[
  {
    "path": ".github/workflows/build.yml",
    "content": "on: #ָ workflow ¼\n  push: #ʱ\n\njobs: #幤\n  build: #Ϊ build\n    runs-on: ubuntu-22.04 #ʹ Ubuntu 22.04 ִ\n    container: #\n      image: archlinux:latest #ʹ Arch Linux \n    steps: #幤еIJ\n      - name: Install dependencies\n        run: |\n          pacman -Syyu --noconfirm \\\n            base-devel \\\n            arm-none-eabi-gcc \\\n            arm-none-eabi-newlib \\\n            git \\\n            python-pip \\\n            python-crcmod \\\n\n      - name: Checkout #ȡ\n        uses: actions/checkout@v4 #ʹ GitHub Actions ṩ checkout \n\n      - name: safe.directory # git  safe.directory \n        run: git config --global --add safe.directory /__w/uv-k5-firmware-custom/uv-k5-firmware-custom\n\n      - name: Make #ִ make \n        run: make full  #Ŀ\n\n      - name: size # firmware С\n        run: arm-none-eabi-size firmware #ʹ arm-none-eabi-size ̼С\n\n      - name: Upload Artifact #ϴ̼ļ\n        uses: actions/upload-artifact@v4 #ʹ GitHub Actions ṩ upload-artifact \n        with:\n          name: firmware # artifact Ϊ firmware\n          path: LOSEHU*.bin #ϴļ·Ϊ LOSEHU*.bin\n\n\n"
  },
  {
    "path": ".github/workflows/docker-image.yml",
    "content": "on: #指定触发 workflow 的事件\r\n  workflow_dispatch: #当代码推送时触发\r\n\r\njobs: #定义工作流程\r\n  build: #工作流名称为 build\r\n    runs-on: ubuntu-22.04 #使用 Ubuntu 22.04 环境执行\r\n    container: #定义容器\r\n      image: archlinux:latest #使用 Arch Linux 镜像\r\n    steps: #定义工作流程中的步骤\r\n      - name: Install dependencies\r\n        run: |\r\n          pacman -Syyu --noconfirm \\\r\n            base-devel \\\r\n            arm-none-eabi-gcc \\\r\n            arm-none-eabi-newlib \\\r\n            git \\\r\n            python-pip \\\r\n            python-crcmod \\\r\n            zip \\\r\n            lftp    \\\r\n            python-requests\r\n\r\n      - name: Checkout #拉取代码\r\n        uses: actions/checkout@v4 #使用 GitHub Actions 提供的 checkout 动作\r\n\r\n      - name: safe.directory #设置 git 的 safe.directory 配置\r\n        run: git config --global --add safe.directory /__w/uv-k5-firmware-custom/uv-k5-firmware-custom\r\n\r\n      - name: Generate #生成固件\r\n        run: |\r\n          python gen.py\r\n          python genJson.py\r\n\r\n      - name: Create ZIP file\r\n        run: |\r\n            mkdir -p output\r\n            zip -j output/losehu.zip ./LOSEHU*.bin ./version.json ./function.json\r\n\r\n      - name: Upload ALL #上传固件文件\r\n        uses: actions/upload-artifact@v4 #使用 GitHub Actions 提供的 upload-artifact 动作\r\n        with:\r\n          name: firmware_all #设置 artifact 名称为 firmware\r\n          path: output/losehu.zip #上传文件路径为 LOSEHU*.bin\r\n\r\n      - name: Upload files\r\n        run: |\r\n          echo \"Uploading LOSEHU.zip to ftp\"\r\n          lftp -u ${{ secrets.FTP_USERNAME }},${{ secrets.FTP_PASSWORD }} ${{ secrets.FTP_SERVER }} <<EOF\r\n          cd losehu\r\n          set ssl:verify-certificate no\r\n          put output/losehu.zip\r\n          bye\r\n          EOF\r\n      \r\n\r\n      - name: Call API\r\n        env:\r\n          API_URL: ${{ secrets.API_URL }}\r\n        run: |\r\n          python -c \"\r\n          import time\r\n          import requests\r\n          import os\r\n          timestamp = int(time.time())\r\n          url = f'{os.getenv('API_URL')}?v={timestamp}'\r\n          response = requests.get(url)\r\n          if response.status_code == 200:\r\n            print('API called successfully')\r\n          else:\r\n            print(f'Failed to call API: {response.status_code}')\"\r\n\r\n"
  },
  {
    "path": ".gitignore",
    "content": "*.d\r\n*.o\r\nfirmware\r\n/firmware.packed.bin\r\n/firmware.bin\r\n/compiled-firmware\r\n"
  },
  {
    "path": ".vscode/launch.json",
    "content": "{\n    // 使用 IntelliSense 了解相关属性。 \n    // 悬停以查看现有属性的描述。\n    // 欲了解更多信息，请访问: https://go.microsoft.com/fwlink/?linkid=830387\n    \n        \"version\": \"0.2.0\",\n        \"configurations\": [\n          {\n            \"name\": \"K5 Debug (ST-Link)\",\n            \"cwd\": \"${workspaceRoot}\",\n            \"executable\": \"${workspaceRoot}/firmware\", \n            \"request\": \"launch\",\n            \"type\": \"cortex-debug\",\n            \"servertype\": \"openocd\",\n            \"serverpath\": \"C:/OpenOCD-20240916-0.12.0/bin/openocd.exe\", //OPENOCD PATH\n            \"device\": \"dp32g030\", \n            \"configFiles\": [\n              \"interface/stlink.cfg\", //OPENOCD STLINK CFG PATH\n              \"${workspaceRoot}/dp32g030.cfg\" \n            ],\n            \"svdFile\": \"${workspaceRoot}/dp32g030.svd\", \n            \"interface\": \"swd\", \n            \"openOCDPreConfigLaunchCommands\": [\n              \"adapter speed 24000\" \n            ]\n          }\n        ]\n      \n}"
  },
  {
    "path": "DP32G030.svd",
    "content": "<?xml version='1.0' encoding='UTF-8'?>\n<device xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" schemaVersion=\"1.1\" xsi:noNamespaceSchemaLocation=\"CMSIS-SVD_Schema_1_1.xsd\">\n\t<name>HM1030</name>\n\t<version>0.1</version>\n\t<description>HM1030 Microcontroller registers</description>\n    \n\t<addressUnitBits>8</addressUnitBits>\n  \n\t<width>32</width>\n\n\t<size>32</size>\n  \n\t<access>read-write</access>\n  \n\t<resetValue>0</resetValue>\n  \n\t<resetMask>0</resetMask>\n\n\t<peripherals>\n  \n\t\t<peripheral>\n\t  \n\t\t\t<name>SYS</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>SYS</groupName>\n\t\t\t<baseAddress>0x40000000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x188</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t  \n\t\t\t<registers>\n  \n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CLK_SEL</name>\n\t\t\t\t\t<description>Clock Select</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000002</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SYS</name>\n\t\t\t\t\t\t<description>系统时钟选择 0 RCHF  1 CLK_DIV </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DIV_CLK</name>\n\t\t\t\t\t\t<description>CLK_DIVx  0 DIV1  1 DIV2  2 DIV4   3 DIV8  4  DIV16   5  DIV32 </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SRC_SEL</name>\n\t\t\t\t\t\t<description>SRC  0 RCHF   1 RCLF   2 XTAH   3 XTAL 4 PLL  </description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PLL_CLK</name>\n\t\t\t\t\t\t<description>SRC  0 RCHF   1 XTAH  </description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADC</name>\n\t\t\t\t\t\t<description>ADC 时钟选择  0 DIV1  1 DIV2  2 DIV4   3 DIV8  </description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t  \n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t  \n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DIV_CLK_GATE</name>\n\t\t\t\t\t<description>Clock DIV Enable</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DIV_EN</name>\n\t\t\t\t\t\t<description>Clock DIV Enable</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DEV_CLK_GATE</name>\n\t\t\t\t\t<description>Clock Enable</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>GPIOA</name>\n\t\t\t\t\t\t<description>GPIOA field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>GPIOB</name>\n\t\t\t\t\t\t<description>GPIOB field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>GPIOC</name>\n\t\t\t\t\t\t<description>GPIOC field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IIC0</name>\n\t\t\t\t\t\t<description>IIC0 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IIC1</name>\n\t\t\t\t\t\t<description>IIC1 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UART0</name>\n\t\t\t\t\t\t<description>UART0 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UART1</name>\n\t\t\t\t\t\t<description>UART1 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UART2</name>\n\t\t\t\t\t\t<description>UART2 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SPI0</name>\n\t\t\t\t\t\t<description>SPI0 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SPI1</name>\n\t\t\t\t\t\t<description>SPI1 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TIMERBASE0</name>\n\t\t\t\t\t\t<description>TIMERBASE0 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TIMERBASE1</name>\n\t\t\t\t\t\t<description>TIMERBASE1 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TIMERBASE2</name>\n\t\t\t\t\t\t<description>TIMERBASE2 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TIMERPLUS0</name>\n\t\t\t\t\t\t<description>TIMERPLUS0 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TIMERPLUS1</name>\n\t\t\t\t\t\t<description>TIMERPLUS1 field</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PWMBASE0</name>\n\t\t\t\t\t\t<description>PWMBASE0 field</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PWMBASE1</name>\n\t\t\t\t\t\t<description>PWMBASE1 field</description>\n\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PWMPLUS0</name>\n\t\t\t\t\t\t<description>PWMPLUS0 field</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PWMPLUS1</name>\n\t\t\t\t\t\t<description>PWMPLUS1 field</description>\n\t\t\t\t\t\t<bitOffset>21</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTC</name>\n\t\t\t\t\t\t<description>RTC field</description>\n\t\t\t\t\t\t<bitOffset>22</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IWDT</name>\n\t\t\t\t\t\t<description>IWDT field</description>\n\t\t\t\t\t\t<bitOffset>23</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>WWDT</name>\n\t\t\t\t\t\t<description>WWDT field</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADC</name>\n\t\t\t\t\t\t<description>ADC field</description>\n\t\t\t\t\t\t<bitOffset>25</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CRC</name>\n\t\t\t\t\t\t<description>CRC field</description>\n\t\t\t\t\t\t<bitOffset>27</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>AES</name>\n\t\t\t\t\t\t<description>AES field</description>\n\t\t\t\t\t\t<bitOffset>28</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>RC_FREQ_DELTA</name>\n\t\t\t\t\t<description>RC Register</description>\n\t\t\t\t\t<addressOffset>0x00000078</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RCLF_DELTA</name>\n\t\t\t\t\t\t<description>RCLF 差值</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>10</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RCLF_SIG</name>\n\t\t\t\t\t\t<description>RCLF 符号    0 - 1 +     </description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RCHF_DELTA</name>\n\t\t\t\t\t\t<description>RCHF 差值  </description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>10</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RCHF_SIG</name>\n\t\t\t\t\t\t<description> RCHF 符号    0 - 1 + </description>\n\t\t\t\t\t\t<bitOffset>31</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>VREF_VOLT_DELTA</name>\n\t\t\t\t\t<description>RC Control Register</description>\n\t\t\t\t\t<addressOffset>0x0000007C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>VREF_DELTA</name>\n\t\t\t\t\t\t<description>VREF 差值    </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>5</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>VREF_SIG</name>\n\t\t\t\t\t\t<description>VREF 符号    0 - 1 +    </description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>CHIP_ID0</name>\n\t\t\t\t\t<description>CHIP ID0 Register</description>\n\t\t\t\t\t<addressOffset>0x00000080</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CHIP_ID0</name>\n\t\t\t\t\t\t<description>CHIP_ID0 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>CHIP_ID1</name>\n\t\t\t\t\t<description>CHIP ID1 Register</description>\n\t\t\t\t\t<addressOffset>0x00000084</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CHIP_ID1</name>\n\t\t\t\t\t\t<description>CHIP_ID1 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>CHIP_ID2</name>\n\t\t\t\t\t<description>CHIP ID2 Register</description>\n\t\t\t\t\t<addressOffset>0x00000088</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CHIP_ID2</name>\n\t\t\t\t\t\t<description>CHIP_ID2 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>CHIP_ID3</name>\n\t\t\t\t\t<description>CHIP ID3 Register</description>\n\t\t\t\t\t<addressOffset>0x0000008C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CHIP_ID3</name>\n\t\t\t\t\t\t<description>CHIP_ID3 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>RCTRIM_EN</name>\n\t\t\t\t\t<description>RCTRIM_EN Register</description>\n\t\t\t\t\t<addressOffset>0x00000100</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TIMP_SRC_XTAH_EN</name>\n\t\t\t\t\t\t<description>TIMP_SRC_XTAH_EN </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TIMP_SRC_RCLF_EN</name>\n\t\t\t\t\t\t<description>TIMP_SRC_RCLF_EN </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>CMP_CFG</name>\n\t\t\t\t\t<description>CMP_CFG Register</description>\n\t\t\t\t\t<addressOffset>0x00000120</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CMP_EN</name>\n\t\t\t\t\t\t<description>CMP_EN </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CMP_INTEN</name>\n\t\t\t\t\t\t<description>CMP_INTEN </description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CMP0_HYS</name>\n\t\t\t\t\t\t<description>CMP0_HYS </description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CMP1_HYS</name>\n\t\t\t\t\t\t<description>CMP1_HYS </description>\n\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CMP2_HYS</name>\n\t\t\t\t\t\t<description>CMP2_HYS </description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>CMP_ST</name>\n\t\t\t\t\t<description>CMP_ST Register</description>\n\t\t\t\t\t<addressOffset>0x00000124</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BIT0_CMP_OUT</name>\n\t\t\t\t\t\t<description>CMP_OUT</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BIT1_CMP_OUT</name>\n\t\t\t\t\t\t<description>CMP_OUT</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BIT2_CMP_OUT</name>\n\t\t\t\t\t\t<description>CMP_OUT</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BIT0_CMP_ORG_OUT</name>\n\t\t\t\t\t\t<description>CMP_OUT</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BIT1_CMP_ORG_OUT</name>\n\t\t\t\t\t\t<description>CMP_OUT</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BIT2_CMP_ORG_OUT</name>\n\t\t\t\t\t\t<description>CMP_OUT</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>COMP0_IF_0TO1</name>\n\t\t\t\t\t\t<description>COMP0_IF</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>COMP0_IF_1TO0</name>\n\t\t\t\t\t\t<description>COMP0_IF</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>COMP1_IF_0TO1</name>\n\t\t\t\t\t\t<description>COMP0_IF</description>\n\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>COMP1_IF_1TO0</name>\n\t\t\t\t\t\t<description>COMP0_IF</description>\n\t\t\t\t\t\t<bitOffset>19</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>COMP2_IF_0TO1</name>\n\t\t\t\t\t\t<description>COMP0_IF</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>COMP2_IF_1TO0</name>\n\t\t\t\t\t\t<description>COMP0_IF</description>\n\t\t\t\t\t\t<bitOffset>21</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\n        \t\t<register>\n\n\t\t\t\t\t<name>OPA_CFG</name>\n\t\t\t\t\t<description>OPA_CFG Register</description>\n\t\t\t\t\t<addressOffset>0x00000140</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CMP_EN_bit0</name>\n\t\t\t\t\t\t<description>CMP_EN </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CMP_EN_bit1</name>\n\t\t\t\t\t\t<description>CMP_EN </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral>\n\t\t\n\t\t\t<name>PMU</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>PMU</groupName>\n\t\t\t<baseAddress>0x40000800</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x00000084</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>LPOW_MD</name>\n\t\t\t\t\t<description>低功耗模式选择寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>STANDBY</name>\n\t\t\t\t\t\t<description>写1，芯片进入STANDBY模式</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLEEP</name>\n\t\t\t\t\t\t<description>写1，芯片进入SLEEP模式</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DEEPSLEEP</name>\n\t\t\t\t\t\t<description>写1，芯片进入DEEPSLEEP模式</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>STOP</name>\n\t\t\t\t\t\t<description>写1，芯片进入STOP模式</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>LPMD_WKEN</name>\n\t\t\t\t\t<description>低功耗唤醒源使能寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTC_ALA_WKEN</name>\n\t\t\t\t\t\t<description>低功耗模式下，RTC_ALA唤醒使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTC_TIM_WKEN</name>\n\t\t\t\t\t\t<description>低功耗模式下，RTC_TIM唤醒使能</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IO_WKEN</name>\n\t\t\t\t\t\t<description>低功耗模式下，IO唤醒使能</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>LPMD_WKST</name>\n\t\t\t\t\t<description>低功耗唤醒源状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTC_ALA_WKST</name>\n\t\t\t\t\t\t<description>低功耗模式下，RTC_ALA唤醒标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTC_TIM_WKST</name>\n\t\t\t\t\t\t<description>低功耗模式下，RTC_TIM唤醒标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IO_WKST</name>\n\t\t\t\t\t\t<description>低功耗模式下，IO唤醒标志</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CHIP_RST_ST</name>\n\t\t\t\t\t<description>低功耗唤醒源标志寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>WWDT_RST_ST</name>\n\t\t\t\t\t\t<description>WWDT复位标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IWDT_RST_ST</name>\n\t\t\t\t\t\t<description>IWDT复位标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>POR_RST_ST</name>\n\t\t\t\t\t\t<description>上电复位标志</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>SRC_CFG</name>\n\t\t\t\t\t<description>时钟控制</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000003</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RCHF_EN</name>\n\t\t\t\t\t\t<description>RCHF 使能控制位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RCHF_FSEL</name>\n\t\t\t\t\t\t<description>RCHF 频率选择控制位</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>XTAH_EN</name>\n\t\t\t\t\t\t<description>XTAH 使能控制位</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>XTAL_EN</name>\n\t\t\t\t\t\t<description>XTAL 使能控制位</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTC_CLK_SEL</name>\n\t\t\t\t\t\t<description>RTC 时钟选择</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TRIM_POW0</name>\n\t\t\t\t\t<description>电压电流TRIM寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_V_HP</name>\n\t\t\t\t\t\t<description>HPBG温度TRIM位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_I_HP</name>\n\t\t\t\t\t\t<description>HPBG电压TRIM位</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_TEMPCO_HPBG</name>\n\t\t\t\t\t\t<description>HPBG电压TRIM位</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TRIM_POW1</name>\n\t\t\t\t\t<description>电压电流TRIM寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000024</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_TEMPCO_LPBG</name>\n\t\t\t\t\t\t<description>LPBG温度trim位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_V_LP</name>\n\t\t\t\t\t\t<description>LPBG电压trim位</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TRIM_POW2</name>\n\t\t\t\t\t<description>TRIM寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000028</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TRIM_POW3</name>\n\t\t\t\t\t<description>TRIM寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000002C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_PD_UVLO</name>\n\t\t\t\t\t\t<description>UVLO33trim位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_LPLDO</name>\n\t\t\t\t\t\t<description>LPLDO电压输出trim位</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_HPLDO_H</name>\n\t\t\t\t\t\t<description>HPLDO电压调整到1.264v</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TRIM_RCHF</name>\n\t\t\t\t\t<description>TRIM寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000030</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_P</name>\n\t\t\t\t\t\t<description>RCHF_P_trim位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_N</name>\n\t\t\t\t\t\t<description>RCHF_N_trim位</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TRIM_RCLF</name>\n\t\t\t\t\t<description>TRIM寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000034</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_FINE</name>\n\t\t\t\t\t\t<description>RCLF_FINE_trim位（精调位）</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_CS</name>\n\t\t\t\t\t\t<description>RCLF_CS_trim位（粗调位）</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TRIM_OPA</name>\n\t\t\t\t\t<description>TRIM寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000038</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OPA0_TRIMN</name>\n\t\t\t\t\t\t<description>OPA0的N端TRIM位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>5</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OPA0_TRIMP</name>\n\t\t\t\t\t\t<description>OPA0的P端TRIM位</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>5</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OPA1_TRIMN</name>\n\t\t\t\t\t\t<description>OPA1的N端TRIM位</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>5</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OPA1_TRIMP</name>\n\t\t\t\t\t\t<description>OPA1的P端TRIM位</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>5</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TRIM_PLL</name>\n\t\t\t\t\t<description>TRIM寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000003C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PLL_R_TRSIM</name>\n\t\t\t\t\t\t<description>PLL的R值TRIM位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TRIM_LOCK</name>\n\t\t\t\t\t<description>TRIM锁定寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000080</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_LOCK</name>\n\t\t\t\t\t\t<description>写入0x55,TRIM_POW和TRIM_RC不能被改写</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIM_UNLOCK</name>\n\t\t\t\t\t\t<description>写入0xAA,TRIM_POW和TRIM_RC能被改写</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\t\t\n\n\t\t<peripheral>\n\t  \n\t\t\t<name>DMA</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>DMA</groupName>\n\t\t\t<baseAddress>0x40001000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x174</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t  \n\t\t\t<registers>\n  \n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CTR</name>\n\t\t\t\t\t<description>DMA使能</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DMA_EN</name>\n\t\t\t\t\t\t<description>DMA使能 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t  \n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_INTEN</name>\n\t\t\t\t\t<description>DMA中断使能</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_TC_INTEN</name>\n\t\t\t\t\t\t<description>通道0传输完成中断使能寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_TC_INTEN</name>\n\t\t\t\t\t\t<description>通道1传输完成中断使能寄存器 </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_TC_INTEN</name>\n\t\t\t\t\t\t<description>通道2传输完成中断使能寄存器 </description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH3_TC_INTEN</name>\n\t\t\t\t\t\t<description>通道3传输完成中断使能寄存器 </description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_THC_INTEN</name>\n\t\t\t\t\t\t<description>通道0传输一半完成中断使能寄存器 </description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_THC_INTEN</name>\n\t\t\t\t\t\t<description>通道1传输一半完成中断使能寄存器 </description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_THC_INTEN</name>\n\t\t\t\t\t\t<description>通道2传输一半完成中断使能寄存器 </description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH3_THC_INTEN</name>\n\t\t\t\t\t\t<description>通道3传输一半完成中断使能寄存器 </description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t  \n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_INTST</name>\n\t\t\t\t\t<description>DMA中断状态</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_TC_INTST</name>\n\t\t\t\t\t\t<description>通道0传输完成中断状态寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_TC_INTST</name>\n\t\t\t\t\t\t<description>通道1传输完成中断状态寄存器 </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_TC_INTST</name>\n\t\t\t\t\t\t<description>通道2传输完成中断状态寄存器 </description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH3_TC_INTST</name>\n\t\t\t\t\t\t<description>通道3传输完成中断状态寄存器 </description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_THC_INTST</name>\n\t\t\t\t\t\t<description>通道0传输一半完成中断状态寄存器 </description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_THC_INTST</name>\n\t\t\t\t\t\t<description>通道1传输一半完成中断状态寄存器 </description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_THC_INTST</name>\n\t\t\t\t\t\t<description>通道2传输一半完成中断状态寄存器 </description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH3_THC_INTST</name>\n\t\t\t\t\t\t<description>通道3传输一半完成中断状态寄存器 </description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t  \n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH0CTR</name>\n\t\t\t\t\t<description>DMA通道0控制寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000100</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EN</name>\n\t\t\t\t\t\t<description>通道使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LENTH</name>\n\t\t\t\t\t\t<description>传输计数</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOOP</name>\n\t\t\t\t\t\t<description>循环方式</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PRI</name>\n\t\t\t\t\t\t<description>通道优先级</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SWRED</name>\n\t\t\t\t\t\t<description>软件请求开始传输</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH0MOD</name>\n\t\t\t\t\t<description>DMA通道0模式寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000104</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t 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</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSSEL</name>\n\t\t\t\t\t\t<description>MS测外设选择</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDADDMOD</name>\n\t\t\t\t\t\t<description>MD测地址变化方式选择</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDSIZE</name>\n\t\t\t\t\t\t<description>MD测总线传输宽度 </description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDSEL</name>\n\t\t\t\t\t\t<description>MD测外设选择</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH0MSADDR</name>\n\t\t\t\t\t<description>DMA通道0源地址寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000108</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  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\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CUR_LENTH</name>\n\t\t\t\t\t\t<description>当前已传输个数</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH1CTR</name>\n\t\t\t\t\t<description>DMA通道1控制寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000120</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EN</name>\n\t\t\t\t\t\t<description>通道使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LENTH</name>\n\t\t\t\t\t\t<description>传输计数</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOOP</name>\n\t\t\t\t\t\t<description>循环方式</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PRI</name>\n\t\t\t\t\t\t<description>通道优先级</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SWRED</name>\n\t\t\t\t\t\t<description>软件请求开始传输</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH1MOD</name>\n\t\t\t\t\t<description>DMA通道1模式寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000124</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSADDMOD</name>\n\t\t\t\t\t\t<description>MS测地址变化方式选择 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSSIZE</name>\n\t\t\t\t\t\t<description>MS测总线传输宽度 </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSSEL</name>\n\t\t\t\t\t\t<description>MS测外设选择</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDADDMOD</name>\n\t\t\t\t\t\t<description>MD测地址变化方式选择</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDSIZE</name>\n\t\t\t\t\t\t<description>MD测总线传输宽度 </description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDSEL</name>\n\t\t\t\t\t\t<description>MD测外设选择</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH1MSADDR</name>\n\t\t\t\t\t<description>DMA通道1源地址寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000128</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSADDR</name>\n\t\t\t\t\t\t<description>MS侧地址(源地址)</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH1MDADDR</name>\n\t\t\t\t\t<description>DMA通道1目标地址寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000012C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDADDR</name>\n\t\t\t\t\t\t<description>MD侧地址(目标地址)</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH1ST</name>\n\t\t\t\t\t<description>DMA通道1状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000130</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CUR_LENTH</name>\n\t\t\t\t\t\t<description>当前已传输个数</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH2CTR</name>\n\t\t\t\t\t<description>DMA通道2控制寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000140</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EN</name>\n\t\t\t\t\t\t<description>通道使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LENTH</name>\n\t\t\t\t\t\t<description>传输计数</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOOP</name>\n\t\t\t\t\t\t<description>循环方式</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PRI</name>\n\t\t\t\t\t\t<description>通道优先级</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SWRED</name>\n\t\t\t\t\t\t<description>软件请求开始传输</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH2MOD</name>\n\t\t\t\t\t<description>DMA通道2模式寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000144</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSADDMOD</name>\n\t\t\t\t\t\t<description>MS测地址变化方式选择 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSSIZE</name>\n\t\t\t\t\t\t<description>MS测总线传输宽度 </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSSEL</name>\n\t\t\t\t\t\t<description>MS测外设选择</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDADDMOD</name>\n\t\t\t\t\t\t<description>MD测地址变化方式选择</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDSIZE</name>\n\t\t\t\t\t\t<description>MD测总线传输宽度 </description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDSEL</name>\n\t\t\t\t\t\t<description>MD测外设选择</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH2MSADDR</name>\n\t\t\t\t\t<description>DMA通道2源地址寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000148</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSADDR</name>\n\t\t\t\t\t\t<description>MS侧地址(源地址)</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH2MDADDR</name>\n\t\t\t\t\t<description>DMA通道2目标地址寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000014C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDADDR</name>\n\t\t\t\t\t\t<description>MD侧地址(目标地址)</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH2ST</name>\n\t\t\t\t\t<description>DMA通道2状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000150</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CUR_LENTH</name>\n\t\t\t\t\t\t<description>当前已传输个数</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH3CTR</name>\n\t\t\t\t\t<description>DMA通道3控制寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000160</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EN</name>\n\t\t\t\t\t\t<description>通道使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LENTH</name>\n\t\t\t\t\t\t<description>传输计数</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOOP</name>\n\t\t\t\t\t\t<description>循环方式</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PRI</name>\n\t\t\t\t\t\t<description>通道优先级</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SWRED</name>\n\t\t\t\t\t\t<description>软件请求开始传输</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH3MOD</name>\n\t\t\t\t\t<description>DMA通道3模式寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000164</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSADDMOD</name>\n\t\t\t\t\t\t<description>MS测地址变化方式选择 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSSIZE</name>\n\t\t\t\t\t\t<description>MS测总线传输宽度 </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSSEL</name>\n\t\t\t\t\t\t<description>MS测外设选择</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDADDMOD</name>\n\t\t\t\t\t\t<description>MD测地址变化方式选择</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDSIZE</name>\n\t\t\t\t\t\t<description>MD测总线传输宽度 </description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDSEL</name>\n\t\t\t\t\t\t<description>MD测外设选择</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH3MSADDR</name>\n\t\t\t\t\t<description>DMA通道3源地址寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000168</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSADDR</name>\n\t\t\t\t\t\t<description>MS侧地址(源地址)</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH3MDADDR</name>\n\t\t\t\t\t<description>DMA通道3目标地址寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000016C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MDADDR</name>\n\t\t\t\t\t\t<description>MD侧地址(目标地址)</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DMA_CH3ST</name>\n\t\t\t\t\t<description>DMA通道3状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000170</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CUR_LENTH</name>\n\t\t\t\t\t\t<description>当前已传输个数</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral>\n\t  \n\t\t\t<name>CRC</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>CRC</groupName>\n\t\t\t<baseAddress>0x40003000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x10</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t  \n\t\t\t<registers>\n  \n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CRC_CR</name>\n\t\t\t\t\t<description>CRC控制</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CRC_EN</name>\n\t\t\t\t\t\t<description>CRC使能 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>INPUT_REV</name>\n\t\t\t\t\t\t<description>输入数据是否取反 </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>INPUT_INV</name>\n\t\t\t\t\t\t<description>输入数据翻转寄存器 </description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OUTPUT_REV</name>\n\t\t\t\t\t\t<description>输出数据是否取反 </description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OUTPUT_INV</name>\n\t\t\t\t\t\t<description>输出数据翻转寄存器 </description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA_WIDTH</name>\n\t\t\t\t\t\t<description>CRC输入数据有效位数寄存器 </description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CRC_SEL</name>\n\t\t\t\t\t\t<description>CRC算法选择寄存器 </description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t  \n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CRC_IV</name>\n\t\t\t\t\t<description>CRC初值</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CRC_IV</name>\n\t\t\t\t\t\t<description>CRC初值 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t  \n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CRC_DATAIN</name>\n\t\t\t\t\t<description>CRC输入数据寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CRC_DATAIN</name>\n\t\t\t\t\t\t<description>CRC输入数据寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t  \n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CRC_DATAOUT</name>\n\t\t\t\t\t<description>CRC输出数据寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t  \n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CRC_DATAOUT</name>\n\t\t\t\t\t\t<description>CRC输出数据寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t  \n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n        \n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral>\n\t\t\n\t\t\t<name>GPIOA</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>GPIO</groupName>\n\t\t\t<baseAddress>0x40060000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x00000024</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t<description>DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DIR</name>\n\t\t\t\t\t<description>0 输入\t1 输出</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTLVLTRG</name>\n\t\t\t\t\t<description>Interrupt Level Trigger  1 电平触发中断\t0 边沿触发中断</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTBE</name>\n\t\t\t\t\t<description>Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择</description>\n\t\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTRISEEN</name>\n\t\t\t\t\t<description>Interrupt Rise Edge Enable   1 上升沿/高电平触发中断\t0 下降沿/低电平触发中断</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTEN</name>\n\t\t\t\t\t<description>1 中断使能\t0 中断禁止</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTRAWSTAT</name>\n\t\t\t\t\t<description>中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件\t0 没有检测到中断触发条件</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTSTAT</name>\n\t\t\t\t\t<description>INTSTAT.PIN0 = INTRAWSTAT.PIN0 and INTEN.PIN0  </description>\n\t\t\t\t\t<addressOffset>0x0000001C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTCLR</name>\n\t\t\t\t\t<description>写1清除中断标志，只对边沿触发中断有用</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t</registers>\n\t\t\t\t\t\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral derivedFrom=\"GPIOA\">\n\t\t\n\t\t\t<name>GPIOB</name>\n\t\t\t<baseAddress>0x40060800</baseAddress>\n\n\t\t</peripheral>\n\n\n\t\t<peripheral>\n\t\t\n\t\t\t<name>GPIOC</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>GPIO</groupName>\n\t\t\t<baseAddress>0x40061000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x00000024</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t<description>DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DIR</name>\n\t\t\t\t\t<description>0 输入\t1 输出</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTLVLTRG</name>\n\t\t\t\t\t<description>Interrupt Level Trigger  1 电平触发中断\t0 边沿触发中断</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTBE</name>\n\t\t\t\t\t<description>Both Edge，当INTLVLTRG设为边沿触发中断时，此位置1表示上升沿和下降沿都触发中断，置0时触发边沿由INTRISEEN选择</description>\n\t\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTRISEEN</name>\n\t\t\t\t\t<description>Interrupt Rise Edge Enable   1 上升沿/高电平触发中断\t0 下降沿/低电平触发中断</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTEN</name>\n\t\t\t\t\t<description>1 中断使能\t0 中断禁止</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTRAWSTAT</name>\n\t\t\t\t\t<description>中断检测单元是否检测到了触发中断的条件 1 检测到了中断触发条件\t0 没有检测到中断触发条件</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTSTAT</name>\n\t\t\t\t\t<description>INTSTAT.PIN0 = INTRAWSTAT.PIN0 and INTEN.PIN0  </description>\n\t\t\t\t\t<addressOffset>0x0000001C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>INTCLR</name>\n\t\t\t\t\t<description>写1清除中断标志，只对边沿触发中断有用</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t</registers>\n\t\t\t\t\t\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral>\n\t\t\n\t\t\t<name>TIMERBASE0</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>TIMERBASE</groupName>\n\t\t\t<baseAddress>0x40064000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x000000038</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TIMERBASE_EN</name>\n\t\t\t\t\t<description>TIMERBASE使能</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_EN</name>\n\t\t\t\t\t\t<description>TIMERBASE_LOW定时器使能寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_EN</name>\n\t\t\t\t\t\t<description>TIMERBASE_HIGH定时器使能寄存器</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TIMERBASE_DIV</name>\n\t\t\t\t\t<description>TIMERBASE预分频</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DIV</name>\n\t\t\t\t\t\t<description>TIMERBASE计数时钟预分频寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TIMERBASE_IE</name>\n\t\t\t\t\t<description>TIMERBASE定时器中断使能</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_IE</name>\n\t\t\t\t\t\t<description>TIMERBASE_LOW定时器中断使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_IE</name>\n\t\t\t\t\t\t<description>TIMERBASE_HIGH定时器中断使能</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TIMERBASE_IF</name>\n\t\t\t\t\t<description>TIMERBASE定时器中断状态</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_IF</name>\n\t\t\t\t\t\t<description>TIMERBASE_LOW定时器中断状态</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_IF</name>\n\t\t\t\t\t\t<description>TIMERBASE_HIGH定时器中断状态</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>HIGH_LOAD</name>\n\t\t\t\t\t<description>TIMERBASE_HIGH定时器目标配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOAD</name>\n\t\t\t\t\t\t<description>TIMERBASE_HIGH定时器目标配置寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>HIGH_CNT</name>\n\t\t\t\t\t<description>TIMERBASE_HIGH定时器当前计数值</description>\n\t\t\t\t\t<addressOffset>0x00000024</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CNT</name>\n\t\t\t\t\t\t<description>TIMERBASE_HIGH定时器当前计数值</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>LOW_LOAD</name>\n\t\t\t\t\t<description>TIMERBASE_LOW定时器目标配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000030</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOAD</name>\n\t\t\t\t\t\t<description>TIMERBASE_LOW定时器目标配置寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>LOW_CNT</name>\n\t\t\t\t\t<description>TIMERBASE_LOW定时器当前计数值</description>\n\t\t\t\t\t<addressOffset>0x00000034</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CNT</name>\n\t\t\t\t\t\t<description>TIMERBASE_LOW定时器当前计数值</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t</registers>\n\t\t\t\t\t\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral derivedFrom=\"TIMERBASE0\">\n\t\t\n\t\t\t<name>TIMERBASE1</name>\n\t\t\t<baseAddress>0x40064800</baseAddress>\n\n\t\t</peripheral>\n\n\t\t<peripheral derivedFrom=\"TIMERBASE0\">\n\t\t\n\t\t\t<name>TIMERBASE2</name>\n\t\t\t<baseAddress>0x40065000</baseAddress>\n\n\t\t</peripheral>\n\n\t\t\n\n\t\t<peripheral>\n\t\t\n\t\t\t<name>TIMERPLUS0</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>TIMERPLUS</groupName>\n\t\t\t<baseAddress>0x40067000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x000000044</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TIMERPLUS_EN</name>\n\t\t\t\t\t<description>TIMERPLUS使能</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_EN</name>\n\t\t\t\t\t\t<description>低16bit定时器使能寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_EN</name>\n\t\t\t\t\t\t<description>高16bit定时器使能寄存器</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TIMERPLUS_DIV</name>\n\t\t\t\t\t<description>TIMERPLUS预分频</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DIV</name>\n\t\t\t\t\t\t<description>计数时钟预分频寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TIMERPLUS_CTR</name>\n\t\t\t\t\t<description>TIMERPLUS配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_MODE</name>\n\t\t\t\t\t\t<description>TIMER_LOW工作模式寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_CLKSEL</name>\n\t\t\t\t\t\t<description>TIMER_LOW计数时钟源选择</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_EXT_SEL</name>\n\t\t\t\t\t\t<description>TIMER_LOW计数模式或输入捕获模式输入信号选择</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_EXT_EDGE</name>\n\t\t\t\t\t\t<description>TIMER_LOW计数模式或输入捕获模式输入信号有效沿选择</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_PO_MD</name>\n\t\t\t\t\t\t<description>TIMER_LOW周期脉冲输出使能</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_DMA_EN</name>\n\t\t\t\t\t\t<description>DMA读取TIMER_LOW捕获值使能</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_MODE</name>\n\t\t\t\t\t\t<description>TIMER_HIGH工作模式寄存器</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_CLKSEL</name>\n\t\t\t\t\t\t<description>TIMER_HIGH计数时钟源选择</description>\n\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_EXT_SEL</name>\n\t\t\t\t\t\t<description>TIMER_HIGH计数模式或输入捕获模式输入信号选择</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_EXT_EDGE</name>\n\t\t\t\t\t\t<description>TIMER_HIGH计数模式或输入捕获模式输入信号有效沿选择</description>\n\t\t\t\t\t\t<bitOffset>21</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_PO_MD</name>\n\t\t\t\t\t\t<description>TIMER_HIGH周期脉冲输出使能</description>\n\t\t\t\t\t\t<bitOffset>23</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_DMA_EN</name>\n\t\t\t\t\t\t<description>DMA读取TIMER_HIGH捕获值使能</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TIMERPLUS_IE</name>\n\t\t\t\t\t<description>TIMERPLUS定时器中断使能</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_TO_IF</name>\n\t\t\t\t\t\t<description>TIMERPLUS_LOW达到目标值中断使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_PR_IE</name>\n\t\t\t\t\t\t<description>TIMERPLUS_LOW输入脉冲上升沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_PF_IE</name>\n\t\t\t\t\t\t<description>TIMERPLUS_LOW输入脉冲下降沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_TO_IE</name>\n\t\t\t\t\t\t<description>TIMERPLUS_HIGH达到目标值中断使能</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_PR_IE</name>\n\t\t\t\t\t\t<description>TIMERPLUS_HIGH输入脉冲上升沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_PF_IE</name>\n\t\t\t\t\t\t<description>TIMERPLUS_HIGH输入脉冲下降沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL0_R_IE</name>\n\t\t\t\t\t\t<description>HALL0上升沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL0_F_IE</name>\n\t\t\t\t\t\t<description>HALL0下降沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL1_R_IE</name>\n\t\t\t\t\t\t<description>HALL1上升沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL1_F_IE</name>\n\t\t\t\t\t\t<description>HALL1下降沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>19</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL2_R_IE</name>\n\t\t\t\t\t\t<description>HALL2上升沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL2_F_IE</name>\n\t\t\t\t\t\t<description>HALL2下降沿中断使能</description>\n\t\t\t\t\t\t<bitOffset>21</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TIMERPLUS_IF</name>\n\t\t\t\t\t<description>TIMERPLUS定时器中断状态</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_TO_IF</name>\n\t\t\t\t\t\t<description>TIMERPLUS_LOW达到目标值中断状态</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_PR_IF</name>\n\t\t\t\t\t\t<description>TIMERPLUS_LOW输入脉冲上升沿中断状态</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LOW_PF_IF</name>\n\t\t\t\t\t\t<description>TIMERPLUS_LOW输入脉冲下降沿中断状态</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_TO_IF</name>\n\t\t\t\t\t\t<description>TIMERPLUS_HIGH达到目标值中断状态</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_PR_IF</name>\n\t\t\t\t\t\t<description>TIMERPLUS_HIGH输入脉冲上升沿中断状态</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HIGH_PF_IF</name>\n\t\t\t\t\t\t<description>TIMERPLUS_HIGH输入脉冲下降沿中断状态</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL0_R_IF</name>\n\t\t\t\t\t\t<description>HALL0上升沿中断状态</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL0_F_IF</name>\n\t\t\t\t\t\t<description>HALL0下降沿中断状态</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL1_R_IF</name>\n\t\t\t\t\t\t<description>HALL1上升沿中断状态</description>\n\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL1_F_IF</name>\n\t\t\t\t\t\t<description>HALL1下降沿中断状态</description>\n\t\t\t\t\t\t<bitOffset>19</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL2_R_IF</name>\n\t\t\t\t\t\t<description>HALL2上升沿中断状态</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HALL2_F_IF</name>\n\t\t\t\t\t\t<description>HALL2 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平</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t</registers>\n\t\t\t\t\t\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral derivedFrom=\"TIMERPLUS0\">\n\t\t\n\t\t\t<name>TIMERPLUS1</name>\n\t\t\t<baseAddress>0x40067800</baseAddress>\n\n\t\t</peripheral>\n\n\t\t<peripheral>\n\t  \n\t\t\t<name>RTC</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>RTC</groupName>\n\t\t\t<baseAddress>0x40069000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x30</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t  \n\t\t\t<registers>\n  \n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CFG</name>\n\t\t\t\t\t<description>配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTC_EN</name>\n\t\t\t\t\t\t<description>RTC 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\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IE</name>\n\t\t\t\t\t<description>中断使能寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SEC_IE</name>\n\t\t\t\t\t\t<description>秒中断使能位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MIN_IE</name>\n\t\t\t\t\t\t<description>分钟中断使能位</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HOUR_IE</name>\n\t\t\t\t\t\t<description>小时中断使能位</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATE_IE</name>\n\t\t\t\t\t\t<description>日中断使能位</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ALM_IE</name>\n\t\t\t\t\t\t<description>闹钟中断使能位</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MS_IE</name>\n\t\t\t\t\t\t<description>1/2秒中断使能位</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IF</name>\n\t\t\t\t\t<description>状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SEC_IF</name>\n\t\t\t\t\t\t<description>秒中断响应</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MIN_IF</name>\n\t\t\t\t\t\t<description>分钟中断响应</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HOUR_IF</name>\n\t\t\t\t\t\t<description>小时中断响应</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATE_IF</name>\n\t\t\t\t\t\t<description>日中断响应</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ALM_IF</name>\n\t\t\t\t\t\t<description>闹钟中断响应</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MS_IF</name>\n\t\t\t\t\t\t<description>1/2秒中断响应</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TIME_ERR</name>\n\t\t\t\t\t\t<description>时间设定有效标志位</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ALM_ERR</name>\n\t\t\t\t\t\t<description>闹钟设定有效标志位</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PRE</name>\n\t\t\t\t\t<description>预分频寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00007fff</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ROUND</name>\n\t\t\t\t\t\t<description>预分频整数部分</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>20</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DECIMAL</name>\n\t\t\t\t\t\t<description>预分频小数部分</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PERIOD</name>\n\t\t\t\t\t\t<description>小数计算周期选择</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TR</name>\n\t\t\t\t\t<description>时间寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SEC</name>\n\t\t\t\t\t\t<description>设定时间所属秒钟的个位数</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SEC_DEC</name>\n\t\t\t\t\t\t<description>设定时间所属秒钟的十位数</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MIN</name>\n\t\t\t\t\t\t<description>设定时间所属分钟的个位数</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MIN_DEC</name>\n\t\t\t\t\t\t<description>设定时间所属分钟的十位数</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HOUR</name>\n\t\t\t\t\t\t<description>设定时间所属小时的个位数</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HOUR_DEC</name>\n\t\t\t\t\t\t<description>设定时间所属小时的十位数</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>WEEK</name>\n\t\t\t\t\t\t<description>设定时间所属星期</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DR</name>\n\t\t\t\t\t<description>日期寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000101</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATE</name>\n\t\t\t\t\t\t<description>设定时间所属日期的个位数</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATE_DEC</name>\n\t\t\t\t\t\t<description>设定时间所属日期的十位数</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MONTH</name>\n\t\t\t\t\t\t<description>设定时间所属月份的个位数</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MONTH_DEC</name>\n\t\t\t\t\t\t<description>设定时间所属月份的十位数</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>YEAR</name>\n\t\t\t\t\t\t<description>设定时间所属月份的个位数</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>YEAR_DEC</name>\n\t\t\t\t\t\t<description>设定时间所属月份的十位数</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>AR</name>\n\t\t\t\t\t<description>闹钟寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000001C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SEC</name>\n\t\t\t\t\t\t<description>闹钟时间所属秒钟的个位数</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SEC_DEC</name>\n\t\t\t\t\t\t<description>闹钟时间所属秒钟的十位数</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MIN</name>\n\t\t\t\t\t\t<description>闹钟时间所属分钟的个位数</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MIN_DEC</name>\n\t\t\t\t\t\t<description>闹钟时间所属分钟的十位数</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HOUR</name>\n\t\t\t\t\t\t<description>闹钟时间所属小时的个位数</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HOUR_DEC</name>\n\t\t\t\t\t\t<description>闹钟时间所属小时的十位数</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>WEEKDAY</name>\n\t\t\t\t\t\t<description>闹钟时间所属星期</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>7</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TSTR</name>\n\t\t\t\t\t<description>当前时间寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SEC</name>\n\t\t\t\t\t\t<description>当前时间所属秒钟的个位数</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SEC_DEC</name>\n\t\t\t\t\t\t<description>当前时间所属秒钟的十位数</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MIN</name>\n\t\t\t\t\t\t<description>当前时间所属分钟的个位数</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MIN_DEC</name>\n\t\t\t\t\t\t<description>当前时间所属分钟的十位数</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HOUR</name>\n\t\t\t\t\t\t<description>当前时间所属小时的个位数</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HOUR_DEC</name>\n\t\t\t\t\t\t<description>当前时间所属小时的十位数</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>WEEKDAY</name>\n\t\t\t\t\t\t<description>当前时间所属星期</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TSDR</name>\n\t\t\t\t\t<description>当前日期寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000024</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000101</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATE</name>\n\t\t\t\t\t\t<description>当前时间所属的日期的个位数e</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATE_DEC</name>\n\t\t\t\t\t\t<description>当前时间所属的日期的十位数</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MONTH</name>\n\t\t\t\t\t\t<description>当前时间所属的月份的个位数</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MONTH_DEC</name>\n\t\t\t\t\t\t<description>当前时间所属的月份的十位数</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>YEAR</name>\n\t\t\t\t\t\t<description>当前时间所属的纪年的个位数</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>YEAR_DEC</name>\n\t\t\t\t\t\t<description>当前时间所属的纪年的十位数</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CNT</name>\n\t\t\t\t\t<description>秒标当前计数值</description>\n\t\t\t\t\t<addressOffset>0x00000028</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x0007FFFF</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CNT_15</name>\n\t\t\t\t\t\t<description>20bit计数位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>20</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>VALID</name>\n\t\t\t\t\t<description>当前时间有效标志寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000002C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CUR_VALID</name>\n\t\t\t\t\t\t<description>当前时间有效标志位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>  \n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t</register>\n\t\t\t\t\t\t\t\t\n        \n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\n\n\t\t<peripheral>\n\t\t\n\t\t\t<name>IWDT</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>IWDT</groupName>\n\t\t\t<baseAddress>0x4006A000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x00000014</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>LOAD</name>\n\t\t\t\t\t<description>初值寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IWDTLOAD</name>\n\t\t\t\t\t\t<description>IWDT计数器的初始值配置寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>20</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>VALUE</name>\n\t\t\t\t\t<description>VALUE register</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CTRL</name>\n\t\t\t\t\t<description>CTRL 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field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>FEED</name>\n\t\t\t\t\t<description>写0x55喂狗</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>FEED</name>\n\t\t\t\t\t\t<description>FEED field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral>\n\t\t\n\t\t\t<name>WWDT</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>WWDT</groupName>\n\t\t\t<baseAddress>0x4006A800</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x00000014</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>LOAD</name>\n\t\t\t\t\t<description>初值寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>INT_LOAD</name>\n\t\t\t\t\t\t<description>窗口中断比较值寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>7</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RST_LOAD</name>\n\t\t\t\t\t\t<description>窗口复位比较值寄存器</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>6</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>VALUE</name>\n\t\t\t\t\t<description>VALUE register</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>VALUE</name>\n\t\t\t\t\t\t<description>计数值寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>7</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CTRL</name>\n\t\t\t\t\t<description>CTRL register</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EN</name>\n\t\t\t\t\t\t<description>启动位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>INTEN</name>\n\t\t\t\t\t\t<description>中断使能位</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PRERSTINTEN</name>\n\t\t\t\t\t\t<description>预复位中断使能位</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IF</name>\n\t\t\t\t\t<description>IWDT状态位</description>\n\t\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>WININT</name>\n\t\t\t\t\t\t<description>窗口中断标志位</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PRERSTINT</name>\n\t\t\t\t\t\t<description>预复位中断标志位</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>FEED</name>\n\t\t\t\t\t<description>写0x55喂狗</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>FEED</name>\n\t\t\t\t\t\t<description>FEED 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00000C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RDR</name>\n\t\t\t\t\t\t<description>读数据寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>9</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\n\t\t\t\t\t<name>IE</name>\n\t\t\t\t\t<description>中断使能寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXDONE</name>\n\t\t\t\t\t\t<description>全部数据发送完成中断使能</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PARITYE</name>\n\t\t\t\t\t\t<description>接收数据出现奇偶校验错中断使能</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>STOPE</name>\n\t\t\t\t\t\t<description>接收数据出现停止位错误中断使能</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXTO</name>\n\t\t\t\t\t\t<description>接收超时中断使能</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO</name>\n\t\t\t\t\t\t<description>接收FIFO中接收的数据达到设定水位中断使能</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXFIFO</name>\n\t\t\t\t\t\t<description>发送FIFO中保存的数据达到设定水位中断使能</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_OVF</name>\n\t\t\t\t\t\t<description>接收FIFO溢出中断使能</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ABRD_OVF</name>\n\t\t\t\t\t\t<description>自动波特率检测功能计数器溢出中断使能</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\n\t\t\t\t\t<name>IF</name>\n\t\t\t\t\t<description>中断状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXDONE</name>\n\t\t\t\t\t\t<description>全部数据发送完成</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PARITYE</name>\n\t\t\t\t\t\t<description>接收数据出现奇偶校验错</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>STOPE</name>\n\t\t\t\t\t\t<description>接收数据出现停止位错误</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXTO</name>\n\t\t\t\t\t\t<description>接收超时标志</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO</name>\n\t\t\t\t\t\t<description>接收FIFO中接收到的数据达到设定水位</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXFIFO</name>\n\t\t\t\t\t\t<description>发送FIFO中保存的数据达到设定水位</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_OVF</name>\n\t\t\t\t\t\t<description>接收FIFO溢出标志</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ABRD_OVF</name>\n\t\t\t\t\t\t<description>自动波特率检测功能计数器溢出标志</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_EMPTY</name>\n\t\t\t\t\t\t<description>接收FIFO空标志</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_FULL</name>\n\t\t\t\t\t\t<description>接收FIFO满标志</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_HFULL</name>\n\t\t\t\t\t\t<description>接收FIFO半满标志</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXFIFO_EMPTY</name>\n\t\t\t\t\t\t<description>发送FIFO空标志</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXFIFO_FULL</name>\n\t\t\t\t\t\t<description>发送FIFO满标志</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXFIFO_HFULL</name>\n\t\t\t\t\t\t<description>发送FIFO半满标志</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXBUSY</name>\n\t\t\t\t\t\t<description>数据发送忙标志</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RF_LEVEL</name>\n\t\t\t\t\t\t<description>接收FIFO水位标志信号</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TF_LEVEL</name>\n\t\t\t\t\t\t<description>发送FIFO水位标志信号</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\n\t\t\t\t\t<name>FIFO</name>\n\t\t\t\t\t<description>FIFO控制寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RF_LEVEL</name>\n\t\t\t\t\t\t<description>用于RXFIFO产生中断的水位设置</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TF_LEVEL</name>\n\t\t\t\t\t\t<description>用于TXFIFO产生中断的水位设置</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RF_CLR</name>\n\t\t\t\t\t\t<description>RXFIFO清除使能</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TF_CLR</name>\n\t\t\t\t\t\t<description>TXFIFO清除使能</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\n\t\t\t\t\t<name>FC</name>\n\t\t\t\t\t<description>流控制配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000001C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CTSEN</name>\n\t\t\t\t\t\t<description>CTS流控使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTSEN</name>\n\t\t\t\t\t\t<description>RTS流控使能</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CTSPOL</name>\n\t\t\t\t\t\t<description>CTS信号极性配置</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTSPOL</name>\n\t\t\t\t\t\t<description>RTS信号极性配置</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CTS_SIGNAL</name>\n\t\t\t\t\t\t<description>表示线上CTS状态</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RTS_SIGNAL</name>\n\t\t\t\t\t\t<description>表示线上RTS状态</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\n\t\t\t\t\t<name>RXTO</name>\n\t\t\t\t\t<description>接收超时配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXTO</name>\n\t\t\t\t\t\t<description>接收数据超时触发比较值</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\n\t\t\t\t</register>\n\n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral derivedFrom=\"UART0\">\n\t\t\n\t\t\t<name>UART1</name>\n\t\t\t<baseAddress>0x4006B800</baseAddress>\n\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral derivedFrom=\"UART0\">\n\t\t\n\t\t\t<name>UART2</name>\n\t\t\t<baseAddress>0x4006C000</baseAddress>\n\t\t\t\n\t\t</peripheral>\n\n\n\t\t<peripheral>\n\n\t\t\t<name>FLASH</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>FLASH</groupName>\n\t\t\t<baseAddress>0x4006F000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t\t<offset>0x00000000</offset>\n\t\t\t\t<size>0x0000002C</size>\n\t\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\n\t\t\t<registers>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>CFG</name>\n\t\t\t\t\t<description>CFG register</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>READ_MD</name>\n\t\t\t\t\t\t<description>读速率模式选择</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NVR_SEL</name>\n\t\t\t\t\t\t<description>NVR区选择</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MODE</name>\n\t\t\t\t\t\t<description>操作模式配置寄存器</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DEEP_PD</name>\n\t\t\t\t\t\t<description>配置FLASH进入deep_power_down模式</description>\n\t\t\t\t\t\t<bitOffset>31</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>ADDR</name>\n\t\t\t\t\t<description>地址寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>ADDR</name>\n\t\t\t\t\t\t\t<description>18位地址</description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>14</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>WDATA</name>\n\t\t\t\t\t<description>写数据寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>START</name>\n\t\t\t\t\t<description>操作启动控制位</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>START</name>\n\t\t\t\t\t\t\t<description>操作启动控制位</description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>SPIF_ST</name>\n\t\t\t\t\t<description>状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>INIT_BUSY</name>\n\t\t\t\t\t\t\t<description>FLASH初始化忙标志</description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>BUSY</name>\n\t\t\t\t\t\t\t<description>控制器忙标志</description>\n\t\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>PROG_BUF_EMPTY</name>\n\t\t\t\t\t\t\t<description>编程数据缓存寄存器空状态标志</description>\n\t\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>LOCK</name>\n\t\t\t\t\t<description>操作锁控制</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>LOCK</name>\n\t\t\t\t\t\t\t<description>操作锁控制</description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>UNLOCK</name>\n\t\t\t\t\t<description>操作解锁控制</description>\n\t\t\t\t\t<addressOffset>0x0000001C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>UNLOCK</name>\n\t\t\t\t\t\t\t<description>操作解锁控制</description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>MASK</name>\n\t\t\t\t\t<description>MASK选择</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>SEL</name>\n\t\t\t\t\t\t\t<description>选择</description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>LOCK</name>\n\t\t\t\t\t\t\t<description>选择锁定控制</description>\n\t\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>ERASETIME</name>\n\t\t\t\t\t<description>时间寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000024</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x7532A31B</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>TERASE</name>\n\t\t\t\t\t\t\t<description>FLASH扇区擦（全片擦）时，TERASE（TSCE）时间寄存器</description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>19</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>TRCV</name>\n\t\t\t\t\t\t\t<description>FLASH扇区擦（全片擦）时，TRCV时间寄存器</description>\n\t\t\t\t\t\t\t<bitOffset>19</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PROGTIME</name>\n\t\t\t\t\t<description>时间寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000028</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x001F4360</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>TPROG</name>\n\t\t\t\t\t\t\t<description>FLASH编程操作时的TPROG时间控制寄存器</description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>11</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>TPGS</name>\n\t\t\t\t\t\t\t<description>FLASH编程操作时的TPGS时间控制寄存器</description>\n\t\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>11</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t</registers>\n\n    \t</peripheral>\n\n\n\t\t<peripheral>\n\t\t\n\t\t\t<name>PORT</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>PORT</groupName>\n\t\t\t<baseAddress>0x400B0000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x00000070C</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTA0_SEL</name>\n\t\t\t\t\t<description>PORTA 功能选择寄存器 0</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>28</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTA1_SEL</name>\n\t\t\t\t\t<description>PORTA 功能选择寄存器 1</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>28</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTB_SEL0</name>\n\t\t\t\t\t<description>PORTB 功能选择寄存器 0</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>28</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTB_SEL1</name>\n\t\t\t\t\t<description>PORTB 功能选择寄存器 1</description>\n\t\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x01001000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>28</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTC_SEL0</name>\n\t\t\t\t\t<description>PORTC 功能选择寄存器 0</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>28</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTA_IE</name>\n\t\t\t\t\t<description>PORTA Input Enable register   0 Input Disable  1  Input Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000100</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTB_IE</name>\n\t\t\t\t\t<description>PORTB Input Enable register   0 Input Disable  1  Input Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000104</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTC_IE</name>\n\t\t\t\t\t<description>PORTC Input Enable register   0 Input Disable  1  Input Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000108</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTA_PU</name>\n\t\t\t\t\t<description>Pull_Up Enable register   0 Pull_Up Disable  1  Pull_Up Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000200</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTB_PU</name>\n\t\t\t\t\t<description>Pull_Up Enable register   0 Pull_Up Disable  1  Pull_Up Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000204</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTC_PU</name>\n\t\t\t\t\t<description>Pull_Up Enable register   0 Pull_Up Disable  1  Pull_Up Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000208</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTA_PD</name>\n\t\t\t\t\t<description>Pull_Down Enable register   0 Pull_Down Disable  1  Pull_Down Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000300</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTB_PD</name>\n\t\t\t\t\t<description>Pull_Down Enable register   0 Pull_Down Disable  1  Pull_Down Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000304</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTC_PD</name>\n\t\t\t\t\t<description>Pull_Down Enable register   0 Pull_Down Disable  1  Pull_Down Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000308</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTA_OD</name>\n\t\t\t\t\t<description>Open_Drain Enable register   0 Open_Drain Disable  1  Open_Drain Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000400</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTB_OD</name>\n\t\t\t\t\t<description>Open_Drain Enable register   0 Open_Drain Disable  1  Open_Drain Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000404</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTC_OD</name>\n\t\t\t\t\t<description>Open_Drain Enable register   0 Open_Drain Disable  1  Open_Drain Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000408</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTA_WKE</name>\n\t\t\t\t\t<description>WakeUp Enable register   0 WakeUp Disable  1  WakeUp Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000500</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTB_WKE</name>\n\t\t\t\t\t<description>WakeUp Enable register   0 WakeUp Disable  1  WakeUp Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000504</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTC_WKE</name>\n\t\t\t\t\t<description>WakeUp Enable register   0 WakeUp Disable  1  WakeUp Enable  </description>\n\t\t\t\t\t<addressOffset>0x00000508</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORT_CFG</name>\n\t\t\t\t\t<description>Configure register  </description>\n\t\t\t\t\t<addressOffset>0x00000600</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PORTA_DS</name>\n\t\t\t\t\t\t<description>PORTA 驱动能力选择寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PORTB_DS</name>\n\t\t\t\t\t\t<description>PORTB 驱动能力选择寄存器</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PORTC_DS</name>\n\t\t\t\t\t\t<description>PORTC 驱动能力选择寄存器</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PORT_HYS</name>\n\t\t\t\t\t\t<description>PORT 输入迟滞等级选择</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTA_WK_SEL</name>\n\t\t\t\t\t<description>PORTA唤醒功能沿配置</description>\n\t\t\t\t\t<addressOffset>0x00000700</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTB_WK_SEL</name>\n\t\t\t\t\t<description>PORTB唤醒功能沿配置</description>\n\t\t\t\t\t<addressOffset>0x00000704</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN8</name>\n\t\t\t\t\t\t<description>PIN8 field</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN9</name>\n\t\t\t\t\t\t<description>PIN9 field</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN10</name>\n\t\t\t\t\t\t<description>PIN10 field</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN11</name>\n\t\t\t\t\t\t<description>PIN11 field</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN12</name>\n\t\t\t\t\t\t<description>PIN12 field</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN13</name>\n\t\t\t\t\t\t<description>PIN13 field</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN14</name>\n\t\t\t\t\t\t<description>PIN14 field</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN15</name>\n\t\t\t\t\t\t<description>PIN15 field</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PORTC_WK_SEL</name>\n\t\t\t\t\t<description>PORTC唤醒功能沿配置</description>\n\t\t\t\t\t<addressOffset>0x00000708</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN0</name>\n\t\t\t\t\t\t<description>PIN0 field</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN1</name>\n\t\t\t\t\t\t<description>PIN1 field</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN2</name>\n\t\t\t\t\t\t<description>PIN2 field</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN3</name>\n\t\t\t\t\t\t<description>PIN3 field</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN4</name>\n\t\t\t\t\t\t<description>PIN4 field</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN5</name>\n\t\t\t\t\t\t<description>PIN5 field</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN6</name>\n\t\t\t\t\t\t<description>PIN6 field</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PIN7</name>\n\t\t\t\t\t\t<description>PIN7 field</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\n\t\t\t</registers>\n\t\t\n\t\t</peripheral>\n\n\t\t\n\t\t<peripheral>\n\t\t\n\t\t\t<name>PWMBASE0</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>PWMBASE</groupName>\n\t\t\t<baseAddress>0x400B1000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x00000044</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>EN</name>\n\t\t\t\t\t<description>PWMBASE使能寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>COUNTER_EN</name>\n\t\t\t\t\t\t<description>PWMBASE计数器使能寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PWMBASE_DIV</name>\n\t\t\t\t\t<description>PWMBASE时钟预分频寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PWMBASE_DIV</name>\n\t\t\t\t\t\t<description>PWMBASE计数时钟预分频寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PWM_CON</name>\n\t\t\t\t\t<description>PWMBASE输出配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_OUT_INV</name>\n\t\t\t\t\t\t<description>PWM0CH0输出极性是否翻转寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_OUT_INV</name>\n\t\t\t\t\t\t<description>CH1输出极性是否翻转寄存器</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_OUT_INV</name>\n\t\t\t\t\t\t<description>CH2输出极性是否翻转寄存器</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_OE</name>\n\t\t\t\t\t\t<description>CH0通道波形输出使能</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_OE</name>\n\t\t\t\t\t\t<description>CH1通道波形输出使能</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_OE</name>\n\t\t\t\t\t\t<description>CH2通道波形输出使能</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\n\t\t\t\t<register>\n\n\t\t\t\t<name>PWMBASE_PERIOD</name>\n\t\t\t\t<description>PWMBASE周期配置寄存器</description>\n\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t<access>read-write</access>\n\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t<name>PWM_PERIOD</name>\n\t\t\t\t\t<description>PWM输出周期配置寄存器 </description>\n\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n        \n\t\t\t\t<register>\n\t\t\t\t\t\t\n\t\t\t\t\t<name>PWMBASE_INTEN</name>\n\t\t\t\t\t<description>PWMBASE_INTEN register</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_COMP_IE</name>\n\t\t\t\t\t\t<description>CH0到达翻转点中断使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_COMP_IE</name>\n\t\t\t\t\t\t<description>CH1到达翻转点中断使能</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_COMP_IE</name>\n\t\t\t\t\t\t<description>CH2到达翻转点中断使能</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>POF_IE</name>\n\t\t\t\t\t\t<description>周期溢出中断使能</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>PWMBASE_IF</name>\n\t\t\t\t\t<description>PWMBASE_IF register</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_COMP_IF</name>\n\t\t\t\t\t\t<description>CH0到达翻转点状态</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_COMP_IF</name>\n\t\t\t\t\t\t<description>CH1到达翻转点状态</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_COMP_IF</name>\n\t\t\t\t\t\t<description>CH2到达翻转点状态</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>POF_IF</name>\n\t\t\t\t\t\t<description>周期溢出中断状态</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMBASE_CNT</name>\n\t\t\t\t\t<description>PWMBASE当前计数值寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PWMBASE_CNT</name>\n\t\t\t\t\t\t<description>PWMBASE计数器当前计数值寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMBASE_CH0_COMP</name>\n\t\t\t\t\t<description>PWMBASE通道0翻转点配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_COMP</name>\n\t\t\t\t\t\t<description>CH0翻转点配置寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMBASE_CH1_COMP</name>\n\t\t\t\t\t<description>PWMBASE通道1翻转点配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000030</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_COMP</name>\n\t\t\t\t\t\t<description>CH1翻转点配置寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t<name>PWMBASE_CH2_COMP</name>\n\t\t\t\t<description>PWMBASE通道2翻转点配置寄存器</description>\n\t\t\t\t<addressOffset>0x00000040</addressOffset>\n\t\t\t\t<access>read-write</access>\n\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t<name>CH2_COMP</name>\n\t\t\t\t\t<description>CH2翻转点配置寄存器 </description>\n\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t</fields>\n\n\t\t\t\t</register>\n        \n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\n\t\t<peripheral derivedFrom=\"PWMBASE0\">\n\t\t\n\t\t\t<name>PWMBASE1</name>\n\t\t\t<baseAddress>0x400B1800</baseAddress>\n\n\t\t</peripheral>\n\n\t\t\n\t\t<peripheral>\n\t\t\n\t\t\t<name>PWMPLUS0</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>PWMPLUS</groupName>\n\t\t\t<baseAddress>0x400B4000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x000000e8</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\n\t\t\t\t\t<name>PWMPLUS_CFG</name>\n\t\t\t\t\t<description>PWMPLUS配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>COUNTER_EN</name>\n\t\t\t\t\t\t<description>计数器使能寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n            \n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CNT_TYPE</name>\n\t\t\t\t\t\t<description>PWM计数器行为方式</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CNT_REP</name>\n\t\t\t\t\t\t<description>PWM计数器循环方式</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OUT_MODE</name>\n\t\t\t\t\t\t<description>PWM输出模式</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>AUTO_RELOAD</name>\n\t\t\t\t\t\t<description>自动装载寄存器，表示周期溢出多少次后自动装载一次周期值、比较值、死区值和TRIGGER值。</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n            \n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\n\t\t\t\t\t<name>PWMPLUS_GEN</name>\n\t\t\t\t\t<description>PWMPLUS通道波形生成寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_IDLE</name>\n\t\t\t\t\t\t<description>原始CH0通道空闲时输出状态值</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n            \n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0N_IDLE</name>\n\t\t\t\t\t\t<description>原始CH0N通道空闲时输出状态值</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_IDLE</name>\n\t\t\t\t\t\t<description>原始CH1通道空闲时输出状态值</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1N_IDLE</name>\n\t\t\t\t\t\t<description>原始CH1N通道空闲时输出状态值</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_IDLE</name>\n\t\t\t\t\t\t<description>原始CH2通道空闲时输出状态值</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2N_IDLE</name>\n\t\t\t\t\t\t<description>原始CH2N通道空闲时输出状态值</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_START</name>\n\t\t\t\t\t\t<description>原始CH0通道开始计数时输出状态值</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_START</name>\n\t\t\t\t\t\t<description>原始CH1通道计数开始时输出状态值</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_START</name>\n\t\t\t\t\t\t<description>原始CH2通道计数开始时输出状态值</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_OUTINV</name>\n\t\t\t\t\t\t<description>CH0通道输出状态选择</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0N_OUTINV</name>\n\t\t\t\t\t\t<description>CH0N通道输出状态选择</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_OUTINV</name>\n\t\t\t\t\t\t<description>CH1通道输出状态选择</description>\n\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1N_OUTINV</name>\n\t\t\t\t\t\t<description>CH1N通道输出状态选择</description>\n\t\t\t\t\t\t<bitOffset>19</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_OUTINV</name>\n\t\t\t\t\t\t<description>CH2通道输出状态选择</description>\n\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2N_OUTINV</name>\n\t\t\t\t\t\t<description>CH2N通道输出状态选择</description>\n\t\t\t\t\t\t<bitOffset>21</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_OE</name>\n\t\t\t\t\t\t<description>CH0通道波形输出使能</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0N_OE</name>\n\t\t\t\t\t\t<description>CH0N通道波形输出使能</description>\n\t\t\t\t\t\t<bitOffset>25</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_OE</name>\n\t\t\t\t\t\t<description>CH1通道波形输出使能</description>\n\t\t\t\t\t\t<bitOffset>26</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1N_OE</name>\n\t\t\t\t\t\t<description>CH1N通道波形输出使能</description>\n\t\t\t\t\t\t<bitOffset>27</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_OE</name>\n\t\t\t\t\t\t<description>CH2通道波形输出使能</description>\n\t\t\t\t\t\t<bitOffset>28</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2N_OE</name>\n\t\t\t\t\t\t<description>CH2N通道波形输出使能</description>\n\t\t\t\t\t\t<bitOffset>29</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n            \n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\n\t\t\t\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_CLKSRC</name>\n\t\t\t\t\t<description>PWMPLUS时钟源和分频配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CNT_SRC</name>\n\t\t\t\t\t\t\t<description>PWMPLUS计数器计数时钟选择 </description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>EXTPULSE0_EDGE</name>\n\t\t\t\t\t\t\t<description>Extpulse0作为计数时钟时边沿选择控制 </description>\n\t\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>EXTPULSE1_EDGE</name>\n\t\t\t\t\t\t\t<description>Extpulse1作为计数时钟时边沿选择控制 </description>\n\t\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>PREDIV</name>\n\t\t\t\t\t\t\t<description>内部预分频时钟频率选择。</description>\n\t\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n      \n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_BRAKE_CFG</name>\n\t\t\t\t\t<description>PWMPLUS刹车配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000000c</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CH0_BRAKE</name>\n\t\t\t\t\t\t\t<description>CH0/CH0N刹车控制选择 </description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CH1_BRAKE</name>\n\t\t\t\t\t\t\t<description>CH1/CH1N刹车控制选择 </description>\n\t\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CH2_BRAKE</name>\n\t\t\t\t\t\t\t<description>CH2/CH2N刹车控制选择 </description>\n\t\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>BRAKE_LEV</name>\n\t\t\t\t\t\t\t<description>刹车有效电平选择 </description>\n\t\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>BRAKE_CH0POL</name>\n\t\t\t\t\t\t\t<description>刹车时CH0输出电平选择</description>\n\t\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>BRAKE_CH0NPOL</name>\n\t\t\t\t\t\t\t<description>刹车时CH0N输出电平选择</description>\n\t\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>BRAKE_CH1POL</name>\n\t\t\t\t\t\t\t<description>刹车时CH1输出电平选择</description>\n\t\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>BRAKE_CH1NPOL</name>\n\t\t\t\t\t\t\t<description>刹车时CH1N输出电平选择</description>\n\t\t\t\t\t\t\t<bitOffset>19</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>BRAKE_CH2POL</name>\n\t\t\t\t\t\t\t<description>刹车时CH2输出电平选择</description>\n\t\t\t\t\t\t\t<bitOffset>20</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>BRAKE_CH2NPOL</name>\n\t\t\t\t\t\t\t<description>刹车时CH2N输出电平选择</description>\n\t\t\t\t\t\t\t<bitOffset>21</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>BRAKE_FILLER</name>\n\t\t\t\t\t\t\t<description>刹车信号数字滤波控制</description>\n\t\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_MASK_LEV</name>\n\t\t\t\t\t<description>PWMPLUS强制输出电平选择寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CH0_MASK_LEV</name>\n\t\t\t\t\t\t\t<description>CH0通道屏蔽电平选择 </description>\n\t\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CH0N_MASK_LEV</name>\n\t\t\t\t\t\t\t<description>CH0N通道屏蔽电平选择 </description>\n\t\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CH1_MASK_LEV</name>\n\t\t\t\t\t\t\t<description>CH1通道屏蔽电平选择 </description>\n\t\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CH1N_MASK_LEV</name>\n\t\t\t\t\t\t\t<description>CH1N通道屏蔽电平选择 </description>\n\t\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CH2_MASK_LEV</name>\n\t\t\t\t\t\t\t<description>CH2通道屏蔽电平选择 </description>\n\t\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t\t<name>CH2N_MASK_LEV</name>\n\t\t\t\t\t\t\t<description>CH2N通道屏蔽电平选择 </description>\n\t\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n      \n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_PERIOD</name>\n\t\t\t\t\t<description>PWMPLUS计数器周期值寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000001C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>PERIOD</name>\n\t\t\t\t\t\t<description>PWMPLUS周期配置寄存器。 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_CH0_COMP</name>\n\t\t\t\t\t<description>PWMPLUS通道0翻转点配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_COMP</name>\n\t\t\t\t\t\t<description>CH0/CH0N翻转点配置寄存器。 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_CH1_COMP</name>\n\t\t\t\t\t<description>PWMPLUS通道1翻转点配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000024</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_COMP</name>\n\t\t\t\t\t\t<description>CH1/CH1N翻转点配置寄存器。 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_CH2_COMP</name>\n\t\t\t\t\t<description>PWMPLUS通道2翻转点配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000028</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_COMP</name>\n\t\t\t\t\t\t<description>CH2/CH2N翻转点配置寄存器。 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_CH0_DT</name>\n\t\t\t\t\t<description>PWMPLUS通道0死区长度配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000030</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_DT</name>\n\t\t\t\t\t\t<description>CH0/CH0N死区长度配置寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>10</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n      \n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_CH1_DT</name>\n\t\t\t\t\t<description>PWMPLUS通道1死区长度配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000034</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_DT</name>\n\t\t\t\t\t\t<description>CH1/CH1N死区长度配置寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>10</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n      \n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_CH2_DT</name>\n\t\t\t\t\t<description>PWMPLUS通道2死区长度配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000038</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_DT</name>\n\t\t\t\t\t\t<description>CH2/CH2N死区长度配置寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>10</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n      \n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_TRIG_COMP</name>\n\t\t\t\t\t<description>PWMPLUS内部触发比较值寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000040</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIG_COMP</name>\n\t\t\t\t\t\t<description>内部触发点配置寄存器 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>16</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_TRIG_CFG</name>\n\t\t\t\t\t<description>PWMPLUS内部触发配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000044</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TRIGOUT0_SEL</name>\n\t\t\t\t\t\t<description>输出的trigger0信号功能选择 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\t\t\t\t\t\n\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_IE</name>\n\t\t\t\t\t<description>PWMPLUS中断使能寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000060</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UP_CH0COMP_IE</name>\n\t\t\t\t\t\t<description>向上计数CH0到达翻转点中断使能 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UP_CH1COMP_IE</name>\n\t\t\t\t\t\t<description>向上计数CH1到达翻转点中断使能 </description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UP_CH2COMP_IE</name>\n\t\t\t\t\t\t<description>向上计数CH2到达翻转点中断使能 </description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UP_POF_IE</name>\n\t\t\t\t\t\t<description>向上计数周期溢出中断使能 </description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UP_TRIG_IE</name>\n\t\t\t\t\t\t<description>向上计数达到TRIGGER触发点中断使能 </description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DOWN_CH0COMP_IE</name>\n\t\t\t\t\t\t<description>向下计数CH0到达翻转点中断使能 </description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DOWN_CH1COMP_IE</name>\n\t\t\t\t\t\t<description>向下计数CH1到达翻转点中断使能 </description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DOWN_CH2COMP_IE</name>\n\t\t\t\t\t\t<description>向下计数CH2到达翻转点中断使能 </description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DOWN_POF_IE</name>\n\t\t\t\t\t\t<description>向下计数周期溢出中断使能 </description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DOWN_TRIG_IE</name>\n\t\t\t\t\t\t<description>向下计数达到TRIGGER触发点中断使能 </description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BRAK0_IE</name>\n\t\t\t\t\t\t<description>刹车0中断使能 </description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BRAK1_IE</name>\n\t\t\t\t\t\t<description>刹车1中断使能 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</description>\n\t\t\t\t\t\t<bitOffset>19</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_IF</name>\n\t\t\t\t\t<description>PWMPLUS中断状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000064</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UP_CH0COMP_IF</name>\n\t\t\t\t\t\t<description>向上计数CH0到达翻转点中断状态 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>UP_CH1COMP_IF</name>\n\t\t\t\t\t\t<description>向上计数CH1到达翻转点中断状态 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</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DOWN_CH0COMP_IF</name>\n\t\t\t\t\t\t<description>向下计数CH0到达翻转点中断状态 </description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DOWN_CH1COMP_IF</name>\n\t\t\t\t\t\t<description>向下计数CH1到达翻转点中断状态 </description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DOWN_CH2COMP_IF</name>\n\t\t\t\t\t\t<description>向下计数CH2到达翻转点中断状态 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</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CNT_ST</name>\n\t\t\t\t\t\t<description>PWM计数器工作状态 </description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n      \n\t\t\t\t<register>\n\n\t\t\t\t\t<name>PWMPLUS_BRAKE_ST</name>\n\t\t\t\t\t<description>PWMPLUS刹车状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x000000E4</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BRAKE_ST</name>\n\t\t\t\t\t\t<description>刹车输入信号当前状态 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register</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SPR0</name>\n\t\t\t\t\t\t<description>SPI波特率选择位0</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SPR1</name>\n\t\t\t\t\t\t<description>SPI波特率选择位1</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SPR2</name>\n\t\t\t\t\t\t<description>SPI波特率选择位2</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SPE</name>\n\t\t\t\t\t\t<description>SPI系统使能</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CPHA</name>\n\t\t\t\t\t\t<description>时钟相位选择</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CPOL</name>\n\t\t\t\t\t\t<description>时钟极性选择</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MSTR</name>\n\t\t\t\t\t\t<description>主从模式选择</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LSB</name>\n\t\t\t\t\t\t<description>数据传输顺序选择</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CPHA_DATAHOLD_S</name>\n\t\t\t\t\t\t<description>从模式下 CPHA 为 1 时，数据保持时间配置寄存器</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SSN</name>\n\t\t\t\t\t\t<description>主模式下SSN输出</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXDMAEN</name>\n\t\t\t\t\t\t<description>接收DMA控制使能位</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXDMAEN</name>\n\t\t\t\t\t\t<description>发送DMA控制使能位</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RF_CLR</name>\n\t\t\t\t\t\t<description>接收FIFO清除位</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TF_CLR</name>\n\t\t\t\t\t\t<description>发送FIFO清除位</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>WDR</name>\n\t\t\t\t\t<description>WDR register</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>WDR</name>\n\t\t\t\t\t\t<description>写数据寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>RDR</name>\n\t\t\t\t\t<description>RDR register</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RDR</name>\n\t\t\t\t\t\t<description>读数据寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IE</name>\n\t\t\t\t\t<description>IE register</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_OVF</name>\n\t\t\t\t\t\t<description>接收FIFO溢出中断使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_FULL</name>\n\t\t\t\t\t\t<description>接收FIFO满中断使能</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_HFULL</name>\n\t\t\t\t\t\t<description>接收FIFO半满中断使能</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXFIFO_EMPTY</name>\n\t\t\t\t\t\t<description>发送FIFO空中断使能</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXFIFO_HFULL</name>\n\t\t\t\t\t\t<description>发送FIFO半满中断使能</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IF</name>\n\t\t\t\t\t<description>IF register</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_OVF</name>\n\t\t\t\t\t\t<description>接收FIFO溢出标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_FULL</name>\n\t\t\t\t\t\t<description>接收FIFO满标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXFIFO_HFULL</name>\n\t\t\t\t\t\t<description>接收FIFO半满标志</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXFIFO_EMPTY</name>\n\t\t\t\t\t\t<description>发送FIFO空标志</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXFIFO_HFULL</name>\n\t\t\t\t\t\t<description>发送FIFO半满标志</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BUSY</name>\n\t\t\t\t\t\t<description>SPI忙标志</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>FIFOST</name>\n\t\t\t\t\t<description>FIFOST register</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RFE</name>\n\t\t\t\t\t\t<description>接收FIFO空标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RFF</name>\n\t\t\t\t\t\t<description>接收FIFO满标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RFHF</name>\n\t\t\t\t\t\t<description>接收FIFO半满标志</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TFE</name>\n\t\t\t\t\t\t<description>发送FIFO空标志</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TFF</name>\n\t\t\t\t\t\t<description>发送FIFO满标志</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TFHF</name>\n\t\t\t\t\t\t<description>发送FIFO半满标志</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RF_LEVEL</name>\n\t\t\t\t\t\t<description>接收FIFO水位状态</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TF_LEVEL</name>\n\t\t\t\t\t\t<description>发送FIFO水位状态</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\n    \t<peripheral derivedFrom=\"SPI0\">\n\t\t\n\t\t\t<name>SPI1</name>\n\t\t\t<baseAddress>0x400B8800</baseAddress>\n\t\t\n\t\t</peripheral>\n\n\n\t\t<peripheral>\n  \n\t\t\t<name>IIC0</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>IIC</groupName>\n\t\t\t<baseAddress>0x400B9000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x00000038</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CCFG</name>\n\t\t\t\t\t<description>通用配置寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x0000010C</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EN</name>\n\t\t\t\t\t\t<description>IIC 总线使能</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MODE</name>\n\t\t\t\t\t\t<description>模式控制</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HS</name>\n\t\t\t\t\t\t<description>High-speed mode。</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DNF</name>\n\t\t\t\t\t\t<description>ReceiveSDA、SCL数字噪声滤波</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\n\t\t\t\t\t<name>CST</name>\n\t\t\t\t\t<description>CST register</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000006</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BUSY</name>\n\t\t\t\t\t\t<description>总线忙状态</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SCL</name>\n\t\t\t\t\t\t<description>IICSCL状态</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SDA</name>\n\t\t\t\t\t\t<description>IICSDA状态</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLV_ACTIVE</name>\n\t\t\t\t\t\t<description>Slave活跃状态</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLV_RD</name>\n\t\t\t\t\t\t<description>Slave读状态</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLV_WR</name>\n\t\t\t\t\t\t<description>Slave写状态</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLV_STRETCH_BUSY</name>\n\t\t\t\t\t\t<description>SlaveClockStretching忙状态</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLV_RXDT</name>\n\t\t\t\t\t\t<description>Slave接收到的数据类型</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CTRANS</name>\n\t\t\t\t\t<description>CTRANS register</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TX_ACK</name>\n\t\t\t\t\t\t<description>发送 ACK/NACK</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RX_ACK</name>\n\t\t\t\t\t\t<description>接收到的ACK/NACK</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXD_CLR</name>\n\t\t\t\t\t\t<description>发送数据寄存器清空</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>RXDATA</name>\n\t\t\t\t\t<description>RXDATA register</description>\n\t\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXDATA</name>\n\t\t\t\t\t\t<description>接收数据寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>TXDATA</name>\n\t\t\t\t\t<description>TXDATA register</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXDATA</name>\n\t\t\t\t\t\t<description>发送数据寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IE</name>\n\t\t\t\t\t<description>IE register</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000001</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXOVF</name>\n\t\t\t\t\t\t<description>接收数据寄存器溢出中断使能</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXF</name>\n\t\t\t\t\t\t<description>发送数据结束中断使能</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXF</name>\n\t\t\t\t\t\t<description>接收数据结束中断使能</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLV_STA</name>\n\t\t\t\t\t\t<description>Slave检测到START中断使能</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLV_STO</name>\n\t\t\t\t\t\t<description>Slave检测到STOP中断使能</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>AL</name>\n\t\t\t\t\t\t<description>Master仲裁丢失总线中断使能</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MLTO</name>\n\t\t\t\t\t\t<description>Master SCL LOW 超时中断使能</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IF</name>\n\t\t\t\t\t<description>IF register</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000001</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXE</name>\n\t\t\t\t\t\t<description>发送数据寄存器空</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXNE</name>\n\t\t\t\t\t\t<description>接收数据寄存器非空</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXOVF</name>\n\t\t\t\t\t\t<description>接收数据寄存器溢出</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>TXF</name>\n\t\t\t\t\t\t<description>发送数据结束</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RXF</name>\n\t\t\t\t\t\t<description>接收数据结束</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLV_STA</name>\n\t\t\t\t\t\t<description>Slave检测到START</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SLV_STO</name>\n\t\t\t\t\t\t<description>Slave检测到STOP</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>AL</name>\n\t\t\t\t\t\t<description>Master仲裁丢失总线</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MLTO</name>\n\t\t\t\t\t\t<description>Master SCL LOW 超时</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\t  \n\t\t\t\t<register>\n  \n\t\t\t\t\t<name>MCTRL</name>\n\t\t\t\t\t<description>MCTRL register</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>STA</name>\n\t\t\t\t\t\t<description>写1，产生START</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RD</name>\n\t\t\t\t\t\t<description>写1，接收数据到RXDATA中</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>WR</name>\n\t\t\t\t\t\t<description>写1，发送TXDATA中数据</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>STO</name>\n\t\t\t\t\t\t<description>写1,产生STOP，</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t  \n\t\t\t\t\t<name>MSPC</name>\n\t\t\t\t\t<description>MSPC register</description>\n\t\t\t\t\t<addressOffset>0x00000024</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00034080</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SCL_LOW</name>\n\t\t\t\t\t\t<description>SCL时钟低电平时间配置</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SCL_HI</name>\n\t\t\t\t\t\t<description>SCL时钟高电平时间配置</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CPD</name>\n\t\t\t\t\t\t<description>时钟预分频，详见SCL_HI和SCL_LOW描述</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DAT_HD</name>\n\t\t\t\t\t\t<description>SDA数据保持时间配置</description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t  \n\t\t\t\t\t<name>SCTRL</name>\n\t\t\t\t\t<description>SCTRL register</description>\n\t\t\t\t\t<addressOffset>0x00000030</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADMD</name>\n\t\t\t\t\t\t<description>slave地址模式控制</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MCDE</name>\n\t\t\t\t\t\t<description>Master Code Detect Enable</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>STRETCH</name>\n\t\t\t\t\t\t<description>Clock stretching使能控制</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ASDS</name>\n\t\t\t\t\t\t<description>Stretching 后数据建立时间自适应使能</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t  \n\t\t\t\t\t<name>SADDR</name>\n\t\t\t\t\t<description>SADDR register</description>\n\t\t\t\t\t<addressOffset>0x00000034</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADDR0</name>\n\t\t\t\t\t\t<description>地址</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADDR7_1</name>\n\t\t\t\t\t\t<description>地址[7:1]</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>7</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADDR9_8</name>\n\t\t\t\t\t\t<description>地址[9:8]</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MASK_ADDR0</name>\n\t\t\t\t\t\t<description>Slave 对应地址位掩码</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MASK_ADDR7_1</name>\n\t\t\t\t\t\t<description>Slave 对应地址位掩码</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>7</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\t\t\n\t\t<peripheral derivedFrom=\"IIC0\">\n  \n\t\t\t<name>IIC1</name>\n\t\t\t<baseAddress>0x400B9800</baseAddress>\n\n\t\t</peripheral>\n\n\n\t\t<peripheral>\n\n\t\t\t<name>ADC</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>ADC</groupName>\n\t\t\t<baseAddress>0x400BA000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x000000F8</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CTRL</name>\n\t\t\t\t\t<description>CTRL register</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0</name>\n\t\t\t\t\t\t<description>通道0选中</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1</name>\n\t\t\t\t\t\t<description>通道1选中</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2</name>\n\t\t\t\t\t\t<description>通道2选中</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH3</name>\n\t\t\t\t\t\t<description>通道3选中</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH4</name>\n\t\t\t\t\t\t<description>通道4选中</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH5</name>\n\t\t\t\t\t\t<description>通道5选中</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH6</name>\n\t\t\t\t\t\t<description>通道6选中</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH7</name>\n\t\t\t\t\t\t<description>通道7选中</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH8</name>\n\t\t\t\t\t\t<description>通道8选中</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH9</name>\n\t\t\t\t\t\t<description>通道9选中</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH10</name>\n\t\t\t\t\t\t<description>通道10选中</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH11</name>\n\t\t\t\t\t\t<description>通道11选中</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH12</name>\n\t\t\t\t\t\t<description>通道12选中</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH13</name>\n\t\t\t\t\t\t<description>通道13选中</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH14</name>\n\t\t\t\t\t\t<description>通道14选中</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH15</name>\n\t\t\t\t\t\t<description>通道15选中</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>AVG</name>\n\t\t\t\t\t\t<description>一次启动 ADC 采样取平均次数配置寄存器</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CONT</name>\n\t\t\t\t\t\t<description>ADC 采样工作模式</description>\n\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SMPL_SETUP</name>\n\t\t\t\t\t\t<description>外部采样时钟下采样建立时间</description>\n\t\t\t\t\t\t<bitOffset>19</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADC_MEM_MODE</name>\n\t\t\t\t\t\t<description>ADC 数据存储方式选择 </description>\n\t\t\t\t\t\t<bitOffset>22</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADC_SMPL_CLK</name>\n\t\t\t\t\t\t<description>ADC采样模式选择</description>\n\t\t\t\t\t\t<bitOffset>23</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IN_SMPL_WIN</name>\n\t\t\t\t\t\t<description>ADC 内部采样时钟方式采样窗口设置 </description>\n\t\t\t\t\t\t<bitOffset>24</bitOffset>\n\t\t\t\t\t\t<bitWidth>3</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADC_EN</name>\n\t\t\t\t\t\t<description>ADC使能位 </description>\n\t\t\t\t\t\t<bitOffset>27</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ADC_TRIG</name>\n\t\t\t\t\t\t<description>ADC触发源选择 </description>\n\t\t\t\t\t\t<bitOffset>28</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DMA_EN</name>\n\t\t\t\t\t\t<description>DMA读取FIFO使能</description>\n\t\t\t\t\t\t<bitOffset>29</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n            \n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>START</name>\n\t\t\t\t\t<description>START register</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>START</name>\n\t\t\t\t\t\t<description>启动信号</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>BUSY</name>\n\t\t\t\t\t\t<description>忙信号</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>SOFT_RESET</name>\n\t\t\t\t\t\t<description>软复位使能</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>FIFOCLR</name>\n\t\t\t\t\t\t<description>FIFO清除使能</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>IE</name>\n\t\t\t\t\t<description>IE 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register</description>\n\t\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH0_EOC</name>\n\t\t\t\t\t\t<description>通道0转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH1_EOC</name>\n\t\t\t\t\t\t<description>通道1转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH2_EOC</name>\n\t\t\t\t\t\t<description>通道2转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH3_EOC</name>\n\t\t\t\t\t\t<description>通道3转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH4_EOC</name>\n\t\t\t\t\t\t<description>通道4转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH5_EOC</name>\n\t\t\t\t\t\t<description>通道5转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH6_EOC</name>\n\t\t\t\t\t\t<description>通道6转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>6</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH7_EOC</name>\n\t\t\t\t\t\t<description>通道7转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH8_EOC</name>\n\t\t\t\t\t\t<description>通道8转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH9_EOC</name>\n\t\t\t\t\t\t<description>通道9转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>9</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH10_EOC</name>\n\t\t\t\t\t\t<description>通道10转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>10</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH11_EOC</name>\n\t\t\t\t\t\t<description>通道11转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>11</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH12_EOC</name>\n\t\t\t\t\t\t<description>通道12转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH13_EOC</name>\n\t\t\t\t\t\t<description>通道13转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>13</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH14_EOC</name>\n\t\t\t\t\t\t<description>通道14转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>14</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CH15_EOC</name>\n\t\t\t\t\t\t<description>通道15转换完成中断状态</description>\n\t\t\t\t\t\t<bitOffset>15</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>FIFO_FULL</name>\n\t\t\t\t\t\t<description>FIFO满中断状态</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>FIFO_HFULL</name>\n\t\t\t\t\t\t<description>FIFO半满中断状态</description>\n\t\t\t\t\t\t<bitOffset>17</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>FIFO_OVF</name>\n\t\t\t\t\t\t<description>FIFO溢出中断状态</description>\n\t\t\t\t\t\t<bitOffset>18</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH0_STATE</name>\n\t\t\t\t\t<description>CH0_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH0_DATA</name>\n\t\t\t\t\t<description>CH0_DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH1_STATE</name>\n\t\t\t\t\t<description>CH1_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH1_DATA</name>\n\t\t\t\t\t<description>CH1_DATA register</description>\n\t\t\t\t\t<addressOffset>0x0000001C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH2_STATE</name>\n\t\t\t\t\t<description>CH2_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH2_DATA</name>\n\t\t\t\t\t<description>CH2_DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000024</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH3_STATE</name>\n\t\t\t\t\t<description>CH3_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000028</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH3_DATA</name>\n\t\t\t\t\t<description>CH3_DATA register</description>\n\t\t\t\t\t<addressOffset>0x0000002C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH4_STATE</name>\n\t\t\t\t\t<description>CH4_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000030</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH4_DATA</name>\n\t\t\t\t\t<description>CH4_DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000034</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH5_STATE</name>\n\t\t\t\t\t<description>CH5_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000038</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH5_DATA</name>\n\t\t\t\t\t<description>CH5_DATA register</description>\n\t\t\t\t\t<addressOffset>0x0000003C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH6_STATE</name>\n\t\t\t\t\t<description>CH6_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000040</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH6_DATA</name>\n\t\t\t\t\t<description>CH6_DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000044</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH7_STATE</name>\n\t\t\t\t\t<description>CH7_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000048</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH7_DATA</name>\n\t\t\t\t\t<description>CH7_DATA register</description>\n\t\t\t\t\t<addressOffset>0x0000004C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH8_STATE</name>\n\t\t\t\t\t<description>CH8_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000050</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH8_DATA</name>\n\t\t\t\t\t<description>CH8_DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000054</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH9_STATE</name>\n\t\t\t\t\t<description>CH9_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000058</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH9_DATA</name>\n\t\t\t\t\t<description>CH9_DATA register</description>\n\t\t\t\t\t<addressOffset>0x0000005C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH10_STATE</name>\n\t\t\t\t\t<description>CH10_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000060</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH10_DATA</name>\n\t\t\t\t\t<description>CH10_DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000064</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH11_STATE</name>\n\t\t\t\t\t<description>CH11_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000068</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH11_DATA</name>\n\t\t\t\t\t<description>CH11_DATA register</description>\n\t\t\t\t\t<addressOffset>0x0000006C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH12_STATE</name>\n\t\t\t\t\t<description>CH12_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000070</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH12_DATA</name>\n\t\t\t\t\t<description>CH12_DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000074</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH13_STATE</name>\n\t\t\t\t\t<description>CH13_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000078</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH13_DATA</name>\n\t\t\t\t\t<description>CH13_DATA register</description>\n\t\t\t\t\t<addressOffset>0x0000007C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH14_STATE</name>\n\t\t\t\t\t<description>CH14_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000080</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH14_DATA</name>\n\t\t\t\t\t<description>CH14_DATA register</description>\n\t\t\t\t\t<addressOffset>0x00000084</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH15_STATE</name>\n\t\t\t\t\t<description>CH15_STATE register</description>\n\t\t\t\t\t<addressOffset>0x00000088</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EOC</name>\n\t\t\t\t\t\t<description>转换完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>CH15_DATA</name>\n\t\t\t\t\t<description>CH15_DATA register</description>\n\t\t\t\t\t<addressOffset>0x0000008C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>FIFO_STATE</name>\n\t\t\t\t\t<description>FIFO_STATE register</description>\n\t\t\t\t\t<addressOffset>0x000000A0</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>FULL</name>\n\t\t\t\t\t\t<description>满标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>HFULL</name>\n\t\t\t\t\t\t<description>半满标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EMPTY</name>\n\t\t\t\t\t\t<description>空标志</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OVF</name>\n\t\t\t\t\t\t<description>溢出标志</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>LEVEL</name>\n\t\t\t\t\t\t<description>水位</description>\n\t\t\t\t\t\t<bitOffset>4</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>FIFO_DATA</name>\n\t\t\t\t\t<description>FIFO_DATA register</description>\n\t\t\t\t\t<addressOffset>0x000000A4</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>NUM</name>\n\t\t\t\t\t\t<description>通道编号</description>\n\t\t\t\t\t\t<bitOffset>12</bitOffset>\n\t\t\t\t\t\t<bitWidth>4</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\n\n\t\t\t\t\t<name>EXTTRIG_SEL</name>\n\t\t\t\t\t<description>外部信号触发ADC选择寄存器</description>\n\t\t\t\t\t<addressOffset>0x000000B0</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\n\t\t\t\t\t<fields>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATA</name>\n\t\t\t\t\t\t<description>通道12bit数据</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>12</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n        \n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>ADC_CALIB_OFFSET</name>\n\t\t\t\t\t<description>ADC_CALIB_OFFSET register</description>\n\t\t\t\t\t<addressOffset>0x000000F0</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OFFSET</name>\n\t\t\t\t\t\t<description>ADC数据校准的OFFSET值 </description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>8</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>OFFSET_VALID</name>\n\t\t\t\t\t\t<description>OFFSET数据是否有效 </description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t<register>\t\t\n\n\t\t\t\t\t<name>ADC_CALIB_KD</name>\n\t\t\t\t\t<description>ADC_CALIB_KD register</description>\n\t\t\t\t\t<addressOffset>0x000000F4</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>KD</name>\n\t\t\t\t\t\t<description>ADC数据校准K值的小数部分</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>10</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>VALID</name>\n\t\t\t\t\t\t<description>KD数据是否有效</description>\n\t\t\t\t\t\t<bitOffset>16</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\n\t\t\t\t</register>\n\t\t\t\t\n\t\t\t\t\n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\n\n\n\t\t<peripheral>\n  \n\t\t\t<name>AES</name>\n\t\t\t<description>Registers group</description>\n\t\t\t<groupName>AES</groupName>\n\t\t\t<baseAddress>0x400BD000</baseAddress>\n\t\t\t<addressBlock>\n\t\t\t<offset>0x00000000</offset>\n\t\t\t<size>0x00000030</size>\n\t\t\t<usage>registers</usage>\n\t\t\t</addressBlock>\n\t\t\t\n\t\t\t<registers>\n\t\t\t\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>CR</name>\n\t\t\t\t\t<description>控制寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000000</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>EN</name>\n\t\t\t\t\t\t<description>使能信号</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DATATYPE</name>\n\t\t\t\t\t\t<description>数据类型选择</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>MODE</name>\n\t\t\t\t\t\t<description>模式选择</description>\n\t\t\t\t\t\t<bitOffset>3</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CHMOD</name>\n\t\t\t\t\t\t<description>链接模式选择</description>\n\t\t\t\t\t\t<bitOffset>5</bitOffset>\n\t\t\t\t\t\t<bitWidth>2</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CCFC</name>\n\t\t\t\t\t\t<description>计算完成标志清除</description>\n\t\t\t\t\t\t<bitOffset>7</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>ERRC</name>\n\t\t\t\t\t\t<description>错误标志清除</description>\n\t\t\t\t\t\t<bitOffset>8</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>SR</name>\n\t\t\t\t\t<description>状态寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000004</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>CCF</name>\n\t\t\t\t\t\t<description>计算完成标志</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>RDERR</name>\n\t\t\t\t\t\t<description>读取错误标志</description>\n\t\t\t\t\t\t<bitOffset>1</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>WRERR</name>\n\t\t\t\t\t\t<description>写入错误标志</description>\n\t\t\t\t\t\t<bitOffset>2</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DINR</name>\n\t\t\t\t\t<description>输入数据寄存器</description>\n\t\t\t\t\t<addressOffset>0x00000008</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DINR</name>\n\t\t\t\t\t\t<description>输入数据寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>DOUTR</name>\n\t\t\t\t\t<description>输出数据寄存器</description>\n\t\t\t\t\t<addressOffset>0x0000000C</addressOffset>\n\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>DOUTR</name>\n\t\t\t\t\t\t<description>数据输出寄存器</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-only</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>KEYR0</name>\n\t\t\t\t\t<description>密钥寄存器0</description>\n\t\t\t\t\t<addressOffset>0x00000010</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>KEYR</name>\n\t\t\t\t\t\t<description>密钥寄存器[31:0]</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>KEYR1</name>\n\t\t\t\t\t<description>密钥寄存器1</description>\n\t\t\t\t\t<addressOffset>0x00000014</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>KEYR</name>\n\t\t\t\t\t\t<description>密钥寄存器[63:32]</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>KEYR2</name>\n\t\t\t\t\t<description>密钥寄存器2</description>\n\t\t\t\t\t<addressOffset>0x00000018</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>KEYR</name>\n\t\t\t\t\t\t<description>密钥寄存器[95:64]</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>KEYR3</name>\n\t\t\t\t\t<description>密钥寄存器3</description>\n\t\t\t\t\t<addressOffset>0x0000001C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>KEYR</name>\n\t\t\t\t\t\t<description>密钥寄存器[127:96]</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>32</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IVR0</name>\n\t\t\t\t\t<description>加密起始点寄存器0</description>\n\t\t\t\t\t<addressOffset>0x00000020</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IVR</name>\n\t\t\t\t\t\t<description>初始化向量寄存器[31：0]</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IVR1</name>\n\t\t\t\t\t<description>加密起始点寄存器1</description>\n\t\t\t\t\t<addressOffset>0x00000024</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IVR</name>\n\t\t\t\t\t\t<description>初始化向量寄存器[63:32]</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IVR2</name>\n\t\t\t\t\t<description>加密起始点寄存器2</description>\n\t\t\t\t\t<addressOffset>0x00000028</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IVR</name>\n\t\t\t\t\t\t<description>初始化向量寄存器[95:64]</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\t\t\t\t<register>\n\t\t\t\t\n\t\t\t\t\t<name>IVR3</name>\n\t\t\t\t\t<description>加密起始点寄存器3</description>\n\t\t\t\t\t<addressOffset>0x0000002C</addressOffset>\n\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t<resetValue>0x00000000</resetValue>\n\t\t\t\t\t<resetMask>0xFFFFFFFF</resetMask>\n\t\t\t\t\t\n\t\t\t\t\t<fields>\n\t\t\t\t\t\n\t\t\t\t\t\t<field>\n\t\t\t\t\t\t<name>IVR</name>\n\t\t\t\t\t\t<description>初始化向量寄存器（MSB IVR [127：96]）</description>\n\t\t\t\t\t\t<bitOffset>0</bitOffset>\n\t\t\t\t\t\t<bitWidth>1</bitWidth>\n\t\t\t\t\t\t<access>read-write</access>\n\t\t\t\t\t\t</field>\n\t\t\t\t\t\t\n\t\t\t\t\t</fields>\n\t\t\t\t\n\t\t\t\t</register>\n\n\n\t\t\t</registers>\n\t\t\t\n\t\t</peripheral>\n\t\t\n\n\t</peripherals>\n\n</device>"
  },
  {
    "path": "Dockerfile",
    "content": "FROM --platform=amd64 archlinux:latest\r\nRUN pacman -Syyu base-devel --noconfirm\r\nRUN pacman -Syyu arm-none-eabi-gcc --noconfirm\r\nRUN pacman -Syyu arm-none-eabi-newlib --noconfirm\r\nRUN pacman -Syyu git --noconfirm\r\nRUN pacman -Syyu python-pip --noconfirm\r\nRUN pacman -Syyu python-crcmod --noconfirm\r\nWORKDIR /app\r\nCOPY . .\r\n\r\nRUN git submodule update --init --recursive\r\n#RUN make && cp firmware* compiled-firmware/"
  },
  {
    "path": "Dockerfile_cn",
    "content": "# 使用指定平台和最新的 Arch Linux 镜像\nFROM --platform=amd64 archlinux:latest\n\n# 更换镜像源为更快的服务器，并更新系统和安装必要的软件包\nRUN echo 'Server = http://mirrors.ustc.edu.cn/archlinux/$repo/os/$arch' > /etc/pacman.d/mirrorlist\nRUN   pacman -Syyu --noconfirm\nRUN   pacman -S --noconfirm --needed base-devel arm-none-eabi-gcc arm-none-eabi-newlib git python-pip python-crcmod\nRUN   pacman -Scc --noconfirm\n\n# 设置工作目录\nWORKDIR /app\n\n# 复制当前目录内容到工作目录\nCOPY . .\n\n# 初始化并更新子模块\nRUN git submodule update --init --recursive\n\n# 如果需要编译固件，取消注释以下行\n# RUN make && cp firmware* compiled-firmware/\n"
  },
  {
    "path": "Doxyfile",
    "content": "OUTPUT_DIRECTORY       = docs\nGENERATE_LATEX         = NO\nGENERATE_RTF           = NO\nGENERATE_MAN           = NO\nOPTIMIZE_OUTPUT_FOR_C  = YES\nHAVE_DOT               = YES\nEXTRACT_ALL            = YES\nEXTRACT_PRIVATE        = YES\nEXTRACT_STATIC         = YES\nCALL_GRAPH             = YES\nCALLER_GRAPH           = YES\nDISABLE_INDEX          = YES\nGENERATE_TREEVIEW      = YES\nRECURSIVE              = YES\nCOLLABORATION_GRAPH    = YES\nGRAPHICAL_HIERARCHY    = YES\nDOT_MULTI_TARGETS      = YES"
  },
  {
    "path": "LICENSE",
    "content": "                                 Apache License\r\n                           Version 2.0, January 2004\r\n                        http://www.apache.org/licenses/\r\n\r\n   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION\r\n\r\n   1. Definitions.\r\n\r\n      \"License\" shall mean the terms and conditions for use, reproduction,\r\n      and distribution as defined by Sections 1 through 9 of this document.\r\n\r\n      \"Licensor\" shall mean the copyright owner or entity authorized by\r\n      the copyright owner that is granting the License.\r\n\r\n      \"Legal Entity\" shall mean the union of the acting entity and all\r\n      other entities that control, are controlled by, or are under common\r\n      control with that entity. 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For the purposes\r\n      of this License, Derivative Works shall not include works that remain\r\n      separable from, or merely link (or bind by name) to the interfaces of,\r\n      the Work and Derivative Works thereof.\r\n\r\n      \"Contribution\" shall mean any work of authorship, including\r\n      the original version of the Work and any modifications or additions\r\n      to that Work or Derivative Works thereof, that is intentionally\r\n      submitted to Licensor for inclusion in the Work by the copyright owner\r\n      or by an individual or Legal Entity authorized to submit on behalf of\r\n      the copyright owner. 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  },
  {
    "path": "Makefile",
    "content": "\r\n# compile options (see README.md for descriptions)\r\n# 0 = disable\r\n# 1 = enable\r\n\r\n# ---- COMPILER/LINKER OPTIONS ----\r\nENABLE_CLANG                  ?= 0\r\nENABLE_SWD                    ?= 1\r\nENABLE_OVERLAY                ?= 0\r\nENABLE_LTO                    ?= 1\r\n\r\n# ---- STOCK QUANSHENG FERATURES ----\r\nENABLE_UART                   ?= 1\r\nENABLE_AIRCOPY                ?= 0\r\nENABLE_FMRADIO                = 0\r\nENABLE_NOAA                   ?= 0\r\nENABLE_VOICE                  ?= 0\r\nENABLE_VOX                    ?= 1\r\nENABLE_ALARM                  ?= 0\r\nENABLE_TX1750                 ?= 0\r\nENABLE_PWRON_PASSWORD         ?= 0\r\nENABLE_DTMF_CALLING           ?= 1\r\nENABLE_FLASHLIGHT             ?= 1\r\nENABLE_BOOTLOADER\t\t\t ?= 0\r\n# ---- CUSTOM MODS ----\r\nENABLE_BIG_FREQ               ?= 1\r\nENABLE_KEEP_MEM_NAME          ?= 1\r\nENABLE_WIDE_RX                ?= 1\r\nENABLE_TX_WHEN_AM             ?= 0\r\nENABLE_F_CAL_MENU             ?= 0\r\nENABLE_CTCSS_TAIL_PHASE_SHIFT ?= 0\r\nENABLE_BOOT_BEEPS             ?= 0\r\nENABLE_SHOW_CHARGE_LEVEL      ?= 0\r\nENABLE_REVERSE_BAT_SYMBOL     ?= 0\r\nENABLE_NO_CODE_SCAN_TIMEOUT   ?= 1\r\nENABLE_AM_FIX                 ?= 1\r\nENABLE_SQUELCH_MORE_SENSITIVE ?= 1\r\nENABLE_FASTER_CHANNEL_SCAN    ?= 1\r\nENABLE_RSSI_BAR               ?= 1\r\nENABLE_COPY_CHAN_TO_VFO       ?= 1\r\nENABLE_SPECTRUM               = 0\r\nENABLE_REDUCE_LOW_MID_TX_POWER?= 0\r\nENABLE_BYP_RAW_DEMODULATORS   ?= 0\r\nENABLE_BLMIN_TMP_OFF          ?= 0\r\nENABLE_SCAN_RANGES            ?= 1\r\nENABLE_MDC1200                = 0\r\nENABLE_MDC1200_SHOW_OP_ARG    = 0\r\nENABLE_MDC1200_SIDE_BEEP      = 0\r\nENABLE_MDC1200_CONTACT        = 0\r\nENABLE_MDC1200_EDIT\t\t\t  = 0\r\nENABLE_UART_RW_BK_REGS \t\t  ?= 0\r\nENABLE_AUDIO_BAR_DEFAULT      ?= 0\r\nENABLE_EEPROM_TYPE        \t   = 0\r\nENABLE_CHINESE_FULL \t\t   = 0\r\nENABLE_ENGLISH\t\t\t\t    =0\r\nENABLE_DOCK \t\t          ?= 0\r\nENABLE_CUSTOM_SIDEFUNCTIONS   ?= 1\r\nENABLE_SIDEFUNCTIONS_SEND     ?= 1\r\nENABLE_BLOCK                  ?= 0\r\nENABLE_PINYIN \t\t\t\t   =0\r\nENABLE_TURN ?=1\r\n# ---- DEBUGGING ----\r\nENABLE_AM_FIX_SHOW_DATA       ?= 0\r\nENABLE_AGC_SHOW_DATA          ?= 0\r\nENABLE_TIMER\t\t          ?= 0\r\nVSCODE_DEBUG\t\t\t\t   = 0\r\nENABLE_WARNING \t\t\t\t  ?= 1\r\nENABLE_MESSENGER              \t\t\t= 0\r\nENABLE_MESSENGER_DELIVERY_NOTIFICATION\t= 0\r\nENABLE_MESSENGER_NOTIFICATION\t\t\t= 0\r\nENABLE_4732 =0\r\nENABLE_4732SSB =0\r\n\r\nENABLE_DOPPLER               =0\r\n#############################################################\r\nPACKED_FILE_SUFFIX = LOSEHU132\r\nifeq ($(ENABLE_PINYIN),1)\r\n\tENABLE_CHINESE_FULL=4\r\nendif\r\n\r\nifeq ($(ENABLE_DOPPLER),1)\r\n\tENABLE_SPECTRUM=1\r\nendif\r\n\r\nifeq ($(ENABLE_CHINESE_FULL),0)\r\n    ifeq ($(ENABLE_ENGLISH),1)\r\n        $(info E)\r\n        PACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)E\r\n    endif\r\nendif\r\n\r\nifeq ($(ENABLE_CHINESE_FULL),4)\r\n\r\n    ifeq ($(ENABLE_ENGLISH),1)\r\n        $(info EK)\r\n        PACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)EK\r\n    else ifeq ($(ENABLE_PINYIN),1)\r\n        $(info H)\r\n        PACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)H\r\n    else\r\n        $(info K)\r\n        PACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)K\r\n    endif\r\nendif\r\nifeq ($(ENABLE_4732),1)\r\n\tENABLE_FMRADIO=0\r\n\tPACKED_FILE_SUFFIX := $(PACKED_FILE_SUFFIX)S\r\n    $(info SI4732)\r\n\r\nendif\r\nifeq ($(ENABLE_FMRADIO),1)\r\n\tENABLE_4732=0\r\nendif\r\n\r\n\r\nCFLAGS =\r\n\r\n\r\nifeq ($(ENABLE_MDC1200),0)\r\n\tENABLE_MDC1200_SHOW_OP_ARG    = 0\r\n\tENABLE_MDC1200_SIDE_BEEP      = 0\r\n\tENABLE_MDC1200_CONTACT        = 0\r\n\tENABLE_MDC1200_EDIT\t\t\t=0\r\nendif\r\n\r\n\r\n\r\n\r\nOPENOCD = C:/OpenOCD-20240916-0.12.0/bin/openocd.exe\r\nTARGET = firmware\r\n\r\nifeq ($(ENABLE_CLANG),1)\r\n\t# GCC's linker, ld, doesn't understand LLVM's generated bytecode\r\n\tENABLE_LTO := 0\r\nendif\r\n\r\nifeq ($(ENABLE_LTO),1)\r\n\t# can't have LTO and OVERLAY enabled at same time\r\n\tENABLE_OVERLAY := 0\r\nendif\r\n\r\nBSP_DEFINITIONS := $(wildcard hardware/*/*.def)\r\nBSP_HEADERS     := $(patsubst hardware/%,bsp/%,$(BSP_DEFINITIONS))\r\nBSP_HEADERS     := $(patsubst %.def,%.h,$(BSP_HEADERS))\r\n\r\nOBJS =\r\n# Startup files\r\nOBJS += start.o\r\nOBJS += init.o\r\nOBJS += app/messenger.o\r\n\r\nifeq ($(ENABLE_MESSENGER),1)\r\n\tOBJS += ui/messenger.o\r\nendif\r\n\r\n\r\n\r\n\r\nifeq ($(ENABLE_OVERLAY),1)\r\n\tOBJS += sram-overlay.o\r\nendif\r\nOBJS += external/printf/printf.o\r\nifeq ($(ENABLE_TIMER),1)\r\n    OBJS += driver/rtc.o\r\nendif\r\nifeq ($(ENABLE_DOPPLER),1)\r\n    OBJS += driver/rtc.o\r\nendif\r\n\r\nifeq ($(ENABLE_MDC1200),1)\r\n    OBJS += app/mdc1200.o\r\nendif\r\nifeq ($(ENABLE_DOPPLER),1)\r\n    OBJS += app/doppler.o\r\nendif\r\n# Drivers\r\nOBJS += driver/adc.o\r\nifeq ($(ENABLE_UART),1)\r\n\tOBJS += driver/aes.o\r\nendif\r\nOBJS += driver/backlight.o\r\nifeq ($(ENABLE_FMRADIO),1)\r\n\tOBJS += driver/bk1080.o\r\nendif\r\nOBJS += driver/bk4819.o\r\nifeq ($(filter $(ENABLE_AIRCOPY) $(ENABLE_UART),1),1)\r\n\tOBJS += driver/crc.o\r\nendif\r\nOBJS += driver/eeprom.o\r\nifeq ($(ENABLE_OVERLAY),1)\r\n\tOBJS += driver/flash.o\r\nendif\r\nifeq ($(ENABLE_4732),1)\r\n        OBJS += app/si.o\r\n        OBJS += driver/si473x.o\r\n        OBJS += helper/rds.o\r\n        OBJS += app/spectrum.o\r\nendif\r\nOBJS += driver/gpio.o\r\nOBJS += driver/i2c.o\r\nOBJS += driver/keyboard.o\r\nOBJS += driver/spi.o\r\nOBJS += driver/st7565.o\r\nOBJS += driver/system.o\r\nOBJS += driver/systick.o\r\nifeq ($(ENABLE_UART),1)\r\n\tOBJS += driver/uart.o\r\nendif\r\n\r\n# Main\r\nOBJS += app/action.o\r\nifeq ($(ENABLE_AIRCOPY),1)\r\n\tOBJS += app/aircopy.o\r\nendif\r\nOBJS += app/app.o\r\nOBJS += app/chFrScanner.o\r\nOBJS += app/common.o\r\nOBJS += app/dtmf.o\r\nifeq ($(ENABLE_FLASHLIGHT),1)\r\n\tOBJS += app/flashlight.o\r\nendif\r\nifeq ($(ENABLE_FMRADIO),1)\r\n\tOBJS += app/fm.o\r\nendif\r\nOBJS += app/generic.o\r\nOBJS += app/main.o\r\nOBJS += app/menu.o\r\nifeq ($(ENABLE_SPECTRUM), 1)\r\nOBJS += app/spectrum.o\r\nendif\r\nOBJS += app/scanner.o\r\nifeq ($(ENABLE_UART),1)\r\n\tOBJS += app/uart.o\r\nendif\r\nifeq ($(ENABLE_AM_FIX), 1)\r\n\tOBJS += am_fix.o\r\nendif\r\nOBJS += audio.o\r\nOBJS += bitmaps.o\r\nOBJS += board.o\r\nOBJS += dcs.o\r\nOBJS += font.o\r\nOBJS += frequencies.o\r\nOBJS += functions.o\r\nOBJS += helper/battery.o\r\nOBJS += helper/boot.o\r\nOBJS += misc.o\r\nOBJS += radio.o\r\nOBJS += scheduler.o\r\nOBJS += settings.o\r\nifeq ($(ENABLE_AIRCOPY),1)\r\n\tOBJS += ui/aircopy.o\r\nendif\r\nOBJS += ui/battery.o\r\nifeq ($(ENABLE_FMRADIO),1)\r\n\tOBJS += ui/fmradio.o\r\nendif\r\nOBJS += ui/helper.o\r\nOBJS += ui/inputbox.o\r\nifeq ($(ENABLE_PWRON_PASSWORD),1)\r\n\tOBJS += ui/lock.o\r\nendif\r\nOBJS += ui/main.o\r\nOBJS += ui/menu.o\r\nOBJS += ui/scanner.o\r\nOBJS += ui/status.o\r\nOBJS += ui/ui.o\r\nOBJS += ui/welcome.o\r\nOBJS += version.o\r\nOBJS += main.o\r\n\r\nifeq ($(OS), Windows_NT) # windows\r\n    TOP := $(dir $(realpath $(lastword $(MAKEFILE_LIST))))\r\n    RM = del /Q\r\n    FixPath = $(subst /,\\,$1)\r\n    WHERE = where\r\n    NULL_OUTPUT = nul\r\nelse # unix\r\n    TOP := $(shell pwd)\r\n    RM = rm -f\r\n    FixPath = $1\r\n    WHERE = which\r\n    NULL_OUTPUT = /dev/null\r\nendif\r\n\r\n\r\nAS = arm-none-eabi-gcc\r\nLD = arm-none-eabi-gcc\r\n\r\nifeq ($(ENABLE_CLANG),0)\r\n\tCC = arm-none-eabi-gcc\r\n# Use GCC's linker to avoid undefined symbol errors\r\n#\tLD += arm-none-eabi-gcc\r\nelse\r\n#\tMay need to adjust this to match your system\r\n\tCC = clang --sysroot=/usr/arm-none-eabi --target=arm-none-eabi\r\n#\tBloats binaries to 512MB\r\n#\tLD = ld.lld\r\nendif\r\n\r\nOBJCOPY = arm-none-eabi-objcopy\r\nSIZE = arm-none-eabi-size\r\n\r\nAUTHOR_STRING ?= LOSEHU\r\n# the user might not have/want git installed\r\n# can set own version string here (max 7 chars)\r\nifneq (, $(shell $(WHERE) git))\r\n\tVERSION_STRING ?= $(shell git describe --tags --exact-match 2>$(NULL_OUTPUT))\r\n\tifeq (, $(VERSION_STRING))\r\n    \tVERSION_STRING := $(shell git rev-parse --short HEAD)\r\n\tendif\r\nendif\r\n# If there is still no VERSION_STRING we need to make one.\r\n# It is needed for the firmware packing script\r\nifeq (, $(VERSION_STRING))\r\n\tVERSION_STRING := NOGIT\r\nendif\r\n#VERSION_STRING := 230930b\r\n\r\n\r\nASFLAGS = -c -mcpu=cortex-m0\r\nifeq ($(ENABLE_OVERLAY),1)\r\n\tASFLAGS += -DENABLE_OVERLAY\r\nendif\r\n\r\nifeq ($(ENABLE_CLANG),0)\r\n\tCFLAGS += -Os -Wall -Wno-error -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c2x -MMD -w\r\n\t#CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c11 -MMD\r\n\t#CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c99 -MMD\r\n\t#CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=gnu99 -MMD\r\n\t#CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=gnu11 -MMD\r\nelse\r\n\t# Oz needed to make it fit on flash\r\n\tCFLAGS += -Oz -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c2x -MMD\r\nendif\r\n\r\nifeq ($(ENABLE_LTO),1)\r\n\tCFLAGS += -flto=auto\r\nelse\r\n\t# We get most of the space savings if LTO creates problems\r\n\tCFLAGS += -ffunction-sections -fdata-sections\r\nendif\r\n\r\n# May cause unhelpful build failures\r\n#CFLAGS += -Wpadded\r\n\r\n# catch any and all warnings\r\nCFLAGS += -Wextra\r\n#CFLAGS += -Wpedantic\r\n\r\n# 设置PACKED_FILE_SUFFIX，根据ENABLE_CHINESE_FULL的值设置不同的后缀\r\n\r\nCFLAGS += -DENABLE_EEPROM_TYPE=$(ENABLE_EEPROM_TYPE)\r\n\r\nCFLAGS += -DENABLE_CHINESE_FULL=$(ENABLE_CHINESE_FULL)\r\nCFLAGS += -DPACKED_FILE_SUFFIX=\\\"$(PACKED_FILE_SUFFIX)\\\"\r\nCFLAGS += -DPRINTF_INCLUDE_CONFIG_H\r\nCFLAGS += -DAUTHOR_STRING=\\\"$(AUTHOR_STRING)\\\" -DVERSION_STRING=\\\"$(VERSION_STRING)\\\"\r\n\r\nifeq ($(ENABLE_MDC1200_EDIT),1)\r\nCFLAGS += -DENABLE_MDC1200_EDIT\r\nendif\r\nifeq ($(ENABLE_SPECTRUM),1)\r\nCFLAGS += -DENABLE_SPECTRUM\r\nendif\r\nifeq ($(ENABLE_MDC1200),1)\r\n    CFLAGS  += -DENABLE_MDC1200\r\nendif\r\nifeq ($(ENABLE_BOOTLOADER),1)\r\n    CFLAGS  += -DENABLE_BOOTLOADER\r\nendif\r\nifeq ($(VSCODE_DEBUG),1)\r\n    CFLAGS  += -DVSCODE_DEBUG\r\nendif\r\n\r\nifeq ($(ENABLE_WARNING),1)\r\n    CFLAGS  += -DENABLE_WARNING\r\nendif\r\n\r\nifeq ($(ENABLE_DOCK),1)\r\n    CFLAGS  += -DENABLE_DOCK\r\nendif\r\nifeq ($(ENABLE_ENGLISH),1)\r\n    CFLAGS  += -DENABLE_ENGLISH\r\nendif\r\n\r\nifeq ($(ENABLE_PINYIN),1)\r\n\tCFLAGS += -DENABLE_PINYIN\r\nendif\r\nifeq ($(ENABLE_TURN),1)\r\n\tCFLAGS += -DENABLE_TURN\r\nendif\r\n\r\nifeq ($(ENABLE_BLOCK),1)\r\n\tCFLAGS += -DENABLE_BLOCK\r\nendif\r\nifeq ($(ENABLE_MESSENGER),1)\r\n\tCFLAGS  += -DENABLE_MESSENGER\r\nendif\r\nifeq ($(ENABLE_DOPPLER),1)\r\n\tCFLAGS  += -DENABLE_DOPPLER\r\nendif\r\nifeq ($(ENABLE_4732),1)\r\n\tCFLAGS  += -DENABLE_4732\r\nendif\r\nifeq ($(ENABLE_4732SSB),1)\r\n\tCFLAGS  += -DENABLE_4732SSB\r\nendif\r\nifeq ($(ENABLE_MESSENGER_DELIVERY_NOTIFICATION),1)\r\n\tCFLAGS += -DENABLE_MESSENGER_DELIVERY_NOTIFICATION\r\nendif\r\nifeq ($(ENABLE_MESSENGER_NOTIFICATION),1)\r\n\tCFLAGS += -DENABLE_MESSENGER_NOTIFICATION\r\nendif\r\n#ifeq ($(ENABLE_CHINESE_FULL),4)\r\nifeq ($(ENABLE_CUSTOM_SIDEFUNCTIONS),1)\r\n    CFLAGS  += -DENABLE_CUSTOM_SIDEFUNCTIONS\r\nendif\r\nifeq ($(ENABLE_SIDEFUNCTIONS_SEND),1)\r\n    CFLAGS  += -DENABLE_SIDEFUNCTIONS_SEND\r\nendif\r\n#endif\r\n\r\nifeq ($(ENABLE_TIMER),1)\r\n    CFLAGS  += -DENABLE_TIMER\r\nendif\r\n\r\n\r\nifeq ($(ENABLE_MDC1200_CONTACT),1)\r\n    CFLAGS  += -DENABLE_MDC1200_CONTACT\r\nendif\r\nifeq ($(ENABLE_AUDIO_BAR_DEFAULT),1)\r\n    CFLAGS  += -DENABLE_AUDIO_BAR_DEFAULT\r\nendif\r\nifeq ($(ENABLE_CHINESE_FULL),4)\r\n\r\nifeq ($(ENABLE_EEPROM_4M),1)\r\n    CFLAGS  += -DENABLE_EEPROM_4M\r\nendif\r\nendif\r\n\r\nifeq ($(ENABLE_MDC1200_SHOW_OP_ARG),1)\r\n    CFLAGS  += -DENABLE_MDC1200_SHOW_OP_ARG\r\nendif\r\nifeq ($(ENABLE_MDC1200_SIDE_BEEP),1)\r\n    CFLAGS  += -DENABLE_MDC1200_SIDE_BEEP\r\nendif\r\nifeq ($(ENABLE_SWD),1)\r\n\tCFLAGS += -DENABLE_SWD\r\nendif\r\nifeq ($(ENABLE_OVERLAY),1)\r\n\tCFLAGS += -DENABLE_OVERLAY\r\nendif\r\nifeq ($(ENABLE_AIRCOPY),1)\r\n\tCFLAGS += -DENABLE_AIRCOPY\r\nendif\r\nifeq ($(ENABLE_FMRADIO),1)\r\n\tCFLAGS += -DENABLE_FMRADIO\r\nendif\r\nifeq ($(ENABLE_UART),1)\r\n\tCFLAGS += -DENABLE_UART\r\nendif\r\nifeq ($(ENABLE_UART_RW_BK_REGS),1)\r\n\tCFLAGS  += -DENABLE_UART_RW_BK_REGS\r\nendif\r\nifeq ($(ENABLE_BIG_FREQ),1)\r\n\tCFLAGS  += -DENABLE_BIG_FREQ\r\nendif\r\n\r\nifeq ($(ENABLE_NOAA),1)\r\n\tCFLAGS  += -DENABLE_NOAA\r\nendif\r\nifeq ($(ENABLE_VOICE),1)\r\n\tCFLAGS  += -DENABLE_VOICE\r\nendif\r\nifeq ($(ENABLE_VOX),1)\r\n\tCFLAGS  += -DENABLE_VOX\r\nendif\r\nifeq ($(ENABLE_ALARM),1)\r\n\tCFLAGS  += -DENABLE_ALARM\r\nendif\r\nifeq ($(ENABLE_TX1750),1)\r\n\tCFLAGS  += -DENABLE_TX1750\r\nendif\r\nifeq ($(ENABLE_PWRON_PASSWORD),1)\r\n\tCFLAGS  += -DENABLE_PWRON_PASSWORD\r\nendif\r\nifeq ($(ENABLE_KEEP_MEM_NAME),1)\r\n\tCFLAGS  += -DENABLE_KEEP_MEM_NAME\r\nendif\r\nifeq ($(ENABLE_WIDE_RX),1)\r\n\tCFLAGS  += -DENABLE_WIDE_RX\r\nendif\r\nifeq ($(ENABLE_TX_WHEN_AM),1)\r\n\tCFLAGS  += -DENABLE_TX_WHEN_AM\r\nendif\r\nifeq ($(ENABLE_F_CAL_MENU),1)\r\n\tCFLAGS  += -DENABLE_F_CAL_MENU\r\nendif\r\nifeq ($(ENABLE_CTCSS_TAIL_PHASE_SHIFT),1)\r\n\tCFLAGS  += -DENABLE_CTCSS_TAIL_PHASE_SHIFT\r\nendif\r\nifeq ($(ENABLE_BOOT_BEEPS),1)\r\n\tCFLAGS  += -DENABLE_BOOT_BEEPS\r\nendif\r\nifeq ($(ENABLE_SHOW_CHARGE_LEVEL),1)\r\n\tCFLAGS  += -DENABLE_SHOW_CHARGE_LEVEL\r\nendif\r\nifeq ($(ENABLE_REVERSE_BAT_SYMBOL),1)\r\n\tCFLAGS  += -DENABLE_REVERSE_BAT_SYMBOL\r\nendif\r\nifeq ($(ENABLE_NO_CODE_SCAN_TIMEOUT),1)\r\n\tCFLAGS += -DENABLE_NO_CODE_SCAN_TIMEOUT\r\nendif\r\nifeq ($(ENABLE_AM_FIX),1)\r\n\tCFLAGS  += -DENABLE_AM_FIX\r\nendif\r\nifeq ($(ENABLE_AM_FIX_SHOW_DATA),1)\r\n\tCFLAGS  += -DENABLE_AM_FIX_SHOW_DATA\r\nendif\r\nifeq ($(ENABLE_SQUELCH_MORE_SENSITIVE),1)\r\n\tCFLAGS  += -DENABLE_SQUELCH_MORE_SENSITIVE\r\nendif\r\nifeq ($(ENABLE_FASTER_CHANNEL_SCAN),1)\r\n\tCFLAGS  += -DENABLE_FASTER_CHANNEL_SCAN\r\nendif\r\nifeq ($(ENABLE_BACKLIGHT_ON_RX),1)\r\n\tCFLAGS  += -DENABLE_BACKLIGHT_ON_RX\r\nendif\r\nifeq ($(ENABLE_RSSI_BAR),1)\r\n\tCFLAGS  += -DENABLE_RSSI_BAR\r\nendif\r\nifeq ($(ENABLE_AUDIO_BAR),1)\r\n\tCFLAGS  += -DENABLE_AUDIO_BAR\r\nendif\r\nifeq ($(ENABLE_COPY_CHAN_TO_VFO),1)\r\n\tCFLAGS  += -DENABLE_COPY_CHAN_TO_VFO\r\nendif\r\nifeq ($(ENABLE_SINGLE_VFO_CHAN),1)\r\n\tCFLAGS  += -DENABLE_SINGLE_VFO_CHAN\r\nendif\r\nifeq ($(ENABLE_BAND_SCOPE),1)\r\n\tCFLAGS += -DENABLE_BAND_SCOPE\r\nendif\r\nifeq ($(ENABLE_REDUCE_LOW_MID_TX_POWER),1)\r\n\tCFLAGS  += -DENABLE_REDUCE_LOW_MID_TX_POWER\r\nendif\r\nifeq ($(ENABLE_BYP_RAW_DEMODULATORS),1)\r\n\tCFLAGS  += -DENABLE_BYP_RAW_DEMODULATORS\r\nendif\r\n\r\nifeq ($(ENABLE_SCAN_RANGES),1)\r\n\tCFLAGS  += -DENABLE_SCAN_RANGES\r\nendif\r\nifeq ($(ENABLE_DTMF_CALLING),1)\r\n\tCFLAGS  += -DENABLE_DTMF_CALLING\r\nendif\r\nifeq ($(ENABLE_AGC_SHOW_DATA),1)\r\n\tCFLAGS  += -DENABLE_AGC_SHOW_DATA\r\nendif\r\nifeq ($(ENABLE_FLASHLIGHT),1)\r\n\tCFLAGS  += -DENABLE_FLASHLIGHT\r\nendif\r\n\r\nLDFLAGS =\r\nLDFLAGS += -z noexecstack -mcpu=cortex-m0 -nostartfiles -Wl,-T,firmware.ld -Wl,--gc-sections\r\n\r\n# Use newlib-nano instead of newlib\r\nLDFLAGS += --specs=nano.specs\r\nifeq ($(VSCODE_DEBUG),1)\r\n\tASFLAGS += -g\r\n\tCFLAGS  += -g\r\n\tLDFLAGS += -g\r\nendif\r\n\r\n\r\n\r\nINC =\r\nINC += -I $(TOP)\r\nINC += -I $(TOP)/external/CMSIS_5/CMSIS/Core/Include/\r\nINC += -I $(TOP)/external/CMSIS_5/Device/ARM/ARMCM0/Include\r\n\r\nLIBS =\r\n\r\n\r\nDEPS = $(OBJS:.o=.d)\r\n\r\n\r\n\r\nifneq (, $(shell $(WHERE) python))\r\n    MY_PYTHON := python\r\nelse ifneq (, $(shell $(WHERE) python3))\r\n    MY_PYTHON := python3\r\nendif\r\n\r\nifdef MY_PYTHON\r\n    HAS_CRCMOD := $(shell $(MY_PYTHON) -c \"import crcmod\" 2>&1)\r\nendif\r\n\r\nfull:\r\n\t$(RM) *.bin\r\n\t$(MAKE) build ENABLE_CHINESE_FULL=0 ENABLE_ENGLISH=1 ENABLE_FMRADIO=1 ENABLE_MESSENGER=1 ENABLE_MESSENGER_DELIVERY_NOTIFICATION=1 ENABLE_MESSENGER_NOTIFICATION=1 ENABLE_SPECTRUM=1 ENABLE_MDC1200=1 ENABLE_MDC1200_EDIT=1 ENABLE_MDC1200_CONTACT=1\r\n\t$(MAKE) build ENABLE_CHINESE_FULL=4 ENABLE_ENGLISH=1 ENABLE_DOPPLER=1 ENABLE_SPECTRUM=1 ENABLE_FMRADIO=1 ENABLE_MDC1200=1 ENABLE_MDC1200_EDIT=1 ENABLE_MDC1200_CONTACT=1\r\n\t$(MAKE) build ENABLE_CHINESE_FULL=0 ENABLE_SPECTRUM=1 ENABLE_FMRADIO=1 ENABLE_MDC1200=1 ENABLE_MDC1200_EDIT=1 ENABLE_MDC1200_CONTACT=1\r\n\t$(MAKE) build ENABLE_CHINESE_FULL=4 ENABLE_DOPPLER=1 ENABLE_SPECTRUM=1 ENABLE_FMRADIO=1 ENABLE_MDC1200=1 ENABLE_MDC1200_EDIT=1 ENABLE_MDC1200_CONTACT=1\r\n\t$(MAKE) build ENABLE_CHINESE_FULL=4 ENABLE_DOPPLER=1 ENABLE_PINYIN=1 ENABLE_SPECTRUM=1 ENABLE_FMRADIO=1\r\n\t$(MAKE) build ENABLE_CHINESE_FULL=4 ENABLE_PINYIN=1 ENABLE_4732=1 ENABLE_4732SSB=1  ENABLE_SPECTRUM=1\r\n\r\ntest:\r\n\t$(RM) *.bin\r\n\t$(MAKE) build ENABLE_CHINESE_FULL=0   ENABLE_MDC1200=0 ENABLE_MDC1200_EDIT=0 ENABLE_MDC1200_CONTACT=0 ENABLE_FMRADIO=0 ENABLE_MESSENGER=1 ENABLE_MESSENGER_DELIVERY_NOTIFICATION=1 ENABLE_MESSENGER_NOTIFICATION=1 VSCODE_DEBUG=1\r\n\r\n\r\n\r\nbuild:clean $(TARGET)\r\n\t@$(OBJCOPY) -O binary $(TARGET) $(TARGET).bin\r\nifndef MY_PYTHON\r\n\t$(info )\r\n\t$(info )\r\nelse ifneq (,$(HAS_CRCMOD))\r\n\t$(info )\r\n\t$(info !!!!!!!! run: pip install crcmod)\r\n\t$(info )\r\nelse\r\n\t-$(MY_PYTHON) fw-pack.py $(TARGET).bin $(AUTHOR_STRING) $(PACKED_FILE_SUFFIX).bin\r\nendif\r\n\t$(SIZE) $(TARGET)\r\n\r\n\r\n\r\n\r\n\r\nall:\r\n\t$(MAKE) build\r\n\t$(MAKE) flash\r\n\r\ndebug:\r\n\t$(OPENOCD) -c \"bindto 0.0.0.0\" -f interface/stlink.cfg -f dp32g030.cfg\r\n\r\nflash:\r\n\t$(OPENOCD) -c \"bindto 0.0.0.0\" -f interface/stlink.cfg -f dp32g030.cfg -c \"write_image firmware.bin 0; shutdown;\"\r\n\r\nversion.o: .FORCE\r\n\r\n$(TARGET): $(OBJS)\r\n\t@$(LD) $(LDFLAGS) $^ -o $@ $(LIBS)\r\n\r\nbsp/dp32g030/%.h: hardware/dp32g030/%.def\r\n\r\n%.o: %.c | $(BSP_HEADERS)\r\n\t@$(CC) $(CFLAGS) $(INC) -c $< -o $@\r\n\r\n%.o: %.S\r\n\t@$(AS) $(ASFLAGS) $< -o $@\r\n\r\n.FORCE:\r\n\r\n-include $(DEPS)\r\n\r\nCUSCANSHU ?= NUL\r\nCUSTOMNAME ?= NUL\r\nfull_all:\r\n\t$(MAKE) build_all $(CUSCANSHU) CUSTOMNAME=\"$(CUSTOMNAME)\"\r\n\r\n\r\nbuild_all: clean $(TARGET)\r\n\t$(OBJCOPY) -O binary $(TARGET) $(TARGET).bin\r\nifndef MY_PYTHON\r\n\r\nelse ifneq (,$(HAS_CRCMOD))\r\n\t$(info )\r\n\t$(info !!!!!!!! run: pip install crcmod)\r\n\t$(info )\r\nelse\r\n\t-$(MY_PYTHON) fw-pack.py $(TARGET).bin $(AUTHOR_STRING) $(CUSTOMNAME).bin\r\nendif\r\n\t$(SIZE) $(TARGET)\r\n\r\n\r\n\r\n\r\nclean:\r\n\t@$(RM) $(call FixPath, $(TARGET).bin $(PACKED_FILE_SUFFIX).bin $(TARGET) )\r\n\r\nifeq ($(OS), Windows_NT) # Windows 系统\r\n\t@call del_win.bat\r\nelse # 类 Unix 系统（Linux, macOS, 等）\r\n\tchmod +x del_linux.sh\r\n\tsh ./del_linux.sh\r\nendif\r\n\r\n"
  },
  {
    "path": "README.md",
    "content": "**Read this in other languages: [English](./README_en.md), [中文](./README.md).**\r\n\r\n**语言版本: [English](./README_en.md), [中文](./README.md).**\r\n\r\n\r\n# [K5Web]( https://k5.vicicode.com/)\r\n* 支持在线固件功能编译，无需安装编译环境！！\r\n* 多普勒卫星、开机图片文字、SI4732 SSB补丁的写频方式！\r\n* 支持**创意工坊**，注册后登录可上传自定义固件和开机图片！！！\r\n\r\n请访问：[K5Web]( https://k5.vicicode.com/)\r\n\r\n# [自定义引导](https://github.com/losehu/uv-k5-bootloader-custom)\r\n* 通过创立一个引导程序加载进RAM实现固件切换\r\n* 可切换任意固件\r\n* 目前仅适用于4Mib的EEPROM，通过修改代码可轻松拓展至其他大小EEPROM\r\n  \r\n# [独立的多普勒卫星固件](https://github.com/losehu/uv-k5-firmware-custom/tree/doppler)\r\n* 可以独立解算最多40个卫星的角度，高度，速度，距离，频偏\r\n* 需要扩容2Mit及以上的EEprom\r\n* 可以显示卫星位置，带方位图\r\n\r\n# [更大固件系统](https://github.com/losehu/uv-k5-system-custom/)\r\n* 可以让UVK5加载超过64KB大小的固件，最高512MB\r\n* 更大的固件可以在一个固件中实现所有功能！！！\r\n* 开发中。。。敬请期待\r\n\r\n# 版本说明\r\n\r\n* 目前分为如下几个版本：**LOSEHUxxx**、**LOSEHUxxxK**、**LOSEHUxxxH**、**LOSEHUxxxE**、**LOSEHUxxxEK**、**LOSEHUxxxHS**\r\n* \r\n| 版本         | 语言 | EEPROM 需求 | MDC1200 | 多普勒模式 | 频谱 | 收音机 | 中文信道名 | 自定义开机中文字符 | 开机图片 | 中文输入法 | 短信 |\r\n|--------------|------|-------------|---------|------------|------|--------|------------|--------------------|----------|------------|------|\r\n| LOSEHUxxx    | 中文 | 无需扩容    | ✅      | ❌         | ✅   | ✅     | ❌         | ❌                 | ❌       | ❌         | ❌   |\r\n| LOSEHUxxxK   | 中文 | 1Mib 以上   | ✅      | ✅         | ✅   | ✅     | ✅         | ✅                 | ✅       | ❌         | ❌   |\r\n| LOSEHUxxxH   | 中文 | 2Mib 以上   | ✅      | ✅         | ✅   | ✅     | ✅         | ✅                 | ✅       | ✅         | ❌   |\r\n| LOSEHUxxxHS  | 中文 | 2Mib 以上   | ❌      | ❌         | ✅   | ✅     | ✅         | ✅                 | ✅       | ✅         | ❌   |\r\n| LOSEHUxxxE   | 英文 | 无需扩容    | ✅      | ❌         | ✅   | ✅     | ❌         | ❌                 | ❌       | ❌         | ✅   |\r\n| LOSEHUxxxEK  | 英文 | 1Mib 以上   | ✅      | ✅         | ✅   | ✅     | ❌         | ✅                 | ✅       | ❌         | ❌   |\r\n\r\n### 说明：\r\n- ✅ 表示支持该功能\r\n- ❌ 表示不支持该功能\r\n- 表格中的“收音机”功能在 LOSEHUxxxHS 版本中特指 SI4732 收音机\r\n\r\n# 多功能的K5/6固件\r\n\r\n该固件基于多个开源固件修改合并，拥有最多样性的功能\r\n\r\n* **更大容量的Eeprom芯片**\r\n* **自动多普勒频移**\r\n* **自定义开机图**\r\n* **SI4732支持**\r\n* **中/英文支持**\r\n* **中文输入法**\r\n* **GB2312中文界面、信道**\r\n* **频谱图**\r\n* **MDC1200信令、联系人**\r\n* **短信**\r\n* **信号强度指示器（ S表 ）**\r\n* **一键扫频**\r\n* **收音机**\r\n* **AM 修复**\r\n* **SSB 解调**\r\n\r\n# 操作说明(必读！！)\r\n\r\n| 按键                         | 功能                                                   |\r\n|----------------------------|------------------------------------------------------|\r\n| 🐤 **主界面下**                |                                                      |\r\n| **单按`上/下`**                | 调整频率（步长为菜单1项`步进频率`）                                  |\r\n| **单按`数字`**                 | 在频率模式下快捷输入频率                                         |\r\n| **单按`*`**                  | 输入要发送的DTMF(`A、B、C、D、*、#`对应`M、上、下、*、F`键侧键1退格,按PPT键发送) |\r\n| **长按`F`**                  | 锁定键盘                                                 |\r\n| **长按`M`**                  | 切换调制模式                                               |\r\n| **长按`*`**                  | 信道模式下是搜索列表,多次长按可切换(列表1/2/全部)，频率模式下,从当前频率开始搜索         |\r\n| **长按`0`/`F+0`**            | 打开/关闭收音机(或SI4732)                                    |\r\n| **长按`1`/`F+1`**            | 在信道模式下将当前信道复制到另一个VFO                                 |\r\n| **长按`2`/`F+2`**            | 切换A/B通道                                              |\r\n| **长按`3`/`F+3`**            | 切换频率/信道                                              |\r\n| **长按`4`/`F+4`**            | 一键对频                                                 |\r\n| **长按`5`**                  | 信道模式下切换搜索列表                                          |\r\n| **长按`5`**                  | 频率模式下设置搜索频率范围(从通道A到通道B频率),按*键开始搜索                    |\r\n| **`F+5`**                  | 频谱                                                   |\r\n| **长按`6`/`F+6`**            | 切换发射功率                                               |\r\n| **长按`7`/`F+7`**            | 声控发射开关                                               |\r\n| **长按`8`/`F+8`**            | 一键倒频                                                 |\r\n| **长按`9`/`F+9`**            | 一键即呼                                                 |\r\n| **`F+M`**                  | 打开短信                                                 |\r\n| **`F+UP`**                 | 按键音开关                                                |\r\n| **`F+Down`**               | 自动多普勒                                                |\r\n| **`F+EXIT`**               | 菜单上下颠倒                                               |\r\n| **`F+*`**                  | 扫描(数字/模拟)亚音                                          |\r\n| **短按`侧键1`**                | 监听                                                   |\r\n| **长按`侧键1`**                | DTMF解码开关                                             |\r\n| **短按`侧键2`**                | 设置宽窄带                                                |\r\n| **长按`侧键2`**                | 手电筒                                                  |\r\n| **宽窄带、DTMF解码、切换FM/AM/USB** | 集成至自定义的 **侧键与M**                                     |\r\n| 🎤 **SI4732收音机**           |                                                      |\r\n| **短按`侧键1`、短按`侧键2`**        |      SSB模式下更改bfo                                                 |\r\n| **短按`5`**                  | 输入频率，**短按`*`** 小数点 , **短按`MENU`** 确认                 |\r\n| **短按`0`**                  | 切换模式(AM/FM/SSB)，**短按`F`** 切换LSB/USB                  |\r\n| **短按`1`**、**短按`7`**        | 切换步进频率                                               |\r\n| **短按`4`**                  | 切换显示信号强度                                             |\r\n| **短按`6`**                  | 切换带宽                                                 |\r\n| **短按`2`**、**短按`8`**        | 切换ATT                                                |\r\n| **短按`3`**、**短按`9`**        |     上下搜索 ，**短按`EXIT`** 停止搜索                                       |\r\n| 🔑 **多普勒模式**               |                                                      |\r\n| **短按`5`**                  | 输入时间，**短按`*`** 小数点 , **短按`MENU`** 确认                 |\r\n| **短按`MENU`**               | 切换参数，上下调节                                            |\r\n| **短按`PPT`**                | 发射                                                   |\r\n| **短按`侧键1`**                | 开启监听                                                 |\r\n\r\n\r\n\r\n\r\n# EEPROM分布说明\r\n\r\n| EEPROM地址                               | 描述                                                        |\r\n|----------------------------------------|-----------------------------------------------------------|\r\n| 😭 **通用**                              | 版本号：LOSEHUxxx                                             |\r\n| 0X01D00~0x02000                        | 基本不变                                                      |\r\n| 0X01D00 ~ 0X01E00<br/>0X1F90 ~ 0X01FF0 | **MDC1200**-22个MDC联系人<br/>每个联系人占用16B，前2B为MDC ID，后14B为联系人名 |\r\n| 0X01FFF                                | **MDC1200**-MDC联系人数量                                      |\r\n| 0x01FFD~0x01FFE                        | **MDC1200**-MDC ID                                        |\r\n| 0x01FF8~0x01FFC                        | 侧键功能                                                      |\r\n| 0x01FFD~0x01FFE                        | **MDC1200**-MDC ID                                        |\r\n| 😱 **扩容版(K、H)**                        | 版本号：LOSEHUxxxK、LOSEHUxxxH                                 |\r\n| 0x02000~0x02012                        | 开机字符1                                                     |\r\n| 0x02012~0x02024                        | 开机字符2                                                     |\r\n| 0x02024~0x02025                        | 开机字符1、2的长度                                                |\r\n| 0x02080~0x02480                        | 开机画面，长度128（宽）*64/8=1024=0x400                             |\r\n| 0x01FFD~0x01FFE                        | **MDC1200**-MDC ID                                        |\r\n| 0x02480~0x0255C                        | gFontBigDigits，长度11*20=220=0XDC                           |\r\n| 0x0255C~0x0267C                        | gFont3x5，长度96*3=288=0X120                                 |\r\n| 0x0267C~0x028B0                        | gFontSmall，长度96*6=564=0X234                               |\r\n| 0x028B0~0x02B96                        | 菜单编码，长度53*14=742=0X2E6                                    |\r\n| 0x02BA0~0x02BA9                        | **多普勒**-卫星名称,首字符在前,最多9个英文，最后一个为'\\0'                       |\r\n| 0x02BAA~0x02BAF                        | **多普勒**-开始过境时间的年份十位个位、月、日、时、分、秒                           |\r\n| 0x02BB0~0x2BB5                         | **多普勒**-离境时间的年份十位个位、月、日、时、分、秒                             |\r\n| 0x02BB6~0x02BB7                        | **多普勒**-总过境时间（秒），低位在前，高位在后                                |\r\n| 0x02BB8~0x02BB9                        | **多普勒**-手台的发射亚音，低位在前，高位在后                                 |\r\n| 0x02BBA~0x02BBB                        | **多普勒**-手台的接收亚音，低位在前，高位在后                                 |\r\n| 0x02C00~0x02C64                        | **多普勒**-CTCSS_Options,长度50*2=100=0x64                     |\r\n| 0x02C64~0x02D34                        | **多普勒**-DCS_Options,长度104*2=208=0xD0                      |\r\n| 0x02BBC~0X02BBF                        | **多普勒**-开始过境时间与2000年1月1日UNIX时间戳的差,低位在前，高位在后               |\r\n| 0X02BC0~0X02BC5                        | **多普勒**-当前时间的年份十位个位、月、日、时、分、秒                             |\r\n| 0x02E00~0x1E1E6                        | GB2312中文字库,共6763*11*12/8=111590=0x1B3E6                   |\r\n| 0x1E200~0x20000(MAX)                   | **多普勒**-第2*n（偶数）秒卫星数据，每秒8B,包括上下行频率/10，低位在前，高位在后           |\r\n| 😰 **2Mib扩容版（H）**                      | 版本号：LOSEHUxxxH                                            |\r\n| 0x20000~0x26B00                        | **中文输入法**-拼音索引、对应字数、字的起始地址                                |\r\n| 0x26B00~0x2A330                        | **中文输入法**-拼音汉字表                                           |\r\n| 0x3C228~0x40000                        | **SI4732**-patch，长度为0x3DD8，用于SI4732的固件升级                  |\r\n| 0x3C210~0x3C21C                        | **SI4732**FM、AM、SSB频率、模式                                  |\r\n[多普勒EEPROM分布说明](https://github.com/losehu/uv-k5-firmware-chinese/blob/main/doc/多普勒eeprom详细说明.txt)\r\n\r\n\r\n# 用户功能自定义\r\n\r\n你可以通过启用/禁用各种编译选项来定制固件\r\n\r\n| 编译选项                                   | 描述                                                                            |\r\n|----------------------------------------|-------------------------------------------------------------------------------|\r\n| 🧰 **泉盛基本功能**                          | [Quansheng Basic Functions](https://github.com/egzumer/uv-k5-firmware-custom) |\r\n| ENABLE_UART                            | 串口，没有这个,你就不能通过PC配置无线电！                                                        |\r\n| ENABLE_AIRCOPY                         | AirCopy无线复制                                                                   |\r\n| ENABLE_FMRADIO                         | 收音机功能                                                                         |\r\n| ENABLE_NOAA                            | NOAA功能 (只有在美国有用)                                                              |\r\n| ENABLE_VOICE                           | 语音播报                                                                          |\r\n| ENABLE_VOX                             | VOX声控发射                                                                       |\r\n| ENABLE_ALARM                           | TX 警报                                                                         |\r\n| ENABLE_PWRON_PASSWORD                  | 开机密码                                                                          |\r\n| ENABLE_DTMF_CALLING                    | DTMF拨号功能，呼叫发起，呼叫接收，群组通话，联系人列表等                                                |\r\n| ENABLE_FLASHLIGHT                      | 启用顶部手电筒LED灯（开启，闪烁，SOS）                                                        |\r\n| ⌚ **自定义模组**                            |                                                                               |\r\n| ENABLE_BIG_FREQ                        | 大号字体的频率显示（类似官方泉盛固件）                                                           |\r\n| ENABLE_KEEP_MEM_NAME                   | 在重新保存内存频道时保持频道名称                                                              |\r\n| ENABLE_WIDE_RX                         | 全频18MHz至1300MHz接收（尽管前端/功率放大器未设计用于整个范围）                                        |\r\n| ENABLE_TX_WHEN_AM                      | 当RX设置为AM时允许TX（始终为FM）                                                          |\r\n| ENABLE_F_CAL_MENU                      | 启用收音机的隐藏频率校准菜单                                                                |\r\n| ENABLE_CTCSS_TAIL_PHASE_SHIFT          | 使用标准CTCSS尾部相移，而不是QS独有的55Hz音调方法                                                |\r\n| ENABLE_BOOT_BEEPS                      | 在启动时为用户提供音频反馈，指示音量旋钮的位置                                                       |\r\n| ENABLE_SHOW_CHARGE_LEVEL               | 在收音机充电时显示电池充电水平                                                               |\r\n| ENABLE_REVERSE_BAT_SYMBOL              | 在状态栏上镜像电池符号（正极在右侧）                                                            |\r\n| ENABLE_NO_CODE_SCAN_TIMEOUT            | 禁用32秒CTCSS/DCS扫描超时（按退出按钮而不是等待超时结束扫描                                           |\r\n| ENABLE_AM_FIX                          | 在AM模式下动态调整前端增益，以帮助防止AM解调器饱和，暂时忽略屏幕上的RSSI级别                                    |\r\n| ENABLE_SQUELCH_MORE_SENSITIVE          | 将静噪电平稍微调敏感一些                                                                  |\r\n| ENABLE_FASTER_CHANNEL_SCAN             | 增加频道扫描速度，但静噪调敏度也增加了                                                           |\r\n| ENABLE_RSSI_BAR                        | 启用以dBm/Sn为单位的RSSI条形图水平，取代小天线符号                                                |\r\n| ENABLE_AUDIO_BAR                       | 发送时显示音频条级别                                                                    |\r\n| ENABLE_COPY_CHAN_TO_VFO                | 将当前频道设置复制到频率模式。在频道模式下长按  `1 BAND`                                             |\r\n| ENABLE_SPECTRUM                        | fagci 频谱分析仪，`F` + `5 NOAA`激活                                                  |\r\n| ENABLE_REDUCE_LOW_MID_TX_POWER         | 使中等和低功率设置更低                                                                   |\r\n| ENABLE_BYP_RAW_DEMODULATORS            | 额外的BYP（旁路？）和RAW解调选项，被证明并不十分有用，但如果你想实验的话，它是存在的                                 |\r\n| ENABLE_SCAN_RANGES                     | 频率扫描的扫描范围模式                                                                   |\r\n| ENABLE_BLOCK                           | EEPROM上锁                                                                      |\r\n| ENABLE_WARNING                         | \t    BEEP提示音                                                                  |\r\n| ENABLE_CUSTOM_SIDEFUNCTIONS            | 自定义侧键功能                                                                       |\r\n| ENABLE_SIDEFUNCTIONS_SEND              | 自定义侧键功能（侧键发射功能）                                                               |\r\n| ENABLE_AUDIO_BAR_DEFAULT               | 默认语音条样式                                                                       |\r\n| 📡 **自动多普勒**                           | [Automatic Doppler](https://github.com/losehu/uv-k5-firmware-custom)          |\r\n| ENABLE_DOPPLER                         | 自动多普勒功能                                                                       |\r\n| 📧 **短信**                              | [SMS](https://github.com/joaquimorg/uv-k5-firmware-custom)                    |\r\n| ENABLE_MESSENGER                       | 发送和接收短文本消息（按键 = `F` + `MENU`）                                                 |\r\n| ENABLE_MESSENGER_DELIVERY_NOTIFICATION | 如果收到消息，则向发送方发送通知                                                              |\r\n| ENABLE_MESSENGER_NOTIFICATION          | 在收到消息时播放声音                                                                    |\r\n| 📱 **MDC1200**                         | [MDC1200](https://github.com/OneOfEleven/uv-k5-firmware-custom)               |\r\n| ENABLE_MDC1200                         | MDC1200发送功能                                                                   |\r\n| ENABLE_MDC1200_SHOW_OP_ARG             | MDC显示首尾音参数                                                                    |\r\n| ENABLE_MDC1200_SIDE_BEEP               | MDC侧音                                                                         |\r\n| ENABLE_MDC1200_CONTACT                 | MDC联系人                                                                        |\r\n| 🎛️ **DOCK**                           | [DOCK](https://github.com/nicsure/QuanshengDock)                              |\r\n| ENABLE_DOCK                            | 允许通过电脑控制手台，无屏幕显示！                                                             |\r\n| 🚫 **调试**                              |                                                                               |\r\n| ENABLE_AM_FIX_SHOW_DATA                | 显示AM修复的调试数据                                                                   |\r\n| ENABLE_AGC_SHOW_DATA                   | 显示ACG参数                                                                       |\r\n| ENABLE_UART_RW_BK_REGS                 | 添加了两个额外的命令，允许读取和写入BK4819寄存器                                                   |\r\n| ⚠️ **编译选项**                            |                                                                               |\r\n| ENABLE_CLANG                           | 实验性质，使用clang而不是gcc构建（如果启用此选项，LTO将被禁用）                                         |\r\n| ENABLE_SWD                             | 使用CPU的SWD端口，调试/编程时需要                                                          |\r\n| ENABLE_OVERLAY                         | CPU FLASH相关内容，不需要                                                             |\r\n| ENABLE_LTO                             | 减小编译固件的大小，但可能会破坏EEPROM读取（启用后OVERLAY将被禁用）                                      |\r\n\r\n# 打赏\r\n\r\n如果这个项目对您有帮助,可以考虑赞助来支持开发工作。\r\n\r\n这是：[打赏名单](https://losehu.github.io/payment-codes/#%E6%94%B6%E6%AC%BE%E7%A0%81) 非常感谢各位的支持！！！\r\n\r\n打赏码：\r\n\r\n[![打赏码](https://github.com/losehu/uv-k5-firmware-chinese/blob/main/payment/show.png)](https://losehu.github.io/payment-codes/)\r\n\r\n\r\n## Star History\r\n\r\n[![Star History Chart](https://api.star-history.com/svg?repos=losehu/uv-k5-firmware-custom&type=Date)](https://star-history.com/#losehu/uv-k5-firmware-custom&Date)\r\n\r\n"
  },
  {
    "path": "README_en.md",
    "content": "**Read this in other languages: [English](./README_en.md), [中文](./README.md).**\n\n**语言版本: [English](./README_en.md), [中文](./README.md).**\n\n# [K5Web]( https://k5.vicicode.com/)\n* Supports online firmware functionality compilation, no need to install the compilation environment!!\n* Doppler satellite, boot image text, SI4732 SSB patch frequency writing method!\n* Supports **Workshop**, register and log in to upload custom firmware and boot images!!!\n\nPlease visit: [K5Web]( https://k5.vicicode.com/)\n\n# [Custom Bootloader](https://github.com/losehu/uv-k5-bootloader-custom)\n* Achieves firmware switching by creating a bootloader loaded into RAM\n* Can switch any firmware\n* Currently only applicable to 4Mib EEPROM, can be easily expanded to other EEPROM sizes by modifying the code\n  \n# [Standalone Doppler Satellite Firmware](https://github.com/losehu/uv-k5-firmware-custom/tree/doppler)\n* Can independently calculate up to 40 satellites’ angles, altitudes, speeds, distances, and frequency offsets\n* Requires expansion of 2Mit or larger EEPROM\n* Can display satellite positions with azimuth map\n  \n# [Larger Firmware System](https://github.com/losehu/uv-k5-system-custom/)\n* Allows UVK5 to load firmware larger than 64KB, up to 512MB\n* A larger firmware can implement all functions in a single firmware!!!\n* In development... Stay tuned\n\n# Version Description\n\n* The current versions are: **LOSEHUxxx**, **LOSEHUxxxK**, **LOSEHUxxxH**, **LOSEHUxxxE**, **LOSEHUxxxEK**, **LOSEHUxxxHS**\n* \n| Version       | Language | EEPROM Requirement | MDC1200 | Doppler Mode | Spectrum | Radio | Chinese Channel Name | Custom Boot Image | Boot Image | Chinese Input Method | SMS |\n|---------------|----------|---------------------|---------|--------------|----------|-------|----------------------|-------------------|------------|----------------------|-----|\n| LOSEHUxxx     | Chinese | No expansion needed  | ✅      | ❌           | ✅       | ✅    | ❌                   | ❌                | ❌         | ❌                   | ❌  |\n| LOSEHUxxxK    | Chinese | 1Mib or above       | ✅      | ✅           | ✅       | ✅    | ✅                   | ✅                | ✅         | ❌                   | ❌  |\n| LOSEHUxxxH    | Chinese | 2Mib or above       | ✅      | ✅           | ✅       | ✅    | ✅                   | ✅                | ✅         | ✅                   | ❌  |\n| LOSEHUxxxHS   | Chinese | 2Mib or above       | ❌      | ❌           | ✅       | ✅    | ✅                   | ✅                | ✅         | ✅                   | ❌  |\n| LOSEHUxxxE    | English | No expansion needed  | ✅      | ❌           | ✅       | ✅    | ❌                   | ❌                | ❌         | ❌                   | ✅  |\n| LOSEHUxxxEK   | English | 1Mib or above       | ✅      | ✅           | ✅       | ✅    | ❌                   | ✅                | ✅         | ❌                   | ❌  |\n\n### Explanation:\n- ✅ means the feature is supported\n- ❌ means the feature is not supported\n- The \"Radio\" feature in the LOSEHUxxxHS version specifically refers to the SI4732 radio\n\n# Multi-functional K5/6 Firmware\n\nThis firmware is based on modifications and merges of multiple open-source firmware, featuring the most diverse\nfunctions:\n* **Larger EEPROM capacity**\n* **Automatic Doppler frequency shift**\n* Custom boot logo\n* **SI4732 support**\n* **Chinese/English support**\n* **Chinese input method**\n* **GB2312 Chinese interface, channels**\n* **Spectrum graph**\n* **MDC1200 signaling, contacts**\n* **SMS**\n* **Signal strength indicator (S meter)**\n* **One-touch frequency scanning**\n* **Radio receiver**\n* **AM fix**\n* **SSB demodulation**\n\n\n# Operating Instructions (Mandatory Reading!!)\n\n| Key              | Function                                                                                                                                                 |\n|-----------------|----------------------------------------------------------------------------------------------------------------------------------------------------------|\n| 🐤 **Main Interface** |                                                                                                                                                          |\n| **Single Press `Up/Down`** | Adjust frequency (step size is set by menu item `Step Frequency`)                                                                                        |\n| **Single Press `Number`** | Quickly input frequency in frequency mode                                                                                                                |\n| **Single Press `*`** | Input DTMF to be sent (`A, B, C, D, *, #` correspond to `M, Up, Down, *, F` respectively. Side Key 1 acts as backspace, press PTT key to send)           |\n| **Long Press `F`** | Keyboard Lock                                                                                                                                            |\n| **Long Press `M`** | Switch modulation mode                                                                                                                                   |\n| **Long Press `*`** | In channel mode, activates search list, multiple long presses toggle between lists (1/2/All). In frequency mode, initiates search from current frequency |\n| **Long Press `0`/`F+0`** | Open/Close radio receiver(OR SI4732)                                                                                                                     |\n| **Long Press `1`/`F+1`** | In channel mode, copies current channel to another VFO                                                                                                   |\n| **Long Press `2`/`F+2`** | Switch between A/B channels                                                                                                                              |\n| **Long Press `3`/`F+3`** | Switch between frequency/channel                                                                                                                         |\n| **Long Press `4`/`F+4`** | One-touch frequency alignment                                                                                                                            |\n| **Long Press `5`** | In channel mode, toggles search list                                                                                                                     |\n| **Long Press `5`** | In frequency mode, sets search frequency range (from channel A to channel B frequency), press * key to start search                                      |\n| **`F+5`** | Spectrum                                                                                                                                                 |\n| **Long Press `6`/`F+6`** | Switch transmit power                                                                                                                                    |\n| **Long Press `7`/`F+7`** | Voice-activated transmission switch                                                                                                                      |\n| **Long Press `8`/`F+8`** | One-touch reverse frequency                                                                                                                              |\n| **Long Press `9`/`F+9`** | One-touch call                                                                                                                                           |\n| **`F+M`** | Open SMS                                                                                                                                                 |\n| **`F+UP`** | Key tone switch                                                                                                                                          |\n| **`F+Down`** | Automatic Doppler shift                                                                                                                                  |\n| **`F+EXIT`** | Inverts menu navigation (Up/Down)                                                                                                                        |\n| **`F+*`** | Scan (Digital/Analog) sub-audio                                                                                                                          |\n| **Short Press Side Key 1** | Monitor                                                                                                                                                  |\n| **Long Press Side Key 1** | DTMF decoding switch                                                                                                                                     |\n| **Short Press Side Key 2** | Set wide/narrow band                                                                                                                                     |\n| **Long Press Side Key 2** | Flashlight                                                                                                                                               |\n|**Wide/Narrow Band, DTMF decoding, FM/AM/USB Switching**| Integrated into custom **Side Key and M**                                                                                                                |\n| 🎤 **SI4732 Radio**          |                                                      |\n| **Short press `Side Key 1`, Short press `Side Key 2`** | Change BFO in SSB mode                                      |\n| **Short press `5`**                  | Enter frequency, **short press `*`** for decimal point, **short press `MENU`** to confirm                 |\n| **Short press `0`**                  | Switch mode (AM/FM/SSB), **short press `F`** to switch LSB/USB                  |\n| **Short press `1`, Short press `7`**        | Change step frequency                                               |\n| **Short press `4`**                  | Toggle signal strength display                                             |\n| **Short press `6`**                  | Change bandwidth                                                 |\n| **Short press `2`, Short press `8`**        | Toggle ATT                                                |\n| **Short press `3`, Short press `9`**        | Search up/down, **short press `EXIT`** to stop search                                       |\n| 🔑 **Doppler Mode**               |                                                      |\n| **Short press `5`**                  | Enter time, **short press `*`** for decimal point, **short press `MENU`** to confirm                 |\n| **Short press `MENU`**               | Toggle parameters, adjust up/down                                            |\n| **Short press `PPT`**                | Transmit                                                   |\n| **Short press `Side Key 1`**                | Enable listening                                                 |\n                                                                                                                           |\n# Eeprom Layout Explanation\n\n| Eeprom Address                          | Description                                                                                                                                             |\n|----------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------|\n| 😭 **General**                          | Version: LOSEHUxxx                                                                                                                                      |\n| 0X01D00~0x02000                        | Rarely changed                                                                                                                                          |\n| 0X01D00 ~ 0X01E00<br/>0X1F90 ~ 0X01FF0 | **MDC1200** - 22 MDC contacts<br/>Each contact occupies 16B, with the first 2B being MDC ID and the next 14B being contact name                         |\n| 0X01FFF                                | **MDC1200** - Number of MDC contacts                                                                                                                    |\n| 0x01FFD~0x01FFE                        | **MDC1200** - MDC ID                                                                                                                                    |\n| 0x01FF8~0x01FFC                        | Side key functions                                                                                                                                      |\n| 0x01FFD~0x01FFE                        | **MDC1200** - MDC ID                                                                                                                                    |\n| 😱 **Expanded Version (K, H)**          | Version: LOSEHUxxxK, LOSEHUxxxH                                                                                                                         |\n| 0x02000~0x02012                        | Boot character 1                                                                                                                                        |\n| 0x02012~0x02024                        | Boot character 2                                                                                                                                        |\n| 0x02024~0x02025                        | Length of boot characters 1 and 2                                                                                                                       |\n| 0x02080~0x02480                        | Boot screen, length 128 (width) * 64/8 = 1024 = 0x400                                                                                                   |\n| 0x01FFD~0x01FFE                        | **MDC1200** - MDC ID                                                                                                                                    |\n| 0x02480~0x0255C                        | gFontBigDigits, length 11 * 20 = 220 = 0XDC                                                                                                             |\n| 0x0255C~0x0267C                        | gFont3x5, length 96 * 3 = 288 = 0X120                                                                                                                   |\n| 0x0267C~0x028B0                        | gFontSmall, length 96 * 6 = 564 = 0X234                                                                                                                 |\n| 0x028B0~0x02B96                        | Menu encoding, length 53 * 14 = 742 = 0X2E6                                                                                                             |\n| 0x02BA0~0x02BA9                        | **Doppler** - Satellite names, with the first character first, up to 9 English characters, the last one being '\\0'                                      |\n| 0x02BAA~0x02BAF                        | **Doppler** - Year (tens and units), month, day, hour, minute, and second of start transit time                                                         |\n| 0x02BB0~0x2BB5                         | **Doppler** - Year (tens and units), month, day, hour, minute, and second of departure time                                                             |\n| 0x02BB6~0x02BB7                        | **Doppler** - Total transit time (seconds), with the low byte first and the high byte second                                                            |\n| 0x02BB8~0x02BB9                        | **Doppler** - Transmitter sub-audio, with the low byte first and the high byte second                                                                   |\n| 0x02BBA~0x02BBB                        | **Doppler** - Receiver sub-audio, with the low byte first and the high byte second                                                                      |\n| 0x02C00~0x02C64                        | **Doppler** - CTCSS_Options, length 50 * 2 = 100 = 0x64                                                                                                 |\n| 0x02C64~0x02D34                        | **Doppler** - DCS_Options, length 104 * 2 = 208 = 0xD0                                                                                                  |\n| 0x02BBC~0X02BBF                        | **Doppler** - Difference between start transit time and UNIX timestamp of January 1, 2000, with the low byte first and the high byte second             |\n| 0X02BC0~0X02BC5                        | **Doppler** - Year (tens and units), month, day, hour, minute, and second of current time                                                               |\n| 0x02E00~0x1E1E6                        | GB2312 Chinese font library, total 6763 * 11 * 12/8 = 111590 = 0x1B3E6                                                                                  |\n| 0x1E200~0x20000(MAX)                   | **Doppler** - 2*n (even) second satellite data, 8B per second, including uplink/downlink frequency/10, with the low byte first and the high byte second |\n| 😰 **2Mib Expanded Version (H)**        | Version: LOSEHUxxxH                                                                                                                                     |\n| 0x20000~0x26B00                        | **Chinese Input Method** - Pinyin index, corresponding number of characters, starting address of characters                                             |\n| 0x26B00~0X2A330                        | **Chinese Input Method** - Pinyin Chinese character table                                                                                               |\n| 0x3C228~0x40000                        | **SI4732**-patch，Length 0x3DD8，used to update SI4732 firmware                                                                                           |\n| 0x3C210~0x3C21C                        | **SI4732**FM、AM、SSB Freq、Mode                                                                                                                           |\n[Doppler Eeprom Layout Explanation](https://github.com/losehu/uv-k5-firmware-chinese/blob/main/doc/多普勒eeprom详细说明.txt)\n\n# Examples\n\n<p float=\"left\">\n  <img src=\"/images/c1.JPG\" width=300 />\n  <img src=\"/images/c2.JPG\" width=300 />\n  <img src=\"/images/c3.JPG\" width=300 />\n  <img src=\"/images/c4.JPG\" width=300 />\n</p>\n\n# User Function Customization\n\nYou can customize the firmware by enabling/disabling various compilation options.\n\n| Compilation Option                     | Description                                                                                                                     |\n|----------------------------------------|---------------------------------------------------------------------------------------------------------------------------------|\n| 🧰 **Quansheng Basic Functions**       | [Quansheng Basic Functions](https://github.com/egzumer/uv-k5-firmware-custom)                                                   |\n| ENABLE_UART                            | UART, without this, you cannot configure the radio via PC!                                                                      |\n| ENABLE_AIRCOPY                         | AirCopy wireless copy                                                                                                           |\n| ENABLE_FMRADIO                         | FM radio function                                                                                                               |\n| ENABLE_NOAA                            | NOAA function (only useful in the US)                                                                                           |\n| ENABLE_VOICE                           | Voice broadcast                                                                                                                 |\n| ENABLE_VOX                             | VOX voice-controlled transmission                                                                                               |\n| ENABLE_ALARM                           | TX alarm                                                                                                                        |\n| ENABLE_PWRON_PASSWORD                  | Boot password                                                                                                                   |\n| ENABLE_DTMF_CALLING                    | DTMF dialing function, call initiation, call reception, group call, contact list, etc.                                          |\n| ENABLE_FLASHLIGHT                      | Enable top flashlight LED light (on, blink, SOS)                                                                                |\n| ⌚ **Custom Module**                    |                                                                                                                                 |\n| ENABLE_BIG_FREQ                        | Large font frequency display (similar to official Quansheng firmware)                                                           |\n| ENABLE_KEEP_MEM_NAME                   | Keep channel name when saving memory channel                                                                                    |\n| ENABLE_WIDE_RX                         | Receive full range from 18MHz to 1300MHz (although the front end/power amplifier is not designed for the entire range)          |\n| ENABLE_TX_WHEN_AM                      | Allow TX when RX is set to AM (always FM)                                                                                       |\n| ENABLE_F_CAL_MENU                      | Enable hidden frequency calibration menu for radio                                                                              |\n| ENABLE_CTCSS_TAIL_PHASE_SHIFT          | Use standard CTCSS tail phase shift instead of the unique QS 55Hz tone method                                                   |\n| ENABLE_BOOT_BEEPS                      | Provide audio feedback for users at startup, indicating the position of the volume knob                                         |\n| ENABLE_SHOW_CHARGE_LEVEL               | Display battery charge level while radio is charging                                                                            |\n| ENABLE_REVERSE_BAT_SYMBOL              | Mirror battery symbol in status bar (positive pole on right)                                                                    |\n| ENABLE_NO_CODE_SCAN_TIMEOUT            | Disable 32-second CTCSS/DCS scan timeout (exit button instead of waiting for timeout to end scan)                               |\n| ENABLE_AM_FIX                          | Dynamically adjust front-end gain in AM mode to help prevent AM demodulator saturation, temporarily ignore RSSI level on screen |\n| ENABLE_SQUELCH_MORE_SENSITIVE          | Slightly increase squelch sensitivity                                                                                           |\n| ENABLE_FASTER_CHANNEL_SCAN             | Increase channel scan speed, but also increase squelch sensitivity                                                              |\n| ENABLE_RSSI_BAR                        | Enable RSSI bar graph level in dBm/Sn units, instead of small antenna symbol                                                    |\n| ENABLE_AUDIO_BAR                       | Display audio bar level while transmitting                                                                                      |\n| ENABLE_COPY_CHAN_TO_VFO                | Copy current channel setting to frequency mode. Long press `1 BAND` in channel mode                                             |\n| ENABLE_SPECTRUM                        | Spectrum analyzer, activated by `F` + `5 NOAA`                                                                                  |\n| ENABLE_REDUCE_LOW_MID_TX_POWER         | Reduce mid and low power settings even lower                                                                                    |\n| ENABLE_BYP_RAW_DEMODULATORS            | Additional BYP (bypass?) and RAW demodulation options, proven not very useful, but available if you want to experiment          |\n| ENABLE_SCAN_RANGES                     | Scan range mode for frequency scanning                                                                                          |\n| ENABLE_BLOCK                           | EEPROM lock                                                                                                                     |\n| ENABLE_WARNING                         | Beep prompt                                                                                                                     |\n| ENABLE_CUSTOM_SIDEFUNCTIONS            | Custom side key function                                                                                                        |\n| ENABLE_SIDEFUNCTIONS_SEND              | Custom side key function (side key transmit function)                                                                           |\n| ENABLE_AUDIO_BAR_DEFAULT               | Default audio bar style                                                                                                         |\n| 📡 **Automatic Doppler**               | [Automatic Doppler](https://github.com/losehu/uv-k5-firmware-custom)                                                            |\n| ENABLE_DOPPLER                         | Automatic Doppler function                                                                                                      |\n| 📧 **SMS**                             | [SMS](https://github.com/joaquimorg/uv-k5-firmware-custom)                                                                      |\n| ENABLE_MESSENGER                       | Send and receive short text messages (button = `F` + `MENU`)                                                                    |\n| ENABLE_MESSENGER_DELIVERY_NOTIFICATION | Send notification to sender if message received                                                                                 |\n| ENABLE_MESSENGER_NOTIFICATION          | Play sound when message received                                                                                                |\n| 📱 **MDC1200**                         | [MDC1200](https://github.com/OneOfEleven/uv-k5-firmware-custom)                                                                 |\n| ENABLE_MDC1200                         | MDC1200 transmission function                                                                                                   |\n| ENABLE_MDC1200_SHOW_OP_ARG             | MDC display head/tail parameter                                                                                                 |\n| ENABLE_MDC1200_SIDE_BEEP               | MDC side tone                                                                                                                   |\n| ENABLE_MDC1200_CONTACT                 | MDC contact                                                                                                                     |\n| 🎛️ **DOCK**                           | [DOCK](https://github.com/nicsure/QuanshengDock)                                                                                |\n| ENABLE_DOCK                            | Allow control of the radio via PC, no screen display!                                                                           |\n| 🚫 **Debug**                           |                                                                                                                                 |\n| ENABLE_AM_FIX_SHOW_DATA                | Display debug data for AM fix                                                                                                   |\n| ENABLE_AGC_SHOW_DATA                   | Display ACG parameters                                                                                                          |\n| ENABLE_UART_RW_BK_REGS                 | Added two extra commands to read and write BK4819 registers                                                                     |\n| ⚠️ **Compilation Options**             |                                                                                                                                 |\n| ENABLE_CLANG                           | Experimental, build with clang instead of gcc (if this option is enabled, LTO will be disabled)                                 |\n| ENABLE_SWD                             | Use the CPU's SWD port, required for debugging/programming                                                                      |\n| ENABLE_OVERLAY                         | CPU FLASH-related content, not needed                                                                                           |\n| ENABLE_LTO                             | Reduce the size of the compiled firmware, but may break EEPROM reading (OVERLAY will be disabled after enabling)                |\n\n# Donations\n\nIf this project has been helpful to you, consider sponsoring to support development work.\n\n[Donation List](https://losehu.github.io/payment-codes/#%E6%94%B6%E6%AC%BE%E7%A0%81) Thank you very much for\nyour support!!!\n\nDonation Codes:\n\n[![Donation Codes](https://github.com/losehu/uv-k5-firmware-chinese/blob/main/payment/show.png)](https://losehu.github.io/payment-codes/)\n\n\n## Star History\n\n[![Star History Chart](https://api.star-history.com/svg?repos=losehu/uv-k5-firmware-custom&type=Date)](https://star-history.com/#losehu/uv-k5-firmware-custom&Date)\n"
  },
  {
    "path": "am_fix.c",
    "content": "\r\n/* Copyright 2023 OneOfEleven\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n// code to 'try' and reduce the AM demodulator saturation problem\r\n//\r\n// that is until someone works out how to properly configure the BK chip !\r\n\r\n#include <string.h>\r\n\r\n#include \"am_fix.h\"\r\n#include \"app/main.h\"\r\n#include \"board.h\"\r\n#include \"driver/bk4819.h\"\r\n//#include \"external/printf/printf.h\"\r\n#include \"frequencies.h\"\r\n#include \"functions.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n\r\n#ifdef ENABLE_AGC_SHOW_DATA\r\n#include \"ui/main.h\"\r\n#endif\r\n#ifdef ENABLE_AM_FIX\r\n\r\ntypedef struct\r\n{\r\n    uint16_t reg_val;\r\n    int8_t   gain_dB;\r\n} __attribute__((packed)) t_gain_table;\r\n\r\n// REG_10 AGC gain table\r\n//\r\n// <15:10> ???\r\n//\r\n//   <9:8> = LNA Gain Short\r\n//           3 =   0dB   < original value\r\n//           2 = -19dB   // was -11\r\n//           1 = -24dB   // was -16\r\n//           0 = -28dB   // was -19\r\n//\r\n//   <7:5> = LNA Gain\r\n//           7 =   0dB\r\n//           6 =  -2dB\r\n//           5 =  -4dB   < original value\r\n//           4 =  -6dB\r\n//           3 =  -9dB\r\n//           2 = -14dB\r\n//           1 = -19dB\r\n//           0 = -24dB\r\n//\r\n//   <4:3> = MIXER Gain\r\n//           3 =   0dB   < original value\r\n//           2 =  -3dB\r\n//           1 =  -6dB\r\n//           0 =  -8dB\r\n//\r\n//   <2:0> = PGA Gain\r\n//           7 =   0dB\r\n//           6 =  -3dB   < original value\r\n//           5 =  -6dB\r\n//           4 =  -9dB\r\n//           3 = -15dB\r\n//           2 = -21dB\r\n//           1 = -27dB\r\n//           0 = -33dB\r\n\r\n// front end register dB values\r\n//\r\n// these values need to be accurate for the code to properly/reliably switch\r\n// between table entries when adjusting the front end registers.\r\n//\r\n// these 4 tables need a measuring/calibration update\r\n//\r\n////\tstatic const int16_t lna_short_dB[] = {  -19,   -16,   -11,     0};   // was (but wrong)\r\n//\tstatic const int16_t lna_short_dB[] = { (-28), (-24), (-19),    0};   // corrected'ish\r\n//\tstatic const int16_t lna_dB[]       = { (-24), (-19), (-14), ( -9), (-6), (-4), (-2), 0};\r\n//\tstatic const int16_t mixer_dB[]     = { ( -8), ( -6), ( -3),    0};\r\n//\tstatic const int16_t pga_dB[]       = { (-33), (-27), (-21), (-15), (-9), (-6), (-3), 0};\r\n\r\n// lookup table is hugely easier than writing code to do the same\r\n//\r\n\r\n#define LOOKUP_TABLE 1\r\n\r\n#if LOOKUP_TABLE\r\nstatic const t_gain_table gain_table[] =\r\n{\r\n    {0x03BE, -7},   //  0 .. 3 5 3 6 ..   0dB  -4dB  0dB  -3dB ..  -7dB original\r\n\r\n    {0x0000,-93},   //  1 .. 0 0 0 0 .. -28dB -24dB -8dB -33dB .. -93dB\r\n    {0x0008,-91},   //  2 .. 0 0 1 0 .. -28dB -24dB -6dB -33dB .. -91dB\r\n    {0x0010,-88},   //  3 .. 0 0 2 0 .. -28dB -24dB -3dB -33dB .. -88dB\r\n    {0x0001,-87},   //  4 .. 0 0 0 1 .. -28dB -24dB -8dB -27dB .. -87dB\r\n    {0x0009,-85},   //  5 .. 0 0 1 1 .. -28dB -24dB -6dB -27dB .. -85dB\r\n    {0x0011,-82},   //  6 .. 0 0 2 1 .. -28dB -24dB -3dB -27dB .. -82dB\r\n    {0x0002,-81},   //  7 .. 0 0 0 2 .. -28dB -24dB -8dB -21dB .. -81dB\r\n    {0x000A,-79},   //  8 .. 0 0 1 2 .. -28dB -24dB -6dB -21dB .. -79dB\r\n    {0x0012,-76},   //  9 .. 0 0 2 2 .. -28dB -24dB -3dB -21dB .. -76dB\r\n    {0x0003,-75},   // 10 .. 0 0 0 3 .. -28dB -24dB -8dB -15dB .. -75dB\r\n    {0x000B,-73},   // 11 .. 0 0 1 3 .. -28dB -24dB -6dB -15dB .. -73dB\r\n    {0x0013,-70},   // 12 .. 0 0 2 3 .. -28dB -24dB -3dB -15dB .. -70dB\r\n    {0x0004,-69},   // 13 .. 0 0 0 4 .. -28dB -24dB -8dB  -9dB .. -69dB\r\n    {0x000C,-67},   // 14 .. 0 0 1 4 .. -28dB -24dB -6dB  -9dB .. -67dB\r\n    {0x000D,-64},   // 15 .. 0 0 1 5 .. -28dB -24dB -6dB  -6dB .. -64dB\r\n    {0x001C,-61},   // 16 .. 0 0 3 4 .. -28dB -24dB  0dB - 9dB .. -61dB\r\n    {0x001D,-58},   // 17 .. 0 0 3 5 .. -28dB -24dB  0dB  -6dB .. -58dB\r\n    {0x001E,-55},   // 18 .. 0 0 3 6 .. -28dB -24dB  0dB  -3dB .. -55dB\r\n    {0x001F,-52},   // 19 .. 0 0 3 7 .. -28dB -24dB  0dB   0dB .. -52dB\r\n    {0x003E,-50},   // 20 .. 0 1 3 6 .. -28dB -19dB  0dB  -3dB .. -50dB\r\n    {0x003F,-47},   // 21 .. 0 1 3 7 .. -28dB -19dB  0dB   0dB .. -47dB\r\n    {0x005E,-45},   // 22 .. 0 2 3 6 .. -28dB -14dB  0dB  -3dB .. -45dB\r\n    {0x005F,-42},   // 23 .. 0 2 3 7 .. -28dB -14dB  0dB   0dB .. -42dB\r\n    {0x007E,-40},   // 24 .. 0 3 3 6 .. -28dB  -9dB  0dB  -3dB .. -40dB\r\n    {0x007F,-37},   // 25 .. 0 3 3 7 .. -28dB  -9dB  0dB   0dB .. -37dB\r\n    {0x009F,-34},   // 26 .. 0 4 3 7 .. -28dB  -6dB  0dB   0dB .. -34dB\r\n    {0x00BF,-32},   // 27 .. 0 5 3 7 .. -28dB  -4dB  0dB   0dB .. -32dB\r\n    {0x00DF,-30},   // 28 .. 0 6 3 7 .. -28dB  -2dB  0dB   0dB .. -30dB\r\n    {0x00FF,-28},   // 29 .. 0 7 3 7 .. -28dB   0dB  0dB   0dB .. -28dB\r\n    {0x01DF,-26},   // 30 .. 1 6 3 7 .. -24dB  -2dB  0dB   0dB .. -26dB\r\n    {0x01FF,-24},   // 31 .. 1 7 3 7 .. -24dB   0dB  0dB   0dB .. -24dB\r\n    {0x02BF,-23},   // 32 .. 2 5 3 7 .. -19dB  -4dB  0dB   0dB .. -23dB\r\n    {0x02DF,-21},   // 33 .. 2 6 3 7 .. -19dB  -2dB  0dB  -0dB .. -21dB\r\n    {0x02FF,-19},   // 34 .. 2 7 3 7 .. -19dB   0dB  0dB   0dB .. -19dB\r\n    {0x035E,-17},   // 35 .. 3 2 3 6 ..   0dB -14dB  0dB  -3dB .. -17dB\r\n    {0x035F,-14},   // 36 .. 3 2 3 7 ..   0dB -14dB  0dB   0dB .. -14dB\r\n    {0x037E,-12},   // 37 .. 3 3 3 6 ..   0dB  -9dB  0dB  -3dB .. -12dB\r\n    {0x037F,-9},    // 38 .. 3 3 3 7 ..   0dB  -9dB  0dB   0dB ..  -9dB\r\n    {0x038F,-6},    // 39 .. 3 4 3 7 ..   0dB - 6dB  0dB   0dB ..  -6dB\r\n    {0x03BF,-4},    // 40 .. 3 5 3 7 ..   0dB  -4dB  0dB   0dB ..  -4dB\r\n    {0x03DF,-2},    // 41 .. 3 6 3 7 ..   0dB - 2dB  0dB   0dB ..  -2dB\r\n    {0x03FF,0}      // 42 .. 3 7 3 7 ..   0dB   0dB  0dB   0dB ..   0dB\r\n};\r\nconst uint8_t gain_table_size = ARRAY_SIZE(gain_table);\r\n#else\r\n\r\nt_gain_table gain_table[100] = {{0x03BE, -7}}; //original\r\nuint8_t gain_table_size = 0;\r\n\r\nvoid CreateTable()\r\n{\r\ntypedef union  {\r\n    struct {\r\n        uint8_t pgaIdx:3;\r\n        uint8_t mixerIdx:2;\r\n        uint8_t lnaIdx:3;\r\n        uint8_t lnaSIdx:2;\r\n    };\r\n    uint16_t __raw;\r\n} GainData;\r\n\r\n    static const int8_t lna_short_dB[] = {-28, -24, -19,  0};   // corrected'ish\r\n    static const int8_t lna_dB[]       = {-24, -19, -14,  -9, -6, -4, -2, 0};\r\n    static const int8_t mixer_dB[]     = { -8,  -6,  -3,   0};\r\n    static const int8_t pga_dB[]       = {-33, -27, -21, -15, -9, -6, -3, 0};\r\n\r\n    unsigned i;\r\n    for (uint8_t lnaSIdx = 0; lnaSIdx < ARRAY_SIZE(lna_short_dB); lnaSIdx++) {\r\n        for (uint8_t lnaIdx = 0; lnaIdx < ARRAY_SIZE(lna_dB); lnaIdx++) {\r\n            for (uint8_t mixerIdx = 0; mixerIdx < ARRAY_SIZE(mixer_dB); mixerIdx++) {\r\n                for (uint8_t pgaIdx = 0; pgaIdx < ARRAY_SIZE(pga_dB); pgaIdx++) {\r\n                    int16_t db = lna_short_dB[lnaSIdx] + lna_dB[lnaIdx] + mixer_dB[mixerIdx] + pga_dB[pgaIdx];\r\n                    GainData gainData = {{\r\n                        pgaIdx,\r\n                        mixerIdx,\r\n                        lnaIdx,\r\n                        lnaSIdx,\r\n                    }};\r\n\r\n                    for (i = 1; i < ARRAY_SIZE(gain_table); i++) {\r\n                        t_gain_table * gain = &gain_table[i];\r\n                        if (db == gain->gain_dB)\r\n                            break;\r\n                        if (db > gain->gain_dB)\r\n                            continue;\r\n                        if (db < gain->gain_dB) {\r\n                            if(gain->gain_dB)\r\n                                memmove(gain + 1, gain, 100 - i);\r\n                            gain->gain_dB = db;\r\n                            gain->reg_val = gainData.__raw;\r\n                            break;\r\n                        }\r\n                        gain->gain_dB = db;\r\n                        gain->reg_val = gainData.__raw;\r\n                        break;\r\n                    }\r\n                }\r\n            }\r\n        }\r\n    }\r\n\r\n    gain_table_size = i+1;\r\n}\r\n#endif\r\n\r\n\r\n#ifdef ENABLE_AM_FIX_SHOW_DATA\r\n    // display update rate\r\n    static const unsigned int display_update_rate = 250 / 10;   // max 250ms display update rate\r\n    unsigned int counter = 0;\r\n#endif\r\n\r\nunsigned int gain_table_index[2] = {0, 0};\r\n// used simply to detect a changed gain setting\r\nunsigned int gain_table_index_prev[2] = {0, 0};\r\n// holds the previous RSSI level .. we do an average of old + new RSSI reading\r\nint16_t prev_rssi[2] = {0, 0};\r\n// to help reduce gain hunting, peak hold count down tick\r\nunsigned int hold_counter[2] = {0, 0};\r\n// -89dBm, any higher and the AM demodulator starts to saturate/clip/distort\r\nconst int16_t desired_rssi = (-89 + 160) * 2;\r\n\r\nint8_t currentGainDiff;\r\nbool enabled = true;\r\n\r\nvoid AM_fix_init(void)\r\n{\t// called at boot-up\r\n    for (int i = 0; i < 2; i++) {\r\n        gain_table_index[i] = 0;  // re-start with original QS setting\r\n    }\r\n#if !LOOKUP_TABLE\r\n    CreateTable();\r\n#endif\r\n}\r\n\r\nvoid AM_fix_reset(const unsigned vfo)\r\n{\t// reset the AM fixer upper\r\n    if (vfo > 1)\r\n        return;\r\n\r\n#ifdef ENABLE_AM_FIX_SHOW_DATA\r\n        counter = 0;\r\n#endif\r\n\r\n    prev_rssi[vfo] = 0;\r\n    hold_counter[vfo] = 0;\r\n    gain_table_index_prev[vfo] = 0;\r\n}\r\n\r\n// adjust the RX gain to try and prevent the AM demodulator from\r\n// saturating/overloading/clipping (distorted AM audio)\r\n//\r\n// we're actually doing the BK4819's job for it here, but as the chip\r\n// won't/don't do it for itself, we're left to bodging it ourself by\r\n// playing with the RF front end gain setting\r\n//\r\nvoid AM_fix_10ms(const unsigned vfo)\r\n{\r\n    if(!gSetting_AM_fix || !enabled || vfo > 1 )\r\n        return;\r\n\r\nswitch (gCurrentFunction)\r\n{\r\n        case FUNCTION_TRANSMIT:\r\n        case FUNCTION_BAND_SCOPE:\r\n        case FUNCTION_POWER_SAVE:\r\n#ifdef ENABLE_AM_FIX_SHOW_DATA\r\n            counter = display_update_rate;  // queue up a display update as soon as we switch to RX mode\r\n#endif\r\n\r\n            return;\r\ndefault:\r\nbreak;\r\n    }\r\n\r\n#ifdef ENABLE_AM_FIX_SHOW_DATA\r\n    if (counter > 0) {\r\n        if (++counter >= display_update_rate) {\t// trigger a display update\r\n            counter        = 0;\r\n            gUpdateDisplay = true;\r\n        }\r\n    }\r\n#endif\r\n\r\n    static uint32_t lastFreq[2];\r\n    if(gEeprom.VfoInfo[vfo].pRX->Frequency != lastFreq[vfo]) {\r\n        lastFreq[vfo] = gEeprom.VfoInfo[vfo].pRX->Frequency;\r\n        AM_fix_reset(vfo);\r\n    }\r\n\r\n    int16_t rssi;\r\n    {\t// sample the current RSSI level\r\n        // average it with the previous rssi (a bit of noise/spike immunity)\r\n        const int16_t new_rssi = BK4819_GetRSSI();\r\n        rssi                   = (prev_rssi[vfo] > 0) ? (prev_rssi[vfo] + new_rssi) / 2 : new_rssi;\r\n        prev_rssi[vfo]         = new_rssi;\r\n    }\r\n\r\n#ifdef ENABLE_AM_FIX_SHOW_DATA\r\n    {\r\n        static int16_t lastRssi;\r\n\r\n        if (lastRssi != rssi) { // rssi changed\r\n            lastRssi = rssi;\r\n\r\n            if (counter == 0) {\r\n                counter        = 1;\r\n                gUpdateDisplay = true; // trigger a display update\r\n            }\r\n        }\r\n    }\r\n#endif\r\n\r\n    // automatically adjust the RF RX gain\r\n\r\n    // update the gain hold counter\r\n    if (hold_counter[vfo] > 0)\r\n        hold_counter[vfo]--;\r\n\r\n    // dB difference between actual and desired RSSI level\r\n    int16_t diff_dB = (rssi - desired_rssi) / 2;\r\n\r\n    if (diff_dB > 0) {\t// decrease gain\r\n        unsigned int index = gain_table_index[vfo];   // current position we're at\r\n\r\n        if (diff_dB >= 10) {\t// jump immediately to a new gain setting\r\n            // this greatly speeds up initial gain reduction (but reduces noise/spike immunity)\r\n\r\n            const int16_t desired_gain_dB = (int16_t)gain_table[index].gain_dB - diff_dB + 8; // get no closer than 8dB (bit of noise/spike immunity)\r\n\r\n            // scan the table to see what index to jump straight too\r\n            while (index > 1)\r\n                if (gain_table[--index].gain_dB <= desired_gain_dB)\r\n                    break;\r\n        }\r\n        else\r\n        {\t// incrementally reduce the gain .. taking it slow improves noise/spike immunity\r\n            if (index > 1)\r\n                index--;     // slow step-by-step gain reduction\r\n        }\r\n\r\n        index = MAX(1u, index);\r\n\r\n        if (gain_table_index[vfo] != index)\r\n        {\r\n            gain_table_index[vfo] = index;\r\n            hold_counter[vfo] = 30;       // 300ms hold\r\n        }\r\n    }\r\n\r\n    if (diff_dB >= -6)                    // 6dB hysterisis (help reduce gain hunting)\r\n        hold_counter[vfo] = 30;           // 300ms hold\r\n\r\n    if (hold_counter[vfo] == 0)\r\n    {\t// hold has been released, we're free to increase gain\r\n        const unsigned int index = gain_table_index[vfo] + 1;                 // move up to next gain index\r\n        gain_table_index[vfo] = MIN(index, gain_table_size - 1u);\r\n    }\r\n\r\n\r\n    {\t// apply the new settings to the front end registers\r\n        const unsigned int index = gain_table_index[vfo];\r\n\r\n        // remember the new table index\r\n        gain_table_index_prev[vfo] = index;\r\n        currentGainDiff = gain_table[0].gain_dB - gain_table[index].gain_dB;\r\n        BK4819_WriteRegister(BK4819_REG_13, gain_table[index].reg_val);\r\n#ifdef ENABLE_AGC_SHOW_DATA\r\n        UI_MAIN_PrintAGC(true);\r\n#endif\r\n    }\r\n\r\n#ifdef ENABLE_AM_FIX_SHOW_DATA\r\n    if (counter == 0) {\r\n        counter        = 1;\r\n        gUpdateDisplay = true;\r\n    }\r\n#endif\r\n}\r\n\r\n#ifdef ENABLE_AM_FIX_SHOW_DATA\r\nvoid AM_fix_print_data(const unsigned vfo, char *s) {\r\n    if (s != NULL && vfo < ARRAY_SIZE(gain_table_index)) {\r\n        const unsigned int index = gain_table_index[vfo];\r\n        sprintf(s, \"%2u %4ddB %3u\", index, gain_table[index].gain_dB, prev_rssi[vfo]);\r\n        counter = 0;\r\n    }\r\n}\r\n#endif\r\n\r\nint8_t AM_fix_get_gain_diff()\r\n{\r\n    return currentGainDiff;\r\n}\r\n\r\nvoid AM_fix_enable(bool on)\r\n{\r\n    enabled = on;\r\n}\r\n#endif\r\n"
  },
  {
    "path": "am_fix.h",
    "content": "\r\n/* Copyright 2023 OneOfEleven\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef AM_FIXH\r\n\r\n#include <stdint.h>\r\n#include <stdbool.h>\r\n\r\n#ifdef ENABLE_AM_FIX\r\nvoid AM_fix_init(void);\r\nvoid AM_fix_reset(const unsigned vfo);\r\n\r\nvoid AM_fix_10ms(const unsigned vfo);\r\n\t#ifdef ENABLE_AM_FIX_SHOW_DATA\r\n\t\tvoid AM_fix_print_data(const unsigned vfo, char *s);\r\n    #endif\r\n\r\nint8_t AM_fix_get_gain_diff();\r\n\tvoid AM_fix_enable(bool on);\r\n#endif\r\n\r\n#endif"
  },
  {
    "path": "app/action.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#  include <assert.h>\r\n#include \"app/generic.h\"\r\n\r\n#include <string.h>\r\n\r\n#ifdef ENABLE_FLASHLIGHT\r\n#include \"app/flashlight.h\"\r\n#endif\r\n\r\n#include \"app/action.h\"\r\n#include \"app/app.h\"\r\n#include \"app/chFrScanner.h\"\r\n#include \"app/common.h\"\r\n#include \"app/dtmf.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"app/scanner.h\"\r\n#include \"audio.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"driver/bk1080.h\"\r\n#endif\r\n\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/backlight.h\"\r\n#include \"functions.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/ui.h\"\r\n\r\n#if defined(ENABLE_FMRADIO)\r\nstatic void ACTION_Scan_FM(bool bRestart);\r\n#endif\r\n\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\nstatic void ACTION_AlarmOr1750(bool b1750);\r\ninline static void ACTION_Alarm() { ACTION_AlarmOr1750(false); }\r\ninline static void ACTION_1750() { ACTION_AlarmOr1750(true); };\r\n#endif\r\n\r\ninline static void ACTION_ScanRestart() { ACTION_Scan(true); };\r\n\r\nvoid (*action_opt_table[])(void) = {\r\n        [ACTION_OPT_NONE] = &FUNCTION_NOP,\r\n        [ACTION_OPT_POWER] = &ACTION_Power,\r\n        [ACTION_OPT_MONITOR] = &ACTION_Monitor,\r\n        [ACTION_OPT_SCAN] = &ACTION_ScanRestart,\r\n        [ACTION_OPT_KEYLOCK] = &COMMON_KeypadLockToggle,\r\n        [ACTION_OPT_A_B] = &COMMON_SwitchVFOs,\r\n        [ACTION_OPT_VFO_MR] = &COMMON_SwitchVFOMode,\r\n        [ACTION_OPT_SWITCH_DEMODUL] = &ACTION_SwitchDemodul,\r\n\r\n#ifdef ENABLE_FLASHLIGHT\r\n        [ACTION_OPT_FLASHLIGHT] = &ACTION_FlashLight,\r\n#else\r\n        [ACTION_OPT_FLASHLIGHT] = &FUNCTION_NOP,\r\n#endif\r\n#ifdef ENABLE_VOX\r\n        [ACTION_OPT_VOX] = &ACTION_Vox,\r\n#else\r\n        [ACTION_OPT_VOX] = &FUNCTION_NOP,\r\n#endif\r\n\r\n#ifdef ENABLE_FMRADIO\r\n        [ACTION_OPT_FM] = &ACTION_FM,\r\n#else\r\n        [ACTION_OPT_FM] = &FUNCTION_NOP,\r\n#endif\r\n\r\n#ifdef ENABLE_ALARM\r\n        [ACTION_OPT_ALARM] = &ACTION_Alarm,\r\n#else\r\n        [ACTION_OPT_ALARM] = &FUNCTION_NOP,\r\n#endif\r\n\r\n#ifdef ENABLE_TX1750\r\n        [ACTION_OPT_1750] = &ACTION_1750,\r\n#else\r\n        [ACTION_OPT_1750] = &FUNCTION_NOP,\r\n#endif\r\n\r\n#ifdef ENABLE_BLMIN_TMP_OFF\r\n        [ACTION_OPT_BLMIN_TMP_OFF] = &ACTION_BlminTmpOff,\r\n#else\r\n        [ACTION_OPT_BLMIN_TMP_OFF] = &FUNCTION_NOP,\r\n#endif\r\n\r\n        [ACTION_OPT_D_DCD] = &ACTION_D_DCD,\r\n        [ACTION_OPT_WIDTH] = &ACTION_WIDTH,\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\n        [ACTION_OPT_SEND_CURRENT] = &ACTION_SEND_CURRENT,\r\n        [ACTION_OPT_SEND_OTHER] = &ACTION_SEND_OTHER\r\n#endif\r\n};\r\n\r\nstatic_assert(ARRAY_SIZE(action_opt_table) == ACTION_OPT_LEN);\r\n\r\nvoid ACTION_Power(void) {\r\n    if (++gTxVfo->OUTPUT_POWER > OUTPUT_POWER_HIGH)\r\n        gTxVfo->OUTPUT_POWER = OUTPUT_POWER_LOW;\r\n\r\n    gRequestSaveChannel = 1;\r\n    gRequestDisplayScreen = gScreenToDisplay;\r\n#ifdef ENABLE_VOICE\r\n    gAnotherVoiceID   = VOICE_ID_POWER;\r\n#endif\r\n\r\n}\r\n\r\nvoid ACTION_Monitor(void) {\r\n\r\n    if (gCurrentFunction != FUNCTION_MONITOR) { // enable the monitor\r\n        RADIO_SelectVfos();\r\n\r\n#ifdef ENABLE_NOAA\r\n        if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE) && gIsNoaaMode)\r\n            gNoaaChannel = gRxVfo->CHANNEL_SAVE - NOAA_CHANNEL_FIRST;\r\n#endif\r\n        RADIO_SetupRegisters(true);\r\n        APP_StartListening(FUNCTION_MONITOR);\r\n        return;\r\n    }\r\n\r\n    gMonitor = false;\r\n\r\n    if (gScanStateDir != SCAN_OFF) {\r\n        gScanPauseDelayIn_10ms = scan_pause_delay_in_1_10ms;\r\n        gScheduleScanListen = false;\r\n        gScanPauseMode = true;\r\n    }\r\n\r\n#ifdef ENABLE_NOAA\r\n    if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF && gIsNoaaMode) {\r\n        gNOAA_Countdown_10ms = NOAA_countdown_10ms;\r\n        gScheduleNOAA        = false;\r\n    }\r\n#endif\r\n\r\n    RADIO_SetupRegisters(true);\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFmRadioMode) {\r\n        FM_Start();\r\n        gRequestDisplayScreen = DISPLAY_FM;\r\n    }\r\n    else\r\n#endif\r\n    gRequestDisplayScreen = gScreenToDisplay;\r\n}\r\n\r\nvoid ACTION_Scan(bool bRestart) {\r\n    (void) bRestart;\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFmRadioMode) {\r\n        ACTION_Scan_FM(bRestart);\r\n        return;\r\n    }\r\n#endif\r\n\r\n    if (SCANNER_IsScanning()) {\r\n        return;\r\n    }\r\n\r\n    // not scanning\r\n    gMonitor = false;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    DTMF_clear_RX();\r\n#endif\r\n\r\n    gDTMF_RX_live_timeout = 0;\r\n    memset(gDTMF_RX_live, 0, sizeof(gDTMF_RX_live));\r\n\r\n    RADIO_SelectVfos();\r\n#ifdef ENABLE_NOAA\r\n    if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE)) {\r\n        return;\r\n    }\r\n#endif\r\n\r\n    GUI_SelectNextDisplay(DISPLAY_MAIN);\r\n\r\n    if (gScanStateDir != SCAN_OFF) {\r\n        // already scanning\r\n\r\n        if (!IS_MR_CHANNEL(gNextMrChannel)) {\r\n            CHFRSCANNER_Stop();\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID = VOICE_ID_SCANNING_STOP;\r\n#endif\r\n            return;\r\n        }\r\n\r\n        // channel mode. Keep scanning but toggle between scan lists\r\n        gEeprom.SCAN_LIST_DEFAULT = (gEeprom.SCAN_LIST_DEFAULT + 1) % 3;\r\n\r\n        // jump to the next channel\r\n        CHFRSCANNER_Start(false, gScanStateDir);\r\n        gScanPauseDelayIn_10ms = 1;\r\n        gScheduleScanListen = false;\r\n\r\n    } else {\r\n        // start scanning\r\n        CHFRSCANNER_Start(true, SCAN_FWD);\r\n\r\n#ifdef ENABLE_VOICE\r\n        AUDIO_SetVoiceID(0, VOICE_ID_SCANNING_BEGIN);\r\n        AUDIO_PlaySingleVoice(true);\r\n#endif\r\n\r\n        // clear the other vfo's rssi level (to hide the antenna symbol)\r\n        gVFO_RSSI_bar_level[(gEeprom.RX_VFO + 1) & 1U] = 0;\r\n\r\n        // let the user see DW is not active\r\n        gDualWatchActive = false;\r\n    }\r\n\r\n    gUpdateStatus = true;\r\n}\r\n\r\n\r\nvoid ACTION_SwitchDemodul(void) {\r\n    gRequestSaveChannel = 1;\r\n    gTxVfo->Modulation++;\r\n    if (gTxVfo->Modulation == MODULATION_UKNOWN)\r\n        gTxVfo->Modulation = MODULATION_FM;\r\n\r\n}\r\n\r\n\r\nvoid ACTION_Handle(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) {\r\n    if (gScreenToDisplay == DISPLAY_MAIN && gDTMF_InputMode) {\r\n        // entering DTMF code\r\n\r\n        gPttWasReleased = true;\r\n\r\n        if (Key != KEY_SIDE1 || bKeyHeld || !bKeyPressed) {\r\n            return;\r\n        }\r\n\r\n        // side1 btn pressed\r\n\r\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n        gRequestDisplayScreen = DISPLAY_MAIN;\r\n\r\n        if (gDTMF_InputBox_Index <= 0) {\r\n            // turn off DTMF input box if no codes left\r\n            gDTMF_InputMode = false;\r\n            return;\r\n        }\r\n\r\n        // DTMF codes are in the input box\r\n        gDTMF_InputBox[--gDTMF_InputBox_Index] = '-'; // delete one code\r\n\r\n#ifdef ENABLE_VOICE\r\n        gAnotherVoiceID   = VOICE_ID_CANCEL;\r\n#endif\r\n        return;\r\n    }\r\n\r\n    enum ACTION_OPT_t funcShort = ACTION_OPT_NONE;\r\n    enum ACTION_OPT_t funcLong = ACTION_OPT_NONE;\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n    switch(Key) {\r\n        case KEY_SIDE1:\r\n            funcShort = gEeprom.KEY_1_SHORT_PRESS_ACTION;\r\n            funcLong  = gEeprom.KEY_1_LONG_PRESS_ACTION;\r\n            break;\r\n        case KEY_SIDE2:\r\n            funcShort = gEeprom.KEY_2_SHORT_PRESS_ACTION;\r\n            funcLong  = gEeprom.KEY_2_LONG_PRESS_ACTION;\r\n            break;\r\n        case KEY_MENU:\r\n            funcLong  = gEeprom.KEY_M_LONG_PRESS_ACTION;\r\n            break;\r\n        default:\r\n            break;\r\n    }\r\n#else\r\n    switch (Key) {\r\n        case KEY_SIDE1:\r\n            funcShort = ACTION_OPT_MONITOR;//gEeprom.KEY_1_SHORT_PRESS_ACTION;\r\n            funcLong = ACTION_OPT_D_DCD;//gEeprom.KEY_1_LONG_PRESS_ACTION;\r\n            break;\r\n        case KEY_SIDE2:\r\n            funcShort = ACTION_OPT_WIDTH;// gEeprom.KEY_2_SHORT_PRESS_ACTION;\r\n            funcLong = ACTION_OPT_FLASHLIGHT;\r\n            break;\r\n        case KEY_MENU:\r\n            funcLong = ACTION_OPT_SWITCH_DEMODUL;//gEeprom.KEY_M_LONG_PRESS_ACTION;\r\n            break;\r\n        default:\r\n            break;\r\n    }\r\n#endif\r\n\r\n    if (!bKeyHeld && bKeyPressed) // button pushed\r\n    {\r\n        return;\r\n    }\r\n\r\n    // held or released beyond this point\r\n\r\n    if (!(bKeyHeld && !bKeyPressed)) // don't beep on released after hold\r\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n\r\n    if (bKeyHeld || bKeyPressed) // held\r\n    {\r\n        funcShort = funcLong;\r\n\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\n        if(funcShort == ACTION_OPT_SEND_CURRENT || funcShort == ACTION_OPT_SEND_OTHER){\r\n            gFlagLastVfo = gEeprom.TX_VFO;\r\n            gEeprom.TX_VFO = funcShort == ACTION_OPT_SEND_CURRENT ? gFlagLastVfo : !gFlagLastVfo;\r\n            gFlagReconfigureVfos  = true;\r\n            gFlagStopTX = true;\r\n            GENERIC_Key_PTT(bKeyPressed);\r\n        }\r\n#endif\r\n\r\n        if (!bKeyPressed) //ignore release if held\r\n            return;\r\n    }\r\n\r\n    // held or released after short press beyond this point\r\n    action_opt_table[funcShort]();\r\n//\tswitch (funcShort)\r\n//\t{\r\n//\t\tdefault:\r\n//        case   ACTION_OPT_WIDTH:\r\n//            gTxVfo->CHANNEL_BANDWIDTH=!gTxVfo->CHANNEL_BANDWIDTH;\r\n//        gRequestSaveChannel = 1;\r\n//            break;\r\n//\t\tcase ACTION_OPT_NONE:\r\n//\t\t\tbreak;\r\n//\r\n//\t\tcase ACTION_OPT_POWER:\r\n//\t\t\tACTION_Power();\r\n//\t\t\tbreak;\r\n//\t\tcase ACTION_OPT_MONITOR:\r\n//\t\t\tACTION_Monitor();\r\n//\t\t\tbreak;\r\n//\t\tcase ACTION_OPT_SCAN:\r\n//\t\t\tACTION_Scan(true);\r\n//\t\t\tbreak;\r\n//\r\n//\t\tcase ACTION_OPT_KEYLOCK:\r\n//\t\t\tCOMMON_KeypadLockToggle();\r\n//\t\t\tbreak;\r\n//\t\tcase ACTION_OPT_A_B:\r\n//\t\t\tCOMMON_SwitchVFOs();\r\n//\t\t\tbreak;\r\n//\t\tcase ACTION_OPT_VFO_MR:\r\n//\t\t\tCOMMON_SwitchVFOMode();\r\n//\t\t\tbreak;\r\n//\t\tcase ACTION_OPT_SWITCH_DEMODUL:\r\n//\t\t\tACTION_SwitchDemodul();\r\n//\t\t\tbreak;\r\n//#ifdef ENABLE_FLASHLIGHT\r\n//            case ACTION_OPT_FLASHLIGHT:\r\n//\t\t\tACTION_FlashLight();\r\n//#endif\r\n//            break;\r\n//#ifdef ENABLE_VOX\r\n//            case ACTION_OPT_VOX:\r\n//\t\t\tACTION_Vox();\r\n//#endif\r\n//            break;\r\n//#ifdef ENABLE_FMRADIO\r\n//            case ACTION_OPT_FM:\r\n//\t\t\tACTION_FM();\r\n//#endif\r\n//            break;\r\n//#ifdef ENABLE_ALARM\r\n//            case ACTION_OPT_ALARM:\r\n//\t\t\tACTION_AlarmOr1750(false);\r\n//\t\t\tbreak;\r\n//#endif\r\n//        case ACTION_OPT_1750:\r\n//#if defined(ENABLE_TX1750)\r\n//            ACTION_AlarmOr1750(true);\r\n//\t\t\tbreak;\r\n//#endif\r\n//#ifdef ENABLE_DTMF_CALLING\r\n//           \tcase ACTION_OPT_D_DCD:\r\n//\t\t\tgTxVfo->DTMF_DECODING_ENABLE = !gTxVfo->DTMF_DECODING_ENABLE;\r\n//\t\t\tDTMF_clear_RX();\r\n//\t\t\tgRequestSaveChannel = 1;\r\n//\t\t\tbreak;\r\n//\r\n//#endif\r\n//#ifdef ENABLE_BLMIN_TMP_OFF\r\n//\t\tcase ACTION_OPT_BLMIN_TMP_OFF:\r\n//\t\t\tACTION_BlminTmpOff();\r\n//\t\t\tbreak;\r\n//#endif\r\n//\t}\r\n}\r\n\r\n#ifdef ENABLE_FMRADIO\r\nvoid ACTION_FM(void)\r\n{\r\nif (gCurrentFunction != FUNCTION_TRANSMIT && gCurrentFunction != FUNCTION_MONITOR)\r\n    {\r\n        gInputBoxIndex = 0;\r\n\r\n        if (gFmRadioMode) {\r\n            FM_TurnOff();\r\n            gFlagReconfigureVfos  = true;\r\n            gRequestDisplayScreen = DISPLAY_MAIN;\r\n\r\n#ifdef ENABLE_VOX\r\n            gVoxResumeCountdown = 80;\r\n#endif\r\n            return;\r\n        }\r\n\r\n        gMonitor = false;\r\n\r\n        RADIO_SelectVfos();\r\n        RADIO_SetupRegisters(true);\r\n\r\n        FM_Start();\r\n\r\n        gRequestDisplayScreen = DISPLAY_FM;\r\n    }\r\n}\r\n\r\n\r\nstatic void ACTION_Scan_FM(bool bRestart)\r\n{\r\n    if (FUNCTION_IsRx())\r\n        return;\r\n\r\n\r\n    GUI_SelectNextDisplay(DISPLAY_FM);\r\n    gMonitor = false;\r\n\r\n    if (gFM_ScanState != FM_SCAN_OFF) {\r\n        FM_PlayAndUpdate();\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID = VOICE_ID_SCANNING_STOP;\r\n#endif\r\n        return;\r\n    }\r\n\r\n    uint16_t freq;\r\n\r\n    if (bRestart) {\r\n        gFM_AutoScan        = true;\r\n        gFM_ChannelPosition = 0;\r\n        FM_EraseChannels();\r\n        freq           = gEeprom.FM_LowerLimit;\r\n    } else {\r\n        gFM_AutoScan        = false;\r\n        gFM_ChannelPosition = 0;\r\n        freq           = gEeprom.FM_FrequencyPlaying;\r\n    }\r\n\r\n    BK1080_GetFrequencyDeviation(freq);\r\n    FM_Tune(freq, 1, bRestart);\r\n\r\n#ifdef ENABLE_VOICE\r\n    gAnotherVoiceID = VOICE_ID_SCANNING_BEGIN;\r\n#endif\r\n\r\n}\r\n\r\n#endif\r\n\r\n\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\nstatic void ACTION_AlarmOr1750(const bool b1750)\r\n{\r\n\r\n#if defined(ENABLE_ALARM)\r\n        const AlarmState_t alarm_mode = (gEeprom.ALARM_MODE == ALARM_MODE_TONE) ? ALARM_STATE_TXALARM : ALARM_STATE_SITE_ALARM;\r\n        gAlarmRunningCounter = 0;\r\n#endif\r\n\r\n#if defined(ENABLE_ALARM) && defined(ENABLE_TX1750)\r\n        gAlarmState = b1750 ? ALARM_STATE_TX1750 : alarm_mode;\r\n#elif defined(ENABLE_ALARM)\r\n        gAlarmState = alarm_mode;\r\n#else\r\n        gAlarmState = ALARM_STATE_TX1750;\r\n#endif\r\n\r\n    (void)b1750;\r\n    gInputBoxIndex = 0;\r\n\r\n    gFlagPrepareTX = gAlarmState != ALARM_STATE_OFF;\r\n\r\n    if (gScreenToDisplay != DISPLAY_MENU)      // 1of11 .. don't close the menu\r\n        gRequestDisplayScreen = DISPLAY_MAIN;\r\n\r\n}\r\n#endif\r\n\r\n\r\n#ifdef ENABLE_VOX\r\nvoid ACTION_Vox(void)\r\n{\r\n    gEeprom.VOX_SWITCH   = !gEeprom.VOX_SWITCH;\r\n    gRequestSaveSettings = true;\r\n    gFlagReconfigureVfos = true;\r\n    gUpdateStatus        = true;\r\n\r\n#ifdef ENABLE_VOICE\r\n    gAnotherVoiceID  = VOICE_ID_VOX;\r\n#endif\r\n\r\n}\r\n#endif\r\n\r\n\r\n#ifdef ENABLE_BLMIN_TMP_OFF\r\nvoid ACTION_BlminTmpOff(void)\r\n{\r\n    if(++gEeprom.BACKLIGHT_MIN_STAT == BLMIN_STAT_UNKNOWN) {\r\n        gEeprom.BACKLIGHT_MIN_STAT = BLMIN_STAT_ON;\r\n        BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MIN);\r\n    } else {\r\n        BACKLIGHT_SetBrightness(0);\r\n    }\r\n}\r\n#endif\r\n\r\nvoid ACTION_WIDTH(void) {\r\n    gRequestSaveChannel = 1;\r\n\r\n    gTxVfo->CHANNEL_BANDWIDTH = !gTxVfo->CHANNEL_BANDWIDTH;\r\n}\r\n\r\nvoid ACTION_D_DCD(void) {\r\n    gRequestSaveChannel = 1;\r\n\r\n    gTxVfo->DTMF_DECODING_ENABLE = !gTxVfo->DTMF_DECODING_ENABLE;\r\n    DTMF_clear_RX();\r\n}\r\n\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\nvoid ACTION_SEND_CURRENT(void){return;}\r\nvoid ACTION_SEND_OTHER(void){return;}\r\n#endif"
  },
  {
    "path": "app/action.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef APP_ACTION_H\r\n#define APP_ACTION_H\r\n\r\n#include \"driver/keyboard.h\"\r\n\r\n//static void ACTION_FlashLight(void)\r\nvoid ACTION_Power(void);\r\n\r\nvoid ACTION_Monitor(void);\r\n\r\nvoid ACTION_Scan(bool bRestart);\r\n\r\n#ifdef ENABLE_VOX\r\nvoid ACTION_Vox(void);\r\n#endif\r\n\r\n#ifdef ENABLE_FMRADIO\r\nvoid ACTION_FM(void);\r\n#endif\r\n\r\nvoid ACTION_SwitchDemodul(void);\r\n\r\nvoid ACTION_SwitchWidth(void);\r\n\r\nvoid ACTION_SwitchDTMFDecode(void);\r\n\r\n\r\n#ifdef ENABLE_BLMIN_TMP_OFF\r\nvoid ACTION_BlminTmpOff(void);\r\n#endif\r\n\r\nvoid ACTION_D_DCD(void);\r\n\r\nvoid ACTION_WIDTH(void);\r\n\r\nvoid ACTION_Handle(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld);\r\n\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\nvoid ACTION_SEND_CURRENT(void);\r\nvoid ACTION_SEND_OTHER(void);\r\n#endif\r\n#endif\r\n\r\n"
  },
  {
    "path": "app/aircopy.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n\r\n#include \"app/aircopy.h\"\r\n#include \"audio.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/crc.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"frequencies.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/ui.h\"\r\n\r\nstatic const uint16_t Obfuscation[8] = { 0x6C16, 0xE614, 0x912E, 0x400D, 0x3521, 0x40D5, 0x0313, 0x80E9 };\r\n\r\nAIRCOPY_State_t gAircopyState;\r\nuint16_t gAirCopyBlockNumber;\r\nuint16_t gErrorsDuringAirCopy;\r\nuint8_t gAirCopyIsSendMode;\r\n\r\nuint16_t g_FSK_Buffer[36];\r\n\r\nbool AIRCOPY_SendMessage(void)\r\n{\r\n    static uint8_t gAircopySendCountdown = 1;\r\n\r\n    if (gAircopyState != AIRCOPY_TRANSFER) {\r\n        return 1;\r\n    }\r\n\r\n    if (--gAircopySendCountdown) {\r\n        return 1;\r\n    }\r\n\r\n    g_FSK_Buffer[1] = (gAirCopyBlockNumber & 0x3FF) << 6;\r\n\r\n    EEPROM_ReadBuffer(g_FSK_Buffer[1], &g_FSK_Buffer[2], 64);\r\n\r\n    g_FSK_Buffer[34] = CRC_Calculate(&g_FSK_Buffer[1], 2 + 64);\r\n\r\n    for (unsigned int i = 0; i < 34; i++) {\r\n        g_FSK_Buffer[i + 1] ^= Obfuscation[i % 8];\r\n    }\r\n\r\n    if (++gAirCopyBlockNumber >= 0x78) {\r\n        gAircopyState = AIRCOPY_COMPLETE;\r\n    }\r\n\r\n    RADIO_SetTxParameters();\r\n\r\n    BK4819_SendFSKData(g_FSK_Buffer);\r\n    BK4819_SetupPowerAmplifier(0, 0);\r\n    BK4819_ToggleGpioOut(BK4819_GPIO1_PIN29_PA_ENABLE, false);\r\n\r\n    gAircopySendCountdown = 30;\r\n\r\n    return 0;\r\n}\r\n\r\nvoid AIRCOPY_StorePacket(void)\r\n{\r\n    if (gFSKWriteIndex < 36) {\r\n        return;\r\n    }\r\n\r\n    gFSKWriteIndex = 0;\r\n    gUpdateDisplay = true;\r\n    uint16_t Status = BK4819_ReadRegister(BK4819_REG_0B);\r\n    BK4819_PrepareFSKReceive();\r\n\r\n    // Doc says bit 4 should be 1 = CRC OK, 0 = CRC FAIL, but original firmware checks for FAIL.\r\n\r\n    if ((Status & 0x0010U) != 0 || g_FSK_Buffer[0] != 0xABCD || g_FSK_Buffer[35] != 0xDCBA) {\r\n        gErrorsDuringAirCopy++;\r\n        return;\r\n    }\r\n\r\n    for (unsigned int i = 0; i < 34; i++) {\r\n        g_FSK_Buffer[i + 1] ^= Obfuscation[i % 8];\r\n    }\r\n\r\n    uint16_t CRC = CRC_Calculate(&g_FSK_Buffer[1], 2 + 64);\r\n    if (g_FSK_Buffer[34] != CRC) {\r\n        gErrorsDuringAirCopy++;\r\n        return;\r\n    }\r\n\r\n    uint16_t Offset = g_FSK_Buffer[1];\r\n\r\n    if (Offset >= 0x1E00) {\r\n        gErrorsDuringAirCopy++;\r\n        return;\r\n    }\r\n\r\n    const uint16_t *pData = &g_FSK_Buffer[2];\r\n    for (unsigned int i = 0; i < 8; i++) {\r\n        EEPROM_WriteBuffer(Offset, pData,8);\r\n        pData += 4;\r\n        Offset += 8;\r\n    }\r\n\r\n    if (Offset == 0x1E00) {\r\n        gAircopyState = AIRCOPY_COMPLETE;\r\n    }\r\n\r\n    gAirCopyBlockNumber++;\r\n}\r\n\r\nstatic void AIRCOPY_Key_DIGITS(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld)\r\n{\r\n    if (bKeyHeld || !bKeyPressed) {\r\n        return;\r\n    }\r\n\r\n    INPUTBOX_Append(Key);\r\n\r\n    gRequestDisplayScreen = DISPLAY_AIRCOPY;\r\n\r\n    if (gInputBoxIndex < 6) {\r\n#ifdef ENABLE_VOICE\r\n        gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n        return;\r\n    }\r\n\r\n    gInputBoxIndex = 0;\r\n    uint32_t Frequency = StrToUL(INPUTBOX_GetAscii()) * 100;\r\n\r\n    for (unsigned int i = 0; i < BAND_N_ELEM; i++) {\r\n        if (Frequency < frequencyBandTable[i].lower || Frequency >= frequencyBandTable[i].upper) {\r\n            continue;\r\n        }\r\n\r\n        if (TX_freq_check(Frequency)) {\r\n            continue;\r\n        }\r\n\r\n#ifdef ENABLE_VOICE\r\n        gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n\r\n        Frequency = FREQUENCY_RoundToStep(Frequency, gRxVfo->StepFrequency);\r\n        gRxVfo->Band = i;\r\n        gRxVfo->freq_config_RX.Frequency = Frequency;\r\n        gRxVfo->freq_config_TX.Frequency = Frequency;\r\n        RADIO_ConfigureSquelchAndOutputPower(gRxVfo);\r\n        gCurrentVfo = gRxVfo;\r\n        RADIO_SetupRegisters(true);\r\n        BK4819_SetupAircopy();\r\n        BK4819_ResetFSK();\r\n        return;\r\n    }\r\n\r\n    gRequestDisplayScreen = DISPLAY_AIRCOPY;\r\n}\r\n\r\nstatic void AIRCOPY_Key_EXIT(bool bKeyPressed, bool bKeyHeld)\r\n{\r\n    if (bKeyHeld || !bKeyPressed) {\r\n        return;\r\n    }\r\n\r\n    if (gInputBoxIndex == 0) {\r\n        gFSKWriteIndex = 0;\r\n        gAirCopyBlockNumber = 0;\r\n        gInputBoxIndex = 0;\r\n        gErrorsDuringAirCopy = 0;\r\n        gAirCopyIsSendMode = 0;\r\n\r\n        BK4819_PrepareFSKReceive();\r\n\r\n        gAircopyState = AIRCOPY_TRANSFER;\r\n    } else {\r\n        gInputBox[--gInputBoxIndex] = 10;\r\n    }\r\n\r\n    gRequestDisplayScreen = DISPLAY_AIRCOPY;\r\n}\r\n\r\nstatic void AIRCOPY_Key_MENU(bool bKeyPressed, bool bKeyHeld)\r\n{\r\n    if (bKeyHeld || !bKeyPressed) {\r\n        return;\r\n    }\r\n\r\n    gFSKWriteIndex = 0;\r\n    gAirCopyBlockNumber = 0;\r\n    gInputBoxIndex = 0;\r\n    gAirCopyIsSendMode = 1;\r\n    g_FSK_Buffer[0] = 0xABCD;\r\n    g_FSK_Buffer[1] = 0;\r\n    g_FSK_Buffer[35] = 0xDCBA;\r\n\r\n    GUI_DisplayScreen();\r\n\r\n    gAircopyState = AIRCOPY_TRANSFER;\r\n}\r\n\r\nvoid AIRCOPY_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld)\r\n{\r\n    switch (Key) {\r\n    case KEY_0:\r\n    case KEY_1:\r\n    case KEY_2:\r\n    case KEY_3:\r\n    case KEY_4:\r\n    case KEY_5:\r\n    case KEY_6:\r\n    case KEY_7:\r\n    case KEY_8:\r\n    case KEY_9:\r\n        AIRCOPY_Key_DIGITS(Key, bKeyPressed, bKeyHeld);\r\n        break;\r\n    case KEY_MENU:\r\n        AIRCOPY_Key_MENU(bKeyPressed, bKeyHeld);\r\n        break;\r\n    case KEY_EXIT:\r\n        AIRCOPY_Key_EXIT(bKeyPressed, bKeyHeld);\r\n        break;\r\n    default:\r\n        break;\r\n    }\r\n}\r\n\r\n#endif"
  },
  {
    "path": "app/aircopy.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef APP_AIRCOPY_H\r\n#define APP_AIRCOPY_H\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n\r\n#include \"driver/keyboard.h\"\r\n\r\nenum AIRCOPY_State_t\r\n{\r\n    AIRCOPY_READY = 0,\r\n    AIRCOPY_TRANSFER,\r\n    AIRCOPY_COMPLETE\r\n};\r\n\r\ntypedef enum AIRCOPY_State_t AIRCOPY_State_t;\r\n\r\nextern AIRCOPY_State_t gAircopyState;\r\nextern uint16_t        gAirCopyBlockNumber;\r\nextern uint16_t        gErrorsDuringAirCopy;\r\nextern uint8_t         gAirCopyIsSendMode;\r\n\r\nextern uint16_t        g_FSK_Buffer[36];\r\n\r\nbool AIRCOPY_SendMessage(void);\r\nvoid AIRCOPY_StorePacket(void);\r\nvoid AIRCOPY_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld);\r\n\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "app/app.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include \"assert.h\"\r\n\r\n#ifdef ENABLE_FLASHLIGHT\r\n#include \"app/flashlight.h\"\r\n#endif\r\n\r\n#include <assert.h>\r\n#include <stdint.h>\r\n#include <string.h>\r\n#include \"mdc1200.h\"\r\n#include \"app/action.h\"\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n#include \"app/aircopy.h\"\r\n#endif\r\n\r\n#include \"app/app.h\"\r\n#include \"app/chFrScanner.h\"\r\n#include \"app/dtmf.h\"\r\n#include \"driver/uart.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"app/generic.h\"\r\n#include \"app/main.h\"\r\n#include \"app/menu.h\"\r\n#include \"app/scanner.h\"\r\n\r\n#ifdef ENABLE_UART\r\n#include \"app/uart.h\"\r\n#endif\r\n\r\n#include \"ARMCM0.h\"\r\n#include \"audio.h\"\r\n#include \"board.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/backlight.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"driver/bk1080.h\"\r\n#endif\r\n\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/keyboard.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"driver/system.h\"\r\n#include \"am_fix.h\"\r\n#include \"dtmf.h\"\r\n//#include \"external/printf/printf.h\"\r\n#include \"frequencies.h\"\r\n#include \"functions.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"settings.h\"\r\n\r\n#if defined(ENABLE_OVERLAY)\r\n#include \"sram-overlay.h\"\r\n#endif\r\n#ifdef ENABLE_MESSENGER\r\n#include \"app/messenger.h\"\r\n#endif\r\n#ifdef ENABLE_DOPPLER\r\n#include \"app/doppler.h\"\r\n#endif\r\n\r\n#include \"ui/battery.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/main.h\"\r\n#include \"ui/menu.h\"\r\n#include \"ui/status.h\"\r\n#include \"ui/ui.h\"\r\n#include \"messenger.h\"\r\n\r\n#ifdef ENABLE_MESSENGER_NOTIFICATION\r\nbool gPlayMSGRing = false;\r\nuint8_t gPlayMSGRingCount = 0;\r\n#endif\r\nstatic bool flagSaveVfo;\r\nstatic bool flagSaveSettings;\r\nstatic bool flagSaveChannel;\r\n\r\nstatic void ProcessKey(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld);\r\n\r\nvoid (*ProcessKeysFunctions[])(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) = {\r\n        [DISPLAY_MAIN] = &MAIN_ProcessKeys,\r\n        [DISPLAY_MENU] = &MENU_ProcessKeys,\r\n        [DISPLAY_SCANNER] = &SCANNER_ProcessKeys,\r\n\r\n#ifdef ENABLE_FMRADIO\r\n        [DISPLAY_FM] = &FM_ProcessKeys,\r\n#endif\r\n#ifdef ENABLE_MESSENGER\r\n        [DISPLAY_MSG] = &MSG_ProcessKeys,\r\n#endif\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n        [DISPLAY_AIRCOPY] = &AIRCOPY_ProcessKeys,\r\n#endif\r\n\r\n};\r\n\r\nstatic_assert(ARRAY_SIZE(ProcessKeysFunctions) == DISPLAY_N_ELEM);\r\n\r\nstatic void CheckForIncoming(void) {\r\n    if (!g_SquelchLost)\r\n        return;          // squelch is closed\r\n\r\n    // squelch is open\r\n\r\n    if (gScanStateDir == SCAN_OFF) {    // not RF scanning\r\n        if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF) {    // dual watch is disabled\r\n\r\n#ifdef ENABLE_NOAA\r\n            if (gIsNoaaMode)\r\n                {\r\n                    gNOAA_Countdown_10ms = NOAA_countdown_3_10ms;\r\n                    gScheduleNOAA        = false;\r\n                }\r\n#endif\r\n\r\n            if (gCurrentFunction != FUNCTION_INCOMING) {\r\n                FUNCTION_Select(FUNCTION_INCOMING);\r\n                //gUpdateDisplay = true;\r\n\r\n\r\n            }\r\n\r\n            return;\r\n        }\r\n\r\n        // dual watch is enabled and we're RX'ing a signal\r\n\r\n        if (gRxReceptionMode != RX_MODE_NONE) {\r\n            if (gCurrentFunction != FUNCTION_INCOMING) {\r\n                FUNCTION_Select(FUNCTION_INCOMING);\r\n                //gUpdateDisplay = true;\r\n\r\n\r\n            }\r\n            return;\r\n        }\r\n\r\n        gDualWatchCountdown_10ms = dual_watch_count_after_rx_10ms;\r\n        gScheduleDualWatch = false;\r\n\r\n        // let the user see DW is not active\r\n        gDualWatchActive = false;\r\n        gUpdateStatus = true;\r\n    } else {    // RF scanning\r\n        if (gRxReceptionMode != RX_MODE_NONE) {\r\n            if (gCurrentFunction != FUNCTION_INCOMING) {\r\n                FUNCTION_Select(FUNCTION_INCOMING);\r\n                //gUpdateDisplay = true;\r\n\r\n\r\n            }\r\n            return;\r\n        }\r\n\r\n        gScanPauseDelayIn_10ms = scan_pause_delay_in_3_10ms;\r\n        gScheduleScanListen = false;\r\n    }\r\n\r\n    gRxReceptionMode = RX_MODE_DETECTED;\r\n\r\n    if (gCurrentFunction != FUNCTION_INCOMING) {\r\n        FUNCTION_Select(FUNCTION_INCOMING);\r\n        //gUpdateDisplay = true;\r\n\r\n\r\n    }\r\n}\r\n\r\nstatic void HandleIncoming(void) {\r\n\r\n\r\n    if (!g_SquelchLost) {    // squelch is closed\r\n#ifdef ENABLE_DTMF_CALLING\r\n        if (gDTMF_RX_index > 0)\r\n            DTMF_clear_RX();\r\n#endif\r\n        if (gCurrentFunction != FUNCTION_FOREGROUND) {\r\n            FUNCTION_Select(FUNCTION_FOREGROUND); //OK\r\n            gUpdateDisplay = true;\r\n        }\r\n        return;\r\n    }\r\n\r\n    bool bFlag = (gScanStateDir == SCAN_OFF && gCurrentCodeType == CODE_TYPE_OFF);\r\n#ifdef ENABLE_NOAA\r\n    if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE) && gNOAACountdown_10ms > 0) {\r\n        gNOAACountdown_10ms = 0;\r\n        bFlag               = true;\r\n    }\r\n#endif\r\n\r\n    if (g_CTCSS_Lost && gCurrentCodeType == CODE_TYPE_CONTINUOUS_TONE) {\r\n        bFlag = true;\r\n        gFoundCTCSS = false;\r\n    }\r\n\r\n    if (g_CDCSS_Lost && gCDCSSCodeType == CDCSS_POSITIVE_CODE\r\n        && (gCurrentCodeType == CODE_TYPE_DIGITAL || gCurrentCodeType == CODE_TYPE_REVERSE_DIGITAL)) {\r\n        gFoundCDCSS = false;\r\n    } else if (!bFlag)\r\n        return;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (gScanStateDir == SCAN_OFF && (gRxVfo->DTMF_DECODING_ENABLE || gSetting_KILLED)) {\r\n\r\n        // DTMF DCD is enabled\r\n        DTMF_HandleRequest();\r\n        if (gDTMF_CallState == DTMF_CALL_STATE_NONE) {\r\n            if (gRxReceptionMode != RX_MODE_DETECTED) {\r\n                return;\r\n            }\r\n            gDualWatchCountdown_10ms = dual_watch_count_after_1_10ms;\r\n            gScheduleDualWatch       = false;\r\n\r\n            gRxReceptionMode = RX_MODE_LISTENING;\r\n\r\n            // let the user see DW is not active\r\n            gDualWatchActive = false;\r\n            gUpdateStatus    = true;\r\n\r\n            gUpdateDisplay = true;\r\n            return;\r\n        }\r\n    }\r\n#endif\r\n\r\n    APP_StartListening(gMonitor ? FUNCTION_MONITOR : FUNCTION_RECEIVE);\r\n}\r\n\r\nstatic void HandleReceive(void) {\r\n#define END_OF_RX_MODE_SKIP 0\r\n#define END_OF_RX_MODE_END  1\r\n#define END_OF_RX_MODE_TTE  2\r\n\r\n    uint8_t Mode = END_OF_RX_MODE_SKIP;\r\n\r\n    if (gFlagTailToneEliminationComplete) {\r\n        Mode = END_OF_RX_MODE_END;\r\n        goto Skip;\r\n    }\r\n\r\n    if (gScanStateDir != SCAN_OFF && IS_FREQ_CHANNEL(gNextMrChannel)) { // we are scanning in the frequency mode\r\n        if (g_SquelchLost)\r\n            return;\r\n\r\n        Mode = END_OF_RX_MODE_END;\r\n        goto Skip;\r\n    }\r\n\r\n    switch (gCurrentCodeType) {\r\n        default:\r\n        case CODE_TYPE_OFF:\r\n            break;\r\n\r\n        case CODE_TYPE_CONTINUOUS_TONE:\r\n            if (gFoundCTCSS && gFoundCTCSSCountdown_10ms == 0) {\r\n                gFoundCTCSS = false;\r\n                gFoundCDCSS = false;\r\n                Mode = END_OF_RX_MODE_END;\r\n                goto Skip;\r\n            }\r\n            break;\r\n\r\n        case CODE_TYPE_DIGITAL:\r\n        case CODE_TYPE_REVERSE_DIGITAL:\r\n            if (gFoundCDCSS && gFoundCDCSSCountdown_10ms == 0) {\r\n                gFoundCTCSS = false;\r\n                gFoundCDCSS = false;\r\n                Mode = END_OF_RX_MODE_END;\r\n                goto Skip;\r\n            }\r\n            break;\r\n    }\r\n\r\n    if (g_SquelchLost) {\r\n#ifdef ENABLE_NOAA\r\n        if (!gEndOfRxDetectedMaybe && !IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE))\r\n#else\r\n        if (!gEndOfRxDetectedMaybe)\r\n#endif\r\n        {\r\n            switch (gCurrentCodeType) {\r\n                case CODE_TYPE_OFF:\r\n                    if (gEeprom.SQUELCH_LEVEL) {\r\n                        if (g_CxCSS_TAIL_Found) {\r\n                            Mode = END_OF_RX_MODE_TTE;\r\n                            g_CxCSS_TAIL_Found = false;\r\n                        }\r\n                    }\r\n                    break;\r\n\r\n                case CODE_TYPE_CONTINUOUS_TONE:\r\n                    if (g_CTCSS_Lost) {\r\n                        gFoundCTCSS = false;\r\n                    } else if (!gFoundCTCSS) {\r\n                        gFoundCTCSS = true;\r\n                        gFoundCTCSSCountdown_10ms = 100;   // 1 sec\r\n                    }\r\n\r\n                    if (g_CxCSS_TAIL_Found) {\r\n                        Mode = END_OF_RX_MODE_TTE;\r\n                        g_CxCSS_TAIL_Found = false;\r\n                    }\r\n                    break;\r\n\r\n                case CODE_TYPE_DIGITAL:\r\n                case CODE_TYPE_REVERSE_DIGITAL:\r\n                    if (g_CDCSS_Lost && gCDCSSCodeType == CDCSS_POSITIVE_CODE) {\r\n                        gFoundCDCSS = false;\r\n                    } else if (!gFoundCDCSS) {\r\n                        gFoundCDCSS = true;\r\n                        gFoundCDCSSCountdown_10ms = 100;   // 1 sec\r\n                    }\r\n\r\n                    if (g_CxCSS_TAIL_Found) {\r\n                        if (BK4819_GetCTCType() == 1)\r\n                            Mode = END_OF_RX_MODE_TTE;\r\n\r\n                        g_CxCSS_TAIL_Found = false;\r\n                    }\r\n\r\n                    break;\r\n            }\r\n        }\r\n    } else\r\n        Mode = END_OF_RX_MODE_END;\r\n\r\n    if (!gEndOfRxDetectedMaybe &&\r\n        Mode == END_OF_RX_MODE_SKIP &&\r\n        gNextTimeslice40ms &&\r\n        gEeprom.TAIL_TONE_ELIMINATION &&\r\n        (gCurrentCodeType == CODE_TYPE_DIGITAL || gCurrentCodeType == CODE_TYPE_REVERSE_DIGITAL) &&\r\n        BK4819_GetCTCType() == 1)\r\n        Mode = END_OF_RX_MODE_TTE;\r\n    else\r\n        gNextTimeslice40ms = false;\r\n\r\n    Skip:\r\n    switch (Mode) {\r\n        case END_OF_RX_MODE_SKIP:\r\n            break;\r\n\r\n        case END_OF_RX_MODE_END:\r\n            RADIO_SetupRegisters(true);\r\n\r\n#ifdef ENABLE_NOAA\r\n            if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE))\r\n                    gNOAACountdown_10ms = 300;         // 3 sec\r\n#endif\r\n\r\n            gUpdateDisplay = true;\r\n\r\n            if (gScanStateDir != SCAN_OFF) {\r\n                switch (gEeprom.SCAN_RESUME_MODE) {\r\n                    case SCAN_RESUME_TO:\r\n                        break;\r\n\r\n                    case SCAN_RESUME_CO:\r\n                        gScanPauseDelayIn_10ms = scan_pause_delay_in_7_10ms;\r\n                        gScheduleScanListen = false;\r\n                        break;\r\n\r\n                    case SCAN_RESUME_SE:\r\n                        CHFRSCANNER_Stop();\r\n                        break;\r\n                }\r\n            }\r\n\r\n            break;\r\n\r\n        case END_OF_RX_MODE_TTE:\r\n            if (gEeprom.TAIL_TONE_ELIMINATION) {\r\n                AUDIO_AudioPathOff();\r\n\r\n                gTailToneEliminationCountdown_10ms = 20;\r\n                gFlagTailToneEliminationComplete = false;\r\n                gEndOfRxDetectedMaybe = true;\r\n                gEnableSpeaker = false;\r\n            }\r\n            break;\r\n    }\r\n}\r\n\r\nstatic void HandlePowerSave() {\r\n    if (!gRxIdleMode) {\r\n        CheckForIncoming();\r\n    }\r\n}\r\n\r\nstatic void (*HandleFunction_fn_table[])(void) = {\r\n        [FUNCTION_FOREGROUND] = &CheckForIncoming,\r\n        [FUNCTION_TRANSMIT] = &FUNCTION_NOP,\r\n        [FUNCTION_MONITOR] = &FUNCTION_NOP,\r\n        [FUNCTION_INCOMING] = &HandleIncoming,\r\n        [FUNCTION_RECEIVE] = &HandleReceive,\r\n        [FUNCTION_POWER_SAVE] = &HandlePowerSave,\r\n        [FUNCTION_BAND_SCOPE] = &FUNCTION_NOP,\r\n};\r\n\r\nstatic_assert(ARRAY_SIZE(HandleFunction_fn_table) == FUNCTION_N_ELEM);\r\n\r\nstatic void HandleFunction(void) {\r\n    HandleFunction_fn_table[gCurrentFunction]();\r\n}\r\n\r\nvoid APP_StartListening(FUNCTION_Type_t function) {\r\n    const unsigned int vfo = gEeprom.RX_VFO;\r\n    //\tconst unsigned int chan = gRxVfo->CHANNEL_SAVE;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (gSetting_KILLED)\r\n        return;\r\n#endif\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFmRadioMode)\r\n        BK1080_Init(0, false);\r\n#endif\r\n\r\n    // clear the other vfo's rssi level (to hide the antenna symbol)\r\n    gVFO_RSSI_bar_level[!vfo] = 0;\r\n    AUDIO_AudioPathOn();\r\n    gEnableSpeaker = true;\r\n\r\n    BACKLIGHT_TurnOn();\r\n\r\n    if (gScanStateDir != SCAN_OFF)\r\n        CHFRSCANNER_Found();\r\n\r\n#ifdef ENABLE_NOAA\r\n    if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE) && gIsNoaaMode) {\r\n        gRxVfo->CHANNEL_SAVE        = gNoaaChannel + NOAA_CHANNEL_FIRST;\r\n        gRxVfo->pRX->Frequency      = NoaaFrequencyTable[gNoaaChannel];\r\n        gRxVfo->pTX->Frequency      = NoaaFrequencyTable[gNoaaChannel];\r\ngEeprom.ScreenChannel[vfo] = gRxVfo->CHANNEL_SAVE;\r\n        gNOAA_Countdown_10ms        = 500;   // 5 sec\r\n        gScheduleNOAA               = false;\r\n    }\r\n#endif\r\n\r\n    if (gScanStateDir == SCAN_OFF &&\r\n        gEeprom.DUAL_WATCH != DUAL_WATCH_OFF) {    // not scanning, dual watch is enabled\r\n\r\n        gDualWatchCountdown_10ms = dual_watch_count_after_2_10ms;\r\n        gScheduleDualWatch = false;\r\n\r\n        // when crossband is active only the main VFO should be used for TX\r\n        if (gEeprom.CROSS_BAND_RX_TX == CROSS_BAND_OFF)\r\n            gRxVfoIsActive = true;\r\n\r\n        // let the user see DW is not active\r\n        gDualWatchActive = false;\r\n        gUpdateStatus = true;\r\n    }\r\n\r\n\r\n    BK4819_WriteRegister(BK4819_REG_48,\r\n                         (11u << 12) |     // ??? .. 0 to 15, doesn't seem to make any difference\r\n                         (0u << 10) |     // AF Rx Gain-1\r\n                         (gEeprom.VOLUME_GAIN << 4) |     // AF Rx Gain-2\r\n                         (gEeprom.DAC_GAIN << 0));     // AF DAC Gain (after Gain-1 and Gain-2)\r\n\r\n\r\n#ifdef ENABLE_VOICE\r\n    if (gVoiceWriteIndex == 0)       // AM/FM RX mode will be set when the voice has finished\r\n#endif\r\n    RADIO_SetModulation(gRxVfo->Modulation);  // no need, set it now\r\n\r\n    FUNCTION_Select(function);\r\n#ifdef ENABLE_FMRADIO\r\n    if (function == FUNCTION_MONITOR || gFmRadioMode)\r\n#else\r\n    if (function == FUNCTION_MONITOR)\r\n#endif\r\n    {    // squelch is disabled\r\n        if (gScreenToDisplay != DISPLAY_MENU)     // 1of11 .. don't close the menu\r\n            GUI_SelectNextDisplay(DISPLAY_MAIN);\r\n    } else\r\n        gUpdateDisplay = true;\r\n\r\n    gUpdateStatus = true;\r\n}\r\n\r\nuint32_t APP_SetFreqByStepAndLimits(VFO_Info_t *pInfo, int8_t direction, uint32_t lower, uint32_t upper) {\r\n    uint32_t Frequency = FREQUENCY_RoundToStep(pInfo->freq_config_RX.Frequency + (direction * pInfo->StepFrequency),\r\n                                               pInfo->StepFrequency);\r\n\r\n    if (Frequency >= upper)\r\n        Frequency = lower;\r\n    else if (Frequency < lower)\r\n        Frequency = FREQUENCY_RoundToStep(upper - pInfo->StepFrequency, pInfo->StepFrequency);\r\n\r\n    return Frequency;\r\n}\r\n\r\nuint32_t APP_SetFrequencyByStep(VFO_Info_t *pInfo, int8_t direction) {\r\n    return APP_SetFreqByStepAndLimits(pInfo, direction, frequencyBandTable[pInfo->Band].lower,\r\n                                      frequencyBandTable[pInfo->Band].upper);\r\n}\r\n\r\n#ifdef ENABLE_NOAA\r\nstatic void NOAA_IncreaseChannel(void)\r\n    {\r\n        if (++gNoaaChannel > 9)\r\n            gNoaaChannel = 0;\r\n    }\r\n#endif\r\n\r\nstatic void DualwatchAlternate(void) {\r\n#ifdef ENABLE_NOAA\r\n    if (gIsNoaaMode)\r\n        {\r\n            if (!IS_NOAA_CHANNEL(gEeprom.ScreenChannel[0]) || !IS_NOAA_CHANNEL(gEeprom.ScreenChannel[1]))\r\n                gEeprom.RX_VFO = (gEeprom.RX_VFO + 1) & 1;\r\n            else\r\n                gEeprom.RX_VFO = 0;\r\n\r\n            gRxVfo = &gEeprom.VfoInfo[gEeprom.RX_VFO];\r\n\r\n            if (IS_NOAA_CHANNEL(gEeprom.VfoInfo[0].CHANNEL_SAVE))\r\n                NOAA_IncreaseChannel();\r\n        }\r\n        else\r\n#endif\r\n    {    // toggle between VFO's\r\n        gEeprom.RX_VFO = !gEeprom.RX_VFO;\r\n        gRxVfo = &gEeprom.VfoInfo[gEeprom.RX_VFO];\r\n\r\n        if (!gDualWatchActive) {    // let the user see DW is active\r\n            gDualWatchActive = true;\r\n            gUpdateStatus = true;\r\n        }\r\n    }\r\n\r\n    RADIO_SetupRegisters(false);\r\n\r\n#ifdef ENABLE_NOAA\r\n    gDualWatchCountdown_10ms = gIsNoaaMode ? dual_watch_count_noaa_10ms : dual_watch_count_toggle_10ms;\r\n#else\r\n    gDualWatchCountdown_10ms = dual_watch_count_toggle_10ms;\r\n#endif\r\n}\r\n\r\nstatic void CheckRadioInterrupts(void) {\r\n    if (SCANNER_IsScanning())\r\n        return;\r\n\r\n    while (BK4819_ReadRegister(BK4819_REG_0C) & 1u) { // BK chip interrupt request\r\n        // clear interrupts\r\n        BK4819_WriteRegister(BK4819_REG_02, 0);\r\n        // fetch interrupt status bits\r\n\r\n        union {\r\n            struct {\r\n                uint16_t __UNUSED: 1;\r\n                uint16_t fskRxSync: 1;\r\n                uint16_t sqlLost: 1;\r\n                uint16_t sqlFound: 1;\r\n                uint16_t voxLost: 1;\r\n                uint16_t voxFound: 1;\r\n                uint16_t ctcssLost: 1;\r\n                uint16_t ctcssFound: 1;\r\n                uint16_t cdcssLost: 1;\r\n                uint16_t cdcssFound: 1;\r\n                uint16_t cssTailFound: 1;\r\n                uint16_t dtmf5ToneFound: 1;\r\n                uint16_t fskFifoAlmostFull: 1;\r\n                uint16_t fskRxFinied: 1;\r\n                uint16_t fskFifoAlmostEmpty: 1;\r\n                uint16_t fskTxFinied: 1;\r\n            };\r\n            uint16_t __raw;\r\n        } interrupts;\r\n\r\n        interrupts.__raw = BK4819_ReadRegister(BK4819_REG_02);\r\n\r\n        // 0 = no phase shift\r\n        // 1 = 120deg phase shift\r\n        // 2 = 180deg phase shift\r\n        // 3 = 240deg phase shift\r\n//\t\tconst uint8_t ctcss_shift = BK4819_GetCTCShift();\r\n//\t\tif (ctcss_shift > 0)\r\n//\t\t\tg_CTCSS_Lost = true;\r\n\r\n        if (interrupts.dtmf5ToneFound) {\r\n            const char c = DTMF_GetCharacter(BK4819_GetDTMF_5TONE_Code()); // save the RX'ed DTMF character\r\n            if (c != 0xff) {\r\n                if (gCurrentFunction != FUNCTION_TRANSMIT) {\r\n                    if (gSetting_live_DTMF_decoder) {\r\n                        size_t len = strlen(gDTMF_RX_live);\r\n                        if (len >= sizeof(gDTMF_RX_live) - 1) { // make room\r\n                            memmove(&gDTMF_RX_live[0], &gDTMF_RX_live[1], sizeof(gDTMF_RX_live) - 1);\r\n                            len--;\r\n                        }\r\n                        gDTMF_RX_live[len++] = c;\r\n                        gDTMF_RX_live[len] = 0;\r\n                        gDTMF_RX_live_timeout = DTMF_RX_live_timeout_500ms;  // time till we delete it\r\n                        gUpdateDisplay = true;\r\n                    }\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n                    if (gRxVfo->DTMF_DECODING_ENABLE || gSetting_KILLED) {\r\n                        if (gDTMF_RX_index >= sizeof(gDTMF_RX) - 1) { // make room\r\n                            memmove(&gDTMF_RX[0], &gDTMF_RX[1], sizeof(gDTMF_RX) - 1);\r\n                            gDTMF_RX_index--;\r\n                        }\r\n                        gDTMF_RX[gDTMF_RX_index++] = c;\r\n                        gDTMF_RX[gDTMF_RX_index]   = 0;\r\n                        gDTMF_RX_timeout           = DTMF_RX_timeout_500ms;  // time till we delete it\r\n                        gDTMF_RX_pending           = true;\r\n\r\n                        SYSTEM_DelayMs(3);//fix DTMF not reply@Yurisu\r\n                        DTMF_HandleRequest();\r\n                    }\r\n#endif\r\n                }\r\n            }\r\n        }\r\n\r\n        if (interrupts.cssTailFound)\r\n            g_CxCSS_TAIL_Found = true;\r\n\r\n        if (interrupts.cdcssLost) {\r\n            g_CDCSS_Lost = true;\r\n            gCDCSSCodeType = BK4819_GetCDCSSCodeType();\r\n        }\r\n\r\n        if (interrupts.cdcssFound)\r\n            g_CDCSS_Lost = false;\r\n\r\n        if (interrupts.ctcssLost)\r\n            g_CTCSS_Lost = true;\r\n\r\n        if (interrupts.ctcssFound)\r\n            g_CTCSS_Lost = false;\r\n\r\n#ifdef ENABLE_VOX\r\n        if (interrupts.voxLost) {\r\n            g_VOX_Lost         = true;\r\n            gVoxPauseCountdown = 10;\r\n\r\n            if (gEeprom.VOX_SWITCH) {\r\n                if (gCurrentFunction == FUNCTION_POWER_SAVE && !gRxIdleMode) {\r\n                    gPowerSave_10ms            = power_save2_10ms;\r\n                    gPowerSaveCountdownExpired = 0;\r\n                }\r\n\r\n                if (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF && (gScheduleDualWatch || gDualWatchCountdown_10ms < dual_watch_count_after_vox_10ms)) {\r\n                    gDualWatchCountdown_10ms = dual_watch_count_after_vox_10ms;\r\n                    gScheduleDualWatch = false;\r\n\r\n                    // let the user see DW is not active\r\n                    gDualWatchActive = false;\r\n                    gUpdateStatus    = true;\r\n                }\r\n            }\r\n        }\r\n\r\n        if (interrupts.voxFound) {\r\n            g_VOX_Lost         = false;\r\n            gVoxPauseCountdown = 0;\r\n        }\r\n#endif\r\n\r\n        if (interrupts.sqlLost) {\r\n            g_SquelchLost = true;\r\n            BK4819_ToggleGpioOut(BK4819_GPIO6_PIN2_GREEN, true);\r\n        }\r\n\r\n        if (interrupts.sqlFound) {\r\n            g_SquelchLost = false;\r\n            BK4819_ToggleGpioOut(BK4819_GPIO6_PIN2_GREEN, false);\r\n        }\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n        if (interrupts.fskFifoAlmostFull &&\r\n            gScreenToDisplay == DISPLAY_AIRCOPY &&\r\n            gAircopyState == AIRCOPY_TRANSFER &&\r\n            gAirCopyIsSendMode == 0)\r\n        {\r\n            for (unsigned int i = 0; i < 4; i++) {\r\n                g_FSK_Buffer[gFSKWriteIndex++] = BK4819_ReadRegister(BK4819_REG_5F);\r\n            }\r\n\r\n            AIRCOPY_StorePacket();\r\n        }\r\n#endif\r\n\r\n        //ok\r\n\r\n#if defined(ENABLE_MESSENGER) || defined(ENABLE_MDC1200)\r\n        solve_sign(interrupts.__raw);\r\n#endif\r\n\r\n\r\n    }\r\n}\r\n\r\n\r\nvoid APP_EndTransmission(bool inmediately) {\r\n    // back to RX mode\r\n    RADIO_SendEndOfTransmission();\r\n    if (gMonitor) {\r\n        //turn the monitor back on\r\n        gFlagReconfigureVfos = true;\r\n    }\r\n    if (inmediately || gEeprom.REPEATER_TAIL_TONE_ELIMINATION == 0) {\r\n        FUNCTION_Select(FUNCTION_FOREGROUND);//OK\r\n    } else {\r\n        gRTTECountdown_10ms = gEeprom.REPEATER_TAIL_TONE_ELIMINATION * 10;\r\n    }\r\n}\r\n\r\n#ifdef ENABLE_VOX\r\nstatic void HandleVox(void)\r\n{\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (gSetting_KILLED)\r\n        return;\r\n#endif\r\n\r\n    if (gVoxResumeCountdown == 0)\r\n    {\r\n        if (gVoxPauseCountdown)\r\n            return;\r\n    }\r\n    else\r\n    {\r\n        g_VOX_Lost         = false;\r\n        gVoxPauseCountdown = 0;\r\n    }\r\n\r\n#ifdef ENABLE_FMRADIO\r\n        if (gFmRadioMode)\r\n            return;\r\n#endif\r\n\r\n    if (gCurrentFunction == FUNCTION_RECEIVE || gCurrentFunction == FUNCTION_MONITOR)\r\n        return;\r\n\r\n    if (gScanStateDir != SCAN_OFF)\r\n        return;\r\n\r\n    if (gVOX_NoiseDetected)\r\n    {\r\n        if (g_VOX_Lost)\r\n            gVoxStopCountdown_10ms = vox_stop_count_down_10ms;\r\n        else if (gVoxStopCountdown_10ms == 0)\r\n            gVOX_NoiseDetected = false;\r\n\r\n        if (gCurrentFunction == FUNCTION_TRANSMIT && !gPttIsPressed && !gVOX_NoiseDetected)\r\n        {\r\n\r\n                APP_EndTransmission(false);\r\n            gUpdateStatus        = true;\r\n            gUpdateDisplay       = true;\r\n        }\r\n        return;\r\n    }\r\n\r\n    if (g_VOX_Lost)\r\n    {\r\n        gVOX_NoiseDetected = true;\r\n\r\n        if (gCurrentFunction == FUNCTION_POWER_SAVE)\r\n            FUNCTION_Select(FUNCTION_FOREGROUND); //OK\r\nif (gCurrentFunction != FUNCTION_TRANSMIT && !SerialConfigInProgress())\r\n        {\r\n#ifdef ENABLE_DTMF_CALLING\r\n            gDTMF_ReplyState = DTMF_REPLY_NONE;\r\n#endif\r\n            RADIO_PrepareTX();\r\n            gUpdateDisplay = true;\r\n        }\r\n    }\r\n}\r\n#endif\r\n\r\nvoid APP_Update(void) {\r\n#ifdef ENABLE_VOICE\r\n    if (gFlagPlayQueuedVoice) {\r\n            AUDIO_PlayQueuedVoice();\r\n            gFlagPlayQueuedVoice = false;\r\n    }\r\n#endif\r\n\r\n    if (gCurrentFunction == FUNCTION_TRANSMIT &&\r\n        (gTxTimeoutReached || SerialConfigInProgress())) {    // transmitter timed out or must de-key\r\n        gTxTimeoutReached = false;\r\n\r\n        APP_EndTransmission(true);\r\n#ifdef    ENABLE_WARNING\r\n\r\n        AUDIO_PlayBeep(BEEP_880HZ_60MS_TRIPLE_BEEP);\r\n#endif\r\n\r\n        RADIO_SetVfoState(VFO_STATE_TIMEOUT);\r\n\r\n        GUI_DisplayScreen();\r\n    }\r\n\r\n    if (gReducedService)\r\n        return;\r\n\r\n    if (gCurrentFunction != FUNCTION_TRANSMIT)\r\n        HandleFunction();\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    //\tif (gFmRadioCountdown_500ms > 0)\r\n    if (gFmRadioMode && gFmRadioCountdown_500ms > 0)    // 1of11\r\n        return;\r\n#endif\r\n\r\n#ifdef ENABLE_VOICE\r\n    if (!SCANNER_IsScanning() && gScanStateDir != SCAN_OFF && gScheduleScanListen && !gPttIsPressed && gVoiceWriteIndex == 0)\r\n#else\r\n    if (!SCANNER_IsScanning() && gScanStateDir != SCAN_OFF && gScheduleScanListen && !gPttIsPressed)\r\n#endif\r\n    {    // scanning\r\n        CHFRSCANNER_ContinueScanning();\r\n    }\r\n\r\n#ifdef ENABLE_NOAA\r\n#ifdef ENABLE_VOICE\r\n    if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF && gIsNoaaMode && gScheduleNOAA && gVoiceWriteIndex == 0)\r\n#else\r\n    if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF && gIsNoaaMode && gScheduleNOAA)\r\n#endif\r\n    {\r\n        NOAA_IncreaseChannel();\r\n        RADIO_SetupRegisters(false);\r\n\r\n        gNOAA_Countdown_10ms = 7;      // 70ms\r\n        gScheduleNOAA        = false;\r\n    }\r\n#endif\r\n\r\n    // toggle between the VFO's if dual watch is enabled\r\n    if (!SCANNER_IsScanning()\r\n        && gEeprom.DUAL_WATCH != DUAL_WATCH_OFF\r\n        && gScheduleDualWatch\r\n        && gScanStateDir == SCAN_OFF\r\n        && !gPttIsPressed\r\n        && gCurrentFunction != FUNCTION_POWER_SAVE\r\n#ifdef ENABLE_VOICE\r\n        && gVoiceWriteIndex == 0\r\n#endif\r\n#ifdef ENABLE_FMRADIO\r\n        && !gFmRadioMode\r\n#endif\r\n#ifdef ENABLE_DTMF_CALLING\r\n        && gDTMF_CallState == DTMF_CALL_STATE_NONE\r\n#endif\r\n            ) {\r\n        DualwatchAlternate();    // toggle between the two VFO's\r\n\r\n        if (gRxVfoIsActive && gScreenToDisplay == DISPLAY_MAIN) {\r\n            GUI_SelectNextDisplay(DISPLAY_MAIN);\r\n        }\r\n\r\n        gRxVfoIsActive = false;\r\n        gScanPauseMode = false;\r\n        gRxReceptionMode = RX_MODE_NONE;\r\n        gScheduleDualWatch = false;\r\n    }\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gScheduleFM && gFM_ScanState != FM_SCAN_OFF && !FUNCTION_IsRx()) {\r\n        // switch to FM radio mode\r\n        FM_Play();\r\n        gScheduleFM = false;\r\n    }\r\n#endif\r\n\r\n#ifdef ENABLE_VOX\r\n    if (gEeprom.VOX_SWITCH)\r\n        HandleVox();\r\n#endif\r\n\r\n    if (gSchedulePowerSave) {\r\n        if (gPttIsPressed\r\n            || gKeyBeingHeld\r\n            || gEeprom.BATTERY_SAVE == 0\r\n            || gScanStateDir != SCAN_OFF\r\n            || gCssBackgroundScan\r\n            || gScreenToDisplay != DISPLAY_MAIN\r\n#ifdef ENABLE_FMRADIO\r\n            || gFmRadioMode\r\n#endif\r\n#ifdef ENABLE_DTMF_CALLING\r\n            || gDTMF_CallState != DTMF_CALL_STATE_NONE\r\n#endif\r\n\r\n\r\n#ifdef ENABLE_NOAA\r\n            || (gIsNoaaMode && (IS_NOAA_CHANNEL(gEeprom.ScreenChannel[0]) || IS_NOAA_CHANNEL(gEeprom.ScreenChannel[1])))\r\n#endif\r\n                ) {\r\n            gBatterySaveCountdown_10ms = battery_save_count_10ms;\r\n        } else {\r\n            FUNCTION_Select(FUNCTION_POWER_SAVE);\r\n        }\r\n\r\n        gSchedulePowerSave = false;\r\n    }\r\n\r\n    if (gPowerSaveCountdownExpired && gCurrentFunction == FUNCTION_POWER_SAVE\r\n#ifdef ENABLE_VOICE\r\n        && gVoiceWriteIndex == 0\r\n#endif\r\n            ) {\r\n        static bool goToSleep;\r\n        // wake up, enable RX then go back to sleep\r\n        if (gRxIdleMode) {\r\n            BK4819_Conditional_RX_TurnOn_and_GPIO6_Enable();\r\n\r\n#ifdef ENABLE_VOX\r\n            if (gEeprom.VOX_SWITCH)\r\n                BK4819_EnableVox(gEeprom.VOX1_THRESHOLD, gEeprom.VOX0_THRESHOLD);\r\n#endif\r\n\r\n            if (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF &&\r\n                gScanStateDir == SCAN_OFF &&\r\n                !gCssBackgroundScan) {    // dual watch mode, toggle between the two VFO's\r\n                DualwatchAlternate();\r\n                goToSleep = false;\r\n            }\r\n\r\n            FUNCTION_Init();\r\n\r\n            gPowerSave_10ms = power_save1_10ms; // come back here in a bit\r\n            gRxIdleMode = false;            // RX is awake\r\n        } else if (gEeprom.DUAL_WATCH == DUAL_WATCH_OFF || gScanStateDir != SCAN_OFF || gCssBackgroundScan ||\r\n                   goToSleep) {    // dual watch mode off or scanning or rssi update request\r\n            // go back to sleep\r\n\r\n            gPowerSave_10ms = gEeprom.BATTERY_SAVE * 10;\r\n            gRxIdleMode = true;\r\n            goToSleep = false;\r\n\r\n            BK4819_DisableVox();\r\n            BK4819_Sleep();\r\n            BK4819_ToggleGpioOut(BK4819_GPIO0_PIN28_RX_ENABLE, false);\r\n\r\n            // Authentic device checked removed\r\n\r\n        } else {\r\n            // toggle between the two VFO's\r\n            DualwatchAlternate();\r\n            gPowerSave_10ms = power_save1_10ms;\r\n            goToSleep = true;\r\n        }\r\n\r\n        gPowerSaveCountdownExpired = false;\r\n    }\r\n}\r\n\r\n// called every 10ms\r\nstatic void CheckKeys(void) {\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if(gSetting_KILLED){\r\n        return;\r\n    }\r\n#endif\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n    if (gScreenToDisplay == DISPLAY_AIRCOPY && gAircopyState != AIRCOPY_READY){\r\n        return;\r\n    }\r\n#endif\r\n\r\n\r\n// -------------------- PTT ------------------------\r\n    if (gPttIsPressed) {\r\n\r\n        if (GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT) ||\r\n            SerialConfigInProgress()) {    // PTT released or serial comms config in progress\r\n            if (++gPttDebounceCounter >= 3 || SerialConfigInProgress())        // 30ms\r\n            {    // stop transmitting\r\n                ProcessKey(KEY_PTT, false, false);\r\n                gPttIsPressed = false;\r\n                if (gKeyReading1 != KEY_INVALID)\r\n                    gPttWasReleased = true;\r\n            }\r\n        } else\r\n            gPttDebounceCounter = 0;\r\n    } else if (!GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT) && !SerialConfigInProgress()) {    // PTT pressed\r\n        if (++gPttDebounceCounter >= 3)        // 30ms\r\n        {    // start transmitting\r\n            boot_counter_10ms = 0;\r\n            gPttDebounceCounter = 0;\r\n            gPttIsPressed = true;\r\n            ProcessKey(KEY_PTT, true, false);\r\n        }\r\n    } else\r\n        gPttDebounceCounter = 0;\r\n\r\n// --------------------- OTHER KEYS ----------------------------\r\n\r\n    // scan the hardware keys\r\n    KEY_Code_t Key = KEYBOARD_Poll();\r\n\r\n    if (Key != KEY_INVALID) // any key pressed\r\n        boot_counter_10ms = 0;   // cancel boot screen/beeps if any key pressed\r\n\r\n    if (gKeyReading0 != Key) // new key pressed\r\n    {\r\n\r\n        if (gKeyReading0 != KEY_INVALID && Key != KEY_INVALID)\r\n            ProcessKey(gKeyReading1, false, gKeyBeingHeld);  // key pressed without releasing previous key\r\n\r\n        gKeyReading0 = Key;\r\n        gDebounceCounter = 0;\r\n        return;\r\n    }\r\n\r\n    gDebounceCounter++;\r\n\r\n    if (gDebounceCounter == key_debounce_10ms) // debounced new key pressed\r\n    {\r\n        if (Key == KEY_INVALID) //all non PTT keys released\r\n        {\r\n            if (gKeyReading1 != KEY_INVALID) // some button was pressed before\r\n            {\r\n                ProcessKey(gKeyReading1, false, gKeyBeingHeld); // process last button released event\r\n                gKeyReading1 = KEY_INVALID;\r\n            }\r\n        } else // process new key pressed\r\n        {\r\n            gKeyReading1 = Key;\r\n            ProcessKey(Key, true, false);\r\n\r\n        }\r\n\r\n        gKeyBeingHeld = false;\r\n        return;\r\n    }\r\n\r\n    if (gDebounceCounter < key_repeat_delay_10ms ||\r\n        Key == KEY_INVALID) // the button is not held long enough for repeat yet, or not really pressed\r\n        return;\r\n\r\n    if (gDebounceCounter == key_repeat_delay_10ms) //initial key repeat with longer delay\r\n    {\r\n        if (Key != KEY_PTT) {\r\n            gKeyBeingHeld = true;\r\n            ProcessKey(Key, true, true); // key held event\r\n\r\n        }\r\n\r\n    } else //subsequent fast key repeats\r\n    {\r\n        if (Key == KEY_UP || Key == KEY_DOWN) // fast key repeats for up/down buttons\r\n        {\r\n            gKeyBeingHeld = true;\r\n            if ((gDebounceCounter % key_repeat_10ms) == 0)\r\n                ProcessKey(Key, true, true); // key held event\r\n\r\n\r\n\r\n        }\r\n\r\n        if (gDebounceCounter < 0xFFFF)\r\n            return;\r\n\r\n        gDebounceCounter = key_repeat_delay_10ms + 1;\r\n    }\r\n\r\n}\r\n\r\nvoid APP_TimeSlice10ms(void) {\r\n    gNextTimeslice = false;\r\n    gFlashLightBlinkCounter++;\r\n#ifdef ENABLE_MESSENGER\r\n    keyTickCounter++;\r\n#endif\r\n#ifdef ENABLE_BOOT_BEEPS\r\n    if (boot_counter_10ms > 0 && (boot_counter_10ms % 25) == 0) {\r\n        AUDIO_PlayBeep(BEEP_880HZ_40MS_OPTIONAL);\r\n    }\r\n#endif\r\n\r\n#ifdef ENABLE_AM_FIX\r\n    if (gRxVfo->Modulation == MODULATION_AM) {\r\n        AM_fix_10ms(gEeprom.RX_VFO);\r\n    }\r\n#endif\r\n#ifdef ENABLE_UART\r\n\r\n    if (UART_IsCommandAvailable()) {\r\n\r\n        __disable_irq();\r\n\r\n        UART_HandleCommand();\r\n        __enable_irq();\r\n    }\r\n#endif\r\n    if (gReducedService)\r\n        return;\r\n\r\n    if (gCurrentFunction != FUNCTION_POWER_SAVE || !gRxIdleMode)\r\n        CheckRadioInterrupts();\r\n\r\n    if (gCurrentFunction == FUNCTION_TRANSMIT) {    // transmitting\r\n//#ifdef ENABLE_AUDIO_BAR\r\n        if ((gFlashLightBlinkCounter % (150 / 10)) == 0) // once every 150ms\r\n            UI_DisplayAudioBar();\r\n//#endif\r\n    }\r\n\r\n    if (gUpdateDisplay) {\r\n        gUpdateDisplay = false;\r\n        GUI_DisplayScreen();\r\n    }\r\n\r\n\r\n    if (gUpdateStatus)\r\n        UI_DisplayStatus();\r\n\r\n    // Skipping authentic device checks\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFmRadioMode && gFmRadioCountdown_500ms > 0)   // 1of11\r\n            return;\r\n#endif\r\n#ifdef ENABLE_FLASHLIGHT\r\n    //    FlashlightTimeSlice();\r\n#endif\r\n#ifdef ENABLE_VOX\r\n    if (gVoxResumeCountdown > 0)\r\n            gVoxResumeCountdown--;\r\n\r\n        if (gVoxPauseCountdown > 0)\r\n            gVoxPauseCountdown--;\r\n#endif\r\n\r\n\r\n    if (gCurrentFunction == FUNCTION_TRANSMIT) {\r\n#ifdef ENABLE_ALARM\r\n        if (gAlarmState == ALARM_STATE_TXALARM || gAlarmState == ALARM_STATE_SITE_ALARM)\r\n\r\n            {\r\n                uint16_t Tone;\r\n\r\n                gAlarmRunningCounter++;\r\n                gAlarmToneCounter++;\r\n\r\n                Tone = 500 + (gAlarmToneCounter * 25);\r\n                if (Tone > 1500)\r\n                {\r\n                    Tone              = 500;\r\n                    gAlarmToneCounter = 0;\r\n                }\r\n\r\n                BK4819_SetScrambleFrequencyControlWord(Tone);\r\n\r\n                if (gEeprom.ALARM_MODE == ALARM_MODE_TONE && gAlarmRunningCounter == 512)\r\n                {\r\n                    gAlarmRunningCounter = 0;\r\n\r\n                    if (gAlarmState == ALARM_STATE_TXALARM)\r\n                    {\r\ngAlarmState = ALARM_STATE_SITE_ALARM;\r\n                        if(gEeprom.TAIL_TONE_ELIMINATION)\r\n                        RADIO_SendCssTail();\r\n                        BK4819_SetupPowerAmplifier(0, 0);\r\n                        BK4819_ToggleGpioOut(BK4819_GPIO1_PIN29_PA_ENABLE, false);\r\n                        BK4819_Enable_AfDac_DiscMode_TxDsp();\r\n                        BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, false);\r\n\r\n                        GUI_DisplayScreen();\r\n                    }\r\n                    else\r\n                    {\r\n                        gAlarmState = ALARM_STATE_TXALARM;\r\n\r\n                        GUI_DisplayScreen();\r\n\r\n                        BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, true);\r\n                        RADIO_SetTxParameters();\r\n                        BK4819_TransmitTone(true, 500);\r\n                        SYSTEM_DelayMs(2);\r\n                        AUDIO_AudioPathOn();\r\n\r\n                        gEnableSpeaker    = true;\r\n                        gAlarmToneCounter = 0;\r\n                    }\r\n                }\r\n            }\r\n#endif\r\n\r\n        // repeater tail tone elimination\r\n        if (gRTTECountdown_10ms > 0) {\r\n            if (--gRTTECountdown_10ms == 0) {\r\n                FUNCTION_Select(FUNCTION_FOREGROUND); //OK\r\n                gUpdateStatus = true;\r\n                gUpdateDisplay = true;\r\n            }\r\n        }\r\n    }\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFmRadioMode && gFM_RestoreCountdown_10ms > 0)\r\n    {\r\n        if (--gFM_RestoreCountdown_10ms == 0)\r\n        {\t// switch back to FM radio mode\r\n            FM_Start();\r\n            GUI_SelectNextDisplay(DISPLAY_FM);\r\n        }\r\n    }\r\n#endif\r\n\r\n\r\n    SCANNER_TimeSlice10ms();\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n    if (gScreenToDisplay == DISPLAY_AIRCOPY && gAircopyState == AIRCOPY_TRANSFER && gAirCopyIsSendMode == 1)\r\n    {\r\n        if (!AIRCOPY_SendMessage()) {\r\n            GUI_DisplayScreen();\r\n        }\r\n    }\r\n#endif\r\n\r\n    CheckKeys();\r\n}\r\n\r\nvoid cancelUserInputModes(void) {\r\n    if (gDTMF_InputMode || gDTMF_InputBox_Index > 0) {\r\n        DTMF_clear_input_box();\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n        gRequestDisplayScreen = DISPLAY_MAIN;\r\n        gUpdateDisplay = true;\r\n    }\r\n\r\n    if (gWasFKeyPressed || gKeyInputCountdown > 0 || gInputBoxIndex > 0) {\r\n        gWasFKeyPressed = false;\r\n        gInputBoxIndex = 0;\r\n        gKeyInputCountdown = 0;\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n        gUpdateStatus = true;\r\n        gUpdateDisplay = true;\r\n    }\r\n}\r\n\r\n// this is called once every 500ms\r\nvoid APP_TimeSlice500ms(void) {\r\n    gNextTimeslice_500ms = false;\r\n    bool exit_menu = false;\r\n#ifdef ENABLE_MESSENGER_NOTIFICATION\r\n    if (gPlayMSGRing) {\r\n        gPlayMSGRingCount = 5;\r\n        gPlayMSGRing = false;\r\n    }\r\n    if (gPlayMSGRingCount > 0) {\r\n\r\n        AUDIO_PlayBeep(BEEP_880HZ_200MS);\r\n        gPlayMSGRingCount--;\r\n    }\r\n#endif\r\n\r\n#ifdef ENABLE_MESSENGER\r\n    if (hasNewMessage > 0) {\r\n        if (hasNewMessage == 1) {\r\n            hasNewMessage = 2;\r\n        } else if (hasNewMessage == 2) {\r\n            hasNewMessage = 1;\r\n        }\r\n    }\r\n#endif\r\n\r\n    // Skipped authentic device check\r\n\r\n    if (gKeypadLocked > 0)\r\n        if (--gKeypadLocked == 0)\r\n            gUpdateDisplay = true;\r\n\r\n    if (gKeyInputCountdown > 0) {\r\n        if (--gKeyInputCountdown == 0) {\r\n            cancelUserInputModes();\r\n\r\n            if (gBeepToPlay != BEEP_NONE) {\r\n#ifdef    ENABLE_WARNING\r\n\r\n                AUDIO_PlayBeep(gBeepToPlay);\r\n#endif\r\n                gBeepToPlay = BEEP_NONE;\r\n            }\r\n        }\r\n    }\r\n\r\n    if (gDTMF_RX_live_timeout > 0) {\r\n#ifdef ENABLE_RSSI_BAR\r\n        if (center_line == CENTER_LINE_DTMF_DEC ||\r\n                center_line == CENTER_LINE_NONE)  // wait till the center line is free for us to use before timing out\r\n#endif\r\n        {\r\n            if (--gDTMF_RX_live_timeout == 0) {\r\n                if (gDTMF_RX_live[0] != 0) {\r\n                    memset(gDTMF_RX_live, 0, sizeof(gDTMF_RX_live));\r\n                    gUpdateDisplay = true;\r\n                }\r\n            }\r\n        }\r\n    }\r\n\r\n    if (gMenuCountdown > 0)\r\n        if (--gMenuCountdown == 0)\r\n            exit_menu = (gScreenToDisplay == DISPLAY_MENU);    // exit menu mode\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (gDTMF_RX_timeout > 0)\r\n        if (--gDTMF_RX_timeout == 0)\r\n            DTMF_clear_RX();\r\n#endif\r\n#ifdef ENABLE_MDC1200\r\n    if (mdc1200_rx_ready_tick_500ms > 0)\r\n        {\r\n            if (--mdc1200_rx_ready_tick_500ms == 0)\r\n            {\r\n                if (center_line == CENTER_LINE_MDC1200)\r\n                    center_line = CENTER_LINE_NONE;\r\n                gUpdateDisplay = true;\r\n            }\r\n        }\r\n#endif\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFmRadioCountdown_500ms > 0)\r\n    {\r\n        gFmRadioCountdown_500ms--;\r\n        if (gFmRadioMode)           // 1of11\r\n            return;\r\n    }\r\n#endif\r\n\r\n    if (gBacklightCountdown_500ms > 0 && !gAskToSave && !gCssBackgroundScan\r\n        // don't turn off backlight if user is in backlight menu option\r\n        && !(gScreenToDisplay == DISPLAY_MENU &&\r\n             (UI_MENU_GetCurrentMenuId() == MENU_ABR || UI_MENU_GetCurrentMenuId() == MENU_ABR_MAX))\r\n        && --gBacklightCountdown_500ms == 0\r\n        && gEeprom.BACKLIGHT_TIME < (ARRAY_SIZE(gSubMenu_BACKLIGHT) - 1)\r\n            ) {\r\n        BACKLIGHT_TurnOff();\r\n\r\n\r\n    }\r\n    if (gReducedService) {\r\n        BOARD_ADC_GetBatteryInfo(&gBatteryCurrentVoltage, &gBatteryCurrent);\r\n\r\n        if (gBatteryCurrent > 500 || gBatteryCalibration[3] < gBatteryCurrentVoltage) {\r\n#ifdef ENABLE_OVERLAY\r\n            overlay_FLASH_RebootToBootloader();\r\n#else\r\n            NVIC_SystemReset();\r\n#endif\r\n        }\r\n\r\n        return;\r\n    }\r\n\r\n    gBatteryCheckCounter++;\r\n\r\n    // Skipped authentic device check\r\n\r\n    if (gCurrentFunction != FUNCTION_TRANSMIT) {\r\n\r\n        if ((gBatteryCheckCounter & 1) == 0) {\r\n            BOARD_ADC_GetBatteryInfo(&gBatteryVoltages[gBatteryVoltageIndex++], &gBatteryCurrent);\r\n            if (gBatteryVoltageIndex > 3)\r\n                gBatteryVoltageIndex = 0;\r\n            BATTERY_GetReadings(true);\r\n        }\r\n    }\r\n\r\n    // regular display updates (once every 2 sec) - if need be\r\n    if ((gBatteryCheckCounter & 3) == 0) {\r\n        if (gChargingWithTypeC)\r\n            gUpdateStatus = true;\r\n#ifdef ENABLE_SHOW_CHARGE_LEVEL\r\n        if (gChargingWithTypeC)\r\n                gUpdateDisplay = true;\r\n#endif\r\n    }\r\n\r\n    if (!gCssBackgroundScan && gScanStateDir == SCAN_OFF && !SCANNER_IsScanning()\r\n#ifdef ENABLE_FMRADIO\r\n        && (gFM_ScanState == FM_SCAN_OFF || gAskToSave)\r\n#endif\r\n#ifdef ENABLE_AIRCOPY\r\n        && gScreenToDisplay != DISPLAY_AIRCOPY\r\n#endif\r\n            ) {\r\n\r\n\r\n        if (exit_menu) {\r\n            gMenuCountdown = 0;\r\n\r\n            if (gEeprom.BACKLIGHT_TIME == 0) {\r\n                BACKLIGHT_TurnOff();\r\n            }\r\n#ifdef    ENABLE_WARNING\r\n\r\n            if (gInputBoxIndex > 0 || gDTMF_InputMode) {\r\n                AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL);\r\n            }\r\n#endif\r\n/*\r\n\t\t\tif (SCANNER_IsScanning()) {\r\n\t\t\t\tBK4819_StopScan();\r\n\t\t\t\tRADIO_ConfigureChannel(0, VFO_CONFIGURE_RELOAD);\r\n\t\t\t\tRADIO_ConfigureChannel(1, VFO_CONFIGURE_RELOAD);\r\n\t\t\t\tRADIO_SetupRegisters(true);\r\n\t\t\t}\r\n*/\r\n            DTMF_clear_input_box();\r\n\r\n            gWasFKeyPressed = false;\r\n            gInputBoxIndex = 0;\r\n\r\n            gAskToSave = false;\r\n            gAskToDelete = false;\r\n\r\n            gUpdateStatus = true;\r\n            gUpdateDisplay = true;\r\n\r\n            GUI_DisplayType_t disp = DISPLAY_INVALID;\r\n\r\n#ifdef ENABLE_FMRADIO\r\n            if (gFmRadioMode && ! FUNCTION_IsRx()) {\r\n                disp = DISPLAY_FM;\r\n            }\r\n#endif\r\n\r\n            if (disp == DISPLAY_INVALID\r\n#ifdef ENABLE_NO_CODE_SCAN_TIMEOUT\r\n                && !SCANNER_IsScanning()\r\n#endif\r\n                    ) {\r\n                disp = DISPLAY_MAIN;\r\n            }\r\n\r\n            if (disp != DISPLAY_INVALID) {\r\n                GUI_SelectNextDisplay(disp);\r\n            }\r\n        }\r\n    }\r\n\r\n    if (!gPttIsPressed && gVFOStateResumeCountdown_500ms > 0 && --gVFOStateResumeCountdown_500ms == 0) {\r\n        RADIO_SetVfoState(VFO_STATE_NORMAL);\r\n#ifdef ENABLE_FMRADIO\r\n        if (gFmRadioMode && !FUNCTION_IsRx()) {\r\n            // switch back to FM radio mode\r\n            FM_Start();\r\n            GUI_SelectNextDisplay(DISPLAY_FM);\r\n        }\r\n#endif\r\n    }\r\n    BATTERY_TimeSlice500ms();\r\n    SCANNER_TimeSlice500ms();\r\n    UI_MAIN_TimeSlice500ms();\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (gCurrentFunction != FUNCTION_TRANSMIT) {\r\n    if (gDTMF_DecodeRingCountdown_500ms > 0) {\r\n        // make \"ring-ring\" sound\r\n        gDTMF_DecodeRingCountdown_500ms--;\r\n#ifdef    ENABLE_WARNING\r\n\r\n        AUDIO_PlayBeep(BEEP_880HZ_200MS);\r\n#endif\r\n    }\r\n} else {\r\n    gDTMF_DecodeRingCountdown_500ms = 0;\r\n}\r\nif (gDTMF_CallState  != DTMF_CALL_STATE_NONE && gCurrentFunction != FUNCTION_TRANSMIT\r\n    && gCurrentFunction != FUNCTION_RECEIVE && gDTMF_auto_reset_time_500ms > 0\r\n    && --gDTMF_auto_reset_time_500ms == 0)\r\n{\r\n    gUpdateDisplay  = true;\r\n    if (gDTMF_CallState == DTMF_CALL_STATE_RECEIVED && gEeprom.DTMF_auto_reset_time >= DTMF_HOLD_MAX) {\r\n        gDTMF_CallState = DTMF_CALL_STATE_RECEIVED_STAY;     // keep message on-screen till a key is pressed\r\n    } else {\r\n        gDTMF_CallState = DTMF_CALL_STATE_NONE;\r\n    }\r\n}\r\n\r\nif (gDTMF_IsTx && gDTMF_TxStopCountdown_500ms > 0 && --gDTMF_TxStopCountdown_500ms == 0) {\r\n    gDTMF_IsTx     = false;\r\n    gUpdateDisplay = true;\r\n}\r\n#endif\r\n\r\n#ifdef ENABLE_TURN\r\n    if(turn_flag && !gWasFKeyPressed){\r\n        turn_flag = 0;\r\n    }\r\n#endif\r\n}\r\n\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\nstatic void ALARM_Off(void)\r\n{\r\n    AUDIO_AudioPathOff();\r\n    gEnableSpeaker = false;\r\n\r\nif (gAlarmState == ALARM_STATE_TXALARM || gAlarmState == ALARM_STATE_TX1750) {\r\n        APP_EndTransmission(false); //OK\r\n    }\r\n\r\n    gAlarmState = ALARM_STATE_OFF;\r\n\r\n#ifdef ENABLE_VOX\r\n    gVoxResumeCountdown = 80;\r\n#endif\r\n\r\n    SYSTEM_DelayMs(5);\r\n\r\n    RADIO_SetupRegisters(true);\r\n\r\n    if (gScreenToDisplay != DISPLAY_MENU)     // 1of11 .. don't close the menu\r\n        gRequestDisplayScreen = DISPLAY_MAIN;\r\n}\r\n#endif\r\n\r\n\r\nstatic void ProcessKey(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) {\r\n    if (Key == KEY_EXIT && !BACKLIGHT_IsOn() &&\r\n        gEeprom.BACKLIGHT_TIME > 0) {    // just turn the light on for now so the user can see what's what\r\n        BACKLIGHT_TurnOn();\r\n        gBeepToPlay = BEEP_NONE;\r\n        return;\r\n    }\r\n\r\n    if (gCurrentFunction == FUNCTION_POWER_SAVE)\r\n        FUNCTION_Select(FUNCTION_FOREGROUND); //OK\r\n\r\n    gBatterySaveCountdown_10ms = battery_save_count_10ms;\r\n\r\n\r\n    if (!bKeyPressed) // key released\r\n    {\r\n        if (flagSaveVfo) {\r\n            SETTINGS_SaveVfoIndices();\r\n            flagSaveVfo = false;\r\n        }\r\n\r\n        if (flagSaveSettings) {\r\n            SETTINGS_SaveSettings();\r\n            flagSaveSettings = false;\r\n        }\r\n\r\n#ifdef ENABLE_FMRADIO\r\n        if (gFlagSaveFM)\r\n            {\r\n                SETTINGS_SaveFM();\r\n                gFlagSaveFM = false;\r\n            }\r\n#endif\r\n\r\n        if (flagSaveChannel) {\r\n            SETTINGS_SaveChannel(gTxVfo->CHANNEL_SAVE, gEeprom.TX_VFO, gTxVfo, flagSaveChannel);\r\n            flagSaveChannel = false;\r\n\r\n            if (!SCANNER_IsScanning() && gVfoConfigureMode == VFO_CONFIGURE_NONE)\r\n                // gVfoConfigureMode is so as we don't wipe out previously setting this variable elsewhere\r\n                gVfoConfigureMode = VFO_CONFIGURE;\r\n        }\r\n\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\n        if (gFlagStopTX)\r\n        {\r\n            gFlagStopTX = false;\r\n            APP_EndTransmission(true);\r\n            RADIO_SetupRegisters(true);\r\n            GUI_SelectNextDisplay(DISPLAY_MAIN);\r\n            gEeprom.TX_VFO = gFlagLastVfo;\r\n            gFlagReconfigureVfos = true;\r\n            gUpdateDisplay = true;\r\n            return;\r\n        }\r\n#endif\r\n    } else // key pressed or held\r\n    {\r\n        //  const uint8_t s = BACKLIGHT_ON_TR_TXRX;\r\n        const int m = UI_MENU_GetCurrentMenuId();\r\n        if (    //not when PTT and the backlight shouldn't turn on on TX\r\n            /*    !(Key == KEY_PTT && s != BACKLIGHT_ON_TR_TX && s != BACKLIGHT_ON_TR_TXRX)\r\n                // not in the backlight menu\r\n                &&*/ !(gScreenToDisplay == DISPLAY_MENU && (m == MENU_ABR || m == MENU_ABR_MAX))\r\n                ) {\r\n            BACKLIGHT_TurnOn();\r\n        }\r\n\r\n        if (Key == KEY_EXIT && bKeyHeld) {    // exit key held pressed\r\n\r\n            // clear the live DTMF decoder\r\n            if (gDTMF_RX_live[0] != 0) {\r\n                memset(gDTMF_RX_live, 0, sizeof(gDTMF_RX_live));\r\n                gDTMF_RX_live_timeout = 0;\r\n                gUpdateDisplay = true;\r\n            }\r\n\r\n            // cancel user input\r\n            cancelUserInputModes();\r\n\r\n            if (gMonitor)\r\n                ACTION_Monitor(); //turn off the monitor\r\n#ifdef ENABLE_SCAN_RANGES\r\n            gScanRangeStart = 0;\r\n#endif\r\n        }\r\n\r\n        if (gScreenToDisplay == DISPLAY_MENU)       // 1of11\r\n            gMenuCountdown = menu_timeout_500ms;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n        if (gDTMF_DecodeRingCountdown_500ms > 0)\r\n        {\t// cancel the ringing\r\n            gDTMF_DecodeRingCountdown_500ms = 0;\r\n#ifdef    ENABLE_WARNING\r\n\r\n            AUDIO_PlayBeep(BEEP_1KHZ_60MS_OPTIONAL);\r\n#endif\r\n            if (Key != KEY_PTT)\r\n            {\r\n                gPttWasReleased = true;\r\n                return;\r\n            }\r\n        }\r\n#endif\r\n    }\r\n\r\n    bool lowBatPopup = gLowBattery && !gLowBatteryConfirmed && gScreenToDisplay == DISPLAY_MAIN;\r\n\r\n    if ((gEeprom.KEY_LOCK || lowBatPopup) && gCurrentFunction != FUNCTION_TRANSMIT &&\r\n        Key != KEY_PTT) {    // keyboard is locked or low battery popup\r\n\r\n        // close low battery popup\r\n        if (Key == KEY_EXIT && bKeyPressed && lowBatPopup) {\r\n            gLowBatteryConfirmed = true;\r\n            gUpdateDisplay = true;\r\n#ifdef    ENABLE_WARNING\r\n\r\n            AUDIO_PlayBeep(BEEP_1KHZ_60MS_OPTIONAL);\r\n#endif\r\n            return;\r\n        }\r\n\r\n        if (Key == KEY_F) {    // function/key-lock key\r\n\r\n            if (!bKeyPressed)\r\n                return;\r\n\r\n            if (!bKeyHeld) {    // keypad is locked, tell the user\r\n#ifdef    ENABLE_WARNING\r\n\r\n                AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL);\r\n#endif\r\n                gKeypadLocked = 4;      // 2 seconds\r\n                gUpdateDisplay = true;\r\n                return;\r\n            }\r\n        }\r\n            // KEY_MENU has a special treatment here, because we want to pass hold event to ACTION_Handle\r\n            // but we don't want it to complain when initial press happens\r\n            // we want to react on realese instead\r\n            // KEY_MENU has a special treatment here, because we want to pass hold event to ACTION_Handle\r\n            // but we don't want it to complain when initial press happens\r\n            // we want to react on realese instead\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n            else if (Key != KEY_SIDE1 && Key != KEY_SIDE2 &&        // pass side buttons\r\n                 !(Key == KEY_MENU && bKeyHeld && gEeprom.KEY_M_LONG_PRESS_ACTION == ACTION_OPT_KEYLOCK)) // pass KEY_MENU held\r\n#else\r\n        else if (Key != KEY_SIDE1 && Key != KEY_SIDE2) // pass KEY_MENU held\r\n#endif\r\n        {\r\n\r\n            // keypad is locked, tell the user\r\n#ifdef    ENABLE_WARNING\r\n\r\n            AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL);\r\n#endif\r\n            gKeypadLocked = 4;          // 2 seconds\r\n            gUpdateDisplay = true;\r\n            return;\r\n        }\r\n    }\r\n\r\n    if (Key <= KEY_9 || Key == KEY_F) {\r\n        if (gScanStateDir != SCAN_OFF || gCssBackgroundScan) {    // FREQ/CTCSS/DCS scanning\r\n#ifdef    ENABLE_WARNING\r\n\r\n            if (bKeyPressed && !bKeyHeld)\r\n                AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL);\r\n#endif\r\n            return;\r\n        }\r\n    }\r\n\r\n    bool bFlag = false;\r\n    if (Key == KEY_PTT) {\r\n//        if(gEeprom.KEY_LOCK)\r\n//        {\r\n//            gKeypadLocked  = 4;          // 2 seconds\r\n//            return;\r\n//        }\r\n        if (gPttWasPressed) {\r\n            bFlag = bKeyHeld;\r\n            if (!bKeyPressed) {\r\n                bFlag = true;\r\n                gPttWasPressed = false;\r\n\r\n\r\n            }\r\n        }\r\n    } else if (gPttWasReleased) {\r\n        if (bKeyHeld)\r\n            bFlag = true;\r\n        if (!bKeyPressed) {\r\n            bFlag = true;\r\n            gPttWasReleased = false;\r\n        }\r\n    }\r\n\r\n    if (gWasFKeyPressed &&\r\n        (Key == KEY_PTT || Key == KEY_EXIT || Key == KEY_SIDE1 || Key == KEY_SIDE2)) {    // cancel the F-key\r\n        gWasFKeyPressed = false;\r\n        gUpdateStatus = true;\r\n    }\r\n\r\n    if (bFlag) {\r\n        goto Skip;\r\n    }\r\n    if (gCurrentFunction == FUNCTION_TRANSMIT) {\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\n        if (gAlarmState == ALARM_STATE_OFF)\r\n#endif\r\n        {\r\n            char Code;\r\n\r\n            if (Key == KEY_PTT) {\r\n                GENERIC_Key_PTT(bKeyPressed);\r\n                goto Skip;\r\n            }\r\n\r\n            if (Key == KEY_SIDE2) {    // transmit 1750Hz tone\r\n                Code = 0xFE;\r\n            } else {\r\n\r\n                Code = DTMF_GetCharacter(Key - KEY_0);\r\n                if (Code == 0xFF)\r\n                    goto Skip;\r\n\r\n                // transmit DTMF keys\r\n            }\r\n\r\n            if (!bKeyPressed || bKeyHeld) {\r\n                if (!bKeyPressed) {\r\n                    AUDIO_AudioPathOff();\r\n\r\n                    gEnableSpeaker = false;\r\n\r\n                    BK4819_ExitDTMF_TX(false);\r\n\r\n                    if (gCurrentVfo->SCRAMBLING_TYPE == 0 || !gSetting_ScrambleEnable)\r\n                        BK4819_DisableScramble();\r\n                    else\r\n                        BK4819_EnableScramble(gCurrentVfo->SCRAMBLING_TYPE - 1);\r\n                }\r\n            } else {\r\n                if (gEeprom.DTMF_SIDE_TONE) {    // user will here the DTMF tones in speaker\r\n                    AUDIO_AudioPathOn();\r\n                    gEnableSpeaker = true;\r\n                }\r\n\r\n                BK4819_DisableScramble();\r\n\r\n                if (Code == 0xFE)\r\n                    BK4819_TransmitTone(gEeprom.DTMF_SIDE_TONE, 1750);\r\n                else\r\n                    BK4819_PlayDTMFEx(gEeprom.DTMF_SIDE_TONE, Code);\r\n            }\r\n        }\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\n        else if ((!bKeyHeld && bKeyPressed) || (gAlarmState == ALARM_STATE_TX1750 && bKeyHeld && !bKeyPressed)) {\r\n            ALARM_Off();\r\n\r\n            if (Key == KEY_PTT)\r\n                gPttWasPressed  = true;\r\n            else if (!bKeyHeld)\r\n                gPttWasReleased = true;\r\n        }\r\n#endif\r\n    } else if (Key != KEY_SIDE1 && Key != KEY_SIDE2 && gScreenToDisplay != DISPLAY_INVALID) {\r\n        ProcessKeysFunctions[gScreenToDisplay](Key, bKeyPressed, bKeyHeld);\r\n    } else if (!SCANNER_IsScanning()\r\n#ifdef ENABLE_AIRCOPY\r\n        && gScreenToDisplay != DISPLAY_AIRCOPY\r\n#endif\r\n            ) {\r\n        ACTION_Handle(Key, bKeyPressed, bKeyHeld);\r\n    } else if (!bKeyHeld && bKeyPressed) {\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n    }\r\n\r\n    Skip:\r\n    if (gBeepToPlay != BEEP_NONE) {\r\n#ifdef    ENABLE_WARNING\r\n\r\n        AUDIO_PlayBeep(gBeepToPlay);\r\n#endif\r\n        gBeepToPlay = BEEP_NONE;\r\n    }\r\n\r\n    if (gFlagAcceptSetting) {\r\n        gMenuCountdown = menu_timeout_500ms;\r\n\r\n        MENU_AcceptSetting();\r\n\r\n        gFlagRefreshSetting = true;\r\n        gFlagAcceptSetting = false;\r\n    }\r\n\r\n    if (gRequestSaveSettings) {\r\n        if (!bKeyHeld)\r\n            SETTINGS_SaveSettings();\r\n        else\r\n            flagSaveSettings = 1;\r\n        gRequestSaveSettings = false;\r\n        gUpdateStatus = true;\r\n    }\r\n#ifdef ENABLE_FMRADIO\r\n    if (gRequestSaveFM)\r\n    {\r\n        gRequestSaveFM = false;\r\n        if (!bKeyHeld)\r\n            SETTINGS_SaveFM();\r\n        else\r\n            gFlagSaveFM = true;\r\n    }\r\n#endif\r\n\r\n    if (gRequestSaveVFO) {\r\n        gRequestSaveVFO = false;\r\n        if (!bKeyHeld)\r\n            SETTINGS_SaveVfoIndices();\r\n        else\r\n            flagSaveVfo = true;\r\n    }\r\n\r\n    if (gRequestSaveChannel > 0) {\r\n        if (!bKeyHeld)// TODO: remove the gRequestSaveChannel, why use global variable for that??\r\n        {\r\n            SETTINGS_SaveChannel(gTxVfo->CHANNEL_SAVE, gEeprom.TX_VFO, gTxVfo, gRequestSaveChannel);\r\n\r\n            if (!SCANNER_IsScanning() && gVfoConfigureMode == VFO_CONFIGURE_NONE)\r\n                // gVfoConfigureMode is so as we don't wipe out previously setting this variable elsewhere\r\n                gVfoConfigureMode = VFO_CONFIGURE;\r\n        } else {// this is probably so settings are not saved when up/down button is held and save is postponed to btn release\r\n            flagSaveChannel = gRequestSaveChannel;\r\n\r\n            if (gRequestDisplayScreen == DISPLAY_INVALID)\r\n                gRequestDisplayScreen = DISPLAY_MAIN;\r\n        }\r\n\r\n        gRequestSaveChannel = 0;\r\n    }\r\n\r\n    if (gVfoConfigureMode != VFO_CONFIGURE_NONE) {\r\n        if (gFlagResetVfos) {\r\n            RADIO_ConfigureChannel(0, gVfoConfigureMode);\r\n            RADIO_ConfigureChannel(1, gVfoConfigureMode);\r\n        } else\r\n            RADIO_ConfigureChannel(gEeprom.TX_VFO, gVfoConfigureMode);\r\n\r\n        if (gRequestDisplayScreen == DISPLAY_INVALID)\r\n            gRequestDisplayScreen = DISPLAY_MAIN;\r\n\r\n        gFlagReconfigureVfos = true;\r\n        gVfoConfigureMode = VFO_CONFIGURE_NONE;\r\n        gFlagResetVfos = false;\r\n    }\r\n\r\n    if (gFlagReconfigureVfos) {\r\n        RADIO_SelectVfos();\r\n\r\n#ifdef ENABLE_NOAA\r\n        RADIO_ConfigureNOAA();\r\n#endif\r\n\r\n        RADIO_SetupRegisters(true);\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n        gDTMF_auto_reset_time_500ms = 0;\r\n        gDTMF_CallState             = DTMF_CALL_STATE_NONE;\r\n        gDTMF_TxStopCountdown_500ms = 0;\r\n        gDTMF_IsTx                  = false;\r\n#endif\r\n\r\n        gVFO_RSSI_bar_level[0] = 0;\r\n        gVFO_RSSI_bar_level[1] = 0;\r\n\r\n        gFlagReconfigureVfos = false;\r\n\r\n        if (gMonitor)\r\n            ACTION_Monitor();   // 1of11\r\n    }\r\n\r\n    if (gFlagRefreshSetting) {\r\n        gFlagRefreshSetting = false;\r\n        gMenuCountdown = menu_timeout_500ms;\r\n\r\n        MENU_ShowCurrentSetting();\r\n    }\r\n\r\n    if (gFlagPrepareTX) {\r\n        RADIO_PrepareTX();\r\n        gFlagPrepareTX = false;\r\n    }\r\n\r\n#ifdef ENABLE_VOICE\r\n    if (gAnotherVoiceID != VOICE_ID_INVALID) {\r\n        if (gAnotherVoiceID < 76)\r\n            AUDIO_SetVoiceID(0, gAnotherVoiceID);\r\n        AUDIO_PlaySingleVoice(false);\r\n        gAnotherVoiceID = VOICE_ID_INVALID;\r\n    }\r\n#endif\r\n\r\n    GUI_SelectNextDisplay(gRequestDisplayScreen);\r\n    gRequestDisplayScreen = DISPLAY_INVALID;\r\n\r\n    gUpdateDisplay = true;\r\n\r\n}\r\n"
  },
  {
    "path": "app/app.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef APP_APP_H\r\n#define APP_APP_H\r\n\r\n#include <stdbool.h>\r\n\r\n#include \"functions.h\"\r\n#include \"frequencies.h\"\r\n#include \"radio.h\"\r\n\r\n#ifdef ENABLE_MESSENGER_NOTIFICATION\r\nextern bool gPlayMSGRing;\r\n#endif\r\n\r\nvoid APP_EndTransmission(bool inmediately);\r\n\r\nvoid APP_StartListening(FUNCTION_Type_t function);\r\n\r\nuint32_t APP_SetFreqByStepAndLimits(VFO_Info_t *pInfo, int8_t direction, uint32_t lower, uint32_t upper);\r\n\r\nuint32_t APP_SetFrequencyByStep(VFO_Info_t *pInfo, int8_t direction);\r\n\r\nvoid APP_Update(void);\r\n\r\nvoid APP_TimeSlice10ms(void);\r\n\r\nvoid APP_TimeSlice500ms(void);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "app/chFrScanner.c",
    "content": "\r\n#include \"app/app.h\"\r\n#include \"app/chFrScanner.h\"\r\n#include \"functions.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n\r\nint8_t gScanStateDir;\r\nbool gScanKeepResult;\r\nbool gScanPauseMode;\r\n\r\n#ifdef ENABLE_SCAN_RANGES\r\nuint32_t          gScanRangeStart;\r\nuint32_t gScanRangeStop;\r\n#endif\r\n\r\ntypedef enum {\r\n    SCAN_NEXT_CHAN_SCANLIST1 = 0,\r\n    SCAN_NEXT_CHAN_SCANLIST2,\r\n    SCAN_NEXT_CHAN_DUAL_WATCH,\r\n    SCAN_NEXT_CHAN_MR,\r\n    SCAN_NEXT_NUM\r\n} scan_next_chan_t;\r\n\r\nscan_next_chan_t currentScanList;\r\nuint32_t initialFrqOrChan;\r\nuint8_t initialCROSS_BAND_RX_TX;\r\nuint32_t lastFoundFrqOrChan;\r\n\r\nstatic void NextFreqChannel(void);\r\n\r\nstatic void NextMemChannel(void);\r\n\r\nvoid CHFRSCANNER_Start(const bool storeBackupSettings, const int8_t scan_direction) {\r\n    if (storeBackupSettings) {\r\n        initialCROSS_BAND_RX_TX = gEeprom.CROSS_BAND_RX_TX;\r\n        gEeprom.CROSS_BAND_RX_TX = CROSS_BAND_OFF;\r\n        gScanKeepResult = false;\r\n    }\r\n\r\n    RADIO_SelectVfos();\r\n\r\n    gNextMrChannel = gRxVfo->CHANNEL_SAVE;\r\n    currentScanList = SCAN_NEXT_CHAN_SCANLIST1;\r\n    gScanStateDir = scan_direction;\r\n\r\n    if (IS_MR_CHANNEL(gNextMrChannel)) {    // channel mode\r\n        if (storeBackupSettings) {\r\n            initialFrqOrChan = gRxVfo->CHANNEL_SAVE;\r\n            lastFoundFrqOrChan = initialFrqOrChan;\r\n        }\r\n        NextMemChannel();\r\n    } else {    // frequency mode\r\n        if (storeBackupSettings) {\r\n            initialFrqOrChan = gRxVfo->freq_config_RX.Frequency;\r\n            lastFoundFrqOrChan = initialFrqOrChan;\r\n        }\r\n        NextFreqChannel();\r\n    }\r\n\r\n    gScanPauseDelayIn_10ms = scan_pause_delay_in_2_10ms;\r\n    gScheduleScanListen = false;\r\n    gRxReceptionMode = RX_MODE_NONE;\r\n    gScanPauseMode = false;\r\n}\r\n\r\nvoid CHFRSCANNER_ContinueScanning(void) {\r\n    if (IS_FREQ_CHANNEL(gNextMrChannel)) {\r\n        if (gCurrentFunction == FUNCTION_INCOMING)\r\n            APP_StartListening(gMonitor ? FUNCTION_MONITOR : FUNCTION_RECEIVE);\r\n        else\r\n            NextFreqChannel();  // switch to next frequency\r\n    } else {\r\n        if (gCurrentCodeType == CODE_TYPE_OFF && gCurrentFunction == FUNCTION_INCOMING)\r\n            APP_StartListening(gMonitor ? FUNCTION_MONITOR : FUNCTION_RECEIVE);\r\n        else\r\n            NextMemChannel();    // switch to next channel\r\n    }\r\n\r\n    gScanPauseMode = false;\r\n    gRxReceptionMode = RX_MODE_NONE;\r\n    gScheduleScanListen = false;\r\n}\r\n\r\nvoid CHFRSCANNER_Found(void) {\r\n    switch (gEeprom.SCAN_RESUME_MODE) {\r\n        case SCAN_RESUME_TO:\r\n            if (!gScanPauseMode) {\r\n                gScanPauseDelayIn_10ms = scan_pause_delay_in_1_10ms;\r\n                gScheduleScanListen = false;\r\n                gScanPauseMode = true;\r\n            }\r\n            break;\r\n\r\n        case SCAN_RESUME_CO:\r\n        case SCAN_RESUME_SE:\r\n            gScanPauseDelayIn_10ms = 0;\r\n            gScheduleScanListen = false;\r\n            break;\r\n    }\r\n\r\n    if (IS_MR_CHANNEL(gRxVfo->CHANNEL_SAVE)) { //memory scan\r\n        lastFoundFrqOrChan = gRxVfo->CHANNEL_SAVE;\r\n    } else { // frequency scan\r\n        lastFoundFrqOrChan = gRxVfo->freq_config_RX.Frequency;\r\n    }\r\n\r\n\r\n    gScanKeepResult = true;\r\n}\r\n\r\nvoid CHFRSCANNER_Stop(void) {\r\n    if (initialCROSS_BAND_RX_TX != CROSS_BAND_OFF) {\r\n        gEeprom.CROSS_BAND_RX_TX = initialCROSS_BAND_RX_TX;\r\n        initialCROSS_BAND_RX_TX = CROSS_BAND_OFF;\r\n    }\r\n\r\n    gScanStateDir = SCAN_OFF;\r\n\r\n    const uint32_t chFr = gScanKeepResult ? lastFoundFrqOrChan : initialFrqOrChan;\r\n    const bool channelChanged = chFr != initialFrqOrChan;\r\n    if (IS_MR_CHANNEL(gNextMrChannel)) {\r\n        gEeprom.MrChannel[gEeprom.RX_VFO] = chFr;\r\n        gEeprom.ScreenChannel[gEeprom.RX_VFO] = chFr;\r\n        RADIO_ConfigureChannel(gEeprom.RX_VFO, VFO_CONFIGURE_RELOAD);\r\n\r\n        if (channelChanged) {\r\n            SETTINGS_SaveVfoIndices();\r\n            gUpdateStatus = true;\r\n        }\r\n    } else {\r\n        gRxVfo->freq_config_RX.Frequency = chFr;\r\n        RADIO_ApplyOffset(gRxVfo);\r\n        RADIO_ConfigureSquelchAndOutputPower(gRxVfo);\r\n        if (channelChanged) {\r\n            SETTINGS_SaveChannel(gRxVfo->CHANNEL_SAVE, gEeprom.RX_VFO, gRxVfo, 1);\r\n        }\r\n    }\r\n\r\n    RADIO_SetupRegisters(true);\r\n    gUpdateDisplay = true;\r\n}\r\n\r\nstatic void NextFreqChannel(void) {\r\n#ifdef ENABLE_SCAN_RANGES\r\n    if(gScanRangeStart) {\r\n        gRxVfo->freq_config_RX.Frequency = APP_SetFreqByStepAndLimits(gRxVfo, gScanStateDir, gScanRangeStart, gScanRangeStop);\r\n    }\r\n    else\r\n#endif\r\n    gRxVfo->freq_config_RX.Frequency = APP_SetFrequencyByStep(gRxVfo, gScanStateDir);\r\n\r\n    RADIO_ApplyOffset(gRxVfo);\r\n    RADIO_ConfigureSquelchAndOutputPower(gRxVfo);\r\n    RADIO_SetupRegisters(true);\r\n\r\n#ifdef ENABLE_FASTER_CHANNEL_SCAN\r\n    gScanPauseDelayIn_10ms = 9;   // 90ms\r\n#else\r\n    gScanPauseDelayIn_10ms = scan_pause_delay_in_6_10ms;\r\n#endif\r\n\r\n    gUpdateDisplay = true;\r\n}\r\n\r\nstatic void NextMemChannel(void) {\r\n    static unsigned int prev_mr_chan = 0;\r\n    const bool enabled = (gEeprom.SCAN_LIST_DEFAULT < 2) ? gEeprom.SCAN_LIST_ENABLED[gEeprom.SCAN_LIST_DEFAULT] : true;\r\n    const int chan1 = (gEeprom.SCAN_LIST_DEFAULT < 2) ? gEeprom.SCANLIST_PRIORITY_CH1[gEeprom.SCAN_LIST_DEFAULT] : -1;\r\n    const int chan2 = (gEeprom.SCAN_LIST_DEFAULT < 2) ? gEeprom.SCANLIST_PRIORITY_CH2[gEeprom.SCAN_LIST_DEFAULT] : -1;\r\n    const unsigned int prev_chan = gNextMrChannel;\r\n    unsigned int chan = 0;\r\n\r\n    if (enabled) {\r\n        switch (currentScanList) {\r\n            case SCAN_NEXT_CHAN_SCANLIST1:\r\n                prev_mr_chan = gNextMrChannel;\r\n\r\n                if (chan1 >= 0) {\r\n                    if (RADIO_CheckValidChannel(chan1, false, 0)) {\r\n                        currentScanList = SCAN_NEXT_CHAN_SCANLIST1;\r\n                        gNextMrChannel = chan1;\r\n                        break;\r\n                    }\r\n                }\r\n                [[fallthrough]];\r\n            case SCAN_NEXT_CHAN_SCANLIST2:\r\n                if (chan2 >= 0) {\r\n                    if (RADIO_CheckValidChannel(chan2, false, 0)) {\r\n                        currentScanList = SCAN_NEXT_CHAN_SCANLIST2;\r\n                        gNextMrChannel = chan2;\r\n                        break;\r\n                    }\r\n                }\r\n                [[fallthrough]];\r\n\r\n                // this bit doesn't yet work if the other VFO is a frequency\r\n            case SCAN_NEXT_CHAN_DUAL_WATCH:\r\n                // dual watch is enabled - include the other VFO in the scan\r\n//\t\t\t\tif (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF)\r\n//\t\t\t\t{\r\n//\t\t\t\t\tchan = (gEeprom.RX_VFO + 1) & 1u;\r\n//\t\t\t\t\tchan = gEeprom.ScreenChannel[chan];\r\n//\t\t\t\t\tif (IS_MR_CHANNEL(chan))\r\n//\t\t\t\t\t{\r\n//\t\t\t\t\t\tcurrentScanList = SCAN_NEXT_CHAN_DUAL_WATCH;\r\n//\t\t\t\t\t\tgNextMrChannel   = chan;\r\n//\t\t\t\t\t\tbreak;\r\n//\t\t\t\t\t}\r\n//\t\t\t\t}\r\n\r\n            default:\r\n            case SCAN_NEXT_CHAN_MR:\r\n                currentScanList = SCAN_NEXT_CHAN_MR;\r\n                gNextMrChannel = prev_mr_chan;\r\n                chan = 0xff;\r\n                break;\r\n        }\r\n    }\r\n\r\n    if (!enabled || chan == 0xff) {\r\n        chan = RADIO_FindNextChannel(gNextMrChannel + gScanStateDir, gScanStateDir,\r\n                                     (gEeprom.SCAN_LIST_DEFAULT < 2) ? true : false, gEeprom.SCAN_LIST_DEFAULT);\r\n        if (chan == 0xFF) {    // no valid channel found\r\n            chan = MR_CHANNEL_FIRST;\r\n        }\r\n\r\n        gNextMrChannel = chan;\r\n    }\r\n\r\n    if (gNextMrChannel != prev_chan) {\r\n        gEeprom.MrChannel[gEeprom.RX_VFO] = gNextMrChannel;\r\n        gEeprom.ScreenChannel[gEeprom.RX_VFO] = gNextMrChannel;\r\n\r\n        RADIO_ConfigureChannel(gEeprom.RX_VFO, VFO_CONFIGURE_RELOAD);\r\n        RADIO_SetupRegisters(true);\r\n\r\n        gUpdateDisplay = true;\r\n    }\r\n\r\n#ifdef ENABLE_FASTER_CHANNEL_SCAN\r\n    gScanPauseDelayIn_10ms = 9;  // 90ms .. <= ~60ms it misses signals (squelch response and/or PLL lock time) ?\r\n#else\r\n    gScanPauseDelayIn_10ms = scan_pause_delay_in_3_10ms;\r\n#endif\r\n\r\n    if (enabled)\r\n        if (++currentScanList >= SCAN_NEXT_NUM)\r\n            currentScanList = SCAN_NEXT_CHAN_SCANLIST1;  // back round we go\r\n}"
  },
  {
    "path": "app/chFrScanner.h",
    "content": "#ifndef APP_CHFRSCANNER_H\r\n#define APP_CHFRSCANNER_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n// scan direction, if not equal SCAN_OFF indicates \r\n// that we are in a process of scanning channels/frequencies\r\nextern int8_t gScanStateDir;\r\nextern bool gScanKeepResult;\r\nextern bool gScanPauseMode;\r\n\r\n#ifdef ENABLE_SCAN_RANGES\r\nextern uint32_t          gScanRangeStart;\r\nextern uint32_t gScanRangeStop;\r\n#endif\r\n\r\nvoid CHFRSCANNER_Found(void);\r\n\r\nvoid CHFRSCANNER_Stop(void);\r\n\r\nvoid CHFRSCANNER_Start(const bool storeBackupSettings, const int8_t scan_direction);\r\n\r\nvoid CHFRSCANNER_ContinueScanning(void);\r\n\r\n#endif"
  },
  {
    "path": "app/common.c",
    "content": "#include \"app/chFrScanner.h\"\r\n#include \"audio.h\"\r\n#include \"functions.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/ui.h\"\r\n\r\nvoid COMMON_KeypadLockToggle() {\r\n\r\n    if (gScreenToDisplay != DISPLAY_MENU &&\r\n        gCurrentFunction != FUNCTION_TRANSMIT) {    // toggle the keyboad lock\r\n\r\n#ifdef ENABLE_VOICE\r\n        gAnotherVoiceID = gEeprom.KEY_LOCK ? VOICE_ID_UNLOCK : VOICE_ID_LOCK;\r\n#endif\r\n\r\n        gEeprom.KEY_LOCK = !gEeprom.KEY_LOCK;\r\n        //按键锁定禁止发射 取消\r\n        // RADIO_SetVfoState(VFO_STATE_NORMAL);\r\n\r\n        gRequestSaveSettings = true;\r\n    }\r\n}\r\n\r\nvoid COMMON_SwitchVFOs() {\r\n#ifdef ENABLE_SCAN_RANGES\r\n    gScanRangeStart = 0;\r\n#endif\r\n    gEeprom.TX_VFO ^= 1;\r\n\r\n    if (gEeprom.CROSS_BAND_RX_TX != CROSS_BAND_OFF)\r\n        gEeprom.CROSS_BAND_RX_TX = gEeprom.TX_VFO + 1;\r\n    if (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF)\r\n        gEeprom.DUAL_WATCH = gEeprom.TX_VFO + 1;\r\n\r\n    gRequestSaveSettings = 1;\r\n    gFlagReconfigureVfos = true;\r\n    gScheduleDualWatch = true;\r\n\r\n    gRequestDisplayScreen = DISPLAY_MAIN;\r\n}\r\n\r\nvoid COMMON_SwitchVFOMode() {\r\n#ifdef ENABLE_NOAA\r\n    if (gEeprom.VFO_OPEN && !IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE))\r\n#else\r\n    if (gEeprom.VFO_OPEN)\r\n#endif\r\n    {\r\n        if (IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) {    // swap to frequency mode\r\n            gEeprom.ScreenChannel[gEeprom.TX_VFO] = gEeprom.FreqChannel[gEeprom.TX_VFO];\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID        = VOICE_ID_FREQUENCY_MODE;\r\n#endif\r\n            gRequestSaveVFO = true;\r\n            gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\r\n            return;\r\n        }\r\n\r\n        uint8_t Channel = RADIO_FindNextChannel(gEeprom.MrChannel[gEeprom.TX_VFO], 1, false, 0);\r\n        if (Channel != 0xFF) {    // swap to channel mode\r\n            gEeprom.ScreenChannel[gEeprom.TX_VFO] = Channel;\r\n#ifdef ENABLE_VOICE\r\n            AUDIO_SetVoiceID(0, VOICE_ID_CHANNEL_MODE);\r\n            AUDIO_SetDigitVoice(1, Channel + 1);\r\n            gAnotherVoiceID = (VOICE_ID_t)0xFE;\r\n#endif\r\n            gRequestSaveVFO = true;\r\n            gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\r\n            return;\r\n        }\r\n    }\r\n}"
  },
  {
    "path": "app/common.h",
    "content": "\r\n#ifndef APP_COMMON_H\r\n#define APP_COMMON_H\r\n\r\n#include \"functions.h\"\r\n#include \"settings.h\"\r\n#include \"ui/ui.h\"\r\n\r\nvoid COMMON_KeypadLockToggle();\r\n\r\nvoid COMMON_SwitchVFOs();\r\n\r\nvoid COMMON_SwitchVFOMode();\r\n\r\n#endif"
  },
  {
    "path": "app/doppler.c",
    "content": "#include \"doppler.h\"\n#include \"string.h\"\n#include \"driver/eeprom.h\"\n#include \"bsp/dp32g030/rtc.h\"\n#include \"ui/helper.h\"\n\nstruct satellite_t satellite;\nstruct satellite_d satellite_data;\nbool DOPPLER_FLAG = true;\n//0x02BA0~0x2BA9 10B,卫星名称,首字符在前,最多9个英文，最后一个为'\\0'\n//\n//\n//0x2BAA 1B,开始过境时间的年份的十位个位，0~99，如:2024即为24\n//0x2BAB 1B,开始过境时间的月份，1~12\n//0x2BAC 1B,开始过境时间的日期，1~31\n//0x2BAD 1B,开始过境时间的时，0~23\n//0x2BAE 1B,开始过境时间的分，0~59\n//0x2BAF 1B,开始过境时间的秒，0~59\n//\n//0x2BB0 1B,离境时间的年份的十位个位，0~99，如:2077即为77\n//0x2BB1 1B,离境时间的月份，1~12\n//0x2BB2 1B,离境时间的日期，1~31\n//0x2BB3 1B,离境时间的时，0~23\n//0x2BB4 1B,离境时间的分，0~59\n//0x2BB5 1B,离境时间的秒，0~59\n//\n//0x2BB6~0x2BB7 2B，总的过境时间（秒），高位在前，低位在后\n//\n//0x2BB8~0x2BB9 2B，手台的发射亚音\n//0x2BBA~0x2BBB 2B，手台的接收亚音\n#include <stdint.h>\n\nvoid uint16_to_uint8_array(uint16_t value, uint8_t array[2]) {\n    array[0] = value & 0xFF;        // 获取低8位\n    array[1] = (value >> 8) & 0xFF; // 获取高8位\n}\n\nvoid INIT_DOPPLER_DATA() {\n    memset(&satellite, 0, sizeof(satellite));\n    EEPROM_ReadBuffer(0x02BA0, &satellite, sizeof(satellite));\n    if (satellite.name[9] != 0 ||\n        !(satellite.name[0] >= 32 && satellite.name[0] <= 126)\n            ) {\n        DOPPLER_FLAG = 0;\n        return;\n    }\n\n    for (int i = strlen(satellite.name); i < 10; i++)\n        if (satellite.name[i] != 0) {\n            DOPPLER_FLAG = 0;\n            return;\n        }\n\n\n}\n\n// 判断是否是闰年\nint is_leap_year(int year) {\n    return (year % 4 == 0 && year % 100 != 0) || (year % 400 == 0);\n}\n\n// 计算某个月的天数\nint days_in_month(int year, int month) {\n    int days[] = {31, 28 + is_leap_year(year), 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};\n    return days[month - 1];\n}\n\n\nint32_t UNIX_TIME(uint8_t time2[6]) {\n    // 2000 年 1 月 1 日的年、月、日、时、分、秒\n    int32_t seconds = 0;\n    // 计算年份之间的秒数差\n    for (int year = 0; year < time2[0]; year++) {\n        seconds += (is_leap_year(year) + 365) * 24 * 3600;\n    }\n\n    // 计算当年之内的秒数差\n    for (int month = 1; month < time2[1]; month++) {\n        seconds += days_in_month(time2[0], month) * 24 * 3600;\n    }\n    // 计算当月之内的秒数差\n    seconds += (time2[2] - 1) * 24 * 3600;\n    seconds += time2[3] * 3600;\n    seconds += time2[4] * 60;\n    seconds += time2[5];\n    return seconds;\n}\n\nvoid READ_DATA(int32_t time_diff, int32_t time_diff1) {\n    int32_t n = -time_diff;\n    if (time_diff <= 0 && time_diff1 >= 0)//正在过境\n    {\n\n        if ((n & 0x01) != 0)return;\n        n = n >> 1;\n    } else n = 0;\n\n    EEPROM_ReadBuffer(0x1E200 + (n << 3), &satellite_data, sizeof(satellite_data));\n\n//    AZ（-180~180，两位浮点，度）2B,EI（-180~180，两位浮点，度）2B,上行频率/10（正整数hz）4B、下行频率/10(正整数hz)4B、距离（两位浮点，km）3B：\n//    第1B~2B:AZ的数字部分，只有正，低位在前高位在后，\n//    低1~8位为AZ整数部分，8bit（0~180）\n//    低9~16位为AZ浮点部分，8bit（0~99）\n//    如：-179.85，那么为10110011（179）01010101（85）\n//\n//    第3B~4B:EI的数字部分,与AZ同理\n//    第5B:AZ,EI的符号，低位在前高位在后，前4bit为AZ符号，后4bit为EI符号\n//    4bit为0XA时表示正，0XC表示负\n//    第6B~9B:上行频率/10,只有正,如:438.5MHZ，那么为438,500,00，都是低位在前，高位在后\n//    第10B~13B:下行频率/10,只有正,如:144.5MHZ，那么为144,500,00，都是低位在前，高位在后\n//    第14B~15B:距离整数部分，只有正，如：6748.85，那么为6748\n//    第16B:距离浮点部分*100,只有正，如：6748.85，那么为85\n\n\n\n}"
  },
  {
    "path": "app/doppler.h",
    "content": "#ifndef _DOPPLER_\n#define _DOPPLER_\n\n#include \"stdint.h\"\n#include \"stdbool.h\"\n\nstruct satellite_t {\n    char name[10];\n    uint8_t start_time[6];\n    uint8_t end_time[6];\n    uint16_t sum_time;\n    uint16_t SEND_CTCSS;\n    uint16_t RECV_CTCSS;\n    uint32_t START_TIME_UNIX;\n};\nstruct satellite_d {\n\n    uint32_t UPLink;\n    uint32_t DownLink;\n\n};\n\nvoid READ_DATA(int32_t time_diff, int32_t time_diff1);\n\nvoid INIT_DOPPLER_DATA();\n\nint32_t UNIX_TIME(uint8_t time2[6]);\n\nextern struct satellite_d satellite_data;\nextern bool DOPPLER_FLAG;\nextern struct satellite_t satellite;\n#endif"
  },
  {
    "path": "app/dtmf.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#ifdef ENABLE_DOPPLER\r\n#include \"app/doppler.h\"\r\n#endif\r\n\r\n#include \"app/messenger.h\"\r\n#include <string.h>\r\n#include <stdio.h>   // NULL\r\n\r\n#include \"app/chFrScanner.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"app/scanner.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"audio.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/system.h\"\r\n#include \"dtmf.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/ui.h\"\r\n\r\nchar gDTMF_String[15];\r\n\r\nchar gDTMF_InputBox[15];\r\nuint8_t gDTMF_InputBox_Index = 0;\r\nbool gDTMF_InputMode = false;\r\nuint8_t gDTMF_PreviousIndex = 0;\r\n\r\nchar gDTMF_RX_live[20];\r\nuint8_t gDTMF_RX_live_timeout = 0;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\nchar              gDTMF_RX[17];\r\nuint8_t           gDTMF_RX_index   = 0;\r\nuint8_t           gDTMF_RX_timeout = 0;\r\nbool              gDTMF_RX_pending = false;\r\n\r\nbool              gIsDtmfContactValid;\r\nchar              gDTMF_ID[4];\r\nchar              gDTMF_Caller[4];\r\nchar              gDTMF_Callee[4];\r\nDTMF_State_t      gDTMF_State;\r\nuint8_t           gDTMF_DecodeRingCountdown_500ms;\r\nuint8_t           gDTMF_chosen_contact;\r\nuint8_t           gDTMF_auto_reset_time_500ms;\r\nDTMF_CallState_t  gDTMF_CallState;\r\nDTMF_CallMode_t   gDTMF_CallMode;\r\n\r\nbool              gDTMF_IsTx;\r\n\r\nuint8_t           gDTMF_TxStopCountdown_500ms;\r\nbool              gDTMF_IsGroupCall;\r\n#endif\r\nDTMF_ReplyState_t gDTMF_ReplyState;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\nvoid DTMF_clear_RX(void)\r\n{\r\n    gDTMF_RX_timeout = 0;\r\n    gDTMF_RX_index   = 0;\r\n    gDTMF_RX_pending = false;\r\n    memset(gDTMF_RX, 0, sizeof(gDTMF_RX));\r\n}\r\n#endif\r\n\r\nbool DTMF_ValidateCodes(char *pCode, const unsigned int size) {\r\n    unsigned int i;\r\n\r\n    if (pCode[0] == 0xFF || pCode[0] == 0)\r\n        return false;\r\n\r\n    for (i = 0; i < size; i++) {\r\n        if (pCode[i] == 0xFF || pCode[i] == 0) {\r\n            pCode[i] = 0;\r\n            break;\r\n        }\r\n\r\n        if ((pCode[i] < '0' || pCode[i] > '9') && (pCode[i] < 'A' || pCode[i] > 'D') && pCode[i] != '*' &&\r\n            pCode[i] != '#')\r\n            return false;\r\n    }\r\n\r\n    return true;\r\n}\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\nbool DTMF_GetContact(const int Index, char *pContact)\r\n{\r\n    if (Index < 0 || Index >= MAX_DTMF_CONTACTS || pContact == NULL) {\r\n        return false;\r\n    }\r\n\r\n    EEPROM_ReadBuffer(0x1C00 + (Index * 16), pContact, 16);\r\n\r\n#if ENABLE_CHINESE_FULL == 4\r\n    return pContact[0] != 0xff;\r\n#else\r\n    // check whether the first character is printable or not\r\n    return (pContact[0] >= ' ' && pContact[0] < 127);\r\n#endif\r\n}\r\nbool DTMF_FindContact(const char *pContact, char *pResult)\r\n{\r\n    pResult[0] = 0;\r\n\r\n    for (unsigned int i = 0; i < MAX_DTMF_CONTACTS; i++) {\r\n        char Contact[16];\r\n        if (!DTMF_GetContact(i, Contact)) {\r\n            return false;\r\n        }\r\n\r\n        if (memcmp(pContact, Contact + 8, 3) == 0) {\r\n            memcpy(pResult, Contact, 8);\r\n            pResult[8] = 0;\r\n            return true;\r\n        }\r\n    }\r\n\r\n    return false;\r\n}\r\n\r\n#endif\r\n\r\nchar DTMF_GetCharacter(const unsigned int code) {\r\n    switch (code) {\r\n        case KEY_0:\r\n            return '0';\r\n        case KEY_1:\r\n            return '1';\r\n        case KEY_2:\r\n            return '2';\r\n        case KEY_3:\r\n            return '3';\r\n        case KEY_4:\r\n            return '4';\r\n        case KEY_5:\r\n            return '5';\r\n        case KEY_6:\r\n            return '6';\r\n        case KEY_7:\r\n            return '7';\r\n        case KEY_8:\r\n            return '8';\r\n        case KEY_9:\r\n            return '9';\r\n        case KEY_MENU:\r\n            return 'A';\r\n        case KEY_UP:\r\n            return 'B';\r\n        case KEY_DOWN:\r\n            return 'C';\r\n        case KEY_EXIT:\r\n            return 'D';\r\n        case KEY_STAR:\r\n            return '*';\r\n        case KEY_F:\r\n            return '#';\r\n        default:\r\n            return 0xff;\r\n    }\r\n}\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\nstatic bool CompareMessage(const char *pMsg, const char *pTemplate, const unsigned int size, const bool bCheckGroup)\r\n{\r\n    unsigned int i;\r\n    for (i = 0; i < size; i++)\r\n    {\r\n        if (pMsg[i] != pTemplate[i])\r\n        {\r\n            if (!bCheckGroup || pMsg[i] != gEeprom.DTMF_GROUP_CALL_CODE)\r\n                return false;\r\n            gDTMF_IsGroupCall = true;\r\n        }\r\n    }\r\n\r\n    return true;\r\n}\r\n\r\nDTMF_CallMode_t DTMF_CheckGroupCall(const char *pMsg, const unsigned int size)\r\n{\r\n    unsigned int i;\r\n    for (i = 0; i < size; i++)\r\n        if (pMsg[i] == gEeprom.DTMF_GROUP_CALL_CODE)\r\n            break;\r\n\r\n    return (i < size) ? DTMF_CALL_MODE_GROUP : DTMF_CALL_MODE_NOT_GROUP;\r\n}\r\n#endif\r\n\r\nvoid DTMF_clear_input_box(void) {\r\n    memset(gDTMF_InputBox, 0, sizeof(gDTMF_InputBox));\r\n    gDTMF_InputBox_Index = 0;\r\n    gDTMF_InputMode = false;\r\n    gPttWasReleased = false;\r\n}\r\n\r\nvoid DTMF_Append(const char code) {\r\n    if (gDTMF_InputBox_Index == 0) {\r\n        memset(gDTMF_InputBox, '-', sizeof(gDTMF_InputBox) - 1);\r\n        gDTMF_InputBox[sizeof(gDTMF_InputBox) - 1] = 0;\r\n    }\r\n\r\n    if (gDTMF_InputBox_Index < (sizeof(gDTMF_InputBox) - 1))\r\n        gDTMF_InputBox[gDTMF_InputBox_Index++] = code;\r\n}\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\nvoid DTMF_HandleRequest(void)\r\n{\t// proccess the RX'ed DTMF characters\r\n\r\n    char         String[21];\r\n    unsigned int Offset;\r\n\r\n    if (!gDTMF_RX_pending)\r\n        return;   // nothing new received\r\n\r\n    if (gScanStateDir != SCAN_OFF || gCssBackgroundScan)\r\n    {\t// we're busy scanning\r\n        DTMF_clear_RX();\r\n        return;\r\n    }\r\n\r\n    if (!gRxVfo->DTMF_DECODING_ENABLE && !gSetting_KILLED)\r\n    {\t// D-DCD is disabled or we're alive\r\n        DTMF_clear_RX();\r\n        return;\r\n    }\r\n\r\n    gDTMF_RX_pending = false;\r\n\r\n    if (gDTMF_RX_index >= 9)\r\n    {\t// look for the KILL code\r\n\r\n        sprintf(String, \"%s%c%s\", gEeprom.ANI_DTMF_ID, gEeprom.DTMF_SEPARATE_CODE, gEeprom.KILL_CODE);\r\n\r\n        Offset = gDTMF_RX_index - strlen(String);\r\n\r\n        if (CompareMessage(gDTMF_RX + Offset, String, strlen(String), true))\r\n        {\t// bugger\r\n\r\n            if (gEeprom.PERMIT_REMOTE_KILL)\r\n            {\r\n                gSetting_KILLED = true;      // oooerr !\r\n\r\n                DTMF_clear_RX();\r\n\r\n                SETTINGS_SaveSettings();\r\n\r\n                gDTMF_ReplyState = DTMF_REPLY_AB;\r\n\r\n#ifdef ENABLE_FMRADIO\r\n                    if (gFmRadioMode)\r\n                    {\r\n                        FM_TurnOff();\r\n                        GUI_SelectNextDisplay(DISPLAY_MAIN);\r\n                    }\r\n#endif\r\n            }\r\n            else\r\n            {\r\n                gDTMF_ReplyState = DTMF_REPLY_NONE;\r\n            }\r\n\r\n            gDTMF_CallState = DTMF_CALL_STATE_NONE;\r\n\r\n            gUpdateDisplay  = true;\r\n            gUpdateStatus   = true;\r\n            return;\r\n        }\r\n    }\r\n\r\n    if (gDTMF_RX_index >= 9)\r\n    {\t// look for the REVIVE code\r\n\r\n        sprintf(String, \"%s%c%s\", gEeprom.ANI_DTMF_ID, gEeprom.DTMF_SEPARATE_CODE, gEeprom.REVIVE_CODE);\r\n\r\n        Offset = gDTMF_RX_index - strlen(String);\r\n\r\n        if (CompareMessage(gDTMF_RX + Offset, String, strlen(String), true))\r\n        {\t// shit, we're back !\r\n\r\n            gSetting_KILLED  = false;\r\n\r\n            DTMF_clear_RX();\r\n\r\n            SETTINGS_SaveSettings();\r\n\r\n            gDTMF_ReplyState = DTMF_REPLY_AB;\r\n            gDTMF_CallState  = DTMF_CALL_STATE_NONE;\r\n\r\n            gUpdateDisplay   = true;\r\n            gUpdateStatus    = true;\r\n            return;\r\n        }\r\n    }\r\n\r\n    if (gDTMF_RX_index >= 2)\r\n    {\t// look for ACK reply\r\n\r\nchar *pPrintStr = \"AB\";\r\n\r\n        Offset = gDTMF_RX_index - strlen(pPrintStr);\r\n\r\n        if (CompareMessage(gDTMF_RX + Offset, pPrintStr, strlen(pPrintStr), true)) {\r\n            // ends with \"AB\"\r\n\r\n            if (gDTMF_ReplyState != DTMF_REPLY_NONE)          // 1of11\r\n//\t\t\tif (gDTMF_CallState != DTMF_CALL_STATE_NONE)      // 1of11\r\n//\t\t\tif (gDTMF_CallState == DTMF_CALL_STATE_CALL_OUT)  // 1of11\r\n            {\r\n                gDTMF_State = DTMF_STATE_TX_SUCC;\r\n                DTMF_clear_RX();\r\n                gUpdateDisplay = true;\r\n                return;\r\n            }\r\n        }\r\n    }\r\n\r\n    if (gDTMF_CallState == DTMF_CALL_STATE_CALL_OUT &&\r\n        gDTMF_CallMode  == DTMF_CALL_MODE_NOT_GROUP &&\r\n        gDTMF_RX_index >= 9)\r\n    {\t// waiting for a reply\r\n\r\n        sprintf(String, \"%s%c%s\", gDTMF_String, gEeprom.DTMF_SEPARATE_CODE, \"AAAAA\");\r\n\r\n        Offset = gDTMF_RX_index - strlen(String);\r\n\r\n        if (CompareMessage(gDTMF_RX + Offset, String, strlen(String), false))\r\n        {\t// we got a response\r\n            gDTMF_State    = DTMF_STATE_CALL_OUT_RSP;\r\n            DTMF_clear_RX();\r\n            gUpdateDisplay = true;\r\n        }\r\n    }\r\n\r\n    if (gSetting_KILLED || gDTMF_CallState != DTMF_CALL_STATE_NONE)\r\n    {\t// we've been killed or expecting a reply\r\n        return;\r\n    }\r\n\r\n    if (gDTMF_RX_index >= 7)\r\n    {\t// see if we're being called\r\n\r\n        gDTMF_IsGroupCall = false;\r\n\r\n        sprintf(String, \"%s%c\", gEeprom.ANI_DTMF_ID, gEeprom.DTMF_SEPARATE_CODE);\r\n\r\n        Offset = gDTMF_RX_index - strlen(String) - 3;\r\n\r\n        if (CompareMessage(gDTMF_RX + Offset, String, strlen(String), true))\r\n        {\t// it's for us !\r\n\r\n            gDTMF_CallState = DTMF_CALL_STATE_RECEIVED;\r\n\r\n            memset(gDTMF_Callee, 0, sizeof(gDTMF_Callee));\r\n            memset(gDTMF_Caller, 0, sizeof(gDTMF_Caller));\r\n            memcpy(gDTMF_Callee, gDTMF_RX + Offset + 0, 3);\r\n            memcpy(gDTMF_Caller, gDTMF_RX + Offset + 4, 3);\r\n\r\n            DTMF_clear_RX();\r\n\r\n            gUpdateDisplay = true;\r\n\r\n            switch (gEeprom.DTMF_DECODE_RESPONSE)\r\n            {\r\n                case DTMF_DEC_RESPONSE_BOTH:\r\n                    gDTMF_DecodeRingCountdown_500ms = DTMF_decode_ring_countdown_500ms;\r\n                    [[fallthrough]];\r\n                case DTMF_DEC_RESPONSE_REPLY:\r\n                    gDTMF_ReplyState = DTMF_REPLY_AAAAA;\r\n                    break;\r\n                case DTMF_DEC_RESPONSE_RING:\r\n                    gDTMF_DecodeRingCountdown_500ms = DTMF_decode_ring_countdown_500ms;\r\n                    break;\r\n                default:\r\n                case DTMF_DEC_RESPONSE_NONE:\r\n                    gDTMF_DecodeRingCountdown_500ms = 0;\r\n                    gDTMF_ReplyState = DTMF_REPLY_NONE;\r\n                    break;\r\n            }\r\n\r\n            if (gDTMF_IsGroupCall)\r\n                gDTMF_ReplyState = DTMF_REPLY_NONE;\r\n        }\r\n    }\r\n}\r\n#endif\r\n\r\nbool DTMF_Reply() {\r\n    uint16_t Delay;\r\n#ifdef ENABLE_DTMF_CALLING\r\n    char        String[23];\r\n#endif\r\n    const char *pString = NULL;\r\n\r\n    switch (gDTMF_ReplyState) {\r\n        case DTMF_REPLY_ANI:\r\n#ifdef ENABLE_DTMF_CALLING\r\n            if (gDTMF_CallMode != DTMF_CALL_MODE_DTMF)\r\n            {\t// append our ID code onto the end of the DTMF code to send\r\n                sprintf(String, \"%s%c%s\", gDTMF_String, gEeprom.DTMF_SEPARATE_CODE, gEeprom.ANI_DTMF_ID);\r\n                pString = String;\r\n            }\r\n            else\r\n#endif\r\n        {\r\n            pString = gDTMF_String;\r\n        }\r\n\r\n            break;\r\n#ifdef ENABLE_DTMF_CALLING\r\n            case DTMF_REPLY_AB:\r\n            pString = \"AB\";\r\n            break;\r\n\r\n        case DTMF_REPLY_AAAAA:\r\n            sprintf(String, \"%s%c%s\", gEeprom.ANI_DTMF_ID, gEeprom.DTMF_SEPARATE_CODE, \"AAAAA\");\r\n            pString = String;\r\n            break;\r\n#endif\r\n        default:\r\n        case DTMF_REPLY_NONE:\r\n            if (\r\n#ifdef ENABLE_DTMF_CALLING\r\ngDTMF_CallState != DTMF_CALL_STATE_NONE           ||\r\n#endif\r\ngCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_APOLLO ||\r\ngCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_OFF ||\r\ngCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_TX_DOWN) {\r\n                gDTMF_ReplyState = DTMF_REPLY_NONE;\r\n                return false;\r\n            }\r\n\r\n            // send TX-UP DTMF\r\n            pString = gEeprom.DTMF_UP_CODE;\r\n            break;\r\n    }\r\n\r\n    gDTMF_ReplyState = DTMF_REPLY_NONE;\r\n\r\n    if (pString == NULL)\r\n        return false;\r\n\r\n    Delay = (gEeprom.DTMF_PRELOAD_TIME < 200) ? 200 : gEeprom.DTMF_PRELOAD_TIME;\r\n\r\n    if (gEeprom.DTMF_SIDE_TONE) {    // the user will also hear the transmitted tones\r\n        AUDIO_AudioPathOn();\r\n        gEnableSpeaker = true;\r\n    }\r\n\r\n    SYSTEM_DelayMs(Delay);\r\n\r\n    BK4819_EnterDTMF_TX(gEeprom.DTMF_SIDE_TONE);\r\n\r\n    BK4819_PlayDTMFString(\r\n            pString,\r\n            1,\r\n            gEeprom.DTMF_FIRST_CODE_PERSIST_TIME,\r\n            gEeprom.DTMF_HASH_CODE_PERSIST_TIME,\r\n            gEeprom.DTMF_CODE_PERSIST_TIME,\r\n            gEeprom.DTMF_CODE_INTERVAL_TIME);\r\n\r\n    AUDIO_AudioPathOff();\r\n\r\n    gEnableSpeaker = false;\r\n\r\n    BK4819_ExitDTMF_TX(false);\r\n    return true;\r\n\r\n}\r\n\r\nvoid DTMF_SendEndOfTransmission(void) {\r\n#ifdef  ENABLE_MESSENGER\r\n\r\n    if(!stop_mdc_flag) {\r\n#endif\r\n    if (gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_APOLLO) {\r\n        BK4819_PlaySingleTone(2475, 250, 28, gEeprom.DTMF_SIDE_TONE);\r\n    } else if ((gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_TX_DOWN ||\r\n                gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_BOTH)\r\n#ifdef ENABLE_DTMF_CALLING\r\n        && gDTMF_CallState == DTMF_CALL_STATE_NONE\r\n#endif\r\n            ) {    // end-of-tx\r\n        if (gEeprom.DTMF_SIDE_TONE) {\r\n            AUDIO_AudioPathOn();\r\n            gEnableSpeaker = true;\r\n            SYSTEM_DelayMs(60);\r\n        }\r\n\r\n        BK4819_EnterDTMF_TX(gEeprom.DTMF_SIDE_TONE);\r\n\r\n        BK4819_PlayDTMFString(\r\n                gEeprom.DTMF_DOWN_CODE,\r\n                0,\r\n                gEeprom.DTMF_FIRST_CODE_PERSIST_TIME,\r\n                gEeprom.DTMF_HASH_CODE_PERSIST_TIME,\r\n                gEeprom.DTMF_CODE_PERSIST_TIME,\r\n                gEeprom.DTMF_CODE_INTERVAL_TIME);\r\n\r\n        AUDIO_AudioPathOff();\r\n        gEnableSpeaker = false;\r\n    }\r\n#ifdef  ENABLE_MESSENGER\r\n\r\n    }\r\n#endif\r\n\r\n    BK4819_ExitDTMF_TX(true);\r\n}"
  },
  {
    "path": "app/dtmf.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DTMF_H\r\n#define DTMF_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n#define    MAX_DTMF_CONTACTS   16\r\n\r\nenum DTMF_State_t {\r\n    DTMF_STATE_0 = 0,\r\n    DTMF_STATE_TX_SUCC,\r\n    DTMF_STATE_CALL_OUT_RSP\r\n};\r\n\r\ntypedef enum DTMF_State_t DTMF_State_t;\r\n\r\nenum DTMF_CallState_t {\r\n    DTMF_CALL_STATE_NONE = 0,\r\n    DTMF_CALL_STATE_CALL_OUT,\r\n    DTMF_CALL_STATE_RECEIVED,\r\n    DTMF_CALL_STATE_RECEIVED_STAY\r\n};\r\n\r\nenum DTMF_DecodeResponse_t {\r\n    DTMF_DEC_RESPONSE_NONE = 0,\r\n    DTMF_DEC_RESPONSE_RING,\r\n    DTMF_DEC_RESPONSE_REPLY,\r\n    DTMF_DEC_RESPONSE_BOTH\r\n};\r\n\r\ntypedef enum DTMF_CallState_t DTMF_CallState_t;\r\n\r\nenum DTMF_ReplyState_t {\r\n    DTMF_REPLY_NONE = 0,\r\n    DTMF_REPLY_ANI,\r\n    DTMF_REPLY_AB,\r\n    DTMF_REPLY_AAAAA\r\n};\r\n\r\ntypedef enum DTMF_ReplyState_t DTMF_ReplyState_t;\r\n\r\nenum DTMF_CallMode_t {\r\n    DTMF_CALL_MODE_NOT_GROUP = 0,\r\n    DTMF_CALL_MODE_GROUP,\r\n    DTMF_CALL_MODE_DTMF\r\n};\r\n\r\nenum {  // seconds\r\n    DTMF_HOLD_MIN = 5,\r\n    DTMF_HOLD_MAX = 60\r\n};\r\n\r\ntypedef enum DTMF_CallMode_t DTMF_CallMode_t;\r\n\r\nextern char gDTMF_String[15];\r\n\r\nextern char gDTMF_InputBox[15];\r\nextern uint8_t gDTMF_InputBox_Index;\r\nextern bool gDTMF_InputMode;\r\nextern uint8_t gDTMF_PreviousIndex;\r\n\r\nextern char gDTMF_RX_live[20];\r\nextern uint8_t gDTMF_RX_live_timeout;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\nextern char              gDTMF_RX[17];\r\nextern uint8_t           gDTMF_RX_index;\r\nextern uint8_t           gDTMF_RX_timeout;\r\nextern bool              gDTMF_RX_pending;\r\n\r\nextern bool              gIsDtmfContactValid;\r\nextern char              gDTMF_ID[4];\r\nextern char              gDTMF_Caller[4];\r\nextern char              gDTMF_Callee[4];\r\nextern DTMF_State_t      gDTMF_State;\r\nextern uint8_t           gDTMF_DecodeRingCountdown_500ms;\r\nextern uint8_t           gDTMF_chosen_contact;\r\nextern uint8_t           gDTMF_auto_reset_time_500ms;\r\nextern DTMF_CallState_t  gDTMF_CallState;\r\n\r\nextern DTMF_CallMode_t   gDTMF_CallMode;\r\nextern bool              gDTMF_IsTx;\r\nextern uint8_t           gDTMF_TxStopCountdown_500ms;\r\n#endif\r\nextern DTMF_ReplyState_t gDTMF_ReplyState;\r\n\r\nbool DTMF_ValidateCodes(char *pCode, const unsigned int size);\r\n\r\nchar DTMF_GetCharacter(const unsigned int code);\r\n\r\nvoid DTMF_clear_input_box(void);\r\n\r\nvoid DTMF_Append(const char vode);\r\n\r\nbool DTMF_Reply();\r\n\r\nvoid DTMF_SendEndOfTransmission(void);\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\nvoid DTMF_clear_RX(void);\r\nDTMF_CallMode_t DTMF_CheckGroupCall(const char *pDTMF, const unsigned int size);\r\nbool DTMF_GetContact(const int Index, char *pContact);\r\nbool DTMF_FindContact(const char *pContact, char *pResult);\r\nvoid DTMF_HandleRequest(void);\r\n#endif\r\n\r\n#endif"
  },
  {
    "path": "app/flashlight.c",
    "content": "#ifdef ENABLE_FLASHLIGHT\n\n#include \"driver/gpio.h\"\n#include \"bsp/dp32g030/gpio.h\"\n\n#include \"flashlight.h\"\n\nenum FlashlightMode_t  gFlashLightState;\n\nvoid FlashlightTimeSlice()\n{\n    if (gFlashLightState == FLASHLIGHT_BLINK && (gFlashLightBlinkCounter & 15u) == 0) {\n        GPIO_FlipBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT);\n        return;\n    }\n\n    if (gFlashLightState == FLASHLIGHT_SOS) {\n        const uint16_t u = 15;\n        static uint8_t c;\n        static uint16_t next;\n\n        if (gFlashLightBlinkCounter - next > 7 * u) {\n            c = 0;\n            next = gFlashLightBlinkCounter + 1;\n            return;\n        }\n\n        if (gFlashLightBlinkCounter == next) {\n            if (c==0) {\n                GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT);\n            } else {\n                GPIO_FlipBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT);\n            }\n\n            if (c >= 18) {\n                next = gFlashLightBlinkCounter + 7 * u;\n                c = 0;\n            } else if(c==7 || c==9 || c==11) {\n                next = gFlashLightBlinkCounter + 3 * u;\n            } else {\n                next = gFlashLightBlinkCounter + u;\n            }\n            c++;\n        }\n    }\n}\n\nvoid ACTION_FlashLight(void)\n{\n    if(gFlashLightState)\n        {\n        GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT);\ngFlashLightState=0;\n\n        }else\n            {\n        GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT);\n        gFlashLightState=1;\n            }\n//\tswitch (gFlashLightState) {\n//\t\tcase FLASHLIGHT_OFF:\n//\t\t\tgFlashLightState++;\n//\t\t\tGPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT);\n//\t\t\tbreak;\n//\t\tcase FLASHLIGHT_ON:\n////\t\tcase FLASHLIGHT_BLINK:\n//\t\t\tgFlashLightState++;\n//\t\t\tbreak;\n////\t\tcase FLASHLIGHT_SOS:\n//\t\tdefault:\n//\t\t\tgFlashLightState = 0;\n//\t\t\tGPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_FLASHLIGHT);\n//\t}\n}\n\n#endif"
  },
  {
    "path": "app/flashlight.h",
    "content": "#ifndef APP_FLASHLIGHT_H\n#define APP_FLASHLIGHT_H\n\n#ifdef ENABLE_FLASHLIGHT\n\n#include <stdint.h>\n\nenum FlashlightMode_t {\n    FLASHLIGHT_OFF = 0,\n    FLASHLIGHT_ON,\n    FLASHLIGHT_BLINK,\n    FLASHLIGHT_SOS\n};\n\nextern enum FlashlightMode_t gFlashLightState;\nextern volatile uint16_t     gFlashLightBlinkCounter;\n\nvoid FlashlightTimeSlice(void);\nvoid ACTION_FlashLight(void);\n\n#endif\n\n#endif"
  },
  {
    "path": "app/fm.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifdef ENABLE_FMRADIO\r\n\r\n#include <string.h>\r\n\r\n#include \"app/action.h\"\r\n#include \"app/fm.h\"\r\n#include \"app/generic.h\"\r\n#include \"audio.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/bk1080.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"functions.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/ui.h\"\r\n\r\n#ifndef ARRAY_SIZE\r\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r\n#endif\r\n\r\nuint16_t          gFM_Channels[20];\r\nbool              gFmRadioMode;\r\nuint8_t           gFmRadioCountdown_500ms;\r\nvolatile uint16_t gFmPlayCountdown_10ms;\r\nvolatile int8_t   gFM_ScanState;\r\nbool              gFM_AutoScan;\r\nuint8_t           gFM_ChannelPosition;\r\nbool              gFM_FoundFrequency;\r\nbool              gFM_AutoScan;\r\nuint16_t          gFM_RestoreCountdown_10ms;\r\n\r\n\r\n\r\nconst uint8_t BUTTON_STATE_PRESSED = 1 << 0;\r\nconst uint8_t BUTTON_STATE_HELD = 1 << 1;\r\n\r\nconst uint8_t BUTTON_EVENT_PRESSED = BUTTON_STATE_PRESSED;\r\nconst uint8_t BUTTON_EVENT_HELD = BUTTON_STATE_PRESSED | BUTTON_STATE_HELD;\r\nconst uint8_t BUTTON_EVENT_SHORT =  0;\r\nconst uint8_t BUTTON_EVENT_LONG =  BUTTON_STATE_HELD;\r\n\r\n\r\nstatic void Key_FUNC(KEY_Code_t Key, uint8_t state);\r\n\r\nbool FM_CheckValidChannel(uint8_t Channel)\r\n{\r\nreturn (Channel < ARRAY_SIZE(gFM_Channels) && (gFM_Channels[Channel] >= 640 && gFM_Channels[Channel] < 1080));\r\n}\r\n\r\nuint8_t FM_FindNextChannel(uint8_t Channel, uint8_t Direction)\r\n{\r\n    unsigned int i;\r\n\r\n    for (i = 0; i < ARRAY_SIZE(gFM_Channels); i++)\r\n    {\r\n        if (Channel == 0xFF)\r\n            Channel = ARRAY_SIZE(gFM_Channels) - 1;\r\n        else\r\n        if (Channel >= ARRAY_SIZE(gFM_Channels))\r\n            Channel = 0;\r\n        if (FM_CheckValidChannel(Channel))\r\n            return Channel;\r\n        Channel += Direction;\r\n    }\r\n\r\n    return 0xFF;\r\n}\r\n\r\nint FM_ConfigureChannelState(void)\r\n{\r\n    gEeprom.FM_FrequencyPlaying = gEeprom.FM_SelectedFrequency;\r\n\r\n    if (gEeprom.FM_IsMrMode)\r\n    {\r\n        const uint8_t Channel = FM_FindNextChannel(gEeprom.FM_SelectedChannel, FM_CHANNEL_UP);\r\n        if (Channel == 0xFF)\r\n        {\r\n            gEeprom.FM_IsMrMode = false;\r\n            return -1;\r\n        }\r\n        gEeprom.FM_SelectedChannel  = Channel;\r\n        gEeprom.FM_FrequencyPlaying = gFM_Channels[Channel];\r\n    }\r\n\r\n    return 0;\r\n}\r\n\r\nvoid FM_TurnOff(void)\r\n{\r\n    gFmRadioMode              = false;\r\n    gFM_ScanState             = FM_SCAN_OFF;\r\n    gFM_RestoreCountdown_10ms = 0;\r\n\r\n    AUDIO_AudioPathOff();\r\n\r\n    gEnableSpeaker = false;\r\n\r\n    BK1080_Init(0, false);\r\n\r\n    gUpdateStatus  = true;\r\n}\r\n\r\nvoid FM_EraseChannels(void)\r\n{\r\n    unsigned int i;\r\n    uint8_t      Template[8];\r\n\r\n    memset(Template, 0xFF, sizeof(Template));\r\n    for (i = 0; i < 5; i++)\r\n        EEPROM_WriteBuffer(0x0E40 + (i * 8), Template,8);\r\n\r\n    memset(gFM_Channels, 0xFF, sizeof(gFM_Channels));\r\n}\r\n\r\nvoid FM_Tune(uint16_t Frequency, int8_t Step, bool bFlag)\r\n{\r\n    AUDIO_AudioPathOff();\r\n\r\n    gEnableSpeaker = false;\r\n\r\n    gFmPlayCountdown_10ms = (gFM_ScanState == FM_SCAN_OFF) ? fm_play_countdown_noscan_10ms : fm_play_countdown_scan_10ms;\r\n\r\n    gScheduleFM                 = false;\r\n    gFM_FoundFrequency          = false;\r\n    gAskToSave                  = false;\r\n    gAskToDelete                = false;\r\n    gEeprom.FM_FrequencyPlaying = Frequency;\r\n\r\n    if (!bFlag)\r\n    {\r\n        Frequency += Step;\r\n        if (Frequency < gEeprom.FM_LowerLimit)\r\n            Frequency = gEeprom.FM_UpperLimit;\r\n        else\r\n        if (Frequency > gEeprom.FM_UpperLimit)\r\n            Frequency = gEeprom.FM_LowerLimit;\r\n\r\n        gEeprom.FM_FrequencyPlaying = Frequency;\r\n    }\r\n\r\n    gFM_ScanState = Step;\r\n\r\n    BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying);\r\n}\r\n\r\nvoid FM_PlayAndUpdate(void)\r\n{\r\n    gFM_ScanState = FM_SCAN_OFF;\r\n\r\n    if (gFM_AutoScan)\r\n    {\r\n        gEeprom.FM_IsMrMode        = true;\r\n        gEeprom.FM_SelectedChannel = 0;\r\n    }\r\n\r\n    FM_ConfigureChannelState();\r\n    BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying);\r\n    SETTINGS_SaveFM();\r\n\r\n    gFmPlayCountdown_10ms = 0;\r\n    gScheduleFM           = false;\r\n    gAskToSave            = false;\r\n\r\n    AUDIO_AudioPathOn();\r\n\r\n    gEnableSpeaker   = true;\r\n}\r\n\r\nint FM_CheckFrequencyLock(uint16_t Frequency, uint16_t LowerLimit)\r\n{\r\n    int ret = -1;\r\n\r\n    const uint16_t Test2 = BK1080_ReadRegister(BK1080_REG_07);\r\n\r\n    // This is supposed to be a signed value, but above function is unsigned\r\n    const uint16_t Deviation = BK1080_REG_07_GET_FREQD(Test2);\r\nif (BK1080_REG_07_GET_SNR(Test2) <= 2){\r\n        goto Bail;\r\n    }\r\n\r\n    const uint16_t Status = BK1080_ReadRegister(BK1080_REG_10);\r\n\r\n    if ((Status & BK1080_REG_10_MASK_AFCRL) != BK1080_REG_10_AFCRL_NOT_RAILED || BK1080_REG_10_GET_RSSI(Status) < 10) {\r\n        goto Bail;\r\n    }\r\n\r\n    //if (Deviation > -281 && Deviation < 280)\r\n    if (Deviation >= 280 && Deviation <= 3815) {\r\n        goto Bail;\r\n    }\r\n\r\n    // not BLE(less than or equal)\r\n    if (Frequency > LowerLimit && (Frequency - BK1080_BaseFrequency) == 1) {\r\n        if (BK1080_FrequencyDeviation & 0x800 || (BK1080_FrequencyDeviation < 20))\r\n            goto Bail;\r\n    }\r\n\r\n    // not BLT(less than)\r\n\r\n    if (Frequency >= LowerLimit && (BK1080_BaseFrequency - Frequency) == 1) {\r\n        if ((BK1080_FrequencyDeviation & 0x800) == 0 || (BK1080_FrequencyDeviation > 4075))\r\n            goto Bail;\r\n\r\n    }\r\nret = 0;\r\nBail:\r\n    BK1080_FrequencyDeviation = Deviation;\r\n    BK1080_BaseFrequency      = Frequency;\r\n\r\n    return ret;\r\n}\r\n\r\nstatic void Key_DIGITS(KEY_Code_t Key, uint8_t state)\r\n{\r\n    enum { STATE_FREQ_MODE, STATE_MR_MODE, STATE_SAVE };\r\n\r\n    if (state == BUTTON_EVENT_SHORT && !gWasFKeyPressed) {\r\n            uint8_t State;\r\n\r\n            if (gAskToDelete) {\r\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n                return;\r\n            }\r\n\r\n            if (gAskToSave) {\r\n                State = STATE_SAVE;\r\n            }\r\n            else {\r\n                if (gFM_ScanState != FM_SCAN_OFF) {\r\n                    gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n                    return;\r\n                }\r\n\r\n                State = gEeprom.FM_IsMrMode ? STATE_MR_MODE : STATE_FREQ_MODE;\r\n            }\r\n\r\n            INPUTBOX_Append(Key);\r\n\r\n            gRequestDisplayScreen = DISPLAY_FM;\r\n\r\n            if (State == STATE_FREQ_MODE) {\r\n                if (gInputBoxIndex == 1) {\r\n                    if (gInputBox[0] > 1) {\r\n                        gInputBox[1] = gInputBox[0];\r\n                        gInputBox[0] = 0;\r\n                        gInputBoxIndex = 2;\r\n                    }\r\n                }\r\n                else if (gInputBoxIndex > 3) {\r\n                    uint32_t Frequency;\r\n\r\n                    gInputBoxIndex = 0;\r\n                    Frequency = StrToUL(INPUTBOX_GetAscii());\r\n\r\n                    if (Frequency < gEeprom.FM_LowerLimit || gEeprom.FM_UpperLimit < Frequency) {\r\n                        gBeepToPlay           = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n                        gRequestDisplayScreen = DISPLAY_FM;\r\n                        return;\r\n                    }\r\n\r\n                    gEeprom.FM_SelectedFrequency = (uint16_t)Frequency;\r\n#ifdef ENABLE_VOICE\r\n                    gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n                    gEeprom.FM_FrequencyPlaying = gEeprom.FM_SelectedFrequency;\r\n                    BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying);\r\n                    gRequestSaveFM = true;\r\n                    return;\r\n                }\r\n            }\r\n            else if (gInputBoxIndex == 2) {\r\n                uint8_t Channel;\r\n\r\n                gInputBoxIndex = 0;\r\n                Channel = ((gInputBox[0] * 10) + gInputBox[1]) - 1;\r\n\r\n                if (State == STATE_MR_MODE) {\r\n                    if (FM_CheckValidChannel(Channel)) {\r\n#ifdef ENABLE_VOICE\r\n                        gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n                        gEeprom.FM_SelectedChannel = Channel;\r\n                        gEeprom.FM_FrequencyPlaying = gFM_Channels[Channel];\r\n                        BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying);\r\n                        gRequestSaveFM = true;\r\n                        return;\r\n                    }\r\n                }\r\n                else if (Channel < 20) {\r\n#ifdef ENABLE_VOICE\r\n                    gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n                    gRequestDisplayScreen = DISPLAY_FM;\r\n                    gInputBoxIndex = 0;\r\n                    gFM_ChannelPosition = Channel;\r\n                    return;\r\n                }\r\n\r\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n                return;\r\n            }\r\n\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n    }\r\n    else\r\n        Key_FUNC(Key, state);\r\n}\r\n\r\nstatic void Key_FUNC(KEY_Code_t Key, uint8_t state)\r\n{\r\nif (state == BUTTON_EVENT_SHORT || state == BUTTON_EVENT_HELD)\r\n{\r\n        bool autoScan = gWasFKeyPressed || (state == BUTTON_EVENT_HELD);\r\n\r\n        gBeepToPlay           = BEEP_1KHZ_60MS_OPTIONAL;\r\n        gWasFKeyPressed       = false;\r\n        gUpdateStatus         = true;\r\n        gRequestDisplayScreen = DISPLAY_FM;\r\n\r\n        switch (Key) {\r\n            case KEY_0:\r\n                ACTION_FM();\r\n                break;\r\n\r\n            case KEY_3:\r\n                gEeprom.FM_IsMrMode = !gEeprom.FM_IsMrMode;\r\n\r\n                if (!FM_ConfigureChannelState())\r\n                {\r\n                    BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying);\r\n                    gRequestSaveFM = true;\r\n                }\r\n                else\r\n                    gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n                break;\r\n\r\n            case KEY_STAR:\r\n                ACTION_Scan(autoScan);\r\n                break;\r\n\r\n            default:\r\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n                break;\r\n        }\r\n    }\r\n}\r\n\r\nstatic void Key_EXIT(uint8_t state)\r\n{\r\n    if (state != BUTTON_EVENT_SHORT)\r\n        return;\r\n\r\n    gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n\r\n    if (gFM_ScanState == FM_SCAN_OFF)\r\n    {\r\n        if (gInputBoxIndex == 0)\r\n        {\r\n            if (!gAskToSave && !gAskToDelete)\r\n            {\r\n                ACTION_FM();\r\n                return;\r\n            }\r\n\r\n            gAskToSave   = false;\r\n            gAskToDelete = false;\r\n        }\r\n        else\r\n        {\r\n            gInputBox[--gInputBoxIndex] = 10;\r\n\r\n            if (gInputBoxIndex)\r\n            {\r\n                if (gInputBoxIndex != 1)\r\n                {\r\n                    gRequestDisplayScreen = DISPLAY_FM;\r\n                    return;\r\n                }\r\n\r\n                if (gInputBox[0] != 0)\r\n                {\r\n                    gRequestDisplayScreen = DISPLAY_FM;\r\n                    return;\r\n                }\r\n            }\r\n\r\n            gInputBoxIndex = 0;\r\n        }\r\n\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID = VOICE_ID_CANCEL;\r\n#endif\r\n    }\r\n    else\r\n    {\r\n        FM_PlayAndUpdate();\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID = VOICE_ID_SCANNING_STOP;\r\n#endif\r\n    }\r\n\r\n    gRequestDisplayScreen = DISPLAY_FM;\r\n}\r\n\r\nstatic void Key_MENU(uint8_t state)\r\n{\r\n    if (state != BUTTON_EVENT_SHORT)\r\n        return;\r\n\r\n\r\n    gRequestDisplayScreen = DISPLAY_FM;\r\n    gBeepToPlay           = BEEP_1KHZ_60MS_OPTIONAL;\r\n\r\n    if (gFM_ScanState == FM_SCAN_OFF)\r\n    {\r\n        if (!gEeprom.FM_IsMrMode)\r\n        {\r\n            if (gAskToSave)\r\n            {\r\n                gFM_Channels[gFM_ChannelPosition] = gEeprom.FM_FrequencyPlaying;\r\n        gRequestSaveFM = true;\r\n\r\n            }\r\ngAskToSave = !gAskToSave;\r\n        }\r\n        else\r\n        {\r\n            if (gAskToDelete)\r\n            {\r\n                gFM_Channels[gEeprom.FM_SelectedChannel] = 0xFFFF;\r\n\r\n                FM_ConfigureChannelState();\r\n                BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying);\r\n\r\n                gRequestSaveFM = true;\r\n            }\r\n    gAskToDelete = !gAskToDelete;\r\n        }\r\n    }\r\n    else\r\n    {\r\n        if (gFM_AutoScan || !gFM_FoundFrequency)\r\n        {\r\n            gBeepToPlay    = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n            gInputBoxIndex = 0;\r\n            return;\r\n        }\r\n\r\n        if (gAskToSave)\r\n        {\r\n            gFM_Channels[gFM_ChannelPosition] = gEeprom.FM_FrequencyPlaying;\r\n            gRequestSaveFM = true;\r\n        }\r\ngAskToSave = !gAskToSave;\r\n    }\r\n}\r\n\r\nstatic void Key_UP_DOWN(uint8_t state, int8_t Step)\r\n{\r\n    if (state == BUTTON_EVENT_PRESSED) {\r\n        if (gInputBoxIndex) {\r\n            gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n            return;\r\n        }\r\n\r\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n    } else if (gInputBoxIndex || state!=BUTTON_EVENT_HELD) {\r\n        return;\r\n    }\r\n\r\n    if (gAskToSave) {\r\n        gRequestDisplayScreen = DISPLAY_FM;\r\n        gFM_ChannelPosition   = NUMBER_AddWithWraparound(gFM_ChannelPosition, Step, 0, 19);\r\n        return;\r\n    }\r\n\r\n    if (gFM_ScanState != FM_SCAN_OFF) {\r\n        if (gFM_AutoScan) {\r\n            gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n            return;\r\n        }\r\n\r\n        FM_Tune(gEeprom.FM_FrequencyPlaying, Step, false);\r\n        gRequestDisplayScreen = DISPLAY_FM;\r\n        return;\r\n    }\r\n\r\n    if (gEeprom.FM_IsMrMode) {\r\n        const uint8_t Channel = FM_FindNextChannel(gEeprom.FM_SelectedChannel + Step, Step);\r\n        if (Channel == 0xFF || gEeprom.FM_SelectedChannel == Channel)\r\n            goto Bail;\r\n\r\n        gEeprom.FM_SelectedChannel  = Channel;\r\n        gEeprom.FM_FrequencyPlaying = gFM_Channels[Channel];\r\n    }\r\n    else {\r\n        uint16_t Frequency = gEeprom.FM_SelectedFrequency + Step;\r\n        if (Frequency < gEeprom.FM_LowerLimit)\r\n            Frequency = gEeprom.FM_UpperLimit;\r\n        else\r\n        if (Frequency > gEeprom.FM_UpperLimit)\r\n            Frequency = gEeprom.FM_LowerLimit;\r\n\r\n        gEeprom.FM_FrequencyPlaying  = Frequency;\r\n        gEeprom.FM_SelectedFrequency = gEeprom.FM_FrequencyPlaying;\r\n    }\r\n\r\n    gRequestSaveFM = true;\r\n\r\nBail:\r\n    BK1080_SetFrequency(gEeprom.FM_FrequencyPlaying);\r\n\r\n    gRequestDisplayScreen = DISPLAY_FM;\r\n}\r\n\r\nvoid FM_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld)\r\n{\r\n    uint8_t state = bKeyPressed + 2 * bKeyHeld;\r\n\r\n    switch (Key)\r\n    {\r\n        case KEY_0:\r\n        case KEY_1:\r\n        case KEY_2:\r\n        case KEY_3:\r\n        case KEY_4:\r\n        case KEY_5:\r\n        case KEY_6:\r\n        case KEY_7:\r\n        case KEY_8:\r\n        case KEY_9:\r\n            Key_DIGITS(Key, state);\r\n            break;\r\n        case KEY_STAR:\r\n            Key_FUNC(Key, state);\r\n            break;\r\n        case KEY_MENU:\r\n            Key_MENU(state);\r\n            break;\r\n        case KEY_UP:\r\n            Key_UP_DOWN(state, 1);\r\n            break;\r\n        case KEY_DOWN:\r\n            Key_UP_DOWN(state, -1);\r\n            break;;\r\n        case KEY_EXIT:\r\n            Key_EXIT(state);\r\n            break;\r\n        case KEY_F:\r\n            GENERIC_Key_F(bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_PTT:\r\n            GENERIC_Key_PTT(bKeyPressed);\r\n            break;\r\n        default:\r\n            if (!bKeyHeld && bKeyPressed)\r\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n            break;\r\n    }\r\n}\r\n\r\nvoid FM_Play(void)\r\n{\r\n    if (!FM_CheckFrequencyLock(gEeprom.FM_FrequencyPlaying, gEeprom.FM_LowerLimit))\r\n    {\r\n        if (!gFM_AutoScan)\r\n        {\r\n            gFmPlayCountdown_10ms = 0;\r\n            gFM_FoundFrequency    = true;\r\n\r\n            if (!gEeprom.FM_IsMrMode)\r\n                gEeprom.FM_SelectedFrequency = gEeprom.FM_FrequencyPlaying;\r\n\r\n            AUDIO_AudioPathOn();\r\n            gEnableSpeaker = true;\r\n\r\n            GUI_SelectNextDisplay(DISPLAY_FM);\r\n            return;\r\n        }\r\n\r\n        if (gFM_ChannelPosition < 20)\r\n            gFM_Channels[gFM_ChannelPosition++] = gEeprom.FM_FrequencyPlaying;\r\n\r\n        if (gFM_ChannelPosition >= 20)\r\n        {\r\n            FM_PlayAndUpdate();\r\n            GUI_SelectNextDisplay(DISPLAY_FM);\r\n            return;\r\n        }\r\n    }\r\n\r\n    if (gFM_AutoScan && gEeprom.FM_FrequencyPlaying >= gEeprom.FM_UpperLimit)\r\n        FM_PlayAndUpdate();\r\n    else\r\n        FM_Tune(gEeprom.FM_FrequencyPlaying, gFM_ScanState, false);\r\n\r\n    GUI_SelectNextDisplay(DISPLAY_FM);\r\n}\r\n\r\nvoid FM_Start(void)\r\n{\r\n    gDualWatchActive = false;\r\n    gFmRadioMode              = true;\r\n    gFM_ScanState             = FM_SCAN_OFF;\r\n    gFM_RestoreCountdown_10ms = 0;\r\n\r\n    BK1080_Init(gEeprom.FM_FrequencyPlaying, true);\r\n\r\n    AUDIO_AudioPathOn();\r\n\r\n    gEnableSpeaker       = true;\r\n    gUpdateStatus        = true;\r\n}\r\n\r\n#endif"
  },
  {
    "path": "app/fm.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef APP_FM_H\r\n#define APP_FM_H\r\n\r\n#ifdef ENABLE_FMRADIO\r\n\r\n#include \"driver/keyboard.h\"\r\n\r\n#define FM_CHANNEL_UP\t0x01\r\n#define FM_CHANNEL_DOWN\t0xFF\r\n\r\nenum {\r\n    FM_SCAN_OFF = 0U,\r\n};\r\nextern bool              FM_EXIT_FLAG;\r\n\r\nextern uint16_t          gFM_Channels[20];\r\nextern bool              gFmRadioMode;\r\nextern uint8_t           gFmRadioCountdown_500ms;\r\nextern volatile uint16_t gFmPlayCountdown_10ms;\r\nextern volatile int8_t   gFM_ScanState;\r\nextern uint8_t           gFM_ChannelPosition;\r\n// Doubts about          whether this should be signed or not\r\nextern uint16_t          gFM_FrequencyDeviation;\r\nextern bool              gFM_FoundFrequency;\r\nextern bool              gFM_AutoScan;\r\nextern uint16_t          gFM_RestoreCountdown_10ms;\r\n\r\nbool    FM_CheckValidChannel(uint8_t Channel);\r\nuint8_t FM_FindNextChannel(uint8_t Channel, uint8_t Direction);\r\nint     FM_ConfigureChannelState(void);\r\nvoid    FM_TurnOff(void);\r\nvoid    FM_EraseChannels(void);\r\n\r\nvoid    FM_Tune(uint16_t Frequency, int8_t Step, bool bFlag);\r\nvoid    FM_PlayAndUpdate(void);\r\nint     FM_CheckFrequencyLock(uint16_t Frequency, uint16_t LowerLimit);\r\n\r\nvoid    FM_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld);\r\n\r\nvoid    FM_Play(void);\r\nvoid    FM_Start(void);\r\n\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "app/generic.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <string.h>\r\n\r\n#include \"app/app.h\"\r\n#include \"app/chFrScanner.h\"\r\n#include \"app/common.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"app/generic.h\"\r\n#include \"app/menu.h\"\r\n#include \"app/scanner.h\"\r\n#include \"audio.h\"\r\n#include \"driver/keyboard.h\"\r\n#include \"dtmf.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"functions.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/ui.h\"\r\n#ifdef ENABLE_TURN\r\n\r\nbool turn_flag = 0;\r\n#endif\r\nvoid GENERIC_Key_F(bool bKeyPressed, bool bKeyHeld) {\r\n    if (gInputBoxIndex > 0) {\r\n        if (!bKeyHeld && bKeyPressed) // short pressed\r\n            gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n        return;\r\n    }\r\n\r\n    if (bKeyHeld || !bKeyPressed) // held or released\r\n    {\r\n        if (bKeyHeld ||\r\n            bKeyPressed) // held or pressed (cannot be held and not pressed I guess, so it checks only if HELD?)\r\n        {\r\n            if (!bKeyHeld) // won't ever pass\r\n                return;\r\n\r\n            if (!bKeyPressed) // won't ever pass\r\n                return;\r\n\r\n            COMMON_KeypadLockToggle();\r\n        } else // released\r\n        {\r\n#ifdef ENABLE_FMRADIO\r\n            if ((gFmRadioMode || gScreenToDisplay != DISPLAY_MAIN) && gScreenToDisplay != DISPLAY_FM)\r\n                    return;\r\n#else\r\n            if (gScreenToDisplay != DISPLAY_MAIN)\r\n                return;\r\n#endif\r\n\r\n            gWasFKeyPressed = !gWasFKeyPressed; // toggle F function\r\n#ifdef ENABLE_TURN\r\n\r\n            turn_flag = gWasFKeyPressed;\r\n#endif\r\n            if (gWasFKeyPressed)\r\n                gKeyInputCountdown = key_input_timeout_500ms;\r\n\r\n#ifdef ENABLE_VOICE\r\n            if (!gWasFKeyPressed)\r\n                    gAnotherVoiceID = VOICE_ID_CANCEL;\r\n#endif\r\n\r\n            gUpdateStatus = true;\r\n        }\r\n    } else // short pressed\r\n    {\r\n\r\n#ifdef ENABLE_FMRADIO\r\n        if (gScreenToDisplay != DISPLAY_FM)\r\n#endif\r\n        {\r\n            gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n            return;\r\n        }\r\n\r\n#ifdef ENABLE_FMRADIO\r\n        if (gFM_ScanState == FM_SCAN_OFF) // not scanning\r\n            {\r\n                gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n                return;\r\n            }\r\n#endif\r\n\r\n        gBeepToPlay = BEEP_440HZ_500MS;\r\n\r\n        gPttWasReleased = true;\r\n    }\r\n}\r\n\r\nvoid GENERIC_Key_PTT(bool bKeyPressed) {\r\n    gInputBoxIndex = 0;\r\n    if (!bKeyPressed || SerialConfigInProgress()) {    // PTT released\r\n        if (gCurrentFunction == FUNCTION_TRANSMIT) {    // we are transmitting .. stop\r\n\r\n\r\n            APP_EndTransmission(SerialConfigInProgress());\r\n\r\n\r\n#ifdef ENABLE_VOX\r\n            gVOX_NoiseDetected = false;\r\n#endif\r\n\r\n            RADIO_SetVfoState(VFO_STATE_NORMAL);\r\n\r\n            if (gScreenToDisplay != DISPLAY_MENU)     // 1of11 .. don't close the menu\r\n                gRequestDisplayScreen = DISPLAY_MAIN;\r\n        }\r\n\r\n        return;\r\n    }\r\n\r\n    // PTT pressed\r\n\r\n\r\n    if (SCANNER_IsScanning()) {    // CTCSS/CDCSS scanning .. stop\r\n        SCANNER_Stop();\r\n        goto cancel_tx;\r\n    }\r\n\r\n    if (gScanStateDir != SCAN_OFF) {    // frequency/channel scanning . .stop\r\n        CHFRSCANNER_Stop();\r\n        goto cancel_tx;\r\n    }\r\n\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFM_ScanState != FM_SCAN_OFF)\r\n    {\t// FM radio is scanning .. stop\r\n        FM_PlayAndUpdate();\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID = VOICE_ID_SCANNING_STOP;\r\n#endif\r\n        gRequestDisplayScreen = DISPLAY_FM;\r\n        goto cancel_tx;\r\n    }\r\n#endif\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gScreenToDisplay == DISPLAY_FM)\r\n        goto start_tx;\t// listening to the FM radio .. start TX'ing\r\n#endif\r\n\r\n    if (gCurrentFunction == FUNCTION_TRANSMIT && gRTTECountdown_10ms == 0) {    // already transmitting\r\n        gInputBoxIndex = 0;\r\n        return;\r\n    }\r\n\r\n    if (gScreenToDisplay != DISPLAY_MENU)     // 1of11 .. don't close the menu\r\n        gRequestDisplayScreen = DISPLAY_MAIN;\r\n\r\n\r\n    if (!gDTMF_InputMode && gDTMF_InputBox_Index == 0)\r\n        goto start_tx;    // wasn't entering a DTMF code .. start TX'ing (maybe)\r\n\r\n    // was entering a DTMF string\r\n\r\n    if (gDTMF_InputBox_Index > 0 || gDTMF_PreviousIndex > 0) {    // going to transmit a DTMF string\r\n\r\n        if (gDTMF_InputBox_Index == 0 && gDTMF_PreviousIndex > 0)\r\n            gDTMF_InputBox_Index = gDTMF_PreviousIndex;           // use the previous DTMF string\r\n\r\n        if (gDTMF_InputBox_Index < sizeof(gDTMF_InputBox))\r\n            gDTMF_InputBox[gDTMF_InputBox_Index] = 0;             // NULL term the string\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n        // append our DTMF ID to the inputted DTMF code -\r\n        //  IF the user inputted code is exactly 3 digits long and D-DCD is enabled\r\n        if (gDTMF_InputBox_Index == 3 && gTxVfo->DTMF_DECODING_ENABLE > 0)\r\n            gDTMF_CallMode = DTMF_CheckGroupCall(gDTMF_InputBox, 3);\r\n        else\r\n            gDTMF_CallMode = DTMF_CALL_MODE_DTMF;\r\n\r\n        gDTMF_State      = DTMF_STATE_0;\r\n#endif\r\n        // remember the DTMF string\r\n        gDTMF_PreviousIndex = gDTMF_InputBox_Index;\r\n        strcpy(gDTMF_String, gDTMF_InputBox);\r\n        gDTMF_ReplyState = DTMF_REPLY_ANI;\r\n    }\r\n\r\n    DTMF_clear_input_box();\r\n\r\n    start_tx:\r\n    // request start TX\r\n    gFlagPrepareTX = true;\r\n    goto done;\r\n\r\n    cancel_tx:\r\n    if (gPttIsPressed) {\r\n        gPttWasPressed = true;\r\n    }\r\n\r\n    done:\r\n    gPttDebounceCounter = 0;\r\n    if (gScreenToDisplay != DISPLAY_MENU\r\n#ifdef ENABLE_FMRADIO\r\n        && gRequestDisplayScreen != DISPLAY_FM\r\n#endif\r\n            ) {\r\n        // 1of11 .. don't close the menu\r\n        gRequestDisplayScreen = DISPLAY_MAIN;\r\n    }\r\n    gUpdateStatus = true;\r\n    gUpdateDisplay = true;\r\n}"
  },
  {
    "path": "app/generic.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef APP_GENERIC_H\r\n#define APP_GENERIC_H\r\n\r\n#include <stdbool.h>\r\n\r\nvoid GENERIC_Key_F(bool bKeyPressed, bool bKeyHeld);\r\n\r\nvoid GENERIC_Key_PTT(bool bKeyPressed);\r\n\r\nextern bool turn_flag;\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "app/main.c",
    "content": "/* Copyright 2023 Dual Tachyon\n * https://github.com/DualTachyon\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http://www.apache.org/licenses/LICENSE-2.0\n *\n *     Unless required by applicable law or agreed to in writing, software\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n *     See the License for the specific language governing permissions and\n *     limitations under the License.\n */\n\n#include <string.h>\n\n#include \"app/action.h\"\n#include \"app/app.h\"\n#include \"app/chFrScanner.h\"\n#include \"app/common.h\"\n#include \"chinese.h\"\n#ifdef ENABLE_4732\n#include \"app/si.h\"\n#endif\n#ifdef ENABLE_FMRADIO\n#include \"app/fm.h\"\n#endif\n\n#include \"app/generic.h\"\n#include \"app/main.h\"\n#include \"app/scanner.h\"\n\n#ifdef ENABLE_SPECTRUM\n#include \"app/spectrum.h\"\n#endif\n\n#include \"audio.h\"\n#include \"board.h\"\n#include \"driver/bk4819.h\"\n#include \"dtmf.h\"\n#include \"frequencies.h\"\n#include \"misc.h\"\n#include \"radio.h\"\n#include \"settings.h\"\n#include \"ui/inputbox.h\"\n#include \"ui/ui.h\"\n#include <stdlib.h>\n\n#ifdef ENABLE_MESSENGER\n#include \"app/messenger.h\"\n#endif\n#ifdef ENABLE_DOPPLER\n#include \"app/doppler.h\"\n#endif\n\nvoid toggle_chan_scanlist(void) {    // toggle the selected channels scanlist setting\n    if (SCANNER_IsScanning())\n        return;\n    if (!IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) {\n#ifdef ENABLE_SCAN_RANGES\n        gScanRangeStart = gScanRangeStart ? 0 : gTxVfo->pRX->Frequency;\n        gScanRangeStop = gEeprom.VfoInfo[!gEeprom.TX_VFO].freq_config_RX.Frequency;\n        if(gScanRangeStart > gScanRangeStop)\n            SWAP(gScanRangeStart, gScanRangeStop);\n#endif\n        return;\n    }\n\n    if (gTxVfo->SCANLIST1_PARTICIPATION ^ gTxVfo->SCANLIST2_PARTICIPATION) {\n        gTxVfo->SCANLIST2_PARTICIPATION = gTxVfo->SCANLIST1_PARTICIPATION;\n    } else {\n        gTxVfo->SCANLIST1_PARTICIPATION = !gTxVfo->SCANLIST1_PARTICIPATION;\n    }\n\n    SETTINGS_UpdateChannel(gTxVfo->CHANNEL_SAVE, gTxVfo, true);\n\n    gVfoConfigureMode = VFO_CONFIGURE;\n    gFlagResetVfos = true;\n}\n\nstatic void processFKeyFunction(const KEY_Code_t Key, const bool beep) {\n    uint8_t Vfo = gEeprom.TX_VFO;\n\n    if (gScreenToDisplay == DISPLAY_MENU) {\n//\t\tif (beep)\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n        return;\n    }\n    gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n\n    switch (Key) {\n\n        case KEY_0:\n#ifdef ENABLE_FMRADIO\n            ACTION_FM();\n#endif\n#ifdef ENABLE_4732\n            SI4732_Main();\n#endif\n            break;\n\n        case KEY_1:\n            if (!IS_FREQ_CHANNEL(gTxVfo->CHANNEL_SAVE)) {\n                gWasFKeyPressed = false;\n                gUpdateStatus = true;\n                gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n\n#ifdef ENABLE_COPY_CHAN_TO_VFO\n                if (!gEeprom.VFO_OPEN || gCssBackgroundScan)\n                {\ngBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n                    return;\n                }\n                   if (gScanStateDir != SCAN_OFF)\n                {\n                    if (gCurrentFunction != FUNCTION_INCOMING ||\n                        gRxReceptionMode == RX_MODE_NONE      ||\n                        gScanPauseDelayIn_10ms == 0)\n                    {\t// scan is running (not paused)\n                        return;\n                    }\n}\n                const uint8_t vfo = gEeprom.TX_VFO;\n                   if (IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo]))\n                {\t// copy channel to VFO, then swap to the VFO\n\n                       gEeprom.ScreenChannel[vfo] = FREQ_CHANNEL_FIRST + gEeprom.VfoInfo[vfo].Band;\n                    gEeprom.VfoInfo[vfo].CHANNEL_SAVE = gEeprom.ScreenChannel[vfo];\n\n                    RADIO_SelectVfos();\n                    RADIO_ApplyOffset(gRxVfo);\n                    RADIO_ConfigureSquelchAndOutputPower(gRxVfo);\n                    RADIO_SetupRegisters(true);\n                                    //SETTINGS_SaveChannel(channel, gEeprom.RX_VFO, gRxVfo, 1);\n\n                    gUpdateDisplay = true;\n\n                }\n#endif\n                return;\n            }\n\n#ifdef ENABLE_WIDE_RX\n            if(gTxVfo->Band == BAND7_470MHz && gTxVfo->pRX->Frequency < _1GHz_in_KHz) {\n                    gTxVfo->pRX->Frequency = _1GHz_in_KHz;\n                    return;\n            }\n#endif\n\n            gTxVfo->Band += 1;\n\n            if (gTxVfo->Band == BAND5_350MHz && gSetting_F_LOCK != F_LOCK_NONE) {\n                // skip if not enabled\n                gTxVfo->Band += 1;\n            } else if (gTxVfo->Band >= BAND_N_ELEM) {\n                // go arround if overflowed\n                gTxVfo->Band = BAND1_50MHz;\n            }\n\n            gEeprom.ScreenChannel[Vfo] = FREQ_CHANNEL_FIRST + gTxVfo->Band;\n            gEeprom.FreqChannel[Vfo] = FREQ_CHANNEL_FIRST + gTxVfo->Band;\n\n            gRequestSaveVFO = true;\n            gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\n\n            gRequestDisplayScreen = DISPLAY_MAIN;\n\n            if (beep)\n                gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n\n            break;\n\n        case KEY_2:\n            COMMON_SwitchVFOs();\n\n            if (beep)\n                gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n            break;\n\n        case KEY_3:\n            COMMON_SwitchVFOMode();\n\n            if (beep)\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n\n            break;\n\n        case KEY_4:\n            gWasFKeyPressed = false;\n\n            gBackup_CROSS_BAND_RX_TX = gEeprom.CROSS_BAND_RX_TX;\n            gEeprom.CROSS_BAND_RX_TX = CROSS_BAND_OFF;\n            gUpdateStatus = true;\n            if (beep)\n                gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n\n            SCANNER_Start(false);\n            gRequestDisplayScreen = DISPLAY_SCANNER;\n            break;\n\n        case KEY_5:\n\n            if (beep) {\n#ifdef ENABLE_NOAA\n\n                if (!IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE))\n                {\n                    gEeprom.ScreenChannel[Vfo] = gEeprom.NoaaChannel[gEeprom.TX_VFO];\n                }\n                else\n                {\n                    gEeprom.ScreenChannel[Vfo] = gEeprom.FreqChannel[gEeprom.TX_VFO];\n#ifdef ENABLE_VOICE\n                        gAnotherVoiceID = VOICE_ID_FREQUENCY_MODE;\n#endif\n                }\n                gRequestSaveVFO   = true;\n                gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\n#elif defined(ENABLE_SPECTRUM)\n#ifdef ENABLE_DOPPLER\n                DOPPLER_MODE=0;\n#endif\n                APP_RunSpectrum();\n                gRequestDisplayScreen = DISPLAY_MAIN;\n#endif\n            } else {\n#ifdef ENABLE_VOX\n                toggle_chan_scanlist();\n#endif\n            }\n\n            break;\n\n\n        case KEY_6:\n            ACTION_Power();\n            break;\n\n        case KEY_7:\n#ifdef ENABLE_VOX\n            ACTION_Vox();\n#else\n            toggle_chan_scanlist();\n#endif\n            break;\n\n        case KEY_8:\n            gTxVfo->FrequencyReverse = ++gTxVfo->FrequencyReverse % 3;\n            gRequestSaveChannel = 1;\n            break;\n\n        case KEY_9:\n            if (RADIO_CheckValidChannel(gEeprom.CHAN_1_CALL, false, 0)) {\n                gEeprom.MrChannel[Vfo] = gEeprom.CHAN_1_CALL;\n                gEeprom.ScreenChannel[Vfo] = gEeprom.CHAN_1_CALL;\n#ifdef ENABLE_VOICE\n                AUDIO_SetVoiceID(0, VOICE_ID_CHANNEL_MODE);\n                AUDIO_SetDigitVoice(1, gEeprom.CHAN_1_CALL + 1);\n                gAnotherVoiceID        = (VOICE_ID_t)0xFE;\n#endif\n                gRequestSaveVFO = true;\n                gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\n                break;\n            }\n\n            if (beep)\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n            break;\n\n        default:\n            gUpdateStatus = true;\n            gWasFKeyPressed = false;\n\n            if (beep)\n                gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n            break;\n    }\n}\n\nstatic void MAIN_Key_DIGITS(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) {\n    if (bKeyHeld) {    // key held down\n\n        if (bKeyPressed) {\n            if (gScreenToDisplay == DISPLAY_MAIN) {\n                if (gInputBoxIndex > 0) {    // delete any inputted chars\n                    gInputBoxIndex = 0;\n                    gRequestDisplayScreen = DISPLAY_MAIN;\n                }\n\n                gWasFKeyPressed = false;\n                gUpdateStatus = true;\n\n                processFKeyFunction(Key, false);\n            }\n        }\n\n        return;\n    }\n\n    if (bKeyPressed) {    // key is pressed\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;  // beep when key is pressed\n        return;                                 // don't use the key till it's released\n    }\n\n    if (!gWasFKeyPressed) {    // F-key wasn't pressed\n\n        const uint8_t Vfo = gEeprom.TX_VFO;\n\n        gKeyInputCountdown = key_input_timeout_500ms;\n\n        INPUTBOX_Append(Key);\n\n        gRequestDisplayScreen = DISPLAY_MAIN;\n\n        if (IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) {    // user is entering channel number\n\n            if (gInputBoxIndex != 3) {\n#ifdef ENABLE_VOICE\n                gAnotherVoiceID   = (VOICE_ID_t)Key;\n#endif\n                gRequestDisplayScreen = DISPLAY_MAIN;\n                return;\n            }\n\n            gInputBoxIndex = 0;\n\n            const uint16_t Channel = ((gInputBox[0] * 100) + (gInputBox[1] * 10) + gInputBox[2]) - 1;\n\n            if (!RADIO_CheckValidChannel(Channel, false, 0)) {\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n                return;\n            }\n\n#ifdef ENABLE_VOICE\n            gAnotherVoiceID        = (VOICE_ID_t)Key;\n#endif\n\n            gEeprom.MrChannel[Vfo] = (uint8_t) Channel;\n            gEeprom.ScreenChannel[Vfo] = (uint8_t) Channel;\n            gRequestSaveVFO = true;\n            gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\n\n            return;\n        }\n\n//\t\t#ifdef ENABLE_NOAA\n//\t\t\tif (!IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE))\n//\t\t#endif\n        if (IS_FREQ_CHANNEL(gTxVfo->CHANNEL_SAVE)) {    // user is entering a frequency\n\n#ifdef ENABLE_VOICE\n            gAnotherVoiceID = (VOICE_ID_t)Key;\n#endif\n            bool isGigaF = gTxVfo->pRX->Frequency >= _1GHz_in_KHz;\n            if (gInputBoxIndex < 6 + isGigaF) {\n                return;\n            }\n\n            gInputBoxIndex = 0;\n            uint32_t Frequency = StrToUL(INPUTBOX_GetAscii()) * 100;\n\n            // clamp the frequency entered to some valid value\n            if (Frequency < frequencyBandTable[0].lower) {\n                Frequency = frequencyBandTable[0].lower;\n            } else if (Frequency >= BX4819_band1.upper && Frequency < BX4819_band2.lower) {\n                const uint32_t center = (BX4819_band1.upper + BX4819_band2.lower) / 2;\n                Frequency = (Frequency < center) ? BX4819_band1.upper : BX4819_band2.lower;\n            } else if (Frequency > frequencyBandTable[BAND_N_ELEM - 1].upper) {\n                Frequency = frequencyBandTable[BAND_N_ELEM - 1].upper;\n            }\n\n            const FREQUENCY_Band_t band = FREQUENCY_GetBand(Frequency);\n\n            if (gTxVfo->Band != band) {\n                gTxVfo->Band = band;\n                gEeprom.ScreenChannel[Vfo] = band + FREQ_CHANNEL_FIRST;\n                gEeprom.FreqChannel[Vfo] = band + FREQ_CHANNEL_FIRST;\n\n                SETTINGS_SaveVfoIndices();\n\n                RADIO_ConfigureChannel(Vfo, VFO_CONFIGURE_RELOAD);\n            }\n\n            Frequency = FREQUENCY_RoundToStep(Frequency, gTxVfo->StepFrequency);\n\n            if (Frequency >= BX4819_band1.upper &&\n                Frequency < BX4819_band2.lower) {    // clamp the frequency to the limit\n                const uint32_t center = (BX4819_band1.upper + BX4819_band2.lower) / 2;\n                Frequency = (Frequency < center) ? BX4819_band1.upper - gTxVfo->StepFrequency : BX4819_band2.lower;\n            }\n\n            gTxVfo->freq_config_RX.Frequency = Frequency;\n\n            gRequestSaveChannel = 1;\n            return;\n\n        }\n#ifdef ENABLE_NOAA\n        else\n            if (IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE))\n            {\t// user is entering NOAA channel\n                if (gInputBoxIndex != 2)\n                {\n#ifdef ENABLE_VOICE\n                        gAnotherVoiceID   = (VOICE_ID_t)Key;\n#endif\n                    gRequestDisplayScreen = DISPLAY_MAIN;\n                    return;\n                }\n\n                gInputBoxIndex = 0;\n\n                uint8_t Channel = (gInputBox[0] * 10) + gInputBox[1];\n                if (Channel >= 1 && Channel <= ARRAY_SIZE(NoaaFrequencyTable))\n                {\n                    Channel                   += NOAA_CHANNEL_FIRST;\n#ifdef ENABLE_VOICE\n                        gAnotherVoiceID        = (VOICE_ID_t)Key;\n#endif\n                    gEeprom.NoaaChannel[Vfo]   = Channel;\n                    gEeprom.ScreenChannel[Vfo] = Channel;\n                    gRequestSaveVFO            = true;\n                    gVfoConfigureMode          = VFO_CONFIGURE_RELOAD;\n                    return;\n                }\n            }\n#endif\n\n        gRequestDisplayScreen = DISPLAY_MAIN;\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n        return;\n    }\n\n    gWasFKeyPressed = false;\n    gUpdateStatus = true;\n\n    processFKeyFunction(Key, true);\n}\n\nstatic void MAIN_Key_EXIT(bool bKeyPressed, bool bKeyHeld) {\n\n#include \"app/menu.h\"\n#ifdef ENABLE_TURN\n    if (turn_flag) {\n        turn_flag = false;\n        key_dir *= -1;\n        gRequestSaveSettings = true;\n        return;\n    }\n#endif\n    if (!bKeyHeld && bKeyPressed) {    // exit key pressed\n\n\n\n\n\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n#ifdef ENABLE_DTMF_CALLING\n        if (gDTMF_CallState != DTMF_CALL_STATE_NONE &&\n            gCurrentFunction != FUNCTION_TRANSMIT) {    // clear CALL mode being displayed\n            gDTMF_CallState = DTMF_CALL_STATE_NONE;\n            gUpdateDisplay = true;\n            return;\n        }\n#endif\n\n\n#ifdef ENABLE_FMRADIO\n        if (!gFmRadioMode)\n#endif\n        {\n            if (gScanStateDir == SCAN_OFF) {\n                if (gInputBoxIndex == 0)\n                    return;\n                gInputBox[--gInputBoxIndex] = 10;\n\n                gKeyInputCountdown = key_input_timeout_500ms;\n\n#ifdef ENABLE_VOICE\n                if (gInputBoxIndex == 0)\n                    gAnotherVoiceID = VOICE_ID_CANCEL;\n#endif\n            } else {\n                gScanKeepResult = false;\n                CHFRSCANNER_Stop();\n\n#ifdef ENABLE_VOICE\n                gAnotherVoiceID = VOICE_ID_SCANNING_STOP;\n#endif\n            }\n\n            gRequestDisplayScreen = DISPLAY_MAIN;\n            return;\n        }\n\n#ifdef ENABLE_FMRADIO\n        ACTION_FM();\n#endif\n\n        return;\n    }\n\n    if (bKeyHeld && bKeyPressed) {    // exit key held down\n\n        if (gInputBoxIndex > 0 || gDTMF_InputBox_Index > 0 ||\n            gDTMF_InputMode) {    // cancel key input mode (channel/frequency entry)\n            DTMF_clear_input_box();\n            memset(gDTMF_String, 0, sizeof(gDTMF_String));\n            gInputBoxIndex = 0;\n            gRequestDisplayScreen = DISPLAY_MAIN;\n            gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n        }\n    }\n\n}\n\nstatic void MAIN_Key_MENU(const bool bKeyPressed, const bool bKeyHeld) {\n\n    if (bKeyPressed && !bKeyHeld)\n        // menu key pressed\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n\n    if (bKeyHeld) {    // menu key held down (long press)\n\n        if (bKeyPressed) {    // long press MENU key\n\n            gWasFKeyPressed = false;\n\n            if (gScreenToDisplay == DISPLAY_MAIN) {\n                if (gInputBoxIndex > 0) {    // delete any inputted chars\n                    gInputBoxIndex = 0;\n                    gRequestDisplayScreen = DISPLAY_MAIN;\n                }\n\n                gWasFKeyPressed = false;\n                gUpdateStatus = true;\n\n                ACTION_Handle(KEY_MENU, bKeyPressed, bKeyHeld);\n            }\n        }\n\n        return;\n    }\n\n    if (!bKeyPressed && !gDTMF_InputMode) {    // menu key released\n\n#ifdef ENABLE_MESSENGER\n        if (gWasFKeyPressed) {\n            hasNewMessage = 0;\n            gRequestDisplayScreen = DISPLAY_MSG;\n            return;\n        }\n#endif\n\n\n        const bool bFlag = !gInputBoxIndex;\n        gInputBoxIndex = 0;\n\n        if (bFlag) {\n            if (gScanStateDir != SCAN_OFF) {\n                CHFRSCANNER_Stop();\n                return;\n            }\n\n            gFlagRefreshSetting = true;\n            gRequestDisplayScreen = DISPLAY_MENU;\n#ifdef ENABLE_VOICE\n            gAnotherVoiceID   = VOICE_ID_MENU;\n#endif\n        } else {\n            gRequestDisplayScreen = DISPLAY_MAIN;\n        }\n    }\n}\n\nstatic void MAIN_Key_STAR(bool bKeyPressed, bool bKeyHeld) {\n    if (gCurrentFunction == FUNCTION_TRANSMIT)\n        return;\n\n    if (gInputBoxIndex) {\n        if (!bKeyHeld && bKeyPressed)\n            gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n        return;\n    }\n\n    if (bKeyHeld && !gWasFKeyPressed) // long press\n    {\n        if (!bKeyPressed) // released\n            return;\n\n        ACTION_Scan(false);// toggle scanning\n\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n        return;\n    }\n\n    if (bKeyPressed) // just pressed\n    {\n\n        return;\n    }\n\n    // just released\n\n    if (!gWasFKeyPressed) // pressed without the F-key\n    {\n\n        if (gScanStateDir == SCAN_OFF\n#ifdef ENABLE_NOAA\n            && !IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE)\n#endif\n#ifdef ENABLE_SCAN_RANGES\n            && gScanRangeStart == 0\n#endif\n                ) {    // start entering a DTMF string\n            gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n            memcpy(gDTMF_InputBox, gDTMF_String, MIN(sizeof(gDTMF_InputBox), sizeof(gDTMF_String) - 1));\n            gDTMF_InputBox_Index = 0;\n            gDTMF_InputMode = true;\n\n            gKeyInputCountdown = key_input_timeout_500ms;\n\n            gRequestDisplayScreen = DISPLAY_MAIN;\n        } else\n            gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n    } else {    // with the F-key\n        gWasFKeyPressed = false;\n\n#ifdef ENABLE_NOAA\n        if (IS_NOAA_CHANNEL(gTxVfo->CHANNEL_SAVE)) {\n            gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n            return;\n        }\n#endif\n\n        // scan the CTCSS/DCS code\n        gBackup_CROSS_BAND_RX_TX = gEeprom.CROSS_BAND_RX_TX;\n        gEeprom.CROSS_BAND_RX_TX = CROSS_BAND_OFF;\n        SCANNER_Start(true);\n        gRequestDisplayScreen = DISPLAY_SCANNER;\n    }\n\n    gPttWasReleased = true;\n\n    gUpdateStatus = true;\n}\n\nstatic void MAIN_Key_UP_DOWN(bool bKeyPressed, bool bKeyHeld, int8_t Direction) {\n    uint8_t Channel = gEeprom.ScreenChannel[gEeprom.TX_VFO];\n    if (gWasFKeyPressed) {\n        gWasFKeyPressed = false;\n\n        if (Direction == 1) {\n            gEeprom.BEEP_CONTROL = !gEeprom.BEEP_CONTROL;\n            gRequestSaveSettings = 1;\n        }\n#ifdef ENABLE_DOPPLER\n        if (Direction==-1) {\n\n        if (!DOPPLER_FLAG) {\n            BACKLIGHT_TurnOn();\n            UI_DisplayClear();\n#ifndef ENABLE_ENGLISH\n//ȡ\n            UI_PrintStringSmall(\"\\xD0\\xB4\\xC8\\xEB\\xCA\\xFD\\xBE\\xDD:\", 0, 127, 2);\n#else\n            UI_PrintStringSmall(\"GET DATA:\", 0, 127, 2);\n#endif\n            UI_PrintStringSmall(\"k5.vicicode.com\", 0, 127, 4);\n\n            ST7565_BlitFullScreen();\n            uint8_t cnt_i = 200;\n            while (cnt_i) {\n\n                SYSTEM_DelayMs(10);\ncnt_i--;\n            }\n\n        }else{\n#ifdef ENABLE_DOPPLER\n            DOPPLER_MODE=1;\n#endif\n            APP_RunSpectrum();\n            gRequestDisplayScreen = DISPLAY_MAIN;\n            }\n        }\n#endif\n        return;\n    }\n\n    if (bKeyHeld || !bKeyPressed) { // key held or released\n\n        if (gInputBoxIndex > 0)\n            return; // leave if input box active\n\n        if (!bKeyPressed) {\n\n\n            if (!bKeyHeld || IS_FREQ_CHANNEL(Channel))\n                return;\n            // if released long button press and not in freq mode\n#ifdef ENABLE_VOICE\n            AUDIO_SetDigitVoice(0, gTxVfo->CHANNEL_SAVE + 1); // say channel number\n            gAnotherVoiceID = (VOICE_ID_t)0xFE;\n#endif\n            return;\n        }\n\n    } else {\n        if (gInputBoxIndex > 0) {\n            gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n            return;\n        }\n\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n    }\n\n    if (gScanStateDir == SCAN_OFF) {\n#ifdef ENABLE_NOAA\n        if (!IS_NOAA_CHANNEL(Channel))\n#endif\n        {\n            uint8_t Next;\n\n            if (IS_FREQ_CHANNEL(Channel)) {    // step/down in frequency\n                const uint32_t frequency = APP_SetFrequencyByStep(gTxVfo, Direction);\n\n                if (RX_freq_check(frequency) < 0) {    // frequency not allowed\n                    gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n                    return;\n                }\n\n                gTxVfo->freq_config_RX.Frequency = frequency;\n                BK4819_SetFrequency(frequency);\n                BK4819_RX_TurnOn();\n                gRequestSaveChannel = 1;\n                return;\n            }\n\n            Next = RADIO_FindNextChannel(Channel + Direction, Direction, false, 0);\n            if (Next == 0xFF)\n                return;\n\n            if (Channel == Next)\n                return;\n\n            gEeprom.MrChannel[gEeprom.TX_VFO] = Next;\n            gEeprom.ScreenChannel[gEeprom.TX_VFO] = Next;\n\n            if (!bKeyHeld) {\n#ifdef ENABLE_VOICE\n                AUDIO_SetDigitVoice(0, Next + 1);\n                gAnotherVoiceID = (VOICE_ID_t)0xFE;\n#endif\n            }\n        }\n#ifdef ENABLE_NOAA\n        else\n        {\n            Channel = NOAA_CHANNEL_FIRST + NUMBER_AddWithWraparound(gEeprom.ScreenChannel[gEeprom.TX_VFO] - NOAA_CHANNEL_FIRST, Direction, 0, 9);\n            gEeprom.NoaaChannel[gEeprom.TX_VFO]   = Channel;\n            gEeprom.ScreenChannel[gEeprom.TX_VFO] = Channel;\n        }\n#endif\n\n        gRequestSaveVFO = true;\n        gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\n        return;\n    }\n\n    // jump to the next channel\n    CHFRSCANNER_Start(false, Direction);\n    gScanPauseDelayIn_10ms = 1;\n    gScheduleScanListen = false;\n\n    gPttWasReleased = true;\n}\n\nvoid MAIN_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) {\n    if (bKeyPressed)\n        last_rx_vfo = -1;\n#ifdef ENABLE_FMRADIO\n    if (gFmRadioMode && Key != KEY_PTT && Key != KEY_EXIT)\n    {\n        if (!bKeyHeld && bKeyPressed)\n            gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n        return;\n    }\n#endif\n\n    if (gDTMF_InputMode && bKeyPressed && !bKeyHeld) {\n        const char Character = DTMF_GetCharacter(Key);\n        if (Character != 0xFF) {    // add key to DTMF string\n            DTMF_Append(Character);\n            gKeyInputCountdown = key_input_timeout_500ms;\n            gRequestDisplayScreen = DISPLAY_MAIN;\n            gPttWasReleased = true;\n            gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\n            return;\n        }\n    }\n\n    // TODO: ???\n//\tif (Key > KEY_PTT)\n//\t{\n//\t\tKey = KEY_SIDE2;      // what's this doing ???\n//\t}\n\n    switch (Key) {\n        case KEY_0...KEY_9:\n            MAIN_Key_DIGITS(Key, bKeyPressed, bKeyHeld);\n            break;\n        case KEY_MENU:\n            MAIN_Key_MENU(bKeyPressed, bKeyHeld);\n            break;\n        case KEY_UP:\n            MAIN_Key_UP_DOWN(bKeyPressed, bKeyHeld, 1);\n            break;\n        case KEY_DOWN:\n            MAIN_Key_UP_DOWN(bKeyPressed, bKeyHeld, -1);\n            break;\n        case KEY_EXIT:\n            MAIN_Key_EXIT(bKeyPressed, bKeyHeld);\n            break;\n        case KEY_STAR:\n            MAIN_Key_STAR(bKeyPressed, bKeyHeld);\n            break;\n        case KEY_F:\n            GENERIC_Key_F(bKeyPressed, bKeyHeld);\n            break;\n        case KEY_PTT:\n            GENERIC_Key_PTT(bKeyPressed);\n            break;\n        default:\n            if (!bKeyHeld && bKeyPressed)\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\n            break;\n    }\n}\n"
  },
  {
    "path": "app/main.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef APP_MAIN_H\r\n#define APP_MAIN_H\r\n\r\n#include \"driver/keyboard.h\"\r\n\r\nvoid MAIN_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "app/mdc1200.c",
    "content": "\n#include \"driver/bk4819.h\"\n#include \"driver/crc.h\"\n#include \"driver/uart.h\"\n#include \"mdc1200.h\"\n#include \"misc.h\"\n#include <string.h>\n#include \"driver/eeprom.h\"\n\n\nconst uint8_t mdc1200_pre_amble[] = {0x00, 0x00, 0x00};\nconst uint8_t mdc1200_sync[5] = {0x07, 0x09, 0x2a, 0x44, 0x6f};\n\nconst uint8_t mdc1200_sync_suc_xor[5] = {0xfb, 0x72, 0x40, 0x99, 0xa7};\n\n\nvoid error_correction(void *data) {    // can correct up to 3 or 4 corrupted bits (I think)\n\n    int i;\n    uint8_t shift_reg;\n    uint8_t syn;\n    uint8_t *data8 = (uint8_t *) data;\n\n    for (i = 0, shift_reg = 0, syn = 0; i < MDC1200_FEC_K; i++) {\n        const uint8_t bi = data8[i];\n        int bit_num;\n        for (bit_num = 0; bit_num < 8; bit_num++) {\n            uint8_t b;\n            unsigned int k = 0;\n\n            shift_reg = (shift_reg << 1) | ((bi >> bit_num) & 1u);\n            b = ((shift_reg >> 6) ^ (shift_reg >> 5) ^ (shift_reg >> 2) ^ (shift_reg >> 0)) & 1u;\n            syn = (syn << 1) | (((b ^ (data8[i + MDC1200_FEC_K] >> bit_num)) & 1u) ? 1u : 0u);\n\n            if (syn & 0x80) k++;\n            if (syn & 0x20) k++;\n            if (syn & 0x04) k++;\n            if (syn & 0x02) k++;\n\n            if (k >= 3) {    // correct a bit error\n                int ii = i;\n                int bn = bit_num - 7;\n                if (bn < 0) {\n                    bn += 8;\n                    ii--;\n                }\n                if (ii >= 0)\n                    data8[ii] ^= 1u << bn;   // fix a bit\n                syn ^= 0xA6;   // 10100110\n            }\n        }\n    }\n}\n\nbool decode_data(void *data) {\n    uint16_t crc1;\n    uint16_t crc2;\n    uint8_t *data8 = (uint8_t *) data;\n\n    {    // de-interleave\n\n        unsigned int i;\n        unsigned int k;\n        unsigned int m;\n        uint8_t deinterleaved[(MDC1200_FEC_K * 2) * 8];  // temp individual bit storage\n\n        // interleave order\n        //  0, 16, 32, 48, 64, 80,  96,\n        //  1, 17, 33, 49, 65, 81,  97,\n        //  2, 18, 34, 50, 66, 82,  98,\n        //  3, 19, 35, 51, 67, 83,  99,\n        //  4, 20, 36, 52, 68, 84, 100,\n        //  5, 21, 37, 53, 69, 85, 101,\n        //  6, 22, 38, 54, 70, 86, 102,\n        //  7, 23, 39, 55, 71, 87, 103,\n        //  8, 24, 40, 56, 72, 88, 104,\n        //  9, 25, 41, 57, 73, 89, 105,\n        // 10, 26, 42, 58, 74, 90, 106,\n        // 11, 27, 43, 59, 75, 91, 107,\n        // 12, 28, 44, 60, 76, 92, 108,\n        // 13, 29, 45, 61, 77, 93, 109,\n        // 14, 30, 46, 62, 78, 94, 110,\n        // 15, 31, 47, 63, 79, 95, 111\n\n        // de-interleave the received bits\n        for (i = 0, k = 0; i < 16; i++) {\n            for (m = 0; m < MDC1200_FEC_K; m++) {\n                const unsigned int n = (m * 16) + i;\n                deinterleaved[k++] = (data8[n >> 3] >> ((7 - n) & 7u)) & 1u;\n            }\n        }\n\n        // copy the de-interleaved bits back into the data buffer\n        for (i = 0, m = 0; i < (MDC1200_FEC_K * 2); i++) {\n            unsigned int k;\n            uint8_t b = 0;\n            for (k = 0; k < 8; k++)\n                if (deinterleaved[m++])\n                    b |= 1u << k;\n            data8[i] = b;\n        }\n    }\n\n    // try to correct the odd corrupted bit\n    error_correction(data);\n\n    // rx'ed de-interleaved data (min 14 bytes) looks like this ..\n    //\n    // OP  ARG  ID    CRC   STATUS  FEC bits\n    // 01  80   1234  2E3E  00      6580A862DD8808\n\n    crc1 = compute_crc(data, 4);\n    crc2 = ((uint16_t) data8[5] << 8) | (data8[4] << 0);\n\n    return (crc1 == crc2) ? true : false;\n}\n\n// **********************************************************\n// TX\n\nvoid xor_modulation(void *data, const unsigned int size) {    // exclusive-or succesive bits - the entire packet\n    unsigned int i;\n    uint8_t *data8 = (uint8_t *) data;\n    uint8_t prev_bit = 0;\n    for (i = 0; i < size; i++) {\n        int bit_num;\n        uint8_t in = data8[i];\n        uint8_t out = 0;\n        for (bit_num = 7; bit_num >= 0; bit_num--) {\n            const uint8_t new_bit = (in >> bit_num) & 1u;\n            if (new_bit != prev_bit)\n                out |= 1u << bit_num;        // previous bit and new bit are different - send a '1'\n            prev_bit = new_bit;\n        }\n        data8[i] = out ^ 0xff;\n    }\n}\n\nuint8_t *encode_data(void *data) {\n    // R=1/2 K=7 convolutional coder\n    //\n    // OP  ARG  ID    CRC   STATUS  FEC bits\n    // 01  80   1234  2E3E  00      6580A862DD8808\n    //\n    // 1. reverse the bit order for each byte of the first 7 bytes (to undo the reversal performed for display, above)\n    // 2. feed those bits into a shift register which is preloaded with all zeros\n    // 3. for each bit, calculate the modulo-2 sum: bit(n-0) + bit(n-2) + bit(n-5) + bit(n-6)\n    // 4. then for each byte of resulting output, again reverse those bits to generate the values shown above\n\n    uint8_t *data8 = (uint8_t *) data;\n\n    {    // add the FEC bits to the end of the data\n        unsigned int i;\n        uint8_t shift_reg = 0;\n        for (i = 0; i < MDC1200_FEC_K; i++) {\n            unsigned int bit_num;\n            const uint8_t bi = data8[i];\n            uint8_t bo = 0;\n            for (bit_num = 0; bit_num < 8; bit_num++) {\n                shift_reg = (shift_reg << 1) | ((bi >> bit_num) & 1u);\n                bo |= (((shift_reg >> 6) ^ (shift_reg >> 5) ^ (shift_reg >> 2) ^ (shift_reg >> 0)) & 1u) << bit_num;\n            }\n            data8[MDC1200_FEC_K + i] = bo;\n        }\n    }\n\n\n    {    // interleave the bits\n\n        unsigned int i;\n        unsigned int k;\n        uint8_t interleaved[(MDC1200_FEC_K * 2) * 8];   // temp individual bit storage\n\n        // interleave order\n        //  0, 16, 32, 48, 64, 80,  96,\n        //  1, 17, 33, 49, 65, 81,  97,\n        //  2, 18, 34, 50, 66, 82,  98,\n        //  3, 19, 35, 51, 67, 83,  99,\n        //  4, 20, 36, 52, 68, 84, 100,\n        //  5, 21, 37, 53, 69, 85, 101,\n        //  6, 22, 38, 54, 70, 86, 102,\n        //  7, 23, 39, 55, 71, 87, 103,\n        //  8, 24, 40, 56, 72, 88, 104,\n        //  9, 25, 41, 57, 73, 89, 105,\n        // 10, 26, 42, 58, 74, 90, 106,\n        // 11, 27, 43, 59, 75, 91, 107,\n        // 12, 28, 44, 60, 76, 92, 108,\n        // 13, 29, 45, 61, 77, 93, 109,\n        // 14, 30, 46, 62, 78, 94, 110,\n        // 15, 31, 47, 63, 79, 95, 111\n\n        // bit interleaver\n        for (i = 0, k = 0; i < (MDC1200_FEC_K * 2); i++) {\n            unsigned int bit_num;\n            const uint8_t b = data8[i];\n            for (bit_num = 0; bit_num < 8; bit_num++) {\n                interleaved[k] = (b >> bit_num) & 1u;\n                k += 16;\n                if (k >= sizeof(interleaved))\n                    k -= sizeof(interleaved) - 1;\n            }\n        }\n\n        // copy the interleaved bits back to the data buffer\n        for (i = 0, k = 0; i < (MDC1200_FEC_K * 2); i++) {\n            int bit_num;\n            uint8_t b = 0;\n            for (bit_num = 7; bit_num >= 0; bit_num--)\n                if (interleaved[k++])\n                    b |= 1u << bit_num;\n            data8[i] = b;\n        }\n    }\n\n    return data8 + (MDC1200_FEC_K * 2);\n}\n\nunsigned int MDC1200_encode_single_packet(void *data, const uint8_t op, const uint8_t arg, const uint16_t unit_id) {\n    unsigned int size;\n    uint16_t crc;\n    uint8_t *p = (uint8_t *) data;\n\n    memcpy(p, mdc1200_pre_amble, sizeof(mdc1200_pre_amble));\n    p += sizeof(mdc1200_pre_amble);\n    memcpy(p, mdc1200_sync, sizeof(mdc1200_sync));\n    p += sizeof(mdc1200_sync);\n\n    p[0] = op;\n    p[1] = arg;\n    p[2] = (unit_id >> 8) & 0x00ff;\n    p[3] = (unit_id >> 0) & 0x00ff;\n    crc = compute_crc(p, 4);\n    p[4] = (crc >> 0) & 0x00ff;\n    p[5] = (crc >> 8) & 0x00ff;\n    p[6] = 0;      // unknown field (00 for PTTIDs, 76 for STS and MSG)\n\n    p = encode_data(p);\n\n    size = (unsigned int) (p - (uint8_t *) data);\n\n    xor_modulation(data, size);\n\n    return size;\n}\n\n\nstruct {\n    uint8_t bit;\n    uint8_t prev_bit;\n    uint8_t xor_bit;\n    uint64_t shift_reg;\n    unsigned int bit_count;\n    unsigned int stage;\n    bool inverted_sync;\n    unsigned int data_index;\n    uint8_t data[40];\n} rx;\n\nvoid MDC1200_reset_rx(void) {\n    memset(&rx, 0, sizeof(rx));\n}\n\nbool MDC1200_process_rx_data(\n        const void *buffer,\n        const unsigned int size,\n        //const bool inverted,\n        uint8_t *op,\n        uint8_t *arg,\n        uint16_t *unit_id) {\n    const uint8_t *buffer8 = (const uint8_t *) buffer;\n    unsigned int index;\n\n    // 04 8D BF 66 58   sync\n    // FB 72 40 99 A7   inverted sync\n    //\n    // 04 8D BF 66 58   40 C4 B0 32 BA F9 33 18 35 08 83 F6 0C 36 .. 80 87 20 23 2C AE 22 10 26 0F 02 A4 08 24\n    // 04 8D BF 66 58   45 DB 03 07 BC FA 35 2E 33 0E 83 0E 83 69 .. 86 92 02 05 28 AC 26 34 22 0B 02 0B 02 4E\n\n    memset(&rx, 0, sizeof(rx));\n\n    for (index = 0; index < size; index++) {\n        int bit;\n        const uint8_t rx_byte = buffer8[index];\n\n        for (bit = 7; bit >= 0; bit--) {\n            unsigned int i;\n\n            rx.prev_bit = rx.bit;\n\n            rx.bit = (rx_byte >> bit) & 1u;\n\n            rx.xor_bit = (rx.xor_bit ^ rx.bit) & 1u;  // toggle our bit if the rx bit is high\n\n            rx.shift_reg = (rx.shift_reg << 1) | rx.xor_bit;\n            rx.bit_count++;\n\n            // *********\n\n            if (rx.stage == 0) {    // looking for the 40-bit sync pattern\n\n                const unsigned int sync_bit_ok_threshold = 32;\n\n                if (rx.bit_count >= 40) {\n                    // 40-bit sync pattern\n                    uint64_t sync_nor = 0x07092a446fu;            // normal\n                    uint64_t sync_inv = 0xffffffffffu ^ sync_nor; // bit inverted\n\n                    sync_nor ^= rx.shift_reg;\n                    sync_inv ^= rx.shift_reg;\n\n                    unsigned int nor_count = 0;\n                    unsigned int inv_count = 0;\n                    for (i = 40; i > 0; i--, sync_nor >>= 1, sync_inv >>= 1) {\n                        nor_count += sync_nor & 1u;\n                        inv_count += sync_inv & 1u;\n                    }\n                    nor_count = 40 - nor_count;\n                    inv_count = 40 - inv_count;\n\n\n                    if (nor_count >= sync_bit_ok_threshold || inv_count >= sync_bit_ok_threshold) {    // good enough\n\n                        rx.inverted_sync = (inv_count > nor_count) ? true : false;\n                        rx.data_index = 0;\n                        rx.bit_count = 0;\n                        rx.stage = 1;\n\n\n                    }\n                }\n\n                continue;\n            }\n\n            if (rx.bit_count < 8)\n                continue;\n\n            rx.bit_count = 0;\n\n            rx.data[rx.data_index++] = rx.shift_reg & 0xff;  // save the last 8 bits\n\n            if (rx.data_index < (MDC1200_FEC_K * 2))\n                continue;\n\n\n            if (!decode_data(rx.data)) {\n                MDC1200_reset_rx();\n\n\n                continue;\n            }\n\n            // extract the info from the packet\n            *op = rx.data[0];\n            *arg = rx.data[1];\n            *unit_id = ((uint16_t) rx.data[2] << 8) | (rx.data[3] << 0);\n\n\n            // reset the detector\n            MDC1200_reset_rx();\n\n            return true;\n        }\n    }\n\n    MDC1200_reset_rx();\n\n    return false;\n}\n\nuint8_t mdc1200_rx_buffer[5 + (MDC1200_FEC_K * 2)];\nunsigned int mdc1200_rx_buffer_index = 0;\n\nuint8_t mdc1200_op;\nuint8_t mdc1200_arg;\nuint16_t mdc1200_unit_id;\nuint8_t mdc1200_rx_ready_tick_500ms;\n\n\nvoid MDC1200_init(void) {\n//    memcpy(mdc1200_sync_suc_xor, mdc1200_sync, sizeof(mdc1200_sync));\n//    xor_modulation(mdc1200_sync_suc_xor, sizeof(mdc1200_sync_suc_xor));\n\n    MDC1200_reset_rx();\n}\n\nuint16_t extractHex(const char *str) {\n    uint16_t result = 0;\n    while (*str) {\n        char c = *str++;\n        if (c >= '0' && c <= '9') {\n            result = (result << 4) | (c - '0');\n\n        } else if (c >= 'A' && c <= 'F') {\n            result = (result << 4) | (c - 'A' + 10);\n        } else {\n            continue; // 遇到非十六进制字符，停止解析\n        }\n    }\n    return result;\n}\n\n#ifdef  ENABLE_MDC1200_CONTACT\nuint8_t contact_num=0;\n//uint16_t MDC_ADD[6] = {0x1D00, 0x1D40, 0x1D80,0x1DC0,0X1F90,0X1FD0};//SHIT ADDRESS COMBINE :(\nvoid mdc1200_update_contact_num()\n{\n    EEPROM_ReadBuffer(MDC_NUM_ADD, (uint8_t *)&contact_num, 1);\n    if(contact_num>MAX_CONTACT_NUM)contact_num=0;\n}\nbool mdc1200_contact_find(uint16_t mdc_id, char *contact) {\n    mdc1200_update_contact_num();\n    uint16_t add = 0x1D00;\n    for (uint8_t i = 0; i < contact_num; i++) {\n        uint8_t read_once[16]={0};\n\n        EEPROM_ReadBuffer(add , read_once, 16);\n        if (mdc_id == (uint16_t) (read_once[1] | (read_once[0] << 8))) {\n            for (int j = 0; j < 14; ++j) {\n                if(read_once[2+j]<' '||read_once[2+j]>'~')\n                    return false;\n            }\n\n            memcpy(contact,read_once+2,14);\n\n            return true;\n        }\n                add+=16;\n        if(add==0x1E00)add=0X1F90;\n    }\n    return false;\n}\n#endif\n"
  },
  {
    "path": "app/mdc1200.h",
    "content": "\n#ifndef MDC1200H\n#define MDC1200H\n\n#include <stdint.h>\n#include <stdbool.h>\n\n#define MDC1200_FEC_K   7        // R=1/2 K=7 convolutional coder\n\n// 0x00 (0x81) emergency alarm\n// 0x20 (0x00) emergency alarm ack\n//\n// 0x01 (0x80) is PTT ID\n// 0x01 (0x00) is POST ID\n// 0x11 (0x8A) is REMOTE MONITOR\n// 0x22 (0x06) is STATUS REQ\n// 0x2B (0x0C) is RADIO ENABLE\n// 0x2B (0x00) is RADIO DISABLE\n// 0x35 (0x89) is CALL ALERT\n// 0x46 (0xXX) is STS XX\n// 0x47 (0xXX) is MSG XX\n//\n// 0x63 (0x85) is RADIO CHECK\n// 0x30 (0x00) is RADIO CHECK ack\n//\n// * CALL ALERT [Double packet - 2 codewords, 1234 places call to 5678]\n// 3589 5678 830D 1234 [Spectra, Astro Saber \"PAGE\", Maxtrac \"CA\" w/Ack Expected=Y]\n// 3589 5678 810D 1234 [Maxtrac \"CA\" w/Ack Expected=N]\n//\n// * VOICE SELECTIVE CALL [Double packet - 2 codewords, 1234 places call to 5678]\n// 3589 5678 8205 1234 [Spectra \"CALL\"]\n// 3589 5678 8015 1234 [Maxtrac \"SC\", Astro Saber \"CALL\"]\n// \n// * CALL ALERT ACKNOWLEDGE [Double packet - 2 codewords, 5678 acks the call from 1234]\n// 3589 1234 A000 5678\n// \n// * SIMPLE STATUS [unit 1234 transmits status number X]\n// 460X 1234\n// \n// * STATUS ACKNOWLEDGE\n// 2300 1234\n// \n// * STATUS REQUEST [i.e. unit 5678 report your last status]\n// 2206 5678\n// \n// * STATUS RESPONSE [from target 5678 when interrogated]\n// 060X 5678\n// \n// * INBOUND MESSAGE\n// 470X 1234 [ack expected]\n// 070X 1234 [ack not expected CDM1550]\n// \n// * INBOUND MESSAGE ACKNOWLEDGE\n// 2300 1234\n// \n// * REMOTE MONITOR [No MDC response from target unless it has PTT ID]\n// 118A 5678 [118A per KA6SQG]\n// \n// * SELECTIVE RADIO INHIBIT [Fixed end inhibits target 5678]\n// 2B00 5678\n// \n// * SELECTIVE RADIO INHIBIT ACKNOWLEDGE [5678 acks the inhibit]\n// 0B00 5678\n// \n// * SELECTIVE RADIO INHIBIT CANCEL [Fixed end enables target 5678]\n// 2B0C 5678\n// \n// * SELECTIVE RADIO INHIBIT CANCEL [5678 acks the enable]\n// 0B0C 5678\n// \n// * REQUEST TO TALK [Unit 1234 asks fixed end for permission to PTT]\n// 4001 1234 [CDM1550 dedicated button]\n// 4101 1234 [CDM1550 slaved to mic PTT]\n// \n// * REQUEST TO TALK ACKNOWLEDGE\n// 2300 1234 [general ack - not same as permission to PTT]\n\nenum mdc1200_op_code_e {\n    MDC1200_OP_CODE_PTT_ID = 0x01,\n    MDC1200_OP_CODE_POST_ID = 0x01,\n    MDC1200_OP_CODE_REMOTE_MONITOR = 0x11,\n    MDC1200_OP_CODE_STATUS_REQ = 0x22,\n    MDC1200_OP_CODE_RADIO_ENABLE = 0x2B,\n    MDC1200_OP_CODE_RADIO_DISABLE = 0x2B,\n    MDC1200_OP_CODE_CALL_ALERT = 0x35,\n    MDC1200_OP_CODE_STS_XX = 0x46,\n    MDC1200_OP_CODE_MSG_XX = 0x47,\n    MDC1200_OP_CODE_RADIO_CHECK = 0x63\n};\ntypedef enum mdc1200_op_code_e mdc1200_op_code_t;\n\nextern const uint8_t mdc1200_sync[5];\nextern const uint8_t mdc1200_sync_suc_xor[5];\n\nextern uint8_t mdc1200_op;\nextern uint8_t mdc1200_arg;\nextern uint16_t mdc1200_unit_id;\n\nbool mdc1200_contact_find(uint16_t mdc_id, char *contact);\n\nextern uint8_t mdc1200_rx_buffer[5 + (MDC1200_FEC_K * 2)];\nextern unsigned int mdc1200_rx_buffer_index;\n\nbool MDC1200_process_rx_data(const void *buffer, const unsigned int size, uint8_t *op, uint8_t *arg, uint16_t *unit_id);\n\nextern uint8_t mdc1200_rx_ready_tick_500ms;\n\nunsigned int MDC1200_encode_single_packet(void *data, const uint8_t op, const uint8_t arg, const uint16_t unit_id);\n\nvoid MDC1200_reset_rx(void);\n\nvoid MDC1200_init(void);\n\n\nuint16_t extractHex(const char *str);\n\n//extern uint16_t MDC_ADD[6];\n#define MDC_NUM_ADD 0X1FFF\n#define MAX_CONTACT_NUM 21\nextern uint8_t contact_num;\n\n#endif\n"
  },
  {
    "path": "app/menu.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include <stdio.h>\r\n#include \"app/mdc1200.h\"\r\n#include <string.h>\r\n#include \"driver/uart.h\"\r\n#include \"ui/helper.h\"\r\n\r\n#if !defined(ENABLE_OVERLAY)\r\n\r\n#include \"ARMCM0.h\"\r\n\r\n#endif\r\n\r\n#include \"app/dtmf.h\"\r\n#include \"app/generic.h\"\r\n#include \"app/menu.h\"\r\n#include \"app/scanner.h\"\r\n#include \"audio.h\"\r\n#include \"board.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/backlight.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/keyboard.h\"\r\n#include \"frequencies.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n\r\n#if defined(ENABLE_OVERLAY)\r\n#include \"sram-overlay.h\"\r\n#endif\r\n\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/menu.h\"\r\n#include \"ui/menu.h\"\r\n#include \"ui/ui.h\"\r\n\r\n#ifndef ARRAY_SIZE\r\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r\n#endif\r\n\r\n//uint8_t gUnlockAllTxConfCnt;\r\n\r\n#ifdef ENABLE_F_CAL_MENU\r\nvoid writeXtalFreqCal(const int32_t value, const bool update_eeprom)\r\n{\r\n    BK4819_WriteRegister(BK4819_REG_3B, 22656 + value);\r\n\r\n    if (update_eeprom)\r\n    {\r\n        struct\r\n        {\r\n            int16_t  BK4819_XtalFreqLow;\r\n            uint16_t EEPROM_1F8A;\r\n            uint16_t EEPROM_1F8C;\r\n            uint8_t  VOLUME_GAIN;\r\n            uint8_t  DAC_GAIN;\r\n        } __attribute__((packed)) misc;\r\n\r\n        gEeprom.BK4819_XTAL_FREQ_LOW = value;\r\n\r\n        // radio 1 .. 04 00 46 00 50 00 2C 0E\r\n        // radio 2 .. 05 00 46 00 50 00 2C 0E\r\n        //\r\n        EEPROM_ReadBuffer(0x1F88, &misc, 8);\r\n        misc.BK4819_XtalFreqLow = value;\r\n        EEPROM_WriteBuffer(0x1F88, &misc,8);\r\n    }\r\n}\r\n#endif\r\n\r\n\r\nvoid MENU_StartCssScan(void) {\r\n    SCANNER_Start(true);\r\n    gUpdateStatus = true;\r\n    gCssBackgroundScan = true;\r\n\r\n    gRequestDisplayScreen = DISPLAY_MENU;\r\n}\r\n#ifdef ENABLE_PINYIN\r\nvoid PINYIN_SOLVE(uint32_t tmp) {\r\n\r\n    if (INPUT_STAGE == 0) {\r\n        INPUT_STAGE = 1;\r\n    }\r\n    uint8_t tmp_PINYIN_SEARCH_INDEX = PINYIN_SEARCH_INDEX;\r\n    uint8_t tmp_PINYIN_SEARCH_NUM = PINYIN_SEARCH_NUM;\r\n    uint8_t tmp_PINYIN_SEARCH_FOUND = PINYIN_SEARCH_FOUND;\r\n\r\n    PINYIN_SEARCH_INDEX = sear_pinyin_code(PINYIN_CODE, &PINYIN_SEARCH_NUM, &PINYIN_SEARCH_FOUND);\r\n\r\n    if (PINYIN_SEARCH_INDEX == 255 && PINYIN_SEARCH_FOUND == 0) {\r\n        PINYIN_CODE = tmp;\r\n        PINYIN_CODE_INDEX *= 10;\r\n        PINYIN_SEARCH_INDEX = tmp_PINYIN_SEARCH_INDEX;\r\n        PINYIN_SEARCH_NUM = tmp_PINYIN_SEARCH_NUM;\r\n        PINYIN_SEARCH_FOUND = tmp_PINYIN_SEARCH_FOUND;\r\n        if (PINYIN_CODE_INDEX == 100000)INPUT_STAGE = 0;\r\n    }\r\n\r\n    if (INPUT_STAGE) {\r\n        //Ҫѡƴ\r\n        if (PINYIN_SEARCH_FOUND) {\r\n            if (PINYIN_SEARCH_INDEX != 255) {\r\n                //ȷʵƴ\r\n                PINYIN_NOW_INDEX = PINYIN_SEARCH_INDEX;\r\n                PINYIN_NOW_NUM = PINYIN_SEARCH_NUM;\r\n                PINYIN_SEARCH_MODE = 1;\r\n            }\r\n        } else {\r\n            //ûƴϵбѡ\r\n//            PINYIN_SEARCH_MODE = 2;\r\n//            PINYIN_NOW_INDEX = PINYIN_SEARCH_INDEX;\r\n//            PINYIN_NOW_NUM = PINYIN_SEARCH_NUM;\r\n//            PINYIN_START_INDEX = PINYIN_NOW_INDEX;\r\n//\r\n//            for (int i = PINYIN_START_INDEX; i < 214; ++i) {\r\n//                uint8_t tmp[4];\r\n//                uint32_t tmp_code;\r\n//                EEPROM_ReadBuffer(128 * i + 0x20000, tmp, 4);\r\n//                tmp_code = tmp[0] | tmp[1] << 8 | tmp[2] << 16 | tmp[3] << 24;\r\n//                if (judge_belong(PINYIN_CODE, tmp_code)) {\r\n//                    PINYIN_END_INDEX = i;\r\n//                } else break;\r\n//            }\r\n        }\r\n    }\r\n}\r\n#endif\r\nvoid MENU_CssScanFound(void) {\r\n    if (gScanCssResultType == CODE_TYPE_DIGITAL || gScanCssResultType == CODE_TYPE_REVERSE_DIGITAL) {\r\n        gMenuCursor = UI_MENU_GetMenuIdx(MENU_R_DCS);\r\n    } else if (gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE) {\r\n        gMenuCursor = UI_MENU_GetMenuIdx(MENU_R_CTCS);\r\n    }\r\n\r\n    MENU_ShowCurrentSetting();\r\n\r\n    gUpdateStatus = true;\r\n    gUpdateDisplay = true;\r\n}\r\n\r\nvoid MENU_StopCssScan(void) {\r\n    gCssBackgroundScan = false;\r\n\r\n#ifdef ENABLE_VOICE\r\n    gAnotherVoiceID       = VOICE_ID_SCANNING_STOP;\r\n#endif\r\n    gUpdateDisplay = true;\r\n    gUpdateStatus = true;\r\n}\r\n\r\nint MENU_GetLimits(uint8_t menu_id, int32_t *pMin, int32_t *pMax) {\r\n    switch (menu_id) {\r\n        case MENU_SQL:\r\n            *pMin = 0;\r\n            *pMax = 9;\r\n            break;\r\n\r\n        case MENU_STEP:\r\n            *pMin = 0;\r\n            *pMax = STEP_N_ELEM - 1;\r\n            break;\r\n\r\n        case MENU_ABR:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_BACKLIGHT) - 1;\r\n            break;\r\n\r\n//\t\tcase MENU_ABR_MIN:\r\n//\t\t\t*pMin = 0;\r\n//\t\t\t*pMax = 9;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_ABR_MAX:\r\n            *pMin = 1;\r\n            *pMax = 10;\r\n            break;\r\n\r\n        case MENU_F_LOCK:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_F_LOCK) - 1;\r\n            break;\r\n\r\n        case MENU_MDF:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_MDF) - 1;\r\n            break;\r\n\r\n//\t\tcase MENU_TXP:\r\n//\t\t\t*pMin = 0;\r\n//\t\t\t*pMax = ARRAY_SIZE(gSubMenu_TXP) - 1;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_SFT_D:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_SFT_D) - 1;\r\n            break;\r\n\r\n        case MENU_TDR:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_RXMode) - 1;\r\n            break;\r\n\r\n#ifdef ENABLE_VOICE\r\n            case MENU_VOICE:\r\n                *pMin = 0;\r\n                *pMax = ARRAY_SIZE(gSubMenu_VOICE) - 1;\r\n                break;\r\n#endif\r\n\r\n        case MENU_SC_REV:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_SC_REV) - 1;\r\n            break;\r\n\r\n        case MENU_ROGER:\r\n            *pMin = 0;\r\n#ifndef ENABLE_MDC1200\r\n            *pMax = 1;\r\n#else\r\n            *pMax = ARRAY_SIZE(gSubMenu_ROGER) - 1;\r\n#endif\r\n            break;\r\n#if ENABLE_CHINESE_FULL == 4\r\n\r\n            case MENU_PONMSG:\r\n                *pMin = 0;\r\n                *pMax = ARRAY_SIZE(gSubMenu_PONMSG) - 1;\r\n                break;\r\n#endif\r\n        case MENU_R_DCS:\r\n        case MENU_T_DCS:\r\n            *pMin = 0;\r\n            *pMax = 208;\r\n            //*pMax = (104 * 2);\r\n            break;\r\n\r\n        case MENU_R_CTCS:\r\n        case MENU_T_CTCS:\r\n            *pMin = 0;\r\n            *pMax = 50;\r\n            break;\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n            case MENU_W_N:\r\n                *pMin = 0;\r\n                *pMax = ARRAY_SIZE(gSubMenu_W_N) - 1;\r\n                break;\r\n#endif\r\n#ifdef ENABLE_ALARM\r\n            case MENU_AL_MOD:\r\n                *pMin = 0;\r\n                *pMax = ARRAY_SIZE(gSubMenu_AL_MOD) - 1;\r\n                break;\r\n#endif\r\n\r\n        case MENU_RESET:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_RESET) - 1;\r\n            break;\r\n\r\n        case MENU_COMPAND:\r\n//\t\tcase MENU_ABR_ON_TX_RX:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_RX_TX) - 1;\r\n            break;\r\n\r\n#ifdef ENABLE_AM_FIX_TEST1\r\n            case MENU_AM_FIX_TEST1:\r\n                *pMin = 0;\r\n                *pMax = ARRAY_SIZE(gSubMenu_AM_fix_test1) - 1;\r\n                break;\r\n#endif\r\n\r\n#ifdef ENABLE_AM_FIX\r\n            case MENU_AM_FIX:\r\n#endif\r\n//#ifdef ENABLE_AUDIO_BAR\r\n            //case MENU_MIC_BAR:\r\n//#endif\r\n        case MENU_BCL:\r\n            //\tcase MENU_BEEP:\r\n            //case MENU_AUTOLK:\r\n            //case MENU_S_ADD1:\r\n            //case MENU_S_ADD2:\r\n        case MENU_STE:\r\n        case MENU_D_ST:\r\n#ifdef ENABLE_DTMF_CALLING\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n            case MENU_D_DCD:\r\n#endif\r\n#endif\r\n        case MENU_D_LIVE_DEC:\r\n#ifdef ENABLE_NOAA\r\n            case MENU_NOAA_S:\r\n#endif\r\n//\t\tcase MENU_350TX:\r\n//\t\tcase MENU_200TX:\r\n//\t\tcase MENU_500TX:\r\n//\t\tcase MENU_350EN:\r\n//\t\tcase MENU_SCREN:\r\n//\t\t\t*pMin = 0;\r\n//\t\t\t*pMax = ARRAY_SIZE(gSubMenu_OFF_ON) - 1;\r\n//\t\t\tbreak;\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_OFF_ON) - 1;\r\n            break;\r\n//\t\tcase MENU_AM:\r\n//\t\t\t*pMin = 0;\r\n//\t\t\t*pMax = ARRAY_SIZE(gModulationStr) - 1;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_SCR:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_SCRAMBLER) - 1;\r\n            break;\r\n\r\n        case MENU_TOT:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_TOT) - 1;\r\n            break;\r\n\r\n#ifdef ENABLE_VOX\r\n            //case MENU_VOX:\r\n#endif\r\n        case MENU_RP_STE:\r\n            *pMin = 0;\r\n            *pMax = 10;\r\n            break;\r\n\r\n        case MENU_MEM_CH:\r\n        case MENU_1_CALL:\r\n        case MENU_DEL_CH:\r\n        case MENU_MEM_NAME:\r\n            *pMin = 0;\r\n            *pMax = MR_CHANNEL_LAST;\r\n            break;\r\n\r\n        case MENU_SLIST1:\r\n        case MENU_SLIST2:\r\n            *pMin = -1;\r\n            *pMax = MR_CHANNEL_LAST;\r\n            break;\r\n\r\n        case MENU_SAVE:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_SAVE) - 1;\r\n            break;\r\n\r\n        case MENU_MIC:\r\n            *pMin = 0;\r\n            *pMax = 4;\r\n            break;\r\n\r\n        case MENU_S_LIST:\r\n            *pMin = 0;\r\n            *pMax = 2;\r\n            break;\r\n#ifdef ENABLE_DTMF_CALLING\r\n            case MENU_D_RSP:\r\n                *pMin = 0;\r\n                *pMax = ARRAY_SIZE(gSubMenu_D_RSP) - 1;\r\n                break;\r\n#endif\r\n        case MENU_PTT_ID:\r\n            *pMin = 0;\r\n            *pMax = ARRAY_SIZE(gSubMenu_PTT_ID) - 1;\r\n            break;\r\n\r\n//\t\tcase MENU_BAT_TXT:\r\n//\t\t\t*pMin = 0;\r\n//\t\t\t*pMax = ARRAY_SIZE(gSubMenu_BAT_TXT) - 1;\r\n//\t\t\tbreak;\r\n#ifdef ENABLE_DTMF_CALLING\r\n            case MENU_D_HOLD:\r\n                *pMin = 5;\r\n                *pMax = 60;\r\n                break;\r\n#endif\r\n        case MENU_D_PRE:\r\n            *pMin = 3;\r\n            *pMax = 99;\r\n            break;\r\n#ifdef ENABLE_DTMF_CALLING\r\n            case MENU_D_LIST:\r\n                *pMin = 1;\r\n                *pMax = 16;\r\n                break;\r\n#endif\r\n#ifdef ENABLE_F_CAL_MENU\r\n            case MENU_F_CALI:\r\n                *pMin = -50;\r\n                *pMax = +50;\r\n                break;\r\n#endif\r\n\r\n        case MENU_BATCAL:\r\n            *pMin = 1600;\r\n            *pMax = 2200;\r\n            break;\r\n\r\n        case MENU_BATTYP:\r\n            *pMin = 0;\r\n            *pMax = 1;\r\n            break;\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n            case MENU_F1SHRT:\r\n            case MENU_F2SHRT:\r\n                *pMin = 0;\r\n\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\n                *pMax = gSubMenu_SIDEFUNCTIONS_size-3;\r\n\r\n#else\r\n                *pMax =gSubMenu_SIDEFUNCTIONS_size-1;\r\n\r\n#endif\r\n                 break;\r\n            case MENU_F1LONG:\r\n            case MENU_F2LONG:\r\n            case MENU_MLONG:\r\n                *pMin = 0;\r\n\r\n\r\n                *pMax = gSubMenu_SIDEFUNCTIONS_size-1;\r\n\r\n                break;\r\n#endif\r\n\r\n        default:\r\n            return -1;\r\n    }\r\n\r\n    return 0;\r\n}\r\n\r\nvoid MENU_AcceptSetting(void) {\r\n    int32_t Min;\r\n    int32_t Max;\r\n    FREQ_Config_t *pConfig = &gTxVfo->freq_config_RX;\r\n\r\n    if (!MENU_GetLimits(UI_MENU_GetCurrentMenuId(), &Min, &Max)) {\r\n        if (gSubMenuSelection < Min) gSubMenuSelection = Min;\r\n        else if (gSubMenuSelection > Max) gSubMenuSelection = Max;\r\n    }\r\n    char a = gSubMenuSelection;//UART_Send(a,1);\r\n    UART_Send((uint8_t *) &a, 1);\r\n\r\n    switch (UI_MENU_GetCurrentMenuId()) {\r\n        default:\r\n            return;\r\n\r\n        case MENU_SQL:\r\n            gEeprom.SQUELCH_LEVEL = gSubMenuSelection;\r\n            gVfoConfigureMode = VFO_CONFIGURE;\r\n            break;\r\n\r\n        case MENU_STEP:\r\n            gTxVfo->STEP_SETTING = FREQUENCY_GetStepIdxFromSortedIdx(gSubMenuSelection);\r\n            if (IS_FREQ_CHANNEL(gTxVfo->CHANNEL_SAVE)) {\r\n                gRequestSaveChannel = 1;\r\n                return;\r\n            }\r\n            return;\r\n\r\n//\t\tcase MENU_TXP:\r\n//\t\t\tgTxVfo->OUTPUT_POWER = gSubMenuSelection;\r\n//\t\t\tgRequestSaveChannel = 1;\r\n//\t\t\treturn;\r\n\r\n        case MENU_T_DCS:\r\n            pConfig = &gTxVfo->freq_config_TX;\r\n\r\n            // Fallthrough\r\n\r\n        case MENU_R_DCS: {\r\n            if (gSubMenuSelection == 0) {\r\n                if (pConfig->CodeType == CODE_TYPE_CONTINUOUS_TONE) {\r\n                    return;\r\n                }\r\n                pConfig->Code = 0;\r\n                pConfig->CodeType = CODE_TYPE_OFF;\r\n            } else if (gSubMenuSelection < 105) {\r\n                pConfig->CodeType = CODE_TYPE_DIGITAL;\r\n                pConfig->Code = gSubMenuSelection - 1;\r\n            } else {\r\n                pConfig->CodeType = CODE_TYPE_REVERSE_DIGITAL;\r\n                pConfig->Code = gSubMenuSelection - 105;\r\n            }\r\n\r\n            gRequestSaveChannel = 1;\r\n            return;\r\n        }\r\n        case MENU_T_CTCS:\r\n            pConfig = &gTxVfo->freq_config_TX;\r\n            [[fallthrough]];\r\n        case MENU_R_CTCS: {\r\n            if (gSubMenuSelection == 0) {\r\n                if (pConfig->CodeType != CODE_TYPE_CONTINUOUS_TONE) {\r\n                    return;\r\n                }\r\n                pConfig->Code = 0;\r\n                pConfig->CodeType = CODE_TYPE_OFF;\r\n\r\n            } else {\r\n                pConfig->Code = gSubMenuSelection - 1;\r\n                pConfig->CodeType = CODE_TYPE_CONTINUOUS_TONE;\r\n\r\n            }\r\n\r\n            gRequestSaveChannel = 1;\r\n            return;\r\n        }\r\n\r\n        case MENU_SFT_D:\r\n            gTxVfo->TX_OFFSET_FREQUENCY_DIRECTION = gSubMenuSelection;\r\n            gRequestSaveChannel = 1;\r\n            return;\r\n\r\n        case MENU_OFFSET:\r\n            gTxVfo->TX_OFFSET_FREQUENCY = gSubMenuSelection;\r\n            gRequestSaveChannel = 1;\r\n            return;\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n            case MENU_W_N:\r\n                gTxVfo->CHANNEL_BANDWIDTH = gSubMenuSelection;\r\n                gRequestSaveChannel       = 1;\r\n                return;\r\n#endif\r\n        case MENU_SCR:\r\n            gTxVfo->SCRAMBLING_TYPE = gSubMenuSelection;\r\n#if 0\r\n            if (gSubMenuSelection > 0 && gSetting_ScrambleEnable)\r\n                BK4819_EnableScramble(gSubMenuSelection - 1);\r\n            else\r\n                BK4819_DisableScramble();\r\n#endif\r\n            gRequestSaveChannel = 1;\r\n            return;\r\n\r\n        case MENU_BCL:\r\n            gTxVfo->BUSY_CHANNEL_LOCK = gSubMenuSelection;\r\n            gRequestSaveChannel = 1;\r\n            return;\r\n\r\n        case MENU_MEM_CH:\r\n            gTxVfo->CHANNEL_SAVE = gSubMenuSelection;\r\n#if 0\r\n            gEeprom.MrChannel[0] = gSubMenuSelection;\r\n#else\r\n            gEeprom.MrChannel[gEeprom.TX_VFO] = gSubMenuSelection;\r\n#endif\r\n            gRequestSaveChannel = 2;\r\n            gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\r\n            gFlagResetVfos = true;\r\n            return;\r\n#ifdef ENABLE_MDC1200\r\n            case MENU_MDC_ID:\r\n#ifdef ENABLE_MDC1200_EDIT\r\n        gEeprom.MDC1200_ID=extractHex(edit);\r\n#endif\r\n\r\n            return;\r\n#endif\r\n        case MENU_MEM_NAME: //뷨\r\n            // trailing trim\r\n            for (int i = MAX_EDIT_INDEX - 1; i >= 0; i--) {\r\n                if (edit[i] != ' ' && edit[i] != '_' && edit[i] != 0x00 && edit[i] != 0xff)\r\n                    break;\r\n                edit[i] = 0;\r\n            }\r\n\r\n            SETTINGS_SaveChannelName(gSubMenuSelection, edit);\r\n            return;\r\n\r\n        case MENU_SAVE:\r\n            gEeprom.BATTERY_SAVE = gSubMenuSelection;\r\n            break;\r\n\r\n#ifdef ENABLE_VOX\r\n            //\t\t\tcase MENU_VOX:\r\n            //\t\t\t\tgEeprom.VOX_SWITCH = gSubMenuSelection != 0;\r\n            //\t\t\t\tif (gEeprom.VOX_SWITCH)\r\n            //\t\t\t\t\tgEeprom.VOX_LEVEL = gSubMenuSelection - 1;\r\n            //\t\t\t\tSETTINGS_LoadCalibration();\r\n            //\t\t\t\tgFlagReconfigureVfos = true;\r\n            //\t\t\t\tgUpdateStatus        = true;\r\n            //\t\t\t\tbreak;\r\n#endif\r\n\r\n        case MENU_ABR:\r\n            gEeprom.BACKLIGHT_TIME = gSubMenuSelection;\r\n            break;\r\n\r\n//\t\tcase MENU_ABR_MIN:\r\n//\t\t\tgEeprom.BACKLIGHT_MIN = gSubMenuSelection;\r\n//\t\t\tgEeprom.BACKLIGHT_MAX = MAX(gSubMenuSelection + 1 , gEeprom.BACKLIGHT_MAX);\r\n//\t\t\tbreak;\r\n\r\n        case MENU_ABR_MAX:\r\n            gEeprom.BACKLIGHT_MAX = gSubMenuSelection;\r\n            break;\r\n\r\n//\t\tcase MENU_ABR_ON_TX_RX:\r\n//\t\t\tgSetting_backlight_on_tx_rx = gSubMenuSelection;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_TDR:\r\n            gEeprom.DUAL_WATCH = (gEeprom.TX_VFO + 1) * (gSubMenuSelection & 1);\r\n            gEeprom.CROSS_BAND_RX_TX = (gEeprom.TX_VFO + 1) * ((gSubMenuSelection & 2) > 0);\r\n\r\n            gFlagReconfigureVfos = true;\r\n            gUpdateStatus = true;\r\n            break;\r\n\r\n//\t\tcase MENU_BEEP:\r\n//\t\t\tgEeprom.BEEP_CONTROL = gSubMenuSelection;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_TOT:\r\n            gEeprom.TX_TIMEOUT_TIMER = gSubMenuSelection;\r\n            break;\r\n\r\n#ifdef ENABLE_VOICE\r\n            case MENU_VOICE:\r\n                gEeprom.VOICE_PROMPT = gSubMenuSelection;\r\n                gUpdateStatus        = true;\r\n                break;\r\n#endif\r\n\r\n        case MENU_SC_REV:\r\n            gEeprom.SCAN_RESUME_MODE = gSubMenuSelection;\r\n            break;\r\n\r\n        case MENU_MDF:\r\n            gEeprom.CHANNEL_DISPLAY_MODE = gSubMenuSelection;\r\n            break;\r\n\r\n//\t\tcase MENU_AUTOLK:\r\n//\t\t\tgEeprom.AUTO_KEYPAD_LOCK = gSubMenuSelection;\r\n//\t\t\tgKeyLockCountdown        = 30;\r\n//\t\t\tbreak;\r\n\r\n//\t\tcase MENU_S_ADD1:\r\n//\t\t\tgTxVfo->SCANLIST1_PARTICIPATION = gSubMenuSelection;\r\n//\t\t\tSETTINGS_UpdateChannel(gTxVfo->CHANNEL_SAVE, gTxVfo, true);\r\n//\t\t\tgVfoConfigureMode = VFO_CONFIGURE;\r\n//\t\t\tgFlagResetVfos    = true;\r\n//\t\t\treturn;\r\n\r\n//\t\tcase MENU_S_ADD2:\r\n//\t\t\tgTxVfo->SCANLIST2_PARTICIPATION = gSubMenuSelection;\r\n//\t\t\tSETTINGS_UpdateChannel(gTxVfo->CHANNEL_SAVE, gTxVfo, true);\r\n//\t\t\tgVfoConfigureMode = VFO_CONFIGURE;\r\n//\t\t\tgFlagResetVfos    = true;\r\n//\t\t\treturn;\r\n\r\n        case MENU_STE:\r\n            gEeprom.TAIL_TONE_ELIMINATION = gSubMenuSelection;\r\n            break;\r\n\r\n        case MENU_RP_STE:\r\n            gEeprom.REPEATER_TAIL_TONE_ELIMINATION = gSubMenuSelection;\r\n            break;\r\n\r\n        case MENU_MIC:\r\n            gEeprom.MIC_SENSITIVITY = gSubMenuSelection;\r\n            SETTINGS_LoadCalibration();\r\n            gFlagReconfigureVfos = true;\r\n            break;\r\n\r\n//#ifdef ENABLE_AUDIO_BAR\r\n            //\t\t\tcase MENU_MIC_BAR:\r\n            //\t\t\t\tgSetting_mic_bar = gSubMenuSelection;\r\n            //\t\t\t\tbreak;\r\n//#endif\r\n\r\n        case MENU_COMPAND:\r\n            gTxVfo->Compander = gSubMenuSelection;\r\n            SETTINGS_UpdateChannel(gTxVfo->CHANNEL_SAVE, gTxVfo, true);\r\n            gVfoConfigureMode = VFO_CONFIGURE;\r\n            gFlagResetVfos = true;\r\n//\t\t\tgRequestSaveChannel = 1;\r\n            return;\r\n\r\n        case MENU_1_CALL:\r\n            gEeprom.CHAN_1_CALL = gSubMenuSelection;\r\n            break;\r\n\r\n        case MENU_S_LIST:\r\n            gEeprom.SCAN_LIST_DEFAULT = gSubMenuSelection;\r\n            break;\r\n\r\n#ifdef ENABLE_ALARM\r\n            case MENU_AL_MOD:\r\n                gEeprom.ALARM_MODE = gSubMenuSelection;\r\n                break;\r\n#endif\r\n\r\n        case MENU_D_ST:\r\n            gEeprom.DTMF_SIDE_TONE = gSubMenuSelection;\r\n            break;\r\n#ifdef ENABLE_DTMF_CALLING\r\n            case MENU_D_RSP:\r\n                gEeprom.DTMF_DECODE_RESPONSE = gSubMenuSelection;\r\n                break;\r\n\r\n            case MENU_D_HOLD:\r\n                gEeprom.DTMF_auto_reset_time = gSubMenuSelection;\r\n                break;\r\n#endif\r\n        case MENU_D_PRE:\r\n            gEeprom.DTMF_PRELOAD_TIME = gSubMenuSelection * 10;\r\n            break;\r\n\r\n        case MENU_PTT_ID:\r\n            gTxVfo->DTMF_PTT_ID_TX_MODE = gSubMenuSelection;\r\n            gRequestSaveChannel = 1;\r\n            return;\r\n\r\n//\t\tcase MENU_BAT_TXT:\r\n//\t\t\tgSetting_battery_text = gSubMenuSelection;\r\n//\t\t\tbreak;\r\n#ifdef ENABLE_DTMF_CALLING\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n            case MENU_D_DCD:\r\n                gTxVfo->DTMF_DECODING_ENABLE = gSubMenuSelection;\r\n                DTMF_clear_RX();\r\n                gRequestSaveChannel = 1;\r\n                return;\r\n#endif\r\n#endif\r\n        case MENU_D_LIVE_DEC:\r\n            gSetting_live_DTMF_decoder = gSubMenuSelection;\r\n            gDTMF_RX_live_timeout = 0;\r\n            memset(gDTMF_RX_live, 0, sizeof(gDTMF_RX_live));\r\n            if (!gSetting_live_DTMF_decoder)\r\n                BK4819_DisableDTMF();\r\n            gFlagReconfigureVfos = true;\r\n            gUpdateStatus = true;\r\n            break;\r\n#ifdef ENABLE_DTMF_CALLING\r\n            case MENU_D_LIST:\r\n                gDTMF_chosen_contact = gSubMenuSelection - 1;\r\n                if (gIsDtmfContactValid)\r\n                {\r\n                    GUI_SelectNextDisplay(DISPLAY_MAIN);\r\n                    gDTMF_InputMode       = true;\r\n                    gDTMF_InputBox_Index  = 3;\r\n                    memcpy(gDTMF_InputBox, gDTMF_ID, 4);\r\n                    gRequestDisplayScreen = DISPLAY_INVALID;\r\n                }\r\n                return;\r\n#endif\r\n#if ENABLE_CHINESE_FULL == 4\r\n\r\n            case MENU_PONMSG:\r\n                gEeprom.POWER_ON_DISPLAY_MODE = gSubMenuSelection;\r\n                break;\r\n#endif\r\n        case MENU_ROGER:\r\n            gEeprom.ROGER = gSubMenuSelection;\r\n            break;\r\n\r\n//\t\tcase MENU_AM:\r\n//\t\t\tgTxVfo->Modulation     = gSubMenuSelection;\r\n//\t\t\tgRequestSaveChannel = 1;\r\n//\t\t\treturn;\r\n\r\n#ifdef ENABLE_AM_FIX\r\n            case MENU_AM_FIX:\r\n                gSetting_AM_fix = gSubMenuSelection;\r\n                gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\r\n                gFlagResetVfos    = true;\r\n                break;\r\n#endif\r\n\r\n#ifdef ENABLE_AM_FIX_TEST1\r\n            case MENU_AM_FIX_TEST1:\r\n                gSetting_AM_fix_test1 = gSubMenuSelection;\r\n                gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\r\n                gFlagResetVfos    = true;\r\n                break;\r\n#endif\r\n\r\n#ifdef ENABLE_NOAA\r\n            case MENU_NOAA_S:\r\n                gEeprom.NOAA_AUTO_SCAN = gSubMenuSelection;\r\n                gFlagReconfigureVfos   = true;\r\n                break;\r\n#endif\r\n\r\n        case MENU_DEL_CH:\r\n            SETTINGS_UpdateChannel(gSubMenuSelection, NULL, false);\r\n            gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\r\n            gFlagResetVfos = true;\r\n            return;\r\n\r\n        case MENU_RESET:\r\n            SETTINGS_FactoryReset(gSubMenuSelection);\r\n            return;\r\n\r\n//\t\tcase MENU_350TX:\r\n//\t\t\tgSetting_350TX = gSubMenuSelection;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_F_LOCK: {\r\n//\t\t\tif(gSubMenuSelection == F_LOCK_NONE) { // select 10 times to enable\r\n//\t\t\t\tgUnlockAllTxConfCnt++;\r\n//\t\t\t\tif(gUnlockAllTxConfCnt < 10)\r\n//\t\t\t\t\treturn;\r\n//\t\t\t}\r\n//\t\t\telse\r\n//\t\t\t\tgUnlockAllTxConfCnt = 0;\r\n\r\n            gSetting_F_LOCK = gSubMenuSelection;\r\n            break;\r\n        }\r\n//\t\tcase MENU_200TX:\r\n//\t\t\tgSetting_200TX = gSubMenuSelection;\r\n//\t\t\tbreak;\r\n//\r\n//\t\tcase MENU_500TX:\r\n//\t\t\tgSetting_500TX = gSubMenuSelection;\r\n//\t\t\tbreak;\r\n\r\n//\t\tcase MENU_350EN:\r\n//\t\t\tgSetting_350EN       = gSubMenuSelection;\r\n//\t\t\tgVfoConfigureMode    = VFO_CONFIGURE_RELOAD;\r\n//\t\t\tgFlagResetVfos       = true;\r\n//\t\t\tbreak;\r\n\r\n//\t\tcase MENU_SCREN:\r\n//\t\t\tgSetting_ScrambleEnable = gSubMenuSelection;\r\n//\t\t\tgFlagReconfigureVfos    = true;\r\n//\t\t\tbreak;\r\n\r\n#ifdef ENABLE_F_CAL_MENU\r\n            case MENU_F_CALI:\r\n                writeXtalFreqCal(gSubMenuSelection, true);\r\n                return;\r\n#endif\r\n\r\n        case MENU_BATCAL: {                                                                 // voltages are averages between discharge curves of 1600 and 2200 mAh\r\n            // gBatteryCalibration[0] = (520ul * gSubMenuSelection) / 760;  // 5.20V empty, blinking above this value, reduced functionality below\r\n            // gBatteryCalibration[1] = (689ul * gSubMenuSelection) / 760;  // 6.89V,  ~5%, 1 bars above this value\r\n            // gBatteryCalibration[2] = (724ul * gSubMenuSelection) / 760;  // 7.24V, ~17%, 2 bars above this value\r\n            gBatteryCalibration[3] = gSubMenuSelection;         // 7.6V,  ~29%, 3 bars above this value\r\n            // gBatteryCalibration[4] = (771ul * gSubMenuSelection) / 760;  // 7.71V, ~65%, 4 bars above this value\r\n            // gBatteryCalibration[5] = 2300;\r\n            SETTINGS_SaveBatteryCalibration(gBatteryCalibration);\r\n            return;\r\n        }\r\n\r\n        case MENU_BATTYP:\r\n            gEeprom.BATTERY_TYPE = gSubMenuSelection;\r\n            break;\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n            case MENU_F1SHRT:\r\n            case MENU_F1LONG:\r\n            case MENU_F2SHRT:\r\n            case MENU_F2LONG:\r\n            case MENU_MLONG:\r\n                {\r\n                    uint8_t * fun[]= {\r\n                        &gEeprom.KEY_1_SHORT_PRESS_ACTION,\r\n                        &gEeprom.KEY_1_LONG_PRESS_ACTION,\r\n                        &gEeprom.KEY_2_SHORT_PRESS_ACTION,\r\n                        &gEeprom.KEY_2_LONG_PRESS_ACTION,\r\n                        &gEeprom.KEY_M_LONG_PRESS_ACTION};\r\n                    *fun[UI_MENU_GetCurrentMenuId()-MENU_F1SHRT] = gSubMenu_SIDEFUNCTIONS[gSubMenuSelection].id;\r\n                }\r\n                break;\r\n#endif\r\n\r\n    }\r\n\r\n    gRequestSaveSettings = true;\r\n}\r\n\r\nstatic void MENU_ClampSelection(int8_t Direction) {\r\n    int32_t Min;\r\n    int32_t Max;\r\n\r\n    if (!MENU_GetLimits(UI_MENU_GetCurrentMenuId(), &Min, &Max)) {\r\n        int32_t Selection = gSubMenuSelection;\r\n        if (Selection < Min) Selection = Min;\r\n        else if (Selection > Max) Selection = Max;\r\n        gSubMenuSelection = NUMBER_AddWithWraparound(Selection, Direction, Min, Max);\r\n    }\r\n}\r\n\r\nvoid MENU_ShowCurrentSetting(void) {\r\n    switch (UI_MENU_GetCurrentMenuId()) {\r\n        case MENU_SQL:\r\n            gSubMenuSelection = gEeprom.SQUELCH_LEVEL;\r\n            break;\r\n\r\n        case MENU_STEP:\r\n            gSubMenuSelection = FREQUENCY_GetSortedIdxFromStepIdx(gTxVfo->STEP_SETTING);\r\n            break;\r\n\r\n//\t\tcase MENU_TXP:\r\n//\t\t\tgSubMenuSelection = gTxVfo->OUTPUT_POWER;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_RESET:\r\n            gSubMenuSelection = 0;\r\n            break;\r\n\r\n        case MENU_R_DCS:\r\n        case MENU_R_CTCS: {\r\n            DCS_CodeType_t type = gTxVfo->freq_config_RX.CodeType;\r\n            uint8_t code = gTxVfo->freq_config_RX.Code;\r\n            int menuid = UI_MENU_GetCurrentMenuId();\r\n\r\n            if (gScanUseCssResult) {\r\n                gScanUseCssResult = false;\r\n                type = gScanCssResultType;\r\n                code = gScanCssResultCode;\r\n            }\r\n            if ((menuid == MENU_R_CTCS) ^ (type == CODE_TYPE_CONTINUOUS_TONE)) { //not the same type\r\n                gSubMenuSelection = 0;\r\n                break;\r\n            }\r\n\r\n            switch (type) {\r\n                case CODE_TYPE_CONTINUOUS_TONE:\r\n                case CODE_TYPE_DIGITAL:\r\n                    gSubMenuSelection = code + 1;\r\n                    break;\r\n                case CODE_TYPE_REVERSE_DIGITAL:\r\n                    gSubMenuSelection = code + 105;\r\n                    break;\r\n                default:\r\n                    gSubMenuSelection = 0;\r\n                    break;\r\n            }\r\n            break;\r\n        }\r\n\r\n        case MENU_T_DCS:\r\n            switch (gTxVfo->freq_config_TX.CodeType) {\r\n                case CODE_TYPE_DIGITAL:\r\n                    gSubMenuSelection = gTxVfo->freq_config_TX.Code + 1;\r\n                    break;\r\n                case CODE_TYPE_REVERSE_DIGITAL:\r\n                    gSubMenuSelection = gTxVfo->freq_config_TX.Code + 105;\r\n                    break;\r\n                default:\r\n                    gSubMenuSelection = 0;\r\n                    break;\r\n            }\r\n            break;\r\n\r\n        case MENU_T_CTCS:\r\n            gSubMenuSelection = (gTxVfo->freq_config_TX.CodeType == CODE_TYPE_CONTINUOUS_TONE) ?\r\n                                gTxVfo->freq_config_TX.Code + 1 : 0;\r\n            break;\r\n\r\n        case MENU_SFT_D:\r\n            gSubMenuSelection = gTxVfo->TX_OFFSET_FREQUENCY_DIRECTION;\r\n            break;\r\n\r\n        case MENU_OFFSET:\r\n            gSubMenuSelection = gTxVfo->TX_OFFSET_FREQUENCY;\r\n            break;\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n        case MENU_W_N:\r\n            gSubMenuSelection = gTxVfo->CHANNEL_BANDWIDTH;\r\n            break;\r\n#endif\r\n        case MENU_SCR:\r\n            gSubMenuSelection = gTxVfo->SCRAMBLING_TYPE;\r\n            break;\r\n\r\n        case MENU_BCL:\r\n            gSubMenuSelection = gTxVfo->BUSY_CHANNEL_LOCK;\r\n            break;\r\n\r\n        case MENU_MEM_CH:\r\n#if 0\r\n            gSubMenuSelection = gEeprom.MrChannel[0];\r\n#else\r\n            gSubMenuSelection = gEeprom.MrChannel[gEeprom.TX_VFO];\r\n#endif\r\n            break;\r\n\r\n        case MENU_MEM_NAME:\r\n            gSubMenuSelection = gEeprom.MrChannel[gEeprom.TX_VFO];\r\n            break;\r\n\r\n        case MENU_SAVE:\r\n            gSubMenuSelection = gEeprom.BATTERY_SAVE;\r\n            break;\r\n\r\n#ifdef ENABLE_VOX\r\n            //\t\tcase MENU_VOX:\r\n            //\t\t\tgSubMenuSelection = gEeprom.VOX_SWITCH ? gEeprom.VOX_LEVEL + 1 : 0;\r\n            //\t\t\tbreak;\r\n#endif\r\n\r\n        case MENU_ABR:\r\n            gSubMenuSelection = gEeprom.BACKLIGHT_TIME;\r\n            break;\r\n\r\n//\t\tcase MENU_ABR_MIN:\r\n//\t\t\tgSubMenuSelection = gEeprom.BACKLIGHT_MIN;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_ABR_MAX:\r\n            gSubMenuSelection = gEeprom.BACKLIGHT_MAX;\r\n            break;\r\n\r\n//\t\tcase MENU_ABR_ON_TX_RX:\r\n//\t\t\tgSubMenuSelection = gSetting_backlight_on_tx_rx;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_TDR:\r\n            gSubMenuSelection =\r\n                    (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF) + (gEeprom.CROSS_BAND_RX_TX != CROSS_BAND_OFF) * 2;\r\n            break;\r\n\r\n//\t\tcase MENU_BEEP:\r\n//\t\t\tgSubMenuSelection = gEeprom.BEEP_CONTROL;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_TOT:\r\n            gSubMenuSelection = gEeprom.TX_TIMEOUT_TIMER;\r\n            break;\r\n\r\n#ifdef ENABLE_VOICE\r\n            case MENU_VOICE:\r\n                gSubMenuSelection = gEeprom.VOICE_PROMPT;\r\n                break;\r\n#endif\r\n\r\n        case MENU_SC_REV:\r\n            gSubMenuSelection = gEeprom.SCAN_RESUME_MODE;\r\n            break;\r\n\r\n        case MENU_MDF:\r\n            gSubMenuSelection = gEeprom.CHANNEL_DISPLAY_MODE;\r\n            break;\r\n\r\n//\t\tcase MENU_AUTOLK:\r\n//\t\t\tgSubMenuSelection = gEeprom.AUTO_KEYPAD_LOCK;\r\n//\t\t\tbreak;\r\n\r\n//\t\tcase MENU_S_ADD1:\r\n//\t\t\tgSubMenuSelection = gTxVfo->SCANLIST1_PARTICIPATION;\r\n//\t\t\tbreak;\r\n//\r\n//\t\tcase MENU_S_ADD2:\r\n//\t\t\tgSubMenuSelection = gTxVfo->SCANLIST2_PARTICIPATION;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_STE:\r\n            gSubMenuSelection = gEeprom.TAIL_TONE_ELIMINATION;\r\n            break;\r\n\r\n        case MENU_RP_STE:\r\n            gSubMenuSelection = gEeprom.REPEATER_TAIL_TONE_ELIMINATION;\r\n            break;\r\n\r\n        case MENU_MIC:\r\n            gSubMenuSelection = gEeprom.MIC_SENSITIVITY;\r\n            break;\r\n\r\n//#ifdef ENABLE_AUDIO_BAR\r\n            //\t\tcase MENU_MIC_BAR:\r\n            //\t\t\tgSubMenuSelection = gSetting_mic_bar;\r\n            //\t\t\tbreak;\r\n//#endif\r\n\r\n        case MENU_COMPAND:\r\n            gSubMenuSelection = gTxVfo->Compander;\r\n            return;\r\n\r\n        case MENU_1_CALL:\r\n            gSubMenuSelection = gEeprom.CHAN_1_CALL;\r\n            break;\r\n\r\n        case MENU_S_LIST:\r\n            gSubMenuSelection = gEeprom.SCAN_LIST_DEFAULT;\r\n            break;\r\n\r\n        case MENU_SLIST1:\r\n            gSubMenuSelection = RADIO_FindNextChannel(0, 1, true, 0);\r\n            break;\r\n\r\n        case MENU_SLIST2:\r\n            gSubMenuSelection = RADIO_FindNextChannel(0, 1, true, 1);\r\n            break;\r\n\r\n#ifdef ENABLE_ALARM\r\n            case MENU_AL_MOD:\r\n                gSubMenuSelection = gEeprom.ALARM_MODE;\r\n                break;\r\n#endif\r\n\r\n        case MENU_D_ST:\r\n            gSubMenuSelection = gEeprom.DTMF_SIDE_TONE;\r\n            break;\r\n#ifdef ENABLE_DTMF_CALLING\r\n        case MENU_D_RSP:\r\n            gSubMenuSelection = gEeprom.DTMF_DECODE_RESPONSE;\r\n            break;\r\n\r\n        case MENU_D_HOLD:\r\n            gSubMenuSelection = gEeprom.DTMF_auto_reset_time;\r\n            break;\r\n#endif\r\n        case MENU_D_PRE:\r\n            gSubMenuSelection = gEeprom.DTMF_PRELOAD_TIME / 10;\r\n            break;\r\n\r\n        case MENU_PTT_ID:\r\n            gSubMenuSelection = gTxVfo->DTMF_PTT_ID_TX_MODE;\r\n            break;\r\n\r\n//\t\tcase MENU_BAT_TXT:\r\n//\t\t\tgSubMenuSelection = gSetting_battery_text;\r\n//\t\t\treturn;\r\n#ifdef ENABLE_DTMF_CALLING\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n        case MENU_D_DCD:\r\n            gSubMenuSelection = gTxVfo->DTMF_DECODING_ENABLE;\r\n            break;\r\n#endif\r\n        case MENU_D_LIST:\r\n            gSubMenuSelection = gDTMF_chosen_contact + 1;\r\n            break;\r\n#endif\r\n        case MENU_D_LIVE_DEC:\r\n            gSubMenuSelection = gSetting_live_DTMF_decoder;\r\n            break;\r\n#if ENABLE_CHINESE_FULL == 4\r\n        case MENU_PONMSG:\r\n            gSubMenuSelection = gEeprom.POWER_ON_DISPLAY_MODE;\r\n            break;\r\n#endif\r\n        case MENU_ROGER:\r\n            gSubMenuSelection = gEeprom.ROGER;\r\n            break;\r\n\r\n//\t\tcase MENU_AM:\r\n//\t\t\tgSubMenuSelection = gTxVfo->Modulation;\r\n//\t\t\tbreak;\r\n\r\n#ifdef ENABLE_AM_FIX\r\n        case MENU_AM_FIX:\r\n            gSubMenuSelection = gSetting_AM_fix;\r\n            break;\r\n#endif\r\n\r\n#ifdef ENABLE_AM_FIX_TEST1\r\n            case MENU_AM_FIX_TEST1:\r\n                gSubMenuSelection = gSetting_AM_fix_test1;\r\n                break;\r\n#endif\r\n\r\n#ifdef ENABLE_NOAA\r\n            case MENU_NOAA_S:\r\n                gSubMenuSelection = gEeprom.NOAA_AUTO_SCAN;\r\n                break;\r\n#endif\r\n\r\n        case MENU_DEL_CH:\r\n#if 0\r\n            gSubMenuSelection = RADIO_FindNextChannel(gEeprom.MrChannel[0], 1, false, 1);\r\n#else\r\n            gSubMenuSelection = RADIO_FindNextChannel(gEeprom.MrChannel[gEeprom.TX_VFO], 1, false, 1);\r\n#endif\r\n            break;\r\n\r\n//\t\tcase MENU_350TX:\r\n//\t\t\tgSubMenuSelection = gSetting_350TX;\r\n//\t\t\tbreak;\r\n\r\n        case MENU_F_LOCK:\r\n            gSubMenuSelection = gSetting_F_LOCK;\r\n            break;\r\n\r\n//\t\tcase MENU_200TX:\r\n//\t\t\tgSubMenuSelection = gSetting_200TX;\r\n//\t\t\tbreak;\r\n//\r\n//\t\tcase MENU_500TX:\r\n//\t\t\tgSubMenuSelection = gSetting_500TX;\r\n//\t\t\tbreak;\r\n//\r\n//\t\tcase MENU_350EN:\r\n//\t\t\tgSubMenuSelection = gSetting_350EN;\r\n//\t\t\tbreak;\r\n\r\n//\t\tcase MENU_SCREN:\r\n//\t\t\tgSubMenuSelection = gSetting_ScrambleEnable;\r\n//\t\t\tbreak;\r\n\r\n#ifdef ENABLE_F_CAL_MENU\r\n            case MENU_F_CALI:\r\n                gSubMenuSelection = gEeprom.BK4819_XTAL_FREQ_LOW;\r\n                break;\r\n#endif\r\n\r\n        case MENU_BATCAL:\r\n            gSubMenuSelection = gBatteryCalibration[3];\r\n            break;\r\n\r\n        case MENU_BATTYP:\r\n            gSubMenuSelection = gEeprom.BATTERY_TYPE;\r\n            break;\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n        case MENU_F1SHRT:\r\n        case MENU_F1LONG:\r\n        case MENU_F2SHRT:\r\n        case MENU_F2LONG:\r\n        case MENU_MLONG: {\r\n            uint8_t *fun[] = {\r\n                &gEeprom.KEY_1_SHORT_PRESS_ACTION,\r\n                &gEeprom.KEY_1_LONG_PRESS_ACTION,\r\n                &gEeprom.KEY_2_SHORT_PRESS_ACTION,\r\n                &gEeprom.KEY_2_LONG_PRESS_ACTION,\r\n                &gEeprom.KEY_M_LONG_PRESS_ACTION\r\n            };\r\n            uint8_t id = *fun[UI_MENU_GetCurrentMenuId() - MENU_F1SHRT];\r\n\r\n            for (int i = 0; i < gSubMenu_SIDEFUNCTIONS_size; i++) {\r\n                if (gSubMenu_SIDEFUNCTIONS[i].id == id) {\r\n                    gSubMenuSelection = i;\r\n                    break;\r\n                }\r\n            }\r\n            break;\r\n        }\r\n#endif\r\n\r\n        default:\r\n            return;\r\n    }\r\n}\r\n\r\nstatic void MENU_Key_0_to_9(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) {\r\n    uint8_t Offset;\r\n    int32_t Min;\r\n    int32_t Max;\r\n    uint16_t Value = 0;\r\n\r\n    if (bKeyHeld || !bKeyPressed)\r\n        return;\r\n\r\n    gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n    uint8_t now_menu = UI_MENU_GetCurrentMenuId();\r\n#ifdef ENABLE_MDC1200_EDIT //뷨\r\n    uint8_t end_index = now_menu == MENU_MEM_NAME ? MAX_EDIT_INDEX : 4;\r\n#else\r\n    uint8_t end_index = MAX_EDIT_INDEX;\r\n#endif\r\n    if ((now_menu == MENU_MEM_NAME //뷨\r\n#ifdef ENABLE_MDC1200\r\n#ifdef ENABLE_MDC1200_EDIT\r\n                || now_menu == MENU_MDC_ID\r\n#endif\r\n#endif\r\n        ) &&\r\n        edit_index >= 0) {    // currently editing the channel name\r\n\r\n        if (edit_index < end_index) {\r\n            if (Key <= KEY_9) {\r\n                {\r\n#ifdef ENABLE_PINYIN\r\n\r\n#ifdef ENABLE_MDC1200\r\n#ifdef ENABLE_MDC1200_EDIT\r\n                    if (now_menu == MENU_MEM_NAME) {\r\n#endif\r\n#endif\r\n                        if (INPUT_MODE == 0) {\r\n                            //ƴ\r\n                            if (Key >= 2 && PINYIN_CODE_INDEX && INPUT_STAGE <= 1) {\r\n                                uint32_t tmp = PINYIN_CODE;\r\n                                PINYIN_CODE += Key * PINYIN_CODE_INDEX;\r\n                                PINYIN_CODE_INDEX /= 10;\r\n                                PINYIN_SOLVE(tmp);\r\n\r\n                                //                            if(end_index>100)end_index=0;\r\n                            } else if (INPUT_STAGE == 2) {\r\n                                uint8_t SHOW_NUM =\r\n                                        CHN_NOW_NUM - CHN_NOW_PAGE * 6 > 6 ? 6 : CHN_NOW_NUM - CHN_NOW_PAGE * 6;\r\n                                if (Key > 0 && Key <= SHOW_NUM) {\r\n                                    if (edit_chn[edit_index + 1] == 1)edit[edit_index + 2] = '_';\r\n                                    EEPROM_ReadBuffer(CHN_NOW_ADD + CHN_NOW_PAGE * 6 * 2 + 2 * (Key - 1), &edit[edit_index], 2);\r\n                                    edit_index += 2;\r\n                                    PINYIN_NUM_SELECT = 0;\r\n                                    PINYIN_CODE = 0;\r\n                                    PINYIN_SEARCH_MODE = 0;\r\n                                    INPUT_STAGE = 0;\r\n\r\n                                    CHN_NOW_PAGE = 0;\r\n                                    PINYIN_CODE_INDEX = 100000;\r\n\r\n                                    if (edit_index >= end_index) {    // exit edit\r\n                                        //gFlagAcceptSetting = false;\r\n                                        gAskForConfirmation = 1;\r\n                                    }\r\n                                }\r\n                            }\r\n                        } else if (INPUT_MODE == 1) {\r\n                            if (INPUT_STAGE == 0) {\r\n                                if (Key >= KEY_2) { //ѡĸ\r\n                                    INPUT_STAGE = 1;\r\n                                    INPUT_SELECT = Key;\r\n                                }\r\n                            } else {\r\n                                if (Key >= 1 && Key <= 2 *num_size[INPUT_SELECT - 2]) {//ѡĸ\r\n                                    if (edit_chn[edit_index] == 1) edit[edit_index+1] = '_';\r\n                                    if (Key > num_size[INPUT_SELECT - 2])\r\n                                        edit[edit_index] = num_excel[INPUT_SELECT - 2][Key - 1 - num_size[INPUT_SELECT - 2]] - 32;\r\n                                    else\r\n                                        edit[edit_index] = num_excel[INPUT_SELECT - 2][Key - 1];\r\n                                    if (++edit_index >= end_index) {    // exit edit\r\n                                        //gFlagAcceptSetting = false;\r\n                                        gAskForConfirmation = 1;\r\n                                    }\r\n                                    INPUT_STAGE = 0;\r\n                                }\r\n                            }\r\n                        } else if (INPUT_MODE == 2) {\r\n                            if (edit_chn[edit_index])edit[edit_index + 1] = '_';\r\n                            edit[edit_index] = '0' + Key;\r\n                            if (++edit_index >= end_index) {    // exit edit\r\n                                //gFlagAcceptSetting = false;\r\n                                gAskForConfirmation = 1;\r\n                            }\r\n                        }\r\n#ifdef ENABLE_MDC1200\r\n#ifdef ENABLE_MDC1200_EDIT\r\n                    } else {\r\n                        edit[edit_index] = '0' + Key ;\r\n                        if (++edit_index >= end_index) {    // exit edit\r\n                            //gFlagAcceptSetting = false;\r\n                            gAskForConfirmation = 1;\r\n                        }\r\n                    }\r\n#endif\r\n#endif\r\n\r\n#else\r\n                    edit[edit_index] = '0' + Key ;\r\n                    if (++edit_index >= end_index) {    // exit edit\r\n                        //gFlagAcceptSetting = false;\r\n                        gAskForConfirmation = 1;\r\n                    }\r\n#endif\r\n                }\r\n\r\n                gRequestDisplayScreen = DISPLAY_MENU;\r\n            }\r\n        }\r\n\r\n        return;\r\n    }\r\n\r\n    INPUTBOX_Append(Key);\r\n\r\n    gRequestDisplayScreen = DISPLAY_MENU;\r\n\r\n    if (!gIsInSubMenu) {\r\n        switch (gInputBoxIndex) {\r\n            case 2:\r\n                gInputBoxIndex = 0;\r\n\r\n                Value = (gInputBox[0] * 10) + gInputBox[1];\r\n\r\n                if (Value > 0 && Value <= gMenuListCount) {\r\n                    gMenuCursor = Value - 1;\r\n#ifndef ENABLE_MDC1200\r\n                    if (gMenuCursor + 1 >= 26)gMenuCursor++;\r\n\r\n#endif\r\n                    gFlagRefreshSetting = true;\r\n                    return;\r\n                }\r\n\r\n                if (Value <= gMenuListCount)\r\n                    break;\r\n\r\n                gInputBox[0] = gInputBox[1];\r\n                gInputBoxIndex = 1;\r\n                [[fallthrough]];\r\n            case 1:\r\n                Value = gInputBox[0];\r\n                if (Value > 0 && Value <= gMenuListCount) {\r\n                    gMenuCursor = Value - 1;\r\n#ifndef ENABLE_MDC1200\r\n                    if (gMenuCursor + 1 >= 26)gMenuCursor++;\r\n\r\n#endif\r\n                    gFlagRefreshSetting = true;\r\n                    return;\r\n                }\r\n                break;\r\n        }\r\n\r\n        gInputBoxIndex = 0;\r\n\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n        return;\r\n    }\r\n\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_OFFSET) {\r\n        uint32_t Frequency;\r\n\r\n        if (gInputBoxIndex < 6) {    // invalid frequency\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n            return;\r\n        }\r\n\r\n#ifdef ENABLE_VOICE\r\n        gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n\r\n        Frequency = StrToUL(INPUTBOX_GetAscii()) * 100;\r\n        gSubMenuSelection = FREQUENCY_RoundToStep(Frequency, gTxVfo->StepFrequency);\r\n\r\n        gInputBoxIndex = 0;\r\n        return;\r\n    }\r\n\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_MEM_CH ||\r\n        UI_MENU_GetCurrentMenuId() == MENU_DEL_CH ||\r\n        UI_MENU_GetCurrentMenuId() == MENU_1_CALL ||\r\n        UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME) {    // enter 3-digit channel number\r\n\r\n        if (gInputBoxIndex < 3) {\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID   = (VOICE_ID_t)Key;\r\n#endif\r\n            gRequestDisplayScreen = DISPLAY_MENU;\r\n            return;\r\n        }\r\n\r\n        gInputBoxIndex = 0;\r\n\r\n        Value = ((gInputBox[0] * 100) + (gInputBox[1] * 10) + gInputBox[2]) - 1;\r\n\r\n        if (IS_MR_CHANNEL(Value)) {\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n            gSubMenuSelection = Value;\r\n            return;\r\n        }\r\n\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n        return;\r\n    }\r\n\r\n    if (MENU_GetLimits(UI_MENU_GetCurrentMenuId(), &Min, &Max)) {\r\n        gInputBoxIndex = 0;\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n        return;\r\n    }\r\n\r\n    Offset = (Max >= 100) ? 3 : (Max >= 10) ? 2 : 1;\r\n\r\n    switch (gInputBoxIndex) {\r\n        case 1:\r\n            Value = gInputBox[0];\r\n            break;\r\n        case 2:\r\n            Value = (gInputBox[0] * 10) + gInputBox[1];\r\n            break;\r\n        case 3:\r\n            Value = (gInputBox[0] * 100) + (gInputBox[1] * 10) + gInputBox[2];\r\n            break;\r\n    }\r\n\r\n    if (Offset == gInputBoxIndex)\r\n        gInputBoxIndex = 0;\r\n\r\n    if (Value <= Max) {\r\n        gSubMenuSelection = Value;\r\n        return;\r\n    }\r\n\r\n    gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n}\r\n\r\nstatic void MENU_Key_EXIT(bool bKeyPressed, bool bKeyHeld) {\r\n    if (bKeyHeld || !bKeyPressed)\r\n        return;\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME && gIsInSubMenu == true && edit_index >= 0&&gAskForConfirmation == 0) {\r\n#ifdef ENABLE_PINYIN\r\n        if (INPUT_MODE == 0) {\r\n\r\n            if (INPUT_STAGE == 1 && PINYIN_CODE > 0) {\r\n\r\n                if (PINYIN_CODE_INDEX != 0) {\r\n                    PINYIN_CODE = PINYIN_CODE / (PINYIN_CODE_INDEX * 100) * (PINYIN_CODE_INDEX * 100);\r\n                    PINYIN_CODE_INDEX *= 10;\r\n                } else {\r\n                    PINYIN_CODE = PINYIN_CODE - PINYIN_CODE % 10;\r\n                    PINYIN_CODE_INDEX = 1;\r\n                }\r\n\r\n                uint32_t tmp = PINYIN_CODE;\r\n                PINYIN_SEARCH_MODE=0;\r\n                PINYIN_NUM_SELECT = 0;\r\n                PINYIN_SOLVE(tmp);\r\n\r\n                if (PINYIN_CODE == 0) {\r\n                    INPUT_STAGE = 0;\r\n                }\r\n\r\n            } else if (INPUT_STAGE == 2) {\r\n\r\n                INPUT_STAGE = 1;\r\n\r\n            } else edit_index = -1;\r\n\r\n        } else if (INPUT_MODE == 1) {\r\n            if (INPUT_STAGE == 1)INPUT_STAGE = 0;\r\n            else  edit_index = -1;\r\n        } else\r\n\r\n\r\n#endif\r\n            edit_index = -1;\r\n        return;\r\n    }\r\n#ifdef  ENABLE_PINYIN\r\n\r\n//    if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME && gAskForConfirmation == 0) { //뷨exit\r\n//\r\n//\r\n//    }\r\n\r\n#endif\r\n    gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n\r\n    if (!gCssBackgroundScan) {\r\n        /* Backlight related menus set full brightness. Set it back to the configured value,\r\n\t\t   just in case we are exiting from one of them. */\r\n        BACKLIGHT_TurnOn();\r\n        if (gIsInSubMenu) {\r\n            if (gInputBoxIndex == 0 || UI_MENU_GetCurrentMenuId() != MENU_OFFSET) {\r\n                gAskForConfirmation = 0;\r\n                gIsInSubMenu = false;\r\n                gInputBoxIndex = 0;\r\n                gFlagRefreshSetting = true;\r\n\r\n#ifdef ENABLE_VOICE\r\n                gAnotherVoiceID = VOICE_ID_CANCEL;\r\n#endif\r\n            } else\r\n                gInputBox[--gInputBoxIndex] = 10;\r\n\r\n            // ***********************\r\n\r\n            gRequestDisplayScreen = DISPLAY_MENU;\r\n            return;\r\n        }\r\n\r\n#ifdef ENABLE_VOICE\r\n        gAnotherVoiceID = VOICE_ID_CANCEL;\r\n#endif\r\n\r\n        gRequestDisplayScreen = DISPLAY_MAIN;\r\n\r\n        if (gEeprom.BACKLIGHT_TIME == 0) // backlight set to always off\r\n        {\r\n            BACKLIGHT_TurnOff();    // turn the backlight OFF\r\n        }\r\n    } else {\r\n        MENU_StopCssScan();\r\n\r\n#ifdef ENABLE_VOICE\r\n        gAnotherVoiceID   = VOICE_ID_SCANNING_STOP;\r\n#endif\r\n\r\n        gRequestDisplayScreen = DISPLAY_MENU;\r\n    }\r\n\r\n    gPttWasReleased = true;\r\n}\r\n#ifdef ENABLE_PINYIN\r\nvoid UPDATE_CHN()\r\n{\r\n    uint8_t tmp[5];\r\n\r\n    EEPROM_ReadBuffer(PINYIN_NOW_INDEX * 128 + 0X20000 + 16 + PINYIN_NUM_SELECT * 16 + 6, tmp, 5);\r\n    CHN_NOW_ADD = tmp[1] | tmp[2] << 8 | tmp[3] << 16 | tmp[4] << 24;\r\n    CHN_NOW_NUM = tmp[0];\r\n    CHN_NOW_PAGE = 0;\r\n}\r\n#endif\r\nstatic void MENU_Key_MENU(const bool bKeyPressed, const bool bKeyHeld) {\r\n    if (bKeyHeld || !bKeyPressed)\r\n        return;\r\n    gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n    gRequestDisplayScreen = DISPLAY_MENU;\r\n#ifdef ENABLE_PINYIN\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME) {\r\n        if (edit_index == -1) {\r\n            //뷨ʼmenu\r\n            INPUT_MODE = 0;\r\n            INPUT_SELECT = 0;\r\n            INPUT_STAGE = 0;\r\n            INPUT_MODE_LAST = 0;\r\n            PINYIN_CODE = 0;\r\n            PINYIN_CODE_INDEX = 100000;\r\n        }\r\n        if (gIsInSubMenu) {\r\n            if (INPUT_MODE == 0) {\r\n                if (PINYIN_CODE && PINYIN_SEARCH_MODE == 0)return;\r\n                if (PINYIN_SEARCH_MODE == 1) {\r\n                    if (INPUT_STAGE == 1) {\r\n                        PINYIN_NUM_SELECT = 0;\r\n                        INPUT_STAGE = 2;\r\n                        UPDATE_CHN();\r\n                        return;\r\n                    } else if (INPUT_STAGE == 2) {\r\n                        if (PINYIN_NUM_SELECT < PINYIN_SEARCH_NUM - 1)PINYIN_NUM_SELECT++;\r\n                        else PINYIN_NUM_SELECT = 0;\r\n                        UPDATE_CHN();\r\n                        return;\r\n                    }\r\n                }\r\n            } else if (INPUT_MODE == 3) {\r\n                INPUT_MODE = INPUT_MODE_LAST;\r\n            }\r\n        }\r\n    }\r\n\r\n#endif\r\n    if (!gIsInSubMenu) {\r\n#ifdef ENABLE_VOICE\r\n        if (UI_MENU_GetCurrentMenuId() != MENU_SCR)\r\n            gAnotherVoiceID = MenuList[gMenuCursor].voice_id;\r\n#endif\r\n        if (UI_MENU_GetCurrentMenuId() == MENU_DEL_CH || UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME)\r\n//            if (!RADIO_CheckValidChannel(gSubMenuSelection, false, 0))\r\n//                return;  // invalid channel\r\n        {\r\n            uint8_t before=gSubMenuSelection;\r\n            while(!RADIO_CheckValidChannel(gSubMenuSelection, false, 0))\r\n            {\r\n                gSubMenuSelection++;\r\n                if (gSubMenuSelection==before)\r\n                    return;  // invalid channel\r\n                    else if(gSubMenuSelection==MR_CHANNEL_LAST)gSubMenuSelection=0;\r\n            }\r\n        }\r\n\r\n        if (UI_MENU_GetCurrentMenuId() == MENU_UPCODE\r\n            || UI_MENU_GetCurrentMenuId() == MENU_DWCODE\r\n            #ifdef ENABLE_DTMF_CALLING\r\n            || UI_MENU_GetCurrentMenuId() == MENU_ANI_ID\r\n            #endif\r\n            #ifndef ENABLE_MDC1200_EDIT\r\n            || UI_MENU_GetCurrentMenuId() == MENU_MDC_ID\r\n#endif\r\n                )\r\n            return;  // invalid\r\n        gAskForConfirmation = 0;\r\n        gIsInSubMenu = true;\r\n\r\n//\t\tif (UI_MENU_GetCurrentMenuId() != MENU_D_LIST)\r\n        {\r\n            gInputBoxIndex = 0;\r\n            edit_index = -1;\r\n\r\n        }\r\n#ifdef ENABLE_MDC1200\r\n#ifdef ENABLE_MDC1200_EDIT\r\n        if (UI_MENU_GetCurrentMenuId() == MENU_MDC_ID) {\r\n            edit_index = 0;\r\n            memmove(edit_original, edit, sizeof(edit_original));\r\n        }\r\n#endif\r\n#endif\r\n        return;\r\n    }\r\n#ifdef ENABLE_MDC1200\r\n#ifdef ENABLE_MDC1200_EDIT\r\n\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_MDC_ID && edit_index < 4) {    // editing the channel name characters\r\n\r\n        if (++edit_index < 4)\r\n            return;\r\n\r\n        // exit\r\n        if (memcmp(edit_original, edit, sizeof(edit_original)) == 0) {    // no change - drop it\r\n            gIsInSubMenu = false;\r\n        }\r\n        //gFlagAcceptSetting = false;\r\n        gAskForConfirmation = 0;\r\n\r\n    }\r\n#endif\r\n\r\n#endif\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME) { //뷨MENU\r\n        if (edit_index < 0) {    // enter channel name edit mode\r\n            if (!RADIO_CheckValidChannel(gSubMenuSelection, false, 0))\r\n                return;\r\n\r\n            SETTINGS_FetchChannelName(edit, gSubMenuSelection);\r\n            // pad the channel name out with '_'\r\n            edit_index = strlen(edit);\r\n            while (edit_index < MAX_EDIT_INDEX)edit[edit_index++] = '_';\r\n            edit[edit_index] = 0;\r\n            edit_index = 0;  // 'edit_index' is going to be used as the cursor position\r\n\r\n            memcpy(edit_original, edit, sizeof(edit_original));\r\n            return;\r\n        } else if (edit_index >= 0 && edit_index < MAX_EDIT_INDEX) {    // editing the channel name characters\r\n\r\n#ifdef ENABLE_PINYIN\r\n            if (edit_chn[edit_index] == 1)\r\n                    edit_index++;\r\n#endif\r\n            edit_index++;\r\n#ifdef ENABLE_PINYIN\r\n            if (INPUT_MODE == 3)INPUT_MODE = INPUT_MODE_LAST;\r\n#endif\r\n            if (edit_index < MAX_EDIT_INDEX) {\r\n#ifdef ENABLE_PINYIN\r\n                if (INPUT_MODE == 0 && edit_index + 1 >= MAX_EDIT_INDEX)\r\n                    INPUT_MODE = 1;\r\n#endif\r\n\r\n                return;\r\n            }\r\n            // exit\r\n            if (memcmp(edit_original, edit, sizeof(edit_original)) == 0) {    // no change - drop it\r\n                gIsInSubMenu = false;\r\n            }\r\n            //gFlagAcceptSetting = false;\r\n            gAskForConfirmation = 0;\r\n        }\r\n    }\r\n#ifdef ENABLE_PINYIN //˳ģʽ\r\n\r\n//    PINYIN_MODE=0;\r\n#endif\r\n    // exiting the sub menu\r\n\r\n    if (gIsInSubMenu) {\r\n        if (UI_MENU_GetCurrentMenuId() == MENU_RESET ||\r\n            UI_MENU_GetCurrentMenuId() == MENU_MEM_CH ||\r\n            UI_MENU_GetCurrentMenuId() == MENU_DEL_CH ||\r\n            UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME\r\n#ifdef ENABLE_MDC1200\r\n#ifdef ENABLE_MDC1200_EDIT\r\n\r\n            ||\r\nUI_MENU_GetCurrentMenuId() == MENU_MDC_ID\r\n#endif\r\n#endif\r\n\r\n                ) {\r\n            switch (gAskForConfirmation) {\r\n                case 0:\r\n                    gAskForConfirmation = 1;\r\n                    break;\r\n\r\n                case 1:\r\n                    gAskForConfirmation = 2;\r\n\r\n                    UI_DisplayMenu();\r\n\r\n                    if (UI_MENU_GetCurrentMenuId() == MENU_RESET) {\r\n#ifdef ENABLE_VOICE\r\n                        AUDIO_SetVoiceID(0, VOICE_ID_CONFIRM);\r\n                        AUDIO_PlaySingleVoice(true);\r\n#endif\r\n\r\n                        MENU_AcceptSetting();\r\n\r\n#if defined(ENABLE_OVERLAY)\r\n                        overlay_FLASH_RebootToBootloader();\r\n#else\r\n                        NVIC_SystemReset();\r\n#endif\r\n                    }\r\n\r\n                    gFlagAcceptSetting = true;\r\n                    gIsInSubMenu = false;\r\n                    gAskForConfirmation = 0;\r\n            }\r\n        } else {\r\n            gFlagAcceptSetting = true;\r\n            gIsInSubMenu = false;\r\n        }\r\n    }\r\n    SCANNER_Stop();\r\n\r\n#ifdef ENABLE_VOICE\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_SCR)\r\n        gAnotherVoiceID = (gSubMenuSelection == 0) ? VOICE_ID_SCRAMBLER_OFF : VOICE_ID_SCRAMBLER_ON;\r\n    else\r\n        gAnotherVoiceID = VOICE_ID_CONFIRM;\r\n#endif\r\n\r\n    gInputBoxIndex = 0;\r\n}\r\n\r\nstatic void MENU_Key_STAR(const bool bKeyPressed, const bool bKeyHeld) {\r\n    if (bKeyHeld || !bKeyPressed)\r\n        return;\r\n\r\n    gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n//뷨ģʽл\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME && edit_index >= 0) {    // currently editing the channel name\r\n\r\n        if (edit_index < MAX_EDIT_INDEX) {\r\n#ifndef ENABLE_PINYIN\r\n            edit[edit_index] = '-';\r\n            if (++edit_index >= MAX_EDIT_INDEX) {    // exit edit\r\n                //gFlagAcceptSetting = false;\r\n                gAskForConfirmation = 1;\r\n            }\r\n\r\n#else //뷨ģʽл\r\n            INPUT_MODE++;\r\n            if (INPUT_MODE >= 3)INPUT_MODE = 0;\r\n            if (INPUT_MODE == 0 && edit_index + 1 >= MAX_EDIT_INDEX)\r\n                INPUT_MODE = 1;\r\n            if (INPUT_MODE == 0) {\r\n                PINYIN_CODE = 0;\r\n                PINYIN_CODE_INDEX = 100000;\r\n            }\r\n            INPUT_STAGE = 0;\r\n#endif\r\n\r\n            gRequestDisplayScreen = DISPLAY_MENU;\r\n        }\r\n\r\n        return;\r\n    }\r\n\r\n    RADIO_SelectVfos();\r\n\r\n#ifdef ENABLE_NOAA\r\n    if (!IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE) && gRxVfo->Modulation == MODULATION_FM)\r\n#else\r\n    if (gRxVfo->Modulation == MODULATION_FM)\r\n#endif\r\n    {\r\n        if ((UI_MENU_GetCurrentMenuId() == MENU_R_CTCS || UI_MENU_GetCurrentMenuId() == MENU_R_DCS) &&\r\n            gIsInSubMenu) {    // scan CTCSS or DCS to find the tone/code of the incoming signal\r\n            if (!SCANNER_IsScanning())\r\n                MENU_StartCssScan();\r\n            else\r\n                MENU_StopCssScan();\r\n        }\r\n\r\n        gPttWasReleased = true;\r\n        return;\r\n    }\r\n\r\n    gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n}\r\n\r\nstatic void MENU_Key_UP_DOWN(bool bKeyPressed, bool bKeyHeld, int8_t Direction) {\r\n    uint8_t VFO;\r\n    uint8_t Channel;\r\n    bool bCheckScanList;\r\n    if (gIsInSubMenu && edit_index >= 0) { //뷨UP DOWN\r\n        if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME) {    // change the character\r\n\r\n            if (bKeyPressed && edit_index < MAX_EDIT_INDEX) {\r\n#ifdef  ENABLE_PINYIN//ƴ\r\n\r\n                if (INPUT_MODE == 0) {\r\n                    if (INPUT_STAGE == 2) {\r\n                        if (PINYIN_SEARCH_MODE == 1)//׼ȷ\r\n                        {\r\n                            if (Direction == 1) {\r\n                                if (CHN_NOW_PAGE) CHN_NOW_PAGE--;\r\n                            } else if (Direction == -1) {\r\n                                if ((CHN_NOW_PAGE + 1) * 6 < CHN_NOW_NUM)CHN_NOW_PAGE++;\r\n\r\n                            }\r\n                            return;\r\n                        }\r\n                    }\r\n                }\r\n\r\n                if (((INPUT_MODE == 0 || INPUT_MODE == 1) && INPUT_STAGE == 0) || INPUT_MODE == 2 || INPUT_MODE == 3) {\r\n                    INPUT_MODE_LAST = INPUT_MODE;\r\n                    INPUT_MODE = 3;\r\n\r\n                    if (edit_chn[edit_index]) {\r\n                        edit[edit_index + 1] = '_';\r\n                        edit[edit_index] = '_';\r\n\r\n                    }\r\n                    char c = edit[edit_index] + Direction;\r\n                    while (c >= 32 && c <= 126) {\r\n                        if ((c >= 'A' && c <= 'Z') || (c >= 'a' && c <= 'z' )||\r\n                           ( c >= '0' && c <= '9')) {    // choose next character\r\n                            c += Direction;\r\n                        } else break;\r\n                    }\r\n                    edit[edit_index] = ((uint8_t) c < 32) ? 126 : ((uint8_t) c > 126) ? 32 : c;\r\n                }\r\n\r\n\r\n#else\r\n                if (isChineseChar(edit[edit_index], edit_index, MAX_EDIT_INDEX)) {\r\n                    edit[edit_index + 1] = '_';\r\n                    edit[edit_index] = '_';\r\n\r\n                }\r\n                const char unwanted[] = \"$%&!\\\"':;?^`|{}\";\r\n                char c = edit[edit_index] + Direction;\r\n                unsigned int i = 0;\r\n                while (i < sizeof(unwanted) && c >= 32 && c <= 126) {\r\n                    if (c == unwanted[i++]) {    // choose next character\r\n                        c += Direction;\r\n                        i = 0;\r\n                    }\r\n                }\r\n                edit[edit_index] = ((uint8_t) c < 32) ? 126 : ((uint8_t) c > 126) ? 32 : c;\r\n#endif\r\n                gRequestDisplayScreen = DISPLAY_MENU;\r\n            }\r\n            return;\r\n        }\r\n#ifdef ENABLE_MDC1200\r\n#ifdef ENABLE_MDC1200_EDIT\r\n        if (UI_MENU_GetCurrentMenuId() == MENU_MDC_ID) {\r\n            if (bKeyPressed && edit_index < 4) {\r\n                char c = edit[edit_index] + Direction;\r\n                if (c < '0')c = 'F';\r\n                else if (c > 'F')c = '0';\r\n                else if (c > '9' && c < 'A') {\r\n                    if (Direction == 1)c = 'A';\r\n                    else c = '9';\r\n                }\r\n\r\n                edit[edit_index] = c;\r\n\r\n                gRequestDisplayScreen = DISPLAY_MENU;\r\n            }\r\n            return;\r\n        }\r\n#endif\r\n#endif\r\n\r\n    }\r\n    if (!bKeyHeld) {\r\n        if (!bKeyPressed)\r\n            return;\r\n\r\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n\r\n        gInputBoxIndex = 0;\r\n    } else if (!bKeyPressed)\r\n        return;\r\n\r\n    if (SCANNER_IsScanning()) {\r\n        return;\r\n    }\r\n\r\n    if (!gIsInSubMenu) {\r\n#ifndef ENABLE_MDC1200\r\n        uint8_t last_num = gMenuCursor;\r\n#endif\r\n        gMenuCursor = NUMBER_AddWithWraparound(gMenuCursor, key_dir * Direction, 0, gMenuListCount - 1);\r\n#ifndef ENABLE_MDC1200\r\n        if (last_num + 1 < 26 && gMenuCursor + 1 == 26)gMenuCursor++;\r\n        else if (last_num + 1 == 27 && gMenuCursor + 1 == 26)gMenuCursor--;\r\n#endif\r\n        gFlagRefreshSetting = true;\r\n\r\n        gRequestDisplayScreen = DISPLAY_MENU;\r\n\r\n        if (UI_MENU_GetCurrentMenuId() != MENU_ABR\r\n            && UI_MENU_GetCurrentMenuId() != MENU_ABR_MAX\r\n            && gEeprom.BACKLIGHT_TIME == 0) // backlight always off and not in the backlight menu\r\n        {\r\n            BACKLIGHT_TurnOff();\r\n        }\r\n\r\n        return;\r\n    }\r\n\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_OFFSET) {\r\n        int32_t Offset = (Direction * gTxVfo->StepFrequency) + gSubMenuSelection;\r\n        if (Offset < 99999990) {\r\n            if (Offset < 0)\r\n                Offset = 99999990;\r\n        } else\r\n            Offset = 0;\r\n\r\n        gSubMenuSelection = FREQUENCY_RoundToStep(Offset, gTxVfo->StepFrequency);\r\n        gRequestDisplayScreen = DISPLAY_MENU;\r\n        return;\r\n    }\r\n\r\n    VFO = 0;\r\n\r\n    switch (UI_MENU_GetCurrentMenuId()) {\r\n        case MENU_DEL_CH:\r\n        case MENU_1_CALL:\r\n        case MENU_MEM_NAME:\r\n            bCheckScanList = false;\r\n            break;\r\n\r\n        case MENU_SLIST2:\r\n            VFO = 1;\r\n            [[fallthrough]];\r\n        case MENU_SLIST1:\r\n            bCheckScanList = true;\r\n            break;\r\n\r\n        default:\r\n            MENU_ClampSelection(Direction);\r\n            gRequestDisplayScreen = DISPLAY_MENU;\r\n            return;\r\n    }\r\n\r\n    Channel = RADIO_FindNextChannel(gSubMenuSelection + Direction, Direction, bCheckScanList, VFO);\r\n    if (Channel != 0xFF)\r\n        gSubMenuSelection = Channel;\r\n\r\n    gRequestDisplayScreen = DISPLAY_MENU;\r\n}\r\n\r\nvoid MENU_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) {\r\n    switch (Key) {\r\n        case KEY_0:\r\n        case KEY_1:\r\n        case KEY_2:\r\n        case KEY_3:\r\n        case KEY_4:\r\n        case KEY_5:\r\n        case KEY_6:\r\n        case KEY_7:\r\n        case KEY_8:\r\n        case KEY_9:\r\n            MENU_Key_0_to_9(Key, bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_MENU:\r\n            MENU_Key_MENU(bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_UP:\r\n            MENU_Key_UP_DOWN(bKeyPressed, bKeyHeld, 1);\r\n            break;\r\n        case KEY_DOWN:\r\n            MENU_Key_UP_DOWN(bKeyPressed, bKeyHeld, -1);\r\n            break;\r\n        case KEY_EXIT:\r\n            MENU_Key_EXIT(bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_STAR:\r\n            MENU_Key_STAR(bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_F:\r\n            if (UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME && //뷨\r\n                edit_index >= 0) {    // currently editing the channel name\r\n                if (!bKeyHeld && bKeyPressed) {\r\n                    gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n#ifdef ENABLE_PINYIN\r\n\r\n                    bool flag_space = true;\r\n                    if ((INPUT_MODE == 0 && INPUT_STAGE > 0 )|| (INPUT_MODE == 1 && INPUT_STAGE > 0))flag_space = false;\r\n#endif\r\n\r\n\r\n                    if (edit_index < MAX_EDIT_INDEX\r\n                        #ifdef ENABLE_PINYIN\r\n                        && flag_space\r\n#endif\r\n\r\n\r\n                            ) {\r\n\r\n#ifdef ENABLE_PINYIN\r\n                        if (edit_chn[edit_index]) {\r\n                            edit[edit_index + 1] = '_';\r\n\r\n                        }\r\n#endif\r\n\r\n                        edit[edit_index] = ' ';\r\n\r\n\r\n                        if (++edit_index >= MAX_EDIT_INDEX) {    // exit edit\r\n                            //gFlagAcceptSetting = false;\r\n                            gAskForConfirmation = 1;\r\n                        }\r\n\r\n\r\n                        gRequestDisplayScreen = DISPLAY_MENU;\r\n                    }\r\n                }\r\n                break;\r\n            }\r\n\r\n            GENERIC_Key_F(bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_PTT:\r\n            GENERIC_Key_PTT(bKeyPressed);\r\n            break;\r\n        default:\r\n            if (!bKeyHeld && bKeyPressed)\r\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n            break;\r\n    }\r\n\r\n    if (gScreenToDisplay == DISPLAY_MENU) {\r\n        if (/*UI_MENU_GetCurrentMenuId() == MENU_VOL||*/\r\n#ifdef ENABLE_F_CAL_MENU\r\nUI_MENU_GetCurrentMenuId() == MENU_F_CALI||\r\n#endif\r\nUI_MENU_GetCurrentMenuId() == MENU_BATCAL\r\n                ) {\r\n            gMenuCountdown = menu_timeout_long_500ms;\r\n        } else {\r\n            gMenuCountdown = menu_timeout_500ms;\r\n        }\r\n    }\r\n\r\n}\r\n"
  },
  {
    "path": "app/menu.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef APP_MENU_H\r\n#define APP_MENU_H\r\n\r\n#include \"driver/keyboard.h\"\r\n\r\n#ifdef ENABLE_F_CAL_MENU\r\nvoid writeXtalFreqCal(const int32_t value, const bool update_eeprom);\r\n#endif\r\n\r\n//extern uint8_t gUnlockAllTxConfCnt;\r\n\r\nint MENU_GetLimits(uint8_t menu_id, int32_t *pMin, int32_t *pMax);\r\n\r\nvoid MENU_AcceptSetting(void);\r\n\r\nvoid MENU_ShowCurrentSetting(void);\r\n\r\nvoid MENU_StartCssScan(void);\r\n\r\nvoid MENU_CssScanFound(void);\r\n\r\nvoid MENU_StopCssScan(void);\r\n\r\nvoid MENU_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld);\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "app/messenger.c",
    "content": "#include \"app/mdc1200.h\"\n#include <string.h>\n#include \"driver/keyboard.h\"\n#include \"driver/st7565.h\"\n#include \"driver/bk4819.h\"\n#include \"external/printf/printf.h\"\n#include \"misc.h\"\n#include \"settings.h\"\n#include \"radio.h\"\n#include \"app.h\"\n#include \"audio.h\"\n#include \"functions.h\"\n#include \"frequencies.h\"\n#include \"driver/system.h\"\n#include \"app/messenger.h\"\n#include \"ui/ui.h\"\n#include \"driver/uart.h\"\n#include \"stdbool.h\"\n\n#if defined(ENABLE_UART)\n#include \"driver/uart.h\"\n#endif\n#ifdef ENABLE_MESSENGER\nbool stop_mdc_flag=0;\n\n\n\n//bool stop_mdc_rx=0;\nconst uint8_t MSG_BUTTON_STATE_HELD = 1 << 1;\n\nconst uint8_t MSG_BUTTON_EVENT_SHORT =  0;\nconst uint8_t MSG_BUTTON_EVENT_LONG =  MSG_BUTTON_STATE_HELD;\n\nconst uint8_t MAX_MSG_LENGTH = TX_MSG_LENGTH - 1;\n\nconst uint16_t TONE2_FREQ = 0x3065; // 0x2854\n\n#define NEXT_CHAR_DELAY 100 // 10ms tick\n\nchar T9TableLow[9][4] = { {',', '.', '?', '!'}, {'a', 'b', 'c', '\\0'}, {'d', 'e', 'f', '\\0'}, {'g', 'h', 'i', '\\0'}, {'j', 'k', 'l', '\\0'}, {'m', 'n', 'o', '\\0'}, {'p', 'q', 'r', 's'}, {'t', 'u', 'v', '\\0'}, {'w', 'x', 'y', 'z'} };\nchar T9TableUp[9][4] = { {',', '.', '?', '!'}, {'A', 'B', 'C', '\\0'}, {'D', 'E', 'F', '\\0'}, {'G', 'H', 'I', '\\0'}, {'J', 'K', 'L', '\\0'}, {'M', 'N', 'O', '\\0'}, {'P', 'Q', 'R', 'S'}, {'T', 'U', 'V', '\\0'}, {'W', 'X', 'Y', 'Z'} };\nunsigned char numberOfLettersAssignedToKey[9] = { 4, 3, 3, 3, 3, 3, 4, 3, 4 };\n\nchar T9TableNum[9][4] = { {'1', '\\0', '\\0', '\\0'}, {'2', '\\0', '\\0', '\\0'}, {'3', '\\0', '\\0', '\\0'}, {'4', '\\0', '\\0', '\\0'}, {'5', '\\0', '\\0', '\\0'}, {'6', '\\0', '\\0', '\\0'}, {'7', '\\0', '\\0', '\\0'}, {'8', '\\0', '\\0', '\\0'}, {'9', '\\0', '\\0', '\\0'} };\nunsigned char numberOfNumsAssignedToKey[9] = { 1, 1, 1, 1, 1, 1, 1, 1, 1 };\n\nchar cMessage[TX_MSG_LENGTH];\nchar lastcMessage[TX_MSG_LENGTH];\nchar rxMessage[4][MAX_RX_MSG_LENGTH + 2];\nunsigned char cIndex = 0;\nunsigned char prevKey = 0, prevLetter = 0;\nKeyboardType keyboardType = UPPERCASE;\n\nMsgStatus msgStatus = READY;\n\nuint8_t msgFSKBuffer[MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH];\n\nuint16_t gErrorsDuringMSG;\n\nuint8_t hasNewMessage = 0;\n\nuint8_t keyTickCounter = 0;\n\n// -----------------------------------------------------\n\nvoid MSG_FSKSendData() {\n\n    uint16_t fsk_reg59;\n\n    // REG_51\n    //\n    // <15>  TxCTCSS/CDCSS   0 = disable 1 = Enable\n    //\n    // turn off CTCSS/CDCSS during FFSK\n    const uint16_t css_val = BK4819_ReadRegister(BK4819_REG_51);\n    BK4819_WriteRegister(BK4819_REG_51, 0);\n\n    // set the FM deviation level\n    const uint16_t dev_val = BK4819_ReadRegister(BK4819_REG_40);\n    //UART_printf(\"\\n BANDWIDTH : 0x%.4X\", dev_val);\n    {\n        uint16_t deviation = 850;\n        switch (gEeprom.VfoInfo[gEeprom.TX_VFO].CHANNEL_BANDWIDTH)\n        {\n            case BK4819_FILTER_BW_WIDE:     deviation = 1050; break;\n            case BK4819_FILTER_BW_NARROW:   deviation =  850; break;\n            case BK4819_FILTER_BW_NARROWER: deviation =  750; break;\n        }\n        //BK4819_WriteRegister(0x40, (3u << 12) | (deviation & 0xfff));\n        BK4819_WriteRegister(BK4819_REG_40, (dev_val & 0xf000) | (deviation & 0xfff));\n    }\n\n    // REG_2B   0\n    //\n    // <15> 1 Enable CTCSS/CDCSS DC cancellation after FM Demodulation   1 = enable 0 = disable\n    // <14> 1 Enable AF DC cancellation after FM Demodulation            1 = enable 0 = disable\n    // <10> 0 AF RX HPF 300Hz filter     0 = enable 1 = disable\n    // <9>  0 AF RX LPF 3kHz filter      0 = enable 1 = disable\n    // <8>  0 AF RX de-emphasis filter   0 = enable 1 = disable\n    // <2>  0 AF TX HPF 300Hz filter     0 = enable 1 = disable\n    // <1>  0 AF TX LPF filter           0 = enable 1 = disable\n    // <0>  0 AF TX pre-emphasis filter  0 = enable 1 = disable\n    //\n    // disable the 300Hz HPF and FM pre-emphasis filter\n    //\n    const uint16_t filt_val = BK4819_ReadRegister(BK4819_REG_2B);\n    BK4819_WriteRegister(BK4819_REG_2B, (1u << 2) | (1u << 0));\n\n    // *******************************************\n    // setup the FFSK modem as best we can\n\n    // Uses 1200/1800 Hz FSK tone frequencies 1200 bits/s\n    //\n    BK4819_WriteRegister(BK4819_REG_58, // 0x37C3);   // 001 101 11 11 00 001 1\n        (1u << 13) |\t\t// 1 FSK TX mode selection\n                            //   0 = FSK 1.2K and FSK 2.4K TX .. no tones, direct FM\n                            //   1 = FFSK 1200/1800 TX\n                            //   2 = ???\n                            //   3 = FFSK 1200/2400 TX\n                            //   4 = ???\n                            //   5 = NOAA SAME TX\n                            //   6 = ???\n                            //   7 = ???\n                            //\n        (7u << 10) |\t\t// 0 FSK RX mode selection\n                            //   0 = FSK 1.2K, FSK 2.4K RX and NOAA SAME RX .. no tones, direct FM\n                            //   1 = ???\n                            //   2 = ???\n                            //   3 = ???\n                            //   4 = FFSK 1200/2400 RX\n                            //   5 = ???\n                            //   6 = ???\n                            //   7 = FFSK 1200/1800 RX\n                            //\n        (0u << 8) |\t\t\t// 0 FSK RX gain\n                            //   0 ~ 3\n                            //\n        (0u << 6) |\t\t\t// 0 ???\n                            //   0 ~ 3\n                            //\n        (0u << 4) |\t\t\t// 0 FSK preamble type selection\n                            //   0 = 0xAA or 0x55 due to the MSB of FSK sync byte 0\n                            //   1 = ???\n                            //   2 = 0x55\n                            //   3 = 0xAA\n                            //\n        (1u << 1) |\t\t\t// 1 FSK RX bandwidth setting\n                            //   0 = FSK 1.2K .. no tones, direct FM\n                            //   1 = FFSK 1200/1800\n                            //   2 = NOAA SAME RX\n                            //   3 = ???\n                            //   4 = FSK 2.4K and FFSK 1200/2400\n                            //   5 = ???\n                            //   6 = ???\n                            //   7 = ???\n                            //\n        (1u << 0));\t\t\t// 1 FSK enable\n                            //   0 = disable\n                            //   1 = enable\n\n    // REG_72\n    //\n    // <15:0> 0x2854 TONE-2 / FSK frequency control word\n    //        = freq(Hz) * 10.32444 for XTAL 13M / 26M or\n    //        = freq(Hz) * 10.48576 for XTAL 12.8M / 19.2M / 25.6M / 38.4M\n    //\n    // tone-2 = 1200Hz\n    // 18583,92\n    BK4819_WriteRegister(BK4819_REG_72, TONE2_FREQ);\n\n    // REG_70\n    //\n    // <15>   0 TONE-1\n    //        1 = enable\n    //        0 = disable\n    //\n    // <14:8> 0 TONE-1 tuning\n    //\n    // <7>    0 TONE-2\n    //        1 = enable\n    //        0 = disable\n    //\n    // <6:0>  0 TONE-2 / FSK tuning\n    //        0 ~ 127\n    //\n    // enable tone-2, set gain\n    //\n    BK4819_WriteRegister(BK4819_REG_70,   // 0 0000000 1 1100000\n        ( 0u << 15) |    // 0\n        ( 0u <<  8) |    // 0\n        ( 1u <<  7) |    // 1\n        (96u <<  0));    // 96\n\n    // REG_59\n    //\n    // <15>  0 TX FIFO             1 = clear\n    // <14>  0 RX FIFO             1 = clear\n    // <13>  0 FSK Scramble        1 = Enable\n    // <12>  0 FSK RX              1 = Enable\n    // <11>  0 FSK TX              1 = Enable\n    // <10>  0 FSK data when RX    1 = Invert\n    // <9>   0 FSK data when TX    1 = Invert\n    // <8>   0 ???\n    //\n    // <7:4> 0 FSK preamble length selection\n    //       0  =  1 byte\n    //       1  =  2 bytes\n    //       2  =  3 bytes\n    //       15 = 16 bytes\n    //\n    // <3>   0 FSK sync length selection\n    //       0 = 2 bytes (FSK Sync Byte 0, 1)\n    //       1 = 4 bytes (FSK Sync Byte 0, 1, 2, 3)\n    //\n    // <2:0> 0 ???\n    //\n    fsk_reg59 = (0u << 15) |   // 0/1     1 = clear TX FIFO\n                (0u << 14) |   // 0/1     1 = clear RX FIFO\n                (0u << 13) |   // 0/1     1 = scramble\n                (0u << 12) |   // 0/1     1 = enable RX\n                (0u << 11) |   // 0/1     1 = enable TX\n                (0u << 10) |   // 0/1     1 = invert data when RX\n                (0u <<  9) |   // 0/1     1 = invert data when TX\n                (0u <<  8) |   // 0/1     ???\n                (15u <<  4) |   // 0 ~ 15  preamble length .. bit toggling\n                (1u <<  3) |   // 0/1     sync length\n                (0u <<  0);    // 0 ~ 7   ???\n\n    // Set packet length (not including pre-amble and sync bytes that we can't seem to disable)\n    BK4819_WriteRegister(BK4819_REG_5D, ((MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH) << 8));\n\n    // REG_5A\n    //\n    // <15:8> 0x55 FSK Sync Byte 0 (Sync Byte 0 first, then 1,2,3)\n    // <7:0>  0x55 FSK Sync Byte 1\n    //\n    BK4819_WriteRegister(BK4819_REG_5A, 0x7240);                   // bytes 1 & 2\n\n    // REG_5B\n    //\n    // <15:8> 0x55 FSK Sync Byte 2 (Sync Byte 0 first, then 1,2,3)\n    // <7:0>  0xAA FSK Sync Byte 3\n    //\n    BK4819_WriteRegister(BK4819_REG_5B, 0x99a7);                   // bytes 2 & 3\n\n    // CRC setting (plus other stuff we don't know what)\n    //\n    // REG_5C\n    //\n    // <15:7> ???\n    //\n    // <6>    1 CRC option enable    0 = disable  1 = enable\n    //\n    // <5:0>  ???\n    //\n    // disable CRC\n    //\n    // NB, this also affects TX pre-amble in some way\n    //\n    BK4819_WriteRegister(BK4819_REG_5C, 0x5625);   // 010101100 0 100101\n//\t\tBK4819_WriteRegister(0x5C, 0xAA30);   // 101010100 0 110000\n//\t\tBK4819_WriteRegister(0x5C, 0x0030);   // 000000000 0 110000\n\n    BK4819_WriteRegister(BK4819_REG_59, (1u << 15) | (1u << 14) | fsk_reg59);   // clear FIFO's\n    BK4819_WriteRegister(BK4819_REG_59, fsk_reg59);\n\n    SYSTEM_DelayMs(100);\n\n    {\t// load the entire packet data into the TX FIFO buffer\n        const uint16_t len_buff = (MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH);\n        for (size_t i = 0, j = 0; i < len_buff; i += 2, j++) {\n            BK4819_WriteRegister(BK4819_REG_5F, (msgFSKBuffer[i + 1] << 8) | msgFSKBuffer[i]);\n        }\n    }\n\n    // enable FSK TX\n    BK4819_WriteRegister(BK4819_REG_59, (1u << 11) | fsk_reg59);\n\n    {\n        // allow up to 310ms for the TX to complete\n        // if it takes any longer then somethings gone wrong, we shut the TX down\n        unsigned int timeout = 1000 / 5;\n\n        while (timeout-- > 0)\n        {\n            SYSTEM_DelayMs(5);\n            if (BK4819_ReadRegister(BK4819_REG_0C) & (1u << 0))\n            {\t// we have interrupt flags\n                BK4819_WriteRegister(BK4819_REG_02, 0);\n                if (BK4819_ReadRegister(BK4819_REG_02) & BK4819_REG_02_FSK_TX_FINISHED)\n                    timeout = 0;       // TX is complete\n            }\n        }\n    }\n    //BK4819_WriteRegister(BK4819_REG_02, 0);\n\n    SYSTEM_DelayMs(100);\n\n    // disable FSK\n    BK4819_WriteRegister(BK4819_REG_59, fsk_reg59);\n\n    // restore FM deviation level\n    BK4819_WriteRegister(BK4819_REG_40, dev_val);\n\n    // restore TX/RX filtering\n    BK4819_WriteRegister(BK4819_REG_2B, filt_val);\n\n    // restore the CTCSS/CDCSS setting\n    BK4819_WriteRegister(BK4819_REG_51, css_val);\n\n}\n\n\n\n// -----------------------------------------------------\n\nvoid moveUP(char (*rxMessages)[MAX_RX_MSG_LENGTH + 2]) {\n    // Shift existing lines up\n    strcpy(rxMessages[0], rxMessages[1]);\n    strcpy(rxMessages[1], rxMessages[2]);\n    strcpy(rxMessages[2], rxMessages[3]);\n\n    // Insert the new line at the last position\n    memset(rxMessages[3], 0, sizeof(rxMessages[3]));\n}\n\nvoid MSG_Send(const char *txMessage, bool bServiceMessage) {\n\n    if ( msgStatus != READY ) return;\n    stop_mdc_flag=1;\n    if ( strlen(txMessage) > 0 && (TX_freq_check(gCurrentVfo->pTX->Frequency) == 0) ) {\n\n        msgStatus = SENDING;\n\n        RADIO_SetVfoState(VFO_STATE_NORMAL);\n        BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, true);\n\n//\t\tmemset(msgFSKBuffer, 0, sizeof(msgFSKBuffer));\n\n        // ? ToDo\n        // first 20 byte sync, msg type and ID\n        msgFSKBuffer[0] = 'M';\n        msgFSKBuffer[1] = 'S';\n\n        // next 20 for msg\n        memcpy(msgFSKBuffer + 2, txMessage, TX_MSG_LENGTH);\n\n        // CRC ? ToDo\n\n        msgFSKBuffer[MAX_RX_MSG_LENGTH - 1] = '\\0';\n        msgFSKBuffer[MAX_RX_MSG_LENGTH + 0] = 'I';\n        msgFSKBuffer[MAX_RX_MSG_LENGTH + 1] = 'D';\n        msgFSKBuffer[MAX_RX_MSG_LENGTH + 2] = '0';\n        msgFSKBuffer[(MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH) - 1] = '#';\n        msgFSKBuffer[(MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH) ] = '\\0';\n\n        BK4819_DisableDTMF();\n\n        //RADIO_SetTxParameters();\n        FUNCTION_Select(FUNCTION_TRANSMIT);\n        //SYSTEM_DelayMs(500);\n        BK4819_PlayRogerNormal();\n        SYSTEM_DelayMs(100);\n\n        BK4819_ExitTxMute();\n\n        MSG_FSKSendData();\n\n        //SYSTEM_DelayMs(100);\n\n        APP_EndTransmission(true); //OK\n\n        RADIO_SetVfoState(VFO_STATE_NORMAL);\n\n        BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, false);\n\n        enable_msg_rx(true);\n        if (!bServiceMessage) {\n            moveUP(rxMessage);\n            sprintf(rxMessage[3], \"> %s\", txMessage);\n//\t\t\tmemset(lastcMessage, 0, sizeof(lastcMessage));\n            memcpy(lastcMessage, txMessage, TX_MSG_LENGTH);\n            lastcMessage[TX_MSG_LENGTH]=0;\n            cIndex = 0;\n            prevKey = 0;\n            prevLetter = 0;\n            memset(cMessage, 0, sizeof(cMessage));\n//            cMessage[0]='\\0';\n        }\n        msgStatus = READY;\n\n    }\n#ifdef    ENABLE_WARNING\n\n    else {\n        AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL);\n    }\n#endif\n    stop_mdc_flag=0;\n}\n\nuint8_t validate_char( uint8_t rchar ) {\n    if ( (rchar == 0x1b) || (rchar >= 32 && rchar <= 127) ) {\n        return rchar;\n    }\n    return 32;\n}\n\n\n\nvoid MSG_Init() {\n    memset(rxMessage, 0, sizeof(rxMessage));\n//\tmemset(cMessage, 0, sizeof(cMessage));\n//\tmemset(lastcMessage, 0, sizeof(lastcMessage));\n    lastcMessage[0]=0;cMessage[0]=0;\n    hasNewMessage = 0;\n    msgStatus = READY;\n    prevKey = 0;\n    prevLetter = 0;\n    cIndex = 0;\n}\n\n// ---------------------------------------------------------------------------------\n\nvoid insertCharInMessage(uint8_t key) {\n    if ( key == KEY_0 ) {\n        if ( keyboardType == NUMERIC ) {\n            cMessage[cIndex] = '0';\n        } else {\n            cMessage[cIndex] = ' ';\n        }\n        if ( cIndex < MAX_MSG_LENGTH ) {\n            cIndex++;\n        }\n    } else if (prevKey == key)\n    {\n        cIndex = (cIndex > 0) ? cIndex - 1 : 0;\n        if ( keyboardType == NUMERIC ) {\n            cMessage[cIndex] = T9TableNum[key - 1][(++prevLetter) % numberOfNumsAssignedToKey[key - 1]];\n        } else if ( keyboardType == LOWERCASE ) {\n            cMessage[cIndex] = T9TableLow[key - 1][(++prevLetter) % numberOfLettersAssignedToKey[key - 1]];\n        } else {\n            cMessage[cIndex] = T9TableUp[key - 1][(++prevLetter) % numberOfLettersAssignedToKey[key - 1]];\n        }\n        if ( cIndex < MAX_MSG_LENGTH ) {\n            cIndex++;\n        }\n    }\n    else\n    {\n        prevLetter = 0;\n        if ( cIndex >= MAX_MSG_LENGTH ) {\n            cIndex = (cIndex > 0) ? cIndex - 1 : 0;\n        }\n        if ( keyboardType == NUMERIC ) {\n            cMessage[cIndex] = T9TableNum[key - 1][prevLetter];\n        } else if ( keyboardType == LOWERCASE ) {\n            cMessage[cIndex] = T9TableLow[key - 1][prevLetter];\n        } else {\n            cMessage[cIndex] = T9TableUp[key - 1][prevLetter];\n        }\n        if ( cIndex < MAX_MSG_LENGTH ) {\n            cIndex++;\n        }\n\n    }\n    cMessage[cIndex] = '\\0';\n    if ( keyboardType == NUMERIC ) {\n        prevKey = 0;\n        prevLetter = 0;\n    } else {\n        prevKey = key;\n    }\n}\n\nvoid processBackspace() {\n    cIndex = (cIndex > 0) ? cIndex - 1 : 0;\n    cMessage[cIndex] = '\\0';\n    prevKey = 0;\n    prevLetter = 0;\n}\n\nvoid  MSG_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) {\n    uint8_t state = bKeyPressed + 2 * bKeyHeld;\n\n    if (state == MSG_BUTTON_EVENT_SHORT) {\n\n        switch (Key)\n        {\n            case KEY_0...KEY_9:\n                if ( keyTickCounter > NEXT_CHAR_DELAY) {\n                    prevKey = 0;\n                    prevLetter = 0;\n                }\n                insertCharInMessage(Key);\n                keyTickCounter = 0;\n                break;\n            case KEY_STAR:\n                keyboardType = (KeyboardType)((keyboardType + 1) % END_TYPE_KBRD);\n                break;\n            case KEY_F:\n                processBackspace();\n                break;\n            case KEY_UP:\n//\t\t\t\tmemset(cMessage, 0, sizeof(cMessage));\n                memcpy(cMessage, lastcMessage, TX_MSG_LENGTH);\n                cMessage[TX_MSG_LENGTH]='\\0';\n                cIndex = strlen(cMessage);\n                break;\n            /*case KEY_DOWN:\n                break;*/\n            case KEY_MENU:\n                // Send message\n                MSG_Send(cMessage, false);\n                break;\n            case KEY_EXIT:\n                gRequestDisplayScreen = DISPLAY_MAIN;\n                break;\n\n            default:\n#ifdef    ENABLE_WARNING\n\n                AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL);\n#endif\n                break;\n        }\n\n    } else if (state == MSG_BUTTON_EVENT_LONG) {\n\n        switch (Key)\n        {\n            case KEY_F:\n                MSG_Init();\n                break;\n            default:\n#ifdef    ENABLE_WARNING\n                AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL);\n#endif\n                break;\n        }\n    }\n\n}\n\n\n#endif\n\nvoid solve_sign(const uint16_t interrupt_bits) {\n\n\n    //const uint16_t rx_sync_flags   = BK4819_ReadRegister(BK4819_REG_0B);\n\n    const bool rx_sync = (interrupt_bits & BK4819_REG_02_FSK_RX_SYNC) ? true : false;\n    const bool rx_fifo_almost_full = (interrupt_bits & BK4819_REG_02_FSK_FIFO_ALMOST_FULL) ? true : false;\n    const bool rx_finished = (interrupt_bits & BK4819_REG_02_FSK_RX_FINISHED) ? true : false;\n\n    const uint16_t rx_sync_flags = BK4819_ReadRegister(0x0B);\n#if defined(ENABLE_MDC1200)||defined(ENABLE_MESSENGER)\n\n    const bool rx_sync_neg = (rx_sync_flags & (1u << 7)) ? true : false;\n#endif\n    if (rx_sync) {\n#ifdef ENABLE_MESSENGER\n\n        gFSKWriteIndex = 0;\n//        memset(msgFSKBuffer, 0, sizeof(msgFSKBuffer));\n        msgStatus = RECEIVING;\n\n#endif\n#ifdef ENABLE_MDC1200\n        mdc1200_rx_buffer_index = 0;\n\n        {\n//            memset(mdc1200_rx_buffer, 0, sizeof(mdc1200_rx_buffer));\n            for (unsigned int  i = 0; i < sizeof(mdc1200_sync_suc_xor); i++)\n                mdc1200_rx_buffer[mdc1200_rx_buffer_index++] = mdc1200_sync_suc_xor[i] ^ (rx_sync_neg ? 0xFF : 0x00);\n        }\n#endif\n    }\n\n    if (rx_fifo_almost_full) {\n        const uint16_t count = BK4819_ReadRegister(BK4819_REG_5E) & (7u << 0);  // almost full threshold\n#if defined(ENABLE_MDC1200)||defined(ENABLE_MESSENGER)\n        uint16_t read_reg[count];\n#endif\n#ifdef ENABLE_MDC1200\n\n        {\n\n            // fetch received packet data\n            for (int i = 0; i < count; i++) {\n                read_reg[i]=BK4819_ReadRegister(0x5F);\n                const uint16_t word =read_reg[i] ^ (rx_sync_neg ? 0xFFFF : 0x0000);\n\n\n                if (mdc1200_rx_buffer_index < sizeof(mdc1200_rx_buffer))\n                    mdc1200_rx_buffer[mdc1200_rx_buffer_index++] = (word >> 0) & 0xff;\n\n                if (mdc1200_rx_buffer_index < sizeof(mdc1200_rx_buffer))\n                    mdc1200_rx_buffer[mdc1200_rx_buffer_index++] = (word >> 8) & 0xff;\n#ifdef ENABLE_MESSENGER\n\n                  if (gFSKWriteIndex < sizeof(msgFSKBuffer))\n                    msgFSKBuffer[gFSKWriteIndex++] = validate_char((read_reg[i]  >> 0) & 0xff);\n                if (gFSKWriteIndex < sizeof(msgFSKBuffer))\n                    msgFSKBuffer[gFSKWriteIndex++] = validate_char((read_reg[i]  >> 8) & 0xff);\n#endif\n            }\n#ifdef ENABLE_MESSENGER\n\n            msgFSKBuffer[gFSKWriteIndex]='\\0';\n#endif\n\n            if (mdc1200_rx_buffer_index >= sizeof(mdc1200_rx_buffer)) {\n\n\n                if (MDC1200_process_rx_data(\n                        mdc1200_rx_buffer,\n                        mdc1200_rx_buffer_index,\n                        &mdc1200_op,\n                        &mdc1200_arg,\n                        &mdc1200_unit_id)) {\n                    mdc1200_rx_ready_tick_500ms = 2 * 5;  // 6 second MDC display time\n                    gUpdateDisplay = true;\n\n                }\n\n                mdc1200_rx_buffer_index = 0;\n            }\n\n        }\n#endif\n\n    }\n\n    if (rx_finished) {\n\n        const uint16_t fsk_reg59 =\n                BK4819_ReadRegister(BK4819_REG_59) & ~((1u << 15) | (1u << 14) | (1u << 12) | (1u << 11));\n\n        BK4819_WriteRegister(BK4819_REG_59, (1u << 15) | (1u << 14) | fsk_reg59);\n        BK4819_WriteRegister(BK4819_REG_59, (1u << 12) | fsk_reg59);\n#ifdef ENABLE_MESSENGER\n\n        msgStatus = READY;\n\n//        if (gFSKWriteIndex > 2) {\n\n            // If there's three 0x1b bytes, then it's a service message\n            if (msgFSKBuffer[2] == 0x1b && msgFSKBuffer[3] == 0x1b && msgFSKBuffer[4] == 0x1b) {\n#ifdef ENABLE_MESSENGER_DELIVERY_NOTIFICATION\n                // If the next 4 bytes are \"RCVD\", then it's a delivery notification\n                if (msgFSKBuffer[5] == 'R' && msgFSKBuffer[6] == 'C' && msgFSKBuffer[7] == 'V' && msgFSKBuffer[8] == 'D') {\n                    rxMessage[3][strlen(rxMessage[3])] = '+';\n                    gUpdateStatus = true;\n                    gUpdateDisplay = true;\n                }\n#endif\n            } else {\n                bool show_flag=0;\n                if (msgFSKBuffer[0] == 'M' && msgFSKBuffer[1] == 'S')\n                {\n                    moveUP(rxMessage);\n                    show_flag=1;\n                    snprintf(rxMessage[3], TX_MSG_LENGTH + 2, \"< %s\", &msgFSKBuffer[2]);\n                    MSG_Send(\"\\x1b\\x1b\\x1bRCVD\", true);\n\n                }\n\n                if(show_flag){\n                    if ( gScreenToDisplay != DISPLAY_MSG ) {\n                        hasNewMessage = 1;\n                        gUpdateStatus = true;\n                        gUpdateDisplay = true;\n#ifdef ENABLE_MESSENGER_NOTIFICATION\n                        gPlayMSGRing = true;\n#endif\n                    }\n                    else {\n                        gUpdateDisplay = true;\n                    }\n                }\n            }\n//        }\n\n        gFSKWriteIndex = 0;\n\n#endif\n    }\n}"
  },
  {
    "path": "app/messenger.h",
    "content": "#ifndef APP_MSG_H\n#define APP_MSG_H\n\n#include <stdbool.h>\n#include <stdint.h>\n#include <string.h>\n#include \"driver/keyboard.h\"\n\n#ifdef ENABLE_MESSENGER\n\n\ntypedef enum KeyboardType {\n    UPPERCASE,\n      LOWERCASE,\n      NUMERIC,\n      END_TYPE_KBRD\n} KeyboardType;\ntypedef enum MsgStatus {\n    READY,\n      SENDING,\n      RECEIVING,\n} MsgStatus;\nenum {\n    TX_MSG_LENGTH = 30,\n    MSG_HEADER_LENGTH = 20,\n    MAX_RX_MSG_LENGTH = TX_MSG_LENGTH + 2\n};\n//const uint8_t TX_MSG_LENGTH = 30;\n//const uint8_t MAX_RX_MSG_LENGTH = TX_MSG_LENGTH + 2;\nuint8_t validate_char( uint8_t rchar ) ;\n\nextern KeyboardType keyboardType;\nextern uint16_t gErrorsDuringMSG;\nextern char cMessage[TX_MSG_LENGTH];\nextern char rxMessage[4][MAX_RX_MSG_LENGTH + 2];\nextern uint8_t hasNewMessage;\nextern uint8_t keyTickCounter;\n\nvoid MSG_Init();\nvoid MSG_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld);\nvoid MSG_Send(const char *txMessage, bool bServiceMessage);\nextern unsigned char cIndex ;\n//extern bool stop_mdc_rx;\nextern uint8_t msgFSKBuffer[MSG_HEADER_LENGTH + MAX_RX_MSG_LENGTH];\nvoid moveUP(char (*rxMessages)[MAX_RX_MSG_LENGTH + 2]) ;\n\nextern MsgStatus msgStatus ;\nextern bool stop_mdc_flag;\n\n#endif\n\nvoid solve_sign(const uint16_t interrupt_bits);\n\n#endif\n"
  },
  {
    "path": "app/scanner.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"app/app.h\"\r\n#include \"app/dtmf.h\"\r\n#include \"app/generic.h\"\r\n#include \"app/menu.h\"\r\n#include \"app/scanner.h\"\r\n#include \"audio.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"frequencies.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"settings.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/ui.h\"\r\n\r\nDCS_CodeType_t gScanCssResultType;\r\nuint8_t gScanCssResultCode;\r\n#ifdef  TEST_UNDE_CTCSS\r\nuint16_t           gScanCssResultCode_all;\r\n#endif\r\nbool gScanSingleFrequency; // scan CTCSS/DCS codes for current frequency\r\nSCAN_SaveState_t gScannerSaveState;\r\nuint8_t gScanChannel;\r\nuint32_t gScanFrequency;\r\nSCAN_CssState_t gScanCssState;\r\nuint8_t gScanProgressIndicator;\r\nbool gScanUseCssResult;\r\n\r\nSTEP_Setting_t stepSetting;\r\nuint8_t scanHitCount;\r\n\r\n\r\nstatic void SCANNER_Key_DIGITS(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) {\r\n    if (!bKeyHeld && bKeyPressed) {\r\n        if (gScannerSaveState == SCAN_SAVE_CHAN_SEL) {\r\n            gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n\r\n            INPUTBOX_Append(Key);\r\n\r\n            gRequestDisplayScreen = DISPLAY_SCANNER;\r\n\r\n            if (gInputBoxIndex < 3) {\r\n#ifdef ENABLE_VOICE\r\n                gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n                return;\r\n            }\r\n\r\n            gInputBoxIndex = 0;\r\n\r\n            uint16_t chan = ((gInputBox[0] * 100) + (gInputBox[1] * 10) + gInputBox[2]) - 1;\r\n            if (IS_MR_CHANNEL(chan)) {\r\n#ifdef ENABLE_VOICE\r\n                gAnotherVoiceID = (VOICE_ID_t)Key;\r\n#endif\r\n                gShowChPrefix = RADIO_CheckValidChannel(chan, false, 0);\r\n                gScanChannel = (uint8_t) chan;\r\n                return;\r\n            }\r\n        }\r\n\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n    }\r\n}\r\n\r\nstatic void SCANNER_Key_EXIT(bool bKeyPressed, bool bKeyHeld) {\r\n    if (!bKeyHeld && bKeyPressed) { // short pressed\r\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n\r\n        switch (gScannerSaveState) {\r\n            case SCAN_SAVE_NO_PROMPT:\r\n                SCANNER_Stop();\r\n                gRequestDisplayScreen = DISPLAY_MAIN;\r\n                break;\r\n\r\n            case SCAN_SAVE_CHAN_SEL:\r\n                if (gInputBoxIndex > 0) {\r\n                    gInputBox[--gInputBoxIndex] = 10;\r\n                    gRequestDisplayScreen = DISPLAY_SCANNER;\r\n                    break;\r\n                }\r\n\r\n                // Fallthrough\r\n\r\n            case SCAN_SAVE_CHANNEL:\r\n                gScannerSaveState = SCAN_SAVE_NO_PROMPT;\r\n#ifdef ENABLE_VOICE\r\n                gAnotherVoiceID   = VOICE_ID_CANCEL;\r\n#endif\r\n                gRequestDisplayScreen = DISPLAY_SCANNER;\r\n                break;\r\n        }\r\n    }\r\n}\r\n\r\nstatic void SCANNER_Key_MENU(bool bKeyPressed, bool bKeyHeld) {\r\n    if (bKeyHeld || !bKeyPressed) // ignore long press or release button events\r\n        return;\r\n\r\n    if (gScanCssState == SCAN_CSS_STATE_OFF && !gScanSingleFrequency) {\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n        return;\r\n    }\r\n\r\n    if (gScanCssState == SCAN_CSS_STATE_SCANNING && gScanSingleFrequency) {\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n        return;\r\n    }\r\n\r\n    if (gScanCssState == SCAN_CSS_STATE_FAILED) {\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n        return;\r\n    }\r\n\r\n    gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n\r\n    switch (gScannerSaveState) {\r\n        case SCAN_SAVE_NO_PROMPT:\r\n            if (!gScanSingleFrequency) {\r\n                uint32_t freq250 = FREQUENCY_RoundToStep(gScanFrequency, 250);\r\n                uint32_t freq625 = FREQUENCY_RoundToStep(gScanFrequency, 625);\r\n\r\n                uint32_t diff250 = gScanFrequency > freq250 ? gScanFrequency - freq250 : freq250 - gScanFrequency;\r\n                uint32_t diff625 = gScanFrequency > freq625 ? gScanFrequency - freq625 : freq625 - gScanFrequency;\r\n\r\n                if (diff250 > diff625) {\r\n                    stepSetting = STEP_6_25kHz;\r\n                    gScanFrequency = freq625;\r\n                } else {\r\n                    stepSetting = STEP_2_5kHz;\r\n                    gScanFrequency = freq250;\r\n                }\r\n            }\r\n\r\n            if (IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) {\r\n                gScannerSaveState = SCAN_SAVE_CHAN_SEL;\r\n                gScanChannel = gTxVfo->CHANNEL_SAVE;\r\n                gShowChPrefix = RADIO_CheckValidChannel(gTxVfo->CHANNEL_SAVE, false, 0);\r\n            } else {\r\n                gScannerSaveState = SCAN_SAVE_CHANNEL;\r\n            }\r\n\r\n            gScanCssState = SCAN_CSS_STATE_FOUND;\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID   = VOICE_ID_MEMORY_CHANNEL;\r\n#endif\r\n            gRequestDisplayScreen = DISPLAY_SCANNER;\r\n\r\n            gUpdateStatus = true;\r\n            break;\r\n\r\n        case SCAN_SAVE_CHAN_SEL:\r\n            if (gInputBoxIndex == 0) {\r\n                gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n                gRequestDisplayScreen = DISPLAY_SCANNER;\r\n                gScannerSaveState = SCAN_SAVE_CHANNEL;\r\n            }\r\n            break;\r\n\r\n        case SCAN_SAVE_CHANNEL:\r\n            if (!gScanSingleFrequency) {\r\n                RADIO_InitInfo(gTxVfo, gTxVfo->CHANNEL_SAVE, gScanFrequency);\r\n\r\n                if (gScanUseCssResult) {\r\n                    gTxVfo->freq_config_RX.CodeType = gScanCssResultType;\r\n                    gTxVfo->freq_config_RX.Code = gScanCssResultCode;\r\n                }\r\n\r\n                gTxVfo->freq_config_TX = gTxVfo->freq_config_RX;\r\n                gTxVfo->STEP_SETTING = stepSetting;\r\n            } else {\r\n                RADIO_ConfigureChannel(0, VFO_CONFIGURE_RELOAD);\r\n                RADIO_ConfigureChannel(1, VFO_CONFIGURE_RELOAD);\r\n\r\n                gTxVfo->freq_config_RX.CodeType = gScanCssResultType;\r\n                gTxVfo->freq_config_RX.Code = gScanCssResultCode;\r\n                gTxVfo->freq_config_TX.CodeType = gScanCssResultType;\r\n                gTxVfo->freq_config_TX.Code = gScanCssResultCode;\r\n            }\r\n\r\n            uint8_t chan;\r\n            if (IS_MR_CHANNEL(gTxVfo->CHANNEL_SAVE)) {\r\n                chan = gScanChannel;\r\n                gEeprom.MrChannel[gEeprom.TX_VFO] = chan;\r\n            } else {\r\n                chan = gTxVfo->Band + FREQ_CHANNEL_FIRST;\r\n                gEeprom.FreqChannel[gEeprom.TX_VFO] = chan;\r\n            }\r\n\r\n            gTxVfo->CHANNEL_SAVE = chan;\r\n            gEeprom.ScreenChannel[gEeprom.TX_VFO] = chan;\r\n#ifdef ENABLE_VOICE\r\n            gAnotherVoiceID = VOICE_ID_CONFIRM;\r\n#endif\r\n            gRequestDisplayScreen = DISPLAY_SCANNER;\r\n            gRequestSaveChannel = 2;\r\n            gScannerSaveState = SCAN_SAVE_NO_PROMPT;\r\n            break;\r\n\r\n        default:\r\n            gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n            break;\r\n    }\r\n}\r\n\r\nstatic void SCANNER_Key_STAR(bool bKeyPressed, bool bKeyHeld) {\r\n    if (!bKeyHeld && bKeyPressed) {\r\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n        SCANNER_Start(gScanSingleFrequency);\r\n    }\r\n    return;\r\n}\r\n\r\nstatic void SCANNER_Key_UP_DOWN(bool bKeyPressed, bool pKeyHeld, int8_t Direction) {\r\n    if (pKeyHeld) {\r\n        if (!bKeyPressed)\r\n            return;\r\n    } else {\r\n        if (!bKeyPressed)\r\n            return;\r\n\r\n        gInputBoxIndex = 0;\r\n        gBeepToPlay = BEEP_1KHZ_60MS_OPTIONAL;\r\n    }\r\n\r\n    if (gScannerSaveState == SCAN_SAVE_CHAN_SEL) {\r\n        gScanChannel = NUMBER_AddWithWraparound(gScanChannel, Direction, 0, MR_CHANNEL_LAST);\r\n        gShowChPrefix = RADIO_CheckValidChannel(gScanChannel, false, 0);\r\n        gRequestDisplayScreen = DISPLAY_SCANNER;\r\n    } else\r\n        gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n}\r\n\r\nvoid SCANNER_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld) {\r\n    switch (Key) {\r\n        case KEY_0:\r\n        case KEY_1:\r\n        case KEY_2:\r\n        case KEY_3:\r\n        case KEY_4:\r\n        case KEY_5:\r\n        case KEY_6:\r\n        case KEY_7:\r\n        case KEY_8:\r\n        case KEY_9:\r\n            SCANNER_Key_DIGITS(Key, bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_MENU:\r\n            SCANNER_Key_MENU(bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_UP:\r\n            SCANNER_Key_UP_DOWN(bKeyPressed, bKeyHeld, 1);\r\n            break;\r\n        case KEY_DOWN:\r\n            SCANNER_Key_UP_DOWN(bKeyPressed, bKeyHeld, -1);\r\n            break;\r\n        case KEY_EXIT:\r\n            SCANNER_Key_EXIT(bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_STAR:\r\n            SCANNER_Key_STAR(bKeyPressed, bKeyHeld);\r\n            break;\r\n        case KEY_PTT:\r\n            GENERIC_Key_PTT(bKeyPressed);\r\n            break;\r\n        default:\r\n            if (!bKeyHeld && bKeyPressed)\r\n                gBeepToPlay = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n            break;\r\n    }\r\n}\r\n\r\nvoid SCANNER_Start(bool singleFreq) {\r\n    gScanSingleFrequency = singleFreq;\r\n    gMonitor = false;\r\n\r\n#ifdef ENABLE_VOICE\r\n    gAnotherVoiceID = VOICE_ID_SCANNING_BEGIN;\r\n#endif\r\n\r\n    BK4819_StopScan();\r\n    RADIO_SelectVfos();\r\n\r\n#ifdef ENABLE_NOAA\r\n    if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE))\r\n        gRxVfo->CHANNEL_SAVE = FREQ_CHANNEL_FIRST + BAND6_400MHz;\r\n#endif\r\n\r\n    uint8_t backupStep = gRxVfo->STEP_SETTING;\r\n    uint16_t backupFrequency = gRxVfo->StepFrequency;\r\n\r\n    RADIO_InitInfo(gRxVfo, gRxVfo->CHANNEL_SAVE, gRxVfo->pRX->Frequency);\r\n\r\n    gRxVfo->STEP_SETTING = backupStep;\r\n    gRxVfo->StepFrequency = backupFrequency;\r\n\r\n    RADIO_SetupRegisters(true);\r\n\r\n#ifdef ENABLE_NOAA\r\n    gIsNoaaMode = false;\r\n#endif\r\n\r\n    if (gScanSingleFrequency) {\r\n        gScanCssState = SCAN_CSS_STATE_SCANNING;\r\n        gScanFrequency = gRxVfo->pRX->Frequency;\r\n        stepSetting = gRxVfo->STEP_SETTING;\r\n\r\n        BK4819_PickRXFilterPathBasedOnFrequency(gScanFrequency);\r\n        BK4819_SetScanFrequency(gScanFrequency);\r\n\r\n        gUpdateStatus = true;\r\n    } else {\r\n        gScanCssState = SCAN_CSS_STATE_OFF;\r\n        gScanFrequency = 0xFFFFFFFF;\r\n\r\n        BK4819_PickRXFilterPathBasedOnFrequency(gScanFrequency);\r\n        BK4819_EnableFrequencyScan();\r\n\r\n        gUpdateStatus = true;\r\n    }\r\n#ifdef ENABLE_DTMF_CALLING\r\n    DTMF_clear_RX();\r\n#endif\r\n    gScanDelay_10ms = scan_delay_10ms;\r\n    gScanCssResultCode = 0xFF;\r\n#ifdef TEST_UNDE_CTCSS\r\n\r\n    gScanCssResultCode_all=0xffff;\r\n#endif\r\n\r\n    gScanCssResultType = 0xFF;\r\n    scanHitCount = 0;\r\n    gScanUseCssResult = false;\r\n    g_CxCSS_TAIL_Found = false;\r\n    g_CDCSS_Lost = false;\r\n    gCDCSSCodeType = 0;\r\n    g_CTCSS_Lost = false;\r\n#ifdef ENABLE_VOX\r\n    g_VOX_Lost         = false;\r\n#endif\r\n    g_SquelchLost = false;\r\n    gScannerSaveState = SCAN_SAVE_NO_PROMPT;\r\n    gScanProgressIndicator = 0;\r\n}\r\n\r\nvoid SCANNER_Stop(void) {\r\n    if (SCANNER_IsScanning()) {\r\n        gEeprom.CROSS_BAND_RX_TX = gBackup_CROSS_BAND_RX_TX;\r\n        gVfoConfigureMode = VFO_CONFIGURE_RELOAD;\r\n        gFlagResetVfos = true;\r\n        gUpdateStatus = true;\r\n        gCssBackgroundScan = false;\r\n        gScanUseCssResult = false;\r\n#ifdef ENABLE_VOICE\r\n        gAnotherVoiceID          = VOICE_ID_CANCEL;\r\n#endif\r\n        BK4819_StopScan();\r\n    }\r\n}\r\n\r\nvoid SCANNER_TimeSlice10ms(void) {\r\n    if (!SCANNER_IsScanning())\r\n        return;\r\n\r\n    if (gScanDelay_10ms > 0) {\r\n        gScanDelay_10ms--;\r\n        return;\r\n    }\r\n\r\n    if (gScannerSaveState != SCAN_SAVE_NO_PROMPT) {\r\n        return;\r\n    }\r\n\r\n    switch (gScanCssState) {\r\n        case SCAN_CSS_STATE_OFF: {\r\n            // must be RF frequency scanning if we're here ?\r\n            uint32_t result;\r\n            if (!BK4819_GetFrequencyScanResult(&result))\r\n                break;\r\n\r\n            int32_t delta = result - gScanFrequency;\r\n            gScanFrequency = result;\r\n\r\n            if (delta < 0)\r\n                delta = -delta;\r\n            if (delta < 100)\r\n                scanHitCount++;\r\n            else\r\n                scanHitCount = 0;\r\n\r\n            BK4819_DisableFrequencyScan();\r\n\r\n            if (scanHitCount < 3) {\r\n                BK4819_EnableFrequencyScan();\r\n            } else {\r\n                BK4819_SetScanFrequency(gScanFrequency);\r\n                gScanCssResultCode = 0xFF;\r\n#ifdef TEST_UNDE_CTCSS\r\n\r\n                gScanCssResultCode_all=0xffff;\r\n#endif\r\n                gScanCssResultType = 0xFF;\r\n                scanHitCount = 0;\r\n                gScanUseCssResult = false;\r\n                gScanProgressIndicator = 0;\r\n                gScanCssState = SCAN_CSS_STATE_SCANNING;\r\n\r\n                if (!gCssBackgroundScan)\r\n                    GUI_SelectNextDisplay(DISPLAY_SCANNER);\r\n\r\n                gUpdateStatus = true;\r\n            }\r\n\r\n            gScanDelay_10ms = scan_delay_10ms;\r\n            //gScanDelay_10ms = 1;   // 10ms\r\n            break;\r\n        }\r\n        case SCAN_CSS_STATE_SCANNING: {\r\n            uint32_t cdcssFreq;\r\n            uint16_t ctcssFreq;\r\n            BK4819_CssScanResult_t scanResult = BK4819_GetCxCSSScanResult(&cdcssFreq, &ctcssFreq);\r\n            if (scanResult == BK4819_CSS_RESULT_NOT_FOUND)\r\n                break;\r\n\r\n            BK4819_Disable();\r\n\r\n            if (scanResult == BK4819_CSS_RESULT_CDCSS) {\r\n                const uint8_t Code = DCS_GetCdcssCode(cdcssFreq);\r\n                if (Code != 0xFF) {\r\n                    gScanCssResultCode = Code;\r\n                    gScanCssResultType = CODE_TYPE_DIGITAL;\r\n                    gScanCssState = SCAN_CSS_STATE_FOUND;\r\n                    gScanUseCssResult = true;\r\n                    gUpdateStatus = true;\r\n                }\r\n            } else if (scanResult == BK4819_CSS_RESULT_CTCSS) {\r\n#ifdef TEST_UNDE_CTCSS\r\n                const uint16_t Code = DCS_GetCtcssCode_ALL(ctcssFreq);\r\n#else\r\n                const uint8_t Code = DCS_GetCtcssCode(ctcssFreq);\r\n#endif\r\n#ifdef TEST_UNDE_CTCSS\r\n                if (Code != 0xFFFF) {\r\n                                        if (Code == gScanCssResultCode_all && gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE) {\r\n\r\n#else\r\n                if (Code != 0xFF) {\r\n                    if (Code == gScanCssResultCode && gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE) {\r\n\r\n#endif\r\n                        if (++scanHitCount >= 2) {\r\n                            gScanCssState = SCAN_CSS_STATE_FOUND;\r\n                            gScanUseCssResult = true;\r\n                            gUpdateStatus = true;\r\n                        }\r\n                    } else\r\n                        scanHitCount = 0;\r\n\r\n                    gScanCssResultType = CODE_TYPE_CONTINUOUS_TONE;\r\n#ifdef TEST_UNDE_CTCSS\r\n                    gScanCssResultCode_all = Code;\r\n#else\r\n                    gScanCssResultCode = Code;\r\n#endif\r\n                }\r\n            }\r\n//            else if (scanResult == BK4819_CSS_RESULT_CTCSS) {\r\n//                const uint8_t Code = DCS_GetCtcssCode(ctcssFreq);\r\n//                if (Code != 0xFF) {\r\n//                    if (Code == gScanCssResultCode && gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE) {\r\n//                        if (++scanHitCount >= 2) {\r\n//                            gScanCssState     = SCAN_CSS_STATE_FOUND;\r\n//                            gScanUseCssResult = true;\r\n//                            gUpdateStatus     = true;\r\n//                        }\r\n//                    }\r\n//                    else\r\n//                        scanHitCount = 0;\r\n//\r\n//                    gScanCssResultType = CODE_TYPE_CONTINUOUS_TONE;\r\n//                    gScanCssResultCode = Code;\r\n//                }\r\n//            }\r\n            if (gScanCssState < SCAN_CSS_STATE_FOUND) { // scanning or off\r\n                BK4819_SetScanFrequency(gScanFrequency);\r\n                gScanDelay_10ms = scan_delay_10ms;\r\n                break;\r\n            }\r\n\r\n            if (gCssBackgroundScan) {\r\n                gCssBackgroundScan = false;\r\n                if (gScanUseCssResult)\r\n                    MENU_CssScanFound();\r\n            } else\r\n                GUI_SelectNextDisplay(DISPLAY_SCANNER);\r\n\r\n\r\n            break;\r\n        }\r\n        default:\r\n            gCssBackgroundScan = false;\r\n            break;\r\n    }\r\n\r\n}\r\n\r\nvoid SCANNER_TimeSlice500ms(void) {\r\n    if (SCANNER_IsScanning() && gScannerSaveState == SCAN_SAVE_NO_PROMPT && gScanCssState < SCAN_CSS_STATE_FOUND) {\r\n        gScanProgressIndicator++;\r\n#ifndef ENABLE_NO_CODE_SCAN_TIMEOUT\r\n        if (gScanProgressIndicator > 32) {\r\n            if (gScanCssState == SCAN_CSS_STATE_SCANNING && !gScanSingleFrequency)\r\n                gScanCssState = SCAN_CSS_STATE_FOUND;\r\n            else\r\n                gScanCssState = SCAN_CSS_STATE_FAILED;\r\n\r\n            gUpdateStatus = true;\r\n        }\r\n#endif\r\n        gUpdateDisplay = true;\r\n    } else if (gCssBackgroundScan) {\r\n        gUpdateDisplay = true;\r\n    }\r\n}\r\n\r\nbool SCANNER_IsScanning(void) {\r\n    return gCssBackgroundScan || (gScreenToDisplay == DISPLAY_SCANNER);\r\n}"
  },
  {
    "path": "app/scanner.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef APP_SCANNER_H\r\n#define APP_SCANNER_H\r\n\r\n#include \"dcs.h\"\r\n#include \"driver/keyboard.h\"\r\n\r\ntypedef enum {\r\n    SCAN_CSS_STATE_OFF,\r\n    SCAN_CSS_STATE_SCANNING,\r\n    SCAN_CSS_STATE_FOUND,\r\n    SCAN_CSS_STATE_FAILED\r\n} SCAN_CssState_t;\r\n\r\ntypedef enum {\r\n    SCAN_SAVE_NO_PROMPT, // saving process not initiated\r\n    SCAN_SAVE_CHAN_SEL,  // \"SAVE: \", channel select prompt, actives only in channel mode\r\n    SCAN_SAVE_CHANNEL,   // \"SAVE?\" prompt, waits for confirmation to save settings to channel, or current VFO\r\n} SCAN_SaveState_t;\r\n\r\n\r\nextern DCS_CodeType_t gScanCssResultType;\r\nextern uint8_t gScanCssResultCode;\r\nextern uint16_t gScanCssResultCode_all;\r\n\r\nextern bool gScanSingleFrequency;\r\nextern SCAN_SaveState_t gScannerSaveState;\r\nextern uint8_t gScanChannel;\r\nextern uint32_t gScanFrequency;\r\nextern SCAN_CssState_t gScanCssState;\r\nextern uint8_t gScanProgressIndicator;\r\nextern bool gScanUseCssResult;\r\n\r\nvoid SCANNER_ProcessKeys(KEY_Code_t Key, bool bKeyPressed, bool bKeyHeld);\r\n\r\nvoid SCANNER_Start(bool singleFreq);\r\n\r\nvoid SCANNER_Stop(void);\r\n\r\nvoid SCANNER_TimeSlice10ms(void);\r\n\r\nvoid SCANNER_TimeSlice500ms(void);\r\n\r\nbool SCANNER_IsScanning(void);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "app/si.c",
    "content": "#include \"si.h\"\n#include \"../driver/bk4819.h\"\n#include \"../driver/si473x.h\"\n#include \"../helper/rds.h\"\n#include \"../misc.h\"\n\n//\n// Created by RUPC on 2024/3/10.\n//\n#include \"board.h\"\n\n#include \"driver/si473x.h\"\n#include \"bsp/dp32g030/gpio.h\"\n#include \"bsp/dp32g030/syscon.h\"\n\n#include \"driver/gpio.h\"\n#include \"driver/i2c.h\"\n#include \"driver/system.h\"\n#include \"frequencies.h\"\n#include \"misc.h\"\n#include \"ui/helper.h\"\n#include <string.h>\n#include \"./si.h\"\n#include \"app/fm.h\"\n#include \"driver/st7565.h\"\n#include \"external/printf/printf.h\"\n#include \"misc.h\"\n#include \"settings.h\"\n#include \"ui/fmradio.h\"\n#include \"ui/helper.h\"\n#include \"ui/inputbox.h\"\n\n#include \"stdbool.h\"\n\n#include \"driver/eeprom.h\"\n#include \"driver/backlight.h\"\n#include \"ui/helper.h\"\n\n#include <stdint.h>\n\ntypedef enum {\n    FM_BT,\n    MW_BT,\n    SW_BT,\n    LW_BT,\n} BandType;\n\nstatic const char SI47XX_BW_NAMES[5][6] = {\n        \"6 kHz\", \"4 kHz\", \"3 kHz\", \"2 kHz\", \"1 kHz\",\n};\n\nstatic const char SI47XX_SSB_BW_NAMES[6][8] = {\n        \"1.2 kHz\", \"2.2 kHz\", \"3 kHz\", \"4 kHz\", \"0.5 kHz\", \"1 kHz\",\n};\n\nstatic const char SI47XX_MODE_NAMES[5][4] = {\n        \"FM\", \"AM\", \"LSB\", \"USB\", \"CW\",\n};\n\nstatic SI47XX_FilterBW bw = SI47XX_BW_6_kHz;\nstatic SI47XX_SsbFilterBW ssbBw = SI47XX_SSB_BW_3_kHz;\nstatic int8_t currentBandIndex = -1;\nbool SNR_flag = true;\nbool SI_run = true;\n\n#include \"app/spectrum.h\"\ntypedef struct // Band data\n{\n    const char *bandName; // Bandname\n//    BandType bandType;    // Band type (FM, MW or SW)\n//    SI47XX_MODE prefmod;  // Pref. modulation\n    uint16_t minimumFreq; // Minimum frequency of the band\n    uint16_t maximumFreq; // maximum frequency of the band\n//    uint16_t currentFreq; // Default frequency or current frequency\n//    uint8_t currentStep;  // Default step (increment and decrement)\n//    int lastBFO;          // Last BFO per band\n//    int lastmanuBFO;      // Last Manual BFO per band using X-Tal\n\n} SIBand;\n\nSIBand bands[] = {\n        {\"LW\"/*,         LW_BT, SI47XX_AM*/,  148,   283/*,   198,   9, 0, 0*/},         //  LW          1\n        {\"LW\"/*,         LW_BT, SI47XX_AM*/,  100,   514/*,   198,   9, 0, 0*/},         //  LW          1\n        {\"MW Bcast\"/*,   MW_BT, SI47XX_AM*/,  526,   1606/*,  1395,  9, 0, 0*/}, //  MW          2\n        {\"MW\"/*,         MW_BT, SI47XX_AM*/,  514,   1800/*,  1395,  9, 0, 0*/},       //  MW          2\n        {\"BACON Ham\"/*,  LW_BT, SI47XX_AM*/,  280,   470/*,   284,   1, 0, 0*/},  // Ham  800M 3\n        {\"630M Ham\"/*,   SW_BT, SI47XX_LSB*/, 470,   480/*,   475,   1, 0, 0*/},  // Ham  630M 4\n        {\"160M Ham\"/*,   SW_BT, SI47XX_LSB*/, 1800,  2000/*,  1850,  1, 0, 0*/},  // Ham  160M 5\n        {\"120M Bcast\"/*, SW_BT, SI47XX_AM*/,  2300,  2495/*,  2400,  5, 0, 0*/}, //      120M 6\n        {\"120M\"/*,       SW_BT, SI47XX_AM*/,  2000,  3200/*,  2400,  5, 0, 0*/},       //      120M 6\n        {\"90M Bcast\"/*,  SW_BT, SI47XX_AM*/,  3200,  3400/*,  3300,  5, 0, 0*/},  //       90M 7\n        {\"90M\"/*,        SW_BT, SI47XX_AM*/,  3200,  3500/*,  3300,  5, 0, 0*/},        //       90M 7\n        {\"80M Ham\"/*,    SW_BT, SI47XX_LSB*/, 3500,  3900/*,  3630,  1, 0, 0*/},   // Ham   80M 8\n        {\"75M Bcast\"/*,  SW_BT, SI47XX_AM*/,  3900,  4000/*,  3950,  5, 0, 0*/},  //       75M 9\n        {\"75M Bacst\"/*,  SW_BT, SI47XX_AM*/,  4750,  5100/*,  3950,  5, 0, 0*/},  //       75M 9\n        {\"75M\"/*,        SW_BT, SI47XX_AM*/,  3900,  5300/*,  3950,  5, 0, 0*/},        //       75M 9\n        {\"60M\"/*,        SW_BT, SI47XX_USB*/, 5300,  5900/*,  5375,  1, 0, 0*/}, // Ham   60M   10\n        {\"49M Bcast\"/*,  SW_BT, SI47XX_AM*/,  5850,  6350/*,  6000,  5, 0, 0*/}, //       49M 11\n        {\"49M\"/*,        SW_BT, SI47XX_AM*/,  5900,  7000/*,  6000,  5, 0, 0*/},       //       49M 11\n        {\"41M Bcast\"/*,  SW_BT, SI47XX_AM*/,  7200,  7500/*,  7210,  5, 0, 0*/}, //       41M 13\n        {\"40M Ham\"/*,    SW_BT, SI47XX_LSB*/, 7000,  7500/*,  7074,  1, 0, 0*/}, // Ham   40M   12\n        {\"41M\"/*,        SW_BT, SI47XX_AM*/,  7500,  9000/*,  7210,  5, 0, 0*/},      //       41M 13\n        {\"31M Bcast\"/*,  SW_BT, SI47XX_AM*/,  9400,  9990/*,  9600,  5, 0, 0*/}, //       31M 14\n        {\"31M\"/*,        SW_BT, SI47XX_AM*/,  9000,  10000/*, 9600,  5, 0, 0*/}, //       31M   14\n        {\"30M Ham\"/*,    SW_BT, SI47XX_USB*/, 10000, 10200/*, 10099, 1, 0, 0*/}, // Ham   30M   15\n        {\"25M Bcast\"/*,  SW_BT, SI47XX_AM*/,  11600, 12100/*, 11700, 5, 0, 0*/},                                                     //       25M   16\n        {\"25M\"/*,        SW_BT, SI47XX_AM*/,  10200, 13500/*, 11700, 5, 0, 0*/}, //       25M   16\n        {\"22M  Bcast\"/*, SW_BT, SI47XX_AM*/,  13500, 13870/*, 13700, 5, 0,0*/},                                                     //       22M   17\n        {\"22M\"/*,        SW_BT, SI47XX_AM*/,  13500, 14000/*, 13700, 5, 0, 0*/}, //       22M   17\n        {\"20M Ham\"/*,    SW_BT, SI47XX_USB*/, 14000, 14500/*, 14074, 1, 0, 0*/}, // Ham   20M   18\n        {\"19M Bcast\"/*,  SW_BT, SI47XX_AM*/,  15100, 15800/*, 15700, 5, 0, 0*/}, //       19M   19\n        {\"17M Bcast\"/*,  SW_BT, SI47XX_AM*/,  17480, 18050/*, 17600, 5, 0, 0*/},                                                     //       17M   20\n        {\"19M\"/*,        SW_BT, SI47XX_AM*/,  14500, 17500/*, 15700, 5, 0, 0*/}, //       19M   19\n        {\"17M\"/*,        SW_BT, SI47XX_AM*/,  17500, 18000/*, 17600, 5, 0, 0*/}, //       17M   20\n        {\"16M Ham\"/*,    SW_BT, SI47XX_USB*/, 18000, 18500/*, 18100, 1, 0, 0*/}, // Ham   16M   21\n        {\"15M Bcast\"/*,  SW_BT, SI47XX_AM*/,  18900, 19020/*, 18950, 5, 0,0*/},                                                     //       15M   22\n        {\"15M\"/*,        SW_BT, SI47XX_AM*/,  18500, 21000/*, 18950, 5, 0, 0*/}, //       15M   22\n        {\"14M Ham\"/*,    SW_BT, SI47XX_USB*/, 21000, 21450/*, 21074, 1, 0,0*/}, // Ham   14M   23\n        {\"14M Bcast\"/*,  SW_BT, SI47XX_USB*/, 21450, 21850/*, 21074, 1, 0,0*/},                                                     // Ham   14M   23\n        {\"13M\"/*,        SW_BT, SI47XX_AM*/,  21500, 24000/*, 21500, 5, 0, 0*/}, //       13M   24\n        {\"12M Ham\"/*,    SW_BT, SI47XX_USB*/, 24000, 25500/*, 24940, 1, 0,0*/}, // Ham   12M   25\n        {\"11M Bcast\"/*,  SW_BT, SI47XX_AM*/,  25600, 26100/*, 25800, 5, 0,0*/},                                                     //       11M   26\n        {\"11M\"/*,        SW_BT, SI47XX_AM*/,  25500, 26100/*, 25800, 5, 0, 0*/}, //       11M   26\n        {\"CB\"/*,         SW_BT, SI47XX_AM*/,  26100, 28000/*, 27200, 1, 0, 0*/},  // CB band 27\n        {\"10M Ham\"/*,    SW_BT, SI47XX_USB*/, 28000, 29750/*, 28500, 1, 0,0*/},                                                      // Ham   10M   28\n        {\"10M\"/*,        SW_BT, SI47XX_USB*/, 28000, 30000/*, 28500, 1, 0, 0*/}, // Ham   10M   28\n        {\"SW\" /*,         SW_BT, SI47XX_AM*/, 100,   30000/*, 15500, 5, 0, 0*/}      // Whole SW 29\n};\nstatic const uint8_t BANDS_COUNT = ARRAY_SIZE(bands);\n\nstatic int8_t getCurrentBandIndex() {\n    for (int8_t i = 0; i < BANDS_COUNT; ++i) {\n        if (siCurrentFreq >= bands[i].minimumFreq &&\n            siCurrentFreq <= bands[i].maximumFreq) {\n            return i;\n        }\n    }\n    return -1;\n}\n\nstatic uint8_t att = 0;\nstatic uint16_t step = 10;\n\nstatic DateTime dt;\nstatic int16_t bfo = 0;\nuint32_t light_time;\nbool INPUT_STATE = false;\n\nstatic void light_open() {\n    if(gEeprom.BACKLIGHT_TIME) {\n        light_time = (BACKLIGHT_MAP[gEeprom.BACKLIGHT_TIME-1]-1>=0?BACKLIGHT_MAP[gEeprom.BACKLIGHT_TIME-1]-1:0)*500;\n        BACKLIGHT_TurnOn();\n    }\n\n}\n\nvoid WaitDisplay() {\n    UI_DisplayClear();\n    UI_PrintStringSmall(\"SI4732 Wait...\", 0, 127, 3);\n    ST7565_BlitFullScreen();\n\n}\n\nstatic void tune(uint32_t f) {\n    if (si4732mode == SI47XX_FM) {\n        if (f < 6400000 || f > 10800000) {\n            return;\n        }\n    } else {\n        if (f < 15000 || f > 3000000) {\n            return;\n        }\n    }\n    EEPROM_WriteBuffer(SI4732_FREQ_ADD + si4732mode * 4, (uint8_t * ) & f, 4);\n\n    f /= divider;\n    if (si4732mode == SI47XX_FM) {\n        f -= f % 5;\n    }\n\n    SI47XX_ClearRDS();\n\n    SI47XX_SetFreq(f);\n    SI47XX_SetAutomaticGainControl(att > 0, att);\n    currentBandIndex = getCurrentBandIndex();\n}\n\nvoid SI_init() {\n    SI_run = true;\n    BK4819_ToggleGpioOut(BK4819_GPIO6_PIN2_GREEN, false);\n    BK4819_Disable();\n\n\n    SI47XX_PowerUp();\n\n    SI47XX_SetAutomaticGainControl(att > 0, att);\n}\n\n\nstatic bool seeking = false;\nstatic uint8_t seeking_way = 0;\n\n\nstatic void resetBFO() {\n        bfo = 0;\n        SI47XX_SetBFO(bfo);\n\n}\n\n\nvoid SI_deinit() {\n    SI47XX_PowerDown();\n    BK4819_RX_TurnOn();\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_AUDIO_PATH);\n#ifdef ENABLE_DOPPLER\n    SYSCON_DEV_CLK_GATE|=(1<<22);\n#endif\n}\n\nbool display_flag = 0;\nKeyboardState kbds = {KEY_INVALID, KEY_INVALID, 0};\n\n\nvoid SI4732_Display() {\n    UI_DisplayClear();\n\n    memset(gStatusLine, 0, sizeof(gStatusLine));\n    if (INPUT_STATE) {\n        UI_PrintStringSmall(freqInputString, 2, 127, 1);\n\n    } else {\n        uint8_t String[19];\n\n        //频率显示\n        uint32_t f = siCurrentFreq * divider;\n        uint16_t fp1 = f / 100000;\n        uint16_t fp2 = f / 100 % 1000;\n        sprintf(String, \"%3u.%03u\", fp1, fp2);\n        UI_DisplayFrequency(String, 64 - strlen(String) * 13 / 2, 2, false);\n        //模式显示\n        const uint8_t BASE = 38;\n        GUI_DisplaySmallest(SI47XX_MODE_NAMES[si4732mode], LCD_WIDTH - 12, BASE - 10 - 8, false, true);\n\n\n        if (SI47XX_IsSSB()) {\n            sprintf(String, \"%d\", bfo);\n            GUI_DisplaySmallest(String, LCD_WIDTH - strlen(String) * 4, BASE - 8, false, true);\n        }\n\n        if (si4732mode == SI47XX_FM) {\n            if (rds.RDSSignal) {\n                GUI_DisplaySmallest(\"RDS\", LCD_WIDTH - 12, 12 - 8, false, true);\n            }\n\n            char genre[17];\n            const char wd[8][3] = {\"SU\", \"MO\", \"TU\", \"WE\", \"TH\", \"FR\", \"SA\", \"SU\"};\n            SI47XX_GetProgramType(genre);\n\n            GUI_DisplaySmallest(genre, 64 - strlen(genre) * 2, 15 - 8, false, true);\n\n\n            if (SI47XX_GetLocalDateTime(&dt)) {\n                sprintf(String, \"%02u.%02u.%04u, %s %02u:%02u\", dt.day, dt.month, dt.year, wd[dt.wday], dt.hour,\n                        dt.minute);\n                GUI_DisplaySmallest(String, 64 - strlen(String) * 2, 22 - 8, false, true);\n\n            }\n            GUI_DisplaySmallest(rds.radioText, 0, LCD_HEIGHT - 8 - 8, false, true);\n        }\n\n        if (si4732mode == SI47XX_FM) {\n            sprintf(String, \"STP %u ATT %u\", step, att);\n        } else if (SI47XX_IsSSB()) {\n            sprintf(String, \"STP %u ATT %u BW %s\", step, att, SI47XX_SSB_BW_NAMES[ssbBw]);\n        } else {\n            sprintf(String, \"STP %u ATT %u BW %s\", step, att, SI47XX_BW_NAMES[bw]);\n        }\n        GUI_DisplaySmallest(String, 64 - strlen(String) * 2, BASE + 6 - 8, false, true);\n        if (si4732mode != SI47XX_FM) {\n            if (currentBandIndex >= 0) {\n                sprintf(String, \"%s %d - %dkHz\", bands[currentBandIndex].bandName, bands[currentBandIndex].minimumFreq,\n                        bands[currentBandIndex].maximumFreq);\n                GUI_DisplaySmallest(String, 64 - strlen(String) * 2, LCD_HEIGHT - 5 - 9, false, true);\n            }\n        }\n        if (SNR_flag) {\n            uint8_t rssi = rsqStatus.resp.RSSI;\n            if (rssi > 64) {\n                rssi = 64;\n            }\n            for (int i = 0; i < rssi * 2; ++i) {\n                gFrameBuffer[0][i] |= 0b00111100;\n            }\n\n\n            sprintf(String, \"SNR %u\", rsqStatus.resp.SNR);\n\n            GUI_DisplaySmallest(String, 0, 15 - 8, false, true);\n        }\n\n    }\n\n    ST7565_BlitFullScreen();\n}\n\n\nstatic void OnKeyDownFreqInput(uint8_t key) {\n    switch (key) {\n        case KEY_0:\n        case KEY_1:\n        case KEY_2:\n        case KEY_3:\n        case KEY_4:\n        case KEY_5:\n        case KEY_6:\n        case KEY_7:\n        case KEY_8:\n        case KEY_9:\n        case KEY_STAR:\n            UpdateFreqInput(key);\n            break;\n        case KEY_EXIT:\n            if (freqInputIndex == 0) {\n                INPUT_STATE = false;\n                break;\n            }\n            UpdateFreqInput(key);\n\n            break;\n        case KEY_MENU:\n            if (!FreqCheck(tempFreq)) {\n                break;\n            }\n            INPUT_STATE = false;\n            tune(tempFreq);\n            resetBFO();\n\n            break;\n        default:\n            break;\n    }\n}\n\n\nvoid HandleUserInput() {\n    kbds.prev = kbds.current;\n    kbds.current = GetKey();\n    bool KEY_TYPE1 = false, KEY_TYPE2 = false, KEY_TYPE3 = false;\n    // 无按键\n    if (kbds.current == KEY_INVALID) {\n        if (kbds.counter > 2 && kbds.counter <= 6) {\n            // 短按松手\n            KEY_TYPE3 = true;\n        }\n        kbds.counter = 0;\n    } else {\n        if (kbds.counter >= 6 && kbds.counter % 2 == 1) {\n            KEY_TYPE1 = true;\n        }\n        if (kbds.current == kbds.prev) {\n            // 持续按下\n            if (kbds.counter <= 14) {\n\n                KEY_TYPE2 = true;\n                kbds.counter++;\n            }\n        } else {\n            // 按键变化，重置计数器\n            kbds.counter = 1;\n        }\n        SYSTEM_DelayMs(20);\n    }\n\n    if (KEY_TYPE1 || KEY_TYPE2 || KEY_TYPE3) {\n        light_open();\n        display_flag = 1;\n    }\n     SI_key(kbds.current, KEY_TYPE1, KEY_TYPE2, KEY_TYPE3, kbds.prev);\n\n}\n\nvoid SI_key(KEY_Code_t key, bool KEY_TYPE1, bool KEY_TYPE2, bool KEY_TYPE3, KEY_Code_t key_prev) {\n    // up-down keys\n    if (INPUT_STATE && KEY_TYPE3) {\n        OnKeyDownFreqInput(key_prev);\n        return ;\n    }\n    if (KEY_TYPE1 || KEY_TYPE3) {\n        if (KEY_TYPE3)key = key_prev;\n        switch (key) {\n            case KEY_UP:\n            case KEY_DOWN:\n                tune((siCurrentFreq + (key == KEY_UP ? step : -step)) * divider);\n                resetBFO();\n                return ;\n#ifdef ENABLE_4732SSB\n                case KEY_SIDE1:\n                case KEY_SIDE2:\n                    if (SI47XX_IsSSB()) {\n                        if (key == KEY_SIDE1 ? (bfo < INT16_MAX - 10) : (bfo > INT16_MIN + 10)) {\n                            bfo = bfo + (key == KEY_SIDE1 ? 10 : -10);\n                        }\n                        SI47XX_SetBFO(bfo);\n                    }\n                    return ;\n\n#endif\n            case KEY_2:\n            case KEY_8:\n                if (key == KEY_2 ? att < 37 : att > 0) {\n                    key == KEY_2 ? att++ : att--;\n                    SI47XX_SetAutomaticGainControl(key == KEY_2 ? 1 : att > 0, att);\n                }\n                return ;\n\n            default:\n                break;\n        }\n    }\n\n    // Simple keypress\n    if (KEY_TYPE3) {\n\n        switch (key_prev) {\n            case KEY_4:\n                SNR_flag = !SNR_flag;\n                return ;\n            case KEY_1:\n                if (step < 1000) {\n                    if (step == 1 || step == 10 || step == 100 ) {\n                        step *= 5;\n                    } else {\n                        step *= 2;\n                    }\n                }\n                return ;\n\n\n            case KEY_7:\n                if (step > 1) {\n                    if ( step == 10 || step == 100 || step == 1000) {\n                        step /= 2;\n                    } else {\n                        step /= 5;\n                    }\n                }\n                return ;\n\n            case KEY_6:\n#ifdef ENABLE_4732SSB\n\n                if (SI47XX_IsSSB()) {\n                                    if (ssbBw == SI47XX_SSB_BW_1_0_kHz) {\n                                        ssbBw = SI47XX_SSB_BW_1_2_kHz;\n                                    } else {\n                                        ssbBw++;\n                                    }\n                                    SI47XX_SetSsbBandwidth(ssbBw);\n                                } else {\n#endif\n                if (bw == SI47XX_BW_1_kHz) {\n                    bw = SI47XX_BW_6_kHz;\n                } else {\n                    bw++;\n                }\n                SI47XX_SetBandwidth(bw, true);\n#ifdef ENABLE_4732SSB\n\n                }\n#endif\n\n                return ;\n\n            case KEY_5:\n                INPUT_STATE = 1;\n                FreqInput();\n                return ;\n            case KEY_0:\n                divider = 100;\n                WaitDisplay();\n                if (si4732mode == SI47XX_FM) {\n                    SI47XX_SwitchMode(SI47XX_AM);\n                    SI47XX_SetBandwidth(bw, true);\n//                    tune(720000);\n                    step = 5;\n                }\n#ifdef ENABLE_4732SSB\n\n\n                    else if (si4732mode == SI47XX_AM) {\n\n                        SI47XX_SwitchMode(SI47XX_LSB);\n                        SI47XX_SetSsbBandwidth(ssbBw);\n    //                    tune(711300);\n                        step = 1;\n                    }\n#endif\n\n                else {\n                    divider = 1000;\n                    SI47XX_SwitchMode(SI47XX_FM);\n//                    tune(10000000);\n                    step = 10;\n                }\n                tune(Read_FreqSaved());\n                resetBFO();\n                return ;\n#ifdef ENABLE_4732SSB\n\n                case KEY_F:\n                    if (SI47XX_IsSSB()) {\n                        uint32_t tmpF;\n                        SI47XX_SwitchMode(si4732mode == SI47XX_LSB ? SI47XX_USB : SI47XX_LSB);\n                        tune(Read_FreqSaved()); // to apply SSB\n                        return ;\n                    }\n#endif\n\n            case KEY_EXIT:\n                if (seeking) {\n                    SI47XX_PowerDown();\n                    SI47XX_PowerUp();\n                    seeking = false;\n                } else SI_run = false;\n                return ;\n            case KEY_3:\n            case KEY_9:\n#ifdef ENABLE_4732SSB\n\n                if (SI47XX_IsSSB()) {\n                                    return ;\n                                }\n#endif\n                if (si4732mode == SI47XX_FM) {\n                    SI47XX_SetSeekFmSpacing(step);\n                } else {\n                    SI47XX_SetSeekAmSpacing(step);\n                }\n\n                SI47XX_Seek(key == KEY_3 ? 1 : 0, 1);\n                if (key == KEY_3)seeking_way = 1;\n                else seeking_way = 0;\n\n\n                seeking = true;\n                return ;\n            default:\n                break;\n        }\n    }\n    return ;\n}\n\n\nvoid SI4732_Main() {\n#ifdef ENABLE_DOPPLER\n    SYSCON_DEV_CLK_GATE= SYSCON_DEV_CLK_GATE & ( ~(1 << 22));\n#endif\n\n    light_open();\n    SI_init();\n\n    uint16_t cnt = 500;\n    while (SI_run) {\n        if (light_time && gEeprom.BACKLIGHT_TIME != 7) {\n            light_time--;\n            if (light_time == 0)BACKLIGHT_TurnOff();\n        }\n        if (cnt == 500) {\n            DrawPower();\n            ST7565_BlitStatusLine();\n            cnt = 0;\n\n            if (si4732mode == SI47XX_FM) {\n                if (SI47XX_GetRDS()) display_flag = 1;\n            }\n            if (SNR_flag) {\n                RSQ_GET();\n                display_flag = 1;\n            }\n        }\n\n        if (cnt % 25 == 0) {\n          HandleUserInput();\n        }\n\n        if (seeking && cnt % 100 == 0) {\n            UI_PrintStringSmallBuffer(\"*\", gStatusLine);\n            bool valid = false;\n            siCurrentFreq = SI47XX_getFrequency(&valid);\n            uint32_t f = siCurrentFreq * divider;\n            EEPROM_WriteBuffer(SI4732_FREQ_ADD + si4732mode * 4, (uint8_t * ) & f, 4);\n\n            if (valid) {\n                seeking = false;\n                light_open();\n                tune((siCurrentFreq) * divider);\n            }\n\n            display_flag = 1;\n        }\n        cnt++;\n        if (display_flag) {\n            display_flag = 0;\n            SI4732_Display();\n        }\n        SYSTEM_DelayMs(1);\n    }\n    SI_deinit();\n\n}\n"
  },
  {
    "path": "app/si.h",
    "content": "#ifndef APP_SI_H\n#define APP_SI_H\n#include \"spectrum.h\"\n\n#include \"../driver/keyboard.h\"\n#include <stdbool.h>\n#include <stdint.h>\n\nvoid SI_init();\nvoid SI_update();\nvoid SI_key(KEY_Code_t key, bool KEY_TYPE1, bool KEY_TYPE2, bool KEY_TYPE3,KEY_Code_t key_prev) ;\n\nvoid SI_render();\nvoid SI_deinit();\nvoid Key_FM(KeyboardState kbds) ;\nvoid HandleUserInput() ;\nvoid SI4732_Main();\n#endif /* end of include guard: APP_SI_H */\n"
  },
  {
    "path": "app/spectrum.c",
    "content": "/* Copyright 2023 fagci\r\n * https://github.com/fagci\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n//#define ENABLE_DOPPLER\r\n\r\n#include \"functions.h\"\r\n#include \"stdbool.h\"\r\n\r\n#ifdef ENABLE_DOPPLER\r\n\r\n#include \"app/doppler.h\"\r\n#include \"bsp/dp32g030/rtc.h\"\r\n\r\n#endif\r\n\r\n#include \"app/spectrum.h\"\r\n#include \"am_fix.h\"\r\n#include \"audio.h\"\r\n#include \"misc.h\"\r\n\r\n\r\n//#define ENABLE_DOPPLER\r\n#ifdef ENABLE_SCAN_RANGES\r\n#include \"chFrScanner.h\"\r\n#endif\r\n\r\n#include \"driver/eeprom.h\"\r\n\r\n#include \"driver/backlight.h\"\r\n#include \"frequencies.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/main.h\"\r\n\r\nstatic void ToggleRX(bool on);\r\n\r\nstruct FrequencyBandInfo {\r\n    uint32_t lower;\r\n    uint32_t upper;\r\n    uint32_t middle;\r\n};\r\n\r\nint Mid(uint16_t *array, uint8_t n) {\r\n    int32_t sum = 0;\r\n    for (int i = 0; i < n; ++i) {\r\n        sum += array[i];\r\n    }\r\n    return sum / n;\r\n}\r\n//\r\n//static void UpdateBatteryInfo() {\r\n//    for (uint8_t i = 0; i < 4; i++) {\r\n//        BOARD_ADC_GetBatteryInfo(&gBatteryVoltages[i], &gBatteryCurrent);\r\n//    }\r\n//\r\n//    uint16_t voltage = Mid(gBatteryVoltages, ARRAY_SIZE(gBatteryVoltages));\r\n//    gBatteryDisplayLevel = 0;\r\n//\r\n//    for (int i = ARRAY_SIZE(gBatteryCalibration) - 1; i >= 0; --i) {\r\n//        if (gBatteryCalibration[i] < voltage) {\r\n//            gBatteryDisplayLevel = i + 1;\r\n//            break;\r\n//        }\r\n//    }\r\n//}\r\n\r\n#define F_MIN frequencyBandTable[0].lower\r\n#define F_MAX frequencyBandTable[BAND_N_ELEM - 1].upper\r\n\r\nconst uint16_t RSSI_MAX_VALUE = 65535;\r\nint32_t time_diff, time_diff1;\r\nstatic uint32_t initialFreq;\r\nstatic char String[32];\r\n#ifdef ENABLE_DOPPLER\r\nbool DOPPLER_MODE = 0;\r\n#endif\r\nbool TX_ON = false;\r\nbool isInitialized = false;\r\nbool isListening = true;\r\nbool monitorMode = false;\r\nbool redrawStatus = true;\r\nbool redrawScreen = false;\r\nbool newScanStart = true;\r\nbool preventKeypress = true;\r\nbool audioState = true;\r\nbool lockAGC = false;\r\n\r\nState currentState ,previousState ;\r\n\r\nPeakInfo peak;\r\nScanInfo scanInfo;\r\nKeyboardState kbd = {KEY_INVALID, KEY_INVALID, 0};\r\n\r\n#ifdef ENABLE_SCAN_RANGES\r\nstatic uint16_t blacklistFreqs[15];\r\nstatic uint8_t blacklistFreqsIdx;\r\n#endif\r\n\r\nconst char *bwOptions[] = {\"  25k\", \"12.5k\", \"6.25k\"};\r\nconst uint8_t modulationTypeTuneSteps[] = {100, 50, 10};\r\nconst uint8_t modTypeReg47Values[] = {1, 7, 5};\r\n\r\nSpectrumSettings settings = {.stepsCount = STEPS_64,\r\n        .scanStepIndex = S_STEP_25_0kHz,\r\n        .frequencyChangeStep = 80000,\r\n        .scanDelay = 3200,\r\n        .rssiTriggerLevel = 150,\r\n        .backlightState = true,\r\n        .bw = BK4819_FILTER_BW_WIDE,\r\n        .listenBw = BK4819_FILTER_BW_WIDE,\r\n        .modulationType = false,\r\n        .dbMin = -130,\r\n        .dbMax = -50\r\n};\r\n\r\nuint32_t fMeasure = 0;\r\nuint32_t currentFreq, tempFreq;\r\nuint16_t rssiHistory[128];\r\nint vfo;\r\nuint8_t freqInputIndex = 0;\r\nuint8_t freqInputDotIndex = 0;\r\nKEY_Code_t freqInputArr[10];\r\nchar freqInputString[11];\r\n\r\nuint8_t menuState = 0;\r\nuint16_t listenT = 0;\r\n\r\nRegisterSpec registerSpecs[] = {\r\n        {},\r\n        {\"LNAs\", BK4819_REG_13, 8, 0b11,   1},\r\n        {\"LNA\",  BK4819_REG_13, 5, 0b111,  1},\r\n        {\"PGA\",  BK4819_REG_13, 0, 0b111,  1},\r\n        {\"IF\",   BK4819_REG_3D, 0, 0xFFFF, 0x2aaa},\r\n        // {\"MIX\", 0x13, 3, 0b11, 1}, // '\r\n};\r\n\r\nuint16_t statuslineUpdateTimer = 0;\r\nVfoState_t txAllowState;\r\nbool isTransmitting = false;\r\n\r\nstatic uint8_t DBm2S(int dbm) {\r\n    uint8_t i = 0;\r\n    dbm *= -1;\r\n    for (i = 0; i < ARRAY_SIZE(U8RssiMap); i++) {\r\n        if (dbm >= U8RssiMap[i]) {\r\n            return i;\r\n        }\r\n    }\r\n    return i;\r\n}\r\n\r\nuint16_t registersVault[128] = {0};\r\n#ifdef ENABLE_DOPPLER\r\n\r\nstatic void RegBackup() {\r\n    for (int i = 0; i < 128; ++i) {\r\n        registersVault[i] = BK4819_ReadRegister(i);\r\n\r\n    }\r\n}\r\n#endif\r\n#ifdef ENABLE_DOPPLER\r\nstatic void RegRestore() {\r\n    for (int i = 0; i < 128; ++i) {\r\n        BK4819_WriteRegister(i, registersVault[i]);\r\n    }\r\n}\r\n#endif\r\nstatic void ToggleAudio(bool on) {\r\n//    if (on == audioState) {\r\n//        return;\r\n//    }\r\n//    audioState = on;\r\n    if (on) {\r\n        AUDIO_AudioPathOn();\r\n    } else {\r\n        AUDIO_AudioPathOff();\r\n    }\r\n}\r\n\r\nvoid SetTxF(uint32_t f, bool precise) {\r\n    BK4819_PickRXFilterPathBasedOnFrequency(f);\r\n    BK4819_SetFrequency(f);\r\n    uint16_t reg = BK4819_ReadRegister(BK4819_REG_30);\r\n    if (precise) {\r\n        BK4819_WriteRegister(BK4819_REG_30, 0x0200); // from radtel-rt-890-oefw\r\n    } else {\r\n        BK4819_WriteRegister(BK4819_REG_30, reg & ~BK4819_REG_30_ENABLE_VCO_CALIB);\r\n    }\r\n    BK4819_WriteRegister(BK4819_REG_30, reg);\r\n}\r\n\r\n#ifdef ENABLE_DOPPLER\r\nstatic void ToggleTX(bool on) {\r\n    if (isTransmitting == on) {\r\n        return;\r\n    }\r\n    isTransmitting = on;\r\n    if (on) {\r\n        ToggleRX(false);\r\n    }\r\n\r\n    BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, on);\r\n\r\n    if (on) {\r\n        TX_ON=1;\r\n        fMeasure = satellite_data.UPLink;\r\n\r\n        AUDIO_AudioPathOff();\r\n\r\n        SetTxF(fMeasure, true);\r\n        RegBackup();\r\n\r\n        BK4819_WriteRegister(BK4819_REG_47, 0x6040);\r\n        BK4819_WriteRegister(BK4819_REG_7E, 0x302E);\r\n        BK4819_WriteRegister(BK4819_REG_50, 0x3B20);\r\n        BK4819_WriteRegister(BK4819_REG_37, 0x1D0F);\r\n        BK4819_WriteRegister(BK4819_REG_52, 0x028F);\r\n        BK4819_WriteRegister(BK4819_REG_30, 0x0000);\r\n        BK4819_WriteRegister(BK4819_REG_30, 0xC1FE);\r\n        BK4819_WriteRegister(BK4819_REG_51, 0x9033);\r\n\r\n        //亚音\r\n        if (satellite.SEND_CTCSS == 0)\r\n            BK4819_ExitSubAu();\r\n        else\r\n            BK4819_SetCTCSSFrequency(satellite.SEND_CTCSS);\r\n\r\n        //功率\r\n        FREQUENCY_Band_t Band = FREQUENCY_GetBand(fMeasure);\r\n        uint8_t Txp[3];\r\n        EEPROM_ReadBuffer(0x1ED0 + (Band * 16) + (OUTPUT_POWER_HIGH * 3), Txp, 3);\r\n        BK4819_SetupPowerAmplifier(Txp[2], fMeasure);\r\n\r\n\r\n#if defined(ENABLE_MESSENGER) || defined(ENABLE_MDC1200)\r\n        enable_msg_rx(false);\r\n#endif\r\n        //DTMF\r\n        BK4819_DisableDTMF();\r\n        //加密\r\n        BK4819_DisableScramble();\r\n    } else {\r\n        BK4819_GenTail(4); // CTC55\r\n        BK4819_WriteRegister(BK4819_REG_51, 0x904A);\r\n//        SYSTEM_DelayMs(200);\r\n        BK4819_SetupPowerAmplifier(0, 0);\r\n        RegRestore();\r\n//TODO:发射频率\r\n        fMeasure = satellite_data.DownLink;\r\n        SetTxF(fMeasure, true);\r\n                TX_ON=0;\r\n\r\n    }\r\n    BK4819_ToggleGpioOut(BK4819_GPIO0_PIN28_RX_ENABLE, !on);\r\n    BK4819_ToggleGpioOut(BK4819_GPIO1_PIN29_PA_ENABLE, on);\r\n}\r\n#endif\r\n\r\nstatic int Rssi2DBm(uint16_t rssi) {\r\n    return (rssi / 2) - 160 + dBmCorrTable[gRxVfo->Band];\r\n}\r\n\r\nstatic uint16_t GetRegMenuValue(uint8_t st) {\r\n    RegisterSpec s = registerSpecs[st];\r\n    return (BK4819_ReadRegister(s.num) >> s.offset) & s.mask;\r\n}\r\n\r\nvoid LockAGC() {\r\n    RADIO_SetupAGC(settings.modulationType == MODULATION_AM, lockAGC);\r\n    lockAGC = true;\r\n}\r\n\r\nstatic void SetRegMenuValue(uint8_t st, bool add) {\r\n    uint16_t v = GetRegMenuValue(st);\r\n    RegisterSpec s = registerSpecs[st];\r\n\r\n    if (s.num == BK4819_REG_13)\r\n        LockAGC();\r\n\r\n    uint16_t reg = BK4819_ReadRegister(s.num);\r\n    if (add && v <= s.mask - s.inc) {\r\n        v += s.inc;\r\n    } else if (!add && v >= 0 + s.inc) {\r\n        v -= s.inc;\r\n    }\r\n    // mask in spec\r\n    reg &= ~(s.mask << s.offset);\r\n    BK4819_WriteRegister(s.num, reg | (v << s.offset));\r\n    redrawScreen = true;\r\n}\r\n\r\n\r\n// Utility functions\r\n\r\n\r\nstatic int clamp(int v, int min, int max) {\r\n    return v <= min ? min : (v >= max ? max : v);\r\n}\r\n\r\nstatic uint8_t my_abs(signed v) { return v > 0 ? v : -v; }\r\n\r\nvoid SetState(State state) {\r\n    previousState = currentState;\r\n    currentState = state;\r\n    redrawScreen = true;\r\n    redrawStatus = true;\r\n}\r\n\r\n// Radio functions\r\n\r\nstatic void ToggleAFBit(bool on) {\r\n    uint16_t reg = BK4819_ReadRegister(BK4819_REG_47);\r\n    reg &= ~(1 << 8);\r\n    if (on)\r\n        reg |= on << 8;\r\n    BK4819_WriteRegister(BK4819_REG_47, reg);\r\n}\r\n\r\nstatic const BK4819_REGISTER_t registers_to_save[] = {\r\n//        BK4819_REG_30,\r\n//        BK4819_REG_37,\r\n//        BK4819_REG_3D,\r\n//        BK4819_REG_43,\r\n//        BK4819_REG_47,\r\n//        BK4819_REG_48,\r\n//        BK4819_REG_7E,\r\n\r\n        0x13, 0x30, 0x31, 0x37, 0x3D, 0x40, 0x43, 0x47, 0x48, 0x7D, 0x7E,\r\n\r\n};\r\n\r\nstatic uint16_t registers_stack[sizeof(registers_to_save)];\r\n\r\nstatic void BackupRegisters() {\r\n    for (uint32_t i = 0; i < ARRAY_SIZE(registers_to_save); i++) {\r\n        registers_stack[i] = BK4819_ReadRegister(registers_to_save[i]);\r\n    }\r\n}\r\n\r\nstatic void RestoreRegisters() {\r\n\r\n    for (uint32_t i = 0; i < ARRAY_SIZE(registers_to_save); i++) {\r\n        BK4819_WriteRegister(registers_to_save[i], registers_stack[i]);\r\n    }\r\n}\r\n\r\nstatic void ToggleAFDAC(bool on) {\r\n    uint32_t Reg = BK4819_ReadRegister(BK4819_REG_30);\r\n    Reg &= ~(1 << 9);\r\n    if (on)\r\n        Reg |= (1 << 9);\r\n    BK4819_WriteRegister(BK4819_REG_30, Reg);\r\n}\r\n\r\nstatic void SetF(uint32_t f) {\r\n    fMeasure = f;\r\n\r\n    BK4819_SetFrequency(fMeasure);\r\n    BK4819_PickRXFilterPathBasedOnFrequency(fMeasure);\r\n    uint16_t reg = BK4819_ReadRegister(BK4819_REG_30);\r\n    BK4819_WriteRegister(BK4819_REG_30, 0);\r\n    BK4819_WriteRegister(BK4819_REG_30, reg);\r\n\r\n\r\n}\r\n\r\n// Spectrum related\r\n\r\nbool IsPeakOverLevel() { return peak.rssi >= settings.rssiTriggerLevel; }\r\n\r\nstatic void ResetPeak() {\r\n    peak.t = 0;\r\n    peak.rssi = 0;\r\n}\r\n\r\nbool IsCenterMode() { return settings.scanStepIndex < S_STEP_2_5kHz; }\r\n\r\n// scan step in 0.01khz\r\nuint16_t GetScanStep() { return scanStepValues[settings.scanStepIndex]; }\r\n\r\nuint16_t GetStepsCount() {\r\n#ifdef ENABLE_SCAN_RANGES\r\n    if(gScanRangeStart) {\r\n        return (gScanRangeStop - gScanRangeStart) / GetScanStep();\r\n    }\r\n#endif\r\n    return 128 >> settings.stepsCount;\r\n}\r\n\r\nuint32_t GetBW() { return GetStepsCount() * GetScanStep(); }\r\n\r\nuint32_t GetFStart() {\r\n    return IsCenterMode() ? currentFreq - (GetBW() >> 1) : currentFreq;\r\n}\r\n\r\nuint32_t GetFEnd() { return currentFreq + GetBW(); }\r\n\r\nstatic void TuneToPeak() {\r\n    scanInfo.f = peak.f;\r\n    scanInfo.rssi = peak.rssi;\r\n    scanInfo.i = peak.i;\r\n    SetF(scanInfo.f);\r\n}\r\n\r\nstatic void DeInitSpectrum() {\r\n    SetF(initialFreq);\r\n    RestoreRegisters();\r\n    isInitialized = false;\r\n}\r\n\r\nstatic uint8_t GetBWRegValueForScan() {\r\n    return scanStepBWRegValues[settings.scanStepIndex];\r\n}\r\n\r\nstatic uint16_t GetRssi() {\r\n    // SYSTICK_DelayUs(800);\r\n    // testing autodelay based on Glitch value\r\n    while ((BK4819_ReadRegister(0x63) & 0b11111111) >= 255) {\r\n        SYSTICK_DelayUs(100);\r\n    }\r\n    uint16_t rssi = BK4819_GetRSSI();\r\n#ifdef ENABLE_AM_FIX\r\n    if(settings.modulationType==MODULATION_AM && gSetting_AM_fix)\r\n        rssi += AM_fix_get_gain_diff()*2;\r\n#endif\r\n    return rssi;\r\n}\r\n\r\nstatic void ToggleRX(bool on) {\r\n//    if(isTransmitting&&on)return;\r\n\r\n\r\n    isListening = on;\r\n#ifdef ENABLE_DOPPLER\r\n    if (DOPPLER_MODE && on) {\r\n        ToggleTX(false);\r\n    }\r\n\r\n#endif\r\n    RADIO_SetupAGC(on, lockAGC);\r\n    BK4819_ToggleGpioOut(BK4819_GPIO6_PIN2_GREEN, on);\r\n\r\n    ToggleAudio(on);\r\n    ToggleAFDAC(on);\r\n    ToggleAFBit(on);\r\n\r\n    if (on) {\r\n        listenT = 1000;\r\n        BK4819_WriteRegister(0x43, listenBWRegValues[settings.listenBw]);\r\n    } else {\r\n        BK4819_WriteRegister(0x43, GetBWRegValueForScan());\r\n    }\r\n}\r\n\r\n// Scan info\r\n\r\nstatic void ResetScanStats() {\r\n    scanInfo.rssi = 0;\r\n    scanInfo.rssiMax = 0;\r\n    scanInfo.iPeak = 0;\r\n    scanInfo.fPeak = 0;\r\n}\r\n\r\nstatic void InitScan() {\r\n    ResetScanStats();\r\n    scanInfo.i = 0;\r\n    scanInfo.f = GetFStart();\r\n\r\n    scanInfo.scanStep = GetScanStep();\r\n    scanInfo.measurementsCount = GetStepsCount();\r\n}\r\n\r\nstatic void ResetBlacklist() {\r\n    for (int i = 0; i < 128; ++i) {\r\n        if (rssiHistory[i] == RSSI_MAX_VALUE)\r\n            rssiHistory[i] = 0;\r\n    }\r\n#ifdef ENABLE_SCAN_RANGES\r\n    memset(blacklistFreqs, 0, sizeof(blacklistFreqs));\r\n    blacklistFreqsIdx = 0;\r\n#endif\r\n}\r\n\r\nstatic void RelaunchScan() {\r\n    InitScan();\r\n    ResetPeak();\r\n    ToggleRX(false);\r\n#ifdef SPECTRUM_AUTOMATIC_SQUELCH\r\n    settings.rssiTriggerLevel = RSSI_MAX_VALUE;\r\n#endif\r\n    preventKeypress = true;\r\n    scanInfo.rssiMin = RSSI_MAX_VALUE;\r\n}\r\n\r\nstatic void UpdateScanInfo() {\r\n    if (scanInfo.rssi > scanInfo.rssiMax) {\r\n        scanInfo.rssiMax = scanInfo.rssi;\r\n        scanInfo.fPeak = scanInfo.f;\r\n        scanInfo.iPeak = scanInfo.i;\r\n    }\r\n\r\n    if (scanInfo.rssi < scanInfo.rssiMin) {\r\n        scanInfo.rssiMin = scanInfo.rssi;\r\n        settings.dbMin = Rssi2DBm(scanInfo.rssiMin);\r\n        redrawStatus = true;\r\n    }\r\n}\r\n\r\nstatic void AutoTriggerLevel() {\r\n    if (settings.rssiTriggerLevel == RSSI_MAX_VALUE) {\r\n        settings.rssiTriggerLevel = clamp(scanInfo.rssiMax + 8, 0, RSSI_MAX_VALUE);\r\n    }\r\n}\r\n\r\nstatic void UpdatePeakInfoForce() {\r\n    peak.t = 0;\r\n    peak.rssi = scanInfo.rssiMax;\r\n    peak.f = scanInfo.fPeak;\r\n    peak.i = scanInfo.iPeak;\r\n    AutoTriggerLevel();\r\n}\r\n\r\nstatic void UpdatePeakInfo() {\r\n    if (peak.f == 0 || peak.t >= 1024 || peak.rssi < scanInfo.rssiMax)\r\n        UpdatePeakInfoForce();\r\n}\r\n\r\nstatic void SetRssiHistory(uint16_t idx, uint16_t rssi) {\r\n#ifdef ENABLE_SCAN_RANGES\r\n    if(scanInfo.measurementsCount > 128) {\r\n        uint8_t i = (uint32_t)ARRAY_SIZE(rssiHistory) * 1000 / scanInfo.measurementsCount * idx / 1000;\r\n        if(rssiHistory[i] < rssi || isListening)\r\n            rssiHistory[i] = rssi;\r\n        rssiHistory[(i+1)%128] = 0;\r\n        return;\r\n    }\r\n#endif\r\n    rssiHistory[idx] = rssi;\r\n}\r\n\r\nstatic void Measure() {\r\n    uint16_t rssi = scanInfo.rssi = GetRssi();\r\n    SetRssiHistory(scanInfo.i, rssi);\r\n}\r\n\r\n// Update things by keypress\r\n\r\nstatic uint16_t dbm2rssi(int dBm) {\r\n    return (dBm + 160 - dBmCorrTable[gRxVfo->Band]) * 2;\r\n}\r\n\r\nstatic void ClampRssiTriggerLevel() {\r\n    settings.rssiTriggerLevel =\r\n            clamp(settings.rssiTriggerLevel, dbm2rssi(settings.dbMin),\r\n                  dbm2rssi(settings.dbMax));\r\n}\r\n\r\nstatic void UpdateRssiTriggerLevel(bool inc) {\r\n    if (inc)\r\n        settings.rssiTriggerLevel += 2;\r\n    else\r\n        settings.rssiTriggerLevel -= 2;\r\n\r\n    ClampRssiTriggerLevel();\r\n\r\n    redrawScreen = true;\r\n    redrawStatus = true;\r\n}\r\n\r\nstatic void UpdateDBMax(bool inc) {\r\n    uint8_t tmp = 12;\r\n#ifdef ENBALE_DOPPLER\r\n    if(DOPPLER_MODE) tmp=10;\r\n#endif\r\n\r\n    if (inc && settings.dbMax < 10) {\r\n        settings.dbMax += 1;\r\n    } else if (!inc && settings.dbMax > tmp + settings.dbMin) {\r\n        settings.dbMax -= 1;\r\n    } else {\r\n        return;\r\n    }\r\n\r\n    ClampRssiTriggerLevel();\r\n    redrawStatus = true;\r\n    redrawScreen = true;\r\n    SYSTEM_DelayMs(20);\r\n}\r\n\r\nstatic void UpdateScanStep(bool inc) {\r\n    if (inc) {\r\n        settings.scanStepIndex = settings.scanStepIndex != S_STEP_100_0kHz ? settings.scanStepIndex + 1 : 0;\r\n    } else {\r\n        settings.scanStepIndex = settings.scanStepIndex != 0 ? settings.scanStepIndex - 1 : S_STEP_100_0kHz;\r\n    }\r\n\r\n    settings.frequencyChangeStep = GetBW() >> 1;\r\n    RelaunchScan();\r\n    ResetBlacklist();\r\n    redrawScreen = true;\r\n}\r\n\r\nstatic void UpdateCurrentFreq(bool inc) {\r\n    if (inc && currentFreq < F_MAX) {\r\n        currentFreq += settings.frequencyChangeStep;\r\n    } else if (!inc && currentFreq > F_MIN) {\r\n        currentFreq -= settings.frequencyChangeStep;\r\n    } else {\r\n        return;\r\n    }\r\n    RelaunchScan();\r\n    ResetBlacklist();\r\n    redrawScreen = true;\r\n}\r\n\r\nstatic void UpdateCurrentFreqStill(bool inc) {\r\n    uint8_t offset = modulationTypeTuneSteps[settings.modulationType];\r\n    uint32_t f = fMeasure;\r\n    if (inc && f < F_MAX) {\r\n        f += offset;\r\n    } else if (!inc && f > F_MIN) {\r\n        f -= offset;\r\n    }\r\n    SetF(f);\r\n    redrawScreen = true;\r\n}\r\n\r\nstatic void UpdateFreqChangeStep(bool inc) {\r\n    uint16_t diff = GetScanStep() * 4;\r\n    if (inc && settings.frequencyChangeStep < 200000) {\r\n        settings.frequencyChangeStep += diff;\r\n    } else if (!inc && settings.frequencyChangeStep > 10000) {\r\n        settings.frequencyChangeStep -= diff;\r\n    }\r\n    SYSTEM_DelayMs(100);\r\n    redrawScreen = true;\r\n}\r\n\r\nstatic void ToggleModulation() {\r\n    if (settings.modulationType < MODULATION_UKNOWN - 1) {\r\n        settings.modulationType++;\r\n    } else {\r\n        settings.modulationType = MODULATION_FM;\r\n    }\r\n    RADIO_SetModulation(settings.modulationType);\r\n\r\n    RelaunchScan();\r\n    redrawScreen = true;\r\n#ifdef ENABLE_DOPPLER\r\n    if (DOPPLER_MODE) redrawStatus = true;\r\n#endif\r\n}\r\n\r\nstatic void ToggleListeningBW() {\r\n    if (settings.listenBw == BK4819_FILTER_BW_NARROWER) {\r\n        settings.listenBw = BK4819_FILTER_BW_WIDE;\r\n    } else {\r\n        settings.listenBw++;\r\n    }\r\n    redrawScreen = true;\r\n#ifdef ENABLE_DOPPLER\r\n    if (DOPPLER_MODE) redrawStatus = true;\r\n#endif\r\n}\r\n\r\nstatic void ToggleBacklight() {\r\n    settings.backlightState = !settings.backlightState;\r\n    if (settings.backlightState) {\r\n        BACKLIGHT_TurnOn();\r\n    } else {\r\n        BACKLIGHT_TurnOff();\r\n    }\r\n}\r\n\r\nstatic void ToggleStepsCount() {\r\n    if (settings.stepsCount == STEPS_128) {\r\n        settings.stepsCount = STEPS_16;\r\n    } else {\r\n        settings.stepsCount--;\r\n    }\r\n    settings.frequencyChangeStep = GetBW() >> 1;\r\n    RelaunchScan();\r\n    ResetBlacklist();\r\n    redrawScreen = true;\r\n}\r\n\r\n void ResetFreqInput() {\r\n    tempFreq = 0;\r\n    for (int i = 0; i < 10; ++i) {\r\n        freqInputString[i] = '-';\r\n    }\r\n}\r\n\r\n void FreqInput() {\r\n    freqInputIndex = 0;\r\n    freqInputDotIndex = 0;\r\n    ResetFreqInput();\r\n    SetState(FREQ_INPUT);\r\n}\r\n\r\n\r\n void UpdateFreqInput(KEY_Code_t key) {\r\n    if (key != KEY_EXIT && freqInputIndex >= 10) {\r\n        return;\r\n    }\r\n    if (key == KEY_STAR) {\r\n        if (freqInputIndex == 0 || freqInputDotIndex) {\r\n            return;\r\n        }\r\n        freqInputDotIndex = freqInputIndex;\r\n    }\r\n    if (key == KEY_EXIT) {\r\n        freqInputIndex--;\r\n        if (freqInputDotIndex == freqInputIndex)\r\n            freqInputDotIndex = 0;\r\n    } else {\r\n        freqInputArr[freqInputIndex++] = key;\r\n    }\r\n\r\n    ResetFreqInput();\r\n\r\n    uint8_t dotIndex =\r\n            freqInputDotIndex == 0 ? freqInputIndex : freqInputDotIndex;\r\n\r\n    KEY_Code_t digitKey;\r\n    for (int i = 0; i < 10; ++i) {\r\n        if (i < freqInputIndex) {\r\n            digitKey = freqInputArr[i];\r\n            freqInputString[i] = digitKey <= KEY_9 ? '0' + digitKey : '.';\r\n        } else {\r\n            freqInputString[i] = '-';\r\n        }\r\n    }\r\n\r\n    uint32_t base = 100000; // 1MHz in BK units\r\n//#ifdef ENABLE_DOPPLER\r\n//    if(DOPPLER_MODE)base=1;\r\n//#endif\r\n    for (int i = dotIndex - 1; i >= 0; --i) {\r\n        tempFreq += (freqInputArr[i]) * base;\r\n        base *= 10;\r\n    }\r\n\r\n    base = 10000; // 0.1MHz in BK units\r\n    if (dotIndex < freqInputIndex) {\r\n        for (int i = dotIndex + 1; i < freqInputIndex; ++i) {\r\n            tempFreq += (freqInputArr[i]) * base;\r\n            base /= 10;\r\n        }\r\n    }\r\n    redrawScreen = true;\r\n}\r\n\r\nstatic void Blacklist() {\r\n#ifdef ENABLE_SCAN_RANGES\r\n    blacklistFreqs[blacklistFreqsIdx++ % ARRAY_SIZE(blacklistFreqs)] = peak.i;\r\n#endif\r\n\r\n    SetRssiHistory(peak.i, RSSI_MAX_VALUE);\r\n    ResetPeak();\r\n    ToggleRX(false);\r\n    ResetScanStats();\r\n}\r\n\r\n#ifdef ENABLE_SCAN_RANGES\r\nstatic bool IsBlacklisted(uint16_t idx)\r\n{\r\n    for(uint8_t i = 0; i < ARRAY_SIZE(blacklistFreqs); i++)\r\n        if(blacklistFreqs[i] == idx)\r\n            return true;\r\n    return false;\r\n}\r\n#endif\r\n\r\n// Draw things\r\n// applied x2 to prevent initial rounding\r\nstatic uint8_t Rssi2PX(uint16_t rssi, uint8_t pxMin, uint8_t pxMax) {\r\n    const int DB_MIN = settings.dbMin << 1;\r\n    const int DB_MAX = settings.dbMax << 1;\r\n    const int DB_RANGE = DB_MAX - DB_MIN;\r\n\r\n    const uint8_t PX_RANGE = pxMax - pxMin;\r\n\r\n    int dbm = clamp(Rssi2DBm(rssi) << 1, DB_MIN, DB_MAX);\r\n\r\n//    return ((dbm - DB_MIN) * PX_RANGE + DB_RANGE / 2) / DB_RANGE + pxMin;\r\n    return (dbm - DB_MIN) * PX_RANGE / DB_RANGE + pxMin;\r\n}\r\n\r\nuint8_t Rssi2Y(uint16_t rssi) {\r\n    return DrawingEndY - Rssi2PX(rssi, 0, DrawingEndY);\r\n}\r\n\r\nstatic void DrawSpectrum() {\r\n    for (uint8_t x = 0; x < 128; ++x) {\r\n        uint16_t rssi = rssiHistory[x >> settings.stepsCount];\r\n        if (rssi != RSSI_MAX_VALUE) {\r\n            DrawVLine(Rssi2Y(rssi), DrawingEndY, x, true);\r\n        }\r\n    }\r\n}\r\n\r\n  void DrawPower() {\r\n    BOARD_ADC_GetBatteryInfo(&gBatteryVoltages[gBatteryCheckCounter++ % 4],\r\n                             &gBatteryCurrent);\r\n\r\n    uint16_t voltage = (gBatteryVoltages[0] + gBatteryVoltages[1] +\r\n                        gBatteryVoltages[2] + gBatteryVoltages[3]) /\r\n                       4 * 760 / gBatteryCalibration[3];\r\n\r\n    unsigned perc = BATTERY_VoltsToPercent(voltage);\r\n\r\n    // sprintf(String, \"%d %d\", voltage, perc);\r\n    // GUI_DisplaySmallest(String, 48, 1, true, true);\r\n\r\n    gStatusLine[116] = 0b00011100;\r\n    gStatusLine[117] = 0b00111110;\r\n    for (int i = 118; i <= 126; i++) {\r\n        gStatusLine[i] = 0b00100010;\r\n    }\r\n\r\n    for (unsigned i = 127; i >= 118; i--) {\r\n        if (127 - i <= (perc + 5) * 9 / 100) {\r\n            gStatusLine[i] = 0b00111110;\r\n        }\r\n    }\r\n}\r\n\r\nstatic void DrawStatus() {\r\n\r\n#ifdef SPECTRUM_EXTRA_VALUES\r\n    sprintf(String, \"%d/%d P:%d T:%d\", settings.dbMin, settings.dbMax,\r\n          Rssi2DBm(peak.rssi), Rssi2DBm(settings.rssiTriggerLevel));\r\n#else\r\n    sprintf(String, \"%d/%d\", settings.dbMin, settings.dbMax);\r\n#endif\r\n#ifdef ENABLE_DOPPLER\r\n\r\n    if (DOPPLER_MODE) {\r\n        //UI绘制状态栏\r\n        memset(gStatusLine, 0x7f, 39);\r\n        GUI_DisplaySmallest(satellite.name, 2, 1, true, false);\r\n        GUI_DisplaySmallest(String, 42 + (settings.dbMax > -100 ? 4 : 0), 1, true, true);\r\n\r\n        sprintf(String, \"%3s\", gModulationStr[settings.modulationType]);\r\n        GUI_DisplaySmallest(String, 42 + 38, 1, true, true);\r\n\r\n        sprintf(String, \"%s\", bwOptions[settings.listenBw]);\r\n        GUI_DisplaySmallest(String, 42 + 53 - (settings.listenBw == 0 ? 8 : 0), 1, true, true);\r\n    } else {\r\n#endif\r\n    GUI_DisplaySmallest(String, 0, 1, true, true);\r\n#ifdef ENABLE_DOPPLER\r\n    }\r\n#endif\r\n\r\n    DrawPower();\r\n\r\n}\r\n\r\nstatic void DrawF(uint32_t f) {\r\n#ifdef ENABLE_DOPPLER\r\n    if (DOPPLER_MODE) {\r\n        //UI绘制\r\n        sprintf(String, \"%03u.%05u\", f / 100000, f % 100000);\r\n\r\n        UI_DisplayFrequency(String, 8, 0, false);\r\n\r\n    } else {\r\n#endif\r\n    sprintf(String, \"%u.%05u\", f / 100000, f % 100000);\r\n    UI_PrintStringSmall(String, 8, 127, 0);\r\n\r\n\r\n    sprintf(String, \"%3s\", gModulationStr[settings.modulationType]);\r\n    GUI_DisplaySmallest(String, 116, 1, false, true);\r\n    sprintf(String, \"%s\", bwOptions[settings.listenBw]);\r\n    GUI_DisplaySmallest(String, 108, 7, false, true);\r\n#ifdef ENABLE_DOPPLER\r\n    }\r\n#endif\r\n\r\n}\r\n\r\nstatic void DrawNums() {\r\n\r\n    if (currentState == SPECTRUM) {\r\n        sprintf(String, \"%ux\", GetStepsCount());\r\n        GUI_DisplaySmallest(String, 0, 1, false, true);\r\n        sprintf(String, \"%u.%02uk\", GetScanStep() / 100, GetScanStep() % 100);\r\n        GUI_DisplaySmallest(String, 0, 7, false, true);\r\n    }\r\n\r\n    if (IsCenterMode()) {\r\n        sprintf(String, \"%u.%05u \\x7F%u.%02uk\", currentFreq / 100000,\r\n                currentFreq % 100000, settings.frequencyChangeStep / 100,\r\n                settings.frequencyChangeStep % 100);\r\n        GUI_DisplaySmallest(String, 36, 49, false, true);\r\n    } else {\r\n        sprintf(String, \"%u.%05u\", GetFStart() / 100000, GetFStart() % 100000);\r\n        GUI_DisplaySmallest(String, 0, 49, false, true);\r\n\r\n        sprintf(String, \"\\x7F%u.%02uk\", settings.frequencyChangeStep / 100,\r\n                settings.frequencyChangeStep % 100);\r\n        GUI_DisplaySmallest(String, 48, 49, false, true);\r\n\r\n        sprintf(String, \"%u.%05u\", GetFEnd() / 100000, GetFEnd() % 100000);\r\n        GUI_DisplaySmallest(String, 93, 49, false, true);\r\n    }\r\n}\r\n\r\nstatic void DrawRssiTriggerLevel() {\r\n    if (settings.rssiTriggerLevel == RSSI_MAX_VALUE || monitorMode)\r\n        return;\r\n    uint8_t y = Rssi2Y(settings.rssiTriggerLevel);\r\n    for (uint8_t x = 0; x < 128; x += 2) {\r\n        PutPixel(x, y, true);\r\n    }\r\n}\r\n\r\nstatic void DrawTicks() {\r\n    uint32_t f = GetFStart();\r\n    uint32_t span = GetFEnd() - GetFStart();\r\n    uint32_t step = span / 128;\r\n    for (uint8_t i = 0; i < 128; i += (1 << settings.stepsCount)) {\r\n        f = GetFStart() + span * i / 128;\r\n        uint8_t barValue = 0b00000001;\r\n        (f % 10000) < step && (barValue |= 0b00000010);\r\n        (f % 50000) < step && (barValue |= 0b00000100);\r\n        (f % 100000) < step && (barValue |= 0b00011000);\r\n\r\n        gFrameBuffer[5][i] |= barValue;\r\n    }\r\n\r\n    // center\r\n    if (IsCenterMode()) {\r\n        memset(gFrameBuffer[5] + 62, 0x80, 5);\r\n        gFrameBuffer[5][64] = 0xff;\r\n    } else {\r\n        memset(gFrameBuffer[5] + 1, 0x80, 3);\r\n        memset(gFrameBuffer[5] + 124, 0x80, 3);\r\n\r\n        gFrameBuffer[5][0] = 0xff;\r\n        gFrameBuffer[5][127] = 0xff;\r\n    }\r\n}\r\n\r\nstatic void DrawArrow(uint8_t x) {\r\n    for (signed i = -2; i <= 2; ++i) {\r\n        signed v = x + i;\r\n        if (!(v & 128)) {\r\n            gFrameBuffer[5][v] |= (0b01111000 << my_abs(i)) & 0b01111000;\r\n        }\r\n    }\r\n}\r\n\r\nstatic void OnKeyDown(uint8_t key) {\r\n    switch (key) {\r\n        case KEY_3:\r\n            UpdateDBMax(true);\r\n            break;\r\n        case KEY_9:\r\n            UpdateDBMax(false);\r\n            break;\r\n        case KEY_1:\r\n            UpdateScanStep(true);\r\n            break;\r\n        case KEY_7:\r\n            UpdateScanStep(false);\r\n            break;\r\n        case KEY_2:\r\n            UpdateFreqChangeStep(true);\r\n            break;\r\n        case KEY_8:\r\n            UpdateFreqChangeStep(false);\r\n            break;\r\n        case KEY_UP:\r\n#ifdef ENABLE_SCAN_RANGES\r\n            if(!gScanRangeStart)\r\n#endif\r\n                UpdateCurrentFreq(true);\r\n            break;\r\n        case KEY_DOWN:\r\n#ifdef ENABLE_SCAN_RANGES\r\n            if(!gScanRangeStart)\r\n#endif\r\n                UpdateCurrentFreq(false);\r\n            break;\r\n        case KEY_SIDE1:\r\n            Blacklist();\r\n            break;\r\n        case KEY_STAR:\r\n            UpdateRssiTriggerLevel(true);\r\n            break;\r\n        case KEY_F:\r\n            UpdateRssiTriggerLevel(false);\r\n            break;\r\n        case KEY_5:\r\n#ifdef ENABLE_SCAN_RANGES\r\n            if(!gScanRangeStart)\r\n\r\n#endif\r\n                FreqInput();\r\n\r\n\r\n            break;\r\n        case KEY_0:\r\n            ToggleModulation();\r\n            break;\r\n        case KEY_6:\r\n            ToggleListeningBW();\r\n            break;\r\n        case KEY_4:\r\n#ifdef ENABLE_SCAN_RANGES\r\n            if(!gScanRangeStart)\r\n#endif\r\n                ToggleStepsCount();\r\n            break;\r\n        case KEY_SIDE2:\r\n            ToggleBacklight();\r\n            break;\r\n        case KEY_PTT:\r\n            SetState(STILL);\r\n            TuneToPeak();\r\n            break;\r\n        case KEY_MENU:\r\n            break;\r\n        case KEY_EXIT:\r\n            if (menuState) {\r\n                menuState = 0;\r\n                break;\r\n            }\r\n            DeInitSpectrum();\r\n            break;\r\n        default:\r\n            break;\r\n    }\r\n}\r\n\r\nstatic void OnKeyDownFreqInput(uint8_t key) {\r\n    switch (key) {\r\n        case KEY_0:\r\n        case KEY_1:\r\n        case KEY_2:\r\n        case KEY_3:\r\n        case KEY_4:\r\n        case KEY_5:\r\n        case KEY_6:\r\n        case KEY_7:\r\n        case KEY_8:\r\n        case KEY_9:\r\n        case KEY_STAR:\r\n            UpdateFreqInput(key);\r\n            break;\r\n        case KEY_EXIT:\r\n            if (freqInputIndex == 0) {\r\n                SetState(previousState);\r\n                break;\r\n            }\r\n            UpdateFreqInput(key);\r\n            break;\r\n        case KEY_MENU:\r\n#ifdef ENABLE_DOPPLER\r\n            if(DOPPLER_MODE)\r\n           {\r\n\r\n\r\n        time[3]=tempFreq/100000;\r\n        time[4]=(tempFreq/1000)%100;\r\n        time[5]=(tempFreq/10)%100;\r\n                        RTC_Set();\r\n                     SetState(previousState);\r\n\r\n                break;\r\n               }\r\n#endif\r\n            if (tempFreq < F_MIN || tempFreq > F_MAX) {\r\n                break;\r\n            }\r\n            SetState(previousState);\r\n            currentFreq = tempFreq;\r\n            if (currentState == SPECTRUM) {\r\n                ResetBlacklist();\r\n                RelaunchScan();\r\n            } else {\r\n                SetF(currentFreq);\r\n            }\r\n            break;\r\n        default:\r\n            break;\r\n    }\r\n}\r\n\r\nvoid OnKeyDownStill(KEY_Code_t key) {\r\n    switch (key) {\r\n        case KEY_3:\r\n            UpdateDBMax(true);\r\n            break;\r\n        case KEY_9:\r\n            UpdateDBMax(false);\r\n            break;\r\n        case KEY_UP:\r\n            if (menuState) {\r\n                SetRegMenuValue(menuState, true);\r\n                break;\r\n            }\r\n#ifdef ENABLE_DOPPLER\r\n            if (!DOPPLER_MODE)\r\n#endif\r\n            UpdateCurrentFreqStill(true);\r\n            break;\r\n        case KEY_DOWN:\r\n\r\n            if (menuState) {\r\n                SetRegMenuValue(menuState, false);\r\n                break;\r\n            }\r\n#ifdef ENABLE_DOPPLER\r\n            if (!DOPPLER_MODE)\r\n#endif\r\n            UpdateCurrentFreqStill(false);\r\n\r\n            break;\r\n        case KEY_STAR:\r\n            UpdateRssiTriggerLevel(true);\r\n            break;\r\n        case KEY_F:\r\n            UpdateRssiTriggerLevel(false);\r\n            break;\r\n        case KEY_5:\r\n//#ifdef ENABLE_DOPPLER\r\n//            if (DOPPLER_MODE) {\r\n//\r\n//\r\n//            } else\r\n//#endif\r\n\r\n\r\n            FreqInput();\r\n\r\n\r\n            break;\r\n        case KEY_0:\r\n#ifdef ENABLE_DOPPLER\r\n            if (!DOPPLER_MODE)\r\n#endif\r\n            ToggleModulation();\r\n            break;\r\n        case KEY_6:\r\n#ifdef ENABLE_DOPPLER\r\n            if (!DOPPLER_MODE)\r\n#endif\r\n            ToggleListeningBW();\r\n            break;\r\n        case KEY_SIDE1:\r\n            monitorMode = !monitorMode;\r\n            break;\r\n        case KEY_SIDE2:\r\n            ToggleBacklight();\r\n            break;\r\n        case KEY_PTT:\r\n#ifdef ENABLE_DOPPLER\r\n            if (DOPPLER_MODE) {\r\n                ToggleTX(true);\r\n                redrawScreen = true;\r\n            }\r\n#endif\r\n            break;\r\n        case KEY_MENU:\r\n            if (menuState == ARRAY_SIZE(registerSpecs) - 1) {\r\n                menuState = 1;\r\n            } else {\r\n                menuState++;\r\n            }\r\n            redrawScreen = true;\r\n            break;\r\n        case KEY_EXIT:\r\n            if (!menuState) {\r\n                SetState(SPECTRUM);\r\n                lockAGC = false;\r\n                monitorMode = false;\r\n                RelaunchScan();\r\n\r\n#ifdef ENABLE_DOPPLER\r\n                if (DOPPLER_MODE)DeInitSpectrum();\r\n#endif\r\n\r\n\r\n                break;\r\n            }\r\n            menuState = 0;\r\n            break;\r\n\r\n        default:\r\n\r\n\r\n            break;\r\n    }\r\n}\r\n\r\n void RenderFreqInput() {\r\n    UI_PrintStringSmall(freqInputString, 2, 127, 0);\r\n//    show_uint32(tempFreq,3);\r\n}\r\n\r\nstatic void UpdateStill() {\r\n    if (TX_ON)return;\r\n    Measure();\r\n    redrawScreen = true;\r\n    preventKeypress = false;\r\n\r\n    peak.rssi = scanInfo.rssi;\r\n    AutoTriggerLevel();\r\n\r\n    ToggleRX((IsPeakOverLevel() || monitorMode));\r\n}\r\n\r\nstatic void RenderStatus() {\r\n\r\n    memset(gStatusLine, 0, sizeof(gStatusLine));\r\n    DrawStatus();\r\n    ST7565_BlitStatusLine();\r\n}\r\n\r\nstatic void RenderSpectrum() {\r\n    DrawTicks();\r\n    DrawArrow(128u * peak.i / GetStepsCount());\r\n    DrawSpectrum();\r\n    DrawRssiTriggerLevel();\r\n    DrawF(peak.f);\r\n    DrawNums();\r\n}\r\n\r\n#ifdef ENABLE_DOPPLER\r\n\r\nstatic void Draw_DOPPLER_Process(uint8_t DATA_LINE) {\r\n    int process = 0;\r\n    if (time_diff > 0)//还没来卫星\r\n    {\r\n        if (time_diff > 1000)//还早\r\n        {\r\n            strcpy(String, \"Long\");\r\n\r\n        } else//1000s以内\r\n        {\r\n            sprintf(String, \"-%4d sec\", time_diff);\r\n            process = time_diff * 45 / 1000;\r\n        }\r\n    } else { //已经来了\r\n        if (time_diff1 >= 0)//正在过境\r\n        {\r\n            sprintf(String, \"+%4d sec\", satellite.sum_time + time_diff);\r\n            process = 45 - (satellite.sum_time + time_diff) * 45 / satellite.sum_time;\r\n        } else {\r\n\r\n            strcpy(String, \"Passed\");\r\n        }\r\n    }\r\n    GUI_DisplaySmallest(String, 85, DATA_LINE + 15, false, true);\r\n    memset(&gFrameBuffer[6][80], 0b01000000, 45);\r\n    gFrameBuffer[6][79] = 0b00111110;\r\n    gFrameBuffer[6][45 + 80] = 0b00111110;\r\n    for (int i = 0; i < 45; i++) {\r\n        if (i < process)\r\n            gFrameBuffer[6][i + 80] = 0b00111110;\r\n        else\r\n            gFrameBuffer[6][i + 80] = 0b00100010;\r\n    }\r\n    sprintf(String, \"20%02d-%02d-%02d %02d:%02d:%02d\", time[0], time[1], time[2], time[3], time[4], time[5]);\r\n    GUI_DisplaySmallest(String, 1, DATA_LINE + 23, false, true);\r\n}\r\n\r\n#endif\r\n\r\nstatic void RenderStill() {\r\n    DrawF(fMeasure);//绘制频率\r\n    uint8_t METER_PAD_LEFT = 3;\r\n    uint8_t P_WIDTH = 120;\r\n    uint8_t S_LINE = 25;\r\n    uint8_t S_X = 4;\r\n    uint8_t DBM_X = 22;\r\n#ifdef ENABLE_DOPPLER\r\n    if (DOPPLER_MODE) {\r\n        P_WIDTH = 50;\r\n        METER_PAD_LEFT = 70;\r\n        S_LINE = 18;\r\n        S_X = 58;\r\n        DBM_X = 6;\r\n    }\r\n#endif\r\n    memset(&gFrameBuffer[2][METER_PAD_LEFT], 0b01000000, P_WIDTH);\r\n\r\n    for (int i = 0; i <= P_WIDTH; i += 5) { //小刻度\r\n        gFrameBuffer[2][i + METER_PAD_LEFT] = 0b01100000;\r\n\r\n    }\r\n    uint8_t x = Rssi2PX(scanInfo.rssi, 0, P_WIDTH);//信号强度\r\n    for (int i = 0; i < x; i++) {\r\n        if (i % 5) {\r\n            gFrameBuffer[2][i + METER_PAD_LEFT] |= 0b00001110;\r\n        }\r\n    }\r\n\r\n//S表参数绘制\r\n    int dbm = Rssi2DBm(scanInfo.rssi);\r\n    uint8_t s = DBm2S(dbm);\r\n    bool fill = true;\r\n#ifdef ENABLE_DOPPLER\r\n    if ((monitorMode || IsPeakOverLevel()) && DOPPLER_MODE) {\r\n        memset(gFrameBuffer[2] + DBM_X - 2, 0b11111110, 51);\r\n        fill = false;\r\n    }\r\n#endif\r\n    sprintf(String, \"S%u\", s);\r\n    GUI_DisplaySmallest(String, S_X, S_LINE, false, true);\r\n    sprintf(String, \"%4d/%4ddBm\", dbm, Rssi2DBm(settings.rssiTriggerLevel));\r\n    GUI_DisplaySmallest(String, DBM_X, S_LINE, false, fill);\r\n\r\n    if (!monitorMode) {\r\n        uint8_t x = Rssi2PX(settings.rssiTriggerLevel, 0, P_WIDTH);\r\n        gFrameBuffer[2][METER_PAD_LEFT + x] = 0b11111111;\r\n    }\r\n    //增益参数\r\n    const uint8_t PAD_LEFT = 4;\r\n    const uint8_t CELL_WIDTH = 30;\r\n    uint8_t offset = PAD_LEFT;\r\n    uint8_t row = 4;\r\n    uint8_t DATA_LINE;\r\n    uint8_t SHOW_LINE=4;\r\n#ifdef ENABLE_DOPPLER\r\n    if (DOPPLER_MODE)SHOW_LINE = 3;\r\n#endif\r\n    for (int i = 0, idx = 1; idx <= 4; ++i, ++idx) {\r\n//        if (idx == 5) {\r\n//            row += 2;\r\n//            i = 0;\r\n//        }\r\n        offset = PAD_LEFT + i * CELL_WIDTH;\r\n        if (menuState == idx) {\r\n            for (int j = 0; j < CELL_WIDTH; ++j) {\r\n                gFrameBuffer[SHOW_LINE][j + offset] = 0xFF;\r\n                gFrameBuffer[SHOW_LINE + 1][j + offset] = 0xFF;\r\n            }\r\n        }\r\n        DATA_LINE = row * 8 + 2;\r\n#ifdef ENABLE_DOPPLER\r\n        if (DOPPLER_MODE)DATA_LINE -= 8;\r\n#endif\r\n        sprintf(String, \"%s\", registerSpecs[idx].name);\r\n        GUI_DisplaySmallest(String, offset + 2, DATA_LINE, false,\r\n                            menuState != idx);\r\n        sprintf(String, \"%u\", GetRegMenuValue(idx));\r\n        GUI_DisplaySmallest(String, offset + 2, DATA_LINE + 7, false,\r\n                            menuState != idx);\r\n    }\r\n#ifdef ENABLE_DOPPLER\r\n\r\n    if (DOPPLER_MODE) {\r\n        Draw_DOPPLER_Process(26);\r\n        bool flag = true;\r\n        if (!isTransmitting)\r\n            sprintf(String, \"UPLink:%4d.%05d\", satellite_data.UPLink / 100000, satellite_data.UPLink % 100000);\r\n        else {\r\n            memset(gFrameBuffer[5], 0x7f, 77);\r\n            flag = false;\r\n            sprintf(String, \"DownLink:%4d.%05d\", satellite_data.DownLink / 100000, satellite_data.DownLink % 100000);\r\n        }\r\n        GUI_DisplaySmallest(String, 1, DATA_LINE + 15, false, flag);\r\n\r\n    }\r\n#endif\r\n}\r\n\r\nstatic void Render() {\r\n    UI_DisplayClear();\r\n    switch (currentState) {\r\n        case SPECTRUM:\r\n            RenderSpectrum();\r\n            break;\r\n        case FREQ_INPUT:\r\n            RenderFreqInput();\r\n            break;\r\n        case STILL:\r\n            RenderStill();\r\n            break;\r\n\r\n    }\r\n    ST7565_BlitFullScreen();\r\n}\r\n\r\nstatic void HandleUserInput() {\r\n    kbd.prev = kbd.current;\r\n    kbd.current = GetKey();\r\n    if (kbd.current == KEY_INVALID) {\r\n        kbd.counter = 0;\r\n#ifdef ENABLE_DOPPLER\r\n        if (DOPPLER_MODE && isTransmitting) {\r\n            ToggleTX(false);\r\n        }\r\n#endif\r\n//        return true;\r\n    }\r\n\r\n    if (kbd.current != KEY_INVALID && kbd.current == kbd.prev) {\r\n        if (kbd.counter < 16)\r\n            kbd.counter++;\r\n        else\r\n            kbd.counter -= 3;\r\n        SYSTEM_DelayMs(20);\r\n    } else {\r\n        kbd.counter = 0;\r\n    }\r\n\r\n\r\n    if (kbd.counter == 2 || kbd.counter == 16) {\r\n        switch (currentState) {\r\n            case SPECTRUM:\r\n                OnKeyDown(kbd.current);\r\n                break;\r\n            case FREQ_INPUT:\r\n                OnKeyDownFreqInput(kbd.current);\r\n                break;\r\n            case STILL:\r\n                OnKeyDownStill(kbd.current);\r\n                break;\r\n\r\n        }\r\n    }\r\n\r\n}\r\n\r\nstatic void Scan() {\r\n    if (rssiHistory[scanInfo.i] != RSSI_MAX_VALUE\r\n        #ifdef ENABLE_SCAN_RANGES\r\n        && !IsBlacklisted(scanInfo.i)\r\n#endif\r\n            ) {\r\n        SetF(scanInfo.f);\r\n        Measure();\r\n        UpdateScanInfo();\r\n    }\r\n}\r\n\r\nstatic void NextScanStep() {\r\n    ++peak.t;\r\n    ++scanInfo.i;\r\n    scanInfo.f += scanInfo.scanStep;\r\n}\r\n\r\nstatic void UpdateScan() {\r\n    Scan();\r\n\r\n    if (scanInfo.i < scanInfo.measurementsCount) {\r\n        NextScanStep();\r\n        return;\r\n    }\r\n\r\n    if (scanInfo.measurementsCount < 128)\r\n        memset(&rssiHistory[scanInfo.measurementsCount], 0,\r\n               sizeof(rssiHistory) - scanInfo.measurementsCount * sizeof(rssiHistory[0]));\r\n\r\n    redrawScreen = true;\r\n    preventKeypress = false;\r\n\r\n    UpdatePeakInfo();\r\n    if (IsPeakOverLevel()) {\r\n        ToggleRX(true);\r\n        TuneToPeak();\r\n        return;\r\n    }\r\n\r\n    newScanStart = true;\r\n}\r\n\r\n\r\nstatic void UpdateListening() {\r\n    preventKeypress = false;\r\n    if (currentState == STILL) {\r\n        listenT = 0;\r\n    }\r\n    if (listenT) {\r\n        listenT--;\r\n        SYSTEM_DelayMs(1);\r\n        return;\r\n    }\r\n\r\n    if (currentState == SPECTRUM) {\r\n        BK4819_WriteRegister(0x43, GetBWRegValueForScan());\r\n        Measure();\r\n        BK4819_WriteRegister(0x43, listenBWRegValues[settings.listenBw]);\r\n    } else {\r\n        Measure();\r\n    }\r\n\r\n    peak.rssi = scanInfo.rssi;\r\n    redrawScreen = true;\r\n\r\n    if (IsPeakOverLevel() || monitorMode) {\r\n        listenT = 1000;\r\n        return;\r\n    }\r\n\r\n    ToggleRX(false);\r\n    ResetScanStats();\r\n}\r\n\r\nstatic void Tick() {\r\n#ifdef ENABLE_AM_FIX\r\n    if (gNextTimeslice) {\r\n        gNextTimeslice = false;\r\n        if(settings.modulationType == MODULATION_AM && !lockAGC) {\r\n            AM_fix_10ms(vfo); //allow AM_Fix to apply its AGC action\r\n        }\r\n    }\r\n#endif\r\n\r\n#ifdef ENABLE_SCAN_RANGES\r\n    if (gNextTimeslice_500ms) {\r\n        gNextTimeslice_500ms = false;\r\n\r\n        // if a lot of steps then it takes long time\r\n        // we don't want to wait for whole scan\r\n        // listening has it's own timer\r\n        if(GetStepsCount()>128 && !isListening) {\r\n            UpdatePeakInfo();\r\n            if (IsPeakOverLevel()) {\r\n                ToggleRX(true);\r\n                TuneToPeak();\r\n                return;\r\n            }\r\n            redrawScreen = true;\r\n            preventKeypress = false;\r\n        }\r\n    }\r\n#endif\r\n\r\n    if (!preventKeypress) {\r\n        HandleUserInput();\r\n    }\r\n    if (newScanStart) {\r\n        InitScan();\r\n        newScanStart = false;\r\n    }\r\n    if (isListening && currentState != FREQ_INPUT) {\r\n        UpdateListening();\r\n    } else {\r\n        if (currentState == SPECTRUM) {\r\n            UpdateScan();\r\n        } else if (currentState == STILL) {\r\n            UpdateStill();\r\n        }\r\n\r\n\r\n    }\r\n\r\n\r\n    if (redrawStatus || ++statuslineUpdateTimer > 4096) {\r\n        RenderStatus();\r\n        redrawStatus = false;\r\n        statuslineUpdateTimer = 0;\r\n    }\r\n\r\n\r\n    if (redrawScreen) {\r\n        Render();\r\n        redrawScreen = false;\r\n    }\r\n}\r\n\r\n\r\n void APP_RunSpectrum() {\r\n    currentState = SPECTRUM;\r\n    previousState=SPECTRUM;\r\n    // TX here coz it always? set to active VFO\r\n    vfo = gEeprom.TX_VFO;\r\n    // set the current frequency in the middle of the display\r\n#ifdef ENABLE_SCAN_RANGES\r\n    if(gScanRangeStart) {\r\n        currentFreq = initialFreq = gScanRangeStart;\r\n        for(uint8_t i = 0; i < ARRAY_SIZE(scanStepValues); i++) {\r\n            if(scanStepValues[i] >= gTxVfo->StepFrequency) {\r\n                settings.scanStepIndex = i;\r\n                break;\r\n            }\r\n        }\r\n        settings.stepsCount = STEPS_128;\r\n    }\r\n    else\r\n#endif\r\n    {\r\n        currentFreq = initialFreq = gTxVfo->pRX->Frequency -\r\n                                    ((GetStepsCount() / 2) * GetScanStep());\r\n    }\r\n    BackupRegisters();\r\n\r\n    isListening = true; // to turn off RX later\r\n    redrawStatus = true;\r\n    redrawScreen = true;\r\n    newScanStart = true;\r\n\r\n\r\n    ToggleRX(true), ToggleRX(false); // hack to prevent noise when squelch off\r\n    RADIO_SetModulation(settings.modulationType = gTxVfo->Modulation);\r\n\r\n    BK4819_SetFilterBandwidth(settings.listenBw = BK4819_FILTER_BW_WIDE, false);\r\n\r\n    RelaunchScan();\r\n\r\n    memset(rssiHistory, 0, sizeof(rssiHistory));\r\n    isInitialized = true;\r\n#ifdef ENABLE_DOPPLER\r\n    statuslineUpdateTimer = 4097;\r\n\r\n    if (DOPPLER_MODE) {\r\n        settings.listenBw = 0;\r\n        settings.modulationType = MODULATION_FM;\r\n        SetState(STILL);\r\n        TuneToPeak();\r\n\r\n\r\n        settings.dbMin = -130;\r\n    }\r\n#endif\r\n    while (isInitialized) {\r\n//#ifdef ENABLE_DOPPLER\r\n//\r\n//        if (DOPPLER_MODE) {\r\n//            satellite_data.DownLink=43850000;\r\n//            SetF(satellite_data.DownLink);\r\n//            currentFreq = satellite_data.DownLink;\r\n//        }\r\n//#endif\r\n#ifdef ENABLE_DOPPLER\r\n        if (DOPPLER_MODE&&!isTransmitting&&currentFreq!=satellite_data.DownLink) {\r\n            SetF(satellite_data.DownLink);\r\n            currentFreq = satellite_data.DownLink;\r\n        }\r\n\r\n#endif\r\n        Tick();\r\n\r\n    }\r\n\r\n}\r\n\r\n#ifdef ENABLE_DOPPLER\r\n\r\nvoid RTCHandler(void) {\r\n\r\n\r\n    RTC_Get();\r\n    int32_t NOW_UNIX_TIME = UNIX_TIME(time);\r\n    time_diff = satellite.START_TIME_UNIX - NOW_UNIX_TIME; //卫星开始时间-现在时间\r\n    time_diff1 = satellite.sum_time + time_diff;//结束-开始+开始-现在\r\n\r\n    READ_DATA(time_diff, time_diff1);\r\n\r\n\r\n    RTC_IF |= (1 << 5);//清除中断标志位\r\n\r\n}\r\n\r\n#endif\r\n"
  },
  {
    "path": "app/spectrum.h",
    "content": "/* Copyright 2023 fagci\r\n * https://github.com/fagci\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef SPECTRUM_H\r\n#define SPECTRUM_H\r\n\r\n#include \"../bitmaps.h\"\r\n#include \"../board.h\"\r\n#include \"../bsp/dp32g030/gpio.h\"\r\n#include \"../driver/bk4819-regs.h\"\r\n#include \"../driver/bk4819.h\"\r\n#include \"../driver/gpio.h\"\r\n#include \"../driver/keyboard.h\"\r\n#include \"../driver/st7565.h\"\r\n#include \"../driver/system.h\"\r\n#include \"../driver/systick.h\"\r\n#include \"../external/printf/printf.h\"\r\n#include \"../font.h\"\r\n#include \"../helper/battery.h\"\r\n#include \"../misc.h\"\r\n#include \"../radio.h\"\r\n#include \"../settings.h\"\r\n#include \"../ui/helper.h\"\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n#include <string.h>\r\n\r\nstatic const uint8_t DrawingEndY = 40;\r\n\r\nstatic const uint8_t U8RssiMap[] = {\r\n        121, 115, 109, 103, 97, 91, 85, 79, 73, 63,\r\n};\r\n\r\nstatic const uint16_t scanStepValues[] = {\r\n        1, 10, 50, 100, 250, 500, 625, 833,\r\n        1000, 1250, 1500, 2000, 2500, 5000, 10000,\r\n};\r\n\r\nstatic const uint16_t scanStepBWRegValues[] = {\r\n        //     RX  RXw TX  BW\r\n        // 0b0 000 000 001 01 1000\r\n        // 1\r\n        0b0000000001011000, // 6.25\r\n        // 10\r\n        0b0000000001011000, // 6.25\r\n        // 50\r\n        0b0000000001011000, // 6.25\r\n        // 100\r\n        0b0000000001011000, // 6.25\r\n        // 250\r\n        0b0000000001011000, // 6.25\r\n        // 500\r\n        0b0010010001011000, // 6.25\r\n        // 625\r\n        0b0100100001011000, // 6.25\r\n        // 833\r\n        0b0110110001001000, // 6.25\r\n        // 1000\r\n        0b0110110001001000, // 6.25\r\n        // 1250\r\n        0b0111111100001000, // 6.25\r\n        // 2500\r\n        0b0011011000101000, // 25\r\n        // 10000\r\n        0b0011011000101000, // 25\r\n};\r\n\r\nstatic const uint16_t listenBWRegValues[] = {\r\n        0b0011011000101000, // 25\r\n        0b0111111100001000, // 12.5\r\n        0b0100100001011000, // 6.25\r\n};\r\n\r\ntypedef enum State {\r\n    SPECTRUM,\r\n    FREQ_INPUT,\r\n    STILL,\r\n} State;\r\n\r\ntypedef enum StepsCount {\r\n    STEPS_128,\r\n    STEPS_64,\r\n    STEPS_32,\r\n    STEPS_16,\r\n} StepsCount;\r\n\r\ntypedef enum ScanStep {\r\n    S_STEP_0_01kHz,\r\n    S_STEP_0_1kHz,\r\n    S_STEP_0_5kHz,\r\n    S_STEP_1_0kHz,\r\n\r\n    S_STEP_2_5kHz,\r\n    S_STEP_5_0kHz,\r\n    S_STEP_6_25kHz,\r\n    S_STEP_8_33kHz,\r\n    S_STEP_10_0kHz,\r\n    S_STEP_12_5kHz,\r\n    S_STEP_15_0kHz,\r\n    S_STEP_20_0kHz,\r\n    S_STEP_25_0kHz,\r\n    S_STEP_50_0kHz,\r\n    S_STEP_100_0kHz,\r\n} ScanStep;\r\n\r\ntypedef struct SpectrumSettings {\r\n    uint32_t frequencyChangeStep;\r\n    StepsCount stepsCount;\r\n    ScanStep scanStepIndex;\r\n    uint16_t scanDelay;\r\n    uint16_t rssiTriggerLevel;\r\n    BK4819_FilterBandwidth_t bw;\r\n    BK4819_FilterBandwidth_t listenBw;\r\n    int dbMin;\r\n    int dbMax;\r\n    ModulationMode_t modulationType;\r\n    bool backlightState;\r\n} SpectrumSettings;\r\n\r\ntypedef enum {\r\n    KEY_STATE_IDLE,\r\n    KEY_STATE_PRESSED,\r\n    KEY_STATE_HELD,\r\n    KEY_STATE_RELEASED\r\n} KeyState_t;\r\n\r\ntypedef struct KeyboardState {\r\n    KEY_Code_t current;\r\n    KEY_Code_t prev;\r\n    uint8_t counter;\r\n    KeyState_t state;\r\n    bool gRepeatHeld;\r\n\r\n} KeyboardState;\r\n\r\ntypedef struct ScanInfo {\r\n    uint16_t rssi, rssiMin, rssiMax;\r\n    uint16_t i, iPeak;\r\n    uint32_t f, fPeak;\r\n    uint16_t scanStep;\r\n    uint16_t measurementsCount;\r\n} ScanInfo;\r\n\r\ntypedef struct PeakInfo {\r\n    uint16_t t;\r\n    uint16_t rssi;\r\n    uint32_t f;\r\n    uint16_t i;\r\n} PeakInfo;\r\nextern uint32_t tempFreq;\r\nextern char freqInputString[11];\r\nextern uint8_t freqInputIndex ;\r\nextern uint8_t freqInputDotIndex ;\r\nextern State currentState , previousState ;\r\nvoid SetState(State state) ;\r\nvoid ResetFreqInput() ;\r\nvoid UpdateFreqInput(KEY_Code_t key) ;\r\n void RenderFreqInput() ;\r\n void FreqInput() ;\r\nextern KEY_Code_t freqInputArr[10];\r\n void APP_RunSpectrum(void);\r\n void DrawPower();\r\n#ifdef ENABLE_DOPPLER\r\nextern bool DOPPLER_MODE;\r\nvoid RTCHandler();\r\n#endif\r\n#endif /* ifndef SPECTRUM_H */\r\n\r\n// vim: ft=c"
  },
  {
    "path": "app/uart.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <string.h>\r\n#include \"font.h\"\r\n\r\n#if !defined(ENABLE_OVERLAY)\r\n\r\n#include \"ARMCM0.h\"\r\n\r\n#endif\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n#ifdef ENABLE_DOPPLER\r\n#include \"bsp/dp32g030/rtc.h\"\r\n#endif\r\n\r\n#include \"app/uart.h\"\r\n#include \"board.h\"\r\n#include \"bsp/dp32g030/dma.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/aes.h\"\r\n#include \"driver/backlight.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/crc.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/uart.h\"\r\n#include \"functions.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n\r\n#if defined(ENABLE_OVERLAY)\r\n#include \"sram-overlay.h\"\r\n#endif\r\n\r\n#include \"version.h\"\r\n\r\n#define DMA_INDEX(x, y) (((x) + (y)) % sizeof(UART_DMA_Buffer))\r\n\r\ntypedef struct {\r\n    uint16_t ID;\r\n    uint16_t Size;\r\n} Header_t;\r\n#ifdef ENABLE_DOCK\r\ntypedef struct {\r\n        Header_t Header;\r\n        uint8_t Key;\r\n        uint8_t Padding;\r\n        uint32_t Timestamp;\r\n    } CMD_0801_t; // simulate key press\r\n#endif\r\ntypedef struct {\r\n    uint8_t Padding[2];\r\n    uint16_t ID;\r\n} Footer_t;\r\n\r\ntypedef struct {\r\n    Header_t Header;\r\n    uint32_t Timestamp;\r\n} CMD_0514_t;\r\n\r\ntypedef struct {\r\n    Header_t Header;\r\n    struct {\r\n        char Version[16];\r\n        bool bHasCustomAesKey;\r\n        bool bIsInLockScreen;\r\n        uint8_t Padding[2];\r\n        uint32_t Challenge[4];\r\n    } Data;\r\n} REPLY_0514_t;\r\n\r\ntypedef struct {\r\n    Header_t Header;\r\n    uint16_t Offset;\r\n    uint8_t Size;\r\n    uint8_t Padding;\r\n    uint32_t Timestamp;\r\n    uint8_t ADD[2];\r\n} CMD_051B_t;\r\ntypedef struct {\r\n    Header_t Header;\r\n    uint16_t Offset;\r\n    uint8_t Size;\r\n    uint8_t Padding;\r\n    uint32_t Timestamp;\r\n    uint8_t ADD[2];\r\n\r\n} CMD_052B_t;\r\ntypedef struct {\r\n    Header_t Header;\r\n    struct {\r\n        uint16_t Offset;\r\n        uint8_t Size;\r\n        uint8_t Padding;\r\n        uint8_t Data[128];\r\n    } Data;\r\n} REPLY_051B_t;\r\n\r\ntypedef struct {\r\n    Header_t Header;\r\n    uint16_t Offset;\r\n    uint8_t Size;\r\n    bool bAllowPassword;\r\n    uint32_t Timestamp;\r\n    uint8_t Data[0];\r\n} CMD_051D_t;\r\n\r\ntypedef struct {\r\n    Header_t Header;\r\n    struct {\r\n        uint16_t Offset;\r\n    } Data;\r\n} REPLY_051D_t;\r\n\r\ntypedef struct {\r\n    Header_t Header;\r\n    struct {\r\n        uint16_t RSSI;\r\n        uint8_t ExNoiseIndicator;\r\n        uint8_t GlitchIndicator;\r\n    } Data;\r\n} REPLY_0527_t;\r\n\r\ntypedef struct {\r\n    Header_t Header;\r\n    struct {\r\n        uint16_t Voltage;\r\n        uint16_t Current;\r\n    } Data;\r\n} REPLY_0529_t;\r\n\r\ntypedef struct {\r\n    Header_t Header;\r\n    uint32_t Response[4];\r\n} CMD_052D_t;\r\n#ifdef ENABLE_BLOCK\r\ntypedef struct {\r\n    Header_t Header;\r\n    struct {\r\n        bool bIsLocked;\r\n        uint8_t Padding[3];\r\n    } Data;\r\n} REPLY_052D_t;\r\n#endif\r\ntypedef struct {\r\n    Header_t Header;\r\n    uint32_t Timestamp;\r\n} CMD_052F_t;\r\n\r\nstatic const uint8_t Obfuscation[16] =\r\n        {\r\n                0x16, 0x6C, 0x14, 0xE6, 0x2E, 0x91, 0x0D, 0x40, 0x21, 0x35, 0xD5, 0x40, 0x13, 0x03, 0xE9, 0x80\r\n        };\r\n\r\nstatic union {\r\n    uint8_t Buffer[256];\r\n    struct {\r\n        Header_t Header;\r\n        uint8_t Data[252];\r\n    };\r\n} UART_Command;\r\n\r\nstatic uint32_t Timestamp;\r\nstatic uint16_t gUART_WriteIndex;\r\nstatic bool bIsEncrypted = true;\r\n\r\nstatic void SendReply(void *pReply, uint16_t Size) {\r\n    Header_t Header;\r\n    Footer_t Footer;\r\n\r\n    if (bIsEncrypted) {\r\n        uint8_t *pBytes = (uint8_t *) pReply;\r\n        unsigned int i;\r\n        for (i = 0; i < Size; i++)\r\n            pBytes[i] ^= Obfuscation[i % 16];\r\n    }\r\n\r\n    Header.ID = 0xCDAB;\r\n    Header.Size = Size;\r\n    UART_Send(&Header, sizeof(Header));\r\n    UART_Send(pReply, Size);\r\n\r\n    if (bIsEncrypted) {\r\n        Footer.Padding[0] = Obfuscation[(Size + 0) % 16] ^ 0xFF;\r\n        Footer.Padding[1] = Obfuscation[(Size + 1) % 16] ^ 0xFF;\r\n    } else {\r\n        Footer.Padding[0] = 0xFF;\r\n        Footer.Padding[1] = 0xFF;\r\n    }\r\n    Footer.ID = 0xBADC;\r\n\r\n    UART_Send(&Footer, sizeof(Footer));\r\n}\r\n\r\nstatic void SendVersion(void) {\r\n    REPLY_0514_t Reply;\r\n\r\n    Reply.Header.ID = 0x0515;\r\n    Reply.Header.Size = sizeof(Reply.Data);\r\n    strcpy(Reply.Data.Version, Version);\r\n    Reply.Data.bHasCustomAesKey = bHasCustomAesKey;\r\n    Reply.Data.bIsInLockScreen = bIsInLockScreen;\r\n    Reply.Data.Challenge[0] = gChallenge[0];\r\n    Reply.Data.Challenge[1] = gChallenge[1];\r\n    Reply.Data.Challenge[2] = gChallenge[2];\r\n    Reply.Data.Challenge[3] = gChallenge[3];\r\n\r\n    SendReply(&Reply, sizeof(Reply));\r\n}\r\n\r\n#ifdef ENABLE_BLOCK\r\nstatic bool IsBadChallenge(const uint32_t *pKey, const uint32_t *pIn, const uint32_t *pResponse) {\r\n    unsigned int i;\r\n    uint32_t IV[4];\r\n\r\n    IV[0] = 0;\r\n    IV[1] = 0;\r\n    IV[2] = 0;\r\n    IV[3] = 0;\r\n\r\n    AES_Encrypt(pKey, IV, pIn, IV, true);\r\n\r\n    for (i = 0; i < 4; i++)\r\n        if (IV[i] != pResponse[i])\r\n            return true;\r\n\r\n    return false;\r\n}\r\n#endif\r\n\r\nstatic void CMD_0514(const uint8_t *pBuffer) {\r\n    const CMD_0514_t *pCmd = (const CMD_0514_t *) pBuffer;\r\n\r\n    Timestamp = pCmd->Timestamp;\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    gFmRadioCountdown_500ms = fm_radio_countdown_500ms;\r\n#endif\r\n\r\n    gSerialConfigCountDown_500ms = 12; // 6 sec\r\n\r\n    // turn the LCD backlight off\r\n    BACKLIGHT_TurnOff();\r\n\r\n    SendVersion();\r\n}\r\n\r\nstatic void CMD_051B(const uint8_t *pBuffer) {\r\n    const CMD_051B_t *pCmd = (const CMD_051B_t *) pBuffer;\r\n    REPLY_051B_t Reply;\r\n#ifdef ENABLE_BLOCK\r\n\r\n    bool bLocked = false;\r\n#endif\r\n    if (pCmd->Timestamp != Timestamp)\r\n        return;\r\n\r\n    gSerialConfigCountDown_500ms = 12; // 6 sec\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    gFmRadioCountdown_500ms = fm_radio_countdown_500ms;\r\n#endif\r\n\r\n//    memset(&Reply, 0, sizeof(Reply));\r\n    Reply.Header.ID = 0x051C;\r\n    Reply.Header.Size = pCmd->Size + 4;\r\n    Reply.Data.Offset = pCmd->Offset;\r\n    Reply.Data.Size = pCmd->Size;\r\n#ifdef ENABLE_BLOCK\r\n\r\n    if (bHasCustomAesKey)\r\n        bLocked = gIsLocked;\r\n\r\n    if (!bLocked)\r\n#endif\r\n    if (pCmd->Header.ID == 0x051B)\r\n        EEPROM_ReadBuffer(pCmd->Offset, Reply.Data.Data, pCmd->Size);\r\n    else\r\n        EEPROM_ReadBuffer(((pCmd->Offset) << 16) + ((pCmd->ADD[1]) << 8) + (pCmd->ADD[0]), Reply.Data.Data, pCmd->Size);\r\n    SendReply(&Reply, pCmd->Size + 8);\r\n}\r\n\r\nstatic void CMD_051D(const uint8_t *pBuffer) {\r\n    const CMD_051D_t *pCmd = (const CMD_051D_t *) pBuffer;\r\n    REPLY_051D_t Reply;\r\n#ifdef ENABLE_BLOCK\r\n    bool bIsLocked;\r\n#endif\r\n    if (pCmd->Timestamp != Timestamp)\r\n        return;\r\n\r\n    gSerialConfigCountDown_500ms = 12; // 6 sec\r\n\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    gFmRadioCountdown_500ms = fm_radio_countdown_500ms;\r\n#endif\r\n\r\n    Reply.Header.ID = 0x051E;\r\n    Reply.Header.Size = sizeof(Reply.Data);\r\n    Reply.Data.Offset = pCmd->Offset;\r\n#ifdef ENABLE_BLOCK\r\n\r\n    bIsLocked = bHasCustomAesKey ? gIsLocked : bHasCustomAesKey;\r\n#endif\r\n#ifdef ENABLE_BLOCK\r\n\r\n    if (!bIsLocked) {\r\n#endif\r\n\r\n\r\n    for (unsigned int i = 0; i < (pCmd->Size / 8); i++) {\r\n        const uint16_t Offset = pCmd->Offset + (i * 8U);\r\n#ifdef ENABLE_BLOCK\r\n\r\n        if (Offset >= 0x0F30 && Offset < 0x0F40)\r\n            if (!gIsLocked)\r\n#endif\r\n\r\n#ifdef ENABLE_BLOCK\r\n\r\n        if ((Offset < 0x0E98 || Offset >= 0x0EA0) || !bIsInLockScreen || pCmd->bAllowPassword)\r\n#endif\r\n\r\n        EEPROM_WriteBuffer(Offset, &pCmd->Data[i * 8U], 8);\r\n\r\n    }\r\n\r\n\r\n    SETTINGS_InitEEPROM();\r\n#ifdef ENABLE_BLOCK\r\n\r\n    }\r\n#endif\r\n\r\n    SendReply(&Reply, sizeof(Reply));\r\n}\r\n\r\nstatic void CMD_0527(void) {\r\n    REPLY_0527_t Reply;\r\n\r\n    Reply.Header.ID = 0x0528;\r\n    Reply.Header.Size = sizeof(Reply.Data);\r\n    Reply.Data.RSSI = BK4819_ReadRegister(BK4819_REG_67) & 0x01FF;\r\n    Reply.Data.ExNoiseIndicator = BK4819_ReadRegister(BK4819_REG_65) & 0x007F;\r\n    Reply.Data.GlitchIndicator = BK4819_ReadRegister(BK4819_REG_63);\r\n\r\n    SendReply(&Reply, sizeof(Reply));\r\n}\r\n\r\nstatic void CMD_0529(void) {\r\n    REPLY_0529_t Reply;\r\n\r\n    Reply.Header.ID = 0x52A;\r\n    Reply.Header.Size = sizeof(Reply.Data);\r\n\r\n    // Original doesn't actually send current!\r\n    BOARD_ADC_GetBatteryInfo(&Reply.Data.Voltage, &Reply.Data.Current);\r\n\r\n    SendReply(&Reply, sizeof(Reply));\r\n}\r\n\r\n#ifdef ENABLE_BLOCK\r\nstatic void CMD_052D(const uint8_t *pBuffer) {\r\n    const CMD_052D_t *pCmd = (const CMD_052D_t *) pBuffer;\r\n    REPLY_052D_t Reply;\r\n    bool bIsLocked;\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    gFmRadioCountdown_500ms = fm_radio_countdown_500ms;\r\n#endif\r\n    Reply.Header.ID = 0x052E;\r\n    Reply.Header.Size = sizeof(Reply.Data);\r\n\r\n    bIsLocked = bHasCustomAesKey;\r\n\r\n    if (!bIsLocked)\r\n        bIsLocked = IsBadChallenge(gCustomAesKey, gChallenge, pCmd->Response);\r\n\r\n    if (!bIsLocked) {\r\n        bIsLocked = IsBadChallenge(gDefaultAesKey, gChallenge, pCmd->Response);\r\n        if (bIsLocked)\r\n            gTryCount++;\r\n    }\r\n\r\n    if (gTryCount < 3) {\r\n        if (!bIsLocked)\r\n            gTryCount = 0;\r\n    } else {\r\n        gTryCount = 3;\r\n        bIsLocked = true;\r\n    }\r\n\r\n    gIsLocked = bIsLocked;\r\n    Reply.Data.bIsLocked = bIsLocked;\r\n\r\n    SendReply(&Reply, sizeof(Reply));\r\n}\r\n#endif\r\n\r\n// session init, sends back version info and state\r\n// timestamp is a session id really\r\n// this command also disables dual watch, crossband,\r\n// DTMF side tones, freq reverse, PTT ID, DTMF decoding, frequency offset\r\n// exits power save, sets main VFO to upper,\r\nstatic void CMD_052F(const uint8_t *pBuffer) {\r\n    const CMD_052F_t *pCmd = (const CMD_052F_t *) pBuffer;\r\n\r\n    gEeprom.DUAL_WATCH = DUAL_WATCH_OFF;\r\n    gEeprom.CROSS_BAND_RX_TX = CROSS_BAND_OFF;\r\n    gEeprom.RX_VFO = 0;\r\n    gEeprom.DTMF_SIDE_TONE = false;\r\n    gEeprom.VfoInfo[0].FrequencyReverse = 0;\r\n    gEeprom.VfoInfo[0].pRX = &gEeprom.VfoInfo[0].freq_config_RX;\r\n    gEeprom.VfoInfo[0].pTX = &gEeprom.VfoInfo[0].freq_config_TX;\r\n    gEeprom.VfoInfo[0].TX_OFFSET_FREQUENCY_DIRECTION = TX_OFFSET_FREQUENCY_DIRECTION_OFF;\r\n    gEeprom.VfoInfo[0].DTMF_PTT_ID_TX_MODE = PTT_ID_OFF;\r\n#ifdef ENABLE_DTMF_CALLING\r\n    gEeprom.VfoInfo[0].DTMF_DECODING_ENABLE          = false;\r\n#endif\r\n\r\n#ifdef ENABLE_NOAA\r\n    gIsNoaaMode = false;\r\n#endif\r\n\r\n    if (gCurrentFunction == FUNCTION_POWER_SAVE)\r\n        FUNCTION_Select(FUNCTION_FOREGROUND); //OK\r\n\r\n    gSerialConfigCountDown_500ms = 12; // 6 sec\r\n\r\n    Timestamp = pCmd->Timestamp;\r\n\r\n    // turn the LCD backlight off\r\n    BACKLIGHT_TurnOff();\r\n\r\n    SendVersion();\r\n}\r\n\r\n#ifdef ENABLE_UART_RW_BK_REGS\r\nstatic void CMD_0601_ReadBK4819Reg(const uint8_t *pBuffer)\r\n{\r\n    typedef struct  __attribute__((__packed__)) {\r\n        Header_t header;\r\n        uint8_t reg;\r\n    } CMD_0601_t;\r\n\r\n    CMD_0601_t *cmd = (CMD_0601_t*) pBuffer;\r\n\r\n    struct  __attribute__((__packed__)) {\r\n        Header_t header;\r\n    struct __attribute__((__packed__)) {\r\n            uint8_t reg;\r\n            uint16_t value;\r\n        } data;\r\n    } reply;\r\n\r\n    reply.header.ID = 0x0601;\r\n    reply.header.Size = sizeof(reply.data);\r\n    reply.data.reg = cmd->reg;\r\n    reply.data.value = BK4819_ReadRegister(cmd->reg);\r\n    SendReply(&reply, sizeof(reply));\r\n}\r\n\r\nstatic void CMD_0602_WriteBK4819Reg(const uint8_t *pBuffer)\r\n{\r\n    typedef struct  __attribute__((__packed__)) {\r\n        Header_t header;\r\n        uint8_t reg;\r\n        uint16_t value;\r\n    } CMD_0602_t;\r\n\r\n    CMD_0602_t *cmd = (CMD_0602_t*) pBuffer;\r\n    BK4819_WriteRegister(cmd->reg, cmd->value);\r\n}\r\n#endif\r\n\r\nbool UART_IsCommandAvailable(void) {\r\n    uint16_t Index;\r\n    uint16_t TailIndex;\r\n    uint16_t Size;\r\n    uint16_t CRC;\r\n    uint16_t CommandLength;\r\n    uint16_t DmaLength = DMA_CH0->ST & 0xFFFU;\r\n\r\n\r\n    while (1) {\r\n        if (gUART_WriteIndex == DmaLength)\r\n            return false;\r\n\r\n        while (gUART_WriteIndex != DmaLength && UART_DMA_Buffer[gUART_WriteIndex] != 0xABU)\r\n            gUART_WriteIndex = DMA_INDEX(gUART_WriteIndex, 1);\r\n\r\n        if (gUART_WriteIndex == DmaLength)\r\n            return false;\r\n\r\n        if (gUART_WriteIndex < DmaLength)\r\n            CommandLength = DmaLength - gUART_WriteIndex;\r\n        else\r\n            CommandLength = (DmaLength + sizeof(UART_DMA_Buffer)) - gUART_WriteIndex;\r\n\r\n        if (CommandLength < 8)\r\n            return 0;\r\n\r\n        if (UART_DMA_Buffer[DMA_INDEX(gUART_WriteIndex, 1)] == 0xCD)\r\n            break;\r\n\r\n        gUART_WriteIndex = DMA_INDEX(gUART_WriteIndex, 1);\r\n    }\r\n\r\n    Index = DMA_INDEX(gUART_WriteIndex, 2);\r\n    Size = (UART_DMA_Buffer[DMA_INDEX(Index, 1)] << 8) | UART_DMA_Buffer[Index];\r\n\r\n    if ((Size + 8u) > sizeof(UART_DMA_Buffer)) {\r\n        gUART_WriteIndex = DmaLength;\r\n        return false;\r\n    }\r\n\r\n    if (CommandLength < (Size + 8))\r\n        return false;\r\n\r\n    Index = DMA_INDEX(Index, 2);\r\n    TailIndex = DMA_INDEX(Index, Size + 2);\r\n\r\n    if (UART_DMA_Buffer[TailIndex] != 0xDC || UART_DMA_Buffer[DMA_INDEX(TailIndex, 1)] != 0xBA) {\r\n        gUART_WriteIndex = DmaLength;\r\n        return false;\r\n    }\r\n\r\n    if (TailIndex < Index) {\r\n        const uint16_t ChunkSize = sizeof(UART_DMA_Buffer) - Index;\r\n        memcpy(UART_Command.Buffer, UART_DMA_Buffer + Index, ChunkSize);\r\n        memcpy(UART_Command.Buffer + ChunkSize, UART_DMA_Buffer, TailIndex);\r\n    } else\r\n        memcpy(UART_Command.Buffer, UART_DMA_Buffer + Index, TailIndex - Index);\r\n\r\n    TailIndex = DMA_INDEX(TailIndex, 2);\r\n    if (TailIndex < gUART_WriteIndex) {\r\n        memset(UART_DMA_Buffer + gUART_WriteIndex, 0, sizeof(UART_DMA_Buffer) - gUART_WriteIndex);\r\n        memset(UART_DMA_Buffer, 0, TailIndex);\r\n    } else\r\n        memset(UART_DMA_Buffer + gUART_WriteIndex, 0, TailIndex - gUART_WriteIndex);\r\n\r\n    gUART_WriteIndex = TailIndex;\r\n\r\n    if (UART_Command.Header.ID == 0x0514)\r\n        bIsEncrypted = false;\r\n\r\n    if (UART_Command.Header.ID == 0x6902)\r\n        bIsEncrypted = true;\r\n\r\n    if (bIsEncrypted) {\r\n        unsigned int i;\r\n        for (i = 0; i < (Size + 2u); i++)\r\n            UART_Command.Buffer[i] ^= Obfuscation[i % 16];\r\n    }\r\n\r\n    CRC = UART_Command.Buffer[Size] | (UART_Command.Buffer[Size + 1] << 8);\r\n//    char b[2]=\"3K\";\r\n//     uint8_t tmp[Size];\r\n//    for (int i = 0; i < Size; i++) {\r\n//        tmp[i]=UART_Command.Buffer[i];\r\n//    }\r\n    bool judge = (CRC_Calculate1(UART_Command.Buffer, Size) != CRC) ? false : true;\r\n\r\n    return judge;\r\n}\r\n\r\n#if ENABLE_CHINESE_FULL == 4\r\n//\r\n//static void CMD_052B(const uint8_t *pBuffer)//read\r\n//{\r\n//    const CMD_052B_t *pCmd = (const CMD_052B_t *) pBuffer;\r\n//    REPLY_051B_t Reply;\r\n//\r\n//\r\n//    if (pCmd->Timestamp != Timestamp)\r\n//        return;\r\n//\r\n//    gSerialConfigCountDown_500ms = 12; // 6 sec\r\n//\r\n//#ifdef ENABLE_FMRADIO\r\n//    gFmRadioCountdown_500ms = fm_radio_countdown_500ms;\r\n//#endif\r\n//\r\n////    memset(&Reply, 0, sizeof(Reply));\r\n//    Reply.Header.ID = 0x051C;\r\n//    Reply.Header.Size = pCmd->Size + 4;\r\n//    Reply.Data.Offset = pCmd->Offset;\r\n//\r\n//    Reply.Data.Size = pCmd->Size;\r\n//\r\n//\r\n//        EEPROM_ReadBuffer(((pCmd->Offset) << 16) + ((pCmd->ADD[1]) << 8) + (pCmd->ADD[0]), Reply.Data.Data, pCmd->Size);\r\n//\r\n//    SendReply(&Reply, pCmd->Size + 8);\r\n//}\r\n\r\nstatic void CMD_0538(const uint8_t *pBuffer)//write\r\n{\r\n    const CMD_051D_t *pCmd = (const CMD_051D_t *) pBuffer;\r\n    REPLY_051D_t Reply;\r\n    if (pCmd->Timestamp != Timestamp)\r\n        return;\r\n    gSerialConfigCountDown_500ms = 12; // 6 sec\r\n#ifdef ENABLE_FMRADIO\r\n    gFmRadioCountdown_500ms = fm_radio_countdown_500ms;\r\n#endif\r\n    Reply.Header.ID = 0x051E;\r\n    Reply.Header.Size = sizeof(Reply.Data);\r\n    Reply.Data.Offset = pCmd->Offset;\r\n    int add=((pCmd->Size) - 2)%8;\r\n\r\n\r\n\r\n        for ( int i = 0; i < ((pCmd->Size) - 2) / 8+(add==0?0:1); i++) {\r\n            const uint32_t Offset = ((pCmd->Offset) << 16) + ((pCmd->Data[1]) << 8) + (pCmd->Data[0]) + (i * 8U);\r\n//#ifdef ENABLE_DOPPLER\r\n//            if(Offset>=0x90000)\r\n//                {\r\n//                memcpy(time,pCmd->Data[i * 8U + 2],6);\r\n//                RTC_Set(time);\r\n//                continue;\r\n//                }\r\n//#endif\r\n                if(add&&i==((pCmd->Size) - 2) / 8+(add==0?0:1)-1)\r\n                    EEPROM_WriteBuffer(Offset, &pCmd->Data[i * 8U + 2], add);\r\n                else\r\n                    EEPROM_WriteBuffer(Offset, &pCmd->Data[i * 8U + 2], 8);\r\n        }\r\n            SETTINGS_InitEEPROM();\r\n\r\n    SendReply(&Reply, sizeof(Reply));\r\n}\r\n#endif\r\n\r\n#ifdef ENABLE_DOCK\r\nstatic void CMD_0801(const uint8_t *pBuffer)\r\n    {\r\n        const CMD_0801_t *pCmd = (const CMD_0801_t *)pBuffer;\r\n        const uint8_t key = pCmd->Key & 0x1f;\r\n        const bool click = pCmd->Key & 32;\r\n        if(key != KEY_INVALID)\r\n        {\r\n            gSimulateKey = key;\r\n            gDebounceDefeat = 0;\r\n        }\r\n        gSimulateHold = click ? KEY_INVALID : key;\r\n    }\r\n#endif\r\n\r\nvoid UART_HandleCommand(void) {\r\n    switch (UART_Command.Header.ID) {\r\n#if ENABLE_CHINESE_FULL == 4\r\n        case 0x052B://read\r\n            CMD_051B(UART_Command.Buffer);\r\n            break;\r\n        case 0x0538://write\r\n            CMD_0538(UART_Command.Buffer);\r\n            break;\r\n#endif\r\n#ifdef ENABLE_DOCK\r\n        case 0x0801:\r\n            CMD_0801(UART_Command.Buffer);\r\n            break;\r\n\r\n#endif\r\n        case 0x0514:\r\n            CMD_0514(UART_Command.Buffer);\r\n            break;\r\n\r\n        case 0x051B:\r\n            CMD_051B(UART_Command.Buffer);\r\n            break;\r\n\r\n        case 0x051D:\r\n            CMD_051D(UART_Command.Buffer);\r\n            break;\r\n\r\n\r\n        case 0x0527:\r\n            CMD_0527();\r\n            break;\r\n\r\n        case 0x0529:\r\n            CMD_0529();\r\n            break;\r\n#ifdef ENABLE_BLOCK\r\n\r\n            case 0x052D:\r\n                CMD_052D(UART_Command.Buffer);\r\n                break;\r\n#endif\r\n        case 0x052F:\r\n            CMD_052F(UART_Command.Buffer);\r\n            break;\r\n\r\n        case 0x05DD:\r\n#if defined(ENABLE_OVERLAY)\r\n            overlay_FLASH_RebootToBootloader();\r\n#else\r\n            NVIC_SystemReset();\r\n#endif\r\n            break;\r\n#ifdef ENABLE_UART_RW_BK_REGS\r\n            case 0x0601:\r\n            CMD_0601_ReadBK4819Reg(UART_Command.Buffer);\r\n            break;\r\n\r\n        case 0x0602:\r\n            CMD_0602_WriteBK4819Reg(UART_Command.Buffer);\r\n            break;\r\n#endif\r\n    }\r\n}"
  },
  {
    "path": "app/uart.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef APP_UART_H\r\n#define APP_UART_H\r\n\r\n#include <stdbool.h>\r\n\r\nbool UART_IsCommandAvailable(void);\r\n\r\nvoid UART_HandleCommand(void);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "audio.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"audio.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"driver/bk1080.h\"\r\n#endif\r\n\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/system.h\"\r\n#include \"driver/systick.h\"\r\n#include \"functions.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/ui.h\"\r\n\r\n\r\nBEEP_Type_t gBeepToPlay = BEEP_NONE;\r\n\r\nvoid AUDIO_PlayBeep(BEEP_Type_t Beep) {\r\n\r\n    if (Beep != BEEP_880HZ_60MS_TRIPLE_BEEP &&\r\n        Beep != BEEP_500HZ_60MS_DOUBLE_BEEP &&\r\n        Beep != BEEP_440HZ_500MS &&\r\n        Beep != BEEP_880HZ_200MS &&\r\n        Beep != BEEP_880HZ_500MS &&\r\n        !gEeprom.BEEP_CONTROL)\r\n        return;\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n    if (gScreenToDisplay == DISPLAY_AIRCOPY)\r\n        return;\r\n#endif\r\n\r\n    if (gCurrentFunction == FUNCTION_RECEIVE || gCurrentFunction == FUNCTION_MONITOR)\r\n        return;\r\n\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFmRadioMode)\r\n        BK1080_Mute(true);\r\n#endif\r\n\r\n    AUDIO_AudioPathOff();\r\n\r\n    if (gCurrentFunction == FUNCTION_POWER_SAVE && gRxIdleMode)\r\n        BK4819_RX_TurnOn();\r\n\r\n    SYSTEM_DelayMs(20);\r\n\r\n    uint16_t ToneConfig = BK4819_ReadRegister(BK4819_REG_71);\r\n\r\n    uint16_t ToneFrequency;\r\n    switch (Beep) {\r\n        default:\r\n        case BEEP_NONE:\r\n            ToneFrequency = 220;\r\n            break;\r\n        case BEEP_1KHZ_60MS_OPTIONAL:\r\n            ToneFrequency = 1000;\r\n            break;\r\n        case BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL:\r\n        case BEEP_500HZ_60MS_DOUBLE_BEEP:\r\n            ToneFrequency = 500;\r\n            break;\r\n        case BEEP_440HZ_40MS_OPTIONAL:\r\n        case BEEP_440HZ_500MS:\r\n            ToneFrequency = 440;\r\n            break;\r\n        case BEEP_880HZ_40MS_OPTIONAL:\r\n        case BEEP_880HZ_60MS_TRIPLE_BEEP:\r\n        case BEEP_880HZ_200MS:\r\n        case BEEP_880HZ_500MS:\r\n            ToneFrequency = 880;\r\n            break;\r\n    }\r\n\r\n    BK4819_PlayTone(ToneFrequency, true);\r\n\r\n    SYSTEM_DelayMs(2);\r\n\r\n    AUDIO_AudioPathOn();\r\n\r\n    SYSTEM_DelayMs(60);\r\n\r\n    uint16_t Duration;\r\n    switch (Beep) {\r\n        case BEEP_880HZ_60MS_TRIPLE_BEEP:\r\n            BK4819_ExitTxMute();\r\n            SYSTEM_DelayMs(60);\r\n            BK4819_EnterTxMute();\r\n            SYSTEM_DelayMs(20);\r\n            [[fallthrough]];\r\n        case BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL:\r\n        case BEEP_500HZ_60MS_DOUBLE_BEEP:\r\n            BK4819_ExitTxMute();\r\n            SYSTEM_DelayMs(60);\r\n            BK4819_EnterTxMute();\r\n            SYSTEM_DelayMs(20);\r\n            [[fallthrough]];\r\n        case BEEP_1KHZ_60MS_OPTIONAL:\r\n            BK4819_ExitTxMute();\r\n            Duration = 60;\r\n            break;\r\n        case BEEP_880HZ_40MS_OPTIONAL:\r\n        case BEEP_440HZ_40MS_OPTIONAL:\r\n            BK4819_ExitTxMute();\r\n            Duration = 40;\r\n            break;\r\n        case BEEP_880HZ_200MS:\r\n            BK4819_ExitTxMute();\r\n            Duration = 200;\r\n            break;\r\n        case BEEP_440HZ_500MS:\r\n        case BEEP_880HZ_500MS:\r\n        default:\r\n            BK4819_ExitTxMute();\r\n            Duration = 500;\r\n            break;\r\n    }\r\n\r\n    SYSTEM_DelayMs(Duration);\r\n    BK4819_EnterTxMute();\r\n    SYSTEM_DelayMs(20);\r\n\r\n    AUDIO_AudioPathOff();\r\n\r\n    SYSTEM_DelayMs(5);\r\n    BK4819_TurnsOffTones_TurnsOnRX();\r\n    SYSTEM_DelayMs(5);\r\n    BK4819_WriteRegister(BK4819_REG_71, ToneConfig);\r\n\r\n    if (gEnableSpeaker)\r\n        AUDIO_AudioPathOn();\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFmRadioMode)\r\n        BK1080_Mute(false);\r\n#endif\r\n\r\n    if (gCurrentFunction == FUNCTION_POWER_SAVE && gRxIdleMode)\r\n        BK4819_Sleep();\r\n\r\n#ifdef ENABLE_VOX\r\n    gVoxResumeCountdown = 80;\r\n#endif\r\n\r\n}\r\n\r\n#ifdef ENABLE_VOICE\r\n\r\nstatic const uint8_t VoiceClipLengthChinese[58] =\r\n{\r\n    0x32, 0x32, 0x32, 0x37, 0x37, 0x32, 0x32, 0x32,\r\n    0x32, 0x37, 0x37, 0x32, 0x64, 0x64, 0x64, 0x64,\r\n    0x64, 0x69, 0x64, 0x69, 0x5A, 0x5F, 0x5F, 0x64,\r\n    0x64, 0x69, 0x64, 0x64, 0x69, 0x69, 0x69, 0x64,\r\n    0x64, 0x6E, 0x69, 0x5F, 0x64, 0x64, 0x64, 0x69,\r\n    0x69, 0x69, 0x64, 0x69, 0x64, 0x64, 0x55, 0x5F,\r\n    0x5A, 0x4B, 0x4B, 0x46, 0x46, 0x69, 0x64, 0x6E,\r\n    0x5A, 0x64,\r\n};\r\n\r\nstatic const uint8_t VoiceClipLengthEnglish[76] =\r\n{\r\n    0x50, 0x32, 0x2D, 0x2D, 0x2D, 0x37, 0x37, 0x37,\r\n    0x32, 0x32, 0x3C, 0x37, 0x46, 0x46, 0x4B, 0x82,\r\n    0x82, 0x6E, 0x82, 0x46, 0x96, 0x64, 0x46, 0x6E,\r\n    0x78, 0x6E, 0x87, 0x64, 0x96, 0x96, 0x46, 0x9B,\r\n    0x91, 0x82, 0x82, 0x73, 0x78, 0x64, 0x82, 0x6E,\r\n    0x78, 0x82, 0x87, 0x6E, 0x55, 0x78, 0x64, 0x69,\r\n    0x9B, 0x5A, 0x50, 0x3C, 0x32, 0x55, 0x64, 0x64,\r\n    0x50, 0x46, 0x46, 0x46, 0x4B, 0x4B, 0x50, 0x50,\r\n    0x55, 0x4B, 0x4B, 0x32, 0x32, 0x32, 0x32, 0x37,\r\n    0x41, 0x32, 0x3C, 0x37,\r\n};\r\n\r\nVOICE_ID_t        gVoiceID[8];\r\nuint8_t           gVoiceReadIndex;\r\nuint8_t           gVoiceWriteIndex;\r\nvolatile uint16_t gCountdownToPlayNextVoice_10ms;\r\nvolatile bool     gFlagPlayQueuedVoice;\r\nVOICE_ID_t        gAnotherVoiceID = VOICE_ID_INVALID;\r\n\r\n\r\nstatic void AUDIO_PlayVoice(uint8_t VoiceID)\r\n{\r\n    unsigned int i;\r\n\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_VOICE_0);\r\n    SYSTEM_DelayMs(20);\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_VOICE_0);\r\n\r\n    for (i = 0; i < 8; i++)\r\n    {\r\n        if ((VoiceID & 0x80U) == 0)\r\n            GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_VOICE_1);\r\n        else\r\n            GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_VOICE_1);\r\n\r\n        SYSTICK_DelayUs(1000);\r\n        GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_VOICE_0);\r\n        SYSTICK_DelayUs(1200);\r\n        GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_VOICE_0);\r\n        VoiceID <<= 1;\r\n        SYSTICK_DelayUs(200);\r\n    }\r\n}\r\n\r\nvoid AUDIO_PlaySingleVoice(bool bFlag)\r\n{\r\n    uint8_t VoiceID;\r\n    uint8_t Delay;\r\n\r\n    VoiceID = gVoiceID[0];\r\n\r\n    if (gEeprom.VOICE_PROMPT != VOICE_PROMPT_OFF && gVoiceWriteIndex > 0)\r\n    {\r\n        if (gEeprom.VOICE_PROMPT == VOICE_PROMPT_CHINESE)\r\n        {\t// Chinese\r\n            if (VoiceID >= ARRAY_SIZE(VoiceClipLengthChinese))\r\n                goto Bailout;\r\n\r\n            Delay    = VoiceClipLengthChinese[VoiceID];\r\n            VoiceID += VOICE_ID_CHI_BASE;\r\n        }\r\n        else\r\n        {\t// English\r\n            if (VoiceID >= ARRAY_SIZE(VoiceClipLengthEnglish))\r\n                goto Bailout;\r\n\r\n            Delay    = VoiceClipLengthEnglish[VoiceID];\r\n            VoiceID += VOICE_ID_ENG_BASE;\r\n        }\r\n\r\n        if (FUNCTION_IsRx())   // 1of11\r\n            BK4819_SetAF(BK4819_AF_MUTE);\r\n\r\n#ifdef ENABLE_FMRADIO\r\n            if (gFmRadioMode)\r\n                BK1080_Mute(true);\r\n#endif\r\n\r\n        AUDIO_AudioPathOn();\r\n\r\n#ifdef ENABLE_VOX\r\n            gVoxResumeCountdown = 2000;\r\n#endif\r\n\r\n        SYSTEM_DelayMs(5);\r\n        AUDIO_PlayVoice(VoiceID);\r\n\r\n        if (gVoiceWriteIndex == 1)\r\n            Delay += 3;\r\n\r\n        if (bFlag)\r\n        {\r\n            SYSTEM_DelayMs(Delay * 10);\r\n\r\n            if (FUNCTION_IsRx())\t// 1of11\r\n                RADIO_SetModulation(gRxVfo->Modulation);\r\n\r\n#ifdef ENABLE_FMRADIO\r\n                if (gFmRadioMode)\r\n                    BK1080_Mute(false);\r\n#endif\r\n\r\n            if (!gEnableSpeaker)\r\n                AUDIO_AudioPathOff();\r\n\r\n            gVoiceWriteIndex    = 0;\r\n            gVoiceReadIndex     = 0;\r\n\r\n#ifdef ENABLE_VOX\r\n                gVoxResumeCountdown = 80;\r\n#endif\r\n\r\n            return;\r\n        }\r\n\r\n        gVoiceReadIndex                = 1;\r\n        gCountdownToPlayNextVoice_10ms = Delay;\r\n        gFlagPlayQueuedVoice           = false;\r\n\r\n        return;\r\n    }\r\n\r\nBailout:\r\n    gVoiceReadIndex  = 0;\r\n    gVoiceWriteIndex = 0;\r\n}\r\n\r\nvoid AUDIO_SetVoiceID(uint8_t Index, VOICE_ID_t VoiceID)\r\n{\r\n    if (Index >= ARRAY_SIZE(gVoiceID))\r\n        return;\r\n\r\n    if (Index == 0)\r\n    {\r\n        gVoiceWriteIndex = 0;\r\n        gVoiceReadIndex  = 0;\r\n    }\r\n\r\n    gVoiceID[Index] = VoiceID;\r\n\r\n    gVoiceWriteIndex++;\r\n}\r\n\r\nuint8_t AUDIO_SetDigitVoice(uint8_t Index, uint16_t Value)\r\n{\r\n    uint16_t Remainder;\r\n    uint8_t  Result;\r\n    uint8_t  Count;\r\n\r\n    if (Index == 0)\r\n    {\r\n        gVoiceWriteIndex = 0;\r\n        gVoiceReadIndex  = 0;\r\n    }\r\n\r\n    Count     = 0;\r\n    Result    = Value / 1000U;\r\n    Remainder = Value % 1000U;\r\n    if (Remainder < 100U)\r\n    {\r\n        if (Remainder < 10U)\r\n            goto Skip;\r\n    }\r\n    else\r\n    {\r\n        Result = Remainder / 100U;\r\n        gVoiceID[gVoiceWriteIndex++] = (VOICE_ID_t)Result;\r\n        Count++;\r\n        Remainder -= Result * 100U;\r\n    }\r\n    Result = Remainder / 10U;\r\n    gVoiceID[gVoiceWriteIndex++] = (VOICE_ID_t)Result;\r\n    Count++;\r\n    Remainder -= Result * 10U;\r\n\r\nSkip:\r\n    gVoiceID[gVoiceWriteIndex++] = (VOICE_ID_t)Remainder;\r\n\r\n    return Count + 1U;\r\n}\r\n\r\nvoid AUDIO_PlayQueuedVoice(void)\r\n{\r\n    uint8_t VoiceID;\r\n    uint8_t Delay;\r\n    bool    Skip;\r\n\r\n    Skip = false;\r\n\r\n    if (gVoiceReadIndex != gVoiceWriteIndex && gEeprom.VOICE_PROMPT != VOICE_PROMPT_OFF)\r\n    {\r\n        VoiceID = gVoiceID[gVoiceReadIndex];\r\n        if (gEeprom.VOICE_PROMPT == VOICE_PROMPT_CHINESE)\r\n        {\r\n            if (VoiceID < ARRAY_SIZE(VoiceClipLengthChinese))\r\n            {\r\n                Delay = VoiceClipLengthChinese[VoiceID];\r\n                VoiceID += VOICE_ID_CHI_BASE;\r\n            }\r\n            else\r\n                Skip = true;\r\n        }\r\n        else\r\n        {\r\n            if (VoiceID < ARRAY_SIZE(VoiceClipLengthEnglish))\r\n            {\r\n                Delay = VoiceClipLengthEnglish[VoiceID];\r\n                VoiceID += VOICE_ID_ENG_BASE;\r\n            }\r\n            else\r\n                Skip = true;\r\n        }\r\n\r\n        gVoiceReadIndex++;\r\n\r\n        if (!Skip)\r\n        {\r\n            if (gVoiceReadIndex == gVoiceWriteIndex)\r\n                Delay += 3;\r\n\r\n            AUDIO_PlayVoice(VoiceID);\r\n\r\n            gCountdownToPlayNextVoice_10ms = Delay;\r\n            gFlagPlayQueuedVoice           = false;\r\n\r\n#ifdef ENABLE_VOX\r\n                gVoxResumeCountdown = 2000;\r\n#endif\r\n\r\n            return;\r\n        }\r\n    }\r\n\r\n    if (FUNCTION_IsRx())\r\n    {\r\n        RADIO_SetModulation(gRxVfo->Modulation); // 1of11\r\n    }\r\n\r\n#ifdef ENABLE_FMRADIO\r\n        if (gFmRadioMode)\r\n            BK1080_Mute(false);\r\n#endif\r\n\r\n    if (!gEnableSpeaker)\r\n        AUDIO_AudioPathOff();\r\n\r\n#ifdef ENABLE_VOX\r\n        gVoxResumeCountdown = 80;\r\n#endif\r\n\r\n    gVoiceWriteIndex    = 0;\r\n    gVoiceReadIndex     = 0;\r\n}\r\n\r\n#endif"
  },
  {
    "path": "audio.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef AUDIO_H\r\n#define AUDIO_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/gpio.h\"\r\n\r\nenum BEEP_Type_t\r\n{\r\n\tBEEP_NONE = 0,\r\n\tBEEP_1KHZ_60MS_OPTIONAL,\r\n\tBEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL,\r\n\tBEEP_440HZ_500MS,\r\n\tBEEP_880HZ_200MS,\r\n\tBEEP_880HZ_500MS,\r\n\tBEEP_500HZ_60MS_DOUBLE_BEEP,\r\n\tBEEP_440HZ_40MS_OPTIONAL,\r\n\tBEEP_880HZ_40MS_OPTIONAL,\r\n\tBEEP_880HZ_60MS_TRIPLE_BEEP\r\n};\r\n\r\ntypedef enum BEEP_Type_t BEEP_Type_t;\r\n\r\nextern BEEP_Type_t       gBeepToPlay;\r\n\r\nvoid AUDIO_PlayBeep(BEEP_Type_t Beep);\r\n\r\nenum\r\n{\r\n\tVOICE_ID_CHI_BASE = 0x10U,\r\n\tVOICE_ID_ENG_BASE = 0x60U,\r\n};\r\n\r\nenum VOICE_ID_t\r\n{\r\n\tVOICE_ID_0                             = 0x00U,\r\n\tVOICE_ID_1                             = 0x01U,\r\n\tVOICE_ID_2                             = 0x02U,\r\n\tVOICE_ID_3                             = 0x03U,\r\n\tVOICE_ID_4                             = 0x04U,\r\n\tVOICE_ID_5                             = 0x05U,\r\n\tVOICE_ID_6                             = 0x06U,\r\n\tVOICE_ID_7                             = 0x07U,\r\n\tVOICE_ID_8                             = 0x08U,\r\n\tVOICE_ID_9                             = 0x09U,\r\n\tVOICE_ID_10                            = 0x0AU,\r\n\tVOICE_ID_100                           = 0x0BU,\r\n\tVOICE_ID_WELCOME                       = 0x0CU,\r\n\tVOICE_ID_LOCK                          = 0x0DU,\r\n\tVOICE_ID_UNLOCK                        = 0x0EU,\r\n\tVOICE_ID_SCANNING_BEGIN                = 0x0FU,\r\n\tVOICE_ID_SCANNING_STOP                 = 0x10U,\r\n\tVOICE_ID_SCRAMBLER_ON                  = 0x11U,\r\n\tVOICE_ID_SCRAMBLER_OFF                 = 0x12U,\r\n\tVOICE_ID_FUNCTION                      = 0x13U,\r\n\tVOICE_ID_CTCSS                         = 0x14U,\r\n\tVOICE_ID_DCS                           = 0x15U,\r\n\tVOICE_ID_POWER                         = 0x16U,\r\n\tVOICE_ID_SAVE_MODE                     = 0x17U,\r\n\tVOICE_ID_MEMORY_CHANNEL                = 0x18U,\r\n\tVOICE_ID_DELETE_CHANNEL                = 0x19U,\r\n\tVOICE_ID_FREQUENCY_STEP                = 0x1AU,\r\n\tVOICE_ID_SQUELCH                       = 0x1BU,\r\n\tVOICE_ID_TRANSMIT_OVER_TIME            = 0x1CU,\r\n\tVOICE_ID_BACKLIGHT_SELECTION           = 0x1DU,\r\n\tVOICE_ID_VOX                           = 0x1EU,\r\n\tVOICE_ID_TX_OFFSET_FREQUENCY_DIRECTION = 0x1FU,\r\n\tVOICE_ID_TX_OFFSET_FREQUENCY           = 0x20U,\r\n\tVOICE_ID_TRANSMITING_MEMORY            = 0x21U,\r\n\tVOICE_ID_RECEIVING_MEMORY              = 0x22U,\r\n\tVOICE_ID_EMERGENCY_CALL                = 0x23U,\r\n\tVOICE_ID_LOW_VOLTAGE                   = 0x24U,\r\n\tVOICE_ID_CHANNEL_MODE                  = 0x25U,\r\n\tVOICE_ID_FREQUENCY_MODE                = 0x26U,\r\n\tVOICE_ID_VOICE_PROMPT                  = 0x27U,\r\n\tVOICE_ID_BAND_SELECTION                = 0x28U,\r\n\tVOICE_ID_DUAL_STANDBY                  = 0x29U,\r\n\tVOICE_ID_CHANNEL_BANDWIDTH             = 0x2AU,\r\n\tVOICE_ID_OPTIONAL_SIGNAL               = 0x2BU,\r\n\tVOICE_ID_MUTE_MODE                     = 0x2CU,\r\n\tVOICE_ID_BUSY_LOCKOUT                  = 0x2DU,\r\n\tVOICE_ID_BEEP_PROMPT                   = 0x2EU,\r\n\tVOICE_ID_ANI_CODE                      = 0x2FU,\r\n\tVOICE_ID_INITIALISATION                = 0x30U,\r\n\tVOICE_ID_CONFIRM                       = 0x31U,\r\n\tVOICE_ID_CANCEL                        = 0x32U,\r\n\tVOICE_ID_ON                            = 0x33U,\r\n\tVOICE_ID_OFF                           = 0x34U,\r\n\tVOICE_ID_2_TONE                        = 0x35U,\r\n\tVOICE_ID_5_TONE                        = 0x36U,\r\n\tVOICE_ID_DIGITAL_SIGNAL                = 0x37U,\r\n\tVOICE_ID_REPEATER                      = 0x38U,\r\n\tVOICE_ID_MENU                          = 0x39U,\r\n\tVOICE_ID_11                            = 0x3AU,\r\n\tVOICE_ID_12                            = 0x3BU,\r\n\tVOICE_ID_13                            = 0x3CU,\r\n\tVOICE_ID_14                            = 0x3DU,\r\n\tVOICE_ID_15                            = 0x3EU,\r\n\tVOICE_ID_16                            = 0x3FU,\r\n\tVOICE_ID_17                            = 0x40U,\r\n\tVOICE_ID_18                            = 0x41U,\r\n\tVOICE_ID_19                            = 0x42U,\r\n\tVOICE_ID_20                            = 0x43U,\r\n\tVOICE_ID_30                            = 0x44U,\r\n\tVOICE_ID_40                            = 0x45U,\r\n\tVOICE_ID_50                            = 0x46U,\r\n\tVOICE_ID_60                            = 0x47U,\r\n\tVOICE_ID_70                            = 0x48U,\r\n\tVOICE_ID_80                            = 0x49U,\r\n\tVOICE_ID_90                            = 0x4AU,\r\n\tVOICE_ID_END                           = 0x4BU,\r\n\r\n\tVOICE_ID_INVALID                       = 0xFFU,\r\n};\r\n\r\ntypedef enum VOICE_ID_t  VOICE_ID_t;\r\n\t\r\nstatic inline void AUDIO_AudioPathOn(void) {\r\n\tGPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_AUDIO_PATH);\r\n}\r\n\r\nstatic inline void AUDIO_AudioPathOff(void) {\r\n\tGPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_AUDIO_PATH);\r\n}\r\n\r\n#ifdef ENABLE_VOICE\r\n\textern VOICE_ID_t        gVoiceID[8];\r\n\textern uint8_t           gVoiceReadIndex;\r\n\textern uint8_t           gVoiceWriteIndex;\r\n\textern volatile uint16_t gCountdownToPlayNextVoice_10ms;\r\n\textern volatile bool     gFlagPlayQueuedVoice;\r\n\textern VOICE_ID_t        gAnotherVoiceID;\r\n\t\r\n\tvoid    AUDIO_PlaySingleVoice(bool bFlag);\r\n\tvoid    AUDIO_SetVoiceID(uint8_t Index, VOICE_ID_t VoiceID);\r\n\tuint8_t AUDIO_SetDigitVoice(uint8_t Index, uint16_t Value);\r\n\tvoid    AUDIO_PlayQueuedVoice(void);\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bitmaps.c",
    "content": "\r\n#include \"bitmaps.h\"\r\n\r\n// all these images are on their right sides\r\n// turn your monitor 90-deg anti-clockwise to see the images\r\n\r\nconst uint8_t BITMAP_POWERSAVE[8] =\r\n        {\r\n                // \"PS\"\r\n                0b00000000,\r\n                0b01111111,\r\n                0b00010001,\r\n                0b00001110,\r\n                0b00000000,\r\n                0b01000110,\r\n                0b01001001,\r\n                0b00110001\r\n\r\n        };\r\n\r\nconst uint8_t BITMAP_TX[6] =\r\n        {\t// \"TX\"\r\n                0b00000000,\r\n                0b00000001,\r\n                0b00000001,\r\n                0b01111111,\r\n                0b00000001,\r\n                0b00000001,\r\n//                0b00000000,\r\n//                0b00000000\r\n        };\r\n\r\nconst uint8_t BITMAP_RX[5] =\r\n        {\t// \"RX\"\r\n                0b00000000,\r\n                0b01111111,\r\n                0b00001001,\r\n                0b00011001,\r\n                0b01100110,\r\n//                0b00000000,\r\n//                0b00000000,\r\n//                0b00000000\r\n        };\r\n\r\nconst uint8_t BITMAP_FM[10] =\r\n        {\t// \"FM\"\r\n                0b00000000,\r\n                0b01111111,\r\n                0b00001001,\r\n                0b00000001,\r\n                0b00000000,\r\n                0b01111111,\r\n                0b00000010,\r\n                0b00001100,\r\n                0b00000010,\r\n                0b01111111\r\n        };\r\n\r\nconst uint8_t BITMAP_BatteryLevel[2] =\r\n        {\r\n                0b01011101,\r\n                0b01011101\r\n        };\r\n\r\n#ifndef ENABLE_REVERSE_BAT_SYMBOL\r\n// Quansheng way (+ pole to the left)\r\nconst uint8_t BITMAP_BatteryLevel1[17] =\r\n        {\r\n                0b00000000,\r\n                0b00111110,\r\n                0b00100010,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b01111111\r\n        };\r\n#else\r\n// reversed (+ pole to the right)\r\n\tconst uint8_t BITMAP_BatteryLevel1[17] =\r\n\t{\r\n\t\t0b00000000,\r\n\t\t0b01111111,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b00100010,\r\n\t\t0b00111110\r\n\t};\r\n#endif\r\n\r\nconst uint8_t BITMAP_USB_C[9] =\r\n        {\t// USB symbol\r\n                0b00000000,\r\n                0b00011100,\r\n                0b00100111,\r\n                0b01000100,\r\n                0b01000100,\r\n                0b01000100,\r\n                0b01000100,\r\n                0b00100111,\r\n                0b00011100\r\n        };\r\n\r\nconst uint8_t BITMAP_KeyLock[6] =\r\n        {\t// teeny padlock symbol\r\n                0b00000000,\r\n                0b01111100,\r\n                0b01000110,\r\n                0b01000101,\r\n                0b01000110,\r\n                0b01111100\r\n        };\r\n\r\nconst uint8_t BITMAP_F_Key[6] =\r\n        {\t// F-Key symbol\r\n                0b00000000,\r\n                0b01011111,\r\n                0b01000101,\r\n                0b01000101,\r\n                0b01000101,\r\n                0b01000001\r\n        };\r\n\r\n#ifdef ENABLE_VOX\r\nconst uint8_t BITMAP_VOX[18] =\r\n\t{\t// \"VOX\"\r\n\t\t0b00000000,\r\n\t\t0b00011111,\r\n\t\t0b00100000,\r\n\t\t0b01000000,\r\n\t\t0b00100000,\r\n\t\t0b00011111,\r\n\t\t0b00000000,\r\n\t\t0b00111110,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b01000001,\r\n\t\t0b00111110,\r\n\t\t0b00000000,\r\n\t\t0b01100011,\r\n\t\t0b00010100,\r\n\t\t0b00001000,\r\n\t\t0b00010100,\r\n\t\t0b01100011\r\n\t};\r\n#endif\r\n\r\n\r\n// 'XB' (cross-band/cross-VFO)\r\nconst uint8_t BITMAP_XB[12] =\r\n        {\t// \"XB\"\r\n                0b00000000,\r\n                0b01100011,\r\n                0b00010100,\r\n                0b00001000,\r\n                0b00010100,\r\n                0b01100011,\r\n                0b00000000,\r\n                0b01111111,\r\n                0b01001001,\r\n                0b01001001,\r\n                0b01001001,\r\n                0b00110110\r\n        };\r\n\r\n\r\nconst uint8_t BITMAP_TDR1[16] =\r\n        {\t// \"DWR\"\r\n                0b00000000,\r\n                0b01111111,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b00111110,\r\n                0b00000000,\r\n                0b01111111,\r\n                0b00100000,\r\n                0b00011000,\r\n                0b00100000,\r\n                0b01111111,\r\n                0b00000000,\r\n                0b01111111,\r\n                0b00011001,\r\n                0b00101001,\r\n                0b01000110\r\n        };\r\n\r\nconst uint8_t BITMAP_TDR2[9] =\r\n        {\t// \"><\" .. DW on hold\r\n//                0b00000000,\r\n                0b00100010,\r\n                0b00110110,\r\n                0b00011100,\r\n                0b00001000,\r\n                0b00000000,\r\n                0b00001000,\r\n                0b00011100,\r\n                0b00110110,\r\n                0b00100010,\r\n        };\r\n\r\n#ifdef ENABLE_VOICE\r\nconst uint8_t BITMAP_VoicePrompt[9] =\r\n\t{\r\n\t\t0b00000000,\r\n\t\t0b00011000,\r\n\t\t0b00011000,\r\n\t\t0b00100100,\r\n\t\t0b00100100,\r\n\t\t0b01000010,\r\n\t\t0b01000010,\r\n\t\t0b11111111,\r\n\t\t0b00011000\r\n\t};\r\n#endif\r\n\r\n#ifdef ENABLE_NOAA\r\nconst uint8_t BITMAP_NOAA[11] =\r\n\t{\t// \"NS\"\r\n\t\t0b00000000,\r\n\t\t0b01111111,\r\n\t\t0b00000100,\r\n\t\t0b00001000,\r\n\t\t0b00010000,\r\n\t\t0b01111111,\r\n\t\t0b00000000,\r\n\t\t0b01000110,\r\n\t\t0b01001001,\r\n\t\t0b01001001,\r\n\t\t0b00110001\r\n\t};\r\n#endif\r\n\r\nconst uint8_t BITMAP_Antenna[5] =\r\n        {\r\n                0b00000011,\r\n                0b00000101,\r\n                0b01111111,\r\n                0b00000101,\r\n                0b00000011\r\n        };\r\n\r\nconst uint8_t BITMAP_VFO_Default[7] =\r\n        {\r\n//                0b00000000,\r\n                0b01111111,\r\n                0b01111111,\r\n                0b00111110,\r\n                0b00111110,\r\n                0b00011100,\r\n                0b00011100,\r\n                0b00001000\r\n        };\r\n\r\nconst uint8_t BITMAP_VFO_NotDefault[7] =\r\n        {\r\n//                0b00000000,\r\n                0b01000001,\r\n                0b01000001,\r\n                0b00100010,\r\n                0b00100010,\r\n                0b00010100,\r\n                0b00010100,\r\n                0b00001000\r\n        };\r\n\r\nconst uint8_t BITMAP_ScanList1[3] =\r\n        {\t// 'I' symbol\r\n//                0b00000000,\r\n//                0b00000000,\r\n                0b01000010,\r\n                0b01111110,\r\n                0b01000010,\r\n//                0b00000000\r\n        };\r\n\r\nconst uint8_t BITMAP_ScanList2[5] =\r\n        {\t// 'II' symbol\r\n//                0b00000000,\r\n                0b01000010,\r\n                0b01111110,\r\n                0b01000010,\r\n                0b01111110,\r\n                0b01000010\r\n        };\r\n\r\nconst uint8_t BITMAP_compand[5] =\r\n        {\r\n//                0b00000000,\r\n                0b00111100,\r\n                0b01000010,\r\n                0b01000010,\r\n                0b01000010,\r\n                0b00100100\r\n        };\r\nconst uint8_t BITMAP_RECV[13] =\r\n        {\r\n\r\n\r\n                0x7F, 0x7F, 0x1B, 0x3B, 0x7F, 0x66,0X00,0x63, 0x77, 0x1C, 0x1C, 0x77, 0x63\r\n        };\r\nconst uint8_t BITMAP_SEND[13] =\r\n        {\r\n                0x03, 0x03, 0x7F, 0x7F, 0x03, 0x03,0X00, 0x63, 0x77, 0x1C, 0x1C, 0x77, 0x63\r\n        };\r\n\r\n\r\n#ifdef ENABLE_MESSENGER\r\nconst uint8_t BITMAP_NEWMSG[7] =\r\n{\t// message icon\r\n//\t0b00000000,\r\n\t0b01111110,\r\n\t0b01000110,\r\n\t0b01001010,\r\n\t0b01010010,\r\n\t0b01001010,\r\n\t0b01000110,\r\n\t0b01111110,\r\n};\r\nconst uint8_t BITMAP_t[6] =\r\n        {\t// \"t\"\r\n                0b00000000,\r\n                0b00000100,\r\n                0b00000100,\r\n                0b00111111,\r\n                0b01000100,\r\n                0b00100100,\r\n\r\n        };\r\n\r\nconst uint8_t BITMAP_1[6] =\r\n        {\t// \"1\"\r\n                0b00000000,\r\n                0b00000000,\r\n                0b01000010,\r\n                0b01111111,\r\n                0b01000000,\r\n                0b00000000,\r\n\r\n        };\r\n#endif\r\n#include \"ui/helper.h\"\r\n#ifdef ENABLE_PINYIN\r\nconst uint8_t BITMAP_ARRAY_DOWN[5] =\r\n        {\r\n                0b00000011,\r\n                0b00001111,\r\n                0b00011111,\r\n                0b00001111,\r\n                0b00000011\r\n        };\r\nconst uint8_t BITMAP_ARRAY_UP[5] =\r\n        {\r\n                0b01100000,\r\n                0b01111000,\r\n                0b01111110,\r\n                0b01111000,\r\n                0b01100000\r\n        };\r\n const uint8_t BITMAP_CN[7] ={\r\n                0b00111100,\r\n                0b00100100,\r\n                0b00100100,\r\n                0b11111111,\r\n                0b00100100,\r\n                0b00100100,\r\n                0b00111100,\r\n\r\n};\r\n const uint8_t BITMAP_POINT[2] ={\r\n                0b0000011,\r\n                0b00110000,\r\n\r\n\r\n};\r\n\r\n\r\n#endif"
  },
  {
    "path": "bitmaps.h",
    "content": "\r\n#ifndef BITMAP_H\r\n#define BITMAP_H\r\n\r\n#include <stdint.h>\r\n\r\nextern const uint8_t BITMAP_POWERSAVE[8];\r\nextern const uint8_t BITMAP_TX[6];\r\nextern const uint8_t BITMAP_RX[5];\r\nextern const uint8_t BITMAP_FM[10];\r\nextern const uint8_t BITMAP_BatteryLevel[2];\r\nextern const uint8_t BITMAP_BatteryLevel1[17];\r\n\r\nextern const uint8_t BITMAP_USB_C[9];\r\n\r\nextern const uint8_t BITMAP_KeyLock[6];\r\n\r\nextern const uint8_t BITMAP_F_Key[6];\r\n\r\n#ifdef ENABLE_VOX\r\nextern const uint8_t BITMAP_VOX[18];\r\n#endif\r\n\r\nextern const uint8_t BITMAP_XB[12];\r\n\r\nextern const uint8_t BITMAP_TDR1[16];\r\nextern const uint8_t BITMAP_TDR2[9];\r\n\r\n#ifdef ENABLE_VOICE\r\nextern const uint8_t BITMAP_VoicePrompt[9];\r\n#endif\r\n\r\n#ifdef ENABLE_NOAA\r\nextern const uint8_t BITMAP_NOAA[11];\r\n#endif\r\n\r\nextern const uint8_t BITMAP_Antenna[5];\r\n\r\nextern const uint8_t BITMAP_VFO_Default[7];\r\nextern const uint8_t BITMAP_VFO_NotDefault[7];\r\n\r\nextern const uint8_t BITMAP_ScanList1[3];\r\nextern const uint8_t BITMAP_ScanList2[5];\r\n\r\nextern const uint8_t BITMAP_compand[5];\r\nextern const uint8_t BITMAP_RECV[13] ;\r\nextern const uint8_t BITMAP_SEND[13] ;\r\n#ifdef ENABLE_MESSENGER\r\n\r\nextern const uint8_t BITMAP_1[6] ;\r\nextern const uint8_t BITMAP_t[6] ;\r\nextern const uint8_t BITMAP_NEWMSG[7] ;\r\n#endif\r\n#ifdef ENABLE_PINYIN\r\nextern const uint8_t BITMAP_ARRAY_DOWN[5] ;\r\nextern const uint8_t BITMAP_ARRAY_UP[5] ;\r\nextern const uint8_t BITMAP_CN[7] ;\r\n\r\n#endif\r\n#endif"
  },
  {
    "path": "board.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <string.h>\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"board.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"bsp/dp32g030/portcon.h\"\r\n#include \"bsp/dp32g030/saradc.h\"\r\n#include \"bsp/dp32g030/syscon.h\"\r\n#include \"driver/adc.h\"\r\n#include \"driver/backlight.h\"\r\n#include \"ARMCM0.h\"\r\n#include \"bsp/dp32g030/pmu.h\"\r\n#include \"bsp/dp32g030/saradc.h\"\r\n#include \"bsp/dp32g030/syscon.h\"\r\n#include \"sram-overlay.h\"\r\n#include \"driver/eeprom.h\"\r\n#ifdef ENABLE_FMRADIO\r\n#include \"driver/bk1080.h\"\r\n#endif\r\n\r\n#include \"driver/crc.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/flash.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/system.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"frequencies.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n\r\n#if defined(ENABLE_OVERLAY)\r\n#include \"sram-overlay.h\"\r\n#endif\r\n\r\n#if defined(ENABLE_OVERLAY)\r\nvoid BOARD_FLASH_Init(void)\r\n    {\r\n        FLASH_Init(FLASH_READ_MODE_1_CYCLE);\r\n        FLASH_ConfigureTrimValues();\r\n        SYSTEM_ConfigureClocks();\r\n\r\n        overlay_FLASH_MainClock       = 48000000;\r\n        overlay_FLASH_ClockMultiplier = 48;\r\n\r\n        FLASH_Init(FLASH_READ_MODE_2_CYCLE);\r\n    }\r\n#endif\r\n\r\nvoid BOARD_GPIO_Init(void) {\r\n    GPIOA->DIR |= 0\r\n                  // A7 = UART1 TX default as OUTPUT from bootloader!\r\n                  // A8 = UART1 RX default as INPUT from bootloader!\r\n                  // Key pad + I2C\r\n                  | GPIO_DIR_10_BITS_OUTPUT\r\n                  // Key pad + I2C\r\n                  | GPIO_DIR_11_BITS_OUTPUT\r\n                  // Key pad + Voice chip\r\n                  | GPIO_DIR_12_BITS_OUTPUT\r\n                  // Key pad + Voice chip\r\n                  | GPIO_DIR_13_BITS_OUTPUT;\r\n    GPIOA->DIR &= ~(0\r\n                    // Key pad\r\n                    | GPIO_DIR_3_MASK // INPUT\r\n                    // Key pad\r\n                    | GPIO_DIR_4_MASK // INPUT\r\n                    // Key pad\r\n                    | GPIO_DIR_5_MASK // INPUT\r\n                    // Key pad\r\n                    | GPIO_DIR_6_MASK // INPUT\r\n    );\r\n    GPIOB->DIR |= 0\r\n                  // ST7565\r\n                  | GPIO_DIR_9_BITS_OUTPUT\r\n                  // ST7565 + SWD IO\r\n                  | GPIO_DIR_11_BITS_OUTPUT\r\n                  // B14 = SWD_CLK assumed INPUT by default\r\n                  // BK1080\r\n                  | GPIO_DIR_15_BITS_OUTPUT;\r\n    GPIOC->DIR |= 0\r\n                  // BK4819 SCN\r\n                  | GPIO_DIR_0_BITS_OUTPUT\r\n                  // BK4819 SCL\r\n                  | GPIO_DIR_1_BITS_OUTPUT\r\n                  // BK4819 SDA\r\n                  | GPIO_DIR_2_BITS_OUTPUT\r\n                  // Flash light\r\n                  | GPIO_DIR_3_BITS_OUTPUT\r\n                  // Speaker\r\n                  | GPIO_DIR_4_BITS_OUTPUT;\r\n    GPIOC->DIR &= ~(0\r\n                    // PTT button\r\n                    | GPIO_DIR_5_MASK // INPUT\r\n    );\r\n\r\n#if defined(ENABLE_FMRADIO)\r\n    GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_BK1080);\r\n#endif\r\n}\r\n\r\nvoid BOARD_PORTCON_Init(void) {\r\n    // PORT A pin selection\r\n\r\n    PORTCON_PORTA_SEL0 &= ~(0\r\n                            // Key pad\r\n                            | PORTCON_PORTA_SEL0_A3_MASK\r\n                            // Key pad\r\n                            | PORTCON_PORTA_SEL0_A4_MASK\r\n                            // Key pad\r\n                            | PORTCON_PORTA_SEL0_A5_MASK\r\n                            // Key pad\r\n                            | PORTCON_PORTA_SEL0_A6_MASK\r\n    );\r\n    PORTCON_PORTA_SEL0 |= 0\r\n                          // Key pad\r\n                          | PORTCON_PORTA_SEL0_A3_BITS_GPIOA3\r\n                          // Key pad\r\n                          | PORTCON_PORTA_SEL0_A4_BITS_GPIOA4\r\n                          // Key pad\r\n                          | PORTCON_PORTA_SEL0_A5_BITS_GPIOA5\r\n                          // Key pad\r\n                          | PORTCON_PORTA_SEL0_A6_BITS_GPIOA6\r\n                          // UART1 TX, wasn't cleared in previous step / relying on default value!\r\n                          | PORTCON_PORTA_SEL0_A7_BITS_UART1_TX;\r\n\r\n    PORTCON_PORTA_SEL1 &= ~(0\r\n                            // Key pad + I2C\r\n                            | PORTCON_PORTA_SEL1_A10_MASK\r\n                            // Key pad + I2C\r\n                            | PORTCON_PORTA_SEL1_A11_MASK\r\n                            // Key pad + Voice chip\r\n                            | PORTCON_PORTA_SEL1_A12_MASK\r\n                            // Key pad + Voice chip\r\n                            | PORTCON_PORTA_SEL1_A13_MASK\r\n    );\r\n    PORTCON_PORTA_SEL1 |= 0\r\n                          // UART1 RX, wasn't cleared in previous step / relying on default value!\r\n                          | PORTCON_PORTA_SEL1_A8_BITS_UART1_RX\r\n                          // Battery voltage, wasn't cleared in previous step / relying on default value!\r\n                          | PORTCON_PORTA_SEL1_A9_BITS_SARADC_CH4\r\n                          // Key pad + I2C\r\n                          | PORTCON_PORTA_SEL1_A10_BITS_GPIOA10\r\n                          // Key pad + I2C\r\n                          | PORTCON_PORTA_SEL1_A11_BITS_GPIOA11\r\n                          // Key pad + Voice chip\r\n                          | PORTCON_PORTA_SEL1_A12_BITS_GPIOA12\r\n                          // Key pad + Voice chip\r\n                          | PORTCON_PORTA_SEL1_A13_BITS_GPIOA13\r\n                          // Battery Current, wasn't cleared in previous step / relying on default value!\r\n                          | PORTCON_PORTA_SEL1_A14_BITS_SARADC_CH9;\r\n\r\n    // PORT B pin selection\r\n\r\n    PORTCON_PORTB_SEL0 &= ~(0\r\n                            // SPI0 SSN\r\n                            | PORTCON_PORTB_SEL0_B7_MASK\r\n    );\r\n    PORTCON_PORTB_SEL0 |= 0\r\n                          // SPI0 SSN\r\n                          | PORTCON_PORTB_SEL0_B7_BITS_SPI0_SSN;\r\n\r\n    PORTCON_PORTB_SEL1 &= ~(0\r\n                            // ST7565\r\n                            | PORTCON_PORTB_SEL1_B9_MASK\r\n                            // ST7565 + SWD IO\r\n                            | PORTCON_PORTB_SEL1_B11_MASK\r\n                            // SWD CLK\r\n                            | PORTCON_PORTB_SEL1_B14_MASK\r\n                            // BK1080\r\n                            | PORTCON_PORTB_SEL1_B15_MASK\r\n    );\r\n    PORTCON_PORTB_SEL1 |= 0\r\n                          // SPI0 CLK, wasn't cleared in previous step / relying on default value!\r\n                          | PORTCON_PORTB_SEL1_B8_BITS_SPI0_CLK\r\n                          // ST7565\r\n                          | PORTCON_PORTB_SEL1_B9_BITS_GPIOB9\r\n                          // SPI0 MOSI, wasn't cleared in previous step / relying on default value!\r\n                          | PORTCON_PORTB_SEL1_B10_BITS_SPI0_MOSI\r\n                          #if defined(ENABLE_SWD)\r\n                          // SWD IO\r\n\t\t| PORTCON_PORTB_SEL1_B11_BITS_SWDIO\r\n\t\t// SWD CLK\r\n\t\t| PORTCON_PORTB_SEL1_B14_BITS_SWCLK\r\n                          #else\r\n                          // ST7565\r\n                          | PORTCON_PORTB_SEL1_B11_BITS_GPIOB11\r\n#endif\r\n            ;\r\n\r\n    // PORT C pin selection\r\n\r\n    PORTCON_PORTC_SEL0 &= ~(0\r\n                            // BK4819 SCN\r\n                            | PORTCON_PORTC_SEL0_C0_MASK\r\n                            // BK4819 SCL\r\n                            | PORTCON_PORTC_SEL0_C1_MASK\r\n                            // BK4819 SDA\r\n                            | PORTCON_PORTC_SEL0_C2_MASK\r\n                            // Flash light\r\n                            | PORTCON_PORTC_SEL0_C3_MASK\r\n                            // Speaker\r\n                            | PORTCON_PORTC_SEL0_C4_MASK\r\n                            // PTT button\r\n                            | PORTCON_PORTC_SEL0_C5_MASK\r\n    );\r\n\r\n    // PORT A pin configuration\r\n\r\n    PORTCON_PORTA_IE |= 0\r\n                        // Keypad\r\n                        | PORTCON_PORTA_IE_A3_BITS_ENABLE\r\n                        // Keypad\r\n                        | PORTCON_PORTA_IE_A4_BITS_ENABLE\r\n                        // Keypad\r\n                        | PORTCON_PORTA_IE_A5_BITS_ENABLE\r\n                        // Keypad\r\n                        | PORTCON_PORTA_IE_A6_BITS_ENABLE\r\n                        // A7 = UART1 TX disabled by default\r\n                        // UART1 RX\r\n                        | PORTCON_PORTA_IE_A8_BITS_ENABLE;\r\n    PORTCON_PORTA_IE &= ~(0\r\n                          // Keypad + I2C\r\n                          | PORTCON_PORTA_IE_A10_MASK\r\n                          // Keypad + I2C\r\n                          | PORTCON_PORTA_IE_A11_MASK\r\n                          // Keypad + Voice chip\r\n                          | PORTCON_PORTA_IE_A12_MASK\r\n                          // Keypad + Voice chip\r\n                          | PORTCON_PORTA_IE_A13_MASK\r\n    );\r\n\r\n    PORTCON_PORTA_PU |= 0\r\n                        // Keypad\r\n                        | PORTCON_PORTA_PU_A3_BITS_ENABLE\r\n                        // Keypad\r\n                        | PORTCON_PORTA_PU_A4_BITS_ENABLE\r\n                        // Keypad\r\n                        | PORTCON_PORTA_PU_A5_BITS_ENABLE\r\n                        // Keypad\r\n                        | PORTCON_PORTA_PU_A6_BITS_ENABLE;\r\n    PORTCON_PORTA_PU &= ~(0\r\n                          // Keypad + I2C\r\n                          | PORTCON_PORTA_PU_A10_MASK\r\n                          // Keypad + I2C\r\n                          | PORTCON_PORTA_PU_A11_MASK\r\n                          // Keypad + Voice chip\r\n                          | PORTCON_PORTA_PU_A12_MASK\r\n                          // Keypad + Voice chip\r\n                          | PORTCON_PORTA_PU_A13_MASK\r\n    );\r\n\r\n    PORTCON_PORTA_PD &= ~(0\r\n                          // Keypad\r\n                          | PORTCON_PORTA_PD_A3_MASK\r\n                          // Keypad\r\n                          | PORTCON_PORTA_PD_A4_MASK\r\n                          // Keypad\r\n                          | PORTCON_PORTA_PD_A5_MASK\r\n                          // Keypad\r\n                          | PORTCON_PORTA_PD_A6_MASK\r\n                          // Keypad + I2C\r\n                          | PORTCON_PORTA_PD_A10_MASK\r\n                          // Keypad + I2C\r\n                          | PORTCON_PORTA_PD_A11_MASK\r\n                          // Keypad + Voice chip\r\n                          | PORTCON_PORTA_PD_A12_MASK\r\n                          // Keypad + Voice chip\r\n                          | PORTCON_PORTA_PD_A13_MASK\r\n    );\r\n\r\n    PORTCON_PORTA_OD |= 0\r\n                        // Keypad\r\n                        | PORTCON_PORTA_OD_A3_BITS_ENABLE\r\n                        // Keypad\r\n                        | PORTCON_PORTA_OD_A4_BITS_ENABLE\r\n                        // Keypad\r\n                        | PORTCON_PORTA_OD_A5_BITS_ENABLE\r\n                        // Keypad\r\n                        | PORTCON_PORTA_OD_A6_BITS_ENABLE;\r\n    PORTCON_PORTA_OD &= ~(0\r\n                          // Keypad + I2C\r\n                          | PORTCON_PORTA_OD_A10_MASK\r\n                          // Keypad + I2C\r\n                          | PORTCON_PORTA_OD_A11_MASK\r\n                          // Keypad + Voice chip\r\n                          | PORTCON_PORTA_OD_A12_MASK\r\n                          // Keypad + Voice chip\r\n                          | PORTCON_PORTA_OD_A13_MASK\r\n    );\r\n\r\n    // PORT B pin configuration\r\n\r\n    PORTCON_PORTB_IE |= 0\r\n                        | PORTCON_PORTB_IE_B14_BITS_ENABLE;\r\n    PORTCON_PORTB_IE &= ~(0\r\n                          // Back light\r\n                          | PORTCON_PORTB_IE_B6_MASK\r\n                          // UART1\r\n                          | PORTCON_PORTB_IE_B7_MASK\r\n                          | PORTCON_PORTB_IE_B8_MASK\r\n                          // ST7565\r\n                          | PORTCON_PORTB_IE_B9_MASK\r\n                          // SPI0 MOSI\r\n                          | PORTCON_PORTB_IE_B10_MASK\r\n                          #if !defined(ENABLE_SWD)\r\n                          // ST7565\r\n                          | PORTCON_PORTB_IE_B11_MASK\r\n                          #endif\r\n                          // BK1080\r\n                          | PORTCON_PORTB_IE_B15_MASK\r\n    );\r\n\r\n    PORTCON_PORTB_PU &= ~(0\r\n                          // Back light\r\n                          | PORTCON_PORTB_PU_B6_MASK\r\n                          // ST7565\r\n                          | PORTCON_PORTB_PU_B9_MASK\r\n                          // ST7565 + SWD IO\r\n                          | PORTCON_PORTB_PU_B11_MASK\r\n                          // SWD CLK\r\n                          | PORTCON_PORTB_PU_B14_MASK\r\n                          // BK1080\r\n                          | PORTCON_PORTB_PU_B15_MASK\r\n    );\r\n\r\n    PORTCON_PORTB_PD &= ~(0\r\n                          // Back light\r\n                          | PORTCON_PORTB_PD_B6_MASK\r\n                          // ST7565\r\n                          | PORTCON_PORTB_PD_B9_MASK\r\n                          // ST7565 + SWD IO\r\n                          | PORTCON_PORTB_PD_B11_MASK\r\n                          // SWD CLK\r\n                          | PORTCON_PORTB_PD_B14_MASK\r\n                          // BK1080\r\n                          | PORTCON_PORTB_PD_B15_MASK\r\n    );\r\n\r\n    PORTCON_PORTB_OD &= ~(0\r\n                          // Back light\r\n                          | PORTCON_PORTB_OD_B6_MASK\r\n                          // ST7565\r\n                          | PORTCON_PORTB_OD_B9_MASK\r\n                          // ST7565 + SWD IO\r\n                          | PORTCON_PORTB_OD_B11_MASK\r\n                          // BK1080\r\n                          | PORTCON_PORTB_OD_B15_MASK\r\n    );\r\n\r\n    PORTCON_PORTB_OD |= 0\r\n                        // SWD CLK\r\n                        | PORTCON_PORTB_OD_B14_BITS_ENABLE;\r\n\r\n    // PORT C pin configuration\r\n\r\n    PORTCON_PORTC_IE |= 0\r\n                        // PTT button\r\n                        | PORTCON_PORTC_IE_C5_BITS_ENABLE;\r\n    PORTCON_PORTC_IE &= ~(0\r\n                          // BK4819 SCN\r\n                          | PORTCON_PORTC_IE_C0_MASK\r\n                          // BK4819 SCL\r\n                          | PORTCON_PORTC_IE_C1_MASK\r\n                          // BK4819 SDA\r\n                          | PORTCON_PORTC_IE_C2_MASK\r\n                          // Flash Light\r\n                          | PORTCON_PORTC_IE_C3_MASK\r\n                          // Speaker\r\n                          | PORTCON_PORTC_IE_C4_MASK\r\n    );\r\n\r\n    PORTCON_PORTC_PU |= 0\r\n                        // PTT button\r\n                        | PORTCON_PORTC_PU_C5_BITS_ENABLE;\r\n    PORTCON_PORTC_PU &= ~(0\r\n                          // BK4819 SCN\r\n                          | PORTCON_PORTC_PU_C0_MASK\r\n                          // BK4819 SCL\r\n                          | PORTCON_PORTC_PU_C1_MASK\r\n                          // BK4819 SDA\r\n                          | PORTCON_PORTC_PU_C2_MASK\r\n                          // Flash Light\r\n                          | PORTCON_PORTC_PU_C3_MASK\r\n                          // Speaker\r\n                          | PORTCON_PORTC_PU_C4_MASK\r\n    );\r\n\r\n    PORTCON_PORTC_PD &= ~(0\r\n                          // BK4819 SCN\r\n                          | PORTCON_PORTC_PD_C0_MASK\r\n                          // BK4819 SCL\r\n                          | PORTCON_PORTC_PD_C1_MASK\r\n                          // BK4819 SDA\r\n                          | PORTCON_PORTC_PD_C2_MASK\r\n                          // Flash Light\r\n                          | PORTCON_PORTC_PD_C3_MASK\r\n                          // Speaker\r\n                          | PORTCON_PORTC_PD_C4_MASK\r\n                          // PTT Button\r\n                          | PORTCON_PORTC_PD_C5_MASK\r\n    );\r\n\r\n    PORTCON_PORTC_OD &= ~(0\r\n                          // BK4819 SCN\r\n                          | PORTCON_PORTC_OD_C0_MASK\r\n                          // BK4819 SCL\r\n                          | PORTCON_PORTC_OD_C1_MASK\r\n                          // BK4819 SDA\r\n                          | PORTCON_PORTC_OD_C2_MASK\r\n                          // Flash Light\r\n                          | PORTCON_PORTC_OD_C3_MASK\r\n                          // Speaker\r\n                          | PORTCON_PORTC_OD_C4_MASK\r\n    );\r\n    PORTCON_PORTC_OD |= 0\r\n                        // BK4819 SCN\r\n                        | PORTCON_PORTC_OD_C0_BITS_DISABLE\r\n                        // BK4819 SCL\r\n                        | PORTCON_PORTC_OD_C1_BITS_DISABLE\r\n                        // BK4819 SDA\r\n                        | PORTCON_PORTC_OD_C2_BITS_DISABLE\r\n                        // Flash Light\r\n                        | PORTCON_PORTC_OD_C3_BITS_DISABLE\r\n                        // Speaker\r\n                        | PORTCON_PORTC_OD_C4_BITS_DISABLE\r\n                        // PTT button\r\n                        | PORTCON_PORTC_OD_C5_BITS_ENABLE;\r\n}\r\n\r\nvoid BOARD_ADC_Init(void) {\r\n\r\n    ADC_Configure();\r\n    ADC_Enable();\r\n    ADC_SoftReset();\r\n}\r\n\r\nvoid BOARD_ADC_GetBatteryInfo(uint16_t *pVoltage, uint16_t *pCurrent) {\r\n    ADC_Start();\r\n    while (!ADC_CheckEndOfConversion(ADC_CH9)) {}\r\n    *pVoltage = ADC_GetValue(ADC_CH4);\r\n    *pCurrent = ADC_GetValue(ADC_CH9);\r\n}\r\n\r\nvoid BOARD_Init(void) {\r\n    BOARD_PORTCON_Init();\r\n    BOARD_GPIO_Init();\r\n    BACKLIGHT_InitHardware();\r\n    BOARD_ADC_Init();\r\n    ST7565_Init();\r\n#ifdef ENABLE_FMRADIO\r\n    BK1080_Init(0, false);\r\n#endif\r\n\r\n#if defined(ENABLE_UART) || defined(ENABLED_AIRCOPY)\r\n    CRC_Init();\r\n#endif\r\n\r\n}\r\n\r\nvoid write_to_memory(uint32_t address, uint32_t data) {\r\n    // ֵַתΪָ\r\n    uint32_t *target_address = (uint32_t *) address;\r\n    // Ŀַд\r\n    *target_address = data;\r\n    // Ϊ˱Żȷ벻ᱻŻ\r\n    volatile uint32_t read_back = *target_address;\r\n}\r\n//JUMP_TO_FLASH(0xa10A,0x20003ff0);\r\nvoid JUMP_TO_FLASH(uint32_t flash_add,uint32_t stack_add)\r\n{\r\n    __disable_irq();\r\n    ClearStack();\r\n    __set_MSP(stack_add);\r\n    __set_PC(flash_add);\r\n}"
  },
  {
    "path": "board.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef BOARD_H\r\n#define BOARD_H\r\n\r\n#include <stdint.h>\r\n#include <stdbool.h>\r\n\r\nvoid     BOARD_FLASH_Init(void);\r\nvoid     BOARD_GPIO_Init(void);\r\nvoid     BOARD_PORTCON_Init(void);\r\nvoid     BOARD_ADC_Init(void);\r\nvoid     BOARD_ADC_GetBatteryInfo(uint16_t *pVoltage, uint16_t *pCurrent);\r\nvoid     BOARD_Init(void);\r\nvoid JUMP_TO_FLASH(uint32_t flash_add,uint32_t stack_add);\r\n        void write_to_memory(uint32_t address, uint32_t data) ;\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/aes.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_AES_H\r\n#define HARDWARE_DP32G030_AES_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- AES -------- */\r\n#define AES_BASE_ADDR                  0x400BD000U\r\n#define AES_BASE_SIZE                  0x00000800U\r\n\r\n#define AES_CR_ADDR                    (AES_BASE_ADDR + 0x0000U)\r\n#define AES_CR                         (*(volatile uint32_t *)AES_CR_ADDR)\r\n#define AES_CR_EN_SHIFT                0\r\n#define AES_CR_EN_WIDTH                1\r\n#define AES_CR_EN_MASK                 (((1U << AES_CR_EN_WIDTH) - 1U) << AES_CR_EN_SHIFT)\r\n#define AES_CR_EN_VALUE_DISABLE        0U\r\n#define AES_CR_EN_BITS_DISABLE         (AES_CR_EN_VALUE_DISABLE << AES_CR_EN_SHIFT)\r\n#define AES_CR_EN_VALUE_ENABLE         1U\r\n#define AES_CR_EN_BITS_ENABLE          (AES_CR_EN_VALUE_ENABLE << AES_CR_EN_SHIFT)\r\n\r\n#define AES_CR_CHMOD_SHIFT             5\r\n#define AES_CR_CHMOD_WIDTH             2\r\n#define AES_CR_CHMOD_MASK              (((1U << AES_CR_CHMOD_WIDTH) - 1U) << AES_CR_CHMOD_SHIFT)\r\n#define AES_CR_CHMOD_VALUE_ECB         0U\r\n#define AES_CR_CHMOD_BITS_ECB          (AES_CR_CHMOD_VALUE_ECB << AES_CR_CHMOD_SHIFT)\r\n#define AES_CR_CHMOD_VALUE_CBC         1U\r\n#define AES_CR_CHMOD_BITS_CBC          (AES_CR_CHMOD_VALUE_CBC << AES_CR_CHMOD_SHIFT)\r\n#define AES_CR_CHMOD_VALUE_CTR         2U\r\n#define AES_CR_CHMOD_BITS_CTR          (AES_CR_CHMOD_VALUE_CTR << AES_CR_CHMOD_SHIFT)\r\n\r\n#define AES_CR_CCFC_SHIFT              7\r\n#define AES_CR_CCFC_WIDTH              1\r\n#define AES_CR_CCFC_MASK               (((1U << AES_CR_CCFC_WIDTH) - 1U) << AES_CR_CCFC_SHIFT)\r\n#define AES_CR_CCFC_VALUE_SET          1U\r\n#define AES_CR_CCFC_BITS_SET           (AES_CR_CCFC_VALUE_SET << AES_CR_CCFC_SHIFT)\r\n\r\n#define AES_SR_ADDR                    (AES_BASE_ADDR + 0x0004U)\r\n#define AES_SR                         (*(volatile uint32_t *)AES_SR_ADDR)\r\n#define AES_SR_CCF_SHIFT               0\r\n#define AES_SR_CCF_WIDTH               1\r\n#define AES_SR_CCF_MASK                (((1U << AES_SR_CCF_WIDTH) - 1U) << AES_SR_CCF_SHIFT)\r\n#define AES_SR_CCF_VALUE_NOT_COMPLETE  0U\r\n#define AES_SR_CCF_BITS_NOT_COMPLETE   (AES_SR_CCF_VALUE_NOT_COMPLETE << AES_SR_CCF_SHIFT)\r\n#define AES_SR_CCF_VALUE_COMPLETE      1U\r\n#define AES_SR_CCF_BITS_COMPLETE       (AES_SR_CCF_VALUE_COMPLETE << AES_SR_CCF_SHIFT)\r\n\r\n#define AES_DINR_ADDR                  (AES_BASE_ADDR + 0x0008U)\r\n#define AES_DINR                       (*(volatile uint32_t *)AES_DINR_ADDR)\r\n#define AES_DOUTR_ADDR                 (AES_BASE_ADDR + 0x000CU)\r\n#define AES_DOUTR                      (*(volatile uint32_t *)AES_DOUTR_ADDR)\r\n#define AES_KEYR0_ADDR                 (AES_BASE_ADDR + 0x0010U)\r\n#define AES_KEYR0                      (*(volatile uint32_t *)AES_KEYR0_ADDR)\r\n#define AES_KEYR1_ADDR                 (AES_BASE_ADDR + 0x0014U)\r\n#define AES_KEYR1                      (*(volatile uint32_t *)AES_KEYR1_ADDR)\r\n#define AES_KEYR2_ADDR                 (AES_BASE_ADDR + 0x0018U)\r\n#define AES_KEYR2                      (*(volatile uint32_t *)AES_KEYR2_ADDR)\r\n#define AES_KEYR3_ADDR                 (AES_BASE_ADDR + 0x001CU)\r\n#define AES_KEYR3                      (*(volatile uint32_t *)AES_KEYR3_ADDR)\r\n#define AES_IVR0_ADDR                  (AES_BASE_ADDR + 0x0020U)\r\n#define AES_IVR0                       (*(volatile uint32_t *)AES_IVR0_ADDR)\r\n#define AES_IVR1_ADDR                  (AES_BASE_ADDR + 0x0024U)\r\n#define AES_IVR1                       (*(volatile uint32_t *)AES_IVR1_ADDR)\r\n#define AES_IVR2_ADDR                  (AES_BASE_ADDR + 0x0028U)\r\n#define AES_IVR2                       (*(volatile uint32_t *)AES_IVR2_ADDR)\r\n#define AES_IVR3_ADDR                  (AES_BASE_ADDR + 0x002CU)\r\n#define AES_IVR3                       (*(volatile uint32_t *)AES_IVR3_ADDR)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/crc.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_CRC_H\r\n#define HARDWARE_DP32G030_CRC_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- CRC -------- */\r\n#define CRC_BASE_ADDR                              0x40003000U\r\n#define CRC_BASE_SIZE                              0x00000800U\r\n\r\n#define CRC_CR_ADDR                                (CRC_BASE_ADDR + 0x0000U)\r\n#define CRC_CR                                     (*(volatile uint32_t *)CRC_CR_ADDR)\r\n#define CRC_CR_CRC_EN_SHIFT                        0\r\n#define CRC_CR_CRC_EN_WIDTH                        1\r\n#define CRC_CR_CRC_EN_MASK                         (((1U << CRC_CR_CRC_EN_WIDTH) - 1U) << CRC_CR_CRC_EN_SHIFT)\r\n#define CRC_CR_CRC_EN_VALUE_DISABLE                0U\r\n#define CRC_CR_CRC_EN_BITS_DISABLE                 (CRC_CR_CRC_EN_VALUE_DISABLE << CRC_CR_CRC_EN_SHIFT)\r\n#define CRC_CR_CRC_EN_VALUE_ENABLE                 1U\r\n#define CRC_CR_CRC_EN_BITS_ENABLE                  (CRC_CR_CRC_EN_VALUE_ENABLE << CRC_CR_CRC_EN_SHIFT)\r\n\r\n#define CRC_CR_INPUT_REV_SHIFT                     1\r\n#define CRC_CR_INPUT_REV_WIDTH                     1\r\n#define CRC_CR_INPUT_REV_MASK                      (((1U << CRC_CR_INPUT_REV_WIDTH) - 1U) << CRC_CR_INPUT_REV_SHIFT)\r\n#define CRC_CR_INPUT_REV_VALUE_NORMAL              0U\r\n#define CRC_CR_INPUT_REV_BITS_NORMAL               (CRC_CR_INPUT_REV_VALUE_NORMAL << CRC_CR_INPUT_REV_SHIFT)\r\n#define CRC_CR_INPUT_REV_VALUE_REVERSED            1U\r\n#define CRC_CR_INPUT_REV_BITS_REVERSED             (CRC_CR_INPUT_REV_VALUE_REVERSED << CRC_CR_INPUT_REV_SHIFT)\r\n\r\n#define CRC_CR_INPUT_INV_SHIFT                     2\r\n#define CRC_CR_INPUT_INV_WIDTH                     2\r\n#define CRC_CR_INPUT_INV_MASK                      (((1U << CRC_CR_INPUT_INV_WIDTH) - 1U) << CRC_CR_INPUT_INV_SHIFT)\r\n#define CRC_CR_INPUT_INV_VALUE_NORMAL              0U\r\n#define CRC_CR_INPUT_INV_BITS_NORMAL               (CRC_CR_INPUT_INV_VALUE_NORMAL << CRC_CR_INPUT_INV_SHIFT)\r\n#define CRC_CR_INPUT_INV_VALUE_BIT_INVERTED        1U\r\n#define CRC_CR_INPUT_INV_BITS_BIT_INVERTED         (CRC_CR_INPUT_INV_VALUE_BIT_INVERTED << CRC_CR_INPUT_INV_SHIFT)\r\n#define CRC_CR_INPUT_INV_VALUE_BYTE_INVERTED       2U\r\n#define CRC_CR_INPUT_INV_BITS_BYTE_INVERTED        (CRC_CR_INPUT_INV_VALUE_BYTE_INVERTED << CRC_CR_INPUT_INV_SHIFT)\r\n#define CRC_CR_INPUT_INV_VALUE_BIT_BYTE_INVERTED   3U\r\n#define CRC_CR_INPUT_INV_BITS_BIT_BYTE_INVERTED    (CRC_CR_INPUT_INV_VALUE_BIT_BYTE_INVERTED << CRC_CR_INPUT_INV_SHIFT)\r\n\r\n#define CRC_CR_OUTPUT_REV_SHIFT                    4\r\n#define CRC_CR_OUTPUT_REV_WIDTH                    1\r\n#define CRC_CR_OUTPUT_REV_MASK                     (((1U << CRC_CR_OUTPUT_REV_WIDTH) - 1U) << CRC_CR_OUTPUT_REV_SHIFT)\r\n#define CRC_CR_OUTPUT_REV_VALUE_NORMAL             0U\r\n#define CRC_CR_OUTPUT_REV_BITS_NORMAL              (CRC_CR_OUTPUT_REV_VALUE_NORMAL << CRC_CR_OUTPUT_REV_SHIFT)\r\n#define CRC_CR_OUTPUT_REV_VALUE_REVERSED           1U\r\n#define CRC_CR_OUTPUT_REV_BITS_REVERSED            (CRC_CR_OUTPUT_REV_VALUE_REVERSED << CRC_CR_OUTPUT_REV_SHIFT)\r\n\r\n#define CRC_CR_OUTPUT_INV_SHIFT                    5\r\n#define CRC_CR_OUTPUT_INV_WIDTH                    2\r\n#define CRC_CR_OUTPUT_INV_MASK                     (((1U << CRC_CR_OUTPUT_INV_WIDTH) - 1U) << CRC_CR_OUTPUT_INV_SHIFT)\r\n#define CRC_CR_OUTPUT_INV_VALUE_NORMAL             0U\r\n#define CRC_CR_OUTPUT_INV_BITS_NORMAL              (CRC_CR_OUTPUT_INV_VALUE_NORMAL << CRC_CR_OUTPUT_INV_SHIFT)\r\n#define CRC_CR_OUTPUT_INV_VALUE_BIT_INVERTED       1U\r\n#define CRC_CR_OUTPUT_INV_BITS_BIT_INVERTED        (CRC_CR_OUTPUT_INV_VALUE_BIT_INVERTED << CRC_CR_OUTPUT_INV_SHIFT)\r\n#define CRC_CR_OUTPUT_INV_VALUE_BYTE_INVERTED      2U\r\n#define CRC_CR_OUTPUT_INV_BITS_BYTE_INVERTED       (CRC_CR_OUTPUT_INV_VALUE_BYTE_INVERTED << CRC_CR_OUTPUT_INV_SHIFT)\r\n#define CRC_CR_OUTPUT_INV_VALUE_BIT_BYTE_INVERTED  3U\r\n#define CRC_CR_OUTPUT_INV_BITS_BIT_BYTE_INVERTED   (CRC_CR_OUTPUT_INV_VALUE_BIT_BYTE_INVERTED << CRC_CR_OUTPUT_INV_SHIFT)\r\n\r\n#define CRC_CR_DATA_WIDTH_SHIFT                    7\r\n#define CRC_CR_DATA_WIDTH_WIDTH                    2\r\n#define CRC_CR_DATA_WIDTH_MASK                     (((1U << CRC_CR_DATA_WIDTH_WIDTH) - 1U) << CRC_CR_DATA_WIDTH_SHIFT)\r\n#define CRC_CR_DATA_WIDTH_VALUE_32                 0U\r\n#define CRC_CR_DATA_WIDTH_BITS_32                  (CRC_CR_DATA_WIDTH_VALUE_32 << CRC_CR_DATA_WIDTH_SHIFT)\r\n#define CRC_CR_DATA_WIDTH_VALUE_16                 1U\r\n#define CRC_CR_DATA_WIDTH_BITS_16                  (CRC_CR_DATA_WIDTH_VALUE_16 << CRC_CR_DATA_WIDTH_SHIFT)\r\n#define CRC_CR_DATA_WIDTH_VALUE_8                  2U\r\n#define CRC_CR_DATA_WIDTH_BITS_8                   (CRC_CR_DATA_WIDTH_VALUE_8 << CRC_CR_DATA_WIDTH_SHIFT)\r\n\r\n#define CRC_CR_CRC_SEL_SHIFT                       9\r\n#define CRC_CR_CRC_SEL_WIDTH                       2\r\n#define CRC_CR_CRC_SEL_MASK                        (((1U << CRC_CR_CRC_SEL_WIDTH) - 1U) << CRC_CR_CRC_SEL_SHIFT)\r\n#define CRC_CR_CRC_SEL_VALUE_CRC_16_CCITT          0U\r\n#define CRC_CR_CRC_SEL_BITS_CRC_16_CCITT           (CRC_CR_CRC_SEL_VALUE_CRC_16_CCITT << CRC_CR_CRC_SEL_SHIFT)\r\n#define CRC_CR_CRC_SEL_VALUE_CRC_8_ATM             1U\r\n#define CRC_CR_CRC_SEL_BITS_CRC_8_ATM              (CRC_CR_CRC_SEL_VALUE_CRC_8_ATM << CRC_CR_CRC_SEL_SHIFT)\r\n#define CRC_CR_CRC_SEL_VALUE_CRC_16                2U\r\n#define CRC_CR_CRC_SEL_BITS_CRC_16                 (CRC_CR_CRC_SEL_VALUE_CRC_16 << CRC_CR_CRC_SEL_SHIFT)\r\n#define CRC_CR_CRC_SEL_VALUE_CRC_32_IEEE802_3      3U\r\n#define CRC_CR_CRC_SEL_BITS_CRC_32_IEEE802_3       (CRC_CR_CRC_SEL_VALUE_CRC_32_IEEE802_3 << CRC_CR_CRC_SEL_SHIFT)\r\n\r\n#define CRC_IV_ADDR                                (CRC_BASE_ADDR + 0x0004U)\r\n#define CRC_IV                                     (*(volatile uint32_t *)CRC_IV_ADDR)\r\n#define CRC_DATAIN_ADDR                            (CRC_BASE_ADDR + 0x0008U)\r\n#define CRC_DATAIN                                 (*(volatile uint32_t *)CRC_DATAIN_ADDR)\r\n#define CRC_DATAOUT_ADDR                           (CRC_BASE_ADDR + 0x000CU)\r\n#define CRC_DATAOUT                                (*(volatile uint32_t *)CRC_DATAOUT_ADDR)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/dma.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_DMA_H\r\n#define HARDWARE_DP32G030_DMA_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- DMA -------- */\r\n#define DMA_BASE_ADDR                          0x40001000U\r\n#define DMA_BASE_SIZE                          0x00000100U\r\n\r\n#define DMA_CTR_ADDR                           (DMA_BASE_ADDR + 0x0000U)\r\n#define DMA_CTR                                (*(volatile uint32_t *)DMA_CTR_ADDR)\r\n#define DMA_CTR_DMAEN_SHIFT                    0\r\n#define DMA_CTR_DMAEN_WIDTH                    1\r\n#define DMA_CTR_DMAEN_MASK                     (((1U << DMA_CTR_DMAEN_WIDTH) - 1U) << DMA_CTR_DMAEN_SHIFT)\r\n#define DMA_CTR_DMAEN_VALUE_DISABLE            0U\r\n#define DMA_CTR_DMAEN_BITS_DISABLE             (DMA_CTR_DMAEN_VALUE_DISABLE << DMA_CTR_DMAEN_SHIFT)\r\n#define DMA_CTR_DMAEN_VALUE_ENABLE             1U\r\n#define DMA_CTR_DMAEN_BITS_ENABLE              (DMA_CTR_DMAEN_VALUE_ENABLE << DMA_CTR_DMAEN_SHIFT)\r\n\r\n#define DMA_INTEN_ADDR                         (DMA_BASE_ADDR + 0x0004U)\r\n#define DMA_INTEN                              (*(volatile uint32_t *)DMA_INTEN_ADDR)\r\n#define DMA_INTEN_CH0_TC_INTEN_SHIFT           0\r\n#define DMA_INTEN_CH0_TC_INTEN_WIDTH           1\r\n#define DMA_INTEN_CH0_TC_INTEN_MASK            (((1U << DMA_INTEN_CH0_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_TC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH0_TC_INTEN_VALUE_DISABLE   0U\r\n#define DMA_INTEN_CH0_TC_INTEN_BITS_DISABLE    (DMA_INTEN_CH0_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH0_TC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH0_TC_INTEN_VALUE_ENABLE    1U\r\n#define DMA_INTEN_CH0_TC_INTEN_BITS_ENABLE     (DMA_INTEN_CH0_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH0_TC_INTEN_SHIFT)\r\n\r\n#define DMA_INTEN_CH1_TC_INTEN_SHIFT           1\r\n#define DMA_INTEN_CH1_TC_INTEN_WIDTH           1\r\n#define DMA_INTEN_CH1_TC_INTEN_MASK            (((1U << DMA_INTEN_CH1_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_TC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH1_TC_INTEN_VALUE_DISABLE   0U\r\n#define DMA_INTEN_CH1_TC_INTEN_BITS_DISABLE    (DMA_INTEN_CH1_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH1_TC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH1_TC_INTEN_VALUE_ENABLE    1U\r\n#define DMA_INTEN_CH1_TC_INTEN_BITS_ENABLE     (DMA_INTEN_CH1_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH1_TC_INTEN_SHIFT)\r\n\r\n#define DMA_INTEN_CH2_TC_INTEN_SHIFT           2\r\n#define DMA_INTEN_CH2_TC_INTEN_WIDTH           1\r\n#define DMA_INTEN_CH2_TC_INTEN_MASK            (((1U << DMA_INTEN_CH2_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_TC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH2_TC_INTEN_VALUE_DISABLE   0U\r\n#define DMA_INTEN_CH2_TC_INTEN_BITS_DISABLE    (DMA_INTEN_CH2_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH2_TC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH2_TC_INTEN_VALUE_ENABLE    1U\r\n#define DMA_INTEN_CH2_TC_INTEN_BITS_ENABLE     (DMA_INTEN_CH2_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH2_TC_INTEN_SHIFT)\r\n\r\n#define DMA_INTEN_CH3_TC_INTEN_SHIFT           3\r\n#define DMA_INTEN_CH3_TC_INTEN_WIDTH           1\r\n#define DMA_INTEN_CH3_TC_INTEN_MASK            (((1U << DMA_INTEN_CH3_TC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_TC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH3_TC_INTEN_VALUE_DISABLE   0U\r\n#define DMA_INTEN_CH3_TC_INTEN_BITS_DISABLE    (DMA_INTEN_CH3_TC_INTEN_VALUE_DISABLE << DMA_INTEN_CH3_TC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH3_TC_INTEN_VALUE_ENABLE    1U\r\n#define DMA_INTEN_CH3_TC_INTEN_BITS_ENABLE     (DMA_INTEN_CH3_TC_INTEN_VALUE_ENABLE << DMA_INTEN_CH3_TC_INTEN_SHIFT)\r\n\r\n#define DMA_INTEN_CH0_THC_INTEN_SHIFT          8\r\n#define DMA_INTEN_CH0_THC_INTEN_WIDTH          1\r\n#define DMA_INTEN_CH0_THC_INTEN_MASK           (((1U << DMA_INTEN_CH0_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH0_THC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH0_THC_INTEN_VALUE_DISABLE  0U\r\n#define DMA_INTEN_CH0_THC_INTEN_BITS_DISABLE   (DMA_INTEN_CH0_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH0_THC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH0_THC_INTEN_VALUE_ENABLE   1U\r\n#define DMA_INTEN_CH0_THC_INTEN_BITS_ENABLE    (DMA_INTEN_CH0_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH0_THC_INTEN_SHIFT)\r\n\r\n#define DMA_INTEN_CH1_THC_INTEN_SHIFT          9\r\n#define DMA_INTEN_CH1_THC_INTEN_WIDTH          1\r\n#define DMA_INTEN_CH1_THC_INTEN_MASK           (((1U << DMA_INTEN_CH1_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH1_THC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH1_THC_INTEN_VALUE_DISABLE  0U\r\n#define DMA_INTEN_CH1_THC_INTEN_BITS_DISABLE   (DMA_INTEN_CH1_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH1_THC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH1_THC_INTEN_VALUE_ENABLE   1U\r\n#define DMA_INTEN_CH1_THC_INTEN_BITS_ENABLE    (DMA_INTEN_CH1_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH1_THC_INTEN_SHIFT)\r\n\r\n#define DMA_INTEN_CH2_THC_INTEN_SHIFT          10\r\n#define DMA_INTEN_CH2_THC_INTEN_WIDTH          1\r\n#define DMA_INTEN_CH2_THC_INTEN_MASK           (((1U << DMA_INTEN_CH2_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH2_THC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH2_THC_INTEN_VALUE_DISABLE  0U\r\n#define DMA_INTEN_CH2_THC_INTEN_BITS_DISABLE   (DMA_INTEN_CH2_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH2_THC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH2_THC_INTEN_VALUE_ENABLE   1U\r\n#define DMA_INTEN_CH2_THC_INTEN_BITS_ENABLE    (DMA_INTEN_CH2_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH2_THC_INTEN_SHIFT)\r\n\r\n#define DMA_INTEN_CH3_THC_INTEN_SHIFT          11\r\n#define DMA_INTEN_CH3_THC_INTEN_WIDTH          1\r\n#define DMA_INTEN_CH3_THC_INTEN_MASK           (((1U << DMA_INTEN_CH3_THC_INTEN_WIDTH) - 1U) << DMA_INTEN_CH3_THC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH3_THC_INTEN_VALUE_DISABLE  0U\r\n#define DMA_INTEN_CH3_THC_INTEN_BITS_DISABLE   (DMA_INTEN_CH3_THC_INTEN_VALUE_DISABLE << DMA_INTEN_CH3_THC_INTEN_SHIFT)\r\n#define DMA_INTEN_CH3_THC_INTEN_VALUE_ENABLE   1U\r\n#define DMA_INTEN_CH3_THC_INTEN_BITS_ENABLE    (DMA_INTEN_CH3_THC_INTEN_VALUE_ENABLE << DMA_INTEN_CH3_THC_INTEN_SHIFT)\r\n\r\n#define DMA_INTST_ADDR                         (DMA_BASE_ADDR + 0x0008U)\r\n#define DMA_INTST                              (*(volatile uint32_t *)DMA_INTST_ADDR)\r\n#define DMA_INTST_CH0_TC_INTST_SHIFT           0\r\n#define DMA_INTST_CH0_TC_INTST_WIDTH           1\r\n#define DMA_INTST_CH0_TC_INTST_MASK            (((1U << DMA_INTST_CH0_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_TC_INTST_SHIFT)\r\n#define DMA_INTST_CH0_TC_INTST_VALUE_NOT_SET   0U\r\n#define DMA_INTST_CH0_TC_INTST_BITS_NOT_SET    (DMA_INTST_CH0_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH0_TC_INTST_SHIFT)\r\n#define DMA_INTST_CH0_TC_INTST_VALUE_SET       1U\r\n#define DMA_INTST_CH0_TC_INTST_BITS_SET        (DMA_INTST_CH0_TC_INTST_VALUE_SET << DMA_INTST_CH0_TC_INTST_SHIFT)\r\n\r\n#define DMA_INTST_CH1_TC_INTST_SHIFT           1\r\n#define DMA_INTST_CH1_TC_INTST_WIDTH           1\r\n#define DMA_INTST_CH1_TC_INTST_MASK            (((1U << DMA_INTST_CH1_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_TC_INTST_SHIFT)\r\n#define DMA_INTST_CH1_TC_INTST_VALUE_NOT_SET   0U\r\n#define DMA_INTST_CH1_TC_INTST_BITS_NOT_SET    (DMA_INTST_CH1_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH1_TC_INTST_SHIFT)\r\n#define DMA_INTST_CH1_TC_INTST_VALUE_SET       1U\r\n#define DMA_INTST_CH1_TC_INTST_BITS_SET        (DMA_INTST_CH1_TC_INTST_VALUE_SET << DMA_INTST_CH1_TC_INTST_SHIFT)\r\n\r\n#define DMA_INTST_CH2_TC_INTST_SHIFT           2\r\n#define DMA_INTST_CH2_TC_INTST_WIDTH           1\r\n#define DMA_INTST_CH2_TC_INTST_MASK            (((1U << DMA_INTST_CH2_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_TC_INTST_SHIFT)\r\n#define DMA_INTST_CH2_TC_INTST_VALUE_NOT_SET   0U\r\n#define DMA_INTST_CH2_TC_INTST_BITS_NOT_SET    (DMA_INTST_CH2_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH2_TC_INTST_SHIFT)\r\n#define DMA_INTST_CH2_TC_INTST_VALUE_SET       1U\r\n#define DMA_INTST_CH2_TC_INTST_BITS_SET        (DMA_INTST_CH2_TC_INTST_VALUE_SET << DMA_INTST_CH2_TC_INTST_SHIFT)\r\n\r\n#define DMA_INTST_CH3_TC_INTST_SHIFT           3\r\n#define DMA_INTST_CH3_TC_INTST_WIDTH           1\r\n#define DMA_INTST_CH3_TC_INTST_MASK            (((1U << DMA_INTST_CH3_TC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_TC_INTST_SHIFT)\r\n#define DMA_INTST_CH3_TC_INTST_VALUE_NOT_SET   0U\r\n#define DMA_INTST_CH3_TC_INTST_BITS_NOT_SET    (DMA_INTST_CH3_TC_INTST_VALUE_NOT_SET << DMA_INTST_CH3_TC_INTST_SHIFT)\r\n#define DMA_INTST_CH3_TC_INTST_VALUE_SET       1U\r\n#define DMA_INTST_CH3_TC_INTST_BITS_SET        (DMA_INTST_CH3_TC_INTST_VALUE_SET << DMA_INTST_CH3_TC_INTST_SHIFT)\r\n\r\n#define DMA_INTST_CH0_THC_INTST_SHIFT          8\r\n#define DMA_INTST_CH0_THC_INTST_WIDTH          1\r\n#define DMA_INTST_CH0_THC_INTST_MASK           (((1U << DMA_INTST_CH0_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH0_THC_INTST_SHIFT)\r\n#define DMA_INTST_CH0_THC_INTST_VALUE_NOT_SET  0U\r\n#define DMA_INTST_CH0_THC_INTST_BITS_NOT_SET   (DMA_INTST_CH0_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH0_THC_INTST_SHIFT)\r\n#define DMA_INTST_CH0_THC_INTST_VALUE_SET      1U\r\n#define DMA_INTST_CH0_THC_INTST_BITS_SET       (DMA_INTST_CH0_THC_INTST_VALUE_SET << DMA_INTST_CH0_THC_INTST_SHIFT)\r\n\r\n#define DMA_INTST_CH1_THC_INTST_SHIFT          9\r\n#define DMA_INTST_CH1_THC_INTST_WIDTH          1\r\n#define DMA_INTST_CH1_THC_INTST_MASK           (((1U << DMA_INTST_CH1_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH1_THC_INTST_SHIFT)\r\n#define DMA_INTST_CH1_THC_INTST_VALUE_NOT_SET  0U\r\n#define DMA_INTST_CH1_THC_INTST_BITS_NOT_SET   (DMA_INTST_CH1_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH1_THC_INTST_SHIFT)\r\n#define DMA_INTST_CH1_THC_INTST_VALUE_SET      1U\r\n#define DMA_INTST_CH1_THC_INTST_BITS_SET       (DMA_INTST_CH1_THC_INTST_VALUE_SET << DMA_INTST_CH1_THC_INTST_SHIFT)\r\n\r\n#define DMA_INTST_CH2_THC_INTST_SHIFT          10\r\n#define DMA_INTST_CH2_THC_INTST_WIDTH          1\r\n#define DMA_INTST_CH2_THC_INTST_MASK           (((1U << DMA_INTST_CH2_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH2_THC_INTST_SHIFT)\r\n#define DMA_INTST_CH2_THC_INTST_VALUE_NOT_SET  0U\r\n#define DMA_INTST_CH2_THC_INTST_BITS_NOT_SET   (DMA_INTST_CH2_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH2_THC_INTST_SHIFT)\r\n#define DMA_INTST_CH2_THC_INTST_VALUE_SET      1U\r\n#define DMA_INTST_CH2_THC_INTST_BITS_SET       (DMA_INTST_CH2_THC_INTST_VALUE_SET << DMA_INTST_CH2_THC_INTST_SHIFT)\r\n\r\n#define DMA_INTST_CH3_THC_INTST_SHIFT          11\r\n#define DMA_INTST_CH3_THC_INTST_WIDTH          1\r\n#define DMA_INTST_CH3_THC_INTST_MASK           (((1U << DMA_INTST_CH3_THC_INTST_WIDTH) - 1U) << DMA_INTST_CH3_THC_INTST_SHIFT)\r\n#define DMA_INTST_CH3_THC_INTST_VALUE_NOT_SET  0U\r\n#define DMA_INTST_CH3_THC_INTST_BITS_NOT_SET   (DMA_INTST_CH3_THC_INTST_VALUE_NOT_SET << DMA_INTST_CH3_THC_INTST_SHIFT)\r\n#define DMA_INTST_CH3_THC_INTST_VALUE_SET      1U\r\n#define DMA_INTST_CH3_THC_INTST_BITS_SET       (DMA_INTST_CH3_THC_INTST_VALUE_SET << DMA_INTST_CH3_THC_INTST_SHIFT)\r\n\r\n/* -------- DMA_CH0 -------- */\r\n#define DMA_CH0_BASE_ADDR                      0x40001100U\r\n#define DMA_CH0_BASE_SIZE                      0x00000020U\r\n#define DMA_CH0                                ((volatile DMA_Channel_t *)DMA_CH0_BASE_ADDR)\r\n\r\n/* -------- DMA_CH1 -------- */\r\n#define DMA_CH1_BASE_ADDR                      0x40001120U\r\n#define DMA_CH1_BASE_SIZE                      0x00000020U\r\n#define DMA_CH1                                ((volatile DMA_Channel_t *)DMA_CH1_BASE_ADDR)\r\n\r\n/* -------- DMA_CH2 -------- */\r\n#define DMA_CH2_BASE_ADDR                      0x40001140U\r\n#define DMA_CH2_BASE_SIZE                      0x00000020U\r\n#define DMA_CH2                                ((volatile DMA_Channel_t *)DMA_CH2_BASE_ADDR)\r\n\r\n/* -------- DMA_CH3 -------- */\r\n#define DMA_CH3_BASE_ADDR                      0x40001160U\r\n#define DMA_CH3_BASE_SIZE                      0x00000020U\r\n#define DMA_CH3                                ((volatile DMA_Channel_t *)DMA_CH3_BASE_ADDR)\r\n\r\n/* -------- DMA_CH -------- */\r\n\r\ntypedef struct {\r\n\tuint32_t CTR;\r\n\tuint32_t MOD;\r\n\tuint32_t MSADDR;\r\n\tuint32_t MDADDR;\r\n\tuint32_t ST;\r\n} DMA_Channel_t;\r\n\r\n#define DMA_CH_CTR_CH_EN_SHIFT                 0\r\n#define DMA_CH_CTR_CH_EN_WIDTH                 1\r\n#define DMA_CH_CTR_CH_EN_MASK                  (((1U << DMA_CH_CTR_CH_EN_WIDTH) - 1U) << DMA_CH_CTR_CH_EN_SHIFT)\r\n#define DMA_CH_CTR_CH_EN_VALUE_DISABLE         0U\r\n#define DMA_CH_CTR_CH_EN_BITS_DISABLE          (DMA_CH_CTR_CH_EN_VALUE_DISABLE << DMA_CH_CTR_CH_EN_SHIFT)\r\n#define DMA_CH_CTR_CH_EN_VALUE_ENABLE          1U\r\n#define DMA_CH_CTR_CH_EN_BITS_ENABLE           (DMA_CH_CTR_CH_EN_VALUE_ENABLE << DMA_CH_CTR_CH_EN_SHIFT)\r\n\r\n#define DMA_CH_CTR_LENGTH_SHIFT                1\r\n#define DMA_CH_CTR_LENGTH_WIDTH                12\r\n#define DMA_CH_CTR_LENGTH_MASK                 (((1U << DMA_CH_CTR_LENGTH_WIDTH) - 1U) << DMA_CH_CTR_LENGTH_SHIFT)\r\n#define DMA_CH_CTR_LOOP_SHIFT                  13\r\n#define DMA_CH_CTR_LOOP_WIDTH                  1\r\n#define DMA_CH_CTR_LOOP_MASK                   (((1U << DMA_CH_CTR_LOOP_WIDTH) - 1U) << DMA_CH_CTR_LOOP_SHIFT)\r\n#define DMA_CH_CTR_LOOP_VALUE_DISABLE          0U\r\n#define DMA_CH_CTR_LOOP_BITS_DISABLE           (DMA_CH_CTR_LOOP_VALUE_DISABLE << DMA_CH_CTR_LOOP_SHIFT)\r\n#define DMA_CH_CTR_LOOP_VALUE_ENABLE           1U\r\n#define DMA_CH_CTR_LOOP_BITS_ENABLE            (DMA_CH_CTR_LOOP_VALUE_ENABLE << DMA_CH_CTR_LOOP_SHIFT)\r\n\r\n#define DMA_CH_CTR_PRI_SHIFT                   14\r\n#define DMA_CH_CTR_PRI_WIDTH                   2\r\n#define DMA_CH_CTR_PRI_MASK                    (((1U << DMA_CH_CTR_PRI_WIDTH) - 1U) << DMA_CH_CTR_PRI_SHIFT)\r\n#define DMA_CH_CTR_PRI_VALUE_LOW               0U\r\n#define DMA_CH_CTR_PRI_BITS_LOW                (DMA_CH_CTR_PRI_VALUE_LOW << DMA_CH_CTR_PRI_SHIFT)\r\n#define DMA_CH_CTR_PRI_VALUE_MEDIUM            1U\r\n#define DMA_CH_CTR_PRI_BITS_MEDIUM             (DMA_CH_CTR_PRI_VALUE_MEDIUM << DMA_CH_CTR_PRI_SHIFT)\r\n#define DMA_CH_CTR_PRI_VALUE_HIGH              2U\r\n#define DMA_CH_CTR_PRI_BITS_HIGH               (DMA_CH_CTR_PRI_VALUE_HIGH << DMA_CH_CTR_PRI_SHIFT)\r\n#define DMA_CH_CTR_PRI_VALUE_HIGHEST           3U\r\n#define DMA_CH_CTR_PRI_BITS_HIGHEST            (DMA_CH_CTR_PRI_VALUE_HIGHEST << DMA_CH_CTR_PRI_SHIFT)\r\n\r\n#define DMA_CH_CTR_SWREQ_SHIFT                 16\r\n#define DMA_CH_CTR_SWREQ_WIDTH                 1\r\n#define DMA_CH_CTR_SWREQ_MASK                  (((1U << DMA_CH_CTR_SWREQ_WIDTH) - 1U) << DMA_CH_CTR_SWREQ_SHIFT)\r\n#define DMA_CH_CTR_SWREQ_VALUE_SET             1U\r\n#define DMA_CH_CTR_SWREQ_BITS_SET              (DMA_CH_CTR_SWREQ_VALUE_SET << DMA_CH_CTR_SWREQ_SHIFT)\r\n\r\n#define DMA_CH_MOD_MS_ADDMOD_SHIFT             0\r\n#define DMA_CH_MOD_MS_ADDMOD_WIDTH             1\r\n#define DMA_CH_MOD_MS_ADDMOD_MASK              (((1U << DMA_CH_MOD_MS_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MS_ADDMOD_SHIFT)\r\n#define DMA_CH_MOD_MS_ADDMOD_VALUE_NONE        0U\r\n#define DMA_CH_MOD_MS_ADDMOD_BITS_NONE         (DMA_CH_MOD_MS_ADDMOD_VALUE_NONE << DMA_CH_MOD_MS_ADDMOD_SHIFT)\r\n#define DMA_CH_MOD_MS_ADDMOD_VALUE_INCREMENT   1U\r\n#define DMA_CH_MOD_MS_ADDMOD_BITS_INCREMENT    (DMA_CH_MOD_MS_ADDMOD_VALUE_INCREMENT << DMA_CH_MOD_MS_ADDMOD_SHIFT)\r\n\r\n#define DMA_CH_MOD_MS_SIZE_SHIFT               1\r\n#define DMA_CH_MOD_MS_SIZE_WIDTH               2\r\n#define DMA_CH_MOD_MS_SIZE_MASK                (((1U << DMA_CH_MOD_MS_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MS_SIZE_SHIFT)\r\n#define DMA_CH_MOD_MS_SIZE_VALUE_8BIT          0U\r\n#define DMA_CH_MOD_MS_SIZE_BITS_8BIT           (DMA_CH_MOD_MS_SIZE_VALUE_8BIT << DMA_CH_MOD_MS_SIZE_SHIFT)\r\n#define DMA_CH_MOD_MS_SIZE_VALUE_16BIT         1U\r\n#define DMA_CH_MOD_MS_SIZE_BITS_16BIT          (DMA_CH_MOD_MS_SIZE_VALUE_16BIT << DMA_CH_MOD_MS_SIZE_SHIFT)\r\n#define DMA_CH_MOD_MS_SIZE_VALUE_32BIT         2U\r\n#define DMA_CH_MOD_MS_SIZE_BITS_32BIT          (DMA_CH_MOD_MS_SIZE_VALUE_32BIT << DMA_CH_MOD_MS_SIZE_SHIFT)\r\n#define DMA_CH_MOD_MS_SIZE_VALUE_KEEP          3U\r\n#define DMA_CH_MOD_MS_SIZE_BITS_KEEP           (DMA_CH_MOD_MS_SIZE_VALUE_KEEP << DMA_CH_MOD_MS_SIZE_SHIFT)\r\n\r\n#define DMA_CH_MOD_MS_SEL_SHIFT                3\r\n#define DMA_CH_MOD_MS_SEL_WIDTH                3\r\n#define DMA_CH_MOD_MS_SEL_MASK                 (((1U << DMA_CH_MOD_MS_SEL_WIDTH) - 1U) << DMA_CH_MOD_MS_SEL_SHIFT)\r\n#define DMA_CH_MOD_MS_SEL_VALUE_SRAM           0U\r\n#define DMA_CH_MOD_MS_SEL_BITS_SRAM            (DMA_CH_MOD_MS_SEL_VALUE_SRAM << DMA_CH_MOD_MS_SEL_SHIFT)\r\n#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS0      1U\r\n#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS0       (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS0 << DMA_CH_MOD_MS_SEL_SHIFT)\r\n#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS1      2U\r\n#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1       (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS1 << DMA_CH_MOD_MS_SEL_SHIFT)\r\n#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS2      3U\r\n#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS2       (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS2 << DMA_CH_MOD_MS_SEL_SHIFT)\r\n#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS3      4U\r\n#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS3       (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS3 << DMA_CH_MOD_MS_SEL_SHIFT)\r\n#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS4      5U\r\n#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS4       (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS4 << DMA_CH_MOD_MS_SEL_SHIFT)\r\n#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS5      6U\r\n#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS5       (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS5 << DMA_CH_MOD_MS_SEL_SHIFT)\r\n#define DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS6      7U\r\n#define DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS6       (DMA_CH_MOD_MS_SEL_VALUE_HSREQ_MS6 << DMA_CH_MOD_MS_SEL_SHIFT)\r\n\r\n#define DMA_CH_MOD_MD_ADDMOD_SHIFT             8\r\n#define DMA_CH_MOD_MD_ADDMOD_WIDTH             1\r\n#define DMA_CH_MOD_MD_ADDMOD_MASK              (((1U << DMA_CH_MOD_MD_ADDMOD_WIDTH) - 1U) << DMA_CH_MOD_MD_ADDMOD_SHIFT)\r\n#define DMA_CH_MOD_MD_ADDMOD_VALUE_NONE        0U\r\n#define DMA_CH_MOD_MD_ADDMOD_BITS_NONE         (DMA_CH_MOD_MD_ADDMOD_VALUE_NONE << DMA_CH_MOD_MD_ADDMOD_SHIFT)\r\n#define DMA_CH_MOD_MD_ADDMOD_VALUE_INCREMENT   1U\r\n#define DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT    (DMA_CH_MOD_MD_ADDMOD_VALUE_INCREMENT << DMA_CH_MOD_MD_ADDMOD_SHIFT)\r\n\r\n#define DMA_CH_MOD_MD_SIZE_SHIFT               9\r\n#define DMA_CH_MOD_MD_SIZE_WIDTH               2\r\n#define DMA_CH_MOD_MD_SIZE_MASK                (((1U << DMA_CH_MOD_MD_SIZE_WIDTH) - 1U) << DMA_CH_MOD_MD_SIZE_SHIFT)\r\n#define DMA_CH_MOD_MD_SIZE_VALUE_8BIT          0U\r\n#define DMA_CH_MOD_MD_SIZE_BITS_8BIT           (DMA_CH_MOD_MD_SIZE_VALUE_8BIT << DMA_CH_MOD_MD_SIZE_SHIFT)\r\n#define DMA_CH_MOD_MD_SIZE_VALUE_16BIT         1U\r\n#define DMA_CH_MOD_MD_SIZE_BITS_16BIT          (DMA_CH_MOD_MD_SIZE_VALUE_16BIT << DMA_CH_MOD_MD_SIZE_SHIFT)\r\n#define DMA_CH_MOD_MD_SIZE_VALUE_32BIT         2U\r\n#define DMA_CH_MOD_MD_SIZE_BITS_32BIT          (DMA_CH_MOD_MD_SIZE_VALUE_32BIT << DMA_CH_MOD_MD_SIZE_SHIFT)\r\n#define DMA_CH_MOD_MD_SIZE_VALUE_KEEP          3U\r\n#define DMA_CH_MOD_MD_SIZE_BITS_KEEP           (DMA_CH_MOD_MD_SIZE_VALUE_KEEP << DMA_CH_MOD_MD_SIZE_SHIFT)\r\n\r\n#define DMA_CH_MOD_MD_SEL_SHIFT                11\r\n#define DMA_CH_MOD_MD_SEL_WIDTH                3\r\n#define DMA_CH_MOD_MD_SEL_MASK                 (((1U << DMA_CH_MOD_MD_SEL_WIDTH) - 1U) << DMA_CH_MOD_MD_SEL_SHIFT)\r\n#define DMA_CH_MOD_MD_SEL_VALUE_SRAM           0U\r\n#define DMA_CH_MOD_MD_SEL_BITS_SRAM            (DMA_CH_MOD_MD_SEL_VALUE_SRAM << DMA_CH_MOD_MD_SEL_SHIFT)\r\n#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS0      1U\r\n#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS0       (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS0 << DMA_CH_MOD_MD_SEL_SHIFT)\r\n#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS1      2U\r\n#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS1       (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS1 << DMA_CH_MOD_MD_SEL_SHIFT)\r\n#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS2      3U\r\n#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS2       (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS2 << DMA_CH_MOD_MD_SEL_SHIFT)\r\n#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS3      4U\r\n#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS3       (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS3 << DMA_CH_MOD_MD_SEL_SHIFT)\r\n#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS4      5U\r\n#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS4       (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS4 << DMA_CH_MOD_MD_SEL_SHIFT)\r\n#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS5      6U\r\n#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS5       (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS5 << DMA_CH_MOD_MD_SEL_SHIFT)\r\n#define DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS6      7U\r\n#define DMA_CH_MOD_MD_SEL_BITS_HSREQ_MS6       (DMA_CH_MOD_MD_SEL_VALUE_HSREQ_MS6 << DMA_CH_MOD_MD_SEL_SHIFT)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/flash.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_FLASH_H\r\n#define HARDWARE_DP32G030_FLASH_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- FLASH -------- */\r\n#define FLASH_BASE_ADDR                          0x4006F000U\r\n#define FLASH_BASE_SIZE                          0x00000800U\r\n\r\n#define FLASH_CFG_ADDR                           (FLASH_BASE_ADDR + 0x0000U)\r\n#define FLASH_CFG                                (*(volatile uint32_t *)FLASH_CFG_ADDR)\r\n#define FLASH_CFG_READ_MD_SHIFT                  0\r\n#define FLASH_CFG_READ_MD_WIDTH                  1\r\n#define FLASH_CFG_READ_MD_MASK                   (((1U << FLASH_CFG_READ_MD_WIDTH) - 1U) << FLASH_CFG_READ_MD_SHIFT)\r\n#define FLASH_CFG_READ_MD_VALUE_1_CYCLE          0U\r\n#define FLASH_CFG_READ_MD_BITS_1_CYCLE           (FLASH_CFG_READ_MD_VALUE_1_CYCLE << FLASH_CFG_READ_MD_SHIFT)\r\n#define FLASH_CFG_READ_MD_VALUE_2_CYCLE          1U\r\n#define FLASH_CFG_READ_MD_BITS_2_CYCLE           (FLASH_CFG_READ_MD_VALUE_2_CYCLE << FLASH_CFG_READ_MD_SHIFT)\r\n\r\n#define FLASH_CFG_NVR_SEL_SHIFT                  1\r\n#define FLASH_CFG_NVR_SEL_WIDTH                  1\r\n#define FLASH_CFG_NVR_SEL_MASK                   (((1U << FLASH_CFG_NVR_SEL_WIDTH) - 1U) << FLASH_CFG_NVR_SEL_SHIFT)\r\n#define FLASH_CFG_NVR_SEL_VALUE_MAIN             0U\r\n#define FLASH_CFG_NVR_SEL_BITS_MAIN              (FLASH_CFG_NVR_SEL_VALUE_MAIN << FLASH_CFG_NVR_SEL_SHIFT)\r\n#define FLASH_CFG_NVR_SEL_VALUE_NVR              1U\r\n#define FLASH_CFG_NVR_SEL_BITS_NVR               (FLASH_CFG_NVR_SEL_VALUE_NVR << FLASH_CFG_NVR_SEL_SHIFT)\r\n\r\n#define FLASH_CFG_MODE_SHIFT                     2\r\n#define FLASH_CFG_MODE_WIDTH                     3\r\n#define FLASH_CFG_MODE_MASK                      (((1U << FLASH_CFG_MODE_WIDTH) - 1U) << FLASH_CFG_MODE_SHIFT)\r\n#define FLASH_CFG_MODE_VALUE_READ_AHB            0U\r\n#define FLASH_CFG_MODE_BITS_READ_AHB             (FLASH_CFG_MODE_VALUE_READ_AHB << FLASH_CFG_MODE_SHIFT)\r\n#define FLASH_CFG_MODE_VALUE_PROGRAM             1U\r\n#define FLASH_CFG_MODE_BITS_PROGRAM              (FLASH_CFG_MODE_VALUE_PROGRAM << FLASH_CFG_MODE_SHIFT)\r\n#define FLASH_CFG_MODE_VALUE_ERASE               2U\r\n#define FLASH_CFG_MODE_BITS_ERASE                (FLASH_CFG_MODE_VALUE_ERASE << FLASH_CFG_MODE_SHIFT)\r\n#define FLASH_CFG_MODE_VALUE_READ_APB            5U\r\n#define FLASH_CFG_MODE_BITS_READ_APB             (FLASH_CFG_MODE_VALUE_READ_APB << FLASH_CFG_MODE_SHIFT)\r\n\r\n#define FLASH_CFG_DEEP_PD_SHIFT                  31\r\n#define FLASH_CFG_DEEP_PD_WIDTH                  1\r\n#define FLASH_CFG_DEEP_PD_MASK                   (((1U << FLASH_CFG_DEEP_PD_WIDTH) - 1U) << FLASH_CFG_DEEP_PD_SHIFT)\r\n#define FLASH_CFG_DEEP_PD_VALUE_NORMAL           0U\r\n#define FLASH_CFG_DEEP_PD_BITS_NORMAL            (FLASH_CFG_DEEP_PD_VALUE_NORMAL << FLASH_CFG_DEEP_PD_SHIFT)\r\n#define FLASH_CFG_DEEP_PD_VALUE_LOW_POWER        1U\r\n#define FLASH_CFG_DEEP_PD_BITS_LOW_POWER         (FLASH_CFG_DEEP_PD_VALUE_LOW_POWER << FLASH_CFG_DEEP_PD_SHIFT)\r\n\r\n#define FLASH_ADDR_ADDR                          (FLASH_BASE_ADDR + 0x0004U)\r\n#define FLASH_ADDR                               (*(volatile uint32_t *)FLASH_ADDR_ADDR)\r\n#define FLASH_WDATA_ADDR                         (FLASH_BASE_ADDR + 0x0008U)\r\n#define FLASH_WDATA                              (*(volatile uint32_t *)FLASH_WDATA_ADDR)\r\n#define FLASH_RDATA_ADDR                         (FLASH_BASE_ADDR + 0x000CU)\r\n#define FLASH_RDATA                              (*(volatile uint32_t *)FLASH_RDATA_ADDR)\r\n\r\n#define FLASH_START_ADDR                         (FLASH_BASE_ADDR + 0x0010U)\r\n#define FLASH_START                              (*(volatile uint32_t *)FLASH_START_ADDR)\r\n#define FLASH_START_START_SHIFT                  0\r\n#define FLASH_START_START_WIDTH                  1\r\n#define FLASH_START_START_MASK                   (((1U << FLASH_START_START_WIDTH) - 1U) << FLASH_START_START_SHIFT)\r\n#define FLASH_START_START_VALUE_START            1U\r\n#define FLASH_START_START_BITS_START             (FLASH_START_START_VALUE_START << FLASH_START_START_SHIFT)\r\n\r\n#define FLASH_ST_ADDR                            (FLASH_BASE_ADDR + 0x0014U)\r\n#define FLASH_ST                                 (*(volatile uint32_t *)FLASH_ST_ADDR)\r\n#define FLASH_ST_INIT_BUSY_SHIFT                 0\r\n#define FLASH_ST_INIT_BUSY_WIDTH                 1\r\n#define FLASH_ST_INIT_BUSY_MASK                  (((1U << FLASH_ST_INIT_BUSY_WIDTH) - 1U) << FLASH_ST_INIT_BUSY_SHIFT)\r\n#define FLASH_ST_INIT_BUSY_VALUE_COMPLETE        0U\r\n#define FLASH_ST_INIT_BUSY_BITS_COMPLETE         (FLASH_ST_INIT_BUSY_VALUE_COMPLETE << FLASH_ST_INIT_BUSY_SHIFT)\r\n#define FLASH_ST_INIT_BUSY_VALUE_BUSY            1U\r\n#define FLASH_ST_INIT_BUSY_BITS_BUSY             (FLASH_ST_INIT_BUSY_VALUE_BUSY << FLASH_ST_INIT_BUSY_SHIFT)\r\n\r\n#define FLASH_ST_BUSY_SHIFT                      1\r\n#define FLASH_ST_BUSY_WIDTH                      1\r\n#define FLASH_ST_BUSY_MASK                       (((1U << FLASH_ST_BUSY_WIDTH) - 1U) << FLASH_ST_BUSY_SHIFT)\r\n#define FLASH_ST_BUSY_VALUE_READY                0U\r\n#define FLASH_ST_BUSY_BITS_READY                 (FLASH_ST_BUSY_VALUE_READY << FLASH_ST_BUSY_SHIFT)\r\n#define FLASH_ST_BUSY_VALUE_BUSY                 1U\r\n#define FLASH_ST_BUSY_BITS_BUSY                  (FLASH_ST_BUSY_VALUE_BUSY << FLASH_ST_BUSY_SHIFT)\r\n\r\n#define FLASH_ST_PROG_BUF_EMPTY_SHIFT            2\r\n#define FLASH_ST_PROG_BUF_EMPTY_WIDTH            1\r\n#define FLASH_ST_PROG_BUF_EMPTY_MASK             (((1U << FLASH_ST_PROG_BUF_EMPTY_WIDTH) - 1U) << FLASH_ST_PROG_BUF_EMPTY_SHIFT)\r\n#define FLASH_ST_PROG_BUF_EMPTY_VALUE_NOT_EMPTY  0U\r\n#define FLASH_ST_PROG_BUF_EMPTY_BITS_NOT_EMPTY   (FLASH_ST_PROG_BUF_EMPTY_VALUE_NOT_EMPTY << FLASH_ST_PROG_BUF_EMPTY_SHIFT)\r\n#define FLASH_ST_PROG_BUF_EMPTY_VALUE_EMPTY      1U\r\n#define FLASH_ST_PROG_BUF_EMPTY_BITS_EMPTY       (FLASH_ST_PROG_BUF_EMPTY_VALUE_EMPTY << FLASH_ST_PROG_BUF_EMPTY_SHIFT)\r\n\r\n#define FLASH_LOCK_ADDR                          (FLASH_BASE_ADDR + 0x0018U)\r\n#define FLASH_LOCK                               (*(volatile uint32_t *)FLASH_LOCK_ADDR)\r\n#define FLASH_LOCK_LOCK_SHIFT                    0\r\n#define FLASH_LOCK_LOCK_WIDTH                    8\r\n#define FLASH_LOCK_LOCK_MASK                     (((1U << FLASH_LOCK_LOCK_WIDTH) - 1U) << FLASH_LOCK_LOCK_SHIFT)\r\n#define FLASH_LOCK_LOCK_VALUE_LOCK               85U\r\n#define FLASH_LOCK_LOCK_BITS_LOCK                (FLASH_LOCK_LOCK_VALUE_LOCK << FLASH_LOCK_LOCK_SHIFT)\r\n\r\n#define FLASH_UNLOCK_ADDR                        (FLASH_BASE_ADDR + 0x001CU)\r\n#define FLASH_UNLOCK                             (*(volatile uint32_t *)FLASH_UNLOCK_ADDR)\r\n#define FLASH_UNLOCK_UNLOCK_SHIFT                0\r\n#define FLASH_UNLOCK_UNLOCK_WIDTH                8\r\n#define FLASH_UNLOCK_UNLOCK_MASK                 (((1U << FLASH_UNLOCK_UNLOCK_WIDTH) - 1U) << FLASH_UNLOCK_UNLOCK_SHIFT)\r\n#define FLASH_UNLOCK_UNLOCK_VALUE_UNLOCK         170U\r\n#define FLASH_UNLOCK_UNLOCK_BITS_UNLOCK          (FLASH_UNLOCK_UNLOCK_VALUE_UNLOCK << FLASH_UNLOCK_UNLOCK_SHIFT)\r\n\r\n#define FLASH_MASK_ADDR                          (FLASH_BASE_ADDR + 0x0020U)\r\n#define FLASH_MASK                               (*(volatile uint32_t *)FLASH_MASK_ADDR)\r\n#define FLASH_MASK_SEL_SHIFT                     0\r\n#define FLASH_MASK_SEL_WIDTH                     2\r\n#define FLASH_MASK_SEL_MASK                      (((1U << FLASH_MASK_SEL_WIDTH) - 1U) << FLASH_MASK_SEL_SHIFT)\r\n#define FLASH_MASK_SEL_VALUE_NONE                0U\r\n#define FLASH_MASK_SEL_BITS_NONE                 (FLASH_MASK_SEL_VALUE_NONE << FLASH_MASK_SEL_SHIFT)\r\n#define FLASH_MASK_SEL_VALUE_2KB                 1U\r\n#define FLASH_MASK_SEL_BITS_2KB                  (FLASH_MASK_SEL_VALUE_2KB << FLASH_MASK_SEL_SHIFT)\r\n#define FLASH_MASK_SEL_VALUE_4KB                 2U\r\n#define FLASH_MASK_SEL_BITS_4KB                  (FLASH_MASK_SEL_VALUE_4KB << FLASH_MASK_SEL_SHIFT)\r\n#define FLASH_MASK_SEL_VALUE_8KB                 3U\r\n#define FLASH_MASK_SEL_BITS_8KB                  (FLASH_MASK_SEL_VALUE_8KB << FLASH_MASK_SEL_SHIFT)\r\n\r\n#define FLASH_MASK_LOCK_SHIFT                    2\r\n#define FLASH_MASK_LOCK_WIDTH                    1\r\n#define FLASH_MASK_LOCK_MASK                     (((1U << FLASH_MASK_LOCK_WIDTH) - 1U) << FLASH_MASK_LOCK_SHIFT)\r\n#define FLASH_MASK_LOCK_VALUE_NOT_SET            0U\r\n#define FLASH_MASK_LOCK_BITS_NOT_SET             (FLASH_MASK_LOCK_VALUE_NOT_SET << FLASH_MASK_LOCK_SHIFT)\r\n#define FLASH_MASK_LOCK_VALUE_SET                1U\r\n#define FLASH_MASK_LOCK_BITS_SET                 (FLASH_MASK_LOCK_VALUE_SET << FLASH_MASK_LOCK_SHIFT)\r\n\r\n#define FLASH_ERASETIME_ADDR                     (FLASH_BASE_ADDR + 0x0024U)\r\n#define FLASH_ERASETIME                          (*(volatile uint32_t *)FLASH_ERASETIME_ADDR)\r\n#define FLASH_ERASETIME_TERASE_SHIFT             0\r\n#define FLASH_ERASETIME_TERASE_WIDTH             19\r\n#define FLASH_ERASETIME_TERASE_MASK              (((1U << FLASH_ERASETIME_TERASE_WIDTH) - 1U) << FLASH_ERASETIME_TERASE_SHIFT)\r\n#define FLASH_ERASETIME_TRCV_SHIFT               19\r\n#define FLASH_ERASETIME_TRCV_WIDTH               12\r\n#define FLASH_ERASETIME_TRCV_MASK                (((1U << FLASH_ERASETIME_TRCV_WIDTH) - 1U) << FLASH_ERASETIME_TRCV_SHIFT)\r\n\r\n#define FLASH_PROGTIME_ADDR                      (FLASH_BASE_ADDR + 0x0028U)\r\n#define FLASH_PROGTIME                           (*(volatile uint32_t *)FLASH_PROGTIME_ADDR)\r\n#define FLASH_PROGTIME_TPROG_SHIFT               0\r\n#define FLASH_PROGTIME_TPROG_WIDTH               11\r\n#define FLASH_PROGTIME_TPROG_MASK                (((1U << FLASH_PROGTIME_TPROG_WIDTH) - 1U) << FLASH_PROGTIME_TPROG_SHIFT)\r\n#define FLASH_PROGTIME_TPGS_SHIFT                11\r\n#define FLASH_PROGTIME_TPGS_WIDTH                11\r\n#define FLASH_PROGTIME_TPGS_MASK                 (((1U << FLASH_PROGTIME_TPGS_WIDTH) - 1U) << FLASH_PROGTIME_TPGS_SHIFT)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/gpio.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_GPIO_H\r\n#define HARDWARE_DP32G030_GPIO_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- GPIOA -------- */\r\n#define GPIOA_BASE_ADDR           0x40060000U\r\n#define GPIOA_BASE_SIZE           0x00000800U\r\n#define GPIOA                     ((volatile GPIO_Bank_t *)GPIOA_BASE_ADDR)\r\n\r\n/* -------- GPIOB -------- */\r\n#define GPIOB_BASE_ADDR           0x40060800U\r\n#define GPIOB_BASE_SIZE           0x00000800U\r\n#define GPIOB                     ((volatile GPIO_Bank_t *)GPIOB_BASE_ADDR)\r\n\r\n/* -------- GPIOC -------- */\r\n#define GPIOC_BASE_ADDR           0x40061000U\r\n#define GPIOC_BASE_SIZE           0x00000800U\r\n#define GPIOC                     ((volatile GPIO_Bank_t *)GPIOC_BASE_ADDR)\r\n\r\n/* -------- GPIO -------- */\r\n\r\ntypedef struct {\r\n\tuint32_t DATA;\r\n\tuint32_t DIR;\r\n} GPIO_Bank_t;\r\n\r\n#define GPIO_DIR_0_SHIFT          0\r\n#define GPIO_DIR_0_WIDTH          1\r\n#define GPIO_DIR_0_MASK           (((1U << GPIO_DIR_0_WIDTH) - 1U) << GPIO_DIR_0_SHIFT)\r\n#define GPIO_DIR_0_VALUE_INPUT    0U\r\n#define GPIO_DIR_0_BITS_INPUT     (GPIO_DIR_0_VALUE_INPUT << GPIO_DIR_0_SHIFT)\r\n#define GPIO_DIR_0_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_0_BITS_OUTPUT    (GPIO_DIR_0_VALUE_OUTPUT << GPIO_DIR_0_SHIFT)\r\n\r\n#define GPIO_DIR_1_SHIFT          1\r\n#define GPIO_DIR_1_WIDTH          1\r\n#define GPIO_DIR_1_MASK           (((1U << GPIO_DIR_1_WIDTH) - 1U) << GPIO_DIR_1_SHIFT)\r\n#define GPIO_DIR_1_VALUE_INPUT    0U\r\n#define GPIO_DIR_1_BITS_INPUT     (GPIO_DIR_1_VALUE_INPUT << GPIO_DIR_1_SHIFT)\r\n#define GPIO_DIR_1_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_1_BITS_OUTPUT    (GPIO_DIR_1_VALUE_OUTPUT << GPIO_DIR_1_SHIFT)\r\n\r\n#define GPIO_DIR_2_SHIFT          2\r\n#define GPIO_DIR_2_WIDTH          1\r\n#define GPIO_DIR_2_MASK           (((1U << GPIO_DIR_2_WIDTH) - 1U) << GPIO_DIR_2_SHIFT)\r\n#define GPIO_DIR_2_VALUE_INPUT    0U\r\n#define GPIO_DIR_2_BITS_INPUT     (GPIO_DIR_2_VALUE_INPUT << GPIO_DIR_2_SHIFT)\r\n#define GPIO_DIR_2_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_2_BITS_OUTPUT    (GPIO_DIR_2_VALUE_OUTPUT << GPIO_DIR_2_SHIFT)\r\n\r\n#define GPIO_DIR_3_SHIFT          3\r\n#define GPIO_DIR_3_WIDTH          1\r\n#define GPIO_DIR_3_MASK           (((1U << GPIO_DIR_3_WIDTH) - 1U) << GPIO_DIR_3_SHIFT)\r\n#define GPIO_DIR_3_VALUE_INPUT    0U\r\n#define GPIO_DIR_3_BITS_INPUT     (GPIO_DIR_3_VALUE_INPUT << GPIO_DIR_3_SHIFT)\r\n#define GPIO_DIR_3_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_3_BITS_OUTPUT    (GPIO_DIR_3_VALUE_OUTPUT << GPIO_DIR_3_SHIFT)\r\n\r\n#define GPIO_DIR_4_SHIFT          4\r\n#define GPIO_DIR_4_WIDTH          1\r\n#define GPIO_DIR_4_MASK           (((1U << GPIO_DIR_4_WIDTH) - 1U) << GPIO_DIR_4_SHIFT)\r\n#define GPIO_DIR_4_VALUE_INPUT    0U\r\n#define GPIO_DIR_4_BITS_INPUT     (GPIO_DIR_4_VALUE_INPUT << GPIO_DIR_4_SHIFT)\r\n#define GPIO_DIR_4_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_4_BITS_OUTPUT    (GPIO_DIR_4_VALUE_OUTPUT << GPIO_DIR_4_SHIFT)\r\n\r\n#define GPIO_DIR_5_SHIFT          5\r\n#define GPIO_DIR_5_WIDTH          1\r\n#define GPIO_DIR_5_MASK           (((1U << GPIO_DIR_5_WIDTH) - 1U) << GPIO_DIR_5_SHIFT)\r\n#define GPIO_DIR_5_VALUE_INPUT    0U\r\n#define GPIO_DIR_5_BITS_INPUT     (GPIO_DIR_5_VALUE_INPUT << GPIO_DIR_5_SHIFT)\r\n#define GPIO_DIR_5_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_5_BITS_OUTPUT    (GPIO_DIR_5_VALUE_OUTPUT << GPIO_DIR_5_SHIFT)\r\n\r\n#define GPIO_DIR_6_SHIFT          6\r\n#define GPIO_DIR_6_WIDTH          1\r\n#define GPIO_DIR_6_MASK           (((1U << GPIO_DIR_6_WIDTH) - 1U) << GPIO_DIR_6_SHIFT)\r\n#define GPIO_DIR_6_VALUE_INPUT    0U\r\n#define GPIO_DIR_6_BITS_INPUT     (GPIO_DIR_6_VALUE_INPUT << GPIO_DIR_6_SHIFT)\r\n#define GPIO_DIR_6_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_6_BITS_OUTPUT    (GPIO_DIR_6_VALUE_OUTPUT << GPIO_DIR_6_SHIFT)\r\n\r\n#define GPIO_DIR_7_SHIFT          7\r\n#define GPIO_DIR_7_WIDTH          1\r\n#define GPIO_DIR_7_MASK           (((1U << GPIO_DIR_7_WIDTH) - 1U) << GPIO_DIR_7_SHIFT)\r\n#define GPIO_DIR_7_VALUE_INPUT    0U\r\n#define GPIO_DIR_7_BITS_INPUT     (GPIO_DIR_7_VALUE_INPUT << GPIO_DIR_7_SHIFT)\r\n#define GPIO_DIR_7_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_7_BITS_OUTPUT    (GPIO_DIR_7_VALUE_OUTPUT << GPIO_DIR_7_SHIFT)\r\n\r\n#define GPIO_DIR_8_SHIFT          8\r\n#define GPIO_DIR_8_WIDTH          1\r\n#define GPIO_DIR_8_MASK           (((1U << GPIO_DIR_8_WIDTH) - 1U) << GPIO_DIR_8_SHIFT)\r\n#define GPIO_DIR_8_VALUE_INPUT    0U\r\n#define GPIO_DIR_8_BITS_INPUT     (GPIO_DIR_8_VALUE_INPUT << GPIO_DIR_8_SHIFT)\r\n#define GPIO_DIR_8_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_8_BITS_OUTPUT    (GPIO_DIR_8_VALUE_OUTPUT << GPIO_DIR_8_SHIFT)\r\n\r\n#define GPIO_DIR_9_SHIFT          9\r\n#define GPIO_DIR_9_WIDTH          1\r\n#define GPIO_DIR_9_MASK           (((1U << GPIO_DIR_9_WIDTH) - 1U) << GPIO_DIR_9_SHIFT)\r\n#define GPIO_DIR_9_VALUE_INPUT    0U\r\n#define GPIO_DIR_9_BITS_INPUT     (GPIO_DIR_9_VALUE_INPUT << GPIO_DIR_9_SHIFT)\r\n#define GPIO_DIR_9_VALUE_OUTPUT   1U\r\n#define GPIO_DIR_9_BITS_OUTPUT    (GPIO_DIR_9_VALUE_OUTPUT << GPIO_DIR_9_SHIFT)\r\n\r\n#define GPIO_DIR_10_SHIFT         10\r\n#define GPIO_DIR_10_WIDTH         1\r\n#define GPIO_DIR_10_MASK          (((1U << GPIO_DIR_10_WIDTH) - 1U) << GPIO_DIR_10_SHIFT)\r\n#define GPIO_DIR_10_VALUE_INPUT   0U\r\n#define GPIO_DIR_10_BITS_INPUT    (GPIO_DIR_10_VALUE_INPUT << GPIO_DIR_10_SHIFT)\r\n#define GPIO_DIR_10_VALUE_OUTPUT  1U\r\n#define GPIO_DIR_10_BITS_OUTPUT   (GPIO_DIR_10_VALUE_OUTPUT << GPIO_DIR_10_SHIFT)\r\n\r\n#define GPIO_DIR_11_SHIFT         11\r\n#define GPIO_DIR_11_WIDTH         1\r\n#define GPIO_DIR_11_MASK          (((1U << GPIO_DIR_11_WIDTH) - 1U) << GPIO_DIR_11_SHIFT)\r\n#define GPIO_DIR_11_VALUE_INPUT   0U\r\n#define GPIO_DIR_11_BITS_INPUT    (GPIO_DIR_11_VALUE_INPUT << GPIO_DIR_11_SHIFT)\r\n#define GPIO_DIR_11_VALUE_OUTPUT  1U\r\n#define GPIO_DIR_11_BITS_OUTPUT   (GPIO_DIR_11_VALUE_OUTPUT << GPIO_DIR_11_SHIFT)\r\n\r\n#define GPIO_DIR_12_SHIFT         12\r\n#define GPIO_DIR_12_WIDTH         1\r\n#define GPIO_DIR_12_MASK          (((1U << GPIO_DIR_12_WIDTH) - 1U) << GPIO_DIR_12_SHIFT)\r\n#define GPIO_DIR_12_VALUE_INPUT   0U\r\n#define GPIO_DIR_12_BITS_INPUT    (GPIO_DIR_12_VALUE_INPUT << GPIO_DIR_12_SHIFT)\r\n#define GPIO_DIR_12_VALUE_OUTPUT  1U\r\n#define GPIO_DIR_12_BITS_OUTPUT   (GPIO_DIR_12_VALUE_OUTPUT << GPIO_DIR_12_SHIFT)\r\n\r\n#define GPIO_DIR_13_SHIFT         13\r\n#define GPIO_DIR_13_WIDTH         1\r\n#define GPIO_DIR_13_MASK          (((1U << GPIO_DIR_13_WIDTH) - 1U) << GPIO_DIR_13_SHIFT)\r\n#define GPIO_DIR_13_VALUE_INPUT   0U\r\n#define GPIO_DIR_13_BITS_INPUT    (GPIO_DIR_13_VALUE_INPUT << GPIO_DIR_13_SHIFT)\r\n#define GPIO_DIR_13_VALUE_OUTPUT  1U\r\n#define GPIO_DIR_13_BITS_OUTPUT   (GPIO_DIR_13_VALUE_OUTPUT << GPIO_DIR_13_SHIFT)\r\n\r\n#define GPIO_DIR_14_SHIFT         14\r\n#define GPIO_DIR_14_WIDTH         1\r\n#define GPIO_DIR_14_MASK          (((1U << GPIO_DIR_14_WIDTH) - 1U) << GPIO_DIR_14_SHIFT)\r\n#define GPIO_DIR_14_VALUE_INPUT   0U\r\n#define GPIO_DIR_14_BITS_INPUT    (GPIO_DIR_14_VALUE_INPUT << GPIO_DIR_14_SHIFT)\r\n#define GPIO_DIR_14_VALUE_OUTPUT  1U\r\n#define GPIO_DIR_14_BITS_OUTPUT   (GPIO_DIR_14_VALUE_OUTPUT << GPIO_DIR_14_SHIFT)\r\n\r\n#define GPIO_DIR_15_SHIFT         15\r\n#define GPIO_DIR_15_WIDTH         1\r\n#define GPIO_DIR_15_MASK          (((1U << GPIO_DIR_15_WIDTH) - 1U) << GPIO_DIR_15_SHIFT)\r\n#define GPIO_DIR_15_VALUE_INPUT   0U\r\n#define GPIO_DIR_15_BITS_INPUT    (GPIO_DIR_15_VALUE_INPUT << GPIO_DIR_15_SHIFT)\r\n#define GPIO_DIR_15_VALUE_OUTPUT  1U\r\n#define GPIO_DIR_15_BITS_OUTPUT   (GPIO_DIR_15_VALUE_OUTPUT << GPIO_DIR_15_SHIFT)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/irq.h",
    "content": "#ifndef DP32G030_IRQ_H\r\n#define DP32G030_IRQ_H\r\n\r\nenum {\r\n\tDP32_WWDT_IRQn = 0,\r\n\tDP32_IWDT_IRQn,\r\n\tDP32_RTC_IRQn,\r\n\tDP32_DMA_IRQn,\r\n\tDP32_SARADC_IRQn,\r\n\tDP32_TIMER_BASE0_IRQn,\r\n\tDP32_TIMER_BASE1_IRQn,\r\n\tDP32_TIMER_PLUS0_IRQn,\r\n\tDP32_TIMER_PLUS1_IRQn,\r\n\tDP32_PWM_BASE0_IRQn,\r\n\tDP32_PWM_BASE1_IRQn,\r\n\tDP32_PWM_PLUS0_IRQn,\r\n\tDP32_PWM_PLUS1_IRQn,\r\n\tDP32_UART0_IRQn,\r\n\tDP32_UART1_IRQn,\r\n\tDP32_UART2_IRQn,\r\n\tDP32_SPI0_IRQn,\r\n\tDP32_SPI1_IRQn,\r\n\tDP32_IIC0_IRQn,\r\n\tDP32_IIC1_IRQn,\r\n\tDP32_CMP_IRQn,\r\n\tDP32_TIMER_BASE2_IRQn,\r\n\tDP32_GPIOA5_IRQn,\r\n\tDP32_GPIOA6_IRQn,\r\n\tDP32_GPIOA7_IRQn,\r\n\tDP32_GPIOB0_IRQn,\r\n\tDP32_GPIOB1_IRQn,\r\n\tDP32_GPIOC0_IRQn,\r\n\tDP32_GPIOC1_IRQn,\r\n\tDP32_GPIOA_IRQn,\r\n\tDP32_GPIOB_IRQn,\r\n\tDP32_GPIOC_IRQn,\r\n};\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/pmu.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_PMU_H\r\n#define HARDWARE_DP32G030_PMU_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- PMU -------- */\r\n#define PMU_BASE_ADDR                      0x40000800U\r\n#define PMU_BASE_SIZE                      0x00000800U\r\n\r\n#define PMU_SRC_CFG_ADDR                   (PMU_BASE_ADDR + 0x0010U)\r\n#define PMU_SRC_CFG                        (*(volatile uint32_t *)PMU_SRC_CFG_ADDR)\r\n#define PMU_SRC_CFG_RCHF_EN_SHIFT          0\r\n#define PMU_SRC_CFG_RCHF_EN_WIDTH          1\r\n#define PMU_SRC_CFG_RCHF_EN_MASK           (((1U << PMU_SRC_CFG_RCHF_EN_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_EN_SHIFT)\r\n#define PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE  0U\r\n#define PMU_SRC_CFG_RCHF_EN_BITS_DISABLE   (PMU_SRC_CFG_RCHF_EN_VALUE_DISABLE << PMU_SRC_CFG_RCHF_EN_SHIFT)\r\n#define PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE   1U\r\n#define PMU_SRC_CFG_RCHF_EN_BITS_ENABLE    (PMU_SRC_CFG_RCHF_EN_VALUE_ENABLE << PMU_SRC_CFG_RCHF_EN_SHIFT)\r\n\r\n#define PMU_SRC_CFG_RCHF_SEL_SHIFT         1\r\n#define PMU_SRC_CFG_RCHF_SEL_WIDTH         1\r\n#define PMU_SRC_CFG_RCHF_SEL_MASK          (((1U << PMU_SRC_CFG_RCHF_SEL_WIDTH) - 1U) << PMU_SRC_CFG_RCHF_SEL_SHIFT)\r\n#define PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ   0U\r\n#define PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ    (PMU_SRC_CFG_RCHF_SEL_VALUE_48MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT)\r\n#define PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ   1U\r\n#define PMU_SRC_CFG_RCHF_SEL_BITS_24MHZ    (PMU_SRC_CFG_RCHF_SEL_VALUE_24MHZ << PMU_SRC_CFG_RCHF_SEL_SHIFT)\r\n\r\n#define PMU_TRIM_POW0_ADDR                 (PMU_BASE_ADDR + 0x0020U)\r\n#define PMU_TRIM_POW0                      (*(volatile uint32_t *)PMU_TRIM_POW0_ADDR)\r\n#define PMU_TRIM_POW1_ADDR                 (PMU_BASE_ADDR + 0x0024U)\r\n#define PMU_TRIM_POW1                      (*(volatile uint32_t *)PMU_TRIM_POW1_ADDR)\r\n#define PMU_TRIM_POW2_ADDR                 (PMU_BASE_ADDR + 0x0028U)\r\n#define PMU_TRIM_POW2                      (*(volatile uint32_t *)PMU_TRIM_POW2_ADDR)\r\n#define PMU_TRIM_POW3_ADDR                 (PMU_BASE_ADDR + 0x002CU)\r\n#define PMU_TRIM_POW3                      (*(volatile uint32_t *)PMU_TRIM_POW3_ADDR)\r\n#define PMU_TRIM_RCHF_ADDR                 (PMU_BASE_ADDR + 0x0030U)\r\n#define PMU_TRIM_RCHF                      (*(volatile uint32_t *)PMU_TRIM_RCHF_ADDR)\r\n#define PMU_TRIM_RCLF_ADDR                 (PMU_BASE_ADDR + 0x0034U)\r\n#define PMU_TRIM_RCLF                      (*(volatile uint32_t *)PMU_TRIM_RCLF_ADDR)\r\n#define PMU_TRIM_OPA_ADDR                  (PMU_BASE_ADDR + 0x0038U)\r\n#define PMU_TRIM_OPA                       (*(volatile uint32_t *)PMU_TRIM_OPA_ADDR)\r\n#define PMU_TRIM_PLL_ADDR                  (PMU_BASE_ADDR + 0x003CU)\r\n#define PMU_TRIM_PLL                       (*(volatile uint32_t *)PMU_TRIM_PLL_ADDR)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/portcon.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_PORTCON_H\r\n#define HARDWARE_DP32G030_PORTCON_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- PORTCON -------- */\r\n#define PORTCON_BASE_ADDR                           0x400B0000U\r\n#define PORTCON_BASE_SIZE                           0x00000800U\r\n\r\n#define PORTCON_PORTA_SEL0_ADDR                     (PORTCON_BASE_ADDR + 0x0000U)\r\n#define PORTCON_PORTA_SEL0                          (*(volatile uint32_t *)PORTCON_PORTA_SEL0_ADDR)\r\n#define PORTCON_PORTA_SEL0_A0_SHIFT                 0\r\n#define PORTCON_PORTA_SEL0_A0_WIDTH                 4\r\n#define PORTCON_PORTA_SEL0_A0_MASK                  (((1U << PORTCON_PORTA_SEL0_A0_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A0_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A0_VALUE_GPIOA0          0U\r\n#define PORTCON_PORTA_SEL0_A0_BITS_GPIOA0           (PORTCON_PORTA_SEL0_A0_VALUE_GPIOA0 << PORTCON_PORTA_SEL0_A0_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A0_VALUE_PWMP1_PLUS0     1U\r\n#define PORTCON_PORTA_SEL0_A0_BITS_PWMP1_PLUS0      (PORTCON_PORTA_SEL0_A0_VALUE_PWMP1_PLUS0 << PORTCON_PORTA_SEL0_A0_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A0_VALUE_PWMP0_PLUS1     2U\r\n#define PORTCON_PORTA_SEL0_A0_BITS_PWMP0_PLUS1      (PORTCON_PORTA_SEL0_A0_VALUE_PWMP0_PLUS1 << PORTCON_PORTA_SEL0_A0_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A0_VALUE_TM              3U\r\n#define PORTCON_PORTA_SEL0_A0_BITS_TM               (PORTCON_PORTA_SEL0_A0_VALUE_TM << PORTCON_PORTA_SEL0_A0_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A0_VALUE_WAKEUP0         4U\r\n#define PORTCON_PORTA_SEL0_A0_BITS_WAKEUP0          (PORTCON_PORTA_SEL0_A0_VALUE_WAKEUP0 << PORTCON_PORTA_SEL0_A0_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL0_A1_SHIFT                 4\r\n#define PORTCON_PORTA_SEL0_A1_WIDTH                 4\r\n#define PORTCON_PORTA_SEL0_A1_MASK                  (((1U << PORTCON_PORTA_SEL0_A1_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A1_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A1_VALUE_GPIOA1          0U\r\n#define PORTCON_PORTA_SEL0_A1_BITS_GPIOA1           (PORTCON_PORTA_SEL0_A1_VALUE_GPIOA1 << PORTCON_PORTA_SEL0_A1_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A1_VALUE_XTAL_XI         1U\r\n#define PORTCON_PORTA_SEL0_A1_BITS_XTAL_XI          (PORTCON_PORTA_SEL0_A1_VALUE_XTAL_XI << PORTCON_PORTA_SEL0_A1_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL0_A2_SHIFT                 8\r\n#define PORTCON_PORTA_SEL0_A2_WIDTH                 4\r\n#define PORTCON_PORTA_SEL0_A2_MASK                  (((1U << PORTCON_PORTA_SEL0_A2_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A2_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A2_VALUE_GPIOA2          0U\r\n#define PORTCON_PORTA_SEL0_A2_BITS_GPIOA2           (PORTCON_PORTA_SEL0_A2_VALUE_GPIOA2 << PORTCON_PORTA_SEL0_A2_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A2_VALUE_XTAL_XO         1U\r\n#define PORTCON_PORTA_SEL0_A2_BITS_XTAL_XO          (PORTCON_PORTA_SEL0_A2_VALUE_XTAL_XO << PORTCON_PORTA_SEL0_A2_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL0_A3_SHIFT                 12\r\n#define PORTCON_PORTA_SEL0_A3_WIDTH                 4\r\n#define PORTCON_PORTA_SEL0_A3_MASK                  (((1U << PORTCON_PORTA_SEL0_A3_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A3_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A3_VALUE_GPIOA3          0U\r\n#define PORTCON_PORTA_SEL0_A3_BITS_GPIOA3           (PORTCON_PORTA_SEL0_A3_VALUE_GPIOA3 << PORTCON_PORTA_SEL0_A3_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A3_VALUE_CMP0_VN         1U\r\n#define PORTCON_PORTA_SEL0_A3_BITS_CMP0_VN          (PORTCON_PORTA_SEL0_A3_VALUE_CMP0_VN << PORTCON_PORTA_SEL0_A3_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A3_VALUE_XTAH_XI         2U\r\n#define PORTCON_PORTA_SEL0_A3_BITS_XTAH_XI          (PORTCON_PORTA_SEL0_A3_VALUE_XTAH_XI << PORTCON_PORTA_SEL0_A3_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL0_A4_SHIFT                 16\r\n#define PORTCON_PORTA_SEL0_A4_WIDTH                 4\r\n#define PORTCON_PORTA_SEL0_A4_MASK                  (((1U << PORTCON_PORTA_SEL0_A4_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A4_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A4_VALUE_GPIOA4          0U\r\n#define PORTCON_PORTA_SEL0_A4_BITS_GPIOA4           (PORTCON_PORTA_SEL0_A4_VALUE_GPIOA4 << PORTCON_PORTA_SEL0_A4_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A4_VALUE_CMP0_VP         1U\r\n#define PORTCON_PORTA_SEL0_A4_BITS_CMP0_VP          (PORTCON_PORTA_SEL0_A4_VALUE_CMP0_VP << PORTCON_PORTA_SEL0_A4_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A4_VALUE_XTAH_XO         2U\r\n#define PORTCON_PORTA_SEL0_A4_BITS_XTAH_XO          (PORTCON_PORTA_SEL0_A4_VALUE_XTAH_XO << PORTCON_PORTA_SEL0_A4_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL0_A5_SHIFT                 20\r\n#define PORTCON_PORTA_SEL0_A5_WIDTH                 4\r\n#define PORTCON_PORTA_SEL0_A5_MASK                  (((1U << PORTCON_PORTA_SEL0_A5_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A5_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A5_VALUE_GPIOA5          0U\r\n#define PORTCON_PORTA_SEL0_A5_BITS_GPIOA5           (PORTCON_PORTA_SEL0_A5_VALUE_GPIOA5 << PORTCON_PORTA_SEL0_A5_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A5_VALUE_UART1_CTS       1U\r\n#define PORTCON_PORTA_SEL0_A5_BITS_UART1_CTS        (PORTCON_PORTA_SEL0_A5_VALUE_UART1_CTS << PORTCON_PORTA_SEL0_A5_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A5_VALUE_PWMP1_PLUS1     2U\r\n#define PORTCON_PORTA_SEL0_A5_BITS_PWMP1_PLUS1      (PORTCON_PORTA_SEL0_A5_VALUE_PWMP1_PLUS1 << PORTCON_PORTA_SEL0_A5_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_IN0     3U\r\n#define PORTCON_PORTA_SEL0_A5_BITS_TIMERP1_IN0      (PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL0_A5_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_OUT_L   4U\r\n#define PORTCON_PORTA_SEL0_A5_BITS_TIMERP1_OUT_L    (PORTCON_PORTA_SEL0_A5_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL0_A5_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A5_VALUE_WAKEUP1         5U\r\n#define PORTCON_PORTA_SEL0_A5_BITS_WAKEUP1          (PORTCON_PORTA_SEL0_A5_VALUE_WAKEUP1 << PORTCON_PORTA_SEL0_A5_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A5_VALUE_SARADC_CH1      6U\r\n#define PORTCON_PORTA_SEL0_A5_BITS_SARADC_CH1       (PORTCON_PORTA_SEL0_A5_VALUE_SARADC_CH1 << PORTCON_PORTA_SEL0_A5_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL0_A6_SHIFT                 24\r\n#define PORTCON_PORTA_SEL0_A6_WIDTH                 4\r\n#define PORTCON_PORTA_SEL0_A6_MASK                  (((1U << PORTCON_PORTA_SEL0_A6_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A6_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A6_VALUE_GPIOA6          0U\r\n#define PORTCON_PORTA_SEL0_A6_BITS_GPIOA6           (PORTCON_PORTA_SEL0_A6_VALUE_GPIOA6 << PORTCON_PORTA_SEL0_A6_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A6_VALUE_UART1_RTS       1U\r\n#define PORTCON_PORTA_SEL0_A6_BITS_UART1_RTS        (PORTCON_PORTA_SEL0_A6_VALUE_UART1_RTS << PORTCON_PORTA_SEL0_A6_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_IN1     2U\r\n#define PORTCON_PORTA_SEL0_A6_BITS_TIMERP1_IN1      (PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL0_A6_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_OUT_H   3U\r\n#define PORTCON_PORTA_SEL0_A6_BITS_TIMERP1_OUT_H    (PORTCON_PORTA_SEL0_A6_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL0_A6_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A6_VALUE_SARADC_CH1      4U\r\n#define PORTCON_PORTA_SEL0_A6_BITS_SARADC_CH1       (PORTCON_PORTA_SEL0_A6_VALUE_SARADC_CH1 << PORTCON_PORTA_SEL0_A6_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A6_VALUE_OPA0_OUT        5U\r\n#define PORTCON_PORTA_SEL0_A6_BITS_OPA0_OUT         (PORTCON_PORTA_SEL0_A6_VALUE_OPA0_OUT << PORTCON_PORTA_SEL0_A6_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL0_A7_SHIFT                 28\r\n#define PORTCON_PORTA_SEL0_A7_WIDTH                 4\r\n#define PORTCON_PORTA_SEL0_A7_MASK                  (((1U << PORTCON_PORTA_SEL0_A7_WIDTH) - 1U) << PORTCON_PORTA_SEL0_A7_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A7_VALUE_GPIOA7          0U\r\n#define PORTCON_PORTA_SEL0_A7_BITS_GPIOA7           (PORTCON_PORTA_SEL0_A7_VALUE_GPIOA7 << PORTCON_PORTA_SEL0_A7_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A7_VALUE_UART1_TX        1U\r\n#define PORTCON_PORTA_SEL0_A7_BITS_UART1_TX         (PORTCON_PORTA_SEL0_A7_VALUE_UART1_TX << PORTCON_PORTA_SEL0_A7_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_IN0     2U\r\n#define PORTCON_PORTA_SEL0_A7_BITS_TIMERP0_IN0      (PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_IN0 << PORTCON_PORTA_SEL0_A7_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_OUT_L   3U\r\n#define PORTCON_PORTA_SEL0_A7_BITS_TIMERP0_OUT_L    (PORTCON_PORTA_SEL0_A7_VALUE_TIMERP0_OUT_L << PORTCON_PORTA_SEL0_A7_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A7_VALUE_SARADC_CH2      4U\r\n#define PORTCON_PORTA_SEL0_A7_BITS_SARADC_CH2       (PORTCON_PORTA_SEL0_A7_VALUE_SARADC_CH2 << PORTCON_PORTA_SEL0_A7_SHIFT)\r\n#define PORTCON_PORTA_SEL0_A7_VALUE_OPA0_VP         5U\r\n#define PORTCON_PORTA_SEL0_A7_BITS_OPA0_VP          (PORTCON_PORTA_SEL0_A7_VALUE_OPA0_VP << PORTCON_PORTA_SEL0_A7_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL1_ADDR                     (PORTCON_BASE_ADDR + 0x0004U)\r\n#define PORTCON_PORTA_SEL1                          (*(volatile uint32_t *)PORTCON_PORTA_SEL1_ADDR)\r\n#define PORTCON_PORTA_SEL1_A8_SHIFT                 0\r\n#define PORTCON_PORTA_SEL1_A8_WIDTH                 4\r\n#define PORTCON_PORTA_SEL1_A8_MASK                  (((1U << PORTCON_PORTA_SEL1_A8_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A8_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A8_VALUE_GPIOA8          0U\r\n#define PORTCON_PORTA_SEL1_A8_BITS_GPIOA8           (PORTCON_PORTA_SEL1_A8_VALUE_GPIOA8 << PORTCON_PORTA_SEL1_A8_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A8_VALUE_UART1_RX        1U\r\n#define PORTCON_PORTA_SEL1_A8_BITS_UART1_RX         (PORTCON_PORTA_SEL1_A8_VALUE_UART1_RX << PORTCON_PORTA_SEL1_A8_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_IN1     2U\r\n#define PORTCON_PORTA_SEL1_A8_BITS_TIMERP0_IN1      (PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_IN1 << PORTCON_PORTA_SEL1_A8_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_OUT_H   3U\r\n#define PORTCON_PORTA_SEL1_A8_BITS_TIMERP0_OUT_H    (PORTCON_PORTA_SEL1_A8_VALUE_TIMERP0_OUT_H << PORTCON_PORTA_SEL1_A8_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A8_VALUE_SARADC_CH3      4U\r\n#define PORTCON_PORTA_SEL1_A8_BITS_SARADC_CH3       (PORTCON_PORTA_SEL1_A8_VALUE_SARADC_CH3 << PORTCON_PORTA_SEL1_A8_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A8_VALUE_OPA0_VN         5U\r\n#define PORTCON_PORTA_SEL1_A8_BITS_OPA0_VN          (PORTCON_PORTA_SEL1_A8_VALUE_OPA0_VN << PORTCON_PORTA_SEL1_A8_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL1_A9_SHIFT                 4\r\n#define PORTCON_PORTA_SEL1_A9_WIDTH                 4\r\n#define PORTCON_PORTA_SEL1_A9_MASK                  (((1U << PORTCON_PORTA_SEL1_A9_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A9_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A9_VALUE_GPIOA9          0U\r\n#define PORTCON_PORTA_SEL1_A9_BITS_GPIOA9           (PORTCON_PORTA_SEL1_A9_VALUE_GPIOA9 << PORTCON_PORTA_SEL1_A9_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A9_VALUE_SPI0_SSN        1U\r\n#define PORTCON_PORTA_SEL1_A9_BITS_SPI0_SSN         (PORTCON_PORTA_SEL1_A9_VALUE_SPI0_SSN << PORTCON_PORTA_SEL1_A9_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_IN0     2U\r\n#define PORTCON_PORTA_SEL1_A9_BITS_TIMERP1_IN0      (PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL1_A9_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_OUT_L   3U\r\n#define PORTCON_PORTA_SEL1_A9_BITS_TIMERP1_OUT_L    (PORTCON_PORTA_SEL1_A9_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL1_A9_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A9_VALUE_TM              4U\r\n#define PORTCON_PORTA_SEL1_A9_BITS_TM               (PORTCON_PORTA_SEL1_A9_VALUE_TM << PORTCON_PORTA_SEL1_A9_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A9_VALUE_SARADC_CH4      5U\r\n#define PORTCON_PORTA_SEL1_A9_BITS_SARADC_CH4       (PORTCON_PORTA_SEL1_A9_VALUE_SARADC_CH4 << PORTCON_PORTA_SEL1_A9_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A9_VALUE_CMP1_VN         6U\r\n#define PORTCON_PORTA_SEL1_A9_BITS_CMP1_VN          (PORTCON_PORTA_SEL1_A9_VALUE_CMP1_VN << PORTCON_PORTA_SEL1_A9_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL1_A10_SHIFT                8\r\n#define PORTCON_PORTA_SEL1_A10_WIDTH                4\r\n#define PORTCON_PORTA_SEL1_A10_MASK                 (((1U << PORTCON_PORTA_SEL1_A10_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A10_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A10_VALUE_GPIOA10        0U\r\n#define PORTCON_PORTA_SEL1_A10_BITS_GPIOA10         (PORTCON_PORTA_SEL1_A10_VALUE_GPIOA10 << PORTCON_PORTA_SEL1_A10_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A10_VALUE_SPI0_CLK       1U\r\n#define PORTCON_PORTA_SEL1_A10_BITS_SPI0_CLK        (PORTCON_PORTA_SEL1_A10_VALUE_SPI0_CLK << PORTCON_PORTA_SEL1_A10_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A10_VALUE_SARADC_CH5     2U\r\n#define PORTCON_PORTA_SEL1_A10_BITS_SARADC_CH5      (PORTCON_PORTA_SEL1_A10_VALUE_SARADC_CH5 << PORTCON_PORTA_SEL1_A10_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A10_VALUE_CMP1_VP        3U\r\n#define PORTCON_PORTA_SEL1_A10_BITS_CMP1_VP         (PORTCON_PORTA_SEL1_A10_VALUE_CMP1_VP << PORTCON_PORTA_SEL1_A10_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL1_A11_SHIFT                12\r\n#define PORTCON_PORTA_SEL1_A11_WIDTH                4\r\n#define PORTCON_PORTA_SEL1_A11_MASK                 (((1U << PORTCON_PORTA_SEL1_A11_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A11_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A11_VALUE_GPIOA11        0U\r\n#define PORTCON_PORTA_SEL1_A11_BITS_GPIOA11         (PORTCON_PORTA_SEL1_A11_VALUE_GPIOA11 << PORTCON_PORTA_SEL1_A11_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A11_VALUE_SPI0_MISO      1U\r\n#define PORTCON_PORTA_SEL1_A11_BITS_SPI0_MISO       (PORTCON_PORTA_SEL1_A11_VALUE_SPI0_MISO << PORTCON_PORTA_SEL1_A11_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A11_VALUE_PWMB0_CH0      2U\r\n#define PORTCON_PORTA_SEL1_A11_BITS_PWMB0_CH0       (PORTCON_PORTA_SEL1_A11_VALUE_PWMB0_CH0 << PORTCON_PORTA_SEL1_A11_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A11_VALUE_PWMP0_BRAKE0   3U\r\n#define PORTCON_PORTA_SEL1_A11_BITS_PWMP0_BRAKE0    (PORTCON_PORTA_SEL1_A11_VALUE_PWMP0_BRAKE0 << PORTCON_PORTA_SEL1_A11_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_IN1    4U\r\n#define PORTCON_PORTA_SEL1_A11_BITS_TIMERP1_IN1     (PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL1_A11_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_OUT_H  5U\r\n#define PORTCON_PORTA_SEL1_A11_BITS_TIMERP1_OUT_H   (PORTCON_PORTA_SEL1_A11_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL1_A11_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A11_VALUE_SARADC_CH6     6U\r\n#define PORTCON_PORTA_SEL1_A11_BITS_SARADC_CH6      (PORTCON_PORTA_SEL1_A11_VALUE_SARADC_CH6 << PORTCON_PORTA_SEL1_A11_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL1_A12_SHIFT                16\r\n#define PORTCON_PORTA_SEL1_A12_WIDTH                4\r\n#define PORTCON_PORTA_SEL1_A12_MASK                 (((1U << PORTCON_PORTA_SEL1_A12_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A12_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A12_VALUE_GPIOA12        0U\r\n#define PORTCON_PORTA_SEL1_A12_BITS_GPIOA12         (PORTCON_PORTA_SEL1_A12_VALUE_GPIOA12 << PORTCON_PORTA_SEL1_A12_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A12_VALUE_SPI0_MOSI      1U\r\n#define PORTCON_PORTA_SEL1_A12_BITS_SPI0_MOSI       (PORTCON_PORTA_SEL1_A12_VALUE_SPI0_MOSI << PORTCON_PORTA_SEL1_A12_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A12_VALUE_PWMB0_CH1      2U\r\n#define PORTCON_PORTA_SEL1_A12_BITS_PWMB0_CH1       (PORTCON_PORTA_SEL1_A12_VALUE_PWMB0_CH1 << PORTCON_PORTA_SEL1_A12_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A12_VALUE_PWMP0_CH0N     3U\r\n#define PORTCON_PORTA_SEL1_A12_BITS_PWMP0_CH0N      (PORTCON_PORTA_SEL1_A12_VALUE_PWMP0_CH0N << PORTCON_PORTA_SEL1_A12_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_IN0    4U\r\n#define PORTCON_PORTA_SEL1_A12_BITS_TIMERP0_IN0     (PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_IN0 << PORTCON_PORTA_SEL1_A12_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_OUT_L  5U\r\n#define PORTCON_PORTA_SEL1_A12_BITS_TIMERP0_OUT_L   (PORTCON_PORTA_SEL1_A12_VALUE_TIMERP0_OUT_L << PORTCON_PORTA_SEL1_A12_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A12_VALUE_SARADC_CH7     6U\r\n#define PORTCON_PORTA_SEL1_A12_BITS_SARADC_CH7      (PORTCON_PORTA_SEL1_A12_VALUE_SARADC_CH7 << PORTCON_PORTA_SEL1_A12_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL1_A13_SHIFT                20\r\n#define PORTCON_PORTA_SEL1_A13_WIDTH                4\r\n#define PORTCON_PORTA_SEL1_A13_MASK                 (((1U << PORTCON_PORTA_SEL1_A13_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A13_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A13_VALUE_GPIOA13        0U\r\n#define PORTCON_PORTA_SEL1_A13_BITS_GPIOA13         (PORTCON_PORTA_SEL1_A13_VALUE_GPIOA13 << PORTCON_PORTA_SEL1_A13_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A13_VALUE_PWMB0_CH2      1U\r\n#define PORTCON_PORTA_SEL1_A13_BITS_PWMB0_CH2       (PORTCON_PORTA_SEL1_A13_VALUE_PWMB0_CH2 << PORTCON_PORTA_SEL1_A13_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A13_VALUE_PWMP0_CH1N     2U\r\n#define PORTCON_PORTA_SEL1_A13_BITS_PWMP0_CH1N      (PORTCON_PORTA_SEL1_A13_VALUE_PWMP0_CH1N << PORTCON_PORTA_SEL1_A13_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_IN1    3U\r\n#define PORTCON_PORTA_SEL1_A13_BITS_TIMERP0_IN1     (PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_IN1 << PORTCON_PORTA_SEL1_A13_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_OUT_H  4U\r\n#define PORTCON_PORTA_SEL1_A13_BITS_TIMERP0_OUT_H   (PORTCON_PORTA_SEL1_A13_VALUE_TIMERP0_OUT_H << PORTCON_PORTA_SEL1_A13_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A13_VALUE_SARADC_CH8     5U\r\n#define PORTCON_PORTA_SEL1_A13_BITS_SARADC_CH8      (PORTCON_PORTA_SEL1_A13_VALUE_SARADC_CH8 << PORTCON_PORTA_SEL1_A13_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL1_A14_SHIFT                24\r\n#define PORTCON_PORTA_SEL1_A14_WIDTH                4\r\n#define PORTCON_PORTA_SEL1_A14_MASK                 (((1U << PORTCON_PORTA_SEL1_A14_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A14_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A14_VALUE_GPIOA14        0U\r\n#define PORTCON_PORTA_SEL1_A14_BITS_GPIOA14         (PORTCON_PORTA_SEL1_A14_VALUE_GPIOA14 << PORTCON_PORTA_SEL1_A14_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A14_VALUE_PWMB1_CH0      1U\r\n#define PORTCON_PORTA_SEL1_A14_BITS_PWMB1_CH0       (PORTCON_PORTA_SEL1_A14_VALUE_PWMB1_CH0 << PORTCON_PORTA_SEL1_A14_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A14_VALUE_PWMP0_CH2N     2U\r\n#define PORTCON_PORTA_SEL1_A14_BITS_PWMP0_CH2N      (PORTCON_PORTA_SEL1_A14_VALUE_PWMP0_CH2N << PORTCON_PORTA_SEL1_A14_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_IN0    3U\r\n#define PORTCON_PORTA_SEL1_A14_BITS_TIMERP1_IN0     (PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_IN0 << PORTCON_PORTA_SEL1_A14_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_OUT_L  4U\r\n#define PORTCON_PORTA_SEL1_A14_BITS_TIMERP1_OUT_L   (PORTCON_PORTA_SEL1_A14_VALUE_TIMERP1_OUT_L << PORTCON_PORTA_SEL1_A14_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A14_VALUE_SARADC_CH9     5U\r\n#define PORTCON_PORTA_SEL1_A14_BITS_SARADC_CH9      (PORTCON_PORTA_SEL1_A14_VALUE_SARADC_CH9 << PORTCON_PORTA_SEL1_A14_SHIFT)\r\n\r\n#define PORTCON_PORTA_SEL1_A15_SHIFT                28\r\n#define PORTCON_PORTA_SEL1_A15_WIDTH                4\r\n#define PORTCON_PORTA_SEL1_A15_MASK                 (((1U << PORTCON_PORTA_SEL1_A15_WIDTH) - 1U) << PORTCON_PORTA_SEL1_A15_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A15_VALUE_GPIOA15        0U\r\n#define PORTCON_PORTA_SEL1_A15_BITS_GPIOA15         (PORTCON_PORTA_SEL1_A15_VALUE_GPIOA15 << PORTCON_PORTA_SEL1_A15_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A15_VALUE_PWMB1_CH1      1U\r\n#define PORTCON_PORTA_SEL1_A15_BITS_PWMB1_CH1       (PORTCON_PORTA_SEL1_A15_VALUE_PWMB1_CH1 << PORTCON_PORTA_SEL1_A15_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A15_VALUE_PWMP0_CH0      2U\r\n#define PORTCON_PORTA_SEL1_A15_BITS_PWMP0_CH0       (PORTCON_PORTA_SEL1_A15_VALUE_PWMP0_CH0 << PORTCON_PORTA_SEL1_A15_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_IN1    3U\r\n#define PORTCON_PORTA_SEL1_A15_BITS_TIMERP1_IN1     (PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_IN1 << PORTCON_PORTA_SEL1_A15_SHIFT)\r\n#define PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_OUT_H  4U\r\n#define PORTCON_PORTA_SEL1_A15_BITS_TIMERP1_OUT_H   (PORTCON_PORTA_SEL1_A15_VALUE_TIMERP1_OUT_H << PORTCON_PORTA_SEL1_A15_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL0_ADDR                     (PORTCON_BASE_ADDR + 0x0008U)\r\n#define PORTCON_PORTB_SEL0                          (*(volatile uint32_t *)PORTCON_PORTB_SEL0_ADDR)\r\n#define PORTCON_PORTB_SEL0_B0_SHIFT                 0\r\n#define PORTCON_PORTB_SEL0_B0_WIDTH                 4\r\n#define PORTCON_PORTB_SEL0_B0_MASK                  (((1U << PORTCON_PORTB_SEL0_B0_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B0_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B0_VALUE_GPIOB0          0U\r\n#define PORTCON_PORTB_SEL0_B0_BITS_GPIOB0           (PORTCON_PORTB_SEL0_B0_VALUE_GPIOB0 << PORTCON_PORTB_SEL0_B0_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B0_VALUE_UART2_TX        1U\r\n#define PORTCON_PORTB_SEL0_B0_BITS_UART2_TX         (PORTCON_PORTB_SEL0_B0_VALUE_UART2_TX << PORTCON_PORTB_SEL0_B0_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B0_VALUE_IIC0_SCL        2U\r\n#define PORTCON_PORTB_SEL0_B0_BITS_IIC0_SCL         (PORTCON_PORTB_SEL0_B0_VALUE_IIC0_SCL << PORTCON_PORTB_SEL0_B0_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B0_VALUE_PWMB1_CH2       3U\r\n#define PORTCON_PORTB_SEL0_B0_BITS_PWMB1_CH2        (PORTCON_PORTB_SEL0_B0_VALUE_PWMB1_CH2 << PORTCON_PORTB_SEL0_B0_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B0_VALUE_PWMP0_CH1       4U\r\n#define PORTCON_PORTB_SEL0_B0_BITS_PWMP0_CH1        (PORTCON_PORTB_SEL0_B0_VALUE_PWMP0_CH1 << PORTCON_PORTB_SEL0_B0_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL0_B1_SHIFT                 4\r\n#define PORTCON_PORTB_SEL0_B1_WIDTH                 4\r\n#define PORTCON_PORTB_SEL0_B1_MASK                  (((1U << PORTCON_PORTB_SEL0_B1_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B1_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B1_VALUE_GPIOB1          0U\r\n#define PORTCON_PORTB_SEL0_B1_BITS_GPIOB1           (PORTCON_PORTB_SEL0_B1_VALUE_GPIOB1 << PORTCON_PORTB_SEL0_B1_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B1_VALUE_UART2_RX        1U\r\n#define PORTCON_PORTB_SEL0_B1_BITS_UART2_RX         (PORTCON_PORTB_SEL0_B1_VALUE_UART2_RX << PORTCON_PORTB_SEL0_B1_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B1_VALUE_IIC0_SDA        2U\r\n#define PORTCON_PORTB_SEL0_B1_BITS_IIC0_SDA         (PORTCON_PORTB_SEL0_B1_VALUE_IIC0_SDA << PORTCON_PORTB_SEL0_B1_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B1_VALUE_PWMP0_CH2       3U\r\n#define PORTCON_PORTB_SEL0_B1_BITS_PWMP0_CH2        (PORTCON_PORTB_SEL0_B1_VALUE_PWMP0_CH2 << PORTCON_PORTB_SEL0_B1_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL0_B2_SHIFT                 8\r\n#define PORTCON_PORTB_SEL0_B2_WIDTH                 4\r\n#define PORTCON_PORTB_SEL0_B2_MASK                  (((1U << PORTCON_PORTB_SEL0_B2_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B2_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B2_VALUE_GPIOB2          0U\r\n#define PORTCON_PORTB_SEL0_B2_BITS_GPIOB2           (PORTCON_PORTB_SEL0_B2_VALUE_GPIOB2 << PORTCON_PORTB_SEL0_B2_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B2_VALUE_SPI1_SSN        1U\r\n#define PORTCON_PORTB_SEL0_B2_BITS_SPI1_SSN         (PORTCON_PORTB_SEL0_B2_VALUE_SPI1_SSN << PORTCON_PORTB_SEL0_B2_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B2_VALUE_PWMP0_BRAKE1    2U\r\n#define PORTCON_PORTB_SEL0_B2_BITS_PWMP0_BRAKE1     (PORTCON_PORTB_SEL0_B2_VALUE_PWMP0_BRAKE1 << PORTCON_PORTB_SEL0_B2_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B2_VALUE_TIMERP1_HALL0   3U\r\n#define PORTCON_PORTB_SEL0_B2_BITS_TIMERP1_HALL0    (PORTCON_PORTB_SEL0_B2_VALUE_TIMERP1_HALL0 << PORTCON_PORTB_SEL0_B2_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL0_B3_SHIFT                 12\r\n#define PORTCON_PORTB_SEL0_B3_WIDTH                 4\r\n#define PORTCON_PORTB_SEL0_B3_MASK                  (((1U << PORTCON_PORTB_SEL0_B3_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B3_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B3_VALUE_GPIOB3          0U\r\n#define PORTCON_PORTB_SEL0_B3_BITS_GPIOB3           (PORTCON_PORTB_SEL0_B3_VALUE_GPIOB3 << PORTCON_PORTB_SEL0_B3_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B3_VALUE_SPI1_CLK        1U\r\n#define PORTCON_PORTB_SEL0_B3_BITS_SPI1_CLK         (PORTCON_PORTB_SEL0_B3_VALUE_SPI1_CLK << PORTCON_PORTB_SEL0_B3_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B3_VALUE_IIC1_SDA        2U\r\n#define PORTCON_PORTB_SEL0_B3_BITS_IIC1_SDA         (PORTCON_PORTB_SEL0_B3_VALUE_IIC1_SDA << PORTCON_PORTB_SEL0_B3_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B3_VALUE_PWMP0_CH0N      3U\r\n#define PORTCON_PORTB_SEL0_B3_BITS_PWMP0_CH0N       (PORTCON_PORTB_SEL0_B3_VALUE_PWMP0_CH0N << PORTCON_PORTB_SEL0_B3_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B3_VALUE_TIMERP1_HALL1   4U\r\n#define PORTCON_PORTB_SEL0_B3_BITS_TIMERP1_HALL1    (PORTCON_PORTB_SEL0_B3_VALUE_TIMERP1_HALL1 << PORTCON_PORTB_SEL0_B3_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL0_B4_SHIFT                 16\r\n#define PORTCON_PORTB_SEL0_B4_WIDTH                 4\r\n#define PORTCON_PORTB_SEL0_B4_MASK                  (((1U << PORTCON_PORTB_SEL0_B4_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B4_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B4_VALUE_GPIOB4          0U\r\n#define PORTCON_PORTB_SEL0_B4_BITS_GPIOB4           (PORTCON_PORTB_SEL0_B4_VALUE_GPIOB4 << PORTCON_PORTB_SEL0_B4_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B4_VALUE_SPI1_MISO       1U\r\n#define PORTCON_PORTB_SEL0_B4_BITS_SPI1_MISO        (PORTCON_PORTB_SEL0_B4_VALUE_SPI1_MISO << PORTCON_PORTB_SEL0_B4_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B4_VALUE_IIC1_SCL        2U\r\n#define PORTCON_PORTB_SEL0_B4_BITS_IIC1_SCL         (PORTCON_PORTB_SEL0_B4_VALUE_IIC1_SCL << PORTCON_PORTB_SEL0_B4_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B4_VALUE_PWMP1_CH0       3U\r\n#define PORTCON_PORTB_SEL0_B4_BITS_PWMP1_CH0        (PORTCON_PORTB_SEL0_B4_VALUE_PWMP1_CH0 << PORTCON_PORTB_SEL0_B4_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B4_VALUE_PWMP0_CH1N      4U\r\n#define PORTCON_PORTB_SEL0_B4_BITS_PWMP0_CH1N       (PORTCON_PORTB_SEL0_B4_VALUE_PWMP0_CH1N << PORTCON_PORTB_SEL0_B4_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B4_VALUE_TIMERP1_HALL2   5U\r\n#define PORTCON_PORTB_SEL0_B4_BITS_TIMERP1_HALL2    (PORTCON_PORTB_SEL0_B4_VALUE_TIMERP1_HALL2 << PORTCON_PORTB_SEL0_B4_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL0_B5_SHIFT                 20\r\n#define PORTCON_PORTB_SEL0_B5_WIDTH                 4\r\n#define PORTCON_PORTB_SEL0_B5_MASK                  (((1U << PORTCON_PORTB_SEL0_B5_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B5_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B5_VALUE_GPIOB5          0U\r\n#define PORTCON_PORTB_SEL0_B5_BITS_GPIOB5           (PORTCON_PORTB_SEL0_B5_VALUE_GPIOB5 << PORTCON_PORTB_SEL0_B5_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B5_VALUE_SPI1_MOSI       1U\r\n#define PORTCON_PORTB_SEL0_B5_BITS_SPI1_MOSI        (PORTCON_PORTB_SEL0_B5_VALUE_SPI1_MOSI << PORTCON_PORTB_SEL0_B5_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B5_VALUE_PWMP1_CH0N      2U\r\n#define PORTCON_PORTB_SEL0_B5_BITS_PWMP1_CH0N       (PORTCON_PORTB_SEL0_B5_VALUE_PWMP1_CH0N << PORTCON_PORTB_SEL0_B5_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B5_VALUE_PWMP0_CH2N      3U\r\n#define PORTCON_PORTB_SEL0_B5_BITS_PWMP0_CH2N       (PORTCON_PORTB_SEL0_B5_VALUE_PWMP0_CH2N << PORTCON_PORTB_SEL0_B5_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_IN0     4U\r\n#define PORTCON_PORTB_SEL0_B5_BITS_TIMERP0_IN0      (PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_IN0 << PORTCON_PORTB_SEL0_B5_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_OUT_L   5U\r\n#define PORTCON_PORTB_SEL0_B5_BITS_TIMERP0_OUT_L    (PORTCON_PORTB_SEL0_B5_VALUE_TIMERP0_OUT_L << PORTCON_PORTB_SEL0_B5_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL0_B6_SHIFT                 24\r\n#define PORTCON_PORTB_SEL0_B6_WIDTH                 4\r\n#define PORTCON_PORTB_SEL0_B6_MASK                  (((1U << PORTCON_PORTB_SEL0_B6_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B6_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B6_VALUE_GPIOB6          0U\r\n#define PORTCON_PORTB_SEL0_B6_BITS_GPIOB6           (PORTCON_PORTB_SEL0_B6_VALUE_GPIOB6 << PORTCON_PORTB_SEL0_B6_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B6_VALUE_PWMP0_CH0       1U\r\n#define PORTCON_PORTB_SEL0_B6_BITS_PWMP0_CH0        (PORTCON_PORTB_SEL0_B6_VALUE_PWMP0_CH0 << PORTCON_PORTB_SEL0_B6_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_IN1     2U\r\n#define PORTCON_PORTB_SEL0_B6_BITS_TIMERP0_IN1      (PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_IN1 << PORTCON_PORTB_SEL0_B6_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_OUT_H   3U\r\n#define PORTCON_PORTB_SEL0_B6_BITS_TIMERP0_OUT_H    (PORTCON_PORTB_SEL0_B6_VALUE_TIMERP0_OUT_H << PORTCON_PORTB_SEL0_B6_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL0_B7_SHIFT                 28\r\n#define PORTCON_PORTB_SEL0_B7_WIDTH                 4\r\n#define PORTCON_PORTB_SEL0_B7_MASK                  (((1U << PORTCON_PORTB_SEL0_B7_WIDTH) - 1U) << PORTCON_PORTB_SEL0_B7_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B7_VALUE_GPIOB7          0U\r\n#define PORTCON_PORTB_SEL0_B7_BITS_GPIOB7           (PORTCON_PORTB_SEL0_B7_VALUE_GPIOB7 << PORTCON_PORTB_SEL0_B7_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B7_VALUE_SPI0_SSN        1U\r\n#define PORTCON_PORTB_SEL0_B7_BITS_SPI0_SSN         (PORTCON_PORTB_SEL0_B7_VALUE_SPI0_SSN << PORTCON_PORTB_SEL0_B7_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B7_VALUE_UART0_TX        2U\r\n#define PORTCON_PORTB_SEL0_B7_BITS_UART0_TX         (PORTCON_PORTB_SEL0_B7_VALUE_UART0_TX << PORTCON_PORTB_SEL0_B7_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B7_VALUE_IIC0_SCL        3U\r\n#define PORTCON_PORTB_SEL0_B7_BITS_IIC0_SCL         (PORTCON_PORTB_SEL0_B7_VALUE_IIC0_SCL << PORTCON_PORTB_SEL0_B7_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B7_VALUE_PWMP1_BRAKE0    4U\r\n#define PORTCON_PORTB_SEL0_B7_BITS_PWMP1_BRAKE0     (PORTCON_PORTB_SEL0_B7_VALUE_PWMP1_BRAKE0 << PORTCON_PORTB_SEL0_B7_SHIFT)\r\n#define PORTCON_PORTB_SEL0_B7_VALUE_PWMP0_CH1       5U\r\n#define PORTCON_PORTB_SEL0_B7_BITS_PWMP0_CH1        (PORTCON_PORTB_SEL0_B7_VALUE_PWMP0_CH1 << PORTCON_PORTB_SEL0_B7_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL1_ADDR                     (PORTCON_BASE_ADDR + 0x000CU)\r\n#define PORTCON_PORTB_SEL1                          (*(volatile uint32_t *)PORTCON_PORTB_SEL1_ADDR)\r\n#define PORTCON_PORTB_SEL1_B8_SHIFT                 0\r\n#define PORTCON_PORTB_SEL1_B8_WIDTH                 4\r\n#define PORTCON_PORTB_SEL1_B8_MASK                  (((1U << PORTCON_PORTB_SEL1_B8_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B8_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B8_VALUE_GPIOB8          0U\r\n#define PORTCON_PORTB_SEL1_B8_BITS_GPIOB8           (PORTCON_PORTB_SEL1_B8_VALUE_GPIOB8 << PORTCON_PORTB_SEL1_B8_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B8_VALUE_SPI0_CLK        1U\r\n#define PORTCON_PORTB_SEL1_B8_BITS_SPI0_CLK         (PORTCON_PORTB_SEL1_B8_VALUE_SPI0_CLK << PORTCON_PORTB_SEL1_B8_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B8_VALUE_UART0_RX        2U\r\n#define PORTCON_PORTB_SEL1_B8_BITS_UART0_RX         (PORTCON_PORTB_SEL1_B8_VALUE_UART0_RX << PORTCON_PORTB_SEL1_B8_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B8_VALUE_IIC0_SDA        3U\r\n#define PORTCON_PORTB_SEL1_B8_BITS_IIC0_SDA         (PORTCON_PORTB_SEL1_B8_VALUE_IIC0_SDA << PORTCON_PORTB_SEL1_B8_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B8_VALUE_PWMB0_CH0       4U\r\n#define PORTCON_PORTB_SEL1_B8_BITS_PWMB0_CH0        (PORTCON_PORTB_SEL1_B8_VALUE_PWMB0_CH0 << PORTCON_PORTB_SEL1_B8_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B8_VALUE_PWMP1_BRAKE1    5U\r\n#define PORTCON_PORTB_SEL1_B8_BITS_PWMP1_BRAKE1     (PORTCON_PORTB_SEL1_B8_VALUE_PWMP1_BRAKE1 << PORTCON_PORTB_SEL1_B8_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B8_VALUE_PWMP0_CH2       6U\r\n#define PORTCON_PORTB_SEL1_B8_BITS_PWMP0_CH2        (PORTCON_PORTB_SEL1_B8_VALUE_PWMP0_CH2 << PORTCON_PORTB_SEL1_B8_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL1_B9_SHIFT                 4\r\n#define PORTCON_PORTB_SEL1_B9_WIDTH                 4\r\n#define PORTCON_PORTB_SEL1_B9_MASK                  (((1U << PORTCON_PORTB_SEL1_B9_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B9_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B9_VALUE_GPIOB9          0U\r\n#define PORTCON_PORTB_SEL1_B9_BITS_GPIOB9           (PORTCON_PORTB_SEL1_B9_VALUE_GPIOB9 << PORTCON_PORTB_SEL1_B9_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B9_VALUE_SPI0_MISO       1U\r\n#define PORTCON_PORTB_SEL1_B9_BITS_SPI0_MISO        (PORTCON_PORTB_SEL1_B9_VALUE_SPI0_MISO << PORTCON_PORTB_SEL1_B9_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B9_VALUE_UART0_CTS       2U\r\n#define PORTCON_PORTB_SEL1_B9_BITS_UART0_CTS        (PORTCON_PORTB_SEL1_B9_VALUE_UART0_CTS << PORTCON_PORTB_SEL1_B9_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B9_VALUE_PWMB0_CH1       3U\r\n#define PORTCON_PORTB_SEL1_B9_BITS_PWMB0_CH1        (PORTCON_PORTB_SEL1_B9_VALUE_PWMB0_CH1 << PORTCON_PORTB_SEL1_B9_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B9_VALUE_PWMP1_CH0       4U\r\n#define PORTCON_PORTB_SEL1_B9_BITS_PWMP1_CH0        (PORTCON_PORTB_SEL1_B9_VALUE_PWMP1_CH0 << PORTCON_PORTB_SEL1_B9_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_IN1     5U\r\n#define PORTCON_PORTB_SEL1_B9_BITS_TIMERP1_IN1      (PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_IN1 << PORTCON_PORTB_SEL1_B9_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_OUT_H   6U\r\n#define PORTCON_PORTB_SEL1_B9_BITS_TIMERP1_OUT_H    (PORTCON_PORTB_SEL1_B9_VALUE_TIMERP1_OUT_H << PORTCON_PORTB_SEL1_B9_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL1_B10_SHIFT                8\r\n#define PORTCON_PORTB_SEL1_B10_WIDTH                4\r\n#define PORTCON_PORTB_SEL1_B10_MASK                 (((1U << PORTCON_PORTB_SEL1_B10_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B10_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B10_VALUE_GPIOB10        0U\r\n#define PORTCON_PORTB_SEL1_B10_BITS_GPIOB10         (PORTCON_PORTB_SEL1_B10_VALUE_GPIOB10 << PORTCON_PORTB_SEL1_B10_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B10_VALUE_SPI0_MOSI      1U\r\n#define PORTCON_PORTB_SEL1_B10_BITS_SPI0_MOSI       (PORTCON_PORTB_SEL1_B10_VALUE_SPI0_MOSI << PORTCON_PORTB_SEL1_B10_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B10_VALUE_UART0_RTS      2U\r\n#define PORTCON_PORTB_SEL1_B10_BITS_UART0_RTS       (PORTCON_PORTB_SEL1_B10_VALUE_UART0_RTS << PORTCON_PORTB_SEL1_B10_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B10_VALUE_PWMB0_CH2      3U\r\n#define PORTCON_PORTB_SEL1_B10_BITS_PWMB0_CH2       (PORTCON_PORTB_SEL1_B10_VALUE_PWMB0_CH2 << PORTCON_PORTB_SEL1_B10_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B10_VALUE_PWMP1_CH1      4U\r\n#define PORTCON_PORTB_SEL1_B10_BITS_PWMP1_CH1       (PORTCON_PORTB_SEL1_B10_VALUE_PWMP1_CH1 << PORTCON_PORTB_SEL1_B10_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B10_VALUE_PWMP0_PLUS0    5U\r\n#define PORTCON_PORTB_SEL1_B10_BITS_PWMP0_PLUS0     (PORTCON_PORTB_SEL1_B10_VALUE_PWMP0_PLUS0 << PORTCON_PORTB_SEL1_B10_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_IN0    6U\r\n#define PORTCON_PORTB_SEL1_B10_BITS_TIMERP1_IN0     (PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_IN0 << PORTCON_PORTB_SEL1_B10_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_OUT_L  7U\r\n#define PORTCON_PORTB_SEL1_B10_BITS_TIMERP1_OUT_L   (PORTCON_PORTB_SEL1_B10_VALUE_TIMERP1_OUT_L << PORTCON_PORTB_SEL1_B10_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL1_B11_SHIFT                12\r\n#define PORTCON_PORTB_SEL1_B11_WIDTH                4\r\n#define PORTCON_PORTB_SEL1_B11_MASK                 (((1U << PORTCON_PORTB_SEL1_B11_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B11_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B11_VALUE_GPIOB11        0U\r\n#define PORTCON_PORTB_SEL1_B11_BITS_GPIOB11         (PORTCON_PORTB_SEL1_B11_VALUE_GPIOB11 << PORTCON_PORTB_SEL1_B11_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B11_VALUE_SWDIO          1U\r\n#define PORTCON_PORTB_SEL1_B11_BITS_SWDIO           (PORTCON_PORTB_SEL1_B11_VALUE_SWDIO << PORTCON_PORTB_SEL1_B11_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B11_VALUE_PWMP1_CH2      2U\r\n#define PORTCON_PORTB_SEL1_B11_BITS_PWMP1_CH2       (PORTCON_PORTB_SEL1_B11_VALUE_PWMP1_CH2 << PORTCON_PORTB_SEL1_B11_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B11_VALUE_PWMP0_BRAKE2   3U\r\n#define PORTCON_PORTB_SEL1_B11_BITS_PWMP0_BRAKE2    (PORTCON_PORTB_SEL1_B11_VALUE_PWMP0_BRAKE2 << PORTCON_PORTB_SEL1_B11_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL1_B12_SHIFT                16\r\n#define PORTCON_PORTB_SEL1_B12_WIDTH                4\r\n#define PORTCON_PORTB_SEL1_B12_MASK                 (((1U << PORTCON_PORTB_SEL1_B12_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B12_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B12_VALUE_GPIOB12        0U\r\n#define PORTCON_PORTB_SEL1_B12_BITS_GPIOB12         (PORTCON_PORTB_SEL1_B12_VALUE_GPIOB12 << PORTCON_PORTB_SEL1_B12_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B12_VALUE_UART1_TX       1U\r\n#define PORTCON_PORTB_SEL1_B12_BITS_UART1_TX        (PORTCON_PORTB_SEL1_B12_VALUE_UART1_TX << PORTCON_PORTB_SEL1_B12_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B12_VALUE_IIC1_SCL       2U\r\n#define PORTCON_PORTB_SEL1_B12_BITS_IIC1_SCL        (PORTCON_PORTB_SEL1_B12_VALUE_IIC1_SCL << PORTCON_PORTB_SEL1_B12_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B12_VALUE_PWMP1_CH0N     3U\r\n#define PORTCON_PORTB_SEL1_B12_BITS_PWMP1_CH0N      (PORTCON_PORTB_SEL1_B12_VALUE_PWMP1_CH0N << PORTCON_PORTB_SEL1_B12_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL1_B13_SHIFT                20\r\n#define PORTCON_PORTB_SEL1_B13_WIDTH                4\r\n#define PORTCON_PORTB_SEL1_B13_MASK                 (((1U << PORTCON_PORTB_SEL1_B13_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B13_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B13_VALUE_GPIOB13        0U\r\n#define PORTCON_PORTB_SEL1_B13_BITS_GPIOB13         (PORTCON_PORTB_SEL1_B13_VALUE_GPIOB13 << PORTCON_PORTB_SEL1_B13_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B13_VALUE_UART1_RX       1U\r\n#define PORTCON_PORTB_SEL1_B13_BITS_UART1_RX        (PORTCON_PORTB_SEL1_B13_VALUE_UART1_RX << PORTCON_PORTB_SEL1_B13_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B13_VALUE_IIC1_SDA       2U\r\n#define PORTCON_PORTB_SEL1_B13_BITS_IIC1_SDA        (PORTCON_PORTB_SEL1_B13_VALUE_IIC1_SDA << PORTCON_PORTB_SEL1_B13_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B13_VALUE_PWMP1_CH1N     3U\r\n#define PORTCON_PORTB_SEL1_B13_BITS_PWMP1_CH1N      (PORTCON_PORTB_SEL1_B13_VALUE_PWMP1_CH1N << PORTCON_PORTB_SEL1_B13_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL1_B14_SHIFT                24\r\n#define PORTCON_PORTB_SEL1_B14_WIDTH                4\r\n#define PORTCON_PORTB_SEL1_B14_MASK                 (((1U << PORTCON_PORTB_SEL1_B14_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B14_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B14_VALUE_GPIOB14        0U\r\n#define PORTCON_PORTB_SEL1_B14_BITS_GPIOB14         (PORTCON_PORTB_SEL1_B14_VALUE_GPIOB14 << PORTCON_PORTB_SEL1_B14_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B14_VALUE_SWCLK          1U\r\n#define PORTCON_PORTB_SEL1_B14_BITS_SWCLK           (PORTCON_PORTB_SEL1_B14_VALUE_SWCLK << PORTCON_PORTB_SEL1_B14_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B14_VALUE_UART2_TX       2U\r\n#define PORTCON_PORTB_SEL1_B14_BITS_UART2_TX        (PORTCON_PORTB_SEL1_B14_VALUE_UART2_TX << PORTCON_PORTB_SEL1_B14_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B14_VALUE_PWMP1_CH2N     3U\r\n#define PORTCON_PORTB_SEL1_B14_BITS_PWMP1_CH2N      (PORTCON_PORTB_SEL1_B14_VALUE_PWMP1_CH2N << PORTCON_PORTB_SEL1_B14_SHIFT)\r\n\r\n#define PORTCON_PORTB_SEL1_B15_SHIFT                28\r\n#define PORTCON_PORTB_SEL1_B15_WIDTH                4\r\n#define PORTCON_PORTB_SEL1_B15_MASK                 (((1U << PORTCON_PORTB_SEL1_B15_WIDTH) - 1U) << PORTCON_PORTB_SEL1_B15_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B15_VALUE_GPIOB15        0U\r\n#define PORTCON_PORTB_SEL1_B15_BITS_GPIOB15         (PORTCON_PORTB_SEL1_B15_VALUE_GPIOB15 << PORTCON_PORTB_SEL1_B15_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B15_VALUE_SPI1_SSN       1U\r\n#define PORTCON_PORTB_SEL1_B15_BITS_SPI1_SSN        (PORTCON_PORTB_SEL1_B15_VALUE_SPI1_SSN << PORTCON_PORTB_SEL1_B15_SHIFT)\r\n#define PORTCON_PORTB_SEL1_B15_VALUE_UART2_RX       2U\r\n#define PORTCON_PORTB_SEL1_B15_BITS_UART2_RX        (PORTCON_PORTB_SEL1_B15_VALUE_UART2_RX << PORTCON_PORTB_SEL1_B15_SHIFT)\r\n\r\n#define PORTCON_PORTC_SEL0_ADDR                     (PORTCON_BASE_ADDR + 0x0010U)\r\n#define PORTCON_PORTC_SEL0                          (*(volatile uint32_t *)PORTCON_PORTC_SEL0_ADDR)\r\n#define PORTCON_PORTC_SEL0_C0_SHIFT                 0\r\n#define PORTCON_PORTC_SEL0_C0_WIDTH                 4\r\n#define PORTCON_PORTC_SEL0_C0_MASK                  (((1U << PORTCON_PORTC_SEL0_C0_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C0_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C0_VALUE_GPIOC0          0U\r\n#define PORTCON_PORTC_SEL0_C0_BITS_GPIOC0           (PORTCON_PORTC_SEL0_C0_VALUE_GPIOC0 << PORTCON_PORTC_SEL0_C0_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C0_VALUE_SPI1_CLK        1U\r\n#define PORTCON_PORTC_SEL0_C0_BITS_SPI1_CLK         (PORTCON_PORTC_SEL0_C0_VALUE_SPI1_CLK << PORTCON_PORTC_SEL0_C0_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C0_VALUE_UART2_CTS       2U\r\n#define PORTCON_PORTC_SEL0_C0_BITS_UART2_CTS        (PORTCON_PORTC_SEL0_C0_VALUE_UART2_CTS << PORTCON_PORTC_SEL0_C0_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C0_VALUE_PWMB1_CH0       3U\r\n#define PORTCON_PORTC_SEL0_C0_BITS_PWMB1_CH0        (PORTCON_PORTC_SEL0_C0_VALUE_PWMB1_CH0 << PORTCON_PORTC_SEL0_C0_SHIFT)\r\n\r\n#define PORTCON_PORTC_SEL0_C1_SHIFT                 4\r\n#define PORTCON_PORTC_SEL0_C1_WIDTH                 4\r\n#define PORTCON_PORTC_SEL0_C1_MASK                  (((1U << PORTCON_PORTC_SEL0_C1_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C1_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C1_VALUE_GPIOC1          0U\r\n#define PORTCON_PORTC_SEL0_C1_BITS_GPIOC1           (PORTCON_PORTC_SEL0_C1_VALUE_GPIOC1 << PORTCON_PORTC_SEL0_C1_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C1_VALUE_SPI1_MISO       1U\r\n#define PORTCON_PORTC_SEL0_C1_BITS_SPI1_MISO        (PORTCON_PORTC_SEL0_C1_VALUE_SPI1_MISO << PORTCON_PORTC_SEL0_C1_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C1_VALUE_UART2_RTS       2U\r\n#define PORTCON_PORTC_SEL0_C1_BITS_UART2_RTS        (PORTCON_PORTC_SEL0_C1_VALUE_UART2_RTS << PORTCON_PORTC_SEL0_C1_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C1_VALUE_PWMB1_CH1       3U\r\n#define PORTCON_PORTC_SEL0_C1_BITS_PWMB1_CH1        (PORTCON_PORTC_SEL0_C1_VALUE_PWMB1_CH1 << PORTCON_PORTC_SEL0_C1_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_IN0     4U\r\n#define PORTCON_PORTC_SEL0_C1_BITS_TIMERP0_IN0      (PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_IN0 << PORTCON_PORTC_SEL0_C1_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_OUT_L   5U\r\n#define PORTCON_PORTC_SEL0_C1_BITS_TIMERP0_OUT_L    (PORTCON_PORTC_SEL0_C1_VALUE_TIMERP0_OUT_L << PORTCON_PORTC_SEL0_C1_SHIFT)\r\n\r\n#define PORTCON_PORTC_SEL0_C2_SHIFT                 8\r\n#define PORTCON_PORTC_SEL0_C2_WIDTH                 4\r\n#define PORTCON_PORTC_SEL0_C2_MASK                  (((1U << PORTCON_PORTC_SEL0_C2_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C2_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C2_VALUE_GPIOC2          0U\r\n#define PORTCON_PORTC_SEL0_C2_BITS_GPIOC2           (PORTCON_PORTC_SEL0_C2_VALUE_GPIOC2 << PORTCON_PORTC_SEL0_C2_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C2_VALUE_SPI1_MOSI       1U\r\n#define PORTCON_PORTC_SEL0_C2_BITS_SPI1_MOSI        (PORTCON_PORTC_SEL0_C2_VALUE_SPI1_MOSI << PORTCON_PORTC_SEL0_C2_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C2_VALUE_PWMB1_CH2       2U\r\n#define PORTCON_PORTC_SEL0_C2_BITS_PWMB1_CH2        (PORTCON_PORTC_SEL0_C2_VALUE_PWMB1_CH2 << PORTCON_PORTC_SEL0_C2_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C2_VALUE_PWMP1_BRAKE2    3U\r\n#define PORTCON_PORTC_SEL0_C2_BITS_PWMP1_BRAKE2     (PORTCON_PORTC_SEL0_C2_VALUE_PWMP1_BRAKE2 << PORTCON_PORTC_SEL0_C2_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_IN1     4U\r\n#define PORTCON_PORTC_SEL0_C2_BITS_TIMERP0_IN1      (PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_IN1 << PORTCON_PORTC_SEL0_C2_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_OUT_H   5U\r\n#define PORTCON_PORTC_SEL0_C2_BITS_TIMERP0_OUT_H    (PORTCON_PORTC_SEL0_C2_VALUE_TIMERP0_OUT_H << PORTCON_PORTC_SEL0_C2_SHIFT)\r\n\r\n#define PORTCON_PORTC_SEL0_C3_SHIFT                 12\r\n#define PORTCON_PORTC_SEL0_C3_WIDTH                 4\r\n#define PORTCON_PORTC_SEL0_C3_MASK                  (((1U << PORTCON_PORTC_SEL0_C3_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C3_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C3_VALUE_GPIOC3          0U\r\n#define PORTCON_PORTC_SEL0_C3_BITS_GPIOC3           (PORTCON_PORTC_SEL0_C3_VALUE_GPIOC3 << PORTCON_PORTC_SEL0_C3_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C3_VALUE_UART0_TX        1U\r\n#define PORTCON_PORTC_SEL0_C3_BITS_UART0_TX         (PORTCON_PORTC_SEL0_C3_VALUE_UART0_TX << PORTCON_PORTC_SEL0_C3_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C3_VALUE_IIC0_SCL        2U\r\n#define PORTCON_PORTC_SEL0_C3_BITS_IIC0_SCL         (PORTCON_PORTC_SEL0_C3_VALUE_IIC0_SCL << PORTCON_PORTC_SEL0_C3_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C3_VALUE_PWMP1_CH1N      3U\r\n#define PORTCON_PORTC_SEL0_C3_BITS_PWMP1_CH1N       (PORTCON_PORTC_SEL0_C3_VALUE_PWMP1_CH1N << PORTCON_PORTC_SEL0_C3_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C3_VALUE_TIMERP0_HALL0   4U\r\n#define PORTCON_PORTC_SEL0_C3_BITS_TIMERP0_HALL0    (PORTCON_PORTC_SEL0_C3_VALUE_TIMERP0_HALL0 << PORTCON_PORTC_SEL0_C3_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C3_VALUE_CMP2_VN         5U\r\n#define PORTCON_PORTC_SEL0_C3_BITS_CMP2_VN          (PORTCON_PORTC_SEL0_C3_VALUE_CMP2_VN << PORTCON_PORTC_SEL0_C3_SHIFT)\r\n\r\n#define PORTCON_PORTC_SEL0_C4_SHIFT                 16\r\n#define PORTCON_PORTC_SEL0_C4_WIDTH                 4\r\n#define PORTCON_PORTC_SEL0_C4_MASK                  (((1U << PORTCON_PORTC_SEL0_C4_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C4_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C4_VALUE_GPIOC4          0U\r\n#define PORTCON_PORTC_SEL0_C4_BITS_GPIOC4           (PORTCON_PORTC_SEL0_C4_VALUE_GPIOC4 << PORTCON_PORTC_SEL0_C4_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C4_VALUE_UART0_RX        1U\r\n#define PORTCON_PORTC_SEL0_C4_BITS_UART0_RX         (PORTCON_PORTC_SEL0_C4_VALUE_UART0_RX << PORTCON_PORTC_SEL0_C4_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C4_VALUE_IIC0_SDA        2U\r\n#define PORTCON_PORTC_SEL0_C4_BITS_IIC0_SDA         (PORTCON_PORTC_SEL0_C4_VALUE_IIC0_SDA << PORTCON_PORTC_SEL0_C4_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C4_VALUE_PWMP1_CH2N      3U\r\n#define PORTCON_PORTC_SEL0_C4_BITS_PWMP1_CH2N       (PORTCON_PORTC_SEL0_C4_VALUE_PWMP1_CH2N << PORTCON_PORTC_SEL0_C4_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C4_VALUE_TIMERP0_HALL1   4U\r\n#define PORTCON_PORTC_SEL0_C4_BITS_TIMERP0_HALL1    (PORTCON_PORTC_SEL0_C4_VALUE_TIMERP0_HALL1 << PORTCON_PORTC_SEL0_C4_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C4_VALUE_CMP2_VP         5U\r\n#define PORTCON_PORTC_SEL0_C4_BITS_CMP2_VP          (PORTCON_PORTC_SEL0_C4_VALUE_CMP2_VP << PORTCON_PORTC_SEL0_C4_SHIFT)\r\n\r\n#define PORTCON_PORTC_SEL0_C5_SHIFT                 20\r\n#define PORTCON_PORTC_SEL0_C5_WIDTH                 4\r\n#define PORTCON_PORTC_SEL0_C5_MASK                  (((1U << PORTCON_PORTC_SEL0_C5_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C5_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C5_VALUE_GPIOC5          0U\r\n#define PORTCON_PORTC_SEL0_C5_BITS_GPIOC5           (PORTCON_PORTC_SEL0_C5_VALUE_GPIOC5 << PORTCON_PORTC_SEL0_C5_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C5_VALUE_TIMERP0_HALL2   1U\r\n#define PORTCON_PORTC_SEL0_C5_BITS_TIMERP0_HALL2    (PORTCON_PORTC_SEL0_C5_VALUE_TIMERP0_HALL2 << PORTCON_PORTC_SEL0_C5_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C5_VALUE_TM              2U\r\n#define PORTCON_PORTC_SEL0_C5_BITS_TM               (PORTCON_PORTC_SEL0_C5_VALUE_TM << PORTCON_PORTC_SEL0_C5_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C5_VALUE_OPA1_VP         3U\r\n#define PORTCON_PORTC_SEL0_C5_BITS_OPA1_VP          (PORTCON_PORTC_SEL0_C5_VALUE_OPA1_VP << PORTCON_PORTC_SEL0_C5_SHIFT)\r\n\r\n#define PORTCON_PORTC_SEL0_C6_SHIFT                 24\r\n#define PORTCON_PORTC_SEL0_C6_WIDTH                 4\r\n#define PORTCON_PORTC_SEL0_C6_MASK                  (((1U << PORTCON_PORTC_SEL0_C6_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C6_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C6_VALUE_GPIOC6          0U\r\n#define PORTCON_PORTC_SEL0_C6_BITS_GPIOC6           (PORTCON_PORTC_SEL0_C6_VALUE_GPIOC6 << PORTCON_PORTC_SEL0_C6_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C6_VALUE_IIC1_SCL        1U\r\n#define PORTCON_PORTC_SEL0_C6_BITS_IIC1_SCL         (PORTCON_PORTC_SEL0_C6_VALUE_IIC1_SCL << PORTCON_PORTC_SEL0_C6_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C6_VALUE_PWMP1_CH1       2U\r\n#define PORTCON_PORTC_SEL0_C6_BITS_PWMP1_CH1        (PORTCON_PORTC_SEL0_C6_VALUE_PWMP1_CH1 << PORTCON_PORTC_SEL0_C6_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_IN1     3U\r\n#define PORTCON_PORTC_SEL0_C6_BITS_TIMERP1_IN1      (PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_IN1 << PORTCON_PORTC_SEL0_C6_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_OUT_H   4U\r\n#define PORTCON_PORTC_SEL0_C6_BITS_TIMERP1_OUT_H    (PORTCON_PORTC_SEL0_C6_VALUE_TIMERP1_OUT_H << PORTCON_PORTC_SEL0_C6_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C6_VALUE_OPA1_VN         5U\r\n#define PORTCON_PORTC_SEL0_C6_BITS_OPA1_VN          (PORTCON_PORTC_SEL0_C6_VALUE_OPA1_VN << PORTCON_PORTC_SEL0_C6_SHIFT)\r\n\r\n#define PORTCON_PORTC_SEL0_C7_SHIFT                 28\r\n#define PORTCON_PORTC_SEL0_C7_WIDTH                 4\r\n#define PORTCON_PORTC_SEL0_C7_MASK                  (((1U << PORTCON_PORTC_SEL0_C7_WIDTH) - 1U) << PORTCON_PORTC_SEL0_C7_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C7_VALUE_GPIOC7          0U\r\n#define PORTCON_PORTC_SEL0_C7_BITS_GPIOC7           (PORTCON_PORTC_SEL0_C7_VALUE_GPIOC7 << PORTCON_PORTC_SEL0_C7_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C7_VALUE_IIC1_SDA        1U\r\n#define PORTCON_PORTC_SEL0_C7_BITS_IIC1_SDA         (PORTCON_PORTC_SEL0_C7_VALUE_IIC1_SDA << PORTCON_PORTC_SEL0_C7_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C7_VALUE_PWMP1_CH2       2U\r\n#define PORTCON_PORTC_SEL0_C7_BITS_PWMP1_CH2        (PORTCON_PORTC_SEL0_C7_VALUE_PWMP1_CH2 << PORTCON_PORTC_SEL0_C7_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_IN0     3U\r\n#define PORTCON_PORTC_SEL0_C7_BITS_TIMERP1_IN0      (PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_IN0 << PORTCON_PORTC_SEL0_C7_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_OUT_L   4U\r\n#define PORTCON_PORTC_SEL0_C7_BITS_TIMERP1_OUT_L    (PORTCON_PORTC_SEL0_C7_VALUE_TIMERP1_OUT_L << PORTCON_PORTC_SEL0_C7_SHIFT)\r\n#define PORTCON_PORTC_SEL0_C7_VALUE_OPA1_OUT        5U\r\n#define PORTCON_PORTC_SEL0_C7_BITS_OPA1_OUT         (PORTCON_PORTC_SEL0_C7_VALUE_OPA1_OUT << PORTCON_PORTC_SEL0_C7_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_ADDR                       (PORTCON_BASE_ADDR + 0x0100U)\r\n#define PORTCON_PORTA_IE                            (*(volatile uint32_t *)PORTCON_PORTA_IE_ADDR)\r\n#define PORTCON_PORTA_IE_A0_SHIFT                   0\r\n#define PORTCON_PORTA_IE_A0_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A0_MASK                    (((1U << PORTCON_PORTA_IE_A0_WIDTH) - 1U) << PORTCON_PORTA_IE_A0_SHIFT)\r\n#define PORTCON_PORTA_IE_A0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A0_BITS_DISABLE            (PORTCON_PORTA_IE_A0_VALUE_DISABLE << PORTCON_PORTA_IE_A0_SHIFT)\r\n#define PORTCON_PORTA_IE_A0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A0_BITS_ENABLE             (PORTCON_PORTA_IE_A0_VALUE_ENABLE << PORTCON_PORTA_IE_A0_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A1_SHIFT                   1\r\n#define PORTCON_PORTA_IE_A1_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A1_MASK                    (((1U << PORTCON_PORTA_IE_A1_WIDTH) - 1U) << PORTCON_PORTA_IE_A1_SHIFT)\r\n#define PORTCON_PORTA_IE_A1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A1_BITS_DISABLE            (PORTCON_PORTA_IE_A1_VALUE_DISABLE << PORTCON_PORTA_IE_A1_SHIFT)\r\n#define PORTCON_PORTA_IE_A1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A1_BITS_ENABLE             (PORTCON_PORTA_IE_A1_VALUE_ENABLE << PORTCON_PORTA_IE_A1_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A2_SHIFT                   2\r\n#define PORTCON_PORTA_IE_A2_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A2_MASK                    (((1U << PORTCON_PORTA_IE_A2_WIDTH) - 1U) << PORTCON_PORTA_IE_A2_SHIFT)\r\n#define PORTCON_PORTA_IE_A2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A2_BITS_DISABLE            (PORTCON_PORTA_IE_A2_VALUE_DISABLE << PORTCON_PORTA_IE_A2_SHIFT)\r\n#define PORTCON_PORTA_IE_A2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A2_BITS_ENABLE             (PORTCON_PORTA_IE_A2_VALUE_ENABLE << PORTCON_PORTA_IE_A2_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A3_SHIFT                   3\r\n#define PORTCON_PORTA_IE_A3_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A3_MASK                    (((1U << PORTCON_PORTA_IE_A3_WIDTH) - 1U) << PORTCON_PORTA_IE_A3_SHIFT)\r\n#define PORTCON_PORTA_IE_A3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A3_BITS_DISABLE            (PORTCON_PORTA_IE_A3_VALUE_DISABLE << PORTCON_PORTA_IE_A3_SHIFT)\r\n#define PORTCON_PORTA_IE_A3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A3_BITS_ENABLE             (PORTCON_PORTA_IE_A3_VALUE_ENABLE << PORTCON_PORTA_IE_A3_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A4_SHIFT                   4\r\n#define PORTCON_PORTA_IE_A4_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A4_MASK                    (((1U << PORTCON_PORTA_IE_A4_WIDTH) - 1U) << PORTCON_PORTA_IE_A4_SHIFT)\r\n#define PORTCON_PORTA_IE_A4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A4_BITS_DISABLE            (PORTCON_PORTA_IE_A4_VALUE_DISABLE << PORTCON_PORTA_IE_A4_SHIFT)\r\n#define PORTCON_PORTA_IE_A4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A4_BITS_ENABLE             (PORTCON_PORTA_IE_A4_VALUE_ENABLE << PORTCON_PORTA_IE_A4_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A5_SHIFT                   5\r\n#define PORTCON_PORTA_IE_A5_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A5_MASK                    (((1U << PORTCON_PORTA_IE_A5_WIDTH) - 1U) << PORTCON_PORTA_IE_A5_SHIFT)\r\n#define PORTCON_PORTA_IE_A5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A5_BITS_DISABLE            (PORTCON_PORTA_IE_A5_VALUE_DISABLE << PORTCON_PORTA_IE_A5_SHIFT)\r\n#define PORTCON_PORTA_IE_A5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A5_BITS_ENABLE             (PORTCON_PORTA_IE_A5_VALUE_ENABLE << PORTCON_PORTA_IE_A5_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A6_SHIFT                   6\r\n#define PORTCON_PORTA_IE_A6_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A6_MASK                    (((1U << PORTCON_PORTA_IE_A6_WIDTH) - 1U) << PORTCON_PORTA_IE_A6_SHIFT)\r\n#define PORTCON_PORTA_IE_A6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A6_BITS_DISABLE            (PORTCON_PORTA_IE_A6_VALUE_DISABLE << PORTCON_PORTA_IE_A6_SHIFT)\r\n#define PORTCON_PORTA_IE_A6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A6_BITS_ENABLE             (PORTCON_PORTA_IE_A6_VALUE_ENABLE << PORTCON_PORTA_IE_A6_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A7_SHIFT                   7\r\n#define PORTCON_PORTA_IE_A7_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A7_MASK                    (((1U << PORTCON_PORTA_IE_A7_WIDTH) - 1U) << PORTCON_PORTA_IE_A7_SHIFT)\r\n#define PORTCON_PORTA_IE_A7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A7_BITS_DISABLE            (PORTCON_PORTA_IE_A7_VALUE_DISABLE << PORTCON_PORTA_IE_A7_SHIFT)\r\n#define PORTCON_PORTA_IE_A7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A7_BITS_ENABLE             (PORTCON_PORTA_IE_A7_VALUE_ENABLE << PORTCON_PORTA_IE_A7_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A8_SHIFT                   8\r\n#define PORTCON_PORTA_IE_A8_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A8_MASK                    (((1U << PORTCON_PORTA_IE_A8_WIDTH) - 1U) << PORTCON_PORTA_IE_A8_SHIFT)\r\n#define PORTCON_PORTA_IE_A8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A8_BITS_DISABLE            (PORTCON_PORTA_IE_A8_VALUE_DISABLE << PORTCON_PORTA_IE_A8_SHIFT)\r\n#define PORTCON_PORTA_IE_A8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A8_BITS_ENABLE             (PORTCON_PORTA_IE_A8_VALUE_ENABLE << PORTCON_PORTA_IE_A8_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A9_SHIFT                   9\r\n#define PORTCON_PORTA_IE_A9_WIDTH                   1\r\n#define PORTCON_PORTA_IE_A9_MASK                    (((1U << PORTCON_PORTA_IE_A9_WIDTH) - 1U) << PORTCON_PORTA_IE_A9_SHIFT)\r\n#define PORTCON_PORTA_IE_A9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_IE_A9_BITS_DISABLE            (PORTCON_PORTA_IE_A9_VALUE_DISABLE << PORTCON_PORTA_IE_A9_SHIFT)\r\n#define PORTCON_PORTA_IE_A9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_IE_A9_BITS_ENABLE             (PORTCON_PORTA_IE_A9_VALUE_ENABLE << PORTCON_PORTA_IE_A9_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A10_SHIFT                  10\r\n#define PORTCON_PORTA_IE_A10_WIDTH                  1\r\n#define PORTCON_PORTA_IE_A10_MASK                   (((1U << PORTCON_PORTA_IE_A10_WIDTH) - 1U) << PORTCON_PORTA_IE_A10_SHIFT)\r\n#define PORTCON_PORTA_IE_A10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_IE_A10_BITS_DISABLE           (PORTCON_PORTA_IE_A10_VALUE_DISABLE << PORTCON_PORTA_IE_A10_SHIFT)\r\n#define PORTCON_PORTA_IE_A10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_IE_A10_BITS_ENABLE            (PORTCON_PORTA_IE_A10_VALUE_ENABLE << PORTCON_PORTA_IE_A10_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A11_SHIFT                  11\r\n#define PORTCON_PORTA_IE_A11_WIDTH                  1\r\n#define PORTCON_PORTA_IE_A11_MASK                   (((1U << PORTCON_PORTA_IE_A11_WIDTH) - 1U) << PORTCON_PORTA_IE_A11_SHIFT)\r\n#define PORTCON_PORTA_IE_A11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_IE_A11_BITS_DISABLE           (PORTCON_PORTA_IE_A11_VALUE_DISABLE << PORTCON_PORTA_IE_A11_SHIFT)\r\n#define PORTCON_PORTA_IE_A11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_IE_A11_BITS_ENABLE            (PORTCON_PORTA_IE_A11_VALUE_ENABLE << PORTCON_PORTA_IE_A11_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A12_SHIFT                  12\r\n#define PORTCON_PORTA_IE_A12_WIDTH                  1\r\n#define PORTCON_PORTA_IE_A12_MASK                   (((1U << PORTCON_PORTA_IE_A12_WIDTH) - 1U) << PORTCON_PORTA_IE_A12_SHIFT)\r\n#define PORTCON_PORTA_IE_A12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_IE_A12_BITS_DISABLE           (PORTCON_PORTA_IE_A12_VALUE_DISABLE << PORTCON_PORTA_IE_A12_SHIFT)\r\n#define PORTCON_PORTA_IE_A12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_IE_A12_BITS_ENABLE            (PORTCON_PORTA_IE_A12_VALUE_ENABLE << PORTCON_PORTA_IE_A12_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A13_SHIFT                  13\r\n#define PORTCON_PORTA_IE_A13_WIDTH                  1\r\n#define PORTCON_PORTA_IE_A13_MASK                   (((1U << PORTCON_PORTA_IE_A13_WIDTH) - 1U) << PORTCON_PORTA_IE_A13_SHIFT)\r\n#define PORTCON_PORTA_IE_A13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_IE_A13_BITS_DISABLE           (PORTCON_PORTA_IE_A13_VALUE_DISABLE << PORTCON_PORTA_IE_A13_SHIFT)\r\n#define PORTCON_PORTA_IE_A13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_IE_A13_BITS_ENABLE            (PORTCON_PORTA_IE_A13_VALUE_ENABLE << PORTCON_PORTA_IE_A13_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A14_SHIFT                  14\r\n#define PORTCON_PORTA_IE_A14_WIDTH                  1\r\n#define PORTCON_PORTA_IE_A14_MASK                   (((1U << PORTCON_PORTA_IE_A14_WIDTH) - 1U) << PORTCON_PORTA_IE_A14_SHIFT)\r\n#define PORTCON_PORTA_IE_A14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_IE_A14_BITS_DISABLE           (PORTCON_PORTA_IE_A14_VALUE_DISABLE << PORTCON_PORTA_IE_A14_SHIFT)\r\n#define PORTCON_PORTA_IE_A14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_IE_A14_BITS_ENABLE            (PORTCON_PORTA_IE_A14_VALUE_ENABLE << PORTCON_PORTA_IE_A14_SHIFT)\r\n\r\n#define PORTCON_PORTA_IE_A15_SHIFT                  15\r\n#define PORTCON_PORTA_IE_A15_WIDTH                  1\r\n#define PORTCON_PORTA_IE_A15_MASK                   (((1U << PORTCON_PORTA_IE_A15_WIDTH) - 1U) << PORTCON_PORTA_IE_A15_SHIFT)\r\n#define PORTCON_PORTA_IE_A15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_IE_A15_BITS_DISABLE           (PORTCON_PORTA_IE_A15_VALUE_DISABLE << PORTCON_PORTA_IE_A15_SHIFT)\r\n#define PORTCON_PORTA_IE_A15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_IE_A15_BITS_ENABLE            (PORTCON_PORTA_IE_A15_VALUE_ENABLE << PORTCON_PORTA_IE_A15_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_ADDR                       (PORTCON_BASE_ADDR + 0x0104U)\r\n#define PORTCON_PORTB_IE                            (*(volatile uint32_t *)PORTCON_PORTB_IE_ADDR)\r\n#define PORTCON_PORTB_IE_B0_SHIFT                   0\r\n#define PORTCON_PORTB_IE_B0_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B0_MASK                    (((1U << PORTCON_PORTB_IE_B0_WIDTH) - 1U) << PORTCON_PORTB_IE_B0_SHIFT)\r\n#define PORTCON_PORTB_IE_B0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B0_BITS_DISABLE            (PORTCON_PORTB_IE_B0_VALUE_DISABLE << PORTCON_PORTB_IE_B0_SHIFT)\r\n#define PORTCON_PORTB_IE_B0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B0_BITS_ENABLE             (PORTCON_PORTB_IE_B0_VALUE_ENABLE << PORTCON_PORTB_IE_B0_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B1_SHIFT                   1\r\n#define PORTCON_PORTB_IE_B1_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B1_MASK                    (((1U << PORTCON_PORTB_IE_B1_WIDTH) - 1U) << PORTCON_PORTB_IE_B1_SHIFT)\r\n#define PORTCON_PORTB_IE_B1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B1_BITS_DISABLE            (PORTCON_PORTB_IE_B1_VALUE_DISABLE << PORTCON_PORTB_IE_B1_SHIFT)\r\n#define PORTCON_PORTB_IE_B1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B1_BITS_ENABLE             (PORTCON_PORTB_IE_B1_VALUE_ENABLE << PORTCON_PORTB_IE_B1_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B2_SHIFT                   2\r\n#define PORTCON_PORTB_IE_B2_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B2_MASK                    (((1U << PORTCON_PORTB_IE_B2_WIDTH) - 1U) << PORTCON_PORTB_IE_B2_SHIFT)\r\n#define PORTCON_PORTB_IE_B2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B2_BITS_DISABLE            (PORTCON_PORTB_IE_B2_VALUE_DISABLE << PORTCON_PORTB_IE_B2_SHIFT)\r\n#define PORTCON_PORTB_IE_B2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B2_BITS_ENABLE             (PORTCON_PORTB_IE_B2_VALUE_ENABLE << PORTCON_PORTB_IE_B2_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B3_SHIFT                   3\r\n#define PORTCON_PORTB_IE_B3_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B3_MASK                    (((1U << PORTCON_PORTB_IE_B3_WIDTH) - 1U) << PORTCON_PORTB_IE_B3_SHIFT)\r\n#define PORTCON_PORTB_IE_B3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B3_BITS_DISABLE            (PORTCON_PORTB_IE_B3_VALUE_DISABLE << PORTCON_PORTB_IE_B3_SHIFT)\r\n#define PORTCON_PORTB_IE_B3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B3_BITS_ENABLE             (PORTCON_PORTB_IE_B3_VALUE_ENABLE << PORTCON_PORTB_IE_B3_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B4_SHIFT                   4\r\n#define PORTCON_PORTB_IE_B4_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B4_MASK                    (((1U << PORTCON_PORTB_IE_B4_WIDTH) - 1U) << PORTCON_PORTB_IE_B4_SHIFT)\r\n#define PORTCON_PORTB_IE_B4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B4_BITS_DISABLE            (PORTCON_PORTB_IE_B4_VALUE_DISABLE << PORTCON_PORTB_IE_B4_SHIFT)\r\n#define PORTCON_PORTB_IE_B4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B4_BITS_ENABLE             (PORTCON_PORTB_IE_B4_VALUE_ENABLE << PORTCON_PORTB_IE_B4_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B5_SHIFT                   5\r\n#define PORTCON_PORTB_IE_B5_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B5_MASK                    (((1U << PORTCON_PORTB_IE_B5_WIDTH) - 1U) << PORTCON_PORTB_IE_B5_SHIFT)\r\n#define PORTCON_PORTB_IE_B5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B5_BITS_DISABLE            (PORTCON_PORTB_IE_B5_VALUE_DISABLE << PORTCON_PORTB_IE_B5_SHIFT)\r\n#define PORTCON_PORTB_IE_B5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B5_BITS_ENABLE             (PORTCON_PORTB_IE_B5_VALUE_ENABLE << PORTCON_PORTB_IE_B5_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B6_SHIFT                   6\r\n#define PORTCON_PORTB_IE_B6_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B6_MASK                    (((1U << PORTCON_PORTB_IE_B6_WIDTH) - 1U) << PORTCON_PORTB_IE_B6_SHIFT)\r\n#define PORTCON_PORTB_IE_B6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B6_BITS_DISABLE            (PORTCON_PORTB_IE_B6_VALUE_DISABLE << PORTCON_PORTB_IE_B6_SHIFT)\r\n#define PORTCON_PORTB_IE_B6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B6_BITS_ENABLE             (PORTCON_PORTB_IE_B6_VALUE_ENABLE << PORTCON_PORTB_IE_B6_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B7_SHIFT                   7\r\n#define PORTCON_PORTB_IE_B7_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B7_MASK                    (((1U << PORTCON_PORTB_IE_B7_WIDTH) - 1U) << PORTCON_PORTB_IE_B7_SHIFT)\r\n#define PORTCON_PORTB_IE_B7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B7_BITS_DISABLE            (PORTCON_PORTB_IE_B7_VALUE_DISABLE << PORTCON_PORTB_IE_B7_SHIFT)\r\n#define PORTCON_PORTB_IE_B7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B7_BITS_ENABLE             (PORTCON_PORTB_IE_B7_VALUE_ENABLE << PORTCON_PORTB_IE_B7_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B8_SHIFT                   8\r\n#define PORTCON_PORTB_IE_B8_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B8_MASK                    (((1U << PORTCON_PORTB_IE_B8_WIDTH) - 1U) << PORTCON_PORTB_IE_B8_SHIFT)\r\n#define PORTCON_PORTB_IE_B8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B8_BITS_DISABLE            (PORTCON_PORTB_IE_B8_VALUE_DISABLE << PORTCON_PORTB_IE_B8_SHIFT)\r\n#define PORTCON_PORTB_IE_B8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B8_BITS_ENABLE             (PORTCON_PORTB_IE_B8_VALUE_ENABLE << PORTCON_PORTB_IE_B8_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B9_SHIFT                   9\r\n#define PORTCON_PORTB_IE_B9_WIDTH                   1\r\n#define PORTCON_PORTB_IE_B9_MASK                    (((1U << PORTCON_PORTB_IE_B9_WIDTH) - 1U) << PORTCON_PORTB_IE_B9_SHIFT)\r\n#define PORTCON_PORTB_IE_B9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_IE_B9_BITS_DISABLE            (PORTCON_PORTB_IE_B9_VALUE_DISABLE << PORTCON_PORTB_IE_B9_SHIFT)\r\n#define PORTCON_PORTB_IE_B9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_IE_B9_BITS_ENABLE             (PORTCON_PORTB_IE_B9_VALUE_ENABLE << PORTCON_PORTB_IE_B9_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B10_SHIFT                  10\r\n#define PORTCON_PORTB_IE_B10_WIDTH                  1\r\n#define PORTCON_PORTB_IE_B10_MASK                   (((1U << PORTCON_PORTB_IE_B10_WIDTH) - 1U) << PORTCON_PORTB_IE_B10_SHIFT)\r\n#define PORTCON_PORTB_IE_B10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_IE_B10_BITS_DISABLE           (PORTCON_PORTB_IE_B10_VALUE_DISABLE << PORTCON_PORTB_IE_B10_SHIFT)\r\n#define PORTCON_PORTB_IE_B10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_IE_B10_BITS_ENABLE            (PORTCON_PORTB_IE_B10_VALUE_ENABLE << PORTCON_PORTB_IE_B10_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B11_SHIFT                  11\r\n#define PORTCON_PORTB_IE_B11_WIDTH                  1\r\n#define PORTCON_PORTB_IE_B11_MASK                   (((1U << PORTCON_PORTB_IE_B11_WIDTH) - 1U) << PORTCON_PORTB_IE_B11_SHIFT)\r\n#define PORTCON_PORTB_IE_B11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_IE_B11_BITS_DISABLE           (PORTCON_PORTB_IE_B11_VALUE_DISABLE << PORTCON_PORTB_IE_B11_SHIFT)\r\n#define PORTCON_PORTB_IE_B11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_IE_B11_BITS_ENABLE            (PORTCON_PORTB_IE_B11_VALUE_ENABLE << PORTCON_PORTB_IE_B11_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B12_SHIFT                  12\r\n#define PORTCON_PORTB_IE_B12_WIDTH                  1\r\n#define PORTCON_PORTB_IE_B12_MASK                   (((1U << PORTCON_PORTB_IE_B12_WIDTH) - 1U) << PORTCON_PORTB_IE_B12_SHIFT)\r\n#define PORTCON_PORTB_IE_B12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_IE_B12_BITS_DISABLE           (PORTCON_PORTB_IE_B12_VALUE_DISABLE << PORTCON_PORTB_IE_B12_SHIFT)\r\n#define PORTCON_PORTB_IE_B12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_IE_B12_BITS_ENABLE            (PORTCON_PORTB_IE_B12_VALUE_ENABLE << PORTCON_PORTB_IE_B12_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B13_SHIFT                  13\r\n#define PORTCON_PORTB_IE_B13_WIDTH                  1\r\n#define PORTCON_PORTB_IE_B13_MASK                   (((1U << PORTCON_PORTB_IE_B13_WIDTH) - 1U) << PORTCON_PORTB_IE_B13_SHIFT)\r\n#define PORTCON_PORTB_IE_B13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_IE_B13_BITS_DISABLE           (PORTCON_PORTB_IE_B13_VALUE_DISABLE << PORTCON_PORTB_IE_B13_SHIFT)\r\n#define PORTCON_PORTB_IE_B13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_IE_B13_BITS_ENABLE            (PORTCON_PORTB_IE_B13_VALUE_ENABLE << PORTCON_PORTB_IE_B13_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B14_SHIFT                  14\r\n#define PORTCON_PORTB_IE_B14_WIDTH                  1\r\n#define PORTCON_PORTB_IE_B14_MASK                   (((1U << PORTCON_PORTB_IE_B14_WIDTH) - 1U) << PORTCON_PORTB_IE_B14_SHIFT)\r\n#define PORTCON_PORTB_IE_B14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_IE_B14_BITS_DISABLE           (PORTCON_PORTB_IE_B14_VALUE_DISABLE << PORTCON_PORTB_IE_B14_SHIFT)\r\n#define PORTCON_PORTB_IE_B14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_IE_B14_BITS_ENABLE            (PORTCON_PORTB_IE_B14_VALUE_ENABLE << PORTCON_PORTB_IE_B14_SHIFT)\r\n\r\n#define PORTCON_PORTB_IE_B15_SHIFT                  15\r\n#define PORTCON_PORTB_IE_B15_WIDTH                  1\r\n#define PORTCON_PORTB_IE_B15_MASK                   (((1U << PORTCON_PORTB_IE_B15_WIDTH) - 1U) << PORTCON_PORTB_IE_B15_SHIFT)\r\n#define PORTCON_PORTB_IE_B15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_IE_B15_BITS_DISABLE           (PORTCON_PORTB_IE_B15_VALUE_DISABLE << PORTCON_PORTB_IE_B15_SHIFT)\r\n#define PORTCON_PORTB_IE_B15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_IE_B15_BITS_ENABLE            (PORTCON_PORTB_IE_B15_VALUE_ENABLE << PORTCON_PORTB_IE_B15_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_ADDR                       (PORTCON_BASE_ADDR + 0x0108U)\r\n#define PORTCON_PORTC_IE                            (*(volatile uint32_t *)PORTCON_PORTC_IE_ADDR)\r\n#define PORTCON_PORTC_IE_C0_SHIFT                   0\r\n#define PORTCON_PORTC_IE_C0_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C0_MASK                    (((1U << PORTCON_PORTC_IE_C0_WIDTH) - 1U) << PORTCON_PORTC_IE_C0_SHIFT)\r\n#define PORTCON_PORTC_IE_C0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C0_BITS_DISABLE            (PORTCON_PORTC_IE_C0_VALUE_DISABLE << PORTCON_PORTC_IE_C0_SHIFT)\r\n#define PORTCON_PORTC_IE_C0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C0_BITS_ENABLE             (PORTCON_PORTC_IE_C0_VALUE_ENABLE << PORTCON_PORTC_IE_C0_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C1_SHIFT                   1\r\n#define PORTCON_PORTC_IE_C1_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C1_MASK                    (((1U << PORTCON_PORTC_IE_C1_WIDTH) - 1U) << PORTCON_PORTC_IE_C1_SHIFT)\r\n#define PORTCON_PORTC_IE_C1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C1_BITS_DISABLE            (PORTCON_PORTC_IE_C1_VALUE_DISABLE << PORTCON_PORTC_IE_C1_SHIFT)\r\n#define PORTCON_PORTC_IE_C1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C1_BITS_ENABLE             (PORTCON_PORTC_IE_C1_VALUE_ENABLE << PORTCON_PORTC_IE_C1_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C2_SHIFT                   2\r\n#define PORTCON_PORTC_IE_C2_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C2_MASK                    (((1U << PORTCON_PORTC_IE_C2_WIDTH) - 1U) << PORTCON_PORTC_IE_C2_SHIFT)\r\n#define PORTCON_PORTC_IE_C2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C2_BITS_DISABLE            (PORTCON_PORTC_IE_C2_VALUE_DISABLE << PORTCON_PORTC_IE_C2_SHIFT)\r\n#define PORTCON_PORTC_IE_C2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C2_BITS_ENABLE             (PORTCON_PORTC_IE_C2_VALUE_ENABLE << PORTCON_PORTC_IE_C2_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C3_SHIFT                   3\r\n#define PORTCON_PORTC_IE_C3_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C3_MASK                    (((1U << PORTCON_PORTC_IE_C3_WIDTH) - 1U) << PORTCON_PORTC_IE_C3_SHIFT)\r\n#define PORTCON_PORTC_IE_C3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C3_BITS_DISABLE            (PORTCON_PORTC_IE_C3_VALUE_DISABLE << PORTCON_PORTC_IE_C3_SHIFT)\r\n#define PORTCON_PORTC_IE_C3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C3_BITS_ENABLE             (PORTCON_PORTC_IE_C3_VALUE_ENABLE << PORTCON_PORTC_IE_C3_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C4_SHIFT                   4\r\n#define PORTCON_PORTC_IE_C4_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C4_MASK                    (((1U << PORTCON_PORTC_IE_C4_WIDTH) - 1U) << PORTCON_PORTC_IE_C4_SHIFT)\r\n#define PORTCON_PORTC_IE_C4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C4_BITS_DISABLE            (PORTCON_PORTC_IE_C4_VALUE_DISABLE << PORTCON_PORTC_IE_C4_SHIFT)\r\n#define PORTCON_PORTC_IE_C4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C4_BITS_ENABLE             (PORTCON_PORTC_IE_C4_VALUE_ENABLE << PORTCON_PORTC_IE_C4_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C5_SHIFT                   5\r\n#define PORTCON_PORTC_IE_C5_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C5_MASK                    (((1U << PORTCON_PORTC_IE_C5_WIDTH) - 1U) << PORTCON_PORTC_IE_C5_SHIFT)\r\n#define PORTCON_PORTC_IE_C5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C5_BITS_DISABLE            (PORTCON_PORTC_IE_C5_VALUE_DISABLE << PORTCON_PORTC_IE_C5_SHIFT)\r\n#define PORTCON_PORTC_IE_C5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C5_BITS_ENABLE             (PORTCON_PORTC_IE_C5_VALUE_ENABLE << PORTCON_PORTC_IE_C5_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C6_SHIFT                   6\r\n#define PORTCON_PORTC_IE_C6_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C6_MASK                    (((1U << PORTCON_PORTC_IE_C6_WIDTH) - 1U) << PORTCON_PORTC_IE_C6_SHIFT)\r\n#define PORTCON_PORTC_IE_C6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C6_BITS_DISABLE            (PORTCON_PORTC_IE_C6_VALUE_DISABLE << PORTCON_PORTC_IE_C6_SHIFT)\r\n#define PORTCON_PORTC_IE_C6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C6_BITS_ENABLE             (PORTCON_PORTC_IE_C6_VALUE_ENABLE << PORTCON_PORTC_IE_C6_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C7_SHIFT                   7\r\n#define PORTCON_PORTC_IE_C7_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C7_MASK                    (((1U << PORTCON_PORTC_IE_C7_WIDTH) - 1U) << PORTCON_PORTC_IE_C7_SHIFT)\r\n#define PORTCON_PORTC_IE_C7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C7_BITS_DISABLE            (PORTCON_PORTC_IE_C7_VALUE_DISABLE << PORTCON_PORTC_IE_C7_SHIFT)\r\n#define PORTCON_PORTC_IE_C7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C7_BITS_ENABLE             (PORTCON_PORTC_IE_C7_VALUE_ENABLE << PORTCON_PORTC_IE_C7_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C8_SHIFT                   8\r\n#define PORTCON_PORTC_IE_C8_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C8_MASK                    (((1U << PORTCON_PORTC_IE_C8_WIDTH) - 1U) << PORTCON_PORTC_IE_C8_SHIFT)\r\n#define PORTCON_PORTC_IE_C8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C8_BITS_DISABLE            (PORTCON_PORTC_IE_C8_VALUE_DISABLE << PORTCON_PORTC_IE_C8_SHIFT)\r\n#define PORTCON_PORTC_IE_C8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C8_BITS_ENABLE             (PORTCON_PORTC_IE_C8_VALUE_ENABLE << PORTCON_PORTC_IE_C8_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C9_SHIFT                   9\r\n#define PORTCON_PORTC_IE_C9_WIDTH                   1\r\n#define PORTCON_PORTC_IE_C9_MASK                    (((1U << PORTCON_PORTC_IE_C9_WIDTH) - 1U) << PORTCON_PORTC_IE_C9_SHIFT)\r\n#define PORTCON_PORTC_IE_C9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_IE_C9_BITS_DISABLE            (PORTCON_PORTC_IE_C9_VALUE_DISABLE << PORTCON_PORTC_IE_C9_SHIFT)\r\n#define PORTCON_PORTC_IE_C9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_IE_C9_BITS_ENABLE             (PORTCON_PORTC_IE_C9_VALUE_ENABLE << PORTCON_PORTC_IE_C9_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C10_SHIFT                  10\r\n#define PORTCON_PORTC_IE_C10_WIDTH                  1\r\n#define PORTCON_PORTC_IE_C10_MASK                   (((1U << PORTCON_PORTC_IE_C10_WIDTH) - 1U) << PORTCON_PORTC_IE_C10_SHIFT)\r\n#define PORTCON_PORTC_IE_C10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_IE_C10_BITS_DISABLE           (PORTCON_PORTC_IE_C10_VALUE_DISABLE << PORTCON_PORTC_IE_C10_SHIFT)\r\n#define PORTCON_PORTC_IE_C10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_IE_C10_BITS_ENABLE            (PORTCON_PORTC_IE_C10_VALUE_ENABLE << PORTCON_PORTC_IE_C10_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C11_SHIFT                  11\r\n#define PORTCON_PORTC_IE_C11_WIDTH                  1\r\n#define PORTCON_PORTC_IE_C11_MASK                   (((1U << PORTCON_PORTC_IE_C11_WIDTH) - 1U) << PORTCON_PORTC_IE_C11_SHIFT)\r\n#define PORTCON_PORTC_IE_C11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_IE_C11_BITS_DISABLE           (PORTCON_PORTC_IE_C11_VALUE_DISABLE << PORTCON_PORTC_IE_C11_SHIFT)\r\n#define PORTCON_PORTC_IE_C11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_IE_C11_BITS_ENABLE            (PORTCON_PORTC_IE_C11_VALUE_ENABLE << PORTCON_PORTC_IE_C11_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C12_SHIFT                  12\r\n#define PORTCON_PORTC_IE_C12_WIDTH                  1\r\n#define PORTCON_PORTC_IE_C12_MASK                   (((1U << PORTCON_PORTC_IE_C12_WIDTH) - 1U) << PORTCON_PORTC_IE_C12_SHIFT)\r\n#define PORTCON_PORTC_IE_C12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_IE_C12_BITS_DISABLE           (PORTCON_PORTC_IE_C12_VALUE_DISABLE << PORTCON_PORTC_IE_C12_SHIFT)\r\n#define PORTCON_PORTC_IE_C12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_IE_C12_BITS_ENABLE            (PORTCON_PORTC_IE_C12_VALUE_ENABLE << PORTCON_PORTC_IE_C12_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C13_SHIFT                  13\r\n#define PORTCON_PORTC_IE_C13_WIDTH                  1\r\n#define PORTCON_PORTC_IE_C13_MASK                   (((1U << PORTCON_PORTC_IE_C13_WIDTH) - 1U) << PORTCON_PORTC_IE_C13_SHIFT)\r\n#define PORTCON_PORTC_IE_C13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_IE_C13_BITS_DISABLE           (PORTCON_PORTC_IE_C13_VALUE_DISABLE << PORTCON_PORTC_IE_C13_SHIFT)\r\n#define PORTCON_PORTC_IE_C13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_IE_C13_BITS_ENABLE            (PORTCON_PORTC_IE_C13_VALUE_ENABLE << PORTCON_PORTC_IE_C13_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C14_SHIFT                  14\r\n#define PORTCON_PORTC_IE_C14_WIDTH                  1\r\n#define PORTCON_PORTC_IE_C14_MASK                   (((1U << PORTCON_PORTC_IE_C14_WIDTH) - 1U) << PORTCON_PORTC_IE_C14_SHIFT)\r\n#define PORTCON_PORTC_IE_C14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_IE_C14_BITS_DISABLE           (PORTCON_PORTC_IE_C14_VALUE_DISABLE << PORTCON_PORTC_IE_C14_SHIFT)\r\n#define PORTCON_PORTC_IE_C14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_IE_C14_BITS_ENABLE            (PORTCON_PORTC_IE_C14_VALUE_ENABLE << PORTCON_PORTC_IE_C14_SHIFT)\r\n\r\n#define PORTCON_PORTC_IE_C15_SHIFT                  15\r\n#define PORTCON_PORTC_IE_C15_WIDTH                  1\r\n#define PORTCON_PORTC_IE_C15_MASK                   (((1U << PORTCON_PORTC_IE_C15_WIDTH) - 1U) << PORTCON_PORTC_IE_C15_SHIFT)\r\n#define PORTCON_PORTC_IE_C15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_IE_C15_BITS_DISABLE           (PORTCON_PORTC_IE_C15_VALUE_DISABLE << PORTCON_PORTC_IE_C15_SHIFT)\r\n#define PORTCON_PORTC_IE_C15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_IE_C15_BITS_ENABLE            (PORTCON_PORTC_IE_C15_VALUE_ENABLE << PORTCON_PORTC_IE_C15_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_ADDR                       (PORTCON_BASE_ADDR + 0x0200U)\r\n#define PORTCON_PORTA_PU                            (*(volatile uint32_t *)PORTCON_PORTA_PU_ADDR)\r\n#define PORTCON_PORTA_PU_A0_SHIFT                   0\r\n#define PORTCON_PORTA_PU_A0_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A0_MASK                    (((1U << PORTCON_PORTA_PU_A0_WIDTH) - 1U) << PORTCON_PORTA_PU_A0_SHIFT)\r\n#define PORTCON_PORTA_PU_A0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A0_BITS_DISABLE            (PORTCON_PORTA_PU_A0_VALUE_DISABLE << PORTCON_PORTA_PU_A0_SHIFT)\r\n#define PORTCON_PORTA_PU_A0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A0_BITS_ENABLE             (PORTCON_PORTA_PU_A0_VALUE_ENABLE << PORTCON_PORTA_PU_A0_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A1_SHIFT                   1\r\n#define PORTCON_PORTA_PU_A1_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A1_MASK                    (((1U << PORTCON_PORTA_PU_A1_WIDTH) - 1U) << PORTCON_PORTA_PU_A1_SHIFT)\r\n#define PORTCON_PORTA_PU_A1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A1_BITS_DISABLE            (PORTCON_PORTA_PU_A1_VALUE_DISABLE << PORTCON_PORTA_PU_A1_SHIFT)\r\n#define PORTCON_PORTA_PU_A1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A1_BITS_ENABLE             (PORTCON_PORTA_PU_A1_VALUE_ENABLE << PORTCON_PORTA_PU_A1_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A2_SHIFT                   2\r\n#define PORTCON_PORTA_PU_A2_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A2_MASK                    (((1U << PORTCON_PORTA_PU_A2_WIDTH) - 1U) << PORTCON_PORTA_PU_A2_SHIFT)\r\n#define PORTCON_PORTA_PU_A2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A2_BITS_DISABLE            (PORTCON_PORTA_PU_A2_VALUE_DISABLE << PORTCON_PORTA_PU_A2_SHIFT)\r\n#define PORTCON_PORTA_PU_A2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A2_BITS_ENABLE             (PORTCON_PORTA_PU_A2_VALUE_ENABLE << PORTCON_PORTA_PU_A2_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A3_SHIFT                   3\r\n#define PORTCON_PORTA_PU_A3_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A3_MASK                    (((1U << PORTCON_PORTA_PU_A3_WIDTH) - 1U) << PORTCON_PORTA_PU_A3_SHIFT)\r\n#define PORTCON_PORTA_PU_A3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A3_BITS_DISABLE            (PORTCON_PORTA_PU_A3_VALUE_DISABLE << PORTCON_PORTA_PU_A3_SHIFT)\r\n#define PORTCON_PORTA_PU_A3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A3_BITS_ENABLE             (PORTCON_PORTA_PU_A3_VALUE_ENABLE << PORTCON_PORTA_PU_A3_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A4_SHIFT                   4\r\n#define PORTCON_PORTA_PU_A4_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A4_MASK                    (((1U << PORTCON_PORTA_PU_A4_WIDTH) - 1U) << PORTCON_PORTA_PU_A4_SHIFT)\r\n#define PORTCON_PORTA_PU_A4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A4_BITS_DISABLE            (PORTCON_PORTA_PU_A4_VALUE_DISABLE << PORTCON_PORTA_PU_A4_SHIFT)\r\n#define PORTCON_PORTA_PU_A4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A4_BITS_ENABLE             (PORTCON_PORTA_PU_A4_VALUE_ENABLE << PORTCON_PORTA_PU_A4_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A5_SHIFT                   5\r\n#define PORTCON_PORTA_PU_A5_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A5_MASK                    (((1U << PORTCON_PORTA_PU_A5_WIDTH) - 1U) << PORTCON_PORTA_PU_A5_SHIFT)\r\n#define PORTCON_PORTA_PU_A5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A5_BITS_DISABLE            (PORTCON_PORTA_PU_A5_VALUE_DISABLE << PORTCON_PORTA_PU_A5_SHIFT)\r\n#define PORTCON_PORTA_PU_A5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A5_BITS_ENABLE             (PORTCON_PORTA_PU_A5_VALUE_ENABLE << PORTCON_PORTA_PU_A5_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A6_SHIFT                   6\r\n#define PORTCON_PORTA_PU_A6_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A6_MASK                    (((1U << PORTCON_PORTA_PU_A6_WIDTH) - 1U) << PORTCON_PORTA_PU_A6_SHIFT)\r\n#define PORTCON_PORTA_PU_A6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A6_BITS_DISABLE            (PORTCON_PORTA_PU_A6_VALUE_DISABLE << PORTCON_PORTA_PU_A6_SHIFT)\r\n#define PORTCON_PORTA_PU_A6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A6_BITS_ENABLE             (PORTCON_PORTA_PU_A6_VALUE_ENABLE << PORTCON_PORTA_PU_A6_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A7_SHIFT                   7\r\n#define PORTCON_PORTA_PU_A7_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A7_MASK                    (((1U << PORTCON_PORTA_PU_A7_WIDTH) - 1U) << PORTCON_PORTA_PU_A7_SHIFT)\r\n#define PORTCON_PORTA_PU_A7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A7_BITS_DISABLE            (PORTCON_PORTA_PU_A7_VALUE_DISABLE << PORTCON_PORTA_PU_A7_SHIFT)\r\n#define PORTCON_PORTA_PU_A7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A7_BITS_ENABLE             (PORTCON_PORTA_PU_A7_VALUE_ENABLE << PORTCON_PORTA_PU_A7_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A8_SHIFT                   8\r\n#define PORTCON_PORTA_PU_A8_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A8_MASK                    (((1U << PORTCON_PORTA_PU_A8_WIDTH) - 1U) << PORTCON_PORTA_PU_A8_SHIFT)\r\n#define PORTCON_PORTA_PU_A8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A8_BITS_DISABLE            (PORTCON_PORTA_PU_A8_VALUE_DISABLE << PORTCON_PORTA_PU_A8_SHIFT)\r\n#define PORTCON_PORTA_PU_A8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A8_BITS_ENABLE             (PORTCON_PORTA_PU_A8_VALUE_ENABLE << PORTCON_PORTA_PU_A8_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A9_SHIFT                   9\r\n#define PORTCON_PORTA_PU_A9_WIDTH                   1\r\n#define PORTCON_PORTA_PU_A9_MASK                    (((1U << PORTCON_PORTA_PU_A9_WIDTH) - 1U) << PORTCON_PORTA_PU_A9_SHIFT)\r\n#define PORTCON_PORTA_PU_A9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PU_A9_BITS_DISABLE            (PORTCON_PORTA_PU_A9_VALUE_DISABLE << PORTCON_PORTA_PU_A9_SHIFT)\r\n#define PORTCON_PORTA_PU_A9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PU_A9_BITS_ENABLE             (PORTCON_PORTA_PU_A9_VALUE_ENABLE << PORTCON_PORTA_PU_A9_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A10_SHIFT                  10\r\n#define PORTCON_PORTA_PU_A10_WIDTH                  1\r\n#define PORTCON_PORTA_PU_A10_MASK                   (((1U << PORTCON_PORTA_PU_A10_WIDTH) - 1U) << PORTCON_PORTA_PU_A10_SHIFT)\r\n#define PORTCON_PORTA_PU_A10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PU_A10_BITS_DISABLE           (PORTCON_PORTA_PU_A10_VALUE_DISABLE << PORTCON_PORTA_PU_A10_SHIFT)\r\n#define PORTCON_PORTA_PU_A10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PU_A10_BITS_ENABLE            (PORTCON_PORTA_PU_A10_VALUE_ENABLE << PORTCON_PORTA_PU_A10_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A11_SHIFT                  11\r\n#define PORTCON_PORTA_PU_A11_WIDTH                  1\r\n#define PORTCON_PORTA_PU_A11_MASK                   (((1U << PORTCON_PORTA_PU_A11_WIDTH) - 1U) << PORTCON_PORTA_PU_A11_SHIFT)\r\n#define PORTCON_PORTA_PU_A11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PU_A11_BITS_DISABLE           (PORTCON_PORTA_PU_A11_VALUE_DISABLE << PORTCON_PORTA_PU_A11_SHIFT)\r\n#define PORTCON_PORTA_PU_A11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PU_A11_BITS_ENABLE            (PORTCON_PORTA_PU_A11_VALUE_ENABLE << PORTCON_PORTA_PU_A11_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A12_SHIFT                  12\r\n#define PORTCON_PORTA_PU_A12_WIDTH                  1\r\n#define PORTCON_PORTA_PU_A12_MASK                   (((1U << PORTCON_PORTA_PU_A12_WIDTH) - 1U) << PORTCON_PORTA_PU_A12_SHIFT)\r\n#define PORTCON_PORTA_PU_A12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PU_A12_BITS_DISABLE           (PORTCON_PORTA_PU_A12_VALUE_DISABLE << PORTCON_PORTA_PU_A12_SHIFT)\r\n#define PORTCON_PORTA_PU_A12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PU_A12_BITS_ENABLE            (PORTCON_PORTA_PU_A12_VALUE_ENABLE << PORTCON_PORTA_PU_A12_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A13_SHIFT                  13\r\n#define PORTCON_PORTA_PU_A13_WIDTH                  1\r\n#define PORTCON_PORTA_PU_A13_MASK                   (((1U << PORTCON_PORTA_PU_A13_WIDTH) - 1U) << PORTCON_PORTA_PU_A13_SHIFT)\r\n#define PORTCON_PORTA_PU_A13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PU_A13_BITS_DISABLE           (PORTCON_PORTA_PU_A13_VALUE_DISABLE << PORTCON_PORTA_PU_A13_SHIFT)\r\n#define PORTCON_PORTA_PU_A13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PU_A13_BITS_ENABLE            (PORTCON_PORTA_PU_A13_VALUE_ENABLE << PORTCON_PORTA_PU_A13_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A14_SHIFT                  14\r\n#define PORTCON_PORTA_PU_A14_WIDTH                  1\r\n#define PORTCON_PORTA_PU_A14_MASK                   (((1U << PORTCON_PORTA_PU_A14_WIDTH) - 1U) << PORTCON_PORTA_PU_A14_SHIFT)\r\n#define PORTCON_PORTA_PU_A14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PU_A14_BITS_DISABLE           (PORTCON_PORTA_PU_A14_VALUE_DISABLE << PORTCON_PORTA_PU_A14_SHIFT)\r\n#define PORTCON_PORTA_PU_A14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PU_A14_BITS_ENABLE            (PORTCON_PORTA_PU_A14_VALUE_ENABLE << PORTCON_PORTA_PU_A14_SHIFT)\r\n\r\n#define PORTCON_PORTA_PU_A15_SHIFT                  15\r\n#define PORTCON_PORTA_PU_A15_WIDTH                  1\r\n#define PORTCON_PORTA_PU_A15_MASK                   (((1U << PORTCON_PORTA_PU_A15_WIDTH) - 1U) << PORTCON_PORTA_PU_A15_SHIFT)\r\n#define PORTCON_PORTA_PU_A15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PU_A15_BITS_DISABLE           (PORTCON_PORTA_PU_A15_VALUE_DISABLE << PORTCON_PORTA_PU_A15_SHIFT)\r\n#define PORTCON_PORTA_PU_A15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PU_A15_BITS_ENABLE            (PORTCON_PORTA_PU_A15_VALUE_ENABLE << PORTCON_PORTA_PU_A15_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_ADDR                       (PORTCON_BASE_ADDR + 0x0204U)\r\n#define PORTCON_PORTB_PU                            (*(volatile uint32_t *)PORTCON_PORTB_PU_ADDR)\r\n#define PORTCON_PORTB_PU_B0_SHIFT                   0\r\n#define PORTCON_PORTB_PU_B0_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B0_MASK                    (((1U << PORTCON_PORTB_PU_B0_WIDTH) - 1U) << PORTCON_PORTB_PU_B0_SHIFT)\r\n#define PORTCON_PORTB_PU_B0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B0_BITS_DISABLE            (PORTCON_PORTB_PU_B0_VALUE_DISABLE << PORTCON_PORTB_PU_B0_SHIFT)\r\n#define PORTCON_PORTB_PU_B0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B0_BITS_ENABLE             (PORTCON_PORTB_PU_B0_VALUE_ENABLE << PORTCON_PORTB_PU_B0_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B1_SHIFT                   1\r\n#define PORTCON_PORTB_PU_B1_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B1_MASK                    (((1U << PORTCON_PORTB_PU_B1_WIDTH) - 1U) << PORTCON_PORTB_PU_B1_SHIFT)\r\n#define PORTCON_PORTB_PU_B1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B1_BITS_DISABLE            (PORTCON_PORTB_PU_B1_VALUE_DISABLE << PORTCON_PORTB_PU_B1_SHIFT)\r\n#define PORTCON_PORTB_PU_B1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B1_BITS_ENABLE             (PORTCON_PORTB_PU_B1_VALUE_ENABLE << PORTCON_PORTB_PU_B1_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B2_SHIFT                   2\r\n#define PORTCON_PORTB_PU_B2_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B2_MASK                    (((1U << PORTCON_PORTB_PU_B2_WIDTH) - 1U) << PORTCON_PORTB_PU_B2_SHIFT)\r\n#define PORTCON_PORTB_PU_B2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B2_BITS_DISABLE            (PORTCON_PORTB_PU_B2_VALUE_DISABLE << PORTCON_PORTB_PU_B2_SHIFT)\r\n#define PORTCON_PORTB_PU_B2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B2_BITS_ENABLE             (PORTCON_PORTB_PU_B2_VALUE_ENABLE << PORTCON_PORTB_PU_B2_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B3_SHIFT                   3\r\n#define PORTCON_PORTB_PU_B3_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B3_MASK                    (((1U << PORTCON_PORTB_PU_B3_WIDTH) - 1U) << PORTCON_PORTB_PU_B3_SHIFT)\r\n#define PORTCON_PORTB_PU_B3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B3_BITS_DISABLE            (PORTCON_PORTB_PU_B3_VALUE_DISABLE << PORTCON_PORTB_PU_B3_SHIFT)\r\n#define PORTCON_PORTB_PU_B3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B3_BITS_ENABLE             (PORTCON_PORTB_PU_B3_VALUE_ENABLE << PORTCON_PORTB_PU_B3_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B4_SHIFT                   4\r\n#define PORTCON_PORTB_PU_B4_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B4_MASK                    (((1U << PORTCON_PORTB_PU_B4_WIDTH) - 1U) << PORTCON_PORTB_PU_B4_SHIFT)\r\n#define PORTCON_PORTB_PU_B4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B4_BITS_DISABLE            (PORTCON_PORTB_PU_B4_VALUE_DISABLE << PORTCON_PORTB_PU_B4_SHIFT)\r\n#define PORTCON_PORTB_PU_B4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B4_BITS_ENABLE             (PORTCON_PORTB_PU_B4_VALUE_ENABLE << PORTCON_PORTB_PU_B4_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B5_SHIFT                   5\r\n#define PORTCON_PORTB_PU_B5_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B5_MASK                    (((1U << PORTCON_PORTB_PU_B5_WIDTH) - 1U) << PORTCON_PORTB_PU_B5_SHIFT)\r\n#define PORTCON_PORTB_PU_B5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B5_BITS_DISABLE            (PORTCON_PORTB_PU_B5_VALUE_DISABLE << PORTCON_PORTB_PU_B5_SHIFT)\r\n#define PORTCON_PORTB_PU_B5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B5_BITS_ENABLE             (PORTCON_PORTB_PU_B5_VALUE_ENABLE << PORTCON_PORTB_PU_B5_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B6_SHIFT                   6\r\n#define PORTCON_PORTB_PU_B6_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B6_MASK                    (((1U << PORTCON_PORTB_PU_B6_WIDTH) - 1U) << PORTCON_PORTB_PU_B6_SHIFT)\r\n#define PORTCON_PORTB_PU_B6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B6_BITS_DISABLE            (PORTCON_PORTB_PU_B6_VALUE_DISABLE << PORTCON_PORTB_PU_B6_SHIFT)\r\n#define PORTCON_PORTB_PU_B6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B6_BITS_ENABLE             (PORTCON_PORTB_PU_B6_VALUE_ENABLE << PORTCON_PORTB_PU_B6_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B7_SHIFT                   7\r\n#define PORTCON_PORTB_PU_B7_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B7_MASK                    (((1U << PORTCON_PORTB_PU_B7_WIDTH) - 1U) << PORTCON_PORTB_PU_B7_SHIFT)\r\n#define PORTCON_PORTB_PU_B7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B7_BITS_DISABLE            (PORTCON_PORTB_PU_B7_VALUE_DISABLE << PORTCON_PORTB_PU_B7_SHIFT)\r\n#define PORTCON_PORTB_PU_B7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B7_BITS_ENABLE             (PORTCON_PORTB_PU_B7_VALUE_ENABLE << PORTCON_PORTB_PU_B7_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B8_SHIFT                   8\r\n#define PORTCON_PORTB_PU_B8_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B8_MASK                    (((1U << PORTCON_PORTB_PU_B8_WIDTH) - 1U) << PORTCON_PORTB_PU_B8_SHIFT)\r\n#define PORTCON_PORTB_PU_B8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B8_BITS_DISABLE            (PORTCON_PORTB_PU_B8_VALUE_DISABLE << PORTCON_PORTB_PU_B8_SHIFT)\r\n#define PORTCON_PORTB_PU_B8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B8_BITS_ENABLE             (PORTCON_PORTB_PU_B8_VALUE_ENABLE << PORTCON_PORTB_PU_B8_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B9_SHIFT                   9\r\n#define PORTCON_PORTB_PU_B9_WIDTH                   1\r\n#define PORTCON_PORTB_PU_B9_MASK                    (((1U << PORTCON_PORTB_PU_B9_WIDTH) - 1U) << PORTCON_PORTB_PU_B9_SHIFT)\r\n#define PORTCON_PORTB_PU_B9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PU_B9_BITS_DISABLE            (PORTCON_PORTB_PU_B9_VALUE_DISABLE << PORTCON_PORTB_PU_B9_SHIFT)\r\n#define PORTCON_PORTB_PU_B9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PU_B9_BITS_ENABLE             (PORTCON_PORTB_PU_B9_VALUE_ENABLE << PORTCON_PORTB_PU_B9_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B10_SHIFT                  10\r\n#define PORTCON_PORTB_PU_B10_WIDTH                  1\r\n#define PORTCON_PORTB_PU_B10_MASK                   (((1U << PORTCON_PORTB_PU_B10_WIDTH) - 1U) << PORTCON_PORTB_PU_B10_SHIFT)\r\n#define PORTCON_PORTB_PU_B10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PU_B10_BITS_DISABLE           (PORTCON_PORTB_PU_B10_VALUE_DISABLE << PORTCON_PORTB_PU_B10_SHIFT)\r\n#define PORTCON_PORTB_PU_B10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PU_B10_BITS_ENABLE            (PORTCON_PORTB_PU_B10_VALUE_ENABLE << PORTCON_PORTB_PU_B10_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B11_SHIFT                  11\r\n#define PORTCON_PORTB_PU_B11_WIDTH                  1\r\n#define PORTCON_PORTB_PU_B11_MASK                   (((1U << PORTCON_PORTB_PU_B11_WIDTH) - 1U) << PORTCON_PORTB_PU_B11_SHIFT)\r\n#define PORTCON_PORTB_PU_B11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PU_B11_BITS_DISABLE           (PORTCON_PORTB_PU_B11_VALUE_DISABLE << PORTCON_PORTB_PU_B11_SHIFT)\r\n#define PORTCON_PORTB_PU_B11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PU_B11_BITS_ENABLE            (PORTCON_PORTB_PU_B11_VALUE_ENABLE << PORTCON_PORTB_PU_B11_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B12_SHIFT                  12\r\n#define PORTCON_PORTB_PU_B12_WIDTH                  1\r\n#define PORTCON_PORTB_PU_B12_MASK                   (((1U << PORTCON_PORTB_PU_B12_WIDTH) - 1U) << PORTCON_PORTB_PU_B12_SHIFT)\r\n#define PORTCON_PORTB_PU_B12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PU_B12_BITS_DISABLE           (PORTCON_PORTB_PU_B12_VALUE_DISABLE << PORTCON_PORTB_PU_B12_SHIFT)\r\n#define PORTCON_PORTB_PU_B12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PU_B12_BITS_ENABLE            (PORTCON_PORTB_PU_B12_VALUE_ENABLE << PORTCON_PORTB_PU_B12_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B13_SHIFT                  13\r\n#define PORTCON_PORTB_PU_B13_WIDTH                  1\r\n#define PORTCON_PORTB_PU_B13_MASK                   (((1U << PORTCON_PORTB_PU_B13_WIDTH) - 1U) << PORTCON_PORTB_PU_B13_SHIFT)\r\n#define PORTCON_PORTB_PU_B13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PU_B13_BITS_DISABLE           (PORTCON_PORTB_PU_B13_VALUE_DISABLE << PORTCON_PORTB_PU_B13_SHIFT)\r\n#define PORTCON_PORTB_PU_B13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PU_B13_BITS_ENABLE            (PORTCON_PORTB_PU_B13_VALUE_ENABLE << PORTCON_PORTB_PU_B13_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B14_SHIFT                  14\r\n#define PORTCON_PORTB_PU_B14_WIDTH                  1\r\n#define PORTCON_PORTB_PU_B14_MASK                   (((1U << PORTCON_PORTB_PU_B14_WIDTH) - 1U) << PORTCON_PORTB_PU_B14_SHIFT)\r\n#define PORTCON_PORTB_PU_B14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PU_B14_BITS_DISABLE           (PORTCON_PORTB_PU_B14_VALUE_DISABLE << PORTCON_PORTB_PU_B14_SHIFT)\r\n#define PORTCON_PORTB_PU_B14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PU_B14_BITS_ENABLE            (PORTCON_PORTB_PU_B14_VALUE_ENABLE << PORTCON_PORTB_PU_B14_SHIFT)\r\n\r\n#define PORTCON_PORTB_PU_B15_SHIFT                  15\r\n#define PORTCON_PORTB_PU_B15_WIDTH                  1\r\n#define PORTCON_PORTB_PU_B15_MASK                   (((1U << PORTCON_PORTB_PU_B15_WIDTH) - 1U) << PORTCON_PORTB_PU_B15_SHIFT)\r\n#define PORTCON_PORTB_PU_B15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PU_B15_BITS_DISABLE           (PORTCON_PORTB_PU_B15_VALUE_DISABLE << PORTCON_PORTB_PU_B15_SHIFT)\r\n#define PORTCON_PORTB_PU_B15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PU_B15_BITS_ENABLE            (PORTCON_PORTB_PU_B15_VALUE_ENABLE << PORTCON_PORTB_PU_B15_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_ADDR                       (PORTCON_BASE_ADDR + 0x0208U)\r\n#define PORTCON_PORTC_PU                            (*(volatile uint32_t *)PORTCON_PORTC_PU_ADDR)\r\n#define PORTCON_PORTC_PU_C0_SHIFT                   0\r\n#define PORTCON_PORTC_PU_C0_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C0_MASK                    (((1U << PORTCON_PORTC_PU_C0_WIDTH) - 1U) << PORTCON_PORTC_PU_C0_SHIFT)\r\n#define PORTCON_PORTC_PU_C0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C0_BITS_DISABLE            (PORTCON_PORTC_PU_C0_VALUE_DISABLE << PORTCON_PORTC_PU_C0_SHIFT)\r\n#define PORTCON_PORTC_PU_C0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C0_BITS_ENABLE             (PORTCON_PORTC_PU_C0_VALUE_ENABLE << PORTCON_PORTC_PU_C0_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C1_SHIFT                   1\r\n#define PORTCON_PORTC_PU_C1_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C1_MASK                    (((1U << PORTCON_PORTC_PU_C1_WIDTH) - 1U) << PORTCON_PORTC_PU_C1_SHIFT)\r\n#define PORTCON_PORTC_PU_C1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C1_BITS_DISABLE            (PORTCON_PORTC_PU_C1_VALUE_DISABLE << PORTCON_PORTC_PU_C1_SHIFT)\r\n#define PORTCON_PORTC_PU_C1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C1_BITS_ENABLE             (PORTCON_PORTC_PU_C1_VALUE_ENABLE << PORTCON_PORTC_PU_C1_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C2_SHIFT                   2\r\n#define PORTCON_PORTC_PU_C2_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C2_MASK                    (((1U << PORTCON_PORTC_PU_C2_WIDTH) - 1U) << PORTCON_PORTC_PU_C2_SHIFT)\r\n#define PORTCON_PORTC_PU_C2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C2_BITS_DISABLE            (PORTCON_PORTC_PU_C2_VALUE_DISABLE << PORTCON_PORTC_PU_C2_SHIFT)\r\n#define PORTCON_PORTC_PU_C2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C2_BITS_ENABLE             (PORTCON_PORTC_PU_C2_VALUE_ENABLE << PORTCON_PORTC_PU_C2_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C3_SHIFT                   3\r\n#define PORTCON_PORTC_PU_C3_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C3_MASK                    (((1U << PORTCON_PORTC_PU_C3_WIDTH) - 1U) << PORTCON_PORTC_PU_C3_SHIFT)\r\n#define PORTCON_PORTC_PU_C3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C3_BITS_DISABLE            (PORTCON_PORTC_PU_C3_VALUE_DISABLE << PORTCON_PORTC_PU_C3_SHIFT)\r\n#define PORTCON_PORTC_PU_C3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C3_BITS_ENABLE             (PORTCON_PORTC_PU_C3_VALUE_ENABLE << PORTCON_PORTC_PU_C3_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C4_SHIFT                   4\r\n#define PORTCON_PORTC_PU_C4_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C4_MASK                    (((1U << PORTCON_PORTC_PU_C4_WIDTH) - 1U) << PORTCON_PORTC_PU_C4_SHIFT)\r\n#define PORTCON_PORTC_PU_C4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C4_BITS_DISABLE            (PORTCON_PORTC_PU_C4_VALUE_DISABLE << PORTCON_PORTC_PU_C4_SHIFT)\r\n#define PORTCON_PORTC_PU_C4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C4_BITS_ENABLE             (PORTCON_PORTC_PU_C4_VALUE_ENABLE << PORTCON_PORTC_PU_C4_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C5_SHIFT                   5\r\n#define PORTCON_PORTC_PU_C5_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C5_MASK                    (((1U << PORTCON_PORTC_PU_C5_WIDTH) - 1U) << PORTCON_PORTC_PU_C5_SHIFT)\r\n#define PORTCON_PORTC_PU_C5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C5_BITS_DISABLE            (PORTCON_PORTC_PU_C5_VALUE_DISABLE << PORTCON_PORTC_PU_C5_SHIFT)\r\n#define PORTCON_PORTC_PU_C5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C5_BITS_ENABLE             (PORTCON_PORTC_PU_C5_VALUE_ENABLE << PORTCON_PORTC_PU_C5_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C6_SHIFT                   6\r\n#define PORTCON_PORTC_PU_C6_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C6_MASK                    (((1U << PORTCON_PORTC_PU_C6_WIDTH) - 1U) << PORTCON_PORTC_PU_C6_SHIFT)\r\n#define PORTCON_PORTC_PU_C6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C6_BITS_DISABLE            (PORTCON_PORTC_PU_C6_VALUE_DISABLE << PORTCON_PORTC_PU_C6_SHIFT)\r\n#define PORTCON_PORTC_PU_C6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C6_BITS_ENABLE             (PORTCON_PORTC_PU_C6_VALUE_ENABLE << PORTCON_PORTC_PU_C6_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C7_SHIFT                   7\r\n#define PORTCON_PORTC_PU_C7_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C7_MASK                    (((1U << PORTCON_PORTC_PU_C7_WIDTH) - 1U) << PORTCON_PORTC_PU_C7_SHIFT)\r\n#define PORTCON_PORTC_PU_C7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C7_BITS_DISABLE            (PORTCON_PORTC_PU_C7_VALUE_DISABLE << PORTCON_PORTC_PU_C7_SHIFT)\r\n#define PORTCON_PORTC_PU_C7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C7_BITS_ENABLE             (PORTCON_PORTC_PU_C7_VALUE_ENABLE << PORTCON_PORTC_PU_C7_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C8_SHIFT                   8\r\n#define PORTCON_PORTC_PU_C8_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C8_MASK                    (((1U << PORTCON_PORTC_PU_C8_WIDTH) - 1U) << PORTCON_PORTC_PU_C8_SHIFT)\r\n#define PORTCON_PORTC_PU_C8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C8_BITS_DISABLE            (PORTCON_PORTC_PU_C8_VALUE_DISABLE << PORTCON_PORTC_PU_C8_SHIFT)\r\n#define PORTCON_PORTC_PU_C8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C8_BITS_ENABLE             (PORTCON_PORTC_PU_C8_VALUE_ENABLE << PORTCON_PORTC_PU_C8_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C9_SHIFT                   9\r\n#define PORTCON_PORTC_PU_C9_WIDTH                   1\r\n#define PORTCON_PORTC_PU_C9_MASK                    (((1U << PORTCON_PORTC_PU_C9_WIDTH) - 1U) << PORTCON_PORTC_PU_C9_SHIFT)\r\n#define PORTCON_PORTC_PU_C9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PU_C9_BITS_DISABLE            (PORTCON_PORTC_PU_C9_VALUE_DISABLE << PORTCON_PORTC_PU_C9_SHIFT)\r\n#define PORTCON_PORTC_PU_C9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PU_C9_BITS_ENABLE             (PORTCON_PORTC_PU_C9_VALUE_ENABLE << PORTCON_PORTC_PU_C9_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C10_SHIFT                  10\r\n#define PORTCON_PORTC_PU_C10_WIDTH                  1\r\n#define PORTCON_PORTC_PU_C10_MASK                   (((1U << PORTCON_PORTC_PU_C10_WIDTH) - 1U) << PORTCON_PORTC_PU_C10_SHIFT)\r\n#define PORTCON_PORTC_PU_C10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PU_C10_BITS_DISABLE           (PORTCON_PORTC_PU_C10_VALUE_DISABLE << PORTCON_PORTC_PU_C10_SHIFT)\r\n#define PORTCON_PORTC_PU_C10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PU_C10_BITS_ENABLE            (PORTCON_PORTC_PU_C10_VALUE_ENABLE << PORTCON_PORTC_PU_C10_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C11_SHIFT                  11\r\n#define PORTCON_PORTC_PU_C11_WIDTH                  1\r\n#define PORTCON_PORTC_PU_C11_MASK                   (((1U << PORTCON_PORTC_PU_C11_WIDTH) - 1U) << PORTCON_PORTC_PU_C11_SHIFT)\r\n#define PORTCON_PORTC_PU_C11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PU_C11_BITS_DISABLE           (PORTCON_PORTC_PU_C11_VALUE_DISABLE << PORTCON_PORTC_PU_C11_SHIFT)\r\n#define PORTCON_PORTC_PU_C11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PU_C11_BITS_ENABLE            (PORTCON_PORTC_PU_C11_VALUE_ENABLE << PORTCON_PORTC_PU_C11_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C12_SHIFT                  12\r\n#define PORTCON_PORTC_PU_C12_WIDTH                  1\r\n#define PORTCON_PORTC_PU_C12_MASK                   (((1U << PORTCON_PORTC_PU_C12_WIDTH) - 1U) << PORTCON_PORTC_PU_C12_SHIFT)\r\n#define PORTCON_PORTC_PU_C12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PU_C12_BITS_DISABLE           (PORTCON_PORTC_PU_C12_VALUE_DISABLE << PORTCON_PORTC_PU_C12_SHIFT)\r\n#define PORTCON_PORTC_PU_C12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PU_C12_BITS_ENABLE            (PORTCON_PORTC_PU_C12_VALUE_ENABLE << PORTCON_PORTC_PU_C12_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C13_SHIFT                  13\r\n#define PORTCON_PORTC_PU_C13_WIDTH                  1\r\n#define PORTCON_PORTC_PU_C13_MASK                   (((1U << PORTCON_PORTC_PU_C13_WIDTH) - 1U) << PORTCON_PORTC_PU_C13_SHIFT)\r\n#define PORTCON_PORTC_PU_C13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PU_C13_BITS_DISABLE           (PORTCON_PORTC_PU_C13_VALUE_DISABLE << PORTCON_PORTC_PU_C13_SHIFT)\r\n#define PORTCON_PORTC_PU_C13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PU_C13_BITS_ENABLE            (PORTCON_PORTC_PU_C13_VALUE_ENABLE << PORTCON_PORTC_PU_C13_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C14_SHIFT                  14\r\n#define PORTCON_PORTC_PU_C14_WIDTH                  1\r\n#define PORTCON_PORTC_PU_C14_MASK                   (((1U << PORTCON_PORTC_PU_C14_WIDTH) - 1U) << PORTCON_PORTC_PU_C14_SHIFT)\r\n#define PORTCON_PORTC_PU_C14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PU_C14_BITS_DISABLE           (PORTCON_PORTC_PU_C14_VALUE_DISABLE << PORTCON_PORTC_PU_C14_SHIFT)\r\n#define PORTCON_PORTC_PU_C14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PU_C14_BITS_ENABLE            (PORTCON_PORTC_PU_C14_VALUE_ENABLE << PORTCON_PORTC_PU_C14_SHIFT)\r\n\r\n#define PORTCON_PORTC_PU_C15_SHIFT                  15\r\n#define PORTCON_PORTC_PU_C15_WIDTH                  1\r\n#define PORTCON_PORTC_PU_C15_MASK                   (((1U << PORTCON_PORTC_PU_C15_WIDTH) - 1U) << PORTCON_PORTC_PU_C15_SHIFT)\r\n#define PORTCON_PORTC_PU_C15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PU_C15_BITS_DISABLE           (PORTCON_PORTC_PU_C15_VALUE_DISABLE << PORTCON_PORTC_PU_C15_SHIFT)\r\n#define PORTCON_PORTC_PU_C15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PU_C15_BITS_ENABLE            (PORTCON_PORTC_PU_C15_VALUE_ENABLE << PORTCON_PORTC_PU_C15_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_ADDR                       (PORTCON_BASE_ADDR + 0x0300U)\r\n#define PORTCON_PORTA_PD                            (*(volatile uint32_t *)PORTCON_PORTA_PD_ADDR)\r\n#define PORTCON_PORTA_PD_A0_SHIFT                   0\r\n#define PORTCON_PORTA_PD_A0_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A0_MASK                    (((1U << PORTCON_PORTA_PD_A0_WIDTH) - 1U) << PORTCON_PORTA_PD_A0_SHIFT)\r\n#define PORTCON_PORTA_PD_A0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A0_BITS_DISABLE            (PORTCON_PORTA_PD_A0_VALUE_DISABLE << PORTCON_PORTA_PD_A0_SHIFT)\r\n#define PORTCON_PORTA_PD_A0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A0_BITS_ENABLE             (PORTCON_PORTA_PD_A0_VALUE_ENABLE << PORTCON_PORTA_PD_A0_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A1_SHIFT                   1\r\n#define PORTCON_PORTA_PD_A1_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A1_MASK                    (((1U << PORTCON_PORTA_PD_A1_WIDTH) - 1U) << PORTCON_PORTA_PD_A1_SHIFT)\r\n#define PORTCON_PORTA_PD_A1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A1_BITS_DISABLE            (PORTCON_PORTA_PD_A1_VALUE_DISABLE << PORTCON_PORTA_PD_A1_SHIFT)\r\n#define PORTCON_PORTA_PD_A1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A1_BITS_ENABLE             (PORTCON_PORTA_PD_A1_VALUE_ENABLE << PORTCON_PORTA_PD_A1_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A2_SHIFT                   2\r\n#define PORTCON_PORTA_PD_A2_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A2_MASK                    (((1U << PORTCON_PORTA_PD_A2_WIDTH) - 1U) << PORTCON_PORTA_PD_A2_SHIFT)\r\n#define PORTCON_PORTA_PD_A2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A2_BITS_DISABLE            (PORTCON_PORTA_PD_A2_VALUE_DISABLE << PORTCON_PORTA_PD_A2_SHIFT)\r\n#define PORTCON_PORTA_PD_A2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A2_BITS_ENABLE             (PORTCON_PORTA_PD_A2_VALUE_ENABLE << PORTCON_PORTA_PD_A2_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A3_SHIFT                   3\r\n#define PORTCON_PORTA_PD_A3_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A3_MASK                    (((1U << PORTCON_PORTA_PD_A3_WIDTH) - 1U) << PORTCON_PORTA_PD_A3_SHIFT)\r\n#define PORTCON_PORTA_PD_A3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A3_BITS_DISABLE            (PORTCON_PORTA_PD_A3_VALUE_DISABLE << PORTCON_PORTA_PD_A3_SHIFT)\r\n#define PORTCON_PORTA_PD_A3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A3_BITS_ENABLE             (PORTCON_PORTA_PD_A3_VALUE_ENABLE << PORTCON_PORTA_PD_A3_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A4_SHIFT                   4\r\n#define PORTCON_PORTA_PD_A4_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A4_MASK                    (((1U << PORTCON_PORTA_PD_A4_WIDTH) - 1U) << PORTCON_PORTA_PD_A4_SHIFT)\r\n#define PORTCON_PORTA_PD_A4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A4_BITS_DISABLE            (PORTCON_PORTA_PD_A4_VALUE_DISABLE << PORTCON_PORTA_PD_A4_SHIFT)\r\n#define PORTCON_PORTA_PD_A4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A4_BITS_ENABLE             (PORTCON_PORTA_PD_A4_VALUE_ENABLE << PORTCON_PORTA_PD_A4_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A5_SHIFT                   5\r\n#define PORTCON_PORTA_PD_A5_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A5_MASK                    (((1U << PORTCON_PORTA_PD_A5_WIDTH) - 1U) << PORTCON_PORTA_PD_A5_SHIFT)\r\n#define PORTCON_PORTA_PD_A5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A5_BITS_DISABLE            (PORTCON_PORTA_PD_A5_VALUE_DISABLE << PORTCON_PORTA_PD_A5_SHIFT)\r\n#define PORTCON_PORTA_PD_A5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A5_BITS_ENABLE             (PORTCON_PORTA_PD_A5_VALUE_ENABLE << PORTCON_PORTA_PD_A5_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A6_SHIFT                   6\r\n#define PORTCON_PORTA_PD_A6_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A6_MASK                    (((1U << PORTCON_PORTA_PD_A6_WIDTH) - 1U) << PORTCON_PORTA_PD_A6_SHIFT)\r\n#define PORTCON_PORTA_PD_A6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A6_BITS_DISABLE            (PORTCON_PORTA_PD_A6_VALUE_DISABLE << PORTCON_PORTA_PD_A6_SHIFT)\r\n#define PORTCON_PORTA_PD_A6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A6_BITS_ENABLE             (PORTCON_PORTA_PD_A6_VALUE_ENABLE << PORTCON_PORTA_PD_A6_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A7_SHIFT                   7\r\n#define PORTCON_PORTA_PD_A7_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A7_MASK                    (((1U << PORTCON_PORTA_PD_A7_WIDTH) - 1U) << PORTCON_PORTA_PD_A7_SHIFT)\r\n#define PORTCON_PORTA_PD_A7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A7_BITS_DISABLE            (PORTCON_PORTA_PD_A7_VALUE_DISABLE << PORTCON_PORTA_PD_A7_SHIFT)\r\n#define PORTCON_PORTA_PD_A7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A7_BITS_ENABLE             (PORTCON_PORTA_PD_A7_VALUE_ENABLE << PORTCON_PORTA_PD_A7_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A8_SHIFT                   8\r\n#define PORTCON_PORTA_PD_A8_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A8_MASK                    (((1U << PORTCON_PORTA_PD_A8_WIDTH) - 1U) << PORTCON_PORTA_PD_A8_SHIFT)\r\n#define PORTCON_PORTA_PD_A8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A8_BITS_DISABLE            (PORTCON_PORTA_PD_A8_VALUE_DISABLE << PORTCON_PORTA_PD_A8_SHIFT)\r\n#define PORTCON_PORTA_PD_A8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A8_BITS_ENABLE             (PORTCON_PORTA_PD_A8_VALUE_ENABLE << PORTCON_PORTA_PD_A8_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A9_SHIFT                   9\r\n#define PORTCON_PORTA_PD_A9_WIDTH                   1\r\n#define PORTCON_PORTA_PD_A9_MASK                    (((1U << PORTCON_PORTA_PD_A9_WIDTH) - 1U) << PORTCON_PORTA_PD_A9_SHIFT)\r\n#define PORTCON_PORTA_PD_A9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_PD_A9_BITS_DISABLE            (PORTCON_PORTA_PD_A9_VALUE_DISABLE << PORTCON_PORTA_PD_A9_SHIFT)\r\n#define PORTCON_PORTA_PD_A9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_PD_A9_BITS_ENABLE             (PORTCON_PORTA_PD_A9_VALUE_ENABLE << PORTCON_PORTA_PD_A9_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A10_SHIFT                  10\r\n#define PORTCON_PORTA_PD_A10_WIDTH                  1\r\n#define PORTCON_PORTA_PD_A10_MASK                   (((1U << PORTCON_PORTA_PD_A10_WIDTH) - 1U) << PORTCON_PORTA_PD_A10_SHIFT)\r\n#define PORTCON_PORTA_PD_A10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PD_A10_BITS_DISABLE           (PORTCON_PORTA_PD_A10_VALUE_DISABLE << PORTCON_PORTA_PD_A10_SHIFT)\r\n#define PORTCON_PORTA_PD_A10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PD_A10_BITS_ENABLE            (PORTCON_PORTA_PD_A10_VALUE_ENABLE << PORTCON_PORTA_PD_A10_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A11_SHIFT                  11\r\n#define PORTCON_PORTA_PD_A11_WIDTH                  1\r\n#define PORTCON_PORTA_PD_A11_MASK                   (((1U << PORTCON_PORTA_PD_A11_WIDTH) - 1U) << PORTCON_PORTA_PD_A11_SHIFT)\r\n#define PORTCON_PORTA_PD_A11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PD_A11_BITS_DISABLE           (PORTCON_PORTA_PD_A11_VALUE_DISABLE << PORTCON_PORTA_PD_A11_SHIFT)\r\n#define PORTCON_PORTA_PD_A11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PD_A11_BITS_ENABLE            (PORTCON_PORTA_PD_A11_VALUE_ENABLE << PORTCON_PORTA_PD_A11_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A12_SHIFT                  12\r\n#define PORTCON_PORTA_PD_A12_WIDTH                  1\r\n#define PORTCON_PORTA_PD_A12_MASK                   (((1U << PORTCON_PORTA_PD_A12_WIDTH) - 1U) << PORTCON_PORTA_PD_A12_SHIFT)\r\n#define PORTCON_PORTA_PD_A12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PD_A12_BITS_DISABLE           (PORTCON_PORTA_PD_A12_VALUE_DISABLE << PORTCON_PORTA_PD_A12_SHIFT)\r\n#define PORTCON_PORTA_PD_A12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PD_A12_BITS_ENABLE            (PORTCON_PORTA_PD_A12_VALUE_ENABLE << PORTCON_PORTA_PD_A12_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A13_SHIFT                  13\r\n#define PORTCON_PORTA_PD_A13_WIDTH                  1\r\n#define PORTCON_PORTA_PD_A13_MASK                   (((1U << PORTCON_PORTA_PD_A13_WIDTH) - 1U) << PORTCON_PORTA_PD_A13_SHIFT)\r\n#define PORTCON_PORTA_PD_A13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PD_A13_BITS_DISABLE           (PORTCON_PORTA_PD_A13_VALUE_DISABLE << PORTCON_PORTA_PD_A13_SHIFT)\r\n#define PORTCON_PORTA_PD_A13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PD_A13_BITS_ENABLE            (PORTCON_PORTA_PD_A13_VALUE_ENABLE << PORTCON_PORTA_PD_A13_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A14_SHIFT                  14\r\n#define PORTCON_PORTA_PD_A14_WIDTH                  1\r\n#define PORTCON_PORTA_PD_A14_MASK                   (((1U << PORTCON_PORTA_PD_A14_WIDTH) - 1U) << PORTCON_PORTA_PD_A14_SHIFT)\r\n#define PORTCON_PORTA_PD_A14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PD_A14_BITS_DISABLE           (PORTCON_PORTA_PD_A14_VALUE_DISABLE << PORTCON_PORTA_PD_A14_SHIFT)\r\n#define PORTCON_PORTA_PD_A14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PD_A14_BITS_ENABLE            (PORTCON_PORTA_PD_A14_VALUE_ENABLE << PORTCON_PORTA_PD_A14_SHIFT)\r\n\r\n#define PORTCON_PORTA_PD_A15_SHIFT                  15\r\n#define PORTCON_PORTA_PD_A15_WIDTH                  1\r\n#define PORTCON_PORTA_PD_A15_MASK                   (((1U << PORTCON_PORTA_PD_A15_WIDTH) - 1U) << PORTCON_PORTA_PD_A15_SHIFT)\r\n#define PORTCON_PORTA_PD_A15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_PD_A15_BITS_DISABLE           (PORTCON_PORTA_PD_A15_VALUE_DISABLE << PORTCON_PORTA_PD_A15_SHIFT)\r\n#define PORTCON_PORTA_PD_A15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_PD_A15_BITS_ENABLE            (PORTCON_PORTA_PD_A15_VALUE_ENABLE << PORTCON_PORTA_PD_A15_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_ADDR                       (PORTCON_BASE_ADDR + 0x0304U)\r\n#define PORTCON_PORTB_PD                            (*(volatile uint32_t *)PORTCON_PORTB_PD_ADDR)\r\n#define PORTCON_PORTB_PD_B0_SHIFT                   0\r\n#define PORTCON_PORTB_PD_B0_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B0_MASK                    (((1U << PORTCON_PORTB_PD_B0_WIDTH) - 1U) << PORTCON_PORTB_PD_B0_SHIFT)\r\n#define PORTCON_PORTB_PD_B0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B0_BITS_DISABLE            (PORTCON_PORTB_PD_B0_VALUE_DISABLE << PORTCON_PORTB_PD_B0_SHIFT)\r\n#define PORTCON_PORTB_PD_B0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B0_BITS_ENABLE             (PORTCON_PORTB_PD_B0_VALUE_ENABLE << PORTCON_PORTB_PD_B0_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B1_SHIFT                   1\r\n#define PORTCON_PORTB_PD_B1_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B1_MASK                    (((1U << PORTCON_PORTB_PD_B1_WIDTH) - 1U) << PORTCON_PORTB_PD_B1_SHIFT)\r\n#define PORTCON_PORTB_PD_B1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B1_BITS_DISABLE            (PORTCON_PORTB_PD_B1_VALUE_DISABLE << PORTCON_PORTB_PD_B1_SHIFT)\r\n#define PORTCON_PORTB_PD_B1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B1_BITS_ENABLE             (PORTCON_PORTB_PD_B1_VALUE_ENABLE << PORTCON_PORTB_PD_B1_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B2_SHIFT                   2\r\n#define PORTCON_PORTB_PD_B2_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B2_MASK                    (((1U << PORTCON_PORTB_PD_B2_WIDTH) - 1U) << PORTCON_PORTB_PD_B2_SHIFT)\r\n#define PORTCON_PORTB_PD_B2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B2_BITS_DISABLE            (PORTCON_PORTB_PD_B2_VALUE_DISABLE << PORTCON_PORTB_PD_B2_SHIFT)\r\n#define PORTCON_PORTB_PD_B2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B2_BITS_ENABLE             (PORTCON_PORTB_PD_B2_VALUE_ENABLE << PORTCON_PORTB_PD_B2_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B3_SHIFT                   3\r\n#define PORTCON_PORTB_PD_B3_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B3_MASK                    (((1U << PORTCON_PORTB_PD_B3_WIDTH) - 1U) << PORTCON_PORTB_PD_B3_SHIFT)\r\n#define PORTCON_PORTB_PD_B3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B3_BITS_DISABLE            (PORTCON_PORTB_PD_B3_VALUE_DISABLE << PORTCON_PORTB_PD_B3_SHIFT)\r\n#define PORTCON_PORTB_PD_B3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B3_BITS_ENABLE             (PORTCON_PORTB_PD_B3_VALUE_ENABLE << PORTCON_PORTB_PD_B3_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B4_SHIFT                   4\r\n#define PORTCON_PORTB_PD_B4_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B4_MASK                    (((1U << PORTCON_PORTB_PD_B4_WIDTH) - 1U) << PORTCON_PORTB_PD_B4_SHIFT)\r\n#define PORTCON_PORTB_PD_B4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B4_BITS_DISABLE            (PORTCON_PORTB_PD_B4_VALUE_DISABLE << PORTCON_PORTB_PD_B4_SHIFT)\r\n#define PORTCON_PORTB_PD_B4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B4_BITS_ENABLE             (PORTCON_PORTB_PD_B4_VALUE_ENABLE << PORTCON_PORTB_PD_B4_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B5_SHIFT                   5\r\n#define PORTCON_PORTB_PD_B5_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B5_MASK                    (((1U << PORTCON_PORTB_PD_B5_WIDTH) - 1U) << PORTCON_PORTB_PD_B5_SHIFT)\r\n#define PORTCON_PORTB_PD_B5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B5_BITS_DISABLE            (PORTCON_PORTB_PD_B5_VALUE_DISABLE << PORTCON_PORTB_PD_B5_SHIFT)\r\n#define PORTCON_PORTB_PD_B5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B5_BITS_ENABLE             (PORTCON_PORTB_PD_B5_VALUE_ENABLE << PORTCON_PORTB_PD_B5_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B6_SHIFT                   6\r\n#define PORTCON_PORTB_PD_B6_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B6_MASK                    (((1U << PORTCON_PORTB_PD_B6_WIDTH) - 1U) << PORTCON_PORTB_PD_B6_SHIFT)\r\n#define PORTCON_PORTB_PD_B6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B6_BITS_DISABLE            (PORTCON_PORTB_PD_B6_VALUE_DISABLE << PORTCON_PORTB_PD_B6_SHIFT)\r\n#define PORTCON_PORTB_PD_B6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B6_BITS_ENABLE             (PORTCON_PORTB_PD_B6_VALUE_ENABLE << PORTCON_PORTB_PD_B6_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B7_SHIFT                   7\r\n#define PORTCON_PORTB_PD_B7_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B7_MASK                    (((1U << PORTCON_PORTB_PD_B7_WIDTH) - 1U) << PORTCON_PORTB_PD_B7_SHIFT)\r\n#define PORTCON_PORTB_PD_B7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B7_BITS_DISABLE            (PORTCON_PORTB_PD_B7_VALUE_DISABLE << PORTCON_PORTB_PD_B7_SHIFT)\r\n#define PORTCON_PORTB_PD_B7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B7_BITS_ENABLE             (PORTCON_PORTB_PD_B7_VALUE_ENABLE << PORTCON_PORTB_PD_B7_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B8_SHIFT                   8\r\n#define PORTCON_PORTB_PD_B8_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B8_MASK                    (((1U << PORTCON_PORTB_PD_B8_WIDTH) - 1U) << PORTCON_PORTB_PD_B8_SHIFT)\r\n#define PORTCON_PORTB_PD_B8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B8_BITS_DISABLE            (PORTCON_PORTB_PD_B8_VALUE_DISABLE << PORTCON_PORTB_PD_B8_SHIFT)\r\n#define PORTCON_PORTB_PD_B8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B8_BITS_ENABLE             (PORTCON_PORTB_PD_B8_VALUE_ENABLE << PORTCON_PORTB_PD_B8_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B9_SHIFT                   9\r\n#define PORTCON_PORTB_PD_B9_WIDTH                   1\r\n#define PORTCON_PORTB_PD_B9_MASK                    (((1U << PORTCON_PORTB_PD_B9_WIDTH) - 1U) << PORTCON_PORTB_PD_B9_SHIFT)\r\n#define PORTCON_PORTB_PD_B9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_PD_B9_BITS_DISABLE            (PORTCON_PORTB_PD_B9_VALUE_DISABLE << PORTCON_PORTB_PD_B9_SHIFT)\r\n#define PORTCON_PORTB_PD_B9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_PD_B9_BITS_ENABLE             (PORTCON_PORTB_PD_B9_VALUE_ENABLE << PORTCON_PORTB_PD_B9_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B10_SHIFT                  10\r\n#define PORTCON_PORTB_PD_B10_WIDTH                  1\r\n#define PORTCON_PORTB_PD_B10_MASK                   (((1U << PORTCON_PORTB_PD_B10_WIDTH) - 1U) << PORTCON_PORTB_PD_B10_SHIFT)\r\n#define PORTCON_PORTB_PD_B10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PD_B10_BITS_DISABLE           (PORTCON_PORTB_PD_B10_VALUE_DISABLE << PORTCON_PORTB_PD_B10_SHIFT)\r\n#define PORTCON_PORTB_PD_B10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PD_B10_BITS_ENABLE            (PORTCON_PORTB_PD_B10_VALUE_ENABLE << PORTCON_PORTB_PD_B10_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B11_SHIFT                  11\r\n#define PORTCON_PORTB_PD_B11_WIDTH                  1\r\n#define PORTCON_PORTB_PD_B11_MASK                   (((1U << PORTCON_PORTB_PD_B11_WIDTH) - 1U) << PORTCON_PORTB_PD_B11_SHIFT)\r\n#define PORTCON_PORTB_PD_B11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PD_B11_BITS_DISABLE           (PORTCON_PORTB_PD_B11_VALUE_DISABLE << PORTCON_PORTB_PD_B11_SHIFT)\r\n#define PORTCON_PORTB_PD_B11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PD_B11_BITS_ENABLE            (PORTCON_PORTB_PD_B11_VALUE_ENABLE << PORTCON_PORTB_PD_B11_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B12_SHIFT                  12\r\n#define PORTCON_PORTB_PD_B12_WIDTH                  1\r\n#define PORTCON_PORTB_PD_B12_MASK                   (((1U << PORTCON_PORTB_PD_B12_WIDTH) - 1U) << PORTCON_PORTB_PD_B12_SHIFT)\r\n#define PORTCON_PORTB_PD_B12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PD_B12_BITS_DISABLE           (PORTCON_PORTB_PD_B12_VALUE_DISABLE << PORTCON_PORTB_PD_B12_SHIFT)\r\n#define PORTCON_PORTB_PD_B12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PD_B12_BITS_ENABLE            (PORTCON_PORTB_PD_B12_VALUE_ENABLE << PORTCON_PORTB_PD_B12_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B13_SHIFT                  13\r\n#define PORTCON_PORTB_PD_B13_WIDTH                  1\r\n#define PORTCON_PORTB_PD_B13_MASK                   (((1U << PORTCON_PORTB_PD_B13_WIDTH) - 1U) << PORTCON_PORTB_PD_B13_SHIFT)\r\n#define PORTCON_PORTB_PD_B13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PD_B13_BITS_DISABLE           (PORTCON_PORTB_PD_B13_VALUE_DISABLE << PORTCON_PORTB_PD_B13_SHIFT)\r\n#define PORTCON_PORTB_PD_B13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PD_B13_BITS_ENABLE            (PORTCON_PORTB_PD_B13_VALUE_ENABLE << PORTCON_PORTB_PD_B13_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B14_SHIFT                  14\r\n#define PORTCON_PORTB_PD_B14_WIDTH                  1\r\n#define PORTCON_PORTB_PD_B14_MASK                   (((1U << PORTCON_PORTB_PD_B14_WIDTH) - 1U) << PORTCON_PORTB_PD_B14_SHIFT)\r\n#define PORTCON_PORTB_PD_B14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PD_B14_BITS_DISABLE           (PORTCON_PORTB_PD_B14_VALUE_DISABLE << PORTCON_PORTB_PD_B14_SHIFT)\r\n#define PORTCON_PORTB_PD_B14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PD_B14_BITS_ENABLE            (PORTCON_PORTB_PD_B14_VALUE_ENABLE << PORTCON_PORTB_PD_B14_SHIFT)\r\n\r\n#define PORTCON_PORTB_PD_B15_SHIFT                  15\r\n#define PORTCON_PORTB_PD_B15_WIDTH                  1\r\n#define PORTCON_PORTB_PD_B15_MASK                   (((1U << PORTCON_PORTB_PD_B15_WIDTH) - 1U) << PORTCON_PORTB_PD_B15_SHIFT)\r\n#define PORTCON_PORTB_PD_B15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_PD_B15_BITS_DISABLE           (PORTCON_PORTB_PD_B15_VALUE_DISABLE << PORTCON_PORTB_PD_B15_SHIFT)\r\n#define PORTCON_PORTB_PD_B15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_PD_B15_BITS_ENABLE            (PORTCON_PORTB_PD_B15_VALUE_ENABLE << PORTCON_PORTB_PD_B15_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_ADDR                       (PORTCON_BASE_ADDR + 0x0308U)\r\n#define PORTCON_PORTC_PD                            (*(volatile uint32_t *)PORTCON_PORTC_PD_ADDR)\r\n#define PORTCON_PORTC_PD_C0_SHIFT                   0\r\n#define PORTCON_PORTC_PD_C0_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C0_MASK                    (((1U << PORTCON_PORTC_PD_C0_WIDTH) - 1U) << PORTCON_PORTC_PD_C0_SHIFT)\r\n#define PORTCON_PORTC_PD_C0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C0_BITS_DISABLE            (PORTCON_PORTC_PD_C0_VALUE_DISABLE << PORTCON_PORTC_PD_C0_SHIFT)\r\n#define PORTCON_PORTC_PD_C0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C0_BITS_ENABLE             (PORTCON_PORTC_PD_C0_VALUE_ENABLE << PORTCON_PORTC_PD_C0_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C1_SHIFT                   1\r\n#define PORTCON_PORTC_PD_C1_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C1_MASK                    (((1U << PORTCON_PORTC_PD_C1_WIDTH) - 1U) << PORTCON_PORTC_PD_C1_SHIFT)\r\n#define PORTCON_PORTC_PD_C1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C1_BITS_DISABLE            (PORTCON_PORTC_PD_C1_VALUE_DISABLE << PORTCON_PORTC_PD_C1_SHIFT)\r\n#define PORTCON_PORTC_PD_C1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C1_BITS_ENABLE             (PORTCON_PORTC_PD_C1_VALUE_ENABLE << PORTCON_PORTC_PD_C1_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C2_SHIFT                   2\r\n#define PORTCON_PORTC_PD_C2_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C2_MASK                    (((1U << PORTCON_PORTC_PD_C2_WIDTH) - 1U) << PORTCON_PORTC_PD_C2_SHIFT)\r\n#define PORTCON_PORTC_PD_C2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C2_BITS_DISABLE            (PORTCON_PORTC_PD_C2_VALUE_DISABLE << PORTCON_PORTC_PD_C2_SHIFT)\r\n#define PORTCON_PORTC_PD_C2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C2_BITS_ENABLE             (PORTCON_PORTC_PD_C2_VALUE_ENABLE << PORTCON_PORTC_PD_C2_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C3_SHIFT                   3\r\n#define PORTCON_PORTC_PD_C3_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C3_MASK                    (((1U << PORTCON_PORTC_PD_C3_WIDTH) - 1U) << PORTCON_PORTC_PD_C3_SHIFT)\r\n#define PORTCON_PORTC_PD_C3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C3_BITS_DISABLE            (PORTCON_PORTC_PD_C3_VALUE_DISABLE << PORTCON_PORTC_PD_C3_SHIFT)\r\n#define PORTCON_PORTC_PD_C3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C3_BITS_ENABLE             (PORTCON_PORTC_PD_C3_VALUE_ENABLE << PORTCON_PORTC_PD_C3_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C4_SHIFT                   4\r\n#define PORTCON_PORTC_PD_C4_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C4_MASK                    (((1U << PORTCON_PORTC_PD_C4_WIDTH) - 1U) << PORTCON_PORTC_PD_C4_SHIFT)\r\n#define PORTCON_PORTC_PD_C4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C4_BITS_DISABLE            (PORTCON_PORTC_PD_C4_VALUE_DISABLE << PORTCON_PORTC_PD_C4_SHIFT)\r\n#define PORTCON_PORTC_PD_C4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C4_BITS_ENABLE             (PORTCON_PORTC_PD_C4_VALUE_ENABLE << PORTCON_PORTC_PD_C4_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C5_SHIFT                   5\r\n#define PORTCON_PORTC_PD_C5_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C5_MASK                    (((1U << PORTCON_PORTC_PD_C5_WIDTH) - 1U) << PORTCON_PORTC_PD_C5_SHIFT)\r\n#define PORTCON_PORTC_PD_C5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C5_BITS_DISABLE            (PORTCON_PORTC_PD_C5_VALUE_DISABLE << PORTCON_PORTC_PD_C5_SHIFT)\r\n#define PORTCON_PORTC_PD_C5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C5_BITS_ENABLE             (PORTCON_PORTC_PD_C5_VALUE_ENABLE << PORTCON_PORTC_PD_C5_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C6_SHIFT                   6\r\n#define PORTCON_PORTC_PD_C6_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C6_MASK                    (((1U << PORTCON_PORTC_PD_C6_WIDTH) - 1U) << PORTCON_PORTC_PD_C6_SHIFT)\r\n#define PORTCON_PORTC_PD_C6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C6_BITS_DISABLE            (PORTCON_PORTC_PD_C6_VALUE_DISABLE << PORTCON_PORTC_PD_C6_SHIFT)\r\n#define PORTCON_PORTC_PD_C6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C6_BITS_ENABLE             (PORTCON_PORTC_PD_C6_VALUE_ENABLE << PORTCON_PORTC_PD_C6_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C7_SHIFT                   7\r\n#define PORTCON_PORTC_PD_C7_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C7_MASK                    (((1U << PORTCON_PORTC_PD_C7_WIDTH) - 1U) << PORTCON_PORTC_PD_C7_SHIFT)\r\n#define PORTCON_PORTC_PD_C7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C7_BITS_DISABLE            (PORTCON_PORTC_PD_C7_VALUE_DISABLE << PORTCON_PORTC_PD_C7_SHIFT)\r\n#define PORTCON_PORTC_PD_C7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C7_BITS_ENABLE             (PORTCON_PORTC_PD_C7_VALUE_ENABLE << PORTCON_PORTC_PD_C7_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C8_SHIFT                   8\r\n#define PORTCON_PORTC_PD_C8_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C8_MASK                    (((1U << PORTCON_PORTC_PD_C8_WIDTH) - 1U) << PORTCON_PORTC_PD_C8_SHIFT)\r\n#define PORTCON_PORTC_PD_C8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C8_BITS_DISABLE            (PORTCON_PORTC_PD_C8_VALUE_DISABLE << PORTCON_PORTC_PD_C8_SHIFT)\r\n#define PORTCON_PORTC_PD_C8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C8_BITS_ENABLE             (PORTCON_PORTC_PD_C8_VALUE_ENABLE << PORTCON_PORTC_PD_C8_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C9_SHIFT                   9\r\n#define PORTCON_PORTC_PD_C9_WIDTH                   1\r\n#define PORTCON_PORTC_PD_C9_MASK                    (((1U << PORTCON_PORTC_PD_C9_WIDTH) - 1U) << PORTCON_PORTC_PD_C9_SHIFT)\r\n#define PORTCON_PORTC_PD_C9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_PD_C9_BITS_DISABLE            (PORTCON_PORTC_PD_C9_VALUE_DISABLE << PORTCON_PORTC_PD_C9_SHIFT)\r\n#define PORTCON_PORTC_PD_C9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_PD_C9_BITS_ENABLE             (PORTCON_PORTC_PD_C9_VALUE_ENABLE << PORTCON_PORTC_PD_C9_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C10_SHIFT                  10\r\n#define PORTCON_PORTC_PD_C10_WIDTH                  1\r\n#define PORTCON_PORTC_PD_C10_MASK                   (((1U << PORTCON_PORTC_PD_C10_WIDTH) - 1U) << PORTCON_PORTC_PD_C10_SHIFT)\r\n#define PORTCON_PORTC_PD_C10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PD_C10_BITS_DISABLE           (PORTCON_PORTC_PD_C10_VALUE_DISABLE << PORTCON_PORTC_PD_C10_SHIFT)\r\n#define PORTCON_PORTC_PD_C10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PD_C10_BITS_ENABLE            (PORTCON_PORTC_PD_C10_VALUE_ENABLE << PORTCON_PORTC_PD_C10_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C11_SHIFT                  11\r\n#define PORTCON_PORTC_PD_C11_WIDTH                  1\r\n#define PORTCON_PORTC_PD_C11_MASK                   (((1U << PORTCON_PORTC_PD_C11_WIDTH) - 1U) << PORTCON_PORTC_PD_C11_SHIFT)\r\n#define PORTCON_PORTC_PD_C11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PD_C11_BITS_DISABLE           (PORTCON_PORTC_PD_C11_VALUE_DISABLE << PORTCON_PORTC_PD_C11_SHIFT)\r\n#define PORTCON_PORTC_PD_C11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PD_C11_BITS_ENABLE            (PORTCON_PORTC_PD_C11_VALUE_ENABLE << PORTCON_PORTC_PD_C11_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C12_SHIFT                  12\r\n#define PORTCON_PORTC_PD_C12_WIDTH                  1\r\n#define PORTCON_PORTC_PD_C12_MASK                   (((1U << PORTCON_PORTC_PD_C12_WIDTH) - 1U) << PORTCON_PORTC_PD_C12_SHIFT)\r\n#define PORTCON_PORTC_PD_C12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PD_C12_BITS_DISABLE           (PORTCON_PORTC_PD_C12_VALUE_DISABLE << PORTCON_PORTC_PD_C12_SHIFT)\r\n#define PORTCON_PORTC_PD_C12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PD_C12_BITS_ENABLE            (PORTCON_PORTC_PD_C12_VALUE_ENABLE << PORTCON_PORTC_PD_C12_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C13_SHIFT                  13\r\n#define PORTCON_PORTC_PD_C13_WIDTH                  1\r\n#define PORTCON_PORTC_PD_C13_MASK                   (((1U << PORTCON_PORTC_PD_C13_WIDTH) - 1U) << PORTCON_PORTC_PD_C13_SHIFT)\r\n#define PORTCON_PORTC_PD_C13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PD_C13_BITS_DISABLE           (PORTCON_PORTC_PD_C13_VALUE_DISABLE << PORTCON_PORTC_PD_C13_SHIFT)\r\n#define PORTCON_PORTC_PD_C13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PD_C13_BITS_ENABLE            (PORTCON_PORTC_PD_C13_VALUE_ENABLE << PORTCON_PORTC_PD_C13_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C14_SHIFT                  14\r\n#define PORTCON_PORTC_PD_C14_WIDTH                  1\r\n#define PORTCON_PORTC_PD_C14_MASK                   (((1U << PORTCON_PORTC_PD_C14_WIDTH) - 1U) << PORTCON_PORTC_PD_C14_SHIFT)\r\n#define PORTCON_PORTC_PD_C14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PD_C14_BITS_DISABLE           (PORTCON_PORTC_PD_C14_VALUE_DISABLE << PORTCON_PORTC_PD_C14_SHIFT)\r\n#define PORTCON_PORTC_PD_C14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PD_C14_BITS_ENABLE            (PORTCON_PORTC_PD_C14_VALUE_ENABLE << PORTCON_PORTC_PD_C14_SHIFT)\r\n\r\n#define PORTCON_PORTC_PD_C15_SHIFT                  15\r\n#define PORTCON_PORTC_PD_C15_WIDTH                  1\r\n#define PORTCON_PORTC_PD_C15_MASK                   (((1U << PORTCON_PORTC_PD_C15_WIDTH) - 1U) << PORTCON_PORTC_PD_C15_SHIFT)\r\n#define PORTCON_PORTC_PD_C15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_PD_C15_BITS_DISABLE           (PORTCON_PORTC_PD_C15_VALUE_DISABLE << PORTCON_PORTC_PD_C15_SHIFT)\r\n#define PORTCON_PORTC_PD_C15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_PD_C15_BITS_ENABLE            (PORTCON_PORTC_PD_C15_VALUE_ENABLE << PORTCON_PORTC_PD_C15_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_ADDR                       (PORTCON_BASE_ADDR + 0x0400U)\r\n#define PORTCON_PORTA_OD                            (*(volatile uint32_t *)PORTCON_PORTA_OD_ADDR)\r\n#define PORTCON_PORTA_OD_A0_SHIFT                   0\r\n#define PORTCON_PORTA_OD_A0_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A0_MASK                    (((1U << PORTCON_PORTA_OD_A0_WIDTH) - 1U) << PORTCON_PORTA_OD_A0_SHIFT)\r\n#define PORTCON_PORTA_OD_A0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A0_BITS_DISABLE            (PORTCON_PORTA_OD_A0_VALUE_DISABLE << PORTCON_PORTA_OD_A0_SHIFT)\r\n#define PORTCON_PORTA_OD_A0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A0_BITS_ENABLE             (PORTCON_PORTA_OD_A0_VALUE_ENABLE << PORTCON_PORTA_OD_A0_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A1_SHIFT                   1\r\n#define PORTCON_PORTA_OD_A1_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A1_MASK                    (((1U << PORTCON_PORTA_OD_A1_WIDTH) - 1U) << PORTCON_PORTA_OD_A1_SHIFT)\r\n#define PORTCON_PORTA_OD_A1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A1_BITS_DISABLE            (PORTCON_PORTA_OD_A1_VALUE_DISABLE << PORTCON_PORTA_OD_A1_SHIFT)\r\n#define PORTCON_PORTA_OD_A1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A1_BITS_ENABLE             (PORTCON_PORTA_OD_A1_VALUE_ENABLE << PORTCON_PORTA_OD_A1_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A2_SHIFT                   2\r\n#define PORTCON_PORTA_OD_A2_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A2_MASK                    (((1U << PORTCON_PORTA_OD_A2_WIDTH) - 1U) << PORTCON_PORTA_OD_A2_SHIFT)\r\n#define PORTCON_PORTA_OD_A2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A2_BITS_DISABLE            (PORTCON_PORTA_OD_A2_VALUE_DISABLE << PORTCON_PORTA_OD_A2_SHIFT)\r\n#define PORTCON_PORTA_OD_A2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A2_BITS_ENABLE             (PORTCON_PORTA_OD_A2_VALUE_ENABLE << PORTCON_PORTA_OD_A2_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A3_SHIFT                   3\r\n#define PORTCON_PORTA_OD_A3_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A3_MASK                    (((1U << PORTCON_PORTA_OD_A3_WIDTH) - 1U) << PORTCON_PORTA_OD_A3_SHIFT)\r\n#define PORTCON_PORTA_OD_A3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A3_BITS_DISABLE            (PORTCON_PORTA_OD_A3_VALUE_DISABLE << PORTCON_PORTA_OD_A3_SHIFT)\r\n#define PORTCON_PORTA_OD_A3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A3_BITS_ENABLE             (PORTCON_PORTA_OD_A3_VALUE_ENABLE << PORTCON_PORTA_OD_A3_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A4_SHIFT                   4\r\n#define PORTCON_PORTA_OD_A4_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A4_MASK                    (((1U << PORTCON_PORTA_OD_A4_WIDTH) - 1U) << PORTCON_PORTA_OD_A4_SHIFT)\r\n#define PORTCON_PORTA_OD_A4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A4_BITS_DISABLE            (PORTCON_PORTA_OD_A4_VALUE_DISABLE << PORTCON_PORTA_OD_A4_SHIFT)\r\n#define PORTCON_PORTA_OD_A4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A4_BITS_ENABLE             (PORTCON_PORTA_OD_A4_VALUE_ENABLE << PORTCON_PORTA_OD_A4_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A5_SHIFT                   5\r\n#define PORTCON_PORTA_OD_A5_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A5_MASK                    (((1U << PORTCON_PORTA_OD_A5_WIDTH) - 1U) << PORTCON_PORTA_OD_A5_SHIFT)\r\n#define PORTCON_PORTA_OD_A5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A5_BITS_DISABLE            (PORTCON_PORTA_OD_A5_VALUE_DISABLE << PORTCON_PORTA_OD_A5_SHIFT)\r\n#define PORTCON_PORTA_OD_A5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A5_BITS_ENABLE             (PORTCON_PORTA_OD_A5_VALUE_ENABLE << PORTCON_PORTA_OD_A5_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A6_SHIFT                   6\r\n#define PORTCON_PORTA_OD_A6_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A6_MASK                    (((1U << PORTCON_PORTA_OD_A6_WIDTH) - 1U) << PORTCON_PORTA_OD_A6_SHIFT)\r\n#define PORTCON_PORTA_OD_A6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A6_BITS_DISABLE            (PORTCON_PORTA_OD_A6_VALUE_DISABLE << PORTCON_PORTA_OD_A6_SHIFT)\r\n#define PORTCON_PORTA_OD_A6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A6_BITS_ENABLE             (PORTCON_PORTA_OD_A6_VALUE_ENABLE << PORTCON_PORTA_OD_A6_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A7_SHIFT                   7\r\n#define PORTCON_PORTA_OD_A7_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A7_MASK                    (((1U << PORTCON_PORTA_OD_A7_WIDTH) - 1U) << PORTCON_PORTA_OD_A7_SHIFT)\r\n#define PORTCON_PORTA_OD_A7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A7_BITS_DISABLE            (PORTCON_PORTA_OD_A7_VALUE_DISABLE << PORTCON_PORTA_OD_A7_SHIFT)\r\n#define PORTCON_PORTA_OD_A7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A7_BITS_ENABLE             (PORTCON_PORTA_OD_A7_VALUE_ENABLE << PORTCON_PORTA_OD_A7_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A8_SHIFT                   8\r\n#define PORTCON_PORTA_OD_A8_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A8_MASK                    (((1U << PORTCON_PORTA_OD_A8_WIDTH) - 1U) << PORTCON_PORTA_OD_A8_SHIFT)\r\n#define PORTCON_PORTA_OD_A8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A8_BITS_DISABLE            (PORTCON_PORTA_OD_A8_VALUE_DISABLE << PORTCON_PORTA_OD_A8_SHIFT)\r\n#define PORTCON_PORTA_OD_A8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A8_BITS_ENABLE             (PORTCON_PORTA_OD_A8_VALUE_ENABLE << PORTCON_PORTA_OD_A8_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A9_SHIFT                   9\r\n#define PORTCON_PORTA_OD_A9_WIDTH                   1\r\n#define PORTCON_PORTA_OD_A9_MASK                    (((1U << PORTCON_PORTA_OD_A9_WIDTH) - 1U) << PORTCON_PORTA_OD_A9_SHIFT)\r\n#define PORTCON_PORTA_OD_A9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTA_OD_A9_BITS_DISABLE            (PORTCON_PORTA_OD_A9_VALUE_DISABLE << PORTCON_PORTA_OD_A9_SHIFT)\r\n#define PORTCON_PORTA_OD_A9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTA_OD_A9_BITS_ENABLE             (PORTCON_PORTA_OD_A9_VALUE_ENABLE << PORTCON_PORTA_OD_A9_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A10_SHIFT                  10\r\n#define PORTCON_PORTA_OD_A10_WIDTH                  1\r\n#define PORTCON_PORTA_OD_A10_MASK                   (((1U << PORTCON_PORTA_OD_A10_WIDTH) - 1U) << PORTCON_PORTA_OD_A10_SHIFT)\r\n#define PORTCON_PORTA_OD_A10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_OD_A10_BITS_DISABLE           (PORTCON_PORTA_OD_A10_VALUE_DISABLE << PORTCON_PORTA_OD_A10_SHIFT)\r\n#define PORTCON_PORTA_OD_A10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_OD_A10_BITS_ENABLE            (PORTCON_PORTA_OD_A10_VALUE_ENABLE << PORTCON_PORTA_OD_A10_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A11_SHIFT                  11\r\n#define PORTCON_PORTA_OD_A11_WIDTH                  1\r\n#define PORTCON_PORTA_OD_A11_MASK                   (((1U << PORTCON_PORTA_OD_A11_WIDTH) - 1U) << PORTCON_PORTA_OD_A11_SHIFT)\r\n#define PORTCON_PORTA_OD_A11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_OD_A11_BITS_DISABLE           (PORTCON_PORTA_OD_A11_VALUE_DISABLE << PORTCON_PORTA_OD_A11_SHIFT)\r\n#define PORTCON_PORTA_OD_A11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_OD_A11_BITS_ENABLE            (PORTCON_PORTA_OD_A11_VALUE_ENABLE << PORTCON_PORTA_OD_A11_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A12_SHIFT                  12\r\n#define PORTCON_PORTA_OD_A12_WIDTH                  1\r\n#define PORTCON_PORTA_OD_A12_MASK                   (((1U << PORTCON_PORTA_OD_A12_WIDTH) - 1U) << PORTCON_PORTA_OD_A12_SHIFT)\r\n#define PORTCON_PORTA_OD_A12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_OD_A12_BITS_DISABLE           (PORTCON_PORTA_OD_A12_VALUE_DISABLE << PORTCON_PORTA_OD_A12_SHIFT)\r\n#define PORTCON_PORTA_OD_A12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_OD_A12_BITS_ENABLE            (PORTCON_PORTA_OD_A12_VALUE_ENABLE << PORTCON_PORTA_OD_A12_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A13_SHIFT                  13\r\n#define PORTCON_PORTA_OD_A13_WIDTH                  1\r\n#define PORTCON_PORTA_OD_A13_MASK                   (((1U << PORTCON_PORTA_OD_A13_WIDTH) - 1U) << PORTCON_PORTA_OD_A13_SHIFT)\r\n#define PORTCON_PORTA_OD_A13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_OD_A13_BITS_DISABLE           (PORTCON_PORTA_OD_A13_VALUE_DISABLE << PORTCON_PORTA_OD_A13_SHIFT)\r\n#define PORTCON_PORTA_OD_A13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_OD_A13_BITS_ENABLE            (PORTCON_PORTA_OD_A13_VALUE_ENABLE << PORTCON_PORTA_OD_A13_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A14_SHIFT                  14\r\n#define PORTCON_PORTA_OD_A14_WIDTH                  1\r\n#define PORTCON_PORTA_OD_A14_MASK                   (((1U << PORTCON_PORTA_OD_A14_WIDTH) - 1U) << PORTCON_PORTA_OD_A14_SHIFT)\r\n#define PORTCON_PORTA_OD_A14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_OD_A14_BITS_DISABLE           (PORTCON_PORTA_OD_A14_VALUE_DISABLE << PORTCON_PORTA_OD_A14_SHIFT)\r\n#define PORTCON_PORTA_OD_A14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_OD_A14_BITS_ENABLE            (PORTCON_PORTA_OD_A14_VALUE_ENABLE << PORTCON_PORTA_OD_A14_SHIFT)\r\n\r\n#define PORTCON_PORTA_OD_A15_SHIFT                  15\r\n#define PORTCON_PORTA_OD_A15_WIDTH                  1\r\n#define PORTCON_PORTA_OD_A15_MASK                   (((1U << PORTCON_PORTA_OD_A15_WIDTH) - 1U) << PORTCON_PORTA_OD_A15_SHIFT)\r\n#define PORTCON_PORTA_OD_A15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTA_OD_A15_BITS_DISABLE           (PORTCON_PORTA_OD_A15_VALUE_DISABLE << PORTCON_PORTA_OD_A15_SHIFT)\r\n#define PORTCON_PORTA_OD_A15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTA_OD_A15_BITS_ENABLE            (PORTCON_PORTA_OD_A15_VALUE_ENABLE << PORTCON_PORTA_OD_A15_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_ADDR                       (PORTCON_BASE_ADDR + 0x0404U)\r\n#define PORTCON_PORTB_OD                            (*(volatile uint32_t *)PORTCON_PORTB_OD_ADDR)\r\n#define PORTCON_PORTB_OD_B0_SHIFT                   0\r\n#define PORTCON_PORTB_OD_B0_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B0_MASK                    (((1U << PORTCON_PORTB_OD_B0_WIDTH) - 1U) << PORTCON_PORTB_OD_B0_SHIFT)\r\n#define PORTCON_PORTB_OD_B0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B0_BITS_DISABLE            (PORTCON_PORTB_OD_B0_VALUE_DISABLE << PORTCON_PORTB_OD_B0_SHIFT)\r\n#define PORTCON_PORTB_OD_B0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B0_BITS_ENABLE             (PORTCON_PORTB_OD_B0_VALUE_ENABLE << PORTCON_PORTB_OD_B0_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B1_SHIFT                   1\r\n#define PORTCON_PORTB_OD_B1_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B1_MASK                    (((1U << PORTCON_PORTB_OD_B1_WIDTH) - 1U) << PORTCON_PORTB_OD_B1_SHIFT)\r\n#define PORTCON_PORTB_OD_B1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B1_BITS_DISABLE            (PORTCON_PORTB_OD_B1_VALUE_DISABLE << PORTCON_PORTB_OD_B1_SHIFT)\r\n#define PORTCON_PORTB_OD_B1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B1_BITS_ENABLE             (PORTCON_PORTB_OD_B1_VALUE_ENABLE << PORTCON_PORTB_OD_B1_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B2_SHIFT                   2\r\n#define PORTCON_PORTB_OD_B2_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B2_MASK                    (((1U << PORTCON_PORTB_OD_B2_WIDTH) - 1U) << PORTCON_PORTB_OD_B2_SHIFT)\r\n#define PORTCON_PORTB_OD_B2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B2_BITS_DISABLE            (PORTCON_PORTB_OD_B2_VALUE_DISABLE << PORTCON_PORTB_OD_B2_SHIFT)\r\n#define PORTCON_PORTB_OD_B2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B2_BITS_ENABLE             (PORTCON_PORTB_OD_B2_VALUE_ENABLE << PORTCON_PORTB_OD_B2_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B3_SHIFT                   3\r\n#define PORTCON_PORTB_OD_B3_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B3_MASK                    (((1U << PORTCON_PORTB_OD_B3_WIDTH) - 1U) << PORTCON_PORTB_OD_B3_SHIFT)\r\n#define PORTCON_PORTB_OD_B3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B3_BITS_DISABLE            (PORTCON_PORTB_OD_B3_VALUE_DISABLE << PORTCON_PORTB_OD_B3_SHIFT)\r\n#define PORTCON_PORTB_OD_B3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B3_BITS_ENABLE             (PORTCON_PORTB_OD_B3_VALUE_ENABLE << PORTCON_PORTB_OD_B3_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B4_SHIFT                   4\r\n#define PORTCON_PORTB_OD_B4_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B4_MASK                    (((1U << PORTCON_PORTB_OD_B4_WIDTH) - 1U) << PORTCON_PORTB_OD_B4_SHIFT)\r\n#define PORTCON_PORTB_OD_B4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B4_BITS_DISABLE            (PORTCON_PORTB_OD_B4_VALUE_DISABLE << PORTCON_PORTB_OD_B4_SHIFT)\r\n#define PORTCON_PORTB_OD_B4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B4_BITS_ENABLE             (PORTCON_PORTB_OD_B4_VALUE_ENABLE << PORTCON_PORTB_OD_B4_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B5_SHIFT                   5\r\n#define PORTCON_PORTB_OD_B5_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B5_MASK                    (((1U << PORTCON_PORTB_OD_B5_WIDTH) - 1U) << PORTCON_PORTB_OD_B5_SHIFT)\r\n#define PORTCON_PORTB_OD_B5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B5_BITS_DISABLE            (PORTCON_PORTB_OD_B5_VALUE_DISABLE << PORTCON_PORTB_OD_B5_SHIFT)\r\n#define PORTCON_PORTB_OD_B5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B5_BITS_ENABLE             (PORTCON_PORTB_OD_B5_VALUE_ENABLE << PORTCON_PORTB_OD_B5_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B6_SHIFT                   6\r\n#define PORTCON_PORTB_OD_B6_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B6_MASK                    (((1U << PORTCON_PORTB_OD_B6_WIDTH) - 1U) << PORTCON_PORTB_OD_B6_SHIFT)\r\n#define PORTCON_PORTB_OD_B6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B6_BITS_DISABLE            (PORTCON_PORTB_OD_B6_VALUE_DISABLE << PORTCON_PORTB_OD_B6_SHIFT)\r\n#define PORTCON_PORTB_OD_B6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B6_BITS_ENABLE             (PORTCON_PORTB_OD_B6_VALUE_ENABLE << PORTCON_PORTB_OD_B6_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B7_SHIFT                   7\r\n#define PORTCON_PORTB_OD_B7_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B7_MASK                    (((1U << PORTCON_PORTB_OD_B7_WIDTH) - 1U) << PORTCON_PORTB_OD_B7_SHIFT)\r\n#define PORTCON_PORTB_OD_B7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B7_BITS_DISABLE            (PORTCON_PORTB_OD_B7_VALUE_DISABLE << PORTCON_PORTB_OD_B7_SHIFT)\r\n#define PORTCON_PORTB_OD_B7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B7_BITS_ENABLE             (PORTCON_PORTB_OD_B7_VALUE_ENABLE << PORTCON_PORTB_OD_B7_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B8_SHIFT                   8\r\n#define PORTCON_PORTB_OD_B8_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B8_MASK                    (((1U << PORTCON_PORTB_OD_B8_WIDTH) - 1U) << PORTCON_PORTB_OD_B8_SHIFT)\r\n#define PORTCON_PORTB_OD_B8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B8_BITS_DISABLE            (PORTCON_PORTB_OD_B8_VALUE_DISABLE << PORTCON_PORTB_OD_B8_SHIFT)\r\n#define PORTCON_PORTB_OD_B8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B8_BITS_ENABLE             (PORTCON_PORTB_OD_B8_VALUE_ENABLE << PORTCON_PORTB_OD_B8_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B9_SHIFT                   9\r\n#define PORTCON_PORTB_OD_B9_WIDTH                   1\r\n#define PORTCON_PORTB_OD_B9_MASK                    (((1U << PORTCON_PORTB_OD_B9_WIDTH) - 1U) << PORTCON_PORTB_OD_B9_SHIFT)\r\n#define PORTCON_PORTB_OD_B9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTB_OD_B9_BITS_DISABLE            (PORTCON_PORTB_OD_B9_VALUE_DISABLE << PORTCON_PORTB_OD_B9_SHIFT)\r\n#define PORTCON_PORTB_OD_B9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTB_OD_B9_BITS_ENABLE             (PORTCON_PORTB_OD_B9_VALUE_ENABLE << PORTCON_PORTB_OD_B9_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B10_SHIFT                  10\r\n#define PORTCON_PORTB_OD_B10_WIDTH                  1\r\n#define PORTCON_PORTB_OD_B10_MASK                   (((1U << PORTCON_PORTB_OD_B10_WIDTH) - 1U) << PORTCON_PORTB_OD_B10_SHIFT)\r\n#define PORTCON_PORTB_OD_B10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_OD_B10_BITS_DISABLE           (PORTCON_PORTB_OD_B10_VALUE_DISABLE << PORTCON_PORTB_OD_B10_SHIFT)\r\n#define PORTCON_PORTB_OD_B10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_OD_B10_BITS_ENABLE            (PORTCON_PORTB_OD_B10_VALUE_ENABLE << PORTCON_PORTB_OD_B10_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B11_SHIFT                  11\r\n#define PORTCON_PORTB_OD_B11_WIDTH                  1\r\n#define PORTCON_PORTB_OD_B11_MASK                   (((1U << PORTCON_PORTB_OD_B11_WIDTH) - 1U) << PORTCON_PORTB_OD_B11_SHIFT)\r\n#define PORTCON_PORTB_OD_B11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_OD_B11_BITS_DISABLE           (PORTCON_PORTB_OD_B11_VALUE_DISABLE << PORTCON_PORTB_OD_B11_SHIFT)\r\n#define PORTCON_PORTB_OD_B11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_OD_B11_BITS_ENABLE            (PORTCON_PORTB_OD_B11_VALUE_ENABLE << PORTCON_PORTB_OD_B11_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B12_SHIFT                  12\r\n#define PORTCON_PORTB_OD_B12_WIDTH                  1\r\n#define PORTCON_PORTB_OD_B12_MASK                   (((1U << PORTCON_PORTB_OD_B12_WIDTH) - 1U) << PORTCON_PORTB_OD_B12_SHIFT)\r\n#define PORTCON_PORTB_OD_B12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_OD_B12_BITS_DISABLE           (PORTCON_PORTB_OD_B12_VALUE_DISABLE << PORTCON_PORTB_OD_B12_SHIFT)\r\n#define PORTCON_PORTB_OD_B12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_OD_B12_BITS_ENABLE            (PORTCON_PORTB_OD_B12_VALUE_ENABLE << PORTCON_PORTB_OD_B12_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B13_SHIFT                  13\r\n#define PORTCON_PORTB_OD_B13_WIDTH                  1\r\n#define PORTCON_PORTB_OD_B13_MASK                   (((1U << PORTCON_PORTB_OD_B13_WIDTH) - 1U) << PORTCON_PORTB_OD_B13_SHIFT)\r\n#define PORTCON_PORTB_OD_B13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_OD_B13_BITS_DISABLE           (PORTCON_PORTB_OD_B13_VALUE_DISABLE << PORTCON_PORTB_OD_B13_SHIFT)\r\n#define PORTCON_PORTB_OD_B13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_OD_B13_BITS_ENABLE            (PORTCON_PORTB_OD_B13_VALUE_ENABLE << PORTCON_PORTB_OD_B13_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B14_SHIFT                  14\r\n#define PORTCON_PORTB_OD_B14_WIDTH                  1\r\n#define PORTCON_PORTB_OD_B14_MASK                   (((1U << PORTCON_PORTB_OD_B14_WIDTH) - 1U) << PORTCON_PORTB_OD_B14_SHIFT)\r\n#define PORTCON_PORTB_OD_B14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_OD_B14_BITS_DISABLE           (PORTCON_PORTB_OD_B14_VALUE_DISABLE << PORTCON_PORTB_OD_B14_SHIFT)\r\n#define PORTCON_PORTB_OD_B14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_OD_B14_BITS_ENABLE            (PORTCON_PORTB_OD_B14_VALUE_ENABLE << PORTCON_PORTB_OD_B14_SHIFT)\r\n\r\n#define PORTCON_PORTB_OD_B15_SHIFT                  15\r\n#define PORTCON_PORTB_OD_B15_WIDTH                  1\r\n#define PORTCON_PORTB_OD_B15_MASK                   (((1U << PORTCON_PORTB_OD_B15_WIDTH) - 1U) << PORTCON_PORTB_OD_B15_SHIFT)\r\n#define PORTCON_PORTB_OD_B15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTB_OD_B15_BITS_DISABLE           (PORTCON_PORTB_OD_B15_VALUE_DISABLE << PORTCON_PORTB_OD_B15_SHIFT)\r\n#define PORTCON_PORTB_OD_B15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTB_OD_B15_BITS_ENABLE            (PORTCON_PORTB_OD_B15_VALUE_ENABLE << PORTCON_PORTB_OD_B15_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_ADDR                       (PORTCON_BASE_ADDR + 0x0408U)\r\n#define PORTCON_PORTC_OD                            (*(volatile uint32_t *)PORTCON_PORTC_OD_ADDR)\r\n#define PORTCON_PORTC_OD_C0_SHIFT                   0\r\n#define PORTCON_PORTC_OD_C0_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C0_MASK                    (((1U << PORTCON_PORTC_OD_C0_WIDTH) - 1U) << PORTCON_PORTC_OD_C0_SHIFT)\r\n#define PORTCON_PORTC_OD_C0_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C0_BITS_DISABLE            (PORTCON_PORTC_OD_C0_VALUE_DISABLE << PORTCON_PORTC_OD_C0_SHIFT)\r\n#define PORTCON_PORTC_OD_C0_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C0_BITS_ENABLE             (PORTCON_PORTC_OD_C0_VALUE_ENABLE << PORTCON_PORTC_OD_C0_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C1_SHIFT                   1\r\n#define PORTCON_PORTC_OD_C1_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C1_MASK                    (((1U << PORTCON_PORTC_OD_C1_WIDTH) - 1U) << PORTCON_PORTC_OD_C1_SHIFT)\r\n#define PORTCON_PORTC_OD_C1_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C1_BITS_DISABLE            (PORTCON_PORTC_OD_C1_VALUE_DISABLE << PORTCON_PORTC_OD_C1_SHIFT)\r\n#define PORTCON_PORTC_OD_C1_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C1_BITS_ENABLE             (PORTCON_PORTC_OD_C1_VALUE_ENABLE << PORTCON_PORTC_OD_C1_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C2_SHIFT                   2\r\n#define PORTCON_PORTC_OD_C2_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C2_MASK                    (((1U << PORTCON_PORTC_OD_C2_WIDTH) - 1U) << PORTCON_PORTC_OD_C2_SHIFT)\r\n#define PORTCON_PORTC_OD_C2_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C2_BITS_DISABLE            (PORTCON_PORTC_OD_C2_VALUE_DISABLE << PORTCON_PORTC_OD_C2_SHIFT)\r\n#define PORTCON_PORTC_OD_C2_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C2_BITS_ENABLE             (PORTCON_PORTC_OD_C2_VALUE_ENABLE << PORTCON_PORTC_OD_C2_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C3_SHIFT                   3\r\n#define PORTCON_PORTC_OD_C3_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C3_MASK                    (((1U << PORTCON_PORTC_OD_C3_WIDTH) - 1U) << PORTCON_PORTC_OD_C3_SHIFT)\r\n#define PORTCON_PORTC_OD_C3_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C3_BITS_DISABLE            (PORTCON_PORTC_OD_C3_VALUE_DISABLE << PORTCON_PORTC_OD_C3_SHIFT)\r\n#define PORTCON_PORTC_OD_C3_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C3_BITS_ENABLE             (PORTCON_PORTC_OD_C3_VALUE_ENABLE << PORTCON_PORTC_OD_C3_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C4_SHIFT                   4\r\n#define PORTCON_PORTC_OD_C4_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C4_MASK                    (((1U << PORTCON_PORTC_OD_C4_WIDTH) - 1U) << PORTCON_PORTC_OD_C4_SHIFT)\r\n#define PORTCON_PORTC_OD_C4_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C4_BITS_DISABLE            (PORTCON_PORTC_OD_C4_VALUE_DISABLE << PORTCON_PORTC_OD_C4_SHIFT)\r\n#define PORTCON_PORTC_OD_C4_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C4_BITS_ENABLE             (PORTCON_PORTC_OD_C4_VALUE_ENABLE << PORTCON_PORTC_OD_C4_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C5_SHIFT                   5\r\n#define PORTCON_PORTC_OD_C5_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C5_MASK                    (((1U << PORTCON_PORTC_OD_C5_WIDTH) - 1U) << PORTCON_PORTC_OD_C5_SHIFT)\r\n#define PORTCON_PORTC_OD_C5_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C5_BITS_DISABLE            (PORTCON_PORTC_OD_C5_VALUE_DISABLE << PORTCON_PORTC_OD_C5_SHIFT)\r\n#define PORTCON_PORTC_OD_C5_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C5_BITS_ENABLE             (PORTCON_PORTC_OD_C5_VALUE_ENABLE << PORTCON_PORTC_OD_C5_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C6_SHIFT                   6\r\n#define PORTCON_PORTC_OD_C6_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C6_MASK                    (((1U << PORTCON_PORTC_OD_C6_WIDTH) - 1U) << PORTCON_PORTC_OD_C6_SHIFT)\r\n#define PORTCON_PORTC_OD_C6_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C6_BITS_DISABLE            (PORTCON_PORTC_OD_C6_VALUE_DISABLE << PORTCON_PORTC_OD_C6_SHIFT)\r\n#define PORTCON_PORTC_OD_C6_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C6_BITS_ENABLE             (PORTCON_PORTC_OD_C6_VALUE_ENABLE << PORTCON_PORTC_OD_C6_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C7_SHIFT                   7\r\n#define PORTCON_PORTC_OD_C7_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C7_MASK                    (((1U << PORTCON_PORTC_OD_C7_WIDTH) - 1U) << PORTCON_PORTC_OD_C7_SHIFT)\r\n#define PORTCON_PORTC_OD_C7_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C7_BITS_DISABLE            (PORTCON_PORTC_OD_C7_VALUE_DISABLE << PORTCON_PORTC_OD_C7_SHIFT)\r\n#define PORTCON_PORTC_OD_C7_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C7_BITS_ENABLE             (PORTCON_PORTC_OD_C7_VALUE_ENABLE << PORTCON_PORTC_OD_C7_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C8_SHIFT                   8\r\n#define PORTCON_PORTC_OD_C8_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C8_MASK                    (((1U << PORTCON_PORTC_OD_C8_WIDTH) - 1U) << PORTCON_PORTC_OD_C8_SHIFT)\r\n#define PORTCON_PORTC_OD_C8_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C8_BITS_DISABLE            (PORTCON_PORTC_OD_C8_VALUE_DISABLE << PORTCON_PORTC_OD_C8_SHIFT)\r\n#define PORTCON_PORTC_OD_C8_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C8_BITS_ENABLE             (PORTCON_PORTC_OD_C8_VALUE_ENABLE << PORTCON_PORTC_OD_C8_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C9_SHIFT                   9\r\n#define PORTCON_PORTC_OD_C9_WIDTH                   1\r\n#define PORTCON_PORTC_OD_C9_MASK                    (((1U << PORTCON_PORTC_OD_C9_WIDTH) - 1U) << PORTCON_PORTC_OD_C9_SHIFT)\r\n#define PORTCON_PORTC_OD_C9_VALUE_DISABLE           0U\r\n#define PORTCON_PORTC_OD_C9_BITS_DISABLE            (PORTCON_PORTC_OD_C9_VALUE_DISABLE << PORTCON_PORTC_OD_C9_SHIFT)\r\n#define PORTCON_PORTC_OD_C9_VALUE_ENABLE            1U\r\n#define PORTCON_PORTC_OD_C9_BITS_ENABLE             (PORTCON_PORTC_OD_C9_VALUE_ENABLE << PORTCON_PORTC_OD_C9_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C10_SHIFT                  10\r\n#define PORTCON_PORTC_OD_C10_WIDTH                  1\r\n#define PORTCON_PORTC_OD_C10_MASK                   (((1U << PORTCON_PORTC_OD_C10_WIDTH) - 1U) << PORTCON_PORTC_OD_C10_SHIFT)\r\n#define PORTCON_PORTC_OD_C10_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_OD_C10_BITS_DISABLE           (PORTCON_PORTC_OD_C10_VALUE_DISABLE << PORTCON_PORTC_OD_C10_SHIFT)\r\n#define PORTCON_PORTC_OD_C10_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_OD_C10_BITS_ENABLE            (PORTCON_PORTC_OD_C10_VALUE_ENABLE << PORTCON_PORTC_OD_C10_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C11_SHIFT                  11\r\n#define PORTCON_PORTC_OD_C11_WIDTH                  1\r\n#define PORTCON_PORTC_OD_C11_MASK                   (((1U << PORTCON_PORTC_OD_C11_WIDTH) - 1U) << PORTCON_PORTC_OD_C11_SHIFT)\r\n#define PORTCON_PORTC_OD_C11_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_OD_C11_BITS_DISABLE           (PORTCON_PORTC_OD_C11_VALUE_DISABLE << PORTCON_PORTC_OD_C11_SHIFT)\r\n#define PORTCON_PORTC_OD_C11_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_OD_C11_BITS_ENABLE            (PORTCON_PORTC_OD_C11_VALUE_ENABLE << PORTCON_PORTC_OD_C11_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C12_SHIFT                  12\r\n#define PORTCON_PORTC_OD_C12_WIDTH                  1\r\n#define PORTCON_PORTC_OD_C12_MASK                   (((1U << PORTCON_PORTC_OD_C12_WIDTH) - 1U) << PORTCON_PORTC_OD_C12_SHIFT)\r\n#define PORTCON_PORTC_OD_C12_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_OD_C12_BITS_DISABLE           (PORTCON_PORTC_OD_C12_VALUE_DISABLE << PORTCON_PORTC_OD_C12_SHIFT)\r\n#define PORTCON_PORTC_OD_C12_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_OD_C12_BITS_ENABLE            (PORTCON_PORTC_OD_C12_VALUE_ENABLE << PORTCON_PORTC_OD_C12_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C13_SHIFT                  13\r\n#define PORTCON_PORTC_OD_C13_WIDTH                  1\r\n#define PORTCON_PORTC_OD_C13_MASK                   (((1U << PORTCON_PORTC_OD_C13_WIDTH) - 1U) << PORTCON_PORTC_OD_C13_SHIFT)\r\n#define PORTCON_PORTC_OD_C13_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_OD_C13_BITS_DISABLE           (PORTCON_PORTC_OD_C13_VALUE_DISABLE << PORTCON_PORTC_OD_C13_SHIFT)\r\n#define PORTCON_PORTC_OD_C13_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_OD_C13_BITS_ENABLE            (PORTCON_PORTC_OD_C13_VALUE_ENABLE << PORTCON_PORTC_OD_C13_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C14_SHIFT                  14\r\n#define PORTCON_PORTC_OD_C14_WIDTH                  1\r\n#define PORTCON_PORTC_OD_C14_MASK                   (((1U << PORTCON_PORTC_OD_C14_WIDTH) - 1U) << PORTCON_PORTC_OD_C14_SHIFT)\r\n#define PORTCON_PORTC_OD_C14_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_OD_C14_BITS_DISABLE           (PORTCON_PORTC_OD_C14_VALUE_DISABLE << PORTCON_PORTC_OD_C14_SHIFT)\r\n#define PORTCON_PORTC_OD_C14_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_OD_C14_BITS_ENABLE            (PORTCON_PORTC_OD_C14_VALUE_ENABLE << PORTCON_PORTC_OD_C14_SHIFT)\r\n\r\n#define PORTCON_PORTC_OD_C15_SHIFT                  15\r\n#define PORTCON_PORTC_OD_C15_WIDTH                  1\r\n#define PORTCON_PORTC_OD_C15_MASK                   (((1U << PORTCON_PORTC_OD_C15_WIDTH) - 1U) << PORTCON_PORTC_OD_C15_SHIFT)\r\n#define PORTCON_PORTC_OD_C15_VALUE_DISABLE          0U\r\n#define PORTCON_PORTC_OD_C15_BITS_DISABLE           (PORTCON_PORTC_OD_C15_VALUE_DISABLE << PORTCON_PORTC_OD_C15_SHIFT)\r\n#define PORTCON_PORTC_OD_C15_VALUE_ENABLE           1U\r\n#define PORTCON_PORTC_OD_C15_BITS_ENABLE            (PORTCON_PORTC_OD_C15_VALUE_ENABLE << PORTCON_PORTC_OD_C15_SHIFT)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/pwmplus.h",
    "content": "#ifndef HARDWARE_DP32G030_PWMPLUS_H\r\n#define HARDWARE_DP32G030_PWMPLUS_H\r\n\r\n#define PWM_PLUS0_BASE_ADDR 0x400B4000U\r\n\r\n//---------------\r\n\r\n#define PWMPLUS_CFG                             0x00U\r\n\r\n#define PWMPLUS_CFG_COUNTER_EN_SHIFT            0U\r\n#define PWMPLUS_CFG_COUNTER_EN_WIDTH            1U\r\n#define PWMPLUS_CFG_COUNTER_EN_MASK             (((1U << PWMPLUS_CFG_COUNTER_EN_WIDTH) - 1U) << PWMPLUS_CFG_COUNTER_EN_SHIFT)\r\n#define PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE     1U\r\n#define PWMPLUS_CFG_COUNTER_EN_BITS_ENABLE      (PWMPLUS_CFG_COUNTER_EN_VALUE_ENABLE << PWMPLUS_CFG_COUNTER_EN_SHIFT)\r\n\r\n#define PWMPLUS_CFG_CNT_TYPE_SHIFT              1U\r\n\r\n#define PWMPLUS_CFG_CNT_REP_SHIFT               2U\r\n#define PWMPLUS_CFG_CNT_REP_WIDTH               1U\r\n#define PWMPLUS_CFG_CNT_REP_VALUE_ENABLE        1U\r\n#define PWMPLUS_CFG_CNT_REP_BITS_ENABLE         (PWMPLUS_CFG_CNT_REP_VALUE_ENABLE << PWMPLUS_CFG_CNT_REP_SHIFT)\r\n\r\n#define PWMPLUS_CFG_OUT_MODE_SHIFT              3U\r\n#define PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE       1U\r\n#define PWMPLUS_CFG_OUT_MODE_BITS_ENABLE        (PWMPLUS_CFG_OUT_MODE_VALUE_ENABLE << PWMPLUS_CFG_OUT_MODE_SHIFT)\r\n\r\n#define PWMPLUS_CFG_AUTO_RELOAD_SHIFT           8U\r\n\r\n//---------------\r\n\r\n#define PWMPLUS_GEN                             0x04U\r\n\r\n#define PWMPLUS_GEN_CH0_OE_SHIFT                24U\r\n#define PWMPLUS_GEN_CH0_OE_WIDTH                1U\r\n#define PWMPLUS_GEN_CH0_OE_VALUE_ENABLE         1U\r\n#define PWMPLUS_GEN_CH0_OE_BITS_ENABLE          (PWMPLUS_GEN_CH0_OE_VALUE_ENABLE << PWMPLUS_GEN_CH0_OE_SHIFT)\r\n\r\n#define PWMPLUS_GEN_CH0_OUTINV_SHIFT            16U\r\n#define PWMPLUS_GEN_CH0_OUTINV_WIDTH            1U\r\n#define PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE     1U\r\n#define PWMPLUS_GEN_CH0_OUTINV_BITS_ENABLE      (PWMPLUS_GEN_CH0_OUTINV_VALUE_ENABLE << PWMPLUS_GEN_CH0_OUTINV_SHIFT)\r\n\r\n#define PWMPLUS_GEN_CH0_START_SHIFT             8U\r\n#define PWMPLUS_GEN_CH0_START_WIDTH             1U\r\n#define PWMPLUS_GEN_CH0_START_VALUE_ENABLE      1U\r\n#define PWMPLUS_GEN_CH0_START_BITS_ENABLE       (PWMPLUS_GEN_CH0_START_VALUE_ENABLE << PWMPLUS_GEN_CH0_START_SHIFT)\r\n\r\n#define PWMPLUS_GEN_CH0_IDLE_SHIFT              0U\r\n#define PWMPLUS_GEN_CH0_IDLE_WIDTH              1U\r\n#define PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE       1U\r\n#define PWMPLUS_GEN_CH0_IDLE_BITS_ENABLE        (PWMPLUS_GEN_CH0_IDLE_VALUE_ENABLE << PWMPLUS_GEN_CH0_IDLE_SHIFT)\r\n\r\n//---------------\r\n\r\n#define PWMPLUS_CLKSRC      0x08U\r\n#define PWMPLUS_BRAKE_CFG   0x0CU\r\n#define PWMPLUS_MASK_LEV    0x10U\r\n#define PWMPLUS_PERIOD      0x1CU\r\n#define PWMPLUS_CH0_COMP    0x20U\r\n#define PWMPLUS_CH1_COMP    0x24U\r\n#define PWMPLUS_CH2_COMP    0x28U\r\n#define PWMPLUS_CH0_DT      0x30U\r\n#define PWMPLUS_CH1_DT      0x34U\r\n#define PWMPLUS_CH2_DT      0x38U\r\n#define PWMPLUS_TRIG_COMP   0x40U\r\n#define PWMPLUS_TRIG_CFG    0x44U\r\n#define PWMPLUS_IE          0x60U\r\n#define PWMPLUS_IF          0x64U\r\n#define PWMPLUS_SWLOAD      0x84U\r\n#define PWMPLUS_MASK_EN     0x88\r\n#define PWMPLUS_CNT_ST      0xE0\r\n#define PWMPLUS_BRAKE_ST    0xE4\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n#define PWM_PLUS0_CFG_ADDR          (PWM_PLUS0_BASE_ADDR + PWMPLUS_CFG)\r\n#define PWM_PLUS0_CFG               (*(volatile uint32_t *)PWM_PLUS0_CFG_ADDR)\r\n\r\n#define PWM_PLUS0_GEN_ADDR          (PWM_PLUS0_BASE_ADDR + PWMPLUS_GEN)\r\n#define PWM_PLUS0_GEN               (*(volatile uint32_t *)PWM_PLUS0_GEN_ADDR)\r\n\r\n#define PWM_PLUS0_CLKSRC_ADDR       (PWM_PLUS0_BASE_ADDR + PWMPLUS_CLKSRC)\r\n#define PWM_PLUS0_CLKSRC            (*(volatile uint32_t *)PWM_PLUS0_CLKSRC_ADDR)\r\n\r\n#define PWM_PLUS0_BRAKE_CFG_ADDR    (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_CFG)\r\n#define PWM_PLUS0_BRAKE_CFG         (*(volatile uint32_t *)PWM_PLUS0_BRAKE_CFG_ADDR)\r\n\r\n#define PWM_PLUS0_MASK_LEV_ADDR     (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_LEV)\r\n#define PWM_PLUS0_MASK_LEV          (*(volatile uint32_t *)PWM_PLUS0_MASK_LEV_ADDR)\r\n\r\n#define PWM_PLUS0_PERIOD_ADDR       (PWM_PLUS0_BASE_ADDR + PWMPLUS_PERIOD)\r\n#define PWM_PLUS0_PERIOD            (*(volatile uint32_t *)PWM_PLUS0_PERIOD_ADDR)\r\n\r\n#define PWM_PLUS0_CH0_COMP_ADDR     (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_COMP)\r\n#define PWM_PLUS0_CH0_COMP          (*(volatile uint32_t *)PWM_PLUS0_CH0_COMP_ADDR)\r\n\r\n#define PWM_PLUS0_CH1_COMP_ADDR     (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_COMP)\r\n#define PWM_PLUS0_CH1_COMP          (*(volatile uint32_t *)PWM_PLUS0_CH1_COMP_ADDR)\r\n\r\n#define PWM_PLUS0_CH2_COMP_ADDR     (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_COMP)\r\n#define PWM_PLUS0_CH2_COMP          (*(volatile uint32_t *)PWM_PLUS0_CH2_COMP_ADDR)\r\n\r\n#define PWM_PLUS0_CH0_DT_ADDR       (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH0_DT)\r\n#define PWM_PLUS0_CH0_DT            (*(volatile uint32_t *)PWM_PLUS0_CH0_DT_ADDR)\r\n\r\n#define PWM_PLUS0_CH1_DT_ADDR       (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH1_DT)\r\n#define PWM_PLUS0_CH1_DT            (*(volatile uint32_t *)PWM_PLUS0_CH1_DT_ADDR)\r\n\r\n#define PWM_PLUS0_CH2_DT_ADDR       (PWM_PLUS0_BASE_ADDR + PWMPLUS_CH2_DT)\r\n#define PWM_PLUS0_CH2_DT            (*(volatile uint32_t *)PWM_PLUS0_CH2_DT_ADDR)\r\n\r\n#define PWM_PLUS0_TRIG_COMP_ADDR    (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_COMP)\r\n#define PWM_PLUS0_TRIG_COMP         (*(volatile uint32_t *)PWM_PLUS0_TRIG_COMP_ADDR)\r\n\r\n#define PWM_PLUS0_TRIG_CFG_ADDR     (PWM_PLUS0_BASE_ADDR + PWMPLUS_TRIG_CFG)\r\n#define PWM_PLUS0_TRIG_CFG          (*(volatile uint32_t *)PWM_PLUS0_TRIG_CFG_ADDR)\r\n\r\n#define PWM_PLUS0_IE_ADDR           (PWM_PLUS0_BASE_ADDR + PWMPLUS_IE)\r\n#define PWM_PLUS0_IE                (*(volatile uint32_t *)PWM_PLUS0_IE_ADDR)\r\n\r\n#define PWM_PLUS0_IF_ADDR           (PWM_PLUS0_BASE_ADDR + PWMPLUS_IF)\r\n#define PWM_PLUS0_IF                (*(volatile uint32_t *)PWM_PLUS0_IF_ADDR)\r\n\r\n#define PWM_PLUS0_SWLOAD_ADDR       (PWM_PLUS0_BASE_ADDR + PWMPLUS_SWLOAD)\r\n#define PWM_PLUS0_SWLOAD            (*(volatile uint32_t *)PWM_PLUS0_SWLOAD_ADDR)\r\n\r\n#define PWM_PLUS0_MASK_EN_ADDR      (PWM_PLUS0_BASE_ADDR + PWMPLUS_MASK_EN)\r\n#define PWM_PLUS0_MASK_EN           (*(volatile uint32_t *)PWM_PLUS0_MASK_EN_ADDR)\r\n\r\n#define PWM_PLUS0_CNT_ST_ADDR       (PWM_PLUS0_BASE_ADDR + PWMPLUS_CNT_ST)\r\n#define PWM_PLUS0_CNT_ST            (*(volatile uint32_t *)PWM_PLUS0_CNT_ST_ADDR)\r\n\r\n#define PWM_PLUS0_BRAKE_ST_ADDR     (PWM_PLUS0_BASE_ADDR + PWMPLUS_BRAKE_ST)\r\n#define PWM_PLUS0_BRAKE_ST          (*(volatile uint32_t *)PWM_PLUS0_BRAKE_ST_ADDR)\r\n\r\n#endif"
  },
  {
    "path": "bsp/dp32g030/rtc.h",
    "content": "//\n// Created by RUPC on 2024/1/30.\n//\n#ifndef HARDWARE_DP32G030_RTC_H\n#define HARDWARE_DP32G030_RTC_H\n#include <stdint.h>\n\n//RCLF 32768HZ\n#define RTC_BASE_ADD 0x40069000\n#define RTC_CFG_ADD (0x00+RTC_BASE_ADD) //配置寄存器\n#define RTC_IE_ADD (0x04+RTC_BASE_ADD) //中断使能寄存器\n#define RTC_IF_ADD (0x08+RTC_BASE_ADD)// 状态寄存器\n#define RTC_PRE_ADD (0x10+RTC_BASE_ADD) // 预分频寄存器\n#define RTC_TR_ADD (0x14+RTC_BASE_ADD) //时间寄存器\n#define RTC_DR_ADD (0x18+RTC_BASE_ADD) // 日期寄存器\n#define RTC_AR_ADD (0x1C+RTC_BASE_ADD) //闹钟寄存器\n#define RTC_TSTR_ADD (0x20+RTC_BASE_ADD) //当前时间寄存器\n#define RTC_TSDR_ADD (0x24+RTC_BASE_ADD) // 当前日期寄存器\n#define RTC_CNT_ADD (0x28+RTC_BASE_ADD) // 秒标当前计数值\n#define RTC_VALID_ADD (0x2C+RTC_BASE_ADD) //当前时间有效标志寄存器\n\n#define RTC_CFG (*(volatile uint32_t *)RTC_CFG_ADD) //配置寄存器\n#define RTC_IE (*(volatile uint32_t *)RTC_IE_ADD) //中断使能寄存器\n#define RTC_IF (*(volatile uint32_t *)RTC_IF_ADD)// 状态寄存器\n#define RTC_PRE (*(volatile uint32_t *)RTC_PRE_ADD) // 预分频寄存器\n#define RTC_TR (*(volatile uint32_t *)RTC_TR_ADD) //时间寄存器\n#define RTC_DR (*(volatile uint32_t *)RTC_DR_ADD) // 日期寄存器\n#define RTC_AR (*(volatile uint32_t *)RTC_AR_ADD) //闹钟寄存器\n#define RTC_TSTR (*(volatile uint32_t *)RTC_TSTR_ADD) //当前时间寄存器\n#define RTC_TSDR (*(volatile uint32_t *)RTC_TSDR_ADD) // 当前日期寄存器\n#define RTC_CNT (*(volatile uint32_t *)RTC_CNT_ADD) // 秒标当前计数值\n#define RTC_VALID (*(volatile uint32_t *)RTC_VALID_ADD) //当前时间有效标志寄存器\n#define RC_FREQ_DELTA (*(volatile uint32_t *)(0x40000000u+0x78u))\n#define TRIM_RCLF (*(volatile uint32_t *)(0x40000800u+0x34u))\n#define TEMP1 (*(volatile uint32_t *)(0x40000800u+0x20u))\n#define TEMP2 (*(volatile uint32_t *)(0x40000800u+0x24u))\n\nvoid RTC_INIT(void);\nvoid RTC_Set( );\nvoid RTC_Get();\n\nextern uint8_t time[6];\n\n#endif"
  },
  {
    "path": "bsp/dp32g030/saradc.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_SARADC_H\r\n#define HARDWARE_DP32G030_SARADC_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- SARADC -------- */\r\n#define SARADC_BASE_ADDR                        0x400BA000U\r\n#define SARADC_BASE_SIZE                        0x00000800U\r\n\r\n#define SARADC_CFG_ADDR                         (SARADC_BASE_ADDR + 0x0000U)\r\n#define SARADC_CFG                              (*(volatile uint32_t *)SARADC_CFG_ADDR)\r\n#define SARADC_CFG_CH_SEL_SHIFT                 0\r\n#define SARADC_CFG_CH_SEL_WIDTH                 15\r\n#define SARADC_CFG_CH_SEL_MASK                  (((1U << SARADC_CFG_CH_SEL_WIDTH) - 1U) << SARADC_CFG_CH_SEL_SHIFT)\r\n#define SARADC_CFG_AVG_SHIFT                    16\r\n#define SARADC_CFG_AVG_WIDTH                    2\r\n#define SARADC_CFG_AVG_MASK                     (((1U << SARADC_CFG_AVG_WIDTH) - 1U) << SARADC_CFG_AVG_SHIFT)\r\n#define SARADC_CFG_AVG_VALUE_1_SAMPLE           0U\r\n#define SARADC_CFG_AVG_BITS_1_SAMPLE            (SARADC_CFG_AVG_VALUE_1_SAMPLE << SARADC_CFG_AVG_SHIFT)\r\n#define SARADC_CFG_AVG_VALUE_2_SAMPLE           1U\r\n#define SARADC_CFG_AVG_BITS_2_SAMPLE            (SARADC_CFG_AVG_VALUE_2_SAMPLE << SARADC_CFG_AVG_SHIFT)\r\n#define SARADC_CFG_AVG_VALUE_4_SAMPLE           2U\r\n#define SARADC_CFG_AVG_BITS_4_SAMPLE            (SARADC_CFG_AVG_VALUE_4_SAMPLE << SARADC_CFG_AVG_SHIFT)\r\n#define SARADC_CFG_AVG_VALUE_8_SAMPLE           3U\r\n#define SARADC_CFG_AVG_BITS_8_SAMPLE            (SARADC_CFG_AVG_VALUE_8_SAMPLE << SARADC_CFG_AVG_SHIFT)\r\n\r\n#define SARADC_CFG_CONT_SHIFT                   18\r\n#define SARADC_CFG_CONT_WIDTH                   1\r\n#define SARADC_CFG_CONT_MASK                    (((1U << SARADC_CFG_CONT_WIDTH) - 1U) << SARADC_CFG_CONT_SHIFT)\r\n#define SARADC_CFG_CONT_VALUE_SINGLE            0U\r\n#define SARADC_CFG_CONT_BITS_SINGLE             (SARADC_CFG_CONT_VALUE_SINGLE << SARADC_CFG_CONT_SHIFT)\r\n#define SARADC_CFG_CONT_VALUE_CONTINUOUS        1U\r\n#define SARADC_CFG_CONT_BITS_CONTINUOUS         (SARADC_CFG_CONT_VALUE_CONTINUOUS << SARADC_CFG_CONT_SHIFT)\r\n\r\n#define SARADC_CFG_SMPL_SETUP_SHIFT             19\r\n#define SARADC_CFG_SMPL_SETUP_WIDTH             3\r\n#define SARADC_CFG_SMPL_SETUP_MASK              (((1U << SARADC_CFG_SMPL_SETUP_WIDTH) - 1U) << SARADC_CFG_SMPL_SETUP_SHIFT)\r\n#define SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE     0U\r\n#define SARADC_CFG_SMPL_SETUP_BITS_1_CYCLE      (SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)\r\n#define SARADC_CFG_SMPL_SETUP_VALUE_2_CYCLE     1U\r\n#define SARADC_CFG_SMPL_SETUP_BITS_2_CYCLE      (SARADC_CFG_SMPL_SETUP_VALUE_2_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)\r\n#define SARADC_CFG_SMPL_SETUP_VALUE_4_CYCLE     2U\r\n#define SARADC_CFG_SMPL_SETUP_BITS_4_CYCLE      (SARADC_CFG_SMPL_SETUP_VALUE_4_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)\r\n#define SARADC_CFG_SMPL_SETUP_VALUE_8_CYCLE     3U\r\n#define SARADC_CFG_SMPL_SETUP_BITS_8_CYCLE      (SARADC_CFG_SMPL_SETUP_VALUE_8_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)\r\n#define SARADC_CFG_SMPL_SETUP_VALUE_16_CYCLE    4U\r\n#define SARADC_CFG_SMPL_SETUP_BITS_16_CYCLE     (SARADC_CFG_SMPL_SETUP_VALUE_16_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)\r\n#define SARADC_CFG_SMPL_SETUP_VALUE_32_CYCLE    5U\r\n#define SARADC_CFG_SMPL_SETUP_BITS_32_CYCLE     (SARADC_CFG_SMPL_SETUP_VALUE_32_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)\r\n#define SARADC_CFG_SMPL_SETUP_VALUE_64_CYCLE    6U\r\n#define SARADC_CFG_SMPL_SETUP_BITS_64_CYCLE     (SARADC_CFG_SMPL_SETUP_VALUE_64_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)\r\n#define SARADC_CFG_SMPL_SETUP_VALUE_128_CYCLE   7U\r\n#define SARADC_CFG_SMPL_SETUP_BITS_128_CYCLE    (SARADC_CFG_SMPL_SETUP_VALUE_128_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT)\r\n\r\n#define SARADC_CFG_MEM_MODE_SHIFT               22\r\n#define SARADC_CFG_MEM_MODE_WIDTH               1\r\n#define SARADC_CFG_MEM_MODE_MASK                (((1U << SARADC_CFG_MEM_MODE_WIDTH) - 1U) << SARADC_CFG_MEM_MODE_SHIFT)\r\n#define SARADC_CFG_MEM_MODE_VALUE_FIFO          0U\r\n#define SARADC_CFG_MEM_MODE_BITS_FIFO           (SARADC_CFG_MEM_MODE_VALUE_FIFO << SARADC_CFG_MEM_MODE_SHIFT)\r\n#define SARADC_CFG_MEM_MODE_VALUE_CHANNEL       1U\r\n#define SARADC_CFG_MEM_MODE_BITS_CHANNEL        (SARADC_CFG_MEM_MODE_VALUE_CHANNEL << SARADC_CFG_MEM_MODE_SHIFT)\r\n\r\n#define SARADC_CFG_SMPL_CLK_SHIFT               23\r\n#define SARADC_CFG_SMPL_CLK_WIDTH               1\r\n#define SARADC_CFG_SMPL_CLK_MASK                (((1U << SARADC_CFG_SMPL_CLK_WIDTH) - 1U) << SARADC_CFG_SMPL_CLK_SHIFT)\r\n#define SARADC_CFG_SMPL_CLK_VALUE_EXTERNAL      0U\r\n#define SARADC_CFG_SMPL_CLK_BITS_EXTERNAL       (SARADC_CFG_SMPL_CLK_VALUE_EXTERNAL << SARADC_CFG_SMPL_CLK_SHIFT)\r\n#define SARADC_CFG_SMPL_CLK_VALUE_INTERNAL      1U\r\n#define SARADC_CFG_SMPL_CLK_BITS_INTERNAL       (SARADC_CFG_SMPL_CLK_VALUE_INTERNAL << SARADC_CFG_SMPL_CLK_SHIFT)\r\n\r\n#define SARADC_CFG_SMPL_WIN_SHIFT               24\r\n#define SARADC_CFG_SMPL_WIN_WIDTH               3\r\n#define SARADC_CFG_SMPL_WIN_MASK                (((1U << SARADC_CFG_SMPL_WIN_WIDTH) - 1U) << SARADC_CFG_SMPL_WIN_SHIFT)\r\n#define SARADC_CFG_SMPL_WIN_VALUE_1_CYCLE       0U\r\n#define SARADC_CFG_SMPL_WIN_BITS_1_CYCLE        (SARADC_CFG_SMPL_WIN_VALUE_1_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)\r\n#define SARADC_CFG_SMPL_WIN_VALUE_3_CYCLE       1U\r\n#define SARADC_CFG_SMPL_WIN_BITS_3_CYCLE        (SARADC_CFG_SMPL_WIN_VALUE_3_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)\r\n#define SARADC_CFG_SMPL_WIN_VALUE_5_CYCLE       2U\r\n#define SARADC_CFG_SMPL_WIN_BITS_5_CYCLE        (SARADC_CFG_SMPL_WIN_VALUE_5_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)\r\n#define SARADC_CFG_SMPL_WIN_VALUE_7_CYCLE       3U\r\n#define SARADC_CFG_SMPL_WIN_BITS_7_CYCLE        (SARADC_CFG_SMPL_WIN_VALUE_7_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)\r\n#define SARADC_CFG_SMPL_WIN_VALUE_9_CYCLE       4U\r\n#define SARADC_CFG_SMPL_WIN_BITS_9_CYCLE        (SARADC_CFG_SMPL_WIN_VALUE_9_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)\r\n#define SARADC_CFG_SMPL_WIN_VALUE_11_CYCLE      5U\r\n#define SARADC_CFG_SMPL_WIN_BITS_11_CYCLE       (SARADC_CFG_SMPL_WIN_VALUE_11_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)\r\n#define SARADC_CFG_SMPL_WIN_VALUE_13_CYCLE      6U\r\n#define SARADC_CFG_SMPL_WIN_BITS_13_CYCLE       (SARADC_CFG_SMPL_WIN_VALUE_13_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)\r\n#define SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE      7U\r\n#define SARADC_CFG_SMPL_WIN_BITS_15_CYCLE       (SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT)\r\n\r\n#define SARADC_CFG_ADC_EN_SHIFT                 27\r\n#define SARADC_CFG_ADC_EN_WIDTH                 1\r\n#define SARADC_CFG_ADC_EN_MASK                  (((1U << SARADC_CFG_ADC_EN_WIDTH) - 1U) << SARADC_CFG_ADC_EN_SHIFT)\r\n#define SARADC_CFG_ADC_EN_VALUE_DISABLE         0U\r\n#define SARADC_CFG_ADC_EN_BITS_DISABLE          (SARADC_CFG_ADC_EN_VALUE_DISABLE << SARADC_CFG_ADC_EN_SHIFT)\r\n#define SARADC_CFG_ADC_EN_VALUE_ENABLE          1U\r\n#define SARADC_CFG_ADC_EN_BITS_ENABLE           (SARADC_CFG_ADC_EN_VALUE_ENABLE << SARADC_CFG_ADC_EN_SHIFT)\r\n\r\n#define SARADC_CFG_ADC_TRIG_SHIFT               28\r\n#define SARADC_CFG_ADC_TRIG_WIDTH               1\r\n#define SARADC_CFG_ADC_TRIG_MASK                (((1U << SARADC_CFG_ADC_TRIG_WIDTH) - 1U) << SARADC_CFG_ADC_TRIG_SHIFT)\r\n#define SARADC_CFG_ADC_TRIG_VALUE_CPU           0U\r\n#define SARADC_CFG_ADC_TRIG_BITS_CPU            (SARADC_CFG_ADC_TRIG_VALUE_CPU << SARADC_CFG_ADC_TRIG_SHIFT)\r\n#define SARADC_CFG_ADC_TRIG_VALUE_EXTERNAL      1U\r\n#define SARADC_CFG_ADC_TRIG_BITS_EXTERNAL       (SARADC_CFG_ADC_TRIG_VALUE_EXTERNAL << SARADC_CFG_ADC_TRIG_SHIFT)\r\n\r\n#define SARADC_CFG_DMA_EN_SHIFT                 29\r\n#define SARADC_CFG_DMA_EN_WIDTH                 1\r\n#define SARADC_CFG_DMA_EN_MASK                  (((1U << SARADC_CFG_DMA_EN_WIDTH) - 1U) << SARADC_CFG_DMA_EN_SHIFT)\r\n#define SARADC_CFG_DMA_EN_VALUE_DISABLE         0U\r\n#define SARADC_CFG_DMA_EN_BITS_DISABLE          (SARADC_CFG_DMA_EN_VALUE_DISABLE << SARADC_CFG_DMA_EN_SHIFT)\r\n#define SARADC_CFG_DMA_EN_VALUE_ENABLE          1U\r\n#define SARADC_CFG_DMA_EN_BITS_ENABLE           (SARADC_CFG_DMA_EN_VALUE_ENABLE << SARADC_CFG_DMA_EN_SHIFT)\r\n\r\n#define SARADC_START_ADDR                       (SARADC_BASE_ADDR + 0x0004U)\r\n#define SARADC_START                            (*(volatile uint32_t *)SARADC_START_ADDR)\r\n#define SARADC_START_START_SHIFT                0\r\n#define SARADC_START_START_WIDTH                1\r\n#define SARADC_START_START_MASK                 (((1U << SARADC_START_START_WIDTH) - 1U) << SARADC_START_START_SHIFT)\r\n#define SARADC_START_START_VALUE_DISABLE        0U\r\n#define SARADC_START_START_BITS_DISABLE         (SARADC_START_START_VALUE_DISABLE << SARADC_START_START_SHIFT)\r\n#define SARADC_START_START_VALUE_ENABLE         1U\r\n#define SARADC_START_START_BITS_ENABLE          (SARADC_START_START_VALUE_ENABLE << SARADC_START_START_SHIFT)\r\n\r\n#define SARADC_START_SOFT_RESET_SHIFT           2\r\n#define SARADC_START_SOFT_RESET_WIDTH           1\r\n#define SARADC_START_SOFT_RESET_MASK            (((1U << SARADC_START_SOFT_RESET_WIDTH) - 1U) << SARADC_START_SOFT_RESET_SHIFT)\r\n#define SARADC_START_SOFT_RESET_VALUE_ASSERT    0U\r\n#define SARADC_START_SOFT_RESET_BITS_ASSERT     (SARADC_START_SOFT_RESET_VALUE_ASSERT << SARADC_START_SOFT_RESET_SHIFT)\r\n#define SARADC_START_SOFT_RESET_VALUE_DEASSERT  1U\r\n#define SARADC_START_SOFT_RESET_BITS_DEASSERT   (SARADC_START_SOFT_RESET_VALUE_DEASSERT << SARADC_START_SOFT_RESET_SHIFT)\r\n\r\n#define SARADC_IE_ADDR                          (SARADC_BASE_ADDR + 0x0008U)\r\n#define SARADC_IE                               (*(volatile uint32_t *)SARADC_IE_ADDR)\r\n#define SARADC_IE_CHx_EOC_SHIFT                 0\r\n#define SARADC_IE_CHx_EOC_WIDTH                 16\r\n#define SARADC_IE_CHx_EOC_MASK                  (((1U << SARADC_IE_CHx_EOC_WIDTH) - 1U) << SARADC_IE_CHx_EOC_SHIFT)\r\n#define SARADC_IE_CHx_EOC_VALUE_NONE            0U\r\n#define SARADC_IE_CHx_EOC_BITS_NONE             (SARADC_IE_CHx_EOC_VALUE_NONE << SARADC_IE_CHx_EOC_SHIFT)\r\n#define SARADC_IE_CHx_EOC_VALUE_ALL             65535U\r\n#define SARADC_IE_CHx_EOC_BITS_ALL              (SARADC_IE_CHx_EOC_VALUE_ALL << SARADC_IE_CHx_EOC_SHIFT)\r\n\r\n#define SARADC_IE_FIFO_FULL_SHIFT               16\r\n#define SARADC_IE_FIFO_FULL_WIDTH               1\r\n#define SARADC_IE_FIFO_FULL_MASK                (((1U << SARADC_IE_FIFO_FULL_WIDTH) - 1U) << SARADC_IE_FIFO_FULL_SHIFT)\r\n#define SARADC_IE_FIFO_FULL_VALUE_DISABLE       0U\r\n#define SARADC_IE_FIFO_FULL_BITS_DISABLE        (SARADC_IE_FIFO_FULL_VALUE_DISABLE << SARADC_IE_FIFO_FULL_SHIFT)\r\n#define SARADC_IE_FIFO_FULL_VALUE_ENABLE        1U\r\n#define SARADC_IE_FIFO_FULL_BITS_ENABLE         (SARADC_IE_FIFO_FULL_VALUE_ENABLE << SARADC_IE_FIFO_FULL_SHIFT)\r\n\r\n#define SARADC_IE_FIFO_HFULL_SHIFT              17\r\n#define SARADC_IE_FIFO_HFULL_WIDTH              1\r\n#define SARADC_IE_FIFO_HFULL_MASK               (((1U << SARADC_IE_FIFO_HFULL_WIDTH) - 1U) << SARADC_IE_FIFO_HFULL_SHIFT)\r\n#define SARADC_IE_FIFO_HFULL_VALUE_DISABLE      0U\r\n#define SARADC_IE_FIFO_HFULL_BITS_DISABLE       (SARADC_IE_FIFO_HFULL_VALUE_DISABLE << SARADC_IE_FIFO_HFULL_SHIFT)\r\n#define SARADC_IE_FIFO_HFULL_VALUE_ENABLE       1U\r\n#define SARADC_IE_FIFO_HFULL_BITS_ENABLE        (SARADC_IE_FIFO_HFULL_VALUE_ENABLE << SARADC_IE_FIFO_HFULL_SHIFT)\r\n\r\n#define SARADC_IF_ADDR                          (SARADC_BASE_ADDR + 0x000CU)\r\n#define SARADC_IF                               (*(volatile uint32_t *)SARADC_IF_ADDR)\r\n#define SARADC_IF_CHx_EOC_SHIFT                 0\r\n#define SARADC_IF_CHx_EOC_WIDTH                 16\r\n#define SARADC_IF_CHx_EOC_MASK                  (((1U << SARADC_IF_CHx_EOC_WIDTH) - 1U) << SARADC_IF_CHx_EOC_SHIFT)\r\n#define SARADC_IF_FIFO_FULL_SHIFT               16\r\n#define SARADC_IF_FIFO_FULL_WIDTH               1\r\n#define SARADC_IF_FIFO_FULL_MASK                (((1U << SARADC_IF_FIFO_FULL_WIDTH) - 1U) << SARADC_IF_FIFO_FULL_SHIFT)\r\n#define SARADC_IF_FIFO_FULL_VALUE_NOT_SET       0U\r\n#define SARADC_IF_FIFO_FULL_BITS_NOT_SET        (SARADC_IF_FIFO_FULL_VALUE_NOT_SET << SARADC_IF_FIFO_FULL_SHIFT)\r\n#define SARADC_IF_FIFO_FULL_VALUE_SET           1U\r\n#define SARADC_IF_FIFO_FULL_BITS_SET            (SARADC_IF_FIFO_FULL_VALUE_SET << SARADC_IF_FIFO_FULL_SHIFT)\r\n\r\n#define SARADC_IF_FIFO_HFULL_SHIFT              17\r\n#define SARADC_IF_FIFO_HFULL_WIDTH              1\r\n#define SARADC_IF_FIFO_HFULL_MASK               (((1U << SARADC_IF_FIFO_HFULL_WIDTH) - 1U) << SARADC_IF_FIFO_HFULL_SHIFT)\r\n#define SARADC_IF_FIFO_HFULL_VALUE_NOT_SET      0U\r\n#define SARADC_IF_FIFO_HFULL_BITS_NOT_SET       (SARADC_IF_FIFO_HFULL_VALUE_NOT_SET << SARADC_IF_FIFO_HFULL_SHIFT)\r\n#define SARADC_IF_FIFO_HFULL_VALUE_SET          1U\r\n#define SARADC_IF_FIFO_HFULL_BITS_SET           (SARADC_IF_FIFO_HFULL_VALUE_SET << SARADC_IF_FIFO_HFULL_SHIFT)\r\n\r\n#define SARADC_CH0_ADDR                         (SARADC_BASE_ADDR + 0x0010U)\r\n#define SARADC_CH0                              (*(volatile uint32_t *)SARADC_CH0_ADDR)\r\n#define SARADC_EXTTRIG_SEL_ADDR                 (SARADC_BASE_ADDR + 0x00B0U)\r\n#define SARADC_EXTTRIG_SEL                      (*(volatile uint32_t *)SARADC_EXTTRIG_SEL_ADDR)\r\n\r\n#define SARADC_CALIB_OFFSET_ADDR                (SARADC_BASE_ADDR + 0x00F0U)\r\n#define SARADC_CALIB_OFFSET                     (*(volatile uint32_t *)SARADC_CALIB_OFFSET_ADDR)\r\n#define SARADC_CALIB_OFFSET_OFFSET_SHIFT        0\r\n#define SARADC_CALIB_OFFSET_OFFSET_WIDTH        8\r\n#define SARADC_CALIB_OFFSET_OFFSET_MASK         (((1U << SARADC_CALIB_OFFSET_OFFSET_WIDTH) - 1U) << SARADC_CALIB_OFFSET_OFFSET_SHIFT)\r\n#define SARADC_CALIB_OFFSET_VALID_SHIFT         16\r\n#define SARADC_CALIB_OFFSET_VALID_WIDTH         1\r\n#define SARADC_CALIB_OFFSET_VALID_MASK          (((1U << SARADC_CALIB_OFFSET_VALID_WIDTH) - 1U) << SARADC_CALIB_OFFSET_VALID_SHIFT)\r\n#define SARADC_CALIB_OFFSET_VALID_VALUE_NO      0U\r\n#define SARADC_CALIB_OFFSET_VALID_BITS_NO       (SARADC_CALIB_OFFSET_VALID_VALUE_NO << SARADC_CALIB_OFFSET_VALID_SHIFT)\r\n#define SARADC_CALIB_OFFSET_VALID_VALUE_YES     1U\r\n#define SARADC_CALIB_OFFSET_VALID_BITS_YES      (SARADC_CALIB_OFFSET_VALID_VALUE_YES << SARADC_CALIB_OFFSET_VALID_SHIFT)\r\n\r\n#define SARADC_CALIB_KD_ADDR                    (SARADC_BASE_ADDR + 0x00F4U)\r\n#define SARADC_CALIB_KD                         (*(volatile uint32_t *)SARADC_CALIB_KD_ADDR)\r\n#define SARADC_CALIB_KD_KD_SHIFT                0\r\n#define SARADC_CALIB_KD_KD_WIDTH                8\r\n#define SARADC_CALIB_KD_KD_MASK                 (((1U << SARADC_CALIB_KD_KD_WIDTH) - 1U) << SARADC_CALIB_KD_KD_SHIFT)\r\n#define SARADC_CALIB_KD_VALID_SHIFT             16\r\n#define SARADC_CALIB_KD_VALID_WIDTH             1\r\n#define SARADC_CALIB_KD_VALID_MASK              (((1U << SARADC_CALIB_KD_VALID_WIDTH) - 1U) << SARADC_CALIB_KD_VALID_SHIFT)\r\n#define SARADC_CALIB_KD_VALID_VALUE_NO          0U\r\n#define SARADC_CALIB_KD_VALID_BITS_NO           (SARADC_CALIB_KD_VALID_VALUE_NO << SARADC_CALIB_KD_VALID_SHIFT)\r\n#define SARADC_CALIB_KD_VALID_VALUE_YES         1U\r\n#define SARADC_CALIB_KD_VALID_BITS_YES          (SARADC_CALIB_KD_VALID_VALUE_YES << SARADC_CALIB_KD_VALID_SHIFT)\r\n\r\n/* -------- ADC_CHx -------- */\r\n\r\ntypedef struct {\r\n\tuint32_t STAT;\r\n\tuint32_t DATA;\r\n} ADC_Channel_t;\r\n\r\n#define ADC_CHx_STAT_EOC_SHIFT                  0\r\n#define ADC_CHx_STAT_EOC_WIDTH                  1\r\n#define ADC_CHx_STAT_EOC_MASK                   (((1U << ADC_CHx_STAT_EOC_WIDTH) - 1U) << ADC_CHx_STAT_EOC_SHIFT)\r\n#define ADC_CHx_STAT_EOC_VALUE_NOT_COMPLETE     0U\r\n#define ADC_CHx_STAT_EOC_BITS_NOT_COMPLETE      (ADC_CHx_STAT_EOC_VALUE_NOT_COMPLETE << ADC_CHx_STAT_EOC_SHIFT)\r\n#define ADC_CHx_STAT_EOC_VALUE_COMPLETE         1U\r\n#define ADC_CHx_STAT_EOC_BITS_COMPLETE          (ADC_CHx_STAT_EOC_VALUE_COMPLETE << ADC_CHx_STAT_EOC_SHIFT)\r\n\r\n#define ADC_CHx_DATA_DATA_SHIFT                 0\r\n#define ADC_CHx_DATA_DATA_WIDTH                 12\r\n#define ADC_CHx_DATA_DATA_MASK                  (((1U << ADC_CHx_DATA_DATA_WIDTH) - 1U) << ADC_CHx_DATA_DATA_SHIFT)\r\n#define ADC_CHx_DATA_NUM_SHIFT                  12\r\n#define ADC_CHx_DATA_NUM_WIDTH                  4\r\n#define ADC_CHx_DATA_NUM_MASK                   (((1U << ADC_CHx_DATA_NUM_WIDTH) - 1U) << ADC_CHx_DATA_NUM_SHIFT)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/spi.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_SPI_H\r\n#define HARDWARE_DP32G030_SPI_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- SPI0 -------- */\r\n#define SPI0_BASE_ADDR                       0x400B8000U\r\n#define SPI0_BASE_SIZE                       0x00000800U\r\n#define SPI0                                 ((volatile SPI_Port_t *)SPI0_BASE_ADDR)\r\n\r\n/* -------- SPI1 -------- */\r\n#define SPI1_BASE_ADDR                       0x400B8800U\r\n#define SPI1_BASE_SIZE                       0x00000800U\r\n#define SPI1                                 ((volatile SPI_Port_t *)SPI1_BASE_ADDR)\r\n\r\n/* -------- SPI -------- */\r\n\r\ntypedef struct {\r\n\tuint32_t CR;\r\n\tuint32_t WDR;\r\n\tuint32_t RDR;\r\n\tuint32_t Reserved_000C[1];\r\n\tuint32_t IE;\r\n\tuint32_t IF;\r\n\tuint32_t FIFOST;\r\n} SPI_Port_t;\r\n\r\n#define SPI_CR_SPR_SHIFT                     0\r\n#define SPI_CR_SPR_WIDTH                     3\r\n#define SPI_CR_SPR_MASK                      (((1U << SPI_CR_SPR_WIDTH) - 1U) << SPI_CR_SPR_SHIFT)\r\n#define SPI_CR_SPR_VALUE_FPCLK_DIV_4         0U\r\n#define SPI_CR_SPR_BITS_FPCLK_DIV_4          (SPI_CR_SPR_VALUE_FPCLK_DIV_4 << SPI_CR_SPR_SHIFT)\r\n#define SPI_CR_SPR_VALUE_FPCLK_DIV_8         1U\r\n#define SPI_CR_SPR_BITS_FPCLK_DIV_8          (SPI_CR_SPR_VALUE_FPCLK_DIV_8 << SPI_CR_SPR_SHIFT)\r\n#define SPI_CR_SPR_VALUE_FPCLK_DIV_16        2U\r\n#define SPI_CR_SPR_BITS_FPCLK_DIV_16         (SPI_CR_SPR_VALUE_FPCLK_DIV_16 << SPI_CR_SPR_SHIFT)\r\n#define SPI_CR_SPR_VALUE_FPCLK_DIV_32        3U\r\n#define SPI_CR_SPR_BITS_FPCLK_DIV_32         (SPI_CR_SPR_VALUE_FPCLK_DIV_32 << SPI_CR_SPR_SHIFT)\r\n#define SPI_CR_SPR_VALUE_FPCLK_DIV_64        4U\r\n#define SPI_CR_SPR_BITS_FPCLK_DIV_64         (SPI_CR_SPR_VALUE_FPCLK_DIV_64 << SPI_CR_SPR_SHIFT)\r\n#define SPI_CR_SPR_VALUE_FPCLK_DIV_128       5U\r\n#define SPI_CR_SPR_BITS_FPCLK_DIV_128        (SPI_CR_SPR_VALUE_FPCLK_DIV_128 << SPI_CR_SPR_SHIFT)\r\n#define SPI_CR_SPR_VALUE_FPCLK_DIV_256       6U\r\n#define SPI_CR_SPR_BITS_FPCLK_DIV_256        (SPI_CR_SPR_VALUE_FPCLK_DIV_256 << SPI_CR_SPR_SHIFT)\r\n#define SPI_CR_SPR_VALUE_FPCLK_DIV_512       7U\r\n#define SPI_CR_SPR_BITS_FPCLK_DIV_512        (SPI_CR_SPR_VALUE_FPCLK_DIV_512 << SPI_CR_SPR_SHIFT)\r\n\r\n#define SPI_CR_SPE_SHIFT                     3\r\n#define SPI_CR_SPE_WIDTH                     1\r\n#define SPI_CR_SPE_MASK                      (((1U << SPI_CR_SPE_WIDTH) - 1U) << SPI_CR_SPE_SHIFT)\r\n#define SPI_CR_SPE_VALUE_DISABLE             0U\r\n#define SPI_CR_SPE_BITS_DISABLE              (SPI_CR_SPE_VALUE_DISABLE << SPI_CR_SPE_SHIFT)\r\n#define SPI_CR_SPE_VALUE_ENABLE              1U\r\n#define SPI_CR_SPE_BITS_ENABLE               (SPI_CR_SPE_VALUE_ENABLE << SPI_CR_SPE_SHIFT)\r\n\r\n#define SPI_CR_CPHA_SHIFT                    4\r\n#define SPI_CR_CPHA_WIDTH                    1\r\n#define SPI_CR_CPHA_MASK                     (((1U << SPI_CR_CPHA_WIDTH) - 1U) << SPI_CR_CPHA_SHIFT)\r\n#define SPI_CR_CPOL_SHIFT                    5\r\n#define SPI_CR_CPOL_WIDTH                    1\r\n#define SPI_CR_CPOL_MASK                     (((1U << SPI_CR_CPOL_WIDTH) - 1U) << SPI_CR_CPOL_SHIFT)\r\n#define SPI_CR_MSTR_SHIFT                    6\r\n#define SPI_CR_MSTR_WIDTH                    1\r\n#define SPI_CR_MSTR_MASK                     (((1U << SPI_CR_MSTR_WIDTH) - 1U) << SPI_CR_MSTR_SHIFT)\r\n#define SPI_CR_LSB_SHIFT                     7\r\n#define SPI_CR_LSB_WIDTH                     1\r\n#define SPI_CR_LSB_MASK                      (((1U << SPI_CR_LSB_WIDTH) - 1U) << SPI_CR_LSB_SHIFT)\r\n#define SPI_CR_CPHA_DATA_HOLD_S_SHIFT        8\r\n#define SPI_CR_CPHA_DATA_HOLD_S_WIDTH        4\r\n#define SPI_CR_CPHA_DATA_HOLD_S_MASK         (((1U << SPI_CR_CPHA_DATA_HOLD_S_WIDTH) - 1U) << SPI_CR_CPHA_DATA_HOLD_S_SHIFT)\r\n#define SPI_CR_MSR_SSN_SHIFT                 12\r\n#define SPI_CR_MSR_SSN_WIDTH                 1\r\n#define SPI_CR_MSR_SSN_MASK                  (((1U << SPI_CR_MSR_SSN_WIDTH) - 1U) << SPI_CR_MSR_SSN_SHIFT)\r\n#define SPI_CR_MSR_SSN_VALUE_DISABLE         0U\r\n#define SPI_CR_MSR_SSN_BITS_DISABLE          (SPI_CR_MSR_SSN_VALUE_DISABLE << SPI_CR_MSR_SSN_SHIFT)\r\n#define SPI_CR_MSR_SSN_VALUE_ENABLE          1U\r\n#define SPI_CR_MSR_SSN_BITS_ENABLE           (SPI_CR_MSR_SSN_VALUE_ENABLE << SPI_CR_MSR_SSN_SHIFT)\r\n\r\n#define SPI_CR_RXDMAEN_SHIFT                 13\r\n#define SPI_CR_RXDMAEN_WIDTH                 1\r\n#define SPI_CR_RXDMAEN_MASK                  (((1U << SPI_CR_RXDMAEN_WIDTH) - 1U) << SPI_CR_RXDMAEN_SHIFT)\r\n#define SPI_CR_TXDMAEN_SHIFT                 14\r\n#define SPI_CR_TXDMAEN_WIDTH                 1\r\n#define SPI_CR_TXDMAEN_MASK                  (((1U << SPI_CR_TXDMAEN_WIDTH) - 1U) << SPI_CR_TXDMAEN_SHIFT)\r\n#define SPI_CR_RF_CLR_SHIFT                  15\r\n#define SPI_CR_RF_CLR_WIDTH                  1\r\n#define SPI_CR_RF_CLR_MASK                   (((1U << SPI_CR_RF_CLR_WIDTH) - 1U) << SPI_CR_RF_CLR_SHIFT)\r\n#define SPI_CR_TF_CLR_SHIFT                  16\r\n#define SPI_CR_TF_CLR_WIDTH                  1\r\n#define SPI_CR_TF_CLR_MASK                   (((1U << SPI_CR_TF_CLR_WIDTH) - 1U) << SPI_CR_TF_CLR_SHIFT)\r\n\r\n#define SPI_IE_RXFIFO_OVF_SHIFT              0\r\n#define SPI_IE_RXFIFO_OVF_WIDTH              1\r\n#define SPI_IE_RXFIFO_OVF_MASK               (((1U << SPI_IE_RXFIFO_OVF_WIDTH) - 1U) << SPI_IE_RXFIFO_OVF_SHIFT)\r\n#define SPI_IE_RXFIFO_OVF_VALUE_DISABLE      0U\r\n#define SPI_IE_RXFIFO_OVF_BITS_DISABLE       (SPI_IE_RXFIFO_OVF_VALUE_DISABLE << SPI_IE_RXFIFO_OVF_SHIFT)\r\n#define SPI_IE_RXFIFO_OVF_VALUE_ENABLE       1U\r\n#define SPI_IE_RXFIFO_OVF_BITS_ENABLE        (SPI_IE_RXFIFO_OVF_VALUE_ENABLE << SPI_IE_RXFIFO_OVF_SHIFT)\r\n\r\n#define SPI_IE_RXFIFO_FULL_SHIFT             1\r\n#define SPI_IE_RXFIFO_FULL_WIDTH             1\r\n#define SPI_IE_RXFIFO_FULL_MASK              (((1U << SPI_IE_RXFIFO_FULL_WIDTH) - 1U) << SPI_IE_RXFIFO_FULL_SHIFT)\r\n#define SPI_IE_RXFIFO_FULL_VALUE_DISABLE     0U\r\n#define SPI_IE_RXFIFO_FULL_BITS_DISABLE      (SPI_IE_RXFIFO_FULL_VALUE_DISABLE << SPI_IE_RXFIFO_FULL_SHIFT)\r\n#define SPI_IE_RXFIFO_FULL_VALUE_ENABLE      1U\r\n#define SPI_IE_RXFIFO_FULL_BITS_ENABLE       (SPI_IE_RXFIFO_FULL_VALUE_ENABLE << SPI_IE_RXFIFO_FULL_SHIFT)\r\n\r\n#define SPI_IE_RXFIFO_HFULL_SHIFT            2\r\n#define SPI_IE_RXFIFO_HFULL_WIDTH            1\r\n#define SPI_IE_RXFIFO_HFULL_MASK             (((1U << SPI_IE_RXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_RXFIFO_HFULL_SHIFT)\r\n#define SPI_IE_RXFIFO_HFULL_VALUE_DISABLE    0U\r\n#define SPI_IE_RXFIFO_HFULL_BITS_DISABLE     (SPI_IE_RXFIFO_HFULL_VALUE_DISABLE << SPI_IE_RXFIFO_HFULL_SHIFT)\r\n#define SPI_IE_RXFIFO_HFULL_VALUE_ENABLE     1U\r\n#define SPI_IE_RXFIFO_HFULL_BITS_ENABLE      (SPI_IE_RXFIFO_HFULL_VALUE_ENABLE << SPI_IE_RXFIFO_HFULL_SHIFT)\r\n\r\n#define SPI_IE_TXFIFO_EMPTY_SHIFT            3\r\n#define SPI_IE_TXFIFO_EMPTY_WIDTH            1\r\n#define SPI_IE_TXFIFO_EMPTY_MASK             (((1U << SPI_IE_TXFIFO_EMPTY_WIDTH) - 1U) << SPI_IE_TXFIFO_EMPTY_SHIFT)\r\n#define SPI_IE_TXFIFO_EMPTY_VALUE_DISABLE    0U\r\n#define SPI_IE_TXFIFO_EMPTY_BITS_DISABLE     (SPI_IE_TXFIFO_EMPTY_VALUE_DISABLE << SPI_IE_TXFIFO_EMPTY_SHIFT)\r\n#define SPI_IE_TXFIFO_EMPTY_VALUE_ENABLE     1U\r\n#define SPI_IE_TXFIFO_EMPTY_BITS_ENABLE      (SPI_IE_TXFIFO_EMPTY_VALUE_ENABLE << SPI_IE_TXFIFO_EMPTY_SHIFT)\r\n\r\n#define SPI_IE_TXFIFO_HFULL_SHIFT            4\r\n#define SPI_IE_TXFIFO_HFULL_WIDTH            1\r\n#define SPI_IE_TXFIFO_HFULL_MASK             (((1U << SPI_IE_TXFIFO_HFULL_WIDTH) - 1U) << SPI_IE_TXFIFO_HFULL_SHIFT)\r\n#define SPI_IE_TXFIFO_HFULL_VALUE_DISABLE    0U\r\n#define SPI_IE_TXFIFO_HFULL_BITS_DISABLE     (SPI_IE_TXFIFO_HFULL_VALUE_DISABLE << SPI_IE_TXFIFO_HFULL_SHIFT)\r\n#define SPI_IE_TXFIFO_HFULL_VALUE_ENABLE     1U\r\n#define SPI_IE_TXFIFO_HFULL_BITS_ENABLE      (SPI_IE_TXFIFO_HFULL_VALUE_ENABLE << SPI_IE_TXFIFO_HFULL_SHIFT)\r\n\r\n#define SPI_FIFOST_RFE_SHIFT                 0\r\n#define SPI_FIFOST_RFE_WIDTH                 1\r\n#define SPI_FIFOST_RFE_MASK                  (((1U << SPI_FIFOST_RFE_WIDTH) - 1U) << SPI_FIFOST_RFE_SHIFT)\r\n#define SPI_FIFOST_RFE_VALUE_NOT_EMPTY       0U\r\n#define SPI_FIFOST_RFE_BITS_NOT_EMPTY        (SPI_FIFOST_RFE_VALUE_NOT_EMPTY << SPI_FIFOST_RFE_SHIFT)\r\n#define SPI_FIFOST_RFE_VALUE_EMPTY           1U\r\n#define SPI_FIFOST_RFE_BITS_EMPTY            (SPI_FIFOST_RFE_VALUE_EMPTY << SPI_FIFOST_RFE_SHIFT)\r\n\r\n#define SPI_FIFOST_RFF_SHIFT                 1\r\n#define SPI_FIFOST_RFF_WIDTH                 1\r\n#define SPI_FIFOST_RFF_MASK                  (((1U << SPI_FIFOST_RFF_WIDTH) - 1U) << SPI_FIFOST_RFF_SHIFT)\r\n#define SPI_FIFOST_RFF_VALUE_NOT_FULL        0U\r\n#define SPI_FIFOST_RFF_BITS_NOT_FULL         (SPI_FIFOST_RFF_VALUE_NOT_FULL << SPI_FIFOST_RFF_SHIFT)\r\n#define SPI_FIFOST_RFF_VALUE_FULL            1U\r\n#define SPI_FIFOST_RFF_BITS_FULL             (SPI_FIFOST_RFF_VALUE_FULL << SPI_FIFOST_RFF_SHIFT)\r\n\r\n#define SPI_FIFOST_RFHF_SHIFT                2\r\n#define SPI_FIFOST_RFHF_WIDTH                1\r\n#define SPI_FIFOST_RFHF_MASK                 (((1U << SPI_FIFOST_RFHF_WIDTH) - 1U) << SPI_FIFOST_RFHF_SHIFT)\r\n#define SPI_FIFOST_RFHF_VALUE_NOT_HALF_FULL  0U\r\n#define SPI_FIFOST_RFHF_BITS_NOT_HALF_FULL   (SPI_FIFOST_RFHF_VALUE_NOT_HALF_FULL << SPI_FIFOST_RFHF_SHIFT)\r\n#define SPI_FIFOST_RFHF_VALUE_HALF_FULL      1U\r\n#define SPI_FIFOST_RFHF_BITS_HALF_FULL       (SPI_FIFOST_RFHF_VALUE_HALF_FULL << SPI_FIFOST_RFHF_SHIFT)\r\n\r\n#define SPI_FIFOST_TFE_SHIFT                 3\r\n#define SPI_FIFOST_TFE_WIDTH                 1\r\n#define SPI_FIFOST_TFE_MASK                  (((1U << SPI_FIFOST_TFE_WIDTH) - 1U) << SPI_FIFOST_TFE_SHIFT)\r\n#define SPI_FIFOST_TFE_VALUE_NOT_EMPTY       0U\r\n#define SPI_FIFOST_TFE_BITS_NOT_EMPTY        (SPI_FIFOST_TFE_VALUE_NOT_EMPTY << SPI_FIFOST_TFE_SHIFT)\r\n#define SPI_FIFOST_TFE_VALUE_EMPTY           1U\r\n#define SPI_FIFOST_TFE_BITS_EMPTY            (SPI_FIFOST_TFE_VALUE_EMPTY << SPI_FIFOST_TFE_SHIFT)\r\n\r\n#define SPI_FIFOST_TFF_SHIFT                 4\r\n#define SPI_FIFOST_TFF_WIDTH                 1\r\n#define SPI_FIFOST_TFF_MASK                  (((1U << SPI_FIFOST_TFF_WIDTH) - 1U) << SPI_FIFOST_TFF_SHIFT)\r\n#define SPI_FIFOST_TFF_VALUE_NOT_FULL        0U\r\n#define SPI_FIFOST_TFF_BITS_NOT_FULL         (SPI_FIFOST_TFF_VALUE_NOT_FULL << SPI_FIFOST_TFF_SHIFT)\r\n#define SPI_FIFOST_TFF_VALUE_FULL            1U\r\n#define SPI_FIFOST_TFF_BITS_FULL             (SPI_FIFOST_TFF_VALUE_FULL << SPI_FIFOST_TFF_SHIFT)\r\n\r\n#define SPI_FIFOST_TFHF_SHIFT                5\r\n#define SPI_FIFOST_TFHF_WIDTH                1\r\n#define SPI_FIFOST_TFHF_MASK                 (((1U << SPI_FIFOST_TFHF_WIDTH) - 1U) << SPI_FIFOST_TFHF_SHIFT)\r\n#define SPI_FIFOST_TFHF_VALUE_NOT_HALF_FULL  0U\r\n#define SPI_FIFOST_TFHF_BITS_NOT_HALF_FULL   (SPI_FIFOST_TFHF_VALUE_NOT_HALF_FULL << SPI_FIFOST_TFHF_SHIFT)\r\n#define SPI_FIFOST_TFHF_VALUE_HALF_FULL      1U\r\n#define SPI_FIFOST_TFHF_BITS_HALF_FULL       (SPI_FIFOST_TFHF_VALUE_HALF_FULL << SPI_FIFOST_TFHF_SHIFT)\r\n\r\n#define SPI_FIFOST_RF_LEVEL_SHIFT            6\r\n#define SPI_FIFOST_RF_LEVEL_WIDTH            3\r\n#define SPI_FIFOST_RF_LEVEL_MASK             (((1U << SPI_FIFOST_RF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_RF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_RF_LEVEL_VALUE_0_BYTE     0U\r\n#define SPI_FIFOST_RF_LEVEL_BITS_0_BYTE      (SPI_FIFOST_RF_LEVEL_VALUE_0_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_RF_LEVEL_VALUE_1_BYTE     1U\r\n#define SPI_FIFOST_RF_LEVEL_BITS_1_BYTE      (SPI_FIFOST_RF_LEVEL_VALUE_1_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_RF_LEVEL_VALUE_2_BYTE     2U\r\n#define SPI_FIFOST_RF_LEVEL_BITS_2_BYTE      (SPI_FIFOST_RF_LEVEL_VALUE_2_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_RF_LEVEL_VALUE_3_BYTE     3U\r\n#define SPI_FIFOST_RF_LEVEL_BITS_3_BYTE      (SPI_FIFOST_RF_LEVEL_VALUE_3_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_RF_LEVEL_VALUE_4_BYTE     4U\r\n#define SPI_FIFOST_RF_LEVEL_BITS_4_BYTE      (SPI_FIFOST_RF_LEVEL_VALUE_4_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_RF_LEVEL_VALUE_5_BYTE     5U\r\n#define SPI_FIFOST_RF_LEVEL_BITS_5_BYTE      (SPI_FIFOST_RF_LEVEL_VALUE_5_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_RF_LEVEL_VALUE_6_BYTE     6U\r\n#define SPI_FIFOST_RF_LEVEL_BITS_6_BYTE      (SPI_FIFOST_RF_LEVEL_VALUE_6_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_RF_LEVEL_VALUE_7_BYTE     7U\r\n#define SPI_FIFOST_RF_LEVEL_BITS_7_BYTE      (SPI_FIFOST_RF_LEVEL_VALUE_7_BYTE << SPI_FIFOST_RF_LEVEL_SHIFT)\r\n\r\n#define SPI_FIFOST_TF_LEVEL_SHIFT            9\r\n#define SPI_FIFOST_TF_LEVEL_WIDTH            3\r\n#define SPI_FIFOST_TF_LEVEL_MASK             (((1U << SPI_FIFOST_TF_LEVEL_WIDTH) - 1U) << SPI_FIFOST_TF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_TF_LEVEL_VALUE_0_BYTE     0U\r\n#define SPI_FIFOST_TF_LEVEL_BITS_0_BYTE      (SPI_FIFOST_TF_LEVEL_VALUE_0_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_TF_LEVEL_VALUE_1_BYTE     1U\r\n#define SPI_FIFOST_TF_LEVEL_BITS_1_BYTE      (SPI_FIFOST_TF_LEVEL_VALUE_1_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_TF_LEVEL_VALUE_2_BYTE     2U\r\n#define SPI_FIFOST_TF_LEVEL_BITS_2_BYTE      (SPI_FIFOST_TF_LEVEL_VALUE_2_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_TF_LEVEL_VALUE_3_BYTE     3U\r\n#define SPI_FIFOST_TF_LEVEL_BITS_3_BYTE      (SPI_FIFOST_TF_LEVEL_VALUE_3_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_TF_LEVEL_VALUE_4_BYTE     4U\r\n#define SPI_FIFOST_TF_LEVEL_BITS_4_BYTE      (SPI_FIFOST_TF_LEVEL_VALUE_4_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_TF_LEVEL_VALUE_5_BYTE     5U\r\n#define SPI_FIFOST_TF_LEVEL_BITS_5_BYTE      (SPI_FIFOST_TF_LEVEL_VALUE_5_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_TF_LEVEL_VALUE_6_BYTE     6U\r\n#define SPI_FIFOST_TF_LEVEL_BITS_6_BYTE      (SPI_FIFOST_TF_LEVEL_VALUE_6_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT)\r\n#define SPI_FIFOST_TF_LEVEL_VALUE_7_BYTE     7U\r\n#define SPI_FIFOST_TF_LEVEL_BITS_7_BYTE      (SPI_FIFOST_TF_LEVEL_VALUE_7_BYTE << SPI_FIFOST_TF_LEVEL_SHIFT)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/syscon.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_SYSCON_H\r\n#define HARDWARE_DP32G030_SYSCON_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- SYSCON -------- */\r\n#define SYSCON_BASE_ADDR                                0x40000000U\r\n#define SYSCON_BASE_SIZE                                0x00000800U\r\n\r\n#define SYSCON_CLK_SEL_ADDR                             (SYSCON_BASE_ADDR + 0x0000U)\r\n#define SYSCON_CLK_SEL                                  (*(volatile uint32_t *)SYSCON_CLK_SEL_ADDR)\r\n#define SYSCON_CLK_SEL_SYS_SHIFT                        0\r\n#define SYSCON_CLK_SEL_SYS_WIDTH                        1\r\n#define SYSCON_CLK_SEL_SYS_MASK                         (((1U << SYSCON_CLK_SEL_SYS_WIDTH) - 1U) << SYSCON_CLK_SEL_SYS_SHIFT)\r\n#define SYSCON_CLK_SEL_SYS_VALUE_RCHF                   0U\r\n#define SYSCON_CLK_SEL_SYS_BITS_RCHF                    (SYSCON_CLK_SEL_SYS_VALUE_RCHF << SYSCON_CLK_SEL_SYS_SHIFT)\r\n#define SYSCON_CLK_SEL_SYS_VALUE_DIV_CLK                1U\r\n#define SYSCON_CLK_SEL_SYS_BITS_DIV_CLK                 (SYSCON_CLK_SEL_SYS_VALUE_DIV_CLK << SYSCON_CLK_SEL_SYS_SHIFT)\r\n\r\n#define SYSCON_CLK_SEL_DIV_SHIFT                        1\r\n#define SYSCON_CLK_SEL_DIV_WIDTH                        3\r\n#define SYSCON_CLK_SEL_DIV_MASK                         (((1U << SYSCON_CLK_SEL_DIV_WIDTH) - 1U) << SYSCON_CLK_SEL_DIV_SHIFT)\r\n#define SYSCON_CLK_SEL_DIV_VALUE_1                      0U\r\n#define SYSCON_CLK_SEL_DIV_BITS_1                       (SYSCON_CLK_SEL_DIV_VALUE_1 << SYSCON_CLK_SEL_DIV_SHIFT)\r\n#define SYSCON_CLK_SEL_DIV_VALUE_2                      1U\r\n#define SYSCON_CLK_SEL_DIV_BITS_2                       (SYSCON_CLK_SEL_DIV_VALUE_2 << SYSCON_CLK_SEL_DIV_SHIFT)\r\n#define SYSCON_CLK_SEL_DIV_VALUE_4                      2U\r\n#define SYSCON_CLK_SEL_DIV_BITS_4                       (SYSCON_CLK_SEL_DIV_VALUE_4 << SYSCON_CLK_SEL_DIV_SHIFT)\r\n#define SYSCON_CLK_SEL_DIV_VALUE_8                      3U\r\n#define SYSCON_CLK_SEL_DIV_BITS_8                       (SYSCON_CLK_SEL_DIV_VALUE_8 << SYSCON_CLK_SEL_DIV_SHIFT)\r\n#define SYSCON_CLK_SEL_DIV_VALUE_16                     4U\r\n#define SYSCON_CLK_SEL_DIV_BITS_16                      (SYSCON_CLK_SEL_DIV_VALUE_16 << SYSCON_CLK_SEL_DIV_SHIFT)\r\n#define SYSCON_CLK_SEL_DIV_VALUE_32                     5U\r\n#define SYSCON_CLK_SEL_DIV_BITS_32                      (SYSCON_CLK_SEL_DIV_VALUE_32 << SYSCON_CLK_SEL_DIV_SHIFT)\r\n\r\n#define SYSCON_CLK_SEL_SRC_SHIFT                        4\r\n#define SYSCON_CLK_SEL_SRC_WIDTH                        3\r\n#define SYSCON_CLK_SEL_SRC_MASK                         (((1U << SYSCON_CLK_SEL_SRC_WIDTH) - 1U) << SYSCON_CLK_SEL_SRC_SHIFT)\r\n#define SYSCON_CLK_SEL_SRC_VALUE_RCHF                   0U\r\n#define SYSCON_CLK_SEL_SRC_BITS_RCHF                    (SYSCON_CLK_SEL_SRC_VALUE_RCHF << SYSCON_CLK_SEL_SRC_SHIFT)\r\n#define SYSCON_CLK_SEL_SRC_VALUE_RCLF                   1U\r\n#define SYSCON_CLK_SEL_SRC_BITS_RCLF                    (SYSCON_CLK_SEL_SRC_VALUE_RCLF << SYSCON_CLK_SEL_SRC_SHIFT)\r\n#define SYSCON_CLK_SEL_SRC_VALUE_XTAH                   2U\r\n#define SYSCON_CLK_SEL_SRC_BITS_XTAH                    (SYSCON_CLK_SEL_SRC_VALUE_XTAH << SYSCON_CLK_SEL_SRC_SHIFT)\r\n#define SYSCON_CLK_SEL_SRC_VALUE_XTAL                   3U\r\n#define SYSCON_CLK_SEL_SRC_BITS_XTAL                    (SYSCON_CLK_SEL_SRC_VALUE_XTAL << SYSCON_CLK_SEL_SRC_SHIFT)\r\n#define SYSCON_CLK_SEL_SRC_VALUE_PLL                    4U\r\n#define SYSCON_CLK_SEL_SRC_BITS_PLL                     (SYSCON_CLK_SEL_SRC_VALUE_PLL << SYSCON_CLK_SEL_SRC_SHIFT)\r\n\r\n#define SYSCON_CLK_SEL_W_PLL_SHIFT                      7\r\n#define SYSCON_CLK_SEL_W_PLL_WIDTH                      1\r\n#define SYSCON_CLK_SEL_W_PLL_MASK                       (((1U << SYSCON_CLK_SEL_W_PLL_WIDTH) - 1U) << SYSCON_CLK_SEL_W_PLL_SHIFT)\r\n#define SYSCON_CLK_SEL_W_PLL_VALUE_RCHF                 0U\r\n#define SYSCON_CLK_SEL_W_PLL_BITS_RCHF                  (SYSCON_CLK_SEL_W_PLL_VALUE_RCHF << SYSCON_CLK_SEL_W_PLL_SHIFT)\r\n#define SYSCON_CLK_SEL_W_PLL_VALUE_XTAH                 1U\r\n#define SYSCON_CLK_SEL_W_PLL_BITS_XTAH                  (SYSCON_CLK_SEL_W_PLL_VALUE_XTAH << SYSCON_CLK_SEL_W_PLL_SHIFT)\r\n\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT              9\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_WIDTH              2\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_MASK               (((1U << SYSCON_CLK_SEL_R_SARADC_SMPL_WIDTH) - 1U) << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT)\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV1         0U\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV1          (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV1 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT)\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV2         1U\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV2          (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV2 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT)\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV4         2U\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV4          (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV4 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT)\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV8         3U\r\n#define SYSCON_CLK_SEL_R_SARADC_SMPL_BITS_DIV8          (SYSCON_CLK_SEL_R_SARADC_SMPL_VALUE_DIV8 << SYSCON_CLK_SEL_R_SARADC_SMPL_SHIFT)\r\n\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT              10\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_WIDTH              2\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_MASK               (((1U << SYSCON_CLK_SEL_W_SARADC_SMPL_WIDTH) - 1U) << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT)\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV1         0U\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV1          (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV1 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT)\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV2         1U\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV2          (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV2 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT)\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV4         2U\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV4          (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV4 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT)\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV8         3U\r\n#define SYSCON_CLK_SEL_W_SARADC_SMPL_BITS_DIV8          (SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV8 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT)\r\n\r\n#define SYSCON_CLK_SEL_R_PLL_SHIFT                      11\r\n#define SYSCON_CLK_SEL_R_PLL_WIDTH                      1\r\n#define SYSCON_CLK_SEL_R_PLL_MASK                       (((1U << SYSCON_CLK_SEL_R_PLL_WIDTH) - 1U) << SYSCON_CLK_SEL_R_PLL_SHIFT)\r\n#define SYSCON_CLK_SEL_R_PLL_VALUE_RCHF                 0U\r\n#define SYSCON_CLK_SEL_R_PLL_BITS_RCHF                  (SYSCON_CLK_SEL_R_PLL_VALUE_RCHF << SYSCON_CLK_SEL_R_PLL_SHIFT)\r\n#define SYSCON_CLK_SEL_R_PLL_VALUE_XTAH                 1U\r\n#define SYSCON_CLK_SEL_R_PLL_BITS_XTAH                  (SYSCON_CLK_SEL_R_PLL_VALUE_XTAH << SYSCON_CLK_SEL_R_PLL_SHIFT)\r\n\r\n#define SYSCON_DIV_CLK_GATE_ADDR                        (SYSCON_BASE_ADDR + 0x0004U)\r\n#define SYSCON_DIV_CLK_GATE                             (*(volatile uint32_t *)SYSCON_DIV_CLK_GATE_ADDR)\r\n#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT          0\r\n#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH          1\r\n#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK           (((1U << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_WIDTH) - 1U) << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT)\r\n#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_DISABLE  0U\r\n#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE   (SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_DISABLE << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT)\r\n#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_ENABLE   1U\r\n#define SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_ENABLE    (SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_VALUE_ENABLE << SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_ADDR                        (SYSCON_BASE_ADDR + 0x0008U)\r\n#define SYSCON_DEV_CLK_GATE                             (*(volatile uint32_t *)SYSCON_DEV_CLK_GATE_ADDR)\r\n#define SYSCON_DEV_CLK_GATE_GPIOA_SHIFT                 0\r\n#define SYSCON_DEV_CLK_GATE_GPIOA_WIDTH                 1\r\n#define SYSCON_DEV_CLK_GATE_GPIOA_MASK                  (((1U << SYSCON_DEV_CLK_GATE_GPIOA_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_GPIOA_VALUE_DISABLE         0U\r\n#define SYSCON_DEV_CLK_GATE_GPIOA_BITS_DISABLE          (SYSCON_DEV_CLK_GATE_GPIOA_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_GPIOA_VALUE_ENABLE          1U\r\n#define SYSCON_DEV_CLK_GATE_GPIOA_BITS_ENABLE           (SYSCON_DEV_CLK_GATE_GPIOA_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOA_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_GPIOB_SHIFT                 1\r\n#define SYSCON_DEV_CLK_GATE_GPIOB_WIDTH                 1\r\n#define SYSCON_DEV_CLK_GATE_GPIOB_MASK                  (((1U << SYSCON_DEV_CLK_GATE_GPIOB_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_GPIOB_VALUE_DISABLE         0U\r\n#define SYSCON_DEV_CLK_GATE_GPIOB_BITS_DISABLE          (SYSCON_DEV_CLK_GATE_GPIOB_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_GPIOB_VALUE_ENABLE          1U\r\n#define SYSCON_DEV_CLK_GATE_GPIOB_BITS_ENABLE           (SYSCON_DEV_CLK_GATE_GPIOB_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOB_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_GPIOC_SHIFT                 2\r\n#define SYSCON_DEV_CLK_GATE_GPIOC_WIDTH                 1\r\n#define SYSCON_DEV_CLK_GATE_GPIOC_MASK                  (((1U << SYSCON_DEV_CLK_GATE_GPIOC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_GPIOC_VALUE_DISABLE         0U\r\n#define SYSCON_DEV_CLK_GATE_GPIOC_BITS_DISABLE          (SYSCON_DEV_CLK_GATE_GPIOC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_GPIOC_VALUE_ENABLE          1U\r\n#define SYSCON_DEV_CLK_GATE_GPIOC_BITS_ENABLE           (SYSCON_DEV_CLK_GATE_GPIOC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_GPIOC_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_IIC0_SHIFT                  4\r\n#define SYSCON_DEV_CLK_GATE_IIC0_WIDTH                  1\r\n#define SYSCON_DEV_CLK_GATE_IIC0_MASK                   (((1U << SYSCON_DEV_CLK_GATE_IIC0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_IIC0_VALUE_DISABLE          0U\r\n#define SYSCON_DEV_CLK_GATE_IIC0_BITS_DISABLE           (SYSCON_DEV_CLK_GATE_IIC0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IIC0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_IIC0_VALUE_ENABLE           1U\r\n#define SYSCON_DEV_CLK_GATE_IIC0_BITS_ENABLE            (SYSCON_DEV_CLK_GATE_IIC0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IIC0_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_IIC1_SHIFT                  5\r\n#define SYSCON_DEV_CLK_GATE_IIC1_WIDTH                  1\r\n#define SYSCON_DEV_CLK_GATE_IIC1_MASK                   (((1U << SYSCON_DEV_CLK_GATE_IIC1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IIC1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_IIC1_VALUE_DISABLE          0U\r\n#define SYSCON_DEV_CLK_GATE_IIC1_BITS_DISABLE           (SYSCON_DEV_CLK_GATE_IIC1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IIC1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_IIC1_VALUE_ENABLE           1U\r\n#define SYSCON_DEV_CLK_GATE_IIC1_BITS_ENABLE            (SYSCON_DEV_CLK_GATE_IIC1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IIC1_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_UART0_SHIFT                 6\r\n#define SYSCON_DEV_CLK_GATE_UART0_WIDTH                 1\r\n#define SYSCON_DEV_CLK_GATE_UART0_MASK                  (((1U << SYSCON_DEV_CLK_GATE_UART0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_UART0_VALUE_DISABLE         0U\r\n#define SYSCON_DEV_CLK_GATE_UART0_BITS_DISABLE          (SYSCON_DEV_CLK_GATE_UART0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_UART0_VALUE_ENABLE          1U\r\n#define SYSCON_DEV_CLK_GATE_UART0_BITS_ENABLE           (SYSCON_DEV_CLK_GATE_UART0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART0_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_UART1_SHIFT                 7\r\n#define SYSCON_DEV_CLK_GATE_UART1_WIDTH                 1\r\n#define SYSCON_DEV_CLK_GATE_UART1_MASK                  (((1U << SYSCON_DEV_CLK_GATE_UART1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_UART1_VALUE_DISABLE         0U\r\n#define SYSCON_DEV_CLK_GATE_UART1_BITS_DISABLE          (SYSCON_DEV_CLK_GATE_UART1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_UART1_VALUE_ENABLE          1U\r\n#define SYSCON_DEV_CLK_GATE_UART1_BITS_ENABLE           (SYSCON_DEV_CLK_GATE_UART1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART1_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_UART2_SHIFT                 8\r\n#define SYSCON_DEV_CLK_GATE_UART2_WIDTH                 1\r\n#define SYSCON_DEV_CLK_GATE_UART2_MASK                  (((1U << SYSCON_DEV_CLK_GATE_UART2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_UART2_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_UART2_VALUE_DISABLE         0U\r\n#define SYSCON_DEV_CLK_GATE_UART2_BITS_DISABLE          (SYSCON_DEV_CLK_GATE_UART2_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_UART2_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_UART2_VALUE_ENABLE          1U\r\n#define SYSCON_DEV_CLK_GATE_UART2_BITS_ENABLE           (SYSCON_DEV_CLK_GATE_UART2_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_UART2_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_SPI0_SHIFT                  10\r\n#define SYSCON_DEV_CLK_GATE_SPI0_WIDTH                  1\r\n#define SYSCON_DEV_CLK_GATE_SPI0_MASK                   (((1U << SYSCON_DEV_CLK_GATE_SPI0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_SPI0_VALUE_DISABLE          0U\r\n#define SYSCON_DEV_CLK_GATE_SPI0_BITS_DISABLE           (SYSCON_DEV_CLK_GATE_SPI0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SPI0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_SPI0_VALUE_ENABLE           1U\r\n#define SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE            (SYSCON_DEV_CLK_GATE_SPI0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SPI0_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_SPI1_SHIFT                  11\r\n#define SYSCON_DEV_CLK_GATE_SPI1_WIDTH                  1\r\n#define SYSCON_DEV_CLK_GATE_SPI1_MASK                   (((1U << SYSCON_DEV_CLK_GATE_SPI1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SPI1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_SPI1_VALUE_DISABLE          0U\r\n#define SYSCON_DEV_CLK_GATE_SPI1_BITS_DISABLE           (SYSCON_DEV_CLK_GATE_SPI1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SPI1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_SPI1_VALUE_ENABLE           1U\r\n#define SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE            (SYSCON_DEV_CLK_GATE_SPI1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SPI1_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT           12\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH           1\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_MASK            (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_DISABLE   0U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_BITS_DISABLE    (SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_ENABLE    1U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE0_BITS_ENABLE     (SYSCON_DEV_CLK_GATE_TIMER_BASE0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE0_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT           13\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH           1\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_MASK            (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_DISABLE   0U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_BITS_DISABLE    (SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_ENABLE    1U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE1_BITS_ENABLE     (SYSCON_DEV_CLK_GATE_TIMER_BASE1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE1_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT           14\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH           1\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_MASK            (((1U << SYSCON_DEV_CLK_GATE_TIMER_BASE2_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_DISABLE   0U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_BITS_DISABLE    (SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_ENABLE    1U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_BASE2_BITS_ENABLE     (SYSCON_DEV_CLK_GATE_TIMER_BASE2_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_BASE2_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT           15\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH           1\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_MASK            (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_DISABLE   0U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_BITS_DISABLE    (SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_ENABLE    1U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS0_BITS_ENABLE     (SYSCON_DEV_CLK_GATE_TIMER_PLUS0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS0_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT           16\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH           1\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_MASK            (((1U << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_DISABLE   0U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_BITS_DISABLE    (SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_ENABLE    1U\r\n#define SYSCON_DEV_CLK_GATE_TIMER_PLUS1_BITS_ENABLE     (SYSCON_DEV_CLK_GATE_TIMER_PLUS1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_TIMER_PLUS1_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT             17\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH             1\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE0_MASK              (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_DISABLE     0U\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE0_BITS_DISABLE      (SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_ENABLE      1U\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE0_BITS_ENABLE       (SYSCON_DEV_CLK_GATE_PWM_BASE0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_BASE0_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT             18\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH             1\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE1_MASK              (((1U << SYSCON_DEV_CLK_GATE_PWM_BASE1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_DISABLE     0U\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE1_BITS_DISABLE      (SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_ENABLE      1U\r\n#define SYSCON_DEV_CLK_GATE_PWM_BASE1_BITS_ENABLE       (SYSCON_DEV_CLK_GATE_PWM_BASE1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_BASE1_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT             20\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH             1\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_MASK              (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS0_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_DISABLE     0U\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_BITS_DISABLE      (SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_ENABLE      1U\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS0_BITS_ENABLE       (SYSCON_DEV_CLK_GATE_PWM_PLUS0_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS0_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT             21\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH             1\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_MASK              (((1U << SYSCON_DEV_CLK_GATE_PWM_PLUS1_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_DISABLE     0U\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_BITS_DISABLE      (SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_ENABLE      1U\r\n#define SYSCON_DEV_CLK_GATE_PWM_PLUS1_BITS_ENABLE       (SYSCON_DEV_CLK_GATE_PWM_PLUS1_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_PWM_PLUS1_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_RTC_SHIFT                   22\r\n#define SYSCON_DEV_CLK_GATE_RTC_WIDTH                   1\r\n#define SYSCON_DEV_CLK_GATE_RTC_MASK                    (((1U << SYSCON_DEV_CLK_GATE_RTC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_RTC_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_RTC_VALUE_DISABLE           0U\r\n#define SYSCON_DEV_CLK_GATE_RTC_BITS_DISABLE            (SYSCON_DEV_CLK_GATE_RTC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_RTC_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_RTC_VALUE_ENABLE            1U\r\n#define SYSCON_DEV_CLK_GATE_RTC_BITS_ENABLE             (SYSCON_DEV_CLK_GATE_RTC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_RTC_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_IWDT_SHIFT                  23\r\n#define SYSCON_DEV_CLK_GATE_IWDT_WIDTH                  1\r\n#define SYSCON_DEV_CLK_GATE_IWDT_MASK                   (((1U << SYSCON_DEV_CLK_GATE_IWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_IWDT_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_IWDT_VALUE_DISABLE          0U\r\n#define SYSCON_DEV_CLK_GATE_IWDT_BITS_DISABLE           (SYSCON_DEV_CLK_GATE_IWDT_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_IWDT_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_IWDT_VALUE_ENABLE           1U\r\n#define SYSCON_DEV_CLK_GATE_IWDT_BITS_ENABLE            (SYSCON_DEV_CLK_GATE_IWDT_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_IWDT_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_WWDT_SHIFT                  24\r\n#define SYSCON_DEV_CLK_GATE_WWDT_WIDTH                  1\r\n#define SYSCON_DEV_CLK_GATE_WWDT_MASK                   (((1U << SYSCON_DEV_CLK_GATE_WWDT_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_WWDT_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_WWDT_VALUE_DISABLE          0U\r\n#define SYSCON_DEV_CLK_GATE_WWDT_BITS_DISABLE           (SYSCON_DEV_CLK_GATE_WWDT_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_WWDT_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_WWDT_VALUE_ENABLE           1U\r\n#define SYSCON_DEV_CLK_GATE_WWDT_BITS_ENABLE            (SYSCON_DEV_CLK_GATE_WWDT_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_WWDT_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_SARADC_SHIFT                25\r\n#define SYSCON_DEV_CLK_GATE_SARADC_WIDTH                1\r\n#define SYSCON_DEV_CLK_GATE_SARADC_MASK                 (((1U << SYSCON_DEV_CLK_GATE_SARADC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_SARADC_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_SARADC_VALUE_DISABLE        0U\r\n#define SYSCON_DEV_CLK_GATE_SARADC_BITS_DISABLE         (SYSCON_DEV_CLK_GATE_SARADC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_SARADC_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_SARADC_VALUE_ENABLE         1U\r\n#define SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE          (SYSCON_DEV_CLK_GATE_SARADC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_SARADC_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_CRC_SHIFT                   27\r\n#define SYSCON_DEV_CLK_GATE_CRC_WIDTH                   1\r\n#define SYSCON_DEV_CLK_GATE_CRC_MASK                    (((1U << SYSCON_DEV_CLK_GATE_CRC_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_CRC_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_CRC_VALUE_DISABLE           0U\r\n#define SYSCON_DEV_CLK_GATE_CRC_BITS_DISABLE            (SYSCON_DEV_CLK_GATE_CRC_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_CRC_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_CRC_VALUE_ENABLE            1U\r\n#define SYSCON_DEV_CLK_GATE_CRC_BITS_ENABLE             (SYSCON_DEV_CLK_GATE_CRC_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_CRC_SHIFT)\r\n\r\n#define SYSCON_DEV_CLK_GATE_AES_SHIFT                   28\r\n#define SYSCON_DEV_CLK_GATE_AES_WIDTH                   1\r\n#define SYSCON_DEV_CLK_GATE_AES_MASK                    (((1U << SYSCON_DEV_CLK_GATE_AES_WIDTH) - 1U) << SYSCON_DEV_CLK_GATE_AES_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_AES_VALUE_DISABLE           0U\r\n#define SYSCON_DEV_CLK_GATE_AES_BITS_DISABLE            (SYSCON_DEV_CLK_GATE_AES_VALUE_DISABLE << SYSCON_DEV_CLK_GATE_AES_SHIFT)\r\n#define SYSCON_DEV_CLK_GATE_AES_VALUE_ENABLE            1U\r\n#define SYSCON_DEV_CLK_GATE_AES_BITS_ENABLE             (SYSCON_DEV_CLK_GATE_AES_VALUE_ENABLE << SYSCON_DEV_CLK_GATE_AES_SHIFT)\r\n\r\n#define SYSCON_RC_FREQ_DELTA_ADDR                       (SYSCON_BASE_ADDR + 0x0078U)\r\n#define SYSCON_RC_FREQ_DELTA                            (*(volatile uint32_t *)SYSCON_RC_FREQ_DELTA_ADDR)\r\n#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT           0\r\n#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH           10\r\n#define SYSCON_RC_FREQ_DELTA_RCLF_DELTA_MASK            (((1U << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_DELTA_SHIFT)\r\n#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT             10\r\n#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH             1\r\n#define SYSCON_RC_FREQ_DELTA_RCLF_SIG_MASK              (((1U << SYSCON_RC_FREQ_DELTA_RCLF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCLF_SIG_SHIFT)\r\n#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT           11\r\n#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH           20\r\n#define SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK            (((1U << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT)\r\n#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT             31\r\n#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH             1\r\n#define SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK              (((1U << SYSCON_RC_FREQ_DELTA_RCHF_SIG_WIDTH) - 1U) << SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT)\r\n\r\n#define SYSCON_VREF_VOLT_DELTA_ADDR                     (SYSCON_BASE_ADDR + 0x007CU)\r\n#define SYSCON_VREF_VOLT_DELTA                          (*(volatile uint32_t *)SYSCON_VREF_VOLT_DELTA_ADDR)\r\n#define SYSCON_CHIP_ID0_ADDR                            (SYSCON_BASE_ADDR + 0x0080U)\r\n#define SYSCON_CHIP_ID0                                 (*(volatile uint32_t *)SYSCON_CHIP_ID0_ADDR)\r\n#define SYSCON_CHIP_ID1_ADDR                            (SYSCON_BASE_ADDR + 0x0084U)\r\n#define SYSCON_CHIP_ID1                                 (*(volatile uint32_t *)SYSCON_CHIP_ID1_ADDR)\r\n#define SYSCON_CHIP_ID2_ADDR                            (SYSCON_BASE_ADDR + 0x0088U)\r\n#define SYSCON_CHIP_ID2                                 (*(volatile uint32_t *)SYSCON_CHIP_ID2_ADDR)\r\n#define SYSCON_CHIP_ID3_ADDR                            (SYSCON_BASE_ADDR + 0x008CU)\r\n#define SYSCON_CHIP_ID3                                 (*(volatile uint32_t *)SYSCON_CHIP_ID3_ADDR)\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "bsp/dp32g030/timer.h",
    "content": "//\n// Created by RUPC on 2024/1/8.\n//\n\n#ifndef HARDWARE_DP32G030_TIMER_H\n#define HARDWARE_DP32G030_TIMER_H\n#include <stdint.h>\n\n#define TIMERBASE0_ADD 0x40064000\n//TIMER0\n#define TIMERBASE0_EN_ADD (0X00+TIMERBASE0_ADD)\n#define TIMERBASE0_DIV_ADD (0X04+TIMERBASE0_ADD)\n#define TIMERBASE0_IE_ADD (0X10+TIMERBASE0_ADD)\n#define TIMERBASE0_IF_ADD (0X14+TIMERBASE0_ADD)\n#define TIMERBASE0_HIGH_LOAD_ADD (0X20+TIMERBASE0_ADD)\n#define TIMERBASE0_HIGH_CNT_ADD (0X24+TIMERBASE0_ADD)\n#define TIMERBASE0_LOW_LOAD_ADD (0X30+TIMERBASE0_ADD)\n#define TIMERBASE0_LOW_CNT_ADD (0X34+TIMERBASE0_ADD)\n\n#define TIMERBASE0_EN (*(volatile uint32_t *)TIMERBASE0_EN_ADD)\n#define TIMERBASE0_DIV (*(volatile uint32_t *)TIMERBASE0_DIV_ADD)\n#define TIMERBASE0_IE (*(volatile uint32_t *)TIMERBASE0_IE_ADD)\n#define TIMERBASE0_IF (*(volatile uint32_t *)TIMERBASE0_IF_ADD)\n#define TIMERBASE0_HIGH_LOAD (*(volatile uint32_t *)TIMERBASE0_HIGH_LOAD_ADD)\n#define TIMERBASE0_HIGH_CNT (*(volatile uint32_t *)TIMERBASE0_HIGH_CNT_ADD)\n#define TIMERBASE0_LOW_LOAD (*(volatile uint32_t *)TIMERBASE0_LOW_LOAD_ADD)\n#define TIMERBASE0_LOW_CNT (*(volatile uint32_t *)TIMERBASE0_LOW_CNT_ADD)\n\n\n\n\nextern uint32_t TIM0_CNT;\n\nvoid TIM0_INIT();\n\n#endif //UV_K5_FIRMWARE_CUSTOM_0_17_TIMER_H\n"
  },
  {
    "path": "bsp/dp32g030/uart.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n * Unless required by applicable law or agreed to in writing, software\r\n * distributed under the License is distributed on an \"AS IS\" BASIS,\r\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n * See the License for the specific language governing permissions and\r\n * limitations under the License.\r\n */\r\n\r\n#ifndef HARDWARE_DP32G030_UART_H\r\n#define HARDWARE_DP32G030_UART_H\r\n\r\n#if !defined(__ASSEMBLY__)\r\n#include <stdint.h>\r\n#endif\r\n\r\n/* -------- UART0 -------- */\r\n#define UART0_BASE_ADDR                     0x4006B000U\r\n#define UART0_BASE_SIZE                     0x00000800U\r\n#define UART0                               ((volatile UART_Port_t *)UART0_BASE_ADDR)\r\n\r\n/* -------- UART1 -------- */\r\n#define UART1_BASE_ADDR                     0x4006B800U\r\n#define UART1_BASE_SIZE                     0x00000800U\r\n#define UART1                               ((volatile UART_Port_t *)UART1_BASE_ADDR)\r\n\r\n/* -------- UART2 -------- */\r\n#define UART2_BASE_ADDR                     0x4006C000U\r\n#define UART2_BASE_SIZE                     0x00000800U\r\n#define UART2                               ((volatile UART_Port_t *)UART2_BASE_ADDR)\r\n\r\n/* -------- UART -------- */\r\n\r\ntypedef struct {\r\n\tuint32_t CTRL;\r\n\tuint32_t BAUD;\r\n\tuint32_t TDR;\r\n\tuint32_t RDR;\r\n\tuint32_t IE;\r\n\tuint32_t IF;\r\n\tuint32_t FIFO;\r\n\tuint32_t FC;\r\n\tuint32_t RXTO;\r\n} UART_Port_t;\r\n\r\n#define UART_CTRL_UARTEN_SHIFT              0\r\n#define UART_CTRL_UARTEN_WIDTH              1\r\n#define UART_CTRL_UARTEN_MASK               (((1U << UART_CTRL_UARTEN_WIDTH) - 1U) << UART_CTRL_UARTEN_SHIFT)\r\n#define UART_CTRL_UARTEN_VALUE_DISABLE      0U\r\n#define UART_CTRL_UARTEN_BITS_DISABLE       (UART_CTRL_UARTEN_VALUE_DISABLE << UART_CTRL_UARTEN_SHIFT)\r\n#define UART_CTRL_UARTEN_VALUE_ENABLE       1U\r\n#define UART_CTRL_UARTEN_BITS_ENABLE        (UART_CTRL_UARTEN_VALUE_ENABLE << UART_CTRL_UARTEN_SHIFT)\r\n\r\n#define UART_CTRL_RXEN_SHIFT                1\r\n#define UART_CTRL_RXEN_WIDTH                1\r\n#define UART_CTRL_RXEN_MASK                 (((1U << UART_CTRL_RXEN_WIDTH) - 1U) << UART_CTRL_RXEN_SHIFT)\r\n#define UART_CTRL_RXEN_VALUE_DISABLE        0U\r\n#define UART_CTRL_RXEN_BITS_DISABLE         (UART_CTRL_RXEN_VALUE_DISABLE << UART_CTRL_RXEN_SHIFT)\r\n#define UART_CTRL_RXEN_VALUE_ENABLE         1U\r\n#define UART_CTRL_RXEN_BITS_ENABLE          (UART_CTRL_RXEN_VALUE_ENABLE << UART_CTRL_RXEN_SHIFT)\r\n\r\n#define UART_CTRL_TXEN_SHIFT                2\r\n#define UART_CTRL_TXEN_WIDTH                1\r\n#define UART_CTRL_TXEN_MASK                 (((1U << UART_CTRL_TXEN_WIDTH) - 1U) << UART_CTRL_TXEN_SHIFT)\r\n#define UART_CTRL_TXEN_VALUE_DISABLE        0U\r\n#define UART_CTRL_TXEN_BITS_DISABLE         (UART_CTRL_TXEN_VALUE_DISABLE << UART_CTRL_TXEN_SHIFT)\r\n#define UART_CTRL_TXEN_VALUE_ENABLE         1U\r\n#define UART_CTRL_TXEN_BITS_ENABLE          (UART_CTRL_TXEN_VALUE_ENABLE << UART_CTRL_TXEN_SHIFT)\r\n\r\n#define UART_CTRL_RXDMAEN_SHIFT             3\r\n#define UART_CTRL_RXDMAEN_WIDTH             1\r\n#define UART_CTRL_RXDMAEN_MASK              (((1U << UART_CTRL_RXDMAEN_WIDTH) - 1U) << UART_CTRL_RXDMAEN_SHIFT)\r\n#define UART_CTRL_RXDMAEN_VALUE_DISABLE     0U\r\n#define UART_CTRL_RXDMAEN_BITS_DISABLE      (UART_CTRL_RXDMAEN_VALUE_DISABLE << UART_CTRL_RXDMAEN_SHIFT)\r\n#define UART_CTRL_RXDMAEN_VALUE_ENABLE      1U\r\n#define UART_CTRL_RXDMAEN_BITS_ENABLE       (UART_CTRL_RXDMAEN_VALUE_ENABLE << UART_CTRL_RXDMAEN_SHIFT)\r\n\r\n#define UART_CTRL_TXDMAEN_SHIFT             4\r\n#define UART_CTRL_TXDMAEN_WIDTH             1\r\n#define UART_CTRL_TXDMAEN_MASK              (((1U << UART_CTRL_TXDMAEN_WIDTH) - 1U) << UART_CTRL_TXDMAEN_SHIFT)\r\n#define UART_CTRL_TXDMAEN_VALUE_DISABLE     0U\r\n#define UART_CTRL_TXDMAEN_BITS_DISABLE      (UART_CTRL_TXDMAEN_VALUE_DISABLE << UART_CTRL_TXDMAEN_SHIFT)\r\n#define UART_CTRL_TXDMAEN_VALUE_ENABLE      1U\r\n#define UART_CTRL_TXDMAEN_BITS_ENABLE       (UART_CTRL_TXDMAEN_VALUE_ENABLE << UART_CTRL_TXDMAEN_SHIFT)\r\n\r\n#define UART_CTRL_NINEBIT_SHIFT             5\r\n#define UART_CTRL_NINEBIT_WIDTH             1\r\n#define UART_CTRL_NINEBIT_MASK              (((1U << UART_CTRL_NINEBIT_WIDTH) - 1U) << UART_CTRL_NINEBIT_SHIFT)\r\n#define UART_CTRL_NINEBIT_VALUE_DISABLE     0U\r\n#define UART_CTRL_NINEBIT_BITS_DISABLE      (UART_CTRL_NINEBIT_VALUE_DISABLE << UART_CTRL_NINEBIT_SHIFT)\r\n#define UART_CTRL_NINEBIT_VALUE_ENABLE      1U\r\n#define UART_CTRL_NINEBIT_BITS_ENABLE       (UART_CTRL_NINEBIT_VALUE_ENABLE << UART_CTRL_NINEBIT_SHIFT)\r\n\r\n#define UART_CTRL_PAREN_SHIFT               6\r\n#define UART_CTRL_PAREN_WIDTH               1\r\n#define UART_CTRL_PAREN_MASK                (((1U << UART_CTRL_PAREN_WIDTH) - 1U) << UART_CTRL_PAREN_SHIFT)\r\n#define UART_CTRL_PAREN_VALUE_DISABLE       0U\r\n#define UART_CTRL_PAREN_BITS_DISABLE        (UART_CTRL_PAREN_VALUE_DISABLE << UART_CTRL_PAREN_SHIFT)\r\n#define UART_CTRL_PAREN_VALUE_ENABLE        1U\r\n#define UART_CTRL_PAREN_BITS_ENABLE         (UART_CTRL_PAREN_VALUE_ENABLE << UART_CTRL_PAREN_SHIFT)\r\n\r\n#define UART_IE_TXDONE_SHIFT                2\r\n#define UART_IE_TXDONE_WIDTH                1\r\n#define UART_IE_TXDONE_MASK                 (((1U << UART_IE_TXDONE_WIDTH) - 1U) << UART_IE_TXDONE_SHIFT)\r\n#define UART_IE_TXDONE_VALUE_DISABLE        0U\r\n#define UART_IE_TXDONE_BITS_DISABLE         (UART_IE_TXDONE_VALUE_DISABLE << UART_IE_TXDONE_SHIFT)\r\n#define UART_IE_TXDONE_VALUE_ENABLE         1U\r\n#define UART_IE_TXDONE_BITS_ENABLE          (UART_IE_TXDONE_VALUE_ENABLE << UART_IE_TXDONE_SHIFT)\r\n\r\n#define UART_IE_PARITYE_SHIFT               3\r\n#define UART_IE_PARITYE_WIDTH               1\r\n#define UART_IE_PARITYE_MASK                (((1U << UART_IE_PARITYE_WIDTH) - 1U) << UART_IE_PARITYE_SHIFT)\r\n#define UART_IE_PARITYE_VALUE_DISABLE       0U\r\n#define UART_IE_PARITYE_BITS_DISABLE        (UART_IE_PARITYE_VALUE_DISABLE << UART_IE_PARITYE_SHIFT)\r\n#define UART_IE_PARITYE_VALUE_ENABLE        1U\r\n#define UART_IE_PARITYE_BITS_ENABLE         (UART_IE_PARITYE_VALUE_ENABLE << UART_IE_PARITYE_SHIFT)\r\n\r\n#define UART_IE_STOPE_SHIFT                 4\r\n#define UART_IE_STOPE_WIDTH                 1\r\n#define UART_IE_STOPE_MASK                  (((1U << UART_IE_STOPE_WIDTH) - 1U) << UART_IE_STOPE_SHIFT)\r\n#define UART_IE_STOPE_VALUE_DISABLE         0U\r\n#define UART_IE_STOPE_BITS_DISABLE          (UART_IE_STOPE_VALUE_DISABLE << UART_IE_STOPE_SHIFT)\r\n#define UART_IE_STOPE_VALUE_ENABLE          1U\r\n#define UART_IE_STOPE_BITS_ENABLE           (UART_IE_STOPE_VALUE_ENABLE << UART_IE_STOPE_SHIFT)\r\n\r\n#define UART_IE_RXTO_SHIFT                  5\r\n#define UART_IE_RXTO_WIDTH                  1\r\n#define UART_IE_RXTO_MASK                   (((1U << UART_IE_RXTO_WIDTH) - 1U) << UART_IE_RXTO_SHIFT)\r\n#define UART_IE_RXTO_VALUE_DISABLE          0U\r\n#define UART_IE_RXTO_BITS_DISABLE           (UART_IE_RXTO_VALUE_DISABLE << UART_IE_RXTO_SHIFT)\r\n#define UART_IE_RXTO_VALUE_ENABLE           1U\r\n#define UART_IE_RXTO_BITS_ENABLE            (UART_IE_RXTO_VALUE_ENABLE << UART_IE_RXTO_SHIFT)\r\n\r\n#define UART_IE_RXFIFO_SHIFT                6\r\n#define UART_IE_RXFIFO_WIDTH                1\r\n#define UART_IE_RXFIFO_MASK                 (((1U << UART_IE_RXFIFO_WIDTH) - 1U) << UART_IE_RXFIFO_SHIFT)\r\n#define UART_IE_RXFIFO_VALUE_DISABLE        0U\r\n#define UART_IE_RXFIFO_BITS_DISABLE         (UART_IE_RXFIFO_VALUE_DISABLE << UART_IE_RXFIFO_SHIFT)\r\n#define UART_IE_RXFIFO_VALUE_ENABLE         1U\r\n#define UART_IE_RXFIFO_BITS_ENABLE          (UART_IE_RXFIFO_VALUE_ENABLE << UART_IE_RXFIFO_SHIFT)\r\n\r\n#define UART_IE_TXFIFO_SHIFT                7\r\n#define UART_IE_TXFIFO_WIDTH                1\r\n#define UART_IE_TXFIFO_MASK                 (((1U << UART_IE_TXFIFO_WIDTH) - 1U) << UART_IE_TXFIFO_SHIFT)\r\n#define UART_IE_TXFIFO_VALUE_DISABLE        0U\r\n#define UART_IE_TXFIFO_BITS_DISABLE         (UART_IE_TXFIFO_VALUE_DISABLE << UART_IE_TXFIFO_SHIFT)\r\n#define UART_IE_TXFIFO_VALUE_ENABLE         1U\r\n#define UART_IE_TXFIFO_BITS_ENABLE          (UART_IE_TXFIFO_VALUE_ENABLE << UART_IE_TXFIFO_SHIFT)\r\n\r\n#define UART_IE_RXFIFO_OVF_SHIFT            8\r\n#define UART_IE_RXFIFO_OVF_WIDTH            1\r\n#define UART_IE_RXFIFO_OVF_MASK             (((1U << UART_IE_RXFIFO_OVF_WIDTH) - 1U) << UART_IE_RXFIFO_OVF_SHIFT)\r\n#define UART_IE_RXFIFO_OVF_VALUE_DISABLE    0U\r\n#define UART_IE_RXFIFO_OVF_BITS_DISABLE     (UART_IE_RXFIFO_OVF_VALUE_DISABLE << UART_IE_RXFIFO_OVF_SHIFT)\r\n#define UART_IE_RXFIFO_OVF_VALUE_ENABLE     1U\r\n#define UART_IE_RXFIFO_OVF_BITS_ENABLE      (UART_IE_RXFIFO_OVF_VALUE_ENABLE << UART_IE_RXFIFO_OVF_SHIFT)\r\n\r\n#define UART_IE_ABRD_OVF_SHIFT              9\r\n#define UART_IE_ABRD_OVF_WIDTH              1\r\n#define UART_IE_ABRD_OVF_MASK               (((1U << UART_IE_ABRD_OVF_WIDTH) - 1U) << UART_IE_ABRD_OVF_SHIFT)\r\n#define UART_IE_ABRD_OVF_VALUE_DISABLE      0U\r\n#define UART_IE_ABRD_OVF_BITS_DISABLE       (UART_IE_ABRD_OVF_VALUE_DISABLE << UART_IE_ABRD_OVF_SHIFT)\r\n#define UART_IE_ABRD_OVF_VALUE_ENABLE       1U\r\n#define UART_IE_ABRD_OVF_BITS_ENABLE        (UART_IE_ABRD_OVF_VALUE_ENABLE << UART_IE_ABRD_OVF_SHIFT)\r\n\r\n#define UART_IF_TXDONE_SHIFT                2\r\n#define UART_IF_TXDONE_WIDTH                1\r\n#define UART_IF_TXDONE_MASK                 (((1U << UART_IF_TXDONE_WIDTH) - 1U) << UART_IF_TXDONE_SHIFT)\r\n#define UART_IF_TXDONE_VALUE_NOT_SET        0U\r\n#define UART_IF_TXDONE_BITS_NOT_SET         (UART_IF_TXDONE_VALUE_NOT_SET << UART_IF_TXDONE_SHIFT)\r\n#define UART_IF_TXDONE_VALUE_SET            1U\r\n#define UART_IF_TXDONE_BITS_SET             (UART_IF_TXDONE_VALUE_SET << UART_IF_TXDONE_SHIFT)\r\n\r\n#define UART_IF_PARITYE_SHIFT               3\r\n#define UART_IF_PARITYE_WIDTH               1\r\n#define UART_IF_PARITYE_MASK                (((1U << UART_IF_PARITYE_WIDTH) - 1U) << UART_IF_PARITYE_SHIFT)\r\n#define UART_IF_PARITYE_VALUE_NOT_SET       0U\r\n#define UART_IF_PARITYE_BITS_NOT_SET        (UART_IF_PARITYE_VALUE_NOT_SET << UART_IF_PARITYE_SHIFT)\r\n#define UART_IF_PARITYE_VALUE_SET           1U\r\n#define UART_IF_PARITYE_BITS_SET            (UART_IF_PARITYE_VALUE_SET << UART_IF_PARITYE_SHIFT)\r\n\r\n#define UART_IF_STOPE_SHIFT                 4\r\n#define UART_IF_STOPE_WIDTH                 1\r\n#define UART_IF_STOPE_MASK                  (((1U << UART_IF_STOPE_WIDTH) - 1U) << UART_IF_STOPE_SHIFT)\r\n#define UART_IF_STOPE_VALUE_NOT_SET         0U\r\n#define UART_IF_STOPE_BITS_NOT_SET          (UART_IF_STOPE_VALUE_NOT_SET << UART_IF_STOPE_SHIFT)\r\n#define UART_IF_STOPE_VALUE_SET             1U\r\n#define UART_IF_STOPE_BITS_SET              (UART_IF_STOPE_VALUE_SET << UART_IF_STOPE_SHIFT)\r\n\r\n#define UART_IF_RXTO_SHIFT                  5\r\n#define UART_IF_RXTO_WIDTH                  1\r\n#define UART_IF_RXTO_MASK                   (((1U << UART_IF_RXTO_WIDTH) - 1U) << UART_IF_RXTO_SHIFT)\r\n#define UART_IF_RXTO_VALUE_NOT_SET          0U\r\n#define UART_IF_RXTO_BITS_NOT_SET           (UART_IF_RXTO_VALUE_NOT_SET << UART_IF_RXTO_SHIFT)\r\n#define UART_IF_RXTO_VALUE_SET              1U\r\n#define UART_IF_RXTO_BITS_SET               (UART_IF_RXTO_VALUE_SET << UART_IF_RXTO_SHIFT)\r\n\r\n#define UART_IF_RXFIFO_SHIFT                6\r\n#define UART_IF_RXFIFO_WIDTH                1\r\n#define UART_IF_RXFIFO_MASK                 (((1U << UART_IF_RXFIFO_WIDTH) - 1U) << UART_IF_RXFIFO_SHIFT)\r\n#define UART_IF_RXFIFO_VALUE_NOT_SET        0U\r\n#define UART_IF_RXFIFO_BITS_NOT_SET         (UART_IF_RXFIFO_VALUE_NOT_SET << UART_IF_RXFIFO_SHIFT)\r\n#define UART_IF_RXFIFO_VALUE_SET            1U\r\n#define UART_IF_RXFIFO_BITS_SET             (UART_IF_RXFIFO_VALUE_SET << UART_IF_RXFIFO_SHIFT)\r\n\r\n#define UART_IF_TXFIFO_SHIFT                7\r\n#define UART_IF_TXFIFO_WIDTH                1\r\n#define UART_IF_TXFIFO_MASK                 (((1U << UART_IF_TXFIFO_WIDTH) - 1U) << UART_IF_TXFIFO_SHIFT)\r\n#define UART_IF_TXFIFO_VALUE_NOT_SET        0U\r\n#define UART_IF_TXFIFO_BITS_NOT_SET         (UART_IF_TXFIFO_VALUE_NOT_SET << UART_IF_TXFIFO_SHIFT)\r\n#define UART_IF_TXFIFO_VALUE_SET            1U\r\n#define UART_IF_TXFIFO_BITS_SET             (UART_IF_TXFIFO_VALUE_SET << UART_IF_TXFIFO_SHIFT)\r\n\r\n#define UART_IF_RXFIFO_OVF_SHIFT            8\r\n#define UART_IF_RXFIFO_OVF_WIDTH            1\r\n#define UART_IF_RXFIFO_OVF_MASK             (((1U << UART_IF_RXFIFO_OVF_WIDTH) - 1U) << UART_IF_RXFIFO_OVF_SHIFT)\r\n#define UART_IF_RXFIFO_OVF_VALUE_NOT_SET    0U\r\n#define UART_IF_RXFIFO_OVF_BITS_NOT_SET     (UART_IF_RXFIFO_OVF_VALUE_NOT_SET << UART_IF_RXFIFO_OVF_SHIFT)\r\n#define UART_IF_RXFIFO_OVF_VALUE_SET        1U\r\n#define UART_IF_RXFIFO_OVF_BITS_SET         (UART_IF_RXFIFO_OVF_VALUE_SET << UART_IF_RXFIFO_OVF_SHIFT)\r\n\r\n#define UART_IF_ABRD_OVF_SHIFT              9\r\n#define UART_IF_ABRD_OVF_WIDTH              1\r\n#define UART_IF_ABRD_OVF_MASK               (((1U << UART_IF_ABRD_OVF_WIDTH) - 1U) << UART_IF_ABRD_OVF_SHIFT)\r\n#define UART_IF_ABRD_OVF_VALUE_NOT_SET      0U\r\n#define UART_IF_ABRD_OVF_BITS_NOT_SET       (UART_IF_ABRD_OVF_VALUE_NOT_SET << UART_IF_ABRD_OVF_SHIFT)\r\n#define UART_IF_ABRD_OVF_VALUE_SET          1U\r\n#define UART_IF_ABRD_OVF_BITS_SET           (UART_IF_ABRD_OVF_VALUE_SET << UART_IF_ABRD_OVF_SHIFT)\r\n\r\n#define UART_IF_RXFIFO_EMPTY_SHIFT          10\r\n#define UART_IF_RXFIFO_EMPTY_WIDTH          1\r\n#define UART_IF_RXFIFO_EMPTY_MASK           (((1U << UART_IF_RXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_RXFIFO_EMPTY_SHIFT)\r\n#define UART_IF_RXFIFO_EMPTY_VALUE_NOT_SET  0U\r\n#define UART_IF_RXFIFO_EMPTY_BITS_NOT_SET   (UART_IF_RXFIFO_EMPTY_VALUE_NOT_SET << UART_IF_RXFIFO_EMPTY_SHIFT)\r\n#define UART_IF_RXFIFO_EMPTY_VALUE_SET      1U\r\n#define UART_IF_RXFIFO_EMPTY_BITS_SET       (UART_IF_RXFIFO_EMPTY_VALUE_SET << UART_IF_RXFIFO_EMPTY_SHIFT)\r\n\r\n#define UART_IF_RXFIFO_FULL_SHIFT           11\r\n#define UART_IF_RXFIFO_FULL_WIDTH           1\r\n#define UART_IF_RXFIFO_FULL_MASK            (((1U << UART_IF_RXFIFO_FULL_WIDTH) - 1U) << UART_IF_RXFIFO_FULL_SHIFT)\r\n#define UART_IF_RXFIFO_FULL_VALUE_NOT_SET   0U\r\n#define UART_IF_RXFIFO_FULL_BITS_NOT_SET    (UART_IF_RXFIFO_FULL_VALUE_NOT_SET << UART_IF_RXFIFO_FULL_SHIFT)\r\n#define UART_IF_RXFIFO_FULL_VALUE_SET       1U\r\n#define UART_IF_RXFIFO_FULL_BITS_SET        (UART_IF_RXFIFO_FULL_VALUE_SET << UART_IF_RXFIFO_FULL_SHIFT)\r\n\r\n#define UART_IF_RXFIFO_HFULL_SHIFT          12\r\n#define UART_IF_RXFIFO_HFULL_WIDTH          1\r\n#define UART_IF_RXFIFO_HFULL_MASK           (((1U << UART_IF_RXFIFO_HFULL_WIDTH) - 1U) << UART_IF_RXFIFO_HFULL_SHIFT)\r\n#define UART_IF_RXFIFO_HFULL_VALUE_NOT_SET  0U\r\n#define UART_IF_RXFIFO_HFULL_BITS_NOT_SET   (UART_IF_RXFIFO_HFULL_VALUE_NOT_SET << UART_IF_RXFIFO_HFULL_SHIFT)\r\n#define UART_IF_RXFIFO_HFULL_VALUE_SET      1U\r\n#define UART_IF_RXFIFO_HFULL_BITS_SET       (UART_IF_RXFIFO_HFULL_VALUE_SET << UART_IF_RXFIFO_HFULL_SHIFT)\r\n\r\n#define UART_IF_TXFIFO_EMPTY_SHIFT          13\r\n#define UART_IF_TXFIFO_EMPTY_WIDTH          1\r\n#define UART_IF_TXFIFO_EMPTY_MASK           (((1U << UART_IF_TXFIFO_EMPTY_WIDTH) - 1U) << UART_IF_TXFIFO_EMPTY_SHIFT)\r\n#define UART_IF_TXFIFO_EMPTY_VALUE_NOT_SET  0U\r\n#define UART_IF_TXFIFO_EMPTY_BITS_NOT_SET   (UART_IF_TXFIFO_EMPTY_VALUE_NOT_SET << UART_IF_TXFIFO_EMPTY_SHIFT)\r\n#define UART_IF_TXFIFO_EMPTY_VALUE_SET      1U\r\n#define UART_IF_TXFIFO_EMPTY_BITS_SET       (UART_IF_TXFIFO_EMPTY_VALUE_SET << UART_IF_TXFIFO_EMPTY_SHIFT)\r\n\r\n#define UART_IF_TXFIFO_FULL_SHIFT           14\r\n#define UART_IF_TXFIFO_FULL_WIDTH           1\r\n#define UART_IF_TXFIFO_FULL_MASK            (((1U << UART_IF_TXFIFO_FULL_WIDTH) - 1U) << UART_IF_TXFIFO_FULL_SHIFT)\r\n#define UART_IF_TXFIFO_FULL_VALUE_NOT_SET   0U\r\n#define UART_IF_TXFIFO_FULL_BITS_NOT_SET    (UART_IF_TXFIFO_FULL_VALUE_NOT_SET << UART_IF_TXFIFO_FULL_SHIFT)\r\n#define UART_IF_TXFIFO_FULL_VALUE_SET       1U\r\n#define UART_IF_TXFIFO_FULL_BITS_SET        (UART_IF_TXFIFO_FULL_VALUE_SET << UART_IF_TXFIFO_FULL_SHIFT)\r\n\r\n#define UART_IF_TXFIFO_HFULL_SHIFT          15\r\n#define UART_IF_TXFIFO_HFULL_WIDTH          1\r\n#define UART_IF_TXFIFO_HFULL_MASK           (((1U << UART_IF_TXFIFO_HFULL_WIDTH) - 1U) << UART_IF_TXFIFO_HFULL_SHIFT)\r\n#define UART_IF_TXFIFO_HFULL_VALUE_NOT_SET  0U\r\n#define UART_IF_TXFIFO_HFULL_BITS_NOT_SET   (UART_IF_TXFIFO_HFULL_VALUE_NOT_SET << UART_IF_TXFIFO_HFULL_SHIFT)\r\n#define UART_IF_TXFIFO_HFULL_VALUE_SET      1U\r\n#define UART_IF_TXFIFO_HFULL_BITS_SET       (UART_IF_TXFIFO_HFULL_VALUE_SET << UART_IF_TXFIFO_HFULL_SHIFT)\r\n\r\n#define UART_IF_TXBUSY_SHIFT                16\r\n#define UART_IF_TXBUSY_WIDTH                1\r\n#define UART_IF_TXBUSY_MASK                 (((1U << UART_IF_TXBUSY_WIDTH) - 1U) << UART_IF_TXBUSY_SHIFT)\r\n#define UART_IF_TXBUSY_VALUE_NOT_SET        0U\r\n#define UART_IF_TXBUSY_BITS_NOT_SET         (UART_IF_TXBUSY_VALUE_NOT_SET << UART_IF_TXBUSY_SHIFT)\r\n#define UART_IF_TXBUSY_VALUE_SET            1U\r\n#define UART_IF_TXBUSY_BITS_SET             (UART_IF_TXBUSY_VALUE_SET << UART_IF_TXBUSY_SHIFT)\r\n\r\n#define UART_IF_RF_LEVEL_SHIFT              17\r\n#define UART_IF_RF_LEVEL_WIDTH              3\r\n#define UART_IF_RF_LEVEL_MASK               (((1U << UART_IF_RF_LEVEL_WIDTH) - 1U) << UART_IF_RF_LEVEL_SHIFT)\r\n#define UART_IF_RF_LEVEL_VALUE_0_8_BYTE     0U\r\n#define UART_IF_RF_LEVEL_BITS_0_8_BYTE      (UART_IF_RF_LEVEL_VALUE_0_8_BYTE << UART_IF_RF_LEVEL_SHIFT)\r\n#define UART_IF_RF_LEVEL_VALUE_1_BYTE       1U\r\n#define UART_IF_RF_LEVEL_BITS_1_BYTE        (UART_IF_RF_LEVEL_VALUE_1_BYTE << UART_IF_RF_LEVEL_SHIFT)\r\n#define UART_IF_RF_LEVEL_VALUE_2_BYTE       2U\r\n#define UART_IF_RF_LEVEL_BITS_2_BYTE        (UART_IF_RF_LEVEL_VALUE_2_BYTE << UART_IF_RF_LEVEL_SHIFT)\r\n#define UART_IF_RF_LEVEL_VALUE_3_BYTE       3U\r\n#define UART_IF_RF_LEVEL_BITS_3_BYTE        (UART_IF_RF_LEVEL_VALUE_3_BYTE << UART_IF_RF_LEVEL_SHIFT)\r\n#define UART_IF_RF_LEVEL_VALUE_4_BYTE       4U\r\n#define UART_IF_RF_LEVEL_BITS_4_BYTE        (UART_IF_RF_LEVEL_VALUE_4_BYTE << UART_IF_RF_LEVEL_SHIFT)\r\n#define UART_IF_RF_LEVEL_VALUE_5_BYTE       5U\r\n#define UART_IF_RF_LEVEL_BITS_5_BYTE        (UART_IF_RF_LEVEL_VALUE_5_BYTE << UART_IF_RF_LEVEL_SHIFT)\r\n#define UART_IF_RF_LEVEL_VALUE_6_BYTE       6U\r\n#define UART_IF_RF_LEVEL_BITS_6_BYTE        (UART_IF_RF_LEVEL_VALUE_6_BYTE << UART_IF_RF_LEVEL_SHIFT)\r\n#define UART_IF_RF_LEVEL_VALUE_7_BYTE       7U\r\n#define UART_IF_RF_LEVEL_BITS_7_BYTE        (UART_IF_RF_LEVEL_VALUE_7_BYTE << UART_IF_RF_LEVEL_SHIFT)\r\n\r\n#define UART_IF_TF_LEVEL_SHIFT              20\r\n#define UART_IF_TF_LEVEL_WIDTH              3\r\n#define UART_IF_TF_LEVEL_MASK               (((1U << UART_IF_TF_LEVEL_WIDTH) - 1U) << UART_IF_TF_LEVEL_SHIFT)\r\n#define UART_IF_TF_LEVEL_VALUE_0_8_BYTE     0U\r\n#define UART_IF_TF_LEVEL_BITS_0_8_BYTE      (UART_IF_TF_LEVEL_VALUE_0_8_BYTE << UART_IF_TF_LEVEL_SHIFT)\r\n#define UART_IF_TF_LEVEL_VALUE_1_BYTE       1U\r\n#define UART_IF_TF_LEVEL_BITS_1_BYTE        (UART_IF_TF_LEVEL_VALUE_1_BYTE << UART_IF_TF_LEVEL_SHIFT)\r\n#define UART_IF_TF_LEVEL_VALUE_2_BYTE       2U\r\n#define UART_IF_TF_LEVEL_BITS_2_BYTE        (UART_IF_TF_LEVEL_VALUE_2_BYTE << UART_IF_TF_LEVEL_SHIFT)\r\n#define UART_IF_TF_LEVEL_VALUE_3_BYTE       3U\r\n#define UART_IF_TF_LEVEL_BITS_3_BYTE        (UART_IF_TF_LEVEL_VALUE_3_BYTE << UART_IF_TF_LEVEL_SHIFT)\r\n#define UART_IF_TF_LEVEL_VALUE_4_BYTE       4U\r\n#define UART_IF_TF_LEVEL_BITS_4_BYTE        (UART_IF_TF_LEVEL_VALUE_4_BYTE << UART_IF_TF_LEVEL_SHIFT)\r\n#define UART_IF_TF_LEVEL_VALUE_5_BYTE       5U\r\n#define UART_IF_TF_LEVEL_BITS_5_BYTE        (UART_IF_TF_LEVEL_VALUE_5_BYTE << UART_IF_TF_LEVEL_SHIFT)\r\n#define UART_IF_TF_LEVEL_VALUE_6_BYTE       6U\r\n#define UART_IF_TF_LEVEL_BITS_6_BYTE        (UART_IF_TF_LEVEL_VALUE_6_BYTE << UART_IF_TF_LEVEL_SHIFT)\r\n#define UART_IF_TF_LEVEL_VALUE_7_BYTE       7U\r\n#define UART_IF_TF_LEVEL_BITS_7_BYTE        (UART_IF_TF_LEVEL_VALUE_7_BYTE << UART_IF_TF_LEVEL_SHIFT)\r\n\r\n#define UART_FIFO_RF_LEVEL_SHIFT            0\r\n#define UART_FIFO_RF_LEVEL_WIDTH            3\r\n#define UART_FIFO_RF_LEVEL_MASK             (((1U << UART_FIFO_RF_LEVEL_WIDTH) - 1U) << UART_FIFO_RF_LEVEL_SHIFT)\r\n#define UART_FIFO_RF_LEVEL_VALUE_1_BYTE     0U\r\n#define UART_FIFO_RF_LEVEL_BITS_1_BYTE      (UART_FIFO_RF_LEVEL_VALUE_1_BYTE << UART_FIFO_RF_LEVEL_SHIFT)\r\n#define UART_FIFO_RF_LEVEL_VALUE_2_BYTE     1U\r\n#define UART_FIFO_RF_LEVEL_BITS_2_BYTE      (UART_FIFO_RF_LEVEL_VALUE_2_BYTE << UART_FIFO_RF_LEVEL_SHIFT)\r\n#define UART_FIFO_RF_LEVEL_VALUE_3_BYTE     2U\r\n#define UART_FIFO_RF_LEVEL_BITS_3_BYTE      (UART_FIFO_RF_LEVEL_VALUE_3_BYTE << UART_FIFO_RF_LEVEL_SHIFT)\r\n#define UART_FIFO_RF_LEVEL_VALUE_4_BYTE     3U\r\n#define UART_FIFO_RF_LEVEL_BITS_4_BYTE      (UART_FIFO_RF_LEVEL_VALUE_4_BYTE << UART_FIFO_RF_LEVEL_SHIFT)\r\n#define UART_FIFO_RF_LEVEL_VALUE_5_BYTE     4U\r\n#define UART_FIFO_RF_LEVEL_BITS_5_BYTE      (UART_FIFO_RF_LEVEL_VALUE_5_BYTE << UART_FIFO_RF_LEVEL_SHIFT)\r\n#define UART_FIFO_RF_LEVEL_VALUE_6_BYTE     5U\r\n#define UART_FIFO_RF_LEVEL_BITS_6_BYTE      (UART_FIFO_RF_LEVEL_VALUE_6_BYTE << UART_FIFO_RF_LEVEL_SHIFT)\r\n#define UART_FIFO_RF_LEVEL_VALUE_7_BYTE     6U\r\n#define UART_FIFO_RF_LEVEL_BITS_7_BYTE      (UART_FIFO_RF_LEVEL_VALUE_7_BYTE << UART_FIFO_RF_LEVEL_SHIFT)\r\n#define UART_FIFO_RF_LEVEL_VALUE_8_BYTE     7U\r\n#define UART_FIFO_RF_LEVEL_BITS_8_BYTE      (UART_FIFO_RF_LEVEL_VALUE_8_BYTE << UART_FIFO_RF_LEVEL_SHIFT)\r\n\r\n#define UART_FIFO_TF_LEVEL_SHIFT            3\r\n#define UART_FIFO_TF_LEVEL_WIDTH            3\r\n#define UART_FIFO_TF_LEVEL_MASK             (((1U << UART_FIFO_TF_LEVEL_WIDTH) - 1U) << UART_FIFO_TF_LEVEL_SHIFT)\r\n#define UART_FIFO_TF_LEVEL_VALUE_0_BYTE     0U\r\n#define UART_FIFO_TF_LEVEL_BITS_0_BYTE      (UART_FIFO_TF_LEVEL_VALUE_0_BYTE << UART_FIFO_TF_LEVEL_SHIFT)\r\n#define UART_FIFO_TF_LEVEL_VALUE_1_BYTE     1U\r\n#define UART_FIFO_TF_LEVEL_BITS_1_BYTE      (UART_FIFO_TF_LEVEL_VALUE_1_BYTE << UART_FIFO_TF_LEVEL_SHIFT)\r\n#define UART_FIFO_TF_LEVEL_VALUE_2_BYTE     2U\r\n#define UART_FIFO_TF_LEVEL_BITS_2_BYTE      (UART_FIFO_TF_LEVEL_VALUE_2_BYTE << UART_FIFO_TF_LEVEL_SHIFT)\r\n#define UART_FIFO_TF_LEVEL_VALUE_3_BYTE     3U\r\n#define UART_FIFO_TF_LEVEL_BITS_3_BYTE      (UART_FIFO_TF_LEVEL_VALUE_3_BYTE << UART_FIFO_TF_LEVEL_SHIFT)\r\n#define UART_FIFO_TF_LEVEL_VALUE_4_BYTE     4U\r\n#define UART_FIFO_TF_LEVEL_BITS_4_BYTE      (UART_FIFO_TF_LEVEL_VALUE_4_BYTE << UART_FIFO_TF_LEVEL_SHIFT)\r\n#define UART_FIFO_TF_LEVEL_VALUE_5_BYTE     5U\r\n#define UART_FIFO_TF_LEVEL_BITS_5_BYTE      (UART_FIFO_TF_LEVEL_VALUE_5_BYTE << UART_FIFO_TF_LEVEL_SHIFT)\r\n#define UART_FIFO_TF_LEVEL_VALUE_6_BYTE     6U\r\n#define UART_FIFO_TF_LEVEL_BITS_6_BYTE      (UART_FIFO_TF_LEVEL_VALUE_6_BYTE << UART_FIFO_TF_LEVEL_SHIFT)\r\n#define UART_FIFO_TF_LEVEL_VALUE_7_BYTE     7U\r\n#define UART_FIFO_TF_LEVEL_BITS_7_BYTE      (UART_FIFO_TF_LEVEL_VALUE_7_BYTE << UART_FIFO_TF_LEVEL_SHIFT)\r\n\r\n#define UART_FIFO_RF_CLR_SHIFT              6\r\n#define UART_FIFO_RF_CLR_WIDTH              1\r\n#define UART_FIFO_RF_CLR_MASK               (((1U << UART_FIFO_RF_CLR_WIDTH) - 1U) << UART_FIFO_RF_CLR_SHIFT)\r\n#define UART_FIFO_RF_CLR_VALUE_DISABLE      0U\r\n#define UART_FIFO_RF_CLR_BITS_DISABLE       (UART_FIFO_RF_CLR_VALUE_DISABLE << UART_FIFO_RF_CLR_SHIFT)\r\n#define UART_FIFO_RF_CLR_VALUE_ENABLE       1U\r\n#define UART_FIFO_RF_CLR_BITS_ENABLE        (UART_FIFO_RF_CLR_VALUE_ENABLE << UART_FIFO_RF_CLR_SHIFT)\r\n\r\n#define UART_FIFO_TF_CLR_SHIFT              7\r\n#define UART_FIFO_TF_CLR_WIDTH              1\r\n#define UART_FIFO_TF_CLR_MASK               (((1U << UART_FIFO_TF_CLR_WIDTH) - 1U) << UART_FIFO_TF_CLR_SHIFT)\r\n#define UART_FIFO_TF_CLR_VALUE_DISABLE      0U\r\n#define UART_FIFO_TF_CLR_BITS_DISABLE       (UART_FIFO_TF_CLR_VALUE_DISABLE << UART_FIFO_TF_CLR_SHIFT)\r\n#define UART_FIFO_TF_CLR_VALUE_ENABLE       1U\r\n#define UART_FIFO_TF_CLR_BITS_ENABLE        (UART_FIFO_TF_CLR_VALUE_ENABLE << UART_FIFO_TF_CLR_SHIFT)\r\n\r\n#define UART_FC_CTSEN_SHIFT                 0\r\n#define UART_FC_CTSEN_WIDTH                 1\r\n#define UART_FC_CTSEN_MASK                  (((1U << UART_FC_CTSEN_WIDTH) - 1U) << UART_FC_CTSEN_SHIFT)\r\n#define UART_FC_CTSEN_VALUE_DISABLE         0U\r\n#define UART_FC_CTSEN_BITS_DISABLE          (UART_FC_CTSEN_VALUE_DISABLE << UART_FC_CTSEN_SHIFT)\r\n#define UART_FC_CTSEN_VALUE_ENABLE          1U\r\n#define UART_FC_CTSEN_BITS_ENABLE           (UART_FC_CTSEN_VALUE_ENABLE << UART_FC_CTSEN_SHIFT)\r\n\r\n#define UART_FC_RTSEN_SHIFT                 1\r\n#define UART_FC_RTSEN_WIDTH                 1\r\n#define UART_FC_RTSEN_MASK                  (((1U << UART_FC_RTSEN_WIDTH) - 1U) << UART_FC_RTSEN_SHIFT)\r\n#define UART_FC_RTSEN_VALUE_DISABLE         0U\r\n#define UART_FC_RTSEN_BITS_DISABLE          (UART_FC_RTSEN_VALUE_DISABLE << UART_FC_RTSEN_SHIFT)\r\n#define UART_FC_RTSEN_VALUE_ENABLE          1U\r\n#define UART_FC_RTSEN_BITS_ENABLE           (UART_FC_RTSEN_VALUE_ENABLE << UART_FC_RTSEN_SHIFT)\r\n\r\n#define UART_FC_CTSPOL_SHIFT                2\r\n#define UART_FC_CTSPOL_WIDTH                1\r\n#define UART_FC_CTSPOL_MASK                 (((1U << UART_FC_CTSPOL_WIDTH) - 1U) << UART_FC_CTSPOL_SHIFT)\r\n#define UART_FC_CTSPOL_VALUE_LOW            0U\r\n#define UART_FC_CTSPOL_BITS_LOW             (UART_FC_CTSPOL_VALUE_LOW << UART_FC_CTSPOL_SHIFT)\r\n#define UART_FC_CTSPOL_VALUE_HIGH           1U\r\n#define UART_FC_CTSPOL_BITS_HIGH            (UART_FC_CTSPOL_VALUE_HIGH << UART_FC_CTSPOL_SHIFT)\r\n\r\n#define UART_FC_RTSPOL_SHIFT                3\r\n#define UART_FC_RTSPOL_WIDTH                1\r\n#define UART_FC_RTSPOL_MASK                 (((1U << UART_FC_RTSPOL_WIDTH) - 1U) << UART_FC_RTSPOL_SHIFT)\r\n#define UART_FC_RTSPOL_VALUE_LOW            0U\r\n#define UART_FC_RTSPOL_BITS_LOW             (UART_FC_RTSPOL_VALUE_LOW << UART_FC_RTSPOL_SHIFT)\r\n#define UART_FC_RTSPOL_VALUE_HIGH           1U\r\n#define UART_FC_RTSPOL_BITS_HIGH            (UART_FC_RTSPOL_VALUE_HIGH << UART_FC_RTSPOL_SHIFT)\r\n\r\n#define UART_FC_CTS_SIGNAL_SHIFT            4\r\n#define UART_FC_CTS_SIGNAL_WIDTH            1\r\n#define UART_FC_CTS_SIGNAL_MASK             (((1U << UART_FC_CTS_SIGNAL_WIDTH) - 1U) << UART_FC_CTS_SIGNAL_SHIFT)\r\n#define UART_FC_CTS_SIGNAL_VALUE_LOW        0U\r\n#define UART_FC_CTS_SIGNAL_BITS_LOW         (UART_FC_CTS_SIGNAL_VALUE_LOW << UART_FC_CTS_SIGNAL_SHIFT)\r\n#define UART_FC_CTS_SIGNAL_VALUE_HIGH       1U\r\n#define UART_FC_CTS_SIGNAL_BITS_HIGH        (UART_FC_CTS_SIGNAL_VALUE_HIGH << UART_FC_CTS_SIGNAL_SHIFT)\r\n\r\n#define UART_FC_RTS_SIGNAL_SHIFT            5\r\n#define UART_FC_RTS_SIGNAL_WIDTH            1\r\n#define UART_FC_RTS_SIGNAL_MASK             (((1U << UART_FC_RTS_SIGNAL_WIDTH) - 1U) << UART_FC_RTS_SIGNAL_SHIFT)\r\n#define UART_FC_RTS_SIGNAL_VALUE_LOW        0U\r\n#define UART_FC_RTS_SIGNAL_BITS_LOW         (UART_FC_RTS_SIGNAL_VALUE_LOW << UART_FC_RTS_SIGNAL_SHIFT)\r\n#define UART_FC_RTS_SIGNAL_VALUE_HIGH       1U\r\n#define UART_FC_RTS_SIGNAL_BITS_HIGH        (UART_FC_RTS_SIGNAL_VALUE_HIGH << UART_FC_RTS_SIGNAL_SHIFT)\r\n\r\n\r\n#endif\r\n\r\n"
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    "content": "# This is the CMakeCache file.\n# For build in directory: c:/Users/RUPC/Desktop/losehu/uv-k5-firmware-custom/build\n# It was generated by CMake: C:/Program Files/CMake/bin/cmake.exe\n# You can edit this file to change values found and used by cmake.\n# If you do not want to change any of the values, simply exit the editor.\n# If you do want to change a value, simply edit, save, and exit the editor.\n# The syntax for the file is as follows:\n# KEY:TYPE=VALUE\n# KEY is the name of a variable in the cache.\n# TYPE is a hint to GUIs for the type of VALUE, DO NOT EDIT TYPE!.\n# VALUE is the current value for the KEY.\n\n########################\n# EXTERNAL cache entries\n########################\n\n//No help, variable specified on the command line.\nCMAKE_BUILD_TYPE:STRING=Debug\n\n//No help, variable specified on the command line.\nCMAKE_CXX_COMPILER:FILEPATH=C:/Qt/Qt5.14.2/Tools/mingw730_64/bin/g++.exe\n\n//No help, variable specified on the command line.\nCMAKE_C_COMPILER:FILEPATH=C:/Qt/Qt5.14.2/Tools/mingw730_64/bin/gcc.exe\n\n//No help, variable specified on the command line.\nCMAKE_EXPORT_COMPILE_COMMANDS:BOOL=TRUE\n\n\n########################\n# INTERNAL cache entries\n########################\n\n//This is the directory where this CMakeCache.txt was created\nCMAKE_CACHEFILE_DIR:INTERNAL=c:/Users/RUPC/Desktop/losehu/uv-k5-firmware-custom/build\n//Major version of cmake used to create the current loaded cache\nCMAKE_CACHE_MAJOR_VERSION:INTERNAL=3\n//Minor version of cmake used to create the current loaded cache\nCMAKE_CACHE_MINOR_VERSION:INTERNAL=22\n//Patch version of cmake used to create the current loaded cache\nCMAKE_CACHE_PATCH_VERSION:INTERNAL=6\n//Path to CMake executable.\nCMAKE_COMMAND:INTERNAL=C:/Program Files/CMake/bin/cmake.exe\n//Path to cpack program executable.\nCMAKE_CPACK_COMMAND:INTERNAL=C:/Program Files/CMake/bin/cpack.exe\n//Path to ctest program executable.\nCMAKE_CTEST_COMMAND:INTERNAL=C:/Program Files/CMake/bin/ctest.exe\n//Path to cache edit program executable.\nCMAKE_EDIT_COMMAND:INTERNAL=C:/Program Files/CMake/bin/cmake-gui.exe\n//Name of external makefile project generator.\nCMAKE_EXTRA_GENERATOR:INTERNAL=\n//Name of generator.\nCMAKE_GENERATOR:INTERNAL=MinGW Makefiles\n//Generator instance identifier.\nCMAKE_GENERATOR_INSTANCE:INTERNAL=\n//Name of generator platform.\nCMAKE_GENERATOR_PLATFORM:INTERNAL=\n//Name of generator toolset.\nCMAKE_GENERATOR_TOOLSET:INTERNAL=\n//Source directory with the top level CMakeLists.txt file for this\n// project\nCMAKE_HOME_DIRECTORY:INTERNAL=C:/Users/RUPC/Desktop/losehu/uv-k5-firmware-custom\n//number of local generators\nCMAKE_NUMBER_OF_MAKEFILES:INTERNAL=1\n//Path to CMake installation.\nCMAKE_ROOT:INTERNAL=C:/Program Files/CMake/share/cmake-3.22\n\n"
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  {
    "path": "chinese.h",
    "content": "//\n// Created by RUPC on 2023/11/30.\n//\n\n#ifndef UV_K5_FIRMWARE_CUSTOM_0_17_CHINESE_H\n#define UV_K5_FIRMWARE_CUSTOM_0_17_CHINESE_H\n#include \"font.h\"\n#if ENABLE_CHINESE_FULL!=4 || defined(ENABLE_ENGLISH)\n#ifdef ENABLE_ENGLISH\n#define 步进频率 \"Step\"\n#define 接收数字亚音 \"RxDCS\"\n#define 接收模拟亚音 \"RxCTCS\"\n#define 发送数字亚音 \"TxDCS\"\n#define 发送模拟亚音 \"TxCTCS\"\n#define 频差方向 \"TxODir\"\n#define 频差频率 \"TxOffs\"\n#define 加密 \"Scramb\"\n#define 遇忙禁发 \"BusyCL\"\n#define 压扩 \"Compnd\"\n#define 存置信道 \"ChSave\"\n#define 删除信道 \"ChDele\"\n#define 命名信道 \"ChName\"\n#define 信道扫描列表 \"SList\"\n#define 扫描列表1 \"SList1\"\n#define 扫描列表2 \"SList2\"\n#define 搜索恢复模式 \"ScnRev\"\n#define 发送超时 \"TxTOut\"\n#define 省电模式 \"BatSav\"\n#define 麦克风增益 \"Mic\"\n#define 信道显示模式 \"ChDisp\"\n#define 自动背光 \"BackLt\"\n#define 背光亮度 \"Light\"\n#define 首尾音 \"Roger\"\n#define MDC_ID \"MDC ID\"\n#define 尾音消除 \"STE\"\n#define 过中继尾音消除 \"RP STE\"\n#define 按键即呼 \"1 Call\"\n#define DTMF_ID \"D ID\"\n#define DTMF上线码 \"UPCode\"\n#define DTMF下线码 \"DWCode\"\n#define DTMF发送 \"PTT ID\"\n#define DTMF侧音 \"D ST\"\n#define DTMF响应 \"D Resp\"\n#define DTMF复位 \"D Hold\"\n#define DTMF预载波 \"D Prel\"\n#define DTMF联系人 \"D List\"\n#define DTMF显示 \"D Live\"\n#define AM自动增益 \"AM Fix\"\n#define 收发模式 \"RxMode\"\n#define 静噪等级 \"Sql\"\n#define 频段解锁 \"F Lock\"\n#define 两百M发射 \"Tx 200\"\n#define 三百五十M发射 \"Tx 350\"\n#define 五百M发射 \"Tx 500\"\n#define 三百五十M接收 \"350 En\"\n#define 电池调压 \"BatCal\"\n#define 电池大小 \"BatVol\"\n#define 参数复位 \"Reset\"\n#define 发送等于接收 \"OFF\"\n#define 发送等于接收加偏移 \"+\"\n#define 发送等于接收减偏移 \"-\"\n#define 关闭 \"OFF\"\n#define 开启 \"ON\"\n#define 一级 \"1:1\"\n#define 二级 \"1:2\"\n#define 三级 \"1:3\"\n#define 四级 \"1:4\"\n#define 三十秒 \"30 sec\"\n#define 一分 \"1 min\"\n#define 两分 \"2 min\"\n#define 三分 \"3 min\"\n#define 四分 \"4 min\"\n#define 五分 \"5 min\"\n#define 六分 \"6 min\"\n#define 七分 \"7 min\"\n#define 八分 \"8 min\"\n#define 九分 \"9 min\"\n#define 十五分 \"15 min\"\n#define 主信道接收发射 \"MAIN\\nONLY\"\n#define 双信道接收 \"DUAL RX\\nRESPOND\"\n#define 主信道发射副信道接收 \"CROSS\\nBAND\"\n#define 主信道发射双信道接收 \"MAIN TX\\nDUAL RX\"\n#define 遇信号5秒后搜索 \"TIME\"\n#define 信号停止后搜索 \"CARRIER\"\n#define 遇信号后停止搜索 \"STOP\"\n#define 频率 \"FREQ\"\n#define 信道号 \"CHANNEL\\nNUMBER\"\n#define 名称 \"NAME\"\n#define 名称加频率 \"NAME +\\nFREQ\"\n#define 不响应 \"DO\\nNOTHING\"\n#define 本地响铃 \"RING\"\n#define 回复响应 \"REPLY\"\n#define 本地响铃回复响应 \"BOTH\"\n#define 不发送 \"OFF\"\n#define 上线码 \"UP CODE\"\n#define 下线码 \"DOWN CODE\"\n#define 上线加下线码 \"UP+DOWN\\nCODE\"\n#define Quindar码 \"APOLLO\\nQUINDAR\"\n#define 关闭 \"OFF\"\n#define ROGER尾音 \"ROGER\"\n#define MDC尾音 \"MDC\\nEND\"\n#define MDC首音 \"MDC\\nBGN\"\n#define MDC首尾音 \"MDC\\nBOTH\"\n#define MDC首音加ROGER \"MDC BGN\\n+ROGER\"\n#define 除信道参数 \"VFO\"\n#define 全部参数 \"ALL\"\n#define 禁用全部 \"DISABLE\\nALL\"\n#define 解锁全部 \"UNLOCK\\nALL\"\n#define 五秒 \"5 sec\"\n#define 十秒 \"10 sec\"\n#define 二十秒 \"20 sec\"\n#define 发送时 \"TX\"\n#define 接收时 \"RX\"\n#define 发送接收时 \"TX/RX\"\n#define 全部 \"ALL\"\n#define 扫描 \"Scan\"\n#define 低电压 \"LOW VOL\"\n#define 遇忙 \"BUSY\"\n#define 禁止发射 \"DISABLE\"\n#define 发送超时 \"TxTOut\"\n#define 高电压 \"HIGH VOL\"\n#define 按EXIT键 \"Press EXIT\"\n#define 存置问 \"SAVE?\"\n#define 存置了 \"SAVED!\"\n#define 删除问 \"DEL?\"\n#define 列表 \"List\"\n#define 模拟亚音 \"CTCS\"\n#define 数字亚音 \"DCS\"\n#define 图片 \"PIC\"\n#define 信息 \"TxT\"\n#define 侧键1短按 \"F1Shrt\"\n#define 侧键1长按 \"F1Long\"\n#define 侧键2短按 \"F2Shrt\"\n#define 侧键2长按 \"F2Long\"\n#define M键长按 \"M Long\"\n#define 手电 \"LIGHT\"\n#define 切换发射功率 \"POWER\"\n#define 监听 \"MONITOR\"\n#define 声控发射 \"VOX\"\n#define FM收音机 \"FM RADIO\"\n#define 锁定按键 \"LOCK KEY\"\n#define 切换信道 \"SWITCH VFO\"\n#define 切换信道模式 \"VFO/MR\"\n#define 切换调制模式 \"Demodu\"\n#define DTMF解码 \"D Decd\"\n#define 切换宽窄带 \"W/N\"\n#define 宽窄带 \"W/N\"\n#define 宽带 \"WIDE\"\n#define 窄带 \"NARROW\"\n#define 主信道发射 \"MAIN SEND\"\n#define 副信道发射 \"DUAL SEND\"\n#define 开机显示 \"POnMsg\"\n\n\n#else\n#define 步进频率  \"\\x01\\x02\\x03\\x04\"\n#define 接收数字亚音  \"\\x05\\x06\\x07\\x08\\x09\\x0B\"\n#define 接收模拟亚音  \"\\x05\\x06\\x0C\\x0D\\x09\\x0B\"\n#define 发送数字亚音  \"\\x0E\\x0F\\x07\\x08\\x09\\x0B\"\n#define 发送模拟亚音  \"\\x0E\\x0F\\x0C\\x0D\\x09\\x0B\"\n#define 频差方向  \"\\x03\\x10\\x11\\x12\"\n#define 频差频率  \"\\x03\\x10\\x03\\x04\"\n#define 加密  \"\\x13\\x14\"\n#define 遇忙禁发  \"\\x15\\x16\\x17\\x0E\"\n#define 压扩  \"\\x18\\x19\"\n#define 存置信道  \"\\x1A\\x1B\\x1C\\x1D\"\n#define 删除信道  \"\\x1E\\x1F\\x1C\\x1D\"\n#define 命名信道  \"\\x7F\\x80\\x1C\\x1D\"\n#define 信道扫描列表  \"\\x1C\\x1D\\x81\\x82\\x83\\x84\"\n#define 扫描列表1  \"\\x81\\x82\\x83\\x84\\x31\"\n#define 扫描列表2  \"\\x81\\x82\\x83\\x84\\x32\"\n#define 搜索恢复模式  \"\\x85\\x86\\x87\\x88\\x0C\\x89\"\n#define 发送超时  \"\\x0E\\x0F\\x8A\\x8B\"\n#define 省电模式  \"\\x8C\\x8D\\x0C\\x89\"\n#define 麦克风增益  \"\\x8E\\x8F\\x90\\x91\\x92\"\n#define 信道显示模式  \"\\x1C\\x1D\\x93\\x94\\x0C\\x89\"\n#define 自动背光  \"\\x95\\x96\\x97\\x98\"\n#define 背光亮度  \"\\x97\\x98\\x99\\x9A\"\n#define 首尾音  \"\\x9B\\x9C\\x0B\"\n#define MDC_ID  \"\\x4D\\x44\\x43\\x20\\x49\\x44\"\n#define 尾音消除  \"\\x9C\\x0B\\x9D\\x1F\"\n#define 过中继尾音消除  \"\\x9E\\x9F\\xA0\\x9C\\x0B\\x9D\\x1F\"\n#define 按键即呼  \"\\xA1\\xA2\\xA3\\xA4\"\n#define DTMF_ID  \"\\x44\\x54\\x4D\\x46\\x20\\x49\\x44\"\n#define DTMF上线码  \"\\x44\\x54\\x4D\\x46\\xA5\\xA6\\xA7\"\n#define DTMF下线码  \"\\x44\\x54\\x4D\\x46\\xA8\\xA6\\xA7\"\n#define DTMF发送  \"\\x44\\x54\\x4D\\x46\\x0E\\x0F\"\n#define DTMF侧音  \"\\x44\\x54\\x4D\\x46\\xA9\\x0B\"\n#define DTMF响应  \"\\x44\\x54\\x4D\\x46\\xAA\\xAB\"\n#define DTMF复位  \"\\x44\\x54\\x4D\\x46\\x88\\xAC\"\n#define DTMF预载波  \"\\x44\\x54\\x4D\\x46\\xAD\\xAE\\xAF\"\n#define DTMF联系人  \"\\x44\\x54\\x4D\\x46\\xB0\\xB1\\xB2\"\n#define DTMF显示  \"\\x44\\x54\\x4D\\x46\\x93\\x94\"\n#define AM自动增益  \"\\x41\\x4D\\x95\\x96\\x91\\x92\"\n#define 收发模式  \"\\x06\\x0E\\x0C\\x89\"\n#define 静噪等级  \"\\xB3\\xB4\\xB5\\xB6\"\n#define 频段解锁  \"\\x03\\xB7\\xB8\\xB9\"\n#define 电池调压  \"\\x8D\\xBA\\xBB\\x18\"\n#define 电池大小  \"\\x8D\\xBA\\xBC\\xBD\"\n#define 参数复位  \"\\xBE\\x07\\x88\\xAC\"\n#define 发送等于接收  \"\\x0E\\x0F\\x3D\\x05\\x06\"\n#define 发送等于接收加偏移  \"\\x0E\\x0F\\x3D\\n\\x05\\x06\\x2B\\xBF\\xC0\"\n#define 发送等于接收减偏移  \"\\x0E\\x0F\\x3D\\n\\x05\\x06\\x2D\\xBF\\xC0\"\n#define 关闭  \"\\xC1\\xC2\"\n#define 开启  \"\\xC3\\xC4\"\n#define 一级  \"\\x31\\x20\\xB6\"\n#define 二级  \"\\x32\\x20\\xB6\"\n#define 三级  \"\\x33\\x20\\xB6\"\n#define 四级  \"\\x34\\x20\\xB6\"\n#define 三十秒  \"\\x33\\x30\\x20\\xC5\"\n#define 一分  \"\\x31\\x20\\xC6\"\n#define 两分  \"\\x32\\x20\\xC6\"\n#define 三分  \"\\x33\\x20\\xC6\"\n#define 四分  \"\\x34\\x20\\xC6\"\n#define 五分  \"\\x35\\x20\\xC6\"\n#define 六分  \"\\x36\\x20\\xC6\"\n#define 七分  \"\\x37\\x20\\xC6\"\n#define 八分  \"\\x38\\x20\\xC6\"\n#define 九分  \"\\x39\\x20\\xC6\"\n#define 十五分  \"\\x31\\x35\\x20\\xC6\"\n#define 主信道接收发射  \"\\xC7\\x1C\\x1D\\n\\x05\\x06\\x0E\\xC8\"\n#define 双信道接收  \"\\xC9\\x1C\\x1D\\n\\x05\\x06\"\n#define 主信道发射副信道接收  \"\\xC7\\x1C\\x1D\\x0E\\xC8\\n\\xCA\\x1C\\x1D\\x05\\x06\"\n#define 主信道发射双信道接收  \"\\xC7\\x1C\\x1D\\x0E\\xC8\\n\\xC9\\x1C\\x1D\\x05\\x06\"\n#define 遇信号5秒后搜索  \"\\x15\\x1C\\xCB\\n\\x35\\xC5\\xCC\\x85\\x86\"\n#define 信号停止后搜索  \"\\x1C\\xCB\\xCD\\xCE\\xCC\\n\\x85\\x86\"\n#define 遇信号后停止搜索  \"\\x15\\x1C\\xCB\\xCC\\n\\xCD\\xCE\\x85\\x86\"\n#define 频率  \"\\x03\\x04\"\n#define 信道号  \"\\x1C\\x1D\\xCB\"\n#define 名称  \"\\x80\\xCF\"\n#define 名称加频率  \"\\x80\\xCF\\x2B\\n\\x03\\x04\"\n#define 不响应  \"\\xD0\\xAA\\xAB\"\n#define 本地响铃  \"\\xD1\\xD2\\xAA\\xD3\"\n#define 回复响应  \"\\xD4\\x88\\xAA\\xAB\"\n#define 本地响铃回复响应  \"\\xD1\\xD2\\xAA\\xD3\\n\\xD4\\x88\\xAA\\xAB\"\n#define 不发送  \"\\xD0\\x0E\\x0F\"\n#define 上线码  \"\\xA5\\xA6\\xA7\"\n#define 下线码  \"\\xA8\\xA6\\xA7\"\n#define 上线加下线码  \"\\xA5\\xA6\\x2B\\xA8\\xA6\\xA7\"\n#define Quindar码  \"\\x51\\x75\\x69\\x6E\\x64\\x61\\x72\\xA7\"\n#define 关闭  \"\\xC1\\xC2\"\n#define ROGER尾音  \"\\x52\\x4F\\x47\\x45\\x52\\x9C\\x0B\"\n#define MDC尾音  \"\\x4D\\x44\\x43\\x9C\\x0B\"\n#define MDC首音  \"\\x4D\\x44\\x43\\x9B\\x0B\"\n#define MDC首尾音  \"\\x4D\\x44\\x43\\x9B\\x9C\\x0B\"\n#define MDC首音加ROGER  \"\\x4D\\x44\\x43\\x9B\\x0B\\x2B\\n\\x52\\x4F\\x47\\x45\\x52\"\n#define 除信道参数  \"\\x1F\\x1C\\x1D\\xBE\\x07\"\n#define 全部参数  \"\\xD5\\xD6\\xBE\\x07\"\n#define 禁用全部  \"\\x17\\xD7\\xD5\\xD6\"\n#define 解锁全部  \"\\xB8\\xB9\\xD5\\xD6\"\n#define 五秒  \"\\x35\\x20\\xC5\"\n#define 十秒  \"\\x31\\x30\\x20\\xC5\"\n#define 二十秒  \"\\x32\\x30\\x20\\xC5\"\n#define 发送时  \"\\x0E\\x0F\\x8B\"\n#define 接收时  \"\\x05\\x06\\x8B\"\n#define 发送接收时  \"\\x0E\\x0F\\x2F\\x05\\x06\\x8B\"\n#define 列表  \"\\x83\\x84\"\n#define 全部  \"\\xD5\\xD6\"\n#define 扫描  \"\\x81\\x82\"\n#define 低电压  \"\\xD8\\x8D\\x18\"\n#define 长按井键解锁  \"\\xD9\\xA1\\x20\\x23\\x20\\xA2\\xB8\\xB9\"\n#define 遇忙  \"\\x15\\x16\"\n#define 禁止发射  \"\\x17\\xCE\\x0E\\xC8\"\n#define 发送超时  \"\\x0E\\x0F\\x8A\\x8B\"\n#define 高电压  \"\\xDA\\x8D\\x18\"\n#define 按EXIT键  \"\\xA1\\x20\\x45\\x58\\x49\\x54\\x20\\xA2\"\n#define 全部按键  \"\\xD5\\xD6\\xA1\\xA2\"\n#define 解锁  \"\\xB8\\xB9\"\n#define 模拟亚音  \"\\x0C\\x0D\\x09\\x0B\"\n#define 数字亚音  \"\\x07\\x08\\x09\\x0B\"\n#define 频率  \"\\x03\\x04\"\n#define 存置问  \"\\x1A\\x1B\\x3F\"\n#define 存置了  \"\\x1A\\x1B\\x3A\"\n#define 扫描  \"\\x81\\x82\"\n#define 删除问  \"\\x1E\\x1F\\x3F\"\n\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\n\n#define 侧键1短按 \"\\xA9\\xA2\\x31\\xDB\\xA1\"\n#define 侧键1长按 \"\\xA9\\xA2\\x31\\xD9\\xA1\"\n#define 侧键2短按 \"\\xA9\\xA2\\x32\\xDB\\xA1\"\n#define 侧键2长按 \"\\xA9\\xA2\\x32\\xD9\\xA1\"\n#define M键长按 \"\\x4D\\xA2\\xD9\\xA1\"\n#define 手电 \"\\xDC\\x8D\"\n#define 切换发射功率 \"\\xDD\\xDE\\x0E\\xC8\\xDF\\x04\"\n#define 监听 \"\\xE0\\xE1\"\n#define 声控发射 \"\\xE2\\xE3\\x0E\\xC8\"\n#define FM收音机 \"\\x46\\x4D\\x06\\x0B\\xE4\"\n#define 锁定按键 \"\\xB9\\xE5\\xA1\\xA2\"\n#define 切换信道 \"\\xDD\\xDE\\x1C\\x1D\"\n#define 切换信道模式 \"\\xDD\\xDE\\x1C\\x1D\\x0C\\x89\"\n#define 切换调制模式 \"\\xDD\\xDE\\xBB\\xE6\\x0C\\x89\"\n#define DTMF解码 \"\\x44\\x54\\x4D\\x46\\xB8\\xA7\"\n#define 切换宽窄带 \"\\xDD\\xDE\\xE7\\xE8\\xE9\"\n#define 宽窄带 \"\\xE7\\xE8\\xE9\"\n#define 宽带 \"\\xE7\\xE9\"\n#define 窄带 \"\\xE8\\xE9\"\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\n#define 主信道发射 \"\\xC7\\x1C\\x1D\\x0E\\xC8\"\n#define 副信道发射 \"\\xCA\\x1C\\x1D\\x0E\\xC8\"\n#endif\n#endif\n#endif\n\n\n\n\n#elif ENABLE_CHINESE_FULL==4\n#define 步进频率 \"\\xB2\\xBD\\xBD\\xF8\\xC6\\xB5\\xC2\\xCA\"\n#define 接收数字亚音 \"\\xBD\\xD3\\xCA\\xD5\\xCA\\xFD\\xD7\\xD6\\xD1\\xC7\\xD2\\xF4\"\n#define 接收模拟亚音 \"\\xBD\\xD3\\xCA\\xD5\\xC4\\xA3\\xC4\\xE2\\xD1\\xC7\\xD2\\xF4\"\n#define 发送数字亚音 \"\\xB7\\xA2\\xCB\\xCD\\xCA\\xFD\\xD7\\xD6\\xD1\\xC7\\xD2\\xF4\"\n#define 发送模拟亚音 \"\\xB7\\xA2\\xCB\\xCD\\xC4\\xA3\\xC4\\xE2\\xD1\\xC7\\xD2\\xF4\"\n#define 频差方向 \"\\xC6\\xB5\\xB2\\xEE\\xB7\\xBD\\xCF\\xF2\"\n#define 频差频率 \"\\xC6\\xB5\\xB2\\xEE\\xC6\\xB5\\xC2\\xCA\"\n#define 加密 \"\\xBC\\xD3\\xC3\\xDC\"\n#define 遇忙禁发 \"\\xD3\\xF6\\xC3\\xA6\\xBD\\xFB\\xB7\\xA2\"\n#define 压扩 \"\\xD1\\xB9\\xC0\\xA9\"\n#define 存置信道 \"\\xB1\\xA3\\xB4\\xE6\\xD0\\xC5\\xB5\\xC0\"\n#define 删除信道 \"\\xC9\\xBE\\xB3\\xFD\\xD0\\xC5\\xB5\\xC0\"\n#define 命名信道 \"\\xC3\\xFC\\xC3\\xFB\\xD0\\xC5\\xB5\\xC0\"\n#define 信道扫描列表 \"\\xD0\\xC5\\xB5\\xC0\\xC9\\xA8\\xC3\\xE8\\xC1\\xD0\\xB1\\xED\"\n#define 扫描列表1 \"\\xC9\\xA8\\xC3\\xE8\\xC1\\xD0\\xB1\\xED\\x31\"\n#define 扫描列表2 \"\\xC9\\xA8\\xC3\\xE8\\xC1\\xD0\\xB1\\xED\\x32\"\n#define 搜索恢复模式 \"\\xCB\\xD1\\xCB\\xF7\\xBB\\xD6\\xB8\\xB4\\xC4\\xA3\\xCA\\xBD\"\n#define 发送超时 \"\\xB7\\xA2\\xCB\\xCD\\xB3\\xAC\\xCA\\xB1\"\n#define 省电模式 \"\\xCA\\xA1\\xB5\\xE7\\xC4\\xA3\\xCA\\xBD\"\n#define 麦克风增益 \"\\xC2\\xF3\\xBF\\xCB\\xB7\\xE7\\xD4\\xF6\\xD2\\xE6\"\n#define 信道显示模式 \"\\xD0\\xC5\\xB5\\xC0\\xCF\\xD4\\xCA\\xBE\\xC4\\xA3\\xCA\\xBD\"\n#define 自动背光 \"\\xD7\\xD4\\xB6\\xAF\\xB1\\xB3\\xB9\\xE2\"\n#define 背光亮度 \"\\xB1\\xB3\\xB9\\xE2\\xC1\\xC1\\xB6\\xC8\"\n#define 首尾音 \"\\xCA\\xD7\\xCE\\xB2\\xD2\\xF4\"\n#define MDC_ID \"\\x4D\\x44\\x43\\x20\\x49\\x44\"\n#define 尾音消除 \"\\xCE\\xB2\\xD2\\xF4\\xCF\\xFB\\xB3\\xFD\"\n#define 过中继尾音消除 \"\\xB9\\xFD\\xD6\\xD0\\xBC\\xCC\\xCE\\xB2\\xD2\\xF4\\xCF\\xFB\\xB3\\xFD\"\n#define 按键即呼 \"\\xB0\\xB4\\xBC\\xFC\\xBC\\xB4\\xBA\\xF4\"\n#define DTMF_ID \"\\x44\\x54\\x4D\\x46\\x20\\x49\\x44\"\n#define DTMF上线码 \"\\x44\\x54\\x4D\\x46\\xC9\\xCF\\xCF\\xDF\\xC2\\xEB\"\n#define DTMF下线码 \"\\x44\\x54\\x4D\\x46\\xCF\\xC2\\xCF\\xDF\\xC2\\xEB\"\n#define DTMF发送 \"\\x44\\x54\\x4D\\x46\\xB7\\xA2\\xCB\\xCD\"\n#define DTMF侧音 \"\\x44\\x54\\x4D\\x46\\xB2\\xE0\\xD2\\xF4\"\n#define DTMF响应 \"\\x44\\x54\\x4D\\x46\\xCF\\xEC\\xD3\\xA6\"\n#define DTMF复位 \"\\x44\\x54\\x4D\\x46\\xB8\\xB4\\xCE\\xBB\"\n#define DTMF预载波 \"\\x44\\x54\\x4D\\x46\\xD4\\xA4\\xD4\\xD8\\xB2\\xA8\"\n#define DTMF联系人 \"\\x44\\x54\\x4D\\x46\\xC1\\xAA\\xCF\\xB5\\xC8\\xCB\"\n#define DTMF显示 \"\\x44\\x54\\x4D\\x46\\xCF\\xD4\\xCA\\xBE\"\n#define AM自动增益 \"\\x41\\x4D\\xD7\\xD4\\xB6\\xAF\\xD4\\xF6\\xD2\\xE6\"\n#define 收发模式 \"\\xCA\\xD5\\xB7\\xA2\\xC4\\xA3\\xCA\\xBD\"\n#define 静噪等级 \"\\xBE\\xB2\\xD4\\xEB\\xB5\\xC8\\xBC\\xB6\"\n#define 频段解锁 \"\\xC6\\xB5\\xB6\\xCE\\xBD\\xE2\\xCB\\xF8\"\n#define 两百M发射 \"\\x32\\x30\\x30\\x4D\\xB7\\xA2\\xC9\\xE4\"\n#define 三百五十M发射 \"\\x33\\x35\\x30\\x4D\\xB7\\xA2\\xC9\\xE4\"\n#define 五百M发射 \"\\x35\\x30\\x30\\x4D\\xB7\\xA2\\xC9\\xE4\"\n#define 三百五十M接收 \"\\x33\\x35\\x30\\x4D\\xBD\\xD3\\xCA\\xD5\"\n#define 电池调压 \"\\xB5\\xE7\\xB3\\xD8\\xB5\\xF7\\xD1\\xB9\"\n#define 电池大小 \"\\xB5\\xE7\\xB3\\xD8\\xB4\\xF3\\xD0\\xA1\"\n#define 参数复位 \"\\xB2\\xCE\\xCA\\xFD\\xB8\\xB4\\xCE\\xBB\"\n#define 发送等于接收 \"\\xB7\\xA2\\xCB\\xCD\\x3D\\xBD\\xD3\\xCA\\xD5\"\n#define 发送等于接收加偏移 \"\\xB7\\xA2\\xCB\\xCD\\x3D\\n\\xBD\\xD3\\xCA\\xD5\\x2B\\xC6\\xAB\\xD2\\xC6\"\n#define 发送等于接收减偏移 \"\\xB7\\xA2\\xCB\\xCD\\x3D\\n\\xBD\\xD3\\xCA\\xD5\\x2D\\xC6\\xAB\\xD2\\xC6\"\n#define 关闭 \"\\xB9\\xD8\\xB1\\xD5\"\n#define 开启 \"\\xBF\\xAA\\xC6\\xF4\"\n#define 一级 \"\\x31\\x20\\xBC\\xB6\"\n#define 二级 \"\\x32\\x20\\xBC\\xB6\"\n#define 三级 \"\\x33\\x20\\xBC\\xB6\"\n#define 四级 \"\\x34\\x20\\xBC\\xB6\"\n#define 三十秒 \"\\x33\\x30\\x20\\xC3\\xEB\"\n#define 一分 \"\\x31\\x20\\xB7\\xD6\"\n#define 两分 \"\\x32\\x20\\xB7\\xD6\"\n#define 三分 \"\\x33\\x20\\xB7\\xD6\"\n#define 四分 \"\\x34\\x20\\xB7\\xD6\"\n#define 五分 \"\\x35\\x20\\xB7\\xD6\"\n#define 六分 \"\\x36\\x20\\xB7\\xD6\"\n#define 七分 \"\\x37\\x20\\xB7\\xD6\"\n#define 八分 \"\\x38\\x20\\xB7\\xD6\"\n#define 九分 \"\\x39\\x20\\xB7\\xD6\"\n#define 十五分 \"\\x31\\x35\\x20\\xB7\\xD6\"\n#define 主信道接收发射 \"\\xD6\\xF7\\xD0\\xC5\\xB5\\xC0\\n\\xBD\\xD3\\xCA\\xD5\\xB7\\xA2\\xC9\\xE4\"\n#define 双信道接收 \"\\xCB\\xAB\\xD0\\xC5\\xB5\\xC0\\n\\xBD\\xD3\\xCA\\xD5\"\n#define 主信道发射副信道接收 \"\\xD6\\xF7\\xD0\\xC5\\xB5\\xC0\\xB7\\xA2\\xC9\\xE4\\n\\xB8\\xB1\\xD0\\xC5\\xB5\\xC0\\xBD\\xD3\\xCA\\xD5\"\n#define 主信道发射双信道接收 \"\\xD6\\xF7\\xD0\\xC5\\xB5\\xC0\\xB7\\xA2\\xC9\\xE4\\n\\xCB\\xAB\\xD0\\xC5\\xB5\\xC0\\xBD\\xD3\\xCA\\xD5\"\n#define 遇信号5秒后搜索 \"\\xD3\\xF6\\xD0\\xC5\\xBA\\xC5\\n\\x35\\xC3\\xEB\\xBA\\xF3\\xCB\\xD1\\xCB\\xF7\"\n#define 信号停止后搜索 \"\\xD0\\xC5\\xBA\\xC5\\xCD\\xA3\\xD6\\xB9\\xBA\\xF3\\n\\xCB\\xD1\\xCB\\xF7\"\n#define 遇信号后停止搜索 \"\\xD3\\xF6\\xD0\\xC5\\xBA\\xC5\\xBA\\xF3\\n\\xCD\\xA3\\xD6\\xB9\\xCB\\xD1\\xCB\\xF7\"\n#define 频率 \"\\xC6\\xB5\\xC2\\xCA\"\n#define 信道号 \"\\xD0\\xC5\\xB5\\xC0\\xBA\\xC5\"\n#define 名称 \"\\xC3\\xFB\\xB3\\xC6\"\n#define 名称加频率 \"\\xC3\\xFB\\xB3\\xC6\\x2B\\n\\xC6\\xB5\\xC2\\xCA\"\n#define 不响应 \"\\xB2\\xBB\\xCF\\xEC\\xD3\\xA6\"\n#define 本地响铃 \"\\xB1\\xBE\\xB5\\xD8\\xCF\\xEC\\xC1\\xE5\"\n#define 回复响应 \"\\xBB\\xD8\\xB8\\xB4\\xCF\\xEC\\xD3\\xA6\"\n#define 本地响铃回复响应 \"\\xB1\\xBE\\xB5\\xD8\\xCF\\xEC\\xC1\\xE5\\n\\xBB\\xD8\\xB8\\xB4\\xCF\\xEC\\xD3\\xA6\"\n#define 不发送 \"\\xB2\\xBB\\xB7\\xA2\\xCB\\xCD\"\n#define 上线码 \"\\xC9\\xCF\\xCF\\xDF\\xC2\\xEB\"\n#define 下线码 \"\\xCF\\xC2\\xCF\\xDF\\xC2\\xEB\"\n#define 上线加下线码 \"\\xC9\\xCF\\xCF\\xDF\\x2B\\xCF\\xC2\\xCF\\xDF\\xC2\\xEB\"\n#define Quindar码 \"\\x51\\x75\\x69\\x6E\\x64\\x61\\x72\\xC2\\xEB\"\n#define 关闭 \"\\xB9\\xD8\\xB1\\xD5\"\n#define ROGER尾音 \"\\x52\\x4F\\x47\\x45\\x52\\xCE\\xB2\\xD2\\xF4\"\n#define MDC尾音 \"\\x4D\\x44\\x43\\xCE\\xB2\\xD2\\xF4\"\n#define MDC首音 \"\\x4D\\x44\\x43\\xCA\\xD7\\xD2\\xF4\"\n#define MDC首尾音 \"\\x4D\\x44\\x43\\xCA\\xD7\\xCE\\xB2\\xD2\\xF4\"\n#define MDC首音加ROGER \"\\x4D\\x44\\x43\\xCA\\xD7\\xD2\\xF4\\x2B\\n\\x52\\x4F\\x47\\x45\\x52\"\n#define 除信道参数 \"\\xB3\\xFD\\xD0\\xC5\\xB5\\xC0\\xB2\\xCE\\xCA\\xFD\"\n#define 全部参数 \"\\xC8\\xAB\\xB2\\xBF\\xB2\\xCE\\xCA\\xFD\"\n#define 禁用全部 \"\\xBD\\xFB\\xD3\\xC3\\xC8\\xAB\\xB2\\xBF\"\n#define 解锁全部 \"\\xBD\\xE2\\xCB\\xF8\\xC8\\xAB\\xB2\\xBF\"\n#define 五秒 \"\\x35\\x20\\xC3\\xEB\"\n#define 十秒 \"\\x31\\x30\\x20\\xC3\\xEB\"\n#define 二十秒 \"\\x32\\x30\\x20\\xC3\\xEB\"\n#define 发送时 \"\\xB7\\xA2\\xCB\\xCD\\xCA\\xB1\"\n#define 接收时 \"\\xBD\\xD3\\xCA\\xD5\\xCA\\xB1\"\n#define 发送接收时 \"\\xB7\\xA2\\xCB\\xCD\\x2F\\xBD\\xD3\\xCA\\xD5\\xCA\\xB1\"\n#define 全部 \"\\xC8\\xAB\\xB2\\xBF\"\n#define 扫描 \"\\xC9\\xA8\\xC3\\xE8\"\n#define 低电压 \"\\xB5\\xCD\\xB5\\xE7\\xD1\\xB9\"\n#define 长按井键解锁 \"\\xB3\\xA4\\xB0\\xB4\\x20\\x23\\x20\\xBC\\xFC\\xBD\\xE2\\xCB\\xF8\"\n#define 遇忙 \"\\xD3\\xF6\\xC3\\xA6\"\n#define 禁止发射 \"\\xBD\\xFB\\xD6\\xB9\\xB7\\xA2\\xC9\\xE4\"\n#define 发送超时 \"\\xB7\\xA2\\xCB\\xCD\\xB3\\xAC\\xCA\\xB1\"\n#define 高电压 \"\\xB8\\xDF\\xB5\\xE7\\xD1\\xB9\"\n#define 按EXIT键 \"\\xB0\\xB4\\x20\\x45\\x58\\x49\\x54\\x20\\xBC\\xFC\"\n#define 全部按键 \"\\xC8\\xAB\\xB2\\xBF\\xB0\\xB4\\xBC\\xFC\"\n#define 解锁 \"\\xBD\\xE2\\xCB\\xF8\"\n#define 存置问 \"\\xB1\\xA3\\xB4\\xE6\\x3F\"\n#define 存置了 \"\\xB1\\xA3\\xB4\\xE6\\x3A\"\n#define 扫描 \"\\xC9\\xA8\\xC3\\xE8\"\n#define 删除问 \"\\xC9\\xBE\\xB3\\xFD\\x3F\"\n#define 列表 \"\\xC1\\xD0\\xB1\\xED\"\n#define 模拟亚音 \"\\xC4\\xA3\\xC4\\xE2\\xD1\\xC7\\xD2\\xF4\"\n#define 数字亚音 \"\\xCA\\xFD\\xD7\\xD6\\xD1\\xC7\\xD2\\xF4\"\n#define 图片 \"\\xCD\\xBC\\xC6\\xAC\"\n#define 信息 \"\\xD0\\xC5\\xCF\\xA2\"\n#define 侧键1短按 \"\\xB2\\xE0\\xBC\\xFC\\x31\\xB6\\xCC\\xB0\\xB4\"\n#define 侧键1长按 \"\\xB2\\xE0\\xBC\\xFC\\x31\\xB3\\xA4\\xB0\\xB4\"\n#define 侧键2短按 \"\\xB2\\xE0\\xBC\\xFC\\x32\\xB6\\xCC\\xB0\\xB4\"\n#define 侧键2长按 \"\\xB2\\xE0\\xBC\\xFC\\x32\\xB3\\xA4\\xB0\\xB4\"\n#define M键长按 \"\\x4D\\xBC\\xFC\\xB3\\xA4\\xB0\\xB4\"\n#define 手电 \"\\xCA\\xD6\\xB5\\xE7\\xCD\\xB2\"\n#define 切换发射功率 \"\\xC7\\xD0\\xBB\\xBB\\xB7\\xA2\\xC9\\xE4\\xB9\\xA6\\xC2\\xCA\"\n#define 监听 \"\\xBC\\xE0\\xCC\\xFD\"\n#define 声控发射 \"\\xC9\\xF9\\xBF\\xD8\\xB7\\xA2\\xC9\\xE4\"\n#define FM收音机 \"\\x46\\x4D\\xCA\\xD5\\xD2\\xF4\\xBB\\xFA\"\n#define 锁定按键 \"\\xCB\\xF8\\xB6\\xA8\\xB0\\xB4\\xBC\\xFC\"\n#define 切换信道 \"\\xC7\\xD0\\xBB\\xBB\\xD0\\xC5\\xB5\\xC0\"\n#define 切换信道模式 \"\\xC7\\xD0\\xBB\\xBB\\xD0\\xC5\\xB5\\xC0\\xC4\\xA3\\xCA\\xBD\"\n#define 切换调制模式 \"\\xC7\\xD0\\xBB\\xBB\\xB5\\xF7\\xD6\\xC6\\xC4\\xA3\\xCA\\xBD\"\n#define DTMF解码 \"\\x44\\x54\\x4D\\x46\\xBD\\xE2\\xC2\\xEB\"\n#define 切换宽窄带 \"\\xC7\\xD0\\xBB\\xBB\\xBF\\xED\\xD5\\xAD\\xB4\\xF8\"\n#define 宽窄带 \"\\xBF\\xED\\xD5\\xAD\\xB4\\xF8\"\n#define 宽带 \"\\xBF\\xED\\xB4\\xF8\"\n#define 窄带 \"\\xD5\\xAD\\xB4\\xF8\"\n#define 主信道发射 \"\\xD6\\xF7\\xD0\\xC5\\xB5\\xC0\\xB7\\xA2\\xC9\\xE4\"\n#define 副信道发射 \"\\xB8\\xB1\\xD0\\xC5\\xB5\\xC0\\xB7\\xA2\\xC9\\xE4\"\n#define 开机显示 \"\\xBF\\xAA\\xBB\\xFA\\xCF\\xD4\\xCA\\xBE\"\n\n#endif\n\n#endif //UV_K5_FIRMWARE_CUSTOM_0_17_CHINESE_H\n"
  },
  {
    "path": "compile-with-docker.bat",
    "content": "@echo on\r\nmake clean\r\ndocker build -t uvk5 .\r\ndocker run --rm -v %CD%\\compiled-firmware:/app/compiled-firmware uvk5 /bin/bash -c \"cd /app &&rm -rf compiled&& make clean && make full&& cp *.bin compiled-firmware/\"\r\npause\r\n"
  },
  {
    "path": "compile-with-docker.sh",
    "content": "#!/bin/sh\nrm -rf compiled\nmake clean\ndocker build -t uvk5 .\ndocker run --rm -v \"$(pwd)/compiled-firmware:/app/compiled-firmware\" uvk5 /bin/bash -c \"cd /app && rm -rf compiled && make clean && make && cp *.bin compiled-firmware/\"\n"
  },
  {
    "path": "dcs.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include \"driver/eeprom.h\"\r\n#include \"dcs.h\"\r\n\r\n#ifndef ARRAY_SIZE\r\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r\n#endif\r\n\r\n\r\n#ifdef TEST_UNDE_CTCSS\r\n\r\nconst uint16_t CTCSS_Options[50] = {\r\n     200,  693,  719,  744,  770,  797,  825,  854,  885,  915,\r\n     948,  974, 1000, 1035, 1072, 1109, 1148, 1188, 1230, 1273,\r\n    1318, 1365, 1413, 1462, 1514, 1567, 1598, 1622, 1655, 1679,\r\n    1713, 1738, 1773, 1799, 1835, 1862, 1899, 1928, 1966, 1995,\r\n    2035, 2065, 2107, 2181, 2257, 2291, 2336, 2418, 2503, 2541\r\n};\r\n#else\r\n//CTCSS Hz * 10\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\nconst uint16_t CTCSS_Options[50] = {\r\n        670, 693, 719, 744, 770, 797, 825, 854, 885, 915,\r\n        948, 974, 1000, 1035, 1072, 1109, 1148, 1188, 1230, 1273,\r\n        1318, 1365, 1413, 1462, 1514, 1567, 1598, 1622, 1655, 1679,\r\n        1713, 1738, 1773, 1799, 1835, 1862, 1899, 1928, 1966, 1995,\r\n        2035, 2065, 2107, 2181, 2257, 2291, 2336, 2418, 2503, 2541\r\n};\r\n#endif\r\n#endif\r\n\r\n#if ENABLE_CHINESE_FULL == 0|| defined(ENABLE_ENGLISH)\r\n\r\nconst uint16_t DCS_Options[104] = {\r\n        0x0013, 0x0015, 0x0016, 0x0019, 0x001A, 0x001E, 0x0023, 0x0027,\r\n        0x0029, 0x002B, 0x002C, 0x0035, 0x0039, 0x003A, 0x003B, 0x003C,\r\n        0x004C, 0x004D, 0x004E, 0x0052, 0x0055, 0x0059, 0x005A, 0x005C,\r\n        0x0063, 0x0065, 0x006A, 0x006D, 0x006E, 0x0072, 0x0075, 0x007A,\r\n        0x007C, 0x0085, 0x008A, 0x0093, 0x0095, 0x0096, 0x00A3, 0x00A4,\r\n        0x00A5, 0x00A6, 0x00A9, 0x00AA, 0x00AD, 0x00B1, 0x00B3, 0x00B5,\r\n        0x00B6, 0x00B9, 0x00BC, 0x00C6, 0x00C9, 0x00CD, 0x00D5, 0x00D9,\r\n        0x00DA, 0x00E3, 0x00E6, 0x00E9, 0x00EE, 0x00F4, 0x00F5, 0x00F9,\r\n        0x0109, 0x010A, 0x010B, 0x0113, 0x0119, 0x011A, 0x0125, 0x0126,\r\n        0x012A, 0x012C, 0x012D, 0x0132, 0x0134, 0x0135, 0x0136, 0x0143,\r\n        0x0146, 0x014E, 0x0153, 0x0156, 0x015A, 0x0166, 0x0175, 0x0186,\r\n        0x018A, 0x0194, 0x0197, 0x0199, 0x019A, 0x01AC, 0x01B2, 0x01B4,\r\n        0x01C3, 0x01CA, 0x01D3, 0x01D9, 0x01DA, 0x01DC, 0x01E3, 0x01EC,\r\n};\r\n#endif\r\n\r\nstatic uint32_t DCS_CalculateGolay(uint32_t CodeWord) {\r\n    unsigned int i;\r\n    uint32_t Word = CodeWord;\r\n    for (i = 0; i < 12; i++) {\r\n        Word <<= 1;\r\n        if (Word & 0x1000)\r\n            Word ^= 0x08EA;\r\n    }\r\n    return CodeWord | ((Word & 0x0FFE) << 11);\r\n}\r\n\r\nuint32_t DCS_GetGolayCodeWord(DCS_CodeType_t CodeType, uint8_t Option) {\r\n\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n    uint32_t Code = DCS_CalculateGolay(DCS_Options[Option] + 0x800U);\r\n\r\n#else\r\n    uint8_t read_tmp[2];\r\nEEPROM_ReadBuffer(0x02C64+(Option)*2, read_tmp, 2);\r\nuint16_t DCS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\nuint32_t Code = DCS_CalculateGolay(DCS_Options_read + 0x800U);\r\n\r\n\r\n#endif\r\n\r\n//\tuint32_t Code = DCS_CalculateGolay(DCS_Options[Option] + 0x800U);\r\n    if (CodeType == CODE_TYPE_REVERSE_DIGITAL)\r\n        Code ^= 0x7FFFFF;\r\n    return Code;\r\n}\r\n\r\nuint8_t DCS_GetCdcssCode(uint32_t Code) {\r\n    unsigned int i;\r\n    for (i = 0; i < 23; i++) {\r\n        uint32_t Shift;\r\n\r\n        if (((Code >> 9) & 0x7U) == 4) {\r\n            unsigned int j;\r\n\r\n\r\n            for (j = 0; j < 104; j++) {\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n                if (DCS_Options[j] == (Code & 0x1FF))\r\n\r\n#else\r\n                    uint8_t read_tmp[2];\r\n        EEPROM_ReadBuffer(0x02C64+(j)*2, read_tmp, 2);\r\n        uint16_t DCS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\n            if (DCS_Options_read == (Code & 0x1FF))\r\n\r\n\r\n#endif\r\n                    if (DCS_GetGolayCodeWord(2, j) == Code)\r\n                        return j;\r\n            }\r\n        }\r\n\r\n        Shift = Code >> 1;\r\n        if (Code & 1U)\r\n            Shift |= 0x400000U;\r\n        Code = Shift;\r\n    }\r\n\r\n    return 0xFF;\r\n}\r\n\r\nuint8_t DCS_GetCtcssCode(int Code) {\r\n    unsigned int i;\r\n    uint8_t Result = 0xFF;\r\n    int Smallest = 50;\r\n\r\n    for (i = 0; i < 50; i++) {\r\n\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n        int Delta = Code - CTCSS_Options[i];\r\n        if (Delta < 0)\r\n            Delta = -(Code - CTCSS_Options[i]);\r\n#else\r\n        uint8_t read_tmp[2];\r\n        EEPROM_ReadBuffer(0x02C00+i*2, read_tmp, 2);\r\n        uint16_t CTCSS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\n\r\n        int Delta = Code - CTCSS_Options_read;\r\n        if (Delta < 0)\r\n            Delta = -(Code - CTCSS_Options_read);\r\n#endif\r\n        if (Smallest > Delta) {\r\n            Smallest = Delta;\r\n            Result = i;\r\n        }\r\n    }\r\n\r\n    return Result;\r\n}\r\n\r\n#ifdef TEST_UNDE_CTCSS\r\n\r\nuint16_t DCS_GetCtcssCode_ALL(int Code)\r\n{\r\n    unsigned int i;\r\n    uint16_t      Result = 0xFFFF;\r\n    int          Smallest = 50;\r\n\r\n    for (i = 0; i <2550; i++)\r\n    {\r\n        int Delta = Code - i;\r\n        if (Delta < 0)\r\n            Delta = -(Code - i);\r\n        if (Smallest > Delta)\r\n        {\r\n            Smallest = Delta;\r\n            Result   = i;\r\n        }\r\n    }\r\n\r\n    return Result;\r\n}\r\n#endif"
  },
  {
    "path": "dcs.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DCS_H\r\n#define DCS_H\r\n\r\n#include <stdint.h>\r\n\r\nenum DCS_CodeType_t\r\n{\r\n\tCODE_TYPE_OFF = 0,\r\n\tCODE_TYPE_CONTINUOUS_TONE,\r\n\tCODE_TYPE_DIGITAL,\r\n\tCODE_TYPE_REVERSE_DIGITAL\r\n};\r\n\r\ntypedef enum DCS_CodeType_t DCS_CodeType_t;\r\n\r\nenum {\r\n\tCDCSS_POSITIVE_CODE = 1U,\r\n\tCDCSS_NEGATIVE_CODE = 2U,\r\n};\r\n\r\nextern const uint16_t CTCSS_Options[50];\r\nextern const uint16_t DCS_Options[104];\r\n\r\nuint32_t DCS_GetGolayCodeWord(DCS_CodeType_t CodeType, uint8_t Option);\r\nuint8_t DCS_GetCdcssCode(uint32_t Code);\r\nuint8_t DCS_GetCtcssCode(int Code);\r\n#ifdef TEST_UNDE_CTCSS\r\n\r\nuint16_t DCS_GetCtcssCode_ALL(int Code);\r\n#endif\r\n#endif\r\n\r\n"
  },
  {
    "path": "debugging.h",
    "content": "#ifndef DEBUGGING_H\r\n#define DEBUGGING_H\r\n#ifdef ENABLE_UART\r\n#include \"driver/uart.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"string.h\"\r\n#include <stdio.h>\r\n\r\n#include \"am_fix.h\"\r\n\r\nstatic inline void LogUartf(const char* format, ...)\r\n{\r\n\tchar buffer[128];\r\n\tva_list va;\r\n\tva_start(va, format);\r\n\tvsnprintf(buffer, (size_t)-1, format, va);\r\n\tva_end(va);\r\n\tUART_Send(buffer, strlen(buffer));\r\n}\r\n\r\nstatic inline void LogUart(const char *const str)\r\n{\r\n\tUART_Send(str, strlen(str));\r\n}\r\n\r\nstatic inline void LogRegUart(uint16_t reg)\r\n{\r\n\tuint16_t regVal = BK4819_ReadRegister(reg);\r\n\tchar buf[32];\r\n\tsprintf(buf, \"reg%02X: %04X\\n\", reg, regVal);\r\n\tLogUart(buf);\r\n}\r\n\r\nstatic inline void LogPrint()\r\n{\r\n\tuint16_t rssi = BK4819_GetRSSI();\r\n\tuint16_t reg7e = BK4819_ReadRegister(0x7E);\r\n\tchar buf[32];\r\n\tsprintf(buf, \"reg7E: %d  %2d  %6d  %2d  %d   rssi: %d\\n\", (reg7e >> 15),\r\n\t\t(reg7e >> 12) & 0b111, (reg7e >> 5) & 0b1111111,\r\n\t\t(reg7e >> 2) & 0b111, (reg7e >> 0) & 0b11, rssi);\r\n\tLogUart(buf);\r\n}\r\n\r\n#endif\r\n\r\n#endif"
  },
  {
    "path": "del_linux.sh",
    "content": "#!/bin/bash\ntarget_directory=\"./\"\nfind \"$target_directory\" -type f \\( -name \"*.o\" -o -name \"*.d\" \\)  -delete\necho \"Deletion complete.\"\n"
  },
  {
    "path": "del_win.bat",
    "content": "@echo off\nsetlocal\n\nrem ĿĿ¼\nset \"target_directory=./\"  rem 滻ΪĿĿ¼·\n\nrem ɾ .o  .d ļ\nfor /r \"%target_directory%\" %%f in (*.o *.d) do (\n    del \"%%f\"\n)\n\necho Deletion complete.\nendlocal\n\n"
  },
  {
    "path": "doc/多普勒eeprom详细说明.txt",
    "content": "0x02BA0~0x2BA9 10B,卫星名称,首字符在前,最多9个英文，最后一个为'\\0'\n\n\n0x2BAA 1B,开始过境时间的年份的十位个位，0~99，如:2024即为24\n0x2BAB 1B,开始过境时间的月份，1~12\n0x2BAC 1B,开始过境时间的日期，1~31\n0x2BAD 1B,开始过境时间的时，0~23\n0x2BAE 1B,开始过境时间的分，0~59\n0x2BAF 1B,开始过境时间的秒，0~59\n\n0x2BB0 1B,离境时间的年份的十位个位，0~99，如:2077即为77\n0x2BB1 1B,离境时间的月份，1~12\n0x2BB2 1B,离境时间的日期，1~31\n0x2BB3 1B,离境时间的时，0~23\n0x2BB4 1B,离境时间的分，0~59\n0x2BB5 1B,离境时间的秒，0~59\n\n0x2BB6~0x2BB7 2B，总的过境时间（秒），低位在前，高位在后\n\n0x2BB8~0x2BB9 2B，手台的发射亚音，低位在前，高位在后\n0x2BBA~0x2BBB 2B，手台的接收亚音，低位在前，高位在后\n\n0x2BBC~0X2BBF ,4B,为开始过境时间的UNIX时间戳与2000年1月1日UNIX时间戳的差,4B，正整数，低位在前，高位在后\n0X2BC0~0X2BC5 时间\n第n秒的卫星数据共8B，从0x1E200开始存放，2秒更新一次，最多支持(0X20000-0x1E200)/8*2=1920s=32min\n也就是说:0B~7B放第1秒卫星的频率（第1秒=开始过境时间）\n       8B~15B放第3秒卫星的频率\n       16B~23B放第5秒卫星的频率\n8B包括:\n        上行频率/10（正整数hz）4B、下行频率/10(正整数hz)4B\n        第1B~4B:上行频率/10,只有正,如:438.5MHZ，那么为438,500,00，都是低位在前，高位在后\n        第5B~8B:下行频率/10,只有正,如:144.5MHZ，那么为144,500,00，都是低位在前，高位在后\n\n        (K5频率精度为10，所以/10方便处理)\n\n\n"
  },
  {
    "path": "dp32g030.cfg",
    "content": "transport select hla_swd\n\nreset_config srst_only srst_nogate connect_assert_srst\ngdb breakpoint_override hard\n\nadapter speed 24000\n\nadapter srst delay 100\n\nreset_config srst_nogate\n\nset _CHIP_NAME DP32G0xx\nset CPUTAPID 0x0bb11477\n\n\n# Create a new dap, with name chip and role CPU, -enable let's OpenOCD to know to add it to the scan\nswd newdap $_CHIP_NAME cpu -enable -expected-id $CPUTAPID\n\n\n# Create the DAP instance, this must be explicitly created according to the OpenOCD docs\ndap create $_CHIP_NAME.dap -chain-position $_CHIP_NAME.cpu\n\n\n# Set up the GDB target for the CPU, cortex_m is the CPU type,\ntarget create $_CHIP_NAME.cpu cortex_m -dap $_CHIP_NAME.dap\n\n\nset _SECTOR_SIZE 512\n\n\nproc uv_clear_flash_sector {sector_number} {\n\techo [format \"Erasing sector 0x%02x = offset 0x%04x\" [expr {$sector_number}]  [expr {$sector_number*256}]  ]\n\twrite_memory 0x4006F000 32 {0x09}                           ;#set erasing mode\n\twrite_memory 0x4006F004 32 [expr {$sector_number << 6}]\n\twrite_memory 0x4006F01c 32 {0xAA}                           ;#unlock flash\n\twrite_memory 0x4006F010 32 {0x01}                           ;#set OPSTART=1\n\tread_memory 0x4006F014 32 1                                 ;#check status for 0x02\n\tuv_wait_busy\n\twrite_memory 0x4006F018 32 {0x55}                           ;#lock flash\n}\n\n\nproc uv_clear_whole_flash {} {\n\tfor {set i 0} {$i < 0x100} {incr i} {\n\t\tuv_clear_flash_sector $i\n\t}\n}\n\nproc uv_clear_sectors {sectors_count} {\n\tfor {set i 0} {$i < $sectors_count} {incr i} {\n\t\tuv_clear_flash_sector $i\n\t}\n}\n\n\nproc uv_flash_unlock {} {\n\twrite_memory 0x4006F01c 32 {0xAA}     ;#unlock flash\n\tuv_wait_busy\n}\n\n\nproc uv_flash_lock {} {\n\twrite_memory 0x4006F018 32 {0x55}     ;#lock flash\n\tuv_wait_busy\n}\n\n\nproc uv_flash_write {address value} {\n\twrite_memory 0x4006F000 32 {0x05}                          ;#set writing mode\n\twrite_memory 0x4006F004 32 [expr {($address>>2)+0xC000}]   ;#set address in flash\n\twrite_memory 0x4006F008 32 $value                          ;#set data\n\twrite_memory 0x4006F010 32 {0x01}                          ;#set OPSTART=1\n\twhile {1} {\n\t\tset status [read_memory 0x4006F014 32 1]\n\t\tif {($status & 0x4) != 0} {\n\t\t\tbreak\n\t\t}\n\t}\n\tuv_wait_busy\n}\nproc uv_wait_busy {} {\n\twhile {1} {\n\t\tset status [read_memory 0x4006F014 32 1]\n\t\tif {($status & 0x2) == 0} {\n\t\t\tbreak\n\t\t}\n\t}\n}\n\nproc write_image {filename address} {\n\tglobal _SECTOR_SIZE\n\n\tset fs [file size $filename]\n\tset fd [open $filename \"rb\"]\n\n\techo \"Checking mask\"\n\tset status [read_memory 0x4006F020 32 1]\n\tif {$status != 6} {\n\t\techo \"Changing mask\"\n\t\twrite_memory 0x4006F020 32 0\n\t\tuv_wait_busy\n\t\twrite_memory 0x4006F020 32 6\n\t\tuv_wait_busy\n\t\tset status [read_memory 0x4006F020 32 1]\n\t\tif {$status != 6} {\n\t\t\techo [format \"Cannot set flash mask %d!\" $status]\n\t\t\tclose $fd\n\t\t\treturn\n\t\t}\n\t}\n\tuv_clear_sectors [expr {(($fs+$_SECTOR_SIZE-1)&(0x10000000-$_SECTOR_SIZE))/($_SECTOR_SIZE/2)}]\n\tuv_flash_unlock\n\n\tset addr $address\n\twhile {![eof $fd]} {\n\t\tset data [read $fd 4]\n\t\tif {[string length $data] == 4} {\n\t\t\tset b0 [scan [string index $data 0] %c]\n\t\t\tset b1 [scan [string index $data 1] %c]\n\t\t\tset b2 [scan [string index $data 2] %c]\n\t\t\tset b3 [scan [string index $data 3] %c]\n\t\t\tset i_data [expr {$b0 | $b1 << 8 | $b2 << 16 | $b3 << 24}]\n\n\t\t\techo [format \"Writing 0x%04x to address 0x%04x (%02d %%)\" $i_data $addr [expr {(100*($addr+4)/$fs)}]]\n\t\t\tuv_flash_write $addr $i_data\n\t\t\tincr addr 4\n\t\t}\n\t}\n\tuv_flash_lock\n\n\tclose $fd\n}\n\n# dap init\ninit\nhalt\n# reset halt"
  },
  {
    "path": "driver/adc.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"ARMCM0.h\"\r\n#include \"adc.h\"\r\n#include \"bsp/dp32g030/irq.h\"\r\n#include \"bsp/dp32g030/saradc.h\"\r\n#include \"bsp/dp32g030/syscon.h\"\r\n\r\nuint8_t ADC_GetChannelNumber(ADC_CH_MASK Mask) {\r\n    return __builtin_ctz(Mask);\r\n}\r\n\r\nvoid ADC_Disable(void) {\r\n    SARADC_CFG = (SARADC_CFG & ~SARADC_CFG_ADC_EN_MASK) | SARADC_CFG_ADC_EN_BITS_DISABLE;\r\n}\r\n\r\nvoid ADC_Enable(void) {\r\n    SARADC_CFG = (SARADC_CFG & ~SARADC_CFG_ADC_EN_MASK) | SARADC_CFG_ADC_EN_BITS_ENABLE;\r\n}\r\n\r\nvoid ADC_SoftReset(void) {\r\n    SARADC_START = (SARADC_START & ~SARADC_START_SOFT_RESET_MASK) | SARADC_START_SOFT_RESET_BITS_ASSERT;\r\n    SARADC_START = (SARADC_START & ~SARADC_START_SOFT_RESET_MASK) | SARADC_START_SOFT_RESET_BITS_DEASSERT;\r\n}\r\n// The firmware thinks W_SARADC_SMPL_CLK_SEL is at [8:7] but the TRM says it's at [10:9]\r\n#define FW_R_SARADC_SMPL_SHIFT 7\r\n#define FW_R_SARADC_SMPL_MASK (3U << FW_R_SARADC_SMPL_SHIFT)\r\n\r\nuint32_t ADC_GetClockConfig(void) {\r\n    uint32_t Value;\r\n\r\n    Value = SYSCON_CLK_SEL;\r\n\r\n    Value = 0\r\n            | (Value & ~(SYSCON_CLK_SEL_R_PLL_MASK | FW_R_SARADC_SMPL_MASK))\r\n            | (((Value & SYSCON_CLK_SEL_R_PLL_MASK) >> SYSCON_CLK_SEL_R_PLL_SHIFT) << SYSCON_CLK_SEL_W_PLL_SHIFT)\r\n            | (((Value & FW_R_SARADC_SMPL_MASK) >> FW_R_SARADC_SMPL_SHIFT) << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT);\r\n\r\n    return Value;\r\n}\r\n\r\nvoid ADC_Configure() {\r\n    SYSCON_DEV_CLK_GATE =\r\n            (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SARADC_MASK) | SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE;\r\n\r\n    ADC_Disable();\r\n\r\n    SYSCON_CLK_SEL = (ADC_GetClockConfig() & ~SYSCON_CLK_SEL_W_SARADC_SMPL_MASK) |\r\n                     ((SYSCON_CLK_SEL_W_SARADC_SMPL_VALUE_DIV2 << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) & SYSCON_CLK_SEL_W_SARADC_SMPL_MASK);\r\n\r\n    SARADC_CFG = 0\r\n                 | (SARADC_CFG & ~(0\r\n                                   | SARADC_CFG_CH_SEL_MASK\r\n                                   | SARADC_CFG_AVG_MASK\r\n                                   | SARADC_CFG_CONT_MASK\r\n                                   | SARADC_CFG_SMPL_SETUP_MASK\r\n                                   | SARADC_CFG_MEM_MODE_MASK\r\n                                   | SARADC_CFG_SMPL_CLK_MASK\r\n                                   | SARADC_CFG_SMPL_WIN_MASK\r\n                                   | SARADC_CFG_ADC_TRIG_MASK\r\n                                   | SARADC_CFG_DMA_EN_MASK\r\n    ))\r\n                 | (((ADC_CH4 | ADC_CH9) << SARADC_CFG_CH_SEL_SHIFT) & SARADC_CFG_CH_SEL_MASK)\r\n                 | ((SARADC_CFG_AVG_VALUE_8_SAMPLE << SARADC_CFG_AVG_SHIFT) & SARADC_CFG_AVG_MASK)\r\n                 | ((SARADC_CFG_CONT_VALUE_SINGLE<< SARADC_CFG_CONT_SHIFT) & SARADC_CFG_CONT_MASK)\r\n                 | ((SARADC_CFG_SMPL_SETUP_VALUE_1_CYCLE << SARADC_CFG_SMPL_SETUP_SHIFT) & SARADC_CFG_SMPL_SETUP_MASK)\r\n                 | ((SARADC_CFG_MEM_MODE_VALUE_CHANNEL << SARADC_CFG_MEM_MODE_SHIFT) & SARADC_CFG_MEM_MODE_MASK)\r\n                 | ((SARADC_CFG_SMPL_CLK_VALUE_INTERNAL<< SARADC_CFG_SMPL_CLK_SHIFT) & SARADC_CFG_SMPL_CLK_MASK)\r\n                 | ((SARADC_CFG_SMPL_WIN_VALUE_15_CYCLE << SARADC_CFG_SMPL_WIN_SHIFT) & SARADC_CFG_SMPL_WIN_MASK)\r\n                 | ((SARADC_CFG_ADC_TRIG_VALUE_CPU<< SARADC_CFG_ADC_TRIG_SHIFT) & SARADC_CFG_ADC_TRIG_MASK)\r\n                 | ((SARADC_CFG_DMA_EN_VALUE_DISABLE << SARADC_CFG_DMA_EN_SHIFT) & SARADC_CFG_DMA_EN_MASK);\r\n\r\n    SARADC_EXTTRIG_SEL =0;\r\n\r\n        SARADC_CALIB_OFFSET =\r\n                (SARADC_CALIB_OFFSET & ~SARADC_CALIB_OFFSET_VALID_MASK) | SARADC_CALIB_OFFSET_VALID_BITS_YES;\r\n\r\n        SARADC_CALIB_KD = (SARADC_CALIB_KD & ~SARADC_CALIB_KD_VALID_MASK) | SARADC_CALIB_KD_VALID_BITS_YES;\r\n\r\n\r\n    SARADC_IF = 0xFFFFFFFF;\r\n    SARADC_IE = 0\r\n                | (SARADC_IE & ~(0\r\n                                 | SARADC_IE_CHx_EOC_MASK\r\n                                 | SARADC_IE_FIFO_FULL_MASK\r\n                                 | SARADC_IE_FIFO_HFULL_MASK\r\n    ))\r\n                | ((SARADC_IE_CHx_EOC_VALUE_NONE<< SARADC_IE_CHx_EOC_SHIFT) & SARADC_IE_CHx_EOC_MASK)\r\n                | ((SARADC_IE_FIFO_FULL_VALUE_DISABLE<< SARADC_IE_FIFO_FULL_SHIFT) & SARADC_IE_FIFO_FULL_MASK)\r\n                | ((SARADC_IE_FIFO_HFULL_VALUE_DISABLE << SARADC_IE_FIFO_HFULL_SHIFT) & SARADC_IE_FIFO_HFULL_MASK);\r\n\r\n    if (SARADC_IE == 0) {\r\n        NVIC_DisableIRQ((IRQn_Type) DP32_SARADC_IRQn);\r\n    } else {\r\n        NVIC_EnableIRQ((IRQn_Type) DP32_SARADC_IRQn);\r\n    }\r\n}\r\n\r\nvoid ADC_Start(void) {\r\n    SARADC_START = (SARADC_START & ~SARADC_START_START_MASK) | SARADC_START_START_BITS_ENABLE;\r\n}\r\n\r\nbool ADC_CheckEndOfConversion(ADC_CH_MASK Mask) {\r\n    volatile ADC_Channel_t *pChannels = (volatile ADC_Channel_t *) &SARADC_CH0;\r\n    uint8_t Channel = ADC_GetChannelNumber(Mask);\r\n\r\n    return (pChannels[Channel].STAT & ADC_CHx_STAT_EOC_MASK) >> ADC_CHx_STAT_EOC_SHIFT;\r\n}\r\n\r\nuint16_t ADC_GetValue(ADC_CH_MASK Mask) {\r\n    volatile ADC_Channel_t *pChannels = (volatile ADC_Channel_t *) &SARADC_CH0;\r\n    uint8_t Channel = ADC_GetChannelNumber(Mask);\r\n\r\n    SARADC_IF = 1 << Channel; // TODO: Or just use 'Mask'\r\n\r\n    return (pChannels[Channel].DATA & ADC_CHx_DATA_DATA_MASK) >> ADC_CHx_DATA_DATA_SHIFT;\r\n}\r\n\r\n"
  },
  {
    "path": "driver/adc.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_ADC_H\r\n#define DRIVER_ADC_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\nenum ADC_CH_MASK {\r\n\tADC_CH0 = 0x0001U,\r\n\r\n\tADC_CH1 = 0x0002U,\r\n\tADC_CH2 = 0x0004U,\r\n\tADC_CH3 = 0x0008U,\r\n\tADC_CH4 = 0x0010U,\r\n\tADC_CH5 = 0x0020U,\r\n\tADC_CH6 = 0x0040U,\r\n\tADC_CH7 = 0x0080U,\r\n\tADC_CH8 = 0x0100U,\r\n\tADC_CH9 = 0x0200U,\r\n\tADC_CH10 = 0x0400U,\r\n\tADC_CH11 = 0x0800U,\r\n\tADC_CH12 = 0x1000U,\r\n\tADC_CH13 = 0x2000U,\r\n\tADC_CH14 = 0x4000U,\r\n\tADC_CH15 = 0x8000U,\r\n};\r\n\r\n\r\ntypedef enum ADC_CH_MASK ADC_CH_MASK;\r\n\r\n//typedef struct {\r\n//\tuint16_t EXTTRIG_SEL;\r\n//\tuint16_t IE_CHx_EOC;\r\n//\tADC_CH_MASK CH_SEL;\r\n//\tuint8_t CLK_SEL;\r\n//\tuint8_t AVG;\r\n//\tuint8_t CONT;\r\n//\tuint8_t MEM_MODE;\r\n//\tuint8_t SMPL_CLK;\r\n//\tuint8_t SMPL_SETUP;\r\n//\tuint8_t SMPL_WIN;\r\n//\tuint8_t ADC_TRIG;\r\n//\tuint8_t DMA_EN;\r\n//\tuint8_t IE_FIFO_HFULL;\r\n//\tuint8_t IE_FIFO_FULL;\r\n//\tbool CALIB_OFFSET_VALID;\r\n//\tbool CALIB_KD_VALID;\r\n//\tuint8_t _pad[1];\r\n//} ADC_Config_t;\r\n\r\nuint8_t ADC_GetChannelNumber(ADC_CH_MASK Mask);\r\nvoid ADC_Disable(void);\r\nvoid ADC_Enable(void);\r\nvoid ADC_SoftReset(void);\r\nuint32_t ADC_GetClockConfig(void);\r\nvoid ADC_Configure();\r\nvoid ADC_Start(void);\r\nbool ADC_CheckEndOfConversion(ADC_CH_MASK Mask);\r\nuint16_t ADC_GetValue(ADC_CH_MASK Mask);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/aes.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <stdbool.h>\r\n\r\n#include \"bsp/dp32g030/aes.h\"\r\n#include \"driver/aes.h\"\r\n\r\nstatic void AES_Setup_ENC_CBC(bool IsDecrypt, const void *pKey, const void *pIv) {\r\n    const uint32_t *pK = (const uint32_t *) pKey;\r\n    const uint32_t *pI = (const uint32_t *) pIv;\r\n\r\n    (void) IsDecrypt;    // unused\r\n\r\n    AES_CR = (AES_CR & ~AES_CR_EN_MASK) | AES_CR_EN_BITS_DISABLE;\r\n    AES_CR = AES_CR_CHMOD_BITS_CBC;\r\n    AES_KEYR3 = pK[0];\r\n    AES_KEYR2 = pK[1];\r\n    AES_KEYR1 = pK[2];\r\n    AES_KEYR0 = pK[3];\r\n    AES_IVR3 = pI[0];\r\n    AES_IVR2 = pI[1];\r\n    AES_IVR1 = pI[2];\r\n    AES_IVR0 = pI[3];\r\n    AES_CR = (AES_CR & ~AES_CR_EN_MASK) | AES_CR_EN_BITS_ENABLE;\r\n}\r\n\r\nstatic void AES_Transform(const void *pIn, void *pOut) {\r\n    const uint32_t *pI = (const uint32_t *) pIn;\r\n    uint32_t *pO = (uint32_t *) pOut;\r\n\r\n    AES_DINR = pI[0];\r\n    AES_DINR = pI[1];\r\n    AES_DINR = pI[2];\r\n    AES_DINR = pI[3];\r\n\r\n    while ((AES_SR & AES_SR_CCF_MASK) == AES_SR_CCF_BITS_NOT_COMPLETE) {\r\n    }\r\n\r\n    pO[0] = AES_DOUTR;\r\n    pO[1] = AES_DOUTR;\r\n    pO[2] = AES_DOUTR;\r\n    pO[3] = AES_DOUTR;\r\n\r\n    AES_CR |= AES_CR_CCFC_BITS_SET;\r\n}\r\n\r\nvoid AES_Encrypt(const void *pKey, const void *pIv, const void *pIn, void *pOut, uint8_t NumBlocks) {\r\n    const uint8_t *pI = (const uint8_t *) pIn;\r\n    uint8_t *pO = (uint8_t *) pOut;\r\n    uint8_t i;\r\n\r\n    AES_Setup_ENC_CBC(0, pKey, pIv);\r\n    for (i = 0; i < NumBlocks; i++) {\r\n        AES_Transform(pI + (i * 16), pO + (i * 16));\r\n    }\r\n}\r\n\r\n"
  },
  {
    "path": "driver/aes.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_AES_H\r\n#define DRIVER_AES_H\r\n\r\n#include <stdint.h>\r\n\r\nvoid AES_Encrypt(const void *pKey, const void *pIv, const void *pIn, void *pOut, uint8_t NumBlocks);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/backlight.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"backlight.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"bsp/dp32g030/pwmplus.h\"\r\n#include \"bsp/dp32g030/portcon.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"settings.h\"\r\n\r\n// this is decremented once every 500ms\r\nuint16_t gBacklightCountdown_500ms = 0;\r\nbool backlightOn;\r\n\r\nvoid BACKLIGHT_InitHardware() {\r\n    // 48MHz / 94 / 1024 ~ 500Hz\r\n    const uint32_t PWM_FREQUENCY_HZ = 25000;\r\n    PWM_PLUS0_CLKSRC |= ((48000000 / 1024 / PWM_FREQUENCY_HZ) << 16);\r\n    PWM_PLUS0_PERIOD = 1023;\r\n\r\n    PORTCON_PORTB_SEL0 &= ~(0\r\n                            // Back light\r\n                            | PORTCON_PORTB_SEL0_B6_MASK\r\n    );\r\n    PORTCON_PORTB_SEL0 |= 0\r\n                          // Back light PWM\r\n                          | PORTCON_PORTB_SEL0_B6_BITS_PWMP0_CH0;\r\n\r\n    PWM_PLUS0_GEN =\r\n            PWMPLUS_GEN_CH0_OE_BITS_ENABLE |\r\n            PWMPLUS_GEN_CH0_OUTINV_BITS_ENABLE |\r\n            0;\r\n\r\n    PWM_PLUS0_CFG =\r\n            PWMPLUS_CFG_CNT_REP_BITS_ENABLE |\r\n            PWMPLUS_CFG_COUNTER_EN_BITS_ENABLE |\r\n            0;\r\n}\r\nunsigned short BACKLIGHT_MAP[7]={11,21,41,121,241,481,0};\r\n\r\nvoid BACKLIGHT_TurnOn(void) {\r\n    if (gEeprom.BACKLIGHT_TIME == 0) {\r\n        BACKLIGHT_TurnOff();\r\n        return;\r\n    }\r\n\r\n    backlightOn = true;\r\n    BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MAX);\r\n    gBacklightCountdown_500ms = BACKLIGHT_MAP[gEeprom.BACKLIGHT_TIME-1];\r\n\r\n}\r\n\r\nvoid BACKLIGHT_TurnOff() {\r\n#ifdef ENABLE_BLMIN_TMP_OFF\r\n    register uint8_t tmp;\r\n\r\n\r\n        tmp = 0;\r\n\r\n    BACKLIGHT_SetBrightness(tmp);\r\n#else\r\n    BACKLIGHT_SetBrightness(0);\r\n#endif\r\n    gBacklightCountdown_500ms = 0;\r\n    backlightOn = false;\r\n}\r\n\r\nbool BACKLIGHT_IsOn() {\r\n    return backlightOn;\r\n}\r\n\r\nstatic uint8_t currentBrightness;\r\n\r\nvoid BACKLIGHT_SetBrightness(uint8_t brigtness) {\r\n    const uint8_t value[]= {0,3,6,9,15,24,38,62,100,159,255};\r\n    currentBrightness = brigtness;\r\n    PWM_PLUS0_CH0_COMP =  value[brigtness]<<2;\r\n    //PWM_PLUS0_SWLOAD = 1;\r\n}\r\n\r\nuint8_t BACKLIGHT_GetBrightness(void) {\r\n    return currentBrightness;\r\n}"
  },
  {
    "path": "driver/backlight.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_BACKLIGHT_H\r\n#define DRIVER_BACKLIGHT_H\r\n\r\n#include <stdint.h>\r\n#include <stdbool.h>\r\n\r\nextern uint16_t gBacklightCountdown_500ms;\r\nextern uint8_t gBacklightBrightness;\r\n\r\n#ifdef ENABLE_BLMIN_TMP_OFF\r\ntypedef enum {\r\n    BLMIN_STAT_ON,\r\n    BLMIN_STAT_OFF,\r\n    BLMIN_STAT_UNKNOWN\r\n} BLMIN_STAT_t;\r\n#endif\r\n\r\nvoid BACKLIGHT_InitHardware();\r\nvoid BACKLIGHT_TurnOn();\r\nvoid BACKLIGHT_TurnOff();\r\nbool BACKLIGHT_IsOn();\r\nvoid BACKLIGHT_SetBrightness(uint8_t brigtness);\r\nuint8_t BACKLIGHT_GetBrightness(void);\r\nextern unsigned short BACKLIGHT_MAP[7];\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/bk1080-regs.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef BK1080_REGS_H\r\n#define BK1080_REGS_H\r\n\r\nenum BK1080_Register_t {\r\n\tBK1080_REG_00                       = 0x00U,\r\n\tBK1080_REG_02_POWER_CONFIGURATION   = 0x02U,\r\n\tBK1080_REG_03_CHANNEL               = 0x03U,\r\n\tBK1080_REG_05_SYSTEM_CONFIGURATION2 = 0x05U,\r\n\tBK1080_REG_07                       = 0x07U,\r\n\tBK1080_REG_10                       = 0x0AU,\r\n\tBK1080_REG_25_INTERNAL              = 0x19U,\r\n};\r\n\r\ntypedef enum BK1080_Register_t BK1080_Register_t;\r\n\r\n// REG 07\r\n\r\n#define BK1080_REG_07_SHIFT_FREQD\t\t4\r\n#define BK1080_REG_07_SHIFT_SNR\t\t\t0\r\n\r\n#define BK1080_REG_07_MASK_FREQD\t\t(0xFFFU << BK1080_REG_07_SHIFT_FREQD)\r\n#define BK1080_REG_07_MASK_SNR\t\t\t(0x00FU << BK1080_REG_07_SHIFT_SNR)\r\n\r\n#define BK1080_REG_07_GET_FREQD(x)\t\t(((x) & BK1080_REG_07_MASK_FREQD) >> BK1080_REG_07_SHIFT_FREQD)\r\n#define BK1080_REG_07_GET_SNR(x)\t\t(((x) & BK1080_REG_07_MASK_SNR) >> BK1080_REG_07_SHIFT_SNR)\r\n\r\n// REG 10\r\n\r\n#define BK1080_REG_10_SHIFT_AFCRL\t\t12\r\n#define BK1080_REG_10_SHIFT_RSSI\t\t0\r\n\r\n#define BK1080_REG_10_MASK_AFCRL\t\t(0x01U << BK1080_REG_10_SHIFT_AFCRL)\r\n#define BK1080_REG_10_MASK_RSSI\t\t\t(0xFFU << BK1080_REG_10_SHIFT_RSSI)\r\n\r\n#define BK1080_REG_10_AFCRL_NOT_RAILED\t\t(0U << BK1080_REG_10_SHIFT_AFCRL)\r\n#define BK1080_REG_10_AFCRL_RAILED\t\t(1U << BK1080_REG_10_SHIFT_AFCRL)\r\n\r\n#define BK1080_REG_10_GET_RSSI(x)\t\t(((x) & BK1080_REG_10_MASK_RSSI) >> BK1080_REG_10_SHIFT_RSSI)\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/bk1080.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"bk1080.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/i2c.h\"\r\n#include \"driver/system.h\"\r\n#include \"frequencies.h\"\r\n#include \"misc.h\"\r\n\r\n//#define CHAN_SPACING     0u  // 200kHz\r\n//#define CHAN_SPACING     1u  // 100kHz\r\n#define   CHAN_SPACING     2u  // 50kHz\r\n\r\n#define VOLUME             15u\r\n\r\n#define SEEK_THRESHOLD     10u\r\n\r\nconst freq_band_table_t FM_RADIO_FREQ_BAND_TABLE[] =\r\n        {\r\n                {875, 1080},   // 87.5 ~ 108 MHz\r\n                {760, 1080},   // 76   ~ 108 MHz\r\n                {760, 900},   // 76   ~  90 MHz\r\n                {640, 760}    // 64   ~  76 MHz\r\n        };\r\n\r\nstatic const uint16_t BK1080_RegisterTable[] =\r\n        {\r\n                0x0008,                 // 0x00\r\n                0x1080,                 // 0x01   chip ID\r\n                (1u << 9) | (1u << 0),  // 0x02   0x0201  0000001000000001\r\n                0x0000,                 // 0x03\r\n                0x40C0,                 // 0x04   0100000011000000\r\n                (SEEK_THRESHOLD << 8) | (0u << 6) | (CHAN_SPACING << 4) |\r\n                (VOLUME << 0), // 0x0A1F,  // 0x05  00001010 00 01 1111\r\n                0x002E,                 // 0x06   0000000000101110\r\n                0x02FF,                 // 0x07   0000001011111111\r\n                0x5B11,                 // 0x08   0101101100010001\r\n                0x0000,                 // 0x09\r\n                0x411E,                 // 0x0A   0100000100011110\r\n                0x0000,                 // 0x0B\r\n                0xCE00,                 // 0x0C   1100111000000000\r\n                0x0000,                 // 0x0D\r\n                0x0000,                 // 0x0E\r\n                0x1000,                 // 0x0F   1000000000000000\r\n                0x3197,                 // 0x10   0011000110010111\r\n                0x0000,                 // 0x11\r\n                0x13FF,                 // 0x12   0001001111111111\r\n                0x9852,                 // 0x13   1001100001010010\r\n                0x0000,                 // 0x14\r\n                0x0000,                 // 0x15\r\n                0x0008,                 // 0x16\r\n                0x0000,                 // 0x17\r\n                0x51E1,                 // 0x18   0101000111100001\r\n                0xA8BC,                 // 0x19   1010100010111100\r\n                0x2645,                 // 0x1A   0010011001000101\r\n                0x00E4,                 // 0x1B   0000000011100100\r\n                0x1CD8,                 // 0x1C   0001110011011000\r\n                0x3A50,                 // 0x1D   0011101001010000\r\n                0xEAE0,                 // 0x1E   1110101011100000\r\n                0x3000,                 // 0x1F   0011000000000000\r\n                0x0200,                 // 0x20   0010000000000000\r\n                0x0000                  // 0x21\r\n        };\r\n\r\nuint16_t BK1080_BaseFrequency;\r\nuint16_t BK1080_FrequencyDeviation;\r\n\r\nbool is_init;\r\nuint16_t BK1080_freq_lower;\r\nuint16_t BK1080_freq_upper;\r\nuint16_t BK1080_freq_base;\r\nint16_t BK1080_freq_offset;\r\n\r\nvoid BK1080_Init(const uint16_t frequency, const bool initialise) {\r\n    unsigned int i;\r\n\r\n    // determine the lower and upper frequency limits when multiple bands are used\r\n\r\n    if (!is_init) {\r\n        BK1080_freq_base = 0;\r\n        BK1080_freq_offset = 0;\r\n\r\n        BK1080_freq_lower = 0xffff;\r\n        BK1080_freq_upper = 0;\r\n\r\n        for (i = 0; i < ARRAY_SIZE(FM_RADIO_FREQ_BAND_TABLE); i++) {\r\n            const uint16_t lower = FM_RADIO_FREQ_BAND_TABLE[i].lower;\r\n            const uint16_t upper = FM_RADIO_FREQ_BAND_TABLE[i].upper;\r\n\r\n            if (BK1080_freq_lower > lower)\r\n                BK1080_freq_lower = lower;\r\n\r\n            if (BK1080_freq_upper < upper)\r\n                BK1080_freq_upper = upper;\r\n        }\r\n    }\r\n\r\n    if (initialise) {    // init and enable the chip\r\n\r\n        GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_BK1080);\r\n\r\n        if (!is_init) {\r\n            for (i = 0; i < ARRAY_SIZE(BK1080_RegisterTable); i++)\r\n                BK1080_WriteRegister(i, BK1080_RegisterTable[i]);\r\n\r\n            SYSTEM_DelayMs(250);\r\n\r\n            BK1080_WriteRegister(BK1080_REG_25_INTERNAL, 0xA83C);  // 1010 1000 0011 1100\r\n            BK1080_WriteRegister(BK1080_REG_25_INTERNAL, 0xA8BC);  // 1010 1000 1011 1100\r\n\r\n            SYSTEM_DelayMs(60);\r\n\r\n            is_init = true;\r\n        } else {\r\n            BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, (1u << 9) | (1u << 0));\r\n        }\r\n\r\n        BK1080_WriteRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2, 0x0A5F);  // 0000 1010 0101 1111\r\n\r\n        BK1080_SetFrequency(frequency);\r\n    } else {    // disable the chip\r\n\r\n        BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION,\r\n                             (1u << 9) | (1u << 6) | (1u << 0)); // 0x0241); // 0000 0010 0100 0001\r\n        GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_BK1080);\r\n    }\r\n}\r\n\r\nuint16_t BK1080_ReadRegister(BK1080_Register_t Register) {\r\n    uint8_t Value[2];\r\n    I2C_Start();\r\n    I2C_Write(0x80);\r\n    I2C_Write((Register << 1) | I2C_READ);\r\n    I2C_ReadBuffer(Value, sizeof(Value));\r\n    I2C_Stop();\r\n    return (Value[0] << 8) | Value[1];\r\n}\r\n\r\nvoid BK1080_WriteRegister(BK1080_Register_t Register, uint16_t Value) {\r\n    I2C_Start();\r\n    I2C_Write(0x80);\r\n    I2C_Write((Register << 1) | I2C_WRITE);\r\n    Value = ((Value >> 8) & 0xFF) | ((Value & 0xFF) << 8);\r\n    I2C_WriteBuffer(&Value, sizeof(Value));\r\n    I2C_Stop();\r\n}\r\n\r\nvoid BK1080_Mute(const bool Mute) {\r\n    BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, (1u << 9) | (1u << 0) | (Mute ? 1u << 14 : 0u));\r\n}\r\n\r\nvoid BK1080_SetFrequency(uint16_t Frequency) {\r\n    int channel;\r\n    uint16_t band = 0;\r\n\r\n    // determine which band to use\r\n    for (band = 0; band < ARRAY_SIZE(FM_RADIO_FREQ_BAND_TABLE); band++)\r\n        if (Frequency >= FM_RADIO_FREQ_BAND_TABLE[band].lower && Frequency < FM_RADIO_FREQ_BAND_TABLE[band].upper)\r\n            break;\r\n\r\n    if (band >= ARRAY_SIZE(FM_RADIO_FREQ_BAND_TABLE)) {\r\n        Frequency = BK1080_freq_lower;\r\n    }\r\n\r\n//\tchannel =  (int)Frequency - FM_RADIO_FREQ_BAND_TABLE[band].lower;       // 100kHz channel spacing\r\n    channel = ((int) Frequency - FM_RADIO_FREQ_BAND_TABLE[band].lower) * 2;  // 50kHz channel spacing\r\n    channel = (channel < 0) ? 0 : (channel > 1023) ? 1023 : channel;\r\n\r\n    BK1080_WriteRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2,\r\n                         (SEEK_THRESHOLD << 8) | (band << 6) | (CHAN_SPACING << 4) | (VOLUME << 0));\r\n\r\n    BK1080_WriteRegister(BK1080_REG_03_CHANNEL, (uint16_t) channel);\r\n//\tSYSTEM_DelayMs(1);\r\n    BK1080_WriteRegister(BK1080_REG_03_CHANNEL, (uint16_t) channel | (1u << 15));\r\n}\r\n\r\nint16_t BK1080_get_freq_offset(const uint16_t Frequency) {\r\n    BK1080_freq_base = Frequency;\r\n    BK1080_freq_offset = (int16_t) BK1080_ReadRegister(BK1080_REG_07) / 16;\r\n    return BK1080_freq_offset;\r\n}\r\n\r\nvoid BK1080_GetFrequencyDeviation(uint16_t Frequency) {\r\n    BK1080_BaseFrequency = Frequency;\r\n    BK1080_FrequencyDeviation = BK1080_ReadRegister(BK1080_REG_07) / 16;\r\n}"
  },
  {
    "path": "driver/bk1080.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_BK1080_H\r\n#define DRIVER_BK1080_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n#include \"driver/bk1080-regs.h\"\r\n\r\nextern uint16_t BK1080_BaseFrequency;\r\nextern uint16_t BK1080_FrequencyDeviation;\r\n\r\nvoid BK1080_Init(uint16_t Frequency, bool bDoScan);\r\nuint16_t BK1080_ReadRegister(BK1080_Register_t Register);\r\nvoid BK1080_WriteRegister(BK1080_Register_t Register, uint16_t Value);\r\nvoid BK1080_Mute(bool Mute);\r\nvoid BK1080_SetFrequency(uint16_t Frequency);\r\nvoid BK1080_GetFrequencyDeviation(uint16_t Frequency);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/bk4819-regs.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef BK4819_REGS_H\r\n#define BK4819_REGS_H\r\n\r\n#include <stdint.h>\r\ntypedef struct {\r\n  const char *name;\r\n  uint8_t num;\r\n  uint8_t offset;\r\n  uint16_t mask;\r\n  uint16_t inc;\r\n} RegisterSpec;\r\n\r\nstatic const RegisterSpec afcDisableRegSpec = {\"AFC Disable\", 0x73, 4, 1, 1};\r\nstatic const RegisterSpec afOutRegSpec = {\"AF Output Select\", 0x47, 8, 0xF, 1};\r\nstatic const RegisterSpec afDacGainRegSpec = {\"AF DAC Gain\", 0x48, 0, 0xF, 1};\r\n\r\nenum BK4819_REGISTER_t {\r\n\tBK4819_REG_00 = 0x00U,\r\n\tBK4819_REG_02 = 0x02U,\r\n\tBK4819_REG_06 = 0x06U,\r\n\tBK4819_REG_07 = 0x07U,\r\n\tBK4819_REG_08 = 0x08U,\r\n\tBK4819_REG_09 = 0x09U,\r\n\tBK4819_REG_0B = 0x0BU,\r\n\tBK4819_REG_0C = 0x0CU,\r\n\tBK4819_REG_0D = 0x0DU,\r\n\tBK4819_REG_0E = 0x0EU,\r\n\tBK4819_REG_10 = 0x10U,\r\n\tBK4819_REG_11 = 0x11U,\r\n\tBK4819_REG_12 = 0x12U,\r\n\tBK4819_REG_13 = 0x13U,\r\n\tBK4819_REG_14 = 0x14U,\r\n\tBK4819_REG_19 = 0x19U,\r\n\tBK4819_REG_1F = 0x1FU,\r\n\tBK4819_REG_20 = 0x20U,\r\n\tBK4819_REG_21 = 0x21U,\r\n\tBK4819_REG_24 = 0x24U,\r\n\tBK4819_REG_28 = 0x28U,\r\n\tBK4819_REG_29 = 0x29U,\r\n\tBK4819_REG_2B = 0x2BU,\r\n\tBK4819_REG_30 = 0x30U,\r\n\tBK4819_REG_31 = 0x31U,\r\n\tBK4819_REG_32 = 0x32U,\r\n\tBK4819_REG_33 = 0x33U,\r\n\tBK4819_REG_36 = 0x36U,\r\n\tBK4819_REG_37 = 0x37U,\r\n\tBK4819_REG_38 = 0x38U,\r\n\tBK4819_REG_39 = 0x39U,\r\n\tBK4819_REG_3A = 0x3AU,\r\n\tBK4819_REG_3B = 0x3BU,\r\n\tBK4819_REG_3C = 0x3CU,\r\n\tBK4819_REG_3D = 0x3DU,\r\n\tBK4819_REG_3E = 0x3EU,\r\n\tBK4819_REG_3F = 0x3FU,\r\n    BK4819_REG_40 = 0x40U,\r\n\r\n    BK4819_REG_43 = 0x43U,\r\n\tBK4819_REG_46 = 0x46U,\r\n\tBK4819_REG_47 = 0x47U,\r\n\tBK4819_REG_48 = 0x48U,\r\n\tBK4819_REG_49 = 0x49U,\r\n\tBK4819_REG_4D = 0x4DU,\r\n\tBK4819_REG_4E = 0x4EU,\r\n\tBK4819_REG_4F = 0x4FU,\r\n\tBK4819_REG_50 = 0x50U,\r\n\tBK4819_REG_51 = 0x51U,\r\n\tBK4819_REG_52 = 0x52U,\r\n\tBK4819_REG_58 = 0x58U,\r\n\tBK4819_REG_59 = 0x59U,\r\n\tBK4819_REG_5A = 0x5AU,\r\n\tBK4819_REG_5B = 0x5BU,\r\n\tBK4819_REG_5C = 0x5CU,\r\n\tBK4819_REG_5D = 0x5DU,\r\n    BK4819_REG_5E = 0x5EU,\r\n\r\n    BK4819_REG_5F = 0x5FU,\r\n\tBK4819_REG_63 = 0x63U,\r\n\tBK4819_REG_64 = 0x64U,\r\n\tBK4819_REG_65 = 0x65U,\r\n\tBK4819_REG_67 = 0x67U,\r\n\tBK4819_REG_68 = 0x68U,\r\n\tBK4819_REG_69 = 0x69U,\r\n\tBK4819_REG_6A = 0x6AU,\r\n\tBK4819_REG_6F = 0x6FU,\r\n\tBK4819_REG_70 = 0x70U,\r\n\tBK4819_REG_71 = 0x71U,\r\n\tBK4819_REG_72 = 0x72U,\r\n\tBK4819_REG_78 = 0x78U,\r\n\tBK4819_REG_79 = 0x79U,\r\n\tBK4819_REG_7A = 0x7AU,\r\n\tBK4819_REG_7B = 0x7BU,\r\n\tBK4819_REG_7C = 0x7CU,\r\n\tBK4819_REG_7D = 0x7DU,\r\n\tBK4819_REG_7E = 0x7EU,\r\n};\r\n\r\ntypedef enum BK4819_REGISTER_t BK4819_REGISTER_t;\r\n\r\nenum BK4819_GPIO_PIN_t {\r\n\tBK4819_GPIO0_PIN28_RX_ENABLE = 0,\r\n\tBK4819_GPIO1_PIN29_PA_ENABLE = 1,\r\n\tBK4819_GPIO3_PIN31_UHF_LNA = 3,\r\n\tBK4819_GPIO4_PIN32_VHF_LNA = 4,\r\n\tBK4819_GPIO5_PIN1_RED = 5,\r\n\tBK4819_GPIO6_PIN2_GREEN = 6,\r\n};\r\n\r\ntypedef enum BK4819_GPIO_PIN_t BK4819_GPIO_PIN_t;\r\n\r\n// REG 02\r\n\r\n#define BK4819_REG_02_SHIFT_FSK_TX_FINISHED\t\t15\r\n#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY\t14\r\n#define BK4819_REG_02_SHIFT_FSK_RX_FINISHED\t\t13\r\n#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL\t12\r\n#define BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND\t\t11\r\n#define BK4819_REG_02_SHIFT_CxCSS_TAIL\t\t\t10\r\n#define BK4819_REG_02_SHIFT_CDCSS_FOUND\t\t\t9\r\n#define BK4819_REG_02_SHIFT_CDCSS_LOST\t\t\t8\r\n#define BK4819_REG_02_SHIFT_CTCSS_FOUND\t\t\t7\r\n#define BK4819_REG_02_SHIFT_CTCSS_LOST\t\t\t6\r\n#define BK4819_REG_02_SHIFT_VOX_FOUND\t\t\t5\r\n#define BK4819_REG_02_SHIFT_VOX_LOST\t\t\t4\r\n#define BK4819_REG_02_SHIFT_SQUELCH_FOUND\t\t3\r\n#define BK4819_REG_02_SHIFT_SQUELCH_LOST\t\t2\r\n#define BK4819_REG_02_SHIFT_FSK_RX_SYNC\t\t\t1\r\n\r\n#define BK4819_REG_02_MASK_FSK_TX_FINISHED\t\t(1U << BK4819_REG_02_SHIFT_FSK_TX)\r\n#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_EMPTY\t(1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)\r\n#define BK4819_REG_02_MASK_FSK_RX_FINISHED\t\t(1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)\r\n#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_FULL\t\t(1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)\r\n#define BK4819_REG_02_MASK_DTMF_5TONE_FOUND\t\t(1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)\r\n#define BK4819_REG_02_MASK_CxCSS_TAIL\t\t\t(1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)\r\n#define BK4819_REG_02_MASK_CDCSS_FOUND\t\t\t(1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)\r\n#define BK4819_REG_02_MASK_CDCSS_LOST\t\t\t(1U << BK4819_REG_02_SHIFT_CDCSS_LOST)\r\n#define BK4819_REG_02_MASK_CTCSS_FOUND\t\t\t(1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)\r\n#define BK4819_REG_02_MASK_CTCSS_LOST\t\t\t(1U << BK4819_REG_02_SHIFT_CTCSS_LOST)\r\n#define BK4819_REG_02_MASK_VOX_FOUND\t\t\t(1U << BK4819_REG_02_SHIFT_VOX_FOUND)\r\n#define BK4819_REG_02_MASK_VOX_LOST\t\t\t(1U << BK4819_REG_02_SHIFT_VOX_LOST)\r\n#define BK4819_REG_02_MASK_SQUELCH_FOUND\t\t(1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)\r\n#define BK4819_REG_02_MASK_SQUELCH_LOST\t\t\t(1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)\r\n#define BK4819_REG_02_MASK_FSK_RX_SYNC\t\t\t(1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)\r\n\r\n#define BK4819_REG_02_FSK_TX_FINISHED\t\t\t(1U << BK4819_REG_02_SHIFT_FSK_TX_FINISHED)\r\n#define BK4819_REG_02_FSK_FIFO_ALMOST_EMPTY\t\t(1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)\r\n#define BK4819_REG_02_FSK_RX_FINISHED\t\t\t(1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)\r\n#define BK4819_REG_02_FSK_FIFO_ALMOST_FULL\t\t(1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)\r\n#define BK4819_REG_02_DTMF_5TONE_FOUND\t\t\t(1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)\r\n#define BK4819_REG_02_CxCSS_TAIL\t\t\t(1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)\r\n#define BK4819_REG_02_CDCSS_FOUND\t\t\t(1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)\r\n#define BK4819_REG_02_CDCSS_LOST\t\t\t(1U << BK4819_REG_02_SHIFT_CDCSS_LOST)\r\n#define BK4819_REG_02_CTCSS_FOUND\t\t\t(1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)\r\n#define BK4819_REG_02_CTCSS_LOST\t\t\t(1U << BK4819_REG_02_SHIFT_CTCSS_LOST)\r\n#define BK4819_REG_02_VOX_FOUND\t\t\t\t(1U << BK4819_REG_02_SHIFT_VOX_FOUND)\r\n#define BK4819_REG_02_VOX_LOST\t\t\t\t(1U << BK4819_REG_02_SHIFT_VOX_LOST)\r\n#define BK4819_REG_02_SQUELCH_FOUND\t\t\t(1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)\r\n#define BK4819_REG_02_SQUELCH_LOST\t\t\t(1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)\r\n#define BK4819_REG_02_FSK_RX_SYNC\t\t\t(1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)\r\n\r\n// REG 07\r\n\r\n#define BK4819_REG_07_SHIFT_FREQUENCY_MODE\t13\r\n#define BK4819_REG_07_SHIFT_FREQUENCY\t\t0\r\n\r\n#define BK4819_REG_07_MASK_FREQUENCY_MODE\t(0x0007U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)\r\n#define BK4819_REG_07_MASK_FREQUENCY\t\t(0x1FFFU << BK4819_REG_07_SHIFT_FREQUENCY)\r\n\r\n#define BK4819_REG_07_MODE_CTC1\t\t\t(0U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)\r\n#define BK4819_REG_07_MODE_CTC2\t\t\t(1U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)\r\n#define BK4819_REG_07_MODE_CDCSS\t\t(2U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)\r\n\r\n// REG 24\r\n\r\n#define BK4819_REG_24_SHIFT_UNKNOWN_15   15\r\n#define BK4819_REG_24_SHIFT_THRESHOLD    7\r\n#define BK4819_REG_24_SHIFT_UNKNOWN_6    6\r\n#define BK4819_REG_24_SHIFT_ENABLE       5\r\n#define BK4819_REG_24_SHIFT_SELECT       4\r\n#define BK4819_REG_24_SHIFT_MAX_SYMBOLS  0\r\n\r\n#define BK4819_REG_24_MASK_THRESHOLD     (0x2Fu << BK4819_REG_24_SHIFT_THRESHOLD)\r\n#define BK4819_REG_24_MASK_ENABLE        (0x01u << BK4819_REG_24_SHIFT_ENABLE)\r\n#define BK4819_REG_24_MASK_SELECT        (0x04u << BK4819_REG_24_SHIFT_SELECT)\r\n#define BK4819_REG_24_MASK_MAX_SYMBOLS   (0x0Fu << BK4819_REG_24_SHIFT_MAX_SYMBOLS)\r\n\r\n#define BK4819_REG_24_ENABLE             (1u << BK4819_REG_24_SHIFT_ENABLE)\r\n#define BK4819_REG_24_DISABLE            (0u << BK4819_REG_24_SHIFT_ENABLE)\r\n#define BK4819_REG_24_SELECT_DTMF        (1u << BK4819_REG_24_SHIFT_SELECT)\r\n#define BK4819_REG_24_SELECT_SELCALL     (0u << BK4819_REG_24_SHIFT_SELECT)\r\n\r\n// REG 30\r\n\r\n#define BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB\t15\r\n#define BK4819_REG_30_SHIFT_ENABLE_UNKNOWN\t14\r\n#define BK4819_REG_30_SHIFT_ENABLE_RX_LINK\t10\r\n#define BK4819_REG_30_SHIFT_ENABLE_AF_DAC\t9\r\n#define BK4819_REG_30_SHIFT_ENABLE_DISC_MODE\t8\r\n#define BK4819_REG_30_SHIFT_ENABLE_PLL_VCO\t4\r\n#define BK4819_REG_30_SHIFT_ENABLE_PA_GAIN\t3\r\n#define BK4819_REG_30_SHIFT_ENABLE_MIC_ADC\t2\r\n#define BK4819_REG_30_SHIFT_ENABLE_TX_DSP\t1\r\n#define BK4819_REG_30_SHIFT_ENABLE_RX_DSP\t0\r\n\r\n#define BK4819_REG_30_MASK_ENABLE_VCO_CALIB\t(0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB)\r\n#define BK4819_REG_30_MASK_ENABLE_UNKNOWN\t(0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN)\r\n#define BK4819_REG_30_MASK_ENABLE_RX_LINK\t(0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK)\r\n#define BK4819_REG_30_MASK_ENABLE_AF_DAC\t(0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC)\r\n#define BK4819_REG_30_MASK_ENABLE_DISC_MODE\t(0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE)\r\n#define BK4819_REG_30_MASK_ENABLE_PLL_VCO\t(0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO)\r\n#define BK4819_REG_30_MASK_ENABLE_PA_GAIN\t(0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN)\r\n#define BK4819_REG_30_MASK_ENABLE_MIC_ADC\t(0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC)\r\n#define BK4819_REG_30_MASK_ENABLE_TX_DSP\t(0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP)\r\n#define BK4819_REG_30_MASK_ENABLE_RX_DSP\t(0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP)\r\n\r\nenum {\r\n\tBK4819_REG_30_ENABLE_VCO_CALIB\t\t= (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),\r\n\tBK4819_REG_30_DISABLE_VCO_CALIB\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),\r\n\tBK4819_REG_30_ENABLE_UNKNOWN\t\t= (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),\r\n\tBK4819_REG_30_DISABLE_UNKNOWN\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),\r\n\tBK4819_REG_30_ENABLE_RX_LINK\t\t= (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),\r\n\tBK4819_REG_30_DISABLE_RX_LINK\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),\r\n\tBK4819_REG_30_ENABLE_AF_DAC\t\t= (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),\r\n\tBK4819_REG_30_DISABLE_AF_DAC\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),\r\n\tBK4819_REG_30_ENABLE_DISC_MODE\t\t= (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),\r\n\tBK4819_REG_30_DISABLE_DISC_MODE\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),\r\n\tBK4819_REG_30_ENABLE_PLL_VCO\t\t= (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),\r\n\tBK4819_REG_30_DISABLE_PLL_VCO\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),\r\n\tBK4819_REG_30_ENABLE_PA_GAIN\t\t= (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),\r\n\tBK4819_REG_30_DISABLE_PA_GAIN\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),\r\n\tBK4819_REG_30_ENABLE_MIC_ADC\t\t= (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),\r\n\tBK4819_REG_30_DISABLE_MIC_ADC\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),\r\n\tBK4819_REG_30_ENABLE_TX_DSP\t\t= (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),\r\n\tBK4819_REG_30_DISABLE_TX_DSP\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),\r\n\tBK4819_REG_30_ENABLE_RX_DSP\t\t= (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),\r\n\tBK4819_REG_30_DISABLE_RX_DSP\t\t= (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),\r\n};\r\n\r\n// REG 3F\r\n\r\n#define BK4819_REG_3F_SHIFT_FSK_TX_FINISHED\t\t15\r\n#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY\t14\r\n#define BK4819_REG_3F_SHIFT_FSK_RX_FINISHED\t\t13\r\n#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL\t12\r\n#define BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND\t\t11\r\n#define BK4819_REG_3F_SHIFT_CxCSS_TAIL\t\t\t10\r\n#define BK4819_REG_3F_SHIFT_CDCSS_FOUND\t\t\t9\r\n#define BK4819_REG_3F_SHIFT_CDCSS_LOST\t\t\t8\r\n#define BK4819_REG_3F_SHIFT_CTCSS_FOUND\t\t\t7\r\n#define BK4819_REG_3F_SHIFT_CTCSS_LOST\t\t\t6\r\n#define BK4819_REG_3F_SHIFT_VOX_FOUND\t\t\t5\r\n#define BK4819_REG_3F_SHIFT_VOX_LOST\t\t\t4\r\n#define BK4819_REG_3F_SHIFT_SQUELCH_FOUND\t\t3\r\n#define BK4819_REG_3F_SHIFT_SQUELCH_LOST\t\t2\r\n#define BK4819_REG_3F_SHIFT_FSK_RX_SYNC\t\t\t1\r\n\r\n#define BK4819_REG_3F_MASK_FSK_TX_FINISHED\t\t(1U << BK4819_REG_3F_SHIFT_FSK_TX)\r\n#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_EMPTY\t(1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)\r\n#define BK4819_REG_3F_MASK_FSK_RX_FINISHED\t\t(1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)\r\n#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_FULL\t\t(1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)\r\n#define BK4819_REG_3F_MASK_DTMF_5TONE_FOUND\t\t(1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)\r\n#define BK4819_REG_3F_MASK_CxCSS_TAIL\t\t\t(1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)\r\n#define BK4819_REG_3F_MASK_CDCSS_FOUND\t\t\t(1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)\r\n#define BK4819_REG_3F_MASK_CDCSS_LOST\t\t\t(1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)\r\n#define BK4819_REG_3F_MASK_CTCSS_FOUND\t\t\t(1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)\r\n#define BK4819_REG_3F_MASK_CTCSS_LOST\t\t\t(1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)\r\n#define BK4819_REG_3F_MASK_VOX_FOUND\t\t\t(1U << BK4819_REG_3F_SHIFT_VOX_FOUND)\r\n#define BK4819_REG_3F_MASK_VOX_LOST\t\t\t(1U << BK4819_REG_3F_SHIFT_VOX_LOST)\r\n#define BK4819_REG_3F_MASK_SQUELCH_FOUND\t\t(1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)\r\n#define BK4819_REG_3F_MASK_SQUELCH_LOST\t\t\t(1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)\r\n#define BK4819_REG_3F_MASK_FSK_RX_SYNC\t\t\t(1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)\r\n\r\n#define BK4819_REG_3F_FSK_TX_FINISHED\t\t\t(1U << BK4819_REG_3F_SHIFT_FSK_TX_FINISHED)\r\n#define BK4819_REG_3F_FSK_FIFO_ALMOST_EMPTY\t\t(1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)\r\n#define BK4819_REG_3F_FSK_RX_FINISHED\t\t\t(1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)\r\n#define BK4819_REG_3F_FSK_FIFO_ALMOST_FULL\t\t(1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)\r\n#define BK4819_REG_3F_DTMF_5TONE_FOUND\t\t\t(1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)\r\n#define BK4819_REG_3F_CxCSS_TAIL\t\t\t(1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)\r\n#define BK4819_REG_3F_CDCSS_FOUND\t\t\t(1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)\r\n#define BK4819_REG_3F_CDCSS_LOST\t\t\t(1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)\r\n#define BK4819_REG_3F_CTCSS_FOUND\t\t\t(1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)\r\n#define BK4819_REG_3F_CTCSS_LOST\t\t\t(1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)\r\n#define BK4819_REG_3F_VOX_FOUND\t\t\t\t(1U << BK4819_REG_3F_SHIFT_VOX_FOUND)\r\n#define BK4819_REG_3F_VOX_LOST\t\t\t\t(1U << BK4819_REG_3F_SHIFT_VOX_LOST)\r\n#define BK4819_REG_3F_SQUELCH_FOUND\t\t\t(1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)\r\n#define BK4819_REG_3F_SQUELCH_LOST\t\t\t(1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)\r\n#define BK4819_REG_3F_FSK_RX_SYNC\t\t\t(1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)\r\n\r\n// REG 51\r\n\r\n#define BK4819_REG_51_SHIFT_ENABLE_CxCSS        15\r\n#define BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT    14\r\n#define BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY   13\r\n#define BK4819_REG_51_SHIFT_CxCSS_MODE          12\r\n#define BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH     11\r\n#define BK4819_REG_51_SHIFT_1050HZ_DETECTION    10\r\n#define BK4819_REG_51_SHIFT_AUTO_CDCSS_BW       9\r\n#define BK4819_REG_51_SHIFT_AUTO_CTCSS_BW       8\r\n#define BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1      0\r\n\r\n#define BK4819_REG_51_MASK_ENABLE_CxCSS        (0x01U << BK4819_REG_51_SHIFT_ENABLE_CxCSS)\r\n#define BK4819_REG_51_MASK_GPIO6_PIN2_INPUT    (0x01U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT)\r\n#define BK4819_REG_51_MASK_TX_CDCSS_POLARITY   (0x01U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY)\r\n#define BK4819_REG_51_MASK_CxCSS_MODE          (0x01U << BK4819_REG_51_SHIFT_CxCSS_MODE)\r\n#define BK4819_REG_51_MASK_CDCSS_BIT_WIDTH     (0x01U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH)\r\n#define BK4819_REG_51_MASK_1050HZ_DETECTION    (0x01U << BK4819_REG_51_SHIFT_1050HZ_DETECTION)\r\n#define BK4819_REG_51_MASK_AUTO_CDCSS_BW       (0x01U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW)\r\n#define BK4819_REG_51_MASK_AUTO_CTCSS_BW       (0x01U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW)\r\n#define BK4819_REG_51_MASK_CxCSS_TX_GAIN1      (0x7FU << BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1)\r\n\r\nenum {\r\n\tBK4819_REG_51_ENABLE_CxCSS          = (1U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),\r\n\tBK4819_REG_51_DISABLE_CxCSS         = (0U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),\r\n\r\n\tBK4819_REG_51_GPIO6_PIN2_INPUT      = (1U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),\r\n\tBK4819_REG_51_GPIO6_PIN2_NORMAL     = (0U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),\r\n\r\n\tBK4819_REG_51_TX_CDCSS_NEGATIVE     = (1U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),\r\n\tBK4819_REG_51_TX_CDCSS_POSITIVE     = (0U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),\r\n\r\n\tBK4819_REG_51_MODE_CTCSS            = (1U << BK4819_REG_51_SHIFT_CxCSS_MODE),\r\n\tBK4819_REG_51_MODE_CDCSS            = (0U << BK4819_REG_51_SHIFT_CxCSS_MODE),\r\n\r\n\tBK4819_REG_51_CDCSS_24_BIT          = (1U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),\r\n\tBK4819_REG_51_CDCSS_23_BIT          = (0U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),\r\n\r\n\tBK4819_REG_51_1050HZ_DETECTION      = (1U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),\r\n\tBK4819_REG_51_1050HZ_NO_DETECTION   = (0U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),\r\n\r\n\tBK4819_REG_51_AUTO_CDCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),\r\n\tBK4819_REG_51_AUTO_CDCSS_BW_ENABLE  = (0U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),\r\n\r\n\tBK4819_REG_51_AUTO_CTCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),\r\n\tBK4819_REG_51_AUTO_CTCSS_BW_ENABLE  = (0U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),\r\n};\r\n\r\n// REG 70\r\n\r\n#define BK4819_REG_70_SHIFT_ENABLE_TONE1\t15\r\n#define BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN\t8\r\n#define BK4819_REG_70_SHIFT_ENABLE_TONE2\t7\r\n#define BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN\t0\r\n\r\n#define BK4819_REG_70_MASK_ENABLE_TONE1\t\t(0x01U << BK4819_REG_70_SHIFT_ENABLE_TONE1)\r\n#define BK4819_REG_70_MASK_TONE1_TUNING_GAIN\t(0x7FU << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN)\r\n#define BK4819_REG_70_MASK_ENABLE_TONE2\t\t(0x01U << BK4819_REG_70_SHIFT_ENABLE_TONE2)\r\n#define BK4819_REG_70_MASK_TONE2_TUNING_GAIN\t(0x7FU << BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN)\r\n\r\nenum {\r\n\tBK4819_REG_70_ENABLE_TONE1\t\t= (1U << BK4819_REG_70_SHIFT_ENABLE_TONE1),\r\n\tBK4819_REG_70_ENABLE_TONE2\t\t= (1U << BK4819_REG_70_SHIFT_ENABLE_TONE2),\r\n};\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/bk4819.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include \"app/messenger.h\"\r\n#include \"app/messenger.h\"\r\n#include <stdint.h>\r\n#include \"app/app.h\"\r\n#include \"ui/ui.h\"\r\n#include <stdio.h>\r\n#include \"string.h\"\r\n#include \"settings.h\"\r\n#include \"../audio.h\"\r\n#include \"../bsp/dp32g030/gpio.h\"\r\n#include \"../bsp/dp32g030/portcon.h\"\r\n#include \"bk4819.h\"\r\n#include \"gpio.h\"\r\n#include \"app/messenger.h\"\r\n#include \"system.h\"\r\n#include \"systick.h\"\r\n\r\n#ifdef ENABLE_MDC1200\r\n#include \"app/mdc1200.h\"\r\n#endif\r\n\r\n#include \"misc.h\"\r\n\r\n#ifndef ARRAY_SIZE\r\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r\n#endif\r\nBK4819_FilterBandwidth_t m_bandwidth = BK4819_FILTER_BW_NARROW;\r\n\r\n\r\nstatic const uint8_t DTMF_TONE1_GAIN = 65;\r\nstatic const uint8_t DTMF_TONE2_GAIN = 93;\r\n\r\nstatic uint16_t gBK4819_GpioOutState;\r\n\r\nbool gRxIdleMode;\r\n\r\n__inline uint16_t scale_freq(const uint16_t freq) {\r\n//\treturn (((uint32_t)freq * 1032444u) + 50000u) / 100000u;   // with rounding\r\n    return (((uint32_t) freq * 1353245u) + (1u << 16)) >> 17;   // with rounding\r\n}\r\n\r\nvoid BK4819_Init(void) {\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN);\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_00, 0x8000);\r\n    BK4819_WriteRegister(BK4819_REG_00, 0x0000);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_37, 0x1D0F);\r\n    BK4819_WriteRegister(BK4819_REG_36, 0x0022);\r\n\r\n    BK4819_InitAGC(false);\r\n    BK4819_SetAGC(true);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_19, 0b0001000001000001);   // <15> MIC AGC  1 = disable  0 = enable\r\n\r\n    BK4819_WriteRegister(BK4819_REG_7D, 0xE940);\r\n\r\n    // REG_48 .. RX AF level\r\n    //\r\n    // <15:12> 11  ???  0 to 15\r\n    //\r\n    // <11:10> 0 AF Rx Gain-1\r\n    //         0 =   0dB\r\n    //         1 =  -6dB\r\n    //         2 = -12dB\r\n    //         3 = -18dB\r\n    //\r\n    // <9:4>   60 AF Rx Gain-2  -26dB ~ 5.5dB   0.5dB/step\r\n    //         63 = max\r\n    //          0 = mute\r\n    //\r\n    // <3:0>   15 AF DAC Gain (after Gain-1 and Gain-2) approx 2dB/step\r\n    //         15 = max\r\n    //          0 = min\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_48,    //  0xB3A8);     // 1011 00 111010 1000\r\n                         (11u << 12) |     // ??? 0..15\r\n                         (0u << 10) |     // AF Rx Gain-1\r\n                         (58u << 4) |     // AF Rx Gain-2\r\n                         (8u << 0));     // AF DAC Gain (after Gain-1 and Gain-2)\r\n\r\n#if 1\r\n    const uint8_t dtmf_coeffs[] = {111, 107, 103, 98, 80, 71, 58, 44, 65, 55, 37, 23, 228, 203, 181, 159};\r\n    for (unsigned int i = 0; i < ARRAY_SIZE(dtmf_coeffs); i++)\r\n        BK4819_WriteRegister(BK4819_REG_09, (i << 12) | dtmf_coeffs[i]);\r\n#else\r\n    // original code\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x006F);  // 6F\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x106B);  // 6B\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x2067);  // 67\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x3062);  // 62\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x4050);  // 50\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x5047);  // 47\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x603A);  // 3A\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x702C);  // 2C\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x8041);  // 41\r\n    BK4819_WriteRegister(BK4819_REG_09, 0x9037);  // 37\r\n    BK4819_WriteRegister(BK4819_REG_09, 0xA025);  // 25\r\n    BK4819_WriteRegister(BK4819_REG_09, 0xB017);  // 17\r\n    BK4819_WriteRegister(BK4819_REG_09, 0xC0E4);  // E4\r\n    BK4819_WriteRegister(BK4819_REG_09, 0xD0CB);  // CB\r\n    BK4819_WriteRegister(BK4819_REG_09, 0xE0B5);  // B5\r\n    BK4819_WriteRegister(BK4819_REG_09, 0xF09F);  // 9F\r\n#endif\r\n\r\n    BK4819_WriteRegister(BK4819_REG_1F, 0x5454);\r\n    BK4819_WriteRegister(BK4819_REG_3E, 0xA037);\r\n\r\n    gBK4819_GpioOutState = 0x9000;\r\n\r\n    BK4819_WriteRegister(BK4819_REG_33, 0x9000);\r\n    BK4819_WriteRegister(BK4819_REG_3F, 0);\r\n}\r\n\r\nstatic uint16_t BK4819_ReadU16(void) {\r\n    unsigned int i;\r\n    uint16_t Value;\r\n\r\n    PORTCON_PORTC_IE = (PORTCON_PORTC_IE & ~PORTCON_PORTC_IE_C2_MASK) | PORTCON_PORTC_IE_C2_BITS_ENABLE;\r\n    GPIOC->DIR = (GPIOC->DIR & ~GPIO_DIR_2_MASK) | GPIO_DIR_2_BITS_INPUT;\r\n    //SYSTICK_DelayUs(1);\r\n    SYSTICK_Delay250ns(1);\r\n    Value = 0;\r\n    for (i = 0; i < 16; i++) {\r\n        Value <<= 1;\r\n        Value |= GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA);\r\n        GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n        SYSTICK_Delay250ns(1);\r\n        GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n        SYSTICK_Delay250ns(1);\r\n    }\r\n    PORTCON_PORTC_IE = (PORTCON_PORTC_IE & ~PORTCON_PORTC_IE_C2_MASK) | PORTCON_PORTC_IE_C2_BITS_DISABLE;\r\n    GPIOC->DIR = (GPIOC->DIR & ~GPIO_DIR_2_MASK) | GPIO_DIR_2_BITS_OUTPUT;\r\n\r\n    return Value;\r\n}\r\n\r\nuint16_t BK4819_ReadRegister(BK4819_REGISTER_t Register) {\r\n    uint16_t Value;\r\n\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN);\r\n    GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n\r\n    SYSTICK_Delay250ns(1);\r\n\r\n    GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN);\r\n    BK4819_WriteU8(Register | 0x80);\r\n    Value = BK4819_ReadU16();\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN);\r\n\r\n    SYSTICK_Delay250ns(1);\r\n\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA);\r\n\r\n    return Value;\r\n\r\n}\r\n\r\nvoid BK4819_WriteRegister(BK4819_REGISTER_t Register, uint16_t Data) {\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN);\r\n    GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n\r\n    SYSTICK_Delay250ns(1);\r\n\r\n    GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN);\r\n    BK4819_WriteU8(Register);\r\n\r\n    //SYSTICK_Delay250ns(1);\r\n\r\n    BK4819_WriteU16(Data);\r\n\r\n    //SYSTICK_Delay250ns(1);\r\n\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCN);\r\n\r\n    SYSTICK_Delay250ns(1);\r\n\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n    GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA);\r\n}\r\n\r\nvoid BK4819_WriteU8(uint8_t Data) {\r\n    unsigned int i;\r\n\r\n    GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n    for (i = 0; i < 8; i++) {\r\n        if ((Data & 0x80) == 0)\r\n            GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA);\r\n        else\r\n            GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA);\r\n\r\n        SYSTICK_Delay250ns(1);\r\n        GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n        SYSTICK_Delay250ns(1);\r\n\r\n        Data <<= 1;\r\n\r\n        GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n        SYSTICK_Delay250ns(1);\r\n    }\r\n}\r\n\r\nvoid BK4819_WriteU16(uint16_t Data) {\r\n    unsigned int i;\r\n\r\n    GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n    for (i = 0; i < 16; i++) {\r\n        if ((Data & 0x8000) == 0)\r\n            GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA);\r\n        else\r\n            GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SDA);\r\n\r\n        SYSTICK_Delay250ns(1);\r\n        GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n\r\n        Data <<= 1;\r\n\r\n        SYSTICK_Delay250ns(1);\r\n        GPIO_ClearBit(&GPIOC->DATA, GPIOC_PIN_BK4819_SCL);\r\n        SYSTICK_Delay250ns(1);\r\n    }\r\n}\r\n\r\nvoid BK4819_SetAGC(bool enable) {\r\n    uint16_t regVal = BK4819_ReadRegister(BK4819_REG_7E);\r\n    if (!(regVal & (1 << 15)) == enable)\r\n        return;\r\n\r\n    BK4819_WriteRegister(BK4819_REG_7E, (regVal & ~(1 << 15) & ~(0b111 << 12))\r\n                                        | (!enable << 15)   // 0  AGC fix mode\r\n                                        | (3u << 12)       // 3  AGC fix index\r\n    );\r\n\r\n    // if(enable) {\r\n    // \tBK4819_WriteRegister(BK4819_REG_7B, 0x8420);\r\n    // }\r\n    // else {\r\n    // \tBK4819_WriteRegister(BK4819_REG_7B, 0x318C);\r\n\r\n    // \tBK4819_WriteRegister(BK4819_REG_7C, 0x595E);\r\n    // \tBK4819_WriteRegister(BK4819_REG_20, 0x8DEF);\r\n\r\n    // \tfor (uint8_t i = 0; i < 8; i++) {\r\n    // \t\t//BK4819_WriteRegister(BK4819_REG_06, ((i << 13) | 0x2500u) + 0x036u);\r\n    // \t\tBK4819_WriteRegister(BK4819_REG_06, (i & 7) << 13 | 0x4A << 7 | 0x36);\r\n    // \t}\r\n    // }\r\n}\r\n\r\nvoid BK4819_InitAGC(bool amModulation) {\r\n    // REG_10, REG_11, REG_12 REG_13, REG_14\r\n    //\r\n    // Rx AGC Gain Table[]. (Index Max->Min is 3,2,1,0,-1)\r\n    //\r\n    // <15:10> ???\r\n    //\r\n    // <9:8>   LNA Gain Short\r\n    //         3 =   0dB  <<<\t\t1o11\t\t\t\tread from spectrum\t\t\treference manual\r\n    //         2 = \t\t\t\t\t-24dB  \t\t\t\t-19     \t\t\t\t\t -11\r\n    //         1 = \t\t\t\t\t-30dB  \t\t\t\t-24     \t\t\t\t\t -16\r\n    //         0 = \t\t\t\t\t-33dB  \t\t\t\t-28     \t\t\t\t\t -19\r\n    //\r\n    // <7:5>   LNA Gain\r\n    //         7 =   0dB\r\n    //         6 =  -2dB\r\n    //         5 =  -4dB\r\n    //         4 =  -6dB\r\n    //         3 =  -9dB\r\n    //         2 = -14dB <<<\r\n    //         1 = -19dB\r\n    //         0 = -24dB\r\n    //\r\n    // <4:3>   MIXER Gain\r\n    //         3 =   0dB <<<\r\n    //         2 =  -3dB\r\n    //         1 =  -6dB\r\n    //         0 =  -8dB\r\n    //\r\n    // <2:0>   PGA Gain\r\n    //         7 =   0dB\r\n    //         6 =  -3dB <<<\r\n    //         5 =  -6dB\r\n    //         4 =  -9dB\r\n    //         3 = -15dB\r\n    //         2 = -21dB\r\n    //         1 = -27dB\r\n    //         0 = -33dB\r\n    //\r\n\r\n    BK4819_WriteRegister(BK4819_REG_13, 0x03BE);  // 0x03BE / 000000 11 101 11 110 /  -7dB\r\n    BK4819_WriteRegister(BK4819_REG_12, 0x037B);  // 0x037B / 000000 11 011 11 011 / -24dB\r\n    BK4819_WriteRegister(BK4819_REG_11, 0x027B);  // 0x027B / 000000 10 011 11 011 / -43dB\r\n    BK4819_WriteRegister(BK4819_REG_10, 0x007A);  // 0x007A / 000000 00 011 11 010 / -58dB\r\n\r\n    if (amModulation) {\r\n        BK4819_WriteRegister(BK4819_REG_14, 0x0000);\r\n        BK4819_WriteRegister(BK4819_REG_49, (0 << 14) | (50 << 7) | (32 << 0));\r\n    } else {\r\n        BK4819_WriteRegister(BK4819_REG_14, 0x0019);  // 0x0019 / 000000 00 000 11 001 / -79dB\r\n        BK4819_WriteRegister(BK4819_REG_49, (0 << 14) | (84 << 7) | (56 << 0)); //0x2A38 / 00 1010100 0111000 / 84, 56\r\n    }\r\n    BK4819_WriteRegister(BK4819_REG_7B, 0x8420);\r\n\r\n}\r\n\r\n\r\nvoid BK4819_PlayRoger(void) {\r\n#ifdef ENABLE_MESSENGER\r\n    if(stop_mdc_flag) return;\r\n#endif\r\n    if (gEeprom.ROGER == ROGER_MODE_ROGER || gEeprom.ROGER == ROGER_MODE_MDC_HEAD_ROGER)\r\n        BK4819_PlayRogerNormal();\r\n#ifdef ENABLE_MDC1200\r\n    else\r\n    if ((gEeprom.ROGER == ROGER_MODE_MDC_END||gEeprom.ROGER==ROGER_MODE_MDC_BOTH)\r\n\r\n\r\n    ) {\r\n\r\n        BK4819_send_MDC1200(MDC1200_OP_CODE_POST_ID, 0x00, gEeprom.MDC1200_ID, false);\r\n\r\n#ifdef ENABLE_MDC1200_SIDE_BEEP\r\n        BK4819_start_tone(880, 10, true, true);\r\n            SYSTEM_DelayMs(120);\r\n            BK4819_stop_tones(true);\r\n#endif\r\n    }\r\n#endif\r\n}\r\n\r\nint8_t BK4819_GetRxGain_dB(void) {\r\n    union {\r\n        struct {\r\n            uint16_t pga: 3;\r\n            uint16_t mixer: 2;\r\n            uint16_t lna: 3;\r\n            uint16_t lnaS: 2;\r\n        };\r\n        uint16_t __raw;\r\n    } agcGainReg;\r\n\r\n    union {\r\n        struct {\r\n            uint16_t _: 5;\r\n            uint16_t agcSigStrength: 7;\r\n            int16_t gainIdx: 3;\r\n            uint16_t agcEnab: 1;\r\n        };\r\n        uint16_t __raw;\r\n    } reg7e;\r\n\r\n    reg7e.__raw = BK4819_ReadRegister(BK4819_REG_7E);\r\n    uint8_t gainAddr = reg7e.gainIdx < 0 ? BK4819_REG_14 : BK4819_REG_10 + reg7e.gainIdx;\r\n    agcGainReg.__raw = BK4819_ReadRegister(gainAddr);\r\n    int8_t lnaShortTab[] = {-28, -24, -19, 0};\r\n    int8_t lnaTab[] = {-24, -19, -14, -9, -6, -4, -2, 0};\r\n    int8_t mixerTab[] = {-8, -6, -3, 0};\r\n    int8_t pgaTab[] = {-33, -27, -21, -15, -9, -6, -3, 0};\r\n    return lnaShortTab[agcGainReg.lnaS] + lnaTab[agcGainReg.lna] + mixerTab[agcGainReg.mixer] + pgaTab[agcGainReg.pga];\r\n}\r\n\r\nint16_t BK4819_GetRSSI_dBm(void) {\r\n    uint16_t rssi = BK4819_GetRSSI();\r\n    return (rssi / 2) - 160;// - BK4819_GetRxGain_dB();\r\n}\r\n\r\nvoid BK4819_ToggleGpioOut(BK4819_GPIO_PIN_t Pin, bool bSet) {\r\n    if (bSet)\r\n        gBK4819_GpioOutState |= (0x40u >> Pin);\r\n    else\r\n        gBK4819_GpioOutState &= ~(0x40u >> Pin);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_33, gBK4819_GpioOutState);\r\n}\r\n\r\nvoid BK4819_SetCDCSSCodeWord(uint32_t CodeWord) {\r\n    // REG_51\r\n    //\r\n    // <15>  0\r\n    //       1 = Enable TxCTCSS/CDCSS\r\n    //       0 = Disable\r\n    //\r\n    // <14>  0\r\n    //       1 = GPIO0Input for CDCSS\r\n    //       0 = Normal Mode (for BK4819 v3)\r\n    //\r\n    // <13>  0\r\n    //       1 = Transmit negative CDCSS code\r\n    //       0 = Transmit positive CDCSS code\r\n    //\r\n    // <12>  0 CTCSS/CDCSS mode selection\r\n    //       1 = CTCSS\r\n    //       0 = CDCSS\r\n    //\r\n    // <11>  0 CDCSS 24/23bit selection\r\n    //       1 = 24bit\r\n    //       0 = 23bit\r\n    //\r\n    // <10>  0 1050HzDetectionMode\r\n    //       1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz\r\n    //\r\n    // <9>   0 Auto CDCSS Bw Mode\r\n    //       1 = Disable\r\n    //       0 = Enable\r\n    //\r\n    // <8>   0 Auto CTCSS Bw Mode\r\n    //       0 = Enable\r\n    //       1 = Disable\r\n    //\r\n    // <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning\r\n    //       0   = min\r\n    //       127 = max\r\n\r\n    // Enable CDCSS\r\n    // Transmit positive CDCSS code\r\n    // CDCSS Mode\r\n    // CDCSS 23bit\r\n    // Enable Auto CDCSS Bw Mode\r\n    // Enable Auto CTCSS Bw Mode\r\n    // CTCSS/CDCSS Tx Gain1 Tuning = 51\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_51,\r\n                         BK4819_REG_51_ENABLE_CxCSS |\r\n                         BK4819_REG_51_GPIO6_PIN2_NORMAL |\r\n                         BK4819_REG_51_TX_CDCSS_POSITIVE |\r\n                         BK4819_REG_51_MODE_CDCSS |\r\n                         BK4819_REG_51_CDCSS_23_BIT |\r\n                         BK4819_REG_51_1050HZ_NO_DETECTION |\r\n                         BK4819_REG_51_AUTO_CDCSS_BW_ENABLE |\r\n                         BK4819_REG_51_AUTO_CTCSS_BW_ENABLE |\r\n                         (51u << BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1));\r\n\r\n    // REG_07 <15:0>\r\n    //\r\n    // When <13> = 0 for CTC1\r\n    // <12:0> = CTC1 frequency control word =\r\n    //                          freq(Hz) * 20.64888 for XTAL 13M/26M or\r\n    //                          freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    // When <13> = 1 for CTC2 (Tail 55Hz Rx detection)\r\n    // <12:0> = CTC2 (should below 100Hz) frequency control word =\r\n    //                          25391 / freq(Hz) for XTAL 13M/26M or\r\n    //                          25000 / freq(Hz) for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    // When <13> = 2 for CDCSS 134.4Hz\r\n    // <12:0> = CDCSS baud rate frequency (134.4Hz) control word =\r\n    //                          freq(Hz) * 20.64888 for XTAL 13M/26M or\r\n    //                          freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_07, BK4819_REG_07_MODE_CTC1 | 2775u);\r\n\r\n    // REG_08 <15:0> <15> = 1 for CDCSS high 12bit\r\n    //               <15> = 0 for CDCSS low  12bit\r\n    // <11:0> = CDCSShigh/low 12bit code\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_08, (0u << 15) | ((CodeWord >> 0) & 0x0FFF)); // LS 12-bits\r\n    BK4819_WriteRegister(BK4819_REG_08, (1u << 15) | ((CodeWord >> 12) & 0x0FFF)); // MS 12-bits\r\n}\r\n\r\nvoid BK4819_SetCTCSSFrequency(uint32_t FreqControlWord) {\r\n    // REG_51 <15>  0                                 1 = Enable TxCTCSS/CDCSS           0 = Disable\r\n    // REG_51 <14>  0                                 1 = GPIO0Input for CDCSS           0 = Normal Mode.(for BK4819v3)\r\n    // REG_51 <13>  0                                 1 = Transmit negative CDCSS code   0 = Transmit positive CDCSScode\r\n    // REG_51 <12>  0 CTCSS/CDCSS mode selection      1 = CTCSS                          0 = CDCSS\r\n    // REG_51 <11>  0 CDCSS 24/23bit selection        1 = 24bit                          0 = 23bit\r\n    // REG_51 <10>  0 1050HzDetectionMode             1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz\r\n    // REG_51 <9>   0 Auto CDCSS Bw Mode              1 = Disable                        0 = Enable.\r\n    // REG_51 <8>   0 Auto CTCSS Bw Mode              0 = Enable                         1 = Disable\r\n    // REG_51 <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning     0 = min                            127 = max\r\n\r\n    uint16_t Config;\r\n    if (FreqControlWord == 2625) {    // Enables 1050Hz detection mode\r\n        // Enable TxCTCSS\r\n        // CTCSS Mode\r\n        // 1050/4 Detect Enable\r\n        // Enable Auto CDCSS Bw Mode\r\n        // Enable Auto CTCSS Bw Mode\r\n        // CTCSS/CDCSS Tx Gain1 Tuning = 74\r\n        //\r\n        Config = 0x944A;   // 1 0 0 1 0 1 0 0 0 1001010\r\n    } else {    // Enable TxCTCSS\r\n        // CTCSS Mode\r\n        // Enable Auto CDCSS Bw Mode\r\n        // Enable Auto CTCSS Bw Mode\r\n        // CTCSS/CDCSS Tx Gain1 Tuning = 74\r\n        //亚音\r\n//        Config = 0x904A;   // 1 0 0 1 0 0 0 0 0 1001010\r\n        Config = 0x9033;\r\n    }\r\n    BK4819_WriteRegister(BK4819_REG_51, Config);\r\n\r\n    // REG_07 <15:0>\r\n    //\r\n    // When <13> = 0 for CTC1\r\n    // <12:0> = CTC1 frequency control word =\r\n    //                          freq(Hz) * 20.64888 for XTAL 13M/26M or\r\n    //                          freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    // When <13> = 1 for CTC2 (Tail RX detection)\r\n    // <12:0> = CTC2 (should below 100Hz) frequency control word =\r\n    //                          25391 / freq(Hz) for XTAL 13M/26M or\r\n    //                          25000 / freq(Hz) for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    // When <13> = 2 for CDCSS 134.4Hz\r\n    // <12:0> = CDCSS baud rate frequency (134.4Hz) control word =\r\n    //                          freq(Hz) * 20.64888 for XTAL 13M/26M or\r\n    //                          freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_07, BK4819_REG_07_MODE_CTC1 |\r\n                                        (((FreqControlWord * 206488u) + 50000u) / 100000u));   // with rounding\r\n}\r\n\r\n// freq_10Hz is CTCSS Hz * 10\r\nvoid BK4819_SetTailDetection(const uint32_t freq_10Hz) {\r\n    // REG_07 <15:0>\r\n    //\r\n    // When <13> = 0 for CTC1\r\n    // <12:0> = CTC1 frequency control word =\r\n    //                          freq(Hz) * 20.64888 for XTAL 13M/26M or\r\n    //                          freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    // When <13> = 1 for CTC2 (Tail RX detection)\r\n    // <12:0> = CTC2 (should below 100Hz) frequency control word =\r\n    //                          25391 / freq(Hz) for XTAL 13M/26M or\r\n    //                          25000 / freq(Hz) for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    // When <13> = 2 for CDCSS 134.4Hz\r\n    // <12:0> = CDCSS baud rate frequency (134.4Hz) control word =\r\n    //                          freq(Hz) * 20.64888 for XTAL 13M/26M or\r\n    //                          freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_07,\r\n                         BK4819_REG_07_MODE_CTC2 | ((253910 + (freq_10Hz / 2)) / freq_10Hz));  // with rounding\r\n}\r\n\r\nvoid BK4819_EnableVox(uint16_t VoxEnableThreshold, uint16_t VoxDisableThreshold) {\r\n    //VOX Algorithm\r\n    //if (voxamp>VoxEnableThreshold)                VOX = 1;\r\n    //else\r\n    //if (voxamp<VoxDisableThreshold) (After Delay) VOX = 0;\r\n\r\n    const uint16_t REG_31_Value = BK4819_ReadRegister(BK4819_REG_31);\r\n\r\n    // 0xA000 is undocumented?\r\n    BK4819_WriteRegister(BK4819_REG_46, 0xA000 | (VoxEnableThreshold & 0x07FF));\r\n\r\n    // 0x1800 is undocumented?\r\n    BK4819_WriteRegister(BK4819_REG_79, 0x1800 | (VoxDisableThreshold & 0x07FF));\r\n\r\n    // Bottom 12 bits are undocumented, 15:12 vox disable delay *128ms\r\n    BK4819_WriteRegister(BK4819_REG_7A, 0x289A); // vox disable delay = 128*5 = 640ms\r\n\r\n    // Enable VOX\r\n    BK4819_WriteRegister(BK4819_REG_31, REG_31_Value | (1u << 2));    // VOX Enable\r\n}\r\n\r\nvoid BK4819_SetFilterBandwidth(const BK4819_FilterBandwidth_t Bandwidth, const bool weak_no_different) {\r\n    // REG_43\r\n    // <15>    0 ???\r\n    //\r\n    // <14:12> 4 RF filter bandwidth\r\n    //         0 = 1.7  kHz\r\n    //         1 = 2.0  kHz\r\n    //         2 = 2.5  kHz\r\n    //         3 = 3.0  kHz\r\n    //         4 = 3.75 kHz\r\n    //         5 = 4.0  kHz\r\n    //         6 = 4.25 kHz\r\n    //         7 = 4.5  kHz\r\n    // if <5> == 1, RF filter bandwidth * 2\r\n    //\r\n    // <11:9>  0 RF filter bandwidth when signal is weak\r\n    //         0 = 1.7  kHz\r\n    //         1 = 2.0  kHz\r\n    //         2 = 2.5  kHz\r\n    //         3 = 3.0  kHz\r\n    //         4 = 3.75 kHz\r\n    //         5 = 4.0  kHz\r\n    //         6 = 4.25 kHz\r\n    //         7 = 4.5  kHz\r\n    // if <5> == 1, RF filter bandwidth * 2\r\n    //\r\n    // <8:6>   1 AFTxLPF2 filter Band Width\r\n    //         1 = 2.5  kHz (for 12.5k channel space)\r\n    //         2 = 2.75 kHz\r\n    //         0 = 3.0  kHz (for 25k   channel space)\r\n    //         3 = 3.5  kHz\r\n    //         4 = 4.5  kHz\r\n    //         5 = 4.25 kHz\r\n    //         6 = 4.0  kHz\r\n    //         7 = 3.75 kHz\r\n    //\r\n    // <5:4>   0 BW Mode Selection\r\n    //         0 = 12.5k\r\n    //         1 =  6.25k\r\n    //         2 = 25k/20k\r\n    //\r\n    // <3>     1 ???\r\n    //\r\n    // <2>     0 Gain after FM Demodulation\r\n    //         0 = 0dB\r\n    //         1 = 6dB\r\n    //\r\n    // <1:0>   0 ???\r\n\r\n    uint16_t val;\r\n    m_bandwidth = Bandwidth;\r\n\r\n    switch (Bandwidth) {\r\n        default:\r\n        case BK4819_FILTER_BW_WIDE:    // 25kHz\r\n            if (weak_no_different) {    // make the RX bandwidth the same with weak signals\r\n                val =\r\n                        (0u << 15) |     //  0\r\n                        (4u << 12) |     // *3 RF filter bandwidth\r\n                        (4u << 9) |     // *0 RF filter bandwidth when signal is weak\r\n                        (6u << 6) |     // *0 AFTxLPF2 filter Band Width\r\n                        (2u << 4) |     //  2 BW Mode Selection\r\n                        (1u << 3) |     //  1\r\n                        (0u << 2) |     //  0 Gain after FM Demodulation\r\n                        (0u << 0);      //  0\r\n            } else {    // with weak RX signals the RX bandwidth is reduced\r\n                val =                // 0x3028);         // 0 011 000 000 10 1 0 00\r\n                        (0u << 15) |     //  0\r\n                        (4u << 12) |     // *3 RF filter bandwidth\r\n                        (2u << 9) |     // *0 RF filter bandwidth when signal is weak\r\n                        (6u << 6) |     // *0 AFTxLPF2 filter Band Width\r\n                        (2u << 4) |     //  2 BW Mode Selection\r\n                        (1u << 3) |     //  1\r\n                        (0u << 2) |     //  0 Gain after FM Demodulation\r\n                        (0u << 0);      //  0\r\n            }\r\n            break;\r\n\r\n        case BK4819_FILTER_BW_NARROW:    // 12.5kHz\r\n            if (weak_no_different) {\r\n                val =\r\n                        (0u << 15) |     //  0\r\n                        (4u << 12) |     // *4 RF filter bandwidth\r\n                        (4u << 9) |     // *0 RF filter bandwidth when signal is weak\r\n                        (0u << 6) |     // *1 AFTxLPF2 filter Band Width\r\n                        (0u << 4) |     //  0 BW Mode Selection\r\n                        (1u << 3) |     //  1\r\n                        (0u << 2) |     //  0 Gain after FM Demodulation\r\n                        (0u << 0);      //  0\r\n            } else {\r\n                val =                // 0x4048);        // 0 100 000 001 00 1 0 00\r\n                        (0u << 15) |     //  0\r\n                        (4u << 12) |     // *4 RF filter bandwidth\r\n                        (2u << 9) |     // *0 RF filter bandwidth when signal is weak\r\n                        (0u << 6) |     // *1 AFTxLPF2 filter Band Width\r\n                        (0u << 4) |     //  0 BW Mode Selection\r\n                        (1u << 3) |     //  1\r\n                        (0u << 2) |     //  0 Gain after FM Demodulation\r\n                        (0u << 0);      //  0\r\n            }\r\n            break;\r\n\r\n        case BK4819_FILTER_BW_NARROWER:    // 6.25kHz\r\n            if (weak_no_different) {\r\n                val =\r\n                        (0u << 15) |     //  0\r\n                        (3u << 12) |     //  3 RF filter bandwidth\r\n                        (3u << 9) |     // *0 RF filter bandwidth when signal is weak\r\n                        (1u << 6) |     //  1 AFTxLPF2 filter Band Width\r\n                        (1u << 4) |     //  1 BW Mode Selection\r\n                        (1u << 3) |     //  1\r\n                        (0u << 2) |     //  0 Gain after FM Demodulation\r\n                        (0u << 0);      //  0\r\n            } else {\r\n                val =\r\n                        (0u << 15) |     //  0\r\n                        (3u << 12) |     //  3 RF filter bandwidth\r\n                        (0u << 9) |     //  0 RF filter bandwidth when signal is weak\r\n                        (1u << 6) |     //  1 AFTxLPF2 filter Band Width\r\n                        (1u << 4) |     //  1 BW Mode Selection\r\n                        (1u << 3) |     //  1\r\n                        (0u << 2) |     //  1 Gain after FM Demodulation\r\n                        (0u << 0);      //  0\r\n            }\r\n            break;\r\n    }\r\n\r\n    BK4819_WriteRegister(BK4819_REG_43, val);\r\n}\r\n\r\nvoid BK4819_SetupPowerAmplifier(const uint8_t bias, const uint32_t frequency) {\r\n    // REG_36 <15:8> 0 PA Bias output 0 ~ 3.2V\r\n    //               255 = 3.2V\r\n    //                 0 = 0V\r\n    //\r\n    // REG_36 <7>    0\r\n    //               1 = Enable PA-CTL output\r\n    //               0 = Disable (Output 0 V)\r\n    //\r\n    // REG_36 <5:3>  7 PA gain 1 tuning\r\n    //               7 = max\r\n    //               0 = min\r\n    //\r\n    // REG_36 <2:0>  7 PA gain 2 tuning\r\n    //               7 = max\r\n    //               0 = min\r\n    //\r\n    //                                  280MHz       gain 1 = 1  gain 2 = 0  gain 1 = 4  gain 2 = 2\r\n    const uint8_t gain = (frequency < 28000000) ? (1u << 3) | (0u << 0) : (4u << 3) | (2u << 0);\r\n    const uint8_t enable = 1;\r\n    BK4819_WriteRegister(BK4819_REG_36, (bias << 8) | (enable << 7) | (gain << 0));\r\n}\r\n\r\nvoid BK4819_SetFrequency(uint32_t Frequency) {\r\n    BK4819_WriteRegister(BK4819_REG_38, (Frequency >> 0) & 0xFFFF);\r\n    BK4819_WriteRegister(BK4819_REG_39, (Frequency >> 16) & 0xFFFF);\r\n}\r\n\r\nvoid BK4819_SetupSquelch(\r\n        uint8_t SquelchOpenRSSIThresh,\r\n        uint8_t SquelchCloseRSSIThresh,\r\n        uint8_t SquelchOpenNoiseThresh,\r\n        uint8_t SquelchCloseNoiseThresh,\r\n        uint8_t SquelchCloseGlitchThresh,\r\n        uint8_t SquelchOpenGlitchThresh) {\r\n    // REG_70\r\n    //\r\n    // <15>   0 Enable TONE1\r\n    //        1 = Enable\r\n    //        0 = Disable\r\n    //\r\n    // <14:8> 0 TONE1 tuning gain\r\n    //        0 ~ 127\r\n    //\r\n    // <7>    0 Enable TONE2\r\n    //        1 = Enable\r\n    //        0 = Disable\r\n    //\r\n    // <6:0>  0 TONE2/FSK tuning gain\r\n    //        0 ~ 127\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_70, 0);\r\n\r\n    // Glitch threshold for Squelch = close\r\n    //\r\n    // 0 ~ 255\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_4D, 0xA000 | SquelchCloseGlitchThresh);\r\n\r\n    // REG_4E\r\n    //\r\n    // <15:14> 1 ???\r\n    //\r\n    // <13:11> 5 Squelch = open  Delay Setting\r\n    //         0 ~ 7\r\n    //\r\n    // <10:9>  7 Squelch = close Delay Setting\r\n    //         0 ~ 3\r\n    //\r\n    // <8>     0 ???\r\n    //\r\n    // <7:0>   8 Glitch threshold for Squelch = open\r\n    //         0 ~ 255\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_4E,  // 01 101 11 1 00000000\r\n\r\n            // original (*)\r\n                         (1u << 14) |                  //  1 ???\r\n                         (5u << 11) |                  // *5  squelch = open  delay .. 0 ~ 7\r\n                         (6u << 9) |                  // *3  squelch = close delay .. 0 ~ 3\r\n                         SquelchOpenGlitchThresh);     //  0 ~ 255\r\n\r\n\r\n    // REG_4F\r\n    //\r\n    // <14:8> 47 Ex-noise threshold for Squelch = close\r\n    //        0 ~ 127\r\n    //\r\n    // <7>    ???\r\n    //\r\n    // <6:0>  46 Ex-noise threshold for Squelch = open\r\n    //        0 ~ 127\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_4F, ((uint16_t) SquelchCloseNoiseThresh << 8) | SquelchOpenNoiseThresh);\r\n\r\n    // REG_78\r\n    //\r\n    // <15:8> 72 RSSI threshold for Squelch = open    0.5dB/step\r\n    //\r\n    // <7:0>  70 RSSI threshold for Squelch = close   0.5dB/step\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_78, ((uint16_t) SquelchOpenRSSIThresh << 8) | SquelchCloseRSSIThresh);\r\n\r\n    BK4819_SetAF(BK4819_AF_MUTE);\r\n\r\n    BK4819_RX_TurnOn();\r\n}\r\n\r\nvoid BK4819_SetAF(BK4819_AF_Type_t AF) {\r\n    // AF Output Inverse Mode = Inverse\r\n    // Undocumented bits 0x2040\r\n    //\r\n//\tBK4819_WriteRegister(BK4819_REG_47, 0x6040 | (AF << 8));\r\n    BK4819_WriteRegister(BK4819_REG_47, (6u << 12) | (AF << 8) | (1u << 6));\r\n}\r\n\r\nvoid BK4819_SetRegValue(RegisterSpec s, uint16_t v) {\r\n    uint16_t reg = BK4819_ReadRegister(s.num);\r\n    reg &= ~(s.mask << s.offset);\r\n    BK4819_WriteRegister(s.num, reg | (v << s.offset));\r\n}\r\n\r\nvoid BK4819_RX_TurnOn(void) {\r\n    // DSP Voltage Setting = 1\r\n    // ANA LDO = 2.7v\r\n    // VCO LDO = 2.7v\r\n    // RF LDO  = 2.7v\r\n    // PLL LDO = 2.7v\r\n    // ANA LDO bypass\r\n    // VCO LDO bypass\r\n    // RF LDO  bypass\r\n    // PLL LDO bypass\r\n    // Reserved bit is 1 instead of 0\r\n    // Enable  DSP\r\n    // Enable  XTAL\r\n    // Enable  Band Gap\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_37, 0x1F0F);  // 0001111100001111\r\n\r\n    // Turn off everything\r\n    BK4819_WriteRegister(BK4819_REG_30, 0);\r\n\r\n\r\n    BK4819_WriteRegister(BK4819_REG_30,\r\n                         BK4819_REG_30_ENABLE_VCO_CALIB |\r\n                         BK4819_REG_30_DISABLE_UNKNOWN |\r\n                         BK4819_REG_30_ENABLE_RX_LINK |\r\n                         BK4819_REG_30_ENABLE_AF_DAC |\r\n                         BK4819_REG_30_ENABLE_DISC_MODE |\r\n                         BK4819_REG_30_ENABLE_PLL_VCO |\r\n                         BK4819_REG_30_DISABLE_PA_GAIN |\r\n                         BK4819_REG_30_DISABLE_MIC_ADC |\r\n                         BK4819_REG_30_DISABLE_TX_DSP |\r\n                         BK4819_REG_30_ENABLE_RX_DSP);\r\n}\r\n\r\nvoid BK4819_PickRXFilterPathBasedOnFrequency(uint32_t Frequency) {\r\n    if (Frequency < 28000000) {    // VHF\r\n        BK4819_ToggleGpioOut(BK4819_GPIO4_PIN32_VHF_LNA, true);\r\n        BK4819_ToggleGpioOut(BK4819_GPIO3_PIN31_UHF_LNA, false);\r\n    } else if (Frequency == 0xFFFFFFFF) {    // OFF\r\n        BK4819_ToggleGpioOut(BK4819_GPIO4_PIN32_VHF_LNA, false);\r\n        BK4819_ToggleGpioOut(BK4819_GPIO3_PIN31_UHF_LNA, false);\r\n    } else {    // UHF\r\n        BK4819_ToggleGpioOut(BK4819_GPIO4_PIN32_VHF_LNA, false);\r\n        BK4819_ToggleGpioOut(BK4819_GPIO3_PIN31_UHF_LNA, true);\r\n    }\r\n}\r\n\r\nvoid BK4819_DisableScramble(void) {\r\n    const uint16_t Value = BK4819_ReadRegister(BK4819_REG_31);\r\n    BK4819_WriteRegister(BK4819_REG_31, Value & ~(1u << 1));\r\n}\r\n\r\nvoid BK4819_EnableScramble(uint8_t Type) {\r\n    const uint16_t Value = BK4819_ReadRegister(BK4819_REG_31);\r\n    BK4819_WriteRegister(BK4819_REG_31, Value | (1u << 1));\r\n\r\n    BK4819_WriteRegister(BK4819_REG_71, 0x68DC + (Type * 1032));   // 0110 1000 1101 1100\r\n}\r\n\r\nbool BK4819_CompanderEnabled(void) {\r\n    return (BK4819_ReadRegister(BK4819_REG_31) & (1u << 3)) ? true : false;\r\n}\r\n\r\nvoid BK4819_SetCompander(const unsigned int mode) {\r\n    // mode 0 .. OFF\r\n    // mode 1 .. TX\r\n    // mode 2 .. RX\r\n    // mode 3 .. TX and RX\r\n\r\n    const uint16_t r31 = BK4819_ReadRegister(BK4819_REG_31);\r\n\r\n    if (mode == 0) {    // disable\r\n        BK4819_WriteRegister(BK4819_REG_31, r31 & ~(1u << 3));\r\n        return;\r\n    }\r\n\r\n    // REG_29\r\n    //\r\n    // <15:14> 10 Compress (AF Tx) Ratio\r\n    //         00 = Disable\r\n    //         01 = 1.333:1\r\n    //         10 = 2:1\r\n    //         11 = 4:1\r\n    //\r\n    // <13:7>  86 Compress (AF Tx) 0 dB point (dB)\r\n    //\r\n    // <6:0>   64 Compress (AF Tx) noise point (dB)\r\n    //\r\n    const uint16_t compress_ratio = (mode == 1 || mode >= 3) ? 2 : 0;  // 2:1\r\n    const uint16_t compress_0dB = 86;\r\n    const uint16_t compress_noise_dB = 64;\r\n//\tAB40  10 1010110 1000000\r\n    BK4819_WriteRegister(BK4819_REG_29, // (BK4819_ReadRegister(BK4819_REG_29) & ~(3u << 14)) | (compress_ratio << 14));\r\n                         (compress_ratio << 14) |\r\n                         (compress_0dB << 7) |\r\n                         (compress_noise_dB << 0));\r\n\r\n    // REG_28\r\n    //\r\n    // <15:14> 01 Expander (AF Rx) Ratio\r\n    //         00 = Disable\r\n    //         01 = 1:2\r\n    //         10 = 1:3\r\n    //         11 = 1:4\r\n    //\r\n    // <13:7>  86 Expander (AF Rx) 0 dB point (dB)\r\n    //\r\n    // <6:0>   56 Expander (AF Rx) noise point (dB)\r\n    //\r\n    const uint16_t expand_ratio = (mode >= 2) ? 1 : 0;   // 1:2\r\n    const uint16_t expand_0dB = 86;\r\n    const uint16_t expand_noise_dB = 56;\r\n//\t6B38  01 1010110 0111000\r\n    BK4819_WriteRegister(BK4819_REG_28, // (BK4819_ReadRegister(BK4819_REG_28) & ~(3u << 14)) | (expand_ratio << 14));\r\n                         (expand_ratio << 14) |\r\n                         (expand_0dB << 7) |\r\n                         (expand_noise_dB << 0));\r\n\r\n    // enable\r\n    BK4819_WriteRegister(BK4819_REG_31, r31 | (1u << 3));\r\n}\r\n\r\nvoid BK4819_DisableVox(void) {\r\n    const uint16_t Value = BK4819_ReadRegister(BK4819_REG_31);\r\n    BK4819_WriteRegister(BK4819_REG_31, Value & 0xFFFB);\r\n}\r\n\r\nvoid BK4819_DisableDTMF(void) {\r\n    BK4819_WriteRegister(BK4819_REG_24, 0);\r\n}\r\n\r\nvoid BK4819_EnableDTMF(void) {\r\n    // no idea what this does\r\n    BK4819_WriteRegister(BK4819_REG_21, 0x06D8);        // 0000 0110 1101 1000\r\n\r\n    // REG_24\r\n    //\r\n    // <15>   1  ???\r\n    //\r\n    // <14:7> 24 Threshold\r\n    //\r\n    // <6>    1  ???\r\n    //\r\n    // <5>    0  DTMF/SelCall enable\r\n    //        1 = Enable\r\n    //        0 = Disable\r\n    //\r\n    // <4>    1  DTMF or SelCall detection mode\r\n    //        1 = for DTMF\r\n    //        0 = for SelCall\r\n    //\r\n    // <3:0>  14 Max symbol number for SelCall detection\r\n    //\r\n//\tconst uint16_t threshold = 24;    // default, but doesn't decode non-QS radios\r\n    const uint16_t threshold = 130;   // but 128 ~ 247 does\r\n    BK4819_WriteRegister(BK4819_REG_24,                      // 1 00011000 1 1 1 1110\r\n                         (1u << BK4819_REG_24_SHIFT_UNKNOWN_15) |\r\n                         (threshold << BK4819_REG_24_SHIFT_THRESHOLD) |      // 0 ~ 255\r\n                         (1u << BK4819_REG_24_SHIFT_UNKNOWN_6) |\r\n                         BK4819_REG_24_ENABLE |\r\n                         BK4819_REG_24_SELECT_DTMF |\r\n                         (15u << BK4819_REG_24_SHIFT_MAX_SYMBOLS));     // 0 ~ 15\r\n}\r\n\r\nvoid BK4819_PlayTone(uint16_t Frequency, bool bTuningGainSwitch) {\r\n    uint16_t ToneConfig = BK4819_REG_70_ENABLE_TONE1;\r\n\r\n    BK4819_EnterTxMute();\r\n    BK4819_SetAF(BK4819_AF_BEEP);\r\n\r\n    if (bTuningGainSwitch == 0)\r\n        ToneConfig |= 96u << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN;\r\n    else\r\n        ToneConfig |= 28u << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN;\r\n    BK4819_WriteRegister(BK4819_REG_70, ToneConfig);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_30, 0);\r\n    BK4819_WriteRegister(BK4819_REG_30,\r\n                         BK4819_REG_30_ENABLE_AF_DAC | BK4819_REG_30_ENABLE_DISC_MODE | BK4819_REG_30_ENABLE_TX_DSP);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_71, scale_freq(Frequency));\r\n}\r\n\r\n// level 0 ~ 127\r\nvoid BK4819_PlaySingleTone(const unsigned int tone_Hz, const unsigned int delay, const unsigned int level,\r\n                           const bool play_speaker) {\r\n    BK4819_EnterTxMute();\r\n\r\n    if (play_speaker) {\r\n        AUDIO_AudioPathOn();\r\n        BK4819_SetAF(BK4819_AF_BEEP);\r\n    } else\r\n        BK4819_SetAF(BK4819_AF_MUTE);\r\n\r\n\r\n    BK4819_WriteRegister(BK4819_REG_70,\r\n                         BK4819_REG_70_ENABLE_TONE1 | ((level & 0x7f) << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN));\r\n\r\n    BK4819_EnableTXLink();\r\n    SYSTEM_DelayMs(50);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_71, scale_freq(tone_Hz));\r\n\r\n    BK4819_ExitTxMute();\r\n    SYSTEM_DelayMs(delay);\r\n    BK4819_EnterTxMute();\r\n\r\n    if (play_speaker) {\r\n        AUDIO_AudioPathOff();\r\n        BK4819_SetAF(BK4819_AF_MUTE);\r\n    }\r\n\r\n    BK4819_WriteRegister(BK4819_REG_70, 0x0000);\r\n    BK4819_WriteRegister(BK4819_REG_30, 0xC1FE);\r\n    BK4819_ExitTxMute();\r\n}\r\n\r\nvoid BK4819_EnterTxMute(void) {\r\n    BK4819_WriteRegister(BK4819_REG_50, 0xBB20);\r\n}\r\n\r\nvoid BK4819_ExitTxMute(void) {\r\n    BK4819_WriteRegister(BK4819_REG_50, 0x3B20);\r\n}\r\n\r\nvoid BK4819_Sleep(void) {\r\n    BK4819_WriteRegister(BK4819_REG_30, 0);\r\n    BK4819_WriteRegister(BK4819_REG_37, 0x1D00);\r\n}\r\n\r\nvoid BK4819_TurnsOffTones_TurnsOnRX(void) {\r\n    BK4819_WriteRegister(BK4819_REG_70, 0);\r\n    BK4819_SetAF(BK4819_AF_MUTE);\r\n\r\n    BK4819_ExitTxMute();\r\n\r\n    BK4819_WriteRegister(BK4819_REG_30, 0);\r\n    BK4819_WriteRegister(BK4819_REG_30,\r\n                         BK4819_REG_30_ENABLE_VCO_CALIB |\r\n                         BK4819_REG_30_ENABLE_RX_LINK |\r\n                         BK4819_REG_30_ENABLE_AF_DAC |\r\n                         BK4819_REG_30_ENABLE_DISC_MODE |\r\n                         BK4819_REG_30_ENABLE_PLL_VCO |\r\n                         BK4819_REG_30_ENABLE_RX_DSP);\r\n}\r\n\r\n#ifdef ENABLE_AIRCOPY\r\nvoid BK4819_SetupAircopy(void)\r\n    {\r\n        BK4819_WriteRegister(BK4819_REG_70, 0x00E0);    // Enable Tone2, tuning gain 48\r\n        BK4819_WriteRegister(BK4819_REG_72, 0x3065);    // Tone2 baudrate 1200\r\n        BK4819_WriteRegister(BK4819_REG_58, 0x00C1);    // FSK Enable, FSK 1.2K RX Bandwidth, Preamble 0xAA or 0x55, RX Gain 0, RX Mode\r\n                                                        // (FSK1.2K, FSK2.4K Rx and NOAA SAME Rx), TX Mode FSK 1.2K and FSK 2.4K Tx\r\n        BK4819_WriteRegister(BK4819_REG_5C, 0x5665);    // Enable CRC among other things we don't know yet\r\n        BK4819_WriteRegister(BK4819_REG_5D, 0x4700);    // FSK Data Length 72 Bytes (0xabcd + 2 byte length + 64 byte payload + 2 byte CRC + 0xdcba)\r\n    }\r\n#endif\r\n\r\nvoid BK4819_ResetFSK(void) {\r\n    BK4819_WriteRegister(BK4819_REG_3F, 0x0000);        // Disable interrupts\r\n    BK4819_WriteRegister(BK4819_REG_59, 0x0068);        // Sync length 4 bytes, 7 byte preamble\r\n\r\n    SYSTEM_DelayMs(30);\r\n\r\n    BK4819_Disable();\r\n}\r\n\r\nvoid BK4819_ExitBypass(void) {\r\n    BK4819_SetAF(BK4819_AF_MUTE);\r\n\r\n    // REG_7E\r\n    //\r\n    // <15>    0 AGC fix mode\r\n    //         1 = fix\r\n    //         0 = auto\r\n    //\r\n    // <14:12> 3 AGC fix index\r\n    //         3 ( 3) = max\r\n    //         2 ( 2)\r\n    //         1 ( 1)\r\n    //         0 ( 0)\r\n    //         7 (-1)\r\n    //         6 (-2)\r\n    //         5 (-3)\r\n    //         4 (-4) = min\r\n    //\r\n    // <11:6>  0 ???\r\n    //\r\n    // <5:3>   5 DC filter band width for Tx (MIC In)\r\n    //         0 ~ 7\r\n    //         0 = bypass DC filter\r\n    //\r\n    // <2:0>   6 DC filter band width for Rx (I.F In)\r\n    //         0 ~ 7\r\n    //         0 = bypass DC filter\r\n    //\r\n\r\n    uint16_t regVal = BK4819_ReadRegister(BK4819_REG_7E);\r\n\r\n    // 0x302E / 0 011 000000 101 110\r\n    BK4819_WriteRegister(BK4819_REG_7E, (regVal & ~(0b111 << 3))\r\n\r\n                                        | (5u << 3)       // 5  DC Filter band width for Tx (MIC In)\r\n\r\n    );\r\n}\r\n\r\nvoid BK4819_PrepareTransmit(void) {\r\n    BK4819_ExitBypass();\r\n    BK4819_ExitTxMute();\r\n    BK4819_TxOn_Beep();\r\n}\r\n\r\nvoid BK4819_TxOn_Beep(void) {\r\n    BK4819_WriteRegister(BK4819_REG_37, 0x1D0F);\r\n    BK4819_WriteRegister(BK4819_REG_52, 0x028F);\r\n    BK4819_WriteRegister(BK4819_REG_30, 0x0000);\r\n    BK4819_WriteRegister(BK4819_REG_30, 0xC1FE);\r\n}\r\n\r\nvoid BK4819_ExitSubAu(void) {\r\n    // REG_51\r\n    //\r\n    // <15>  0\r\n    //       1 = Enable TxCTCSS/CDCSS\r\n    //       0 = Disable\r\n    //\r\n    // <14>  0\r\n    //       1 = GPIO0Input for CDCSS\r\n    //       0 = Normal Mode (for BK4819 v3)\r\n    //\r\n    // <13>  0\r\n    //       1 = Transmit negative CDCSS code\r\n    //       0 = Transmit positive CDCSS code\r\n    //\r\n    // <12>  0 CTCSS/CDCSS mode selection\r\n    //       1 = CTCSS\r\n    //       0 = CDCSS\r\n    //\r\n    // <11>  0 CDCSS 24/23bit selection\r\n    //       1 = 24bit\r\n    //       0 = 23bit\r\n    //\r\n    // <10>  0 1050HzDetectionMode\r\n    //       1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz\r\n    //\r\n    // <9>   0 Auto CDCSS Bw Mode\r\n    //       1 = Disable\r\n    //       0 = Enable\r\n    //\r\n    // <8>   0 Auto CTCSS Bw Mode\r\n    //       0 = Enable\r\n    //       1 = Disable\r\n    //\r\n    // <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning\r\n    //       0   = min\r\n    //       127 = max\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_51, 0x0000);\r\n}\r\n\r\nvoid BK4819_Conditional_RX_TurnOn_and_GPIO6_Enable(void) {\r\n    if (gRxIdleMode) {\r\n        BK4819_ToggleGpioOut(BK4819_GPIO0_PIN28_RX_ENABLE, true);\r\n        BK4819_RX_TurnOn();\r\n    }\r\n}\r\n\r\nvoid BK4819_EnterDTMF_TX(bool bLocalLoopback) {\r\n    BK4819_EnableDTMF();\r\n    BK4819_EnterTxMute();\r\n    BK4819_SetAF(bLocalLoopback ? BK4819_AF_BEEP : BK4819_AF_MUTE);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_70,\r\n                         BK4819_REG_70_MASK_ENABLE_TONE1 |\r\n                         (DTMF_TONE1_GAIN << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN) |\r\n                         BK4819_REG_70_MASK_ENABLE_TONE2 |\r\n                         (DTMF_TONE2_GAIN << BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN));\r\n\r\n    BK4819_EnableTXLink();\r\n}\r\n\r\nvoid BK4819_ExitDTMF_TX(bool bKeep) {\r\n    BK4819_EnterTxMute();\r\n    BK4819_SetAF(BK4819_AF_MUTE);\r\n    BK4819_WriteRegister(BK4819_REG_70, 0x0000);\r\n    BK4819_DisableDTMF();\r\n    BK4819_WriteRegister(BK4819_REG_30, 0xC1FE);\r\n    if (!bKeep)\r\n        BK4819_ExitTxMute();\r\n}\r\n\r\nvoid BK4819_EnableTXLink(void) {\r\n    BK4819_WriteRegister(BK4819_REG_30,\r\n                         BK4819_REG_30_ENABLE_VCO_CALIB |\r\n                         BK4819_REG_30_ENABLE_UNKNOWN |\r\n                         BK4819_REG_30_DISABLE_RX_LINK |\r\n                         BK4819_REG_30_ENABLE_AF_DAC |\r\n                         BK4819_REG_30_ENABLE_DISC_MODE |\r\n                         BK4819_REG_30_ENABLE_PLL_VCO |\r\n                         BK4819_REG_30_ENABLE_PA_GAIN |\r\n                         BK4819_REG_30_DISABLE_MIC_ADC |\r\n                         BK4819_REG_30_ENABLE_TX_DSP |\r\n                         BK4819_REG_30_DISABLE_RX_DSP);\r\n}\r\n\r\nvoid BK4819_PlayDTMF(char Code) {\r\n\r\n    struct DTMF_TonePair {\r\n        uint16_t tone1;\r\n        uint16_t tone2;\r\n    };\r\n\r\n    const struct DTMF_TonePair tones[] = {\r\n            {941, 1336},\r\n            {697, 1209},\r\n            {697, 1336},\r\n            {697, 1477},\r\n            {770, 1209},\r\n            {770, 1336},\r\n            {770, 1477},\r\n            {852, 1209},\r\n            {852, 1336},\r\n            {852, 1477},\r\n            {697, 1633},\r\n            {770, 1633},\r\n            {852, 1633},\r\n            {941, 1633},\r\n            {941, 1209},\r\n            {941, 1477},\r\n    };\r\n\r\n\r\n    const struct DTMF_TonePair *pSelectedTone = NULL;\r\n    switch (Code) {\r\n        case '0'...'9':\r\n            pSelectedTone = &tones[0 + Code - '0'];\r\n            break;\r\n        case 'A'...'D':\r\n            pSelectedTone = &tones[10 + Code - 'A'];\r\n            break;\r\n        case '*':\r\n            pSelectedTone = &tones[14];\r\n            break;\r\n        case '#':\r\n            pSelectedTone = &tones[15];\r\n            break;\r\n        default:\r\n            pSelectedTone = NULL;\r\n    }\r\n\r\n    if (pSelectedTone) {\r\n        BK4819_WriteRegister(BK4819_REG_71,\r\n                             (((uint32_t) pSelectedTone->tone1 * 103244) + 5000) / 10000);   // with rounding\r\n        BK4819_WriteRegister(BK4819_REG_72,\r\n                             (((uint32_t) pSelectedTone->tone2 * 103244) + 5000) / 10000);   // with rounding\r\n    }\r\n}\r\n\r\nvoid BK4819_PlayDTMFString(const char *pString, bool bDelayFirst, uint16_t FirstCodePersistTime,\r\n                           uint16_t HashCodePersistTime, uint16_t CodePersistTime, uint16_t CodeInternalTime) {\r\n    unsigned int i;\r\n\r\n    if (pString == NULL)\r\n        return;\r\n\r\n    for (i = 0; pString[i]; i++) {\r\n        uint16_t Delay;\r\n        BK4819_PlayDTMF(pString[i]);\r\n        BK4819_ExitTxMute();\r\n        if (bDelayFirst && i == 0)\r\n            Delay = FirstCodePersistTime;\r\n        else if (pString[i] == '*' || pString[i] == '#')\r\n            Delay = HashCodePersistTime;\r\n        else\r\n            Delay = CodePersistTime;\r\n        SYSTEM_DelayMs(Delay);\r\n        BK4819_EnterTxMute();\r\n        SYSTEM_DelayMs(CodeInternalTime);\r\n    }\r\n}\r\n\r\nvoid BK4819_TransmitTone(bool bLocalLoopback, uint32_t Frequency) {\r\n    BK4819_EnterTxMute();\r\n\r\n    // REG_70\r\n    //\r\n    // <15>   0 Enable TONE1\r\n    //        1 = Enable\r\n    //        0 = Disable\r\n    //\r\n    // <14:8> 0 TONE1 tuning gain\r\n    //        0 ~ 127\r\n    //\r\n    // <7>    0 Enable TONE2\r\n    //        1 = Enable\r\n    //        0 = Disable\r\n    //\r\n    // <6:0>  0 TONE2/FSK amplitude\r\n    //        0 ~ 127\r\n    //\r\n    // set the tone amplitude\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_70,\r\n                         BK4819_REG_70_MASK_ENABLE_TONE1 | (66u << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN));\r\n\r\n    BK4819_WriteRegister(BK4819_REG_71, scale_freq(Frequency));\r\n\r\n    BK4819_SetAF(bLocalLoopback ? BK4819_AF_BEEP : BK4819_AF_MUTE);\r\n\r\n    BK4819_EnableTXLink();\r\n\r\n    SYSTEM_DelayMs(50);\r\n\r\n    BK4819_ExitTxMute();\r\n}\r\n\r\nvoid BK4819_GenTail(uint8_t Tail) {\r\n    // REG_52\r\n    //\r\n    // <15>    0 Enable 120/180/240 degree shift CTCSS or 134.4Hz Tail when CDCSS mode\r\n    //         0 = Normal\r\n    //         1 = Enable\r\n    //\r\n    // <14:13> 0 CTCSS tail mode selection (only valid when REG_52 <15> = 1)\r\n    //         00 = for 134.4Hz CTCSS Tail when CDCSS mode\r\n    //         01 = CTCSS0 120° phase shift\r\n    //         10 = CTCSS0 180° phase shift\r\n    //         11 = CTCSS0 240° phase shift\r\n    //\r\n    // <12>    0 CTCSSDetectionThreshold Mode\r\n    //         1 = ~0.1%\r\n    //         0 =  0.1 Hz\r\n    //\r\n    // <11:6>  0x0A CTCSS found detect threshold\r\n    //\r\n    // <5:0>   0x0F CTCSS lost  detect threshold\r\n\r\n    // REG_07 <15:0>\r\n    //\r\n    // When <13> = 0 for CTC1\r\n    // <12:0> = CTC1 frequency control word =\r\n    //                          freq(Hz) * 20.64888 for XTAL 13M/26M or\r\n    //                          freq(Hz) * 20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    // When <13> = 1 for CTC2 (Tail 55Hz Rx detection)\r\n    // <12:0> = CTC2 (should below 100Hz) frequency control word =\r\n    //                          25391 / freq(Hz) for XTAL 13M/26M or\r\n    //                          25000 / freq(Hz) for XTAL 12.8M/19.2M/25.6M/38.4M\r\n    //\r\n    // When <13> = 2 for CDCSS 134.4Hz\r\n    // <12:0> = CDCSS baud rate frequency (134.4Hz) control word =\r\n    //                          freq(Hz) * 20.64888 for XTAL 13M/26M or\r\n    //                          freq(Hz)*20.97152 for XTAL 12.8M/19.2M/25.6M/38.4M\r\n\r\n    switch (Tail) {\r\n        case 0: // 134.4Hz CTCSS Tail\r\n            BK4819_WriteRegister(BK4819_REG_52, 0x828F);   // 1 00 0 001010 001111\r\n            break;\r\n        case 1: // 120° phase shift\r\n            BK4819_WriteRegister(BK4819_REG_52, 0xA28F);   // 1 01 0 001010 001111\r\n            break;\r\n        case 2: // 180° phase shift\r\n            BK4819_WriteRegister(BK4819_REG_52, 0xC28F);   // 1 10 0 001010 001111\r\n            break;\r\n        case 3: // 240° phase shift\r\n            BK4819_WriteRegister(BK4819_REG_52, 0xE28F);   // 1 11 0 001010 001111\r\n            break;\r\n        case 4: // 55Hz tone freq\r\n            BK4819_WriteRegister(BK4819_REG_07, 0x046f);   // 0 00 0 010001 101111\r\n            break;\r\n    }\r\n}\r\n\r\nvoid BK4819_PlayCDCSSTail(void) {\r\n    BK4819_GenTail(0);     // CTC134\r\n    //亚音\r\n//    BK4819_WriteRegister(BK4819_REG_51, 0x804A);\r\n    BK4819_WriteRegister(BK4819_REG_51, 0x8033);\r\n\r\n}\r\n\r\nvoid BK4819_PlayCTCSSTail(void) {\r\n#ifdef ENABLE_CTCSS_TAIL_PHASE_SHIFT\r\n    //BK4819_GenTail(1);     // 120° phase shift\r\n        BK4819_GenTail(2);       // 180° phase shift\r\n        //BK4819_GenTail(3);     // 240° phase shift\r\n#else\r\n    BK4819_GenTail(4);       // 55Hz tone freq\r\n#endif\r\n\r\n    // REG_51\r\n    //\r\n    // <15>  0\r\n    //       1 = Enable TxCTCSS/CDCSS\r\n    //       0 = Disable\r\n    //\r\n    // <14>  0\r\n    //       1 = GPIO0Input for CDCSS\r\n    //       0 = Normal Mode (for BK4819 v3)\r\n    //\r\n    // <13>  0\r\n    //       1 = Transmit negative CDCSS code\r\n    //       0 = Transmit positive CDCSS code\r\n    //\r\n    // <12>  0 CTCSS/CDCSS mode selection\r\n    //       1 = CTCSS\r\n    //       0 = CDCSS\r\n    //\r\n    // <11>  0 CDCSS 24/23bit selection\r\n    //       1 = 24bit\r\n    //       0 = 23bit\r\n    //\r\n    // <10>  0 1050HzDetectionMode\r\n    //       1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz\r\n    //\r\n    // <9>   0 Auto CDCSS Bw Mode\r\n    //       1 = Disable\r\n    //       0 = Enable\r\n    //\r\n    // <8>   0 Auto CTCSS Bw Mode\r\n    //       0 = Enable\r\n    //       1 = Disable\r\n    //\r\n    // <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning\r\n    //       0   = min\r\n    //       127 = max\r\n//亚音\r\n//    BK4819_WriteRegister(BK4819_REG_51, 0x904A); // 1 0 0 1 0 0 0 0 0 1001010\r\n    BK4819_WriteRegister(BK4819_REG_51, 0x9033); // 1 0 0 1 0 0 0 0 0 1001010\r\n\r\n}\r\n\r\nuint16_t BK4819_GetRSSI(void) {\r\n    return BK4819_ReadRegister(BK4819_REG_67) & 0x01FF;\r\n}\r\n\r\nuint8_t BK4819_GetGlitchIndicator(void) {\r\n    return BK4819_ReadRegister(BK4819_REG_63) & 0x00FF;\r\n}\r\n\r\nuint8_t BK4819_GetExNoiceIndicator(void) {\r\n    return BK4819_ReadRegister(BK4819_REG_65) & 0x007F;\r\n}\r\n\r\nuint16_t BK4819_GetVoiceAmplitudeOut(void) {\r\n    return BK4819_ReadRegister(BK4819_REG_64);\r\n}\r\n\r\nuint8_t BK4819_GetAfTxRx(void) {\r\n    return BK4819_ReadRegister(BK4819_REG_6F) & 0x003F;\r\n}\r\n\r\nbool BK4819_GetFrequencyScanResult(uint32_t *pFrequency) {\r\n    const uint16_t High = BK4819_ReadRegister(BK4819_REG_0D);\r\n    const bool Finished = (High & 0x8000) == 0;\r\n    if (Finished) {\r\n        const uint16_t Low = BK4819_ReadRegister(BK4819_REG_0E);\r\n        *pFrequency = (uint32_t) ((High & 0x7FF) << 16) | Low;\r\n    }\r\n    return Finished;\r\n}\r\n\r\nBK4819_CssScanResult_t BK4819_GetCxCSSScanResult(uint32_t *pCdcssFreq, uint16_t *pCtcssFreq) {\r\n    uint16_t Low;\r\n    uint16_t High = BK4819_ReadRegister(BK4819_REG_69);\r\n\r\n    if ((High & 0x8000) == 0) {\r\n        Low = BK4819_ReadRegister(BK4819_REG_6A);\r\n        *pCdcssFreq = ((High & 0xFFF) << 12) | (Low & 0xFFF);\r\n        return BK4819_CSS_RESULT_CDCSS;\r\n    }\r\n\r\n    Low = BK4819_ReadRegister(BK4819_REG_68);\r\n\r\n    if ((Low & 0x8000) == 0) {\r\n        *pCtcssFreq = ((Low & 0x1FFF) * 4843) / 10000;\r\n        return BK4819_CSS_RESULT_CTCSS;\r\n    }\r\n\r\n    return BK4819_CSS_RESULT_NOT_FOUND;\r\n}\r\n\r\nvoid BK4819_DisableFrequencyScan(void) {\r\n    // REG_32\r\n    //\r\n    // <15:14> 0 frequency scan time\r\n    //         0 = 0.2 sec\r\n    //         1 = 0.4 sec\r\n    //         2 = 0.8 sec\r\n    //         3 = 1.6 sec\r\n    //\r\n    // <13:1>  ???\r\n    //\r\n    // <0>     0 frequency scan enable\r\n    //         1 = enable\r\n    //         0 = disable\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_32, // 0x0244);    // 00 0000100100010 0\r\n                         (0u << 14) |          // 0 frequency scan Time\r\n                         (290u << 1) |          // ???\r\n                         (0u << 0));          // 0 frequency scan enable\r\n}\r\n\r\nvoid BK4819_EnableFrequencyScan(void) {\r\n    // REG_32\r\n    //\r\n    // <15:14> 0 frequency scan time\r\n    //         0 = 0.2 sec\r\n    //         1 = 0.4 sec\r\n    //         2 = 0.8 sec\r\n    //         3 = 1.6 sec\r\n    //\r\n    // <13:1>  ???\r\n    //\r\n    // <0>     0 frequency scan enable\r\n    //         1 = enable\r\n    //         0 = disable\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_32, // 0x0245);   // 00 0000100100010 1\r\n                         (0u << 14) |          // 0 frequency scan time\r\n                         (290u << 1) |          // ???\r\n                         (1u << 0));          // 1 frequency scan enable\r\n}\r\n\r\nvoid BK4819_SetScanFrequency(uint32_t Frequency) {\r\n    BK4819_SetFrequency(Frequency);\r\n\r\n    // REG_51\r\n    //\r\n    // <15>  0\r\n    //       1 = Enable TxCTCSS/CDCSS\r\n    //       0 = Disable\r\n    //\r\n    // <14>  0\r\n    //       1 = GPIO0Input for CDCSS\r\n    //       0 = Normal Mode (for BK4819 v3)\r\n    //\r\n    // <13>  0\r\n    //       1 = Transmit negative CDCSS code\r\n    //       0 = Transmit positive CDCSS code\r\n    //\r\n    // <12>  0 CTCSS/CDCSS mode selection\r\n    //       1 = CTCSS\r\n    //       0 = CDCSS\r\n    //\r\n    // <11>  0 CDCSS 24/23bit selection\r\n    //       1 = 24bit\r\n    //       0 = 23bit\r\n    //\r\n    // <10>  0 1050HzDetectionMode\r\n    //       1 = 1050/4 Detect Enable, CTC1 should be set to 1050/4 Hz\r\n    //\r\n    // <9>   0 Auto CDCSS Bw Mode\r\n    //       1 = Disable\r\n    //       0 = Enable\r\n    //\r\n    // <8>   0 Auto CTCSS Bw Mode\r\n    //       0 = Enable\r\n    //       1 = Disable\r\n    //\r\n    // <6:0> 0 CTCSS/CDCSS Tx Gain1 Tuning\r\n    //       0   = min\r\n    //       127 = max\r\n    //\r\n    BK4819_WriteRegister(BK4819_REG_51,\r\n                         BK4819_REG_51_DISABLE_CxCSS |\r\n                         BK4819_REG_51_GPIO6_PIN2_NORMAL |\r\n                         BK4819_REG_51_TX_CDCSS_POSITIVE |\r\n                         BK4819_REG_51_MODE_CDCSS |\r\n                         BK4819_REG_51_CDCSS_23_BIT |\r\n                         BK4819_REG_51_1050HZ_NO_DETECTION |\r\n                         BK4819_REG_51_AUTO_CDCSS_BW_DISABLE |\r\n                         BK4819_REG_51_AUTO_CTCSS_BW_DISABLE);\r\n\r\n    BK4819_RX_TurnOn();\r\n}\r\n\r\nvoid BK4819_Disable(void) {\r\n    BK4819_WriteRegister(BK4819_REG_30, 0);\r\n\r\n}\r\n\r\nvoid BK4819_StopScan(void) {\r\n    BK4819_DisableFrequencyScan();\r\n    BK4819_Disable();\r\n}\r\n\r\nuint8_t BK4819_GetDTMF_5TONE_Code(void) {\r\n    return (BK4819_ReadRegister(BK4819_REG_0B) >> 8) & 0x0F;\r\n}\r\n\r\nuint8_t BK4819_GetCDCSSCodeType(void) {\r\n    return (BK4819_ReadRegister(BK4819_REG_0C) >> 14) & 3u;\r\n}\r\n\r\nuint8_t BK4819_GetCTCShift(void) {\r\n    return (BK4819_ReadRegister(BK4819_REG_0C) >> 12) & 3u;\r\n}\r\n\r\nuint8_t BK4819_GetCTCType(void) {\r\n    return (BK4819_ReadRegister(BK4819_REG_0C) >> 10) & 3u;\r\n}\r\n\r\nvoid BK4819_SendFSKData(uint16_t *pData) {\r\n    unsigned int i;\r\n    uint8_t Timeout = 200;\r\n\r\n    SYSTEM_DelayMs(20);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_3F, BK4819_REG_3F_FSK_TX_FINISHED);\r\n    BK4819_WriteRegister(BK4819_REG_59, 0x8068);\r\n    BK4819_WriteRegister(BK4819_REG_59, 0x0068);\r\n\r\n    for (i = 0; i < 36; i++)\r\n        BK4819_WriteRegister(BK4819_REG_5F, pData[i]);\r\n\r\n    SYSTEM_DelayMs(20);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_59, 0x2868);\r\n\r\n    while (Timeout-- && (BK4819_ReadRegister(BK4819_REG_0C) & 1u) == 0)\r\n        SYSTEM_DelayMs(5);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_02, 0);\r\n\r\n    SYSTEM_DelayMs(20);\r\n\r\n    BK4819_ResetFSK();\r\n}\r\n\r\nvoid BK4819_PrepareFSKReceive(void) {\r\n    BK4819_ResetFSK();\r\n    BK4819_WriteRegister(BK4819_REG_02, 0);\r\n    BK4819_WriteRegister(BK4819_REG_3F, 0);\r\n    BK4819_RX_TurnOn();\r\n    BK4819_WriteRegister(BK4819_REG_3F, 0 | BK4819_REG_3F_FSK_RX_FINISHED | BK4819_REG_3F_FSK_FIFO_ALMOST_FULL);\r\n\r\n    // Clear RX FIFO\r\n    // FSK Preamble Length 7 bytes\r\n    // FSK SyncLength Selection\r\n    BK4819_WriteRegister(BK4819_REG_59, 0x4068);\r\n\r\n    // Enable FSK Scramble\r\n    // Enable FSK RX\r\n    // FSK Preamble Length 7 bytes\r\n    // FSK SyncLength Selection\r\n    BK4819_WriteRegister(BK4819_REG_59, 0x3068);\r\n}\r\n\r\n\r\nvoid BK4819_PlayRogerNormal(void) {\r\n#if 0\r\n    const uint32_t tone1_Hz = 500;\r\n        const uint32_t tone2_Hz = 700;\r\n#else\r\n    // motorola type\r\n    const uint32_t tone1_Hz = 1540;\r\n    const uint32_t tone2_Hz = 1310;\r\n#endif\r\n\r\n    BK4819_EnterTxMute();\r\n    BK4819_SetAF(BK4819_AF_MUTE);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_70, BK4819_REG_70_ENABLE_TONE1 | (66u << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN));\r\n\r\n    BK4819_EnableTXLink();\r\n    SYSTEM_DelayMs(50);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_71, scale_freq(tone1_Hz));\r\n\r\n    BK4819_ExitTxMute();\r\n    SYSTEM_DelayMs(80);\r\n    BK4819_EnterTxMute();\r\n\r\n    BK4819_WriteRegister(BK4819_REG_71, scale_freq(tone2_Hz));\r\n\r\n    BK4819_ExitTxMute();\r\n    SYSTEM_DelayMs(80);\r\n    BK4819_EnterTxMute();\r\n\r\n    BK4819_WriteRegister(BK4819_REG_70, 0x0000);\r\n    BK4819_WriteRegister(BK4819_REG_30, 0xC1FE);   // 1 1 0000 0 1 1111 1 1 1 0\r\n}\r\n\r\n\r\nvoid BK4819_Enable_AfDac_DiscMode_TxDsp(void) {\r\n    BK4819_WriteRegister(BK4819_REG_30, 0x0000);\r\n    BK4819_WriteRegister(BK4819_REG_30, 0x0302);\r\n}\r\n\r\nvoid BK4819_GetVoxAmp(uint16_t *pResult) {\r\n    *pResult = BK4819_ReadRegister(BK4819_REG_64) & 0x7FFF;\r\n}\r\n\r\nvoid BK4819_SetScrambleFrequencyControlWord(uint32_t Frequency) {\r\n    BK4819_WriteRegister(BK4819_REG_71, scale_freq(Frequency));\r\n}\r\n\r\nvoid BK4819_PlayDTMFEx(bool bLocalLoopback, char Code) {\r\n    BK4819_EnableDTMF();\r\n    BK4819_EnterTxMute();\r\n\r\n    BK4819_SetAF(bLocalLoopback ? BK4819_AF_BEEP : BK4819_AF_MUTE);\r\n\r\n    BK4819_WriteRegister(BK4819_REG_70,\r\n                         BK4819_REG_70_MASK_ENABLE_TONE1 |\r\n                         (DTMF_TONE1_GAIN << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN) |\r\n                         BK4819_REG_70_MASK_ENABLE_TONE2 |\r\n                         (DTMF_TONE2_GAIN << BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN));\r\n\r\n    BK4819_EnableTXLink();\r\n\r\n    SYSTEM_DelayMs(50);\r\n\r\n    BK4819_PlayDTMF(Code);\r\n\r\n    BK4819_ExitTxMute();\r\n}\r\n\r\n#ifdef ENABLE_MDC1200\r\nvoid BK4819_start_tone(const uint16_t frequency, const unsigned int level, const bool tx, const bool tx_mute)\r\n{\r\n    SYSTEM_DelayMs(1);\r\n\r\n    GPIO_ClearBit(&GPIOC->DATA, 4);\r\n\r\n    SYSTEM_DelayMs(1);\r\n\r\n    // mute TX\r\n    BK4819_WriteRegister(0x50, (1u << 15) | 0x3B20);\r\n\r\n    BK4819_WriteRegister(0x70, BK4819_REG_70_ENABLE_TONE1 | ((level & 0x7f) << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN));\r\n\r\n    BK4819_WriteRegister(0x30, 0);\r\n\r\n    if (!tx)\r\n    {\r\n        BK4819_WriteRegister(0x30,\r\n//\t\t\tBK4819_REG_30_ENABLE_VCO_CALIB |\r\n//\t\t\tBK4819_REG_30_ENABLE_UNKNOWN   |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_LINK   |\r\n            BK4819_REG_30_ENABLE_AF_DAC    |\r\n            BK4819_REG_30_ENABLE_DISC_MODE |\r\n//\t\t\tBK4819_REG_30_ENABLE_PLL_VCO   |\r\n//\t\t\tBK4819_REG_30_ENABLE_PA_GAIN   |\r\n//\t\t\tBK4819_REG_30_ENABLE_MIC_ADC   |\r\n            BK4819_REG_30_ENABLE_TX_DSP    |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_DSP    |\r\n        0);\r\n    }\r\n    else\r\n    {\r\n        BK4819_WriteRegister(0x30,\r\n            BK4819_REG_30_ENABLE_VCO_CALIB |\r\n            BK4819_REG_30_ENABLE_UNKNOWN   |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_LINK   |\r\n            BK4819_REG_30_ENABLE_AF_DAC    |\r\n            BK4819_REG_30_ENABLE_DISC_MODE |\r\n            BK4819_REG_30_ENABLE_PLL_VCO   |\r\n            BK4819_REG_30_ENABLE_PA_GAIN   |\r\n//\t\t\tBK4819_REG_30_ENABLE_MIC_ADC   |\r\n            BK4819_REG_30_ENABLE_TX_DSP    |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_DSP    |\r\n        0);\r\n    }\r\n\r\n    BK4819_WriteRegister(0x71, scale_freq(frequency));\r\n\r\n    SYSTEM_DelayMs(1);\r\n\r\n//\tBK4819_SetAF(tx ? BK4819_AF_BEEP : 2);\r\n    BK4819_SetAF(2);  // RX\r\n//\tBK4819_SetAF(BK4819_AF_BEEP);  // TX\r\n\r\n    if (!tx_mute)\r\n        BK4819_WriteRegister(0x50, 0x3B20);   // 0011 1011 0010 0000\r\n\r\n    GPIO_SetBit(&GPIOC->DATA, 4);\r\n\r\n    SYSTEM_DelayMs(1);\r\n}\r\n\r\nvoid BK4819_stop_tones(const bool tx)\r\n{\r\n    SYSTEM_DelayMs(1);\r\n\r\n    GPIO_ClearBit(&GPIOC->DATA, 4);\r\n\r\n    SYSTEM_DelayMs(1);\r\n\r\n    BK4819_SetAF(BK4819_AF_MUTE);\r\n\r\n//\tBK4819_EnterTxMute();\r\n\r\n    SYSTEM_DelayMs(1);\r\n\r\n    BK4819_WriteRegister(0x70, 0);\r\n\r\n    BK4819_WriteRegister(0x30, 0);\r\n    if (!tx)\r\n    {\r\n        BK4819_WriteRegister(0x30,\r\n            BK4819_REG_30_ENABLE_VCO_CALIB |\r\n//\t\t\tBK4819_REG_30_ENABLE_UNKNOWN   |\r\n            BK4819_REG_30_ENABLE_RX_LINK   |\r\n            BK4819_REG_30_ENABLE_AF_DAC    |\r\n            BK4819_REG_30_ENABLE_DISC_MODE |\r\n            BK4819_REG_30_ENABLE_PLL_VCO   |\r\n//\t\t\tBK4819_REG_30_ENABLE_PA_GAIN   |\r\n//\t\t\tBK4819_REG_30_ENABLE_MIC_ADC   |\r\n//\t\t\tBK4819_REG_30_ENABLE_TX_DSP    |\r\n            BK4819_REG_30_ENABLE_RX_DSP    |\r\n        0);\r\n    }\r\n    else\r\n    {\r\n        BK4819_WriteRegister(0x30,\r\n            BK4819_REG_30_ENABLE_VCO_CALIB |\r\n            BK4819_REG_30_ENABLE_UNKNOWN   |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_LINK   |\r\n            BK4819_REG_30_ENABLE_AF_DAC    |\r\n            BK4819_REG_30_ENABLE_DISC_MODE |\r\n            BK4819_REG_30_ENABLE_PLL_VCO   |\r\n            BK4819_REG_30_ENABLE_PA_GAIN   |\r\n            BK4819_REG_30_ENABLE_MIC_ADC   |\r\n            BK4819_REG_30_ENABLE_TX_DSP    |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_DSP    |\r\n        0);\r\n    }\r\n\r\n    SYSTEM_DelayMs(1);\r\n\r\n    BK4819_ExitTxMute();\r\n\r\n    SYSTEM_DelayMs(1);\r\n}\r\n\r\n\r\n    void BK4819_send_MDC1200(const uint8_t op, const uint8_t arg, const uint16_t id, const bool long_preamble)\r\n    {\r\n        uint16_t fsk_reg59;\r\n        uint8_t  packet[42];\r\n\r\n        // create the MDC1200 packet\r\n        const unsigned int size = MDC1200_encode_single_packet(packet, op, arg, id);\r\n\r\n        //BK4819_ExitTxMute();\r\n        BK4819_WriteRegister(0x50, 0x3B20);  // 0011 1011 0010 0000\r\n\r\n        BK4819_WriteRegister(0x30,\r\n            BK4819_REG_30_ENABLE_VCO_CALIB |\r\n            BK4819_REG_30_ENABLE_UNKNOWN   |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_LINK   |\r\n            BK4819_REG_30_ENABLE_AF_DAC    |\r\n            BK4819_REG_30_ENABLE_DISC_MODE |\r\n            BK4819_REG_30_ENABLE_PLL_VCO   |\r\n            BK4819_REG_30_ENABLE_PA_GAIN   |\r\n//\t\t\tBK4819_REG_30_ENABLE_MIC_ADC   |\r\n            BK4819_REG_30_ENABLE_TX_DSP    |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_DSP    |\r\n        0);\r\n\r\n#if 1\r\n            GPIO_ClearBit(&GPIOC->DATA, 4);\r\n            BK4819_SetAF(BK4819_AF_MUTE);\r\n#else\r\n            // let the user hear the FSK being sent\r\n            BK4819_SetAF(BK4819_AF_BEEP);\r\n            GPIO_SetBit(&GPIOC->DATA, 4);\r\n#endif\r\n//\t\tSYSTEM_DelayMs(2);\r\n\r\n        // REG_51\r\n        //\r\n        // <15>  TxCTCSS/CDCSS   0 = disable 1 = Enable\r\n        //\r\n        // turn off CTCSS/CDCSS during FFSK\r\n        const uint16_t css_val = BK4819_ReadRegister(0x51);\r\n        BK4819_WriteRegister(0x51, 0);\r\n\r\n        // set the FM deviation level\r\n        const uint16_t dev_val = BK4819_ReadRegister(0x40);\r\n#if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG)\r\n//\t\t\tUART_printf(\"tx dev %04X\\r\\n\", dev_val);\r\n#endif\r\n        {\r\n            uint16_t deviation = 850;\r\n            switch (m_bandwidth)\r\n            {\r\n                case BK4819_FILTER_BW_WIDE:     deviation = 1050; break;\r\n                case BK4819_FILTER_BW_NARROW:   deviation =  850; break;\r\n                case BK4819_FILTER_BW_NARROWER: deviation =  750; break;\r\n            }\r\n            //BK4819_WriteRegister(0x40, (3u << 12) | (deviation & 0xfff));\r\n            BK4819_WriteRegister(0x40, (dev_val & 0xf000) | (deviation & 0xfff));\r\n        }\r\n\r\n        // REG_2B   0\r\n        //\r\n        // <15> 1 Enable CTCSS/CDCSS DC cancellation after FM Demodulation   1 = enable 0 = disable\r\n        // <14> 1 Enable AF DC cancellation after FM Demodulation            1 = enable 0 = disable\r\n        // <10> 0 AF RX HPF 300Hz filter     0 = enable 1 = disable\r\n        // <9>  0 AF RX LPF 3kHz filter      0 = enable 1 = disable\r\n        // <8>  0 AF RX de-emphasis filter   0 = enable 1 = disable\r\n        // <2>  0 AF TX HPF 300Hz filter     0 = enable 1 = disable\r\n        // <1>  0 AF TX LPF filter           0 = enable 1 = disable\r\n        // <0>  0 AF TX pre-emphasis filter  0 = enable 1 = disable\r\n        //\r\n        // disable the 300Hz HPF and FM pre-emphasis filter\r\n        //\r\n        const uint16_t filt_val = BK4819_ReadRegister(0x2B);\r\n        BK4819_WriteRegister(0x2B, (1u << 2) | (1u << 0));\r\n\r\n        // *******************************************\r\n        // setup the FFSK modem as best we can for MDC1200\r\n\r\n        // MDC1200 uses 1200/1800 Hz FSK tone frequencies 1200 bits/s\r\n        //\r\n        BK4819_WriteRegister(0x58, // 0x37C3);   // 001 101 11 11 00 001 1\r\n            (1u << 13) |\t\t// 1 FSK TX mode selection\r\n                                //   0 = FSK 1.2K and FSK 2.4K TX .. no tones, direct FM\r\n                                //   1 = FFSK 1200/1800 TX\r\n                                //   2 = ???\r\n                                //   3 = FFSK 1200/2400 TX\r\n                                //   4 = ???\r\n                                //   5 = NOAA SAME TX\r\n                                //   6 = ???\r\n                                //   7 = ???\r\n                                //\r\n            (7u << 10) |\t\t// 0 FSK RX mode selection\r\n                                //   0 = FSK 1.2K, FSK 2.4K RX and NOAA SAME RX .. no tones, direct FM\r\n                                //   1 = ???\r\n                                //   2 = ???\r\n                                //   3 = ???\r\n                                //   4 = FFSK 1200/2400 RX\r\n                                //   5 = ???\r\n                                //   6 = ???\r\n                                //   7 = FFSK 1200/1800 RX\r\n                                //\r\n            (0u << 8) |\t\t\t// 0 FSK RX gain\r\n                                //   0 ~ 3\r\n                                //\r\n            (0u << 6) |\t\t\t// 0 ???\r\n                                //   0 ~ 3\r\n                                //\r\n            (0u << 4) |\t\t\t// 0 FSK preamble type selection\r\n                                //   0 = 0xAA or 0x55 due to the MSB of FSK sync byte 0\r\n                                //   1 = ???\r\n                                //   2 = 0x55\r\n                                //   3 = 0xAA\r\n                                //\r\n            (1u << 1) |\t\t\t// 1 FSK RX bandwidth setting\r\n                                //   0 = FSK 1.2K .. no tones, direct FM\r\n                                //   1 = FFSK 1200/1800\r\n                                //   2 = NOAA SAME RX\r\n                                //   3 = ???\r\n                                //   4 = FSK 2.4K and FFSK 1200/2400\r\n                                //   5 = ???\r\n                                //   6 = ???\r\n                                //   7 = ???\r\n                                //\r\n            (1u << 0));\t\t\t// 1 FSK enable\r\n                                //   0 = disable\r\n                                //   1 = enable\r\n\r\n        // REG_72\r\n        //\r\n        // <15:0> 0x2854 TONE-2 / FSK frequency control word\r\n        //        = freq(Hz) * 10.32444 for XTAL 13M / 26M or\r\n        //        = freq(Hz) * 10.48576 for XTAL 12.8M / 19.2M / 25.6M / 38.4M\r\n        //\r\n        // tone-2 = 1200Hz\r\n        //\r\n        BK4819_WriteRegister(0x72, scale_freq(1200));\r\n\r\n        // REG_70\r\n        //\r\n        // <15>   0 TONE-1\r\n        //        1 = enable\r\n        //        0 = disable\r\n        //\r\n        // <14:8> 0 TONE-1 tuning\r\n        //\r\n        // <7>    0 TONE-2\r\n        //        1 = enable\r\n        //        0 = disable\r\n        //\r\n        // <6:0>  0 TONE-2 / FSK tuning\r\n        //        0 ~ 127\r\n        //\r\n        // enable tone-2, set gain\r\n        //\r\n        BK4819_WriteRegister(0x70,   // 0 0000000 1 1100000\r\n            ( 0u << 15) |    // 0\r\n            ( 0u <<  8) |    // 0\r\n            ( 1u <<  7) |    // 1\r\n            (96u <<  0));    // 96\r\n//\t\t\t(127u <<  0));\r\n\r\n        // REG_59\r\n        //\r\n        // <15>  0 TX FIFO             1 = clear\r\n        // <14>  0 RX FIFO             1 = clear\r\n        // <13>  0 FSK Scramble        1 = Enable\r\n        // <12>  0 FSK RX              1 = Enable\r\n        // <11>  0 FSK TX              1 = Enable\r\n        // <10>  0 FSK data when RX    1 = Invert\r\n        // <9>   0 FSK data when TX    1 = Invert\r\n        // <8>   0 ???\r\n        //\r\n        // <7:4> 0 FSK preamble length selection\r\n        //       0  =  1 byte\r\n        //       1  =  2 bytes\r\n        //       2  =  3 bytes\r\n        //       15 = 16 bytes\r\n        //\r\n        // <3>   0 FSK sync length selection\r\n        //       0 = 2 bytes (FSK Sync Byte 0, 1)\r\n        //       1 = 4 bytes (FSK Sync Byte 0, 1, 2, 3)\r\n        //\r\n        // <2:0> 0 ???\r\n        //\r\n        fsk_reg59 = (0u << 15) |   // 0/1     1 = clear TX FIFO\r\n                    (0u << 14) |   // 0/1     1 = clear RX FIFO\r\n                    (0u << 13) |   // 0/1     1 = scramble\r\n                    (0u << 12) |   // 0/1     1 = enable RX\r\n                    (0u << 11) |   // 0/1     1 = enable TX\r\n                    (0u << 10) |   // 0/1     1 = invert data when RX\r\n                    (0u <<  9) |   // 0/1     1 = invert data when TX\r\n                    (0u <<  8) |   // 0/1     ???\r\n                    (0u <<  4) |   // 0 ~ 15  preamble length .. bit toggling\r\n                    (1u <<  3) |   // 0/1     sync length\r\n                    (0u <<  0);    // 0 ~ 7   ???\r\n        fsk_reg59 |= long_preamble ? 15u << 4 : 3u << 4;\r\n\r\n        // Set packet length (not including pre-amble and sync bytes that we can't seem to disable)\r\n        BK4819_WriteRegister(0x5D, ((size - 1) << 8));\r\n\r\n        // REG_5A\r\n        //\r\n        // <15:8> 0x55 FSK Sync Byte 0 (Sync Byte 0 first, then 1,2,3)\r\n        // <7:0>  0x55 FSK Sync Byte 1\r\n        //\r\n        BK4819_WriteRegister(0x5A, 0x0000);                   // bytes 1 & 2\r\n\r\n        // REG_5B\r\n        //\r\n        // <15:8> 0x55 FSK Sync Byte 2 (Sync Byte 0 first, then 1,2,3)\r\n        // <7:0>  0xAA FSK Sync Byte 3\r\n        //\r\n        BK4819_WriteRegister(0x5B, 0x0000);                   // bytes 2 & 3\r\n\r\n        // CRC setting (plus other stuff we don't know what)\r\n        //\r\n        // REG_5C\r\n        //\r\n        // <15:7> ???\r\n        //\r\n        // <6>    1 CRC option enable    0 = disable  1 = enable\r\n        //\r\n        // <5:0>  ???\r\n        //\r\n        // disable CRC\r\n        //\r\n        // NB, this also affects TX pre-amble in some way\r\n        //\r\n        BK4819_WriteRegister(0x5C, 0x5625);   // 010101100 0 100101\r\n//\t\tBK4819_WriteRegister(0x5C, 0xAA30);   // 101010100 0 110000\r\n//\t\tBK4819_WriteRegister(0x5C, 0x0030);   // 000000000 0 110000\r\n\r\n        BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59);   // clear FIFO's\r\n        BK4819_WriteRegister(0x59, fsk_reg59);                             // release the FIFO reset\r\n\r\n        {\t// load the entire packet data into the TX FIFO buffer\r\n            unsigned int i;\r\n            const uint16_t *p = (const uint16_t *)packet;\r\n            for (i = 0; i < (size / sizeof(p[0])); i++)\r\n                BK4819_WriteRegister(0x5F, p[i]);  // load 16-bits at a time\r\n        }\r\n\r\n        // enable tx interrupt\r\n        BK4819_WriteRegister(0x3F, BK4819_REG_3F_FSK_TX_FINISHED);\r\n\r\n        // enable FSK TX\r\n        BK4819_WriteRegister(0x59, (1u << 11) | fsk_reg59);\r\n\r\n        {\t// packet time is ..\r\n            // 173ms for PTT ID, acks, emergency\r\n            // 266ms for call alert and sel-calls\r\n\r\n            // allow up to 310ms for the TX to complete\r\n            // if it takes any longer then somethings gone wrong, we shut the TX down\r\n            unsigned int timeout = 300 / 4;\r\n\r\n            while (timeout-- > 0)\r\n            {\r\n                SYSTEM_DelayMs(4);\r\n                if (BK4819_ReadRegister(0x0C) & (1u << 0))\r\n                {\t// we have interrupt flags\r\n                    BK4819_WriteRegister(0x02, 0);\r\n                    if (BK4819_ReadRegister(0x02) & BK4819_REG_02_FSK_TX_FINISHED)\r\n                        timeout = 0;       // TX is complete\r\n                }\r\n            }\r\n        }\r\n\r\n        GPIO_ClearBit(&GPIOC->DATA, 4);\r\n\r\n        // disable FSK\r\n        BK4819_WriteRegister(0x59, fsk_reg59);\r\n\r\n        BK4819_WriteRegister(0x3F, 0);   // disable interrupts\r\n        BK4819_WriteRegister(0x70, 0);\r\n        BK4819_WriteRegister(0x58, 0);\r\n\r\n        // restore FM deviation level\r\n        BK4819_WriteRegister(0x40, dev_val);\r\n\r\n        // restore TX/RX filtering\r\n        BK4819_WriteRegister(0x2B, filt_val);\r\n\r\n        // restore the CTCSS/CDCSS setting\r\n        BK4819_WriteRegister(0x51, css_val);\r\n\r\n        //BK4819_EnterTxMute();\r\n        BK4819_WriteRegister(0x50, 0xBB20); // 1011 1011 0010 0000\r\n\r\n        //BK4819_SetAF(BK4819_AF_MUTE);\r\n        BK4819_WriteRegister(0x47, (1u << 14) | (1u << 13) | (BK4819_AF_MUTE << 8) | (1u << 6));\r\n\r\n        BK4819_WriteRegister(0x30,\r\n            BK4819_REG_30_ENABLE_VCO_CALIB |\r\n            BK4819_REG_30_ENABLE_UNKNOWN   |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_LINK   |\r\n//\t\t\tBK4819_REG_30_ENABLE_AF_DAC    |\r\n            BK4819_REG_30_ENABLE_DISC_MODE |\r\n            BK4819_REG_30_ENABLE_PLL_VCO   |\r\n            BK4819_REG_30_ENABLE_PA_GAIN   |\r\n            BK4819_REG_30_ENABLE_MIC_ADC   |\r\n            BK4819_REG_30_ENABLE_TX_DSP    |\r\n//\t\t\tBK4819_REG_30_ENABLE_RX_DSP    |\r\n        0);\r\n\r\n        //BK4819_ExitTxMute();\r\n        BK4819_WriteRegister(0x50, 0x3B20);  // 0011 1011 0010 0000\r\n    }\r\n#endif\r\n\r\nvoid enable_msg_rx(const bool enable) {\r\n    // REG_70\r\n    //\r\n    // <15>    0 TONE-1\r\n    //         1 = enable\r\n    //         0 = disable\r\n    //\r\n    // <14:8>  0 TONE-1 gain\r\n    //\r\n    // <7>     0 TONE-2\r\n    //         1 = enable\r\n    //         0 = disable\r\n    //\r\n    // <6:0>   0 TONE-2 / FSK gain\r\n    //         0 ~ 127\r\n    //\r\n    // enable tone-2, set gain\r\n\r\n    // REG_72\r\n    //\r\n    // <15:0>  0x2854 TONE-2 / FSK frequency control word\r\n    //         = freq(Hz) * 10.32444 for XTAL 13M / 26M or\r\n    //         = freq(Hz) * 10.48576 for XTAL 12.8M / 19.2M / 25.6M / 38.4M\r\n    //\r\n    // tone-2 = 1200Hz\r\n\r\n    // REG_58\r\n    //\r\n    // <15:13> 1 FSK TX mode selection\r\n    //         0 = FSK 1.2K and FSK 2.4K TX .. no tones, direct FM\r\n    //         1 = FFSK 1200 / 1800 TX\r\n    //         2 = ???\r\n    //         3 = FFSK 1200 / 2400 TX\r\n    //         4 = ???\r\n    //         5 = NOAA SAME TX\r\n    //         6 = ???\r\n    //         7 = ???\r\n    //\r\n    // <12:10> 0 FSK RX mode selection\r\n    //         0 = FSK 1.2K, FSK 2.4K RX and NOAA SAME RX .. no tones, direct FM\r\n    //         1 = ???\r\n    //         2 = ???\r\n    //         3 = ???\r\n    //         4 = FFSK 1200 / 2400 RX\r\n    //         5 = ???\r\n    //         6 = ???\r\n    //         7 = FFSK 1200 / 1800 RX\r\n    //\r\n    // <9:8>   0 FSK RX gain\r\n    //         0 ~ 3\r\n    //\r\n    // <7:6>   0 ???\r\n    //         0 ~ 3\r\n    //\r\n    // <5:4>   0 FSK preamble type selection\r\n    //         0 = 0xAA or 0x55 due to the MSB of FSK sync byte 0\r\n    //         1 = ???\r\n    //         2 = 0x55\r\n    //         3 = 0xAA\r\n    //\r\n    // <3:1>   1 FSK RX bandwidth setting\r\n    //         0 = FSK 1.2K .. no tones, direct FM\r\n    //         1 = FFSK 1200 / 1800\r\n    //         2 = NOAA SAME RX\r\n    //         3 = ???\r\n    //         4 = FSK 2.4K and FFSK 1200 / 2400\r\n    //         5 = ???\r\n    //         6 = ???\r\n    //         7 = ???\r\n    //\r\n    // <0>     1 FSK enable\r\n    //         0 = disable\r\n    //         1 = enable\r\n\r\n    // REG_5C\r\n    //\r\n    // <15:7>  ???\r\n    //\r\n    // <6>     1 CRC option enable\r\n    //         0 = disable\r\n    //         1 = enable\r\n    //\r\n    // <5:0>   ???\r\n    //\r\n    // disable CRC\r\n\r\n    // REG_5D\r\n    //\r\n    // set the packet size\r\n\r\n    if (enable) {\r\n        const uint16_t fsk_reg59 =\r\n                (0u << 15) |   // 1 = clear TX FIFO\r\n                (0u << 14) |   // 1 = clear RX FIFO\r\n                (0u << 13) |   // 1 = scramble\r\n                (0u << 12) |   // 1 = enable RX\r\n                (0u << 11) |   // 1 = enable TX\r\n                (0u << 10) |   // 1 = invert data when RX\r\n                (0u << 9) |   // 1 = invert data when TX\r\n                (0u << 8) |   // ???\r\n                (0u << 4) |   // 0 ~ 15 preamble length selection .. mdc1200 does not send bit reversals :(\r\n                (1u << 3) |   // 0/1 sync length selection\r\n                (0u << 0);    // 0 ~ 7  ???\r\n\r\n        BK4819_WriteRegister(0x70,\r\n                             (0u << 15) |    // 0\r\n                             (0u << 8) |    // 0\r\n                             (1u << 7) |    // 1\r\n                             (96u << 0));    // 96\r\n\r\n        BK4819_WriteRegister(0x72, scale_freq(1200));\r\n\r\n        BK4819_WriteRegister(0x58,\r\n                             (1u << 13) |        // 1 FSK TX mode selection\r\n                             //   0 = FSK 1.2K and FSK 2.4K TX .. no tones, direct FM\r\n                             //   1 = FFSK 1200 / 1800 TX\r\n                             //   2 = ???\r\n                             //   3 = FFSK 1200 / 2400 TX\r\n                             //   4 = ???\r\n                             //   5 = NOAA SAME TX\r\n                             //   6 = ???\r\n                             //   7 = ???\r\n                             //\r\n                             (7u << 10) |        // 0 FSK RX mode selection\r\n                             //   0 = FSK 1.2K, FSK 2.4K RX and NOAA SAME RX .. no tones, direct FM\r\n                             //   1 = ???\r\n                             //   2 = ???\r\n                             //   3 = ???\r\n                             //   4 = FFSK 1200 / 2400 RX\r\n                             //   5 = ???\r\n                             //   6 = ???\r\n                             //   7 = FFSK 1200 / 1800 RX\r\n                             //\r\n                             (3u << 8) |            // 0 FSK RX gain\r\n                             //   0 ~ 3\r\n                             //\r\n                             (0u << 6) |            // 0 ???\r\n                             //   0 ~ 3\r\n                             //\r\n                             (0u << 4) |            // 0 FSK preamble type selection\r\n                             //   0 = 0xAA or 0x55 due to the MSB of FSK sync byte 0\r\n                             //   1 = ???\r\n                             //   2 = 0x55\r\n                             //   3 = 0xAA\r\n                             //\r\n                             (1u << 1) |            // 1 FSK RX bandwidth setting\r\n                             //   0 = FSK 1.2K .. no tones, direct FM\r\n                             //   1 = FFSK 1200 / 1800\r\n                             //   2 = NOAA SAME RX\r\n                             //   3 = ???\r\n                             //   4 = FSK 2.4K and FFSK 1200 / 2400\r\n                             //   5 = ???\r\n                             //   6 = ???\r\n                             //   7 = ???\r\n                             //\r\n                             (1u << 0));            // 1 FSK enable\r\n        //   0 = disable\r\n        //   1 = enable\r\n\r\n        // REG_5A .. bytes 0 & 1 sync pattern\r\n        //\r\n        // <15:8> sync byte 0\r\n        // < 7:0> sync byte 1\r\n//\t\t\tBK4819_WriteRegister(0x5A, ((uint16_t)mdc1200_sync_suc_xor[0] << 8) | (mdc1200_sync_suc_xor[1] << 0));\r\n        BK4819_WriteRegister(0x5A, 0x7240); //0x7240\r\n\r\n        // REG_5B .. bytes 2 & 3 sync pattern\r\n        //\r\n        // <15:8> sync byte 2\r\n        // < 7:0> sync byte 3\r\n//\t\t\tBK4819_WriteRegister(0x5B, ((uint16_t)mdc1200_sync_suc_xor[2] << 8) | (mdc1200_sync_suc_xor[3] << 0));\r\n        BK4819_WriteRegister(0x5B, 0x99a7);//0x99a7\r\n\r\n        // disable CRC\r\n        BK4819_WriteRegister(0x5C, 0x5625);   // 01010110 0 0 100101\r\n//\t\t\tBK4819_WriteRegister(0x5C, 0xAA30);   // 10101010 0 0 110000\r\n\r\n        // set the almost full threshold\r\n        BK4819_WriteRegister(0x5E, (64u << 3) | (1u << 0));  // 0 ~ 127, 0 ~ 7\r\n\r\n//\t\t\t{\t// packet size .. sync + 14 bytes - size of a single mdc1200 packet\r\n////\t\t\t\tuint16_t size = 1 + (MDC1200_FEC_K * 2);\r\n//\t\t\t\tuint16_t size = 0 + (MDC1200_FEC_K * 2);\r\n////\t\t\t\tsize -= (fsk_reg59 & (1u << 3)) ? 4 : 2;\r\n//\t\t\t\tsize = ((size + 1) / 2) * 2;             // round up to even, else FSK RX doesn't work\r\n//\t\t\t\tBK4819_WriteRegister(0x5D, ((size - 1) << 8));\r\n//\t\t\t}\r\n        {    // packet size .. sync + 14 bytes - size of a single packet\r\n\r\n            uint16_t size = 52;\r\n            // size -= (fsk_reg59 & (1u << 3)) ? 4 : 2;\r\n            size = (((size + 1) / 2) * 2) + 2;             // round up to even, else FSK RX doesn't work\r\n            BK4819_WriteRegister(0x5D, (size << 8));\r\n        }\r\n\r\n        // clear FIFO's then enable RX\r\n        BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59);\r\n        BK4819_WriteRegister(0x59, (1u << 12) | fsk_reg59);\r\n\r\n        // clear interrupt flags\r\n        BK4819_WriteRegister(0x02, 0);\r\n\r\n//\t\t\tBK4819_RX_TurnOn();\r\n\r\n        // enable interrupts\r\n//\t\t\tBK4819_WriteRegister(0x3F, BK4819_ReadRegister(0x3F) | BK4819_REG_3F_FSK_RX_SYNC | BK4819_REG_3F_FSK_RX_FINISHED | BK4819_REG_3F_FSK_FIFO_ALMOST_FULL);\r\n    } else {\r\n        BK4819_WriteRegister(0x70, 0);\r\n        BK4819_WriteRegister(0x58, 0);\r\n    }\r\n}\r\n"
  },
  {
    "path": "driver/bk4819.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_BK4819_h\r\n#define DRIVER_BK4819_h\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n#include \"driver/bk4819-regs.h\"\r\n\r\nenum BK4819_AF_Type_t\r\n{\r\n\tBK4819_AF_MUTE      =  0u,  //\r\n\tBK4819_AF_FM        =  1u,  // FM\r\n\tBK4819_AF_ALAM      =  2u,  //\r\n\tBK4819_AF_BEEP      =  3u,  //\r\n\tBK4819_AF_BASEBAND1 =  4u,  // RAW\r\n\tBK4819_AF_BASEBAND2 =  5u,  // USB\r\n\tBK4819_AF_CTCO      =  6u,  // strange LF audio .. maybe the CTCSS LF line ?\r\n\tBK4819_AF_AM        =  7u,  // AM\r\n\tBK4819_AF_FSKO      =  8u,  // nothing\r\n\tBK4819_AF_UNKNOWN3  =  9u,  // BYP\r\n\tBK4819_AF_UNKNOWN4  = 10u,  // nothing at all\r\n\tBK4819_AF_UNKNOWN5  = 11u,  // distorted\r\n\tBK4819_AF_UNKNOWN6  = 12u,  // distorted\r\n\tBK4819_AF_UNKNOWN7  = 13u,  // interesting\r\n\tBK4819_AF_UNKNOWN8  = 14u,  // interesting \r\n\tBK4819_AF_UNKNOWN9  = 15u   // not a lot\r\n};\r\n\r\ntypedef enum BK4819_AF_Type_t BK4819_AF_Type_t;\r\n\r\nenum BK4819_FilterBandwidth_t\r\n{\r\n\tBK4819_FILTER_BW_WIDE = 0,\r\n\tBK4819_FILTER_BW_NARROW,\r\n\tBK4819_FILTER_BW_NARROWER\r\n};\r\n\r\ntypedef enum BK4819_FilterBandwidth_t BK4819_FilterBandwidth_t;\r\n\r\nenum BK4819_CssScanResult_t\r\n{\r\n\tBK4819_CSS_RESULT_NOT_FOUND = 0,\r\n\tBK4819_CSS_RESULT_CTCSS,\r\n\tBK4819_CSS_RESULT_CDCSS\r\n};\r\n\r\ntypedef enum BK4819_CssScanResult_t BK4819_CssScanResult_t;\r\n\r\n// radio is asleep, not listening\r\nextern bool gRxIdleMode;\r\n\r\nvoid     BK4819_Init(void);\r\n\r\nuint16_t BK4819_ReadRegister(BK4819_REGISTER_t Register);\r\nvoid     BK4819_WriteRegister(BK4819_REGISTER_t Register, uint16_t Data);\r\nvoid     BK4819_SetRegValue(RegisterSpec s, uint16_t v);\r\nvoid     BK4819_WriteU8(uint8_t Data);\r\nvoid     BK4819_WriteU16(uint16_t Data);\r\n\r\nvoid     BK4819_SetAGC(bool enable);\r\nvoid BK4819_InitAGC(bool amModulation);\r\nvoid     BK4819_ToggleGpioOut(BK4819_GPIO_PIN_t Pin, bool bSet);\r\nint8_t   BK4819_GetRxGain_dB(void);\r\nint16_t  BK4819_GetRSSI_dBm(void);\r\nvoid     BK4819_SetCDCSSCodeWord(uint32_t CodeWord);\r\nvoid     BK4819_SetCTCSSFrequency(uint32_t BaudRate);\r\nvoid     BK4819_SetTailDetection(const uint32_t freq_10Hz);\r\nvoid     BK4819_EnableVox(uint16_t Vox1Threshold, uint16_t Vox0Threshold);\r\nvoid     BK4819_SetFilterBandwidth(const BK4819_FilterBandwidth_t Bandwidth, const bool weak_no_different);\r\nvoid     BK4819_SetupPowerAmplifier(const uint8_t bias, const uint32_t frequency);\r\nvoid     BK4819_SetFrequency(uint32_t Frequency);\r\nvoid     BK4819_SetupSquelch(\r\n\t\t\tuint8_t SquelchOpenRSSIThresh,\r\n\t\t\tuint8_t SquelchCloseRSSIThresh,\r\n\t\t\tuint8_t SquelchOpenNoiseThresh,\r\n\t\t\tuint8_t SquelchCloseNoiseThresh,\r\n\t\t\tuint8_t SquelchCloseGlitchThresh,\r\n\t\t\tuint8_t SquelchOpenGlitchThresh);\r\n\r\nvoid     BK4819_SetAF(BK4819_AF_Type_t AF);\r\nvoid     BK4819_RX_TurnOn(void);\r\nvoid     BK4819_PickRXFilterPathBasedOnFrequency(uint32_t Frequency);\r\nvoid     BK4819_DisableScramble(void);\r\nvoid     BK4819_EnableScramble(uint8_t Type);\r\n\r\nbool     BK4819_CompanderEnabled(void);\r\nvoid     BK4819_SetCompander(const unsigned int mode);\r\n\r\nvoid     BK4819_DisableVox(void);\r\nvoid     BK4819_DisableDTMF(void);\r\nvoid     BK4819_EnableDTMF(void);\r\nvoid     BK4819_PlayTone(uint16_t Frequency, bool bTuningGainSwitch);\r\nvoid     BK4819_PlaySingleTone(const unsigned int tone_Hz, const unsigned int delay, const unsigned int level, const bool play_speaker);\r\nvoid     BK4819_EnterTxMute(void);\r\nvoid     BK4819_ExitTxMute(void);\r\nvoid     BK4819_Sleep(void);\r\nvoid     BK4819_TurnsOffTones_TurnsOnRX(void);\r\n#ifdef ENABLE_AIRCOPY\r\n\tvoid     BK4819_SetupAircopy(void);\r\n#endif\r\nvoid     BK4819_ResetFSK(void);\r\nvoid     BK4819_ExitBypass(void);\r\nvoid     BK4819_PrepareTransmit(void);\r\nvoid     BK4819_TxOn_Beep(void);\r\nvoid     BK4819_ExitSubAu(void);\r\n\r\nvoid     BK4819_Conditional_RX_TurnOn_and_GPIO6_Enable(void);\r\n\r\nvoid     BK4819_EnterDTMF_TX(bool bLocalLoopback);\r\nvoid     BK4819_ExitDTMF_TX(bool bKeep);\r\nvoid     BK4819_EnableTXLink(void);\r\n\r\nvoid     BK4819_PlayDTMF(char Code);\r\nvoid     BK4819_PlayDTMFString(const char *pString, bool bDelayFirst, uint16_t FirstCodePersistTime, uint16_t HashCodePersistTime, uint16_t CodePersistTime, uint16_t CodeInternalTime);\r\n\r\nvoid     BK4819_TransmitTone(bool bLocalLoopback, uint32_t Frequency);\r\n\r\nvoid     BK4819_GenTail(uint8_t Tail);\r\nvoid     BK4819_PlayCDCSSTail(void);\r\nvoid     BK4819_PlayCTCSSTail(void);\r\n\r\nuint16_t BK4819_GetRSSI(void);\r\nuint8_t  BK4819_GetGlitchIndicator(void);\r\nuint8_t  BK4819_GetExNoiceIndicator(void);\r\nuint16_t BK4819_GetVoiceAmplitudeOut(void);\r\nuint8_t  BK4819_GetAfTxRx(void);\r\n\r\nbool     BK4819_GetFrequencyScanResult(uint32_t *pFrequency);\r\nBK4819_CssScanResult_t BK4819_GetCxCSSScanResult(uint32_t *pCdcssFreq, uint16_t *pCtcssFreq);\r\nvoid     BK4819_DisableFrequencyScan(void);\r\nvoid     BK4819_EnableFrequencyScan(void);\r\nvoid     BK4819_SetScanFrequency(uint32_t Frequency);\r\n\r\nvoid     BK4819_Disable(void);\r\n\r\nvoid     BK4819_StopScan(void);\r\n\r\nuint8_t  BK4819_GetDTMF_5TONE_Code(void);\r\n\r\nuint8_t  BK4819_GetCDCSSCodeType(void);\r\nuint8_t  BK4819_GetCTCShift(void);\r\nuint8_t  BK4819_GetCTCType(void);\r\n\r\nvoid     BK4819_SendFSKData(uint16_t *pData);\r\nvoid     BK4819_PrepareFSKReceive(void);\r\nvoid BK4819_PlayRoger(void);\r\n\r\n void    BK4819_PlayRogerNormal(void);\r\nvoid     BK4819_PlayRogerMDC(void);\r\n\t    \r\nvoid     BK4819_Enable_AfDac_DiscMode_TxDsp(void);\r\n\t    \r\nvoid     BK4819_GetVoxAmp(uint16_t *pResult);\r\nvoid     BK4819_SetScrambleFrequencyControlWord(uint32_t Frequency);\r\nvoid     BK4819_PlayDTMFEx(bool bLocalLoopback, char Code);\r\nvoid BK4819_send_MDC1200(const uint8_t op, const uint8_t arg, const uint16_t id, const bool long_preamble);\r\n\r\nvoid BK4819_stop_tones(const bool tx);\r\nvoid BK4819_start_tone(const uint16_t frequency, const unsigned int level, const bool tx, const bool tx_mute);\r\nvoid enable_msg_rx(const bool enable);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/crc.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"../bsp/dp32g030/crc.h\"\r\n#include \"crc.h\"\r\n\r\nvoid CRC_Init(void) {\r\n    CRC_CR =\r\n            CRC_CR_CRC_EN_BITS_DISABLE |\r\n            CRC_CR_INPUT_REV_BITS_NORMAL |\r\n            CRC_CR_INPUT_INV_BITS_BIT_INVERTED |\r\n            CRC_CR_OUTPUT_REV_BITS_REVERSED |\r\n            CRC_CR_OUTPUT_INV_BITS_BIT_INVERTED |\r\n            CRC_CR_DATA_WIDTH_BITS_8 |\r\n            CRC_CR_CRC_SEL_BITS_CRC_16_CCITT;\r\n\r\n    CRC_IV = 0;\r\n\r\n}\r\n\r\n\r\n#define CRC16_XMODEM_POLY 0x1021\r\n\r\nuint16_t CRC_Calculate1(void *pBuffer, uint16_t Size) {\r\n    uint8_t *pData = (uint8_t *) pBuffer;\r\n    uint16_t crc = 0; // 初始CRC值为0\r\n\r\n    while (Size--) {\r\n        crc ^= (*pData++) << 8; // 将数据字节的最高位与CRC异或\r\n        for (uint8_t i = 0; i < 8; i++) {\r\n            if (crc & 0x8000) { // 检查最高位是否为1\r\n                crc = (crc << 1) ^ CRC16_XMODEM_POLY; // 如果最高位为1，执行CRC多项式计算\r\n            } else {\r\n                crc = crc << 1; // 如果最高位为0，继续左移\r\n            }\r\n        }\r\n    }\r\n\r\n    return crc;\r\n}\r\n\r\nuint16_t compute_crc(const void *data, const unsigned int data_len) {    // let the CPU's hardware do some work :)\r\n    uint16_t crc;\r\n    CRC_Init();\r\n    crc = CRC_Calculate(data, data_len);\r\n    return crc;\r\n}\r\n\r\nuint16_t CRC_Calculate(const void *buffer, const unsigned int size) {\r\n    const uint8_t *data = (const uint8_t *) buffer;\r\n    uint16_t i;\r\n    uint16_t crc;\r\n\r\n    CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_ENABLE;\r\n\r\n    for (i = 0; i < size; i++)\r\n        CRC_DATAIN = data[i];\r\n    crc = (uint16_t) CRC_DATAOUT;\r\n\r\n    CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_DISABLE;\r\n\r\n    return crc;\r\n}\r\n"
  },
  {
    "path": "driver/crc.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_CRC_H\r\n#define DRIVER_CRC_H\r\n\r\n#include <stdint.h>\r\n\r\nvoid CRC_Init(void);\r\nuint16_t CRC_Calculate(const void *buffer, const unsigned int size);\r\nuint16_t CRC_Calculate1( void *pBuffer, uint16_t Size);\r\nuint16_t compute_crc(const void *data, const unsigned int data_len) ;    // let the CPU's hardware do some work :)\r\n\r\nvoid CRC_InitReverse(void);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/eeprom.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <stddef.h>\r\n#include <string.h>\r\n\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/i2c.h\"\r\n#include \"driver/system.h\"\r\n#include \"assert.h\"\r\n\r\n#ifdef ENABLE_FLASHLIGHT\r\n#include \"app/flashlight.h\"\r\n#endif\r\n\r\n#include <assert.h>\r\n#include <stdint.h>\r\n#include <string.h>\r\n#include \"app/action.h\"\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n#include \"app/aircopy.h\"\r\n#endif\r\n\r\n#include \"app/app.h\"\r\n#include \"app/chFrScanner.h\"\r\n#include \"app/dtmf.h\"\r\n#include \"driver/uart.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"app/generic.h\"\r\n#include \"app/main.h\"\r\n#include \"app/menu.h\"\r\n#include \"app/scanner.h\"\r\n\r\n#ifdef ENABLE_UART\r\n#include \"app/uart.h\"\r\n#endif\r\n\r\n#include \"ARMCM0.h\"\r\n#include \"audio.h\"\r\n#include \"board.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/backlight.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"driver/bk1080.h\"\r\n#endif\r\n\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/keyboard.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"driver/system.h\"\r\n#include \"am_fix.h\"\r\n//#include \"external/printf/printf.h\"\r\n#include \"frequencies.h\"\r\n#include \"functions.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"settings.h\"\r\n\r\n#if defined(ENABLE_OVERLAY)\r\n#include \"sram-overlay.h\"\r\n#endif\r\n#ifdef ENABLE_MESSENGER\r\n#include \"app/messenger.h\"\r\n#endif\r\n#ifdef ENABLE_DOPPLER\r\n#include \"app/doppler.h\"\r\n#endif\r\n\r\n#include \"ui/battery.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/main.h\"\r\n#include \"ui/menu.h\"\r\n#include \"ui/status.h\"\r\n#include \"ui/ui.h\"\r\n\r\n\r\n\r\nvoid EEPROM_ReadBuffer(uint32_t Address, void *pBuffer, uint8_t Size) {\r\n\r\n    __disable_irq();\r\n    I2C_Start();\r\n\r\n    uint8_t IIC_ADD =    0xA0 | Address >> 15 &14;\r\n\r\n    I2C_Write(IIC_ADD);\r\n    I2C_Write((Address >> 8) & 0xFF);\r\n    I2C_Write((Address >> 0) & 0xFF);\r\n\r\n    I2C_Start();\r\n\r\n    I2C_Write(IIC_ADD + 1);\r\n\r\n    I2C_ReadBuffer(pBuffer, Size);\r\n\r\n    I2C_Stop();\r\n    __enable_irq();\r\n\r\n}\r\n\r\nvoid EEPROM_WriteBuffer(uint32_t Address, const void *pBuffer, uint8_t WRITE_SIZE) {\r\n\r\n//    if (pBuffer == NULL)\r\n//        return;\r\n    uint8_t buffer[128];\r\n    EEPROM_ReadBuffer(Address, buffer, WRITE_SIZE);\r\n    if (memcmp(pBuffer, buffer, WRITE_SIZE) != 0) {\r\n        uint8_t IIC_ADD =    0xA0 | Address >> 15 &14;\r\n\r\n        I2C_Start();\r\n\r\n        I2C_Write(IIC_ADD);\r\n\r\n        I2C_Write((Address >> 8) & 0xFF);\r\n        I2C_Write((Address) & 0xFF);\r\n        I2C_WriteBuffer(pBuffer, WRITE_SIZE);\r\n        I2C_Stop();\r\n    }\r\n    SYSTEM_DelayMs(10);\r\n\r\n}\r\n\r\n\r\n"
  },
  {
    "path": "driver/eeprom.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_EEPROM_H\r\n#define DRIVER_EEPROM_H\r\n\r\n#include <stdint.h>\r\n\r\nvoid EEPROM_ReadBuffer(uint32_t Address, void *pBuffer, uint8_t Size);\r\n\r\nvoid EEPROM_WriteBuffer(uint32_t Address, const void *pBuffer, uint8_t WRITE_SIZE);\r\n\r\n\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/flash.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"driver/flash.h\"\r\n#include \"sram-overlay.h\"\r\n\r\nvoid FLASH_Init(FLASH_READ_MODE ReadMode) {\r\n    overlay_FLASH_Init(ReadMode);\r\n}\r\n\r\nvoid FLASH_ConfigureTrimValues(void) {\r\n    overlay_FLASH_ConfigureTrimValues();\r\n}\r\n\r\nuint32_t FLASH_ReadNvrWord(uint32_t Address) {\r\n    return overlay_FLASH_ReadNvrWord(Address);\r\n}\r\n"
  },
  {
    "path": "driver/flash.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_FLASH_H\r\n#define DRIVER_FLASH_H\r\n\r\n#include \"bsp/dp32g030/flash.h\"\r\n\r\nenum FLASH_READ_MODE {\r\n\tFLASH_READ_MODE_1_CYCLE = FLASH_CFG_READ_MD_VALUE_1_CYCLE,\r\n\tFLASH_READ_MODE_2_CYCLE = FLASH_CFG_READ_MD_VALUE_2_CYCLE,\r\n};\r\n\r\ntypedef enum FLASH_READ_MODE FLASH_READ_MODE;\r\n\r\nenum FLASH_MASK_SELECTION {\r\n\tFLASH_MASK_SELECTION_NONE = FLASH_MASK_SEL_VALUE_NONE,\r\n\tFLASH_MASK_SELECTION_2KB  = FLASH_MASK_SEL_VALUE_2KB,\r\n\tFLASH_MASK_SELECTION_4KB  = FLASH_MASK_SEL_VALUE_4KB,\r\n\tFLASH_MASK_SELECTION_8KB  = FLASH_MASK_SEL_VALUE_8KB,\r\n};\r\n\r\ntypedef enum FLASH_MASK_SELECTION FLASH_MASK_SELECTION;\r\n\r\nenum FLASH_MODE {\r\n\tFLASH_MODE_READ_AHB = FLASH_CFG_MODE_VALUE_READ_AHB,\r\n\tFLASH_MODE_PROGRAM  = FLASH_CFG_MODE_VALUE_PROGRAM,\r\n\tFLASH_MODE_ERASE    = FLASH_CFG_MODE_VALUE_ERASE,\r\n\tFLASH_MODE_READ_APB = FLASH_CFG_MODE_VALUE_READ_APB,\r\n};\r\n\r\ntypedef enum FLASH_MODE FLASH_MODE;\r\n\r\nenum FLASH_AREA {\r\n\tFLASH_AREA_MAIN = FLASH_CFG_NVR_SEL_VALUE_MAIN,\r\n\tFLASH_AREA_NVR  = FLASH_CFG_NVR_SEL_VALUE_NVR,\r\n};\r\n\r\ntypedef enum FLASH_AREA FLASH_AREA;\r\n\r\nvoid FLASH_Init(FLASH_READ_MODE ReadMode);\r\nvoid FLASH_ConfigureTrimValues(void);\r\nuint32_t FLASH_ReadNvrWord(uint32_t Address);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/gpio.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n\r\n\r\n"
  },
  {
    "path": "driver/gpio.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_GPIO_H\r\n#define DRIVER_GPIO_H\r\n\r\n#include <stdint.h>\r\n\r\nenum GPIOA_PINS {\r\n\tGPIOA_PIN_KEYBOARD_0 = 3,\r\n\tGPIOA_PIN_KEYBOARD_1 = 4,\r\n\tGPIOA_PIN_KEYBOARD_2 = 5,\r\n\tGPIOA_PIN_KEYBOARD_3 = 6,\r\n\tGPIOA_PIN_KEYBOARD_4 = 10, // Shared with I2C!\r\n\tGPIOA_PIN_KEYBOARD_5 = 11, // Shared with I2C!\r\n\tGPIOA_PIN_KEYBOARD_6 = 12, // Shared with voice chip!\r\n\tGPIOA_PIN_KEYBOARD_7 = 13, // Shared with voice chip!\r\n\r\n\tGPIOA_PIN_I2C_SCL    = 10, // Shared with keyboard!\r\n\tGPIOA_PIN_I2C_SDA    = 11, // Shared with keyboard!\r\n\r\n\tGPIOA_PIN_VOICE_0    = 12, // Shared with keyboard!\r\n\tGPIOA_PIN_VOICE_1    = 13  // Shared with keyboard!\r\n};\r\n\r\nenum GPIOB_PINS {\r\n\tGPIOB_PIN_BACKLIGHT  = 6,\r\n\r\n\tGPIOB_PIN_ST7565_A0  = 9,\r\n\tGPIOB_PIN_ST7565_RES = 11, // Shared with SWD!\r\n\r\n\tGPIOB_PIN_SWD_IO     = 11, // Shared with ST7565!\r\n\tGPIOB_PIN_SWD_CLK    = 14,\r\n\r\n\tGPIOB_PIN_BK1080     = 15\r\n};\r\n\r\nenum GPIOC_PINS {\r\n\tGPIOC_PIN_BK4819_SCN = 0,\r\n\tGPIOC_PIN_BK4819_SCL = 1,\r\n\tGPIOC_PIN_BK4819_SDA = 2,\r\n\r\n\tGPIOC_PIN_FLASHLIGHT = 3,\r\n\tGPIOC_PIN_AUDIO_PATH = 4,\r\n\tGPIOC_PIN_PTT        = 5\r\n};\r\n\r\nstatic inline void GPIO_ClearBit(volatile uint32_t *pReg, uint8_t Bit) {\r\n\t*pReg &= ~(1U << Bit);\r\n}\r\n\r\nstatic inline uint8_t GPIO_CheckBit(volatile uint32_t *pReg, uint8_t Bit) {\r\n\treturn (*pReg >> Bit) & 1U;\r\n}\r\n\r\nstatic inline void GPIO_FlipBit(volatile uint32_t *pReg, uint8_t Bit) {\r\n\t*pReg ^= 1U << Bit;\r\n}\r\n\r\nstatic inline void GPIO_SetBit(volatile uint32_t *pReg, uint8_t Bit) {\r\n\t*pReg |= 1U << Bit;\r\n}\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/i2c.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"bsp/dp32g030/portcon.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/i2c.h\"\r\n#include \"driver/systick.h\"\r\n\r\nvoid I2C_Start(void) {\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n    SYSTICK_DelayUs(1);\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n    SYSTICK_DelayUs(1);\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n}\r\n\r\nvoid I2C_Stop(void) {\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n    SYSTICK_DelayUs(1);\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n    SYSTICK_DelayUs(1);\r\n}\r\n\r\nuint8_t I2C_Read(bool bFinal) {\r\n    uint8_t i, Data;\r\n\r\n    PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE;\r\n    PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK;\r\n    GPIOA->DIR &= ~GPIO_DIR_11_MASK;\r\n\r\n    Data = 0;\r\n    for (i = 0; i < 8; i++) {\r\n        GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n        SYSTICK_DelayUs(1);\r\n        GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n        SYSTICK_DelayUs(1);\r\n        Data <<= 1;\r\n        SYSTICK_DelayUs(1);\r\n        if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA)) {\r\n            Data |= 1U;\r\n        }\r\n        GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n        SYSTICK_DelayUs(1);\r\n    }\r\n\r\n    PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK;\r\n    PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE;\r\n    GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT;\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n    if (bFinal) {\r\n        GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n    } else {\r\n        GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n    }\r\n    SYSTICK_DelayUs(1);\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n\r\n    return Data;\r\n}\r\n\r\nint I2C_Write(uint8_t Data) {\r\n    uint8_t i;\r\n    int ret = -1;\r\n\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n    for (i = 0; i < 8; i++) {\r\n        if ((Data & 0x80) == 0) {\r\n            GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n        } else {\r\n            GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n        }\r\n        Data <<= 1;\r\n        SYSTICK_DelayUs(1);\r\n        GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n        SYSTICK_DelayUs(1);\r\n        GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n        SYSTICK_DelayUs(1);\r\n    }\r\n\r\n    PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE;\r\n    PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK;\r\n    GPIOA->DIR &= ~GPIO_DIR_11_MASK;\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n    SYSTICK_DelayUs(1);\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n\r\n    for (i = 0; i < 255; i++) {\r\n        if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA) == 0) {\r\n            ret = 0;\r\n            break;\r\n        }\r\n    }\r\n\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);\r\n    SYSTICK_DelayUs(1);\r\n    PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK;\r\n    PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE;\r\n    GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT;\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);\r\n\r\n    return ret;\r\n}\r\n\r\nint I2C_ReadBuffer(void *pBuffer, uint8_t Size) {\r\n    uint8_t *pData = (uint8_t *) pBuffer;\r\n    uint8_t i;\r\n\r\n    if (Size == 1) {\r\n        *pData = I2C_Read(true);\r\n        return 1;\r\n    }\r\n\r\n    for (i = 0; i < Size - 1; i++) {\r\n        SYSTICK_DelayUs(1);\r\n        pData[i] = I2C_Read(false);\r\n    }\r\n\r\n    SYSTICK_DelayUs(1);\r\n    pData[i++] = I2C_Read(true);\r\n\r\n    return Size;\r\n}\r\n\r\nint I2C_WriteBuffer(const void *pBuffer, uint8_t Size) {\r\n    const uint8_t *pData = (const uint8_t *) pBuffer;\r\n    uint8_t i;\r\n\r\n    for (i = 0; i < Size; i++) {\r\n        if (I2C_Write(*pData++) < 0) {\r\n            return -1;\r\n        }\r\n    }\r\n\r\n    return 0;\r\n}\r\n\r\n"
  },
  {
    "path": "driver/i2c.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_I2C_H\r\n#define DRIVER_I2C_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\nenum {\r\n\tI2C_WRITE = 0U,\r\n\tI2C_READ = 1U,\r\n};\r\n\r\nvoid I2C_Start(void);\r\nvoid I2C_Stop(void);\r\n\r\nuint8_t I2C_Read(bool bFinal);\r\nint I2C_Write(uint8_t Data);\r\n\r\nint I2C_ReadBuffer(void *pBuffer, uint8_t Size);\r\nint I2C_WriteBuffer(const void *pBuffer, uint8_t Size);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/keyboard.c",
    "content": "/* Copyright 2023 Manuel Jinger\r\n * Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/keyboard.h\"\r\n#include \"driver/systick.h\"\r\n#include \"driver/i2c.h\"\r\n#include \"misc.h\"\r\n\r\nKEY_Code_t gKeyReading0 = KEY_INVALID;\r\nKEY_Code_t gKeyReading1 = KEY_INVALID;\r\nuint16_t gDebounceCounter = 0;\r\nbool gWasFKeyPressed = false;\r\n#ifdef ENABLE_DOCK\r\nKEY_Code_t gSimulateKey     = KEY_INVALID;\r\n    KEY_Code_t gSimulateHold     = KEY_INVALID;\r\n    uint8_t gDebounceDefeat = 0;\r\n#endif\r\nstatic const struct {\r\n\r\n    // Using a 16 bit pre-calculated shift and invert is cheaper\r\n    // than using 8 bit and doing shift and invert in code.\r\n    uint16_t set_to_zero_mask;\r\n\r\n    // We are very fortunate.\r\n    // The key and pin defines fit together in a single u8, making this very efficient\r\n    struct {\r\n        KEY_Code_t key: 5;\r\n        uint8_t pin: 3; // Pin 6 is highest\r\n    } pins[4];\r\n\r\n} keyboard[] = {\r\n\r\n        {    // Zero row\r\n                // Set to zero to handle special case of nothing pulled down\r\n                .set_to_zero_mask = 0xffff,\r\n                .pins = {\r\n                        {.key = KEY_SIDE1, .pin = GPIOA_PIN_KEYBOARD_0},\r\n                        {.key = KEY_SIDE2, .pin = GPIOA_PIN_KEYBOARD_1},\r\n\r\n                        // Duplicate to fill the array with valid values\r\n                        {.key = KEY_INVALID, .pin = GPIOA_PIN_KEYBOARD_1},\r\n                        {.key = KEY_INVALID, .pin = GPIOA_PIN_KEYBOARD_1}\r\n                }\r\n        },\r\n        {    // First row\r\n                .set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_4) & 0xffff,\r\n                .pins = {\r\n                        {.key = KEY_MENU, .pin = GPIOA_PIN_KEYBOARD_0},\r\n                        {.key = KEY_1, .pin = GPIOA_PIN_KEYBOARD_1},\r\n                        {.key = KEY_4, .pin = GPIOA_PIN_KEYBOARD_2},\r\n                        {.key = KEY_7, .pin = GPIOA_PIN_KEYBOARD_3}\r\n                }\r\n        },\r\n        {    // Second row\r\n                .set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_5) & 0xffff,\r\n                .pins = {\r\n                        {.key = KEY_UP, .pin = GPIOA_PIN_KEYBOARD_0},\r\n                        {.key = KEY_2, .pin = GPIOA_PIN_KEYBOARD_1},\r\n                        {.key = KEY_5, .pin = GPIOA_PIN_KEYBOARD_2},\r\n                        {.key = KEY_8, .pin = GPIOA_PIN_KEYBOARD_3}\r\n                }\r\n        },\r\n        {    // Third row\r\n                .set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_6) & 0xffff,\r\n                .pins = {\r\n                        {.key = KEY_DOWN, .pin = GPIOA_PIN_KEYBOARD_0},\r\n                        {.key = KEY_3, .pin = GPIOA_PIN_KEYBOARD_1},\r\n                        {.key = KEY_6, .pin = GPIOA_PIN_KEYBOARD_2},\r\n                        {.key = KEY_9, .pin = GPIOA_PIN_KEYBOARD_3}\r\n                }\r\n        },\r\n        {    // Fourth row\r\n                .set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_7) & 0xffff,\r\n                .pins = {\r\n                        {.key = KEY_EXIT, .pin = GPIOA_PIN_KEYBOARD_0},\r\n                        {.key = KEY_STAR, .pin = GPIOA_PIN_KEYBOARD_1},\r\n                        {.key = KEY_0, .pin = GPIOA_PIN_KEYBOARD_2},\r\n                        {.key = KEY_F, .pin = GPIOA_PIN_KEYBOARD_3}\r\n                }\r\n        }\r\n};\r\n\r\nKEY_Code_t KEYBOARD_Poll(void) {\r\n\r\n#ifdef ENABLE_DOCK\r\n    if(gSimulateKey != KEY_INVALID)\r\n        {\r\n            const KEY_Code_t temp = gSimulateKey;\r\n            if(gDebounceDefeat++ >= 5)\r\n                gSimulateKey = KEY_INVALID;\r\n            return temp;\r\n        }\r\n        if(gSimulateHold != KEY_INVALID)\r\n        {\r\n            return gSimulateHold;\r\n        }\r\n#endif\r\n\r\n    KEY_Code_t Key = KEY_INVALID;\r\n\r\n//\tif (!GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT))\r\n//\t\treturn KEY_PTT;\r\n\r\n    // *****************\r\n\r\n    for (unsigned int j = 0; j < ARRAY_SIZE(keyboard); j++) {\r\n        uint16_t reg;\r\n        unsigned int i;\r\n        unsigned int k;\r\n\r\n        // Set all high\r\n        GPIOA->DATA |= 1u << GPIOA_PIN_KEYBOARD_4 |\r\n                       1u << GPIOA_PIN_KEYBOARD_5 |\r\n                       1u << GPIOA_PIN_KEYBOARD_6 |\r\n                       1u << GPIOA_PIN_KEYBOARD_7;\r\n\r\n        // Clear the pin we are selecting\r\n        GPIOA->DATA &= keyboard[j].set_to_zero_mask;\r\n\r\n        // Read all 4 GPIO pins at once .. with de-noise, max of 8 sample loops\r\n        for (i = 0, k = 0, reg = 0; i < 3 && k < 8; i++, k++) {\r\n            SYSTICK_DelayUs(1);\r\n            uint16_t reg2 = GPIOA->DATA;\r\n            i *= reg == reg2;\r\n            reg = reg2;\r\n        }\r\n        if (i < 3)\r\n            break;    // noise is too bad\r\n\r\n        for (unsigned int i = 0; i < ARRAY_SIZE(keyboard[j].pins); i++) {\r\n            const uint16_t mask = 1u << keyboard[j].pins[i].pin;\r\n            if (!(reg & mask)) {\r\n                Key = keyboard[j].pins[i].key;\r\n                break;\r\n            }\r\n        }\r\n\r\n        if (Key != KEY_INVALID)\r\n            break;\r\n    }\r\n\r\n    // Create I2C stop condition since we might have toggled I2C pins\r\n    // This leaves GPIOA_PIN_KEYBOARD_4 and GPIOA_PIN_KEYBOARD_5 high\r\n//    I2C_Stop();\r\n\r\n    // Reset VOICE pins\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_KEYBOARD_6);\r\n    GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_KEYBOARD_7);\r\n\r\n    return Key;\r\n}\r\n\r\nKEY_Code_t GetKey() {\r\n    KEY_Code_t btn = KEYBOARD_Poll();\r\n    if (btn == KEY_INVALID && !GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT)) {\r\n        btn = KEY_PTT;\r\n    }\r\n    return btn;\r\n}"
  },
  {
    "path": "driver/keyboard.h",
    "content": "/* Copyright 2023 Manuel Jinger\r\n * Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_KEYBOARD_H\r\n#define DRIVER_KEYBOARD_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\nenum KEY_Code_e {\r\n\tKEY_0 = 0,  // 0\r\n\tKEY_1,      // 1\r\n\tKEY_2,      // 2\r\n\tKEY_3,      // 3\r\n\tKEY_4,      // 4\r\n\tKEY_5,      // 5\r\n\tKEY_6,      // 6\r\n\tKEY_7,      // 7\r\n\tKEY_8,      // 8\r\n\tKEY_9,      // 9\r\n\tKEY_MENU,   // A\r\n\tKEY_UP,     // B\r\n\tKEY_DOWN,   // C\r\n\tKEY_EXIT,   // D\r\n\tKEY_STAR,   // *\r\n\tKEY_F,      // #\r\n\tKEY_PTT,    //\r\n\tKEY_SIDE2,  //\r\n\tKEY_SIDE1,  //\r\n\tKEY_INVALID //\r\n};\r\ntypedef enum KEY_Code_e KEY_Code_t;\r\n\r\nextern KEY_Code_t gKeyReading0;\r\nextern KEY_Code_t gKeyReading1;\r\nextern uint16_t   gDebounceCounter;\r\nextern bool       gWasFKeyPressed;\r\n\r\nKEY_Code_t KEYBOARD_Poll(void);\r\nKEY_Code_t GetKey() ;\r\n#ifdef ENABLE_DOCK\r\nextern KEY_Code_t gSimulateKey;\r\n\textern KEY_Code_t gSimulateHold;\r\n\textern uint8_t gDebounceDefeat;\r\n#endif\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/rtc.c",
    "content": "//\n// Created by RUPC on 2024/1/30.\n//\n#include \"bsp/dp32g030/rtc.h\"\n#include \"ARMCM0.h\"\n#include \"driver/eeprom.h\"\n#include \"driver/system.h\"\n#include \"ui/helper.h\"\n\nuint8_t time[6];\n\nvoid RTC_INIT() {\n\n    uint32_t correct_freq = 32768 - 1 + ((((RC_FREQ_DELTA & 0x400) >> 10) ? 1 : -1) * (RC_FREQ_DELTA & 0x3ff));\n    // 清空PRE_PERIOD, PRE_DECIMAL 和 PRE_ROUND相关位\n    RTC_PRE &= ~((0x7fff << 0) | (0xf << 20) | (0x1 << 24));\n    RTC_PRE |= correct_freq//PRE_ROUND=32768HZ-1\n               | (0 << 20)//DECIMAL=0\n               | (0 << 24);//PRE_PERIOD=8s\n\n\n    EEPROM_ReadBuffer(0X2BC0, time, 6);\n\n    RTC_Set();\n\n    NVIC_SetPriority(Interrupt2_IRQn, 0);\n\n\n    RTC_IF |= (1 << 0);//清除中断标志位\n    RTC_IE |= (1 << 0);//使能秒中断\n\n    RTC_CFG |= //(1 << 2)|//打开设置时间功能\n            (1 << 0);//RTC使能\n\n    NVIC_EnableIRQ(Interrupt2_IRQn);\n\n\n}\n\nvoid RTC_Set() {\n\n\n    RTC_DR = (2 << 24)//day 2\n             | (time[0] / 10 << 20)//YEAR TEN\n             | (time[0] % 10 << 16) //YEAR ONE\n             | (time[1] / 10 << 12)//MONTH TEN\n             | (time[1] % 10 << 8)//MONTH ONE\n             | (time[2] / 10 << 4)//DAY TEN\n             | (time[2] % 10 << 0);//DAY ONE\n    RTC_TR = (time[3] / 10 << 20) //h十位\n             | (time[3] % 10 << 16)//h个位\n             | (time[4] / 10 << 12)//min十位\n             | (time[4] % 10 << 8)//min个位\n             | (time[5] / 10 << 4)//sec十位\n             | (time[5] % 10 << 0);//sec个位\n    RTC_CFG |= (1 << 2);//打开设置时间功能\n\n}\n\nvoid RTC_Get() {\n    time[0] = (RTC_TSDR >> 20 & 0b1111) * 10 + (RTC_TSDR >> 16 & 0b1111);\n    time[1] = (RTC_TSDR >> 12 & 0b1) * 10 + (RTC_TSDR >> 8 & 0b1111);\n    time[2] = (RTC_TSDR >> 4 & 0b1111) * 10 + (RTC_TSDR >> 0 & 0b1111);\n\n    time[3] = (RTC_TSTR >> 20 & 0b111) * 10 + (RTC_TSTR >> 16 & 0b1111);\n    time[4] = (RTC_TSTR >> 12 & 0b111) * 10 + (RTC_TSTR >> 8 & 0b1111);\n    time[5] = (RTC_TSTR >> 4 & 0b111) * 10 + (RTC_TSTR >> 0 & 0b1111);\n\n}\n"
  },
  {
    "path": "driver/si473x.c",
    "content": "#include \"si473x.h\"\n#include \"../settings.h\"\n#include \"../audio.h\"\n#include \"eeprom.h\"\n#include \"gpio.h\"\n#include \"i2c.h\"\n#include \"system.h\"\n#include \"systick.h\"\n\nstatic const uint8_t SI47XX_I2C_ADDR = 0x22;\n\n#define RST_HIGH GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_BK1080)\n#define RST_LOW GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_BK1080)\n\nRSQStatus rsqStatus;\nSsbMode currentSsbMode;\n uint16_t divider = 1000;\n\nSI47XX_MODE si4732mode = SI47XX_FM;\nuint16_t siCurrentFreq = 10210;\n\nvoid SI47XX_ReadBuffer(uint8_t *buf, uint8_t size) {\n  I2C_Start();\n  I2C_Write(SI47XX_I2C_ADDR + 1);\n  I2C_ReadBuffer(buf, size);\n  I2C_Stop();\n}\n\nvoid SI47XX_WriteBuffer(uint8_t *buf, uint8_t size) {\n  I2C_Start();\n  I2C_Write(SI47XX_I2C_ADDR);\n  I2C_WriteBuffer(buf, size);\n  I2C_Stop();\n}\n\nbool SI47XX_IsSSB() {\n  return si4732mode == SI47XX_USB || si4732mode == SI47XX_LSB;\n}\n\nvoid waitToSend() {\n  uint8_t tmp = 0;\n  SI47XX_ReadBuffer((uint8_t *)&tmp, 1);\n  while (!(tmp & STATUS_CTS)) {\n    SYSTICK_DelayUs(1);\n    SI47XX_ReadBuffer((uint8_t *)&tmp, 1);\n  }\n}\n\n\nvoid sendProperty(uint16_t prop, uint16_t parameter) {\n  waitToSend();\n  uint8_t tmp[6] = {CMD_SET_PROPERTY, 0, prop >> 8, prop & 0xff, parameter >> 8,\n                    parameter & 0xff};\n  SI47XX_WriteBuffer(tmp, 6);\n  SYSTEM_DelayMs(10); // irrespective of CTS coming up earlier than that\n}\n\nuint16_t getProperty(uint16_t prop, bool *valid) {\n  uint8_t response[4] = {0};\n  uint8_t tmp[4] = {CMD_GET_PROPERTY, 0, prop >> 8, prop & 0xff};\n  waitToSend();\n  SI47XX_WriteBuffer(tmp, 4);\n  SI47XX_ReadBuffer(response, 4);\n\n  if (valid) {\n    *valid = !(response[0] & STATUS_ERR);\n  }\n\n  return (response[2] << 8) | response[3];\n}\n\nvoid RSQ_GET() {\n  uint8_t cmd[2] = {CMD_FM_RSQ_STATUS, 0x01};\n  if (si4732mode != SI47XX_FM) {\n    cmd[0] = CMD_AM_RSQ_STATUS;\n  }\n\n  waitToSend();\n  SI47XX_WriteBuffer(cmd, 2);\n  SI47XX_ReadBuffer(rsqStatus.raw, si4732mode == SI47XX_FM ? 8 : 6);\n}\n\nvoid setVolume(uint8_t volume) {\n  if (volume < 0)\n    volume = 0;\n  if (volume > 63)\n    volume = 63;\n  sendProperty(PROP_RX_VOLUME, volume);\n}\n\nvoid setAvcAmMaxGain(uint8_t gain) {\n  if (gain < 12 || gain > 90)\n    return;\n  sendProperty(PROP_AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN, gain * 340);\n}\n\nvoid enableRDS(void) {\n  // Enable and configure RDS reception\n  if (si4732mode == SI47XX_FM) {\n    sendProperty(PROP_FM_RDS_INT_SOURCE, FLG_RDSRECV);\n    // Set the FIFO high-watermark to 12 RDS blocks, which is safe even for\n    // old chips, yet large enough to improve performance.\n    sendProperty(PROP_FM_RDS_INT_FIFO_COUNT, 12);\n    sendProperty(\n        PROP_FM_RDS_CONFIG,\n        ((FLG_BLETHA_35 | FLG_BLETHB_35 | FLG_BLETHC_35 | FLG_BLETHD_35) << 8) |\n            FLG_RDSEN);\n  };\n}\n\nvoid SI47XX_SetAutomaticGainControl(uint8_t AGCDIS, uint8_t AGCIDX) {\n  SI47XX_AgcOverrride agc;\n\n  uint8_t cmd;\n\n  if (si4732mode == SI47XX_FM)\n    cmd = CMD_FM_AGC_OVERRIDE;\n  else\n    cmd = CMD_AM_AGC_OVERRIDE; // both for AM and SSB\n\n  agc.arg.DUMMY = 0; // ARG1: bits 7:1 Always write to 0;\n  agc.arg.AGCDIS = AGCDIS;\n  agc.arg.AGCIDX = AGCIDX;\n\n  waitToSend();\n\n  uint8_t cmd2[] = {cmd, agc.raw[0], agc.raw[1]};\n  SI47XX_WriteBuffer(cmd2, 3);\n}\n\n\nbool FreqCheck(uint32_t f) {\n    if (si4732mode == SI47XX_FM) {\n        if (f < 6400000 || f > 10800000) {\n            return false;\n        }\n    } else {\n        if (f < 15000 || f > 3000000) {\n            return false;\n        }\n    }\n    return true;\n}\nuint32_t Read_FreqSaved()\n{\n    uint32_t tmpF;\n    EEPROM_ReadBuffer(SI4732_FREQ_ADD + si4732mode * 4, (uint8_t *) &tmpF, 4);\n    if (!FreqCheck(tmpF)) {\n        if (si4732mode == SI47XX_FM) {\n            tmpF=10210000;\n        } else if (si4732mode == SI47XX_AM) {\n            tmpF=720000;\n        } else {\n            tmpF= 711300;\n        }\n    }\n    return tmpF;\n\n}\nvoid SI47XX_PowerUp() {\n  RST_HIGH;\n\n  uint8_t cmd[3] = {CMD_POWER_UP, FLG_XOSCEN | FUNC_FM, OUT_ANALOG};\n  if (si4732mode == SI47XX_AM) {\n    cmd[1] = FLG_XOSCEN | FUNC_AM;\n  }\n  waitToSend();\n  SI47XX_WriteBuffer(cmd, 3);\n  SYSTEM_DelayMs(500);\n\n    AUDIO_AudioPathOn();\n  setVolume(63);\n\n  if (si4732mode == SI47XX_FM) {\n    enableRDS();\n  } else if (si4732mode == SI47XX_AM) {\n    SI47XX_SetAutomaticGainControl(1, 0);\n    sendProperty(PROP_AM_SOFT_MUTE_MAX_ATTENUATION, 0);\n    sendProperty(PROP_AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN, 0x7800);\n    SI47XX_SetSeekAmLimits(1800, 30000);\n  }\n  SI47XX_SetFreq(  Read_FreqSaved()/divider);\n}\n\nvoid SI47XX_SsbSetup(SI47XX_SsbFilterBW AUDIOBW, uint8_t SBCUTFLT,\n                     uint8_t AVC_DIVIDER, uint8_t AVCEN, uint8_t SMUTESEL,\n                     uint8_t DSP_AFCDIS) {\n  currentSsbMode.param.SBCUTFLT = SBCUTFLT;\n  currentSsbMode.param.AVC_DIVIDER = AVC_DIVIDER;\n  currentSsbMode.param.AVCEN = AVCEN;\n  currentSsbMode.param.SMUTESEL = SMUTESEL;\n  currentSsbMode.param.DSP_AFCDIS = DSP_AFCDIS;\n  currentSsbMode.param.AUDIOBW = AUDIOBW;\n  sendProperty(PROP_SSB_MODE,\n               (currentSsbMode.raw[1] << 8) | currentSsbMode.raw[0]);\n}\n\nbool SI47XX_downloadPatch() {\n    uint8_t buf[248];\n//    const uint8_t PAGE_SIZE = SETTINGS_GetPageSize();\n    const uint32_t EEPROM_SIZE = 262144;\n    const uint32_t PATCH_START = EEPROM_SIZE - PATCH_SIZE;\n    for (uint16_t offset = 0; offset < PATCH_SIZE; offset += 248) {\n        uint32_t eepromN = PATCH_SIZE - offset > 248 ? 248 : PATCH_SIZE - offset;\n        EEPROM_ReadBuffer(PATCH_START + offset, buf, eepromN);\n        for (uint8_t i = 0; i < eepromN; i += 8) {\n            waitToSend();\n            SI47XX_WriteBuffer(buf + i, 8);\n        }\n    }\n    return true;\n}\nvoid SI47XX_PatchPowerUp() {\n    RST_HIGH;\n\n    uint8_t cmd[3] = {CMD_POWER_UP, 0b00110001, OUT_ANALOG};\n    waitToSend();\n    SI47XX_WriteBuffer(cmd, 3);\n    SYSTEM_DelayMs(550);\n\n    SI47XX_downloadPatch();\n\n    SI47XX_SsbSetup(2, 1, 0, 1, 0, 1);\n\n    AUDIO_AudioPathOn();\n    setVolume(63);\n\n    SI47XX_SetFreq(Read_FreqSaved()/divider);\n    sendProperty(PROP_SSB_SOFT_MUTE_MAX_ATTENUATION, 0);\n    sendProperty(PROP_AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN, 0x7800);\n}\n\nvoid SI47XX_SetSsbBandwidth(SI47XX_SsbFilterBW bw) {\n  SI47XX_SsbSetup(bw, 1, 0, 1, 0, 1);\n}\n\nvoid SI47XX_Seek(bool up, bool wrap) {\n  uint8_t seekOpt = (up ? FLG_SEEKUP : 0) | (wrap ? FLG_WRAP : 0);\n  uint8_t cmd[6] = {CMD_FM_SEEK_START, seekOpt, 0x00, 0x00, 0x00, 0x00};\n\n  if (si4732mode == SI47XX_AM) {\n    cmd[0] = CMD_AM_SEEK_START;\n    cmd[5] = (siCurrentFreq > 1800) ? 1 : 0;\n  }\n\n  waitToSend();\n  SI47XX_WriteBuffer(cmd, si4732mode == SI47XX_FM ? 2 : 6);\n}\n\nuint16_t SI47XX_getFrequency(bool *valid) {\n  uint8_t response[4] = {0};\n  uint8_t cmd[1] = {CMD_FM_TUNE_STATUS};\n\n  if (si4732mode == SI47XX_AM) {\n    cmd[0] = CMD_AM_TUNE_STATUS;\n  }\n\n  waitToSend();\n  SI47XX_WriteBuffer(cmd, 1);\n  SI47XX_ReadBuffer(response, 4);\n\n  if (valid) {\n    *valid = (response[1] & STATUS_VALID);\n  }\n\n  return (response[2] << 8) | response[3];\n}\n\nvoid SI47XX_PowerDown() {\n    AUDIO_AudioPathOff();\n  uint8_t cmd[1] = {CMD_POWER_DOWN};\n\n  waitToSend();\n  SI47XX_WriteBuffer(cmd, 1);\n  SYSTICK_Delay250ns(10);\n  RST_LOW;\n}\n\nvoid SI47XX_SwitchMode(SI47XX_MODE mode) {\n    if (si4732mode != mode) {\n        bool wasSSB = SI47XX_IsSSB();\n        si4732mode = mode;\n        if (mode == SI47XX_USB || mode == SI47XX_LSB) {\n            if (!wasSSB) {\n                SI47XX_PowerDown();\n                SI47XX_PatchPowerUp();\n            }\n        } else {\n            SI47XX_PowerDown();\n            SI47XX_PowerUp();\n        }\n    }\n}\n\nvoid SI47XX_SetFreq(uint16_t freq) {\n  uint8_t hb = (freq >> 8) & 0xFF;\n  uint8_t lb = freq & 0xFF;\n\n  bool isSW = freq > 1800;\n\n  uint8_t size = 4;\n  uint8_t cmd[6] = {CMD_FM_TUNE_FREQ, 0x00, hb, lb, 0, 0};\n\n  if (si4732mode == SI47XX_FM || si4732mode == SI47XX_AM) {\n    cmd[1] = 0x01; // FAST\n  }\n\n  if (si4732mode == SI47XX_AM) {\n    cmd[0] = CMD_AM_TUNE_FREQ;\n    size = 5;\n  }\n\n  if (SI47XX_IsSSB()) {\n    cmd[0] = CMD_AM_TUNE_FREQ; // same as AM 0x40\n    if (si4732mode == SI47XX_USB) {\n      cmd[1] = 0b10000000;\n    } else {\n      cmd[1] = 0b01000000;\n    }\n    size = 6;\n  }\n\n  if (si4732mode != SI47XX_FM) {\n    if (isSW) {\n      cmd[5] = 1;\n    }\n  }\n\n  waitToSend();\n  SI47XX_WriteBuffer(cmd, size);\n  siCurrentFreq = freq;\n\n  SYSTEM_DelayMs(30);\n  // RSQ_GET();\n}\n\nvoid SI47XX_SetAMFrontendAGC(uint8_t minGainIdx, uint8_t attnBackup) {\n  sendProperty(PROP_AM_FRONTEND_AGC_CONTROL, minGainIdx << 8 | attnBackup);\n}\n\nvoid SI47XX_SetBandwidth(SI47XX_FilterBW AMCHFLT, bool AMPLFLT) {\n  SI47XX_BW_Config cfg = {0};\n  cfg.param.AMCHFLT = AMCHFLT;\n  cfg.param.AMPLFLT = AMPLFLT;\n  sendProperty(PROP_AM_CHANNEL_FILTER, (cfg.raw[1] << 8) | cfg.raw[0]);\n}\n\nvoid SI47XX_ReadRDS(uint8_t buf[13]) {\n  uint8_t cmd[2] = {CMD_FM_RDS_STATUS, RDS_STATUS_ARG1_CLEAR_INT};\n  waitToSend();\n  SI47XX_WriteBuffer(cmd, 2);\n  SI47XX_ReadBuffer(buf, 13);\n}\n\nvoid SI47XX_SetSeekFmLimits(uint16_t bottom, uint16_t top) {\n  sendProperty(PROP_FM_SEEK_BAND_BOTTOM, bottom);\n  sendProperty(PROP_FM_SEEK_BAND_TOP, top);\n}\n\nvoid SI47XX_SetSeekAmLimits(uint16_t bottom, uint16_t top) {\n  sendProperty(PROP_AM_SEEK_BAND_BOTTOM, bottom);\n  sendProperty(PROP_AM_SEEK_BAND_TOP, top);\n}\n\nvoid SI47XX_SetSeekFmSpacing(uint16_t spacing) {\n  sendProperty(PROP_FM_SEEK_FREQ_SPACING, spacing);\n}\n\nvoid SI47XX_SetSeekAmSpacing(uint16_t spacing) {\n  sendProperty(PROP_AM_SEEK_FREQ_SPACING, spacing);\n}\n\nvoid SI47XX_SetSeekFmRssiThreshold(uint16_t value) {\n  sendProperty(PROP_FM_SEEK_TUNE_RSSI_THRESHOLD, value);\n}\n\nvoid SI47XX_SetSeekAmRssiThreshold(uint16_t value) {\n  sendProperty(PROP_AM_SEEK_TUNE_RSSI_THRESHOLD, value);\n}\n\nvoid SI47XX_SetBFO(int16_t bfo) { sendProperty(PROP_SSB_BFO, bfo); }\n"
  },
  {
    "path": "driver/si473x.h",
    "content": "#ifndef SI473X_H\n#define SI473X_H\n\n#include <stdbool.h>\n#include <stdint.h>\n\ntypedef enum {\n    SI47XX_FM,\n    SI47XX_AM,\n    SI47XX_LSB,\n    SI47XX_USB,\n    SI47XX_CW,\n} SI47XX_MODE;\n\ntypedef enum {\n    SI47XX_BW_6_kHz,\n    SI47XX_BW_4_kHz,\n    SI47XX_BW_3_kHz,\n    SI47XX_BW_2_kHz,\n    SI47XX_BW_1_kHz,\n    SI47XX_BW_1_8_kHz,\n    SI47XX_BW_2_5_kHz,\n} SI47XX_FilterBW;\n\ntypedef enum {\n    SI47XX_SSB_BW_1_2_kHz,\n    SI47XX_SSB_BW_2_2_kHz,\n    SI47XX_SSB_BW_3_kHz,\n    SI47XX_SSB_BW_4_kHz,\n    SI47XX_SSB_BW_0_5_kHz,\n    SI47XX_SSB_BW_1_0_kHz,\n} SI47XX_SsbFilterBW;\n\ntypedef enum {\n    CMD_POWER_UP = 0x01,\n    CMD_GET_REV = 0x10,\n    CMD_POWER_DOWN = 0x11,\n    CMD_SET_PROPERTY = 0x12,\n    CMD_GET_PROPERTY = 0x13,\n    CMD_GET_INT_STATUS = 0x14,\n    CMD_PATCH_ARGS = 0x15,\n    CMD_PATCH_DATA = 0x16,\n    CMD_FM_TUNE_FREQ = 0x20,\n    CMD_FM_SEEK_START = 0x21,\n    CMD_FM_TUNE_STATUS = 0x22,\n    CMD_FM_RSQ_STATUS = 0x23,\n    CMD_FM_RDS_STATUS = 0x24,\n    CMD_FM_AGC_STATUS = 0x27,\n    CMD_FM_AGC_OVERRIDE = 0x28,\n    CMD_TX_TUNE_FREQ = 0x30,\n    CMD_TX_TUNE_POWER = 0x31,\n    CMD_TX_TUNE_MEASURE = 0x32,\n    CMD_TX_TUNE_STATUS = 0x33,\n    CMD_TX_ASQ_STATUS = 0x34,\n    CMD_TX_RDS_BUF = 0x35,\n    CMD_TX_RDS_PS = 0x36,\n    CMD_AM_TUNE_FREQ = 0x40,\n    CMD_AM_SEEK_START = 0x41,\n    CMD_AM_TUNE_STATUS = 0x42,\n    CMD_AM_RSQ_STATUS = 0x43,\n    CMD_AM_AGC_STATUS = 0x47,\n    CMD_AM_AGC_OVERRIDE = 0x48,\n    CMD_WB_TUNE_FREQ = 0x50,\n    CMD_WB_TUNE_STATUS = 0x52,\n    CMD_WB_RSQ_STATUS = 0x53,\n    CMD_WB_SAME_STATUS = 0x54,\n    CMD_WB_ASQ_STATUS = 0x55,\n    CMD_WB_AGC_STATUS = 0x57,\n    CMD_WB_AGC_OVERRIDE = 0x58,\n    CMD_AUX_ASRC_START = 0x61,\n    CMD_AUX_ASQ_STATUS = 0x65,\n    CMD_GPIO_CTL = 0x80,\n    CMD_GPIO_SET = 0x81,\n} SI47XX_Commands;\n\ntypedef enum {\n    FLG_CTSIEN = 0x80,\n    FLG_GPO2IEN = 0x40,\n    FLG_PATCH = 0x20,\n    FLG_XOSCEN = 0x10,\n    FLG_FREEZE = 0x02,\n    FLG_FAST = 0x01,\n    FLG_SEEKUP = 0x08,\n    FLG_WRAP = 0x04,\n    FLG_CANCEL = 0x02,\n    FLG_INTACK = 0x01,\n    FLG_STATUSONLY = 0x04,\n    FLG_MTFIFO = 0x02,\n    FLG_GPO3OEN = 0x08,\n    FLG_GPO2OEN = 0x04,\n    FLG_GPO1OEN = 0x02,\n    FLG_GPO3LEVEL = 0x08,\n    FLG_GPO2LEVEL = 0x04,\n    FLG_GPO1LEVEL = 0x02,\n    FLG_BLETHA_0 = 0x00,\n    FLG_BLETHA_12 = 0x40,\n    FLG_BLETHA_35 = 0x80,\n    FLG_BLETHA_U = FLG_BLETHA_12 | FLG_BLETHA_35,\n    FLG_BLETHB_0 = FLG_BLETHA_0,\n    FLG_BLETHB_12 = 0x10,\n    FLG_BLETHB_35 = 0x20,\n    FLG_BLETHB_U = FLG_BLETHB_12 | FLG_BLETHB_35,\n    FLG_BLETHC_0 = FLG_BLETHA_0,\n    FLG_BLETHC_12 = 0x04,\n    FLG_BLETHC_35 = 0x08,\n    FLG_BLETHC_U = FLG_BLETHC_12 | FLG_BLETHC_35,\n    FLG_BLETHD_0 = FLG_BLETHA_0,\n    FLG_BLETHD_12 = 0x01,\n    FLG_BLETHD_35 = 0x02,\n    FLG_BLETHD_U = FLG_BLETHD_12 | FLG_BLETHD_35,\n    FLG_RDSEN = 0x01,\n    FLG_DEEMPH_NONE = 0x00,\n    FLG_DEEMPH_50 = 0x01,\n    FLG_DEEMPH_75 = 0x02,\n    FLG_RSQREP = 0x08,\n    FLG_RDSREP = 0x04,\n    FLG_STCREP = 0x01,\n    FLG_ERRIEN = 0x40,\n    FLG_RSQIEN = 0x08,\n    FLG_RDSIEN = 0x04,\n    FLG_STCIEN = 0x01,\n    FLG_RDSNEWBLOCKB = 0x20,\n    FLG_RDSNEWBLOCKA = 0x10,\n    FLG_RDSSYNCFOUND = 0x04,\n    FLG_RDSSYNCLOST = 0x02,\n    FLG_RDSRECV = 0x01,\n    FLG_GRPLOST = 0x04,\n    FLG_RDSSYNC = 0x01,\n    FLG_AMPLFLT = 0x01,\n    FLG_AMCHFLT_6KHZ = 0x00,\n    FLG_AMCHFLT_4KHZ = 0x01,\n    FLG_AMCHFLT_3KHZ = 0x02,\n    FLG_AMCHFLT_2KHZ = 0x03,\n    FLG_AMCHFLT_1KHZ = 0x04,\n    FLG_AMCHFLT_1KHZ8 = 0x05,\n    FLG_AMCHFLT_2KHZ5 = 0x06,\n} SI47XX_Flags;\n\n// Define Si4735 Function modes\ntypedef enum {\n    FUNC_FM = 0x00,\n    FUNC_AM = 0x01,\n    FUNC_VER = 0x0F,\n} SI47XX_FunctionModes;\n\n// Define Si4735 Output modes\ntypedef enum {\n    OUT_RDS = 0x00, // RDS only\n    OUT_ANALOG = 0x05,\n    OUT_DIGITAL1 = 0x0B, // DCLK, LOUT/DFS, ROUT/DIO\n    OUT_DIGITAL2 = 0xB0, // DCLK, DFS, DIO\n    OUT_BOTH = OUT_ANALOG | OUT_DIGITAL2,\n} SI47XX_OutputModes;\n\ntypedef union {\n    struct {\n        uint8_t AUDIOBW: 4;  //!<  0 = 1.2kHz (default); 1=2.2kHz; 2=3kHz; 3=4kHz;\n        //!<  4=500Hz; 5=1kHz\n        uint8_t SBCUTFLT: 4; //!<  SSB side band cutoff filter for band passand low\n        //!<  pass filter\n        uint8_t AVC_DIVIDER: 4; //!<  set 0 for SSB mode; set 3 for SYNC mode;\n        uint8_t AVCEN: 1;       //!<  SSB Automatic Volume Control (AVC) enable;\n        //!<  0=disable; 1=enable (default);\n        uint8_t SMUTESEL: 1;    //!<  SSB Soft-mute Based on RSSI or SNR\n        uint8_t DUMMY1: 1;      //!<  Always write 0;\n        uint8_t\n                DSP_AFCDIS: 1; //!<  0=SYNC MODE, AFC enable; 1=SSB MODE, AFC disable.\n    } param;\n    uint8_t raw[2];\n} SsbMode;\n\n// Define Si47xx Status flag masks (bits the chip fed us)\ntypedef enum {\n    STATUS_CTS = 0x80,\n    STATUS_ERR = 0x40,\n    STATUS_RSQINT = 0x08,\n    STATUS_RDSINT = 0x04,\n    STATUS_ASQINT = 0x02,\n    STATUS_STCINT = 0x01,\n    STATUS_BLTF = 0x80,\n    STATUS_AFCRL = 0x02,\n    STATUS_VALID = 0x01,\n    STATUS_BLENDINT = 0x80,\n    STATUS_MULTHINT = 0x20,\n    STATUS_MULTLINT = 0x10,\n    STATUS_SNRHINT = 0x08,\n    STATUS_SNRLINT = 0x04,\n    STATUS_RSSIHINT = 0x02,\n    STATUS_RSSILINT = 0x01,\n    STATUS_SMUTE = 0x08,\n    STATUS_PILOT = 0x80,\n    STATUS_OVERMOD = 0x04,\n    STATUS_IALH = 0x02,\n    STATUS_IALL = 0x01,\n} SI47XX_StatusFlagMasks;\n\n// Define Si47xx Property codes\ntypedef enum {\n    PROP_GPO_IEN = (uint16_t) 0x0001,\n    PROP_DIGITAL_INPUT_FORMAT = 0x0101,\n    PROP_DIGITAL_OUTPUT_FORMAT = 0x0102,\n    PROP_DIGITAL_INPUT_SAMPLE_RATE = 0x0103,\n    PROP_DIGITAL_OUTPUT_SAMPLE_RATE = 0x0104,\n    PROP_REFCLK_FREQ = 0x0201,\n    PROP_REFCLK_PRESCALE = 0x0202,\n    PROP_FM_DEEMPHASIS = 0x1100,\n    PROP_FM_CHANNEL_FILTER = 0x1102,\n    PROP_FM_BLEND_STEREO_THRESHOLD = 0x1105,\n    PROP_FM_BLEND_MONO_THRESHOLD = 0x1106,\n    PROP_FM_ANTENNA_INPUT = 0x1107,\n    PROP_FM_MAX_TUNE_ERROR = 0x1108,\n    PROP_FM_RSQ_INT_SOURCE = 0x1200,\n    PROP_FM_RSQ_SNR_HI_THRESHOLD = 0x1201,\n    PROP_FM_RSQ_SNR_LO_THRESHOLD = 0x1202,\n    PROP_FM_RSQ_RSSI_HI_THRESHOLD = 0x1203,\n    PROP_FM_RSQ_RSSI_LO_THRESHOLD = 0x1204,\n    PROP_FM_RSQ_MULTIPATH_HI_THRESHOLD = 0x1205,\n    PROP_FM_RSQ_MULTIPATH_LO_THRESHOLD = 0x1206,\n    PROP_FM_RSQ_BLEND_THRESHOLD = 0x1207,\n    PROP_FM_SOFT_MUTE_RATE = 0x1300,\n    PROP_FM_SOFT_MUTE_SLOPE = 0x1301,\n    PROP_FM_SOFT_MUTE_MAX_ATTENUATION = 0x1302,\n    PROP_FM_SOFT_MUTE_SNR_THRESHOLD = 0x1303,\n    PROP_FM_SOFT_MUTE_RELEASE_RATE = 0x1304,\n    PROP_FM_SOFT_MUTE_ATTACK_RATE = 0x1305,\n    PROP_FM_SEEK_BAND_BOTTOM = 0x1400,\n    PROP_FM_SEEK_BAND_TOP = 0x1401,\n    PROP_FM_SEEK_FREQ_SPACING = 0x1402,\n    PROP_FM_SEEK_TUNE_SNR_THRESHOLD = 0x1403,\n    PROP_FM_SEEK_TUNE_RSSI_THRESHOLD = 0x1404,\n    PROP_FM_RDS_INT_SOURCE = 0x1500,\n    PROP_FM_RDS_INT_FIFO_COUNT = 0x1501,\n    PROP_FM_RDS_CONFIG = 0x1502,\n    PROP_FM_RDS_CONFIDENCE = 0x1503,\n    PROP_FM_AGC_ATTACK_RATE = 0x1700,\n    PROP_FM_AGC_RELEASE_RATE = 0x1701,\n    PROP_FM_BLEND_RSSI_STEREO_THRESHOLD = 0x1800,\n    PROP_FM_BLEND_RSSI_MONO_THRESHOLD = 0x1801,\n    PROP_FM_BLEND_RSSI_ATTACK_RATE = 0x1802,\n    PROP_FM_BLEND_RSSI_RELEASE_RATE = 0x1803,\n    PROP_FM_BLEND_SNR_STEREO_THRESHOLD = 0x1804,\n    PROP_FM_BLEND_SNR_MONO_THRESHOLD = 0x1805,\n    PROP_FM_BLEND_SNR_ATTACK_RATE = 0x1806,\n    PROP_FM_BLEND_SNR_RELEASE_RATE = 0x1807,\n    PROP_FM_BLEND_MULTIPATH_STEREO_THRESHOLD = 0x1808,\n    PROP_FM_BLEND_MULTIPATH_MONO_THRESHOLD = 0x1809,\n    PROP_FM_BLEND_MULTIPATH_ATTACK_RATE = 0x180A,\n    PROP_FM_BLEND_MULTIPATH_RELEASE_RATE = 0x180B,\n    PROP_FM_BLEND_MAX_STEREO_SEPARATION = 0x180C,\n    PROP_FM_NB_DETECT_THRESHOLD = 0x1900,\n    PROP_FM_NB_INTERVAL = 0x1901,\n    PROP_FM_NB_RATE = 0x1902,\n    PROP_FM_NB_IIR_FILTER = 0x1903,\n    PROP_FM_NB_DELAY = 0x1904,\n    PROP_FM_HICUT_SNR_HIGH_THRESHOLD = 0x1A00,\n    PROP_FM_HICUT_SNR_LOW_THRESHOLD = 0x1A01,\n    PROP_FM_HICUT_ATTACK_RATE = 0x1A02,\n    PROP_FM_HICUT_RELEASE_RATE = 0x1A03,\n    PROP_FM_HICUT_MULTIPATH_TRIGGER_THRESHOLD = 0x1A04,\n    PROP_FM_HICUT_MULTIPATH_END_THRESHOLD = 0x1A05,\n    PROP_FM_HICUT_CUTOFF_FREQUENCY = 0x1A06,\n    PROP_TX_COMPONENT_ENABLE = 0x2100,\n    PROP_TX_AUDIO_DEVIATION = 0x2101,\n    PROP_TX_PILOT_DEVIATION = 0x2102,\n    PROP_TX_RDS_DEVIATION = 0x2103,\n    PROP_TX_LINE_INPUT_LEVEL = 0x2104,\n    PROP_TX_LINE_INPUT_MUTE = 0x2105,\n    PROP_TX_PREEMPHASIS = 0x2106,\n    PROP_TX_PILOT_FREQUENCY = 0x2107,\n    PROP_TX_ACOMP_ENABLE = 0x2200,\n    PROP_TX_ACOMP_THRESHOLD = 0x2201,\n    PROP_TX_ACOMP_ATTACK_TIME = 0x2202,\n    PROP_TX_ACOMP_RELEASE_TIME = 0x2203,\n    PROP_TX_ACOMP_GAIN = 0x2204,\n    PROP_TX_LIMITER_RELEASE_TIME = 0x2205,\n    PROP_TX_ASQ_INTERRUPT_SOURCE = 0x2300,\n    PROP_TX_ASQ_LEVEL_LOW = 0x2301,\n    PROP_TX_ASQ_DURATION_LOW = 0x2302,\n    PROP_TX_ASQ_LEVEL_HIGH = 0x2303,\n    PROP_TX_ASQ_DURATION_HIGH = 0x2304,\n    PROP_TX_RDS_INTERRUPT_SOURCE = 0x2C00,\n    PROP_TX_RDS_PI = 0x2C01,\n    PROP_TX_RDS_PS_MIX = 0x2C02,\n    PROP_TX_RDS_PS_MISC = 0x2C03,\n    PROP_TX_RDS_PS_REPEAT_COUNT = 0x2C04,\n    PROP_TX_RDS_PS_MESSAGE_COUNT = 0x2C05,\n    PROP_TX_RDS_PS_AF = 0x2C06,\n    PROP_TX_RDS_FIFO_SIZE = 0x2C07,\n    PROP_AM_DEEMPHASIS = 0x3100,\n    PROP_AM_CHANNEL_FILTER = 0x3102,\n    PROP_AM_AUTOMATIC_VOLUME_CONTROL_MAX_GAIN = 0x3103,\n    PROP_AM_MODE_AFC_SW_PULL_IN_RANGE = 0x3104,\n    PROP_AM_MODE_AFC_SW_LOCK_IN_RANGE = 0x3105,\n    PROP_AM_RSQ_INTERRUPTS = 0x3200,\n    PROP_AM_RSQ_SNR_HIGH_THRESHOLD = 0x3201,\n    PROP_AM_RSQ_SNR_LOW_THRESHOLD = 0x3202,\n    PROP_AM_RSQ_RSSI_HIGH_THRESHOLD = 0x3203,\n    PROP_AM_RSQ_RSSI_LOW_THRESHOLD = 0x3204,\n    PROP_AM_SOFT_MUTE_RATE = 0x3300,\n    PROP_AM_SOFT_MUTE_SLOPE = 0x3301,\n    PROP_AM_SOFT_MUTE_MAX_ATTENUATION = 0x3302,\n    PROP_AM_SOFT_MUTE_SNR_THRESHOLD = 0x3303,\n    PROP_AM_SOFT_MUTE_RELEASE_RATE = 0x3304,\n    PROP_AM_SOFT_MUTE_ATTACK_RATE = 0x3305,\n    PROP_AM_SEEK_BAND_BOTTOM = 0x3400,\n    PROP_AM_SEEK_BAND_TOP = 0x3401,\n    PROP_AM_SEEK_FREQ_SPACING = 0x3402,\n    PROP_AM_SEEK_TUNE_SNR_THRESHOLD = 0x3403,\n    PROP_AM_SEEK_TUNE_RSSI_THRESHOLD = 0x3404,\n    PROP_AM_AGC_ATTACK_RATE = 0x3702,\n    PROP_AM_AGC_RELEASE_RATE = 0x3703,\n    PROP_AM_FRONTEND_AGC_CONTROL = 0x3705,\n    PROP_AM_NB_DETECT_THRESHOLD = 0x3900,\n    PROP_AM_NB_INTERVAL = 0x3901,\n    PROP_AM_NB_RATE = 0x3902,\n    PROP_AM_NB_IIR_FILTER = 0x3903,\n    PROP_AM_NB_DELAY = 0x3904,\n    PROP_RX_VOLUME = 0x4000,\n    PROP_RX_HARD_MUTE = 0x4001,\n    PROP_WB_MAX_TUNE_ERROR = 0x5108,\n    PROP_WB_RSQ_INT_SOURCE = 0x5200,\n    PROP_WB_RSQ_SNR_HI_THRESHOLD = 0x5201,\n    PROP_WB_RSQ_SNR_LO_THRESHOLD = 0x5202,\n    PROP_WB_RSQ_RSSI_HI_THRESHOLD = 0x5203,\n    PROP_WB_RSQ_RSSI_LO_THRESHOLD = 0x5204,\n    PROP_WB_VALID_SNR_THRESHOLD = 0x5403,\n    PROP_WB_VALID_RSSI_THRESHOLD = 0x5404,\n    PROP_WB_SAME_INTERRUPT_SOURCE = 0x5500,\n    PROP_WB_ASQ_INTERRUPT_SOURCE = 0x5600,\n    PROP_AUX_ASQ_INTERRUPT_SOURCE = 0x6600,\n    PROP_DEBUG_CONTROL = 0xFF00,\n    PROP_AM_RSQ_INT_SOURCE = 0x3200,\n    PROP_WB_SAME_INT_SOURCE = 0x5500, // Si4707 only\n    PROP_WB_ASQ_INT_SOURCE = 0x5600,\n    PROP_AUX_ASQ_INT_SOURCE = 0x6600, // AUX mode - Si4735-D60 or later\n\n    PROP_SSB_BFO = 0x0100, // Sets the Beat Frequency Offset (BFO) under SSB mode.\n    PROP_SSB_MODE = 0x0101, // Sets number of properties of the SSB mode.\n    PROP_SSB_RSQ_INTERRUPTS = 0x3200, // Configure Interrupts related to RSQ\n    PROP_SSB_RSQ_SNR_HI_THRESHOLD =\n    0x3201, // Sets high threshold for SNR interrupt\n    PROP_SSB_RSQ_SNR_LO_THRESHOLD =\n    0x3202, // Sets low threshold for SNR interrupt\n    PROP_SSB_RSQ_RSSI_HI_THRESHOLD =\n    0x3203, // Sets high threshold for RSSI interrupt\n    PROP_SSB_RSQ_RSSI_LO_THRESHOLD =\n    0x3204,                       // Sets low threshold for RSSI interrupt\n    PROP_SSB_SOFT_MUTE_RATE = 0x3300, // Sets the attack and decay rates when\n    // entering or leaving soft mute\n    PROP_SSB_SOFT_MUTE_MAX_ATTENUATION =\n    0x3302, // Sets the maximum attenuation during soft mute (db); 0dB to\n    // disable soft mute; defaul 8dB;\n    PROP_SSB_SOFT_MUTE_SNR_THRESHOLD =\n    0x3303, // Sets SNR threshould to engage soft mute. Defaul 8dB\n    PROP_SSB_RF_AGC_ATTACK_RATE =\n    0x3700, // Sets the number of milliseconds the high RF peak detector must\n    // be exceeded before decreasing the gain. Defaul 4.\n    PROP_SSB_RF_AGC_RELEASE_RATE =\n    0x3701, // Sets the number of milliseconds the low RF peak detector must\n    // be exceeded before increasing the gain. Defaul 24.\n    PROP_SSB_IF_AGC_RELEASE_RATE =\n    0x3703, // Sets the number of milliseconds the low IF peak detector must\n    // not be exceeded before increasing the gain. Default value is\n    // 140 (approximately 40 dB / s).\n    PROP_SSB_IF_AGC_ATTACK_RATE =\n    0x3702, // Sets the number of milliseconds the high IF peak detector must\n    // be exceeded before decreasing gain. Default value is 4\n    // (approximately 1400 dB / s).\n\n} SI47XX_PropertyCodes;\n\nenum {\n    // POWER_UP\n    /* See POWER_UP_AUDIO_OUT constants above for ARG2. */\n    POWER_UP_ARG1_CTSIEN = 0b10000000,  // CTS interrupt enable\n    POWER_UP_ARG1_GPO2OEN = 0b01000000, // GPO2/INT output enable\n    POWER_UP_ARG1_PATCH = 0b00100000,   // Patch enable\n    POWER_UP_ARG1_XOSCEN =\n    0b00010000, // Enable internal oscillator with external 32768 Hz crystal\n    POWER_UP_ARG1_FUNC_FM = 0x0,  // FM receive mode\n    POWER_UP_ARG1_FUNC_AM = 0x1,  // AM receive mode\n    POWER_UP_ARG1_FUNC_TX = 0x2,  // FM transmit mode - not Si4735 or Si4707\n    POWER_UP_ARG1_FUNC_WB = 0x3,  // WB receive mode - not Si4735\n    POWER_UP_ARG1_FUNC_AUX = 0x4, // Auxiliary input mode - Si4735-D60 or later\n    POWER_UP_ARG1_FUNC_REV = 0xF, // Query chip's hardware and firmware revisions\n    // FM_TUNE_FREQ, AM_TUNE_FREQ\n    FM_TUNE_FREQ_ARG1_FREEZE = 0b10,\n    TUNE_FREQ_ARG1_FAST = 0b01, // Fast, inaccurate tune\n    // FM_SEEK_START, AM_SEEK_START\n    SEEK_START_ARG1_SEEK_UP = 0b1000, // 1 = Seek up, 0 = Seek down\n    SEEK_START_ARG1_WRAP = 0b0100,    // Wrap when band limit reached\n    // FM_TUNE_STATUS, AM_TUNE_STATUS, WB_TUNE_STATUS\n    TUNE_STATUS_ARG1_CANCEL_SEEK = 0b10, // Cancel seek operation - not WB\n    TUNE_STATUS_ARG1_CLEAR_INT = 0b01,   // Clear STC interrupt\n    // FM_RSQ_STATUS, AM_RSQ_STATUS, WB_RSQ_STATUS\n    RSQ_STATUS_ARG1_CLEAR_INT = 0b1, // Clear RSQ and related interrupts\n    // FM_RDS_STATUS\n    RDS_STATUS_ARG1_STATUS_ONLY = 0b100,\n    RDS_STATUS_ARG1_CLEAR_FIFO = 0b010, // Clear RDS receive FIFO\n    RDS_STATUS_ARG1_CLEAR_INT = 0b001,  // Clear RDS interrupt\n    // WB_SAME_STATUS\n    SAME_STATUS_ARG1_CLEAR_BUFFER = 0b10, // Clear SAME receive buffer\n    SAME_STATUS_ARG1_CLEAR_INT = 0b01,    // Clear SAME interrupt\n    // AUX_ASQ_STATUS, WB_ASQ_STATUS\n    ASQ_STATUS_ARG1_CLEAR_INT = 0b1, // Clear ASQ interrupt\n    // FM_AGC_OVERRIDE, AM_AGC_OVERRIDE, WB_AGC_OVERRIDE\n    AGC_OVERRIDE_ARG1_DISABLE_AGC = 0b1, // Disable AGC\n    // GPIO_CTL, GPIO_SET\n    GPIO_ARG1_GPO3 = 0b1000, // GPO3\n    GPIO_ARG1_GPO2 = 0b0100, // GPO2\n    GPIO_ARG1_GPO1 = 0b0010, // GPO1\n};\n\n// Command responses\n// Names that begin with FIELD are argument masks.  Others are argument\n// constants.\nenum {\n    // FM_TUNE_STATUS, AM_TUNE_STATUS, WB_TUNE_STATUS\n    FIELD_TUNE_STATUS_RESP1_SEEK_LIMIT =\n    0b10000000,                            // Seek hit search limit - not WB\n    FIELD_TUNE_STATUS_RESP1_AFC_RAILED = 0b10, // AFC railed\n    FIELD_TUNE_STATUS_RESP1_SEEKABLE =\n    0b01, // Station could currently be found by seek,\n    FIELD_TUNE_STATUS_RESP1_VALID = 0b01, // that is, the station is valid\n    // FM_RSQ_STATUS, AM_RSQ_STATUS, WB_RSQ_STATUS\n    /* See RSQ interrupts above for RESP1. */\n    FIELD_RSQ_STATUS_RESP2_SOFT_MUTE = 0b1000,  // Soft mute active - not WB\n    FIELD_RSQ_STATUS_RESP2_AFC_RAILED = 0b0010, // AFC railed\n    FIELD_RSQ_STATUS_RESP2_SEEKABLE =\n    0b0001, // Station could currently be found by seek,\n    FIELD_RSQ_STATUS_RESP2_VALID = 0b0001,      // that is, the station is valid\n    FIELD_RSQ_STATUS_RESP3_STEREO = 0b10000000, // Stereo pilot found - FM only\n    FIELD_RSQ_STATUS_RESP3_STEREO_BLEND =\n    0b01111111, // Stereo blend in % (100 = full stereo, 0 = full mono) - FM\n    // only\n    // FM_RDS_STATUS\n    /* See RDS interrupts above for RESP1. */\n    FIELD_RDS_STATUS_RESP2_FIFO_OVERFLOW = 0b00000100, // FIFO overflowed\n    FIELD_RDS_STATUS_RESP2_SYNC = 0b00000001, // RDS currently synchronized\n    FIELD_RDS_STATUS_RESP12_BLOCK_A = 0b11000000,\n    FIELD_RDS_STATUS_RESP12_BLOCK_B = 0b00110000,\n    FIELD_RDS_STATUS_RESP12_BLOCK_C = 0b00001100,\n    FIELD_RDS_STATUS_RESP12_BLOCK_D = 0b00000011,\n    RDS_STATUS_RESP12_BLOCK_A_NO_ERRORS = 0U << 6,     // Block had no errors\n    RDS_STATUS_RESP12_BLOCK_A_2_BIT_ERRORS = 1U << 6,  // Block had 1-2 bit errors\n    RDS_STATUS_RESP12_BLOCK_A_5_BIT_ERRORS = 2U << 6,  // Block had 3-5 bit errors\n    RDS_STATUS_RESP12_BLOCK_A_UNCORRECTABLE = 3U << 6, // Block was uncorrectable\n    RDS_STATUS_RESP12_BLOCK_B_NO_ERRORS = 0U << 4,\n    RDS_STATUS_RESP12_BLOCK_B_2_BIT_ERRORS = 1U << 4,\n    RDS_STATUS_RESP12_BLOCK_B_5_BIT_ERRORS = 2U << 4,\n    RDS_STATUS_RESP12_BLOCK_B_UNCORRECTABLE = 3U << 4,\n    RDS_STATUS_RESP12_BLOCK_C_NO_ERRORS = 0U << 2,\n    RDS_STATUS_RESP12_BLOCK_C_2_BIT_ERRORS = 1U << 2,\n    RDS_STATUS_RESP12_BLOCK_C_5_BIT_ERRORS = 2U << 2,\n    RDS_STATUS_RESP12_BLOCK_C_UNCORRECTABLE = 3U << 2,\n    RDS_STATUS_RESP12_BLOCK_D_NO_ERRORS = 0U << 0,\n    RDS_STATUS_RESP12_BLOCK_D_2_BIT_ERRORS = 1U << 0,\n    RDS_STATUS_RESP12_BLOCK_D_5_BIT_ERRORS = 2U << 0,\n    RDS_STATUS_RESP12_BLOCK_D_UNCORRECTABLE = 3U << 0,\n    // WB_SAME_STATUS - TODO\n\n    // AUX_ASQ_STATUS, WB_ASQ_STATUS\n    /* See ASQ interrupts above for RESP1. */\n    FIELD_AUX_ASQ_STATUS_RESP2_OVERLOAD =\n    0b1, // Audio input is currently overloading ADC\n    FIELD_WB_ASQ_STATUS_RESP2_ALERT = 0b1, // Alert tone is present\n    // FM_AGC_STATUS, AM_AGC_STATUS, WB_AGC_STATUS\n    FIELD_AGC_STATUS_RESP1_DISABLE_AGC = 0b1, // True if AGC disabled\n};\n\ntypedef union {\n    struct {\n        // status (\"RESP0\")\n        uint8_t STCINT: 1;\n        uint8_t DUMMY1: 1;\n        uint8_t RDSINT: 1;\n        uint8_t RSQINT: 1;\n        uint8_t DUMMY2: 2;\n        uint8_t ERR: 1;\n        uint8_t CTS: 1;\n        // RESP1\n        uint8_t RSSIILINT: 1; //!<  RSSI Detect Low.\n        uint8_t RSSIHINT: 1;  //!<  RSSI Detect High.\n        uint8_t SNRLINT: 1;   //!<  SNR Detect Low.\n        uint8_t SNRHINT: 1;   //!<  SNR Detect High.\n        uint8_t MULTLINT: 1;  //!<  Multipath Detect Low\n        uint8_t MULTHINT: 1;  //!<  Multipath Detect High\n        uint8_t DUMMY3: 1;\n        uint8_t BLENDINT: 1; //!<  Blend Detect Interrupt.\n        // RESP2\n        uint8_t VALID: 1; //!<  Valid Channel.\n        uint8_t AFCRL: 1; //!<  AFC Rail Indicator.\n        uint8_t DUMMY4: 1;\n        uint8_t\n                SMUTE: 1; //!<  Soft Mute Indicator. Indicates soft mute is engaged.\n        uint8_t DUMMY5: 4;\n        // RESP3\n        uint8_t STBLEND: 7; //!<  Indicates amount of stereo blend in% (100 = full\n        //!<  stereo, 0 = full mono).\n        uint8_t PILOT: 1;   //!<  Indicates stereo pilot presence.\n        // RESP4 to RESP7\n        uint8_t RSSI; //!<  RESP4 - Contains the current receive signal strength\n        //!<  (0–127 dBμV).\n        uint8_t SNR;  //!<  RESP5 - Contains the current SNR metric (0–127 dB).\n        uint8_t MULT; //!<  RESP6 - Contains the current multipath metric. (0 = no\n        //!<  multipath; 100 = full multipath)\n        uint8_t FREQOFF; //!<  RESP7 - Signed frequency offset (kHz).\n    } resp;\n    uint8_t raw[8];\n} RSQStatus;\n\ntypedef union {\n    struct {\n        // ARG1\n        uint8_t AGCDIS: 1; // if set to 1 indicates if the AGC is disabled. 0 = AGC\n        // enabled; 1 = AGC disabled.\n        uint8_t DUMMY: 7;\n        // ARG2\n        uint8_t AGCIDX; // AGC Index; If AMAGCDIS = 1, this byte forces the AGC gain\n        // index; 0 = Minimum attenuation (max gain)\n    } arg;\n    uint8_t raw[2];\n} SI47XX_AgcOverrride;\n\ntypedef union {\n    struct {\n        uint8_t\n                FAST: 1; //!<  ARG1 - FAST Tuning. If set, executes fast and\n        //!<  invalidated tune. The tune status will not be accurate.\n        uint8_t FREEZE: 1; //!<  Valid only for FM (Must be 0 to AM)\n        uint8_t DUMMY1: 4; //!<  Always set 0\n        uint8_t\n                USBLSB: 2; //!<  SSB Upper Side Band (USB) and Lower Side Band (LSB)\n        //!<  Selection. 10 = USB is selected; 01 = LSB is selected.\n        uint8_t FREQH;  //!<  ARG2 - Tune Frequency High byte.\n        uint8_t FREQL;  //!<  ARG3 - Tune Frequency Low byte.\n        uint8_t ANTCAPH; //!<  ARG4 - Antenna Tuning Capacitor High byte.\n        uint8_t ANTCAPL; //!<  ARG5 - Antenna Tuning Capacitor Low byte. Note used\n        //!<  for FM.\n    } arg;\n    uint8_t raw[5];\n} SI47XX_SetFrequency;\n\ntypedef union {\n    struct {\n        uint8_t AMCHFLT: 4; //!<  Selects the bandwidth of the AM channel filter.\n        uint8_t DUMMY1: 4;\n        uint8_t AMPLFLT: 1; //!<  Enables the AM Power Line Noise Rejection Filter.\n        uint8_t DUMMY2: 7;\n    } param;\n    uint8_t raw[2];\n} SI47XX_BW_Config; // AM_CHANNEL_FILTER\n\nvoid SI47XX_PowerUp();\n\nvoid SI47XX_PowerDown();\n\nvoid SI47XX_SetFreq(uint16_t freq);\n\nvoid SI47XX_ReadRDS(uint8_t buf[13]);\n\nvoid SI47XX_SwitchMode(SI47XX_MODE mode);\n\nbool SI47XX_IsSSB();\n\nvoid RSQ_GET();\n\nvoid SI47XX_SetAutomaticGainControl(uint8_t AGCDIS, uint8_t AGCIDX);\n\nvoid SI47XX_Seek(bool up, bool wrap);\n\nuint16_t SI47XX_getFrequency(bool *valid);\n\nvoid SI47XX_SetBandwidth(SI47XX_FilterBW AMCHFLT, bool AMPLFLT);\n\nvoid SI47XX_SetSsbBandwidth(SI47XX_SsbFilterBW bw);\n\nvoid SI47XX_SetSeekFmLimits(uint16_t bottom, uint16_t top);\n\nvoid SI47XX_SetSeekAmLimits(uint16_t bottom, uint16_t top);\n\nvoid SI47XX_SetSeekFmSpacing(uint16_t spacing);\n\nvoid SI47XX_SetSeekAmSpacing(uint16_t spacing);\n\nvoid SI47XX_SetSeekFmRssiThreshold(uint16_t value);\n\nvoid SI47XX_SetSeekAmRssiThreshold(uint16_t value);\n\nvoid SI47XX_SetBFO(int16_t bfo);\n\nvoid SI47XX_SetSsbCapacitor(uint16_t v);\n\nuint32_t Read_FreqSaved();\n\nbool FreqCheck(uint32_t f);\nvoid setVolume(uint8_t volume) ;\n\nextern SI47XX_MODE si4732mode;\nextern RSQStatus rsqStatus;\nextern uint16_t siCurrentFreq;\nextern uint16_t divider;\n\n#define PATCH_SIZE 15832\n\n\n#define SI4732_FREQ_ADD 0X01FE0\n\n\n\n\n#endif /* end of include guard: SI473X_H */\n"
  },
  {
    "path": "driver/spi.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"ARMCM0.h\"\r\n#include \"bsp/dp32g030/spi.h\"\r\n#include \"bsp/dp32g030/syscon.h\"\r\n#include \"bsp/dp32g030/irq.h\"\r\n#include \"driver/spi.h\"\r\n\r\nvoid SPI0_Init(void) {\r\n    SPI_Config_t Config;\r\n\r\n    SPI_Disable(&SPI0->CR);\r\n\r\n    Config.TXFIFO_EMPTY = 0;\r\n    Config.RXFIFO_HFULL = 0;\r\n    Config.RXFIFO_FULL = 0;\r\n    Config.RXFIFO_OVF = 0;\r\n    Config.MSTR = 1;\r\n    Config.SPR = 2;\r\n    Config.CPHA = 1;\r\n    Config.CPOL = 1;\r\n    Config.LSB = 0;\r\n    Config.TF_CLR = 0;\r\n    Config.RF_CLR = 0;\r\n    Config.TXFIFO_HFULL = 0;\r\n    SPI_Configure(SPI0, &Config);\r\n\r\n    SPI_Enable(&SPI0->CR);\r\n}\r\n\r\nvoid SPI_WaitForUndocumentedTxFifoStatusBit(void) {\r\n    uint32_t Timeout;\r\n\r\n    Timeout = 0;\r\n    do {\r\n        // Undocumented bit!\r\n        if ((SPI0->IF & 0x20) == 0) {\r\n            break;\r\n        }\r\n        Timeout++;\r\n    } while (Timeout <= 100000);\r\n}\r\n\r\nvoid SPI_Disable(volatile uint32_t *pCR) {\r\n    *pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_DISABLE;\r\n}\r\n\r\nvoid SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig) {\r\n    if (pPort == SPI0) {\r\n        SYSCON_DEV_CLK_GATE =\r\n                (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI0_MASK) | SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE;\r\n    } else if (pPort == SPI1) {\r\n        SYSCON_DEV_CLK_GATE =\r\n                (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI1_MASK) | SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE;\r\n    }\r\n\r\n    SPI_Disable(&pPort->CR);\r\n\r\n    pPort->CR = 0\r\n                | (pPort->CR &\r\n                   ~(SPI_CR_SPR_MASK | SPI_CR_CPHA_MASK | SPI_CR_CPOL_MASK | SPI_CR_MSTR_MASK | SPI_CR_LSB_MASK |\r\n                     SPI_CR_RF_CLR_MASK))\r\n                | ((pConfig->SPR << SPI_CR_SPR_SHIFT) & SPI_CR_SPR_MASK)\r\n                | ((pConfig->CPHA << SPI_CR_CPHA_SHIFT) & SPI_CR_CPHA_MASK)\r\n                | ((pConfig->CPOL << SPI_CR_CPOL_SHIFT) & SPI_CR_CPOL_MASK)\r\n                | ((pConfig->MSTR << SPI_CR_MSTR_SHIFT) & SPI_CR_MSTR_MASK)\r\n                | ((pConfig->LSB << SPI_CR_LSB_SHIFT) & SPI_CR_LSB_MASK)\r\n                | ((pConfig->RF_CLR << SPI_CR_RF_CLR_SHIFT) & SPI_CR_RF_CLR_MASK)\r\n                | ((pConfig->TF_CLR << SPI_CR_TF_CLR_SHIFT) & SPI_CR_TF_CLR_MASK);\r\n\r\n    pPort->IE = 0\r\n                | ((pConfig->RXFIFO_OVF << SPI_IE_RXFIFO_OVF_SHIFT) & SPI_IE_RXFIFO_OVF_MASK)\r\n                | ((pConfig->RXFIFO_FULL << SPI_IE_RXFIFO_FULL_SHIFT) & SPI_IE_RXFIFO_FULL_MASK)\r\n                | ((pConfig->RXFIFO_HFULL << SPI_IE_RXFIFO_HFULL_SHIFT) & SPI_IE_RXFIFO_HFULL_MASK)\r\n                | ((pConfig->TXFIFO_EMPTY << SPI_IE_TXFIFO_EMPTY_SHIFT) & SPI_IE_TXFIFO_EMPTY_MASK)\r\n                | ((pConfig->TXFIFO_HFULL << SPI_IE_TXFIFO_HFULL_SHIFT) & SPI_IE_TXFIFO_HFULL_MASK);\r\n\r\n    if (pPort->IE) {\r\n        if (pPort == SPI0) {\r\n            NVIC_EnableIRQ((IRQn_Type) DP32_SPI0_IRQn);\r\n        } else if (pPort == SPI1) {\r\n            NVIC_EnableIRQ((IRQn_Type) DP32_SPI1_IRQn);\r\n        }\r\n    }\r\n}\r\n\r\nvoid SPI_ToggleMasterMode(volatile uint32_t *pCR, bool bIsMaster) {\r\n    if (bIsMaster) {\r\n        *pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_ENABLE;\r\n    } else {\r\n        *pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_DISABLE;\r\n    }\r\n}\r\n\r\nvoid SPI_Enable(volatile uint32_t *pCR) {\r\n    *pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_ENABLE;\r\n}\r\n\r\n"
  },
  {
    "path": "driver/spi.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_SPI_H\r\n#define DRIVER_SPI_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\ntypedef struct {\r\n\tuint8_t MSTR;\r\n\tuint8_t SPR;\r\n\tuint8_t CPHA;\r\n\tuint8_t CPOL;\r\n\tuint8_t LSB;\r\n\tuint8_t TF_CLR;\r\n\tuint8_t RF_CLR;\r\n\tuint8_t TXFIFO_HFULL;\r\n\tuint8_t TXFIFO_EMPTY;\r\n\tuint8_t RXFIFO_HFULL;\r\n\tuint8_t RXFIFO_FULL;\r\n\tuint8_t RXFIFO_OVF;\r\n} SPI_Config_t;\r\n\r\nvoid SPI0_Init(void);\r\nvoid SPI_WaitForUndocumentedTxFifoStatusBit(void);\r\n\r\nvoid SPI_Disable(volatile uint32_t *pCR);\r\nvoid SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig);\r\nvoid SPI_ToggleMasterMode(volatile uint32_t *pCr, bool bIsMaster);\r\nvoid SPI_Enable(volatile uint32_t *pCR);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/st7565.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <stdint.h>\r\n#include <stdio.h>     // NULL\r\n\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"bsp/dp32g030/spi.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/spi.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"driver/system.h\"\r\n#include \"misc.h\"\r\n\r\nuint8_t gStatusLine[LCD_WIDTH];\r\nuint8_t gFrameBuffer[FRAME_LINES][LCD_WIDTH];\r\n\r\nstatic void DrawLine(uint8_t column, uint8_t line, const uint8_t *lineBuffer, unsigned size_defVal) {\r\n    ST7565_SelectColumnAndLine(column + 4, line);\r\n    GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0);\r\n    for (unsigned i = 0; i < size_defVal; i++) {\r\n        while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}\r\n        SPI0->WDR = lineBuffer ? lineBuffer[i] : size_defVal;\r\n    }\r\n    SPI_WaitForUndocumentedTxFifoStatusBit();\r\n}\r\n\r\nvoid\r\nST7565_DrawLine(const unsigned int Column, const unsigned int Line, const uint8_t *pBitmap, const unsigned int Size) {\r\n    SPI_ToggleMasterMode(&SPI0->CR, false);\r\n    DrawLine(Column, Line, pBitmap, Size);\r\n    SPI_ToggleMasterMode(&SPI0->CR, true);\r\n}\r\n\r\nvoid ST7565_BlitFullScreen(void) {\r\n    SPI_ToggleMasterMode(&SPI0->CR, false);\r\n    ST7565_WriteByte(0x40);\r\n    for (unsigned line = 0; line < FRAME_LINES; line++) {\r\n        DrawLine(0, line + 1, gFrameBuffer[line], LCD_WIDTH);\r\n    }\r\n    SPI_ToggleMasterMode(&SPI0->CR, true);\r\n}\r\n\r\nvoid ST7565_BlitLine(unsigned line) {\r\n    SPI_ToggleMasterMode(&SPI0->CR, false);\r\n    ST7565_WriteByte(0x40);    // start line ?\r\n    DrawLine(0, line + 1, gFrameBuffer[line], LCD_WIDTH);\r\n    SPI_ToggleMasterMode(&SPI0->CR, true);\r\n}\r\n\r\nvoid ST7565_BlitStatusLine(void) {    // the top small text line on the display\r\n    SPI_ToggleMasterMode(&SPI0->CR, false);\r\n    ST7565_WriteByte(0x40);    // start line ?\r\n    DrawLine(0, 0, gStatusLine, LCD_WIDTH);\r\n    SPI_ToggleMasterMode(&SPI0->CR, true);\r\n}\r\n\r\nvoid ST7565_FillScreen(uint8_t value) {\r\n    SPI_ToggleMasterMode(&SPI0->CR, false);\r\n    for (unsigned i = 0; i < 8; i++) {\r\n        DrawLine(0, i, NULL, value);\r\n    }\r\n    SPI_ToggleMasterMode(&SPI0->CR, true);\r\n}\r\n\r\n// Software reset\r\nconst uint8_t ST7565_CMD_SOFTWARE_RESET = 0xE2;\r\n// Bias Select\r\n// 1 0 1 0 0 0 1 BS\r\n// Select bias setting 0=1/9; 1=1/7 (at 1/65 duty)\r\nconst uint8_t ST7565_CMD_BIAS_SELECT = 0xA2;\r\n// COM Direction\r\n// 1 1 0 0 MY - - -\r\n// Set output direction of COM\r\n// MY=1, reverse direction\r\n// MY=0, normal direction\r\nconst uint8_t ST7565_CMD_COM_DIRECTION = 0xC0;\r\n// SEG Direction\r\n// 1 0 1 0 0 0 0 MX\r\n// Set scan direction of SEG\r\n// MX=1, reverse direction\r\n// MX=0, normal direction\r\nconst uint8_t ST7565_CMD_SEG_DIRECTION = 0xA0;\r\n// Inverse Display\r\n// 1 0 1 0 0 1 1 INV\r\n// INV =1, inverse display\r\n// INV =0, normal display\r\nconst uint8_t ST7565_CMD_INVERSE_DISPLAY = 0xA6;\r\n// All Pixel ON\r\n// 1 0 1 0 0 1 0 AP\r\n// AP=1, set all pixel ON\r\n// AP=0, normal display\r\nconst uint8_t ST7565_CMD_ALL_PIXEL_ON = 0xA4;\r\n// Regulation Ratio\r\n// 0 0 1 0 0 RR2 RR1 RR0\r\n// This instruction controls the regulation ratio of the built-in regulator\r\nconst uint8_t ST7565_CMD_REGULATION_RATIO = 0x20;\r\n// Double command!! Set electronic volume (EV) level\r\n// Send next: 0 0 EV5 EV4 EV3 EV2 EV1 EV0  contrast 0-63\r\nconst uint8_t ST7565_CMD_SET_EV = 0x81;\r\n// Control built-in power circuit ON/OFF - 0 0 1 0 1 VB VR VF\r\n// VB: Built-in Booster\r\n// VR: Built-in Regulator\r\n// VF: Built-in Follower\r\nconst uint8_t ST7565_CMD_POWER_CIRCUIT = 0x28;\r\n// Set display start line 0-63\r\n// 0 0 0 1 S5 S4 S3 S2 S1 S0\r\nconst uint8_t ST7565_CMD_SET_START_LINE = 0x40;\r\n// Display ON/OFF\r\n// 0 0 1 0 1 0 1 1 1 D\r\n// D=1, display ON\r\n// D=0, display OFF\r\nconst uint8_t ST7565_CMD_DISPLAY_ON_OFF = 0xAE;\r\n\r\nuint8_t cmds[] = {\r\n        ST7565_CMD_BIAS_SELECT | 0,            // Select bias setting: 1/9\r\n        ST7565_CMD_COM_DIRECTION | (0 << 3),    // Set output direction of COM: normal\r\n        ST7565_CMD_SEG_DIRECTION | 1,            // Set scan direction of SEG: reverse\r\n        ST7565_CMD_INVERSE_DISPLAY | 0,        // Inverse Display: false\r\n        ST7565_CMD_ALL_PIXEL_ON | 0,            // All Pixel ON: false - normal display\r\n        ST7565_CMD_REGULATION_RATIO | (4 << 0), // Regulation Ratio 5.0\r\n\r\n        ST7565_CMD_SET_EV,                        // Set contrast\r\n        31,\r\n\r\n        ST7565_CMD_POWER_CIRCUIT | 0b111,        // Built-in power circuit ON/OFF: VB=1 VR=1 VF=1\r\n        ST7565_CMD_SET_START_LINE | 0,            // Set Start Line: 0\r\n        ST7565_CMD_DISPLAY_ON_OFF | 1,            // Display ON/OFF: ON\r\n};\r\n\r\nvoid ST7565_Init(void) {\r\n    SPI0_Init();\r\n    ST7565_HardwareReset();\r\n    SPI_ToggleMasterMode(&SPI0->CR, false);\r\n    ST7565_WriteByte(ST7565_CMD_SOFTWARE_RESET);   // software reset\r\n    SYSTEM_DelayMs(120);\r\n\r\n    for (uint8_t i = 0; i < 8; i++)\r\n        ST7565_WriteByte(cmds[i]);\r\n\r\n    ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b011);   // VB=0 VR=1 VF=1\r\n    SYSTEM_DelayMs(1);\r\n    ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b110);   // VB=1 VR=1 VF=0\r\n    SYSTEM_DelayMs(1);\r\n\r\n    for (uint8_t i = 0; i < 4; i++) // why 4 times?\r\n        ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b111);   // VB=1 VR=1 VF=1\r\n\r\n    SYSTEM_DelayMs(40);\r\n\r\n    ST7565_WriteByte(ST7565_CMD_SET_START_LINE | 0);   // line 0\r\n    ST7565_WriteByte(ST7565_CMD_DISPLAY_ON_OFF | 1);   // D=1\r\n    SPI_WaitForUndocumentedTxFifoStatusBit();\r\n    SPI_ToggleMasterMode(&SPI0->CR, true);\r\n\r\n    ST7565_FillScreen(0x00);\r\n}\r\n\r\nvoid ST7565_FixInterfGlitch(void) {\r\n    SPI_ToggleMasterMode(&SPI0->CR, false);\r\n    for (uint8_t i = 0; i < ARRAY_SIZE(cmds); i++)\r\n        ST7565_WriteByte(cmds[i]);\r\n    SPI_WaitForUndocumentedTxFifoStatusBit();\r\n    SPI_ToggleMasterMode(&SPI0->CR, true);\r\n}\r\n\r\nvoid ST7565_HardwareReset(void) {\r\n    GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES);\r\n    SYSTEM_DelayMs(1);\r\n    GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES);\r\n    SYSTEM_DelayMs(20);\r\n    GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES);\r\n    SYSTEM_DelayMs(120);\r\n}\r\n\r\nvoid ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line) {\r\n    GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0);\r\n    while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}\r\n    SPI0->WDR = Line + 176;\r\n    while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}\r\n    SPI0->WDR = ((Column >> 4) & 0x0F) | 0x10;\r\n    while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}\r\n    SPI0->WDR = ((Column >> 0) & 0x0F);\r\n    SPI_WaitForUndocumentedTxFifoStatusBit();\r\n}\r\n\r\nvoid ST7565_WriteByte(uint8_t Value) {\r\n    GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0);\r\n    while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}\r\n    SPI0->WDR = Value;\r\n}"
  },
  {
    "path": "driver/st7565.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_ST7565_H\r\n#define DRIVER_ST7565_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n#define LCD_WIDTH       128\r\n#define LCD_HEIGHT       64\r\n#define FRAME_LINES 7\r\n\r\nextern uint8_t gStatusLine[LCD_WIDTH];\r\nextern uint8_t gFrameBuffer[FRAME_LINES][LCD_WIDTH];\r\n\r\nvoid ST7565_DrawLine(const unsigned int Column, const unsigned int Line, const uint8_t *pBitmap, const unsigned int Size);\r\nvoid ST7565_BlitFullScreen(void);\r\nvoid ST7565_BlitLine(unsigned line);\r\nvoid ST7565_BlitStatusLine(void);\r\nvoid ST7565_FillScreen(uint8_t Value);\r\nvoid ST7565_Init(void);\r\nvoid ST7565_FixInterfGlitch(void);\r\nvoid ST7565_HardwareReset(void);\r\nvoid ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line);\r\nvoid ST7565_WriteByte(uint8_t Value);\r\n\r\n#endif"
  },
  {
    "path": "driver/system.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"../bsp/dp32g030/pmu.h\"\r\n#include \"../bsp/dp32g030/syscon.h\"\r\n#include \"system.h\"\r\n#include \"systick.h\"\r\n\r\nvoid SYSTEM_DelayMs(uint32_t Delay) {\r\n    SYSTICK_DelayUs(Delay * 1000);\r\n}\r\n\r\nvoid SYSTEM_ConfigureClocks(void) {\r\n    // Set source clock from external crystal\r\n    PMU_SRC_CFG =\r\n            (PMU_SRC_CFG & ~(PMU_SRC_CFG_RCHF_SEL_MASK | PMU_SRC_CFG_RCHF_EN_MASK)) | PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ |\r\n            PMU_SRC_CFG_RCHF_EN_BITS_ENABLE;\r\n\r\n    // Divide by 2\r\n    SYSCON_CLK_SEL = SYSCON_CLK_SEL_DIV_BITS_2;\r\n\r\n    // Disable division clock gate\r\n    SYSCON_DIV_CLK_GATE = (SYSCON_DIV_CLK_GATE & ~SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK) |\r\n                          SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE;\r\n}\r\n"
  },
  {
    "path": "driver/system.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_SYSTEM_H\r\n#define DRIVER_SYSTEM_H\r\n\r\n#include <stdint.h>\r\n\r\nvoid SYSTEM_DelayMs(uint32_t Delay);\r\nvoid SYSTEM_ConfigureClocks(void);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/systick.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"ARMCM0.h\"\r\n#include \"systick.h\"\r\n#include \"../misc.h\"\r\n\r\n// 0x20000324\r\nstatic uint32_t gTickMultiplier;\r\n\r\nvoid SYSTICK_Init(void) {\r\n    SysTick_Config(480000);\r\n    gTickMultiplier = 48;\r\n}\r\n\r\nvoid SYSTICK_DelayUs(uint32_t Delay) {\r\n    const uint32_t ticks = Delay * gTickMultiplier;\r\n    uint32_t elapsed_ticks = 0;\r\n    uint32_t Start = SysTick->LOAD;\r\n    uint32_t Previous = SysTick->VAL;\r\n    do {\r\n        uint32_t Current;\r\n\r\n        do {\r\n            Current = SysTick->VAL;\r\n        } while (Current == Previous);\r\n\r\n        uint32_t Delta = ((Current < Previous) ? -Current : Start - Current);\r\n\r\n        elapsed_ticks += Delta + Previous;\r\n\r\n        Previous = Current;\r\n    } while (elapsed_ticks < ticks);\r\n}\r\n\r\nvoid SYSTICK_Delay250ns(const uint32_t Delay) {\r\n    const uint32_t ticks = (Delay * gTickMultiplier) >> 2;\r\n    uint32_t i = 0;\r\n    uint32_t Start = SysTick->LOAD;\r\n    uint32_t Previous = SysTick->VAL;\r\n\r\n    do {\r\n        uint32_t Delta;\r\n        uint32_t Current;\r\n\r\n        do Current = SysTick->VAL;\r\n        while (Current == Previous);\r\n\r\n        Delta = (Current < Previous) ? -Current : Start - Current;\r\n        i += Delta + Previous;\r\n        Previous = Current;\r\n\r\n    } while (i < ticks);\r\n}\r\n"
  },
  {
    "path": "driver/systick.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef DRIVER_SYSTICK_H\r\n#define DRIVER_SYSTICK_H\r\n\r\n#include <stdint.h>\r\n\r\nvoid SYSTICK_Init(void);\r\nvoid SYSTICK_DelayUs(uint32_t Delay);\r\nvoid SYSTICK_Delay250ns(const uint32_t Delay);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "driver/timer.c",
    "content": "//\n// Created by RUPC on 2024/1/8.\n//\n#include \"bsp/dp32g030/timer.h\"\n#include \"ARMCM0.h\"\n\nvoid TIM0_INIT() {\n    TIMERBASE0_DIV = 4800;\n    TIMERBASE0_LOW_LOAD = 10000; //1s\n    NVIC_SetPriority(Interrupt5_IRQn, 0); /* set Priority for Systick Interrupt */\n    TIMERBASE0_IF |= 0x01; // 写1清零 清除定时器中断状态\n    TIMERBASE0_IE |= 0x01;\n    TIMERBASE0_EN |= 0x01;\n    NVIC_EnableIRQ(Interrupt5_IRQn);\n}\n\nuint32_t TIM0_CNT = 0;\n\nvoid TIM0Handler(void);\n\nvoid TIM0Handler(void) {\n    TIM0_CNT++;\n    TIMERBASE0_IF |= 0x01;\n\n}\n\n\n"
  },
  {
    "path": "driver/uart.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <stdbool.h>\r\n#include \"bsp/dp32g030/dma.h\"\r\n#include \"bsp/dp32g030/syscon.h\"\r\n#include \"bsp/dp32g030/uart.h\"\r\n#include \"driver/uart.h\"\r\n\r\nstatic bool UART_IsLogEnabled;\r\nuint8_t UART_DMA_Buffer[256];\r\n\r\nvoid UART_Init(void) {\r\n    uint32_t Delta;\r\n    uint32_t Positive;\r\n    uint32_t Frequency;\r\n\r\n    UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_BITS_DISABLE;\r\n    Delta = SYSCON_RC_FREQ_DELTA;\r\n    Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT;\r\n    Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT;\r\n    if (Positive) {\r\n        Frequency += 48000000U;\r\n    } else {\r\n        Frequency = 48000000U - Frequency;\r\n    }\r\n\r\n    UART1->BAUD = Frequency / 39053U;\r\n    UART1->CTRL = UART_CTRL_RXEN_BITS_ENABLE | UART_CTRL_TXEN_BITS_ENABLE | UART_CTRL_RXDMAEN_BITS_ENABLE;\r\n    UART1->RXTO = 4;\r\n    UART1->FC = 0;\r\n    UART1->FIFO = UART_FIFO_RF_LEVEL_BITS_8_BYTE | UART_FIFO_RF_CLR_BITS_ENABLE | UART_FIFO_TF_CLR_BITS_ENABLE;\r\n    UART1->IE = 0;\r\n\r\n    DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_DISABLE;\r\n\r\n    DMA_CH0->MSADDR = (uint32_t) (uintptr_t) &UART1->RDR;\r\n    DMA_CH0->MDADDR = (uint32_t) (uintptr_t) UART_DMA_Buffer;\r\n    DMA_CH0->MOD = 0\r\n                   // Source\r\n                   | DMA_CH_MOD_MS_ADDMOD_BITS_NONE\r\n                   | DMA_CH_MOD_MS_SIZE_BITS_8BIT\r\n                   | DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1\r\n                   // Destination\r\n                   | DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT\r\n                   | DMA_CH_MOD_MD_SIZE_BITS_8BIT\r\n                   | DMA_CH_MOD_MD_SEL_BITS_SRAM;\r\n    DMA_INTEN = 0;\r\n    DMA_INTST = 0\r\n                | DMA_INTST_CH0_TC_INTST_BITS_SET\r\n                | DMA_INTST_CH1_TC_INTST_BITS_SET\r\n                | DMA_INTST_CH2_TC_INTST_BITS_SET\r\n                | DMA_INTST_CH3_TC_INTST_BITS_SET\r\n                | DMA_INTST_CH0_THC_INTST_BITS_SET\r\n                | DMA_INTST_CH1_THC_INTST_BITS_SET\r\n                | DMA_INTST_CH2_THC_INTST_BITS_SET\r\n                | DMA_INTST_CH3_THC_INTST_BITS_SET;\r\n    DMA_CH0->CTR = 0\r\n                   | DMA_CH_CTR_CH_EN_BITS_ENABLE\r\n                   | ((0xFF << DMA_CH_CTR_LENGTH_SHIFT) & DMA_CH_CTR_LENGTH_MASK)\r\n                   | DMA_CH_CTR_LOOP_BITS_ENABLE\r\n                   | DMA_CH_CTR_PRI_BITS_MEDIUM;\r\n    UART1->IF = UART_IF_RXTO_BITS_SET;\r\n\r\n    DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_ENABLE;\r\n\r\n    UART1->CTRL |= UART_CTRL_UARTEN_BITS_ENABLE;\r\n}\r\n\r\nvoid UART_Send(const void *pBuffer, uint32_t Size) {\r\n    const uint8_t *pData = (const uint8_t *) pBuffer;\r\n    uint32_t i;\r\n\r\n    for (i = 0; i < Size; i++) {\r\n        UART1->TDR = pData[i];\r\n        while ((UART1->IF & UART_IF_TXFIFO_FULL_MASK) != UART_IF_TXFIFO_FULL_BITS_NOT_SET) {\r\n        }\r\n    }\r\n}\r\n\r\nvoid UART_LogSend(const void *pBuffer, uint32_t Size) {\r\n    if (UART_IsLogEnabled) {\r\n        UART_Send(pBuffer, Size);\r\n    }\r\n}"
  },
  {
    "path": "driver/uart.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n *\r\n */\r\n\r\n#ifndef DRIVER_UART_H\r\n#define DRIVER_UART_H\r\n\r\n#include <stdint.h>\r\n\r\nextern uint8_t UART_DMA_Buffer[256];\r\n\r\nvoid UART_Init(void);\r\nvoid UART_Send(const void *pBuffer, uint32_t Size);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "external/CMSIS_5/.gitattributes",
    "content": "# Set the default behavior, in case people don't have core.autocrlf set.\n* text=auto\n# Explicitly declare text files you want to always be normalized and converted\n# to native line endings on checkout.\n*.c text\n*.h text\n*.txt text\n*.xsd text\n*.pdsc text\n*.svd text\n*.bat text\n# Declare files that will always have CRLF line endings on checkout.\n*.uvproj text eol=crlf\n*.uvproj text eol=crlf\n# Denote all files that are truly binary and should not be modified.\n*.png binary\n*.jpg binary\n# Script files\n*.py text eol=lf\n*.sh text eol=lf\n"
  },
  {
    "path": "external/CMSIS_5/.github/fileheader.json",
    "content": "{\n\t\"problemMatcher\": [\n\t\t{\n\t\t\t\"owner\": \"fileheader\",\n\t\t\t\"severity\": \"error\",\n\t\t\t\"pattern\": [\n\t\t\t\t{\n\t\t\t\t\t\"regexp\": \"^(.*):(\\\\d+):(.*)$\",\n\t\t\t\t\t\"file\": 1,\n\t\t\t\t\t\"line\": 2,\n\t\t\t\t\t\"message\": 3\n\t\t\t\t}\n\t\t\t]\n\t\t}\n\t]\n}\n"
  },
  {
    "path": "external/CMSIS_5/.github/linkchecker.json",
    "content": "{\n\t\"problemMatcher\": [\n\t\t{\n\t\t\t\"owner\": \"fileheader\",\n\t\t\t\"severity\": \"error\",\n\t\t\t\"pattern\": [\n\t\t\t\t{\n\t\t\t\t\t\"regexp\": \"^(.*):(\\\\d+);(.*);(.*)$\",\n\t\t\t\t\t\"file\": 1,\n\t\t\t\t\t\"line\": 2,\n\t\t\t\t\t\"message\": 4\n\t\t\t\t}\n\t\t\t]\n\t\t}\n\t]\n}\n"
  },
  {
    "path": "external/CMSIS_5/.github/workflows/caller-corevalidation.yml",
    "content": "name: Caller CoreValidation\non:\n  push:\n    branches: [ main ]\n  pull_request:\n    paths:\n      - .github/workflows/caller-corevalidation.yml\n      - CMSIS/Core/**/*\n      - CMSIS/Core_A/**/*\n      - CMSIS/CoreValidation/**/*\n      - Device/ARM/**/*\n  workflow_dispatch:\n\njobs:\n  upload_pr_number:\n    runs-on: ubuntu-latest\n    steps:\n      - name: Save PR number\n        env:\n          PR_NUMBER: ${{ github.event.number }}\n        run: |\n          mkdir -p ./pr\n          echo -n $PR_NUMBER > ./pr/pr_number\n      - uses: actions/upload-artifact@v3\n        with:\n          name: pr_number\n          path: pr/\n"
  },
  {
    "path": "external/CMSIS_5/.github/workflows/codeql-analysis.yml",
    "content": "name: \"CodeQL\"\n\non:\n  workflow_dispatch:\n  push:\n    branches: [ develop ]\n    paths:\n      - 'CMSIS/Core/**'\n      - 'CMSIS/Core_A/**'\n      - 'CMSIS/CoreValidation/**'\n      - 'Device/ARM/**'\n  pull_request:\n    branches: [ develop ]\n    paths:\n      - '.github/workflows/codeql-analysis.yml'\n      - 'CMSIS/Core/**'\n      - 'CMSIS/Core_A/**'\n      - 'CMSIS/CoreValidation/**'\n      - 'Device/ARM/**'\njobs:\n  analyze:\n    name: Analyze\n    runs-on: ubuntu-latest\n    permissions:\n      actions: read\n      contents: read\n      security-events: write\n    env:\n      CMSIS_PACK_ROOT: /tmp/.packs-${{ github.run_id }}\n\n    steps:\n    - name: Checkout repository\n      uses: actions/checkout@v3\n\n    - name: Install build dependencies\n      run: |\n        sudo apt install gcc-arm-none-eabi ninja-build cmake\n\n    - name: Cache pack folder\n      id: cache-packs\n      uses: actions/cache@v3\n      with:\n        key: packs-${{ github.run_id }}\n        restore-keys: |\n          packs-\n        path: /tmp/.packs-${{ github.run_id }}\n\n    - name: Install CMSIS-Toolbox\n      run: |\n        wget https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases/download/1.5.0/cmsis-toolbox.sh\n        chmod +x cmsis-toolbox.sh\n        sudo ./cmsis-toolbox.sh <<EOI\n        /opt/ctools\n        $CMSIS_PACK_ROOT\n\n\n        $(dirname $(which arm-none-eabi-gcc 2>/dev/null))\n\n        EOI\n        echo \"/opt/ctools/bin\" >> $GITHUB_PATH\n        echo \"cpackget : $(which cpackget)\"\n        echo \"csolution: $(which csolution)\"\n        echo \"cbuild   : $(which cbuild)\"\n\n    - name: Initialize packs folder\n      if: steps.cache-packs.outputs.cache-hit != 'true'\n      run: cpackget init https://www.keil.com/pack/index.pidx\n\n    - name: Update pack index\n      if: steps.cache-packs.outputs.cache-hit == 'true'\n      run: cpackget update-index\n\n    - name: Install build.py requirements\n      run: pip install -r requirements.txt\n      working-directory: CMSIS/CoreValidation/Project\n\n    # Initializes the CodeQL tools for scanning.\n    - name: Initialize CodeQL\n      uses: github/codeql-action/init@v2\n      with:\n        languages: cpp\n        queries: security-and-quality\n\n    - name: Build projects\n      working-directory: CMSIS/CoreValidation/Project\n      run: |\n        pip install -r requirements.txt\n        cpackget add -a -f cpacklist.txt\n        python build.py --verbose -c GCC -d \"CM[047]*\" -d \"CM[23]3*\" -o low build || echo \"Something failed!\"\n\n    - name: Perform CodeQL Analysis\n      uses: github/codeql-action/analyze@v2\n"
  },
  {
    "path": "external/CMSIS_5/.github/workflows/corevalidation-report.yml",
    "content": "name: Publish CoreValidation Test Results\n\non:\n  workflow_run:\n    workflows: [\"CoreValidation\"]\n    branches-ignore: [\"develop\"]\n    types:\n      - completed\n\njobs:\n  publish-test-results:\n    name: Publish CoreValidation Test Results\n    runs-on: ubuntu-latest\n    permissions:\n      contents: read\n      issues: read\n      checks: write\n      pull-requests: write\n    if: github.event.workflow_run.conclusion != 'skipped'\n\n    steps:\n      - name: Download test results\n        env:\n          GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}\n        run: |\n           mkdir -p artifacts && cd artifacts\n\n           artifacts_url=${{ github.event.workflow_run.artifacts_url }}\n\n           gh api \"$artifacts_url\" -q '.artifacts[] | select(.name==\"tests\" or .name==\"EventFile\") | [.name, .archive_download_url] | @tsv' | \\\n           while read artifact; do\n             IFS=$'\\t' read name url <<< \"$artifact\"\n             gh api $url > \"$name.zip\"\n             unzip -d \"$name\" \"$name.zip\"\n           done\n\n      - name: Publish Test Results\n        uses: EnricoMi/publish-unit-test-result-action@v2\n        with:\n          commit: ${{ github.event.workflow_run.head_sha }}\n          event_file: artifacts/EventFile/event.json\n          report_individual_runs: true\n          event_name: ${{ github.event.workflow_run.event }}\n          junit_files: \"artifacts/**/*.junit\"\n"
  },
  {
    "path": "external/CMSIS_5/.github/workflows/corevalidation.yml",
    "content": "# This workflow is triggered whenever \"Caller CoreValidation\" workflow is completed (which is called by PR).\n# This workflow ideally should be triggered also by PR, but forked PR has limited permissions which does not\n# allow to use `configure-aws-credentials` actions and using secrets.\n# It will update its status back to the caller PR as \"CoreValidation\" check name\nname: CoreValidation\non:\n  workflow_run:\n    workflows:\n      - Caller CoreValidation\n    types:\n      - completed\n\n# The env variables relate to an ARM AWS account for CMSIS_5\n# If you are forking CMSIS_5 repo, please use your own info.\nenv:\n  AWS_ASSUME_ROLE: ${{ secrets.AWS_ASSUME_ROLE }}\n  AWS_DEFAULT_REGION: ${{ secrets.AWS_DEFAULT_REGION }}\n  AWS_IAM_PROFILE: ${{ secrets.AWS_IAM_PROFILE }}\n  AWS_S3_BUCKET_NAME: ${{ secrets.AWS_S3_BUCKET_NAME }}\n  AWS_SECURITY_GROUP_ID: ${{ secrets.AWS_SECURITY_GROUP_ID }}\n  AWS_SUBNET_ID: ${{ secrets.AWS_SUBNET_ID }}\n\njobs:\n  set_pending_status_to_pr:\n    runs-on: ubuntu-latest\n    steps:\n      - name: Set a pending status to the PR\n        env:\n          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}\n        run: |\n          curl --request POST \\\n            --url https://api.github.com/repos/${{ github.repository }}/statuses/${{ github.event.workflow_run.head_commit.id }} \\\n            --header \"authorization: Bearer ${{ secrets.GITHUB_TOKEN }}\" \\\n            --header 'content-type: application/json' \\\n            --data '{\n              \"state\": \"pending\",\n              \"context\": \"CoreValidation\",\n              \"target_url\": \"https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id\t}}\"\n              }' \\\n            --fail\n\n  ci_test:\n    runs-on: ubuntu-latest\n    needs: set_pending_status_to_pr\n    permissions:\n      id-token: write\n      contents: read\n    outputs:\n      avhresult: ${{ steps.avh.conclusion }}\n      testbadge: ${{ steps.avh.outputs.badge }}\n    steps:\n    - name: Download workflow artifact\n      uses: dawidd6/action-download-artifact@v2\n      with:\n        github_token: ${{ secrets.GITHUB_TOKEN }}\n        workflow: caller-corevalidation.yml\n        run_id: ${{ github.event.workflow_run.id }}\n\n    - name: Read the pr_num file\n      id: pr_num_reader\n      uses: juliangruber/read-file-action@v1.1.6\n      with:\n        path: ./pr_number/pr_number\n        trim: true\n\n    - name: Clone this repo\n      uses: actions/checkout@v3\n      with:\n        fetch-depth: 0\n\n    - name: Checkout PR\n      env:\n        GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}\n      run: |\n        gh pr checkout ${{ steps.pr_num_reader.outputs.content }}\n\n    - name: Set up Python 3.10\n      uses: actions/setup-python@v4\n      with:\n        python-version: '3.10'\n\n    - name: Install AVH Client for Python\n      run: |\n        pip install git+https://github.com/ARM-software/avhclient.git@v0.1\n\n    - uses: ammaraskar/gcc-problem-matcher@master\n\n    - name: Configure AWS Credentials\n      uses: aws-actions/configure-aws-credentials@v1-node16\n      with:\n        role-to-assume: ${{ env.AWS_ASSUME_ROLE }}\n        aws-region: ${{ env.AWS_DEFAULT_REGION }}\n\n    - name: Run tests\n      id: avh\n      run: |\n        avhclient -b aws execute --specfile CMSIS/CoreValidation/Project/avh.yml\n\n    - name: Archive build results\n      uses: actions/upload-artifact@v3\n      with:\n        name: builds\n        path: CMSIS/CoreValidation/Project/Core_Validation-*.zip\n        retention-days: 1\n        if-no-files-found: error\n      if: always()\n\n    - name: Archive test results\n      uses: actions/upload-artifact@v3\n      with:\n        name: tests\n        path: CMSIS/CoreValidation/Project/Core_Validation-*.junit\n        retention-days: 1\n        if-no-files-found: error\n      if: always()\n\n    - name: Archive event file\n      uses: actions/upload-artifact@v3\n      with:\n        name: EventFile\n        path: ${{ github.event_path }}\n\n  set_success_status_to_pr:\n    runs-on: ubuntu-latest\n    needs: ci_test\n    if: ${{ success() }}\n    steps:\n      - name: Set success status to the PR\n        env:\n          GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}\n        run: |\n          curl --request POST \\\n            --url https://api.github.com/repos/${{ github.repository }}/statuses/${{ github.event.workflow_run.head_commit.id }} \\\n            --header \"authorization: Bearer ${{ secrets.GITHUB_TOKEN }}\" \\\n            --header 'content-type: application/json' \\\n            --data '{\n              \"state\": \"success\",\n              \"context\": \"CoreValidation\",\n              \"target_url\": \"https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id\t}}\"\n              }' \\\n            --fail\n\n  set_failure_status_to_pr:\n    runs-on: ubuntu-latest\n    needs: ci_test\n    if: ${{ failure() }}\n    steps:\n      - name: Set failure status to the PR\n        env:\n          GITHUB_TOKEN: ${{secrets.GITHUB_TOKEN}}\n        run: |\n          curl --request POST \\\n            --url https://api.github.com/repos/${{ github.repository }}/statuses/${{ github.event.workflow_run.head_commit.id }} \\\n            --header \"authorization: Bearer ${{ secrets.GITHUB_TOKEN }}\" \\\n            --header 'content-type: application/json' \\\n            --data '{\n              \"state\": \"failure\",\n              \"context\": \"CoreValidation\",\n              \"target_url\": \"https://github.com/${{ github.repository }}/actions/runs/${{ github.run_id\t}}\"\n              }' \\\n            --fail\n"
  },
  {
    "path": "external/CMSIS_5/.github/workflows/fileheader.yml",
    "content": "name: File header\n\non:\n  pull_request:\n    branches: [ develop ]\n    paths:\n      - 'CMSIS/Core/**'\n      - 'CMSIS/Core_A/**'\n      - 'CMSIS/RTOS2/Include/**'\n      - 'CMSIS/RTOS2/Source/**'\n      - 'Device/**'\n\npermissions:\n  contents: read\n  pull-requests: write\n\njobs:\n  check:\n    name: Check file header\n    runs-on: ubuntu-latest\n    steps:\n    - name: Calculate depth\n      id: depth\n      run: |\n        echo ::set-output name=GIT_COMMITS::$((${{ github.event.pull_request.commits }} + 1))\n    - name: Checkout repository\n      uses: actions/checkout@v2\n      with:\n        ref: ${{ github.event.pull_request.head.sha }}\n        fetch-depth: ${{ steps.depth.outputs.GIT_COMMITS }}\n    - id: files\n      uses: jitterbit/get-changed-files@v1\n    - name: Check changed files\n      run: |\n        echo \"GIT_COMMITS=${{ steps.depth.outputs.GIT_COMMITS }}\"\n        echo \"::add-matcher::.github/fileheader.json\"\n        RC=0\n        for changed_file in ${{ steps.files.outputs.added_modified }}; do\n          ./CMSIS/Utilities/check_header.sh -v -b HEAD~${{ github.event.pull_request.commits }} ${changed_file} || RC=1\n        done\n        echo \"::remove-matcher owner=fileheader::\"\n        exit $RC\n"
  },
  {
    "path": "external/CMSIS_5/.github/workflows/gh-pages.yaml",
    "content": "name: Publish Documentation\non:\n  workflow_dispatch:\n  pull_request:\n    branches: [ develop ]\n    paths:\n      - '.github/workflows/gh-pages.yaml'\n      - 'CMSIS/Utilities/check_links.sh'\n      - 'CMSIS/DoxyGen/**'\n  push:\n    branches: [ develop ]\n    paths:\n      - '.github/workflows/gh-pages.yaml'\n      - 'CMSIS/Utilities/check_links.sh'\n      - 'CMSIS/DoxyGen/**'\njobs:\n  docs:\n    name: Build develop documentation\n    runs-on: ubuntu-20.04\n    steps:\n      - uses: actions/checkout@v2\n      - uses: actions/setup-node@v1\n      - name: Install Doxygen 1.8.6\n        run: |\n          wget http://archive.ubuntu.com/ubuntu/pool/main/d/doxygen/doxygen_1.8.6-2_amd64.deb\n          sudo dpkg -i doxygen_1.8.6-2_amd64.deb\n      - name: Install mscgen 0.20\n        run: |\n          sudo apt-get update\n          sudo apt-get install --no-install-recommends -y mscgen=0.20-12\n      - name: Install linkchecker\n        run: |\n          sudo pip install LinkChecker\n      - name: Generate doxygen\n        run: CMSIS/DoxyGen/gen_doc.sh\n      - name: Run linkchecker\n        run: |\n          echo \"::add-matcher::.github/linkchecker.json\"\n          CMSIS/Utilities/check_links.sh CMSIS/Documentation/index.html\n      - name: Upload documentation\n        if: ${{ github.event_name == 'pull_request' }}\n        uses: actions/upload-artifact@v2\n        with:\n          path: CMSIS/Documentation/**\n      - name: Archive documentation\n        if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }}\n        run: |\n          cd CMSIS/Documentation\n          tar -cvjf /tmp/doc.tbz2 .\n      - uses: actions/checkout@v2\n        if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }}\n        with:\n          ref: gh-pages\n      - name: Publish documentation\n        if: ${{ github.event_name == 'push' || github.event_name == 'workflow_dispatch' }}\n        run: |\n          rm -r develop\n          mkdir develop\n          cd develop\n          tar -xvjf /tmp/doc.tbz2\n          git config user.name github-actions\n          git config user.email github-actions@github.com\n          git add .\n          git commit -m \"Update develop documentation\"\n          git push\n"
  },
  {
    "path": "external/CMSIS_5/.github/workflows/packdesc.yml",
    "content": "name: Pack Description\n\non:\n  pull_request:\n    branches: [ develop ]\n    paths:\n      - 'ARM.CMSIS.pdsc'\n\npermissions:\n  contents: read\n  pull-requests: write\n\njobs:\n  check:\n    name: Check pack description schema\n    runs-on: ubuntu-latest\n    steps:\n    - name: Install xmllint\n      run: |\n        sudo apt-get update\n        sudo apt-get install libxml2-utils\n    - name: Checkout repository\n      uses: actions/checkout@v2\n      with:\n        ref: ${{ github.event.pull_request.head.sha }}\n    - name: Run xmllint\n      run: |\n        curl https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/main/schema/PACK.xsd -o CMSIS/Utilities/PACK.xsd\n        echo \"::add-matcher::.github/xmllint.json\"\n        xmllint --noout --schema \"$(realpath -m ./CMSIS/Utilities/PACK.xsd)\" \"ARM.CMSIS.pdsc\"\n        echo \"::remove-matcher owner=xmllint::\"\n"
  },
  {
    "path": "external/CMSIS_5/.github/workflows/release.yaml",
    "content": "name: Release Documentation\non:\n  release:\n    types: [published]\njobs:\n  docs:\n    name: Build release documentation\n    runs-on: ubuntu-20.04\n    steps:\n      - uses: actions/checkout@v2\n      - uses: actions/setup-node@v1\n      - name: Install Doxygen 1.8.6\n        run: |\n          wget http://archive.ubuntu.com/ubuntu/pool/main/d/doxygen/doxygen_1.8.6-2_amd64.deb\n          sudo dpkg -i doxygen_1.8.6-2_amd64.deb\n      - name: Install mscgen 0.20\n        run: |\n          sudo apt-get update\n          sudo apt-get install --no-install-recommends -y mscgen=0.20-12\n      - name: Generate doxygen\n        run: CMSIS/DoxyGen/gen_doc.sh\n      - name: Archive documentation\n        run: |\n          cd CMSIS/Documentation\n          tar -cvjf /tmp/doc.tbz2 .\n      - uses: actions/checkout@v2\n        with:\n          ref: gh-pages\n      - name: Publish documentation\n        run: |\n          RELEASE=$(echo $GITHUB_REF | sed 's/refs\\/tags\\///')\n          mkdir ${RELEASE}\n          rm latest\n          ln -s ${RELEASE} latest\n          cd ${RELEASE}\n          tar -xvjf /tmp/doc.tbz2\n          git config user.name github-actions\n          git config user.email github-actions@github.com\n          git add . ../latest\n          git commit -m \"Update documentation for release ${RELEASE}\"\n          git push\n"
  },
  {
    "path": "external/CMSIS_5/.github/xmllint.json",
    "content": "{\n  \"problemMatcher\": [\n    {\n      \"owner\": \"xmllint\",\n      \"severity\": \"error\",\n      \"pattern\": [\n        {\n          \"regexp\": \"^(.*):(\\\\d+):(.*)$\",\n          \"file\": 1,\n          \"line\": 2,\n          \"message\": 3\n        }\n      ]\n    }\n  ]\n}\n"
  },
  {
    "path": "external/CMSIS_5/.gitignore",
    "content": "*.breadcrumb\n*.junit\n**/__pycache__\nLocal_Release/\nCMSIS/Documentation/\nCMSIS/RTOS2/RTX/Library/ARM/MDK/RTX_CM.uvguix.*\nCMSIS/CoreValidation/Project/*.zip\nCMSIS/CoreValidation/Project/*.junit\nCMSIS/CoreValidation/Project/Validation.*/\nCMSIS/CoreValidation/Project/Bootloader.*/\n*.uvguix.*\n*.uvmpw.uvgui.*\n*.zip\ndocker/dependenciesFiles\nCMSIS/RTOS/RTX/LIB/**/*.a\nCMSIS/RTOS/RTX/LIB/**/*.lib\nCMSIS/RTOS2/RTX/Library/**/*.a\nCMSIS/RTOS2/RTX/Library/**/*.lib\noutput\n.DS_Store\ninternal.cp310-win_amd64.pyd\nCMSIS/Utilities/Darwin64\nCMSIS/Utilities/Linux64\nCMSIS/Utilities/Win32\n"
  },
  {
    "path": "external/CMSIS_5/ARM.CMSIS.pdsc",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n\n<package schemaVersion=\"1.7.7\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/v1.7.7/schema/PACK.xsd\">\n  <name>CMSIS</name>\n  <description>CMSIS (Common Microcontroller Software Interface Standard)</description>\n  <vendor>ARM</vendor>\n  <!-- <license>license.txt</license> -->\n  <url>https://www.keil.com/pack/</url>\n\n  <releases>\n    <release version=\"5.9.1\">\n      Active development ...\n      CMSIS-Core(M): 5.7.0\n       - Added new compiler macros.\n      CMSIS-DSP: Moved into separate pack!\n      CMSIS-NN: Moved into separate pack!\n      CMSIS-RTOS2: 2.2.0 (see revision history for details)\n        - RTX 5.7.0 (see revision history for details)\n      CMSIS-DAP: 2.1.2 (see revision history for details)\n       - Fix DAP_Transfer handling when transfer fails\n    </release>\n    <release version=\"5.9.0\" date=\"2022-05-02\">\n      CMSIS-Core(M): 5.6.0\n       - Arm Cortex-M85 cpu support\n       - Arm China STAR-MC1 cpu support\n       - Updated system_ARMCM55.c\n      CMSIS-DSP: 1.10.0 (see revision history for details)\n      CMSIS-NN: 3.1.0 (see revision history for details)\n       - Support for int16 convolution and fully connected for reference implementation\n       - Support for DSP extension optimization for int16 convolution and fully connected\n       - Support dilation for int8 convolution\n       - Support dilation for int8 depthwise convolution\n       - Support for int16 depthwise conv for reference implementation including dilation\n       - Support for int16 average and max pooling for reference implementation\n       - Support for elementwise add and mul int16 scalar version\n       - Support for softmax int16 scalar version\n       - Support for SVDF with 8 bit state tensor\n      CMSIS-RTOS2: 2.1.3 (unchanged)\n        - RTX 5.5.4 (see revision history for details)\n      CMSIS-Pack: deprecated (moved to Open-CMSIS-Pack)\n      CMSIS-SVD: 1.3.9 (see revision history for details)\n      CMSIS-DAP: 2.1.1 (see revision history for details)\n       - Allow default clock frequency to use fast clock mode\n      Devices\n       - Support for Cortex-M85\n      Utilities\n        - SVDConv 3.3.42\n        - PackChk 1.3.95\n    </release>\n    <release version=\"5.8.0\" date=\"2021-06-24\">\n      CMSIS-Core(M): 5.5.0 (see revision history for details)\n        - Updated GCC LinkerDescription, GCC Assembler startup\n        - Added Armv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC\n        - Changed C-Startup to default Startup.\n        - Updated Armv8-M Assembler startup to use GAS syntax\n          Note: Updating existing projects may need manual user interaction!\n      CMSIS-Core(A): 1.2.1 (see revision history for details)\n        - Bugfixes for Cortex-A32\n      CMSIS-DAP: 2.1.0 (see revision history for details)\n        - Enhanced DAP_Info\n        - Added extra UART support\n      CMSIS-DSP: 1.9.0 (see revision history for details)\n        - Purged pre-built libs from Git\n        - Enhanced support for f16 datatype\n        - Fixed couple of GCC issues\n      CMSIS-NN: 3.0.0 (see revision history for details including version 2.0.0)\n        - Major interface change for functions compatible with TensorFlow Lite for Microcontroller\n        - Added optimization for SVDF kernel\n        - Improved MVE performance for fully Connected and max pool operator\n        - NULL bias support for fully connected operator in non-MVE case(Can affect performance)\n        - Expanded existing unit test suite along with support for FVP\n        - Removed Examples folder\n      CMSIS-RTOS2:\n        - RTX 5.5.3 (see revision history for details)\n          - CVE-2021-27431 vulnerability mitigation.\n          - Enhanced stack overrun checking.\n          - Various bug fixes and improvements.\n      CMSIS-Pack: 1.7.2 (see revision history for details)\n        - Support for Microchip XC32 compiler\n        - Support for Custom Datapath Extension\n    </release>\n    <release version=\"5.7.0\" date=\"2020-04-09\">\n      CMSIS-Build: 0.9.0 (beta)\n        - Draft for CMSIS Project description (CPRJ)\n      CMSIS-Core(M): 5.4.0 (see revision history for details)\n        - Cortex-M55 cpu support\n        - Enhanced MVE support for Armv8.1-MML\n        - Fixed device config define checks.\n        - L1 Cache functions for Armv7-M and later\n      CMSIS-Core(A): 1.2.0 (see revision history for details)\n        - Fixed GIC_SetPendingIRQ to use GICD_SGIR\n        - Added missing DSP intrinsics\n        - Reworked assembly intrinsics: volatile, barriers and clobber\n      CMSIS-DSP: 1.8.0 (see revision history for details)\n        - Added new functions and function groups\n        - Added MVE support\n      CMSIS-NN: 1.3.0 (see revision history for details)\n        - Added MVE support\n        - Further optimizations for kernels using DSP extension\n      CMSIS-RTOS2:\n        - RTX 5.5.2 (see revision history for details)\n      CMSIS-Driver: 2.8.0\n        - Added VIO API 0.1.0 (Preview)\n        - removed volatile from status related typedefs in APIs\n        - enhanced WiFi Interface API with support for polling Socket Receive/Send\n      CMSIS-Pack: 1.6.3 (see revision history for details)\n        - deprecating all types specific to cpdsc format. Cpdsc is replaced by Cprj with dedicated schema.\n      Devices:\n        - ARMCM55 device\n        - ARMv81MML startup code recognizing __MVE_USED macro\n        - Refactored vector table references for all Cortex-M devices\n        - Reworked ARMCM* C-StartUp files.\n        - Include L1 Cache functions in ARMv8MML/ARMv81MML devices\n      Utilities:\n        Attention: Linux binaries moved to Linux64 folder!\n        - SVDConv 3.3.35\n        - PackChk 1.3.89\n    </release>\n    <release version=\"5.6.0\" date=\"2019-07-10\">\n      CMSIS-Core(M): 5.3.0 (see revision history for details)\n        - Added provisions for compiler-independent C startup code.\n      CMSIS-Core(A): 1.1.4 (see revision history for details)\n        - Fixed __FPU_Enable.\n      CMSIS-DSP: 1.7.0 (see revision history for details)\n        - New Neon versions of f32 functions\n        - Python wrapper\n        - Preliminary cmake build\n        - Compilation flags for FFTs\n        - Changes to arm_math.h\n      CMSIS-NN: 1.2.0 (see revision history for details)\n        - New function for depthwise convolution with asymmetric quantization.\n        - New support functions for requantization.\n      CMSIS-RTOS:\n        - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+)\n      CMSIS-RTOS2:\n        - RTX 5.5.1 (see revision history for details)\n      CMSIS-Driver: 2.7.1\n        - WiFi Interface API 1.0.0\n      Devices:\n        - Generalized C startup code for all Cortex-M family devices.\n        - Updated Cortex-A default memory regions and MMU configurations\n        - Moved Cortex-A memory and system config files to avoid include path issues\n    </release>\n    <release version=\"5.5.1\" date=\"2019-03-20\">\n      The following folders are deprecated\n        - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/)\n\n      CMSIS-Core(M): 5.2.1 (see revision history for details)\n        - Fixed compilation issue in cmsis_armclang_ltm.h\n    </release>\n    <release version=\"5.5.0\" date=\"2019-03-18\">\n      The following folders have been removed:\n        - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/)\n        - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/)\n      The following folders are deprecated\n        - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/)\n\n      CMSIS-Core(M): 5.2.0 (see revision history for details)\n        - Reworked Stack/Heap configuration for ARM startup files.\n        - Added Cortex-M35P device support.\n        - Added generic Armv8.1-M Mainline device support.\n      CMSIS-Core(A): 1.1.3 (see revision history for details)\n      CMSIS-DSP: 1.6.0 (see revision history for details)\n        - reworked DSP library source files\n        - reworked DSP library documentation\n        - Changed DSP folder structure\n        - moved DSP libraries to folder ./DSP/Lib\n        - ARM DSP Libraries are built with ARMCLANG\n        - Added DSP Libraries Source variant\n      CMSIS-RTOS2:\n        - RTX 5.5.0 (see revision history for details)\n      CMSIS-Driver: 2.7.0\n        - Added WiFi Interface API 1.0.0-beta\n        - Added components for project specific driver implementations\n      CMSIS-Pack: 1.6.0 (see revision history for details)\n      Devices:\n        - Added Cortex-M35P and ARMv81MML device templates.\n        - Fixed C-Startup Code for GCC (aligned with other compilers)\n      Utilities:\n        - SVDConv 3.3.25\n        - PackChk 1.3.82\n    </release>\n    <release version=\"5.4.0\" date=\"2018-08-01\">\n      Aligned pack structure with repository.\n      The following folders are deprecated:\n        - CMSIS/Include/\n        - CMSIS/DSP_Lib/\n\n      CMSIS-Core(M): 5.1.2 (see revision history for details)\n        - Added Cortex-M1 support (beta).\n      CMSIS-Core(A): 1.1.2 (see revision history for details)\n      CMSIS-NN: 1.1.0\n        - Added new math functions.\n      CMSIS-RTOS2:\n        - API 2.1.3 (see revision history for details)\n        - RTX 5.4.0 (see revision history for details)\n          * Updated exception handling on Cortex-A\n      CMSIS-Driver:\n        - Flash Driver API V2.2.0\n      Utilities:\n        - SVDConv 3.3.21\n        - PackChk 1.3.71\n    </release>\n    <release version=\"5.3.0\" date=\"2018-02-22\">\n      Updated Arm company brand.\n      CMSIS-Core(M): 5.1.1 (see revision history for details)\n      CMSIS-Core(A): 1.1.1 (see revision history for details)\n      CMSIS-DAP: 2.0.0 (see revision history for details)\n      CMSIS-NN: 1.0.0\n        - Initial contribution of the bare metal Neural Network Library.\n      CMSIS-RTOS2:\n        - RTX 5.3.0 (see revision history for details)\n        - OS Tick API 1.0.1\n    </release>\n    <release version=\"5.2.0\" date=\"2017-11-16\">\n      CMSIS-Core(M): 5.1.0 (see revision history for details)\n        - Added MPU Functions for ARMv8-M for Cortex-M23/M33.\n        - Added compiler_iccarm.h to replace compiler_iar.h shipped with the compiler.\n      CMSIS-Core(A): 1.1.0 (see revision history for details)\n        - Added compiler_iccarm.h.\n        - Added additional access functions for physical timer.\n      CMSIS-DAP: 1.2.0 (see revision history for details)\n      CMSIS-DSP: 1.5.2 (see revision history for details)\n      CMSIS-Driver: 2.6.0 (see revision history for details)\n        - CAN Driver API V1.2.0\n        - NAND Driver API V2.3.0\n      CMSIS-RTOS:\n        - RTX: added variant for Infineon XMC4 series affected by PMU_CM.001 errata.\n      CMSIS-RTOS2:\n        - API 2.1.2 (see revision history for details)\n        - RTX 5.2.3 (see revision history for details)\n      Devices:\n        - Added GCC startup and linker script for Cortex-A9.\n        - Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.\n        - Added IAR startup code for Cortex-A9\n    </release>\n    <release version=\"5.1.1\" date=\"2017-09-19\">\n      CMSIS-RTOS2:\n      - RTX 5.2.1 (see revision history for details)\n    </release>\n    <release version=\"5.1.0\" date=\"2017-08-04\">\n      CMSIS-Core(M): 5.0.2 (see revision history for details)\n      - Changed Version Control macros to be core agnostic.\n      - Added MPU Functions for ARMv7-M for Cortex-M0+/M3/M4/M7.\n      CMSIS-Core(A): 1.0.0 (see revision history for details)\n      - Initial release\n      - IRQ Controller API 1.0.0\n      CMSIS-Driver: 2.05 (see revision history for details)\n      - All typedefs related to status have been made volatile.\n      CMSIS-RTOS2:\n      - API 2.1.1 (see revision history for details)\n      - RTX 5.2.0 (see revision history for details)\n      - OS Tick API 1.0.0\n      CMSIS-DSP: 1.5.2 (see revision history for details)\n      - Fixed GNU Compiler specific diagnostics.\n      CMSIS-Pack: 1.5.0 (see revision history for details)\n      - added System Description File (*.SDF) Format\n      CMSIS-Zone: 0.0.1 (Preview)\n      - Initial specification draft\n    </release>\n    <release version=\"5.0.1\" date=\"2017-02-03\">\n      Package Description:\n      - added taxonomy for Cclass RTOS\n      CMSIS-RTOS2:\n      - API 2.1   (see revision history for details)\n      - RTX 5.1.0 (see revision history for details)\n      CMSIS-Core: 5.0.1 (see revision history for details)\n      - Added __PACKED_STRUCT macro\n      - Added uVisior support\n      - Updated cmsis_armcc.h: corrected macro __ARM_ARCH_6M__\n      - Updated template for secure main function (main_s.c)\n      - Updated template for Context Management for ARMv8-M TrustZone (tz_context.c)\n      CMSIS-DSP: 1.5.1 (see revision history for details)\n      - added ARMv8M DSP libraries.\n      CMSIS-Pack:1.4.9 (see revision history for details)\n      - added Pack Index File specification and schema file\n    </release>\n    <release version=\"5.0.0\" date=\"2016-11-11\">\n      Changed open source license to Apache 2.0\n      CMSIS_Core:\n       - Added support for Cortex-M23 and Cortex-M33.\n       - Added ARMv8-M device configurations for mainline and baseline.\n       - Added CMSE support and thread context management for TrustZone for ARMv8-M\n       - Added cmsis_compiler.h to unify compiler behaviour.\n       - Updated function SCB_EnableICache (for Cortex-M7).\n       - Added functions: NVIC_GetEnableIRQ, SCB_GetFPUType\n      CMSIS-RTOS:\n        - bug fix in RTX 4.82 (see revision history for details)\n      CMSIS-RTOS2:\n        - new API including compatibility layer to CMSIS-RTOS\n        - reference implementation based on RTX5\n        - supports all Cortex-M variants including TrustZone for ARMv8-M\n      CMSIS-SVD:\n       - reworked SVD format documentation\n       - removed SVD file database documentation as SVD files are distributed in packs\n       - updated SVDConv for Win32 and Linux\n      CMSIS-DSP:\n       - Moved DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.\n       - Added DSP libraries build projects to CMSIS pack.\n    </release>\n    <release version=\"4.5.0\" date=\"2015-10-28\">\n      - CMSIS-Core     4.30.0  (see revision history for details)\n      - CMSIS-DAP      1.1.0   (unchanged)\n      - CMSIS-Driver   2.04.0  (see revision history for details)\n      - CMSIS-DSP      1.4.7   (no source code change [still labeled 1.4.5], see revision history for details)\n      - CMSIS-Pack     1.4.1   (see revision history for details)\n      - CMSIS-RTOS     4.80.0  Restored time delay parameter 'millisec' old behavior (prior V4.79) for software compatibility. (see revision history for details)\n      - CMSIS-SVD      1.3.1   (see revision history for details)\n    </release>\n    <release version=\"4.4.0\" date=\"2015-09-11\">\n      - CMSIS-Core     4.20   (see revision history for details)\n      - CMSIS-DSP      1.4.6  (no source code change [still labeled 1.4.5], see revision history for details)\n      - CMSIS-Pack     1.4.0  (adding memory attributes, algorithm style)\n      - CMSIS-Driver   2.03.0 (adding CAN [Controller Area Network] API)\n      - CMSIS-RTOS\n        -- API         1.02   (unchanged)\n        -- RTX         4.79   (see revision history for details)\n      - CMSIS-SVD      1.3.0  (see revision history for details)\n      - CMSIS-DAP      1.1.0  (extended with SWO support)\n    </release>\n    <release version=\"4.3.0\" date=\"2015-03-20\">\n      - CMSIS-Core     4.10   (Cortex-M7 extended Cache Maintenance functions)\n      - CMSIS-DSP      1.4.5  (see revision history for details)\n      - CMSIS-Driver   2.02   (adding SAI (Serial Audio Interface) API)\n      - CMSIS-Pack     1.3.3  (Semantic Versioning, Generator extensions)\n      - CMSIS-RTOS\n        -- API         1.02   (unchanged)\n        -- RTX         4.78   (see revision history for details)\n      - CMSIS-SVD      1.2    (unchanged)\n    </release>\n    <release version=\"4.2.0\" date=\"2014-09-24\">\n      Adding Cortex-M7 support\n      - CMSIS-Core     4.00  (Cortex-M7 support, corrected C++ include guards in core header files)\n      - CMSIS-DSP      1.4.4 (Cortex-M7 support and corrected out of bound issues)\n      - CMSIS-Pack     1.3.1 (Cortex-M7 updates, clarification, corrected batch files in Tutorial)\n      - CMSIS-SVD      1.2   (Cortex-M7 extensions)\n      - CMSIS-RTOS RTX 4.75  (see revision history for details)\n    </release>\n    <release version=\"4.1.1\" date=\"2014-06-30\">\n      - fixed conditions preventing the inclusion of the DSP library in projects for Infineon XMC4000 series devices\n    </release>\n    <release version=\"4.1.0\" date=\"2014-06-12\">\n      - CMSIS-Driver   2.02  (incompatible update)\n      - CMSIS-Pack     1.3   (see revision history for details)\n      - CMSIS-DSP      1.4.2 (unchanged)\n      - CMSIS-Core     3.30  (unchanged)\n      - CMSIS-RTOS RTX 4.74  (unchanged)\n      - CMSIS-RTOS API 1.02  (unchanged)\n      - CMSIS-SVD      1.10  (unchanged)\n      PACK:\n      - removed G++ specific files from PACK\n      - added Component Startup variant \"C Startup\"\n      - added Pack Checking Utility\n      - updated conditions to reflect tool-chain dependency\n      - added Taxonomy for Graphics\n      - updated Taxonomy for unified drivers from \"Drivers\" to \"CMSIS Drivers\"\n    </release>\n    <!-- release version=\"4.0.0\">\n      - CMSIS-Driver   2.00  Preliminary (incompatible update)\n      - CMSIS-Pack     1.1   Preliminary\n      - CMSIS-DSP      1.4.2 (see revision history for details)\n      - CMSIS-Core     3.30  (see revision history for details)\n      - CMSIS-RTOS RTX 4.74  (see revision history for details)\n      - CMSIS-RTOS API 1.02  (unchanged)\n      - CMSIS-SVD      1.10  (unchanged)\n    </release -->\n    <release version=\"3.20.4\" date=\"2014-02-20\">\n      - CMSIS-RTOS 4.74 (see revision history for details)\n      - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1.\n    </release>\n    <!-- release version=\"3.20.3\">\n      - CMSIS-Driver API Version 1.10 ARM prefix added (incompatible change)\n      - CMSIS-RTOS 4.73 (see revision history for details)\n    </release -->\n    <!-- release version=\"3.20.2\">\n      - CMSIS-Pack documentation has been added\n      - CMSIS-Drivers header and documentation have been added to PACK\n      - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged\n    </release -->\n    <!-- release version=\"3.20.1\">\n      - CMSIS-RTOS Keil RTX V4.72 has been added to PACK\n      - CMSIS-CORE, CMSIS-DSP, CMSIS-RTOS API and CMSIS-SVD remain unchanged\n    </release -->\n    <!-- release version=\"3.20.0\">\n      The software portions that are deployed in the application program are now under a BSD license which allows usage\n      of CMSIS components in any commercial or open source projects.  The Pack Description file Arm.CMSIS.pdsc describes the use cases\n      The individual components have been update as listed below:\n      - CMSIS-CORE adds functions for setting breakpoints, supports the latest GCC Compiler, and contains several corrections.\n      - CMSIS-DSP library is optimized for more performance and contains several bug fixes.\n      - CMSIS-RTOS API is extended with capabilities for short timeouts, Kernel initialization, and prepared for a C++ interface.\n      - CMSIS-SVD is unchanged.\n    </release -->\n  </releases>\n\n  <taxonomy>\n    <description Cclass=\"Audio\">Software components for audio processing</description>\n    <description Cclass=\"Board Support\">Generic Interfaces for Evaluation and Development Boards</description>\n    <description Cclass=\"Board Part\">Drivers that support an external component available on an evaluation board</description>\n    <description Cclass=\"Compiler\">Compiler Software Extensions</description>\n    <description Cclass=\"CMSIS\" doc=\"CMSIS/Documentation/General/html/index.html\">Cortex Microcontroller Software Interface Components</description>\n    <description Cclass=\"CMSIS Driver\" doc=\"CMSIS/Documentation/Driver/html/index.html\">Unified Device Drivers compliant to CMSIS-Driver Specifications</description>\n    <description Cclass=\"Device\" doc=\"CMSIS/Documentation/Core/html/index.html\">Startup, System Setup</description>\n    <description Cclass=\"Data Exchange\">Data exchange or data formatter</description>\n    <description Cclass=\"Extension Board\">Drivers that support an extension board or shield</description>\n    <description Cclass=\"File System\">File Drive Support and File System</description>\n    <description Cclass=\"IoT Client\">IoT cloud client connector</description>\n    <description Cclass=\"IoT Service\">IoT specific services</description>\n    <description Cclass=\"IoT Utility\">IoT specific software utility</description>\n    <description Cclass=\"Graphics\">Graphical User Interface</description>\n    <description Cclass=\"Network\">Network Stack using Internet Protocols</description>\n    <description Cclass=\"RTOS\">Real-time Operating System</description>\n    <description Cclass=\"Security\">Encryption for secure communication or storage</description>\n    <description Cclass=\"USB\">Universal Serial Bus Stack</description>\n    <description Cclass=\"Utility\">Generic software utility components</description>\n  </taxonomy>\n\n  <devices>\n    <!-- ******************************  Cortex-M0  ****************************** -->\n    <family Dfamily=\"ARM Cortex M0\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/dui0497\" title=\"Cortex-M0 Processor Devices Generic Users Guide\"/>\n      <description>\nThe Cortex-M0 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:\n- simple, easy-to-use programmers model\n- highly efficient ultra-low power operation\n- excellent code density\n- deterministic, high-performance interrupt handling\n- upward compatibility with the rest of the Cortex-M processor family.\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM0.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00040000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMCM0\">\n        <processor Dcore=\"Cortex-M0\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"NO_MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM0/Include/ARMCM0.h\" define=\"ARMCM0\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M0P  ****************************** -->\n    <family Dfamily=\"ARM Cortex M0 plus\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/dui0662\" title=\"Cortex-M0+ Processor Devices Generic Users Guide\"/>\n      <description>\nThe Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:\n- simple, easy-to-use programmers model\n- highly efficient ultra-low power operation\n- excellent code density\n- deterministic, high-performance interrupt handling\n- upward compatibility with the rest of the Cortex-M processor family.\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM0P.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00040000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMCM0P\">\n        <processor Dcore=\"Cortex-M0+\" DcoreVersion=\"r0p1\" Dfpu=\"NO_FPU\" Dmpu=\"NO_MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM0plus/Include/ARMCM0plus.h\" define=\"ARMCM0P\"/>\n      </device>\n\n      <device Dname=\"ARMCM0P_MPU\">\n        <processor Dcore=\"Cortex-M0+\" DcoreVersion=\"r0p1\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h\" define=\"ARMCM0P_MPU\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M1  ****************************** -->\n    <family Dfamily=\"ARM Cortex M1\" Dvendor=\"ARM:82\">\n      <!--book name=\"https://developer.arm.com/documentation/dui0497\" title=\"Cortex-M0 Processor Devices Generic Users Guide\"/-->\n      <description>\nThe ARM Cortex-M1 FPGA processor is intended for deeply embedded applications that require a small processor integrated into an FPGA.\nThe ARM Cortex-M1 processor implements the ARMv6-M architecture profile.\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM0.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00040000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMCM1\">\n        <processor Dcore=\"Cortex-M1\" DcoreVersion=\"r1p0\" Dfpu=\"NO_FPU\" Dmpu=\"NO_MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM1/Include/ARMCM1.h\" define=\"ARMCM1\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M3  ****************************** -->\n    <family Dfamily=\"ARM Cortex M3\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/dui0552\" title=\"Cortex-M3 Processor Devices Generic Users Guide\"/>\n      <description>\nThe Cortex-M3 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:\n- simple, easy-to-use programmers model\n- highly efficient ultra-low power operation\n- excellent code density\n- deterministic, high-performance interrupt handling\n- upward compatibility with the rest of the Cortex-M processor family.\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM3.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00040000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMCM3\">\n        <processor Dcore=\"Cortex-M3\" DcoreVersion=\"r2p1\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM3/Include/ARMCM3.h\" define=\"ARMCM3\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M4  ****************************** -->\n    <family Dfamily=\"ARM Cortex M4\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/dui0553\" title=\"Cortex-M4 Processor Devices Generic Users Guide\"/>\n      <description>\nThe Cortex-M4 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:\n- simple, easy-to-use programmers model\n- highly efficient ultra-low power operation\n- excellent code density\n- deterministic, high-performance interrupt handling\n- upward compatibility with the rest of the Cortex-M processor family.\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM4.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00040000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMCM4\">\n        <processor Dcore=\"Cortex-M4\" DcoreVersion=\"r0p1\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM4/Include/ARMCM4.h\"    define=\"ARMCM4\"/>\n      </device>\n\n      <device Dname=\"ARMCM4_FP\">\n        <processor Dcore=\"Cortex-M4\" DcoreVersion=\"r0p1\" Dfpu=\"SP_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM4/Include/ARMCM4_FP.h\" define=\"ARMCM4_FP\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M7  ****************************** -->\n    <family Dfamily=\"ARM Cortex M7\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/dui0646\" title=\"Cortex-M7 Processor Devices Generic Users Guide\"/>\n      <description>\nThe Cortex-M7 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including:\n- simple, easy-to-use programmers model\n- highly efficient ultra-low power operation\n- excellent code density\n- deterministic, high-performance interrupt handling\n- upward compatibility with the rest of the Cortex-M processor family.\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM7.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00040000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMCM7\">\n        <processor Dcore=\"Cortex-M7\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM7/Include/ARMCM7.h\" define=\"ARMCM7\"/>\n      </device>\n\n      <device Dname=\"ARMCM7_SP\">\n        <processor Dcore=\"Cortex-M7\" DcoreVersion=\"r0p0\" Dfpu=\"SP_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM7/Include/ARMCM7_SP.h\" define=\"ARMCM7_SP\"/>\n      </device>\n\n      <device Dname=\"ARMCM7_DP\">\n        <processor Dcore=\"Cortex-M7\" DcoreVersion=\"r0p0\" Dfpu=\"DP_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM7/Include/ARMCM7_DP.h\" define=\"ARMCM7_DP\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M23  ********************** -->\n    <family Dfamily=\"ARM Cortex M23\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/dui1095\"       title=\"Cortex-M23 Processor Devices Generic Users Guide\"/>\n      <description>\nThe Arm Cortex-M23 is based on the Armv8-M baseline architecture.\nIt is the smallest and most energy efficient Arm processor with Arm TrustZone technology.\nCortex-M23 is the ideal processor for constrained embedded applications requiring efficient security.\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM23.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00200000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IROM2\"                                start=\"0x00200000\" size=\"0x00200000\" startup=\"0\" default=\"0\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <memory id=\"IRAM2\"                                start=\"0x20200000\" size=\"0x00020000\" init   =\"0\" default=\"0\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMCM23\">\n        <processor Dcore=\"Cortex-M23\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Dtz=\"NO_TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM23/Include/ARMCM23.h\" define=\"ARMCM23\"/>\n      </device>\n\n      <device Dname=\"ARMCM23_TZ\">\n        <processor Dcore=\"Cortex-M23\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMCM23/Include/ARMCM23_TZ.h\" define=\"ARMCM23_TZ\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M33  ****************************** -->\n    <family Dfamily=\"ARM Cortex M33\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/100235\"       title=\"Cortex-M33 Processor Devices Generic Users Guide\"/>\n      <description>\nThe Arm Cortex-M33 is the most configurable of all Cortex-M processors. It is a full featured microcontroller\nclass processor based on the Armv8-M mainline architecture with Arm TrustZone security.\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM33.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00200000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IROM2\"                                start=\"0x00200000\" size=\"0x00200000\" startup=\"0\" default=\"0\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <memory id=\"IRAM2\"                                start=\"0x20200000\" size=\"0x00020000\" init   =\"0\" default=\"0\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"          default=\"1\"/-->\n\n      <device Dname=\"ARMCM33\">\n        <processor Dcore=\"Cortex-M33\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Ddsp=\"NO_DSP\" Dtz=\"NO_TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          no DSP Instructions, no Floating Point Unit, no TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMCM33/Include/ARMCM33.h\" define=\"ARMCM33\"/>\n      </device>\n\n      <device Dname=\"ARMCM33_TZ\">\n        <processor Dcore=\"Cortex-M33\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Ddsp=\"NO_DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          no DSP Instructions, no Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMCM33/Include/ARMCM33_TZ.h\" define=\"ARMCM33_TZ\"/>\n      </device>\n\n      <device Dname=\"ARMCM33_DSP_FP\">\n        <processor Dcore=\"Cortex-M33\" DcoreVersion=\"r0p0\" Dfpu=\"SP_FPU\" Dmpu=\"MPU\" Ddsp=\"DSP\" Dtz=\"NO_TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          DSP Instructions, Single Precision Floating Point Unit, no TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h\" define=\"ARMCM33_DSP_FP\"/>\n      </device>\n\n      <device Dname=\"ARMCM33_DSP_FP_TZ\">\n        <processor Dcore=\"Cortex-M33\" DcoreVersion=\"r0p0\" Dfpu=\"SP_FPU\" Dmpu=\"MPU\" Ddsp=\"DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          DSP Instructions, Single Precision Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h\" define=\"ARMCM33_DSP_FP_TZ\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M35P  ****************************** -->\n    <family Dfamily=\"ARM Cortex M35P\" Dvendor=\"ARM:82\">\n      <!--book name=\"Device/ARM/Documents/??_dgug.pdf\"       title=\"?? Device Generic Users Guide\"/-->\n      <description>\nThe Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller\nclass processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications.\n      </description>\n\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM35P.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00200000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IROM2\"                                start=\"0x00200000\" size=\"0x00200000\" startup=\"0\" default=\"0\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <memory id=\"IRAM2\"                                start=\"0x20200000\" size=\"0x00020000\" init   =\"0\" default=\"0\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"          default=\"1\"/-->\n\n      <device Dname=\"ARMCM35P\">\n        <processor Dcore=\"Cortex-M35P\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Ddsp=\"NO_DSP\" Dtz=\"NO_TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          no DSP Instructions, no Floating Point Unit, no TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMCM35P/Include/ARMCM35P.h\" define=\"ARMCM35P\"/>\n      </device>\n\n      <device Dname=\"ARMCM35P_TZ\">\n        <processor Dcore=\"Cortex-M35P\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Ddsp=\"NO_DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          no DSP Instructions, no Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h\" define=\"ARMCM35P_TZ\"/>\n      </device>\n\n      <device Dname=\"ARMCM35P_DSP_FP\">\n        <processor Dcore=\"Cortex-M35P\" DcoreVersion=\"r0p0\" Dfpu=\"SP_FPU\" Dmpu=\"MPU\" Ddsp=\"DSP\" Dtz=\"NO_TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          DSP Instructions, Single Precision Floating Point Unit, no TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h\" define=\"ARMCM35P_DSP_FP\"/>\n      </device>\n\n      <device Dname=\"ARMCM35P_DSP_FP_TZ\">\n        <processor Dcore=\"Cortex-M35P\" DcoreVersion=\"r0p0\" Dfpu=\"SP_FPU\" Dmpu=\"MPU\" Ddsp=\"DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          DSP Instructions, Single Precision Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h\" define=\"ARMCM35P_DSP_FP_TZ\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M55  ****************************** -->\n    <family Dfamily=\"ARM Cortex M55\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/101273\"       title=\"Cortex-M55 Processor Devices Generic Users Guide\"/>\n      <description>\nThe Arm Cortex-M55 processor is a fully synthesizable, mid-range, microcontroller-class processor that implements the Armv8.1-M mainline architecture and includes support for the M-profile Vector Extension (MVE), also known as Arm Helium technology.\nIt is Arm's most AI-capable Cortex-M processor, delivering enhanced, energy-efficient digital signal processing (DSP) and machine learning (ML) performance.\nThe Cortex-M55 processor achieves high compute performance across scalar and vector operations, while maintaining low energy consumption.\n      </description>\n\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM55.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x10000000\" size=\"0x00200000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IROM2\"                                start=\"0x00000000\" size=\"0x00200000\" startup=\"0\" default=\"0\"/>\n      <memory id=\"IRAM1\"                                start=\"0x30000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <memory id=\"IRAM2\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"0\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMCM55\">\n        <processor Dcore=\"Cortex-M55\" DcoreVersion=\"r0p0\" Dfpu=\"DP_FPU\" Dmpu=\"MPU\" Dmve=\"FP_MVE\" Ddsp=\"DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMCM55/Include/ARMCM55.h\" define=\"ARMCM55\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-M85  ****************************** -->\n    <family Dfamily=\"ARM Cortex M85\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/1019283\"       title=\"Cortex-M85 Processor Devices Generic Users Guide\"/>\n      <description>\nThe Arm Cortex-M85 processor is a fully synthesizable high-performance microcontroller class processor that implements the Armv8.1-M Mainline architecture which includes support for the M-profile Vector Extension (MVE).\nThe processor also supports previous Armv8-M architectural features.\nThe design is focused on compute applications such as Digital Signal Processing (DSP) and machine learning.\nThe Arm Cortex-M85 processor is energy efficient and achieves high compute performance across scalar and vector operations while maintaining low power consumption.\n      </description>\n\n      <!-- debug svd=\"Device/ARM/SVD/ARMCM85.svd\"/ SVD files do not contain any peripheral -->\n      <memory name=\"ROM_NS\" access=\"rxn\"  start=\"0x00000000\" size=\"0x00200000\" startup=\"1\" default=\"1\" alias=\"ROM_S\"/>\n      <memory name=\"RAM_NS\" access=\"rwxn\" start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\" alias=\"RAM_S\"/>\n      <memory name=\"ROM_S\"  access=\"rxn\"  start=\"0x10000000\" size=\"0x00200000\" startup=\"1\" default=\"1\"/>\n      <memory name=\"RAM_S\"  access=\"rwxn\" start=\"0x30000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMCM85\">\n        <processor Dcore=\"Cortex-M85\" DcoreVersion=\"r0p0\" Dpacbti=\"PACBTI\" Dmpu=\"MPU\" Dfpu=\"DP_FPU\" Dmve=\"FP_MVE\" Ddsp=\"DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          Floating Point Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone, PACBTI\n        </description>\n        <compile header=\"Device/ARM/ARMCM85/Include/ARMCM85.h\" define=\"ARMCM85\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  ARMSC000  ****************************** -->\n    <family Dfamily=\"ARM SC000\" Dvendor=\"ARM:82\">\n      <description>\nThe Arm SC000 processor is an entry-level 32-bit Arm Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:\n- simple, easy-to-use programmers model\n- highly efficient ultra-low power operation\n- excellent code density\n- deterministic, high-performance interrupt handling\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMSC000.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00040000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMSC000\">\n        <processor Dcore=\"SC000\" DcoreVersion=\"r0p1\" Dfpu=\"NO_FPU\" Dmpu=\"NO_MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMSC000/Include/ARMSC000.h\" define=\"ARMSC000\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  ARMSC300  ****************************** -->\n    <family Dfamily=\"ARM SC300\" Dvendor=\"ARM:82\">\n      <description>\nThe ARM SC300 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of secure embedded applications. It offers significant benefits to developers, including:\n- simple, easy-to-use programmers model\n- highly efficient ultra-low power operation\n- excellent code density\n- deterministic, high-performance interrupt handling\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMSC300.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00040000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMSC300\">\n        <processor Dcore=\"SC300\" DcoreVersion=\"r0p1\" Dfpu=\"NO_FPU\" Dmpu=\"NO_MPU\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMSC300/Include/ARMSC300.h\" define=\"ARMSC300\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  ARMv8-M Baseline  ********************** -->\n    <family Dfamily=\"ARMv8-M Baseline\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/ddi0553\"       title=\"Armv8-M Architecture Reference Manual\"/>\n      <description>\nArmv8-M Baseline based device with TrustZone\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMv8MBL.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00200000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IROM2\"                                start=\"0x00200000\" size=\"0x00200000\" startup=\"0\" default=\"0\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <memory id=\"IRAM2\"                                start=\"0x20200000\" size=\"0x00020000\" init   =\"0\" default=\"0\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMv8MBL\">\n        <processor Dcore=\"ARMV8MBL\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <compile header=\"Device/ARM/ARMv8MBL/Include/ARMv8MBL.h\" define=\"ARMv8MBL\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  ARMv8-M Mainline  ****************************** -->\n    <family Dfamily=\"ARMv8-M Mainline\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/ddi0553\"       title=\"Armv8-M Architecture Reference Manual\"/>\n      <description>\nArmv8-M Mainline based device with TrustZone\n      </description>\n      <!-- debug svd=\"Device/ARM/SVD/ARMv8MML.svd\"/ SVD files do not contain any peripheral -->\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x00200000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IROM2\"                                start=\"0x00200000\" size=\"0x00200000\" startup=\"0\" default=\"0\"/>\n      <memory id=\"IRAM1\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <memory id=\"IRAM2\"                                start=\"0x20200000\" size=\"0x00020000\" init   =\"0\" default=\"0\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n      <device Dname=\"ARMv8MML\">\n        <processor Dcore=\"ARMV8MML\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Ddsp=\"NO_DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          no DSP Instructions, no Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMv8MML/Include/ARMv8MML.h\" define=\"ARMv8MML\"/>\n      </device>\n\n      <device Dname=\"ARMv8MML_DSP\">\n        <processor Dcore=\"ARMV8MML\" DcoreVersion=\"r0p0\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Ddsp=\"DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          DSP Instructions, no Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h\" define=\"ARMv8MML_DSP\"/>\n      </device>\n\n      <device Dname=\"ARMv8MML_SP\">\n        <processor Dcore=\"ARMV8MML\" DcoreVersion=\"r0p1\" Dfpu=\"SP_FPU\" Dmpu=\"MPU\" Ddsp=\"NO_DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          no DSP Instructions, Single Precision Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h\" define=\"ARMv8MML_SP\"/>\n      </device>\n\n      <device Dname=\"ARMv8MML_DSP_SP\">\n        <processor Dcore=\"ARMV8MML\" DcoreVersion=\"r0p1\" Dfpu=\"SP_FPU\" Dmpu=\"MPU\" Ddsp=\"DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          DSP Instructions, Single Precision Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h\" define=\"ARMv8MML_DSP_SP\"/>\n      </device>\n\n      <device Dname=\"ARMv8MML_DP\">\n        <processor Dcore=\"ARMV8MML\" DcoreVersion=\"r0p1\" Dfpu=\"DP_FPU\" Dmpu=\"MPU\" Ddsp=\"NO_DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          no DSP Instructions, Double Precision Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h\" define=\"ARMv8MML_DP\"/>\n      </device>\n\n      <device Dname=\"ARMv8MML_DSP_DP\">\n        <processor Dcore=\"ARMV8MML\" DcoreVersion=\"r0p1\" Dfpu=\"DP_FPU\" Dmpu=\"MPU\" Ddsp=\"DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          DSP Instructions, Double Precision Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h\" define=\"ARMv8MML_DSP_DP\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  ARMv8.1-M Mainline  ****************************** -->\n    <family Dfamily=\"ARMv8.1-M Mainline\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/ddi0553\"       title=\"Armv8-M Architecture Reference Manual\"/>\n      <description>\nArmv8.1-M Mainline based device with TrustZone and MVE\n      </description>\n      <!-- <debug svd=\"Device/ARM/SVD/ARMv8MML.svd\"/> -->\n      <memory id=\"IROM1\"                                start=\"0x10000000\" size=\"0x00200000\" startup=\"1\" default=\"1\"/>\n      <memory id=\"IROM2\"                                start=\"0x00000000\" size=\"0x00200000\" startup=\"0\" default=\"0\"/>\n      <memory id=\"IRAM1\"                                start=\"0x30000000\" size=\"0x00020000\" init   =\"0\" default=\"1\"/>\n      <memory id=\"IRAM2\"                                start=\"0x20000000\" size=\"0x00020000\" init   =\"0\" default=\"0\"/>\n      <!--algorithm name=\"Device/ARM/Flash/NEW_DEVICE.FLM\" start=\"0x00000000\" size=\"0x00040000\"             default=\"1\"/-->\n\n\n      <device Dname=\"ARMv81MML_DSP_DP_MVE_FP\">\n        <processor Dcore=\"ARMV81MML\" DcoreVersion=\"r0p0\" Dfpu=\"DP_FPU\" Dmpu=\"MPU\" Dmve=\"FP_MVE\" Ddsp=\"DSP\" Dtz=\"TZ\" Dendian=\"Configurable\" Dclock=\"10000000\"/>\n        <description>\n          Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone\n        </description>\n        <compile header=\"Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h\" define=\"ARMv81MML_DSP_DP_MVE_FP\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-A5  ****************************** -->\n    <family Dfamily=\"ARM Cortex A5\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/ddi0433\" title=\"Cortex-A5 Technical Reference Manual\"/>\n      <description>\nThe Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full\nvirtual memory capabilities. The Cortex-A5 processor implements the Armv7-A architecture profile and can execute 32-bit\nArm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family.\n      </description>\n\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x04000000\" startup=\"1\" default=\"1\"/> <!-- 64MB NOR -->\n      <memory id=\"IROM2\"                                start=\"0x0C000000\" size=\"0x04000000\" startup=\"0\" default=\"0\"/> <!-- 64MB NOR -->\n      <memory id=\"IRAM1\"                                start=\"0x14000000\" size=\"0x02000000\" init   =\"0\" default=\"1\"/> <!-- 32MB SRAM -->\n      <memory id=\"IRAM2\"                                start=\"0x80000000\" size=\"0x40000000\" init   =\"0\" default=\"0\"/> <!-- 1GB DRAM -->\n\n      <device Dname=\"ARMCA5\">\n        <processor Dcore=\"Cortex-A5\" DcoreVersion=\"r0p1\" Dfpu=\"DP_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"12000000\"/>\n        <compile header=\"Device/ARM/ARMCA5/Include/ARMCA5.h\" define=\"ARMCA5\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-A7  ****************************** -->\n    <family Dfamily=\"ARM Cortex A7\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/ddi0464\" title=\"Cortex-A7 MPCore Technical Reference Manual\"/>\n      <description>\nThe Cortex-A7 MPCore processor is a high-performance, low-power processor that implements the Armv7-A architecture.\nThe Cortex-A7 MPCore processor has one to four processors in a single multiprocessor device with a L1 cache subsystem,\nan optional integrated GIC, and an optional L2 cache controller.\n      </description>\n\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x04000000\" startup=\"1\" default=\"1\"/> <!-- 64MB NOR -->\n      <memory id=\"IROM2\"                                start=\"0x0C000000\" size=\"0x04000000\" startup=\"0\" default=\"0\"/> <!-- 64MB NOR -->\n      <memory id=\"IRAM1\"                                start=\"0x14000000\" size=\"0x02000000\" init   =\"0\" default=\"1\"/> <!-- 32MB SRAM -->\n      <memory id=\"IRAM2\"                                start=\"0x80000000\" size=\"0x40000000\" init   =\"0\" default=\"0\"/> <!-- 1GB DRAM -->\n\n      <device Dname=\"ARMCA7\">\n        <processor Dcore=\"Cortex-A7\" DcoreVersion=\"r0p5\" Dfpu=\"DP_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"12000000\"/>\n        <compile header=\"Device/ARM/ARMCA7/Include/ARMCA7.h\" define=\"ARMCA7\"/>\n      </device>\n    </family>\n\n    <!-- ******************************  Cortex-A9  ****************************** -->\n    <family Dfamily=\"ARM Cortex A9\" Dvendor=\"ARM:82\">\n      <book name=\"https://developer.arm.com/documentation/100511\" title=\"Cortex-A9 Technical Reference Manual\"/>\n      <description>\nThe Cortex-A9 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities.\nThe Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions,\nand 8-bit Java bytecodes in Jazelle state.\n      </description>\n\n      <memory id=\"IROM1\"                                start=\"0x00000000\" size=\"0x04000000\" startup=\"1\" default=\"1\"/> <!-- 64MB NOR -->\n      <memory id=\"IROM2\"                                start=\"0x0C000000\" size=\"0x04000000\" startup=\"0\" default=\"0\"/> <!-- 64MB NOR -->\n      <memory id=\"IRAM1\"                                start=\"0x14000000\" size=\"0x02000000\" init   =\"0\" default=\"1\"/> <!-- 32MB SRAM -->\n      <memory id=\"IRAM2\"                                start=\"0x80000000\" size=\"0x40000000\" init   =\"0\" default=\"0\"/> <!-- 1GB DRAM -->\n\n      <device Dname=\"ARMCA9\">\n        <processor Dcore=\"Cortex-A9\" DcoreVersion=\"r4p1\" Dfpu=\"DP_FPU\" Dmpu=\"MPU\" Dendian=\"Configurable\" Dclock=\"12000000\"/>\n        <compile header=\"Device/ARM/ARMCA9/Include/ARMCA9.h\" define=\"ARMCA9\"/>\n      </device>\n    </family>\n  </devices>\n\n\n  <apis>\n    <!-- CMSIS Device API -->\n    <api Cclass=\"Device\" Cgroup=\"IRQ Controller\" Capiversion=\"1.0.0\" exclusive=\"1\">\n      <description>Device interrupt controller interface</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Core_A/Include/irq_ctrl.h\"/>\n      </files>\n    </api>\n    <api Cclass=\"Device\" Cgroup=\"OS Tick\" Capiversion=\"1.0.1\" exclusive=\"1\">\n      <description>RTOS Kernel system tick timer interface</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/RTOS2/Include/os_tick.h\"/>\n      </files>\n    </api>\n    <!-- CMSIS-RTOS API -->\n    <api Cclass=\"CMSIS\" Cgroup=\"RTOS\" Capiversion=\"1.0.0\" exclusive=\"1\">\n      <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/RTOS/html/index.html\"/>\n      </files>\n    </api>\n    <api Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Capiversion=\"2.2.0\" exclusive=\"1\">\n      <description>CMSIS-RTOS API for Cortex-M, SC000, and SC300</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/RTOS2/html/index.html\"/>\n        <file category=\"header\" name=\"CMSIS/RTOS2/Include/cmsis_os2.h\"/>\n      </files>\n    </api>\n    <!-- CMSIS Driver API -->\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"USART\" Capiversion=\"2.4.0\" exclusive=\"0\">\n      <description>USART Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__usart__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_USART.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"SPI\" Capiversion=\"2.3.0\" exclusive=\"0\">\n      <description>SPI Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__spi__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_SPI.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"SAI\" Capiversion=\"1.2.0\" exclusive=\"0\">\n      <description>SAI Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__sai__interface__gr.html\"/>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_SAI.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"I2C\" Capiversion=\"2.4.0\" exclusive=\"0\">\n      <description>I2C Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__i2c__interface__gr.html\"/>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_I2C.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"CAN\" Capiversion=\"1.3.0\" exclusive=\"0\">\n      <description>CAN Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__can__interface__gr.html\"/>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_CAN.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"Flash\" Capiversion=\"2.3.0\" exclusive=\"0\">\n      <description>Flash Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__flash__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_Flash.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"MCI\" Capiversion=\"2.4.0\" exclusive=\"0\">\n      <description>MCI Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__mci__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_MCI.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"NAND\" Capiversion=\"2.4.0\" exclusive=\"0\">\n      <description>NAND Flash Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__nand__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_NAND.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"Ethernet\" Capiversion=\"2.2.0\" exclusive=\"0\">\n      <description>Ethernet MAC and PHY Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__eth__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_ETH_MAC.h\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_ETH_PHY.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"Ethernet MAC\" Capiversion=\"2.2.0\" exclusive=\"0\">\n      <description>Ethernet MAC Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__eth__mac__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_ETH_MAC.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"Ethernet PHY\" Capiversion=\"2.2.0\" exclusive=\"0\">\n      <description>Ethernet PHY Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__eth__phy__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_ETH_PHY.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"USB Device\" Capiversion=\"2.3.0\" exclusive=\"0\">\n      <description>USB Device Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__usbd__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_USBD.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"USB Host\" Capiversion=\"2.3.0\" exclusive=\"0\">\n      <description>USB Host Driver API for Cortex-M</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__usbh__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_USBH.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"WiFi\" Capiversion=\"1.1.0\" exclusive=\"0\">\n      <description>WiFi driver</description>\n      <files>\n        <file category=\"doc\" name=\"CMSIS/Documentation/Driver/html/group__wifi__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_WiFi.h\" />\n      </files>\n    </api>\n    <api Cclass=\"CMSIS Driver\" Cgroup=\"VIO\" Capiversion=\"0.1.0\" exclusive=\"1\">\n      <description>Virtual I/O</description>\n      <files>\n        <file category=\"doc\"    name=\"CMSIS/Documentation/Driver/html/group__vio__interface__gr.html\" />\n        <file category=\"header\" name=\"CMSIS/Driver/VIO/Include/cmsis_vio.h\" />\n        <file category=\"other\"  name=\"CMSIS/Driver/VIO/cmsis_vio.scvd\" />\n      </files>\n    </api>\n  </apis>\n\n  <!-- conditions are dependency rules that can apply to a component or an individual file -->\n  <conditions>\n    <!-- compiler -->\n    <condition id=\"ARMCC6\">\n      <accept Tcompiler=\"ARMCC\" Toptions=\"AC6\"/>\n      <accept Tcompiler=\"ARMCC\" Toptions=\"AC6LTO\"/>\n    </condition>\n    <condition id=\"ARMCC5\">\n      <require Tcompiler=\"ARMCC\" Toptions=\"AC5\"/>\n    </condition>\n    <condition id=\"ARMCC\">\n      <require Tcompiler=\"ARMCC\"/>\n    </condition>\n    <condition id=\"GCC\">\n      <require Tcompiler=\"GCC\"/>\n    </condition>\n    <condition id=\"IAR\">\n      <require Tcompiler=\"IAR\"/>\n    </condition>\n    <condition id=\"ARMCC GCC\">\n      <accept Tcompiler=\"ARMCC\"/>\n      <accept Tcompiler=\"GCC\"/>\n    </condition>\n    <condition id=\"ARMCC GCC IAR\">\n      <accept Tcompiler=\"ARMCC\"/>\n      <accept Tcompiler=\"GCC\"/>\n      <accept Tcompiler=\"IAR\"/>\n    </condition>\n\n    <!-- Arm architecture -->\n    <condition id=\"ARMv6-M Device\">\n      <description>Armv6-M architecture based device</description>\n      <accept Dcore=\"Cortex-M0\"/>\n      <accept Dcore=\"Cortex-M1\"/>\n      <accept Dcore=\"Cortex-M0+\"/>\n      <accept Dcore=\"SC000\"/>\n    </condition>\n    <condition id=\"ARMv7-M Device\">\n      <description>Armv7-M architecture based device</description>\n      <accept Dcore=\"Cortex-M3\"/>\n      <accept Dcore=\"Cortex-M4\"/>\n      <accept Dcore=\"Cortex-M7\"/>\n      <accept Dcore=\"SC300\"/>\n    </condition>\n    <condition id=\"ARMv8-MBL Device\">\n      <description>Armv8-M base line architecture based device</description>\n      <accept Dcore=\"ARMV8MBL\"/>\n      <accept Dcore=\"Cortex-M23\"/>\n    </condition>\n    <condition id=\"ARMv8-MML Device\">\n      <description>Armv8-M main line architecture based device</description>\n      <accept Dcore=\"ARMV8MML\"/>\n      <accept Dcore=\"Cortex-M33\"/>\n      <accept Dcore=\"Cortex-M35P\"/>\n      <accept Dcore=\"Star-MC1\"/>\n    </condition>\n    <condition id=\"ARMv81-MML Device\">\n      <description>Armv8.1-M main line architecture based device</description>\n      <accept Dcore=\"ARMV81MML\"/>\n      <accept Dcore=\"Cortex-M55\"/>\n      <accept Dcore=\"Cortex-M85\"/>\n    </condition>\n    <condition id=\"ARMv8x-MML Device\">\n      <description>Armv8-M/Armv8.1-M architecture based device</description>\n      <accept condition=\"ARMv8-MML Device\"/>\n      <accept condition=\"ARMv81-MML Device\"/>\n    </condition>\n    <condition id=\"ARMv8-M Device\">\n      <description>Armv8-M architecture based device</description>\n      <accept condition=\"ARMv8-MBL Device\"/>\n      <accept condition=\"ARMv8-MML Device\"/>\n      <accept condition=\"ARMv81-MML Device\"/>\n    </condition>\n    <condition id=\"ARMv6_7-M Device\">\n      <description>Armv6_7-M architecture based device</description>\n      <accept condition=\"ARMv6-M Device\"/>\n      <accept condition=\"ARMv7-M Device\"/>\n    </condition>\n    <condition id=\"ARMv6_7_8-M Device\">\n      <description>Armv6_7_8-M architecture based device</description>\n      <accept condition=\"ARMv6-M Device\"/>\n      <accept condition=\"ARMv7-M Device\"/>\n      <accept condition=\"ARMv8-M Device\"/>\n    </condition>\n    <condition id=\"ARMv7-A Device\">\n      <description>Armv7-A architecture based device</description>\n      <accept Dcore=\"Cortex-A5\"/>\n      <accept Dcore=\"Cortex-A7\"/>\n      <accept Dcore=\"Cortex-A9\"/>\n    </condition>\n\n    <condition id=\"No TrustZone\">\n      <description>No TrustZone</description>\n      <require Dtz=\"NO_TZ\"/>\n    </condition>\n    <condition id=\"TrustZone\">\n      <description>TrustZone</description>\n      <require Dtz=\"TZ\"/>\n    </condition>\n    <condition id=\"TZ Disabled\">\n      <description>TrustZone (Disabled)</description>\n      <require Dtz=\"TZ\"/>\n      <require Dsecure=\"TZ-disabled\"/>\n    </condition>\n    <condition id=\"TZ Secure\">\n      <description>TrustZone (Secure)</description>\n      <require Dtz=\"TZ\"/>\n      <require Dsecure=\"Secure\"/>\n    </condition>\n    <condition id=\"TZ Non-secure\">\n      <description>TrustZone (Non-secure)</description>\n      <require Dtz=\"TZ\"/>\n      <require Dsecure=\"Non-secure\"/>\n    </condition>\n\n    <condition id=\"ARMv8-M Device without TrustZone\">\n      <description>Armv8-M architecture based device without TrustZone</description>\n      <require condition=\"ARMv8-M Device\"/>\n      <require condition=\"No TrustZone\"/>\n    </condition>\n    <condition id=\"ARMv8-M Device with TZ Disabled\">\n      <description>Armv8-M architecture based device with TrustZone (Disabled)</description>\n      <require condition=\"ARMv8-M Device\"/>\n      <require condition=\"TZ Disabled\"/>\n    </condition>\n    <condition id=\"ARMv8-M Device with TZ Secure\">\n      <description>Armv8-M architecture based device with TrustZone (Secure)</description>\n      <require condition=\"ARMv8-M Device\"/>\n      <require condition=\"TZ Secure\"/>\n    </condition>\n    <condition id=\"ARMv8-M Device with TZ Non-secure\">\n      <description>Armv8-M architecture based device with TrustZone (Non-secure)</description>\n      <require condition=\"ARMv8-M Device\"/>\n      <require condition=\"TZ Non-secure\"/>\n    </condition>\n\n    <!-- Startup -->\n    <condition id=\"Startup ARMCC6 Secure\">\n      <description>Startup files for Arm Compiler 6 targeting TrustZone secure mode</description>\n      <require condition=\"ARMCC6\"/>\n      <require condition=\"TZ Secure\"/>\n    </condition>\n    <condition id=\"Startup ARMCC6 Unsecure\">\n      <description>Startup files for Arm Compiler 6 targeting non-TrustZone or TrustZone non-secure mode</description>\n      <require condition=\"ARMCC6\"/>\n      <deny condition=\"TZ Secure\"/>\n    </condition>\n\n    <!-- CMSIS-Core -->\n    <condition id=\"ARMCM0 CMSIS\">\n      <description>Generic Arm Cortex-M0 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM0\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM0+ CMSIS\">\n      <description>Generic Arm Cortex-M0+ device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM0P*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM1 CMSIS\">\n      <description>Generic Arm Cortex-M1 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM1\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM3 CMSIS\">\n      <description>Generic Arm Cortex-M3 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM3\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM4 CMSIS\">\n      <description>Generic Arm Cortex-M4 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM4*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM7 CMSIS\">\n      <description>Generic Arm Cortex-M7 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM7*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM23 CMSIS\">\n      <description>Generic Arm Cortex-M23 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM23*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM33 CMSIS\">\n      <description>Generic Arm Cortex-M33 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM33*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM35P CMSIS\">\n      <description>Generic Arm Cortex-M35P device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM35P*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM55 CMSIS\">\n      <description>Generic Arm Cortex-M55 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM55*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCM85 CMSIS\">\n      <description>Generic Arm Cortex-M85 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCM85*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMSC000 CMSIS\">\n      <description>Generic Arm SC000 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMSC000\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMSC300 CMSIS\">\n      <description>Generic Arm SC300 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMSC300\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMv8MBL CMSIS\">\n      <description>Generic Armv8-M Baseline device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMv8MBL\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMv8MML CMSIS\">\n      <description>Generic Armv8-M Mainline device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMv8MML*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMv81MML CMSIS\">\n      <description>Generic Armv8.1-M Mainline device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMv81MML*\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCA5 CMSIS\">\n      <description>Generic Arm Cortex-A5 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCA5\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCA7 CMSIS\">\n      <description>Generic Arm Cortex-A7 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCA7\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <condition id=\"ARMCA9 CMSIS\">\n      <description>Generic Arm Cortex-A9 device startup and depends on CMSIS Core</description>\n      <require Dvendor=\"ARM:82\" Dname=\"ARMCA9\"/>\n      <require Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n    </condition>\n\n    <!-- RTOS RTX -->\n    <condition id=\"RTOS RTX\">\n      <description>Components required for RTOS RTX</description>\n      <require condition=\"ARMv6_7-M Device\"/>\n      <require condition=\"ARMCC GCC IAR\"/>\n      <require Cclass=\"Device\" Cgroup=\"Startup\"/>\n      <deny    Cclass=\"CMSIS\"  Cgroup=\"RTOS2\" Csub=\"Keil RTX5\"/>\n    </condition>\n    <condition id=\"RTOS RTX IFX\">\n      <description>Components required for RTOS RTX IFX</description>\n      <require condition=\"ARMv6_7-M Device\"/>\n      <require condition=\"ARMCC GCC IAR\"/>\n      <require Dvendor=\"Infineon:7\" Dname=\"XMC4*\"/>\n      <require Cclass=\"Device\" Cgroup=\"Startup\"/>\n      <deny    Cclass=\"CMSIS\"  Cgroup=\"RTOS2\" Csub=\"Keil RTX5\"/>\n    </condition>\n    <condition id=\"RTOS RTX5\">\n      <description>Components required for RTOS RTX5</description>\n      <require condition=\"ARMv6_7_8-M Device\"/>\n      <require condition=\"ARMCC GCC IAR\"/>\n      <require Cclass=\"CMSIS\"  Cgroup=\"RTOS2\" Csub=\"Keil RTX5\"/>\n    </condition>\n    <condition id=\"RTOS2 RTX5\">\n      <description>Components required for RTOS2 RTX5</description>\n      <accept  condition=\"ARMv6_7-M Device\"/>\n      <accept  condition=\"ARMv8-M Device without TrustZone\"/>\n      <accept  condition=\"ARMv8-M Device with TZ Disabled\"/>\n      <accept  condition=\"ARMv8-M Device with TZ Secure\"/>\n      <require condition=\"ARMCC GCC IAR\"/>\n      <require Cclass=\"CMSIS\"  Cgroup=\"CORE\"/>\n      <require Cclass=\"Device\" Cgroup=\"Startup\"/>\n    </condition>\n    <condition id=\"RTOS2 RTX5 v7-A\">\n      <description>Components required for RTOS2 RTX5 on Armv7-A</description>\n      <require condition=\"ARMv7-A Device\"/>\n      <require condition=\"ARMCC GCC IAR\"/>\n      <require Cclass=\"CMSIS\"  Cgroup=\"CORE\"/>\n      <require Cclass=\"Device\" Cgroup=\"Startup\"/>\n      <require Cclass=\"Device\" Cgroup=\"OS Tick\"/>\n      <require Cclass=\"Device\" Cgroup=\"IRQ Controller\"/>\n    </condition>\n    <condition id=\"RTOS2 RTX5 NS\">\n      <description>Components required for RTOS2 RTX5 in Non-Secure Domain</description>\n      <require condition=\"ARMv8-M Device with TZ Non-secure\"/>\n      <require condition=\"ARMCC GCC IAR\"/>\n      <require Cclass=\"CMSIS\"  Cgroup=\"CORE\"/>\n      <require Cclass=\"Device\" Cgroup=\"Startup\"/>\n    </condition>\n\n    <condition id=\"ARMCC ARMv6-M LE\">\n        <description>Arm Compiler for Armv6-M architecture (little endian)</description>\n        <require condition=\"ARMCC\"/>\n        <require condition=\"ARMv6-M Device\"/>\n        <require Dendian=\"Little-endian\"/>\n    </condition>\n    <condition id=\"ARMCC ARMv6-M BE\">\n        <description>Arm Compiler for Armv6-M architecture (big endian)</description>\n        <require condition=\"ARMCC\"/>\n        <require condition=\"ARMv6-M Device\"/>\n        <require Dendian=\"Big-endian\"/>\n    </condition>\n    <condition id=\"ARMCC ARMv7-M NOFP LE\">\n        <description>Arm Compiler for Armv7-M architecture without FPU (little endian)</description>\n        <require condition=\"ARMCC\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n    </condition>\n    <condition id=\"ARMCC ARMv7-M NOFP BE\">\n        <description>Arm Compiler for Armv7-M architecture without FPU (big endian)</description>\n        <require condition=\"ARMCC\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Big-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n    </condition>\n    <condition id=\"ARMCC ARMv7-M FP LE\">\n        <description>Arm Compiler for Armv7-M architecture with FPU (little endian)</description>\n        <require condition=\"ARMCC\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n    </condition>\n    <condition id=\"ARMCC ARMv7-M FP BE\">\n        <description>Arm Compiler for Armv7-M architecture with FPU (big endian)</description>\n        <require condition=\"ARMCC\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Big-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n    </condition>\n    <condition id=\"ARMCC ARMv8-MBL LE\">\n        <description>Arm Compiler for Armv8-M base line architecture (little endian)</description>\n        <require condition=\"ARMCC\"/>\n        <require condition=\"ARMv8-MBL Device\"/>\n        <require Dendian=\"Little-endian\"/>\n    </condition>\n    <condition id=\"ARMCC ARMv8-MML NOFP LE\">\n        <description>Arm Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian)</description>\n        <require condition=\"ARMCC\"/>\n        <require condition=\"ARMv8x-MML Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n        <require Dmve=\"NO_MVE\"/>\n    </condition>\n     <condition id=\"ARMCC ARMv8-MML FP LE\">\n        <description>Arm Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian)</description>\n        <require condition=\"ARMCC\"/>\n        <require condition=\"ARMv8x-MML Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n        <accept Dmve=\"MVE\"/>\n        <accept Dmve=\"FP_MVE\"/>\n    </condition>\n\n    <condition id=\"GCC ARMv6-M LE\">\n        <description>GNU Compiler for Armv6-M architecture (little endian)</description>\n        <require condition=\"GCC\"/>\n        <require condition=\"ARMv6-M Device\"/>\n        <require Dendian=\"Little-endian\"/>\n    </condition>\n    <condition id=\"GCC ARMv6-M BE\">\n        <description>GNU Compiler for Armv6-M architecture (big endian)</description>\n        <require condition=\"GCC\"/>\n        <require condition=\"ARMv6-M Device\"/>\n        <require Dendian=\"Big-endian\"/>\n    </condition>\n    <condition id=\"GCC ARMv7-M NOFP LE\">\n        <description>GNU Compiler for Armv7-M architecture without FPU (little endian)</description>\n        <require condition=\"GCC\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n    </condition>\n    <condition id=\"GCC ARMv7-M NOFP BE\">\n        <description>GNU Compiler for Armv7-M architecture without FPU (big endian)</description>\n        <require condition=\"GCC\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Big-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n    </condition>\n    <condition id=\"GCC ARMv7-M FP LE\">\n        <description>GNU Compiler for Armv7-M architecture with FPU (little endian)</description>\n        <require condition=\"GCC\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n    </condition>\n    <condition id=\"GCC ARMv7-M FP BE\">\n        <description>GNU Compiler for Armv7-M architecture with FPU (big endian)</description>\n        <require condition=\"GCC\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Big-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n    </condition>\n    <condition id=\"GCC ARMv8-MBL LE\">\n        <description>GNU Compiler for Armv8-M base line architecture (little endian)</description>\n        <require condition=\"GCC\"/>\n        <require condition=\"ARMv8-MBL Device\"/>\n        <require Dendian=\"Little-endian\"/>\n    </condition>\n    <condition id=\"GCC ARMv8-MML NOFP LE\">\n        <description>GNU Compiler for Armv8-M/Armv8.1-M main line architecture without FPU/MVE (little endian)</description>\n        <require condition=\"GCC\"/>\n        <require condition=\"ARMv8x-MML Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n        <require Dmve=\"NO_MVE\"/>\n    </condition>\n     <condition id=\"GCC ARMv8-MML FP LE\">\n        <description>GNU Compiler for Armv8-M/Armv8.1-M main line architecture with FPU/MVE (little endian)</description>\n        <require condition=\"GCC\"/>\n        <require condition=\"ARMv8x-MML Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n        <accept Dmve=\"MVE\"/>\n        <accept Dmve=\"FP_MVE\"/>\n    </condition>\n\n    <condition id=\"IARCC ARMv6-M LE\">\n        <description>IAR Compiler for Armv6-M architecture (little endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv6-M Device\"/>\n        <require Dendian=\"Little-endian\"/>\n    </condition>\n    <condition id=\"IARCC ARMv6-M BE\">\n        <description>IAR Compiler for Armv6-M architecture (big endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv6-M Device\"/>\n        <require Dendian=\"Big-endian\"/>\n    </condition>\n    <condition id=\"IARCC ARMv7-M NOFP LE\">\n        <description>IAR Compiler for Armv7-M architecture without FPU (little endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n    </condition>\n    <condition id=\"IARCC ARMv7-M NOFP BE\">\n        <description>IAR Compiler for Armv7-M architecture without FPU (big endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Big-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n    </condition>\n    <condition id=\"IARCC ARMv7-M FP LE\">\n        <description>IAR Compiler for Armv7-M architecture with FPU (little endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n    </condition>\n    <condition id=\"IARCC ARMv7-M FP BE\">\n        <description>IAR Compiler for Armv7-M architecture with FPU (big endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv7-M Device\"/>\n        <require Dendian=\"Big-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n    </condition>\n    <condition id=\"IARCC ARMv8-MBL LE\">\n        <description>IAR Compiler for Armv8-M base line architecture (little endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv8-MBL Device\"/>\n        <require Dendian=\"Little-endian\"/>\n    </condition>\n    <condition id=\"IARCC ARMv8-MML NOFP LE\">\n        <description>IAR Compiler for Armv8-M main line architecture without FPU (little endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv8-MML Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n    </condition>\n    <condition id=\"IARCC ARMv8-MML FP LE\">\n        <description>IAR Compiler for Armv8-M main line architecture with FPU (little endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv8-MML Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n    </condition>\n    <condition id=\"IARCC ARMv81-MML NOFP LE\">\n        <description>IAR Compiler for Armv8.1-M main line architecture without FPU/MVE (little endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv81-MML Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <require Dfpu=\"NO_FPU\"/>\n        <require Dmve=\"NO_MVE\"/>\n    </condition>\n     <condition id=\"IARCC ARMv81-MML FP LE\">\n        <description>IAR Compiler for Armv8.1-M main line architecture with FPU/MVE (little endian)</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv81-MML Device\"/>\n        <require Dendian=\"Little-endian\"/>\n        <accept Dfpu=\"SP_FPU\"/>\n        <accept Dfpu=\"DP_FPU\"/>\n        <accept Dmve=\"MVE\"/>\n        <accept Dmve=\"FP_MVE\"/>\n    </condition>\n\n    <condition id=\"ARMASM ARMv6-M\">\n        <description>Arm Assembler for Armv6-M architecture</description>\n        <require condition=\"ARMCC5\"/>\n        <require condition=\"ARMv6-M Device\"/>\n    </condition>\n    <condition id=\"GNUASM ARMv6-M\">\n        <description>GNU Assembler for Armv6-M architecture</description>\n        <accept condition=\"ARMCC6\"/>\n        <accept condition=\"GCC\"/>\n        <require condition=\"ARMv6-M Device\"/>\n    </condition>\n    <condition id=\"IARASM ARMv6-M\">\n        <description>IAR Assembler for Armv6-M architecture</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv6-M Device\"/>\n    </condition>\n\n    <condition id=\"ARMASM ARMv7-M\">\n        <description>Arm Assembler for Armv7-M architecture</description>\n        <require condition=\"ARMCC5\"/>\n        <require condition=\"ARMv7-M Device\"/>\n    </condition>\n    <condition id=\"GNUASM ARMv7-M\">\n        <description>GNU Assembler for Armv7-M architecture</description>\n        <accept condition=\"ARMCC6\"/>\n        <accept condition=\"GCC\"/>\n        <require condition=\"ARMv7-M Device\"/>\n    </condition>\n    <condition id=\"IARASM ARMv7-M\">\n        <description>IAR Assembler for Armv7-M architecture</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv7-M Device\"/>\n    </condition>\n\n    <condition id=\"GNUASM ARMv8-MBL\">\n        <description>GNU Assembler for Armv8-M base line architecture</description>\n        <require condition=\"ARMCC GCC\"/>\n        <require condition=\"ARMv8-MBL Device\"/>\n    </condition>\n    <condition id=\"GNUASM ARMv8-MML\">\n        <description>GNU Assembler for Armv8-M/Armv8.1-M main line architecture</description>\n        <require condition=\"ARMCC GCC\"/>\n        <require condition=\"ARMv8x-MML Device\"/>\n    </condition>\n    <condition id=\"IARASM ARMv8-MBL\">\n        <description>IAR Assembler for Armv8-M base line architecture</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv8-MBL Device\"/>\n    </condition>\n    <condition id=\"IARASM ARMv8-MML\">\n        <description>IAR Assembler for Armv8-M main line architecture</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv8x-MML Device\"/>\n    </condition>\n\n    <condition id=\"ARMASM ARMv7-A\">\n        <description>Arm Assembler for Armv7-A architecture</description>\n        <require condition=\"ARMCC5\"/>\n        <require condition=\"ARMv7-A Device\"/>\n    </condition>\n    <condition id=\"GNUASM ARMv7-A\">\n        <description>GNU Assembler for Armv7-A architecture</description>\n        <accept condition=\"ARMCC6\"/>\n        <accept condition=\"GCC\"/>\n        <require condition=\"ARMv7-A Device\"/>\n    </condition>\n    <condition id=\"IARASM ARMv7-A\">\n        <description>IAR Assembler for Armv7-A architecture</description>\n        <require condition=\"IAR\"/>\n        <require condition=\"ARMv7-A Device\"/>\n    </condition>\n\n    <!-- OS Tick -->\n    <condition id=\"OS Tick PTIM\">\n      <description>Components required for OS Tick Private Timer</description>\n      <accept Dcore=\"Cortex-A5\"/>\n      <accept Dcore=\"Cortex-A9\"/>\n      <require Cclass=\"Device\" Cgroup=\"IRQ Controller\"/>\n    </condition>\n\n    <condition id=\"OS Tick GTIM\">\n      <description>Components required for OS Tick Generic Physical Timer</description>\n      <accept Dcore=\"Cortex-A7\"/>\n      <require Cclass=\"Device\" Cgroup=\"IRQ Controller\"/>\n    </condition>\n\n  </conditions>\n\n  <components>\n    <!-- CMSIS-Core component -->\n    <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cversion=\"5.7.0\"  condition=\"ARMv6_7_8-M Device\" >\n      <description>CMSIS-CORE for Cortex-M, SC000, SC300, Star-MC1, ARMv8-M, ARMv8.1-M</description>\n      <files>\n        <!-- CPU independent -->\n        <file category=\"doc\"     name=\"CMSIS/Documentation/Core/html/index.html\"/>\n        <file category=\"include\" name=\"CMSIS/Core/Include/\"/>\n        <file category=\"header\"  name=\"CMSIS/Core/Include/tz_context.h\" condition=\"TrustZone\"/>\n        <!-- Code template -->\n        <file category=\"sourceC\" attr=\"template\" condition=\"TZ Secure\" name=\"CMSIS/Core/Template/ARMv8-M/main_s.c\"     version=\"1.1.1\" select=\"Secure mode 'main' module for ARMv8-M\"/>\n        <file category=\"sourceC\" attr=\"template\" condition=\"TZ Secure\" name=\"CMSIS/Core/Template/ARMv8-M/tz_context.c\" version=\"1.1.1\" select=\"RTOS Context Management (TrustZone for ARMv8-M)\" />\n      </files>\n    </component>\n\n    <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cversion=\"1.2.1\"  condition=\"ARMv7-A Device\" >\n      <description>CMSIS-CORE for Cortex-A</description>\n      <files>\n        <!-- CPU independent -->\n        <file category=\"doc\"     name=\"CMSIS/Documentation/Core_A/html/index.html\"/>\n        <file category=\"include\" name=\"CMSIS/Core_A/Include/\"/>\n      </files>\n    </component>\n\n    <!-- CMSIS-Startup components -->\n    <!-- Cortex-M0 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.0.3\" condition=\"ARMCM0 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm Cortex-M0 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMCM0/Include/ARMCM0.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM0/Source/startup_ARMCM0.c\"     version=\"2.0.3\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac5.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac6.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM0/Source/system_ARMCM0.c\"      version=\"1.0.0\" attr=\"config\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.2\" condition=\"ARMCM0 CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm Cortex-M0 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMCM0/Include/ARMCM0.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S\" version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM0/Source/system_ARMCM0.c\"      version=\"1.0.0\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M0+ -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.0.3\" condition=\"ARMCM0+ CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm Cortex-M0+ device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMCM0plus/Include/ARMCM0plus.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM0plus/Source/startup_ARMCM0plus.c\"     version=\"2.0.3\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld\"           version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c\"      version=\"1.0.0\" attr=\"config\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.3.0\" condition=\"ARMCM0+ CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMCM0plus/Include/ARMCM0plus.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S\" version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld\"           version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c\"      version=\"1.0.0\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M1 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.0.3\" condition=\"ARMCM1 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm Cortex-M1 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMCM1/Include/ARMCM1.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM1/Source/startup_ARMCM1.c\"     version=\"2.0.3\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac5.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac6.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM1/Source/system_ARMCM1.c\"      version=\"1.0.0\" attr=\"config\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.2\" condition=\"ARMCM1 CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm Cortex-M1 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMCM1/Include/ARMCM1.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S\" version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM1/Source/system_ARMCM1.c\"      version=\"1.0.0\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M3 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm Cortex-M3 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMCM3/Include/ARMCM3.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM3/Source/startup_ARMCM3.c\"     version=\"2.0.3\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM3/Source/system_ARMCM3.c\"      version=\"1.0.1\" attr=\"config\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.2\" condition=\"ARMCM3 CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm Cortex-M3 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMCM3/Include/ARMCM3.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S\" version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM3/Source/system_ARMCM3.c\"      version=\"1.0.1\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M4 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.0.3\" condition=\"ARMCM4 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm Cortex-M4 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\" name=\"Device/ARM/ARMCM4/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM4/Source/startup_ARMCM4.c\"     version=\"2.0.3\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n       <file category=\"sourceC\"       name=\"Device/ARM/ARMCM4/Source/system_ARMCM4.c\"      version=\"1.0.1\" attr=\"config\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.2\" condition=\"ARMCM4 CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm Cortex-M4 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\" name=\"Device/ARM/ARMCM4/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S\" version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM4/Source/system_ARMCM4.c\"      version=\"1.0.1\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M7 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.0.3\" condition=\"ARMCM7 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm Cortex-M7 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"  name=\"Device/ARM/ARMCM7/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM7/Source/startup_ARMCM7.c\"     version=\"2.0.3\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM7/Source/system_ARMCM7.c\"      version=\"1.0.1\" attr=\"config\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.2\" condition=\"ARMCM7 CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm Cortex-M7 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"  name=\"Device/ARM/ARMCM7/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S\" version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld\"       version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM7/Source/system_ARMCM7.c\"      version=\"1.0.1\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M23 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.1.0\" condition=\"ARMCM23 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm Cortex-M23 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"  name=\"Device/ARM/ARMCM23/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM23/Source/startup_ARMCM23.c\"             version=\"2.1.0\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld\"                version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM23/Source/system_ARMCM23.c\"     version=\"1.0.1\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h\" version=\"1.0.0\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.0\" condition=\"ARMCM23 CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm Cortex-M23 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMCM23/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.S\"         version=\"2.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S\"         version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld\"                version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s\" version=\"1.1.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM23/Source/system_ARMCM23.c\"      version=\"1.0.1\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h\" version=\"1.0.0\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M33 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm Cortex-M33 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"  name=\"Device/ARM/ARMCM33/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM33/Source/startup_ARMCM33.c\"             version=\"2.1.0\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld\"                version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM33/Source/system_ARMCM33.c\"              version=\"1.0.1\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h\" version=\"1.1.1\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.3.0\" condition=\"ARMCM33 CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm Cortex-M33 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMCM33/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.S\"         version=\"2.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S\"         version=\"2.3.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld\"                version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s\"         version=\"1.1.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM33/Source/system_ARMCM33.c\"              version=\"1.0.1\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h\" version=\"1.1.1\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M35P -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.1.0\" condition=\"ARMCM35P CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm Cortex-M35P device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"  name=\"Device/ARM/ARMCM35P/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM35P/Source/startup_ARMCM35P.c\"             version=\"2.1.0\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld\"                 version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM35P/Source/system_ARMCM35P.c\"              version=\"1.0.1\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h\" version=\"1.0.0\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.0\" condition=\"ARMCM35P CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm Cortex-M35P device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMCM35P/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.S\"         version=\"2.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S\"         version=\"1.3.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld\"                 version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s\"         version=\"2.1.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM35P/Source/system_ARMCM35P.c\"              version=\"1.0.1\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h\" version=\"1.0.0\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M55 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"1.1.0\" condition=\"ARMCM55 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Cortex-M55 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMCM55/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM55/Source/startup_ARMCM55.c\"             version=\"1.1.0\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM55/Source/GCC/gcc_arm.ld\"                version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM55/Source/system_ARMCM55.c\"              version=\"1.1.0\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMCM55/Include/Template/partition_ARMCM55.h\" version=\"1.0.0\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-M85 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"1.0.0\" condition=\"ARMCM85 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Cortex-M85 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMCM85/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM85/Source/startup_ARMCM85.c\"             version=\"1.0.0\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6_s.sct\"         version=\"1.0.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6.sct\"           version=\"1.0.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCM85/Source/GCC/gcc_arm.ld\"                version=\"1.0.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCM85/Source/system_ARMCM85.c\"              version=\"1.0.0\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMCM85/Include/Template/partition_ARMCM85.h\" version=\"1.0.0\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-SC000 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.0.3\" condition=\"ARMSC000 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm SC000 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMSC000/Include/ARMSC000.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMSC000/Source/startup_ARMSC000.c\"     version=\"2.0.3\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld\"         version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMSC000/Source/system_ARMSC000.c\"      version=\"1.0.0\" attr=\"config\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.3\" condition=\"ARMSC000 CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm SC000 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMSC000/Include/ARMSC000.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S\" version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld\"         version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMSC000/Source/system_ARMSC000.c\"      version=\"1.0.0\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-SC300 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.0.3\" condition=\"ARMSC300 CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Arm SC300 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMSC300/Include/ARMSC300.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMSC300/Source/startup_ARMSC300.c\"     version=\"2.0.3\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct\"   version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld\"         version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMSC300/Source/system_ARMSC300.c\"      version=\"1.0.1\" attr=\"config\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.3\" condition=\"ARMSC300 CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Arm SC300 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"header\"  name=\"Device/ARM/ARMSC300/Include/ARMSC300.h\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S\" version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld\"         version=\"2.1.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMSC300/Source/system_ARMSC300.c\"      version=\"1.0.1\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- ARMv8MBL -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.1.0\" condition=\"ARMv8MBL CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Armv8-M Baseline device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"  name=\"Device/ARM/ARMv8MBL/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMv8MBL/Source/startup_ARMv8MBL.c\"             version=\"2.1.0\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld\"                 version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c\"             version=\"1.0.1\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h\" version=\"1.0.0\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.2.0\" condition=\"ARMv8MBL CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Armv8-M Baseline device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMv8MBL/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.S\"         version=\"2.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S\"         version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld\"                 version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c\"      version=\"1.0.1\" attr=\"config\" condition=\"ARMCC GCC\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h\" version=\"1.0.0\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- ARMv8MML -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.1.0\" condition=\"ARMv8MML CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Armv8-M Mainline device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMv8MML/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMv8MML/Source/startup_ARMv8MML.c\"             version=\"2.1.0\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld\"                 version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMv8MML/Source/system_ARMv8MML.c\"              version=\"1.0.1\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h\" version=\"1.1.1\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.3.0\" condition=\"ARMv8MML CMSIS\">\n      <description>DEPRECATED: System and Startup for Generic Armv8-M Mainline device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMv8MML/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.S\"         version=\"2.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S\"         version=\"2.3.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld\"                 version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMv8MML/Source/system_ARMv8MML.c\"              version=\"1.0.1\" attr=\"config\" condition=\"ARMCC GCC\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h\" version=\"1.1.1\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n\n    <!-- ARMv81MML -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cversion=\"2.2.0\" condition=\"ARMv81MML CMSIS\" isDefaultVariant=\"true\">\n      <description>System and Startup for Generic Armv8.1-M Mainline device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMv81MML/Include/\"/>\n        <!-- startup / system file -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMv81MML/Source/startup_ARMv81MML.c\"             version=\"2.1.0\" attr=\"config\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6_s.sct\"         version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Secure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6.sct\"           version=\"1.1.0\" attr=\"config\" condition=\"Startup ARMCC6 Unsecure\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMv81MML/Source/GCC/gcc_arm.ld\"                  version=\"2.2.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMv81MML/Source/system_ARMv81MML.c\"              version=\"1.2.1\" attr=\"config\"/>\n        <!-- SAU configuration -->\n        <file category=\"header\"       name=\"Device/ARM/ARMv81MML/Include/Template/partition_ARMv81MML.h\" version=\"1.0.1\" attr=\"config\" condition=\"TZ Secure\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-A5 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.0.1\" condition=\"ARMCA5 CMSIS\">\n      <description>System and Startup for Generic Arm Cortex-A5 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMCA5/Include/\"/>\n        <!-- startup / system / mmu files -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c\" version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct\"       version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct\"       version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c\" version=\"1.0.1\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld\"        version=\"1.0.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf\"       version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA5/Source/system_ARMCA5.c\"      version=\"1.0.1\" attr=\"config\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA5/Source/mmu_ARMCA5.c\"         version=\"1.2.0\" attr=\"config\"/>\n        <file category=\"header\"       name=\"Device/ARM/ARMCA5/Config/system_ARMCA5.h\"      version=\"1.0.0\" attr=\"config\"/>\n        <file category=\"header\"       name=\"Device/ARM/ARMCA5/Config/mem_ARMCA5.h\"         version=\"1.1.0\" attr=\"config\"/>\n\n      </files>\n    </component>\n\n    <!-- Cortex-A7 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.0.1\" condition=\"ARMCA7 CMSIS\">\n      <description>System and Startup for Generic Arm Cortex-A7 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"      name=\"Device/ARM/ARMCA7/Include/\"/>\n        <!-- startup / system / mmu files -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c\" version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct\"       version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct\"       version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c\" version=\"1.0.1\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld\"        version=\"1.0.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf\"       version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA7/Source/system_ARMCA7.c\"      version=\"1.0.1\" attr=\"config\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA7/Source/mmu_ARMCA7.c\"         version=\"1.2.0\" attr=\"config\"/>\n        <file category=\"header\"       name=\"Device/ARM/ARMCA7/Config/system_ARMCA7.h\"      version=\"1.0.0\" attr=\"config\"/>\n        <file category=\"header\"       name=\"Device/ARM/ARMCA7/Config/mem_ARMCA7.h\"         version=\"1.1.0\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- Cortex-A9 -->\n    <component Cclass=\"Device\" Cgroup=\"Startup\"                      Cversion=\"1.0.2\" condition=\"ARMCA9 CMSIS\">\n      <description>System and Startup for Generic Arm Cortex-A9 device</description>\n      <files>\n        <!-- include folder / device header file -->\n        <file category=\"include\"  name=\"Device/ARM/ARMCA9/Include/\"/>\n        <!-- startup / system / mmu files -->\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c\" version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct\"       version=\"1.0.0\" attr=\"config\" condition=\"ARMCC5\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c\" version=\"1.0.1\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct\"       version=\"1.0.0\" attr=\"config\" condition=\"ARMCC6\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c\" version=\"1.0.1\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld\"        version=\"1.0.0\" attr=\"config\" condition=\"GCC\"/>\n        <file category=\"sourceAsm\"    name=\"Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s\" version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"linkerScript\" name=\"Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf\"       version=\"1.0.0\" attr=\"config\" condition=\"IAR\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA9/Source/system_ARMCA9.c\"      version=\"1.0.1\" attr=\"config\"/>\n        <file category=\"sourceC\"      name=\"Device/ARM/ARMCA9/Source/mmu_ARMCA9.c\"         version=\"1.2.0\" attr=\"config\"/>\n        <file category=\"header\"       name=\"Device/ARM/ARMCA9/Config/system_ARMCA9.h\"      version=\"1.0.0\" attr=\"config\"/>\n        <file category=\"header\"       name=\"Device/ARM/ARMCA9/Config/mem_ARMCA9.h\"         version=\"1.1.0\" attr=\"config\"/>\n      </files>\n    </component>\n\n    <!-- IRQ Controller -->\n    <component Cclass=\"Device\" Cgroup=\"IRQ Controller\" Csub=\"GIC\" Capiversion=\"1.0.0\" Cversion=\"1.2.0\" condition=\"ARMv7-A Device\">\n      <description>IRQ Controller implementation using GIC</description>\n      <files>\n        <file category=\"sourceC\" name=\"CMSIS/Core_A/Source/irq_ctrl_gic.c\"/>\n      </files>\n    </component>\n\n    <!-- OS Tick -->\n    <component Cclass=\"Device\" Cgroup=\"OS Tick\" Csub=\"Private Timer\" Capiversion=\"1.0.1\" Cversion=\"1.0.2\" condition=\"OS Tick PTIM\">\n      <description>OS Tick implementation using Private Timer</description>\n      <files>\n        <file category=\"sourceC\" name=\"CMSIS/RTOS2/Source/os_tick_ptim.c\"/>\n      </files>\n    </component>\n\n    <component Cclass=\"Device\" Cgroup=\"OS Tick\" Csub=\"Generic Physical Timer\" Capiversion=\"1.0.1\" Cversion=\"1.0.1\" condition=\"OS Tick GTIM\">\n      <description>OS Tick implementation using Generic Physical Timer</description>\n      <files>\n        <file category=\"sourceC\" name=\"CMSIS/RTOS2/Source/os_tick_gtim.c\"/>\n      </files>\n    </component>\n\n    <!-- CMSIS-RTOS Keil RTX component -->\n    <component Cclass=\"CMSIS\" Cgroup=\"RTOS\" Csub=\"Keil RTX\" Cversion=\"4.82.0\" Capiversion=\"1.0.0\" isDefaultVariant=\"1\" condition=\"RTOS RTX\">\n      <description>CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300</description>\n      <RTE_Components_h>\n        <!-- the following content goes into file 'RTE_Components.h' -->\n        #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */\n        #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */\n      </RTE_Components_h>\n      <files>\n        <!-- CPU independent -->\n        <file category=\"doc\" name=\"CMSIS/Documentation/RTOS/html/rtxImplementation.html\"/>\n        <file category=\"header\" name=\"CMSIS/RTOS/RTX/INC/cmsis_os.h\"/>\n        <file category=\"source\" attr=\"config\"   name=\"CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c\" version=\"4.70.1\"/>\n\n        <!-- RTX templates -->\n        <file category=\"header\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h\" select=\"CMSIS-RTOS 'main' function\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/main.c\"      select=\"CMSIS-RTOS 'main' function\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c\" select=\"CMSIS-RTOS Mail Queue\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c\"   select=\"CMSIS-RTOS Memory Pool\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c\"  select=\"CMSIS-RTOS Message Queue\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c\"     select=\"CMSIS-RTOS Mutex\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c\" select=\"CMSIS-RTOS Semaphore\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c\"    select=\"CMSIS-RTOS Thread\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c\"     select=\"CMSIS-RTOS Timer\"/>\n        <!-- tool-chain specific template file -->\n        <file category=\"source\" attr=\"template\" condition=\"ARMCC\" name=\"CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s\" select=\"CMSIS-RTOS User SVC\"/>\n        <file category=\"source\" attr=\"template\" condition=\"GCC\"   name=\"CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S\" select=\"CMSIS-RTOS User SVC\"/>\n        <file category=\"source\" attr=\"template\" condition=\"IAR\"   name=\"CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s\" select=\"CMSIS-RTOS User SVC\"/>\n\n        <!-- CPU and Compiler dependent -->\n        <!-- ARMCC -->\n        <file category=\"library\" condition=\"ARMCC ARMv6-M LE\"      name=\"CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib\"    src=\"CMSIS/RTOS/RTX/SRC/ARM\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv6-M BE\"      name=\"CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib\"  src=\"CMSIS/RTOS/RTX/SRC/ARM\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv7-M NOFP LE\" name=\"CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib\"    src=\"CMSIS/RTOS/RTX/SRC/ARM\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv7-M NOFP BE\" name=\"CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib\"  src=\"CMSIS/RTOS/RTX/SRC/ARM\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv7-M FP LE\"   name=\"CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib\"    src=\"CMSIS/RTOS/RTX/SRC/ARM\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv7-M FP BE\"   name=\"CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib\"  src=\"CMSIS/RTOS/RTX/SRC/ARM\"/>\n        <!-- GCC -->\n        <file category=\"library\" condition=\"GCC ARMv6-M LE\"        name=\"CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a\"   src=\"CMSIS/RTOS/RTX/SRC/GCC\"/>\n        <file category=\"library\" condition=\"GCC ARMv6-M BE\"        name=\"CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a\" src=\"CMSIS/RTOS/RTX/SRC/GCC\"/>\n        <file category=\"library\" condition=\"GCC ARMv7-M NOFP LE\"   name=\"CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a\"   src=\"CMSIS/RTOS/RTX/SRC/GCC\"/>\n        <file category=\"library\" condition=\"GCC ARMv7-M NOFP BE\"   name=\"CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a\" src=\"CMSIS/RTOS/RTX/SRC/GCC\"/>\n        <file category=\"library\" condition=\"GCC ARMv7-M FP LE\"     name=\"CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a\"   src=\"CMSIS/RTOS/RTX/SRC/GCC\"/>\n        <file category=\"library\" condition=\"GCC ARMv7-M FP BE\"     name=\"CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a\" src=\"CMSIS/RTOS/RTX/SRC/GCC\"/>\n        <!-- IAR -->\n        <file category=\"library\" condition=\"IARCC ARMv6-M LE\"      name=\"CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a\"      src=\"CMSIS/RTOS/RTX/SRC/IAR\"/>\n        <file category=\"library\" condition=\"IARCC ARMv6-M BE\"      name=\"CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a\"    src=\"CMSIS/RTOS/RTX/SRC/IAR\"/>\n        <file category=\"library\" condition=\"IARCC ARMv7-M NOFP LE\" name=\"CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a\"      src=\"CMSIS/RTOS/RTX/SRC/IAR\"/>\n        <file category=\"library\" condition=\"IARCC ARMv7-M NOFP BE\" name=\"CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a\"    src=\"CMSIS/RTOS/RTX/SRC/IAR\"/>\n        <file category=\"library\" condition=\"IARCC ARMv7-M FP LE\"   name=\"CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a\"      src=\"CMSIS/RTOS/RTX/SRC/IAR\"/>\n        <file category=\"library\" condition=\"IARCC ARMv7-M FP BE\"   name=\"CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a\"    src=\"CMSIS/RTOS/RTX/SRC/IAR\"/>\n      </files>\n    </component>\n    <!-- CMSIS-RTOS Keil RTX component (IFX variant) -->\n    <component Cclass=\"CMSIS\" Cgroup=\"RTOS\" Csub=\"Keil RTX\" Cvariant=\"IFX\" Cversion=\"4.82.0\" Capiversion=\"1.0.0\" condition=\"RTOS RTX IFX\">\n      <description>CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata</description>\n      <RTE_Components_h>\n        <!-- the following content goes into file 'RTE_Components.h' -->\n        #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */\n        #define RTE_CMSIS_RTOS_RTX              /* CMSIS-RTOS Keil RTX */\n      </RTE_Components_h>\n      <files>\n        <!-- CPU independent -->\n        <file category=\"doc\" name=\"CMSIS/Documentation/RTOS/html/rtxImplementation.html\"/>\n        <file category=\"header\" name=\"CMSIS/RTOS/RTX/INC/cmsis_os.h\"/>\n        <file category=\"source\" attr=\"config\"   name=\"CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c\" version=\"4.70.1\"/>\n\n        <!-- RTX templates -->\n        <file category=\"header\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h\" select=\"CMSIS-RTOS 'main' function\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/main.c\"      select=\"CMSIS-RTOS 'main' function\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c\" select=\"CMSIS-RTOS Mail Queue\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c\"   select=\"CMSIS-RTOS Memory Pool\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c\"  select=\"CMSIS-RTOS Message Queue\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c\"     select=\"CMSIS-RTOS Mutex\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c\" select=\"CMSIS-RTOS Semaphore\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c\"    select=\"CMSIS-RTOS Thread\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c\"     select=\"CMSIS-RTOS Timer\"/>\n        <!-- tool-chain specific template file -->\n        <file category=\"source\" attr=\"template\" condition=\"ARMCC\" name=\"CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s\" select=\"CMSIS-RTOS User SVC\"/>\n        <file category=\"source\" attr=\"template\" condition=\"GCC\"   name=\"CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S\" select=\"CMSIS-RTOS User SVC\"/>\n        <file category=\"source\" attr=\"template\" condition=\"IAR\"   name=\"CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s\" select=\"CMSIS-RTOS User SVC\"/>\n\n        <!-- CPU and Compiler dependent -->\n        <!-- ARMCC -->\n        <file category=\"library\" condition=\"ARMCC ARMv7-M NOFP LE\" name=\"CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib\"  src=\"CMSIS/RTOS/RTX/SRC/ARM\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv7-M FP LE\"   name=\"CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib\"  src=\"CMSIS/RTOS/RTX/SRC/ARM\"/>\n        <!-- GCC -->\n        <file category=\"library\" condition=\"GCC ARMv7-M NOFP LE\"   name=\"CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a\" src=\"CMSIS/RTOS/RTX/SRC/GCC\"/>\n        <file category=\"library\" condition=\"GCC ARMv7-M FP LE\"     name=\"CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a\" src=\"CMSIS/RTOS/RTX/SRC/GCC\"/>\n        <!-- IAR -->\n      </files>\n    </component>\n\n    <!-- CMSIS-RTOS Keil RTX5 component -->\n    <component Cclass=\"CMSIS\" Cgroup=\"RTOS\" Csub=\"Keil RTX5\" Cversion=\"5.7.0\" Capiversion=\"1.0.0\" condition=\"RTOS RTX5\">\n      <description>CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300</description>\n      <RTE_Components_h>\n        <!-- the following content goes into file 'RTE_Components.h' -->\n        #define RTE_CMSIS_RTOS                  /* CMSIS-RTOS */\n        #define RTE_CMSIS_RTOS_RTX5             /* CMSIS-RTOS Keil RTX5 */\n      </RTE_Components_h>\n      <files>\n        <!-- RTX header file -->\n        <file category=\"header\" name=\"CMSIS/RTOS2/RTX/Include1/cmsis_os.h\"/>\n        <!-- RTX compatibility module for API V1 -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Library/cmsis_os1.c\"/>\n      </files>\n    </component>\n\n    <!-- CMSIS-RTOS2 Keil RTX5 component -->\n    <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Library\" Cversion=\"5.7.0\" Capiversion=\"2.2.0\" condition=\"RTOS2 RTX5\">\n      <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Library)</description>\n      <RTE_Components_h>\n        <!-- the following content goes into file 'RTE_Components.h' -->\n        #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */\n        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */\n      </RTE_Components_h>\n      <files>\n        <!-- RTX documentation -->\n        <file category=\"doc\"    name=\"CMSIS/Documentation/RTOS2/html/rtx5_impl.html\"/>\n\n        <!-- RTX header files -->\n        <file category=\"header\" name=\"CMSIS/RTOS2/RTX/Include/rtx_os.h\"/>\n\n        <!-- RTX configuration -->\n        <file category=\"header\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.h\"  version=\"5.6.0\"/>\n        <file category=\"source\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.c\"  version=\"5.2.0\"/>\n\n        <!-- RTX templates -->\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/main.c\"      version=\"2.1.0\" select=\"CMSIS-RTOS2 'main' function\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Events.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Events\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MemPool.c\"   version=\"2.0.0\" select=\"CMSIS-RTOS2 Memory Pool\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MsgQueue.c\"  version=\"2.0.0\" select=\"CMSIS-RTOS2 Message Queue\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Mutex.c\"     version=\"2.0.0\" select=\"CMSIS-RTOS2 Mutex\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Semaphore.c\" version=\"2.0.0\" select=\"CMSIS-RTOS2 Semaphore\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Thread.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Thread\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Timer.c\"     version=\"2.0.1\" select=\"CMSIS-RTOS2 Timer\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/svc_user.c\"  version=\"1.0.0\" select=\"CMSIS-RTOS2 SVC User Table\"/>\n        <file category=\"other\"  name=\"CMSIS/RTOS2/RTX/RTX5.scvd\"/>\n\n        <!-- RTX library configuration -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_lib.c\"/>\n\n        <!-- RTX libraries (CPU and Compiler dependent) -->\n        <!-- ARMCC -->\n        <file category=\"library\" condition=\"ARMCC ARMv6-M LE\"         name=\"CMSIS/RTOS2/RTX/Library/ARM/RTX_CM0.lib\"    src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv7-M NOFP LE\"    name=\"CMSIS/RTOS2/RTX/Library/ARM/RTX_CM3.lib\"    src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv7-M FP LE\"      name=\"CMSIS/RTOS2/RTX/Library/ARM/RTX_CM4F.lib\"   src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv8-MBL LE\"       name=\"CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MB.lib\"   src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv8-MML NOFP LE\"  name=\"CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MM.lib\"   src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv8-MML FP LE\"    name=\"CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMF.lib\"  src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <!-- GCC -->\n        <file category=\"library\" condition=\"GCC ARMv6-M LE\"           name=\"CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM0.a\"   src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"GCC ARMv7-M NOFP LE\"      name=\"CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM3.a\"   src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"GCC ARMv7-M FP LE\"        name=\"CMSIS/RTOS2/RTX/Library/GCC/libRTX_CM4F.a\"  src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"GCC ARMv8-MBL LE\"         name=\"CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MB.a\"  src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"GCC ARMv8-MML NOFP LE\"    name=\"CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MM.a\"  src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"GCC ARMv8-MML FP LE\"      name=\"CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMF.a\" src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <!-- IAR -->\n        <file category=\"library\" condition=\"IARCC ARMv6-M LE\"         name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_CM0.a\"      src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv7-M NOFP LE\"    name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_CM3.a\"      src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv7-M FP LE\"      name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_CM4F.a\"     src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv8-MBL LE\"       name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MB.a\"     src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv8-MML NOFP LE\"  name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MM.a\"     src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv8-MML FP LE\"    name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMF.a\"    src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv81-MML NOFP LE\" name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V81MM.a\"    src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv81-MML FP LE\"   name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V81MMF.a\"   src=\"CMSIS/RTOS2/RTX/Source\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Library\" Cversion=\"5.7.0\" Capiversion=\"2.2.0\" condition=\"RTOS2 RTX5 NS\">\n      <description>CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Library)</description>\n      <RTE_Components_h>\n        <!-- the following content goes into file 'RTE_Components.h' -->\n        #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */\n        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */\n        #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */\n      </RTE_Components_h>\n      <files>\n        <!-- RTX documentation -->\n        <file category=\"doc\"    name=\"CMSIS/Documentation/RTOS2/html/rtx5_impl.html\"/>\n\n        <!-- RTX header files -->\n        <file category=\"header\" name=\"CMSIS/RTOS2/RTX/Include/rtx_os.h\"/>\n\n        <!-- RTX configuration -->\n        <file category=\"header\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.h\"  version=\"5.6.0\"/>\n        <file category=\"source\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.c\"  version=\"5.2.0\"/>\n\n        <!-- RTX templates -->\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/main.c\"      version=\"2.1.0\" select=\"CMSIS-RTOS2 'main' function\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Events.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Events\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MemPool.c\"   version=\"2.0.0\" select=\"CMSIS-RTOS2 Memory Pool\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MsgQueue.c\"  version=\"2.0.0\" select=\"CMSIS-RTOS2 Message Queue\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Mutex.c\"     version=\"2.0.0\" select=\"CMSIS-RTOS2 Mutex\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Semaphore.c\" version=\"2.0.0\" select=\"CMSIS-RTOS2 Semaphore\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Thread.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Thread\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Timer.c\"     version=\"2.0.1\" select=\"CMSIS-RTOS2 Timer\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/svc_user.c\"  version=\"1.0.0\" select=\"CMSIS-RTOS2 SVC User Table\"/>\n        <file category=\"other\"  name=\"CMSIS/RTOS2/RTX/RTX5.scvd\"/>\n\n        <!-- RTX library configuration -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_lib.c\"/>\n\n        <!-- RTX libraries (CPU and Compiler dependent) -->\n        <!-- ARMCC -->\n        <file category=\"library\" condition=\"ARMCC ARMv8-MBL LE\"       name=\"CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MBN.lib\"   src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv8-MML NOFP LE\"  name=\"CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib\"   src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"ARMCC ARMv8-MML FP LE\"    name=\"CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMFN.lib\"  src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <!-- GCC -->\n        <file category=\"library\" condition=\"GCC ARMv8-MBL LE\"         name=\"CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MBN.a\"  src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"GCC ARMv8-MML NOFP LE\"    name=\"CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a\"  src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"GCC ARMv8-MML FP LE\"      name=\"CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMFN.a\" src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <!-- IAR -->\n        <file category=\"library\" condition=\"IARCC ARMv8-MBL LE\"       name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MBN.a\"     src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv8-MML NOFP LE\"  name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMN.a\"     src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv8-MML FP LE\"    name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V8MMFN.a\"    src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv81-MML NOFP LE\" name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V81MMN.a\"    src=\"CMSIS/RTOS2/RTX/Source\"/>\n        <file category=\"library\" condition=\"IARCC ARMv81-MML FP LE\"   name=\"CMSIS/RTOS2/RTX/Library/IAR/RTX_V81MMFN.a\"   src=\"CMSIS/RTOS2/RTX/Source\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cversion=\"5.7.0\" Capiversion=\"2.2.0\" condition=\"RTOS2 RTX5\">\n      <description>CMSIS-RTOS2 RTX5 for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M (Source)</description>\n      <RTE_Components_h>\n        <!-- the following content goes into file 'RTE_Components.h' -->\n        #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */\n        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */\n        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */\n      </RTE_Components_h>\n      <files>\n        <!-- RTX documentation -->\n        <file category=\"doc\"    name=\"CMSIS/Documentation/RTOS2/html/rtx5_impl.html\"/>\n\n        <!-- RTX header files -->\n        <file category=\"header\" name=\"CMSIS/RTOS2/RTX/Include/rtx_os.h\"/>\n\n        <!-- RTX configuration -->\n        <file category=\"header\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.h\"  version=\"5.6.0\"/>\n        <file category=\"source\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.c\"  version=\"5.2.0\"/>\n\n        <!-- RTX templates -->\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/main.c\"      version=\"2.1.0\" select=\"CMSIS-RTOS2 'main' function\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Events.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Events\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MemPool.c\"   version=\"2.0.0\" select=\"CMSIS-RTOS2 Memory Pool\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MsgQueue.c\"  version=\"2.0.0\" select=\"CMSIS-RTOS2 Message Queue\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Mutex.c\"     version=\"2.0.0\" select=\"CMSIS-RTOS2 Mutex\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Semaphore.c\" version=\"2.0.0\" select=\"CMSIS-RTOS2 Semaphore\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Thread.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Thread\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Timer.c\"     version=\"2.0.1\" select=\"CMSIS-RTOS2 Timer\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/svc_user.c\"  version=\"1.0.0\" select=\"CMSIS-RTOS2 SVC User Table\"/>\n        <file category=\"other\"  name=\"CMSIS/RTOS2/RTX/RTX5.scvd\"/>\n\n        <!-- RTX sources (core) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_kernel.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_thread.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_delay.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_timer.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evflags.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mutex.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_semaphore.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_memory.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mempool.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_system.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evr.c\"/>\n        <!-- RTX sources (library configuration) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_lib.c\"/>\n        <!-- RTX sources (handlers ARMASM) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s\"   condition=\"ARMASM ARMv6-M\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s\"   condition=\"ARMASM ARMv7-M\"/>\n        <!-- RTX sources (handlers GAS) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S\"   condition=\"GNUASM ARMv6-M\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S\"   condition=\"GNUASM ARMv7-M\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S\" condition=\"GNUASM ARMv8-MBL\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S\" condition=\"GNUASM ARMv8-MML\"/>\n        <!-- RTX sources (handlers IAR) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s\"   condition=\"IARASM ARMv6-M\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s\"   condition=\"IARASM ARMv7-M\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s\" condition=\"IARASM ARMv8-MBL\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s\" condition=\"IARASM ARMv8-MML\"/>\n        <!-- OS Tick (SysTick) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/Source/os_systick.c\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cversion=\"5.7.0\" Capiversion=\"2.2.0\" condition=\"RTOS2 RTX5 v7-A\">\n      <description>CMSIS-RTOS2 RTX5 for Armv7-A (Source)</description>\n      <RTE_Components_h>\n        <!-- the following content goes into file 'RTE_Components.h' -->\n        #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */\n        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */\n        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */\n      </RTE_Components_h>\n      <files>\n        <!-- RTX documentation -->\n        <file category=\"doc\"    name=\"CMSIS/Documentation/RTOS2/html/rtx5_impl.html\"/>\n\n        <!-- RTX header files -->\n        <file category=\"header\" name=\"CMSIS/RTOS2/RTX/Include/rtx_os.h\"/>\n\n        <!-- RTX configuration -->\n        <file category=\"header\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.h\"  version=\"5.6.0\"/>\n        <file category=\"source\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.c\"  version=\"5.2.0\"/>\n\n        <file category=\"source\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/handlers.c\"    version=\"5.1.0\"/>\n\n        <!-- RTX templates -->\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/main.c\"      version=\"2.1.0\" select=\"CMSIS-RTOS2 'main' function\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Events.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Events\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MemPool.c\"   version=\"2.0.0\" select=\"CMSIS-RTOS2 Memory Pool\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MsgQueue.c\"  version=\"2.0.0\" select=\"CMSIS-RTOS2 Message Queue\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Mutex.c\"     version=\"2.0.0\" select=\"CMSIS-RTOS2 Mutex\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Semaphore.c\" version=\"2.0.0\" select=\"CMSIS-RTOS2 Semaphore\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Thread.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Thread\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Timer.c\"     version=\"2.0.1\" select=\"CMSIS-RTOS2 Timer\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/svc_user.c\"  version=\"1.0.0\" select=\"CMSIS-RTOS2 SVC User Table\"/>\n        <file category=\"other\"  name=\"CMSIS/RTOS2/RTX/RTX5.scvd\"/>\n\n        <!-- RTX sources (core) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_kernel.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_thread.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_delay.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_timer.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evflags.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mutex.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_semaphore.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_memory.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mempool.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_system.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evr.c\"/>\n        <!-- RTX sources (library configuration) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_lib.c\"/>\n        <!-- RTX sources (handlers ARMASM) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s\" condition=\"ARMASM ARMv7-A\"/>\n        <!-- RTX sources (handlers GAS) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S\" condition=\"GNUASM ARMv7-A\"/>\n        <!-- RTX sources (handlers IAR) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s\" condition=\"IARASM ARMv7-A\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cversion=\"5.7.0\" Capiversion=\"2.2.0\" condition=\"RTOS2 RTX5 NS\">\n      <description>CMSIS-RTOS2 RTX5 for Armv8-M/Armv8.1-M Non-Secure Domain (Source)</description>\n      <RTE_Components_h>\n        <!-- the following content goes into file 'RTE_Components.h' -->\n        #define RTE_CMSIS_RTOS2                 /* CMSIS-RTOS2 */\n        #define RTE_CMSIS_RTOS2_RTX5            /* CMSIS-RTOS2 Keil RTX5 */\n        #define RTE_CMSIS_RTOS2_RTX5_SOURCE     /* CMSIS-RTOS2 Keil RTX5 Source */\n        #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS  /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */\n      </RTE_Components_h>\n      <files>\n        <!-- RTX documentation -->\n        <file category=\"doc\"    name=\"CMSIS/Documentation/RTOS2/html/rtx5_impl.html\"/>\n\n        <!-- RTX header files -->\n        <file category=\"header\" name=\"CMSIS/RTOS2/RTX/Include/rtx_os.h\"/>\n\n        <!-- RTX configuration -->\n        <file category=\"header\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.h\"  version=\"5.6.0\"/>\n        <file category=\"source\" attr=\"config\"   name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.c\"  version=\"5.2.0\"/>\n\n        <!-- RTX templates -->\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/main.c\"      version=\"2.1.0\" select=\"CMSIS-RTOS2 'main' function\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Events.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Events\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MemPool.c\"   version=\"2.0.0\" select=\"CMSIS-RTOS2 Memory Pool\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/MsgQueue.c\"  version=\"2.0.0\" select=\"CMSIS-RTOS2 Message Queue\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Mutex.c\"     version=\"2.0.0\" select=\"CMSIS-RTOS2 Mutex\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Semaphore.c\" version=\"2.0.0\" select=\"CMSIS-RTOS2 Semaphore\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Thread.c\"    version=\"2.0.0\" select=\"CMSIS-RTOS2 Thread\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/Timer.c\"     version=\"2.0.1\" select=\"CMSIS-RTOS2 Timer\"/>\n        <file category=\"source\" attr=\"template\" name=\"CMSIS/RTOS2/RTX/Template/svc_user.c\"  version=\"1.0.0\" select=\"CMSIS-RTOS2 SVC User Table\"/>\n        <file category=\"other\"  name=\"CMSIS/RTOS2/RTX/RTX5.scvd\"/>\n\n        <!-- RTX sources (core) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_kernel.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_thread.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_delay.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_timer.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evflags.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mutex.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_semaphore.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_memory.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mempool.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_system.c\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evr.c\"/>\n        <!-- RTX sources (library configuration) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_lib.c\"/>\n        <!-- RTX sources (GAS handlers) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S\" condition=\"GNUASM ARMv8-MBL\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S\" condition=\"GNUASM ARMv8-MML\"/>\n        <!-- RTX sources (IAR handlers) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s\" condition=\"IARASM ARMv8-MBL\"/>\n        <file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s\" condition=\"IARASM ARMv8-MML\"/>\n        <!-- OS Tick (SysTick) -->\n        <file category=\"source\" name=\"CMSIS/RTOS2/Source/os_systick.c\"/>\n      </files>\n    </component>\n\n    <!-- CMSIS-Driver Custom components -->\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"USART\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.4.0\" custom=\"1\">\n      <description>Access to #include Driver_USART.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_USART.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_USART.c\" select=\"USART Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"SPI\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.3.0\" custom=\"1\">\n      <description>Access to #include Driver_SPI.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_SPI.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_SPI.c\" select=\"SPI Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"SAI\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"1.2.0\" custom=\"1\">\n      <description>Access to #include Driver_SAI.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_SAI.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_SAI.c\" select=\"SAI Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"I2C\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.4.0\" custom=\"1\">\n      <description>Access to #include Driver_I2C.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_I2C.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_I2C.c\" select=\"I2C Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"CAN\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"1.3.0\" custom=\"1\">\n      <description>Access to #include Driver_CAN.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_CAN.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_CAN.c\" select=\"CAN Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"Flash\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.3.0\" custom=\"1\">\n      <description>Access to #include Driver_Flash.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_Flash.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_Flash.c\" select=\"Flash Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"MCI\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.4.0\" custom=\"1\">\n      <description>Access to #include Driver_MCI.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_MCI.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_MCI.c\" select=\"MCI Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"NAND\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.4.0\" custom=\"1\">\n      <description>Access to #include Driver_NAND.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_NAND.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_NAND.c\" select=\"NAND Flash Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"Ethernet\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.2.0\" custom=\"1\">\n      <description>Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_ETH_MAC.h\" />\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_ETH_PHY.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c\" select=\"Ethernet PHY and MAC Driver\"/>\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c\" select=\"Ethernet PHY and MAC Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"Ethernet MAC\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.2.0\" custom=\"1\">\n      <description>Access to #include Driver_ETH_MAC.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_ETH_MAC.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c\" select=\"Ethernet MAC Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"Ethernet PHY\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.2.0\" custom=\"1\">\n      <description>Access to #include Driver_ETH_PHY.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_ETH_PHY.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c\" select=\"Ethernet PHY Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"USB Device\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.3.0\" custom=\"1\">\n      <description>Access to #include Driver_USBD.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_USBD.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_USBD.c\" select=\"USB Device Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"USB Host\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"2.3.0\" custom=\"1\">\n      <description>Access to #include Driver_USBH.h file and code template for custom implementation</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_USBH.h\" />\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_USBH.c\" select=\"USB Host Driver\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"WiFi\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"1.1.0\" custom=\"1\">\n      <description>Access to #include Driver_WiFi.h file</description>\n      <files>\n        <file category=\"header\" name=\"CMSIS/Driver/Include/Driver_WiFi.h\"/>\n        <file category=\"sourceC\" attr=\"template\" name=\"CMSIS/Driver/DriverTemplates/Driver_WiFi.c\" select=\"WiFi Driver\"/>\n      </files>\n    </component>\n\n    <!-- VIO components -->\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"VIO\" Csub=\"Custom\" Cversion=\"1.0.0\" Capiversion=\"0.1.0\" custom=\"1\">\n      <description>Virtual I/O custom implementation template</description>\n      <files>\n        <file category=\"sourceC\" name=\"CMSIS/Driver/VIO/Source/vio.c\" attr=\"template\" select=\"Virtual I/O\"/>\n      </files>\n    </component>\n    <component Cclass=\"CMSIS Driver\" Cgroup=\"VIO\" Csub=\"Virtual\" Cversion=\"1.0.0\" Capiversion=\"0.1.0\">\n      <description>Virtual I/O implementation using memory only</description>\n      <files>\n        <file category=\"sourceC\" name=\"CMSIS/Driver/VIO/Source/vio_memory.c\"/>\n      </files>\n    </component>\n\n  </components>\n\n  <boards>\n    <board name=\"uVision Simulator\" vendor=\"Keil\">\n      <description>uVision Simulator</description>\n      <mountedDevice    deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM0\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM0P\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM0P_MPU\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM1\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM3\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM4\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM4_FP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM7\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM7_SP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM7_DP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv8MBL\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv8MML\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv8MML_SP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv8MML_DP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv81MML_DSP_DP_MVE_FP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM23\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM23_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM33\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM33_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM33_DSP_FP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM33_DSP_FP_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM35P\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM35P_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM35P_DSP_FP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM35P_DSP_FP_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM55\"/>\n    </board>\n\n    <board name=\"EWARM Simulator\" vendor=\"IAR\">\n      <description>EWARM Simulator</description>\n      <mountedDevice    deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM0\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM0P\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM0P_MPU\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM1\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM3\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM4\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM4_FP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM7\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM7_SP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM7_DP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv8MBL\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv8MML\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv8MML_SP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv8MML_DP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMv81MML_DSP_DP_MVE_FP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM23\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM23_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM33\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM33_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM33_DSP_FP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM33_DSP_FP_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM35P\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM35P_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM35P_DSP_FP\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM35P_DSP_FP_TZ\"/>\n      <compatibleDevice deviceIndex=\"0\" Dvendor=\"ARM:82\" Dname=\"ARMCM55\"/>\n    </board>\n  </boards>\n\n  <examples>\n    <example name=\"CMSIS-RTOS2 Blinky\" doc=\"Abstract.txt\" folder=\"CMSIS/RTOS2/RTX/Examples/Blinky\">\n      <description>CMSIS-RTOS2 Blinky example</description>\n      <board name=\"uVision Simulator\" vendor=\"Keil\"/>\n      <project>\n        <environment name=\"uv\" load=\"Blinky.uvprojx\"/>\n      </project>\n      <attributes>\n        <component Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n        <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\"/>\n        <component Cclass=\"Device\" Cgroup=\"Startup\"/>\n        <category>Getting Started</category>\n      </attributes>\n    </example>\n\n    <example name=\"CMSIS-RTOS2 RTX5 Migration\" doc=\"Abstract.txt\" folder=\"CMSIS/RTOS2/RTX/Examples/Migration\">\n      <description>CMSIS-RTOS2 mixed API v1 and v2</description>\n      <board name=\"uVision Simulator\" vendor=\"Keil\"/>\n      <project>\n        <environment name=\"uv\" load=\"Blinky.uvprojx\"/>\n      </project>\n      <attributes>\n        <component Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n        <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\"/>\n        <component Cclass=\"Device\" Cgroup=\"Startup\"/>\n        <category>Getting Started</category>\n      </attributes>\n    </example>\n\n    <example name=\"CMSIS-RTOS2 RTX5 Message Queue\" doc=\"Abstract.txt\" folder=\"CMSIS/RTOS2/RTX/Examples/MsgQueue\">\n      <description>CMSIS-RTOS2 Message Queue Example</description>\n      <board name=\"uVision Simulator\" vendor=\"Keil\"/>\n      <project>\n        <environment name=\"uv\" load=\"MsqQueue.uvprojx\"/>\n      </project>\n      <attributes>\n        <component Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n        <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\"/>\n        <component Cclass=\"Compiler\" Cgroup=\"EventRecorder\"/>\n        <component Cclass=\"Device\" Cgroup=\"Startup\"/>\n        <category>Getting Started</category>\n      </attributes>\n    </example>\n\n    <example name=\"CMSIS-RTOS2 RTX5 Memory Pool\" doc=\"Abstract.txt\" folder=\"CMSIS/RTOS2/RTX/Examples/MemPool\">\n      <description>CMSIS-RTOS2 Memory Pool Example</description>\n      <board name=\"uVision Simulator\" vendor=\"Keil\"/>\n      <project>\n        <environment name=\"uv\" load=\"MemPool.uvprojx\"/>\n      </project>\n      <attributes>\n        <component Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n        <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\"/>\n        <component Cclass=\"Compiler\" Cgroup=\"EventRecorder\"/>\n        <component Cclass=\"Device\" Cgroup=\"Startup\"/>\n        <category>Getting Started</category>\n      </attributes>\n    </example>\n\n    <example name=\"TrustZone for ARMv8-M No RTOS\" doc=\"Abstract.txt\" folder=\"CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS\">\n      <description>Bare-metal secure/non-secure example without RTOS</description>\n      <board name=\"uVision Simulator\" vendor=\"Keil\"/>\n      <project>\n        <environment name=\"uv\" load=\"NoRTOS.uvmpw\"/>\n      </project>\n      <attributes>\n        <component Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n        <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\"/>\n        <component Cclass=\"Device\" Cgroup=\"Startup\"/>\n        <category>Getting Started</category>\n      </attributes>\n    </example>\n\n    <example name=\"TrustZone for ARMv8-M RTOS\"  doc=\"Abstract.txt\" folder=\"CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS\">\n      <description>Secure/non-secure RTOS example with thread context management</description>\n      <board name=\"uVision Simulator\" vendor=\"Keil\"/>\n      <project>\n        <environment name=\"uv\" load=\"RTOS.uvmpw\"/>\n      </project>\n      <attributes>\n        <component Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n        <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\"/>\n        <component Cclass=\"Device\" Cgroup=\"Startup\"/>\n        <category>Getting Started</category>\n      </attributes>\n    </example>\n\n    <example name=\"TrustZone for ARMv8-M RTOS Security Tests\"  doc=\"Abstract.txt\" folder=\"CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults\">\n      <description>Secure/non-secure RTOS example with security test cases and system recovery</description>\n      <board name=\"uVision Simulator\" vendor=\"Keil\"/>\n      <project>\n        <environment name=\"uv\" load=\"RTOS_Faults.uvmpw\"/>\n      </project>\n      <attributes>\n        <component Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n        <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\"/>\n        <component Cclass=\"Device\" Cgroup=\"Startup\"/>\n        <category>Getting Started</category>\n      </attributes>\n    </example>\n\n    <example name=\"CMSIS-RTOS2 Blinky\" doc=\"Abstract.txt\" folder=\"CMSIS/RTOS2/RTX/Examples_IAR/Blinky\">\n      <description>CMSIS-RTOS2 Blinky example</description>\n      <board name=\"EWARM Simulator\" vendor=\"IAR\"/>\n      <project>\n        <environment name=\"iar\" load=\"Blinky/Blinky.ewp\"/>\n      </project>\n      <attributes>\n        <component Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n        <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\"/>\n        <component Cclass=\"Device\" Cgroup=\"Startup\"/>\n        <category>Getting Started</category>\n      </attributes>\n    </example>\n\n    <example name=\"CMSIS-RTOS2 RTX5 Message Queue\" doc=\"Abstract.txt\" folder=\"CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue\">\n      <description>CMSIS-RTOS2 Message Queue Example</description>\n      <board name=\"EWARM Simulator\" vendor=\"IAR\"/>\n      <project>\n        <environment name=\"iar\" load=\"MsgQueue/MsgQueue.ewp\"/>\n      </project>\n      <attributes>\n        <component Cclass=\"CMSIS\" Cgroup=\"CORE\"/>\n        <component Cclass=\"CMSIS\" Cgroup=\"RTOS2\"/>\n        <component Cclass=\"Device\" Cgroup=\"Startup\"/>\n        <category>Getting Started</category>\n      </attributes>\n    </example>\n\n  </examples>\n\n</package>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h",
    "content": "/******************************************************************************\n * @file     cachel1_armv7.h\n * @brief    CMSIS Level 1 Cache API for Armv7-M and later\n * @version  V1.0.3\n * @date     17. March 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2020-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n\n#ifndef ARM_CACHEL1_ARMV7_H\n#define ARM_CACHEL1_ARMV7_H\n\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_CacheFunctions Cache Functions\n  \\brief    Functions that configure Instruction and Data cache.\n  @{\n */\n\n/* Cache Size ID Register Macros */\n#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\n#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\n\n#ifndef __SCB_DCACHE_LINE_SIZE\n#define __SCB_DCACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */\n#endif\n\n#ifndef __SCB_ICACHE_LINE_SIZE\n#define __SCB_ICACHE_LINE_SIZE  32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */\n#endif\n\n/**\n  \\brief   Enable I-Cache\n  \\details Turns on I-Cache\n  */\n__STATIC_FORCEINLINE void SCB_EnableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */\n\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable I-Cache\n  \\details Turns off I-Cache\n  */\n__STATIC_FORCEINLINE void SCB_DisableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate I-Cache\n  \\details Invalidates I-Cache\n  */\n__STATIC_FORCEINLINE void SCB_InvalidateICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   I-Cache Invalidate by address\n  \\details Invalidates I-Cache for the given address.\n           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           I-Cache memory blocks which are part of given address + given size are invalidated.\n  \\param[in]   addr    address\n  \\param[in]   isize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    if ( isize > 0 ) {\n       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;\n\n      __DSB();\n\n      do {\n        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr += __SCB_ICACHE_LINE_SIZE;\n        op_size -= __SCB_ICACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n\n/**\n  \\brief   Enable D-Cache\n  \\details Turns on D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_EnableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n    __DSB();\n\n    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable D-Cache\n  \\details Turns off D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_DisableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    struct {\n      uint32_t ccsidr;\n      uint32_t sets;\n      uint32_t ways;\n    } locals\n    #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))\n       __ALIGNED(__SCB_DCACHE_LINE_SIZE)\n    #endif\n    ;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\n    __DSB();\n\n    #if !defined(__OPTIMIZE__)\n      /*\n       * For the endless loop issue with no optimization builds.\n       * More details, see https://github.com/ARM-software/CMSIS_5/issues/620\n       *\n       * The issue only happens when local variables are in stack. If\n       * local variables are saved in general purpose register, then the function\n       * is OK.\n       *\n       * When local variables are in stack, after disabling the cache, flush the\n       * local variables cache line for data consistency.\n       */\n      /* Clean and invalidate the local variable cache. */\n    #if defined(__ICCARM__)\n    /* As we can't align the stack to the cache line size, invalidate each of the variables */\n      SCB->DCCIMVAC = (uint32_t)&locals.sets;\n      SCB->DCCIMVAC = (uint32_t)&locals.ways;\n      SCB->DCCIMVAC = (uint32_t)&locals.ccsidr;\n    #else\n      SCB->DCCIMVAC = (uint32_t)&locals;\n    #endif\n      __DSB();\n      __ISB();\n    #endif\n\n    locals.ccsidr = SCB->CCSIDR;\n                                            /* clean & invalidate D-Cache */\n    locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));\n    do {\n      locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));\n      do {\n        SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (locals.ways-- != 0U);\n    } while(locals.sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate D-Cache\n  \\details Invalidates D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean D-Cache\n  \\details Cleans D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_CleanDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\n                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean & Invalidate D-Cache\n  \\details Cleans and Invalidates D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean & invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Invalidate by address\n  \\details Invalidates D-Cache for the given address.\n           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           D-Cache memory blocks which are part of given address + given size are invalidated.\n  \\param[in]   addr    address\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    if ( dsize > 0 ) {\n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\n\n      __DSB();\n\n      do {\n        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr += __SCB_DCACHE_LINE_SIZE;\n        op_size -= __SCB_DCACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean by address\n  \\details Cleans D-Cache for the given address\n           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.\n           D-Cache memory blocks which are part of given address + given size are cleaned.\n  \\param[in]   addr    address\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    if ( dsize > 0 ) {\n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\n\n      __DSB();\n\n      do {\n        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr += __SCB_DCACHE_LINE_SIZE;\n        op_size -= __SCB_DCACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean and Invalidate by address\n  \\details Cleans and invalidates D_Cache for the given address\n           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    if ( dsize > 0 ) {\n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\n\n      __DSB();\n\n      do {\n        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr +=          __SCB_DCACHE_LINE_SIZE;\n        op_size -=          __SCB_DCACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n/*@} end of CMSIS_Core_CacheFunctions */\n\n#endif /* ARM_CACHEL1_ARMV7_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armcc.h\n * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file\n * @version  V5.4.0\n * @date     20. January 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_ARMCC_H\n#define __CMSIS_ARMCC_H\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\n  #error \"Please use Arm Compiler Toolchain V4.0.677 or later!\"\n#endif\n\n/* CMSIS compiler control architecture macros */\n#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \\\n     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )\n  #define __ARM_ARCH_6M__           1\n#endif\n\n#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))\n  #define __ARM_ARCH_7M__           1\n#endif\n\n#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\n  #define __ARM_ARCH_7EM__          1\n#endif\n\n  /* __ARM_ARCH_8M_BASE__  not applicable */\n  /* __ARM_ARCH_8M_MAIN__  not applicable */\n  /* __ARM_ARCH_8_1M_MAIN__  not applicable */\n\n/* CMSIS compiler control DSP macros */\n#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n  #define __ARM_FEATURE_DSP         1\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   static __forceinline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __declspec(noreturn)\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        __packed struct\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         __packed union\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __memory_changed()\n#endif\n#ifndef __NO_INIT\n  #define __NO_INIT                              __attribute__ ((section (\".bss.noinit\"), zero_init))\n#endif\n#ifndef __ALIAS\n  #define __ALIAS(x)                             __attribute__ ((alias(x)))\n#endif\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n#define __PROGRAM_START           __main\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(\"RESET\")))\n#endif\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP                             __nop\n\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI                             __wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE                             __wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV                             __sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()                           __isb(0xF)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()                           __dsb(0xF)\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()                           __dmb(0xF)\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV                             __rev\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".rev16_text\"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\n{\n  rev16 r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".revsh_text\"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\n{\n  revsh r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n#define __ROR                             __ror\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __breakpoint(value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n  #define __RBIT                          __rbit\n#else\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n  return result;\n}\n#endif\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ                             __clz\n\n\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))\n#else\n  #define __LDREXB(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint8_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))\n#else\n  #define __LDREXH(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint16_t) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))\n#else\n  #define __LDREXW(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint32_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXB(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXB(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXH(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXH(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXW(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXW(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX                           __clrex\n\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT                            __ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT                            __usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".rrx_text\"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\n{\n  rrx r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRBT(value, ptr)               __strt(value, ptr)\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRHT(value, ptr)               __strt(value, ptr)\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRT(value, ptr)                __strt(value, ptr)\n\n#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq();     */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq();    */\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_INLINE uint32_t __get_CONTROL(void)\n{\n  register uint32_t __regControl         __ASM(\"control\");\n  return(__regControl);\n}\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_INLINE void __set_CONTROL(uint32_t control)\n{\n  register uint32_t __regControl         __ASM(\"control\");\n  __regControl = control;\n  __ISB();\n}\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_INLINE uint32_t __get_IPSR(void)\n{\n  register uint32_t __regIPSR          __ASM(\"ipsr\");\n  return(__regIPSR);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_INLINE uint32_t __get_APSR(void)\n{\n  register uint32_t __regAPSR          __ASM(\"apsr\");\n  return(__regAPSR);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_INLINE uint32_t __get_xPSR(void)\n{\n  register uint32_t __regXPSR          __ASM(\"xpsr\");\n  return(__regXPSR);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_INLINE uint32_t __get_PSP(void)\n{\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\n  return(__regProcessStackPointer);\n}\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\n  __regProcessStackPointer = topOfProcStack;\n}\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_INLINE uint32_t __get_MSP(void)\n{\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\n  return(__regMainStackPointer);\n}\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\n  __regMainStackPointer = topOfMainStack;\n}\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_INLINE uint32_t __get_PRIMASK(void)\n{\n  register uint32_t __regPriMask         __ASM(\"primask\");\n  return(__regPriMask);\n}\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\n{\n  register uint32_t __regPriMask         __ASM(\"primask\");\n  __regPriMask = (priMask);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_INLINE uint32_t  __get_BASEPRI(void)\n{\n  register uint32_t __regBasePri         __ASM(\"basepri\");\n  return(__regBasePri);\n}\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\n{\n  register uint32_t __regBasePri         __ASM(\"basepri\");\n  __regBasePri = (basePri & 0xFFU);\n}\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  register uint32_t __regBasePriMax      __ASM(\"basepri_max\");\n  __regBasePriMax = (basePri & 0xFFU);\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_INLINE uint32_t __get_FAULTMASK(void)\n{\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\n  return(__regFaultMask);\n}\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\n  __regFaultMask = (faultMask & (uint32_t)1U);\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_INLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  return(__regfpscr);\n#else\n   return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  __regfpscr = (fpscr);\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n#define __SADD8                           __sadd8\n#define __QADD8                           __qadd8\n#define __SHADD8                          __shadd8\n#define __UADD8                           __uadd8\n#define __UQADD8                          __uqadd8\n#define __UHADD8                          __uhadd8\n#define __SSUB8                           __ssub8\n#define __QSUB8                           __qsub8\n#define __SHSUB8                          __shsub8\n#define __USUB8                           __usub8\n#define __UQSUB8                          __uqsub8\n#define __UHSUB8                          __uhsub8\n#define __SADD16                          __sadd16\n#define __QADD16                          __qadd16\n#define __SHADD16                         __shadd16\n#define __UADD16                          __uadd16\n#define __UQADD16                         __uqadd16\n#define __UHADD16                         __uhadd16\n#define __SSUB16                          __ssub16\n#define __QSUB16                          __qsub16\n#define __SHSUB16                         __shsub16\n#define __USUB16                          __usub16\n#define __UQSUB16                         __uqsub16\n#define __UHSUB16                         __uhsub16\n#define __SASX                            __sasx\n#define __QASX                            __qasx\n#define __SHASX                           __shasx\n#define __UASX                            __uasx\n#define __UQASX                           __uqasx\n#define __UHASX                           __uhasx\n#define __SSAX                            __ssax\n#define __QSAX                            __qsax\n#define __SHSAX                           __shsax\n#define __USAX                            __usax\n#define __UQSAX                           __uqsax\n#define __UHSAX                           __uhsax\n#define __USAD8                           __usad8\n#define __USADA8                          __usada8\n#define __SSAT16                          __ssat16\n#define __USAT16                          __usat16\n#define __UXTB16                          __uxtb16\n#define __UXTAB16                         __uxtab16\n#define __SXTB16                          __sxtb16\n#define __SXTAB16                         __sxtab16\n#define __SMUAD                           __smuad\n#define __SMUADX                          __smuadx\n#define __SMLAD                           __smlad\n#define __SMLADX                          __smladx\n#define __SMLALD                          __smlald\n#define __SMLALDX                         __smlaldx\n#define __SMUSD                           __smusd\n#define __SMUSDX                          __smusdx\n#define __SMLSD                           __smlsd\n#define __SMLSDX                          __smlsdx\n#define __SMLSLD                          __smlsld\n#define __SMLSLDX                         __smlsldx\n#define __SEL                             __sel\n#define __QADD                            __qadd\n#define __QSUB                            __qsub\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\\n                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))\n\n#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))\n\n#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))\n\n#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCC_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armclang.h\n * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\n * @version  V5.5.0\n * @date     20. January 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\n\n#ifndef __CMSIS_ARMCLANG_H\n#define __CMSIS_ARMCLANG_H\n\n#pragma clang system_header   /* treat file as system include file */\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n#ifndef __NO_INIT\n  #define __NO_INIT                              __attribute__ ((section (\".bss.noinit\")))\n#endif\n#ifndef __ALIAS\n  #define __ALIAS(x)                             __attribute__ ((alias(x)))\n#endif\n\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n#define __PROGRAM_START           __main\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(\"RESET\")))\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#ifndef __STACK_SEAL\n#define __STACK_SEAL              Image$$STACKSEAL$$ZI$$Base\n#endif\n\n#ifndef __TZ_STACK_SEAL_SIZE\n#define __TZ_STACK_SEAL_SIZE      8U\n#endif\n\n#ifndef __TZ_STACK_SEAL_VALUE\n#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL\n#endif\n\n\n__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {\n  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;\n}\n#endif\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP          __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI          __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE          __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV          __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()        __builtin_arm_isb(0xF)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()        __builtin_arm_dsb(0xF)\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()        __builtin_arm_dmb(0xF)\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV(value)   __builtin_bswap32(value)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16(value) __ROR(__REV(value), 16)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REVSH(value) (int16_t)__builtin_bswap16(value)\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)     __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT            __builtin_arm_rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n\n#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT             __builtin_arm_ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n          (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n          (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n          (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n  return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n  return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n  return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n/** @}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n#ifndef __ARM_COMPAT_H\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n#ifndef __ARM_COMPAT_H\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n  __ISB();\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n  __ISB();\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\n#else\n#define __get_FPSCR()      ((uint32_t)0U)\n#endif\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __set_FPSCR      __builtin_arm_set_fpscr\n#else\n#define __set_FPSCR(fpscr)      ((void)(fpscr))\n#endif\n\n\n/** @} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n#define     __SADD8                 __builtin_arm_sadd8\n#define     __QADD8                 __builtin_arm_qadd8\n#define     __SHADD8                __builtin_arm_shadd8\n#define     __UADD8                 __builtin_arm_uadd8\n#define     __UQADD8                __builtin_arm_uqadd8\n#define     __UHADD8                __builtin_arm_uhadd8\n#define     __SSUB8                 __builtin_arm_ssub8\n#define     __QSUB8                 __builtin_arm_qsub8\n#define     __SHSUB8                __builtin_arm_shsub8\n#define     __USUB8                 __builtin_arm_usub8\n#define     __UQSUB8                __builtin_arm_uqsub8\n#define     __UHSUB8                __builtin_arm_uhsub8\n#define     __SADD16                __builtin_arm_sadd16\n#define     __QADD16                __builtin_arm_qadd16\n#define     __SHADD16               __builtin_arm_shadd16\n#define     __UADD16                __builtin_arm_uadd16\n#define     __UQADD16               __builtin_arm_uqadd16\n#define     __UHADD16               __builtin_arm_uhadd16\n#define     __SSUB16                __builtin_arm_ssub16\n#define     __QSUB16                __builtin_arm_qsub16\n#define     __SHSUB16               __builtin_arm_shsub16\n#define     __USUB16                __builtin_arm_usub16\n#define     __UQSUB16               __builtin_arm_uqsub16\n#define     __UHSUB16               __builtin_arm_uhsub16\n#define     __SASX                  __builtin_arm_sasx\n#define     __QASX                  __builtin_arm_qasx\n#define     __SHASX                 __builtin_arm_shasx\n#define     __UASX                  __builtin_arm_uasx\n#define     __UQASX                 __builtin_arm_uqasx\n#define     __UHASX                 __builtin_arm_uhasx\n#define     __SSAX                  __builtin_arm_ssax\n#define     __QSAX                  __builtin_arm_qsax\n#define     __SHSAX                 __builtin_arm_shsax\n#define     __USAX                  __builtin_arm_usax\n#define     __UQSAX                 __builtin_arm_uqsax\n#define     __UHSAX                 __builtin_arm_uhsax\n#define     __USAD8                 __builtin_arm_usad8\n#define     __USADA8                __builtin_arm_usada8\n#define     __SSAT16                __builtin_arm_ssat16\n#define     __USAT16                __builtin_arm_usat16\n#define     __UXTB16                __builtin_arm_uxtb16\n#define     __UXTAB16               __builtin_arm_uxtab16\n#define     __SXTB16                __builtin_arm_sxtb16\n#define     __SXTAB16               __builtin_arm_sxtab16\n#define     __SMUAD                 __builtin_arm_smuad\n#define     __SMUADX                __builtin_arm_smuadx\n#define     __SMLAD                 __builtin_arm_smlad\n#define     __SMLADX                __builtin_arm_smladx\n#define     __SMLALD                __builtin_arm_smlald\n#define     __SMLALDX               __builtin_arm_smlaldx\n#define     __SMUSD                 __builtin_arm_smusd\n#define     __SMUSDX                __builtin_arm_smusdx\n#define     __SMLSD                 __builtin_arm_smlsd\n#define     __SMLSDX                __builtin_arm_smlsdx\n#define     __SMLSLD                __builtin_arm_smlsld\n#define     __SMLSLDX               __builtin_arm_smlsldx\n#define     __SEL                   __builtin_arm_sel\n#define     __QADD                  __builtin_arm_qadd\n#define     __QSUB                  __builtin_arm_qsub\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))\n\n#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n  int32_t result;\n\n  __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/** @} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCLANG_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armclang_ltm.h\n * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\n * @version  V1.6.0\n * @date     20. January 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2018-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\n\n#ifndef __CMSIS_ARMCLANG_H\n#define __CMSIS_ARMCLANG_H\n\n#pragma clang system_header   /* treat file as system include file */\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n#ifndef __NO_INIT\n  #define __NO_INIT                              __attribute__ ((section (\".bss.noinit\")))\n#endif\n#ifndef __ALIAS\n  #define __ALIAS(x)                             __attribute__ ((alias(x)))\n#endif\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n#define __PROGRAM_START           __main\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(\"RESET\")))\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#ifndef __STACK_SEAL\n#define __STACK_SEAL              Image$$STACKSEAL$$ZI$$Base\n#endif\n\n#ifndef __TZ_STACK_SEAL_SIZE\n#define __TZ_STACK_SEAL_SIZE      8U\n#endif\n\n#ifndef __TZ_STACK_SEAL_VALUE\n#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL\n#endif\n\n\n__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {\n  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;\n}\n#endif\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP          __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI          __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE          __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV          __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()        __builtin_arm_isb(0xF)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()        __builtin_arm_dsb(0xF)\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()        __builtin_arm_dmb(0xF)\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV(value)   __builtin_bswap32(value)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16(value) __ROR(__REV(value), 16)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REVSH(value) (int16_t)__builtin_bswap16(value)\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)     __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT            __builtin_arm_rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT             __builtin_arm_ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n  return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n  return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n  return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n#ifndef __ARM_COMPAT_H\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n#ifndef __ARM_COMPAT_H\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n  __ISB();\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n  __ISB();\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\n#else\n#define __get_FPSCR()      ((uint32_t)0U)\n#endif\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __set_FPSCR      __builtin_arm_set_fpscr\n#else\n#define __set_FPSCR(x)      ((void)(x))\n#endif\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))\n\n#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n  int32_t result;\n\n  __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCLANG_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_compiler.h\n * @brief    CMSIS compiler generic header file\n * @version  V5.3.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_COMPILER_H\n#define __CMSIS_COMPILER_H\n\n#include <stdint.h>\n\n/*\n * Arm Compiler 4/5\n */\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n\n/*\n * Arm Compiler 6.6 LTM (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)\n  #include \"cmsis_armclang_ltm.h\"\n\n  /*\n * Arm Compiler above 6.10.1 (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  #include \"cmsis_armclang.h\"\n\n/*\n * TI Arm Clang Compiler (tiarmclang)\n */\n#elif defined (__ti__)\n  #include \"cmsis_tiarmclang.h\"\n\n/*\n * GNU Compiler\n */\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n\n/*\n * IAR Compiler\n */\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iccarm.h>\n\n\n/*\n * TI Arm Compiler (armcl)\n */\n#elif defined ( __TI_ARM__ )\n  #include <cmsis_ccs.h>\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __attribute__((packed))\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)                           __attribute__((aligned(x)))\n  #endif\n  #ifndef   __RESTRICT\n    #define __RESTRICT                             __restrict\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n  #ifndef __NO_INIT\n    #define __NO_INIT                              __attribute__ ((section (\".bss.noinit\")))\n  #endif\n  #ifndef __ALIAS\n    #define __ALIAS(x)                             __attribute__ ((alias(x)))\n  #endif\n\n/*\n * TASKING Compiler\n */\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __packed__\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __packed__\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __packed__\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __packed__ T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)              __align(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n  #ifndef __NO_INIT\n    #define __NO_INIT                              __attribute__ ((section (\".bss.noinit\")))\n  #endif\n  #ifndef __ALIAS\n    #define __ALIAS(x)                             __attribute__ ((alias(x)))\n  #endif\n\n/*\n * COSMIC Compiler\n */\n#elif defined ( __CSMC__ )\n   #include <cmsis_csm.h>\n\n #ifndef   __ASM\n    #define __ASM                                  _asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    // NO RETURN is automatically detected hence no warning here\n    #define __NO_RETURN\n  #endif\n  #ifndef   __USED\n    #warning No compiler specific solution for __USED. __USED is ignored.\n    #define __USED\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __weak\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               @packed\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        @packed struct\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         @packed union\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    @packed struct T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()                   (void)0\n  #endif\n  #ifndef __NO_INIT\n    #define __NO_INIT                              __attribute__ ((section (\".bss.noinit\")))\n  #endif\n  #ifndef __ALIAS\n    #define __ALIAS(x)                             __attribute__ ((alias(x)))\n  #endif\n\n#else\n  #error Unknown compiler.\n#endif\n\n\n#endif /* __CMSIS_COMPILER_H */\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_gcc.h\n * @brief    CMSIS compiler GCC header file\n * @version  V5.4.2\n * @date     17. December 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_GCC_H\n#define __CMSIS_GCC_H\n\n/* ignore some GCC warnings */\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n\n/* Fallback for __has_builtin */\n#ifndef __has_builtin\n  #define __has_builtin(x) (0)\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n#ifndef __NO_INIT\n  #define __NO_INIT                              __attribute__ ((section (\".bss.noinit\")))\n#endif\n#ifndef __ALIAS\n  #define __ALIAS(x)                             __attribute__ ((alias(x)))\n#endif\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n\n/**\n  \\brief   Initializes data and bss sections\n  \\details This default implementations initialized all data and additional bss\n           sections relying on .copy.table and .zero.table specified properly\n           in the used linker script.\n\n */\n__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)\n{\n  extern void _start(void) __NO_RETURN;\n\n  typedef struct __copy_table {\n    uint32_t const* src;\n    uint32_t* dest;\n    uint32_t  wlen;\n  } __copy_table_t;\n\n  typedef struct __zero_table {\n    uint32_t* dest;\n    uint32_t  wlen;\n  } __zero_table_t;\n\n  extern const __copy_table_t __copy_table_start__;\n  extern const __copy_table_t __copy_table_end__;\n  extern const __zero_table_t __zero_table_start__;\n  extern const __zero_table_t __zero_table_end__;\n\n  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {\n    for(uint32_t i=0u; i<pTable->wlen; ++i) {\n      pTable->dest[i] = pTable->src[i];\n    }\n  }\n\n  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {\n    for(uint32_t i=0u; i<pTable->wlen; ++i) {\n      pTable->dest[i] = 0u;\n    }\n  }\n\n  _start();\n}\n\n#define __PROGRAM_START           __cmsis_start\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              __StackTop\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             __StackLimit\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(\".vectors\")))\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#ifndef __STACK_SEAL\n#define __STACK_SEAL              __StackSeal\n#endif\n\n#ifndef __TZ_STACK_SEAL_SIZE\n#define __TZ_STACK_SEAL_SIZE      8U\n#endif\n\n#ifndef __TZ_STACK_SEAL_VALUE\n#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL\n#endif\n\n\n__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {\n  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;\n}\n#endif\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP()                             __ASM volatile (\"nop\")\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI()                             __ASM volatile (\"wfi\":::\"memory\")\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE()                             __ASM volatile (\"wfe\":::\"memory\")\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV()                             __ASM volatile (\"sev\")\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n__STATIC_FORCEINLINE void __ISB(void)\n{\n  __ASM volatile (\"isb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n__STATIC_FORCEINLINE void __DSB(void)\n{\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n__STATIC_FORCEINLINE void __DMB(void)\n{\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\n  return __builtin_bswap32(value);\n#else\n  uint32_t result;\n\n  __ASM (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n  return (int16_t)__builtin_bswap16(value);\n#else\n  int16_t result;\n\n  __ASM (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n   __ASM (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n#else\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n#endif\n  return result;\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n__STATIC_FORCEINLINE void __CLREX(void)\n{\n  __ASM volatile (\"clrex\" ::: \"memory\");\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT(ARG1, ARG2) \\\n__extension__ \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM volatile (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) : \"cc\" ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT(ARG1, ARG2) \\\n__extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM volatile (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) : \"cc\" ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexb %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexh %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaex %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n   return(result);\n}\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n  __ISB();\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n  __ISB();\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n#define STACK_SIZE 0x80 // ջС128ֽڣ\n#define STACK_END  0x20004000 // ջַ\n__STATIC_FORCEINLINE void ClearStack(void) {\n    uint32_t *stack_ptr = (uint32_t *)STACK_END; // ջַ\n    uint32_t stack_bottom = (uint32_t)stack_ptr - STACK_SIZE; // ջʼַ\n\n    while ((uint32_t)stack_ptr > stack_bottom) {\n        stack_ptr--;\n        *stack_ptr = 0; // ջ\n    }\n}\n__STATIC_FORCEINLINE uint32_t __get_PC(void) {\n    uint32_t result;\n    __ASM volatile (\n            \"MOV %0, r15\\n\"\n            : \"=r\" (result)\n            );\n    return result;\n}\n\n__STATIC_FORCEINLINE void __set_PC(uint32_t pc) {\n    __ASM volatile (\n            \"MOV r15, %0\\n\"\n            :\n            : \"r\" (pc)\n            );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_get_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  return __builtin_arm_get_fpscr();\n#else\n  uint32_t result;\n\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n  return(result);\n#endif\n#else\n  return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_set_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  __builtin_arm_set_fpscr(fpscr);\n#else\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\", \"memory\");\n#endif\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1, ARG2) \\\n__extension__ \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM volatile (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) : \"cc\" ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1, ARG2) \\\n__extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM volatile (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) : \"cc\" ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)\n{\n  uint32_t result;\n  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {\n    __ASM volatile (\"sxtb16 %0, %1, ROR %2\" : \"=r\" (result) : \"r\" (op1), \"i\" (rotate) );\n  } else {\n    result = __SXTB16(__ROR(op1, rotate)) ;\n  }\n  return result;\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)\n{\n  uint32_t result;\n  if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {\n    __ASM volatile (\"sxtab16 %0, %1, %2, ROR %3\" : \"=r\" (result) : \"r\" (op1) , \"r\" (op2) , \"i\" (rotate));\n  } else {\n    result = __SXTAB16(op1, __ROR(op2, rotate));\n  }\n  return result;\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n__extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n__extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#pragma GCC diagnostic pop\n\n#endif /* __CMSIS_GCC_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_iccarm.h\n * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file\n * @version  V5.4.0\n * @date     20. January 2023\n ******************************************************************************/\n\n//------------------------------------------------------------------------------\n//\n// Copyright (c) 2017-2021 IAR Systems\n// Copyright (c) 2017-2023 Arm Limited. All rights reserved.\n//\n// SPDX-License-Identifier: Apache-2.0\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\")\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//     http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n//------------------------------------------------------------------------------\n\n\n#ifndef __CMSIS_ICCARM_H__\n#define __CMSIS_ICCARM_H__\n\n#ifndef __ICCARM__\n  #error This file should only be compiled by ICCARM\n#endif\n\n#pragma system_include\n\n#define __IAR_FT _Pragma(\"inline=forced\") __intrinsic\n\n#if (__VER__ >= 8000000)\n  #define __ICCARM_V8 1\n#else\n  #define __ICCARM_V8 0\n#endif\n\n#ifndef __ALIGNED\n  #if __ICCARM_V8\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #elif (__VER__ >= 7080000)\n    /* Needs IAR language extensions */\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #else\n    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n#endif\n\n\n/* Define compiler macros for CPU architecture, used in CMSIS 5.\n */\n#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\n/* Macros already defined */\n#else\n  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #elif defined(__ARM8M_BASELINE__)\n    #define __ARM_ARCH_8M_BASE__ 1\n  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\n    #if __ARM_ARCH == 6\n      #define __ARM_ARCH_6M__ 1\n    #elif __ARM_ARCH == 7\n      #if __ARM_FEATURE_DSP\n        #define __ARM_ARCH_7EM__ 1\n      #else\n        #define __ARM_ARCH_7M__ 1\n      #endif\n    #endif /* __ARM_ARCH */\n  #endif /* __ARM_ARCH_PROFILE == 'M' */\n#endif\n\n/* Alternativ core deduction for older ICCARM's */\n#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\\n    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\n  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\n    #define __ARM_ARCH_6M__ 1\n  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\n    #define __ARM_ARCH_7M__ 1\n  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\n    #define __ARM_ARCH_7EM__  1\n  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\n    #define __ARM_ARCH_8M_BASE__ 1\n  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #else\n    #error \"Unknown target.\"\n  #endif\n#endif\n\n\n\n#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\n  #define __IAR_M0_FAMILY  1\n#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\n  #define __IAR_M0_FAMILY  1\n#else\n  #define __IAR_M0_FAMILY  0\n#endif\n\n#ifndef __NO_INIT\n  #define __NO_INIT __attribute__ ((section (\".noinit\")))\n#endif\n#ifndef __ALIAS\n  #define __ALIAS(x) __attribute__ ((alias(x)))\n#endif\n\n#ifndef __ASM\n  #define __ASM __asm\n#endif\n\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER() __ASM volatile(\"\":::\"memory\")\n#endif\n\n#ifndef __INLINE\n  #define __INLINE inline\n#endif\n\n#ifndef   __NO_RETURN\n  #if __ICCARM_V8\n    #define __NO_RETURN __attribute__((__noreturn__))\n  #else\n    #define __NO_RETURN _Pragma(\"object_attribute=__noreturn\")\n  #endif\n#endif\n\n#ifndef   __PACKED\n  #if __ICCARM_V8\n    #define __PACKED __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED __packed\n  #endif\n#endif\n\n#ifndef   __PACKED_STRUCT\n  #if __ICCARM_V8\n    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_STRUCT __packed struct\n  #endif\n#endif\n\n#ifndef   __PACKED_UNION\n  #if __ICCARM_V8\n    #define __PACKED_UNION union __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_UNION __packed union\n  #endif\n#endif\n\n#ifndef   __RESTRICT\n  #if __ICCARM_V8\n    #define __RESTRICT            __restrict\n  #else\n    /* Needs IAR language extensions */\n    #define __RESTRICT            restrict\n  #endif\n#endif\n\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE       static inline\n#endif\n\n#ifndef   __FORCEINLINE\n  #define __FORCEINLINE         _Pragma(\"inline=forced\")\n#endif\n\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE\n#endif\n\n#ifndef __UNALIGNED_UINT16_READ\n#pragma language=save\n#pragma language=extended\n__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\n{\n  return *(__packed uint16_t*)(ptr);\n}\n#pragma language=restore\n#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\n#endif\n\n\n#ifndef __UNALIGNED_UINT16_WRITE\n#pragma language=save\n#pragma language=extended\n__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\n{\n  *(__packed uint16_t*)(ptr) = val;;\n}\n#pragma language=restore\n#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\n#endif\n\n#ifndef __UNALIGNED_UINT32_READ\n#pragma language=save\n#pragma language=extended\n__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\n{\n  return *(__packed uint32_t*)(ptr);\n}\n#pragma language=restore\n#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\n#endif\n\n#ifndef __UNALIGNED_UINT32_WRITE\n#pragma language=save\n#pragma language=extended\n__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\n{\n  *(__packed uint32_t*)(ptr) = val;;\n}\n#pragma language=restore\n#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\n#endif\n\n#ifndef __UNALIGNED_UINT32   /* deprecated */\n#pragma language=save\n#pragma language=extended\n__packed struct  __iar_u32 { uint32_t v; };\n#pragma language=restore\n#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\n#endif\n\n#ifndef   __USED\n  #if __ICCARM_V8\n    #define __USED __attribute__((used))\n  #else\n    #define __USED _Pragma(\"__root\")\n  #endif\n#endif\n\n#undef __WEAK                           /* undo the definition from DLib_Defaults.h */\n#ifndef   __WEAK\n  #if __ICCARM_V8\n    #define __WEAK __attribute__((weak))\n  #else\n    #define __WEAK _Pragma(\"__weak\")\n  #endif\n#endif\n\n#ifndef __PROGRAM_START\n#define __PROGRAM_START           __iar_program_start\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              CSTACK$$Limit\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             CSTACK$$Base\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __vector_table\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  @\".intvec\"\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#ifndef __STACK_SEAL\n#define __STACK_SEAL              STACKSEAL$$Base\n#endif\n\n#ifndef __TZ_STACK_SEAL_SIZE\n#define __TZ_STACK_SEAL_SIZE      8U\n#endif\n\n#ifndef __TZ_STACK_SEAL_VALUE\n#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL\n#endif\n\n__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {\n  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;\n}\n#endif\n\n#ifndef __ICCARM_INTRINSICS_VERSION__\n  #define __ICCARM_INTRINSICS_VERSION__  0\n#endif\n\n#if __ICCARM_INTRINSICS_VERSION__ == 2\n\n  #if defined(__CLZ)\n    #undef __CLZ\n  #endif\n  #if defined(__REVSH)\n    #undef __REVSH\n  #endif\n  #if defined(__RBIT)\n    #undef __RBIT\n  #endif\n  #if defined(__SSAT)\n    #undef __SSAT\n  #endif\n  #if defined(__USAT)\n    #undef __USAT\n  #endif\n\n  #include \"iccarm_builtin.h\"\n\n  #define __disable_fault_irq __iar_builtin_disable_fiq\n  #define __disable_irq       __iar_builtin_disable_interrupt\n  #define __enable_fault_irq  __iar_builtin_enable_fiq\n  #define __enable_irq        __iar_builtin_enable_interrupt\n  #define __arm_rsr           __iar_builtin_rsr\n  #define __arm_wsr           __iar_builtin_wsr\n\n\n  #define __get_APSR()                (__arm_rsr(\"APSR\"))\n  #define __get_BASEPRI()             (__arm_rsr(\"BASEPRI\"))\n  #define __get_CONTROL()             (__arm_rsr(\"CONTROL\"))\n  #define __get_FAULTMASK()           (__arm_rsr(\"FAULTMASK\"))\n\n  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n    #define __get_FPSCR()             (__arm_rsr(\"FPSCR\"))\n    #define __set_FPSCR(VALUE)        (__arm_wsr(\"FPSCR\", (VALUE)))\n  #else\n    #define __get_FPSCR()             ( 0 )\n    #define __set_FPSCR(VALUE)        ((void)VALUE)\n  #endif\n\n  #define __get_IPSR()                (__arm_rsr(\"IPSR\"))\n  #define __get_MSP()                 (__arm_rsr(\"MSP\"))\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure MSPLIM is RAZ/WI\n    #define __get_MSPLIM()            (0U)\n  #else\n    #define __get_MSPLIM()            (__arm_rsr(\"MSPLIM\"))\n  #endif\n  #define __get_PRIMASK()             (__arm_rsr(\"PRIMASK\"))\n  #define __get_PSP()                 (__arm_rsr(\"PSP\"))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __get_PSPLIM()            (0U)\n  #else\n    #define __get_PSPLIM()            (__arm_rsr(\"PSPLIM\"))\n  #endif\n\n  #define __get_xPSR()                (__arm_rsr(\"xPSR\"))\n\n  #define __set_BASEPRI(VALUE)        (__arm_wsr(\"BASEPRI\", (VALUE)))\n  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr(\"BASEPRI_MAX\", (VALUE)))\n\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __arm_wsr(\"CONTROL\", control);\n  __iar_builtin_ISB();\n}\n\n  #define __set_FAULTMASK(VALUE)      (__arm_wsr(\"FAULTMASK\", (VALUE)))\n  #define __set_MSP(VALUE)            (__arm_wsr(\"MSP\", (VALUE)))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure MSPLIM is RAZ/WI\n    #define __set_MSPLIM(VALUE)       ((void)(VALUE))\n  #else\n    #define __set_MSPLIM(VALUE)       (__arm_wsr(\"MSPLIM\", (VALUE)))\n  #endif\n  #define __set_PRIMASK(VALUE)        (__arm_wsr(\"PRIMASK\", (VALUE)))\n  #define __set_PSP(VALUE)            (__arm_wsr(\"PSP\", (VALUE)))\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __set_PSPLIM(VALUE)       ((void)(VALUE))\n  #else\n    #define __set_PSPLIM(VALUE)       (__arm_wsr(\"PSPLIM\", (VALUE)))\n  #endif\n\n  #define __TZ_get_CONTROL_NS()       (__arm_rsr(\"CONTROL_NS\"))\n\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __arm_wsr(\"CONTROL_NS\", control);\n  __iar_builtin_ISB();\n}\n\n  #define __TZ_get_PSP_NS()           (__arm_rsr(\"PSP_NS\"))\n  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr(\"PSP_NS\", (VALUE)))\n  #define __TZ_get_MSP_NS()           (__arm_rsr(\"MSP_NS\"))\n  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr(\"MSP_NS\", (VALUE)))\n  #define __TZ_get_SP_NS()            (__arm_rsr(\"SP_NS\"))\n  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr(\"SP_NS\", (VALUE)))\n  #define __TZ_get_PRIMASK_NS()       (__arm_rsr(\"PRIMASK_NS\"))\n  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr(\"PRIMASK_NS\", (VALUE)))\n  #define __TZ_get_BASEPRI_NS()       (__arm_rsr(\"BASEPRI_NS\"))\n  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr(\"BASEPRI_NS\", (VALUE)))\n  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr(\"FAULTMASK_NS\"))\n  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr(\"FAULTMASK_NS\", (VALUE)))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __TZ_get_PSPLIM_NS()      (0U)\n    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\n  #else\n    #define __TZ_get_PSPLIM_NS()      (__arm_rsr(\"PSPLIM_NS\"))\n    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr(\"PSPLIM_NS\", (VALUE)))\n  #endif\n\n  #define __TZ_get_MSPLIM_NS()        (__arm_rsr(\"MSPLIM_NS\"))\n  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr(\"MSPLIM_NS\", (VALUE)))\n\n  #define __NOP     __iar_builtin_no_operation\n\n  #define __CLZ     __iar_builtin_CLZ\n  #define __CLREX   __iar_builtin_CLREX\n\n  #define __DMB     __iar_builtin_DMB\n  #define __DSB     __iar_builtin_DSB\n  #define __ISB     __iar_builtin_ISB\n\n  #define __LDREXB  __iar_builtin_LDREXB\n  #define __LDREXH  __iar_builtin_LDREXH\n  #define __LDREXW  __iar_builtin_LDREX\n\n  #define __RBIT    __iar_builtin_RBIT\n  #define __REV     __iar_builtin_REV\n  #define __REV16   __iar_builtin_REV16\n\n  __IAR_FT int16_t __REVSH(int16_t val)\n  {\n    return (int16_t) __iar_builtin_REVSH(val);\n  }\n\n  #define __ROR     __iar_builtin_ROR\n  #define __RRX     __iar_builtin_RRX\n\n  #define __SEV     __iar_builtin_SEV\n\n  #if !__IAR_M0_FAMILY\n    #define __SSAT    __iar_builtin_SSAT\n  #endif\n\n  #define __STREXB  __iar_builtin_STREXB\n  #define __STREXH  __iar_builtin_STREXH\n  #define __STREXW  __iar_builtin_STREX\n\n  #if !__IAR_M0_FAMILY\n    #define __USAT    __iar_builtin_USAT\n  #endif\n\n  #define __WFE     __iar_builtin_WFE\n  #define __WFI     __iar_builtin_WFI\n\n  #if __ARM_MEDIA__\n    #define __SADD8   __iar_builtin_SADD8\n    #define __QADD8   __iar_builtin_QADD8\n    #define __SHADD8  __iar_builtin_SHADD8\n    #define __UADD8   __iar_builtin_UADD8\n    #define __UQADD8  __iar_builtin_UQADD8\n    #define __UHADD8  __iar_builtin_UHADD8\n    #define __SSUB8   __iar_builtin_SSUB8\n    #define __QSUB8   __iar_builtin_QSUB8\n    #define __SHSUB8  __iar_builtin_SHSUB8\n    #define __USUB8   __iar_builtin_USUB8\n    #define __UQSUB8  __iar_builtin_UQSUB8\n    #define __UHSUB8  __iar_builtin_UHSUB8\n    #define __SADD16  __iar_builtin_SADD16\n    #define __QADD16  __iar_builtin_QADD16\n    #define __SHADD16 __iar_builtin_SHADD16\n    #define __UADD16  __iar_builtin_UADD16\n    #define __UQADD16 __iar_builtin_UQADD16\n    #define __UHADD16 __iar_builtin_UHADD16\n    #define __SSUB16  __iar_builtin_SSUB16\n    #define __QSUB16  __iar_builtin_QSUB16\n    #define __SHSUB16 __iar_builtin_SHSUB16\n    #define __USUB16  __iar_builtin_USUB16\n    #define __UQSUB16 __iar_builtin_UQSUB16\n    #define __UHSUB16 __iar_builtin_UHSUB16\n    #define __SASX    __iar_builtin_SASX\n    #define __QASX    __iar_builtin_QASX\n    #define __SHASX   __iar_builtin_SHASX\n    #define __UASX    __iar_builtin_UASX\n    #define __UQASX   __iar_builtin_UQASX\n    #define __UHASX   __iar_builtin_UHASX\n    #define __SSAX    __iar_builtin_SSAX\n    #define __QSAX    __iar_builtin_QSAX\n    #define __SHSAX   __iar_builtin_SHSAX\n    #define __USAX    __iar_builtin_USAX\n    #define __UQSAX   __iar_builtin_UQSAX\n    #define __UHSAX   __iar_builtin_UHSAX\n    #define __USAD8   __iar_builtin_USAD8\n    #define __USADA8  __iar_builtin_USADA8\n    #define __SSAT16  __iar_builtin_SSAT16\n    #define __USAT16  __iar_builtin_USAT16\n    #define __UXTB16  __iar_builtin_UXTB16\n    #define __UXTAB16 __iar_builtin_UXTAB16\n    #define __SXTB16  __iar_builtin_SXTB16\n    #define __SXTAB16 __iar_builtin_SXTAB16\n    #define __SMUAD   __iar_builtin_SMUAD\n    #define __SMUADX  __iar_builtin_SMUADX\n    #define __SMMLA   __iar_builtin_SMMLA\n    #define __SMLAD   __iar_builtin_SMLAD\n    #define __SMLADX  __iar_builtin_SMLADX\n    #define __SMLALD  __iar_builtin_SMLALD\n    #define __SMLALDX __iar_builtin_SMLALDX\n    #define __SMUSD   __iar_builtin_SMUSD\n    #define __SMUSDX  __iar_builtin_SMUSDX\n    #define __SMLSD   __iar_builtin_SMLSD\n    #define __SMLSDX  __iar_builtin_SMLSDX\n    #define __SMLSLD  __iar_builtin_SMLSLD\n    #define __SMLSLDX __iar_builtin_SMLSLDX\n    #define __SEL     __iar_builtin_SEL\n    #define __QADD    __iar_builtin_QADD\n    #define __QSUB    __iar_builtin_QSUB\n    #define __PKHBT   __iar_builtin_PKHBT\n    #define __PKHTB   __iar_builtin_PKHTB\n  #endif\n\n#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n  #if __IAR_M0_FAMILY\n   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\n    #define __CLZ  __cmsis_iar_clz_not_active\n    #define __SSAT __cmsis_iar_ssat_not_active\n    #define __USAT __cmsis_iar_usat_not_active\n    #define __RBIT __cmsis_iar_rbit_not_active\n    #define __get_APSR  __cmsis_iar_get_APSR_not_active\n  #endif\n\n\n  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\n    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\n    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\n  #endif\n\n  #ifdef __INTRINSICS_INCLUDED\n  #error intrinsics.h is already included previously!\n  #endif\n\n  #include <intrinsics.h>\n\n  #if __IAR_M0_FAMILY\n   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\n    #undef __CLZ\n    #undef __SSAT\n    #undef __USAT\n    #undef __RBIT\n    #undef __get_APSR\n\n    __STATIC_INLINE uint8_t __CLZ(uint32_t data)\n    {\n      if (data == 0U) { return 32U; }\n\n      uint32_t count = 0U;\n      uint32_t mask = 0x80000000U;\n\n      while ((data & mask) == 0U)\n      {\n        count += 1U;\n        mask = mask >> 1U;\n      }\n      return count;\n    }\n\n    __STATIC_INLINE uint32_t __RBIT(uint32_t v)\n    {\n      uint8_t sc = 31U;\n      uint32_t r = v;\n      for (v >>= 1U; v; v >>= 1U)\n      {\n        r <<= 1U;\n        r |= v & 1U;\n        sc--;\n      }\n      return (r << sc);\n    }\n\n    __STATIC_INLINE  uint32_t __get_APSR(void)\n    {\n      uint32_t res;\n      __asm(\"MRS      %0,APSR\" : \"=r\" (res));\n      return res;\n    }\n\n  #endif\n\n  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\n    #undef __get_FPSCR\n    #undef __set_FPSCR\n    #define __get_FPSCR()       (0)\n    #define __set_FPSCR(VALUE)  ((void)VALUE)\n  #endif\n\n  #pragma diag_suppress=Pe940\n  #pragma diag_suppress=Pe177\n\n  #define __enable_irq    __enable_interrupt\n  #define __disable_irq   __disable_interrupt\n  #define __NOP           __no_operation\n\n  #define __get_xPSR      __get_PSR\n\n  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\n\n    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\n    {\n      return __LDREX((unsigned long *)ptr);\n    }\n\n    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\n    {\n      return __STREX(value, (unsigned long *)ptr);\n    }\n  #endif\n\n\n  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\n  #if (__CORTEX_M >= 0x03)\n\n    __IAR_FT uint32_t __RRX(uint32_t value)\n    {\n      uint32_t result;\n      __ASM volatile(\"RRX      %0, %1\" : \"=r\"(result) : \"r\" (value));\n      return(result);\n    }\n\n    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\n    {\n      __asm volatile(\"MSR      BASEPRI_MAX,%0\"::\"r\" (value));\n    }\n\n\n    #define __enable_fault_irq  __enable_fiq\n    #define __disable_fault_irq __disable_fiq\n\n\n  #endif /* (__CORTEX_M >= 0x03) */\n\n  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\n  {\n    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\n  }\n\n  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n   __IAR_FT uint32_t __get_MSPLIM(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure MSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,MSPLIM\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __set_MSPLIM(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure MSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      MSPLIM,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t __get_PSPLIM(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,PSPLIM\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __set_PSPLIM(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      PSPLIM,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,CONTROL_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      CONTROL_NS,%0\" :: \"r\" (value));\n      __iar_builtin_ISB();\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,PSP_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      PSP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,MSP_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      MSP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_SP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,SP_NS\" : \"=r\" (res));\n      return res;\n    }\n    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      SP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,PRIMASK_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      PRIMASK_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,BASEPRI_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      BASEPRI_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,FAULTMASK_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      FAULTMASK_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,PSPLIM_NS\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      PSPLIM_NS,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,MSPLIM_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      MSPLIM_NS,%0\" :: \"r\" (value));\n    }\n\n  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\n\n#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n#define __BKPT(value)    __asm volatile (\"BKPT     %0\" : : \"i\"(value))\n\n#if __IAR_M0_FAMILY\n  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\n  {\n    if ((sat >= 1U) && (sat <= 32U))\n    {\n      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n      const int32_t min = -1 - max ;\n      if (val > max)\n      {\n        return max;\n      }\n      else if (val < min)\n      {\n        return min;\n      }\n    }\n    return val;\n  }\n\n  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\n  {\n    if (sat <= 31U)\n    {\n      const uint32_t max = ((1U << sat) - 1U);\n      if (val > (int32_t)max)\n      {\n        return max;\n      }\n      else if (val < 0)\n      {\n        return 0U;\n      }\n    }\n    return (uint32_t)val;\n  }\n#endif\n\n#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\n\n  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDRBT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDRHT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDRT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\n  {\n    __ASM volatile (\"STRBT %1, [%0]\" : : \"r\" (addr), \"r\" ((uint32_t)value) : \"memory\");\n  }\n\n  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\n  {\n    __ASM volatile (\"STRHT %1, [%0]\" : : \"r\" (addr), \"r\" ((uint32_t)value) : \"memory\");\n  }\n\n  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\n  {\n    __ASM volatile (\"STRT %1, [%0]\" : : \"r\" (addr), \"r\" (value) : \"memory\");\n  }\n\n#endif /* (__CORTEX_M >= 0x03) */\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n\n  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAB %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAH %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDA %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\n  {\n    __ASM volatile (\"STLB %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\n  {\n    __ASM volatile (\"STLH %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\n  {\n    __ASM volatile (\"STL %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEXB %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEXH %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEX %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEXB %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEXH %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEX %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\n\n#undef __IAR_FT\n#undef __IAR_M0_FAMILY\n#undef __ICCARM_V8\n\n#pragma diag_default=Pe940\n#pragma diag_default=Pe177\n\n#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))\n\n#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))\n\n#endif /* __CMSIS_ICCARM_H__ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/cmsis_tiarmclang.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_tiarmclang.h\n * @brief    CMSIS compiler tiarmclang header file\n * @version  V1.0.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\n\n#ifndef __CMSIS_TIARMCLANG_H\n#define __CMSIS_TIARMCLANG_H\n\n#pragma clang system_header   /* treat file as system include file */\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n#ifndef __NO_INIT\n  #define __NO_INIT                              __attribute__ ((section (\".bss.noinit\")))\n#endif\n#ifndef __ALIAS\n  #define __ALIAS(x)                             __attribute__ ((alias(x)))\n#endif\n\n\n/* #########################  Startup and Lowlevel Init  ######################## */\n\n#ifndef __PROGRAM_START\n#define __PROGRAM_START           _c_int00\n#endif\n\n#ifndef __INITIAL_SP\n#define __INITIAL_SP              __STACK_END\n#endif\n\n#ifndef __STACK_LIMIT\n#define __STACK_LIMIT             __STACK_SIZE\n#endif\n\n#ifndef __VECTOR_TABLE\n#define __VECTOR_TABLE            __Vectors\n#endif\n\n#ifndef __VECTOR_TABLE_ATTRIBUTE\n#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(\".intvecs\")))\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#ifndef __STACK_SEAL\n#define __STACK_SEAL              Image$$STACKSEAL$$ZI$$Base\n#endif\n\n#ifndef __TZ_STACK_SEAL_SIZE\n#define __TZ_STACK_SEAL_SIZE      8U\n#endif\n\n#ifndef __TZ_STACK_SEAL_VALUE\n#define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL\n#endif\n\n\n__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {\n  *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;\n}\n#endif\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP          __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI          __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE          __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV          __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()        __builtin_arm_isb(0xF)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()        __builtin_arm_dsb(0xF)\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()        __builtin_arm_dmb(0xF)\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV(value)   __builtin_bswap32(value)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16(value) __ROR(__REV(value), 16)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REVSH(value) (int16_t)__builtin_bswap16(value)\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)     __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT            __builtin_arm_rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n\n#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT             __builtin_arm_ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n          (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n          (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n          (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n  return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n  return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) : \"memory\" );\n  return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) : \"memory\" );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n/** @}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n#ifndef __ARM_COMPAT_H\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n#ifndef __ARM_COMPAT_H\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n  __ISB();\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n  __ISB();\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__       ) && (__ARM_ARCH_7M__        == 1)) || \\\n           (defined (__ARM_ARCH_7EM__      ) && (__ARM_ARCH_7EM__       == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!((defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n       (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))   ) )\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__  ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__  ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n           (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1))     ) */\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\n#else\n#define __get_FPSCR()      ((uint32_t)0U)\n#endif\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __set_FPSCR      __builtin_arm_set_fpscr\n#else\n#define __set_FPSCR(fpscr)      ((void)(fpscr))\n#endif\n\n\n/** @} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n#define     __SADD8                 __builtin_arm_sadd8\n#define     __QADD8                 __builtin_arm_qadd8\n#define     __SHADD8                __builtin_arm_shadd8\n#define     __UADD8                 __builtin_arm_uadd8\n#define     __UQADD8                __builtin_arm_uqadd8\n#define     __UHADD8                __builtin_arm_uhadd8\n#define     __SSUB8                 __builtin_arm_ssub8\n#define     __QSUB8                 __builtin_arm_qsub8\n#define     __SHSUB8                __builtin_arm_shsub8\n#define     __USUB8                 __builtin_arm_usub8\n#define     __UQSUB8                __builtin_arm_uqsub8\n#define     __UHSUB8                __builtin_arm_uhsub8\n#define     __SADD16                __builtin_arm_sadd16\n#define     __QADD16                __builtin_arm_qadd16\n#define     __SHADD16               __builtin_arm_shadd16\n#define     __UADD16                __builtin_arm_uadd16\n#define     __UQADD16               __builtin_arm_uqadd16\n#define     __UHADD16               __builtin_arm_uhadd16\n#define     __SSUB16                __builtin_arm_ssub16\n#define     __QSUB16                __builtin_arm_qsub16\n#define     __SHSUB16               __builtin_arm_shsub16\n#define     __USUB16                __builtin_arm_usub16\n#define     __UQSUB16               __builtin_arm_uqsub16\n#define     __UHSUB16               __builtin_arm_uhsub16\n#define     __SASX                  __builtin_arm_sasx\n#define     __QASX                  __builtin_arm_qasx\n#define     __SHASX                 __builtin_arm_shasx\n#define     __UASX                  __builtin_arm_uasx\n#define     __UQASX                 __builtin_arm_uqasx\n#define     __UHASX                 __builtin_arm_uhasx\n#define     __SSAX                  __builtin_arm_ssax\n#define     __QSAX                  __builtin_arm_qsax\n#define     __SHSAX                 __builtin_arm_shsax\n#define     __USAX                  __builtin_arm_usax\n#define     __UQSAX                 __builtin_arm_uqsax\n#define     __UHSAX                 __builtin_arm_uhsax\n#define     __USAD8                 __builtin_arm_usad8\n#define     __USADA8                __builtin_arm_usada8\n#define     __SSAT16                __builtin_arm_ssat16\n#define     __USAT16                __builtin_arm_usat16\n#define     __UXTB16                __builtin_arm_uxtb16\n#define     __UXTAB16               __builtin_arm_uxtab16\n#define     __SXTB16                __builtin_arm_sxtb16\n#define     __SXTAB16               __builtin_arm_sxtab16\n#define     __SMUAD                 __builtin_arm_smuad\n#define     __SMUADX                __builtin_arm_smuadx\n#define     __SMLAD                 __builtin_arm_smlad\n#define     __SMLADX                __builtin_arm_smladx\n#define     __SMLALD                __builtin_arm_smlald\n#define     __SMLALDX               __builtin_arm_smlaldx\n#define     __SMUSD                 __builtin_arm_smusd\n#define     __SMUSDX                __builtin_arm_smusdx\n#define     __SMLSD                 __builtin_arm_smlsd\n#define     __SMLSDX                __builtin_arm_smlsdx\n#define     __SMLSLD                __builtin_arm_smlsld\n#define     __SMLSLDX               __builtin_arm_smlsldx\n#define     __SEL                   __builtin_arm_sel\n#define     __QADD                  __builtin_arm_qadd\n#define     __QSUB                  __builtin_arm_qsub\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n#define __SXTB16_RORn(ARG1, ARG2)        __SXTB16(__ROR(ARG1, ARG2))\n\n#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n  int32_t result;\n\n  __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/** @} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_TIARMCLANG_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/cmsis_version.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_version.h\n * @brief    CMSIS Core(M) Version definitions\n * @version  V5.0.5\n * @date     02. February 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CMSIS_VERSION_H\n#define __CMSIS_VERSION_H\n\n/*  CMSIS Version definitions */\n#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */\n#define __CM_CMSIS_VERSION_SUB   ( 6U)                                      /*!< [15:0]  CMSIS Core(M) sub version */\n#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \\\n                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h",
    "content": "/**************************************************************************//**\n * @file     core_armv81mml.h\n * @brief    CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File\n * @version  V1.5.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2018-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include                        /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header                   /* treat file as system include file */\n#elif defined ( __GNUC__ )\n  #pragma GCC diagnostic ignored \"-Wpedantic\"   /* disable pedantic warning due to unnamed structs/unions */\n#endif\n\n#ifndef __CORE_ARMV81MML_H_GENERIC\n#define __CORE_ARMV81MML_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMV81MML\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS ARMV81MML definitions */\n#define __ARMv81MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv81MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv81MML_CMSIS_VERSION       ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv81MML_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                      (81U)                                       /*!< Cortex-M Core */\n\n#if defined ( __CC_ARM )\n  #error Legacy Arm Compiler does not support Armv8.1-M target architecture.\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED       0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV81MML_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV81MML_H_DEPENDANT\n#define __CORE_ARMV81MML_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv81MML_REV\n    #define __ARMv81MML_REV               0x0000U\n    #warning \"__ARMv81MML_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #if __FPU_PRESENT != 0U\n    #ifndef __FPU_DP\n      #define __FPU_DP             0U\n      #warning \"__FPU_DP not defined in device header file; using default!\"\n    #endif\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ICACHE_PRESENT\n    #define __ICACHE_PRESENT          0U\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DCACHE_PRESENT\n    #define __DCACHE_PRESENT          0U\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __PMU_PRESENT\n    #define __PMU_PRESENT             0U\n    #warning \"__PMU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #if __PMU_PRESENT != 0U\n    #ifndef __PMU_NUM_EVENTCNT\n      #define __PMU_NUM_EVENTCNT      2U\n      #warning \"__PMU_NUM_EVENTCNT not defined in device header file; using default!\"\n    #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2)\n    #error \"__PMU_NUM_EVENTCNT is out of range in device header file!\" */\n    #endif\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group ARMv81MML */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED7[21U];\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */\n        uint32_t RESERVED3[69U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n  __IOM uint32_t RFSR;                   /*!< Offset: 0x204 (R/W)  RAS Fault Status Register */\n        uint32_t RESERVED4[14U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_IESB_Pos                  5U                                            /*!< SCB AIRCR: Implicit ESB Enable Position */\n#define SCB_AIRCR_IESB_Msk                 (1UL << SCB_AIRCR_IESB_Pos)                    /*!< SCB AIRCR: Implicit ESB Enable Mask */\n\n#define SCB_AIRCR_DIT_Pos                   4U                                            /*!< SCB AIRCR: Data Independent Timing Position */\n#define SCB_AIRCR_DIT_Msk                  (1UL << SCB_AIRCR_DIT_Pos)                     /*!< SCB AIRCR: Data Independent Timing Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_TRD_Pos                    20U                                            /*!< SCB CCR: TRD Position */\n#define SCB_CCR_TRD_Msk                    (1UL << SCB_CCR_TRD_Pos)                       /*!< SCB CCR: TRD Mask */\n\n#define SCB_CCR_LOB_Pos                    19U                                            /*!< SCB CCR: LOB Position */\n#define SCB_CCR_LOB_Msk                    (1UL << SCB_CCR_LOB_Pos)                       /*!< SCB CCR: LOB Mask */\n\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_PMU_Pos                    5U                                            /*!< SCB DFSR: PMU Position */\n#define SCB_DFSR_PMU_Msk                   (1UL << SCB_DFSR_PMU_Pos)                      /*!< SCB DFSR: PMU Mask */\n\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CP7_Pos                   7U                                            /*!< SCB NSACR: CP7 Position */\n#define SCB_NSACR_CP7_Msk                  (1UL << SCB_NSACR_CP7_Pos)                     /*!< SCB NSACR: CP7 Mask */\n\n#define SCB_NSACR_CP6_Pos                   6U                                            /*!< SCB NSACR: CP6 Position */\n#define SCB_NSACR_CP6_Msk                  (1UL << SCB_NSACR_CP6_Pos)                     /*!< SCB NSACR: CP6 Mask */\n\n#define SCB_NSACR_CP5_Pos                   5U                                            /*!< SCB NSACR: CP5 Position */\n#define SCB_NSACR_CP5_Msk                  (1UL << SCB_NSACR_CP5_Pos)                     /*!< SCB NSACR: CP5 Mask */\n\n#define SCB_NSACR_CP4_Pos                   4U                                            /*!< SCB NSACR: CP4 Position */\n#define SCB_NSACR_CP4_Msk                  (1UL << SCB_NSACR_CP4_Pos)                     /*!< SCB NSACR: CP4 Mask */\n\n#define SCB_NSACR_CP3_Pos                   3U                                            /*!< SCB NSACR: CP3 Position */\n#define SCB_NSACR_CP3_Msk                  (1UL << SCB_NSACR_CP3_Pos)                     /*!< SCB NSACR: CP3 Mask */\n\n#define SCB_NSACR_CP2_Pos                   2U                                            /*!< SCB NSACR: CP2 Position */\n#define SCB_NSACR_CP2_Msk                  (1UL << SCB_NSACR_CP2_Pos)                     /*!< SCB NSACR: CP2 Mask */\n\n#define SCB_NSACR_CP1_Pos                   1U                                            /*!< SCB NSACR: CP1 Position */\n#define SCB_NSACR_CP1_Msk                  (1UL << SCB_NSACR_CP1_Pos)                     /*!< SCB NSACR: CP1 Mask */\n\n#define SCB_NSACR_CP0_Pos                   0U                                            /*!< SCB NSACR: CP0 Position */\n#define SCB_NSACR_CP0_Msk                  (1UL /*<< SCB_NSACR_CP0_Pos*/)                 /*!< SCB NSACR: CP0 Mask */\n\n/* SCB Debug Feature Register 0 Definitions */\n#define SCB_ID_DFR_UDE_Pos                 28U                                            /*!< SCB ID_DFR: UDE Position */\n#define SCB_ID_DFR_UDE_Msk                 (0xFUL << SCB_ID_DFR_UDE_Pos)                  /*!< SCB ID_DFR: UDE Mask */\n\n#define SCB_ID_DFR_MProfDbg_Pos            20U                                            /*!< SCB ID_DFR: MProfDbg Position */\n#define SCB_ID_DFR_MProfDbg_Msk            (0xFUL << SCB_ID_DFR_MProfDbg_Pos)             /*!< SCB ID_DFR: MProfDbg Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB RAS Fault Status Register Definitions */\n#define SCB_RFSR_V_Pos                     31U                                            /*!< SCB RFSR: V Position */\n#define SCB_RFSR_V_Msk                     (1UL << SCB_RFSR_V_Pos)                        /*!< SCB RFSR: V Mask */\n\n#define SCB_RFSR_IS_Pos                    16U                                            /*!< SCB RFSR: IS Position */\n#define SCB_RFSR_IS_Msk                    (0x7FFFUL << SCB_RFSR_IS_Pos)                  /*!< SCB RFSR: IS Mask */\n\n#define SCB_RFSR_UET_Pos                    0U                                            /*!< SCB RFSR: UET Position */\n#define SCB_RFSR_UET_Msk                   (3UL /*<< SCB_RFSR_UET_Pos*/)                  /*!< SCB RFSR: UET Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[3U];\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  ITM Device Type Register */\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFmt_Pos                  0U                                         /*!< TPI FFCR: EnFmt Position */\n#define TPI_FFCR_EnFmt_Msk                 (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)           /*!< TPI FFCR: EnFmt Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_PMU     Performance Monitoring Unit (PMU)\n  \\brief    Type definitions for the Performance Monitoring Unit (PMU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Performance Monitoring Unit (PMU).\n */\ntypedef struct\n{\n  __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT];        /*!< Offset: 0x0 (R/W)    PMU Event Counter Registers */\n#if __PMU_NUM_EVENTCNT<31\n        uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];\n#endif\n  __IOM uint32_t CCNTR;                             /*!< Offset: 0x7C (R/W)   PMU Cycle Counter Register */\n        uint32_t RESERVED1[224];\n  __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT];       /*!< Offset: 0x400 (R/W)  PMU Event Type and Filter Registers */\n#if __PMU_NUM_EVENTCNT<31\n        uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];\n#endif\n  __IOM uint32_t CCFILTR;                           /*!< Offset: 0x47C (R/W)  PMU Cycle Counter Filter Register */\n        uint32_t RESERVED3[480];\n  __IOM uint32_t CNTENSET;                          /*!< Offset: 0xC00 (R/W)  PMU Count Enable Set Register */\n        uint32_t RESERVED4[7];\n  __IOM uint32_t CNTENCLR;                          /*!< Offset: 0xC20 (R/W)  PMU Count Enable Clear Register */\n        uint32_t RESERVED5[7];\n  __IOM uint32_t INTENSET;                          /*!< Offset: 0xC40 (R/W)  PMU Interrupt Enable Set Register */\n        uint32_t RESERVED6[7];\n  __IOM uint32_t INTENCLR;                          /*!< Offset: 0xC60 (R/W)  PMU Interrupt Enable Clear Register */\n        uint32_t RESERVED7[7];\n  __IOM uint32_t OVSCLR;                            /*!< Offset: 0xC80 (R/W)  PMU Overflow Flag Status Clear Register */\n        uint32_t RESERVED8[7];\n  __IOM uint32_t SWINC;                             /*!< Offset: 0xCA0 (R/W)  PMU Software Increment Register */\n        uint32_t RESERVED9[7];\n  __IOM uint32_t OVSSET;                            /*!< Offset: 0xCC0 (R/W)  PMU Overflow Flag Status Set Register */\n        uint32_t RESERVED10[79];\n  __IOM uint32_t TYPE;                              /*!< Offset: 0xE00 (R/W)  PMU Type Register */\n  __IOM uint32_t CTRL;                              /*!< Offset: 0xE04 (R/W)  PMU Control Register */\n        uint32_t RESERVED11[108];\n  __IOM uint32_t AUTHSTATUS;                        /*!< Offset: 0xFB8 (R/W)  PMU Authentication Status Register */\n  __IOM uint32_t DEVARCH;                           /*!< Offset: 0xFBC (R/W)  PMU Device Architecture Register */\n        uint32_t RESERVED12[3];\n  __IOM uint32_t DEVTYPE;                           /*!< Offset: 0xFCC (R/W)  PMU Device Type Register */\n  __IOM uint32_t PIDR4;                             /*!< Offset: 0xFD0 (R/W)  PMU Peripheral Identification Register 4 */\n        uint32_t RESERVED13[3];\n  __IOM uint32_t PIDR0;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 0 */\n  __IOM uint32_t PIDR1;                             /*!< Offset: 0xFE4 (R/W)  PMU Peripheral Identification Register 1 */\n  __IOM uint32_t PIDR2;                             /*!< Offset: 0xFE8 (R/W)  PMU Peripheral Identification Register 2 */\n  __IOM uint32_t PIDR3;                             /*!< Offset: 0xFEC (R/W)  PMU Peripheral Identification Register 3 */\n  __IOM uint32_t CIDR0;                             /*!< Offset: 0xFF0 (R/W)  PMU Component Identification Register 0 */\n  __IOM uint32_t CIDR1;                             /*!< Offset: 0xFF4 (R/W)  PMU Component Identification Register 1 */\n  __IOM uint32_t CIDR2;                             /*!< Offset: 0xFF8 (R/W)  PMU Component Identification Register 2 */\n  __IOM uint32_t CIDR3;                             /*!< Offset: 0xFFC (R/W)  PMU Component Identification Register 3 */\n} PMU_Type;\n\n/** \\brief PMU Event Counter Registers (0-30) Definitions  */\n\n#define PMU_EVCNTR_CNT_Pos                    0U                                           /*!< PMU EVCNTR: Counter Position */\n#define PMU_EVCNTR_CNT_Msk                   (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/)         /*!< PMU EVCNTR: Counter Mask */\n\n/** \\brief PMU Event Type and Filter Registers (0-30) Definitions  */\n\n#define PMU_EVTYPER_EVENTTOCNT_Pos            0U                                           /*!< PMU EVTYPER: Event to Count Position */\n#define PMU_EVTYPER_EVENTTOCNT_Msk           (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/)     /*!< PMU EVTYPER: Event to Count Mask */\n\n/** \\brief PMU Count Enable Set Register Definitions */\n\n#define PMU_CNTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */\n#define PMU_CNTENSET_CNT0_ENABLE_Msk         (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/)     /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT1_ENABLE_Pos          1U                                           /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */\n#define PMU_CNTENSET_CNT1_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT2_ENABLE_Pos          2U                                           /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */\n#define PMU_CNTENSET_CNT2_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT3_ENABLE_Pos          3U                                           /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */\n#define PMU_CNTENSET_CNT3_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT4_ENABLE_Pos          4U                                           /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */\n#define PMU_CNTENSET_CNT4_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT5_ENABLE_Pos          5U                                           /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */\n#define PMU_CNTENSET_CNT5_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT6_ENABLE_Pos          6U                                           /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */\n#define PMU_CNTENSET_CNT6_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT7_ENABLE_Pos          7U                                           /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */\n#define PMU_CNTENSET_CNT7_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT8_ENABLE_Pos          8U                                           /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */\n#define PMU_CNTENSET_CNT8_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT9_ENABLE_Pos          9U                                           /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */\n#define PMU_CNTENSET_CNT9_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT10_ENABLE_Pos         10U                                          /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */\n#define PMU_CNTENSET_CNT10_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT11_ENABLE_Pos         11U                                          /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */\n#define PMU_CNTENSET_CNT11_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT12_ENABLE_Pos         12U                                          /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */\n#define PMU_CNTENSET_CNT12_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT13_ENABLE_Pos         13U                                          /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */\n#define PMU_CNTENSET_CNT13_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT14_ENABLE_Pos         14U                                          /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */\n#define PMU_CNTENSET_CNT14_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT15_ENABLE_Pos         15U                                          /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */\n#define PMU_CNTENSET_CNT15_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT16_ENABLE_Pos         16U                                          /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */\n#define PMU_CNTENSET_CNT16_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT17_ENABLE_Pos         17U                                          /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */\n#define PMU_CNTENSET_CNT17_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT18_ENABLE_Pos         18U                                          /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */\n#define PMU_CNTENSET_CNT18_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT19_ENABLE_Pos         19U                                          /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */\n#define PMU_CNTENSET_CNT19_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT20_ENABLE_Pos         20U                                          /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */\n#define PMU_CNTENSET_CNT20_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT21_ENABLE_Pos         21U                                          /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */\n#define PMU_CNTENSET_CNT21_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT22_ENABLE_Pos         22U                                          /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */\n#define PMU_CNTENSET_CNT22_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT23_ENABLE_Pos         23U                                          /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */\n#define PMU_CNTENSET_CNT23_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT24_ENABLE_Pos         24U                                          /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */\n#define PMU_CNTENSET_CNT24_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT25_ENABLE_Pos         25U                                          /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */\n#define PMU_CNTENSET_CNT25_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT26_ENABLE_Pos         26U                                          /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */\n#define PMU_CNTENSET_CNT26_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT27_ENABLE_Pos         27U                                          /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */\n#define PMU_CNTENSET_CNT27_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT28_ENABLE_Pos         28U                                          /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */\n#define PMU_CNTENSET_CNT28_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT29_ENABLE_Pos         29U                                          /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */\n#define PMU_CNTENSET_CNT29_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT30_ENABLE_Pos         30U                                          /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */\n#define PMU_CNTENSET_CNT30_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */\n\n#define PMU_CNTENSET_CCNTR_ENABLE_Pos         31U                                          /*!< PMU CNTENSET: Cycle Counter Enable Set Position */\n#define PMU_CNTENSET_CCNTR_ENABLE_Msk        (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos)        /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */\n\n/** \\brief PMU Count Enable Clear Register Definitions */\n\n#define PMU_CNTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */\n#define PMU_CNTENCLR_CNT0_ENABLE_Msk         (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/)     /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT1_ENABLE_Pos          1U                                           /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */\n#define PMU_CNTENCLR_CNT1_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */\n\n#define PMU_CNTENCLR_CNT2_ENABLE_Pos          2U                                           /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */\n#define PMU_CNTENCLR_CNT2_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT3_ENABLE_Pos          3U                                           /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */\n#define PMU_CNTENCLR_CNT3_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT4_ENABLE_Pos          4U                                           /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */\n#define PMU_CNTENCLR_CNT4_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT5_ENABLE_Pos          5U                                           /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */\n#define PMU_CNTENCLR_CNT5_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT6_ENABLE_Pos          6U                                           /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */\n#define PMU_CNTENCLR_CNT6_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT7_ENABLE_Pos          7U                                           /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */\n#define PMU_CNTENCLR_CNT7_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT8_ENABLE_Pos          8U                                           /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */\n#define PMU_CNTENCLR_CNT8_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT9_ENABLE_Pos          9U                                           /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */\n#define PMU_CNTENCLR_CNT9_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT10_ENABLE_Pos         10U                                          /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */\n#define PMU_CNTENCLR_CNT10_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT11_ENABLE_Pos         11U                                          /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */\n#define PMU_CNTENCLR_CNT11_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT12_ENABLE_Pos         12U                                          /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */\n#define PMU_CNTENCLR_CNT12_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT13_ENABLE_Pos         13U                                          /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */\n#define PMU_CNTENCLR_CNT13_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT14_ENABLE_Pos         14U                                          /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */\n#define PMU_CNTENCLR_CNT14_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT15_ENABLE_Pos         15U                                          /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */\n#define PMU_CNTENCLR_CNT15_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT16_ENABLE_Pos         16U                                          /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */\n#define PMU_CNTENCLR_CNT16_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT17_ENABLE_Pos         17U                                          /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */\n#define PMU_CNTENCLR_CNT17_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT18_ENABLE_Pos         18U                                          /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */\n#define PMU_CNTENCLR_CNT18_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT19_ENABLE_Pos         19U                                          /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */\n#define PMU_CNTENCLR_CNT19_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT20_ENABLE_Pos         20U                                          /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */\n#define PMU_CNTENCLR_CNT20_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT21_ENABLE_Pos         21U                                          /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */\n#define PMU_CNTENCLR_CNT21_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT22_ENABLE_Pos         22U                                          /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */\n#define PMU_CNTENCLR_CNT22_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT23_ENABLE_Pos         23U                                          /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */\n#define PMU_CNTENCLR_CNT23_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT24_ENABLE_Pos         24U                                          /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */\n#define PMU_CNTENCLR_CNT24_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT25_ENABLE_Pos         25U                                          /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */\n#define PMU_CNTENCLR_CNT25_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT26_ENABLE_Pos         26U                                          /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */\n#define PMU_CNTENCLR_CNT26_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT27_ENABLE_Pos         27U                                          /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */\n#define PMU_CNTENCLR_CNT27_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT28_ENABLE_Pos         28U                                          /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */\n#define PMU_CNTENCLR_CNT28_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT29_ENABLE_Pos         29U                                          /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */\n#define PMU_CNTENCLR_CNT29_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT30_ENABLE_Pos         30U                                          /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */\n#define PMU_CNTENCLR_CNT30_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CCNTR_ENABLE_Pos         31U                                          /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */\n#define PMU_CNTENCLR_CCNTR_ENABLE_Msk        (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos)        /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */\n\n/** \\brief PMU Interrupt Enable Set Register Definitions */\n\n#define PMU_INTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT0_ENABLE_Msk         (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/)     /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT1_ENABLE_Pos          1U                                           /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT1_ENABLE_Msk         (1UL << PMU_INTENSET_CNT1_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT2_ENABLE_Pos          2U                                           /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT2_ENABLE_Msk         (1UL << PMU_INTENSET_CNT2_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT3_ENABLE_Pos          3U                                           /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT3_ENABLE_Msk         (1UL << PMU_INTENSET_CNT3_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT4_ENABLE_Pos          4U                                           /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT4_ENABLE_Msk         (1UL << PMU_INTENSET_CNT4_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT5_ENABLE_Pos          5U                                           /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT5_ENABLE_Msk         (1UL << PMU_INTENSET_CNT5_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT6_ENABLE_Pos          6U                                           /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT6_ENABLE_Msk         (1UL << PMU_INTENSET_CNT6_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT7_ENABLE_Pos          7U                                           /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT7_ENABLE_Msk         (1UL << PMU_INTENSET_CNT7_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT8_ENABLE_Pos          8U                                           /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT8_ENABLE_Msk         (1UL << PMU_INTENSET_CNT8_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT9_ENABLE_Pos          9U                                           /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT9_ENABLE_Msk         (1UL << PMU_INTENSET_CNT9_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT10_ENABLE_Pos         10U                                          /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT10_ENABLE_Msk        (1UL << PMU_INTENSET_CNT10_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT11_ENABLE_Pos         11U                                          /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT11_ENABLE_Msk        (1UL << PMU_INTENSET_CNT11_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT12_ENABLE_Pos         12U                                          /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT12_ENABLE_Msk        (1UL << PMU_INTENSET_CNT12_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT13_ENABLE_Pos         13U                                          /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT13_ENABLE_Msk        (1UL << PMU_INTENSET_CNT13_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT14_ENABLE_Pos         14U                                          /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT14_ENABLE_Msk        (1UL << PMU_INTENSET_CNT14_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT15_ENABLE_Pos         15U                                          /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT15_ENABLE_Msk        (1UL << PMU_INTENSET_CNT15_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT16_ENABLE_Pos         16U                                          /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT16_ENABLE_Msk        (1UL << PMU_INTENSET_CNT16_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT17_ENABLE_Pos         17U                                          /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT17_ENABLE_Msk        (1UL << PMU_INTENSET_CNT17_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT18_ENABLE_Pos         18U                                          /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT18_ENABLE_Msk        (1UL << PMU_INTENSET_CNT18_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT19_ENABLE_Pos         19U                                          /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT19_ENABLE_Msk        (1UL << PMU_INTENSET_CNT19_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT20_ENABLE_Pos         20U                                          /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT20_ENABLE_Msk        (1UL << PMU_INTENSET_CNT20_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT21_ENABLE_Pos         21U                                          /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT21_ENABLE_Msk        (1UL << PMU_INTENSET_CNT21_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT22_ENABLE_Pos         22U                                          /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT22_ENABLE_Msk        (1UL << PMU_INTENSET_CNT22_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT23_ENABLE_Pos         23U                                          /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT23_ENABLE_Msk        (1UL << PMU_INTENSET_CNT23_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT24_ENABLE_Pos         24U                                          /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT24_ENABLE_Msk        (1UL << PMU_INTENSET_CNT24_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT25_ENABLE_Pos         25U                                          /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT25_ENABLE_Msk        (1UL << PMU_INTENSET_CNT25_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT26_ENABLE_Pos         26U                                          /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT26_ENABLE_Msk        (1UL << PMU_INTENSET_CNT26_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT27_ENABLE_Pos         27U                                          /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT27_ENABLE_Msk        (1UL << PMU_INTENSET_CNT27_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT28_ENABLE_Pos         28U                                          /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT28_ENABLE_Msk        (1UL << PMU_INTENSET_CNT28_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT29_ENABLE_Pos         29U                                          /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT29_ENABLE_Msk        (1UL << PMU_INTENSET_CNT29_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT30_ENABLE_Pos         30U                                          /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT30_ENABLE_Msk        (1UL << PMU_INTENSET_CNT30_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CYCCNT_ENABLE_Pos        31U                                          /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */\n#define PMU_INTENSET_CCYCNT_ENABLE_Msk       (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos)       /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */\n\n/** \\brief PMU Interrupt Enable Clear Register Definitions */\n\n#define PMU_INTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT0_ENABLE_Msk         (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/)     /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT1_ENABLE_Pos          1U                                           /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT1_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */\n\n#define PMU_INTENCLR_CNT2_ENABLE_Pos          2U                                           /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT2_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT3_ENABLE_Pos          3U                                           /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT3_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT4_ENABLE_Pos          4U                                           /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT4_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT5_ENABLE_Pos          5U                                           /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT5_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT6_ENABLE_Pos          6U                                           /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT6_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT7_ENABLE_Pos          7U                                           /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT7_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT8_ENABLE_Pos          8U                                           /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT8_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT9_ENABLE_Pos          9U                                           /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT9_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT10_ENABLE_Pos         10U                                          /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT10_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT11_ENABLE_Pos         11U                                          /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT11_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT12_ENABLE_Pos         12U                                          /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT12_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT13_ENABLE_Pos         13U                                          /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT13_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT14_ENABLE_Pos         14U                                          /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT14_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT15_ENABLE_Pos         15U                                          /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT15_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT16_ENABLE_Pos         16U                                          /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT16_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT17_ENABLE_Pos         17U                                          /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT17_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT18_ENABLE_Pos         18U                                          /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT18_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT19_ENABLE_Pos         19U                                          /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT19_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT20_ENABLE_Pos         20U                                          /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT20_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT21_ENABLE_Pos         21U                                          /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT21_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT22_ENABLE_Pos         22U                                          /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT22_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT23_ENABLE_Pos         23U                                          /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT23_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT24_ENABLE_Pos         24U                                          /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT24_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT25_ENABLE_Pos         25U                                          /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT25_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT26_ENABLE_Pos         26U                                          /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT26_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT27_ENABLE_Pos         27U                                          /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT27_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT28_ENABLE_Pos         28U                                          /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT28_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT29_ENABLE_Pos         29U                                          /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT29_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT30_ENABLE_Pos         30U                                          /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT30_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CYCCNT_ENABLE_Pos        31U                                          /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CYCCNT_ENABLE_Msk       (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos)       /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */\n\n/** \\brief PMU Overflow Flag Status Set Register Definitions */\n\n#define PMU_OVSSET_CNT0_STATUS_Pos            0U                                           /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */\n#define PMU_OVSSET_CNT0_STATUS_Msk           (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/)       /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT1_STATUS_Pos            1U                                           /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */\n#define PMU_OVSSET_CNT1_STATUS_Msk           (1UL << PMU_OVSSET_CNT1_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT2_STATUS_Pos            2U                                           /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */\n#define PMU_OVSSET_CNT2_STATUS_Msk           (1UL << PMU_OVSSET_CNT2_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT3_STATUS_Pos            3U                                           /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */\n#define PMU_OVSSET_CNT3_STATUS_Msk           (1UL << PMU_OVSSET_CNT3_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT4_STATUS_Pos            4U                                           /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */\n#define PMU_OVSSET_CNT4_STATUS_Msk           (1UL << PMU_OVSSET_CNT4_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT5_STATUS_Pos            5U                                           /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */\n#define PMU_OVSSET_CNT5_STATUS_Msk           (1UL << PMU_OVSSET_CNT5_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT6_STATUS_Pos            6U                                           /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */\n#define PMU_OVSSET_CNT6_STATUS_Msk           (1UL << PMU_OVSSET_CNT6_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT7_STATUS_Pos            7U                                           /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */\n#define PMU_OVSSET_CNT7_STATUS_Msk           (1UL << PMU_OVSSET_CNT7_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT8_STATUS_Pos            8U                                           /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */\n#define PMU_OVSSET_CNT8_STATUS_Msk           (1UL << PMU_OVSSET_CNT8_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT9_STATUS_Pos            9U                                           /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */\n#define PMU_OVSSET_CNT9_STATUS_Msk           (1UL << PMU_OVSSET_CNT9_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT10_STATUS_Pos           10U                                          /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */\n#define PMU_OVSSET_CNT10_STATUS_Msk          (1UL << PMU_OVSSET_CNT10_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT11_STATUS_Pos           11U                                          /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */\n#define PMU_OVSSET_CNT11_STATUS_Msk          (1UL << PMU_OVSSET_CNT11_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT12_STATUS_Pos           12U                                          /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */\n#define PMU_OVSSET_CNT12_STATUS_Msk          (1UL << PMU_OVSSET_CNT12_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT13_STATUS_Pos           13U                                          /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */\n#define PMU_OVSSET_CNT13_STATUS_Msk          (1UL << PMU_OVSSET_CNT13_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT14_STATUS_Pos           14U                                          /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */\n#define PMU_OVSSET_CNT14_STATUS_Msk          (1UL << PMU_OVSSET_CNT14_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT15_STATUS_Pos           15U                                          /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */\n#define PMU_OVSSET_CNT15_STATUS_Msk          (1UL << PMU_OVSSET_CNT15_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT16_STATUS_Pos           16U                                          /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */\n#define PMU_OVSSET_CNT16_STATUS_Msk          (1UL << PMU_OVSSET_CNT16_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT17_STATUS_Pos           17U                                          /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */\n#define PMU_OVSSET_CNT17_STATUS_Msk          (1UL << PMU_OVSSET_CNT17_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT18_STATUS_Pos           18U                                          /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */\n#define PMU_OVSSET_CNT18_STATUS_Msk          (1UL << PMU_OVSSET_CNT18_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT19_STATUS_Pos           19U                                          /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */\n#define PMU_OVSSET_CNT19_STATUS_Msk          (1UL << PMU_OVSSET_CNT19_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT20_STATUS_Pos           20U                                          /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */\n#define PMU_OVSSET_CNT20_STATUS_Msk          (1UL << PMU_OVSSET_CNT20_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT21_STATUS_Pos           21U                                          /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */\n#define PMU_OVSSET_CNT21_STATUS_Msk          (1UL << PMU_OVSSET_CNT21_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT22_STATUS_Pos           22U                                          /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */\n#define PMU_OVSSET_CNT22_STATUS_Msk          (1UL << PMU_OVSSET_CNT22_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT23_STATUS_Pos           23U                                          /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */\n#define PMU_OVSSET_CNT23_STATUS_Msk          (1UL << PMU_OVSSET_CNT23_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT24_STATUS_Pos           24U                                          /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */\n#define PMU_OVSSET_CNT24_STATUS_Msk          (1UL << PMU_OVSSET_CNT24_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT25_STATUS_Pos           25U                                          /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */\n#define PMU_OVSSET_CNT25_STATUS_Msk          (1UL << PMU_OVSSET_CNT25_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT26_STATUS_Pos           26U                                          /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */\n#define PMU_OVSSET_CNT26_STATUS_Msk          (1UL << PMU_OVSSET_CNT26_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT27_STATUS_Pos           27U                                          /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */\n#define PMU_OVSSET_CNT27_STATUS_Msk          (1UL << PMU_OVSSET_CNT27_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT28_STATUS_Pos           28U                                          /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */\n#define PMU_OVSSET_CNT28_STATUS_Msk          (1UL << PMU_OVSSET_CNT28_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT29_STATUS_Pos           29U                                          /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */\n#define PMU_OVSSET_CNT29_STATUS_Msk          (1UL << PMU_OVSSET_CNT29_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT30_STATUS_Pos           30U                                          /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */\n#define PMU_OVSSET_CNT30_STATUS_Msk          (1UL << PMU_OVSSET_CNT30_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */\n\n#define PMU_OVSSET_CYCCNT_STATUS_Pos          31U                                          /*!< PMU OVSSET: Cycle Counter Overflow Set Position */\n#define PMU_OVSSET_CYCCNT_STATUS_Msk         (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos)         /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */\n\n/** \\brief PMU Overflow Flag Status Clear Register Definitions */\n\n#define PMU_OVSCLR_CNT0_STATUS_Pos            0U                                           /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */\n#define PMU_OVSCLR_CNT0_STATUS_Msk           (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/)       /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT1_STATUS_Pos            1U                                           /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */\n#define PMU_OVSCLR_CNT1_STATUS_Msk           (1UL << PMU_OVSCLR_CNT1_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */\n\n#define PMU_OVSCLR_CNT2_STATUS_Pos            2U                                           /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */\n#define PMU_OVSCLR_CNT2_STATUS_Msk           (1UL << PMU_OVSCLR_CNT2_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT3_STATUS_Pos            3U                                           /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */\n#define PMU_OVSCLR_CNT3_STATUS_Msk           (1UL << PMU_OVSCLR_CNT3_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT4_STATUS_Pos            4U                                           /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */\n#define PMU_OVSCLR_CNT4_STATUS_Msk           (1UL << PMU_OVSCLR_CNT4_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT5_STATUS_Pos            5U                                           /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */\n#define PMU_OVSCLR_CNT5_STATUS_Msk           (1UL << PMU_OVSCLR_CNT5_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT6_STATUS_Pos            6U                                           /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */\n#define PMU_OVSCLR_CNT6_STATUS_Msk           (1UL << PMU_OVSCLR_CNT6_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT7_STATUS_Pos            7U                                           /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */\n#define PMU_OVSCLR_CNT7_STATUS_Msk           (1UL << PMU_OVSCLR_CNT7_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT8_STATUS_Pos            8U                                           /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */\n#define PMU_OVSCLR_CNT8_STATUS_Msk           (1UL << PMU_OVSCLR_CNT8_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT9_STATUS_Pos            9U                                           /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */\n#define PMU_OVSCLR_CNT9_STATUS_Msk           (1UL << PMU_OVSCLR_CNT9_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT10_STATUS_Pos           10U                                          /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */\n#define PMU_OVSCLR_CNT10_STATUS_Msk          (1UL << PMU_OVSCLR_CNT10_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT11_STATUS_Pos           11U                                          /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */\n#define PMU_OVSCLR_CNT11_STATUS_Msk          (1UL << PMU_OVSCLR_CNT11_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT12_STATUS_Pos           12U                                          /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */\n#define PMU_OVSCLR_CNT12_STATUS_Msk          (1UL << PMU_OVSCLR_CNT12_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT13_STATUS_Pos           13U                                          /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */\n#define PMU_OVSCLR_CNT13_STATUS_Msk          (1UL << PMU_OVSCLR_CNT13_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT14_STATUS_Pos           14U                                          /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */\n#define PMU_OVSCLR_CNT14_STATUS_Msk          (1UL << PMU_OVSCLR_CNT14_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT15_STATUS_Pos           15U                                          /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */\n#define PMU_OVSCLR_CNT15_STATUS_Msk          (1UL << PMU_OVSCLR_CNT15_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT16_STATUS_Pos           16U                                          /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */\n#define PMU_OVSCLR_CNT16_STATUS_Msk          (1UL << PMU_OVSCLR_CNT16_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT17_STATUS_Pos           17U                                          /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */\n#define PMU_OVSCLR_CNT17_STATUS_Msk          (1UL << PMU_OVSCLR_CNT17_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT18_STATUS_Pos           18U                                          /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */\n#define PMU_OVSCLR_CNT18_STATUS_Msk          (1UL << PMU_OVSCLR_CNT18_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT19_STATUS_Pos           19U                                          /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */\n#define PMU_OVSCLR_CNT19_STATUS_Msk          (1UL << PMU_OVSCLR_CNT19_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT20_STATUS_Pos           20U                                          /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */\n#define PMU_OVSCLR_CNT20_STATUS_Msk          (1UL << PMU_OVSCLR_CNT20_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT21_STATUS_Pos           21U                                          /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */\n#define PMU_OVSCLR_CNT21_STATUS_Msk          (1UL << PMU_OVSCLR_CNT21_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT22_STATUS_Pos           22U                                          /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */\n#define PMU_OVSCLR_CNT22_STATUS_Msk          (1UL << PMU_OVSCLR_CNT22_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT23_STATUS_Pos           23U                                          /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */\n#define PMU_OVSCLR_CNT23_STATUS_Msk          (1UL << PMU_OVSCLR_CNT23_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT24_STATUS_Pos           24U                                          /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */\n#define PMU_OVSCLR_CNT24_STATUS_Msk          (1UL << PMU_OVSCLR_CNT24_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT25_STATUS_Pos           25U                                          /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */\n#define PMU_OVSCLR_CNT25_STATUS_Msk          (1UL << PMU_OVSCLR_CNT25_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT26_STATUS_Pos           26U                                          /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */\n#define PMU_OVSCLR_CNT26_STATUS_Msk          (1UL << PMU_OVSCLR_CNT26_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT27_STATUS_Pos           27U                                          /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */\n#define PMU_OVSCLR_CNT27_STATUS_Msk          (1UL << PMU_OVSCLR_CNT27_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT28_STATUS_Pos           28U                                          /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */\n#define PMU_OVSCLR_CNT28_STATUS_Msk          (1UL << PMU_OVSCLR_CNT28_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT29_STATUS_Pos           29U                                          /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */\n#define PMU_OVSCLR_CNT29_STATUS_Msk          (1UL << PMU_OVSCLR_CNT29_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT30_STATUS_Pos           30U                                          /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */\n#define PMU_OVSCLR_CNT30_STATUS_Msk          (1UL << PMU_OVSCLR_CNT30_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CYCCNT_STATUS_Pos          31U                                          /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */\n#define PMU_OVSCLR_CYCCNT_STATUS_Msk         (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos)         /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */\n\n/** \\brief PMU Software Increment Counter */\n\n#define PMU_SWINC_CNT0_Pos                    0U                                           /*!< PMU SWINC: Event Counter 0 Software Increment Position */\n#define PMU_SWINC_CNT0_Msk                   (1UL /*<< PMU_SWINC_CNT0_Pos */)              /*!< PMU SWINC: Event Counter 0 Software Increment Mask */\n\n#define PMU_SWINC_CNT1_Pos                    1U                                           /*!< PMU SWINC: Event Counter 1 Software Increment Position */\n#define PMU_SWINC_CNT1_Msk                   (1UL << PMU_SWINC_CNT1_Pos)                   /*!< PMU SWINC: Event Counter 1 Software Increment Mask */\n\n#define PMU_SWINC_CNT2_Pos                    2U                                           /*!< PMU SWINC: Event Counter 2 Software Increment Position */\n#define PMU_SWINC_CNT2_Msk                   (1UL << PMU_SWINC_CNT2_Pos)                   /*!< PMU SWINC: Event Counter 2 Software Increment Mask */\n\n#define PMU_SWINC_CNT3_Pos                    3U                                           /*!< PMU SWINC: Event Counter 3 Software Increment Position */\n#define PMU_SWINC_CNT3_Msk                   (1UL << PMU_SWINC_CNT3_Pos)                   /*!< PMU SWINC: Event Counter 3 Software Increment Mask */\n\n#define PMU_SWINC_CNT4_Pos                    4U                                           /*!< PMU SWINC: Event Counter 4 Software Increment Position */\n#define PMU_SWINC_CNT4_Msk                   (1UL << PMU_SWINC_CNT4_Pos)                   /*!< PMU SWINC: Event Counter 4 Software Increment Mask */\n\n#define PMU_SWINC_CNT5_Pos                    5U                                           /*!< PMU SWINC: Event Counter 5 Software Increment Position */\n#define PMU_SWINC_CNT5_Msk                   (1UL << PMU_SWINC_CNT5_Pos)                   /*!< PMU SWINC: Event Counter 5 Software Increment Mask */\n\n#define PMU_SWINC_CNT6_Pos                    6U                                           /*!< PMU SWINC: Event Counter 6 Software Increment Position */\n#define PMU_SWINC_CNT6_Msk                   (1UL << PMU_SWINC_CNT6_Pos)                   /*!< PMU SWINC: Event Counter 6 Software Increment Mask */\n\n#define PMU_SWINC_CNT7_Pos                    7U                                           /*!< PMU SWINC: Event Counter 7 Software Increment Position */\n#define PMU_SWINC_CNT7_Msk                   (1UL << PMU_SWINC_CNT7_Pos)                   /*!< PMU SWINC: Event Counter 7 Software Increment Mask */\n\n#define PMU_SWINC_CNT8_Pos                    8U                                           /*!< PMU SWINC: Event Counter 8 Software Increment Position */\n#define PMU_SWINC_CNT8_Msk                   (1UL << PMU_SWINC_CNT8_Pos)                   /*!< PMU SWINC: Event Counter 8 Software Increment Mask */\n\n#define PMU_SWINC_CNT9_Pos                    9U                                           /*!< PMU SWINC: Event Counter 9 Software Increment Position */\n#define PMU_SWINC_CNT9_Msk                   (1UL << PMU_SWINC_CNT9_Pos)                   /*!< PMU SWINC: Event Counter 9 Software Increment Mask */\n\n#define PMU_SWINC_CNT10_Pos                   10U                                          /*!< PMU SWINC: Event Counter 10 Software Increment Position */\n#define PMU_SWINC_CNT10_Msk                  (1UL << PMU_SWINC_CNT10_Pos)                  /*!< PMU SWINC: Event Counter 10 Software Increment Mask */\n\n#define PMU_SWINC_CNT11_Pos                   11U                                          /*!< PMU SWINC: Event Counter 11 Software Increment Position */\n#define PMU_SWINC_CNT11_Msk                  (1UL << PMU_SWINC_CNT11_Pos)                  /*!< PMU SWINC: Event Counter 11 Software Increment Mask */\n\n#define PMU_SWINC_CNT12_Pos                   12U                                          /*!< PMU SWINC: Event Counter 12 Software Increment Position */\n#define PMU_SWINC_CNT12_Msk                  (1UL << PMU_SWINC_CNT12_Pos)                  /*!< PMU SWINC: Event Counter 12 Software Increment Mask */\n\n#define PMU_SWINC_CNT13_Pos                   13U                                          /*!< PMU SWINC: Event Counter 13 Software Increment Position */\n#define PMU_SWINC_CNT13_Msk                  (1UL << PMU_SWINC_CNT13_Pos)                  /*!< PMU SWINC: Event Counter 13 Software Increment Mask */\n\n#define PMU_SWINC_CNT14_Pos                   14U                                          /*!< PMU SWINC: Event Counter 14 Software Increment Position */\n#define PMU_SWINC_CNT14_Msk                  (1UL << PMU_SWINC_CNT14_Pos)                  /*!< PMU SWINC: Event Counter 14 Software Increment Mask */\n\n#define PMU_SWINC_CNT15_Pos                   15U                                          /*!< PMU SWINC: Event Counter 15 Software Increment Position */\n#define PMU_SWINC_CNT15_Msk                  (1UL << PMU_SWINC_CNT15_Pos)                  /*!< PMU SWINC: Event Counter 15 Software Increment Mask */\n\n#define PMU_SWINC_CNT16_Pos                   16U                                          /*!< PMU SWINC: Event Counter 16 Software Increment Position */\n#define PMU_SWINC_CNT16_Msk                  (1UL << PMU_SWINC_CNT16_Pos)                  /*!< PMU SWINC: Event Counter 16 Software Increment Mask */\n\n#define PMU_SWINC_CNT17_Pos                   17U                                          /*!< PMU SWINC: Event Counter 17 Software Increment Position */\n#define PMU_SWINC_CNT17_Msk                  (1UL << PMU_SWINC_CNT17_Pos)                  /*!< PMU SWINC: Event Counter 17 Software Increment Mask */\n\n#define PMU_SWINC_CNT18_Pos                   18U                                          /*!< PMU SWINC: Event Counter 18 Software Increment Position */\n#define PMU_SWINC_CNT18_Msk                  (1UL << PMU_SWINC_CNT18_Pos)                  /*!< PMU SWINC: Event Counter 18 Software Increment Mask */\n\n#define PMU_SWINC_CNT19_Pos                   19U                                          /*!< PMU SWINC: Event Counter 19 Software Increment Position */\n#define PMU_SWINC_CNT19_Msk                  (1UL << PMU_SWINC_CNT19_Pos)                  /*!< PMU SWINC: Event Counter 19 Software Increment Mask */\n\n#define PMU_SWINC_CNT20_Pos                   20U                                          /*!< PMU SWINC: Event Counter 20 Software Increment Position */\n#define PMU_SWINC_CNT20_Msk                  (1UL << PMU_SWINC_CNT20_Pos)                  /*!< PMU SWINC: Event Counter 20 Software Increment Mask */\n\n#define PMU_SWINC_CNT21_Pos                   21U                                          /*!< PMU SWINC: Event Counter 21 Software Increment Position */\n#define PMU_SWINC_CNT21_Msk                  (1UL << PMU_SWINC_CNT21_Pos)                  /*!< PMU SWINC: Event Counter 21 Software Increment Mask */\n\n#define PMU_SWINC_CNT22_Pos                   22U                                          /*!< PMU SWINC: Event Counter 22 Software Increment Position */\n#define PMU_SWINC_CNT22_Msk                  (1UL << PMU_SWINC_CNT22_Pos)                  /*!< PMU SWINC: Event Counter 22 Software Increment Mask */\n\n#define PMU_SWINC_CNT23_Pos                   23U                                          /*!< PMU SWINC: Event Counter 23 Software Increment Position */\n#define PMU_SWINC_CNT23_Msk                  (1UL << PMU_SWINC_CNT23_Pos)                  /*!< PMU SWINC: Event Counter 23 Software Increment Mask */\n\n#define PMU_SWINC_CNT24_Pos                   24U                                          /*!< PMU SWINC: Event Counter 24 Software Increment Position */\n#define PMU_SWINC_CNT24_Msk                  (1UL << PMU_SWINC_CNT24_Pos)                  /*!< PMU SWINC: Event Counter 24 Software Increment Mask */\n\n#define PMU_SWINC_CNT25_Pos                   25U                                          /*!< PMU SWINC: Event Counter 25 Software Increment Position */\n#define PMU_SWINC_CNT25_Msk                  (1UL << PMU_SWINC_CNT25_Pos)                  /*!< PMU SWINC: Event Counter 25 Software Increment Mask */\n\n#define PMU_SWINC_CNT26_Pos                   26U                                          /*!< PMU SWINC: Event Counter 26 Software Increment Position */\n#define PMU_SWINC_CNT26_Msk                  (1UL << PMU_SWINC_CNT26_Pos)                  /*!< PMU SWINC: Event Counter 26 Software Increment Mask */\n\n#define PMU_SWINC_CNT27_Pos                   27U                                          /*!< PMU SWINC: Event Counter 27 Software Increment Position */\n#define PMU_SWINC_CNT27_Msk                  (1UL << PMU_SWINC_CNT27_Pos)                  /*!< PMU SWINC: Event Counter 27 Software Increment Mask */\n\n#define PMU_SWINC_CNT28_Pos                   28U                                          /*!< PMU SWINC: Event Counter 28 Software Increment Position */\n#define PMU_SWINC_CNT28_Msk                  (1UL << PMU_SWINC_CNT28_Pos)                  /*!< PMU SWINC: Event Counter 28 Software Increment Mask */\n\n#define PMU_SWINC_CNT29_Pos                   29U                                          /*!< PMU SWINC: Event Counter 29 Software Increment Position */\n#define PMU_SWINC_CNT29_Msk                  (1UL << PMU_SWINC_CNT29_Pos)                  /*!< PMU SWINC: Event Counter 29 Software Increment Mask */\n\n#define PMU_SWINC_CNT30_Pos                   30U                                          /*!< PMU SWINC: Event Counter 30 Software Increment Position */\n#define PMU_SWINC_CNT30_Msk                  (1UL << PMU_SWINC_CNT30_Pos)                  /*!< PMU SWINC: Event Counter 30 Software Increment Mask */\n\n/** \\brief PMU Control Register Definitions */\n\n#define PMU_CTRL_ENABLE_Pos                   0U                                           /*!< PMU CTRL: ENABLE Position */\n#define PMU_CTRL_ENABLE_Msk                  (1UL /*<< PMU_CTRL_ENABLE_Pos*/)              /*!< PMU CTRL: ENABLE Mask */\n\n#define PMU_CTRL_EVENTCNT_RESET_Pos           1U                                           /*!< PMU CTRL: Event Counter Reset Position */\n#define PMU_CTRL_EVENTCNT_RESET_Msk          (1UL << PMU_CTRL_EVENTCNT_RESET_Pos)          /*!< PMU CTRL: Event Counter Reset Mask */\n\n#define PMU_CTRL_CYCCNT_RESET_Pos             2U                                           /*!< PMU CTRL: Cycle Counter Reset Position */\n#define PMU_CTRL_CYCCNT_RESET_Msk            (1UL << PMU_CTRL_CYCCNT_RESET_Pos)            /*!< PMU CTRL: Cycle Counter Reset Mask */\n\n#define PMU_CTRL_CYCCNT_DISABLE_Pos           5U                                           /*!< PMU CTRL: Disable Cycle Counter Position */\n#define PMU_CTRL_CYCCNT_DISABLE_Msk          (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos)          /*!< PMU CTRL: Disable Cycle Counter Mask */\n\n#define PMU_CTRL_FRZ_ON_OV_Pos                9U                                           /*!< PMU CTRL: Freeze-on-overflow Position */\n#define PMU_CTRL_FRZ_ON_OV_Msk               (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos)         /*!< PMU CTRL: Freeze-on-overflow Mask */\n\n#define PMU_CTRL_TRACE_ON_OV_Pos              11U                                          /*!< PMU CTRL: Trace-on-overflow Position */\n#define PMU_CTRL_TRACE_ON_OV_Msk             (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos)       /*!< PMU CTRL: Trace-on-overflow Mask */\n\n/** \\brief PMU Type Register Definitions */\n\n#define PMU_TYPE_NUM_CNTS_Pos                 0U                                           /*!< PMU TYPE: Number of Counters Position */\n#define PMU_TYPE_NUM_CNTS_Msk                (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/)         /*!< PMU TYPE: Number of Counters Mask */\n\n#define PMU_TYPE_SIZE_CNTS_Pos                8U                                           /*!< PMU TYPE: Size of Counters Position */\n#define PMU_TYPE_SIZE_CNTS_Msk               (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos)            /*!< PMU TYPE: Size of Counters Mask */\n\n#define PMU_TYPE_CYCCNT_PRESENT_Pos           14U                                          /*!< PMU TYPE: Cycle Counter Present Position */\n#define PMU_TYPE_CYCCNT_PRESENT_Msk          (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos)          /*!< PMU TYPE: Cycle Counter Present Mask */\n\n#define PMU_TYPE_FRZ_OV_SUPPORT_Pos           21U                                          /*!< PMU TYPE: Freeze-on-overflow Support Position */\n#define PMU_TYPE_FRZ_OV_SUPPORT_Msk          (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)          /*!< PMU TYPE: Freeze-on-overflow Support Mask */\n\n#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos      23U                                          /*!< PMU TYPE: Trace-on-overflow Support Position */\n#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk     (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)          /*!< PMU TYPE: Trace-on-overflow Support Mask */\n\n/** \\brief PMU Authentication Status Register Definitions */\n\n#define PMU_AUTHSTATUS_NSID_Pos               0U                                           /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */\n#define PMU_AUTHSTATUS_NSID_Msk              (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/)        /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_NSNID_Pos              2U                                           /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_NSNID_Msk             (0x3UL << PMU_AUTHSTATUS_NSNID_Pos)           /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SID_Pos                4U                                           /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */\n#define PMU_AUTHSTATUS_SID_Msk               (0x3UL << PMU_AUTHSTATUS_SID_Pos)             /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SNID_Pos               6U                                           /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_SNID_Msk              (0x3UL << PMU_AUTHSTATUS_SNID_Pos)            /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_NSUID_Pos              16U                                          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */\n#define PMU_AUTHSTATUS_NSUID_Msk             (0x3UL << PMU_AUTHSTATUS_NSUID_Pos)           /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_NSUNID_Pos             18U                                          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_NSUNID_Msk            (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos)          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SUID_Pos               20U                                          /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */\n#define PMU_AUTHSTATUS_SUID_Msk              (0x3UL << PMU_AUTHSTATUS_SUID_Pos)            /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SUNID_Pos              22U                                          /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_SUNID_Msk             (0x3UL << PMU_AUTHSTATUS_SUNID_Pos)           /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */\n\n/*@} end of group CMSIS_PMU */\n#endif\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_PXN_Pos                    4U                                            /*!< MPU RLAR: PXN Position */\n#define MPU_RLAR_PXN_Msk                   (1UL << MPU_RLAR_PXN_Pos)                      /*!< MPU RLAR: PXN Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (7UL << MPU_RLAR_AttrIndx_Pos)                 /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n#define FPU_FPDSCR_FZ16_Pos                19U                                            /*!< FPDSCR: FZ16 bit Position */\n#define FPU_FPDSCR_FZ16_Msk                (1UL << FPU_FPDSCR_FZ16_Pos)                   /*!< FPDSCR: FZ16 bit Mask */\n\n#define FPU_FPDSCR_LTPSIZE_Pos             16U                                            /*!< FPDSCR: LTPSIZE bit Position */\n#define FPU_FPDSCR_LTPSIZE_Msk             (7UL << FPU_FPDSCR_LTPSIZE_Pos)                /*!< FPDSCR: LTPSIZE bit Mask */\n\n/* Media and VFP Feature Register 0 Definitions */\n#define FPU_MVFR0_FPRound_Pos              28U                                            /*!< MVFR0: FPRound bits Position */\n#define FPU_MVFR0_FPRound_Msk              (0xFUL << FPU_MVFR0_FPRound_Pos)               /*!< MVFR0: FPRound bits Mask */\n\n#define FPU_MVFR0_FPSqrt_Pos               20U                                            /*!< MVFR0: FPSqrt bits Position */\n#define FPU_MVFR0_FPSqrt_Msk               (0xFUL << FPU_MVFR0_FPSqrt_Pos)                 /*!< MVFR0: FPSqrt bits Mask */\n\n#define FPU_MVFR0_FPDivide_Pos             16U                                            /*!< MVFR0: FPDivide bits Position */\n#define FPU_MVFR0_FPDivide_Msk             (0xFUL << FPU_MVFR0_FPDivide_Pos)              /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FPDP_Pos                  8U                                            /*!< MVFR0: FPDP bits Position */\n#define FPU_MVFR0_FPDP_Msk                 (0xFUL << FPU_MVFR0_FPDP_Pos)                  /*!< MVFR0: FPDP bits Mask */\n\n#define FPU_MVFR0_FPSP_Pos                  4U                                            /*!< MVFR0: FPSP bits Position */\n#define FPU_MVFR0_FPSP_Msk                 (0xFUL << FPU_MVFR0_FPSP_Pos)                  /*!< MVFR0: FPSP bits Mask */\n\n#define FPU_MVFR0_SIMDReg_Pos               0U                                            /*!< MVFR0: SIMDReg bits Position */\n#define FPU_MVFR0_SIMDReg_Msk              (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)           /*!< MVFR0: SIMDReg bits Mask */\n\n/* Media and VFP Feature Register 1 Definitions */\n#define FPU_MVFR1_FMAC_Pos                 28U                                            /*!< MVFR1: FMAC bits Position */\n#define FPU_MVFR1_FMAC_Msk                 (0xFUL << FPU_MVFR1_FMAC_Pos)                  /*!< MVFR1: FMAC bits Mask */\n\n#define FPU_MVFR1_FPHP_Pos                 24U                                            /*!< MVFR1: FPHP bits Position */\n#define FPU_MVFR1_FPHP_Msk                 (0xFUL << FPU_MVFR1_FPHP_Pos)                  /*!< MVFR1: FPHP bits Mask */\n\n#define FPU_MVFR1_FP16_Pos                 20U                                            /*!< MVFR1: FP16 bits Position */\n#define FPU_MVFR1_FP16_Msk                 (0xFUL << FPU_MVFR1_FP16_Pos)                  /*!< MVFR1: FP16 bits Mask */\n\n#define FPU_MVFR1_MVE_Pos                   8U                                            /*!< MVFR1: MVE bits Position */\n#define FPU_MVFR1_MVE_Msk                  (0xFUL << FPU_MVFR1_MVE_Pos)                   /*!< MVFR1: MVE bits Mask */\n\n#define FPU_MVFR1_FPDNaN_Pos                4U                                            /*!< MVFR1: FPDNaN bits Position */\n#define FPU_MVFR1_FPDNaN_Msk               (0xFUL << FPU_MVFR1_FPDNaN_Pos)                /*!< MVFR1: FPDNaN bits Mask */\n\n#define FPU_MVFR1_FPFtZ_Pos                 0U                                            /*!< MVFR1: FPFtZ bits Position */\n#define FPU_MVFR1_FPFtZ_Msk                (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)             /*!< MVFR1: FPFtZ bits Mask */\n\n/* Media and VFP Feature Register 2 Definitions */\n#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */\n#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  \\deprecated Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n  __OM  uint32_t DSCEMCR;                /*!< Offset: 0x010 ( /W)  Debug Set Clear Exception and Monitor Control Register */\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \\deprecated CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \\deprecated CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_FPD_Pos          23U                                            /*!< \\deprecated CoreDebug DHCSR: S_FPD Position */\n#define CoreDebug_DHCSR_S_FPD_Msk          (1UL << CoreDebug_DHCSR_S_FPD_Pos)             /*!< \\deprecated CoreDebug DHCSR: S_FPD Mask */\n\n#define CoreDebug_DHCSR_S_SUIDE_Pos        22U                                            /*!< \\deprecated CoreDebug DHCSR: S_SUIDE Position */\n#define CoreDebug_DHCSR_S_SUIDE_Msk        (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SUIDE Mask */\n\n#define CoreDebug_DHCSR_S_NSUIDE_Pos       21U                                            /*!< \\deprecated CoreDebug DHCSR: S_NSUIDE Position */\n#define CoreDebug_DHCSR_S_NSUIDE_Msk       (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_NSUIDE Mask */\n\n#define CoreDebug_DHCSR_S_SDE_Pos          20U                                            /*!< \\deprecated CoreDebug DHCSR: S_SDE Position */\n#define CoreDebug_DHCSR_S_SDE_Msk          (1UL << CoreDebug_DHCSR_S_SDE_Pos)             /*!< \\deprecated CoreDebug DHCSR: S_SDE Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \\deprecated CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_PMOV_Pos          6U                                            /*!< \\deprecated CoreDebug DHCSR: C_PMOV Position */\n#define CoreDebug_DHCSR_C_PMOV_Msk         (1UL << CoreDebug_DHCSR_C_PMOV_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_PMOV Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \\deprecated CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \\deprecated CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \\deprecated CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \\deprecated CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \\deprecated CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \\deprecated CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< \\deprecated CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< \\deprecated CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< \\deprecated CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< \\deprecated CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< \\deprecated CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< \\deprecated CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< \\deprecated CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< \\deprecated CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Set Clear Exception and Monitor Control Register Definitions */\n#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos  19U                                            /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */\n#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk  (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)     /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */\n\n#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U                                            /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */\n#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)    /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */\n\n#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U                                            /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */\n#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk  (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)     /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */\n\n#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos  1U                                            /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */\n#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)    /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_UIDEN_Pos      10U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: UIDEN, Position */\n#define CoreDebug_DAUTHCTRL_UIDEN_Msk      (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)         /*!< \\deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos     9U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */\n#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk    (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)       /*!< \\deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_FSDMA_Pos       8U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: FSDMA, Position */\n#define CoreDebug_DAUTHCTRL_FSDMA_Msk      (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)         /*!< \\deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \\deprecated CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \\deprecated CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DCB       Debug Control Block\n  \\brief    Type definitions for the Debug Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Control Block Registers (DCB).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n  __OM  uint32_t DSCEMCR;                /*!< Offset: 0x010 ( /W)  Debug Set Clear Exception and Monitor Control Register */\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} DCB_Type;\n\n/* DHCSR, Debug Halting Control and Status Register Definitions */\n#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */\n#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */\n\n#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */\n#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */\n\n#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */\n#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */\n\n#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */\n#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */\n\n#define DCB_DHCSR_S_FPD_Pos                23U                                            /*!< DCB DHCSR: Floating-point registers Debuggable Position */\n#define DCB_DHCSR_S_FPD_Msk                (0x1UL << DCB_DHCSR_S_FPD_Pos)                 /*!< DCB DHCSR: Floating-point registers Debuggable Mask */\n\n#define DCB_DHCSR_S_SUIDE_Pos              22U                                            /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */\n#define DCB_DHCSR_S_SUIDE_Msk              (0x1UL << DCB_DHCSR_S_SUIDE_Pos)               /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */\n\n#define DCB_DHCSR_S_NSUIDE_Pos             21U                                            /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */\n#define DCB_DHCSR_S_NSUIDE_Msk             (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)              /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */\n\n#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */\n#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */\n\n#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */\n#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */\n\n#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */\n#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */\n\n#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */\n#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */\n\n#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */\n#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */\n\n#define DCB_DHCSR_C_PMOV_Pos                6U                                            /*!< DCB DHCSR: Halt on PMU overflow control Position */\n#define DCB_DHCSR_C_PMOV_Msk               (0x1UL << DCB_DHCSR_C_PMOV_Pos)                /*!< DCB DHCSR: Halt on PMU overflow control Mask */\n\n#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */\n#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */\n\n#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */\n#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */\n\n#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */\n#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */\n\n#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */\n#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */\n\n#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */\n#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */\n\n/* DCRSR, Debug Core Register Select Register Definitions */\n#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */\n#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */\n\n#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */\n#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */\n\n/* DCRDR, Debug Core Register Data Register Definitions */\n#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */\n#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */\n\n/* DEMCR, Debug Exception and Monitor Control Register Definitions */\n#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */\n#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */\n\n#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */\n#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */\n\n#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */\n#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */\n\n#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */\n#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */\n\n#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */\n#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */\n\n#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */\n#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */\n\n#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */\n#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */\n\n#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */\n#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */\n\n#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */\n#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */\n\n#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */\n#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */\n\n#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */\n#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */\n\n#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */\n#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */\n\n#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */\n#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */\n\n#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */\n#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */\n\n#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */\n#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */\n\n#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */\n#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */\n\n#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */\n#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */\n\n/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */\n#define DCB_DSCEMCR_CLR_MON_REQ_Pos        19U                                            /*!< DCB DSCEMCR: Clear monitor request Position */\n#define DCB_DSCEMCR_CLR_MON_REQ_Msk        (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)         /*!< DCB DSCEMCR: Clear monitor request Mask */\n\n#define DCB_DSCEMCR_CLR_MON_PEND_Pos       17U                                            /*!< DCB DSCEMCR: Clear monitor pend Position */\n#define DCB_DSCEMCR_CLR_MON_PEND_Msk       (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)        /*!< DCB DSCEMCR: Clear monitor pend Mask */\n\n#define DCB_DSCEMCR_SET_MON_REQ_Pos         3U                                            /*!< DCB DSCEMCR: Set monitor request Position */\n#define DCB_DSCEMCR_SET_MON_REQ_Msk        (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)         /*!< DCB DSCEMCR: Set monitor request Mask */\n\n#define DCB_DSCEMCR_SET_MON_PEND_Pos        1U                                            /*!< DCB DSCEMCR: Set monitor pend Position */\n#define DCB_DSCEMCR_SET_MON_PEND_Msk       (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)        /*!< DCB DSCEMCR: Set monitor pend Mask */\n\n/* DAUTHCTRL, Debug Authentication Control Register Definitions */\n#define DCB_DAUTHCTRL_UIDEN_Pos            10U                                            /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */\n#define DCB_DAUTHCTRL_UIDEN_Msk            (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)             /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */\n\n#define DCB_DAUTHCTRL_UIDAPEN_Pos           9U                                            /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */\n#define DCB_DAUTHCTRL_UIDAPEN_Msk          (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)           /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */\n\n#define DCB_DAUTHCTRL_FSDMA_Pos             8U                                            /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */\n#define DCB_DAUTHCTRL_FSDMA_Msk            (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)             /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */\n\n#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */\n\n#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */\n\n/* DSCSR, Debug Security Control and Status Register Definitions */\n#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */\n#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */\n\n#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */\n#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */\n\n#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */\n#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */\n\n#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */\n#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */\n\n/*@} end of group CMSIS_DCB */\n\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DIB       Debug Identification Block\n  \\brief    Type definitions for the Debug Identification Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Identification Block Registers (DIB).\n */\ntypedef struct\n{\n  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */\n  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */\n  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */\n  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */\n  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */\n} DIB_Type;\n\n/* DLAR, SCS Software Lock Access Register Definitions */\n#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */\n#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */\n\n/* DLSR, SCS Software Lock Status Register Definitions */\n#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */\n#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */\n\n#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */\n#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */\n\n#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */\n#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */\n\n/* DAUTHSTATUS, Debug Authentication Status Register Definitions */\n#define DIB_DAUTHSTATUS_SUNID_Pos          22U                                            /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */\n#define DIB_DAUTHSTATUS_SUNID_Msk          (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )          /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */\n\n#define DIB_DAUTHSTATUS_SUID_Pos           20U                                            /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */\n#define DIB_DAUTHSTATUS_SUID_Msk           (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )           /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */\n\n#define DIB_DAUTHSTATUS_NSUNID_Pos         18U                                            /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */\n#define DIB_DAUTHSTATUS_NSUNID_Msk         (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )         /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */\n\n#define DIB_DAUTHSTATUS_NSUID_Pos          16U                                            /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */\n#define DIB_DAUTHSTATUS_NSUID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */\n\n#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */\n\n/* DDEVARCH, SCS Device Architecture Register Definitions */\n#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */\n#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */\n\n#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */\n#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */\n\n#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */\n#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */\n\n#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */\n#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */\n\n#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */\n#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */\n\n/* DDEVTYPE, SCS Device Type Register Definitions */\n#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */\n#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */\n\n#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */\n#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */\n\n\n/*@} end of group CMSIS_DIB */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \\deprecated Core Debug Base Address */\n  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */\n  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \\deprecated Core Debug configuration struct */\n  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */\n  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)\n    #define PMU_BASE          (0xE0003000UL)                             /*!< PMU Base Address */\n    #define PMU               ((PMU_Type       *)     PMU_BASE         ) /*!< PMU configuration struct */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \\deprecated Core Debug Base Address           (non-secure address space) */\n  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */\n  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \\deprecated Core Debug configuration struct   (non-secure address space) */\n  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */\n  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */\n/*@} */\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)                      );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  PMU functions and events  #################################### */\n\n#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)\n\n#include \"pmu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n/* ##########################  MVE functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_MveFunctions MVE Functions\n  \\brief    Function that provides MVE type.\n  @{\n */\n\n/**\n  \\brief   get MVE type\n  \\details returns the MVE type\n  \\returns\n   - \\b  0: No Vector Extension (MVE)\n   - \\b  1: Integer Vector Extension (MVE-I)\n   - \\b  2: Floating-point Vector Extension (MVE-F)\n */\n__STATIC_INLINE uint32_t SCB_GetMVEType(void)\n{\n  const uint32_t mvfr1 = FPU->MVFR1;\n  if      ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))\n  {\n    return 2U;\n  }\n  else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))\n  {\n    return 1U;\n  }\n  else\n  {\n    return 0U;\n  }\n}\n\n\n/*@} end of CMSIS_Core_MveFunctions */\n\n\n/* ##########################  Cache functions  #################################### */\n\n#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \\\n     (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))\n#include \"cachel1_armv7.h\"\n#endif\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    Debug Control function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DCBFunctions Debug Control Functions\n  \\brief    Functions that access the Debug Control Block.\n  @{\n */\n\n\n/**\n  \\brief   Set Debug Authentication Control Register\n  \\details writes to Debug Authentication Control register.\n  \\param [in]  value  value to be writen.\n */\n__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register\n  \\details Reads Debug Authentication Control register.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)\n{\n    return (DCB->DAUTHCTRL);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Debug Authentication Control Register (non-secure)\n  \\details writes to non-secure Debug Authentication Control register when in secure state.\n  \\param [in]  value  value to be writen\n */\n__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB_NS->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register (non-secure)\n  \\details Reads non-secure Debug Authentication Control register when in secure state.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)\n{\n    return (DCB_NS->DAUTHCTRL);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    Debug Identification function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions\n  \\brief    Functions that access the Debug Identification Block.\n  @{\n */\n\n\n/**\n  \\brief   Get Debug Authentication Status Register\n  \\details Reads Debug Authentication Status register.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)\n{\n    return (DIB->DAUTHSTATUS);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Debug Authentication Status Register (non-secure)\n  \\details Reads non-secure Debug Authentication Status register when in secure state.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)\n{\n    return (DIB_NS->DAUTHSTATUS);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV81MML_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h",
    "content": "/**************************************************************************//**\n * @file     core_armv8mbl.h\n * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\n * @version  V5.2.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include                        /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header                   /* treat file as system include file */\n#elif defined ( __GNUC__ )\n  #pragma GCC diagnostic ignored \"-Wpedantic\"   /* disable pedantic warning due to unnamed structs/unions */\n#endif\n\n#ifndef __CORE_ARMV8MBL_H_GENERIC\n#define __CORE_ARMV8MBL_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMv8MBL\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS definitions */\n#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                     (2U)                                        /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MBL_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV8MBL_H_DEPENDANT\n#define __CORE_ARMV8MBL_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv8MBL_REV\n    #define __ARMv8MBL_REV               0x0000U\n    #warning \"__ARMv8MBL_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ETM_PRESENT\n    #define __ETM_PRESENT             0U\n    #warning \"__ETM_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MTB_PRESENT\n    #define __MTB_PRESENT             0U\n    #warning \"__MTB_PRESENT not defined in device header file; using default!\"\n  #endif\n\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group ARMv8MBL */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n        uint32_t RESERVED0[6U];\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n        uint32_t RESERVED0[7U];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#endif\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  \\deprecated Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \\deprecated CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \\deprecated CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \\deprecated CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \\deprecated CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \\deprecated CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \\deprecated CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \\deprecated CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \\deprecated CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \\deprecated CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< \\deprecated CoreDebug DEMCR: DWTENA Position */\n#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< \\deprecated CoreDebug DEMCR: DWTENA Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \\deprecated CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \\deprecated CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup CMSIS_DCB       Debug Control Block\n  \\brief    Type definitions for the Debug Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Control Block Registers (DCB).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} DCB_Type;\n\n/* DHCSR, Debug Halting Control and Status Register Definitions */\n#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */\n#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */\n\n#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */\n#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */\n\n#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */\n#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */\n\n#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */\n#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */\n\n#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */\n#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */\n\n#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */\n#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */\n\n#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */\n#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */\n\n#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */\n#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */\n\n#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */\n#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */\n\n#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */\n#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */\n\n#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */\n#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */\n\n#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */\n#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */\n\n#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */\n#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */\n\n/* DCRSR, Debug Core Register Select Register Definitions */\n#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */\n#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */\n\n#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */\n#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */\n\n/* DCRDR, Debug Core Register Data Register Definitions */\n#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */\n#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */\n\n/* DEMCR, Debug Exception and Monitor Control Register Definitions */\n#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */\n#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */\n\n#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */\n#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */\n\n#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */\n#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */\n\n/* DAUTHCTRL, Debug Authentication Control Register Definitions */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */\n\n#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */\n\n/* DSCSR, Debug Security Control and Status Register Definitions */\n#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */\n#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */\n\n#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */\n#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */\n\n#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */\n#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */\n\n#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */\n#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */\n\n/*@} end of group CMSIS_DCB */\n\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DIB       Debug Identification Block\n  \\brief    Type definitions for the Debug Identification Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Identification Block Registers (DIB).\n */\ntypedef struct\n{\n  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */\n  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */\n  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */\n  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */\n  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */\n} DIB_Type;\n\n/* DLAR, SCS Software Lock Access Register Definitions */\n#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */\n#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */\n\n/* DLSR, SCS Software Lock Status Register Definitions */\n#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */\n#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */\n\n#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */\n#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */\n\n#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */\n#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */\n\n/* DAUTHSTATUS, Debug Authentication Status Register Definitions */\n#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */\n\n/* DDEVARCH, SCS Device Architecture Register Definitions */\n#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */\n#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */\n\n#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */\n#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */\n\n#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */\n#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */\n\n#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */\n#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */\n\n#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */\n#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */\n\n/* DDEVTYPE, SCS Device Type Register Definitions */\n#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */\n#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */\n\n#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */\n#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */\n\n\n/*@} end of group CMSIS_DIB */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \\deprecated Core Debug Base Address */\n  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */\n  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \\deprecated Core Debug configuration struct */\n  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */\n  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \\deprecated Core Debug Base Address           (non-secure address space) */\n  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */\n  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \\deprecated Core Debug configuration struct   (non-secure address space) */\n  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */\n  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    Debug Control function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DCBFunctions Debug Control Functions\n  \\brief    Functions that access the Debug Control Block.\n  @{\n */\n\n \n/**\n  \\brief   Set Debug Authentication Control Register\n  \\details writes to Debug Authentication Control register.\n  \\param [in]  value  value to be writen.\n */\n__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register\n  \\details Reads Debug Authentication Control register.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)\n{\n    return (DCB->DAUTHCTRL);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Debug Authentication Control Register (non-secure)\n  \\details writes to non-secure Debug Authentication Control register when in secure state.\n  \\param [in]  value  value to be writen\n */\n__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB_NS->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register (non-secure)\n  \\details Reads non-secure Debug Authentication Control register when in secure state.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)\n{\n    return (DCB_NS->DAUTHCTRL);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    Debug Identification function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions\n  \\brief    Functions that access the Debug Identification Block.\n  @{\n */\n\n \n/**\n  \\brief   Get Debug Authentication Status Register\n  \\details Reads Debug Authentication Status register.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)\n{\n    return (DIB->DAUTHSTATUS);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Debug Authentication Status Register (non-secure)\n  \\details Reads non-secure Debug Authentication Status register when in secure state.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)\n{\n    return (DIB_NS->DAUTHSTATUS);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h",
    "content": "/**************************************************************************//**\n * @file     core_armv8mml.h\n * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\n * @version  V5.3.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include                        /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header                   /* treat file as system include file */\n#elif defined ( __GNUC__ )\n  #pragma GCC diagnostic ignored \"-Wpedantic\"   /* disable pedantic warning due to unnamed structs/unions */\n#endif\n\n#ifndef __CORE_ARMV8MML_H_GENERIC\n#define __CORE_ARMV8MML_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMv8MML\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS Armv8MML definitions */\n#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                     (80U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED       0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MML_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV8MML_H_DEPENDANT\n#define __CORE_ARMV8MML_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv8MML_REV\n    #define __ARMv8MML_REV               0x0000U\n    #warning \"__ARMv8MML_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/** @} end of group ARMv8MML */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/** @} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/** @} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED7[21U];\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */\n        uint32_t RESERVED3[69U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/** @} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/** @} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/** @} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/** @}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/** @}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/** @}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/** @} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/** @} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and VFP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and VFP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and VFP Feature Register 2 Definitions */\n#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */\n#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */\n\n/** @} end of group CMSIS_FPU */\n\n/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  \\deprecated Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \\deprecated CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \\deprecated CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \\deprecated CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \\deprecated CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \\deprecated CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \\deprecated CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \\deprecated CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \\deprecated CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \\deprecated CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< \\deprecated CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< \\deprecated CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< \\deprecated CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< \\deprecated CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< \\deprecated CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< \\deprecated CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< \\deprecated CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< \\deprecated CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \\deprecated CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \\deprecated CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Mask */\n\n/** @} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup CMSIS_DCB       Debug Control Block\n  \\brief    Type definitions for the Debug Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Control Block Registers (DCB).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} DCB_Type;\n\n/* DHCSR, Debug Halting Control and Status Register Definitions */\n#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */\n#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */\n\n#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */\n#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */\n\n#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */\n#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */\n\n#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */\n#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */\n\n#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */\n#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */\n\n#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */\n#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */\n\n#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */\n#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */\n\n#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */\n#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */\n\n#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */\n#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */\n\n#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */\n#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */\n\n#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */\n#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */\n\n#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */\n#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */\n\n#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */\n#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */\n\n#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */\n#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */\n\n/* DCRSR, Debug Core Register Select Register Definitions */\n#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */\n#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */\n\n#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */\n#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */\n\n/* DCRDR, Debug Core Register Data Register Definitions */\n#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */\n#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */\n\n/* DEMCR, Debug Exception and Monitor Control Register Definitions */\n#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */\n#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */\n\n#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */\n#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */\n\n#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */\n#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */\n\n#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */\n#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */\n\n#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */\n#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */\n\n#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */\n#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */\n\n#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */\n#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */\n\n#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */\n#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */\n\n#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */\n#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */\n\n#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */\n#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */\n\n#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */\n#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */\n\n#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */\n#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */\n\n#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */\n#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */\n\n#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */\n#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */\n\n#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */\n#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */\n\n#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */\n#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */\n\n#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */\n#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */\n\n/* DAUTHCTRL, Debug Authentication Control Register Definitions */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */\n\n#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */\n\n/* DSCSR, Debug Security Control and Status Register Definitions */\n#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */\n#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */\n\n#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */\n#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */\n\n#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */\n#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */\n\n#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */\n#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */\n\n/** @} end of group CMSIS_DCB */\n\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DIB       Debug Identification Block\n  \\brief    Type definitions for the Debug Identification Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Identification Block Registers (DIB).\n */\ntypedef struct\n{\n  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */\n  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */\n  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */\n  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */\n  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */\n} DIB_Type;\n\n/* DLAR, SCS Software Lock Access Register Definitions */\n#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */\n#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */\n\n/* DLSR, SCS Software Lock Status Register Definitions */\n#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */\n#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */\n\n#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */\n#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */\n\n#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */\n#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */\n\n/* DAUTHSTATUS, Debug Authentication Status Register Definitions */\n#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */\n\n/* DDEVARCH, SCS Device Architecture Register Definitions */\n#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */\n#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */\n\n#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */\n#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */\n\n#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */\n#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */\n\n#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */\n#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */\n\n#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */\n#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */\n\n/* DDEVTYPE, SCS Device Type Register Definitions */\n#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */\n#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */\n\n#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */\n#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */\n\n\n/** @} end of group CMSIS_DIB */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/** @} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \\deprecated Core Debug Base Address */\n  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */\n  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \\deprecated Core Debug configuration struct */\n  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */\n  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \\deprecated Core Debug Base Address           (non-secure address space) */\n  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */\n  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \\deprecated Core Debug configuration struct   (non-secure address space) */\n  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */\n  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/** @} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */\n/*@} */\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)                      );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/** @} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/** @} end of CMSIS_Core_FpuFunctions */\n\n\n/* ##########################  Cache functions  #################################### */\n\n#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \\\n     (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))\n#include \"cachel1_armv7.h\"\n#endif\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/** @} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    Debug Control function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DCBFunctions Debug Control Functions\n  \\brief    Functions that access the Debug Control Block.\n  @{\n */\n\n\n/**\n  \\brief   Set Debug Authentication Control Register\n  \\details writes to Debug Authentication Control register.\n  \\param [in]  value  value to be writen.\n */\n__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register\n  \\details Reads Debug Authentication Control register.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)\n{\n    return (DCB->DAUTHCTRL);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Debug Authentication Control Register (non-secure)\n  \\details writes to non-secure Debug Authentication Control register when in secure state.\n  \\param [in]  value  value to be writen\n */\n__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB_NS->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register (non-secure)\n  \\details Reads non-secure Debug Authentication Control register when in secure state.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)\n{\n    return (DCB_NS->DAUTHCTRL);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/** @} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    Debug Identification function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions\n  \\brief    Functions that access the Debug Identification Block.\n  @{\n */\n\n\n/**\n  \\brief   Get Debug Authentication Status Register\n  \\details Reads Debug Authentication Status register.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)\n{\n    return (DIB->DAUTHSTATUS);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Debug Authentication Status Register (non-secure)\n  \\details Reads non-secure Debug Authentication Status register when in secure state.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)\n{\n    return (DIB_NS->DAUTHSTATUS);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/** @} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/** @} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/** @} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MML_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm0.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0.h\n * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0_H_GENERIC\n#define __CORE_CM0_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M0\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM0 definitions */\n#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ti__)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0_H_DEPENDANT\n#define __CORE_CM0_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0_REV\n    #define __CM0_REV               0x0000U\n    #warning \"__CM0_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M0 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */\n  *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to access vector */\n  /* ARM Application Note 321 states that the M0 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */\n  return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to access vector */\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0plus.h\n * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0PLUS_H_GENERIC\n#define __CORE_CM0PLUS_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex-M0+\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM0+ definitions */\n#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\\n                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ti__)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0PLUS_H_DEPENDANT\n#define __CORE_CM0PLUS_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0PLUS_REV\n    #define __CM0PLUS_REV             0x0000U\n    #warning \"__CM0PLUS_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex-M0+ */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0+ header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n#else\n  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */\n  *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to access vector */\n#endif\n  /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n#else\n  uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt */\n  return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to access vector */\n#endif\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm1.h",
    "content": "/**************************************************************************//**\n * @file     core_cm1.h\n * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File\n * @version  V1.1.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM1_H_GENERIC\n#define __CORE_CM1_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M1\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM1 definitions */\n#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ti__)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM1_H_DEPENDANT\n#define __CORE_CM1_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM1_REV\n    #define __CM1_REV               0x0100U\n    #warning \"__CM1_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M1 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */\n\n#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M1 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  /* ARM Application Note 321 states that the M1 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm23.h",
    "content": "/**************************************************************************//**\n * @file     core_cm23.h\n * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File\n * @version  V5.2.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include                        /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header                   /* treat file as system include file */\n#elif defined ( __GNUC__ )\n  #pragma GCC diagnostic ignored \"-Wpedantic\"   /* disable pedantic warning due to unnamed structs/unions */\n#endif\n\n#ifndef __CORE_CM23_H_GENERIC\n#define __CORE_CM23_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M23\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS definitions */\n#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ti__)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM23_H_DEPENDANT\n#define __CORE_CM23_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM23_REV\n    #define __CM23_REV                0x0000U\n    #warning \"__CM23_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ETM_PRESENT\n    #define __ETM_PRESENT             0U\n    #warning \"__ETM_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MTB_PRESENT\n    #define __MTB_PRESENT             0U\n    #warning \"__MTB_PRESENT not defined in device header file; using default!\"\n  #endif\n\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M23 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n        uint32_t RESERVED0[6U];\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n        uint32_t RESERVED0[7U];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#endif\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  \\deprecated Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \\deprecated CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \\deprecated CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \\deprecated CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \\deprecated CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \\deprecated CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \\deprecated CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \\deprecated CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \\deprecated CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \\deprecated CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register */\n#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< \\deprecated CoreDebug DEMCR: DWTENA Position */\n#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< \\deprecated CoreDebug DEMCR: DWTENA Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \\deprecated CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \\deprecated CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup CMSIS_DCB       Debug Control Block\n  \\brief    Type definitions for the Debug Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Control Block Registers (DCB).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} DCB_Type;\n\n/* DHCSR, Debug Halting Control and Status Register Definitions */\n#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */\n#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */\n\n#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */\n#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */\n\n#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */\n#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */\n\n#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */\n#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */\n\n#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */\n#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */\n\n#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */\n#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */\n\n#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */\n#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */\n\n#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */\n#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */\n\n#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */\n#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */\n\n#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */\n#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */\n\n#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */\n#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */\n\n#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */\n#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */\n\n#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */\n#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */\n\n/* DCRSR, Debug Core Register Select Register Definitions */\n#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */\n#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */\n\n#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */\n#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */\n\n/* DCRDR, Debug Core Register Data Register Definitions */\n#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */\n#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */\n\n/* DEMCR, Debug Exception and Monitor Control Register Definitions */\n#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */\n#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */\n\n#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */\n#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */\n\n#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */\n#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */\n\n/* DAUTHCTRL, Debug Authentication Control Register Definitions */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */\n\n#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */\n\n/* DSCSR, Debug Security Control and Status Register Definitions */\n#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */\n#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */\n\n#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */\n#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */\n\n#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */\n#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */\n\n#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */\n#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */\n\n/*@} end of group CMSIS_DCB */\n\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DIB       Debug Identification Block\n  \\brief    Type definitions for the Debug Identification Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Identification Block Registers (DIB).\n */\ntypedef struct\n{\n  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */\n  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */\n  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */\n  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */\n  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */\n} DIB_Type;\n\n/* DLAR, SCS Software Lock Access Register Definitions */\n#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */\n#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */\n\n/* DLSR, SCS Software Lock Status Register Definitions */\n#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */\n#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */\n\n#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */\n#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */\n\n#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */\n#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */\n\n/* DAUTHSTATUS, Debug Authentication Status Register Definitions */\n#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */\n\n/* DDEVARCH, SCS Device Architecture Register Definitions */\n#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */\n#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */\n\n#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */\n#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */\n\n#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */\n#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */\n\n#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */\n#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */\n\n#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */\n#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */\n\n/* DDEVTYPE, SCS Device Type Register Definitions */\n#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */\n#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */\n\n#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */\n#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */\n\n\n/*@} end of group CMSIS_DIB */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \\deprecated Core Debug Base Address */\n  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */\n  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \\deprecated Core Debug configuration struct */\n  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */\n  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \\deprecated Core Debug Base Address           (non-secure address space) */\n  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */\n  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \\deprecated Core Debug configuration struct   (non-secure address space) */\n  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */\n  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */\n/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    Debug Control function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DCBFunctions Debug Control Functions\n  \\brief    Functions that access the Debug Control Block.\n  @{\n */\n\n \n/**\n  \\brief   Set Debug Authentication Control Register\n  \\details writes to Debug Authentication Control register.\n  \\param [in]  value  value to be writen.\n */\n__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register\n  \\details Reads Debug Authentication Control register.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)\n{\n    return (DCB->DAUTHCTRL);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Debug Authentication Control Register (non-secure)\n  \\details writes to non-secure Debug Authentication Control register when in secure state.\n  \\param [in]  value  value to be writen\n */\n__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB_NS->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register (non-secure)\n  \\details Reads non-secure Debug Authentication Control register when in secure state.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)\n{\n    return (DCB_NS->DAUTHCTRL);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    Debug Identification function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions\n  \\brief    Functions that access the Debug Identification Block.\n  @{\n */\n\n \n/**\n  \\brief   Get Debug Authentication Status Register\n  \\details Reads Debug Authentication Status register.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)\n{\n    return (DIB->DAUTHSTATUS);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Debug Authentication Status Register (non-secure)\n  \\details Reads non-secure Debug Authentication Status register when in secure state.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)\n{\n    return (DIB_NS->DAUTHSTATUS);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm3.h",
    "content": "/**************************************************************************//**\n * @file     core_cm3.h\n * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\n * @version  V5.2.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM3_H_GENERIC\n#define __CORE_CM3_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M3\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM3 definitions */\n#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ti__)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM3_H_DEPENDANT\n#define __CORE_CM3_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM3_REV\n    #define __CM3_REV               0x0200U\n    #warning \"__CM3_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M3 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#else\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n#else\n        uint32_t RESERVED1[1U];\n#endif\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\n\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n#endif\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_BYTEACC_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_BYTEACC_Msk                (1UL << ITM_LSR_BYTEACC_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_ACCESS_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_ACCESS_Msk                 (1UL << ITM_LSR_ACCESS_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_PRESENT_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_PRESENT_Msk                (1UL /*<< ITM_LSR_PRESENT_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n\n/* Capitalize ITM_TCR Register Definitions */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_TraceBusID_Pos           (ITM_TCR_TRACEBUSID_Pos)     /*!< \\deprecated ITM_TCR_TraceBusID_Pos */\n#define ITM_TCR_TraceBusID_Msk           (ITM_TCR_TRACEBUSID_Msk)     /*!< \\deprecated ITM_TCR_TraceBusID_Msk */\n\n#define ITM_TCR_TSPrescale_Pos           (ITM_TCR_TSPRESCALE_Pos)     /*!< \\deprecated ITM_TCR_TSPrescale_Pos */\n#define ITM_TCR_TSPrescale_Msk           (ITM_TCR_TSPRESCALE_Msk)     /*!< \\deprecated ITM_TCR_TSPrescale_Msk */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos              (ITM_LSR_BYTEACC_Pos)        /*!< \\deprecated ITM_LSR_ByteAcc_Pos */\n#define ITM_LSR_ByteAcc_Msk              (ITM_LSR_BYTEACC_Msk)        /*!< \\deprecated ITM_LSR_ByteAcc_Msk */\n\n#define ITM_LSR_Access_Pos               (ITM_LSR_ACCESS_Pos)         /*!< \\deprecated ITM_LSR_Access_Pos */\n#define ITM_LSR_Access_Msk               (ITM_LSR_ACCESS_Msk)         /*!< \\deprecated ITM_LSR_Access_Msk */\n\n#define ITM_LSR_Present_Pos              (ITM_LSR_PRESENT_Pos)        /*!< \\deprecated ITM_LSR_Present_Pos */\n#define ITM_LSR_Present_Msk              (ITM_LSR_PRESENT_Msk)        /*!< \\deprecated ITM_LSR_Present_Msk */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  /* ARM Application Note 321 states that the M3 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm33.h",
    "content": "/**************************************************************************//**\n * @file     core_cm33.h\n * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File\n * @version  V5.3.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include                        /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header                   /* treat file as system include file */\n#elif defined ( __GNUC__ )\n  #pragma GCC diagnostic ignored \"-Wpedantic\"   /* disable pedantic warning due to unnamed structs/unions */\n#endif\n\n#ifndef __CORE_CM33_H_GENERIC\n#define __CORE_CM33_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M33\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM33 definitions */\n#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined (__TARGET_FPU_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED       0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined (__ARMVFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined (__TI_VFP_SUPPORT__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined (__FPU_VFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM33_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM33_H_DEPENDANT\n#define __CORE_CM33_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM33_REV\n    #define __CM33_REV                0x0000U\n    #warning \"__CM33_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M33 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED7[21U];\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */\n        uint32_t RESERVED3[69U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and VFP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and VFP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and VFP Feature Register 2 Definitions */\n#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */\n#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  \\deprecated Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \\deprecated CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \\deprecated CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \\deprecated CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \\deprecated CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \\deprecated CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \\deprecated CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \\deprecated CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \\deprecated CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \\deprecated CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< \\deprecated CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< \\deprecated CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< \\deprecated CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< \\deprecated CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< \\deprecated CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< \\deprecated CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< \\deprecated CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< \\deprecated CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \\deprecated CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \\deprecated CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup CMSIS_DCB       Debug Control Block\n  \\brief    Type definitions for the Debug Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Control Block Registers (DCB).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} DCB_Type;\n\n/* DHCSR, Debug Halting Control and Status Register Definitions */\n#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */\n#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */\n\n#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */\n#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */\n\n#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */\n#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */\n\n#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */\n#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */\n\n#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */\n#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */\n\n#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */\n#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */\n\n#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */\n#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */\n\n#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */\n#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */\n\n#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */\n#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */\n\n#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */\n#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */\n\n#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */\n#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */\n\n#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */\n#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */\n\n#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */\n#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */\n\n#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */\n#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */\n\n/* DCRSR, Debug Core Register Select Register Definitions */\n#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */\n#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */\n\n#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */\n#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */\n\n/* DCRDR, Debug Core Register Data Register Definitions */\n#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */\n#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */\n\n/* DEMCR, Debug Exception and Monitor Control Register Definitions */\n#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */\n#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */\n\n#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */\n#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */\n\n#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */\n#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */\n\n#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */\n#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */\n\n#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */\n#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */\n\n#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */\n#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */\n\n#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */\n#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */\n\n#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */\n#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */\n\n#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */\n#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */\n\n#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */\n#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */\n\n#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */\n#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */\n\n#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */\n#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */\n\n#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */\n#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */\n\n#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */\n#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */\n\n#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */\n#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */\n\n#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */\n#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */\n\n#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */\n#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */\n\n/* DAUTHCTRL, Debug Authentication Control Register Definitions */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */\n\n#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */\n\n/* DSCSR, Debug Security Control and Status Register Definitions */\n#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */\n#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */\n\n#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */\n#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */\n\n#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */\n#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */\n\n#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */\n#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */\n\n/*@} end of group CMSIS_DCB */\n\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DIB       Debug Identification Block\n  \\brief    Type definitions for the Debug Identification Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Identification Block Registers (DIB).\n */\ntypedef struct\n{\n  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */\n  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */\n  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */\n  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */\n  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */\n} DIB_Type;\n\n/* DLAR, SCS Software Lock Access Register Definitions */\n#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */\n#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */\n\n/* DLSR, SCS Software Lock Status Register Definitions */\n#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */\n#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */\n\n#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */\n#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */\n\n#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */\n#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */\n\n/* DAUTHSTATUS, Debug Authentication Status Register Definitions */\n#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */\n\n/* DDEVARCH, SCS Device Architecture Register Definitions */\n#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */\n#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */\n\n#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */\n#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */\n\n#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */\n#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */\n\n#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */\n#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */\n\n#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */\n#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */\n\n/* DDEVTYPE, SCS Device Type Register Definitions */\n#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */\n#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */\n\n#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */\n#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */\n\n\n/*@} end of group CMSIS_DIB */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \\deprecated Core Debug Base Address */\n  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */\n  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \\deprecated Core Debug configuration struct */\n  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */\n  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \\deprecated Core Debug Base Address           (non-secure address space) */\n  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */\n  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \\deprecated Core Debug configuration struct   (non-secure address space) */\n  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */\n  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */\n/*@} */\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    Debug Control function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DCBFunctions Debug Control Functions\n  \\brief    Functions that access the Debug Control Block.\n  @{\n */\n\n\n/**\n  \\brief   Set Debug Authentication Control Register\n  \\details writes to Debug Authentication Control register.\n  \\param [in]  value  value to be writen.\n */\n__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register\n  \\details Reads Debug Authentication Control register.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)\n{\n    return (DCB->DAUTHCTRL);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Debug Authentication Control Register (non-secure)\n  \\details writes to non-secure Debug Authentication Control register when in secure state.\n  \\param [in]  value  value to be writen\n */\n__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB_NS->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register (non-secure)\n  \\details Reads non-secure Debug Authentication Control register when in secure state.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)\n{\n    return (DCB_NS->DAUTHCTRL);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    Debug Identification function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions\n  \\brief    Functions that access the Debug Identification Block.\n  @{\n */\n\n\n/**\n  \\brief   Get Debug Authentication Status Register\n  \\details Reads Debug Authentication Status register.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)\n{\n    return (DIB->DAUTHSTATUS);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Debug Authentication Status Register (non-secure)\n  \\details Reads non-secure Debug Authentication Status register when in secure state.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)\n{\n    return (DIB_NS->DAUTHSTATUS);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM33_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm35p.h",
    "content": "/**************************************************************************//**\n * @file     core_cm35p.h\n * @brief    CMSIS Cortex-M35P Core Peripheral Access Layer Header File\n * @version  V1.2.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2018-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include                        /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header                   /* treat file as system include file */\n#elif defined ( __GNUC__ )\n  #pragma GCC diagnostic ignored \"-Wpedantic\"   /* disable pedantic warning due to unnamed structs/unions */\n#endif\n\n#ifndef __CORE_CM35P_H_GENERIC\n#define __CORE_CM35P_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M35P\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM35P definitions */\n#define __CM35P_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM35P_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                   /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM35P_CMSIS_VERSION       ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __CM35P_CMSIS_VERSION_SUB           )    /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (35U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined (__TARGET_FPU_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED       0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined (__ARMVFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined (__TI_VFP_SUPPORT__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined (__FPU_VFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM35P_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM35P_H_DEPENDANT\n#define __CORE_CM35P_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM35P_REV\n    #define __CM35P_REV               0x0000U\n    #warning \"__CM35P_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M35P */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED7[21U];\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */\n        uint32_t RESERVED3[69U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and VFP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and VFP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and VFP Feature Register 2 Definitions */\n#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */\n#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  \\deprecated Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \\deprecated CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \\deprecated CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \\deprecated CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \\deprecated CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \\deprecated CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \\deprecated CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \\deprecated CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \\deprecated CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \\deprecated CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< \\deprecated CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< \\deprecated CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< \\deprecated CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< \\deprecated CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< \\deprecated CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< \\deprecated CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< \\deprecated CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< \\deprecated CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \\deprecated CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \\deprecated CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup CMSIS_DCB       Debug Control Block\n  \\brief    Type definitions for the Debug Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Control Block Registers (DCB).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} DCB_Type;\n\n/* DHCSR, Debug Halting Control and Status Register Definitions */\n#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */\n#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */\n\n#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */\n#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */\n\n#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */\n#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */\n\n#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */\n#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */\n\n#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */\n#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */\n\n#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */\n#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */\n\n#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */\n#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */\n\n#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */\n#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */\n\n#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */\n#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */\n\n#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */\n#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */\n\n#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */\n#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */\n\n#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */\n#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */\n\n#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */\n#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */\n\n#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */\n#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */\n\n/* DCRSR, Debug Core Register Select Register Definitions */\n#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */\n#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */\n\n#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */\n#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */\n\n/* DCRDR, Debug Core Register Data Register Definitions */\n#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */\n#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */\n\n/* DEMCR, Debug Exception and Monitor Control Register Definitions */\n#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */\n#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */\n\n#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */\n#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */\n\n#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */\n#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */\n\n#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */\n#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */\n\n#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */\n#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */\n\n#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */\n#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */\n\n#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */\n#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */\n\n#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */\n#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */\n\n#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */\n#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */\n\n#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */\n#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */\n\n#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */\n#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */\n\n#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */\n#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */\n\n#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */\n#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */\n\n#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */\n#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */\n\n#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */\n#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */\n\n#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */\n#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */\n\n#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */\n#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */\n\n/* DAUTHCTRL, Debug Authentication Control Register Definitions */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */\n\n#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */\n\n/* DSCSR, Debug Security Control and Status Register Definitions */\n#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */\n#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */\n\n#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */\n#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */\n\n#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */\n#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */\n\n#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */\n#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */\n\n/*@} end of group CMSIS_DCB */\n\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DIB       Debug Identification Block\n  \\brief    Type definitions for the Debug Identification Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Identification Block Registers (DIB).\n */\ntypedef struct\n{\n  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */\n  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */\n  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */\n  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */\n  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */\n} DIB_Type;\n\n/* DLAR, SCS Software Lock Access Register Definitions */\n#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */\n#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */\n\n/* DLSR, SCS Software Lock Status Register Definitions */\n#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */\n#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */\n\n#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */\n#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */\n\n#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */\n#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */\n\n/* DAUTHSTATUS, Debug Authentication Status Register Definitions */\n#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */\n\n/* DDEVARCH, SCS Device Architecture Register Definitions */\n#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */\n#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */\n\n#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */\n#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */\n\n#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */\n#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */\n\n#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */\n#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */\n\n#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */\n#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */\n\n/* DDEVTYPE, SCS Device Type Register Definitions */\n#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */\n#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */\n\n#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */\n#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */\n\n\n/*@} end of group CMSIS_DIB */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \\deprecated Core Debug Base Address */\n  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */\n  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \\deprecated Core Debug configuration struct */\n  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */\n  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \\deprecated Core Debug Base Address           (non-secure address space) */\n  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */\n  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \\deprecated Core Debug configuration struct   (non-secure address space) */\n  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */\n  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */\n/*@} */\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    Debug Control function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DCBFunctions Debug Control Functions\n  \\brief    Functions that access the Debug Control Block.\n  @{\n */\n\n\n/**\n  \\brief   Set Debug Authentication Control Register\n  \\details writes to Debug Authentication Control register.\n  \\param [in]  value  value to be writen.\n */\n__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register\n  \\details Reads Debug Authentication Control register.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)\n{\n    return (DCB->DAUTHCTRL);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Debug Authentication Control Register (non-secure)\n  \\details writes to non-secure Debug Authentication Control register when in secure state.\n  \\param [in]  value  value to be writen\n */\n__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB_NS->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register (non-secure)\n  \\details Reads non-secure Debug Authentication Control register when in secure state.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)\n{\n    return (DCB_NS->DAUTHCTRL);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    Debug Identification function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions\n  \\brief    Functions that access the Debug Identification Block.\n  @{\n */\n\n\n/**\n  \\brief   Get Debug Authentication Status Register\n  \\details Reads Debug Authentication Status register.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)\n{\n    return (DIB->DAUTHSTATUS);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Debug Authentication Status Register (non-secure)\n  \\details Reads non-secure Debug Authentication Status register when in secure state.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)\n{\n    return (DIB_NS->DAUTHSTATUS);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM35P_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm4.h",
    "content": "/**************************************************************************//**\n * @file     core_cm4.h\n * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\n * @version  V5.2.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM4_H_GENERIC\n#define __CORE_CM4_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M4\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM4 definitions */\n#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM4_H_DEPENDANT\n#define __CORE_CM4_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM4_REV\n    #define __CM4_REV               0x0000U\n    #warning \"__CM4_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M4 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\n\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_BYTEACC_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_BYTEACC_Msk                (1UL << ITM_LSR_BYTEACC_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_ACCESS_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_ACCESS_Msk                 (1UL << ITM_LSR_ACCESS_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_PRESENT_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_PRESENT_Msk                (1UL /*<< ITM_LSR_PRESENT_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and FP Feature Register 2 Definitions */\n\n#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */\n#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n\n/*@} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n\n/* Capitalize ITM_TCR Register Definitions */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_TraceBusID_Pos           (ITM_TCR_TRACEBUSID_Pos)     /*!< \\deprecated ITM_TCR_TraceBusID_Pos */\n#define ITM_TCR_TraceBusID_Msk           (ITM_TCR_TRACEBUSID_Msk)     /*!< \\deprecated ITM_TCR_TraceBusID_Msk */\n\n#define ITM_TCR_TSPrescale_Pos           (ITM_TCR_TSPRESCALE_Pos)     /*!< \\deprecated ITM_TCR_TSPrescale_Pos */\n#define ITM_TCR_TSPrescale_Msk           (ITM_TCR_TSPRESCALE_Msk)     /*!< \\deprecated ITM_TCR_TSPrescale_Msk */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos              (ITM_LSR_BYTEACC_Pos)        /*!< \\deprecated ITM_LSR_ByteAcc_Pos */\n#define ITM_LSR_ByteAcc_Msk              (ITM_LSR_BYTEACC_Msk)        /*!< \\deprecated ITM_LSR_ByteAcc_Msk */\n\n#define ITM_LSR_Access_Pos               (ITM_LSR_ACCESS_Pos)         /*!< \\deprecated ITM_LSR_Access_Pos */\n#define ITM_LSR_Access_Msk               (ITM_LSR_ACCESS_Msk)         /*!< \\deprecated ITM_LSR_Access_Msk */\n\n#define ITM_LSR_Present_Pos              (ITM_LSR_PRESENT_Pos)        /*!< \\deprecated ITM_LSR_Present_Pos */\n#define ITM_LSR_Present_Msk              (ITM_LSR_PRESENT_Msk)        /*!< \\deprecated ITM_LSR_Present_Msk */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  /* ARM Application Note 321 states that the M4 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm55.h",
    "content": "/**************************************************************************//**\n * @file     core_cm55.h\n * @brief    CMSIS Cortex-M55 Core Peripheral Access Layer Header File\n * @version  V1.5.2\n * @date     19. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2018-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include                        /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header                   /* treat file as system include file */\n#elif defined ( __GNUC__ )\n  #pragma GCC diagnostic ignored \"-Wpedantic\"   /* disable pedantic warning due to unnamed structs/unions */\n#endif\n\n#ifndef __CORE_CM55_H_GENERIC\n#define __CORE_CM55_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M55\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM55 definitions */\n#define __CM55_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM55_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                   /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM55_CMSIS_VERSION       ((__CM55_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM55_CMSIS_VERSION_SUB           )     /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                      (55U)                                 /*!< Cortex-M Core */\n\n#if defined ( __CC_ARM )\n  #error Legacy Arm Compiler does not support Armv8.1-M target architecture.\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED       0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED       0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM55_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM55_H_DEPENDANT\n#define __CORE_CM55_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM55_REV\n    #define __CM55_REV               0x0000U\n    #warning \"__CM55_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #if __FPU_PRESENT != 0U\n    #ifndef __FPU_DP\n      #define __FPU_DP             0U\n      #warning \"__FPU_DP not defined in device header file; using default!\"\n    #endif\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ICACHE_PRESENT\n    #define __ICACHE_PRESENT          0U\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DCACHE_PRESENT\n    #define __DCACHE_PRESENT          0U\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __PMU_PRESENT\n    #define __PMU_PRESENT             0U\n    #warning \"__PMU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #if __PMU_PRESENT != 0U\n    #ifndef __PMU_NUM_EVENTCNT\n      #define __PMU_NUM_EVENTCNT      8U\n      #warning \"__PMU_NUM_EVENTCNT not defined in device header file; using default!\"\n    #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2)\n    #error \"__PMU_NUM_EVENTCNT is out of range in device header file!\" */\n    #endif\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M55 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core EWIC Register\n  - Core EWIC Interrupt Status Access Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core PMU Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED7[21U];\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */\n        uint32_t RESERVED3[69U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n  __IOM uint32_t RFSR;                   /*!< Offset: 0x204 (R/W)  RAS Fault Status Register */\n        uint32_t RESERVED4[14U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_IESB_Pos                  5U                                            /*!< SCB AIRCR: Implicit ESB Enable Position */\n#define SCB_AIRCR_IESB_Msk                 (1UL << SCB_AIRCR_IESB_Pos)                    /*!< SCB AIRCR: Implicit ESB Enable Mask */\n\n#define SCB_AIRCR_DIT_Pos                   4U                                            /*!< SCB AIRCR: Data Independent Timing Position */\n#define SCB_AIRCR_DIT_Msk                  (1UL << SCB_AIRCR_DIT_Pos)                     /*!< SCB AIRCR: Data Independent Timing Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_TRD_Pos                    20U                                            /*!< SCB CCR: TRD Position */\n#define SCB_CCR_TRD_Msk                    (1UL << SCB_CCR_TRD_Pos)                       /*!< SCB CCR: TRD Mask */\n\n#define SCB_CCR_LOB_Pos                    19U                                            /*!< SCB CCR: LOB Position */\n#define SCB_CCR_LOB_Msk                    (1UL << SCB_CCR_LOB_Pos)                       /*!< SCB CCR: LOB Mask */\n\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_PMU_Pos                    5U                                            /*!< SCB DFSR: PMU Position */\n#define SCB_DFSR_PMU_Msk                   (1UL << SCB_DFSR_PMU_Pos)                      /*!< SCB DFSR: PMU Mask */\n\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CP7_Pos                   7U                                            /*!< SCB NSACR: CP7 Position */\n#define SCB_NSACR_CP7_Msk                  (1UL << SCB_NSACR_CP7_Pos)                     /*!< SCB NSACR: CP7 Mask */\n\n#define SCB_NSACR_CP6_Pos                   6U                                            /*!< SCB NSACR: CP6 Position */\n#define SCB_NSACR_CP6_Msk                  (1UL << SCB_NSACR_CP6_Pos)                     /*!< SCB NSACR: CP6 Mask */\n\n#define SCB_NSACR_CP5_Pos                   5U                                            /*!< SCB NSACR: CP5 Position */\n#define SCB_NSACR_CP5_Msk                  (1UL << SCB_NSACR_CP5_Pos)                     /*!< SCB NSACR: CP5 Mask */\n\n#define SCB_NSACR_CP4_Pos                   4U                                            /*!< SCB NSACR: CP4 Position */\n#define SCB_NSACR_CP4_Msk                  (1UL << SCB_NSACR_CP4_Pos)                     /*!< SCB NSACR: CP4 Mask */\n\n#define SCB_NSACR_CP3_Pos                   3U                                            /*!< SCB NSACR: CP3 Position */\n#define SCB_NSACR_CP3_Msk                  (1UL << SCB_NSACR_CP3_Pos)                     /*!< SCB NSACR: CP3 Mask */\n\n#define SCB_NSACR_CP2_Pos                   2U                                            /*!< SCB NSACR: CP2 Position */\n#define SCB_NSACR_CP2_Msk                  (1UL << SCB_NSACR_CP2_Pos)                     /*!< SCB NSACR: CP2 Mask */\n\n#define SCB_NSACR_CP1_Pos                   1U                                            /*!< SCB NSACR: CP1 Position */\n#define SCB_NSACR_CP1_Msk                  (1UL << SCB_NSACR_CP1_Pos)                     /*!< SCB NSACR: CP1 Mask */\n\n#define SCB_NSACR_CP0_Pos                   0U                                            /*!< SCB NSACR: CP0 Position */\n#define SCB_NSACR_CP0_Msk                  (1UL /*<< SCB_NSACR_CP0_Pos*/)                 /*!< SCB NSACR: CP0 Mask */\n\n/* SCB Debug Feature Register 0 Definitions */\n#define SCB_ID_DFR_UDE_Pos                 28U                                            /*!< SCB ID_DFR: UDE Position */\n#define SCB_ID_DFR_UDE_Msk                 (0xFUL << SCB_ID_DFR_UDE_Pos)                  /*!< SCB ID_DFR: UDE Mask */\n\n#define SCB_ID_DFR_MProfDbg_Pos            20U                                            /*!< SCB ID_DFR: MProfDbg Position */\n#define SCB_ID_DFR_MProfDbg_Msk            (0xFUL << SCB_ID_DFR_MProfDbg_Pos)             /*!< SCB ID_DFR: MProfDbg Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB RAS Fault Status Register Definitions */\n#define SCB_RFSR_V_Pos                     31U                                            /*!< SCB RFSR: V Position */\n#define SCB_RFSR_V_Msk                     (1UL << SCB_RFSR_V_Pos)                        /*!< SCB RFSR: V Mask */\n\n#define SCB_RFSR_IS_Pos                    16U                                            /*!< SCB RFSR: IS Position */\n#define SCB_RFSR_IS_Msk                    (0x7FFFUL << SCB_RFSR_IS_Pos)                  /*!< SCB RFSR: IS Mask */\n\n#define SCB_RFSR_UET_Pos                    0U                                            /*!< SCB RFSR: UET Position */\n#define SCB_RFSR_UET_Msk                   (3UL /*<< SCB_RFSR_UET_Pos*/)                  /*!< SCB RFSR: UET Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ICB Implementation Control Block register (ICB)\n  \\brief    Type definitions for the Implementation Control Block Register\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Implementation Control Block (ICB).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} ICB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define ICB_ACTLR_DISCRITAXIRUW_Pos     27U                                               /*!< ACTLR: DISCRITAXIRUW Position */\n#define ICB_ACTLR_DISCRITAXIRUW_Msk     (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)              /*!< ACTLR: DISCRITAXIRUW Mask */\n\n#define ICB_ACTLR_DISDI_Pos             16U                                               /*!< ACTLR: DISDI Position */\n#define ICB_ACTLR_DISDI_Msk             (3UL << ICB_ACTLR_DISDI_Pos)                      /*!< ACTLR: DISDI Mask */\n\n#define ICB_ACTLR_DISCRITAXIRUR_Pos     15U                                               /*!< ACTLR: DISCRITAXIRUR Position */\n#define ICB_ACTLR_DISCRITAXIRUR_Msk     (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)              /*!< ACTLR: DISCRITAXIRUR Mask */\n\n#define ICB_ACTLR_EVENTBUSEN_Pos        14U                                               /*!< ACTLR: EVENTBUSEN Position */\n#define ICB_ACTLR_EVENTBUSEN_Msk        (1UL << ICB_ACTLR_EVENTBUSEN_Pos)                 /*!< ACTLR: EVENTBUSEN Mask */\n\n#define ICB_ACTLR_EVENTBUSEN_S_Pos      13U                                               /*!< ACTLR: EVENTBUSEN_S Position */\n#define ICB_ACTLR_EVENTBUSEN_S_Msk      (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)               /*!< ACTLR: EVENTBUSEN_S Mask */\n\n#define ICB_ACTLR_DISITMATBFLUSH_Pos    12U                                               /*!< ACTLR: DISITMATBFLUSH Position */\n#define ICB_ACTLR_DISITMATBFLUSH_Msk    (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)             /*!< ACTLR: DISITMATBFLUSH Mask */\n\n#define ICB_ACTLR_DISNWAMODE_Pos        11U                                               /*!< ACTLR: DISNWAMODE Position */\n#define ICB_ACTLR_DISNWAMODE_Msk        (1UL << ICB_ACTLR_DISNWAMODE_Pos)                 /*!< ACTLR: DISNWAMODE Mask */\n\n#define ICB_ACTLR_FPEXCODIS_Pos         10U                                               /*!< ACTLR: FPEXCODIS Position */\n#define ICB_ACTLR_FPEXCODIS_Msk         (1UL << ICB_ACTLR_FPEXCODIS_Pos)                  /*!< ACTLR: FPEXCODIS Mask */\n\n#define ICB_ACTLR_DISOLAP_Pos            7U                                               /*!< ACTLR: DISOLAP Position */\n#define ICB_ACTLR_DISOLAP_Msk           (1UL << ICB_ACTLR_DISOLAP_Pos)                    /*!< ACTLR: DISOLAP Mask */\n\n#define ICB_ACTLR_DISOLAPS_Pos           6U                                               /*!< ACTLR: DISOLAPS Position */\n#define ICB_ACTLR_DISOLAPS_Msk          (1UL << ICB_ACTLR_DISOLAPS_Pos)                   /*!< ACTLR: DISOLAPS Mask */\n\n#define ICB_ACTLR_DISLOBR_Pos            5U                                               /*!< ACTLR: DISLOBR Position */\n#define ICB_ACTLR_DISLOBR_Msk           (1UL << ICB_ACTLR_DISLOBR_Pos)                    /*!< ACTLR: DISLOBR Mask */\n\n#define ICB_ACTLR_DISLO_Pos              4U                                               /*!< ACTLR: DISLO Position */\n#define ICB_ACTLR_DISLO_Msk             (1UL << ICB_ACTLR_DISLO_Pos)                      /*!< ACTLR: DISLO Mask */\n\n#define ICB_ACTLR_DISLOLEP_Pos           3U                                               /*!< ACTLR: DISLOLEP Position */\n#define ICB_ACTLR_DISLOLEP_Msk          (1UL << ICB_ACTLR_DISLOLEP_Pos)                   /*!< ACTLR: DISLOLEP Mask */\n\n#define ICB_ACTLR_DISFOLD_Pos            2U                                               /*!< ACTLR: DISFOLD Position */\n#define ICB_ACTLR_DISFOLD_Msk           (1UL << ICB_ACTLR_DISFOLD_Pos)                    /*!< ACTLR: DISFOLD Mask */\n\n/* Interrupt Controller Type Register Definitions */\n#define ICB_ICTR_INTLINESNUM_Pos         0U                                               /*!< ICTR: INTLINESNUM Position */\n#define ICB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)           /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_ICB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[27U];\n  __IM  uint32_t ITREAD;                 /*!< Offset: 0xEF0 (R/ )  ITM Integration Read Register */\n        uint32_t RESERVED4[1U];\n  __OM  uint32_t ITWRITE;                /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED6[46U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED7[3U];\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  ITM Device Type Register */\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_ITREAD_AFVALID_Pos              1U                                            /*!< ITM ITREAD: AFVALID Position */\n#define ITM_ITREAD_AFVALID_Msk             (0x1UL << ITM_ITREAD_AFVALID_Pos)              /*!< ITM ITREAD: AFVALID Mask */\n\n#define ITM_ITREAD_ATREADY_Pos              0U                                            /*!< ITM ITREAD: ATREADY Position */\n#define ITM_ITREAD_ATREADY_Msk             (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)          /*!< ITM ITREAD: ATREADY Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_ITWRITE_AFVALID_Pos             1U                                            /*!< ITM ITWRITE: AFVALID Position */\n#define ITM_ITWRITE_AFVALID_Msk            (0x1UL << ITM_ITWRITE_AFVALID_Pos)             /*!< ITM ITWRITE: AFVALID Mask */\n\n#define ITM_ITWRITE_ATREADY_Pos             0U                                            /*!< ITM ITWRITE: ATREADY Position */\n#define ITM_ITWRITE_ATREADY_Msk            (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)         /*!< ITM ITWRITE: ATREADY Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_ITCTRL_IME_Pos                  0U                                            /*!< ITM ITCTRL: IME Position */\n#define ITM_ITCTRL_IME_Msk                 (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)              /*!< ITM ITCTRL: IME Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n  __IOM uint32_t VMASK1;                 /*!< Offset: 0x03C (R/W)  Comparator Value Mask 1 */\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n  __IOM uint32_t VMASK3;                 /*!< Offset: 0x05C (R/W)  Comparator Value Mask 3 */\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED14[968U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Type Architecture Register */\n        uint32_t RESERVED15[3U];\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup MemSysCtl_Type     Memory System Control Registers (IMPLEMENTATION DEFINED)\n  \\brief    Type definitions for the Memory System Control Registers (MEMSYSCTL)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory System Control Registers (MEMSYSCTL).\n */\ntypedef struct\n{\n  __IOM uint32_t MSCR;                   /*!< Offset: 0x000 (R/W)  Memory System Control Register */\n  __IOM uint32_t PFCR;                   /*!< Offset: 0x004 (R/W)  Prefetcher Control Register */\n        uint32_t RESERVED1[2U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x010 (R/W)  ITCM Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x014 (R/W)  DTCM Control Register */\n  __IOM uint32_t PAHBCR;                 /*!< Offset: 0x018 (R/W)  P-AHB Control Register */\n        uint32_t RESERVED2[313U];\n  __IOM uint32_t ITGU_CTRL;              /*!< Offset: 0x500 (R/W)  ITGU Control Register */\n  __IOM uint32_t ITGU_CFG;               /*!< Offset: 0x504 (R/W)  ITGU Configuration Register */\n        uint32_t RESERVED3[2U];\n  __IOM uint32_t ITGU_LUT[16U];          /*!< Offset: 0x510 (R/W)  ITGU Look Up Table Register */\n        uint32_t RESERVED4[44U];\n  __IOM uint32_t DTGU_CTRL;              /*!< Offset: 0x600 (R/W)  DTGU Control Registers */\n  __IOM uint32_t DTGU_CFG;               /*!< Offset: 0x604 (R/W)  DTGU Configuration Register */\n        uint32_t RESERVED5[2U];\n  __IOM uint32_t DTGU_LUT[16U];          /*!< Offset: 0x610 (R/W)  DTGU Look Up Table Register */\n} MemSysCtl_Type;\n\n/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */\n#define MEMSYSCTL_MSCR_CPWRDN_Pos          17U                                         /*!< MEMSYSCTL MSCR: CPWRDN Position */\n#define MEMSYSCTL_MSCR_CPWRDN_Msk          (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)        /*!< MEMSYSCTL MSCR: CPWRDN Mask */\n\n#define MEMSYSCTL_MSCR_DCCLEAN_Pos         16U                                         /*!< MEMSYSCTL MSCR: DCCLEAN Position */\n#define MEMSYSCTL_MSCR_DCCLEAN_Msk         (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)       /*!< MEMSYSCTL MSCR: DCCLEAN Mask */\n\n#define MEMSYSCTL_MSCR_ICACTIVE_Pos        13U                                         /*!< MEMSYSCTL MSCR: ICACTIVE Position */\n#define MEMSYSCTL_MSCR_ICACTIVE_Msk        (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)      /*!< MEMSYSCTL MSCR: ICACTIVE Mask */\n\n#define MEMSYSCTL_MSCR_DCACTIVE_Pos        12U                                         /*!< MEMSYSCTL MSCR: DCACTIVE Position */\n#define MEMSYSCTL_MSCR_DCACTIVE_Msk        (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)      /*!< MEMSYSCTL MSCR: DCACTIVE Mask */\n\n#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos       4U                                         /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */\n#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk      (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos)    /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */\n\n#define MEMSYSCTL_MSCR_EVECCFAULT_Pos       3U                                         /*!< MEMSYSCTL MSCR: EVECCFAULT Position */\n#define MEMSYSCTL_MSCR_EVECCFAULT_Msk      (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)    /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */\n\n#define MEMSYSCTL_MSCR_FORCEWT_Pos          2U                                         /*!< MEMSYSCTL MSCR: FORCEWT Position */\n#define MEMSYSCTL_MSCR_FORCEWT_Msk         (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)       /*!< MEMSYSCTL MSCR: FORCEWT Mask */\n\n#define MEMSYSCTL_MSCR_ECCEN_Pos            1U                                         /*!< MEMSYSCTL MSCR: ECCEN Position */\n#define MEMSYSCTL_MSCR_ECCEN_Msk           (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)         /*!< MEMSYSCTL MSCR: ECCEN Mask */\n\n/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */\n#define MEMSYSCTL_PFCR_MAX_OS_Pos           7U                                         /*!< MEMSYSCTL PFCR: MAX_OS Position */\n#define MEMSYSCTL_PFCR_MAX_OS_Msk          (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos)        /*!< MEMSYSCTL PFCR: MAX_OS Mask */\n\n#define MEMSYSCTL_PFCR_MAX_LA_Pos           4U                                         /*!< MEMSYSCTL PFCR: MAX_LA Position */\n#define MEMSYSCTL_PFCR_MAX_LA_Msk          (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos)        /*!< MEMSYSCTL PFCR: MAX_LA Mask */\n\n#define MEMSYSCTL_PFCR_MIN_LA_Pos           1U                                         /*!< MEMSYSCTL PFCR: MIN_LA Position */\n#define MEMSYSCTL_PFCR_MIN_LA_Msk          (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos)        /*!< MEMSYSCTL PFCR: MIN_LA Mask */\n\n#define MEMSYSCTL_PFCR_ENABLE_Pos           0U                                         /*!< MEMSYSCTL PFCR: ENABLE Position */\n#define MEMSYSCTL_PFCR_ENABLE_Msk          (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)    /*!< MEMSYSCTL PFCR: ENABLE Mask */\n\n/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */\n#define MEMSYSCTL_ITCMCR_SZ_Pos             3U                                         /*!< MEMSYSCTL ITCMCR: SZ Position */\n#define MEMSYSCTL_ITCMCR_SZ_Msk            (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)          /*!< MEMSYSCTL ITCMCR: SZ Mask */\n\n#define MEMSYSCTL_ITCMCR_EN_Pos             0U                                         /*!< MEMSYSCTL ITCMCR: EN Position */\n#define MEMSYSCTL_ITCMCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)      /*!< MEMSYSCTL ITCMCR: EN Mask */\n\n/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */\n#define MEMSYSCTL_DTCMCR_SZ_Pos             3U                                         /*!< MEMSYSCTL DTCMCR: SZ Position */\n#define MEMSYSCTL_DTCMCR_SZ_Msk            (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)          /*!< MEMSYSCTL DTCMCR: SZ Mask */\n\n#define MEMSYSCTL_DTCMCR_EN_Pos             0U                                         /*!< MEMSYSCTL DTCMCR: EN Position */\n#define MEMSYSCTL_DTCMCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)      /*!< MEMSYSCTL DTCMCR: EN Mask */\n\n/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */\n#define MEMSYSCTL_PAHBCR_SZ_Pos             1U                                         /*!< MEMSYSCTL PAHBCR: SZ Position */\n#define MEMSYSCTL_PAHBCR_SZ_Msk            (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)          /*!< MEMSYSCTL PAHBCR: SZ Mask */\n\n#define MEMSYSCTL_PAHBCR_EN_Pos             0U                                         /*!< MEMSYSCTL PAHBCR: EN Position */\n#define MEMSYSCTL_PAHBCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)      /*!< MEMSYSCTL PAHBCR: EN Mask */\n\n/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */\n#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos       1U                                         /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */\n#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk      (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)    /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */\n\n#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos       0U                                         /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */\n#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk      (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */\n\n/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */\n#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos     31U                                         /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */\n#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk     (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)   /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */\n\n#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos      8U                                         /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */\n#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk     (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)   /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */\n\n#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos        0U                                         /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */\n#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk       (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */\n\n/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */\n#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos       1U                                         /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */\n#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk      (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)    /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */\n\n#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos       0U                                         /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */\n#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk      (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */\n\n/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */\n#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos     31U                                         /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */\n#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk     (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)   /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */\n\n#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos      8U                                         /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */\n#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk     (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)   /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */\n\n#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos        0U                                         /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */\n#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk       (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */\n\n\n/*@}*/ /* end of group MemSysCtl_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup PwrModCtl_Type     Power Mode Control Registers\n  \\brief    Type definitions for the Power Mode Control Registers (PWRMODCTL)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Power Mode Control Registers (PWRMODCTL).\n */\ntypedef struct\n{\n  __IOM uint32_t CPDLPSTATE;             /*!< Offset: 0x000 (R/W)  Core Power Domain Low Power State Register */\n  __IOM uint32_t DPDLPSTATE;             /*!< Offset: 0x004 (R/W)  Debug Power Domain Low Power State Register */\n} PwrModCtl_Type;\n\n/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */\n#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U                                              /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */\n#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk  (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)     /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */\n\n#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U                                              /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */\n#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk  (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)     /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */\n\n#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U                                              /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */\n#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */\n\n/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */\n#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U                                              /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */\n#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk  (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */\n\n/*@}*/ /* end of group PwrModCtl_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup EWIC_Type     External Wakeup Interrupt Controller Registers\n  \\brief    Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).\n */\ntypedef struct\n{\n  __IOM uint32_t EWIC_CR;                /*!< Offset: 0x000 (R/W)  EWIC Control Register */\n  __IOM uint32_t EWIC_ASCR;              /*!< Offset: 0x004 (R/W)  EWIC Automatic Sequence Control Register */\n  __OM  uint32_t EWIC_CLRMASK;           /*!< Offset: 0x008 ( /W)  EWIC Clear Mask Register */\n  __IM  uint32_t EWIC_NUMID;             /*!< Offset: 0x00C (R/ )  EWIC Event Number ID Register */\n        uint32_t RESERVED0[124U];\n  __IOM uint32_t EWIC_MASKA;             /*!< Offset: 0x200 (R/W)  EWIC MaskA Register */\n  __IOM uint32_t EWIC_MASKn[15];         /*!< Offset: 0x204 (R/W)  EWIC Maskn Registers */\n        uint32_t RESERVED1[112U];\n  __IM  uint32_t EWIC_PENDA;             /*!< Offset: 0x400 (R/ )  EWIC PendA Event Register */\n  __IOM uint32_t EWIC_PENDn[15];         /*!< Offset: 0x404 (R/W)  EWIC Pendn Event Registers */\n        uint32_t RESERVED2[112U];\n  __IM  uint32_t EWIC_PSR;               /*!< Offset: 0x600 (R/ )  EWIC Pend Summary Register */\n} EWIC_Type;\n\n/* EWIC Control (EWIC_CR) Register Definitions */\n#define EWIC_EWIC_CR_EN_Pos                 0U                                         /*!< EWIC EWIC_CR: EN Position */\n#define EWIC_EWIC_CR_EN_Msk                (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/)          /*!< EWIC EWIC_CR: EN Mask */\n\n/* EWIC Automatic Sequence Control (EWIC_ASCR) Register Definitions */\n#define EWIC_EWIC_ASCR_ASPU_Pos             1U                                         /*!< EWIC EWIC_ASCR: ASPU Position */\n#define EWIC_EWIC_ASCR_ASPU_Msk            (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos)          /*!< EWIC EWIC_ASCR: ASPU Mask */\n\n#define EWIC_EWIC_ASCR_ASPD_Pos             0U                                         /*!< EWIC EWIC_ASCR: ASPD Position */\n#define EWIC_EWIC_ASCR_ASPD_Msk            (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/)      /*!< EWIC EWIC_ASCR: ASPD Mask */\n\n/* EWIC Event Number ID (EWIC_NUMID) Register Definitions */\n#define EWIC_EWIC_NUMID_NUMEVENT_Pos        0U                                         /*!< EWIC_NUMID: NUMEVENT Position */\n#define EWIC_EWIC_NUMID_NUMEVENT_Msk       (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */\n\n/* EWIC Mask A (EWIC_MASKA) Register Definitions */\n#define EWIC_EWIC_MASKA_EDBGREQ_Pos         2U                                         /*!< EWIC EWIC_MASKA: EDBGREQ Position */\n#define EWIC_EWIC_MASKA_EDBGREQ_Msk        (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos)      /*!< EWIC EWIC_MASKA: EDBGREQ Mask */\n\n#define EWIC_EWIC_MASKA_NMI_Pos             1U                                         /*!< EWIC EWIC_MASKA: NMI Position */\n#define EWIC_EWIC_MASKA_NMI_Msk            (0x1UL << EWIC_EWIC_MASKA_NMI_Pos)          /*!< EWIC EWIC_MASKA: NMI Mask */\n\n#define EWIC_EWIC_MASKA_EVENT_Pos           0U                                         /*!< EWIC EWIC_MASKA: EVENT Position */\n#define EWIC_EWIC_MASKA_EVENT_Msk          (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/)    /*!< EWIC EWIC_MASKA: EVENT Mask */\n\n/* EWIC Mask n (EWIC_MASKn) Register Definitions */\n#define EWIC_EWIC_MASKn_IRQ_Pos             0U                                           /*!< EWIC EWIC_MASKn: IRQ Position */\n#define EWIC_EWIC_MASKn_IRQ_Msk            (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */\n\n/* EWIC Pend A (EWIC_PENDA) Register Definitions */\n#define EWIC_EWIC_PENDA_EDBGREQ_Pos         2U                                         /*!< EWIC EWIC_PENDA: EDBGREQ Position */\n#define EWIC_EWIC_PENDA_EDBGREQ_Msk        (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos)      /*!< EWIC EWIC_PENDA: EDBGREQ Mask */\n\n#define EWIC_EWIC_PENDA_NMI_Pos             1U                                         /*!< EWIC EWIC_PENDA: NMI Position */\n#define EWIC_EWIC_PENDA_NMI_Msk            (0x1UL << EWIC_EWIC_PENDA_NMI_Pos)          /*!< EWIC EWIC_PENDA: NMI Mask */\n\n#define EWIC_EWIC_PENDA_EVENT_Pos           0U                                         /*!< EWIC EWIC_PENDA: EVENT Position */\n#define EWIC_EWIC_PENDA_EVENT_Msk          (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/)    /*!< EWIC EWIC_PENDA: EVENT Mask */\n\n/* EWIC Pend n (EWIC_PENDn) Register Definitions */\n#define EWIC_EWIC_PENDn_IRQ_Pos             0U                                           /*!< EWIC EWIC_PENDn: IRQ Position */\n#define EWIC_EWIC_PENDn_IRQ_Msk            (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */\n\n/* EWIC Pend Summary (EWIC_PSR) Register Definitions */\n#define EWIC_EWIC_PSR_NZ_Pos                1U                                         /*!< EWIC EWIC_PSR: NZ Position */\n#define EWIC_EWIC_PSR_NZ_Msk               (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos)          /*!< EWIC EWIC_PSR: NZ Mask */\n\n#define EWIC_EWIC_PSR_NZA_Pos               0U                                         /*!< EWIC EWIC_PSR: NZA Position */\n#define EWIC_EWIC_PSR_NZA_Msk              (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/)        /*!< EWIC EWIC_PSR: NZA Mask */\n\n/*@}*/ /* end of group EWIC_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup EWIC_ISA_Type     External Wakeup Interrupt Controller (EWIC) interrupt status access registers\n  \\brief    Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA).\n */\ntypedef struct\n{\n  __OM  uint32_t EVENTSPR;               /*!< Offset: 0x000 ( /W)  Event Set Pending Register */\n        uint32_t RESERVED0[31U];\n  __IM  uint32_t EVENTMASKA;             /*!< Offset: 0x080 (R/ )  Event Mask A Register */\n  __IM  uint32_t EVENTMASKn[15];         /*!< Offset: 0x084 (R/ )  Event Mask Register */\n} EWIC_ISA_Type;\n\n/* EWIC_ISA Event Set Pending (EVENTSPR) Register Definitions */\n#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos       2U                                         /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */\n#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk      (0x1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos)    /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */\n\n#define EWIC_ISA_EVENTSPR_NMI_Pos           1U                                         /*!< EWIC_ISA EVENTSPR: NMI Position */\n#define EWIC_ISA_EVENTSPR_NMI_Msk          (0x1UL << EWIC_ISA_EVENTSPR_NMI_Pos)        /*!< EWIC_ISA EVENTSPR: NMI Mask */\n\n#define EWIC_ISA_EVENTSPR_EVENT_Pos         0U                                         /*!< EWIC_ISA EVENTSPR: EVENT Position */\n#define EWIC_ISA_EVENTSPR_EVENT_Msk        (0x1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/)  /*!< EWIC_ISA EVENTSPR: EVENT Mask */\n\n/* EWIC_ISA Event Mask A (EVENTMASKA) Register Definitions */\n#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos     2U                                         /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */\n#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk    (0x1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos)  /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */\n\n#define EWIC_ISA_EVENTMASKA_NMI_Pos         1U                                         /*!< EWIC_ISA EVENTMASKA: NMI Position */\n#define EWIC_ISA_EVENTMASKA_NMI_Msk        (0x1UL << EWIC_ISA_EVENTMASKA_NMI_Pos)      /*!< EWIC_ISA EVENTMASKA: NMI Mask */\n\n#define EWIC_ISA_EVENTMASKA_EVENT_Pos       0U                                               /*!< EWIC_ISA EVENTMASKA: EVENT Position */\n#define EWIC_ISA_EVENTMASKA_EVENT_Msk      (0x1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/)      /*!< EWIC_ISA EVENTMASKA: EVENT Mask */\n\n/* EWIC_ISA Event Mask n (EVENTMASKn) Register Definitions */\n#define EWIC_ISA_EVENTMASKn_IRQ_Pos         0U                                               /*!< EWIC_ISA EVENTMASKn: IRQ Position */\n#define EWIC_ISA_EVENTMASKn_IRQ_Msk        (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/) /*!< EWIC_ISA EVENTMASKn: IRQ Mask */\n\n/*@}*/ /* end of group EWIC_ISA_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup ErrBnk_Type     Error Banking Registers (IMPLEMENTATION DEFINED)\n  \\brief    Type definitions for the Error Banking Registers (ERRBNK)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Error Banking Registers (ERRBNK).\n */\ntypedef struct\n{\n  __IOM uint32_t IEBR0;                  /*!< Offset: 0x000 (R/W)  Instruction Cache Error Bank Register 0 */\n  __IOM uint32_t IEBR1;                  /*!< Offset: 0x004 (R/W)  Instruction Cache Error Bank Register 1 */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t DEBR0;                  /*!< Offset: 0x010 (R/W)  Data Cache Error Bank Register 0 */\n  __IOM uint32_t DEBR1;                  /*!< Offset: 0x014 (R/W)  Data Cache Error Bank Register 1 */\n        uint32_t RESERVED1[2U];\n  __IOM uint32_t TEBR0;                  /*!< Offset: 0x020 (R/W)  TCM Error Bank Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t TEBR1;                  /*!< Offset: 0x028 (R/W)  TCM Error Bank Register 1 */\n} ErrBnk_Type;\n\n/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */\n#define ERRBNK_IEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK IEBR0: SWDEF Position */\n#define ERRBNK_IEBR0_SWDEF_Msk             (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)           /*!< ERRBNK IEBR0: SWDEF Mask */\n\n#define ERRBNK_IEBR0_BANK_Pos              16U                                         /*!< ERRBNK IEBR0: BANK Position */\n#define ERRBNK_IEBR0_BANK_Msk              (0x1UL << ERRBNK_IEBR0_BANK_Pos)            /*!< ERRBNK IEBR0: BANK Mask */\n\n#define ERRBNK_IEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK IEBR0: LOCATION Position */\n#define ERRBNK_IEBR0_LOCATION_Msk          (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)     /*!< ERRBNK IEBR0: LOCATION Mask */\n\n#define ERRBNK_IEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK IEBR0: LOCKED Position */\n#define ERRBNK_IEBR0_LOCKED_Msk            (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)          /*!< ERRBNK IEBR0: LOCKED Mask */\n\n#define ERRBNK_IEBR0_VALID_Pos              0U                                         /*!< ERRBNK IEBR0: VALID Position */\n#define ERRBNK_IEBR0_VALID_Msk             (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)       /*!< ERRBNK IEBR0: VALID Mask */\n\n/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */\n#define ERRBNK_IEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK IEBR1: SWDEF Position */\n#define ERRBNK_IEBR1_SWDEF_Msk             (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)           /*!< ERRBNK IEBR1: SWDEF Mask */\n\n#define ERRBNK_IEBR1_BANK_Pos              16U                                         /*!< ERRBNK IEBR1: BANK Position */\n#define ERRBNK_IEBR1_BANK_Msk              (0x1UL << ERRBNK_IEBR1_BANK_Pos)            /*!< ERRBNK IEBR1: BANK Mask */\n\n#define ERRBNK_IEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK IEBR1: LOCATION Position */\n#define ERRBNK_IEBR1_LOCATION_Msk          (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)     /*!< ERRBNK IEBR1: LOCATION Mask */\n\n#define ERRBNK_IEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK IEBR1: LOCKED Position */\n#define ERRBNK_IEBR1_LOCKED_Msk            (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)          /*!< ERRBNK IEBR1: LOCKED Mask */\n\n#define ERRBNK_IEBR1_VALID_Pos              0U                                         /*!< ERRBNK IEBR1: VALID Position */\n#define ERRBNK_IEBR1_VALID_Msk             (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)       /*!< ERRBNK IEBR1: VALID Mask */\n\n/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */\n#define ERRBNK_DEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK DEBR0: SWDEF Position */\n#define ERRBNK_DEBR0_SWDEF_Msk             (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)           /*!< ERRBNK DEBR0: SWDEF Mask */\n\n#define ERRBNK_DEBR0_TYPE_Pos              17U                                         /*!< ERRBNK DEBR0: TYPE Position */\n#define ERRBNK_DEBR0_TYPE_Msk              (0x1UL << ERRBNK_DEBR0_TYPE_Pos)            /*!< ERRBNK DEBR0: TYPE Mask */\n\n#define ERRBNK_DEBR0_BANK_Pos              16U                                         /*!< ERRBNK DEBR0: BANK Position */\n#define ERRBNK_DEBR0_BANK_Msk              (0x1UL << ERRBNK_DEBR0_BANK_Pos)            /*!< ERRBNK DEBR0: BANK Mask */\n\n#define ERRBNK_DEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK DEBR0: LOCATION Position */\n#define ERRBNK_DEBR0_LOCATION_Msk          (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)     /*!< ERRBNK DEBR0: LOCATION Mask */\n\n#define ERRBNK_DEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK DEBR0: LOCKED Position */\n#define ERRBNK_DEBR0_LOCKED_Msk            (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)          /*!< ERRBNK DEBR0: LOCKED Mask */\n\n#define ERRBNK_DEBR0_VALID_Pos              0U                                         /*!< ERRBNK DEBR0: VALID Position */\n#define ERRBNK_DEBR0_VALID_Msk             (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)       /*!< ERRBNK DEBR0: VALID Mask */\n\n/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */\n#define ERRBNK_DEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK DEBR1: SWDEF Position */\n#define ERRBNK_DEBR1_SWDEF_Msk             (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)           /*!< ERRBNK DEBR1: SWDEF Mask */\n\n#define ERRBNK_DEBR1_TYPE_Pos              17U                                         /*!< ERRBNK DEBR1: TYPE Position */\n#define ERRBNK_DEBR1_TYPE_Msk              (0x1UL << ERRBNK_DEBR1_TYPE_Pos)            /*!< ERRBNK DEBR1: TYPE Mask */\n\n#define ERRBNK_DEBR1_BANK_Pos              16U                                         /*!< ERRBNK DEBR1: BANK Position */\n#define ERRBNK_DEBR1_BANK_Msk              (0x1UL << ERRBNK_DEBR1_BANK_Pos)            /*!< ERRBNK DEBR1: BANK Mask */\n\n#define ERRBNK_DEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK DEBR1: LOCATION Position */\n#define ERRBNK_DEBR1_LOCATION_Msk          (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)     /*!< ERRBNK DEBR1: LOCATION Mask */\n\n#define ERRBNK_DEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK DEBR1: LOCKED Position */\n#define ERRBNK_DEBR1_LOCKED_Msk            (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)          /*!< ERRBNK DEBR1: LOCKED Mask */\n\n#define ERRBNK_DEBR1_VALID_Pos              0U                                         /*!< ERRBNK DEBR1: VALID Position */\n#define ERRBNK_DEBR1_VALID_Msk             (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)       /*!< ERRBNK DEBR1: VALID Mask */\n\n/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */\n#define ERRBNK_TEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK TEBR0: SWDEF Position */\n#define ERRBNK_TEBR0_SWDEF_Msk             (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)           /*!< ERRBNK TEBR0: SWDEF Mask */\n\n#define ERRBNK_TEBR0_POISON_Pos            28U                                         /*!< ERRBNK TEBR0: POISON Position */\n#define ERRBNK_TEBR0_POISON_Msk            (0x1UL << ERRBNK_TEBR0_POISON_Pos)          /*!< ERRBNK TEBR0: POISON Mask */\n\n#define ERRBNK_TEBR0_TYPE_Pos              27U                                         /*!< ERRBNK TEBR0: TYPE Position */\n#define ERRBNK_TEBR0_TYPE_Msk              (0x1UL << ERRBNK_TEBR0_TYPE_Pos)            /*!< ERRBNK TEBR0: TYPE Mask */\n\n#define ERRBNK_TEBR0_BANK_Pos              24U                                         /*!< ERRBNK TEBR0: BANK Position */\n#define ERRBNK_TEBR0_BANK_Msk              (0x7UL << ERRBNK_TEBR0_BANK_Pos)            /*!< ERRBNK TEBR0: BANK Mask */\n\n#define ERRBNK_TEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK TEBR0: LOCATION Position */\n#define ERRBNK_TEBR0_LOCATION_Msk          (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)   /*!< ERRBNK TEBR0: LOCATION Mask */\n\n#define ERRBNK_TEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK TEBR0: LOCKED Position */\n#define ERRBNK_TEBR0_LOCKED_Msk            (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)          /*!< ERRBNK TEBR0: LOCKED Mask */\n\n#define ERRBNK_TEBR0_VALID_Pos              0U                                         /*!< ERRBNK TEBR0: VALID Position */\n#define ERRBNK_TEBR0_VALID_Msk             (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)       /*!< ERRBNK TEBR0: VALID Mask */\n\n/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */\n#define ERRBNK_TEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK TEBR1: SWDEF Position */\n#define ERRBNK_TEBR1_SWDEF_Msk             (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)           /*!< ERRBNK TEBR1: SWDEF Mask */\n\n#define ERRBNK_TEBR1_POISON_Pos            28U                                         /*!< ERRBNK TEBR1: POISON Position */\n#define ERRBNK_TEBR1_POISON_Msk            (0x1UL << ERRBNK_TEBR1_POISON_Pos)          /*!< ERRBNK TEBR1: POISON Mask */\n\n#define ERRBNK_TEBR1_TYPE_Pos              27U                                         /*!< ERRBNK TEBR1: TYPE Position */\n#define ERRBNK_TEBR1_TYPE_Msk              (0x1UL << ERRBNK_TEBR1_TYPE_Pos)            /*!< ERRBNK TEBR1: TYPE Mask */\n\n#define ERRBNK_TEBR1_BANK_Pos              24U                                         /*!< ERRBNK TEBR1: BANK Position */\n#define ERRBNK_TEBR1_BANK_Msk              (0x7UL << ERRBNK_TEBR1_BANK_Pos)            /*!< ERRBNK TEBR1: BANK Mask */\n\n#define ERRBNK_TEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK TEBR1: LOCATION Position */\n#define ERRBNK_TEBR1_LOCATION_Msk          (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)   /*!< ERRBNK TEBR1: LOCATION Mask */\n\n#define ERRBNK_TEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK TEBR1: LOCKED Position */\n#define ERRBNK_TEBR1_LOCKED_Msk            (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)          /*!< ERRBNK TEBR1: LOCKED Mask */\n\n#define ERRBNK_TEBR1_VALID_Pos              0U                                         /*!< ERRBNK TEBR1: VALID Position */\n#define ERRBNK_TEBR1_VALID_Msk             (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)       /*!< ERRBNK TEBR1: VALID Mask */\n\n/*@}*/ /* end of group ErrBnk_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup PrcCfgInf_Type     Processor Configuration Information Registers (IMPLEMENTATION DEFINED)\n  \\brief    Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Processor Configuration Information Registerss (PRCCFGINF).\n */\ntypedef struct\n{\n  __OM  uint32_t CFGINFOSEL;             /*!< Offset: 0x000 ( /W)  Processor Configuration Information Selection Register */\n  __IM  uint32_t CFGINFORD;              /*!< Offset: 0x004 (R/ )  Processor Configuration Information Read Data Register */\n} PrcCfgInf_Type;\n\n/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */\n\n/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */\n\n/*@}*/ /* end of group PrcCfgInf_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup STL_Type     Software Test Library Observation Registers\n  \\brief    Type definitions for the Software Test Library Observation Registerss (STL)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Software Test Library Observation Registerss (STL).\n */\ntypedef struct\n{\n  __IM  uint32_t STLNVICPENDOR;          /*!< Offset: 0x000 (R/ )  NVIC Pending Priority Tree Register */\n  __IM  uint32_t STLNVICACTVOR;          /*!< Offset: 0x004 (R/ )  NVIC Active Priority Tree Register */\n        uint32_t RESERVED0[2U];\n  __OM  uint32_t STLIDMPUSR;             /*!< Offset: 0x010 ( /W)  MPU Sample Register */\n  __IM  uint32_t STLIMPUOR;              /*!< Offset: 0x014 (R/ )  MPU Region Hit Register */\n  __IM  uint32_t STLD0MPUOR;             /*!< Offset: 0x018 (R/ )  MPU Memory Attributes Register 0 */\n  __IM  uint32_t STLD1MPUOR;             /*!< Offset: 0x01C (R/ )  MPU Memory Attributes Register 1 */\n\n} STL_Type;\n\n/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */\n#define STL_STLNVICPENDOR_VALID_Pos        18U                                         /*!< STL STLNVICPENDOR: VALID Position */\n#define STL_STLNVICPENDOR_VALID_Msk        (0x1UL << STL_STLNVICPENDOR_VALID_Pos)      /*!< STL STLNVICPENDOR: VALID Mask */\n\n#define STL_STLNVICPENDOR_TARGET_Pos       17U                                         /*!< STL STLNVICPENDOR: TARGET Position */\n#define STL_STLNVICPENDOR_TARGET_Msk       (0x1UL << STL_STLNVICPENDOR_TARGET_Pos)     /*!< STL STLNVICPENDOR: TARGET Mask */\n\n#define STL_STLNVICPENDOR_PRIORITY_Pos      9U                                         /*!< STL STLNVICPENDOR: PRIORITY Position */\n#define STL_STLNVICPENDOR_PRIORITY_Msk     (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos)  /*!< STL STLNVICPENDOR: PRIORITY Mask */\n\n#define STL_STLNVICPENDOR_INTNUM_Pos        0U                                         /*!< STL STLNVICPENDOR: INTNUM Position */\n#define STL_STLNVICPENDOR_INTNUM_Msk       (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */\n\n/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */\n#define STL_STLNVICACTVOR_VALID_Pos        18U                                         /*!< STL STLNVICACTVOR: VALID Position */\n#define STL_STLNVICACTVOR_VALID_Msk        (0x1UL << STL_STLNVICACTVOR_VALID_Pos)      /*!< STL STLNVICACTVOR: VALID Mask */\n\n#define STL_STLNVICACTVOR_TARGET_Pos       17U                                         /*!< STL STLNVICACTVOR: TARGET Position */\n#define STL_STLNVICACTVOR_TARGET_Msk       (0x1UL << STL_STLNVICACTVOR_TARGET_Pos)     /*!< STL STLNVICACTVOR: TARGET Mask */\n\n#define STL_STLNVICACTVOR_PRIORITY_Pos      9U                                         /*!< STL STLNVICACTVOR: PRIORITY Position */\n#define STL_STLNVICACTVOR_PRIORITY_Msk     (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos)  /*!< STL STLNVICACTVOR: PRIORITY Mask */\n\n#define STL_STLNVICACTVOR_INTNUM_Pos        0U                                         /*!< STL STLNVICACTVOR: INTNUM Position */\n#define STL_STLNVICACTVOR_INTNUM_Msk       (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */\n\n/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */\n#define STL_STLIDMPUSR_ADDR_Pos             5U                                         /*!< STL STLIDMPUSR: ADDR Position */\n#define STL_STLIDMPUSR_ADDR_Msk            (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos)    /*!< STL STLIDMPUSR: ADDR Mask */\n\n#define STL_STLIDMPUSR_INSTR_Pos            2U                                         /*!< STL STLIDMPUSR: INSTR Position */\n#define STL_STLIDMPUSR_INSTR_Msk           (0x1UL << STL_STLIDMPUSR_INSTR_Pos)         /*!< STL STLIDMPUSR: INSTR Mask */\n\n#define STL_STLIDMPUSR_DATA_Pos             1U                                         /*!< STL STLIDMPUSR: DATA Position */\n#define STL_STLIDMPUSR_DATA_Msk            (0x1UL << STL_STLIDMPUSR_DATA_Pos)          /*!< STL STLIDMPUSR: DATA Mask */\n\n/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */\n#define STL_STLIMPUOR_HITREGION_Pos         9U                                         /*!< STL STLIMPUOR: HITREGION Position */\n#define STL_STLIMPUOR_HITREGION_Msk        (0xFFUL << STL_STLIMPUOR_HITREGION_Pos)     /*!< STL STLIMPUOR: HITREGION Mask */\n\n#define STL_STLIMPUOR_ATTR_Pos              0U                                         /*!< STL STLIMPUOR: ATTR Position */\n#define STL_STLIMPUOR_ATTR_Msk             (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/)     /*!< STL STLIMPUOR: ATTR Mask */\n\n/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */\n#define STL_STLD0MPUOR_HITREGION_Pos        9U                                         /*!< STL STLD0MPUOR: HITREGION Position */\n#define STL_STLD0MPUOR_HITREGION_Msk       (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos)    /*!< STL STLD0MPUOR: HITREGION Mask */\n\n#define STL_STLD0MPUOR_ATTR_Pos             0U                                         /*!< STL STLD0MPUOR: ATTR Position */\n#define STL_STLD0MPUOR_ATTR_Msk            (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/)    /*!< STL STLD0MPUOR: ATTR Mask */\n\n/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */\n#define STL_STLD1MPUOR_HITREGION_Pos        9U                                         /*!< STL STLD1MPUOR: HITREGION Position */\n#define STL_STLD1MPUOR_HITREGION_Msk       (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos)    /*!< STL STLD1MPUOR: HITREGION Mask */\n\n#define STL_STLD1MPUOR_ATTR_Pos             0U                                         /*!< STL STLD1MPUOR: ATTR Position */\n#define STL_STLD1MPUOR_ATTR_Msk            (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/)    /*!< STL STLD1MPUOR: ATTR Mask */\n\n/*@}*/ /* end of group STL_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFmt_Pos                  0U                                         /*!< TPI FFCR: EnFmt Position */\n#define TPI_FFCR_EnFmt_Msk                 (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)           /*!< TPI FFCR: EnFmt Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_PMU     Performance Monitoring Unit (PMU)\n  \\brief    Type definitions for the Performance Monitoring Unit (PMU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Performance Monitoring Unit (PMU).\n */\ntypedef struct\n{\n  __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT];        /*!< Offset: 0x0 (R/W)    PMU Event Counter Registers */\n#if __PMU_NUM_EVENTCNT<31\n        uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];\n#endif\n  __IOM uint32_t CCNTR;                             /*!< Offset: 0x7C (R/W)   PMU Cycle Counter Register */\n        uint32_t RESERVED1[224];\n  __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT];       /*!< Offset: 0x400 (R/W)  PMU Event Type and Filter Registers */\n#if __PMU_NUM_EVENTCNT<31\n        uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];\n#endif\n  __IOM uint32_t CCFILTR;                           /*!< Offset: 0x47C (R/W)  PMU Cycle Counter Filter Register */\n        uint32_t RESERVED3[480];\n  __IOM uint32_t CNTENSET;                          /*!< Offset: 0xC00 (R/W)  PMU Count Enable Set Register */\n        uint32_t RESERVED4[7];\n  __IOM uint32_t CNTENCLR;                          /*!< Offset: 0xC20 (R/W)  PMU Count Enable Clear Register */\n        uint32_t RESERVED5[7];\n  __IOM uint32_t INTENSET;                          /*!< Offset: 0xC40 (R/W)  PMU Interrupt Enable Set Register */\n        uint32_t RESERVED6[7];\n  __IOM uint32_t INTENCLR;                          /*!< Offset: 0xC60 (R/W)  PMU Interrupt Enable Clear Register */\n        uint32_t RESERVED7[7];\n  __IOM uint32_t OVSCLR;                            /*!< Offset: 0xC80 (R/W)  PMU Overflow Flag Status Clear Register */\n        uint32_t RESERVED8[7];\n  __IOM uint32_t SWINC;                             /*!< Offset: 0xCA0 (R/W)  PMU Software Increment Register */\n        uint32_t RESERVED9[7];\n  __IOM uint32_t OVSSET;                            /*!< Offset: 0xCC0 (R/W)  PMU Overflow Flag Status Set Register */\n        uint32_t RESERVED10[79];\n  __IOM uint32_t TYPE;                              /*!< Offset: 0xE00 (R/W)  PMU Type Register */\n  __IOM uint32_t CTRL;                              /*!< Offset: 0xE04 (R/W)  PMU Control Register */\n        uint32_t RESERVED11[108];\n  __IOM uint32_t AUTHSTATUS;                        /*!< Offset: 0xFB8 (R/W)  PMU Authentication Status Register */\n  __IOM uint32_t DEVARCH;                           /*!< Offset: 0xFBC (R/W)  PMU Device Architecture Register */\n        uint32_t RESERVED12[3];\n  __IOM uint32_t DEVTYPE;                           /*!< Offset: 0xFCC (R/W)  PMU Device Type Register */\n  __IOM uint32_t PIDR4;                             /*!< Offset: 0xFD0 (R/W)  PMU Peripheral Identification Register 4 */\n        uint32_t RESERVED13[3];\n  __IOM uint32_t PIDR0;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 0 */\n  __IOM uint32_t PIDR1;                             /*!< Offset: 0xFE4 (R/W)  PMU Peripheral Identification Register 1 */\n  __IOM uint32_t PIDR2;                             /*!< Offset: 0xFE8 (R/W)  PMU Peripheral Identification Register 2 */\n  __IOM uint32_t PIDR3;                             /*!< Offset: 0xFEC (R/W)  PMU Peripheral Identification Register 3 */\n  __IOM uint32_t CIDR0;                             /*!< Offset: 0xFF0 (R/W)  PMU Component Identification Register 0 */\n  __IOM uint32_t CIDR1;                             /*!< Offset: 0xFF4 (R/W)  PMU Component Identification Register 1 */\n  __IOM uint32_t CIDR2;                             /*!< Offset: 0xFF8 (R/W)  PMU Component Identification Register 2 */\n  __IOM uint32_t CIDR3;                             /*!< Offset: 0xFFC (R/W)  PMU Component Identification Register 3 */\n} PMU_Type;\n\n/** \\brief PMU Event Counter Registers (0-30) Definitions  */\n\n#define PMU_EVCNTR_CNT_Pos                    0U                                           /*!< PMU EVCNTR: Counter Position */\n#define PMU_EVCNTR_CNT_Msk                   (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/)         /*!< PMU EVCNTR: Counter Mask */\n\n/** \\brief PMU Event Type and Filter Registers (0-30) Definitions  */\n\n#define PMU_EVTYPER_EVENTTOCNT_Pos            0U                                           /*!< PMU EVTYPER: Event to Count Position */\n#define PMU_EVTYPER_EVENTTOCNT_Msk           (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/)     /*!< PMU EVTYPER: Event to Count Mask */\n\n/** \\brief PMU Count Enable Set Register Definitions */\n\n#define PMU_CNTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */\n#define PMU_CNTENSET_CNT0_ENABLE_Msk         (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/)     /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT1_ENABLE_Pos          1U                                           /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */\n#define PMU_CNTENSET_CNT1_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT2_ENABLE_Pos          2U                                           /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */\n#define PMU_CNTENSET_CNT2_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT3_ENABLE_Pos          3U                                           /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */\n#define PMU_CNTENSET_CNT3_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT4_ENABLE_Pos          4U                                           /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */\n#define PMU_CNTENSET_CNT4_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT5_ENABLE_Pos          5U                                           /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */\n#define PMU_CNTENSET_CNT5_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT6_ENABLE_Pos          6U                                           /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */\n#define PMU_CNTENSET_CNT6_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT7_ENABLE_Pos          7U                                           /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */\n#define PMU_CNTENSET_CNT7_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT8_ENABLE_Pos          8U                                           /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */\n#define PMU_CNTENSET_CNT8_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT9_ENABLE_Pos          9U                                           /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */\n#define PMU_CNTENSET_CNT9_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT10_ENABLE_Pos         10U                                          /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */\n#define PMU_CNTENSET_CNT10_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT11_ENABLE_Pos         11U                                          /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */\n#define PMU_CNTENSET_CNT11_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT12_ENABLE_Pos         12U                                          /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */\n#define PMU_CNTENSET_CNT12_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT13_ENABLE_Pos         13U                                          /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */\n#define PMU_CNTENSET_CNT13_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT14_ENABLE_Pos         14U                                          /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */\n#define PMU_CNTENSET_CNT14_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT15_ENABLE_Pos         15U                                          /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */\n#define PMU_CNTENSET_CNT15_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT16_ENABLE_Pos         16U                                          /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */\n#define PMU_CNTENSET_CNT16_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT17_ENABLE_Pos         17U                                          /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */\n#define PMU_CNTENSET_CNT17_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT18_ENABLE_Pos         18U                                          /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */\n#define PMU_CNTENSET_CNT18_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT19_ENABLE_Pos         19U                                          /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */\n#define PMU_CNTENSET_CNT19_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT20_ENABLE_Pos         20U                                          /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */\n#define PMU_CNTENSET_CNT20_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT21_ENABLE_Pos         21U                                          /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */\n#define PMU_CNTENSET_CNT21_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT22_ENABLE_Pos         22U                                          /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */\n#define PMU_CNTENSET_CNT22_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT23_ENABLE_Pos         23U                                          /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */\n#define PMU_CNTENSET_CNT23_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT24_ENABLE_Pos         24U                                          /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */\n#define PMU_CNTENSET_CNT24_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT25_ENABLE_Pos         25U                                          /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */\n#define PMU_CNTENSET_CNT25_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT26_ENABLE_Pos         26U                                          /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */\n#define PMU_CNTENSET_CNT26_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT27_ENABLE_Pos         27U                                          /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */\n#define PMU_CNTENSET_CNT27_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT28_ENABLE_Pos         28U                                          /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */\n#define PMU_CNTENSET_CNT28_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT29_ENABLE_Pos         29U                                          /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */\n#define PMU_CNTENSET_CNT29_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT30_ENABLE_Pos         30U                                          /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */\n#define PMU_CNTENSET_CNT30_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */\n\n#define PMU_CNTENSET_CCNTR_ENABLE_Pos         31U                                          /*!< PMU CNTENSET: Cycle Counter Enable Set Position */\n#define PMU_CNTENSET_CCNTR_ENABLE_Msk        (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos)        /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */\n\n/** \\brief PMU Count Enable Clear Register Definitions */\n\n#define PMU_CNTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */\n#define PMU_CNTENCLR_CNT0_ENABLE_Msk         (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/)     /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT1_ENABLE_Pos          1U                                           /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */\n#define PMU_CNTENCLR_CNT1_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */\n\n#define PMU_CNTENCLR_CNT2_ENABLE_Pos          2U                                           /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */\n#define PMU_CNTENCLR_CNT2_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT3_ENABLE_Pos          3U                                           /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */\n#define PMU_CNTENCLR_CNT3_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT4_ENABLE_Pos          4U                                           /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */\n#define PMU_CNTENCLR_CNT4_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT5_ENABLE_Pos          5U                                           /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */\n#define PMU_CNTENCLR_CNT5_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT6_ENABLE_Pos          6U                                           /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */\n#define PMU_CNTENCLR_CNT6_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT7_ENABLE_Pos          7U                                           /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */\n#define PMU_CNTENCLR_CNT7_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT8_ENABLE_Pos          8U                                           /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */\n#define PMU_CNTENCLR_CNT8_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT9_ENABLE_Pos          9U                                           /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */\n#define PMU_CNTENCLR_CNT9_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT10_ENABLE_Pos         10U                                          /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */\n#define PMU_CNTENCLR_CNT10_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT11_ENABLE_Pos         11U                                          /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */\n#define PMU_CNTENCLR_CNT11_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT12_ENABLE_Pos         12U                                          /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */\n#define PMU_CNTENCLR_CNT12_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT13_ENABLE_Pos         13U                                          /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */\n#define PMU_CNTENCLR_CNT13_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT14_ENABLE_Pos         14U                                          /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */\n#define PMU_CNTENCLR_CNT14_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT15_ENABLE_Pos         15U                                          /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */\n#define PMU_CNTENCLR_CNT15_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT16_ENABLE_Pos         16U                                          /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */\n#define PMU_CNTENCLR_CNT16_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT17_ENABLE_Pos         17U                                          /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */\n#define PMU_CNTENCLR_CNT17_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT18_ENABLE_Pos         18U                                          /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */\n#define PMU_CNTENCLR_CNT18_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT19_ENABLE_Pos         19U                                          /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */\n#define PMU_CNTENCLR_CNT19_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT20_ENABLE_Pos         20U                                          /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */\n#define PMU_CNTENCLR_CNT20_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT21_ENABLE_Pos         21U                                          /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */\n#define PMU_CNTENCLR_CNT21_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT22_ENABLE_Pos         22U                                          /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */\n#define PMU_CNTENCLR_CNT22_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT23_ENABLE_Pos         23U                                          /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */\n#define PMU_CNTENCLR_CNT23_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT24_ENABLE_Pos         24U                                          /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */\n#define PMU_CNTENCLR_CNT24_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT25_ENABLE_Pos         25U                                          /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */\n#define PMU_CNTENCLR_CNT25_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT26_ENABLE_Pos         26U                                          /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */\n#define PMU_CNTENCLR_CNT26_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT27_ENABLE_Pos         27U                                          /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */\n#define PMU_CNTENCLR_CNT27_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT28_ENABLE_Pos         28U                                          /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */\n#define PMU_CNTENCLR_CNT28_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT29_ENABLE_Pos         29U                                          /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */\n#define PMU_CNTENCLR_CNT29_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT30_ENABLE_Pos         30U                                          /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */\n#define PMU_CNTENCLR_CNT30_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CCNTR_ENABLE_Pos         31U                                          /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */\n#define PMU_CNTENCLR_CCNTR_ENABLE_Msk        (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos)        /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */\n\n/** \\brief PMU Interrupt Enable Set Register Definitions */\n\n#define PMU_INTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT0_ENABLE_Msk         (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/)     /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT1_ENABLE_Pos          1U                                           /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT1_ENABLE_Msk         (1UL << PMU_INTENSET_CNT1_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT2_ENABLE_Pos          2U                                           /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT2_ENABLE_Msk         (1UL << PMU_INTENSET_CNT2_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT3_ENABLE_Pos          3U                                           /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT3_ENABLE_Msk         (1UL << PMU_INTENSET_CNT3_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT4_ENABLE_Pos          4U                                           /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT4_ENABLE_Msk         (1UL << PMU_INTENSET_CNT4_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT5_ENABLE_Pos          5U                                           /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT5_ENABLE_Msk         (1UL << PMU_INTENSET_CNT5_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT6_ENABLE_Pos          6U                                           /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT6_ENABLE_Msk         (1UL << PMU_INTENSET_CNT6_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT7_ENABLE_Pos          7U                                           /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT7_ENABLE_Msk         (1UL << PMU_INTENSET_CNT7_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT8_ENABLE_Pos          8U                                           /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT8_ENABLE_Msk         (1UL << PMU_INTENSET_CNT8_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT9_ENABLE_Pos          9U                                           /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT9_ENABLE_Msk         (1UL << PMU_INTENSET_CNT9_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT10_ENABLE_Pos         10U                                          /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT10_ENABLE_Msk        (1UL << PMU_INTENSET_CNT10_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT11_ENABLE_Pos         11U                                          /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT11_ENABLE_Msk        (1UL << PMU_INTENSET_CNT11_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT12_ENABLE_Pos         12U                                          /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT12_ENABLE_Msk        (1UL << PMU_INTENSET_CNT12_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT13_ENABLE_Pos         13U                                          /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT13_ENABLE_Msk        (1UL << PMU_INTENSET_CNT13_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT14_ENABLE_Pos         14U                                          /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT14_ENABLE_Msk        (1UL << PMU_INTENSET_CNT14_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT15_ENABLE_Pos         15U                                          /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT15_ENABLE_Msk        (1UL << PMU_INTENSET_CNT15_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT16_ENABLE_Pos         16U                                          /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT16_ENABLE_Msk        (1UL << PMU_INTENSET_CNT16_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT17_ENABLE_Pos         17U                                          /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT17_ENABLE_Msk        (1UL << PMU_INTENSET_CNT17_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT18_ENABLE_Pos         18U                                          /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT18_ENABLE_Msk        (1UL << PMU_INTENSET_CNT18_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT19_ENABLE_Pos         19U                                          /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT19_ENABLE_Msk        (1UL << PMU_INTENSET_CNT19_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT20_ENABLE_Pos         20U                                          /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT20_ENABLE_Msk        (1UL << PMU_INTENSET_CNT20_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT21_ENABLE_Pos         21U                                          /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT21_ENABLE_Msk        (1UL << PMU_INTENSET_CNT21_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT22_ENABLE_Pos         22U                                          /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT22_ENABLE_Msk        (1UL << PMU_INTENSET_CNT22_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT23_ENABLE_Pos         23U                                          /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT23_ENABLE_Msk        (1UL << PMU_INTENSET_CNT23_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT24_ENABLE_Pos         24U                                          /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT24_ENABLE_Msk        (1UL << PMU_INTENSET_CNT24_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT25_ENABLE_Pos         25U                                          /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT25_ENABLE_Msk        (1UL << PMU_INTENSET_CNT25_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT26_ENABLE_Pos         26U                                          /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT26_ENABLE_Msk        (1UL << PMU_INTENSET_CNT26_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT27_ENABLE_Pos         27U                                          /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT27_ENABLE_Msk        (1UL << PMU_INTENSET_CNT27_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT28_ENABLE_Pos         28U                                          /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT28_ENABLE_Msk        (1UL << PMU_INTENSET_CNT28_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT29_ENABLE_Pos         29U                                          /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT29_ENABLE_Msk        (1UL << PMU_INTENSET_CNT29_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT30_ENABLE_Pos         30U                                          /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT30_ENABLE_Msk        (1UL << PMU_INTENSET_CNT30_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CYCCNT_ENABLE_Pos        31U                                          /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */\n#define PMU_INTENSET_CCYCNT_ENABLE_Msk       (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos)       /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */\n\n/** \\brief PMU Interrupt Enable Clear Register Definitions */\n\n#define PMU_INTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT0_ENABLE_Msk         (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/)     /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT1_ENABLE_Pos          1U                                           /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT1_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */\n\n#define PMU_INTENCLR_CNT2_ENABLE_Pos          2U                                           /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT2_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT3_ENABLE_Pos          3U                                           /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT3_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT4_ENABLE_Pos          4U                                           /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT4_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT5_ENABLE_Pos          5U                                           /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT5_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT6_ENABLE_Pos          6U                                           /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT6_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT7_ENABLE_Pos          7U                                           /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT7_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT8_ENABLE_Pos          8U                                           /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT8_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT9_ENABLE_Pos          9U                                           /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT9_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT10_ENABLE_Pos         10U                                          /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT10_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT11_ENABLE_Pos         11U                                          /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT11_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT12_ENABLE_Pos         12U                                          /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT12_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT13_ENABLE_Pos         13U                                          /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT13_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT14_ENABLE_Pos         14U                                          /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT14_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT15_ENABLE_Pos         15U                                          /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT15_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT16_ENABLE_Pos         16U                                          /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT16_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT17_ENABLE_Pos         17U                                          /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT17_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT18_ENABLE_Pos         18U                                          /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT18_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT19_ENABLE_Pos         19U                                          /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT19_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT20_ENABLE_Pos         20U                                          /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT20_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT21_ENABLE_Pos         21U                                          /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT21_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT22_ENABLE_Pos         22U                                          /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT22_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT23_ENABLE_Pos         23U                                          /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT23_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT24_ENABLE_Pos         24U                                          /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT24_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT25_ENABLE_Pos         25U                                          /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT25_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT26_ENABLE_Pos         26U                                          /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT26_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT27_ENABLE_Pos         27U                                          /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT27_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT28_ENABLE_Pos         28U                                          /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT28_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT29_ENABLE_Pos         29U                                          /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT29_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT30_ENABLE_Pos         30U                                          /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT30_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CYCCNT_ENABLE_Pos        31U                                          /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CYCCNT_ENABLE_Msk       (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos)       /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */\n\n/** \\brief PMU Overflow Flag Status Set Register Definitions */\n\n#define PMU_OVSSET_CNT0_STATUS_Pos            0U                                           /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */\n#define PMU_OVSSET_CNT0_STATUS_Msk           (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/)       /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT1_STATUS_Pos            1U                                           /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */\n#define PMU_OVSSET_CNT1_STATUS_Msk           (1UL << PMU_OVSSET_CNT1_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT2_STATUS_Pos            2U                                           /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */\n#define PMU_OVSSET_CNT2_STATUS_Msk           (1UL << PMU_OVSSET_CNT2_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT3_STATUS_Pos            3U                                           /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */\n#define PMU_OVSSET_CNT3_STATUS_Msk           (1UL << PMU_OVSSET_CNT3_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT4_STATUS_Pos            4U                                           /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */\n#define PMU_OVSSET_CNT4_STATUS_Msk           (1UL << PMU_OVSSET_CNT4_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT5_STATUS_Pos            5U                                           /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */\n#define PMU_OVSSET_CNT5_STATUS_Msk           (1UL << PMU_OVSSET_CNT5_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT6_STATUS_Pos            6U                                           /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */\n#define PMU_OVSSET_CNT6_STATUS_Msk           (1UL << PMU_OVSSET_CNT6_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT7_STATUS_Pos            7U                                           /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */\n#define PMU_OVSSET_CNT7_STATUS_Msk           (1UL << PMU_OVSSET_CNT7_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT8_STATUS_Pos            8U                                           /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */\n#define PMU_OVSSET_CNT8_STATUS_Msk           (1UL << PMU_OVSSET_CNT8_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT9_STATUS_Pos            9U                                           /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */\n#define PMU_OVSSET_CNT9_STATUS_Msk           (1UL << PMU_OVSSET_CNT9_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT10_STATUS_Pos           10U                                          /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */\n#define PMU_OVSSET_CNT10_STATUS_Msk          (1UL << PMU_OVSSET_CNT10_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT11_STATUS_Pos           11U                                          /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */\n#define PMU_OVSSET_CNT11_STATUS_Msk          (1UL << PMU_OVSSET_CNT11_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT12_STATUS_Pos           12U                                          /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */\n#define PMU_OVSSET_CNT12_STATUS_Msk          (1UL << PMU_OVSSET_CNT12_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT13_STATUS_Pos           13U                                          /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */\n#define PMU_OVSSET_CNT13_STATUS_Msk          (1UL << PMU_OVSSET_CNT13_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT14_STATUS_Pos           14U                                          /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */\n#define PMU_OVSSET_CNT14_STATUS_Msk          (1UL << PMU_OVSSET_CNT14_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT15_STATUS_Pos           15U                                          /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */\n#define PMU_OVSSET_CNT15_STATUS_Msk          (1UL << PMU_OVSSET_CNT15_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT16_STATUS_Pos           16U                                          /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */\n#define PMU_OVSSET_CNT16_STATUS_Msk          (1UL << PMU_OVSSET_CNT16_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT17_STATUS_Pos           17U                                          /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */\n#define PMU_OVSSET_CNT17_STATUS_Msk          (1UL << PMU_OVSSET_CNT17_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT18_STATUS_Pos           18U                                          /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */\n#define PMU_OVSSET_CNT18_STATUS_Msk          (1UL << PMU_OVSSET_CNT18_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT19_STATUS_Pos           19U                                          /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */\n#define PMU_OVSSET_CNT19_STATUS_Msk          (1UL << PMU_OVSSET_CNT19_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT20_STATUS_Pos           20U                                          /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */\n#define PMU_OVSSET_CNT20_STATUS_Msk          (1UL << PMU_OVSSET_CNT20_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT21_STATUS_Pos           21U                                          /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */\n#define PMU_OVSSET_CNT21_STATUS_Msk          (1UL << PMU_OVSSET_CNT21_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT22_STATUS_Pos           22U                                          /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */\n#define PMU_OVSSET_CNT22_STATUS_Msk          (1UL << PMU_OVSSET_CNT22_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT23_STATUS_Pos           23U                                          /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */\n#define PMU_OVSSET_CNT23_STATUS_Msk          (1UL << PMU_OVSSET_CNT23_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT24_STATUS_Pos           24U                                          /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */\n#define PMU_OVSSET_CNT24_STATUS_Msk          (1UL << PMU_OVSSET_CNT24_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT25_STATUS_Pos           25U                                          /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */\n#define PMU_OVSSET_CNT25_STATUS_Msk          (1UL << PMU_OVSSET_CNT25_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT26_STATUS_Pos           26U                                          /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */\n#define PMU_OVSSET_CNT26_STATUS_Msk          (1UL << PMU_OVSSET_CNT26_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT27_STATUS_Pos           27U                                          /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */\n#define PMU_OVSSET_CNT27_STATUS_Msk          (1UL << PMU_OVSSET_CNT27_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT28_STATUS_Pos           28U                                          /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */\n#define PMU_OVSSET_CNT28_STATUS_Msk          (1UL << PMU_OVSSET_CNT28_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT29_STATUS_Pos           29U                                          /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */\n#define PMU_OVSSET_CNT29_STATUS_Msk          (1UL << PMU_OVSSET_CNT29_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT30_STATUS_Pos           30U                                          /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */\n#define PMU_OVSSET_CNT30_STATUS_Msk          (1UL << PMU_OVSSET_CNT30_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */\n\n#define PMU_OVSSET_CYCCNT_STATUS_Pos          31U                                          /*!< PMU OVSSET: Cycle Counter Overflow Set Position */\n#define PMU_OVSSET_CYCCNT_STATUS_Msk         (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos)         /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */\n\n/** \\brief PMU Overflow Flag Status Clear Register Definitions */\n\n#define PMU_OVSCLR_CNT0_STATUS_Pos            0U                                           /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */\n#define PMU_OVSCLR_CNT0_STATUS_Msk           (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/)       /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT1_STATUS_Pos            1U                                           /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */\n#define PMU_OVSCLR_CNT1_STATUS_Msk           (1UL << PMU_OVSCLR_CNT1_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */\n\n#define PMU_OVSCLR_CNT2_STATUS_Pos            2U                                           /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */\n#define PMU_OVSCLR_CNT2_STATUS_Msk           (1UL << PMU_OVSCLR_CNT2_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT3_STATUS_Pos            3U                                           /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */\n#define PMU_OVSCLR_CNT3_STATUS_Msk           (1UL << PMU_OVSCLR_CNT3_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT4_STATUS_Pos            4U                                           /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */\n#define PMU_OVSCLR_CNT4_STATUS_Msk           (1UL << PMU_OVSCLR_CNT4_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT5_STATUS_Pos            5U                                           /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */\n#define PMU_OVSCLR_CNT5_STATUS_Msk           (1UL << PMU_OVSCLR_CNT5_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT6_STATUS_Pos            6U                                           /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */\n#define PMU_OVSCLR_CNT6_STATUS_Msk           (1UL << PMU_OVSCLR_CNT6_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT7_STATUS_Pos            7U                                           /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */\n#define PMU_OVSCLR_CNT7_STATUS_Msk           (1UL << PMU_OVSCLR_CNT7_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT8_STATUS_Pos            8U                                           /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */\n#define PMU_OVSCLR_CNT8_STATUS_Msk           (1UL << PMU_OVSCLR_CNT8_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT9_STATUS_Pos            9U                                           /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */\n#define PMU_OVSCLR_CNT9_STATUS_Msk           (1UL << PMU_OVSCLR_CNT9_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT10_STATUS_Pos           10U                                          /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */\n#define PMU_OVSCLR_CNT10_STATUS_Msk          (1UL << PMU_OVSCLR_CNT10_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT11_STATUS_Pos           11U                                          /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */\n#define PMU_OVSCLR_CNT11_STATUS_Msk          (1UL << PMU_OVSCLR_CNT11_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT12_STATUS_Pos           12U                                          /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */\n#define PMU_OVSCLR_CNT12_STATUS_Msk          (1UL << PMU_OVSCLR_CNT12_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT13_STATUS_Pos           13U                                          /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */\n#define PMU_OVSCLR_CNT13_STATUS_Msk          (1UL << PMU_OVSCLR_CNT13_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT14_STATUS_Pos           14U                                          /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */\n#define PMU_OVSCLR_CNT14_STATUS_Msk          (1UL << PMU_OVSCLR_CNT14_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT15_STATUS_Pos           15U                                          /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */\n#define PMU_OVSCLR_CNT15_STATUS_Msk          (1UL << PMU_OVSCLR_CNT15_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT16_STATUS_Pos           16U                                          /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */\n#define PMU_OVSCLR_CNT16_STATUS_Msk          (1UL << PMU_OVSCLR_CNT16_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT17_STATUS_Pos           17U                                          /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */\n#define PMU_OVSCLR_CNT17_STATUS_Msk          (1UL << PMU_OVSCLR_CNT17_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT18_STATUS_Pos           18U                                          /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */\n#define PMU_OVSCLR_CNT18_STATUS_Msk          (1UL << PMU_OVSCLR_CNT18_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT19_STATUS_Pos           19U                                          /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */\n#define PMU_OVSCLR_CNT19_STATUS_Msk          (1UL << PMU_OVSCLR_CNT19_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT20_STATUS_Pos           20U                                          /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */\n#define PMU_OVSCLR_CNT20_STATUS_Msk          (1UL << PMU_OVSCLR_CNT20_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT21_STATUS_Pos           21U                                          /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */\n#define PMU_OVSCLR_CNT21_STATUS_Msk          (1UL << PMU_OVSCLR_CNT21_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT22_STATUS_Pos           22U                                          /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */\n#define PMU_OVSCLR_CNT22_STATUS_Msk          (1UL << PMU_OVSCLR_CNT22_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT23_STATUS_Pos           23U                                          /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */\n#define PMU_OVSCLR_CNT23_STATUS_Msk          (1UL << PMU_OVSCLR_CNT23_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT24_STATUS_Pos           24U                                          /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */\n#define PMU_OVSCLR_CNT24_STATUS_Msk          (1UL << PMU_OVSCLR_CNT24_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT25_STATUS_Pos           25U                                          /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */\n#define PMU_OVSCLR_CNT25_STATUS_Msk          (1UL << PMU_OVSCLR_CNT25_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT26_STATUS_Pos           26U                                          /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */\n#define PMU_OVSCLR_CNT26_STATUS_Msk          (1UL << PMU_OVSCLR_CNT26_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT27_STATUS_Pos           27U                                          /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */\n#define PMU_OVSCLR_CNT27_STATUS_Msk          (1UL << PMU_OVSCLR_CNT27_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT28_STATUS_Pos           28U                                          /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */\n#define PMU_OVSCLR_CNT28_STATUS_Msk          (1UL << PMU_OVSCLR_CNT28_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT29_STATUS_Pos           29U                                          /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */\n#define PMU_OVSCLR_CNT29_STATUS_Msk          (1UL << PMU_OVSCLR_CNT29_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT30_STATUS_Pos           30U                                          /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */\n#define PMU_OVSCLR_CNT30_STATUS_Msk          (1UL << PMU_OVSCLR_CNT30_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CYCCNT_STATUS_Pos          31U                                          /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */\n#define PMU_OVSCLR_CYCCNT_STATUS_Msk         (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos)         /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */\n\n/** \\brief PMU Software Increment Counter */\n\n#define PMU_SWINC_CNT0_Pos                    0U                                           /*!< PMU SWINC: Event Counter 0 Software Increment Position */\n#define PMU_SWINC_CNT0_Msk                   (1UL /*<< PMU_SWINC_CNT0_Pos */)              /*!< PMU SWINC: Event Counter 0 Software Increment Mask */\n\n#define PMU_SWINC_CNT1_Pos                    1U                                           /*!< PMU SWINC: Event Counter 1 Software Increment Position */\n#define PMU_SWINC_CNT1_Msk                   (1UL << PMU_SWINC_CNT1_Pos)                   /*!< PMU SWINC: Event Counter 1 Software Increment Mask */\n\n#define PMU_SWINC_CNT2_Pos                    2U                                           /*!< PMU SWINC: Event Counter 2 Software Increment Position */\n#define PMU_SWINC_CNT2_Msk                   (1UL << PMU_SWINC_CNT2_Pos)                   /*!< PMU SWINC: Event Counter 2 Software Increment Mask */\n\n#define PMU_SWINC_CNT3_Pos                    3U                                           /*!< PMU SWINC: Event Counter 3 Software Increment Position */\n#define PMU_SWINC_CNT3_Msk                   (1UL << PMU_SWINC_CNT3_Pos)                   /*!< PMU SWINC: Event Counter 3 Software Increment Mask */\n\n#define PMU_SWINC_CNT4_Pos                    4U                                           /*!< PMU SWINC: Event Counter 4 Software Increment Position */\n#define PMU_SWINC_CNT4_Msk                   (1UL << PMU_SWINC_CNT4_Pos)                   /*!< PMU SWINC: Event Counter 4 Software Increment Mask */\n\n#define PMU_SWINC_CNT5_Pos                    5U                                           /*!< PMU SWINC: Event Counter 5 Software Increment Position */\n#define PMU_SWINC_CNT5_Msk                   (1UL << PMU_SWINC_CNT5_Pos)                   /*!< PMU SWINC: Event Counter 5 Software Increment Mask */\n\n#define PMU_SWINC_CNT6_Pos                    6U                                           /*!< PMU SWINC: Event Counter 6 Software Increment Position */\n#define PMU_SWINC_CNT6_Msk                   (1UL << PMU_SWINC_CNT6_Pos)                   /*!< PMU SWINC: Event Counter 6 Software Increment Mask */\n\n#define PMU_SWINC_CNT7_Pos                    7U                                           /*!< PMU SWINC: Event Counter 7 Software Increment Position */\n#define PMU_SWINC_CNT7_Msk                   (1UL << PMU_SWINC_CNT7_Pos)                   /*!< PMU SWINC: Event Counter 7 Software Increment Mask */\n\n#define PMU_SWINC_CNT8_Pos                    8U                                           /*!< PMU SWINC: Event Counter 8 Software Increment Position */\n#define PMU_SWINC_CNT8_Msk                   (1UL << PMU_SWINC_CNT8_Pos)                   /*!< PMU SWINC: Event Counter 8 Software Increment Mask */\n\n#define PMU_SWINC_CNT9_Pos                    9U                                           /*!< PMU SWINC: Event Counter 9 Software Increment Position */\n#define PMU_SWINC_CNT9_Msk                   (1UL << PMU_SWINC_CNT9_Pos)                   /*!< PMU SWINC: Event Counter 9 Software Increment Mask */\n\n#define PMU_SWINC_CNT10_Pos                   10U                                          /*!< PMU SWINC: Event Counter 10 Software Increment Position */\n#define PMU_SWINC_CNT10_Msk                  (1UL << PMU_SWINC_CNT10_Pos)                  /*!< PMU SWINC: Event Counter 10 Software Increment Mask */\n\n#define PMU_SWINC_CNT11_Pos                   11U                                          /*!< PMU SWINC: Event Counter 11 Software Increment Position */\n#define PMU_SWINC_CNT11_Msk                  (1UL << PMU_SWINC_CNT11_Pos)                  /*!< PMU SWINC: Event Counter 11 Software Increment Mask */\n\n#define PMU_SWINC_CNT12_Pos                   12U                                          /*!< PMU SWINC: Event Counter 12 Software Increment Position */\n#define PMU_SWINC_CNT12_Msk                  (1UL << PMU_SWINC_CNT12_Pos)                  /*!< PMU SWINC: Event Counter 12 Software Increment Mask */\n\n#define PMU_SWINC_CNT13_Pos                   13U                                          /*!< PMU SWINC: Event Counter 13 Software Increment Position */\n#define PMU_SWINC_CNT13_Msk                  (1UL << PMU_SWINC_CNT13_Pos)                  /*!< PMU SWINC: Event Counter 13 Software Increment Mask */\n\n#define PMU_SWINC_CNT14_Pos                   14U                                          /*!< PMU SWINC: Event Counter 14 Software Increment Position */\n#define PMU_SWINC_CNT14_Msk                  (1UL << PMU_SWINC_CNT14_Pos)                  /*!< PMU SWINC: Event Counter 14 Software Increment Mask */\n\n#define PMU_SWINC_CNT15_Pos                   15U                                          /*!< PMU SWINC: Event Counter 15 Software Increment Position */\n#define PMU_SWINC_CNT15_Msk                  (1UL << PMU_SWINC_CNT15_Pos)                  /*!< PMU SWINC: Event Counter 15 Software Increment Mask */\n\n#define PMU_SWINC_CNT16_Pos                   16U                                          /*!< PMU SWINC: Event Counter 16 Software Increment Position */\n#define PMU_SWINC_CNT16_Msk                  (1UL << PMU_SWINC_CNT16_Pos)                  /*!< PMU SWINC: Event Counter 16 Software Increment Mask */\n\n#define PMU_SWINC_CNT17_Pos                   17U                                          /*!< PMU SWINC: Event Counter 17 Software Increment Position */\n#define PMU_SWINC_CNT17_Msk                  (1UL << PMU_SWINC_CNT17_Pos)                  /*!< PMU SWINC: Event Counter 17 Software Increment Mask */\n\n#define PMU_SWINC_CNT18_Pos                   18U                                          /*!< PMU SWINC: Event Counter 18 Software Increment Position */\n#define PMU_SWINC_CNT18_Msk                  (1UL << PMU_SWINC_CNT18_Pos)                  /*!< PMU SWINC: Event Counter 18 Software Increment Mask */\n\n#define PMU_SWINC_CNT19_Pos                   19U                                          /*!< PMU SWINC: Event Counter 19 Software Increment Position */\n#define PMU_SWINC_CNT19_Msk                  (1UL << PMU_SWINC_CNT19_Pos)                  /*!< PMU SWINC: Event Counter 19 Software Increment Mask */\n\n#define PMU_SWINC_CNT20_Pos                   20U                                          /*!< PMU SWINC: Event Counter 20 Software Increment Position */\n#define PMU_SWINC_CNT20_Msk                  (1UL << PMU_SWINC_CNT20_Pos)                  /*!< PMU SWINC: Event Counter 20 Software Increment Mask */\n\n#define PMU_SWINC_CNT21_Pos                   21U                                          /*!< PMU SWINC: Event Counter 21 Software Increment Position */\n#define PMU_SWINC_CNT21_Msk                  (1UL << PMU_SWINC_CNT21_Pos)                  /*!< PMU SWINC: Event Counter 21 Software Increment Mask */\n\n#define PMU_SWINC_CNT22_Pos                   22U                                          /*!< PMU SWINC: Event Counter 22 Software Increment Position */\n#define PMU_SWINC_CNT22_Msk                  (1UL << PMU_SWINC_CNT22_Pos)                  /*!< PMU SWINC: Event Counter 22 Software Increment Mask */\n\n#define PMU_SWINC_CNT23_Pos                   23U                                          /*!< PMU SWINC: Event Counter 23 Software Increment Position */\n#define PMU_SWINC_CNT23_Msk                  (1UL << PMU_SWINC_CNT23_Pos)                  /*!< PMU SWINC: Event Counter 23 Software Increment Mask */\n\n#define PMU_SWINC_CNT24_Pos                   24U                                          /*!< PMU SWINC: Event Counter 24 Software Increment Position */\n#define PMU_SWINC_CNT24_Msk                  (1UL << PMU_SWINC_CNT24_Pos)                  /*!< PMU SWINC: Event Counter 24 Software Increment Mask */\n\n#define PMU_SWINC_CNT25_Pos                   25U                                          /*!< PMU SWINC: Event Counter 25 Software Increment Position */\n#define PMU_SWINC_CNT25_Msk                  (1UL << PMU_SWINC_CNT25_Pos)                  /*!< PMU SWINC: Event Counter 25 Software Increment Mask */\n\n#define PMU_SWINC_CNT26_Pos                   26U                                          /*!< PMU SWINC: Event Counter 26 Software Increment Position */\n#define PMU_SWINC_CNT26_Msk                  (1UL << PMU_SWINC_CNT26_Pos)                  /*!< PMU SWINC: Event Counter 26 Software Increment Mask */\n\n#define PMU_SWINC_CNT27_Pos                   27U                                          /*!< PMU SWINC: Event Counter 27 Software Increment Position */\n#define PMU_SWINC_CNT27_Msk                  (1UL << PMU_SWINC_CNT27_Pos)                  /*!< PMU SWINC: Event Counter 27 Software Increment Mask */\n\n#define PMU_SWINC_CNT28_Pos                   28U                                          /*!< PMU SWINC: Event Counter 28 Software Increment Position */\n#define PMU_SWINC_CNT28_Msk                  (1UL << PMU_SWINC_CNT28_Pos)                  /*!< PMU SWINC: Event Counter 28 Software Increment Mask */\n\n#define PMU_SWINC_CNT29_Pos                   29U                                          /*!< PMU SWINC: Event Counter 29 Software Increment Position */\n#define PMU_SWINC_CNT29_Msk                  (1UL << PMU_SWINC_CNT29_Pos)                  /*!< PMU SWINC: Event Counter 29 Software Increment Mask */\n\n#define PMU_SWINC_CNT30_Pos                   30U                                          /*!< PMU SWINC: Event Counter 30 Software Increment Position */\n#define PMU_SWINC_CNT30_Msk                  (1UL << PMU_SWINC_CNT30_Pos)                  /*!< PMU SWINC: Event Counter 30 Software Increment Mask */\n\n/** \\brief PMU Control Register Definitions */\n\n#define PMU_CTRL_ENABLE_Pos                   0U                                           /*!< PMU CTRL: ENABLE Position */\n#define PMU_CTRL_ENABLE_Msk                  (1UL /*<< PMU_CTRL_ENABLE_Pos*/)              /*!< PMU CTRL: ENABLE Mask */\n\n#define PMU_CTRL_EVENTCNT_RESET_Pos           1U                                           /*!< PMU CTRL: Event Counter Reset Position */\n#define PMU_CTRL_EVENTCNT_RESET_Msk          (1UL << PMU_CTRL_EVENTCNT_RESET_Pos)          /*!< PMU CTRL: Event Counter Reset Mask */\n\n#define PMU_CTRL_CYCCNT_RESET_Pos             2U                                           /*!< PMU CTRL: Cycle Counter Reset Position */\n#define PMU_CTRL_CYCCNT_RESET_Msk            (1UL << PMU_CTRL_CYCCNT_RESET_Pos)            /*!< PMU CTRL: Cycle Counter Reset Mask */\n\n#define PMU_CTRL_CYCCNT_DISABLE_Pos           5U                                           /*!< PMU CTRL: Disable Cycle Counter Position */\n#define PMU_CTRL_CYCCNT_DISABLE_Msk          (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos)          /*!< PMU CTRL: Disable Cycle Counter Mask */\n\n#define PMU_CTRL_FRZ_ON_OV_Pos                9U                                           /*!< PMU CTRL: Freeze-on-overflow Position */\n#define PMU_CTRL_FRZ_ON_OV_Msk               (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos)         /*!< PMU CTRL: Freeze-on-overflow Mask */\n\n#define PMU_CTRL_TRACE_ON_OV_Pos              11U                                          /*!< PMU CTRL: Trace-on-overflow Position */\n#define PMU_CTRL_TRACE_ON_OV_Msk             (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos)       /*!< PMU CTRL: Trace-on-overflow Mask */\n\n/** \\brief PMU Type Register Definitions */\n\n#define PMU_TYPE_NUM_CNTS_Pos                 0U                                           /*!< PMU TYPE: Number of Counters Position */\n#define PMU_TYPE_NUM_CNTS_Msk                (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/)         /*!< PMU TYPE: Number of Counters Mask */\n\n#define PMU_TYPE_SIZE_CNTS_Pos                8U                                           /*!< PMU TYPE: Size of Counters Position */\n#define PMU_TYPE_SIZE_CNTS_Msk               (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos)            /*!< PMU TYPE: Size of Counters Mask */\n\n#define PMU_TYPE_CYCCNT_PRESENT_Pos           14U                                          /*!< PMU TYPE: Cycle Counter Present Position */\n#define PMU_TYPE_CYCCNT_PRESENT_Msk          (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos)          /*!< PMU TYPE: Cycle Counter Present Mask */\n\n#define PMU_TYPE_FRZ_OV_SUPPORT_Pos           21U                                          /*!< PMU TYPE: Freeze-on-overflow Support Position */\n#define PMU_TYPE_FRZ_OV_SUPPORT_Msk          (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)          /*!< PMU TYPE: Freeze-on-overflow Support Mask */\n\n#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos      23U                                          /*!< PMU TYPE: Trace-on-overflow Support Position */\n#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk     (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)          /*!< PMU TYPE: Trace-on-overflow Support Mask */\n\n/** \\brief PMU Authentication Status Register Definitions */\n\n#define PMU_AUTHSTATUS_NSID_Pos               0U                                           /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */\n#define PMU_AUTHSTATUS_NSID_Msk              (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/)        /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_NSNID_Pos              2U                                           /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_NSNID_Msk             (0x3UL << PMU_AUTHSTATUS_NSNID_Pos)           /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SID_Pos                4U                                           /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */\n#define PMU_AUTHSTATUS_SID_Msk               (0x3UL << PMU_AUTHSTATUS_SID_Pos)             /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SNID_Pos               6U                                           /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_SNID_Msk              (0x3UL << PMU_AUTHSTATUS_SNID_Pos)            /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_NSUID_Pos              16U                                          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */\n#define PMU_AUTHSTATUS_NSUID_Msk             (0x3UL << PMU_AUTHSTATUS_NSUID_Pos)           /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_NSUNID_Pos             18U                                          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_NSUNID_Msk            (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos)          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SUID_Pos               20U                                          /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */\n#define PMU_AUTHSTATUS_SUID_Msk              (0x3UL << PMU_AUTHSTATUS_SUID_Pos)            /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SUNID_Pos              22U                                          /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_SUNID_Msk             (0x3UL << PMU_AUTHSTATUS_SUNID_Pos)           /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */\n\n\n/*@} end of group CMSIS_PMU */\n#endif\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_PXN_Pos                    4U                                            /*!< MPU RLAR: PXN Position */\n#define MPU_RLAR_PXN_Msk                   (1UL << MPU_RLAR_PXN_Pos)                      /*!< MPU RLAR: PXN Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (7UL << MPU_RLAR_AttrIndx_Pos)                 /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n#define FPU_FPDSCR_FZ16_Pos                19U                                            /*!< FPDSCR: FZ16 bit Position */\n#define FPU_FPDSCR_FZ16_Msk                (1UL << FPU_FPDSCR_FZ16_Pos)                   /*!< FPDSCR: FZ16 bit Mask */\n\n#define FPU_FPDSCR_LTPSIZE_Pos             16U                                            /*!< FPDSCR: LTPSIZE bit Position */\n#define FPU_FPDSCR_LTPSIZE_Msk             (7UL << FPU_FPDSCR_LTPSIZE_Pos)                /*!< FPDSCR: LTPSIZE bit Mask */\n\n/* Media and VFP Feature Register 0 Definitions */\n#define FPU_MVFR0_FPRound_Pos              28U                                            /*!< MVFR0: FPRound bits Position */\n#define FPU_MVFR0_FPRound_Msk              (0xFUL << FPU_MVFR0_FPRound_Pos)               /*!< MVFR0: FPRound bits Mask */\n\n#define FPU_MVFR0_FPSqrt_Pos               20U                                            /*!< MVFR0: FPSqrt bits Position */\n#define FPU_MVFR0_FPSqrt_Msk               (0xFUL << FPU_MVFR0_FPSqrt_Pos)                 /*!< MVFR0: FPSqrt bits Mask */\n\n#define FPU_MVFR0_FPDivide_Pos             16U                                            /*!< MVFR0: FPDivide bits Position */\n#define FPU_MVFR0_FPDivide_Msk             (0xFUL << FPU_MVFR0_FPDivide_Pos)              /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FPDP_Pos                  8U                                            /*!< MVFR0: FPDP bits Position */\n#define FPU_MVFR0_FPDP_Msk                 (0xFUL << FPU_MVFR0_FPDP_Pos)                  /*!< MVFR0: FPDP bits Mask */\n\n#define FPU_MVFR0_FPSP_Pos                  4U                                            /*!< MVFR0: FPSP bits Position */\n#define FPU_MVFR0_FPSP_Msk                 (0xFUL << FPU_MVFR0_FPSP_Pos)                  /*!< MVFR0: FPSP bits Mask */\n\n#define FPU_MVFR0_SIMDReg_Pos               0U                                            /*!< MVFR0: SIMDReg bits Position */\n#define FPU_MVFR0_SIMDReg_Msk              (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)           /*!< MVFR0: SIMDReg bits Mask */\n\n/* Media and VFP Feature Register 1 Definitions */\n#define FPU_MVFR1_FMAC_Pos                 28U                                            /*!< MVFR1: FMAC bits Position */\n#define FPU_MVFR1_FMAC_Msk                 (0xFUL << FPU_MVFR1_FMAC_Pos)                  /*!< MVFR1: FMAC bits Mask */\n\n#define FPU_MVFR1_FPHP_Pos                 24U                                            /*!< MVFR1: FPHP bits Position */\n#define FPU_MVFR1_FPHP_Msk                 (0xFUL << FPU_MVFR1_FPHP_Pos)                  /*!< MVFR1: FPHP bits Mask */\n\n#define FPU_MVFR1_FP16_Pos                 20U                                            /*!< MVFR1: FP16 bits Position */\n#define FPU_MVFR1_FP16_Msk                 (0xFUL << FPU_MVFR1_FP16_Pos)                  /*!< MVFR1: FP16 bits Mask */\n\n#define FPU_MVFR1_MVE_Pos                   8U                                            /*!< MVFR1: MVE bits Position */\n#define FPU_MVFR1_MVE_Msk                  (0xFUL << FPU_MVFR1_MVE_Pos)                   /*!< MVFR1: MVE bits Mask */\n\n#define FPU_MVFR1_FPDNaN_Pos                4U                                            /*!< MVFR1: FPDNaN bits Position */\n#define FPU_MVFR1_FPDNaN_Msk               (0xFUL << FPU_MVFR1_FPDNaN_Pos)                /*!< MVFR1: FPDNaN bits Mask */\n\n#define FPU_MVFR1_FPFtZ_Pos                 0U                                            /*!< MVFR1: FPFtZ bits Position */\n#define FPU_MVFR1_FPFtZ_Msk                (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)             /*!< MVFR1: FPFtZ bits Mask */\n\n/* Media and VFP Feature Register 2 Definitions */\n#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */\n#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  \\deprecated Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n  __OM  uint32_t DSCEMCR;                /*!< Offset: 0x010 ( /W)  Debug Set Clear Exception and Monitor Control Register */\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \\deprecated CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \\deprecated CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_FPD_Pos          23U                                            /*!< \\deprecated CoreDebug DHCSR: S_FPD Position */\n#define CoreDebug_DHCSR_S_FPD_Msk          (1UL << CoreDebug_DHCSR_S_FPD_Pos)             /*!< \\deprecated CoreDebug DHCSR: S_FPD Mask */\n\n#define CoreDebug_DHCSR_S_SUIDE_Pos        22U                                            /*!< \\deprecated CoreDebug DHCSR: S_SUIDE Position */\n#define CoreDebug_DHCSR_S_SUIDE_Msk        (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SUIDE Mask */\n\n#define CoreDebug_DHCSR_S_NSUIDE_Pos       21U                                            /*!< \\deprecated CoreDebug DHCSR: S_NSUIDE Position */\n#define CoreDebug_DHCSR_S_NSUIDE_Msk       (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_NSUIDE Mask */\n\n#define CoreDebug_DHCSR_S_SDE_Pos          20U                                            /*!< \\deprecated CoreDebug DHCSR: S_SDE Position */\n#define CoreDebug_DHCSR_S_SDE_Msk          (1UL << CoreDebug_DHCSR_S_SDE_Pos)             /*!< \\deprecated CoreDebug DHCSR: S_SDE Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \\deprecated CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_PMOV_Pos          6U                                            /*!< \\deprecated CoreDebug DHCSR: C_PMOV Position */\n#define CoreDebug_DHCSR_C_PMOV_Msk         (1UL << CoreDebug_DHCSR_C_PMOV_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_PMOV Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \\deprecated CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \\deprecated CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \\deprecated CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \\deprecated CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \\deprecated CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \\deprecated CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< \\deprecated CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< \\deprecated CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< \\deprecated CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< \\deprecated CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< \\deprecated CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< \\deprecated CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< \\deprecated CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< \\deprecated CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Set Clear Exception and Monitor Control Register Definitions */\n#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos  19U                                            /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */\n#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk  (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)     /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */\n\n#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U                                            /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */\n#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)    /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */\n\n#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U                                            /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */\n#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk  (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)     /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */\n\n#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos  1U                                            /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */\n#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)    /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_UIDEN_Pos      10U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: UIDEN, Position */\n#define CoreDebug_DAUTHCTRL_UIDEN_Msk      (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)         /*!< \\deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos     9U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */\n#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk    (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)       /*!< \\deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_FSDMA_Pos       8U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: FSDMA, Position */\n#define CoreDebug_DAUTHCTRL_FSDMA_Msk      (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)         /*!< \\deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \\deprecated CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \\deprecated CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DCB       Debug Control Block\n  \\brief    Type definitions for the Debug Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Control Block Registers (DCB).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n  __OM  uint32_t DSCEMCR;                /*!< Offset: 0x010 ( /W)  Debug Set Clear Exception and Monitor Control Register */\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} DCB_Type;\n\n/* DHCSR, Debug Halting Control and Status Register Definitions */\n#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */\n#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */\n\n#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */\n#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */\n\n#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */\n#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */\n\n#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */\n#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */\n\n#define DCB_DHCSR_S_FPD_Pos                23U                                            /*!< DCB DHCSR: Floating-point registers Debuggable Position */\n#define DCB_DHCSR_S_FPD_Msk                (0x1UL << DCB_DHCSR_S_FPD_Pos)                 /*!< DCB DHCSR: Floating-point registers Debuggable Mask */\n\n#define DCB_DHCSR_S_SUIDE_Pos              22U                                            /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */\n#define DCB_DHCSR_S_SUIDE_Msk              (0x1UL << DCB_DHCSR_S_SUIDE_Pos)               /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */\n\n#define DCB_DHCSR_S_NSUIDE_Pos             21U                                            /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */\n#define DCB_DHCSR_S_NSUIDE_Msk             (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)              /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */\n\n#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */\n#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */\n\n#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */\n#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */\n\n#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */\n#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */\n\n#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */\n#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */\n\n#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */\n#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */\n\n#define DCB_DHCSR_C_PMOV_Pos                6U                                            /*!< DCB DHCSR: Halt on PMU overflow control Position */\n#define DCB_DHCSR_C_PMOV_Msk               (0x1UL << DCB_DHCSR_C_PMOV_Pos)                /*!< DCB DHCSR: Halt on PMU overflow control Mask */\n\n#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */\n#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */\n\n#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */\n#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */\n\n#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */\n#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */\n\n#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */\n#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */\n\n#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */\n#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */\n\n/* DCRSR, Debug Core Register Select Register Definitions */\n#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */\n#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */\n\n#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */\n#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */\n\n/* DCRDR, Debug Core Register Data Register Definitions */\n#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */\n#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */\n\n/* DEMCR, Debug Exception and Monitor Control Register Definitions */\n#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */\n#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */\n\n#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */\n#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */\n\n#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */\n#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */\n\n#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */\n#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */\n\n#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */\n#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */\n\n#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */\n#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */\n\n#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */\n#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */\n\n#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */\n#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */\n\n#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */\n#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */\n\n#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */\n#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */\n\n#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */\n#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */\n\n#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */\n#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */\n\n#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */\n#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */\n\n#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */\n#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */\n\n#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */\n#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */\n\n#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */\n#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */\n\n#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */\n#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */\n\n/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */\n#define DCB_DSCEMCR_CLR_MON_REQ_Pos        19U                                            /*!< DCB DSCEMCR: Clear monitor request Position */\n#define DCB_DSCEMCR_CLR_MON_REQ_Msk        (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)         /*!< DCB DSCEMCR: Clear monitor request Mask */\n\n#define DCB_DSCEMCR_CLR_MON_PEND_Pos       17U                                            /*!< DCB DSCEMCR: Clear monitor pend Position */\n#define DCB_DSCEMCR_CLR_MON_PEND_Msk       (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)        /*!< DCB DSCEMCR: Clear monitor pend Mask */\n\n#define DCB_DSCEMCR_SET_MON_REQ_Pos         3U                                            /*!< DCB DSCEMCR: Set monitor request Position */\n#define DCB_DSCEMCR_SET_MON_REQ_Msk        (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)         /*!< DCB DSCEMCR: Set monitor request Mask */\n\n#define DCB_DSCEMCR_SET_MON_PEND_Pos        1U                                            /*!< DCB DSCEMCR: Set monitor pend Position */\n#define DCB_DSCEMCR_SET_MON_PEND_Msk       (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)        /*!< DCB DSCEMCR: Set monitor pend Mask */\n\n/* DAUTHCTRL, Debug Authentication Control Register Definitions */\n#define DCB_DAUTHCTRL_UIDEN_Pos            10U                                            /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */\n#define DCB_DAUTHCTRL_UIDEN_Msk            (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)             /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */\n\n#define DCB_DAUTHCTRL_UIDAPEN_Pos           9U                                            /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */\n#define DCB_DAUTHCTRL_UIDAPEN_Msk          (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)           /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */\n\n#define DCB_DAUTHCTRL_FSDMA_Pos             8U                                            /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */\n#define DCB_DAUTHCTRL_FSDMA_Msk            (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)             /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */\n\n#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */\n\n#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */\n\n/* DSCSR, Debug Security Control and Status Register Definitions */\n#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */\n#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */\n\n#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */\n#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */\n\n#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */\n#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */\n\n#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */\n#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */\n\n/*@} end of group CMSIS_DCB */\n\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DIB       Debug Identification Block\n  \\brief    Type definitions for the Debug Identification Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Identification Block Registers (DIB).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */\n  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */\n        uint32_t RESERVED1[3U];\n  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x01C (R/ )  SCS Device Type Register */\n} DIB_Type;\n\n/* DAUTHSTATUS, Debug Authentication Status Register Definitions */\n#define DIB_DAUTHSTATUS_SUNID_Pos          22U                                            /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */\n#define DIB_DAUTHSTATUS_SUNID_Msk          (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )          /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */\n\n#define DIB_DAUTHSTATUS_SUID_Pos           20U                                            /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */\n#define DIB_DAUTHSTATUS_SUID_Msk           (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )           /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */\n\n#define DIB_DAUTHSTATUS_NSUNID_Pos         18U                                            /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */\n#define DIB_DAUTHSTATUS_NSUNID_Msk         (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )         /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */\n\n#define DIB_DAUTHSTATUS_NSUID_Pos          16U                                            /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */\n#define DIB_DAUTHSTATUS_NSUID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */\n\n#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */\n\n/* DDEVARCH, SCS Device Architecture Register Definitions */\n#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */\n#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */\n\n#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */\n#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */\n\n#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */\n#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */\n\n#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */\n#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */\n\n#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */\n#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */\n\n/* DDEVTYPE, SCS Device Type Register Definitions */\n#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */\n#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */\n\n#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */\n#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */\n\n\n/*@} end of group CMSIS_DIB */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define MEMSYSCTL_BASE      (0xE001E000UL)                             /*!< Memory System Control Base Address */\n  #define ERRBNK_BASE         (0xE001E100UL)                             /*!< Error Banking Base Address */\n  #define PWRMODCTL_BASE      (0xE001E300UL)                             /*!< Power Mode Control Base Address */\n  #define EWIC_ISA_BASE       (0xE001E400UL)                             /*!< External Wakeup Interrupt Controller interrupt status access Base Address */\n  #define PRCCFGINF_BASE      (0xE001E700UL)                             /*!< Processor Configuration Information Base Address */\n  #define STL_BASE            (0xE001E800UL)                             /*!< Software Test Library Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define EWIC_BASE           (0xE0047000UL)                             /*!< External Wakeup Interrupt Controller Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \\deprecated Core Debug Base Address */\n  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */\n  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define ICB                 ((ICB_Type       *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define MEMSYSCTL           ((MemSysCtl_Type *)     MEMSYSCTL_BASE   ) /*!< Memory System Control configuration struct */\n  #define ERRBNK              ((ErrBnk_Type    *)     ERRBNK_BASE      ) /*!< Error Banking configuration struct */\n  #define PWRMODCTL           ((PwrModCtl_Type *)     PWRMODCTL_BASE   ) /*!< Power Mode Control configuration struct */\n  #define EWIC_ISA            ((EWIC_ISA_Type  *)     EWIC_ISA_BASE    ) /*!< EWIC interrupt status access struct */\n  #define EWIC                ((EWIC_Type      *)     EWIC_BASE        ) /*!< EWIC configuration struct */\n  #define PRCCFGINF           ((PrcCfgInf_Type *)     PRCCFGINF_BASE   ) /*!< Processor Configuration Information configuration struct */\n  #define STL                 ((STL_Type       *)     STL_BASE         ) /*!< Software Test Library configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \\deprecated Core Debug configuration struct */\n  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */\n  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)\n    #define PMU_BASE          (0xE0003000UL)                             /*!< PMU Base Address */\n    #define PMU               ((PMU_Type       *)     PMU_BASE         ) /*!< PMU configuration struct */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \\deprecated Core Debug Base Address           (non-secure address space) */\n  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */\n  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define ICB_NS              ((ICB_Type       *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \\deprecated Core Debug configuration struct   (non-secure address space) */\n  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */\n  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n#define ID_ADR  (ID_AFR)    /*!< SCB Auxiliary Feature Register */\n\n/* 'SCnSCB' is deprecated and replaced by 'ICB' */\ntypedef ICB_Type SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos   (ICB_ACTLR_DISCRITAXIRUW_Pos)\n#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk   (ICB_ACTLR_DISCRITAXIRUW_Msk)\n\n#define SCnSCB_ACTLR_DISDI_Pos           (ICB_ACTLR_DISDI_Pos)\n#define SCnSCB_ACTLR_DISDI_Msk           (ICB_ACTLR_DISDI_Msk)\n\n#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos   (ICB_ACTLR_DISCRITAXIRUR_Pos)\n#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk   (ICB_ACTLR_DISCRITAXIRUR_Msk)\n\n#define SCnSCB_ACTLR_EVENTBUSEN_Pos      (ICB_ACTLR_EVENTBUSEN_Pos)\n#define SCnSCB_ACTLR_EVENTBUSEN_Msk      (ICB_ACTLR_EVENTBUSEN_Msk)\n\n#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos    (ICB_ACTLR_EVENTBUSEN_S_Pos)\n#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk    (ICB_ACTLR_EVENTBUSEN_S_Msk)\n\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos  (ICB_ACTLR_DISITMATBFLUSH_Pos)\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk  (ICB_ACTLR_DISITMATBFLUSH_Msk)\n\n#define SCnSCB_ACTLR_DISNWAMODE_Pos      (ICB_ACTLR_DISNWAMODE_Pos)\n#define SCnSCB_ACTLR_DISNWAMODE_Msk      (ICB_ACTLR_DISNWAMODE_Msk)\n\n#define SCnSCB_ACTLR_FPEXCODIS_Pos       (ICB_ACTLR_FPEXCODIS_Pos)\n#define SCnSCB_ACTLR_FPEXCODIS_Msk       (ICB_ACTLR_FPEXCODIS_Msk)\n\n#define SCnSCB_ACTLR_DISOLAP_Pos         (ICB_ACTLR_DISOLAP_Pos)\n#define SCnSCB_ACTLR_DISOLAP_Msk         (ICB_ACTLR_DISOLAP_Msk)\n\n#define SCnSCB_ACTLR_DISOLAPS_Pos        (ICB_ACTLR_DISOLAPS_Pos)\n#define SCnSCB_ACTLR_DISOLAPS_Msk        (ICB_ACTLR_DISOLAPS_Msk)\n\n#define SCnSCB_ACTLR_DISLOBR_Pos         (ICB_ACTLR_DISLOBR_Pos)\n#define SCnSCB_ACTLR_DISLOBR_Msk         (ICB_ACTLR_DISLOBR_Msk)\n\n#define SCnSCB_ACTLR_DISLO_Pos           (ICB_ACTLR_DISLO_Pos)\n#define SCnSCB_ACTLR_DISLO_Msk           (ICB_ACTLR_DISLO_Msk)\n\n#define SCnSCB_ACTLR_DISLOLEP_Pos        (ICB_ACTLR_DISLOLEP_Pos)\n#define SCnSCB_ACTLR_DISLOLEP_Msk        (ICB_ACTLR_DISLOLEP_Msk)\n\n#define SCnSCB_ACTLR_DISFOLD_Pos         (ICB_ACTLR_DISFOLD_Pos)\n#define SCnSCB_ACTLR_DISFOLD_Msk         (ICB_ACTLR_DISFOLD_Msk)\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos      (ICB_ICTR_INTLINESNUM_Pos)\n#define SCnSCB_ICTR_INTLINESNUM_Msk      (ICB_ICTR_INTLINESNUM_Msk)\n\n#define SCnSCB                           (ICB)\n#define SCnSCB_NS                        (ICB_NS)\n\n/*@} */\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)                      );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  PMU functions and events  #################################### */\n\n#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)\n\n#include \"pmu_armv8.h\"\n\n/**\n  \\brief   Cortex-M55 PMU events\n  \\note    Architectural PMU events can be found in pmu_armv8.h\n*/\n\n#define ARMCM55_PMU_ECC_ERR                          0xC000             /*!< Any ECC error */\n#define ARMCM55_PMU_ECC_ERR_FATAL                    0xC001             /*!< Any fatal ECC error */\n#define ARMCM55_PMU_ECC_ERR_DCACHE                   0xC010             /*!< Any ECC error in the data cache */\n#define ARMCM55_PMU_ECC_ERR_ICACHE                   0xC011             /*!< Any ECC error in the instruction cache */\n#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE             0xC012             /*!< Any fatal ECC error in the data cache */\n#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE             0xC013             /*!< Any fatal ECC error in the instruction cache*/\n#define ARMCM55_PMU_ECC_ERR_DTCM                     0xC020             /*!< Any ECC error in the DTCM */\n#define ARMCM55_PMU_ECC_ERR_ITCM                     0xC021             /*!< Any ECC error in the ITCM */\n#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM               0xC022             /*!< Any fatal ECC error in the DTCM */\n#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM               0xC023             /*!< Any fatal ECC error in the ITCM */\n#define ARMCM55_PMU_PF_LINEFILL                      0xC100             /*!< A prefetcher starts a line-fill */\n#define ARMCM55_PMU_PF_CANCEL                        0xC101             /*!< A prefetcher stops prefetching */\n#define ARMCM55_PMU_PF_DROP_LINEFILL                 0xC102             /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */\n#define ARMCM55_PMU_NWAMODE_ENTER                    0xC200             /*!< No write-allocate mode entry */\n#define ARMCM55_PMU_NWAMODE                          0xC201             /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */\n#define ARMCM55_PMU_SAHB_ACCESS                      0xC300             /*!< Read or write access on the S-AHB interface to the TCM */\n#define ARMCM55_PMU_PAHB_ACCESS                      0xC301             /*!< Read or write access to the P-AHB write interface */\n#define ARMCM55_PMU_AXI_WRITE_ACCESS                 0xC302             /*!< Any beat access to M-AXI write interface */\n#define ARMCM55_PMU_AXI_READ_ACCESS                  0xC303             /*!< Any beat access to M-AXI read interface */\n#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE                0xC400             /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */\n#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE                0xC401             /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */\n#define ARMCM55_PMU_CDE_INST_RETIRED                 0xC402             /*!< CDE instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_CX1_INST_RETIRED             0xC404             /*!< CDE CX1 instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_CX2_INST_RETIRED             0xC406             /*!< CDE CX2 instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_CX3_INST_RETIRED             0xC408             /*!< CDE CX3 instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_VCX1_INST_RETIRED            0xC40A             /*!< CDE VCX1 instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_VCX2_INST_RETIRED            0xC40C             /*!< CDE VCX2 instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_VCX3_INST_RETIRED            0xC40E             /*!< CDE VCX3 instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_VCX1_VEC_INST_RETIRED        0xC410             /*!< CDE VCX1 Vector instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_VCX2_VEC_INST_RETIRED        0xC412             /*!< CDE VCX2 Vector instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_VCX3_VEC_INST_RETIRED        0xC414             /*!< CDE VCX3 Vector instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_PRED                         0xC416             /*!< Cycles where one or more predicated beats of a CDE instruction architecturally executed. */\n#define ARMCM55_PMU_CDE_STALL                        0xC417             /*!< Stall cycles caused by a CDE instruction. */\n#define ARMCM55_PMU_CDE_STALL_RESOURCE               0xC418             /*!< Stall cycles caused by a CDE instruction because of resource conflicts */\n#define ARMCM55_PMU_CDE_STALL_DEPENDENCY             0xC419             /*!< Stall cycles caused by a CDE register dependency. */\n#define ARMCM55_PMU_CDE_STALL_CUSTOM                 0xC41A             /*!< Stall cycles caused by a CDE instruction are generated by the custom hardware. */\n#define ARMCM55_PMU_CDE_STALL_OTHER                  0xC41B             /*!< Stall cycles caused by a CDE instruction are not covered by the other counters. */\n#define ARMCM55_PMU_PF_LF_LA_1                       0xC41C             /*!< A data prefetcher line-fill request is made while the lookahead distance is 1. */\n#define ARMCM55_PMU_PF_LF_LA_2                       0xC41D             /*!< A data prefetcher line-fill request is made while the lookahead distance is 2. */\n#define ARMCM55_PMU_PF_LF_LA_3                       0xC41E             /*!< A data prefetcher line-fill request is made while the lookahead distance is 3. */\n#define ARMCM55_PMU_PF_LF_LA_4                       0xC41F             /*!< A data prefetcher line-fill request is made while the lookahead distance is 4. */\n#define ARMCM55_PMU_PF_LF_LA_5                       0xC420             /*!< A data prefetcher line-fill request is made while the lookahead distance is 5. */\n#define ARMCM55_PMU_PF_LF_LA_6                       0xC421             /*!< A data prefetcher line-fill request is made while the lookahead distance is 6. */\n#define ARMCM55_PMU_PF_BUFFER_FULL                   0xC422             /*!< A data prefetcher request is made while the buffer is full. */\n#define ARMCM55_PMU_PF_BUFFER_MISS                   0xC423             /*!< A load requires a line-fill which misses in the data prefetcher buffer. */\n#define ARMCM55_PMU_PF_BUFFER_HIT                    0xC424             /*!< A load access hits in the data prefetcher buffer. */\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n/* ##########################  MVE functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_MveFunctions MVE Functions\n  \\brief    Function that provides MVE type.\n  @{\n */\n\n/**\n  \\brief   get MVE type\n  \\details returns the MVE type\n  \\returns\n   - \\b  0: No Vector Extension (MVE)\n   - \\b  1: Integer Vector Extension (MVE-I)\n   - \\b  2: Floating-point Vector Extension (MVE-F)\n */\n__STATIC_INLINE uint32_t SCB_GetMVEType(void)\n{\n  const uint32_t mvfr1 = FPU->MVFR1;\n  if      ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))\n  {\n    return 2U;\n  }\n  else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))\n  {\n    return 1U;\n  }\n  else\n  {\n    return 0U;\n  }\n}\n\n\n/*@} end of CMSIS_Core_MveFunctions */\n\n\n/* ##########################  Cache functions  #################################### */\n\n#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \\\n     (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))\n#include \"cachel1_armv7.h\"\n#endif\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    Debug Control function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DCBFunctions Debug Control Functions\n  \\brief    Functions that access the Debug Control Block.\n  @{\n */\n\n\n/**\n  \\brief   Set Debug Authentication Control Register\n  \\details writes to Debug Authentication Control register.\n  \\param [in]  value  value to be writen.\n */\n__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register\n  \\details Reads Debug Authentication Control register.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)\n{\n    return (DCB->DAUTHCTRL);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Debug Authentication Control Register (non-secure)\n  \\details writes to non-secure Debug Authentication Control register when in secure state.\n  \\param [in]  value  value to be writen\n */\n__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB_NS->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register (non-secure)\n  \\details Reads non-secure Debug Authentication Control register when in secure state.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)\n{\n    return (DCB_NS->DAUTHCTRL);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    Debug Identification function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions\n  \\brief    Functions that access the Debug Identification Block.\n  @{\n */\n\n\n/**\n  \\brief   Get Debug Authentication Status Register\n  \\details Reads Debug Authentication Status register.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)\n{\n    return (DIB->DAUTHSTATUS);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Debug Authentication Status Register (non-secure)\n  \\details Reads non-secure Debug Authentication Status register when in secure state.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)\n{\n    return (DIB_NS->DAUTHSTATUS);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM55_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm7.h",
    "content": "/**************************************************************************//**\n * @file     core_cm7.h\n * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File\n * @version  V5.2.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM7_H_GENERIC\n#define __CORE_CM7_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M7\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM7 definitions */\n#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM7_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM7_H_DEPENDANT\n#define __CORE_CM7_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM7_REV\n    #define __CM7_REV               0x0000U\n    #warning \"__CM7_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ICACHE_PRESENT\n    #define __ICACHE_PRESENT          0U\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DCACHE_PRESENT\n    #define __DCACHE_PRESENT          0U\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DTCM_PRESENT\n    #define __DTCM_PRESENT            0U\n    #warning \"__DTCM_PRESENT        not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M7 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n        uint32_t RESERVED3[93U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */\n        uint32_t RESERVED7[5U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */\n\n#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */\n\n#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */\n\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\n\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\n\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* AHBP Control Register Definitions */\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\n\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< \\deprecated SCB CACR: ECCEN Position */\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< \\deprecated SCB CACR: ECCEN Mask */\n\n#define SCB_CACR_ECCDIS_Pos                 1U                                            /*!< SCB CACR: ECCDIS Position */\n#define SCB_CACR_ECCDIS_Msk                (1UL << SCB_CACR_ECCDIS_Pos)                   /*!< SCB CACR: ECCDIS Mask */\n\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\n\n/* AHBS Control Register Definitions */\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\n\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBSCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\n\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBSCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\n\n/* Auxiliary Bus Fault Status Register Definitions */\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\n\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\n\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\n\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\n\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\n\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISDYNADD_Pos         26U                                         /*!< ACTLR: DISDYNADD Position */\n#define SCnSCB_ACTLR_DISDYNADD_Msk         (1UL << SCnSCB_ACTLR_DISDYNADD_Pos)         /*!< ACTLR: DISDYNADD Mask */\n\n#define SCnSCB_ACTLR_DISISSCH1_Pos         21U                                         /*!< ACTLR: DISISSCH1 Position */\n#define SCnSCB_ACTLR_DISISSCH1_Msk         (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos)      /*!< ACTLR: DISISSCH1 Mask */\n\n#define SCnSCB_ACTLR_DISDI_Pos             16U                                         /*!< ACTLR: DISDI Position */\n#define SCnSCB_ACTLR_DISDI_Msk             (0x1FUL << SCnSCB_ACTLR_DISDI_Pos)          /*!< ACTLR: DISDI Mask */\n\n#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos     15U                                         /*!< ACTLR: DISCRITAXIRUR Position */\n#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk     (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos)     /*!< ACTLR: DISCRITAXIRUR Mask */\n\n#define SCnSCB_ACTLR_DISBTACALLOC_Pos      14U                                         /*!< ACTLR: DISBTACALLOC Position */\n#define SCnSCB_ACTLR_DISBTACALLOC_Msk      (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos)      /*!< ACTLR: DISBTACALLOC Mask */\n\n#define SCnSCB_ACTLR_DISBTACREAD_Pos       13U                                         /*!< ACTLR: DISBTACREAD Position */\n#define SCnSCB_ACTLR_DISBTACREAD_Msk       (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos)       /*!< ACTLR: DISBTACREAD Mask */\n\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */\n\n#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */\n#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */\n\n#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */\n#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_BYTEACC_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_BYTEACC_Msk                (1UL << ITM_LSR_BYTEACC_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_ACCESS_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_ACCESS_Msk                 (1UL << ITM_LSR_ACCESS_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_PRESENT_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_PRESENT_Msk                (1UL /*<< ITM_LSR_PRESENT_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED3[981U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and FP Feature Register 2 Definitions */\n\n#define FPU_MVFR2_VFP_Misc_Pos              4U                                            /*!< MVFR2: VFP Misc bits Position */\n#define FPU_MVFR2_VFP_Misc_Msk             (0xFUL << FPU_MVFR2_VFP_Misc_Pos)              /*!< MVFR2: VFP Misc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n\n/*@} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n\n/* Capitalize ITM_TCR Register Definitions */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_TraceBusID_Pos           (ITM_TCR_TRACEBUSID_Pos)     /*!< \\deprecated ITM_TCR_TraceBusID_Pos */\n#define ITM_TCR_TraceBusID_Msk           (ITM_TCR_TRACEBUSID_Msk)     /*!< \\deprecated ITM_TCR_TraceBusID_Msk */\n\n#define ITM_TCR_TSPrescale_Pos           (ITM_TCR_TSPRESCALE_Pos)     /*!< \\deprecated ITM_TCR_TSPrescale_Pos */\n#define ITM_TCR_TSPrescale_Msk           (ITM_TCR_TSPRESCALE_Msk)     /*!< \\deprecated ITM_TCR_TSPrescale_Msk */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos              (ITM_LSR_BYTEACC_Pos)        /*!< \\deprecated ITM_LSR_ByteAcc_Pos */\n#define ITM_LSR_ByteAcc_Msk              (ITM_LSR_BYTEACC_Msk)        /*!< \\deprecated ITM_LSR_ByteAcc_Msk */\n\n#define ITM_LSR_Access_Pos               (ITM_LSR_ACCESS_Pos)         /*!< \\deprecated ITM_LSR_Access_Pos */\n#define ITM_LSR_Access_Msk               (ITM_LSR_ACCESS_Msk)         /*!< \\deprecated ITM_LSR_Access_Msk */\n\n#define ITM_LSR_Present_Pos              (ITM_LSR_PRESENT_Pos)        /*!< \\deprecated ITM_LSR_Present_Pos */\n#define ITM_LSR_Present_Msk              (ITM_LSR_PRESENT_Msk)        /*!< \\deprecated ITM_LSR_Present_Msk */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = SCB->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n/* ##########################  Cache functions  #################################### */\n\n#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \\\n     (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))\n#include \"cachel1_armv7.h\"\n#endif\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM7_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_cm85.h",
    "content": "/**************************************************************************//**\n * @file     core_cm85.h\n * @brief    CMSIS Cortex-M85 Core Peripheral Access Layer Header File\n * @version  V1.3.1\n * @date     19. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2022-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include                        /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header                   /* treat file as system include file */\n#elif defined ( __GNUC__ )\n  #pragma GCC diagnostic ignored \"-Wpedantic\"   /* disable pedantic warning due to unnamed structs/unions */\n#endif\n\n#ifndef __CORE_CM85_H_GENERIC\n#define __CORE_CM85_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M85\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM85 definitions */\n\n#define __CORTEX_M                      (85U)                                 /*!< Cortex-M Core */\n\n#if defined ( __CC_ARM )\n  #error Legacy Arm Compiler does not support Armv8.1-M target architecture.\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED       0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED       0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM85_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM85_H_DEPENDANT\n#define __CORE_CM85_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM85_REV\n    #define __CM85_REV               0x0001U\n    #warning \"__CM85_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #if __FPU_PRESENT != 0U\n    #ifndef __FPU_DP\n      #define __FPU_DP             0U\n      #warning \"__FPU_DP not defined in device header file; using default!\"\n    #endif\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ICACHE_PRESENT\n    #define __ICACHE_PRESENT          0U\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DCACHE_PRESENT\n    #define __DCACHE_PRESENT          0U\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __PMU_PRESENT\n    #define __PMU_PRESENT             0U\n    #warning \"__PMU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #if __PMU_PRESENT != 0U\n    #ifndef __PMU_NUM_EVENTCNT\n      #define __PMU_NUM_EVENTCNT      8U\n      #warning \"__PMU_NUM_EVENTCNT not defined in device header file; using default!\"\n    #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2)\n    #error \"__PMU_NUM_EVENTCNT is out of range in device header file!\" */\n    #endif\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M85 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core EWIC Register\n  - Core EWIC Interrupt Status Access Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core PMU Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:1;               /*!< bit:     20  Reserved */\n    uint32_t B:1;                        /*!< bit:     21  BTI active       (read 0) */\n    uint32_t _reserved2:2;               /*!< bit: 22..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_B_Pos                         21U                                            /*!< xPSR: B Position */\n#define xPSR_B_Msk                         (1UL << xPSR_B_Pos)                            /*!< xPSR: B Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t BTI_EN:1;                   /*!< bit:      4  Privileged branch target identification enable */\n    uint32_t UBTI_EN:1;                  /*!< bit:      5  Unprivileged branch target identification enable */\n    uint32_t PAC_EN:1;                   /*!< bit:      6  Privileged pointer authentication enable */\n    uint32_t UPAC_EN:1;                  /*!< bit:      7  Unprivileged pointer authentication enable */\n    uint32_t _reserved1:24;              /*!< bit:  8..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_UPAC_EN_Pos                 7U                                            /*!< CONTROL: UPAC_EN Position */\n#define CONTROL_UPAC_EN_Msk                (1UL << CONTROL_UPAC_EN_Pos)                   /*!< CONTROL: UPAC_EN Mask */\n\n#define CONTROL_PAC_EN_Pos                  6U                                            /*!< CONTROL: PAC_EN Position */\n#define CONTROL_PAC_EN_Msk                 (1UL << CONTROL_PAC_EN_Pos)                    /*!< CONTROL: PAC_EN Mask */\n\n#define CONTROL_UBTI_EN_Pos                 5U                                            /*!< CONTROL: UBTI_EN Position */\n#define CONTROL_UBTI_EN_Msk                (1UL << CONTROL_UBTI_EN_Pos)                   /*!< CONTROL: UBTI_EN Mask */\n\n#define CONTROL_BTI_EN_Pos                  4U                                            /*!< CONTROL: BTI_EN Position */\n#define CONTROL_BTI_EN_Msk                 (1UL << CONTROL_BTI_EN_Pos)                    /*!< CONTROL: BTI_EN Mask */\n\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED7[21U];\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */\n        uint32_t RESERVED3[69U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n  __IOM uint32_t RFSR;                   /*!< Offset: 0x204 (R/W)  RAS Fault Status Register */\n        uint32_t RESERVED4[14U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n  __OM  uint32_t BPIALL;                 /*!< Offset: 0x278 ( /W)  Branch Predictor Invalidate All */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_IESB_Pos                  5U                                            /*!< SCB AIRCR: Implicit ESB Enable Position */\n#define SCB_AIRCR_IESB_Msk                 (1UL << SCB_AIRCR_IESB_Pos)                    /*!< SCB AIRCR: Implicit ESB Enable Mask */\n\n#define SCB_AIRCR_DIT_Pos                   4U                                            /*!< SCB AIRCR: Data Independent Timing Position */\n#define SCB_AIRCR_DIT_Msk                  (1UL << SCB_AIRCR_DIT_Pos)                     /*!< SCB AIRCR: Data Independent Timing Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_TRD_Pos                    20U                                            /*!< SCB CCR: TRD Position */\n#define SCB_CCR_TRD_Msk                    (1UL << SCB_CCR_TRD_Pos)                       /*!< SCB CCR: TRD Mask */\n\n#define SCB_CCR_LOB_Pos                    19U                                            /*!< SCB CCR: LOB Position */\n#define SCB_CCR_LOB_Msk                    (1UL << SCB_CCR_LOB_Pos)                       /*!< SCB CCR: LOB Mask */\n\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_PMU_Pos                    5U                                            /*!< SCB DFSR: PMU Position */\n#define SCB_DFSR_PMU_Msk                   (1UL << SCB_DFSR_PMU_Pos)                      /*!< SCB DFSR: PMU Mask */\n\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CP7_Pos                   7U                                            /*!< SCB NSACR: CP7 Position */\n#define SCB_NSACR_CP7_Msk                  (1UL << SCB_NSACR_CP7_Pos)                     /*!< SCB NSACR: CP7 Mask */\n\n#define SCB_NSACR_CP6_Pos                   6U                                            /*!< SCB NSACR: CP6 Position */\n#define SCB_NSACR_CP6_Msk                  (1UL << SCB_NSACR_CP6_Pos)                     /*!< SCB NSACR: CP6 Mask */\n\n#define SCB_NSACR_CP5_Pos                   5U                                            /*!< SCB NSACR: CP5 Position */\n#define SCB_NSACR_CP5_Msk                  (1UL << SCB_NSACR_CP5_Pos)                     /*!< SCB NSACR: CP5 Mask */\n\n#define SCB_NSACR_CP4_Pos                   4U                                            /*!< SCB NSACR: CP4 Position */\n#define SCB_NSACR_CP4_Msk                  (1UL << SCB_NSACR_CP4_Pos)                     /*!< SCB NSACR: CP4 Mask */\n\n#define SCB_NSACR_CP3_Pos                   3U                                            /*!< SCB NSACR: CP3 Position */\n#define SCB_NSACR_CP3_Msk                  (1UL << SCB_NSACR_CP3_Pos)                     /*!< SCB NSACR: CP3 Mask */\n\n#define SCB_NSACR_CP2_Pos                   2U                                            /*!< SCB NSACR: CP2 Position */\n#define SCB_NSACR_CP2_Msk                  (1UL << SCB_NSACR_CP2_Pos)                     /*!< SCB NSACR: CP2 Mask */\n\n#define SCB_NSACR_CP1_Pos                   1U                                            /*!< SCB NSACR: CP1 Position */\n#define SCB_NSACR_CP1_Msk                  (1UL << SCB_NSACR_CP1_Pos)                     /*!< SCB NSACR: CP1 Mask */\n\n#define SCB_NSACR_CP0_Pos                   0U                                            /*!< SCB NSACR: CP0 Position */\n#define SCB_NSACR_CP0_Msk                  (1UL /*<< SCB_NSACR_CP0_Pos*/)                 /*!< SCB NSACR: CP0 Mask */\n\n/* SCB Debug Feature Register 0 Definitions */\n#define SCB_ID_DFR_UDE_Pos                 28U                                            /*!< SCB ID_DFR: UDE Position */\n#define SCB_ID_DFR_UDE_Msk                 (0xFUL << SCB_ID_DFR_UDE_Pos)                  /*!< SCB ID_DFR: UDE Mask */\n\n#define SCB_ID_DFR_MProfDbg_Pos            20U                                            /*!< SCB ID_DFR: MProfDbg Position */\n#define SCB_ID_DFR_MProfDbg_Msk            (0xFUL << SCB_ID_DFR_MProfDbg_Pos)             /*!< SCB ID_DFR: MProfDbg Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB RAS Fault Status Register Definitions */\n#define SCB_RFSR_V_Pos                     31U                                            /*!< SCB RFSR: V Position */\n#define SCB_RFSR_V_Msk                     (1UL << SCB_RFSR_V_Pos)                        /*!< SCB RFSR: V Mask */\n\n#define SCB_RFSR_IS_Pos                    16U                                            /*!< SCB RFSR: IS Position */\n#define SCB_RFSR_IS_Msk                    (0x7FFFUL << SCB_RFSR_IS_Pos)                  /*!< SCB RFSR: IS Mask */\n\n#define SCB_RFSR_UET_Pos                    0U                                            /*!< SCB RFSR: UET Position */\n#define SCB_RFSR_UET_Msk                   (3UL /*<< SCB_RFSR_UET_Pos*/)                  /*!< SCB RFSR: UET Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ICB Implementation Control Block register (ICB)\n  \\brief    Type definitions for the Implementation Control Block Register\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Implementation Control Block (ICB).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} ICB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define ICB_ACTLR_DISCRITAXIRUW_Pos     27U                                               /*!< ACTLR: DISCRITAXIRUW Position */\n#define ICB_ACTLR_DISCRITAXIRUW_Msk     (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)              /*!< ACTLR: DISCRITAXIRUW Mask */\n\n#define ICB_ACTLR_DISCRITAXIRUR_Pos     15U                                               /*!< ACTLR: DISCRITAXIRUR Position */\n#define ICB_ACTLR_DISCRITAXIRUR_Msk     (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)              /*!< ACTLR: DISCRITAXIRUR Mask */\n\n#define ICB_ACTLR_EVENTBUSEN_Pos        14U                                               /*!< ACTLR: EVENTBUSEN Position */\n#define ICB_ACTLR_EVENTBUSEN_Msk        (1UL << ICB_ACTLR_EVENTBUSEN_Pos)                 /*!< ACTLR: EVENTBUSEN Mask */\n\n#define ICB_ACTLR_EVENTBUSEN_S_Pos      13U                                               /*!< ACTLR: EVENTBUSEN_S Position */\n#define ICB_ACTLR_EVENTBUSEN_S_Msk      (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)               /*!< ACTLR: EVENTBUSEN_S Mask */\n\n#define ICB_ACTLR_DISITMATBFLUSH_Pos    12U                                               /*!< ACTLR: DISITMATBFLUSH Position */\n#define ICB_ACTLR_DISITMATBFLUSH_Msk    (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)             /*!< ACTLR: DISITMATBFLUSH Mask */\n\n#define ICB_ACTLR_DISNWAMODE_Pos        11U                                               /*!< ACTLR: DISNWAMODE Position */\n#define ICB_ACTLR_DISNWAMODE_Msk        (1UL << ICB_ACTLR_DISNWAMODE_Pos)                 /*!< ACTLR: DISNWAMODE Mask */\n\n#define ICB_ACTLR_FPEXCODIS_Pos         10U                                               /*!< ACTLR: FPEXCODIS Position */\n#define ICB_ACTLR_FPEXCODIS_Msk         (1UL << ICB_ACTLR_FPEXCODIS_Pos)                  /*!< ACTLR: FPEXCODIS Mask */\n\n/* Interrupt Controller Type Register Definitions */\n#define ICB_ICTR_INTLINESNUM_Pos         0U                                               /*!< ICTR: INTLINESNUM Position */\n#define ICB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)           /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_ICB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[27U];\n  __IM  uint32_t ITREAD;                 /*!< Offset: 0xEF0 (R/ )  ITM Integration Read Register */\n        uint32_t RESERVED4[1U];\n  __OM  uint32_t ITWRITE;                /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED6[46U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED7[3U];\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  ITM Device Type Register */\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_ITREAD_AFVALID_Pos              1U                                            /*!< ITM ITREAD: AFVALID Position */\n#define ITM_ITREAD_AFVALID_Msk             (0x1UL << ITM_ITREAD_AFVALID_Pos)              /*!< ITM ITREAD: AFVALID Mask */\n\n#define ITM_ITREAD_ATREADY_Pos              0U                                            /*!< ITM ITREAD: ATREADY Position */\n#define ITM_ITREAD_ATREADY_Msk             (0x1UL /*<< ITM_ITREAD_ATREADY_Pos*/)          /*!< ITM ITREAD: ATREADY Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_ITWRITE_AFVALID_Pos             1U                                            /*!< ITM ITWRITE: AFVALID Position */\n#define ITM_ITWRITE_AFVALID_Msk            (0x1UL << ITM_ITWRITE_AFVALID_Pos)             /*!< ITM ITWRITE: AFVALID Mask */\n\n#define ITM_ITWRITE_ATREADY_Pos             0U                                            /*!< ITM ITWRITE: ATREADY Position */\n#define ITM_ITWRITE_ATREADY_Msk            (0x1UL /*<< ITM_ITWRITE_ATREADY_Pos*/)         /*!< ITM ITWRITE: ATREADY Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_ITCTRL_IME_Pos                  0U                                            /*!< ITM ITCTRL: IME Position */\n#define ITM_ITCTRL_IME_Msk                 (0x1UL /*<< ITM_ITCTRL_IME_Pos*/)              /*!< ITM ITCTRL: IME Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n  __IOM uint32_t VMASK1;                 /*!< Offset: 0x03C (R/W)  Comparator Value Mask 1 */\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n  __IOM uint32_t VMASK3;                 /*!< Offset: 0x05C (R/W)  Comparator Value Mask 3 */\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED14[968U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Type Architecture Register */\n        uint32_t RESERVED15[3U];\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup MemSysCtl_Type     Memory System Control Registers (IMPLEMENTATION DEFINED)\n  \\brief    Type definitions for the Memory System Control Registers (MEMSYSCTL)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory System Control Registers (MEMSYSCTL).\n */\ntypedef struct\n{\n  __IOM uint32_t MSCR;                   /*!< Offset: 0x000 (R/W)  Memory System Control Register */\n  __IOM uint32_t PFCR;                   /*!< Offset: 0x004 (R/W)  Prefetcher Control Register */\n        uint32_t RESERVED1[2U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x010 (R/W)  ITCM Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x014 (R/W)  DTCM Control Register */\n  __IOM uint32_t PAHBCR;                 /*!< Offset: 0x018 (R/W)  P-AHB Control Register */\n        uint32_t RESERVED2[313U];\n  __IOM uint32_t ITGU_CTRL;              /*!< Offset: 0x500 (R/W)  ITGU Control Register */\n  __IOM uint32_t ITGU_CFG;               /*!< Offset: 0x504 (R/W)  ITGU Configuration Register */\n        uint32_t RESERVED3[2U];\n  __IOM uint32_t ITGU_LUT[16U];          /*!< Offset: 0x510 (R/W)  ITGU Look Up Table Register */\n        uint32_t RESERVED4[44U];\n  __IOM uint32_t DTGU_CTRL;              /*!< Offset: 0x600 (R/W)  DTGU Control Registers */\n  __IOM uint32_t DTGU_CFG;               /*!< Offset: 0x604 (R/W)  DTGU Configuration Register */\n        uint32_t RESERVED5[2U];\n  __IOM uint32_t DTGU_LUT[16U];          /*!< Offset: 0x610 (R/W)  DTGU Look Up Table Register */\n} MemSysCtl_Type;\n\n/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */\n#define MEMSYSCTL_MSCR_CPWRDN_Pos          17U                                         /*!< MEMSYSCTL MSCR: CPWRDN Position */\n#define MEMSYSCTL_MSCR_CPWRDN_Msk          (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)        /*!< MEMSYSCTL MSCR: CPWRDN Mask */\n\n#define MEMSYSCTL_MSCR_DCCLEAN_Pos         16U                                         /*!< MEMSYSCTL MSCR: DCCLEAN Position */\n#define MEMSYSCTL_MSCR_DCCLEAN_Msk         (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)       /*!< MEMSYSCTL MSCR: DCCLEAN Mask */\n\n#define MEMSYSCTL_MSCR_ICACTIVE_Pos        13U                                         /*!< MEMSYSCTL MSCR: ICACTIVE Position */\n#define MEMSYSCTL_MSCR_ICACTIVE_Msk        (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)      /*!< MEMSYSCTL MSCR: ICACTIVE Mask */\n\n#define MEMSYSCTL_MSCR_DCACTIVE_Pos        12U                                         /*!< MEMSYSCTL MSCR: DCACTIVE Position */\n#define MEMSYSCTL_MSCR_DCACTIVE_Msk        (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)      /*!< MEMSYSCTL MSCR: DCACTIVE Mask */\n\n#define MEMSYSCTL_MSCR_EVECCFAULT_Pos       3U                                         /*!< MEMSYSCTL MSCR: EVECCFAULT Position */\n#define MEMSYSCTL_MSCR_EVECCFAULT_Msk      (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)    /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */\n\n#define MEMSYSCTL_MSCR_FORCEWT_Pos          2U                                         /*!< MEMSYSCTL MSCR: FORCEWT Position */\n#define MEMSYSCTL_MSCR_FORCEWT_Msk         (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)       /*!< MEMSYSCTL MSCR: FORCEWT Mask */\n\n#define MEMSYSCTL_MSCR_ECCEN_Pos            1U                                         /*!< MEMSYSCTL MSCR: ECCEN Position */\n#define MEMSYSCTL_MSCR_ECCEN_Msk           (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)         /*!< MEMSYSCTL MSCR: ECCEN Mask */\n\n/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */\n#define MEMSYSCTL_PFCR_DIS_NLP_Pos          7U                                         /*!< MEMSYSCTL PFCR: DIS_NLP Position */\n#define MEMSYSCTL_PFCR_DIS_NLP_Msk         (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)       /*!< MEMSYSCTL PFCR: DIS_NLP Mask */\n\n#define MEMSYSCTL_PFCR_ENABLE_Pos           0U                                         /*!< MEMSYSCTL PFCR: ENABLE Position */\n#define MEMSYSCTL_PFCR_ENABLE_Msk          (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)    /*!< MEMSYSCTL PFCR: ENABLE Mask */\n\n/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */\n#define MEMSYSCTL_ITCMCR_SZ_Pos             3U                                         /*!< MEMSYSCTL ITCMCR: SZ Position */\n#define MEMSYSCTL_ITCMCR_SZ_Msk            (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)          /*!< MEMSYSCTL ITCMCR: SZ Mask */\n\n#define MEMSYSCTL_ITCMCR_EN_Pos             0U                                         /*!< MEMSYSCTL ITCMCR: EN Position */\n#define MEMSYSCTL_ITCMCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)      /*!< MEMSYSCTL ITCMCR: EN Mask */\n\n/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */\n#define MEMSYSCTL_DTCMCR_SZ_Pos             3U                                         /*!< MEMSYSCTL DTCMCR: SZ Position */\n#define MEMSYSCTL_DTCMCR_SZ_Msk            (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)          /*!< MEMSYSCTL DTCMCR: SZ Mask */\n\n#define MEMSYSCTL_DTCMCR_EN_Pos             0U                                         /*!< MEMSYSCTL DTCMCR: EN Position */\n#define MEMSYSCTL_DTCMCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)      /*!< MEMSYSCTL DTCMCR: EN Mask */\n\n/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */\n#define MEMSYSCTL_PAHBCR_SZ_Pos             1U                                         /*!< MEMSYSCTL PAHBCR: SZ Position */\n#define MEMSYSCTL_PAHBCR_SZ_Msk            (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)          /*!< MEMSYSCTL PAHBCR: SZ Mask */\n\n#define MEMSYSCTL_PAHBCR_EN_Pos             0U                                         /*!< MEMSYSCTL PAHBCR: EN Position */\n#define MEMSYSCTL_PAHBCR_EN_Msk            (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)      /*!< MEMSYSCTL PAHBCR: EN Mask */\n\n/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */\n#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos       1U                                         /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */\n#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk      (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)    /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */\n\n#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos       0U                                         /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */\n#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk      (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */\n\n/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */\n#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos     31U                                         /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */\n#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk     (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)   /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */\n\n#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos      8U                                         /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */\n#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk     (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)   /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */\n\n#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos        0U                                         /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */\n#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk       (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */\n\n/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */\n#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos       1U                                         /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */\n#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk      (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)    /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */\n\n#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos       0U                                         /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */\n#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk      (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */\n\n/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */\n#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos     31U                                         /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */\n#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk     (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)   /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */\n\n#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos      8U                                         /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */\n#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk     (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)   /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */\n\n#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos        0U                                         /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */\n#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk       (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */\n\n\n/*@}*/ /* end of group MemSysCtl_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup PwrModCtl_Type     Power Mode Control Registers\n  \\brief    Type definitions for the Power Mode Control Registers (PWRMODCTL)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Power Mode Control Registers (PWRMODCTL).\n */\ntypedef struct\n{\n  __IOM uint32_t CPDLPSTATE;             /*!< Offset: 0x000 (R/W)  Core Power Domain Low Power State Register */\n  __IOM uint32_t DPDLPSTATE;             /*!< Offset: 0x004 (R/W)  Debug Power Domain Low Power State Register */\n} PwrModCtl_Type;\n\n/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */\n#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U                                              /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */\n#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk  (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)     /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */\n\n#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U                                              /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */\n#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk  (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)     /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */\n\n#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U                                              /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */\n#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */\n\n/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */\n#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U                                              /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */\n#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk  (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */\n\n/*@}*/ /* end of group PwrModCtl_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup EWIC_Type     External Wakeup Interrupt Controller Registers\n  \\brief    Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).\n */\ntypedef struct\n{\n  __IOM uint32_t EWIC_CR;                /*!< Offset: 0x000 (R/W)  EWIC Control Register */\n  __IOM uint32_t EWIC_ASCR;              /*!< Offset: 0x004 (R/W)  EWIC Automatic Sequence Control Register */\n  __OM  uint32_t EWIC_CLRMASK;           /*!< Offset: 0x008 ( /W)  EWIC Clear Mask Register */\n  __IM  uint32_t EWIC_NUMID;             /*!< Offset: 0x00C (R/ )  EWIC Event Number ID Register */\n        uint32_t RESERVED0[124U];\n  __IOM uint32_t EWIC_MASKA;             /*!< Offset: 0x200 (R/W)  EWIC MaskA Register */\n  __IOM uint32_t EWIC_MASKn[15];         /*!< Offset: 0x204 (R/W)  EWIC Maskn Registers */\n        uint32_t RESERVED1[112U];\n  __IM  uint32_t EWIC_PENDA;             /*!< Offset: 0x400 (R/ )  EWIC PendA Event Register */\n  __IOM uint32_t EWIC_PENDn[15];         /*!< Offset: 0x404 (R/W)  EWIC Pendn Event Registers */\n        uint32_t RESERVED2[112U];\n  __IM  uint32_t EWIC_PSR;               /*!< Offset: 0x600 (R/ )  EWIC Pend Summary Register */\n} EWIC_Type;\n\n/* EWIC Control (EWIC_CR) Register Definitions */\n#define EWIC_EWIC_CR_EN_Pos                 0U                                         /*!< EWIC EWIC_CR: EN Position */\n#define EWIC_EWIC_CR_EN_Msk                (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/)          /*!< EWIC EWIC_CR: EN Mask */\n\n/* EWIC Automatic Sequence Control (EWIC_ASCR) Register Definitions */\n#define EWIC_EWIC_ASCR_ASPU_Pos             1U                                         /*!< EWIC EWIC_ASCR: ASPU Position */\n#define EWIC_EWIC_ASCR_ASPU_Msk            (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos)          /*!< EWIC EWIC_ASCR: ASPU Mask */\n\n#define EWIC_EWIC_ASCR_ASPD_Pos             0U                                         /*!< EWIC EWIC_ASCR: ASPD Position */\n#define EWIC_EWIC_ASCR_ASPD_Msk            (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/)      /*!< EWIC EWIC_ASCR: ASPD Mask */\n\n/* EWIC Event Number ID (EWIC_NUMID) Register Definitions */\n#define EWIC_EWIC_NUMID_NUMEVENT_Pos        0U                                         /*!< EWIC_NUMID: NUMEVENT Position */\n#define EWIC_EWIC_NUMID_NUMEVENT_Msk       (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */\n\n/* EWIC MaskA (EWIC_MASKA) Register Definitions */\n#define EWIC_EWIC_MASKA_EDBGREQ_Pos         2U                                         /*!< EWIC EWIC_MASKA: EDBGREQ Position */\n#define EWIC_EWIC_MASKA_EDBGREQ_Msk        (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos)      /*!< EWIC EWIC_MASKA: EDBGREQ Mask */\n\n#define EWIC_EWIC_MASKA_NMI_Pos             1U                                         /*!< EWIC EWIC_MASKA: NMI Position */\n#define EWIC_EWIC_MASKA_NMI_Msk            (0x1UL << EWIC_EWIC_MASKA_NMI_Pos)          /*!< EWIC EWIC_MASKA: NMI Mask */\n\n#define EWIC_EWIC_MASKA_EVENT_Pos           0U                                         /*!< EWIC EWIC_MASKA: EVENT Position */\n#define EWIC_EWIC_MASKA_EVENT_Msk          (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/)    /*!< EWIC EWIC_MASKA: EVENT Mask */\n\n/* EWIC Mask n (EWIC_MASKn) Register Definitions */\n#define EWIC_EWIC_MASKn_IRQ_Pos             0U                                           /*!< EWIC EWIC_MASKn: IRQ Position */\n#define EWIC_EWIC_MASKn_IRQ_Msk            (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */\n\n/* EWIC PendA (EWIC_PENDA) Register Definitions */\n#define EWIC_EWIC_PENDA_EDBGREQ_Pos         2U                                         /*!< EWIC EWIC_PENDA: EDBGREQ Position */\n#define EWIC_EWIC_PENDA_EDBGREQ_Msk        (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos)      /*!< EWIC EWIC_PENDA: EDBGREQ Mask */\n\n#define EWIC_EWIC_PENDA_NMI_Pos             1U                                         /*!< EWIC EWIC_PENDA: NMI Position */\n#define EWIC_EWIC_PENDA_NMI_Msk            (0x1UL << EWIC_EWIC_PENDA_NMI_Pos)          /*!< EWIC EWIC_PENDA: NMI Mask */\n\n#define EWIC_EWIC_PENDA_EVENT_Pos           0U                                         /*!< EWIC EWIC_PENDA: EVENT Position */\n#define EWIC_EWIC_PENDA_EVENT_Msk          (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/)    /*!< EWIC EWIC_PENDA: EVENT Mask */\n\n/* EWIC Pend n (EWIC_PENDn) Register Definitions */\n#define EWIC_EWIC_PENDn_IRQ_Pos             0U                                           /*!< EWIC EWIC_PENDn: IRQ Position */\n#define EWIC_EWIC_PENDn_IRQ_Msk            (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */\n\n/* EWIC Pend Summary (EWIC_PSR) Register Definitions */\n#define EWIC_EWIC_PSR_NZ_Pos                1U                                         /*!< EWIC EWIC_PSR: NZ Position */\n#define EWIC_EWIC_PSR_NZ_Msk               (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos)          /*!< EWIC EWIC_PSR: NZ Mask */\n\n#define EWIC_EWIC_PSR_NZA_Pos               0U                                         /*!< EWIC EWIC_PSR: NZA Position */\n#define EWIC_EWIC_PSR_NZA_Msk              (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/)        /*!< EWIC EWIC_PSR: NZA Mask */\n\n/*@}*/ /* end of group EWIC_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup EWIC_ISA_Type     External Wakeup Interrupt Controller (EWIC) interrupt status access registers\n  \\brief    Type definitions for the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the External Wakeup Interrupt Controller interrupt status access registers (EWIC_ISA).\n */\ntypedef struct\n{\n  __OM  uint32_t EVENTSPR;               /*!< Offset: 0x000 ( /W)  Event Set Pending Register */\n        uint32_t RESERVED0[31U];\n  __IM  uint32_t EVENTMASKA;             /*!< Offset: 0x080 (R/ )  Event Mask A Register */\n  __IM  uint32_t EVENTMASKn[15];         /*!< Offset: 0x084 (R/ )  Event Mask Register */\n} EWIC_ISA_Type;\n\n/* EWIC_ISA Event Set Pending (EVENTSPR) Register Definitions */\n#define EWIC_ISA_EVENTSPR_EDBGREQ_Pos   2U                                             /*!< EWIC_ISA EVENTSPR: EDBGREQ Position */\n#define EWIC_ISA_EVENTSPR_EDBGREQ_Msk  (0x1UL << EWIC_ISA_EVENTSPR_EDBGREQ_Pos)        /*!< EWIC_ISA EVENTSPR: EDBGREQ Mask */\n\n#define EWIC_ISA_EVENTSPR_NMI_Pos   1U                                                 /*!< EWIC_ISA EVENTSPR: NMI Position */\n#define EWIC_ISA_EVENTSPR_NMI_Msk  (0x1UL << EWIC_ISA_EVENTSPR_NMI_Pos)                /*!< EWIC_ISA EVENTSPR: NMI Mask */\n\n#define EWIC_ISA_EVENTSPR_EVENT_Pos   0U                                               /*!< EWIC_ISA EVENTSPR: EVENT Position */\n#define EWIC_ISA_EVENTSPR_EVENT_Msk  (0x1UL /*<< EWIC_ISA_EVENTSPR_EVENT_Pos*/)        /*!< EWIC_ISA EVENTSPR: EVENT Mask */\n\n/* EWIC_ISA Event Mask A (EVENTMASKA) Register Definitions */\n#define EWIC_ISA_EVENTMASKA_EDBGREQ_Pos   2U                                           /*!< EWIC_ISA EVENTMASKA: EDBGREQ Position */\n#define EWIC_ISA_EVENTMASKA_EDBGREQ_Msk  (0x1UL << EWIC_ISA_EVENTMASKA_EDBGREQ_Pos)    /*!< EWIC_ISA EVENTMASKA: EDBGREQ Mask */\n\n#define EWIC_ISA_EVENTMASKA_NMI_Pos   1U                                               /*!< EWIC_ISA EVENTMASKA: NMI Position */\n#define EWIC_ISA_EVENTMASKA_NMI_Msk  (0x1UL << EWIC_ISA_EVENTMASKA_NMI_Pos)            /*!< EWIC_ISA EVENTMASKA: NMI Mask */\n\n#define EWIC_ISA_EVENTMASKA_EVENT_Pos   0U                                             /*!< EWIC_ISA EVENTMASKA: EVENT Position */\n#define EWIC_ISA_EVENTMASKA_EVENT_Msk  (0x1UL /*<< EWIC_ISA_EVENTMASKA_EVENT_Pos*/)    /*!< EWIC_ISA EVENTMASKA: EVENT Mask */\n\n/* EWIC_ISA Event Mask n (EVENTMASKn) Register Definitions */\n#define EWIC_ISA_EVENTMASKn_IRQ_Pos   0U                                                /*!< EWIC_ISA EVENTMASKn: IRQ Position */\n#define EWIC_ISA_EVENTMASKn_IRQ_Msk  (0xFFFFFFFFUL /*<< EWIC_ISA_EVENTMASKn_IRQ_Pos*/)  /*!< EWIC_ISA EVENTMASKn: IRQ Mask */\n\n/*@}*/ /* end of group EWIC_ISA_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup ErrBnk_Type     Error Banking Registers (IMPLEMENTATION DEFINED)\n  \\brief    Type definitions for the Error Banking Registers (ERRBNK)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Error Banking Registers (ERRBNK).\n */\ntypedef struct\n{\n  __IOM uint32_t IEBR0;                  /*!< Offset: 0x000 (R/W)  Instruction Cache Error Bank Register 0 */\n  __IOM uint32_t IEBR1;                  /*!< Offset: 0x004 (R/W)  Instruction Cache Error Bank Register 1 */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t DEBR0;                  /*!< Offset: 0x010 (R/W)  Data Cache Error Bank Register 0 */\n  __IOM uint32_t DEBR1;                  /*!< Offset: 0x014 (R/W)  Data Cache Error Bank Register 1 */\n        uint32_t RESERVED1[2U];\n  __IOM uint32_t TEBR0;                  /*!< Offset: 0x020 (R/W)  TCM Error Bank Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t TEBR1;                  /*!< Offset: 0x028 (R/W)  TCM Error Bank Register 1 */\n} ErrBnk_Type;\n\n/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */\n#define ERRBNK_IEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK IEBR0: SWDEF Position */\n#define ERRBNK_IEBR0_SWDEF_Msk             (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)           /*!< ERRBNK IEBR0: SWDEF Mask */\n\n#define ERRBNK_IEBR0_BANK_Pos              16U                                         /*!< ERRBNK IEBR0: BANK Position */\n#define ERRBNK_IEBR0_BANK_Msk              (0x1UL << ERRBNK_IEBR0_BANK_Pos)            /*!< ERRBNK IEBR0: BANK Mask */\n\n#define ERRBNK_IEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK IEBR0: LOCATION Position */\n#define ERRBNK_IEBR0_LOCATION_Msk          (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)     /*!< ERRBNK IEBR0: LOCATION Mask */\n\n#define ERRBNK_IEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK IEBR0: LOCKED Position */\n#define ERRBNK_IEBR0_LOCKED_Msk            (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)          /*!< ERRBNK IEBR0: LOCKED Mask */\n\n#define ERRBNK_IEBR0_VALID_Pos              0U                                         /*!< ERRBNK IEBR0: VALID Position */\n#define ERRBNK_IEBR0_VALID_Msk             (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)       /*!< ERRBNK IEBR0: VALID Mask */\n\n/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */\n#define ERRBNK_IEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK IEBR1: SWDEF Position */\n#define ERRBNK_IEBR1_SWDEF_Msk             (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)           /*!< ERRBNK IEBR1: SWDEF Mask */\n\n#define ERRBNK_IEBR1_BANK_Pos              16U                                         /*!< ERRBNK IEBR1: BANK Position */\n#define ERRBNK_IEBR1_BANK_Msk              (0x1UL << ERRBNK_IEBR1_BANK_Pos)            /*!< ERRBNK IEBR1: BANK Mask */\n\n#define ERRBNK_IEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK IEBR1: LOCATION Position */\n#define ERRBNK_IEBR1_LOCATION_Msk          (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)     /*!< ERRBNK IEBR1: LOCATION Mask */\n\n#define ERRBNK_IEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK IEBR1: LOCKED Position */\n#define ERRBNK_IEBR1_LOCKED_Msk            (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)          /*!< ERRBNK IEBR1: LOCKED Mask */\n\n#define ERRBNK_IEBR1_VALID_Pos              0U                                         /*!< ERRBNK IEBR1: VALID Position */\n#define ERRBNK_IEBR1_VALID_Msk             (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)       /*!< ERRBNK IEBR1: VALID Mask */\n\n/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */\n#define ERRBNK_DEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK DEBR0: SWDEF Position */\n#define ERRBNK_DEBR0_SWDEF_Msk             (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)           /*!< ERRBNK DEBR0: SWDEF Mask */\n\n#define ERRBNK_DEBR0_TYPE_Pos              17U                                         /*!< ERRBNK DEBR0: TYPE Position */\n#define ERRBNK_DEBR0_TYPE_Msk              (0x1UL << ERRBNK_DEBR0_TYPE_Pos)            /*!< ERRBNK DEBR0: TYPE Mask */\n\n#define ERRBNK_DEBR0_BANK_Pos              16U                                         /*!< ERRBNK DEBR0: BANK Position */\n#define ERRBNK_DEBR0_BANK_Msk              (0x1UL << ERRBNK_DEBR0_BANK_Pos)            /*!< ERRBNK DEBR0: BANK Mask */\n\n#define ERRBNK_DEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK DEBR0: LOCATION Position */\n#define ERRBNK_DEBR0_LOCATION_Msk          (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)     /*!< ERRBNK DEBR0: LOCATION Mask */\n\n#define ERRBNK_DEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK DEBR0: LOCKED Position */\n#define ERRBNK_DEBR0_LOCKED_Msk            (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)          /*!< ERRBNK DEBR0: LOCKED Mask */\n\n#define ERRBNK_DEBR0_VALID_Pos              0U                                         /*!< ERRBNK DEBR0: VALID Position */\n#define ERRBNK_DEBR0_VALID_Msk             (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)       /*!< ERRBNK DEBR0: VALID Mask */\n\n/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */\n#define ERRBNK_DEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK DEBR1: SWDEF Position */\n#define ERRBNK_DEBR1_SWDEF_Msk             (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)           /*!< ERRBNK DEBR1: SWDEF Mask */\n\n#define ERRBNK_DEBR1_TYPE_Pos              17U                                         /*!< ERRBNK DEBR1: TYPE Position */\n#define ERRBNK_DEBR1_TYPE_Msk              (0x1UL << ERRBNK_DEBR1_TYPE_Pos)            /*!< ERRBNK DEBR1: TYPE Mask */\n\n#define ERRBNK_DEBR1_BANK_Pos              16U                                         /*!< ERRBNK DEBR1: BANK Position */\n#define ERRBNK_DEBR1_BANK_Msk              (0x1UL << ERRBNK_DEBR1_BANK_Pos)            /*!< ERRBNK DEBR1: BANK Mask */\n\n#define ERRBNK_DEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK DEBR1: LOCATION Position */\n#define ERRBNK_DEBR1_LOCATION_Msk          (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)     /*!< ERRBNK DEBR1: LOCATION Mask */\n\n#define ERRBNK_DEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK DEBR1: LOCKED Position */\n#define ERRBNK_DEBR1_LOCKED_Msk            (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)          /*!< ERRBNK DEBR1: LOCKED Mask */\n\n#define ERRBNK_DEBR1_VALID_Pos              0U                                         /*!< ERRBNK DEBR1: VALID Position */\n#define ERRBNK_DEBR1_VALID_Msk             (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)       /*!< ERRBNK DEBR1: VALID Mask */\n\n/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */\n#define ERRBNK_TEBR0_SWDEF_Pos             30U                                         /*!< ERRBNK TEBR0: SWDEF Position */\n#define ERRBNK_TEBR0_SWDEF_Msk             (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)           /*!< ERRBNK TEBR0: SWDEF Mask */\n\n#define ERRBNK_TEBR0_POISON_Pos            28U                                         /*!< ERRBNK TEBR0: POISON Position */\n#define ERRBNK_TEBR0_POISON_Msk            (0x1UL << ERRBNK_TEBR0_POISON_Pos)          /*!< ERRBNK TEBR0: POISON Mask */\n\n#define ERRBNK_TEBR0_TYPE_Pos              27U                                         /*!< ERRBNK TEBR0: TYPE Position */\n#define ERRBNK_TEBR0_TYPE_Msk              (0x1UL << ERRBNK_TEBR0_TYPE_Pos)            /*!< ERRBNK TEBR0: TYPE Mask */\n\n#define ERRBNK_TEBR0_BANK_Pos              24U                                         /*!< ERRBNK TEBR0: BANK Position */\n#define ERRBNK_TEBR0_BANK_Msk              (0x7UL << ERRBNK_TEBR0_BANK_Pos)            /*!< ERRBNK TEBR0: BANK Mask */\n\n#define ERRBNK_TEBR0_LOCATION_Pos           2U                                         /*!< ERRBNK TEBR0: LOCATION Position */\n#define ERRBNK_TEBR0_LOCATION_Msk          (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)   /*!< ERRBNK TEBR0: LOCATION Mask */\n\n#define ERRBNK_TEBR0_LOCKED_Pos             1U                                         /*!< ERRBNK TEBR0: LOCKED Position */\n#define ERRBNK_TEBR0_LOCKED_Msk            (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)          /*!< ERRBNK TEBR0: LOCKED Mask */\n\n#define ERRBNK_TEBR0_VALID_Pos              0U                                         /*!< ERRBNK TEBR0: VALID Position */\n#define ERRBNK_TEBR0_VALID_Msk             (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)       /*!< ERRBNK TEBR0: VALID Mask */\n\n/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */\n#define ERRBNK_TEBR1_SWDEF_Pos             30U                                         /*!< ERRBNK TEBR1: SWDEF Position */\n#define ERRBNK_TEBR1_SWDEF_Msk             (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)           /*!< ERRBNK TEBR1: SWDEF Mask */\n\n#define ERRBNK_TEBR1_POISON_Pos            28U                                         /*!< ERRBNK TEBR1: POISON Position */\n#define ERRBNK_TEBR1_POISON_Msk            (0x1UL << ERRBNK_TEBR1_POISON_Pos)          /*!< ERRBNK TEBR1: POISON Mask */\n\n#define ERRBNK_TEBR1_TYPE_Pos              27U                                         /*!< ERRBNK TEBR1: TYPE Position */\n#define ERRBNK_TEBR1_TYPE_Msk              (0x1UL << ERRBNK_TEBR1_TYPE_Pos)            /*!< ERRBNK TEBR1: TYPE Mask */\n\n#define ERRBNK_TEBR1_BANK_Pos              24U                                         /*!< ERRBNK TEBR1: BANK Position */\n#define ERRBNK_TEBR1_BANK_Msk              (0x7UL << ERRBNK_TEBR1_BANK_Pos)            /*!< ERRBNK TEBR1: BANK Mask */\n\n#define ERRBNK_TEBR1_LOCATION_Pos           2U                                         /*!< ERRBNK TEBR1: LOCATION Position */\n#define ERRBNK_TEBR1_LOCATION_Msk          (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)   /*!< ERRBNK TEBR1: LOCATION Mask */\n\n#define ERRBNK_TEBR1_LOCKED_Pos             1U                                         /*!< ERRBNK TEBR1: LOCKED Position */\n#define ERRBNK_TEBR1_LOCKED_Msk            (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)          /*!< ERRBNK TEBR1: LOCKED Mask */\n\n#define ERRBNK_TEBR1_VALID_Pos              0U                                         /*!< ERRBNK TEBR1: VALID Position */\n#define ERRBNK_TEBR1_VALID_Msk             (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)       /*!< ERRBNK TEBR1: VALID Mask */\n\n/*@}*/ /* end of group ErrBnk_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup PrcCfgInf_Type     Processor Configuration Information Registers (IMPLEMENTATION DEFINED)\n  \\brief    Type definitions for the Processor Configuration Information Registerss (PRCCFGINF)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Processor Configuration Information Registerss (PRCCFGINF).\n */\ntypedef struct\n{\n  __OM  uint32_t CFGINFOSEL;             /*!< Offset: 0x000 ( /W)  Processor Configuration Information Selection Register */\n  __IM  uint32_t CFGINFORD;              /*!< Offset: 0x004 (R/ )  Processor Configuration Information Read Data Register */\n} PrcCfgInf_Type;\n\n/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */\n\n/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */\n\n/*@}*/ /* end of group PrcCfgInf_Type */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFmt_Pos                  0U                                         /*!< TPI FFCR: EnFmt Position */\n#define TPI_FFCR_EnFmt_Msk                 (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)           /*!< TPI FFCR: EnFmt Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_PMU     Performance Monitoring Unit (PMU)\n  \\brief    Type definitions for the Performance Monitoring Unit (PMU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Performance Monitoring Unit (PMU).\n */\ntypedef struct\n{\n  __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT];        /*!< Offset: 0x0 (R/W)    PMU Event Counter Registers */\n#if __PMU_NUM_EVENTCNT<31\n        uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];\n#endif\n  __IOM uint32_t CCNTR;                             /*!< Offset: 0x7C (R/W)   PMU Cycle Counter Register */\n        uint32_t RESERVED1[224];\n  __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT];       /*!< Offset: 0x400 (R/W)  PMU Event Type and Filter Registers */\n#if __PMU_NUM_EVENTCNT<31\n        uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];\n#endif\n  __IOM uint32_t CCFILTR;                           /*!< Offset: 0x47C (R/W)  PMU Cycle Counter Filter Register */\n        uint32_t RESERVED3[480];\n  __IOM uint32_t CNTENSET;                          /*!< Offset: 0xC00 (R/W)  PMU Count Enable Set Register */\n        uint32_t RESERVED4[7];\n  __IOM uint32_t CNTENCLR;                          /*!< Offset: 0xC20 (R/W)  PMU Count Enable Clear Register */\n        uint32_t RESERVED5[7];\n  __IOM uint32_t INTENSET;                          /*!< Offset: 0xC40 (R/W)  PMU Interrupt Enable Set Register */\n        uint32_t RESERVED6[7];\n  __IOM uint32_t INTENCLR;                          /*!< Offset: 0xC60 (R/W)  PMU Interrupt Enable Clear Register */\n        uint32_t RESERVED7[7];\n  __IOM uint32_t OVSCLR;                            /*!< Offset: 0xC80 (R/W)  PMU Overflow Flag Status Clear Register */\n        uint32_t RESERVED8[7];\n  __IOM uint32_t SWINC;                             /*!< Offset: 0xCA0 (R/W)  PMU Software Increment Register */\n        uint32_t RESERVED9[7];\n  __IOM uint32_t OVSSET;                            /*!< Offset: 0xCC0 (R/W)  PMU Overflow Flag Status Set Register */\n        uint32_t RESERVED10[79];\n  __IOM uint32_t TYPE;                              /*!< Offset: 0xE00 (R/W)  PMU Type Register */\n  __IOM uint32_t CTRL;                              /*!< Offset: 0xE04 (R/W)  PMU Control Register */\n        uint32_t RESERVED11[108];\n  __IOM uint32_t AUTHSTATUS;                        /*!< Offset: 0xFB8 (R/W)  PMU Authentication Status Register */\n  __IOM uint32_t DEVARCH;                           /*!< Offset: 0xFBC (R/W)  PMU Device Architecture Register */\n        uint32_t RESERVED12[3];\n  __IOM uint32_t DEVTYPE;                           /*!< Offset: 0xFCC (R/W)  PMU Device Type Register */\n  __IOM uint32_t PIDR4;                             /*!< Offset: 0xFD0 (R/W)  PMU Peripheral Identification Register 4 */\n        uint32_t RESERVED13[3];\n  __IOM uint32_t PIDR0;                             /*!< Offset: 0xFE0 (R/W)  PMU Peripheral Identification Register 0 */\n  __IOM uint32_t PIDR1;                             /*!< Offset: 0xFE4 (R/W)  PMU Peripheral Identification Register 1 */\n  __IOM uint32_t PIDR2;                             /*!< Offset: 0xFE8 (R/W)  PMU Peripheral Identification Register 2 */\n  __IOM uint32_t PIDR3;                             /*!< Offset: 0xFEC (R/W)  PMU Peripheral Identification Register 3 */\n  __IOM uint32_t CIDR0;                             /*!< Offset: 0xFF0 (R/W)  PMU Component Identification Register 0 */\n  __IOM uint32_t CIDR1;                             /*!< Offset: 0xFF4 (R/W)  PMU Component Identification Register 1 */\n  __IOM uint32_t CIDR2;                             /*!< Offset: 0xFF8 (R/W)  PMU Component Identification Register 2 */\n  __IOM uint32_t CIDR3;                             /*!< Offset: 0xFFC (R/W)  PMU Component Identification Register 3 */\n} PMU_Type;\n\n/** \\brief PMU Event Counter Registers (0-30) Definitions  */\n\n#define PMU_EVCNTR_CNT_Pos                    0U                                           /*!< PMU EVCNTR: Counter Position */\n#define PMU_EVCNTR_CNT_Msk                   (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/)         /*!< PMU EVCNTR: Counter Mask */\n\n/** \\brief PMU Event Type and Filter Registers (0-30) Definitions  */\n\n#define PMU_EVTYPER_EVENTTOCNT_Pos            0U                                           /*!< PMU EVTYPER: Event to Count Position */\n#define PMU_EVTYPER_EVENTTOCNT_Msk           (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/)     /*!< PMU EVTYPER: Event to Count Mask */\n\n/** \\brief PMU Count Enable Set Register Definitions */\n\n#define PMU_CNTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */\n#define PMU_CNTENSET_CNT0_ENABLE_Msk         (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/)     /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT1_ENABLE_Pos          1U                                           /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */\n#define PMU_CNTENSET_CNT1_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT2_ENABLE_Pos          2U                                           /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */\n#define PMU_CNTENSET_CNT2_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT3_ENABLE_Pos          3U                                           /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */\n#define PMU_CNTENSET_CNT3_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT4_ENABLE_Pos          4U                                           /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */\n#define PMU_CNTENSET_CNT4_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT5_ENABLE_Pos          5U                                           /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */\n#define PMU_CNTENSET_CNT5_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT6_ENABLE_Pos          6U                                           /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */\n#define PMU_CNTENSET_CNT6_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT7_ENABLE_Pos          7U                                           /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */\n#define PMU_CNTENSET_CNT7_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT8_ENABLE_Pos          8U                                           /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */\n#define PMU_CNTENSET_CNT8_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT9_ENABLE_Pos          9U                                           /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */\n#define PMU_CNTENSET_CNT9_ENABLE_Msk         (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos)         /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT10_ENABLE_Pos         10U                                          /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */\n#define PMU_CNTENSET_CNT10_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT11_ENABLE_Pos         11U                                          /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */\n#define PMU_CNTENSET_CNT11_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT12_ENABLE_Pos         12U                                          /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */\n#define PMU_CNTENSET_CNT12_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT13_ENABLE_Pos         13U                                          /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */\n#define PMU_CNTENSET_CNT13_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT14_ENABLE_Pos         14U                                          /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */\n#define PMU_CNTENSET_CNT14_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT15_ENABLE_Pos         15U                                          /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */\n#define PMU_CNTENSET_CNT15_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT16_ENABLE_Pos         16U                                          /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */\n#define PMU_CNTENSET_CNT16_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT17_ENABLE_Pos         17U                                          /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */\n#define PMU_CNTENSET_CNT17_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT18_ENABLE_Pos         18U                                          /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */\n#define PMU_CNTENSET_CNT18_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT19_ENABLE_Pos         19U                                          /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */\n#define PMU_CNTENSET_CNT19_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT20_ENABLE_Pos         20U                                          /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */\n#define PMU_CNTENSET_CNT20_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT21_ENABLE_Pos         21U                                          /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */\n#define PMU_CNTENSET_CNT21_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT22_ENABLE_Pos         22U                                          /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */\n#define PMU_CNTENSET_CNT22_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT23_ENABLE_Pos         23U                                          /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */\n#define PMU_CNTENSET_CNT23_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT24_ENABLE_Pos         24U                                          /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */\n#define PMU_CNTENSET_CNT24_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT25_ENABLE_Pos         25U                                          /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */\n#define PMU_CNTENSET_CNT25_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT26_ENABLE_Pos         26U                                          /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */\n#define PMU_CNTENSET_CNT26_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT27_ENABLE_Pos         27U                                          /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */\n#define PMU_CNTENSET_CNT27_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT28_ENABLE_Pos         28U                                          /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */\n#define PMU_CNTENSET_CNT28_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT29_ENABLE_Pos         29U                                          /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */\n#define PMU_CNTENSET_CNT29_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */\n\n#define PMU_CNTENSET_CNT30_ENABLE_Pos         30U                                          /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */\n#define PMU_CNTENSET_CNT30_ENABLE_Msk        (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos)        /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */\n\n#define PMU_CNTENSET_CCNTR_ENABLE_Pos         31U                                          /*!< PMU CNTENSET: Cycle Counter Enable Set Position */\n#define PMU_CNTENSET_CCNTR_ENABLE_Msk        (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos)        /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */\n\n/** \\brief PMU Count Enable Clear Register Definitions */\n\n#define PMU_CNTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */\n#define PMU_CNTENCLR_CNT0_ENABLE_Msk         (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/)     /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT1_ENABLE_Pos          1U                                           /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */\n#define PMU_CNTENCLR_CNT1_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */\n\n#define PMU_CNTENCLR_CNT2_ENABLE_Pos          2U                                           /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */\n#define PMU_CNTENCLR_CNT2_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT3_ENABLE_Pos          3U                                           /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */\n#define PMU_CNTENCLR_CNT3_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT4_ENABLE_Pos          4U                                           /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */\n#define PMU_CNTENCLR_CNT4_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT5_ENABLE_Pos          5U                                           /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */\n#define PMU_CNTENCLR_CNT5_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT6_ENABLE_Pos          6U                                           /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */\n#define PMU_CNTENCLR_CNT6_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT7_ENABLE_Pos          7U                                           /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */\n#define PMU_CNTENCLR_CNT7_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT8_ENABLE_Pos          8U                                           /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */\n#define PMU_CNTENCLR_CNT8_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT9_ENABLE_Pos          9U                                           /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */\n#define PMU_CNTENCLR_CNT9_ENABLE_Msk         (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos)         /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT10_ENABLE_Pos         10U                                          /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */\n#define PMU_CNTENCLR_CNT10_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT11_ENABLE_Pos         11U                                          /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */\n#define PMU_CNTENCLR_CNT11_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT12_ENABLE_Pos         12U                                          /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */\n#define PMU_CNTENCLR_CNT12_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT13_ENABLE_Pos         13U                                          /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */\n#define PMU_CNTENCLR_CNT13_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT14_ENABLE_Pos         14U                                          /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */\n#define PMU_CNTENCLR_CNT14_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT15_ENABLE_Pos         15U                                          /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */\n#define PMU_CNTENCLR_CNT15_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT16_ENABLE_Pos         16U                                          /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */\n#define PMU_CNTENCLR_CNT16_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT17_ENABLE_Pos         17U                                          /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */\n#define PMU_CNTENCLR_CNT17_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT18_ENABLE_Pos         18U                                          /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */\n#define PMU_CNTENCLR_CNT18_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT19_ENABLE_Pos         19U                                          /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */\n#define PMU_CNTENCLR_CNT19_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT20_ENABLE_Pos         20U                                          /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */\n#define PMU_CNTENCLR_CNT20_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT21_ENABLE_Pos         21U                                          /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */\n#define PMU_CNTENCLR_CNT21_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT22_ENABLE_Pos         22U                                          /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */\n#define PMU_CNTENCLR_CNT22_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT23_ENABLE_Pos         23U                                          /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */\n#define PMU_CNTENCLR_CNT23_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT24_ENABLE_Pos         24U                                          /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */\n#define PMU_CNTENCLR_CNT24_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT25_ENABLE_Pos         25U                                          /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */\n#define PMU_CNTENCLR_CNT25_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT26_ENABLE_Pos         26U                                          /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */\n#define PMU_CNTENCLR_CNT26_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT27_ENABLE_Pos         27U                                          /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */\n#define PMU_CNTENCLR_CNT27_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT28_ENABLE_Pos         28U                                          /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */\n#define PMU_CNTENCLR_CNT28_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT29_ENABLE_Pos         29U                                          /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */\n#define PMU_CNTENCLR_CNT29_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CNT30_ENABLE_Pos         30U                                          /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */\n#define PMU_CNTENCLR_CNT30_ENABLE_Msk        (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos)        /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */\n\n#define PMU_CNTENCLR_CCNTR_ENABLE_Pos         31U                                          /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */\n#define PMU_CNTENCLR_CCNTR_ENABLE_Msk        (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos)        /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */\n\n/** \\brief PMU Interrupt Enable Set Register Definitions */\n\n#define PMU_INTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT0_ENABLE_Msk         (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/)     /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT1_ENABLE_Pos          1U                                           /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT1_ENABLE_Msk         (1UL << PMU_INTENSET_CNT1_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT2_ENABLE_Pos          2U                                           /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT2_ENABLE_Msk         (1UL << PMU_INTENSET_CNT2_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT3_ENABLE_Pos          3U                                           /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT3_ENABLE_Msk         (1UL << PMU_INTENSET_CNT3_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT4_ENABLE_Pos          4U                                           /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT4_ENABLE_Msk         (1UL << PMU_INTENSET_CNT4_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT5_ENABLE_Pos          5U                                           /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT5_ENABLE_Msk         (1UL << PMU_INTENSET_CNT5_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT6_ENABLE_Pos          6U                                           /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT6_ENABLE_Msk         (1UL << PMU_INTENSET_CNT6_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT7_ENABLE_Pos          7U                                           /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT7_ENABLE_Msk         (1UL << PMU_INTENSET_CNT7_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT8_ENABLE_Pos          8U                                           /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT8_ENABLE_Msk         (1UL << PMU_INTENSET_CNT8_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT9_ENABLE_Pos          9U                                           /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT9_ENABLE_Msk         (1UL << PMU_INTENSET_CNT9_ENABLE_Pos)         /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT10_ENABLE_Pos         10U                                          /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT10_ENABLE_Msk        (1UL << PMU_INTENSET_CNT10_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT11_ENABLE_Pos         11U                                          /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT11_ENABLE_Msk        (1UL << PMU_INTENSET_CNT11_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT12_ENABLE_Pos         12U                                          /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT12_ENABLE_Msk        (1UL << PMU_INTENSET_CNT12_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT13_ENABLE_Pos         13U                                          /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT13_ENABLE_Msk        (1UL << PMU_INTENSET_CNT13_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT14_ENABLE_Pos         14U                                          /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT14_ENABLE_Msk        (1UL << PMU_INTENSET_CNT14_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT15_ENABLE_Pos         15U                                          /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT15_ENABLE_Msk        (1UL << PMU_INTENSET_CNT15_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT16_ENABLE_Pos         16U                                          /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT16_ENABLE_Msk        (1UL << PMU_INTENSET_CNT16_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT17_ENABLE_Pos         17U                                          /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT17_ENABLE_Msk        (1UL << PMU_INTENSET_CNT17_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT18_ENABLE_Pos         18U                                          /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT18_ENABLE_Msk        (1UL << PMU_INTENSET_CNT18_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT19_ENABLE_Pos         19U                                          /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT19_ENABLE_Msk        (1UL << PMU_INTENSET_CNT19_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT20_ENABLE_Pos         20U                                          /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT20_ENABLE_Msk        (1UL << PMU_INTENSET_CNT20_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT21_ENABLE_Pos         21U                                          /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT21_ENABLE_Msk        (1UL << PMU_INTENSET_CNT21_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT22_ENABLE_Pos         22U                                          /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT22_ENABLE_Msk        (1UL << PMU_INTENSET_CNT22_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT23_ENABLE_Pos         23U                                          /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT23_ENABLE_Msk        (1UL << PMU_INTENSET_CNT23_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT24_ENABLE_Pos         24U                                          /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT24_ENABLE_Msk        (1UL << PMU_INTENSET_CNT24_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT25_ENABLE_Pos         25U                                          /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT25_ENABLE_Msk        (1UL << PMU_INTENSET_CNT25_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT26_ENABLE_Pos         26U                                          /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT26_ENABLE_Msk        (1UL << PMU_INTENSET_CNT26_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT27_ENABLE_Pos         27U                                          /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT27_ENABLE_Msk        (1UL << PMU_INTENSET_CNT27_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT28_ENABLE_Pos         28U                                          /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT28_ENABLE_Msk        (1UL << PMU_INTENSET_CNT28_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT29_ENABLE_Pos         29U                                          /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT29_ENABLE_Msk        (1UL << PMU_INTENSET_CNT29_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CNT30_ENABLE_Pos         30U                                          /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */\n#define PMU_INTENSET_CNT30_ENABLE_Msk        (1UL << PMU_INTENSET_CNT30_ENABLE_Pos)        /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */\n\n#define PMU_INTENSET_CYCCNT_ENABLE_Pos        31U                                          /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */\n#define PMU_INTENSET_CCYCNT_ENABLE_Msk       (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos)       /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */\n\n/** \\brief PMU Interrupt Enable Clear Register Definitions */\n\n#define PMU_INTENSET_CNT0_ENABLE_Pos          0U                                           /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT0_ENABLE_Msk         (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/)     /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT1_ENABLE_Pos          1U                                           /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT1_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */\n\n#define PMU_INTENCLR_CNT2_ENABLE_Pos          2U                                           /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT2_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT3_ENABLE_Pos          3U                                           /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT3_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT4_ENABLE_Pos          4U                                           /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT4_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT5_ENABLE_Pos          5U                                           /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT5_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT6_ENABLE_Pos          6U                                           /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT6_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT7_ENABLE_Pos          7U                                           /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT7_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT8_ENABLE_Pos          8U                                           /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT8_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT9_ENABLE_Pos          9U                                           /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT9_ENABLE_Msk         (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos)         /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT10_ENABLE_Pos         10U                                          /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT10_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT11_ENABLE_Pos         11U                                          /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT11_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT12_ENABLE_Pos         12U                                          /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT12_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT13_ENABLE_Pos         13U                                          /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT13_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT14_ENABLE_Pos         14U                                          /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT14_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT15_ENABLE_Pos         15U                                          /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT15_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT16_ENABLE_Pos         16U                                          /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT16_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT17_ENABLE_Pos         17U                                          /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT17_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT18_ENABLE_Pos         18U                                          /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT18_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT19_ENABLE_Pos         19U                                          /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT19_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT20_ENABLE_Pos         20U                                          /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT20_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT21_ENABLE_Pos         21U                                          /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT21_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT22_ENABLE_Pos         22U                                          /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT22_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT23_ENABLE_Pos         23U                                          /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT23_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT24_ENABLE_Pos         24U                                          /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT24_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT25_ENABLE_Pos         25U                                          /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT25_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT26_ENABLE_Pos         26U                                          /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT26_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT27_ENABLE_Pos         27U                                          /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT27_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT28_ENABLE_Pos         28U                                          /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT28_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT29_ENABLE_Pos         29U                                          /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT29_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CNT30_ENABLE_Pos         30U                                          /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CNT30_ENABLE_Msk        (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos)        /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */\n\n#define PMU_INTENCLR_CYCCNT_ENABLE_Pos        31U                                          /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */\n#define PMU_INTENCLR_CYCCNT_ENABLE_Msk       (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos)       /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */\n\n/** \\brief PMU Overflow Flag Status Set Register Definitions */\n\n#define PMU_OVSSET_CNT0_STATUS_Pos            0U                                           /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */\n#define PMU_OVSSET_CNT0_STATUS_Msk           (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/)       /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT1_STATUS_Pos            1U                                           /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */\n#define PMU_OVSSET_CNT1_STATUS_Msk           (1UL << PMU_OVSSET_CNT1_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT2_STATUS_Pos            2U                                           /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */\n#define PMU_OVSSET_CNT2_STATUS_Msk           (1UL << PMU_OVSSET_CNT2_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT3_STATUS_Pos            3U                                           /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */\n#define PMU_OVSSET_CNT3_STATUS_Msk           (1UL << PMU_OVSSET_CNT3_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT4_STATUS_Pos            4U                                           /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */\n#define PMU_OVSSET_CNT4_STATUS_Msk           (1UL << PMU_OVSSET_CNT4_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT5_STATUS_Pos            5U                                           /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */\n#define PMU_OVSSET_CNT5_STATUS_Msk           (1UL << PMU_OVSSET_CNT5_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT6_STATUS_Pos            6U                                           /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */\n#define PMU_OVSSET_CNT6_STATUS_Msk           (1UL << PMU_OVSSET_CNT6_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT7_STATUS_Pos            7U                                           /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */\n#define PMU_OVSSET_CNT7_STATUS_Msk           (1UL << PMU_OVSSET_CNT7_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT8_STATUS_Pos            8U                                           /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */\n#define PMU_OVSSET_CNT8_STATUS_Msk           (1UL << PMU_OVSSET_CNT8_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT9_STATUS_Pos            9U                                           /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */\n#define PMU_OVSSET_CNT9_STATUS_Msk           (1UL << PMU_OVSSET_CNT9_STATUS_Pos)           /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT10_STATUS_Pos           10U                                          /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */\n#define PMU_OVSSET_CNT10_STATUS_Msk          (1UL << PMU_OVSSET_CNT10_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT11_STATUS_Pos           11U                                          /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */\n#define PMU_OVSSET_CNT11_STATUS_Msk          (1UL << PMU_OVSSET_CNT11_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT12_STATUS_Pos           12U                                          /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */\n#define PMU_OVSSET_CNT12_STATUS_Msk          (1UL << PMU_OVSSET_CNT12_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT13_STATUS_Pos           13U                                          /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */\n#define PMU_OVSSET_CNT13_STATUS_Msk          (1UL << PMU_OVSSET_CNT13_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT14_STATUS_Pos           14U                                          /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */\n#define PMU_OVSSET_CNT14_STATUS_Msk          (1UL << PMU_OVSSET_CNT14_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT15_STATUS_Pos           15U                                          /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */\n#define PMU_OVSSET_CNT15_STATUS_Msk          (1UL << PMU_OVSSET_CNT15_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT16_STATUS_Pos           16U                                          /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */\n#define PMU_OVSSET_CNT16_STATUS_Msk          (1UL << PMU_OVSSET_CNT16_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT17_STATUS_Pos           17U                                          /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */\n#define PMU_OVSSET_CNT17_STATUS_Msk          (1UL << PMU_OVSSET_CNT17_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT18_STATUS_Pos           18U                                          /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */\n#define PMU_OVSSET_CNT18_STATUS_Msk          (1UL << PMU_OVSSET_CNT18_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT19_STATUS_Pos           19U                                          /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */\n#define PMU_OVSSET_CNT19_STATUS_Msk          (1UL << PMU_OVSSET_CNT19_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT20_STATUS_Pos           20U                                          /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */\n#define PMU_OVSSET_CNT20_STATUS_Msk          (1UL << PMU_OVSSET_CNT20_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT21_STATUS_Pos           21U                                          /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */\n#define PMU_OVSSET_CNT21_STATUS_Msk          (1UL << PMU_OVSSET_CNT21_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT22_STATUS_Pos           22U                                          /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */\n#define PMU_OVSSET_CNT22_STATUS_Msk          (1UL << PMU_OVSSET_CNT22_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT23_STATUS_Pos           23U                                          /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */\n#define PMU_OVSSET_CNT23_STATUS_Msk          (1UL << PMU_OVSSET_CNT23_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT24_STATUS_Pos           24U                                          /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */\n#define PMU_OVSSET_CNT24_STATUS_Msk          (1UL << PMU_OVSSET_CNT24_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT25_STATUS_Pos           25U                                          /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */\n#define PMU_OVSSET_CNT25_STATUS_Msk          (1UL << PMU_OVSSET_CNT25_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT26_STATUS_Pos           26U                                          /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */\n#define PMU_OVSSET_CNT26_STATUS_Msk          (1UL << PMU_OVSSET_CNT26_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT27_STATUS_Pos           27U                                          /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */\n#define PMU_OVSSET_CNT27_STATUS_Msk          (1UL << PMU_OVSSET_CNT27_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT28_STATUS_Pos           28U                                          /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */\n#define PMU_OVSSET_CNT28_STATUS_Msk          (1UL << PMU_OVSSET_CNT28_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT29_STATUS_Pos           29U                                          /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */\n#define PMU_OVSSET_CNT29_STATUS_Msk          (1UL << PMU_OVSSET_CNT29_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */\n\n#define PMU_OVSSET_CNT30_STATUS_Pos           30U                                          /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */\n#define PMU_OVSSET_CNT30_STATUS_Msk          (1UL << PMU_OVSSET_CNT30_STATUS_Pos)          /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */\n\n#define PMU_OVSSET_CYCCNT_STATUS_Pos          31U                                          /*!< PMU OVSSET: Cycle Counter Overflow Set Position */\n#define PMU_OVSSET_CYCCNT_STATUS_Msk         (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos)         /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */\n\n/** \\brief PMU Overflow Flag Status Clear Register Definitions */\n\n#define PMU_OVSCLR_CNT0_STATUS_Pos            0U                                           /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */\n#define PMU_OVSCLR_CNT0_STATUS_Msk           (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/)       /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT1_STATUS_Pos            1U                                           /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */\n#define PMU_OVSCLR_CNT1_STATUS_Msk           (1UL << PMU_OVSCLR_CNT1_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */\n\n#define PMU_OVSCLR_CNT2_STATUS_Pos            2U                                           /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */\n#define PMU_OVSCLR_CNT2_STATUS_Msk           (1UL << PMU_OVSCLR_CNT2_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT3_STATUS_Pos            3U                                           /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */\n#define PMU_OVSCLR_CNT3_STATUS_Msk           (1UL << PMU_OVSCLR_CNT3_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT4_STATUS_Pos            4U                                           /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */\n#define PMU_OVSCLR_CNT4_STATUS_Msk           (1UL << PMU_OVSCLR_CNT4_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT5_STATUS_Pos            5U                                           /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */\n#define PMU_OVSCLR_CNT5_STATUS_Msk           (1UL << PMU_OVSCLR_CNT5_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT6_STATUS_Pos            6U                                           /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */\n#define PMU_OVSCLR_CNT6_STATUS_Msk           (1UL << PMU_OVSCLR_CNT6_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT7_STATUS_Pos            7U                                           /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */\n#define PMU_OVSCLR_CNT7_STATUS_Msk           (1UL << PMU_OVSCLR_CNT7_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT8_STATUS_Pos            8U                                           /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */\n#define PMU_OVSCLR_CNT8_STATUS_Msk           (1UL << PMU_OVSCLR_CNT8_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT9_STATUS_Pos            9U                                           /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */\n#define PMU_OVSCLR_CNT9_STATUS_Msk           (1UL << PMU_OVSCLR_CNT9_STATUS_Pos)           /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT10_STATUS_Pos           10U                                          /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */\n#define PMU_OVSCLR_CNT10_STATUS_Msk          (1UL << PMU_OVSCLR_CNT10_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT11_STATUS_Pos           11U                                          /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */\n#define PMU_OVSCLR_CNT11_STATUS_Msk          (1UL << PMU_OVSCLR_CNT11_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT12_STATUS_Pos           12U                                          /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */\n#define PMU_OVSCLR_CNT12_STATUS_Msk          (1UL << PMU_OVSCLR_CNT12_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT13_STATUS_Pos           13U                                          /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */\n#define PMU_OVSCLR_CNT13_STATUS_Msk          (1UL << PMU_OVSCLR_CNT13_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT14_STATUS_Pos           14U                                          /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */\n#define PMU_OVSCLR_CNT14_STATUS_Msk          (1UL << PMU_OVSCLR_CNT14_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT15_STATUS_Pos           15U                                          /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */\n#define PMU_OVSCLR_CNT15_STATUS_Msk          (1UL << PMU_OVSCLR_CNT15_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT16_STATUS_Pos           16U                                          /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */\n#define PMU_OVSCLR_CNT16_STATUS_Msk          (1UL << PMU_OVSCLR_CNT16_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT17_STATUS_Pos           17U                                          /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */\n#define PMU_OVSCLR_CNT17_STATUS_Msk          (1UL << PMU_OVSCLR_CNT17_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT18_STATUS_Pos           18U                                          /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */\n#define PMU_OVSCLR_CNT18_STATUS_Msk          (1UL << PMU_OVSCLR_CNT18_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT19_STATUS_Pos           19U                                          /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */\n#define PMU_OVSCLR_CNT19_STATUS_Msk          (1UL << PMU_OVSCLR_CNT19_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT20_STATUS_Pos           20U                                          /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */\n#define PMU_OVSCLR_CNT20_STATUS_Msk          (1UL << PMU_OVSCLR_CNT20_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT21_STATUS_Pos           21U                                          /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */\n#define PMU_OVSCLR_CNT21_STATUS_Msk          (1UL << PMU_OVSCLR_CNT21_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT22_STATUS_Pos           22U                                          /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */\n#define PMU_OVSCLR_CNT22_STATUS_Msk          (1UL << PMU_OVSCLR_CNT22_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT23_STATUS_Pos           23U                                          /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */\n#define PMU_OVSCLR_CNT23_STATUS_Msk          (1UL << PMU_OVSCLR_CNT23_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT24_STATUS_Pos           24U                                          /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */\n#define PMU_OVSCLR_CNT24_STATUS_Msk          (1UL << PMU_OVSCLR_CNT24_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT25_STATUS_Pos           25U                                          /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */\n#define PMU_OVSCLR_CNT25_STATUS_Msk          (1UL << PMU_OVSCLR_CNT25_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT26_STATUS_Pos           26U                                          /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */\n#define PMU_OVSCLR_CNT26_STATUS_Msk          (1UL << PMU_OVSCLR_CNT26_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT27_STATUS_Pos           27U                                          /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */\n#define PMU_OVSCLR_CNT27_STATUS_Msk          (1UL << PMU_OVSCLR_CNT27_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT28_STATUS_Pos           28U                                          /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */\n#define PMU_OVSCLR_CNT28_STATUS_Msk          (1UL << PMU_OVSCLR_CNT28_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT29_STATUS_Pos           29U                                          /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */\n#define PMU_OVSCLR_CNT29_STATUS_Msk          (1UL << PMU_OVSCLR_CNT29_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CNT30_STATUS_Pos           30U                                          /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */\n#define PMU_OVSCLR_CNT30_STATUS_Msk          (1UL << PMU_OVSCLR_CNT30_STATUS_Pos)          /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */\n\n#define PMU_OVSCLR_CYCCNT_STATUS_Pos          31U                                          /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */\n#define PMU_OVSCLR_CYCCNT_STATUS_Msk         (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos)         /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */\n\n/** \\brief PMU Software Increment Counter */\n\n#define PMU_SWINC_CNT0_Pos                    0U                                           /*!< PMU SWINC: Event Counter 0 Software Increment Position */\n#define PMU_SWINC_CNT0_Msk                   (1UL /*<< PMU_SWINC_CNT0_Pos */)              /*!< PMU SWINC: Event Counter 0 Software Increment Mask */\n\n#define PMU_SWINC_CNT1_Pos                    1U                                           /*!< PMU SWINC: Event Counter 1 Software Increment Position */\n#define PMU_SWINC_CNT1_Msk                   (1UL << PMU_SWINC_CNT1_Pos)                   /*!< PMU SWINC: Event Counter 1 Software Increment Mask */\n\n#define PMU_SWINC_CNT2_Pos                    2U                                           /*!< PMU SWINC: Event Counter 2 Software Increment Position */\n#define PMU_SWINC_CNT2_Msk                   (1UL << PMU_SWINC_CNT2_Pos)                   /*!< PMU SWINC: Event Counter 2 Software Increment Mask */\n\n#define PMU_SWINC_CNT3_Pos                    3U                                           /*!< PMU SWINC: Event Counter 3 Software Increment Position */\n#define PMU_SWINC_CNT3_Msk                   (1UL << PMU_SWINC_CNT3_Pos)                   /*!< PMU SWINC: Event Counter 3 Software Increment Mask */\n\n#define PMU_SWINC_CNT4_Pos                    4U                                           /*!< PMU SWINC: Event Counter 4 Software Increment Position */\n#define PMU_SWINC_CNT4_Msk                   (1UL << PMU_SWINC_CNT4_Pos)                   /*!< PMU SWINC: Event Counter 4 Software Increment Mask */\n\n#define PMU_SWINC_CNT5_Pos                    5U                                           /*!< PMU SWINC: Event Counter 5 Software Increment Position */\n#define PMU_SWINC_CNT5_Msk                   (1UL << PMU_SWINC_CNT5_Pos)                   /*!< PMU SWINC: Event Counter 5 Software Increment Mask */\n\n#define PMU_SWINC_CNT6_Pos                    6U                                           /*!< PMU SWINC: Event Counter 6 Software Increment Position */\n#define PMU_SWINC_CNT6_Msk                   (1UL << PMU_SWINC_CNT6_Pos)                   /*!< PMU SWINC: Event Counter 6 Software Increment Mask */\n\n#define PMU_SWINC_CNT7_Pos                    7U                                           /*!< PMU SWINC: Event Counter 7 Software Increment Position */\n#define PMU_SWINC_CNT7_Msk                   (1UL << PMU_SWINC_CNT7_Pos)                   /*!< PMU SWINC: Event Counter 7 Software Increment Mask */\n\n#define PMU_SWINC_CNT8_Pos                    8U                                           /*!< PMU SWINC: Event Counter 8 Software Increment Position */\n#define PMU_SWINC_CNT8_Msk                   (1UL << PMU_SWINC_CNT8_Pos)                   /*!< PMU SWINC: Event Counter 8 Software Increment Mask */\n\n#define PMU_SWINC_CNT9_Pos                    9U                                           /*!< PMU SWINC: Event Counter 9 Software Increment Position */\n#define PMU_SWINC_CNT9_Msk                   (1UL << PMU_SWINC_CNT9_Pos)                   /*!< PMU SWINC: Event Counter 9 Software Increment Mask */\n\n#define PMU_SWINC_CNT10_Pos                   10U                                          /*!< PMU SWINC: Event Counter 10 Software Increment Position */\n#define PMU_SWINC_CNT10_Msk                  (1UL << PMU_SWINC_CNT10_Pos)                  /*!< PMU SWINC: Event Counter 10 Software Increment Mask */\n\n#define PMU_SWINC_CNT11_Pos                   11U                                          /*!< PMU SWINC: Event Counter 11 Software Increment Position */\n#define PMU_SWINC_CNT11_Msk                  (1UL << PMU_SWINC_CNT11_Pos)                  /*!< PMU SWINC: Event Counter 11 Software Increment Mask */\n\n#define PMU_SWINC_CNT12_Pos                   12U                                          /*!< PMU SWINC: Event Counter 12 Software Increment Position */\n#define PMU_SWINC_CNT12_Msk                  (1UL << PMU_SWINC_CNT12_Pos)                  /*!< PMU SWINC: Event Counter 12 Software Increment Mask */\n\n#define PMU_SWINC_CNT13_Pos                   13U                                          /*!< PMU SWINC: Event Counter 13 Software Increment Position */\n#define PMU_SWINC_CNT13_Msk                  (1UL << PMU_SWINC_CNT13_Pos)                  /*!< PMU SWINC: Event Counter 13 Software Increment Mask */\n\n#define PMU_SWINC_CNT14_Pos                   14U                                          /*!< PMU SWINC: Event Counter 14 Software Increment Position */\n#define PMU_SWINC_CNT14_Msk                  (1UL << PMU_SWINC_CNT14_Pos)                  /*!< PMU SWINC: Event Counter 14 Software Increment Mask */\n\n#define PMU_SWINC_CNT15_Pos                   15U                                          /*!< PMU SWINC: Event Counter 15 Software Increment Position */\n#define PMU_SWINC_CNT15_Msk                  (1UL << PMU_SWINC_CNT15_Pos)                  /*!< PMU SWINC: Event Counter 15 Software Increment Mask */\n\n#define PMU_SWINC_CNT16_Pos                   16U                                          /*!< PMU SWINC: Event Counter 16 Software Increment Position */\n#define PMU_SWINC_CNT16_Msk                  (1UL << PMU_SWINC_CNT16_Pos)                  /*!< PMU SWINC: Event Counter 16 Software Increment Mask */\n\n#define PMU_SWINC_CNT17_Pos                   17U                                          /*!< PMU SWINC: Event Counter 17 Software Increment Position */\n#define PMU_SWINC_CNT17_Msk                  (1UL << PMU_SWINC_CNT17_Pos)                  /*!< PMU SWINC: Event Counter 17 Software Increment Mask */\n\n#define PMU_SWINC_CNT18_Pos                   18U                                          /*!< PMU SWINC: Event Counter 18 Software Increment Position */\n#define PMU_SWINC_CNT18_Msk                  (1UL << PMU_SWINC_CNT18_Pos)                  /*!< PMU SWINC: Event Counter 18 Software Increment Mask */\n\n#define PMU_SWINC_CNT19_Pos                   19U                                          /*!< PMU SWINC: Event Counter 19 Software Increment Position */\n#define PMU_SWINC_CNT19_Msk                  (1UL << PMU_SWINC_CNT19_Pos)                  /*!< PMU SWINC: Event Counter 19 Software Increment Mask */\n\n#define PMU_SWINC_CNT20_Pos                   20U                                          /*!< PMU SWINC: Event Counter 20 Software Increment Position */\n#define PMU_SWINC_CNT20_Msk                  (1UL << PMU_SWINC_CNT20_Pos)                  /*!< PMU SWINC: Event Counter 20 Software Increment Mask */\n\n#define PMU_SWINC_CNT21_Pos                   21U                                          /*!< PMU SWINC: Event Counter 21 Software Increment Position */\n#define PMU_SWINC_CNT21_Msk                  (1UL << PMU_SWINC_CNT21_Pos)                  /*!< PMU SWINC: Event Counter 21 Software Increment Mask */\n\n#define PMU_SWINC_CNT22_Pos                   22U                                          /*!< PMU SWINC: Event Counter 22 Software Increment Position */\n#define PMU_SWINC_CNT22_Msk                  (1UL << PMU_SWINC_CNT22_Pos)                  /*!< PMU SWINC: Event Counter 22 Software Increment Mask */\n\n#define PMU_SWINC_CNT23_Pos                   23U                                          /*!< PMU SWINC: Event Counter 23 Software Increment Position */\n#define PMU_SWINC_CNT23_Msk                  (1UL << PMU_SWINC_CNT23_Pos)                  /*!< PMU SWINC: Event Counter 23 Software Increment Mask */\n\n#define PMU_SWINC_CNT24_Pos                   24U                                          /*!< PMU SWINC: Event Counter 24 Software Increment Position */\n#define PMU_SWINC_CNT24_Msk                  (1UL << PMU_SWINC_CNT24_Pos)                  /*!< PMU SWINC: Event Counter 24 Software Increment Mask */\n\n#define PMU_SWINC_CNT25_Pos                   25U                                          /*!< PMU SWINC: Event Counter 25 Software Increment Position */\n#define PMU_SWINC_CNT25_Msk                  (1UL << PMU_SWINC_CNT25_Pos)                  /*!< PMU SWINC: Event Counter 25 Software Increment Mask */\n\n#define PMU_SWINC_CNT26_Pos                   26U                                          /*!< PMU SWINC: Event Counter 26 Software Increment Position */\n#define PMU_SWINC_CNT26_Msk                  (1UL << PMU_SWINC_CNT26_Pos)                  /*!< PMU SWINC: Event Counter 26 Software Increment Mask */\n\n#define PMU_SWINC_CNT27_Pos                   27U                                          /*!< PMU SWINC: Event Counter 27 Software Increment Position */\n#define PMU_SWINC_CNT27_Msk                  (1UL << PMU_SWINC_CNT27_Pos)                  /*!< PMU SWINC: Event Counter 27 Software Increment Mask */\n\n#define PMU_SWINC_CNT28_Pos                   28U                                          /*!< PMU SWINC: Event Counter 28 Software Increment Position */\n#define PMU_SWINC_CNT28_Msk                  (1UL << PMU_SWINC_CNT28_Pos)                  /*!< PMU SWINC: Event Counter 28 Software Increment Mask */\n\n#define PMU_SWINC_CNT29_Pos                   29U                                          /*!< PMU SWINC: Event Counter 29 Software Increment Position */\n#define PMU_SWINC_CNT29_Msk                  (1UL << PMU_SWINC_CNT29_Pos)                  /*!< PMU SWINC: Event Counter 29 Software Increment Mask */\n\n#define PMU_SWINC_CNT30_Pos                   30U                                          /*!< PMU SWINC: Event Counter 30 Software Increment Position */\n#define PMU_SWINC_CNT30_Msk                  (1UL << PMU_SWINC_CNT30_Pos)                  /*!< PMU SWINC: Event Counter 30 Software Increment Mask */\n\n/** \\brief PMU Control Register Definitions */\n\n#define PMU_CTRL_ENABLE_Pos                   0U                                           /*!< PMU CTRL: ENABLE Position */\n#define PMU_CTRL_ENABLE_Msk                  (1UL /*<< PMU_CTRL_ENABLE_Pos*/)              /*!< PMU CTRL: ENABLE Mask */\n\n#define PMU_CTRL_EVENTCNT_RESET_Pos           1U                                           /*!< PMU CTRL: Event Counter Reset Position */\n#define PMU_CTRL_EVENTCNT_RESET_Msk          (1UL << PMU_CTRL_EVENTCNT_RESET_Pos)          /*!< PMU CTRL: Event Counter Reset Mask */\n\n#define PMU_CTRL_CYCCNT_RESET_Pos             2U                                           /*!< PMU CTRL: Cycle Counter Reset Position */\n#define PMU_CTRL_CYCCNT_RESET_Msk            (1UL << PMU_CTRL_CYCCNT_RESET_Pos)            /*!< PMU CTRL: Cycle Counter Reset Mask */\n\n#define PMU_CTRL_CYCCNT_DISABLE_Pos           5U                                           /*!< PMU CTRL: Disable Cycle Counter Position */\n#define PMU_CTRL_CYCCNT_DISABLE_Msk          (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos)          /*!< PMU CTRL: Disable Cycle Counter Mask */\n\n#define PMU_CTRL_FRZ_ON_OV_Pos                9U                                           /*!< PMU CTRL: Freeze-on-overflow Position */\n#define PMU_CTRL_FRZ_ON_OV_Msk               (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos)         /*!< PMU CTRL: Freeze-on-overflow Mask */\n\n#define PMU_CTRL_TRACE_ON_OV_Pos              11U                                          /*!< PMU CTRL: Trace-on-overflow Position */\n#define PMU_CTRL_TRACE_ON_OV_Msk             (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos)       /*!< PMU CTRL: Trace-on-overflow Mask */\n\n/** \\brief PMU Type Register Definitions */\n\n#define PMU_TYPE_NUM_CNTS_Pos                 0U                                           /*!< PMU TYPE: Number of Counters Position */\n#define PMU_TYPE_NUM_CNTS_Msk                (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/)         /*!< PMU TYPE: Number of Counters Mask */\n\n#define PMU_TYPE_SIZE_CNTS_Pos                8U                                           /*!< PMU TYPE: Size of Counters Position */\n#define PMU_TYPE_SIZE_CNTS_Msk               (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos)            /*!< PMU TYPE: Size of Counters Mask */\n\n#define PMU_TYPE_CYCCNT_PRESENT_Pos           14U                                          /*!< PMU TYPE: Cycle Counter Present Position */\n#define PMU_TYPE_CYCCNT_PRESENT_Msk          (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos)          /*!< PMU TYPE: Cycle Counter Present Mask */\n\n#define PMU_TYPE_FRZ_OV_SUPPORT_Pos           21U                                          /*!< PMU TYPE: Freeze-on-overflow Support Position */\n#define PMU_TYPE_FRZ_OV_SUPPORT_Msk          (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)          /*!< PMU TYPE: Freeze-on-overflow Support Mask */\n\n#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos      23U                                          /*!< PMU TYPE: Trace-on-overflow Support Position */\n#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk     (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos)          /*!< PMU TYPE: Trace-on-overflow Support Mask */\n\n/** \\brief PMU Authentication Status Register Definitions */\n\n#define PMU_AUTHSTATUS_NSID_Pos               0U                                           /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */\n#define PMU_AUTHSTATUS_NSID_Msk              (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/)        /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_NSNID_Pos              2U                                           /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_NSNID_Msk             (0x3UL << PMU_AUTHSTATUS_NSNID_Pos)           /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SID_Pos                4U                                           /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */\n#define PMU_AUTHSTATUS_SID_Msk               (0x3UL << PMU_AUTHSTATUS_SID_Pos)             /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SNID_Pos               6U                                           /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_SNID_Msk              (0x3UL << PMU_AUTHSTATUS_SNID_Pos)            /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_NSUID_Pos              16U                                          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */\n#define PMU_AUTHSTATUS_NSUID_Msk             (0x3UL << PMU_AUTHSTATUS_NSUID_Pos)           /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_NSUNID_Pos             18U                                          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_NSUNID_Msk            (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos)          /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SUID_Pos               20U                                          /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */\n#define PMU_AUTHSTATUS_SUID_Msk              (0x3UL << PMU_AUTHSTATUS_SUID_Pos)            /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */\n\n#define PMU_AUTHSTATUS_SUNID_Pos              22U                                          /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */\n#define PMU_AUTHSTATUS_SUNID_Msk             (0x3UL << PMU_AUTHSTATUS_SUNID_Pos)           /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */\n\n\n/*@} end of group CMSIS_PMU */\n#endif\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_PXN_Pos                    4U                                            /*!< MPU RLAR: PXN Position */\n#define MPU_RLAR_PXN_Msk                   (1UL << MPU_RLAR_PXN_Pos)                      /*!< MPU RLAR: PXN Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (7UL << MPU_RLAR_AttrIndx_Pos)                 /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n#define FPU_FPDSCR_FZ16_Pos                19U                                            /*!< FPDSCR: FZ16 bit Position */\n#define FPU_FPDSCR_FZ16_Msk                (1UL << FPU_FPDSCR_FZ16_Pos)                   /*!< FPDSCR: FZ16 bit Mask */\n\n#define FPU_FPDSCR_LTPSIZE_Pos             16U                                            /*!< FPDSCR: LTPSIZE bit Position */\n#define FPU_FPDSCR_LTPSIZE_Msk             (7UL << FPU_FPDSCR_LTPSIZE_Pos)                /*!< FPDSCR: LTPSIZE bit Mask */\n\n/* Media and VFP Feature Register 0 Definitions */\n#define FPU_MVFR0_FPRound_Pos              28U                                            /*!< MVFR0: FPRound bits Position */\n#define FPU_MVFR0_FPRound_Msk              (0xFUL << FPU_MVFR0_FPRound_Pos)               /*!< MVFR0: FPRound bits Mask */\n\n#define FPU_MVFR0_FPSqrt_Pos               20U                                            /*!< MVFR0: FPSqrt bits Position */\n#define FPU_MVFR0_FPSqrt_Msk               (0xFUL << FPU_MVFR0_FPSqrt_Pos)                 /*!< MVFR0: FPSqrt bits Mask */\n\n#define FPU_MVFR0_FPDivide_Pos             16U                                            /*!< MVFR0: FPDivide bits Position */\n#define FPU_MVFR0_FPDivide_Msk             (0xFUL << FPU_MVFR0_FPDivide_Pos)              /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FPDP_Pos                  8U                                            /*!< MVFR0: FPDP bits Position */\n#define FPU_MVFR0_FPDP_Msk                 (0xFUL << FPU_MVFR0_FPDP_Pos)                  /*!< MVFR0: FPDP bits Mask */\n\n#define FPU_MVFR0_FPSP_Pos                  4U                                            /*!< MVFR0: FPSP bits Position */\n#define FPU_MVFR0_FPSP_Msk                 (0xFUL << FPU_MVFR0_FPSP_Pos)                  /*!< MVFR0: FPSP bits Mask */\n\n#define FPU_MVFR0_SIMDReg_Pos               0U                                            /*!< MVFR0: SIMDReg bits Position */\n#define FPU_MVFR0_SIMDReg_Msk              (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)           /*!< MVFR0: SIMDReg bits Mask */\n\n/* Media and VFP Feature Register 1 Definitions */\n#define FPU_MVFR1_FMAC_Pos                 28U                                            /*!< MVFR1: FMAC bits Position */\n#define FPU_MVFR1_FMAC_Msk                 (0xFUL << FPU_MVFR1_FMAC_Pos)                  /*!< MVFR1: FMAC bits Mask */\n\n#define FPU_MVFR1_FPHP_Pos                 24U                                            /*!< MVFR1: FPHP bits Position */\n#define FPU_MVFR1_FPHP_Msk                 (0xFUL << FPU_MVFR1_FPHP_Pos)                  /*!< MVFR1: FPHP bits Mask */\n\n#define FPU_MVFR1_FP16_Pos                 20U                                            /*!< MVFR1: FP16 bits Position */\n#define FPU_MVFR1_FP16_Msk                 (0xFUL << FPU_MVFR1_FP16_Pos)                  /*!< MVFR1: FP16 bits Mask */\n\n#define FPU_MVFR1_MVE_Pos                   8U                                            /*!< MVFR1: MVE bits Position */\n#define FPU_MVFR1_MVE_Msk                  (0xFUL << FPU_MVFR1_MVE_Pos)                   /*!< MVFR1: MVE bits Mask */\n\n#define FPU_MVFR1_FPDNaN_Pos                4U                                            /*!< MVFR1: FPDNaN bits Position */\n#define FPU_MVFR1_FPDNaN_Msk               (0xFUL << FPU_MVFR1_FPDNaN_Pos)                /*!< MVFR1: FPDNaN bits Mask */\n\n#define FPU_MVFR1_FPFtZ_Pos                 0U                                            /*!< MVFR1: FPFtZ bits Position */\n#define FPU_MVFR1_FPFtZ_Msk                (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)             /*!< MVFR1: FPFtZ bits Mask */\n\n/* Media and VFP Feature Register 2 Definitions */\n#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */\n#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  \\deprecated Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n  __OM  uint32_t DSCEMCR;                /*!< Offset: 0x010 ( /W)  Debug Set Clear Exception and Monitor Control Register */\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< \\deprecated CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< \\deprecated CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< \\deprecated CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< \\deprecated CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< \\deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_FPD_Pos          23U                                            /*!< \\deprecated CoreDebug DHCSR: S_FPD Position */\n#define CoreDebug_DHCSR_S_FPD_Msk          (1UL << CoreDebug_DHCSR_S_FPD_Pos)             /*!< \\deprecated CoreDebug DHCSR: S_FPD Mask */\n\n#define CoreDebug_DHCSR_S_SUIDE_Pos        22U                                            /*!< \\deprecated CoreDebug DHCSR: S_SUIDE Position */\n#define CoreDebug_DHCSR_S_SUIDE_Msk        (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SUIDE Mask */\n\n#define CoreDebug_DHCSR_S_NSUIDE_Pos       21U                                            /*!< \\deprecated CoreDebug DHCSR: S_NSUIDE Position */\n#define CoreDebug_DHCSR_S_NSUIDE_Msk       (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_NSUIDE Mask */\n\n#define CoreDebug_DHCSR_S_SDE_Pos          20U                                            /*!< \\deprecated CoreDebug DHCSR: S_SDE Position */\n#define CoreDebug_DHCSR_S_SDE_Msk          (1UL << CoreDebug_DHCSR_S_SDE_Pos)             /*!< \\deprecated CoreDebug DHCSR: S_SDE Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< \\deprecated CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< \\deprecated CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< \\deprecated CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_PMOV_Pos          6U                                            /*!< \\deprecated CoreDebug DHCSR: C_PMOV Position */\n#define CoreDebug_DHCSR_C_PMOV_Msk         (1UL << CoreDebug_DHCSR_C_PMOV_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_PMOV Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< \\deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< \\deprecated CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< \\deprecated CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< \\deprecated CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< \\deprecated CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< \\deprecated CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< \\deprecated CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< \\deprecated CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< \\deprecated CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< \\deprecated CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< \\deprecated CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< \\deprecated CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< \\deprecated CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< \\deprecated CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< \\deprecated CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< \\deprecated CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< \\deprecated CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< \\deprecated CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< \\deprecated CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< \\deprecated CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< \\deprecated CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< \\deprecated CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< \\deprecated CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Set Clear Exception and Monitor Control Register Definitions */\n#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos  19U                                            /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */\n#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk  (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)     /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */\n\n#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U                                            /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */\n#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)    /*!< \\deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */\n\n#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U                                            /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */\n#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk  (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)     /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */\n\n#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos  1U                                            /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */\n#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)    /*!< \\deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_UIDEN_Pos      10U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: UIDEN, Position */\n#define CoreDebug_DAUTHCTRL_UIDEN_Msk      (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)         /*!< \\deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos     9U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */\n#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk    (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)       /*!< \\deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_FSDMA_Pos       8U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: FSDMA, Position */\n#define CoreDebug_DAUTHCTRL_FSDMA_Msk      (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)         /*!< \\deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< \\deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< \\deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \\deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< \\deprecated CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< \\deprecated CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< \\deprecated CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< \\deprecated CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DCB       Debug Control Block\n  \\brief    Type definitions for the Debug Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Control Block Registers (DCB).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n  __OM  uint32_t DSCEMCR;                /*!< Offset: 0x010 ( /W)  Debug Set Clear Exception and Monitor Control Register */\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} DCB_Type;\n\n/* DHCSR, Debug Halting Control and Status Register Definitions */\n#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */\n#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */\n\n#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */\n#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */\n\n#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */\n#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */\n\n#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */\n#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */\n\n#define DCB_DHCSR_S_FPD_Pos                23U                                            /*!< DCB DHCSR: Floating-point registers Debuggable Position */\n#define DCB_DHCSR_S_FPD_Msk                (0x1UL << DCB_DHCSR_S_FPD_Pos)                 /*!< DCB DHCSR: Floating-point registers Debuggable Mask */\n\n#define DCB_DHCSR_S_SUIDE_Pos              22U                                            /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */\n#define DCB_DHCSR_S_SUIDE_Msk              (0x1UL << DCB_DHCSR_S_SUIDE_Pos)               /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */\n\n#define DCB_DHCSR_S_NSUIDE_Pos             21U                                            /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */\n#define DCB_DHCSR_S_NSUIDE_Msk             (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)              /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */\n\n#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */\n#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */\n\n#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */\n#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */\n\n#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */\n#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */\n\n#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */\n#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */\n\n#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */\n#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */\n\n#define DCB_DHCSR_C_PMOV_Pos                6U                                            /*!< DCB DHCSR: Halt on PMU overflow control Position */\n#define DCB_DHCSR_C_PMOV_Msk               (0x1UL << DCB_DHCSR_C_PMOV_Pos)                /*!< DCB DHCSR: Halt on PMU overflow control Mask */\n\n#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */\n#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */\n\n#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */\n#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */\n\n#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */\n#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */\n\n#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */\n#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */\n\n#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */\n#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */\n\n/* DCRSR, Debug Core Register Select Register Definitions */\n#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */\n#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */\n\n#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */\n#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */\n\n/* DCRDR, Debug Core Register Data Register Definitions */\n#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */\n#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */\n\n/* DEMCR, Debug Exception and Monitor Control Register Definitions */\n#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */\n#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */\n\n#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */\n#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */\n\n#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */\n#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */\n\n#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */\n#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */\n\n#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */\n#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */\n\n#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */\n#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */\n\n#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */\n#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */\n\n#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */\n#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */\n\n#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */\n#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */\n\n#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */\n#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */\n\n#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */\n#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */\n\n#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */\n#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */\n\n#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */\n#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */\n\n#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */\n#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */\n\n#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */\n#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */\n\n#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */\n#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */\n\n#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */\n#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */\n\n/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */\n#define DCB_DSCEMCR_CLR_MON_REQ_Pos        19U                                            /*!< DCB DSCEMCR: Clear monitor request Position */\n#define DCB_DSCEMCR_CLR_MON_REQ_Msk        (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)         /*!< DCB DSCEMCR: Clear monitor request Mask */\n\n#define DCB_DSCEMCR_CLR_MON_PEND_Pos       17U                                            /*!< DCB DSCEMCR: Clear monitor pend Position */\n#define DCB_DSCEMCR_CLR_MON_PEND_Msk       (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)        /*!< DCB DSCEMCR: Clear monitor pend Mask */\n\n#define DCB_DSCEMCR_SET_MON_REQ_Pos         3U                                            /*!< DCB DSCEMCR: Set monitor request Position */\n#define DCB_DSCEMCR_SET_MON_REQ_Msk        (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)         /*!< DCB DSCEMCR: Set monitor request Mask */\n\n#define DCB_DSCEMCR_SET_MON_PEND_Pos        1U                                            /*!< DCB DSCEMCR: Set monitor pend Position */\n#define DCB_DSCEMCR_SET_MON_PEND_Msk       (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)        /*!< DCB DSCEMCR: Set monitor pend Mask */\n\n/* DAUTHCTRL, Debug Authentication Control Register Definitions */\n#define DCB_DAUTHCTRL_UIDEN_Pos            10U                                            /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */\n#define DCB_DAUTHCTRL_UIDEN_Msk            (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)             /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */\n\n#define DCB_DAUTHCTRL_UIDAPEN_Pos           9U                                            /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */\n#define DCB_DAUTHCTRL_UIDAPEN_Msk          (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)           /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */\n\n#define DCB_DAUTHCTRL_FSDMA_Pos             8U                                            /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */\n#define DCB_DAUTHCTRL_FSDMA_Msk            (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)             /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */\n\n#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */\n\n#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */\n\n/* DSCSR, Debug Security Control and Status Register Definitions */\n#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */\n#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */\n\n#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */\n#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */\n\n#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */\n#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */\n\n#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */\n#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */\n\n/*@} end of group CMSIS_DCB */\n\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DIB       Debug Identification Block\n  \\brief    Type definitions for the Debug Identification Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Identification Block Registers (DIB).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */\n  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */\n        uint32_t RESERVED1[3U];\n  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x01C (R/ )  SCS Device Type Register */\n} DIB_Type;\n\n/* DAUTHSTATUS, Debug Authentication Status Register Definitions */\n#define DIB_DAUTHSTATUS_SUNID_Pos          22U                                            /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */\n#define DIB_DAUTHSTATUS_SUNID_Msk          (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )          /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */\n\n#define DIB_DAUTHSTATUS_SUID_Pos           20U                                            /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */\n#define DIB_DAUTHSTATUS_SUID_Msk           (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )           /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */\n\n#define DIB_DAUTHSTATUS_NSUNID_Pos         18U                                            /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */\n#define DIB_DAUTHSTATUS_NSUNID_Msk         (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )         /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */\n\n#define DIB_DAUTHSTATUS_NSUID_Pos          16U                                            /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */\n#define DIB_DAUTHSTATUS_NSUID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */\n\n#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */\n\n/* DDEVARCH, SCS Device Architecture Register Definitions */\n#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */\n#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */\n\n#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */\n#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */\n\n#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */\n#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */\n\n#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */\n#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */\n\n#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */\n#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */\n\n/* DDEVTYPE, SCS Device Type Register Definitions */\n#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */\n#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */\n\n#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */\n#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */\n\n\n/*@} end of group CMSIS_DIB */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define MEMSYSCTL_BASE      (0xE001E000UL)                             /*!< Memory System Control Base Address */\n  #define ERRBNK_BASE         (0xE001E100UL)                             /*!< Error Banking Base Address */\n  #define PWRMODCTL_BASE      (0xE001E300UL)                             /*!< Power Mode Control Base Address */\n  #define EWIC_ISA_BASE       (0xE001E400UL)                             /*!< External Wakeup Interrupt Controller interrupt status access Base Address */\n  #define PRCCFGINF_BASE      (0xE001E700UL)                             /*!< Processor Configuration Information Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define EWIC_BASE           (0xE0047000UL)                             /*!< External Wakeup Interrupt Controller Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< \\deprecated Core Debug Base Address */\n  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */\n  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define ICB                 ((ICB_Type       *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define MEMSYSCTL           ((MemSysCtl_Type *)     MEMSYSCTL_BASE   ) /*!< Memory System Control configuration struct */\n  #define ERRBNK              ((ErrBnk_Type    *)     ERRBNK_BASE      ) /*!< Error Banking configuration struct */\n  #define PWRMODCTL           ((PwrModCtl_Type *)     PWRMODCTL_BASE   ) /*!< Power Mode Control configuration struct */\n  #define EWIC_ISA            ((EWIC_ISA_Type  *)     EWIC_ISA_BASE    ) /*!< EWIC interrupt status access struct */\n  #define EWIC                ((EWIC_Type      *)     EWIC_BASE        ) /*!< EWIC configuration struct */\n  #define PRCCFGINF           ((PrcCfgInf_Type *)     PRCCFGINF_BASE   ) /*!< Processor Configuration Information configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< \\deprecated Core Debug configuration struct */\n  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */\n  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)\n    #define PMU_BASE          (0xE0003000UL)                             /*!< PMU Base Address */\n    #define PMU               ((PMU_Type       *)     PMU_BASE         ) /*!< PMU configuration struct */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< \\deprecated Core Debug Base Address           (non-secure address space) */\n  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */\n  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define ICB_NS              ((ICB_Type       *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< \\deprecated Core Debug configuration struct   (non-secure address space) */\n  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */\n  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n\n/*@} */\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)                      );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  PMU functions and events  #################################### */\n\n#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U)\n\n#include \"pmu_armv8.h\"\n\n/**\n  \\brief   Cortex-M85 PMU events\n  \\note    Architectural PMU events can be found in pmu_armv8.h\n*/\n\n#define ARMCM85_PMU_ECC_ERR                          0xC000             /*!< One or more Error Correcting Code (ECC) errors detected */\n#define ARMCM85_PMU_ECC_ERR_MBIT                     0xC001             /*!< One or more multi-bit ECC errors detected */\n#define ARMCM85_PMU_ECC_ERR_DCACHE                   0xC010             /*!< One or more ECC errors in the data cache */\n#define ARMCM85_PMU_ECC_ERR_ICACHE                   0xC011             /*!< One or more ECC errors in the instruction cache */\n#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE              0xC012             /*!< One or more multi-bit ECC errors in the data cache */\n#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE              0xC013             /*!< One or more multi-bit ECC errors in the instruction cache */\n#define ARMCM85_PMU_ECC_ERR_DTCM                     0xC020             /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */\n#define ARMCM85_PMU_ECC_ERR_ITCM                     0xC021             /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */\n#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM                0xC022             /*!< One or more multi-bit ECC errors in the DTCM */\n#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM                0xC023             /*!< One or more multi-bit ECC errors in the ITCM */\n#define ARMCM85_PMU_PF_LINEFILL                      0xC100             /*!< The prefetcher starts a line-fill */\n#define ARMCM85_PMU_PF_CANCEL                        0xC101             /*!< The prefetcher stops prefetching */\n#define ARMCM85_PMU_PF_DROP_LINEFILL                 0xC102             /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */\n#define ARMCM85_PMU_NWAMODE_ENTER                    0xC200             /*!< No write-allocate mode entry */\n#define ARMCM85_PMU_NWAMODE                          0xC201             /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */\n#define ARMCM85_PMU_SAHB_ACCESS                      0xC300             /*!< Read or write access on the S-AHB interface to the TCM */\n#define ARMCM85_PMU_PAHB_ACCESS                      0xC301             /*!< Read or write access on the P-AHB write interface */\n#define ARMCM85_PMU_AXI_WRITE_ACCESS                 0xC302             /*!< Any beat access to M-AXI write interface */\n#define ARMCM85_PMU_AXI_READ_ACCESS                  0xC303             /*!< Any beat access to M-AXI read interface */\n#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE                0xC400             /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */\n#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE                0xC401             /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */\n#define ARMCM85_PMU_FUSED_INST_RETIRED               0xC500             /*!< Fused instructions architecturally executed */\n#define ARMCM85_PMU_BR_INDIRECT                      0xC501             /*!< Indirect branch instruction architecturally executed */\n#define ARMCM85_PMU_BTAC_HIT                         0xC502             /*!< BTAC branch predictor hit */\n#define ARMCM85_PMU_BTAC_HIT_RETURNS                 0xC503             /*!< Return branch hits BTAC */\n#define ARMCM85_PMU_BTAC_HIT_CALLS                   0xC504             /*!< Call branch hits BTAC */\n#define ARMCM85_PMU_BTAC_HIT_INDIRECT                0xC505             /*!< Indirect branch hits BTACT */\n#define ARMCM85_PMU_BTAC_NEW_ALLOC                   0xC506             /*!< New allocation to BTAC */\n#define ARMCM85_PMU_BR_IND_MIS_PRED                  0xC507             /*!< Indirect branch mis-predicted */\n#define ARMCM85_PMU_BR_RETURN_MIS_PRED               0xC508             /*!< Return branch mis-predicted */\n#define ARMCM85_PMU_BR_BTAC_OFFSET_OVERFLOW          0xC509             /*!< Branch does not allocate in BTAC due to offset overflow */\n#define ARMCM85_PMU_STB_FULL_STALL_AXI               0xC50A             /*!< STore Buffer (STB) full with AXI requests causing CPU to stall */\n#define ARMCM85_PMU_STB_FULL_STALL_TCM               0xC50B             /*!< STB full with TCM requests causing CPU to stall */\n#define ARMCM85_PMU_CPU_STALLED_AHBS                 0xC50C             /*!< CPU is stalled because TCM access through AHBS */\n#define ARMCM85_PMU_AHBS_STALLED_CPU                 0xC50D             /*!< AHBS is stalled due to TCM access by CPU */\n#define ARMCM85_PMU_BR_INTERSTATING_MIS_PRED         0xC50E             /*!< Inter-stating branch is mis-predicted. */\n#define ARMCM85_PMU_DWT_STALL                        0xC50F             /*!< Data Watchpoint and Trace (DWT) stall */\n#define ARMCM85_PMU_DWT_FLUSH                        0xC510             /*!< DWT flush */\n#define ARMCM85_PMU_ETM_STALL                        0xC511             /*!< Embedded Trace Macrocell (ETM) stall */\n#define ARMCM85_PMU_ETM_FLUSH                        0xC512             /*!< ETM flush */\n#define ARMCM85_PMU_ADDRESS_BANK_CONFLICT            0xC513             /*!< Bank conflict prevents memory instruction dual issue */\n#define ARMCM85_PMU_BLOCKED_DUAL_ISSUE               0xC514             /*!< Dual instruction issuing is prevented */\n#define ARMCM85_PMU_FP_CONTEXT_TRIGGER               0xC515             /*!< Floating Point Context is created */\n#define ARMCM85_PMU_TAIL_CHAIN                       0xC516             /*!< New exception is handled without first unstacking */\n#define ARMCM85_PMU_LATE_ARRIVAL                     0xC517             /*!< Late-arriving exception taken during exception entry */\n#define ARMCM85_PMU_INT_STALL_FAULT                  0xC518             /*!< Delayed exception entry due to ongoing fault processing */\n#define ARMCM85_PMU_INT_STALL_DEV                    0xC519             /*!< Delayed exception entry due to outstanding device access */\n#define ARMCM85_PMU_PAC_STALL                        0xC51A             /*!< Stall caused by authentication code computation */\n#define ARMCM85_PMU_PAC_RETIRED                      0xC51B             /*!< PAC instruction architecturally executed */\n#define ARMCM85_PMU_AUT_RETIRED                      0xC51C             /*!< AUT instruction architecturally executed */\n#define ARMCM85_PMU_BTI_RETIRED                      0xC51D             /*!< BTI instruction architecturally executed */\n#define ARMCM85_PMU_PF_NL_MODE                       0xC51E             /*!< Prefetch in next line mode */\n#define ARMCM85_PMU_PF_STREAM_MODE                   0xC51F             /*!< Prefetch in stream mode */\n#define ARMCM85_PMU_PF_BUFF_CACHE_HIT                0xC520             /*!< Prefetch request that hit in the cache */\n#define ARMCM85_PMU_PF_REQ_LFB_HIT                   0xC521             /*!< Prefetch request that hit in line fill buffers */\n#define ARMCM85_PMU_PF_BUFF_FULL                     0xC522             /*!< Number of times prefetch buffer is full */\n#define ARMCM85_PMU_PF_REQ_DCACHE_HIT                0xC523             /*!< Generated prefetch request address that hit in D-Cache */\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n/* ##########################  MVE functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_MveFunctions MVE Functions\n  \\brief    Function that provides MVE type.\n  @{\n */\n\n/**\n  \\brief   get MVE type\n  \\details returns the MVE type\n  \\returns\n   - \\b  0: No Vector Extension (MVE)\n   - \\b  1: Integer Vector Extension (MVE-I)\n   - \\b  2: Floating-point Vector Extension (MVE-F)\n */\n__STATIC_INLINE uint32_t SCB_GetMVEType(void)\n{\n  const uint32_t mvfr1 = FPU->MVFR1;\n  if      ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos))\n  {\n    return 2U;\n  }\n  else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos))\n  {\n    return 1U;\n  }\n  else\n  {\n    return 0U;\n  }\n}\n\n\n/*@} end of CMSIS_Core_MveFunctions */\n\n\n/* ##########################  Cache functions  #################################### */\n\n#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \\\n     (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))\n#include \"cachel1_armv7.h\"\n#endif\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n/* ###################  PAC Key functions  ########################### */\n\n#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))\n#include \"pac_armv81.h\"\n#endif\n\n\n/* ##################################    Debug Control function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DCBFunctions Debug Control Functions\n  \\brief    Functions that access the Debug Control Block.\n  @{\n */\n\n\n/**\n  \\brief   Set Debug Authentication Control Register\n  \\details writes to Debug Authentication Control register.\n  \\param [in]  value  value to be writen.\n */\n__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register\n  \\details Reads Debug Authentication Control register.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)\n{\n    return (DCB->DAUTHCTRL);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Debug Authentication Control Register (non-secure)\n  \\details writes to non-secure Debug Authentication Control register when in secure state.\n  \\param [in]  value  value to be writen\n */\n__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB_NS->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register (non-secure)\n  \\details Reads non-secure Debug Authentication Control register when in secure state.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)\n{\n    return (DCB_NS->DAUTHCTRL);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    Debug Identification function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions\n  \\brief    Functions that access the Debug Identification Block.\n  @{\n */\n\n\n/**\n  \\brief   Get Debug Authentication Status Register\n  \\details Reads Debug Authentication Status register.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)\n{\n    return (DIB->DAUTHSTATUS);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Debug Authentication Status Register (non-secure)\n  \\details Reads non-secure Debug Authentication Status register when in secure state.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)\n{\n    return (DIB_NS->DAUTHSTATUS);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM85_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_sc000.h",
    "content": "/**************************************************************************//**\n * @file     core_sc000.h\n * @brief    CMSIS SC000 Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_SC000_H_GENERIC\n#define __CORE_SC000_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup SC000\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS SC000 definitions */\n#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC000_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_SC000_H_DEPENDANT\n#define __CORE_SC000_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __SC000_REV\n    #define __SC000_REV             0x0000U\n    #warning \"__SC000_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n  \n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group SC000 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n        uint32_t RESERVED1[154U];\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n} MPU_Type;\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the SC000 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */\n/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC000_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_sc300.h",
    "content": "/**************************************************************************//**\n * @file     core_sc300.h\n * @brief    CMSIS SC300 Core Peripheral Access Layer Header File\n * @version  V5.1.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_SC300_H_GENERIC\n#define __CORE_SC300_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup SC3000\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS SC300 definitions */\n#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_FP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC300_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_SC300_H_DEPENDANT\n#define __CORE_SC300_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __SC300_REV\n    #define __SC300_REV               0x0000U\n    #warning \"__SC300_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT             1U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group SC300 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RESERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n        uint32_t RESERVED1[129U];\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_BYTEACC_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_BYTEACC_Msk                (1UL << ITM_LSR_BYTEACC_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_ACCESS_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_ACCESS_Msk                 (1UL << ITM_LSR_ACCESS_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_PRESENT_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_PRESENT_Msk                (1UL /*<< ITM_LSR_PRESENT_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_register_aliases     Backwards Compatibility Aliases\n  \\brief      Register alias definitions for backwards compatibility.\n  @{\n */\n\n/* Capitalize ITM_TCR Register Definitions */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_TraceBusID_Pos           (ITM_TCR_TRACEBUSID_Pos)     /*!< \\deprecated ITM_TCR_TraceBusID_Pos */\n#define ITM_TCR_TraceBusID_Msk           (ITM_TCR_TRACEBUSID_Msk)     /*!< \\deprecated ITM_TCR_TraceBusID_Msk */\n\n#define ITM_TCR_TSPrescale_Pos           (ITM_TCR_TSPRESCALE_Pos)     /*!< \\deprecated ITM_TCR_TSPrescale_Pos */\n#define ITM_TCR_TSPrescale_Msk           (ITM_TCR_TSPRESCALE_Msk)     /*!< \\deprecated ITM_TCR_TSPrescale_Msk */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos              (ITM_LSR_BYTEACC_Pos)        /*!< \\deprecated ITM_LSR_ByteAcc_Pos */\n#define ITM_LSR_ByteAcc_Msk              (ITM_LSR_BYTEACC_Msk)        /*!< \\deprecated ITM_LSR_ByteAcc_Msk */\n\n#define ITM_LSR_Access_Pos               (ITM_LSR_ACCESS_Pos)         /*!< \\deprecated ITM_LSR_Access_Pos */\n#define ITM_LSR_Access_Msk               (ITM_LSR_ACCESS_Msk)         /*!< \\deprecated ITM_LSR_Access_Msk */\n\n#define ITM_LSR_Present_Pos              (ITM_LSR_PRESENT_Pos)        /*!< \\deprecated ITM_LSR_Present_Pos */\n#define ITM_LSR_Present_Msk              (ITM_LSR_PRESENT_Msk)        /*!< \\deprecated ITM_LSR_Present_Msk */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  /* ARM Application Note 321 states that the M3 does not require the architectural barrier */\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC300_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/core_starmc1.h",
    "content": "/**************************************************************************//**\n * @file     core_starmc1.h\n * @brief    CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File\n * @version  V1.1.0\n * @date     04. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2013 Arm Limited. \n * Copyright (c) 2018-2022 Arm China. \n * All rights reserved.\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header                   /* treat file as system include file */\n#elif defined ( __GNUC__ )\n  #pragma GCC diagnostic ignored \"-Wpedantic\"   /* disable pedantic warning due to unnamed structs/unions */\n#endif\n\n#ifndef __CORE_STAR_H_GENERIC\n#define __CORE_STAR_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup STAR-MC1\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* Macro Define for STAR-MC1 */\n#define __STAR_MC                 (1U)                                       /*!< STAR-MC Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined (__TARGET_FPU_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ti__)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED       0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined (__ARMVFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined (__TI_VFP_SUPPORT__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined (__FPU_VFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_STAR_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_STAR_H_DEPENDANT\n#define __CORE_STAR_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __STAR_REV\n    #define __STAR_REV                0x0000U\n    #warning \"__STAR_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ICACHE_PRESENT\n    #define __ICACHE_PRESENT          0U\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DCACHE_PRESENT\n    #define __DCACHE_PRESENT          0U\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DTCM_PRESENT\n    #define __DTCM_PRESENT            0U\n    #warning \"__DTCM_PRESENT        not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group STAR-MC1 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for STAR-MC1 processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED_ADD1[21U];      \n  __IOM uint32_t SFSR;                   /*!< Offset: 0x0E4 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x0E8 (R/W)  Secure Fault Address Register */\n        uint32_t RESERVED3[69U];\n  __OM  uint32_t STIR;                   /*!< Offset: F00-D00=0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n} SCB_Type;\n\ntypedef struct\n{\n  __IOM uint32_t CACR;\t\t\t\t       /*!< Offset: 0x0 (R/W)  L1 Cache Control Register */\n  __IOM uint32_t ITCMCR;\t\t\t\t   /*!< Offset: 0x10 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;\t\t\t\t   /*!< Offset: 0x14 (R/W)  Data Tightly-Coupled Memory Control Registers */ \n}EMSS_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 7U)                 /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 5U)                 /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_CFSR_MEMFAULTSR_Pos + 4U)                 /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_CFSR_MEMFAULTSR_Pos + 3U)                 /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 1U)                 /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_CFSR_MEMFAULTSR_Pos + 0U)                 /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n#define SCB_CLIDR_IC_Pos                   0U                                             /*!< SCB CLIDR: IC Position */\n#define SCB_CLIDR_IC_Msk                   (1UL << SCB_CLIDR_IC_Pos)                      /*!< SCB CLIDR: IC Mask */\n\n#define SCB_CLIDR_DC_Pos                   1U                                             /*!< SCB CLIDR: DC Position */\n#define SCB_CLIDR_DC_Msk                   (1UL << SCB_CLIDR_DC_Pos)                      /*!< SCB CLIDR: DC Mask */\n\n\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache line Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_LEVEL_Pos                1U                                             /*!< SCB DCISW: Level Position */\n#define SCB_DCISW_LEVEL_Msk                (7UL << SCB_DCISW_LEVEL_Pos)                   /*!< SCB DCISW: Level Mask */\n\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0xFFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean line by Set-way Register Definitions */\n#define SCB_DCCSW_LEVEL_Pos                1U                                             /*!< SCB DCCSW: Level Position */\n#define SCB_DCCSW_LEVEL_Msk                (7UL << SCB_DCCSW_LEVEL_Pos)                   /*!< SCB DCCSW: Level Mask */\n\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0xFFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_LEVEL_Pos               1U                                             /*!< SCB DCCISW: Level Position */\n#define SCB_DCCISW_LEVEL_Msk               (7UL << SCB_DCCISW_LEVEL_Pos)                  /*!< SCB DCCISW: Level Mask */\n\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0xFFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* ArmChina: Implementation Defined */\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_DCCLEAN_Pos                16U                                            /*!< SCB CACR: DCCLEAN Position */\n#define SCB_CACR_DCCLEAN_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: DCCLEAN Mask */\n\n#define SCB_CACR_ICACTIVE_Pos                13U                                            /*!< SCB CACR: ICACTIVE Position */\n#define SCB_CACR_ICACTIVE_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: ICACTIVE Mask */\n\n#define SCB_CACR_DCACTIVE_Pos                12U                                            /*!< SCB CACR: DCACTIVE Position */\n#define SCB_CACR_DCACTIVE_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: DCACTIVE Mask */\n\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[32U];\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and VFP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and VFP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and VFP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and VFP Feature Register 2 Definitions */\n#define FPU_MVFR2_FPMisc_Pos                4U                                            /*!< MVFR2: FPMisc bits Position */\n#define FPU_MVFR2_FPMisc_Msk               (0xFUL << FPU_MVFR2_FPMisc_Pos)                /*!< MVFR2: FPMisc bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup CMSIS_DCB       Debug Control Block\n  \\brief    Type definitions for the Debug Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Control Block Registers (DCB).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} DCB_Type;\n\n/* DHCSR, Debug Halting Control and Status Register Definitions */\n#define DCB_DHCSR_DBGKEY_Pos               16U                                            /*!< DCB DHCSR: Debug key Position */\n#define DCB_DHCSR_DBGKEY_Msk               (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos)             /*!< DCB DHCSR: Debug key Mask */\n\n#define DCB_DHCSR_S_RESTART_ST_Pos         26U                                            /*!< DCB DHCSR: Restart sticky status Position */\n#define DCB_DHCSR_S_RESTART_ST_Msk         (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos)          /*!< DCB DHCSR: Restart sticky status Mask */\n\n#define DCB_DHCSR_S_RESET_ST_Pos           25U                                            /*!< DCB DHCSR: Reset sticky status Position */\n#define DCB_DHCSR_S_RESET_ST_Msk           (0x1UL << DCB_DHCSR_S_RESET_ST_Pos)            /*!< DCB DHCSR: Reset sticky status Mask */\n\n#define DCB_DHCSR_S_RETIRE_ST_Pos          24U                                            /*!< DCB DHCSR: Retire sticky status Position */\n#define DCB_DHCSR_S_RETIRE_ST_Msk          (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos)           /*!< DCB DHCSR: Retire sticky status Mask */\n\n#define DCB_DHCSR_S_SDE_Pos                20U                                            /*!< DCB DHCSR: Secure debug enabled Position */\n#define DCB_DHCSR_S_SDE_Msk                (0x1UL << DCB_DHCSR_S_SDE_Pos)                 /*!< DCB DHCSR: Secure debug enabled Mask */\n\n#define DCB_DHCSR_S_LOCKUP_Pos             19U                                            /*!< DCB DHCSR: Lockup status Position */\n#define DCB_DHCSR_S_LOCKUP_Msk             (0x1UL << DCB_DHCSR_S_LOCKUP_Pos)              /*!< DCB DHCSR: Lockup status Mask */\n\n#define DCB_DHCSR_S_SLEEP_Pos              18U                                            /*!< DCB DHCSR: Sleeping status Position */\n#define DCB_DHCSR_S_SLEEP_Msk              (0x1UL << DCB_DHCSR_S_SLEEP_Pos)               /*!< DCB DHCSR: Sleeping status Mask */\n\n#define DCB_DHCSR_S_HALT_Pos               17U                                            /*!< DCB DHCSR: Halted status Position */\n#define DCB_DHCSR_S_HALT_Msk               (0x1UL << DCB_DHCSR_S_HALT_Pos)                /*!< DCB DHCSR: Halted status Mask */\n\n#define DCB_DHCSR_S_REGRDY_Pos             16U                                            /*!< DCB DHCSR: Register ready status Position */\n#define DCB_DHCSR_S_REGRDY_Msk             (0x1UL << DCB_DHCSR_S_REGRDY_Pos)              /*!< DCB DHCSR: Register ready status Mask */\n\n#define DCB_DHCSR_C_SNAPSTALL_Pos           5U                                            /*!< DCB DHCSR: Snap stall control Position */\n#define DCB_DHCSR_C_SNAPSTALL_Msk          (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos)           /*!< DCB DHCSR: Snap stall control Mask */\n\n#define DCB_DHCSR_C_MASKINTS_Pos            3U                                            /*!< DCB DHCSR: Mask interrupts control Position */\n#define DCB_DHCSR_C_MASKINTS_Msk           (0x1UL << DCB_DHCSR_C_MASKINTS_Pos)            /*!< DCB DHCSR: Mask interrupts control Mask */\n\n#define DCB_DHCSR_C_STEP_Pos                2U                                            /*!< DCB DHCSR: Step control Position */\n#define DCB_DHCSR_C_STEP_Msk               (0x1UL << DCB_DHCSR_C_STEP_Pos)                /*!< DCB DHCSR: Step control Mask */\n\n#define DCB_DHCSR_C_HALT_Pos                1U                                            /*!< DCB DHCSR: Halt control Position */\n#define DCB_DHCSR_C_HALT_Msk               (0x1UL << DCB_DHCSR_C_HALT_Pos)                /*!< DCB DHCSR: Halt control Mask */\n\n#define DCB_DHCSR_C_DEBUGEN_Pos             0U                                            /*!< DCB DHCSR: Debug enable control Position */\n#define DCB_DHCSR_C_DEBUGEN_Msk            (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/)         /*!< DCB DHCSR: Debug enable control Mask */\n\n/* DCRSR, Debug Core Register Select Register Definitions */\n#define DCB_DCRSR_REGWnR_Pos               16U                                            /*!< DCB DCRSR: Register write/not-read Position */\n#define DCB_DCRSR_REGWnR_Msk               (0x1UL << DCB_DCRSR_REGWnR_Pos)                /*!< DCB DCRSR: Register write/not-read Mask */\n\n#define DCB_DCRSR_REGSEL_Pos                0U                                            /*!< DCB DCRSR: Register selector Position */\n#define DCB_DCRSR_REGSEL_Msk               (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/)           /*!< DCB DCRSR: Register selector Mask */\n\n/* DCRDR, Debug Core Register Data Register Definitions */\n#define DCB_DCRDR_DBGTMP_Pos                0U                                            /*!< DCB DCRDR: Data temporary buffer Position */\n#define DCB_DCRDR_DBGTMP_Msk               (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/)     /*!< DCB DCRDR: Data temporary buffer Mask */\n\n/* DEMCR, Debug Exception and Monitor Control Register Definitions */\n#define DCB_DEMCR_TRCENA_Pos               24U                                            /*!< DCB DEMCR: Trace enable Position */\n#define DCB_DEMCR_TRCENA_Msk               (0x1UL << DCB_DEMCR_TRCENA_Pos)                /*!< DCB DEMCR: Trace enable Mask */\n\n#define DCB_DEMCR_MONPRKEY_Pos             23U                                            /*!< DCB DEMCR: Monitor pend req key Position */\n#define DCB_DEMCR_MONPRKEY_Msk             (0x1UL << DCB_DEMCR_MONPRKEY_Pos)              /*!< DCB DEMCR: Monitor pend req key Mask */\n\n#define DCB_DEMCR_UMON_EN_Pos              21U                                            /*!< DCB DEMCR: Unprivileged monitor enable Position */\n#define DCB_DEMCR_UMON_EN_Msk              (0x1UL << DCB_DEMCR_UMON_EN_Pos)               /*!< DCB DEMCR: Unprivileged monitor enable Mask */\n\n#define DCB_DEMCR_SDME_Pos                 20U                                            /*!< DCB DEMCR: Secure DebugMonitor enable Position */\n#define DCB_DEMCR_SDME_Msk                 (0x1UL << DCB_DEMCR_SDME_Pos)                  /*!< DCB DEMCR: Secure DebugMonitor enable Mask */\n\n#define DCB_DEMCR_MON_REQ_Pos              19U                                            /*!< DCB DEMCR: Monitor request Position */\n#define DCB_DEMCR_MON_REQ_Msk              (0x1UL << DCB_DEMCR_MON_REQ_Pos)               /*!< DCB DEMCR: Monitor request Mask */\n\n#define DCB_DEMCR_MON_STEP_Pos             18U                                            /*!< DCB DEMCR: Monitor step Position */\n#define DCB_DEMCR_MON_STEP_Msk             (0x1UL << DCB_DEMCR_MON_STEP_Pos)              /*!< DCB DEMCR: Monitor step Mask */\n\n#define DCB_DEMCR_MON_PEND_Pos             17U                                            /*!< DCB DEMCR: Monitor pend Position */\n#define DCB_DEMCR_MON_PEND_Msk             (0x1UL << DCB_DEMCR_MON_PEND_Pos)              /*!< DCB DEMCR: Monitor pend Mask */\n\n#define DCB_DEMCR_MON_EN_Pos               16U                                            /*!< DCB DEMCR: Monitor enable Position */\n#define DCB_DEMCR_MON_EN_Msk               (0x1UL << DCB_DEMCR_MON_EN_Pos)                /*!< DCB DEMCR: Monitor enable Mask */\n\n#define DCB_DEMCR_VC_SFERR_Pos             11U                                            /*!< DCB DEMCR: Vector Catch SecureFault Position */\n#define DCB_DEMCR_VC_SFERR_Msk             (0x1UL << DCB_DEMCR_VC_SFERR_Pos)              /*!< DCB DEMCR: Vector Catch SecureFault Mask */\n\n#define DCB_DEMCR_VC_HARDERR_Pos           10U                                            /*!< DCB DEMCR: Vector Catch HardFault errors Position */\n#define DCB_DEMCR_VC_HARDERR_Msk           (0x1UL << DCB_DEMCR_VC_HARDERR_Pos)            /*!< DCB DEMCR: Vector Catch HardFault errors Mask */\n\n#define DCB_DEMCR_VC_INTERR_Pos             9U                                            /*!< DCB DEMCR: Vector Catch interrupt errors Position */\n#define DCB_DEMCR_VC_INTERR_Msk            (0x1UL << DCB_DEMCR_VC_INTERR_Pos)             /*!< DCB DEMCR: Vector Catch interrupt errors Mask */\n\n#define DCB_DEMCR_VC_BUSERR_Pos             8U                                            /*!< DCB DEMCR: Vector Catch BusFault errors Position */\n#define DCB_DEMCR_VC_BUSERR_Msk            (0x1UL << DCB_DEMCR_VC_BUSERR_Pos)             /*!< DCB DEMCR: Vector Catch BusFault errors Mask */\n\n#define DCB_DEMCR_VC_STATERR_Pos            7U                                            /*!< DCB DEMCR: Vector Catch state errors Position */\n#define DCB_DEMCR_VC_STATERR_Msk           (0x1UL << DCB_DEMCR_VC_STATERR_Pos)            /*!< DCB DEMCR: Vector Catch state errors Mask */\n\n#define DCB_DEMCR_VC_CHKERR_Pos             6U                                            /*!< DCB DEMCR: Vector Catch check errors Position */\n#define DCB_DEMCR_VC_CHKERR_Msk            (0x1UL << DCB_DEMCR_VC_CHKERR_Pos)             /*!< DCB DEMCR: Vector Catch check errors Mask */\n\n#define DCB_DEMCR_VC_NOCPERR_Pos            5U                                            /*!< DCB DEMCR: Vector Catch NOCP errors Position */\n#define DCB_DEMCR_VC_NOCPERR_Msk           (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos)            /*!< DCB DEMCR: Vector Catch NOCP errors Mask */\n\n#define DCB_DEMCR_VC_MMERR_Pos              4U                                            /*!< DCB DEMCR: Vector Catch MemManage errors Position */\n#define DCB_DEMCR_VC_MMERR_Msk             (0x1UL << DCB_DEMCR_VC_MMERR_Pos)              /*!< DCB DEMCR: Vector Catch MemManage errors Mask */\n\n#define DCB_DEMCR_VC_CORERESET_Pos          0U                                            /*!< DCB DEMCR: Vector Catch Core reset Position */\n#define DCB_DEMCR_VC_CORERESET_Msk         (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/)      /*!< DCB DEMCR: Vector Catch Core reset Mask */\n\n/* DAUTHCTRL, Debug Authentication Control Register Definitions */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Pos        3U                                            /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPNIDEN_Msk       (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos)        /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPNIDENSEL_Pos        2U                                            /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPNIDENSEL_Msk       (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos)        /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */\n\n#define DCB_DAUTHCTRL_INTSPIDEN_Pos         1U                                            /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */\n#define DCB_DAUTHCTRL_INTSPIDEN_Msk        (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos)         /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */\n\n#define DCB_DAUTHCTRL_SPIDENSEL_Pos         0U                                            /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */\n#define DCB_DAUTHCTRL_SPIDENSEL_Msk        (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/)     /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */\n\n/* DSCSR, Debug Security Control and Status Register Definitions */\n#define DCB_DSCSR_CDSKEY_Pos               17U                                            /*!< DCB DSCSR: CDS write-enable key Position */\n#define DCB_DSCSR_CDSKEY_Msk               (0x1UL << DCB_DSCSR_CDSKEY_Pos)                /*!< DCB DSCSR: CDS write-enable key Mask */\n\n#define DCB_DSCSR_CDS_Pos                  16U                                            /*!< DCB DSCSR: Current domain Secure Position */\n#define DCB_DSCSR_CDS_Msk                  (0x1UL << DCB_DSCSR_CDS_Pos)                   /*!< DCB DSCSR: Current domain Secure Mask */\n\n#define DCB_DSCSR_SBRSEL_Pos                1U                                            /*!< DCB DSCSR: Secure banked register select Position */\n#define DCB_DSCSR_SBRSEL_Msk               (0x1UL << DCB_DSCSR_SBRSEL_Pos)                /*!< DCB DSCSR: Secure banked register select Mask */\n\n#define DCB_DSCSR_SBRSELEN_Pos              0U                                            /*!< DCB DSCSR: Secure banked register select enable Position */\n#define DCB_DSCSR_SBRSELEN_Msk             (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/)          /*!< DCB DSCSR: Secure banked register select enable Mask */\n\n/*@} end of group CMSIS_DCB */\n\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DIB       Debug Identification Block\n  \\brief    Type definitions for the Debug Identification Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Debug Identification Block Registers (DIB).\n */\ntypedef struct\n{\n  __OM  uint32_t DLAR;                   /*!< Offset: 0x000 ( /W)  SCS Software Lock Access Register */\n  __IM  uint32_t DLSR;                   /*!< Offset: 0x004 (R/ )  SCS Software Lock Status Register */\n  __IM  uint32_t DAUTHSTATUS;            /*!< Offset: 0x008 (R/ )  Debug Authentication Status Register */\n  __IM  uint32_t DDEVARCH;               /*!< Offset: 0x00C (R/ )  SCS Device Architecture Register */\n  __IM  uint32_t DDEVTYPE;               /*!< Offset: 0x010 (R/ )  SCS Device Type Register */\n} DIB_Type;\n\n/* DLAR, SCS Software Lock Access Register Definitions */\n#define DIB_DLAR_KEY_Pos                    0U                                            /*!< DIB DLAR: KEY Position */\n#define DIB_DLAR_KEY_Msk                   (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */)        /*!< DIB DLAR: KEY Mask */\n\n/* DLSR, SCS Software Lock Status Register Definitions */\n#define DIB_DLSR_nTT_Pos                    2U                                            /*!< DIB DLSR: Not thirty-two bit Position */\n#define DIB_DLSR_nTT_Msk                   (0x1UL << DIB_DLSR_nTT_Pos )                   /*!< DIB DLSR: Not thirty-two bit Mask */\n\n#define DIB_DLSR_SLK_Pos                    1U                                            /*!< DIB DLSR: Software Lock status Position */\n#define DIB_DLSR_SLK_Msk                   (0x1UL << DIB_DLSR_SLK_Pos )                   /*!< DIB DLSR: Software Lock status Mask */\n\n#define DIB_DLSR_SLI_Pos                    0U                                            /*!< DIB DLSR: Software Lock implemented Position */\n#define DIB_DLSR_SLI_Msk                   (0x1UL /*<< DIB_DLSR_SLI_Pos*/)                /*!< DIB DLSR: Software Lock implemented Mask */\n\n/* DAUTHSTATUS, Debug Authentication Status Register Definitions */\n#define DIB_DAUTHSTATUS_SNID_Pos            6U                                            /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_SNID_Msk           (0x3UL << DIB_DAUTHSTATUS_SNID_Pos )           /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_SID_Pos             4U                                            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_SID_Msk            (0x3UL << DIB_DAUTHSTATUS_SID_Pos )            /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSNID_Pos           2U                                            /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSNID_Msk          (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos )          /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */\n\n#define DIB_DAUTHSTATUS_NSID_Pos            0U                                            /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */\n#define DIB_DAUTHSTATUS_NSID_Msk           (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/)        /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */\n\n/* DDEVARCH, SCS Device Architecture Register Definitions */\n#define DIB_DDEVARCH_ARCHITECT_Pos         21U                                            /*!< DIB DDEVARCH: Architect Position */\n#define DIB_DDEVARCH_ARCHITECT_Msk         (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos )       /*!< DIB DDEVARCH: Architect Mask */\n\n#define DIB_DDEVARCH_PRESENT_Pos           20U                                            /*!< DIB DDEVARCH: DEVARCH Present Position */\n#define DIB_DDEVARCH_PRESENT_Msk           (0x1FUL << DIB_DDEVARCH_PRESENT_Pos )          /*!< DIB DDEVARCH: DEVARCH Present Mask */\n\n#define DIB_DDEVARCH_REVISION_Pos          16U                                            /*!< DIB DDEVARCH: Revision Position */\n#define DIB_DDEVARCH_REVISION_Msk          (0xFUL << DIB_DDEVARCH_REVISION_Pos )          /*!< DIB DDEVARCH: Revision Mask */\n\n#define DIB_DDEVARCH_ARCHVER_Pos           12U                                            /*!< DIB DDEVARCH: Architecture Version Position */\n#define DIB_DDEVARCH_ARCHVER_Msk           (0xFUL << DIB_DDEVARCH_ARCHVER_Pos )           /*!< DIB DDEVARCH: Architecture Version Mask */\n\n#define DIB_DDEVARCH_ARCHPART_Pos           0U                                            /*!< DIB DDEVARCH: Architecture Part Position */\n#define DIB_DDEVARCH_ARCHPART_Msk          (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/)     /*!< DIB DDEVARCH: Architecture Part Mask */\n\n/* DDEVTYPE, SCS Device Type Register Definitions */\n#define DIB_DDEVTYPE_SUB_Pos                4U                                            /*!< DIB DDEVTYPE: Sub-type Position */\n#define DIB_DDEVTYPE_SUB_Msk               (0xFUL << DIB_DDEVTYPE_SUB_Pos )               /*!< DIB DDEVTYPE: Sub-type Mask */\n\n#define DIB_DDEVTYPE_MAJOR_Pos              0U                                            /*!< DIB DDEVTYPE: Major type Position */\n#define DIB_DDEVTYPE_MAJOR_Msk             (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/)          /*!< DIB DDEVTYPE: Major type Mask */\n\n\n/*@} end of group CMSIS_DIB */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define DCB_BASE            (0xE000EDF0UL)                             /*!< DCB Base Address */\n  #define DIB_BASE            (0xE000EFB0UL)                             /*!< DIB Base Address */\n  #define EMSS_BASE           (0xE001E000UL)                             /*!<Enhanced Memory SubSystem Base Address */\n  \n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define DCB                 ((DCB_Type       *)     DCB_BASE         ) /*!< DCB configuration struct */\n  #define DIB                 ((DIB_Type       *)     DIB_BASE         ) /*!< DIB configuration struct */\n  #define EMSS                ((EMSS_Type      *)     EMSS_BASE        ) /*!<Ehanced MSS Registers struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n\n  #define DCB_BASE_NS         (0xE002EDF0UL)                             /*!< DCB Base Address                  (non-secure address space) */\n  #define DIB_BASE_NS         (0xE002EFB0UL)                             /*!< DIB Base Address                  (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define DCB_NS              ((DCB_Type       *)     DCB_BASE_NS      ) /*!< DCB configuration struct          (non-secure address space) */\n  #define DIB_NS              ((DIB_Type       *)     DIB_BASE_NS      ) /*!< DIB configuration struct          (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n  #define SW_SystemReset              __SW_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else \n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    __COMPILER_BARRIER();\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __COMPILER_BARRIER();\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n  __DSB();\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses including\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/**\n  \\brief   Software Reset\n  \\details Initiates a system reset request to reset the CPU.\n */\n__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses including\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         \n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n/* ##################################    Debug Control function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DCBFunctions Debug Control Functions\n  \\brief    Functions that access the Debug Control Block.\n  @{\n */\n\n\n/**\n  \\brief   Set Debug Authentication Control Register\n  \\details writes to Debug Authentication Control register.\n  \\param [in]  value  value to be writen.\n */\n__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register\n  \\details Reads Debug Authentication Control register.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)\n{\n    return (DCB->DAUTHCTRL);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Debug Authentication Control Register (non-secure)\n  \\details writes to non-secure Debug Authentication Control register when in secure state.\n  \\param [in]  value  value to be writen\n */\n__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)\n{\n    __DSB();\n    __ISB();\n    DCB_NS->DAUTHCTRL = value;\n    __DSB();\n    __ISB();\n}\n\n\n/**\n  \\brief   Get Debug Authentication Control Register (non-secure)\n  \\details Reads non-secure Debug Authentication Control register when in secure state.\n  \\return             Debug Authentication Control Register.\n */\n__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)\n{\n    return (DCB_NS->DAUTHCTRL);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n\n\n/* ##################################    Debug Identification function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_DIBFunctions Debug Identification Functions\n  \\brief    Functions that access the Debug Identification Block.\n  @{\n */\n\n\n/**\n  \\brief   Get Debug Authentication Status Register\n  \\details Reads Debug Authentication Status register.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t DIB_GetAuthStatus(void)\n{\n    return (DIB->DAUTHSTATUS);\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Debug Authentication Status Register (non-secure)\n  \\details Reads non-secure Debug Authentication Status register when in secure state.\n  \\return             Debug Authentication Status Register.\n */\n__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)\n{\n    return (DIB_NS->DAUTHSTATUS);\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_DCBFunctions */\n\n\n#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \\\n     (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))\n\n/* ##########################  Cache functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_CacheFunctions Cache Functions\n  \\brief    Functions that configure Instruction and Data cache.\n  @{\n */\n\n/* Cache Size ID Register Macros */\n#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\n#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\n\n#define __SCB_DCACHE_LINE_SIZE  32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */\n#define __SCB_ICACHE_LINE_SIZE  32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */\n\n/**\n  \\brief   Enable I-Cache\n  \\details Turns on I-Cache\n  */\n__STATIC_FORCEINLINE void SCB_EnableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    if (SCB->CCR & SCB_CCR_IC_Msk) return;  /* return if ICache is already enabled */\n\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable I-Cache\n  \\details Turns off I-Cache\n  */\n__STATIC_FORCEINLINE void SCB_DisableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate I-Cache\n  \\details Invalidates I-Cache\n  */\n__STATIC_FORCEINLINE void SCB_InvalidateICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   I-Cache Invalidate by address\n  \\details Invalidates I-Cache for the given address.\n           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           I-Cache memory blocks which are part of given address + given size are invalidated.\n  \\param[in]   addr    address\n  \\param[in]   isize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    if ( isize > 0 ) {\n       int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;\n\n      __DSB();\n\n      do {\n        SCB->ICIMVAU = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr += __SCB_ICACHE_LINE_SIZE;\n        op_size -= __SCB_ICACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n\n/**\n  \\brief   Enable D-Cache\n  \\details Turns on D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_EnableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    if (SCB->CCR & SCB_CCR_DC_Msk) return;  /* return if DCache is already enabled */\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n    __DSB();\n\n    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable D-Cache\n  \\details Turns off D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_DisableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean & invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate D-Cache\n  \\details Invalidates D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean D-Cache\n  \\details Cleans D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_CleanDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\n                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean & Invalidate D-Cache\n  \\details Cleans and Invalidates D-Cache\n  */\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U;                       /* select Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean & invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Invalidate by address\n  \\details Invalidates D-Cache for the given address.\n           D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           D-Cache memory blocks which are part of given address + given size are invalidated.\n  \\param[in]   addr    address\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    if ( dsize > 0 ) { \n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\n    \n      __DSB();\n\n      do {\n        SCB->DCIMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr += __SCB_DCACHE_LINE_SIZE;\n        op_size -= __SCB_DCACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean by address\n  \\details Cleans D-Cache for the given address\n           D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.\n           D-Cache memory blocks which are part of given address + given size are cleaned.\n  \\param[in]   addr    address\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    if ( dsize > 0 ) { \n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\n    \n      __DSB();\n\n      do {\n        SCB->DCCMVAC = op_addr;             /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr += __SCB_DCACHE_LINE_SIZE;\n        op_size -= __SCB_DCACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean and Invalidate by address\n  \\details Cleans and invalidates D_Cache for the given address\n           D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    if ( dsize > 0 ) { \n       int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));\n      uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;\n    \n      __DSB();\n\n      do {\n        SCB->DCCIMVAC = op_addr;            /* register accepts only 32byte aligned values, only bits 31..5 are valid */\n        op_addr +=          __SCB_DCACHE_LINE_SIZE;\n        op_size -=          __SCB_DCACHE_LINE_SIZE;\n      } while ( op_size > 0 );\n\n      __DSB();\n      __ISB();\n    }\n  #endif\n}\n\n/*@} end of CMSIS_Core_CacheFunctions */\n#endif\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_STAR_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h",
    "content": "/******************************************************************************\n * @file     mpu_armv7.h\n * @brief    CMSIS MPU API for Armv7-M MPU\n * @version  V5.1.2\n * @date     25. May 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n \n#ifndef ARM_MPU_ARMV7_H\n#define ARM_MPU_ARMV7_H\n\n#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\n#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\n#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\n#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\n#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\n#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\n#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\n#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\n#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\n#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\n#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\n#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\n#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\n#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\n#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\n#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\n#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\n#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\n#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\n#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\n#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\n#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\n#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\n#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\n#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\n#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\n#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\n#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\n\n#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\n#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\n#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only\n#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\n#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only\n#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access\n\n/** MPU Region Base Address Register Value\n*\n* \\param Region The region to be configured, number 0 to 15.\n* \\param BaseAddress The base address for the region.\n*/\n#define ARM_MPU_RBAR(Region, BaseAddress) \\\n  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \\\n   ((Region) & MPU_RBAR_REGION_Msk)    |  \\\n   (MPU_RBAR_VALID_Msk))\n\n/**\n* MPU Memory Access Attributes\n* \n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n*/  \n#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \\\n  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \\\n   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \\\n   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \\\n   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))\n\n/**\n* MPU Region Attribute and Size Register Value\n* \n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param AccessAttributes  Memory access attribution, see \\ref ARM_MPU_ACCESS_.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/\n#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \\\n  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \\\n   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \\\n   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \\\n   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \\\n   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \\\n   (((MPU_RASR_ENABLE_Msk))))\n\n/**\n* MPU Region Attribute and Size Register Value\n* \n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/                         \n#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\\n  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\n\n/**\n* MPU Memory Access Attribute for strongly ordered memory.\n*  - TEX: 000b\n*  - Shareable\n*  - Non-cacheable\n*  - Non-bufferable\n*/ \n#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\n\n/**\n* MPU Memory Access Attribute for device memory.\n*  - TEX: 000b (if shareable) or 010b (if non-shareable)\n*  - Shareable or non-shareable\n*  - Non-cacheable\n*  - Bufferable (if shareable) or non-bufferable (if non-shareable)\n*\n* \\param IsShareable Configures the device memory as shareable or non-shareable.\n*/ \n#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\n\n/**\n* MPU Memory Access Attribute for normal memory.\n*  - TEX: 1BBb (reflecting outer cacheability rules)\n*  - Shareable or non-shareable\n*  - Cacheable or non-cacheable (reflecting inner cacheability rules)\n*  - Bufferable or non-bufferable (reflecting inner cacheability rules)\n*\n* \\param OuterCp Configures the outer cache policy.\n* \\param InnerCp Configures the inner cache policy.\n* \\param IsShareable Configures the memory as shareable or non-shareable.\n*/ \n#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))\n\n/**\n* MPU Memory Access Attribute non-cacheable policy.\n*/\n#define ARM_MPU_CACHEP_NOCACHE 0U\n\n/**\n* MPU Memory Access Attribute write-back, write and read allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_WRA 1U\n\n/**\n* MPU Memory Access Attribute write-through, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WT_NWA 2U\n\n/**\n* MPU Memory Access Attribute write-back, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_NWA 3U\n\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR; //!< The region base address register value (RBAR)\n  uint32_t RASR; //!< The region attribute and size register value (RASR) \\ref MPU_RASR\n} ARM_MPU_Region_t;\n    \n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\n{\n  __DMB();\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  __DSB();\n  __ISB();\n}\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void)\n{\n  __DMB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n  __DSB();\n  __ISB();\n}\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\n{\n  MPU->RNR = rnr;\n  MPU->RASR = 0U;\n}\n\n/** Configure an MPU region.\n* \\param rbar Value for RBAR register.\n* \\param rasr Value for RASR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\n{\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rasr Value for RASR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\n{\n  MPU->RNR = rnr;\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i) \n  {\n    dst[i] = src[i];\n  }\n}\n\n/** Load the given number of MPU regions from a table.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\n  while (cnt > MPU_TYPE_RALIASES) {\n    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\n    table += MPU_TYPE_RALIASES;\n    cnt -= MPU_TYPE_RALIASES;\n  }\n  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\n}\n\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h",
    "content": "/******************************************************************************\n * @file     mpu_armv8.h\n * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU\n * @version  V5.9.0\n * @date     11. April 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n\n#ifndef ARM_MPU_ARMV8_H\n#define ARM_MPU_ARMV8_H\n\n/** \\brief Attribute for device memory (outer only) */\n#define ARM_MPU_ATTR_DEVICE                           ( 0U )\n\n/** \\brief Attribute for non-cacheable, normal memory */\n#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )\n\n/** \\brief Attribute for Normal memory, Outer and Inner cacheability.\n* \\param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.\n* \\param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.\n* \\param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.\n* \\param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.\n*/\n#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\\n  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))\n\n/** \\brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\n\n/** \\brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)\n\n/** \\brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)\n\n/** \\brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_GRE    (3U)\n\n/** \\brief Normal memory outer-cacheable and inner-cacheable attributes\n* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate\n*/\n#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100)\n#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA      (0b0010)\n#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA      (0b0001)\n#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA   (0b0011)\n#define MPU_ATTR_NORMAL_OUTER_WT_RA         (0b1010)\n#define MPU_ATTR_NORMAL_OUTER_WT_WA         (0b1001)\n#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA      (0b1011)\n#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA      (0b0101)\n#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA      (0b0110)\n#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA   (0b0111)\n#define MPU_ATTR_NORMAL_OUTER_WB_RA         (0b1101)\n#define MPU_ATTR_NORMAL_OUTER_WB_WA         (0b1110)\n#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA      (0b1111)\n#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100)\n#define MPU_ATTR_NORMAL_INNER_WT_TR_RA      (0b0010)\n#define MPU_ATTR_NORMAL_INNER_WT_TR_WA      (0b0001)\n#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA   (0b0011)\n#define MPU_ATTR_NORMAL_INNER_WT_RA         (0b1010)\n#define MPU_ATTR_NORMAL_INNER_WT_WA         (0b1001)\n#define MPU_ATTR_NORMAL_INNER_WT_RA_WA      (0b1011)\n#define MPU_ATTR_NORMAL_INNER_WB_TR_RA      (0b0101)\n#define MPU_ATTR_NORMAL_INNER_WB_TR_WA      (0b0110)\n#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA   (0b0111)\n#define MPU_ATTR_NORMAL_INNER_WB_RA         (0b1101)\n#define MPU_ATTR_NORMAL_INNER_WB_WA         (0b1110)\n#define MPU_ATTR_NORMAL_INNER_WB_RA_WA      (0b1111)\n\n/** \\brief Memory Attribute\n* \\param O Outer memory attributes\n* \\param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\n*/\n#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))\n\n/* \\brief Specifies MAIR_ATTR number */\n#define MAIR_ATTR(x)\t\t\t\t\t\t((x > 7 || x < 0) ? 0 : x)\n\n/**\n * Shareability\n */\n/** \\brief Normal memory, non-shareable  */\n#define ARM_MPU_SH_NON   (0U)\n\n/** \\brief Normal memory, outer shareable  */\n#define ARM_MPU_SH_OUTER (2U)\n\n/** \\brief Normal memory, inner shareable  */\n#define ARM_MPU_SH_INNER (3U)\n\n/**\n * Access permissions\n * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only\n */\n/** \\brief Normal memory, read/write */\n#define ARM_MPU_AP_RW (0U)\n\n/** \\brief Normal memory, read-only */\n#define ARM_MPU_AP_RO (1U)\n\n/** \\brief Normal memory, any privilege level */\n#define ARM_MPU_AP_NP (1U)\n\n/** \\brief Normal memory, privileged access only */\n#define ARM_MPU_AP_PO (0U)\n\n/*\n * Execute-never\n * XN = Execute-never, EX = Executable\n */\n/** \\brief Normal memory, Execution only permitted if read permitted */\n#define ARM_MPU_XN (1U)\n\n/** \\brief Normal memory, Execution only permitted if read permitted */\n#define ARM_MPU_EX (0U)\n\n/** \\brief Memory access permissions\n* \\param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory.\n* \\param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory.\n*/\n#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))\n\n/** \\brief Region Base Address Register value\n* \\param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\n* \\param SH Defines the Shareability domain for this memory region.\n* \\param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.\n* \\param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.\n* \\param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.\n*/\n#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\\n  (((BASE) & MPU_RBAR_BASE_Msk) | \\\n  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\\n  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\\n  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\n\n/** \\brief Region Limit Address Register value\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\n* \\param IDX The attribute index to be associated with this memory region.\n*/\n#define ARM_MPU_RLAR(LIMIT, IDX) \\\n  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \\\n  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\\n  (MPU_RLAR_EN_Msk))\n\n#if defined(MPU_RLAR_PXN_Pos)\n  \n/** \\brief Region Limit Address Register with PXN value\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\n* \\param PXN Privileged execute never. Defines whether code can be executed from this privileged region.\n* \\param IDX The attribute index to be associated with this memory region.\n*/\n#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \\\n  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \\\n  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \\\n  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\\n  (MPU_RLAR_EN_Msk))\n  \n#endif\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR;                   /*!< Region Base Address Register value */\n  uint32_t RLAR;                   /*!< Region Limit Address Register value */\n} ARM_MPU_Region_t;\n\n/**\n  \\brief  Read MPU Type Register\n  \\return Number of MPU regions\n*/\n__STATIC_INLINE uint32_t ARM_MPU_TYPE()\n{\n  return ((MPU->TYPE) >> 8);\n}\n    \n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\n{\n  __DMB();\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  __DSB();\n  __ISB();\n}\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void)\n{\n  __DMB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n  __DSB();\n  __ISB();\n}\n\n#ifdef MPU_NS\n/** Enable the Non-secure MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\n{\n  __DMB();\n  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  __DSB();\n  __ISB();\n}\n\n/** Disable the Non-secure MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable_NS(void)\n{\n  __DMB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n  __DSB();\n  __ISB();\n}\n#endif\n\n/** Set the memory attribute encoding to the given MPU.\n* \\param mpu Pointer to the MPU to be configured.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\n{\n  const uint8_t reg = idx / 4U;\n  const uint32_t pos = ((idx % 4U) * 8U);\n  const uint32_t mask = 0xFFU << pos;\n  \n  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\n    return; // invalid index\n  }\n  \n  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\n}\n\n/** Set the memory attribute encoding.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\n{\n  ARM_MPU_SetMemAttrEx(MPU, idx, attr);\n}\n\n#ifdef MPU_NS\n/** Set the memory attribute encoding to the Non-secure MPU.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\n{\n  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\n}\n#endif\n\n/** Clear and disable the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\n{\n  mpu->RNR = rnr;\n  mpu->RLAR = 0U;\n}\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\n{\n  ARM_MPU_ClrRegionEx(MPU, rnr);\n}\n\n#ifdef MPU_NS\n/** Clear and disable the given Non-secure MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\n{  \n  ARM_MPU_ClrRegionEx(MPU_NS, rnr);\n}\n#endif\n\n/** Configure the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  mpu->RNR = rnr;\n  mpu->RBAR = rbar;\n  mpu->RLAR = rlar;\n}\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\n}\n\n#ifdef MPU_NS\n/** Configure the given Non-secure MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  \n}\n#endif\n\n/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i) \n  {\n    dst[i] = src[i];\n  }\n}\n\n/** Load the given number of MPU regions from a table to the given MPU.\n* \\param mpu Pointer to the MPU registers to be used.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\n  if (cnt == 1U) {\n    mpu->RNR = rnr;\n    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\n  } else {\n    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);\n    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\n    \n    mpu->RNR = rnrBase;\n    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\n      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\n      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\n      table += c;\n      cnt -= c;\n      rnrOffset = 0U;\n      rnrBase += MPU_TYPE_RALIASES;\n      mpu->RNR = rnrBase;\n    }\n    \n    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\n  }\n}\n\n/** Load the given number of MPU regions from a table.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  ARM_MPU_LoadEx(MPU, rnr, table, cnt);\n}\n\n#ifdef MPU_NS\n/** Load the given number of MPU regions from a table to the Non-secure MPU.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\n}\n#endif\n\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/pac_armv81.h",
    "content": "/******************************************************************************\n * @file     pac_armv81.h\n * @brief    CMSIS PAC key functions for Armv8.1-M PAC extension\n * @version  V1.0.0\n * @date     23. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n\n#ifndef PAC_ARMV81_H\n#define PAC_ARMV81_H\n\n\n/* ###################  PAC Key functions  ########################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_PacKeyFunctions PAC Key functions\n  \\brief    Functions that access the PAC keys.\n  @{\n */\n\n#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))\n\n/**\n  \\brief   read the PAC key used for privileged mode\n  \\details Reads the PAC key stored in the PAC_KEY_P registers.\n  \\param [out]    pPacKey  128bit PAC key\n */\n__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {\n  __ASM volatile (\n  \"mrs   r1, pac_key_p_0\\n\"\n  \"str   r1,[%0,#0]\\n\"\n  \"mrs   r1, pac_key_p_1\\n\"\n  \"str   r1,[%0,#4]\\n\"\n  \"mrs   r1, pac_key_p_2\\n\"\n  \"str   r1,[%0,#8]\\n\"\n  \"mrs   r1, pac_key_p_3\\n\"\n  \"str   r1,[%0,#12]\\n\"\n  : : \"r\" (pPacKey) : \"memory\", \"r1\"\n  );\n}\n\n/**\n  \\brief   write the PAC key used for privileged mode\n  \\details writes the given PAC key to the PAC_KEY_P registers.\n  \\param [in]    pPacKey  128bit PAC key\n */\n__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {\n  __ASM volatile (\n  \"ldr   r1,[%0,#0]\\n\"\n  \"msr   pac_key_p_0, r1\\n\"\n  \"ldr   r1,[%0,#4]\\n\"\n  \"msr   pac_key_p_1, r1\\n\"\n  \"ldr   r1,[%0,#8]\\n\"\n  \"msr   pac_key_p_2, r1\\n\"\n  \"ldr   r1,[%0,#12]\\n\"\n  \"msr   pac_key_p_3, r1\\n\"\n  : : \"r\" (pPacKey) : \"memory\", \"r1\"\n  );\n}\n\n/**\n  \\brief   read the PAC key used for unprivileged mode\n  \\details Reads the PAC key stored in the PAC_KEY_U registers.\n  \\param [out]    pPacKey  128bit PAC key\n */\n__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {\n  __ASM volatile (\n  \"mrs   r1, pac_key_u_0\\n\"\n  \"str   r1,[%0,#0]\\n\"\n  \"mrs   r1, pac_key_u_1\\n\"\n  \"str   r1,[%0,#4]\\n\"\n  \"mrs   r1, pac_key_u_2\\n\"\n  \"str   r1,[%0,#8]\\n\"\n  \"mrs   r1, pac_key_u_3\\n\"\n  \"str   r1,[%0,#12]\\n\"\n  : : \"r\" (pPacKey) : \"memory\", \"r1\"\n  );\n}\n\n/**\n  \\brief   write the PAC key used for unprivileged mode\n  \\details writes the given PAC key to the PAC_KEY_U registers.\n  \\param [in]    pPacKey  128bit PAC key\n */\n__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {\n  __ASM volatile (\n  \"ldr   r1,[%0,#0]\\n\"\n  \"msr   pac_key_u_0, r1\\n\"\n  \"ldr   r1,[%0,#4]\\n\"\n  \"msr   pac_key_u_1, r1\\n\"\n  \"ldr   r1,[%0,#8]\\n\"\n  \"msr   pac_key_u_2, r1\\n\"\n  \"ldr   r1,[%0,#12]\\n\"\n  \"msr   pac_key_u_3, r1\\n\"\n  : : \"r\" (pPacKey) : \"memory\", \"r1\"\n  );\n}\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n\n/**\n  \\brief   read the PAC key used for privileged mode (non-secure)\n  \\details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.\n  \\param [out]    pPacKey  128bit PAC key\n */\n__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {\n  __ASM volatile (\n  \"mrs   r1, pac_key_p_0_ns\\n\"\n  \"str   r1,[%0,#0]\\n\"\n  \"mrs   r1, pac_key_p_1_ns\\n\"\n  \"str   r1,[%0,#4]\\n\"\n  \"mrs   r1, pac_key_p_2_ns\\n\"\n  \"str   r1,[%0,#8]\\n\"\n  \"mrs   r1, pac_key_p_3_ns\\n\"\n  \"str   r1,[%0,#12]\\n\"\n  : : \"r\" (pPacKey) : \"memory\", \"r1\"\n  );\n}\n\n/**\n  \\brief   write the PAC key used for privileged mode (non-secure)\n  \\details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.\n  \\param [in]    pPacKey  128bit PAC key\n */\n__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {\n  __ASM volatile (\n  \"ldr   r1,[%0,#0]\\n\"\n  \"msr   pac_key_p_0_ns, r1\\n\"\n  \"ldr   r1,[%0,#4]\\n\"\n  \"msr   pac_key_p_1_ns, r1\\n\"\n  \"ldr   r1,[%0,#8]\\n\"\n  \"msr   pac_key_p_2_ns, r1\\n\"\n  \"ldr   r1,[%0,#12]\\n\"\n  \"msr   pac_key_p_3_ns, r1\\n\"\n  : : \"r\" (pPacKey) : \"memory\", \"r1\"\n  );\n}\n\n/**\n  \\brief   read the PAC key used for unprivileged mode (non-secure)\n  \\details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.\n  \\param [out]    pPacKey  128bit PAC key\n */\n__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {\n  __ASM volatile (\n  \"mrs   r1, pac_key_u_0_ns\\n\"\n  \"str   r1,[%0,#0]\\n\"\n  \"mrs   r1, pac_key_u_1_ns\\n\"\n  \"str   r1,[%0,#4]\\n\"\n  \"mrs   r1, pac_key_u_2_ns\\n\"\n  \"str   r1,[%0,#8]\\n\"\n  \"mrs   r1, pac_key_u_3_ns\\n\"\n  \"str   r1,[%0,#12]\\n\"\n  : : \"r\" (pPacKey) : \"memory\", \"r1\"\n  );\n}\n\n/**\n  \\brief   write the PAC key used for unprivileged mode (non-secure)\n  \\details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.\n  \\param [in]    pPacKey  128bit PAC key\n */\n__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {\n  __ASM volatile (\n  \"ldr   r1,[%0,#0]\\n\"\n  \"msr   pac_key_u_0_ns, r1\\n\"\n  \"ldr   r1,[%0,#4]\\n\"\n  \"msr   pac_key_u_1_ns, r1\\n\"\n  \"ldr   r1,[%0,#8]\\n\"\n  \"msr   pac_key_u_2_ns, r1\\n\"\n  \"ldr   r1,[%0,#12]\\n\"\n  \"msr   pac_key_u_3_ns, r1\\n\"\n  : : \"r\" (pPacKey) : \"memory\", \"r1\"\n  );\n}\n\n#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */\n\n#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */\n\n/*@} end of CMSIS_Core_PacKeyFunctions */\n\n\n#endif /* PAC_ARMV81_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h",
    "content": "/******************************************************************************\n * @file     pmu_armv8.h\n * @brief    CMSIS PMU API for Armv8.1-M PMU\n * @version  V1.0.1\n * @date     15. April 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n\n#ifndef ARM_PMU_ARMV8_H\n#define ARM_PMU_ARMV8_H\n\n/**\n * \\brief PMU Events\n * \\note  See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.\n * */\n\n#define ARM_PMU_SW_INCR                              0x0000             /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */\n#define ARM_PMU_L1I_CACHE_REFILL                     0x0001             /*!< L1 I-Cache refill */\n#define ARM_PMU_L1D_CACHE_REFILL                     0x0003             /*!< L1 D-Cache refill */\n#define ARM_PMU_L1D_CACHE                            0x0004             /*!< L1 D-Cache access */\n#define ARM_PMU_LD_RETIRED                           0x0006             /*!< Memory-reading instruction architecturally executed and condition code check pass */\n#define ARM_PMU_ST_RETIRED                           0x0007             /*!< Memory-writing instruction architecturally executed and condition code check pass */\n#define ARM_PMU_INST_RETIRED                         0x0008             /*!< Instruction architecturally executed */\n#define ARM_PMU_EXC_TAKEN                            0x0009             /*!< Exception entry */\n#define ARM_PMU_EXC_RETURN                           0x000A             /*!< Exception return instruction architecturally executed and the condition code check pass */\n#define ARM_PMU_PC_WRITE_RETIRED                     0x000C             /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */\n#define ARM_PMU_BR_IMMED_RETIRED                     0x000D             /*!< Immediate branch architecturally executed */\n#define ARM_PMU_BR_RETURN_RETIRED                    0x000E             /*!< Function return instruction architecturally executed and the condition code check pass */\n#define ARM_PMU_UNALIGNED_LDST_RETIRED               0x000F             /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */\n#define ARM_PMU_BR_MIS_PRED                          0x0010             /*!< Mispredicted or not predicted branch speculatively executed */\n#define ARM_PMU_CPU_CYCLES                           0x0011             /*!< Cycle */\n#define ARM_PMU_BR_PRED                              0x0012             /*!< Predictable branch speculatively executed */\n#define ARM_PMU_MEM_ACCESS                           0x0013             /*!< Data memory access */\n#define ARM_PMU_L1I_CACHE                            0x0014             /*!< Level 1 instruction cache access */\n#define ARM_PMU_L1D_CACHE_WB                         0x0015             /*!< Level 1 data cache write-back */\n#define ARM_PMU_L2D_CACHE                            0x0016             /*!< Level 2 data cache access */\n#define ARM_PMU_L2D_CACHE_REFILL                     0x0017             /*!< Level 2 data cache refill */\n#define ARM_PMU_L2D_CACHE_WB                         0x0018             /*!< Level 2 data cache write-back */\n#define ARM_PMU_BUS_ACCESS                           0x0019             /*!< Bus access */\n#define ARM_PMU_MEMORY_ERROR                         0x001A             /*!< Local memory error */\n#define ARM_PMU_INST_SPEC                            0x001B             /*!< Instruction speculatively executed */\n#define ARM_PMU_BUS_CYCLES                           0x001D             /*!< Bus cycles */\n#define ARM_PMU_CHAIN                                0x001E             /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */\n#define ARM_PMU_L1D_CACHE_ALLOCATE                   0x001F             /*!< Level 1 data cache allocation without refill */\n#define ARM_PMU_L2D_CACHE_ALLOCATE                   0x0020             /*!< Level 2 data cache allocation without refill */\n#define ARM_PMU_BR_RETIRED                           0x0021             /*!< Branch instruction architecturally executed */\n#define ARM_PMU_BR_MIS_PRED_RETIRED                  0x0022             /*!< Mispredicted branch instruction architecturally executed */\n#define ARM_PMU_STALL_FRONTEND                       0x0023             /*!< No operation issued because of the frontend */\n#define ARM_PMU_STALL_BACKEND                        0x0024             /*!< No operation issued because of the backend */\n#define ARM_PMU_L2I_CACHE                            0x0027             /*!< Level 2 instruction cache access */\n#define ARM_PMU_L2I_CACHE_REFILL                     0x0028             /*!< Level 2 instruction cache refill */\n#define ARM_PMU_L3D_CACHE_ALLOCATE                   0x0029             /*!< Level 3 data cache allocation without refill */\n#define ARM_PMU_L3D_CACHE_REFILL                     0x002A             /*!< Level 3 data cache refill */\n#define ARM_PMU_L3D_CACHE                            0x002B             /*!< Level 3 data cache access */\n#define ARM_PMU_L3D_CACHE_WB                         0x002C             /*!< Level 3 data cache write-back */\n#define ARM_PMU_LL_CACHE_RD                          0x0036             /*!< Last level data cache read */\n#define ARM_PMU_LL_CACHE_MISS_RD                     0x0037             /*!< Last level data cache read miss */\n#define ARM_PMU_L1D_CACHE_MISS_RD                    0x0039             /*!< Level 1 data cache read miss */\n#define ARM_PMU_OP_COMPLETE                          0x003A             /*!< Operation retired */\n#define ARM_PMU_OP_SPEC                              0x003B             /*!< Operation speculatively executed */\n#define ARM_PMU_STALL                                0x003C             /*!< Stall cycle for instruction or operation not sent for execution */\n#define ARM_PMU_STALL_OP_BACKEND                     0x003D             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */\n#define ARM_PMU_STALL_OP_FRONTEND                    0x003E             /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */\n#define ARM_PMU_STALL_OP                             0x003F             /*!< Instruction or operation slots not occupied each cycle */\n#define ARM_PMU_L1D_CACHE_RD                         0x0040             /*!< Level 1 data cache read */\n#define ARM_PMU_LE_RETIRED                           0x0100             /*!< Loop end instruction executed */\n#define ARM_PMU_LE_SPEC                              0x0101             /*!< Loop end instruction speculatively executed */\n#define ARM_PMU_BF_RETIRED                           0x0104             /*!< Branch future instruction architecturally executed and condition code check pass */\n#define ARM_PMU_BF_SPEC                              0x0105             /*!< Branch future instruction speculatively executed and condition code check pass */\n#define ARM_PMU_LE_CANCEL                            0x0108             /*!< Loop end instruction not taken */\n#define ARM_PMU_BF_CANCEL                            0x0109             /*!< Branch future instruction not taken */\n#define ARM_PMU_SE_CALL_S                            0x0114             /*!< Call to secure function, resulting in Security state change */\n#define ARM_PMU_SE_CALL_NS                           0x0115             /*!< Call to non-secure function, resulting in Security state change */\n#define ARM_PMU_DWT_CMPMATCH0                        0x0118             /*!< DWT comparator 0 match */\n#define ARM_PMU_DWT_CMPMATCH1                        0x0119             /*!< DWT comparator 1 match */\n#define ARM_PMU_DWT_CMPMATCH2                        0x011A             /*!< DWT comparator 2 match */\n#define ARM_PMU_DWT_CMPMATCH3                        0x011B             /*!< DWT comparator 3 match */\n#define ARM_PMU_MVE_INST_RETIRED                     0x0200             /*!< MVE instruction architecturally executed */\n#define ARM_PMU_MVE_INST_SPEC                        0x0201             /*!< MVE instruction speculatively executed */\n#define ARM_PMU_MVE_FP_RETIRED                       0x0204             /*!< MVE floating-point instruction architecturally executed */\n#define ARM_PMU_MVE_FP_SPEC                          0x0205             /*!< MVE floating-point instruction speculatively executed */\n#define ARM_PMU_MVE_FP_HP_RETIRED                    0x0208             /*!< MVE half-precision floating-point instruction architecturally executed */\n#define ARM_PMU_MVE_FP_HP_SPEC                       0x0209             /*!< MVE half-precision floating-point instruction speculatively executed */\n#define ARM_PMU_MVE_FP_SP_RETIRED                    0x020C             /*!< MVE single-precision floating-point instruction architecturally executed */\n#define ARM_PMU_MVE_FP_SP_SPEC                       0x020D             /*!< MVE single-precision floating-point instruction speculatively executed */\n#define ARM_PMU_MVE_FP_MAC_RETIRED                   0x0214             /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */\n#define ARM_PMU_MVE_FP_MAC_SPEC                      0x0215             /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */\n#define ARM_PMU_MVE_INT_RETIRED                      0x0224             /*!< MVE integer instruction architecturally executed */\n#define ARM_PMU_MVE_INT_SPEC                         0x0225             /*!< MVE integer instruction speculatively executed */\n#define ARM_PMU_MVE_INT_MAC_RETIRED                  0x0228             /*!< MVE multiply or multiply-accumulate instruction architecturally executed */\n#define ARM_PMU_MVE_INT_MAC_SPEC                     0x0229             /*!< MVE multiply or multiply-accumulate instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_RETIRED                     0x0238             /*!< MVE load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_SPEC                        0x0239             /*!< MVE load or store instruction speculatively executed */\n#define ARM_PMU_MVE_LD_RETIRED                       0x023C             /*!< MVE load instruction architecturally executed */\n#define ARM_PMU_MVE_LD_SPEC                          0x023D             /*!< MVE load instruction speculatively executed */\n#define ARM_PMU_MVE_ST_RETIRED                       0x0240             /*!< MVE store instruction architecturally executed */\n#define ARM_PMU_MVE_ST_SPEC                          0x0241             /*!< MVE store instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_CONTIG_RETIRED              0x0244             /*!< MVE contiguous load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_CONTIG_SPEC                 0x0245             /*!< MVE contiguous load or store instruction speculatively executed */\n#define ARM_PMU_MVE_LD_CONTIG_RETIRED                0x0248             /*!< MVE contiguous load instruction architecturally executed */\n#define ARM_PMU_MVE_LD_CONTIG_SPEC                   0x0249             /*!< MVE contiguous load instruction speculatively executed */\n#define ARM_PMU_MVE_ST_CONTIG_RETIRED                0x024C             /*!< MVE contiguous store instruction architecturally executed */\n#define ARM_PMU_MVE_ST_CONTIG_SPEC                   0x024D             /*!< MVE contiguous store instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED           0x0250             /*!< MVE non-contiguous load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC              0x0251             /*!< MVE non-contiguous load or store instruction speculatively executed */\n#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED             0x0254             /*!< MVE non-contiguous load instruction architecturally executed */\n#define ARM_PMU_MVE_LD_NONCONTIG_SPEC                0x0255             /*!< MVE non-contiguous load instruction speculatively executed */\n#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED             0x0258             /*!< MVE non-contiguous store instruction architecturally executed */\n#define ARM_PMU_MVE_ST_NONCONTIG_SPEC                0x0259             /*!< MVE non-contiguous store instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_MULTI_RETIRED               0x025C             /*!< MVE memory instruction targeting multiple registers architecturally executed */\n#define ARM_PMU_MVE_LDST_MULTI_SPEC                  0x025D             /*!< MVE memory instruction targeting multiple registers speculatively executed */\n#define ARM_PMU_MVE_LD_MULTI_RETIRED                 0x0260             /*!< MVE memory load instruction targeting multiple registers architecturally executed */\n#define ARM_PMU_MVE_LD_MULTI_SPEC                    0x0261             /*!< MVE memory load instruction targeting multiple registers speculatively executed */\n#define ARM_PMU_MVE_ST_MULTI_RETIRED                 0x0261             /*!< MVE memory store instruction targeting multiple registers architecturally executed */\n#define ARM_PMU_MVE_ST_MULTI_SPEC                    0x0265             /*!< MVE memory store instruction targeting multiple registers speculatively executed */\n#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED           0x028C             /*!< MVE unaligned memory load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC              0x028D             /*!< MVE unaligned memory load or store instruction speculatively executed */\n#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED             0x0290             /*!< MVE unaligned load instruction architecturally executed */\n#define ARM_PMU_MVE_LD_UNALIGNED_SPEC                0x0291             /*!< MVE unaligned load instruction speculatively executed */\n#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED             0x0294             /*!< MVE unaligned store instruction architecturally executed */\n#define ARM_PMU_MVE_ST_UNALIGNED_SPEC                0x0295             /*!< MVE unaligned store instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298             /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC    0x0299             /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */\n#define ARM_PMU_MVE_VREDUCE_RETIRED                  0x02A0             /*!< MVE vector reduction instruction architecturally executed */\n#define ARM_PMU_MVE_VREDUCE_SPEC                     0x02A1             /*!< MVE vector reduction instruction speculatively executed */\n#define ARM_PMU_MVE_VREDUCE_FP_RETIRED               0x02A4             /*!< MVE floating-point vector reduction instruction architecturally executed */\n#define ARM_PMU_MVE_VREDUCE_FP_SPEC                  0x02A5             /*!< MVE floating-point vector reduction instruction speculatively executed */\n#define ARM_PMU_MVE_VREDUCE_INT_RETIRED              0x02A8             /*!< MVE integer vector reduction instruction architecturally executed */\n#define ARM_PMU_MVE_VREDUCE_INT_SPEC                 0x02A9             /*!< MVE integer vector reduction instruction speculatively executed */\n#define ARM_PMU_MVE_PRED                             0x02B8             /*!< Cycles where one or more predicated beats architecturally executed */\n#define ARM_PMU_MVE_STALL                            0x02CC             /*!< Stall cycles caused by an MVE instruction */\n#define ARM_PMU_MVE_STALL_RESOURCE                   0x02CD             /*!< Stall cycles caused by an MVE instruction because of resource conflicts */\n#define ARM_PMU_MVE_STALL_RESOURCE_MEM               0x02CE             /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */\n#define ARM_PMU_MVE_STALL_RESOURCE_FP                0x02CF             /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */\n#define ARM_PMU_MVE_STALL_RESOURCE_INT               0x02D0             /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */\n#define ARM_PMU_MVE_STALL_BREAK                      0x02D3             /*!< Stall cycles caused by an MVE chain break */\n#define ARM_PMU_MVE_STALL_DEPENDENCY                 0x02D4             /*!< Stall cycles caused by MVE register dependency */\n#define ARM_PMU_ITCM_ACCESS                          0x4007             /*!< Instruction TCM access */\n#define ARM_PMU_DTCM_ACCESS                          0x4008             /*!< Data TCM access */\n#define ARM_PMU_TRCEXTOUT0                           0x4010             /*!< ETM external output 0 */\n#define ARM_PMU_TRCEXTOUT1                           0x4011             /*!< ETM external output 1 */\n#define ARM_PMU_TRCEXTOUT2                           0x4012             /*!< ETM external output 2 */\n#define ARM_PMU_TRCEXTOUT3                           0x4013             /*!< ETM external output 3 */\n#define ARM_PMU_CTI_TRIGOUT4                         0x4018             /*!< Cross-trigger Interface output trigger 4 */\n#define ARM_PMU_CTI_TRIGOUT5                         0x4019             /*!< Cross-trigger Interface output trigger 5 */\n#define ARM_PMU_CTI_TRIGOUT6                         0x401A             /*!< Cross-trigger Interface output trigger 6 */\n#define ARM_PMU_CTI_TRIGOUT7                         0x401B             /*!< Cross-trigger Interface output trigger 7 */\n\n/** \\brief PMU Functions */\n\n__STATIC_INLINE void ARM_PMU_Enable(void);\n__STATIC_INLINE void ARM_PMU_Disable(void);\n\n__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);\n\n__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);\n__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);\n\n__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);\n__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);\n\n__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);\n__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);\n\n__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);\n__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);\n\n__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);\n__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);\n\n__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);\n\n/** \n  \\brief   Enable the PMU\n*/\n__STATIC_INLINE void ARM_PMU_Enable(void) \n{\n  PMU->CTRL |= PMU_CTRL_ENABLE_Msk;\n}\n\n/** \n  \\brief   Disable the PMU\n*/\n__STATIC_INLINE void ARM_PMU_Disable(void) \n{\n  PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;\n}\n\n/** \n  \\brief   Set event to count for PMU eventer counter\n  \\param [in]    num     Event counter (0-30) to configure\n  \\param [in]    type    Event to count\n*/\n__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)\n{\n  PMU->EVTYPER[num] = type;\n}\n\n/** \n  \\brief  Reset cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)\n{\n  PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;\n}\n\n/** \n  \\brief  Reset all event counters\n*/\n__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)\n{\n  PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;\n}\n\n/** \n  \\brief  Enable counters \n  \\param [in]     mask    Counters to enable\n  \\note   Enables one or more of the following:\n          - event counters (0-30)\n          - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)\n{\n  PMU->CNTENSET = mask;\n}\n\n/** \n  \\brief  Disable counters\n  \\param [in]     mask    Counters to enable\n  \\note   Disables one or more of the following:\n          - event counters (0-30)\n          - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)\n{\n  PMU->CNTENCLR = mask;\n}\n\n/** \n  \\brief  Read cycle counter\n  \\return                 Cycle count\n*/\n__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)\n{\n  return PMU->CCNTR;\n}\n\n/** \n  \\brief   Read event counter\n  \\param [in]     num     Event counter (0-30) to read\n  \\return                 Event count\n*/\n__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)\n{\n  return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];\n}\n\n/** \n  \\brief   Read counter overflow status\n  \\return  Counter overflow status bits for the following:\n          - event counters (0-30)\n          - cycle counter\n*/\n__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)\n{\n  return PMU->OVSSET;\t\n}\n\n/** \n  \\brief   Clear counter overflow status\n  \\param [in]     mask    Counter overflow status bits to clear\n  \\note    Clears overflow status bits for one or more of the following:\n           - event counters (0-30)\n           - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)\n{\n  PMU->OVSCLR = mask;\n}\n\n/** \n  \\brief   Enable counter overflow interrupt request \n  \\param [in]     mask    Counter overflow interrupt request bits to set\n  \\note    Sets overflow interrupt request bits for one or more of the following:\n           - event counters (0-30)\n           - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)\n{\n  PMU->INTENSET = mask;\n}\n\n/** \n  \\brief   Disable counter overflow interrupt request \n  \\param [in]     mask    Counter overflow interrupt request bits to clear\n  \\note    Clears overflow interrupt request bits for one or more of the following:\n           - event counters (0-30)\n           - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)\n{\n  PMU->INTENCLR = mask;\n}\n\n/** \n  \\brief   Software increment event counter \n  \\param [in]     mask    Counters to increment\n  \\note    Software increment bits for one or more event counters (0-30)\n*/\n__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)\n{\n  PMU->SWINC = mask;\n}\n\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Include/tz_context.h",
    "content": "/******************************************************************************\n * @file     tz_context.h\n * @brief    Context Management for Armv8-M TrustZone\n * @version  V1.0.1\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef TZ_CONTEXT_H\n#define TZ_CONTEXT_H\n \n#include <stdint.h>\n \n#ifndef TZ_MODULEID_T\n#define TZ_MODULEID_T\n/// \\details Data type that identifies secure software modules called by a process.\ntypedef uint32_t TZ_ModuleId_t;\n#endif\n \n/// \\details TZ Memory ID identifies an allocated memory slot.\ntypedef uint32_t TZ_MemoryId_t;\n  \n/// Initialize secure context memory system\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_InitContextSystem_S (void);\n \n/// Allocate context memory for calling secure software modules in TrustZone\n/// \\param[in]  module   identifies software modules called from non-secure mode\n/// \\return value != 0 id TrustZone memory slot identifier\n/// \\return value 0    no memory available or internal error\nTZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\n \n/// Free context memory that was previously allocated with \\ref TZ_AllocModuleContext_S\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\n \n/// Load secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\n \n/// Store secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\n \n#endif  // TZ_CONTEXT_H\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/main_s.c",
    "content": "/******************************************************************************\n * @file     main_s.c\n * @brief    Code template for secure main function\n * @version  V1.1.1\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2013-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Use CMSE intrinsics */\n#include <arm_cmse.h>\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n/* TZ_START_NS: Start address of non-secure application */\n#ifndef TZ_START_NS\n#define TZ_START_NS (0x200000U)\n#endif\n\n/* typedef for non-secure callback functions */\ntypedef void (*funcptr_void)(void) __attribute__((cmse_nonsecure_call));\n\n/* Secure main() */\nint main(void) {\n    funcptr_void NonSecure_ResetHandler;\n\n    /* Add user setup code for secure part here*/\n\n    /* Set non-secure main stack (MSP_NS) */\n    __TZ_set_MSP_NS(*((uint32_t * )(TZ_START_NS)));\n\n    /* Get non-secure reset handler */\n    NonSecure_ResetHandler = (funcptr_void) (*((uint32_t * )((TZ_START_NS) + 4U)));\n\n    /* Start non-secure state software application */\n    NonSecure_ResetHandler();\n\n    /* Non-secure software does not return, this code is not executed */\n    while (1) {\n        __NOP();\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core/Template/ARMv8-M/tz_context.c",
    "content": "/******************************************************************************\n * @file     tz_context.c\n * @brief    Context Management for Armv8-M TrustZone - Sample implementation\n * @version  V1.1.1\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2016-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"tz_context.h\"\n\n/// Number of process slots (threads may call secure library code)\n#ifndef TZ_PROCESS_STACK_SLOTS\n#define TZ_PROCESS_STACK_SLOTS     8U\n#endif\n\n/// Stack size of the secure library code\n#ifndef TZ_PROCESS_STACK_SIZE\n#define TZ_PROCESS_STACK_SIZE      256U\n#endif\n\ntypedef struct {\n    uint32_t sp_top;      // stack space top\n    uint32_t sp_limit;    // stack space limit\n    uint32_t sp;          // current stack pointer\n} stack_info_t;\n\nstatic stack_info_t ProcessStackInfo[TZ_PROCESS_STACK_SLOTS];\nstatic uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE / 8U];\nstatic uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;\n\n\n/// Initialize secure context memory system\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_InitContextSystem_S(void) {\n    uint32_t n;\n\n    if (__get_IPSR() == 0U) {\n        return 0U;  // Thread Mode\n    }\n\n    for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {\n        ProcessStackInfo[n].sp = 0U;\n        ProcessStackInfo[n].sp_limit = (uint32_t) &ProcessStackMemory[n];\n        ProcessStackInfo[n].sp_top = (uint32_t) &ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;\n        *((uint32_t *) ProcessStackMemory[n]) = n + 1U;\n    }\n    *((uint32_t *) ProcessStackMemory[--n]) = 0xFFFFFFFFU;\n\n    ProcessStackFreeSlot = 0U;\n\n    // Default process stack pointer and stack limit\n    __set_PSPLIM((uint32_t) ProcessStackMemory);\n    __set_PSP((uint32_t) ProcessStackMemory);\n\n    // Privileged Thread Mode using PSP\n    __set_CONTROL(0x02U);\n\n    return 1U;    // Success\n}\n\n\n/// Allocate context memory for calling secure software modules in TrustZone\n/// \\param[in]  module   identifies software modules called from non-secure mode\n/// \\return value != 0 id TrustZone memory slot identifier\n/// \\return value 0    no memory available or internal error\n__attribute__((cmse_nonsecure_entry))\nTZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module) {\n    uint32_t slot;\n\n    (void) module; // Ignore (fixed Stack size)\n\n    if (__get_IPSR() == 0U) {\n        return 0U;  // Thread Mode\n    }\n\n    if (ProcessStackFreeSlot == 0xFFFFFFFFU) {\n        return 0U;  // No slot available\n    }\n\n    slot = ProcessStackFreeSlot;\n    ProcessStackFreeSlot = *((uint32_t *) ProcessStackMemory[slot]);\n\n    ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;\n\n    return (slot + 1U);\n}\n\n\n/// Free context memory that was previously allocated with \\ref TZ_AllocModuleContext_S\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id) {\n    uint32_t slot;\n\n    if (__get_IPSR() == 0U) {\n        return 0U;  // Thread Mode\n    }\n\n    if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {\n        return 0U;  // Invalid ID\n    }\n\n    slot = id - 1U;\n\n    if (ProcessStackInfo[slot].sp == 0U) {\n        return 0U;  // Inactive slot\n    }\n    ProcessStackInfo[slot].sp = 0U;\n\n    *((uint32_t *) ProcessStackMemory[slot]) = ProcessStackFreeSlot;\n    ProcessStackFreeSlot = slot;\n\n    return 1U;    // Success\n}\n\n\n/// Load secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_LoadContext_S(TZ_MemoryId_t id) {\n    uint32_t slot;\n\n    if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {\n        return 0U;  // Thread Mode or using Main Stack for threads\n    }\n\n    if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {\n        return 0U;  // Invalid ID\n    }\n\n    slot = id - 1U;\n\n    if (ProcessStackInfo[slot].sp == 0U) {\n        return 0U;  // Inactive slot\n    }\n\n    // Setup process stack pointer and stack limit\n    __set_PSPLIM(ProcessStackInfo[slot].sp_limit);\n    __set_PSP(ProcessStackInfo[slot].sp);\n\n    return 1U;    // Success\n}\n\n\n/// Store secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_StoreContext_S(TZ_MemoryId_t id) {\n    uint32_t slot;\n    uint32_t sp;\n\n    if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {\n        return 0U;  // Thread Mode or using Main Stack for threads\n    }\n\n    if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {\n        return 0U;  // Invalid ID\n    }\n\n    slot = id - 1U;\n\n    if (ProcessStackInfo[slot].sp == 0U) {\n        return 0U;  // Inactive slot\n    }\n\n    sp = __get_PSP();\n    if ((sp < ProcessStackInfo[slot].sp_limit) ||\n        (sp > ProcessStackInfo[slot].sp_top)) {\n        return 0U;  // SP out of range\n    }\n    ProcessStackInfo[slot].sp = sp;\n\n    // Default process stack pointer and stack limit\n    __set_PSPLIM((uint32_t) ProcessStackMemory);\n    __set_PSP((uint32_t) ProcessStackMemory);\n\n    return 1U;    // Success\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Framework.h",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_Framework.h \n *      Purpose:      Framework header\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#ifndef __FRAMEWORK_H__\n#define __FRAMEWORK_H__\n\n#include \"CV_Typedefs.h\"\n#include \"CV_Report.h\"\n\n/*-----------------------------------------------------------------------------\n * Test framework global definitions\n *----------------------------------------------------------------------------*/\n\n/* Test case definition macro                                                 */\n#define TCD(x, y) {x, #x, y}\n\n/* Test case description structure                                            */\ntypedef struct __TestCase {\n  void (*TestFunc)(void);             /* Test function                        */\n  const char *TFName;                 /* Test function name string            */\n  BOOL en;                            /* Test function enabled                */\n} TEST_CASE;\n\n/* Test suite description structure                                           */\ntypedef struct __TestSuite {\n  const char *FileName;               /* Test module file name                */\n  const char *Date;                   /* Compilation date                     */\n  const char *Time;                   /* Compilation time                     */\n  const char *ReportTitle;            /* Title or name of module under test   */\n  void (*Init)(void);                 /* Init function callback               */\n  \n  uint32_t TCBaseNum;                 /* Base number for test case numbering  */\n  TEST_CASE *TC;                      /* Array of test cases                  */\n  uint32_t NumOfTC;                   /* Number of test cases (sz of TC array)*/\n\n} TEST_SUITE;\n\n/* Defined in user test module                                                */\nextern TEST_SUITE ts;\n\n#endif /* __FRAMEWORK_H__ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Report.h",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_Report.h \n *      Purpose:      Report statistics and layout header\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#ifndef __REPORT_H__\n#define __REPORT_H__\n\n#include \"CV_Config.h\"\n#include \"CV_Typedefs.h\"\n\n/*-----------------------------------------------------------------------------\n * Test report global definitions\n *----------------------------------------------------------------------------*/\n \n#define REP_TC_FAIL 0\n#define REP_TC_WARN 1\n#define REP_TC_PASS 2\n#define REP_TC_NOEX 3\n\n/* Test case result definition */\ntypedef enum {\n  PASSED = 0,\n  WARNING,\n  FAILED,\n  NOT_EXECUTED\n} TC_RES;\n\n/* Assertion result info */\ntypedef struct {\n  const char    *module;                  /* Module name                        */\n  uint32_t       line;                    /* Assertion line                     */\n} AS_INFO;\n\n/* Test case callback interface definition */\ntypedef struct {\n  BOOL (* Result) (TC_RES res);\n  BOOL (* Dbgi)   (TC_RES res, const char *fn, uint32_t ln, char *desc);\n} TC_ITF;\n\n/* Assert interface to the report */\nextern TC_ITF tcitf;\n\n/* Assertion result buffer */\ntypedef struct {\nAS_INFO passed[BUFFER_ASSERTIONS];  \nAS_INFO failed[BUFFER_ASSERTIONS];  \nAS_INFO warnings[BUFFER_ASSERTIONS];  \n} AS_T_INFO;\n\n/* Assertion statistics */\ntypedef struct {\n  uint32_t passed;           /* Total assertions passed                  */\n  uint32_t failed;           /* Total assertions failed                  */\n  uint32_t warnings;         /* Total assertions warnings                */\n  AS_T_INFO info;            /* Detailed assertion info                  */\n} AS_STAT;\n\n/* Test global statistics */\ntypedef struct {\n  uint32_t  tests;           /* Total test cases count                   */\n  uint32_t  executed;        /* Total test cases executed                */\n  uint32_t  passed;          /* Total test cases passed                  */\n  uint32_t  failed;          /* Total test cases failed                  */\n  uint32_t  warnings;        /* Total test cases warnings                */\n  AS_STAT   assertions;      /* Total assertions statistics              */\n} TEST_REPORT;\n\n/* Test report interface */\ntypedef struct {\n  BOOL (* Init)     (void);\n  BOOL (* Open)     (const char *title, const char *date, const char *time, const char *fn);\n  BOOL (* Close)    (void);  \n  BOOL (* Open_TC)  (uint32_t num, const char *fn);\n  BOOL (* Close_TC) (void);\n} REPORT_ITF;\n\n/* Test report statistics */\nextern TEST_REPORT  test_report;\n\n/* Test report interface */\nextern REPORT_ITF   ritf;\n\n/* Assertions and test results */\nextern TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc);\nextern TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond);\n\n#endif /* __REPORT_H__ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Include/CV_Typedefs.h",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_Typedefs.h\n *      Purpose:      Test framework filetypes and structures description\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#ifndef __TYPEDEFS_H__\n#define __TYPEDEFS_H__\n\n#include <stdint.h>\n#include <stdarg.h>\n#include <string.h>\n#include <stdio.h>\n\ntypedef unsigned int    BOOL;\n\n#ifndef __TRUE\n #define __TRUE         1\n#endif\n#ifndef __FALSE\n #define __FALSE        0\n#endif\n\n#ifndef ENABLED\n #define ENABLED        1\n#endif\n#ifndef DISABLED\n #define DISABLED       0\n#endif\n\n#ifndef NULL\n #ifdef __cplusplus              // EC++\n  #define NULL          0\n #else\n  #define NULL          ((void *) 0)\n #endif\n#endif\n\n#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0]))\n\n#if defined( __GNUC__ ) || defined ( __clang__ )\nstatic const int PATH_DELIMITER = '/';\n#else\nstatic const int PATH_DELIMITER = '\\\\';\n#endif\n\n//lint -emacro(9016,__FILENAME__) allow pointer arithmetic for truncating filename\n//lint -emacro(613,__FILENAME__) null pointer is checked\n#define __FILENAME__ ((strrchr(__FILE__, PATH_DELIMITER) != NULL) ? (strrchr(__FILE__, PATH_DELIMITER) + 1) : __FILE__)\n\n/* Assertions and test results */\n#define SET_RESULT(res, desc) (void)__set_result(__FILENAME__, __LINE__, (res), (desc));\n\n//lint -emacro(9031,ASSERT_TRUE) allow boolean condition as parameter\n//lint -emacro(613,ASSERT_TRUE) null pointer is checked\n#define ASSERT_TRUE(cond) (void)__assert_true (__FILENAME__, __LINE__, (cond) ? 1U : 0U)\n\n#endif /* __TYPEDEFS_H__ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Include/cmsis_cv.h",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         cmsis_cv.h\n *      Purpose:      cmsis_cv header\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2021 Arm Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#ifndef __CMSIS_CV_H\n#define __CMSIS_CV_H\n\n#include <stdint.h>\n#include \"CV_Config.h\"\n\n/* Expansion macro used to create CMSIS Driver references */\n#define EXPAND_SYMBOL(name, port) name##port\n#define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port)\n\n// Simulator counter\n#ifndef HW_PRESENT\nextern uint32_t SIM_CYCCNT;\n#endif\n\n// SVC interrupt callback\nextern void (*TST_IRQHandler)(void);\n\n// Test main function\nextern void cmsis_cv (void);\nextern void cmsis_cv_abort (const char *fn, uint32_t ln, char *desc);\n\n// Test cases\nextern void TC_CoreInstr_NOP (void);\nextern void TC_CoreInstr_SEV (void);\nextern void TC_CoreInstr_BKPT (void);\nextern void TC_CoreInstr_ISB (void);\nextern void TC_CoreInstr_DSB (void);\nextern void TC_CoreInstr_DMB (void);\nextern void TC_CoreInstr_WFI (void);\nextern void TC_CoreInstr_WFE (void);\nextern void TC_CoreInstr_REV (void);\nextern void TC_CoreInstr_REV16 (void);\nextern void TC_CoreInstr_REVSH (void);\nextern void TC_CoreInstr_ROR (void);\nextern void TC_CoreInstr_RBIT (void);\nextern void TC_CoreInstr_CLZ (void);\nextern void TC_CoreInstr_SSAT (void);\nextern void TC_CoreInstr_USAT (void);\nextern void TC_CoreInstr_RRX (void);\nextern void TC_CoreInstr_LoadStoreExclusive (void);\nextern void TC_CoreInstr_LoadStoreUnpriv (void);\nextern void TC_CoreInstr_LoadStoreAcquire (void);\nextern void TC_CoreInstr_LoadStoreAcquireExclusive (void);\nextern void TC_CoreInstr_UnalignedUint16 (void);\nextern void TC_CoreInstr_UnalignedUint32 (void);\n\nextern void TC_CoreSimd_SatAddSub (void);\nextern void TC_CoreSimd_ParSat16 (void);\nextern void TC_CoreSimd_PackUnpack (void);\nextern void TC_CoreSimd_ParSel (void);\nextern void TC_CoreSimd_ParAddSub8 (void);\nextern void TC_CoreSimd_AbsDif8 (void);\nextern void TC_CoreSimd_ParAddSub16 (void);\nextern void TC_CoreSimd_ParMul16 (void);\nextern void TC_CoreSimd_Pack16 (void);\nextern void TC_CoreSimd_MulAcc32 (void);\n\n#if defined(__CORTEX_M)\n  extern void TC_CoreFunc_EnDisIRQ (void);\n  extern void TC_CoreFunc_IRQPrio (void);\n  extern void TC_CoreFunc_EncDecIRQPrio (void);\n  extern void TC_CoreFunc_IRQVect (void);\n  extern void TC_CoreFunc_Control (void);\n  extern void TC_CoreFunc_IPSR (void);\n  extern void TC_CoreFunc_APSR (void);\n  extern void TC_CoreFunc_PSP (void);\n  extern void TC_CoreFunc_MSP (void);\n  extern void TC_CoreFunc_PSPLIM (void);\n  extern void TC_CoreFunc_PSPLIM_NS (void);\n  extern void TC_CoreFunc_MSPLIM (void);\n  extern void TC_CoreFunc_MSPLIM_NS (void);\n  extern void TC_CoreFunc_PRIMASK (void);\n  extern void TC_CoreFunc_FAULTMASK (void);\n  extern void TC_CoreFunc_BASEPRI (void);\n  extern void TC_CoreFunc_FPUType (void);\n  extern void TC_CoreFunc_FPSCR (void);\n#elif defined(__CORTEX_A)\n  extern void TC_CoreAFunc_IRQ (void);\n  extern void TC_CoreAFunc_FaultIRQ (void);\n  extern void TC_CoreAFunc_FPSCR (void);\n  extern void TC_CoreAFunc_CPSR (void);\n  extern void TC_CoreAFunc_Mode (void);\n  extern void TC_CoreAFunc_SP (void);\n  extern void TC_CoreAFunc_SP_usr (void);\n  extern void TC_CoreAFunc_FPEXC (void);\n  extern void TC_CoreAFunc_ACTLR (void);\n  extern void TC_CoreAFunc_CPACR (void);\n  extern void TC_CoreAFunc_DFSR (void);\n  extern void TC_CoreAFunc_IFSR (void);\n  extern void TC_CoreAFunc_ISR (void);\n  extern void TC_CoreAFunc_CBAR (void);\n  extern void TC_CoreAFunc_TTBR0 (void);\n  extern void TC_CoreAFunc_DACR (void);\n  extern void TC_CoreAFunc_SCTLR (void);\n  extern void TC_CoreAFunc_ACTRL (void);\n  extern void TC_CoreAFunc_MPIDR (void);\n  extern void TC_CoreAFunc_VBAR (void);\n  extern void TC_CoreAFunc_MVBAR (void);\n  extern void TC_CoreAFunc_FPU_Enable (void);\n#endif\n\n#if defined(__CORTEX_M)\nextern void TC_MPU_SetClear (void);\nextern void TC_MPU_Load (void);\n#endif\n\n#if defined(__CORTEX_A)\nextern void TC_GenTimer_CNTFRQ (void);\nextern void TC_GenTimer_CNTP_TVAL (void);\nextern void TC_GenTimer_CNTP_CTL (void);\nextern void TC_GenTimer_CNTPCT(void);\nextern void TC_GenTimer_CNTP_CVAL(void);\n#endif\n\n#if defined(__CORTEX_M)\nextern void TC_CML1Cache_EnDisableICache(void);\nextern void TC_CML1Cache_EnDisableDCache(void);\nextern void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void);\n#elif defined(__CORTEX_A)\nextern void TC_CAL1Cache_EnDisable(void);\nextern void TC_CAL1Cache_EnDisableBTAC(void);\nextern void TC_CAL1Cache_log2_up(void);\nextern void TC_CAL1Cache_InvalidateDCacheAll(void);\nextern void TC_CAL1Cache_CleanDCacheAll(void);\nextern void TC_CAL1Cache_CleanInvalidateDCacheAll(void);\n#endif\n\n#endif /* __CMSIS_CV_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/LICENSE.txt",
    "content": "                                 Apache License\n                           Version 2.0, January 2004\n                        http://www.apache.org/licenses/\n\n   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION\n\n   1. Definitions.\n\n      \"License\" shall mean the terms and conditions for use, reproduction,\n      and distribution as defined by Sections 1 through 9 of this document.\n\n      \"Licensor\" shall mean the copyright owner or entity authorized by\n      the copyright owner that is granting the License.\n\n      \"Legal Entity\" shall mean the union of the acting entity and all\n      other entities that control, are controlled by, or are under common\n      control with that entity. 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The text should be enclosed in the appropriate\n      comment syntax for the file format. We also recommend that a\n      file or class name and description of purpose be included on the\n      same \"printed page\" as the copyright notice for easier\n      identification within third-party archives.\n\n   Copyright {yyyy} {name of copyright owner}\n\n   Licensed under the Apache License, Version 2.0 (the \"License\");\n   you may not use this file except in compliance with the License.\n   You may obtain a copy of the License at\n\n       http://www.apache.org/licenses/LICENSE-2.0\n\n   Unless required by applicable law or agreed to in writing, software\n   distributed under the License is distributed on an \"AS IS\" BASIS,\n   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n   See the License for the specific language governing permissions and\n   limitations under the License.\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/App.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: App\n  # name: CMSIS-Core_Validation (Bootloader)\n  description: Validation of CMSIS-Core implementation (Bootloader part)\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  groups:\n    - group: Source Files\n      files:\n        - file: ./bootloader.c\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Bootloader_Cortex-M/bootloader.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        15. October 2016\n * $Revision:    1.1.0\n *\n * Project:      TrustZone for ARMv8-M\n * Title:        Code template for secure main function\n *\n *---------------------------------------------------------------------------*/\n \n#include <stdio.h>\n#include <stdlib.h>\n\n/* Use CMSE intrinsics */\n#include <arm_cmse.h>\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n \n/* TZ_START_NS: Start address of non-secure application */\n#ifndef TZ_START_NS\n#define TZ_START_NS (0x200000U)\n#endif\n\n#if 1\n/* Dummy Non-secure callable (entry) function */\n__attribute__((cmse_nonsecure_entry)) int validationDummy(int x) { \n  return x; \n}\n#endif\n \n/* typedef for non-secure callback functions */\ntypedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));\n\n/* Secure main() */\nint main(void) {\n  funcptr_void NonSecure_ResetHandler;\n \n  /* Add user setup code for secure part here*/\n \n  /* Set non-secure main stack (MSP_NS) */\n  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));\n \n  /* Get non-secure reset handler */\n  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));\n \n  /* Start non-secure state software application */\n  NonSecure_ResetHandler();\n \n  /* Non-secure software does not return, this code is not executed */\n  while (1) {\n    __NOP();\n  }\n}\n\n#if defined(__CORTEX_M)\n__NO_RETURN\nextern void HardFault_Handler(void);\nvoid HardFault_Handler(void) {\n  printf(\"Bootloader HardFault!\\n\");\n  #ifdef __MICROLIB\n  for(;;) {}\n  #else\n  exit(1);\n  #endif\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/App.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: App\n  # name: CMSIS-Core_Validation\n  description: Validation of CMSIS-Core implementation\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  define:\n    - PRINT_XML_REPORT: 1\n\n  add-path:\n    - ../../../Include\n    - ../../../Source/ConfigA\n\n  misc:\n    - for-compiler: AC6\n      C-CPP:\n      - -Wno-declaration-after-statement\n      - -Wno-covered-switch-default\n    - for-compiler: GCC\n      C-CPP:\n      - -Wno-declaration-after-statement\n      - -Wno-covered-switch-default\n\n  groups:\n    - group: Documentation\n      files:\n        - file: ../../../README.md\n\n    - group: Source Files\n      files:\n        - file: ./main.c\n\n    - group: CMSIS-Core_Validation\n      files:\n        - file: ../../../Source/cmsis_cv.c\n        - file: ../../../Source/CV_CoreAFunc.c\n        - file: ../../../Source/CV_CoreInstr.c\n        - file: ../../../Source/CV_CAL1Cache.c\n#        - file: ../../../Source/ConfigA/mmu.c\n\n    - group: Validation Framework\n      files:\n        - file: ../../../Source/CV_Framework.c\n        - file: ../../../Source/CV_Report.c\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-A/main.c",
    "content": "/*\n * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n\n#include \"RTE_Components.h\"\n#include  CMSIS_device_header\n\n#ifdef RTE_Compiler_EventRecorder\n#include \"EventRecorder.h\"\n#endif\n\n#include \"cmsis_cv.h\"\n#include \"CV_Report.h\"\n\n//lint -e970 allow using int for main\n\nint main (void)\n{\n\n  // System Initialization\n  SystemCoreClockUpdate();\n\n#ifdef RTE_Compiler_EventRecorder\n  // Initialize and start Event Recorder\n  (void)EventRecorderInitialize(EventRecordError, 1U);\n  (void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU);\n#endif\n\n  cmsis_cv();\n\n  #ifdef __MICROLIB\n  for(;;) {}\n  #else\n  exit(0);\n  #endif\n}\n\n#if defined(__CORTEX_A)\n#include \"irq_ctrl.h\"\n\n#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \\\n    (defined ( __GNUC__ ))\n  #define __IRQ __attribute__((interrupt(\"IRQ\")))\n#elif defined ( __CC_ARM )\n  #define __IRQ __irq\n#elif defined ( __ICCARM__ )\n  #define __IRQ __irq __arm\n#else\n  #error \"Unsupported compiler!\"\n#endif\n\n\n__IRQ\nvoid IRQ_Handler(void);\n__IRQ\nvoid IRQ_Handler(void) {\n  const IRQn_ID_t irqn = IRQ_GetActiveIRQ();\n  IRQHandler_t const handler = IRQ_GetHandler(irqn);\n  if (handler != NULL) {\n    __enable_irq();\n    handler();\n    __disable_irq();\n  }\n  IRQ_EndOfInterrupt(irqn);\n}\n\n__IRQ __NO_RETURN\nvoid Undef_Handler (void);\n__IRQ __NO_RETURN\nvoid Undef_Handler (void) {\n  cmsis_cv_abort(__FILENAME__, __LINE__, \"Undefined Instruction!\");\n  exit(0);\n}\n\n__IRQ\nvoid SVC_Handler   (void);\n__IRQ\nvoid SVC_Handler   (void) {\n}\n\n__IRQ __NO_RETURN\nvoid PAbt_Handler  (void);\n__IRQ __NO_RETURN\nvoid PAbt_Handler  (void) {\n  cmsis_cv_abort(__FILENAME__, __LINE__, \"Prefetch Abort!\");\n  exit(0);\n}\n\n__IRQ __NO_RETURN\nvoid DAbt_Handler  (void);\n__IRQ __NO_RETURN\nvoid DAbt_Handler  (void) {\n  cmsis_cv_abort(__FILENAME__, __LINE__, \"Data Abort!\");\n  exit(0);\n}\n\n__IRQ\nvoid FIQ_Handler   (void);\n__IRQ\nvoid FIQ_Handler   (void) {\n}\n#endif\n\n#if defined(__CORTEX_M)\n__NO_RETURN\nvoid HardFault_Handler(void);\n__NO_RETURN\nvoid HardFault_Handler(void) {\n  cmsis_cv_abort(__FILENAME__, __LINE__, \"HardFault!\");\n  #ifdef __MICROLIB\n  for(;;) {}\n  #else\n  exit(0);\n  #endif\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/App.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: App\n  # name: CMSIS-Core_Validation\n  description: Validation of CMSIS-Core implementation\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  define:\n    - PRINT_XML_REPORT: 1\n\n  add-path:\n    - ../../../Include\n    - ../../../Source/Config\n\n  misc:\n    - for-compiler: AC6\n      C-CPP:\n      - -Wno-declaration-after-statement\n      - -Wno-covered-switch-default\n    - for-compiler: GCC\n      C-CPP:\n      - -Wno-declaration-after-statement\n      - -Wno-covered-switch-default\n\n  groups:\n    - group: Documentation\n      files:\n        - file: ../../../README.md\n\n    - group: Source Files\n      files:\n        - file: ./main.c\n\n    - group: CMSIS-Core_Validation\n      files:\n        - file: ../../../Source/cmsis_cv.c\n        - file: ../../../Source/CV_CoreFunc.c\n        - file: ../../../Source/CV_CoreInstr.c\n        - file: ../../../Source/CV_CoreSimd.c\n        - file: ../../../Source/CV_CML1Cache.c\n        - file: ../../../Source/CV_MPU_ARMv7.c\n          for-context:\n            - +CM0\n            - +CM0plus\n            - +CM3\n            - +CM4\n            - +CM4FP\n            - +CM7\n            - +CM7SP\n            - +CM7DP\n        - file: ../../../Source/CV_MPU_ARMv8.c\n          for-context:\n            - +CM23\n            - +CM23S\n            - +CM23NS\n            - +CM33\n            - +CM33S\n            - +CM33NS\n            - +CM35P\n            - +CM35PS\n            - +CM35PNS\n            - +CM55S\n            - +CM55NS\n            - +CM85S\n            - +CM85NS\n\n    - group: Validation Framework\n      files:\n        - file: ../../../Source/CV_Framework.c\n        - file: ../../../Source/CV_Report.c\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/App/Validation_Cortex-M/main.c",
    "content": "/*\n * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n\n#include \"RTE_Components.h\"\n#include  CMSIS_device_header\n\n#ifdef RTE_Compiler_EventRecorder\n#include \"EventRecorder.h\"\n#endif\n\n#include \"cmsis_cv.h\"\n#include \"CV_Report.h\"\n\n//lint -e970 allow using int for main\n\n\n#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n  #include <arm_cmse.h>\n\n  /* Dummy Non-secure callable (entry) function */\n  __attribute__((cmse_nonsecure_entry)) int validationDummy(int x) {\n    return x;\n  }\n#endif\n\nint main (void)\n{\n\n  // System Initialization\n  SystemCoreClockUpdate();\n\n#ifdef RTE_Compiler_EventRecorder\n  // Initialize and start Event Recorder\n  (void)EventRecorderInitialize(EventRecordError, 1U);\n  (void)EventRecorderEnable(EventRecordAll, 0xFEU, 0xFEU);\n#endif\n\n  cmsis_cv();\n\n  #ifdef __MICROLIB\n  for(;;) {}\n  #else\n  exit(0);\n  #endif\n}\n\n#if defined(__CORTEX_A)\n#include \"irq_ctrl.h\"\n\n#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \\\n    (defined ( __GNUC__ ))\n  #define __IRQ __attribute__((interrupt(\"IRQ\")))\n#elif defined ( __CC_ARM )\n  #define __IRQ __irq\n#elif defined ( __ICCARM__ )\n  #define __IRQ __irq __arm\n#else\n  #error \"Unsupported compiler!\"\n#endif\n\n\n__IRQ\nvoid IRQ_Handler(void);\n__IRQ\nvoid IRQ_Handler(void) {\n  const IRQn_ID_t irqn = IRQ_GetActiveIRQ();\n  IRQHandler_t const handler = IRQ_GetHandler(irqn);\n  if (handler != NULL) {\n    __enable_irq();\n    handler();\n    __disable_irq();\n  }\n  IRQ_EndOfInterrupt(irqn);\n}\n\n__IRQ __NO_RETURN\nvoid Undef_Handler (void);\n__IRQ __NO_RETURN\nvoid Undef_Handler (void) {\n  cmsis_cv_abort(__FILENAME__, __LINE__, \"Undefined Instruction!\");\n  exit(0);\n}\n\n__IRQ\nvoid SVC_Handler   (void);\n__IRQ\nvoid SVC_Handler   (void) {\n}\n\n__IRQ __NO_RETURN\nvoid PAbt_Handler  (void);\n__IRQ __NO_RETURN\nvoid PAbt_Handler  (void) {\n  cmsis_cv_abort(__FILENAME__, __LINE__, \"Prefetch Abort!\");\n  exit(0);\n}\n\n__IRQ __NO_RETURN\nvoid DAbt_Handler  (void);\n__IRQ __NO_RETURN\nvoid DAbt_Handler  (void) {\n  cmsis_cv_abort(__FILENAME__, __LINE__, \"Data Abort!\");\n  exit(0);\n}\n\n__IRQ\nvoid FIQ_Handler   (void);\n__IRQ\nvoid FIQ_Handler   (void) {\n}\n#endif\n\n#if defined(__CORTEX_M)\n__NO_RETURN\nvoid HardFault_Handler(void);\n__NO_RETURN\nvoid HardFault_Handler(void) {\n  cmsis_cv_abort(__FILENAME__, __LINE__, \"HardFault!\");\n  #ifdef __MICROLIB\n  for(;;) {}\n  #else\n  exit(0);\n  #endif\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf",
    "content": "\n/*-Memory Regions-*/\ndefine symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;\ndefine symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;\ndefine symbol __ICFEDIT_region_IROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;\ndefine symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;\ndefine symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IRAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_TTB_start__   = 0x80500000;\ndefine symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;\n\n/*-Sizes-*/\ndefine symbol __ICFEDIT_size_cstack__        = 0x1000;\ndefine symbol __ICFEDIT_size_irqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_fiqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_svcstack__      = 0x100;\ndefine symbol __ICFEDIT_size_abtstack__      = 0x100;\ndefine symbol __ICFEDIT_size_undstack__      = 0x100;\ndefine symbol __ICFEDIT_size_heap__          = 0x8000;\ndefine symbol __ICFEDIT_size_ttb__           = 0x4000;\n\ndefine memory mem with size = 4G;\ndefine region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]\n                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];\ndefine region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]\n                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];\ndefine region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]\n                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]\n                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];\ndefine region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];\n\ndefine block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };\ndefine block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };\ndefine block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };\ndefine block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };\ndefine block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };\ndefine block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };\ndefine block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };\ndefine block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };\n\ndo not initialize  { section .noinit };\n\ninitialize by copy { readwrite };\nif (isdefinedsymbol(__USE_DLIB_PERTHREAD))\n{\n  // Required in a multi-threaded application\n  initialize by copy with packing = none { section __DLIB_PERTHREAD };\n}\n\nplace at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };\nplace in IROM_region  { readonly };\nplace in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };\nplace in TTB_region   { block TTB };"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.icf.base@1.0.0",
    "content": "\n/*-Memory Regions-*/\ndefine symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;\ndefine symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;\ndefine symbol __ICFEDIT_region_IROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;\ndefine symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;\ndefine symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IRAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_TTB_start__   = 0x80500000;\ndefine symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;\n\n/*-Sizes-*/\ndefine symbol __ICFEDIT_size_cstack__        = 0x1000;\ndefine symbol __ICFEDIT_size_irqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_fiqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_svcstack__      = 0x100;\ndefine symbol __ICFEDIT_size_abtstack__      = 0x100;\ndefine symbol __ICFEDIT_size_undstack__      = 0x100;\ndefine symbol __ICFEDIT_size_heap__          = 0x8000;\ndefine symbol __ICFEDIT_size_ttb__           = 0x4000;\n\ndefine memory mem with size = 4G;\ndefine region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]\n                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];\ndefine region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]\n                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];\ndefine region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]\n                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]\n                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];\ndefine region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];\n\ndefine block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };\ndefine block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };\ndefine block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };\ndefine block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };\ndefine block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };\ndefine block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };\ndefine block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };\ndefine block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };\n\ndo not initialize  { section .noinit };\n\ninitialize by copy { readwrite };\nif (isdefinedsymbol(__USE_DLIB_PERTHREAD))\n{\n  // Required in a multi-threaded application\n  initialize by copy with packing = none { section __DLIB_PERTHREAD };\n}\n\nplace at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };\nplace in IROM_region  { readonly };\nplace in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };\nplace in TTB_region   { block TTB };"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.ld",
    "content": "#include \"mem_ARMCA5.h\" \n\nMEMORY\n{\n  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE \n  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n\n        Image$$VECTORS$$Base = .;\n        * (RESET)\n        KEEP(*(.isr_vector))\n        Image$$VECTORS$$Limit = .;\n\n        *(SVC_TABLE)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        /* .ctors */\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        /* .dtors */\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        Image$$RO_DATA$$Base = .;\n        *(.rodata*)\n        Image$$RO_DATA$$Limit = .;\n\n        KEEP(*(.eh_frame*))\n    } > ROM\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > ROM\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > ROM\n    __exidx_end = .;\n\n\n    .copy.table :\n    {\n        . = ALIGN(4);\n        __copy_table_start__ = .;\n        LONG (__etext)\n        LONG (__data_start__)\n        LONG (__data_end__ - __data_start__)\n        __copy_table_end__ = .;\n    } > ROM\n\n    .zero.table :\n    {\n        . = ALIGN(4);\n        __zero_table_start__ = .;\n        LONG (__bss_start__)\n        LONG (__bss_end__ - __bss_start__)\n        __zero_table_end__ = .;\n    } > ROM\n\n    __etext = .;\n        \n    .ttb :\n    {\n        Image$$TTB$$ZI$$Base = .;\n        . += __TTB_SIZE;\n        Image$$TTB$$ZI$$Limit = .;\n    } > L_TTB\n\n    .data :\n    {\n        Image$$RW_DATA$$Base = .;\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n        Image$$RW_DATA$$Limit = .;\n\n        . = ALIGN(4);\n        /* preinit data */\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        /* init data */\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        /* finit data */\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        /* All data end */\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss ALIGN(0x400):\n    {\n        Image$$ZI_DATA$$Base = .;\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$ZI_DATA$$Limit = .;\n        __end__ = .;\n        end = __end__;\n    } > RAM AT > RAM\n\n#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    \n    .heap (NOLOAD):\n    {\n        . = ALIGN(8);\n        Image$$HEAP$$ZI$$Base = .;\n        . += __HEAP_SIZE;\n        Image$$HEAP$$ZI$$Limit = .;\n        __HeapLimit = .;\n    } > RAM  \n#endif\n\n    .stack (NOLOAD):\n    {\n        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;\n        . = ALIGN(8);\n        \n        __StackTop = .;\n        Image$$SYS_STACK$$ZI$$Base = .;\n        . += __STACK_SIZE;\n        Image$$SYS_STACK$$ZI$$Limit = .;\n        __stack = .;\n\n        Image$$FIQ_STACK$$ZI$$Base = .;\n        . += __FIQ_STACK_SIZE;\n        Image$$FIQ_STACK$$ZI$$Limit = .;\n\n        Image$$IRQ_STACK$$ZI$$Base = .;\n        . += __IRQ_STACK_SIZE;\n        Image$$IRQ_STACK$$ZI$$Limit = .;\n\n        Image$$SVC_STACK$$ZI$$Base = .;\n        . += __SVC_STACK_SIZE;\n        Image$$SVC_STACK$$ZI$$Limit = .;\n\n        Image$$ABT_STACK$$ZI$$Base = .;\n        . += __ABT_STACK_SIZE;\n        Image$$ABT_STACK$$ZI$$Limit = .;\n\n        Image$$UND_STACK$$ZI$$Base = .;\n        . += __UND_STACK_SIZE;\n        Image$$UND_STACK$$ZI$$Limit = .;\n        \n    } > RAM\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/ARMCA5.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA5.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mem_ARMCA5.h",
    "content": "/**************************************************************************//**\n * @file     mem_ARMCA5.h\n * @brief    Memory base and size definitions (used in scatter file)\n * @version  V1.1.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __MEM_ARMCA5_H\n#define __MEM_ARMCA5_H\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap size definition\n *----------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n/*--------------------- ROM Configuration ------------------------------------\n//\n// <h> ROM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>\n//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE       0x80000000\n#define __ROM_SIZE       0x00200000\n\n/*--------------------- RAM Configuration -----------------------------------\n// <h> RAM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>\n//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n//   <h> Data Sections\n//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//   </h>\n//   <h> Stack / Heap Configuration\n//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <h> Exceptional Modes\n//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     </h>\n//   </h>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE       0x80200000\n#define __RAM_SIZE       0x00200000\n\n#define __RW_DATA_SIZE   0x00100000\n#define __ZI_DATA_SIZE   0x000F0000\n\n#define __STACK_SIZE     0x00001000\n#define __HEAP_SIZE      0x00008000\n\n#define __UND_STACK_SIZE 0x00000100\n#define __ABT_STACK_SIZE 0x00000100\n#define __SVC_STACK_SIZE 0x00000100\n#define __IRQ_STACK_SIZE 0x00000100\n#define __FIQ_STACK_SIZE 0x00000100\n\n/*----------------------------------------------------------------------------*/\n\n/*--------------------- TTB Configuration ------------------------------------\n//\n// <h> TTB Configuration\n//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned\n//   <i> The TLB L2 entries are placed after the L1 in the MMU config\n//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>\n//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __TTB_BASE       0x80500000\n#define __TTB_SIZE       0x00005000\n\n#endif /* __MEM_ARMCA5_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mmu_ARMCA5.c",
    "content": "/**************************************************************************//**\n * @file     mmu_ARMCA5.c\n * @brief    MMU Configuration for ARM Cortex-A5 Device Series\n * @version  V1.2.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map\n\n                                                     Memory Type\n0xffffffff |--------------------------|             ------------\n           |       FLAG SYNC          |             Device Memory\n0xfffff000 |--------------------------|             ------------\n           |         Fault            |                Fault\n0xfff00000 |--------------------------|             ------------\n           |                          |                Normal\n           |                          |\n           |      Daughterboard       |\n           |         memory           |\n           |                          |\n0x80505000 |--------------------------|             ------------\n           |TTB (L2 Sync Flags   ) 4k |                Normal\n0x80504C00 |--------------------------|             ------------\n           |TTB (L2 Peripherals-B) 16k|                Normal\n0x80504800 |--------------------------|             ------------\n           |TTB (L2 Peripherals-A) 16k|                Normal\n0x80504400 |--------------------------|             ------------\n           |TTB (L2 Priv Periphs)  4k |                Normal\n0x80504000 |--------------------------|             ------------\n           |    TTB (L1 Descriptors)  |                Normal\n0x80500000 |--------------------------|             ------------\n           |          Stack           |                Normal\n           |--------------------------|             ------------\n           |          Heap            |                Normal\n0x80400000 |--------------------------|             ------------\n           |         ZI Data          |                Normal\n0x80300000 |--------------------------|             ------------\n           |         RW Data          |                Normal\n0x80200000 |--------------------------|             ------------\n           |         RO Data          |                Normal\n           |--------------------------|             ------------\n           |         RO Code          |              USH Normal\n0x80000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |      HSB AXI buses       |\n0x40000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x2c002000 |--------------------------|             ------------\n           |     Private Address      |            Device Memory\n0x2c000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x20000000 |--------------------------|             ------------\n           |       Peripherals        |           Device Memory RW/RO\n           |                          |              & Fault\n0x00000000 |--------------------------|\n*/\n\n// L1 Cache info and restrictions about architecture of the caches (CCSIR register):\n// Write-Through support *not* available\n// Write-Back support available.\n// Read allocation support available.\n// Write allocation support available.\n\n//Note: You should use the Shareable attribute carefully.\n//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.\n//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.\n//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.\n\n//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.\n//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.\n//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.\n\n\n//Following MMU configuration is expected\n//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)\n//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)\n//Domain 0 is always the Client domain\n//Descriptors should place all memory in domain 0\n\n#include \"ARMCA5.h\"\n#include \"mem_ARMCA5.h\"\n\n// TTB base address\n#define TTB_BASE ((uint32_t*)__TTB_BASE)\n\n// L2 table pointers\n//----------------------------------------\n#define TTB_L1_SIZE                    (0x00004000)                        // The L1 translation table divides the full 4GB address space of a 32-bit core\n                                                                           // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.\n                                                                           // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.\n\n#define PRIVATE_TABLE_L2_BASE_4k       (__TTB_BASE + TTB_L1_SIZE)          // Map 4k Private Address space\n#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400)  // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF\n#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800)  // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF\n#define SYNC_FLAGS_TABLE_L2_BASE_4k    (__TTB_BASE + TTB_L1_SIZE + 0xC00)  // Map 4k Flag synchronization\n\n//--------------------- PERIPHERALS -------------------\n#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)\n#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)\n\n//--------------------- SYNC FLAGS --------------------\n#define FLAG_SYNC     0xFFFFF000\n#define F_SYNC_BASE   0xFFF00000  //1M aligned\n\nstatic uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0\nstatic uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable\nstatic uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable\nstatic uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable\n\n/* Define global descriptors */\nstatic uint32_t Page_L1_4k  = 0x0;  //generic\nstatic uint32_t Page_L1_64k = 0x0;  //generic\nstatic uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0\nstatic uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0\n\nvoid MMU_CreateTranslationTable(void)\n{\n    mmu_region_attributes_Type region;\n\n    //Create 4GB of faulting entries\n    MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);\n\n    /*\n     * Generate descriptors. Refer to core_ca.h to get information about attributes\n     *\n     */\n    //Create descriptors for Vectors, RO, RW, ZI sections\n    section_normal(Sect_Normal, region);\n    section_normal_cod(Sect_Normal_Cod, region);\n    section_normal_ro(Sect_Normal_RO, region);\n    section_normal_rw(Sect_Normal_RW, region);\n    //Create descriptors for peripherals\n    section_device_ro(Sect_Device_RO, region);\n    section_device_rw(Sect_Device_RW, region);\n    //Create descriptors for 64k pages\n    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);\n    //Create descriptors for 4k pages\n    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);\n\n\n    /*\n     *  Define MMU flat-map regions and attributes\n     *\n     */\n\n    //Define Image\n    MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections\n    MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);  // multiple of 1MB sections\n\n    //--------------------- PERIPHERALS -------------------\n    MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE0   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE1   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A5_MP_SRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A5_MP_VRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);\n    MMU_TTSection (TTB_BASE, VE_A5_MP_USB_BASE      , 16, Sect_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define private address space entry.\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n    // Define L2CC entry.  Uncomment if PL310 is present\n    //    MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)\n    MMU_TTPage4k (TTB_BASE, F_SYNC_BASE             , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define synchronization space entry.\n    MMU_TTPage4k (TTB_BASE, FLAG_SYNC               ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    /* Set location of level 1 page table\n    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)\n    ; 13:7  - 0x0\n    ; 6     - IRGN[0] 0x1  (Inner WB WA)\n    ; 5     - NOS     0x0  (Non-shared)\n    ; 4:3   - RGN     0x01 (Outer WB WA)\n    ; 2     - IMP     0x0  (Implementation Defined)\n    ; 1     - S       0x0  (Non-shared)\n    ; 0     - IRGN[1] 0x0  (Inner WB WA) */\n    __set_TTBR0(__TTB_BASE | 0x48);\n    __ISB();\n\n    /* Set up domain access control register\n    ; We set domain 0 to Client and all other domains to No Access.\n    ; All translation table entries specify domain 0 */\n    __set_DACR(1);\n    __ISB();\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA5.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA5.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void) __attribute__ ((noreturn));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  \"LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \\n\"\n#elif defined ( __GNUC__ )\n  \"LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \\n\"\n#else\n  #error Unknown compiler.\n#endif\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  \"BL     __main                                   \\n\"\n#elif defined ( __GNUC__ )\n  \"BL     _start                                   \\n\"\n#else\n  #error Unknown compiler.\n#endif\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.c.base@1.0.1",
    "content": "/******************************************************************************\n * @file     startup_ARMCA5.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA5.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void) __attribute__ ((noreturn));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n  \"LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \\n\"\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n  \"BL     __main                                   \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.s\n * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series\n * @version  V1.00\n * @date     01 Nov 2017\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n  MODULE  ?startup_ARMCA5\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n  PUBLIC  Reset_Handler\n  PUBWEAK Undef_Handler\n  PUBWEAK SVC_Handler\n  PUBWEAK PAbt_Handler\n  PUBWEAK DAbt_Handler\n  PUBWEAK IRQ_Handler\n  PUBWEAK FIQ_Handler\n\n  SECTION SVC_STACK:DATA:NOROOT(3)\n  SECTION IRQ_STACK:DATA:NOROOT(3)\n  SECTION FIQ_STACK:DATA:NOROOT(3)\n  SECTION ABT_STACK:DATA:NOROOT(3)\n  SECTION UND_STACK:DATA:NOROOT(3)\n  SECTION USR_STACK:DATA:NOROOT(3)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n\n  section RESET:CODE:NOROOT(2)\n  PUBLIC  Vectors\n\nVectors:  \n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n\n\n  section .text:CODE:NOROOT(4)\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n  *----------------------------------------------------------------------------*/\n  EXTERN  SystemInit\n  EXTERN  __iar_program_start\n\nReset_Handler:  \n\n  // Mask interrupts\n  CPSID   if\n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5\n  ANDS    R0, R0, #3\ngoToSleep:\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exception mode\n  CPS    #0x11\n  LDR    SP, =SFE(FIQ_STACK)\n  CPS    #0x12\n  LDR    SP, =SFE(IRQ_STACK)\n  CPS    #0x13\n  LDR    SP, =SFE(SVC_STACK)\n  CPS    #0x17\n  LDR    SP, =SFE(ABT_STACK)\n  CPS    #0x1B\n  LDR    SP, =SFE(UND_STACK)\n  CPS    #0x1F\n  LDR    SP, =SFE(USR_STACK)\n\n  // Call SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __iar_program_start\n  BL     __iar_program_start\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nUndef_Handler:\nSVC_Handler:\nPAbt_Handler:\nDAbt_Handler:\nIRQ_Handler:\nFIQ_Handler:\nDefault_Handler:\n  B .\n\n  END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/startup_ARMCA5.s.base@1.0.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.s\n * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series\n * @version  V1.00\n * @date     01 Nov 2017\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n  MODULE  ?startup_ARMCA5\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n  PUBLIC  Reset_Handler\n  PUBWEAK Undef_Handler\n  PUBWEAK SVC_Handler\n  PUBWEAK PAbt_Handler\n  PUBWEAK DAbt_Handler\n  PUBWEAK IRQ_Handler\n  PUBWEAK FIQ_Handler\n\n  SECTION SVC_STACK:DATA:NOROOT(3)\n  SECTION IRQ_STACK:DATA:NOROOT(3)\n  SECTION FIQ_STACK:DATA:NOROOT(3)\n  SECTION ABT_STACK:DATA:NOROOT(3)\n  SECTION UND_STACK:DATA:NOROOT(3)\n  SECTION USR_STACK:DATA:NOROOT(3)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n\n  section RESET:CODE:NOROOT(2)\n  PUBLIC  Vectors\n\nVectors:  \n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n\n\n  section .text:CODE:NOROOT(4)\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n  *----------------------------------------------------------------------------*/\n  EXTERN  SystemInit\n  EXTERN  __iar_program_start\n\nReset_Handler:  \n\n  // Mask interrupts\n  CPSID   if\n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5\n  ANDS    R0, R0, #3\ngoToSleep:\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exception mode\n  CPS    #0x11\n  LDR    SP, =SFE(FIQ_STACK)\n  CPS    #0x12\n  LDR    SP, =SFE(IRQ_STACK)\n  CPS    #0x13\n  LDR    SP, =SFE(SVC_STACK)\n  CPS    #0x17\n  LDR    SP, =SFE(ABT_STACK)\n  CPS    #0x1B\n  LDR    SP, =SFE(UND_STACK)\n  CPS    #0x1F\n  LDR    SP, =SFE(USR_STACK)\n\n  // Call SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __iar_program_start\n  BL     __iar_program_start\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nUndef_Handler:\nSVC_Handler:\nPAbt_Handler:\nDAbt_Handler:\nIRQ_Handler:\nFIQ_Handler:\nDefault_Handler:\n  B .\n\n  END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c",
    "content": "/******************************************************************************\n * @file     system_ARMCA5.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series\n * @version  V1.0.1\n * @date     13. February 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"irq_ctrl.h\"\n\n#define  SYSTEM_CLOCK  12000000U\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System Initialization\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* do not use global variables because this function is called before\n   reaching pre-main. RW section may be overwritten afterwards.          */\n\n  // Invalidate entire Unified TLB\n  __set_TLBIALL(0);\n\n  // Invalidate entire branch predictor array\n  __set_BPIALL(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate instruction cache and flush branch target cache\n  __set_ICIALLU(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate data cache\n  L1C_InvalidateDCacheAll();\n\n#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\n  // Enable FPU\n  __FPU_Enable();\n#endif\n\n  // Create Translation Table\n  MMU_CreateTranslationTable();\n\n  // Enable MMU\n  MMU_Enable();\n\n  // Enable Caches\n  L1C_EnableCaches();\n  L1C_EnableBTAC();\n\n#if (__L2C_PRESENT == 1) \n  // Enable GIC\n  L2C_Enable();\n#endif\n\n  // IRQ Initialize\n  IRQ_Initialize();\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.c.base@1.0.1",
    "content": "/******************************************************************************\n * @file     system_ARMCA5.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series\n * @version  V1.0.1\n * @date     13. February 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"irq_ctrl.h\"\n\n#define  SYSTEM_CLOCK  12000000U\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System Initialization\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* do not use global variables because this function is called before\n   reaching pre-main. RW section may be overwritten afterwards.          */\n\n  // Invalidate entire Unified TLB\n  __set_TLBIALL(0);\n\n  // Invalidate entire branch predictor array\n  __set_BPIALL(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate instruction cache and flush branch target cache\n  __set_ICIALLU(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate data cache\n  L1C_InvalidateDCacheAll();\n\n#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\n  // Enable FPU\n  __FPU_Enable();\n#endif\n\n  // Create Translation Table\n  MMU_CreateTranslationTable();\n\n  // Enable MMU\n  MMU_Enable();\n\n  // Enable Caches\n  L1C_EnableCaches();\n  L1C_EnableBTAC();\n\n#if (__L2C_PRESENT == 1) \n  // Enable GIC\n  L2C_Enable();\n#endif\n\n  // IRQ Initialize\n  IRQ_Initialize();\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h",
    "content": "/******************************************************************************\n * @file     system_ARMCA5.h\n * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __SYSTEM_ARMCA5_H\n#define __SYSTEM_ARMCA5_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SYSTEM_ARMCA5_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/system_ARMCA5.h.base@1.0.0",
    "content": "/******************************************************************************\n * @file     system_ARMCA5.h\n * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __SYSTEM_ARMCA5_H\n#define __SYSTEM_ARMCA5_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SYSTEM_ARMCA5_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup\n    - component: Device:IRQ Controller:GIC\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA5/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nmotherboard.vis.disable_visualisation=1               # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncluster.cpu0.vfp-present=1                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support \ncluster.cpu0.ase-present=0                            # (bool  , init-time) default = '1'      : Set whether model has NEON support\ncluster.cpu0.semihosting-enable=1                     # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false\ncluster.cpu0.semihosting-hlt-enable=0                 # (bool  , init-time) default = '0'      : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true\ncluster.cpu0.semihosting-ARM_SVC=0x123456             # (int   , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF]\ncluster.cpu0.semihosting-Thumb_SVC=0xAB               # (int   , init-time) default = '0xAB'   : Thumb SVC number for semihosting : [0x0..0xFF]\ncluster.cpu0.semihosting-ARM_HLT=0xF000               # (int   , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF]\ncluster.cpu0.semihosting-Thumb_HLT=0x3C               # (int   , init-time) default = '0x3C'   : Thumb HLT number for semihosting : [0x0..0x3F]\ncluster.cpu0.semihosting-cmd_line=\"\"                  # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncluster.cpu0.semihosting-heap_base=0x0                # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-heap_limit=0x0               # (int   , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-stack_base=0x0               # (int   , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-stack_limit=0x0              # (int   , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-cwd=\"\"                       # (string, init-time) default = ''       : Base directory for semihosting file access.\ncluster.dcache-state_modelled=1                       # (bool  , run-time ) default = '0'      : Set whether D-cache has stateful implementation\ncluster.icache-state_modelled=1                       # (bool  , run-time ) default = '0'      : Set whether I-cache has stateful implementation\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf",
    "content": "\n/*-Memory Regions-*/\ndefine symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;\ndefine symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;\ndefine symbol __ICFEDIT_region_IROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;\ndefine symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;\ndefine symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IRAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_TTB_start__   = 0x80500000;\ndefine symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;\n\n/*-Sizes-*/\ndefine symbol __ICFEDIT_size_cstack__        = 0x1000;\ndefine symbol __ICFEDIT_size_irqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_fiqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_svcstack__      = 0x100;\ndefine symbol __ICFEDIT_size_abtstack__      = 0x100;\ndefine symbol __ICFEDIT_size_undstack__      = 0x100;\ndefine symbol __ICFEDIT_size_heap__          = 0x8000;\ndefine symbol __ICFEDIT_size_ttb__           = 0x4000;\n\ndefine memory mem with size = 4G;\ndefine region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]\n                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];\ndefine region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]\n                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];\ndefine region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]\n                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]\n                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];\ndefine region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];\n\ndefine block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };\ndefine block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };\ndefine block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };\ndefine block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };\ndefine block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };\ndefine block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };\ndefine block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };\ndefine block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };\n\ndo not initialize  { section .noinit };\n\ninitialize by copy { readwrite };\nif (isdefinedsymbol(__USE_DLIB_PERTHREAD))\n{\n  // Required in a multi-threaded application\n  initialize by copy with packing = none { section __DLIB_PERTHREAD };\n}\n\nplace at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };\nplace in IROM_region  { readonly };\nplace in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };\nplace in TTB_region   { block TTB };"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.icf.base@1.0.0",
    "content": "\n/*-Memory Regions-*/\ndefine symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;\ndefine symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;\ndefine symbol __ICFEDIT_region_IROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;\ndefine symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;\ndefine symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IRAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_TTB_start__   = 0x80500000;\ndefine symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;\n\n/*-Sizes-*/\ndefine symbol __ICFEDIT_size_cstack__        = 0x1000;\ndefine symbol __ICFEDIT_size_irqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_fiqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_svcstack__      = 0x100;\ndefine symbol __ICFEDIT_size_abtstack__      = 0x100;\ndefine symbol __ICFEDIT_size_undstack__      = 0x100;\ndefine symbol __ICFEDIT_size_heap__          = 0x8000;\ndefine symbol __ICFEDIT_size_ttb__           = 0x4000;\n\ndefine memory mem with size = 4G;\ndefine region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]\n                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];\ndefine region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]\n                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];\ndefine region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]\n                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]\n                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];\ndefine region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];\n\ndefine block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };\ndefine block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };\ndefine block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };\ndefine block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };\ndefine block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };\ndefine block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };\ndefine block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };\ndefine block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };\n\ndo not initialize  { section .noinit };\n\ninitialize by copy { readwrite };\nif (isdefinedsymbol(__USE_DLIB_PERTHREAD))\n{\n  // Required in a multi-threaded application\n  initialize by copy with packing = none { section __DLIB_PERTHREAD };\n}\n\nplace at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };\nplace in IROM_region  { readonly };\nplace in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };\nplace in TTB_region   { block TTB };"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.ld",
    "content": "#include \"mem_ARMCA7.h\" \n\nMEMORY\n{\n  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE \n  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n\n        Image$$VECTORS$$Base = .;\n        * (RESET)\n        KEEP(*(.isr_vector))\n        Image$$VECTORS$$Limit = .;\n\n        *(SVC_TABLE)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        /* .ctors */\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        /* .dtors */\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        Image$$RO_DATA$$Base = .;\n        *(.rodata*)\n        Image$$RO_DATA$$Limit = .;\n\n        KEEP(*(.eh_frame*))\n    } > ROM\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > ROM\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > ROM\n    __exidx_end = .;\n\n\n    .copy.table :\n    {\n        . = ALIGN(4);\n        __copy_table_start__ = .;\n        LONG (__etext)\n        LONG (__data_start__)\n        LONG (__data_end__ - __data_start__)\n        __copy_table_end__ = .;\n    } > ROM\n\n    .zero.table :\n    {\n        . = ALIGN(4);\n        __zero_table_start__ = .;\n        LONG (__bss_start__)\n        LONG (__bss_end__ - __bss_start__)\n        __zero_table_end__ = .;\n    } > ROM\n\n    __etext = .;\n        \n    .ttb :\n    {\n        Image$$TTB$$ZI$$Base = .;\n        . += __TTB_SIZE;\n        Image$$TTB$$ZI$$Limit = .;\n    } > L_TTB\n\n    .data :\n    {\n        Image$$RW_DATA$$Base = .;\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n        Image$$RW_DATA$$Limit = .;\n\n        . = ALIGN(4);\n        /* preinit data */\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        /* init data */\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        /* finit data */\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        /* All data end */\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss ALIGN(0x400):\n    {\n        Image$$ZI_DATA$$Base = .;\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$ZI_DATA$$Limit = .;\n        __end__ = .;\n        end = __end__;\n    } > RAM AT > RAM\n\n#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    \n    .heap (NOLOAD):\n    {\n        . = ALIGN(8);\n        Image$$HEAP$$ZI$$Base = .;\n        . += __HEAP_SIZE;\n        Image$$HEAP$$ZI$$Limit = .;\n        __HeapLimit = .;\n    } > RAM  \n#endif\n\n    .stack (NOLOAD):\n    {\n        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;\n        . = ALIGN(8);\n        \n        __StackTop = .;\n        Image$$SYS_STACK$$ZI$$Base = .;\n        . += __STACK_SIZE;\n        Image$$SYS_STACK$$ZI$$Limit = .;\n        __stack = .;\n\n        Image$$FIQ_STACK$$ZI$$Base = .;\n        . += __FIQ_STACK_SIZE;\n        Image$$FIQ_STACK$$ZI$$Limit = .;\n\n        Image$$IRQ_STACK$$ZI$$Base = .;\n        . += __IRQ_STACK_SIZE;\n        Image$$IRQ_STACK$$ZI$$Limit = .;\n\n        Image$$SVC_STACK$$ZI$$Base = .;\n        . += __SVC_STACK_SIZE;\n        Image$$SVC_STACK$$ZI$$Limit = .;\n\n        Image$$ABT_STACK$$ZI$$Base = .;\n        . += __ABT_STACK_SIZE;\n        Image$$ABT_STACK$$ZI$$Limit = .;\n\n        Image$$UND_STACK$$ZI$$Base = .;\n        . += __UND_STACK_SIZE;\n        Image$$UND_STACK$$ZI$$Limit = .;\n        \n    } > RAM\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/ARMCA7.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA7.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mem_ARMCA7.h",
    "content": "/**************************************************************************//**\n * @file     mem_ARMCA7.h\n * @brief    Memory base and size definitions (used in scatter file)\n * @version  V1.1.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __MEM_ARMCA7_H\n#define __MEM_ARMCA7_H\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap size definition\n *----------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n/*--------------------- ROM Configuration ------------------------------------\n//\n// <h> ROM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>\n//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE       0x80000000\n#define __ROM_SIZE       0x00200000\n\n/*--------------------- RAM Configuration -----------------------------------\n// <h> RAM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>\n//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n//   <h> Data Sections\n//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//   </h>\n//   <h> Stack / Heap Configuration\n//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <h> Exceptional Modes\n//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     </h>\n//   </h>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE       0x80200000\n#define __RAM_SIZE       0x00200000\n\n#define __RW_DATA_SIZE   0x00100000\n#define __ZI_DATA_SIZE   0x000F0000\n\n#define __STACK_SIZE     0x00001000\n#define __HEAP_SIZE      0x00008000\n\n#define __UND_STACK_SIZE 0x00000100\n#define __ABT_STACK_SIZE 0x00000100\n#define __SVC_STACK_SIZE 0x00000100\n#define __IRQ_STACK_SIZE 0x00000100\n#define __FIQ_STACK_SIZE 0x00000100\n\n/*----------------------------------------------------------------------------*/\n\n/*--------------------- TTB Configuration ------------------------------------\n//\n// <h> TTB Configuration\n//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned\n//   <i> The TLB L2 entries are placed after the L1 in the MMU config\n//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>\n//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __TTB_BASE       0x80500000\n#define __TTB_SIZE       0x00005000\n\n#endif /* __MEM_ARMCA7_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mmu_ARMCA7.c",
    "content": "/**************************************************************************//**\n * @file     mmu_ARMCA7.c\n * @brief    MMU Configuration for Arm Cortex-A7 Device Series\n * @version  V1.2.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map\n\n                                                     Memory Type\n0xffffffff |--------------------------|             ------------\n           |       FLAG SYNC          |             Device Memory\n0xfffff000 |--------------------------|             ------------\n           |         Fault            |                Fault\n0xfff00000 |--------------------------|             ------------\n           |                          |                Normal\n           |                          |\n           |      Daughterboard       |\n           |         memory           |\n           |                          |\n0x80505000 |--------------------------|             ------------\n           |TTB (L2 Sync Flags   ) 4k |                Normal\n0x80504C00 |--------------------------|             ------------\n           |TTB (L2 Peripherals-B) 16k|                Normal\n0x80504800 |--------------------------|             ------------\n           |TTB (L2 Peripherals-A) 16k|                Normal\n0x80504400 |--------------------------|             ------------\n           |TTB (L2 Priv Periphs)  4k |                Normal\n0x80504000 |--------------------------|             ------------\n           |    TTB (L1 Descriptors)  |                Normal\n0x80500000 |--------------------------|             ------------\n           |          Stack           |                Normal\n           |--------------------------|             ------------\n           |          Heap            |                Normal\n0x80400000 |--------------------------|             ------------\n           |         ZI Data          |                Normal\n0x80300000 |--------------------------|             ------------\n           |         RW Data          |                Normal\n0x80200000 |--------------------------|             ------------\n           |         RO Data          |                Normal\n           |--------------------------|             ------------\n           |         RO Code          |              USH Normal\n0x80000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |      HSB AXI buses       |\n0x40000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x2c002000 |--------------------------|             ------------\n           |     Private Address      |            Device Memory\n0x2c000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x20000000 |--------------------------|             ------------\n           |       Peripherals        |           Device Memory RW/RO\n           |                          |              & Fault\n0x00000000 |--------------------------|\n*/\n\n// L1 Cache info and restrictions about architecture of the caches (CCSIR register):\n// Write-Through support *not* available\n// Write-Back support available.\n// Read allocation support available.\n// Write allocation support available.\n\n//Note: You should use the Shareable attribute carefully.\n//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.\n//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.\n//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.\n\n//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.\n//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.\n//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.\n\n\n//Following MMU configuration is expected\n//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)\n//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)\n//Domain 0 is always the Client domain\n//Descriptors should place all memory in domain 0\n\n#include \"ARMCA7.h\"\n#include \"mem_ARMCA7.h\"\n\n// TTB base address\n#define TTB_BASE ((uint32_t*)__TTB_BASE)\n\n// L2 table pointers\n//----------------------------------------\n#define TTB_L1_SIZE                    (0x00004000)                        // The L1 translation table divides the full 4GB address space of a 32-bit core\n                                                                           // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.\n                                                                           // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.\n\n#define PRIVATE_TABLE_L2_BASE_4k       (__TTB_BASE + TTB_L1_SIZE)          // Map 4k Private Address space\n#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400)  // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF\n#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800)  // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF\n#define SYNC_FLAGS_TABLE_L2_BASE_4k    (__TTB_BASE + TTB_L1_SIZE + 0xC00)  // Map 4k Flag synchronization\n\n//--------------------- PERIPHERALS -------------------\n#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)\n#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)\n\n//--------------------- SYNC FLAGS --------------------\n#define FLAG_SYNC     0xFFFFF000\n#define F_SYNC_BASE   0xFFF00000  //1M aligned\n\nstatic uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0\nstatic uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable\nstatic uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable\nstatic uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable\n\n/* Define global descriptors */\nstatic uint32_t Page_L1_4k  = 0x0;  //generic\nstatic uint32_t Page_L1_64k = 0x0;  //generic\nstatic uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0\nstatic uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0\n\nvoid MMU_CreateTranslationTable(void)\n{\n    mmu_region_attributes_Type region;\n\n    //Create 4GB of faulting entries\n    MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);\n\n    /*\n     * Generate descriptors. Refer to core_ca.h to get information about attributes\n     *\n     */\n    //Create descriptors for Vectors, RO, RW, ZI sections\n    section_normal(Sect_Normal, region);\n    section_normal_cod(Sect_Normal_Cod, region);\n    section_normal_ro(Sect_Normal_RO, region);\n    section_normal_rw(Sect_Normal_RW, region);\n    //Create descriptors for peripherals\n    section_device_ro(Sect_Device_RO, region);\n    section_device_rw(Sect_Device_RW, region);\n    //Create descriptors for 64k pages\n    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);\n    //Create descriptors for 4k pages\n    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);\n\n\n    /*\n     *  Define MMU flat-map regions and attributes\n     *\n     */\n\n    //Define Image\n    MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections\n    MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);  // multiple of 1MB sections\n\n    //--------------------- PERIPHERALS -------------------\n    MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW);\n    MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE      , 16, Sect_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define private address space entry.\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n    // Define L2CC entry.  Uncomment if PL310 is present\n    //    MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)\n    MMU_TTPage4k (TTB_BASE, F_SYNC_BASE             , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define synchronization space entry.\n    MMU_TTPage4k (TTB_BASE, FLAG_SYNC               ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    /* Set location of level 1 page table\n    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)\n    ; 13:7  - 0x0\n    ; 6     - IRGN[0] 0x1  (Inner WB WA)\n    ; 5     - NOS     0x0  (Non-shared)\n    ; 4:3   - RGN     0x01 (Outer WB WA)\n    ; 2     - IMP     0x0  (Implementation Defined)\n    ; 1     - S       0x0  (Non-shared)\n    ; 0     - IRGN[1] 0x0  (Inner WB WA) */\n    __set_TTBR0(__TTB_BASE | 0x48);\n    __ISB();\n\n    /* Set up domain access control register\n    ; We set domain 0 to Client and all other domains to No Access.\n    ; All translation table entries specify domain 0 */\n    __set_DACR(1);\n    __ISB();\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA7.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA7.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void) __attribute__ ((noreturn));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  \"LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \\n\"\n#elif defined ( __GNUC__ )\n  \"LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \\n\"\n#else\n  #error Unknown compiler.\n#endif\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  \"BL     __main                                   \\n\"\n#elif defined ( __GNUC__ )\n  \"BL     _start                                   \\n\"\n#else\n  #error Unknown compiler.\n#endif\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.c.base@1.0.1",
    "content": "/******************************************************************************\n * @file     startup_ARMCA7.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA7.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void) __attribute__ ((noreturn));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n  \"LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \\n\"\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n  \"BL     __main                                   \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s",
    "content": "/******************************************************************************\n * @file     startup_ARMCA7.s\n * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series\n * @version  V1.00\n * @date     01 Nov 2017\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n  MODULE  ?startup_ARMCA7\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n  PUBLIC  Reset_Handler\n  PUBWEAK Undef_Handler\n  PUBWEAK SVC_Handler\n  PUBWEAK PAbt_Handler\n  PUBWEAK DAbt_Handler\n  PUBWEAK IRQ_Handler\n  PUBWEAK FIQ_Handler\n\n  SECTION SVC_STACK:DATA:NOROOT(3)\n  SECTION IRQ_STACK:DATA:NOROOT(3)\n  SECTION FIQ_STACK:DATA:NOROOT(3)\n  SECTION ABT_STACK:DATA:NOROOT(3)\n  SECTION UND_STACK:DATA:NOROOT(3)\n  SECTION USR_STACK:DATA:NOROOT(3)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n\n  section RESET:CODE:NOROOT(2)\n  PUBLIC  Vectors\n\nVectors:\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n\n\n  section .text:CODE:NOROOT(4)\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n  *----------------------------------------------------------------------------*/\n  EXTERN  SystemInit\n  EXTERN  __iar_program_start\n\nReset_Handler:  \n\n  // Mask interrupts\n  CPSID   if\n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5\n  ANDS    R0, R0, #3\ngoToSleep:\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exception mode\n  CPS    #0x11\n  LDR    SP, =SFE(FIQ_STACK)\n  CPS    #0x12\n  LDR    SP, =SFE(IRQ_STACK)\n  CPS    #0x13\n  LDR    SP, =SFE(SVC_STACK)\n  CPS    #0x17\n  LDR    SP, =SFE(ABT_STACK)\n  CPS    #0x1B\n  LDR    SP, =SFE(UND_STACK)\n  CPS    #0x1F\n  LDR    SP, =SFE(USR_STACK)\n\n  // Call SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __iar_program_start\n  BL     __iar_program_start\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nUndef_Handler:\nSVC_Handler:\nPAbt_Handler:\nDAbt_Handler:\nIRQ_Handler:\nFIQ_Handler:\nDefault_Handler:\n  B .\n\n  END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/startup_ARMCA7.s.base@1.0.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCA7.s\n * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series\n * @version  V1.00\n * @date     01 Nov 2017\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n  MODULE  ?startup_ARMCA7\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n  PUBLIC  Reset_Handler\n  PUBWEAK Undef_Handler\n  PUBWEAK SVC_Handler\n  PUBWEAK PAbt_Handler\n  PUBWEAK DAbt_Handler\n  PUBWEAK IRQ_Handler\n  PUBWEAK FIQ_Handler\n\n  SECTION SVC_STACK:DATA:NOROOT(3)\n  SECTION IRQ_STACK:DATA:NOROOT(3)\n  SECTION FIQ_STACK:DATA:NOROOT(3)\n  SECTION ABT_STACK:DATA:NOROOT(3)\n  SECTION UND_STACK:DATA:NOROOT(3)\n  SECTION USR_STACK:DATA:NOROOT(3)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n\n  section RESET:CODE:NOROOT(2)\n  PUBLIC  Vectors\n\nVectors:\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n\n\n  section .text:CODE:NOROOT(4)\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n  *----------------------------------------------------------------------------*/\n  EXTERN  SystemInit\n  EXTERN  __iar_program_start\n\nReset_Handler:  \n\n  // Mask interrupts\n  CPSID   if\n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5\n  ANDS    R0, R0, #3\ngoToSleep:\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exception mode\n  CPS    #0x11\n  LDR    SP, =SFE(FIQ_STACK)\n  CPS    #0x12\n  LDR    SP, =SFE(IRQ_STACK)\n  CPS    #0x13\n  LDR    SP, =SFE(SVC_STACK)\n  CPS    #0x17\n  LDR    SP, =SFE(ABT_STACK)\n  CPS    #0x1B\n  LDR    SP, =SFE(UND_STACK)\n  CPS    #0x1F\n  LDR    SP, =SFE(USR_STACK)\n\n  // Call SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __iar_program_start\n  BL     __iar_program_start\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nUndef_Handler:\nSVC_Handler:\nPAbt_Handler:\nDAbt_Handler:\nIRQ_Handler:\nFIQ_Handler:\nDefault_Handler:\n  B .\n\n  END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c",
    "content": "/******************************************************************************\n * @file     system_ARMCA7.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series\n * @version  V1.0.1\n * @date     13. February 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"irq_ctrl.h\"\n\n#define  SYSTEM_CLOCK  12000000U\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System Initialization\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* do not use global variables because this function is called before\n   reaching pre-main. RW section may be overwritten afterwards.          */\n\n  // Invalidate entire Unified TLB\n  __set_TLBIALL(0);\n\n  // Invalidate entire branch predictor array\n  __set_BPIALL(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate instruction cache and flush branch target cache\n  __set_ICIALLU(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate data cache\n  L1C_InvalidateDCacheAll();\n\n#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\n  // Enable FPU\n  __FPU_Enable();\n#endif\n\n  // Create Translation Table\n  MMU_CreateTranslationTable();\n\n  // Enable MMU\n  MMU_Enable();\n\n  // Enable Caches\n  L1C_EnableCaches();\n  L1C_EnableBTAC();\n\n#if (__L2C_PRESENT == 1) \n  // Enable GIC\n  L2C_Enable();\n#endif\n\n  // IRQ Initialize\n  IRQ_Initialize();\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.c.base@1.0.1",
    "content": "/******************************************************************************\n * @file     system_ARMCA7.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series\n * @version  V1.0.1\n * @date     13. February 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"irq_ctrl.h\"\n\n#define  SYSTEM_CLOCK  12000000U\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System Initialization\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* do not use global variables because this function is called before\n   reaching pre-main. RW section may be overwritten afterwards.          */\n\n  // Invalidate entire Unified TLB\n  __set_TLBIALL(0);\n\n  // Invalidate entire branch predictor array\n  __set_BPIALL(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate instruction cache and flush branch target cache\n  __set_ICIALLU(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate data cache\n  L1C_InvalidateDCacheAll();\n\n#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\n  // Enable FPU\n  __FPU_Enable();\n#endif\n\n  // Create Translation Table\n  MMU_CreateTranslationTable();\n\n  // Enable MMU\n  MMU_Enable();\n\n  // Enable Caches\n  L1C_EnableCaches();\n  L1C_EnableBTAC();\n\n#if (__L2C_PRESENT == 1) \n  // Enable GIC\n  L2C_Enable();\n#endif\n\n  // IRQ Initialize\n  IRQ_Initialize();\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h",
    "content": "/******************************************************************************\n * @file     system_ARMCA7.h\n * @brief    CMSIS Device System Header File for Arm Cortex-A7 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __SYSTEM_ARMCA7_H\n#define __SYSTEM_ARMCA7_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SYSTEM_ARMCA7_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/system_ARMCA7.h.base@1.0.0",
    "content": "/******************************************************************************\n * @file     system_ARMCA7.h\n * @brief    CMSIS Device System Header File for Arm Cortex-A7 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __SYSTEM_ARMCA7_H\n#define __SYSTEM_ARMCA7_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SYSTEM_ARMCA7_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup\n    - component: Device:IRQ Controller:GIC\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA7/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nmotherboard.vis.disable_visualisation=1               # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncluster.cpu0.vfp-present=1                            # (bool  , init-time) default = '1'      : Set whether CT model has been built with VFP support\ncluster.cpu0.ase-present=0                            # (bool  , init-time) default = '1'      : Set whether CT model has been built with NEON support\ncluster.cpu0.semihosting-enable=1                     # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false\ncluster.cpu0.semihosting-hlt-enable=0                 # (bool  , init-time) default = '0'      : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true\ncluster.cpu0.semihosting-ARM_SVC=0x123456             # (int   , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF]\ncluster.cpu0.semihosting-Thumb_SVC=0xAB               # (int   , init-time) default = '0xAB'   : Thumb SVC number for semihosting : [0x0..0xFF]\ncluster.cpu0.semihosting-ARM_HLT=0xF000               # (int   , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF]\ncluster.cpu0.semihosting-Thumb_HLT=0x3C               # (int   , init-time) default = '0x3C'   : Thumb HLT number for semihosting : [0x0..0x3F]\ncluster.cpu0.semihosting-cmd_line=\"\"                  # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncluster.cpu0.semihosting-heap_base=0x0                # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-heap_limit=0x0               # (int   , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-stack_base=0x0               # (int   , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-stack_limit=0x0              # (int   , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-cwd=\"\"                       # (string, init-time) default = ''       : Base directory for semihosting file access.\ncluster.l1_icache-state_modelled=1                    # (bool  , run-time ) default = '0'      : Set whether L1 I-cache has stateful implementation\ncluster.l1_dcache-state_modelled=1                    # (bool  , run-time ) default = '0'      : Set whether L1 D-cache has stateful implementation\ncluster.l2_cache-state_modelled=1                     # (bool  , run-time ) default = '0'      : Set whether L2 cache has stateful implementation\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf",
    "content": "\n/*-Memory Regions-*/\ndefine symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;\ndefine symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;\ndefine symbol __ICFEDIT_region_IROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;\ndefine symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;\ndefine symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IRAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_TTB_start__   = 0x80500000;\ndefine symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;\n\n/*-Sizes-*/\ndefine symbol __ICFEDIT_size_cstack__        = 0x1000;\ndefine symbol __ICFEDIT_size_irqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_fiqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_svcstack__      = 0x100;\ndefine symbol __ICFEDIT_size_abtstack__      = 0x100;\ndefine symbol __ICFEDIT_size_undstack__      = 0x100;\ndefine symbol __ICFEDIT_size_heap__          = 0x8000;\ndefine symbol __ICFEDIT_size_ttb__           = 0x4000;\n\ndefine memory mem with size = 4G;\ndefine region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]\n                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];\ndefine region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]\n                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];\ndefine region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]\n                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]\n                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];\ndefine region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];\n\ndefine block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };\ndefine block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };\ndefine block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };\ndefine block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };\ndefine block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };\ndefine block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };\ndefine block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };\ndefine block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };\n\ndo not initialize  { section .noinit };\n\ninitialize by copy { readwrite };\nif (isdefinedsymbol(__USE_DLIB_PERTHREAD))\n{\n  // Required in a multi-threaded application\n  initialize by copy with packing = none { section __DLIB_PERTHREAD };\n}\n\nplace at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };\nplace in IROM_region  { readonly };\nplace in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };\nplace in TTB_region   { block TTB };"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.icf.base@1.0.0",
    "content": "\n/*-Memory Regions-*/\ndefine symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;\ndefine symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;\ndefine symbol __ICFEDIT_region_IROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;\ndefine symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;\ndefine symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IRAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_TTB_start__   = 0x80500000;\ndefine symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;\n\n/*-Sizes-*/\ndefine symbol __ICFEDIT_size_cstack__        = 0x1000;\ndefine symbol __ICFEDIT_size_irqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_fiqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_svcstack__      = 0x100;\ndefine symbol __ICFEDIT_size_abtstack__      = 0x100;\ndefine symbol __ICFEDIT_size_undstack__      = 0x100;\ndefine symbol __ICFEDIT_size_heap__          = 0x8000;\ndefine symbol __ICFEDIT_size_ttb__           = 0x4000;\n\ndefine memory mem with size = 4G;\ndefine region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]\n                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];\ndefine region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]\n                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];\ndefine region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]\n                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]\n                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];\ndefine region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];\n\ndefine block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };\ndefine block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };\ndefine block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };\ndefine block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };\ndefine block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };\ndefine block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };\ndefine block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };\ndefine block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };\n\ndo not initialize  { section .noinit };\n\ninitialize by copy { readwrite };\nif (isdefinedsymbol(__USE_DLIB_PERTHREAD))\n{\n  // Required in a multi-threaded application\n  initialize by copy with packing = none { section __DLIB_PERTHREAD };\n}\n\nplace at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };\nplace in IROM_region  { readonly };\nplace in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };\nplace in TTB_region   { block TTB };"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.ld",
    "content": "#include \"mem_ARMCA9.h\" \n\nMEMORY\n{\n  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE \n  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n\n        Image$$VECTORS$$Base = .;\n        * (RESET)\n        KEEP(*(.isr_vector))\n        Image$$VECTORS$$Limit = .;\n\n        *(SVC_TABLE)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        /* .ctors */\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        /* .dtors */\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        Image$$RO_DATA$$Base = .;\n        *(.rodata*)\n        Image$$RO_DATA$$Limit = .;\n\n        KEEP(*(.eh_frame*))\n    } > ROM\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > ROM\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > ROM\n    __exidx_end = .;\n\n\n    .copy.table :\n    {\n        . = ALIGN(4);\n        __copy_table_start__ = .;\n        LONG (__etext)\n        LONG (__data_start__)\n        LONG (__data_end__ - __data_start__)\n        __copy_table_end__ = .;\n    } > ROM\n\n    .zero.table :\n    {\n        . = ALIGN(4);\n        __zero_table_start__ = .;\n        LONG (__bss_start__)\n        LONG (__bss_end__ - __bss_start__)\n        __zero_table_end__ = .;\n    } > ROM\n\n    __etext = .;\n        \n    .ttb :\n    {\n        Image$$TTB$$ZI$$Base = .;\n        . += __TTB_SIZE;\n        Image$$TTB$$ZI$$Limit = .;\n    } > L_TTB\n\n    .data :\n    {\n        Image$$RW_DATA$$Base = .;\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n        Image$$RW_DATA$$Limit = .;\n\n        . = ALIGN(4);\n        /* preinit data */\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        /* init data */\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        /* finit data */\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        /* All data end */\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss ALIGN(0x400):\n    {\n        Image$$ZI_DATA$$Base = .;\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$ZI_DATA$$Limit = .;\n        __end__ = .;\n        end = __end__;\n    } > RAM AT > RAM\n\n#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    \n    .heap (NOLOAD):\n    {\n        . = ALIGN(8);\n        Image$$HEAP$$ZI$$Base = .;\n        . += __HEAP_SIZE;\n        Image$$HEAP$$ZI$$Limit = .;\n        __HeapLimit = .;\n    } > RAM  \n#endif\n\n    .stack (NOLOAD):\n    {\n        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;\n        . = ALIGN(8);\n        \n        __StackTop = .;\n        Image$$SYS_STACK$$ZI$$Base = .;\n        . += __STACK_SIZE;\n        Image$$SYS_STACK$$ZI$$Limit = .;\n        __stack = .;\n\n        Image$$FIQ_STACK$$ZI$$Base = .;\n        . += __FIQ_STACK_SIZE;\n        Image$$FIQ_STACK$$ZI$$Limit = .;\n\n        Image$$IRQ_STACK$$ZI$$Base = .;\n        . += __IRQ_STACK_SIZE;\n        Image$$IRQ_STACK$$ZI$$Limit = .;\n\n        Image$$SVC_STACK$$ZI$$Base = .;\n        . += __SVC_STACK_SIZE;\n        Image$$SVC_STACK$$ZI$$Limit = .;\n\n        Image$$ABT_STACK$$ZI$$Base = .;\n        . += __ABT_STACK_SIZE;\n        Image$$ABT_STACK$$ZI$$Limit = .;\n\n        Image$$UND_STACK$$ZI$$Base = .;\n        . += __UND_STACK_SIZE;\n        Image$$UND_STACK$$ZI$$Limit = .;\n        \n    } > RAM\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/ARMCA9.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA9.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mem_ARMCA9.h",
    "content": "/**************************************************************************//**\n * @file     mem_ARMCA9.h\n * @brief    Memory base and size definitions (used in scatter file)\n * @version  V1.1.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __MEM_ARMCA9_H\n#define __MEM_ARMCA9_H\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap size definition\n *----------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n/*--------------------- ROM Configuration ------------------------------------\n//\n// <h> ROM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>\n//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE       0x80000000\n#define __ROM_SIZE       0x00200000\n\n/*--------------------- RAM Configuration -----------------------------------\n// <h> RAM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>\n//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n//   <h> Data Sections\n//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//   </h>\n//   <h> Stack / Heap Configuration\n//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <h> Exceptional Modes\n//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     </h>\n//   </h>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE       0x80200000\n#define __RAM_SIZE       0x00200000\n\n#define __RW_DATA_SIZE   0x00100000\n#define __ZI_DATA_SIZE   0x000F0000\n\n#define __STACK_SIZE     0x00001000\n#define __HEAP_SIZE      0x00008000\n\n#define __UND_STACK_SIZE 0x00000100\n#define __ABT_STACK_SIZE 0x00000100\n#define __SVC_STACK_SIZE 0x00000100\n#define __IRQ_STACK_SIZE 0x00000100\n#define __FIQ_STACK_SIZE 0x00000100\n\n/*----------------------------------------------------------------------------*/\n\n/*--------------------- TTB Configuration ------------------------------------\n//\n// <h> TTB Configuration\n//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned\n//   <i> The TLB L2 entries are placed after the L1 in the MMU config\n//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>\n//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __TTB_BASE       0x80500000\n#define __TTB_SIZE       0x00005000\n\n#endif /* __MEM_ARMCA9_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mmu_ARMCA9.c",
    "content": "/**************************************************************************//**\n * @file     mmu_ARMCA9.c\n * @brief    MMU Configuration for Arm Cortex-A9 Device Series\n * @version  V1.2.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map\n\n                                                     Memory Type\n0xffffffff |--------------------------|             ------------\n           |       FLAG SYNC          |             Device Memory\n0xfffff000 |--------------------------|             ------------\n           |         Fault            |                Fault\n0xfff00000 |--------------------------|             ------------\n           |                          |                Normal\n           |                          |\n           |      Daughterboard       |\n           |         memory           |\n           |                          |\n0x80505000 |--------------------------|             ------------\n           |TTB (L2 Sync Flags   ) 4k |                Normal\n0x80504C00 |--------------------------|             ------------\n           |TTB (L2 Peripherals-B) 16k|                Normal\n0x80504800 |--------------------------|             ------------\n           |TTB (L2 Peripherals-A) 16k|                Normal\n0x80504400 |--------------------------|             ------------\n           |TTB (L2 Priv Periphs)  4k |                Normal\n0x80504000 |--------------------------|             ------------\n           |    TTB (L1 Descriptors)  |                Normal\n0x80500000 |--------------------------|             ------------\n           |          Stack           |                Normal\n           |--------------------------|             ------------\n           |          Heap            |                Normal\n0x80400000 |--------------------------|             ------------\n           |         ZI Data          |                Normal\n0x80300000 |--------------------------|             ------------\n           |         RW Data          |                Normal\n0x80200000 |--------------------------|             ------------\n           |         RO Data          |                Normal\n           |--------------------------|             ------------\n           |         RO Code          |              USH Normal\n0x80000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |      HSB AXI buses       |\n0x40000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x2c002000 |--------------------------|             ------------\n           |     Private Address      |            Device Memory\n0x2c000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x20000000 |--------------------------|             ------------\n           |       Peripherals        |           Device Memory RW/RO\n           |                          |              & Fault\n0x00000000 |--------------------------|\n*/\n\n// L1 Cache info and restrictions about architecture of the caches (CCSIR register):\n// Write-Through support *not* available\n// Write-Back support available.\n// Read allocation support available.\n// Write allocation support available.\n\n//Note: You should use the Shareable attribute carefully.\n//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.\n//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.\n//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.\n\n//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.\n//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.\n//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.\n\n\n//Following MMU configuration is expected\n//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)\n//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)\n//Domain 0 is always the Client domain\n//Descriptors should place all memory in domain 0\n\n#include \"ARMCA9.h\"\n#include \"mem_ARMCA9.h\"\n\n// TTB base address\n#define TTB_BASE ((uint32_t*)__TTB_BASE)\n\n// L2 table pointers\n//----------------------------------------\n#define TTB_L1_SIZE                    (0x00004000)                        // The L1 translation table divides the full 4GB address space of a 32-bit core\n                                                                           // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.\n                                                                           // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.\n\n#define PRIVATE_TABLE_L2_BASE_4k       (__TTB_BASE + TTB_L1_SIZE)          // Map 4k Private Address space\n#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400)  // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF\n#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800)  // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF\n#define SYNC_FLAGS_TABLE_L2_BASE_4k    (__TTB_BASE + TTB_L1_SIZE + 0xC00)  // Map 4k Flag synchronization\n\n//--------------------- PERIPHERALS -------------------\n#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)\n#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)\n\n//--------------------- SYNC FLAGS --------------------\n#define FLAG_SYNC     0xFFFFF000\n#define F_SYNC_BASE   0xFFF00000  //1M aligned\n\nstatic uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0\nstatic uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable\nstatic uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable\nstatic uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable\n\n/* Define global descriptors */\nstatic uint32_t Page_L1_4k  = 0x0;  //generic\nstatic uint32_t Page_L1_64k = 0x0;  //generic\nstatic uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0\nstatic uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0\n\nvoid MMU_CreateTranslationTable(void)\n{\n    mmu_region_attributes_Type region;\n\n    //Create 4GB of faulting entries\n    MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);\n\n    /*\n     * Generate descriptors. Refer to core_ca.h to get information about attributes\n     *\n     */\n    //Create descriptors for Vectors, RO, RW, ZI sections\n    section_normal(Sect_Normal, region);\n    section_normal_cod(Sect_Normal_Cod, region);\n    section_normal_ro(Sect_Normal_RO, region);\n    section_normal_rw(Sect_Normal_RW, region);\n    //Create descriptors for peripherals\n    section_device_ro(Sect_Device_RO, region);\n    section_device_rw(Sect_Device_RW, region);\n    //Create descriptors for 64k pages\n    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);\n    //Create descriptors for 4k pages\n    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);\n\n\n    /*\n     *  Define MMU flat-map regions and attributes\n     *\n     */\n\n    //Define Image\n    MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections\n    MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);  // multiple of 1MB sections\n\n    //--------------------- PERIPHERALS -------------------\n    MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW);\n    MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE      , 16, Sect_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define private address space entry.\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,  2,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n    // Define L2CC entry.  Uncomment if PL310 is present\n    //    MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)\n    MMU_TTPage4k (TTB_BASE, F_SYNC_BASE             , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define synchronization space entry.\n    MMU_TTPage4k (TTB_BASE, FLAG_SYNC               ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    /* Set location of level 1 page table\n    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)\n    ; 13:7  - 0x0\n    ; 6     - IRGN[0] 0x1  (Inner WB WA)\n    ; 5     - NOS     0x0  (Non-shared)\n    ; 4:3   - RGN     0x01 (Outer WB WA)\n    ; 2     - IMP     0x0  (Implementation Defined)\n    ; 1     - S       0x0  (Non-shared)\n    ; 0     - IRGN[1] 0x0  (Inner WB WA) */\n    __set_TTBR0(__TTB_BASE | 0x48);\n    __ISB();\n\n    /* Set up domain access control register\n    ; We set domain 0 to Client and all other domains to No Access.\n    ; All translation table entries specify domain 0 */\n    __set_DACR(1);\n    __ISB();\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A9 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA9.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void) __attribute__ ((noreturn));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  \"LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \\n\"\n#elif defined ( __GNUC__ )\n  \"LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \\n\"\n#else\n  #error Unknown compiler.\n#endif\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  \"BL     __main                                   \\n\"\n#elif defined ( __GNUC__ )\n  \"BL     _start                                   \\n\"\n#else\n  #error Unknown compiler.\n#endif\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.s\n * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series\n * @version  V1.00\n * @date     01 Nov 2017\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n  MODULE  ?startup_ARMCA9\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n  PUBLIC  Reset_Handler\n  PUBWEAK Undef_Handler\n  PUBWEAK SVC_Handler\n  PUBWEAK PAbt_Handler\n  PUBWEAK DAbt_Handler\n  PUBWEAK IRQ_Handler\n  PUBWEAK FIQ_Handler\n\n  SECTION SVC_STACK:DATA:NOROOT(3)\n  SECTION IRQ_STACK:DATA:NOROOT(3)\n  SECTION FIQ_STACK:DATA:NOROOT(3)\n  SECTION ABT_STACK:DATA:NOROOT(3)\n  SECTION UND_STACK:DATA:NOROOT(3)\n  SECTION USR_STACK:DATA:NOROOT(3)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n\n  section RESET:CODE:NOROOT(2)\n  PUBLIC  Vectors\n\nVectors:\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n\n\n  section .text:CODE:NOROOT(2)\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n  *----------------------------------------------------------------------------*/\n  EXTERN  SystemInit\n  EXTERN  __iar_program_start\n\nReset_Handler:  \n\n  // Mask interrupts\n  CPSID   if\n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5\n  ANDS    R0, R0, #3\ngoToSleep:\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exception mode\n  CPS    #0x11\n  LDR    SP, =SFE(FIQ_STACK)\n  CPS    #0x12\n  LDR    SP, =SFE(IRQ_STACK)\n  CPS    #0x13\n  LDR    SP, =SFE(SVC_STACK)\n  CPS    #0x17\n  LDR    SP, =SFE(ABT_STACK)\n  CPS    #0x1B\n  LDR    SP, =SFE(UND_STACK)\n  CPS    #0x1F\n  LDR    SP, =SFE(USR_STACK)\n\n  // Call SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __iar_program_start\n  BL     __iar_program_start\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nUndef_Handler:\nSVC_Handler:\nPAbt_Handler:\nDAbt_Handler:\nIRQ_Handler:\nFIQ_Handler:\nDefault_Handler:\n  B .\n\n  END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/startup_ARMCA9.s.base@1.0.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.s\n * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series\n * @version  V1.00\n * @date     01 Nov 2017\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n  MODULE  ?startup_ARMCA9\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n  PUBLIC  Reset_Handler\n  PUBWEAK Undef_Handler\n  PUBWEAK SVC_Handler\n  PUBWEAK PAbt_Handler\n  PUBWEAK DAbt_Handler\n  PUBWEAK IRQ_Handler\n  PUBWEAK FIQ_Handler\n\n  SECTION SVC_STACK:DATA:NOROOT(3)\n  SECTION IRQ_STACK:DATA:NOROOT(3)\n  SECTION FIQ_STACK:DATA:NOROOT(3)\n  SECTION ABT_STACK:DATA:NOROOT(3)\n  SECTION UND_STACK:DATA:NOROOT(3)\n  SECTION USR_STACK:DATA:NOROOT(3)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n\n  section RESET:CODE:NOROOT(2)\n  PUBLIC  Vectors\n\nVectors:\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n\n\n  section .text:CODE:NOROOT(2)\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n  *----------------------------------------------------------------------------*/\n  EXTERN  SystemInit\n  EXTERN  __iar_program_start\n\nReset_Handler:  \n\n  // Mask interrupts\n  CPSID   if\n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5\n  ANDS    R0, R0, #3\ngoToSleep:\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exception mode\n  CPS    #0x11\n  LDR    SP, =SFE(FIQ_STACK)\n  CPS    #0x12\n  LDR    SP, =SFE(IRQ_STACK)\n  CPS    #0x13\n  LDR    SP, =SFE(SVC_STACK)\n  CPS    #0x17\n  LDR    SP, =SFE(ABT_STACK)\n  CPS    #0x1B\n  LDR    SP, =SFE(UND_STACK)\n  CPS    #0x1F\n  LDR    SP, =SFE(USR_STACK)\n\n  // Call SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __iar_program_start\n  BL     __iar_program_start\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nUndef_Handler:\nSVC_Handler:\nPAbt_Handler:\nDAbt_Handler:\nIRQ_Handler:\nFIQ_Handler:\nDefault_Handler:\n  B .\n\n  END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.c",
    "content": "/******************************************************************************\n * @file     system_ARMCA9.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A9 Device Series\n * @version  V1.0.1\n * @date     13. February 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"irq_ctrl.h\"\n\n#define  SYSTEM_CLOCK  12000000U\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System Initialization\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* do not use global variables because this function is called before\n   reaching pre-main. RW section may be overwritten afterwards.          */\n\n  // Invalidate entire Unified TLB\n  __set_TLBIALL(0);\n\n  // Invalidate entire branch predictor array\n  __set_BPIALL(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate instruction cache and flush branch target cache\n  __set_ICIALLU(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate data cache\n  L1C_InvalidateDCacheAll();\n\n#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\n  // Enable FPU\n  __FPU_Enable();\n#endif\n\n  // Create Translation Table\n  MMU_CreateTranslationTable();\n\n  // Enable MMU\n  MMU_Enable();\n\n  // Enable Caches\n  L1C_EnableCaches();\n  L1C_EnableBTAC();\n\n#if (__L2C_PRESENT == 1) \n  // Enable GIC\n  L2C_Enable();\n#endif\n\n  // IRQ Initialize\n  IRQ_Initialize();\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h",
    "content": "/******************************************************************************\n * @file     system_ARMCA9.h\n * @brief    CMSIS Device System Header File for Arm Cortex-A9 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __SYSTEM_ARMCA9_H\n#define __SYSTEM_ARMCA9_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SYSTEM_ARMCA9_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/system_ARMCA9.h.base@1.0.0",
    "content": "/******************************************************************************\n * @file     system_ARMCA9.h\n * @brief    CMSIS Device System Header File for Arm Cortex-A9 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __SYSTEM_ARMCA9_H\n#define __SYSTEM_ARMCA9_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SYSTEM_ARMCA9_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup\n    - component: Device:IRQ Controller:GIC\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CA9/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nmotherboard.vis.disable_visualisation=1               # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncluster.cpu0.vfp-present=1                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncluster.cpu0.ase-present=0                            # (bool  , init-time) default = '1'      : Set whether model has NEON support\ncluster.cpu0.semihosting-enable=1                     # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false\ncluster.cpu0.semihosting-hlt-enable=0                 # (bool  , init-time) default = '0'      : Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true\ncluster.cpu0.semihosting-ARM_SVC=0x123456             # (int   , init-time) default = '0x123456' : ARM SVC number for semihosting : [0x0..0xFFFFFF]\ncluster.cpu0.semihosting-Thumb_SVC=0xAB               # (int   , init-time) default = '0xAB'   : Thumb SVC number for semihosting : [0x0..0xFF]\ncluster.cpu0.semihosting-ARM_HLT=0xF000               # (int   , init-time) default = '0xF000' : ARM HLT number for semihosting : [0x0..0xFFFF]\ncluster.cpu0.semihosting-Thumb_HLT=0x3C               # (int   , init-time) default = '0x3C'   : Thumb HLT number for semihosting : [0x0..0x3F]\ncluster.cpu0.semihosting-cmd_line=\"\"                  # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncluster.cpu0.semihosting-heap_base=0x0                # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-heap_limit=0x0               # (int   , init-time) default = '0xFF000000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-stack_base=0x0               # (int   , init-time) default = '0xFFFF0000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-stack_limit=0x0              # (int   , init-time) default = '0xFF000000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncluster.cpu0.semihosting-cwd=\"\"                       # (string, init-time) default = ''       : Base directory for semihosting file access.\ncluster.dcache-state_modelled=1                       # (bool  , run-time ) default = '0'      : Set whether D-cache has stateful implementation\ncluster.icache-state_modelled=1                       # (bool  , run-time ) default = '0'      : Set whether I-cache has stateful implementation\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/ARMCM0_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM0.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M0 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM0)\n  #include \"ARMCM0.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10..31 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c.base@2.0.3",
    "content": "/******************************************************************************\n * @file     startup_ARMCM0.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M0 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM0)\n  #include \"ARMCM0.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10..31 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/system_ARMCM0.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM0.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM0 Device\n * @version  V1.0.0\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM0.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/RTE/Device/ARMCM0/tiac_arm.cmd",
    "content": "/****************************************************************************/\n/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS                   */\n/*                                                                          */\n/*   Description: This file is a sample command file that can be used       */\n/*                for linking programs built with the TI Arm Clang          */\n/*                Compiler.   Use it as a guideline; you may want to change */\n/*                the allocation scheme according to the size of your       */\n/*                program and the memory layout of your target system.      */\n/*                                                                          */\n/****************************************************************************/\n-c                                         /* LINK USING C CONVENTIONS      */\n-stack  0x4000                             /* SOFTWARE STACK SIZE           */\n-heap   0x4000                             /* HEAP AREA SIZE                */\n--args 0x1000\n\n/* SPECIFY THE SYSTEM MEMORY MAP */\nMEMORY\n{\n    V_MEM    : org = 0x00000000   len = 0x00001000  /* INT VECTOR */\n    P_MEM    : org = 0x00001000   len = 0x20000000  /* PROGRAM MEMORY (ROM) */\n    D_MEM    : org = 0x20001000   len = 0x20000000  /* DATA MEMORY    (RAM) */\n}\n\n/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */\nSECTIONS\n{\n    .intvecs    : {} > 0x0             /* INTERRUPT VECTORS                 */\n    .bss        : {} > D_MEM           /* GLOBAL & STATIC VARS              */\n    .data       : {} > D_MEM\n    .sysmem     : {} > D_MEM           /* DYNAMIC MEMORY ALLOCATION AREA    */\n    .stack      : {} > D_MEM           /* SOFTWARE SYSTEM STACK             */\n\n    .text       : {} > P_MEM           /* CODE                              */\n    .cinit      : {} > P_MEM           /* INITIALIZATION TABLES             */\n    .const      : {} > P_MEM           /* CONSTANT DATA                     */\n    .rodata     : {} > P_MEM, palign(4)\n    .init_array : {} > P_MEM           /* C++ CONSTRUCTOR TABLES            */\n\n\n    .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT)\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#------------------------------------------------------------------------------\nfvp_mps2.UART0.out_file=-                             # (string, init-time) default = ''       : Output file to hold data written by the UART (use '-' to send all output to stdout)\nfvp_mps2.UART0.shutdown_on_eot=1                      # (bool  , init-time) default = '0'      : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)\nfvp_mps2.UART0.unbuffered_output=1                    # (bool  , init-time) default = '0'      : Unbuffered output\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\n#------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/ARMCM0plus_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM0plus.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM0P)\n  #include \"ARMCM0plus.h\"\n#elif defined (ARMCM0P_MPU)\n  #include \"ARMCM0plus_MPU.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10..31 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c.base@2.0.3",
    "content": "/******************************************************************************\n * @file     startup_ARMCM0plus.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM0P)\n  #include \"ARMCM0plus.h\"\n#elif defined (ARMCM0P_MPU)\n  #include \"ARMCM0plus_MPU.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10..31 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/system_ARMCM0plus.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM0plus.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM0plus Device\n * @version  V1.0.1\n * @date     05. September 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM0plus.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/RTE/Device/ARMCM0P/tiac_arm.cmd",
    "content": "/****************************************************************************/\n/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS                   */\n/*                                                                          */\n/*   Description: This file is a sample command file that can be used       */\n/*                for linking programs built with the TI Arm Clang          */\n/*                Compiler.   Use it as a guideline; you may want to change */\n/*                the allocation scheme according to the size of your       */\n/*                program and the memory layout of your target system.      */\n/*                                                                          */\n/****************************************************************************/\n-c                                         /* LINK USING C CONVENTIONS      */\n-stack  0x4000                             /* SOFTWARE STACK SIZE           */\n-heap   0x4000                             /* HEAP AREA SIZE                */\n--args 0x1000\n\n/* SPECIFY THE SYSTEM MEMORY MAP */\nMEMORY\n{\n    V_MEM    : org = 0x00000000   len = 0x00001000  /* INT VECTOR */\n    P_MEM    : org = 0x00001000   len = 0x20000000  /* PROGRAM MEMORY (ROM) */\n    D_MEM    : org = 0x20001000   len = 0x20000000  /* DATA MEMORY    (RAM) */\n}\n\n/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */\nSECTIONS\n{\n    .intvecs    : {} > 0x0             /* INTERRUPT VECTORS                 */\n    .bss        : {} > D_MEM           /* GLOBAL & STATIC VARS              */\n    .data       : {} > D_MEM\n    .sysmem     : {} > D_MEM           /* DYNAMIC MEMORY ALLOCATION AREA    */\n    .stack      : {} > D_MEM           /* SOFTWARE SYSTEM STACK             */\n\n    .text       : {} > P_MEM           /* CODE                              */\n    .cinit      : {} > P_MEM           /* INITIALIZATION TABLES             */\n    .const      : {} > P_MEM           /* CONSTANT DATA                     */\n    .rodata     : {} > P_MEM, palign(4)\n    .init_array : {} > P_MEM           /* C++ CONSTRUCTOR TABLES            */\n\n\n    .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT)\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM0plus/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#------------------------------------------------------------------------------\nfvp_mps2.UART0.out_file=-                             # (string, init-time) default = ''       : Output file to hold data written by the UART (use '-' to send all output to stdout)\nfvp_mps2.UART0.shutdown_on_eot=1                      # (bool  , init-time) default = '0'      : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)\nfvp_mps2.UART0.unbuffered_output=1                    # (bool  , init-time) default = '0'      : Unbuffered output\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\n#------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/ARMCM23_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE        0x20000000\n#define __RAM_SIZE        0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE)\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.c\n * @brief    CMSIS-Core Device Startup File for a Cortex-M23 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.c\n * @brief    CMSIS-Core Device Startup File for a Cortex-M23 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/RTE/Device/ARMCM23/system_ARMCM23.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM23.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM23 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM23.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.SECEXT=0                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00200000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20200000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE)\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00200000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20200000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.c\n * @brief    CMSIS-Core Device Startup File for a Cortex-M23 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.c\n * @brief    CMSIS-Core Device Startup File for a Cortex-M23 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/RTE/Device/ARMCM23_TZ/system_ARMCM23.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM23.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM23 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM23.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23NS/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM23.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23\n * @version  V5.3.1\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM23_H\n#define PARTITION_ARMCM23_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n\n/*\n// <e>Setup behaviour of single SysTick\n*/\n#define SCB_ICSR_INIT 0\n\n/*\n//   <o> in a single SysTick implementation, SysTick is\n//     <0=>Secure\n//     <1=>Non-Secure\n//   <i> Value for SCB->ICSR register bit STTNS\n//   <i> only for single SysTick implementation \n*/\n#define SCB_ICSR_STTNS_VAL  0\n\n/*\n// </e>\n*/\n\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk |  SCB_AIRCR_PRIS_Msk)        )                     |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)\n    SCB->ICSR  = (SCB->ICSR  & ~(SCB_ICSR_STTNS_Msk        )) |\n                   ((SCB_ICSR_STTNS_VAL         << SCB_ICSR_STTNS_Pos)         & SCB_ICSR_STTNS_Msk);\n  #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM23_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.c\n * @brief    CMSIS-Core Device Startup File for a Cortex-M23 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.c\n * @brief    CMSIS-Core Device Startup File for a Cortex-M23 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/RTE/Device/ARMCM23_TZ/system_ARMCM23.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM23.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM23 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM23.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/ARMCM23_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM23.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23\n * @version  V5.3.1\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM23_H\n#define PARTITION_ARMCM23_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n\n/*\n// <e>Setup behaviour of single SysTick\n*/\n#define SCB_ICSR_INIT 0\n\n/*\n//   <o> in a single SysTick implementation, SysTick is\n//     <0=>Secure\n//     <1=>Non-Secure\n//   <i> Value for SCB->ICSR register bit STTNS\n//   <i> only for single SysTick implementation \n*/\n#define SCB_ICSR_STTNS_VAL  0\n\n/*\n// </e>\n*/\n\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x0000122B\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk |  SCB_AIRCR_PRIS_Msk)        )                     |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)\n    SCB->ICSR  = (SCB->ICSR  & ~(SCB_ICSR_STTNS_Msk        )) |\n                   ((SCB_ICSR_STTNS_VAL         << SCB_ICSR_STTNS_Pos)         & SCB_ICSR_STTNS_Msk);\n  #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM23_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.c\n * @brief    CMSIS-Core Device Startup File for a Cortex-M23 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.c\n * @brief    CMSIS-Core Device Startup File for a Cortex-M23 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/RTE/Device/ARMCM23_TZ/system_ARMCM23.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM23.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM23 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM23.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM23S_BL/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/ARMCM3_ac6.sct.base@1.0.0",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM3.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M3 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM3)\n  #include \"ARMCM3.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c.base@2.0.3",
    "content": "/******************************************************************************\n * @file     startup_ARMCM3.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M3 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM3)\n  #include \"ARMCM3.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM3.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM3 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM3.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c.base@1.0.1",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM3.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM3 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM3.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/RTE/Device/ARMCM3/tiac_arm.cmd",
    "content": "/****************************************************************************/\n/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS                   */\n/*                                                                          */\n/*   Description: This file is a sample command file that can be used       */\n/*                for linking programs built with the TI Arm Clang          */\n/*                Compiler.   Use it as a guideline; you may want to change */\n/*                the allocation scheme according to the size of your       */\n/*                program and the memory layout of your target system.      */\n/*                                                                          */\n/****************************************************************************/\n-c                                         /* LINK USING C CONVENTIONS      */\n-stack  0x4000                             /* SOFTWARE STACK SIZE           */\n-heap   0x4000                             /* HEAP AREA SIZE                */\n--args 0x1000\n\n/* SPECIFY THE SYSTEM MEMORY MAP */\nMEMORY\n{\n    V_MEM    : org = 0x00000000   len = 0x00001000  /* INT VECTOR */\n    P_MEM    : org = 0x00001000   len = 0x20000000  /* PROGRAM MEMORY (ROM) */\n    D_MEM    : org = 0x20001000   len = 0x20000000  /* DATA MEMORY    (RAM) */\n}\n\n/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */\nSECTIONS\n{\n    .intvecs    : {} > 0x0             /* INTERRUPT VECTORS                 */\n    .bss        : {} > D_MEM           /* GLOBAL & STATIC VARS              */\n    .data       : {} > D_MEM\n    .sysmem     : {} > D_MEM           /* DYNAMIC MEMORY ALLOCATION AREA    */\n    .stack      : {} > D_MEM           /* SOFTWARE SYSTEM STACK             */\n\n    .text       : {} > P_MEM           /* CODE                              */\n    .cinit      : {} > P_MEM           /* INITIALIZATION TABLES             */\n    .const      : {} > P_MEM           /* CONSTANT DATA                     */\n    .rodata     : {} > P_MEM, palign(4)\n    .init_array : {} > P_MEM           /* C++ CONSTRUCTOR TABLES            */\n\n\n    .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT)\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM3/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\narmcortexm3ct.semihosting-enable=1                    # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\narmcortexm3ct.semihosting-Thumb_SVC=0xAB              # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\narmcortexm3ct.semihosting-cmd_line=\"\"                 # (string, init-time) default = ''       : Command line available to semihosting SVC calls\narmcortexm3ct.semihosting-heap_base=0x0               # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\narmcortexm3ct.semihosting-heap_limit=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\narmcortexm3ct.semihosting-stack_base=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\narmcortexm3ct.semihosting-stack_limit=0x0             # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\narmcortexm3ct.semihosting-cwd=\"\"                      # (string, init-time) default = ''       : Base directory for semihosting file access.\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/ARMCM33_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/startup_ARMCM33.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/RTE/Device/ARMCM33_DSP_FP/tiac_arm.cmd",
    "content": "/****************************************************************************/\n/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS                   */\n/*                                                                          */\n/*   Description: This file is a sample command file that can be used       */\n/*                for linking programs built with the TI Arm Clang          */\n/*                Compiler.   Use it as a guideline; you may want to change */\n/*                the allocation scheme according to the size of your       */\n/*                program and the memory layout of your target system.      */\n/*                                                                          */\n/****************************************************************************/\n-c                                         /* LINK USING C CONVENTIONS      */\n-stack  0x4000                             /* SOFTWARE STACK SIZE           */\n-heap   0x4000                             /* HEAP AREA SIZE                */\n--args 0x1000\n\n/* SPECIFY THE SYSTEM MEMORY MAP */\nMEMORY\n{\n    V_MEM    : org = 0x00000000   len = 0x00001000  /* INT VECTOR */\n    P_MEM    : org = 0x00001000   len = 0x20000000  /* PROGRAM MEMORY (ROM) */\n    D_MEM    : org = 0x20001000   len = 0x20000000  /* DATA MEMORY    (RAM) */\n}\n\n/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */\nSECTIONS\n{\n    .intvecs    : {} > 0x0             /* INTERRUPT VECTORS                 */\n    .bss        : {} > D_MEM           /* GLOBAL & STATIC VARS              */\n    .data       : {} > D_MEM\n    .sysmem     : {} > D_MEM           /* DYNAMIC MEMORY ALLOCATION AREA    */\n    .stack      : {} > D_MEM           /* SOFTWARE SYSTEM STACK             */\n\n    .text       : {} > P_MEM           /* CODE                              */\n    .cinit      : {} > P_MEM           /* INITIALIZATION TABLES             */\n    .const      : {} > P_MEM           /* CONSTANT DATA                     */\n    .rodata     : {} > P_MEM, palign(4)\n    .init_array : {} > P_MEM           /* C++ CONSTRUCTOR TABLES            */\n\n\n    .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT)\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x0                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=0                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00200000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20200000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00200000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20200000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33NS/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM33.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33\n * @version  V1.1.1\n * @date     12. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM33_H\n#define PARTITION_ARMCM33_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM33_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM33.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33\n * @version  V1.1.1\n * @date     12. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM33_H\n#define PARTITION_ARMCM33_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x0000122B\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM33_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM33S_BL/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/ARMCM35P_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/startup_ARMCM35P.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/RTE/Device/ARMCM35P_DSP_FP/system_ARMCM35P.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM35P.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM35P Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35P/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x0                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=0                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00200000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20200000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00200000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20200000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM35P.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM35P Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PNS/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM35P.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P\n * @version  V1.0.0\n * @date     03. September 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM35P_H\n#define PARTITION_ARMCM35P_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM35P_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM35P.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM35P Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/ARMCM35P_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/partition_ARMCM35P.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM35P.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P\n * @version  V1.0.0\n * @date     03. September 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM35P_H\n#define PARTITION_ARMCM35P_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x0000122B\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM35P_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/startup_ARMCM35P.c.base@2.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/RTE/Device/ARMCM35P_DSP_FP_TZ/system_ARMCM35P.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM35P.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM35P Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM35PS_BL/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/ARMCM4_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM4.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M4 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM4)\n  #include \"ARMCM4.h\"\n#elif defined (ARMCM4_FP)\n  #include \"ARMCM4_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c.base@2.0.3",
    "content": "/******************************************************************************\n * @file     startup_ARMCM4.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M4 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM4)\n  #include \"ARMCM4.h\"\n#elif defined (ARMCM4_FP)\n  #include \"ARMCM4_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/system_ARMCM4.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM4.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM4 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM4)\n  #include \"ARMCM4.h\"\n#elif defined (ARMCM4_FP)\n  #include \"ARMCM4_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/RTE/Device/ARMCM4/tiac_arm.cmd",
    "content": "/****************************************************************************/\n/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS                   */\n/*                                                                          */\n/*   Description: This file is a sample command file that can be used       */\n/*                for linking programs built with the TI Arm Clang          */\n/*                Compiler.   Use it as a guideline; you may want to change */\n/*                the allocation scheme according to the size of your       */\n/*                program and the memory layout of your target system.      */\n/*                                                                          */\n/****************************************************************************/\n-c                                         /* LINK USING C CONVENTIONS      */\n-stack  0x4000                             /* SOFTWARE STACK SIZE           */\n-heap   0x4000                             /* HEAP AREA SIZE                */\n--args 0x1000\n\n/* SPECIFY THE SYSTEM MEMORY MAP */\nMEMORY\n{\n    V_MEM    : org = 0x00000000   len = 0x00001000  /* INT VECTOR */\n    P_MEM    : org = 0x00001000   len = 0x20000000  /* PROGRAM MEMORY (ROM) */\n    D_MEM    : org = 0x20001000   len = 0x20000000  /* DATA MEMORY    (RAM) */\n}\n\n/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */\nSECTIONS\n{\n    .intvecs    : {} > 0x0             /* INTERRUPT VECTORS                 */\n    .bss        : {} > D_MEM           /* GLOBAL & STATIC VARS              */\n    .data       : {} > D_MEM\n    .sysmem     : {} > D_MEM           /* DYNAMIC MEMORY ALLOCATION AREA    */\n    .stack      : {} > D_MEM           /* SOFTWARE SYSTEM STACK             */\n\n    .text       : {} > P_MEM           /* CODE                              */\n    .cinit      : {} > P_MEM           /* INITIALIZATION TABLES             */\n    .const      : {} > P_MEM           /* CONSTANT DATA                     */\n    .rodata     : {} > P_MEM, palign(4)\n    .init_array : {} > P_MEM           /* C++ CONSTRUCTOR TABLES            */\n\n\n    .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT)\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\narmcortexm4ct.vfp-present=0                           # (bool  , init-time) default = '1'      : Set whether the model has VFP support\narmcortexm4ct.semihosting-enable=1                    # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\narmcortexm4ct.semihosting-Thumb_SVC=0xAB              # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\narmcortexm4ct.semihosting-cmd_line=\"\"                 # (string, init-time) default = ''       : Command line available to semihosting SVC calls\narmcortexm4ct.semihosting-heap_base=0x0               # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\narmcortexm4ct.semihosting-heap_limit=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\narmcortexm4ct.semihosting-stack_base=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\narmcortexm4ct.semihosting-stack_limit=0x0             # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\narmcortexm4ct.semihosting-cwd=\"\"                      # (string, init-time) default = ''       : Base directory for semihosting file access.\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/ARMCM4_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM4.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M4 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM4)\n  #include \"ARMCM4.h\"\n#elif defined (ARMCM4_FP)\n  #include \"ARMCM4_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/startup_ARMCM4.c.base@2.0.3",
    "content": "/******************************************************************************\n * @file     startup_ARMCM4.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M4 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM4)\n  #include \"ARMCM4.h\"\n#elif defined (ARMCM4_FP)\n  #include \"ARMCM4_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/system_ARMCM4.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM4.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM4 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM4)\n  #include \"ARMCM4.h\"\n#elif defined (ARMCM4_FP)\n  #include \"ARMCM4_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/RTE/Device/ARMCM4_FP/tiac_arm.cmd",
    "content": "/****************************************************************************/\n/* tiac_arm.cmd - COMMAND FILE FOR LINKING ARM C PROGRAMS                   */\n/*                                                                          */\n/*   Description: This file is a sample command file that can be used       */\n/*                for linking programs built with the TI Arm Clang          */\n/*                Compiler.   Use it as a guideline; you may want to change */\n/*                the allocation scheme according to the size of your       */\n/*                program and the memory layout of your target system.      */\n/*                                                                          */\n/****************************************************************************/\n-c                                         /* LINK USING C CONVENTIONS      */\n-stack  0x4000                             /* SOFTWARE STACK SIZE           */\n-heap   0x4000                             /* HEAP AREA SIZE                */\n--args 0x1000\n\n/* SPECIFY THE SYSTEM MEMORY MAP */\nMEMORY\n{\n    V_MEM    : org = 0x00000000   len = 0x00001000  /* INT VECTOR */\n    P_MEM    : org = 0x00001000   len = 0x20000000  /* PROGRAM MEMORY (ROM) */\n    D_MEM    : org = 0x20001000   len = 0x20000000  /* DATA MEMORY    (RAM) */\n}\n\n/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */\nSECTIONS\n{\n    .intvecs    : {} > 0x0             /* INTERRUPT VECTORS                 */\n    .bss        : {} > D_MEM           /* GLOBAL & STATIC VARS              */\n    .data       : {} > D_MEM\n    .sysmem     : {} > D_MEM           /* DYNAMIC MEMORY ALLOCATION AREA    */\n    .stack      : {} > D_MEM           /* SOFTWARE SYSTEM STACK             */\n\n    .text       : {} > P_MEM           /* CODE                              */\n    .cinit      : {} > P_MEM           /* INITIALIZATION TABLES             */\n    .const      : {} > P_MEM           /* CONSTANT DATA                     */\n    .rodata     : {} > P_MEM, palign(4)\n    .init_array : {} > P_MEM           /* C++ CONSTRUCTOR TABLES            */\n\n\n    .TI.ramfunc : {} load=P_MEM, run=D_MEM, table(BINIT)\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM4FP/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\narmcortexm4ct.vfp-present=1                           # (bool  , init-time) default = '1'      : Set whether the model has VFP support\narmcortexm4ct.semihosting-enable=1                    # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\narmcortexm4ct.semihosting-Thumb_SVC=0xAB              # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\narmcortexm4ct.semihosting-cmd_line=\"\"                 # (string, init-time) default = ''       : Command line available to semihosting SVC calls\narmcortexm4ct.semihosting-heap_base=0x0               # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\narmcortexm4ct.semihosting-heap_limit=0                # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\narmcortexm4ct.semihosting-stack_base=0                # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\narmcortexm4ct.semihosting-stack_limit=0               # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\narmcortexm4ct.semihosting-cwd=\"\"                      # (string, init-time) default = ''       : Base directory for semihosting file access.\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00200000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20200000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00200000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20200000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM55.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M55 Device\n * @version  V1.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM55.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M55 Device\n * @version  V1.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM55.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM55 Device\n * @version  V1.1.0\n * @date     28. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM55.h\"\n  #endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            ( 5000000UL)      /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (5U * XTAL)\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Set low-power state for PDEPU                */\n  /*  0b00  | ON, PDEPU is not in low-power state */\n  /*  0b01  | ON, but the clock is off            */\n  /*  0b10  | RET(ention)                         */\n  /*  0b11  | OFF                                 */\n\n  /* Clear ELPSTATE, value is 0b11 on Cold reset */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM55.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM55 Device\n * @version  V1.1.0\n * @date     28. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM55.h\"\n  #endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            ( 5000000UL)      /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (5U * XTAL)\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Set low-power state for PDEPU                */\n  /*  0b00  | ON, PDEPU is not in low-power state */\n  /*  0b01  | ON, but the clock is off            */\n  /*  0b10  | RET(ention)                         */\n  /*  0b11  | OFF                                 */\n\n  /* Clear ELPSTATE, value is 0b11 on Cold reset */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55NS/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.MVE=2                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/partition_ARMCM55.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM55.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.0\n * @date     20. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM55_H\n#define PARTITION_ARMCM55_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM55_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM55.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M55 Device\n * @version  V1.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM55.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M55 Device\n * @version  V1.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM55.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM55 Device\n * @version  V1.1.0\n * @date     28. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM55.h\"\n  #endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            ( 5000000UL)      /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (5U * XTAL)\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Set low-power state for PDEPU                */\n  /*  0b00  | ON, PDEPU is not in low-power state */\n  /*  0b01  | ON, but the clock is off            */\n  /*  0b10  | RET(ention)                         */\n  /*  0b11  | OFF                                 */\n\n  /* Clear ELPSTATE, value is 0b11 on Cold reset */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM55.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM55 Device\n * @version  V1.1.0\n * @date     28. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM55.h\"\n  #endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            ( 5000000UL)      /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (5U * XTAL)\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Set low-power state for PDEPU                */\n  /*  0b00  | ON, PDEPU is not in low-power state */\n  /*  0b01  | ON, but the clock is off            */\n  /*  0b10  | RET(ention)                         */\n  /*  0b11  | OFF                                 */\n\n  /* Clear ELPSTATE, value is 0b11 on Cold reset */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.MVE=2                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/ARMCM55_ac6_s.sct.base@1.1.0",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/partition_ARMCM55.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM55.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.0\n * @date     20. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM55_H\n#define PARTITION_ARMCM55_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x0000122B\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM55_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM55.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M55 Device\n * @version  V1.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM55.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M55 Device\n * @version  V1.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM55.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM55 Device\n * @version  V1.1.0\n * @date     28. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM55.h\"\n  #endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            ( 5000000UL)      /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (5U * XTAL)\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Set low-power state for PDEPU                */\n  /*  0b00  | ON, PDEPU is not in low-power state */\n  /*  0b01  | ON, but the clock is off            */\n  /*  0b10  | RET(ention)                         */\n  /*  0b11  | OFF                                 */\n\n  /* Clear ELPSTATE, value is 0b11 on Cold reset */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM55.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM55 Device\n * @version  V1.1.0\n * @date     28. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM55.h\"\n  #endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            ( 5000000UL)      /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (5U * XTAL)\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Set low-power state for PDEPU                */\n  /*  0b00  | ON, PDEPU is not in low-power state */\n  /*  0b01  | ON, but the clock is off            */\n  /*  0b10  | RET(ention)                         */\n  /*  0b11  | OFF                                 */\n\n  /* Clear ELPSTATE, value is 0b11 on Cold reset */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM55S_BL/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.MVE=2                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/ARMCM7_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM7.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M7 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c.base@2.0.3",
    "content": "/******************************************************************************\n * @file     startup_ARMCM7.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M7 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/RTE/Device/ARMCM7/system_ARMCM7.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM7.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM7 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\narmcortexm7ct.vfp-present=0                           # (bool  , init-time) default = '1'      : Set whether the model has VFP support\narmcortexm7ct.semihosting-enable=1                    # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\narmcortexm7ct.semihosting-Thumb_SVC=0xAB              # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\narmcortexm7ct.semihosting-cmd_line=\"\"                 # (string, init-time) default = ''       : Command line available to semihosting SVC calls\narmcortexm7ct.semihosting-heap_base=0x0               # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-heap_limit=0                # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-stack_base=0                # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-stack_limit=0               # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-cwd=\"\"                      # (string, init-time) default = ''       : Base directory for semihosting file access.\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/ARMCM7_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM7.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M7 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/startup_ARMCM7.c.base@2.0.3",
    "content": "/******************************************************************************\n * @file     startup_ARMCM7.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M7 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/RTE/Device/ARMCM7_DP/system_ARMCM7.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM7.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM7 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7DP/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\narmcortexm7ct.vfp-present=1                           # (bool  , init-time) default = '1'      : Set whether the model has VFP support\narmcortexm7ct.semihosting-enable=1                    # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\narmcortexm7ct.semihosting-Thumb_SVC=0xAB              # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\narmcortexm7ct.semihosting-cmd_line=\"\"                 # (string, init-time) default = ''       : Command line available to semihosting SVC calls\narmcortexm7ct.semihosting-heap_base=0x0               # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-heap_limit=0                # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-stack_base=0                # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-stack_limit=0               # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-cwd=\"\"                      # (string, init-time) default = ''       : Base directory for semihosting file access.\narmcortexm7ct.DP_FLOAT=1                              # (bool  , init-time) default = '1'      : Support 8-byte floats\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/ARMCM7_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM7.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M7 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/startup_ARMCM7.c.base@2.0.3",
    "content": "/******************************************************************************\n * @file     startup_ARMCM7.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M7 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/RTE/Device/ARMCM7_SP/system_ARMCM7.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM7.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM7 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM7SP/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\narmcortexm7ct.vfp-present=1                           # (bool  , init-time) default = '1'      : Set whether the model has VFP support\narmcortexm7ct.semihosting-enable=1                    # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\narmcortexm7ct.semihosting-Thumb_SVC=0xAB              # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\narmcortexm7ct.semihosting-cmd_line=\"\"                 # (string, init-time) default = ''       : Command line available to semihosting SVC calls\narmcortexm7ct.semihosting-heap_base=0x0               # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-heap_limit=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-stack_base=0x0              # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-stack_limit=0x0             # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\narmcortexm7ct.semihosting-cwd=\"\"                      # (string, init-time) default = ''       : Base directory for semihosting file access.\narmcortexm7ct.DP_FLOAT=0                              # (bool  , init-time) default = '1'      : Support 8-byte floats\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00200000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20200000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0> CMSE VeneerBase Address     <0x0-0xFFFFFFFF:8>\n;     <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)\n;   <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_BASE    0xFFFFFFFF\n#define __CMSEVENEER_SIZE    0x00000400\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#else\n#define __CV_BASE          ( __CMSEVENEER_BASE )\n#endif\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/ARMCM85_ac6.sct.base@1.0.0",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0> CMSE VeneerBase Address     <0x0-0xFFFFFFFF:8>\n;     <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)\n;   <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_BASE    0xFFFFFFFF\n#define __CMSEVENEER_SIZE    0x00000400\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#else\n#define __CV_BASE          ( __CMSEVENEER_BASE )\n#endif\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00200000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20200000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM85.c\n * @brief    CMSIS Device Startup File for ARMCM85 Device\n * @version  V1.0.0\n * @date     07. February 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM85.c\n * @brief    CMSIS Device Startup File for ARMCM85 Device\n * @version  V1.0.0\n * @date     07. February 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM85.c\n * @brief    CMSIS Device System Source File for ARMCM85 Device\n * @version  V1.0.0\n * @date     30. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM85.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n  /* Set CPDLPSTATE.RLPSTATE to 0\n     Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.\n     Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  );\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n\n  /* Enable Branch Prediction */\n  SCB->CCR |= SCB_CCR_BP_Msk;\n\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM85.c\n * @brief    CMSIS Device System Source File for ARMCM85 Device\n * @version  V1.0.0\n * @date     30. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM85.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n  /* Set CPDLPSTATE.RLPSTATE to 0\n     Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.\n     Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  );\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n\n  /* Enable Branch Prediction */\n  SCB->CCR |= SCB_CCR_BP_Msk;\n\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85NS/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.MVE=1                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included\ncpu0.ID_ISAR5.PACBTI=1                                # (int   , init-time) default = '0x0'    : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0> CMSE VeneerBase Address     <0x0-0xFFFFFFFF:8>\n;     <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)\n;   <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_BASE    0xFFFFFFFF\n#define __CMSEVENEER_SIZE    0x00000400\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#else\n#define __CV_BASE          ( __CMSEVENEER_BASE )\n#endif\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0> CMSE VeneerBase Address     <0x0-0xFFFFFFFF:8>\n;     <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)\n;   <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_BASE    0xFFFFFFFF\n#define __CMSEVENEER_SIZE    0x00000400\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#else\n#define __CV_BASE          ( __CMSEVENEER_BASE )\n#endif\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM85.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.0\n * @date     07. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM85_H\n#define PARTITION_ARMCM85_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR0     \"NSC code\"   /* description SAU region 0 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR1     \"NS code\"   /* description SAU region 1 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR2     \"NS data\"   /* description SAU region 2 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR3     \"NS peripherals\"   /* description SAU region 3 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR4     \"SAU region 4\"   /* description SAU region 4 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR5     \"SAU region 5\"   /* description SAU region 5 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR6     \"SAU region 6\"   /* description SAU region 6 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR7     \"SAU region 7\"   /* description SAU region 7 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM85_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM85.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.0\n * @date     07. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM85_H\n#define PARTITION_ARMCM85_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR0     \"NSC code\"   /* description SAU region 0 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR1     \"NS code\"   /* description SAU region 1 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR2     \"NS data\"   /* description SAU region 2 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR3     \"NS peripherals\"   /* description SAU region 3 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR4     \"SAU region 4\"   /* description SAU region 4 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR5     \"SAU region 5\"   /* description SAU region 5 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR6     \"SAU region 6\"   /* description SAU region 6 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR7     \"SAU region 7\"   /* description SAU region 7 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM85_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM85.c\n * @brief    CMSIS Device Startup File for ARMCM85 Device\n * @version  V1.0.0\n * @date     07. February 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM85.c\n * @brief    CMSIS Device Startup File for ARMCM85 Device\n * @version  V1.0.0\n * @date     07. February 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM85.c\n * @brief    CMSIS Device System Source File for ARMCM85 Device\n * @version  V1.0.0\n * @date     30. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM85.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n  /* Set CPDLPSTATE.RLPSTATE to 0\n     Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.\n     Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  );\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n\n  /* Enable Branch Prediction */\n  SCB->CCR |= SCB_CCR_BP_Msk;\n\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM85.c\n * @brief    CMSIS Device System Source File for ARMCM85 Device\n * @version  V1.0.0\n * @date     30. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM85.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n  /* Set CPDLPSTATE.RLPSTATE to 0\n     Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.\n     Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  );\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n\n  /* Enable Branch Prediction */\n  SCB->CCR |= SCB_CCR_BP_Msk;\n\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.MVE=1                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included\ncpu0.ID_ISAR5.PACBTI=1                                # (int   , init-time) default = '0x0'    : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00200000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0> CMSE VeneerBase Address     <0x0-0xFFFFFFFF:8>\n;     <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)\n;   <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_BASE    0xFFFFFFFF\n#define __CMSEVENEER_SIZE    0x00000400\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#else\n#define __CV_BASE          ( __CMSEVENEER_BASE )\n#endif\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/ARMCM85_ac6_s.sct.base@1.0.0",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0> CMSE VeneerBase Address     <0x0-0xFFFFFFFF:8>\n;     <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)\n;   <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_BASE    0xFFFFFFFF\n#define __CMSEVENEER_SIZE    0x00000400\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#else\n#define __CV_BASE          ( __CMSEVENEER_BASE )\n#endif\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00200000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00200000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 8;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/gcc_arm.ld.base@1.0.0",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM85.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.0\n * @date     07. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM85_H\n#define PARTITION_ARMCM85_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR0     \"NSC code\"   /* description SAU region 0 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR1     \"NS code\"   /* description SAU region 1 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR2     \"NS data\"   /* description SAU region 2 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR3     \"NS peripherals\"   /* description SAU region 3 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR4     \"SAU region 4\"   /* description SAU region 4 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR5     \"SAU region 5\"   /* description SAU region 5 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR6     \"SAU region 6\"   /* description SAU region 6 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR7     \"SAU region 7\"   /* description SAU region 7 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x0000122B\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM85_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/partition_ARMCM85.h.base@1.0.0",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM85.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.0\n * @date     07. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM85_H\n#define PARTITION_ARMCM85_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR0     \"NSC code\"   /* description SAU region 0 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR1     \"NS code\"   /* description SAU region 1 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR2     \"NS data\"   /* description SAU region 2 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR3     \"NS peripherals\"   /* description SAU region 3 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR4     \"SAU region 4\"   /* description SAU region 4 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR5     \"SAU region 5\"   /* description SAU region 5 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR6     \"SAU region 6\"   /* description SAU region 6 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR7     \"SAU region 7\"   /* description SAU region 7 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM85_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM85.c\n * @brief    CMSIS Device Startup File for ARMCM85 Device\n * @version  V1.0.0\n * @date     07. February 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/startup_ARMCM85.c.base@1.0.0",
    "content": "/******************************************************************************\n * @file     startup_ARMCM85.c\n * @brief    CMSIS Device Startup File for ARMCM85 Device\n * @version  V1.0.0\n * @date     07. February 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM85.c\n * @brief    CMSIS Device System Source File for ARMCM85 Device\n * @version  V1.0.0\n * @date     30. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM85.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n  /* Set CPDLPSTATE.RLPSTATE to 0\n     Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.\n     Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  );\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n\n  /* Enable Branch Prediction */\n  SCB->CCR |= SCB_CCR_BP_Msk;\n\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/RTE/Device/ARMCM85/system_ARMCM85.c.base@1.0.0",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM85.c\n * @brief    CMSIS Device System Source File for ARMCM85 Device\n * @version  V1.0.0\n * @date     30. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM85.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n  /* Set CPDLPSTATE.RLPSTATE to 0\n     Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.\n     Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  );\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n\n  /* Enable Branch Prediction */\n  SCB->CCR |= SCB_CCR_BP_Msk;\n\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/Target.clayer.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/clayer.schema.json\n\nlayer:\n  # type: Target\n  description: Target setup\n\n  # packs:\n  #   - pack: ARM::CMSIS\n\n  components:\n    # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion]\n    - component: ARM::CMSIS:CORE\n    - component: Device:Startup&C Startup\n\n  misc:\n    - for-compiler: IAR\n      Link: [--config generic_cortex.icf]\n\n  groups:\n    - group: VHT/FVP\n      files:\n        - file: ./model_config.txt\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Layer/Target/CM85S_BL/model_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\nfvp_mps2.mps2_visualisation.disable-visualisation=1   # (bool  , init-time) default = '0'      : Enable/disable visualisation\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.MVE=1                                            # (int   , init-time) default = '0x1'    : Set whether the model has MVE support. If FPU = 0: 0=MVE not included, 1=Integer subset of MVE included. If FPU = 1: 0=MVE not included, 1=Integer subset of MVE included, 2=Integer and half and single precision floating point MVE included\ncpu0.ID_ISAR5.PACBTI=1                                # (int   , init-time) default = '0x0'    : 0: PAC/BTI not implemented, 1: PAC implemented using the QARMA5 algorithm with BTI, 2: PAC implemented using an IMP DEF algorithm with BTI, 4: PAC implemented using the QARMA3 algorithm with BTI\ncpu0.semihosting-enable=1                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.semihosting-Thumb_SVC=0xAB                       # (int   , init-time) default = '0xAB'   : T32 SVC number for semihosting : [0x0..0xFF]\ncpu0.semihosting-cmd_line=\"\"                          # (string, init-time) default = ''       : Command line available to semihosting SVC calls\ncpu0.semihosting-heap_base=0x0                        # (int   , init-time) default = '0x0'    : Virtual address of heap base : [0x0..0xFFFFFFFF]\ncpu0.semihosting-heap_limit=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_base=0x0                       # (int   , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]\ncpu0.semihosting-stack_limit=0x0                      # (int   , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]\ncpu0.semihosting-cwd=\"\"                               # (string, init-time) default = ''       : Base directory for semihosting file access.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Project/Bootloader.cproject.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/cproject.schema.json\n\nproject:\n  layers:\n    # App: CMSIS-Core Validation for Cortex-M (Bootloader part)\n    - layer: ../Layer/App/Bootloader_Cortex-M/App.clayer.yml\n      for-context:\n        - .AC6_low\n        - .AC6_mid\n        - .AC6_high\n        - .AC6_size\n        - .AC6_tiny\n        - .GCC_low\n        - .GCC_mid\n        - .GCC_high\n        - .GCC_size\n        - .GCC_tiny\n        - .IAR_low\n        - .IAR_mid\n        - .IAR_high\n        - .IAR_size\n        - .IAR_tiny\n\n    #Target: CM23S\n    - layer: ../Layer/Target/CM23S_BL/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM23S\n        - .AC6_mid+CM23S\n        - .AC6_high+CM23S\n        - .AC6_size+CM23S\n        - .AC6_tiny+CM23S\n        - .GCC_low+CM23S\n        - .GCC_mid+CM23S\n        - .GCC_high+CM23S\n        - .GCC_size+CM23S\n        - .GCC_tiny+CM23S\n        - .IAR_low+CM23S\n        - .IAR_mid+CM23S\n        - .IAR_high+CM23S\n        - .IAR_size+CM23S\n        - .IAR_tiny+CM23S\n\n    #Target: CM33S\n    - layer: ../Layer/Target/CM33S_BL/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM33S\n        - .AC6_mid+CM33S\n        - .AC6_high+CM33S\n        - .AC6_size+CM33S\n        - .AC6_tiny+CM33S\n        - .GCC_low+CM33S\n        - .GCC_mid+CM33S\n        - .GCC_high+CM33S\n        - .GCC_size+CM33S\n        - .GCC_tiny+CM33S\n        - .IAR_low+CM33S\n        - .IAR_mid+CM33S\n        - .IAR_high+CM33S\n        - .IAR_size+CM33S\n        - .IAR_tiny+CM33S\n\n    #Target: CM35PS\n    - layer: ../Layer/Target/CM35PS_BL/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM35PS\n        - .AC6_mid+CM35PS\n        - .AC6_high+CM35PS\n        - .AC6_size+CM35PS\n        - .AC6_tiny+CM35PS\n        - .GCC_low+CM35PS\n        - .GCC_mid+CM35PS\n        - .GCC_high+CM35PS\n        - .GCC_size+CM35PS\n        - .GCC_tiny+CM35PS\n        - .IAR_low+CM35PS\n        - .IAR_mid+CM35PS\n        - .IAR_high+CM35PS\n        - .IAR_size+CM35PS\n        - .IAR_tiny+CM35PS\n\n    #Target: CM55S\n    - layer: ../Layer/Target/CM55S_BL/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM55S\n        - .AC6_mid+CM55S\n        - .AC6_high+CM55S\n        - .AC6_size+CM55S\n        - .AC6_tiny+CM55S\n        - .GCC_low+CM55S\n        - .GCC_mid+CM55S\n        - .GCC_high+CM55S\n        - .GCC_size+CM55S\n        - .GCC_tiny+CM55S\n        - .IAR_low+CM55S\n        - .IAR_mid+CM55S\n        - .IAR_high+CM55S\n        - .IAR_size+CM55S\n        - .IAR_tiny+CM55S\n\n    #Target: CM85S\n    - layer: ../Layer/Target/CM85S_BL/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM85S\n        - .AC6_mid+CM85S\n        - .AC6_high+CM85S\n        - .AC6_size+CM85S\n        - .AC6_tiny+CM85S\n        - .GCC_low+CM85S\n        - .GCC_mid+CM85S\n        - .GCC_high+CM85S\n        - .GCC_size+CM85S\n        - .GCC_tiny+CM85S\n        - .IAR_low+CM85S\n        - .IAR_mid+CM85S\n        - .IAR_high+CM85S\n        - .IAR_size+CM85S\n        - .IAR_tiny+CM85S\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.cproject.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/cproject.schema.json\n\nproject:\n  layers:\n    # App: CMSIS-Core Validation for Cortex-M\n    - layer: ../Layer/App/Validation_Cortex-M/App.clayer.yml\n      for-context:\n        - +CM0\n        - +CM0plus\n        - +CM3\n        - +CM4\n        - +CM4FP\n        - +CM7\n        - +CM7SP\n        - +CM7DP\n        - +CM23\n        - +CM23S\n        - +CM23NS\n        - +CM33\n        - +CM33S\n        - +CM33NS\n        - +CM35P\n        - +CM35PS\n        - +CM35PNS\n        - +CM55S\n        - +CM55NS\n        - +CM85S\n        - +CM85NS\n\n    # App: CMSIS-Core Validation for Cortex-A\n    - layer: ../Layer/App/Validation_Cortex-A/App.clayer.yml\n      for-context:\n        - +CA5\n        - +CA7\n        - +CA9\n\n    #Target: CM0\n    - layer: ../Layer/Target/CM0/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM0\n        - .AC6_mid+CM0\n        - .AC6_high+CM0\n        - .AC6_size+CM0\n        - .AC6_tiny+CM0\n        - .GCC_low+CM0\n        - .GCC_mid+CM0\n        - .GCC_high+CM0\n        - .GCC_size+CM0\n        - .GCC_tiny+CM0\n        - .IAR_low+CM0\n        - .IAR_mid+CM0\n        - .IAR_high+CM0\n        - .IAR_size+CM0\n        - .IAR_tiny+CM0\n\n    #Target: CM0plus\n    - layer: ../Layer/Target/CM0plus/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM0plus\n        - .AC6_mid+CM0plus\n        - .AC6_high+CM0plus\n        - .AC6_size+CM0plus\n        - .AC6_tiny+CM0plus\n        - .GCC_low+CM0plus\n        - .GCC_mid+CM0plus\n        - .GCC_high+CM0plus\n        - .GCC_size+CM0plus\n        - .GCC_tiny+CM0plus\n        - .IAR_low+CM0plus\n        - .IAR_mid+CM0plus\n        - .IAR_high+CM0plus\n        - .IAR_size+CM0plus\n        - .IAR_tiny+CM0plus\n\n    #Target: CM3\n    - layer: ../Layer/Target/CM3/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM3\n        - .AC6_mid+CM3\n        - .AC6_high+CM3\n        - .AC6_size+CM3\n        - .AC6_tiny+CM3\n        - .GCC_low+CM3\n        - .GCC_mid+CM3\n        - .GCC_high+CM3\n        - .GCC_size+CM3\n        - .GCC_tiny+CM3\n        - .IAR_low+CM3\n        - .IAR_mid+CM3\n        - .IAR_high+CM3\n        - .IAR_size+CM3\n        - .IAR_tiny+CM3\n\n    #Target: CM4\n    - layer: ../Layer/Target/CM4/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM4\n        - .AC6_mid+CM4\n        - .AC6_high+CM4\n        - .AC6_size+CM4\n        - .AC6_tiny+CM4\n        - .GCC_low+CM4\n        - .GCC_mid+CM4\n        - .GCC_high+CM4\n        - .GCC_size+CM4\n        - .GCC_tiny+CM4\n        - .IAR_low+CM4\n        - .IAR_mid+CM4\n        - .IAR_high+CM4\n        - .IAR_size+CM4\n        - .IAR_tiny+CM4\n\n    #Target: CM4FP\n    - layer: ../Layer/Target/CM4FP/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM4FP\n        - .AC6_mid+CM4FP\n        - .AC6_high+CM4FP\n        - .AC6_size+CM4FP\n        - .AC6_tiny+CM4FP\n        - .GCC_low+CM4FP\n        - .GCC_mid+CM4FP\n        - .GCC_high+CM4FP\n        - .GCC_size+CM4FP\n        - .GCC_tiny+CM4FP\n        - .IAR_low+CM4FP\n        - .IAR_mid+CM4FP\n        - .IAR_high+CM4FP\n        - .IAR_size+CM4FP\n        - .IAR_tiny+CM4FP\n\n    #Target: CM7\n    - layer: ../Layer/Target/CM7/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM7\n        - .AC6_mid+CM7\n        - .AC6_high+CM7\n        - .AC6_size+CM7\n        - .AC6_tiny+CM7\n        - .GCC_low+CM7\n        - .GCC_mid+CM7\n        - .GCC_high+CM7\n        - .GCC_size+CM7\n        - .GCC_tiny+CM7\n        - .IAR_low+CM7\n        - .IAR_mid+CM7\n        - .IAR_high+CM7\n        - .IAR_size+CM7\n        - .IAR_tiny+CM7\n\n    #Target: CM7SP\n    - layer: ../Layer/Target/CM7SP/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM7SP\n        - .AC6_mid+CM7SP\n        - .AC6_high+CM7SP\n        - .AC6_size+CM7SP\n        - .AC6_tiny+CM7SP\n        - .GCC_low+CM7SP\n        - .GCC_mid+CM7SP\n        - .GCC_high+CM7SP\n        - .GCC_size+CM7SP\n        - .GCC_tiny+CM7SP\n        - .IAR_low+CM7SP\n        - .IAR_mid+CM7SP\n        - .IAR_high+CM7SP\n        - .IAR_size+CM7SP\n        - .IAR_tiny+CM7SP\n\n    #Target: CM7DP\n    - layer: ../Layer/Target/CM7DP/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM7DP\n        - .AC6_mid+CM7DP\n        - .AC6_high+CM7DP\n        - .AC6_size+CM7DP\n        - .AC6_tiny+CM7DP\n        - .GCC_low+CM7DP\n        - .GCC_mid+CM7DP\n        - .GCC_high+CM7DP\n        - .GCC_size+CM7DP\n        - .GCC_tiny+CM7DP\n        - .IAR_low+CM7DP\n        - .IAR_mid+CM7DP\n        - .IAR_high+CM7DP\n        - .IAR_size+CM7DP\n        - .IAR_tiny+CM7DP\n\n    #Target: CM23\n    - layer: ../Layer/Target/CM23/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM23\n        - .AC6_mid+CM23\n        - .AC6_high+CM23\n        - .AC6_size+CM23\n        - .AC6_tiny+CM23\n        - .GCC_low+CM23\n        - .GCC_mid+CM23\n        - .GCC_high+CM23\n        - .GCC_size+CM23\n        - .GCC_tiny+CM23\n        - .IAR_low+CM23\n        - .IAR_mid+CM23\n        - .IAR_high+CM23\n        - .IAR_size+CM23\n        - .IAR_tiny+CM23\n\n    #Target: CM23S\n    - layer: ../Layer/Target/CM23S/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM23S\n        - .AC6_mid+CM23S\n        - .AC6_high+CM23S\n        - .AC6_size+CM23S\n        - .AC6_tiny+CM23S\n        - .GCC_low+CM23S\n        - .GCC_mid+CM23S\n        - .GCC_high+CM23S\n        - .GCC_size+CM23S\n        - .GCC_tiny+CM23S\n        - .IAR_low+CM23S\n        - .IAR_mid+CM23S\n        - .IAR_high+CM23S\n        - .IAR_size+CM23S\n        - .IAR_tiny+CM23S\n\n    #Target: CM23NS\n    - layer: ../Layer/Target/CM23NS/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM23NS\n        - .AC6_mid+CM23NS\n        - .AC6_high+CM23NS\n        - .AC6_size+CM23NS\n        - .AC6_tiny+CM23NS\n        - .GCC_low+CM23NS\n        - .GCC_mid+CM23NS\n        - .GCC_high+CM23NS\n        - .GCC_size+CM23NS\n        - .GCC_tiny+CM23NS\n        - .IAR_low+CM23NS\n        - .IAR_mid+CM23NS\n        - .IAR_high+CM23NS\n        - .IAR_size+CM23NS\n        - .IAR_tiny+CM23NS\n\n    #Target: CM33\n    - layer: ../Layer/Target/CM33/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM33\n        - .AC6_mid+CM33\n        - .AC6_high+CM33\n        - .AC6_size+CM33\n        - .AC6_tiny+CM33\n        - .GCC_low+CM33\n        - .GCC_mid+CM33\n        - .GCC_high+CM33\n        - .GCC_size+CM33\n        - .GCC_tiny+CM33\n        - .IAR_low+CM33\n        - .IAR_mid+CM33\n        - .IAR_high+CM33\n        - .IAR_size+CM33\n        - .IAR_tiny+CM33\n\n    #Target: CM33S\n    - layer: ../Layer/Target/CM33S/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM33S\n        - .AC6_mid+CM33S\n        - .AC6_high+CM33S\n        - .AC6_size+CM33S\n        - .AC6_tiny+CM33S\n        - .GCC_low+CM33S\n        - .GCC_mid+CM33S\n        - .GCC_high+CM33S\n        - .GCC_size+CM33S\n        - .GCC_tiny+CM33S\n        - .IAR_low+CM33S\n        - .IAR_mid+CM33S\n        - .IAR_high+CM33S\n        - .IAR_size+CM33S\n        - .IAR_tiny+CM33S\n\n    #Target: CM33NS\n    - layer: ../Layer/Target/CM33NS/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM33NS\n        - .AC6_mid+CM33NS\n        - .AC6_high+CM33NS\n        - .AC6_size+CM33NS\n        - .AC6_tiny+CM33NS\n        - .GCC_low+CM33NS\n        - .GCC_mid+CM33NS\n        - .GCC_high+CM33NS\n        - .GCC_size+CM33NS\n        - .GCC_tiny+CM33NS\n        - .IAR_low+CM33NS\n        - .IAR_mid+CM33NS\n        - .IAR_high+CM33NS\n        - .IAR_size+CM33NS\n        - .IAR_tiny+CM33NS\n\n    #Target: CM35P\n    - layer: ../Layer/Target/CM35P/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM35P\n        - .AC6_mid+CM35P\n        - .AC6_high+CM35P\n        - .AC6_size+CM35P\n        - .AC6_tiny+CM35P\n        - .GCC_low+CM35P\n        - .GCC_mid+CM35P\n        - .GCC_high+CM35P\n        - .GCC_size+CM35P\n        - .GCC_tiny+CM35P\n        - .IAR_low+CM35P\n        - .IAR_mid+CM35P\n        - .IAR_high+CM35P\n        - .IAR_size+CM35P\n        - .IAR_tiny+CM35P\n\n    #Target: CM35PS\n    - layer: ../Layer/Target/CM35PS/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM35PS\n        - .AC6_mid+CM35PS\n        - .AC6_high+CM35PS\n        - .AC6_size+CM35PS\n        - .AC6_tiny+CM35PS\n        - .GCC_low+CM35PS\n        - .GCC_mid+CM35PS\n        - .GCC_high+CM35PS\n        - .GCC_size+CM35PS\n        - .GCC_tiny+CM35PS\n        - .IAR_low+CM35PS\n        - .IAR_mid+CM35PS\n        - .IAR_high+CM35PS\n        - .IAR_size+CM35PS\n        - .IAR_tiny+CM35PS\n\n    #Target: CM35PNS\n    - layer: ../Layer/Target/CM35PNS/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM35PNS\n        - .AC6_mid+CM35PNS\n        - .AC6_high+CM35PNS\n        - .AC6_size+CM35PNS\n        - .AC6_tiny+CM35PNS\n        - .GCC_low+CM35PNS\n        - .GCC_mid+CM35PNS\n        - .GCC_high+CM35PNS\n        - .GCC_size+CM35PNS\n        - .GCC_tiny+CM35PNS\n        - .IAR_low+CM35PNS\n        - .IAR_mid+CM35PNS\n        - .IAR_high+CM35PNS\n        - .IAR_size+CM35PNS\n        - .IAR_tiny+CM35PNS\n\n    #Target: CM55S\n    - layer: ../Layer/Target/CM55S/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM55S\n        - .AC6_mid+CM55S\n        - .AC6_high+CM55S\n        - .AC6_size+CM55S\n        - .AC6_tiny+CM55S\n        - .GCC_low+CM55S\n        - .GCC_mid+CM55S\n        - .GCC_high+CM55S\n        - .GCC_size+CM55S\n        - .GCC_tiny+CM55S\n        - .IAR_low+CM55S\n        - .IAR_mid+CM55S\n        - .IAR_high+CM55S\n        - .IAR_size+CM55S\n        - .IAR_tiny+CM55S\n\n    #Target: CM55NS\n    - layer: ../Layer/Target/CM55NS/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM55NS\n        - .AC6_mid+CM55NS\n        - .AC6_high+CM55NS\n        - .AC6_size+CM55NS\n        - .AC6_tiny+CM55NS\n        - .GCC_low+CM55NS\n        - .GCC_mid+CM55NS\n        - .GCC_high+CM55NS\n        - .GCC_size+CM55NS\n        - .GCC_tiny+CM55NS\n        - .IAR_low+CM55NS\n        - .IAR_mid+CM55NS\n        - .IAR_high+CM55NS\n        - .IAR_size+CM55NS\n        - .IAR_tiny+CM55NS\n\n    #Target: CM85S\n    - layer: ../Layer/Target/CM85S/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM85S\n        - .AC6_mid+CM85S\n        - .AC6_high+CM85S\n        - .AC6_size+CM85S\n        - .AC6_tiny+CM85S\n        - .GCC_low+CM85S\n        - .GCC_mid+CM85S\n        - .GCC_high+CM85S\n        - .GCC_size+CM85S\n        - .GCC_tiny+CM85S\n        - .IAR_low+CM85S\n        - .IAR_mid+CM85S\n        - .IAR_high+CM85S\n        - .IAR_size+CM85S\n        - .IAR_tiny+CM85S\n\n    #Target: CM85NS\n    - layer: ../Layer/Target/CM85NS/Target.clayer.yml\n      for-context:\n        - .AC6_low+CM85NS\n        - .AC6_mid+CM85NS\n        - .AC6_high+CM85NS\n        - .AC6_size+CM85NS\n        - .AC6_tiny+CM85NS\n        - .GCC_low+CM85NS\n        - .GCC_mid+CM85NS\n        - .GCC_high+CM85NS\n        - .GCC_size+CM85NS\n        - .GCC_tiny+CM85NS\n        - .IAR_low+CM85NS\n        - .IAR_mid+CM85NS\n        - .IAR_high+CM85NS\n        - .IAR_size+CM85NS\n        - .IAR_tiny+CM85NS\n\n    #Target: CA5\n    - layer: ../Layer/Target/CA5/Target.clayer.yml\n      for-context:\n        - .AC6_low+CA5\n        - .AC6_mid+CA5\n        - .AC6_high+CA5\n        - .AC6_size+CA5\n        - .AC6_tiny+CA5\n        - .GCC_low+CA5\n        - .GCC_mid+CA5\n        - .GCC_high+CA5\n        - .GCC_size+CA5\n        - .GCC_tiny+CA5\n        - .IAR_low+CA5\n        - .IAR_mid+CA5\n        - .IAR_high+CA5\n        - .IAR_size+CA5\n        - .IAR_tiny+CA5\n\n    #Target: CA7\n    - layer: ../Layer/Target/CA7/Target.clayer.yml\n      for-context:\n        - .AC6_low+CA7\n        - .AC6_mid+CA7\n        - .AC6_high+CA7\n        - .AC6_size+CA7\n        - .AC6_tiny+CA7\n        - .GCC_low+CA7\n        - .GCC_mid+CA7\n        - .GCC_high+CA7\n        - .GCC_size+CA7\n        - .GCC_tiny+CA7\n        - .IAR_low+CA7\n        - .IAR_mid+CA7\n        - .IAR_high+CA7\n        - .IAR_size+CA7\n        - .IAR_tiny+CA7\n\n    #Target: CA9\n    - layer: ../Layer/Target/CA9/Target.clayer.yml\n      for-context:\n        - .AC6_low+CA9\n        - .AC6_mid+CA9\n        - .AC6_high+CA9\n        - .AC6_size+CA9\n        - .AC6_tiny+CA9\n        - .GCC_low+CA9\n        - .GCC_mid+CA9\n        - .GCC_high+CA9\n        - .GCC_size+CA9\n        - .GCC_tiny+CA9\n        - .IAR_low+CA9\n        - .IAR_mid+CA9\n        - .IAR_high+CA9\n        - .IAR_size+CA9\n        - .IAR_tiny+CA9\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Project/Validation.csolution.yml",
    "content": "# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/1.3.0/tools/projmgr/schemas/csolution.schema.json\n\nsolution:\n  packs:\n    - pack: ARM::CMSIS\n      path: ../../../\n\n  misc:\n    - for-compiler: AC6\n      C: [-std=c99, -gdwarf-4, -ffunction-sections]\n      Link: [--entry=Reset_Handler, --symbols, --map]\n    - for-compiler: GCC\n      C: [-std=gnu99, -gdwarf-2, -ffunction-sections, -fdata-sections]\n      Link: [--specs=nano.specs, --specs=rdimon.specs]\n    - for-compiler: IAR\n      Link: [--semihosting]\n\n  target-types:\n    #CM0\n    - type: CM0\n      device: ARMCM0\n\n    #CM0plus\n    - type: CM0plus\n      device: ARMCM0P\n\n    #CM3\n    - type: CM3\n      device: ARMCM3\n\n    #CM4\n    - type: CM4\n      device: ARMCM4\n\n    #CM4FP\n    - type: CM4FP\n      device: ARMCM4_FP\n\n    #CM7\n    - type: CM7\n      device: ARMCM7\n\n    #CM7SP\n    - type: CM7SP\n      device: ARMCM7_SP\n\n    #CM7DP\n    - type: CM7DP\n      device: ARMCM7_DP\n\n    #CM23\n    - type: CM23\n      device: ARMCM23\n      processor:\n        trustzone: off\n\n     #CM23S\n    - type: CM23S\n      device: ARMCM23_TZ\n      processor:\n        trustzone: secure\n\n     #CM23NS\n    - type: CM23NS\n      device: ARMCM23_TZ\n      processor:\n        trustzone: non-secure\n\n    #CM33\n    - type: CM33\n      device: ARMCM33_DSP_FP\n      processor:\n        trustzone: off\n\n     #CM33S\n    - type: CM33S\n      device: ARMCM33_DSP_FP_TZ\n      processor:\n        trustzone: secure\n\n     #CM33NS\n    - type: CM33NS\n      device: ARMCM33_DSP_FP_TZ\n      processor:\n        trustzone: non-secure\n\n    #CM35P\n    - type: CM35P\n      device: ARMCM35P_DSP_FP\n      processor:\n        trustzone: off\n\n     #CM35PS\n    - type: CM35PS\n      device: ARMCM35P_DSP_FP_TZ\n      processor:\n        trustzone: secure\n\n     #CM35PNS\n    - type: CM35PNS\n      device: ARMCM35P_DSP_FP_TZ\n      processor:\n        trustzone: non-secure\n\n     #CM55S\n    - type: CM55S\n      device: ARMCM55\n      processor:\n        trustzone: secure\n\n     #CM55NS\n    - type: CM55NS\n      device: ARMCM55\n      processor:\n        trustzone: non-secure\n\n     #CM85S\n    - type: CM85S\n      device: ARMCM85\n      processor:\n        trustzone: secure\n\n     #CM85NS\n    - type: CM85NS\n      device: ARMCM85\n      processor:\n        trustzone: non-secure\n\n    #CA5\n    - type: CA5\n      device: ARMCA5\n\n    #CA7\n    - type: CA7\n      device: ARMCA7\n\n    #CA9\n    - type: CA9\n      device: ARMCA9\n\n  build-types:\n  #AC6_low, AC6_mid, AC6_high, AC6_size, AC6_OZ,\n    - type: AC6_low\n      compiler: AC6\n      misc:\n        - for-compiler: AC6\n          C: [-O1]\n    - type: AC6_mid\n      compiler: AC6\n      misc:\n        - for-compiler: AC6\n          C: [-O2]\n    - type: AC6_high\n      compiler: AC6\n      misc:\n        - for-compiler: AC6\n          C: [-O3]\n    - type: AC6_size\n      compiler: AC6\n      misc:\n        - for-compiler: AC6\n          C: [-Os]\n    - type: AC6_tiny\n      compiler: AC6\n      misc:\n        - for-compiler: AC6\n          C: [-Oz]\n  #GCC_low, GCC_mid, GCC_high, GCC_size, GCC_OZ,\n    - type: GCC_low\n      compiler: GCC\n      misc:\n        - for-compiler: GCC\n          C: [-O1]\n    - type: GCC_mid\n      compiler: GCC\n      misc:\n        - for-compiler: GCC\n          C: [-O2]\n    - type: GCC_high\n      compiler: GCC\n      misc:\n        - for-compiler: GCC\n          C: [-O3]\n    - type: GCC_size\n      compiler: GCC\n      misc:\n        - for-compiler: GCC\n          C: [-Os]\n    - type: GCC_tiny\n      compiler: GCC\n      misc:\n        - for-compiler: GCC\n          C: [-Ofast]\n  #IAR_low\n    - type: IAR_low\n      compiler: IAR\n      misc:\n        - for-compiler: IAR\n          C: [-Ol, --dlib_config DLib_Config_Full.h]\n    - type: IAR_mid\n      compiler: IAR\n      misc:\n        - for-compiler: IAR\n          C: [-Om, --dlib_config DLib_Config_Full.h]\n    - type: IAR_high\n      compiler: IAR\n      misc:\n        - for-compiler: IAR\n          C: [-Oh, --dlib_config DLib_Config_Full.h]\n    - type: IAR_size\n      compiler: IAR\n      misc:\n        - for-compiler: IAR\n          C: [-Ohz, --dlib_config DLib_Config_Full.h]\n    - type: IAR_tiny\n      compiler: IAR\n      misc:\n        - for-compiler: IAR\n          C: [-Ohs, --dlib_config DLib_Config_Full.h]\n\n  projects:\n    - project: ./Validation.cproject.yml\n\n    - project: ./Bootloader.cproject.yml\n      for-context:\n        - +CM23S\n        - +CM33S\n        - +CM35PS\n        - +CM55S\n        - +CM85S\n\n  output-dirs:\n    cprjdir: ./$Project$.$BuildType$+$TargetType$\n    intdir:  ./$Project$.$BuildType$+$TargetType$/intdir\n    outdir:  ./$Project$.$BuildType$+$TargetType$/outdir\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Project/avh.yml",
    "content": "name: \"RTOS2 Validation\"\nworkdir: ../../../\nbackend:\n  aws:\n    ami-version: ~=1.3\n    instance-type: t2.micro\nupload:\n  - ARM.CMSIS.pdsc\n  - CMSIS/Core/**/*\n  - CMSIS/Core_A/**/*\n  - CMSIS/CoreValidation/**/*\n  - -:CMSIS/CoreValidation/Project/Core_Validation-*.zip\n  - -:CMSIS/CoreValidation/Project/Core_Validation-*.junit\n  - -:CMSIS/CoreValidation/Project/Validation.*/**/*\n  - -:CMSIS/CoreValidation/Project/Bootloader.*/**/*\n  - Device/ARM/**/*\nsteps:\n  - run: |\n      wget https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases/download/1.5.0/cmsis-toolbox.sh\n      chmod +x cmsis-toolbox.sh\n      sudo ./cmsis-toolbox.sh <<EOI\n      /opt/ctools\n      $CMSIS_PACK_ROOT\n      $(dirname $(which armclang 2>/dev/null))\n      $(dirname $(which armcc 2>/dev/null))\n      $(dirname $(which arm-none-eabi-gcc 2>/dev/null))\n\n      EOI\n      echo \"cpackget : $(which cpackget)\"\n      echo \"csolution: $(which csolution)\"\n      echo \"cbuild   : $(which cbuild)\"\n  - run: |\n      pip install -r requirements.txt 2>&1\n  - run: |\n      cd CMSIS/CoreValidation/Project\n      python build.py --verbose -c AC6 -c GCC -d \"CM[047]*\" -d \"CM[23]3*\" build run 2>&1 || echo \"Something failed!\"\ndownload:\n  - CMSIS/CoreValidation/Project/Core_Validation-*.zip\n  - CMSIS/CoreValidation/Project/Core_Validation-*.junit\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Project/build.py",
    "content": "#!/usr/bin/python\n# -*- coding: utf-8 -*-\n\nimport logging\n\nfrom datetime import datetime\nfrom enum import Enum\nfrom glob import glob, iglob\nfrom pathlib import Path\n\nfrom lxml.etree import XMLSyntaxError\nfrom zipfile import ZipFile\n\nfrom matrix_runner import main, matrix_axis, matrix_action, matrix_command, matrix_filter, \\\n    ConsoleReport, CropReport, TransformReport, JUnitReport\n\n\n@matrix_axis(\"device\", \"d\", \"Device(s) to be considered.\")\nclass DeviceAxis(Enum):\n    CM0 = ('Cortex-M0', 'CM0')\n    CM0plus = ('Cortex-M0plus', 'CM0plus')\n    CM3 = ('Cortex-M3', 'CM3')\n    CM4 = ('Cortex-M4', 'CM4')\n    CM4FP = ('Cortex-M4FP', 'CM4FP')\n    CM7 = ('Cortex-M7', 'CM7')\n    CM7SP = ('Cortex-M7SP', 'CM7SP')\n    CM7DP = ('Cortex-M7DP', 'CM7DP')\n    CM23 = ('Cortex-M23', 'CM23')\n    CM23S = ('Cortex-M23S', 'CM23S')\n    CM23NS = ('Cortex-M23NS', 'CM23NS')\n    CM33 = ('Cortex-M33', 'CM33')\n    CM33S = ('Cortex-M33S', 'CM33S')\n    CM33NS = ('Cortex-M33NS', 'CM33NS')\n    CM35P = ('Cortex-M35P', 'CM35P')\n    CM35PS = ('Cortex-M35PS', 'CM35PS')\n    CM35PNS = ('Cortex-M35PNS', 'CM35PNS')\n    CM55S = ('Cortex-M55S', 'CM55S')\n    CM55NS = ('Cortex-M55NS', 'CM55NS')\n    CM85S = ('Cortex-M85S', 'CM85S')\n    CM85NS = ('Cortex-M85NS', 'CM85NS')\n    CA5 = ('Cortex-A5', 'CA5')\n    CA7 = ('Cortex-A7', 'CA7')\n    CA9 = ('Cortex-A9', 'CA9')\n#    CA5NEON = ('Cortex-A5neon', 'CA5neon')\n#    CA7NEON = ('Cortex-A7neon', 'CA7neon')\n#    CA9NEON = ('Cortex-A9neon', 'CA9neon')\n\n    def has_bl(self):\n        return self in [\n            DeviceAxis.CM23NS,\n            DeviceAxis.CM33NS,\n            DeviceAxis.CM35PNS,\n            DeviceAxis.CM55NS,\n            DeviceAxis.CM85NS\n        ]\n\n    @property\n    def bl_device(self):\n        bld = {\n            DeviceAxis.CM23NS: 'CM23S',\n            DeviceAxis.CM33NS: 'CM33S',\n            DeviceAxis.CM35PNS: 'CM35PS',\n            DeviceAxis.CM55NS: 'CM55S',\n            DeviceAxis.CM85NS: 'CM85S'\n        }\n        return bld[self]\n\n\n@matrix_axis(\"compiler\", \"c\", \"Compiler(s) to be considered.\")\nclass CompilerAxis(Enum):\n    AC6 = ('AC6')\n    AC6LTM = ('AC6LTM')\n    GCC = ('GCC')\n    IAR = ('IAR')\n\n    @property\n    def image_ext(self):\n        ext = {\n            CompilerAxis.AC6: 'axf',\n            CompilerAxis.AC6LTM: 'axf',\n            CompilerAxis.GCC: 'elf',\n            CompilerAxis.IAR: 'elf'\n        }\n        return ext[self]\n\n\n@matrix_axis(\"optimize\", \"o\", \"Optimization level(s) to be considered.\")\nclass OptimizationAxis(Enum):\n    LOW = ('low', 'O1')\n    MID = ('mid', 'O2')\n    HIGH = ('high', 'Ofast')\n    SIZE = ('size', 'Os')\n    TINY = ('tiny', 'Oz')\n\n\nMODEL_EXECUTABLE = {\n    DeviceAxis.CM0: (\"VHT_MPS2_Cortex-M0\", []),\n    DeviceAxis.CM0plus: (\"VHT_MPS2_Cortex-M0plus\", []),\n    DeviceAxis.CM3: (\"VHT_MPS2_Cortex-M3\", []),\n    DeviceAxis.CM4: (\"VHT_MPS2_Cortex-M4\", []),\n    DeviceAxis.CM4FP: (\"VHT_MPS2_Cortex-M4\", []),\n    DeviceAxis.CM7: (\"VHT_MPS2_Cortex-M7\", []),\n    DeviceAxis.CM7DP: (\"VHT_MPS2_Cortex-M7\", []),\n    DeviceAxis.CM7SP: (\"VHT_MPS2_Cortex-M7\", []),\n    DeviceAxis.CM23: (\"VHT_MPS2_Cortex-M23\", []),\n    DeviceAxis.CM23S: (\"VHT_MPS2_Cortex-M23\", []),\n    DeviceAxis.CM23NS: (\"VHT_MPS2_Cortex-M23\", []),\n    DeviceAxis.CM33: (\"VHT_MPS2_Cortex-M33\", []),\n    DeviceAxis.CM33S: (\"VHT_MPS2_Cortex-M33\", []),\n    DeviceAxis.CM33NS: (\"VHT_MPS2_Cortex-M33\", []),\n    DeviceAxis.CM35P: (\"VHT_MPS2_Cortex-M35P\", []),\n    DeviceAxis.CM35PS: (\"VHT_MPS2_Cortex-M35P\", []),\n    DeviceAxis.CM35PNS: (\"VHT_MPS2_Cortex-M35P\", []),\n    DeviceAxis.CM55S: (\"VHT_MPS2_Cortex-M55\", []),\n    DeviceAxis.CM55NS: (\"VHT_MPS2_Cortex-M55\", []),\n    DeviceAxis.CM85S: (\"VHT_MPS2_Cortex-M85\", []),\n    DeviceAxis.CM85NS: (\"VHT_MPS2_Cortex-M85\", []),\n    DeviceAxis.CA5: (\"FVP_VE_Cortex-A5x1\", []),\n    DeviceAxis.CA7: (\"FVP_VE_Cortex-A7x1\", []),\n    DeviceAxis.CA9: (\"FVP_VE_Cortex-A9x1\", []),\n#    DeviceAxis.CA5NEON: (\"FVP_VE_Cortex-A5x1\", []),\n#    DeviceAxis.CA7NEON: (\"FVP_VE_Cortex-A7x1\", []),\n#    DeviceAxis.CA9NEON: (\"FVP_VE_Cortex-A9x1\", [])\n}\n\ndef config_suffix(config, timestamp=True):\n    suffix = f\"{config.compiler[0]}-{config.optimize[0]}-{config.device[1]}\"\n    if timestamp:\n        suffix += f\"-{datetime.now().strftime('%Y%m%d%H%M%S')}\"\n    return suffix\n\n\ndef image_name(config):\n    return f\"Validation\"\n\n\ndef project_name(config):\n    return f\"Validation.{config.compiler}_{config.optimize}+{config.device[1]}\"\n\n\ndef bl_image_name(config):\n    return f\"Bootloader\"\n\n\ndef bl_project_name(config):\n    return f\"Bootloader.{config.compiler}_{config.optimize}+{config.device.bl_device}\"\n\n\ndef output_dir(config):\n    return \"outdir\"\n\n\ndef bl_output_dir(config):\n    return \"outdir\"\n\n\ndef model_config(config):\n    return f\"../Layer/Target/{config.device[1]}/model_config.txt\"\n\n\n@matrix_action\ndef clean(config):\n    \"\"\"Build the selected configurations using CMSIS-Build.\"\"\"\n    yield cbuild_clean(f\"{project_name(config)}/{project_name(config)}.cprj\")\n\n\n@matrix_action\ndef build(config, results):\n    \"\"\"Build the selected configurations using CMSIS-Build.\"\"\"\n\n    if config.device.has_bl():\n        logging.info(\"Compiling Bootloader...\")\n        yield csolution(f\"{bl_project_name(config)}\")\n        yield cbuild(f\"{bl_project_name(config)}/{bl_project_name(config)}.cprj\")\n\n    logging.info(\"Compiling Tests...\")\n\n    if config.compiler == CompilerAxis.GCC and  config.device.match(\"CA*\"):\n        ldfile = Path(f\"{project_name(config)}/RTE/Device/ARM{config.device[1]}/ARM{config.device[1]}.ld\")\n        infile = ldfile.replace(ldfile.with_suffix('.ld.in'))\n        yield preprocess(infile, ldfile)\n\n    yield csolution(f\"{project_name(config)}\")\n    yield cbuild(f\"{project_name(config)}/{project_name(config)}.cprj\")\n\n    if not all(r.success for r in results):\n        return\n\n    file = f\"Core_Validation-{config_suffix(config)}.zip\"\n    logging.info(f\"Archiving build output to {file}...\")\n    with ZipFile(file, \"w\") as archive:\n        for content in iglob(f\"{project_name(config)}/**/*\", recursive=True):\n            if Path(content).is_file():\n                archive.write(content)\n\n\n@matrix_action\ndef extract(config):\n    \"\"\"Extract the latest build archive.\"\"\"\n    archives = sorted(glob(f\"RTOS2_Validation-{config_suffix(config, timestamp=False)}-*.zip\"), reverse=True)\n    yield unzip(archives[0])\n\n\n@matrix_action\ndef run(config, results):\n    \"\"\"Run the selected configurations.\"\"\"\n    logging.info(\"Running Core Validation on Arm model ...\")\n    yield model_exec(config)\n\n    try:\n        results[0].test_report.write(f\"Core_Validation-{config_suffix(config)}.junit\")\n    except RuntimeError as e:\n        if isinstance(e.__cause__, XMLSyntaxError):\n            logging.error(\"No valid test report found in model output!\")\n        else:\n            logging.exception(e)\n\n\n@matrix_command()\ndef cbuild_clean(project):\n    return [\"cbuild\", \"-c\", project]\n\n\n@matrix_command()\ndef unzip(archive):\n    return [\"bash\", \"-c\", f\"unzip {archive}\"]\n\n\n@matrix_command()\ndef preprocess(infile, outfile):\n    return [\"arm-none-eabi-gcc\", \"-xc\", \"-E\", infile, \"-P\", \"-o\", outfile]\n\n@matrix_command()\ndef csolution(project):\n    return [\"csolution\", \"convert\", \"-s\", \"Validation.csolution.yml\", \"-c\", project]\n\n@matrix_command()\ndef cbuild(project):\n    return [\"cbuild\", project]\n\n\n@matrix_command(test_report=ConsoleReport() |\n                            CropReport('<\\?xml version=\"1.0\"\\?>', '</report>') |\n                            TransformReport('validation.xsl') |\n                            JUnitReport(title=lambda title, result: f\"{result.command.config.compiler}.\"\n                                                                    f\"{result.command.config.optimize}.\"\n                                                                    f\"{result.command.config.device}.\"\n                                                                    f\"{title}\"))\ndef model_exec(config):\n    cmdline = [MODEL_EXECUTABLE[config.device][0], \"-q\", \"--simlimit\", 100, \"-f\", model_config(config)]\n    cmdline += MODEL_EXECUTABLE[config.device][1]\n    cmdline += [\"-a\", f\"{project_name(config)}/{output_dir(config)}/{image_name(config)}.{config.compiler.image_ext}\"]\n    if config.device.has_bl():\n        cmdline += [\"-a\", f\"{bl_project_name(config)}/{bl_output_dir(config)}/{bl_image_name(config)}.{config.compiler.image_ext}\"]\n    return cmdline\n\n\nif __name__ == \"__main__\":\n    main()\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Project/cpacklist.txt",
    "content": "ARM.CMSIS.5.9.0\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Project/requirements.txt",
    "content": "# -*- coding: utf-8 -*-\n#\n# Python requirements for build.py script\n#\npython-matrix-runner~=1.0\nlxml~=4.8\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Project/validation.xsl",
    "content": "<xsl:stylesheet version=\"1.0\" xmlns:xsl=\"http://www.w3.org/1999/XSL/Transform\">\n    <xsl:output method=\"xml\" indent=\"yes\"/>\n    <xsl:template match=\"/\">\n        <testsuites>\n            <xsl:variable name=\"buildName\" select=\"//report/test/title\"/>\n            <xsl:variable name=\"numberOfTests\" select=\"//report/test/summary/tcnt\"/>\n            <xsl:variable name=\"numberOfExecutes\" select=\"//report/test/summary/exec\"/>\n            <xsl:variable name=\"numberOfPasses\" select=\"//report/test/summary/pass\"/>\n            <xsl:variable name=\"numberOfFailures\" select=\"//report/test/summary/fail\"/>\n\t\t\t<xsl:variable name=\"numberOfSkips\" select=\"$numberOfTests - $numberOfExecutes\"/>\n\t\t\t<xsl:variable name=\"numberOfErrors\" select=\"0\"/>\n            <testsuite name=\"{$buildName}\"\n                       tests=\"{$numberOfTests}\" time=\"0\"\n                       failures=\"{$numberOfFailures}\" errors=\"{$numberOfErrors}\"\n                       skipped=\"{$numberOfSkips}\">\n                <xsl:for-each select=\"//report/test/test_cases/tc\">\n                    <xsl:variable name=\"testName\" select=\"func\"/>\n                    <xsl:variable name=\"status\" select=\"res\"/>\n                    <testcase name=\"{$testName}\">\n                        <xsl:choose>\n                            <xsl:when test=\"res='PASSED'\"/>\n\t\t\t\t\t\t\t<xsl:when test=\"res='NOT EXECUTED'\">\n\t\t\t\t\t\t\t\t<skipped/>\n\t\t\t\t\t\t\t</xsl:when>\n                            <xsl:otherwise>\n                                <failure>\n                                    <xsl:for-each select=\"dbgi/detail\">\n                                        <xsl:variable name=\"file\" select=\"module\"/>\n                                        <xsl:variable name=\"line\" select=\"line\"/>\n                                        <xsl:text>&#10;        </xsl:text>\n                                        <xsl:value-of select=\"$file\"/>:<xsl:value-of select=\"$line\"/>\n                                    </xsl:for-each>\n                                    <xsl:text>&#10;      </xsl:text>\n                                 </failure>\n                            </xsl:otherwise>\n                        </xsl:choose>\n                    </testcase>\n                </xsl:for-each>\n            </testsuite>\n        </testsuites>\n    </xsl:template>\n</xsl:stylesheet>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/README.md",
    "content": "# CMSIS-Core Validation\n\nThis folder contains a test suite that validates CMSIS-Core implementations. It uses [**Fixed Virtual Platforms**](https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms) to run tests to verify correct operation of the CMSIS-Core functionality on various Arm Cortex based processors.\n\n## Folder structure\n\n```txt\n    📂 CoreValidation\n    ┣ 📂 Include        Include files for test cases etc.\n    ┣ 📂 Layer          Layers for creating the projects.\n    ┣ 📂 Project        Solution and project files to build tests for various configurations.\n    ┗ 📂 Source         Test case source code.\n```\n\n## Test matrix\n\nCurrently, the following build configurations are provided:\n\n1. Compiler\n   - Arm Compiler 6 (AC6)\n   - GNU Compiler (GCC)\n   - IAR Compiler (IAR)\n2. Devices\n   - Cortex-M0\n   - Cortex-M0+\n   - Cortex-M3\n   - Cortex-M4\n     - w/o FPU\n     - with FPU\n   - Cortex-M7\n     - w/o FPU\n     - with SP FPU\n     - with DP FPU\n   - Cortex-M23\n     - w/o security extensions (TrustZone)\n     - in secure mode\n     - in non-secure mode\n   - Cortex-M33 (with FPU and DSP extensions)\n     - w/o security extensions (TrustZone)\n     - in secure mode\n     - in non-secure mode\n   - Cortex-M35P (with FPU and DSP extensions)\n     - w/o security extensions (TrustZone)\n     - in secure mode\n     - in non-secure mode\n   - Cortex-M55 (with FPU and DSP extensions)\n     - in secure mode\n     - in non-secure mode\n   - Cortex-M85 (with FPU and DSP extensions)\n     - in secure mode\n     - in non-secure mode\n   - Cortex-A5\n     - w/o NEON extensions\n   - Cortex-A7\n     - w/o NEON extensions\n   - Cortex-A9\n     - w/o NEON extensions\n3. Optimization Levels\n   - Low\n     - AC6: `-O1`\n     - GCC: `-O1`\n     - IAR: `-Ol`\n   - Mid\n     - AC6: `-O2`\n     - GCC: `-O2`\n     - IAR: `-Om`\n   - High\n     - AC6: `-O3`\n     - GCC: `-O3`\n     - IAR: `-Oh`\n   - Size\n     - AC6: `-Os`\n     - GCC: `-Os`\n     - IAR: `-Ohz`\n   - Tiny\n     - AC6: `-Oz`\n     - GCC: `-Ofast`\n     - IAR: `-Ohs`\n\n## Prerequisites\n\nThe following tools are required to build and run the CoreValidation tests:\n\n- [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/cmsis-toolbox/releases) 1.3.0 or higher\n- CMake\n- Ninja build\n- Arm Compiler 6\n- GNU Compiler\n- IAR Compiler\n- Python 3.8 or higher\n- Arm Virtual Hardware Models\n\nThe executables need to be present on the `PATH`.\n\nInstall the Python packages required by `build.py`:\n\n```bash\nCMSIS_5/CMSIS/CoreValidation/Project $ pip install -r requirements.txt\n```\n\n## Build and run\n\nTo build and run the CoreValidation tests for one or more configurations use the following command line.\nSelect the `<compiler>`, `<device>`, and `optimize` level to `build` and `run` for.\n\n```bash\nCMSIS_5/CMSIS/CoreValidation/Project $ ./build.py -c <compiler> -d <device> -o <optimize> [build] [run]\n```\n\nFor example, build and run the tests using GCC for Cortex-M3 with low optimization, execute:\n\n```bash\nCMSIS_5/CMSIS/CoreValidation/Project $ ./build.py -c GCC -d CM3 -o low build run\n[GCC][Cortex-M3][low](build:csolution) csolution convert -s Validation.csolution.yml -c Validation.GCC_low+CM3\n[GCC][Cortex-M3][low](build:csolution) csolution succeeded with exit code 0\n[GCC][Cortex-M3][low](build:cbuild) cbuild Validation.GCC_low+CM3/Validation.GCC_low+CM3.cprj\n[GCC][Cortex-M3][low](build:cbuild) cbuild succeeded with exit code 0\n[GCC][Cortex-M3][low](run:model_exec) VHT_MPS2_Cortex-M3 -q --simlimit 100 -f ../Layer/Target/CM3/model_config.txt -a Validation.GCC_low+CM3/Validation.GCC_low+CM3_outdir/Validation.GCC_low+CM3.elf\n[GCC][Cortex-M3][low](run:model_exec) VHT_MPS2_Cortex-M3 succeeded with exit code 0\n\nMatrix Summary\n==============\n\ncompiler    device     optimize    build    clean    extract    run\n----------  ---------  ----------  -------  -------  ---------  -----\nGCC         Cortex-M3  low         success  (skip)   (skip)     35/35\n```\n\nThe full test report is written to `Core_Validation-GCC-low-CM3-<timestamp>.junit` file.\n\n## License\n\n[![License](https://img.shields.io/badge/License-Apache_2.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CAL1Cache.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_CAL1Cache.c \n *      Purpose:      CMSIS CORE validation tests implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2017 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\"\n\n/*-----------------------------------------------------------------------------\n *      Test implementation\n *----------------------------------------------------------------------------*/\n\n/*-----------------------------------------------------------------------------\n *      Test cases\n *----------------------------------------------------------------------------*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CAL1Cache_EnDisable(void) {\n  \n  uint32_t orig = __get_SCTLR();\n  \n  L1C_EnableCaches();\n  \n  uint32_t sctlr = __get_SCTLR();\n  ASSERT_TRUE((sctlr  & SCTLR_I_Msk) == SCTLR_I_Msk);\n  ASSERT_TRUE((sctlr  & SCTLR_C_Msk) == SCTLR_C_Msk);\n  \n  L1C_CleanDCacheAll();\n  L1C_DisableCaches();\n  \n  sctlr = __get_SCTLR();\n  ASSERT_TRUE((sctlr & SCTLR_I_Msk) == 0U);\n  ASSERT_TRUE((sctlr & SCTLR_C_Msk) == 0U);\n  \n  __set_SCTLR(orig);\n  __ISB();\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CAL1Cache_EnDisableBTAC(void) {\n  uint32_t orig = __get_SCTLR();\n  \n  L1C_EnableBTAC();\n  \n  uint32_t sctlr = __get_SCTLR();\n  ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);\n  \n  L1C_DisableBTAC();\n  \n  sctlr = __get_SCTLR();\n#if __CORTEX_A == 7\n  // On Cortex-A7 SCTLR_Z is RAO/WI.\n  ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);\n#else\n  ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == 0U);\n#endif\n\n  __set_SCTLR(orig);\n  __ISB();\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CAL1Cache_log2_up(void) {\n  uint8_t log2 = __log2_up(0U);\n  ASSERT_TRUE(log2 == 0U);\n  \n  log2 = __log2_up(1U);\n  ASSERT_TRUE(log2 == 0U);\n\n  log2 = __log2_up(2U);\n  ASSERT_TRUE(log2 == 1U);\n\n  log2 = __log2_up(3U);\n  ASSERT_TRUE(log2 == 2U);\n\n  log2 = __log2_up(4U);\n  ASSERT_TRUE(log2 == 2U);\n\n  log2 = __log2_up(0x80000000U);\n  ASSERT_TRUE(log2 == 31U);\n\n  log2 = __log2_up(0x80000001U);\n  ASSERT_TRUE(log2 == 32U);\n  \n  log2 = __log2_up(0xFFFFFFFFU);\n  ASSERT_TRUE(log2 == 32U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CAL1Cache_InvalidateDCacheAll(void) {\n  \n  /* setup */\n  uint32_t orig = __get_SCTLR();\n  volatile uint32_t value = 0x0815U;\n\n  L1C_EnableCaches();\n\n  L1C_CleanDCacheAll();\n\n  /* test cached value gets lost */\n  \n  // WHEN a value is written\n  value = 0x4711U;\n  \n  // ... and the cache is invalidated\n  L1C_InvalidateDCacheAll();\n\n  // ... and the cache is disabled\n  L1C_DisableCaches();\n\n  // THEN the new value has been lost\n  ASSERT_TRUE(value == 0x0815U);\n  \n  /* tear down */\n  L1C_InvalidateDCacheAll();\n  __set_SCTLR(orig);\n  __ISB();\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CAL1Cache_CleanDCacheAll(void) {\n  /* setup */\n  uint32_t orig = __get_SCTLR();\n  uint32_t value = 0x0815U;\n\n  L1C_EnableCaches();\n\n  L1C_CleanDCacheAll();\n  \n  /* test cached value is preserved */\n  \n  // WHEN a value is written\n  value = 0x4711U;\n  \n  // ... and the cache is cleaned\n  L1C_CleanDCacheAll();\n  \n  // ... and the cache is disabled\n  L1C_DisableCaches();\n  \n  // THEN the new value is preserved\n  ASSERT_TRUE(value == 0x4711U);\n  \n  /* tear down */\n  L1C_InvalidateDCacheAll();\n  __set_SCTLR(orig);\n  __ISB();\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CAL1Cache_CleanInvalidateDCacheAll(void) {\n  /* setup */\n  uint32_t orig = __get_SCTLR();\n  uint32_t value = 0x0815U;\n\n  L1C_EnableCaches();\n\n  L1C_CleanDCacheAll();\n  \n  /* test cached value is preserved */\n  \n  // WHEN a value is written\n  value = 0x4711U;\n  \n  // ... and the cache is cleaned/invalidated\n  L1C_CleanInvalidateDCacheAll();\n  \n  // ... and the cache is disabled\n  L1C_DisableCaches();\n\n  // THEN the new value is preserved\n  ASSERT_TRUE(value == 0x4711U);\n  \n  /* tear down */\n  L1C_InvalidateDCacheAll();\n  __set_SCTLR(orig);\n  __ISB();\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CML1Cache.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_CML1Cache.c \n *      Purpose:      CMSIS CORE validation tests implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2020 - 2021 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\"\n\n/*-----------------------------------------------------------------------------\n *      Test implementation\n *----------------------------------------------------------------------------*/\n\n/*-----------------------------------------------------------------------------\n *      Test cases\n *----------------------------------------------------------------------------*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CML1Cache_EnDisableICache(void) {\n#ifdef __ICACHE_PRESENT\n  SCB_EnableICache();\n  \n  ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == SCB_CCR_IC_Msk);\n  \n  SCB_DisableICache();\n\n  ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == 0U);\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CML1Cache_EnDisableDCache(void) {\n#ifdef __DCACHE_PRESENT\n  SCB_EnableDCache();\n\n  ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == SCB_CCR_DC_Msk);\n\n  SCB_DisableDCache();\n\n  ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U);\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n#ifdef __DCACHE_PRESENT\nstatic uint32_t TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[] = { 42U, 0U, 8U, 15U };\n#endif\n\nvoid TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void) {\n#ifdef __DCACHE_PRESENT\n  SCB_DisableDCache();\n  SCB_CleanDCache_by_Addr(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values, sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values)/sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[0]));\n  ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U);\n#endif\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreAFunc.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_CoreFunc.c\n *      Purpose:      CMSIS CORE validation tests implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2017 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\"\n\n/*-----------------------------------------------------------------------------\n *      Test implementation\n *----------------------------------------------------------------------------*/\n\n/*-----------------------------------------------------------------------------\n *      Test cases\n *----------------------------------------------------------------------------*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_IRQ(void) {\n  uint32_t orig = __get_CPSR();\n\n  __enable_irq();\n  uint32_t cpsr = __get_CPSR();\n  ASSERT_TRUE((cpsr & CPSR_I_Msk) == 0U);\n\n  __disable_irq();\n  cpsr = __get_CPSR();\n  ASSERT_TRUE((cpsr & CPSR_I_Msk) == CPSR_I_Msk);\n\n  __set_CPSR(orig);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_FaultIRQ(void) {\n  uint32_t orig = __get_CPSR();\n\n  __enable_fault_irq();\n  uint32_t cpsr = __get_CPSR();\n  ASSERT_TRUE((cpsr & CPSR_F_Msk) == 0U);\n\n  __disable_fault_irq();\n  cpsr = __get_CPSR();\n  ASSERT_TRUE((cpsr & CPSR_F_Msk) == CPSR_F_Msk);\n\n  __set_CPSR(orig);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_FPSCR(void) {\n\n  volatile float f1 = 47.11f;\n  volatile float f2 = 8.15f;\n  volatile float f3 = f1 / f2;\n\n  uint32_t fpscr = __get_FPSCR();\n  __set_FPSCR(fpscr);\n\n  ASSERT_TRUE(fpscr == __get_FPSCR());\n  ASSERT_TRUE((f3 < 5.781f) && (f3 > 5.780f));\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n#if defined(__CC_ARM)\n#define __SUBS(Rd, Rm, Rn) __ASM volatile(\"SUBS \" # Rd \", \" # Rm \", \" # Rn)\n#define __ADDS(Rd, Rm, Rn) __ASM volatile(\"ADDS \" # Rd \", \" # Rm \", \" # Rn)\n#elif defined( __GNUC__ ) && defined(__thumb__)\n#define __SUBS(Rd, Rm, Rn) __ASM volatile(\"SUB %0, %1, %2\" : \"=r\"(Rd) : \"r\"(Rm), \"r\"(Rn))\n#define __ADDS(Rd, Rm, Rn) __ASM volatile(\"ADD %0, %1, %2\" : \"=r\"(Rd) : \"r\"(Rm), \"r\"(Rn))\n#else\n#define __SUBS(Rd, Rm, Rn) __ASM volatile(\"SUBS %0, %1, %2\" : \"=r\"(Rd) : \"r\"(Rm), \"r\"(Rn))\n#define __ADDS(Rd, Rm, Rn) __ASM volatile(\"ADDS %0, %1, %2\" : \"=r\"(Rd) : \"r\"(Rm), \"r\"(Rn))\n#endif\n\nvoid TC_CoreAFunc_CPSR(void) {\n  uint32_t result;\n\n  uint32_t cpsr = __get_CPSR();\n  __set_CPSR(cpsr & CPSR_M_Msk);\n\n  // Check negative flag\n  int32_t Rm = 5;\n  int32_t Rn = 7;\n  __SUBS(Rm, Rm, Rn);\n  result  = __get_CPSR();\n  ASSERT_TRUE((result & CPSR_N_Msk) == CPSR_N_Msk);\n\n  // Check zero and compare flag\n  Rm = 5;\n  __SUBS(Rm, Rm, Rm);\n  result  = __get_CPSR();\n  ASSERT_TRUE((result & CPSR_Z_Msk) == CPSR_Z_Msk);\n  ASSERT_TRUE((result & CPSR_C_Msk) == CPSR_C_Msk);\n\n  // Check overflow flag\n  Rm = 5;\n  Rn = INT32_MAX;\n  __ADDS(Rm, Rm, Rn);\n  result  = __get_CPSR();\n  ASSERT_TRUE((result & CPSR_V_Msk) == CPSR_V_Msk);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_Mode(void) {\n  uint32_t mode = __get_mode();\n  __set_mode(mode);\n\n  ASSERT_TRUE(mode == __get_mode());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nstatic uint32_t TC_CoreAFunc_SP_orig;\nstatic uint32_t TC_CoreAFunc_SP_sp;\nstatic uint32_t TC_CoreAFunc_SP_result;\n\nvoid TC_CoreAFunc_SP(void) {\n  TC_CoreAFunc_SP_orig = __get_SP();\n\n  TC_CoreAFunc_SP_sp = TC_CoreAFunc_SP_orig + 0x12345678U;\n  __set_SP(TC_CoreAFunc_SP_sp);\n  TC_CoreAFunc_SP_result = __get_SP();\n\n  __set_SP(TC_CoreAFunc_SP_orig);\n\n  ASSERT_TRUE(TC_CoreAFunc_SP_result == TC_CoreAFunc_SP_sp);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nstatic uint32_t TC_CoreAFunc_SP_usr_orig;\nstatic uint32_t TC_CoreAFunc_SP_usr_sp;\nstatic uint32_t TC_CoreAFunc_SP_usr_result;\n\nvoid TC_CoreAFunc_SP_usr(void) {\n  TC_CoreAFunc_SP_usr_orig = __get_SP_usr();\n\n  TC_CoreAFunc_SP_usr_sp = TC_CoreAFunc_SP_usr_orig + 0x12345678U;\n  __set_SP(TC_CoreAFunc_SP_usr_sp);\n  TC_CoreAFunc_SP_usr_result = __get_SP_usr();\n\n  __set_SP(TC_CoreAFunc_SP_usr_orig);\n\n  ASSERT_TRUE(TC_CoreAFunc_SP_usr_result == TC_CoreAFunc_SP_usr_sp);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_FPEXC(void) {\n  uint32_t fpexc = __get_FPEXC();\n  __set_FPEXC(fpexc);\n\n  ASSERT_TRUE(fpexc == __get_FPEXC());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_ACTLR(void) {\n  uint32_t actlr = __get_ACTLR();\n  __set_ACTLR(actlr);\n\n  ASSERT_TRUE(actlr == __get_ACTLR());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_CPACR(void) {\n  uint32_t cpacr = __get_CPACR();\n  __set_CPACR(cpacr);\n\n  ASSERT_TRUE(cpacr == __get_CPACR());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_DFSR(void) {\n  uint32_t dfsr = __get_DFSR();\n  __set_DFSR(dfsr);\n\n  ASSERT_TRUE(dfsr == __get_DFSR());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_IFSR(void) {\n  uint32_t ifsr = __get_IFSR();\n  __set_IFSR(ifsr);\n\n  ASSERT_TRUE(ifsr == __get_IFSR());\n}\n\n/*0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_ISR(void) {\n  uint32_t isr = __get_ISR();\n\n  ASSERT_TRUE(isr == __get_ISR());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_CBAR(void) {\n  uint32_t cbar = __get_CBAR();\n\n  ASSERT_TRUE(cbar == __get_CBAR());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_TTBR0(void) {\n  uint32_t ttbr0 = __get_TTBR0();\n  __set_TTBR0(ttbr0);\n\n  ASSERT_TRUE(ttbr0 == __get_TTBR0());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_DACR(void) {\n  uint32_t dacr = __get_DACR();\n  __set_DACR(dacr);\n\n  ASSERT_TRUE(dacr == __get_DACR());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_SCTLR(void) {\n  uint32_t sctlr = __get_SCTLR();\n  __set_SCTLR(sctlr);\n\n  ASSERT_TRUE(sctlr == __get_SCTLR());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_ACTRL(void) {\n  uint32_t actrl = __get_ACTRL();\n  __set_ACTRL(actrl);\n\n  ASSERT_TRUE(actrl == __get_ACTRL());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_MPIDR(void) {\n  uint32_t mpidr = __get_MPIDR();\n\n  ASSERT_TRUE(mpidr == __get_MPIDR());\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nstatic uint8_t vectorRAM[32U] __attribute__((aligned(32U)));\n\nvoid TC_CoreAFunc_VBAR(void) {\n  uint32_t vbar = __get_VBAR();\n\n  memcpy(vectorRAM, (void*)vbar, sizeof(vectorRAM));\n\n  __set_VBAR((uint32_t)vectorRAM);\n  ASSERT_TRUE(((uint32_t)vectorRAM) == __get_VBAR());\n\n  __set_VBAR(vbar);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_CoreAFunc_MVBAR(void) {\n  uint32_t mvbar = __get_MVBAR();\n\n  memcpy(vectorRAM, (void*)mvbar, sizeof(vectorRAM));\n\n  __set_MVBAR((uint32_t)vectorRAM);\n  ASSERT_TRUE(((uint32_t)vectorRAM) == __get_MVBAR());\n\n  __set_MVBAR(mvbar);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n\nvoid TC_CoreAFunc_FPU_Enable(void) {\n  uint32_t fpexc = __get_FPEXC();\n  __set_FPEXC(fpexc & ~0x40000000u); // disable FPU\n\n  uint32_t cp15;\n  __get_CP(15, 0, cp15, 1, 0, 2);\n\n  cp15 &= ~0x00F00000u;\n  __set_CP(15, 0, cp15, 1, 0, 2); // disable FPU access\n\n  __FPU_Enable();\n\n  __get_CP(15, 0, cp15, 1, 0, 2);\n  ASSERT_TRUE((cp15 & 0x00F00000u) == 0x00F00000u);\n\n  fpexc = __get_FPEXC();\n  ASSERT_TRUE((fpexc & 0x40000000u) == 0x40000000u);\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreFunc.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_CoreFunc.c\n *      Purpose:      CMSIS CORE validation tests implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2023 Arm Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\"\n\n/*-----------------------------------------------------------------------------\n *      Test implementation\n *----------------------------------------------------------------------------*/\n\nstatic volatile uint32_t irqTaken = 0U;\n#if defined(__CORTEX_M) && (__CORTEX_M > 0)\nstatic volatile uint32_t irqActive = 0U;\n#endif\n\nstatic void TC_CoreFunc_EnDisIRQIRQHandler(void) {\n  ++irqTaken;\n#if defined(__CORTEX_M) && (__CORTEX_M > 0)\n  irqActive = NVIC_GetActive(Interrupt0_IRQn);\n#endif\n}\n\nstatic volatile uint32_t irqIPSR = 0U;\nstatic volatile uint32_t irqXPSR = 0U;\n\nstatic void TC_CoreFunc_IPSR_IRQHandler(void) {\n  irqIPSR = __get_IPSR();\n  irqXPSR = __get_xPSR();\n}\n\n/*-----------------------------------------------------------------------------\n *      Test cases\n *----------------------------------------------------------------------------*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_EnDisIRQ\n\\details\nCheck expected behavior of interrupt related control functions:\n- __disable_irq() and __enable_irq()\n- NVIC_EnableIRQ, NVIC_DisableIRQ,  and NVIC_GetEnableIRQ\n- NVIC_SetPendingIRQ, NVIC_ClearPendingIRQ, and NVIC_GetPendingIRQ\n- NVIC_GetActive (not on Cortex-M0/M0+)\n*/\nvoid TC_CoreFunc_EnDisIRQ (void)\n{\n  // Globally disable all interrupt servicing\n  __disable_irq();\n\n  // Enable the interrupt\n  NVIC_EnableIRQ(Interrupt0_IRQn);\n  ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) != 0U);\n\n  // Clear its pending state\n  NVIC_ClearPendingIRQ(Interrupt0_IRQn);\n  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);\n\n  // Register test interrupt handler.\n  TST_IRQHandler = TC_CoreFunc_EnDisIRQIRQHandler;\n  irqTaken = 0U;\n#if defined(__CORTEX_M) && (__CORTEX_M > 0)\n  irqActive = UINT32_MAX;\n#endif\n\n  // Set the interrupt pending state\n  NVIC_SetPendingIRQ(Interrupt0_IRQn);\n  for(uint32_t i = 10U; i > 0U; --i) {__NOP();}\n\n  // Interrupt is not taken\n  ASSERT_TRUE(irqTaken == 0U);\n  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U);\n#if defined(__CORTEX_M) && (__CORTEX_M > 0)\n  ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U);\n#endif\n\n  // Globally enable interrupt servicing\n  __enable_irq();\n\n  for(uint32_t i = 10U; i > 0U; --i) {__NOP();}\n\n  // Interrupt was taken\n  ASSERT_TRUE(irqTaken == 1U);\n#if defined(__CORTEX_M) && (__CORTEX_M > 0)\n  ASSERT_TRUE(irqActive != 0U);\n  ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U);\n#endif\n\n  // Interrupt it not pending anymore.\n  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);\n\n  // Disable interrupt\n  NVIC_DisableIRQ(Interrupt0_IRQn);\n  ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) == 0U);\n\n  // Set interrupt pending\n  NVIC_SetPendingIRQ(Interrupt0_IRQn);\n  for(uint32_t i = 10U; i > 0U; --i) {__NOP();}\n\n  // Interrupt is not taken again\n  ASSERT_TRUE(irqTaken == 1U);\n  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U);\n\n  // Clear interrupt pending\n  NVIC_ClearPendingIRQ(Interrupt0_IRQn);\n  for(uint32_t i = 10U; i > 0U; --i) {__NOP();}\n\n  // Interrupt it not pending anymore.\n  ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);\n\n  // Globally disable interrupt servicing\n  __disable_irq();\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_IRQPrio\n\\details\nCheck expected behavior of interrupt priority control functions:\n- NVIC_SetPriority, NVIC_GetPriority\n*/\nvoid TC_CoreFunc_IRQPrio (void)\n{\n  /* Test Exception Priority */\n  uint32_t orig = NVIC_GetPriority(SVCall_IRQn);\n\n  NVIC_SetPriority(SVCall_IRQn, orig+1U);\n  uint32_t prio = NVIC_GetPriority(SVCall_IRQn);\n\n  ASSERT_TRUE(prio == orig+1U);\n\n  NVIC_SetPriority(SVCall_IRQn, orig);\n\n  /* Test Interrupt Priority */\n  orig = NVIC_GetPriority(Interrupt0_IRQn);\n\n  NVIC_SetPriority(Interrupt0_IRQn, orig+1U);\n  prio = NVIC_GetPriority(Interrupt0_IRQn);\n\n  ASSERT_TRUE(prio == orig+1U);\n\n  NVIC_SetPriority(Interrupt0_IRQn, orig);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** Helper function for TC_CoreFunc_EncDecIRQPrio\n\\details\nThe helper encodes and decodes the given priority configuration.\n\\param[in] prigroup The PRIGROUP setting to be considered for encoding/decoding.\n\\param[in] pre The preempt priority value.\n\\param[in] sub The subpriority value.\n*/\nstatic void TC_CoreFunc_EncDecIRQPrio_Step(uint32_t prigroup, uint32_t pre, uint32_t sub) {\n  uint32_t prio = NVIC_EncodePriority(prigroup, pre, sub);\n\n  uint32_t ret_pre = UINT32_MAX;\n  uint32_t ret_sub = UINT32_MAX;\n\n  NVIC_DecodePriority(prio, prigroup, &ret_pre, &ret_sub);\n\n  ASSERT_TRUE(ret_pre == pre);\n  ASSERT_TRUE(ret_sub == sub);\n}\n\n/**\n\\brief Test case: TC_CoreFunc_EncDecIRQPrio\n\\details\nCheck expected behavior of interrupt priority encoding/decoding functions:\n- NVIC_EncodePriority, NVIC_DecodePriority\n*/\nvoid TC_CoreFunc_EncDecIRQPrio (void)\n{\n  /* Check only the valid range of PRIGROUP and preempt-/sub-priority values. */\n  static const uint32_t priobits = (__NVIC_PRIO_BITS > 7U) ? 7U : __NVIC_PRIO_BITS;\n  for(uint32_t prigroup = 7U-priobits; prigroup<7U; prigroup++) {\n    for(uint32_t pre = 0U; pre<(128U>>prigroup); pre++) {\n      for(uint32_t sub = 0U; sub<(256U>>(8U-__NVIC_PRIO_BITS+7U-prigroup)); sub++) {\n        TC_CoreFunc_EncDecIRQPrio_Step(prigroup, pre, sub);\n      }\n    }\n  }\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_IRQVect\n\\details\nCheck expected behavior of interrupt vector relocation functions:\n- NVIC_SetVector, NVIC_GetVector\n*/\nvoid TC_CoreFunc_IRQVect(void) {\n#if defined(__VTOR_PRESENT) && __VTOR_PRESENT\n  /* relocate vector table */\n  extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n  static VECTOR_TABLE_Type vectors[sizeof(__VECTOR_TABLE)/sizeof(__VECTOR_TABLE[0])] __ALIGNED(1024) __NO_INIT;\n  memcpy(vectors, __VECTOR_TABLE, sizeof(__VECTOR_TABLE));\n\n  const uint32_t orig_vtor = SCB->VTOR;\n  const uint32_t vtor = ((uint32_t)vectors) & SCB_VTOR_TBLOFF_Msk;\n  SCB->VTOR = vtor;\n\n  ASSERT_TRUE(vtor == SCB->VTOR);\n\n  /* check exception vectors */\n  extern void HardFault_Handler(void);\n  extern void SVC_Handler(void);\n  extern void PendSV_Handler(void);\n  extern void SysTick_Handler(void);\n\n  ASSERT_TRUE(NVIC_GetVector(HardFault_IRQn) == (uint32_t)HardFault_Handler);\n  ASSERT_TRUE(NVIC_GetVector(SVCall_IRQn) == (uint32_t)SVC_Handler);\n  ASSERT_TRUE(NVIC_GetVector(PendSV_IRQn) == (uint32_t)PendSV_Handler);\n  ASSERT_TRUE(NVIC_GetVector(SysTick_IRQn) == (uint32_t)SysTick_Handler);\n\n  /* reconfigure WDT IRQ vector */\n  extern void Interrupt0_Handler(void);\n\n  const uint32_t wdtvec = NVIC_GetVector(Interrupt0_IRQn);\n  ASSERT_TRUE(wdtvec == (uint32_t)Interrupt0_Handler);\n\n  NVIC_SetVector(Interrupt0_IRQn, wdtvec + 32U);\n\n  ASSERT_TRUE(NVIC_GetVector(Interrupt0_IRQn) == (wdtvec + 32U));\n\n  /* restore vector table */\n  SCB->VTOR = orig_vtor;\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_GetCtrl\n\\details\n- Check if __set_CONTROL and __get_CONTROL() sets/gets control register\n*/\nvoid TC_CoreFunc_Control (void) {\n  // don't use stack for this variables\n  static uint32_t orig;\n  static uint32_t ctrl;\n  static uint32_t result;\n\n  orig = __get_CONTROL();\n  ctrl = orig;\n  result = UINT32_MAX;\n\n#ifdef CONTROL_SPSEL_Msk\n  // SPSEL set to 0 (MSP)\n  ASSERT_TRUE((ctrl & CONTROL_SPSEL_Msk) == 0U);\n\n  // SPSEL set to 1 (PSP)\n  ctrl |= CONTROL_SPSEL_Msk;\n\n  // Move MSP to PSP\n  __set_PSP(__get_MSP());\n#endif\n\n  __set_CONTROL(ctrl);\n  __ISB();\n\n  result = __get_CONTROL();\n\n  __set_CONTROL(orig);\n  __ISB();\n\n  ASSERT_TRUE(result == ctrl);\n  ASSERT_TRUE(__get_CONTROL() == orig);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_IPSR\n\\details\n- Check if __get_IPSR intrinsic is available\n- Check if __get_xPSR intrinsic is available\n- Result differentiates between thread and exception modes\n*/\nvoid TC_CoreFunc_IPSR (void) {\n  uint32_t result = __get_IPSR();\n  ASSERT_TRUE(result == 0U); // Thread Mode\n\n  result = __get_xPSR();\n  ASSERT_TRUE((result & xPSR_ISR_Msk) == 0U); // Thread Mode\n\n  TST_IRQHandler = TC_CoreFunc_IPSR_IRQHandler;\n  irqIPSR = 0U;\n  irqXPSR = 0U;\n\n  NVIC_ClearPendingIRQ(Interrupt0_IRQn);\n  NVIC_EnableIRQ(Interrupt0_IRQn);\n  __enable_irq();\n\n  NVIC_SetPendingIRQ(Interrupt0_IRQn);\n  for(uint32_t i = 10U; i > 0U; --i) {__NOP();}\n\n  __disable_irq();\n  NVIC_DisableIRQ(Interrupt0_IRQn);\n\n  ASSERT_TRUE(irqIPSR != 0U); // Exception Mode\n  ASSERT_TRUE((irqXPSR & xPSR_ISR_Msk) != 0U); // Exception Mode\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n\n#if defined(__CC_ARM)\n#define SUBS(Rd, Rm, Rn) __ASM volatile(\"SUBS \" # Rd \", \" # Rm \", \" # Rn)\n#define ADDS(Rd, Rm, Rn) __ASM volatile(\"ADDS \" # Rd \", \" # Rm \", \" # Rn)\n#elif defined( __GNUC__ ) && (!defined(__ti__)) && (!defined(__ARMCC_VERSION))  && (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))\n#define SUBS(Rd, Rm, Rn) __ASM volatile(\"SUB %0, %1, %2\" : \"=r\"(Rd) : \"r\"(Rm), \"r\"(Rn) : \"cc\")\n#define ADDS(Rd, Rm, Rn) __ASM volatile(\"ADD %0, %1, %2\" : \"=r\"(Rd) : \"r\"(Rm), \"r\"(Rn) : \"cc\")\n#elif defined(_lint)\n//lint -save -e(9026) allow function-like macro\n#define SUBS(Rd, Rm, Rn) ((Rd) = (Rm) - (Rn))\n#define ADDS(Rd, Rm, Rn) ((Rd) = (Rm) + (Rn))\n//lint -restore\n#else\n#define SUBS(Rd, Rm, Rn) __ASM volatile(\"SUBS %0, %1, %2\" : \"=r\"(Rd) : \"r\"(Rm), \"r\"(Rn) : \"cc\")\n#define ADDS(Rd, Rm, Rn) __ASM volatile(\"ADDS %0, %1, %2\" : \"=r\"(Rd) : \"r\"(Rm), \"r\"(Rn) : \"cc\")\n#endif\n\n/**\n\\brief Test case: TC_CoreFunc_APSR\n\\details\n- Check if __get_APSR intrinsic is available\n- Check if __get_xPSR intrinsic is available\n- Check negative, zero and overflow flags\n*/\nvoid TC_CoreFunc_APSR (void) {\n  volatile uint32_t result;\n  //lint -esym(838, Rm) unused values\n  //lint -esym(438, Rm) unused values\n\n  // Check negative flag\n  volatile int32_t Rm = 5;\n  volatile int32_t Rn = 7;\n  SUBS(Rm, Rm, Rn);\n  result  = __get_APSR();\n  ASSERT_TRUE((result & APSR_N_Msk) == APSR_N_Msk);\n\n  Rm = 5;\n  Rn = 7;\n  SUBS(Rm, Rm, Rn);\n  result  = __get_xPSR();\n  ASSERT_TRUE((result & xPSR_N_Msk) == xPSR_N_Msk);\n\n  // Check zero and compare flag\n  Rm = 5;\n  SUBS(Rm, Rm, Rm);\n  result  = __get_APSR();\n  ASSERT_TRUE((result & APSR_Z_Msk) == APSR_Z_Msk);\n  ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);\n\n  Rm = 5;\n  SUBS(Rm, Rm, Rm);\n  result  = __get_xPSR();\n  ASSERT_TRUE((result & xPSR_Z_Msk) == xPSR_Z_Msk);\n  ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);\n\n  // Check overflow flag\n  Rm = 5;\n  Rn = INT32_MAX;\n  ADDS(Rm, Rm, Rn);\n  result  = __get_APSR();\n  ASSERT_TRUE((result & APSR_V_Msk) == APSR_V_Msk);\n\n  Rm = 5;\n  Rn = INT32_MAX;\n  ADDS(Rm, Rm, Rn);\n  result  = __get_xPSR();\n  ASSERT_TRUE((result & xPSR_V_Msk) == xPSR_V_Msk);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_PSP\n\\details\n- Check if __get_PSP and __set_PSP intrinsic can be used to manipulate process stack pointer.\n*/\nvoid TC_CoreFunc_PSP (void) {\n  // don't use stack for this variables\n  static uint32_t orig;\n  static uint32_t psp;\n  static uint32_t result;\n\n  orig = __get_PSP();\n\n  psp = orig + 0x12345678U;\n  __set_PSP(psp);\n\n  result = __get_PSP();\n\n  __set_PSP(orig);\n\n  ASSERT_TRUE(result == psp);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_MSP\n\\details\n- Check if __get_MSP and __set_MSP intrinsic can be used to manipulate main stack pointer.\n*/\nvoid TC_CoreFunc_MSP (void) {\n  // don't use stack for this variables\n  static uint32_t orig;\n  static uint32_t msp;\n  static uint32_t result;\n  static uint32_t ctrl;\n\n  ctrl = __get_CONTROL();\n  orig = __get_MSP();\n\n  __set_PSP(orig);\n  __set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP\n\n  msp = orig + 0x12345678U;\n  __set_MSP(msp);\n\n  result = __get_MSP();\n\n  __set_MSP(orig);\n\n  __set_CONTROL(ctrl);\n\n  ASSERT_TRUE(result == msp);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_PSPLIM\n\\details\n- Check if __get_PSPLIM and __set_PSPLIM intrinsic can be used to manipulate process stack pointer limit.\n*/\nvoid TC_CoreFunc_PSPLIM (void) {\n#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__   ) && (__ARM_ARCH_8M_BASE__   == 1))    )\n  // don't use stack for this variables\n  static uint32_t orig;\n  static uint32_t psplim;\n  static uint32_t result;\n\n  orig = __get_PSPLIM();\n\n  psplim = orig + 0x12345678U;\n  __set_PSPLIM(psplim);\n\n  result = __get_PSPLIM();\n\n  __set_PSPLIM(orig);\n\n#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \\\n     !(defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) && \\\n     (!defined (__ARM_FEATURE_CMSE     ) || (__ARM_FEATURE_CMSE      < 3))    )\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  ASSERT_TRUE(result == 0U);\n#else\n  ASSERT_TRUE(result == psplim);\n#endif\n\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_PSPLIM_NS\n\\details\n- Check if __TZ_get_PSPLIM_NS and __TZ_set_PSPLIM_NS intrinsic can be used to manipulate process stack pointer limit.\n*/\nvoid TC_CoreFunc_PSPLIM_NS (void) {\n#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__   ) && (__ARM_ARCH_8M_BASE__   == 1))    )\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n  uint32_t orig;\n  uint32_t psplim;\n  uint32_t result;\n\n  orig = __TZ_get_PSPLIM_NS();\n\n  psplim = orig + 0x12345678U;\n  __TZ_set_PSPLIM_NS(psplim);\n\n  result = __TZ_get_PSPLIM_NS();\n\n  __TZ_set_PSPLIM_NS(orig);\n\n#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \\\n     !(defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1))    )\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  ASSERT_TRUE(result == 0U);\n#else\n  ASSERT_TRUE(result == psplim);\n#endif\n#endif\n\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_MSPLIM\n\\details\n- Check if __get_MSPLIM and __set_MSPLIM intrinsic can be used to manipulate main stack pointer limit.\n*/\nvoid TC_CoreFunc_MSPLIM (void) {\n#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__   ) && (__ARM_ARCH_8M_BASE__   == 1))    )\n  // don't use stack for this variables\n  static uint32_t orig;\n  static uint32_t msplim;\n  static uint32_t result;\n  static uint32_t ctrl;\n\n  ctrl = __get_CONTROL();\n  __set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP\n\n  orig = __get_MSPLIM();\n\n  msplim = orig + 0x12345678U;\n  __set_MSPLIM(msplim);\n\n  result = __get_MSPLIM();\n\n  __set_MSPLIM(orig);\n\n  __set_CONTROL(ctrl);\n\n#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \\\n     !(defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) && \\\n     (!defined (__ARM_FEATURE_CMSE     ) || (__ARM_FEATURE_CMSE      < 3))    )\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  ASSERT_TRUE(result == 0U);\n#else\n  ASSERT_TRUE(result == msplim);\n#endif\n\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_MSPLIM_NS\n\\details\n- Check if __TZ_get_MSPLIM_NS and __TZ_set_MSPLIM_NS intrinsic can be used to manipulate process stack pointer limit.\n*/\nvoid TC_CoreFunc_MSPLIM_NS (void) {\n#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n  uint32_t orig;\n  uint32_t msplim;\n  uint32_t result;\n\n  orig = __TZ_get_MSPLIM_NS();\n\n  msplim = orig + 0x12345678U;\n  __TZ_set_MSPLIM_NS(msplim);\n\n  result = __TZ_get_MSPLIM_NS();\n\n  __TZ_set_MSPLIM_NS(orig);\n\n#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \\\n     !(defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1))    )\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  ASSERT_TRUE(result == 0U);\n#else\n  ASSERT_TRUE(result == msplim);\n#endif\n#endif\n\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_PRIMASK\n\\details\n- Check if __get_PRIMASK and __set_PRIMASK intrinsic can be used to manipulate PRIMASK.\n- Check if __enable_irq and __disable_irq are reflected in PRIMASK.\n*/\nvoid TC_CoreFunc_PRIMASK (void) {\n  uint32_t orig = __get_PRIMASK();\n\n  // toggle primask\n  uint32_t primask = (orig & ~0x01U) | (~orig & 0x01U);\n\n  __set_PRIMASK(primask);\n  uint32_t result = __get_PRIMASK();\n  ASSERT_TRUE(result == primask);\n\n  __disable_irq();\n  result = __get_PRIMASK();\n  ASSERT_TRUE((result & 0x01U) == 1U);\n\n  __enable_irq();\n  result = __get_PRIMASK();\n  ASSERT_TRUE((result & 0x01U) == 0U);\n\n  __disable_irq();\n  result = __get_PRIMASK();\n  ASSERT_TRUE((result & 0x01U) == 1U);\n\n  __set_PRIMASK(orig);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_FAULTMASK\n\\details\n- Check if __get_FAULTMASK and __set_FAULTMASK intrinsic can be used to manipulate FAULTMASK.\n- Check if __enable_fault_irq and __disable_fault_irq are reflected in FAULTMASK.\n*/\nvoid TC_CoreFunc_FAULTMASK (void) {\n#if ((defined (__ARM_ARCH_7M__        ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__       ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))    )\n\n  uint32_t orig = __get_FAULTMASK();\n\n  // toggle faultmask\n  uint32_t faultmask = (orig & ~0x01U) | (~orig & 0x01U);\n\n  __set_FAULTMASK(faultmask);\n  uint32_t result = __get_FAULTMASK();\n  ASSERT_TRUE(result == faultmask);\n\n  __disable_fault_irq();\n  result = __get_FAULTMASK();\n  ASSERT_TRUE((result & 0x01U) == 1U);\n\n  __enable_fault_irq();\n  result = __get_FAULTMASK();\n  ASSERT_TRUE((result & 0x01U) == 0U);\n\n  __disable_fault_irq();\n  result = __get_FAULTMASK();\n  ASSERT_TRUE((result & 0x01U) == 1U);\n\n  __set_FAULTMASK(orig);\n\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_BASEPRI\n\\details\n- Check if __get_BASEPRI and __set_BASEPRI intrinsic can be used to manipulate BASEPRI.\n- Check if __set_BASEPRI_MAX intrinsic can be used to manipulate BASEPRI.\n*/\nvoid TC_CoreFunc_BASEPRI(void) {\n#if ((defined (__ARM_ARCH_7M__        ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__       ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))    )\n\n  uint32_t orig = __get_BASEPRI();\n\n  uint32_t basepri = ~orig & 0x80U;\n  __set_BASEPRI(basepri);\n  uint32_t result = __get_BASEPRI();\n\n  ASSERT_TRUE(result == basepri);\n\n  __set_BASEPRI(orig);\n\n  __set_BASEPRI_MAX(basepri);\n  result = __get_BASEPRI();\n\n  ASSERT_TRUE(result == basepri);\n\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_FPUType\n\\details\nCheck SCB_GetFPUType returns information.\n*/\nvoid TC_CoreFunc_FPUType(void) {\n  uint32_t fpuType = SCB_GetFPUType();\n#if defined(__FPU_PRESENT) && (__FPU_PRESENT != 0)\n  ASSERT_TRUE(fpuType > 0U);\n#else\n  ASSERT_TRUE(fpuType  == 0U);\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreFunc_FPSCR\n\\details\n- Check if __get_FPSCR and __set_FPSCR intrinsics can be used\n*/\nvoid TC_CoreFunc_FPSCR(void) {\n  uint32_t fpscr = __get_FPSCR();\n  __ISB();\n  __DSB();\n\n  __set_FPSCR(~fpscr);\n  __ISB();\n  __DSB();\n\n  uint32_t result = __get_FPSCR();\n\n  __set_FPSCR(fpscr);\n\n#if (defined (__FPU_USED   ) && (__FPU_USED    == 1U))\n  ASSERT_TRUE(result != fpscr);\n#else\n  ASSERT_TRUE(result == 0U);\n#endif\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreInstr.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_CoreInstr.c\n *      Purpose:      CMSIS CORE validation tests implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2021 Arm Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\"\n\n#if defined(__CORTEX_M)\n#elif defined(__CORTEX_A)\n#include \"irq_ctrl.h\"\n#else\n#error __CORTEX_M or __CORTEX_A must be defined!\n#endif\n\n/*-----------------------------------------------------------------------------\n *      Test implementation\n *----------------------------------------------------------------------------*/\n\n/*-----------------------------------------------------------------------------\n *      Test cases\n *----------------------------------------------------------------------------*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_NOP\n\\details\n- Check if __NOP instrinsic is available\n- No real assertion is deployed, just a compile time check.\n*/\nvoid TC_CoreInstr_NOP (void) {\n  __NOP();\n  ASSERT_TRUE(1U == 1U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_SEV\n\\details\n- Check if __SEV instrinsic is available\n- No real assertion is deployed, just a compile time check.\n*/\nvoid TC_CoreInstr_SEV (void) {\n  __SEV();\n  ASSERT_TRUE(1U == 1U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_BKPT\n\\details\n- Check if __BKPT instrinsic is available\n- No real assertion is deployed, just a compile time check.\n*/\nvoid TC_CoreInstr_BKPT (void) {\n  __BKPT(0xABU);\n  ASSERT_TRUE(1U == 1U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_ISB\n\\details\n- Check if __ISB instrinsic is available\n- No real assertion is deployed, just a compile time check.\n*/\nvoid TC_CoreInstr_ISB (void) {\n  __ISB();\n  ASSERT_TRUE(1U == 1U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_DSB\n\\details\n- Check if __DSB instrinsic is available\n- No real assertion is deployed, just a compile time check.\n*/\nvoid TC_CoreInstr_DSB (void) {\n  __DSB();\n  ASSERT_TRUE(1U == 1U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_DMB\n\\details\n- Check if __DNB instrinsic is available\n- No real assertion is deployed, just a compile time check.\n*/\nvoid TC_CoreInstr_DMB (void) {\n  __DMB();\n  ASSERT_TRUE(1U == 1U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_WFI\n\\details\n- Check if __WFI instrinsic is available\n- No real assertion is deployed, just a compile time check.\n*/\nvoid TC_CoreInstr_WFI (void) {\n  __WFI();\n  ASSERT_TRUE(1U == 1U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_WFE\n\\details\n- Check if __WFE instrinsic is available\n- No real assertion is deployed, just a compile time check.\n*/\nvoid TC_CoreInstr_WFE (void) {\n  __WFE();\n  ASSERT_TRUE(1U == 1U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_REV\n\\details\n- Check if __REV instrinsic swaps all bytes in a word.\n*/\nvoid TC_CoreInstr_REV (void) {\n  volatile uint32_t op1_u32;\n  volatile uint32_t res_u32;\n\n  op1_u32 = 0x47110815U;\n  res_u32 = __REV(op1_u32);\n  ASSERT_TRUE(res_u32 == 0x15081147U);\n\n  op1_u32 = 0x80000000U;\n  res_u32 = __REV(op1_u32);\n  ASSERT_TRUE(res_u32 == 0x00000080U);\n\n  op1_u32 = 0x00000080U;\n  res_u32 = __REV(op1_u32);\n  ASSERT_TRUE(res_u32 == 0x80000000U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_REV16\n\\details\n- Check if __REV16 instrinsic swaps the bytes in both halfwords independendly.\n*/\nvoid TC_CoreInstr_REV16(void) {\n  volatile uint32_t op1_u32;\n  volatile uint32_t res_u32;\n\n  op1_u32 = 0x47110815U;\n  res_u32 = __REV16(op1_u32);\n  ASSERT_TRUE(res_u32 == 0x11471508U);\n\n  op1_u32 = 0x00001234U;\n  res_u32 = __REV16(op1_u32);\n  ASSERT_TRUE(res_u32 == 0x00003412U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_REVSH\n\\details\n- Check if __REVSH instrinsic swaps bytes in a signed halfword keeping the sign.\n*/\nvoid TC_CoreInstr_REVSH(void) {\n  volatile int16_t value  = 0U;\n           int16_t result = 0U;\n\n  value = 0x4711;\n  result = __REVSH(value);\n  ASSERT_TRUE(result == 0x1147);\n\n  value = (int16_t)0x8000;\n  result = __REVSH(value);\n  ASSERT_TRUE(result == 0x0080);\n\n  value = 0x0080;\n  result = __REVSH(value);\n  ASSERT_TRUE(result == (int16_t)0x8000);\n\n  value = -0x1234;\n  result = __REVSH(value);\n  ASSERT_TRUE(result == (int16_t)0xcced);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_RBIT\n\\details\n- Check if __RBIT instrinsic revserses the bit order of arbitrary words.\n*/\nvoid TC_CoreInstr_RBIT (void) {\n  volatile uint32_t value  = 0U;\n           uint32_t result = 0U;\n\n  value = 0xAAAAAAAAU;\n  result = __RBIT(value);\n  ASSERT_TRUE(result == 0x55555555U);\n\n  value = 0x55555555U;\n  result = __RBIT(value);\n  ASSERT_TRUE(result == 0xAAAAAAAAU);\n\n  value = 0x00000001U;\n  result = __RBIT(value);\n  ASSERT_TRUE(result == 0x80000000U);\n\n  value = 0x80000000U;\n  result = __RBIT(value);\n  ASSERT_TRUE(result == 0x00000001U);\n\n  value = 0xDEADBEEFU;\n  result = __RBIT(value);\n  ASSERT_TRUE(result == 0xF77DB57BU);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_ROR\n\\details\n- Check if __ROR instrinsic moves all bits as expected.\n*/\nvoid TC_CoreInstr_ROR(void) {\n  volatile uint32_t value  = 0U;\n           uint32_t result = 0U;\n\n  value = 0x00000001U;\n  result = __ROR(value, 1U);\n  ASSERT_TRUE(result == 0x80000000U);\n\n  value = 0x80000000U;\n  result = __ROR(value, 1U);\n  ASSERT_TRUE(result == 0x40000000U);\n\n  value = 0x40000000U;\n  result = __ROR(value, 30U);\n  ASSERT_TRUE(result == 0x00000001U);\n\n  value = 0x00000001U;\n  result = __ROR(value, 32U);\n  ASSERT_TRUE(result == 0x00000001U);\n\n  value = 0x08154711U;\n  result = __ROR(value, 8U);\n  ASSERT_TRUE(result == 0x11081547U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_CLZ\n\\details\n- Check if __CLZ instrinsic counts leading zeros.\n*/\nvoid TC_CoreInstr_CLZ (void) {\n  volatile uint32_t value  = 0U;\n           uint32_t result = 0U;\n\n  value = 0x00000000U;\n  result = __CLZ(value);\n  ASSERT_TRUE(result == 32);\n\n  value = 0x00000001U;\n  result = __CLZ(value);\n  ASSERT_TRUE(result == 31);\n\n  value = 0x40000000U;\n  result = __CLZ(value);\n  ASSERT_TRUE(result == 1);\n\n  value = 0x80000000U;\n  result = __CLZ(value);\n  ASSERT_TRUE(result == 0);\n\n  value = 0xFFFFFFFFU;\n  result = __CLZ(value);\n  ASSERT_TRUE(result == 0);\n\n  value = 0x80000001U;\n  result = __CLZ(value);\n  ASSERT_TRUE(result == 0);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_SSAT\n\\details\n- Check if __SSAT instrinsic saturates signed integer values.\n*/\nvoid TC_CoreInstr_SSAT (void) {\n  volatile int32_t value  = 0;\n           int32_t result = 0;\n\n  value = INT32_MAX;\n  result = __SSAT(value, 32U);\n  ASSERT_TRUE(result == INT32_MAX);\n\n  value = INT32_MAX;\n  result = __SSAT(value, 16U);\n  ASSERT_TRUE(result == INT16_MAX);\n\n  value = INT32_MAX;\n  result = __SSAT(value, 8U);\n  ASSERT_TRUE(result == INT8_MAX);\n\n  value = INT32_MAX;\n  result = __SSAT(value, 1U);\n  ASSERT_TRUE(result == 0);\n\n  value = INT32_MIN;\n  result = __SSAT(value, 32U);\n  ASSERT_TRUE(result == INT32_MIN);\n\n  value = INT32_MIN;\n  result = __SSAT(value, 16U);\n  ASSERT_TRUE(result == INT16_MIN);\n\n  value = INT32_MIN;\n  result = __SSAT(value, 8U);\n  ASSERT_TRUE(result == INT8_MIN);\n\n  value = INT32_MIN;\n  result = __SSAT(value, 1U);\n  ASSERT_TRUE(result == -1);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_USAT\n\\details\n- Check if __USAT instrinsic saturates unsigned integer values.\n*/\nvoid TC_CoreInstr_USAT (void) {\n  volatile  int32_t value  = 0U;\n           uint32_t result = 0U;\n\n  value = INT32_MAX;\n  result = __USAT(value, 31U);\n  ASSERT_TRUE(result == (UINT32_MAX >> 1U));\n\n  value = INT32_MAX;\n  result = __USAT(value, 16U);\n  ASSERT_TRUE(result == UINT16_MAX);\n\n  value = INT32_MAX;\n  result = __USAT(value, 8U);\n  ASSERT_TRUE(result == UINT8_MAX);\n\n  value = INT32_MAX;\n  result = __USAT(value, 0U);\n  ASSERT_TRUE(result == 0U);\n\n  value = INT32_MIN;\n  result = __USAT(value, 31U);\n  ASSERT_TRUE(result == 0U);\n\n  value = INT32_MIN;\n  result = __USAT(value, 16U);\n  ASSERT_TRUE(result == 0U);\n\n  value = INT32_MIN;\n  result = __USAT(value, 8U);\n  ASSERT_TRUE(result == 0U);\n\n  value = INT32_MIN;\n  result = __USAT(value, 0U);\n  ASSERT_TRUE(result == 0U);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_CoreInstr_RRX\n\\details\n- Check if __USAT instrinsic saturates unsigned integer values.\n*/\nvoid TC_CoreInstr_RRX (void) {\n#if ((defined (__ARM_ARCH_7M__        ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__       ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))    )\n\n  volatile uint32_t  value  = 0U;\n  volatile uint32_t  result = 0U;\n  volatile xPSR_Type xPSR;\n\n  value = 0x80000002;\n  xPSR.w = __get_xPSR();\n  result = __RRX(value);\n  ASSERT_TRUE(result == (0x40000001 | (uint32_t)(xPSR.b.C << 31)));\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n#if ((defined (__ARM_ARCH_7M__        ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__       ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__   ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined(__CORTEX_A)                                               )    )\n\n/// Exclusive byte value\nstatic volatile uint8_t TC_CoreInstr_LoadStoreExclusive_byte = 0x47U;\n\n/// Exclusive halfword value\nstatic volatile uint16_t TC_CoreInstr_LoadStoreExclusive_hword = 0x0815U;\n\n/// Exclusive word value\nstatic volatile uint32_t TC_CoreInstr_LoadStoreExclusive_word = 0x08154711U;\n\n/**\n\\brief Interrupt function for TC_CoreInstr_LoadStoreExclusive\n\\details\nThe interrupt manipulates all the global data\nwhich disrupts the exclusive sequences in the test\n*/\nstatic void TC_CoreInstr_LoadStoreExclusive_IRQHandler(void) {\n\n  const uint8_t b = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);\n  __STREXB((uint8_t)~b, &TC_CoreInstr_LoadStoreExclusive_byte);\n\n  const uint16_t hw = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);\n  __STREXH((uint16_t)~hw, &TC_CoreInstr_LoadStoreExclusive_hword);\n\n  const uint32_t w = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);\n  __STREXW((uint32_t)~w, &TC_CoreInstr_LoadStoreExclusive_word);\n}\n\n/**\n\\brief Helper function for TC_CoreInstr_LoadStoreExclusive to enable test interrupt.\n\\details\nThis helper function implements interrupt enabling according to target\narchitecture, i.e. Cortex-A or Cortex-M.\n*/\nstatic void TC_CoreInstr_LoadStoreExclusive_IRQEnable(void) {\n#if defined(__CORTEX_M)\n  TST_IRQHandler = TC_CoreInstr_LoadStoreExclusive_IRQHandler;\n  NVIC_EnableIRQ(Interrupt0_IRQn);\n#elif defined(__CORTEX_A)\n  IRQ_SetHandler(SGI0_IRQn, TC_CoreInstr_LoadStoreExclusive_IRQHandler);\n  IRQ_Enable(SGI0_IRQn);\n#else\n  #error __CORTEX_M or __CORTEX_A must be defined!\n#endif\n  __enable_irq();\n}\n\n/**\n\\brief Helper function for TC_CoreInstr_LoadStoreExclusive to set test interrupt pending.\n\\details\nThis helper function implements set pending the test interrupt according to target\narchitecture, i.e. Cortex-A or Cortex-M.\n*/\nstatic void TC_CoreInstr_LoadStoreExclusive_IRQPend(void) {\n#if defined(__CORTEX_M)\n  NVIC_SetPendingIRQ(Interrupt0_IRQn);\n#elif defined(__CORTEX_A)\n  IRQ_SetPending(SGI0_IRQn);\n#else\n  #error __CORTEX_M or __CORTEX_A must be defined!\n#endif\n  for(uint32_t i = 10U; i > 0U; --i) {}\n}\n\n/**\n\\brief Helper function for TC_CoreInstr_LoadStoreExclusive to disable test interrupt.\n\\details\nThis helper function implements interrupt disabling according to target\narchitecture, i.e. Cortex-A or Cortex-M.\n*/\nstatic void TC_CoreInstr_LoadStoreExclusive_IRQDisable(void) {\n  __disable_irq();\n#if defined(__CORTEX_M)\n  NVIC_DisableIRQ(Interrupt0_IRQn);\n  TST_IRQHandler = NULL;\n#elif defined(__CORTEX_A)\n  IRQ_Disable(SGI0_IRQn);\n  IRQ_SetHandler(SGI0_IRQn, NULL);\n#else\n  #error __CORTEX_M or __CORTEX_A must be defined!\n#endif\n}\n#endif\n\n/**\n\\brief Test case: TC_CoreInstr_LoadStoreExclusive\n\\details\nChecks exclusive load and store instructions:\n- LDREXB, LDREXH, LDREXW\n- STREXB, STREXH, STREXW\n- CLREX\n*/\nvoid TC_CoreInstr_LoadStoreExclusive (void) {\n#if ((defined (__ARM_ARCH_7M__        ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__       ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__   ) && (__ARM_ARCH_8M_BASE__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined(__CORTEX_A)                                               )    )\n  uint8_t  u8,  u8Inv;\n  uint16_t u16, u16Inv;\n  uint32_t u32, u32Inv;\n  uint32_t result;\n\n  /* 1. Test exclusives without interruption */\n  u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);\n  ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte);\n\n  result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte);\n  ASSERT_TRUE(result == 0U);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8+1U);\n\n  u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);\n  ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword);\n\n  result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword);\n  ASSERT_TRUE(result == 0U);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16+1U);\n\n  u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);\n  ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word);\n\n  result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word);\n  ASSERT_TRUE(result == 0U);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32+1U);\n\n  /* 2. Test exclusives with clear */\n  u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);\n  ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte);\n\n  __CLREX();\n\n  result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte);\n  ASSERT_TRUE(result == 1U);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8);\n\n  u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);\n  ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword);\n\n  __CLREX();\n\n  result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword);\n  ASSERT_TRUE(result == 1U);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16);\n\n  u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);\n  ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word);\n\n  __CLREX();\n\n  result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word);\n  ASSERT_TRUE(result == 1U);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32);\n\n  /* 3. Test exclusives with interruption */\n  TC_CoreInstr_LoadStoreExclusive_IRQEnable();\n\n  u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);\n  ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte);\n\n  TC_CoreInstr_LoadStoreExclusive_IRQPend();\n\n  result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte);\n  ASSERT_TRUE(result == 1U);\n  u8Inv = (uint8_t)~u8;\n  ASSERT_TRUE(u8Inv == TC_CoreInstr_LoadStoreExclusive_byte);\n\n  u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);\n  ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword);\n\n  TC_CoreInstr_LoadStoreExclusive_IRQPend();\n\n  result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword);\n  ASSERT_TRUE(result == 1U);\n  u16Inv = (uint16_t)~u16;\n  ASSERT_TRUE(u16Inv == TC_CoreInstr_LoadStoreExclusive_hword);\n\n  u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);\n  ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word);\n\n  TC_CoreInstr_LoadStoreExclusive_IRQPend();\n\n  result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word);\n  ASSERT_TRUE(result == 1U);\n  u32Inv = (uint32_t)~u32;\n  ASSERT_TRUE(u32Inv == TC_CoreInstr_LoadStoreExclusive_word);\n\n  TC_CoreInstr_LoadStoreExclusive_IRQDisable();\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n#if ((defined (__ARM_ARCH_7M__        ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__       ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))    )\n\n/// byte value unprivileged access\nstatic volatile uint8_t TC_CoreInstr_LoadStoreUnpriv_byte = 0x47U;\n\n/// halfword value unprivileged access\nstatic volatile uint16_t TC_CoreInstr_LoadStoreUnpriv_hword = 0x0815U;\n\n/// word value unprivileged access\nstatic volatile uint32_t TC_CoreInstr_LoadStoreUnpriv_word = 0x08154711U;\n#endif\n\n\n/**\n\\brief Test case: TC_CoreInstr_LoadStoreUnpriv\n\\details\nChecks load/store unprivileged instructions:\n- LDRBT, LDRHT, LDRT\n- STRBT, STRHT, STRT\n*/\nvoid TC_CoreInstr_LoadStoreUnpriv (void) {\n#if ((defined (__ARM_ARCH_7M__        ) && (__ARM_ARCH_7M__        == 1)) || \\\n     (defined (__ARM_ARCH_7EM__       ) && (__ARM_ARCH_7EM__       == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))    )\n  uint8_t  u8     = 0U;\n  uint16_t u16    = 0U;\n  uint32_t u32    = 0U;\n\n  /* 1. Test without interruption */\n  u8 = __LDRBT(&TC_CoreInstr_LoadStoreUnpriv_byte);\n  ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreUnpriv_byte);\n\n  __STRBT(u8+1U, &TC_CoreInstr_LoadStoreUnpriv_byte);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_byte == u8+1U);\n\n  u16 = __LDRHT(&TC_CoreInstr_LoadStoreUnpriv_hword);\n  ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreUnpriv_hword);\n\n  __STRHT(u16+1U, &TC_CoreInstr_LoadStoreUnpriv_hword);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_hword == u16+1U);\n\n  u32 = __LDRT(&TC_CoreInstr_LoadStoreUnpriv_word);\n  ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreUnpriv_word);\n\n  __STRT(u32+1U, &TC_CoreInstr_LoadStoreUnpriv_word);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_word == u32+1U);\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__   ) && (__ARM_ARCH_8M_BASE__   == 1))    )\n\n/// byte value unprivileged access\nstatic volatile uint8_t TC_CoreInstr_LoadStoreAcquire_byte = 0x47U;\n\n/// halfword value unprivileged access\nstatic volatile uint16_t TC_CoreInstr_LoadStoreAcquire_hword = 0x0815U;\n\n/// word value unprivileged access\nstatic volatile uint32_t TC_CoreInstr_LoadStoreAcquire_word = 0x08154711U;\n#endif\n\n\n/**\n\\brief Test case: TC_CoreInstr_LoadStoreAquire\n\\details\nChecks Load-Acquire and Store-Release instructions:\n- LDAB, LDAH, LDA\n- STLB, STLH, STL\n*/\nvoid TC_CoreInstr_LoadStoreAcquire (void) {\n#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__   ) && (__ARM_ARCH_8M_BASE__   == 1))    )\n  uint8_t  u8     = 0U;\n  uint16_t u16    = 0U;\n  uint32_t u32    = 0U;\n\n  /* 1. Test without interruption */\n  u8 = __LDAB(&TC_CoreInstr_LoadStoreAcquire_byte);\n  ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquire_byte);\n\n  __STLB(u8+1U, &TC_CoreInstr_LoadStoreAcquire_byte);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_byte == u8+1U);\n\n  u16 = __LDAH(&TC_CoreInstr_LoadStoreAcquire_hword);\n  ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquire_hword);\n\n  __STLH(u16+1U, &TC_CoreInstr_LoadStoreAcquire_hword);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_hword == u16+1U);\n\n  u32 = __LDA(&TC_CoreInstr_LoadStoreAcquire_word);\n  ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquire_word);\n\n  __STL(u32+1U, &TC_CoreInstr_LoadStoreAcquire_word);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_word == u32+1U);\n#endif\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__   ) && (__ARM_ARCH_8M_BASE__   == 1))    )\n\n/// byte value unprivileged access\nstatic volatile uint8_t TC_CoreInstr_LoadStoreAcquireExclusive_byte = 0x47U;\n\n/// halfword value unprivileged access\nstatic volatile uint16_t TC_CoreInstr_LoadStoreAcquireExclusive_hword = 0x0815U;\n\n/// word value unprivileged access\nstatic volatile uint32_t TC_CoreInstr_LoadStoreAcquireExclusive_word = 0x08154711U;\n#endif\n\n\n/**\n\\brief Test case: TC_CoreInstr_LoadStoreAquire\n\\details\nChecks Load-Acquire and Store-Release exclusive instructions:\n- LDAEXB, LDAEXH, LDAEX\n- STLEXB, STLEXH, STLEX\n*/\nvoid TC_CoreInstr_LoadStoreAcquireExclusive (void) {\n#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__   ) && (__ARM_ARCH_8M_MAIN__   == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__   ) && (__ARM_ARCH_8M_BASE__   == 1))    )\n  uint8_t  u8     = 0U;\n  uint16_t u16    = 0U;\n  uint32_t u32    = 0U;\n  uint32_t result = 0U;\n\n  /* 1. Test without interruption */\n  u8 = __LDAEXB(&TC_CoreInstr_LoadStoreAcquireExclusive_byte);\n  ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquireExclusive_byte);\n\n  result = __STLEXB(u8+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_byte);\n  ASSERT_TRUE(result == 0U);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_byte == u8+1U);\n\n  u16 = __LDAEXH(&TC_CoreInstr_LoadStoreAcquireExclusive_hword);\n  ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquireExclusive_hword);\n\n  result = __STLEXH(u16+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_hword);\n  ASSERT_TRUE(result == 0U);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_hword == u16+1U);\n\n  u32 = __LDAEX(&TC_CoreInstr_LoadStoreAcquireExclusive_word);\n  ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquireExclusive_word);\n\n  result = __STLEX(u32+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_word);\n  ASSERT_TRUE(result == 0U);\n  ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_word == u32+1U);\n#endif\n}\n\n\n/**\n\\brief Test case: TC_CoreInstr_UnalignedUint16\n\\details\nChecks macro functions to access unaligned uint16_t values:\n- __UNALIGNED_UINT16_READ\n- __UNALIGNED_UINT16_WRITE\n*/\nvoid TC_CoreInstr_UnalignedUint16(void) {\n  uint8_t buffer[3] = { 0U, 0U, 0U };\n  uint16_t val;\n  \n  for(int i=0; i<2; i++) {\n    __UNALIGNED_UINT16_WRITE(&(buffer[i]), 0x4711U);\n    ASSERT_TRUE(buffer[i]       == 0x11U);\n    ASSERT_TRUE(buffer[i+1]     == 0x47U);\n    ASSERT_TRUE(buffer[(i+2)%3] == 0x00U);\n  \n    buffer[i] = 0x12U;\n    buffer[i+1] = 0x46U;\n  \n    val = __UNALIGNED_UINT16_READ(&(buffer[i]));\n    ASSERT_TRUE(val == 0x4612U);\n  \n    buffer[i]   = 0x00U;\n    buffer[i+1] = 0x00U;\n  }\n}\n\n\n/**\n\\brief Test case: TC_CoreInstr_UnalignedUint32\n\\details\nChecks macro functions to access unaligned uint32_t values:\n- __UNALIGNED_UINT32_READ\n- __UNALIGNED_UINT32_WRITE\n*/\nvoid TC_CoreInstr_UnalignedUint32(void) {\n  uint8_t buffer[7] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U };\n  uint32_t val;\n  \n  for(int i=0; i<4; i++) {\n    __UNALIGNED_UINT32_WRITE(&(buffer[i]), 0x08154711UL);\n    ASSERT_TRUE(buffer[i+0]     == 0x11U);\n    ASSERT_TRUE(buffer[i+1]     == 0x47U);\n    ASSERT_TRUE(buffer[i+2]     == 0x15U);\n    ASSERT_TRUE(buffer[i+3]     == 0x08U);\n    ASSERT_TRUE(buffer[(i+4)%7] == 0x00U);\n    ASSERT_TRUE(buffer[(i+5)%7] == 0x00U);\n    ASSERT_TRUE(buffer[(i+6)%7] == 0x00U);\n  \n    buffer[i+0] = 0x12U;\n    buffer[i+1] = 0x46U;\n    buffer[i+2] = 0x14U;\n    buffer[i+3] = 0x09U;\n  \n    val = __UNALIGNED_UINT32_READ(&(buffer[i]));\n    ASSERT_TRUE(val == 0x09144612UL);\n  \n    buffer[i+0] = 0x00U;\n    buffer[i+1] = 0x00U;\n    buffer[i+2] = 0x00U;\n    buffer[i+3] = 0x00U;\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_CoreSimd.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_CoreSimd.c\n *      Purpose:      CMSIS CORE validation tests implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2018 Arm Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\"\n\n/*-----------------------------------------------------------------------------\n *      Test implementation\n *----------------------------------------------------------------------------*/\n\n/*-----------------------------------------------------------------------------\n *      Test cases\n *----------------------------------------------------------------------------*/\n\n/**\n\\brief Test case: TC_CoreSimd_SatAddSub\n\\details\n- Check Saturating addition and subtraction:\n  __QADD\n  __QSUB\n*/\nvoid TC_CoreSimd_SatAddSub (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile int32_t op1_s32, op2_s32;\n  volatile int32_t res_s32;\n\n  /* --- __QADD Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80000003;\n  op2_s32 = (int32_t)0x00000004;\n  res_s32 = __QADD(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80000007);\n\n  op1_s32 = (int32_t)0x80000000;\n  op2_s32 = (int32_t)0x80000002;\n  res_s32 = __QADD(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80000000);\n\n  /* --- __QSUB Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80000003;\n  op2_s32 = (int32_t)0x00000004;\n  res_s32 = __QSUB(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80000000);\n\n  op1_s32 = (int32_t)0x80000003;\n  op2_s32 = (int32_t)0x00000002;\n  res_s32 = __QSUB(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80000001);\n#endif\n}\n\n/**\n\\brief Test case: TC_CoreSimd_ParSat16\n\\details\n- Check Parallel 16-bit saturation:\n  __SSAT16\n  __USAT16\n*/\nvoid TC_CoreSimd_ParSat16 (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile int32_t op1_s32;\n  volatile int32_t res_s32;\n\n  /* --- __SSAT16 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80030168;\n  res_s32 = __SSAT16(op1_s32, 8);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFF80007F);\n\n  /* --- __USAT16 Test ---------------------------------------------- */\n  op1_s32 = 0x0030168;\n  res_s32 = __USAT16(op1_s32, 8);\n  ASSERT_TRUE(res_s32 == 0x000300FF);\n#endif\n}\n\n/**\n\\brief Test case: TC_CoreSimd_PackUnpack\n\\details\n- Check Packing and unpacking:\n  __SXTB16\n  __SXTB16_RORn\n  __SXTAB16\n  __SXTAB16__RORn\n  __UXTB16\n  __UXTAB16\n*/\nvoid TC_CoreSimd_PackUnpack (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile int32_t op1_s32, op2_s32;\n  volatile int32_t res_s32;\n\n  /* --- __SXTB16 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80830168;\n  res_s32 = __SXTB16(op1_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFF830068);\n\n  /* --- __SXTB16_ROR8 Test ----------------------------------------- */\n  op1_s32 = (int32_t)0x80830168;\n  res_s32 = __SXTB16_RORn(op1_s32, 8);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFF800001);\n\n  /* --- __SXTB16_ROR16 Test ---------------------------------------- */\n  op1_s32 = (int32_t)0x80830168;\n  res_s32 = __SXTB16_RORn(op1_s32, 16);\n  ASSERT_TRUE(res_s32 == (int32_t)0x68FF83);\n\n  /* --- __SXTB16_ROR24 Test ---------------------------------------- */\n  op1_s32 = (int32_t)0x80830168;\n  res_s32 = __SXTB16_RORn(op1_s32, 24);\n  ASSERT_TRUE(res_s32 == (int32_t)0x1FF80);\n\n  /* --- __SXTAB16 Test --------------------------------------------- */\n  op1_s32 = (int32_t)0x000D0008;\n  op2_s32 = (int32_t)0x80830168;\n  res_s32 = __SXTAB16(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFF900070);\n\n  /* --- __SXTAB16__ROR8 Test --------------------------------------- */\n  op1_s32 = (int32_t)0x000A000A;\n  op2_s32 = (int32_t)0x80830168;\n  res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFF8A000B);\n\n  /* --- __SXTAB16__ROR8 Test --------------------------------------- */\n  op1_s32 = (int32_t)0xFFF6FFF6;\n  op2_s32 = (int32_t)0x80830168;\n  res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFF76FFF7);\n\n  /* --- __SXTAB16__ROR16 Test -------------------------------------- */\n  op1_s32 = (int32_t)0xFFF60015;\n  op2_s32 = (int32_t)0x70880168;\n  res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 16);\n  ASSERT_TRUE(res_s32 == (int32_t)0x5EFF9D);\n\n  /* --- __SXTAB16__ROR24 Test -------------------------------------- */\n  op1_s32 = (int32_t)0xFFF60015;\n  op2_s32 = (int32_t)0x70880168;\n  res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 24);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFFF70085);\n\n  /* --- __UXTB16 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80830168;\n  res_s32 = __UXTB16(op1_s32);\n  ASSERT_TRUE(res_s32 == 0x00830068);\n\n  /* --- __UXTAB16 Test --------------------------------------------- */\n  op1_s32 =          0x000D0008;\n  op2_s32 = (int32_t)0x80830168;\n  res_s32 = __UXTAB16(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == 0x00900070);\n#endif\n}\n\n/**\n\\brief Test case: TC_CoreSimd_ParSel\n\\details\n- Check Parallel selection:\n  __SEL\n*/\nvoid TC_CoreSimd_ParSel (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile uint32_t res_u32;\n\n  volatile int32_t op1_s32, op2_s32;\n  volatile int32_t res_s32;\n\n  APSR_Type  apsr;\n  xPSR_Type  xpsr;\n\n  /* --- __SEL Test ---------------------------------------------- */\n  op1_s32 = 0x33221100;\n  op2_s32 = 0x77665544;\n\n  res_s32 = __SADD8(0x80808080, 0x00000000);            /* __sadd8   sets APSR.GE = 0x00 */\n  res_u32 = __get_APSR();\n  apsr.w = __get_APSR();\n  ASSERT_TRUE( (res_u32 == apsr.w) );\n  xpsr.w = __get_xPSR();\n  ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE)  );\n  res_s32 = __SEL(op1_s32, op2_s32);                      /* __sel          APSR.GE = 0x00 */\n  ASSERT_TRUE( res_s32 == 0x77665544);\n\n  res_s32 = __SADD8(0x80808000, 0x00000000);            /* __sadd8   sets APSR.GE = 0x01 */\n  res_u32 = __get_APSR();\n  apsr.w = __get_APSR();\n  ASSERT_TRUE( (res_u32 == apsr.w)  );\n  xpsr.w = __get_xPSR();\n  ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE)  );\n  res_s32 = __SEL(op1_s32, op2_s32);                      /* __sel          APSR.GE = 0x01 */\n  ASSERT_TRUE(res_s32 == 0x77665500);\n\n  res_s32 = __SADD8(0x80800080, 0x00000000);            /* __sadd8   sets APSR.GE = 0x02 */\n  res_u32 = __get_APSR();\n  apsr.w = __get_APSR();\n  ASSERT_TRUE( (res_u32 == apsr.w) );\n  xpsr.w = __get_xPSR();\n  ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE)  );\n  res_s32 = __SEL(op1_s32, op2_s32);                      /* __sel          APSR.GE = 0x02 */\n  ASSERT_TRUE(res_s32 == 0x77661144);\n#endif\n}\n\n/**\n\\brief Test case: TC_CoreSimd_ParAddSub8\n\\details\n- Check Parallel 8-bit addition and subtraction:\n  __SADD8                                   S  Signed\n  __SSUB8                                   Q  Signed Saturating\n  __SHADD8                                  SH Signed Halving\n  __SHSUB8                                  U  Unsigned\n  __QADD8                                   UQ Unsigned Saturating\n  __QSUB8                                   UH Unsigned Halving\n  __UADD8\n  __USUB8\n  __UHADD8\n  __UHSUB8\n  __UQADD8\n  __UQSUB8\n*/\nvoid TC_CoreSimd_ParAddSub8 (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile uint32_t op1_u32, op2_u32;\n  volatile uint32_t res_u32;\n\n  volatile int32_t op1_s32, op2_s32;\n  volatile int32_t res_s32;\n\n  /* --- __SADD8 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x87858381;\n  op2_s32 = (int32_t)0x08060402;\n  res_s32 = __SADD8(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x8F8B8783);\n\n  /* --- __SSUB8 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x8F8B8783;\n  op2_s32 = (int32_t)0x08060402;\n  res_s32 = __SSUB8(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x87858381);\n\n  /* --- __SHADD8 Test ---------------------------------------------- */\n  op1_s32 = 0x07050302;\n  op2_s32 = 0x08060402;\n  res_s32 = __SHADD8(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == 0x07050302);\n\n  /* --- __SHSUB8 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x8F8B8783;\n  op2_s32 = 0x08060402;\n  res_s32 = __SHSUB8(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xC3C2C1C0);\n\n  /* --- __QADD8 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x8085837F;\n  op2_s32 = (int32_t)0xFF060402;\n  res_s32 = __QADD8(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x808B877F);\n\n  /* --- __QSUB8 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x808B8783;\n  op2_s32 = (int32_t)0x08060402;\n  res_s32 = __QSUB8(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80858381);\n\n  /* --- __UADD8 Test ---------------------------------------------- */\n  op1_u32 = 0x07050301;\n  op2_u32 = 0x08060402;\n  res_u32 = __UADD8(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x0F0B0703);\n\n  /* --- __USUB8 Test ---------------------------------------------- */\n  op1_u32 = 0x0F0B0703;\n  op2_u32 = 0x08060402;\n  res_u32 = __USUB8(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x07050301);\n\n  /* --- __UHADD8 Test ---------------------------------------------- */\n  op1_u32 = 0x07050302;\n  op2_u32 = 0x08060402;\n  res_u32 = __UHADD8(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x07050302);\n\n  /* --- __UHSUB8 Test ---------------------------------------------- */\n  op1_u32 = 0x0F0B0703;\n  op2_u32 = 0x08060402;\n  res_u32 = __UHSUB8(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x03020100);\n\n  /* --- __UQADD8 Test ---------------------------------------------- */\n  op1_u32 = 0xFF050301;\n  op2_u32 = 0x08060402;\n  res_u32 = __UQADD8(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0xFF0B0703);\n\n  /* --- __UQSUB8 Test ---------------------------------------------- */\n  op1_u32 = 0x080B0702;\n  op2_u32 = 0x0F060408;\n  res_u32 = __UQSUB8(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x00050300);\n#endif\n}\n\n/**\n\\brief Test case: TC_CoreSimd_AbsDif8\n\\details\n- Check Sum of 8-bit absolute differences:\n  __USAD8\n  __USADA8\n*/\nvoid TC_CoreSimd_AbsDif8 (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile uint32_t op1_u32, op2_u32, op3_u32;\n  volatile uint32_t res_u32;\n\n  /* --- __USAD8 Test ---------------------------------------------- */\n  op1_u32 = 0x87858381;\n  op2_u32 = 0x08060402;\n  res_u32 = __USAD8(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x000001FC);\n\n  /* --- __USADA8 Test ---------------------------------------------- */\n  op1_u32 = 0x87858381;\n  op2_u32 = 0x08060402;\n  op3_u32 = 0x00008000;\n  res_u32 = __USADA8(op1_u32, op2_u32, op3_u32);\n  ASSERT_TRUE(res_u32 == 0x000081FC);\n#endif\n}\n\n/**\n\\brief Test case: TC_CoreSimd_ParAddSub16\n\\details\n- Check Parallel 16-bit addition and subtraction:\n  __SADD16\n  __SSUB16\n  __SASX\n  __SSAX\n  __SHADD16\n  __SHSUB16\n  __SHASX\n  __SHSAX\n  __QADD16\n  __QSUB16\n  __QASX\n  __QSAX\n  __UADD16\n  __USUB16\n  __UASX\n  __USAX\n  __UHADD16\n  __UHSUB16\n  __UHASX\n  __UHSAX\n  __UQSUB16\n  __UQADD16\n  __UQASX\n  __UQSAX\n*/\nvoid TC_CoreSimd_ParAddSub16 (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile uint32_t op1_u32, op2_u32;\n  volatile uint32_t res_u32;\n\n  volatile int32_t op1_s32, op2_s32;\n  volatile int32_t res_s32;\n\n  /* --- __SADD16 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80038001;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SADD16(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80078003);\n\n  /* --- __SSUB16 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80078003;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SSUB16(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80038001);\n\n  /* --- __SASX Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80078003;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SASX(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80097FFF);\n\n  /* --- __SSAX Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80038007;\n  op2_s32 = (int32_t)0x00020004;\n  res_s32 = __SSAX(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x7FFF8009);\n\n  /* --- __SHADD16 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80038001;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SHADD16(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xC003C001);\n\n  /* --- __SHSUB16 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80078003;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SHSUB16(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xC001C000);\n\n  /* --- __SHASX Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80078003;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SHASX(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xC004BFFF);\n\n  /* --- __SHSAX Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80038007;\n  op2_s32 = (int32_t)0x00020004;\n  res_s32 = __SHSAX(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xBFFFC004);\n\n  /* --- __QADD16 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80038000;\n  op2_s32 = (int32_t)0x00048002;\n  res_s32 = __QADD16(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80078000);\n\n  /* --- __QSUB16 Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80038003;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __QSUB16(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80008001);\n\n  /* --- __QASX Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80078003;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __QASX(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80098000);\n\n  /* --- __QSAX Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x80038007;\n  op2_s32 = (int32_t)0x00020004;\n  res_s32 = __QSAX(op1_s32, op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x80008009);\n\n  /* --- __UADD16 Test ---------------------------------------------- */\n  op1_u32 = 0x00010002;\n  op2_u32 = 0x00020004;\n  res_u32 = __UADD16(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x00030006);\n\n  /* --- __USUB16 Test ---------------------------------------------- */\n  op1_u32 = 0x00030006;\n  op2_u32 = 0x00020004;\n  res_u32 = __USUB16(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x00010002);\n\n  /* --- __UASX Test ---------------------------------------------- */\n  op1_u32 = 0x80078003;\n  op2_u32 = 0x00040002;\n  res_u32 = __UASX(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x80097FFF);\n\n  /* --- __USAX Test ---------------------------------------------- */\n  op1_u32 = 0x80038007;\n  op2_u32 = 0x00020004;\n  res_u32 = __USAX(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x7FFF8009);\n\n  /* --- __UHADD16 Test ---------------------------------------------- */\n  op1_u32 = 0x00010002;\n  op2_u32 = 0x00020004;\n  res_u32 = __UHADD16(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x00010003);\n\n  /* --- __UHSUB16 Test ---------------------------------------------- */\n  op1_u32 = 0x00030006;\n  op2_u32 = 0x00020004;\n  res_u32 = __UHSUB16(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x00000001);\n\n  /* --- __UHASX Test ---------------------------------------------- */\n  op1_u32 = 0x80078003;\n  op2_u32 = 0x00040002;\n  res_u32 = __UHASX(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x40043FFF);\n\n  /* --- __UHSAX Test ---------------------------------------------- */\n  op1_u32 = 0x80038007;\n  op2_u32 = 0x00020004;\n  res_u32 = __UHSAX(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x3FFF4004);\n\n  /* --- __UQADD16 Test ---------------------------------------------- */\n  op1_u32 = 0xFFFE0002;\n  op2_u32 = 0x00020004;\n  res_u32 = __UQADD16(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0xFFFF0006);\n\n  /* --- __UQSUB16 Test ---------------------------------------------- */\n  op1_u32 = 0x00020006;\n  op2_u32 = 0x00030004;\n  res_u32 = __UQSUB16(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x00000002);\n\n  /* --- __UQASX Test ---------------------------------------------- */\n  op1_u32 = 0xFFF80003;\n  op2_u32 = 0x00040009;\n  res_u32 = __UQASX(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0xFFFF0000);\n\n  /* --- __UQSAX Test ---------------------------------------------- */\n  op1_u32 = 0x0003FFF8;\n  op2_u32 = 0x00090004;\n  res_u32 = __UQSAX(op1_u32, op2_u32);\n  ASSERT_TRUE(res_u32 == 0x0000FFFF);\n#endif\n}\n\n/**\n\\brief Test case: TC_CoreSimd_ParMul16\n\\details\n- Check Parallel 16-bit multiplication:\n  __SMLAD\n  __SMLADX\n  __SMLALD\n  __SMLALDX\n  __SMLSD\n  __SMLSDX\n  __SMLSLD\n  __SMLSLDX\n  __SMUAD\n  __SMUADX\n  __SMUSD\n  __SMUSDX\n*/\nvoid TC_CoreSimd_ParMul16 (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile int32_t op1_s32, op2_s32, op3_s32;\n  volatile int32_t res_s32;\n\n  volatile int64_t op1_s64;\n  volatile int64_t res_s64;\n\n  /* --- __SMLAD Test ---------------------------------------------- */\n  op1_s32 = 0x00030002;\n  op2_s32 = 0x00050004;\n  op3_s32 = 0x20000000;\n  res_s32 = __SMLAD(op1_s32, op2_s32, op3_s32);\n  ASSERT_TRUE(res_s32 == 0x20000017);\n\n  /* --- __SMLADX Test ---------------------------------------------- */\n  op1_s32 = 0x00030002;\n  op2_s32 = 0x00050004;\n  op3_s32 = 0x00000800;\n  res_s32 = __SMLADX(op1_s32, op2_s32, op3_s32);\n  ASSERT_TRUE(res_s32 == 0x00000816);\n\n  /* --- __SMLALD Test ---------------------------------------------- */\n  op1_s32 = 0x00030002;\n  op2_s32 = 0x00050004;\n  op1_s64 = 0x00000000200000000LL;\n  res_s64 = __SMLALD(op1_s32, op2_s32, op1_s64);\n  ASSERT_TRUE(res_s64 == 0x0000000200000017LL);\n\n  /* --- __SMLALDX Test ---------------------------------------------- */\n  op1_s32 = 0x00030002;\n  op2_s32 = 0x00050004;\n  op1_s64 = 0x00000000200000000LL;\n  res_s64 = __SMLALDX(op1_s32, op2_s32, op1_s64);\n  ASSERT_TRUE(res_s64 == 0x0000000200000016LL);\n\n  /* --- __SMLSD Test ---------------------------------------------- */\n  op1_s32 = 0x00030006;\n  op2_s32 = 0x00050004;\n  op3_s32 = 0x00000800;\n  res_s32 = __SMLSD(op1_s32, op2_s32, op3_s32);\n  ASSERT_TRUE(res_s32 == 0x00000809);\n\n  /* --- __SMLSDX Test ---------------------------------------------- */\n  op1_s32 = 0x00030002;\n  op2_s32 = 0x00050004;\n  op3_s32 = 0x00000800;\n  res_s32 = __SMLSDX(op1_s32, op2_s32, op3_s32);\n  ASSERT_TRUE(res_s32 == 0x000007FE);\n\n  /* --- __SMLSLD Test ---------------------------------------------- */\n  op1_s32 = 0x00030006;\n  op2_s32 = 0x00050004;\n  op1_s64 = 0x00000000200000000LL;\n  res_s64 = __SMLSLD(op1_s32, op2_s32, op1_s64);\n  ASSERT_TRUE(res_s64 == 0x0000000200000009LL);\n\n  /* --- __SMLSLDX Test ---------------------------------------------- */\n  op1_s32 = 0x00030006;\n  op2_s32 = 0x00050004;\n  op1_s64 = 0x00000000200000000LL;\n  res_s64 = __SMLSLDX(op1_s32, op2_s32, op1_s64);\n  ASSERT_TRUE(res_s64 == 0x0000000200000012LL);\n\n  /* --- __SMUAD Test ---------------------------------------------- */\n  op1_s32 = 0x00030001;\n  op2_s32 = 0x00040002;\n  res_s32 = __SMUAD(op1_s32,op2_s32);\n  ASSERT_TRUE(res_s32 == 0x0000000E);\n\n  op1_s32 = (int32_t)0xFFFDFFFF;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SMUAD(op1_s32,op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF2);\n\n  /* --- __SMUADX Test ---------------------------------------------- */\n  op1_s32 = 0x00030001;\n  op2_s32 = 0x00040002;\n  res_s32 = __SMUADX(op1_s32,op2_s32);\n  ASSERT_TRUE(res_s32 == 0x0000000A);\n\n  op1_s32 = (int32_t)0xFFFDFFFF;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SMUADX(op1_s32,op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6);\n\n  /* --- __SMUSD Test ---------------------------------------------- */\n  op1_s32 = (int32_t)0x00030001;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SMUSD(op1_s32,op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6);\n\n  op1_s32 = (int32_t)0xFFFDFFFF;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SMUSD(op1_s32,op2_s32);\n  ASSERT_TRUE(res_s32 == 0x0000000A);\n\n  /* --- __SMUSDX Test ---------------------------------------------- */\n  op1_s32 = 0x00030001;\n  op2_s32 = 0x00040002;\n  res_s32 = __SMUSDX(op1_s32,op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFFE);\n\n  op1_s32 = (int32_t)0xFFFDFFFF;\n  op2_s32 = (int32_t)0x00040002;\n  res_s32 = __SMUSDX(op1_s32,op2_s32);\n  ASSERT_TRUE(res_s32 == (int32_t)0x00000002);\n#endif\n}\n\n/**\n\\brief Test case: TC_CoreSimd_Part9\n\\details\n- Check Packing Halfword:\n  __PKHBT\n  __PKHTB\n*/\nvoid TC_CoreSimd_Pack16 (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile uint32_t op1_u32, op2_u32;\n  volatile uint32_t res_u32;\n\n  /* --- __PKHBT Test ---------------------------------------------- */\n  op1_u32 = 0x00000111;\n  op2_u32 = 0x22200000;\n  res_u32 = __PKHBT(op1_u32, op2_u32, 0);\n  ASSERT_TRUE(res_u32 == 0x22200111);\n\n  op1_u32 = 0x00000111;\n  op2_u32 = 0x22200000;\n  res_u32 = __PKHBT(op1_u32, op2_u32, 4);\n  ASSERT_TRUE(res_u32 == 0x22000111);\n\n  /* --- __PKHTB Test ---------------------------------------------- */\n  op1_u32 = 0x11100000;\n  op2_u32 = 0x00000222;\n  res_u32 = __PKHTB(op1_u32, op2_u32, 0);\n  ASSERT_TRUE(res_u32 == 0x11100222);\n\n  op1_u32 = 0x11100000;\n  op2_u32 = 0x00000222;\n  res_u32 = __PKHTB(op1_u32, op2_u32, 4);\n  ASSERT_TRUE(res_u32 == 0x11100022);\n#endif\n}\n\n/**\n\\brief Test case: TC_CoreSimd_MulAcc32\n\\details\n- Check Signed Most Significant Word Multiply Accumulate:\n  __SMMLA\n*/\nvoid TC_CoreSimd_MulAcc32 (void) {\n#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__  == 1)) || \\\n     (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))     )\n  volatile int32_t op1_s32, op2_s32, op3_s32;\n  volatile int32_t res_s32;\n\n  /* --- __SMMLA Test ---------------------------------------------- */\n  op1_s32 = 0x00000200;\n  op2_s32 = 0x00000004;\n  op3_s32 = 0x00000100;\n  res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32);\n  ASSERT_TRUE(res_s32 == 0x00000100);\n\n  op1_s32 = 0x40000000;\n  op2_s32 = 0x00000010;\n  op3_s32 = 0x00000300;\n  res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32);\n  ASSERT_TRUE(res_s32 == 0x00000304);\n#endif\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Framework.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         cv_framework.c\n *      Purpose:      Test framework entry point\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\" \n  \n/* Prototypes */\nvoid ts_cmsis_cv(void);\nvoid closeDebug(void);\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\defgroup framework_funcs Framework Functions\n\\brief Functions in the Framework software component\n\\details\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Close the debug session.\n\\details\nDebug session dead end - debug script should close session here.\n*/\nvoid closeDebug(void) {\n  __NOP();\n  // Test completed\n}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n\n/**\n\\brief This is CORE Validation test suite.\n\\details\nProgram flow:\n  -# Test report statistics is initialized\n  -# Test report headers are written to the standard output\n  -# All defined test cases are executed:\n      - Test case statistics is initialized\n      - Test case report header is written to the standard output\n      - Test case is executed\n      - Test case results are written to the standard output\n      - Test case report footer is written to the standard output\n      - Test case is closed\n  -# Test report footer is written to the standard output\n  -# Debug session ends in dead loop\n*/\nvoid ts_cmsis_cv () {\n  const char *fn;\n  uint32_t tc, no;\n  (void)ritf.Init ();                           /* Init test report                 */\n  (void)ritf.Open (ts.ReportTitle,              /* Write test report title          */\n                   ts.Date,                     /* Write compilation date           */\n                   ts.Time,                     /* Write compilation time           */\n                   ts.FileName);                /* Write module file name           */\n\n  /* Execute all test cases */\n  for (tc = 0; tc < ts.NumOfTC; tc++) {\n    no = ts.TCBaseNum+tc;                 /* Test case number                 */\n    fn = ts.TC[tc].TFName;                /* Test function name string        */\n    (void)ritf.Open_TC (no, fn);          /* Open test case #(Base + TC)      */\n    if (ts.TC[tc].en != 0U)  {\n      ts.TC[tc].TestFunc();               /* Execute test case if enabled     */\n    }\n    (void)ritf.Close_TC ();               /* Close test case                  */\n  }\n  (void)ritf.Close ();                    /* Close test report                */\n\n  closeDebug();                           /* Close debug session              */\n}\n\n/**\n\\brief This is the entry point of the test framework.\n\\details\nProgram flow:\n  -# Hardware is first initialized if Init callback function is provided\n  -# Main thread is initialized\n*/\nvoid cmsis_cv (void) {\n  \n  /* Init test suite */\n  if (ts.Init != NULL) {\n    ts.Init();                           /* Init hardware                    */\n  }\n\n  ts_cmsis_cv();\n}\n\nvoid cmsis_cv_abort (const char *fn, uint32_t ln, char *desc) {\n  (void)__set_result(fn, ln, FAILED, desc);\n  (void)ritf.Close_TC();\n  (void)ritf.Close();\n  closeDebug();\n}\n\n/**\n@}\n*/ \n// end of group framework_funcs\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_GenTimer.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_GenTimer.c \n *      Purpose:      CMSIS CORE validation tests implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2017 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\"\n\n/*-----------------------------------------------------------------------------\n *      Test implementation\n *----------------------------------------------------------------------------*/\n\n/*-----------------------------------------------------------------------------\n *      Test cases\n *----------------------------------------------------------------------------*/\n\n \n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_GenTimer_CNTFRQ(void) {\n  const uint32_t cntfrq1 = __get_CNTFRQ();\n  __set_CNTFRQ(cntfrq1 + 1U);\n  const uint32_t cntfrq2 = __get_CNTFRQ();\n\n  ASSERT_TRUE((cntfrq1 + 1U) == cntfrq2);\n  \n  __set_CNTFRQ(cntfrq1);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_GenTimer_CNTP_TVAL(void) {\n  const uint32_t cntp_tval1 = __get_CNTP_TVAL();\n  __set_CNTP_TVAL(cntp_tval1 + 1U);\n  const uint32_t cntp_tval2 = __get_CNTP_TVAL();\n\n  ASSERT_TRUE((cntp_tval2 - cntp_tval1) >= 1ULL);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_GenTimer_CNTP_CTL(void) {\n  static const uint32_t CNTP_CTL_ENABLE = 0x01U;\n  const uint32_t cntp_ctl = __get_CNTP_CTL();\n  const uint32_t cntp_ctl_toggled = (cntp_ctl & (~CNTP_CTL_ENABLE)) | ((~cntp_ctl) & CNTP_CTL_ENABLE);\n  __set_CNTP_CTL(cntp_ctl_toggled);\n\n  const uint32_t cntp_ctl_new = __get_CNTP_CTL();\n\n  ASSERT_TRUE((cntp_ctl_toggled & CNTP_CTL_ENABLE) == (cntp_ctl_new & CNTP_CTL_ENABLE));\n  \n  __set_CNTP_CTL(cntp_ctl);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_GenTimer_CNTPCT(void) {\n  const uint64_t cntpct1 = __get_CNTPCT();\n  for(int i=0; i<10; i++);\n  const uint64_t cntpct2 = __get_CNTPCT();\n\n  ASSERT_TRUE((cntpct2 - cntpct1) <= 120ULL);\n}\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\nvoid TC_GenTimer_CNTP_CVAL(void) {\n  const uint64_t cntp_cval1 = __get_CNTP_CVAL();\n  __set_CNTP_CVAL(cntp_cval1 + 1ULL);\n  const uint64_t cntp_cval2 = __get_CNTP_CVAL();\n\n  ASSERT_TRUE((cntp_cval2 - cntp_cval1) >= 1ULL);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_MPU_ARMv7.c \n *      Purpose:      CMSIS CORE validation tests implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2017 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\"\n\n/*-----------------------------------------------------------------------------\n *      Test implementation\n *----------------------------------------------------------------------------*/\n\n#if defined(__MPU_PRESENT) && __MPU_PRESENT\nstatic void ClearMpu(void) {\n  for(uint32_t i = 0U; i < 8U; ++i) {\n    MPU->RNR = i;\n    MPU->RBAR = 0U;\n    MPU->RASR = 0U;\n  }\n}\n#endif\n\n/*-----------------------------------------------------------------------------\n *      Test cases\n *----------------------------------------------------------------------------*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_MPU_SetClear\n\\details\n- Check if ARM_MPU_Load correctly loads MPU table to registers.\n*/\nvoid TC_MPU_SetClear(void)\n{\n#if defined(__MPU_PRESENT) && __MPU_PRESENT\n  static const ARM_MPU_Region_t table[] = {\n    { .RBAR = 0U, .RASR = 0U },\n    { .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) },\n    { .RBAR = 0x50000000U, .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) }\n  };\n  \n  #define ASSERT_MPU_REGION(rnr, region) \\\n    MPU->RNR = rnr; \\\n    ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (region.RBAR & MPU_RBAR_ADDR_Msk)); \\\n    ASSERT_TRUE(MPU->RASR == region.RASR)\n  \n  ClearMpu();\n    \n  ARM_MPU_SetRegion(table[1].RBAR, table[1].RASR);\n  \n  ASSERT_MPU_REGION(1U, table[0]);\n  ASSERT_MPU_REGION(2U, table[1]);\n  ASSERT_MPU_REGION(3U, table[0]);\n  \n  ARM_MPU_SetRegionEx(5U, table[2].RBAR, table[2].RASR);\n  \n  ASSERT_MPU_REGION(4U, table[0]);\n  ASSERT_MPU_REGION(5U, table[2]);\n  ASSERT_MPU_REGION(6U, table[0]);\n  \n  ARM_MPU_ClrRegion(5U);\n  \n  MPU->RNR = 5U;\n  ASSERT_TRUE((MPU->RASR & MPU_RASR_ENABLE_Msk) == 0U);\n  \n  #undef ASSERT_MPU_REGION\n#endif\n}\n  \n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_MPU_Load\n\\details\n- Check if ARM_MPU_Load correctly loads MPU table to registers.\n*/\nvoid TC_MPU_Load(void)\n{\n#if defined(__MPU_PRESENT) && __MPU_PRESENT\n  static const ARM_MPU_Region_t table[] = {\n    { .RBAR = ARM_MPU_RBAR(0U, 0x10000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_32MB)  },\n    { .RBAR = ARM_MPU_RBAR(1U, 0x20000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB)  },\n    { .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) },\n    { .RBAR = ARM_MPU_RBAR(3U, 0x40000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_256MB) },\n    { .RBAR = ARM_MPU_RBAR(4U, 0x50000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_512MB) },\n    { .RBAR = ARM_MPU_RBAR(5U, 0x60000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_16MB)  },\n    { .RBAR = ARM_MPU_RBAR(6U, 0x70000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_8MB)   },\n    { .RBAR = ARM_MPU_RBAR(7U, 0x80000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_4MB)   }\n  };\n  \n  #define ASSERT_MPU_REGION(rnr, table) \\\n    MPU->RNR = rnr; \\\n    ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (table[rnr].RBAR & MPU_RBAR_ADDR_Msk)); \\\n    ASSERT_TRUE(MPU->RASR == table[rnr].RASR)\n\n  ClearMpu();\n  \n  ARM_MPU_Load(&(table[0]), 1U);\n  \n  ASSERT_MPU_REGION(0U, table);\n  \n  ARM_MPU_Load(&(table[1]), 5U);\n\n  ASSERT_MPU_REGION(0U, table);\n  ASSERT_MPU_REGION(1U, table);\n  ASSERT_MPU_REGION(2U, table);\n  ASSERT_MPU_REGION(3U, table);\n  ASSERT_MPU_REGION(4U, table);\n  ASSERT_MPU_REGION(5U, table);\n\n  ARM_MPU_Load(&(table[6]), 2U);\n\n  ASSERT_MPU_REGION(5U, table);\n  ASSERT_MPU_REGION(6U, table);\n  ASSERT_MPU_REGION(7U, table);\n\n  #undef ASSERT_MPU_REGION\n#endif\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_MPU_ARMv8.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_MPU_ARMv7.c \n *      Purpose:      CMSIS CORE validation tests implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2017 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n\n#include \"CV_Framework.h\"\n#include \"cmsis_cv.h\"\n\n/*-----------------------------------------------------------------------------\n *      Test implementation\n *----------------------------------------------------------------------------*/\n\n#if defined(__MPU_PRESENT) && __MPU_PRESENT\nstatic void ClearMpu(void) {\n  for(uint32_t i = 0U; i < 8U; ++i) {\n    MPU->RNR = i;\n    MPU->RBAR = 0U;\n    MPU->RLAR = 0U;\n  }\n}\n#endif\n\n/*-----------------------------------------------------------------------------\n *      Test cases\n *----------------------------------------------------------------------------*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_MPU_SetClear\n\\details\n- Check if ARM_MPU_Load correctly loads MPU table to registers.\n*/\nvoid TC_MPU_SetClear(void)\n{\n#if defined(__MPU_PRESENT) && __MPU_PRESENT\n  static const ARM_MPU_Region_t table[] = {\n    { .RBAR = 0U, .RLAR = 0U },\n    { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x38000000U, 0U) }\n  };\n  \n  #define ASSERT_MPU_REGION(rnr, region) \\\n    MPU->RNR = rnr; \\\n    ASSERT_TRUE(MPU->RBAR == region.RBAR); \\\n    ASSERT_TRUE(MPU->RLAR == region.RLAR)\n  \n  ClearMpu();\n    \n  ARM_MPU_SetRegion(2U, table[1].RBAR, table[1].RLAR);\n  \n  ASSERT_MPU_REGION(1U, table[0]);\n  ASSERT_MPU_REGION(2U, table[1]);\n  ASSERT_MPU_REGION(3U, table[0]);\n  \n  ARM_MPU_ClrRegion(2U);\n  \n  MPU->RNR = 2U;\n  ASSERT_TRUE((MPU->RLAR & MPU_RLAR_EN_Msk) == 0U);\n  \n  #undef ASSERT_MPU_REGION\n#endif\n}\n  \n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\brief Test case: TC_MPU_Load\n\\details\n- Check if ARM_MPU_Load correctly loads MPU table to registers.\n*/\nvoid TC_MPU_Load(void)\n{\n#if defined(__MPU_PRESENT) && __MPU_PRESENT\n  static const ARM_MPU_Region_t table[] = {\n    { .RBAR = ARM_MPU_RBAR(0x10000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x18000000U, 0U) },\n    { .RBAR = ARM_MPU_RBAR(0x20000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x27000000U, 0U) },\n    { .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x36000000U, 0U) },\n    { .RBAR = ARM_MPU_RBAR(0x40000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x45000000U, 0U) },\n    { .RBAR = ARM_MPU_RBAR(0x50000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x54000000U, 0U) },\n    { .RBAR = ARM_MPU_RBAR(0x60000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x63000000U, 0U) },\n    { .RBAR = ARM_MPU_RBAR(0x70000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x72000000U, 0U) },\n    { .RBAR = ARM_MPU_RBAR(0x80000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x31000000U, 0U) }\n  };\n  \n  #define ASSERT_MPU_REGION(rnr, table) \\\n    MPU->RNR = rnr; \\\n    ASSERT_TRUE(MPU->RBAR == table[rnr].RBAR); \\\n    ASSERT_TRUE(MPU->RLAR == table[rnr].RLAR)\n\n  ClearMpu();\n  \n  ARM_MPU_Load(0U, &(table[0]), 1U);\n  \n  ASSERT_MPU_REGION(0U, table);\n  \n  ARM_MPU_Load(1U, &(table[1]), 5U);\n\n  ASSERT_MPU_REGION(0U, table);\n  ASSERT_MPU_REGION(1U, table);\n  ASSERT_MPU_REGION(2U, table);\n  ASSERT_MPU_REGION(3U, table);\n  ASSERT_MPU_REGION(4U, table);\n  ASSERT_MPU_REGION(5U, table);\n\n  ARM_MPU_Load(6U, &(table[6]), 2U);\n\n  ASSERT_MPU_REGION(5U, table);\n  ASSERT_MPU_REGION(6U, table);\n  ASSERT_MPU_REGION(7U, table);\n\n  #undef ASSERT_MPU_REGION\n#endif \n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/CV_Report.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         cv_report.c\n *      Purpose:      Report statistics and layout implementation\n *-----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#include \"CV_Report.h\"\n#include <stdio.h>\n#include <string.h>\n\nTEST_REPORT test_report;\nstatic AS_STAT     current_assertions;   /* Current test case assertions statistics  */\n#define TAS (&test_report.assertions)         /* Total assertions             */\n#define CAS (&current_assertions)             /* Current assertions           */\n\n#ifdef DISABLE_SEMIHOSTING\n#if defined (__CC_ARM)\n  #pragma import __use_no_semihosting\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  __ASM(\".global __use_no_semihosting\");\n#endif\n#define PRINT(x)\n#define FLUSH()\nvoid _sys_exit(int return_code) {}\n#else\n#define PRINT(x) MsgPrint x\n#define FLUSH()  MsgFlush()\n#endif // DISABLE_SEMIHOSTING\n\nstatic uint8_t Passed[] = \"PASSED\";\nstatic uint8_t Warning[] = \"WARNING\";\nstatic uint8_t Failed[] = \"FAILED\";\nstatic uint8_t NotExe[] = \"NOT EXECUTED\";\n\n\n/*-----------------------------------------------------------------------------\n * Test report function prototypes\n *----------------------------------------------------------------------------*/\nstatic BOOL     tr_Init   (void);\nstatic BOOL     tc_Init   (void);\nstatic uint8_t *tr_Eval   (void);\nstatic uint8_t *tc_Eval   (void);\nstatic BOOL     StatCount (TC_RES res);\n\n/*-----------------------------------------------------------------------------\n * Printer function prototypes\n *----------------------------------------------------------------------------*/\nstatic void MsgPrint (const char *msg, ...);\nstatic void MsgFlush (void);\n\n\n/*-----------------------------------------------------------------------------\n * Assert interface function prototypes\n *----------------------------------------------------------------------------*/\nstatic BOOL As_File_Result (TC_RES res);\nstatic BOOL As_File_Dbgi   (TC_RES res, const char *fn, uint32_t ln, char *desc);\n\nTC_ITF tcitf = {\n  As_File_Result,\n  As_File_Dbgi,\n};\n\n\n/*-----------------------------------------------------------------------------\n * Test report interface function prototypes\n *----------------------------------------------------------------------------*/\nBOOL tr_File_Init  (void);\nBOOL tr_File_Open  (const char *title, const char *date, const char *time, const char *fn);\nBOOL tr_File_Close (void);\nBOOL tc_File_Open  (uint32_t num, const char *fn);\nBOOL tc_File_Close (void);\n\nREPORT_ITF ritf = {\n  tr_File_Init,\n  tr_File_Open,\n  tr_File_Close,\n  tc_File_Open,\n  tc_File_Close\n};\n\n\n/*-----------------------------------------------------------------------------\n * Init test report\n *----------------------------------------------------------------------------*/\nBOOL tr_File_Init (void) {\n  return (tr_Init());\n}\n\n\n/*-----------------------------------------------------------------------------\n * Open test report\n *----------------------------------------------------------------------------*/\n#if (PRINT_XML_REPORT==1)\nBOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn) {\n  PRINT((\"<?xml version=\\\"1.0\\\"?>\\n\"));\n  PRINT((\"<?xml-stylesheet href=\\\"TR_Style.xsl\\\" type=\\\"text/xsl\\\" ?>\\n\"));\n  PRINT((\"<report>\\n\"));\n  PRINT((\"<test>\\n\"));\n  PRINT((\"<title>%s</title>\\n\", title));\n  PRINT((\"<date>%s</date>\\n\",   date));\n  PRINT((\"<time>%s</time>\\n\",   time));\n  PRINT((\"<file>%s</file>\\n\",   fn));\n  PRINT((\"<test_cases>\\n\"));\n#else\nBOOL tr_File_Open (const char *title, const char *date, const char *time, const char __attribute__((unused)) *fn) {\n  PRINT((\"%s   %s   %s \\n\\n\", title, date, time));\n#endif\n  return (__TRUE);\n}\n\n\n/*-----------------------------------------------------------------------------\n * Open test case\n *----------------------------------------------------------------------------*/\nBOOL tc_File_Open (uint32_t num, const char *fn) {\n  (void)tc_Init ();\n#if (PRINT_XML_REPORT==1)\n  PRINT((\"<tc>\\n\"));\n  PRINT((\"<no>%d</no>\\n\",     num));\n  PRINT((\"<func>%s</func>\\n\", fn));\n  PRINT((\"<req></req>\"));\n  PRINT((\"<meth></meth>\"));\n  PRINT((\"<dbgi>\\n\"));\n#else\n  PRINT((\"TEST %02d: %-42s \", num, fn));\n#endif\n  return (__TRUE);\n}\n\n\n/*-----------------------------------------------------------------------------\n * Close test case\n *----------------------------------------------------------------------------*/\nBOOL tc_File_Close (void) {\n  uint8_t *res = tc_Eval();\n#if (PRINT_XML_REPORT==1)\n  PRINT((\"</dbgi>\\n\"));\n  PRINT((\"<res>%s</res>\\n\", res));\n  PRINT((\"</tc>\\n\"));\n#else\n  if ((res==Passed)||(res==NotExe)) {\n    PRINT((\"%s\\n\", res));\n  } else {\n    PRINT((\"\\n\"));\n  }\n#endif\n  FLUSH();\n  return (__TRUE);\n}\n\n\n/*-----------------------------------------------------------------------------\n * Close test report\n *----------------------------------------------------------------------------*/\nBOOL tr_File_Close (void) {\n#if (PRINT_XML_REPORT==1)\n  PRINT((\"</test_cases>\\n\"));\n  PRINT((\"<summary>\\n\"));\n  PRINT((\"<tcnt>%d</tcnt>\\n\", test_report.tests));\n  PRINT((\"<exec>%d</exec>\\n\", test_report.executed));\n  PRINT((\"<pass>%d</pass>\\n\", test_report.passed));\n  PRINT((\"<fail>%d</fail>\\n\", test_report.failed));\n  PRINT((\"<warn>%d</warn>\\n\", test_report.warnings));\n  PRINT((\"<tres>%s</tres>\\n\", tr_Eval()));\n  PRINT((\"</summary>\\n\"));\n  PRINT((\"</test>\\n\"));\n  PRINT((\"</report>\\n\"));\n#else\n  PRINT((\"\\nTest Summary: %d Tests, %d Executed, %d Passed, %d Failed, %d Warnings.\\n\",\n         test_report.tests,\n         test_report.executed,\n         test_report.passed,\n         test_report.failed,\n         test_report.warnings));\n  PRINT((\"Test Result: %s\\n\", tr_Eval()));\n#endif\n  FLUSH();\n  return (__TRUE);\n}\n\n\n/*-----------------------------------------------------------------------------\n * Assertion result counter\n *----------------------------------------------------------------------------*/\nstatic BOOL As_File_Result (TC_RES res) {\n  return (StatCount (res));\n}\n\n\n/*-----------------------------------------------------------------------------\n * Set debug information state\n *----------------------------------------------------------------------------*/\n#if (PRINT_XML_REPORT==1)\nstatic BOOL As_File_Dbgi (TC_RES __attribute__((unused)) res, const char *fn, uint32_t ln, char *desc) {\n  PRINT((\"<detail>\\n\"));\n  if (desc!=NULL) PRINT((\"<desc>%s</desc>\\n\", desc));\n  PRINT((\"<module>%s</module>\\n\", fn));\n  PRINT((\"<line>%d</line>\\n\", ln));\n  PRINT((\"</detail>\\n\"));\n#else\nstatic BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc) {\n  PRINT((\"\\n  %s (%d)\", fn, ln));\n  if (res==WARNING){ PRINT((\" [WARNING]\")); }\n  if (res==FAILED) { PRINT((\" [FAILED]\"));  }\n  if (desc!=NULL)  { PRINT((\" %s\", desc));  }\n#endif\n  return (__TRUE);\n}\n\n\n/*-----------------------------------------------------------------------------\n * Init test report\n *----------------------------------------------------------------------------*/\nstatic BOOL tr_Init (void) {\n  TAS->passed = 0;\n  TAS->failed = 0;\n  TAS->warnings = 0;\n  return (__TRUE);\n}\n\n\n/*-----------------------------------------------------------------------------\n * Init test case\n *----------------------------------------------------------------------------*/\nstatic BOOL tc_Init (void) {\n  CAS->passed = 0;\n  CAS->failed = 0;\n  CAS->warnings = 0;\n  return (__TRUE);\n}\n\n\n/*-----------------------------------------------------------------------------\n * Evaluate test report results\n *----------------------------------------------------------------------------*/\nstatic uint8_t *tr_Eval (void) {\n  if (test_report.failed > 0U) {\n    /* Test fails if any test case failed */\n    return (Failed);\n  }\n  else if (test_report.warnings > 0U) {\n    /* Test warns if any test case warnings */\n    return (Warning);\n  }\n  else if (test_report.passed > 0U) {\n    /* Test passes if at least one test case passed */\n    return (Passed);\n  }\n  else {\n    /* No test cases were executed */\n    return (NotExe);\n  }\n}\n\n\n/*-----------------------------------------------------------------------------\n * Evaluate test case results\n *----------------------------------------------------------------------------*/\nstatic uint8_t *tc_Eval (void) {\n  test_report.tests++;\n  test_report.executed++;\n\n  if (CAS->failed > 0U) {\n    /* Test case fails if any failed assertion recorded */\n    test_report.failed++;\n    return Failed;\n  }\n  else if (CAS->warnings > 0U) {\n    /* Test case warns if any warnings assertion recorded */\n    test_report.warnings++;\n    return Warning;\n  }\n  else if (CAS->passed > 0U) {\n    /* Test case passes if at least one assertion passed */\n    test_report.passed++;\n    return Passed;\n  }\n  else {\n    /* Assert was not invoked - nothing to evaluate */\n    test_report.executed--;\n    return NotExe;\n  }\n}\n\n\n/*-----------------------------------------------------------------------------\n * Statistics result counter\n *----------------------------------------------------------------------------*/\nstatic BOOL StatCount (TC_RES res) {\n  switch (res) {\n    case PASSED:\n      CAS->passed++;\n      TAS->passed++;\n      break;\n\n    case WARNING:\n      CAS->warnings++;\n      TAS->warnings++;\n      break;\n\n    case FAILED:\n      CAS->failed++;\n      TAS->failed++;\n      break;\n\n    case NOT_EXECUTED:\n      return (__FALSE);\n\n    default:\n      break;\n  }\n  return (__TRUE);\n}\n\n\n/*-----------------------------------------------------------------------------\n * Set result\n *----------------------------------------------------------------------------*/\nTC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc) {\n\n  // save assertion result\n  switch (res) {\n    case PASSED:\n      if (TAS->passed < BUFFER_ASSERTIONS) {\n        test_report.assertions.info.passed[TAS->passed].module = fn;\n        test_report.assertions.info.passed[TAS->passed].line = ln;\n      }\n      break;\n    case FAILED:\n      if (TAS->failed < BUFFER_ASSERTIONS) {\n        test_report.assertions.info.failed[TAS->failed].module = fn;\n        test_report.assertions.info.failed[TAS->failed].line = ln;\n      }\n      break;\n    case WARNING:\n      if (TAS->warnings < BUFFER_ASSERTIONS) {\n        test_report.assertions.info.warnings[TAS->warnings].module = fn;\n        test_report.assertions.info.warnings[TAS->warnings].line = ln;\n      }\n      break;\n    case NOT_EXECUTED:\n      break;\n\n    default:\n      break;\n  }\n\n  // set debug info (if the test case didn't pass)\n  if (res != PASSED) { (void)tcitf.Dbgi (res, fn, ln, desc); }\n  // set result\n  (void)tcitf.Result (res);\n  return (res);\n}\n\n/*-----------------------------------------------------------------------------\n * Assert true\n *----------------------------------------------------------------------------*/\nTC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond) {\n  TC_RES res = FAILED;\n  if (cond != 0U) { res = PASSED; }\n  (void)__set_result(fn, ln, res, NULL);\n  return (res);\n}\n\n#ifndef DISABLE_SEMIHOSTING\n/*-----------------------------------------------------------------------------\n *       MsgFlush:  Flush the standard output\n *----------------------------------------------------------------------------*/\nstatic void MsgFlush(void) {\n  (void)fflush(stdout);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#pragma clang diagnostic push\n#pragma clang diagnostic ignored \"-Wformat-nonliteral\"\n#endif\n/*-----------------------------------------------------------------------------\n *       MsgPrint:  Print a message to the standard output\n *----------------------------------------------------------------------------*/\nstatic void MsgPrint (const char *msg, ...) {\n  va_list args;\n  va_start(args, msg);\n  vprintf(msg, args);\n  va_end(args);\n}\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#pragma clang diagnostic pop\n#endif\n#endif // DISABLE_SEMIHOSTING\n\n/*-----------------------------------------------------------------------------\n * End of file\n *----------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config.h",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_Config.h\n *      Purpose:      CV Config header\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#ifndef __CV_CONFIG_H\n#define __CV_CONFIG_H\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n#define RTE_CV_COREINSTR 1\n#define RTE_CV_COREFUNC  1\n#define RTE_CV_CORESIMD  1\n#define RTE_CV_MPUFUNC   (__MPU_PRESENT)\n#if defined __ICACHE_PRESENT || defined __DCACHE_PRESENT\n#define RTE_CV_L1CACHE   (__ICACHE_PRESENT || __DCACHE_PRESENT)\n#endif\n\n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n\n// <h> Common Test Settings\n// <o> Print Output Format <0=> Plain Text <1=> XML\n// <i> Set the test results output format to plain text or XML\n#ifndef PRINT_XML_REPORT\n#define PRINT_XML_REPORT            1\n#endif\n// <o> Buffer size for assertions results\n// <i> Set the buffer size for assertions results buffer\n#define BUFFER_ASSERTIONS           128U\n// </h>\n\n// <h> Disable Test Cases\n// <i> Uncheck to disable an individual test case\n// <q0> TC_CoreInstr_NOP\n#define TC_COREINSTR_NOP_EN                        1\n// <q0> TC_CoreInstr_SEV\n#define TC_COREINSTR_SEV_EN                        1\n// <q0> TC_CoreInstr_BKPT\n#define TC_COREINSTR_BKPT_EN                       1\n// <q0> TC_CoreInstr_ISB\n#define TC_COREINSTR_ISB_EN                        1\n// <q0> TC_CoreInstr_DSB\n#define TC_COREINSTR_DSB_EN                        1\n// <q0> TC_CoreInstr_DMB\n#define TC_COREINSTR_DMB_EN                        1\n// <q0> TC_CoreInstr_WFI\n#define TC_COREINSTR_WFI_EN                        0\n// <q0> TC_CoreInstr_WFE\n#define TC_COREINSTR_WFE_EN                        0\n\n// <q0> TC_CoreInstr_REV\n#define TC_COREINSTR_REV_EN                        1\n// <q0> TC_CoreInstr_REV16\n#define TC_COREINSTR_REV16_EN                      1\n// <q0> TC_CoreInstr_REVSH\n#define TC_COREINSTR_REVSH_EN                      1\n// <q0> TC_CoreInstr_ROR\n#define TC_COREINSTR_ROR_EN                        1\n// <q0> TC_CoreInstr_RBIT\n#define TC_COREINSTR_RBIT_EN                       1\n// <q0> TC_CoreInstr_CLZ\n#define TC_COREINSTR_CLZ_EN                        1\n// <q0> TC_CoreInstr_SSAT\n#define TC_COREINSTR_SSAT_EN                       1\n// <q0> TC_CoreInstr_USAT\n#define TC_COREINSTR_USAT_EN                       1\n// <q0> TC_CoreInstr_RRX\n#define TC_COREINSTR_RRX_EN                        1\n// <q0> TC_CoreInstr_LoadStoreExlusive\n#define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN         1\n// <q0> TC_CoreInstr_LoadStoreUnpriv\n#define TC_COREINSTR_LOADSTOREUNPRIV_EN            1\n// <q0> TC_CoreInstr_LoadStoreAcquire\n#define TC_COREINSTR_LOADSTOREACQUIRE_EN           1\n// <q0> TC_CoreInstr_LoadStoreAcquireExclusive\n#define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN  1\n// <q0> TC_CoreInstr_UnalignedUint16\n#define TC_COREINSTR_UNALIGNEDUINT16_EN            1\n// <q0> TC_CoreInstr_UnalignedUint32\n#define TC_COREINSTR_UNALIGNEDUINT32_EN            1\n\n// <q0> TC_CoreSimd_SatAddSub\n#define TC_CORESIMD_SATADDSUB_EN                   1\n// <q0> TC_CoreSimd_ParSat16\n#define TC_CORESIMD_PARSAT16_EN                    1\n// <q0> TC_CoreSimd_PackUnpack\n#define TC_CORESIMD_PACKUNPACK_EN                  1\n// <q0> TC_CoreSimd_ParSel\n#define TC_CORESIMD_PARSEL_EN                      1\n// <q0> TC_CoreSimd_ParAddSub8\n#define TC_CORESIMD_PARADDSUB8_EN                  1\n// <q0> TC_CoreSimd_AbsDif8\n#define TC_CORESIMD_ABSDIF8_EN                     1\n// <q0> TC_CoreSimd_ParAddSub16\n#define TC_CORESIMD_PARADDSUB16_EN                 1\n// <q0> TC_CoreSimd_ParMul16\n#define TC_CORESIMD_PARMUL16_EN                    1\n// <q0> TC_CoreSimd_Pack16\n#define TC_CORESIMD_PACK16_EN                      1\n// <q0> TC_CoreSimd_MulAcc32\n#define TC_CORESIMD_MULACC32_EN                    1\n\n// <q0> TC_CoreFunc_EnDisIRQ\n#define TC_COREFUNC_ENDISIRQ_EN                    1\n// <q0> TC_CoreFunc_IRQPrio\n#define TC_COREFUNC_IRQPRIO_EN                     1\n// <q0> TC_CoreFunc_EncDecIRQPrio\n#define TC_COREFUNC_ENCDECIRQPRIO_EN               1\n// <q0> TC_CoreFunc_IRQVect\n#define TC_COREFUNC_IRQVECT_EN                     1\n// <q0> TC_CoreFunc_Control\n#define TC_COREFUNC_CONTROL_EN                     1\n// <q0> TC_CoreFunc_IPSR\n#define TC_COREFUNC_IPSR_EN                        1\n// <q0> TC_CoreFunc_APSR\n#define TC_COREFUNC_APSR_EN                        1\n// <q0> TC_CoreFunc_PSP\n#define TC_COREFUNC_PSP_EN                         1\n// <q0> TC_CoreFunc_MSP\n#define TC_COREFUNC_MSP_EN                         1\n\n// <q0> TC_CoreFunc_PSPLIM\n#define TC_COREFUNC_PSPLIM_EN                      1\n// <q0> TC_CoreFunc_PSPLIM_NS\n#define TC_COREFUNC_PSPLIM_NS_EN                   1\n// <q0> TC_CoreFunc_MSPLIM\n#define TC_COREFUNC_MSPLIM_EN                      1\n// <q0> TC_CoreFunc_MSPLIM_NS\n#define TC_COREFUNC_MSPLIM_NS_EN                   1\n// <q0> TC_CoreFunc_PRIMASK\n#define TC_COREFUNC_PRIMASK_EN                     1\n// <q0> TC_CoreFunc_FAULTMASK\n#define TC_COREFUNC_FAULTMASK_EN                   1\n// <q0> TC_CoreFunc_BASEPRI\n#define TC_COREFUNC_BASEPRI_EN                     1\n// <q0> TC_CoreFunc_FPUType\n#define TC_COREFUNC_FPUTYPE_EN                     1\n// <q0> TC_CoreFunc_FPSCR\n#define TC_COREFUNC_FPSCR_EN                       1\n\n// <q0> TC_MPU_SetClear\n#define TC_MPU_SETCLEAR_EN                         1\n// <q0> TC_MPU_Load\n#define TC_MPU_LOAD_EN                             1\n\n// <q0> TC_CML1Cache_EnDisableICache\n#define TC_CML1CACHE_ENDISABLE_ICACHE              1\n// <q0> TC_CML1Cache_EnDisableDCache\n#define TC_CML1CACHE_ENDISABLE_DCACHE              1\n// <q0> TC_CML1Cache_CleanDCacheByAddrWhileDisabled\n#define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1\n\n// </h>\n\n#endif /* __CV_CONFIG_H */\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/Config/CV_Config_template.h",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_Config.h\n *      Purpose:      CV Config header\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#ifndef __CV_CONFIG_H\n#define __CV_CONFIG_H\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n\n// <h> Common Test Settings\n// <o> Print Output Format <0=> Plain Text <1=> XML\n// <i> Set the test results output format to plain text or XML\n#ifndef PRINT_XML_REPORT\n#define PRINT_XML_REPORT            1\n#endif\n// <o> Buffer size for assertions results\n// <i> Set the buffer size for assertions results buffer\n#define BUFFER_ASSERTIONS           128U\n// </h>\n\n// <h> Disable Test Cases\n// <i> Uncheck to disable an individual test case\n// <q0> TC_CoreInstr_NOP\n#define TC_COREINSTR_NOP_EN                        1\n// <q0> TC_CoreInstr_SEV\n#define TC_COREINSTR_SEV_EN                        1\n// <q0> TC_CoreInstr_BKPT\n#define TC_COREINSTR_BKPT_EN                       1\n// <q0> TC_CoreInstr_ISB\n#define TC_COREINSTR_ISB_EN                        1\n// <q0> TC_CoreInstr_DSB\n#define TC_COREINSTR_DSB_EN                        1\n// <q0> TC_CoreInstr_DMB\n#define TC_COREINSTR_DMB_EN                        1\n// <q0> TC_CoreInstr_WFI\n#define TC_COREINSTR_WFI_EN                        0\n// <q0> TC_CoreInstr_WFE\n#define TC_COREINSTR_WFE_EN                        0\n\n// <q0> TC_CoreInstr_REV\n#define TC_COREINSTR_REV_EN                        1\n// <q0> TC_CoreInstr_REV16\n#define TC_COREINSTR_REV16_EN                      1\n// <q0> TC_CoreInstr_REVSH\n#define TC_COREINSTR_REVSH_EN                      1\n// <q0> TC_CoreInstr_ROR\n#define TC_COREINSTR_ROR_EN                        1\n// <q0> TC_CoreInstr_RBIT\n#define TC_COREINSTR_RBIT_EN                       1\n// <q0> TC_CoreInstr_CLZ\n#define TC_COREINSTR_CLZ_EN                        1\n// <q0> TC_CoreInstr_SSAT\n#define TC_COREINSTR_SSAT_EN                       1\n// <q0> TC_CoreInstr_USAT\n#define TC_COREINSTR_USAT_EN                       1\n// <q0> TC_CoreInstr_RRX\n#define TC_COREINSTR_RRX_EN                        1\n// <q0> TC_CoreInstr_LoadStoreExlusive\n#define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN         1\n// <q0> TC_CoreInstr_LoadStoreUnpriv\n#define TC_COREINSTR_LOADSTOREUNPRIV_EN            1\n// <q0> TC_CoreInstr_LoadStoreAcquire\n#define TC_COREINSTR_LOADSTOREACQUIRE_EN           1\n// <q0> TC_CoreInstr_LoadStoreAcquireExclusive\n#define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN  1\n\n// <q0> TC_CoreSimd_SatAddSub\n#define TC_CORESIMD_SATADDSUB_EN                   1\n// <q0> TC_CoreSimd_ParSat16\n#define TC_CORESIMD_PARSAT16_EN                    1\n// <q0> TC_CoreSimd_PackUnpack\n#define TC_CORESIMD_PACKUNPACK_EN                  1\n// <q0> TC_CoreSimd_ParSel\n#define TC_CORESIMD_PARSEL_EN                      1\n// <q0> TC_CoreSimd_ParAddSub8\n#define TC_CORESIMD_PARADDSUB8_EN                  1\n// <q0> TC_CoreSimd_AbsDif8\n#define TC_CORESIMD_ABSDIF8_EN                     1\n// <q0> TC_CoreSimd_ParAddSub16\n#define TC_CORESIMD_PARADDSUB16_EN                 1\n// <q0> TC_CoreSimd_ParMul16\n#define TC_CORESIMD_PARMUL16_EN                    1\n// <q0> TC_CoreSimd_Pack16\n#define TC_CORESIMD_PACK16_EN                      1\n// <q0> TC_CoreSimd_MulAcc32\n#define TC_CORESIMD_MULACC32_EN                    1\n\n// <q0> TC_CoreFunc_EnDisIRQ\n#define TC_COREFUNC_ENDISIRQ_EN                    1\n// <q0> TC_CoreFunc_IRQPrio\n#define TC_COREFUNC_IRQPRIO_EN                     1\n// <q0> TC_CoreFunc_EncDecIRQPrio\n#define TC_COREFUNC_ENCDECIRQPRIO_EN               1\n// <q0> TC_CoreFunc_IRQVect\n#define TC_COREFUNC_IRQVECT_EN                     1\n// <q0> TC_CoreFunc_Control\n#define TC_COREFUNC_CONTROL_EN                     1\n// <q0> TC_CoreFunc_IPSR\n#define TC_COREFUNC_IPSR_EN                        1\n// <q0> TC_CoreFunc_APSR\n#define TC_COREFUNC_APSR_EN                        1\n// <q0> TC_CoreFunc_PSP\n#define TC_COREFUNC_PSP_EN                         1\n// <q0> TC_CoreFunc_MSP\n#define TC_COREFUNC_MSP_EN                         1\n\n// <q0> TC_CoreFunc_PSPLIM\n#define TC_COREFUNC_PSPLIM_EN                      1\n// <q0> TC_CoreFunc_PSPLIM_NS\n#define TC_COREFUNC_PSPLIM_NS_EN                   1\n// <q0> TC_CoreFunc_MSPLIM\n#define TC_COREFUNC_MSPLIM_EN                      1\n// <q0> TC_CoreFunc_MSPLIM_NS\n#define TC_COREFUNC_MSPLIM_NS_EN                   1\n// <q0> TC_CoreFunc_PRIMASK\n#define TC_COREFUNC_PRIMASK_EN                     1\n// <q0> TC_CoreFunc_FAULTMASK\n#define TC_COREFUNC_FAULTMASK_EN                   1\n// <q0> TC_CoreFunc_BASEPRI\n#define TC_COREFUNC_BASEPRI_EN                     1\n// <q0> TC_CoreFunc_FPUType\n#define TC_COREFUNC_FPUTYPE_EN                     1\n// <q0> TC_CoreFunc_FPSCR\n#define TC_COREFUNC_FPSCR_EN                       1\n\n// <q0> TC_MPU_SetClear\n#define TC_MPU_SETCLEAR_EN                         1\n// <q0> TC_MPU_Load\n#define TC_MPU_LOAD_EN                             1\n\n// <q0> TC_CML1Cache_EnDisableICache\n#define TC_CML1CACHE_ENDISABLE_ICACHE              1\n// <q0> TC_CML1Cache_EnDisableDCache\n#define TC_CML1CACHE_ENDISABLE_DCACHE              1\n// <q0> TC_CML1Cache_CleanDCacheByAddrWhileDisabled\n#define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1\n\n// </h>\n\n#endif /* __CV_CONFIG_H */\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM23.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM23.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23\n * @version  V5.3.1\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM23_H\n#define PARTITION_ARMCM23_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n\n/*\n// <e>Setup behaviour of single SysTick\n*/\n#define SCB_ICSR_INIT 0\n\n/*\n//   <o> in a single SysTick implementation, SysTick is\n//     <0=>Secure\n//     <1=>Non-Secure\n//   <i> Value for SCB->ICSR register bit STTNS\n//   <i> only for single SysTick implementation \n*/\n#define SCB_ICSR_STTNS_VAL  0\n\n/*\n// </e>\n*/\n\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk |  SCB_AIRCR_PRIS_Msk)        )                     |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)\n    SCB->ICSR  = (SCB->ICSR  & ~(SCB_ICSR_STTNS_Msk        )) |\n                   ((SCB_ICSR_STTNS_VAL         << SCB_ICSR_STTNS_Pos)         & SCB_ICSR_STTNS_Msk);\n  #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM23_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM33.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM33.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33\n * @version  V5.3.1\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM33_H\n#define PARTITION_ARMCM33_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM33_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM35P.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM35P.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P\n * @version  V5.4.1\n * @date     03. September 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM35P_H\n#define PARTITION_ARMCM35P_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM35P_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/Config/partition_ARMCM55.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM55.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.0\n * @date     20. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM55_H\n#define PARTITION_ARMCM55_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM55_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config.h",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_Config.h\n *      Purpose:      CV Config header\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2021 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#ifndef __CV_CONFIG_H\n#define __CV_CONFIG_H\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n#define RTE_CV_COREINSTR  1\n#define RTE_CV_COREFUNC   1\n#define RTE_CV_L1CACHE    1\n\n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n\n// <h> Common Test Settings\n// <o> Print Output Format <0=> Plain Text <1=> XML\n// <i> Set the test results output format to plain text or XML\n#ifndef PRINT_XML_REPORT\n#define PRINT_XML_REPORT            1\n#endif\n// <o> Buffer size for assertions results\n// <i> Set the buffer size for assertions results buffer\n#define BUFFER_ASSERTIONS           128U\n// </h>\n\n// <h> Disable Test Cases\n// <i> Uncheck to disable an individual test case\n// <q0> TC_CoreInstr_NOP\n#define TC_COREINSTR_NOP_EN                   1\n// <q0> TC_CoreInstr_REV\n#define TC_COREINSTR_REV_EN                   1\n// <q0> TC_CoreInstr_REV16\n#define TC_COREINSTR_REV16_EN                 1\n// <q0> TC_CoreInstr_REVSH\n#define TC_COREINSTR_REVSH_EN                 1\n// <q0> TC_CoreInstr_ROR\n#define TC_COREINSTR_ROR_EN                   1\n// <q0> TC_CoreInstr_RBIT\n#define TC_COREINSTR_RBIT_EN                  1\n// <q0> TC_CoreInstr_CLZ\n#define TC_COREINSTR_CLZ_EN                   1\n// <q0> TC_CoreInstr_Exclusives\n#define TC_COREINSTR_EXCLUSIVES_EN            1\n// <q0> TC_CoreInstr_SSAT\n#define TC_COREINSTR_SSAT_EN                  1\n// <q0> TC_CoreInstr_USAT\n#define TC_COREINSTR_USAT_EN                  1\n\n// <q0> TC_CoreAFunc_IRQ\n#define TC_COREAFUNC_IRQ                      1\n// <q0> TC_CoreAFunc_FaultIRQ\n#define TC_COREAFUNC_FAULTIRQ                 1\n// <q0> TC_CoreAFunc_FPSCR\n#define TC_COREAFUNC_FPSCR                    1\n// <q0> TC_CoreAFunc_CPSR\n#define TC_COREAFUNC_CPSR                     1\n// <q0> TC_CoreAFunc_Mode\n#define TC_COREAFUNC_MODE                     1\n// <q0> TC_CoreAFunc_SP\n#define TC_COREAFUNC_SP                       1\n// <q0> TC_CoreAFunc_SP_usr\n#define TC_COREAFUNC_SP_USR                   1\n// <q0> TC_CoreAFunc_FPEXC\n#define TC_COREAFUNC_FPEXC                    1\n// <q0> TC_CoreAFunc_ACTLR\n#define TC_COREAFUNC_ACTLR                    1\n// <q0> TC_CoreAFunc_CPACR\n#define TC_COREAFUNC_CPACR                    1\n// <q0> TC_CoreAFunc_DFSR\n#define TC_COREAFUNC_DFSR                     1\n// <q0> TC_CoreAFunc_IFSR\n#define TC_COREAFUNC_IFSR                     1\n// <q0> TC_CoreAFunc_ISR\n#define TC_COREAFUNC_ISR                      1\n// <q0> TC_CoreAFunc_CBAR\n#define TC_COREAFUNC_CBAR                     1\n// <q0> TC_CoreAFunc_TTBR0\n#define TC_COREAFUNC_TTBR0                    1\n// <q0> TC_CoreAFunc_DACR\n#define TC_COREAFUNC_DACR                     1\n// <q0> TC_CoreAFunc_SCTLR\n#define TC_COREAFUNC_SCTLR                    1\n// <q0> TC_CoreAFunc_ACTRL\n#define TC_COREAFUNC_ACTRL                    1\n// <q0> TC_CoreAFunc_MPIDR\n#define TC_COREAFUNC_MPIDR                    1\n// <q0> TC_CoreAFunc_VBAR\n#define TC_COREAFUNC_VBAR                     1\n// <q0> TC_CoreAFunc_MVBAR\n#define TC_COREAFUNC_MVBAR                    1\n// <q0> TC_CoreAFunc_FPU_Enable\n#define TC_COREAFUNC_FPU_ENABLE               1\n\n// <q0> TC_GenTimer_CNTFRQ\n#define TC_GENTIMER_CNTFRQ                    1\n// <q0> TC_GenTimer_CNTP_TVAL\n#define TC_GENTIMER_CNTP_TVAL                 1\n// <q0> TC_GenTimer_CNTP_CTL\n#define TC_GENTIMER_CNTP_CTL                  1\n// <q0> TC_GenTimer_CNTPCT\n#define TC_GENTIMER_CNTPCT                    1\n// <q0> TC_GenTimer_CNTP_CVAL\n#define TC_GENTIMER_CNTP_CVAL                 1\n\n// <q0> TC_CAL1Cache_EnDisable\n#define TC_CAL1CACHE_ENDISABLE                1\n// <q0> TC_CAL1Cache_EnDisableBTAC\n#define TC_CAL1CACHE_ENDISABLEBTAC            1\n// <q0> TC_CAL1Cache_log2_up\n#define TC_CAL1CACHE_LOG2_UP                  1\n// <q0> TC_CAL1Cache_InvalidateDCacheAll\n#define TC_CAL1CACHE_INVALIDATEDCACHEALL      1\n// <q0> TC_CAL1Cache_CleanDCacheAll\n#define TC_CAL1CACHE_CLEANDCACHEALL           1\n// <q0> TC_CAL1Cache_CleanInvalidateDCacheAll\n#define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1\n// </h>\n\n#endif /* __CV_CONFIG_H */\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/ConfigA/CV_Config_template.h",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         CV_Config.h\n *      Purpose:      CV Config header\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2021 ARM Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#ifndef __CV_CONFIG_H\n#define __CV_CONFIG_H\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n\n// <h> Common Test Settings\n// <o> Print Output Format <0=> Plain Text <1=> XML\n// <i> Set the test results output format to plain text or XML\n#ifndef PRINT_XML_REPORT\n#define PRINT_XML_REPORT            0\n#endif\n// <o> Buffer size for assertions results\n// <i> Set the buffer size for assertions results buffer\n#define BUFFER_ASSERTIONS           128U\n// </h>\n\n// <h> Disable Test Cases\n// <i> Uncheck to disable an individual test case\n// <q0> TC_CoreInstr_NOP\n#define TC_COREINSTR_NOP_EN                   1\n// <q0> TC_CoreInstr_REV\n#define TC_COREINSTR_REV_EN                   1\n// <q0> TC_CoreInstr_REV16\n#define TC_COREINSTR_REV16_EN                 1\n// <q0> TC_CoreInstr_REVSH\n#define TC_COREINSTR_REVSH_EN                 1\n// <q0> TC_CoreInstr_ROR\n#define TC_COREINSTR_ROR_EN                   1\n// <q0> TC_CoreInstr_RBIT\n#define TC_COREINSTR_RBIT_EN                  1\n// <q0> TC_CoreInstr_CLZ\n#define TC_COREINSTR_CLZ_EN                   1\n// <q0> TC_CoreInstr_Exclusives\n#define TC_COREINSTR_EXCLUSIVES_EN            1\n// <q0> TC_CoreInstr_SSAT\n#define TC_COREINSTR_SSAT_EN                  1\n// <q0> TC_CoreInstr_USAT\n#define TC_COREINSTR_USAT_EN                  1\n\n// <q0> TC_CoreAFunc_IRQ\n#define TC_COREAFUNC_IRQ                      1\n// <q0> TC_CoreAFunc_FaultIRQ\n#define TC_COREAFUNC_FAULTIRQ                 1\n// <q0> TC_CoreAFunc_FPSCR\n#define TC_COREAFUNC_FPSCR                    1\n// <q0> TC_CoreAFunc_CPSR\n#define TC_COREAFUNC_CPSR                     1\n// <q0> TC_CoreAFunc_Mode\n#define TC_COREAFUNC_MODE                     1\n// <q0> TC_CoreAFunc_SP\n#define TC_COREAFUNC_SP                       1\n// <q0> TC_CoreAFunc_SP_usr\n#define TC_COREAFUNC_SP_USR                   1\n// <q0> TC_CoreAFunc_FPEXC\n#define TC_COREAFUNC_FPEXC                    1\n// <q0> TC_CoreAFunc_ACTLR\n#define TC_COREAFUNC_ACTLR                    1\n// <q0> TC_CoreAFunc_CPACR\n#define TC_COREAFUNC_CPACR                    1\n// <q0> TC_CoreAFunc_DFSR\n#define TC_COREAFUNC_DFSR                     1\n// <q0> TC_CoreAFunc_IFSR\n#define TC_COREAFUNC_IFSR                     1\n// <q0> TC_CoreAFunc_ISR\n#define TC_COREAFUNC_ISR                      1\n// <q0> TC_CoreAFunc_CBAR\n#define TC_COREAFUNC_CBAR                     1\n// <q0> TC_CoreAFunc_TTBR0\n#define TC_COREAFUNC_TTBR0                    1\n// <q0> TC_CoreAFunc_DACR\n#define TC_COREAFUNC_DACR                     1\n// <q0> TC_CoreAFunc_SCTLR\n#define TC_COREAFUNC_SCTLR                    1\n// <q0> TC_CoreAFunc_ACTRL\n#define TC_COREAFUNC_ACTRL                    1\n// <q0> TC_CoreAFunc_MPIDR\n#define TC_COREAFUNC_MPIDR                    1\n// <q0> TC_CoreAFunc_VBAR\n#define TC_COREAFUNC_VBAR                     1\n// <q0> TC_CoreAFunc_MVBAR\n#define TC_COREAFUNC_MVBAR                    1\n// <q0> TC_CoreAFunc_FPU_Enable\n#define TC_COREAFUNC_FPU_ENABLE               1\n\n// <q0> TC_GenTimer_CNTFRQ\n#define TC_GENTIMER_CNTFRQ                    1\n// <q0> TC_GenTimer_CNTP_TVAL\n#define TC_GENTIMER_CNTP_TVAL                 1\n// <q0> TC_GenTimer_CNTP_CTL\n#define TC_GENTIMER_CNTP_CTL                  1\n// <q0> TC_GenTimer_CNTPCT\n#define TC_GENTIMER_CNTPCT                    1\n// <q0> TC_GenTimer_CNTP_CVAL\n#define TC_GENTIMER_CNTP_CVAL                 1\n\n// <q0> TC_CAL1Cache_EnDisable\n#define TC_CAL1CACHE_ENDISABLE                1\n// <q0> TC_CAL1Cache_EnDisableBTAC\n#define TC_CAL1CACHE_ENDISABLEBTAC            1\n// <q0> TC_CAL1Cache_log2_up\n#define TC_CAL1CACHE_LOG2_UP                  1\n// <q0> TC_CAL1Cache_InvalidateDCacheAll\n#define TC_CAL1CACHE_INVALIDATEDCACHEALL      1\n// <q0> TC_CAL1Cache_CleanDCacheAll\n#define TC_CAL1CACHE_CLEANDCACHEALL           1\n// <q0> TC_CAL1Cache_CleanInvalidateDCacheAll\n#define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1\n// </h>\n\n#endif /* __CV_CONFIG_H */\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/CoreValidation/Source/cmsis_cv.c",
    "content": "/*-----------------------------------------------------------------------------\n *      Name:         cmsis_cv.c\n *      Purpose:      Driver validation test cases entry point\n *----------------------------------------------------------------------------\n *      Copyright (c) 2017 - 2021 Arm Limited. All rights reserved.\n *----------------------------------------------------------------------------*/\n#include \"cmsis_cv.h\"\n#include \"RTE_Components.h\"\n#include \"CV_Framework.h\"\n#include \"CV_Config.h\"\n\n/*-----------------------------------------------------------------------------\n *      Prototypes\n *----------------------------------------------------------------------------*/\n\nvoid Interrupt0_Handler(void);\n\n/*-----------------------------------------------------------------------------\n *      Variables declarations\n *----------------------------------------------------------------------------*/\n\nvoid (*TST_IRQHandler)(void);\n\nvoid Interrupt0_Handler(void) {\n  if (TST_IRQHandler != NULL) TST_IRQHandler();\n}\n\n/*-----------------------------------------------------------------------------\n *      Init test suite\n *----------------------------------------------------------------------------*/\nstatic void TS_Init (void) {\n  TST_IRQHandler = NULL;\n\n#ifdef RTE_CV_MEASURETICKS\n  StartCortexCycleCounter();\n#endif\n}\n\n/*-----------------------------------------------------------------------------\n *      Test cases list\n *----------------------------------------------------------------------------*/\nstatic TEST_CASE TC_LIST[] = {\n#if defined(RTE_CV_COREINSTR) && RTE_CV_COREINSTR\n  #if defined(__CORTEX_M)\n    TCD ( TC_CoreInstr_NOP,                        TC_COREINSTR_NOP_EN                       ),\n    TCD ( TC_CoreInstr_WFI,                        TC_COREINSTR_WFI_EN                       ),\n    TCD ( TC_CoreInstr_WFE,                        TC_COREINSTR_WFE_EN                       ),\n    TCD ( TC_CoreInstr_SEV,                        TC_COREINSTR_SEV_EN                       ),\n    TCD ( TC_CoreInstr_BKPT,                       TC_COREINSTR_BKPT_EN                      ),\n    TCD ( TC_CoreInstr_ISB,                        TC_COREINSTR_ISB_EN                       ),\n    TCD ( TC_CoreInstr_DSB,                        TC_COREINSTR_DSB_EN                       ),\n    TCD ( TC_CoreInstr_DMB,                        TC_COREINSTR_DMB_EN                       ),\n    TCD ( TC_CoreInstr_REV,                        TC_COREINSTR_REV_EN                       ),\n    TCD ( TC_CoreInstr_REV16,                      TC_COREINSTR_REV16_EN                     ),\n    TCD ( TC_CoreInstr_REVSH,                      TC_COREINSTR_REVSH_EN                     ),\n    TCD ( TC_CoreInstr_ROR,                        TC_COREINSTR_ROR_EN                       ),\n    TCD ( TC_CoreInstr_RBIT,                       TC_COREINSTR_RBIT_EN                      ),\n    TCD ( TC_CoreInstr_CLZ,                        TC_COREINSTR_CLZ_EN                       ),\n    TCD ( TC_CoreInstr_SSAT,                       TC_COREINSTR_SSAT_EN                      ),\n    TCD ( TC_CoreInstr_USAT,                       TC_COREINSTR_USAT_EN                      ),\n    TCD ( TC_CoreInstr_RRX,                        TC_COREINSTR_RRX_EN                       ),\n    TCD ( TC_CoreInstr_LoadStoreExclusive,         TC_COREINSTR_LOADSTOREEXCLUSIVE_EN        ),\n    TCD ( TC_CoreInstr_LoadStoreUnpriv,            TC_COREINSTR_LOADSTOREUNPRIV_EN           ),\n    TCD ( TC_CoreInstr_LoadStoreAcquire,           TC_COREINSTR_LOADSTOREACQUIRE_EN          ),\n    TCD ( TC_CoreInstr_LoadStoreAcquireExclusive,  TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN ),\n    TCD ( TC_CoreInstr_UnalignedUint16,            TC_COREINSTR_UNALIGNEDUINT16_EN           ),\n    TCD ( TC_CoreInstr_UnalignedUint32,            TC_COREINSTR_UNALIGNEDUINT32_EN           ),\n\n  #elif defined(__CORTEX_A)\n    TCD (TC_CoreInstr_NOP,                         TC_COREINSTR_NOP_EN                 ),\n    TCD (TC_CoreInstr_REV,                         TC_COREINSTR_REV_EN                 ),\n    TCD (TC_CoreInstr_REV16,                       TC_COREINSTR_REV16_EN               ),\n    TCD (TC_CoreInstr_REVSH,                       TC_COREINSTR_REVSH_EN               ),\n    TCD (TC_CoreInstr_ROR,                         TC_COREINSTR_ROR_EN                 ),\n    TCD (TC_CoreInstr_RBIT,                        TC_COREINSTR_RBIT_EN                ),\n    TCD (TC_CoreInstr_CLZ,                         TC_COREINSTR_CLZ_EN                 ),\n    TCD (TC_CoreInstr_SSAT,                        TC_COREINSTR_SSAT_EN                ),\n    TCD (TC_CoreInstr_USAT,                        TC_COREINSTR_USAT_EN                ),\n    TCD (TC_CoreInstr_LoadStoreExclusive,          TC_COREINSTR_EXCLUSIVES_EN          ),\n  #endif\n#endif /* RTE_CV_COREINSTR */\n\n#if defined (RTE_CV_CORESIMD) && RTE_CV_CORESIMD\n    TCD ( TC_CoreSimd_SatAddSub,                   TC_CORESIMD_SATADDSUB_EN                  ),\n    TCD ( TC_CoreSimd_ParSat16,                    TC_CORESIMD_PARSAT16_EN                   ),\n    TCD ( TC_CoreSimd_PackUnpack,                  TC_CORESIMD_PACKUNPACK_EN                 ),\n    TCD ( TC_CoreSimd_ParSel,                      TC_CORESIMD_PARSEL_EN                     ),\n    TCD ( TC_CoreSimd_ParAddSub8,                  TC_CORESIMD_PARADDSUB8_EN                 ),\n    TCD ( TC_CoreSimd_AbsDif8,                     TC_CORESIMD_ABSDIF8_EN                    ),\n    TCD ( TC_CoreSimd_ParAddSub16,                 TC_CORESIMD_PARADDSUB16_EN                ),\n    TCD ( TC_CoreSimd_ParMul16,                    TC_CORESIMD_PARMUL16_EN                   ),\n    TCD ( TC_CoreSimd_Pack16,                      TC_CORESIMD_PACK16_EN                     ),\n    TCD ( TC_CoreSimd_MulAcc32,                    TC_CORESIMD_MULACC32_EN                   ),\n#endif /* RTE_CV_CORESIMD */\n\n#if defined(RTE_CV_COREFUNC) && RTE_CV_COREFUNC\n  #if defined(__CORTEX_M)\n    TCD ( TC_CoreFunc_EnDisIRQ,                    TC_COREFUNC_ENDISIRQ_EN                   ),\n    TCD ( TC_CoreFunc_IRQPrio,                     TC_COREFUNC_IRQPRIO_EN                    ),\n    TCD ( TC_CoreFunc_EncDecIRQPrio,               TC_COREFUNC_ENCDECIRQPRIO_EN              ),\n    TCD ( TC_CoreFunc_IRQVect,                     TC_COREFUNC_IRQVECT_EN                    ),\n    TCD ( TC_CoreFunc_Control,                     TC_COREFUNC_CONTROL_EN                    ),\n    TCD ( TC_CoreFunc_IPSR,                        TC_COREFUNC_IPSR_EN                       ),\n    TCD ( TC_CoreFunc_APSR,                        TC_COREFUNC_APSR_EN                       ),\n    TCD ( TC_CoreFunc_PSP,                         TC_COREFUNC_PSP_EN                        ),\n    TCD ( TC_CoreFunc_MSP,                         TC_COREFUNC_MSP_EN                        ),\n    TCD ( TC_CoreFunc_PSPLIM,                      TC_COREFUNC_PSPLIM_EN                     ),\n    TCD ( TC_CoreFunc_PSPLIM_NS,                   TC_COREFUNC_PSPLIM_NS_EN                  ),\n    TCD ( TC_CoreFunc_MSPLIM,                      TC_COREFUNC_MSPLIM_EN                     ),\n    TCD ( TC_CoreFunc_MSPLIM_NS,                   TC_COREFUNC_MSPLIM_NS_EN                  ),\n    TCD ( TC_CoreFunc_PRIMASK,                     TC_COREFUNC_PRIMASK_EN                    ),\n    TCD ( TC_CoreFunc_FAULTMASK,                   TC_COREFUNC_FAULTMASK_EN                  ),\n    TCD ( TC_CoreFunc_BASEPRI,                     TC_COREFUNC_BASEPRI_EN                    ),\n    TCD ( TC_CoreFunc_FPUType,                     TC_COREFUNC_FPUTYPE_EN                    ),\n    TCD ( TC_CoreFunc_FPSCR,                       TC_COREFUNC_FPSCR_EN                      ),\n\n  #elif defined(__CORTEX_A)\n    TCD ( TC_CoreAFunc_IRQ,                        TC_COREAFUNC_IRQ                          ),\n    TCD ( TC_CoreAFunc_FaultIRQ,                   TC_COREAFUNC_FAULTIRQ                     ),\n    TCD ( TC_CoreAFunc_FPSCR,                      TC_COREAFUNC_FPSCR                        ),\n    TCD ( TC_CoreAFunc_CPSR,                       TC_COREAFUNC_CPSR                         ),\n    TCD ( TC_CoreAFunc_Mode,                       TC_COREAFUNC_MODE                         ),\n    TCD ( TC_CoreAFunc_SP,                         TC_COREAFUNC_SP                           ),\n    TCD ( TC_CoreAFunc_SP_usr,                     TC_COREAFUNC_SP_USR                       ),\n    TCD ( TC_CoreAFunc_FPEXC,                      TC_COREAFUNC_FPEXC                        ),\n    TCD ( TC_CoreAFunc_ACTLR,                      TC_COREAFUNC_ACTLR                        ),\n    TCD ( TC_CoreAFunc_CPACR,                      TC_COREAFUNC_CPACR                        ),\n    TCD ( TC_CoreAFunc_DFSR,                       TC_COREAFUNC_DFSR                         ),\n    TCD ( TC_CoreAFunc_IFSR,                       TC_COREAFUNC_IFSR                         ),\n    TCD ( TC_CoreAFunc_ISR,                        TC_COREAFUNC_ISR                          ),\n    TCD ( TC_CoreAFunc_CBAR,                       TC_COREAFUNC_CBAR                         ),\n    TCD ( TC_CoreAFunc_TTBR0,                      TC_COREAFUNC_TTBR0                        ),\n    TCD ( TC_CoreAFunc_DACR,                       TC_COREAFUNC_DACR                         ),\n    TCD ( TC_CoreAFunc_SCTLR,                      TC_COREAFUNC_SCTLR                        ),\n    TCD ( TC_CoreAFunc_ACTRL,                      TC_COREAFUNC_ACTRL                        ),\n    TCD ( TC_CoreAFunc_MPIDR,                      TC_COREAFUNC_MPIDR                        ),\n    TCD ( TC_CoreAFunc_VBAR,                       TC_COREAFUNC_VBAR                         ),\n    TCD ( TC_CoreAFunc_MVBAR,                      TC_COREAFUNC_MVBAR                        ),\n    TCD ( TC_CoreAFunc_FPU_Enable,                 TC_COREAFUNC_FPU_ENABLE                   ),\n  #endif\n#endif /* RTE_CV_COREFUNC */\n\n#if defined(RTE_CV_MPUFUNC) && RTE_CV_MPUFUNC\n    TCD ( TC_MPU_SetClear,                         TC_MPU_SETCLEAR_EN                        ),\n    TCD ( TC_MPU_Load,                             TC_MPU_LOAD_EN                            ),\n#endif /* RTE_CV_MPUFUNC */\n\n#if defined(RTE_CV_GENTIMER) && RTE_CV_GENTIMER\n    TCD ( TC_GenTimer_CNTFRQ,                      TC_GENTIMER_CNTFRQ                        ),\n    TCD ( TC_GenTimer_CNTP_TVAL,                   TC_GENTIMER_CNTP_TVAL                     ),\n    TCD ( TC_GenTimer_CNTP_CTL,                    TC_GENTIMER_CNTP_CTL                      ),\n    TCD ( TC_GenTimer_CNTPCT,                      TC_GENTIMER_CNTPCT                        ),\n    TCD ( TC_GenTimer_CNTP_CVAL,                   TC_GENTIMER_CNTP_CVAL                     ),\n#endif /* RTE_CV_GENTIMER */\n\n#if defined(RTE_CV_L1CACHE) && RTE_CV_L1CACHE\n  #if defined(__CORTEX_M)\n    TCD ( TC_CML1Cache_EnDisableICache,              TC_CML1CACHE_ENDISABLE_ICACHE          ),\n    TCD ( TC_CML1Cache_EnDisableDCache,              TC_CML1CACHE_ENDISABLE_DCACHE          ),\n    TCD ( TC_CML1Cache_CleanDCacheByAddrWhileDisabled, TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED),\n  #elif defined(__CORTEX_A)\n    TCD ( TC_CAL1Cache_EnDisable,                    TC_CAL1CACHE_ENDISABLE                 ),\n    TCD ( TC_CAL1Cache_EnDisableBTAC,                TC_CAL1CACHE_ENDISABLEBTAC             ),\n    TCD ( TC_CAL1Cache_log2_up,                      TC_CAL1CACHE_LOG2_UP                   ),\n    TCD ( TC_CAL1Cache_InvalidateDCacheAll,          TC_CAL1CACHE_INVALIDATEDCACHEALL       ),\n    TCD ( TC_CAL1Cache_CleanDCacheAll,               TC_CAL1CACHE_CLEANDCACHEALL            ),\n    TCD ( TC_CAL1Cache_CleanInvalidateDCacheAll,     TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL  ),\n  #endif \n#endif /* RTE_CV_L1CACHE */\n};\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#pragma clang diagnostic push\n#pragma clang diagnostic ignored \"-Wdate-time\"\n#endif\n/*-----------------------------------------------------------------------------\n *      Test suite description\n *----------------------------------------------------------------------------*/\nTEST_SUITE ts = {\n  __FILE__, __DATE__, __TIME__,\n  \"CMSIS-CORE Test Suite\",\n  TS_Init,\n  1,\n  TC_LIST,\n  ARRAY_SIZE (TC_LIST),\n};\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#pragma clang diagnostic pop\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armcc.h\n * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file\n * @version  V1.0.6\n * @date     13. November 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_ARMCC_H\n#define __CMSIS_ARMCC_H\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\n  #error \"Please use Arm Compiler Toolchain V4.0.677 or later!\"\n#endif\n\n/* CMSIS compiler control architecture macros */\n#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A  == 1))\n  #define __ARM_ARCH_7A__           1\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __FORCEINLINE\n  #define __FORCEINLINE                          __forceinline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   static __forceinline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __declspec(noreturn)\n#endif\n#ifndef   CMSIS_DEPRECATED\n  #define CMSIS_DEPRECATED                       __attribute__((deprecated))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        __packed struct\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         __packed union\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __memory_changed()\n#endif\n\n/* ##########################  Core Instruction Access  ######################### */\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP                             __nop\n\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI                             __wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE                             __wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV                             __sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()                           __isb(0xF)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()                           __dsb(0xF)\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()                           __dmb(0xF)\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV                             __rev\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".rev16_text\"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\n{\n  rev16 r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".revsh_text\"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\n{\n  revsh r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n#define __ROR                             __ror\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                     __breakpoint(value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT                            __rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ                             __clz\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))\n#else\n  #define __LDREXB(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint8_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))\n#else\n  #define __LDREXH(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint16_t) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))\n#else\n  #define __LDREXW(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint32_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXB(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXB(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXH(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXH(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXW(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXW(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX                           __clrex\n\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT                            __ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT                            __usat\n\n/* ###########################  Core Function Access  ########################### */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq(); */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting special-purpose register PRIMASK.\n  Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq(void); */\n\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq\n\n/**\n  \\brief   Get FPSCR (Floating Point Status/Control)\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_INLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  return(__regfpscr);\n#else\n   return(0U);\n#endif\n}\n\n/**\n  \\brief   Set FPSCR (Floating Point Status/Control)\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  __regfpscr = (fpscr);\n#else\n  (void)fpscr;\n#endif\n}\n\n/** \\brief  Get CPSR (Current Program Status Register)\n    \\return               CPSR Register value\n */\n__STATIC_INLINE uint32_t __get_CPSR(void)\n{\n  register uint32_t __regCPSR          __ASM(\"cpsr\");\n  return(__regCPSR);\n}\n\n\n/** \\brief  Set CPSR (Current Program Status Register)\n    \\param [in]    cpsr  CPSR value to set\n */\n__STATIC_INLINE void __set_CPSR(uint32_t cpsr)\n{\n  register uint32_t __regCPSR          __ASM(\"cpsr\");\n  __regCPSR = cpsr;\n}\n\n/** \\brief  Get Mode\n    \\return                Processor Mode\n */\n__STATIC_INLINE uint32_t __get_mode(void)\n{\n  return (__get_CPSR() & 0x1FU);\n}\n\n/** \\brief  Set Mode\n    \\param [in]    mode  Mode value to set\n */\n__STATIC_INLINE __ASM void __set_mode(uint32_t mode)\n{\n  MOV  r1, lr\n  MSR  CPSR_C, r0\n  BX   r1\n}\n\n/** \\brief  Get Stack Pointer\n    \\return Stack Pointer\n */\n__STATIC_INLINE __ASM uint32_t __get_SP(void)\n{\n  MOV  r0, sp\n  BX   lr\n}\n\n/** \\brief  Set Stack Pointer\n    \\param [in]    stack  Stack Pointer value to set\n */\n__STATIC_INLINE __ASM void __set_SP(uint32_t stack)\n{\n  MOV  sp, r0\n  BX   lr\n}\n\n\n/** \\brief  Get USR/SYS Stack Pointer\n    \\return USR/SYSStack Pointer\n */\n__STATIC_INLINE __ASM uint32_t __get_SP_usr(void)\n{\n  ARM\n  PRESERVE8\n\n  MRS     R1, CPSR\n  CPS     #0x1F       ;no effect in USR mode\n  MOV     R0, SP\n  MSR     CPSR_c, R1  ;no effect in USR mode\n  ISB\n  BX      LR\n}\n\n/** \\brief  Set USR/SYS Stack Pointer\n    \\param [in]    topOfProcStack  USR/SYS Stack Pointer value to set\n */\n__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)\n{\n  ARM\n  PRESERVE8\n\n  MRS     R1, CPSR\n  CPS     #0x1F       ;no effect in USR mode\n  MOV     SP, R0\n  MSR     CPSR_c, R1  ;no effect in USR mode\n  ISB\n  BX      LR\n}\n\n/** \\brief  Get FPEXC (Floating Point Exception Control Register)\n    \\return               Floating Point Exception Control Register value\n */\n__STATIC_INLINE uint32_t __get_FPEXC(void)\n{\n#if (__FPU_PRESENT == 1)\n  register uint32_t __regfpexc         __ASM(\"fpexc\");\n  return(__regfpexc);\n#else\n  return(0);\n#endif\n}\n\n/** \\brief  Set FPEXC (Floating Point Exception Control Register)\n    \\param [in]    fpexc  Floating Point Exception Control value to set\n */\n__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)\n{\n#if (__FPU_PRESENT == 1)\n  register uint32_t __regfpexc         __ASM(\"fpexc\");\n  __regfpexc = (fpexc);\n#endif\n}\n\n/*\n * Include common core functions to access Coprocessor 15 registers\n */\n\n#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM(\"cp\" # cp \":\" # op1 \":c\" # CRn \":c\" # CRm \":\" # op2); (Rt) = tmp; } while(0)\n#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM(\"cp\" # cp \":\" # op1 \":c\" # CRn \":c\" # CRm \":\" # op2); tmp = (Rt); } while(0)\n#define __get_CP64(cp, op1, Rt, CRm) \\\n  do { \\\n    uint32_t ltmp, htmp; \\\n    __ASM volatile(\"MRRC p\" # cp \", \" # op1 \", ltmp, htmp, c\" # CRm); \\\n    (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \\\n  } while(0)\n\n#define __set_CP64(cp, op1, Rt, CRm) \\\n  do { \\\n    const uint64_t tmp = (Rt); \\\n    const uint32_t ltmp = (uint32_t)(tmp); \\\n    const uint32_t htmp = (uint32_t)(tmp >> 32U); \\\n    __ASM volatile(\"MCRR p\" # cp \", \" # op1 \", ltmp, htmp, c\" # CRm); \\\n  } while(0)\n\n#include \"cmsis_cp15.h\"\n\n/** \\brief  Enable Floating Point Unit\n\n  Critical section, called from undef handler, so systick is disabled\n */\n__STATIC_INLINE __ASM void __FPU_Enable(void)\n{\n        ARM\n\n        //Permit access to VFP/NEON, registers by modifying CPACR\n        MRC     p15,0,R1,c1,c0,2\n        ORR     R1,R1,#0x00F00000\n        MCR     p15,0,R1,c1,c0,2\n\n        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted\n        ISB\n\n        //Enable VFP/NEON\n        VMRS    R1,FPEXC\n        ORR     R1,R1,#0x40000000\n        VMSR    FPEXC,R1\n\n        //Initialise VFP/NEON registers to 0\n        MOV     R2,#0\n\n        //Initialise D16 registers to 0\n        VMOV    D0, R2,R2\n        VMOV    D1, R2,R2\n        VMOV    D2, R2,R2\n        VMOV    D3, R2,R2\n        VMOV    D4, R2,R2\n        VMOV    D5, R2,R2\n        VMOV    D6, R2,R2\n        VMOV    D7, R2,R2\n        VMOV    D8, R2,R2\n        VMOV    D9, R2,R2\n        VMOV    D10,R2,R2\n        VMOV    D11,R2,R2\n        VMOV    D12,R2,R2\n        VMOV    D13,R2,R2\n        VMOV    D14,R2,R2\n        VMOV    D15,R2,R2\n\n  IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32\n        //Initialise D32 registers to 0\n        VMOV    D16,R2,R2\n        VMOV    D17,R2,R2\n        VMOV    D18,R2,R2\n        VMOV    D19,R2,R2\n        VMOV    D20,R2,R2\n        VMOV    D21,R2,R2\n        VMOV    D22,R2,R2\n        VMOV    D23,R2,R2\n        VMOV    D24,R2,R2\n        VMOV    D25,R2,R2\n        VMOV    D26,R2,R2\n        VMOV    D27,R2,R2\n        VMOV    D28,R2,R2\n        VMOV    D29,R2,R2\n        VMOV    D30,R2,R2\n        VMOV    D31,R2,R2\n  ENDIF\n\n        //Initialise FPSCR to a known state\n        VMRS    R1,FPSCR\n        LDR     R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.\n        AND     R1,R1,R2\n        VMSR    FPSCR,R1\n\n        BX      LR\n}\n\n#endif /* __CMSIS_ARMCC_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core_A/Include/cmsis_armclang.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armclang.h\n * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\n * @version  V1.2.2\n * @date     13. November 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_ARMCLANG_H\n#define __CMSIS_ARMCLANG_H\n\n#pragma clang system_header   /* treat file as system include file */\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __FORCEINLINE\n  #define __FORCEINLINE                          __attribute__((always_inline))\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   CMSIS_DEPRECATED\n  #define CMSIS_DEPRECATED                       __attribute__((deprecated))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed))\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n\n/* ##########################  Core Instruction Access  ######################### */\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP                             __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI                             __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE                             __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV                             __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()                           __builtin_arm_isb(0xF)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()                           __builtin_arm_dsb(0xF)\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()                           __builtin_arm_dmb(0xF)\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV(value)   __builtin_bswap32(value)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16(value) __ROR(__REV(value), 16)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REVSH(value) (int16_t)__builtin_bswap16(value)\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)   __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT          __builtin_arm_rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT             __builtin_arm_ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n#define     __SADD8                 __builtin_arm_sadd8\n#define     __SADD16                __builtin_arm_sadd16\n#define     __QADD8                 __builtin_arm_qadd8\n#define     __QSUB8                 __builtin_arm_qsub8\n#define     __QADD16                __builtin_arm_qadd16\n#define     __SHADD16               __builtin_arm_shadd16\n#define     __QSUB16                __builtin_arm_qsub16\n#define     __SHSUB16               __builtin_arm_shsub16\n#define     __QASX                  __builtin_arm_qasx\n#define     __SHASX                 __builtin_arm_shasx\n#define     __QSAX                  __builtin_arm_qsax\n#define     __SHSAX                 __builtin_arm_shsax\n#define     __SXTB16                __builtin_arm_sxtb16\n#define     __SMUAD                 __builtin_arm_smuad\n#define     __SMUADX                __builtin_arm_smuadx\n#define     __SMLAD                 __builtin_arm_smlad\n#define     __SMLADX                __builtin_arm_smladx\n#define     __SMLALD                __builtin_arm_smlald\n#define     __SMLALDX               __builtin_arm_smlaldx\n#define     __SMUSD                 __builtin_arm_smusd\n#define     __SMUSDX                __builtin_arm_smusdx\n#define     __SMLSDX                __builtin_arm_smlsdx\n#define     __USAT16                __builtin_arm_usat16\n#define     __SSUB8                 __builtin_arm_ssub8\n#define     __SXTB16                __builtin_arm_sxtb16\n#define     __SXTAB16               __builtin_arm_sxtab16\n\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n  int32_t result;\n\n  __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n\n/* ###########################  Core Function Access  ########################### */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n  Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#define __get_FPSCR      __builtin_arm_get_fpscr\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#define __set_FPSCR      __builtin_arm_set_fpscr\n\n/** \\brief  Get CPSR Register\n    \\return               CPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CPSR(void)\n{\n  uint32_t result;\n  __ASM volatile(\"MRS %0, cpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n/** \\brief  Set CPSR Register\n    \\param [in]    cpsr  CPSR value to set\n */\n__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)\n{\n  __ASM volatile (\"MSR cpsr, %0\" : : \"r\" (cpsr) : \"cc\", \"memory\");\n}\n\n/** \\brief  Get Mode\n    \\return                Processor Mode\n */\n__STATIC_FORCEINLINE uint32_t __get_mode(void)\n{\n  return (__get_CPSR() & 0x1FU);\n}\n\n/** \\brief  Set Mode\n    \\param [in]    mode  Mode value to set\n */\n__STATIC_FORCEINLINE void __set_mode(uint32_t mode)\n{\n  __ASM volatile(\"MSR  cpsr_c, %0\" : : \"r\" (mode) : \"memory\");\n}\n\n/** \\brief  Get Stack Pointer\n    \\return Stack Pointer value\n */\n__STATIC_FORCEINLINE uint32_t __get_SP(void)\n{\n  uint32_t result;\n  __ASM volatile(\"MOV  %0, sp\" : \"=r\" (result) : : \"memory\");\n  return result;\n}\n\n/** \\brief  Set Stack Pointer\n    \\param [in]    stack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_SP(uint32_t stack)\n{\n  __ASM volatile(\"MOV  sp, %0\" : : \"r\" (stack) : \"memory\");\n}\n\n/** \\brief  Get USR/SYS Stack Pointer\n    \\return USR/SYS Stack Pointer value\n */\n__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)\n{\n  uint32_t cpsr;\n  uint32_t result;\n  __ASM volatile(\n    \"MRS     %0, cpsr   \\n\"\n    \"CPS     #0x1F      \\n\" // no effect in USR mode\n    \"MOV     %1, sp     \\n\"\n    \"MSR     cpsr_c, %0 \\n\" // no effect in USR mode\n    \"ISB\" :  \"=r\"(cpsr), \"=r\"(result) : : \"memory\"\n   );\n  return result;\n}\n\n/** \\brief  Set USR/SYS Stack Pointer\n    \\param [in]    topOfProcStack  USR/SYS Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)\n{\n  uint32_t cpsr;\n  __ASM volatile(\n    \"MRS     %0, cpsr   \\n\"\n    \"CPS     #0x1F      \\n\" // no effect in USR mode\n    \"MOV     sp, %1     \\n\"\n    \"MSR     cpsr_c, %0 \\n\" // no effect in USR mode\n    \"ISB\" : \"=r\"(cpsr) : \"r\" (topOfProcStack) : \"memory\"\n   );\n}\n\n/** \\brief  Get FPEXC\n    \\return               Floating Point Exception Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)\n{\n#if (__FPU_PRESENT == 1)\n  uint32_t result;\n  __ASM volatile(\"VMRS %0, fpexc\" : \"=r\" (result) : : \"memory\");\n  return(result);\n#else\n  return(0);\n#endif\n}\n\n/** \\brief  Set FPEXC\n    \\param [in]    fpexc  Floating Point Exception Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)\n{\n#if (__FPU_PRESENT == 1)\n  __ASM volatile (\"VMSR fpexc, %0\" : : \"r\" (fpexc) : \"memory\");\n#endif\n}\n\n/*\n * Include common core functions to access Coprocessor 15 registers\n */\n\n#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile(\"MRC p\" # cp \", \" # op1 \", %0, c\" # CRn \", c\" # CRm \", \" # op2 : \"=r\" (Rt) : : \"memory\" )\n#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile(\"MCR p\" # cp \", \" # op1 \", %0, c\" # CRn \", c\" # CRm \", \" # op2 : : \"r\" (Rt) : \"memory\" )\n#define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile(\"MRRC p\" # cp \", \" # op1 \", %Q0, %R0, c\" # CRm  : \"=r\" (Rt) : : \"memory\" )\n#define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile(\"MCRR p\" # cp \", \" # op1 \", %Q0, %R0, c\" # CRm  : : \"r\" (Rt) : \"memory\" )\n\n#include \"cmsis_cp15.h\"\n\n/** \\brief  Enable Floating Point Unit\n\n  Critical section, called from undef handler, so systick is disabled\n */\n__STATIC_INLINE void __FPU_Enable(void)\n{\n  __ASM volatile(\n    //Permit access to VFP/NEON, registers by modifying CPACR\n    \"        MRC     p15,0,R1,c1,c0,2  \\n\"\n    \"        ORR     R1,R1,#0x00F00000 \\n\"\n    \"        MCR     p15,0,R1,c1,c0,2  \\n\"\n\n    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted\n    \"        ISB                       \\n\"\n\n    //Enable VFP/NEON\n    \"        VMRS    R1,FPEXC          \\n\"\n    \"        ORR     R1,R1,#0x40000000 \\n\"\n    \"        VMSR    FPEXC,R1          \\n\"\n\n    //Initialise VFP/NEON registers to 0\n    \"        MOV     R2,#0             \\n\"\n\n    //Initialise D16 registers to 0\n    \"        VMOV    D0, R2,R2         \\n\"\n    \"        VMOV    D1, R2,R2         \\n\"\n    \"        VMOV    D2, R2,R2         \\n\"\n    \"        VMOV    D3, R2,R2         \\n\"\n    \"        VMOV    D4, R2,R2         \\n\"\n    \"        VMOV    D5, R2,R2         \\n\"\n    \"        VMOV    D6, R2,R2         \\n\"\n    \"        VMOV    D7, R2,R2         \\n\"\n    \"        VMOV    D8, R2,R2         \\n\"\n    \"        VMOV    D9, R2,R2         \\n\"\n    \"        VMOV    D10,R2,R2         \\n\"\n    \"        VMOV    D11,R2,R2         \\n\"\n    \"        VMOV    D12,R2,R2         \\n\"\n    \"        VMOV    D13,R2,R2         \\n\"\n    \"        VMOV    D14,R2,R2         \\n\"\n    \"        VMOV    D15,R2,R2         \\n\"\n\n#if (defined(__ARM_NEON) && (__ARM_NEON == 1))\n    //Initialise D32 registers to 0\n    \"        VMOV    D16,R2,R2         \\n\"\n    \"        VMOV    D17,R2,R2         \\n\"\n    \"        VMOV    D18,R2,R2         \\n\"\n    \"        VMOV    D19,R2,R2         \\n\"\n    \"        VMOV    D20,R2,R2         \\n\"\n    \"        VMOV    D21,R2,R2         \\n\"\n    \"        VMOV    D22,R2,R2         \\n\"\n    \"        VMOV    D23,R2,R2         \\n\"\n    \"        VMOV    D24,R2,R2         \\n\"\n    \"        VMOV    D25,R2,R2         \\n\"\n    \"        VMOV    D26,R2,R2         \\n\"\n    \"        VMOV    D27,R2,R2         \\n\"\n    \"        VMOV    D28,R2,R2         \\n\"\n    \"        VMOV    D29,R2,R2         \\n\"\n    \"        VMOV    D30,R2,R2         \\n\"\n    \"        VMOV    D31,R2,R2         \\n\"\n#endif\n\n    //Initialise FPSCR to a known state\n    \"        VMRS    R1,FPSCR          \\n\"\n    \"        LDR     R2,=0x00086060    \\n\" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.\n    \"        AND     R1,R1,R2          \\n\"\n    \"        VMSR    FPSCR,R1            \"\n    : : : \"cc\", \"r1\", \"r2\"\n  );\n}\n\n#endif /* __CMSIS_ARMCLANG_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core_A/Include/cmsis_compiler.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_compiler.h\n * @brief    CMSIS compiler specific macros, functions, instructions\n * @version  V1.0.3\n * @date     13. November 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_COMPILER_H\n#define __CMSIS_COMPILER_H\n\n#include <stdint.h>\n\n/*\n * Arm Compiler 4/5\n */\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n\n/*\n * Arm Compiler 6.6 LTM (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)\n  #include \"cmsis_armclang_ltm.h\"\n\n  /*\n * Arm Compiler above 6.10.1 (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)\n  #include \"cmsis_armclang.h\"\n\n\n/*\n * GNU Compiler\n */\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n\n/*\n * IAR Compiler\n */\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iccarm.h>\n\n\n/*\n * TI Arm Compiler\n */\n#elif defined ( __TI_ARM__ )\n  #include <cmsis_ccs.h>\n\n  #ifndef   __ASM\n    #define __ASM                     __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                  inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE           static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE      __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN               __attribute__((noreturn))\n  #endif\n  #ifndef   CMSIS_DEPRECATED\n    #define CMSIS_DEPRECATED          __attribute__((deprecated))\n  #endif\n  #ifndef   __USED\n    #define __USED                    __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                    __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __attribute__((packed))\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)              __attribute__((aligned(x)))\n  #endif\n  #ifndef   __RESTRICT\n    #define __RESTRICT                             __restrict\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()      (void)0\n  #endif\n\n\n/*\n * TASKING Compiler\n */\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n  #ifndef   __ASM\n    #define __ASM                     __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                  inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE           static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE      __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN               __attribute__((noreturn))\n  #endif\n  #ifndef   CMSIS_DEPRECATED\n    #define CMSIS_DEPRECATED          __attribute__((deprecated))\n  #endif\n  #ifndef   __USED\n    #define __USED                    __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                    __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __packed__\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __packed__\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __packed__\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __packed__ T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)              __align(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()      (void)0\n  #endif\n\n\n/*\n * COSMIC Compiler\n */\n#elif defined ( __CSMC__ )\n   #include <cmsis_csm.h>\n\n #ifndef   __ASM\n    #define __ASM                     _asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                  inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE           static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE      __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    // NO RETURN is automatically detected hence no warning here\n    #define __NO_RETURN\n  #endif\n  #ifndef   __USED\n    #warning No compiler specific solution for __USED. __USED is ignored.\n    #define __USED\n  #endif\n  #ifndef   CMSIS_DEPRECATED\n    #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.\n    #define CMSIS_DEPRECATED\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                    __weak\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               @packed\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        @packed struct\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         @packed union\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    @packed struct T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)     (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n  #ifndef   __COMPILER_BARRIER\n    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.\n    #define __COMPILER_BARRIER()      (void)0\n  #endif\n\n\n#else\n  #error Unknown compiler.\n#endif\n\n\n#endif /* __CMSIS_COMPILER_H */\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core_A/Include/cmsis_cp15.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_cp15.h\n * @brief    CMSIS compiler specific macros, functions, instructions\n * @version  V1.0.2\n * @date     19. December 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CMSIS_CP15_H\n#define __CMSIS_CP15_H\n\n/** \\brief  Get ACTLR\n    \\return               Auxiliary Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 1, 0, 1);\n  return(result);\n}\n\n/** \\brief  Set ACTLR\n    \\param [in]    actlr  Auxiliary Control value to set\n */\n__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)\n{\n  __set_CP(15, 0, actlr, 1, 0, 1);\n}\n\n/** \\brief  Get CPACR\n    \\return               Coprocessor Access Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CPACR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 1, 0, 2);\n  return result;\n}\n\n/** \\brief  Set CPACR\n    \\param [in]    cpacr  Coprocessor Access Control value to set\n */\n__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)\n{\n  __set_CP(15, 0, cpacr, 1, 0, 2);\n}\n\n/** \\brief  Get DFSR\n    \\return               Data Fault Status Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_DFSR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 5, 0, 0);\n  return result;\n}\n\n/** \\brief  Set DFSR\n    \\param [in]    dfsr  Data Fault Status value to set\n */\n__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)\n{\n  __set_CP(15, 0, dfsr, 5, 0, 0);\n}\n\n/** \\brief  Get IFSR\n    \\return               Instruction Fault Status Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IFSR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 5, 0, 1);\n  return result;\n}\n\n/** \\brief  Set IFSR\n    \\param [in]    ifsr  Instruction Fault Status value to set\n */\n__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)\n{\n  __set_CP(15, 0, ifsr, 5, 0, 1);\n}\n\n/** \\brief  Get ISR\n    \\return               Interrupt Status Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_ISR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 12, 1, 0);\n  return result;\n}\n\n/** \\brief  Get CBAR\n    \\return               Configuration Base Address register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CBAR(void)\n{\n  uint32_t result;\n  __get_CP(15, 4, result, 15, 0, 0);\n  return result;\n}\n\n/** \\brief  Get TTBR0\n\n    This function returns the value of the Translation Table Base Register 0.\n\n    \\return               Translation Table Base Register 0 value\n */\n__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 2, 0, 0);\n  return result;\n}\n\n/** \\brief  Set TTBR0\n\n    This function assigns the given value to the Translation Table Base Register 0.\n\n    \\param [in]    ttbr0  Translation Table Base Register 0 value to set\n */\n__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)\n{\n  __set_CP(15, 0, ttbr0, 2, 0, 0);\n}\n\n/** \\brief  Get DACR\n\n    This function returns the value of the Domain Access Control Register.\n\n    \\return               Domain Access Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_DACR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 3, 0, 0);\n  return result;\n}\n\n/** \\brief  Set DACR\n\n    This function assigns the given value to the Domain Access Control Register.\n\n    \\param [in]    dacr   Domain Access Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)\n{\n  __set_CP(15, 0, dacr, 3, 0, 0);\n}\n\n/** \\brief  Set SCTLR\n\n    This function assigns the given value to the System Control Register.\n\n    \\param [in]    sctlr  System Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)\n{\n  __set_CP(15, 0, sctlr, 1, 0, 0);\n}\n\n/** \\brief  Get SCTLR\n    \\return               System Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 1, 0, 0);\n  return result;\n}\n\n/** \\brief  Set ACTRL\n    \\param [in]    actrl  Auxiliary Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)\n{\n  __set_CP(15, 0, actrl, 1, 0, 1);\n}\n\n/** \\brief  Get ACTRL\n    \\return               Auxiliary Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 1, 0, 1);\n  return result;\n}\n\n/** \\brief  Get MPIDR\n\n    This function returns the value of the Multiprocessor Affinity Register.\n\n    \\return               Multiprocessor Affinity Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 0, 0, 5);\n  return result;\n}\n\n/** \\brief  Get VBAR\n\n    This function returns the value of the Vector Base Address Register.\n\n    \\return               Vector Base Address Register\n */\n__STATIC_FORCEINLINE uint32_t __get_VBAR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 12, 0, 0);\n  return result;\n}\n\n/** \\brief  Set VBAR\n\n    This function assigns the given value to the Vector Base Address Register.\n\n    \\param [in]    vbar  Vector Base Address Register value to set\n */\n__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)\n{\n  __set_CP(15, 0, vbar, 12, 0, 0);\n}\n\n/** \\brief  Get MVBAR\n\n    This function returns the value of the Monitor Vector Base Address Register.\n\n    \\return               Monitor Vector Base Address Register\n */\n__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 12, 0, 1);\n  return result;\n}\n\n/** \\brief  Set MVBAR\n\n    This function assigns the given value to the Monitor Vector Base Address Register.\n\n    \\param [in]    mvbar  Monitor Vector Base Address Register value to set\n */\n__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)\n{\n  __set_CP(15, 0, mvbar, 12, 0, 1);\n}\n\n#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \\\n    defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \\\n    defined(DOXYGEN)\n\n/** \\brief  Set CNTFRQ\n\n  This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).\n\n  \\param [in]    value  CNTFRQ Register value to set\n*/\n__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)\n{\n  __set_CP(15, 0, value, 14, 0, 0);\n}\n\n/** \\brief  Get CNTFRQ\n\n    This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).\n\n    \\return               CNTFRQ Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 14, 0 , 0);\n  return result;\n}\n\n/** \\brief  Set CNTP_TVAL\n\n  This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).\n\n  \\param [in]    value  CNTP_TVAL Register value to set\n*/\n__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)\n{\n  __set_CP(15, 0, value, 14, 2, 0);\n}\n\n/** \\brief  Get CNTP_TVAL\n\n    This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).\n\n    \\return               CNTP_TVAL Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 14, 2, 0);\n  return result;\n}\n\n/** \\brief  Get CNTPCT\n\n    This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).\n\n    \\return               CNTPCT Register value\n */\n__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)\n{\n  uint64_t result;\n  __get_CP64(15, 0, result, 14);\n  return result;\n}\n\n/** \\brief  Set CNTP_CVAL\n\n  This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).\n\n  \\param [in]    value  CNTP_CVAL Register value to set\n*/\n__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)\n{\n  __set_CP64(15, 2, value, 14);\n}\n\n/** \\brief  Get CNTP_CVAL\n\n    This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).\n\n    \\return               CNTP_CVAL Register value\n */\n__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)\n{\n  uint64_t result;\n  __get_CP64(15, 2, result, 14);\n  return result;\n}\n\n/** \\brief  Set CNTP_CTL\n\n  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).\n\n  \\param [in]    value  CNTP_CTL Register value to set\n*/\n__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)\n{\n  __set_CP(15, 0, value, 14, 2, 1);\n}\n\n/** \\brief  Get CNTP_CTL register\n    \\return               CNTP_CTL Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)\n{\n  uint32_t result;\n  __get_CP(15, 0, result, 14, 2, 1);\n  return result;\n}\n\n#endif\n\n/** \\brief  Set TLBIALL\n\n  TLB Invalidate All\n */\n__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)\n{\n  __set_CP(15, 0, value, 8, 7, 0);\n}\n\n/** \\brief  Set BPIALL.\n\n  Branch Predictor Invalidate All\n */\n__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)\n{\n  __set_CP(15, 0, value, 7, 5, 6);\n}\n\n/** \\brief  Set ICIALLU\n\n  Instruction Cache Invalidate All\n */\n__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)\n{\n  __set_CP(15, 0, value, 7, 5, 0);\n}\n\n/** \\brief  Set ICIMVAC\n\n  Instruction Cache Invalidate\n */\n__STATIC_FORCEINLINE void __set_ICIMVAC(uint32_t value)\n{\n  __set_CP(15, 0, value, 7, 5, 1);\n}\n\n/** \\brief  Set DCCMVAC\n\n  Data cache clean\n */\n__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)\n{\n  __set_CP(15, 0, value, 7, 10, 1);\n}\n\n/** \\brief  Set DCIMVAC\n\n  Data cache invalidate\n */\n__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)\n{\n  __set_CP(15, 0, value, 7, 6, 1);\n}\n\n/** \\brief  Set DCCIMVAC\n\n  Data cache clean and invalidate\n */\n__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)\n{\n  __set_CP(15, 0, value, 7, 14, 1);\n}\n\n/** \\brief  Set CSSELR\n */\n__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)\n{\n//  __ASM volatile(\"MCR p15, 2, %0, c0, c0, 0\" : : \"r\"(value) : \"memory\");\n  __set_CP(15, 2, value, 0, 0, 0);\n}\n\n/** \\brief  Get CSSELR\n    \\return CSSELR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)\n{\n  uint32_t result;\n//  __ASM volatile(\"MRC p15, 2, %0, c0, c0, 0\" : \"=r\"(result) : : \"memory\");\n  __get_CP(15, 2, result, 0, 0, 0);\n  return result;\n}\n\n/** \\brief  Set CCSIDR\n    \\deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.\n */\nCMSIS_DEPRECATED\n__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)\n{\n  __set_CSSELR(value);\n}\n\n/** \\brief  Get CCSIDR\n    \\return CCSIDR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)\n{\n  uint32_t result;\n//  __ASM volatile(\"MRC p15, 1, %0, c0, c0, 0\" : \"=r\"(result) : : \"memory\");\n  __get_CP(15, 1, result, 0, 0, 0);\n  return result;\n}\n\n/** \\brief  Get CLIDR\n    \\return CLIDR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)\n{\n  uint32_t result;\n//  __ASM volatile(\"MRC p15, 1, %0, c0, c0, 1\" : \"=r\"(result) : : \"memory\");\n  __get_CP(15, 1, result, 0, 0, 1);\n  return result;\n}\n\n/** \\brief  Set DCISW\n */\n__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)\n{\n//  __ASM volatile(\"MCR p15, 0, %0, c7, c6, 2\" : : \"r\"(value) : \"memory\")\n  __set_CP(15, 0, value, 7, 6, 2);\n}\n\n/** \\brief  Set DCCSW\n */\n__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)\n{\n//  __ASM volatile(\"MCR p15, 0, %0, c7, c10, 2\" : : \"r\"(value) : \"memory\")\n  __set_CP(15, 0, value, 7, 10, 2);\n}\n\n/** \\brief  Set DCCISW\n */\n__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)\n{\n//  __ASM volatile(\"MCR p15, 0, %0, c7, c14, 2\" : : \"r\"(value) : \"memory\")\n  __set_CP(15, 0, value, 7, 14, 2);\n}\n\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core_A/Include/cmsis_gcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_gcc.h\n * @brief    CMSIS compiler GCC header file\n * @version  V1.3.3\n * @date     13. November 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_GCC_H\n#define __CMSIS_GCC_H\n\n/* ignore some GCC warnings */\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n\n/* Fallback for __has_builtin */\n#ifndef __has_builtin\n  #define __has_builtin(x) (0)\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               inline\n#endif\n#ifndef   __FORCEINLINE\n  #define __FORCEINLINE                          __attribute__((always_inline))\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static inline\n#endif\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\n#endif\n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   CMSIS_DEPRECATED\n  #define CMSIS_DEPRECATED                       __attribute__((deprecated))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER()                   __ASM volatile(\"\":::\"memory\")\n#endif\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP()                             __ASM volatile (\"nop\")\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI()                             __ASM volatile (\"wfi\":::\"memory\")\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE()                             __ASM volatile (\"wfe\":::\"memory\")\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV()                             __ASM volatile (\"sev\")\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n__STATIC_FORCEINLINE  void __ISB(void)\n{\n  __ASM volatile (\"isb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n__STATIC_FORCEINLINE  void __DSB(void)\n{\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n__STATIC_FORCEINLINE  void __DMB(void)\n{\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE  uint32_t __REV(uint32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\n  return __builtin_bswap32(value);\n#else\n  uint32_t result;\n\n  __ASM (\"rev %0, %1\" : \"=r\" (result) : \"r\" (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n  __ASM (\"rev16 %0, %1\" : \"=r\" (result) : \"r\" (value));\n  return result;\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE  int16_t __REVSH(int16_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n  return (int16_t)__builtin_bswap16(value);\n#else\n  int16_t result;\n\n  __ASM (\"revsh %0, %1\" : \"=r\" (result) : \"r\" (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)   __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE  uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n   __ASM (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n  return result;\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)\n{\n  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally\n     __builtin_clz(0) is undefined behaviour, so handle this case specially.\n     This guarantees ARM-compatible results if happening to compile on a non-ARM\n     target, and ensures the compiler doesn't decide to activate any\n     optimisations using the logic \"value was passed to __builtin_clz, so it\n     is non-zero\".\n     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a\n     single CLZ instruction.\n   */\n  if (value == 0U)\n  {\n    return 32U;\n  }\n  return __builtin_clz(value);\n}\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE  uint8_t __LDREXB(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE  uint16_t __LDREXH(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE  uint32_t __LDREXW(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE  uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE  uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE  uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n__STATIC_FORCEINLINE  void __CLREX(void)\n{\n  __ASM volatile (\"clrex\" ::: \"memory\");\n}\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT(ARG1, ARG2) \\\n__extension__ \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM volatile (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) : \"cc\" ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT(ARG1, ARG2) \\\n__extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM volatile (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) : \"cc\" ); \\\n  __RES; \\\n })\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting special-purpose register PRIMASK.\n  Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_FORCEINLINE  uint32_t __get_FPSCR(void)\n{\n  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  #if __has_builtin(__builtin_arm_get_fpscr) \n  // Re-enable using built-in when GCC has been fixed\n  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n    return __builtin_arm_get_fpscr();\n  #else\n    uint32_t result;\n\n    __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n    return(result);\n  #endif\n  #else\n    return(0U);\n  #endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\n{\n  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  #if __has_builtin(__builtin_arm_set_fpscr)\n  // Re-enable using built-in when GCC has been fixed\n  // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n    /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n    __builtin_arm_set_fpscr(fpscr);\n  #else\n    __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\", \"memory\");\n  #endif\n  #else\n    (void)fpscr;\n  #endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n\n/** \\defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n/** \\brief  Get CPSR Register\n    \\return               CPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CPSR(void)\n{\n  uint32_t result;\n  __ASM volatile(\"MRS %0, cpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n/** \\brief  Set CPSR Register\n    \\param [in]    cpsr  CPSR value to set\n */\n__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)\n{\n  __ASM volatile (\"MSR cpsr, %0\" : : \"r\" (cpsr) : \"cc\", \"memory\");\n}\n\n/** \\brief  Get Mode\n    \\return                Processor Mode\n */\n__STATIC_FORCEINLINE uint32_t __get_mode(void)\n{\n  return (__get_CPSR() & 0x1FU);\n}\n\n/** \\brief  Set Mode\n    \\param [in]    mode  Mode value to set\n */\n__STATIC_FORCEINLINE void __set_mode(uint32_t mode)\n{\n  __ASM volatile(\"MSR  cpsr_c, %0\" : : \"r\" (mode) : \"memory\");\n}\n\n/** \\brief  Get Stack Pointer\n    \\return Stack Pointer value\n */\n__STATIC_FORCEINLINE uint32_t __get_SP(void)\n{\n  uint32_t result;\n  __ASM volatile(\"MOV  %0, sp\" : \"=r\" (result) : : \"memory\");\n  return result;\n}\n\n/** \\brief  Set Stack Pointer\n    \\param [in]    stack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_SP(uint32_t stack)\n{\n  __ASM volatile(\"MOV  sp, %0\" : : \"r\" (stack) : \"memory\");\n}\n\n/** \\brief  Get USR/SYS Stack Pointer\n    \\return USR/SYS Stack Pointer value\n */\n__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)\n{\n  uint32_t cpsr = __get_CPSR();\n  uint32_t result;\n  __ASM volatile(\n    \"CPS     #0x1F  \\n\"\n    \"MOV     %0, sp   \" : \"=r\"(result) : : \"memory\"\n   );\n  __set_CPSR(cpsr);\n  __ISB();\n  return result;\n}\n\n/** \\brief  Set USR/SYS Stack Pointer\n    \\param [in]    topOfProcStack  USR/SYS Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)\n{\n  uint32_t cpsr = __get_CPSR();\n  __ASM volatile(\n    \"CPS     #0x1F  \\n\"\n    \"MOV     sp, %0   \" : : \"r\" (topOfProcStack) : \"memory\"\n   );\n  __set_CPSR(cpsr);\n  __ISB();\n}\n\n/** \\brief  Get FPEXC\n    \\return               Floating Point Exception Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)\n{\n#if (__FPU_PRESENT == 1)\n  uint32_t result;\n  __ASM volatile(\"VMRS %0, fpexc\" : \"=r\" (result) : : \"memory\");\n  return(result);\n#else\n  return(0);\n#endif\n}\n\n/** \\brief  Set FPEXC\n    \\param [in]    fpexc  Floating Point Exception Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)\n{\n#if (__FPU_PRESENT == 1)\n  __ASM volatile (\"VMSR fpexc, %0\" : : \"r\" (fpexc) : \"memory\");\n#endif\n}\n\n/*\n * Include common core functions to access Coprocessor 15 registers\n */\n\n#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile(\"MRC p\" # cp \", \" # op1 \", %0, c\" # CRn \", c\" # CRm \", \" # op2 : \"=r\" (Rt) : : \"memory\" )\n#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile(\"MCR p\" # cp \", \" # op1 \", %0, c\" # CRn \", c\" # CRm \", \" # op2 : : \"r\" (Rt) : \"memory\" )\n#define __get_CP64(cp, op1, Rt, CRm)         __ASM volatile(\"MRRC p\" # cp \", \" # op1 \", %Q0, %R0, c\" # CRm  : \"=r\" (Rt) : : \"memory\" )\n#define __set_CP64(cp, op1, Rt, CRm)         __ASM volatile(\"MCRR p\" # cp \", \" # op1 \", %Q0, %R0, c\" # CRm  : : \"r\" (Rt) : \"memory\" )\n\n#include \"cmsis_cp15.h\"\n\n/** \\brief  Enable Floating Point Unit\n\n  Critical section, called from undef handler, so systick is disabled\n */\n__STATIC_INLINE void __FPU_Enable(void)\n{\n  __ASM volatile(\n    //Permit access to VFP/NEON, registers by modifying CPACR\n    \"        MRC     p15,0,R1,c1,c0,2  \\n\"\n    \"        ORR     R1,R1,#0x00F00000 \\n\"\n    \"        MCR     p15,0,R1,c1,c0,2  \\n\"\n\n    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted\n    \"        ISB                       \\n\"\n\n    //Enable VFP/NEON\n    \"        VMRS    R1,FPEXC          \\n\"\n    \"        ORR     R1,R1,#0x40000000 \\n\"\n    \"        VMSR    FPEXC,R1          \\n\"\n\n    //Initialise VFP/NEON registers to 0\n    \"        MOV     R2,#0             \\n\"\n\n    //Initialise D16 registers to 0\n    \"        VMOV    D0, R2,R2         \\n\"\n    \"        VMOV    D1, R2,R2         \\n\"\n    \"        VMOV    D2, R2,R2         \\n\"\n    \"        VMOV    D3, R2,R2         \\n\"\n    \"        VMOV    D4, R2,R2         \\n\"\n    \"        VMOV    D5, R2,R2         \\n\"\n    \"        VMOV    D6, R2,R2         \\n\"\n    \"        VMOV    D7, R2,R2         \\n\"\n    \"        VMOV    D8, R2,R2         \\n\"\n    \"        VMOV    D9, R2,R2         \\n\"\n    \"        VMOV    D10,R2,R2         \\n\"\n    \"        VMOV    D11,R2,R2         \\n\"\n    \"        VMOV    D12,R2,R2         \\n\"\n    \"        VMOV    D13,R2,R2         \\n\"\n    \"        VMOV    D14,R2,R2         \\n\"\n    \"        VMOV    D15,R2,R2         \\n\"\n\n#if (defined(__ARM_NEON) && (__ARM_NEON == 1))\n    //Initialise D32 registers to 0\n    \"        VMOV    D16,R2,R2         \\n\"\n    \"        VMOV    D17,R2,R2         \\n\"\n    \"        VMOV    D18,R2,R2         \\n\"\n    \"        VMOV    D19,R2,R2         \\n\"\n    \"        VMOV    D20,R2,R2         \\n\"\n    \"        VMOV    D21,R2,R2         \\n\"\n    \"        VMOV    D22,R2,R2         \\n\"\n    \"        VMOV    D23,R2,R2         \\n\"\n    \"        VMOV    D24,R2,R2         \\n\"\n    \"        VMOV    D25,R2,R2         \\n\"\n    \"        VMOV    D26,R2,R2         \\n\"\n    \"        VMOV    D27,R2,R2         \\n\"\n    \"        VMOV    D28,R2,R2         \\n\"\n    \"        VMOV    D29,R2,R2         \\n\"\n    \"        VMOV    D30,R2,R2         \\n\"\n    \"        VMOV    D31,R2,R2         \\n\"\n#endif\n\n    //Initialise FPSCR to a known state\n    \"        VMRS    R1,FPSCR          \\n\"\n    \"        LDR     R2,=0x00086060    \\n\" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.\n    \"        AND     R1,R1,R2          \\n\"\n    \"        VMSR    FPSCR,R1            \"\n    : : : \"cc\", \"r1\", \"r2\"\n  );\n}\n\n/*@} end of group CMSIS_Core_intrinsics */\n\n#pragma GCC diagnostic pop\n\n#endif /* __CMSIS_GCC_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core_A/Include/cmsis_iccarm.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_iccarm.h\n * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file\n * @version  V5.0.8\n * @date     13. November 2022\n ******************************************************************************/\n\n//------------------------------------------------------------------------------\n//\n// Copyright (c) 2017-2018 IAR Systems\n// Copyright (c) 2018-2019 Arm Limited \n//\n// SPDX-License-Identifier: Apache-2.0\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\")\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//     http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n//------------------------------------------------------------------------------\n\n\n#ifndef __CMSIS_ICCARM_H__\n#define __CMSIS_ICCARM_H__\n\n#ifndef __ICCARM__\n  #error This file should only be compiled by ICCARM\n#endif\n\n#pragma system_include\n\n#define __IAR_FT _Pragma(\"inline=forced\") __intrinsic\n\n#if (__VER__ >= 8000000)\n  #define __ICCARM_V8 1\n#else\n  #define __ICCARM_V8 0\n#endif\n\n#pragma language=extended\n\n#ifndef __ALIGNED\n  #if __ICCARM_V8\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #elif (__VER__ >= 7080000)\n    /* Needs IAR language extensions */\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #else\n    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n#endif\n\n\n/* Define compiler macros for CPU architecture, used in CMSIS 5.\n */\n#if __ARM_ARCH_7A__\n/* Macro already defined */\n#else\n  #if defined(__ARM7A__)\n    #define __ARM_ARCH_7A__ 1\n  #endif\n#endif\n\n#ifndef __ASM\n  #define __ASM __asm\n#endif\n\n#ifndef   __COMPILER_BARRIER\n  #define __COMPILER_BARRIER() __ASM volatile(\"\":::\"memory\")\n#endif\n\n#ifndef __INLINE\n  #define __INLINE inline\n#endif\n\n#ifndef   __NO_RETURN\n  #if __ICCARM_V8\n    #define __NO_RETURN __attribute__((__noreturn__))\n  #else\n    #define __NO_RETURN _Pragma(\"object_attribute=__noreturn\")\n  #endif\n#endif\n\n#ifndef   __PACKED\n  #if __ICCARM_V8\n    #define __PACKED __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED __packed\n  #endif\n#endif\n\n#ifndef   __PACKED_STRUCT\n  #if __ICCARM_V8\n    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_STRUCT __packed struct\n  #endif\n#endif\n\n#ifndef   __PACKED_UNION\n  #if __ICCARM_V8\n    #define __PACKED_UNION union __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_UNION __packed union\n  #endif\n#endif\n\n#ifndef   __RESTRICT\n  #if __ICCARM_V8\n    #define __RESTRICT            __restrict\n  #else\n    /* Needs IAR language extensions */\n    #define __RESTRICT            restrict\n  #endif\n#endif\n\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE       static inline\n#endif\n\n#ifndef   __FORCEINLINE\n  #define __FORCEINLINE         _Pragma(\"inline=forced\")\n#endif\n\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE\n#endif\n\n#ifndef   CMSIS_DEPRECATED\n  #define CMSIS_DEPRECATED      __attribute__((deprecated))\n#endif\n\n#ifndef __UNALIGNED_UINT16_READ\n  #pragma language=save\n  #pragma language=extended\n  __IAR_FT uint16_t __iar_uint16_read(void const *ptr)\n  {\n    return *(__packed uint16_t*)(ptr);\n  }\n  #pragma language=restore\n  #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\n#endif\n\n\n#ifndef __UNALIGNED_UINT16_WRITE\n  #pragma language=save\n  #pragma language=extended\n  __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\n  {\n    *(__packed uint16_t*)(ptr) = val;;\n  }\n  #pragma language=restore\n  #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\n#endif\n\n#ifndef __UNALIGNED_UINT32_READ\n  #pragma language=save\n  #pragma language=extended\n  __IAR_FT uint32_t __iar_uint32_read(void const *ptr)\n  {\n    return *(__packed uint32_t*)(ptr);\n  }\n  #pragma language=restore\n  #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\n#endif\n\n#ifndef __UNALIGNED_UINT32_WRITE\n  #pragma language=save\n  #pragma language=extended\n  __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\n  {\n    *(__packed uint32_t*)(ptr) = val;;\n  }\n  #pragma language=restore\n  #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\n#endif\n\n#if 0\n#ifndef __UNALIGNED_UINT32   /* deprecated */\n  #pragma language=save\n  #pragma language=extended\n  __packed struct  __iar_u32 { uint32_t v; };\n  #pragma language=restore\n  #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\n#endif\n#endif\n\n#ifndef   __USED\n  #if __ICCARM_V8\n    #define __USED __attribute__((used))\n  #else\n    #define __USED _Pragma(\"__root\")\n  #endif\n#endif\n\n#ifndef   __WEAK\n  #if __ICCARM_V8\n    #define __WEAK __attribute__((weak))\n  #else\n    #define __WEAK _Pragma(\"__weak\")\n  #endif\n#endif\n\n\n#ifndef __ICCARM_INTRINSICS_VERSION__\n  #define __ICCARM_INTRINSICS_VERSION__  0\n#endif\n\n#if __ICCARM_INTRINSICS_VERSION__ == 2\n\n  #if defined(__CLZ)\n    #undef __CLZ\n  #endif\n  #if defined(__REVSH)\n    #undef __REVSH\n  #endif\n  #if defined(__RBIT)\n    #undef __RBIT\n  #endif\n  #if defined(__SSAT)\n    #undef __SSAT\n  #endif\n  #if defined(__USAT)\n    #undef __USAT\n  #endif\n\n  #include \"iccarm_builtin.h\"\n\n  #define __disable_fault_irq   __iar_builtin_disable_fiq\n  #define __disable_irq       __iar_builtin_disable_interrupt\n  #define __enable_fault_irq    __iar_builtin_enable_fiq\n  #define __enable_irq        __iar_builtin_enable_interrupt\n  #define __arm_rsr           __iar_builtin_rsr\n  #define __arm_wsr           __iar_builtin_wsr\n\n  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))\n    #define __get_FPSCR()             (__arm_rsr(\"FPSCR\"))\n    #define __set_FPSCR(VALUE)        (__arm_wsr(\"FPSCR\", (VALUE)))\n  #else\n    #define __get_FPSCR()             ( 0 )\n    #define __set_FPSCR(VALUE)        ((void)VALUE)\n  #endif\n\n  #define __get_CPSR()                (__arm_rsr(\"CPSR\"))\n  #define __get_mode()                (__get_CPSR() & 0x1FU)\n\n  #define __set_CPSR(VALUE)           (__arm_wsr(\"CPSR\", (VALUE)))\n  #define __set_mode(VALUE)           (__arm_wsr(\"CPSR_c\", (VALUE)))\n\n\n  #define __get_FPEXC()       (__arm_rsr(\"FPEXC\"))\n  #define __set_FPEXC(VALUE)    (__arm_wsr(\"FPEXC\", VALUE))\n\n  #define __get_CP(cp, op1, RT, CRn, CRm, op2) \\\n    ((RT) = __arm_rsr(\"p\" # cp \":\" # op1 \":c\" # CRn \":c\" # CRm \":\" # op2))\n\n  #define __set_CP(cp, op1, RT, CRn, CRm, op2) \\\n    (__arm_wsr(\"p\" # cp \":\" # op1 \":c\" # CRn \":c\" # CRm \":\" # op2, (RT)))\n\n  #define __get_CP64(cp, op1, Rt, CRm) \\\n    __ASM volatile(\"MRRC p\" # cp \", \" # op1 \", %Q0, %R0, c\" # CRm  : \"=r\" (Rt) : : \"memory\" )\n\n  #define __set_CP64(cp, op1, Rt, CRm) \\\n    __ASM volatile(\"MCRR p\" # cp \", \" # op1 \", %Q0, %R0, c\" # CRm  : : \"r\" (Rt) : \"memory\" )\n\n  #include \"cmsis_cp15.h\"\n\n  #define __NOP     __iar_builtin_no_operation\n\n  #define __CLZ     __iar_builtin_CLZ\n  #define __CLREX   __iar_builtin_CLREX\n\n  #define __DMB     __iar_builtin_DMB\n  #define __DSB     __iar_builtin_DSB\n  #define __ISB     __iar_builtin_ISB\n\n  #define __LDREXB  __iar_builtin_LDREXB\n  #define __LDREXH  __iar_builtin_LDREXH\n  #define __LDREXW  __iar_builtin_LDREX\n\n  #define __RBIT    __iar_builtin_RBIT\n  #define __REV     __iar_builtin_REV\n  #define __REV16   __iar_builtin_REV16\n\n  __IAR_FT int16_t __REVSH(int16_t val)\n  {\n    return (int16_t) __iar_builtin_REVSH(val);\n  }\n\n  #define __ROR     __iar_builtin_ROR\n  #define __RRX     __iar_builtin_RRX\n\n  #define __SEV     __iar_builtin_SEV\n\n  #define __SSAT    __iar_builtin_SSAT\n\n  #define __STREXB  __iar_builtin_STREXB\n  #define __STREXH  __iar_builtin_STREXH\n  #define __STREXW  __iar_builtin_STREX\n\n  #define __USAT    __iar_builtin_USAT\n\n  #define __WFE     __iar_builtin_WFE\n  #define __WFI     __iar_builtin_WFI\n\n  #define __SADD8   __iar_builtin_SADD8\n  #define __QADD8   __iar_builtin_QADD8\n  #define __SHADD8  __iar_builtin_SHADD8\n  #define __UADD8   __iar_builtin_UADD8\n  #define __UQADD8  __iar_builtin_UQADD8\n  #define __UHADD8  __iar_builtin_UHADD8\n  #define __SSUB8   __iar_builtin_SSUB8\n  #define __QSUB8   __iar_builtin_QSUB8\n  #define __SHSUB8  __iar_builtin_SHSUB8\n  #define __USUB8   __iar_builtin_USUB8\n  #define __UQSUB8  __iar_builtin_UQSUB8\n  #define __UHSUB8  __iar_builtin_UHSUB8\n  #define __SADD16  __iar_builtin_SADD16\n  #define __QADD16  __iar_builtin_QADD16\n  #define __SHADD16 __iar_builtin_SHADD16\n  #define __UADD16  __iar_builtin_UADD16\n  #define __UQADD16 __iar_builtin_UQADD16\n  #define __UHADD16 __iar_builtin_UHADD16\n  #define __SSUB16  __iar_builtin_SSUB16\n  #define __QSUB16  __iar_builtin_QSUB16\n  #define __SHSUB16 __iar_builtin_SHSUB16\n  #define __USUB16  __iar_builtin_USUB16\n  #define __UQSUB16 __iar_builtin_UQSUB16\n  #define __UHSUB16 __iar_builtin_UHSUB16\n  #define __SASX    __iar_builtin_SASX\n  #define __QASX    __iar_builtin_QASX\n  #define __SHASX   __iar_builtin_SHASX\n  #define __UASX    __iar_builtin_UASX\n  #define __UQASX   __iar_builtin_UQASX\n  #define __UHASX   __iar_builtin_UHASX\n  #define __SSAX    __iar_builtin_SSAX\n  #define __QSAX    __iar_builtin_QSAX\n  #define __SHSAX   __iar_builtin_SHSAX\n  #define __USAX    __iar_builtin_USAX\n  #define __UQSAX   __iar_builtin_UQSAX\n  #define __UHSAX   __iar_builtin_UHSAX\n  #define __USAD8   __iar_builtin_USAD8\n  #define __USADA8  __iar_builtin_USADA8\n  #define __SSAT16  __iar_builtin_SSAT16\n  #define __USAT16  __iar_builtin_USAT16\n  #define __UXTB16  __iar_builtin_UXTB16\n  #define __UXTAB16 __iar_builtin_UXTAB16\n  #define __SXTB16  __iar_builtin_SXTB16\n  #define __SXTAB16 __iar_builtin_SXTAB16\n  #define __SMUAD   __iar_builtin_SMUAD\n  #define __SMUADX  __iar_builtin_SMUADX\n  #define __SMMLA   __iar_builtin_SMMLA\n  #define __SMLAD   __iar_builtin_SMLAD\n  #define __SMLADX  __iar_builtin_SMLADX\n  #define __SMLALD  __iar_builtin_SMLALD\n  #define __SMLALDX __iar_builtin_SMLALDX\n  #define __SMUSD   __iar_builtin_SMUSD\n  #define __SMUSDX  __iar_builtin_SMUSDX\n  #define __SMLSD   __iar_builtin_SMLSD\n  #define __SMLSDX  __iar_builtin_SMLSDX\n  #define __SMLSLD  __iar_builtin_SMLSLD\n  #define __SMLSLDX __iar_builtin_SMLSLDX\n  #define __SEL     __iar_builtin_SEL\n  #define __QADD    __iar_builtin_QADD\n  #define __QSUB    __iar_builtin_QSUB\n  #define __PKHBT   __iar_builtin_PKHBT\n  #define __PKHTB   __iar_builtin_PKHTB\n\n#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n  #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))\n    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\n  #endif\n\n  #ifdef __INTRINSICS_INCLUDED\n  #error intrinsics.h is already included previously!\n  #endif\n\n  #include <intrinsics.h>\n\n  #if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))\n    #define __get_FPSCR() (0)\n  #endif\n\n  #pragma diag_suppress=Pe940\n  #pragma diag_suppress=Pe177\n\n  #define __enable_irq        __enable_interrupt\n  #define __disable_irq       __disable_interrupt\n  #define __enable_fault_irq    __enable_fiq\n  #define __disable_fault_irq   __disable_fiq\n  #define __NOP               __no_operation\n\n  #define __get_xPSR          __get_PSR\n\n  __IAR_FT void __set_mode(uint32_t mode)\n  {\n    __ASM volatile(\"MSR  cpsr_c, %0\" : : \"r\" (mode) : \"memory\");\n  }\n\n  __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\n  {\n    return __LDREX((unsigned long *)ptr);\n  }\n\n  __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\n  {\n    return __STREX(value, (unsigned long *)ptr);\n  }\n\n\n  __IAR_FT uint32_t __RRX(uint32_t value)\n  {\n    uint32_t result;\n    __ASM(\"RRX      %0, %1\" : \"=r\"(result) : \"r\" (value) : \"cc\");\n    return(result);\n  }\n\n\n  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\n  {\n    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\n  }\n\n  __IAR_FT uint32_t __get_FPEXC(void)\n  {\n  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))\n    uint32_t result;\n    __ASM volatile(\"VMRS %0, fpexc\" : \"=r\" (result) : : \"memory\");\n    return(result);\n  #else\n    return(0);\n  #endif\n  }\n\n  __IAR_FT void __set_FPEXC(uint32_t fpexc)\n  {\n  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))\n    __ASM volatile (\"VMSR fpexc, %0\" : : \"r\" (fpexc) : \"memory\");\n  #endif\n  }\n\n\n  #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \\\n    __ASM volatile(\"MRC p\" # cp \", \" # op1 \", %0, c\" # CRn \", c\" # CRm \", \" # op2 : \"=r\" (Rt) : : \"memory\" )\n  #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \\\n    __ASM volatile(\"MCR p\" # cp \", \" # op1 \", %0, c\" # CRn \", c\" # CRm \", \" # op2 : : \"r\" (Rt) : \"memory\" )\n  #define __get_CP64(cp, op1, Rt, CRm) \\\n    __ASM volatile(\"MRRC p\" # cp \", \" # op1 \", %Q0, %R0, c\" # CRm  : \"=r\" (Rt) : : \"memory\" )\n  #define __set_CP64(cp, op1, Rt, CRm) \\\n    __ASM volatile(\"MCRR p\" # cp \", \" # op1 \", %Q0, %R0, c\" # CRm  : : \"r\" (Rt) : \"memory\" )\n\n  #include \"cmsis_cp15.h\"\n\n#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n#define __BKPT(value)    __asm volatile (\"BKPT     %0\" : : \"i\"(value))\n\n\n__IAR_FT uint32_t __get_SP_usr(void)\n{\n  uint32_t cpsr;\n  uint32_t result;\n  __ASM volatile(\n    \"MRS     %0, cpsr   \\n\"\n    \"CPS     #0x1F      \\n\" // no effect in USR mode\n    \"MOV     %1, sp     \\n\"\n    \"MSR     cpsr_c, %2 \\n\" // no effect in USR mode\n    \"ISB\" :  \"=r\"(cpsr), \"=r\"(result) : \"r\"(cpsr) : \"memory\"\n   );\n  return result;\n}\n\n__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)\n{\n  uint32_t cpsr;\n  __ASM volatile(\n    \"MRS     %0, cpsr   \\n\"\n    \"CPS     #0x1F      \\n\" // no effect in USR mode\n    \"MOV     sp, %1     \\n\"\n    \"MSR     cpsr_c, %2 \\n\" // no effect in USR mode\n    \"ISB\" : \"=r\"(cpsr) : \"r\" (topOfProcStack), \"r\"(cpsr) : \"memory\"\n   );\n}\n\n#define __get_mode()                (__get_CPSR() & 0x1FU)\n\n__STATIC_INLINE\nvoid __FPU_Enable(void)\n{\n  __ASM volatile(\n    //Permit access to VFP/NEON, registers by modifying CPACR\n    \"        MRC     p15,0,R1,c1,c0,2  \\n\"\n    \"        ORR     R1,R1,#0x00F00000 \\n\"\n    \"        MCR     p15,0,R1,c1,c0,2  \\n\"\n\n    //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted\n    \"        ISB                       \\n\"\n\n    //Enable VFP/NEON\n    \"        VMRS    R1,FPEXC          \\n\"\n    \"        ORR     R1,R1,#0x40000000 \\n\"\n    \"        VMSR    FPEXC,R1          \\n\"\n\n    //Initialise VFP/NEON registers to 0\n    \"        MOV     R2,#0             \\n\"\n\n    //Initialise D16 registers to 0\n    \"        VMOV    D0, R2,R2         \\n\"\n    \"        VMOV    D1, R2,R2         \\n\"\n    \"        VMOV    D2, R2,R2         \\n\"\n    \"        VMOV    D3, R2,R2         \\n\"\n    \"        VMOV    D4, R2,R2         \\n\"\n    \"        VMOV    D5, R2,R2         \\n\"\n    \"        VMOV    D6, R2,R2         \\n\"\n    \"        VMOV    D7, R2,R2         \\n\"\n    \"        VMOV    D8, R2,R2         \\n\"\n    \"        VMOV    D9, R2,R2         \\n\"\n    \"        VMOV    D10,R2,R2         \\n\"\n    \"        VMOV    D11,R2,R2         \\n\"\n    \"        VMOV    D12,R2,R2         \\n\"\n    \"        VMOV    D13,R2,R2         \\n\"\n    \"        VMOV    D14,R2,R2         \\n\"\n    \"        VMOV    D15,R2,R2         \\n\"\n\n#ifdef __ARM_ADVANCED_SIMD__\n    //Initialise D32 registers to 0\n    \"        VMOV    D16,R2,R2         \\n\"\n    \"        VMOV    D17,R2,R2         \\n\"\n    \"        VMOV    D18,R2,R2         \\n\"\n    \"        VMOV    D19,R2,R2         \\n\"\n    \"        VMOV    D20,R2,R2         \\n\"\n    \"        VMOV    D21,R2,R2         \\n\"\n    \"        VMOV    D22,R2,R2         \\n\"\n    \"        VMOV    D23,R2,R2         \\n\"\n    \"        VMOV    D24,R2,R2         \\n\"\n    \"        VMOV    D25,R2,R2         \\n\"\n    \"        VMOV    D26,R2,R2         \\n\"\n    \"        VMOV    D27,R2,R2         \\n\"\n    \"        VMOV    D28,R2,R2         \\n\"\n    \"        VMOV    D29,R2,R2         \\n\"\n    \"        VMOV    D30,R2,R2         \\n\"\n    \"        VMOV    D31,R2,R2         \\n\"\n#endif\n\n    //Initialise FPSCR to a known state\n    \"        VMRS    R1,FPSCR          \\n\"\n    \"        MOV32   R2,#0x00086060    \\n\" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.\n    \"        AND     R1,R1,R2          \\n\"\n    \"        VMSR    FPSCR,R1          \\n\"\n    : : : \"cc\", \"r1\", \"r2\"\n  );\n}\n\n\n\n#undef __IAR_FT\n#undef __ICCARM_V8\n\n#pragma diag_default=Pe940\n#pragma diag_default=Pe177\n\n#endif /* __CMSIS_ICCARM_H__ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core_A/Include/core_ca.h",
    "content": "/**************************************************************************//**\n * @file     core_ca.h\n * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File\n * @version  V1.0.8\n * @date     23. March 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CA_H_GENERIC\n#define __CORE_CA_H_GENERIC\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n\n/*  CMSIS CA definitions */\n#define __CA_CMSIS_VERSION_MAIN  (1U)                                      /*!< \\brief [31:16] CMSIS-Core(A) main version   */\n#define __CA_CMSIS_VERSION_SUB   (1U)                                      /*!< \\brief [15:0]  CMSIS-Core(A) sub version    */\n#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \\\n                                   __CA_CMSIS_VERSION_SUB          )       /*!< \\brief CMSIS-Core(A) version number         */\n\n#if defined ( __CC_ARM )\n  #if defined (__TARGET_FPU_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined (__ARM_FP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined (__ARMVFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TMS470__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined (__FPU_VFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CA_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CA_H_DEPENDANT\n#define __CORE_CA_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n /* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CA_REV\n    #define __CA_REV              0x0000U\n    #warning \"__CA_REV not defined in device header file; using default!\"\n  #endif\n  \n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n    \n  #ifndef __GIC_PRESENT\n    #define __GIC_PRESENT             1U\n    #warning \"__GIC_PRESENT not defined in device header file; using default!\"\n  #endif\n  \n  #ifndef __TIM_PRESENT\n    #define __TIM_PRESENT             1U\n    #warning \"__TIM_PRESENT not defined in device header file; using default!\"\n  #endif\n  \n  #ifndef __L2C_PRESENT\n    #define __L2C_PRESENT             0U\n    #warning \"__L2C_PRESENT not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< \\brief Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< \\brief Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< \\brief Defines 'write only' permissions */\n#define     __IO    volatile             /*!< \\brief Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*!< \\brief Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*!< \\brief Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*!< \\brief Defines 'read / write' structure member permissions */\n#define RESERVED(N, T) T RESERVED##N;    // placeholder struct members used for \"reserved\" areas\n\n /*******************************************************************************\n  *                 Register Abstraction\n   Core Register contain:\n   - CPSR\n   - CP15 Registers\n   - L2C-310 Cache Controller\n   - Generic Interrupt Controller Distributor\n   - Generic Interrupt Controller Interface\n  ******************************************************************************/\n\n/* Core Register CPSR */\ntypedef union\n{\n  struct\n  {\n    uint32_t M:5;                        /*!< \\brief bit:  0.. 4  Mode field */\n    uint32_t T:1;                        /*!< \\brief bit:      5  Thumb execution state bit */\n    uint32_t F:1;                        /*!< \\brief bit:      6  FIQ mask bit */\n    uint32_t I:1;                        /*!< \\brief bit:      7  IRQ mask bit */\n    uint32_t A:1;                        /*!< \\brief bit:      8  Asynchronous abort mask bit */\n    uint32_t E:1;                        /*!< \\brief bit:      9  Endianness execution state bit */\n    uint32_t IT1:6;                      /*!< \\brief bit: 10..15  If-Then execution state bits 2-7 */\n    uint32_t GE:4;                       /*!< \\brief bit: 16..19  Greater than or Equal flags */\n    RESERVED(0:4, uint32_t)              \n    uint32_t J:1;                        /*!< \\brief bit:     24  Jazelle bit */\n    uint32_t IT0:2;                      /*!< \\brief bit: 25..26  If-Then execution state bits 0-1 */\n    uint32_t Q:1;                        /*!< \\brief bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< \\brief bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< \\brief bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< \\brief bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< \\brief bit:     31  Negative condition code flag */\n  } b;                                   /*!< \\brief Structure used for bit  access */\n  uint32_t w;                            /*!< \\brief Type      used for word access */\n} CPSR_Type;\n\n\n\n/* CPSR Register Definitions */\n#define CPSR_N_Pos                       31U                                    /*!< \\brief CPSR: N Position */\n#define CPSR_N_Msk                       (1UL << CPSR_N_Pos)                    /*!< \\brief CPSR: N Mask */\n\n#define CPSR_Z_Pos                       30U                                    /*!< \\brief CPSR: Z Position */\n#define CPSR_Z_Msk                       (1UL << CPSR_Z_Pos)                    /*!< \\brief CPSR: Z Mask */\n\n#define CPSR_C_Pos                       29U                                    /*!< \\brief CPSR: C Position */\n#define CPSR_C_Msk                       (1UL << CPSR_C_Pos)                    /*!< \\brief CPSR: C Mask */\n\n#define CPSR_V_Pos                       28U                                    /*!< \\brief CPSR: V Position */\n#define CPSR_V_Msk                       (1UL << CPSR_V_Pos)                    /*!< \\brief CPSR: V Mask */\n\n#define CPSR_Q_Pos                       27U                                    /*!< \\brief CPSR: Q Position */\n#define CPSR_Q_Msk                       (1UL << CPSR_Q_Pos)                    /*!< \\brief CPSR: Q Mask */\n\n#define CPSR_IT0_Pos                     25U                                    /*!< \\brief CPSR: IT0 Position */\n#define CPSR_IT0_Msk                     (3UL << CPSR_IT0_Pos)                  /*!< \\brief CPSR: IT0 Mask */\n\n#define CPSR_J_Pos                       24U                                    /*!< \\brief CPSR: J Position */\n#define CPSR_J_Msk                       (1UL << CPSR_J_Pos)                    /*!< \\brief CPSR: J Mask */\n\n#define CPSR_GE_Pos                      16U                                    /*!< \\brief CPSR: GE Position */\n#define CPSR_GE_Msk                      (0xFUL << CPSR_GE_Pos)                 /*!< \\brief CPSR: GE Mask */\n\n#define CPSR_IT1_Pos                     10U                                    /*!< \\brief CPSR: IT1 Position */\n#define CPSR_IT1_Msk                     (0x3FUL << CPSR_IT1_Pos)               /*!< \\brief CPSR: IT1 Mask */\n\n#define CPSR_E_Pos                       9U                                     /*!< \\brief CPSR: E Position */\n#define CPSR_E_Msk                       (1UL << CPSR_E_Pos)                    /*!< \\brief CPSR: E Mask */\n\n#define CPSR_A_Pos                       8U                                     /*!< \\brief CPSR: A Position */\n#define CPSR_A_Msk                       (1UL << CPSR_A_Pos)                    /*!< \\brief CPSR: A Mask */\n\n#define CPSR_I_Pos                       7U                                     /*!< \\brief CPSR: I Position */\n#define CPSR_I_Msk                       (1UL << CPSR_I_Pos)                    /*!< \\brief CPSR: I Mask */\n\n#define CPSR_F_Pos                       6U                                     /*!< \\brief CPSR: F Position */\n#define CPSR_F_Msk                       (1UL << CPSR_F_Pos)                    /*!< \\brief CPSR: F Mask */\n\n#define CPSR_T_Pos                       5U                                     /*!< \\brief CPSR: T Position */\n#define CPSR_T_Msk                       (1UL << CPSR_T_Pos)                    /*!< \\brief CPSR: T Mask */\n\n#define CPSR_M_Pos                       0U                                     /*!< \\brief CPSR: M Position */\n#define CPSR_M_Msk                       (0x1FUL << CPSR_M_Pos)                 /*!< \\brief CPSR: M Mask */\n\n#define CPSR_M_USR                       0x10U                                  /*!< \\brief CPSR: M User mode (PL0) */\n#define CPSR_M_FIQ                       0x11U                                  /*!< \\brief CPSR: M Fast Interrupt mode (PL1) */\n#define CPSR_M_IRQ                       0x12U                                  /*!< \\brief CPSR: M Interrupt mode (PL1) */\n#define CPSR_M_SVC                       0x13U                                  /*!< \\brief CPSR: M Supervisor mode (PL1) */\n#define CPSR_M_MON                       0x16U                                  /*!< \\brief CPSR: M Monitor mode (PL1) */\n#define CPSR_M_ABT                       0x17U                                  /*!< \\brief CPSR: M Abort mode (PL1) */\n#define CPSR_M_HYP                       0x1AU                                  /*!< \\brief CPSR: M Hypervisor mode (PL2) */\n#define CPSR_M_UND                       0x1BU                                  /*!< \\brief CPSR: M Undefined mode (PL1) */\n#define CPSR_M_SYS                       0x1FU                                  /*!< \\brief CPSR: M System mode (PL1) */\n\n/* CP15 Register SCTLR */\ntypedef union\n{\n  struct\n  {\n    uint32_t M:1;                        /*!< \\brief bit:     0  MMU enable */\n    uint32_t A:1;                        /*!< \\brief bit:     1  Alignment check enable */\n    uint32_t C:1;                        /*!< \\brief bit:     2  Cache enable */\n    RESERVED(0:2, uint32_t)              \n    uint32_t CP15BEN:1;                  /*!< \\brief bit:     5  CP15 barrier enable */\n    RESERVED(1:1, uint32_t)              \n    uint32_t B:1;                        /*!< \\brief bit:     7  Endianness model */\n    RESERVED(2:2, uint32_t)              \n    uint32_t SW:1;                       /*!< \\brief bit:    10  SWP and SWPB enable */\n    uint32_t Z:1;                        /*!< \\brief bit:    11  Branch prediction enable */\n    uint32_t I:1;                        /*!< \\brief bit:    12  Instruction cache enable */\n    uint32_t V:1;                        /*!< \\brief bit:    13  Vectors bit */\n    uint32_t RR:1;                       /*!< \\brief bit:    14  Round Robin select */\n    RESERVED(3:2, uint32_t)              \n    uint32_t HA:1;                       /*!< \\brief bit:    17  Hardware Access flag enable */\n    RESERVED(4:1, uint32_t)              \n    uint32_t WXN:1;                      /*!< \\brief bit:    19  Write permission implies XN */\n    uint32_t UWXN:1;                     /*!< \\brief bit:    20  Unprivileged write permission implies PL1 XN */\n    uint32_t FI:1;                       /*!< \\brief bit:    21  Fast interrupts configuration enable */\n    uint32_t U:1;                        /*!< \\brief bit:    22  Alignment model */\n    RESERVED(5:1, uint32_t)              \n    uint32_t VE:1;                       /*!< \\brief bit:    24  Interrupt Vectors Enable */\n    uint32_t EE:1;                       /*!< \\brief bit:    25  Exception Endianness */\n    RESERVED(6:1, uint32_t)              \n    uint32_t NMFI:1;                     /*!< \\brief bit:    27  Non-maskable FIQ (NMFI) support */\n    uint32_t TRE:1;                      /*!< \\brief bit:    28  TEX remap enable. */\n    uint32_t AFE:1;                      /*!< \\brief bit:    29  Access flag enable */\n    uint32_t TE:1;                       /*!< \\brief bit:    30  Thumb Exception enable */\n    RESERVED(7:1, uint32_t)              \n  } b;                                   /*!< \\brief Structure used for bit  access */\n  uint32_t w;                            /*!< \\brief Type      used for word access */\n} SCTLR_Type;\n\n#define SCTLR_TE_Pos                     30U                                    /*!< \\brief SCTLR: TE Position */\n#define SCTLR_TE_Msk                     (1UL << SCTLR_TE_Pos)                  /*!< \\brief SCTLR: TE Mask */\n\n#define SCTLR_AFE_Pos                    29U                                    /*!< \\brief SCTLR: AFE Position */\n#define SCTLR_AFE_Msk                    (1UL << SCTLR_AFE_Pos)                 /*!< \\brief SCTLR: AFE Mask */\n\n#define SCTLR_TRE_Pos                    28U                                    /*!< \\brief SCTLR: TRE Position */\n#define SCTLR_TRE_Msk                    (1UL << SCTLR_TRE_Pos)                 /*!< \\brief SCTLR: TRE Mask */\n\n#define SCTLR_NMFI_Pos                   27U                                    /*!< \\brief SCTLR: NMFI Position */\n#define SCTLR_NMFI_Msk                   (1UL << SCTLR_NMFI_Pos)                /*!< \\brief SCTLR: NMFI Mask */\n\n#define SCTLR_EE_Pos                     25U                                    /*!< \\brief SCTLR: EE Position */\n#define SCTLR_EE_Msk                     (1UL << SCTLR_EE_Pos)                  /*!< \\brief SCTLR: EE Mask */\n\n#define SCTLR_VE_Pos                     24U                                    /*!< \\brief SCTLR: VE Position */\n#define SCTLR_VE_Msk                     (1UL << SCTLR_VE_Pos)                  /*!< \\brief SCTLR: VE Mask */\n\n#define SCTLR_U_Pos                      22U                                    /*!< \\brief SCTLR: U Position */\n#define SCTLR_U_Msk                      (1UL << SCTLR_U_Pos)                   /*!< \\brief SCTLR: U Mask */\n\n#define SCTLR_FI_Pos                     21U                                    /*!< \\brief SCTLR: FI Position */\n#define SCTLR_FI_Msk                     (1UL << SCTLR_FI_Pos)                  /*!< \\brief SCTLR: FI Mask */\n\n#define SCTLR_UWXN_Pos                   20U                                    /*!< \\brief SCTLR: UWXN Position */\n#define SCTLR_UWXN_Msk                   (1UL << SCTLR_UWXN_Pos)                /*!< \\brief SCTLR: UWXN Mask */\n\n#define SCTLR_WXN_Pos                    19U                                    /*!< \\brief SCTLR: WXN Position */\n#define SCTLR_WXN_Msk                    (1UL << SCTLR_WXN_Pos)                 /*!< \\brief SCTLR: WXN Mask */\n\n#define SCTLR_HA_Pos                     17U                                    /*!< \\brief SCTLR: HA Position */\n#define SCTLR_HA_Msk                     (1UL << SCTLR_HA_Pos)                  /*!< \\brief SCTLR: HA Mask */\n\n#define SCTLR_RR_Pos                     14U                                    /*!< \\brief SCTLR: RR Position */\n#define SCTLR_RR_Msk                     (1UL << SCTLR_RR_Pos)                  /*!< \\brief SCTLR: RR Mask */\n\n#define SCTLR_V_Pos                      13U                                    /*!< \\brief SCTLR: V Position */\n#define SCTLR_V_Msk                      (1UL << SCTLR_V_Pos)                   /*!< \\brief SCTLR: V Mask */\n\n#define SCTLR_I_Pos                      12U                                    /*!< \\brief SCTLR: I Position */\n#define SCTLR_I_Msk                      (1UL << SCTLR_I_Pos)                   /*!< \\brief SCTLR: I Mask */\n\n#define SCTLR_Z_Pos                      11U                                    /*!< \\brief SCTLR: Z Position */\n#define SCTLR_Z_Msk                      (1UL << SCTLR_Z_Pos)                   /*!< \\brief SCTLR: Z Mask */\n\n#define SCTLR_SW_Pos                     10U                                    /*!< \\brief SCTLR: SW Position */\n#define SCTLR_SW_Msk                     (1UL << SCTLR_SW_Pos)                  /*!< \\brief SCTLR: SW Mask */\n\n#define SCTLR_B_Pos                      7U                                     /*!< \\brief SCTLR: B Position */\n#define SCTLR_B_Msk                      (1UL << SCTLR_B_Pos)                   /*!< \\brief SCTLR: B Mask */\n\n#define SCTLR_CP15BEN_Pos                5U                                     /*!< \\brief SCTLR: CP15BEN Position */\n#define SCTLR_CP15BEN_Msk                (1UL << SCTLR_CP15BEN_Pos)             /*!< \\brief SCTLR: CP15BEN Mask */\n\n#define SCTLR_C_Pos                      2U                                     /*!< \\brief SCTLR: C Position */\n#define SCTLR_C_Msk                      (1UL << SCTLR_C_Pos)                   /*!< \\brief SCTLR: C Mask */\n\n#define SCTLR_A_Pos                      1U                                     /*!< \\brief SCTLR: A Position */\n#define SCTLR_A_Msk                      (1UL << SCTLR_A_Pos)                   /*!< \\brief SCTLR: A Mask */\n\n#define SCTLR_M_Pos                      0U                                     /*!< \\brief SCTLR: M Position */\n#define SCTLR_M_Msk                      (1UL << SCTLR_M_Pos)                   /*!< \\brief SCTLR: M Mask */\n\n/* CP15 Register ACTLR */\ntypedef union\n{\n#if __CORTEX_A == 5 || defined(DOXYGEN)\n  /** \\brief Structure used for bit access on Cortex-A5 */\n  struct\n  {\n    uint32_t FW:1;                      /*!< \\brief bit:      0  Cache and TLB maintenance broadcast */\n    RESERVED(0:5, uint32_t)              \n    uint32_t SMP:1;                      /*!< \\brief bit:     6  Enables coherent requests to the processor */\n    uint32_t EXCL:1;                     /*!< \\brief bit:     7  Exclusive L1/L2 cache control */\n    RESERVED(1:2, uint32_t)\n    uint32_t DODMBS:1;                   /*!< \\brief bit:    10  Disable optimized data memory barrier behavior */\n    uint32_t DWBST:1;                    /*!< \\brief bit:    11  AXI data write bursts to Normal memory */\n    uint32_t RADIS:1;                    /*!< \\brief bit:    12  L1 Data Cache read-allocate mode disable */\n    uint32_t L1PCTL:2;                   /*!< \\brief bit:13..14  L1 Data prefetch control */    \n    uint32_t BP:2;                       /*!< \\brief bit:16..15  Branch prediction policy */\n    uint32_t RSDIS:1;                    /*!< \\brief bit:    17  Disable return stack operation */\n    uint32_t BTDIS:1;                    /*!< \\brief bit:    18  Disable indirect Branch Target Address Cache (BTAC) */\n    RESERVED(3:9, uint32_t)             \n    uint32_t DBDI:1;                     /*!< \\brief bit:    28  Disable branch dual issue */\n    RESERVED(7:3, uint32_t)              \n } b;\n#endif  \n#if __CORTEX_A == 7 || defined(DOXYGEN)\n  /** \\brief Structure used for bit access on Cortex-A7 */\n  struct\n  {\n    RESERVED(0:6, uint32_t)              \n    uint32_t SMP:1;                      /*!< \\brief bit:     6  Enables coherent requests to the processor */\n    RESERVED(1:3, uint32_t)              \n    uint32_t DODMBS:1;                   /*!< \\brief bit:    10  Disable optimized data memory barrier behavior */\n    uint32_t L2RADIS:1;                  /*!< \\brief bit:    11  L2 Data Cache read-allocate mode disable */\n    uint32_t L1RADIS:1;                  /*!< \\brief bit:    12  L1 Data Cache read-allocate mode disable */\n    uint32_t L1PCTL:2;                   /*!< \\brief bit:13..14  L1 Data prefetch control */\n    uint32_t DDVM:1;                     /*!< \\brief bit:    15  Disable Distributed Virtual Memory (DVM) transactions */\n    RESERVED(3:12, uint32_t)             \n    uint32_t DDI:1;                      /*!< \\brief bit:    28  Disable dual issue */\n    RESERVED(7:3, uint32_t)              \n  } b;\n#endif  \n#if __CORTEX_A == 9 || defined(DOXYGEN)\n  /** \\brief Structure used for bit access on Cortex-A9 */\n  struct\n  {\n    uint32_t FW:1;                       /*!< \\brief bit:     0  Cache and TLB maintenance broadcast */\n    RESERVED(0:1, uint32_t)\n    uint32_t L1PE:1;                     /*!< \\brief bit:     2  Dside prefetch */\n    uint32_t WFLZM:1;                    /*!< \\brief bit:     3  Cache and TLB maintenance broadcast */\n    RESERVED(1:2, uint32_t)\n    uint32_t SMP:1;                      /*!< \\brief bit:     6  Enables coherent requests to the processor */\n    uint32_t EXCL:1;                     /*!< \\brief bit:     7  Exclusive L1/L2 cache control */\n    uint32_t AOW:1;                      /*!< \\brief bit:     8  Enable allocation in one cache way only */\n    uint32_t PARITY:1;                   /*!< \\brief bit:     9  Support for parity checking, if implemented */\n    RESERVED(7:22, uint32_t)              \n  } b;\n#endif  \n  uint32_t w;                            /*!< \\brief Type      used for word access */\n} ACTLR_Type;\n\n#define ACTLR_DDI_Pos                    28U                                     /*!< \\brief ACTLR: DDI Position */\n#define ACTLR_DDI_Msk                    (1UL << ACTLR_DDI_Pos)                  /*!< \\brief ACTLR: DDI Mask */\n\n#define ACTLR_DBDI_Pos                   28U                                     /*!< \\brief ACTLR: DBDI Position */\n#define ACTLR_DBDI_Msk                   (1UL << ACTLR_DBDI_Pos)                 /*!< \\brief ACTLR: DBDI Mask */\n\n#define ACTLR_BTDIS_Pos                  18U                                     /*!< \\brief ACTLR: BTDIS Position */\n#define ACTLR_BTDIS_Msk                  (1UL << ACTLR_BTDIS_Pos)                /*!< \\brief ACTLR: BTDIS Mask */\n\n#define ACTLR_RSDIS_Pos                  17U                                     /*!< \\brief ACTLR: RSDIS Position */\n#define ACTLR_RSDIS_Msk                  (1UL << ACTLR_RSDIS_Pos)                /*!< \\brief ACTLR: RSDIS Mask */\n\n#define ACTLR_BP_Pos                     15U                                     /*!< \\brief ACTLR: BP Position */\n#define ACTLR_BP_Msk                     (3UL << ACTLR_BP_Pos)                   /*!< \\brief ACTLR: BP Mask */\n\n#define ACTLR_DDVM_Pos                   15U                                     /*!< \\brief ACTLR: DDVM Position */\n#define ACTLR_DDVM_Msk                   (1UL << ACTLR_DDVM_Pos)                 /*!< \\brief ACTLR: DDVM Mask */\n\n#define ACTLR_L1PCTL_Pos                 13U                                     /*!< \\brief ACTLR: L1PCTL Position */\n#define ACTLR_L1PCTL_Msk                 (3UL << ACTLR_L1PCTL_Pos)               /*!< \\brief ACTLR: L1PCTL Mask */\n\n#define ACTLR_RADIS_Pos                  12U                                     /*!< \\brief ACTLR: RADIS Position */\n#define ACTLR_RADIS_Msk                  (1UL << ACTLR_RADIS_Pos)                /*!< \\brief ACTLR: RADIS Mask */\n\n#define ACTLR_L1RADIS_Pos                12U                                     /*!< \\brief ACTLR: L1RADIS Position */\n#define ACTLR_L1RADIS_Msk                (1UL << ACTLR_L1RADIS_Pos)              /*!< \\brief ACTLR: L1RADIS Mask */\n\n#define ACTLR_DWBST_Pos                  11U                                     /*!< \\brief ACTLR: DWBST Position */\n#define ACTLR_DWBST_Msk                  (1UL << ACTLR_DWBST_Pos)                /*!< \\brief ACTLR: DWBST Mask */\n\n#define ACTLR_L2RADIS_Pos                11U                                     /*!< \\brief ACTLR: L2RADIS Position */\n#define ACTLR_L2RADIS_Msk                (1UL << ACTLR_L2RADIS_Pos)              /*!< \\brief ACTLR: L2RADIS Mask */\n\n#define ACTLR_DODMBS_Pos                 10U                                     /*!< \\brief ACTLR: DODMBS Position */\n#define ACTLR_DODMBS_Msk                 (1UL << ACTLR_DODMBS_Pos)               /*!< \\brief ACTLR: DODMBS Mask */\n\n#define ACTLR_PARITY_Pos                 9U                                      /*!< \\brief ACTLR: PARITY Position */\n#define ACTLR_PARITY_Msk                 (1UL << ACTLR_PARITY_Pos)               /*!< \\brief ACTLR: PARITY Mask */\n\n#define ACTLR_AOW_Pos                    8U                                      /*!< \\brief ACTLR: AOW Position */\n#define ACTLR_AOW_Msk                    (1UL << ACTLR_AOW_Pos)                  /*!< \\brief ACTLR: AOW Mask */\n\n#define ACTLR_EXCL_Pos                   7U                                      /*!< \\brief ACTLR: EXCL Position */\n#define ACTLR_EXCL_Msk                   (1UL << ACTLR_EXCL_Pos)                 /*!< \\brief ACTLR: EXCL Mask */\n\n#define ACTLR_SMP_Pos                    6U                                      /*!< \\brief ACTLR: SMP Position */\n#define ACTLR_SMP_Msk                    (1UL << ACTLR_SMP_Pos)                  /*!< \\brief ACTLR: SMP Mask */\n\n#define ACTLR_WFLZM_Pos                  3U                                      /*!< \\brief ACTLR: WFLZM Position */\n#define ACTLR_WFLZM_Msk                  (1UL << ACTLR_WFLZM_Pos)                /*!< \\brief ACTLR: WFLZM Mask */\n\n#define ACTLR_L1PE_Pos                   2U                                      /*!< \\brief ACTLR: L1PE Position */\n#define ACTLR_L1PE_Msk                   (1UL << ACTLR_L1PE_Pos)                 /*!< \\brief ACTLR: L1PE Mask */\n\n#define ACTLR_FW_Pos                     0U                                      /*!< \\brief ACTLR: FW Position */\n#define ACTLR_FW_Msk                     (1UL << ACTLR_FW_Pos)                   /*!< \\brief ACTLR: FW Mask */\n\n/* CP15 Register CPACR */\ntypedef union\n{\n  struct\n  {\n    uint32_t CP0:2;                      /*!< \\brief bit:  0..1  Access rights for coprocessor 0 */\n    uint32_t CP1:2;                      /*!< \\brief bit:  2..3  Access rights for coprocessor 1 */\n    uint32_t CP2:2;                      /*!< \\brief bit:  4..5  Access rights for coprocessor 2 */\n    uint32_t CP3:2;                      /*!< \\brief bit:  6..7  Access rights for coprocessor 3 */\n    uint32_t CP4:2;                      /*!< \\brief bit:  8..9  Access rights for coprocessor 4 */\n    uint32_t CP5:2;                      /*!< \\brief bit:10..11  Access rights for coprocessor 5 */\n    uint32_t CP6:2;                      /*!< \\brief bit:12..13  Access rights for coprocessor 6 */\n    uint32_t CP7:2;                      /*!< \\brief bit:14..15  Access rights for coprocessor 7 */\n    uint32_t CP8:2;                      /*!< \\brief bit:16..17  Access rights for coprocessor 8 */\n    uint32_t CP9:2;                      /*!< \\brief bit:18..19  Access rights for coprocessor 9 */\n    uint32_t CP10:2;                     /*!< \\brief bit:20..21  Access rights for coprocessor 10 */\n    uint32_t CP11:2;                     /*!< \\brief bit:22..23  Access rights for coprocessor 11 */\n    uint32_t CP12:2;                     /*!< \\brief bit:24..25  Access rights for coprocessor 11 */\n    uint32_t CP13:2;                     /*!< \\brief bit:26..27  Access rights for coprocessor 11 */\n    uint32_t TRCDIS:1;                   /*!< \\brief bit:    28  Disable CP14 access to trace registers */\n    RESERVED(0:1, uint32_t)              \n    uint32_t D32DIS:1;                   /*!< \\brief bit:    30  Disable use of registers D16-D31 of the VFP register file */\n    uint32_t ASEDIS:1;                   /*!< \\brief bit:    31  Disable Advanced SIMD Functionality */\n  } b;                                   /*!< \\brief Structure used for bit  access */\n  uint32_t w;                            /*!< \\brief Type      used for word access */\n} CPACR_Type;\n\n#define CPACR_ASEDIS_Pos                 31U                                    /*!< \\brief CPACR: ASEDIS Position */\n#define CPACR_ASEDIS_Msk                 (1UL << CPACR_ASEDIS_Pos)              /*!< \\brief CPACR: ASEDIS Mask */\n\n#define CPACR_D32DIS_Pos                 30U                                    /*!< \\brief CPACR: D32DIS Position */\n#define CPACR_D32DIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \\brief CPACR: D32DIS Mask */\n\n#define CPACR_TRCDIS_Pos                 28U                                    /*!< \\brief CPACR: D32DIS Position */\n#define CPACR_TRCDIS_Msk                 (1UL << CPACR_D32DIS_Pos)              /*!< \\brief CPACR: D32DIS Mask */\n\n#define CPACR_CP_Pos_(n)                 (n*2U)                                 /*!< \\brief CPACR: CPn Position */\n#define CPACR_CP_Msk_(n)                 (3UL << CPACR_CP_Pos_(n))              /*!< \\brief CPACR: CPn Mask */\n\n#define CPACR_CP_NA                      0U                                     /*!< \\brief CPACR CPn field: Access denied. */\n#define CPACR_CP_PL1                     1U                                     /*!< \\brief CPACR CPn field: Accessible from PL1 only. */\n#define CPACR_CP_FA                      3U                                     /*!< \\brief CPACR CPn field: Full access. */\n\n/* CP15 Register DFSR */\ntypedef union\n{\n  struct\n  {\n    uint32_t FS0:4;                      /*!< \\brief bit: 0.. 3  Fault Status bits bit 0-3 */\n    uint32_t Domain:4;                   /*!< \\brief bit: 4.. 7  Fault on which domain */\n    RESERVED(0:1, uint32_t)              \n    uint32_t LPAE:1;                     /*!< \\brief bit:     9  Large Physical Address Extension */\n    uint32_t FS1:1;                      /*!< \\brief bit:    10  Fault Status bits bit 4 */\n    uint32_t WnR:1;                      /*!< \\brief bit:    11  Write not Read bit */\n    uint32_t ExT:1;                      /*!< \\brief bit:    12  External abort type */\n    uint32_t CM:1;                       /*!< \\brief bit:    13  Cache maintenance fault */\n    RESERVED(1:18, uint32_t)             \n  } s;                                   /*!< \\brief Structure used for bit  access in short format */\n  struct\n  {\n    uint32_t STATUS:5;                   /*!< \\brief bit: 0.. 5  Fault Status bits */\n    RESERVED(0:3, uint32_t)              \n    uint32_t LPAE:1;                     /*!< \\brief bit:     9  Large Physical Address Extension */\n    RESERVED(1:1, uint32_t)              \n    uint32_t WnR:1;                      /*!< \\brief bit:    11  Write not Read bit */\n    uint32_t ExT:1;                      /*!< \\brief bit:    12  External abort type */\n    uint32_t CM:1;                       /*!< \\brief bit:    13  Cache maintenance fault */\n    RESERVED(2:18, uint32_t)             \n  } l;                                   /*!< \\brief Structure used for bit  access in long format */\n  uint32_t w;                            /*!< \\brief Type      used for word access */\n} DFSR_Type;\n\n#define DFSR_CM_Pos                      13U                                    /*!< \\brief DFSR: CM Position */\n#define DFSR_CM_Msk                      (1UL << DFSR_CM_Pos)                   /*!< \\brief DFSR: CM Mask */\n\n#define DFSR_Ext_Pos                     12U                                    /*!< \\brief DFSR: Ext Position */\n#define DFSR_Ext_Msk                     (1UL << DFSR_Ext_Pos)                  /*!< \\brief DFSR: Ext Mask */\n\n#define DFSR_WnR_Pos                     11U                                    /*!< \\brief DFSR: WnR Position */\n#define DFSR_WnR_Msk                     (1UL << DFSR_WnR_Pos)                  /*!< \\brief DFSR: WnR Mask */\n\n#define DFSR_FS1_Pos                     10U                                    /*!< \\brief DFSR: FS1 Position */\n#define DFSR_FS1_Msk                     (1UL << DFSR_FS1_Pos)                  /*!< \\brief DFSR: FS1 Mask */\n\n#define DFSR_LPAE_Pos                    9U                                    /*!< \\brief DFSR: LPAE Position */\n#define DFSR_LPAE_Msk                    (1UL << DFSR_LPAE_Pos)                /*!< \\brief DFSR: LPAE Mask */\n\n#define DFSR_Domain_Pos                  4U                                     /*!< \\brief DFSR: Domain Position */\n#define DFSR_Domain_Msk                  (0xFUL << DFSR_Domain_Pos)             /*!< \\brief DFSR: Domain Mask */\n\n#define DFSR_FS0_Pos                     0U                                     /*!< \\brief DFSR: FS0 Position */\n#define DFSR_FS0_Msk                     (0xFUL << DFSR_FS0_Pos)                /*!< \\brief DFSR: FS0 Mask */\n\n#define DFSR_STATUS_Pos                  0U                                     /*!< \\brief DFSR: STATUS Position */\n#define DFSR_STATUS_Msk                  (0x3FUL << DFSR_STATUS_Pos)            /*!< \\brief DFSR: STATUS Mask */\n\n/* CP15 Register IFSR */\ntypedef union\n{\n  struct\n  {\n    uint32_t FS0:4;                      /*!< \\brief bit: 0.. 3  Fault Status bits bit 0-3 */\n    RESERVED(0:5, uint32_t)              \n    uint32_t LPAE:1;                     /*!< \\brief bit:     9  Large Physical Address Extension */\n    uint32_t FS1:1;                      /*!< \\brief bit:    10  Fault Status bits bit 4 */\n    RESERVED(1:1, uint32_t)              \n    uint32_t ExT:1;                      /*!< \\brief bit:    12  External abort type */\n    RESERVED(2:19, uint32_t)             \n  } s;                                   /*!< \\brief Structure used for bit access in short format */\n  struct\n  {\n    uint32_t STATUS:6;                   /*!< \\brief bit: 0.. 5  Fault Status bits */\n    RESERVED(0:3, uint32_t)              \n    uint32_t LPAE:1;                     /*!< \\brief bit:     9  Large Physical Address Extension */\n    RESERVED(1:2, uint32_t)              \n    uint32_t ExT:1;                      /*!< \\brief bit:    12  External abort type */\n    RESERVED(2:19, uint32_t)             \n  } l;                                   /*!< \\brief Structure used for bit access in long format */\n  uint32_t w;                            /*!< \\brief Type      used for word access */\n} IFSR_Type;\n\n#define IFSR_ExT_Pos                     12U                                    /*!< \\brief IFSR: ExT Position */\n#define IFSR_ExT_Msk                     (1UL << IFSR_ExT_Pos)                  /*!< \\brief IFSR: ExT Mask */\n\n#define IFSR_FS1_Pos                     10U                                    /*!< \\brief IFSR: FS1 Position */\n#define IFSR_FS1_Msk                     (1UL << IFSR_FS1_Pos)                  /*!< \\brief IFSR: FS1 Mask */\n\n#define IFSR_LPAE_Pos                    9U                                     /*!< \\brief IFSR: LPAE Position */\n#define IFSR_LPAE_Msk                    (0x1UL << IFSR_LPAE_Pos)               /*!< \\brief IFSR: LPAE Mask */\n\n#define IFSR_FS0_Pos                     0U                                     /*!< \\brief IFSR: FS0 Position */\n#define IFSR_FS0_Msk                     (0xFUL << IFSR_FS0_Pos)                /*!< \\brief IFSR: FS0 Mask */\n\n#define IFSR_STATUS_Pos                  0U                                     /*!< \\brief IFSR: STATUS Position */\n#define IFSR_STATUS_Msk                  (0x3FUL << IFSR_STATUS_Pos)            /*!< \\brief IFSR: STATUS Mask */\n\n/* CP15 Register ISR */\ntypedef union\n{\n  struct\n  {\n    RESERVED(0:6, uint32_t)              \n    uint32_t F:1;                        /*!< \\brief bit:     6  FIQ pending bit */\n    uint32_t I:1;                        /*!< \\brief bit:     7  IRQ pending bit */\n    uint32_t A:1;                        /*!< \\brief bit:     8  External abort pending bit */\n    RESERVED(1:23, uint32_t)             \n  } b;                                   /*!< \\brief Structure used for bit  access */\n  uint32_t w;                            /*!< \\brief Type      used for word access */\n} ISR_Type;\n\n#define ISR_A_Pos                        13U                                    /*!< \\brief ISR: A Position */\n#define ISR_A_Msk                        (1UL << ISR_A_Pos)                     /*!< \\brief ISR: A Mask */\n\n#define ISR_I_Pos                        12U                                    /*!< \\brief ISR: I Position */\n#define ISR_I_Msk                        (1UL << ISR_I_Pos)                     /*!< \\brief ISR: I Mask */\n\n#define ISR_F_Pos                        11U                                    /*!< \\brief ISR: F Position */\n#define ISR_F_Msk                        (1UL << ISR_F_Pos)                     /*!< \\brief ISR: F Mask */\n\n/* DACR Register */\n#define DACR_D_Pos_(n)                   (2U*n)                                 /*!< \\brief DACR: Dn Position */\n#define DACR_D_Msk_(n)                   (3UL << DACR_D_Pos_(n))                /*!< \\brief DACR: Dn Mask */\n#define DACR_Dn_NOACCESS                 0U                                     /*!< \\brief DACR Dn field: No access */\n#define DACR_Dn_CLIENT                   1U                                     /*!< \\brief DACR Dn field: Client */\n#define DACR_Dn_MANAGER                  3U                                     /*!< \\brief DACR Dn field: Manager */\n\n/**\n  \\brief     Mask and shift a bit field value for use in a register bit range.\n  \\param [in] field  Name of the register bit field.\n  \\param [in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param [in] field  Name of the register bit field.\n  \\param [in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n\n/**\n \\brief  Union type to access the L2C_310 Cache Controller.\n*/\n#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)\ntypedef struct\n{\n  __IM  uint32_t CACHE_ID;                   /*!< \\brief Offset: 0x0000 (R/ ) Cache ID Register               */\n  __IM  uint32_t CACHE_TYPE;                 /*!< \\brief Offset: 0x0004 (R/ ) Cache Type Register             */\n        RESERVED(0[0x3e], uint32_t)\n  __IOM uint32_t CONTROL;                    /*!< \\brief Offset: 0x0100 (R/W) Control Register                */\n  __IOM uint32_t AUX_CNT;                    /*!< \\brief Offset: 0x0104 (R/W) Auxiliary Control               */\n        RESERVED(1[0x3e], uint32_t)\n  __IOM uint32_t EVENT_CONTROL;              /*!< \\brief Offset: 0x0200 (R/W) Event Counter Control           */\n  __IOM uint32_t EVENT_COUNTER1_CONF;        /*!< \\brief Offset: 0x0204 (R/W) Event Counter 1 Configuration   */\n  __IOM uint32_t EVENT_COUNTER0_CONF;        /*!< \\brief Offset: 0x0208 (R/W) Event Counter 1 Configuration   */\n        RESERVED(2[0x2], uint32_t)\n  __IOM uint32_t INTERRUPT_MASK;             /*!< \\brief Offset: 0x0214 (R/W) Interrupt Mask                  */\n  __IM  uint32_t MASKED_INT_STATUS;          /*!< \\brief Offset: 0x0218 (R/ ) Masked Interrupt Status         */\n  __IM  uint32_t RAW_INT_STATUS;             /*!< \\brief Offset: 0x021c (R/ ) Raw Interrupt Status            */\n  __OM  uint32_t INTERRUPT_CLEAR;            /*!< \\brief Offset: 0x0220 ( /W) Interrupt Clear                 */\n        RESERVED(3[0x143], uint32_t)\n  __IOM uint32_t CACHE_SYNC;                 /*!< \\brief Offset: 0x0730 (R/W) Cache Sync                      */\n        RESERVED(4[0xf], uint32_t)\n  __IOM uint32_t INV_LINE_PA;                /*!< \\brief Offset: 0x0770 (R/W) Invalidate Line By PA           */\n        RESERVED(6[2], uint32_t)\n  __IOM uint32_t INV_WAY;                    /*!< \\brief Offset: 0x077c (R/W) Invalidate by Way               */\n        RESERVED(5[0xc], uint32_t)\n  __IOM uint32_t CLEAN_LINE_PA;              /*!< \\brief Offset: 0x07b0 (R/W) Clean Line by PA                */\n        RESERVED(7[1], uint32_t)\n  __IOM uint32_t CLEAN_LINE_INDEX_WAY;       /*!< \\brief Offset: 0x07b8 (R/W) Clean Line by Index/Way         */\n  __IOM uint32_t CLEAN_WAY;                  /*!< \\brief Offset: 0x07bc (R/W) Clean by Way                    */\n        RESERVED(8[0xc], uint32_t)\n  __IOM uint32_t CLEAN_INV_LINE_PA;          /*!< \\brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA  */\n        RESERVED(9[1], uint32_t)\n  __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY;   /*!< \\brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way  */\n  __IOM uint32_t CLEAN_INV_WAY;              /*!< \\brief Offset: 0x07fc (R/W) Clean and Invalidate by Way     */\n        RESERVED(10[0x40], uint32_t)\n  __IOM uint32_t DATA_LOCK_0_WAY;            /*!< \\brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way          */\n  __IOM uint32_t INST_LOCK_0_WAY;            /*!< \\brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way   */\n  __IOM uint32_t DATA_LOCK_1_WAY;            /*!< \\brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way          */\n  __IOM uint32_t INST_LOCK_1_WAY;            /*!< \\brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way   */\n  __IOM uint32_t DATA_LOCK_2_WAY;            /*!< \\brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way          */\n  __IOM uint32_t INST_LOCK_2_WAY;            /*!< \\brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way   */\n  __IOM uint32_t DATA_LOCK_3_WAY;            /*!< \\brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way          */\n  __IOM uint32_t INST_LOCK_3_WAY;            /*!< \\brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way   */\n  __IOM uint32_t DATA_LOCK_4_WAY;            /*!< \\brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way          */\n  __IOM uint32_t INST_LOCK_4_WAY;            /*!< \\brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way   */\n  __IOM uint32_t DATA_LOCK_5_WAY;            /*!< \\brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way          */\n  __IOM uint32_t INST_LOCK_5_WAY;            /*!< \\brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way   */\n  __IOM uint32_t DATA_LOCK_6_WAY;            /*!< \\brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way          */\n  __IOM uint32_t INST_LOCK_6_WAY;            /*!< \\brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way   */\n  __IOM uint32_t DATA_LOCK_7_WAY;            /*!< \\brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way          */\n  __IOM uint32_t INST_LOCK_7_WAY;            /*!< \\brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way   */\n        RESERVED(11[0x4], uint32_t)\n  __IOM uint32_t LOCK_LINE_EN;               /*!< \\brief Offset: 0x0950 (R/W) Lockdown by Line Enable         */\n  __IOM uint32_t UNLOCK_ALL_BY_WAY;          /*!< \\brief Offset: 0x0954 (R/W) Unlock All Lines by Way         */\n        RESERVED(12[0xaa], uint32_t)\n  __IOM uint32_t ADDRESS_FILTER_START;       /*!< \\brief Offset: 0x0c00 (R/W) Address Filtering Start         */\n  __IOM uint32_t ADDRESS_FILTER_END;         /*!< \\brief Offset: 0x0c04 (R/W) Address Filtering End           */\n        RESERVED(13[0xce], uint32_t)\n  __IOM uint32_t DEBUG_CONTROL;              /*!< \\brief Offset: 0x0f40 (R/W) Debug Control Register          */\n} L2C_310_TypeDef;\n\n#define L2C_310           ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \\brief L2C_310 register set access pointer */\n#endif\n\n#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)\n\n/** \\brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)\n*/\ntypedef struct\n{\n  __IOM uint32_t CTLR;                 /*!< \\brief  Offset: 0x000 (R/W) Distributor Control Register */\n  __IM  uint32_t TYPER;                /*!< \\brief  Offset: 0x004 (R/ ) Interrupt Controller Type Register */\n  __IM  uint32_t IIDR;                 /*!< \\brief  Offset: 0x008 (R/ ) Distributor Implementer Identification Register */\n        RESERVED(0, uint32_t)\n  __IOM uint32_t STATUSR;              /*!< \\brief  Offset: 0x010 (R/W) Error Reporting Status Register, optional */\n        RESERVED(1[11], uint32_t)\n  __OM  uint32_t SETSPI_NSR;           /*!< \\brief  Offset: 0x040 ( /W) Set SPI Register */\n        RESERVED(2, uint32_t)\n  __OM  uint32_t CLRSPI_NSR;           /*!< \\brief  Offset: 0x048 ( /W) Clear SPI Register */\n        RESERVED(3, uint32_t)\n  __OM  uint32_t SETSPI_SR;            /*!< \\brief  Offset: 0x050 ( /W) Set SPI, Secure Register */\n        RESERVED(4, uint32_t)\n  __OM  uint32_t CLRSPI_SR;            /*!< \\brief  Offset: 0x058 ( /W) Clear SPI, Secure Register */\n        RESERVED(5[9], uint32_t)\n  __IOM uint32_t IGROUPR[32];          /*!< \\brief  Offset: 0x080 (R/W) Interrupt Group Registers */\n  __IOM uint32_t ISENABLER[32];        /*!< \\brief  Offset: 0x100 (R/W) Interrupt Set-Enable Registers */\n  __IOM uint32_t ICENABLER[32];        /*!< \\brief  Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */\n  __IOM uint32_t ISPENDR[32];          /*!< \\brief  Offset: 0x200 (R/W) Interrupt Set-Pending Registers */\n  __IOM uint32_t ICPENDR[32];          /*!< \\brief  Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */\n  __IOM uint32_t ISACTIVER[32];        /*!< \\brief  Offset: 0x300 (R/W) Interrupt Set-Active Registers */\n  __IOM uint32_t ICACTIVER[32];        /*!< \\brief  Offset: 0x380 (R/W) Interrupt Clear-Active Registers */\n  __IOM uint32_t IPRIORITYR[255];      /*!< \\brief  Offset: 0x400 (R/W) Interrupt Priority Registers */\n        RESERVED(6, uint32_t)\n  __IOM uint32_t  ITARGETSR[255];      /*!< \\brief  Offset: 0x800 (R/W) Interrupt Targets Registers */\n        RESERVED(7, uint32_t)\n  __IOM uint32_t ICFGR[64];            /*!< \\brief  Offset: 0xC00 (R/W) Interrupt Configuration Registers */\n  __IOM uint32_t IGRPMODR[32];         /*!< \\brief  Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */\n        RESERVED(8[32], uint32_t)\n  __IOM uint32_t NSACR[64];            /*!< \\brief  Offset: 0xE00 (R/W) Non-secure Access Control Registers */\n  __OM  uint32_t SGIR;                 /*!< \\brief  Offset: 0xF00 ( /W) Software Generated Interrupt Register */\n        RESERVED(9[3], uint32_t)\n  __IOM uint32_t CPENDSGIR[4];         /*!< \\brief  Offset: 0xF10 (R/W) SGI Clear-Pending Registers */\n  __IOM uint32_t SPENDSGIR[4];         /*!< \\brief  Offset: 0xF20 (R/W) SGI Set-Pending Registers */\n        RESERVED(10[5236], uint32_t)\n  __IOM uint64_t IROUTER[988];         /*!< \\brief  Offset: 0x6100(R/W) Interrupt Routing Registers */\n}  GICDistributor_Type;\n\n#define GICDistributor      ((GICDistributor_Type      *)     GIC_DISTRIBUTOR_BASE ) /*!< \\brief GIC Distributor register set access pointer */\n\n/* GICDistributor CTLR Register */\n#define GICDistributor_CTLR_EnableGrp0_Pos    0U                                                   /*!< GICDistributor CTLR: EnableGrp0 Position */\n#define GICDistributor_CTLR_EnableGrp0_Msk    (0x1U /*<< GICDistributor_CTLR_EnableGrp0_Pos*/)     /*!< GICDistributor CTLR: EnableGrp0 Mask */\n#define GICDistributor_CTLR_EnableGrp0(x)     (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CTLR_EnableGrp0_Pos*/)) & GICDistributor_CTLR_EnableGrp0_Msk)\n\n#define GICDistributor_CTLR_EnableGrp1_Pos    1U                                                   /*!< GICDistributor CTLR: EnableGrp1 Position */\n#define GICDistributor_CTLR_EnableGrp1_Msk    (0x1U << GICDistributor_CTLR_EnableGrp1_Pos)         /*!< GICDistributor CTLR: EnableGrp1 Mask */\n#define GICDistributor_CTLR_EnableGrp1(x)     (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EnableGrp1_Pos)) & GICDistributor_CTLR_EnableGrp1_Msk)\n\n#define GICDistributor_CTLR_ARE_Pos           4U                                                   /*!< GICDistributor CTLR: ARE Position */\n#define GICDistributor_CTLR_ARE_Msk           (0x1U << GICDistributor_CTLR_ARE_Pos)                /*!< GICDistributor CTLR: ARE Mask */\n#define GICDistributor_CTLR_ARE(x)            (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_ARE_Pos)) & GICDistributor_CTLR_ARE_Msk)\n\n#define GICDistributor_CTLR_DC_Pos            6U                                                   /*!< GICDistributor CTLR: DC Position */\n#define GICDistributor_CTLR_DC_Msk            (0x1U << GICDistributor_CTLR_DC_Pos)                 /*!< GICDistributor CTLR: DC Mask */\n#define GICDistributor_CTLR_DC(x)             (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_DC_Pos)) & GICDistributor_CTLR_DC_Msk)\n\n#define GICDistributor_CTLR_EINWF_Pos         7U                                                   /*!< GICDistributor CTLR: EINWF Position */\n#define GICDistributor_CTLR_EINWF_Msk         (0x1U << GICDistributor_CTLR_EINWF_Pos)              /*!< GICDistributor CTLR: EINWF Mask */\n#define GICDistributor_CTLR_EINWF(x)          (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_EINWF_Pos)) & GICDistributor_CTLR_EINWF_Msk)\n\n#define GICDistributor_CTLR_RWP_Pos           31U                                                  /*!< GICDistributor CTLR: RWP Position */\n#define GICDistributor_CTLR_RWP_Msk           (0x1U << GICDistributor_CTLR_RWP_Pos)                /*!< GICDistributor CTLR: RWP Mask */\n#define GICDistributor_CTLR_RWP(x)            (((uint32_t)(((uint32_t)(x)) << GICDistributor_CTLR_RWP_Pos)) & GICDistributor_CTLR_RWP_Msk)\n\n/* GICDistributor TYPER Register */\n#define GICDistributor_TYPER_ITLinesNumber_Pos 0U                                                    /*!< GICDistributor TYPER: ITLinesNumber Position */\n#define GICDistributor_TYPER_ITLinesNumber_Msk (0x1FU /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/) /*!< GICDistributor TYPER: ITLinesNumber Mask */\n#define GICDistributor_TYPER_ITLinesNumber(x)  (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_TYPER_ITLinesNumber_Pos*/)) & GICDistributor_CTLR_ITLinesNumber_Msk)\n\n#define GICDistributor_TYPER_CPUNumber_Pos    5U                                                   /*!< GICDistributor TYPER: CPUNumber Position */\n#define GICDistributor_TYPER_CPUNumber_Msk    (0x7U << GICDistributor_TYPER_CPUNumber_Pos)         /*!< GICDistributor TYPER: CPUNumber Mask */\n#define GICDistributor_TYPER_CPUNumber(x)     (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_CPUNumber_Pos)) & GICDistributor_TYPER_CPUNumber_Msk)\n\n#define GICDistributor_TYPER_SecurityExtn_Pos 10U                                                  /*!< GICDistributor TYPER: SecurityExtn Position */\n#define GICDistributor_TYPER_SecurityExtn_Msk (0x1U << GICDistributor_TYPER_SecurityExtn_Pos)      /*!< GICDistributor TYPER: SecurityExtn Mask */\n#define GICDistributor_TYPER_SecurityExtn(x)  (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_SecurityExtn_Pos)) & GICDistributor_TYPER_SecurityExtn_Msk)\n\n#define GICDistributor_TYPER_LSPI_Pos         11U                                                  /*!< GICDistributor TYPER: LSPI Position */\n#define GICDistributor_TYPER_LSPI_Msk         (0x1FU << GICDistributor_TYPER_LSPI_Pos)             /*!< GICDistributor TYPER: LSPI Mask */\n#define GICDistributor_TYPER_LSPI(x)          (((uint32_t)(((uint32_t)(x)) << GICDistributor_TYPER_LSPI_Pos)) & GICDistributor_TYPER_LSPI_Msk)\n\n/* GICDistributor IIDR Register */\n#define GICDistributor_IIDR_Implementer_Pos   0U                                                   /*!< GICDistributor IIDR: Implementer Position */\n#define GICDistributor_IIDR_Implementer_Msk   (0xFFFU /*<< GICDistributor_IIDR_Implementer_Pos*/)  /*!< GICDistributor IIDR: Implementer Mask */\n#define GICDistributor_IIDR_Implementer(x)    (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_IIDR_Implementer_Pos*/)) & GICDistributor_IIDR_Implementer_Msk)\n\n#define GICDistributor_IIDR_Revision_Pos      12U                                                  /*!< GICDistributor IIDR: Revision Position */\n#define GICDistributor_IIDR_Revision_Msk      (0xFU << GICDistributor_IIDR_Revision_Pos)           /*!< GICDistributor IIDR: Revision Mask */\n#define GICDistributor_IIDR_Revision(x)       (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Revision_Pos)) & GICDistributor_IIDR_Revision_Msk)\n\n#define GICDistributor_IIDR_Variant_Pos       16U                                                  /*!< GICDistributor IIDR: Variant Position */\n#define GICDistributor_IIDR_Variant_Msk       (0xFU << GICDistributor_IIDR_Variant_Pos)            /*!< GICDistributor IIDR: Variant Mask */\n#define GICDistributor_IIDR_Variant(x)        (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_Variant_Pos)) & GICDistributor_IIDR_Variant_Msk)\n\n#define GICDistributor_IIDR_ProductID_Pos     24U                                                  /*!< GICDistributor IIDR: ProductID Position */\n#define GICDistributor_IIDR_ProductID_Msk     (0xFFU << GICDistributor_IIDR_ProductID_Pos)         /*!< GICDistributor IIDR: ProductID Mask */\n#define GICDistributor_IIDR_ProductID(x)      (((uint32_t)(((uint32_t)(x)) << GICDistributor_IIDR_ProductID_Pos)) & GICDistributor_IIDR_ProductID_Msk)\n\n/* GICDistributor STATUSR Register */\n#define GICDistributor_STATUSR_RRD_Pos        0U                                                   /*!< GICDistributor STATUSR: RRD Position */\n#define GICDistributor_STATUSR_RRD_Msk        (0x1U /*<< GICDistributor_STATUSR_RRD_Pos*/)         /*!< GICDistributor STATUSR: RRD Mask */\n#define GICDistributor_STATUSR_RRD(x)         (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_STATUSR_RRD_Pos*/)) & GICDistributor_STATUSR_RRD_Msk)\n\n#define GICDistributor_STATUSR_WRD_Pos        1U                                                   /*!< GICDistributor STATUSR: WRD Position */\n#define GICDistributor_STATUSR_WRD_Msk        (0x1U << GICDistributor_STATUSR_WRD_Pos)             /*!< GICDistributor STATUSR: WRD Mask */\n#define GICDistributor_STATUSR_WRD(x)         (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WRD_Pos)) & GICDistributor_STATUSR_WRD_Msk)\n\n#define GICDistributor_STATUSR_RWOD_Pos       2U                                                   /*!< GICDistributor STATUSR: RWOD Position */\n#define GICDistributor_STATUSR_RWOD_Msk       (0x1U << GICDistributor_STATUSR_RWOD_Pos)            /*!< GICDistributor STATUSR: RWOD Mask */\n#define GICDistributor_STATUSR_RWOD(x)        (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_RWOD_Pos)) & GICDistributor_STATUSR_RWOD_Msk)\n\n#define GICDistributor_STATUSR_WROD_Pos       3U                                                   /*!< GICDistributor STATUSR: WROD Position */\n#define GICDistributor_STATUSR_WROD_Msk       (0x1U << GICDistributor_STATUSR_WROD_Pos)            /*!< GICDistributor STATUSR: WROD Mask */\n#define GICDistributor_STATUSR_WROD(x)        (((uint32_t)(((uint32_t)(x)) << GICDistributor_STATUSR_WROD_Pos)) & GICDistributor_STATUSR_WROD_Msk)\n\n/* GICDistributor SETSPI_NSR Register */ \n#define GICDistributor_SETSPI_NSR_INTID_Pos   0U                                                   /*!< GICDistributor SETSPI_NSR: INTID Position */\n#define GICDistributor_SETSPI_NSR_INTID_Msk   (0x3FFU /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/)  /*!< GICDistributor SETSPI_NSR: INTID Mask */\n#define GICDistributor_SETSPI_NSR_INTID(x)    (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_NSR_INTID_Pos*/)) & GICDistributor_SETSPI_NSR_INTID_Msk)\n\n/* GICDistributor CLRSPI_NSR Register */ \n#define GICDistributor_CLRSPI_NSR_INTID_Pos   0U                                                   /*!< GICDistributor CLRSPI_NSR: INTID Position */\n#define GICDistributor_CLRSPI_NSR_INTID_Msk   (0x3FFU /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/)  /*!< GICDistributor CLRSPI_NSR: INTID Mask */\n#define GICDistributor_CLRSPI_NSR_INTID(x)    (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_NSR_INTID_Pos*/)) & GICDistributor_CLRSPI_NSR_INTID_Msk)\n\n/* GICDistributor SETSPI_SR Register */\n#define GICDistributor_SETSPI_SR_INTID_Pos    0U                                                  /*!< GICDistributor SETSPI_SR: INTID Position */\n#define GICDistributor_SETSPI_SR_INTID_Msk    (0x3FFU /*<< GICDistributor_SETSPI_SR_INTID_Pos*/)  /*!< GICDistributor SETSPI_SR: INTID Mask */\n#define GICDistributor_SETSPI_SR_INTID(x)     (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SETSPI_SR_INTID_Pos*/)) & GICDistributor_SETSPI_SR_INTID_Msk)\n\n/* GICDistributor CLRSPI_SR Register */\n#define GICDistributor_CLRSPI_SR_INTID_Pos    0U                                                  /*!< GICDistributor CLRSPI_SR: INTID Position */\n#define GICDistributor_CLRSPI_SR_INTID_Msk    (0x3FFU /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/)  /*!< GICDistributor CLRSPI_SR: INTID Mask */\n#define GICDistributor_CLRSPI_SR_INTID(x)     (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_CLRSPI_SR_INTID_Pos*/)) & GICDistributor_CLRSPI_SR_INTID_Msk)\n\n/* GICDistributor ITARGETSR Register */\n#define GICDistributor_ITARGETSR_CPU0_Pos     0U                                                   /*!< GICDistributor ITARGETSR: CPU0 Position */\n#define GICDistributor_ITARGETSR_CPU0_Msk     (0x1U /*<< GICDistributor_ITARGETSR_CPU0_Pos*/)      /*!< GICDistributor ITARGETSR: CPU0 Mask */\n#define GICDistributor_ITARGETSR_CPU0(x)      (((uint8_t)(((uint8_t)(x)) /*<< GICDistributor_ITARGETSR_CPU0_Pos*/)) & GICDistributor_ITARGETSR_CPU0_Msk)\n\n#define GICDistributor_ITARGETSR_CPU1_Pos     1U                                                   /*!< GICDistributor ITARGETSR: CPU1 Position */\n#define GICDistributor_ITARGETSR_CPU1_Msk     (0x1U << GICDistributor_ITARGETSR_CPU1_Pos)          /*!< GICDistributor ITARGETSR: CPU1 Mask */\n#define GICDistributor_ITARGETSR_CPU1(x)      (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU1_Pos)) & GICDistributor_ITARGETSR_CPU1_Msk)\n\n#define GICDistributor_ITARGETSR_CPU2_Pos     2U                                                   /*!< GICDistributor ITARGETSR: CPU2 Position */\n#define GICDistributor_ITARGETSR_CPU2_Msk     (0x1U << GICDistributor_ITARGETSR_CPU2_Pos)          /*!< GICDistributor ITARGETSR: CPU2 Mask */\n#define GICDistributor_ITARGETSR_CPU2(x)      (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU2_Pos)) & GICDistributor_ITARGETSR_CPU2_Msk)\n\n#define GICDistributor_ITARGETSR_CPU3_Pos     3U                                                   /*!< GICDistributor ITARGETSR: CPU3 Position */\n#define GICDistributor_ITARGETSR_CPU3_Msk     (0x1U << GICDistributor_ITARGETSR_CPU3_Pos)          /*!< GICDistributor ITARGETSR: CPU3 Mask */\n#define GICDistributor_ITARGETSR_CPU3(x)      (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU3_Pos)) & GICDistributor_ITARGETSR_CPU3_Msk)\n\n#define GICDistributor_ITARGETSR_CPU4_Pos     4U                                                   /*!< GICDistributor ITARGETSR: CPU4 Position */\n#define GICDistributor_ITARGETSR_CPU4_Msk     (0x1U << GICDistributor_ITARGETSR_CPU4_Pos)          /*!< GICDistributor ITARGETSR: CPU4 Mask */\n#define GICDistributor_ITARGETSR_CPU4(x)      (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU4_Pos)) & GICDistributor_ITARGETSR_CPU4_Msk)\n\n#define GICDistributor_ITARGETSR_CPU5_Pos     5U                                                   /*!< GICDistributor ITARGETSR: CPU5 Position */\n#define GICDistributor_ITARGETSR_CPU5_Msk     (0x1U << GICDistributor_ITARGETSR_CPU5_Pos)          /*!< GICDistributor ITARGETSR: CPU5 Mask */\n#define GICDistributor_ITARGETSR_CPU5(x)      (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU5_Pos)) & GICDistributor_ITARGETSR_CPU5_Msk)\n\n#define GICDistributor_ITARGETSR_CPU6_Pos     6U                                                   /*!< GICDistributor ITARGETSR: CPU6 Position */\n#define GICDistributor_ITARGETSR_CPU6_Msk     (0x1U << GICDistributor_ITARGETSR_CPU6_Pos)          /*!< GICDistributor ITARGETSR: CPU6 Mask */\n#define GICDistributor_ITARGETSR_CPU6(x)      (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU6_Pos)) & GICDistributor_ITARGETSR_CPU6_Msk)\n\n#define GICDistributor_ITARGETSR_CPU7_Pos     7U                                                   /*!< GICDistributor ITARGETSR: CPU7 Position */\n#define GICDistributor_ITARGETSR_CPU7_Msk     (0x1U << GICDistributor_ITARGETSR_CPU7_Pos)          /*!< GICDistributor ITARGETSR: CPU7 Mask */\n#define GICDistributor_ITARGETSR_CPU7(x)      (((uint8_t)(((uint8_t)(x)) << GICDistributor_ITARGETSR_CPU7_Pos)) & GICDistributor_ITARGETSR_CPU7_Msk)\n\n/* GICDistributor SGIR Register */ \n#define GICDistributor_SGIR_INTID_Pos         0U                                                   /*!< GICDistributor SGIR: INTID Position */\n#define GICDistributor_SGIR_INTID_Msk         (0x7U /*<< GICDistributor_SGIR_INTID_Pos*/)          /*!< GICDistributor SGIR: INTID Mask */\n#define GICDistributor_SGIR_INTID(x)          (((uint32_t)(((uint32_t)(x)) /*<< GICDistributor_SGIR_INTID_Pos*/)) & GICDistributor_SGIR_INTID_Msk)\n\n#define GICDistributor_SGIR_NSATT_Pos         15U                                                  /*!< GICDistributor SGIR: NSATT Position */\n#define GICDistributor_SGIR_NSATT_Msk         (0x1U << GICDistributor_SGIR_NSATT_Pos)              /*!< GICDistributor SGIR: NSATT Mask */\n#define GICDistributor_SGIR_NSATT(x)          (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_NSATT_Pos)) & GICDistributor_SGIR_NSATT_Msk)\n\n#define GICDistributor_SGIR_CPUTargetList_Pos 16U                                                  /*!< GICDistributor SGIR: CPUTargetList  Position */\n#define GICDistributor_SGIR_CPUTargetList_Msk (0xFFU << GICDistributor_SGIR_CPUTargetList_Pos)     /*!< GICDistributor SGIR: CPUTargetList  Mask */\n#define GICDistributor_SGIR_CPUTargetList(x)  (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_CPUTargetList_Pos)) & GICDistributor_SGIR_CPUTargetList_Msk)\n\n#define GICDistributor_SGIR_TargetFilterList_Pos 24U                                                /*!< GICDistributor SGIR: TargetFilterList Position */\n#define GICDistributor_SGIR_TargetFilterList_Msk (0x3U << GICDistributor_SGIR_TargetFilterList_Pos) /*!< GICDistributor SGIR: TargetFilterList Mask */\n#define GICDistributor_SGIR_TargetFilterList(x)  (((uint32_t)(((uint32_t)(x)) << GICDistributor_SGIR_TargetFilterList_Pos)) & GICDistributor_SGIR_TargetFilterList_Msk)\n\n/* GICDistributor IROUTER Register */\n#define GICDistributor_IROUTER_Aff0_Pos       0UL                                                  /*!< GICDistributor IROUTER: Aff0 Position */\n#define GICDistributor_IROUTER_Aff0_Msk       (0xFFUL /*<< GICDistributor_IROUTER_Aff0_Pos*/)      /*!< GICDistributor IROUTER: Aff0 Mask */\n#define GICDistributor_IROUTER_Aff0(x)        (((uint64_t)(((uint64_t)(x)) /*<< GICDistributor_IROUTER_Aff0_Pos*/)) & GICDistributor_IROUTER_Aff0_Msk)\n\n#define GICDistributor_IROUTER_Aff1_Pos       8UL                                                  /*!< GICDistributor IROUTER: Aff1 Position */\n#define GICDistributor_IROUTER_Aff1_Msk       (0xFFUL << GICDistributor_IROUTER_Aff1_Pos)          /*!< GICDistributor IROUTER: Aff1 Mask */\n#define GICDistributor_IROUTER_Aff1(x)        (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff1_Pos)) & GICDistributor_IROUTER_Aff1_Msk)\n\n#define GICDistributor_IROUTER_Aff2_Pos       16UL                                                 /*!< GICDistributor IROUTER: Aff2 Position */\n#define GICDistributor_IROUTER_Aff2_Msk       (0xFFUL << GICDistributor_IROUTER_Aff2_Pos)          /*!< GICDistributor IROUTER: Aff2 Mask */\n#define GICDistributor_IROUTER_Aff2(x)        (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff2_Pos)) & GICDistributor_IROUTER_Aff2_Msk)\n\n#define GICDistributor_IROUTER_IRM_Pos        31UL                                                 /*!< GICDistributor IROUTER: IRM Position */\n#define GICDistributor_IROUTER_IRM_Msk        (0xFFUL << GICDistributor_IROUTER_IRM_Pos)           /*!< GICDistributor IROUTER: IRM Mask */\n#define GICDistributor_IROUTER_IRM(x)         (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_IRM_Pos)) & GICDistributor_IROUTER_IRM_Msk)\n\n#define GICDistributor_IROUTER_Aff3_Pos       32UL                                                 /*!< GICDistributor IROUTER: Aff3 Position */\n#define GICDistributor_IROUTER_Aff3_Msk       (0xFFUL << GICDistributor_IROUTER_Aff3_Pos)          /*!< GICDistributor IROUTER: Aff3 Mask */\n#define GICDistributor_IROUTER_Aff3(x)        (((uint64_t)(((uint64_t)(x)) << GICDistributor_IROUTER_Aff3_Pos)) & GICDistributor_IROUTER_Aff3_Msk)\n\n\n\n/** \\brief  Structure type to access the Generic Interrupt Controller Interface (GICC)\n*/\ntypedef struct\n{\n  __IOM uint32_t CTLR;                 /*!< \\brief  Offset: 0x000 (R/W) CPU Interface Control Register */\n  __IOM uint32_t PMR;                  /*!< \\brief  Offset: 0x004 (R/W) Interrupt Priority Mask Register */\n  __IOM uint32_t BPR;                  /*!< \\brief  Offset: 0x008 (R/W) Binary Point Register */\n  __IM  uint32_t IAR;                  /*!< \\brief  Offset: 0x00C (R/ ) Interrupt Acknowledge Register */\n  __OM  uint32_t EOIR;                 /*!< \\brief  Offset: 0x010 ( /W) End Of Interrupt Register */\n  __IM  uint32_t RPR;                  /*!< \\brief  Offset: 0x014 (R/ ) Running Priority Register */\n  __IM  uint32_t HPPIR;                /*!< \\brief  Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */\n  __IOM uint32_t ABPR;                 /*!< \\brief  Offset: 0x01C (R/W) Aliased Binary Point Register */\n  __IM  uint32_t AIAR;                 /*!< \\brief  Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */\n  __OM  uint32_t AEOIR;                /*!< \\brief  Offset: 0x024 ( /W) Aliased End Of Interrupt Register */\n  __IM  uint32_t AHPPIR;               /*!< \\brief  Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */\n  __IOM uint32_t STATUSR;              /*!< \\brief  Offset: 0x02C (R/W) Error Reporting Status Register, optional */\n        RESERVED(1[40], uint32_t)\n  __IOM uint32_t APR[4];               /*!< \\brief  Offset: 0x0D0 (R/W) Active Priority Register */\n  __IOM uint32_t NSAPR[4];             /*!< \\brief  Offset: 0x0E0 (R/W) Non-secure Active Priority Register */\n        RESERVED(2[3], uint32_t)\n  __IM  uint32_t IIDR;                 /*!< \\brief  Offset: 0x0FC (R/ ) CPU Interface Identification Register */\n        RESERVED(3[960], uint32_t)\n  __OM  uint32_t DIR;                  /*!< \\brief  Offset: 0x1000( /W) Deactivate Interrupt Register */\n}  GICInterface_Type;\n\n#define GICInterface        ((GICInterface_Type        *)     GIC_INTERFACE_BASE )   /*!< \\brief GIC Interface register set access pointer */\n\n/* GICInterface CTLR Register */\n#define GICInterface_CTLR_Enable_Pos        0U                                              /*!< PTIM CTLR: Enable Position */\n#define GICInterface_CTLR_Enable_Msk        (0x1U /*<< GICInterface_CTLR_Enable_Pos*/)      /*!< PTIM CTLR: Enable Mask */\n#define GICInterface_CTLR_Enable(x)         (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_CTLR_Enable_Pos*/)) & GICInterface_CTLR_Enable_Msk)\n\n/* GICInterface PMR Register */\n#define GICInterface_PMR_Priority_Pos       0U                                              /*!< PTIM PMR: Priority Position */\n#define GICInterface_PMR_Priority_Msk       (0xFFU /*<< GICInterface_PMR_Priority_Pos*/)    /*!< PTIM PMR: Priority Mask */\n#define GICInterface_PMR_Priority(x)        (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_PMR_Priority_Pos*/)) & GICInterface_PMR_Priority_Msk)\n\n/* GICInterface BPR Register */\n#define GICInterface_BPR_Binary_Point_Pos   0U                                              /*!< PTIM BPR: Binary_Point Position */\n#define GICInterface_BPR_Binary_Point_Msk   (0x7U /*<< GICInterface_BPR_Binary_Point_Pos*/) /*!< PTIM BPR: Binary_Point Mask */\n#define GICInterface_BPR_Binary_Point(x)    (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_BPR_Binary_Point_Pos*/)) & GICInterface_BPR_Binary_Point_Msk)\n\n/* GICInterface IAR Register */\n#define GICInterface_IAR_INTID_Pos          0U                                              /*!< PTIM IAR: INTID Position */\n#define GICInterface_IAR_INTID_Msk          (0xFFFFFFU /*<< GICInterface_IAR_INTID_Pos*/)   /*!< PTIM IAR: INTID Mask */\n#define GICInterface_IAR_INTID(x)           (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IAR_INTID_Pos*/)) & GICInterface_IAR_INTID_Msk)\n\n/* GICInterface EOIR Register */\n#define GICInterface_EOIR_INTID_Pos         0U                                              /*!< PTIM EOIR: INTID Position */\n#define GICInterface_EOIR_INTID_Msk         (0xFFFFFFU /*<< GICInterface_EOIR_INTID_Pos*/)  /*!< PTIM EOIR: INTID Mask */\n#define GICInterface_EOIR_INTID(x)          (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_EOIR_INTID_Pos*/)) & GICInterface_EOIR_INTID_Msk)\n\n/* GICInterface RPR Register */\n#define GICInterface_RPR_INTID_Pos          0U                                              /*!< PTIM RPR: INTID Position */\n#define GICInterface_RPR_INTID_Msk          (0xFFU /*<< GICInterface_RPR_INTID_Pos*/)       /*!< PTIM RPR: INTID Mask */\n#define GICInterface_RPR_INTID(x)           (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_RPR_INTID_Pos*/)) & GICInterface_RPR_INTID_Msk)\n\n/* GICInterface HPPIR Register */\n#define GICInterface_HPPIR_INTID_Pos        0U                                               /*!< PTIM HPPIR: INTID Position */\n#define GICInterface_HPPIR_INTID_Msk        (0xFFFFFFU /*<< GICInterface_HPPIR_INTID_Pos*/)  /*!< PTIM HPPIR: INTID Mask */\n#define GICInterface_HPPIR_INTID(x)         (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_HPPIR_INTID_Pos*/)) & GICInterface_HPPIR_INTID_Msk)\n\n/* GICInterface ABPR Register */\n#define GICInterface_ABPR_Binary_Point_Pos  0U                                               /*!< PTIM ABPR: Binary_Point Position */\n#define GICInterface_ABPR_Binary_Point_Msk  (0x7U /*<< GICInterface_ABPR_Binary_Point_Pos*/) /*!< PTIM ABPR: Binary_Point Mask */\n#define GICInterface_ABPR_Binary_Point(x)   (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_ABPR_Binary_Point_Pos*/)) & GICInterface_ABPR_Binary_Point_Msk)\n\n/* GICInterface AIAR Register */\n#define GICInterface_AIAR_INTID_Pos         0U                                              /*!< PTIM AIAR: INTID Position */\n#define GICInterface_AIAR_INTID_Msk         (0xFFFFFFU /*<< GICInterface_AIAR_INTID_Pos*/)  /*!< PTIM AIAR: INTID Mask */\n#define GICInterface_AIAR_INTID(x)          (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AIAR_INTID_Pos*/)) & GICInterface_AIAR_INTID_Msk)\n\n/* GICInterface AEOIR Register */\n#define GICInterface_AEOIR_INTID_Pos        0U                                              /*!< PTIM AEOIR: INTID Position */\n#define GICInterface_AEOIR_INTID_Msk        (0xFFFFFFU /*<< GICInterface_AEOIR_INTID_Pos*/) /*!< PTIM AEOIR: INTID Mask */\n#define GICInterface_AEOIR_INTID(x)         (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AEOIR_INTID_Pos*/)) & GICInterface_AEOIR_INTID_Msk)\n\n/* GICInterface AHPPIR Register */\n#define GICInterface_AHPPIR_INTID_Pos       0U                                               /*!< PTIM AHPPIR: INTID Position */\n#define GICInterface_AHPPIR_INTID_Msk       (0xFFFFFFU /*<< GICInterface_AHPPIR_INTID_Pos*/) /*!< PTIM AHPPIR: INTID Mask */\n#define GICInterface_AHPPIR_INTID(x)        (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_AHPPIR_INTID_Pos*/)) & GICInterface_AHPPIR_INTID_Msk)\n\n/* GICInterface STATUSR Register */\n#define GICInterface_STATUSR_RRD_Pos        0U                                              /*!< GICInterface STATUSR: RRD Position */\n#define GICInterface_STATUSR_RRD_Msk        (0x1U /*<< GICInterface_STATUSR_RRD_Pos*/)      /*!< GICInterface STATUSR: RRD Mask */\n#define GICInterface_STATUSR_RRD(x)         (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_STATUSR_RRD_Pos*/)) & GICInterface_STATUSR_RRD_Msk)\n\n#define GICInterface_STATUSR_WRD_Pos        1U                                              /*!< GICInterface STATUSR: WRD Position */\n#define GICInterface_STATUSR_WRD_Msk        (0x1U << GICInterface_STATUSR_WRD_Pos)          /*!< GICInterface STATUSR: WRD Mask */\n#define GICInterface_STATUSR_WRD(x)         (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WRD_Pos)) & GICInterface_STATUSR_WRD_Msk)\n\n#define GICInterface_STATUSR_RWOD_Pos       2U                                              /*!< GICInterface STATUSR: RWOD Position */\n#define GICInterface_STATUSR_RWOD_Msk       (0x1U << GICInterface_STATUSR_RWOD_Pos)         /*!< GICInterface STATUSR: RWOD Mask */\n#define GICInterface_STATUSR_RWOD(x)        (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_RWOD_Pos)) & GICInterface_STATUSR_RWOD_Msk)\n\n#define GICInterface_STATUSR_WROD_Pos       3U                                              /*!< GICInterface STATUSR: WROD Position */\n#define GICInterface_STATUSR_WROD_Msk       (0x1U << GICInterface_STATUSR_WROD_Pos)         /*!< GICInterface STATUSR: WROD Mask */\n#define GICInterface_STATUSR_WROD(x)        (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_WROD_Pos)) & GICInterface_STATUSR_WROD_Msk)\n\n#define GICInterface_STATUSR_ASV_Pos        4U                                              /*!< GICInterface STATUSR: ASV Position */\n#define GICInterface_STATUSR_ASV_Msk        (0x1U << GICInterface_STATUSR_ASV_Pos)          /*!< GICInterface STATUSR: ASV Mask */\n#define GICInterface_STATUSR_ASV(x)         (((uint32_t)(((uint32_t)(x)) << GICInterface_STATUSR_ASV_Pos)) & GICInterface_STATUSR_ASV_Msk)\n\n/* GICInterface IIDR Register */\n#define GICInterface_IIDR_Implementer_Pos   0U                                                 /*!< GICInterface IIDR: Implementer Position */\n#define GICInterface_IIDR_Implementer_Msk   (0xFFFU /*<< GICInterface_IIDR_Implementer_Pos*/)  /*!< GICInterface IIDR: Implementer Mask */\n#define GICInterface_IIDR_Implementer(x)    (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_IIDR_Implementer_Pos*/)) & GICInterface_IIDR_Implementer_Msk)\n\n#define GICInterface_IIDR_Revision_Pos      12U                                             /*!< GICInterface IIDR: Revision Position */\n#define GICInterface_IIDR_Revision_Msk      (0xFU << GICInterface_IIDR_Revision_Pos)        /*!< GICInterface IIDR: Revision Mask */\n#define GICInterface_IIDR_Revision(x)       (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Revision_Pos)) & GICInterface_IIDR_Revision_Msk)\n\n#define GICInterface_IIDR_Arch_version_Pos  16U                                             /*!< GICInterface IIDR: Arch_version Position */\n#define GICInterface_IIDR_Arch_version_Msk  (0xFU << GICInterface_IIDR_Arch_version_Pos)    /*!< GICInterface IIDR: Arch_version Mask */\n#define GICInterface_IIDR_Arch_version(x)   (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_Arch_version_Pos)) & GICInterface_IIDR_Arch_version_Msk)\n\n#define GICInterface_IIDR_ProductID_Pos     20U                                             /*!< GICInterface IIDR: ProductID Position */\n#define GICInterface_IIDR_ProductID_Msk     (0xFFFU << GICInterface_IIDR_ProductID_Pos)     /*!< GICInterface IIDR: ProductID Mask */\n#define GICInterface_IIDR_ProductID(x)      (((uint32_t)(((uint32_t)(x)) << GICInterface_IIDR_ProductID_Pos)) & GICInterface_IIDR_ProductID_Msk)\n\n/* GICInterface DIR Register */\n#define GICInterface_DIR_INTID_Pos          0U                                              /*!< PTIM DIR: INTID Position */\n#define GICInterface_DIR_INTID_Msk          (0xFFFFFFU /*<< GICInterface_DIR_INTID_Pos*/)   /*!< PTIM DIR: INTID Mask */\n#define GICInterface_DIR_INTID(x)           (((uint32_t)(((uint32_t)(x)) /*<< GICInterface_DIR_INTID_Pos*/)) & GICInterface_DIR_INTID_Msk)\n#endif /*  (__GIC_PRESENT == 1U) || defined(DOXYGEN) */\n\n#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)\n#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)\n/** \\brief Structure type to access the Private Timer\n*/\ntypedef struct\n{\n  __IOM uint32_t LOAD;            //!< \\brief  Offset: 0x000 (R/W) Private Timer Load Register\n  __IOM uint32_t COUNTER;         //!< \\brief  Offset: 0x004 (R/W) Private Timer Counter Register\n  __IOM uint32_t CONTROL;         //!< \\brief  Offset: 0x008 (R/W) Private Timer Control Register\n  __IOM uint32_t ISR;             //!< \\brief  Offset: 0x00C (R/W) Private Timer Interrupt Status Register\n        RESERVED(0[4], uint32_t)\n  __IOM uint32_t WLOAD;           //!< \\brief  Offset: 0x020 (R/W) Watchdog Load Register\n  __IOM uint32_t WCOUNTER;        //!< \\brief  Offset: 0x024 (R/W) Watchdog Counter Register\n  __IOM uint32_t WCONTROL;        //!< \\brief  Offset: 0x028 (R/W) Watchdog Control Register\n  __IOM uint32_t WISR;            //!< \\brief  Offset: 0x02C (R/W) Watchdog Interrupt Status Register\n  __IOM uint32_t WRESET;          //!< \\brief  Offset: 0x030 (R/W) Watchdog Reset Status Register\n  __OM  uint32_t WDISABLE;        //!< \\brief  Offset: 0x034 ( /W) Watchdog Disable Register\n} Timer_Type;\n#define PTIM ((Timer_Type *) TIMER_BASE )   /*!< \\brief Timer register struct */\n\n/* PTIM Control Register */\n#define PTIM_CONTROL_Enable_Pos             0U                                         /*!< PTIM CONTROL: Enable Position */\n#define PTIM_CONTROL_Enable_Msk             (0x1U /*<< PTIM_CONTROL_Enable_Pos*/)      /*!< PTIM CONTROL: Enable Mask */\n#define PTIM_CONTROL_Enable(x)              (((uint32_t)(((uint32_t)(x)) /*<< PTIM_CONTROL_Enable_Pos*/)) & PTIM_CONTROL_Enable_Msk)\n\n#define PTIM_CONTROL_AutoReload_Pos         1U                                         /*!< PTIM CONTROL: Auto Reload Position */\n#define PTIM_CONTROL_AutoReload_Msk         (0x1U << PTIM_CONTROL_AutoReload_Pos)      /*!< PTIM CONTROL: Auto Reload Mask */\n#define PTIM_CONTROL_AutoReload(x)          (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_AutoReload_Pos)) & PTIM_CONTROL_AutoReload_Msk)\n\n#define PTIM_CONTROL_IRQenable_Pos          2U                                         /*!< PTIM CONTROL: IRQ Enabel Position */\n#define PTIM_CONTROL_IRQenable_Msk          (0x1U << PTIM_CONTROL_IRQenable_Pos)       /*!< PTIM CONTROL: IRQ Enabel Mask */\n#define PTIM_CONTROL_IRQenable(x)           (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_IRQenable_Pos)) & PTIM_CONTROL_IRQenable_Msk)\n\n#define PTIM_CONTROL_Prescaler_Pos          8U                                         /*!< PTIM CONTROL: Prescaler Position */\n#define PTIM_CONTROL_Prescaler_Msk          (0xFFU << PTIM_CONTROL_Prescaler_Pos)      /*!< PTIM CONTROL: Prescaler Mask */\n#define PTIM_CONTROL_Prescaler(x)           (((uint32_t)(((uint32_t)(x)) << PTIM_CONTROL_Prescaler_Pos)) & PTIM_CONTROL_Prescaler_Msk)\n\n/* WCONTROL Watchdog Control Register */\n#define PTIM_WCONTROL_Enable_Pos            0U                                         /*!< PTIM WCONTROL: Enable Position */\n#define PTIM_WCONTROL_Enable_Msk            (0x1U /*<< PTIM_WCONTROL_Enable_Pos*/)     /*!< PTIM WCONTROL: Enable Mask */\n#define PTIM_WCONTROL_Enable(x)             (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WCONTROL_Enable_Pos*/)) & PTIM_WCONTROL_Enable_Msk)\n\n#define PTIM_WCONTROL_AutoReload_Pos        1U                                         /*!< PTIM WCONTROL: Auto Reload Position */\n#define PTIM_WCONTROL_AutoReload_Msk        (0x1U << PTIM_WCONTROL_AutoReload_Pos)     /*!< PTIM WCONTROL: Auto Reload Mask */\n#define PTIM_WCONTROL_AutoReload(x)         (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_AutoReload_Pos)) & PTIM_WCONTROL_AutoReload_Msk)\n\n#define PTIM_WCONTROL_IRQenable_Pos         2U                                         /*!< PTIM WCONTROL: IRQ Enable Position */\n#define PTIM_WCONTROL_IRQenable_Msk         (0x1U << PTIM_WCONTROL_IRQenable_Pos)      /*!< PTIM WCONTROL: IRQ Enable Mask */\n#define PTIM_WCONTROL_IRQenable(x)          (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_IRQenable_Pos)) & PTIM_WCONTROL_IRQenable_Msk)\n\n#define PTIM_WCONTROL_Mode_Pos              3U                                         /*!< PTIM WCONTROL: Watchdog Mode Position */\n#define PTIM_WCONTROL_Mode_Msk              (0x1U << PTIM_WCONTROL_Mode_Pos)           /*!< PTIM WCONTROL: Watchdog Mode Mask */\n#define PTIM_WCONTROL_Mode(x)               (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Mode_Pos)) & PTIM_WCONTROL_Mode_Msk)\n\n#define PTIM_WCONTROL_Presacler_Pos         8U                                         /*!< PTIM WCONTROL: Prescaler Position */\n#define PTIM_WCONTROL_Presacler_Msk         (0xFFU << PTIM_WCONTROL_Presacler_Pos)     /*!< PTIM WCONTROL: Prescaler Mask */\n#define PTIM_WCONTROL_Presacler(x)          (((uint32_t)(((uint32_t)(x)) << PTIM_WCONTROL_Presacler_Pos)) & PTIM_WCONTROL_Presacler_Msk)\n\n/* WISR Watchdog Interrupt Status Register */\n#define PTIM_WISR_EventFlag_Pos             0U                                         /*!< PTIM WISR: Event Flag Position */\n#define PTIM_WISR_EventFlag_Msk             (0x1U /*<< PTIM_WISR_EventFlag_Pos*/)      /*!< PTIM WISR: Event Flag Mask */\n#define PTIM_WISR_EventFlag(x)              (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WISR_EventFlag_Pos*/)) & PTIM_WISR_EventFlag_Msk)\n\n/* WRESET Watchdog Reset Status */\n#define PTIM_WRESET_ResetFlag_Pos           0U                                         /*!< PTIM WRESET: Reset Flag Position */\n#define PTIM_WRESET_ResetFlag_Msk           (0x1U /*<< PTIM_WRESET_ResetFlag_Pos*/)    /*!< PTIM WRESET: Reset Flag Mask */\n#define PTIM_WRESET_ResetFlag(x)            (((uint32_t)(((uint32_t)(x)) /*<< PTIM_WRESET_ResetFlag_Pos*/)) & PTIM_WRESET_ResetFlag_Msk)\n\n#endif /* ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) */\n#endif /* (__TIM_PRESENT == 1U) || defined(DOXYGEN) */\n\n /*******************************************************************************\n  *                Hardware Abstraction Layer\n   Core Function Interface contains:\n   - L1 Cache Functions\n   - L2C-310 Cache Controller Functions \n   - PL1 Timer Functions\n   - GIC Functions\n   - MMU Functions\n  ******************************************************************************/\n \n/* ##########################  L1 Cache functions  ################################# */\n\n/** \\brief Enable Caches by setting I and C bits in SCTLR register.\n*/\n__STATIC_FORCEINLINE void L1C_EnableCaches(void) {\n  __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);\n  __ISB();\n}\n\n/** \\brief Disable Caches by clearing I and C bits in SCTLR register.\n*/\n__STATIC_FORCEINLINE void L1C_DisableCaches(void) {\n  __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));\n  __ISB();\n}\n\n/** \\brief  Enable Branch Prediction by setting Z bit in SCTLR register.\n*/\n__STATIC_FORCEINLINE void L1C_EnableBTAC(void) {\n  __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);\n  __ISB();\n}\n\n/** \\brief  Disable Branch Prediction by clearing Z bit in SCTLR register.\n*/\n__STATIC_FORCEINLINE void L1C_DisableBTAC(void) {\n  __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));\n  __ISB();\n}\n\n/** \\brief  Invalidate entire branch predictor array\n*/\n__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {\n  __set_BPIALL(0);\n  __DSB();     //ensure completion of the invalidation\n  __ISB();     //ensure instruction fetch path sees new state\n}\n\n/** \\brief  Clean instruction cache line by address.\n* \\param [in] va Pointer to instructions to clear the cache for.\n*/\n__STATIC_FORCEINLINE void L1C_InvalidateICacheMVA(void *va) {\n  __set_ICIMVAC((uint32_t)va);\n  __DSB();     //ensure completion of the invalidation\n  __ISB();     //ensure instruction fetch path sees new I cache state\n}\n\n/** \\brief  Invalidate the whole instruction cache\n*/\n__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {\n  __set_ICIALLU(0);\n  __DSB();     //ensure completion of the invalidation\n  __ISB();     //ensure instruction fetch path sees new I cache state\n}\n\n/** \\brief  Clean data cache line by address.\n* \\param [in] va Pointer to data to clear the cache for.\n*/\n__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {\n  __set_DCCMVAC((uint32_t)va);\n  __DMB();     //ensure the ordering of data cache maintenance operations and their effects\n}\n\n/** \\brief  Invalidate data cache line by address.\n* \\param [in] va Pointer to data to invalidate the cache for.\n*/\n__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {\n  __set_DCIMVAC((uint32_t)va);\n  __DMB();     //ensure the ordering of data cache maintenance operations and their effects\n}\n\n/** \\brief  Clean and Invalidate data cache by address.\n* \\param [in] va Pointer to data to invalidate the cache for.\n*/\n__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {\n  __set_DCCIMVAC((uint32_t)va);\n  __DMB();     //ensure the ordering of data cache maintenance operations and their effects\n}\n\n/** \\brief Calculate log2 rounded up\n*  - log(0)  => 0\n*  - log(1)  => 0\n*  - log(2)  => 1\n*  - log(3)  => 2\n*  - log(4)  => 2\n*  - log(5)  => 3\n*        :      :\n*  - log(16) => 4\n*  - log(32) => 5\n*        :      :\n* \\param [in] n input value parameter \n* \\return log2(n)\n*/\n__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)\n{\n  if (n < 2U) {\n    return 0U;\n  }\n  uint8_t log = 0U;\n  uint32_t t = n;\n  while(t > 1U)\n  {\n    log++;\n    t >>= 1U;\n  }\n  if (n & 1U) { log++; }\n  return log;\n}\n\n/** \\brief  Apply cache maintenance to given cache level.\n* \\param [in] level cache level to be maintained\n* \\param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean\n*/\n__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)\n{\n  uint32_t Dummy;\n  uint32_t ccsidr;\n  uint32_t num_sets;\n  uint32_t num_ways;\n  uint32_t shift_way;\n  uint32_t log2_linesize;\n   int32_t log2_num_ways;\n\n  Dummy = level << 1U;\n  /* set csselr, select ccsidr register */\n  __set_CSSELR(Dummy);\n  /* get current ccsidr register */\n  ccsidr = __get_CCSIDR();\n  num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;\n  num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;\n  log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;\n  log2_num_ways = __log2_up(num_ways);\n  if ((log2_num_ways < 0) || (log2_num_ways > 32)) {\n    return; // FATAL ERROR\n  }\n  shift_way = 32U - (uint32_t)log2_num_ways;\n  for(int32_t way = num_ways-1; way >= 0; way--)\n  {\n    for(int32_t set = num_sets-1; set >= 0; set--)\n    {\n      Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);\n      switch (maint)\n      {\n        case 0U: __set_DCISW(Dummy);  break;\n        case 1U: __set_DCCSW(Dummy);  break;\n        default: __set_DCCISW(Dummy); break;\n      }\n    }\n  }\n  __DMB();\n}\n\n/** \\brief  Clean and Invalidate the entire data or unified cache\n* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency\n* \\param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean\n*/\n__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {\n  uint32_t clidr;\n  uint32_t cache_type;\n  clidr =  __get_CLIDR();\n  for(uint32_t i = 0U; i<7U; i++)\n  {\n    cache_type = (clidr >> i*3U) & 0x7UL;\n    if ((cache_type >= 2U) && (cache_type <= 4U))\n    {\n      __L1C_MaintainDCacheSetWay(i, op);\n    }\n  }\n}\n\n/** \\brief  Clean and Invalidate the entire data or unified cache\n* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency\n* \\param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean\n* \\deprecated Use generic L1C_CleanInvalidateCache instead.\n*/\nCMSIS_DEPRECATED\n__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {\n  L1C_CleanInvalidateCache(op);\n}\n\n/** \\brief  Invalidate the whole data cache.\n*/\n__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {\n  L1C_CleanInvalidateCache(0);\n}\n\n/** \\brief  Clean the whole data cache.\n */\n__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {\n  L1C_CleanInvalidateCache(1);\n}\n\n/** \\brief  Clean and invalidate the whole data cache.\n */\n__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {\n  L1C_CleanInvalidateCache(2);\n}\n\n/* ##########################  L2 Cache functions  ################################# */\n#if (__L2C_PRESENT == 1U) || defined(DOXYGEN)\n/** \\brief Cache Sync operation by writing CACHE_SYNC register.\n*/\n__STATIC_INLINE void L2C_Sync(void)\n{\n  L2C_310->CACHE_SYNC = 0x0;\n}\n\n/** \\brief Read cache controller cache ID from CACHE_ID register.\n * \\return L2C_310_TypeDef::CACHE_ID\n */\n__STATIC_INLINE int L2C_GetID (void)\n{\n  return L2C_310->CACHE_ID;\n}\n\n/** \\brief Read cache controller cache type from CACHE_TYPE register.\n*  \\return L2C_310_TypeDef::CACHE_TYPE\n*/\n__STATIC_INLINE int L2C_GetType (void)\n{\n  return L2C_310->CACHE_TYPE;\n}\n\n/** \\brief Invalidate all cache by way\n*/\n__STATIC_INLINE void L2C_InvAllByWay (void)\n{\n  unsigned int assoc;\n\n  if (L2C_310->AUX_CNT & (1U << 16U)) {\n    assoc = 16U;\n  } else {\n    assoc =  8U;\n  }\n  \n  L2C_310->INV_WAY = (1U << assoc) - 1U;\n  while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate\n\n  L2C_Sync();\n}\n\n/** \\brief Clean and Invalidate all cache by way\n*/\n__STATIC_INLINE void L2C_CleanInvAllByWay (void)\n{\n  unsigned int assoc;\n\n  if (L2C_310->AUX_CNT & (1U << 16U)) {\n    assoc = 16U;\n  } else {\n    assoc =  8U;\n  }\n\n  L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;\n  while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate\n\n  L2C_Sync();\n}\n\n/** \\brief Enable Level 2 Cache\n*/\n__STATIC_INLINE void L2C_Enable(void)\n{\n  L2C_310->CONTROL = 0;\n  L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;\n  L2C_310->DEBUG_CONTROL = 0;\n  L2C_310->DATA_LOCK_0_WAY = 0;\n  L2C_310->CACHE_SYNC = 0;\n  L2C_310->CONTROL = 0x01;\n  L2C_Sync();\n}\n\n/** \\brief Disable Level 2 Cache\n*/\n__STATIC_INLINE void L2C_Disable(void)\n{\n  L2C_310->CONTROL = 0x00;\n  L2C_Sync();\n}\n\n/** \\brief Invalidate cache by physical address\n* \\param [in] pa Pointer to data to invalidate cache for.\n*/\n__STATIC_INLINE void L2C_InvPa (void *pa)\n{\n  L2C_310->INV_LINE_PA = (unsigned int)pa;\n  L2C_Sync();\n}\n\n/** \\brief Clean cache by physical address\n* \\param [in] pa Pointer to data to invalidate cache for.\n*/\n__STATIC_INLINE void L2C_CleanPa (void *pa)\n{\n  L2C_310->CLEAN_LINE_PA = (unsigned int)pa;\n  L2C_Sync();\n}\n\n/** \\brief Clean and invalidate cache by physical address\n* \\param [in] pa Pointer to data to invalidate cache for.\n*/\n__STATIC_INLINE void L2C_CleanInvPa (void *pa)\n{\n  L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;\n  L2C_Sync();\n}\n#endif\n\n/* ##########################  GIC functions  ###################################### */\n#if (__GIC_PRESENT == 1U) || defined(DOXYGEN)\n  \n/** \\brief  Enable the interrupt distributor using the GIC's CTLR register.\n*/\n__STATIC_INLINE void GIC_EnableDistributor(void)\n{\n  GICDistributor->CTLR |= 1U;\n}\n\n/** \\brief Disable the interrupt distributor using the GIC's CTLR register.\n*/\n__STATIC_INLINE void GIC_DisableDistributor(void)\n{\n  GICDistributor->CTLR &=~1U;\n}\n\n/** \\brief Read the GIC's TYPER register.\n* \\return GICDistributor_Type::TYPER\n*/\n__STATIC_INLINE uint32_t GIC_DistributorInfo(void)\n{\n  return (GICDistributor->TYPER);\n}\n\n/** \\brief Reads the GIC's IIDR register.\n* \\return GICDistributor_Type::IIDR\n*/\n__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)\n{\n  return (GICDistributor->IIDR);\n}\n\n/** \\brief Sets the GIC's ITARGETSR register for the given interrupt.\n* \\param [in] IRQn Interrupt to be configured.\n* \\param [in] cpu_target CPU interfaces to assign this interrupt to.\n*/\n__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)\n{\n  uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));\n  GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));\n}\n\n/** \\brief Read the GIC's ITARGETSR register.\n* \\param [in] IRQn Interrupt to acquire the configuration for.\n* \\return GICDistributor_Type::ITARGETSR\n*/\n__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)\n{\n  return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;\n}\n\n/** \\brief Enable the CPU's interrupt interface.\n*/\n__STATIC_INLINE void GIC_EnableInterface(void)\n{\n  GICInterface->CTLR |= 1U; //enable interface\n}\n\n/** \\brief Disable the CPU's interrupt interface.\n*/\n__STATIC_INLINE void GIC_DisableInterface(void)\n{\n  GICInterface->CTLR &=~1U; //disable distributor\n}\n\n/** \\brief Read the CPU's IAR register.\n* \\return GICInterface_Type::IAR\n*/\n__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)\n{\n  return (IRQn_Type)(GICInterface->IAR);\n}\n\n/** \\brief Writes the given interrupt number to the CPU's EOIR register.\n* \\param [in] IRQn The interrupt to be signaled as finished.\n*/\n__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)\n{\n  GICInterface->EOIR = IRQn;\n}\n\n/** \\brief Enables the given interrupt using GIC's ISENABLER register.\n* \\param [in] IRQn The interrupt to be enabled.\n*/\n__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)\n{\n  GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);\n}\n\n/** \\brief Get interrupt enable status using GIC's ISENABLER register.\n* \\param [in] IRQn The interrupt to be queried.\n* \\return 0 - interrupt is not enabled, 1 - interrupt is enabled.\n*/\n__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;\n}\n\n/** \\brief Disables the given interrupt using GIC's ICENABLER register.\n* \\param [in] IRQn The interrupt to be disabled.\n*/\n__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)\n{\n  GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);\n}\n\n/** \\brief Get interrupt pending status from GIC's ISPENDR register.\n* \\param [in] IRQn The interrupt to be queried.\n* \\return 0 - interrupt is not pending, 1 - interrupt is pendig.\n*/\n__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  uint32_t pend;\n\n  if (IRQn >= 16U) {\n    pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;\n  } else {\n    // INTID 0-15 Software Generated Interrupt\n    pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;\n    // No CPU identification offered\n    if (pend != 0U) {\n      pend = 1U;\n    } else {\n      pend = 0U;\n    }\n  }\n\n  return (pend);\n}\n\n/** \\brief Sets the given interrupt as pending using GIC's ISPENDR register.\n* \\param [in] IRQn The interrupt to be enabled.\n*/\n__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if (IRQn >= 16U) {\n    GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);\n  } else {\n    // INTID 0-15 Software Generated Interrupt\n    // Forward the interrupt to the CPU interface that requested it\n    GICDistributor->SGIR = (IRQn | 0x02000000U);\n  }\n}\n\n/** \\brief Clears the given interrupt from being pending using GIC's ICPENDR register.\n* \\param [in] IRQn The interrupt to be enabled.\n*/\n__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if (IRQn >= 16U) {\n    GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);\n  } else {\n    // INTID 0-15 Software Generated Interrupt\n    GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);\n  }\n}\n\n/** \\brief Sets the interrupt configuration using GIC's ICFGR register.\n* \\param [in] IRQn The interrupt to be configured.\n* \\param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)\n*                                           Bit 1: 0 - level sensitive, 1 - edge triggered\n*/\n__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)\n{\n  uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];  /* read current register content */\n  uint32_t shift = (IRQn % 16U) << 1U;                 /* calculate shift value */\n\n  int_config &= 3U;                                    /* only 2 bits are valid */\n  icfgr &= (~(3U         << shift));                   /* clear bits to change */\n  icfgr |= (  int_config << shift);                    /* set new configuration */\n\n  GICDistributor->ICFGR[IRQn / 16U] = icfgr;           /* write new register content */\n}\n\n/** \\brief Get the interrupt configuration from the GIC's ICFGR register.\n* \\param [in] IRQn Interrupt to acquire the configuration for.\n* \\return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)\n*                                 Bit 1: 0 - level sensitive, 1 - edge triggered\n*/\n__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)\n{\n  return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));\n}\n\n/** \\brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.\n* \\param [in] IRQn The interrupt to be configured.\n* \\param [in] priority The priority for the interrupt, lower values denote higher priorities.\n*/\n__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));\n  GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));\n}\n\n/** \\brief Read the current interrupt priority from GIC's IPRIORITYR register.\n* \\param [in] IRQn The interrupt to be queried.\n*/\n__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)\n{\n  return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;\n}\n\n/** \\brief Set the interrupt priority mask using CPU's PMR register.\n* \\param [in] priority Priority mask to be set.\n*/\n__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)\n{\n  GICInterface->PMR = priority & 0xFFUL; //set priority mask\n}\n\n/** \\brief Read the current interrupt priority mask from CPU's PMR register.\n* \\result GICInterface_Type::PMR\n*/\n__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)\n{\n  return GICInterface->PMR;\n}\n\n/** \\brief Configures the group priority and subpriority split point using CPU's BPR register.\n* \\param [in] binary_point Amount of bits used as subpriority.\n*/\n__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)\n{\n  GICInterface->BPR = binary_point & 7U; //set binary point\n}\n\n/** \\brief Read the current group priority and subpriority split point from CPU's BPR register.\n* \\return GICInterface_Type::BPR\n*/\n__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)\n{\n  return GICInterface->BPR;\n}\n\n/** \\brief Get the status for a given interrupt.\n* \\param [in] IRQn The interrupt to get status for.\n* \\return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active\n*/\n__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)\n{\n  uint32_t pending, active;\n\n  active = ((GICDistributor->ISACTIVER[IRQn / 32U])  >> (IRQn % 32U)) & 1UL;\n  pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;\n\n  return ((active<<1U) | pending);\n}\n\n/** \\brief Generate a software interrupt using GIC's SGIR register.\n* \\param [in] IRQn Software interrupt to be generated.\n* \\param [in] target_list List of CPUs the software interrupt should be forwarded to.\n* \\param [in] filter_list Filter to be applied to determine interrupt receivers.\n*/\n__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)\n{\n  GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);\n}\n\n/** \\brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.\n* \\return GICInterface_Type::HPPIR\n*/\n__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) \n{ \n  return GICInterface->HPPIR; \n}\n\n/** \\brief Provides information about the implementer and revision of the CPU interface.\n* \\return GICInterface_Type::IIDR\n*/\n__STATIC_INLINE uint32_t GIC_GetInterfaceId(void)\n{ \n  return GICInterface->IIDR; \n}\n\n/** \\brief Set the interrupt group from the GIC's IGROUPR register.\n* \\param [in] IRQn The interrupt to be queried.\n* \\param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1\n*/\n__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)\n{\n  uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];\n  uint32_t shift   = (IRQn % 32U);\n\n  igroupr &= (~(1U          << shift));\n  igroupr |= ( (group & 1U) << shift);\n\n  GICDistributor->IGROUPR[IRQn / 32U] = igroupr;\n}\n#define GIC_SetSecurity         GIC_SetGroup\n\n/** \\brief Get the interrupt group from the GIC's IGROUPR register.\n* \\param [in] IRQn The interrupt to be queried.\n* \\return 0 - Group 0, 1 - Group 1\n*/\n__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)\n{\n  return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;\n}\n#define GIC_GetSecurity         GIC_GetGroup\n\n/** \\brief Initialize the interrupt distributor.\n*/\n__STATIC_INLINE void GIC_DistInit(void)\n{\n  uint32_t i;\n  uint32_t num_irq = 0U;\n  uint32_t priority_field;\n\n  //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,\n  //configuring all of the interrupts as Secure.\n\n  //Disable interrupt forwarding\n  GIC_DisableDistributor();\n  //Get the maximum number of interrupts that the GIC supports\n  num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);\n\n  /* Priority level is implementation defined.\n   To determine the number of priority bits implemented write 0xFF to an IPRIORITYR\n   priority field and read back the value stored.*/\n  GIC_SetPriority((IRQn_Type)0U, 0xFFU);\n  priority_field = GIC_GetPriority((IRQn_Type)0U);\n\n  for (i = 32U; i < num_irq; i++)\n  {\n      //Disable the SPI interrupt\n      GIC_DisableIRQ((IRQn_Type)i);\n      //Set level-sensitive (and N-N model)\n      GIC_SetConfiguration((IRQn_Type)i, 0U);\n      //Set priority\n      GIC_SetPriority((IRQn_Type)i, priority_field/2U);\n      //Set target list to CPU0\n      GIC_SetTarget((IRQn_Type)i, 1U);\n  }\n  //Enable distributor\n  GIC_EnableDistributor();\n}\n\n/** \\brief Initialize the CPU's interrupt interface\n*/\n__STATIC_INLINE void GIC_CPUInterfaceInit(void)\n{\n  uint32_t i;\n  uint32_t priority_field;\n\n  //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,\n  //configuring all of the interrupts as Secure.\n\n  //Disable interrupt forwarding\n  GIC_DisableInterface();\n\n  /* Priority level is implementation defined.\n   To determine the number of priority bits implemented write 0xFF to an IPRIORITYR\n   priority field and read back the value stored.*/\n  GIC_SetPriority((IRQn_Type)0U, 0xFFU);\n  priority_field = GIC_GetPriority((IRQn_Type)0U);\n\n  //SGI and PPI\n  for (i = 0U; i < 32U; i++)\n  {\n    if(i > 15U) {\n      //Set level-sensitive (and N-N model) for PPI\n      GIC_SetConfiguration((IRQn_Type)i, 0U);\n    }\n    //Disable SGI and PPI interrupts\n    GIC_DisableIRQ((IRQn_Type)i);\n    //Set priority\n    GIC_SetPriority((IRQn_Type)i, priority_field/2U);\n  }\n  //Enable interface\n  GIC_EnableInterface();\n  //Set binary point to 0\n  GIC_SetBinaryPoint(0U);\n  //Set priority mask\n  GIC_SetInterfacePriorityMask(0xFFU);\n}\n\n/** \\brief Initialize and enable the GIC\n*/\n__STATIC_INLINE void GIC_Enable(void)\n{\n  GIC_DistInit();\n  GIC_CPUInterfaceInit(); //per CPU\n}\n#endif\n\n/* ##########################  Generic Timer functions  ############################ */\n#if (__TIM_PRESENT == 1U) || defined(DOXYGEN)\n  \n/* PL1 Physical Timer */\n#if (__CORTEX_A == 7U) || defined(DOXYGEN)\n  \n/** \\brief Physical Timer Control register */\ntypedef union\n{\n  struct\n  {\n    uint32_t ENABLE:1;      /*!< \\brief bit: 0      Enables the timer. */\n    uint32_t IMASK:1;       /*!< \\brief bit: 1      Timer output signal mask bit. */\n    uint32_t ISTATUS:1;     /*!< \\brief bit: 2      The status of the timer. */\n    RESERVED(0:29, uint32_t)\n  } b;                      /*!< \\brief Structure used for bit  access */\n  uint32_t w;               /*!< \\brief Type      used for word access */\n} CNTP_CTL_Type;\n\n/** \\brief Configures the frequency the timer shall run at.\n* \\param [in] value The timer frequency in Hz.\n*/\n__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)\n{\n  __set_CNTFRQ(value);\n  __ISB();\n}\n\n/** \\brief Sets the reset value of the timer.\n* \\param [in] value The value the timer is loaded with.\n*/\n__STATIC_INLINE void PL1_SetLoadValue(uint32_t value)\n{\n  __set_CNTP_TVAL(value);\n  __ISB();\n}\n\n/** \\brief Get the current counter value.\n* \\return Current counter value.\n*/\n__STATIC_INLINE uint32_t PL1_GetCurrentValue(void)\n{\n  return(__get_CNTP_TVAL());\n}\n\n/** \\brief Get the current physical counter value.\n* \\return Current physical counter value.\n*/\n__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)\n{\n  return(__get_CNTPCT());\n}\n\n/** \\brief Set the physical compare value.\n* \\param [in] value New physical timer compare value.\n*/\n__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)\n{\n  __set_CNTP_CVAL(value);\n  __ISB();\n}\n\n/** \\brief Get the physical compare value.\n* \\return Physical compare value.\n*/\n__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)\n{\n  return(__get_CNTP_CVAL());\n}\n\n/** \\brief Configure the timer by setting the control value.\n* \\param [in] value New timer control value.\n*/\n__STATIC_INLINE void PL1_SetControl(uint32_t value)\n{\n  __set_CNTP_CTL(value);\n  __ISB();\n}\n\n/** \\brief Get the control value.\n* \\return Control value.\n*/\n__STATIC_INLINE uint32_t PL1_GetControl(void)\n{\n  return(__get_CNTP_CTL());\n}\n#endif\n\n/* Private Timer */\n#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN)\n/** \\brief Set the load value to timers LOAD register.\n* \\param [in] value The load value to be set.\n*/\n__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)\n{\n  PTIM->LOAD = value;\n}\n\n/** \\brief Get the load value from timers LOAD register.\n* \\return Timer_Type::LOAD\n*/\n__STATIC_INLINE uint32_t PTIM_GetLoadValue(void)\n{\n  return(PTIM->LOAD);\n}\n\n/** \\brief Set current counter value from its COUNTER register.\n*/\n__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)\n{\n  PTIM->COUNTER = value;\n}\n\n/** \\brief Get current counter value from timers COUNTER register.\n* \\result Timer_Type::COUNTER\n*/\n__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)\n{\n  return(PTIM->COUNTER);\n}\n\n/** \\brief Configure the timer using its CONTROL register.\n* \\param [in] value The new configuration value to be set.\n*/\n__STATIC_INLINE void PTIM_SetControl(uint32_t value)\n{\n  PTIM->CONTROL = value;\n}\n\n/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.\n* \\return Timer_Type::CONTROL\n*/\n__STATIC_INLINE uint32_t PTIM_GetControl(void)\n{\n  return(PTIM->CONTROL);\n}\n\n/** ref Timer_Type::CONTROL Get the event flag in timers ISR register.\n* \\return 0 - flag is not set, 1- flag is set\n*/\n__STATIC_INLINE uint32_t PTIM_GetEventFlag(void)\n{\n  return (PTIM->ISR & 1UL);\n}\n\n/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.\n*/\n__STATIC_INLINE void PTIM_ClearEventFlag(void)\n{\n  PTIM->ISR = 1;\n}\n#endif\n#endif\n\n/* ##########################  MMU functions  ###################################### */\n\n#define SECTION_DESCRIPTOR      (0x2)\n#define SECTION_MASK            (0xFFFFFFFC)\n\n#define SECTION_TEXCB_MASK      (0xFFFF8FF3)\n#define SECTION_B_SHIFT         (2)\n#define SECTION_C_SHIFT         (3)\n#define SECTION_TEX0_SHIFT      (12)\n#define SECTION_TEX1_SHIFT      (13)\n#define SECTION_TEX2_SHIFT      (14)\n\n#define SECTION_XN_MASK         (0xFFFFFFEF)\n#define SECTION_XN_SHIFT        (4)\n\n#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)\n#define SECTION_DOMAIN_SHIFT    (5)\n\n#define SECTION_P_MASK          (0xFFFFFDFF)\n#define SECTION_P_SHIFT         (9)\n\n#define SECTION_AP_MASK         (0xFFFF73FF)\n#define SECTION_AP_SHIFT        (10)\n#define SECTION_AP2_SHIFT       (15)\n\n#define SECTION_S_MASK          (0xFFFEFFFF)\n#define SECTION_S_SHIFT         (16)\n\n#define SECTION_NG_MASK         (0xFFFDFFFF)\n#define SECTION_NG_SHIFT        (17)\n\n#define SECTION_NS_MASK         (0xFFF7FFFF)\n#define SECTION_NS_SHIFT        (19)\n\n#define PAGE_L1_DESCRIPTOR      (0x1)\n#define PAGE_L1_MASK            (0xFFFFFFFC)\n\n#define PAGE_L2_4K_DESC         (0x2)\n#define PAGE_L2_4K_MASK         (0xFFFFFFFD)\n\n#define PAGE_L2_64K_DESC        (0x1)\n#define PAGE_L2_64K_MASK        (0xFFFFFFFC)\n\n#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)\n#define PAGE_4K_B_SHIFT         (2)\n#define PAGE_4K_C_SHIFT         (3)\n#define PAGE_4K_TEX0_SHIFT      (6)\n#define PAGE_4K_TEX1_SHIFT      (7)\n#define PAGE_4K_TEX2_SHIFT      (8)\n\n#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)\n#define PAGE_64K_B_SHIFT        (2)\n#define PAGE_64K_C_SHIFT        (3)\n#define PAGE_64K_TEX0_SHIFT     (12)\n#define PAGE_64K_TEX1_SHIFT     (13)\n#define PAGE_64K_TEX2_SHIFT     (14)\n\n#define PAGE_TEXCB_MASK         (0xFFFF8FF3)\n#define PAGE_B_SHIFT            (2)\n#define PAGE_C_SHIFT            (3)\n#define PAGE_TEX_SHIFT          (12)\n\n#define PAGE_XN_4K_MASK         (0xFFFFFFFE)\n#define PAGE_XN_4K_SHIFT        (0)\n#define PAGE_XN_64K_MASK        (0xFFFF7FFF)\n#define PAGE_XN_64K_SHIFT       (15)\n\n#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)\n#define PAGE_DOMAIN_SHIFT       (5)\n\n#define PAGE_P_MASK             (0xFFFFFDFF)\n#define PAGE_P_SHIFT            (9)\n\n#define PAGE_AP_MASK            (0xFFFFFDCF)\n#define PAGE_AP_SHIFT           (4)\n#define PAGE_AP2_SHIFT          (9)\n\n#define PAGE_S_MASK             (0xFFFFFBFF)\n#define PAGE_S_SHIFT            (10)\n\n#define PAGE_NG_MASK            (0xFFFFF7FF)\n#define PAGE_NG_SHIFT           (11)\n\n#define PAGE_NS_MASK            (0xFFFFFFF7)\n#define PAGE_NS_SHIFT           (3)\n\n#define OFFSET_1M               (0x00100000)\n#define OFFSET_64K              (0x00010000)\n#define OFFSET_4K               (0x00001000)\n\n#define DESCRIPTOR_FAULT        (0x00000000)\n\n/* Attributes enumerations */\n\n/* Region size attributes */\ntypedef enum\n{\n   SECTION,\n   PAGE_4k,\n   PAGE_64k,\n} mmu_region_size_Type;\n\n/* Region type attributes */\ntypedef enum\n{\n   NORMAL,\n   DEVICE,\n   SHARED_DEVICE,\n   NON_SHARED_DEVICE,\n   STRONGLY_ORDERED\n} mmu_memory_Type;\n\n/* Region cacheability attributes */\ntypedef enum\n{\n   NON_CACHEABLE,\n   WB_WA,\n   WT,\n   WB_NO_WA,\n} mmu_cacheability_Type;\n\n/* Region parity check attributes */\ntypedef enum\n{\n   ECC_DISABLED,\n   ECC_ENABLED,\n} mmu_ecc_check_Type;\n\n/* Region execution attributes */\ntypedef enum\n{\n   EXECUTE,\n   NON_EXECUTE,\n} mmu_execute_Type;\n\n/* Region global attributes */\ntypedef enum\n{\n   GLOBAL,\n   NON_GLOBAL,\n} mmu_global_Type;\n\n/* Region shareability attributes */\ntypedef enum\n{\n   NON_SHARED,\n   SHARED,\n} mmu_shared_Type;\n\n/* Region security attributes */\ntypedef enum\n{\n   SECURE,\n   NON_SECURE,\n} mmu_secure_Type;\n\n/* Region access attributes */\ntypedef enum\n{\n   NO_ACCESS,\n   RW,\n   READ,\n} mmu_access_Type;\n\n/* Memory Region definition */\ntypedef struct RegionStruct {\n    mmu_region_size_Type rg_t;\n    mmu_memory_Type mem_t;\n    uint8_t domain;\n    mmu_cacheability_Type inner_norm_t;\n    mmu_cacheability_Type outer_norm_t;\n    mmu_ecc_check_Type e_t;\n    mmu_execute_Type xn_t;\n    mmu_global_Type g_t;\n    mmu_secure_Type sec_t;\n    mmu_access_Type priv_t;\n    mmu_access_Type user_t;\n    mmu_shared_Type sh_t;\n\n} mmu_region_attributes_Type;\n\n//Following macros define the descriptors and attributes\n//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0\n#define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = WB_WA; \\\n                                   region.outer_norm_t = WB_WA; \\\n                                   region.mem_t = NORMAL; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = EXECUTE; \\\n                                   region.priv_t = RW; \\\n                                   region.user_t = RW; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetSectionDescriptor(&descriptor_l1, region);\n\n//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0\n#define section_normal_nc(descriptor_l1, region)     region.rg_t = SECTION; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = NON_CACHEABLE; \\\n                                   region.outer_norm_t = NON_CACHEABLE; \\\n                                   region.mem_t = NORMAL; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = EXECUTE; \\\n                                   region.priv_t = RW; \\\n                                   region.user_t = RW; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetSectionDescriptor(&descriptor_l1, region);\n\n//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0\n#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = WB_WA; \\\n                                   region.outer_norm_t = WB_WA; \\\n                                   region.mem_t = NORMAL; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = EXECUTE; \\\n                                   region.priv_t = READ; \\\n                                   region.user_t = READ; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetSectionDescriptor(&descriptor_l1, region);\n\n//Sect_Normal_RO. Sect_Normal_Cod, but not executable\n#define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = WB_WA; \\\n                                   region.outer_norm_t = WB_WA; \\\n                                   region.mem_t = NORMAL; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = NON_EXECUTE; \\\n                                   region.priv_t = READ; \\\n                                   region.user_t = READ; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetSectionDescriptor(&descriptor_l1, region);\n\n//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable\n#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = WB_WA; \\\n                                   region.outer_norm_t = WB_WA; \\\n                                   region.mem_t = NORMAL; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = NON_EXECUTE; \\\n                                   region.priv_t = RW; \\\n                                   region.user_t = RW; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetSectionDescriptor(&descriptor_l1, region);\n//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0\n#define section_so(descriptor_l1, region) region.rg_t = SECTION; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = NON_CACHEABLE; \\\n                                   region.outer_norm_t = NON_CACHEABLE; \\\n                                   region.mem_t = STRONGLY_ORDERED; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = NON_EXECUTE; \\\n                                   region.priv_t = RW; \\\n                                   region.user_t = RW; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetSectionDescriptor(&descriptor_l1, region);\n\n//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0\n#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = NON_CACHEABLE; \\\n                                   region.outer_norm_t = NON_CACHEABLE; \\\n                                   region.mem_t = STRONGLY_ORDERED; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = NON_EXECUTE; \\\n                                   region.priv_t = READ; \\\n                                   region.user_t = READ; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetSectionDescriptor(&descriptor_l1, region);\n\n//Sect_Device_RW. Sect_Device_RO, but writeable\n#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = NON_CACHEABLE; \\\n                                   region.outer_norm_t = NON_CACHEABLE; \\\n                                   region.mem_t = STRONGLY_ORDERED; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = NON_EXECUTE; \\\n                                   region.priv_t = RW; \\\n                                   region.user_t = RW; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetSectionDescriptor(&descriptor_l1, region);\n//Page_4k_Device_RW.  Shared device, not executable, rw, domain 0\n#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = NON_CACHEABLE; \\\n                                   region.outer_norm_t = NON_CACHEABLE; \\\n                                   region.mem_t = SHARED_DEVICE; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = NON_EXECUTE; \\\n                                   region.priv_t = RW; \\\n                                   region.user_t = RW; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);\n\n//Page_64k_Device_RW.  Shared device, not executable, rw, domain 0\n#define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \\\n                                   region.domain = 0x0; \\\n                                   region.e_t = ECC_DISABLED; \\\n                                   region.g_t = GLOBAL; \\\n                                   region.inner_norm_t = NON_CACHEABLE; \\\n                                   region.outer_norm_t = NON_CACHEABLE; \\\n                                   region.mem_t = SHARED_DEVICE; \\\n                                   region.sec_t = SECURE; \\\n                                   region.xn_t = NON_EXECUTE; \\\n                                   region.priv_t = RW; \\\n                                   region.user_t = RW; \\\n                                   region.sh_t = NON_SHARED; \\\n                                   MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);\n\n/** \\brief  Set section execution-never attribute\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)\n{\n  *descriptor_l1 &= SECTION_XN_MASK;\n  *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set section domain\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]            domain  Section domain\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)\n{\n  *descriptor_l1 &= SECTION_DOMAIN_MASK;\n  *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set section parity check\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)\n{\n  *descriptor_l1 &= SECTION_P_MASK;\n  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set section access privileges\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]              user  User Level Access: NO_ACCESS, RW, READ\n  \\param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ\n  \\param [in]               afe  Access flag enable\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)\n{\n  uint32_t ap = 0;\n\n  if (afe == 0) { //full access\n    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }\n    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }\n    else if ((priv == RW) && (user == READ))        { ap = 0x2; }\n    else if ((priv == RW) && (user == RW))          { ap = 0x3; }\n    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }\n    else if ((priv == READ) && (user == READ))      { ap = 0x7; }\n  }\n\n  else { //Simplified access\n    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }\n    else if ((priv == RW) && (user == RW))          { ap = 0x3; }\n    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }\n    else if ((priv == READ) && (user == READ))      { ap = 0x7; }\n  }\n\n  *descriptor_l1 &= SECTION_AP_MASK;\n  *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;\n  *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;\n\n  return 0;\n}\n\n/** \\brief  Set section shareability\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]             s_bit  Section shareability: NON_SHARED, SHARED\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)\n{\n  *descriptor_l1 &= SECTION_S_MASK;\n  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set section Global attribute\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)\n{\n  *descriptor_l1 &= SECTION_NG_MASK;\n  *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set section Security attribute\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)\n{\n  *descriptor_l1 &= SECTION_NS_MASK;\n  *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);\n  return 0;\n}\n\n/* Page 4k or 64k */\n/** \\brief  Set 4k/64k page execution-never attribute\n\n  \\param [out]    descriptor_l2  L2 descriptor.\n  \\param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.\n  \\param [in]              page  Page size: PAGE_4k, PAGE_64k,\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)\n{\n  if (page == PAGE_4k)\n  {\n      *descriptor_l2 &= PAGE_XN_4K_MASK;\n      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);\n  }\n  else\n  {\n      *descriptor_l2 &= PAGE_XN_64K_MASK;\n      *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);\n  }\n  return 0;\n}\n\n/** \\brief  Set 4k/64k page domain\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]            domain  Page domain\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)\n{\n  *descriptor_l1 &= PAGE_DOMAIN_MASK;\n  *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set 4k/64k page parity check\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)\n{\n  *descriptor_l1 &= SECTION_P_MASK;\n  *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set 4k/64k page access privileges\n\n  \\param [out]    descriptor_l2  L2 descriptor.\n  \\param [in]              user  User Level Access: NO_ACCESS, RW, READ\n  \\param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ\n  \\param [in]               afe  Access flag enable\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)\n{\n  uint32_t ap = 0;\n\n  if (afe == 0) { //full access\n    if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }\n    else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }\n    else if ((priv == RW) && (user == READ))        { ap = 0x2; }\n    else if ((priv == RW) && (user == RW))          { ap = 0x3; }\n    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }\n    else if ((priv == READ) && (user == READ))      { ap = 0x6; }\n  }\n\n  else { //Simplified access\n    if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }\n    else if ((priv == RW) && (user == RW))          { ap = 0x3; }\n    else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }\n    else if ((priv == READ) && (user == READ))      { ap = 0x7; }\n  }\n\n  *descriptor_l2 &= PAGE_AP_MASK;\n  *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;\n  *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;\n\n  return 0;\n}\n\n/** \\brief  Set 4k/64k page shareability\n\n  \\param [out]    descriptor_l2  L2 descriptor.\n  \\param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)\n{\n  *descriptor_l2 &= PAGE_S_MASK;\n  *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set 4k/64k page Global attribute\n\n  \\param [out]    descriptor_l2  L2 descriptor.\n  \\param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)\n{\n  *descriptor_l2 &= PAGE_NG_MASK;\n  *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set 4k/64k page Security attribute\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)\n{\n  *descriptor_l1 &= PAGE_NS_MASK;\n  *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);\n  return 0;\n}\n\n/** \\brief  Set Section memory attributes\n\n  \\param [out]    descriptor_l1  L1 descriptor.\n  \\param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED\n  \\param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,\n  \\param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)\n{\n  *descriptor_l1 &= SECTION_TEXCB_MASK;\n\n  if (STRONGLY_ORDERED == mem)\n  {\n    return 0;\n  }\n  else if (SHARED_DEVICE == mem)\n  {\n    *descriptor_l1 |= (1 << SECTION_B_SHIFT);\n  }\n  else if (NON_SHARED_DEVICE == mem)\n  {\n    *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);\n  }\n  else if (NORMAL == mem)\n  {\n   *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;\n   switch(inner)\n   {\n      case NON_CACHEABLE:\n        break;\n      case WB_WA:\n        *descriptor_l1 |= (1 << SECTION_B_SHIFT);\n        break;\n      case WT:\n        *descriptor_l1 |= 1 << SECTION_C_SHIFT;\n        break;\n      case WB_NO_WA:\n        *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);\n        break;\n    }\n    switch(outer)\n    {\n      case NON_CACHEABLE:\n        break;\n      case WB_WA:\n        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);\n        break;\n      case WT:\n        *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;\n        break;\n      case WB_NO_WA:\n        *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);\n        break;\n    }\n  }\n  return 0;\n}\n\n/** \\brief  Set 4k/64k page memory attributes\n\n  \\param [out]    descriptor_l2  L2 descriptor.\n  \\param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED\n  \\param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,\n  \\param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,\n  \\param [in]              page  Page size\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)\n{\n  *descriptor_l2 &= PAGE_4K_TEXCB_MASK;\n\n  if (page == PAGE_64k)\n  {\n    //same as section\n    MMU_MemorySection(descriptor_l2, mem, outer, inner);\n  }\n  else\n  {\n    if (STRONGLY_ORDERED == mem)\n    {\n      return 0;\n    }\n    else if (SHARED_DEVICE == mem)\n    {\n      *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);\n    }\n    else if (NON_SHARED_DEVICE == mem)\n    {\n      *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);\n    }\n    else if (NORMAL == mem)\n    {\n      *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;\n      switch(inner)\n      {\n        case NON_CACHEABLE:\n          break;\n        case WB_WA:\n          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);\n          break;\n        case WT:\n          *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;\n          break;\n        case WB_NO_WA:\n          *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);\n          break;\n      }\n      switch(outer)\n      {\n        case NON_CACHEABLE:\n          break;\n        case WB_WA:\n          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);\n          break;\n        case WT:\n          *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;\n          break;\n        case WB_NO_WA:\n          *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);\n          break;\n      }\n    }\n  }\n\n  return 0;\n}\n\n/** \\brief  Create a L1 section descriptor\n\n  \\param [out]     descriptor  L1 descriptor\n  \\param [in]      reg  Section attributes\n  \n  \\return          0\n*/\n__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)\n{\n  *descriptor  = 0;\n\n  MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);\n  MMU_XNSection(descriptor,reg.xn_t);\n  MMU_DomainSection(descriptor, reg.domain);\n  MMU_PSection(descriptor, reg.e_t);\n  MMU_APSection(descriptor, reg.user_t, reg.priv_t, 1);\n  MMU_SharedSection(descriptor,reg.sh_t);\n  MMU_GlobalSection(descriptor,reg.g_t);\n  MMU_SecureSection(descriptor,reg.sec_t);\n  *descriptor &= SECTION_MASK;\n  *descriptor |= SECTION_DESCRIPTOR;\n \n  return 0;\n}\n\n\n/** \\brief  Create a L1 and L2 4k/64k page descriptor\n\n  \\param [out]       descriptor  L1 descriptor\n  \\param [out]      descriptor2  L2 descriptor\n  \\param [in]               reg  4k/64k page attributes\n\n  \\return          0\n*/\n__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)\n{\n  *descriptor  = 0;\n  *descriptor2 = 0;\n\n  switch (reg.rg_t)\n  {\n    case PAGE_4k:\n      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);\n      MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);\n      MMU_DomainPage(descriptor, reg.domain);\n      MMU_PPage(descriptor, reg.e_t);\n      MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1);\n      MMU_SharedPage(descriptor2,reg.sh_t);\n      MMU_GlobalPage(descriptor2,reg.g_t);\n      MMU_SecurePage(descriptor,reg.sec_t);\n      *descriptor &= PAGE_L1_MASK;\n      *descriptor |= PAGE_L1_DESCRIPTOR;\n      *descriptor2 &= PAGE_L2_4K_MASK;\n      *descriptor2 |= PAGE_L2_4K_DESC;\n      break;\n\n    case PAGE_64k:\n      MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);\n      MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);\n      MMU_DomainPage(descriptor, reg.domain);\n      MMU_PPage(descriptor, reg.e_t);\n      MMU_APPage(descriptor2, reg.user_t, reg.priv_t, 1);\n      MMU_SharedPage(descriptor2,reg.sh_t);\n      MMU_GlobalPage(descriptor2,reg.g_t);\n      MMU_SecurePage(descriptor,reg.sec_t);\n      *descriptor &= PAGE_L1_MASK;\n      *descriptor |= PAGE_L1_DESCRIPTOR;\n      *descriptor2 &= PAGE_L2_64K_MASK;\n      *descriptor2 |= PAGE_L2_64K_DESC;\n      break;\n\n    case SECTION:\n      //error\n      break;\n  }\n  \n  return 0;\n}\n\n/** \\brief  Create a 1MB Section\n\n  \\param [in]               ttb  Translation table base address\n  \\param [in]      base_address  Section base address\n  \\param [in]             count  Number of sections to create\n  \\param [in]     descriptor_l1  L1 descriptor (region attributes)\n\n*/\n__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)\n{\n  uint32_t offset;\n  uint32_t entry;\n  uint32_t i;\n\n  offset = base_address >> 20;\n  entry  = (base_address & 0xFFF00000) | descriptor_l1;\n\n  //4 bytes aligned\n  ttb = ttb + offset;\n\n  for (i = 0; i < count; i++ )\n  {\n    //4 bytes aligned\n    *ttb++ = entry;\n    entry += OFFSET_1M;\n  }\n}\n\n/** \\brief  Create a 4k page entry\n\n  \\param [in]               ttb  L1 table base address\n  \\param [in]      base_address  4k base address\n  \\param [in]             count  Number of 4k pages to create\n  \\param [in]     descriptor_l1  L1 descriptor (region attributes)\n  \\param [in]            ttb_l2  L2 table base address\n  \\param [in]     descriptor_l2  L2 descriptor (region attributes)\n\n*/\n__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )\n{\n\n  uint32_t offset, offset2;\n  uint32_t entry, entry2;\n  uint32_t i;\n\n  offset = base_address >> 20;\n  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;\n\n  //4 bytes aligned\n  ttb += offset;\n  //create l1_entry\n  *ttb = entry;\n\n  offset2 = (base_address & 0xff000) >> 12;\n  ttb_l2 += offset2;\n  entry2 = (base_address & 0xFFFFF000) | descriptor_l2;\n  for (i = 0; i < count; i++ )\n  {\n    //4 bytes aligned\n    *ttb_l2++ = entry2;\n    entry2 += OFFSET_4K;\n  }\n}\n\n/** \\brief  Create a 64k page entry\n\n  \\param [in]               ttb  L1 table base address\n  \\param [in]      base_address  64k base address\n  \\param [in]             count  Number of 64k pages to create\n  \\param [in]     descriptor_l1  L1 descriptor (region attributes)\n  \\param [in]            ttb_l2  L2 table base address\n  \\param [in]     descriptor_l2  L2 descriptor (region attributes)\n\n*/\n__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )\n{\n  uint32_t offset, offset2;\n  uint32_t entry, entry2;\n  uint32_t i,j;\n\n\n  offset = base_address >> 20;\n  entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;\n\n  //4 bytes aligned\n  ttb += offset;\n  //create l1_entry\n  *ttb = entry;\n\n  offset2 = (base_address & 0xff000) >> 12;\n  ttb_l2 += offset2;\n  entry2 = (base_address & 0xFFFF0000) | descriptor_l2;\n  for (i = 0; i < count; i++ )\n  {\n    //create 16 entries\n    for (j = 0; j < 16; j++)\n    {\n      //4 bytes aligned\n      *ttb_l2++ = entry2;\n    }\n    entry2 += OFFSET_64K;\n  }\n}\n\n/** \\brief  Enable MMU\n*/\n__STATIC_INLINE void MMU_Enable(void)\n{\n  // Set M bit 0 to enable the MMU\n  // Set AFE bit to enable simplified access permissions model\n  // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking\n  __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));\n  __ISB();\n}\n\n/** \\brief  Disable MMU\n*/\n__STATIC_INLINE void MMU_Disable(void)\n{\n  // Clear M bit 0 to disable the MMU\n  __set_SCTLR( __get_SCTLR() & ~1);\n  __ISB();\n}\n\n/** \\brief  Invalidate entire unified TLB\n*/\n\n__STATIC_INLINE void MMU_InvalidateTLB(void)\n{\n  __set_TLBIALL(0);\n  __DSB();     //ensure completion of the invalidation\n  __ISB();     //ensure instruction fetch path sees new state\n}\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CA_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core_A/Include/irq_ctrl.h",
    "content": "/**************************************************************************//**\n * @file     irq_ctrl.h\n * @brief    Interrupt Controller API header file\n * @version  V1.1.0\n * @date     03. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef IRQ_CTRL_H_\n#define IRQ_CTRL_H_\n\n#include <stdint.h>\n\n#ifndef IRQHANDLER_T\n#define IRQHANDLER_T\n/// Interrupt handler data type\ntypedef void (*IRQHandler_t) (void);\n#endif\n\n#ifndef IRQN_ID_T\n#define IRQN_ID_T\n/// Interrupt ID number data type\ntypedef int32_t IRQn_ID_t;\n#endif\n\n/* Interrupt mode bit-masks */\n#define IRQ_MODE_TRIG_Pos           (0U)\n#define IRQ_MODE_TRIG_Msk           (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)\n#define IRQ_MODE_TRIG_LEVEL         (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt\n#define IRQ_MODE_TRIG_LEVEL_LOW     (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt\n#define IRQ_MODE_TRIG_LEVEL_HIGH    (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt\n#define IRQ_MODE_TRIG_EDGE          (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt\n#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt\n#define IRQ_MODE_TRIG_EDGE_FALLING  (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt\n#define IRQ_MODE_TRIG_EDGE_BOTH     (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt\n\n#define IRQ_MODE_TYPE_Pos           (3U)\n#define IRQ_MODE_TYPE_Msk           (0x01UL << IRQ_MODE_TYPE_Pos)\n#define IRQ_MODE_TYPE_IRQ           (0x00UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU IRQ line\n#define IRQ_MODE_TYPE_FIQ           (0x01UL << IRQ_MODE_TYPE_Pos)     ///< Type: interrupt source triggers CPU FIQ line\n\n#define IRQ_MODE_DOMAIN_Pos         (4U)\n#define IRQ_MODE_DOMAIN_Msk         (0x01UL << IRQ_MODE_DOMAIN_Pos)\n#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting non-secure domain\n#define IRQ_MODE_DOMAIN_SECURE      (0x01UL << IRQ_MODE_DOMAIN_Pos)   ///< Domain: interrupt is targeting secure domain\n\n#define IRQ_MODE_CPU_Pos            (5U)\n#define IRQ_MODE_CPU_Msk            (0xFFUL << IRQ_MODE_CPU_Pos)\n#define IRQ_MODE_CPU_ALL            (0x00UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets all CPUs\n#define IRQ_MODE_CPU_0              (0x01UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 0\n#define IRQ_MODE_CPU_1              (0x02UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 1\n#define IRQ_MODE_CPU_2              (0x04UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 2\n#define IRQ_MODE_CPU_3              (0x08UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 3\n#define IRQ_MODE_CPU_4              (0x10UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 4\n#define IRQ_MODE_CPU_5              (0x20UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 5\n#define IRQ_MODE_CPU_6              (0x40UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 6\n#define IRQ_MODE_CPU_7              (0x80UL << IRQ_MODE_CPU_Pos)      ///< CPU: interrupt targets CPU 7\n\n// Encoding in some early GIC implementations\n#define IRQ_MODE_MODEL_Pos          (13U)\n#define IRQ_MODE_MODEL_Msk          (0x1UL << IRQ_MODE_MODEL_Pos)\n#define IRQ_MODE_MODEL_NN           (0x0UL << IRQ_MODE_MODEL_Pos)     ///< Corresponding interrupt is handled using the N-N model\n#define IRQ_MODE_MODEL_1N           (0x1UL << IRQ_MODE_MODEL_Pos)     ///< Corresponding interrupt is handled using the 1-N model\n\n#define IRQ_MODE_ERROR              (0x80000000UL)                    ///< Bit indicating mode value error\n\n/* Interrupt priority bit-masks */\n#define IRQ_PRIORITY_Msk            (0x0000FFFFUL)                    ///< Interrupt priority value bit-mask\n#define IRQ_PRIORITY_ERROR          (0x80000000UL)                    ///< Bit indicating priority value error\n\n/// Initialize interrupt controller.\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_Initialize (void);\n\n/// Register interrupt handler.\n/// \\param[in]     irqn          interrupt ID number\n/// \\param[in]     handler       interrupt handler function address\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);\n\n/// Get the registered interrupt handler.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return registered interrupt handler function address.\nIRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);\n\n/// Enable interrupt.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_Enable (IRQn_ID_t irqn);\n\n/// Disable interrupt.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_Disable (IRQn_ID_t irqn);\n\n/// Get interrupt enable state.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return 0 - interrupt is disabled, 1 - interrupt is enabled.\nuint32_t IRQ_GetEnableState (IRQn_ID_t irqn);\n\n/// Configure interrupt request mode.\n/// \\param[in]     irqn          interrupt ID number\n/// \\param[in]     mode          mode configuration\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);\n\n/// Get interrupt mode configuration.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.\nuint32_t IRQ_GetMode (IRQn_ID_t irqn);\n\n/// Get ID number of current interrupt request (IRQ).\n/// \\return interrupt ID number.\nIRQn_ID_t IRQ_GetActiveIRQ (void);\n\n/// Get ID number of current fast interrupt request (FIQ).\n/// \\return interrupt ID number.\nIRQn_ID_t IRQ_GetActiveFIQ (void);\n\n/// Signal end of interrupt processing.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);\n\n/// Set interrupt pending flag.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_SetPending (IRQn_ID_t irqn);\n\n/// Get interrupt pending flag.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return 0 - interrupt is not pending, 1 - interrupt is pending.\nuint32_t IRQ_GetPending (IRQn_ID_t irqn);\n\n/// Clear interrupt pending flag.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_ClearPending (IRQn_ID_t irqn);\n\n/// Set interrupt priority value.\n/// \\param[in]     irqn          interrupt ID number\n/// \\param[in]     priority      interrupt priority value\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);\n\n/// Get interrupt priority.\n/// \\param[in]     irqn          interrupt ID number\n/// \\return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.\nuint32_t IRQ_GetPriority (IRQn_ID_t irqn);\n\n/// Set priority masking threshold.\n/// \\param[in]     priority      priority masking threshold value\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_SetPriorityMask (uint32_t priority);\n\n/// Get priority masking threshold\n/// \\return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.\nuint32_t IRQ_GetPriorityMask (void);\n\n/// Set priority grouping field split point\n/// \\param[in]     bits          number of MSB bits included in the group priority field comparison\n/// \\return 0 on success, -1 on error.\nint32_t IRQ_SetPriorityGroupBits (uint32_t bits);\n\n/// Get priority grouping field split point\n/// \\return current number of MSB bits included in the group priority field comparison with\n///         optional IRQ_PRIORITY_ERROR bit set.\nuint32_t IRQ_GetPriorityGroupBits (void);\n\n#endif  // IRQ_CTRL_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Core_A/Source/irq_ctrl_gic.c",
    "content": "/**************************************************************************//**\n * @file     irq_ctrl_gic.c\n * @brief    Interrupt controller handling implementation for GIC\n * @version  V1.2.0\n * @date     30. October 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2022 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <stddef.h>\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n#include \"irq_ctrl.h\"\n\n#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)\n\n/// Number of implemented interrupt lines\n#ifndef IRQ_GIC_LINE_COUNT\n#define IRQ_GIC_LINE_COUNT      (1020U)\n#endif\n\n#ifndef IRQ_GIC_EXTERN_IRQ_TABLE\nstatic IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };\n#else\nextern IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT];\n#endif\nstatic uint32_t     IRQ_ID0;\n\n/// Initialize interrupt controller.\n__WEAK int32_t IRQ_Initialize (void) {\n  #ifndef IRQ_GIC_EXTERN_IRQ_TABLE\n    uint32_t i;\n\n    for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {\n      IRQTable[i] = (IRQHandler_t)NULL;\n    }\n    GIC_Enable();\n  #endif\n  return (0);\n}\n\n\n/// Register interrupt handler.\n__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {\n  int32_t status;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    IRQTable[irqn] = handler;\n    status =  0;\n  } else {\n    status = -1;\n  }\n\n  return (status);\n}\n\n/// The Interrupt Handler.\n__WEAK void IRQ_Handler (void) {\n  IRQn_Type irqn = GIC_AcknowledgePending ();\n  if (irqn < (IRQn_Type)IRQ_GIC_LINE_COUNT) {\n    IRQTable[irqn]();\n  }\n  GIC_EndInterrupt (irqn);\n}\n\n\n/// Get the registered interrupt handler.\n__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {\n  IRQHandler_t h;\n\n  // Ignore CPUID field (software generated interrupts)\n  irqn &= 0x3FFU;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    h = IRQTable[irqn];\n  } else {\n    h = (IRQHandler_t)0;\n  }\n\n  return (h);\n}\n\n\n/// Enable interrupt.\n__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {\n  int32_t status;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    GIC_EnableIRQ ((IRQn_Type)irqn);\n    status = 0;\n  } else {\n    status = -1;\n  }\n\n  return (status);\n}\n\n\n/// Disable interrupt.\n__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {\n  int32_t status;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    GIC_DisableIRQ ((IRQn_Type)irqn);\n    status = 0;\n  } else {\n    status = -1;\n  }\n\n  return (status);\n}\n\n\n/// Get interrupt enable state.\n__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {\n  uint32_t enable;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    enable = GIC_GetEnableIRQ((IRQn_Type)irqn);\n  } else {\n    enable = 0U;\n  }\n\n  return (enable);\n}\n\n\n/// Configure interrupt request mode.\n__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {\n  uint32_t val;\n  uint8_t cfg;\n  uint8_t secure;\n  uint8_t cpu;\n  int32_t status = 0;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    // Check triggering mode\n    val = (mode & IRQ_MODE_TRIG_Msk);\n\n    if (val == IRQ_MODE_TRIG_LEVEL) {\n      cfg = 0x00U;\n    } else if (val == IRQ_MODE_TRIG_EDGE) {\n      cfg = 0x02U;\n    } else {\n      cfg = 0x00U;\n      status = -1;\n    }\n\n    val = (mode & IRQ_MODE_MODEL_Msk);\n    if (val == IRQ_MODE_MODEL_1N) {\n      cfg |= 1;   // 1-N model\n    }\n\n    // Check interrupt type\n    val = mode & IRQ_MODE_TYPE_Msk;\n\n    if (val != IRQ_MODE_TYPE_IRQ) {\n      status = -1;\n    }\n\n    // Check interrupt domain\n    val = mode & IRQ_MODE_DOMAIN_Msk;\n\n    if (val == IRQ_MODE_DOMAIN_NONSECURE) {\n      secure = 0U;\n    } else {\n      // Check security extensions support\n      val = GIC_DistributorInfo() & (1UL << 10U);\n\n      if (val != 0U) {\n        // Security extensions are supported\n        secure = 1U;\n      } else {\n        secure = 0U;\n        status = -1;\n      }\n    }\n\n    // Check interrupt CPU targets\n    val = mode & IRQ_MODE_CPU_Msk;\n\n    if (val == IRQ_MODE_CPU_ALL) {\n      cpu = 0xFFU;\n    } else {\n      cpu = (uint8_t)(val >> IRQ_MODE_CPU_Pos);\n    }\n\n    // Apply configuration if no mode error\n    if (status == 0) {\n      GIC_SetConfiguration((IRQn_Type)irqn, cfg);\n      GIC_SetTarget       ((IRQn_Type)irqn, cpu);\n\n      if (secure != 0U) {\n        GIC_SetGroup ((IRQn_Type)irqn, secure);\n      }\n    }\n  }\n\n  return (status);\n}\n\n\n/// Get interrupt mode configuration.\n__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {\n  uint32_t mode;\n  uint32_t val;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    mode = IRQ_MODE_TYPE_IRQ;\n\n    // Get trigger mode\n    val = GIC_GetConfiguration((IRQn_Type)irqn);\n\n    if ((val & 2U) != 0U) {\n      // Corresponding interrupt is edge triggered\n      mode |= IRQ_MODE_TRIG_EDGE;\n    } else {\n      // Corresponding interrupt is level triggered\n      mode |= IRQ_MODE_TRIG_LEVEL;\n    }\n\n    if (val & 1U) {\n      mode |= IRQ_MODE_MODEL_1N;\n    }\n    // Get interrupt CPU targets\n    mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;\n\n  } else {\n    mode = IRQ_MODE_ERROR;\n  }\n\n  return (mode);\n}\n\n\n/// Get ID number of current interrupt request (IRQ).\n__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {\n  IRQn_ID_t irqn;\n  uint32_t prio;\n\n  /* Dummy read to avoid GIC 390 errata 801120 */\n  GIC_GetHighPendingIRQ();\n\n  irqn = GIC_AcknowledgePending();\n\n  __DSB();\n\n  /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014)  */\n  /* The following workaround code is for a single-core system.  It would be       */\n  /* different in a multi-core system.                                             */\n  /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */\n  /* so unlock it, otherwise service the interrupt as normal.                      */\n  /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2  */\n  /* so will not occur here.                                                       */\n\n  if ((irqn == 0) || (irqn >= 0x3FE)) {\n    /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */\n    prio = GIC_GetPriority((IRQn_Type)0);\n    GIC_SetPriority ((IRQn_Type)0, prio);\n\n    __DSB();\n\n    if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {\n      /* If the ID is 0, is active and has not been seen before */\n      IRQ_ID0 = 1U;\n    }\n    /* End of Workaround GIC 390 errata 733075 */\n  }\n\n  return (irqn);\n}\n\n\n/// Get ID number of current fast interrupt request (FIQ).\n__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {\n  return ((IRQn_ID_t)-1);\n}\n\n\n/// Signal end of interrupt processing.\n__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {\n  int32_t status;\n  IRQn_Type irq = (IRQn_Type)irqn;\n\n  irqn &= 0x3FFU;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    GIC_EndInterrupt (irq);\n\n    if (irqn == 0) {\n      IRQ_ID0 = 0U;\n    }\n\n    status = 0;\n  } else {\n    status = -1;\n  }\n\n  return (status);\n}\n\n\n/// Set interrupt pending flag.\n__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {\n  int32_t status;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    GIC_SetPendingIRQ ((IRQn_Type)irqn);\n    status = 0;\n  } else {\n    status = -1;\n  }\n\n  return (status);\n}\n\n/// Get interrupt pending flag.\n__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {\n  uint32_t pending;\n\n  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);\n  } else {\n    pending = 0U;\n  }\n\n  return (pending & 1U);\n}\n\n\n/// Clear interrupt pending flag.\n__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {\n  int32_t status;\n\n  if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    GIC_ClearPendingIRQ ((IRQn_Type)irqn);\n    status = 0;\n  } else {\n    status = -1;\n  }\n\n  return (status);\n}\n\n\n/// Set interrupt priority value.\n__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {\n  int32_t status;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    GIC_SetPriority ((IRQn_Type)irqn, priority);\n    status = 0;\n  } else {\n    status = -1;\n  }\n\n  return (status);\n}\n\n\n/// Get interrupt priority.\n__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {\n  uint32_t priority;\n\n  if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {\n    priority = GIC_GetPriority ((IRQn_Type)irqn);\n  } else {\n    priority = IRQ_PRIORITY_ERROR;\n  }\n\n  return (priority);\n}\n\n\n/// Set priority masking threshold.\n__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {\n  GIC_SetInterfacePriorityMask (priority);\n  return (0);\n}\n\n\n/// Get priority masking threshold\n__WEAK uint32_t IRQ_GetPriorityMask (void) {\n  return GIC_GetInterfacePriorityMask();\n}\n\n\n/// Set priority grouping field split point\n__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {\n  int32_t status;\n\n  if (bits == IRQ_PRIORITY_Msk) {\n    bits = 7U;\n  }\n\n  if (bits < 8U) {\n    GIC_SetBinaryPoint (7U - bits);\n    status = 0;\n  } else {\n    status = -1;\n  }\n\n  return (status);\n}\n\n\n/// Get priority grouping field split point\n__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {\n  uint32_t bp;\n\n  bp = GIC_GetBinaryPoint() & 0x07U;\n\n  return (7U - bp);\n}\n\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DSP/README.md",
    "content": "# CMSIS-DSP\n\n![GitHub release (latest by date including pre-releases)](https://img.shields.io/github/v/release/ARM-software/CMSIS-DSP?include_prereleases) ![GitHub](https://img.shields.io/github/license/ARM-software/CMSIS-DSP)\n\nThis CMSIS component has been moved into its own realm, please find it at [ARM-software/CMSIS-DSP](https://github.com/ARM-software/CMSIS-DSP).\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/CmdLineBuild.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/CmdLineBuild.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/CmdLineBuild.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/build_revisionHistory.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/build_revisionHistory.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/build_revisionHistory.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cbuild.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cbuild.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cbuild.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cbuild_install.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cbuild_install.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cbuild_install.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cbuild_uv.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=index.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"index.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cbuildgen.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cbuildgen.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cbuildgen.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/ccmerge.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=index.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"index.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cmake.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cmake.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cmake.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cmsis.css",
    "content": "/* The standard CSS for doxygen */\n\nbody, table, div, p, dl {\n\tfont-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\n\tfont-size: 13px;\n\tline-height: 1.3;\n}\n\n/* CMSIS styles */\n\n.style1 {\n\t\ttext-align: center;\n}\n.style2 {\n\t\tcolor: #0000FF;\n\t\tfont-weight: normal;\n}\n.style3 {\n\t\ttext-align: left;\n}\n.style4 {\n\t\tcolor: #008000;\n}\n.style5 {\n\t\tcolor: #0000FF;\n}\n.style6 {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n.mand {\n\t\tcolor: #0000FF;\n}\n.opt {\n\t\tcolor: #008000;\n}\n.cond {\n\t\tcolor: #990000;\n}\n\n.choice \n{\n\tbackground-color:#F7F9D0;\n}\n.seq \n{\n\tbackground-color:#C9DECB;\n}\n.group1\n{\n\tbackground-color:#F8F1F1;\n}\n.group2\n{\n\tbackground-color:#DCEDEA;\n}\n\n\nul ul {\n\t\tlist-style-type: disc;\n}\n\nul ul ul {\n\t\tlist-style-type: disc;\n}\n\nul.hierarchy {\n\t\tcolor: green;\n}\n\nem {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n\n\n\n/*  CMSIS Tables */\ntable.cmtab1 {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: justify;\n\twidth:70%;\n}\n\nth.cmtab1 {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n\theight: 28px;\n}\n\ntd.cmtab1 {\n\tpadding:1px;\n\ttext-align: left;\n}\n\ntable.cmtable {\n\tborder-collapse:collapse;\n\ttext-align: justify;\n}\n\ntable.cmtable td, table.cmtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.cmtable th {\n\tbackground-color: #EBEFF6;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n\ttext-align:left;\n}\n\ntd.MonoTxt {\n\tfont-family:\"Arial monospaced for SAP\";\n}\n\ntd.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.h2 \n{\n\tfont-size: 120%;\n\tfont-weight: bold;\n}\n\ndiv.new\n{\n\tbackground-color:#ccffcc; /* light green */\n}\n\ndiv.mod\n{\n\tbackground-color:#ffe6cc;  /* light amber */\n}\n\ndiv.del\n{\n\tbackground-color:#ffcccc;  /* light red */\n}\n\n/* @group Heading Levels */\n\nh1 {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2 {\n\tfont-size: 120%;\n}\n\nh3 {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3A568E;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4464A5;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9AAED5;\n\tcolor: #ffffff;\n\tborder: 1px double #849CCC;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3A568E;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #293C63;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2B4069;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #EBEFF6;\n\tcolor: #000000;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        width: 100%;\n        margin-bottom: 10px;\n        border: 1px solid #A7B8DA;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A7B8DA;\n        border-bottom: 1px solid #A7B8DA;\n        vertical-align: top;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A7B8DA;\n        width: 100%;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        font-size: 90%;\n        color: #233456;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A7B8DA;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tmargin-left: 5px;\n\tfont-size: 8pt;\n\tpadding-left: 5px;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C3CFE6;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 7px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5072B7;\n}\n\n.image\n{\n        text-align: left;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #8EA4D0;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#314877;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D7DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4464A5;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cmsis_footer.js",
    "content": "function writeFooter()  {\n    document.write('Generated on Wed Apr 13 2022 14:13:49 for CMSIS-Pack Version 1.7.2 by Arm Ltd. All rights reserved.');\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cp_init.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=index.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"index.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cp_install.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cpackget.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cpackget.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cprjFormat_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cprjFormat_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cprjFormat_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/cprj_types.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cprj_types.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/cprj_types.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/doxygen.css",
    "content": "/* The standard CSS for doxygen 1.8.6 */\n\nbody, table, div, p, dl {\n\tfont: 400 14px/22px Roboto,sans-serif;\n}\n\n/* @group Heading Levels */\n\nh1.groupheader {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont: 400 14px/28px Roboto,sans-serif;\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2.groupheader {\n\tborder-bottom: 1px solid #879ECB;\n\tcolor: #354C7B;\n\tfont-size: 150%;\n\tfont-weight: normal;\n\tmargin-top: 1.75em;\n\tpadding-top: 8px;\n\tpadding-bottom: 4px;\n\twidth: 100%;\n}\n\nh3.groupheader {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd {\n\tmargin-top: 2px;\n}\n\np.starttd {\n\tmargin-top: 0px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3D578C;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4665A2;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9CAFD4;\n\tcolor: #ffffff;\n\tborder: 1px double #869DCA;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited, a.line, a.line:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C4CFE5;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tmin-height: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\ndiv.line.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 10px cyan;\n}\n\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C4CFE5;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C4CFE5;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EEF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9CAFD4;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4A6AAA;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td, .fieldtable tr {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow, .fieldtable tr.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memSeparator {\n        border-bottom: 1px solid #DEE4F0;\n        line-height: 1px;\n        margin: 0px;\n        padding: 0px;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4665A2;\n        white-space: nowrap;\n\tfont-size: 80%;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4665A2;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n        display: table !important;\n        width: 100%;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A8B8D9;\n        border-left: 1px solid #A8B8D9;\n        border-right: 1px solid #A8B8D9;\n        padding: 6px 0px 6px 0px;\n        color: #253555;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E8F2;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A8B8D9;      \n        border-left: 1px solid #A8B8D9;      \n        border-right: 1px solid #A8B8D9; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n.paramname code {\n        line-height: 14px;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #728DC1;\n        border-top:1px solid #5373B4;\n        border-left:1px solid #5373B4;\n        border-right:1px solid #C4CFE5;\n        border-bottom:1px solid #C4CFE5;\n\ttext-shadow: none;\n\tcolor: white;\n\tmargin-right: 4px;\n\tpadding: 2px 3px;\n\tborder-radius: 3px;\n\tfont-size: 7pt;\n\twhite-space: nowrap;\n\tvertical-align: middle;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n\tpadding-top: 3px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.entry a img {\n        border: none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tpadding-top: 3px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3D578C;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #2A3D61;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #374F7F;\n\tcolor: #FFFFFF;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        /*width: 100%;*/\n        margin-bottom: 10px;\n        border: 1px solid #A8B8D9;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        vertical-align: top;\n}\n\n.fieldtable td.fieldname {\n        padding-top: 3px;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A8B8D9;\n        /*width: 100%;*/\n}\n\n.fieldtable td.fielddoc p:first-child {\n        margin-top: 0px;\n}       \n        \n.fieldtable td.fielddoc p:last-child {\n        margin-bottom: 2px;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E8F2;\n        font-size: 90%;\n        color: #253555;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A8B8D9;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\tbackground-position: 0 -5px;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#8AA0CC;\n\tborder:solid 1px #C2CDE4;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#364D7C;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n\tcolor: #283A5D;\n\tfont-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;\n\ttext-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n\ttext-decoration: none;        \n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6884BD;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#364D7C;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tfont-size: 8pt;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C4CFE5;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 10px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5373B4;\n}\n\n.image\n{\n        text-align: center;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.diagraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #90A5CE;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#334975;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D8DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4665A2;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n/* tooltip related style info */\n\n.ttc {\n        position: absolute;\n        display: none;\n}\n\n#powerTip {\n\tcursor: default;\n\twhite-space: nowrap;\n\tbackground-color: white;\n\tborder: 1px solid gray;\n\tborder-radius: 4px 4px 4px 4px;\n\tbox-shadow: 1px 1px 7px gray;\n\tdisplay: none;\n\tfont-size: smaller;\n\tmax-width: 80%;\n\topacity: 0.9;\n\tpadding: 1ex 1em 1em;\n\tposition: absolute;\n\tz-index: 2147483647;\n}\n\n#powerTip div.ttdoc {\n        color: grey;\n\tfont-style: italic;\n}\n\n#powerTip div.ttname a {\n        font-weight: bold;\n}\n\n#powerTip div.ttname {\n        font-weight: bold;\n}\n\n#powerTip div.ttdeci {\n        color: #006318;\n}\n\n#powerTip div {\n        margin: 0px;\n        padding: 0px;\n        font: 12px/16px Roboto,sans-serif;\n}\n\n#powerTip:before, #powerTip:after {\n\tcontent: \"\";\n\tposition: absolute;\n\tmargin: 0px;\n}\n\n#powerTip.n:after,  #powerTip.n:before,\n#powerTip.s:after,  #powerTip.s:before,\n#powerTip.w:after,  #powerTip.w:before,\n#powerTip.e:after,  #powerTip.e:before,\n#powerTip.ne:after, #powerTip.ne:before,\n#powerTip.se:after, #powerTip.se:before,\n#powerTip.nw:after, #powerTip.nw:before,\n#powerTip.sw:after, #powerTip.sw:before {\n\tborder: solid transparent;\n\tcontent: \" \";\n\theight: 0;\n\twidth: 0;\n\tposition: absolute;\n}\n\n#powerTip.n:after,  #powerTip.s:after,\n#powerTip.w:after,  #powerTip.e:after,\n#powerTip.nw:after, #powerTip.ne:after,\n#powerTip.sw:after, #powerTip.se:after {\n\tborder-color: rgba(255, 255, 255, 0);\n}\n\n#powerTip.n:before,  #powerTip.s:before,\n#powerTip.w:before,  #powerTip.e:before,\n#powerTip.nw:before, #powerTip.ne:before,\n#powerTip.sw:before, #powerTip.se:before {\n\tborder-color: rgba(128, 128, 128, 0);\n}\n\n#powerTip.n:after,  #powerTip.n:before,\n#powerTip.ne:after, #powerTip.ne:before,\n#powerTip.nw:after, #powerTip.nw:before {\n\ttop: 100%;\n}\n\n#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after {\n\tborder-top-color: #ffffff;\n\tborder-width: 10px;\n\tmargin: 0px -10px;\n}\n#powerTip.n:before {\n\tborder-top-color: #808080;\n\tborder-width: 11px;\n\tmargin: 0px -11px;\n}\n#powerTip.n:after, #powerTip.n:before {\n\tleft: 50%;\n}\n\n#powerTip.nw:after, #powerTip.nw:before {\n\tright: 14px;\n}\n\n#powerTip.ne:after, #powerTip.ne:before {\n\tleft: 14px;\n}\n\n#powerTip.s:after,  #powerTip.s:before,\n#powerTip.se:after, #powerTip.se:before,\n#powerTip.sw:after, #powerTip.sw:before {\n\tbottom: 100%;\n}\n\n#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after {\n\tborder-bottom-color: #ffffff;\n\tborder-width: 10px;\n\tmargin: 0px -10px;\n}\n\n#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before {\n\tborder-bottom-color: #808080;\n\tborder-width: 11px;\n\tmargin: 0px -11px;\n}\n\n#powerTip.s:after, #powerTip.s:before {\n\tleft: 50%;\n}\n\n#powerTip.sw:after, #powerTip.sw:before {\n\tright: 14px;\n}\n\n#powerTip.se:after, #powerTip.se:before {\n\tleft: 14px;\n}\n\n#powerTip.e:after, #powerTip.e:before {\n\tleft: 100%;\n}\n#powerTip.e:after {\n\tborder-left-color: #ffffff;\n\tborder-width: 10px;\n\ttop: 50%;\n\tmargin-top: -10px;\n}\n#powerTip.e:before {\n\tborder-left-color: #808080;\n\tborder-width: 11px;\n\ttop: 50%;\n\tmargin-top: -11px;\n}\n\n#powerTip.w:after, #powerTip.w:before {\n\tright: 100%;\n}\n#powerTip.w:after {\n\tborder-right-color: #ffffff;\n\tborder-width: 10px;\n\ttop: 50%;\n\tmargin-top: -10px;\n}\n#powerTip.w:before {\n\tborder-right-color: #808080;\n\tborder-width: 11px;\n\ttop: 50%;\n\tmargin-top: -11px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/dynsections.js",
    "content": "function toggleVisibility(linkObj)\n{\n var base = $(linkObj).attr('id');\n var summary = $('#'+base+'-summary');\n var content = $('#'+base+'-content');\n var trigger = $('#'+base+'-trigger');\n var src=$(trigger).attr('src');\n if (content.is(':visible')===true) {\n   content.hide();\n   summary.show();\n   $(linkObj).addClass('closed').removeClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');\n } else {\n   content.show();\n   summary.hide();\n   $(linkObj).removeClass('closed').addClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');\n } \n return false;\n}\n\nfunction updateStripes()\n{\n  $('table.directory tr').\n       removeClass('even').filter(':visible:even').addClass('even');\n}\nfunction toggleLevel(level)\n{\n  $('table.directory tr').each(function(){ \n    var l = this.id.split('_').length-1;\n    var i = $('#img'+this.id.substring(3));\n    var a = $('#arr'+this.id.substring(3));\n    if (l<level+1) {\n      i.attr('src','ftv2folderopen.png');\n      a.attr('src','ftv2mnode.png');\n      $(this).show();\n    } else if (l==level+1) {\n      i.attr('src','ftv2folderclosed.png');\n      a.attr('src','ftv2pnode.png');\n      $(this).show();\n    } else {\n      $(this).hide();\n    }\n  });\n  updateStripes();\n}\n\nfunction toggleFolder(id)\n{\n  //The clicked row\n  var currentRow = $('#row_'+id);\n  var currentRowImages = currentRow.find(\"img\");\n\n  //All rows after the clicked row\n  var rows = currentRow.nextAll(\"tr\");\n\n  //Only match elements AFTER this one (can't hide elements before)\n  var childRows = rows.filter(function() {\n    var re = new RegExp('^row_'+id+'\\\\d+_$', \"i\"); //only one sub\n    return this.id.match(re);\n  });\n\n  //First row is visible we are HIDING\n  if (childRows.filter(':first').is(':visible')===true) {\n    currentRowImages.filter(\"[id^=arr]\").attr('src', 'ftv2pnode.png');\n    currentRowImages.filter(\"[id^=img]\").attr('src', 'ftv2folderclosed.png');\n    rows.filter(\"[id^=row_\"+id+\"]\").hide();\n  } else { //We are SHOWING\n    //All sub images\n    var childImages = childRows.find(\"img\");\n    var childImg = childImages.filter(\"[id^=img]\");\n    var childArr = childImages.filter(\"[id^=arr]\");\n\n    currentRow.find(\"[id^=arr]\").attr('src', 'ftv2mnode.png'); //open row\n    currentRow.find(\"[id^=img]\").attr('src', 'ftv2folderopen.png'); //open row\n    childImg.attr('src','ftv2folderclosed.png'); //children closed\n    childArr.attr('src','ftv2pnode.png'); //children closed\n    childRows.show(); //show all children\n  }\n  updateStripes();\n}\n\n\nfunction toggleInherit(id)\n{\n  var rows = $('tr.inherit.'+id);\n  var img = $('tr.inherit_header.'+id+' img');\n  var src = $(img).attr('src');\n  if (rows.filter(':first').is(':visible')===true) {\n    rows.css('display','none');\n    $(img).attr('src',src.substring(0,src.length-8)+'closed.png');\n  } else {\n    rows.css('display','table-row'); // using show() causes jump in firefox\n    $(img).attr('src',src.substring(0,src.length-10)+'open.png');\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_compilers.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_compilers.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_compilers.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_components.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_components.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_components.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_cprj.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_cprj.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_cprj.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_created.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_created.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_created.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_files.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_files.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_files.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_info.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_info.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_info.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_layers.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_layers.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_layers.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_packages.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_packages.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_packages.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/element_target.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_target.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/element_target.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/index.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<meta http-equiv=\"Content-Type\" content=\"text/xhtml;charset=UTF-8\"/>\n<meta http-equiv=\"X-UA-Compatible\" content=\"IE=9\"/>\n<title>Overview</title>\n<title>CMSIS-Build: Overview</title>\n<link href=\"tabs.css\" rel=\"stylesheet\" type=\"text/css\"/>\n<link href=\"cmsis.css\" rel=\"stylesheet\" type=\"text/css\" />\n<script type=\"text/javascript\" src=\"jquery.js\"></script>\n<script type=\"text/javascript\" src=\"dynsections.js\"></script>\n<script type=\"text/javascript\" src=\"printComponentTabs.js\"></script>\n<script type=\"text/javascript\" src=\"cmsis_footer.js\"></script>\n<link href=\"navtree.css\" rel=\"stylesheet\" type=\"text/css\"/>\n<script type=\"text/javascript\" src=\"resize.js\"></script>\n<script type=\"text/javascript\" src=\"navtree.js\"></script>\n<script type=\"text/javascript\">\n  $(document).ready(initResizable);\n  $(window).load(resizeHeight);\n</script>\n<link href=\"search/search.css\" rel=\"stylesheet\" type=\"text/css\"/>\n<script type=\"text/javascript\" src=\"search/search.js\"></script>\n<script type=\"text/javascript\">\n  $(document).ready(function() { searchBox.OnSelectItem(0); });\n</script>\n</head>\n<body>\n<div id=\"top\"><!-- do not remove this div, it is closed by doxygen! -->\n<div id=\"titlearea\">\n<table cellspacing=\"0\" cellpadding=\"0\">\n <tbody>\n <tr style=\"height: 46px;\">\n  <td id=\"projectlogo\"><img alt=\"Logo\" src=\"CMSIS_Logo_Final.png\"/></td>\n  <td style=\"padding-left: 0.5em;\">\n   <div id=\"projectname\">CMSIS-Build\n   &#160;<span id=\"projectnumber\">Version 0.10.0 (beta)</span>\n   </div>\n   <div id=\"projectbrief\">Tools, software frameworks, and work flows for productivity with CMSIS based projects</div>\n  </td>\n </tr>\n </tbody>\n</table>\n</div>\n<!-- end header part -->\n<div id=\"CMSISnav\" class=\"tabs1\">\n    <ul class=\"tablist\">\n      <script type=\"text/javascript\">\n\t\t<!--\n\t\twriteComponentTabs.call(this);\n\t\t//-->\n      </script>\n\t  </ul>\n</div>\n<!-- Generated by Doxygen 1.8.6 -->\n<script type=\"text/javascript\">\nvar searchBox = new SearchBox(\"searchBox\", \"search\",false,'Search');\n</script>\n  <div id=\"navrow1\" class=\"tabs\">\n    <ul class=\"tablist\">\n      <li class=\"current\"><a href=\"index.html\"><span>Main&#160;Page</span></a></li>\n      <li><a href=\"pages.html\"><span>Usage&#160;and&#160;Description</span></a></li>\n      <li>\n        <div id=\"MSearchBox\" class=\"MSearchBoxInactive\">\n        <span class=\"left\">\n          <img id=\"MSearchSelect\" src=\"search/mag_sel.png\"\n               onmouseover=\"return searchBox.OnSearchSelectShow()\"\n               onmouseout=\"return searchBox.OnSearchSelectHide()\"\n               alt=\"\"/>\n          <input type=\"text\" id=\"MSearchField\" value=\"Search\" accesskey=\"S\"\n               onfocus=\"searchBox.OnSearchFieldFocus(true)\" \n               onblur=\"searchBox.OnSearchFieldFocus(false)\" \n               onkeyup=\"searchBox.OnSearchFieldChange(event)\"/>\n          </span><span class=\"right\">\n            <a id=\"MSearchClose\" href=\"javascript:searchBox.CloseResultsWindow()\"><img id=\"MSearchCloseImg\" border=\"0\" src=\"search/close.png\" alt=\"\"/></a>\n          </span>\n        </div>\n      </li>\n    </ul>\n  </div>\n</div><!-- top -->\n<div id=\"side-nav\" class=\"ui-resizable side-nav-resizable\">\n  <div id=\"nav-tree\">\n    <div id=\"nav-tree-contents\">\n      <div id=\"nav-sync\" class=\"sync\"></div>\n    </div>\n  </div>\n  <div id=\"splitbar\" style=\"-moz-user-select:none;\" \n       class=\"ui-resizable-handle\">\n  </div>\n</div>\n<script type=\"text/javascript\">\n$(document).ready(function(){initNavTree('index.html','');});\n</script>\n<div id=\"doc-content\">\n<!-- window showing the filter options -->\n<div id=\"MSearchSelectWindow\"\n     onmouseover=\"return searchBox.OnSearchSelectShow()\"\n     onmouseout=\"return searchBox.OnSearchSelectHide()\"\n     onkeydown=\"return searchBox.OnSearchSelectKey(event)\">\n<a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(0)\"><span class=\"SelectionMark\">&#160;</span>All</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(1)\"><span class=\"SelectionMark\">&#160;</span>Pages</a></div>\n\n<!-- iframe showing the search results (closed by default) -->\n<div id=\"MSearchResultsWindow\">\n<iframe src=\"javascript:void(0)\" frameborder=\"0\" \n        name=\"MSearchResults\" id=\"MSearchResults\">\n</iframe>\n</div>\n\n<div class=\"header\">\n  <div class=\"headertitle\">\n<div class=\"title\">Overview </div>  </div>\n</div><!--header-->\n<div class=\"contents\">\n<div class=\"textblock\"><p>CMSIS-Build is now replaced with the <a href=\"https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools\" target=\"_blank\"><b>CMSIS-Toolbox</b></a> that is a set of tools for creating and building projects that are based on software packs.</p>\n\nContent of this documentation is now <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/index.html\" target=\"_blank\"><b>provided here</b></a> and individual pages are redirected to the corresponding pages in CMSIS-Toolbox documents.\n\n<h1><a class=\"anchor\" id=\"Components_of_CMSIS_Toolbox\"></a>\nComponents of CMSIS-Toolbox</h1>\n<p>The <a href=\"https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools\" target=\"_blank\"><b>CMSIS-Toolbox</b></a> is developed under the <a href=\"https://www.open-cmsis-pack.org\" target=\"_blank\">Linaro Open-CMSIS-Pack</a> project and contains these tools:</p>\n<ul>\n<li><b>cpackget</b> download, add and remove software packs.</li>\n<li><b>csolution</b> to create and manage complex applications with user source files and content from software packs</li>\n<li><b>cbuild</b> controls the build process that translates a project to a executable binary image.</li>\n<li><b>packgen</b> to create a software pack from a CMake based software repository.</li>\n<li><b>packchk</b> to validate a software pack</li>\n</ul>\n<p>The <a href=\"https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools\" target=\"_blank\"><b>CMSIS-Toolbox</b></a> can be used as stand-alone tools with command line interface (CLI) but will be integrated into several other Arm tool solutions such as:</p>\n<ul>\n<li><a href=\"https://www.arm.com/virtual-hardware\" target=\"_blank\"><b>Arm Virtual Hardware</b></a> to manage the build process in CI workflows.</li>\n<li><a href=\"https://www.keil.arm.com\" target=\"_blank\"><b>Keil Studio</b></a> as integral part of the project management.</li>\n<li><a href=\"https://www.keil.com/mdk5/\" target=\"_blank\"><b>Keil MDK</b></a> to provide CLI tools for project generation.</li>\n</ul>\n<h1><a class=\"anchor\" id=\"Development_Workflow\"></a>\nDevelopment Workflow</h1>\n<p>The following diagram shows the development workflow using the CMSIS-Toolbox.</p>\n<div class=\"image\">\n<img src=\"CMSIS-Toolbox.png\" alt=\"CMSIS-Toolbox.png\"/>\n<div class=\"caption\">\nDiagram: CMSIS-Toolbox Development Workflow</div></div>\n<p> A solution that manages several related projects and projects can be composed using an intuitive <code>*.yml</code> format. This solution and project files are then translated using <b>csolution</b> CLI tool to the <code>*.CPRJ</code> project file format.</p>\n<p>The individual <code>*.CPRJ</code> project files can be imported to an IDE or by using <b>cbuild</b> translated into executable binary images.</p>\n<p>The <a class=\"el\" href=\"cprjFormat_pg.html\" target=\"_blank\">*.CPRJ Project Format</a> describes the input file format that is used by <b>cbuild</b>.</p>\n<h1><a class=\"anchor\" id=\"Revision_History\"></a>\nRevision History</h1>\n<table class=\"doxtable\">\n<tr>\n<th align=\"left\">Version </th><th align=\"left\">Description  </th></tr>\n<tr>\n<td align=\"left\">replaced by </td><td align=\"left\"><a href=\"https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools\" target=\"_blank\"><b>CMSIS-Toolbox</b></a> now contains the <b>cbuild</b> (aka CMSIS-Build) CLI tool. </td></tr>\n<tr>\n<td align=\"left\">0.10.0 (beta) </td><td align=\"left\">CMake back-end and support for more Cortex-M processors including ArmV8.1M architecture. </td></tr>\n<tr>\n<td align=\"left\">0.9.0 (beta) </td><td align=\"left\">Support for multiple compilers and commands for layer management </td></tr>\n<tr>\n<td align=\"left\">0.1.0 (alpha) </td><td align=\"left\">Release for alpha review </td></tr>\n</table>\n</div></div><!-- contents -->\n</div><!-- doc-content -->\n<!-- start footer part -->\n<div id=\"nav-path\" class=\"navpath\"><!-- id is needed for treeview function! -->\n  <ul>\n    <li class=\"footer\">\n      <script type=\"text/javascript\">\n        <!--\n        writeFooter.call(this);\n        //-->\n      </script>    \n    </li>\n  </ul>\n</div>\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/jquery.js",
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this.bind((a.support.selectstart?\"selectstart\":\"mousedown\")+\".ui-disableSelection\",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(\".ui-disableSelection\")}});a.each([\"Width\",\"Height\"],function(g,e){var f=e===\"Width\"?[\"Left\",\"Right\"]:[\"Top\",\"Bottom\"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,\"padding\"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,\"border\"+this+\"Width\",true))||0}if(n){l-=parseFloat(a.curCSS(m,\"margin\"+this,true))||0}});return l}a.fn[\"inner\"+e]=function(i){if(i===d){return k[\"inner\"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+\"px\")})};a.fn[\"outer\"+e]=function(i,l){if(typeof i!==\"number\"){return k[\"outer\"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+\"px\")})}});function c(g,e){var j=g.nodeName.toLowerCase();if(\"area\"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!==\"map\"){return false}f=a(\"img[usemap=#\"+h+\"]\")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:\"a\"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,\"visibility\")===\"hidden\"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[\":\"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,\"tabindex\")))},tabbable:function(g){var e=a.attr(g,\"tabindex\"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement(\"div\"));f.offsetHeight;a.extend(f.style,{minHeight:\"100px\",height:\"auto\",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart=\"onselectstart\" in f;e.removeChild(f).style.display=\"none\"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h<j.length;h++){if(e.options[j[h][0]]){j[h][1].apply(e.element,f)}}}},contains:function(f,e){return document.compareDocumentPosition?f.compareDocumentPosition(e)&16:f!==e&&f.contains(e)},hasScroll:function(h,f){if(a(h).css(\"overflow\")===\"hidden\"){return false}var e=(f&&f===\"left\")?\"scrollLeft\":\"scrollTop\",g=false;if(h[e]>0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*!\n * jQuery UI Widget 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Widget\n */\n(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler(\"remove\")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b(\"*\",this).add([this]).each(function(){try{b(this).triggerHandler(\"remove\")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(\".\")[0],j;f=f.split(\".\")[1];j=g+\"-\"+f;if(!e){e=h;h=b.Widget}b.expr[\":\"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i===\"string\",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)===\"_\"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:\"widget\",widgetEventPrefix:\"\",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind(\"remove.\"+this.widgetName,function(){e.destroy()});this._create();this._trigger(\"create\");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind(\".\"+this.widgetName).removeData(this.widgetName);this.widget().unbind(\".\"+this.widgetName).removeAttr(\"aria-disabled\").removeClass(this.widgetBaseClass+\"-disabled ui-state-disabled\")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f===\"string\"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e===\"disabled\"){this.widget()[f?\"addClass\":\"removeClass\"](this.widgetBaseClass+\"-disabled ui-state-disabled\").attr(\"aria-disabled\",f)}return this},enable:function(){return this._setOption(\"disabled\",false)},disable:function(){return this._setOption(\"disabled\",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!\n * jQuery UI Mouse 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Mouse\n *\n * Depends:\n *\tjquery.ui.widget.js\n */\n(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget(\"ui.mouse\",{options:{cancel:\":input,option\",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind(\"mousedown.\"+this.widgetName,function(e){return d._mouseDown(e)}).bind(\"click.\"+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+\".preventClickEvent\")){b.removeData(e.target,d.widgetName+\".preventClickEvent\");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind(\".\"+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel==\"string\"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+\".preventClickEvent\")){b.removeData(f.target,this.widgetName+\".preventClickEvent\")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).bind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).unbind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+\".preventClickEvent\",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget(\"ui.resizable\",c.ui.mouse,{widgetEventPrefix:\"resize\",options:{alsoResize:false,animate:false,animateDuration:\"slow\",animateEasing:\"swing\",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:\"e,s,se\",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass(\"ui-resizable\");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||\"ui-resizable-helper\":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class=\"ui-wrapper\" style=\"overflow: hidden;\"></div>').css({position:this.element.css(\"position\"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css(\"top\"),left:this.element.css(\"left\")}));this.element=this.element.parent().data(\"resizable\",this.element.data(\"resizable\"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css(\"marginLeft\"),marginTop:this.originalElement.css(\"marginTop\"),marginRight:this.originalElement.css(\"marginRight\"),marginBottom:this.originalElement.css(\"marginBottom\")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css(\"resize\");this.originalElement.css(\"resize\",\"none\");this._proportionallyResizeElements.push(this.originalElement.css({position:\"static\",zoom:1,display:\"block\"}));this.originalElement.css({margin:this.originalElement.css(\"margin\")});this._proportionallyResize()}this.handles=k.handles||(!c(\".ui-resizable-handle\",this.element).length?\"e,s,se\":{n:\".ui-resizable-n\",e:\".ui-resizable-e\",s:\".ui-resizable-s\",w:\".ui-resizable-w\",se:\".ui-resizable-se\",sw:\".ui-resizable-sw\",ne:\".ui-resizable-ne\",nw:\".ui-resizable-nw\"});if(this.handles.constructor==String){if(this.handles==\"all\"){this.handles=\"n,e,s,w,se,sw,ne,nw\"}var l=this.handles.split(\",\");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e=\"ui-resizable-\"+j;var h=c('<div class=\"ui-resizable-handle '+e+'\"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if(\"se\"==j){h.addClass(\"ui-icon ui-icon-gripsmall-diagonal-se\")}this.handles[j]=\".ui-resizable-\"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=[\"padding\",/ne|nw|n/.test(n)?\"Top\":/se|sw|s/.test(n)?\"Bottom\":/^e$/.test(n)?\"Right\":\"Left\"].join(\"\");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(\".ui-resizable-handle\",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:\"se\"}});if(k.autoHide){this._handles.hide();c(this.element).addClass(\"ui-resizable-autohide\").hover(function(){if(k.disabled){return}c(this).removeClass(\"ui-resizable-autohide\");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass(\"ui-resizable-autohide\");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass(\"ui-resizable ui-resizable-disabled ui-resizable-resizing\").removeData(\"resizable\").unbind(\".resizable\").find(\".ui-resizable-handle\").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css(\"position\"),width:f.outerWidth(),height:f.outerHeight(),top:f.css(\"top\"),left:f.css(\"left\")})).remove()}this.originalElement.css(\"resize\",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(\".ui-draggable\")||(/absolute/).test(e.css(\"position\"))){e.css({position:\"absolute\",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css(\"left\")),h=b(this.helper.css(\"top\"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio==\"number\")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(\".ui-resizable-\"+this.axis).css(\"cursor\");c(\"body\").css(\"cursor\",i==\"auto\"?this.axis+\"-resize\":i);e.addClass(\"ui-resizable-resizing\");this._propagate(\"start\",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate(\"resize\",e);h.css({top:this.position.top+\"px\",left:this.position.left+\"px\",width:this.size.width+\"px\",height:this.size.height+\"px\"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger(\"resize\",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],\"left\")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css(\"left\"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css(\"top\"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c(\"body\").css(\"cursor\",\"auto\");this.element.removeClass(\"ui-resizable-resizing\");this._propagate(\"stop\",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(h<e.maxWidth){e.maxWidth=h}if(k<e.maxHeight){e.maxHeight=k}}this._vBoundaries=e},_updateCache:function(e){var f=this.options;this.offset=this.helper.offset();if(a(e.left)){this.position.left=e.left}if(a(e.top)){this.position.top=e.top}if(a(e.height)){this.size.height=e.height}if(a(e.width)){this.size.width=e.width}},_updateRatio:function(h,g){var i=this.options,j=this.position,f=this.size,e=this.axis;if(a(h.height)){h.width=(h.height*this.aspectRatio)}else{if(a(h.width)){h.height=(h.width/this.aspectRatio)}}if(e==\"sw\"){h.left=j.left+(f.width-h.width);h.top=null}if(e==\"nw\"){h.top=j.top+(f.height-h.height);h.left=j.left+(f.width-h.width)}return h},_respectSize:function(l,g){var j=this.helper,i=this._vBoundaries,r=this._aspectRatio||g.shiftKey,q=this.axis,t=a(l.width)&&i.maxWidth&&(i.maxWidth<l.width),m=a(l.height)&&i.maxHeight&&(i.maxHeight<l.height),h=a(l.width)&&i.minWidth&&(i.minWidth>l.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f<this._proportionallyResizeElements.length;f++){var h=this._proportionallyResizeElements[f];if(!this.borderDif){var e=[h.css(\"borderTopWidth\"),h.css(\"borderRightWidth\"),h.css(\"borderBottomWidth\"),h.css(\"borderLeftWidth\")],j=[h.css(\"paddingTop\"),h.css(\"paddingRight\"),h.css(\"paddingBottom\"),h.css(\"paddingLeft\")];this.borderDif=c.map(e,function(l,n){var m=parseInt(l,10)||0,o=parseInt(j[n],10)||0;return m+o})}if(c.browser.msie&&!(!(c(g).is(\":hidden\")||c(g).parents(\":hidden\").length))){continue}h.css({height:(g.height()-this.borderDif[0]-this.borderDif[2])||0,width:(g.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var f=this.element,i=this.options;this.elementOffset=f.offset();if(this._helper){this.helper=this.helper||c('<div style=\"overflow:hidden;\"></div>');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:\"absolute\",left:this.elementOffset.left-g+\"px\",top:this.elementOffset.top-g+\"px\",zIndex:++i.zIndex});this.helper.appendTo(\"body\").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!=\"resize\"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:\"1.8.18\"});c.ui.plugin.add(\"resizable\",\"alsoResize\",{start:function(f,g){var e=c(this).data(\"resizable\"),i=e.options;var h=function(j){c(j).each(function(){var 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  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/make.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=index.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"index.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/navtree.css",
    "content": "#nav-tree .children_ul {\n  margin:0;\n  padding:4px;\n}\n\n#nav-tree ul {\n  list-style:none outside none;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree li {\n  white-space:nowrap;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .plus {\n  margin:0px;\n}\n\n#nav-tree .selected {\n  background-image: url('tab_a.png');\n  background-repeat:repeat-x;\n  color: #fff;\n  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n\n#nav-tree img {\n  margin:0px;\n  padding:0px;\n  border:0px;\n  vertical-align: middle;\n}\n\n#nav-tree a {\n  text-decoration:none;\n  padding:0px;\n  margin:0px;\n  outline:none;\n}\n\n#nav-tree .label {\n  margin:0px;\n  padding:0px;\n  font: 12px 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;\n}\n\n#nav-tree .label a {\n  padding:2px;\n}\n\n#nav-tree .selected a {\n  text-decoration:none;\n  color:#fff;\n}\n\n#nav-tree .children_ul {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .item {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree {\n  padding: 0px 0px;\n  background-color: #FAFAFF; \n  font-size:14px;\n  overflow:auto;\n}\n\n#doc-content {\n  overflow:auto;\n  display:block;\n  padding:0px;\n  margin:0px;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#side-nav {\n  padding:0 6px 0 0;\n  margin: 0px;\n  display:block;\n  position: absolute;\n  left: 0px;\n  width: 250px;\n}\n\n.ui-resizable .ui-resizable-handle {\n  display:block;\n}\n\n.ui-resizable-e {\n  background:url(\"ftv2splitbar.png\") repeat scroll right center transparent;\n  cursor:e-resize;\n  height:100%;\n  right:0;\n  top:0;\n  width:6px;\n}\n\n.ui-resizable-handle {\n  display:none;\n  font-size:0.1px;\n  position:absolute;\n  z-index:1;\n}\n\n#nav-tree-contents {\n  margin: 6px 0px 0px 0px;\n}\n\n#nav-tree {\n  background-image:url('nav_h.png');\n  background-repeat:repeat-x;\n  background-color: #F9FAFC;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#nav-sync {\n  position:absolute;\n  top:5px;\n  right:24px;\n  z-index:0;\n}\n\n#nav-sync img {\n  opacity:0.3;\n}\n\n#nav-sync img:hover {\n  opacity:0.9;\n}\n\n@media print\n{\n  #nav-tree { display: none; }\n  div.ui-resizable-handle { display: none; position: relative; }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/navtree.js",
    "content": "var NAVTREE =\n[\n  [ \"CMSIS-Build\", \"index.html\"]\n];\n\nvar NAVTREEINDEX =\n[\n\"CmdLineBuild.html\"\n];\n\nvar SYNCONMSG = 'click to disable panel synchronisation';\nvar SYNCOFFMSG = 'click to enable panel synchronisation';\nvar SYNCONMSG = 'click to disable panel synchronisation';\nvar SYNCOFFMSG = 'click to enable panel synchronisation';\nvar navTreeSubIndices = new Array();\n\nfunction getData(varName)\n{\n  var i = varName.lastIndexOf('/');\n  var n = i>=0 ? varName.substring(i+1) : varName;\n  return eval(n.replace(/\\-/g,'_'));\n}\n\nfunction stripPath(uri)\n{\n  return uri.substring(uri.lastIndexOf('/')+1);\n}\n\nfunction stripPath2(uri)\n{\n  var i = uri.lastIndexOf('/');\n  var s = uri.substring(i+1);\n  var m = uri.substring(0,i+1).match(/\\/d\\w\\/d\\w\\w\\/$/);\n  return m ? uri.substring(i-6) : s;\n}\n\nfunction localStorageSupported()\n{\n  try {\n    return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem;\n  }\n  catch(e) {\n    return false;\n  }\n}\n\n\nfunction storeLink(link)\n{\n  if (!$(\"#nav-sync\").hasClass('sync') && localStorageSupported()) {\n      window.localStorage.setItem('navpath',link);\n  }\n}\n\nfunction deleteLink()\n{\n  if (localStorageSupported()) {\n    window.localStorage.setItem('navpath','');\n  } \n}\n\nfunction cachedLink()\n{\n  if (localStorageSupported()) {\n    return window.localStorage.getItem('navpath');\n  } else {\n    return '';\n  }\n}\n\nfunction getScript(scriptName,func,show)\n{\n  var head = document.getElementsByTagName(\"head\")[0]; \n  var script = document.createElement('script');\n  script.id = scriptName;\n  script.type = 'text/javascript';\n  script.onload = func; \n  script.src = scriptName+'.js'; \n  if ($.browser.msie && $.browser.version<=8) { \n    // script.onload does not work with older versions of IE\n    script.onreadystatechange = function() {\n      if (script.readyState=='complete' || script.readyState=='loaded') { \n        func(); if (show) showRoot(); \n      }\n    }\n  }\n  head.appendChild(script); \n}\n\nfunction createIndent(o,domNode,node,level)\n{\n  var level=-1;\n  var n = node;\n  while (n.parentNode) { level++; n=n.parentNode; }\n  if (node.childrenData) {\n    var imgNode = document.createElement(\"img\");\n    imgNode.style.paddingLeft=(16*level).toString()+'px';\n    imgNode.width  = 16;\n    imgNode.height = 22;\n    imgNode.border = 0;\n    node.plus_img = imgNode;\n    node.expandToggle = document.createElement(\"a\");\n    node.expandToggle.href = \"javascript:void(0)\";\n    node.expandToggle.onclick = function() {\n      if (node.expanded) {\n        $(node.getChildrenUL()).slideUp(\"fast\");\n        node.plus_img.src = node.relpath+\"ftv2pnode.png\";\n        node.expanded = false;\n      } else {\n        expandNode(o, node, false, false);\n      }\n    }\n    node.expandToggle.appendChild(imgNode);\n    domNode.appendChild(node.expandToggle);\n    imgNode.src = node.relpath+\"ftv2pnode.png\";\n  } else {\n    var span = document.createElement(\"span\");\n    span.style.display = 'inline-block';\n    span.style.width   = 16*(level+1)+'px';\n    span.style.height  = '22px';\n    span.innerHTML = '&#160;';\n    domNode.appendChild(span);\n  } \n}\n\nvar animationInProgress = false;\n\nfunction gotoAnchor(anchor,aname,updateLocation)\n{\n  var pos, docContent = $('#doc-content');\n  if (anchor.parent().attr('class')=='memItemLeft' ||\n      anchor.parent().attr('class')=='fieldtype' ||\n      anchor.parent().is(':header')) \n  {\n    pos = anchor.parent().position().top;\n  } else if (anchor.position()) {\n    pos = anchor.position().top;\n  }\n  if (pos) {\n    var dist = Math.abs(Math.min(\n               pos-docContent.offset().top,\n               docContent[0].scrollHeight-\n               docContent.height()-docContent.scrollTop()));\n    animationInProgress=true;\n    docContent.animate({\n      scrollTop: pos + docContent.scrollTop() - docContent.offset().top\n    },Math.max(50,Math.min(500,dist)),function(){\n      if (updateLocation) window.location.href=aname;\n      animationInProgress=false;\n    });\n  }\n}\n\nfunction newNode(o, po, text, link, childrenData, lastNode)\n{\n  var node = new Object();\n  node.children = Array();\n  node.childrenData = childrenData;\n  node.depth = po.depth + 1;\n  node.relpath = po.relpath;\n  node.isLast = lastNode;\n\n  node.li = document.createElement(\"li\");\n  po.getChildrenUL().appendChild(node.li);\n  node.parentNode = po;\n\n  node.itemDiv = document.createElement(\"div\");\n  node.itemDiv.className = \"item\";\n\n  node.labelSpan = document.createElement(\"span\");\n  node.labelSpan.className = \"label\";\n\n  createIndent(o,node.itemDiv,node,0);\n  node.itemDiv.appendChild(node.labelSpan);\n  node.li.appendChild(node.itemDiv);\n\n  var a = document.createElement(\"a\");\n  node.labelSpan.appendChild(a);\n  node.label = document.createTextNode(text);\n  node.expanded = false;\n  a.appendChild(node.label);\n  if (link) {\n    var url;\n    if (link.substring(0,1)=='^') {\n      url = link.substring(1);\n      link = url;\n    } else {\n      url = node.relpath+link;\n    }\n    a.className = stripPath(link.replace('#',':'));\n    if (link.indexOf('#')!=-1) {\n      var aname = '#'+link.split('#')[1];\n      var srcPage = stripPath($(location).attr('pathname'));\n      var targetPage = stripPath(link.split('#')[0]);\n      a.href = srcPage!=targetPage ? url : \"javascript:void(0)\"; \n      a.onclick = function(){\n        storeLink(link);\n        if (!$(a).parent().parent().hasClass('selected'))\n        {\n          $('.item').removeClass('selected');\n          $('.item').removeAttr('id');\n          $(a).parent().parent().addClass('selected');\n          $(a).parent().parent().attr('id','selected');\n        }\n        var anchor = $(aname);\n        gotoAnchor(anchor,aname,true);\n      };\n    } else {\n      a.href = url;\n      a.onclick = function() { storeLink(link); }\n    }\n  } else {\n    if (childrenData != null) \n    {\n      a.className = \"nolink\";\n      a.href = \"javascript:void(0)\";\n      a.onclick = node.expandToggle.onclick;\n    }\n  }\n\n  node.childrenUL = null;\n  node.getChildrenUL = function() {\n    if (!node.childrenUL) {\n      node.childrenUL = document.createElement(\"ul\");\n      node.childrenUL.className = \"children_ul\";\n      node.childrenUL.style.display = \"none\";\n      node.li.appendChild(node.childrenUL);\n    }\n    return node.childrenUL;\n  };\n\n  return node;\n}\n\nfunction showRoot()\n{\n  var headerHeight = $(\"#top\").height();\n  var footerHeight = $(\"#nav-path\").height();\n  var windowHeight = $(window).height() - headerHeight - footerHeight;\n  (function (){ // retry until we can scroll to the selected item\n    try {\n      var navtree=$('#nav-tree');\n      navtree.scrollTo('#selected',0,{offset:-windowHeight/2});\n    } catch (err) {\n      setTimeout(arguments.callee, 0);\n    }\n  })();\n}\n\nfunction expandNode(o, node, imm, showRoot)\n{\n  if (node.childrenData && !node.expanded) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        expandNode(o, node, imm, showRoot);\n      }, showRoot);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      } if (imm || ($.browser.msie && $.browser.version>8)) { \n        // somehow slideDown jumps to the start of tree for IE9 :-(\n        $(node.getChildrenUL()).show();\n      } else {\n        $(node.getChildrenUL()).slideDown(\"fast\");\n      }\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n    }\n  }\n}\n\nfunction glowEffect(n,duration)\n{\n  n.addClass('glow').delay(duration).queue(function(next){\n    $(this).removeClass('glow');next();\n  });\n}\n\nfunction highlightAnchor()\n{\n  var aname = $(location).attr('hash');\n  var anchor = $(aname);\n  if (anchor.parent().attr('class')=='memItemLeft'){\n    var rows = $('.memberdecls tr[class$=\"'+\n               window.location.hash.substring(1)+'\"]');\n    glowEffect(rows.children(),300); // member without details\n  } else if (anchor.parents().slice(2).prop('tagName')=='TR') {\n    glowEffect(anchor.parents('div.memitem'),1000); // enum value\n  } else if (anchor.parent().attr('class')=='fieldtype'){\n    glowEffect(anchor.parent().parent(),1000); // struct field\n  } else if (anchor.parent().is(\":header\")) {\n    glowEffect(anchor.parent(),1000); // section header\n  } else {\n    glowEffect(anchor.next(),1000); // normal member\n  }\n  gotoAnchor(anchor,aname,false);\n}\n\nfunction selectAndHighlight(hash,n)\n{\n  var a;\n  if (hash) {\n    var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1);\n    a=$('.item a[class$=\"'+link+'\"]');\n  }\n  if (a && a.length) {\n    a.parent().parent().addClass('selected');\n    a.parent().parent().attr('id','selected');\n    highlightAnchor();\n  } else if (n) {\n    $(n.itemDiv).addClass('selected');\n    $(n.itemDiv).attr('id','selected');\n  }\n  if ($('#nav-tree-contents .item:first').hasClass('selected')) {\n    $('#nav-sync').css('top','30px');\n  } else {\n    $('#nav-sync').css('top','5px');\n  }\n  showRoot();\n}\n\nfunction showNode(o, node, index, hash)\n{\n  if (node && node.childrenData) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        showNode(o,node,index,hash);\n      },true);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      }\n      $(node.getChildrenUL()).css({'display':'block'});\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n      var n = node.children[o.breadcrumbs[index]];\n      if (index+1<o.breadcrumbs.length) {\n        showNode(o,n,index+1,hash);\n      } else {\n        if (typeof(n.childrenData)==='string') {\n          var varName = n.childrenData;\n          getScript(n.relpath+varName,function(){\n            n.childrenData = getData(varName);\n            node.expanded=false;\n            showNode(o,node,index,hash); // retry with child node expanded\n          },true);\n        } else {\n          var rootBase = stripPath(o.toroot.replace(/\\..+$/, ''));\n          if (rootBase==\"index\" || rootBase==\"pages\" || rootBase==\"search\") {\n            expandNode(o, n, true, true);\n          }\n          selectAndHighlight(hash,n);\n        }\n      }\n    }\n  } else {\n    selectAndHighlight(hash);\n  }\n}\n\nfunction removeToInsertLater(element) {\n  var parentNode = element.parentNode;\n  var nextSibling = element.nextSibling;\n  parentNode.removeChild(element);\n  return function() {\n    if (nextSibling) {\n      parentNode.insertBefore(element, nextSibling);\n    } else {\n      parentNode.appendChild(element);\n    }\n  };\n}\n\nfunction getNode(o, po)\n{\n  var insertFunction = removeToInsertLater(po.li);\n  po.childrenVisited = true;\n  var l = po.childrenData.length-1;\n  for (var i in po.childrenData) {\n    var nodeData = po.childrenData[i];\n    po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],\n      i==l);\n  }\n  insertFunction();\n}\n\nfunction gotoNode(o,subIndex,root,hash,relpath)\n{\n  var nti = navTreeSubIndices[subIndex][root+hash];\n  o.breadcrumbs = $.extend(true, [], nti ? nti : navTreeSubIndices[subIndex][root]);\n  if (!o.breadcrumbs && root!=NAVTREE[0][1]) { // fallback: show index\n    navTo(o,NAVTREE[0][1],\"\",relpath);\n    $('.item').removeClass('selected');\n    $('.item').removeAttr('id');\n  }\n  if (o.breadcrumbs) {\n    o.breadcrumbs.unshift(0); // add 0 for root node\n    showNode(o, o.node, 0, hash);\n  }\n}\n\nfunction navTo(o,root,hash,relpath)\n{\n  var link = cachedLink();\n  if (link) {\n    var parts = link.split('#');\n    root = parts[0];\n    if (parts.length>1) hash = '#'+parts[1];\n    else hash='';\n  }\n  if (hash.match(/^#l\\d+$/)) {\n    var anchor=$('a[name='+hash.substring(1)+']');\n    glowEffect(anchor.parent(),1000); // line number\n    hash=''; // strip line number anchors\n    //root=root.replace(/_source\\./,'.'); // source link to doc link\n  }\n  var url=root+hash;\n  var i=-1;\n  while (NAVTREEINDEX[i+1]<=url) i++;\n  if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index\n  if (navTreeSubIndices[i]) {\n    gotoNode(o,i,root,hash,relpath)\n  } else {\n    getScript(relpath+'navtreeindex'+i,function(){\n      navTreeSubIndices[i] = eval('NAVTREEINDEX'+i);\n      if (navTreeSubIndices[i]) {\n        gotoNode(o,i,root,hash,relpath);\n      }\n    },true);\n  }\n}\n\nfunction showSyncOff(n,relpath)\n{\n    n.html('<img src=\"'+relpath+'sync_off.png\" title=\"'+SYNCOFFMSG+'\"/>');\n}\n\nfunction showSyncOn(n,relpath)\n{\n    n.html('<img src=\"'+relpath+'sync_on.png\" title=\"'+SYNCONMSG+'\"/>');\n}\n\nfunction toggleSyncButton(relpath)\n{\n  var navSync = $('#nav-sync');\n  if (navSync.hasClass('sync')) {\n    navSync.removeClass('sync');\n    showSyncOff(navSync,relpath);\n    storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash'));\n  } else {\n    navSync.addClass('sync');\n    showSyncOn(navSync,relpath);\n    deleteLink();\n  }\n}\n\nfunction initNavTree(toroot,relpath)\n{\n  var o = new Object();\n  o.toroot = toroot;\n  o.node = new Object();\n  o.node.li = document.getElementById(\"nav-tree-contents\");\n  o.node.childrenData = NAVTREE;\n  o.node.children = new Array();\n  o.node.childrenUL = document.createElement(\"ul\");\n  o.node.getChildrenUL = function() { return o.node.childrenUL; };\n  o.node.li.appendChild(o.node.childrenUL);\n  o.node.depth = 0;\n  o.node.relpath = relpath;\n  o.node.expanded = false;\n  o.node.isLast = true;\n  o.node.plus_img = document.createElement(\"img\");\n  o.node.plus_img.src = relpath+\"ftv2pnode.png\";\n  o.node.plus_img.width = 16;\n  o.node.plus_img.height = 22;\n\n  if (localStorageSupported()) {\n    var navSync = $('#nav-sync');\n    if (cachedLink()) {\n      showSyncOff(navSync,relpath);\n      navSync.removeClass('sync');\n    } else {\n      showSyncOn(navSync,relpath);\n    }\n    navSync.click(function(){ toggleSyncButton(relpath); });\n  }\n\n  $(window).load(function(){\n    navTo(o,toroot,window.location.hash,relpath);\n    showRoot();\n  });\n\n  $(window).bind('hashchange', function(){\n     if (window.location.hash && window.location.hash.length>1){\n       var a;\n       if ($(location).attr('hash')){\n         var clslink=stripPath($(location).attr('pathname'))+':'+\n                               $(location).attr('hash').substring(1);\n         a=$('.item a[class$=\"'+clslink+'\"]');\n       }\n       if (a==null || !$(a).parent().parent().hasClass('selected')){\n         $('.item').removeClass('selected');\n         $('.item').removeAttr('id');\n       }\n       var link=stripPath2($(location).attr('pathname'));\n       navTo(o,link,$(location).attr('hash'),relpath);\n     } else if (!animationInProgress) {\n       $('#doc-content').scrollTop(0);\n       $('.item').removeClass('selected');\n       $('.item').removeAttr('id');\n       navTo(o,toroot,window.location.hash,relpath);\n     }\n  })\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/navtreeindex0.js",
    "content": "var NAVTREEINDEX0 =\n{\n\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/pages.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/pages.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/pages.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/printComponentTabs.js",
    "content": "var strgURL =   location.pathname;                      // path of current component\n\n// constuctor for the array of objects\nfunction tabElement(id, folderName, tabTxt )  {\n\tthis.id = id;                                       // elementID as needed in html; \n\tthis.folderName = folderName;                       // folder name of the component \n    this.tabTxt = tabTxt;                               // Text displayed as menu on the web\n\tthis.currentListItem = '<li id=\"' + this.id + '\" class=\"current\"> <a href=\"../..' + this.folderName + 'index.html\"><span>' + this.tabTxt + '</span></a></li>';\n\tthis.listItem = '<li id=\"' + this.id + '\"> <a href=\"../..' + this.folderName + 'index.html\"><span>' + this.tabTxt + '</span></a></li>';\n};\n\n// array of objects\nvar arr = [];\n\n// fill array\n arr.push( new tabElement( \"GEN\",     \"/General/html/\",     \"General\")   );\n arr.push( new tabElement( \"CORE_A\",  \"/Core_A/html/\",      \"Core(A)\")   );\n arr.push( new tabElement( \"CORE_M\",  \"/Core/html/\",        \"Core(M)\")   );\n arr.push( new tabElement( \"DRV\",     \"/Driver/html/\",      \"Driver\")    );\n arr.push( new tabElement( \"DSP&ML\",  \"/DSP/html/\",         \"DSP\")       );\n arr.push( new tabElement( \"NN\",      \"/NN/html/\",          \"NN\")        );\n arr.push( new tabElement( \"RTOSv1\",  \"/RTOS/html/\",        \"RTOS v1\")   );\n arr.push( new tabElement( \"RTOSv2\",  \"/RTOS2/html/\",       \"RTOS v2\")   );\n arr.push( new tabElement( \"PACK\",    \"/Pack/html/\",        \"Pack\")      );\n arr.push( new tabElement( \"Build\",   \"/Build/html/\",       \"Build\")     );\n arr.push( new tabElement( \"SVD\",     \"/SVD/html/\",         \"SVD\")       );\n arr.push( new tabElement( \"DAP\",     \"/DAP/html/\",         \"DAP\")       );\n arr.push( new tabElement( \"ZONE\",    \"/Zone/html/\",        \"Zone\")      );\n \n// write tabs\n// called from the header file.\nfunction writeComponentTabs()  {\n  for ( var i=0; i < arr.length; i++ ) {\n    if (strgURL.search(arr[i].folderName) > 0) {                    // if this is the current folder\n      document.write(arr[i].currentListItem);                       // then print and hightlight the tab\n    } else {                                                      \n      document.write(arr[i].listItem);                              // else, print the tab\n    }                                                             \n  }\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/projectDescriptionSchema.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/devtools/buildmgr/latest/projectDescriptionSchema.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/devtools/buildmgr/latest/projectDescriptionSchema.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/resize.js",
    "content": "var cookie_namespace = 'doxygen'; \nvar sidenav,navtree,content,header;\n\nfunction readCookie(cookie) \n{\n  var myCookie = cookie_namespace+\"_\"+cookie+\"=\";\n  if (document.cookie) \n  {\n    var index = document.cookie.indexOf(myCookie);\n    if (index != -1) \n    {\n      var valStart = index + myCookie.length;\n      var valEnd = document.cookie.indexOf(\";\", valStart);\n      if (valEnd == -1) \n      {\n        valEnd = document.cookie.length;\n      }\n      var val = document.cookie.substring(valStart, valEnd);\n      return val;\n    }\n  }\n  return 0;\n}\n\nfunction writeCookie(cookie, val, expiration) \n{\n  if (val==undefined) return;\n  if (expiration == null) \n  {\n    var date = new Date();\n    date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week\n    expiration = date.toGMTString();\n  }\n  document.cookie = cookie_namespace + \"_\" + cookie + \"=\" + val + \"; expires=\" + expiration+\"; path=/\";\n}\n \nfunction resizeWidth() \n{\n  var windowWidth = $(window).width() + \"px\";\n  var sidenavWidth = $(sidenav).outerWidth();\n  content.css({marginLeft:parseInt(sidenavWidth)+\"px\"}); \n  writeCookie('width',sidenavWidth, null);\n}\n\nfunction restoreWidth(navWidth)\n{\n  var windowWidth = $(window).width() + \"px\";\n  content.css({marginLeft:parseInt(navWidth)+6+\"px\"});\n  sidenav.css({width:navWidth + \"px\"});\n}\n\nfunction resizeHeight() \n{\n  var headerHeight = header.outerHeight();\n  var footerHeight = footer.outerHeight();\n  var windowHeight = $(window).height() - headerHeight - footerHeight;\n  content.css({height:windowHeight + \"px\"});\n  navtree.css({height:windowHeight + \"px\"});\n  sidenav.css({height:windowHeight + \"px\",top: headerHeight+\"px\"});\n}\n\nfunction initResizable()\n{\n  header  = $(\"#top\");\n  sidenav = $(\"#side-nav\");\n  content = $(\"#doc-content\");\n  navtree = $(\"#nav-tree\");\n  footer  = $(\"#nav-path\");\n  $(\".side-nav-resizable\").resizable({resize: function(e, ui) { resizeWidth(); } });\n  $(window).resize(function() { resizeHeight(); });\n  var width = readCookie('width');\n  if (width) { restoreWidth(width); } else { resizeWidth(); }\n  resizeHeight();\n  var url = location.href;\n  var i=url.indexOf(\"#\");\n  if (i>=0) window.location.hash=url.substr(i);\n  var _preventDefault = function(evt) { evt.preventDefault(); };\n  $(\"#splitbar\").bind(\"dragstart\", _preventDefault).bind(\"selectstart\", _preventDefault);\n  $(document).bind('touchmove',function(e){\n    var device = navigator.userAgent.toLowerCase();\n    var ios = device.match(/(iphone|ipod|ipad)/);\n    if (ios) {\n      try {\n        var target = e.target;\n        while (target) {\n          if ($(target).css('-webkit-overflow-scrolling')=='touch') return;\n          target = target.parentNode;\n        }\n        e.preventDefault();\n      } catch(err) {\n        e.preventDefault();\n      }\n    }\n  });\n}\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/search/nomatches.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html><head><title></title>\n<meta http-equiv=\"Content-Type\" content=\"text/xhtml;charset=UTF-8\"/>\n<link rel=\"stylesheet\" type=\"text/css\" href=\"search.css\"/>\n<script type=\"text/javascript\" src=\"search.js\"></script>\n</head>\n<body class=\"SRPage\">\n<div id=\"SRIndex\">\n<div class=\"SRStatus\" id=\"NoMatches\">No Matches</div>\n</div>\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/search/search.css",
    "content": "/*---------------- Search Box */\n\n#FSearchBox {\n    float: left;\n}\n\n#searchli {\n    float: right;\n    display: block;\n    width: 170px;\n    height: 24px;\n}\n\n#MSearchBox {\n    white-space : nowrap;\n    position: absolute;\n    float: none;\n    display: inline;\n    margin-top: 3px;\n    right: 0px;\n    width: 170px;\n    z-index: 102;\n}\n\n#MSearchBox .left\n{\n    display:block;\n    position:absolute;\n    left:10px;\n    width:20px;\n    height:19px;\n    background:url('search_l.png') no-repeat;\n    background-position:right;\n}\n\n#MSearchSelect {\n    display:block;\n    position:absolute;\n    width:20px;\n    height:19px;\n}\n\n.left #MSearchSelect {\n    left:4px;\n}\n\n.right #MSearchSelect {\n    right:5px;\n}\n\n#MSearchField {\n    display:block;\n    position:absolute;\n    height:19px;\n    background:url('search_m.png') repeat-x;\n    border:none;\n    width:116px;\n    margin-left:20px;\n    padding-left:4px;\n    color: #909090;\n    outline: none;\n    font: 9pt Arial, Verdana, sans-serif;\n}\n\n#FSearchBox #MSearchField {\n    margin-left:15px;\n}\n\n#MSearchBox .right {\n    display:block;\n    position:absolute;\n    right:10px;\n    top:0px;\n    width:20px;\n    height:19px;\n    background:url('search_r.png') no-repeat;\n    background-position:left;\n}\n\n#MSearchClose {\n    display: none;\n    position: absolute;\n    top: 4px;\n    background : none;\n    border: none;\n    margin: 0px 4px 0px 0px;\n    padding: 0px 0px;\n    outline: none;\n}\n\n.left #MSearchClose {\n    left: 6px;\n}\n\n.right #MSearchClose {\n    right: 2px;\n}\n\n.MSearchBoxActive #MSearchField {\n    color: #000000;\n}\n\n/*---------------- Search filter selection */\n\n#MSearchSelectWindow {\n    display: none;\n    position: absolute;\n    left: 0; top: 0;\n    border: 1px solid #90A5CE;\n    background-color: #F9FAFC;\n    z-index: 1;\n    padding-top: 4px;\n    padding-bottom: 4px;\n    -moz-border-radius: 4px;\n    -webkit-border-top-left-radius: 4px;\n    -webkit-border-top-right-radius: 4px;\n    -webkit-border-bottom-left-radius: 4px;\n    -webkit-border-bottom-right-radius: 4px;\n    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\n.SelectItem {\n    font: 8pt Arial, Verdana, sans-serif;\n    padding-left:  2px;\n    padding-right: 12px;\n    border: 0px;\n}\n\nspan.SelectionMark {\n    margin-right: 4px;\n    font-family: monospace;\n    outline-style: none;\n    text-decoration: none;\n}\n\na.SelectItem {\n    display: block;\n    outline-style: none;\n    color: #000000; \n    text-decoration: none;\n    padding-left:   6px;\n    padding-right: 12px;\n}\n\na.SelectItem:focus,\na.SelectItem:active {\n    color: #000000; \n    outline-style: none;\n    text-decoration: none;\n}\n\na.SelectItem:hover {\n    color: #FFFFFF;\n    background-color: #3D578C;\n    outline-style: none;\n    text-decoration: none;\n    cursor: pointer;\n    display: block;\n}\n\n/*---------------- Search results window */\n\niframe#MSearchResults {\n    width: 60ex;\n    height: 15em;\n}\n\n#MSearchResultsWindow {\n    display: none;\n    position: absolute;\n    left: 0; top: 0;\n    border: 1px solid #000;\n    background-color: #EEF1F7;\n}\n\n/* ----------------------------------- */\n\n\n#SRIndex {\n    clear:both; \n    padding-bottom: 15px;\n}\n\n.SREntry {\n    font-size: 10pt;\n    padding-left: 1ex;\n}\n\n.SRPage .SREntry {\n    font-size: 8pt;\n    padding: 1px 5px;\n}\n\nbody.SRPage {\n    margin: 5px 2px;\n}\n\n.SRChildren {\n    padding-left: 3ex; padding-bottom: .5em \n}\n\n.SRPage .SRChildren {\n    display: none;\n}\n\n.SRSymbol {\n    font-weight: bold; \n    color: #425E97;\n    font-family: Arial, Verdana, sans-serif;\n    text-decoration: none;\n    outline: none;\n}\n\na.SRScope {\n    display: block;\n    color: #425E97; \n    font-family: Arial, Verdana, sans-serif;\n    text-decoration: none;\n    outline: none;\n}\n\na.SRSymbol:focus, a.SRSymbol:active,\na.SRScope:focus, a.SRScope:active {\n    text-decoration: underline;\n}\n\n.SRPage .SRStatus {\n    padding: 2px 5px;\n    font-size: 8pt;\n    font-style: italic;\n}\n\n.SRResult {\n    display: none;\n}\n\nDIV.searchresults {\n    margin-left: 10px;\n    margin-right: 10px;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/search/search.js",
    "content": "// Search script generated by doxygen\n// Copyright (C) 2009 by Dimitri van Heesch.\n\n// The code in this file is loosly based on main.js, part of Natural Docs,\n// which is Copyright (C) 2003-2008 Greg Valure\n// Natural Docs is licensed under the GPL.\n\nvar indexSectionsWithContent =\n{\n  0: \"cmoprs\",\n  1: \"cmoprs\"\n};\n\nvar indexSectionNames =\n{\n  0: \"all\",\n  1: \"pages\"\n};\n\nfunction convertToId(search)\n{\n  var result = '';\n  for (i=0;i<search.length;i++)\n  {\n    var c = search.charAt(i);\n    var cn = c.charCodeAt(0);\n    if (c.match(/[a-z0-9\\u0080-\\uFFFF]/))\n    {\n      result+=c;\n    }\n    else if (cn<16) \n    {\n      result+=\"_0\"+cn.toString(16);\n    }\n    else \n    {\n      result+=\"_\"+cn.toString(16);\n    }\n  }\n  return result;\n}\n\nfunction getXPos(item)\n{\n  var x = 0;\n  if (item.offsetWidth)\n  {\n    while (item && item!=document.body)\n    {\n      x   += item.offsetLeft;\n      item = item.offsetParent;\n    }\n  }\n  return x;\n}\n\nfunction getYPos(item)\n{\n  var y = 0;\n  if (item.offsetWidth)\n  {\n     while (item && item!=document.body)\n     {\n       y   += item.offsetTop;\n       item = item.offsetParent;\n     }\n  }\n  return y;\n}\n\n/* A class handling everything associated with the search panel.\n\n   Parameters:\n   name - The name of the global variable that will be \n          storing this instance.  Is needed to be able to set timeouts.\n   resultPath - path to use for external files\n*/\nfunction SearchBox(name, resultsPath, inFrame, label)\n{\n  if (!name || !resultsPath) {  alert(\"Missing parameters to SearchBox.\"); }\n   \n  // ---------- Instance variables\n  this.name                  = name;\n  this.resultsPath           = resultsPath;\n  this.keyTimeout            = 0;\n  this.keyTimeoutLength      = 500;\n  this.closeSelectionTimeout = 300;\n  this.lastSearchValue       = \"\";\n  this.lastResultsPage       = \"\";\n  this.hideTimeout           = 0;\n  this.searchIndex           = 0;\n  this.searchActive          = false;\n  this.insideFrame           = inFrame;\n  this.searchLabel           = label;\n\n  // ----------- DOM Elements\n\n  this.DOMSearchField = function()\n  {  return document.getElementById(\"MSearchField\");  }\n\n  this.DOMSearchSelect = function()\n  {  return document.getElementById(\"MSearchSelect\");  }\n\n  this.DOMSearchSelectWindow = function()\n  {  return document.getElementById(\"MSearchSelectWindow\");  }\n\n  this.DOMPopupSearchResults = function()\n  {  return document.getElementById(\"MSearchResults\");  }\n\n  this.DOMPopupSearchResultsWindow = function()\n  {  return document.getElementById(\"MSearchResultsWindow\");  }\n\n  this.DOMSearchClose = function()\n  {  return document.getElementById(\"MSearchClose\"); }\n\n  this.DOMSearchBox = function()\n  {  return document.getElementById(\"MSearchBox\");  }\n\n  // ------------ Event Handlers\n\n  // Called when focus is added or removed from the search field.\n  this.OnSearchFieldFocus = function(isActive)\n  {\n    this.Activate(isActive);\n  }\n\n  this.OnSearchSelectShow = function()\n  {\n    var searchSelectWindow = this.DOMSearchSelectWindow();\n    var searchField        = this.DOMSearchSelect();\n\n    if (this.insideFrame)\n    {\n      var left = getXPos(searchField);\n      var top  = getYPos(searchField);\n      left += searchField.offsetWidth + 6;\n      top += searchField.offsetHeight;\n\n      // show search selection popup\n      searchSelectWindow.style.display='block';\n      left -= searchSelectWindow.offsetWidth;\n      searchSelectWindow.style.left =  left + 'px';\n      searchSelectWindow.style.top  =  top  + 'px';\n    }\n    else\n    {\n      var left = getXPos(searchField);\n      var top  = getYPos(searchField);\n      top += searchField.offsetHeight;\n\n      // show search selection popup\n      searchSelectWindow.style.display='block';\n      searchSelectWindow.style.left =  left + 'px';\n      searchSelectWindow.style.top  =  top  + 'px';\n    }\n\n    // stop selection hide timer\n    if (this.hideTimeout) \n    {\n      clearTimeout(this.hideTimeout);\n      this.hideTimeout=0;\n    }\n    return false; // to avoid \"image drag\" default event\n  }\n\n  this.OnSearchSelectHide = function()\n  {\n    this.hideTimeout = setTimeout(this.name +\".CloseSelectionWindow()\",\n                                  this.closeSelectionTimeout);\n  }\n\n  // Called when the content of the search field is changed.\n  this.OnSearchFieldChange = function(evt)\n  {\n    if (this.keyTimeout) // kill running timer\n    {\n      clearTimeout(this.keyTimeout);\n      this.keyTimeout = 0;\n    }\n\n    var e  = (evt) ? evt : window.event; // for IE\n    if (e.keyCode==40 || e.keyCode==13)\n    {\n      if (e.shiftKey==1)\n      {\n        this.OnSearchSelectShow();\n        var win=this.DOMSearchSelectWindow(); \n        for (i=0;i<win.childNodes.length;i++)\n        {\n          var child = win.childNodes[i]; // get span within a\n          if (child.className=='SelectItem')\n          {\n            child.focus();\n            return;\n          }\n        }\n        return;\n      }\n      else if (window.frames.MSearchResults.searchResults)\n      {\n        var elem = window.frames.MSearchResults.searchResults.NavNext(0);\n        if (elem) elem.focus();\n      }\n    }\n    else if (e.keyCode==27) // Escape out of the search field\n    {\n      this.DOMSearchField().blur();\n      this.DOMPopupSearchResultsWindow().style.display = 'none';\n      this.DOMSearchClose().style.display = 'none';\n      this.lastSearchValue = '';\n      this.Activate(false);\n      return;\n    }\n\n    // strip whitespaces\n    var searchValue = this.DOMSearchField().value.replace(/ +/g, \"\");\n\n    if (searchValue != this.lastSearchValue) // search value has changed\n    {\n      if (searchValue != \"\") // non-empty search\n      {\n        // set timer for search update\n        this.keyTimeout = setTimeout(this.name + '.Search()',\n                                     this.keyTimeoutLength);\n      }\n      else // empty search field\n      {\n        this.DOMPopupSearchResultsWindow().style.display = 'none';\n        this.DOMSearchClose().style.display = 'none';\n        this.lastSearchValue = '';\n      }\n    }\n  }\n\n  this.SelectItemCount = function(id)\n  {\n    var count=0;\n    var win=this.DOMSearchSelectWindow(); \n    for (i=0;i<win.childNodes.length;i++)\n    {\n      var child = win.childNodes[i]; // get span within a\n      if (child.className=='SelectItem')\n      {\n        count++;\n      }\n    }\n    return count;\n  }\n\n  this.SelectItemSet = function(id)\n  {\n    var i,j=0;\n    var win=this.DOMSearchSelectWindow(); \n    for (i=0;i<win.childNodes.length;i++)\n    {\n      var child = win.childNodes[i]; // get span within a\n      if (child.className=='SelectItem')\n      {\n        var node = child.firstChild;\n        if (j==id)\n        {\n          node.innerHTML='&#8226;';\n        }\n        else\n        {\n          node.innerHTML='&#160;';\n        }\n        j++;\n      }\n    }\n  }\n\n  // Called when an search filter selection is made.\n  // set item with index id as the active item\n  this.OnSelectItem = function(id)\n  {\n    this.searchIndex = id;\n    this.SelectItemSet(id);\n    var searchValue = this.DOMSearchField().value.replace(/ +/g, \"\");\n    if (searchValue!=\"\" && this.searchActive) // something was found -> do a search\n    {\n      this.Search();\n    }\n  }\n\n  this.OnSearchSelectKey = function(evt)\n  {\n    var e = (evt) ? evt : window.event; // for IE\n    if (e.keyCode==40 && this.searchIndex<this.SelectItemCount()) // Down\n    {\n      this.searchIndex++;\n      this.OnSelectItem(this.searchIndex);\n    }\n    else if (e.keyCode==38 && this.searchIndex>0) // Up\n    {\n      this.searchIndex--;\n      this.OnSelectItem(this.searchIndex);\n    }\n    else if (e.keyCode==13 || e.keyCode==27)\n    {\n      this.OnSelectItem(this.searchIndex);\n      this.CloseSelectionWindow();\n      this.DOMSearchField().focus();\n    }\n    return false;\n  }\n\n  // --------- Actions\n\n  // Closes the results window.\n  this.CloseResultsWindow = function()\n  {\n    this.DOMPopupSearchResultsWindow().style.display = 'none';\n    this.DOMSearchClose().style.display = 'none';\n    this.Activate(false);\n  }\n\n  this.CloseSelectionWindow = function()\n  {\n    this.DOMSearchSelectWindow().style.display = 'none';\n  }\n\n  // Performs a search.\n  this.Search = function()\n  {\n    this.keyTimeout = 0;\n\n    // strip leading whitespace\n    var searchValue = this.DOMSearchField().value.replace(/^ +/, \"\");\n\n    var code = searchValue.toLowerCase().charCodeAt(0);\n    var idxChar = searchValue.substr(0, 1).toLowerCase();\n    if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair\n    {\n      idxChar = searchValue.substr(0, 2);\n    }\n\n    var resultsPage;\n    var resultsPageWithSearch;\n    var hasResultsPage;\n\n    var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar);\n    if (idx!=-1)\n    {\n       var hexCode=idx.toString(16);\n       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';\n       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);\n       hasResultsPage = true;\n    }\n    else // nothing available for this search term\n    {\n       resultsPage = this.resultsPath + '/nomatches.html';\n       resultsPageWithSearch = resultsPage;\n       hasResultsPage = false;\n    }\n\n    window.frames.MSearchResults.location = resultsPageWithSearch;  \n    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();\n\n    if (domPopupSearchResultsWindow.style.display!='block')\n    {\n       var domSearchBox = this.DOMSearchBox();\n       this.DOMSearchClose().style.display = 'inline';\n       if (this.insideFrame)\n       {\n         var domPopupSearchResults = this.DOMPopupSearchResults();\n         domPopupSearchResultsWindow.style.position = 'relative';\n         domPopupSearchResultsWindow.style.display  = 'block';\n         var width = document.body.clientWidth - 8; // the -8 is for IE :-(\n         domPopupSearchResultsWindow.style.width    = width + 'px';\n         domPopupSearchResults.style.width          = width + 'px';\n       }\n       else\n       {\n         var domPopupSearchResults = this.DOMPopupSearchResults();\n         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;\n         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;\n         domPopupSearchResultsWindow.style.display = 'block';\n         left -= domPopupSearchResults.offsetWidth;\n         domPopupSearchResultsWindow.style.top     = top  + 'px';\n         domPopupSearchResultsWindow.style.left    = left + 'px';\n       }\n    }\n\n    this.lastSearchValue = searchValue;\n    this.lastResultsPage = resultsPage;\n  }\n\n  // -------- Activation Functions\n\n  // Activates or deactivates the search panel, resetting things to \n  // their default values if necessary. \n  this.Activate = function(isActive)\n  {\n    if (isActive || // open it\n        this.DOMPopupSearchResultsWindow().style.display == 'block' \n       )\n    {\n      this.DOMSearchBox().className = 'MSearchBoxActive';\n\n      var searchField = this.DOMSearchField();\n\n      if (searchField.value == this.searchLabel) // clear \"Search\" term upon entry\n      {  \n        searchField.value = '';  \n        this.searchActive = true;\n      }\n    }\n    else if (!isActive) // directly remove the panel\n    {\n      this.DOMSearchBox().className = 'MSearchBoxInactive';\n      this.DOMSearchField().value   = this.searchLabel;\n      this.searchActive             = false;\n      this.lastSearchValue          = ''\n      this.lastResultsPage          = '';\n    }\n  }\n}\n\n// -----------------------------------------------------------------------\n\n// The class that handles everything on the search results page.\nfunction SearchResults(name)\n{\n    // The number of matches from the last run of <Search()>.\n    this.lastMatchCount = 0;\n    this.lastKey = 0;\n    this.repeatOn = false;\n\n    // Toggles the visibility of the passed element ID.\n    this.FindChildElement = function(id)\n    {\n      var parentElement = document.getElementById(id);\n      var element = parentElement.firstChild;\n\n      while (element && element!=parentElement)\n      {\n        if (element.nodeName == 'DIV' && element.className == 'SRChildren')\n        {\n          return element;\n        }\n\n        if (element.nodeName == 'DIV' && element.hasChildNodes())\n        {  \n           element = element.firstChild;  \n        }\n        else if (element.nextSibling)\n        {  \n           element = element.nextSibling;  \n        }\n        else\n        {\n          do\n          {\n            element = element.parentNode;\n          }\n          while (element && element!=parentElement && !element.nextSibling);\n\n          if (element && element!=parentElement)\n          {  \n            element = element.nextSibling;  \n          }\n        }\n      }\n    }\n\n    this.Toggle = function(id)\n    {\n      var element = this.FindChildElement(id);\n      if (element)\n      {\n        if (element.style.display == 'block')\n        {\n          element.style.display = 'none';\n        }\n        else\n        {\n          element.style.display = 'block';\n        }\n      }\n    }\n\n    // Searches for the passed string.  If there is no parameter,\n    // it takes it from the URL query.\n    //\n    // Always returns true, since other documents may try to call it\n    // and that may or may not be possible.\n    this.Search = function(search)\n    {\n      if (!search) // get search word from URL\n      {\n        search = window.location.search;\n        search = search.substring(1);  // Remove the leading '?'\n        search = unescape(search);\n      }\n\n      search = search.replace(/^ +/, \"\"); // strip leading spaces\n      search = search.replace(/ +$/, \"\"); // strip trailing spaces\n      search = search.toLowerCase();\n      search = convertToId(search);\n\n      var resultRows = document.getElementsByTagName(\"div\");\n      var matches = 0;\n\n      var i = 0;\n      while (i < resultRows.length)\n      {\n        var row = resultRows.item(i);\n        if (row.className == \"SRResult\")\n        {\n          var rowMatchName = row.id.toLowerCase();\n          rowMatchName = rowMatchName.replace(/^sr\\d*_/, ''); // strip 'sr123_'\n\n          if (search.length<=rowMatchName.length && \n             rowMatchName.substr(0, search.length)==search)\n          {\n            row.style.display = 'block';\n            matches++;\n          }\n          else\n          {\n            row.style.display = 'none';\n          }\n        }\n        i++;\n      }\n      document.getElementById(\"Searching\").style.display='none';\n      if (matches == 0) // no results\n      {\n        document.getElementById(\"NoMatches\").style.display='block';\n      }\n      else // at least one result\n      {\n        document.getElementById(\"NoMatches\").style.display='none';\n      }\n      this.lastMatchCount = matches;\n      return true;\n    }\n\n    // return the first item with index index or higher that is visible\n    this.NavNext = function(index)\n    {\n      var focusItem;\n      while (1)\n      {\n        var focusName = 'Item'+index;\n        focusItem = document.getElementById(focusName);\n        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')\n        {\n          break;\n        }\n        else if (!focusItem) // last element\n        {\n          break;\n        }\n        focusItem=null;\n        index++;\n      }\n      return focusItem;\n    }\n\n    this.NavPrev = function(index)\n    {\n      var focusItem;\n      while (1)\n      {\n        var focusName = 'Item'+index;\n        focusItem = document.getElementById(focusName);\n        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')\n        {\n          break;\n        }\n        else if (!focusItem) // last element\n        {\n          break;\n        }\n        focusItem=null;\n        index--;\n      }\n      return focusItem;\n    }\n\n    this.ProcessKeys = function(e)\n    {\n      if (e.type == \"keydown\") \n      {\n        this.repeatOn = false;\n        this.lastKey = e.keyCode;\n      }\n      else if (e.type == \"keypress\")\n      {\n        if (!this.repeatOn)\n        {\n          if (this.lastKey) this.repeatOn = true;\n          return false; // ignore first keypress after keydown\n        }\n      }\n      else if (e.type == \"keyup\")\n      {\n        this.lastKey = 0;\n        this.repeatOn = false;\n      }\n      return this.lastKey!=0;\n    }\n\n    this.Nav = function(evt,itemIndex) \n    {\n      var e  = (evt) ? evt : window.event; // for IE\n      if (e.keyCode==13) return true;\n      if (!this.ProcessKeys(e)) return false;\n\n      if (this.lastKey==38) // Up\n      {\n        var newIndex = itemIndex-1;\n        var focusItem = this.NavPrev(newIndex);\n        if (focusItem)\n        {\n          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);\n          if (child && child.style.display == 'block') // children visible\n          { \n            var n=0;\n            var tmpElem;\n            while (1) // search for last child\n            {\n              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);\n              if (tmpElem)\n              {\n                focusItem = tmpElem;\n              }\n              else // found it!\n              {\n                break;\n              }\n              n++;\n            }\n          }\n        }\n        if (focusItem)\n        {\n          focusItem.focus();\n        }\n        else // return focus to search field\n        {\n           parent.document.getElementById(\"MSearchField\").focus();\n        }\n      }\n      else if (this.lastKey==40) // Down\n      {\n        var newIndex = itemIndex+1;\n        var focusItem;\n        var item = document.getElementById('Item'+itemIndex);\n        var elem = this.FindChildElement(item.parentNode.parentNode.id);\n        if (elem && elem.style.display == 'block') // children visible\n        {\n          focusItem = document.getElementById('Item'+itemIndex+'_c0');\n        }\n        if (!focusItem) focusItem = this.NavNext(newIndex);\n        if (focusItem)  focusItem.focus();\n      }\n      else if (this.lastKey==39) // Right\n      {\n        var item = document.getElementById('Item'+itemIndex);\n        var elem = this.FindChildElement(item.parentNode.parentNode.id);\n        if (elem) elem.style.display = 'block';\n      }\n      else if (this.lastKey==37) // Left\n      {\n        var item = document.getElementById('Item'+itemIndex);\n        var elem = this.FindChildElement(item.parentNode.parentNode.id);\n        if (elem) elem.style.display = 'none';\n      }\n      else if (this.lastKey==27) // Escape\n      {\n        parent.searchBox.CloseResultsWindow();\n        parent.document.getElementById(\"MSearchField\").focus();\n      }\n      else if (this.lastKey==13) // Enter\n      {\n        return true;\n      }\n      return false;\n    }\n\n    this.NavChild = function(evt,itemIndex,childIndex)\n    {\n      var e  = (evt) ? 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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Build/html/tabs.css",
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/core.dxy",
    "content": "# Doxyfile 1.8.6\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a double hash (##) is considered a comment and is placed in\n# front of the TAG it is preceding.\n#\n# All text after a single hash (#) is considered a comment and will be ignored.\n# The format is:\n# TAG = value [value, ...]\n# For lists, items can also be appended using:\n# TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\\\" \\\").\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the config file\n# that follow. The default is UTF-8 which is also the encoding used for all text\n# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv\n# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv\n# for the list of possible encodings.\n# The default value is: UTF-8.\n\nDOXYFILE_ENCODING      = UTF-8\n\n# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by\n# double-quotes, unless you are using Doxywizard) that should identify the\n# project for which the documentation is generated. This name is used in the\n# title of most generated pages and in a few other places.\n# The default value is: My Project.\n\nPROJECT_NAME           = \"CMSIS-Core (Cortex-M)\"\n\n# The PROJECT_NUMBER tag can be used to enter a project or revision number. This\n# could be handy for archiving the generated documentation or if some version\n# control system is used.\n\nPROJECT_NUMBER         = \"Version 5.7.0\"\n\n# Using the PROJECT_BRIEF tag one can provide an optional one line description\n# for a project that appears at the top of each page and should give viewer a\n# quick idea about the purpose of the project. Keep the description short.\n\nPROJECT_BRIEF          = \"CMSIS-Core support for Cortex-M processor-based devices\"\n\n# With the PROJECT_LOGO tag one can specify an logo or icon that is included in\n# the documentation. The maximum height of the logo should not exceed 55 pixels\n# and the maximum width should not exceed 200 pixels. Doxygen will copy the logo\n# to the output directory.\n\nPROJECT_LOGO           = ../Doxygen_Templates/CMSIS_Logo_Final.png\n\n# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path\n# into which the generated documentation will be written. If a relative path is\n# entered, it will be relative to the location where doxygen was started. If\n# left blank the current directory will be used.\n\nOUTPUT_DIRECTORY       = ../../Documentation/Core\n\n# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-\n# directories (in 2 levels) under the output directory of each output format and\n# will distribute the generated files over these directories. Enabling this\n# option can be useful when feeding doxygen a huge amount of source files, where\n# putting all generated files in the same directory would otherwise causes\n# performance problems for the file system.\n# The default value is: NO.\n\nCREATE_SUBDIRS         = NO\n\n# The OUTPUT_LANGUAGE tag is used to specify the language in which all\n# documentation generated by doxygen is written. Doxygen will use this\n# information to generate all constant output in the proper language.\n# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,\n# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),\n# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,\n# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),\n# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,\n# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,\n# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,\n# Ukrainian and Vietnamese.\n# The default value is: English.\n\nOUTPUT_LANGUAGE        = English\n\n# If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member\n# descriptions after the members that are listed in the file and class\n# documentation (similar to Javadoc). Set to NO to disable this.\n# The default value is: YES.\n\nBRIEF_MEMBER_DESC      = YES\n\n# If the REPEAT_BRIEF tag is set to YES doxygen will prepend the brief\n# description of a member or function before the detailed description\n#\n# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the\n# brief descriptions will be completely suppressed.\n# The default value is: YES.\n\nREPEAT_BRIEF           = YES\n\n# This tag implements a quasi-intelligent brief description abbreviator that is\n# used to form the text in various listings. Each string in this list, if found\n# as the leading text of the brief description, will be stripped from the text\n# and the result, after processing the whole list, is used as the annotated\n# text. Otherwise, the brief description is used as-is. If left blank, the\n# following values are used ($name is automatically replaced with the name of\n# the entity):The $name class, The $name widget, The $name file, is, provides,\n# specifies, contains, represents, a, an and the.\n\nABBREVIATE_BRIEF       = \"The $name class\" \\\n                         \"The $name widget\" \\\n                         \"The $name file\" \\\n                         is \\\n                         provides \\\n                         specifies \\\n                         contains \\\n                         represents \\\n                         a \\\n                         an \\\n                         the\n\n# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then\n# doxygen will generate a detailed section even if there is only a brief\n# description.\n# The default value is: NO.\n\nALWAYS_DETAILED_SEC    = NO\n\n# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all\n# inherited members of a class in the documentation of that class as if those\n# members were ordinary class members. Constructors, destructors and assignment\n# operators of the base classes will not be shown.\n# The default value is: NO.\n\nINLINE_INHERITED_MEMB  = NO\n\n# If the FULL_PATH_NAMES tag is set to YES doxygen will prepend the full path\n# before files name in the file list and in the header files. If set to NO the\n# shortest path that makes the file name unique will be used\n# The default value is: YES.\n\nFULL_PATH_NAMES        = NO\n\n# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.\n# Stripping is only done if one of the specified strings matches the left-hand\n# part of the path. The tag can be used to show relative paths in the file list.\n# If left blank the directory from which doxygen is run is used as the path to\n# strip.\n#\n# Note that you can specify absolute paths here, but also relative paths, which\n# will be relative from the directory where doxygen is started.\n# This tag requires that the tag FULL_PATH_NAMES is set to YES.\n\nSTRIP_FROM_PATH        =\n\n# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the\n# path mentioned in the documentation of a class, which tells the reader which\n# header file to include in order to use a class. If left blank only the name of\n# the header file containing the class definition is used. Otherwise one should\n# specify the list of include paths that are normally passed to the compiler\n# using the -I flag.\n\nSTRIP_FROM_INC_PATH    =\n\n# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but\n# less readable) file names. This can be useful is your file systems doesn't\n# support long names like on DOS, Mac, or CD-ROM.\n# The default value is: NO.\n\nSHORT_NAMES            = NO\n\n# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the\n# first line (until the first dot) of a Javadoc-style comment as the brief\n# description. If set to NO, the Javadoc-style will behave just like regular Qt-\n# style comments (thus requiring an explicit @brief command for a brief\n# description.)\n# The default value is: NO.\n\nJAVADOC_AUTOBRIEF      = NO\n\n# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first\n# line (until the first dot) of a Qt-style comment as the brief description. If\n# set to NO, the Qt-style will behave just like regular Qt-style comments (thus\n# requiring an explicit \\brief command for a brief description.)\n# The default value is: NO.\n\nQT_AUTOBRIEF           = NO\n\n# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a\n# multi-line C++ special comment block (i.e. a block of //! or /// comments) as\n# a brief description. This used to be the default behavior. The new default is\n# to treat a multi-line C++ comment block as a detailed description. Set this\n# tag to YES if you prefer the old behavior instead.\n#\n# Note that setting this tag to YES also means that rational rose comments are\n# not recognized any more.\n# The default value is: NO.\n\nMULTILINE_CPP_IS_BRIEF = YES\n\n# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the\n# documentation from any documented member that it re-implements.\n# The default value is: YES.\n\nINHERIT_DOCS           = NO\n\n# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a\n# new page for each member. If set to NO, the documentation of a member will be\n# part of the file/class/namespace that contains it.\n# The default value is: NO.\n\nSEPARATE_MEMBER_PAGES  = NO\n\n# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen\n# uses this value to replace tabs by spaces in code fragments.\n# Minimum value: 1, maximum value: 16, default value: 4.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that act as commands in\n# the documentation. An alias has the form:\n# name=value\n# For example adding\n# \"sideeffect=@par Side Effects:\\n\"\n# will allow you to put the command \\sideeffect (or @sideeffect) in the\n# documentation, which will result in a user-defined paragraph with heading\n# \"Side Effects:\". You can put \\n's in the value part of an alias to insert\n# newlines.\n\nALIASES                = \"token{1}=<span class=\\\"XML-Token\\\">\\1</span>\"\n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding \"class=itcl::class\"\n# will allow you to use the command class in the itcl::class meaning.\n\nTCL_SUBST              =\n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources\n# only. Doxygen will then generate output that is more tailored for C. For\n# instance, some of the names that are used will be different. The list of all\n# members will be omitted, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_FOR_C  = YES\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or\n# Python sources only. Doxygen will then generate output that is more tailored\n# for that language. For instance, namespaces will be presented as packages,\n# qualified scopes will look different, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources. Doxygen will then generate output that is tailored for Fortran.\n# The default value is: NO.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for VHDL.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given\n# extension. Doxygen has a built-in mapping, but you can override or extend it\n# using this tag. The format is ext=language, where ext is a file extension, and\n# language is one of the parsers supported by doxygen: IDL, Java, Javascript,\n# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C.\n#\n# Note For files without extension you can use no_extension as a placeholder.\n#\n# Note that for custom extensions you also need to set FILE_PATTERNS otherwise\n# the files are not read by doxygen.\n\nEXTENSION_MAPPING      =\n\n# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments\n# according to the Markdown format, which allows for more readable\n# documentation. See http://daringfireball.net/projects/markdown/ for details.\n# The output of markdown processing is further processed by doxygen, so you can\n# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in\n# case of backward compatibilities issues.\n# The default value is: YES.\n\nMARKDOWN_SUPPORT       = YES\n\n# When enabled doxygen tries to link words that correspond to documented\n# classes, or namespaces to their corresponding documentation. Such a link can\n# be prevented in individual cases by by putting a % sign in front of the word\n# or globally by setting AUTOLINK_SUPPORT to NO.\n# The default value is: YES.\n\nAUTOLINK_SUPPORT       = YES\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should set this\n# tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string);\n# versus func(std::string) {}). This also make the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n# The default value is: NO.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n# The default value is: NO.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:\n# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen\n# will parse them like normal C++ but will assume all classes use public instead\n# of private inheritance when no explicit protection keyword is present.\n# The default value is: NO.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate\n# getter and setter methods for a property. Setting this option to YES will make\n# doxygen to replace the get and set methods by a property in the documentation.\n# This will only work if the methods are indeed getting or setting a simple\n# type. If this is not the case, or you want to show the methods anyway, you\n# should set this option to NO.\n# The default value is: YES.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n# The default value is: NO.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES to allow class member groups of the same type\n# (for instance a group of public functions) to be put as a subgroup of that\n# type (e.g. under the Public Functions section). Set it to NO to prevent\n# subgrouping. Alternatively, this can be done per class using the\n# \\nosubgrouping command.\n# The default value is: YES.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions\n# are shown inside the group in which they are included (e.g. using \\ingroup)\n# instead of on a separate page (for HTML and Man pages) or section (for LaTeX\n# and RTF).\n#\n# Note that this feature does not work in combination with\n# SEPARATE_MEMBER_PAGES.\n# The default value is: NO.\n\nINLINE_GROUPED_CLASSES = NO\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions\n# with only public data fields or simple typedef fields will be shown inline in\n# the documentation of the scope in which they are defined (i.e. file,\n# namespace, or group documentation), provided this scope is documented. If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = NO\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = YES\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = YES\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = NO\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = YES\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = NO\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = NO\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = ARMv8M \\\n                         ARMSC  \\\n                         STAR\n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = YES\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    =\n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         =\n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = src/Overview.txt \\\n                         src/Using.txt \\\n                         src/UsingTrustZone.txt \\\n                         src/Template.txt \\\n                         src/MISRA.txt \\\n                         src/Ref_VersionControl.txt \\\n                         src/Ref_CompilerControl.txt \\\n                         src/Ref_Peripheral.txt \\\n                         src/Ref_SystemAndClock.txt \\\n                         src/Ref_NVIC.txt \\\n                         src/Ref_CoreReg.txt \\\n                         src/Ref_cmInstr.txt \\\n                         src/Ref_cm4_simd.txt \\\n                         src/Ref_FPU.txt \\\n                         src/Ref_MVE.txt \\\n                         src/Ref_MPU.txt \\\n                         src/Ref_MPU8.txt \\\n                         src/Ref_PMU8.txt \\\n                         src/Ref_Systick.txt \\\n                         src/Ref_Debug.txt \\\n                         src/Ref_Trustzone.txt \\\n                         src/core_cm7.txt \\\n                         src/Ref_DataStructs.txt \\\n                         src/RegMap_CMSIS2ARM_Doc.txt\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          =\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = NO\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s \\\n                         src/exclude/\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = NO\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       =\n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        =\n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = ../../../Device/_Template_Vendor/Vendor/Device\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           =\n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        =\n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS =\n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE =\n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = YES\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = YES\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = YES\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = NO\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        =\n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../Doxygen_Templates/search.css \\\n                         ../Doxygen_Templates/check.png \\\n                         ../Doxygen_Templates/printComponentTabs.js\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 106\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = CMSIS_Core.chm\n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \"C:/Program Files/HTML Help Workshop/hhc.exe\"\n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     =\n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               =\n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   =\n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  =\n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  =\n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           =\n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     =\n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       =\n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       =\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     =\n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         =\n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           =\n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           =\n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      =\n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    =\n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             =\n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                =\n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen\n# Definitions (see http://autogen.sf.net) file that captures the structure of\n# the code including all documentation. Note that this feature is still\n# experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES doxygen will generate a Perl module\n# file that captures the structure of the code including all documentation.\n#\n# Note that this feature is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES doxygen will generate the necessary\n# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI\n# output from the Perl module output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be nicely\n# formatted so it can be parsed by a human reader. This is useful if you want to\n# understand what is going on. On the other hand, if this tag is set to NO the\n# size of the Perl module output will be much smaller and Perl will parse it\n# just the same.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_PRETTY         = YES\n\n# The names of the make variables in the generated doxyrules.make file are\n# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful\n# so different doxyrules.make files included by the same Makefile don't\n# overwrite each other's variables.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_MAKEVAR_PREFIX =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the preprocessor\n#---------------------------------------------------------------------------\n\n# If the ENABLE_PREPROCESSING tag is set to YES doxygen will evaluate all\n# C-preprocessor directives found in the sources and include files.\n# The default value is: YES.\n\nENABLE_PREPROCESSING   = YES\n\n# If the MACRO_EXPANSION tag is set to YES doxygen will expand all macro names\n# in the source code. If set to NO only conditional compilation will be\n# performed. Macro expansion can be done in a controlled way by setting\n# EXPAND_ONLY_PREDEF to YES.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nMACRO_EXPANSION        = NO\n\n# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then\n# the macro expansion is limited to the macros specified with the PREDEFINED and\n# EXPAND_AS_DEFINED tags.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_ONLY_PREDEF     = NO\n\n# If the SEARCH_INCLUDES tag is set to YES the includes files in the\n# INCLUDE_PATH will be searched if a #include is found.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSEARCH_INCLUDES        = YES\n\n# The INCLUDE_PATH tag can be used to specify one or more directories that\n# contain include files that are not input files but should be processed by the\n# preprocessor.\n# This tag requires that the tag SEARCH_INCLUDES is set to YES.\n\nINCLUDE_PATH           =\n\n# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard\n# patterns (like *.h and *.hpp) to filter out the header-files in the\n# directories. If left blank, the patterns specified with FILE_PATTERNS will be\n# used.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nINCLUDE_FILE_PATTERNS  =\n\n# The PREDEFINED tag can be used to specify one or more macro names that are\n# defined before the preprocessor is started (similar to the -D option of e.g.\n# gcc). The argument of the tag is a list of macros of the form: name or\n# name=definition (no spaces). If the definition and the \"=\" are omitted, \"=1\"\n# is assumed. To prevent a macro definition from being undefined via #undef or\n# recursively expanded use the := operator instead of the = operator.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nPREDEFINED             =\n\n# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this\n# tag can be used to specify a list of macro names that should be expanded. The\n# macro definition that is found in the sources will be used. Use the PREDEFINED\n# tag if you want to use a different macro definition that overrules the\n# definition found in the source code.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_AS_DEFINED      =\n\n# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will\n# remove all refrences to function-like macros that are alone on a line, have an\n# all uppercase name, and do not end with a semicolon. Such function macros are\n# typically used for boiler-plate code, and will confuse the parser if not\n# removed.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSKIP_FUNCTION_MACROS   = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to external references\n#---------------------------------------------------------------------------\n\n# The TAGFILES tag can be used to specify one or more tag files. For each tag\n# file the location of the external documentation should be added. The format of\n# a tag file without this location is as follows:\n# TAGFILES = file1 file2 ...\n# Adding location for the tag files is done as follows:\n# TAGFILES = file1=loc1 \"file2 = loc2\" ...\n# where loc1 and loc2 can be relative or absolute paths or URLs. See the\n# section \"Linking to external documentation\" for more information about the use\n# of tag files.\n# Note: Each tag file must have an unique name (where the name does NOT include\n# the path). If a tag file is not located in the directory in which doxygen is\n# run, you must also specify the path to the tagfile here.\n\nTAGFILES               =\n\n# When a file name is specified after GENERATE_TAGFILE, doxygen will create a\n# tag file that is based on the input files it reads. See section \"Linking to\n# external documentation\" for more information about the usage of tag files.\n\nGENERATE_TAGFILE       =\n\n# If the ALLEXTERNALS tag is set to YES all external class will be listed in the\n# class index. If set to NO only the inherited external classes will be listed.\n# The default value is: NO.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in\n# the modules index. If set to NO, only the current project's groups will be\n# listed.\n# The default value is: YES.\n\nEXTERNAL_GROUPS        = YES\n\n# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in\n# the related pages index. If set to NO, only the current project's pages will\n# be listed.\n# The default value is: YES.\n\nEXTERNAL_PAGES         = YES\n\n# The PERL_PATH should be the absolute path and name of the perl script\n# interpreter (i.e. the result of 'which perl').\n# The default file (with absolute path) is: /usr/bin/perl.\n\nPERL_PATH              = /usr/bin/perl\n\n#---------------------------------------------------------------------------\n# Configuration options related to the dot tool\n#---------------------------------------------------------------------------\n\n# If the CLASS_DIAGRAMS tag is set to YES doxygen will generate a class diagram\n# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to\n# NO turns the diagrams off. Note that this option also works with HAVE_DOT\n# disabled, but it is recommended to install and use dot, since it yields more\n# powerful graphs.\n# The default value is: YES.\n\nCLASS_DIAGRAMS         = YES\n\n# You can define message sequence charts within doxygen comments using the \\msc\n# command. Doxygen will then run the mscgen tool (see:\n# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the\n# documentation. The MSCGEN_PATH tag allows you to specify the directory where\n# the mscgen tool resides. If left empty the tool is assumed to be found in the\n# default search path.\n\nMSCGEN_PATH            =\n\n# You can include diagrams made with dia in doxygen documentation. Doxygen will\n# then run dia to produce the diagram and insert it in the documentation. The\n# DIA_PATH tag allows you to specify the directory where the dia binary resides.\n# If left empty dia is assumed to be found in the default search path.\n\nDIA_PATH               =\n\n# If set to YES, the inheritance and collaboration graphs will hide inheritance\n# and usage relations if the target is undocumented or is not a class.\n# The default value is: YES.\n\nHIDE_UNDOC_RELATIONS   = YES\n\n# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is\n# available from the path. This tool is part of Graphviz (see:\n# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent\n# Bell Labs. The other options in this section have no effect if this option is\n# set to NO\n# The default value is: NO.\n\nHAVE_DOT               = NO\n\n# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed\n# to run in parallel. When set to 0 doxygen will base this on the number of\n# processors available in the system. You can set it explicitly to a value\n# larger than 0 to get control over the balance between CPU load and processing\n# speed.\n# Minimum value: 0, maximum value: 32, default value: 0.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_NUM_THREADS        = 0\n\n# When you want a differently looking font n the dot files that doxygen\n# generates you can specify the font name using DOT_FONTNAME. You need to make\n# sure dot is able to find the font, which can be done by putting it in a\n# standard location or by setting the DOTFONTPATH environment variable or by\n# setting DOT_FONTPATH to the directory containing the font.\n# The default value is: Helvetica.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTNAME           = Helvetica\n\n# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of\n# dot graphs.\n# Minimum value: 4, maximum value: 24, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTSIZE           = 10\n\n# By default doxygen will tell dot to use the default font as specified with\n# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set\n# the path where dot can find it using this tag.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTPATH           =\n\n# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for\n# each documented class showing the direct and indirect inheritance relations.\n# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCLASS_GRAPH            = YES\n\n# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a\n# graph for each documented class showing the direct and indirect implementation\n# dependencies (inheritance, containment, and class references variables) of the\n# class with other documented classes.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCOLLABORATION_GRAPH    = YES\n\n# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for\n# groups, showing the direct groups dependencies.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGROUP_GRAPHS           = YES\n\n# If the UML_LOOK tag is set to YES doxygen will generate inheritance and\n# collaboration diagrams in a style similar to the OMG's Unified Modeling\n# Language.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LOOK               = NO\n\n# If the UML_LOOK tag is enabled, the fields and methods are shown inside the\n# class node. If there are many fields or methods and many nodes the graph may\n# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the\n# number of items for each type to make the size more manageable. Set this to 0\n# for no limit. Note that the threshold may be exceeded by 50% before the limit\n# is enforced. So when you set the threshold to 10, up to 15 fields may appear,\n# but if the number exceeds 15, the total amount of fields shown is limited to\n# 10.\n# Minimum value: 0, maximum value: 100, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LIMIT_NUM_FIELDS   = 10\n\n# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and\n# collaboration graphs will show the relations between templates and their\n# instances.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nTEMPLATE_RELATIONS     = NO\n\n# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to\n# YES then doxygen will generate a graph for each documented file showing the\n# direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDE_GRAPH          = YES\n\n# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are\n# set to YES then doxygen will generate a graph for each documented file showing\n# the direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDED_BY_GRAPH      = YES\n\n# If the CALL_GRAPH tag is set to YES then doxygen will generate a call\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable call graphs for selected\n# functions only using the \\callgraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALL_GRAPH             = NO\n\n# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable caller graphs for selected\n# functions only using the \\callergraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALLER_GRAPH           = NO\n\n# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical\n# hierarchy of all classes instead of a textual one.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGRAPHICAL_HIERARCHY    = YES\n\n# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the\n# dependencies a directory has on other directories in a graphical way. The\n# dependency relations are determined by the #include relations between the\n# files in the directories.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDIRECTORY_GRAPH        = YES\n\n# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images\n# generated by dot.\n# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order\n# to make the SVG files visible in IE 9+ (other browsers do not have this\n# requirement).\n# Possible values are: png, jpg, gif and svg.\n# The default value is: png.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_IMAGE_FORMAT       = png\n\n# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to\n# enable generation of interactive SVG images that allow zooming and panning.\n#\n# Note that this requires a modern browser other than Internet Explorer. Tested\n# and working are Firefox, Chrome, Safari, and Opera.\n# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make\n# the SVG files visible. Older versions of IE do not have SVG support.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINTERACTIVE_SVG        = NO\n\n# The DOT_PATH tag can be used to specify the path where the dot tool can be\n# found. If left blank, it is assumed the dot tool can be found in the path.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_PATH               =\n\n# The DOTFILE_DIRS tag can be used to specify one or more directories that\n# contain dot files that are included in the documentation (see the \\dotfile\n# command).\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOTFILE_DIRS           =\n\n# The MSCFILE_DIRS tag can be used to specify one or more directories that\n# contain msc files that are included in the documentation (see the \\mscfile\n# command).\n\nMSCFILE_DIRS           =\n\n# The DIAFILE_DIRS tag can be used to specify one or more directories that\n# contain dia files that are included in the documentation (see the \\diafile\n# command).\n\nDIAFILE_DIRS           =\n\n# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes\n# that will be shown in the graph. If the number of nodes in a graph becomes\n# larger than this value, doxygen will truncate the graph, which is visualized\n# by representing a node as a red box. Note that doxygen if the number of direct\n# children of the root node in a graph is already larger than\n# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note that\n# the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.\n# Minimum value: 0, maximum value: 10000, default value: 50.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_GRAPH_MAX_NODES    = 50\n\n# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the graphs\n# generated by dot. A depth value of 3 means that only nodes reachable from the\n# root by following a path via at most 3 edges will be shown. Nodes that lay\n# further from the root node will be omitted. Note that setting this option to 1\n# or 2 may greatly reduce the computation time needed for large code bases. Also\n# note that the size of a graph can be further restricted by\n# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.\n# Minimum value: 0, maximum value: 1000, default value: 0.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nMAX_DOT_GRAPH_DEPTH    = 0\n\n# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent\n# background. This is disabled by default, because dot on Windows does not seem\n# to support this out of the box.\n#\n# Warning: Depending on the platform used, enabling this option may lead to\n# badly anti-aliased labels on the edges of a graph (i.e. they become hard to\n# read).\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_TRANSPARENT        = NO\n\n# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output\n# files in one run (i.e. multiple -o and -T options on the command line). This\n# makes dot run faster, but since only newer versions of dot (>1.8.10) support\n# this, this feature is disabled by default.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_MULTI_TARGETS      = NO\n\n# If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page\n# explaining the meaning of the various boxes and arrows in the dot generated\n# graphs.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGENERATE_LEGEND        = YES\n\n# If the DOT_CLEANUP tag is set to YES doxygen will remove the intermediate dot\n# files that are used to generate the various graphs.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_CLEANUP            = YES\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/core_CM0-7.dxy",
    "content": "# Doxyfile 1.8.6\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a double hash (##) is considered a comment and is placed in\n# front of the TAG it is preceding.\n#\n# All text after a single hash (#) is considered a comment and will be ignored.\n# The format is:\n# TAG = value [value, ...]\n# For lists, items can also be appended using:\n# TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\\\" \\\").\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the config file\n# that follow. The default is UTF-8 which is also the encoding used for all text\n# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv\n# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv\n# for the list of possible encodings.\n# The default value is: UTF-8.\n\nDOXYFILE_ENCODING      = UTF-8\n\n# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by\n# double-quotes, unless you are using Doxywizard) that should identify the\n# project for which the documentation is generated. This name is used in the\n# title of most generated pages and in a few other places.\n# The default value is: My Project.\n\nPROJECT_NAME           = \"CMSIS-Core (Cortex-M)\"\n\n# The PROJECT_NUMBER tag can be used to enter a project or revision number. This\n# could be handy for archiving the generated documentation or if some version\n# control system is used.\n\nPROJECT_NUMBER         = \"Version 5.7.0\"\n\n# Using the PROJECT_BRIEF tag one can provide an optional one line description\n# for a project that appears at the top of each page and should give viewer a\n# quick idea about the purpose of the project. Keep the description short.\n\nPROJECT_BRIEF          = \"CMSIS-Core support for Cortex-M processor-based devices\"\n\n# With the PROJECT_LOGO tag one can specify an logo or icon that is included in\n# the documentation. The maximum height of the logo should not exceed 55 pixels\n# and the maximum width should not exceed 200 pixels. Doxygen will copy the logo\n# to the output directory.\n\nPROJECT_LOGO           = ../Doxygen_Templates/CMSIS_Logo_Final.png\n\n# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path\n# into which the generated documentation will be written. If a relative path is\n# entered, it will be relative to the location where doxygen was started. If\n# left blank the current directory will be used.\n\nOUTPUT_DIRECTORY       = ../../Documentation/Core\n\n# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-\n# directories (in 2 levels) under the output directory of each output format and\n# will distribute the generated files over these directories. Enabling this\n# option can be useful when feeding doxygen a huge amount of source files, where\n# putting all generated files in the same directory would otherwise causes\n# performance problems for the file system.\n# The default value is: NO.\n\nCREATE_SUBDIRS         = NO\n\n# The OUTPUT_LANGUAGE tag is used to specify the language in which all\n# documentation generated by doxygen is written. Doxygen will use this\n# information to generate all constant output in the proper language.\n# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,\n# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),\n# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,\n# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),\n# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,\n# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,\n# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,\n# Ukrainian and Vietnamese.\n# The default value is: English.\n\nOUTPUT_LANGUAGE        = English\n\n# If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member\n# descriptions after the members that are listed in the file and class\n# documentation (similar to Javadoc). Set to NO to disable this.\n# The default value is: YES.\n\nBRIEF_MEMBER_DESC      = YES\n\n# If the REPEAT_BRIEF tag is set to YES doxygen will prepend the brief\n# description of a member or function before the detailed description\n#\n# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the\n# brief descriptions will be completely suppressed.\n# The default value is: YES.\n\nREPEAT_BRIEF           = NO\n\n# This tag implements a quasi-intelligent brief description abbreviator that is\n# used to form the text in various listings. Each string in this list, if found\n# as the leading text of the brief description, will be stripped from the text\n# and the result, after processing the whole list, is used as the annotated\n# text. Otherwise, the brief description is used as-is. If left blank, the\n# following values are used ($name is automatically replaced with the name of\n# the entity):The $name class, The $name widget, The $name file, is, provides,\n# specifies, contains, represents, a, an and the.\n\nABBREVIATE_BRIEF       = \"The $name class\" \\\n                         \"The $name widget\" \\\n                         \"The $name file\" \\\n                         is \\\n                         provides \\\n                         specifies \\\n                         contains \\\n                         represents \\\n                         a \\\n                         an \\\n                         the\n\n# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then\n# doxygen will generate a detailed section even if there is only a brief\n# description.\n# The default value is: NO.\n\nALWAYS_DETAILED_SEC    = NO\n\n# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all\n# inherited members of a class in the documentation of that class as if those\n# members were ordinary class members. Constructors, destructors and assignment\n# operators of the base classes will not be shown.\n# The default value is: NO.\n\nINLINE_INHERITED_MEMB  = NO\n\n# If the FULL_PATH_NAMES tag is set to YES doxygen will prepend the full path\n# before files name in the file list and in the header files. If set to NO the\n# shortest path that makes the file name unique will be used\n# The default value is: YES.\n\nFULL_PATH_NAMES        = NO\n\n# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.\n# Stripping is only done if one of the specified strings matches the left-hand\n# part of the path. The tag can be used to show relative paths in the file list.\n# If left blank the directory from which doxygen is run is used as the path to\n# strip.\n#\n# Note that you can specify absolute paths here, but also relative paths, which\n# will be relative from the directory where doxygen is started.\n# This tag requires that the tag FULL_PATH_NAMES is set to YES.\n\nSTRIP_FROM_PATH        =\n\n# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the\n# path mentioned in the documentation of a class, which tells the reader which\n# header file to include in order to use a class. If left blank only the name of\n# the header file containing the class definition is used. Otherwise one should\n# specify the list of include paths that are normally passed to the compiler\n# using the -I flag.\n\nSTRIP_FROM_INC_PATH    =\n\n# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but\n# less readable) file names. This can be useful is your file systems doesn't\n# support long names like on DOS, Mac, or CD-ROM.\n# The default value is: NO.\n\nSHORT_NAMES            = NO\n\n# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the\n# first line (until the first dot) of a Javadoc-style comment as the brief\n# description. If set to NO, the Javadoc-style will behave just like regular Qt-\n# style comments (thus requiring an explicit @brief command for a brief\n# description.)\n# The default value is: NO.\n\nJAVADOC_AUTOBRIEF      = NO\n\n# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first\n# line (until the first dot) of a Qt-style comment as the brief description. If\n# set to NO, the Qt-style will behave just like regular Qt-style comments (thus\n# requiring an explicit \\brief command for a brief description.)\n# The default value is: NO.\n\nQT_AUTOBRIEF           = NO\n\n# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a\n# multi-line C++ special comment block (i.e. a block of //! or /// comments) as\n# a brief description. This used to be the default behavior. The new default is\n# to treat a multi-line C++ comment block as a detailed description. Set this\n# tag to YES if you prefer the old behavior instead.\n#\n# Note that setting this tag to YES also means that rational rose comments are\n# not recognized any more.\n# The default value is: NO.\n\nMULTILINE_CPP_IS_BRIEF = YES\n\n# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the\n# documentation from any documented member that it re-implements.\n# The default value is: YES.\n\nINHERIT_DOCS           = NO\n\n# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a\n# new page for each member. If set to NO, the documentation of a member will be\n# part of the file/class/namespace that contains it.\n# The default value is: NO.\n\nSEPARATE_MEMBER_PAGES  = NO\n\n# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen\n# uses this value to replace tabs by spaces in code fragments.\n# Minimum value: 1, maximum value: 16, default value: 4.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that act as commands in\n# the documentation. An alias has the form:\n# name=value\n# For example adding\n# \"sideeffect=@par Side Effects:\\n\"\n# will allow you to put the command \\sideeffect (or @sideeffect) in the\n# documentation, which will result in a user-defined paragraph with heading\n# \"Side Effects:\". You can put \\n's in the value part of an alias to insert\n# newlines.\n\nALIASES                = \"token{1}=<span class=\\\"XML-Token\\\">\\1</span>\"\n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding \"class=itcl::class\"\n# will allow you to use the command class in the itcl::class meaning.\n\nTCL_SUBST              =\n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources\n# only. Doxygen will then generate output that is more tailored for C. For\n# instance, some of the names that are used will be different. The list of all\n# members will be omitted, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_FOR_C  = YES\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or\n# Python sources only. Doxygen will then generate output that is more tailored\n# for that language. For instance, namespaces will be presented as packages,\n# qualified scopes will look different, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources. Doxygen will then generate output that is tailored for Fortran.\n# The default value is: NO.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for VHDL.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given\n# extension. Doxygen has a built-in mapping, but you can override or extend it\n# using this tag. The format is ext=language, where ext is a file extension, and\n# language is one of the parsers supported by doxygen: IDL, Java, Javascript,\n# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C.\n#\n# Note For files without extension you can use no_extension as a placeholder.\n#\n# Note that for custom extensions you also need to set FILE_PATTERNS otherwise\n# the files are not read by doxygen.\n\nEXTENSION_MAPPING      =\n\n# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments\n# according to the Markdown format, which allows for more readable\n# documentation. See http://daringfireball.net/projects/markdown/ for details.\n# The output of markdown processing is further processed by doxygen, so you can\n# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in\n# case of backward compatibilities issues.\n# The default value is: YES.\n\nMARKDOWN_SUPPORT       = YES\n\n# When enabled doxygen tries to link words that correspond to documented\n# classes, or namespaces to their corresponding documentation. Such a link can\n# be prevented in individual cases by by putting a % sign in front of the word\n# or globally by setting AUTOLINK_SUPPORT to NO.\n# The default value is: YES.\n\nAUTOLINK_SUPPORT       = YES\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should set this\n# tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string);\n# versus func(std::string) {}). This also make the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n# The default value is: NO.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n# The default value is: NO.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:\n# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen\n# will parse them like normal C++ but will assume all classes use public instead\n# of private inheritance when no explicit protection keyword is present.\n# The default value is: NO.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate\n# getter and setter methods for a property. Setting this option to YES will make\n# doxygen to replace the get and set methods by a property in the documentation.\n# This will only work if the methods are indeed getting or setting a simple\n# type. If this is not the case, or you want to show the methods anyway, you\n# should set this option to NO.\n# The default value is: YES.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n# The default value is: NO.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES to allow class member groups of the same type\n# (for instance a group of public functions) to be put as a subgroup of that\n# type (e.g. under the Public Functions section). Set it to NO to prevent\n# subgrouping. Alternatively, this can be done per class using the\n# \\nosubgrouping command.\n# The default value is: YES.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions\n# are shown inside the group in which they are included (e.g. using \\ingroup)\n# instead of on a separate page (for HTML and Man pages) or section (for LaTeX\n# and RTF).\n#\n# Note that this feature does not work in combination with\n# SEPARATE_MEMBER_PAGES.\n# The default value is: NO.\n\nINLINE_GROUPED_CLASSES = NO\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions\n# with only public data fields or simple typedef fields will be shown inline in\n# the documentation of the scope in which they are defined (i.e. file,\n# namespace, or group documentation), provided this scope is documented. If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = NO\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = YES\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = YES\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = NO\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = YES\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = NO\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = NO\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       =\n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = YES\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    =\n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         =\n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = src/Overview.txt \\\n                         src/Using.txt \\\n                         src/UsingTrustZone.txt \\\n                         src/Template.txt \\\n                         src/MISRA.txt \\\n                         src/Ref_VersionControl.txt \\\n                         src/Ref_CompilerControl.txt \\\n                         src/Ref_Peripheral.txt \\\n                         src/Ref_SystemAndClock.txt \\\n                         src/Ref_NVIC.txt \\\n                         src/Ref_CoreReg.txt \\\n                         src/Ref_cmInstr.txt \\\n                         src/Ref_cm4_simd.txt \\\n                         src/Ref_FPU.txt \\\n                         src/Ref_MPU.txt \\\n                         src/Ref_Systick.txt \\\n                         src/Ref_Debug.txt \\\n                         src/Ref_Trustzone.txt \\\n                         src/core_cm7.txt \\\n                         src/Ref_DataStructs.txt \\\n                         src/RegMap_CMSIS2ARM_Doc.txt\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          =\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = NO\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s \\\n                         src/exclude/\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = NO\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       =\n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        =\n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = ../../../Device/_Template_Vendor/Vendor/Device\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           =\n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        =\n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS =\n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE =\n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = YES\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = YES\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = YES\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = NO\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        =\n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../Doxygen_Templates/search.css \\\n                         ../Doxygen_Templates/check.png \\\n                         ../Doxygen_Templates/printComponentTabs.js\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 106\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = CMSIS_Core.chm\n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \"C:/Program Files/HTML Help Workshop/hhc.exe\"\n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     =\n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               =\n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   =\n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  =\n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  =\n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           =\n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     =\n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       =\n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       =\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     =\n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         =\n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           =\n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           =\n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      =\n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    =\n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             =\n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                =\n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen\n# Definitions (see http://autogen.sf.net) file that captures the structure of\n# the code including all documentation. Note that this feature is still\n# experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES doxygen will generate a Perl module\n# file that captures the structure of the code including all documentation.\n#\n# Note that this feature is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES doxygen will generate the necessary\n# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI\n# output from the Perl module output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be nicely\n# formatted so it can be parsed by a human reader. This is useful if you want to\n# understand what is going on. On the other hand, if this tag is set to NO the\n# size of the Perl module output will be much smaller and Perl will parse it\n# just the same.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_PRETTY         = YES\n\n# The names of the make variables in the generated doxyrules.make file are\n# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful\n# so different doxyrules.make files included by the same Makefile don't\n# overwrite each other's variables.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_MAKEVAR_PREFIX =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the preprocessor\n#---------------------------------------------------------------------------\n\n# If the ENABLE_PREPROCESSING tag is set to YES doxygen will evaluate all\n# C-preprocessor directives found in the sources and include files.\n# The default value is: YES.\n\nENABLE_PREPROCESSING   = YES\n\n# If the MACRO_EXPANSION tag is set to YES doxygen will expand all macro names\n# in the source code. If set to NO only conditional compilation will be\n# performed. Macro expansion can be done in a controlled way by setting\n# EXPAND_ONLY_PREDEF to YES.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nMACRO_EXPANSION        = NO\n\n# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then\n# the macro expansion is limited to the macros specified with the PREDEFINED and\n# EXPAND_AS_DEFINED tags.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_ONLY_PREDEF     = NO\n\n# If the SEARCH_INCLUDES tag is set to YES the includes files in the\n# INCLUDE_PATH will be searched if a #include is found.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSEARCH_INCLUDES        = YES\n\n# The INCLUDE_PATH tag can be used to specify one or more directories that\n# contain include files that are not input files but should be processed by the\n# preprocessor.\n# This tag requires that the tag SEARCH_INCLUDES is set to YES.\n\nINCLUDE_PATH           =\n\n# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard\n# patterns (like *.h and *.hpp) to filter out the header-files in the\n# directories. If left blank, the patterns specified with FILE_PATTERNS will be\n# used.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nINCLUDE_FILE_PATTERNS  =\n\n# The PREDEFINED tag can be used to specify one or more macro names that are\n# defined before the preprocessor is started (similar to the -D option of e.g.\n# gcc). The argument of the tag is a list of macros of the form: name or\n# name=definition (no spaces). If the definition and the \"=\" are omitted, \"=1\"\n# is assumed. To prevent a macro definition from being undefined via #undef or\n# recursively expanded use the := operator instead of the = operator.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nPREDEFINED             =\n\n# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this\n# tag can be used to specify a list of macro names that should be expanded. The\n# macro definition that is found in the sources will be used. Use the PREDEFINED\n# tag if you want to use a different macro definition that overrules the\n# definition found in the source code.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_AS_DEFINED      =\n\n# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will\n# remove all refrences to function-like macros that are alone on a line, have an\n# all uppercase name, and do not end with a semicolon. Such function macros are\n# typically used for boiler-plate code, and will confuse the parser if not\n# removed.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSKIP_FUNCTION_MACROS   = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to external references\n#---------------------------------------------------------------------------\n\n# The TAGFILES tag can be used to specify one or more tag files. For each tag\n# file the location of the external documentation should be added. The format of\n# a tag file without this location is as follows:\n# TAGFILES = file1 file2 ...\n# Adding location for the tag files is done as follows:\n# TAGFILES = file1=loc1 \"file2 = loc2\" ...\n# where loc1 and loc2 can be relative or absolute paths or URLs. See the\n# section \"Linking to external documentation\" for more information about the use\n# of tag files.\n# Note: Each tag file must have an unique name (where the name does NOT include\n# the path). If a tag file is not located in the directory in which doxygen is\n# run, you must also specify the path to the tagfile here.\n\nTAGFILES               =\n\n# When a file name is specified after GENERATE_TAGFILE, doxygen will create a\n# tag file that is based on the input files it reads. See section \"Linking to\n# external documentation\" for more information about the usage of tag files.\n\nGENERATE_TAGFILE       =\n\n# If the ALLEXTERNALS tag is set to YES all external class will be listed in the\n# class index. If set to NO only the inherited external classes will be listed.\n# The default value is: NO.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in\n# the modules index. If set to NO, only the current project's groups will be\n# listed.\n# The default value is: YES.\n\nEXTERNAL_GROUPS        = YES\n\n# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in\n# the related pages index. If set to NO, only the current project's pages will\n# be listed.\n# The default value is: YES.\n\nEXTERNAL_PAGES         = YES\n\n# The PERL_PATH should be the absolute path and name of the perl script\n# interpreter (i.e. the result of 'which perl').\n# The default file (with absolute path) is: /usr/bin/perl.\n\nPERL_PATH              = /usr/bin/perl\n\n#---------------------------------------------------------------------------\n# Configuration options related to the dot tool\n#---------------------------------------------------------------------------\n\n# If the CLASS_DIAGRAMS tag is set to YES doxygen will generate a class diagram\n# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to\n# NO turns the diagrams off. Note that this option also works with HAVE_DOT\n# disabled, but it is recommended to install and use dot, since it yields more\n# powerful graphs.\n# The default value is: YES.\n\nCLASS_DIAGRAMS         = YES\n\n# You can define message sequence charts within doxygen comments using the \\msc\n# command. Doxygen will then run the mscgen tool (see:\n# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the\n# documentation. The MSCGEN_PATH tag allows you to specify the directory where\n# the mscgen tool resides. If left empty the tool is assumed to be found in the\n# default search path.\n\nMSCGEN_PATH            =\n\n# You can include diagrams made with dia in doxygen documentation. Doxygen will\n# then run dia to produce the diagram and insert it in the documentation. The\n# DIA_PATH tag allows you to specify the directory where the dia binary resides.\n# If left empty dia is assumed to be found in the default search path.\n\nDIA_PATH               =\n\n# If set to YES, the inheritance and collaboration graphs will hide inheritance\n# and usage relations if the target is undocumented or is not a class.\n# The default value is: YES.\n\nHIDE_UNDOC_RELATIONS   = YES\n\n# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is\n# available from the path. This tool is part of Graphviz (see:\n# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent\n# Bell Labs. The other options in this section have no effect if this option is\n# set to NO\n# The default value is: NO.\n\nHAVE_DOT               = NO\n\n# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed\n# to run in parallel. When set to 0 doxygen will base this on the number of\n# processors available in the system. You can set it explicitly to a value\n# larger than 0 to get control over the balance between CPU load and processing\n# speed.\n# Minimum value: 0, maximum value: 32, default value: 0.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_NUM_THREADS        = 0\n\n# When you want a differently looking font n the dot files that doxygen\n# generates you can specify the font name using DOT_FONTNAME. You need to make\n# sure dot is able to find the font, which can be done by putting it in a\n# standard location or by setting the DOTFONTPATH environment variable or by\n# setting DOT_FONTPATH to the directory containing the font.\n# The default value is: Helvetica.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTNAME           = Helvetica\n\n# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of\n# dot graphs.\n# Minimum value: 4, maximum value: 24, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTSIZE           = 10\n\n# By default doxygen will tell dot to use the default font as specified with\n# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set\n# the path where dot can find it using this tag.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTPATH           =\n\n# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for\n# each documented class showing the direct and indirect inheritance relations.\n# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCLASS_GRAPH            = YES\n\n# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a\n# graph for each documented class showing the direct and indirect implementation\n# dependencies (inheritance, containment, and class references variables) of the\n# class with other documented classes.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCOLLABORATION_GRAPH    = YES\n\n# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for\n# groups, showing the direct groups dependencies.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGROUP_GRAPHS           = YES\n\n# If the UML_LOOK tag is set to YES doxygen will generate inheritance and\n# collaboration diagrams in a style similar to the OMG's Unified Modeling\n# Language.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LOOK               = NO\n\n# If the UML_LOOK tag is enabled, the fields and methods are shown inside the\n# class node. If there are many fields or methods and many nodes the graph may\n# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the\n# number of items for each type to make the size more manageable. Set this to 0\n# for no limit. Note that the threshold may be exceeded by 50% before the limit\n# is enforced. So when you set the threshold to 10, up to 15 fields may appear,\n# but if the number exceeds 15, the total amount of fields shown is limited to\n# 10.\n# Minimum value: 0, maximum value: 100, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LIMIT_NUM_FIELDS   = 10\n\n# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and\n# collaboration graphs will show the relations between templates and their\n# instances.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nTEMPLATE_RELATIONS     = NO\n\n# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to\n# YES then doxygen will generate a graph for each documented file showing the\n# direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDE_GRAPH          = YES\n\n# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are\n# set to YES then doxygen will generate a graph for each documented file showing\n# the direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDED_BY_GRAPH      = YES\n\n# If the CALL_GRAPH tag is set to YES then doxygen will generate a call\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable call graphs for selected\n# functions only using the \\callgraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALL_GRAPH             = NO\n\n# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable caller graphs for selected\n# functions only using the \\callergraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALLER_GRAPH           = NO\n\n# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical\n# hierarchy of all classes instead of a textual one.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGRAPHICAL_HIERARCHY    = YES\n\n# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the\n# dependencies a directory has on other directories in a graphical way. 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Tested\n# and working are Firefox, Chrome, Safari, and Opera.\n# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make\n# the SVG files visible. Older versions of IE do not have SVG support.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINTERACTIVE_SVG        = NO\n\n# The DOT_PATH tag can be used to specify the path where the dot tool can be\n# found. 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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/MISRA.txt",
    "content": "/** \\page coreMISRA_Exceptions_pg MISRA-C Deviations\nCMSIS-Core (Cortex-M) uses the common coding rules for CMSIS components that are documented under \n\\ifnot FuSaRTS <a href=\"../../General/html/index.html\"><b>Introduction</b></a> \\endif \\if FuSaRTS <a href=\"../../Safety/html/index.html#CodingRules\"><b>Coding Rules</b></a> \\endif.\n*/\n\n/*  MISRA-C:2004 no longer included in build\nCMSIS-Core (Cortex-M) violates the following MISRA-C:2004 rules:\n  \n- Required Rule 8.5, object/function definition in header file.<br>\n  Violated since function definitions in header files are used for function inlining'. \n   \n- Advisory Rule 12.4, Side effects on right hand side of logical operator.<br>\n  Violated because volatile is used for core register definitions. \n   \n- Advisory Rule 14.7, Return statement before end of function.<br>\n  Violated to simplify code logic. \n\n- Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n  Violated since unions are used for effective representation of core registers.\n   \n- Advisory Rule 19.4, Disallowed definition for macro.<br>\n  Violated since macros are used for assembler keywords. \n   \n- Advisory Rule 19.7, Function-like macro defined.<br>\n  Violated since function-like macros are used to generate more efficient code. \n   \n- Advisory Rule 19.16, all preprocessing directives must be valid.<br>\n  Violated to set default settings for macros. \n*/\n\n/**\nCMSIS-Core (Cortex-M) violates the following MISRA-C:2012 rules:\n  \n- Directive 4.9, function-like macro defined.<br>\n  Violated since function-like macros are used to generate more efficient code. \n   \n- Rule 1.3, multiple use of '#/##' operators in macro definition.<br>\n  Violated since function-like macros are used to generate more efficient code. \n   \n- Rule 11.4, conversion between a pointer and integer type.<br>\n  Violated because of core register access. \n   \n- Rule 11.6, cast from unsigned long to pointer.<br>\n  Violated because of core register access. \n   \n- Rule 13.5, side effects on right hand side of logical operator.<br>\n  Violated because of shift operand is used in macros and functions. \n   \n- Rule 14.4, conditional expression should have essentially Boolean type.<br>\n  Violated since macros with several instructions are used.\n  \n- Rule 15.5, return statement before end of function.<br>\n  Violated to simplify code logic. \n\n- Rule 20.10, '#/##' operators used.<br>\n  Violated since function-like macros are used to generate more efficient code. \n   \n- Rule 21.1, reserved to the compiler.<br>\n  Violated since macros with leading underscores are used. \n   \n\n  \n&lt;device&gt;.h files generated by <b>SVDConv.exe</b> violate the following MISRA-C:2004 rules:\n\n- Advisory Rule 20.2, Re-use of C90 identifier pattern.<br>\n  Violated since CMSIS macros begin with '__'. Since CMSIS is developed and verified with various compilers this approach is acceptable and avoids conflicts with user symbols. \n\n- Advisory Rule 19.1, Declaration before \\#include.<br>\n  Violated since Interrupt Number Definition Type (IRQn_Type) must be defined before including the core header file. \n */\n   "
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Overview.txt",
    "content": "/** \\mainpage Overview\n\nCMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals.\nIn detail it defines:\n - <b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized  definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.\n - <b>System exception names</b> to interface to system exceptions without having compatibility issues.\n - <b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.\n - <b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.\n - <b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.\n - A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.\n\n\nThe following sections provide details about the CMSIS-Core (Cortex-M):\n - \\ref using_pg describes the project setup and shows a simple program example.\n\\if ARMv8M\n - \\ref using_TrustZone_pg \"Using TrustZone&reg; for Armv8-M\" describes how to use the security extensions available in the Armv8-M architecture.\n\\endif\n - \\ref templates_pg describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.\n - \\ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.\n - <a href=\"modules.html\">\\b Reference </a> describe the features and functions of the \\ref device_h_pg in detail.\n - <a href=\"annotated.html\">\\b Data \\b Structures </a> describe the data structures of the \\ref device_h_pg in detail.\n\n<hr>\n\nCMSIS-Core (Cortex-M) in ARM::CMSIS Pack\n-----------------------------\n\nFiles relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories:\n|File/Folder                   |Content                                                                 |\n|------------------------------|------------------------------------------------------------------------|\n|\\b CMSIS\\\\Documentation\\\\Core | This documentation                                                     |\n|\\b CMSIS\\\\Core\\\\Include       | CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) |\n|\\b Device                     | \\ref using_ARM_pg \"Arm reference implementations\" of Cortex-M devices  |\n|\\b Device\\\\\\_Template_Vendor  | \\ref templates_pg for extension by silicon vendors                     |\n\n<hr>\n\n\\section ref_v6-v8M Processor Support\n\nCMSIS supports the complete range of <a href=\"https://developer.arm.com/products/processors/cortex-m\" target=\"_blank\"><b>Cortex-M processors</b></a> and\nthe <a href=\"https://developer.arm.com/architectures/cpu-architecture/m-profile\" target=\"_blank\"><b>Armv8-M/v8.1-M architecture</b></a> including security extensions.\n\n\\subsection ref_man_sec Cortex-M Generic User Guides\n\nThe Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:\n\n- <a href=\"https://developer.arm.com/documentation/dui0497/latest/\" target=\"_blank\"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)\n- <a href=\"https://developer.arm.com/documentation/dui0662/latest/\"  target=\"_blank\"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)\n- <a href=\"https://developer.arm.com/documentation/dui0552/latest/\"  target=\"_blank\"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)\n- <a href=\"https://developer.arm.com/documentation/dui0553/latest/\"  target=\"_blank\"><b>Cortex-M4 Devices Generic User Guide</b></a> (Armv7-M architecture)\n- <a href=\"https://developer.arm.com/documentation/dui0646/latest/\"  target=\"_blank\"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)\n- <a href=\"https://developer.arm.com/documentation/dui1095/latest/\"  target=\"_blank\"><b>Cortex-M23 Devices Generic User Guide</b></a> (Armv8-M architecture)\n- <a href=\"https://developer.arm.com/documentation/100235/latest/\"   target=\"_blank\"><b>Cortex-M33 Devices Generic User Guide</b></a> (Armv8-M architecture)\n- <a href=\"https://developer.arm.com/documentation/101273/latest/\"   target=\"_blank\"><b>Cortex-M55 Devices Generic User Guide</b></a> (Armv8.1-M architecture)\n- <a href=\"https://developer.arm.com/documentation/101928/latest\"   target=\"_blank\"><b>Cortex-M85 Devices Generic User Guide</b></a> (Armv8.1-M architecture)\n\nCMSIS also supports the following Cortex-M processor variants:\n- <a href=\"https://developer.arm.com/products/processors/cortex-m/cortex-m1\"       target=\"_blank\"><b>Cortex-M1</b></a> is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).\n- <a href=\"https://developer.arm.com/products/processors/cortex-m/sc000-processor\" target=\"_blank\"><b>SecurCore SC000</b></a> is designed specifically for smartcard and security applications (Armv6-M architecture).\n- <a href=\"https://developer.arm.com/products/processors/cortex-m/sc300-processor\" target=\"_blank\"><b>SecurCore SC300</b></a> is designed specifically for smartcard and security applications (Armv7-M architecture).\n- <a href=\"https://developer.arm.com/products/processors/cortex-m/cortex-m35p\"     target=\"_blank\"><b>Cortex-M35P</b></a> is a tamper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.\n- <a href=\"https://www.armchina.com/mountain?infoId=160\"                           target=\"_blank\"><b>STAR-MC1</b></a> is a variant of Armv8-M with TrustZone designed by Arm China.\n\n\n\\subsection ARMv8M Armv8-M and Armv8.1-M Architecture\n\nArmv8-M introduces two profiles \\b baseline (for power and area constrained applications) and \\b mainline (full-featured with optional SIMD, floating-point, and co-processor extensions).\nBoth Armv8-M profiles and Armv8.1-M are supported by CMSIS.\n\nThe Armv8-M architecture is described in the <a href=\"https://developer.arm.com/documentation/ddi0553/latest/\" target=\"_blank\"><b>Armv8-M Architecture Reference Manual</b></a>.\n\nThe Armv8.1-M architecture further extends Armv8-M with Helium (the so called M-Profile Vector Extension (MVE)), as well as further instruction set and debug extensions.\nMore information about Armv8.1-M architecture is available under <a href=\"https://developer.arm.com/technologies/helium\" target=\"_blank\"><b>Arm Helium technology</b></a>.\n\n<hr>\n\n\\section tested_tools_sec Tested and Verified Toolchains\n\nThe \\ref templates_pg supplied by Arm have been tested and verified with the following toolchains:\n - Arm: Arm Compiler 5.06 update 7 (not for Cortex-M23/33/35P/55/85, Armv8-M, Armv8.1-M)\n - Arm: Arm Compiler 6.16\n - Arm: Arm Compiler 6.6.4 (not for Cortex-M0/23/33/35P/55/85, Armv8-M, Armv8.1-M)\n - GNU: GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)\n - IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\n\\page core_revisionHistory Revision History of CMSIS-Core (Cortex-M)\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>V5.7.0</td>\n      <td>\n        <ul>\n          <li>Added: Added new compiler macros __ALIAS and __NO_INIT</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.6.0</td>\n      <td>\n        <ul>\n          <li>Added: Arm Cortex-M85 cpu support</li>\n          <li>Added: Arm China Star-MC1 cpu support</li>\n          <li>Updated: system_ARMCM55.c</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.5.0</td>\n      <td>\n        <ul>\n          <li>Updated GCC LinkerDescription, GCC Assembler startup</li>\n          <li>Added ARMv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC</li>\n          <li>Changed C-Startup to default Startup.</li>\n          </li>\n            Updated Armv8-M Assembler startup to use GAS syntax<br>\n            Note: Updating existing projects may need manual user interaction!\n          </li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.4.0</td>\n      <td>\n        <ul>\n\\if ARMv8M\n          <li>Added: Cortex-M55 cpu support</li>\n          <li>Enhanced: MVE support for Armv8.1-MML</li>\n\\endif\n          <li>Fixed: Device config define checks</li>\n          <li>Added: L1 Cache functions for Armv7-M and later</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.3.0</td>\n      <td>\n        <ul>\n          <li>Added: Provisions for compiler-independent C startup code.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.2.1</td>\n      <td>\n        <ul>\n          <li>Fixed: Compilation issue in cmsis_armclang_ltm.h introduced in 5.2.0</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.2.0</td>\n      <td>\n        <ul>\n          <li>Added: Cortex-M35P support.</li>\n          <li>Added: Cortex-M1 support.\n          <li>Added: Armv8.1 architecture support.\n          <li>Added: \\ref __RESTRICT and \\ref __STATIC_FORCEINLINE compiler control macros.\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.1.2</td>\n      <td>\n        <ul>\n          <li>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.</li>\n          <li>Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.</li>\n          <li>Added support for Cortex-M1 (beta).</li>\n          <li>Removed usage of register keyword.</li>\n          <li>Added defines for EXC_RETURN, FNC_RETURN and integrity signature values.</li>\n          <li>Enhanced MPUv7 API with defines for memory access attributes.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.1.1</td>\n      <td>\n        <ul>\n          <li>Aligned MSPLIM and PSPLIM access functions along supported compilers.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.1.0</td>\n      <td>\n        <ul>\n          <li>Added MPU Functions for ARMv8-M for Cortex-M23/M33.</li>\n          <li>Moved __SSAT and __USAT intrinsics to CMSIS-Core.</li>\n          <li>Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.0.2</td>\n      <td>\n        <ul>\n          <li>Added macros  \\ref \\__UNALIGNED_UINT16_READ,  \\ref \\__UNALIGNED_UINT16_WRITE.</li>\n          <li>Added macros  \\ref \\__UNALIGNED_UINT32_READ,  \\ref \\__UNALIGNED_UINT32_WRITE.</li>\n          <li>Deprecated macro  \\ref \\__UNALIGNED_UINT32.</li>\n          <li>Changed \\ref version_control_gr macros to be core agnostic.</li>\n          <li>Added \\ref mpu_functions for Cortex-M0+/M3/M4/M7.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.0.1</td>\n      <td>\n        <ul>\n          <li>Added: macro \\ref \\__PACKED_STRUCT.</li>\n          <li>Added: uVisor support.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.00</td>\n      <td>\n        <ul>\n          <li>Added: Cortex-M23, Cortex-M33 support.</li>\n          <li>Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>\n          <li>Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>\n          <li>Reworked: SAU register and functions.</li>\n          <li>Added: macro \\ref \\__ALIGNED.</li>\n          <li>Updated: function \\ref SCB_EnableICache.</li>\n          <li>Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions.</li>\n          <li>Added: macro \\ref \\__PACKED.</li>\n          <li>Updated: compiler specific include files.</li>\n          <li>Updated: core dependant include files.</li>\n          <li>Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.00<br>Beta 6</td>\n      <td>\n        <ul>\n          <li>Added: SCB_CFSR register bit definitions.</li>\n          <li>Added: function \\ref NVIC_GetEnableIRQ.</li>\n          <li>Updated: core instruction macros \\ref \\__NOP, \\ref \\__WFI, \\ref \\__WFE, \\ref \\__SEV for toolchain GCC.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.00<br>Beta 5</td>\n      <td>\n        <ul>\n          <li>Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.</li>\n          <li>Added: DSP libraries build projects to CMSIS pack.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.00<br>Beta 4</td>\n      <td>\n        <ul>\n          <li>Updated: ARMv8M device files.</li>\n          <li>Corrected: ARMv8MBL interrupts.</li>\n          <li>Reworked: NVIC functions.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.00<br>Beta 2</td>\n      <td>\n        <ul>\n\\if ARMv8M\n          <li>Changed: ARMv8M SAU regions to 8.</li>\n          <li>Changed: moved function \\ref TZ_SAU_Setup to file partition_&lt;device&gt;.h.</li>\n\\endif\n          <li>Changed: license under Apache-2.0.</li>\n          <li>Added: check if macro is defined before use.</li>\n          <li>Corrected: function \\ref SCB_DisableDCache.</li>\n          <li>Corrected: macros \\ref \\_VAL2FLD, \\ref \\_FLD2VAL.</li>\n          <li>Added: NVIC function virtualization with macros \\ref CMSIS_NVIC_VIRTUAL and \\ref CMSIS_VECTAB_VIRTUAL.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V5.00<br>Beta 1</td>\n      <td>\n        <ul>\n          <li>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.</li>\n          <li>Renamed: core\\_*.h to lower case.</li>\n          <li>Added: function \\ref SCB_GetFPUType to all CMSIS cores.</li>\n          <li>Added: ARMv8-M support.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V4.30</td>\n      <td>\n        <ul>\n          <li>Corrected: DoxyGen function parameter comments.</li>\n          <li>Corrected: IAR toolchain: removed for \\ref NVIC_SystemReset the attribute(noreturn).</li>\n          <li>Corrected: GCC toolchain: suppressed irrelevant compiler warnings.</li>\n          <li>Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V4.20</td>\n      <td>\n        <ul>\n          <li>Corrected: MISRA-C:2004 violations.</li>\n          <li>Corrected: predefined macro for TI CCS Compiler.</li>\n          <li>Corrected: function \\ref __SHADD16 in arm_math.h.</li>\n          <li>Updated: cache functions for Cortex-M7.</li>\n          <li>Added: macros \\ref _VAL2FLD, \\ref _FLD2VAL to core\\_*.h.</li>\n          <li>Updated: functions \\ref __QASX, \\ref __QSAX, \\ref __SHASX, \\ref __SHSAX.</li>\n          <li>Corrected: potential bug in function \\ref __SHADD16.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V4.10</td>\n      <td>\n        <ul>\n          <li>Corrected: MISRA-C:2004 violations.</li>\n          <li>Corrected: intrinsic functions \\ref __DSB, \\ref __DMB, \\ref __ISB.</li>\n          <li>Corrected: register definitions for ITCMCR register.</li>\n          <li>Corrected: register definitions for \\ref CONTROL_Type register.</li>\n          <li>Added: functions \\ref SCB_GetFPUType, \\ref SCB_InvalidateDCache_by_Addr to core_cm7.h.</li>\n          <li>Added: register definitions for \\ref APSR_Type, \\ref IPSR_Type, \\ref xPSR_Type register.</li>\n          <li>Added: \\ref __set_BASEPRI_MAX function to core_cmFunc.h.</li>\n          <li>Added: intrinsic functions \\ref __RBIT, \\ref __CLZ  for Cortex-M0/CortexM0+.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V4.00</td>\n      <td>\n        <ul>\n          <li>Added: Cortex-M7 support.</li>\n          <li>Added: intrinsic functions for \\ref __RRX, \\ref __LDRBT, \\ref __LDRHT, \\ref __LDRT, \\ref __STRBT, \\ref __STRHT, and \\ref __STRT</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V3.40</td>\n      <td>\n       <ul>\n         <li>Corrected: C++ include guard settings.</li>\n       </ul>\n     </td>\n    </tr>\n    <tr>\n      <td>V3.30</td>\n      <td>\n        <ul>\n          <li>Added: COSMIC tool chain support.</li>\n          <li>Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.</li>\n          <li>Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.</li>\n          <li>Corrected: GCC/CLang warnings.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V3.20</td>\n      <td>\n        <ul>\n          <li>Added: \\ref __BKPT instruction intrinsic.</li>\n          <li>Added: \\ref __SMMLA instruction intrinsic for Cortex-M4.</li>\n          <li>Corrected: \\ref ITM_SendChar.</li>\n          <li>Corrected: \\ref __enable_irq, \\ref __disable_irq and inline assembly for GCC Compiler.</li>\n          <li>Corrected: \\ref NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000.</li>\n          <li>Corrected: rework of in-line assembly functions to remove potential compiler warnings.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V3.01</td>\n      <td>\n       <ul>\n         <li>Added support for Cortex-M0+ processor.</li>\n       </ul>\n     </td>\n    </tr>\n    <tr>\n      <td>V3.00</td>\n      <td>\n        <ul>\n          <li>Added support for GNU GCC ARM Embedded Compiler.</li>\n          <li>Added function \\ref __ROR.</li>\n          <li>Added \\ref regMap_pg for TPIU, DWT.</li>\n          <li>Added support for \\ref core_config_sect \"SC000 and SC300 processors\".</li>\n          <li>Corrected \\ref ITM_SendChar function.</li>\n          <li>Corrected the functions \\ref __STREXB, \\ref __STREXH, \\ref __STREXW for the GNU GCC compiler section.</li>\n          <li>Documentation restructured.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V2.10</td>\n      <td>\n        <ul>\n          <li>Updated documentation.</li>\n          <li>Updated CMSIS core include files.</li>\n          <li>Changed CMSIS/Device folder structure.</li>\n          <li>Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.</li>\n          <li>Reworked CMSIS DSP library examples.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V2.00</td>\n      <td>\n       <ul>\n         <li>Added support for Cortex-M4 processor.</li>\n       </ul>\n     </td>\n    </tr>\n    <tr>\n      <td>V1.30</td>\n      <td>\n        <ul>\n          <li>Reworked Startup Concept.</li>\n          <li>Added additional Debug Functionality.</li>\n          <li>Changed folder structure.</li>\n          <li>Added doxygen comments.</li>\n          <li>Added definitions for bit.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V1.01</td>\n      <td>\n       <ul>\n         <li>Added support for Cortex-M0 processor.</li>\n       </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V1.01</td>\n      <td>\n       <ul>\n         <li>Added intrinsic functions for \\ref __LDREXB, \\ref __LDREXH, \\ref __LDREXW, \\ref __STREXB, \\ref __STREXH, \\ref __STREXW, and \\ref __CLREX</li>\n       </ul>\n     </td>\n    </tr>\n    <tr>\n      <td>V1.00</td>\n      <td>\n       <ul>\n         <li>Initial Release for Cortex-M3 processor.</li>\n       </ul>\n     </td>\n    </tr>\n</table>\n\n*/\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_CompilerControl.txt",
    "content": "/**************************************************************************************************/\n/**\n\\defgroup   compiler_conntrol_gr    Compiler Control\n\\brief      Compiler agnostic \\#define symbols for generic C/C++ source code\n\\details\nThe CMSIS-Core provides the header file <b>cmsis_compiler.h</b> with consistent \\#define symbols for generate C or C++ source files that should be compiler agnostic.\nEach CMSIS compliant compiler should support the functionality described in this section.\n\nThe header file <b>cmsis_compiler.h</b> is also included by each \\ref device_h_pg so that these definitions are available.\n@{\n*/\n\n/**\n\\def __ARM_ARCH_6M__\n\\brief Set to 1 when generating code for Armv6-M (Cortex-M0, Cortex-M1)\n\\details\nThe <b>\\#define __ARM_ARCH_6M__</b> is set to 1 when generating code for the Armv6-M architecture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor.\n*/\n#define __ARM_ARCH_6M__\n\n/**\n\\def __ARM_ARCH_7M__\n\\brief Set to 1 when generating code for Armv7-M (Cortex-M3)\n\\details\nThe <b>\\#define __ARM_ARCH_7M__</b> is set to 1 when generating code for the Armv7-M architecture. This architecture is for example used by the Cortex-M3 processor.\n*/\n#define __ARM_ARCH_7M__\n\n/**\n\\def __ARM_ARCH_7EM__\n\\brief Set to 1 when generating code for Armv7-M (Cortex-M4) with FPU\n\\details\nThe <b>\\#define __ARM_ARCH_7EM__</b> is set to 1 when generating code for the Armv7-M architecture with floating point extension. This architecture is for example used by the Cortex-M4 processor with FPU\n*/\n#define __ARM_ARCH_7EM__\n\n/**\n\\cond (ARMv8M)\n*/\n\n/**\n\\def __ARM_ARCH_8M_BASE__\n\\brief Set to 1 when generating code for Armv8-M Baseline\n\\details\nThe <b>\\#define __ARM_ARCH_8M_BASE__</b> is set to 1 when generating code for the Armv8-M architecture baseline variant.\n*/\n#define __ARM_ARCH_8M_BASE__\n\n/**\n\\def __ARM_ARCH_8M_MAIN__\n\\brief Set to 1 when generating code for Armv8-M Mainline\n\\details\nThe <b>\\#define __ARM_ARCH_8M_MAIN__</b> is set to 1 when generating code for the Armv8-M architecture mainline variant.\n*/\n#define __ARM_ARCH_8M_MAIN__\n\n/**\n\\endcond\n*/\n\n\n/**************************************************************************************************/\n/**\n\\def __ASM\n\\brief Pass information from the compiler to the assembler.\n\\details\nThe \\b __ASM keyword can declare or define an embedded assembly function or incorporate inline assembly into a function\n(shown in the code example below).\n\n<b>Code Example:</b>\n\\code\n// Reverse bit order of value\n\n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n   return(result);\n}\n\\endcode\n\n*/\n#define __ASM\n\n/**************************************************************************************************/\n/**\n\\def __INLINE\n\\brief Recommend that function should be inlined by the compiler.\n\\details\nInline functions offer a trade-off between code size and performance. By default, the compiler decides during optimization whether to\ninline code or not. The \\b __INLINE attribute gives the compiler an hint to inline this function. Still, the compiler may decide not to inline\nthe function.  As the function is global an callable function is also generated.\n\n<b>Code Example:</b>\n\\code\nconst uint32_t led_mask[] = {1U << 4, 1U << 5, 1U << 6, 1U << 7};\n\n/*------------------------------------------------------------------------------\n  Switch on LEDs\n *------------------------------------------------------------------------------*/\n__INLINE static void LED_On (uint32_t led) {\n\n  PTD->PCOR   = led_mask[led];\n}\n\\endcode\n\n*/\n#define __INLINE\n\n/**************************************************************************************************/\n/**\n\\def __STATIC_INLINE\n\\brief Define a static function that may be inlined by the compiler.\n\\details\nDefines a static function that may be inlined by the compiler. If the compiler generates inline code for\nall calls to this functions, no additional function implementation is generated which may further optimize space.\n\n<b>Code Example:</b>\n\\code\n\\\\ Get Interrupt Vector\n__STATIC_INLINE uint32_t NVIC_GetVector(IRQn_Type IRQn)\n{\n    uint32_t *vectors = (uint32_t *)SCB->VTOR;\n    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\\endcode\n\n*/\n#define __STATIC_INLINE\n\n/**************************************************************************************************/\n/**\n\\def __STATIC_FORCEINLINE\n\\brief Define a static function that should be always inlined by the compiler.\n\\details\nDefines a static function that should be always inlined by the compiler.\n\n\\note\nFor compilers that do not allow to force function inlining, the macro maps to \\ref __STATIC_INLINE.\n\n<b>Code Example:</b>\n\\code\n\\\\ Get Interrupt Vector\n__STATIC_FORCEINLINE uint32_t NVIC_GetVector(IRQn_Type IRQn)\n{\n    uint32_t *vectors = (uint32_t *)SCB->VTOR;\n    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\\endcode\n\n*/\n#define __STATIC_FORCEINLINE\n\n/**************************************************************************************************/\n/**\n\\def __NO_RETURN\n\\brief Inform the compiler that a function does not return.\n\\details\nInforms the compiler that the function does not return. The compiler can then perform optimizations by\nremoving code that is never reached.\n\n<b>Code Example:</b>\n\\code\n// OS idle demon (running when no other thread is ready to run).\n\n__NO_RETURN void os_idle_demon (void);\n\\endcode\n\n*/\n#define __NO_RETURN\n\n/**************************************************************************************************/\n/**\n\\def __RESTRICT\n\\brief restrict pointer qualifier to enable additional optimizations.\n\\details\nThe __RESTRICT keyword corresponds to the \\b restrict pointer qualifier that has been introduced in C99.\n__RESTRICT is a hint to the compiler that enables additional optimizations. It specifies that for the lifetime\nof the pointer, only the pointer itself or a value directly derived from it (such as pointer + 1) is used to access\nthe object. The compiler may therefore ignore potential pointer aliasing effects and perform additional optimizations.\n\n\\note\nFor compilers that do not support the restrict keyword, __RESTRICT is defined as an empty macro and a warning is issued.\n\n<b>Code Example:</b>\n\\code\n__STATIC_INLINE void ARM_MPU_OrderedMemcpy (volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i)\n  {\n    dst[i] = src[i];   // Since src is restrict, the compiler can assume that dst and src are not overlapping may load multiple values at a time\n  }\n}\n\\endcode\n\n*/\n#define __RESTRICT\n\n/**************************************************************************************************/\n/**\n\\def __USED\n\\brief Inform that a variable shall be retained in executable image.\n\\details\nDefinitions tagged with \\b __USED in the source code should be not removed by the linker when detected as unused.\n\n<b>Code Example:</b>\n\\code\n/* Export following variables for debugging */\n__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;\n__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;\n__USED uint32_t const os_clockrate = OS_TICK;\n__USED uint32_t const os_timernum  = 0;\n\\endcode\n\n*/\n#define __USED\n\n/**************************************************************************************************/\n/**\n\\def __WEAK\n\\brief Export a function or variable weakly to allow overwrites.\n\\details\nFunctions defined with \\b __WEAK export their symbols weakly. A weakly defined function behaves like a normally defined\nfunction unless a non-weakly defined function of the same name is linked into the same image. If both a non-weakly defined\nfunction and a weakly defined function exist in the same image then all calls to the function resolve to call the non-weak\nfunction.\n\nFunctions declared with \\b __WEAK and then defined without \\b __WEAK behave as non-weak functions.\n\n<b>Code Example:</b>\n\\code\n__WEAK void SystemInit(void)\n{\n  SystemCoreSetup();\n  SystemCoreClockSetup();\n}\n\\endcode\n\n*/\n#define __WEAK\n\n/**************************************************************************************************/\n/**\n\\def __PACKED\n\\brief Request smallest possible alignment.\n\\details\nSpecifies that a type must have the smallest possible alignment.\n\n<b>Code Example:</b>\n\\code\nstruct foo {\n  uint8_t  u8;\n  uint32_t u32[2] __PACKED;\n};\n\\endcode\n\n*/\n#define __PACKED\n\n/**************************************************************************************************/\n/**\n\\def __PACKED_STRUCT\n\\brief Request smallest possible alignment for a structure.\n\\details\nSpecifies that a structure must have the smallest possible alignment.\n\n<b>Code Example:</b>\n\\code\n__PACKED_STRUCT foo {\n  uint8_t   u8;\n  uint32_t  u32;\n  uint16_t  u16;\n};\n\\endcode\n\n*/\n#define __PACKED_STRUCT\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT32\n\\brief Pointer for unaligned access of a uint32_t variable.\n\\deprecated\nDo not use this macro.\nIt has been superseded by \\ref __UNALIGNED_UINT32_READ, \\ref __UNALIGNED_UINT32_WRITE and will be removed in the future.\n\\details\nDefines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n\n<b>Code Example:</b>\n\\code\nuint32_t val32;\n\nvoid test (uint8_t *ptr) {\n  __UNALIGNED_UINT32(ptr) = val32;\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT32\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT16_READ\n\\brief Pointer for unaligned read of a uint16_t variable.\n\\details\nDefines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in read\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n\n<b>Code Example:</b>\n\\code\nuint16_t val16;\n\nvoid test (uint8_t *ptr) {\n   val16 = __UNALIGNED_UINT16_READ(ptr);\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT16_READ\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT16_WRITE\n\\brief Pointer for unaligned write of a uint16_t variable.\n\\details\nDefines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in write\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n\n<b>Code Example:</b>\n\\code\nuint16_t val16 = 0U;\n\nvoid test (uint8_t *ptr) {\n   __UNALIGNED_UINT16_WRITE(ptr, val16);\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT16_WRITE\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT32_READ\n\\brief Pointer for unaligned read of a uint32_t variable.\n\\details\nDefines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n\n<b>Code Example:</b>\n\\code\nuint32_t val32;\n\nvoid test (uint8_t *ptr) {\n   val32 = __UNALIGNED_UINT32_READ(ptr);\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT32_READ\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT32_WRITE\n\\brief Pointer for unaligned write of a uint32_t variable.\n\\details\nDefines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in write\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n\n<b>Code Example:</b>\n\\code\nuint32_t val32 = 0U;\n\nvoid test (uint8_t *ptr) {\n   __UNALIGNED_UINT32_WRITE(ptr, val32);\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT32_WRITE\n\n/**************************************************************************************************/\n/**\n\\def __ALIGNED\n\\brief Minimum alignment for a variable.\n\\details\nSpecifies a minimum alignment for a variable or structure field, measured in bytes.\n\n<b>Code Example:</b>\n\\code\nuint32_t stack_space[0x100] __ALIGNED(8);   // 8-byte alignment required\n\\endcode\n\n*/\n#define __ALIGNED\n\n/**************************************************************************************************/\n/**\n\\def __COMPILER_BARRIER\n\\brief Barrier to prevent compiler from reordering instructions.\n\\details\nThis barrier limits the compilers reordering optimizations. It prevents the compiler from swapping\ninstructions resulting from code before and after the barrier.\n\n<b>Code Example:</b>\nThe assignments in the example are independent. Hence the compiler could choose a different order of\nexecution, e.g. for a better pipeline utilization. Using the barrier in between prevents this type\nof reordering.\n\n\\code\nvoid test (uint8_t *ptr) {\n  var1 = 1;\n  __COMPILE_BARRIER();\n  var2 = var3 + 1;\n}\n\\endcode\n\n*/\n#define __COMPILER_BARRIER\n\n/**************************************************************************************************/\n/**\n\\def __NO_INIT\n\\brief Force symbol into uninitialized memory section\n\\details\nThis puts a symbol (such as a variable) into an uninitialized memory section (e.g, .bss.noinit).\n\n<b>Code Example:</b>\nThe EventBuffer in the example does not need to be copy- or zero-initialized. By adding\n__NO_INIT this variable is allocated into an uninitialized memory section.\n\n\\code\nstatic EventRecord_t EventBuffer[EVENT_RECORD_COUNT] __NO_INIT __ALIGNED(16);\n\\endcode\n\n*/\n#define __NO_INIT\n\n/**************************************************************************************************/\n/**\n\\def __ALIAS\n\\brief Creates a symbol as alias to another symbol.\n\n<b>Code Example:</b>\nThe example declares the function Interrupt0_Handler. By default it is just an alias\npointing to Default_Handler. In combination with __WEAK modifier this allows giving\nthe function definition at a later point if required.\n\n\\code\nvoid Interrupt0_Handler     (void) __WEAK __ALIAS(\"Default_Handler\");\n\\endcode\n\n*/\n#define __ALIAS\n\n\n/**************************************************************************************************/\n/**\n\\def __PROGRAM_START\n\\brief Entry function into the user application or library startup.\n\\details\nGives the function to be jumped into right after low level initialization, i.e. SystemInit. This\nis compiler and library specific. CMSIS specifies common default for supported compilers.\n\n\\note This define is only intended to be used by the \\ref startup_c_pg.\n\n<b>Code Example:</b>\n\\code\nvoid Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\\endcode\n*/\n#define __PROGRAM_START\n\n/**************************************************************************************************/\n/**\n\\def __INITIAL_SP\n\\brief Compiler/linker symbol specifying the location of the main stack (MSP).\n\\details\nThe address of the specified symbol is used to initialize the main stack pointer (MSP) during low\nlevel init. This is compiler/linker specific. CMSIS specifies common default for supported compilers.\n\n\\note This define is only intended to be used by the \\ref startup_c_pg.\n*/\n#define __INITIAL_SP\n\n/**************************************************************************************************/\n/**\n\\def __STACK_LIMIT\n\\brief Compiler/linker symbol specifying the limit of the main stack (MSP).\n\\details\nThe address of the specified symbol is used to initialize the main stack pointer limit (MSPLIM on Armv8-M)\nduring low level init. This is compiler/linker specific. CMSIS specifies common default for supported\ncompilers.\n\n\\note This define is only intended to be used by the \\ref startup_c_pg.\n\n<b>Code Example:</b>\n\\code\nvoid Reset_Handler(void)\n{\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  // :\n  // :\n}\n\\endcode\n*/\n#define __STACK_LIMIT\n\n/**************************************************************************************************/\n/**\n\\def __VECTOR_TABLE\n\\brief Symbol name used for the (static) interrupt vector table.\n\\details\nThe given name is used for defining the static (compiler time) interrupt vector table. The name\nmust comply with any compiler/linker conventions, e.g. if used for vector table relocation or debugger\nawareness. CMSIS specifies common default for supported compilers.\n\n\\note This define is only intended to be used by the \\ref startup_c_pg.\n*/\n#define __VECTOR_TABLE\n\n/**************************************************************************************************/\n/**\n\\def __VECTOR_TABLE_ATTRIBUTE\n\\brief Additional decl specs to be used when defining the (static) interrupt vector table.\n\\details\nThe given decl specs are used for defining the static (compiler time) interrupt vector table, e.g.\nto mark the table as used and force it into a specific linker section. CMSIS specifies common default\nfor supported compilers.\n\n\\note This define is only intended to be used by the \\ref startup_c_pg.\n*/\n#define __VECTOR_TABLE_ATTRIBUTE\n\n/** @} */ /** end of compiler_conntrol_gr **/"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt",
    "content": "/**************************************************************************************************/\n/** \\defgroup Core_Register_gr Core Register Access\n\\brief Functions to access the Cortex-M core registers.\n\\details\n  The following functions provide access to Cortex-M core registers. \n\n  @{ \n*/\n\n\n/**************************************************************************************************/\n/** \\brief  Read the CONTROL register\n    \\details\n    The function reads the CONTROL register value using the instruction \\b MRS. \n    \\n\\n\n    The CONTROL register controls the stack used and the privilege level for software execution\n    when the processor is in thread mode and, if implemented, indicates whether the FPU state is\n    active. This register uses the following bits:\n    \\n\n    - \\b CONTROL[2] [only Cortex-M4 and Cortex-M7]\n        - =0 FPU not active\n        - =1 FPU active\n        \\n\\n\n    - \\b CONTROL[1] \n        - =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.\n        - =0 In thread mode - Default stack pointer MSP is used.\n        - =1 In thread mode - Alternate stack pointer PSP is used.\n        \\n\\n\n    - \\b CONTROL[0] [not Cortex-M0]\n        - =0 In thread mode and privileged state.\n        - =1 In thread mode and user state.\n     \n    \\returns    CONTROL register value\n    \n    \\remarks    \n            - The processor can be in user state or privileged state when running in thread mode.\n            - Exception handlers always run in privileged state.\n            - On reset, the processor is in thread mode with privileged access  rights.\n    \n    \\sa     \n            - \\ref __set_CONTROL; CONTROL_Type \n            - \\ref ref_man_sec\n */\nuint32_t __get_CONTROL(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Set the CONTROL Register\n    \\details \n    The function sets the CONTROL register value using the instruction \\b MSR. \n    \\n\\n\n    The CONTROL register controls the stack used and the privilege level for software execution\n    when the processor is in thread mode and, if implemented, indicates whether the FPU state is\n    active. This register uses the following bits:\n    \\n\n    - \\b CONTROL[2] [only Cortex-M4 and Cortex-M7]\n        - =0 FPU not active\n        - =1 FPU active\n        \\n\\n\n    - \\b CONTROL[1] \n        - Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).\n        - =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.\n        - =0 In thread mode - Default stack pointer MSP is used.\n        - =1 In thread mode - Alternate stack pointer PSP is used.\n        \\n\\n\n    - \\b CONTROL[0] [not writeable for Cortex-M0]\n        - Writeable only when the processor is in privileged state.\n        - Can be used to switch the processor to user state (thread mode).\n        - Once in user state, trigger an interrupt and change the state to privileged in the \n        exception handler (the only way).\n        - =0 In thread mode and privileged state.\n        - =1 In thread mode and user state.\n\n     \n    \\param [in] control  CONTROL register value to set    \n    \n    \\remarks    \n            - The processor can be in user state or privileged state when running in thread mode.\n            - Exception handlers always run in privileged state.\n            - On reset, the processor is in thread mode with privileged access  rights.\n\n    \\sa     \n            - \\ref __get_CONTROL; __set_PSP; __set_MSP; CONTROL_Type \n            - \\ref ref_man_sec\n*/\nvoid __set_CONTROL(uint32_t control);\n\n\n/**************************************************************************************************/\n/** \\brief  Read the IPSR register\n    \\details \n    The function reads the Interrupt Program Status Register (IPSR) using the instruction \\b MRS. \n    \\n\\n\n    The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). \n    Each exception has an associated unique IRQn number. The following bits are used:\n    \n    - \\b ISR_NUMBER (IPSR[8:0])\n        - = 0 Thread mode\n        - = 1 Reserved\n        - = 2 NMI\n        - = 3 HardFault\n        - = 4 MemManage\n        - = 5 BusFault\n        - = 6 UsageFault\n        - = 7 SecureFault\n        - = 8-10  Reserved\n        - = 11 SVC\n        - = 12 Reserved for Debug\n        - = 13 Reserved\n        - = 14 PendSV\n        - = 15 SysTick\n        - = 16 IRQ0\n        - ...\n        - = n+15 IRQ(n-1)\n\n    \\returns    ISPR register value\n\n    \\remarks    \n            - This register is read-only.\n\n    \\sa     \n            - \\ref __get_xPSR; IPSR_Type\n            - \\ref NVIC_gr\n            - \\ref ref_man_sec\n*/\nuint32_t __get_IPSR(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Read the APSR register\n    \\details\n    The function reads the Application Program Status Register (APSR) using the instruction \\b MRS.\n    \\n\\n\n    The APSR contains the current state of the condition flags from instructions executed previously.\n    The APSR is essential for controlling conditional branches. The following flags are used:\n    \n    - \\b N (APSR[31]) (Negative flag)\n        - =1 The instruction result has a negative value (when interpreted as signed integer).\n        - =0 The instruction result has a positive value or equal zero.\n    \\n\\n\n    - \\b Z (APSR[30]) (Zero flag)\n        - =1 The instruction result is zero. Or, after a compare instruction, when the two values\n            are the same.\n    \\n\\n\n    - \\b C (APSR[29]) (Carry or borrow flag)\n        - =1 For unsigned additions, if an unsigned overflow occurred.\n        - =<i>inverse of borrow output status</i> For unsigned subtract operations.\n    \\n\\n\n    - \\b V (APSR[28]) (Overflow flag)\n        - =1 A signed overflow occurred (for signed additions or subtractions).\n    \\n\\n\n    - \\b Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]\n        - This flag is a \\em sticky flag. Saturating and certain multiplying instructions can set the\n        flag, but cannot clear it. \n        - =1 When saturation or an overflow occurred.\n    \\n\\n\n    - \\b GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]\n        - Can be set by the parallel add and subtract instructions.\n        - Are used by the <kbd>SEL</kbd> instruction to perform byte-based selection from two registers.\n    \n    \n    \\returns    APSR register value\n\n    \\remarks    \n            - Some instructions update all flags; some instructions update a subset of the flags. \n            - If a flag is not updated, the original value is preserved. \n            - Conditional instructions that are not executed have no effect on the flags.\n            - The CMSIS does not provide a function to update this register.\n\n    \\sa     \n            - \\ref __get_xPSR; APSR_Type \n            - \\ref ref_man_sec\n\n */\nuint32_t __get_APSR(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Read the xPSR register \n    \\details \n    The function reads the combined Program Status Register (xPSR) using the instruction \\b MRS. \n    \\n\\n\n    xPSR provides information about program execution and the APSR flags. It consists of the \n    following PSRs:\n    \\li Application Program Status Register (APSR)\n    \\li Interrupt Program Status Register (IPSR)\n    \\li Execution Program Status Register (EPSR)\n    \n    In addition to the flags described in \\ref __get_APSR and \\ref __get_IPSR, the register provides \n    the following flags:\n    - \\b IT (xPSR[26:25]) (If-Then condition instruction)\n        - Contains up to four instructions following an IT instruction. \n        - Each instruction in the block is conditional. \n        - The conditions for the instructions are either all the same, or some can be the inverse \n        of others.\n    \\n\\n\n    - \\b T (xPSR[24]) (Thumb bit) \n        - =1 Indicates that that the processor is in Thumb state. \n        - =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup. \n        - The conditions for the instructions are either all the same, or some can be the inverse \n        of others.\n    \n    \\returns    xPSR register value \n    \n    \\remarks\n        - The CMSIS does not provide functions that access EPSR.\n\n    \\sa     \n            - \\ref __get_APSR; __get_IPSR; xPSR_Type\n            - \\ref ref_man_sec\n    \n */\nuint32_t __get_xPSR(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Read the PSP register\n    \\details \n    The function reads the Process Stack Pointer (PSP) value using the instruction \\b MRS.\n    \\n\\n\n    Physically two different stack pointers (SP) exist: \n    - The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when \n    running exception handlers (handler mode).\n    - The Process Stack Pointer (PSP), which can be used only in thread mode. \n    \n    Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register: \n    - =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded \n    from the first 32-bit word of the vector table from the program memory.\n    - =1 PSP is the current stack pointer. The initial value is undefined. \n  \n    \\returns    PSP register value\n        \n    \\remarks\n        - Only one of the two SPs is visible at a time.\n        - For many applications, the system can completely rely on the MSP.\n        - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must \n        be separated from the application code.  \n\n    \\sa \n        - \\ref __set_PSP; __get_MSP; __get_CONTROL\n        - \\ref ref_man_sec\n\n    \n */\nuint32_t __get_PSP(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Set the PSP register\n    \\details\n    The function sets the Process Stack Pointer (PSP) value using the instruction \\b MSR.\n    \\n\\n\n    Physically two different stack pointers (SP) exist: \n    - The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when \n    running exception handlers (handler mode).\n    - The Process Stack Pointer (PSP), which can be used only in thread mode. \n    \n    Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register: \n    - =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded \n    from the first 32-bit word of the vector table from the program memory.\n    - =1 PSP is the current stack pointer. The initial value is undefined. \n    \n    \\param [in]    topOfProcStack  PSP value to set\n        \n    \\remarks\n        - Only one of the two SPs is visible at a time.\n        - For many applications, the system can completely rely on the MSP.\n        - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must \n        be separated from the application code.  \n        \n    \\sa \n        - \\ref __get_PSP; __set_MSP; __set_CONTROL\n        - \\ref ref_man_sec\n */\nvoid __set_PSP(uint32_t topOfProcStack);\n\n\n/**************************************************************************************************/\n/** \\brief  Read the MSP register\n    \\details \n    The function reads the Main Stack Pointer (MSP) value using the instruction \\b MRS.\n    \\n\\n\n    Physically two different stack pointers (SP) exist: \n    - The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when \n    running exception handlers (handler mode).\n    - The Process Stack Pointer (PSP), which can be used only in thread mode. \n    \n    Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register: \n    - =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded \n    from the first 32-bit word of the vector table from the program memory.\n    - =1 PSP is the current stack pointer. The initial value is undefined. \n    \n    \\returns    MSP Register value \n\n    \\remarks\n        - Only one of the two SPs is visible at a time.\n        - For many applications, the system can completely rely on the MSP.\n        - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must \n        be separated from the application code.  \n        \n    \\sa \n        - \\ref __set_MSP; __get_PSP; __get_CONTROL\n        - \\ref ref_man_sec\n\n */\nuint32_t __get_MSP(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Set the MSP register\n    \\details \n    The function sets the Main Stack Pointer (MSP) value using the instruction \\b MSR.\n    \\n\\n\n    Physically two different stack pointers (SP) exist: \n    - The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when \n    running exception handlers (handler mode).\n    - The Process Stack Pointer (PSP), which can be used only in thread mode. \n    \n    Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register: \n    - =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded \n    from the first 32-bit word of the vector table from the program memory.\n    - =1 PSP is the current stack pointer. The initial value is undefined. \n    \n    \\param [in]    topOfMainStack  MSP value to set\n\n    \\remarks\n        - Only one of the two SPs is visible at a time.\n        - For many applications, the system can completely rely on the MSP.\n        - The PSP is normally used in designs with an OS where the stack memory for OS Kernel must \n        be separated from the application code.  \n        \n    \\sa \n        - \\ref __get_MSP; __set_PSP; __set_CONTROL\n        - \\ref ref_man_sec\n\n */\nvoid __set_MSP(uint32_t topOfMainStack);\n\n\n/**************************************************************************************************/\n/** \\brief  Read the PRIMASK register bit \n    \\details \n    The function reads the Priority Mask register (PRIMASK) value using the instruction \\b MRS. \n    \\n\\n\n    PRIMASK is a 1-bit-wide interrupt mask register. When set,\n    it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception.\n    The PRIMASK prevents activation of all exceptions with configurable priority.\n\n    \\returns    PRIMASK register value\n                - =0 no effect\n                - =1 prevents the activation of all exceptions with configurable priority\n           \n    \\sa \n        - \\ref __set_PRIMASK; __get_BASEPRI; __get_FAULTMASK\n        - \\ref ref_man_sec                    \n                    \n */\nuint32_t __get_PRIMASK(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Set the Priority Mask bit\n    \\details \n    The function sets the Priority Mask register (PRIMASK) value using the instruction \\b MSR. \n    \\n\\n\n    PRIMASK is a 1-bit-wide interrupt mask register. When set,\n    it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception.\n    The PRIMASK prevents activation of all exceptions with configurable priority.\n\n    \\param [in]    priMask  Priority Mask\n                    - =0 no effect\n                    - =1 prevents the activation of all exceptions with configurable priority\n\n    \\remarks\n        - When set, PRIMASK effectively changes the current priority level to 0. \n        This is the highest programmable level.\n        - When set and a fault occurs, the hard fault handler will be executed.\n        - Useful for temporarily disabling all interrupts for timing critical tasks. \n        - Does not have the ability to mask BusFault or bypass MPU.\n\n    \\sa \n        - \\ref __get_PRIMASK; __set_BASEPRI; __set_FAULTMASK\n        - \\ref ref_man_sec                    \n\n */\nvoid __set_PRIMASK(uint32_t priMask);\n \n\n/**************************************************************************************************/\n/** \\brief  Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]\n    \\details \n    The function returns the Base Priority Mask register (BASEPRI) using the instruction \\b MRS. \n    \\n\\n\n    BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero \n    value, it prevents the activation of all exceptions with the same or lower priority level as \n    the BASEPRI value.\n    \n    \\returns    BASEPRI register value\n\n    \\remarks    \n        - Not for Cortex-M0, Cortex-M0+, or SC000.\n                    \n    \\sa \n        - \\ref __set_BASEPRI;  __set_BASEPRI_MAX; __get_FAULTMASK; __get_PRIMASK\n        - \\ref ref_man_sec\n\n    */\nuint32_t __get_BASEPRI(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]\n    \\details \n    The function sets the Base Priority Mask register (BASEPRI) value using the instruction \\b MSR.\n    \\n\\n\n    BASEPRI defines the minimum priority for exception processing. \n    When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the \n    same or lower priority level as the BASEPRI value.\n    \n    \\param [in]    basePri  BASEPRI value to set\n\n    \\remarks    \n        - Not for Cortex-M0, Cortex-M0+, or SC000.\n        - Cannot be set in user state.\n        - Useful for changing the masking level or disabling the masking.\n\n    \\sa \n        - \\ref __get_BASEPRI;  __set_BASEPRI_MAX; __set_FAULTMASK; __set_PRIMASK\n        - \\ref ref_man_sec\n    \n */\nvoid __set_BASEPRI(uint32_t basePri); \n \n \n/**************************************************************************************************/\n/** \\brief  Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]\n    \\details \n    The function only increases the Base Priority Mask register (BASEPRI) value using the instruction \\b MSR.\n\tThe value is set only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level.\n    \\n\\n\n    BASEPRI defines the minimum priority for exception processing. \n        \n    \\param [in]    basePri  BASEPRI value to set\n\n    \\remarks    \n        - Not for Cortex-M0, Cortex-M0+, or SC000.\n        - Cannot be set in user state.\n        - Useful for increasing the masking level.\n        - Has no effect when \\em basePri is lower than the current value of BASEPRI.\n        - Use \\ref __set_BASEPRI to lower the Base Priority Mask register.\n\n    \\sa \n        - \\ref __set_BASEPRI; __get_BASEPRI; __set_FAULTMASK; __set_PRIMASK\n        - \\ref ref_man_sec\n    \n */\nvoid __set_BASEPRI_MAX(uint32_t basePri); \n\n\n/**************************************************************************************************/\n/** \\brief  Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]\n    \\details \n    The function reads the Fault Mask register (FAULTMASK) value using the instruction \\b MRS. \n    \\n\\n\n    FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).\n\n    \\returns    FAULTMASK register value\n\n    \\remarks    \n        - not for Cortex-M0, Cortex-M0+, or SC000.\n        - Is cleared automatically upon exiting the exception handler, except when returning \n        from the NMI handler.\n\n    \\sa \n        - \\ref __set_FAULTMASK; __get_BASEPRI; __get_PRIMASK \n        - \\ref ref_man_sec\n */\nuint32_t __get_FAULTMASK(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]\n    \\details \n    The function sets the Fault Mask register (FAULTMASK) value using the instruction \\b MSR.\n    \\n\\n\n    FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI).\n    FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or \n    memory management fault) to hard fault level without invoking a hard fault. This allows the \n    fault handler to pretend to be the hard fault handler, with the ability to:\n    -# <b>Mask BusFault</b> by setting the BFHFNMIGN in the Configuration Control register.\n    It can be used to test the bus system without causing a lockup. \n    -# <b>Bypass the MPU</b>, allowing accessing the MPU protected memory location without \n    reprogramming the MPU to just carry out a few transfers for fixing faults.\n\n    \\param [in]    faultMask  FAULTMASK register value to set \n\n    \\remarks    \n        - not for Cortex-M0, Cortex-M0+, or SC000.\n        - Is cleared automatically upon exiting the exception handler, except when returning \n        from the NMI handler.\n        - When set, it changes the effective current priority level to -1, so that even the hard\n        fault handler is blocked.\n        - Can be used by fault handlers to change their priority to -1 to have access to some \n        features for hard fault exceptions (see above).\n        - When set, lockups can still be caused by incorrect or undefined instructions, or by using\n        SVC in the wrong priority level.\n\n    \\sa \n        - \\ref __get_FAULTMASK; __set_BASEPRI; __set_PRIMASK \n        - \\ref ref_man_sec\n */\nvoid __set_FAULTMASK(uint32_t faultMask);\n\n\n/**************************************************************************************************/\n/** \\brief  Read the FPSCR register [only Cortex-M4 and Cortex-M7]\n    \\details \n    The function reads the Floating-Point Status Control Register (FPSCR) value. \n    \\n\\n\n    FPSCR provides all necessary User level controls of the floating-point system. \n        \n    \\returns    \n            - FPSCR register value, when __FPU_PRESENT=1\n            - =0, when __FPU_PRESENT=0\n\n    \\remarks\n            - Only for Cortex-M4 and Cortex-M7.\n                \n    \\sa \n            - \\ref __set_FPSCR\n            - \\ref ref_man_sec\n                    \n */\nuint32_t __get_FPSCR(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Set the FPSC register [only for Cortex-M4 and Cortex-M7]\n    \\details \n    The function sets the Floating-Point Status Control Register (FPSCR) value. \n    \\n\\n\n    FPSCR provides all necessary User level control of the floating-point system. \n    \\n\n    - \\b N (FPSC[31]) (Negative flag)\n        - =1 The instruction result has a negative value (when interpreted as signed integer).\n        - =0 The instruction result has a positive value or equal zero.\n    \\n\\n\n    - \\b Z (FPSC[30]) (Zero flag)\n        - =1 The instruction result is zero. Or, after a compare instruction, when the two values\n            are the same.\n    \\n\\n\n    - \\b C (FPSC[29]) (Carry or borrow flag)\n        - =1 For unsigned additions, if an unsigned overflow occurred.\n        - =<i>inverse of borrow output status</i> For unsigned subtract operations.\n    \\n\\n\n    - \\b V (FPSC[28]) (Overflow flag)\n        - =1 A signed overflow occurred (for signed additions or subtractions).\n    \\n\\n\n    - \\b AHP (FPSC[26]) (Alternative half-precision flag)\n        - =1 Alternative half-precision format selected.\n        - =0 IEEE half-precision format selected.\n    \\n\\n\n    - \\b DN (FPSC[25]) (Default NaN mode control flag)\n        - =1 Any operation involving one or more NaNs returns the Default NaN.\n        - =0 NaN operands propagate through to the output of a floating-point operation.\n    \\n\\n\n    - \\b FZ (FPSC[24]) (Flush-to-zero mode control flag)\n        - =1 Flush-to-zero mode enabled.\n        - =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully \n        compliant with the IEEE 754 standard.\n    \\n\\n\n    - \\b RMode (FPSC[23:22]) (Rounding Mode control flags)\n        - =0b00 Round to Nearest (RN) mode.\n        - =0b01 Round towards Plus Infinity (RP) mode.\n        - =0b10 Round towards Minus Infinity (RM) mode.\n        - =0b11 Round towards Zero (RZ) mode.\n        - The specified rounding mode is used by almost all floating-point instructions.\n    \\n\\n\n    - \\b IDC (FPSC[7]) (Input Denormal cumulative exception flags)\n        - See Cumulative exception bits (FPSC[4:0]).\n    \\n\\n\n    - \\b IXC (FPSC[4]) (Inexact cumulative exception flag)\n        - =1 Exception occurred. \n        - =0 Value has to be set explicitly. \n        - Flag is not cleared automatically.\n    \\n\\n\n    - \\b UFC (FPSC[3]) (Underflow cumulative exception flag)\n        - =1 Exception occurred. \n        - =0 Value has to be set explicitly. \n        - Flag is not cleared automatically.\n    \\n\\n\n    - \\b OFC (FPSC[2]) (Overflow cumulative exception flag)\n        - =1 Exception occurred. \n        - =0 Value has to be set explicitly. \n        - Flag is not cleared automatically.\n    \\n\\n\n    - \\b DZC (FPSC[1]) (Division by Zero cumulative exception flag)\n        - =1 Exception occurred. \n        - =0 Value has to be set explicitly. \n        - Flag is not cleared automatically.\n    \\n\\n\n    - \\b IOC (FPSC[0]) (Invalid Operation cumulative exception flag)\n        - =1 Exception occurred. \n        - =0 Value has to be set explicitly. \n        - Flag is not cleared automatically.\n        \n    \\param [in]    fpscr  FPSCR value to set\n\n    \\remarks\n            - Only for Cortex-M4 and Cortex-M7.\n            - The variable \\b __FPU_PRESENT has to be set to 1.\n    \n    \\sa \n            - \\ref __get_FPSCR\n            - \\ref ref_man_sec\n */\nvoid __set_FPSCR(uint32_t fpscr);\n\n\n/**************************************************************************************************/\n/** \\brief  Globally enables interrupts and configurable fault handlers\n    \\details\n    The function enables interrupts and all configurable fault handlers by clearing PRIMASK.\n    The function uses the instruction <b>CPSIE i</b>.\n\n    \\remarks\n            - Can be executed in privileged mode only. \n            \n    \\sa \n        - \\ref __disable_irq; __set_BASEPRI; __set_CONTROL; __set_PRIMASK\n */\nvoid __enable_irq(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Globally disables interrupts and configurable fault handlers\n    \\details \n    The function disables interrupts and all configurable fault handlers by setting PRIMASK. \n    The function uses the instruction <b>CPSID i</b>.\n\n    \\remarks\n        - Can be executed in privileged mode only. \n        - An interrupt can enter pending state even if it is disabled. Disabling an interrupt \n        only prevents the processor from taking that interrupt.\n\n    \\sa \n        - \\ref __enable_irq;  __set_BASEPRI; __set_CONTROL; __set_PRIMASK\n */\nvoid __disable_irq(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]\n    \\details \n    The function enables interrupts and all fault handlers by clearing FAULTMASK.\n    The function uses the instruction <b>CPSIE f</b>.\n\n    \\remarks\n            - not for Cortex-M0, Cortex-M0+, or SC000.\n            - Can be executed in privileged mode only. \n    \n    \\sa \n        - \\ref __disable_fault_irq; __set_BASEPRI; __set_CONTROL; __set_FAULTMASK\n */\n void __enable_fault_irq(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]\n    \\details \n    The function disables interrupts and all fault handlers by setting FAULTMASK.\n    The function uses the instruction <b>CPSID f</b>.\n\n    \\remarks\n        - not for Cortex-M0, Cortex-M0+, or SC000.\n        - Can be executed in privileged mode only. \n        - An interrupt can enter pending state even if it is disabled. Disabling an interrupt \n        only prevents the processor from taking that interrupt.\n\n    \\sa \n        - \\ref __enable_fault_irq; __set_BASEPRI; __set_CONTROL; __set_FAULTMASK\n */\nvoid __disable_fault_irq(void);\n\n/**\n\\cond (ARMv8M)\n*/\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n  \\note    Only available for Armv8-M Architecture. \n */\nuint32_t __get_PSPLIM(void);\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n  \\note    Only available for Armv8-M Architecture. \n */\nvoid __set_PSPLIM(uint32_t ProcStackPtrLimit);\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n  \\note    Only available for Armv8-M Architecture. \n */\nuint32_t __get_MSPLIM(void);\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n  \\note    Only available for Armv8-M Architecture. \n */\n__set_MSPLIM(uint32_t MainStackPtrLimit);\n\n/**\n\\endcond\n*/\n\n/** @} */ /** end of Core_Register_gr **/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_DataStructs.txt",
    "content": "/****************************    Data Structures    ***********************************************/\n/** \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n#if (__CORTEX_M != 0x04)\n    uint32_t _reserved0:27;              ///< bit:  0..26  Reserved\n#else\n    uint32_t _reserved0:16;              ///< bit:  0..15  Reserved\n    uint32_t GE:4;                       ///< bit: 16..19  Greater than or Equal flags\n    uint32_t _reserved1:7;               ///< bit: 20..26  Reserved\n#endif\n    uint32_t Q:1;                        ///< bit:     27  Saturation condition flag\n    uint32_t V:1;                        ///< bit:     28  Overflow condition code flag\n    uint32_t C:1;                        ///< bit:     29  Carry condition code flag\n    uint32_t Z:1;                        ///< bit:     30  Zero condition code flag\n    uint32_t N:1;                        ///< bit:     31  Negative condition code flag\n  } b;                                   ///< Structure used for bit  access\n  uint32_t w;                            ///< Type      used for word access\n} APSR_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      ///< bit:  0.. 8  Exception number\n    uint32_t _reserved0:23;              ///< bit:  9..31  Reserved\n  } b;                                   ///< Structure used for bit  access\n  uint32_t w;                            ///< Type      used for word access\n} IPSR_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      ///< bit:  0.. 8  Exception number\n#if (__CORTEX_M != 0x04)\n    uint32_t _reserved0:15;              ///< bit:  9..23  Reserved\n#else\n    uint32_t _reserved0:7;               ///< bit:  9..15  Reserved\n    uint32_t GE:4;                       ///< bit: 16..19  Greater than or Equal flags\n    uint32_t _reserved1:4;               ///< bit: 20..23  Reserved\n#endif\n    uint32_t T:1;                        ///< bit:     24  Thumb bit        (read 0)\n    uint32_t IT:2;                       ///< bit: 25..26  saved IT state   (read 0)\n    uint32_t Q:1;                        ///< bit:     27  Saturation condition flag\n    uint32_t V:1;                        ///< bit:     28  Overflow condition code flag\n    uint32_t C:1;                        ///< bit:     29  Carry condition code flag\n    uint32_t Z:1;                        ///< bit:     30  Zero condition code flag\n    uint32_t N:1;                        ///< bit:     31  Negative condition code flag\n  } b;                                   ///< Structure used for bit  access\n  uint32_t w;                            ///< Type      used for word access\n} xPSR_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    ///< bit:      0  Execution privilege in Thread mode\n    uint32_t SPSEL:1;                    ///< bit:      1  Stack to be used\n    uint32_t FPCA:1;                     ///< bit:      2  FP extension active flag\n    uint32_t _reserved0:29;              ///< bit:  3..31  Reserved\n  } b;                                   ///< Structure used for bit  access\n  uint32_t w;                            ///< Type      used for word access\n} CONTROL_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8];                ///< Offset: 0x000 (R/W)  Interrupt Set Enable Register\n        uint32_t RESERVED0[24];          ///< Reserved\n  __IOM uint32_t ICER[8];                ///< Offset: 0x080 (R/W)  Interrupt Clear Enable Register\n        uint32_t RSERVED1[24];           ///< Reserved\n  __IOM uint32_t ISPR[8];                ///< Offset: 0x100 (R/W)  Interrupt Set Pending Register\n        uint32_t RESERVED2[24];          ///< Reserved\n  __IOM uint32_t ICPR[8];                ///< Offset: 0x180 (R/W)  Interrupt Clear Pending Register\n        uint32_t RESERVED3[24];          ///< Reserved\n  __IOM uint32_t IABR[8];                ///< Offset: 0x200 (R/W)  Interrupt Active bit Register\n        uint32_t RESERVED4[56];          ///< Reserved\n  __IOM uint8_t  IP[240];                ///< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide)\n        uint32_t RESERVED5[644];         ///< Reserved\n  __OM  uint32_t STIR;                   ///< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register\n}  NVIC_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  ///< Offset: 0x000 (R/ )  CPUID Base Register\n  __IOM uint32_t ICSR;                   ///< Offset: 0x004 (R/W)  Interrupt Control and State Register\n  __IOM uint32_t VTOR;                   ///< Offset: 0x008 (R/W)  Vector Table Offset Register\n  __IOM uint32_t AIRCR;                  ///< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register\n  __IOM uint32_t SCR;                    ///< Offset: 0x010 (R/W)  System Control Register\n  __IOM uint32_t CCR;                    ///< Offset: 0x014 (R/W)  Configuration Control Register\n  __IOM uint8_t  SHP[12];                ///< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15)\n  __IOM uint32_t SHCSR;                  ///< Offset: 0x024 (R/W)  System Handler Control and State Register\n  __IOM uint32_t CFSR;                   ///< Offset: 0x028 (R/W)  Configurable Fault Status Register\n  __IOM uint32_t HFSR;                   ///< Offset: 0x02C (R/W)  HardFault Status Register\n  __IOM uint32_t DFSR;                   ///< Offset: 0x030 (R/W)  Debug Fault Status Register\n  __IOM uint32_t MMFAR;                  ///< Offset: 0x034 (R/W)  MemManage Fault Address Register\n  __IOM uint32_t BFAR;                   ///< Offset: 0x038 (R/W)  BusFault Address Register\n  __IOM uint32_t AFSR;                   ///< Offset: 0x03C (R/W)  Auxiliary Fault Status Register\n  __IM  uint32_t PFR[2];                 ///< Offset: 0x040 (R/ )  Processor Feature Register\n  __IM  uint32_t DFR;                    ///< Offset: 0x048 (R/ )  Debug Feature Register\n  __IM  uint32_t ADR;                    ///< Offset: 0x04C (R/ )  Auxiliary Feature Register\n  __IM  uint32_t MMFR[4];                ///< Offset: 0x050 (R/ )  Memory Model Feature Register\n  __IM  uint32_t ISAR[5];                ///< Offset: 0x060 (R/ )  Instruction Set Attributes Register\n        uint32_t RESERVED0[5];           ///< Reserved\n  __IOM uint32_t CPACR;                  ///< Offset: 0x088 (R/W)  Coprocessor Access Control Register\n} SCB_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1];           /*!< Reserved */\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register\n                                            \\note available for Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC300 */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register\n                                            \\note available for Cortex-M1, Cortex-M3 , Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC000, SecureCore SC300 */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control Register\n                                            \\note available for Cortex-M33, Cortex-M33P */\n} SCnSCB_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the Implementation Control Block Register (ICB).\n    \\note replaces SCnSCB_Type (only on Cortex-M55/M85)\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} ICB_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   ///< Offset: 0x000 (R/W)  SysTick Control and Status Register\n  __IOM uint32_t LOAD;                   ///< Offset: 0x004 (R/W)  SysTick Reload Value Register\n  __IOM uint32_t VAL;                    ///< Offset: 0x008 (R/W)  SysTick Current Value Register\n  __IM  uint32_t CALIB;                  ///< Offset: 0x00C (R/ )  SysTick Calibration Register\n} SysTick_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n//      uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n//      uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n//      uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n//      uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n//      uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n//      uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register (Cortex-M33 only) */\n//      uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   ///< Offset: 0x000 (R/ )  MPU Type Register\n  __IOM uint32_t CTRL;                   ///< Offset: 0x004 (R/W)  MPU Control Register\n  __IOM uint32_t RNR;                    ///< Offset: 0x008 (R/W)  MPU Region RNRber Register\n  __IOM uint32_t RBAR;                   ///< Offset: 0x00C (R/W)  MPU Region Base Address Register\n  __IOM uint32_t RASR;                   ///< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register\n  __IOM uint32_t RBAR_A1;                ///< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register\n  __IOM uint32_t RASR_A1;                ///< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register\n  __IOM uint32_t RBAR_A2;                ///< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register\n  __IOM uint32_t RASR_A2;                ///< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register\n  __IOM uint32_t RBAR_A3;                ///< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register\n  __IOM uint32_t RASR_A3;                ///< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register\n} MPU_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1];           ///< Reserved\n  __IOM uint32_t FPCCR;                  ///< Offset: 0x004 (R/W)  Floating-Point Context Control Register\n  __IOM uint32_t FPCAR;                  ///< Offset: 0x008 (R/W)  Floating-Point Context Address Register\n  __IOM uint32_t FPDSCR;                 ///< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register\n  __IM  uint32_t MVFR0;                  ///< Offset: 0x010 (R/ )  Media and FP Feature Register 0\n  __IM  uint32_t MVFR1;                  ///< Offset: 0x014 (R/ )  Media and FP Feature Register 1\n} FPU_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  ///< Offset: 0x000 (R/W)  Debug Halting Control and Status Register\n  __OM  uint32_t DCRSR;                  ///< Offset: 0x004 ( /W)  Debug Core Register Selector Register\n  __IOM uint32_t DCRDR;                  ///< Offset: 0x008 (R/W)  Debug Core Register Data Register\n  __IOM uint32_t DEMCR;                  ///< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register\n} CoreDebug_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   ///< Offset: 0x000 (R/W)  Control Register\n  __IOM uint32_t CYCCNT;                 ///< Offset: 0x004 (R/W)  Cycle Count Register\n  __IOM uint32_t CPICNT;                 ///< Offset: 0x008 (R/W)  CPI Count Register\n  __IOM uint32_t EXCCNT;                 ///< Offset: 0x00C (R/W)  Exception Overhead Count Register\n  __IOM uint32_t SLEEPCNT;               ///< Offset: 0x010 (R/W)  Sleep Count Register\n  __IOM uint32_t LSUCNT;                 ///< Offset: 0x014 (R/W)  LSU Count Register\n  __IOM uint32_t FOLDCNT;                ///< Offset: 0x018 (R/W)  Folded-instruction Count Register\n  __IM  uint32_t PCSR;                   ///< Offset: 0x01C (R/ )  Program Counter Sample Register\n  __IOM uint32_t COMP0;                  ///< Offset: 0x020 (R/W)  Comparator Register 0\n  __IOM uint32_t MASK0;                  ///< Offset: 0x024 (R/W)  Mask Register 0\n  __IOM uint32_t FUNCTION0;              ///< Offset: 0x028 (R/W)  Function Register 0\n        uint32_t RESERVED0[1];           ///< Reserved\n  __IOM uint32_t COMP1;                  ///< Offset: 0x030 (R/W)  Comparator Register 1\n  __IOM uint32_t MASK1;                  ///< Offset: 0x034 (R/W)  Mask Register 1\n  __IOM uint32_t FUNCTION1;              ///< Offset: 0x038 (R/W)  Function Register 1\n        uint32_t RESERVED1[1];           ///< Reserved\n  __IOM uint32_t COMP2;                  ///< Offset: 0x040 (R/W)  Comparator Register 2\n  __IOM uint32_t MASK2;                  ///< Offset: 0x044 (R/W)  Mask Register 2\n  __IOM uint32_t FUNCTION2;              ///< Offset: 0x048 (R/W)  Function Register 2\n        uint32_t RESERVED2[1];           ///< Reserved\n  __IOM uint32_t COMP3;                  ///< Offset: 0x050 (R/W)  Comparator Register 3\n  __IOM uint32_t MASK3;                  ///< Offset: 0x054 (R/W)  Mask Register 3\n  __IOM uint32_t FUNCTION3;              ///< Offset: 0x058 (R/W)  Function Register 3\n} DWT_Type;\n\n\n/**************************************************************************************************/\n/** \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IOM uint32_t SSPSR;                  ///< Offset: 0x000 (R/ )  Supported Parallel Port Size Register\n  __IOM uint32_t CSPSR;                  ///< Offset: 0x004 (R/W)  Current Parallel Port Size Register\n        uint32_t RESERVED0[2];           ///< Reserved\n  __IOM uint32_t ACPR;                   ///< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register\n        uint32_t RESERVED1[55];          ///< Reserved\n  __IOM uint32_t SPPR;                   ///< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register\n        uint32_t RESERVED2[131];         ///< Reserved\n  __IM  uint32_t FFSR;                   ///< Offset: 0x300 (R/ )  Formatter and Flush Status Register\n  __IOM uint32_t FFCR;                   ///< Offset: 0x304 (R/W)  Formatter and Flush Control Register\n  __IM  uint32_t FSCR;                   ///< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register\n        uint32_t RESERVED3[759];         ///< Reserved\n  __IM  uint32_t TRIGGER;                ///< Offset: 0xEE8 (R/ )  TRIGGER\n  __IM  uint32_t FIFO0;                  ///< Offset: 0xEEC (R/ )  Integration ETM Data\n  __IM  uint32_t ITATBCTR2;              ///< Offset: 0xEF0 (R/ )  ITATBCTR2\n        uint32_t RESERVED4[1];           ///< Reserved\n  __IM  uint32_t ITATBCTR0;              ///< Offset: 0xEF8 (R/ )  ITATBCTR0\n  __IM  uint32_t FIFO1;                  ///< Offset: 0xEFC (R/ )  Integration ITM Data\n  __IOM uint32_t ITCTRL;                 ///< Offset: 0xF00 (R/W)  Integration Mode Control\n        uint32_t RESERVED5[39];          ///< Reserved\n  __IOM uint32_t CLAIMSET;               ///< Offset: 0xFA0 (R/W)  Claim tag set\n  __IOM uint32_t CLAIMCLR;               ///< Offset: 0xFA4 (R/W)  Claim tag clear\n        uint32_t RESERVED7[8];           ///< Reserved\n  __IM  uint32_t DEVID;                  ///< Offset: 0xFC8 (R/ )  TPIU_DEVID\n  __IM  uint32_t DEVTYPE;                ///< Offset: 0xFCC (R/ )  TPIU_DEVTYPE\n} TPI_Type;\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Debug.txt",
    "content": "/* ##################################### Debug In/Output function ############################### */\n/** \n\\defgroup  ITM_Debug_gr Debug Access\n\\brief Debug Access to the Instrumented Trace Macrocell (ITM)\n\\details\nCMSIS provides additional debug functions to enlarge the Debug Access. \nData can be transmitted via a certain global buffer variable towards the target system.    \n\nThe Cortex-M3 / Cortex-M4 / Cortex-M7 incorporates the <b>Instrumented Trace Macrocell (ITM)</b> that \nprovides together with the <b>Serial Wire Output (SWO)</b> trace capabilities for the \nmicrocontroller system. The ITM has 32 communication channels; two ITM \ncommunication channels are used by CMSIS to output the following information:\n\n- <b>ITM Channel 0</b>: implements the \\ref ITM_SendChar function \nwhich can be used for printf-style output via the debug interface.\n\n- <b>ITM Channel 31</b>: is reserved for the RTOS kernel and can be used for kernel awareness debugging.\n\n\\remarks\n- ITM channels have 4 groups with 8 channels each, whereby each group can be configured for \naccess rights in the Unprivileged level. \n- The ITM channel 0 can be enabled for the user task. \n- ITM channel 31 can be accessed only in Privileged mode \nfrom the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some \nkernels may use the Privileged level for program execution. \n    \n<hr>    \n\\section ITM_debug_uv ITM Debugger Support\n    \nA debugger may support a <b>Debug (printf) Viewer</b> window to display data.\n\n<b>Direction: Microcontroller --&gt; Debugger:</b>\n- Characters received via ITM communication channel 0 are written in a printf-style to the \n<b>Debug (printf) Viewer</b> window.\n    \n<b>Direction: Debugger --&gt; Microcontroller:</b>\n- Check if \\ref ITM_RxBuffer variable is available (only performed once).\n- Read the character from the <b>Debug (printf) Viewer</b> window.\n- If \\ref ITM_RxBuffer is empty, write character to \\ref ITM_RxBuffer.\n\n\\note\nThe current solution does not use a buffer mechanism for transmitting the characters.\n  \n   \n<hr>     \n\\section itm_debug_ex Example:\nExample for the usage of the ITM Channel 31 for RTOS Kernels:\n\n\\code\n// check if debugger connected and ITM channel enabled for tracing\nif ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&\n    (ITM->TCR & ITM_TCR_ITMENA) &&\n    (ITM->TER & (1UL >> 31))) {\n    \n    // transmit trace data\n    while (ITM->PORT31_U32 == 0);\n    ITM->PORT[31].u8 = task_id;      // id of next task\n    while (ITM->PORT[31].u32 == 0);\n    ITM->PORT[31].u32 = task_status; // status information\n}\n\\endcode\n\n\n@{\n*/\n\n\n/**************************************************************************************************/\nvolatile int32_t ITM_RxBuffer;                     ///< external variable to receive characters                    \n\n/********\n#define          ITM_RxBuffer_EMPTY    0x5AA55AA5  ///< value identifying whether \\ref ITM_RxBuffer is ready for the next character \n********/\n\n/**************************************************************************************************/\n/** \\brief  Transmits a character via channel 0.\n\n    This function transmits a character via the ITM channel 0. \n    It returns when no debugger is connected that has booked the output.  \n    It is blocking when a debugger is connected, but the previously sent character has not been \n    transmitted. \n\n    \\param [in]     ch  Character to transmit\n    \n    \\returns            Character to transmit\n*/\nuint32_t ITM_SendChar (uint32_t ch);\n\n\n/**************************************************************************************************/\n/** \\brief  ITM Receive Character\n\n    This function inputs a character via the external variable \\ref ITM_RxBuffer. \n    It returns when no debugger is connected that has booked the output.  \n    It is blocking when a debugger is connected, but the previously sent character has not been transmitted. \n\n    \\returns        \n        - Received character\n        - =1  - No character received\n*/\nint32_t ITM_ReceiveChar (void);\n\n\n/**************************************************************************************************/\n/** \\brief  ITM Check Character\n\n    This function reads the external variable \\ref ITM_RxBuffer and checks whether a character \n    is available or not. \n\n    \\returns   \n        - =0  - No character available\n        - =1  - Character available\n*/\nint32_t ITM_CheckChar (void);\n\n/** @} */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_FPU.txt",
    "content": "/**\n\\defgroup fpu_functions  FPU Functions\n\\brief Functions that relate to the Floating-Point Arithmetic Unit.\n\\details\nSome Cortex-M processors include optional floating-point arithmetic functionality, with support\nfor single and double-precision arithmetic.\nThe Cortex-M processor with FPU is an implementation of the single-precision and\ndouble-precision variant of the Armv7-M Architecture with Floating-Point Extension (FPv5).\n\n@{\n*/\n\n/**\n  \\brief       Get the FPU type.\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n   \n   The function returns the implemented FPU type. \n*/\n__STATIC_INLINE uint32_t SCB_GetFPUType(void);\n\n/**\n @}  \n*/\n\n \n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_MPU.txt",
    "content": "/**\n\\defgroup mpu_functions  MPU Functions for Armv6-M/v7-M\n\\brief Functions that relate to the Memory Protection Unit.\n\\details\nThe following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.\n\nThe MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.\n\n<b>Example:</b>\n\\code\nint main() \n{\n  // Set Region 0\n  ARM_MPU_SetRegionEx(0UL, 0x08000000UL, ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB));\n  \n  ARM_MPU_Enable(0);\n  \n  // Execute application code that is access protected by the MPU\n  \n  ARM_MPU_Disable();\n}\n\\endcode\n\n@{\n*/\n\n/**\n*/\ntypedef struct {} MPU_Type;\n\n\n/** \\def ARM_MPU_RBAR\n* \\brief MPU Region Base Address Register Value\n*\n* This preprocessor function can be used to construct a valid \\ref MPU_Type::RBAR \"RBAR\" value.\n* The VALID bit is implicitly set to 1.\n*\n* \\param Region The region to be configured, number 0 to 15.\n* \\param BaseAddress The base address for the region.\n*/\n#define ARM_MPU_RBAR(Region, BaseAddress)\n\n/**\n* \\def ARM_MPU_RASR\n* \\brief MPU Region Attribute and Size Register Value\n*\n* This macro is used to construct a valid \\ref MPU_Type::RASR \"RASR\" value.\n* The ENABLE bit of the RASR value is implicitly set to 1.\n*\n* \\param DisableExec       Instruction access disable bit. 1 = disable instruction fetches. \n* \\param AccessPermission  Data access permission configures read/write access for User and Privileged mode. Possible values see \\ref ARM_MPU_AP_xxx.\n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       1 = region is shareable between multiple bus masters.\n* \\param IsCacheable       1 = region is cacheable (values may be kept in cache).\n* \\param IsBufferable      1 = region is bufferable (when using write-back caching). Cacheable but non-bufferable regions use write-through policy.\n* \\param SubRegionDisable  Sub-region disable field (8 bits).\n* \\param Size              Region size with values defined under \\ref ARM_MPU_REGION_SIZE_xxx.\n*/                         \n#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)\n\n\n/**\n* \\def ARM_MPU_RASR_EX\n* \\brief MPU Region Attribute and Size Register Value\n*\n* This macro is used to construct a valid \\ref MPU_Type::RASR \"RASR\" value.\n* The ENABLE bit of the RASR value is implicitly set to 1.\n*\n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permission configures read/write access for User and Privileged mode. Possible values see \\ref ARM_MPU_AP_xxx.\n* \\param AccessAttributes  Memory access attribution, see \\ref ARM_MPU_ACCESS_xxx.\n* \\param SubRegionDisable  Sub-region disable field (8 bits).\n* \\param Size              Region size with values defined under \\ref ARM_MPU_REGION_SIZE_xxx.\n*/\n#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)\n\n/**\n* \\brief Setup information of a single MPU Region\n* \\details The typedef \\ref ARM_MPU_Region_t allows to define a MPU table (array of MPU regions) with pre-compiled register values.\n* Such tables enable efficient MPU setup using the function \\ref ARM_MPU_Load.\n* \n* <b>Example:</b>  See \\ref ARM_MPU_Load\n*/\ntypedef struct {\n    uint32_t RBAR; //!< The region base address register value (\\ref MPU_Type::RBAR \"RBAR\")\n    uint32_t RASR; //!< The region attribute and size register value (\\ref MPU_Type::RASR \"RASR\"), see \\ref ARM_MPU_RASR.\n} ARM_MPU_Region_t;\n\n/** \n\\brief Enable the memory protection unit (MPU) and \n\\param MPU_CTRL Additional control settings that configure MPU behaviour\n\\details\nThe function \\ref ARM_MPU_Enable writes to the register \\ref MPU_Type::CTRL \"MPU->CTRL\" and sets bit ENABLE. The parameter \\em MPU_CTRL provides additional bit values \n(see table below) that configure the MPU behaviour.  For processors that implement an <b>MPU Fault Handler</b> the \\ref NVIC_gr \"MemoryManagement_IRQn\" exception is enabled by setting the bit MEMFAULTACT in register SBC->SHCSR.\n\nThe following table contains possible values for the parameter \\em MPU_CTRL that set specific bits in register MPU->CTRL.\n| Bit | MPU_CTRL value           | When applied                                                            | When not applied\n|:----|:-------------------------|:------------------------------------------------------------------------|:---------------------------------------\n| 1   | MPU_CTRL_HFNMIENA_Msk    | Enable MPU during hard fault, NMI, and FAULTMASK handlers execution     | Disable MPU during hard fault, NMI, and FAULTMASK handler execution\n| 2   | MPU_CTRL_PRIVDEFENA_Msk  | Enable default memory map as a background region for privileged access  | Use only MPU region settings\n\n<b>Example:</b>\n\n\\code \n// enable MPU with all region definitions. Exceptions are not protected by MPU.\n  MPU_Enable (0);\n  \n// enable MPU with all region definitions and background regions for privileged access. Exceptions are protected by MPU.\n  MPU_Enable (MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);\n\\endcode  \n\n\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_CTRL);\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable();\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr);\n\n/** Configure an MPU region.\n*\n* The region number should be contained in the rbar value.\n*\n* \\param rbar Value for \\ref MPU_Type::RBAR \"RBAR\" register.\n* \\param rasr Value for \\ref MPU_Type::RASR \"RASR\" register.\n*/ \n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr);\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for \\ref MPU_Type::RBAR \"RBAR\" register.\n* \\param rasr Value for \\ref MPU_Type::RASR \"RASR\" register.\n*/\n__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr);\n\n/** Memcpy with strictly ordered memory access, e.g. used by code in \\ref ARM_MPU_Load.\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len);\n\n/** Load the given number of MPU regions from a table.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Number of regions to be configured.\n*\n* \\note only up to 16 regions can be handled as the function \\ref ARM_MPU_Load uses the REGION field in \\ref MPU_Type::RBAR \"MPU->RBAR\".\n*\n* <b>Example:</b>\n* \\code\n* const ARM_MPU_Region_t mpuTable[3][4] = {\n*   {\n*     { .RBAR = ARM_MPU_RBAR(0UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB)  },\n*     { .RBAR = ARM_MPU_RBAR(1UL, 0x20000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },\n*     { .RBAR = ARM_MPU_RBAR(2UL, 0x40020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB)  }, \n*     { .RBAR = ARM_MPU_RBAR(3UL, 0x40022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB)  }\n*   },\n*   {\n*     { .RBAR = ARM_MPU_RBAR(4UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB)  },\n*     { .RBAR = ARM_MPU_RBAR(5UL, 0x20000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },\n*     { .RBAR = ARM_MPU_RBAR(6UL, 0x40020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB)  }, \n*     { .RBAR = ARM_MPU_RBAR(7UL, 0x40022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB)  }\n*   },\n*   {\n*     { .RBAR = ARM_MPU_RBAR(4UL, 0x18000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB)  },\n*     { .RBAR = ARM_MPU_RBAR(5UL, 0x30000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },\n*     { .RBAR = ARM_MPU_RBAR(6UL, 0x50020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB)  }, \n*     { .RBAR = ARM_MPU_RBAR(7UL, 0x50022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB)  }\n*   }\n* };\n*  \n* void UpdateMpu(uint32_t idx)\n* {\n*    ARM_MPU_Load(mpuTable[idx], 4);\n* }\n* \\endcode\n*\n*/\n__STATIC_INLINE void ARM_MPU_Load(MPU_Region_t const* table, uint32_t cnt);\n\n\n/**\n @}  \n \n\\defgroup mpu_defines Define values\n\\ingroup mpu_functions\n\\brief Define values for MPU region setup.\n\\details\nThe following define values are used with \\ref ARM_MPU_RASR to setup the \\ref MPU_Type::RASR \"RASR\" value field in the MPU region.\n\n\\see \nARM_MPU_Region_t, ARM_MPU_SetRegion, ARM_MPU_SetRegionEx.\n@{\n*/\n\n/** \\def ARM_MPU_REGION_SIZE_xxx\n\\brief Size values of a MPU region (in RASR field)\n\\details\nThe following define values are used to compose the size information for an MPU region:\n\n|\\#define                  | Value            | Description                                              |\n|:-------------------------|:-----------------|:---------------------------------------------------------|\n|ARM_MPU_REGION_SIZE_32B   | 0x04U            | Region size 32 Bytes\n|ARM_MPU_REGION_SIZE_64B   | 0x05U            | Region size 64 Bytes\n|ARM_MPU_REGION_SIZE_128B  | 0x06U            | Region size 128 Bytes\n|ARM_MPU_REGION_SIZE_256B  | 0x07U            | Region size 256 Bytes\n|ARM_MPU_REGION_SIZE_512B  | 0x08U            | Region size 512 Bytes\n|ARM_MPU_REGION_SIZE_1KB   | 0x09U            | Region size 1 KByte\n|ARM_MPU_REGION_SIZE_2KB   | 0x0AU            | Region size 2 KBytes\n|ARM_MPU_REGION_SIZE_4KB   | 0x0BU            | Region size 4 KBytes\n|ARM_MPU_REGION_SIZE_8KB   | 0x0CU            | Region size 8 KBytes\n|ARM_MPU_REGION_SIZE_16KB  | 0x0DU            | Region size 16 KBytes\n|ARM_MPU_REGION_SIZE_32KB  | 0x0EU            | Region size 32 KBytes\n|ARM_MPU_REGION_SIZE_64KB  | 0x0FU            | Region size 64 KBytes\n|ARM_MPU_REGION_SIZE_128KB | 0x10U            | Region size 128 KBytes\n|ARM_MPU_REGION_SIZE_256KB | 0x11U            | Region size 256 KBytes\n|ARM_MPU_REGION_SIZE_512KB | 0x12U            | Region size 512 KBytes\n|ARM_MPU_REGION_SIZE_1MB   | 0x13U            | Region size 1 MByte\n|ARM_MPU_REGION_SIZE_2MB   | 0x14U            | Region size 2 MBytes\n|ARM_MPU_REGION_SIZE_4MB   | 0x15U            | Region size 4 MBytes\n|ARM_MPU_REGION_SIZE_8MB   | 0x16U            | Region size 8 MBytes\n|ARM_MPU_REGION_SIZE_16MB  | 0x17U            | Region size 16 MBytes\n|ARM_MPU_REGION_SIZE_32MB  | 0x18U            | Region size 32 MBytes\n|ARM_MPU_REGION_SIZE_64MB  | 0x19U            | Region size 64 MBytes\n|ARM_MPU_REGION_SIZE_128MB | 0x1AU            | Region size 128 MBytes\n|ARM_MPU_REGION_SIZE_256MB | 0x1BU            | Region size 256 MBytes\n|ARM_MPU_REGION_SIZE_512MB | 0x1CU            | Region size 512 MBytes\n|ARM_MPU_REGION_SIZE_1GB   | 0x1DU            | Region size 1 GByte\n|ARM_MPU_REGION_SIZE_2GB   | 0x1EU            | Region size 2 GBytes\n|ARM_MPU_REGION_SIZE_4GB   | 0x1FU            | Region size 4 GBytes\n*/\n#define ARM_MPU_REGION_SIZE_xxx\n\n/** \\def ARM_MPU_AP_xxx\n\\brief Values for MPU region access permissions (in RASR field)\n\\details\nThe following define values are used to compose the access permission for an MPU region:\n|\\#define                  | Value            | Access permissions               |\n|:-------------------------|:-----------------|:---------------------------------------------------------|\n|ARM_MPU_AP_NONE           | 0x0U             | None: any access generates a permission fault.\n|ARM_MPU_AP_PRIV           | 0x1U             | Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault.\n|ARM_MPU_AP_URO            | 0x2U             | Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault.\n|ARM_MPU_AP_FULL           | 0x3U             | Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated.\n|ARM_MPU_AP_PRO            | 0x5U             | Privileged Read-only: any unprivileged access or privileged write generates a permission fault.\n|ARM_MPU_AP_RO             | 0x6U             | Privileged and Unprivileged Read-only: any write generates a permission fault.\n*/\n#define ARM_MPU_AP_xxx\n\n/** \\def ARM_MPU_ACCESS_xxx\n\\brief Values for MPU region access attributes (in RASR field)\n\\details\nThe following define values are used to compose the access attributes for an MPU region:\n|\\#define                      | TEX  | Shareable | Cacheable | Bufferable | Description             |\n|:-----------------------------|:-----|:----------|:----------|:-----------|:------------------------|\n| ARM_MPU_ACCESS_ORDERED       | 000b | 1         | 0         | 0          | Strongly ordered memory |\n| ARM_MPU_ACCESS_DEVICE(S)     | 0s0b | S         | 0         | S          | Memory mapped peripheral device, shared (S=1) or non-shared (S=0) |\n| ARM_MPU_ACCESS_NORMAL(O,I,S) | 1BBb | S         | A         | A          | Normal memory, with outer/inner cache policy (O/I=\\ref ARM_MPU_CACHEP_xxx, shared (S=1) or non-share (S=0) |\n*/\n#define ARM_MPU_ACCESS_xxx\n \n/** \\def ARM_MPU_CACHEP_xxx\n\\brief Cache policy values for MPU region access attributes (in RASR field)\n\\details\nThe following define values are used to compose the cacheability flags within the\naccess attributes for an MPU region:\n|\\#define                      | Value | Cacheability policy     |\n|:-----------------------------|:------|:------------------------|\n| ARM_MPU_CACHEP_NOCACHE       | 00b   | Non-cacheable           |\n| ARM_MPU_CACHEP_WB_WRA        | 01b   | Write-back, write and read allocate |\n| ARM_MPU_CACHEP_WT_NWA        | 10b   | Write-through, no write allocate    |\n| ARM_MPU_CACHEP_WB_NWA        | 11b   | Write-back, no write allocate       |\n*/\n#define ARM_MPU_CACHEP_xxx\n \n/** @} */\n\n/** \n\n\\var ARM_MPU_Region_t::RBAR\nThis value specifies the start address of the MPU protected memory region. The address must be a multiple of the region size (size aligned).\n\nSee \\ref MPU_Type::RBAR for details about field bit format.\n\n\\var ARM_MPU_Region_t::RASR\nThis value specifies region attributes and size. Use the \\ref ARM_MPU_RASR macro to compose this value.\n\n\\var MPU_Type::TYPE\nThe MPU Type Register indicates how many regions the MPU support. Software can use it\nto determine if the processor implements an MPU.\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:24] | -             | Reserved.                                                     |\n| [23:16] | IREGION       | Instruction region. RAZ. Armv7-M only supports a unified MPU. |\n| [15:8]  | DREGION       | Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU. |\n| [7:1]   | -             | Reserved.                                                     |\n| [0]     | SEPARATE      | Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU. |\n\n\\var MPU_Type::CTRL\nEnables the MPU, and when the MPU is enabled, controls whether the default memory map\nis enabled as a background region for privileged accesses, and whether the MPU is enabled\nfor HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1.\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:3]  | -             | Reserved.                                                     |\n| [2]     | PRIVDEFENA    | 0 - Disables the default memory map. 1 - Enables the default memory map as a background region for privileged access. |\n| [1]     | HFNMIENA      | 0 - Disables the MPU for exception handlers. 1 - Use the MPU for memory accesses by exception handlers. |\n| [0]     | ENABLE        | 0 - The MPU is disabled. 1 - The MPU is enabled.              |\n\n\\var MPU_Type::RNR    \nSelects the region currently accessed by \\ref MPU_Type::RBAR and \\ref MPU_Type::RASR.\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:8]  | -             | Reserved.                                                     |\n| [7:0]   | REGION        | Indicates the memory region accessed.                         |\n\n\\var MPU_Type::RBAR  \nHolds the base address of the region identified by MPU_RNR. On a write, can also be used\nto update the base address of a specified region, in the range 0 to 15, updating MPU_RNR\nwith the new region number.\n \n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:5]  | ADDR          | Base address of the region.                                   |\n| [4]     | VALID         | 1 - Update \\ref MPU_Type::RNR to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region. |\n| [3:0]   | REGION        | On writes, can specify the number of the region to update, see VALID field description. |\n\n\\var MPU_Type::RASR\nDefines the size and access behavior of the region identified by MPU_RNR, and enables\nthat region.\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:29] | -             | Reserved.                                                     |\n| [28]    | XN            | Execute Never.                                                |\n| [27]    | -             | Reserved.                                                     |\n| [26:24] | AP            | Access Permissions, see \\ref ARM_MPU_AP_xxx.                  |\n| [23:22] | -             | Reserved.                                                     |\n| [21:19] | TEX           | Type Extension.                                               |\n| [18]    | S             | Shareable.                                                    |\n| [17]    | C             | Cacheable.                                                    |\n| [16]    | B             | Bufferable.                                                   |\n| [15:8]  | SRD           | Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled (0) or disabled (1). \n| [7:6]   | -             | Reserved.                                                     |\n| [5:1]   | SIZE          | Indicates the region size. The region size, in bytes, is 2(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes. |\n| [0]     | ENABLE        | 0 - This region is disabled. 1 - This region is enabled.      |\n\n\\var MPU_Type::RBAR_A1\nAlias for \\ref MPU_Type::RBAR.\n\n\\var MPU_Type::RASR_A1\nAlias for \\ref MPU_Type::RASR.\n\n\\var MPU_Type::RBAR_A2\nAlias for \\ref MPU_Type::RBAR.\n\n\\var MPU_Type::RASR_A2\nAlias for \\ref MPU_Type::RASR.\n\n\\var MPU_Type::RBAR_A3\nAlias for \\ref MPU_Type::RBAR.\n\n\\var MPU_Type::RASR_A3\nAlias for \\ref MPU_Type::RASR.\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_MPU8.txt",
    "content": "/**\n\\defgroup mpu8_functions  MPU Functions for Armv8-M\n\\brief Functions that relate to the Memory Protection Unit.\n\\details\nThe following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.\n\nThe MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.\n\n<b>Example:</b>\n\\code\nint main() \n{\n  // Set Region 0 using Attr 0\n  ARM_MPU_SetMemAttr(0UL, ARM_MPU_ATTR( /* Normal memory */\n    MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA,  /* Outer Write-Back transient with read and write allocate */\n    MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA   /* Inner Write-Through transient with read and write allocate */\n  ));\n  \n  ARM_MPU_SetRegion(0UL,\n    ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RW, ARM_MPU_AP_NP, ARM_MPU_XN),  /* Non-shareable, read/write, non-privileged, execute-never */\n    ARM_MPU_RLAR(0x080FFFFFUL, MAIR_ATTR(0))                        /* 1MB memory block using Attr 0 */\n  );\n  \n  ARM_MPU_Enable(0);\n  \n  // Execute application code that is access protected by the MPU\n  \n  ARM_MPU_Disable();\n}\n\\endcode\n\n@{\n*/\n\n/** \\brief Attribute for device memory (outer only) */\n#define ARM_MPU_ATTR_DEVICE                           ( 0U )\n\n/** \\brief Attribute for non-cacheable, normal memory */\n#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )\n\n/** \\brief Attribute for Normal memory, Outer and Inner cacheability.\n* \\param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.\n* \\param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.\n* \\param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.\n* \\param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.\n*/\n#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA)\n\n/** \\brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRnE \n\n/** \\brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRE\n\n/** \\brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGRE\n\n/** \\brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_GRE\n\n/** \\brief Normal memory outer-cacheable and inner-cacheable attributes\n* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate\n*/\n#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE\n#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA\n#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA\n#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA\n#define MPU_ATTR_NORMAL_OUTER_WT_RA\n#define MPU_ATTR_NORMAL_OUTER_WT_WA\n#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA\n#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA\n#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA\n#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA\n#define MPU_ATTR_NORMAL_OUTER_WB_RA\n#define MPU_ATTR_NORMAL_OUTER_WB_WA\n#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA\n#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE\n#define MPU_ATTR_NORMAL_INNER_WT_TR_RA\n#define MPU_ATTR_NORMAL_INNER_WT_TR_WA\n#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA\n#define MPU_ATTR_NORMAL_INNER_WT_RA\n#define MPU_ATTR_NORMAL_INNER_WT_WA\n#define MPU_ATTR_NORMAL_INNER_WT_RA_WA\n#define MPU_ATTR_NORMAL_INNER_WB_TR_RA\n#define MPU_ATTR_NORMAL_INNER_WB_TR_WA\n#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA\n#define MPU_ATTR_NORMAL_INNER_WB_RA\n#define MPU_ATTR_NORMAL_INNER_WB_WA\n#define MPU_ATTR_NORMAL_INNER_WB_RA_WA\n\n/** \\brief Memory Attribute\n* \\param O Outer memory attributes\n* \\param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\n*/\n#define ARM_MPU_ATTR(O, I)\n\n/**\n * Shareability\n */\n/** \\brief Normal memory non-shareable  */\n#define ARM_MPU_SH_NON\n\n/** \\brief Normal memory outer shareable  */\n#define ARM_MPU_SH_OUTER\n\n/** \\brief Normal memory inner shareable  */\n#define ARM_MPU_SH_INNER\n\n/**\n * Access permissions\n * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only\n */\n/** \\brief Normal memory, read/write */\n#define ARM_MPU_AP_RW\n\n/** \\brief Normal memory, read-only */\n#define ARM_MPU_AP_RO\n\n/** \\brief Normal memory, any privilege level */\n#define ARM_MPU_AP_NP\n\n/** \\brief Normal memory, privileged access only */\n#define ARM_MPU_AP_PO\n\n/*\n * Execute-never\n * XN = Execute-never, EX = Executable\n */\n/** \\brief Normal memory, Execution only permitted if read permitted */\n#define ARM_MPU_XN\n\n/** \\brief Normal memory, Execution only permitted if read permitted */\n#define ARM_MPU_EX\n\n/** \\brief Memory access permissions\n* \\param RO Read-Only: Set to 1 for read-only memory.\n* \\param NP Non-Privileged: Set to 1 for non-privileged memory.\n*/\n#define ARM_MPU_AP_(RO, NP)\n\n/** \\brief Region Base Address Register value\n* \\param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\n* \\param SH Defines the Shareability domain for this memory region.\n* \\param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.\n* \\param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.\n* \\param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.\n*/\n#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN)\n\n/** \\brief Region Limit Address Register value\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\n* \\param IDX The attribute index to be associated with this memory region.\n*/\n#define ARM_MPU_RLAR(LIMIT, IDX)\n\n/** \\brief Region Limit Address Register with PXN value\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\n* \\param PXN Privileged execute never. Defines whether code can be executed from this privileged region.\n* \\param IDX The attribute index to be associated with this memory region.\n*/\n#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX)\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR;                   /*!< Region Base Address Register value */\n  uint32_t RLAR;                   /*!< Region Limit Address Register value */\n} ARM_MPU_Region_t;\n\n/**\n  \\brief  Read MPU Type Register\n  \\return Number of MPU regions\n*/\n__STATIC_INLINE uint32_t ARM_MPU_TYPE()\n\n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control);\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void);\n\n/** Enable the Non-secure MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE ARM_MPU_Enable_NS(uint32_t MPU_Control);\n\n/** Disable the Non-secure MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable_NS(void);\n\n/** Set the memory attribute encoding to the given MPU.\n* \\param mpu Pointer to the MPU to be configured.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr);\n\n/** Set the memory attribute encoding.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr);\n\n/** Set the memory attribute encoding to the Non-secure MPU.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr);\n\n/** Clear and disable the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr);\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr);\n\n/** Clear and disable the given Non-secure MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr);\n\n/** Configure the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar);\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar);\n\n/** Configure the given Non-secure MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar);\n\n/** Memcpy with strictly ordered memory access, e.g. used by code in \\ref ARM_MPU_LoadEx.\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len);\n\n/** Load the given number of MPU regions from a table to the given MPU.\n* \\param mpu Pointer to the MPU registers to be used.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt);\n\n/** Load the given number of MPU regions from a table.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*\n* <b>Example:</b>\n* \\code\n* const ARM_MPU_Region_t mpuTable[1][4] = {\n*   {\n*     //                     BASE          SH              RO             NP             XN                                LIMIT         ATTR \n*     { .RBAR = ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x080FFFFFUL, MAIR_ATTR(0)) },\n*     { .RBAR = ARM_MPU_RBAR(0x20000000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x20007FFFUL, MAIR_ATTR(0)) },\n*     { .RBAR = ARM_MPU_RBAR(0x40020000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x40021FFFUL, MAIR_ATTR(1)) },\n*     { .RBAR = ARM_MPU_RBAR(0x40022000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x40022FFFUL, MAIR_ATTR(1)) }\n*   }\n* };\n*  \n* void UpdateMpu(uint32_t idx)\n* {\n*    ARM_MPU_Load(0, mpuTable[idx], 4);\n* }\n* \\endcode\n*/\n__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt);\n\n/** Load the given number of MPU regions from a table to the Non-secure MPU.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt);\n\n/** @} */\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_MVE.txt",
    "content": "/**\n\\defgroup mve_functions  MVE Functions\n\\brief Functions that relate to the MVE (Cortex-M Vector Extensions) Unit.\n\\details\nSome Cortex-M processors include an optional MVE unit.\n\n@{\n*/\n\n/**\n  \\brief   Get the MVE type.\n  \\details Returns the MVE type.\n  \\returns\n   - \\b  0: No Vector Extension (MVE)\n   - \\b  1: Integer Vector Extension (MVE-I)\n   - \\b  2: Floating-point Vector Extension (MVE-F)\n */\n__STATIC_INLINE uint32_t SCB_GetMVEType(void);\n\n/**\n @}  \n*/\n\n \n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_NVIC.txt",
    "content": "/**\n\\defgroup   NVIC_gr  Interrupts and Exceptions (NVIC)\n  @{\n\\brief      Functions to access the Nested Vector Interrupt Controller (NVIC).\n\\details\nThis section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC).\n\nArm provides a template file <strong>startup_<em>device</em></strong> for each supported\ncompiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific \ninterrupt handlers. Each interrupt handler is defined as a <strong><em>weak</em></strong> function \nto an dummy handler. These interrupt handlers can be used directly in application software \nwithout being adapted by the programmer.\n\nThe table below lists the core exception vectors of the various Cortex-M processors.\n\n<table class=\"cmtable\" summary=\"Core Exception Name\">\n    <tr>\n      <th>Exception Vector</th>\n      <th>Handler Function</th>\n      <th>IRQn<br/>Value</th>\n      <th title=\"Cortex-M0/M0+\n\\if ARMSC\nand SC000\n\\endif\n      \">Armv6-M</th>\n      <th title=\"Cortex-M3/M4/M7\n\\if ARMSC\nand SC300\n\\endif\n      \">Armv7-M</th>\n\\if ARMv8M\n      <th title=\"Cortex-M23\">Armv8-M<br/>Baseline</th>\n      <th title=\"Cortex-M33/M35P\">Armv8-M<br/>Mainline</th>\n      <th>Armv8.1-M<br/>Mainline</th>\n\\endif\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td><b>NonMaskableInt_IRQn</b></td>\n      <td>NMI_Handler</td>\n      <td>-14</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\if ARMv8M\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\endif\n      <td>Non Maskable Interrupt</td>\n    </tr>\n    <tr>\n      <td><b>HardFault_IRQn</b></td>\n      <td>HardFault_Handler</td>\n      <td>-13</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\if ARMv8M\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\endif\n      <td>Hard Fault Interrupt</td>\n    </tr>\n    <tr>\n      <td><b>MemoryManagement_IRQn</b></td>\n      <td>MemManage_Handler</td>\n      <td>-12</td>\n      <td>&nbsp;</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\if ARMv8M\n      <td>&nbsp;</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\endif\n      <td>Memory Management Interrupt</td>\n    </tr>\n    <tr>\n      <td><b>BusFault_IRQn</b></td>\n      <td>BusFault_Handler</td>\n      <td>-11</td>\n      <td>&nbsp;</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\if ARMv8M\n      <td>&nbsp;</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\endif\n      <td>Bus Fault Interrupt</td>\n    </tr>\n    <tr>\n      <td><b>UsageFault_IRQn</b></td>\n      <td>UsageFault_Handler</td>\n      <td>-10</td>\n      <td>&nbsp;</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\if ARMv8M\n      <td>&nbsp;</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\endif\n      <td>Usage Fault Interrupt</td>\n    </tr>\n\\if ARMv8M\n    <tr>\n      <td><b>SecureFault_IRQn</b></td>\n      <td>SecureFault_Handler</td>\n      <td>-9</td>\n      <td>&nbsp;</td>\n      <td>&nbsp;</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td>Secure Fault Interrupt</td>\n    </tr>\n\\endif\n    <tr>\n      <td><b>SVCall_IRQn</b></td>\n      <td>SVC_Handler</td>\n      <td>-5</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\if ARMv8M\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\endif\n      <td>SVC Interrupt </td>\n    </tr>\n    <tr>\n      <td><b>DebugMonitor_IRQn</b></td>\n      <td>DebugMon_Handler</td>\n      <td>-4</td>\n      <td>&nbsp;</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\if ARMv8M\n      <td>&nbsp;</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\endif\n      <td>Debug Monitor Interrupt</td>\n    </tr>\n    <tr>\n      <td><b>PendSV_IRQn</b></td>\n      <td>PendSV_Handler</td>\n      <td>-2</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\if ARMv8M\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\endif\n      <td>Pend SV Interrupt</td>\n    </tr>\n    <tr>\n      <td><b>SysTick_IRQn</b></td>\n      <td>SysTick_Handler</td>\n      <td>-1</td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\if ARMv8M\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n      <td><img src=\"check.png\" alt=\"available\"></td>\n\\endif\n      <td>System Tick Interrupt</td>\n    </tr>\n</table>\n\n\nVector Table \n============\nThe Vector Table defines the entry addresses of the processor exceptions and the\ndevice specific interrupts.  It is typically located at the beginning of the \nprogram memory, however \\ref using_VTOR_pg it can be relocated to RAM.  The symbol \n<b>__Vectors</b> is the address of the vector table in the startup code and the\nregister <b>SCB->VTOR</b> holds the start address of the vector table. \n\n\\if ARMv8M\nAn Armv8-M implementation with TrustZone provides two vector tables: \n  - vector table for Secure handlers\n  - vector table for Non-Secure handlers\n\nRefer to \\ref Model_TrustZone for more information.\n\\endif\n\nProcessor Exceptions\n--------------------\nAt the beginning of the vector table, the initial stack value and the \nexception vectors of the processor are defined. The vector table below \nshows the exception vectors of a Armv8-M Mainline processor. Other processor\nvariants may have fewer vectors.\n\n\\code\n__Vectors       DCD     __initial_sp              ; Top of Stack initialization\n                DCD     Reset_Handler             ; Reset Handler\n                DCD     NMI_Handler               ; NMI Handler\n                DCD     HardFault_Handler         ; Hard Fault Handler\n                DCD     MemManage_Handler         ; MPU Fault Handler\n                DCD     BusFault_Handler          ; Bus Fault Handler\n                DCD     UsageFault_Handler        ; Usage Fault Handler\n                DCD     SecureFault_Handler       ; Secure Fault Handler\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     SVC_Handler               ; SVC Handler\n                DCD     DebugMon_Handler          ; Debug Monitor Handler\n                DCD     0                         ; Reserved\n                DCD     PendSV_Handler            ; PendSV Handler\n                DCD     SysTick_Handler           ; SysTick Handler\n\\endcode\n\n\nDevice Specific Vectors\n-----------------------\nFollowing the processor exception vectors, the vector table contains also the\ndevice specific interrupt vectors.\n\n\\code\n; device specific interrupts\n                DCD     WWDG_IRQHandler           ; Window Watchdog\n                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect\n                DCD     TAMPER_IRQHandler         ; Tamper\n\\endcode\n\nAll device specific interrupts should have a default interrupt handler function that can \nbe overwritten in user code. Below is an example for this default handler function.\n\n\\code\nDefault_Handler PROC\n                EXPORT WWDG_IRQHandler   [WEAK]\n                EXPORT PVD_IRQHandler    [WEAK]\n                EXPORT TAMPER_IRQHandler [WEAK]\n                :\n                :\n                WWDG_IRQHandler\n                PVD_IRQHandler\n                TAMPER_IRQHandler\n                :\n                :\n                B .\n                ENDP\n\\endcode\n                \n\nThe user application may simply define an interrupt handler function by using the handler name\nas shown below.\n\n\\code\nvoid WWDG_IRQHandler(void)\n{\n  ...\n}\n\\endcode\n\nNVIC Function Usage\n===================\nThe code below shows the usage of various CMSIS NVIC functions with an LPC1700 device.\n\nCode Example 1\n--------------  \n\\code\n#include \"LPC17xx.h\"\n \nuint32_t priorityGroup;                                     /* Variables to store priority group and priority */\nuint32_t priority;\nuint32_t preemptPriority;\nuint32_t subPriority;\n \nint main (void)  {\n  NVIC_SetPriorityGrouping(5);                              /* Set priority group to 5:\n                                                               Bit[7..6] preempt priority Bits, \n                                                               Bit[5..3] subpriority Bits \n                                                               (valid for five priority bits) */\n     \n  priorityGroup =  NVIC_GetPriorityGrouping();              /* Get used priority grouping */\n \n  priority = NVIC_EncodePriority(priorityGroup, 1, 6);      /* Encode priority with 6 for subpriority and 1 for preempt priority\n                                                               Note: priority depends on the used priority grouping */\n  NVIC_SetPriority(UART0_IRQn, priority);                   /* Set new priority */\n \n  priority =  NVIC_GetPriority(UART0_IRQn);                 /* Retrieve priority again */    \n  NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority);\n \n  while(1);\n}\n\\endcode\n\n\nCode Example 2\n--------------\n\\code\n#include \"LPC17xx.h\"\n \nuint32_t active;                                            /* Variable to store interrupt active state */\n \nvoid TIMER0_IRQHandler(void)  {                             /* Timer 0 interrupt handler  */\n \n  if (LPC_TIM0->IR & (1 << 0))  {                           /* Check if interrupt for match channel 0 occurred */ \n    LPC_TIM0->IR |= (1 << 0);                               /* Acknowledge interrupt for match channel 0 occurred */\n  }\n  active = NVIC_GetActive(TIMER0_IRQn);                     /* Get interrupt active state of timer 0 */\n}\n \nint main (void) {\n                                                            /* Set match channel register MR0 to 1 millisecond */\n  LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1);\t    /* 1 ms? */\n   \n  LPC_TIM0->MCR = (3 << 0);                                 /* Enable interrupt and reset for match channel MR0 */\n  NVIC_EnableIRQ(TIMER0_IRQn);                              /* Enable NVIC interrupt for timer 0 */\n  LPC_TIM0->TCR = (1 << 0);                                 /* Enable timer 0 */\n \n  while(1);\n}\n\\endcode\n\n\nNVIC API Virtualization\n=======================\nThe CMSIS-Core has provisions for overriding NVIC APIs as required for implementing\nsecure systems that control access to peripherals and related interrupts.\nThese overrides allow an operating system to control the access privileges of\napplication code to critical interrupts.\n\nThe NVIC function virtualization is enabled with the following \\#define symbols:\n  - \\ref CMSIS_NVIC_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) NVIC functions.\n  - \\ref CMSIS_VECTAB_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) interrupt vector table access functions.\n\n*/     \n\n#define CMSIS_NVIC_VIRTUAL   ///< Virtualization of the NVIC API\n/**\n\\def CMSIS_NVIC_VIRTUAL\nWhen \\ref CMSIS_NVIC_VIRTUAL is defined, the NVIC access functions in the table below must be implemented\nfor virtualizing NVIC access.  These functions should be implemented\nin a separate source module.\nThe original CMSIS-Core __NVIC functions are always available independent of \\ref CMSIS_NVIC_VIRTUAL.\n\nNVIC Access Functions     | CMSIS-Core Functions\n--------------------------|---------------------------------------------\nNVIC_EnableIRQ            | __NVIC_EnableIRQ\nNVIC_GetEnableIRQ         | __NVIC_GetEnableIRQ\nNVIC_DisableIRQ           | __NVIC_DisableIRQ\nNVIC_GetPendingIRQ        | __NVIC_GetPendingIRQ\nNVIC_SetPendingIRQ        | __NVIC_SetPendingIRQ\nNVIC_ClearPendingIRQ      | __NVIC_ClearPendingIRQ\nNVIC_GetActive            | __NVIC_GetActive\nNVIC_SetPriority          | __NVIC_SetPriority\nNVIC_GetPriority          | __NVIC_GetPriority\nNVIC_SetPriorityGrouping  | __NVIC_SetPriorityGrouping\nNVIC_GetPriorityGrouping  | __NVIC_GetPriorityGrouping\n*/     \n\n#define CMSIS_VECTAB_VIRTUAL   ///< Virtualization of interrupt vector table access functions\n/**\n\n\\def CMSIS_VECTAB_VIRTUAL\nWhen \\ref CMSIS_NVIC_VIRTUAL is defined, the functions in the table below must be replaced \nto virtualize the API access functions to the interrupt vector table. The NVIC vector table API should be implemented\nin a separate source module. This allows, for example, alternate implementations to relocate the vector table from flash to RAM on the first vector table update.\n\nThe original CMSIS-Core functions are always available, but prefixed with __NVIC.\n\nInterrupt Vector Table Access  | CMSIS-Core Functions\n-------------------------------|---------------------------------------------\nNVIC_GetVector                 | __NVIC_GetVector\nNVIC_SetVector                 | __NVIC_SetVector\n\n*/     \n\n\n/**************************************************************************************************/\n/** \\brief  Definition of IRQn numbers\n\n\nThe core exception enumeration names for IRQn values are defined in the \\ref device_h_pg.\n\n - Negative IRQn values represent processor core exceptions (internal interrupts).\n - Positive IRQn values represent device-specific exceptions (external interrupts). \n - The first device-specific interrupt has the IRQn value 0.\n\nThe table below describes the core exception names and their availability in various Cortex-M cores.\n*/\ntypedef enum IRQn\n{\n/******  Cortex-M3 Processor Exceptions/Interrupt Numbers     **************************/\n  NonMaskableInt_IRQn      = -14,      ///<  Exception 2: Non Maskable Interrupt\n  HardFault_IRQn           = -13,      ///<  Exception 3: Hard Fault Interrupt\n  MemoryManagement_IRQn    = -12,      ///<  Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]\n  BusFault_IRQn            = -11,      ///<  Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]\n  UsageFault_IRQn          = -10,      ///<  Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]\n\\if ARMv8M  \n  SecureFault_IRQn         = -9,       ///<  Exception 7: Secure Fault Interrupt [only on Armv8-M]\n\\endif  \n  SVCall_IRQn              = -5,       ///<  Exception 11: SVC Interrupt\n  DebugMonitor_IRQn        = -4,       ///<  Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]\n  PendSV_IRQn              = -2,       ///<  Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]\n  SysTick_IRQn             = -1,       ///<  Exception 15: System Tick Interrupt\n/******  Device-specific Interrupt Numbers     *****************************************/\n  WWDG_STM_IRQn            = 0,        ///<  Device Interrupt 0: Window WatchDog Interrupt\n  PVD_STM_IRQn             = 1,        ///<  Device Interrupt 1: PVD through EXTI Line detection Interrupt\n } IRQn_Type;\n\n/**************************************************************************************************/\n/** \\brief  Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]\n\n  The function sets the priority grouping \\em PriorityGroup using the required unlock sequence.\n  \\em PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field\n  determines the split of group priority from subpriority.\n  Only values from 0..7 are used.\n  In case of a conflict between priority grouping and available\n  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n\n    \\param [in]      PriorityGroup  Priority group\n    \n    \\remarks\n        - not for Cortex-M0, Cortex-M0+, or SC000.\n        - By default, priority group setting is zero.\n        \n    \\sa \n        - \\ref NVIC_GetPriorityGrouping; NVIC_SetPriority; SCB_Type\n        - \\ref ref_man_sec\n*/\nvoid NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]\n\n  This function returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).\n\n    \\return                Priority grouping field\n\n    \\remarks\n        - not for Cortex-M0, Cortex-M0+, or SC000.\n        - By default, priority group setting is zero.\n        \n    \\sa \n        - \\ref NVIC_SetPriorityGrouping; NVIC_GetPriority; SCB_Type\n        - \\ref ref_man_sec\n    \n*/\nuint32_t NVIC_GetPriorityGrouping(void);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Enable a device specific interrupt\n\n    This function enables the specified device specific interrupt \\em IRQn. \n    \\em IRQn cannot be a negative value. \n\n    \\param [in]      IRQn  Interrupt number\n\n    \\remarks\n        - IRQn must not be negative.\n        - The registers that control the enabling and disabling of interrupts are called\n        SETENA and CLRENA.\n        - The number of supported interrupts depends on the implementation of the chip designer\n        and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32: \n        \\n ICTR[4:0] \n                - 0 - 32 interrupts supported\n                - 1 - 64 interrupts supported\n                - ...\n        \n    \\sa     \n        - \\ref NVIC_DisableIRQ; SCnSCB_Type;\n        - \\ref ref_man_sec\n*/\nvoid NVIC_EnableIRQ(IRQn_Type IRQn);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Get a device specific interrupt enable status\n\n    This function returns the interrupt enable status for the specified device specific interrupt \\em IRQn. \n    \\em IRQn cannot be a negative value. \n\n    \\param [in]      IRQn  Interrupt number\n    \n    \\returns    \n            - 0  Interrupt is not enabled\n            - 1  Interrupt is enabled\n\n    \\remarks\n        - IRQn must not be negative.\n        - The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.\n        \n    \\sa     \n        - \\ref NVIC_EnableIRQ; NVIC_DisableIRQ;\n        - \\ref ref_man_sec\n*/\nuint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Disable a device specific interrupt\n\n    This function disables the specified device specific interrupt \\em IRQn. \n    \\em IRQn cannot be a negative value. \n\n    \\param [in]      IRQn  Number of the external interrupt to disable\n\n    \\remarks\n        - IRQn must not be negative.\n        - The registers that control the enabling and disabling of interrupts are called\n        SETENA and CLRENA.\n        \n    \\sa     \n        - \\ref NVIC_EnableIRQ\n        - \\ref ref_man_sec\n*/\nvoid NVIC_DisableIRQ(IRQn_Type IRQn);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Get the pending device specific interrupt\n\n    This function returns the pending status of the specified device specific interrupt \\em IRQn. \n\n    \\param [in]      IRQn  Interrupt number\n    \n    \\returns    \n            - 0  Interrupt is not pending\n            - 1  Interrupt is pending\n            \n    \\remarks\n        - IRQn must not be negative.\n        - The registers that control the status of interrupts are called SETPEND and CLRPEND.\n\n    \\sa     \n        - \\ref NVIC_SetPendingIRQ; NVIC_ClearPendingIRQ\n        - \\ref ref_man_sec\n*/\nuint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Set a device specific interrupt to pending\n\n    This function sets the pending bit for the specified device specific interrupt \\em IRQn.\n    \\em IRQn cannot be a negative value.\n\n    \\param [in]      IRQn  Interrupt number \n    \n    \\remarks\n        - IRQn must not be negative.\n        - The registers that control the status of interrupts are called SETPEND and CLRPEND.\n\n    \\sa     \n        - \\ref NVIC_GetPendingIRQ; NVIC_ClearPendingIRQ\n        - \\ref ref_man_sec\n*/\nvoid NVIC_SetPendingIRQ(IRQn_Type IRQn);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Clear a device specific interrupt from pending  \n    \n    This function removes the pending state of the specified device specific interrupt \\em IRQn. \n    \\em IRQn cannot be a negative number.\n\n    \\param [in]      IRQn  Interrupt number\n    \n    \\remarks\n        - IRQn must not be negative.\n        - The registers that control the status of interrupts are called SETPEND and CLRPEND.\n        - An interrupt can have the status pending though it is not active.\n        \n    \\sa     \n        - \\ref NVIC_SetPendingIRQ; NVIC_GetPendingIRQ\n        - \\ref ref_man_sec\n*/\nvoid NVIC_ClearPendingIRQ(IRQn_Type IRQn);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and \n    returns the active bit of the interrupt \\em IRQn.\n    \n    \\param [in]      IRQn  Interrupt number\n\n    \\returns            \n        - 0  Interrupt is not active\n        - 1  Interrupt is active, or active and pending\n    \n    \\remarks\n        - not for Cortex-M0, Cortex-M0+, or SC000.\n        - IRQn must not be negative.\n        - Each external interrupt has an active status bit. When the processor starts the interrupt \n        handler the bit is set to 1 and cleared when the interrupt return is executed.\n        - When an ISR is preempted and the processor executes another interrupt handler, the \n        previous interrupt is still defined as active.\n    \n    \\sa     \n        - \\ref ref_man_sec\n    \n*/\nuint32_t NVIC_GetActive(IRQn_Type IRQn);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Set the priority for an interrupt\n\n    Sets the priority for the interrupt specified by \\em IRQn.\\em IRQn can can specify any \n    device specific interrupt, or processor exception. The \\em priority specifies \n    the interrupt priority value, whereby lower values indicate a higher priority. The default \n    priority is 0 for every interrupt. This is the highest possible priority.\n\n    The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) \n    priority that is higher than any configurable exception or interrupt.\n\n    \\param [in]      IRQn  Interrupt Number\n    \\param [in]  priority  Priority to set\n\n    \\remarks   \n    - The number of priority levels is configurable and depends on the implementation of the \n    chip designer. To determine the number of bits implemented for interrupt priority-level \n    registers, write \\em 0xFF to one of the priority-level register, then read back the value. For \n    example, if the minimum number of 3 bits have been implemented, the read-back value is \\em 0xE0.\n    - Writes to unimplemented bits are ignored.\n    - <b>For Cortex-M0</b>: \n        - Dynamic switching of interrupt priority levels is not supported. The priority level of \n        an interrupt should not be changed after it has been enabled. \n        - Supports 0 to 192 priority levels.\n        - Priority-level registers are 2 bit wide, occupying the two MSBs. \n        Each Interrupt Priority Level Register is 1-byte wide.\n    - <b>For Cortex-M3, Cortex-M4, and Cortex-M7</b>: \n        - Dynamic switching of interrupt priority levels is supported.\n        - Supports 0 to 255 priority levels.\n        - Priority-level registers have a maximum width of 8 bits and a minimum of 3 bits.\n        Each register can be further divided into preempt priority level and subpriority level.\n        \n    \\sa     \n        - \\ref NVIC_GetPriority;  NVIC_SetPriorityGrouping; __set_BASEPRI;\n        - \\ref ref_man_sec\n*/\nvoid NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Get the priority of an interrupt\n\n    This function reads the priority for the specified interrupt \\em IRQn. \\em IRQn can can specify \n    any device specific interrupt, or processor exception.\n\n    The returned priority value is automatically aligned to the implemented\n    priority bits of the microcontroller.\n\n    \\param [in]   IRQn  Interrupt number\n    \n    \\returns            Interrupt priority\n\n    \\remarks\n    - Each external interrupt has an associated priority-level register. \n    - Unimplemented bits are read as zero.\n\n    \\sa     \n        - \\ref NVIC_SetPriority;  NVIC_GetPriorityGrouping; __get_BASEPRI;\n        - \\ref ref_man_sec\n*/\nuint32_t NVIC_GetPriority(IRQn_Type IRQn);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function encodes the priority for an interrupt with the priority group \\em PriorityGroup,\n    preemptive priority value \\em PreemptPriority, and subpriority value \\em SubPriority.\n    In case of a conflict between priority grouping and available\n    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n \n    \\param [in]     PriorityGroup  Priority group\n    \\param [in]   PreemptPriority  Preemptive priority value (starting from 0)\n    \\param [in]       SubPriority  Subpriority value (starting from 0)\n\n    \\returns                        Encoded priority for the interrupt\n\n    \n    \\remarks\n    - not for Cortex-M0, Cortex-M0+, or SC000.\n    \n    \\sa     \n        - \\ref NVIC_DecodePriority;  NVIC_SetPriority; \n        - \\ref ref_man_sec\n*/\nuint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function decodes an interrupt priority value with the priority group \\em PriorityGroup to \n    preemptive priority value \\em pPreemptPriority and subpriority value \\em pSubPriority.\n    In case of a conflict between priority grouping and available\n    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n \n    \\param [in]         Priority    Priority \n    \\param [in]     PriorityGroup   Priority group\n    \\param [out] *pPreemptPriority  Preemptive priority value (starting from 0)\n    \\param [out]     *pSubPriority  Subpriority value (starting from 0)\n\n    \n    \\remarks\n    - not for Cortex-M0, Cortex-M0+, or SC000.\n    \n    \\sa     \n        - \\ref NVIC_EncodePriority;  NVIC_GetPriority; NVIC_GetPriorityGrouping;\n        - \\ref ref_man_sec\n*/\nvoid NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Read Interrupt Vector [not for Cortex-M0, SC000]\n\n    This function allows to read the address of an interrupt handler function.\n\n    \\param [in]      IRQn  Interrupt number\n\n    \\returns               Address of interrupt handler function\n    \n    \\remarks\n\t\t- For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.\n        \n    \\sa     \n        - \\ref NVIC_SetVector\n        - \\ref ref_man_sec\n*/\nuint32_t NVIC_GetVector(IRQn_Type IRQn);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Modify Interrupt Vector [not for Cortex-M0, SC000]\n\n    This function allows to change the address of an interrupt handler function.\n\n    \\param [in]      IRQn  Interrupt number\n    \\param [in]    vector  Address of new interrupt handler function\n    \n    \\remarks\n        - Usage of this function requires vector relocation to RAM. Refer to \\ref using_VTOR_pg for more information.\n\t\t- For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.\n        \n    \\sa     \n        - \\ref NVIC_GetVector\n        - \\ref ref_man_sec\n*/\nvoid NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);\n\n\n/**************************************************************************************************/\n/** \n    \\brief  Reset the system\n\n    This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.\n    \n    \\remarks\n        - In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and \n        most parts of the system, but should not affect the debug system.\n        \n    \\sa     \n        - \\ref ref_man_sec\n*/\nvoid NVIC_SystemReset (void);\n\n/**\n\\cond (ARMv8M)\n*/\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field from the non-secure NVIC when in secure state.\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\n    \\returns            \n        - 0  if interrupt is assigned to Secure\n        - 1  if interrupt is assigned to Non Secure\n    \\remarks\n        - Only available for Armv8-M in secure state.\n        \n    \\sa     \n        - \\ref NVIC_ClearTargetState; NVIC_SetTargetState;\n */\nuint32_t NVIC_GetTargetState(IRQn_Type IRQn);\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the non-secure NVIC when in secure state.\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\n    \\returns            \n        - 0  if interrupt is assigned to Secure\n        - 1  if interrupt is assigned to Non Secure\n    \\remarks\n        - Only available for Armv8-M in secure state.\n        \n    \\sa     \n        - \\ref NVIC_ClearTargetState; NVIC_GetTargetState;\n */\nuint32_t NVIC_SetTargetState(IRQn_Type IRQn);\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the non-secure NVIC when in secure state.\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\n    \\returns            \n        - 0  if interrupt is assigned to Secure\n        - 1  if interrupt is assigned to Non Secure\n    \\remarks\n        - Only available for Armv8-M in secure state.\n        \n    \\sa     \n        - \\ref NVIC_GetTargetState; NVIC_SetTargetState;\n */\nuint32_t NVIC_ClearTargetState(IRQn_Type IRQn);\n\n/**\n\\endcond\n*/\n\n/*@} end of NVIC_gr */\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_PMU8.txt",
    "content": "/**\n\\defgroup pmu8_functions  PMU Functions for Armv8.1-M\n\\brief Functions that relate to the Performance Monitoring Unit.\n\\details\nThe following functions support the Performance Monitoring Unit (PMU) that is available on the Cortex-M55/M85 processors.\n\nThe PMU is used to monitor events that occur during run-time of an application.\n\n<b>Example:</b>\n\\code\n// Initialize counter variables\n \nunsigned int cycle_count = 0;\nunsigned int l1_dcache_miss_count = 0;\nunsigned int instructions_retired_count = 0;\n \n// Enable the PMU\n// Note: Before using the PMU, software needs to ensure \n// that trace is enabled via the Debug Exception Monitor Control Register, DEMCR:\n// CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;\n \nARM_PMU_Enable();\n \n// Configure Event Counter Register 0 to count instructions retired\n// Configure Event Counter Register 1 to count L1 D-Cache misses\n \nARM_PMU_Set_EVTYPER(0, ARM_PMU_INST_RETIRED);\nARM_PMU_Set_EVTYPER(1, ARM_PMU_L1D_CACHE_MISS_RD);\n \n// Reset Event Counters and Cycle Counter\n \nARM_PMU_EVCNTR_ALL_Reset();\nARM_PMU_CYCCNT_Reset();\n \n// Start incrementing Cycle Count Register and Event Counter Registers 0 & 1\n \nARM_PMU_CNTR_Enable(PMU_CNTENSET_CCNTR_ENABLE_Msk|PMU_CNTENSET_CNT0_ENABLE_Msk|PMU_CNTENSET_CNT1_ENABLE_Msk);\n \n// Code you want to measure here\n \n// Stop incrementing Cycle Count Register and Event Counter Registers 0 & 1\n \nARM_PMU_CNTR_Disable(PMU_CNTENCLR_CCNTR_ENABLE_Msk|PMU_CNTENCLR_CNT0_ENABLE_Msk|PMU_CNTENCLR_CNT1_ENABLE_Msk);\n \n// Get cycle count, number of instructions retired and number of L1 D-Cache misses (on read)\n \ncycle_count = cycle_count + ARM_PMU_Get_CCNTR();\ninstructions_retired_count = instructions_retired_count + ARM_PMU_Get_EVCNTR(0);\nl1_dcache_miss_count = l1_dcache_miss_count + ARM_PMU_Get_EVCNTR(1);      // Note: D-Cache must be enabled using\n                                                                          // SCB_EnableDCache() for meaningful result.\n\\endcode\n\n@{\n*/\n\n/**\n\\defgroup pmu8_events_armv81  PMU Events for Armv8.1-M\n\\ingroup pmu8_functions\n\\brief IDs for Armv8.1-M architecture defined events.\n\\details\nThese events are available on all Armv8.1-M devices including a PMU.\n@{\n*/\n\n#define ARM_PMU_SW_INCR                              0x0000             /*!< \\brief Software update to the PMU_SWINC register, architecturally executed and condition code check pass */\n#define ARM_PMU_L1I_CACHE_REFILL                     0x0001             /*!< \\brief L1 I-Cache refill */\n#define ARM_PMU_L1D_CACHE_REFILL                     0x0003             /*!< \\brief L1 D-Cache refill */\n#define ARM_PMU_L1D_CACHE                            0x0004             /*!< \\brief L1 D-Cache access */\n#define ARM_PMU_LD_RETIRED                           0x0006             /*!< \\brief Memory-reading instruction architecturally executed and condition code check pass */\n#define ARM_PMU_ST_RETIRED                           0x0007             /*!< \\brief Memory-writing instruction architecturally executed and condition code check pass */\n#define ARM_PMU_INST_RETIRED                         0x0008             /*!< \\brief Instruction architecturally executed */\n#define ARM_PMU_EXC_TAKEN                            0x0009             /*!< \\brief Exception entry */\n#define ARM_PMU_EXC_RETURN                           0x000A             /*!< \\brief Exception return instruction architecturally executed and the condition code check pass */\n#define ARM_PMU_PC_WRITE_RETIRED                     0x000C             /*!< \\brief Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */\n#define ARM_PMU_BR_IMMED_RETIRED                     0x000D             /*!< \\brief Immediate branch architecturally executed */\n#define ARM_PMU_BR_RETURN_RETIRED                    0x000E             /*!< \\brief Function return instruction architecturally executed and the condition code check pass */\n#define ARM_PMU_UNALIGNED_LDST_RETIRED               0x000F             /*!< \\brief Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */\n#define ARM_PMU_BR_MIS_PRED                          0x0010             /*!< \\brief Mispredicted or not predicted branch speculatively executed */\n#define ARM_PMU_CPU_CYCLES                           0x0011             /*!< \\brief Cycle */\n#define ARM_PMU_BR_PRED                              0x0012             /*!< \\brief Predictable branch speculatively executed */\n#define ARM_PMU_MEM_ACCESS                           0x0013             /*!< \\brief Data memory access */\n#define ARM_PMU_L1I_CACHE                            0x0014             /*!< \\brief Level 1 instruction cache access */\n#define ARM_PMU_L1D_CACHE_WB                         0x0015             /*!< \\brief Level 1 data cache write-back */\n#define ARM_PMU_L2D_CACHE                            0x0016             /*!< \\brief Level 2 data cache access */\n#define ARM_PMU_L2D_CACHE_REFILL                     0x0017             /*!< \\brief Level 2 data cache refill */\n#define ARM_PMU_L2D_CACHE_WB                         0x0018             /*!< \\brief Level 2 data cache write-back */\n#define ARM_PMU_BUS_ACCESS                           0x0019             /*!< \\brief Bus access */\n#define ARM_PMU_MEMORY_ERROR                         0x001A             /*!< \\brief Local memory error */\n#define ARM_PMU_INST_SPEC                            0x001B             /*!< \\brief Instruction speculatively executed */\n#define ARM_PMU_BUS_CYCLES                           0x001D             /*!< \\brief Bus cycles */\n#define ARM_PMU_CHAIN                                0x001E             /*!< \\brief For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */\n#define ARM_PMU_L1D_CACHE_ALLOCATE                   0x001F             /*!< \\brief Level 1 data cache allocation without refill */\n#define ARM_PMU_L2D_CACHE_ALLOCATE                   0x0020             /*!< \\brief Level 2 data cache allocation without refill */\n#define ARM_PMU_BR_RETIRED                           0x0021             /*!< \\brief Branch instruction architecturally executed */\n#define ARM_PMU_BR_MIS_PRED_RETIRED                  0x0022             /*!< \\brief Mispredicted branch instruction architecturally executed */\n#define ARM_PMU_STALL_FRONTEND                       0x0023             /*!< \\brief No operation issued because of the frontend */\n#define ARM_PMU_STALL_BACKEND                        0x0024             /*!< \\brief No operation issued because of the backend */\n#define ARM_PMU_L2I_CACHE                            0x0027             /*!< \\brief Level 2 instruction cache access */\n#define ARM_PMU_L2I_CACHE_REFILL                     0x0028             /*!< \\brief Level 2 instruction cache refill */\n#define ARM_PMU_L3D_CACHE_ALLOCATE                   0x0029             /*!< \\brief Level 3 data cache allocation without refill */\n#define ARM_PMU_L3D_CACHE_REFILL                     0x002A             /*!< \\brief Level 3 data cache refill */\n#define ARM_PMU_L3D_CACHE                            0x002B             /*!< \\brief Level 3 data cache access */\n#define ARM_PMU_L3D_CACHE_WB                         0x002C             /*!< \\brief Level 3 data cache write-back */\n#define ARM_PMU_LL_CACHE_RD                          0x0036             /*!< \\brief Last level data cache read */\n#define ARM_PMU_LL_CACHE_MISS_RD                     0x0037             /*!< \\brief Last level data cache read miss */\n#define ARM_PMU_L1D_CACHE_MISS_RD                    0x0039             /*!< \\brief Level 1 data cache read miss */\n#define ARM_PMU_OP_COMPLETE                          0x003A             /*!< \\brief Operation retired */\n#define ARM_PMU_OP_SPEC                              0x003B             /*!< \\brief Operation speculatively executed */\n#define ARM_PMU_STALL                                0x003C             /*!< \\brief Stall cycle for instruction or operation not sent for execution */\n#define ARM_PMU_STALL_OP_BACKEND                     0x003D             /*!< \\brief Stall cycle for instruction or operation not sent for execution due to pipeline backend */\n#define ARM_PMU_STALL_OP_FRONTEND                    0x003E             /*!< \\brief Stall cycle for instruction or operation not sent for execution due to pipeline frontend */\n#define ARM_PMU_STALL_OP                             0x003F             /*!< \\brief Instruction or operation slots not occupied each cycle */\n#define ARM_PMU_L1D_CACHE_RD                         0x0040             /*!< \\brief Level 1 data cache read */\n#define ARM_PMU_LE_RETIRED                           0x0100             /*!< \\brief Loop end instruction executed */\n#define ARM_PMU_LE_SPEC                              0x0101             /*!< \\brief Loop end instruction speculatively executed */\n#define ARM_PMU_BF_RETIRED                           0x0104             /*!< \\brief Branch future instruction architecturally executed and condition code check pass */\n#define ARM_PMU_BF_SPEC                              0x0105             /*!< \\brief Branch future instruction speculatively executed and condition code check pass */\n#define ARM_PMU_LE_CANCEL                            0x0108             /*!< \\brief Loop end instruction not taken */\n#define ARM_PMU_BF_CANCEL                            0x0109             /*!< \\brief Branch future instruction not taken */\n#define ARM_PMU_SE_CALL_S                            0x0114             /*!< \\brief Call to secure function, resulting in Security state change */\n#define ARM_PMU_SE_CALL_NS                           0x0115             /*!< \\brief Call to non-secure function, resulting in Security state change */\n#define ARM_PMU_DWT_CMPMATCH0                        0x0118             /*!< \\brief DWT comparator 0 match */\n#define ARM_PMU_DWT_CMPMATCH1                        0x0119             /*!< \\brief DWT comparator 1 match */\n#define ARM_PMU_DWT_CMPMATCH2                        0x011A             /*!< \\brief DWT comparator 2 match */\n#define ARM_PMU_DWT_CMPMATCH3                        0x011B             /*!< \\brief DWT comparator 3 match */\n#define ARM_PMU_MVE_INST_RETIRED                     0x0200             /*!< \\brief MVE instruction architecturally executed */\n#define ARM_PMU_MVE_INST_SPEC                        0x0201             /*!< \\brief MVE instruction speculatively executed */\n#define ARM_PMU_MVE_FP_RETIRED                       0x0204             /*!< \\brief MVE floating-point instruction architecturally executed */\n#define ARM_PMU_MVE_FP_SPEC                          0x0205             /*!< \\brief MVE floating-point instruction speculatively executed */\n#define ARM_PMU_MVE_FP_HP_RETIRED                    0x0208             /*!< \\brief MVE half-precision floating-point instruction architecturally executed */\n#define ARM_PMU_MVE_FP_HP_SPEC                       0x0209             /*!< \\brief MVE half-precision floating-point instruction speculatively executed */\n#define ARM_PMU_MVE_FP_SP_RETIRED                    0x020C             /*!< \\brief MVE single-precision floating-point instruction architecturally executed */\n#define ARM_PMU_MVE_FP_SP_SPEC                       0x020D             /*!< \\brief MVE single-precision floating-point instruction speculatively executed */\n#define ARM_PMU_MVE_FP_MAC_RETIRED                   0x0214             /*!< \\brief MVE floating-point multiply or multiply-accumulate instruction architecturally executed */\n#define ARM_PMU_MVE_FP_MAC_SPEC                      0x0215             /*!< \\brief MVE floating-point multiply or multiply-accumulate instruction speculatively executed */\n#define ARM_PMU_MVE_INT_RETIRED                      0x0224             /*!< \\brief MVE integer instruction architecturally executed */\n#define ARM_PMU_MVE_INT_SPEC                         0x0225             /*!< \\brief MVE integer instruction speculatively executed */\n#define ARM_PMU_MVE_INT_MAC_RETIRED                  0x0228             /*!< \\brief MVE multiply or multiply-accumulate instruction architecturally executed */\n#define ARM_PMU_MVE_INT_MAC_SPEC                     0x0229             /*!< \\brief MVE multiply or multiply-accumulate instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_RETIRED                     0x0238             /*!< \\brief MVE load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_SPEC                        0x0239             /*!< \\brief MVE load or store instruction speculatively executed */\n#define ARM_PMU_MVE_LD_RETIRED                       0x023C             /*!< \\brief MVE load instruction architecturally executed */\n#define ARM_PMU_MVE_LD_SPEC                          0x023D             /*!< \\brief MVE load instruction speculatively executed */\n#define ARM_PMU_MVE_ST_RETIRED                       0x0240             /*!< \\brief MVE store instruction architecturally executed */\n#define ARM_PMU_MVE_ST_SPEC                          0x0241             /*!< \\brief MVE store instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_CONTIG_RETIRED              0x0244             /*!< \\brief MVE contiguous load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_CONTIG_SPEC                 0x0245             /*!< \\brief MVE contiguous load or store instruction speculatively executed */\n#define ARM_PMU_MVE_LD_CONTIG_RETIRED                0x0248             /*!< \\brief MVE contiguous load instruction architecturally executed */\n#define ARM_PMU_MVE_LD_CONTIG_SPEC                   0x0249             /*!< \\brief MVE contiguous load instruction speculatively executed */\n#define ARM_PMU_MVE_ST_CONTIG_RETIRED                0x024C             /*!< \\brief MVE contiguous store instruction architecturally executed */\n#define ARM_PMU_MVE_ST_CONTIG_SPEC                   0x024D             /*!< \\brief MVE contiguous store instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED           0x0250             /*!< \\brief MVE non-contiguous load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC              0x0251             /*!< \\brief MVE non-contiguous load or store instruction speculatively executed */\n#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED             0x0254             /*!< \\brief MVE non-contiguous load instruction architecturally executed */\n#define ARM_PMU_MVE_LD_NONCONTIG_SPEC                0x0255             /*!< \\brief MVE non-contiguous load instruction speculatively executed */\n#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED             0x0258             /*!< \\brief MVE non-contiguous store instruction architecturally executed */\n#define ARM_PMU_MVE_ST_NONCONTIG_SPEC                0x0259             /*!< \\brief MVE non-contiguous store instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_MULTI_RETIRED               0x025C             /*!< \\brief MVE memory instruction targeting multiple registers architecturally executed */\n#define ARM_PMU_MVE_LDST_MULTI_SPEC                  0x025D             /*!< \\brief MVE memory instruction targeting multiple registers speculatively executed */\n#define ARM_PMU_MVE_LD_MULTI_RETIRED                 0x0260             /*!< \\brief MVE memory load instruction targeting multiple registers architecturally executed */\n#define ARM_PMU_MVE_LD_MULTI_SPEC                    0x0261             /*!< \\brief MVE memory load instruction targeting multiple registers speculatively executed */\n#define ARM_PMU_MVE_ST_MULTI_RETIRED                 0x0261             /*!< \\brief MVE memory store instruction targeting multiple registers architecturally executed */\n#define ARM_PMU_MVE_ST_MULTI_SPEC                    0x0265             /*!< \\brief MVE memory store instruction targeting multiple registers speculatively executed */\n#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED           0x028C             /*!< \\brief MVE unaligned memory load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC              0x028D             /*!< \\brief MVE unaligned memory load or store instruction speculatively executed */\n#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED             0x0290             /*!< \\brief MVE unaligned load instruction architecturally executed */\n#define ARM_PMU_MVE_LD_UNALIGNED_SPEC                0x0291             /*!< \\brief MVE unaligned load instruction speculatively executed */\n#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED             0x0294             /*!< \\brief MVE unaligned store instruction architecturally executed */\n#define ARM_PMU_MVE_ST_UNALIGNED_SPEC                0x0295             /*!< \\brief MVE unaligned store instruction speculatively executed */\n#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298             /*!< \\brief MVE unaligned noncontiguous load or store instruction architecturally executed */\n#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC    0x0299             /*!< \\brief MVE unaligned noncontiguous load or store instruction speculatively executed */\n#define ARM_PMU_MVE_VREDUCE_RETIRED                  0x02A0             /*!< \\brief MVE vector reduction instruction architecturally executed */\n#define ARM_PMU_MVE_VREDUCE_SPEC                     0x02A1             /*!< \\brief MVE vector reduction instruction speculatively executed */\n#define ARM_PMU_MVE_VREDUCE_FP_RETIRED               0x02A4             /*!< \\brief MVE floating-point vector reduction instruction architecturally executed */\n#define ARM_PMU_MVE_VREDUCE_FP_SPEC                  0x02A5             /*!< \\brief MVE floating-point vector reduction instruction speculatively executed */\n#define ARM_PMU_MVE_VREDUCE_INT_RETIRED              0x02A8             /*!< \\brief MVE integer vector reduction instruction architecturally executed */\n#define ARM_PMU_MVE_VREDUCE_INT_SPEC                 0x02A9             /*!< \\brief MVE integer vector reduction instruction speculatively executed */\n#define ARM_PMU_MVE_PRED                             0x02B8             /*!< \\brief Cycles where one or more predicated beats architecturally executed */\n#define ARM_PMU_MVE_STALL                            0x02CC             /*!< \\brief Stall cycles caused by an MVE instruction */\n#define ARM_PMU_MVE_STALL_RESOURCE                   0x02CD             /*!< \\brief Stall cycles caused by an MVE instruction because of resource conflicts */\n#define ARM_PMU_MVE_STALL_RESOURCE_MEM               0x02CE             /*!< \\brief Stall cycles caused by an MVE instruction because of memory resource conflicts */\n#define ARM_PMU_MVE_STALL_RESOURCE_FP                0x02CF             /*!< \\brief Stall cycles caused by an MVE instruction because of floating-point resource conflicts */\n#define ARM_PMU_MVE_STALL_RESOURCE_INT               0x02D0             /*!< \\brief Stall cycles caused by an MVE instruction because of integer resource conflicts */\n#define ARM_PMU_MVE_STALL_BREAK                      0x02D3             /*!< \\brief Stall cycles caused by an MVE chain break */\n#define ARM_PMU_MVE_STALL_DEPENDENCY                 0x02D4             /*!< \\brief Stall cycles caused by MVE register dependency */\n#define ARM_PMU_ITCM_ACCESS                          0x4007             /*!< \\brief Instruction TCM access */\n#define ARM_PMU_DTCM_ACCESS                          0x4008             /*!< \\brief Data TCM access */\n#define ARM_PMU_TRCEXTOUT0                           0x4010             /*!< \\brief ETM external output 0 */\n#define ARM_PMU_TRCEXTOUT1                           0x4011             /*!< \\brief ETM external output 1 */\n#define ARM_PMU_TRCEXTOUT2                           0x4012             /*!< \\brief ETM external output 2 */\n#define ARM_PMU_TRCEXTOUT3                           0x4013             /*!< \\brief ETM external output 3 */\n#define ARM_PMU_CTI_TRIGOUT4                         0x4018             /*!< \\brief Cross-trigger Interface output trigger 4 */\n#define ARM_PMU_CTI_TRIGOUT5                         0x4019             /*!< \\brief Cross-trigger Interface output trigger 5 */\n#define ARM_PMU_CTI_TRIGOUT6                         0x401A             /*!< \\brief Cross-trigger Interface output trigger 6 */\n#define ARM_PMU_CTI_TRIGOUT7                         0x401B             /*!< \\brief Cross-trigger Interface output trigger 7 */\n\n/** @} */\n\n/**\n\\defgroup pmu8_events_armcm55  PMU Events for Cortex-M55\n\\ingroup pmu8_functions\n\\brief IDs for additional events defined for Cortex-M55.\n\\details\nThese events are available on a Cortex-M55 device including a PMU.\n@{\n*/\n\n#define ARMCM55_PMU_ECC_ERR                          0xC000             /*!< \\brief Any ECC error */\n#define ARMCM55_PMU_ECC_ERR_FATAL                    0xC001             /*!< \\brief Any fatal ECC error */\n#define ARMCM55_PMU_ECC_ERR_DCACHE                   0xC010             /*!< \\brief Any ECC error in the data cache */\n#define ARMCM55_PMU_ECC_ERR_ICACHE                   0xC011             /*!< \\brief Any ECC error in the instruction cache */\n#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE             0xC012             /*!< \\brief Any fatal ECC error in the data cache */\n#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE             0xC013             /*!< \\brief Any fatal ECC error in the instruction cache*/\n#define ARMCM55_PMU_ECC_ERR_DTCM                     0xC020             /*!< \\brief Any ECC error in the DTCM */\n#define ARMCM55_PMU_ECC_ERR_ITCM                     0xC021             /*!< \\brief Any ECC error in the ITCM */\n#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM               0xC022             /*!< \\brief Any fatal ECC error in the DTCM */\n#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM               0xC023             /*!< \\brief Any fatal ECC error in the ITCM */\n#define ARMCM55_PMU_PF_LINEFILL                      0xC100             /*!< \\brief A prefetcher starts a line-fill */\n#define ARMCM55_PMU_PF_CANCEL                        0xC101             /*!< \\brief A prefetcher stops prefetching */\n#define ARMCM55_PMU_PF_DROP_LINEFILL                 0xC102             /*!< \\brief A linefill triggered by a prefetcher has been dropped because of lack of buffering */\n#define ARMCM55_PMU_NWAMODE_ENTER                    0xC200             /*!< \\brief No write-allocate mode entry */\n#define ARMCM55_PMU_NWAMODE                          0xC201             /*!< \\brief Write-allocate store is not allocated into the data cache due to no-write-allocate mode */\n#define ARMCM55_PMU_SAHB_ACCESS                      0xC300             /*!< \\brief Read or write access on the S-AHB interface to the TCM */\n#define ARMCM55_PMU_SAHB_ACCESS                      0xC300             /*!< \\brief Read or write access on the S-AHB interface to the TCM */\n#define ARMCM55_PMU_PAHB_ACCESS                      0xC301             /*!< \\brief Read or write access on the P-AHB interface */\n#define ARMCM55_PMU_AXI_WRITE_ACCESS                 0xC302             /*!< \\brief Any beat access to M-AXI write interface */\n#define ARMCM55_PMU_AXI_READ_ACCESS                  0xC303             /*!< \\brief Any beat access to M-AXI read interface */\n#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE                0xC400             /*!< \\brief Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */\n#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE                0xC401             /*!< \\brief Denial of Service timeout has fired three times and blocked the LSU to force forward progress */\n\n/** @} */\n\n/**\n\\defgroup pmu8_events_armcm85  PMU Events for Cortex-M85\n\\ingroup pmu8_functions\n\\brief IDs for additional events defined for Cortex-M85.\n\\details\nThese events are available on a Cortex-M85 device including a PMU.\n@{\n*/\n\n#define ARMCM85_PMU_ECC_ERR                          0xC000             /*!< \\brief Any ECC error */\n#define ARMCM85_PMU_ECC_ERR_MBIT                     0xC001             /*!< \\brief Any multi-bit ECC error */\n#define ARMCM85_PMU_ECC_ERR_DCACHE                   0xC010             /*!< \\brief Any ECC error in the data cache */\n#define ARMCM85_PMU_ECC_ERR_ICACHE                   0xC011             /*!< \\brief Any ECC error in the instruction cache */\n#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE              0xC012             /*!< \\brief Any multi-bit ECC error in the data cache */\n#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE              0xC013             /*!< \\brief Any multi-biy ECC error in the instruction cache*/\n#define ARMCM85_PMU_ECC_ERR_DTCM                     0xC020             /*!< \\brief Any ECC error in the DTCM */\n#define ARMCM85_PMU_ECC_ERR_ITCM                     0xC021             /*!< \\brief Any ECC error in the ITCM */\n#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM                0xC022             /*!< \\brief Any multi-bit ECC error in the DTCM */\n#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM                0xC023             /*!< \\brief Any multi-bit ECC error in the ITCM */\n#define ARMCM85_PMU_PF_LINEFILL                      0xC100             /*!< \\brief A prefetcher starts a line-fill */\n#define ARMCM85_PMU_PF_CANCEL                        0xC101             /*!< \\brief A prefetcher stops prefetching */\n#define ARMCM85_PMU_PF_DROP_LINEFILL                 0xC102             /*!< \\brief A linefill triggered by a prefetcher has been dropped because of lack of buffering */\n#define ARMCM85_PMU_NWAMODE_ENTER                    0xC200             /*!< \\brief No write-allocate mode entry */\n#define ARMCM85_PMU_NWAMODE                          0xC201             /*!< \\brief Write-allocate store is not allocated into the data cache due to no-write-allocate mode */\n#define ARMCM85_PMU_SAHB_ACCESS                      0xC300             /*!< \\brief Read or write access on the S-AHB interface to the TCM */\n#define ARMCM85_PMU_PAHB_ACCESS                      0xC301             /*!< \\brief Read or write access on the P-AHB interface */\n#define ARMCM85_PMU_AXI_WRITE_ACCESS                 0xC302             /*!< \\brief Any beat access to M-AXI write interface  */\n#define ARMCM85_PMU_AXI_READ_ACCESS                  0xC303             /*!< \\brief Any beat access to M-AXI read interface */\n#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE                0xC400             /*!< \\brief Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */\n#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE                0xC401             /*!< \\brief Denial of Service timeout has fired three times and blocked the LSU to force forward progress */\n\n/** @} */\n\n\n/**\n  \\brief  Structure type to access the Performance Monitoring Unit (PMU).\n */\ntypedef struct\n{\n  __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT];        /*!< Offset: 0x0 (R/W)    \\brief PMU Event Counter Registers \\details Two up to 31 event counters, see device specific \\ref __PMU_NUM_EVENTCNT */\n//      uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; \n  __IOM uint32_t CCNTR;                             /*!< Offset: 0x7C (R/W)   \\brief PMU Cycle Counter Register */\n//      uint32_t RESERVED1[224];                    \n  __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT];       /*!< Offset: 0x400 (R/W)  \\brief PMU Event Type and Filter Registers \\details Two up to 31 event counters, see device specific \\ref __PMU_NUM_EVENTCNT */\n//      uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; \n  __IOM uint32_t CCFILTR;                           /*!< Offset: 0x47C (R/W)  \\brief PMU Cycle Counter Filter Register */\n//      uint32_t RESERVED3[480];                    \n  __IOM uint32_t CNTENSET;                          /*!< Offset: 0xC00 (R/W)  \\brief PMU Count Enable Set Register */\n//      uint32_t RESERVED4[7];                      \n  __IOM uint32_t CNTENCLR;                          /*!< Offset: 0xC20 (R/W)  \\brief PMU Count Enable Clear Register */\n//      uint32_t RESERVED5[7];                      \n  __IOM uint32_t INTENSET;                          /*!< Offset: 0xC40 (R/W)  \\brief PMU Interrupt Enable Set Register */\n//      uint32_t RESERVED6[7];                      \n  __IOM uint32_t INTENCLR;                          /*!< Offset: 0xC60 (R/W)  \\brief PMU Interrupt Enable Clear Register */\n//      uint32_t RESERVED7[7];                      \n  __IOM uint32_t OVSCLR;                            /*!< Offset: 0xC80 (R/W)  \\brief PMU Overflow Flag Status Clear Register */\n//      uint32_t RESERVED8[7];                      \n  __IOM uint32_t SWINC;                             /*!< Offset: 0xCA0 (R/W)  \\brief PMU Software Increment Register */\n//      uint32_t RESERVED9[7];                      \n  __IOM uint32_t OVSSET;                            /*!< Offset: 0xCC0 (R/W)  \\brief PMU Overflow Flag Status Set Register */\n//      uint32_t RESERVED10[79];                    \n  __IOM uint32_t TYPE;                              /*!< Offset: 0xE00 (R/W)  \\brief PMU Type Register */\n  __IOM uint32_t CTRL;                              /*!< Offset: 0xE04 (R/W)  \\brief PMU Control Register */\n//      uint32_t RESERVED11[108];                   \n  __IOM uint32_t AUTHSTATUS;                        /*!< Offset: 0xFB8 (R/W)  \\brief PMU Authentication Status Register */\n  __IOM uint32_t DEVARCH;                           /*!< Offset: 0xFBC (R/W)  \\brief PMU Device Architecture Register */\n//      uint32_t RESERVED12[4];                     \n  __IOM uint32_t DEVTYPE;                           /*!< Offset: 0xFCC (R/W)  \\brief PMU Device Type Register */\n  __IOM uint32_t PIDR4;                             /*!< Offset: 0xFD0 (R/W)  \\brief PMU Peripheral Identification Register 4 */\n//      uint32_t RESERVED13[3];                     \n  __IOM uint32_t PIDR0;                             /*!< Offset: 0xFE0 (R/W)  \\brief PMU Peripheral Identification Register 0 */\n  __IOM uint32_t PIDR1;                             /*!< Offset: 0xFE4 (R/W)  \\brief PMU Peripheral Identification Register 1 */\n  __IOM uint32_t PIDR2;                             /*!< Offset: 0xFE8 (R/W)  \\brief PMU Peripheral Identification Register 2 */\n  __IOM uint32_t PIDR3;                             /*!< Offset: 0xFEC (R/W)  \\brief PMU Peripheral Identification Register 3 */\n//      uint32_t RESERVED14[3];                     \n  __IOM uint32_t CIDR0;                             /*!< Offset: 0xFF0 (R/W)  \\brief PMU Component Identification Register 0 */\n  __IOM uint32_t CIDR1;                             /*!< Offset: 0xFF4 (R/W)  \\brief PMU Component Identification Register 1 */\n  __IOM uint32_t CIDR2;                             /*!< Offset: 0xFF8 (R/W)  \\brief PMU Component Identification Register 2 */\n  __IOM uint32_t CIDR3;                             /*!< Offset: 0xFFC (R/W)  \\brief PMU Component Identification Register 3 */\n} PMU_Type;\n\n/**\n  \\brief PMU configuration struct \n  \\details\n  This macro can be used to access the PMU registers, directly. For the common tasks\n  one should prefer using the control functions.\n  \n  Example:\n  <b>Example:</b>\n  \\code\n  PMU->CTRL |= PMU_CTRL_ENABLE_Msk; // Enable PMU\n  \\endcode\n*/\n#define PMU\n\n/** \n  \\brief   Enable the PMU\n*/\n__STATIC_INLINE void ARM_PMU_Enable(void);\n\n/** \n  \\brief   Disable the PMU\n*/\n__STATIC_INLINE void ARM_PMU_Disable(void); \n\n/** \n  \\brief   Set event to count for PMU event counter\n  \\param [in]    num     Event counter (0-30) to configure\n  \\param [in]    type    Event to count\n*/\n__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);\n\n/** \n  \\brief  Reset cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);\n\n/** \n  \\brief  Reset all event counters\n*/\n__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);\n\n/** \n  \\brief  Enable counters \n  \\param [in]     mask    Counters to enable\n  \\note   Enables one or more of the following:\n          - event counters (0-30)\n          - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);\n\n/** \n  \\brief  Disable counters\n  \\param [in]     mask    Counters to enable\n  \\note   Disables one or more of the following:\n          - event counters (0-30)\n          - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);\n\n/** \n  \\brief  Read cycle counter\n  \\return                 Cycle count\n*/\n__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);\n\n/** \n  \\brief   Read event counter\n  \\param [in]     num     Event counter (0-30) to read\n  \\return                 Event count\n*/\n__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);\n\n/** \n  \\brief   Read counter overflow status\n  \\return  Counter overflow status bits for the following:\n          - event counters (0-30)\n          - cycle counter\n*/\n__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);\n\n/** \n  \\brief   Clear counter overflow status\n  \\param [in]     mask    Counter overflow status bits to clear\n  \\note    Clears overflow status bits for one or more of the following:\n           - event counters (0-30)\n           - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);\n\n/** \n  \\brief   Enable counter overflow interrupt request \n  \\param [in]     mask    Counter overflow interrupt request bits to set\n  \\note    Sets overflow interrupt request bits for one or more of the following:\n           - event counters (0-30)\n           - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);\n\n/** \n  \\brief   Disable counter overflow interrupt request \n  \\param [in]     mask    Counter overflow interrupt request bits to clear\n  \\note    Clears overflow interrupt request bits for one or more of the following:\n           - event counters (0-30)\n           - cycle counter\n*/\n__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);\n\n/** \n  \\brief   Software increment event counter \n  \\param [in]     mask    Counters to increment\n  \\note    Software increment bits for one or more event counters (0-30)\n*/\n__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);\n\n/** @} */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Peripheral.txt",
    "content": "/**************************************************************************************************/\n/**\n    \\defgroup   peripheral_gr    Peripheral Access\n    \\brief      Naming conventions and optional features for accessing peripherals.\n    \\details\n\t\nThe section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals.\nMost of the rules also apply to the core peripherals.  The \\ref device_h_pg contains typically these definition and also includes\nthe core specific header files.\n\n\\ifnot FuSaRTS\nThe definitions for \\ref peripheral_gr can be generated using the <a href=\"../../SVD/html/index.html\"><b>CMSIS-SVD</b></a> System View Description for Peripherals.\nRefer to <a href=\"../../SVD/html/svd_SVDConv_pg.html\"><b>SVDConv.exe</b></a> for more information.\n\\endif\n\t\nEach peripheral provides a data type definition with a name that is composed of:\n  - an optional prefix <b>&lt;<i>device abbreviation&gt;</i>_</b>\n  - <b>&lt;<i>peripheral name</i>&gt;</b>\n  - postfix \\b _Type or \\b _TypeDef to identify a type definition.\n\nExamples:\n  - \\b UART_TypeDef for the peripheral \\b UART.\n  - \\b LPC_UART_TypeDef for the device family \\b LPC and the peripheral \\b UART.\n\nThe data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.\n \n - IO Type Qualifiers are used to specify the access to peripheral variables.\n   IO Type Qualifier  | Type            | Description\n   :------------------|:----------------|:------------\n   \\b __IM            | Struct member   | Defines 'read only' permissions\n   \\b __OM            | Struct member   | Defines 'write only' permissions\n   \\b __IOM           | Struct member   | Defines 'read / write' permissions\n   \\b __I             | Scalar variable | Defines 'read only' permissions\n   \\b __O             | Scalar variable | Defines 'write only' permissions\n   \\b __IO            | Scalar variable | Defines 'read / write' permissions\n   \n\\note \n\\b __IM, \\b __OM, \\b __IOM are added in CMSIS-Core V4.20 to enhance support for C++. Prior version used \\b __I, \\b __O, \\b __IO also for struct member definitions.\n\nThe typedef <b>\\<<i>device abbreviation</i>\\>_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.\n\n\\code\ntypedef struct\n{\n  union {\n  __IM  uint8_t  RBR;                 /* Offset: 0x000 (R/ )  Receiver Buffer Register            */\n  __OM  uint8_t  THR;                 /* Offset: 0x000 ( /W)  Transmit Holding Register           */\n  __IOM uint8_t  DLL;                 /* Offset: 0x000 (R/W)  Divisor Latch LSB                   */\n        uint32_t RESERVED0;\n  };\n  union {\n  __IOM uint8_t  DLM;                 /* Offset: 0x004 (R/W)  Divisor Latch MSB                   */\n  __IOM uint32_t IER;                 /* Offset: 0x004 (R/W)  Interrupt Enable Register           */\n  };\n  union {\n  __IM  uint32_t IIR;                 /* Offset: 0x008 (R/ )  Interrupt ID Register               */\n  __OM  uint8_t  FCR;                 /* Offset: 0x008 ( /W)  FIFO Control Register               */\n  };\n  __IOM uint8_t  LCR;                 /* Offset: 0x00C (R/W)  Line Control Register               */\n        uint8_t  RESERVED1[7];\n  __IM  uint8_t  LSR;                 /* Offset: 0x014 (R/ )  Line Status Register                */\n        uint8_t  RESERVED2[7];\n  __IOM uint8_t  SCR;                 /* Offset: 0x01C (R/W)  Scratch Pad Register                */\n        uint8_t  RESERVED3[3];\n  __IOM uint32_t ACR;                 /* Offset: 0x020 (R/W)  Autobaud Control Register           */\n  __IOM uint8_t  ICR;                 /* Offset: 0x024 (R/W)  IrDA Control Register               */\n        uint8_t  RESERVED4[3];\n  __IOM uint8_t  FDR;                 /* Offset: 0x028 (R/W)  Fractional Divider Register         */\n        uint8_t  RESERVED5[7];\n  __IOM uint8_t  TER;                 /* Offset: 0x030 (R/W)  Transmit Enable Register            */\n        uint8_t  RESERVED6[39];\n  __IM  uint8_t  FIFOLVL;             /* Offset: 0x058 (R/ )  FIFO Level Register                 */\n} LPC_UART_TypeDef;\n\\endcode\n\nTo access the registers of the UART defined above, pointers to this register structure are defined.\nIf more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.\n\n\\b Example:\nIn this example \\b LPC_UART2 and \\b LPC_UART3 are two pointers to UARTs defined with above register structure.\n\\n\n\\code\n#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )\n#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )\n\\endcode\n\n\\note \n - The prefix <b>LPC</b> is optional.\n \nThe registers in the various UARTs can now be referred in the user code as shown below:\\n\n\\code\n val = LPC_UART2->DR   // is the data register of UART1.\n\\endcode\n\n<hr>\n\n\\section core_cmsis_pal_min_reqs Minimal Requirements\n\\details\n To access the peripheral registers and related function in a device, the files <b><i>device.h</i></b> and <b>core_cm<i>#</i>.h</b> define as a minimum:\n\\n\\n\n- The <b>Register Layout Typedef</b> for each peripheral that defines all register names.\n  RESERVED is used to introduce space into the structure for adjusting the addresses of\n  the peripheral registers.\n\\n\\n\n<b>Example:</b>\n\\code\ntypedef struct\n{\n  __IOM uint32_t CTRL;                /* Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                /* Offset: 0x004 (R/W)  SysTick Reload Value Register       */\n  __IOM uint32_t VAL;                 /* Offset: 0x008 (R/W)  SysTick Current Value Register      */\n  __IM  uint32_t CALIB;               /* Offset: 0x00C (R/ )  SysTick Calibration Register        */\n} SysTick_Type;\n    \\endcode\n\n\n- <b>Base Address</b> for each peripheral (in case of multiple peripherals\n    that use the same <b>register layout typedef</b> multiple base addresses are defined).\n    \\n\\n\n<b>Example:</b>\n\\code\n#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address     */\n\\endcode\n\n\n- <b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same\n    <b>register layout typdef</b>, multiple access definitions exist (LPC_UART0, LPC_UART2).\n    \\n\\n\n<b>Example:</b>\n\\code\n#define SysTick ((SysTick_Type *) Systick_BASE)    /* SysTick access definition */\n\\endcode\n\n\nThese definitions allow accessing peripheral registers with simple assignments.\n\n- <b>Example:</b>\n  \\n\n\\code\nSysTick->CTRL = 0;\n\\endcode\n\n<hr>\n\n\\section core_cmsis_pal_opts Optional Features\n\\details\nOptionally, the file <b><i>device</i>.h</b> may define:\n\n-  \\ref core_cmsis_pal_bitfields and \\#define constants that simplify access to peripheral registers.\n\tThese constants may define bit-positions or other specific patterns that are required for\n    programming peripheral registers. The identifiers should start with\n    <b>&lt;<i>device abbreviation</i>&gt;_</b> and <b>&lt;<i>peripheral name</i>&gt;_</b>.\n    It is recommended to use CAPITAL letters for \\#define constants.\n\n-   More complex functions (i.e. status query before\n    a sending register is accessed). Again, these functions start with\n    <b>&lt;<i>device abbreviation</i>&gt;_</b> and <b>&lt;<i>peripheral name</i>&gt;_</b>.\n\n<hr>\n\n\\section core_cmsis_pal_bitfields Register Bit Fields\n\\details\n\nFor Core Register, macros define the position and the mask value for a bit field. It is recommended to create such definitions also\nfor other peripheral registers.\n\n<b>Example:</b>\n\nBit field definitions for register CPUID in SCB (System Control Block).\n\n\n\\code\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos      24U                                       /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk      (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)     /*!< SCB CPUID: IMPLEMENTER Mask */\n                                                                                 \n#define SCB_CPUID_VARIANT_Pos          20U                                       /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk          (0xFUL << SCB_CPUID_VARIANT_Pos)          /*!< SCB CPUID: VARIANT Mask */\n                                                                                 \n#define SCB_CPUID_ARCHITECTURE_Pos     16U                                       /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk     (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)     /*!< SCB CPUID: ARCHITECTURE Mask */\n                                                                                 \n#define SCB_CPUID_PARTNO_Pos            4U                                       /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk           (0xFFFUL << SCB_CPUID_PARTNO_Pos)         /*!< SCB CPUID: PARTNO Mask */\n                                                                                 \n#define SCB_CPUID_REVISION_Pos          0U                                       /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk         (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)     /*!< SCB CPUID: REVISION Mask */\n\\endcode\n\nThe macros <b>_VAL2FLD(field, value)</b> and <b>_FLD2VAL(field, value)</b> enable access to bit fields.\n@{\n*/\n\n/**\n\\def _VAL2FLD(field, value)\n\\param         field        name of bit field.\n\\param         value        value for the bit field. This parameter is interpreted as an uint32_t type.\n\\brief Mask and shift a bit field value for assigning the result to a peripheral register.\n\\details\nThe macro \\ref _VAL2FLD uses the \\#define's <i>_Pos</i> and <i>_Msk</i> of the related bit field to shift bit-field values for\nassigning to a register.\n \n<b>Example:</b>\n\\code\n  SCB->CPUID = _VAL2FLD(SCB_CPUID_REVISION, 0x3) | _VAL2FLD(SCB_CPUID_VARIANT, 0x3);\n\\endcode\n\n*/\n#define _VAL2FLD(field, value)\n\n/**\n \n\\def _FLD2VAL(field, value)\n\\param         field        name of bit field.\n\\param         value        value of the register. This parameter is interpreted as an uint32_t type.\n\\brief Extract from a peripheral register value the a bit field value.\n\\details\nThe macro \\ref _FLD2VAL uses the \\#define's <i>_Pos</i> and <i>_Msk</i> of the related bit field to extract the value of a bit field from a register.\n \n<b>Example:</b>\n\\code\n  id = _FLD2VAL(SCB_CPUID_REVISION, SCB->CPUID);\n\\endcode\n\n*/\n#define _FLD2VAL(field, value)\n\n/**\n@} \n\n*/"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_SystemAndClock.txt",
    "content": "/* ################################  System and Clock Configuration   ########################### */\n/**************************************************************************************************/\n/**\n\\defgroup   system_init_gr   System and Clock Configuration\n\\brief Functions for system and clock setup available in system_<i>device</i>.c.\n\\details\nArm provides a template file <b>system_<i>device</i>.c</b> that must be adapted by \nthe silicon vendor to match their actual device. As a <b>minimum requirement</b>, \nthis file must provide:\n -  A device-specific system configuration function, \\ref SystemInit().\n -  A global variable that contains the system frequency, \\ref SystemCoreClock. \n\nThe file configures the device and, typically, initializes the oscillator (PLL) that is part \nof the microcontroller device. This file might export other functions or variables that provide \na more flexible configuration of the microcontroller system.\n\n\\note Please pay special attention to the static variable \\c SystemCoreClock. This variable might be\nused throughout the whole system initialization and runtime to calculate frequency/time related values.\nThus one must assure that the variable always reflects the actual system clock speed. Be aware that\na value stored to \\c SystemCoreClock during low level initialization (i.e. \\c SystemInit()) might get\noverwritten by C library startup code and/or .bss section initialization.\nThus its highly recommended to call \\ref SystemCoreClockUpdate at the beginning of the user \\c main() routine.\n\n\n\\section system_init_code_ex_sec Code Example     \nThe code below shows the usage of the variable \\ref SystemCoreClock and the functions \nSystemInit() and SystemCoreClockUpdate() with an LPC1700.\n    \n\\code\n#include \"LPC17xx.h\"\n\nuint32_t coreClock_1 = 0;                       /* Variables to store core clock values */\nuint32_t coreClock_2 = 0;\n\n\nint main (void)  {\n\n  coreClock_1 = SystemCoreClock;                /* Store value of predefined SystemCoreClock */\n\n  SystemCoreClockUpdate();                      /* Update SystemCoreClock according to register settings */\n\n  coreClock_2 = SystemCoreClock;                /* Store value of calculated SystemCoreClock */\n\n  if (coreClock_2 != coreClock_1)  {            /* Without changing the clock setting both core clock values should be the same */ \n    // Error Handling\n  }\n\n  while(1);\n}\n\\endcode    \n    \n@{\n*/\n\n\n/**************************************************************************************************/\n/** \n    \\brief      Variable to hold the system core clock value\n    \\details\n    Holds the system core clock, which is the system clock\tfrequency supplied to the SysTick \n    timer and the processor core clock. This variable can be used by debuggers to query the \n    frequency of the debug timer or to configure the trace clock speed.\n                     \n    \\attention  Compilers must be configured to avoid removing this variable in case the application \n                program is not using it. Debugging systems require the variable to be physically \n                present in memory so that it can be examined to configure the debugger.\n*/\nuint32_t SystemCoreClock;\n\n\n/**************************************************************************************************/\n/** \n    \\brief      Function to Initialize the system.\n    \\details    \n    Initializes the microcontroller system. Typically, this function configures the \n                     oscillator (PLL) that is part of the microcontroller device. For systems \n                     with a variable clock speed, it updates the variable \\ref SystemCoreClock.\n                     SystemInit is called from the file <b>startup<i>_device</i></b>.\n*/\nvoid SystemInit (void);\n\n\n/**************************************************************************************************/\n/** \n    \\brief      Function to update the variable \\ref SystemCoreClock\n    \\details    \n    Updates the variable \\ref SystemCoreClock and must be called whenever the core clock is changed \n    during program execution. The function evaluates the clock register settings and calculates \n    the current core clock.\n*/\nvoid SystemCoreClockUpdate (void);\n\n\n/** @} */  /* end group system_init_gr */\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Systick.txt",
    "content": "/* ##################################    SysTick function  ###################################### */\n/** \n\\defgroup    SysTick_gr Systick Timer (SYSTICK)\n\\brief       Initialize and start the SysTick timer.\n\\details\n    The System Tick Time (SysTick) generates interrupt requests on a regular basis.\n    This allows an OS to carry out context switching to support multiple tasking. For applications\n    that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an \n    interrupt source for tasks that need to be executed regularly.\n    \n\n\\section SysTick_code_ex_sec Code Example     \n    The code below shows the usage of the function SysTick_Config() with an LPC1700.\n    \n\\code\n#include \"LPC17xx.h\"\n  \nvolatile uint32_t msTicks = 0;                              /* Variable to store millisecond ticks */\n  \nvoid SysTick_Handler(void)  {                               /* SysTick interrupt Handler. */\n  msTicks++;                                                /* See startup file startup_LPC17xx.s for SysTick vector */ \n}\n  \nint main (void)  {\n  uint32_t returnCode;\n  \n  returnCode = SysTick_Config(SystemCoreClock / 1000);      /* Configure SysTick to generate an interrupt every millisecond */\n  \n  if (returnCode != 0)  {                                   /* Check return code for errors */\n    // Error Handling \n  }\n  \n  while(1);\n}\n\\endcode    \n    \n@{\n*/\n\n\n/**************************************************************************************************/\n/** \\brief  System Tick Timer Configuration\n    \\details\n    Initialises and starts the System Tick Timer and its interrupt.\n    After this call, the SysTick timer creates interrupts with the specified time interval. \n    Counter is in free running mode to generate periodical interrupts.   \n\n    \\param [in]  ticks  Number of ticks between two interrupts\n\n    \\returns          0  - success\n    \\returns          1  - failure\n    \n    \\note\n    When \\ref __Vendor_SysTickConfig is defined to 1, the standard function <b>SysTick_Config</b>\n    is excluded. In this case, the \\ref device_h_pg must contain a vendor specific implementation\n    of this function. \n*/\nuint32_t SysTick_Config(uint32_t ticks);\n\n/** @} */"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt",
    "content": "/**\n\\cond (ARMv8M)\n*/\n\n/**\n\\defgroup trustzone_functions TrustZone for Armv8-M/v8.1-M\n\\brief Functions that related to optional Armv8-M and Armv8.1-M security extension\n  @{\n\\details\nThe Armv8-M architecture has optional Armv8-M security extension based on Arm TrustZone technology.\nTo access Arm TrustZone extensions for Armv8-M additional CMSIS functions are provided:\n - \\ref coreregister_trustzone_functions\n - \\ref nvic_trustzone_functions\n - \\ref systick_trustzone_functions\n - \\ref sau_trustzone_functions\n - \\ref stacksealing_support_trustzone_functions\n - \\ref context_trustzone_functions\n*/\n\n/**\n  \\defgroup coreregister_trustzone_functions Core Register Access Functions\n  \\brief Core register Access functions related to TrustZone for Armv8-M.\n  @{\n*/\n\n/**\n  \\brief   Get Control register (non-secure)\n  \\details Returns the content of the non-secure Control register when in secure mode.\n  \\return               non-secure Control register value\n  \\sa     \n    - \\ref __get_CONTROL; CONTROL_Type \n */\nuint32_t __TZ_get_CONTROL_NS(void);\n\n/**\n  \\brief   Set Control register (non-secure)\n  \\details Writes the given value to the non-secure Control register when in secure state.\n  \\param [in]    control  Control register value to set\n  \\sa     \n    - \\ref __set_CONTROL; CONTROL_Type \n */\nvoid __TZ_set_CONTROL_NS(uint32_t control);\n\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP register value\n  \\sa     \n    - \\ref __get_PSP\n */\nuint32_t __TZ_get_PSP_NS(void);\n\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n  \\sa     \n    - \\ref __set_PSP\n */\nvoid __TZ_set_PSP_NS(uint32_t topOfProcStack);\n\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP register value\n  \\sa     \n    - \\ref __get_MSP\n */\nuint32_t __TZ_get_MSP_NS(void);\n\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n  \\sa     \n    - \\ref __set_MSP\n */\nvoid __TZ_set_MSP_NS(uint32_t topOfMainStack);\n\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP register value\n */\nuint32_t __TZ_get_SP_NS(void);\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\nvoid __TZ_set_SP_NS(uint32_t topOfStack);\n\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask register when in secure state.\n  \\return               Priority Mask value\n  \\sa     \n    - \\ref __get_PRIMASK\n */\nuint32_t __TZ_get_PRIMASK_NS(void);\n\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask register when in secure state.\n  \\param [in]    priMask  Priority Mask\n  \\sa     \n    - \\ref __set_PRIMASK\n */\nvoid __TZ_set_PRIMASK_NS(uint32_t priMask);\n\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n  \\sa     \n    - \\ref __get_BASEPRI\n */\nuint32_t __TZ_get_BASEPRI_NS(void);\n\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n  \\sa     \n    - \\ref __set_BASEPRI\n */\nvoid __TZ_set_BASEPRI_NS(uint32_t basePri);\n\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n  \\sa     \n    - \\ref __get_FAULTMASK\n */\nuint32_t __TZ_get_FAULTMASK_NS(void);\n\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n  \\sa     \n    - \\ref __set_FAULTMASK\n */\nvoid __TZ_set_FAULTMASK_NS(uint32_t faultMask);\n\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM register value \n */\nuint32_t __TZ_get_PSPLIM_NS(void);\n\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\nvoid __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit);\n\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n  \n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM register value\n */\nuint32_t __TZ_get_MSPLIM_NS(void);\n\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\nvoid __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit);\n\n/** close coreregister_trustzone_functions\n  @}\n*/\n\n/**\n  \\defgroup nvic_trustzone_functions NVIC Functions\n  \\brief Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M \n  @{\n*/\n\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n  \\note    Only available for Armv8-M Mainline. \n  \\sa     \n    - \\ref NVIC_SetPriorityGrouping\n */\nvoid TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup);\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n  \\note    Only available for Armv8-M Mainline. \n  \\sa     \n    - \\ref NVIC_GetPriorityGrouping\n */\nuint32_t TZ_NVIC_GetPriorityGrouping_NS(void);\n\n/**\n  \\brief   Enable External Interrupt (non-secure)\n  \\details Enables a device-specific interrupt in the non-secure NVIC when in secure state.\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\n  \\sa     \n    - \\ref NVIC_EnableIRQ\n */\nvoid TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn);\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\sa     \n    - \\ref NVIC_EnableIRQ; NVIC_DisableIRQ;\n */\nuint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn);\n\n/**\n  \\brief   Disable External Interrupt (non-secure)\n  \\details Disables a device-specific interrupt in the non-secure NVIC when in secure state.\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\n  \\sa     \n    - \\ref NVIC_DisableIRQ\n */\nvoid TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn);\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified interrupt.\n  \\param [in]      IRQn  Interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\sa     \n    - \\ref NVIC_GetPendingIRQ\n */\nuint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn);\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of an non-secure external interrupt when in secure state.\n  \\param [in]      IRQn  Interrupt number. Value cannot be negative.\n  \\sa     \n    - \\ref NVIC_SetPendingIRQ\n */\nvoid TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn);\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of an non-secure external interrupt when in secure state.\n  \\param [in]      IRQn  External interrupt number. Value cannot be negative.\n  \\sa     \n    - \\ref NVIC_ClearPendingIRQ\n */\nvoid TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn);\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit.\n  \\param [in]      IRQn  Interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\sa     \n    - \\ref NVIC_GetActive\n */\nuint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn);\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of an non-secure interrupt when in secure state.\n  \\note    The priority cannot be set for every core interrupt.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\sa     \n    - \\ref NVIC_SetPriority\n */\nvoid TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority);\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of an non-secure interrupt when in secure state.\n           The interrupt number can be positive to specify an external (device specific) interrupt,\n           or negative to specify an internal (core) interrupt.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n  \\sa     \n    - \\ref NVIC_GetPriority\n */\nuint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn);\n\n/** close nvic_trustzone_functions\n  @}\n*/\n\n\n/**\n  \\defgroup systick_trustzone_functions SysTick Functions\n  \\brief SysTick functions related to TrustZone for Armv8-M.\n  @{\n*/\n\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n  \\sa     \n    - \\ref SysTick_Config\n */\nuint32_t TZ_SysTick_Config_NS(uint32_t ticks);\n\n/** close systick_trustzone_functions\n  @}\n*/\n\n\n/**\n  \\defgroup sau_trustzone_functions SAU Functions\n  \\brief Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M.\n  @{\n\\details\nThe Secure Attribution Unit (SAU) functions SAU \n\n\\note\nA SAU is always present if the security extension is available.\nThe functionality differs if the SAU contains SAU regions.\nIf SAU regions are available is configured with the macro __SAUREGION_PRESENT (see \\ref core_config_sect).\n\n */\n\n/**\n\\brief   Setup Secure Attribute Unit (SAU) and non-secure interrupts\n\\details \nThe function \\ref TZ_SAU_Setup uses the settings in the \\ref partition_h_pg to initialize\nthe Secure Attribute Unit (SAU) and define non-secure interrupts.  It is called from\nthe function \\ref SystemInit.\n */\nvoid TZ_SAU_Setup (void);\n\n/**\n  \\brief   Enable Security Attribution Unit (SAU)\n  \\details Enables the Security Attribution Unit (SAU).\n */\nvoid TZ_SAU_Enable(void);\n\n/**\n  \\brief   Disable Security Attribution Unit (SAU)\n  \\details Disables the Security Attribution Unit (SAU).\n */\nvoid TZ_SAU_Disable(void);\n\n/** close sau_trustzone_functions\n  @}\n*/\n\n\n/**\n  \\defgroup stacksealing_support_trustzone_functions Stack Sealing Support Functions\n  \\brief Stack sealing macros and helper functions.\n  @{\n\\details\nSee \\ref RTOS_TrustZone_stacksealing for details on stack sealing technique.\n\n */\n\n/**\n  \\brief   Set stack seal at given address (secure)\n  \\details Writes the stack seal values (2 x 0xFEF5EDA5U) to the given address when in secure state.\n  \\param [in]    stackTop  address to write stackseal\n */\nvoid __TZ_set_STACKSEAL_S (uint32_t *stackTop);\n\n/**\n\\def __STACK_SEAL\n\\brief Compiler/linker symbol specifying the location of the stack seal.\n\\details\nThe address of the specified symbol is used to set the stack seal during low level init.\nThis is compiler/linker specific. CMSIS specifies common default for supported compilers. \n\n\\note This define is only intended to be used by the \\ref startup_c_pg.\n*/\n#define __STACK_SEAL\n\n/** close stacksealing_support_trustzone_functions\n  @}\n*/\n\n\n/**\n  \\defgroup context_trustzone_functions RTOS Context Management\n  \\brief RTOS Thread Context Management for Armv8-M TrustZone.\n  @{\n  \\details The CMSIS-Core provides the file <b>tz_context.h</b> which defines an API to standardize the context memory system for real-time operating systems. For more information refer to \\ref RTOS_TrustZone.\n*/\n\n/**\n  \\brief Initialize secure context memory system\n  \\details Initializes the memory allocation management for the secure memory regions. As a minimum the secure thread mode stack will be provided.\n  \\return execution status (1: success, 0: error)\n */\nuint32_t TZ_InitContextSystem_S (void);\n \n/**\n  \\brief Allocate context memory for calling secure software modules in TrustZone\n  \\details \n    Allocates the secure memory regions for thread execution. The parameter \\em module describes\n    the set of secure functions that are called by the non-secure thread.\n    Set \\em module to zero if no secure calls are used/allowed. This leads to no secure memory to be assigned\n    which results in zero being returned as memory id as well.\n    This function should be called by an RTOS kernel at the start of a thread.\n  \\param[in]  module   A non-zero value identifies software modules called from non-secure mode. zero is used if no secure calls are used/allowed.\n  \\return value != 0 id TrustZone memory slot identify\n  \\return value 0    no memory available or internal error\n */\nTZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\n\n/**\n  \\brief Free context memory that was previously allocated with \\ref TZ_AllocModuleContext_S\n  \\details\n    De-allocates the secure memory regions.\n    The parameter \\em id refers to a TrustZone memory slot that has been obtained with \\ref TZ_AllocModuleContext_S.\n    This function should be called by an RTOS kernel at the termination of a thread.\n  \\param[in]  id  TrustZone memory slot identifier\n  \\return execution status (1: success, 0: error)\n */\nuint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\n \n/**\n  \\brief Load secure context (called on RTOS thread context switch)\n  \\details\n    Prepare the secure context for execution so that a thread in the non-secure state can\n    call secure library modules. The parameter \\em id refers to a TrustZone memory slot that has been\n    obtained with \\ref TZ_AllocModuleContext_S which might be zero if not used.\n    This function should be called by an RTOS kernel at thread context switch before running a thread.\n  \\param[in]  id  TrustZone memory slot identifier\n  \\return execution status (1: success, 0: error)\n */\nuint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\n \n/**\n  \\brief Store secure context (called on RTOS thread context switch)\n  \\details\n    Free the secure context that has been previously loaded with \\ref TZ_LoadContext_S. The parameter\n    \\em id refers to a TrustZone memory slot that has been obtained with \\ref TZ_AllocModuleContext_S\n    which might be zero if not used.\n    This function should be called by an RTOS kernel at thread context switch after running a thread.\n  \\param[in]  id  TrustZone memory slot identifier\n  \\return execution status (1: success, 0: error)\n */\nuint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\n\n\n/** close context_trustzone_functions\n  @}\n*/\n\n\n/** close trustzone_functions\n@}\n*/\n\n/**\n\\endcond\n*/"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_VersionControl.txt",
    "content": "/**************************************************************************************************/\n/**\n\\defgroup   version_control_gr    Version Control\n\\brief      Version \\#define symbols for CMSIS release specific C/C++ source code\n\\details\nThe header file <b>cmsis_version.h</b> is included by each core header so that these definitions are available. \n\n<b>Code Example:</b>\n\\code\n#if defined(__CM_CMSIS_VERSION) && \\\n    (__CM_CMSIS_VERSION >= 0x00050001)\n#error Yes, we have CMSIS 5.1 or later\n#else\n#error We need CMSIS 5.1 or later!\n#endif\n\\endcode\n\n<b>Deprecated</b>\n\nThe following macros are deprecated:\n  - \\b __XXX_CMSIS_VERSION_MAIN which is replaced by \\ref __CM_CMSIS_VERSION_MAIN.\n  - \\b __XXX_CMSIS_VERSION_SUB which is replaced by \\ref __CM_CMSIS_VERSION_SUB.\n  - \\b __XXX_CMSIS_VERSION which is replaced by \\ref __CM_CMSIS_VERSION.\n\n@{\n*/\n\n/**\n\\brief Contains the CMSIS major version\n\\details The CMSIS major version can be used to differentiate between CMSIS major releases.\n*/\n#define __CM_CMSIS_VERSION_MAIN\n\n/**\n\\brief Contains the CMSIS minor version\n\\details The CMSIS minor version can be used to query a CMSIS release update level.\n*/\n#define __CM_CMSIS_VERSION_SUB\n\n/**\n\\brief Contains the CMSIS version\n\\details The CMSIS version is a combination of the \\ref __CM_CMSIS_VERSION_MAIN (bits 31..15) and \\ref __CM_CMSIS_VERSION_SUB (bits 14..0).\n*/\n#define __CM_CMSIS_VERSION\n\n/**\n\\brief Contains the core version for a Cortex-M class controller.\n\\details This define can be used to differentiate between the various available Cortex-M controllers.\nPossible values are:\n - 0 for a Cortex-M0 or Cortex-M0+\n - 1 for a Cortex-M1\n - 3 for a Cortex-M3\n - 4 for a Cortex-M4\n - 7 for a Cortex-M7\n\\if ARMv8M\n - 23 for a Cortex-M23\n - 33 for a Cortex-M33\n - 35 for a Cortex-M35P\n - 55 for a Cortex-M55\n - 85 for a Cortex-M85\n - 2  for a Armv8-M Base Line device\n - 80 for a Armv8-M Main Line device\n - 81 for a Armv8.1-M Main Line device\n\\endif \n\nThis define is only available for Cortex-M class controllers.\n<b>Code Example:</b>\n\\code\n#if defined(__CORTEX_M) && (__CORTEX_M == 4)\n#error Yes, we have an Cortex-M4 controller.\n#else\n#error We need a Cortex-M4 controller!\n#endif\n\\endcode\n*/\n#define __CORTEX_M\n\n\n/**\n\\cond (ARMSC)\n*/\n\n/**\n\\brief Contains the core version for a Cortex Secure Core controller.\n\\details This define can be used to differentiate between the various available Cortex Secure Core controllers.\nPossible values are:\n - 000 for a Cortex-SC000\n - 300 for a Cortex-SC300\n \nThis define is only available for Cortex Secure Core controllers.\n<b>Code Example:</b>\n\\code\n#if defined(__CORTEX_SC) && (__CORTEX_SC == 300U)\n#error Yes, we have an Cortex SC300 controller.\n#else\n#error We need a Cortex SC300 controller!\n#endif\n\\endcode\n*/\n#define __CORTEX_SC\n/**\n\\endcond\n*/\n\n/**\n\\cond (STAR)\n*/\n/**\n\\brief Contains the core version for a STAR-MC controller.\n\\details This define can be used to differentiate between the various available STAR-MC controllers.\nPossible values are:\n - 1 for a STAR-MC1\n \nThis define is only available for STAR-MC controllers.\n<b>Code Example:</b>\n\\code\n#if defined(__STAR_MC) && (__STAR_MC == 1U)\n#error Yes, we have a STAR-MC1 controller.\n#else\n#error We need a STAR-MC1 controller!\n#endif\n\\endcode\n*/\n#define __STAR_MC\n/**\n\\endcond\n*/\n\n/**\n@}\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_cm4_simd.txt",
    "content": "/* ######################  CMSIS Support for Cortex-M4/7/33/35P/55 SIMD Instructions  ####################### */\n/**\n\n\\defgroup  intrinsic_SIMD_gr  Intrinsic Functions for SIMD Instructions\n\\brief     Access to dedicated SIMD instructions available on Armv7E-M (Cortex-M4/M7), Armv8-M Mainline\n           (Cortex-M33/M35P), and Armv8.1-M (Cortex-M55/M85).\n\n\\details\n\n<b>Single Instruction Multiple Data (SIMD)</b> extensions are provided <b>only for Cortex-M4 and Cortex-M7 cores</b>\nto simplify development of application software. SIMD extensions increase the processing capability\nwithout materially increasing the power consumption. The SIMD extensions are completely transparent\nto the operating system (OS), allowing existing OS ports to be used.\n\n<b>SIMD Features:</b>\n\n - Simultaneous computation of 2x16-bit or 4x8-bit operands\n - Fractional arithmetic\n - User definable saturation modes (arbitrary word-width)\n - Dual 16x16 multiply-add/subtract 32x32 fractional MAC\n - Simultaneous 8/16-bit select operations\n - Performance up to 3.2 GOPS at 800MHz\n - Performance is achieved with a \"near zero\" increase in power consumption on a typical implementation\n\n\\b Examples:\n\n\\b Addition: Add two values using SIMD function\n\n\\code\nuint32_t add_halfwords(uint32_t val1, uint32_t val2)\n{\n  return __SADD16(val1, val2);\n}\n\\endcode\n\n\n\n\\b Subtraction: Subtract two values using SIMD function\n\n\\code\nuint32_t sub_halfwords(uint32_t val1, uint32_t val2)\n{\n  return __SSUB16(val1, val2);\n}\n\\endcode\n\n\n\\b Multiplication: Performing a multiplication using SIMD function\n\n\\code\nuint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)\n{\n  return __SMUAD(val1, val2);\n}\n\\endcode\n\n @{\n*/\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting quad 8-bit signed addition\n    \\details     This function performs four 8-bit signed integer additions.\n          The GE bits of the APSR are set according to the results of the additions.\n    \\param      val1    first four 8-bit summands.\n    \\param      val2    second four 8-bit summands.\n\n    \\returns\n            \\li the addition of the first bytes from each operand, in the first byte of the return value.\n            \\li the addition of the second bytes of each operand, in the second byte of the return value.\n            \\li the addition of the third bytes of each operand, in the third byte of the return value.\n            \\li the addition of the fourth bytes of each operand, in the fourth byte of the return value.\n        \\par\n            Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n        \\par\n            If \\em res is the return value, then:\n            \\li if res[7:0] \\>= 0 then APSR.GE[0] = 1 else 0\n            \\li if res[15:8] \\>= 0 then APSR.GE[1] = 1 else 0\n            \\li if res[23:16] \\>= 0 then APSR.GE[2] = 1 else 0\n            \\li if res[31:24] \\>= 0 then APSR.GE[3] = 1 else 0\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   + val2[7:0]\n   res[15:8]  = val1[15:8]  + val2[15:8]\n   res[23:16] = val1[23:16] + val2[23:16]\n   res[31:24] = val1[31:24] + val2[31:24]\n        \\endcode\n*/\nuint32_t __SADD8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/** \\ingroup    Intrinsic_SIMD_gr\n    \\brief      Q setting quad 8-bit saturating addition\n    \\details     This function enables you to perform four 8-bit integer additions, saturating the results to\n          the 8-bit signed integer range -2<sup>7</sup> \\<= x \\<= 2<sup>7</sup> - 1.\n    \\param      val1    first four 8-bit summands.\n    \\param      val2    second four 8-bit summands.\n\n    \\returns\n            \\li the saturated addition of the first byte of each operand in the first byte of the return value.\n            \\li the saturated addition of the second byte of each operand in the second byte of the return value.\n            \\li the saturated addition of the third byte of each operand in the third byte of the return value.\n            \\li the saturated addition of the fourth byte of each operand in the fourth byte of the return value.\n        \\par\n            The returned results are saturated to the 16-bit signed integer range -2<sup>7</sup> \\<= x \\<= 2<sup>7</sup> - 1.\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   + val2[7:0]\n   res[15:8]  = val1[15:8]  + val2[15:8]\n   res[23:16] = val1[23:16] + val2[23:16]\n   res[31:24] = val1[31:24] + val2[31:24]\n        \\endcode\n*/\nuint32_t __QADD8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Quad 8-bit signed addition with halved results\n    \\details     This function enables you to perform four signed 8-bit integer additions, halving the results.\n    \\param      val1    first four 8-bit summands.\n    \\param      val2    second four 8-bit summands.\n\n    \\returns\n            \\li the halved addition of the first bytes from each operand, in the first byte of the return value.\n            \\li the halved addition of the second bytes from each operand, in the second byte of the return value.\n            \\li the halved addition of the third bytes from each operand, in the third byte of the return value.\n            \\li the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   + val2[7:0]  >> 1\n   res[15:8]  = val1[15:8]  + val2[15:8] >> 1\n   res[23:16] = val1[23:16] + val2[23:16] >> 1\n   res[31:24] = val1[31:24] + val2[31:24] >> 1\n        \\endcode\n*/\nuint32_t __SHADD8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/** \\ingroup    Intrinsic_SIMD_gr\n    \\brief      GE setting quad 8-bit unsigned addition\n\n    \\details    This function enables you to perform four unsigned 8-bit integer additions.\n                The GE bits of the APSR are set according to the results.\n\n    \\param      val1    first four 8-bit summands for each addition.\n    \\param      val2    second four 8-bit summands for each addition.\n\n    \\returns\n            \\li the halved addition of the first bytes from each operand, in the first byte of the return value.\n            \\li the halved addition of the second bytes from each operand, in the second byte of the return value.\n            \\li the halved addition of the third bytes from each operand, in the third byte of the return value.\n            \\li the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.\n\n    \\par\n            Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.\n\n    \\par\n            If \\em res is the return value, then:\n            \\li if res[7:0] \\>= 0x100 then APSR.GE[0] = 1 else 0\n            \\li if res[15:8] \\>= 0x100 then APSR.GE[1] = 1 else 0\n            \\li if res[23:16] \\>= 0x100 then APSR.GE[2] = 1 else 0\n            \\li if res[31:24] \\>= 0x100 then APSR.GE[3] = 1 else 0\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   + val2[7:0]\n   res[15:8]  = val1[15:8]  + val2[15:8]\n   res[23:16] = val1[23:16] + val2[23:16]\n   res[31:24] = val1[31:24] + val2[31:24]\n        \\endcode\n*/\nuint32_t __UADD8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Quad 8-bit unsigned saturating addition\n\n    \\details    This function enables you to perform four unsigned 8-bit integer additions, saturating the\n           results to the 8-bit unsigned integer range 0 \\< x \\< 2<sup>8</sup> - 1.\n\n    \\param      val1    first four 8-bit summands.\n    \\param      val2    second four 8-bit summands.\n\n    \\returns\n            \\li the halved addition of the first bytes in each operand, in the first byte of the return value.\n            \\li the halved addition of the second bytes in each operand, in the second byte of the return value.\n            \\li the halved addition of the third bytes in each operand, in the third byte of the return value.\n            \\li the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.\n\n    \\par\n            The results are saturated to the 8-bit unsigned integer range 0 \\< x \\< 2<sup>8</sup> - 1.\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   + val2[7:0]\n   res[15:8]  = val1[15:8]  + val2[15:8]\n   res[23:16] = val1[23:16] + val2[23:16]\n   res[31:24] = val1[31:24] + val2[31:24]\n        \\endcode\n*/\nuint32_t __UQADD8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Quad 8-bit unsigned addition with halved results\n\n    \\details    This function enables you to perform four unsigned 8-bit integer additions, halving the results.\n\n    \\param      val1    first four 8-bit summands.\n    \\param      val2    second four 8-bit summands.\n\n    \\returns\n            \\li the halved addition of the first bytes in each operand, in the first byte of the return value.\n            \\li the halved addition of the second bytes in each operand, in the second byte of the return value.\n            \\li the halved addition of the third bytes in each operand, in the third byte of the return value.\n            \\li the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   + val2[7:0]   >> 1\n   res[15:8]  = val1[15:8]  + val2[15:8]  >> 1\n   res[23:16] = val1[23:16] + val2[23:16] >> 1\n   res[31:24] = val1[31:24] + val2[31:24] >> 1\n        \\endcode\n*/\nuint32_t __UHADD8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting quad 8-bit signed subtraction\n\n    \\details    This function enables you to perform four 8-bit signed integer subtractions.<br>\n                The GE bits in the APSR are set according to the results.\n\n    \\param      val1    first four 8-bit  operands of each subtraction.\n    \\param      val2    second four 8-bit  operands of each subtraction.\n\n    \\returns\n            \\li the subtraction of the first byte in the second operand from the first byte in the\n                first operand, in the first bytes of the return value.\n            \\li the subtraction of the second byte in the second operand from the second byte in\n                the first operand, in the second byte of the return value.\n            \\li the subtraction of the third byte in the second operand from the third byte in the\n                first operand, in the third byte of the return value.\n            \\li the subtraction of the fourth byte in the second operand from the fourth byte in\n                the first operand, in the fourth byte of the return value.\n\n        \\par    Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n\n        \\par\n            If \\em res is the return value, then:\n            \\li if res[8:0] \\>= 0 then APSR.GE[0] = 1 else 0\n            \\li if res[15:8] \\>= 0 then APSR.GE[1] = 1 else 0\n            \\li if res[23:16] \\>= 0 then APSR.GE[2] = 1 else 0\n            \\li if res[31:24] \\>= 0 then APSR.GE[3] = 1 else 0\n\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   - val2[7:0]\n   res[15:8]  = val1[15:8]  - val2[15:8]\n   res[23:16] = val1[23:16] - val2[23:16]\n   res[31:24] = val1[31:24] - val2[31:24]\n        \\endcode\n*/\nuint32_t __SSUB8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting quad 8-bit saturating subtract\n\n    \\details    This function enables you to perform four 8-bit integer subtractions, saturating the results\n          to the 8-bit signed integer range -2<sup>7</sup> \\<= x \\<= 2<sup>7</sup> - 1.\n\n    \\param      val1    first four 8-bit  operands.\n    \\param      val2    second four 8-bit  operands.\n\n    \\returns\n            \\li the subtraction of the first byte in the second operand from the first byte in the\n                first operand, in the first bytes of the return value.\n            \\li the subtraction of the second byte in the second operand from the second byte in\n                the first operand, in the second byte of the return value.\n            \\li the subtraction of the third byte in the second operand from the third byte in the\n                first operand, in the third byte of the return value.\n            \\li the subtraction of the fourth byte in the second operand from the fourth byte in\n                the first operand, in the fourth byte of the return value.\n\n        \\par\n            The returned results are saturated to the 8-bit signed integer range -2<sup>7</sup> \\<= x \\<= 2<sup>7</sup> - 1.\n\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   - val2[7:0]\n   res[15:8]  = val1[15:8]  - val2[15:8]\n   res[23:16] = val1[23:16] - val2[23:16]\n   res[31:24] = val1[31:24] - val2[31:24]\n        \\endcode\n*/\nuint32_t __QSUB8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Quad 8-bit signed subtraction with halved results\n\n    \\details    This function enables you to perform four signed 8-bit integer subtractions, halving the\n     results.\n\n    \\param      val1    first four 8-bit  operands.\n    \\param      val2    second four 8-bit  operands.\n\n    \\returns\n            \\li the halved subtraction of the first byte in the second operand from the first byte in the\n                first operand, in the first bytes of the return value.\n            \\li the halved subtraction of the second byte in the second operand from the second byte in\n                the first operand, in the second byte of the return value.\n            \\li the halved subtraction of the third byte in the second operand from the third byte in the\n                first operand, in the third byte of the return value.\n            \\li the halved subtraction of the fourth byte in the second operand from the fourth byte in\n                the first operand, in the fourth byte of the return value.\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   - val2[7:0]   >> 1\n   res[15:8]  = val1[15:8]  - val2[15:8]  >> 1\n   res[23:16] = val1[23:16] - val2[23:16] >> 1\n   res[31:24] = val1[31:24] - val2[31:24] >> 1\n        \\endcode\n*/\nuint32_t __SHSUB8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting quad 8-bit unsigned subtract\n\n    \\details    This function enables you to perform four 8-bit unsigned integer subtractions.\n          The GE bits in the APSR are set according to the results.\n\n    \\param      val1    first four 8-bit  operands.\n    \\param      val2    second four 8-bit  operands.\n\n    \\returns\n            \\li the subtraction of the first byte in the second operand from the first byte in the\n                first operand, in the first bytes of the return value.\n            \\li the subtraction of the second byte in the second operand from the second byte in\n                the first operand, in the second byte of the return value.\n            \\li the subtraction of the third byte in the second operand from the third byte in the\n                first operand, in the third byte of the return value.\n            \\li the subtraction of the fourth byte in the second operand from the fourth byte in\n                the first operand, in the fourth byte of the return value.\n\n    \\par\n        Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n\n    \\par\n        If \\em res is the return value, then:\n            \\li if res[8:0] \\>= 0 then APSR.GE[0] = 1 else 0\n            \\li if res[15:8] \\>= 0 then APSR.GE[1] = 1 else 0\n            \\li if res[23:16] \\>= 0 then APSR.GE[2] = 1 else 0\n            \\li if res[31:24] \\>= 0 then APSR.GE[3] = 1 else 0\n\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   - val2[7:0]\n   res[15:8]  = val1[15:8]  - val2[15:8]\n   res[23:16] = val1[23:16] - val2[23:16]\n   res[31:24] = val1[31:24] - val2[31:24]\n        \\endcode\n*/\nuint32_t __USUB8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Quad 8-bit unsigned saturating subtraction\n\n    \\details    This function enables you to perform four unsigned 8-bit integer subtractions, saturating\n          the results to the 8-bit unsigned integer range 0 \\< x \\< 2<sup>8</sup> - 1.\n\n    \\param      val1    first four 8-bit  operands.\n    \\param      val2    second four 8-bit  operands.\n\n    \\returns\n            \\li the subtraction of the first byte in the second operand from the first byte in the\n                first operand, in the first bytes of the return value.\n            \\li the subtraction of the second byte in the second operand from the second byte in\n                the first operand, in the second byte of the return value.\n            \\li the subtraction of the third byte in the second operand from the third byte in the\n                first operand, in the third byte of the return value.\n            \\li the subtraction of the fourth byte in the second operand from the fourth byte in\n                the first operand, in the fourth byte of the return value.\n\n    \\par\n        The results are saturated to the 8-bit unsigned integer range 0 \\< x \\< 2<sup>8</sup> - 1.\n\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   - val2[7:0]\n   res[15:8]  = val1[15:8]  - val2[15:8]\n   res[23:16] = val1[23:16] - val2[23:16]\n   res[31:24] = val1[31:24] - val2[31:24]\n        \\endcode\n*/\nuint32_t __UQSUB8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Quad 8-bit unsigned subtraction with halved results\n\n    \\details    This function enables you to perform four unsigned 8-bit integer subtractions, halving the\n     results.\n\n    \\param      val1    first four 8-bit  operands.\n    \\param      val2    second four 8-bit  operands.\n\n    \\returns\n            \\li the halved subtraction of the first byte in the second operand from the first byte in the\n                first operand, in the first bytes of the return value.\n            \\li the halved subtraction of the second byte in the second operand from the second byte in\n                the first operand, in the second byte of the return value.\n            \\li the halved subtraction of the third byte in the second operand from the third byte in the\n                first operand, in the third byte of the return value.\n            \\li the halved subtraction of the fourth byte in the second operand from the fourth byte in\n                the first operand, in the fourth byte of the return value.\n\n    \\par Operation:\n        \\code\n   res[7:0]   = val1[7:0]   - val2[7:0]    >> 1\n   res[15:8]  = val1[15:8]  - val2[15:8]   >> 1\n   res[23:16] = val1[23:16] - val2[23:16]  >> 1\n   res[31:24] = val1[31:24] - val2[31:24]  >> 1\n        \\endcode\n*/\nuint32_t __UHSUB8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting dual 16-bit signed addition\n\n    \\details    This function enables you to perform two 16-bit signed integer additions.<br>\n          The GE bits in the APSR are set according to the results of the additions.\n\n    \\param      val1    first two 16-bit  summands.\n    \\param      val2    second two 16-bit  summands.\n\n    \\returns\n            \\li the addition of the low halfwords in the low halfword of the return value.\n            \\li the addition of the high halfwords in the high halfword of the return value.\n\n    \\par\n        Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n    \\par\n        If \\em res is the return value, then:\n            \\li if res[15:0] \\>= 0 then APSR.GE[1:0] = 11 else 00\n            \\li if res[31:16] \\>= 0 then APSR.GE[3:2] = 11 else 00\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[15:0]\n   res[31:16] = val1[31:16] + val2[31:16]\n        \\endcode\n*/\nuint32_t __SADD16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit saturating addition\n\n    \\details    This function enables you to perform two 16-bit integer arithmetic additions in parallel,\n          saturating the results to the 16-bit signed integer range -2<sup>15</sup> \\<= x \\<= 2<sup>15</sup> - 1.\n\n    \\param      val1    first two 16-bit  summands.\n    \\param      val2    second two 16-bit  summands.\n\n    \\returns\n            \\li the saturated addition of the low halfwords, in the low halfword of the return value.\n            \\li the saturated addition of the high halfwords, in the high halfword of the return value.\n\n    \\par\n        The returned results are saturated to the 16-bit signed integer\n             range -2<sup>15</sup> \\<= x \\<= 2<sup>15</sup> - 1\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[15:0]\n   res[31:16] = val1[31:16] + val2[31:16]\n        \\endcode\n*/\nuint32_t __QADD16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit signed addition with halved results\n\n    \\details    This function enables you to perform two signed 16-bit integer additions, halving the\n     results.\n\n    \\param      val1    first two 16-bit  summands.\n    \\param      val2    second two 16-bit  summands.\n\n    \\returns\n            \\li the halved addition of the low halfwords, in the low halfword of the return value.\n            \\li the halved addition of the high halfwords, in the high halfword of the return value.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[15:0]  >> 1\n   res[31:16] = val1[31:16] + val2[31:16] >> 1\n        \\endcode\n*/\nuint32_t __SHADD16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting dual 16-bit unsigned addition\n\n    \\details    This function enables you to perform two 16-bit unsigned integer additions.<br>\n          The GE bits in the APSR are set according to the results.\n\n    \\param      val1    first two 16-bit  summands for each addition.\n    \\param      val2    second two 16-bit  summands for each addition.\n\n    \\returns\n            \\li the addition of the low halfwords in each operand, in the low halfword of the\n                return value.\n            \\li the addition of the high halfwords in each operand, in the high halfword of the\n                return value.\n\n    \\par\n        Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n    \\par\n        If \\em res is the return value, then:\n            \\li if res[15:0] \\>= 0x10000 then APSR.GE[0] = 11 else 00\n            \\li if res[31:16] \\>= 0x10000 then APSR.GE[1] = 11 else 00\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[15:0]\n   res[31:16] = val1[31:16] + val2[31:16]\n        \\endcode\n*/\nuint32_t __UADD16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit unsigned saturating addition\n\n    \\details    This function enables you to perform two unsigned 16-bit integer additions, saturating the\n     results to the 16-bit unsigned integer range 0 \\< x \\< 2<sup>16</sup> - 1.\n\n    \\param      val1    first two 16-bit  summands.\n    \\param      val2    second two 16-bit  summands.\n\n    \\returns\n            \\li the addition of the low halfword in the first operand and the low halfword in the\n                second operand, in the low halfword of the return value.\n            \\li the addition of the high halfword in the first operand and the high halfword in the\n                second operand, in the high halfword of the return value.\n\n    \\par\n        The results are saturated to the 16-bit unsigned integer\n             range 0 \\< x \\< 2<sup>16</sup> - 1.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[15:0]\n   res[31:16] = val1[31:16] + val2[31:16]\n        \\endcode\n*/\nuint32_t __UQADD16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit unsigned addition with halved results\n\n    \\details    This function enables you to perform two unsigned 16-bit integer additions, halving the\n     results.\n\n    \\param      val1    first two 16-bit  summands.\n    \\param      val2    second two 16-bit  summands.\n\n    \\returns\n            \\li the halved addition of the low halfwords in each operand, in the low halfword of\n                the return value.\n            \\li the halved addition of the high halfwords in each operand, in the high halfword\n                of the return value.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[15:0]   >> 1\n   res[31:16] = val1[31:16] + val2[31:16]  >> 1\n        \\endcode\n*/\nuint32_t __UHADD16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting dual 16-bit signed subtraction\n\n    \\details    This function enables you to perform two 16-bit signed integer subtractions.<br>\n          The GE bits in the APSR are set according to the results.\n\n    \\param      val1    first two 16-bit operands of each subtraction.\n    \\param      val2    second two 16-bit operands of each subtraction.\n\n    \\returns\n            \\li the subtraction of the low halfword in the second operand from the low halfword\n                in the first operand, in the low halfword of the return value.\n            \\li the subtraction of the high halfword in the second operand from the high halfword\n                in the first operand, in the high halfword of the return value.\n\n    \\par\n        Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n    \\par\n        If \\li res is the return value, then:\n            \\li if res[15:0] \\>= 0 then APSR.GE[1:0] = 11 else 00\n            \\li if res[31:16] \\>= 0 then APSR.GE[3:2] = 11 else 00\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[15:0]\n   res[31:16] = val1[31:16] - val2[31:16]\n        \\endcode\n*/\nuint32_t __SSUB16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit saturating subtract\n\n    \\details    This function enables you to perform two 16-bit integer subtractions, saturating the\n          results to the 16-bit signed integer range -2<sup>15</sup> \\<= x \\<= 2<sup>15</sup> - 1.\n\n    \\param      val1    first two 16-bit operands.\n    \\param      val2    second two 16-bit operands.\n\n    \\returns\n            \\li the saturated subtraction of the low halfword in the second operand from the low\n                halfword in the first operand, in the low halfword of the returned result.\n            \\li the saturated subtraction of the high halfword in the second operand from the high\n                halfword in the first operand, in the high halfword of the returned result.\n\n    \\par\n        The returned results are saturated to the 16-bit signed integer\n             range -2<sup>15</sup> \\<= x \\<= 2<sup>15</sup> - 1.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[15:0]\n   res[31:16] = val1[31:16] - val2[31:16]\n        \\endcode\n*/\nuint32_t __QSUB16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit signed subtraction with halved results\n\n    \\details    This function enables you to perform two signed 16-bit integer subtractions, halving the\n          results.\n\n    \\param      val1    first two 16-bit operands.\n    \\param      val2    second two 16-bit operands.\n\n    \\returns\n            \\li the halved subtraction of the low halfword in the second operand from the low\n                halfword in the first operand, in the low halfword of the returned result.\n            \\li the halved subtraction of the high halfword in the second operand from the high\n                halfword in the first operand, in the high halfword of the returned result.\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[15:0]   >> 1\n   res[31:16] = val1[31:16] - val2[31:16]  >> 1\n        \\endcode\n*/\nuint32_t __SHSUB16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting dual 16-bit unsigned subtract\n\n    \\details    This function enables you to perform two 16-bit unsigned integer subtractions.<br>\n          The GE bits in the APSR are set according to the results.\n\n    \\param      val1    first two 16-bit operands.\n    \\param      val2    second two 16-bit operands.\n\n    \\returns\n            \\li the subtraction of the low halfword in the second operand from the low halfword\n                in the first operand, in the low halfword of the return value.\n            \\li the subtraction of the high halfword in the second operand from the high halfword\n                in the first operand, in the high halfword of the return value.\n\n    \\par\n        Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n\n    \\par\n        If \\em res is the return value, then:\n            \\li if res[15:0] \\>= 0 then APSR.GE[1:0] = 11 else 00\n            \\li if res[31:16] \\>= 0 then APSR.GE[3:2] = 11 else 00\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[15:0]\n   res[31:16] = val1[31:16] - val2[31:16]\n        \\endcode\n*/\nuint32_t __USUB16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit unsigned saturating subtraction\n\n    \\details    This function enables you to perform two unsigned 16-bit integer subtractions, saturating\n          the results to the 16-bit unsigned integer range 0 \\< x \\< 2<sup>16</sup> - 1.\n\n    \\param      val1    first two 16-bit operands for each subtraction.\n    \\param      val2    second two 16-bit operands for each subtraction.\n\n    \\returns\n            \\li the subtraction of the low halfword in the second operand from the low halfword\n                in the first operand, in the low halfword of the return value.\n            \\li the subtraction of the high halfword in the second operand from the high halfword\n                in the first operand, in the high halfword of the return value.\n\n    \\par\n            The results are saturated to the 16-bit unsigned integer range 0 \\< x \\< 2<sup>16</sup> - 1.\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[15:0]\n   res[31:16] = val1[31:16] - val2[31:16]\n        \\endcode\n*/\nuint32_t __UQSUB16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit unsigned subtraction with halved results\n\n    \\details    This function enables you to perform two unsigned 16-bit integer subtractions, halving\n          the results.\n\n    \\param      val1    first two 16-bit operands.\n    \\param      val2    second two 16-bit operands.\n\n    \\returns\n            \\li the halved subtraction of the low halfword in the second operand from the low halfword\n                in the first operand, in the low halfword of the return value.\n            \\li the halved subtraction of the high halfword in the second operand from the high halfword\n                in the first operand, in the high halfword of the return value.\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[15:0]   >> 1\n   res[31:16] = val1[31:16] - val2[31:16]  >> 1\n        \\endcode\n*/\nuint32_t __UHSUB16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting dual 16-bit addition and subtraction with exchange\n\n    \\details    This function inserts an SASX instruction into the instruction stream generated by the\n          compiler. It enables you to exchange the halfwords of the second operand, add the high\n          halfwords and subtract the low halfwords.<br>\n          The GE bits in the APRS are set according to the results.\n\n    \\param      val1    first operand for the subtraction in the low halfword, and the\n              first operand for the addition in the high halfword.\n    \\param      val2    second operand for the subtraction in the high halfword, and the\n              second operand for the addition in the low halfword.\n\n    \\returns\n            \\li the subtraction of the high halfword in the second operand from the low halfword\n                in the first operand, in the low halfword of the return value.\n            \\li the addition of the high halfword in the first operand and the low halfword in the\n                second operand, in the high halfword of the return value.\n\n    \\par\n        Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n    \\par\n        If \\em res is the return value, then:\n            \\li if res[15:0] \\>= 0 then APSR.GE[1:0] = 11 else 00\n            \\li if res[31:16] \\>= 0 then APSR.GE[3:2] = 11 else 00\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[31:16]\n   res[31:16] = val1[31:16] + val2[15:0]\n        \\endcode\n*/\nuint32_t __SASX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit add and subtract with exchange\n\n    \\details    This function enables you to exchange the halfwords of the one operand, then add the high\n          halfwords and subtract the low halfwords, saturating the results to the 16-bit signed\n          integer range -2<sup>15</sup> \\<= x \\<= 2<sup>15</sup> - 1.\n\n    \\param      val1    first operand for the subtraction in the low halfword, and the\n                       first operand for the addition in the high halfword.\n    \\param      val2    second operand for the subtraction in the high halfword, and the\n                       second operand for the addition in the low halfword.\n\n    \\returns\n            \\li the saturated subtraction of the high halfword in the second operand from the low\n                halfword in the first operand, in the low halfword of the return value.\n            \\li the saturated addition of the high halfword in the first operand and the low\n                halfword in the second operand, in the high halfword of the return value.\n\n    \\par\n        The returned results are saturated to the 16-bit signed integer\n             range -2<sup>15</sup> \\<= x \\<= 2<sup>15</sup> - 1.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[31:16]\n   res[31:16] = val1[31:16] + val2[15:0]\n        \\endcode\n*/\nuint32_t __QASX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit signed addition and subtraction with halved results\n\n    \\details    This function enables you to exchange the two halfwords of one operand, perform one\n          signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.\n\n    \\param      val1    first 16-bit operands.\n    \\param      val2    second 16-bit operands.\n\n    \\returns\n            \\li the halved subtraction of the high halfword in the second operand from the low\n                halfword in the first operand, in the low halfword of the return value.\n            \\li the halved addition of the low halfword in the second operand and the high\n                halfword in the first operand, in the high halfword of the return value.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1\n   res[31:16] = (val1[31:16] + val2[15:0] ) >> 1\n        \\endcode\n*/\nuint32_t __SHASX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting dual 16-bit unsigned addition and subtraction with exchange\n\n    \\details    This function enables you to exchange the two halfwords of the second operand, add the\n          high halfwords and subtract the low halfwords.<br>\n          The GE bits in the APSR are set according to the results.\n\n    \\param      val1    first operand for the subtraction in the low halfword, and the\n              first operand for the addition in the high halfword.\n    \\param      val2    second operand for the subtraction in the high halfword and the\n              second operand for the addition in the low halfword.\n\n    \\returns\n            \\li the subtraction of the high halfword in the second operand from the low halfword\n                in the first operand, in the low halfword of the return value.\n            \\li the addition of the high halfword in the first operand and the low halfword in the\n                second operand, in the high halfword of the return value.\n\n    \\par\n            Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n\n    \\par    If \\em res is the return value, then:\n            \\li if res[15:0] \\>= 0 then APSR.GE[1:0] = 11 else 00\n            \\li if res[31:16] \\>= 0x10000 then APSR.GE[3:2] = 11 else 00\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[31:16]\n   res[31:16] = val1[31:16] + val2[15:0]\n        \\endcode\n*/\nuint32_t __UASX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit unsigned saturating addition and subtraction with exchange\n\n    \\details    This function enables you to exchange the halfwords of the second operand and perform\n          one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the\n          results to the 16-bit unsigned integer range 0 \\<= x \\<= 2<sup>16</sup> - 1.\n\n    \\param      val1    first two 16-bit operands.\n    \\param      val2    second two 16-bit operands.\n\n    \\returns\n            \\li the subtraction of the high halfword in the second operand from the low halfword\n                in the first operand, in the low halfword of the return value.\n            \\li the subtraction of the low halfword in the second operand from the high halfword\n                in the first operand, in the high halfword of the return value.\n\n    \\par\n            The results are saturated to the 16-bit unsigned integer\n             range 0 \\<= x \\<= 2<sup>16</sup> - 1.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  - val2[31:16]\n   res[31:16] = val1[31:16] + val2[15:0]\n        \\endcode\n*/\nuint32_t __UQASX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit unsigned addition and subtraction with halved results and exchange\n\n    \\details    This function enables you to exchange the halfwords of the second operand, add the high\n          halfwords and subtract the low halfwords, halving the results.\n\n    \\param      val1    first operand for the subtraction in the low halfword, and the\n           first operand for the addition in the high halfword.\n    \\param      val2    second operand for the subtraction in the high halfword, and the\n           second operand for the addition in the low halfword.\n\n    \\returns\n            \\li the halved subtraction of the high halfword in the second operand from the low\n                halfword in the first operand.\n            \\li the halved addition of the high halfword in the first operand and the low halfword\n                in the second operand.\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = (val1[15:0]  - val2[31:16]) >> 1\n   res[31:16] = (val1[31:16] + val2[15:0] ) >> 1\n        \\endcode\n*/\nuint32_t __UHASX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting dual 16-bit signed subtraction and addition with exchange\n\n    \\details    This function enables you to exchange the two halfwords of one operand and perform one\n          16-bit integer subtraction and one 16-bit addition.<br>\n          The GE bits in the APSR are set according to the results.\n\n    \\param      val1    first operand for the addition in the low halfword, and the first\n              operand for the subtraction in the high halfword.\n    \\param      val2    second operand for the addition in the high halfword, and the\n              second operand for the subtraction in the low halfword.\n\n    \\returns\n            \\li the addition of the low halfword in the first operand and the high halfword in the\n                second operand, in the low halfword of the return value.\n            \\li the subtraction of the low halfword in the second operand from the high halfword\n                in the first operand, in the high halfword of the return value.\n    \\par\n        Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n    \\par\n        If \\em res is the return value, then:\n            \\li if res[15:0] \\>= 0 then APSR.GE[1:0] = 11 else 00\n            \\li if res[31:16] \\>= 0 then APSR.GE[3:2] = 11 else 00\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[31:16]\n   res[31:16] = val1[31:16] - val2[15:0]\n        \\endcode\n*/\nuint32_t __SSAX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit subtract and add with exchange\n\n    \\details    This function enables you to exchange the halfwords of one operand, then subtract the\n          high halfwords and add the low halfwords, saturating the results to the 16-bit signed\n          integer range -2<sup>15</sup> \\<= x \\<= 2<sup>15</sup> - 1.\n\n    \\param      val1    first operand for the addition in the low halfword, and the first\n           operand for the subtraction in the high halfword.\n    \\param      val2    second operand for the addition in the high halfword, and the\n           second operand for the subtraction in the low halfword.\n\n    \\returns\n            \\li the saturated addition of the low halfword of the first operand and the high\n                halfword of the second operand, in the low halfword of the return value.\n            \\li the saturated subtraction of the low halfword of the second operand from the high\n                halfword of the first operand, in the high halfword of the return value.\n    \\par\n        The returned results are saturated to the 16-bit signed integer\n             range -2<sup>15</sup> \\<= x \\<= 2<sup>15</sup> - 1.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[31:16]\n   res[31:16] = val1[31:16] - val2[15:0]\n        \\endcode\n*/\nuint32_t __QSAX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit signed subtraction and addition with halved results\n\n    \\details    This function enables you to exchange the two halfwords of one operand, perform one\n          signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.\n\n    \\param      val1    first 16-bit operands.\n    \\param      val2    second 16-bit operands.\n\n    \\returns\n            \\li the halved addition of the low halfword in the first operand and the high halfword\n                in the second operand, in the low halfword of the return value.\n            \\li the halved subtraction of the low halfword in the second operand from the high\n                halfword in the first operand, in the high halfword of the return value.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1\n   res[31:16] = (val1[31:16] - val2[15:0] ) >> 1\n        \\endcode\n*/\nuint32_t __SHSAX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      GE setting dual 16-bit unsigned subtract and add with exchange\n\n    \\details    This function enables you to exchange the halfwords of the second operand, subtract the\n          high halfwords and add the low halfwords.<br>\n          The GE bits in the APSR are set according to the results.\n\n    \\param      val1    first operand for the addition in the low halfword, and the first\n              operand for the subtraction in the high halfword.\n    \\param      val2    second operand for the addition in the high halfword, and the\n              second operand for the subtraction in the low halfword.\n\n    \\returns\n            \\li the addition of the low halfword in the first operand and the high halfword in the\n                second operand, in the low halfword of the return value.\n            \\li the subtraction of the low halfword in the second operand from the high halfword\n                in the first operand, in the high halfword of the return value.\n    \\par\n        Each bit in APSR.GE is set or cleared for each byte in the return value, depending on\n             the results of the operation.\n    \\par\n        If \\em res is the return value, then:\n            \\li if res[15:0] \\>= 0x10000 then APSR.GE[1:0] = 11 else 00\n            \\li if res[31:16] \\>= 0 then APSR.GE[3:2] = 11 else 00\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[31:16]\n   res[31:16] = val1[31:16] - val2[15:0]\n        \\endcode\n*/\nuint32_t __USAX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit unsigned saturating subtraction and addition with exchange\n\n    \\details    This function enables you to exchange the halfwords of the second operand and perform\n          one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the\n          results to the 16-bit unsigned integer range 0 \\<= x \\<= 2<sup>16</sup> - 1.\n\n    \\param      val1    first 16-bit operand for the addition in the low halfword, and the\n              first 16-bit operand for the subtraction in the high halfword.\n    \\param      val2    second 16-bit halfword for the addition in the high halfword,\n              and the second 16-bit halfword for the subtraction in the low halfword.\n\n    \\returns\n            \\li the addition of the low halfword in the first operand and the high halfword in the\n                second operand, in the low halfword of the return value.\n            \\li the subtraction of the low halfword in the second operand from the high halfword\n                in the first operand, in the high halfword of the return value.\n    \\par\n        The results are saturated to the 16-bit unsigned integer\n             range 0 \\<= x \\<= 2<sup>16</sup> - 1.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + val2[31:16]\n   res[31:16] = val1[31:16] - val2[15:0]\n        \\endcode\n*/\nuint32_t __UQSAX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit unsigned subtraction and addition with halved results and exchange\n\n    \\details    This function enables you to exchange the halfwords of the second operand, subtract the\n          high halfwords and add the low halfwords, halving the results.\n\n    \\param      val1    first operand for the addition in the low halfword, and the first\n              operand for the subtraction in the high halfword.\n    \\param      val2    second operand for the addition in the high halfword, and the\n              second operand for the subtraction in the low halfword.\n\n    \\returns\n            \\li the halved addition of the high halfword in the second operand and the low\n                halfword in the first operand, in the low halfword of the return value.\n            \\li the halved subtraction of the low halfword in the second operand from the high\n                halfword in the first operand, in the high halfword of the return value.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = (val1[15:0]  + val2[31:16]) >> 1\n   res[31:16] = (val1[31:16] - val2[15:0] ) >> 1\n        \\endcode\n*/\nuint32_t __UHSAX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Unsigned sum of quad 8-bit unsigned absolute difference\n\n    \\details    This function enables you to perform four unsigned 8-bit subtractions, and add the\n          absolute values of the differences together, returning the result as a single unsigned\n          integer.\n\n    \\param      val1    first four 8-bit operands for the subtractions.\n    \\param      val2    second four 8-bit operands for the subtractions.\n\n    \\returns\n            \\li the subtraction of the first byte in the second operand from the first byte in the\n                first operand.\n            \\li the subtraction of the second byte in the second operand from the second byte in\n                the first operand.\n            \\li the subtraction of the third byte in the second operand from the third byte in the\n                first operand.\n            \\li the subtraction of the fourth byte in the second operand from the fourth byte in\n                the first operand.\n    \\par\n        The sum is returned as a single unsigned integer.\n\n\n    \\par Operation:\n        \\code\n   absdiff1  = val1[7:0]   - val2[7:0]\n   absdiff2  = val1[15:8]  - val2[15:8]\n   absdiff3  = val1[23:16] - val2[23:16]\n   absdiff4  = val1[31:24] - val2[31:24]\n   res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4\n        \\endcode\n*/\nuint32_t __USAD8(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate\n\n    \\details    This function enables you to perform four unsigned 8-bit subtractions, and add the\n          absolute values of the differences to a 32-bit accumulate operand.\n\n    \\param      val1    first four 8-bit operands for the subtractions.\n    \\param      val2    second four 8-bit operands for the subtractions.\n    \\param      val3    accumulation value.\n\n    \\returns\n        the sum of the absolute differences of the following\n            bytes, added to the accumulation value:\n            \\li the subtraction of the first byte in the second operand from the first byte in the\n                first operand.\n            \\li the subtraction of the second byte in the second operand from the second byte in\n                the first operand.\n            \\li the subtraction of the third byte in the second operand from the third byte in the\n                first operand.\n            \\li the subtraction of the fourth byte in the second operand from the fourth byte in\n                the first operand.\n\n\n    \\par Operation:\n        \\code\n   absdiff1  = val1[7:0]   - val2[7:0]\n   absdiff2  = val1[15:8]  - val2[15:8]\n   absdiff3  = val1[23:16] - val2[23:16]\n   absdiff4  = val1[31:24] - val2[31:24]\n   sum       = absdiff1 + absdiff2 + absdiff3 + absdiff4\n   res[31:0] = sum[31:0] + val3[31:0]\n        \\endcode\n*/\nuint32_t __USADA8(uint32_t val1, uint32_t val2, uint32_t val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit saturate\n\n    \\details    This function enables you to saturate two signed 16-bit values to a selected signed range.<br>\n          The Q bit is set if either operation saturates.\n\n    \\param      val1    two signed 16-bit values to be saturated.\n    \\param      val2    bit position for saturation, an integral constant expression in the\n              range 1 to 16.\n\n\n    \\returns\n        the sum of the absolute differences of the following\n            bytes, added to the accumulation value:\n            \\li the signed saturation of the low halfword in \\em val1, saturated to the bit position\n                specified in \\em val2 and returned in the low halfword of the return value.\n            \\li the signed saturation of the high halfword in <i>val1</i>, saturated to the bit position\n                specified in <i>val2</i> and returned in the high halfword of the return value.\n\n\n    \\par Operation:\n        \\code\n   Saturate halfwords in val1 to the signed range specified by the bit position in val2\n        \\endcode\n*/\nuint32_t __SSAT16(uint32_t val1, const uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit unsigned saturate\n\n    \\details    This function enables you to saturate two signed 16-bit values to a selected unsigned\n         range.<br>\n         The Q bit is set if either operation saturates.\n\n    \\param      val1    two 16-bit values that are to be saturated.\n    \\param      val2    bit position for saturation, and must be an integral constant\n           expression in the range 0 to 15.\n\n\n    \\returns\n        the saturation of the two signed 16-bit values, as non-negative values.\n            \\li the saturation of the low halfword in \\em val1, saturated to the bit position\n                specified in \\em val2 and returned in the low halfword of the return value.\n            \\li the saturation of the high halfword in \\em val1, saturated to the bit position\n                specified in \\em val2 and returned in the high halfword of the return value.\n\n\n    \\par Operation:\n        \\code\n   Saturate halfwords in val1 to the unsigned range specified by the bit position in val2\n        \\endcode\n*/\nuint32_t __USAT16(uint32_t val1, const uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual extract 8-bits and zero-extend to 16-bits\n\n    \\details    This function enables you to extract two 8-bit values from an operand and zero-extend\n          them to 16 bits each.\n\n    \\param      val     two 8-bit values in val[7:0] and val[23:16] to be sign-extended.\n\n\n    \\returns\n        the 8-bit values zero-extended to 16-bit values.\n            \\li zero-extended value of val[7:0] in the low halfword of the return value.\n            \\li zero-extended value of val[23:16] in the high halfword of the return value.\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = ZeroExtended(val[7:0]  )\n   res[31:16] = ZeroExtended(val[23:16])\n        \\endcode\n*/\nuint32_t __UXTB16(uint32_t val);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Extracted 16-bit to 32-bit unsigned addition\n\n    \\details    This function enables you to extract two 8-bit values from one operand, zero-extend them\n          to 16 bits each, and add the results to two 16-bit values from another operand.\n\n    \\param      val1    value added to the zero-extended to 16-bit values.\n    \\param      val2    two 8-bit values to be extracted and zero-extended.\n\n\n    \\returns\n        the 8-bit values in \\em val2, zero-extended to 16-bit values\n            and added to \\em val1.\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = ZeroExt(val2[7:0]   to 16 bits) + val1[15:0]\n   res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]\n        \\endcode\n*/\nuint32_t __UXTAB16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual extract 8-bits and sign extend each to 16-bits\n\n    \\details    This function enables you to extract two 8-bit values from an operand and sign-extend\n          them to 16 bits each.\n\n    \\param      val     two 8-bit values in val[7:0] and val[23:16] to be sign-extended.\n\n\n\n    \\returns\n        the 8-bit values sign-extended to 16-bit values.\n            \\li     sign-extended value of val[7:0] in the low halfword of the return value.\n            \\li     sign-extended value of val[23:16] in the high halfword of the return value.\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = SignExtended(val[7:0]\n   res[31:16] = SignExtended(val[23:16]\n        \\endcode\n*/\nuint32_t __SXTB16(uint32_t val);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Rotate right, dual extract 8-bits and sign extend each to 16-bits\n\n    \\details    This function enables you to rotate an operand by 8/16/24 bit, extract two 8-bit values and sign-extend\n          them to 16 bits each.\n\n    \\param      val     two 8-bit values in val[7:0] and val[23:16] to be sign-extended.\n    \\param      rotate  number of bits to rotate val. Constant rotate value of 8, 16 and 24 can be\n                \toptimally used with a single __SXTB16 instruction. Any other valid constant rotate\n\t\t\tvalue will result in use of two instructions, __ROR and __SXTB16\n\n\n    \\returns\n        the 8-bit values sign-extended to 16-bit values.\n            \\li     sign-extended value of val[7:0] in the low halfword of the return value.\n            \\li     sign-extended value of val[23:16] in the high halfword of the return value.\n\n\n    \\par Operation:\n        \\code\n   val        = Rotate(val, rotate)\n   res[15:0]  = SignExtended(val[7:0])\n   res[31:16] = SignExtended(val[23:16])\n        \\endcode\n*/\nuint32_t __SXTB16_RORn(uint32_t val, uint32_r rotate);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual extracted 8-bit to 16-bit signed addition\n\n    \\details    This function enables you to extract two 8-bit values from the second operand (at bit\n          positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the\n          first operand.\n\n    \\param      val1    values added to the zero-extended to 16-bit values.\n    \\param      val2    two 8-bit values to be extracted and zero-extended.\n\n\n\n    \\returns\n        the addition of \\em val1 and \\em val2, where the 8-bit values in\n            val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.\n\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]  + SignExtended(val2[7:0])\n   res[31:16] = val1[31:16] + SignExtended(val2[23:16])\n    \\endcode\n*/\nuint32_t __SXTAB16(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Rotate right, followed by sign extension of two 8-bits with add to 16-bits\n\n    \\details    This function enables you to rotate the second operand by 8/16/24 bit as specified by the third\n          operand, extract two 8-bit values from the rotated result (at bit positions [7:0] and [23:16]),\n          sign-extend them to 16-bits each, and add the results to the first operand.\n\n    \\param      val1    two 16-bit values in val1[15:0] and val1[31:16]\n    \\param      val2    two 8-bit values in val[7:0] and val[23:16] to be sign-extended post rotation\n    \\param      rotate  number of bits to rotate val2. Constant rotate value of 8, 16 and 24 can be\n                \toptimally used with a single __SXTAB16 instruction. Any other valid constant rotate\n\t\t\tvalue will result in use of two instructions, __ROR and __SXTAB16\n\n\n    \\returns\n        the addition of \\em val1 and \\em val2, where the rotated 8-bit values in\n            val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.\n\n\n    \\par Operation:\n        \\code\n   val2       = Rotate(val2, rotate)\n   res[15:0]  = val1[15:0]  + SignExtended(val2[7:0])\n   res[31:16] = val1[31:16] + SignExtended(val2[23:16])\n        \\endcode\n*/\nuint32_t __SXTAB16_RORn(uint32_t val1, uint32_t val2, uint32_r rotate);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting sum of dual 16-bit signed multiply\n\n    \\details    This function enables you to perform two 16-bit signed multiplications, adding the\n          products together.<br>\n          The Q bit is set if the addition overflows.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n\n\n\n    \\returns\n        the sum of the products of the two 16-bit signed multiplications.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[15:0]\n   p2 = val1[31:16] * val2[31:16]\n   res[31:0] = p1 + p2\n    \\endcode\n*/\nuint32_t __SMUAD(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting sum of dual 16-bit signed multiply with exchange\n\n    \\details    This function enables you to perform two 16-bit signed multiplications with exchanged\n          halfwords of the second operand, adding the products together.<br>\n          The Q bit is set if the addition overflows.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n\n\n\n    \\returns\n        the sum of the products of the two 16-bit signed multiplications with exchanged\n            halfwords of the second operand.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[31:16]\n   p2 = val1[31:16] * val2[15:0]\n   res[31:0] = p1 + p2\n    \\endcode\n*/\nuint32_t __SMUADX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      32-bit signed multiply with 32-bit truncated accumulator.\n\n    \\details    This function enables you to perform a signed 32-bit multiplications, adding the most significant 32 bits\n\t            of the 64-bit result to a 32-bit accumulate operand.<br>\n\n    \\param      val1    first operand for multiplication.\n    \\param      val2    second operand for multiplication.\n    \\param      val3    accumulate value.\n\n\n    \\returns    the product of multiplication (most significant 32 bits) is added to the accumulate\n            value, as a 32-bit integer.\n\n     \\par Operation:\n        \\code\n   p = val1 * val2\n   res[31:0] = p[61:32] + val3[31:0]\n    \\endcode\n*/\nuint32_t __SMMLA (int32_t val1, int32_t val2, int32_t val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit signed multiply with single 32-bit accumulator\n\n    \\details    This function enables you to perform two signed 16-bit multiplications, adding both\n          results to a 32-bit accumulate operand.<br>\n          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n    \\param      val3    accumulate value.\n\n\n    \\returns\n        the product of each multiplication added to the accumulate\n            value, as a 32-bit integer.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[15:0]\n   p2 = val1[31:16] * val2[31:16]\n   res[31:0] = p1 + p2 + val3[31:0]\n    \\endcode\n*/\nuint32_t __SMLAD(uint32_t val1, uint32_t val2, uint32_t val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator\n\n    \\details    This function enables you to perform two signed 16-bit multiplications with exchanged\n          halfwords of the second operand, adding both results to a 32-bit accumulate operand.<br>\n          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n    \\param      val3    accumulate value.\n\n\n    \\returns\n        the product of each multiplication with exchanged\n            halfwords of the second operand added to the accumulate value, as a 32-bit integer.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[31:16]\n   p2 = val1[31:16] * val2[15:0]\n   res[31:0] = p1 + p2 + val3[31:0]\n    \\endcode\n*/\nuint32_t __SMLADX(uint32_t val1, uint32_t val2, uint32_t val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit signed multiply with single 64-bit accumulator\n\n    \\details    This function enables you to perform two signed 16-bit multiplications, adding both\n          results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit\n          addition. This overflow is not detected if it occurs. Instead, the result wraps around\n          modulo2<sup>64</sup>.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n    \\param      val3    accumulate value.\n\n\n    \\returns\n        the product of each multiplication added to the accumulate value.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[15:0]\n   p2 = val1[31:16] * val2[31:16]\n   sum = p1 + p2 + val3[63:32][31:0]\n   res[63:32] = sum[63:32]\n   res[31:0]  = sum[31:0]\n    \\endcode\n*/\nuint64_t __SMLALD(uint32_t val1, uint32_t val2, uint64_t val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit signed multiply with exchange with single 64-bit accumulator\n\n    \\details    This function enables you to exchange the halfwords of the second operand, and perform\n          two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand.\n          Overflow is only possible as a result of the 64-bit addition. This overflow is not detected\n          if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n    \\param      val3    accumulate value.\n\n\n    \\returns\n        the product of each multiplication added to the accumulate value.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[31:16]\n   p2 = val1[31:16] * val2[15:0]\n   sum = p1 + p2 + val3[63:32][31:0]\n   res[63:32] = sum[63:32]\n   res[31:0] = sum[31:0]\n    \\endcode\n*/\nunsigned long long __SMLALDX(uint32_t val1, uint32_t val2, unsigned long long val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit signed multiply returning difference\n\n    \\details    This function enables you to perform two 16-bit signed multiplications, taking the\n          difference of the products by subtracting the high halfword product from the low\n          halfword product.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n\n\n    \\returns\n        the difference of the products of the two 16-bit signed multiplications.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[15:0]\n   p2 = val1[31:16] * val2[31:16]\n   res[31:0] = p1 - p2\n    \\endcode\n*/\nuint32_t __SMUSD(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Dual 16-bit signed multiply with exchange returning difference\n\n    \\details    This function enables you to perform two 16-bit signed multiplications, subtracting one\n          of the products from the other. The halfwords of the second operand are exchanged\n          before performing the arithmetic. This produces top * bottom and bottom * top\n          multiplication.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n\n\n    \\returns\n        the difference of the products of the two 16-bit signed multiplications.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[31:16]\n   p2 = val1[31:16] * val2[15:0]\n   res[31:0] = p1 - p2\n    \\endcode\n*/\nuint32_t __SMUSDX(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit signed multiply subtract with 32-bit accumulate\n\n    \\details    This function enables you to perform two 16-bit signed multiplications, take the\n          difference of the products, subtracting the high halfword product from the low halfword\n          product, and add the difference to a 32-bit accumulate operand.<br>\n          The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the\n          subtraction.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n    \\param      val3    accumulate value.\n\n\n    \\returns\n        the difference of the product of each multiplication, added\n            to the accumulate value.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[15:0]\n   p2 = val1[31:16] * val2[31:16]\n   res[31:0] = p1 - p2 + val3[31:0]\n    \\endcode\n*/\nuint32_t __SMLSD(uint32_t val1, uint32_t val2, uint32_t val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate\n\n    \\details    This function enables you to exchange the halfwords in the second operand, then perform\n          two 16-bit signed multiplications. The difference of the products is added to a 32-bit\n          accumulate operand.<br>\n          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n    \\param      val3    accumulate value.\n\n\n    \\returns\n        the difference of the product of each multiplication, added\n            to the accumulate value.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[31:16]\n   p2 = val1[31:16] * val2[15:0]\n   res[31:0] = p1 - p2 + val3[31:0]\n    \\endcode\n*/\nuint32_t __SMLSDX(uint32_t val1, uint32_t val2, uint32_t val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit signed multiply subtract with 64-bit accumulate\n\n    \\details    This function It enables you to perform two 16-bit signed multiplications, take the\n          difference of the products, subtracting the high halfword product from the low halfword\n          product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur\n          during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit\n          addition, and this overflow is not detected. Instead, the result wraps round to\n          modulo2<sup>64</sup>.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n    \\param      val3    accumulate value.\n\n\n    \\returns\n        the difference of the product of each multiplication,\n            added to the accumulate value.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[15:0]\n   p2 = val1[31:16] * val2[31:16]\n   res[63:0] = p1 - p2 + val3[63:0]\n    \\endcode\n*/\nuint64_t __SMLSLD(uint32_t val1, uint32_t val2, uint64_t val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate\n\n    \\details    This function enables you to exchange the halfwords of the second operand, perform two\n          16-bit multiplications, adding the difference of the products to a 64-bit accumulate\n          operand. Overflow cannot occur during the multiplications or the subtraction. Overflow\n          can occur as a result of the 64-bit addition, and this overflow is not detected. Instead,\n          the result wraps round to modulo2<sup>64</sup>.\n\n    \\param      val1    first 16-bit operands for each multiplication.\n    \\param      val2    second 16-bit operands for each multiplication.\n    \\param      val3    accumulate value.\n\n\n    \\returns\n        the difference of the product of each multiplication,\n            added to the accumulate value.\n\n\n    \\par Operation:\n        \\code\n   p1 = val1[15:0]  * val2[31:16]\n   p2 = val1[31:16] * val2[15:0]\n   res[63:0] = p1 - p2 + val3[63:0]\n    \\endcode\n*/\nunsigned long long __SMLSLDX(uint32_t val1, uint32_t val2, unsigned long long val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Select bytes based on GE bits\n\n    \\details    This function inserts a SEL instruction into the instruction stream generated by the\n          compiler. It enables you to select bytes from the input parameters, whereby the bytes\n          that are selected depend upon the results of previous SIMD instruction function. The\n          results of previous SIMD instruction function are represented by the Greater than or\n          Equal flags in the Application Program Status Register (APSR).\n          The __SEL function works equally well on both halfword and byte operand function\n          results. This is because halfword operand operations set two (duplicate) GE bits per\n          value.\n\n    \\param      val1    four selectable 8-bit values.\n    \\param      val2    four selectable 8-bit values.\n\n\n    \\returns\n        The function selects bytes from the input parameters and returns them in the\n            return value, res, according to the following criteria:\n            \\li if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]\n            \\li if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]\n            \\li if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]\n            \\li if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]\n\n*/\nuint32_t __SEL(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting saturating add\n\n    \\details    This function enables you to obtain the saturating add of two integers.<br>\n         The Q bit is set if the operation saturates.\n\n    \\param      val1    first summand of the saturating add operation.\n    \\param      val2    second summand of the saturating add operation.\n\n\n    \\returns\n        the saturating addition of val1 and val2.\n\n    \\par Operation:\n        \\code\n   res[31:0] = SAT(val1 + SAT(val2))\n        \\endcode\n*/\nuint32_t __QADD(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Q setting saturating subtract\n\n    \\details    This function enables you to obtain the saturating subtraction of two integers.<br>\n         The Q bit is set if the operation saturates.\n\n    \\param      val1    minuend of the saturating subtraction operation.\n    \\param      val2    subtrahend of the saturating subtraction operation.\n\n\n    \\returns\n        the saturating subtraction of val1 and val2.\n\n    \\par Operation:\n        \\code\n   res[31:0] = SAT(val1 - SAT(val2))\n        \\endcode\n*/\nuint32_t __QSUB(uint32_t val1, uint32_t val2);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Halfword packing instruction. Combines bits[15:0] of <i>val1</i>\n                with bits[31:16] of <i>val2</i> levitated with the <i>val3</i>.\n\n    \\details    Combine a halfword from one register with a halfword from another register.\n                The second argument can be left-shifted before extraction of the halfword. The registers\n                PC and SP are not allowed as arguments. This instruction does not change the flags.\n\n    \\param      val1    first 16-bit operands\n    \\param      val2    second 16-bit operands\n    \\param      val3    value for left-shifting <i>val2</i>. Value range [0..31].\n\n\n    \\returns\n        the combination of halfwords.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val1[15:0]\n   res[31:16] = val2[31:16]<<val3\n        \\endcode\n*/\nuint32_t __PKHBT(uint32_t val1, uint32_t val2, uint32_t val3);\n\n\n/**************************************************************************************************/\n/**\n    \\brief      Halfword packing instruction. Combines bits[31:16] of <i>val1</i>\n                with bits[15:0] of <i>val2</i> right-shifted with the <i>val3</i>.\n\n    \\details    Combines a halfword from one register with a halfword from another register.\n                The second argument can be right-shifted before extraction of the halfword. The registers\n                PC and SP are not allowed as arguments. This instruction does not change the flags.\n\n    \\param      val1    second 16-bit operands\n    \\param      val2    first 16-bit operands\n    \\param      val3    value for right-shifting <i>val2</i>. Value range [1..32].\n\n\n    \\returns\n        the combination of halfwords.\n\n    \\par Operation:\n        \\code\n   res[15:0]  = val2[15:0]>>val3\n   res[31:16] = val1[31:16]\n        \\endcode\n*/\nuint32_t __PKHTB(uint32_t val1, uint32_t val2, uint32_t val3);\n\n/** @} */  /* end group intrinsic_SIMD_gr */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_cmInstr.txt",
    "content": "/**\n\\defgroup intrinsic_CPU_gr Intrinsic Functions for CPU Instructions\n@{\n\\brief Functions that generate specific Cortex-M CPU Instructions.\n\\details\nThe following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler.\nRefer to the \\ref ref_man_sec for detailed information about these Cortex-M instructions.\n\n\\note\nWhen using the <b>Arm Compiler Version 5 Toolchain</b> the following \\ref intrinsic_CPU_gr are implemented using the Embedded Assembler. \nAs the Embedded Assembler may cause side effects (Refer to <b>Arm Compiler v5.xx User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information)\nit is possible to disable the following intrinsic functions and therefore the usage of the Embedded Assembler with the <b><i>define __NO_EMBEDDED_ASM</i></b>: \n - \\ref __REV16\n - \\ref __REVSH\n - \\ref __RRX\n\n\n*/\n/**************************************************************************************************/\n/** \\brief  No Operation\n\n    This function does nothing. This instruction can be used for code alignment purposes.\n */\nvoid __NOP(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Wait For Interrupt\n\n    WFI is a hint instruction that suspends execution until one of the following events occurs:\n    - A non-masked interrupt occurs and is taken.\n    - An interrupt masked by PRIMASK becomes pending.\n    - A Debug Entry request.\n */\nvoid __WFI(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Wait For Event\n\n    Wait For Event is a hint instruction that permits the processor to enter\n    a low-power state until an events occurs:\n    \\li If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:\n    - An exception, unless masked by the exception mask registers or the current priority level.\n    - An exception enters the Pending state, if SEVONPEND in the System Control Register is set.\n    - A Debug Entry request, if Debug is enabled.\n    - An event signaled by a peripheral or another processor in a multiprocessor system using\n    the SEV instruction.\n    \n    \\li If the <b>event register is 1</b>, then WFE clears it to 0 and returns immediately.\n    \n */\nvoid __WFE(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Send Event\n\n    Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\nvoid __SEV(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Set Breakpoint\n\nThis function causes the processor to enter Debug state.\nDebug tools can use this to investigate system state when the instruction at a particular address is reached.\n\n\\param [in]    value  is ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint.\n*/\nvoid __BKPT(uint8_t value);\n\n\n/**************************************************************************************************/\n/** \\brief  Instruction Synchronization Barrier\n\n    Instruction Synchronization Barrier flushes the pipeline in the processor, \n    so that all instructions following the ISB are fetched from cache or \n    memory, after the instruction has been completed.\n */\nvoid __ISB(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Data Synchronization Barrier\n\n\\details\nThis function acts as a special kind of Data Memory Barrier. \nIt completes when all explicit memory accesses before this instruction complete.\n */\nvoid __DSB(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Data Memory Barrier\n\n\\details\nThis function ensures the apparent order of the explicit memory operations before \nand after the instruction, without ensuring their completion.\n */\nvoid __DMB(void);\n\n\n/**************************************************************************************************/\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\nuint32_t __REV(uint32_t value);\n\n\n/**************************************************************************************************/\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\nuint32_t __REV16(uint32_t value);\n\n\n/**************************************************************************************************/\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\nint16_t __REVSH(int16_t value);\n\n\n/**************************************************************************************************/\n/**\n  \\brief   Reverse bit order of value\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\nuint32_t __RBIT(uint32_t value);\n\n\n/**************************************************************************************************/\n/** \\brief  Rotate a value right by a number of bits\n\n    This function rotates a value right by a specified number of bits.\n\n    \\param [in]    value  Value to be shifted right\n    \\param [in]    shift  Number of bits in the range [1..31]\n    \\return               Rotated value\n\t\n */\nuint32_t __ROR(uint32_t value, uint32_t shift);\n\n\n/**************************************************************************************************/\n/** \\brief  LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function executed an exclusive LDR command for 8 bit value [not for Cortex-M0, Cortex-M0+, or SC000].\n\n    \\param [in]    *addr  Pointer to data\n    \\return             value of type uint8_t at (*addr)\n */\nuint8_t __LDREXB(volatile uint8_t *addr);\n\n\n/**************************************************************************************************/\n/** \\brief  LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function executed an exclusive LDR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].\n\n    \\param [in]    *addr  Pointer to data\n    \\return        value of type uint16_t at (*addr)\n */\nuint16_t __LDREXH(volatile uint16_t *addr);\n\n\n/**************************************************************************************************/\n/** \\brief  LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function executed an exclusive LDR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].\n\n    \\param [in]    *addr  Pointer to data\n    \\return        value of type uint32_t at (*addr)\n */\nuint32_t __LDREXW(volatile uint32_t *addr);\n\n\n/**************************************************************************************************/\n/** \\brief  STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function executed an exclusive STR command for 8 bit values [not for Cortex-M0, Cortex-M0+, or SC000].\n\n    \\param [in]  value  Value to store\n    \\param [in]  *addr  Pointer to location\n    \\return          0  Function succeeded\n    \\return          1  Function failed\n */\nuint32_t __STREXB(uint8_t value, volatile uint8_t *addr);\n\n\n/**************************************************************************************************/\n/** \\brief  STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function executed an exclusive STR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].\n\n    \\param [in]  value  Value to store\n    \\param [in]  *addr  Pointer to location\n    \\return          0  Function succeeded\n    \\return          1  Function failed\n */\nuint32_t __STREXH(uint16_t value, volatile uint16_t *addr);\n\n\n/**************************************************************************************************/\n/** \\brief  STR Exclusive (32 bit)  [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function executed an exclusive STR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].\n\n    \\param [in]  value  Value to store\n    \\param [in]  *addr  Pointer to location\n    \\return          0  Function succeeded\n    \\return          1  Function failed\n */\nuint32_t __STREXW(uint32_t value, volatile uint32_t *addr);\n\n\n/**************************************************************************************************/\n/** \\brief  Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000]\n\n    This function removes the exclusive lock which is created by LDREX [not for Cortex-M0, Cortex-M0+, or SC000].\n\n */\nvoid __CLREX(void);\n\n\n/**************************************************************************************************/\n/** \\brief  Signed Saturate\n\n    This function saturates a signed value.\n    The Q bit is set if saturation occurs [not for Cortex-M0, Cortex-M0+, or SC000].\n\n    On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction\n    instruction and thus __SSAT is implemented in software.\n\n    \\param [in]  value  Value to be saturated\n    \\param [in]    sat  Bit position to saturate to [1..32]\n    \\return             Saturated value\n */\nint32_t __SSAT(int32_t value, uint32_t sat);\n\n\n/**************************************************************************************************/\n/** \\brief  Unsigned Saturate\n\n    This function saturates an unsigned value.\n    The Q bit is set if saturation occurs [not for Cortex-M0, Cortex-M0+, or SC000].\n\n    On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction\n    instruction and thus __USAT is implemented in software.\n\n    \\param [in]  value  Value to be saturated\n    \\param [in]    sat  Bit position to saturate to [0..31]\n    \\return             Saturated value\n */\nuint32_t __USAT(int32_t value, uint32_t sat);\n\n\n/**************************************************************************************************/\n/** \\brief  Count leading zeros\n\n    This function counts the number of leading zeros of a data value.\n    \n    On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction\n    instruction and thus __CLZ is implemented in software.\n\n    \\param [in]  value  Value to count the leading zeros\n    \\return             number of leading zeros in value\n */\nuint8_t __CLZ(uint32_t value);\n\n\n/**************************************************************************************************/\n/** \\brief  Rotate Right with Extend (32 bit)\n\n    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.\n\n    \\param [in]    value  Value to rotate\n    \\return               Rotated value\n */\nuint32_t __RRX(uint32_t value);\n\n\n/**************************************************************************************************/\n/** \\brief  LDRT Unprivileged (8 bit)\n\n    This function executed an Unprivileged LDRT command for 8 bit value.\n\n    \\param [in]    ptr  Pointer to data\n    \\return             value of type uint8_t at (*ptr)\n */\nuint8_t  __LDRBT(uint8_t ptr);\n\n\n/**************************************************************************************************/\n/** \\brief  LDRT Unprivileged (16 bit)\n\n    This function executed an Unprivileged LDRT command for 16 bit values.\n\n    \\param [in]    ptr  Pointer to data\n    \\return        value of type uint16_t at (*ptr)\n */\nuint16_t  __LDRHT(uint16_t ptr);\n\n\n/**************************************************************************************************/\n/** \\brief  LDRT Unprivileged (32 bit)\n\n    This function executed an Unprivileged LDRT command for 32 bit values.\n\n    \\param [in]    ptr  Pointer to data\n    \\return        value of type uint32_t at (*ptr)\n */\nuint32_t  __LDRT(uint32_t ptr);\n\n\n/**************************************************************************************************/\n/** \\brief  STRT Unprivileged (8 bit)\n\n    This function executed an Unprivileged STRT command for 8 bit values.\n\n    \\param [in]  value  Value to store\n    \\param [in]    ptr  Pointer to location\n */\nvoid __STRBT(uint8_t value, uint8_t ptr);\n\n\n/**************************************************************************************************/\n/** \\brief  STRT Unprivileged (16 bit)\n\n    This function executed an Unprivileged STRT command for 16 bit values.\n\n    \\param [in]  value  Value to store\n    \\param [in]    ptr  Pointer to location\n */\nvoid __STRHT(uint16_t value, uint16_t ptr);\n\n\n/**************************************************************************************************/\n/** \\brief  STRT Unprivileged (32 bit)\n\n    This function executed an Unprivileged STRT command for 32 bit values.\n\n    \\param [in]  value  Value to store\n    \\param [in]    ptr  Pointer to location\n */\nvoid __STRT(uint32_t value, uint32_t ptr);\n\n\n/**\n\\cond (ARMv8M)\n*/\n\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n  \\note    Only available for Armv8-M Architecture. \n */\nuint8_t __LDAB(volatile uint8_t *ptr);\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n  \\note    Only available for Armv8-M Architecture. \n */\nuint16_t __LDAH(volatile uint16_t *ptr);\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n  \\note    Only available for Armv8-M Architecture. \n */\nuint32_t __LDA(volatile uint32_t *ptr);\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\note    Only available for Armv8-M Architecture. \n */\nvoid __STLB(uint8_t value, volatile uint8_t *ptr);\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\note    Only available for Armv8-M Architecture. \n */\nvoid __STLH(uint16_t value, volatile uint16_t *ptr);\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\note    Only available for Armv8-M Architecture. \n */\nvoid __STL(uint32_t value, volatile uint32_t *ptr);\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n  \\note    Only available for Armv8-M Architecture. \n */\nuint8_t __LDAEXB(volatile uint32_t *ptr);\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n  \\note    Only available for Armv8-M Architecture. \n */\nuint16_t __LDAEXH(volatile uint32_t *ptr);\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n  \\note    Only available for Armv8-M Architecture. \n */\nuint32_t __LDAEX(volatile uint32_t *ptr);\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n  \\note    Only available for Armv8-M Architecture. \n */\nuint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr);\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n  \\note    Only available for Armv8-M Architecture. \n */\nuint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr);\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n  \\note    Only available for Armv8-M Architecture. \n */\nuint32_t __STLEX(uint32_t value, volatile uint32_t *ptr);\n\n/**\n\\endcond\n*/\n\n/*@}*/ /* end of group Intrisic_CPU */\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/RegMap_CMSIS2ARM_Doc.txt",
    "content": "/** \n\\page regMap_pg  Register Mapping\n\n\\details \n\nThe table below associates some common register names used in CMSIS to the register names \nused in Technical Reference Manuals.\n\n<table class=\"cmtable\" summary=\"Register Mapping\">\n    <tr>\n      <th>CMSIS Register Name</th>\n      <th>Cortex-M3, Cortex-M4, and Cortex-M7</th>\n      <th>Cortex-M0 and Cortex-M0+</th>\n      <th>Register Name</th>\n    </tr>\n    <tr>\n      <th colspan=\"4\">Nested Vectored Interrupt Controller (NVIC) Register Access</th>\n    </tr>\n    <tr>\n      <td>NVIC->ISER[]</td>\n      <td>NVIC_ISER0..7</td>\n      <td>ISER</td>\n      <td>Interrupt Set-Enable Registers</td>\n    </tr>\n    <tr>\n      <td>NVIC->ICER[]</td>\n      <td>NVIC_ICER0..7</td>\n      <td>ICER</td>\n      <td>Interrupt Clear-Enable Registers</td>\n    </tr>\n   <tr>\n      <td>NVIC->ISPR[]</td>\n      <td>NVIC_ISPR0..7</td>\n      <td>ISPR</td>\n      <td>Interrupt Set-Pending Registers</td>\n    </tr>\n  <tr>\n      <td>NVIC->ICPR[]</td>\n      <td>NVIC_ICPR0..7</td>\n      <td>ICPR</td>\n      <td>Interrupt Clear-Pending Registers</td>\n    </tr>\n  <tr>\n      <td>NVIC->IABR[]</td>\n      <td>NVIC_IABR0..7</td>\n      <td>-</td>\n      <td>Interrupt Active Bit Register</td>\n  </tr>\n  <tr>\n      <td>NVIC->IP[]</td>\n      <td>NVIC_IPR0..59</td>\n      <td>IPR0..7</td>\n      <td>Interrupt Priority Register</td>\n  </tr>\n  <tr>\n      <td>NVIC->STIR</td>\n      <td>STIR</td>\n      <td>-</td>\n      <td>Software Triggered Interrupt Register</td>\n  </tr>\n  <tr>\n    <th colspan=\"4\">System Control Block (SCB) Register Access</th>\n  </tr>\n  <tr>\n      <td>SCB->CPUID</td>\n      <td>CPUID</td>\n      <td>CPUID</td>\n      <td>CPUID Base Register</td>\n  </tr>\n  <tr>\n      <td>SCB->ICSR</td>\n      <td>ICSR</td>\n      <td>ICSR</td>\n      <td>Interrupt Control and State Register</td>\n  </tr>\n  <tr>\n      <td>SCB->VTOR</td>\n      <td>VTOR</td>\n      <td>-</td>\n      <td>Vector Table Offset Register</td>\n  </tr>\n  <tr>\n      <td>SCB->AIRCR</td>\n      <td>AIRCR</td>\n      <td>AIRCR</td>\n      <td>Application Interrupt and Reset Control Register</td>\n  </tr>\n  <tr>\n      <td>SCB->SCR</td>\n      <td>SCR</td>\n      <td>SCR</td>\n      <td>System Control Register</td>\n  </tr>\n  <tr>\n      <td>SCB->CCR</td>\n      <td>CCR</td>\n      <td>CCR</td>\n      <td>Configuration and Control Register</td>\n  </tr>\n  <tr>\n      <td>SCB->SHP[]</td>\n      <td>SHPR1..3</td>\n      <td>SHPR2..3</td>\n      <td>System Handler Priority Registers</td>\n  </tr>\n  <tr>\n      <td>SCB->SHCSR</td>\n      <td>SHCSR</td>\n      <td>SHCSR</td>\n      <td>System Handler Control and State Register</td>\n  </tr>\n  <tr>\n      <td>SCB->CFSR</td>\n      <td>CFSR</td>\n      <td>-</td>\n      <td>Configurable Fault Status Registers</td>\n  </tr>\n  <tr>\n      <td>SCB->HFSR</td>\n      <td>HFSR</td>\n      <td>-</td>\n      <td>HardFault Status Register</td>\n  </tr>\n  <tr>\n      <td>SCB->DFSR</td>\n      <td>DFSR</td>\n      <td>-</td>\n      <td>Debug Fault Status Register</td>\n  </tr>\n  <tr>\n      <td>SCB->MMFAR</td>\n      <td>MMFAR</td>\n      <td>-</td>\n      <td>MemManage Fault Address Register</td>\n  </tr>\n  <tr>\n      <td>SCB->BFAR</td>\n      <td>BFAR</td>\n      <td>-</td>\n      <td>BusFault Address Register</td>\n  </tr>\n  <tr>\n      <td>SCB->AFSR</td>\n      <td>AFSR</td>\n      <td>-</td>\n      <td>Auxiliary Fault Status Register</td>\n  </tr>\n  <tr>\n      <td>SCB->PFR[]</td>\n      <td>ID_PFR0..1</td>\n      <td>-</td>\n      <td>Processor Feature Registers</td>\n  </tr>\n  <tr>\n      <td>SCB->DFR</td>\n      <td>ID_DFR0</td>\n      <td>-</td>\n      <td>Debug Feature Register</td>\n  </tr>\n  <tr>\n      <td>SCB->ADR</td>\n      <td>ID_AFR0</td>\n      <td>-</td>\n      <td>Auxiliary Feature Register</td>\n  </tr>\n  <tr>\n      <td>SCB->MMFR[]</td>\n      <td>ID_MMFR0..3</td>\n      <td>-</td>\n      <td>Memory Model Feature Registers</td>\n  </tr>\n  <tr>\n      <td>SCB->ISAR[]</td>\n      <td>ID_ISAR0..4</td>\n      <td>-</td>\n      <td>Instruction Set Attributes Registers</td>\n  </tr>\n  <tr>\n      <td>SCB->CPACR</td>\n      <td>CPACR</td>\n      <td>-</td>\n      <td>Coprocessor Access Control Register</td>\n  </tr>\n  <tr>\n    <th colspan=\"4\">System Control and ID Registers not in the SCB (SCnSCB) Register Access</th>\n  </tr>\n  <tr>\n      <td>SCnSCB->ICTR</td>\n      <td>ICTR</td>\n      <td>-</td>\n      <td>Interrupt Controller Type Register</td>\n  </tr>\n  <tr>\n      <td>SCnSCB->ACTLR</td>\n      <td>ACTLR</td>\n      <td>-</td>\n      <td>Auxiliary Control Register</td>\n  </tr>\n  <tr>\n    <th colspan=\"4\">System Timer (SysTick) Control and Status Register Access</th>\n  </tr>\n  <tr>\n      <td>SysTick->CTRL</td>\n      <td>STCSR</td>\n      <td>SYST_CSR</td>\n      <td>SysTick Control and Status Register</td>\n  </tr>\n  <tr>\n      <td>SysTick->LOAD</td>\n      <td>STRVR</td>\n      <td>SYST_RVR</td>\n      <td>SysTick Reload Value Register</td>\n  </tr>\n  <tr>\n      <td>SysTick->VAL</td>\n      <td>STCVR</td>\n      <td>SYST_CVR</td>\n      <td>SysTick Current Value Register</td>\n  </tr>\n  <tr>\n      <td>SysTick->CALIB</td>\n      <td>STCR</td>\n      <td>SYST_CALIB</td>\n      <td>SysTick Calibaration Value Register</td>\n  </tr>\n  <tr>\n    <th colspan=\"4\">Data Watchpoint and Trace (DWT) Register Access</th>\n  </tr>\n  <tr>\n      <td>DWT->CTRL</td>\n      <td>DWT_CTRL</td>\n      <td>-</td>\n      <td>Control Register</td>\n  </tr>\n  <tr>\n      <td>DWT->CYCCNT</td>\n      <td>DWT_CYCCNT</td>\n      <td>-</td>\n      <td>Cycle Count Register</td>\n  </tr>\n  <tr>\n      <td>DWT->CPICNT</td>\n      <td>DWT_CPICNT</td>\n      <td>-</td>\n      <td>CPI Count Register</td>\n  </tr>\n  <tr>\n      <td>DWT->EXCCNT</td>\n      <td>DWT_EXCCNT</td>\n      <td>-</td>\n      <td>Exception Overhead Count Register</td>\n  </tr>\n  <tr>\n      <td>DWT->SLEEPCNT</td>\n      <td>DWT_SLEEPCNT</td>\n      <td>-</td>\n      <td>Sleep Count Register</td>\n  </tr>\n  <tr>\n      <td>DWT->LSUCNT</td>\n      <td>DWT_LSUCNT</td>\n      <td>-</td>\n      <td>LSU Count Register</td>\n  </tr>\n  <tr>\n      <td>DWT->FOLDCNT</td>\n      <td>DWT_FOLDCNT</td>\n      <td>-</td>\n      <td>Folded-instruction Count Register</td>\n  </tr>\n  <tr>\n      <td>DWT->PCSR</td>\n      <td>DWT_PCSR</td>\n      <td>-</td>\n      <td>Program Counter Sample Register</td>\n  </tr>\n  <tr>\n      <td>DWT->COMP0..3</td>\n      <td>DWT_COMP0..3</td>\n      <td>-</td>\n      <td>Comparator Register 0..3</td>\n  </tr>\n  <tr>\n      <td>DWT->MASK0..3</td>\n      <td>DWT_MASK0..3</td>\n      <td>-</td>\n      <td>Mask Register 0..3</td>\n  </tr>\n  <tr>\n      <td>DWT->FUNCTION0..3</td>\n      <td>DWT_FUNCTION0..3</td>\n      <td>-</td>\n      <td>Function Register 0..3</td>\n  </tr>\n  <tr>\n    <th colspan=\"4\">Instrumentation Trace Macrocell (ITM) Register Access</th>\n  </tr>\n  <tr>\n      <td>ITM->PORT[]</td>\n      <td>ITM_STIM0..31</td>\n      <td>-</td>\n      <td>Stimulus Port Registers</td>\n  </tr>\n  <tr>\n      <td>ITM->TER</td>\n      <td>ITM_TER</td>\n      <td>-</td>\n      <td>Trace Enable Register</td>\n  </tr>\n  <tr>\n      <td>ITM->TPR</td>\n      <td>ITM_TPR</td>\n      <td>-</td>\n      <td>ITM Trace Privilege Register</td>\n  </tr>\n  <tr>\n      <td>ITM->TCR</td>\n      <td>ITM_TCR</td>\n      <td>-</td>\n      <td>Trace Control Register</td>\n  </tr>\n  <tr>\n    <th colspan=\"4\">Trace Port Interface (TPIU) Register Access</th>\n  </tr>\n  <tr>\n      <td>TPI->SSPSR</td>\n      <td>TPIU_SSPR</td>\n      <td>-</td>\n      <td>Supported Parallel Port Size Register</td>\n  </tr>\n  <tr>\n      <td>TPI->CSPSR</td>\n      <td>TPIU_CSPSR</td>\n      <td>-</td>\n      <td>Current Parallel Port Size Register</td>\n  </tr>\n  <tr>\n      <td>TPI->ACPR</td>\n      <td>TPIU_ACPR</td>\n      <td>-</td>\n      <td>Asynchronous Clock Prescaler Register</td>\n  </tr>\n  <tr>\n      <td>TPI->SPPR</td>\n      <td>TPIU_SPPR</td>\n      <td>-</td>\n      <td>Selected Pin Protocol Register</td>\n  </tr>\n  <tr>\n      <td>TPI->FFSR</td>\n      <td>TPIU_FFSR</td>\n      <td>-</td>\n      <td>Formatter and Flush Status Register</td>\n  </tr>\n  <tr>\n      <td>TPI->FFCR</td>\n      <td>TPIU_FFCR</td>\n      <td>-</td>\n      <td>Formatter and Flush Control Register</td>\n  </tr>\n  <tr>\n      <td>TPI->FSCR</td>\n      <td>TPIU_FSCR</td>\n      <td>-</td>\n      <td>Formatter Synchronization Counter Register</td>\n  </tr>\n  <tr>\n      <td>TPI->TRIGGER</td>\n      <td>TRIGGER</td>\n      <td>-</td>\n      <td>TRIGGER</td>\n  </tr>\n  <tr>\n      <td>TPI->FIFO0</td>\n      <td>FIFO data 0</td>\n      <td>-</td>\n      <td>Integration ETM Data</td>\n  </tr>\n  <tr>\n      <td>TPI->ITATBCTR2</td>\n      <td>ITATBCTR2</td>\n      <td>-</td>\n      <td>ITATBCTR2</td>\n  </tr>\n  <tr>\n      <td>TPI->ITATBCTR0</td>\n      <td>ITATBCTR0</td>\n      <td>-</td>\n      <td>ITATBCTR0</td>\n  </tr>\n  <tr>\n      <td>TPI->FIFO1</td>\n      <td>FIFO data 1</td>\n      <td>-</td>\n      <td>Integration ITM Data</td>\n  </tr>\n  <tr>\n      <td>TPI->ITCTRL</td>\n      <td>TPIU_ITCTRL</td>\n      <td>-</td>\n      <td>Integration Mode Control</td>\n  </tr>\n  <tr>\n      <td>TPI->CLAIMSET</td>\n      <td>CLAIMSET</td>\n      <td>-</td>\n      <td>Claim tag set</td>\n  </tr>\n  <tr>\n      <td>TPI->CLAIMCLR</td>\n      <td>CLAIMCLR</td>\n      <td>-</td>\n      <td>Claim tag clear</td>\n  </tr>\n  <tr>\n      <td>TPI->DEVID</td>\n      <td>TPIU_DEVID</td>\n      <td>-</td>\n      <td>TPIU_DEVID</td>\n  </tr>\n  <tr>\n      <td>TPI->DEVTYPE</td>\n      <td>TPIU_DEVTYPE</td>\n      <td>-</td>\n      <td>TPIU_DEVTYPE</td>\n  </tr>\n  <tr>\n    <th colspan=\"4\">Memory Protection Unit (MPU) Register Access</th>\n  </tr>\n  <tr>\n      <td>MPU->TYPE</td>\n      <td>MPU_TYPE</td>\n      <td>-</td>\n      <td>MPU Type Register</td>\n  </tr>\n  <tr>\n      <td>MPU->CTRL</td>\n      <td>MPU_CTRL</td>\n      <td>-</td>\n      <td>MPU Control Register</td>\n  </tr>\n  <tr>\n      <td>MPU->RNR</td>\n      <td>MPU_RNR</td>\n      <td>-</td>\n      <td>MPU Region Number Register</td>\n  </tr>\n  <tr>\n      <td>MPU->RBAR</td>\n      <td>MPU_RBAR</td>\n      <td>-</td>\n      <td>MPU Region Base Address Register</td>\n  </tr>\n  <tr>\n      <td>MPU->RASR</td>\n      <td>MPU_RASR</td>\n      <td>-</td>\n      <td>MPU Region Attribute and Size Register</td>\n  </tr>\n  <tr>\n      <td>MPU->RBAR_A1..3</td>\n      <td>MPU_RBAR_A1..3</td>\n      <td>-</td>\n      <td>MPU alias Register</td>\n  </tr>\n  <tr>\n      <td>MPU->RASR_A1..3</td>\n      <td>MPU_RASR_A1..3</td>\n      <td>-</td>\n      <td>MPU alias Register</td>\n  </tr>\n  <tr>\n    <th colspan=\"4\">Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU]</th>\n  </tr>\n  <tr>\n      <td>FPU->FPCCR</td>\n      <td>FPCCR</td>\n      <td>-</td>\n      <td>FP Context Control Register</td>\n  </tr>\n  <tr>\n      <td>FPU->FPCAR</td>\n      <td>FPCAR</td>\n      <td>-</td>\n      <td>FP Context Address Register</td>\n  </tr>\n  <tr>\n      <td>FPU->FPDSCR</td>\n      <td>FPDSCR</td>\n      <td>-</td>\n      <td>FP Default Status Control Register</td>\n  </tr>\n  <tr>\n      <td>FPU->MVFR0..1</td>\n      <td>MVFR0..1</td>\n      <td>-</td>\n      <td>Media and VFP Feature Registers</td>\n  </tr>\n</table>\n*/"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Template.txt",
    "content": "/**\n\\page templates_pg CMSIS-Core Device Templates\n\n\\details\n\nArm supplies CMSIS-Core device template files for the all supported Cortex-M processors and various compiler vendors.\nRefer to the list of \\ref tested_tools_sec for compliance.\n\n\nThese CMSIS-Core device template files include the following:\n - Register names of the Core Peripherals and names of the Core Exception Vectors.\n - Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4 and Cortex-M7)\n - Generic startup code and system configuration code.\n\nThe detailed file structure of the CMSIS-Core device templates is shown in the following picture.\n\n\\image html \"CMSIS_CORE_Files.png\" \"CMSIS-Core File Structure\"\n\n\\section CMSIS_Processor_files CMSIS-Core Processor Files\n\nThe CMSIS-Core processor files provided by Arm are in the directory .\\\\CMSIS\\\\Core\\\\Include. These header files define all processor specific attributes do not need any modifications.\nThe <b>core_&lt;cpu&gt;.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-M processor:\n\n Header File      | Processor\n:-----------      |:---------\ncore_cm0.h        | for the Cortex-M0 processor\ncore_cm0plus.h    | for the Cortex-M0+ processor\ncore_cm3.h        | for the Cortex-M3 processor\ncore_cm4.h        | for the Cortex-M4 processor\ncore_cm7.h        | for the Cortex-M7 processor\n\\if ARMv8M\ncore_cm23.h       | for the Cortex-M23 processor\ncore_cm33.h       | for the Cortex-M33 processor\ncore_cm35p.h      | for the Cortex-M35P processor\ncore_cm55.h       | for the Cortex-M55 processor\ncore_cm85.h       | for the Cortex-M85 processor\n\\endif\n\\if STAR\ncore_starmc1.h    | for the STAR-MC1 processor\n\\endif\n\\if ARMSC\ncore_sc000.h      | for the SecurCore SC000 processor\ncore_sc300.h      | for the SecurCore SC300 processor\n\\endif\n\\if ARMv8M\ncore_armv8mbl.h   | for the Armv8-M Baseline processor\ncore_armv8mml.h   | for the Armv8-M Mainline processor\ncore_armv81mml.h  | for the Armv8.1-M Mainline processor\n\\endif\n\\section device_examples Device Examples\n\nThe CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\\\\Device\\\\ARM\nand include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file <b>ARM.CMSIS.pdsc</b>:\n\n Family            | Device                  | Description\n:------            |:------                  |:-----------\nARM Cortex-M0      | ARMCM0                  | Cortex-M0 based device\nARM Cortex-M0 plus | ARMCM0P                 | Cortex-M0+ based device\nARM Cortex-M3      | ARMCM3                  | Cortex-M3 based device\nARM Cortex-M4      | ARMCM4                  | Cortex-M4 based device without floating-point hardware\nARM Cortex-M4      | ARMCM4_FP               | Cortex-M4 based device with floating-point hardware\nARM Cortex-M7      | ARMCM7                  | Cortex-M4 based device without floating-point hardware\nARM Cortex-M7      | ARMCM7_FP               | Cortex-M7 based device with single precision floating-point unit (FPU)\nARM Cortex-M7      | ARMCM7_DP               | Cortex-M7 based device with double precision floating-point unit\nARM Cortex-M7      | ARMCM7                  | Cortex-M7 based device without floating-point hardware\n\\if ARMv8M\nARM Cortex-M23     | ARMCM23                 | Cortex-M23 based device without TrustZone\nARM Cortex-M23     | ARMCM23_TZ              | Cortex-M23 based device with TrustZone\nARM Cortex-M33     | ARMCM33                 | Cortex-M33 based device without TrustZone, SIMD, FPU\nARM Cortex-M33     | ARMCM33_TZ              | Cortex-M33 based device with TrustZone, no SIMD, no FPU\nARM Cortex-M33     | ARMCM33_DSP_FP          | Cortex-M33 based device with SIMD, FPU, no TrustZone\nARM Cortex-M33     | ARMCM33_DSP_FP_TZ       | Cortex-M33 based device with TrustZone, SIMD, FPU\nARM Cortex-M35P    | ARMCM35P                | Cortex-M35P based device without TrustZone, SIMD, FPU\nARM Cortex-M35P    | ARMCM35P_TZ             | Cortex-M35P based device with TrustZone, no SIMD, no FPU\nARM Cortex-M35P    | ARMCM35P_DSP_FP         | Cortex-M35P based device with SIMD, FPU, no TrustZone\nARM Cortex-M35P    | ARMCM35P_DSP_FP_TZ      | Cortex-M35P based device with TrustZone, SIMD, FPU\nARM Cortex-M55     | ARMCM55                 | Cortex-M55 based device with TrustZone, SIMD, double precision FPU, and floating-point MVE\nARM Cortex-M85     | ARMCM85                 | Cortex-M85 based device with TrustZone, PACBTI, SIMD, double precision FPU, and floating-point MVE\n\\endif\n\\if ARMSC\nARM SC000          | ARM SC000               | SC000 based device\nARM SC300          | ARM SC300               | SC300 based device\n\\endif\n\\if ARMv8M\nARMv8-M Baseline   | ARMv8MBL                | Armv8-M Baseline based device with TrustZone\nARMv8-M Mainline   | ARMv8MML                | Armv8-M Mainline based device with TrustZone\nARMv8-M Mainline   | ARMv8MML_DP             | Armv8-M Mainline based device with TrustZone and double precision FPU\nARMv8-M Mainline   | ARMv8MML_SP             | Armv8-M Mainline based device with TrustZone and single precision FPU\nARMv8-M Mainline   | ARMv8MML_DSP            | Armv8-M Mainline based device with TrustZone and SIMD\nARMv8-M Mainline   | ARMv8MML_DSP_DP         | Armv8-M Mainline based device with TrustZone, SIMD, and double precision FPU\nARMv8-M Mainline   | ARMv8MML_DSP_SP         | Armv8-M Mainline based device with TrustZone, SIMD, and single precision FPU\nARMv8.1-M Mainline | ARMv81MML_DSP_DP_MVE_FP | Armv8.1-M Mainline based device with TrustZone, SIMD, double precision FPU, and floating-point MVE\n\\endif\n\n\\section template_files_sec Template Files\n\nTo simplify the creation of CMSIS-Core device files, the following template files are provided that should be extended by the silicon vendor to reflect the actual device and device peripherals.\nSilicon vendors add to these template files the following information:\n - <b>Device Peripheral Access Layer</b> that provides definitions for device-specific peripherals.\n - <b>Access Functions for Peripherals</b> (optional) that provides additional helper functions to access device-specific peripherals.\n - <b>Interrupt vectors</b> in the startup file that are device specific.\n\n<table class=\"cmtable\">\n    <tr>\n      <th>Template File</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\ARM\\\\startup_Device_ac5_noSct.s</td>\n      <td>Startup file template for Arm Compiler V5. No linker description file necessary.<br>\n          <b>Deprecated</b></td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\ARM\\\\startup_Device_ac5.s</td>\n      <td>Startup file template for Arm Compiler V5. Use of linker description file is <b>necessary</b>.<br>\n          <b>Deprecated</b></td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\ARM\\\\startup_Device_ac6.S</td>\n      <td>Preprocessed startup file template for Arm Compiler V6. Use of linker description file is <b>necessary</b>.<br>\n          <b>Deprecated</b></td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\ARM\\\\Device_ac5.sct</td>\n      <td>Linker description file for Arm Compiler V5.<br>\n          <b>Deprecated</b></td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\ARM\\\\Device_ac6.sct</td>\n      <td>Linker description file for Arm Compiler V6.</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\GCC\\\\startup_Device.S</td>\n      <td>Preprocessed startup file template for GNU GCC Arm Embedded Compiler. Use of linker description file is <b>necessary</b>.<.<br>\n          <b>Deprecated</b></td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\GCC\\\\gcc_arm.ld</td>\n      <td>Linker description file for GNU GCC Arm Embedded Compiler.</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\IAR\\\\startup_Device.s</td>\n      <td>Startup file template for IAR C/C++ Compiler.</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\startup_Device.c</td>\n      <td>Generic startup_Device.c file for device startup implemented in C. Use of linker description file is necessary.</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Source\\\\system_Device.c</td>\n      <td>Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Include\\\\Device.h</td>\n      <td>Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals\n      can be part of that file.</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device\\\\Include\\\\system_Device.h</td>\n      <td>Generic system device configuration include file.</td>\n    </tr>\n</table>\n\n\n<b>Adapt Template Files to a Device</b>\n\nThe following steps describe how to adopt the template files to a specific device or device family.\nCopy the complete all files in the template directory and replace:\n  - directory name 'Vendor' with the abbreviation for the device vendor  e.g.: NXP.\n  - directory name 'Device' with the specific device name e.g.: LPC17xx.\n  - in the file names 'Device' with the specific device name e.g.: LPC17xx.\n\nEach template file contains comments that start with \\b ToDo: that describe a required modification.\nThe template files contain place holders:\n\n<table class=\"cmtable\">\n    <tr>\n      <th>Placeholder</th>\n      <th>Replaced with</th>\n    </tr>\n    <tr>\n      <td>&lt;Device&gt;</td>\n      <td>the specific device name or device family name; i.e. LPC17xx.</td>\n    </tr>\n    <tr>\n      <td>&lt;DeviceInterrupt&gt;</td>\n      <td>a specific interrupt name of the device; i.e. TIM1 for Timer 1.</td>\n    <tr>\n      <td>&lt;DeviceAbbreviation&gt;</td>\n      <td>short name or abbreviation of the device family; i.e. LPC.</td>\n    </tr>\n    <tr>\n      <td>Cortex-M#</td>\n      <td>the specific Cortex-M processor name; i.e. Cortex-M3.</td>\n    </tr>\n</table>\n\n\nThe device configuration of the template files is described in detail on the following pages:\n  - \\subpage startup_c_pg\n  - \\subpage startup_s_pg (deprecated)\n  - \\subpage linker_sct_pg\n  - \\subpage system_c_pg\n  - \\subpage device_h_pg\n\\if ARMv8M\n  - \\subpage partition_h_pg\n  - \\subpage partition_gen_h_pg\n\\endif\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page startup_c_pg Startup File startup_\\<device\\>.c\n\nThe \\ref startup_c_pg contains:\n - The reset handler which is executed after CPU reset and typically calls the \\ref SystemInit function.\n - The setup values for the Main Stack Pointer (MSP).\n - Exception vectors of the Cortex-M Processor with weak functions that implement default routines.\n - Interrupt vectors that are device specific with weak functions that implement default routines.\n\nThe file exists for each supported toolchain and is the only tool-chain specific CMSIS file.\n\nTo adapt the file to a new device only the interrupt vector table needs to be extended with\nthe device-specific interrupt handlers. The naming convention for the interrupt handler names are\n&lt;interrupt_name&gt;_IRQHandler.  This table needs to be consistent with \\ref IRQn_Type that defines all the\nIRQ numbers for each interrupt.\n\n\\b Example:\n\nThe following example shows the extension of the interrupt vector table for the LPC1100 device family.\n\n\\code\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid WAKEUP0_IRQHandler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WAKEUP1_IRQHandler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid WAKEUP2_IRQHandler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n// :\n// :\nvoid EINT1_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid EINT2_IRQHandler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n// :\n// :\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const pFunc __VECTOR_TABLE[240];\n       const pFunc __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (pFunc)(&__INITIAL_SP),                   /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  WAKEUP0_IRQHandler,                       /*   0 Wakeup PIO0.0 */\n  WAKEUP1_IRQHandler,                       /*   1 Wakeup PIO0.1 */\n  WAKEUP2_IRQHandler,                       /*   2 Wakeup PIO0.2 */\n  // :\n  // :\n  EINT1_IRQHandler,                         /*  30 PIO INT1 */\n  EINT2_IRQHandler,                         /*  31 PIO INT2 */\n  // :\n  // :\n};\n\\endcode\n\n\\section startup_c_sec startup_Device.c Template File\n\nA compiler agnostic \\ref startup_c_sec for an Armv7-M processor like Cortex-M3 is shown below.\nThe C startup file relys on certain compiler specific preprocessor defines specified in CMSIS compiler headers:\n - \\ref __INITIAL_SP\n - \\ref __STACK_LIMIT\n - \\ref __PROGRAM_START\n - \\ref __VECTOR_TABLE\n - \\ref __VECTOR_TABLE_ATTRIBUTE\n\n\\verbinclude \"Source/startup_Device.c\"\n\\section startup_c_sec_v8 startup_Device.c Template File (Armv8-M/v8.1-M)\n\nThe C-startup file for an Armv8-M/v8.1-M processor is similar to the one for an Armv7-M processor\nexcept that it offers the possibility of stack sealing for the Main Stack Pointer (MSP).\nThe following preprocessor defines and CMSIS functions are used:\n - \\ref __STACK_SEAL\n - \\ref __TZ_set_STACKSEAL_S\n\nThe stack sealing and the initialization fof the Stack Limit register is done in function <b>void Reset_Handler(void)</b>:\n\n\\code\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\\endcode\n\n\\note Stack Sealing also requires the application project to use a scatter file (or a linker script) as explained in \\ref RTOS_TrustZone_stacksealing section.\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page startup_s_pg Startup File startup_\\<device\\>.s (deprecated)\n\nThe \\ref startup_s_pg contains:\n - The reset handler which is executed after CPU reset and typically calls the \\ref SystemInit function.\n - The setup values for the Main Stack Pointer (MSP).\n - Exception vectors of the Cortex-M Processor with weak functions that implement default routines.\n - Interrupt vectors that are device specific with weak functions that implement default routines.\n\nThe file exists for each supported toolchain and is the only tool-chain specific CMSIS file.\n\nTo adapt the file to a new device only the interrupt vector table needs to be extended with\nthe device-specific interrupt handlers. The naming convention for the interrupt handler names are\n&lt;interrupt_name&gt;_IRQHandler.  This table needs to be consistent with \\ref IRQn_Type that defines all the\nIRQ numbers for each interrupt.\n\n\\b Example:\n\nThe following example shows the extension of the interrupt vector table for the LPC1100 device family.\n\n\\code\n                ; External Interrupts\n                DCD     WAKEUP0_IRQHandler       ; 16+ 0: Wakeup PIO0.0\n                DCD     WAKEUP1_IRQHandler       ; 16+ 1: Wakeup PIO0.1\n                DCD     WAKEUP2_IRQHandler       ; 16+ 2: Wakeup PIO0.2\n                 :       :\n                 :       :\n                DCD     EINT1_IRQHandler         ; 16+30: PIO INT1\n                DCD     EINT0_IRQHandler         ; 16+31: PIO INT0\n   :\n   :\n                EXPORT  WAKEUP0_IRQHandler       [WEAK]\n                EXPORT  WAKEUP1_IRQHandler       [WEAK]\n                EXPORT  WAKEUP2_IRQHandler       [WEAK]\n                 :       :\n                 :       :\n                EXPORT  EINT1_IRQHandler         [WEAK]\n                EXPORT  EINT0_IRQHandler         [WEAK]\n\nWAKEUP0_IRQHandler\nWAKEUP1_IRQHandler\nWAKEUP1_IRQHandler\n      :\n      :\nEINT1_IRQHandler\nEINT0_IRQHandler\n                B       .\n\n\\endcode\n\n\\section startup_s_sec startup_Device.S Template File\n\nAn Arm Compiler V6 assembler \\ref startup_s_sec for an Armv8-M processor like Cortex-M33 is shown below.\nThe files for other compiler vendors differ slightly in the syntax, but not in the overall structure.\n\n\\verbinclude \"Source/ARM/startup_Device_ac6.S\"\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page linker_sct_pg Scatter-Loading description file \\<device\\>_ac<5|6>.sct\n\nA scatter file for linking is required when using a \\ref startup_c_pg \"C startup file\".\n\nThe \\ref linker_sct_pg contains regions for:\n - Code (read-only data, execute-only data)\n - RAM (read/write data, zero-initialized data)\n - Stack\n - Heap\n - Stack seal (Armv8-M/v8.1-M)\n - CMSE veneer (Armv8-M/v8.1-M)\n\nWithin the scatter file, the user needs to specify a set of macros. The scatter file is passed through the\nC preprocessor which uses these macros to calculate the start address and the size of the different regions.\n\n\\code\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\\endcode\n\n\\note\nThe stack is placed at the end of the available RAM and is growing downwards \nwhereas the Heap is placed after the application data and growing upwards.\n\n\\section linker_sct_preproc_sec Preprocessor command\nThe scatter file uses different preprocessor commands for Arm Compiler V6 and Arm Compiler V5\n - \\b AC6: #! armclang -E --target=arm-arm-none-eabi -mcpu=&lt;mcpu&gt; -xc\n - \\b AC5: #! armcc -E\n\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page system_c_pg System Configuration Files system_<device>.c and system_<device>.h\n\nThe \\ref system_c_pg provides as a minimum the functions described under \\ref system_init_gr.\nThese functions are device specific and need adaptations. In addition, the file might have\nconfiguration settings for the device such as XTAL frequency or PLL prescaler settings.\n\nFor devices with external memory BUS the system_<device>.c also configures the BUS system.\n\nThe silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file.\nIn case of additional features the function prototypes need to be added to the system_<device>.h header file.\n\n\\section system_Device_sec system_Device.c Template File\n\nThe \\ref system_Device_sec for the Cortex-M3 is shown below.\n\n\\verbinclude \"Source/system_Device.c\"\n\n\\section system_Device_h_sec system_Device.h Template File\n\nThe system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file.\nThe \\ref system_Device_h_sec is shown below.\n\n\\verbinclude \"Include/system_Device.h\"\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page device_h_pg Device Header File <device.h>\n\nThe \\ref device_h_pg contains the following sections that are device specific:\n\n  - \\ref interrupt_number_sec provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.\n  - \\ref core_config_sect reflect the features of the device.\n  - \\ref device_access provides definitions for the \\ref peripheral_gr to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.\n  - <b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.\n\n<a href=\"modules.html\">\\b Reference </a> describes the standard features and functions of the \\ref device_h_pg in detail.\n\n\\section interrupt_number_sec Interrupt Number Definition\n\n\\ref device_h_pg contains the enumeration \\ref IRQn_Type that defines all exceptions and interrupts of the device.\n  - Negative IRQn values represent processor core exceptions (internal interrupts).\n  - Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0.\n    The IRQn values needs extension to reflect the device-specific interrupt vector table in the \\ref startup_s_pg.\n\n\\b Example:\n\nThe following example shows the extension of the interrupt vector table for the LPC1100 device family.\n\n\\code\ntypedef enum IRQn\n{\n/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/\n  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */\n  HardFault_IRQn                = -13,      /*!< 3 Cortex-M0 Hard Fault Interrupt                 */\n  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M0 SVC Interrupt                       */\n  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M0 PendSV Interrupt                    */\n  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M0 System Tick Interrupt               */\n\n/******  LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/\n  WAKEUP0_IRQn                  = 0,        /*!< All I/O pins can be used as wakeup source.       */\n  WAKEUP1_IRQn                  = 1,        /*!< There are 13 pins in total for LPC11xx           */\n  WAKEUP2_IRQn                  = 2,\n                 :       :\n                 :       :\n  EINT1_IRQn                    = 30,       /*!< External Interrupt 1 Interrupt                   */\n  EINT0_IRQn                    = 31,       /*!< External Interrupt 0 Interrupt                   */\n} IRQn_Type;\n\\endcode\n\n\\section core_config_sect Configuration of the Processor and Core Peripherals\n\nThe \\ref device_h_pg  configures the Cortex-M or SecurCore processor and the core peripherals with <i>\\#defines</i>\nthat are set prior to including the file <b>core_<cpu>.h</b>.\n\nThe following tables list the <i>\\#defines</i> along with the possible values for each processor core.\nIf these <i>\\#defines</i> are missing default values are used.\n\\b core_cm0.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __CM0_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2</td>\n      <td>2</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\n\\b core_cm0plus.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __CM0PLUS_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2</td>\n      <td>2</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\n\\b core_cm3.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __CM3_REV</td>\n      <td>0x0101 | 0x0200</td>\n      <td>0x0200</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2 .. 8</td>\n      <td>4</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __MPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a MPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\n\\b core_cm4.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __CM4_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2 .. 8</td>\n      <td>4</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __MPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a MPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __FPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a FPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\n\\b core_cm7.h\n<table class=\"cmtable\" summary=\"\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __CM7_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __MPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a MPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2 .. 8</td>\n      <td>4</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>\n        If this define is set to 1, then the default <b>SysTick_Config</b> function\n        is excluded. In this case, the file <i><b>device.h</b></i>\n        must contain a vendor specific implementation of this function.\n      </td>\n    </tr>\n    <tr>\n      <td>\\ref __FPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a FPU is present or not.</td>\n    </tr>\n    <tr>\n      <td>\\ref __FPU_DP</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>\n        The combination of the defines \\ref __FPU_PRESENT and \\ref __FPU_DP\n       determine whether the FPU is with single or double precision.\n      </td>\n    </tr>\n    <tr>\n      <td>\\ref __ICACHE_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Instruction Chache present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __DCACHE_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Data Chache present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __DTCM_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Data Tightly Coupled Memory is present or not</td>\n    </tr>\n</table>\n\n\\if ARMSC\n\\b core_sc000.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __SC000_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2</td>\n      <td>2</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __MPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a MPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\\endif\n\n\\if ARMSC\n\\b core_sc300.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __SC300_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2 .. 8</td>\n      <td>4</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __MPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a MPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\\endif\n\n\\if ARMv8M\n\\b core_CM23.h or \\b core_ARMv8MBL.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __ARMv8MBL_REV or \\ref __CM23_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __MPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a MPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __SAUREGION_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if SAU regions are present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2</td>\n      <td>2</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\\endif\n\n\\if ARMv8M\n\\b core_CM33.h or \\b core_cm35p.h or \\b core_ARMv8MML.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __ARMv8MML_REV or \\ref __CM33_REV or \\ref __CM35P_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __MPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a MPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __SAUREGION_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if SAU regions are present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __FPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a FPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2 .. 8</td>\n      <td>3</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\\endif\n\n\\if ARMv8M\n\\b core_CM55.h or \\b core_ARMv81MML.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __ARMv81MML_REV or \\ref __CM55_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __MPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a MPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __SAUREGION_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if SAU regions are present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __FPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a FPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __FPU_DP</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>\n        The combination of the defines \\ref __FPU_PRESENT and \\ref __FPU_DP determine\n        whether the FPU is with single or double precision.\n      </td>\n    </tr>\n    <tr>\n      <td>\\ref __ICACHE_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Instruction Chache present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __DCACHE_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Data Chache present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2 .. 8</td>\n      <td>3</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\\endif\n\n\\if ARMv8M\n\\b core_CM85.h\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\\ref __CM85_REV</td>\n      <td>0x0001</td>\n      <td>0x0001</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>\\ref __MPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a MPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __SAUREGION_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if SAU regions are present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __FPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a FPU is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __FPU_DP</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>\n        The combination of the defines \\ref __FPU_PRESENT and \\ref __FPU_DP determine\n        whether the FPU is with single or double precision.\n      </td>\n    </tr>\n    <tr>\n      <td>\\ref __ICACHE_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Instruction Chache present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __DCACHE_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Data Chache present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __VTOR_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Defines if a VTOR register is present or not</td>\n    </tr>\n    <tr>\n      <td>\\ref __NVIC_PRIO_BITS</td>\n      <td>2 .. 8</td>\n      <td>3</td>\n      <td>Number of priority bits implemented in the NVIC (device specific)</td>\n    </tr>\n    <tr>\n      <td>\\ref __Vendor_SysTickConfig</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Vendor defined <b>SysTick_Config</b> function.</td>\n    </tr>\n</table>\n\\endif\n\n\\b Example\n\nThe following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.\n\n\\code\n#define __CM4_REV                 0x0001U   /* Core revision r0p1                                 */\n#define __MPU_PRESENT             1U        /* MPU present or not                                 */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels            */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used       */\n#define __FPU_PRESENT             1U        /* FPU present or not                                 */\n.\n.\n#include <core_cm4.h>                       /* Cortex-M4 processor and core peripherals           */\n#include \"system_<device>.h\"                /* Device System Header                               */\n\\endcode\n\n\n\\section core_version_sect   CMSIS Version and Processor Information\n\nDefines in the core_<i>cpu</i>.h file identify the version of the CMSIS-Core (Cortex-M) and the processor used.\nThe following shows the defines in the various core_<i>cpu</i>.h files that may be used in the \\ref device_h_pg\nto verify a minimum version or ensure that the right processor core is used.\n\n\\b core_cm0.h\n\\code\n#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         /* [31:16] CMSIS HAL main version */\n#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          /* [15:0]  CMSIS HAL sub version */\n#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM0_CMSIS_VERSION_SUB          )              /* CMSIS HAL version number */\n\n#define __CORTEX_M                (0U)                                              /* Cortex-M Core */\n\\endcode\n\n\n\\b core_cm0plus.h\n\\code\n#define __CM0PLUS_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                     /* [31:16] CMSIS HAL main version */\n#define __CM0PLUS_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                      /* [15:0]  CMSIS HAL sub version */\n#define __CM0PLUS_CMSIS_VERSION       ((__CM0P_CMSIS_VERSION_MAIN << 16U) | \\\n                                        __CM0P_CMSIS_VERSION_SUB          )         /* CMSIS HAL version number */\n\n#define __CORTEX_M                    (0U)                                          /* Cortex-M Core */\n\\endcode\n\n\n\\b core_cm1.h\n\\code\n#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM1_CMSIS_VERSION_SUB           )             /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (1U)                                              /*!< Cortex-M Core */\n\\endcode\n\n\\b core_cm3.h\n\\code\n#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         /* [31:16] CMSIS HAL main version */\n#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          /* [15:0]  CMSIS HAL sub version */\n#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM3_CMSIS_VERSION_SUB          )              /* CMSIS HAL version number */\n\n#define __CORTEX_M                (3U)                                              /* Cortex-M Core */\n\\endcode\n\n\\b core_cm4.h\n\\code\n#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                         /* [31:16] CMSIS HAL main version */\n#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          /* [15:0]  CMSIS HAL sub version */\n#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM4_CMSIS_VERSION_SUB          )              /* CMSIS HAL version number */\n\n#define __CORTEX_M                (4U)                                              /* Cortex-M Core */\n\\endcode\n\n\\b core_cm7.h\n\\code\n#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN                          /* [31:16] CMSIS HAL main version */\n#define __CM7_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                          /* [15:0]  CMSIS HAL sub version */\n#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM7_CMSIS_VERSION_SUB          )              /* CMSIS HAL version number */\n\n#define __CORTEX_M                (7U)                                              /* Cortex-M Core */\n\\endcode\n\n\\if ARMv8M\n\\b core_cm23.h\n\\code\n#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                        /* [31:16] CMSIS HAL main version */\n#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                         /* [15:0]  CMSIS HAL sub version */\n#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM23_CMSIS_VERSION_SUB          )            /* CMSIS HAL version number */\n\n#define __CORTEX_M                (23U)                                             /* Cortex-M Core */\n\\endcode\n\n\\b core_cm33.h\n\\code\n#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                        /* [31:16] CMSIS HAL main version */\n#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                         /* [15:0]  CMSIS HAL sub version */\n#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM33_CMSIS_VERSION_SUB          )            /* CMSIS HAL version number */\n\n#define __CORTEX_M                (33U)                                             /* Cortex-M Core */\n\\endcode\n\n\\b core_cm55.h\n\\code\n#define __CM55_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                        /* [31:16] CMSIS HAL main version */\n#define __CM55_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                         /* [15:0]  CMSIS HAL sub version */\n#define __CM55_CMSIS_VERSION       ((__CM55_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM55_CMSIS_VERSION_SUB          )            /* CMSIS HAL version number */\n\n#define __CORTEX_M                (7U)                                              /* Cortex-M Core */\n\\endcode\n\\endif\n\n\\if ARMSC\n\\b core_sc000.h\n\\code\n#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                       /* [31:16] CMSIS HAL main version */\n#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                        /* [15:0]  CMSIS HAL sub version */\n#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC000_CMSIS_VERSION_SUB          )          /* CMSIS HAL version number */\n\n#define __CORTEX_SC                 (0U)                                            /* Cortex secure core */\n\\endcode\n\\endif\n\n\\if ARMSC\n\\b core_sc300.h\n\\code\n#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                       /* [31:16] CMSIS HAL main version */\n#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                        /* [15:0]  CMSIS HAL sub version */\n#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC300_CMSIS_VERSION_SUB          )          /* CMSIS HAL version number */\n\n#define __CORTEX_SC                 (300U)                                          /* Cortex secure core */\n\\endcode\n\\endif\n\n\\if ARMv8M\n\\if ARMSC\n\\b core_cm35p.h\n\\code\n#define __CM35P_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                       /* [31:16] CMSIS HAL main version */\n#define __CM35P_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                        /* [15:0]  CMSIS HAL sub version */\n#define __CM35P_CMSIS_VERSION       ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __CM35P_CMSIS_VERSION_SUB          )          /* CMSIS HAL version number */\n\n#define __CORTEX_M                (35U)                                             /* Cortex-M Core */\n\\endcode\n\\endif\n\\endif\n\n\\if ARMv8M\n\\b core_ARMv8MBL.h\n\\code\n#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                    /* [31:16] CMSIS HAL main version */\n#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                     /* [15:0]  CMSIS HAL sub version */\n#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MBL_CMSIS_VERSION_SUB           )   /* CMSIS HAL version number */\n\n#define __CORTEX_M                     (2U)                                         /* Cortex secure core */\n\\endcode\n\\endif\n\n\\if ARMv8M\n\\b core_ARMv8MML.h\n\\code\n#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                    /* [31:16] CMSIS HAL main version */\n#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                     /* [15:0]  CMSIS HAL sub version */\n#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MML_CMSIS_VERSION_SUB           )   /* CMSIS HAL version number */\n\n#define __CORTEX_M                     (80U)                                        /* Cortex secure core */\n\\endcode\n\\endif\n\n\\if ARMv81M\n\\b core_ARMv81MML.h\n\\code\n#define __ARMv81MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /* [31:16] CMSIS HAL main version */\n#define __ARMv81MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /* [15:0]  CMSIS HAL sub version */\n#define __ARMv81MML_CMSIS_VERSION       ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \\\n                                          __ARMv81MML_CMSIS_VERSION_SUB           ) /* CMSIS HAL version number */\n\n#define __CORTEX_M                     (81U)                                        /* Cortex secure core */\n\\endcode\n\\endif\n\n\\section device_access Device Peripheral Access Layer\n\nThe \\ref device_h_pg contains for each peripheral:\n - Register Layout Typedef\n - Base Address\n - Access Definitions\n\nThe section \\ref peripheral_gr shows examples for peripheral definitions.\n\n\\section device_h_sec Device.h Template File\n\nThe silicon vendor needs to extend the Device.h template file with the CMSIS features described above.\nIn addition the \\ref device_h_pg may contain functions to access device-specific peripherals.\nThe \\ref system_Device_h_sec which is provided as part of the CMSIS specification is shown below.\n\n\\verbinclude \"Include/Device.h\"\n\n*/\n\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\if ARMv8M\n\n\\page partition_h_pg TrustZone setup: partition_<device>.h\n\nThe \\ref partition_h_pg header file contains the initial setup of the TrustZone hardware in an Armv8-M system.\n\nThis file implements the function \\ref TZ_SAU_Setup that is call from \\ref SystemInit. It uses settings in these files:\n\n - \\ref partition_h_pg \"partition_<device>.h\" that defines the initial system configuration and during SystemInit in Secure state.\n - \\ref partition_gen_h_pg \"partition_gen.h\" that contains SAU region and interrupt target assignments. This file may be generated using <a href=\"../../Zone/html/index.html\"><b>CMSIS-Zone</b></a>.\n\n\\note\n\\ref partition_gen_h_pg \"partition_gen.h\" is optional and can be generated using <a href=\"../../Zone/html/index.html\"><b>CMSIS-Zone</b></a>.  In previous versions of CMSIS-Core(M) this settings were part of \\ref partition_h_pg \"partition_<device>.h\".\n\n&nbsp;\n\n\nThe \\ref partition_h_pg \"partition_<device>.h\" file contains the following configuration settings for:\n  - \\ref sau_ctrlregister_sec provides settings for the SAU CTRL register.\n  - \\ref sau_sleepexception_sec provides device-specific deep-sleep and exception settings.\n  - \\ref sau_fpu_sec defines the usage of the Floating Point Unit in secure and non-secure state.\n\nThe \\ref partition_h_pg \"partition_<device>.h\" file includes the \\ref partition_gen_h_pg \"partition_gen.h\" file with configuration settings for:\n  - \\ref sau_regions_sect provides configuration of the SAU Address Regions.\n  - \\ref sau_interrupttarget_sec provides device-specific interrupt target settings.\n\n\\section sau_ctrlregister_sec  SAU CTRL register settings\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>SAU_INIT_CTRL</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Initialize SAU CTRL register or not\n           - 0: do not initialize SAU CTRL register\n           - 1: initialize SAU CTRL register</td>\n    </tr>\n    <tr>\n      <td>SAU_INIT_CTRL_ENABLE</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>enable/disable the SAU\n           - 0: disable SAU\n           - 1: enable SAU</td>\n    </tr>\n    <tr>\n      <td>SAU_INIT_CTRL_ALLNS</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>value for SAU_CTRL register bit ALLNS\n           - 0: all Memory is Secure\n           - 1: all Memory is Non-Secure</td>\n    </tr>\n</table>\n\n\n\\section sau_sleepexception_sec  Configuration of Sleep and Exception behaviour\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>SCB_CSR_AIRCR_INIT</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Setup behaviour of Sleep and Exception Handling\n           - 0: not setup of CSR and AIRCR registers; the values below are not relevant\n           - 1: setup of CSR and AIRCR registers with values below</td>\n    </tr>\n    <tr>\n      <td>CSR_INIT_DEEPSLEEPS_VAL</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>value for SCB_CSR register bit DEEPSLEEPS\n           - 0: Deep Sleep can be enabled by Secure and Non-Secure state\n           - 1: Deep Sleep can be enabled by Secure state only</td>\n    </tr>\n    <tr>\n      <td>AIRCR_INIT_SYSRESETREQS_VAL</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>value for SCB_AIRCR register bit SYSRESETREQS\n           - 0: System reset request accessible from Secure and Non-Secure state\n           - 1: System reset request accessible from Secure state only</td>\n    </tr>\n    <tr>\n      <td>AIRCR_INIT_PRIS_VAL</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>value for SCB_AIRCR register bit PRIS\n           - 0: Priority of Non-Secure exceptions is Not altered\n           - 1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF</td>\n    </tr>\n    <tr>\n      <td>AIRCR_INIT_BFHFNMINS_VAL</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>value for SCB_AIRCR register bit BFHFNMINS\n           - 0: BusFault, HardFault, and NMI target are Secure state\n           - 1: BusFault, HardFault, and NMI target are Non-Secure state</td>\n    </tr>\n</table>\n\n\n\\section sau_fpu_sec  Configuration of Floating Point Unit\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>TZ_FPU_NS_USAGE</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Setup behaviour of Floating Point Unit\n           - 0: not setup of NSACR and FPCCR registers; the values below are not relevant\n           - 1: setup of NSACR and FPCCR registers with values below</td>\n    </tr>\n    <tr>\n      <td>SCB_NSACR_CP10_11_VAL</td>\n      <td>0 or 3</td>\n      <td>3</td>\n      <td>Floating Point Unit usage (Value for SCB->NSACR register bits CP10, CP11)\n           - 0: Secure state only\n           - 3: Secure and Non-Secure state</td>\n    </tr>\n    <tr>\n      <td>FPU_FPCCR_TS_VAL</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Treat floating-point registers as Secure (value for FPU->FPCCR register bit TS)\n           - 0: Disable\n           - 1: Enabled</td>\n    </tr>\n    <tr>\n      <td>FPU_FPCCR_CLRONRETS_VAL</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Clear on return (CLRONRET) accessibility (Value for FPU->FPCCR register bit CLRONRETS)\n           - 0: Secure and Non-Secure state\n           - 1: Secure state only</td>\n    </tr>\n    <tr>\n      <td>FPU_FPCCR_CLRONRET_VAL</td>\n      <td>0 .. 1</td>\n      <td>1</td>\n      <td>Clear floating-point caller saved registers on exception return (Value for FPU->FPCCR register bit CLRONRET)\n           - 0: Disabled\n           - 1: Enabled</td>\n    </tr>\n</table>\n\n&nbsp;\n\n----\n\n\\section partition_gen_h_pg Region/ISR setup: partition_gen.h\n\nThe \\ref partition_gen_h_pg \"partition_gen.h\" header file can be generated using <a href=\"../../Zone/html/index.html\"><b>CMSIS-Zone</b></a>.\n\nThe \\ref partition_h_pg \"partition_<device>.h\" file includes the \\ref partition_h_pg \"partition_gen.h\" file with configuration settings for:\n  - \\ref sau_regions_sect provides configuration of the SAU Address Regions.\n  - \\ref sau_interrupttarget_sec provides device-specific interrupt target settings.\n\n\\note\nIn previous versions of CMSIS-Core(M) the above settings were part of \\ref partition_h_pg \"partition_<device>.h\"\n\n\\subsection sau_regions_sect  Configuration of the SAU Address Regions\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>SAU_REGIONS_MAX</td>\n      <td>0 .. tbd</td>\n      <td>8</td>\n      <td>maximum number of SAU regions</td>\n    </tr>\n    <tr>\n      <td>SAU_INIT_REGION<number></td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>initialize SAU region or not\n           - 0: do not initialize SAU region\n           - 1: initialize SAU region</td>\n    </tr>\n    <tr>\n      <td>SAU_INIT_START<number></td>\n      <td>0x00000000 .. 0xFFFFFFE0\\n\n          [in steps of 32]</td>\n      <td>0x00000000</td>\n      <td>region start address</td>\n    </tr>\n    <tr>\n      <td>SAU_INIT_END<number></td>\n      <td>0x00000000 .. 0xFFFFFFE0\\n\n          [in steps of 32]</td>\n      <td>0x00000000</td>\n      <td>region start address</td>\n    </tr>\n    <tr>\n      <td>SAU_INIT_NSC<number></td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>SAU region attribute\n           - 0: Non-Secure\n           - 1: Secure, Non-Secure callable</td>\n    </tr>\n</table>\n\nThe range of \\<number\\> is from 0 .. SAU_REGIONS_MAX.\nA set of these macros must exist for each \\<number\\>.\n\nThe following example shows a set of SAU region macros.\n\n\\code\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n#define SAU_INIT_REGION0    1\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n#define SAU_INIT_END0       0x001FFFE0      /* end address of SAU region 0 */\n#define SAU_INIT_NSC0       1\n\n#define SAU_INIT_REGION1    1\n#define SAU_INIT_START1     0x00200000      /* start address of SAU region 1 */\n#define SAU_INIT_END1       0x003FFFE0      /* end address of SAU region 1 */\n#define SAU_INIT_NSC1       0\n\n#define SAU_INIT_REGION2    1\n#define SAU_INIT_START2     0x20200000      /* start address of SAU region 2 */\n#define SAU_INIT_END2       0x203FFFE0      /* end address of SAU region 2 */\n#define SAU_INIT_NSC2       0\n\n#define SAU_INIT_REGION3    1\n#define SAU_INIT_START3     0x40000000      /* start address of SAU region 3 */\n#define SAU_INIT_END3       0x40040000      /* end address of SAU region 3 */\n#define SAU_INIT_NSC3       0\n\n#define SAU_INIT_REGION4    0\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n#define SAU_INIT_NSC4       0\n\n#define SAU_INIT_REGION5    0\n#define SAU_INIT_START5     0x00000000      /* start address of SAU region 5 */\n#define SAU_INIT_END5       0x00000000      /* end address of SAU region 5 */\n#define SAU_INIT_NSC5       0\n\n#define SAU_INIT_REGION6    0\n#define SAU_INIT_START6     0x00000000      /* start address of SAU region 6 */\n#define SAU_INIT_END6       0x00000000      /* end address of SAU region 6 */\n#define SAU_INIT_NSC6       0\n\n#define SAU_INIT_REGION7    0\n#define SAU_INIT_START7     0x00000000      /* start address of SAU region 7 */\n#define SAU_INIT_END7       0x00000000      /* end address of SAU region 7 */\n#define SAU_INIT_NSC7       0\n\\endcode\n\n\n\\subsection sau_interrupttarget_sec Configuration of Interrupt Target settings\n\nEach interrupt has a configuration bit that defines the execution\nin Secure or Non-secure state. The Non-Secure interrupts have a separate\nvector table.  Refer to \\ref Model_TrustZone for more information.\n\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>NVIC_INIT_ITNS<number></td>\n      <td>0x00000000 .. 0xFFFFFFFF\\n\n          [each bit represents an interrupt]</td>\n      <td>0x00000000</td>\n      <td>Interrupt vector target\n           - 0: Secure state\n           - 1: Non-Secure state</td>\n    </tr>\n</table>\n\nThe range of \\<number\\> is 0 .. (\\<number of external interrupts\\> + 31) / 32.\n\nThe following example shows the configuration for a maximum of 64 external interrupts.\n\n\\code\n#define NVIC_INIT_ITNS0      0x0000122B\n#define NVIC_INIT_ITNS1      0x0000003A\n\\endcode\n\n\\endif\n\n*/\n\n/**\n\\defgroup device_config Device capabilitiy defines\n\\brief Defines to configure and check device capabilities.\n\\details\nThese defines are used by the \\ref device_h_pg in order to enable or disable\nfunctionality provided by CMSIS-Core(M) dependent on the device capabilities.\n\n@{\n*/\n\n#define __CM0_REV                     /*!< \\brief Cortex-M0 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM0PLUS_REV                 /*!< \\brief Cortex-M0+ Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM1_REV                     /*!< \\brief Cortex-M1 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM3_REV                     /*!< \\brief Cortex-M3 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM4_REV                     /*!< \\brief Cortex-M4 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM7_REV                     /*!< \\brief Cortex-M7 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __SC000_REV                   /*!< \\brief SC000 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __SC300_REV                   /*!< \\brief SC300 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM23_REV                    /*!< \\brief Cortex-M23 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM33_REV                    /*!< \\brief Cortex-M33 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM35P_REV                   /*!< \\brief Cortex-M35P Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM55_REV                    /*!< \\brief Cortex-M55 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __CM85_REV                    /*!< \\brief Cortex-M85 Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __ARMv8MBL_REV                /*!< \\brief Armv8-M Baseline device Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __ARMv8MML_REV                /*!< \\brief Armv8-M Mainline device Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __ARMv81MML_REV               /*!< \\brief Armv8.1-M Baseline device Core revision r0p1 \\details ([15:8] revision number, [7:0] patch number) */\n#define __NVIC_PRIO_BITS              /*!< \\brief Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig        /*!< \\brief Set to 1 if a venor specfic SysTick configuration is used.\n                                           \\details If this define is set to 1, then the default \\ref SysTick_Config function is excluded. In this\n                                                    case, the file device.h must contain a vendor specific implementation of this function. */\n#define __VTOR_PRESENT                /*!< \\brief VTOR present or not \\details See \\ref SCB_Type::VTOR */\n#define __MPU_PRESENT                 /*!< \\brief MPU present or not */\n\n/**\n  \\brief FPU present or not\n  \\details\n  The combination of the defines \\ref __FPU_PRESENT and \\ref __FPU_DP\n  determine the whether the FPU is with single or double precision as shown\n  in the table below.\n  <table class=\"cmtable\" summary=\"\">\n    <tr bgcolor=\"cyan\">\n      <td>\\ref __FPU_PRESENT</td>\n      <td>\\ref __FPU_DP</td>\n      <td><b>Description</b></td>\n    </tr>\n    <tr>\n      <td align=\"center\">0</td>\n      <td align=\"center\"><i>ignored</i></td>\n      <td>Processor has no FPU. The value set for \\ref __FPU_DP.</td>\n    </tr>\n    <tr>\n      <td align=\"center\">1</td>\n      <td align=\"center\">0</td>\n      <td>Processor with FPU with single precision.</td>\n    </tr>\n    <tr>\n      <td align=\"center\">1</td>\n      <td align=\"center\">1</td>\n      <td>Processor with FPU with double precision.</td>\n    </tr>\n  </table>\n*/\n#define __FPU_PRESENT               /*!< \\brief FPU present \\details The */\n\n/**\n  \\brief Double precision FPU present\n  \\details\n  The combination of the defines \\ref __FPU_PRESENT and \\ref __FPU_DP\n  determine the whether the FPU is with single or double precision as shown\n  in the table below.\n  <table class=\"cmtable\" summary=\"\">\n    <tr bgcolor=\"cyan\">\n      <td>\\ref __FPU_PRESENT</td>\n      <td>\\ref __FPU_DP</td>\n      <td><b>Description</b></td>\n    </tr>\n    <tr>\n      <td align=\"center\">0</td>\n      <td align=\"center\"><i>ignored</i></td>\n      <td>Processor has no FPU. The value set for \\ref __FPU_DP. </td>\n    </tr>\n    <tr>\n      <td align=\"center\">1</td>\n      <td align=\"center\">0</td>\n      <td>Processor with FPU with single precision.</td>\n    </tr>\n    <tr>\n      <td align=\"center\">1</td>\n      <td align=\"center\">1</td>\n      <td>Processor with FPU with double precision.</td>\n    </tr>\n  </table>\n*/\n#define __FPU_DP\n\n#define __DSP_PRESENT               /*!< \\brief DSP extension present or not */\n#define __SAUREGION_PRESENT         /*!< \\brief SAU regions present or not */\n#define __PMU_PRESENT               /*!< \\brief PMU present or not */\n#define __PMU_NUM_EVENTCNT          /*!< \\brief PMU Event Counters \\details The number of Event counters if PMU is present (see \\ref __PMU_PRESENT) */\n#define __ICACHE_PRESENT            /*!< \\brief Instruction Cache present or not */\n#define __DCACHE_PRESENT            /*!< \\brief Data Cache present or not */\n#define __DTCM_PRESENT              /*!< \\brief Data Tightly Coupled Memory is present or not */\n/** @} */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/Using.txt",
    "content": "/** \n\\page using_pg  Using CMSIS in Embedded Applications\n\n\\details\n\nTo use the CMSIS-Core (Cortex-M) the following files are added to the embedded application:\n - \\ref startup_c_pg (formerly \\ref startup_s_pg) with reset handler and exception vectors.\n - \\ref system_c_pg with general device configuration (i.e. for clock and BUS setup).\n - \\ref device_h_pg gives access to processor core and all peripherals.\n\n\\note The files \\ref startup_c_pg (or \\ref startup_s_pg) and \\ref system_c_pg may require application specific adaptations and therefore should be copied \n  into the application project folder prior configuration. The \\ref device_h_pg is included in all source files that need device access \n  and can be stored on a central include folder that is generic for all projects.\n\nThe \\ref startup_c_pg (or \\ref startup_s_pg) is executed after reset and calls \\ref SystemInit. After the system initialization control is transferred to the C/C++ run-time\nlibrary which performs initialization and calls the \\b main function in the user code. In addition the \\ref startup_c_pg (or \\ref startup_s_pg) contains all exception and\ninterrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.\n\nThe \\ref system_c_pg performs the setup for the processor clock. The variable \\ref SystemCoreClock indicates the CPU clock speed.\n\\ref system_init_gr describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration. \n\nThe \\ref device_h_pg is the central include file that the application programmer is using in the C source code.  It provides the following features:\n - \\ref peripheral_gr provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.\n - \\ref NVIC_gr can be accessed with standardized symbols and functions for the Nested Interrupt Vector Controller (NVIC) are provided.\n - \\ref intrinsic_CPU_gr allow to access special instructions, for example for activating sleep mode or the NOP instruction.\n - \\ref intrinsic_SIMD_gr provide access to the DSP-oriented instructions.\n - \\ref SysTick_gr function to configure and start a periodic timer interrupt.\n - \\ref ITM_Debug_gr are functions that allow printf-style I/O via the CoreSight Debug Unit and ITM communication.\n\nCMSIS-Pack provides the <b>\\#define CMSIS_header_file</b> in <a href=\"../../Pack/html/pdsc_components_pg.html#RTE_Components_h\"><b>RTE_Components.h</b></a> which gives you access to this <b><i>device</i>.h</b> file.\n\n\\image html \"CMSIS_CORE_Files_USER.png\" \"CMSIS-Core (Cortex-M) User Files\"\n\nThe CMSIS-Core (Cortex-M) system files are device specific. In addition, the deprecated \\ref startup_s_pg is also compiler vendor specific.\nThe versions provided by CMSIS are only generic templates. The adopted versions for a concrete device are typically provided by the device\nvendor through the according device family pack (DFP).\n\nFor example, the following files are provided by the STM32F10x device family pack:\n\n<table class=\"cmtable\">\n    <tr>\n      <th>File</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\".\\Device\\Source\\ARM\\startup_stm32f10x_cl.s\"</td>\n      <td>\\ref startup_s_pg for the STM32F10x Connectivity Line device variants.</td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\Source\\system_stmf10x.c\"</td>\n      <td>\\ref system_c_pg for the STM32F10x device families.</td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\Include\\stm32f10x.h\"</td>\n      <td>\\ref device_h_pg for the STM32F10x device families.</td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\Include\\system_stm32f10x.h\"</td>\n      <td>\\ref system_Device_h_sec for the STM32F10x device families.</td>\n    </tr>\n</table>\n\n\n\\note The silicon vendors create these device-specific CMSIS-Core (Cortex-M) files based on \\ref templates_pg provide by Arm.\n\nThereafter, the functions described under <a href=\"modules.html\">\\b Reference </a> can be used in the application.\n\n\\b Examples\n - \\subpage using_CMSIS is a simple example that shows the usage of the CMSIS layer.\n - \\subpage using_VTOR_pg shows how to remap the interrupt vector table.\n - \\subpage using_ARM_pg explains how to use CMSIS-Core (Cortex-M) for Arm processors.\n\n\n\\page using_CMSIS Basic CMSIS Example\n\nA typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device. \n    \n\\code\n#include <stm32f10x.h>                           // File name depends on device used\n \nuint32_t volatile msTicks;                       // Counter for millisecond Interval\n \nvoid SysTick_Handler (void) {                    // SysTick Interrupt Handler\n  msTicks++;                                     // Increment Counter\n}\n \nvoid WaitForTick (void)  {\n  uint32_t curTicks;\n \n  curTicks = msTicks;                            // Save Current SysTick Value\n  while (msTicks == curTicks)  {                 // Wait for next SysTick Interrupt\n    __WFE ();                                    // Power-Down until next Event/Interrupt\n  }\n}\n \nvoid TIM1_UP_IRQHandler (void) {                 // Timer Interrupt Handler\n  ;                                              // Add user code here\n}\n \nvoid timer1_init(int frequency) {                // Set up Timer (device specific)\n  NVIC_SetPriority (TIM1_UP_IRQn, 1);            // Set Timer priority\n  NVIC_EnableIRQ (TIM1_UP_IRQn);                 // Enable Timer Interrupt\n}\n \n \nvoid Device_Initialization (void)  {             // Configure & Initialize MCU\n  if (SysTick_Config (SystemCoreClock / 1000)) { // SysTick 1mSec\n       : // Handle Error \n  }\n  timer1_init ();                                // setup device-specific timer\n}\n \n \n// The processor clock is initialized by CMSIS startup + system file\nvoid main (void) {                               // user application starts here\n  Device_Initialization ();                      // Configure & Initialize MCU\n  while (1)  {                                   // Endless Loop (the Super-Loop)\n    __disable_irq ();                            // Disable all interrupts\n    Get_InputValues ();                          // Read Values\n    __enable_irq ();                             // Enable all interrupts \n    Calculation_Response ();                     // Calculate Results\n    Output_Response ();                          // Output Results\n    WaitForTick ();                              // Synchronize to SysTick Timer\n  }\n}\n\\endcode\n\nCMSIS-Pack provides the <b>\\#define CMSIS_header_file</b> in <a href=\"../../Pack/html/pdsc_components_pg.html#RTE_Components_h\"><b>RTE_Components.h</b></a> which gives you access to the <b><i>device</i>.h</b> file \nof a project. This allows you to generate generic software components that use the device selected in a project.\n\n\\code\n#include \"RTE_Components.h\"                      // include information about project configuration\n#include CMSIS_device_header                     // include <device>.h file\n\\endcode\n\n\\page using_VTOR_pg Using Interrupt Vector Remap\n\nMost Cortex-M processors provide VTOR register for remapping interrupt vectors. The following example shows\na typical use case where the interrupt vectors are copied to RAM and the SysTick_Handler is replaced.\n\n\\code\n#include \"ARMCM3.h\"                     // Device header\n \n#define VECTORTABLE_SIZE        (240)    /* size of the used vector tables    */\n                                         /* see startup file startup_ARMCM3.c */\n#define VECTORTABLE_ALIGNMENT   (0x100U) /* 16 Cortex + 32 ARMCM3 = 48 words  */\n                                         /* next power of 2 = 256             */\n\n/* externals from startup_ARMCM3.c */\nextern uint32_t __VECTOR_TABLE[VECTORTABLE_SIZE];        /* vector table ROM  */\n\n/* new vector table in RAM, same size as vector table in ROM */\nuint32_t vectorTable_RAM[VECTORTABLE_SIZE] __attribute__(( aligned (VECTORTABLE_ALIGNMENT) ));\n\n \n/*----------------------------------------------------------------------------\n  SysTick_Handler\n *----------------------------------------------------------------------------*/\nvolatile uint32_t msTicks = 0;                        /* counts 1ms timeTicks */\nvoid SysTick_Handler(void) {\n  msTicks++;                                             /* increment counter */\n}\n \n/*----------------------------------------------------------------------------\n  SysTick_Handler (RAM)\n *----------------------------------------------------------------------------*/\nvolatile uint32_t msTicks_RAM = 0;                    /* counts 1ms timeTicks */\nvoid SysTick_Handler_RAM(void) {\n  msTicks_RAM++;                                         /* increment counter */\n}\n \n/*----------------------------------------------------------------------------\n  MAIN function\n *----------------------------------------------------------------------------*/\nint main (void) {\n  uint32_t i;\n   \n  for (i = 0; i < VECTORTABLE_SIZE; i++) {\n    vectorTable_RAM[i] = __VECTOR_TABLE[i];       /* copy vector table to RAM */\n  }\n                                                   /* replace SysTick Handler */\n  vectorTable_RAM[SysTick_IRQn + 16] = (uint32_t)SysTick_Handler_RAM;\n  \n  /* relocate vector table */ \n  __disable_irq();\n    SCB->VTOR = (uint32_t)&vectorTable_RAM;\n  __DSB();\n  __enable_irq();\n \n  SystemCoreClockUpdate();                        /* Get Core Clock Frequency */\n  SysTick_Config(SystemCoreClock / 1000ul); /* Setup SysTick Timer for 1 msec */\n   \n  while(1);\n}\n\\endcode\n\n    \n\\page using_ARM_pg Using CMSIS with generic Arm Processors\n\nArm provides CMSIS-Core (Cortex-M) files for the supported Arm Processors and for various compiler vendors. \nThese files can be used when standard Arm processors should be used in a project.\nThe table below lists the folder and device names of the Arm processors.\n  \n<table class=\"cmtable\">\n    <tr>\n      <th>Folder</th>\n      <th>Processor</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM0\"</td>\n      <td>Cortex-M0</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M0 processor.\n        The device name is ARMCM0 and the name of the \\ref device_h_pg is <ARMCM0.h>.\n    </td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM0plus\"</td>\n      <td>Cortex-M0+</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M0+ processor.\n        The device name is ARMCM0plus and the name of the \\ref device_h_pg is <ARMCM0plus.h>.\n    </td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM3\"</td>\n      <td>Cortex-M3</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M3 processor.\n        The device name is ARMCM3 and the name of the \\ref device_h_pg is <ARMCM3.h>.\n    </td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM4\"</td>\n      <td>Cortex-M4</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M4 processor.\n        The device name is ARMCM4 and the name of the \\ref device_h_pg is <ARMCM4.h>.\n      </td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM7\"</td>\n      <td>Cortex-M7</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M7 processor.\n        The device name is ARMCM7 and the name of the \\ref device_h_pg is <ARMCM7.h>.\n      </td>\n    </tr>\n\\if ARMv8M\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM23\"</td>\n      <td>Cortex-M23</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M23 processor.\n        The device name is ARMCM23 and the name of the \\ref device_h_pg is <ARMCM23.h>.\n        This device is available with and without TrustZone.\n      </td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM33\"</td>\n      <td>Cortex-M33</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M33 processor.\n        The device name is ARMCM33 and the name of the \\ref device_h_pg is <ARMCM33.h>.\n        This device is available with and without TrustZone.\n      </td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM35P\"</td>\n      <td>Cortex-M35P</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M35P processor.\n        The device name is ARMCM35P and the name of the \\ref device_h_pg is <ARMCM35P.h>.\n        This device is available with and without TrustZone.\n      </td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM55\"</td>\n      <td>Cortex-M55</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M55 processor.\n        The device name is ARMCM55 and the name of the \\ref device_h_pg is <ARMCM55.h>.\n        This device is only available with TrustZone.\n      </td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMCM85\"</td>\n      <td>Cortex-M85</td>\n      <td>Contains \\b Include and \\b Source template files configured for the Cortex-M85 processor.\n        The device name is ARMCM85 and the name of the \\ref device_h_pg is <ARMCM85.h>.\n        This device is only available with TrustZone.\n      </td>\n    </tr>\n\\endif\n\\if ARMSC \n    <tr>\n      <td>\".\\Device\\ARM\\ARMSC000\"</td>\n      <td>SecurCore SC000</td>\n      <td>Contains \\b Include and \\b Source template files configured for the SecurCore SC000 processor.\n        The device name is ARMSC000 and the name of the \\ref device_h_pg is <ARMSC000.h>.\n    </td>\n    </tr>\n    <tr>\n      <td>\".\\Device\\ARM\\ARMSC300\"</td>\n      <td>SecurCore SC300</td>\n      <td>Contains \\b Include and \\b Source template files configured for the SecurCore SC300 processor.\n        The device name is ARMSC300 and the name of the \\ref device_h_pg is <ARMSC300.h>.\n    </td>\n    </tr>\n\\endif  \n</table>\n\n\\note\nCMSIS-Pack provides the <b>\\#define CMSIS_header_file</b> in <a href=\"../../Pack/html/pdsc_components_pg.html#RTE_Components_h\"><b>RTE_Components.h</b></a> which gives you access to the <b><i>device</i>.h</b> file \nof a project. This allows you to generate generic software components that adjust to the device settings.\n\n\n\\section using_ARM_Lib_sec Create generic Libraries with CMSIS\n\nThe CMSIS Processor and Core Peripheral files allow also to create generic libraries. \nThe <a href=\"../../DSP/html/index.html\">\\b CMSIS-DSP </a> Libraries are an example for such a generic library.\n\nTo build a generic Library set the define \\b __CMSIS_GENERIC and include the relevant <b>core_<cpu>.h</b> CMSIS CPU & Core Access header file for the processor.\nThe define <b>__CMSIS_GENERIC</b> disables device-dependent features such as the <b>SysTick</b> timer and the <b>Interrupt System</b>.\nRefer to \\ref core_config_sect for a list of the available <b>core_<cpu>.h</b> header files. \n\n\\b Example:\n\nThe following code section shows the usage of the <b>core_&lt;cpu&gt;.h</b> header files to build a generic library for Cortex-M0, Cortex-M3, Cortex-M4, or Cortex-M7. To\nselect the processor, the source code uses the define \\b CORTEX_M7, \\b CORTEX_M4, \\b CORTEX_M3, \\b CORTEX_M0, or \\b CORTEX_M0PLUS. One of these defines needs to be provided\non the compiler command line. By using this header file, the source code can access the functions for \\ref Core_Register_gr, \\ref intrinsic_CPU_gr, \\ref intrinsic_SIMD_gr,\nand \\ref ITM_Debug_gr.\n\n\\code\n#define __CMSIS_GENERIC              /* disable NVIC and Systick functions */\n\n#if defined (CORTEX_M7)\n  #include \"core_cm7.h\"\n#elif defined (CORTEX_M4)\n  #include \"core_cm4.h\"\n#elif defined (CORTEX_M3)\n  #include \"core_cm3.h\"\n#elif defined (CORTEX_M0)\n  #include \"core_cm0.h\"\n#elif defined (CORTEX_M0PLUS)\n  #include \"core_cm0plus.h\"\n#else\n  #error \"Processor not specified or unsupported.\"\n#endif\n\n\\endcode\n\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/UsingTrustZone.txt",
    "content": "/**\n\\cond (ARMv8M)\n*/\n\n/** \n\\page using_TrustZone_pg  Using TrustZone for Armv8-M\n\n\n\\details \nThe optional Armv8-M Security Extension is similar to Arm TrustZone technology used in Cortex-A processors, but is \noptimized for ultra-low power embedded applications. TrustZone for Armv8-M enables of multiple software security \ndomains that restrict access to secure memory and I/O only for trusted software.\n\nTrustZone for Armv8-M:\n  - preserves low interrupt latencies for both Secure and Non-secure domains.\n  - does not impose code overhead, cycle overhead or the complexity of a virtualization based solution.\n  - introduces the Secure Gateway (SG) processor instruction for calls to the secure domain.\n\n\\b Notations\n\nThis manual uses the following notations to identify functions and hardware resources that are related to TrustZone for Armv8-M:\n\n - prefix \\b TZ or \\b __TZ indicates a function that is available only in Armv8-M TrustZone enabled devices.\n - postfix \\b _NS indicates a hardware resource that belongs to the Non-secure state.\n - postfix \\b _S indicates a hardware resource that belongs to the Secure state.\n \n  \n\\section useCase_TrustZone Simplified Use Case with TrustZone\n\nAn Armv8-M TrustZone enabled device has restricted access for data, code, and I/O access to trusted \nsoftware that runs in the Secure state. Typical applications are secure IoT nodes, firmware IP protection, \nor multi-party embedded software deployments.\n\nThe figure <b>Simplified Use Case</b> shows and embedded application that is split into a <b>User Project</b> \n(executed in Non-secure state) and a <b>Firmware Project</b> (executed in Secure state). \n\n - <b>System Start:</b> after power on or reset, an Armv8-M system starts code execution in the <b>Secure state</b>. The access rights for the <b>Non-secure state</b> is configured.\n\n - <b>User Application:</b> control can be transferred to <b>Non-secure state</b> to execute user code. This code can only call functions in the <b>secure state</b> that are marked for execution with the <b>SG</b> (secure gate) instruction and memory attributes. Any attempt to access memory or peripherals that are assigned to the <b>Secure state</b> triggers a security exception.\n\n - <b>Firmware callbacks:</b> code running in the <b>Secure state</b> can execute code in the <b>Non-secure state</b> using call-back function pointers. For example, a communication stack (protected firmware) could use an I/O driver that is configured in user space.\n \n\\anchor SimpleUseCase\n\\image html \"SimpleUseCase.png\" \"Simplified Use Case\"\n\nProgram execution in the <b>Secure state</b> is further protected by TrustZone hardware from software failures.\nFor example, an Armv8-M system may implement two independent SYSTICK timers which allows to stop code execution \nin <b>Non-secure state</b> in case of timing violations. Also function pointer callbacks from <b>Secure state</b> \nto <b>Non-secure state</b> protected by a special CPU instruction and the address bit 0 which prevents anciently \nexecuting code in <b>Non-secure state</b>.\n\n\\subsection Example_TrustZone Program Examples\n\nThis CMSIS software pack contains the following program examples that show the usage of TrustZone for Armv8-M on Cortex-M33 devices:\n\nExample                                     | Description\n:-------------------------------------------|:----------------\nTrustZone for Armv8-M No RTOS               | bare-metal secure/non-secure programming without RTOS (shows the Simplified Use Case).\nTrustZone for Armv8-M RTOS                  | secure/non-secure RTOS example with thread context management\nTrustZone for Armv8-M RTOS Security Tests   | secure/non-secure RTOS example with security test cases and system recovery\n\nOther sample application that reflects this <a href=\"#SimpleUseCase\"><b>Simplified Use Case</b></a> is the <b>Armv8MBL Secure/Non-Secure example</b> that is available in \nthe Software Pack <b>Keil - Arm V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices</b> \n(Keil:V2M-MPS2_CMx_BSP.1.2.0.pack or higher).\n\n\\section Model_TrustZone Programmers Model with TrustZone\n\nThe figure <a href=\"#MemoryMap_S\"><b>Secure Memory Map</b></a> shows the memory view for the <b>Secure state</b>.  In the Secure state all\nmemory and peripherals can be accessed. The <b>System Control and Debug</b> area provides access to secure peripherals\nand non-secure peripherals that are mirrored at a memory alias.  \n\nThe secure peripherals are only accessible during program execution in <b>Secure state</b>. The Secure Attribute Unit (SAU)\nconfigures the non-secure memory, peripheral, and interrupt access. Also available are a secure MPU (memory protection \nunit), secure SCB (system control block), and secure SysTick timer.\n\nThe system supports two separate interrupt vector tables for secure and non-secure code execution. \nThis interrupt assignment is controlled during <b>Secure state</b> code execution via the NVIC \n(nested vector interrupt controller).\n\n\\anchor MemoryMap_S\n\\image html \"MemoryMap_S.png\" \"Secure Memory Map\"\n\nThe figure <a href=\"#MemoryMap_NS\"><b>Non-Secure Memory Map</b></a> shows the memory view for the Non-secure state. This memory view is identical\nto the traditional Cortex-M memory map. Access to any secure memory or peripheral space triggers the secure exception\nthat executes a handler in <b>Secure state</b>.\n\nThe \\ref partition_h_pg defines the initial setup of the <a href=\"#MemoryMap_NS\"><b>Non-Secure Memory Map</b></a> during system start in the Secure state\n(refer to functions \\ref SystemInit and \\ref TZ_SAU_Setup).\n\n<!-- <img id=\"MemoryMap_NS\" src=\"MemoryMap_NS.png\"><CENTER><b>Non-Secure Memory Map</b></CENTER> -->\n\n\\anchor MemoryMap_NS\n\\image html \"MemoryMap_NS.png\" \"Non-Secure Memory Map\" \n\nThe figure <b>Registers</b> shows the register view of the Armv8-M system with TrustZone. As the general purpose registers\nare can be accessed from any state (secure or non-secure), function calls between the states use these registers for parameter\nand return values.\n\nThe register R13 is the stack pointer alias, and the actual stack pointer (PSP_NS, MSP_NS, PSP_S, MSP_S)  \naccessed depends on state (Secure or Non-secure) and mode (handler=exception/interrupt execution or\nthread=normal code execution). \n\nIn Armv8-M Mainline, each stack pointer has a limit register (PSPLIM_NS, MSPLIM_NS, PSPLIM_S, MSPLIM_S)\nthat traps stack overflows with the \\b UsageFault exception (register UFSR bit STKOF=1).\n\nAn Armv8-M system with TrustZone has an independent \\b CONTROL register for each state (Secure or Non-secure).\nThe interrupt/exception control registers (PRIMASK, FAULTMASK, BASEPRI) are banked between the states (Secure or Non-secure),\nhowever the interrupt priority for the Non-Secure state can be lowered (SCB_AIRCR register bit PRIS) so that \nsecure interrupts have always higher priority.\n\nThe core registers of the current state (Secure or Non-secure) are accessed using the standard \\ref Core_Register_gr\nfunctions. In Secure state all non-secure registers are accessible using the \\ref coreregister_trustzone_functions \nrelated to TrustZone for Armv8-M.\n\n\\image html \"Registers.png\" \"Registers\"\n\n\\subsection RTOS_TrustZone_stacksealing Stack Sealing\n\nCMSIS-Core \\ref stacksealing_support_trustzone_functions provide standard interface for implementing the <a href=\"https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing\" target=\"_blank\"><b>Secure Stack Sealing technique</b></a> recommended for mitigating some security vulnerabilities on Armv8-M systems with TrustZone.\n\n\\ref startup_c_sec_v8 demonstrates how this functionality can be used in a device startup file. \n\nStack Sealing also requires an application project to have a linker script that explicitly reserves 8 bytes for the stack seal on top of the secure main stack. Linker files provided with \\ref device_examples for Armv8-M cores demonstrate how this can be implemented. For example see .\\\\Device\\\\ARM\\\\ARMCM33\\\\Source\\\\ARM\\\\ARMCM33_ac6.sct.\n\nTo learn more about the stack sealing implementation in CMSIS projects for Armv8-M devices, refer to\n<a href=\"https://www.keil.com/appnotes/docs/apnt_335.asp\" target=\"_blank\"><b>Application Note 335</b></a>.\n\n\\section CMSIS_Files_TrustZone CMSIS Files for TrustZone\n\nThe CMSIS-Core files are extended by the header files \\ref partition_h_pg and \\ref partition_gen_h_pg :\n\n - The file \\ref partition_h_pg \"partition_<device>.h\" defines the initial system configuration and during SystemInit in Secure state.\n - The file \\ref partition_gen_h_pg \"partition_gen.h\" is optional and contains SAU region and interrupt target assignments. This file may be generated using CMSIS-Zone.\n\n\\note\nRefer to \\ref using_pg for a general description of the CMSIS-Core (Cortex-M) files.\n\n\\image html \"CMSIS_TZ_files.png\" \"CMSIS with extensions for TrustZone\"\n\n&nbsp;\n\n\\subsection RTOS_TrustZone RTOS Thread Context Management\n\nTo provide a consistent RTOS thread context management for Armv8-M TrustZone across the various real-time operating systems (RTOS), the CMSIS-Core (Cortex-M) includes header file <b>TZ_context.h</b> with API definitions.\nAn <i>non-secure application</i> which uses an RTOS and calls <i>secure</i> library modules requires the management of the <i>secure</i> stack space.   Since <i>secure state</i> registers cannot be accessed \nby the RTOS that runs in <i>non-secure state</i> secure functions implement the thread context switch.\n\nAs the <i>non-secure state</i> and <i>secure state</i> parts of an application are separated, the API for managing the <i>secure</i> stack space should be standardized. Otherwise the <i>secure</i> library modules\nwould force the <i>non-secure state</i> application to use a matching RTOS implementation.\n\n\\image html \"TZ_context.png\" \"RTOS Thread Context Management for Armv8-M TrustZone\"\n\nTo allocate the context memory for threads, an RTOS kernel that runs in <i>non-secure state</i> calls the interface functions defined by the header file <b>TZ_context.h</b>. The <b>TZ_context</b> functions itself are\npart of the <i>secure state</i> application. An minimum implementation is provided as part of RTOS2 and should handle the secure stack for the thread execution. However it is also possible to implement the context memory \nmanagement system with additional features such as access control to <i>secure state</i> memory regions using an MPU.\n\nThe API functions of <b>TZ_context</b> are described in the chapter <a href=\"modules.html\">\\b Reference </a> under \\ref trustzone_functions - \\ref context_trustzone_functions.\n\nRefer to \\ref Example_TrustZone for RTOS examples that provide a template implementation for <b>TZ_context.c</b>.\n  \n*/\n\n/**\n\\endcond\n*/"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core/src/core_cm7.txt",
    "content": "/**\n\\defgroup cache_functions_m7 Cache Functions (Level-1)\n\\brief Functions for level-1 instruction and data cache.\n\\details \nEnhanced Cortex processors (like M7 and M55) include a memory system, which includes an optional\nHarvard level-1 data and instruction cache with ECC. The optional CPU cache has an instruction\nand data cache with sizes of \\token{[0;4;8;16;32;64]KB}.\nBoth instruction and data cache RAM can be configured at implementation time to have Error\nCorrecting Code (ECC) to protect the data stored in the memory from errors.\n\nAll cache maintenance operations are executed by writing to registers in the memory mapped\nSystem Control Space (SCS) region of the internal PPB memory space. \n\n\\note \nAfter reset, you must invalidate each cache before enabling it. \n \nThe functions are grouped for:\n - \\ref Icache_functions_m7\n - \\ref Dcache_functions_m7\n\n@{\n*/\n\n/**\n  \\defgroup Icache_functions_m7 I-Cache Functions\n  \\brief Functions for the level-1 instruction cache.\n  @{\n*/\n \n\n\n/**\n  \\brief Enable I-Cache.\n  \n  The function turns on the instruction cache.\n\\note\nBefore enabling the instruction cache, you must invalidate (\\ref SCB_InvalidateICache) the entire instruction cache if\nexternal memory might have changed since the cache was disabled.\n\\note \nAfter reset, you must invalidate (\\ref SCB_InvalidateICache) each cache before enabling it. \n*/\n__STATIC_FORCEINLINE void SCB_EnableICache (void);\n\n\n/**\n  \\brief Disable I-Cache.\n  \n  The function turns off the instruction cache.\n\n*/\n__STATIC_FORCEINLINE void SCB_DisableICache (void);\n\n\n/**\n  \\brief Invalidate I-Cache.\n  \n  The function invalidates the instruction cache.\n  The instruction cache is never dirty so cache RAM errors are always recoverable by invalidating the cache and retrying the instruction.\n\\note \nAfter reset, you must invalidate each cache before enabling (\\ref SCB_EnableICache) it. \n\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateICache (void);\n\n\n/**\n  \\brief   I-Cache Invalidate by address\n  \\details Invalidates I-Cache for the given address.\n           I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.\n           I-Cache memory blocks which are part of given address + given size are invalidated.\n  \\param[in]   addr    address\n  \\param[in]   isize   size of memory block (in number of bytes)\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize);\n\n/**\n  @}  // close ICache functions\n*/\n \n/**\n  \\defgroup Dcache_functions_m7 D-Cache Functions\n  \\brief Functions for the level-1 data cache.\n\n  @{\n*/\n\n/**\n  \\brief Enable D-Cache.\n  \n  The function turns on the entire data cache.\n\\note \nBefore enabling the data cache, you must invalidate the entire data cache (\\ref SCB_InvalidateDCache), because external\nmemory might have changed from when the cache was disabled.\n\n\\note \nAfter reset, you must invalidate (\\ref SCB_InvalidateDCache) each cache before enabling it. \n*/\n__STATIC_FORCEINLINE void SCB_EnableDCache (void);\n\n\n/** \n  \\brief Disable D-Cache.\n  \n  The function turns off the entire data cache.\n  \n\\note\nWhen disabling the data cache, you must clean (\\ref SCB_CleanDCache) the entire cache to ensure that any dirty data is\nflushed to external memory.\n\n*/\n__STATIC_FORCEINLINE void SCB_DisableDCache (void);\n\n\n/**\n  \\brief Invalidate D-Cache.\n\n  The function invalidates the entire data cache.\n\n\\note\nAfter reset, you must invalidate each cache before enabling (\\ref SCB_EnableDCache) it. \n\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateDCache (void);\n\n\n/** \n  \\brief Clean D-Cache.\n\n  The function cleans the entire data cache.\n*/\n__STATIC_FORCEINLINE void SCB_CleanDCache (void);\n\n\n/** \n  \\brief Clean & Invalidate D-Cache.\n \n  The function cleans and invalidates the entire data cache.\n*/\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void);\n\n\n/**\n  \\brief       D-Cache Invalidate by address\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n  \n  The function invalidates a memory block of size \\em dsize [bytes] starting at address \\em address. The address is aligned to 32-byte boundary.\n*/\n__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize);\n\n\n/**\n  \\brief       D-Cache Clean by address\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n  \n  The function cleans a memory block of size \\em dsize [bytes] starting at address \\em address. The address is aligned to 32-byte boundary.\n\n\n*/\n__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize);\n\n\n/**\n  \\brief       D-Cache Clean and Invalidate by address\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n  \n  The function invalidates and cleans a memory block of size \\em dsize [bytes] starting at address \\em address. The address is aligned to 32-byte boundary.\n*/\n__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize);\n\n/**\n@}  // close D-Cache Functions\n@}\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/core_A.dxy",
    "content": "# Doxyfile 1.8.6\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a double hash (##) is considered a comment and is placed in\n# front of the TAG it is preceding.\n#\n# All text after a single hash (#) is considered a comment and will be ignored.\n# The format is:\n# TAG = value [value, ...]\n# For lists, items can also be appended using:\n# TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\\\" \\\").\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the config file\n# that follow. The default is UTF-8 which is also the encoding used for all text\n# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv\n# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv\n# for the list of possible encodings.\n# The default value is: UTF-8.\n\nDOXYFILE_ENCODING      = UTF-8\n\n# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by\n# double-quotes, unless you are using Doxywizard) that should identify the\n# project for which the documentation is generated. This name is used in the\n# title of most generated pages and in a few other places.\n# The default value is: My Project.\n\nPROJECT_NAME           = \"CMSIS-Core (Cortex-A)\"\n\n# The PROJECT_NUMBER tag can be used to enter a project or revision number. This\n# could be handy for archiving the generated documentation or if some version\n# control system is used.\n\nPROJECT_NUMBER         = \"Version 1.2.1\"\n\n# Using the PROJECT_BRIEF tag one can provide an optional one line description\n# for a project that appears at the top of each page and should give viewer a\n# quick idea about the purpose of the project. Keep the description short.\n\nPROJECT_BRIEF          = \"CMSIS-Core support for Cortex-A processor-based devices\"\n\n# With the PROJECT_LOGO tag one can specify an logo or icon that is included in\n# the documentation. The maximum height of the logo should not exceed 55 pixels\n# and the maximum width should not exceed 200 pixels. Doxygen will copy the logo\n# to the output directory.\n\nPROJECT_LOGO           = ../Doxygen_Templates/CMSIS_Logo_Final.png\n\n# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path\n# into which the generated documentation will be written. If a relative path is\n# entered, it will be relative to the location where doxygen was started. If\n# left blank the current directory will be used.\n\nOUTPUT_DIRECTORY       = ../../Documentation/Core_A\n\n# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-\n# directories (in 2 levels) under the output directory of each output format and\n# will distribute the generated files over these directories. Enabling this\n# option can be useful when feeding doxygen a huge amount of source files, where\n# putting all generated files in the same directory would otherwise causes\n# performance problems for the file system.\n# The default value is: NO.\n\nCREATE_SUBDIRS         = NO\n\n# The OUTPUT_LANGUAGE tag is used to specify the language in which all\n# documentation generated by doxygen is written. Doxygen will use this\n# information to generate all constant output in the proper language.\n# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,\n# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),\n# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,\n# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),\n# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,\n# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,\n# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,\n# Ukrainian and Vietnamese.\n# The default value is: English.\n\nOUTPUT_LANGUAGE        = English\n\n# If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member\n# descriptions after the members that are listed in the file and class\n# documentation (similar to Javadoc). Set to NO to disable this.\n# The default value is: YES.\n\nBRIEF_MEMBER_DESC      = YES\n\n# If the REPEAT_BRIEF tag is set to YES doxygen will prepend the brief\n# description of a member or function before the detailed description\n#\n# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the\n# brief descriptions will be completely suppressed.\n# The default value is: YES.\n\nREPEAT_BRIEF           = NO\n\n# This tag implements a quasi-intelligent brief description abbreviator that is\n# used to form the text in various listings. Each string in this list, if found\n# as the leading text of the brief description, will be stripped from the text\n# and the result, after processing the whole list, is used as the annotated\n# text. Otherwise, the brief description is used as-is. If left blank, the\n# following values are used ($name is automatically replaced with the name of\n# the entity):The $name class, The $name widget, The $name file, is, provides,\n# specifies, contains, represents, a, an and the.\n\nABBREVIATE_BRIEF       = \"The $name class\" \\\n                         \"The $name widget\" \\\n                         \"The $name file\" \\\n                         is \\\n                         provides \\\n                         specifies \\\n                         contains \\\n                         represents \\\n                         a \\\n                         an \\\n                         the\n\n# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then\n# doxygen will generate a detailed section even if there is only a brief\n# description.\n# The default value is: NO.\n\nALWAYS_DETAILED_SEC    = NO\n\n# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all\n# inherited members of a class in the documentation of that class as if those\n# members were ordinary class members. Constructors, destructors and assignment\n# operators of the base classes will not be shown.\n# The default value is: NO.\n\nINLINE_INHERITED_MEMB  = NO\n\n# If the FULL_PATH_NAMES tag is set to YES doxygen will prepend the full path\n# before files name in the file list and in the header files. If set to NO the\n# shortest path that makes the file name unique will be used\n# The default value is: YES.\n\nFULL_PATH_NAMES        = NO\n\n# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.\n# Stripping is only done if one of the specified strings matches the left-hand\n# part of the path. The tag can be used to show relative paths in the file list.\n# If left blank the directory from which doxygen is run is used as the path to\n# strip.\n#\n# Note that you can specify absolute paths here, but also relative paths, which\n# will be relative from the directory where doxygen is started.\n# This tag requires that the tag FULL_PATH_NAMES is set to YES.\n\nSTRIP_FROM_PATH        = \n\n# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the\n# path mentioned in the documentation of a class, which tells the reader which\n# header file to include in order to use a class. If left blank only the name of\n# the header file containing the class definition is used. Otherwise one should\n# specify the list of include paths that are normally passed to the compiler\n# using the -I flag.\n\nSTRIP_FROM_INC_PATH    = \n\n# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but\n# less readable) file names. This can be useful is your file systems doesn't\n# support long names like on DOS, Mac, or CD-ROM.\n# The default value is: NO.\n\nSHORT_NAMES            = NO\n\n# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the\n# first line (until the first dot) of a Javadoc-style comment as the brief\n# description. If set to NO, the Javadoc-style will behave just like regular Qt-\n# style comments (thus requiring an explicit @brief command for a brief\n# description.)\n# The default value is: NO.\n\nJAVADOC_AUTOBRIEF      = NO\n\n# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first\n# line (until the first dot) of a Qt-style comment as the brief description. If\n# set to NO, the Qt-style will behave just like regular Qt-style comments (thus\n# requiring an explicit \\brief command for a brief description.)\n# The default value is: NO.\n\nQT_AUTOBRIEF           = NO\n\n# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a\n# multi-line C++ special comment block (i.e. a block of //! or /// comments) as\n# a brief description. This used to be the default behavior. The new default is\n# to treat a multi-line C++ comment block as a detailed description. Set this\n# tag to YES if you prefer the old behavior instead.\n#\n# Note that setting this tag to YES also means that rational rose comments are\n# not recognized any more.\n# The default value is: NO.\n\nMULTILINE_CPP_IS_BRIEF = YES\n\n# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the\n# documentation from any documented member that it re-implements.\n# The default value is: YES.\n\nINHERIT_DOCS           = NO\n\n# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a\n# new page for each member. If set to NO, the documentation of a member will be\n# part of the file/class/namespace that contains it.\n# The default value is: NO.\n\nSEPARATE_MEMBER_PAGES  = NO\n\n# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen\n# uses this value to replace tabs by spaces in code fragments.\n# Minimum value: 1, maximum value: 16, default value: 4.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that act as commands in\n# the documentation. An alias has the form:\n# name=value\n# For example adding\n# \"sideeffect=@par Side Effects:\\n\"\n# will allow you to put the command \\sideeffect (or @sideeffect) in the\n# documentation, which will result in a user-defined paragraph with heading\n# \"Side Effects:\". You can put \\n's in the value part of an alias to insert\n# newlines.\n\nALIASES                = \"token{1}=<span class=\\\"XML-Token\\\">\\1</span>\"\n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding \"class=itcl::class\"\n# will allow you to use the command class in the itcl::class meaning.\n\nTCL_SUBST              = \n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources\n# only. Doxygen will then generate output that is more tailored for C. For\n# instance, some of the names that are used will be different. The list of all\n# members will be omitted, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_FOR_C  = YES\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or\n# Python sources only. Doxygen will then generate output that is more tailored\n# for that language. For instance, namespaces will be presented as packages,\n# qualified scopes will look different, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources. Doxygen will then generate output that is tailored for Fortran.\n# The default value is: NO.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for VHDL.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given\n# extension. Doxygen has a built-in mapping, but you can override or extend it\n# using this tag. The format is ext=language, where ext is a file extension, and\n# language is one of the parsers supported by doxygen: IDL, Java, Javascript,\n# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C.\n#\n# Note For files without extension you can use no_extension as a placeholder.\n#\n# Note that for custom extensions you also need to set FILE_PATTERNS otherwise\n# the files are not read by doxygen.\n\nEXTENSION_MAPPING      = \n\n# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments\n# according to the Markdown format, which allows for more readable\n# documentation. See http://daringfireball.net/projects/markdown/ for details.\n# The output of markdown processing is further processed by doxygen, so you can\n# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in\n# case of backward compatibilities issues.\n# The default value is: YES.\n\nMARKDOWN_SUPPORT       = YES\n\n# When enabled doxygen tries to link words that correspond to documented\n# classes, or namespaces to their corresponding documentation. Such a link can\n# be prevented in individual cases by by putting a % sign in front of the word\n# or globally by setting AUTOLINK_SUPPORT to NO.\n# The default value is: YES.\n\nAUTOLINK_SUPPORT       = YES\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should set this\n# tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string);\n# versus func(std::string) {}). This also make the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n# The default value is: NO.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n# The default value is: NO.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:\n# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen\n# will parse them like normal C++ but will assume all classes use public instead\n# of private inheritance when no explicit protection keyword is present.\n# The default value is: NO.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate\n# getter and setter methods for a property. Setting this option to YES will make\n# doxygen to replace the get and set methods by a property in the documentation.\n# This will only work if the methods are indeed getting or setting a simple\n# type. If this is not the case, or you want to show the methods anyway, you\n# should set this option to NO.\n# The default value is: YES.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n# The default value is: NO.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES to allow class member groups of the same type\n# (for instance a group of public functions) to be put as a subgroup of that\n# type (e.g. under the Public Functions section). Set it to NO to prevent\n# subgrouping. Alternatively, this can be done per class using the\n# \\nosubgrouping command.\n# The default value is: YES.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions\n# are shown inside the group in which they are included (e.g. using \\ingroup)\n# instead of on a separate page (for HTML and Man pages) or section (for LaTeX\n# and RTF).\n#\n# Note that this feature does not work in combination with\n# SEPARATE_MEMBER_PAGES.\n# The default value is: NO.\n\nINLINE_GROUPED_CLASSES = NO\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions\n# with only public data fields or simple typedef fields will be shown inline in\n# the documentation of the scope in which they are defined (i.e. file,\n# namespace, or group documentation), provided this scope is documented. If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = NO\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = YES\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = YES\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = NO\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = YES\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = NO\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = NO\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = \n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = YES\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         = \n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = src/Overview.txt \\\n                         src/Using.txt \\\n                         src/Template.txt \\\n                         src/MISRA.txt \\\n                         src/Ref_SystemAndClock.txt \\\n                         src/ref_gic.txt \\\n                         src/ref_core_register.txt \\\n                         src/ref_cache.txt \\\n                         src/ref_timer.txt \\\n                         src/ref_mmu.txt \\\n                         src/core_ca.txt \\\n                         src/cmsis_armcc.txt \\\n                         src/irq_ctrl.txt \\\n                         ../../Core_A/Include/core_ca.h \\\n                         ../../Core_A/Include/cmsis_armcc.h \\\n                         ../../Core_A/Include/cmsis_cp15.h \\\n                         ../../Core_A/Source/irq_ctrl_gic.c \\\n                         ../../Core_A/Include/irq_ctrl.h \\\n                         ../../../Device/ARM/ARMCA9/Include/ARMCA9.h \\\n                         ../../../Device/ARM/ARMCA9/Config/mem_ARMCA9.h \\\n                         ../../../Device/ARM/ARMCA9/Config/system_ARMCA9.h \\\n                         ../../../Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          = \n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = NO\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s \\\n                         src/exclude/\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = NO\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       = \n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        = \n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = ../../../Device/_Template_Vendor/Vendor/Device_A\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           = \n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        = \n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS = \n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE = \n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = YES\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = NO\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = NO\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = NO\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        = \n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../Doxygen_Templates/search.css \\\n                         ../Doxygen_Templates/check.png \\\n                         ../Doxygen_Templates/printComponentTabs.js\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 106\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = CMSIS_Core.chm\n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \"C:/Program Files/HTML Help Workshop/hhc.exe\"\n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     = \n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               = \n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   = \n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  = \n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  = \n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           = \n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     = \n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       = \n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       = \n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     = \n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         = \n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           = \n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           = \n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      = \n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    = \n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             = \n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                = \n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen\n# Definitions (see http://autogen.sf.net) file that captures the structure of\n# the code including all documentation. Note that this feature is still\n# experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES doxygen will generate a Perl module\n# file that captures the structure of the code including all documentation.\n#\n# Note that this feature is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES doxygen will generate the necessary\n# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI\n# output from the Perl module output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be nicely\n# formatted so it can be parsed by a human reader. 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This is useful\n# so different doxyrules.make files included by the same Makefile don't\n# overwrite each other's variables.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_MAKEVAR_PREFIX = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the preprocessor\n#---------------------------------------------------------------------------\n\n# If the ENABLE_PREPROCESSING tag is set to YES doxygen will evaluate all\n# C-preprocessor directives found in the sources and include files.\n# The default value is: YES.\n\nENABLE_PREPROCESSING   = YES\n\n# If the MACRO_EXPANSION tag is set to YES doxygen will expand all macro names\n# in the source code. If set to NO only conditional compilation will be\n# performed. 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To prevent a macro definition from being undefined via #undef or\n# recursively expanded use the := operator instead of the = operator.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nPREDEFINED             = DOXYGEN \\\n                         __L2C_PRESENT:=1 \\\n                         __CC_ARM:=1 \\\n                         __TARGET_FPU_VFP:=1 \\\n                         __CHECK_DEVICE_DEFINES:=1 \\\n                         __cplusplus:=1 \\\n                         __TI_ARM__:=1 \\\n                         __TASKING__:=1 \\\n                         __NO_EMBEDDED_ASM:=0 \\\n                         __CORTEX_A:=9 \\\n             __CA_REV:=0x0000 \\\n                         __TARGET_ARCH_7_A:=1\n\n# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this\n# tag can be used to specify a list of macro names that should be expanded. The\n# macro definition that is found in the sources will be used. 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For each tag\n# file the location of the external documentation should be added. The format of\n# a tag file without this location is as follows:\n# TAGFILES = file1 file2 ...\n# Adding location for the tag files is done as follows:\n# TAGFILES = file1=loc1 \"file2 = loc2\" ...\n# where loc1 and loc2 can be relative or absolute paths or URLs. See the\n# section \"Linking to external documentation\" for more information about the use\n# of tag files.\n# Note: Each tag file must have an unique name (where the name does NOT include\n# the path). If a tag file is not located in the directory in which doxygen is\n# run, you must also specify the path to the tagfile here.\n\nTAGFILES               = \n\n# When a file name is specified after GENERATE_TAGFILE, doxygen will create a\n# tag file that is based on the input files it reads. See section \"Linking to\n# external documentation\" for more information about the usage of tag files.\n\nGENERATE_TAGFILE       = \n\n# If the ALLEXTERNALS tag is set to YES all external class will be listed in the\n# class index. If set to NO only the inherited external classes will be listed.\n# The default value is: NO.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in\n# the modules index. If set to NO, only the current project's groups will be\n# listed.\n# The default value is: YES.\n\nEXTERNAL_GROUPS        = YES\n\n# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in\n# the related pages index. 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Note that this option also works with HAVE_DOT\n# disabled, but it is recommended to install and use dot, since it yields more\n# powerful graphs.\n# The default value is: YES.\n\nCLASS_DIAGRAMS         = YES\n\n# You can define message sequence charts within doxygen comments using the \\msc\n# command. Doxygen will then run the mscgen tool (see:\n# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the\n# documentation. The MSCGEN_PATH tag allows you to specify the directory where\n# the mscgen tool resides. If left empty the tool is assumed to be found in the\n# default search path.\n\nMSCGEN_PATH            = \n\n# You can include diagrams made with dia in doxygen documentation. Doxygen will\n# then run dia to produce the diagram and insert it in the documentation. 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The\n# dependency relations are determined by the #include relations between the\n# files in the directories.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDIRECTORY_GRAPH        = YES\n\n# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images\n# generated by dot.\n# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order\n# to make the SVG files visible in IE 9+ (other browsers do not have this\n# requirement).\n# Possible values are: png, jpg, gif and svg.\n# The default value is: png.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_IMAGE_FORMAT       = png\n\n# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to\n# enable generation of interactive SVG images that allow zooming and panning.\n#\n# Note that this requires a modern browser other than Internet Explorer. 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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/MISRA.txt",
    "content": "/** \\page coreMISRA_Exceptions_pg MISRA-C Deviations\nCMSIS-Core (Cortex-A) uses the common coding rules for CMSIS components that are documented under \n<a href=\"../../General/html/index.html\"><b>Introduction</b></a>.\n\n\nCMSIS-Core (Cortex-A) violates the following MISRA-C:2004 rules:\n\nTO BE EVALUATED\n*/\n/*  \n- Required Rule 8.5, object/function definition in header file.<br>\n  Violated since function definitions in header files are used for function inlining'. \n   \n- Advisory Rule 12.4, Side effects on right hand side of logical operator.<br>\n  Violated because volatile is used for core register definitions. \n   \n- Advisory Rule 14.7, Return statement before end of function.<br>\n  Violated to simplify code logic. \n\n- Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n  Violated since unions are used for effective representation of core registers.\n   \n- Advisory Rule 19.4, Disallowed definition for macro.<br>\n  Violated since macros are used for assembler keywords. \n   \n- Advisory Rule 19.7, Function-like macro defined.<br>\n  Violated since function-like macros are used to generate more efficient code. \n   \n- Advisory Rule 19.16, all preprocessing directives must be valid.<br>\n  Violated to set default settings for macros. \n*/\n\n/**\nCMSIS-Core (Cortex-A) violates the following MISRA-C:2012 rules:\n\nTO BE EVALUATED\n*/\n/*\n- Directive 4.9, function-like macro defined.<br>\n  Violated since function-like macros are used to generate more efficient code. \n   \n- Rule 1.3, multiple use of '#/##' operators in macro definition.<br>\n  Violated since function-like macros are used to generate more efficient code. \n   \n- Rule 11.4, conversion between a pointer and integer type.<br>\n  Violated because of core register access. \n   \n- Rule 11.6, cast from unsigned long to pointer.<br>\n  Violated because of core register access. \n   \n- Rule 13.5, side effects on right hand side of logical operator.<br>\n  Violated because of shift operand is used in macros and functions. \n   \n- Rule 14.4, conditional expression should have essentially Boolean type.<br>\n  Violated since macros with several instructions are used.\n  \n- Rule 15.5, return statement before end of function.<br>\n  Violated to simplify code logic. \n\n- Rule 20.10, '#/##' operators used.<br>\n  Violated since function-like macros are used to generate more efficient code. \n   \n- Rule 21.1, reserved to the compiler.<br>\n  Violated since macros with leading underscores are used. \n*/   \n"
  },
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/Overview.txt",
    "content": "/** \\mainpage Overview\n\nCMSIS-Core (Cortex-A) implements the basic run-time system for a Cortex-A device and gives the user access to the processor core and the device peripherals.\nIn detail it defines:\n - <b>Hardware Abstraction Layer (HAL)</b> for Cortex-A processor registers with standardized  definitions for the GIC, FPU, MMU, Cache, and core access functions.\n - <b>System exception names</b> to interface to system exceptions without having compatibility issues.\n - <b>Methods to organize header files</b> that makes it easy to learn new Cortex-A microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.\n - <b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.\n - <b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.\n - A variable to determine the <b>system clock frequency</b> which simplifies the setup of the system timers.\n\n\nThe following sections provide details about the CMSIS-Core (Cortex-A):\n - \\ref using_pg describes the project setup and shows a simple program example.\n - \\ref templates_pg describes the files of the CMSIS-Core (Cortex-A) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.\n - \\ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.\n - <a href=\"modules.html\">\\b Reference </a> describe the features and functions of the \\ref device_h_pg in detail.\n - <a href=\"annotated.html\">\\b Data \\b Structures </a> describe the data structures of the \\ref device_h_pg in detail.\n    \n<hr>\n\nCMSIS-Core (Cortex-A) in ARM::CMSIS Pack\n-----------------------------\n\nFiles relevant to CMSIS-Core (Cortex-A) are present in the following <b>ARM::CMSIS</b> directories:\n|File/Folder                     |Content                                                                 |\n|--------------------------------|------------------------------------------------------------------------|\n|\\b CMSIS\\\\Documentation\\\\Core_A | This documentation                                                     |\n|\\b CMSIS\\\\Core_A\\\\Include       | CMSIS-Core (Cortex-A) header files (for example core_ca.h, etc.)                |\n|\\b Device                       | \\ref using_ARM_pg \"Arm reference implementations\" of Cortex-A devices  |\n|\\b Device\\\\\\_Template_Vendor    | \\ref templates_pg for extension by silicon vendors                     |\n\n<hr>\n\n\\section ref_v7A Processor Support\n\nCMSIS supports a selected subset of <a href=\"http://www.arm.com/products/processors/cortex-a/index.php\" target=\"_blank\"><b>Cortex-A processors</b></a>.\n\n\\subsection ref_man_ca_sec Cortex-A Technical Reference Manuals\n\nThe following Technical Reference Manuals describe the various Arm Cortex-A processors:\n- <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.ddi0433c/DDI0433C_cortex_a5_trm.pdf\" target=\"_blank\"><b>Cortex-A5</b></a> (Armv7-A architecture)\n- <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/DDI0464F_cortex_a7_mpcore_r0p5_trm.pdf\" target=\"_blank\"><b>Cortex-A7</b></a> (Armv7-A architecture)\n- <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.100511_0401_10_en/arm_cortexa9_trm_100511_0401_10_en.pdf\" target=\"_blank\"><b>Cortex-A9</b></a> (Armv7-A architecture)\n \n<hr>\n\n\\section tested_tools_sec Tested and Verified Toolchains\n\nThe \\ref templates_pg supplied by Arm have been tested and verified with the following toolchains:\n - Arm: Arm Compiler 5.06 update 7\n - Arm: Arm Compiler 6.16\n - Arm: Arm Compiler 6.6.4\n - GNU: GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)\n - IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183\n \n<hr>\n*/\n\n\n/**\n\\page rev_histCoreA Revision History of CMSIS-Core (Cortex-A)\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>V1.2.1</td>\n      <td>\n        <ul>\n          <li>Bugfixes for Cortex-A32</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V1.2.0</td>\n      <td>\n        <ul>\n          <li>Fixed GIC_SetPendingIRQ to use GICD_SGIR instead of GICD_SPENDSGIR\n              for compliance with all GIC specification versions.</li>\n          <li>Added missing DSP intrinsics.</li>\n          <li>Reworked assembly intrinsics: volatile, barriers and clobbers.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V1.1.4</td>\n      <td>\n        <ul>\n          <li>Fixed __FPU_Enable().</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V1.1.3</td>\n      <td>\n        <ul>\n          <li>Fixed __get_SP_usr()/__set_SP_usr() for ArmClang.</li>\n          <li>Fixed zero argument handling in __CLZ() .</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V1.1.2</td>\n      <td>\n        <ul>\n          <li>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.</li>\n          <li>Fixed co-processor register access macros for Arm Compiler 5.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V1.1.1</td>\n      <td>\n        <ul>\n          <li>Refactored L1 cache maintenance to be compiler agnostic.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V1.1.0</td>\n      <td>\n        <ul>\n          <li>Added compiler_iccarm.h for IAR compiler.</li>\n          <li>Added missing core access functions for Arm Compiler 5.</li>\n          <li>Aligned access function to coprocessor 15.</li>\n          <li>Additional generic Timer functions.</li>\n          <li>Bug fixes and minor enhancements.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>V1.0.0</td>\n      <td>Initial Release for Cortex-A5/A7/A9 processors.</td>\n    </tr>\n</table>\t\n\t\n*/\n\n\n/**\n\\page device_h_pg Device Header File \\<device.h>\n\nThe \\ref device_h_pg contains the following sections that are device specific:\n - \\ref irqn_defs provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.\n - \\ref config_perifs reflect the features of the device.\n - \\ref access_perifs definitions for the \\ref peripheral_gr to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.\n - <b>Access Functions for Peripherals (optioal)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.\n\n\\section irqn_defs Interrupt Number Definition\n\n\\section config_perifs Configuration of the Processor and Core Peripherals\n\n\\section access_perifs Device Peripheral Access Layer\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/Ref_SystemAndClock.txt",
    "content": "/* ################################  System and Clock Configuration   ########################### */\n/**************************************************************************************************/\n/**\n\\defgroup   system_init_gr   System and Clock Configuration\n\\brief Functions for system and clock setup available in system_<i>device</i>.c.\n\\details\nArm provides a template file <b>system_<i>device</i>.c</b> that must be adapted by \nthe silicon vendor to match their actual device. As a <b>minimum requirement</b>, \nthis file must provide:\n -  A device-specific system configuration function, \\ref SystemInit().\n -  A global variable that contains the system frequency, \\ref SystemCoreClock. \n\nThe file configures the device and, typically, initializes the oscillator (PLL) that is part \nof the microcontroller device. This file might export other functions or variables that provide \na more flexible configuration of the microcontroller system.\n\n\\note Please pay special attention to the static variable \\c SystemCoreClock. This variable might be\nused throughout the whole system initialization and runtime to calculate frequency/time related values.\nThus one must assure that the variable always reflects the actual system clock speed. Be aware that\na value stored to \\c SystemCoreClock during low level initialization (i.e. \\c SystemInit()) might get\noverwritten by C library startup code. Thus its highly recommended to call \\ref SystemCoreClockUpdate\nat the beginning of the user \\c main() routine.\n\n\\section system_init_code_ex_sec Code Example\nThe code below shows the usage of the variable \\ref SystemCoreClock and the functions \nSystemInit() and SystemCoreClockUpdate() with an arbitrary Arm Cortex-A9.\n    \n\\code\n#include \"ARMCA9.h\"\n\nuint32_t coreClock_1 = 0;                       /* Variables to store core clock values */\nuint32_t coreClock_2 = 0;\n\n\nint main (void)  {\n\n  coreClock_1 = SystemCoreClock;                /* Store value of predefined SystemCoreClock */\n\n  SystemCoreClockUpdate();                      /* Update SystemCoreClock according to register settings */\n\n  coreClock_2 = SystemCoreClock;                /* Store value of calculated SystemCoreClock */\n\n  if (coreClock_2 != coreClock_1)  {            /* Without changing the clock setting both core clock values should be the same */ \n    // Error Handling\n  }\n\n  while(1);\n}\n\\endcode    \n    \n@{\n*/\n\n\n/**************************************************************************************************/\n/** \n    \\brief      Variable to hold the system core clock value\n    \\details\n    Holds the system core clock, which is the system clock\tfrequency supplied to the SysTick \n    timer and the processor core clock. This variable can be used by debuggers to query the \n    frequency of the debug timer or to configure the trace clock speed.\n                     \n    \\attention  Compilers must be configured to avoid removing this variable in case the application \n                program is not using it. Debugging systems require the variable to be physically \n                present in memory so that it can be examined to configure the debugger.\n*/\nuint32_t SystemCoreClock;\n\n\n/**************************************************************************************************/\n/** \n    \\brief      Function to Initialize the system.\n    \\details    \n    Initializes the microcontroller system. Typically, this function configures the \n                     oscillator (PLL) that is part of the microcontroller device. For systems \n                     with a variable clock speed, it updates the variable \\ref SystemCoreClock.\n                     SystemInit is called from the file <b>startup<i>_device</i></b>.\n*/\nvoid SystemInit (void);\n\n\n/**************************************************************************************************/\n/** \n    \\brief      Function to update the variable \\ref SystemCoreClock\n    \\details    \n    Updates the variable \\ref SystemCoreClock and must be called whenever the core clock is changed \n    during program execution. The function evaluates the clock register settings and calculates \n    the current core clock.\n*/\nvoid SystemCoreClockUpdate (void);\n\n\n/** @} */  /* end group system_init_gr */\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/Template.txt",
    "content": "/**\n\\page templates_pg CMSIS-Core Device Templates\n\n\\details\n\nArm supplies CMSIS-Core device template files for the all supported Cortex-A processors and various compiler vendors.\nRefer to the list of \\ref tested_tools_sec for compliance.\n\nThese CMSIS-Core device template files include the following:\n - Register names of the Core Peripherals and names of the Core Exception Vectors.\n - Functions to access core peripherals, cache, MMU and special CPU instructions \n - Generic startup code and system configuration code.\n\nThe detailed file structure of the CMSIS-Core device templates is shown in the following picture.\n\n<!-- \\image html \"CMSIS_CORE_Files.png\" \"CMSIS-Core File Structure\" -->\n\n\\section CMSIS_Processor_files CMSIS-Core Processor Files \n\nThe CMSIS-Core processor files provided by Arm are in the directory .\\\\CMSIS\\\\Core_A\\\\Include. These header files define all processor specific attributes do not need any modifications.\nThe <b>core_&lt;cpu&gt;.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-A processor:\n\nHeader File      | Processor\n:----------------|:------------------------------\ncore_ca.h        | generics for all supported Cortex-A processors\n\n\\section device_examples Device Examples\n\nThe CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\\\\Device\\\\ARM\nand include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file <b>ARM.CMSIS.pdsc</b>:\n\nFamily             | Device            | Description\n:------------------|:------------------|:---------------------------------\nARM Cortex-A5      | ARMCA5            | Cortex-A5 based device\nARM Cortex-A7      | ARMCA7            | Cortex-A7 based device\nARM Cortex-A9      | ARMCA9            | Cortex-A9 based device\n\n\n\n\\section template_files_sec Template Files\n\nTo simplify the creation of CMSIS-Core device files, the following template files are provided that should be extended by the silicon vendor to reflect the actual device and device peripherals.\nSilicon vendors add to these template files the following information:\n - <b>Device Peripheral Access Layer</b> that provides definitions for device-specific peripherals.\n - <b>Access Functions for Peripherals</b> (optional) that provides additional helper functions to access device-specific peripherals.\n - <b>Interrupt vectors</b> in the startup file that are device specific.\n\n<table class=\"cmtable\">\n    <tr>\n      <th>Template File</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device_A\\\\Source\\\\ARM\\\\startup_Device.c</td>\n      <td>Startup file template for Arm C/C++ Compiler.</td>\n    </tr>   \n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device_A\\\\Source\\\\ARM\\\\Device.sct</td>\n      <td>Linker scatter file template for Arm C/C++ Compiler.</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device_A\\\\Source\\\\system_Device.c</td>\n      <td>Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system).</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device_A\\\\Source\\\\mmu_Device.c</td>\n      <td>Sample mmu_Device.c file with memory map description for Memory Management Unit (MMU) configuration.</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device_A\\\\Include\\\\Device.h</td>\n      <td>Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals\n      can be part of that file.</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device_A\\\\Include\\\\system_Device.h</td>\n      <td>Generic system device configuration include file.</td>\n    </tr>\n    <tr>\n      <td>.\\\\Device\\\\\\_Template_Vendor\\\\Vendor\\\\Device_A\\\\Include\\\\mem_Device.h</td>\n      <td>Generic memory base address and size definitions used in scatter file. Settable via Configuration Wizard.</td>\n    </tr>\n</table>\n\n\n<b>Adapt Template Files to a Device</b>\n\nThe following steps describe how to adopt the template files to a specific device or device family.\nCopy the complete all files in the template directory and replace:\n  - directory name 'Vendor' with the abbreviation for the device vendor  e.g.: NXP.\n  - directory name 'Device' with the specific device name e.g.: LPC17xx.\n  - in the file names 'Device' with the specific device name e.g.: LPC17xx.\n\nEach template file contains comments that start with \\b ToDo: that describe a required modification.\nThe template files contain place holders:\n\n<table class=\"cmtable\">\n    <tr>\n      <th>Placeholder</th>\n      <th>Replaced with</th>\n    </tr>\n    <tr>\n      <td>&lt;Device&gt;</td>\n      <td>the specific device name or device family name; i.e. LPC17xx.</td>\n    </tr>\n    <tr>\n      <td>&lt;DeviceInterrupt&gt;</td>\n      <td>a specific interrupt name of the device; i.e. TIM1 for Timer 1.</td>\n    <tr>\n      <td>&lt;DeviceAbbreviation&gt;</td>\n      <td>short name or abbreviation of the device family; i.e. LPC.</td>\n    </tr>\n    <tr>\n      <td>Cortex-M#</td>\n      <td>the specific Cortex-M processor name; i.e. Cortex-M3.</td>\n    </tr>\n</table>\n\n\nThe device configuration of the template files is described in detail on the following pages:\n  - \\subpage startup_c_pg\n  - \\subpage system_c_pg\n  - \\subpage device_h_pg\n  - \\subpage mem_h_pg\n  - \\subpage mmu_c_pg\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page startup_c_pg Startup File startup_<device>.c\n\nThe \\ref startup_c_pg contains:\n - Exception vectors of the Cortex-A Processor with weak functions that implement default routines.\n - The reset handler which is executed after CPU reset and typically calls the \\ref SystemInit function.\n - The setup values for the various stack pointers, i.e. per exceptional mode and main stack.\n\nThe file exists for each supported toolchain and is the only tool-chain specific CMSIS file.\n\n\\section startup_c_sec startup_Device.c Template File\n\nAn Arm Compiler specific startup file for an Armv7-A processor like Cortex-A9 is shown below.\nThe files for other compiler vendors differ slightly in the syntax, but not in the overall structure.\n\n\\verbinclude \"Source/ARM/startup_Device.c\"\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page system_c_pg System Configuration Files system_<device>.c and system_<device>.h\n\nThe \\ref system_c_pg provides as a minimum the functions described under \\ref system_init_gr.\nThese functions are device specific and need adaptations. In addition, the file might have\nconfiguration settings for the device such as XTAL frequency or PLL prescaler settings.\n\nFor devices with external memory BUS the system_<device>.c also configures the BUS system.\n\nThe silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file.\nIn case of additional features the function prototypes need to be added to the system_<device>.h header file.\n\n\\section system_Device_sec system_Device.c Template File\n\nThe \\ref system_Device_sec for the Cortex-M3 is shown below.\n\n\\verbinclude \"Source/system_Device.c\"\n\n\\section system_Device_h_sec system_Device.h Template File\n\nThe system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file.\nThe \\ref system_Device_h_sec is shown below.\n\n\\verbinclude \"Include/system_Device.h\"\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page device_h_pg Device Header File \\<device.h>\n\nThe \\ref device_h_pg contains the following sections that are device specific:\n - \\ref irqn_defs provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.\n - \\ref config_perifs reflect the features of the device.\n - \\ref access_perifs definitions for the \\ref peripheral_gr to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.\n - <b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.\n\n<a href=\"modules.html\">\\b Reference </a> describes the standard features and functions of the \\ref device_h_pg in detail.\n\n\\section interrupt_number_sec Interrupt Number Definition\n\n\\ref device_h_pg contains the enumeration \\ref IRQn_Type that defines all exceptions and interrupts of the device.\nFor devices implementing an Arm GIC these are defined as:\n  - IRQn 0-15 represents software generated interrupts (SGI), local to each processor core.\n  - IRQn 16-31 represents private peripheral interrupts (PPI), local to each processor core.\n  - IRQn 32-1019 represents shared peripheral interrupts (SPI), routable to all processor cores.\n  - IRQn 1020-1023 represents special interrupts, refer to the GIC Architecture Specification.\n  \n\\b Example:\n\nThe following example shows the extension of the interrupt vector table for Cortex-A9 class device.\n\n\\code\ntypedef enum IRQn\n{\n/******  SGI Interrupts Numbers                 ****************************************/\n  SGI0_IRQn            =  0,      \n  SGI1_IRQn            =  1,\n  SGI2_IRQn            =  2,\n       :                  :\n  SGI15_IRQn           = 15,\n\n/******  Cortex-A9 Processor Exceptions Numbers ****************************************/\n  GlobalTimer_IRQn     = 27,        /*!< Global Timer Interrupt                        */\n  PrivTimer_IRQn       = 29,        /*!< Private Timer Interrupt                       */\n  PrivWatchdog_IRQn    = 30,        /*!< Private Watchdog Interrupt                    */\n\n/******  Platform Exceptions Numbers ***************************************************/\n  Watchdog_IRQn        = 32,        /*!< SP805 Interrupt        */\n  Timer0_IRQn          = 34,        /*!< SP804 Interrupt        */\n  Timer1_IRQn          = 35,        /*!< SP804 Interrupt        */\n  RTClock_IRQn         = 36,        /*!< PL031 Interrupt        */\n  UART0_IRQn           = 37,        /*!< PL011 Interrupt        */\n       :                  :\n       :                  :\n} IRQn_Type;\n\\endcode\n\n\\section core_config_sect Configuration of the Processor and Core Peripherals\n\nThe \\ref device_h_pg configures the Cortex-A processor and the core peripherals with <i>\\#defines</i>\nthat are set prior to including the file <b>core_<cpu>.h</b>.\n\nThe following tables list the <i>\\#defines</i> along with the possible values for each processor core.\nIf these <i>\\#defines</i> are missing default values are used.\n\n<table class=\"cmtable\">\n    <tr>\n      <th>\\#define</th>\n      <th>Value Range</th>\n      <th>Default</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>__CM0_REV</td>\n      <td>0x0000</td>\n      <td>0x0000</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>__CORTEX_A</td>\n      <td>5, 7, 9</td>\n      <td>(n/a)</td>\n      <td>Core type number</td>\n    </tr>\n    <tr>\n      <td>__FPU_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if an FPU is present or not</td>\n    </tr>\n    <tr>\n      <td>__GIC_PRESENT</td>\n      <td>0 ..1 </td>\n      <td>Defines if an GIC is present or not</td>\n      <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>\n    </tr>\n    <tr>\n      <td>__TIM_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a private timer is present or not</td>\n    </tr>\n    <tr>\n      <td>__L2C_PRESENT</td>\n      <td>0 .. 1</td>\n      <td>0</td>\n      <td>Defines if a level 2 cache controller is present or not</td>\n    </tr>\n</table>\n\n\\b Example\n\nThe following code exemplifies the configuration of the Cortex-A9 Processor and Core Peripherals.\n\n\\code\n#define __CA_REV        0x0000U    /*!< Core revision r0p0                          */\n#define __CORTEX_A           9U    /*!< Cortex-A9 Core                              */\n#define __FPU_PRESENT        1U    /*!< FPU present                                 */\n#define __GIC_PRESENT        1U    /*!< GIC present                                 */\n#define __TIM_PRESENT        0U    /*!< TIM not present                             */\n#define __L2C_PRESENT        0U    /*!< L2C not present                             */\n:\n:\n#include \"core_ca.h\"               /* Cortex-A processor and core peripherals       */\n\\endcode\n\n\n\\section core_version_sect   CMSIS Version and Processor Information\n\nDefines in the core_<i>cpu</i>.h file identify the version of the CMSIS-Core-A and the processor used.\nThe following shows the defines in the various core_<i>cpu</i>.h files that may be used in the \\ref device_h_pg\nto verify a minimum version or ensure that the right processor core is used.\n\n\\code\n#define __CA_CMSIS_VERSION_MAIN  (5U)                                 /* [31:16] CMSIS Core main version */\n#define __CA_CMSIS_VERSION_SUB   (0U)                                 /* [15:0]  CMSIS Core sub version */\n#define __CA_CMSIS_VERSION       ((__CA_CMSIS_VERSION_MAIN << 16U) | \\\n                                   __CA_CMSIS_VERSION_SUB          )  /* CMSIS Core version number */\n\\endcode\n\n\\section device_access Device Peripheral Access Layer\n\nThe \\ref device_h_pg contains for each peripheral:\n - Register Layout Typedef\n - Base Address\n - Access Definitions\n\nThe section \\ref peripheral_gr shows examples for peripheral definitions.\n\n\\section device_h_sec Device.h Template File\n\nThe silicon vendor needs to extend the Device.h template file with the CMSIS features described above.\nIn addition the \\ref device_h_pg may contain functions to access device-specific peripherals.\nThe \\ref system_Device_h_sec which is provided as part of the CMSIS specification is shown below.\n\n\\verbinclude \"Include/Device.h\"\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page mem_h_pg Memory Configuration Files mem_<device>.h\n\n\\verbinclude \"Include/mem_Device.h\"\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page mmu_c_pg Memory Management Unit Files mmu_<device>.c\n\n\\verbinclude \"Source/mmu_Device.c\"\n\n*/\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/Using.txt",
    "content": "/** \n\\page using_pg Using CMSIS in Embedded Applications\n\n\n\\details \n\nTo use the CMSIS-Core-A the following files are added to the embedded application:\n - \\ref startup_c_pg with reset handler and exception vectors.\n - \\ref system_c_pg with general device configuration (i.e. for clock and bus setup).\n - \\ref device_h_pg gives access to processor core and all peripherals.\n - \\ref mem_h_pg contains basic memory configurations.\n - \\ref mmu_c_pg contains the memory management unit setup.\n \n\\note The files \\ref startup_c_pg, \\ref system_c_pg, \\ref mem_h_pg, and \\ref mmu_c_pg may require application specific adaptations and therefore should be copied \n      into the application project folder prior configuration. The \\ref device_h_pg is included in all source files that need device access \n      and can be stored on a central include folder that is generic for all projects.\n\nThe \\ref Reset_Handler defined in \\ref startup_c_pg is executed after reset. \nThe default initialization sequence is\n - set the vector base address register (\\ref __set_VBAR),\n - set stacks for each exception mode (\\ref __set_mode, \\ref __set_SP),\n - call \\ref SystemInit.\n\nAfter the system initialization control is transferred to the C/C++ run-time\nlibrary which performs initialization and calls the \\b main function in the user code. In addition the \\ref startup_c_pg contains a weak default handler\nimplementation for every exception. It may also contain stack and heap configurations for the user application.\n\nThe \\ref system_c_pg performs the setup for the processor clock and the initialization of memory caches, memory management unit, generic interrupt interface\nand floating point unit. The variable \\ref SystemCoreClock indicates the CPU clock speed.\n\\ref system_init_gr describes the minimum feature set. In addition the file may contain functions for the memory bus setup and clock re-configuration. \n\nThe \\ref device_h_pg is the central include file that the application programmer is using in the C/C++ source code. It provides the following features:\n - \\ref peripheral_gr provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.\n - \\ref GIC_functions can be accessed with standardized symbols and functions for the General Interrupt Controller (GIC) are provided.\n - \\ref CMSIS_Core_InstructionInterface allow to access special instructions, for example for activating sleep mode or the NOP instruction.\n - \\ref PL1_timer_functions \"Generic\" and \\ref PTM_timer_functions \"Private\" Timer functions to configure and start a periodic timer interrupt.\n - \\ref L1_cache_functions \"Level 1\" and \\ref L2_cache_functions \"Level 2\" Cache controller functions to enable, disable, clean and invalidate caches.\n\nCMSIS-Pack provides the <b>\\#define CMSIS_header_file</b> in <a href=\"../../Pack/html/pdsc_components_pg.html#RTE_Components_h\"><b>RTE_Components.h</b></a> which gives you access to this <b><i>device</i>.h</b> file.\n\n\\image html \"CMSIS_CORE_A_Files_user.png\" \"CMSIS-Core-A User Files\"\n\nThe CMSIS-Core-A user files are device specific. In addition, the \\ref startup_c_pg is also compiler vendor specific. \nThe various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.\n  \n\\note The silicon vendors create these device-specific CMSIS-Core-A files based on \\ref templates_pg provide by Arm.\n\nThereafter, the functions described under <a href=\"modules.html\">\\b Reference </a> can be used in the application.\n\n\\b Examples\n - \\subpage using_CMSIS is a simple example that shows the usage of the CMSIS layer.\n - \\subpage using_ARM_pg explains how to use CMSIS-Core-M for Arm processors.\n\n\n\\page using_CMSIS Basic CMSIS Example\n\nA typical example for using the CMSIS layer is provided below. The example is based on an unspecific Cortex-A9 Device. \n    \n\\code\n#include <ARMCA9.h>                              // File name depends on device used\n \nstatic const uint32_t TICK_RATE_HZ = 1000U;\n \nuint32_t volatile msTicks;                       // Counter for millisecond Interval\n \nstatic void SysTick_Handler( void )\n{\n  msTicks++;                                     // Increment Counter\n}\n \n// We use the Private Tiemer (PTIM) of the Cortex-A9 FVP Model here.\n// In general the available Timers are highly vendor specific for Cortex-A processors.\nvoid private_timer_init(void) {\n \n  PTIM_SetLoadValue ((SystemCoreClock/TICK_RATE_HZ) - 1U);\n  PTIM_SetControl (PTIM_GetControl() | 7U);\n\n  /* Install SysTick_Handler as the interrupt function for PTIM */\n  IRQ_SetHandler((IRQn_ID_t)PrivTimer_IRQn, SysTick_Handler);\n \n  /* Determine number of implemented priority bits */\n  IRQ_SetPriority ((IRQn_ID_t)PrivTimer_IRQn, IRQ_PRIORITY_Msk);\n \n  /* Set lowest priority -1 */\n  IRQ_SetPriority ((IRQn_ID_t)PrivTimer_IRQn, GIC_GetPriority((IRQn_ID_t)PrivTimer_IRQn)-1);\n \n  /* Enable IRQ */\n  IRQ_Enable ((IRQn_ID_t)PrivTimer_IRQn);\n}\n\n/* Delay execution for given amount of ticks */\nvoid Delay(uint32_t ticks)  {\n  uint32_t tgtTicks = msTicks + ticks;             // target tick count to delay execution to\n  while (msTicks == tgtTicks)  {\n    __WFE ();                                      // Power-Down until next Event/Interrupt\n  }\n}\n \n/* main function */\nint main(void)\n{\n  /* Initialize device HAL here */\n  private_timer_init();\n \n  static uint8_t ledState = 0;\n \n  /* Infinite loop */\n  while (1)\n  {\n    /* Add application code here */\n    ledState = !ledState;\n    Delay(500);\n  }\n}\n\\endcode\n\nCMSIS-Pack provides the <b>\\#define CMSIS_header_file</b> in <a href=\"../../Pack/html/pdsc_components_pg.html#RTE_Components_h\"><b>RTE_Components.h</b></a> which gives you access to the <b><i>device</i>.h</b> file \nof a project. This allows you to generate generic software components that use the device selected in a project.\n\n\\code\n#include \"RTE_Components.h\"     // include information about project configuration\n#include CMSIS_device_header    // include <device>.h file\n\\endcode\n    \n\\page using_ARM_pg Using CMSIS with generic Arm Processors\n\nArm provides CMSIS-Core-A files for the supported Arm Processors and for various compiler vendors. \nThese files can be used when standard Arm processors should be used in a project.\nThe table below lists the folder and device names of the Arm processors.\n  \n<table class=\"cmtable\">\n  <tr>\n    <th>Folder</th>\n    <th>Processor</th>\n    <th>Description</th>\n  </tr>\n  <tr>\n    <td>\".\\Device\\ARM\\ARMCA5\"</td>\n    <td>Cortex-A5</td>\n    <td>Contains \\b Include and \\b Source template files configured for the Cortex-A5 processor.\n        The device name is ARMCA5 and the name of the \\ref device_h_pg is <ARMCA5.h>.\n    </td>\n  </tr>\n  <tr>\n    <td>\".\\Device\\ARM\\ARMCA7\"</td>\n    <td>Cortex-A7</td>\n    <td>Contains \\b Include and \\b Source template files configured for the Cortex-A7 processor.\n        The device name is ARMCA7 and the name of the \\ref device_h_pg is <ARMCA7.h>.\n    </td>\n  </tr>\n  <tr>\n    <td>\".\\Device\\ARM\\ARMCA9\"</td>\n    <td>Cortex-A9</td>\n    <td>Contains \\b Include and \\b Source template files configured for the Cortex-A9 processor.\n        The device name is ARMCA9 and the name of the \\ref device_h_pg is <ARMCA9.h>.\n    </td>\n  </tr>\n</table>\n\n\\note\nCMSIS-Pack provides the <b>\\#define CMSIS_header_file</b> in <a href=\"../../Pack/html/pdsc_components_pg.html#RTE_Components_h\"><b>RTE_Components.h</b></a> which gives you access to the <b><i>device</i>.h</b> file \nof a project. This allows you to generate generic software components that adjust to the device settings.\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/cmsis_armcc.txt",
    "content": "/**************************************************************************//**\n * @file     cmsis_armcc.txt\n * @brief    CMSIS compiler specific macros, functions, instructions\n * @version  V1.00\n * @date     22. Feb 2017\n ******************************************************************************/\n/* CMSIS compiler control architecture macros */\n/**\n\\defgroup comp_cntrl_gr Compiler Control\n\\brief Compiler agnostic \\#define symbols for generic C/C++ source code\n\\details\nThe CMSIS-Core provides the header file \\b cmsis_compiler.h with consistent \\#define symbols to generate C or C++ source files that should be compiler agnostic.\nEach CMSIS compliant compiler should support the functionality described in this section.\n@{\n*/\n\n/**\n\\def __ARMCC_VERSION\n*/\n\n/**\n\\def __ARM_ARCH_7A__    \n\\brief Set to 1 when generating code for Armv7-A (Cortex-A7)\n\\details\nThe \\b \\#define __ARM_ARCH_7A__ is set to 1 when generating code for the Armv7-A architecture. This architecture is for example used by the Cortex-A7 processor.\n*/\n\n/**      \n\\def __ASM           \n\\brief Pass information from the compiler to the assembler.\n\\details\nThe \\b __ASM keyword can declare or define an embedded assembly function or incorporate inline assembly into a function\n(shown in the code example below).\n \n<b>Code Example:</b>\n\\code\n// Reverse bit order of value\n \n__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n \n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n   return(result);\n}\n\\endcode\n*/\n\n/**        \n\\def __INLINE         \n\\brief Recommend that function should be inlined by the compiler.\n\\details\nInline functions offer a trade-off between code size and performance. By default, the compiler decides during optimization whether to\ninline code or not. The \\b __INLINE attribute gives the compiler an hint to inline this function. \nStill, the compiler may decide not to inline the function. As the function is global an callable function is also generated. \n\n<b> Code Example:</b>\n\\code\nconst uint32_t led_mask[] = {1U << 4, 1U << 5, 1U << 6, 1U << 7};\n \n//------------------------------------------------------------------------------\n// Switch on LEDs\n//------------------------------------------------------------------------------\n__INLINE static void LED_On (uint32_t led) {\n \n  PTD->PCOR   = led_mask[led];\n}\n\\endcode\n*/\n\n/**\n\\def __STATIC_INLINE  \n\\brief Define a static function should be inlined by the compiler.\n\\details\nDefines a static function that may be inlined by the compiler. If the compiler generates inline code for \nall calls to this functions, no additional function implementation is generated which may further optimize space.\n\n<b> Code Example:</b>\n\\code\n__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)\n{\n  return((uint32_t)GICDistributor->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)]);\n}\n\\endcode\n*/\n\n/**************************************************************************************************/\n/**\n\\def __STATIC_FORCEINLINE\n\\brief Define a static function that should be always inlined by the compiler.\n\\details\nDefines a static function that should be always inlined by the compiler. \n\n\\note\nFor compilers that do not allow to force function inlining, the macro maps to \\ref __STATIC_INLINE.\n\n<b> Code Example:</b>\n\\code\n\\\\ Get Interrupt Vector\n__STATIC_FORCEINLINE uint32_t NVIC_GetVector(IRQn_Type IRQn)\n{\n    uint32_t *vectors = (uint32_t *)SCB->VTOR;\n    return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\\endcode\n\n*/\n#define __STATIC_FORCEINLINE\n\n/**  \n\\def __NO_RETURN             \n\\brief Inform the compiler that a function does not return.\n\\details\nInforms the compiler that the function does not return. The compiler can then perform optimizations by\nremoving code that is never reached.\n \n<b> Code Example:</b>\n\\code\n// OS idle demon (running when no other thread is ready to run).\n \n__NO_RETURN void os_idle_demon (void);\n\\endcode\n*/\n\n/**\n\\def __USED     \n\\brief Inform that a variable shall be retained in executable image.\n\\details\nDefinitions tagged with \\b __USED in the source code should be not removed by the linker when detected as unused.\n \n<b> Code Example:</b>\n\\code\n// Export following variables for debugging \n__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;\n__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;\n__USED uint32_t const os_clockrate = OS_TICK;\n__USED uint32_t const os_timernum  = 0;\n\\endcode\n**/\n\n/**             \n\\def __WEAK                  \n\\brief Export a function or variable weakly to allow overwrites.\n\\details\nFunctions defined with \\b __WEAK export their symbols weakly. A function defined weak behaves like a normal defined\nfunction unless a non-weak function with the same name is linked into the same image. If both a non-weak\nfunction and a weak defined function exist in the same image, then all calls to the function resolve to the non-weak\nfunction.\n\nFunctions declared with \\b __WEAK and then defined without \\b __WEAK behave as non-weak functions.\n \n<b> Code Example:</b>\n\\code\n__WEAK void SystemInit(void)\n{\n  SystemCoreSetup();\n  SystemCoreClockSetup(); \n}\n\\endcode\n*/\n\n/**\n\\def __ALIGNED(x)  \n\\brief Minimum alignment for a variable.\n\\details\nSpecifies a minimum alignment for a variable or structure field, measured in bytes.\n \n<b> Code Example:</b>\n\\code\nuint32_t stack_space[0x100] __ALIGNED(8);   // 8-byte alignment required\n\\endcode\n*/\n\n/**\n\\def __PACKED   \n\\brief Request smallest possible alignment.\n\\details\nSpecifies that a type must have the smallest possible alignment.\n \n<b> Code Example:</b>\n\\code\nstruct foo {\n  uint8_t  u8;\n  uint32_t u32[2] __PACKED;\n};\n\\endcode\n*/\n/**************************************************************************************************/\n/**\n\\def __PACKED_STRUCT\n\\brief Request smallest possible alignment for a structure.\n\\details\nSpecifies that a structure must have the smallest possible alignment.\n \n<b> Code Example:</b>\n\\code\n__PACKED_STRUCT foo {\n  uint8_t   u8;\n  uint32_t  u32;\n  uint16_t  u16;\n};\n\\endcode\n\n*/\n#define __PACKED_STRUCT\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT32\n\\brief Pointer for unaligned access of a uint32_t variable.\n\\deprecated\nDo not use this macro.\nIt has been superseded by \\ref __UNALIGNED_UINT32_READ, \\ref __UNALIGNED_UINT32_WRITE and will be removed in the future.\n\\details\nDefines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n \n<b> Code Example:</b>\n\\code\nuint32_t val32;\n \nvoid test (uint8_t *ptr) {\n  __UNALIGNED_UINT32(ptr) = val32;\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT32\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT16_READ\n\\brief Pointer for unaligned read of a uint16_t variable.\n\\details\nDefines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in read\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n \n<b> Code Example:</b>\n\\code\nuint16_t val16;\n \nvoid test (uint8_t *ptr) {\n   val16 = __UNALIGNED_UINT16_READ(ptr);\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT16_READ\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT16_WRITE\n\\brief Pointer for unaligned write of a uint16_t variable.\n\\details\nDefines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in write\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n \n<b> Code Example:</b>\n\\code\nuint16_t val16 = 0U;\n \nvoid test (uint8_t *ptr) {\n   __UNALIGNED_UINT16_WRITE(ptr, val16);\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT16_WRITE\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT32_READ\n\\brief Pointer for unaligned read of a uint32_t variable.\n\\details\nDefines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n \n<b> Code Example:</b>\n\\code\nuint32_t val32;\n \nvoid test (uint8_t *ptr) {\n   val32 = __UNALIGNED_UINT32_READ(ptr);\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT32_READ\n\n/**************************************************************************************************/\n/**\n\\def __UNALIGNED_UINT32_WRITE\n\\brief Pointer for unaligned write of a uint32_t variable.\n\\details\nDefines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in write\noperations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm\nprocessor core and compiler settings.\n \n<b> Code Example:</b>\n\\code\nuint32_t val32 = 0U;\n \nvoid test (uint8_t *ptr) {\n   __UNALIGNED_UINT32_WRITE(ptr, val32);\n}\n\\endcode\n\n*/\n#define __UNALIGNED_UINT32_WRITE\n\n/**\n@}\n*/\n/* end group comp_cntrl_gr */\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \n\\defgroup CMSIS_Core_InstructionInterface Intrinsic Functions \n\\brief Functions that generate specific Cortex-A CPU Instructions\n@{\n*/\n\n/**\n\\def __NOP                         \n\\details No Operation does nothing. This instruction can be used for code alignment purposes.\n\n\n\\def __WFI                         \n\\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n\n\\def __WFE                         \n\\details Wait For Event is a hint instruction that permits the processor to enter\n\n\\def __SEV                         \n\\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n\n\\def __ISB()\n\\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n\n\\def __DSB()\n\\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n\n\\def __DMB()\n\\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n\n\\def __BKPT(value) \n\\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n*/\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\nuint32_t __REV(uint32_t value);\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\nuint16_t __REV16(uint16_t value);\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\nint32_t __REVSH(int32_t value);\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\nuint32_t __ROR(uint32_t op1, uint32_t op2);\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\nuint32_t __RBIT(uint32_t value);\n\n/**\n  \\brief   \tCount leading zeros.\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]    value  Value to count the leading zeros\n  \\return               number of leading zeros in value\n */\nuint8_t __CLZ(uint32_t value);\n\n/** @}*/ \n/* end of group CMSIS_Core_InstructionInterface */\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/cmsis_compiler.txt",
    "content": "/**************************************************************************//**\n * @file     cmsis_compiler.txt\n * @brief    CMSIS compiler specific macros, functions, instructions\n * @version  V1.00\n * @date     22. Feb 2017\n ******************************************************************************/\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/core_ca.txt",
    "content": "/**************************************************************************//**\n * @file     core_ca.txt\n * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File\n ******************************************************************************/\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n\\defgroup   peripheral_gr    Peripheral Access\n\\brief      Naming conventions and optional features for accessing peripherals.\n\\details\nThe section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals.\nMost of the rules also apply to the core peripherals.  The \\ref device_h_pg \"Device Header File \\<device.h>\" contains typically these definition and also includes\nthe core specific header files.\n\nThe definitions for \\ref peripheral_gr can be generated using the <a href=\"../../SVD/html/index.html\"><b>CMSIS-SVD</b></a> System View Description for Peripherals.\nRefer to <a href=\"../../SVD/html/svd_SVDConv_pg.html\"><b>SVDConv.exe</b></a> for more information.\n\t\nEach peripheral provides a data type definition with a name that is composed of:\n  - an optional prefix <b>&lt;<i>device abbreviation&gt;</i>_</b>\n  - <b>&lt;<i>peripheral name</i>&gt;</b>\n  - postfix \\b _Type or \\b _TypeDef to identify a type definition.\n\nExamples:\n  - \\b UART_TypeDef for the peripheral \\b UART.\n  - \\b IMX_UART_TypeDef for the device family \\b IMX and the peripheral \\b UART.\n\nThe data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.\n \n - IO Type Qualifiers are used to specify the access to peripheral variables.\n   IO Type Qualifier  | Type            | Description\n   :------------------|:----------------|:------------\n   \\b __IM            | Struct member   | Defines 'read only' permissions\n   \\b __OM            | Struct member   | Defines 'write only' permissions\n   \\b __IOM           | Struct member   | Defines 'read / write' permissions\n   \\b __I             | Scalar variable | Defines 'read only' permissions\n   \\b __O             | Scalar variable | Defines 'write only' permissions\n   \\b __IO            | Scalar variable | Defines 'read / write' permissions\n   \nThe typedef <b>\\<<i>device abbreviation</i>\\>_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.\n\n\\code\ntypedef struct {\n\t__O  uint32_t UART_CR;            // Offset: 0x0000 ( /W) Control Register \n\t__IO uint32_t UART_MR;            // Offset: 0x0004 (R/W) Mode Register \n\t__O  uint32_t UART_IER;           // Offset: 0x0008 ( /W) Interrupt Enable Register \n\t__O  uint32_t UART_IDR;           // Offset: 0x000C ( /W) Interrupt Disable Register \n\t__I  uint32_t UART_IMR;           // Offset: 0x0010 (R/ ) Interrupt Mask Register \n\t__I  uint32_t UART_SR;            // Offset: 0x0014 (R/ ) Status Register \n\t__I  uint32_t UART_RHR;           // Offset: 0x0018 (R/ ) Receive Holding Register \n\t__O  uint32_t UART_THR;           // Offset: 0x001C ( /W) Transmit Holding Register \n\t__IO uint32_t UART_BRGR;          // Offset: 0x0020 (R/W) Baud Rate Generator Register \n\t__IO uint32_t UART_CMPR;          // Offset: 0x0024 (R/W) Comparison Register \n\t__IO uint32_t UART_RTOR;          // Offset: 0x0028 (R/W) Receiver Time-out Register \n\t__I  uint32_t RESERVED[46];       // Offset: 0x002C (R/ ) Reserved                     \n\t__IO uint32_t UART_WPMR;          // Offset: 0x00E4 (R/W) Write Protection Mode Register \n} IMX_UART_TypeDef;\n\\endcode\n\nTo access the registers of the UART defined above, pointers to this register structure are defined.\nIf more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.\n\n\\b Example:\nIn this example, \\b IMX_UART2 and \\b IMX_UART3 are two pointers to UARTs defined with above register structure.\n\\n\n\\code\n#define IMX_UART2   ((IMX_UART_TypeDef *) IMX_UART2_BASE)\n#define IMX_UART3   ((IMX_UART_TypeDef *) IMX_UART3_BASE)\n\\endcode\n\n\\note \n - The prefix <b>IMX</b> is optional.\n \nThe registers in the various UARTs can now be referred in the user code as shown below:\\n\n\\code\n val = IMX_UART2->SR   // is the Status Register of UART2.\n\\endcode\n\n<hr>\n\n\\section core_cmsis_pal_min_reqs Minimal Requirements\n\\details\n To access the peripheral registers and related function in a device, the files <b><i>device.h</i></b> and <b>core_ca.h</b> define as a minimum:\n\\n\\n\n- The <b>Register Layout Typedef</b> for each peripheral that defines all register names.\n  RESERVED is used to introduce space into the structure for adjusting the addresses of\n  the peripheral registers.\n\\n\\n\n<b>Example:</b>\n\\code\ntypedef struct\n{\n  __IOM uint32_t C_CTLR;              // Offset: 0x0000 (R/W) CPU Interface Control Register \n  __IOM uint32_t C_PMR;               // Offset: 0x0004 (R/W) Interrupt Priority Mask Register \n  __IOM uint32_t C_BPR;               // Offset: 0x0008 (R/W) Binary Point Register \n  __IM  uint32_t C_IAR;               // Offset: 0x000C (R/ ) Interrupt Acknowledge Register \n  __OM  uint32_t C_EOIR;              // Offset: 0x0010 ( /W) End Of Interrupt Register \n  __IM  uint32_t C_RPR;               // Offset: 0x0014 (R/ ) Running Priority Register \n  __IM  uint32_t C_HPPIR;             // Offset: 0x0018 (R/ ) Highest Priority Pending Interrupt Register \n  __IOM uint32_t C_ABPR;              // Offset: 0x001C (R/W) Aliased Binary Point Register \n  __IM  uint32_t C_AIAR;              // Offset: 0x0020 (R/ ) Aliased Interrupt Acknowledge Register \n  __OM  uint32_t C_AEOIR;             // Offset: 0x0024 ( /W) Aliased End Of Interrupt Register \n  __IM  uint32_t C_AHPPIR;            // Offset: 0x0028 (R/ ) Aliased Highest Priority Pending Interrupt Register \n  __IOM uint32_t C_STATUSR;           // Offset: 0x002C (R/W) Error Reporting Status Register, optional \n  __I   uint32_t RESERVED1[40];       // Offset: 0x0030 (R/ ) Reserved\n  __IOM uint32_t C_APR[4];            // Offset: 0x00D0 (R/W) Active Priority Register \n  __IOM uint32_t C_NSAPR[4];          // Offset: 0x00E0 (R/W) Non-secure Active Priority Register \n  __I   uint32_t RESERVED2[3];        // Offset: 0x00F6 (R/ ) Reserved\n  __IM  uint32_t C_IIDR;              // Offset: 0x00FC (R/ ) CPU Interface Identification Register \n  __I   uint32_t RESERVED3[960];      // Offset: 0x0100 (R/ ) Reserved\n  __OM  uint32_t C_DIR;               // Offset: 0x1000 ( /W) Deactivate Interrupt Register \n}  GICInterface_Type;\n\\endcode\n\n\n- <b>Base Address</b> for each peripheral (in case of multiple peripherals\n    that use the same <b>register layout typedef</b> multiple base addresses are defined).\n    \\n\\n\n<b>Example:</b>\n\\code\n#define GIC_INTERFACE_BASE (0xe8202000UL)   // GIC Interface Base Address     \n\\endcode\n\n\n- <b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same\n    <b>register layout typedef</b>, multiple access definitions exist.\n    \\n\\n\n<b>Example:</b>\n\\code\n#define GICInterface   ((GICInterface_Type *) GIC_INTERFACE_BASE)   // GIC Interface Access Definition \n\\endcode\n\n\nThese definitions allow accessing peripheral registers with simple assignments.\n\n- <b>Example:</b>\n  \\n\n\\code\nGICInterface->C_CTLR |= 1;   // Enable Interface\n\\endcode\n\n<hr>\n\n\\section core_cmsis_pal_opts Optional Features\n\\details\nOptionally, the file <b><i>device</i>.h</b> may define:\n\n-  \\ref core_cmsis_pal_bitfields and \\#define constants that simplify access to peripheral registers.\n\tThese constants may define bit-positions or other specific patterns that are required for\n    programming peripheral registers. The identifiers should start with\n    <b>&lt;<i>device abbreviation</i>&gt;_</b> and <b>&lt;<i>peripheral name</i>&gt;_</b>.\n    It is recommended to use CAPITAL letters for \\#define constants.\n\n-   More complex functions (i.e. status query before\n    a sending register is accessed). Again, these functions start with\n    <b>&lt;<i>device abbreviation</i>&gt;_</b> and <b>&lt;<i>peripheral name</i>&gt;_</b>.\n\n<hr>\n\n\\section core_cmsis_pal_bitfields Register Bit Fields\n\\details\n\nFor Core Register, macros define the position and the mask value for a bit field.\n\n<b>Example:</b>\n\nBit field definitions for register ACTLR in CP15.\n\n\n\\code\n// CP15 Register ACTLR\n#define ACTLR_DDI_Pos                  28U                       \n#define ACTLR_DDI_Msk                  (1UL << ACTLR_DDI_Pos)    \n                                       \n#define ACTLR_DDVM_Pos                 15U                       \n#define ACTLR_DDVM_Msk                 (1UL << ACTLR_DDVM_Pos)   \n                                       \n#define ACTLR_L1PCTL_Pos               13U                       \n#define ACTLR_L1PCTL_Msk               (3UL << ACTLR_L1PCTL_Pos) \n                                       \n#define ACTLR_L1RADIS_Pos              12U                       \n#define ACTLR_L1RADIS_Msk              (1UL << ACTLR_L1RADIS_Pos)\n                                       \n#define ACTLR_L2RADIS_Pos              11U                       \n#define ACTLR_L2RADIS_Msk              (1UL << ACTLR_L2RADIS_Pos)\n                                       \n#define ACTLR_DODMBS_Pos               10U                       \n#define ACTLR_DODMBS_Msk               (1UL << ACTLR_DODMBS_Pos) \n                                       \n#define ACTLR_SMP_Pos                  6U                        \n#define ACTLR_SMP_Msk                  (1UL << ACTLR_SMP_Pos)     \n\\endcode\n\nThe macros <b>_VAL2FLD(field, value)</b> and <b>_FLD2VAL(field, value)</b> enable access to bit fields.\n@{\n*/\n\n/**\n\\def _VAL2FLD(field, value)\n\\param         field        name of bit field.\n\\param         value        value for the bit field. This parameter is interpreted as an uint32_t type.\n\\brief Mask and shift a bit field value for assigning the result to a peripheral register.\n\\details\nThe macro \\ref _VAL2FLD uses the \\#define's <i>_Pos</i> and <i>_Msk</i> of the related bit field to shift bit-field values for\nassigning to a register.\n \n<b>Example:</b>\n\\code\n  ACTLR = _VAL2FLD(ACTLR_SMP, 0x1)\n\\endcode\n\n*/\n#define _VAL2FLD(field, value)\n\n/**\n \n\\def _FLD2VAL(field, value)\n\\param         field        name of bit field.\n\\param         value        value of the register. This parameter is interpreted as an uint32_t type.\n\\brief Extract from a peripheral register value the a bit field value.\n\\details\nThe macro \\ref _FLD2VAL uses the \\#define's <i>_Pos</i> and <i>_Msk</i> of the related bit field to extract the value of a bit field from a register.\n \n<b>Example:</b>\n\\code\n  i = _FLD2VAL(ACTLR_SMP, ACTLR);\n\\endcode\n\n*/\n#define _FLD2VAL(field, value)\n\n/** @} */ \n/*end of group peripheral_gr */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n\\defgroup version_ctrl Version Control\n\\brief Version symbols for CMSIS release specific C/C++ source code. \n \n@{\n*/\n\n/*  CMSIS CA definitions */\n/**\n\\def __CA_CMSIS_VERSION_MAIN  \n\\details\nUse this define to query the major version of CMSIS-Core(A) component. \n\n\\b Example:\n\\code\n#if __CA_CMSIS_VERSION_MAIN < 5\n#error This code needs at least CMSIS-Core(A) version 5!\n#endif\n\\endcode\n\n\\def __CA_CMSIS_VERSION_SUB   \n\\details\nUse this define to query the minor version of CMSIS-Core(A) component. \n\n\\b Example:\n\\code\n#if __CA_CMSIS_VERSION_MAIN < 5\n#error This code needs at least CMSIS-Core(A) version 5!\n#else\n#if __CA_CMSIS_VERSION_SUB < 1\n#warning Using CMSIS-Core(A) version 5.0 compatibility functions.\n#endif\n#endif\n\\endcode\n\n\\def __CA_CMSIS_VERSION       \n\\details\nUse this define to query the full version of CMSIS-Core(A) component. \n\n| Bits    | Name          | Function                |\n| :------ | :------------ | :-----------------------|\n| [31:16] | MAIN          | __CA_CMSIS_VERSION_MAIN |\n| [15:0]  | SUB           | __CA_CMSIS_VERSION_SUB  |\n\n\n\\b Example:\n\\code\n#if __CA_CMSIS_VERSION < 0x00050001\n#error This code needs at least CMSIS-Core(A) version 5.1!\n#endif\n\\endcode\n\n\\def __CA_REV\n\\brief Contains the core revision for a Cortex-A class device.\n\\details\nUse this define to query the core design revision number implemented in the selected device.\n\n| Bits    | Name          | Function        |\n| :------ | :------------ | :---------------|\n| [15:8]  | REV           | Revision number |\n| [7:0]   | PATCH         | Patch number    |\n\n\\b Example:\n\\code\n#if __CA_REV < 0x0201\n#error This code needs at least a core revision r2p1.\n#endif\n\\endcode\n\n\\def __CORTEX_A\n\\brief Contains the core family for a Cortex-A class device.\n\\details\nUse this define to query the actual Cortex-A class device number implemented in the selected device.\n\n\\b Example:\n\\code\n#if __CORTEX_A == 5\n#warning Running on Cortex-A5.\n#elif __CORTEX_A == 7\n#warning Running on Cortex-A7.\n#elif __CORTEX_A == 9\n#warning Running on Cortex-A9.\n#endif\n\\endcode\n\n*/\n/** @} */ \n/*end of group version_ctrl */\n\n/**\n\\defgroup CMSIS_Core_FunctionInterface Core Peripherals\n\\brief \n\\details\nHardware Abstraction Layer.\n   The Core-A function interface contains:\n   - \\ref FPU_functions\n   - \\ref GIC_functions\n   - \\ref L1_cache_functions \n   - \\ref L2_cache_functions \n   - \\ref MMU_functions\n   - \\ref PL1_timer_functions\n   - \\ref PTM_timer_functions\n\n*/\n\n/* ##########################  FPU functions  ############################ */\n/**\n\\defgroup FPU_functions Floating Point Unit Functions\n\\ingroup CMSIS_Core_FunctionInterface\n\\brief FPU Functions enable the use of Floating Point instructions and extensions.\\n\nReference: <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html\">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>.\n@{\n\\fn __STATIC_INLINE __ASM void __FPU_Enable(void) \n@}\n*/\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/irq_ctrl.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== IRQ Controller API ====\n/** \n\\defgroup irq_ctrl_gr Interrupts and Exceptions\n\\brief Generic functions to access the Interrupt Controller.\n\n\\details This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers.\nThe IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers.\n\n\\note The default implementation for \\ref GIC_functions \"Arm GIC (Generic Interrupt Controller)\" can be found in \\ref irq_ctrl_gic.c.\nIt uses \\c weak functions thus it can easily be overwritten by an alternative user implementation if needed.\n\nThe Armv7-A architecture defines a common set of first level exceptions, see table below.\n\n| Exception                     | CMSIS Handler | Offset | Description                                                                 |\n|-------------------------------|---------------|--------|-----------------------------------------------------------------------------|\n| Reset                         | Reset_Handler | 0x0000 | First instruction executed after reset.                                     |\n| Undefined Instruction (Undef) | Undef_Handler | 0x0004 | Signals usage of an illegal instructions.                                   |\n| Supervisor Call (SVC)         | SVC_Handler   | 0x0008 | Issued by software using SVC instruction.                                   |\n| Prefetch Abort (PAbt)         | PAbt_Handler  | 0x000C | Signals a memory abort on istruction fetch.                                 |\n| Data Abort (DAbt)             | DAbt_Handler  | 0x0010 | Signals a memory abort on data read or write.                               |\n| Hyp Trap                      | (NOP)         | 0x0014 | Hypervisor instruction trap, only available with Virtualization Extensions. |\n| IRQ interrupt                 | IRQ_Handler   | 0x0018 | Interrupt Request (typically from Interrupt Controller)                     |\n| FIQ interrupt                 | FIQ_Handler   | 0x001C | Fast Interrupt Request (typically from Interrupt Controller)                |\n\nBy default those handlers are defined as weak empty functions by the \\ref startup_c_sec \"device specific startup code\".\nSoftware and peripheral interrupts are all handled by one of the both central interrupt handlers (IRQ and FIQ). These needs to\nbe implemented application specific. If an RTOS is used the interrupt handlers are typically provided by the RTOS, e.g. when using \n<a href=\"../../RTOS2/html/rtx5_impl.html\">RTX5</a>.\n\nThe interrupts available depends on the actual device in use. According to CMSIS specification the interrupts are defined\nas \\ref IRQn_Type in \\ref device_h_pg. Using the generic IRQ API one can easily enable and disable interrupts, set up priorities, modes \nand preemption rules, and register interrupt callbacks.\n\n\\b Example:\n\n\\code\nvoid SGI0_Handler() {\n  /* \n   * Handle Interrupt \n   */\n  \n  IRQ_ClearPending((IRQn_ID_t)SGI0_IRQn);\n}\n \nvoid main() {\n  /* Initialize the Interrupt Controller */\n  IRQ_Initialize();\n  \n  /* Register the user defined handler function */\n  IRQ_SetHandler((IRQn_ID_t)SGI0_IRQn, SGI0_Handler);  \n  \n  /* Set the priority considering the priority grouping */\n  const uint32_t subprio = IRQ_GetPriorityGroupBits();\n  IRQ_SetPriority((IRQn_ID_t)SGI0_IRQn, 1u << subprio);\n  \n  /* Set interrupt mode to falling edge */\n  IRQ_SetMode((IRQn_ID_t)SGI0_IRQn, IRQ_MODE_TYPE_IRQ | IRQ_MODE_CPU_0 | IRQ_MODE_TRIG_EDGE | IRQ_MODE_TRIG_EDGE_FALLING);\n  \n  IRQ_Enable((IRQn_ID_t)SGI0_IRQn);\n  \n  /* Trigger interrupt */\n  IRQ_SetPending((IRQn_ID_t)SGI0_IRQn);\n  \n  IRQ_Disable((IRQn_ID_t)SGI0_IRQn);\n}\n\\endcode\n\n@{\n*/\n\n/**\n\\defgroup irq_mode_defs IRQ Mode Bit-Masks\n\\brief Configure interrupt line mode\n\\details\n@{\nThe following codes are used as values for the parameter \\em mode of the function \\ref IRQ_SetMode to configure interrupt line mode.\nThey are also returned by the function \\ref IRQ_GetMode when retrieving interrupt line mode.\n\nThe values of \\b IRQ_MODE_TRIG_x definitions specify\nThe values of \\b IRQ_MODE_TYPE_x definitions specify\nThe values of \\b IRQ_MODE_DOMAIN_x definitions specify\nThe values of \\b IRQ_MODE_CPU_x definitions specify\n\n// Interrupt mode bit-masks\n\\def IRQ_MODE_TRIG_LEVEL\n\\def IRQ_MODE_TRIG_LEVEL_LOW\n\\def IRQ_MODE_TRIG_LEVEL_HIGH\n\\def IRQ_MODE_TRIG_EDGE\n\\def IRQ_MODE_TRIG_EDGE_RISING\n\\def IRQ_MODE_TRIG_EDGE_FALLING\n\\def IRQ_MODE_TRIG_EDGE_BOTH\n\n\\def IRQ_MODE_TYPE_IRQ\n\\def IRQ_MODE_TYPE_FIQ\n\n\\def IRQ_MODE_DOMAIN_NONSECURE\n\\def IRQ_MODE_DOMAIN_SECURE\n\n\\def IRQ_MODE_CPU_ALL\n\\def IRQ_MODE_CPU_0\n\\def IRQ_MODE_CPU_1\n\\def IRQ_MODE_CPU_2\n\\def IRQ_MODE_CPU_3\n\\def IRQ_MODE_CPU_4\n\\def IRQ_MODE_CPU_5\n\\def IRQ_MODE_CPU_6\n\\def IRQ_MODE_CPU_7\n\n\\def IRQ_MODE_ERROR\n@}\n*/\n\n/**\n\\defgroup irq_priority_defs IRQ Priority Bit-Masks\n\\brief Definitions used by interrupt priority functions.\n\\details\n@{\nThe following values are used by the interrupt priority functions.\n\nThe value of \\b IRQ_PRIORITY_Msk specifies maximum interrupt priority value and can be used as parameter for the functions\n\\ref IRQ_GetPriority and \\ref IRQ_SetPriorityGroupBits to retrieve implementation specific priority values.\n\nThe value of \\b IRQ_PRIORITY_ERROR is used by functions \\ref IRQ_GetPriority, IRQ_GetPriorityMask and \\ref IRQ_GetPriorityGroupBits\nto signal function execution error.\n\n\\def IRQ_PRIORITY_Msk\n\\def IRQ_PRIORITY_ERROR\n@}\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_Initialize (void) \n\\details This function initializes interrupt controller.\n\nIt disables all interrupt sources, clears all pending interrupts, sets interrupt priorities to highest priority and\nconfigures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should\nbe set to NULL.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\n/// Number of implemented interrupt lines\n#ifndef IRQ_GIC_LINE_COUNT\n#define IRQ_GIC_LINE_COUNT      (1020U)\n#endif\n \nstatic IRQHandler IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };\n \nint32_t IRQ_Initialize (void) {\n  uint32_t i;\n \n  for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {\n    IRQTable[i] = (IRQHandler)NULL;\n  }\n  GIC_Enable();\n  return (0);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) \n\\details This function registers address of the interrupt handler callback function corresponding to the specified interrupt\nID number.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nint32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {\n  int32_t status;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    IRQTable[irqn] = handler;\n    status =  0;\n  } else {\n    status = -1;\n  }\n \n  return (status);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) \n\\details This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt\nID number.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nIRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {\n  IRQHandler h;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    h = IRQTable[irqn];\n  } else {\n    h = (IRQHandler_t)0;\n  }\n \n  return (h);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_Enable (IRQn_ID_t irqn)\n\\details This function enables forwarding of the corresponding interrupt to the CPU.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nint32_t IRQ_Enable (IRQn_ID_t irqn) {\n  int32_t status;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    GIC_EnableIRQ ((IRQn_Type)irqn);\n    status = 0;\n  } else {\n    status = -1;\n  }\n \n  return (status);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_Disable (IRQn_ID_t irqn)\n\\details This function disables forwarding of the corresponding interrupt to the CPU. \n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nint32_t IRQ_Disable (IRQn_ID_t irqn) {\n  int32_t status;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    GIC_DisableIRQ ((IRQn_Type)irqn);\n    status = 0;\n  } else {\n    status = -1;\n  }\n \n  return (status);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) \n\\details This function retrieves the interrupt enable status of the interrupt identified by the irqn parameter.\n\nInterrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts\nwhich cannot be identified by irqn. \n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nuint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {\n  uint32_t enable;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    enable = GIC_GetEnableIRQ((IRQn_Type)irqn);\n  } else {\n    enable = 0U;\n  }\n \n  return (enable);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode)\n\n\\details This function configures the interrupt triggering mode, type, secure access and target CPUs of the interrupt\n(see \\ref irq_mode_defs) identified by the irqn parameter.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nint32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {\n  int32_t status;\n  uint32_t val;\n  uint8_t cfg;\n  uint8_t secure;\n  uint8_t cpu;\n \n  status = 0;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    // Check triggering mode\n    val = (mode & IRQ_MODE_TRIG_Msk);\n\n    if (val == IRQ_MODE_TRIG_LEVEL) {\n      cfg = 0x00U;\n    } else if (val == IRQ_MODE_TRIG_EDGE) {\n      cfg = 0x02U;\n    } else {\n      status = -1;\n    }\n \n    // Check interrupt type\n    val = mode & IRQ_MODE_TYPE_Msk;\n \n    if (val != IRQ_MODE_TYPE_IRQ) {\n      status = -1;\n    }\n \n    // Check interrupt domain\n    val = mode & IRQ_MODE_DOMAIN_Msk;\n \n    if (val == IRQ_MODE_DOMAIN_NONSECURE) {\n      secure = 0;\n    } else {\n      // Check security extensions support\n      val = GIC_DistributorInfo() & (1UL << 10U);\n \n      if (val != 0U) {\n        // Security extensions are supported\n        secure = 1;\n      } else {\n        status = -1;\n      }\n    }\n \n    // Check interrupt CPU targets\n    val = mode & IRQ_MODE_CPU_Msk;\n \n    if (val == IRQ_MODE_CPU_ALL) {\n      cpu = 0xFF;\n    } else {\n      cpu = val >> IRQ_MODE_CPU_Pos;\n    }\n \n    // Apply configuration if no mode error\n    if (status == 0) {\n      GIC_SetConfiguration((IRQn_Type)irqn, cfg);\n      GIC_SetTarget       ((IRQn_Type)irqn, cpu);\n \n      if (secure != 0U) {\n        GIC_SetGroup ((IRQn_Type)irqn, secure);\n      }\n    }\n  }\n \n  return (status);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t IRQ_GetMode (IRQn_ID_t irqn)\n\\details This function retrieves interrupt mode configuration of the interrupt identified by the irqn parameter.\n\\ref IRQ_MODE_ERROR is returned for interrupts which cannot be identified by irqn.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nuint32_t IRQ_GetMode (IRQn_ID_t irqn) {\n  uint32_t mode;\n  uint32_t val;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    mode = IRQ_MODE_TYPE_IRQ;\n \n    // Get trigger mode\n    val = GIC_GetConfiguration((IRQn_Type)irqn);\n \n    if ((val & 2U) != 0U) {\n      // Corresponding interrupt is edge triggered\n      mode |= IRQ_MODE_TRIG_EDGE;\n    } else {\n      // Corresponding interrupt is level triggered\n      mode |= IRQ_MODE_TRIG_LEVEL;\n    }\n \n    // Get interrupt CPU targets\n    mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;\n \n  } else {\n    mode = IRQ_MODE_ERROR;\n  }\n \n  return (mode);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn IRQn_ID_t IRQ_GetActiveIRQ (void)\n\\details This function retrieves the interrupt ID number of current IRQ source and acknowledges the interrupt. \n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nIRQn_ID_t IRQ_GetActiveIRQ (void) {\n  IRQn_ID_t irqn;\n \n  irqn = (IRQn_ID_t)GIC_AcknowledgePending();\n \n  return (irqn);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn IRQn_ID_t IRQ_GetActiveFIQ (void)\n\\details This function retrieves the interrupt ID number of current FIQ source and acknowledges the interrupt.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nIRQn_ID_t IRQ_GetActiveFIQ (void) {\n  // FIQ is not supported, return invalid ID\n  return ((IRQn_ID_t)-1);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn)\n\\details This function informs the interrupt controller that the interrupt service routine processing of the currently\nactive interrupt request is completed.\n\nThe parameter irqn should specify the value previously returned by the \\ref IRQ_GetActiveIRQ or \\ref IRQ_GetActiveFIQ functions.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nint32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {\n  int32_t status;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    GIC_EndInterrupt ((IRQn_Type)irqn);\n \n    if (irqn == 0) {\n      IRQ_ID0 = 0U;\n    }\n \n    status = 0;\n  } else {\n    status = -1;\n  }\n \n  return (status);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_SetPending (IRQn_ID_t irqn) \n\\details This function sets the pending status of the interrupt identified by the irqn parameter.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nint32_t IRQ_SetPending (IRQn_ID_t irqn) {\n  int32_t status;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    GIC_SetPendingIRQ ((IRQn_Type)irqn);\n    status = 0;\n  } else {\n    status = -1;\n  }\n \n  return (status);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t IRQ_GetPending (IRQn_ID_t irqn)\n\\details This function retrieves the pending status of the interrupt identified by the irqn parameter.\n\nInterrupt pending status can be either not pending (0) or pending (1). Not pending status is returned for interrupts which\ncannot be identified by irqn.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nuint32_t IRQ_GetPending (IRQn_ID_t irqn) {\n  uint32_t pending;\n \n  if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);\n  } else {\n    pending = 0U;\n  }\n \n  return (pending & 1U);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_ClearPending (IRQn_ID_t irqn) \n\\details This function clears the pending status of the interrupt identified by the irqn parameter.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nint32_t IRQ_ClearPending (IRQn_ID_t irqn) {\n  int32_t status;\n \n  if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    GIC_ClearPendingIRQ ((IRQn_Type)irqn);\n    status = 0;\n  } else {\n    status = -1;\n  }\n \n  return (status);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority)\n\\details This function sets the priority of the interrupt identified by the irqn parameter.\n\nHigher priority numbers have lower priority. The highest interrupt priority has priority value 0, while the lowest value\ndepends on the number of implemented priority levels.\n\nThe number of implemented priority bits can be determined by setting value \\ref IRQ_PRIORITY_Msk to arbitrary irqn and by\nretrieving the actual stored value with IRQ_GetPriority function.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nint32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {\n  int32_t status;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    GIC_SetPriority ((IRQn_Type)irqn, priority);\n    status = 0;\n  } else {\n    status = -1;\n  }\n \n  return (status);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t IRQ_GetPriority (IRQn_ID_t irqn) \n\\details This function retrieves the priority of the interrupt identified by the irqn parameter.\n\nThe valid priority value can be from zero (0) to the value of \\ref IRQ_PRIORITY_Msk. \\ref IRQ_PRIORITY_ERROR bit is set in\nreturned value for interrupts which cannot be identified by irqn.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nuint32_t IRQ_GetPriority (IRQn_ID_t irqn) {\n  uint32_t priority;\n \n  if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {\n    priority = GIC_GetPriority ((IRQn_Type)irqn);\n  } else {\n    priority = IRQ_PRIORITY_ERROR;\n  }\n \n  return (priority);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_SetPriorityMask (uint32_t priority) \n\\details This function sets the priority masking threshold for the current processor.\n\nIt ensures that only interrupts with a higher priority than priority threshold value are signaled to the target processor.\nFunction returns error status -1 if priority masking is not supported.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nIRQ_SetPriorityMask (uint32_t priority) {\n  GIC_SetInterfacePriorityMask (priority);\n  return (0);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t IRQ_GetPriorityMask (void)\n\\details This function retrieves the priority masking threshold for the current processor.\n\n\\ref IRQ_PRIORITY_ERROR value is returned if priority masking is not supported.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nuint32_t IRQ_GetPriorityMask (void) {\n  return GIC_GetInterfacePriorityMask();\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t IRQ_SetPriorityGroupBits (uint32_t bits)\n\\details This function sets the number of MSB priority bits used to determine whether a pending interrupt has sufficient\npriority to preempt a currently active interrupt.\n\nThe number of implemented group priority bits can be determined by setting value \\ref IRQ_PRIORITY_Msk and by retrieving the\nactual stored value with \\ref IRQ_GetPriorityGroupBits function.\nFunction returns error status -1 if priority grouping is not supported.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nint32_t IRQ_SetPriorityGroupBits (uint32_t bits) {\n  int32_t status;\n \n  if (bits == IRQ_PRIORITY_Msk) {\n    bits = 7U;\n  }\n \n  if (bits < 8U) {\n    GIC_SetBinaryPoint (7U - bits);\n    status = 0;\n  } else {\n    status = -1;\n  }\n \n  return (status);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t IRQ_GetPriorityGroupBits (void) \n\\details This function retrieves the number of MSB bits used to determine whether a pending interrupt has sufficient\npriority to preempt a currently active interrupt.\n\n\\ref IRQ_PRIORITY_ERROR value is returned when priority grouping is not supported.\n\nFor Arm GIC the default implementation looks like the following example:\n\n\\code\nuint32_t IRQ_GetPriorityGroupBits (void) {\n  uint32_t bp;\n \n  bp = GIC_GetBinaryPoint() & 0x07U;\n \n  return (7U - bp);\n}\n\\endcode\n*/\n\n/** @} */ /* group irq_ctrl_gr */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/ref_cache.txt",
    "content": "/* ##########################  L1 Cache functions  ################################# */\n\n/** \n\\defgroup L1_cache_functions L1 Cache Functions \n\\ingroup CMSIS_Core_FunctionInterface\n\\brief L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache.\n@{\n\\fn __STATIC_INLINE void L1C_EnableCaches(void) \n\\fn __STATIC_INLINE void L1C_DisableCaches(void) \n\\fn __STATIC_INLINE void L1C_EnableBTAC(void) \n\\fn __STATIC_INLINE void L1C_DisableBTAC(void) \n\\fn __STATIC_INLINE void L1C_InvalidateBTAC(void) \n\\fn __STATIC_INLINE void L1C_InvalidateICacheAll(void)\n\\fn __STATIC_INLINE void L1C_CleanDCacheMVA(void *va) \n\\fn __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) \n\\fn __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) \n\n\\fn __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) \n\\details\nGeneric mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.\n\n\\fn __STATIC_INLINE void L1C_InvalidateDCacheAll(void) \n\\fn __STATIC_INLINE void L1C_CleanDCacheAll(void) \n\\fn __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) \n\\fn __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op)\n\\details\nGeneric mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.\n\nThe parameter \\b op defines which cleaning/invalidation strategy should be used:\n - 0 - Cache is invalidated using DCISW register.\n - 1 - Cache is cleaned using DCCSW register.\n - other - Cache is invalidated and cleaned using DCCISW register.\n@}\n*/\n\n/* ##########################  L2 Cache functions  ################################# */\n\n/**\n\\defgroup L2_cache_functions L2C-310 Cache Controller Functions \n\\ingroup CMSIS_Core_FunctionInterface\n\\brief L2C-310 Cache Controller gives access to functions for level 2 cache maintenance.\\n\nReference: <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/index.html\">Level 2 Cache Controller L2C-310 Technical Reference Manual</a>.\n*/\n/** @{ */\n\n/**\n\\struct L2C_310_TypeDef\n\\def L2C_310\n\\fn __STATIC_INLINE void L2C_Sync(void) \n\\fn __STATIC_INLINE int L2C_GetID (void) \n\\fn __STATIC_INLINE int L2C_GetType (void) \n\\fn __STATIC_INLINE void L2C_InvAllByWay (void) \n\\fn __STATIC_INLINE void L2C_CleanInvAllByWay (void) \n\\fn __STATIC_INLINE void L2C_Enable(void) \n\\fn __STATIC_INLINE void L2C_Disable(void) \n\\fn __STATIC_INLINE void L2C_InvPa (void *pa) \n\\fn __STATIC_INLINE void L2C_CleanPa (void *pa) \n\\fn __STATIC_INLINE void L2C_CleanInvPa (void *pa) \n*/\n\n/** @} */\n\n/* ########################## L2C_310_TypeDef Member ########################## */\n/**\n\\var L2C_310_TypeDef::ADDRESS_FILTER_END\n\\brief \n\n\\var __IOM uint32_t L2C_310_TypeDef::ADDRESS_FILTER_START\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::AUX_CNT\n\\brief\n\n\\var __IM  uint32_t L2C_310_TypeDef::CACHE_ID\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::CACHE_SYNC\n\\brief\n\n\\var __IM  uint32_t L2C_310_TypeDef::CACHE_TYPE\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_INDEX_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_PA\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_INDEX_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_PA\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::CLEAN_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::CONTROL\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_0_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_1_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_2_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_3_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_4_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_5_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_6_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_7_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::DEBUG_CONTROL\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::EVENT_CONTROL\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER0_CONF\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER1_CONF\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_0_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_1_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_2_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_3_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_4_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_5_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_6_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_7_WAY\n\\brief\n\n\\var __OM  uint32_t L2C_310_TypeDef::INTERRUPT_CLEAR\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INTERRUPT_MASK\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INV_LINE_PA\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::INV_WAY\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::LOCK_LINE_EN\n\\brief\n\n\\var __IM  uint32_t L2C_310_TypeDef::MASKED_INT_STATUS\n\\brief\n\n\\var __IM  uint32_t L2C_310_TypeDef::RAW_INT_STATUS\n\\brief\n\n\\var __IOM uint32_t L2C_310_TypeDef::UNLOCK_ALL_BY_WAY\n\\brief\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/ref_core_register.txt",
    "content": "/* ###########################  Core Function Access  ########################### */\n/** \n\\defgroup CMSIS_core_register Core Register Access\n\\brief Functions to access the Cortex-A core registers\n\\details\n\n*/\n/* end group CMSIS_core_register */\n\n/* CP15 Register ACTLR */\n/**\n\\defgroup CMSIS_ACTLR Auxiliary Control Register (ACTLR)\n\\ingroup CMSIS_core_register\n\\brief The ACTLR provides IMPLEMENTATION DEFINED configuration and control options.\n\\details\nThe ACTLR characteristics are differs between various Armv7-A implementations.\n\n<b>Cortex-A5</b>\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:29] | -             | Reserved.                                                     |\n| [28]    | DBDI          | Disable Branch Dual Issue                                     |\n| [27:19] | -             | Reserved.                                                     |\n| [18]    | BTDIS         | Disable indirect Branch Target Address Cache (BTAC).          |\n| [17]    | RSDIS         | Disable return stack operation.                               |\n| [16:15] | BP            | Branch prediction policy.                                     |\n| [14:13] | L1PCTL        | L1 Data prefetch control.                                     |\n| [12]    | RADIS         | Disable Data Cache read-allocate mode.                        |\n| [11]    | DWBST         | Disable AXI data write bursts to Normal memory.               |\n| [10]    | DODMBS        | Disable optimized data memory barrier behavior.               |\n| [9:8]   | -             | Reserved.                                                     |\n| [7]     | EXCL          | Exclusive L1/L2 cache control.                                |\n| [6]     | SMP           | Enables coherent requests to the processor.                   |\n| [5:1]   | -             | Reserved.                                                     |\n| [0]     | FW            | Cache and TLB maintenance broadcast.                          |\n\n<b>Cortex-A7</b>\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:29] | -             | Reserved.                                                     |\n| [28]    | DDI           | Disable Dual Issue                                            |\n| [27:16] | -             | Reserved.                                                     |\n| [15]    | DDVM          | Disable Distributed Virtual Memory transactions.              |\n| [14:13] | L1PCTL        | L1 Data prefetch control.                                     |\n| [12]    | L1RADIS       | L1 Data Cache read-allocate mode disable.                     |\n| [11]    | L2RADIS       | L2 Data Cache read-allocate mode disable.                     |\n| [10]    | DODMBS        | Disable optimized data memory barrier behavior.               |\n| [9:7]   | -             | Reserved.                                                     |\n| [6]     | SMP           | Enables coherent requests to the processor.                   |\n| [5:0]   | -             | Reserved.                                                     |\n\n<b>Cortex-A9</b>\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:10] | -             | Reserved.                                                     |\n| [9]     | PARITY        | Support for parity checking, if implemented.                  |\n| [8]     | AOW           | Enable allocation in one cache way only.                      |\n| [7]     | EXCL          | Exclusive L1/L2 cache control.                                |\n| [6]     | SMP           | Enables coherent requests to the processor.                   |\n| [5:4]   | -             | Reserved.                                                     |\n| [3]     | WFLZM         | Enable write full line of zeros modea.                        |\n| [2]     | L1PE          | Dside prefetch.                                               |\n| [1]     | -             | Reserved.                                                     |\n| [0]     | FW            | Cache and TLB maintenance broadcast.                          |\n\nConsider using \\ref __get_ACTLR and \\ref __set_ACTRL to access ACTRL register.\n\n@{\n*/\n\n/**\n\\fn __STATIC_INLINE void __set_ACTRL(uint32_t actrl)\n\\details\n  This function assigns the given value to the \\ref CMSIS_ACTLR.\n\n\\fn __STATIC_INLINE uint32_t __get_ACTLR(void)\n\\details\n  This function returns the value of the \\ref CMSIS_ACTLR.\n\n\\struct ACTLR_Type\n\\brief Bit field declaration for ACTLR layout.\n\n\\defgroup CMSIS_ACTLR_BITS ACTLR Bits\n\\brief Bit position and mask macros\n@{\n\\def ACTLR_DDI_Pos\n\\def ACTLR_DDI_Msk\n\\def ACTLR_DBDI_Pos\n\\def ACTLR_DBDI_Msk\n\\def ACTLR_BTDIS_Pos\n\\def ACTLR_BTDIS_Msk\n\\def ACTLR_RSDIS_Pos\n\\def ACTLR_RSDIS_Msk\n\\def ACTLR_BP_Pos\n\\def ACTLR_BP_Msk\n\\def ACTLR_DDVM_Pos\n\\def ACTLR_DDVM_Msk\n\\def ACTLR_L1PCTL_Pos\n\\def ACTLR_L1PCTL_Msk\n\\def ACTLR_RADIS_Pos\n\\def ACTLR_RADIS_Msk\n\\def ACTLR_L1RADIS_Pos\n\\def ACTLR_L1RADIS_Msk\n\\def ACTLR_DWBST_Pos\n\\def ACTLR_DWBST_Msk\n\\def ACTLR_L2RADIS_Pos\n\\def ACTLR_L2RADIS_Msk\n\\def ACTLR_DODMBS_Pos\n\\def ACTLR_DODMBS_Msk\n\\def ACTLR_PARITY_Pos\n\\def ACTLR_PARITY_Msk\n\\def ACTLR_AOW_Pos\n\\def ACTLR_AOW_Msk\n\\def ACTLR_EXCL_Pos\n\\def ACTLR_EXCL_Msk\n\\def ACTLR_SMP_Pos\n\\def ACTLR_SMP_Msk\n\\def ACTLR_WFLZM_Pos\n\\def ACTLR_WFLZM_Msk\n\\def ACTLR_L1PE_Pos\n\\def ACTLR_L1PE_Msk\n\\def ACTLR_FW_Pos\n\\def ACTLR_FW_Msk\n@}\n*/\n\n/** @} */\n\n/* end group CMSIS_ACTLR */\n\n/* Cache and branch predictor maintenance operations */\n/**\n\\defgroup CMSIS_CBPM Cache and branch predictor maintenance operations\n\\ingroup CMSIS_core_register\n\\brief This section describes the cache and branch predictor maintenance operations.\n\\details\nCache maintenance operations are defined to act on particular memory locations.\nIn addition, for instruction caches and branch predictors, there are operations that invalidate all entries.\n\nConsider using \\ref L1_cache_functions and \\ref L2_cache_functions for cache maintenance instead of\nraw register usage.\n@{\n*/\n/**\n\\fn __STATIC_INLINE void __set_BPIALL(uint32_t value)   \n\\details\n  This function writes the provided value to the Branch Predictor Invalidate All (BPIALL) register.\n\n\\fn __STATIC_INLINE void __set_DCCIMVAC(uint32_t value) \n\\details\n  This function cleans and invalidates data or unified cache line by MVA to PoC.\n\n  \\fn __STATIC_INLINE void __set_DCCMVAC(uint32_t value) \n\\details\n  This function cleans data or unified cache line by MVA to PoC.\n\n\\fn __STATIC_INLINE void __set_DCIMVAC(uint32_t value) \n\\details\n  This function invalidates data or unified cache line by MVA to PoC.\n\n\\fn __STATIC_INLINE void __set_ICIALLU(uint32_t value) \n\\details\n  This function invalidates all instruction cache.\n*/\n\n/** @} */\n/* end group CMSIS_CBPM */\n\n/* CBAR Register */\n/**\n\\defgroup CMSIS_CBAR Configuration Base Address Register (CBAR)\n\\ingroup CMSIS_core_register\n\\brief Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13].\n\\details\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:13] | PERIPHBASE    | Peripheral base address.                                      |\n| [12:0]  | -             | Read as zero.                                                 |\n\nConsider \\ref __get_CBAR to access this register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE uint32_t __get_CBAR()\n\\details\n  This function returns the value of the Configuration Base Address register.\n\n\\defgroup CMSIS_CBAR_BITS CBAR Bits\n\\brief Bit position and mask macros\n@{\n\n@}          \n*/\n\n/** @} */\n/* end group CMSIS_CBAR */\n\n/* CP15 Register CPACR */\n/**\n\\defgroup CMSIS_CPACR Coprocessor Access Control Register (CPACR)\n\\ingroup CMSIS_core_register\n\\brief The CPACR controls access to coprocessors CP0 to CP13.\n\\details\nThe CPACR characteristics are:\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31]    | ASEDIS        | Disable Advanced SIMD functionality.                          |\n| [30]    | D32DIS        | Disable use of D16-D31 of the Floating-point Extension register file. |\n| [29]    | -             | Reserved.                                                     |\n| [28]    | TRCDIS        | Disable CP14 access to trace registers.                       |\n| [27:26] | CP13          | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 13.       |\n| [25:24] | CP12          | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 12.       |\n| [23:22] | CP11          | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 11.       |\n| [21:20] | CP10          | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 10.       |\n| [19:18] | CP9           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 9.        |\n| [17:16] | CP8           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 8.        |\n| [15:14] | CP7           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 7.        |\n| [13:12] | CP6           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 6.        |\n| [11:10] | CP5           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 5.        |\n| [9:8]   | CP4           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 4.        |\n| [7:6]   | CP3           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 3.        |\n| [5:4]   | CP2           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 2.        |\n| [3:2]   | CP1           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 1.        |\n| [1:0]   | CP0           | \\ref CMSIS_CPACR_CP \"Access rights\" for coprocessor 0.        |\n\nConsider \\ref __get_CPACR and \\ref __set_CPACR to access this register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE uint32_t __get_CPACR(void)\n\\details\n  This function returns the current value of the \\ref CMSIS_CPACR.\n\n\\fn __STATIC_INLINE void __set_CPACR(uint32_t cpacr)\n\\details\n  This function assigns the given value to the \\ref CMSIS_CPACR.\n\n\\struct CPACR_Type\n\\brief Bit field declaration for CPACR layout.\n\n\\defgroup CMSIS_CPACR_BITS CPACR Bits\n\\brief Bit position and mask macros\n@{\n\\def CPACR_ASEDIS_Pos         \n\\def CPACR_ASEDIS_Msk\n\\def CPACR_D32DIS_Pos         \n\\def CPACR_D32DIS_Msk\n\\def CPACR_TRCDIS_Pos\n\\def CPACR_TRCDIS_Msk\n\\def CPACR_CP_Pos_(n)\n\\def CPACR_CP_Msk_(n)\n@}       \n\n\\defgroup CMSIS_CPACR_CP CPACR CP field values\n\\brief Valid values for CPACR CP field.\n\\details Defines the access rights for a coprocessor.\n@{\n\\def CPACR_CP_NA \nAny attempt to access the coprocessor generates an Undefined\nInstruction exception.\n\n\\def CPACR_CP_PL1\nAny attempt to access the coprocessor from unprivileged\nsoftware generates an Undefined Instruction exception.\n\n\\def CPACR_CP_FA \nThe meaning of full access is defined by the appropriate coprocessor.\n@}\n*/\n/** @} */\n/* end group CMSIS_CPACR */\n\n/* Core Register CPSR */\n/**\n\\defgroup CMSIS_CPSR Current Program Status Register (CPSR)\n\\ingroup CMSIS_core_register\n\\brief The Current Program Status Register (CPSR) holds processor status and control information.\n\nThe individual register bits have the following meaning:\n\n| Bits    | Name       | Function                                                      |\n| :------ | :--------- | :------------------------------------------------------------ |\n| [31]    | N          | Negative condition code flag                                  |\n| [30]    | Z          | Zero condition code flag                                      |\n| [29]    | C          | Carry condition code flag                                     |\n| [28]    | V          | Overflow condition code flag                                  |\n| [27]    | Q          | Cumulative saturation bit                                     |\n| [26:25] | IT[1:0]    | If-Then execution state bits for the Thumb IT (If-Then) instruction |\n| [24]    | J          | Jazelle bit                                                   |\n| [19:16] | GE         | Greater than or Equal flags                                   |\n| [15:10] | IT[7:2]    | If-Then execution state bits for the Thumb IT (If-Then) instruction |\n| [9]     | E          | Endianness execution state bit: 0 - Little-endian, 1 - Big-endian |\n| [8]     | A          | Asynchronous abort mask bit                                   |\n| [7]     | I          | IRQ mask bit                                                  |\n| [6]     | F          | FIRQ mask bit                                                 |\n| [5]     | T          | Thumb execution state bit                                     |\n| [4:0]   | M          | \\ref CMSIS_CPSR_M \"Mode field\"                                |\n\nConsider using \\ref __get_CPSR and \\ref __set_CPSR for accessing this register.\n\n@{\n*/\n\n/**\n\\fn __STATIC_INLINE uint32_t __get_CPSR(void)\n\\details\n\tThis function returns the content of the \\ref CMSIS_CPSR.\n  \n\\fn __STATIC_INLINE void __set_CPSR(uint32_t cpsr)\n\\details\n\tThis function assigns the given value to the \\ref CMSIS_CPSR.\n\n\\struct CPSR_Type\n\\brief Bit field declaration for CPSR layout.\n\n\\defgroup CMSIS_CPSR_BITS CPSR Bits\n\\brief Bit position and mask macros\n@{\n\\def CPSR_N_Pos                  \n\\def CPSR_N_Msk\n\\def CPSR_Z_Pos                  \n\\def CPSR_Z_Msk                  \n\\def CPSR_C_Pos                  \n\\def CPSR_C_Msk\n\\def CPSR_V_Pos                  \n\\def CPSR_V_Msk\n\\def CPSR_Q_Pos                  \n\\def CPSR_Q_Msk\n\\def CPSR_IT0_Pos                \n\\def CPSR_IT0_Msk\n\\def CPSR_J_Pos                  \n\\def CPSR_J_Msk\n\\def CPSR_GE_Pos                 \n\\def CPSR_GE_Msk\n\\def CPSR_IT1_Pos                \n\\def CPSR_IT1_Msk\n\\def CPSR_E_Pos                  \n\\def CPSR_E_Msk\n\\def CPSR_A_Pos                  \n\\def CPSR_A_Msk\n\\def CPSR_I_Pos                  \n\\def CPSR_I_Msk\n\\def CPSR_F_Pos                  \n\\def CPSR_F_Msk\n\\def CPSR_T_Pos                  \n\\def CPSR_T_Msk\n\\def CPSR_M_Pos                  \n\\def CPSR_M_Msk\n@}\n\n\\defgroup CMSIS_CPSR_M CPSR M field values\n\\brief Valid values for CPSR M field.\n\\details The M field can contain one of these values which indicates the current processor mode.\n@{\n\\def CPSR_M_USR\nAn operating system runs applications in User mode to restrict the use of system resources. Software\nexecuting in User mode executes at PL0. Execution in User mode is sometimes described as\nunprivileged execution.\n\n\\def CPSR_M_FIQ\nFIQ mode is the default mode to which an FIQ interrupt is taken.\n\n\\def CPSR_M_IRQ\nIRQ mode is the default mode to which an IRQ interrupt is taken.\n\n\\def CPSR_M_SVC\nSupervisor mode is the default mode to which a Supervisor Call exception is taken.\n\n\\def CPSR_M_MON\nMonitor mode is the mode to which a Secure Monitor Call exception is taken.\n\n\\def CPSR_M_ABT\nAbort mode is the default mode to which a Data Abort exception or Prefetch Abort exception is\ntaken.\n\n\\def CPSR_M_HYP\nHyp mode is the Non-secure PL2 mode, implemented as part of the Virtualization Extensions. Hyp\nmode is entered on taking an exception from Non-secure state that must be taken to PL2.\n\n\\def CPSR_M_UND\nUndefined mode is the default mode to which an instruction-related exception, including any\nattempt to execute an UNDEFINED instruction, is taken.\n\n\\def CPSR_M_SYS\nSoftware executing in System mode executes at PL1. System mode has the same registers available\nas User mode, and is not entered by any exception.\n\n@}\n*/\n\n/** @} */\n\n\n/* end group CMSIS_CPSR */\n\n\n/* CP15 Register DFSR */\n/**\n\\defgroup CMSIS_DFSR Data Fault Status Register (DFSR)\n\\ingroup CMSIS_core_register\n\\brief The DFSR holds status information about the last data fault.\n\\details\n\n<b>DFSR format when using the Short-descriptor translation table format</b>\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:14] | -             | Reserved.                                                     |\n| [13]    | CM            | Cache maintenance fault.                                      |\n| [12]    | ExT           | External abort type.                                          |\n| [11]    | WnR           | Write not Read bit.                                           |\n| [10]    | FS[4]         | Fault status bits.                                            |\n| [9]     | LPAE          | Large Physical Address Extension.                             |\n| [8]     | -             | Reserved.                                                     |\n| [7:4]   | Domain        | The domain of the fault address.                              |\n| [3:0]   | FS[3:0]       | Fault status bits.                                            |\n\n<b>DFSR format when using the Long-descriptor translation table format</b>\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:14] | -             | Reserved.                                                     |\n| [13]    | CM            | Cache maintenance fault.                                      |\n| [12]    | ExT           | External abort type.                                          |\n| [11]    | WnR           | Write not Read bit.                                           |\n| [10]    | -             | Reserved.                                                     |\n| [9]     | LPAE          | Large Physical Address Extension.                             |\n| [8:6]   | -             | Reserved.                                                     |\n| [5:0]   | STATUS        | Fault status bits.                                            |\n\nConsider \\ref __get_DFSR and \\ref __set_DFSR to access this register.\n\n@{\n*/\n/**\n\\struct DFSR_Type\n\\brief Bit field declaration for DFSR layout.\n\n\\fn __STATIC_INLINE uint32_t __get_DFSR(void)\n\\details\n  This function returns the current value of the \\ref CMSIS_DFSR.\n\n\\fn __STATIC_INLINE void __set_DFSR(uint32_t dfsr)\n\\details\n  This function assigns the given value to the \\ref CMSIS_DFSR.\n  \n\\defgroup CMSIS_DFSR_BITS ACTLR Bits\n\\brief Bit position and mask macros\n@{\n\\def DFSR_CM_Pos             \n\\def DFSR_CM_Msk\n\\def DFSR_Ext_Pos            \n\\def DFSR_Ext_Msk\n\\def DFSR_WnR_Pos            \n\\def DFSR_WnR_Msk\n\\def DFSR_LPAE_Pos\n\\def DFSR_LPAE_Msk\n\\def DFSR_FS1_Pos            \n\\def DFSR_FS1_Msk\n\\def DFSR_Domain_Pos         \n\\def DFSR_Domain_Msk\n\\def DFSR_FS0_Pos\n\\def DFSR_FS0_Msk\n\\def DFSR_STATUS_Pos\n\\def DFSR_STATUS_Msk\n@}    \n\n*/\n/** @} */\n/* end group CMSIS_DFSR */\n\n/* DACR Register */\n/**\n\\defgroup CMSIS_DACR Domain Access Control Register (DACR)\n\\ingroup CMSIS_core_register\n\\brief DACR defines the access permission for each of the sixteen memory domains.\n\\details\n\n| Bits    | Name | Function                                           |\n| :------ | :--- | :------------------------------------------------- |\n| [31:30] | D15  | Domain 15 \\ref CMSIS_DACR_Dn \"access permission\".  |\n| [29:28] | D14  | Domain 14 \\ref CMSIS_DACR_Dn \"access permission\".  |\n| [27:26] | D13  | Domain 13 \\ref CMSIS_DACR_Dn \"access permission\".  |\n| [25:24] | D12  | Domain 12 \\ref CMSIS_DACR_Dn \"access permission\".  |\n| [23:22] | D11  | Domain 11 \\ref CMSIS_DACR_Dn \"access permission\".  |\n| [21:20] | D10  | Domain 10 \\ref CMSIS_DACR_Dn \"access permission\".  |\n| [19:18] | D9   | Domain 9 \\ref CMSIS_DACR_Dn \"access permission\".   |\n| [17:16] | D8   | Domain 8 \\ref CMSIS_DACR_Dn \"access permission\".   |\n| [15:14] | D7   | Domain 7 \\ref CMSIS_DACR_Dn \"access permission\".   |\n| [13:12] | D6   | Domain 6 \\ref CMSIS_DACR_Dn \"access permission\".   |\n| [11:10] | D5   | Domain 5 \\ref CMSIS_DACR_Dn \"access permission\".   |\n| [9:8]   | D4   | Domain 4 \\ref CMSIS_DACR_Dn \"access permission\".   |\n| [7:6]   | D3   | Domain 3 \\ref CMSIS_DACR_Dn \"access permission\".   |\n| [5:4]   | D2   | Domain 2 \\ref CMSIS_DACR_Dn \"access permission\".   |\n| [3:2]   | D1   | Domain 1 \\ref CMSIS_DACR_Dn \"access permission\".   |\n| [1:0]   | D0   | Domain 0 \\ref CMSIS_DACR_Dn \"access permission\".   |\n\nConsider \\ref __get_DACR and \\ref __set_DACR to access this register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE uint32_t __get_DACR() \n\\details\n  This function returns the value of the \\ref CMSIS_DACR.\n\n\\fn __STATIC_INLINE void __set_DACR(uint32_t dacr) \n\\details\n  This function assigns the given value to the \\ref CMSIS_DACR.\n\n\\defgroup CMSIS_DACR_BITS DACR Bits\n\\brief Bit position and mask macros\n@{\n\\def DACR_D_Pos_(n) \n\\details Get the bit position for domain n access permission.\n\n\\b Example:\n\\code\n// retrieve access permission for domain 5\nuint32_t domain5 = (__get_DACR() & DACR_D_Msk_(5)) >> DACR_D_Pos_(5);\n\\endcode\n\n\\def DACR_D_Msk_(n)  \n\\details Get the bit mask for domain n access permission.\n\n\\b Example:\n\\code\n// clear access permission for domain 7\n__set_DACR(__get_DACR() & ~DACR_D_Msk_(7));\n\\endcode\n@}\n\n\\defgroup CMSIS_DACR_Dn DACR Dn field values\n\\brief Valid values for DACR Dn field.\n\\details The Dn field can contain one of these values which indicates the domain n access permission.\n@{\n\\def DACR_Dn_NOACCESS\n\\details Any access to the domain generates a Domain fault.\n\n\\def DACR_Dn_CLIENT  \n\\details Accesses are checked against the permission bits in the translation tables.\n\n\\def DACR_Dn_MANAGER \n\\details Accesses are not checked against the permission bits in the translation tables.\n@}\n*/\n\n/** @} */\n/* end group CMSIS_DACR */\n\n/* FPEXC Register */\n/**\n\\defgroup CMSIS_FPEXC Floating-Point Exception Control register (FPEXC)\n\\ingroup CMSIS_core_register\n\\brief Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and\nindicates how the state of these extensions is recorded.\n\\details\n| Bits    | Name | Function                                           |\n| :------ | :--- | :------------------------------------------------- |\n| [31]    | EX   | Exception bit.                                     |\n| [30]    | EN   | Enable bit.                                        |\n| [29:0]  | -    | SUBARCHITECTURE DEFINED.                           |\n\nConsider \\ref __get_FPEXC and \\ref __set_FPEXC to access this register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE uint32_t __get_FPEXC(void)\n\\details\n  This function returns the current value of the \\ref CMSIS_FPEXC.\n\n\\fn __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)\n\\details\n  This function assigns the given value to the \\ref CMSIS_FPEXC.\n*/\n\n/** @} */\n/* end group CMSIS_FPEXC */\n\n/* FPSCR Register */\n/**\n\\defgroup CMSIS_FPSCR Floating-point Status and Control Register (FPSCR)\n\\ingroup CMSIS_core_register\n\\brief Provides floating-point system status information and control.\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31]    | N             | Negative condition flag.                                      |\n| [30]    | Z             | Zero condition flag.                                          |\n| [29]    | C             | Carry condition flag.                                         |\n| [28]    | V             | Overflow condition flag.                                      |\n| [27]    | QC            | External abort pending bit.                                   |\n| [26]    | AHP           | External abort pending bit.                                   |\n| [25]    | DN            | External abort pending bit.                                   |\n| [24]    | FZ            | External abort pending bit.                                   |\n| [23:22] | RMode         | External abort pending bit.                                   |\n| [21:20] | Stride        | External abort pending bit.                                   |\n| [19]    | -             | Reserved.                                                     |\n| [18:16] | Len           | External abort pending bit.                                   |\n| [15]    | IDE           | IRQ pending bit.                                              |\n| [14:13] | -             | Reserved.                                                     |\n| [12]    | IXE           | IRQ pending bit.                                              |\n| [11]    | UFE           | IRQ pending bit.                                              |\n| [10]    | OFE           | IRQ pending bit.                                              |\n| [9]     | DZE           | IRQ pending bit.                                              |\n| [8]     | IOE           | IRQ pending bit.                                              |\n| [7]     | IDC           | IRQ pending bit.                                              |\n| [6:5]   | -             | Reserved.                                                     |\n| [4]     | IXC           | FIQ pending bit.                                              |\n| [3]     | UFC           | FIQ pending bit.                                              |\n| [2]     | OFC           | FIQ pending bit.                                              |\n| [1]     | DZC           | FIQ pending bit.                                              |\n| [0]     | IOC           | FIQ pending bit.                                              |\n\nConsider \\ref __get_FPSCR and \\ref __set_FPSCR to access this register.\n\n@{\n*/\n/**\n\\struct FPSCR_Type\n\\brief Bit field declaration for FPSCR layout.\n\n\\fn __STATIC_INLINE uint32_t __get_FPSCR(void)\n\\details \n  This function returns the current value of the \\ref CMSIS_FPSCR.\n\n\\fn __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\n\\details \n  Assigns the given value to the \\ref CMSIS_FPSCR.\n\n\\defgroup CMSIS_FPSCR_BITS FPSCR Bits\n\\brief Bit position and mask macros\n@{\n\n@}          \n*/\n\n/** @} */\n/* end group CMSIS_FPSCR */\n\n/* CP15 Register IFSR */\n/**\n\\defgroup CMSIS_IFSR Instruction Fault Status Register (IFSR)\n\\ingroup CMSIS_core_register\n\\brief The IFSR holds status information about the last instruction fault.\n\\details\n\n<b>DFSR format when using the Short-descriptor translation table format</b>\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:13] | -             | Reserved.                                                     |\n| [12]    | ExT           | External abort type.                                          |\n| [11]    | -             | Reserved.                                                     |\n| [10]    | FS[4]         | Fault status bits.                                            |\n| [9]     | LPAE          | Large Physical Address Extension.                             |\n| [8:4]   | -             | Reserved.                                                     |\n| [3:0]   | FS[3:0]       | Fault status bits.                                            |\n\n<b>DFSR format when using the Long-descriptor translation table format</b>\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:13] | -             | Reserved.                                                     |\n| [12]    | ExT           | External abort type.                                          |\n| [11:10] | -             | Reserved.                                                     |\n| [9]     | LPAE          | Large Physical Address Extension.                             |\n| [8:6]   | -             | Reserved.                                                     |\n| [5:0]   | STATUS        | Fault status bits.                                            |\n\nConsider \\ref __get_IFSR and \\ref __set_IFSR to access this register.\n@{\n*/\n/**\n\\struct IFSR_Type\n\\brief Bit field declaration for IFSR layout.\n\n\\fn __STATIC_INLINE uint32_t __get_IFSR(void)\n\\details\n  This function returns the current value of the \\ref CMSIS_IFSR.\n\n\\fn __STATIC_INLINE void __set_IFSR(uint32_t ifsr)\n\\details\n  This function assigns the given value to the \\ref CMSIS_IFSR.\n\n\\defgroup CMSIS_IFSR_BITS IFSR Bits\n\\brief Bit position and mask macros\n@{\n\\def IFSR_ExT_Pos           \n\\def IFSR_ExT_Msk\n\\def IFSR_LPAE_Pos\n\\def IFSR_LPAE_Msk\n\\def IFSR_FS1_Pos           \n\\def IFSR_FS1_Msk\n\\def IFSR_FS0_Pos           \n\\def IFSR_FS0_Msk\n\\def IFSR_STATUS_Pos           \n\\def IFSR_STATUS_Msk\n@}\n*/\n/** @} */\n/* end group CMSIS_IFSR */\n\n/* CP15 Register ISR */\n/**\n\\defgroup CMSIS_ISR Interrupt Status Register (ISR)\n\\ingroup CMSIS_core_register\n\\brief The ISR shows whether an IRQ, FIQ, or external abort is pending.\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:9]  | -             | Reserved.                                                     |\n| [8]     | A             | External abort pending bit.                                   |\n| [7]     | I             | IRQ pending bit.                                              |\n| [6]     | F             | FIQ pending bit.                                              |\n| [5:0]   | -             | Reserved.                                                     |\n\nConsider \\ref __get_IFSR to access this register.\n\n@{\n*/\n/**\n\\struct ISR_Type\n\\brief Bit field declaration for ISR layout.\n\n\\fn __STATIC_INLINE uint32_t __get_ISR(void)\n\\details\n  This function returns the current value of the \\ref CMSIS_ISR.\n\n\\defgroup CMSIS_ISR_BITS ISR Bits\n\\brief Bit position and mask macros\n@{\n\\def ISR_A_Pos             \n\\def ISR_A_Msk\n\\def ISR_I_Pos             \n\\def ISR_I_Msk\n\\def ISR_F_Pos   \n\\def ISR_F_Msk\n@}          \n*/\n\n/** @} */\n/* end group CMSIS_ISR */\n\n/* MPIDR Register */\n/**\n\\defgroup CMSIS_MPIDR Multiprocessor Affinity Register (MPIDR)\n\\ingroup CMSIS_core_register\n\\brief In a multiprocessor system, the MPIDR provides an additional processor identification\nmechanism for scheduling purposes, and indicates whether the implementation includes the\nMultiprocessing Extensions.\n\n\\details\n| Bits    | Name | Function                                           |\n| :------ | :--- | :------------------------------------------------- |\n| [31]    | MPEA | Multiprocessing Extensions Available               |\n| [30]    | U    | Indicates a Uniprocessor system                    |\n| [29:25] | -    | Reserved.                                          |\n| [24]    | MT   | Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach. |\n| [23:16] | Aff2 | Affinity level 2.                                  |\n| [15:8]  | Aff1 | Affinity level 1.                                  |\n| [7:0]   | Aff0 | Affinity level 0.                                  |\n\nConsider \\ref __get_MPIDR to access this register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE uint32_t __get_MPIDR(void)\n\\details\n  This function returns the value of the \\ref CMSIS_MPIDR.\n*/\n\n/** @} */\n/* end group CMSIS_MPIDR */\n\n/* CNTFRQ Register */\n/**\n\\defgroup CMSIS_CNTFRQ Counter Frequency register (CNTFRQ)\n\\ingroup CMSIS_core_register\n\\brief Indicates the clock frequency of the system counter.\n\\details\nConsider \\ref __get_CNTFRQ and \\ref __set_CNTFRQ to access this register.\n\nConsider using \\ref PL1_timer_functions for controlling the PL1 Timer instead.\n@{\n*/\n/**\n\\fn __STATIC_INLINE void __set_CNTFRQ(uint32_t value) \n\\details\n  This function assigns the given value to \\ref CMSIS_CNTFRQ.\n\n\\fn __STATIC_INLINE uint32_t __get_CNTFRQ() \n\\details\n  This function returns the value of the \\ref CMSIS_CNTFRQ.\n*/\n\n/** @} */\n/* end group CMSIS_CNTFRQ */\n\n/* CNTP_CTL Register */\n/**\n\\defgroup CMSIS_CNTP_CTL PL1 Physical Timer Control register (CNTP_CTL)\n\\ingroup CMSIS_core_register\n\\brief The control register for the physical timer.\n\\details\n| Bits    | Name    | Function                                           |\n| :------ | :------ | :------------------------------------------------- |\n| [31:3]  | -       | Reserved.                                          |\n| [2]     | ISTATUS | The status of the timer.                           |\n| [1]     | IMASK   | Timer output signal mask bit.                      |\n| [0]     | ENABLE  | Enables the timer.                                 |\n\nConsider \\ref __get_CNTP_CTL and \\ref __set_CNTP_CTL to access this register.\n\nConsider using \\ref PL1_timer_functions for controlling the PL1 Timer instead.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) \n\\details\n  This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).\n  \n\\fn __STATIC_INLINE uint32_t __get_CNTP_CTL() \n\\details\n  This function returns the value of the PL1 Physical Timer Control Register. (CNTP_CTL).\n*/\n\n/** @} */\n/* end group CMSIS_CNTP_CTL */\n\n/* CNTP_CVAL Register */\n/**\n\\defgroup CMSIS_CNTP_CVAL PL1 Physical Timer Compare Value register (CNTP_CVAL)\n\\ingroup CMSIS_core_register\n\\brief Holds the 64-bit compare value for the PL1 physical timer.\n\\details\nConsider \\ref __get_CNTP_CVAL and \\ref __set_CNTP_CVAL to access this register.\n\nConsider using \\ref PL1_timer_functions for controlling the PL1 Timer instead.\n@{\n*/\n/**\n\\fn __STATIC_INLINE void __set_CNTP_CVAL(uint32_t value) \n\\details\n  This function assigns the given value to \\ref CMSIS_CNTP_CVAL.\n\n\\fn __STATIC_INLINE uint32_t __get_CNTP_CVAL() \n\\details\n  This function returns the value of the \\ref CMSIS_CNTP_CVAL.\n*/\n\n/** @} */\n/* end group CMSIS_CNTP_CVAL */\n\n/* CNTP_TVAL Register */\n/**\n\\defgroup CMSIS_CNTP_TVAL PL1 Physical Timer Value register (CNTP_TVAL)\n\\ingroup CMSIS_core_register\n\\brief Holds the timer value for the PL1 physical timer.\n\\details\nConsider \\ref __get_CNTP_TVAL and \\ref __set_CNTP_TVAL to access this register.\n\nConsider using \\ref PL1_timer_functions for controlling the PL1 Timer instead.\n@{\n*/\n/**\n\\fn __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) \n\\details\n  This function assigns the given value to \\ref CMSIS_CNTP_TVAL.\n\n\\fn __STATIC_INLINE uint32_t __get_CNTP_TVAL() \n\\details\n  This function returns the value of the \\ref CMSIS_CNTP_TVAL.\n*/\n\n/** @} */\n/* end group CMSIS_CNTP_TVAL */\n\n/* CNTPCT Register */\n/**\n\\defgroup CMSIS_CNTPCT PL1 Physical Count register (CNTPCT)\n\\ingroup CMSIS_core_register\n\\brief Holds the 64-bit physical count value.\n\\details\nConsider \\ref __get_CNTPCT to access this register.\n\nConsider using \\ref PL1_timer_functions for controlling the PL1 Timer instead.\n@{\n*/\n/**\n\\fn __STATIC_INLINE uint64_t __get_CNTPCT() \n\\details\n  This function returns the value of the \\ref CMSIS_CNTPCT.\n*/\n\n/** @} */\n/* end group CMSIS_CNTPCT */\n\n/* Stack Pointer */\n/**\n\\defgroup CMSIS_SP Stack Pointer (SP/R13)\n\\ingroup CMSIS_core_register\n\\brief The processor uses SP as a pointer to the active stack.\n\\details \nThe Stack Pointer is banked per processor mode. Accessing the \nactive stack pointer actually returns/modifies the stack pointer\nof the current processor execution mode.\n\n| Mode        | Actual SP |\n| :---------- | :-------- |\n| User/System | SP_usr    |\n| Hypervisor  | SP_hyp    |\n| Supervisor  | SP_svc    |\n| Abort       | SP_abt    |\n| Undefined   | SP_und    |\n| Monitor     | SP_mon    |\n| IRQ         | SP_irq    |\n| FIQ         | SP_fiq    |\n\nConsider \\ref __set_SP and \\ref __set_SP_usr to access this register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE __ASM void __set_SP(uint32_t stack)\n\\details\n  This function assigns the given value to the current stack pointer.\n\n\\fn __STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)\n\\details\n  This function assigns the given value to the User/System Stack Pointer (SP_usr).\n*/\n\n/** @} */\n/* end group CMSIS_SP */\n\n\n/* CP15 Register SCTLR */\n/**\n\\defgroup CMSIS_SCTLR System Control Register (SCTLR)\n\\ingroup CMSIS_core_register\n\\brief The SCTLR provides the top level control of the system, including its memory system.\n\\details \nIn a VMSAv7 implementation, the SCTLR bit assignments are:\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31]    | -             | Reserved.                                                     |\n| [30]    | TE            | Thumb Exception enable.                                       |\n| [29]    | AFE           | Access flag enable bit.                                       |\n| [28]    | TRE           | TEX remap enable bit.                                         |\n| [27:26] | -             | Reserved.                                                     |\n| [25]    | EE            | Exception Endianness bit.                                     |\n| [24:21] | -             | Reserved.                                                     |\n| [20]    | UWXN          | Unprivileged write permission implies PL1 Execute Never (XN). |\n| [19]    | WXN           | Write permission implies Execute Never (XN).                  |\n| [18:14] | -             | Reserved.                                                     |\n| [13]    | V             | Vectors bit.                                                  |\n| [12]    | I             | Instruction cache enable bit.                                 |\n| [11]    | Z             | Branch prediction enable bit.                                 |\n| [10]    | SW            | SWP and SWPB enable bit.                                      |\n| [9:3]   | -             | Reserved.                                                     |\n| [2]     | C             | Cache enable bit.                                             |\n| [1]     | A             | Alignment bit.                                                |\n| [0]     | M             | Address translation enable bit.                               |\n\nConsider using \\ref __get_SCTLR and \\ref __set_SCTLR for accessing this register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)\n\\details\n  This function assigns the given value to the \\ref CMSIS_SCTLR.\n\n\\fn __STATIC_INLINE uint32_t __get_SCTLR() \n\\details\n  This function returns the value of the \\ref CMSIS_SCTLR.\n\n\\struct SCTLR_Type\n\\brief Bit field declaration for SCTLR layout.\n\n\\defgroup CMSIS_SCTLR_BITS SCTLR Bits\n\\brief Bit position and mask macros\n@{\n\\def SCTLR_TE_Pos                  \n\\def SCTLR_TE_Msk\n\\def SCTLR_AFE_Pos                 \n\\def SCTLR_AFE_Msk\n\\def SCTLR_TRE_Pos                 \n\\def SCTLR_TRE_Msk\n\\def SCTLR_NMFI_Pos                \n\\def SCTLR_NMFI_Msk\n\\def SCTLR_EE_Pos                  \n\\def SCTLR_EE_Msk\n\\def SCTLR_VE_Pos                  \n\\def SCTLR_VE_Msk\n\\def SCTLR_U_Pos                   \n\\def SCTLR_U_Msk\n\\def SCTLR_FI_Pos                  \n\\def SCTLR_FI_Msk\n\\def SCTLR_UWXN_Pos                \n\\def SCTLR_UWXN_Msk\n\\def SCTLR_WXN_Pos                 \n\\def SCTLR_WXN_Msk\n\\def SCTLR_HA_Pos                  \n\\def SCTLR_HA_Msk\n\\def SCTLR_RR_Pos                  \n\\def SCTLR_RR_Msk\n\\def SCTLR_V_Pos                   \n\\def SCTLR_V_Msk\n\\def SCTLR_I_Pos                   \n\\def SCTLR_I_Msk\n\\def SCTLR_Z_Pos                   \n\\def SCTLR_Z_Msk\n\\def SCTLR_SW_Pos                  \n\\def SCTLR_SW_Msk\n\\def SCTLR_B_Pos                   \n\\def SCTLR_B_Msk\n\\def SCTLR_CP15BEN_Pos             \n\\def SCTLR_CP15BEN_Msk\n\\def SCTLR_C_Pos                   \n\\def SCTLR_C_Msk\n\\def SCTLR_A_Pos                   \n\\def SCTLR_A_Msk\n\\def SCTLR_M_Pos                   \n\\def SCTLR_M_Msk\n@}\n*/\n/** @} */\n/* end group CMSIS_SCTLR */\n\n/* TLB maintenance operations */\n/**\n\\defgroup CMSIS_TLB TLB maintenance operations\n\\ingroup CMSIS_core_register\n\\brief This section describes the TLB operations that are implemented on all Armv7-A implementations.\n\\details \nTLB maintenance operations provide a mechanism to invalidate entries from a TLB.\n\nConsider using \\ref MMU_functions instead of raw register usage.\n@{\n*/\n/**\n\\fn __STATIC_INLINE void __set_TLBIALL(uint32_t value) \n\\details\n  This function invalidates entire unified TLB.\n*/\n/** @} */\n/* end group CMSIS_TLB */\n\n/* CP15 Register TTBR0/TTBR1 */\n/**\n\\defgroup CMSIS_TTBR Translation Table Base Registers (TTBR0/TTBR1)\n\\ingroup CMSIS_core_register\n\\brief TTBRn holds the base address of translation table n, and information about the memory it occupies.\n\\details \n<b>32-bit TTBR format</b>\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:x]  | BADDR         | Translation table base address, bits[31:x].                   |\n| [x-1:7] | -             | Reserved.                                                     |\n| [6]     | IRGN[0]       | Inner region bit 0.                                           |\n| [5]     | NOS           | Not Outer Shareable bit.                                      |\n| [4:3]   | RGN           | Region bits.                                                  |\n| [2]     | -             | Reserved.                                                     |\n| [1]     | S             | Shareable bit.                                                |\n| [0]     | C/IRGN[1]     | Cacheable bit. / Inner region bit 1.                          |\n\n\\note The width of TTBR0 BADDR field depends on the setting in TTBCR N field, giving `x=14-N`.\n\\note The width of TTBR1 BADDR field is fixed at `x=14`.\n\n<b>64-bit TTBR format</b>\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [63:56] | -             | Reserved.                                                     |\n| [55:48] | ASID          | An ASID for the translation table base address.               |\n| [47:40] | -             | Reserved.                                                     |\n| [39:x]  | BADDR         | Translation table base address, bits[39:x].                   |\n| [x-1:0] | -             | Reserved.                                                     |\n\n\\note The width of TBBR0/TBBR1 BADDR fields depends on the settings in TTBCR T0SZ/T1SZ fields respectively, giving `x=14-TnSZ`.\n\nConsider using \\ref __get_TTBR0 and \\ref __set_TTBR0 for accessing TTBR0 register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE uint32_t __get_TTBR0() \n\\details\n  This function returns the value of the Translation Table Base Register 0.\n\n\\fn __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) \n\\details\n  This function assigns the given value to the Translation Table Base Register 0.\n*/\n/** @} */\n/* end group CMSIS_TTBR */\n\n/* CP15 Register VBAR */\n/**\n\\defgroup CMSIS_VBAR Vector Base Address Register (VBAR)\n\\ingroup CMSIS_core_register\n\\brief When high exception vectors are not selected, the VBAR holds the exception base address\nfor exceptions that are not taken to Monitor mode or to Hyp mode.\n\\details \n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:5]  | VBA           | Bits[31:5] of the base address of the low exception vectors.  |\n| [4:0]   | -             | Reserved.                                                     |\n\nConsider using \\ref __get_VBAR and \\ref __set_VBAR for accessing this register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE uint32_t __get_VBAR(void)\n\\details\n  This function returns the value of the \\ref CMSIS_VBAR.\n\n\\fn __STATIC_INLINE void __set_VBAR(uint32_t vbar)\n\\details\n  This function assigns the given value to the \\ref CMSIS_VBAR.\n*/\n/** @} */\n/* end group CMSIS_VBAR */\n\n/* CP15 Register MVBAR */\n/**\n\\defgroup CMSIS_MVBAR Monitor Vector Base Address Register (MVBAR)\n\\ingroup CMSIS_core_register\n\\brief The MVBAR holds the exception base address for all exceptions that are taken to Monitor\nmode.\n\\details \n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ |\n| [31:5]  | MVBA          | Bits[31:5] of the base address of the exception vectors for exceptions that are taken to Monitor mode. |\n| [4:0]   | -             | Reserved.                                                     |\n\nConsider using \\ref __get_MVBAR and \\ref __set_MVBAR for accessing this register.\n\n@{\n*/\n/**\n\\fn __STATIC_INLINE uint32_t __get_MVBAR(void)\n\\details\n  This function returns the value of the \\ref CMSIS_MVBAR.\n\n\\fn __STATIC_INLINE void __set_MVBAR(uint32_t mvbar)\n\\details\n  This function assigns the given value to the \\ref CMSIS_MVBAR.\n*/\n/** @} */\n/* end group CMSIS_MVBAR */\n\n/** @} */ \n/* end of group CMSIS_core_register */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/ref_gic.txt",
    "content": "/* ##########################  GIC functions  ###################################### */\n/**\n\\defgroup GIC_functions Generic Interrupt Controller Functions\n\\ingroup CMSIS_Core_FunctionInterface\n\\brief The Generic Interrupt Controller Functions grant access to the configuration, control and\nstatus registers of the Generic Interrupt Controller (GIC).\n\nReference: <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069c/index.html\">Generic Interrupt Controller Architecture Specificaton</a>.\n\nThe following table shows the register naming of CMSIS in correlation with various technical reference manuals.\n\n| CMSIS Register Name                                                  | Cortex-A5 TRM  | Cortex-A7 TRM    | Cortex-A9 TRM  | \n| :------------------------------------------------------------------- | :------------- | :--------------- | :------------- | \n| <b>GIC Distributor</b>                                               |                |                  |                |\n| \\ref GICDistributor_Type::CTLR \"GICDistributor->CTLR\"                | ICDDCR         | GICD_CTLR        | ICDDCR         | \n| \\ref GICDistributor_Type::TYPER \"GICDistributor->TYPER\"              | ICDICTR        | GICD_TYPER       | ICDICTR        | \n| \\ref GICDistributor_Type::IIDR \"GICDistributor->IIDR\"                | ICDIIDR        | GICD_IIDR        | ICDIIDR        | \n| \\ref GICDistributor_Type::STATUSR \"GICDistributor->STATUSR\"          |                |                  |                | \n| \\ref GICDistributor_Type::SETSPI_NSR \"GICDistributor->SETSPI_NSR\"    |                |                  |                | \n| \\ref GICDistributor_Type::CLRSPI_NSR \"GICDistributor->CLRSPI_NSR\"    |                |                  |                | \n| \\ref GICDistributor_Type::IGROUPR \"GICDistributor->IGROUPR[]\"        | ICDISR         | GICD_IGROUPRn    | ICDISRn        | \n| \\ref GICDistributor_Type::ISENABLER \"GICDistributor->ISENABLER[]\"    | ICDISER        | GICD_ISENABLERn  | ICDISERn       | \n| \\ref GICDistributor_Type::ICENABLER \"GICDistributor->ICENABLER[]\"    | ICDICER        | GICD_ICENABLERn  | ICDICERn       | \n| \\ref GICDistributor_Type::ISPENDR \"GICDistributor->ISPENDR[]\"        | ICDISPR        | GICD_ISPENDRn    | ICDISPRn       | \n| \\ref GICDistributor_Type::ICPENDR \"GICDistributor->ICPENDR[]\"        | ICDICPR        | GICD_ICPENDRn    | ICDICPRn       | \n| \\ref GICDistributor_Type::ISACTIVER \"GICDistributor->ISACTIVER[]\"    | ICDABR         | GICD_ISACTIVERn  | ICDABRn        | \n| \\ref GICDistributor_Type::ICACTIVER \"GICDistributor->ICACTIVER[]\"    |                | GICD_ICACTIVERn  |                | \n| \\ref GICDistributor_Type::IPRIORITYR \"GICDistributor->IPRIORITYR[]\"  | ICDIPR         | GICD_IPRIORITYRn | ICDIPRn        | \n| \\ref GICDistributor_Type::ITARGETSR \"GICDistributor->ITARGETSR[]\"    | ICDIPTR        | GICD_ITARGETSRn  | ICDIPTRn       | \n| \\ref GICDistributor_Type::ICFGR \"GICDistributor->ICFGR[]\"            | ICDICFR        | GICD_ICFGRn      | ICDICFRn       | \n| \\ref GICDistributor_Type::IGRPMODR \"GICDistributor->IGRPMODR[0]\"     | ICDPPIS        | GICD_PPISR       | ppi_status     | \n| \\ref GICDistributor_Type::IGRPMODR \"GICDistributor->IGRPMODR[31:1]\"  | ICDSPIS        | GICD_SPISRn      | spi_status     | \n| \\ref GICDistributor_Type::NSACR \"GICDistributor->NSACR[]\"            |                |                  |                | \n| \\ref GICDistributor_Type::SGIR \"GICDistributor->SGIR\"                | ICDSGIR        | GICD_SGIR        | ICDSGIR        |\n| \\ref GICDistributor_Type::CPENDSGIR \"GICDistributor->CPENDSGIR[]\"    |                | GICD_CPENDSGIRn  |                | \n| \\ref GICDistributor_Type::SPENDSGIR \"GICDistributor->SPENDSGIR[]\"    |                | GICD_SPENDSGIRn  |                | \n| \\ref GICDistributor_Type::IROUTER \"GICDistributor->IROUTER[]\"        |                |                  |                | \n| <b>GIC Interface</b>                                                 |                |                  |                |\n| \\ref GICInterface_Type::CTLR \"GICInterface->CTLR\"                    | ICPICR         | GICC_CTLR        | ICCICR         | \n| \\ref GICInterface_Type::PMR \"GICInterface->PMR\"                      | ICCIPMR        | GICC_PMRn        | ICCPMR         | \n| \\ref GICInterface_Type::BPR \"GICInterface->BPR\"                      | ICCBPR         | GICC_BPR         | ICCBPR         | \n| \\ref GICInterface_Type::IAR \"GICInterface->IAR\"                      | ICCIAR         | GICC_IAR         | ICCIAR         | \n| \\ref GICInterface_Type::EOIR \"GICInterface->EOIR\"                    | ICCEOIR        | GICC_EOIR        | ICCEOIR        | \n| \\ref GICInterface_Type::RPR \"GICInterface->RPR\"                      | ICCRPR         | GICC_RPR         | ICCRPR         | \n| \\ref GICInterface_Type::HPPIR \"GICInterface->HPPIR\"                  | ICCHPIR        | GICC_HPPIR       | ICCHPIR        | \n| \\ref GICInterface_Type::ABPR \"GICInterface->ABPR\"                    | ICCABPR        | GICC_ABPR        | ICCABPR        | \n| \\ref GICInterface_Type::AIAR \"GICInterface->AIAR\"                    |                | GICC_AIAR        |                | \n| \\ref GICInterface_Type::AEOIR \"GICInterface->AEOIR\"                  |                | GICC_AEOIR       |                | \n| \\ref GICInterface_Type::AHPPIR \"GICInterface->AHPPIR\"                |                | GICC_AHPPIR      |                | \n| \\ref GICInterface_Type::STATUSR \"GICInterface->STATUSR\"              |                |                  |                | \n| \\ref GICInterface_Type::APR \"GICInterface->APR[]\"                    |                | GICC_APR0        |                | \n| \\ref GICInterface_Type::NSAPR \"GICInterface->NSAPR[]\"                |                | GICC_NSAPR0      |                | \n| \\ref GICInterface_Type::IIDR \"GICInterface->IIDR\"                    | ICCIIDR        | GICC_IIDR        | ICCIDR         | \n| \\ref GICInterface_Type::DIR \"GICInterface->DIR\"                      |                | GICC_DIR         |                | \n\n*/\n\n/** @{ */\n\n/**\n\\fn __STATIC_INLINE void GIC_EnableDistributor(void)\n\\details Globally enable the forwarding of interrupts to the CPU interfaces.\n\n\\fn __STATIC_INLINE void GIC_DisableDistributor(void)\n\\details Globally disable the forwarding of interrupts to the CPU interfaces.\n\\see GIC_EnableDistributor\n\n\\fn __STATIC_INLINE uint32_t GIC_DistributorInfo(void)\n\\details \nProvides information about the configuration of the GIC. It indicates:\n - whether the GIC implements the Security Extensions\n - the maximum number of interrupt IDs that the GIC supports\n - the number of CPU interfaces implemented\n - if the GIC implements the Security Extensions, the maximum number of\nimplemented Lockable Shared Peripheral Interrupts (LSPIs).\n\n\\fn __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)\n\\details\nProvides information about the implementer and revision of the Distributor.\n\n\\fn __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)\n\\details \nThe \\ref GICDistributor_Type.ITARGETSR \"ITARGETSR\" registers provide an 8-bit CPU targets field\nfor each interrupt supported by the GIC. This field stores the list of target processors for the\ninterrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the\ninterrupt if it is asserted and has sufficient priority.\n\n\\fn __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)\n\\details\nRead the current interrupt to CPU assignment for the given interrupt.\n\\see GIC_SetTarget\n\n\\fn __STATIC_INLINE void GIC_EnableInterface(void)\n\\details\nSets the Enable bit in the local CPUs \\ref GICInterface_Type.CTLR \"CTLR\" register.\nOnly the CPU executing the call is affected.\n\n\\fn __STATIC_INLINE void GIC_DisableInterface(void)\n\\details\nResets the Enable bit in the local CPUs \\ref GICInterface_Type.CTLR \"CTLR\" register.\nOnly the CPU executing the call is affected.\n\n\\fn __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)\n\\details \nProvides the interrupt number of the highest priority interrupt pending.\nA read of this register acts as an acknowledge for the interrupt.\n\nThe read returns a spurious interrupt number of 1023 if any of the following apply:\n - Forwarding of interrupts by the Distributor to the CPU interface is disabled.\n - Signaling of interrupts by the CPU interface to the connected PE is disabled.\n - There are no pending interrupts on the CPU interface with sufficient priority for the interface to signal it to the PE.\n\n\\see GIC_EndInterrupt\n \n\\fn __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)\nA write to this register performs priority drop for the specified interrupt.\n\nFor nested interrupts, the order of calls to this function must be the reverse of the order of interrupt\nacknowledgement, i.e. calls to \\ref GIC_AcknowledgePending. Behavior is UNPREDICTABLE if:\n - This ordering constraint is not maintained.\n - The given interrupt number does not match an active interrupt, or the ID of a spurious interrupt.\n - The given interrupt number does not match the last valid interrupt value returned by \\ref GIC_AcknowledgePending.\n \n\\fn __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)\n\\details \nEnables forwarding of the corresponding interrupt to the CPU interfaces.\n\n\\fn __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)\n\\details\nDisables forwarding of the corresponding interrupt to the CPU interfaces.\n\n\\fn __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)\n\\details\nAdds the pending state to the corresponding interrupt.\n\n\\fn __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)\n\\details\nRemoves the pending state from the corresponding interrupt.\n\n\\fn __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n\\details \nConfigures the priority of the given interrupt.\n\nThe available interrupt priorities are IMPLEMENTATION DEFINED. In order to\nquery the actual priorities one can \n\n\\code\nGIC_SetPriority(IRQn_TIM1, UINT32_MAX);       // try to configure lowest possible priority\nuint32_t actual = GIC_GetPriority(IRQn_TIM1); // retrieve actual lowest priority usable\n\\endcode\n\n\\fn __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)\n\\details \nCan be used to retrieve the actual priority depending on the GIC implementation.\n\\see GIC_SetPriority\n\n\\fn __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)\n\\details\nOnly interrupts with a higher priority (lower values) than the value provided are signaled.\n\n\\fn __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)\n\\see GIC_SetInterfacePriorityMask\n\n\\fn __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)\n\\details\nThe binary point defines the amount of priority bits used as a group priority and subpriorities.\n\nInterrupts sharing the same group priority do not preempt each other. But interrupts having a\nhigher group priority (lower value) preempt interrups with a lower group priority.\n\nThe subpriority defines the execution sequence of interrupts with the same group priority if\nmultiple are pending at time.\n\n\\fn __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)\n\\details\n\\see GIC_SetBinaryPoint\n\n\\fn __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)\n\\details \nThe return value is a combination of GIC's \\ref GICDistributor_Type::ISACTIVER \"ISACTIVER\" \nand \\ref GICDistributor_Type::ISPENDR \"ISPENDR\" registers.\n\nBit 0 denotes interrupts pending bit (interrupt should be handled) and bit 1 denotes interrupts\nactive bit (interrupt is currently handled).\n\n\\fn __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)\n\\fn __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) \n\\fn __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)\n\\fn __STATIC_INLINE void GIC_DistInit(void)\n\\details\nAll shared peripheral interrupts (SPIs) are initialized to be\n - disabled\n - level-sensitive, 1-N model\n - priority 0x7F\n - targeting CPU0\nand the distributor is enabled.\n \n\\see\nGIC_DisableIRQ\\n\nGIC_SetLevelModel\\n\nGIC_SetPriority\\n\nGIC_SetTarget\\n\nGIC_EnableDistributor\n\n\\fn __STATIC_INLINE void GIC_CPUInterfaceInit(void)\n\\details\nAll software generated (SGIs) and private peripheral interrupts (PPIs) are initialized to be\n - disabled\n - level-sensitive, 1-N model\n - priority 0x7F\nand the interrupt interface is enabled.\n\nThe binary point is set to zero. \n\nThe interrupt priority mask is set to 0xFF.\n\n\\see\nGIC_DisableIRQ\\n\nGIC_SetLevelModel\\n\nGIC_SetPriority\\n\nGIC_EnableInterface\\n\nGIC_SetBinaryPoint\\n\nGIC_SetInterfacePriorityMask\\n\n\n\\fn __STATIC_INLINE void GIC_Enable(void)\n\\details\nInitializes the distributor and the cpu interface.\n\n\\see\nGIC_DistInit\nGIC_CPUInterfaceInit\n*/\n\n/**\n\\def GICDistributor\n\\details\nUse GICDistributor to access the GIC Distributor registers.\n\n\\b Example:\n\\code\nGICDistributor->CTRL |= 1; // Enable group 0 interrupts\n\\endcode\n*/\n\n/**\n\\def GICInterface\n\\details\nUse GICInterface to access the GIC Interface registers.\n\n\\b Example:\n\\code\nGICInterface->CTLR |= 1; // Enable interrupt signaling\n\\endcode\n*/\n\n/**\n\\struct GICInterface_Type\n\n\\struct GICDistributor_Type\n*/\n\n/** @} */\n\n/* ########################## GICInterface_Type Member ########################## */\n/**\n\\var __IOM uint32_t GICInterface_Type::CTLR\n\\details CPU Interface Control Register\n\nEnables the signaling of interrupts by the CPU interface to the connected processor, and\nprovides additional top-level control of the CPU interface. In a GICv2 implementation, this\nincludes control of the end of interrupt (EOI) behavior.\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:1]  | -             | Reserved.                                                      |\n| [0]     | Enable        | Interrupt signaling: 0 - Disable. 1 - Enable.                  |\n\n\\var __IM uint32_t GICInterface_Type::IAR\n\\details CPU Interface Interrupt Acknowledge Register\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:24] | -             | Reserved.                                                      |\n| [23:0]  | INTID         | The interrupt number of the signaled interrupt.                |\n\n\\var __OM uint32_t GICInterface_Type::EOIR\n\\details CPU Interface End Of Interrupt Register\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:24] | -             | Reserved.                                                      |\n| [23:0]  | INTID         | The interrupt number of the finished interrupt.                |\n \n \\var __IM uint32_t GICInterface_Type::HPPIR\n\\details CPU Interface Highest Priority Pending Interrupt Register\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:24] | -             | Reserved.                                                      |\n| [23:0]  | INTID         | The INTID of the signaled interrupt.                           |\n\n\\var  __IM uint32_t GICInterface_Type::IIDR\n\\details CPU Interface Identification Register\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:20] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |\n| [19:16] | Arch_version  | The version of the GIC architecture that is implemented.       |\n| [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number for the CPU interface. |\n| [11:0]  | Implementer   | Contains the JEP106 code of the company that implemented the CPU interface. |\n\n\n\\var __IOM uint32_t GICInterface_Type::PMR\n\\details CPU Interface Priority Mask Register\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:8]  | -             | Reserved.                                                      |\n| [7:0]   | Priority      | The priority mask level for the CPU interface.                 |\n\n\\note IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI.\n \n\\var __IOM uint32_t GICInterface_Type::BPR\n\\details CPU Interface Binary Point Register\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:3]  | -             | Reserved.                                                      |\n| [2:0]   | Binary_Point  | Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field. |\n\nThe binary point (values 0-7) defines the amount of priority bits used as subpriority. Please\nrefer to the section Interrupt prioritization in the\n<a href=\"http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html\">Arm Generic Interrupt Controller Architecture Specificaton</a>\nfor details.\n\n\\var __IOM uint32_t GICInterface_Type::ABPR\n\\details CPU Interface Aliased Binary Point Register\n\\see GICInterface_Type::BPR\n\n\\var __OM uint32_t GICInterface_Type::AEOIR\n\\details CPU Interface Aliased End Of Interrupt Register\n\\see GICInterface_Type::EOIR\n\n\\var __IM uint32_t GICInterface_Type::AHPPIR\n\\details CPU Interface Aliased Highest Priority Pending Interrupt Register\n\\see GICInterface_Type::HPPIR\n\n\\var __IM uint32_t GICInterface_Type::AIAR\n\\details CPU Interface Aliased Interrupt Acknowledge Register\n\\see GICInterface_Type::IAR\n\n\\var __IOM uint32_t GICInterface_Type::APR[4]\n\\details CPU Interface Active Priorities Registers\n\\note The register values are IMPLEMENTATION DEFINED.\n\n\\var __OM uint32_t GICInterface_Type::DIR\n\\details CPU Interface Deactivate Interrupt Register\n\n| Bits    | Name  | Function                                                       |\n| :------ | :---- | :------------------------------------------------------------- |\n| [31:24] | -     | Reserved.                                                      |\n| [23:0]  | INTID | The INTID of the interrupt to be disabled.                     |\n\n\\var __IOM uint32_t GICInterface_Type::NSAPR[4]\n\\details CPU Interface Non-secure Active Priorities Registers\n\\note The register values are IMPLEMENTATION DEFINED.\n\\see GICInterface_Type::APR[4]\n\n\\var __IM uint32_t GICInterface_Type::RPR\n\\details CPU Interface Running Priority Register\n\n| Bits    | Name     | Function                                                       |\n| :------ | :------- | :------------------------------------------------------------- |\n| [31:8]  | -        | Reserved.                                                      |\n| [7:0]   | Priority | The current running priority on the CPU interface.             |\n\n\\var __IOM uint32_t GICInterface_Type::STATUSR\n\\details CPU Interface Status Register\n\n| Bits    | Name     | Function                                                       |\n| :------ | :------- | :------------------------------------------------------------- |\n| [31:5]  | -        | Reserved.                                                      |\n| [4]     | ASV      | Attempted security violation.                                  |\n| [3]     | WROD     | Write to an RO location.                                       |\n| [2]     | RWOD     | Read of a WO location.                                         |\n| [1]     | WRD      | Write to a reserved location.                                  |\n| [0]     | RRD      | Read of a reserved location.                                   |\n*/\n\n/* ########################## GICDistributor_Type Member ########################## */\n/**\n\\var __IOM uint32_t GICDistributor_Type::CTLR\n\\details Distributor Control Register\n\nWhen access is Secure, in a system that supports two Security states:\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31]    | RWP           | Indicates whether a register write is in progress or not.      |\n| [30:8]  | -             | Reserved.                                                      |\n| [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |\n| [6]     | DS            | Disable Security.                                              |\n| [5]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |\n| [4]     | ARE_S         | Affinity Routing Enable, Secure state.                         |\n| [3]     | -             | Reserved.                                                      |\n| [2]     | EnableGrp1S   | Enable Secure Group 1 interrupts.                              |\n| [1]     | EnableGrp1NS  | Enable Non-secure Group 1 interrupts.                          |\n| [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |\n\nWhen access is Non-secure, in a system that supports two Security states:\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31]    | RWP           | Indicates whether a register write is in progress or not.      |\n| [30:5]  | -             | Reserved.                                                      |\n| [4]     | ARE_NS        | Affinity Routing Enable, Non-secure state.                     |\n| [3:2]   | -             | Reserved.                                                      |\n| [1]     | EnableGrp1A   | Enable Non-secure Group 1 interrupts.                          |\n| [0]     | EnableGrp1    | Enable Non-secure Group 1 interrupts.                          |\n\nWhen in a system that supports only a single Security state:\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31]    | RWP           | Indicates whether a register write is in progress or not.      |\n| [30:8]  | -             | Reserved.                                                      |\n| [7]     | EINWF         | Enable 1 of N Wakeup Functionality, if available.              |\n| [6]     | DS            | Disable Security.                                              |\n| [5]     | -             | Reserved.                                                      |\n| [4]     | ARE           | Affinity Routing Enable.                                       |\n| [3:2]   | -             | Reserved.                                                      |\n| [1]     | EnableGrp1    | Enable Group 1 interrupts.                                     |\n| [0]     | EnableGrp0    | Enable Group 0 interrupts.                                     |\n\n\\var __IM uint32_t GICDistributor_Type::TYPER\n\\details Interrupt Controller Type Register\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:16] | -             | Reserved.                                                      |\n| [15:11] | LSPI          | Maximum number of lockable shared interrupts.                  |\n| [10]    | SecurityExtn  | Security Extensions: 0 - not implemented. 1 - implemented.     |\n| [9:8]   | -             | Reserved.                                                      |\n| [7:5]   | CPUNumber     | Number of implemented CPU interfaces [=CPUNumber+1]            |\n| [4:0]   | ITLinesNumber | Maximum number of interrups supported [=32*(ITLinesNumber+1)]. |\n\n\\var __IM uint32_t GICDistributor_Type::IIDR\n\\details Distributor Implementer Identification Register\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:24] | ProductID     | An IMPLEMENTATION DEFINED product identifier                   |\n| [23:20] | -             | Reserved.                                                      |\n| [19:16] | Variant       | An IMPLEMENTATION DEFINED variant number.                      |\n| [15:12] | Revision      | An IMPLEMENTATION DEFINED revision number.                     |\n| [11:0]  | Implementer   | Contains the JEP106 code of the company implemented the GICD.  |\n\n\\var __IOM uint8_t GICDistributor_Type::ITARGETSR[1020]\n\\details Interrupt Processor Targets Registers\n\nEach bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds\nto an unimplemented CPU interface is RAZ/WI.\n\n| CPU target field value | Interrupt targets |\n| :--------------------- | :---------------- |\n| 0bxxxxxxx1             | CPU interface 0   |\n| 0bxxxxxx1x             | CPU interface 1   |\n| 0bxxxxx1xx             | CPU interface 2   |\n| 0bxxxx1xxx             | CPU interface 3   |\n| 0bxxx1xxxx             | CPU interface 4   |\n| 0bxx1xxxxx             | CPU interface 5   |\n| 0bx1xxxxxx             | CPU interface 6   |\n| 0b1xxxxxxx             | CPU interface 7   |\n\n\\var __IOM uint32_t GICDistributor_Type::IGROUPR[32]\n\\details Interrupt Group Registers\n\nEach bit corresponds to one interrupt:\n - Register index is given by INTID/32\n - Bit number is given by INTID%32\n \nAnd the value denotes:\n- 0 When \\ref GICDistributor_Type::CTLR \"CTLR\".DS==1, the corresponding interrupt is Group 0\\n\n    When \\ref GICDistributor_Type::CTLR \"CTLR\".DS==0, the corresponding interrupt is Secure.\n- 1 When \\ref GICDistributor_Type::CTLR \"CTLR\".DS==1, the corresponding interrupt is Group 1.\\n\n    When \\ref GICDistributor_Type::CTLR \"CTLR\".DS==0, the corresponding interrupt is Non-secure Group 1.\n \n\\var __IO uint32_t GICDistributor_Type::CLRSPI_NSR\n\\details Clear Non-secure SPI Pending Register\n\n| Bits    | Name          | Function                                          |\n| :------ | :------------ | :------------------------------------------------ | \n| [31:10] | -             | Reserved.                                         |\n| [9:0]   | INTID         | The interrupt number to clear pending state from. |\n\n\\var __IO uint32_t GICDistributor_Type::CLRSPI_SR\n\\details Clear Secure SPI Pending Register\n\n| Bits    | Name          | Function                                          |\n| :------ | :------------ | :------------------------------------------------ | \n| [31:10] | -             | Reserved.                                         |\n| [9:0]   | INTID         | The interrupt number to clear pending state from. |\n\n\\var __IOM uint32_t GICDistributor_Type::IGRPMODR[32]\n\\details Interrupt Group Modifier Registers\n\nEach bit corresponds to one interrupt:\n - Register index is given by INTID/32\n - Bit number is given by INTID%32\n \n\\var __IOM uint64_t GICDistributor_Type::IROUTER[988]\n\\details Interrupt Routing Registers\n\n| Bits    | Name          | Function                                                      |\n| :------ | :------------ | :------------------------------------------------------------ | \n| [63:40] | -             | Reserved.                                                     |\n| [39:32] | Aff3          | Affinity level 3, the least significant affinity level field. |\n| [31]    | IRM           | Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy. |\n| [30:24] | -             | Reserved.                                                     |\n| [23:16] | Aff2          | Affinity level 2, an intermediate affinity level field.       | \n| [15:8]  | Aff1          | Affinity level 1, an intermediate affinity level field.       |\n| [7:0]   | Aff0          | Affinity level 0, the most significant affinity level field.  |\n\n\\var __IOM uint32_t GICDistributor_Type::NSACR[64]\n\\details Non-secure Access Control Registers\n\nEach two bits corresponds to one interrupt:\n - Register index is given by INTID/16\n - Bit number is given by 2*INTID%16\n\nThe possible values of each 2-bit field are:\n - 00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.\n - 01 - Non-secure accesses are only permitted to requesting fields.\n - 10 - As 01, additionally accesses to clearing field are permitted.\n - 11 - As 10, additionally accesses to target and routing fields are permitted.\n \n\\var __IO uint32_t GICDistributor_Type::SETSPI_NSR\n\\details Set Non-secure SPI Pending Register\n\n| Bits    | Name          | Function                                          |\n| :------ | :------------ | :------------------------------------------------ | \n| [31:10] | -             | Reserved.                                         |\n| [9:0]   | INTID         | The interrupt number to set pending state for.    |\n\n\\var __IO uint32_t GICDistributor_Type::SETSPI_SR\n\\details Set Secure SPI Pending Register\n\n| Bits    | Name          | Function                                          |\n| :------ | :------------ | :------------------------------------------------ | \n| [31:10] | -             | Reserved.                                         |\n| [9:0]   | INTID         | The interrupt number to set pending state for.    |\n\n\\var __IOM uint8_t GICDistributor_Type::SPENDSGIR[16]\n\\details SGI Set-Pending Registers\nEach register corresponds to one software generated interrupt (SGI).\n\nReading from this register reveals\n - 0 - interrupt is not pending\n - 1 - interrupt is pending\n \nWriting to this register causes\n - 0 - no effect\n - 1 - adds the pending state\n \n\\var __IOM uint8_t GICDistributor_Type::CPENDSGIR[16]\n\\details SGI Clear-Pending Registers\nEach register corresponds to one software generated interrupt (SGI).\n\nReading from this register reveals\n - 0 - interrupt is not pending\n - 1 - interrupt is pending\n \nWriting to this register causes\n - 0 - no effect\n - 1 - removes the pending state\n\n\\var __IOM uint32_t GICDistributor_Type::STATUSR\n\\details Error Reporting Status Register\n\n| Bits    | Name          | Function                                          |\n| :------ | :------------ | :------------------------------------------------ | \n| [31:4]  | -             | Reserved.                                         |\n| [3]     | WROD          | Write to an RO location.                          |\n| [2]     | RWOD          | Read of a WO location.                            |\n| [1]     | WRD           | Write to a reserved location.                     |\n| [0]     | RRD           | Read of a reserved location.                      |\n\n\\var __IOM uint32_t GICDistributor_Type::ISENABLER[32]\n\\details Interrupt Set-Enable Registers\n\nEach bit corresponds to one interrupt:\n - Register index is given by INTID/32\n - Bit number is given by INTID%32\n\n\\note Bits corresponding to unimplemented interrupts are RAZ/WI.\n\n\\var __IOM uint32_t GICDistributor_Type::ICENABLER[32]\n\\details Interrupt Clear-Enable Registers\n\nEach bit corresponds to one interrupt:\n - Register index is given by INTID/32\n - Bit number is given by INTID%32\n\n\\note Bits corresponding to unimplemented interrupts are RAZ/WI.\n\n\\var __IOM uint32_t GICDistributor_Type::ISPENDR[32]\n\\details Interrupt Set-Pending Registers\n\nEach bit corresponds to one interrupt:\n - Register index is given by INTID/32\n - Bit number is given by INTID%32\n\n\\note Bits corresponding to unimplemented interrupts are RAZ/WI.\n\n\\var __IOM uint32_t GICDistributor_Type::ICPENDR[32]\n\\details Interrupt Clear-Pending Registers\n\nEach bit corresponds to one interrupt:\n - Register index is given by INTID/32\n - Bit number is given by INTID%32\n \n\\note Bits corresponding to unimplemented interrupts are RAZ/WI.\n\n\\var __IOM uint32_t GICDistributor_Type::ICFGR[64]\n\\details Interrupt Configuration Registers\n\nEach interrupt can be configured by two corresponding bits:\n\n| Bits           | Name          | Function                                                       |\n| :------------- | :------------ | :------------------------------------------------------------- |\n| [2*INTID%16+1] | Edge          | Interrupt is: 0 - level sensitive, 1 - edge triggered          |\n| [2*INTID%16]   | Model         | 0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported          |\n\n\\var __IOM uint8_t GICDistributor_Type::IPRIORITYR[1020]\n\\details Interrupt Priority Registers\n\nA GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each\nfield. In each field, unimplemented bits are RAZ/WI.\n\n\\note A register field corresponding to an unimplemented interrupt is RAZ/WI.\n\n\\var __IOM uint32_t GICDistributor_Type::ISACTIVER[32]\n\\details Interrupt Set-Active Registers\n\nEach bit corresponds to one interrupt:\n - Register index is given by INTID/32\n - Bit number is given by INTID%32\n \n\\note Bits corresponding to unimplemented interrupts are RAZ/WI.\n\n\\var __IOM uint32_t GICDistributor_Type::ICACTIVER[32]\n\\details Interrupt Clear-Active Registers\n\nEach bit corresponds to one interrupt:\n - Register index is given by INTID/32\n - Bit number is given by INTID%32\n\n\\note Bits corresponding to unimplemented interrupts are RAZ/WI.\n\n\\var __OM uint32_t GICDistributor_Type::SGIR\n\\details Software Generated Interrupt Register\n\n| Bits    | Name             | Function                                                         |\n| :------ | :------------    | :--------------------------------------------------------------- |\n| [31:26] | -                | Reserved.                                                        |\n| [25:24] | TargetFilterList | Determines how the Distributor processes the requested SGI.      |\n| [23:16] | CPUTargetList    | When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt. |\n| [15]    | NSATT            | Specifies the required group of the SGI.                         |\n| [14:4]  | -                | Reserved.                                                        |\n| [3:0]   | INTID            | The INTID of the SGI to forward to the specified CPU interfaces. |\n\nRefer to \\ref GICDistributor_Type::ITARGETSR \"ITARGETSR\" for details on TargetFilterList field.\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/ref_mmu.txt",
    "content": "/* ##########################  MMU functions  ###################################### */\n/**\n\\defgroup MMU_functions Memory Management Unit Functions\n\\ingroup CMSIS_Core_FunctionInterface\n\\brief MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.\\n\nReference: <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html\">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a>.\n*/\n\n/** @{ */\n\n/**\n\\fn __STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)\n\\details \n  The function sets section execution-never attribute\n\n\\fn __STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)\n\\details \nThe function sets section domain.\n\n\\fn __STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)\n\\details\n  The function sets section parity check\n\n\\fn __STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)\n\\details \nThe function sets section access privileges\n\n\\fn __STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)\n\\details\n  The function sets section shareability\n\n\\fn __STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)\n\\details\n  The function sets section Global attribute\n\n\\fn __STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)\n\\details\n  The function sets section Global attribute\n\n\\fn __STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)\n\\details\n  The function sets 4k/64k page execution-never attribute\n\n\\fn __STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)\n\\details\n  The function sets 4k/64k page domain\n\n\\fn __STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)\n\\details\n  The function sets 4k/64k page parity check\n\n\\fn __STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)\n\\details\n  The function sets 4k/64k page access privileges\n\\fn __STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)\n\\details\n  The function sets 4k/64k page shareability\n\n\\fn __STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)\n\\details\n  The function sets 4k/64k page Global attribute\n\n\\fn __STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)\n\\details\n  The function sets 4k/64k page Global attribute\n\n\\fn __STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)\n\\details\n  The function sets section memory attributes\n\n\\fn __STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)\n\\details\n  The function sets 4k/64k page memory attributes\n\n\\fn __STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)\n\\details\n  The function creates a section descriptor.\n\n\\fn __STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)\n\\details\n  The function creates a 4k/64k page descriptor.\n  Assumptions:\n  - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor\n  - Functions always return 0\n\n\\fn __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)\n\\fn __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )\n\\fn __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )\n\\fn __STATIC_INLINE void MMU_Enable(void) \n\\details \n   Set M bit 0 to enable the MMU\n   Set AFE bit to enable simplified access permissions model\n   Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking\n\n\\fn __STATIC_INLINE void MMU_Disable(void)\n\n\\fn __STATIC_INLINE void MMU_InvalidateTLB(void) \n*/\n\n/** @} */\n/* end of MMU_functions */\n\n/**\n\\defgroup MMU_defs_gr MMU Defines and Structs\n\\ingroup MMU_functions\n\\brief Defines and structures that relate to the Memory Management Unit\n*/\n\n/** @{ */\n\n/**\n\\def SECTION_DESCRIPTOR\n\\def SECTION_B_SHIFT\n\\def SECTION_C_SHIFT\n\\def SECTION_TEX0_SHIFT      \n\\def SECTION_TEX1_SHIFT      \n\\def SECTION_TEX2_SHIFT      \n\\def SECTION_XN_SHIFT        \n\\def SECTION_DOMAIN_SHIFT    \n\\def SECTION_P_SHIFT         \n\\def SECTION_AP_SHIFT        \n\\def SECTION_AP2_SHIFT       \n\\def SECTION_S_SHIFT         \n\\def SECTION_NG_SHIFT        \n\\def SECTION_NS_SHIFT        \n\\def PAGE_L1_DESCRIPTOR      \n\\def PAGE_L2_4K_DESC         \n\\def PAGE_L2_64K_DESC        \n\\def PAGE_4K_B_SHIFT         \n\\def PAGE_4K_C_SHIFT         \n\\def PAGE_4K_TEX0_SHIFT      \n\\def PAGE_4K_TEX1_SHIFT      \n\\def PAGE_4K_TEX2_SHIFT      \n\\def PAGE_64K_B_SHIFT        \n\\def PAGE_64K_C_SHIFT        \n\\def PAGE_64K_TEX0_SHIFT     \n\\def PAGE_64K_TEX1_SHIFT     \n\\def PAGE_64K_TEX2_SHIFT     \n\\def PAGE_B_SHIFT            \n\\def PAGE_C_SHIFT            \n\\def PAGE_TEX_SHIFT          \n\\def PAGE_XN_4K_SHIFT        \n\\def PAGE_XN_64K_SHIFT       \n\\def PAGE_DOMAIN_SHIFT       \n\\def PAGE_P_SHIFT            \n\\def PAGE_AP_SHIFT           \n\\def PAGE_AP2_SHIFT          \n\\def PAGE_S_SHIFT            \n\\def PAGE_NG_SHIFT           \n\\def PAGE_NS_SHIFT           \n\\def OFFSET_1M               \n\\def OFFSET_64K              \n\\def OFFSET_4K               \n\\def DESCRIPTOR_FAULT             \n\n\\enum mmu_region_size_Type\n\\enum mmu_memory_Type\n\\enum mmu_cacheability_Type\n\\enum mmu_ecc_check_Type\n\\enum mmu_execute_Type\n\\enum mmu_global_Type\n\\enum mmu_shared_Type\n\\enum mmu_secure_Type\n\\enum mmu_access_Type\n\n\\struct  mmu_region_attributes_Type\n\n\\def section_normal(descriptor_l1, region) \n\\def section_normal_cod(descriptor_l1, region)\n\\def section_normal_ro(descriptor_l1, region)\n\\def section_normal_rw(descriptor_l1, region)\n\\def section_so(descriptor_l1, region)\n\\def section_device_ro(descriptor_l1, region)\n\\def section_device_rw(descriptor_l1, region)\n\\def page4k_device_rw(descriptor_l1, descriptor_l2, region)\n\\def page64k_device_rw(descriptor_l1, descriptor_l2, region) \n*/\n/** @} */ \n/* end group MMU_defs_gr */\n"
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Core_A/src/ref_timer.txt",
    "content": "/* ##########################  Generic Physical Timer functions  ############################ */\n/**\n\\defgroup PL1_timer_functions Generic Physical Timer Functions\n\\ingroup CMSIS_Core_FunctionInterface\n\\brief Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.\\n\nReference: <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html\">Cortex-A7 MPCore Technical Reference Manual</a>.\n*/\n/** @{ */\n\n/** \\brief Physical Timer Control register */\ntypedef union\n{\n  struct\n  {\n    uint32_t ENABLE:1;      /*!< \\brief bit: 0      Enables the timer. */\n    uint32_t IMASK:1;       /*!< \\brief bit: 1      Timer output signal mask bit. */\n    uint32_t ISTATUS:1;     /*!< \\brief bit: 2      The status of the timer. */\n    uint32_t _reserved0:29; /*!< \\brief bit: 3..31  Reserved */\n  } b;                      /*!< \\brief Structure used for bit  access */\n  uint32_t w;               /*!< \\brief Type      used for word access */\n} CNTP_CTL_Type;\n\n/** Configures the frequency the timer shall run at.\n* \\param value The timer frequency in Hz.\n*/\n__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value);\n\n/** Sets the reset value of the timer.\n* \\param value The value the timer is loaded with.\n*/\n__STATIC_INLINE void PL1_SetLoadValue(uint32_t value);\n\n/** Get the current counter value.\n* \\return Current counter value.\n*/\n__STATIC_INLINE uint32_t PL1_GetCurrentValue();\n\n/** \\brief Get the current physical counter value.\n* \\return Current physical counter value.\n*/\n__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void);\n\n/** \\brief Set the physical compare value.\n* \\param [in] value New physical timer compare value.\n*/\n__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value);\n\n/** \\brief Get the physical compare value.\n* \\return Physical compare value.\n*/\n__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void);\n\n/** Configure the timer by setting the control value.\n* \\param value New \\ref CNTP_CTL_Type \"timer control value\".\n*/\n__STATIC_INLINE void PL1_SetControl(uint32_t value);\n\n/** Get the timer control value.\n* \\return \\ref CNTP_CTL_Type Timer control value.\n*/\n__STATIC_INLINE uint32_t PL1_GetControl();\n\n/** @} */\n\n/* ##########################  Private Timer functions  ############################ */\n/**\n\\defgroup PTM_timer_functions Private Timer Functions\n\\ingroup CMSIS_Core_FunctionInterface\n\\brief Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.\\n\nReferences: <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.ddi0434c/index.html\">Cortex-A5 MPCore Technical Reference Manual</a>,\n<a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.100486_0401_10_en/index.html\">Cortex-A9 MPCore Technical Reference Manual</a>.\n\n@{\n\\struct Timer_Type\n\\def PTIM\n\\fn __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)\n\\fn __STATIC_INLINE uint32_t PTIM_GetLoadValue()\n\\fn __STATIC_INLINE uint32_t PTIM_GetCurrentValue()\n\\fn __STATIC_INLINE void PTIM_SetControl(uint32_t value)\n\\fn __STATIC_INLINE uint32_t PTIM_GetControl(void)\n\\fn __STATIC_INLINE void PTIM_ClearEventFlag(void)\n@}\n*/\n\n/* ########################## Timer_Type Members ########################## */\n/**\n\\var __IOM uint32_t Timer_Type::LOAD\n\\details Private Timer Load Register\nThe Timer Load Register contains the value copied to the Timer Counter Register when\nit decrements down to zero with auto reload mode enabled. Writing to the Timer Load\nRegister means that you also write to the Timer Counter Register.\n\n\\var __IOM uint32_t Timer_Type::COUNTER\n\\details Private Timer Counter Register\nThe Timer Counter Register is a decrementing counter.\n\nThe Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register.\n\nWhen the Timer Counter Register reaches zero and auto reload mode is enabled, it\nreloads the value in the Timer Load Register and then decrements from that value. If\nauto reload mode is not enabled, the Timer Counter Register decrements down to zero\nand stops.\n\nWhen the Timer Counter Register reaches zero, the timer interrupt status event flag is\nset and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt\ngeneration is enabled in the Timer Control Register.\n\nWriting to the Timer Counter Register or Timer Load Register forces the Timer Counter\nRegister to decrement from the newly written value.\n\n\\var __IOM uint32_t Timer_Type::CONTROL\n\\details Private Timer Control Register\n\n| Bits    | Name          | Function                                                       |\n| :------ | :------------ | :------------------------------------------------------------- |\n| [31:16] | -             | Reserved.                                                      |\n| [15:8]  | Prescaler     | The prescaler modifies the clock period for the decrementing event for the Counter Register. |\n| [7:3]   | -             | Reserved.                                                      |\n| [2]     | IRQ Enable    | If set, the interrupt is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register. |\n| [1]     | Auto Reload   | If set, each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register. |\n| [0]     | Time Enabled  | If set, Timer is enabled and the counter decrements normally. |\n\n\\var __IM uint32_t Timer_Type::ISR\n\\details Private Timer Interrupt Status Register\n\nThe event flag is a sticky bit that is automatically set when the Counter Register reaches\nzero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt\nDistributor after the event flag is set. The event flag is cleared when written to 1.\n\n\\var __IOM uint32_t Timer_Type::WLOAD\n\\details Watchdog Load Register\n\nThe Watchdog Load Register contains the value copied to the Watchdog Counter\nRegister when it decrements down to zero with auto reload mode enabled, in Timer\nmode. Writing to the Watchdog Load Register means that you also write to the\nWatchdog Counter Register.\n\n\\var __IOM uint32_t Timer_Type::WCOUNTER\n\\details Watchdog Counter Register\n\nThe Watchdog Counter Register is a down counter.\n\nThe behavior of the watchdog when the Watchdog Counter Register reaches zero\ndepends on its current mode:\n - Timer mode: The watchdog interrupt status event flag is set and the interrupt\n   is set as pending in the Interrupt Distributor.\n - Watchdog mode: Tthe Watchdog reset status flag is set and the associated WDRESETREQ\n   reset request output pin is asserted.\n\n\\var __IOM uint32_t Timer_Type::WCONTROL\n\\details Watchdog Control Register\n\n| Bits    | Name            | Function                                                       |\n| :------ | :-------------- | :------------------------------------------------------------- |\n| [31:16] | -               | Reserved.                                                      |\n| [15:8]  | Prescaler       | The prescaler modifies the clock period for the decrementing event for the Counter Register. |\n| [7:4]   | -               | Reserved.                                                      |\n| [3]     | Watchdog Mode   | 0 - Timer mode (default), 1 - Watchdog mode                    |\n| [2]     | IT Enable       | Interrupt enable for timer mode.                               |\n| [1]     | Auto Reload     | 0 - Single shot mode, 1 - Continuous timer mode                |\n| [0]     | Watchdog Enable | 0 - Watchdog counter disabled, 1 - Watchdog timer enabled      |\n\n\\var __IOM uint32_t Timer_Type::WISR\n\\details Watchdog Interrupt Status Register\n\n| Bits    | Name            | Function                                                       |\n| :------ | :-------------- | :------------------------------------------------------------- |\n| [31:1]  | -               | Reserved.                                                      |\n| [0]     | Event Flag      | The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode. |\n\n\\var __IOM uint32_t Timer_Type::WRESET\n\\details Watchdog Reset Status Register\n\n| Bits    | Name            | Function                                                       |\n| :------ | :-------------- | :------------------------------------------------------------- |\n| [31:1]  | -               | Reserved.                                                      |\n| [0]     | Reset Flag      | The reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly. (In watchdog mode) | \n\n\\var __IM uint32_t Timer_Type::WDISABLE\n\\details Watchdog Disable Register\n\nUse the Watchdog Disable Register to switch from watchdog to timer mode. The\nsoftware must write 0x12345678 then 0x87654321 successively to the Watchdog Disable\nRegister so that the watchdog mode bit in the Watchdog Control Register is set to zero.\n*/\n\n/* ########################## Private Timer Member ########################## */\n/**\n\n\\var uint32_t CNTP_CTL_Type::ENABLE\n\\details Enables the timer.\n\nPermitted values are:\n - 0 - Timer disabled.\n - 1 - Timer enabled.\n\n\\var uint32_t CNTP_CTL_Type::IMASK\n\\details Timer output signal mask bit. \n\nPermitted values are:\n - 0 - Timer output signal is not masked.\n - 1 - Timer output signal is masked.\n\n\n\\var uint32_t CNTP_CTL_Type::ISTATUS\n\\details The status of the timer.\n\nThis bit indicates whether the timer condition is asserted:\n - 0 - Timer condition is not asserted.\n - 1 - Timer condition is asserted.\n*/\n"
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Doxygen\n# uses this value to replace tabs by spaces in code fragments.\n# Minimum value: 1, maximum value: 16, default value: 4.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that act as commands in\n# the documentation. An alias has the form:\n# name=value\n# For example adding\n# \"sideeffect=@par Side Effects:\\n\"\n# will allow you to put the command \\sideeffect (or @sideeffect) in the\n# documentation, which will result in a user-defined paragraph with heading\n# \"Side Effects:\". You can put \\n's in the value part of an alias to insert\n# newlines.\n\nALIASES                = \n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding \"class=itcl::class\"\n# will allow you to use the command class in the itcl::class meaning.\n\nTCL_SUBST              = \n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources\n# only. Doxygen will then generate output that is more tailored for C. For\n# instance, some of the names that are used will be different. The list of all\n# members will be omitted, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_FOR_C  = YES\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or\n# Python sources only. Doxygen will then generate output that is more tailored\n# for that language. For instance, namespaces will be presented as packages,\n# qualified scopes will look different, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources. Doxygen will then generate output that is tailored for Fortran.\n# The default value is: NO.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for VHDL.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given\n# extension. Doxygen has a built-in mapping, but you can override or extend it\n# using this tag. The format is ext=language, where ext is a file extension, and\n# language is one of the parsers supported by doxygen: IDL, Java, Javascript,\n# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C.\n#\n# Note For files without extension you can use no_extension as a placeholder.\n#\n# Note that for custom extensions you also need to set FILE_PATTERNS otherwise\n# the files are not read by doxygen.\n\nEXTENSION_MAPPING      = \n\n# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments\n# according to the Markdown format, which allows for more readable\n# documentation. See http://daringfireball.net/projects/markdown/ for details.\n# The output of markdown processing is further processed by doxygen, so you can\n# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in\n# case of backward compatibilities issues.\n# The default value is: YES.\n\nMARKDOWN_SUPPORT       = YES\n\n# When enabled doxygen tries to link words that correspond to documented\n# classes, or namespaces to their corresponding documentation. Such a link can\n# be prevented in individual cases by by putting a % sign in front of the word\n# or globally by setting AUTOLINK_SUPPORT to NO.\n# The default value is: YES.\n\nAUTOLINK_SUPPORT       = YES\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should set this\n# tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string);\n# versus func(std::string) {}). This also make the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n# The default value is: NO.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n# The default value is: NO.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:\n# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen\n# will parse them like normal C++ but will assume all classes use public instead\n# of private inheritance when no explicit protection keyword is present.\n# The default value is: NO.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate\n# getter and setter methods for a property. Setting this option to YES will make\n# doxygen to replace the get and set methods by a property in the documentation.\n# This will only work if the methods are indeed getting or setting a simple\n# type. If this is not the case, or you want to show the methods anyway, you\n# should set this option to NO.\n# The default value is: YES.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n# The default value is: NO.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES to allow class member groups of the same type\n# (for instance a group of public functions) to be put as a subgroup of that\n# type (e.g. under the Public Functions section). Set it to NO to prevent\n# subgrouping. Alternatively, this can be done per class using the\n# \\nosubgrouping command.\n# The default value is: YES.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions\n# are shown inside the group in which they are included (e.g. using \\ingroup)\n# instead of on a separate page (for HTML and Man pages) or section (for LaTeX\n# and RTF).\n#\n# Note that this feature does not work in combination with\n# SEPARATE_MEMBER_PAGES.\n# The default value is: NO.\n\nINLINE_GROUPED_CLASSES = NO\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions\n# with only public data fields or simple typedef fields will be shown inline in\n# the documentation of the scope in which they are defined (i.e. file,\n# namespace, or group documentation), provided this scope is documented. If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = NO\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = NO\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = YES\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = YES\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = NO\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = NO\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = NO\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = NO\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= NO\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = \n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = NO\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = NO\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         = \n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = ./src \\\n                         ../../DAP/Firmware/Template \\\n                         ../../DAP/Firmware/Config\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          = *.h \\\n                         *.txt \\\n                         *.c\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = NO\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s \\\n                         src/exclude/\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = NO\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       = \n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        = \n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = ../../DAP\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           = \n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        = \n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS = \n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE = \n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = YES\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = YES\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = YES\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = NO\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 3\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = \n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../Doxygen_Templates/printComponentTabs.js\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 106\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 0\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = CMSIS_Core.chm\n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \"C:/Program Files/HTML Help Workshop/hhc.exe\"\n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     = \n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               = \n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   = \n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  = \n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  = \n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           = \n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     = \n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       = \n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       = \n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     = \n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         = \n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           = \n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           = \n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      = \n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    = \n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             = \n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                = \n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen\n# Definitions (see http://autogen.sf.net) file that captures the structure of\n# the code including all documentation. Note that this feature is still\n# experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES doxygen will generate a Perl module\n# file that captures the structure of the code including all documentation.\n#\n# Note that this feature is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES doxygen will generate the necessary\n# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI\n# output from the Perl module output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be nicely\n# formatted so it can be parsed by a human reader. This is useful if you want to\n# understand what is going on. On the other hand, if this tag is set to NO the\n# size of the Perl module output will be much smaller and Perl will parse it\n# just the same.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_PRETTY         = YES\n\n# The names of the make variables in the generated doxyrules.make file are\n# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful\n# so different doxyrules.make files included by the same Makefile don't\n# overwrite each other's variables.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_MAKEVAR_PREFIX = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the preprocessor\n#---------------------------------------------------------------------------\n\n# If the ENABLE_PREPROCESSING tag is set to YES doxygen will evaluate all\n# C-preprocessor directives found in the sources and include files.\n# The default value is: YES.\n\nENABLE_PREPROCESSING   = YES\n\n# If the MACRO_EXPANSION tag is set to YES doxygen will expand all macro names\n# in the source code. If set to NO only conditional compilation will be\n# performed. Macro expansion can be done in a controlled way by setting\n# EXPAND_ONLY_PREDEF to YES.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nMACRO_EXPANSION        = NO\n\n# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then\n# the macro expansion is limited to the macros specified with the PREDEFINED and\n# EXPAND_AS_DEFINED tags.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_ONLY_PREDEF     = NO\n\n# If the SEARCH_INCLUDES tag is set to YES the includes files in the\n# INCLUDE_PATH will be searched if a #include is found.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSEARCH_INCLUDES        = YES\n\n# The INCLUDE_PATH tag can be used to specify one or more directories that\n# contain include files that are not input files but should be processed by the\n# preprocessor.\n# This tag requires that the tag SEARCH_INCLUDES is set to YES.\n\nINCLUDE_PATH           = \n\n# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard\n# patterns (like *.h and *.hpp) to filter out the header-files in the\n# directories. If left blank, the patterns specified with FILE_PATTERNS will be\n# used.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nINCLUDE_FILE_PATTERNS  = \n\n# The PREDEFINED tag can be used to specify one or more macro names that are\n# defined before the preprocessor is started (similar to the -D option of e.g.\n# gcc). The argument of the tag is a list of macros of the form: name or\n# name=definition (no spaces). If the definition and the \"=\" are omitted, \"=1\"\n# is assumed. To prevent a macro definition from being undefined via #undef or\n# recursively expanded use the := operator instead of the = operator.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nPREDEFINED             = \n\n# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this\n# tag can be used to specify a list of macro names that should be expanded. The\n# macro definition that is found in the sources will be used. Use the PREDEFINED\n# tag if you want to use a different macro definition that overrules the\n# definition found in the source code.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_AS_DEFINED      = \n\n# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will\n# remove all refrences to function-like macros that are alone on a line, have an\n# all uppercase name, and do not end with a semicolon. Such function macros are\n# typically used for boiler-plate code, and will confuse the parser if not\n# removed.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSKIP_FUNCTION_MACROS   = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to external references\n#---------------------------------------------------------------------------\n\n# The TAGFILES tag can be used to specify one or more tag files. For each tag\n# file the location of the external documentation should be added. The format of\n# a tag file without this location is as follows:\n# TAGFILES = file1 file2 ...\n# Adding location for the tag files is done as follows:\n# TAGFILES = file1=loc1 \"file2 = loc2\" ...\n# where loc1 and loc2 can be relative or absolute paths or URLs. See the\n# section \"Linking to external documentation\" for more information about the use\n# of tag files.\n# Note: Each tag file must have an unique name (where the name does NOT include\n# the path). If a tag file is not located in the directory in which doxygen is\n# run, you must also specify the path to the tagfile here.\n\nTAGFILES               = \n\n# When a file name is specified after GENERATE_TAGFILE, doxygen will create a\n# tag file that is based on the input files it reads. See section \"Linking to\n# external documentation\" for more information about the usage of tag files.\n\nGENERATE_TAGFILE       = \n\n# If the ALLEXTERNALS tag is set to YES all external class will be listed in the\n# class index. If set to NO only the inherited external classes will be listed.\n# The default value is: NO.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in\n# the modules index. If set to NO, only the current project's groups will be\n# listed.\n# The default value is: YES.\n\nEXTERNAL_GROUPS        = YES\n\n# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in\n# the related pages index. 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    "path": "external/CMSIS_5/CMSIS/DoxyGen/DAP/src/dap.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\mainpage Firmware for CoreSight Debug Access Port\n\n<b>CMSIS-DAP</b> is a <b>protocol</b> specification and a implementation of a <b>firmware</b> that supports access to the\n<a href=\"https://developer.arm.com/documentation/102585/0000/what-is-a-debug-access-port\" target=\"_blank\"><b>CoreSight Debug Access Port (DAP)</b></a>.\n\nThe various Arm Cortex processors provide\n<a href=\"https://developer.arm.com/ip-products/system-ip/coresight-debug-and-trace\" target=\"_blank\"><b>CoreSight Debug and Trace</b></a>.\nCMSIS-DAP supports target devices that contain one or more Cortex processors. A device provides a Debug Access Port (DAP)\ntypically either with a 5-pin JTAG or with a 2-pin Serial Wired Debug (SWD) interface that connects to a debug unit.\nCMSIS-DAP is the interface firmware for a debug unit that connects the debug port to USB. Debuggers that execute on a host\ncomputer connect via USB and the Debug Unit to the device which runs the application software.\n\n\\image html \"CMSIS_DAP_INTERFACE.png\"\n\nBenefits of CMSIS-DAP\n---------------------\n - Provides a standardized interface for debuggers. Interfaces to many standard debuggers is available.\n - Access to CoreSight registers of all Cortex processor architectures (Cortex-A/R/M).\n - Connects via 5-pin JTAG or 2-pin Serial Wire Debug (SWD).\n - Supports multi-core debugging.\n - Supports Serial Wire Output (SWO) of Cortex-M devices.\n - Easy to deploy to debug units based on Cortex-M microcontrollers. \n - Debug unit may be integrated on an evaluation board.\n - Using USB bulk transfers avoids driver installation on host PC.\n - Supports time-critical JTAG or SWD command execution.\n - Supports Test Domain Timer for time measurement using the debug unit.\n - Supports UART communication port, which can be routed to USB COM Port (optional) or native CMSIS-DAP commands (new in\n   CMSIS-DAP Version 2.1.0).\n \nCMSIS-DAP firmware\n==================\nThe CMSIS-DAP firmware is provided as source code and is fully configurable to a new debug unit. A source code template and\nseveral reference implementations for popular debug units are provided. Refer to \\ref DAP_Config_gr for more information.\n\nThe CMSIS-DAP firmware stack is composed of the following components:\n\n  - CMSIS-DAP firmware that interfaces to JTAG or SWD pins using standard I/O pins of the Cortex-M device.\n  - CMSIS-Driver USART that connects:\n    - the UART of the Cortex-M device to the SWO output from the target.\n    - an additional UART of the Cortex-M device to the UART from the target.\n  - USB stack that interfaces to the USB port of the host computer using:\n    - a custom class (for USB bulk endpoints),\n    - the CDC ACM class to export USB COM Port.\n  - The USB Device middleware may require CMSIS-RTOS and a CMSIS-Driver USB.\n  \nIn the examples provided, the MDK-Middleware USB stack has been used. However, it is possible to use alternative USB stacks.\n\n\\note\n\n- CMSIS-DAP v1.x is \\a deprecated and <i>not recommended for new designs</i>.\n- Use \\ref BulkUSB \"CMSIS-DAP v2.x\" instead that provides high-speed SWO trace streaming and does not require driver\n  installation in modern operating systems (Mac OS, Linux, Windows). Refer to \\ref dap_install for more information.\n\nValidation\n----------\nCMSIS-DAP compliant debug units must be validated using the scripts provided in  \\ref DAP_Validate_gr.\n\nThe CMSIS-DAP firmware is provided in the following directory structure.\n\nDirectory                             | Description\n:-------------------------------------|:------------------------------------------------------\n.\\\\CMSIS\\\\DAP\\\\Firmware\\\\Config       | CMSIS-DAP firmware configuration \n.\\\\CMSIS\\\\DAP\\\\Firmware\\\\Examples     | CMSIS-DAP firmware adapted to various debug units\n.\\\\CMSIS\\\\DAP\\\\Firmware\\\\Include      | CMSIS-DAP firmware header file\n.\\\\CMSIS\\\\DAP\\\\Firmware\\\\Source       | CMSIS-DAP firmware source code\n.\\\\CMSIS\\\\DAP\\\\Firmware\\\\Template     | Interface templates for MDK-Middleware\n.\\\\CMSIS\\\\DAP\\\\Firmware\\\\Validation   | Validation project\n\n<hr>\n\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\page dap_install Installing CMSIS-DAP enabled debug adapters\n\nUsing CMSIS-DAP v2 removes the necessity to install separate drivers on Mac OS, Linux, and Windows (8 and above) for the\ndebug adapter.\n\n\\section udevrules Additional requirements for Linux\n\nOn Linux, permission to access USB devices from user space must be explicitly granted via udev rules. Exemplary udev rules\nare available in the <a href=\"https://github.com/pyocd/pyOCD/tree/main/udev\" target=\"_blank\">pyOCD GitHub repo</a> that\nallow to access common debug probes without requiring it to be run as root.\n\n\\section win7 Additional requirements for Windows 7\n\nFor Windows 7, the CMSIS-DAP v2 device will install automatically if the PC is connected to the Internet and device\ninstallation settings are set to automatically download and install drivers for devices. The installed device will be seen\nin the Device Manager under Universal Serial Bus devices as a WinUSB Device.\n\nIf no Internet connection is available or you want the device to show with a different name in the Device Manager, you\nshould provide an .inf file. Refer to \\ref wininf \"USB Driver and *.inf file\" for more information.\n\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\page dap_revisionHistory Revision History of CMSIS-DAP\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>V2.1.2</td>\n      <td>\n         Fix \\ref DAP_Transfer handling when transfer fails\n      </td>\n    </tr>\n    <tr>\n      <td>V2.1.1</td>\n      <td>\n         Allow default clock frequency to use fast clock mode\n      </td>\n    </tr>\n    <tr>\n      <td>V2.1.0</td>\n      <td>\n         Added: \\ref DAP_uart_gr to support target communication via extra UART\\n\n         Added: UART Receive/Transmit Buffer Size values in the command \\ref DAP_Info \\n\n         Added: Target Board Vendor and Target Board Name strings in the command \\ref DAP_Info \\n\n         Added: Product Firmware Version string in the command \\ref DAP_Info \\n\n         Changed: String encoding in \\ref DAP_Info from ASCII to UTF-8\n      </td>\n    </tr>\n    <tr>\n      <td>V2.0.0</td>\n      <td>\n         Changed: Communication via USB bulk endpoints to achieve high-speed transfer rates\\n\n         Added: Streaming SWO via separate \\ref BulkUSB \"USB bulk endpoint\"\\n\n         Added: \\ref DAP_SWO_Transport extended with transport mode 2 - Send trace data via separate \\ref BulkUSB \"USB bulk endpoint\" \n      </td>\n    </tr>\n    <tr>\n      <td>V1.3.0</td>\n      <td>\n         Added: Target Board Vendor and Target Board Name strings in the command \\ref DAP_Info \\n\n         Added: Product Firmware Version string in the command \\ref DAP_Info \\n\n         Changed: String encoding in \\ref DAP_Info from ASCII to UTF-8\n      </td>\n    </tr>\n    <tr>\n      <td>V1.2.0</td>\n      <td>\n         Added: \\ref DAP_SWD_Sequence to enable SWD multi-drop target selection \\n\n         Added: Test Domain Timer values in the commands \\ref DAP_Info, \\ref DAP_Transfer\n      </td>\n    </tr>\n    <tr>\n      <td>V1.1.0</td>\n      <td>\n         Added: \\ref DAP_swo_gr to support Serial Wire Output (SWO) in UART mode\\n\n         Added: \\ref DAP_atomic_gr support for executing time critical DAP commands\n      </td>\n    </tr>\n    <tr>\n      <td>V1.0.0</td>\n      <td>Version 1.0.0 was never released; version number skipped.</td>\n    </tr>\n    <tr>\n      <td>V0.02</td>\n      <td>Renamed \\b DAP_LED to \\ref DAP_HostStatus.</td>\n    </tr>\n    <tr>\n      <td>V0.01</td>\n      <td>Beta Release.</td>\n    </tr>\n</table>\n*/\n"
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/DAP/src/dap_USB_cmds.txt",
    "content": "/**************************************************************************************************/\n/**\n\\defgroup DAP_Commands_gr CMSIS-DAP Commands\n\nCommands between Debug Unit and host computer.\n\nThis section explains each command that is exchanged between the Debug Unit and the host computer.\nEvery Command starts with a Command-ID and optional data.\nDepending on the Command, the CMSIS-DAP firmware replies with a Response that repeats the Command-ID and\ndelivers additional data.\n\nCommand and Response data have a package size limitation that is defined with \\ref DAP_PACKET_SIZE.\nThis configuration setting can be obtained with the command \\ref DAP_Info and is used to\noptimize the performance for Full-Speed or High-Speed USB. The debugger must ensure that each\ndata package fits within the limitations of the configured \\ref DAP_PACKET_SIZE.\n\n\\note\nCommands that are not implemented reply with 0xFF instead of repeating the command byte.\n\nConventions and Command Structure\n---------------------------------\n\nThe following conventions describe the command semantic used in the following documentation:\n\n Symbol   | Description\n--------- | ------------------------------------------------------------------------------------\n \\>       | Prefix indicating the direction: Command from host to Debug Unit.\n \\<       | Prefix indicating the direction: Response from Debug Unit to host.\n BYTE     | 8-bit value.\n SHORT    | 16-bit value (low byte first).\n WORD     | 32-bit value (low byte first).\n LWORD    | 64-bit value (low byte first).\n FLOAT    | 32-bit single precision floating point value (LSB first).\n 0x01     | Fixed HEX value in C notation. Used for example to identify a command.\n Reserved | The field above is reserved for future extension.\n \\*\\*\\*\\* | The field above has exactly one occurrence.\n \\+\\+\\+\\+ | The field above has a variable length.\n //////// | The field above is repeated and may appear 0..n times.\n\n\nThe commands are described in a structure consisting of three lines.\n  - The first line indicates the field type.\n  - The second line indicates the communication direction and the command structure.\n  - The third line indicates the occurrence of the field.\n\n\\b Examples:\n\\code\n | BYTE | SHORT *| WORD ***|\n > 0x99 | RecLen | Data    |\n |******|********|+++++++++|\n\\endcode\n\nThe Command with the Command-ID <em>0x99</em> is sent from the host computer to the Debug Unit.\nThe value of <em>RecLen</em> indicates the number of WORDS that follow with <em>Data</em>.\n<em>Data</em> is repeated several times depending on the value of <em>RecLen</em>.\n\nDepending on the Command the Debug Unit may send a <b>Response</b>.\n\\code\n | BYTE ***| WORD***********|\n < 0       | Register Value |\n |*Reserved|****************|\n\\endcode\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_genCommands_gr General Commands\n\\ingroup DAP_Commands_gr\nInformation and Control commands for the CMSIS-DAP Debug Unit.\n\nThe General Commands allow to:\n - Connect, disconnect, and identify the Debug Unit.\n - Control the Status LEDs of the Debug Unit.\n - Issue and hardware reset to the connected Device.\n - Terminate previous CMSIS-DAP Commands.\n - Wait for a specified time.\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_swj_gr Common SWD/JTAG Commands\n\\ingroup DAP_Commands_gr\n\\brief Set SWD/JTAG clock and control/monitor SWD/JTAG I/O pins.\n\nThe Common SWD/JTAG Commands allow to:\n - Read and Write the SWD/JTAG I/O pins including nRESET.\n - Configure the SWD/JTAG clock speed.\n - Generate a sequence on the SWD/JTAG I/O pins for SWD<->JTAG mode switch.\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_swd_gr SWD Commands\n\\ingroup DAP_Commands_gr\n\\brief Configure the parameters for SWD mode.\n\nThe SWD Commands allow you to configure the parameters for the Serial Wire Debug (SWD) communication mode.\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_swo_gr SWO Commands\n\\ingroup DAP_Commands_gr\n\\brief Configure the parameters for SWO mode.\n\nCMSIS-DAP SWO (Serial Wire Output)\n----------------------------------\n\nCMSIS-DAP (CoreSight Debug Access Port) specifies debug protocol and interface for devices with CoreSight Debug and Trace.\n\n\\note\nThe \\ref DAP_swo_gr are only available when \\ref DAP_Info with ID=0xF0 (Capabilities) returns in \\b Info - Bit 2: <b>1 = SWO UART</b> or Bit 3: <b>1 = SWO Manchester</b>.\n\nThe following extension adds support for trace over SWO (Serial Wire Output).\n\nSWO add-on is a compatible extension of the existing CMSIS-DAP specification.\nExisting debugger implementations on PC do not require any modifications for debugging. They only need to be extended in order to support trace.\n\nThe following new commands are added:\n - \\ref DAP_SWO_Transport\n - \\ref DAP_SWO_Mode\n - \\ref DAP_SWO_Baudrate\n - \\ref DAP_SWO_Control\n - \\ref DAP_SWO_Status\n - \\ref DAP_SWO_ExtendedStatus\n - \\ref DAP_SWO_Data\n\nFormat of the new commands is specified below using CMSIS-DAP documentation style.\nNote: 16-bit values (SHORT) and 32-bit values (WORD) are encoded as little-endian.\n\nThe following existing commands are extended:\n - \\ref DAP_Info\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_jtag_gr JTAG Commands\n\\ingroup DAP_Commands_gr\n\\brief Detect and configure the JTAG device chain.\n\nThe JTAG Commands allow to:\n - Detect the devices connect to the JTAG chain.\n - Configure the IR register length of each device on the JTAG chain.\n - Read the JTAG IDCODE value of each device on the JTAG chain.\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_transfer_gr Transfer Commands\n\\ingroup DAP_Commands_gr\n\\brief Read and Writes to CoreSight registers.\n\nThe Transfer Commands allow to:\n - Configure the parameters for information exchange with CoreSight registers.\n - Transfer (read or write) a single data word or a data block with CoreSight registers.\n - Terminate an active data transfer.\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_atomic_gr Atomic Commands\n\\ingroup DAP_Commands_gr\n\\brief Execute atomic commands.\n\nCMSIS-DAP command set is extended with two top level commands that allow the execution of multiple DAP commands further USB communication.\nExecuting multiple CMSIS-DAP commands is typically a requirement at the reset time of some devices. The sequence after reset can be time\ncritical and any USB communication would violate the available time window.\n - \\ref DAP_ExecuteCommands_gr : execute multiple DAP commands from a single command request\n - \\ref DAP_QueueCommands_gr : queue of multiple DAP commands before execution\n\nThese two DAP commands are used to collect several other DAP commands before execution.\nPacket Size and Packet Count limitation (as reported via \\ref DAP_Info) must be respected by the debugger.\n\n\\note\nThe \\ref DAP_atomic_gr are only available when \\ref DAP_Info with ID=0xF0 (Capabilities) returns in \\b Info - Bit 4: <b>1 = Atomic Commands</b>.\n\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_uart_gr UART COM Commands\n\\ingroup DAP_Commands_gr\n\\brief Target communication via extra UART.\n\nCMSIS-DAP debug unit can be extended to support a separate UART port that connects to the target. Such a UART communication\nis typically used for printf-style debugging, but the usage is not limited to that.  CMSIS-DAP supports UART communication via:\n  - dedicated CMSIS-DAP commands: connects seamlessly to (Cloud) IDEs that integrate a printf viewer.\n  - via standard USB COM port (optional): for any data communication, i.e. to transmit training data sets for machine learning.\n\nThe following CMSIS-DAP commands are added to support UART communication:\n - \\ref DAP_UART_Transport : \\copybrief DAP_UART_Transport\n - \\ref DAP_UART_Configure : \\copybrief DAP_UART_Configure\n - \\ref DAP_UART_Control : \\copybrief DAP_UART_Control\n - \\ref DAP_UART_Status : \\copybrief DAP_UART_Status\n - \\ref DAP_UART_Transfer : \\copybrief DAP_UART_Transfer\n\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_Response_Status Response Status\n\\ingroup DAP_Commands_gr\n\\brief Status Information in Response Data\n\\details\n\nThe Response data of a command frequently include a Status that indicates correct execution or\ncommand failures.  Currently the following Status codes are returned:\n- 0x00 = DAP_OK: Command has been successfully executed\n- 0xFF = DAP_ERROR: Command did not execute due to communication failure with the device.\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_Info DAP_Info\n\\ingroup DAP_genCommands_gr\n\\brief Get Information about CMSIS-DAP Debug Unit.\n\\details\nThe <b>DAP_Info Command</b> provides configuration information about the Debug Unit itself and the capabilities.\n\n<b>DAP_Info Command:</b>\n\\code\n| BYTE | BYTE |\n> 0x00 | ID   |\n|******|******|\n\\endcode\n\n- \\b ID: Request Identifier to obtain information in the Response:\n  - \\b 0x01 = Get the <b>Vendor Name</b> (string).\n  - \\b 0x02 = Get the <b>Product Name</b> (string).\n  - \\b 0x03 = Get the <b>Serial Number</b> (string).\n  - \\b 0x04 = Get the <b>CMSIS-DAP Protocol Version</b> (string).\n  - \\b 0x05 = Get the <b>Target Device Vendor</b> (string).\n  - \\b 0x06 = Get the <b>Target Device Name</b> (string).\n  - \\b 0x07 = Get the <b>Target Board Vendor</b> (string).\n  - \\b 0x08 = Get the <b>Target Board Name</b> (string).\n  - \\b 0x09 = Get the <b>Product Firmware Version</b> (string, vendor-specific format).\n  - \\b 0xF0 = Get information about the <b>Capabilities</b> (BYTE) of the Debug Unit (see below for details).\n  - \\b 0xF1 = Get the <b>Test Domain Timer</b> parameter information (see below for details).\n  - \\b 0xFB = Get the <b>UART Receive Buffer Size</b> (WORD).\n  - \\b 0xFC = Get the <b>UART Transmit Buffer Size</b> (WORD).\n  - \\b 0xFD = Get the <b>SWO Trace Buffer Size</b> (WORD).\n  - \\b 0xFE = Get the maximum <b>Packet Count</b> (BYTE).\n  - \\b 0xFF = Get the maximum <b>Packet Size</b> (SHORT).\n\n<b>DAP_Info Response:</b>\n\\code\n| BYTE | BYTE | BYTE |\n< 0x00 | Len  | Info |\n|******|******|++++++|\n\\endcode\n\n- \\b Len:  Info length in bytes.\n- \\b Info:\n  - a \\b string encoded as UTF-8. Len is the string length including the \\\\x00 terminator. Len = 0 indicates no information, and is distinct from an empty string indicated by Len = 1.\n  - a \\b BYTE value (indicated with Len = 1).\n  - a \\b SHORT value (indicated with Len = 2).\n  - a \\b WORD value (indicated with Len = 4).\n\n\\note\nAn unrecognized ID returns no value (indicated by Len = 0).\n\n\\note\nThe ID for <b>Vendor Name</b>, <b>Product Name</b>, and <b>Serial Number</b> may return no string (indicated by Len = 0).\nIn this case the USB Device Information is used to obtain Vendor Name, Product Name, and Serial Number.\n\n\\note\nThe value of <b>CMSIS-DAP Protocol Version</b> must be one of the versions from the \\ref dap_revisionHistory \"CMSIS-DAP revision history\", such as \"2.1.0\".\n\n\\note\n<b>Target Device Vendor</b>, <b>Target Device Name</b>, <b>Target Board Vendor</b> and <b>Target Board Name</b>\nare only available on On-Board Debug Units with known Target. Refer to \\ref TARGET_FIXED for more information.\nStrings should match the listed attribute values from the corresponding CMSIS Board Support Pack.\nIf the Target is not known no string is returned (indicated by Len = 0).\n\n\\note\n<b>Target Device Vendor</b> should match the <a href=\"../../Pack/html/pdsc_boards_pg.html#element_board_mountedDevice\">Dvendor</a>\nattribute value (excluding the colon and vendor code suffix when present) of the <tt>mountedDevice</tt>.\n\n\\note\n<b>Target Device Name</b> should match the <a href=\"../../Pack/html/pdsc_boards_pg.html#element_board_mountedDevice\">Dname</a>\nattribute value of the <tt>mountedDevice</tt>.\n\n\\note\n<b>Target Board Vendor</b> should match the <a href=\"../../Pack/html/pdsc_boards_pg.html#element_board\">vendor</a>\nattribute value (excluding the colon and vendor code suffix when present).\n\n\\note\n<b>Target Board Name</b> should match the <a href=\"../../Pack/html/pdsc_boards_pg.html#element_board\">name</a>\nattribute value.\n\n\\note\n<b>Product Firmware Version</b> may return no string (indicated by Len = 0).\n\n<hr>\n\n<b>DAP_Info Response (for ID=0xF0):</b>\n\nThe ID=0xF0 <b>Capabilities</b> obtains information about the available interface to the Device.\nThe reply consists of one or two \\b Info bytes with bits that indicate the features of the <b>Debug Unit</b>.\nThe features indicate the command scope of the CMSIS-DAP firmware. If certain features are not available, the debugger should not call the related commands as the may not be implemented. Commands that are not implemented reply with 0xFF instead of repeating the command byte.\n\n\n\\code\n| BYTE | BYTE | BYTE *| BYTE  |\n< 0x00 | Len  | Info0 | Info1 |\n|******|******|*******|*******|\n\\endcode\n\n- \\b Len:  <b>1 = Info0</b> present, <b>2 = Info0, Info1</b> present.\n\nAvailable transfer protocols to target:\n - Info0 - Bit 0: <b>1 = SWD</b> Serial Wire Debug communication is implemented (0 = \\ref DAP_swd_gr not implemented).\n - Info0 - Bit 1: <b>1 = JTAG</b> communication is implemented (0 = \\ref DAP_jtag_gr not implemented).\n\nSerial Wire Trace (SWO) support:\n - Info0 - Bit 2: <b>1 = SWO UART</b> - UART Serial Wire Output is implemented (0 = not implemented).\n - Info0 - Bit 3: <b>1 = SWO Manchester</b> - Manchester Serial Wire Output is implemented (0 = not implemented).\n\nCommand extensions for transfer protocol:\n - Info0 - Bit 4: <b>1 = Atomic Commands</b> - \\ref DAP_atomic_gr support is implemented (0 = \\ref DAP_atomic_gr not implemented).\n\nTime synchronisation via Test Domain Timer:\n - Info0 - Bit 5: <b>1 = Test Domain Timer</b> - debug unit support for Test Domain Timer is implemented (0 = not implemented).\n\nSWO Streaming Trace support:\n - Info0 - Bit 6: <b>1 = SWO Streaming Trace</b> is implemented (0 = not implemented).\n\nUART Communication Port support:\n - Info0 - Bit 7: <b>1 = UART Communication Port</b> is implemented (0 = not implemented).\n\nUART Communication via USB COM Port support:\n - Info1 - Bit 0: <b>1 = USB COM Port</b> is implemented (0 = not implemented).\n\n<hr>\n\n<b>DAP_Info Response (for ID=0xF1):</b>\n\nThe ID=0xF1 <b>Test Domain Timer</b> obtains the parameter information about an optional 32-bit Test Domain Timer that may be used for various time measurements.\n\n\\code\n| BYTE | BYTE | WORD *****|\n< 0x00 | 0x08 | Frequency |\n|******|******|***********|\n\\endcode\n\n- \\b Frequency:  Input frequency of the Test Domain Timer which indicates the resolution of the 32-bit TD_TimeStamp values.\n\n\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_HostStatus DAP_HostStatus\n\\ingroup DAP_genCommands_gr\nSent status information of the debugger to Debug Unit.\n\nThe <b>DAP_HostStatus Command</b> is used to sent the status information about the debugger to the Debug Unit.\nThis status information may be displayed on the Debug Unit. Therefore a Debug Unit may provide optional Status LEDs:\n - Connect LED: is active when the DAP hardware is connected to a debugger.\n - Running LED: is active when the debugger has put the target device into running state.\n\n<b>DAP_HostStatus Command:</b>\n\\code\n| BYTE | BYTE **| BYTE **|\n> 0x01 | Type   | Status |\n|******|********|********|\n\\endcode\n- \\b Type: specifies the type of the information that is sent in \\b Status:\n  - \\b 0 = Connect: Status indicates that the debugger is connected to the Debug Unit.\n  - \\b 1 = Running: Status indicates that the target hardware is executing application code.\n- \\b Status: contains the actual status information:\n  - \\b 0 = False: may be used to turn off a status LED (Connect or Running) on the Debug Unit.\n  - \\b 1 = True: may be used to turn on a status LED (Connect or Running) on the Debug Unit.\n\n<b>DAP_HostStatus Response:</b>\n\\code\n| BYTE | BYTE **|\n< 0x01 | 0x00   |\n|******|********|\n\\endcode\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_Connect DAP_Connect\n\\ingroup DAP_genCommands_gr\n\\brief Connect to Device and selected DAP mode.\n\\details\nThe <b>DAP_Connect Command</b> initializes the DAP I/O pins for the specified DAP mode (JTAG or\nSWD). This command calls the function \\ref PORT_SWD_SETUP or \\ref PORT_JTAG_SETUP which prepares the\nconnection to the Target Device.\n\n<b>DAP_Connect Command:</b>\n\\code\n| BYTE | BYTE |\n> 0x02 | Port |\n|******|******|\n\\endcode\n\n- \\b Port: Selects the DAP port mode and configures the DAP I/O pins. The possible values are:\n  - 0 = Default mode: configuration of the DAP port mode is derived from \\ref DAP_DEFAULT_PORT (zero configuration).\n  - 1 = SWD mode: connect with Serial Wire Debug mode.\n  - 2 = JTAG mode: connect with 4/5-pin JTAG mode.\n\n\n<b>DAP_Connect Response:</b>\n\\code\n| BYTE | BYTE |\n< 0x02 | Port |\n|******|******|\n\\endcode\n\n- \\b Port: DAP port mode initialized. The possible values are:\n  - 0 = initialization failed; no mode pre-configured.\n  - 1 = initialization for SWD mode.\n  - 2 = initialization for JTAG mode.\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_Disconnect DAP_Disconnect\n\\ingroup DAP_genCommands_gr\n\\brief Disconnect from active Debug Port\n\\details\nThe <b>DAP_Disconnect Command</b> de-initializes the DAP I/O pins by calling the function \\ref PORT_OFF.\n\n<b>DAP_Disconnect Command</b>:\n\\code\n| BYTE |\n> 0x03 |\n|******|\n\\endcode\n\n<b>DAP_Disconnect Response</b>:\n\\code\n| BYTE | BYTE   |\n< 0x03 | Status |\n|******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_WriteABORT DAP_WriteABORT\n\\ingroup DAP_genCommands_gr\n\\brief Write ABORT Register\n\\details\nThe <b>DAP_WriteABORT Command</b> writes an abort request to the CoreSight ABORT register of\nthe Target Device.\n\n<b>DAP_WriteABORT Command</b>:\n\\code\n| BYTE | BYTE *****| WORD *|\n> 0x08 | DAP Index | Abort |\n|******|***********|*******|\n\\endcode\n\n- <b>DAP Index</b>: Zero based device index of the selected JTAG device. For SWD mode the value is ignored.\n- <b>Abort</b>:  32-bit value to write into the CoreSight ABORT register.\n\n<b>DAP_WriteABORT Response</b>:\n\\code\n| BYTE | BYTE **|\n< 0x08 | Status |\n|******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_Delay DAP_Delay\n\\ingroup  DAP_genCommands_gr\n\\brief    Wait for specified delay\n\\details\nThe <b>DAP_Delay< Command</b> waits for a time period specified in micro-seconds.\n\n<b>DAP_Delay Command</b>:\n\\code\n| BYTE | SHORT |\n> 0x09 | Delay |\n|******|*******|\n\\endcode\n\n- \\b Delay: wait time in µs.\n\n<b>DAP_Delay Response</b>:\n\\code\n| BYTE | BYTE   |\n< 0x09 | Status |\n|******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_ResetTarget DAP_ResetTarget\n\\ingroup  DAP_genCommands_gr\n\\brief    Reset Target with Device specific sequence.\n\\details\nThe <b>DAP_ResetTarget Command</b> requests a target reset with a device specific command sequence.\nThis command calls the user configurable function \\ref RESET_TARGET.\n\n<b>DAP_ResetTarget Command</b>:\n\\code\n| BYTE |\n> 0x0A |\n|******|\n\\endcode\n\n<b>DAP_ResetTarget Response</b>:\n\\code\n| BYTE | BYTE   | BYTE    |\n< 0x0A | Status | Execute |\n|******|********|*********|\n\\endcode\n\n- \\b Execute: indicates whether a device specific reset sequence was executed.\n  - no device specific reset sequence is implemented.\n  - 1 = a device specific reset sequence is implemented.\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWJ_Pins DAP_SWJ_Pins\n\\ingroup DAP_swj_gr\n\\brief Control and monitor SWD/JTAG Pins\n\\details\n\nThe <b>DAP_SWJ_Pins Command</b> is used to monitor and control the I/O Pins including the nRESET Device reset line.\n\nThe <b>Pin Wait</b> time is useful in systems where the nRESET pin is implemented as open-drain output.\nAfter nRESET is de-asserted by the debugger, external circuit may still hold the target Device\nunder reset for a time. Using the <b>Pin Wait</b> time, the debugger may monitor\nselected I/O Pins and wait until they the expected value appears or a timeout expires.\n\n<b>I/O Pin Mapping</b> for the fields <b>Pin Output</b>, <b>Pin Select</b>, and <b>Pin Input</b>:\n  - Bit 0: SWCLK/TCK\n  - Bit 1: SWDIO/TMS\n  - Bit 2: TDI\n  - Bit 3: TDO\n  - Bit 5: nTRST\n  - Bit 7: nRESET\n\n\n<b>DAP_SWJ_Pins Command</b>:\n\\code\n| BYTE | BYTE ******| BYTE ******| Word ****|\n> 0x10 | Pin Output | Pin Select | Pin Wait |\n|******|************|************|**********|\n\\endcode\n\n- <b>Pin Output</b>: Value for selected output pins\n- <b>Pin Select</b>: Selects which output pins will be modified\n- <b>Pin Wait</b>: Wait timeout for the selected output to stabilize\n  - 0 = no wait\n  - 1 .. 3000000 = time in µs (max 3s)\n\n<b>DAP_SWJ_Pins Response:</b>\n\\code\n| BYTE | BYTE *****|\n< 0x10 | Pin Input |\n|******|***********|\n\\endcode\n- <b>Pin Input</b>: Pin state read from target Device.\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWJ_Clock DAP_SWJ_Clock\n\\ingroup DAP_swj_gr\n\\brief Select SWD/JTAG Clock\n\\details\nThe <b>DAP_SWJ_Clock Command</b> sets the clock frequency for JTAG and SWD communication mode.\n\n<b>DAP_SWJ_Clock Command</b>:\n\\code\n| BYTE | WORD *|\n> 0x11 | Clock |\n|******|*******|\n\\endcode\n\n- \\b Clock: Selects maximum SWD/JTAG Clock (SWCLK/TCK) value in Hz\n\n<b>DAP_SWJ_Clock Response</b>:\n\\code\n| BYTE | BYTE **|\n< 0x11 | Status |\n|******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWJ_Sequence DAP_SWJ_Sequence\n\\ingroup DAP_swj_gr\n\\brief Generate SWJ sequence SWDIO/TMS \\@SWCLK/TCK\n\\details\n\nThe <b>DAP_SWJ_Sequence Command</b> can be used to generate required SWJ sequences for\nSWD/JTAG Reset, SWD<->JTAG switch and Dormant operation.\n\n<b>DAP_SWJ_Sequence Command</b>\n\\code\n| BYTE | BYTE **************| BYTE *************|\n> 0x12 | Sequence Bit Count | Sequence Bit Data |\n|******|********************|+++++++++++++++++++|\n\\endcode\n\n- <b>Sequence Bit Count</b>: Number of bits in sequence: 1..256 (256 encoded as 0)\n- <b>Sequence Bit Data</b>:  Sequence generated on SWDIO/TMS (with clock \\@SWCLK/TCK) LSB is transmitted  first\n\n\n<b>DAP_SWJ_Sequence Response</b>:\n\\code\n| BYTE | BYTE **|\n< 0x12 | Status |\n|******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWD_Configure DAP_SWD_Configure\n\\ingroup DAP_swd_gr\n\\brief Configure SWD Protocol\n\\details\nThe <b>DAP_SWD_Configure Command</b> sets the SWD protocol configuration. For more information about\nthe SWD protocol refer to the <b>Arm Debug Interface v5 - Interface Specification.</b>\n\n<b>DAP_SWD_Configure Command</b>:\n\\code\n| BYTE | BYTE *********|\n> 0x13 | Configuration |\n|******|***************|\n\\endcode\n\n- \\b Configuration: Contains information about SWD specific features \\n\n  - Bit 1 .. 0: Turnaround clock period of the SWD device (should be identical with the WCR [Write Control Register] value of the target):\n    0 = 1 clock cycle (default), 1 = 2 clock cycles, 2 = 3  clock cycles, 3 = 4 clock cycles.\n\n  - Bit 2: DataPhase: 0 = Do not generate Data Phase on WAIT/FAULT (default), 1 = Always generate Data Phase (also on WAIT/FAULT; Required for Sticky Overrun behavior).\n\n<b>DAP_SWD_Configure Response</b>:\n\\code\n| BYTE | BYTE **|\n< 0x13 | Status |\n|******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWD_Sequence DAP_SWD_Sequence\n\\ingroup DAP_swd_gr\n\\brief Generate SWD sequence and output on SWDIO or capture input from SWDIO data.\n\\details\n\\note\nThe \\ref DAP_SWD_Sequence is available for CMSIS-DAP version 1.2 and higher.  Refer to \\ref DAP_Info for more information on how to query the CMSIS-DAP version.\n\n\nThe <b>DAP_SWD_Sequence Command</b> is used to generate special sequences in SWD mode on the pins SWCLK and SWDIO.\nFor example, for SWD multi-drop target selection (see picture) it is required to put the SWDIO pin to input mode (where it is not driven).\n\n\\image html \"SWD_Sequence.png\" \"SWD sequence for multi-drop target selection\"\n\n - For mode=0 (output: SWDIO is driven), the data for the SWDIO pin are part of the <b>DAP_SWD_Sequence Command</b>.\n - For mode=1 (input: SWDIO is not driven), the data from the SWDIO pin are captured and returned as part of the <b>DAP_SWD_Sequence Response</b>.\n\n<b>DAP_SWD_Sequence Command</b>:\n\\code\n| BYTE | BYTE **********| BYTE *********| BYTE ******|\n> 0x1D | Sequence Count | Sequence Info | SWDIO Data |\n|******|****************|///////////////|++++++++++++|\n\\endcode\n\n- <b>Sequence Count</b>: Number of Sequences\n- <b>Sequence Info</b>: Contains number of SWCLK cycles and SWDIO mode\n  - Bit 5 .. 0: Number of TCK cycles: 1 .. 64 (64 encoded as 0)\n  - Bit 6: reserved\n  - Bit 7: mode: 0=output (SWDIO Data in command), 1=input (SWDIO Data in response)\n- <b>SWDIO Data</b> (only for output mode):  Data generated on SWDIO\n  - One bit for each TCK cycle\n  - LSB transmitted first, padded to BYTE boundary\n\n<b>DAP_SWD_Sequence Response</b>:\n\\code\n| BYTE | BYTE **| BYTE ******|\n< 0x1D | Status | SWDIO Data |\n|******|********|++++++++++++|\n\\endcode\n\n- <b>SWDIO Data</b> (only for input mode):  Data captured from SWDIO\n  - One bit for each SWCLK cycle for input mode\n  - LSB received first, padded to BYTE boundary\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWO_Transport DAP_SWO_Transport\n\\ingroup DAP_swo_gr\n\\brief Set SWO transport mode\n\\details\n\nDAP_SWO_Transport (0x17):\n-------------------------\n\nSets the SWO transport mode for reading trace data.\n\n<b>DAP_SWO_Transport Request:</b>\n\\code\n | BYTE | BYTE      |\n > 0x17 | Transport |\n |******|***********|\n\\endcode\n\n  - \\b Transport:\n    - 0 - None (default)\n    - 1 - Read trace data via DAP_SWO_Data command\n    - 2 - Send trace data via separate \\ref BulkUSB \"USB bulk endpoint\" (requires CMSIS-DAP v2 configuration)\n    - ... - reserved\n\n<b>DAP_SWO_Transport Response:</b>\n\\code\n | BYTE | BYTE   |\n < 0x17 | Status |\n |******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n\n\\note Currently the trace data can only be read via the existing DAP command request/response channel by using DAP_SWO_Data.\n        Future extension might provide separate channels for reading trace data.\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWO_Mode DAP_SWO_Mode\n\\ingroup DAP_swo_gr\n\\brief Set SWO capture mode\n\\details\n\nDAP_SWO_Mode (0x18):\n--------------------\n\nSets the SWO trace capture mode.\n\n<b>DAP_SWO_Mode Request:</b>\n\\code\n | BYTE | BYTE |\n > 0x18 | Mode |\n |******|******|\n\\endcode\n\n- \\b Mode:\n  - 0 - Off (default)\n  - 1 - UART\n  - 2 - Manchester\n\n<b>DAP_SWO_Mode Response:</b>\n\\code\n | BYTE | BYTE   |\n < 0x18 | Status |\n |******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWO_Baudrate DAP_SWO_Baudrate\n\\ingroup DAP_swo_gr\n\\brief Set SWO baudrate\n\\details\n\nDAP_SWO_Baudrate (0x19):\n------------------------\n\nSets the baudrate for capturing SWO trace data. Can be called iteratively to determine supported baudrates.\n\n<b>DAP_SWO_Baudrate Request:</b>\n\\code\n | BYTE | WORD     |\n > 0x19 | Baudrate |\n |******|**********|\n\\endcode\n  - \\b Baudrate: Requested baudrate\n\n<b>DAP_SWO_Baudrate Response:</b>\n\\code\n | BYTE | WORD     |\n < 0x19 | Baudrate |\n |******|**********|\n\\endcode\n\n  - \\b Baudrate: Actual baudrate or 0 (baudrate not configured).\n    When requested baudrate is not achievable the closest configured baudrate can be returned or 0\n    which indicates that baudrate was not configured.\n\n\\note   When Manchester Mode is used and if decoder is implemented with clock recovery then baudrate\n        is not required since clock is automatically decoded. However such decoders are harder to implement\n        (especially for high frequencies) and the clock recovery might not be implemented.\n        Therefore the baudrate should be provided also for Manchester mode.\n\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWO_Control DAP_SWO_Control\n\\ingroup DAP_swo_gr\n\\brief Control SWO trace data capture\n\\details\n\nDAP_SWO_Control (0x1A):\n--------------------\n\nControls the SWO trace data capture.\n\n<b>DAP_SWO_Control Request:</b>\n\\code\n | BYTE | BYTE    |\n > 0x1A | Control |\n |******|*********|\n\\endcode\n  - \\b Control:\n    - 0 - Stop\n    - 1 - Start\n\n<b>DAP_SWO_Control Response:</b>\n\\code\n | BYTE | BYTE   |\n < 0x1A | Status |\n |******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n\n\\note Starting capture automatically flushes any existing trace data in buffers which has not yet been read\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWO_Status DAP_SWO_Status\n\\ingroup DAP_swo_gr\n\\brief Read SWO trace status\n\\details\n\nDAP_SWO_Status (0x1B):\n--------------------\n\nReads the SWO trace status.\n\n<b>DAP_SWO_Status Request:</b>\n\\code\n | BYTE |\n > 0x1B |\n |******|\n\\endcode\n\n<b>DAP_SWO_Status Response:</b>\n\\code\n | BYTE | BYTE         | WORD        |\n < 0x1B | Trace Status | Trace Count |\n |******|**************|*************|\n\\endcode\n\n  - <b>Trace Status</b>:\n    - Bit 0: Trace Capture (1 - active, 0 - inactive)\n    - Bit 6: Trace Stream Error\n    - Bit 7: Trace Buffer Overrun\n  - <b>Trace Count</b>: Number of bytes in Trace Buffer (not yet read)\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWO_ExtendedStatus DAP_SWO_ExtendedStatus\n\\ingroup DAP_swo_gr\n\\brief Read SWO trace extended status\n\\details\n\nDAP_SWO_ExtendedStatus (0x1E):\n-----------------------------\n\nReads extended information about the SWO trace status.\n\n<b>DAP_SWO_ExtendedStatus Request:</b>\n\\code\n | BYTE | BYTE    |\n > 0x1E | Control |\n |******|*********|\n\\endcode\n\n  - <b>Control</b>:\n    - Bit 0: Trace Status (1 - request, 0 - inactive)\n    - Bit 1: Trace Count (1 - request, 0 - inactive)\n    - Bit 2: Index/Timestamp (1 - request, 0 - inactive)\n\n<b>DAP_SWO_ExtendStatus Response:</b>\n\\code\n | BYTE | BYTE         | WORD        | WORD  | WORD         |\n < 0x1E | Trace Status | Trace Count | Index | TD_TimeStamp |\n |******|++++++++++++++|+++++++++++++|+++++++|++++++++++++++|\n\\endcode\n\n  - <b>Trace Status</b>:\n    - Bit 0: Trace Capture (1 - active, 0 - inactive)\n    - Bit 6: Trace Stream Error\n    - Bit 7: Trace Buffer Overrun\n\n  - <b>Trace Count</b>: Number of bytes in Trace Buffer (not yet read)\n\n  - <b>Index</b>: Sequence number of next trace information\n  - <b>TD_TimeStamp</b>: Test Domain Timer value for trace sequence.\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_SWO_Data DAP_SWO_Data\n\\ingroup DAP_swo_gr\n\\brief Read SWO trace data\n\\details\n\nDAP_SWO_Data (0x1C):\n--------------------\n\nReads the captured SWO trace data from Trace Buffer.\n\n<b>DAP_SWO_Data Request:</b>\n\\code\n | BYTE | SHORT       |\n > 0x1C | Trace Count |\n |******|*************|\n\\endcode\n  - <b>Trace Count</b>: Maxim number of Trace Data bytes to read\n\n<b>DAP_SWO_Data Response:</b>\n\\code\n | BYTE | BYTE         | SHORT       | BYTE       |\n < 0x1C | Trace Status | Trace Count | Trace Data |\n |******|**************|*************|////////////|\n\\endcode\n\n  - <b>Trace Status</b>:\n    - Bit 0: Trace Capture (1 - active, 0 - inactive)\n    - Bit 6: Trace Stream Error\n    - Bit 7: Trace Buffer Overrun\n  - <b>Trace Count</b>: Number of Trace Data bytes read\n  - <b>Trace Data</b>:  Trace Data bytes read\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_JTAG_Sequence DAP_JTAG_Sequence\n\\ingroup DAP_jtag_gr\n\\brief Generate JTAG sequence TMS, TDI and capture TDO\n\\details\nThe <b>DAP_JTAG_Sequence Command</b> may be used to auto-detect devices on the JTAG chain.\nThe result of this command can be used to calculate on the host computer the number of JTAG\ndevices and the JTAG IR register length. This information is the input for \\ref DAP_JTAG_Configure.\n\n<b>DAP_JTAG_Sequence Command</b>:\n\\code\n| BYTE | BYTE **********| BYTE *********| BYTE ****|\n> 0x14 | Sequence Count | Sequence Info | TDI Data |\n|******|****************|///////////////|//////////|\n\\endcode\n\n- <b>Sequence Count</b>: Number of Sequences\n- <b>Sequence Info</b>: Contains number of TDI bits and fixed TMS value\n  - Bit 5 .. 0: Number of TCK cycles: 1 .. 64 (64 encoded as 0)\n  - Bit 6: TMS value\n  - Bit 7: TDO Capture\n- <b>TDI Data</b>:  Data generated on TDI\n  - One bit for each TCK cycle\n  - LSB transmitted first, padded to BYTE boundary\n\n<b>DAP_JTAG_Sequence Response</b>:\n\\code\n| BYTE | BYTE **| BYTE ****|\n< 0x14 | Status | TDO Data |\n|******|********|++++++++++|\n\\endcode\n\n- <b>TDO Data</b>:  Data captured from TDO\n  - One bit for each TCK cycle when TDO Capture is enabled\n  - LSB received first, padded to BYTE boundary\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_JTAG_Configure DAP_JTAG_Configure\n\\ingroup DAP_jtag_gr\n\\brief Configure JTAG Chain\n\\details\nThe <b>DAP_JTAG_Configure Command</b> sets the JTAG device chain information for communication with \\ref\nDAP_transfer_gr. The JTAG device chain needs to be iterated with \\ref DAP_JTAG_Sequence or manually\nconfigured by the debugger on the host computer.\n\n<b>DAP_JTAG_Configure Command</b>:\n\\code\n| BYTE | BYTE *| BYTE *****|\n> 0x15 | Count | IR Length |\n|******|*******|+++++++++++|\n\\endcode\n\n- \\b Count: Number of devices in chain\n- <b>IR Length</b>: JTAG IR register length (in bits) for each device.\n\n<b>DAP_JTAG_Configure Response</b>:\n\\code\n| BYTE | BYTE **|\n< 0x15 | Status |\n|******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_jtag_idcode DAP_JTAG_IDCODE\n\\ingroup DAP_jtag_gr\n\\brief Read JTAG IDCODE\n\\details\nThe <b>DAP_JTAG_IDCODE Command</b> request the JTAG IDCODE for the selected device on the JTAG chain.\n\n<b>DAP_JTAG_IDCODE Command</b>:\n\\code\n| BYTE | BYTE ******|\n> 0x16 | JTAG Index |\n|******|************|\n\\endcode\n\n- <b>JTAG Index</b>: Zero based JTAG index of selected device.\n\n<b>DAP_JTAG_IDCODE Response</b>:\n\\code\n| BYTE | BYTE **| WORD ***|\n< 0x16 | Status | ID Code |\n|******|********|*********|\n\\endcode\n\n- <b>ID Code</b>: 32-bit JTAG ID Code of the device.\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_TransferConfigure DAP_TransferConfigure\n\\ingroup DAP_transfer_gr\n\\brief Configure Transfers\n\\details\nThe <b>DAP_TransferConfigure Command</b> sets parameters for \\ref DAP_Transfer and \\ref DAP_TransferBlock.\n\n<b>DAP_TransferConfigure Command:</b>\n\\code\n| BYTE | BYTE ******** SHORT *****| SHORT ******|\n> 0x04 | Idle Cycles | WAIT Retry | Match Retry |\n|******|*************|************|*************|\n\\endcode\n\n- <b>Idle Cycles</b>: Number of extra idle cycles after each transfer.\n- <b>WAIT Retry</b>: Number of transfer retries after WAIT response.\n- <b>Match Retry</b>: Number of retries on reads with Value Match in \\ref DAP_Transfer. On value mismatch the\n    Register is read again until its value matches or the <b>Match Retry</b> count exceeds.\\n\n\\code\n  retry = Match_Retry;\n  do {\n    if ((Register_Value & Match_Mask) == Match_Value) break;\n  } while (retry--);\n\\endcode\n\n<b>DAP_TransferConfigure Response</b>:\n\\code\n| BYTE | BYTE **|\n< 0x04 | Status |\n|******|********|\n\\endcode\n\n- \\b Status: \\ref DAP_Response_Status\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_Transfer DAP_Transfer\n\\ingroup DAP_transfer_gr\n\\brief Read/write single and multiple registers.\n\\details\n\nThe <b>DAP_Transfer Command</b> reads or writes data to CoreSight registers.\nEach CoreSight register is accessed with a single 32-bit read or write.\nThe CoreSight registers are addressed with DPBANKSEL/APBANKSEL and address lines A2, A3 (A0 = 0 and A1 = 0).\nThis command executes several read/write operations on the selected DP/AP registers.\nThe Transfer Data in the Response are in the order of the Transfer Request in the Command but might be shorter in case of communication failures.\nThe data transfer is aborted on a communication error:\n  - Protocol Error\n  - Target FAULT response\n  - Target WAIT responses exceed configured value\n  - Value Mismatch (Read Register with Value Match)\n\n<b>DAP_Transfer Command:</b>\n\\code\n| BYTE | BYTE *****| BYTE **********| BYTE *************| WORD *********|\n> 0x05 | DAP Index | Transfer Count | Transfer Request  | Transfer Data |\n|******|***********|****************|+++++++++++++++++++++++++++++++++++|\n\\endcode\n\n- <b>DAP Index</b>: Zero based device index of the selected JTAG device. For SWD mode the value is ignored.\n\n- <b>Transfer Count</b>: Number of transfers: 1 .. 255. For each transfer a Transfer Request BYTE is sent. Depending on the request an additional Transfer Data WORD is sent.\n\n- <b>Transfer Request</b>: Contains information about requested access from host debugger.\n  - Bit 0: APnDP: 0 = Debug Port (DP), 1 = Access Port (AP).\n  - Bit 1: RnW: 0 = Write Register, 1 = Read Register.\n  - Bit 2: A2 Register Address bit 2.\n  - Bit 3: A3 Register Address bit 3.\n  - Bit 4: Value Match (only valid for Read Register): 0 = Normal Read Register, 1 = Read Register with Value Match.\n  - Bit 5: Match Mask (only valid for Write Register): 0 = Normal Write Register, 1 = Write Match Mask (instead of Register).\n  - Bit 7: TD_TimeStamp request: 0 = No time stamp, 1 = Include time stamp value from Test Domain Timer before every Transfer Data word (restrictions see note).\n\n- <b>Transfer Data</b>: register value or match value\n  - for Write Register transfer request: the register value for the CoreSight register.\n  - for Match Mask transfer request: the match mask for the CoreSight register.\n  - for Value Match transfer request: the match value of the CoreSight register.\n  - no data is sent for other operations.\n\n\\note\n<b>Transfer Request</b> - Bit 7 (Time Stamp) cannot be combined with Bit 4 (Value Match) or Bit 5 (Match Mask).\n\n\n\n<b>DAP_Transfer Response:</b>\n\\code\n| BYTE | BYTE **********| BYTE *************| WORD ********| WORD *********|\n< 0x05 | Transfer Count | Transfer Response | TD_TimeStamp | Transfer Data |\n|******|****************|*******************|//////////////|+++++++++++++++|\n\\endcode\n\n- <b>Transfer Count</b>: Number of transfers: 1 .. 255 that are executed.\n\n- <b>Transfer Response</b>: Contains information about last response from target Device.\n  - Bit 2..0: ACK (Acknowledge) value:\n      - 1 = OK (for SWD protocol), OK or FAULT (for JTAG protocol),\n      - 2 = WAIT\n      - 4 = FAULT\n      - 7 = NO_ACK (no response from target)\n  - Bit 3: 1 = Protocol Error (SWD)\n  - Bit 4: 1 = Value Mismatch (Read Register with Value Match)\n\n- <b>TD_TimeStamp</b>: current Test Domain Timer value is added before each Transfer Data word when Transfer Request - bit 7: TD_TimeStamp request is set.\n\n- <b>Transfer Data</b>: register value or match value in the order of the <b>Transfer Request</b>.\n  - for Read Register transfer request: the register value of the CoreSight register.\n  - no data is sent for other operations.\n*/\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_TransferBlock DAP_TransferBlock\n\\ingroup DAP_transfer_gr\n\\brief Read/Write a block of data from/to a single register.\n\\details\n\nThe <b>DAP_TransferBlock Command</b> read or write a data block to the same CoreSight register.\nA data block are multiple 32-bit values which are read or written from/to the same CoreSight register.\nThe CoreSight register is addressed with DPBANKSEL/APBANKSEL and address lines A2, A3 (A0 = 0 and A1 = 0).\nThe command can execute several read/write operations to a single DP/AP register.\n\nThe data transfer is aborted on a communication error:\n  - Protocol Error\n  - Target FAULT response\n  - Target WAIT responses exceed configured value\n\n<b>DAP_TransferBlock Command</b>:\n\\code\n| BYTE | BYTE *****| SHORT**********| BYTE *************| WORD *********|\n> 0x06 | DAP Index | Transfer Count | Transfer Request  | Transfer Data |\n|******|***********|****************|*******************|+++++++++++++++|\n\\endcode\n\n- <b>DAP Index</b>: Zero based device index of the selected JTAG device. For SWD mode the value is ignored.\n\n- <b>Transfer Count</b>: Number of transfers: 1 .. 65535.\n\n- <b>Transfer Request</b>: Contains information about requested access from host\n  - Bit 0: APnDP: 0 = DP (Debug Port), 1 = AP (Access Port)\n  - Bit 1: RnW: 0 = Write Register, 1 = Read Register\n  - Bit 2: A2 := Register Address bit 2\n  - Bit 3: A3 := Register Address bit 3\n\n- <b>Transfer Data</b>: register values\n  - for Write Register transfer request: the register values written to the CoreSight register.\n  - no data is sent for Read Register operations.\n\n<b>DAP_TransferBlock Response</b>:\n\\code\n| BYTE | SHORT *********| BYTE *************| WORD *********|\n< 0x06 | Transfer Count | Transfer Response | Transfer Data |\n|******|****************|*******************|+++++++++++++++|\n\\endcode\n\n- <b>DAP Index</b>: Zero based device index of the selected JTAG device. For SWD mode the value is ignored.\n\n- <b>Transfer Count</b>: Number of transfers (1 .. 65535) that are executed.\n\n- <b>Transfer Response</b>: Contains information about last response from target\n  - Bit 2..0: ACK (Acknowledge) value:\n      - 1 = OK (for SWD protocol), OK or FAULT (for JTAG protocol),\n      - 2 = WAIT\n      - 4 = FAULT\n      - 7 = NO_ACK (no response from target)\n  - Bit 3: Protocol Error (SWD)\n\n- <b>Transfer Data</b>: register values\n  - no data is receive for Write Register operations.\n  - for Read Register transfer request: the register values read from CoreSight register.\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_TransferAbort DAP_TransferAbort\n\\ingroup DAP_transfer_gr\n\\brief Abort current Transfer\n\\details\nThe <b>DAP_TransferAbort Command</b> aborts the current transfer. The command can be executed while \\ref DAP_Transfer or \\ref DAP_TransferBlock command\nis still in progress. The command is ignored if there is no transfer in progress. The command itself has no response, however the\naborted \\ref DAP_Transfer or \\ref DAP_TransferBlock command will respond with information about the actually transferred data.\n\n<b>DAP_TransferAbort Command</b>:\n\\code\n| BYTE |\n> 0x07 |\n|******|\n\\endcode\n*/\n\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_ExecuteCommands_gr DAP_ExecuteCommands\n\\ingroup DAP_atomic_gr\n\\brief Execute multiple DAP commands from a single packet.\n\nExecutes multiple DAP commands that are provided in a single packet. Packet size limitation for requests and responses needs to respected.\n\n<b>DAP_ExecuteCommands Request:</b>\n\\code\n | BYTE | BYTE **|+++++++++++++++++++|\n > 0x7F | NumCmd | Command Requests  |\n |******|********|+++++++++++++++++++|\n\\endcode\n\n  - \\b NumCmd: Number of commands to execute\n  - <b>Commands Requests</b>: Concatenated command requests\n\n<b>DAP_ExecuteCommands Response:</b>\n\\code\n | BYTE | BYTE **|+++++++++++++++++++|\n < 0x7F | NumCmd | Command Responses |\n |******|********|+++++++++++++++++++|\n\\endcode\n\n  - \\b NumCmd: Number of commands executed\n  - <b>Commands Responses</b>: Concatenated command responses\n\n<b>Example</b>:\n\nExecute two \\ref DAP_SWJ_Pins commands with \\ref DAP_Delay in between.\n\n<b>Request:</b>\n\\code\n | BYTE | BYTE | BYTE | BYTE ******| BYTE ******| WORD ****| BYTE | SHORT | BYTE | BYTE ******| BYTE ******| WORD ****|\n > 0x7F | 0x03 | 0x10 | Pin Output | Pin Select | Pin Wait | 0x09 | Delay | 0x10 | Pin Output | Pin Select | Pin Wait |\n |******|******|******|************|************|**********|******|*******|******|************|************|**********|\n        |NumCmd| DAP_SWJ_Pins                              | DAP_Delay    | DAP_SWJ_Pins                              |\n\\endcode\n\n<b>Response:</b>\n\\code\n | BYTE | BYTE | BYTE | BYTE *****| BYTE | BYTE **| BYTE | BYTE *****|\n < 0x7F | 0x03 | 0x10 | Pin Input | 0x09 | Status | 0x10 | Pin Input |\n |******|******|******|***********|******|********|******|***********|\n        |NumCmd| DAP_SWJ_Pins     | DAP_Delay     | DAP_SWJ_Pins     |\n\\endcode\n*/\n\n\n\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_QueueCommands_gr DAP_QueueCommands\n\\ingroup DAP_atomic_gr\n\\brief Queue multiple DAP commands provided in a multiple packets.\n\nQueues multiple DAP commands provided in multiple packets.\nQueuing starts with the first packet that includes \\b DAP_QueueCommands command and continues with all subsequent packets that also include this command.\nQueued commands execute when a packet without \\b DAP_QueueCommands command is received.\nPacket size and count limitation for requests and responses needs to respected.\n\nThe command is similar to \\ref DAP_ExecuteCommands_gr on a packet level but queues multiple packets before processing them.\n\n<b>DAP_QueueCommands Request:</b>\n\\code\n | BYTE | BYTE **|+++++++++++++++++++|\n > 0x7E | NumCmd | Command Requests  |   First queued packet\n |******|********|+++++++++++++++++++|\n  .\n  .\n  .\n | BYTE | BYTE **|+++++++++++++++++++|\n > 0x7E | NumCmd | Command Requests  |   Last queued packet\n |******|********|+++++++++++++++++++|\n\\endcode\n\n - \\b > Command Request (any command except \\b DAP_QueueCommands)  \\n\n        Queued commands are executed before this command\n - \\b NumCmd: Number of commands to queue (single packet)\n - <b>Commands Requests</b>: Concatenated command requests (single packet)\n\n<b>DAP_QueueCommands Response:</b>\n\\code\n | BYTE | BYTE **|+++++++++++++++++++|\n < 0x7F | NumCmd | Command Responses |\n |******|********|+++++++++++++++++++|\n  .\n  .\n  .\n | BYTE | BYTE **|+++++++++++++++++++|\n < 0x7F | NumCmd | Command Responses |\n |******|********|+++++++++++++++++++|\n\\endcode\n\n - \\b < Command Response (first non \\b DAP_QueueCommands command)\n - \\b NumCmd: Number of commands executed (single packet)\n - <b>Commands Responses</b>: Concatenated command responses (single packet)\n\n\\b Example:\n\nQueue \\ref DAP_SWJ_Pins and \\ref DAP_Delay in first packet. \\n\nQueue \\ref DAP_SWJ_Pins in second packet. \\n\nQueue \\ref DAP_Delay in third packet. \\n\nSend \\ref DAP_SWJ_Pins in fourth packet which executes queued commands and command in the last packet.\n\n\\b Request:\n\n\\code\n | BYTE | BYTE | BYTE | BYTE ******| BYTE ******| WORD ****| BYTE | SHORT |\n > 0x7E | 0x02 | 0x10 | Pin Output | Pin Select | Pin Wait | 0x09 | Delay |\n |******|******|******|************|************|**********|******|*******|\n   Queue|NumCmd| DAP_SWJ_Pins                              | DAP_Delay    |\n\n | BYTE | BYTE | BYTE | BYTE ******| BYTE ******| WORD ****|\n > 0x7E | 0x01 | 0x10 | Pin Output | Pin Select | Pin Wait |\n |******|******|******|************|************|**********|\n   Queue|NumCmd| DAP_SWJ_Pins                              |\n\n | BYTE | BYTE | BYTE | SHORT |\n > 0x7E | 0x01 | 0x09 | Delay |\n |******|******|******|*******|\n   Queue|NumCmd| DAP_Delay    |\n\n | BYTE | BYTE ******| BYTE ******| WORD ****|\n > 0x10 | Pin Output | Pin Select | Pin Wait |\n |******|************|************|**********|\n   DAP_SWJ_Pins                              |\n\\endcode\n\n\\b Response:\n\n\\code\n | BYTE | BYTE | BYTE | BYTE *****| BYTE | BYTE **|\n < 0x7F | 0x02 | 0x10 | Pin Input | 0x09 | Status |\n |******|******|******|***********|******|********|\n        |NumCmd| DAP_SWJ_Pins     | DAP_Delay     |\n\n | BYTE | BYTE | BYTE | BYTE *****|\n < 0x7F | 0x01 | 0x10 | Pin Input |\n |******|******|******|***********|\n        |NumCmd| DAP_SWJ_Pins     |\n\n | BYTE | BYTE | BYTE | BYTE **|\n < 0x7F | 0x01 | 0x09 | Status |\n |******|******|******|********|\n        |NumCmd| DAP_Delay     |\n\n | BYTE | BYTE *****|\n < 0x10 | Pin Input |\n |******|***********|\n   DAP_SWJ_Pins     |\n\\endcode\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_UART_Transport DAP_UART_Transport\n\\ingroup DAP_uart_gr\n\\brief Set UART transport mode.\n\nDAP_UART_Transport (0x1F):\n-------------------------\n\nSets the UART transport mode for receiving and transmitting data.\n\n<b>DAP_UART_Transport Request:</b>\n\\code\n | BYTE | BYTE      |\n > 0x1F | Transport |\n |******|***********|\n\\endcode\n\n- <b>Transport</b>:\n  - 0 - None (default, if transport via USB COM Port is not implemented).\n  - 1 - Transport data via USB COM Port (default, if implemented).\n  - 2 - Transport data via DAP commands.\n\n\\note By default, data is transported via the USB COM Port (if implemented). In this case,\n      the UART is controlled via a terminal (for example Putty), which can configure the\n      UART (data bits, party, baudrate ...) and transfer the data.\n\n\\note When transport data via DAP is enabled, CMSIS-DAP takes control over the UART with commands:\n      \\ref DAP_UART_Configure, \\ref DAP_UART_Control, \\ref DAP_UART_Status and \\ref DAP_UART_Transfer.\n\n<b>DAP_UART_Transport Response:</b>\n\\code\n | BYTE | BYTE   |\n < 0x1F | Status |\n |******|********|\n\\endcode\n\n- <b>Status</b>: \\ref DAP_Response_Status\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_UART_Configure DAP_UART_Configure\n\\ingroup DAP_uart_gr\n\\brief Set UART configuration.\n\nDAP_UART_Configure (0x20):\n-------------------------\n\nSets the UART configuration (only for transport via DAP).\n\n<b>DAP_UART_Configure Request:</b>\n\\code\n | BYTE | BYTE    | WORD     |\n > 0x20 | Control | Baudrate |\n |******|*********|**********|\n\\endcode\n\n- <b>Control</b>: Parameter values are compatible with CMSIS-Driver USART Interface in asynchronous mode and\n  without flow control:\n  - Bit 3..0: Data bits: 5 = 5 Data bits, 6 = 6 Data bits, 7 = 7 Data bits, 0 = 8 Data bits\n  - Bit 5..4: Parity: 0 = None, 1 = Even, 2 = Odd\n  - Bit 7..6: Stop bits: 0 = 1 Stop bit, 1 = 2 Stop bits\n\n- <b>Baudrate</b>: Requested baudrate\n\n\\note \\ref DAP_UART_Configure command can be used only if transport via DAP is enabled.\\n\n\n\\note It is required to configure the UART each time transport via DAP is enabled (\\ref DAP_UART_Transport command).\\n\n      It is recommended to configure the UART before receive and transmit are enabled (\\ref DAP_UART_Control command).\n\n<b>DAP_UART_Configure Response:</b>\n\\code\n | BYTE | BYTE   | WORD     |\n > 0x20 | Status | Baudrate |\n |******|********|**********|\n\\endcode\n\n- <b>Status</b>: 0x00 = OK else ERROR:\n  - Bit 0: 1 = Data bits configuration error.\n  - Bit 1: 1 = Parity configuration error.\n  - Bit 2: 1 = Stop bits configuration error.\n  - Bit 7..3: reserved (0)\n\n- <b>Baudrate</b>: Actual baudrate or 0 (baudrate configuration error).\n    When requested baudrate is not achievable the closest configured baudrate can be returned or 0\n    which indicates baudrate configuration error.\n\n\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_UART_Control DAP_UART_Control\n\\ingroup DAP_uart_gr\n\\brief Control UART data receive and transmit.\n\nDAP_UART_Control (0x22):\n-------------------------\n\nEnables and disables UART receive and transmit (only for transport via DAP).\n\n<b>DAP_UART_Control Request:</b>\n\\code\n | BYTE | BYTE    |\n > 0x22 | Control |\n |******|*********|\n\\endcode\n\n- <b>Control</b>:\n  - Bit 0: 1 = Receive Enable, 0 = no operation\n  - Bit 1: 1 = Receive Disable, 0 = no operation\n  - Bit 2: 1 = Receive Buffer Flush, 0 = no operation\n  - Bit 3: reserved (0)\n  - Bit 4: 1 = Transmit Enable, 0 = no operation\n  - Bit 5: 1 = Transmit Disable, 0 = no operation\n  - Bit 6: 1 = Transmit Buffer Flush, 0 = no operation\n  - Bit 7: reserved (0)\n\n\\note \\ref DAP_UART_Control command can be used only if transport via DAP is enabled.\\n\n      Receive/Transmit enable bit can be set only if DAP UART is already configured (\\ref DAP_UART_Configure).\\n\n\n\\note When enable and disable bits are set at the same time, only disable is executed.\\n\n      Receive/Transmit enable also automatically flushes any existing data in Receive/Transmit buffer.\n\n<b>DAP_UART_Control Response:</b>\n\\code\n | BYTE | BYTE   |\n > 0x22 | Status |\n |******|********|\n\\endcode\n\n- <b>Status</b>: \\ref DAP_Response_Status\n\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_UART_Status DAP_UART_Status\n\\ingroup DAP_uart_gr\n\\brief Get UART status.\n\nDAP_UART_Status (0x23):\n-------------------------\n\nReads UART status (only for transport via DAP).\n\n<b>DAP_UART_Status Request:</b>\n\\code\n | BYTE |\n > 0x23 |\n |******|\n\\endcode\n\n\\note \\ref DAP_UART_Status command can be used only if transport via DAP is enabled.\\n\n\n\n<b>DAP_UART_Status Response:</b>\n\\code\n | BYTE | BYTE   | WORD     | WORD     |\n > 0x23 | Status | Rx Count | Tx Count |\n |******|********|**********|**********|\n\\endcode\n\n- <b>Status</b>:\n  - Bit 0: 1 = Receive enabled, 0 = Receive disabled\n  - Bit 1: 1 = Data lost detected during receive (automatically cleared)\n  - Bit 2: 1 = Framing error detected (automatically cleared)\n  - Bit 3: 1 = Parity error detected (automatically cleared)\n  - Bit 4: 1 = Transmit enabled, 0 = Transmit disabled\n  - Bit 7..5: reserved (0)\n\n- <b>Rx Count</b>: Number of bytes in UART receive buffer (not yet read)\n\n- <b>Tx Count</b>: Number of bytes in UART transmit buffer (not yet transmitted)\n\n\n*/\n\n/**************************************************************************************************/\n/**\n\\defgroup DAP_UART_Transfer DAP_UART_Transfer\n\\ingroup DAP_uart_gr\n\\brief Transfer data via UART.\n\nDAP_UART_Transfer (0x21):\n-------------------------\n\nReceive and Transmit data via target UART (only for transport via DAP).\n\n<b>DAP_UART_Transfer Request:</b>\n\n\\code\n | BYTE | SHORT    | SHORT   | BYTE          |\n > 0x21 | Rx Count | Tx Count| Transmit data |\n |******|**********|*********|+++++++++++++++|\n\\endcode\n\n- <b>Rx Count</b>: Maximum number of bytes to be read from UART receive buffer.\n\n- <b>Tx Count</b>: Number of bytes in <b>Transmit data</b> to be transmitted.\n\n\\note \\ref DAP_UART_Transfer command can be used only if transport via DAP is enabled.\\n\n\n\\note If only receive is required, Tx Count can be 0.\\n\n      If only transmit is required, Rx Count can be 0.\n\n<b>DAP_UART_Transfer Response:</b>\n\n\\code\n | BYTE | BYTE   | SHORT    | SHORT    | BYTE          |\n < 0x21 | Status | Tx Count | Rx Count | Receive data  |\n |******|********|**********|**********|+++++++++++++++|\n\\endcode\n\n- <b>Status</b>:\n  - Bit 0: 1 = Receive enabled, 0 = Receive disabled\n  - Bit 1: 1 = Data lost detected during receive (automatically cleared)\n  - Bit 2: 1 = Framing error detected (automatically cleared)\n  - Bit 3: 1 = Parity error detected (automatically cleared)\n  - Bit 4: 1 = Transmit enabled, 0 = Transmit disabled\n  - Bit 7..5: reserved (0)\n\n- <b>Tx Count</b>: Number of bytes accepted from <b>Transmit data</b> and queued to UART transmit buffer.\n\n- <b>Rx Count</b>: Number of bytes in <b>Receive data</b> read from UART receive buffer.\n\n- <b>Receive data</b>: Bytes received from the target device via UART.\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DAP/src/dap_config.txt",
    "content": "/**************************************************************************************************/\n/**\n\\defgroup DAP_Config_gr Firmware configuration\n\nCMSIS-DAP is designed for debug units with a Cortex-M microcontroller.\n\nThe CMSIS-DAP firmware can be deployed to a debug unit that is based on Cortex-M processor-based microcontroller.\n\n\\image html \"CMSIS_DAP_Debug_Unit.png\" \"CMSIS-DAP debug unit Hardware\"\n\nThe picture below shows the setup with an isolation adapter.\n\n\\image html \"CMSIS_DAP_Debug_Unit_ISO.png\" \"CMSIS-DAP debug unit with isolation adapter\"\n\nHardware requirements\n---------------------\nThe CMSIS-DAP firmware is designed for debug units that fulfil the following hardware\nrequirements:\n  - Cortex-M processor-based microcontroller.\n  - CPU Clock: 48 MHz or higher; microcontroller must have a SYSTICK timer.\n  - RAM: 8 KB or more.\n  - Flash ROM: 16 KB or more.\n  - Full-speed or High-speed USB Device peripheral.\n  - 7 standard I/O pins for JTAG/SWD interface.\n  - Optionally, 2 I/O pins for status LEDs.\n  - Optionally, a UART to support SWO capturing (Rx pin connected to SWO).\n  - Optionally, a UART to support an additional UART communication port (for printf debugging).\n  \nCMSIS-DAP firmware\n------------------\nThe CMSIS-DAP firmware can be configured for a new debug unit using at least the \n<a href=\"https://www.keil.com/mdk5\" target=\"_blank\">Keil MDK-Plus or MDK-Professional Edition</a>.\nReference implementations are provided as source code with complete project files\nand may be used as starting point for the firmware deployment to a new debug unit.\n\nThe folder <b>.\\\\Firmware\\\\Config</b> contains a template of the \\b DAP_config.h configuration file.\nVarious adaptations for different target hardware are provided.\n\nFolders and Files                     | Description\n------------------------------------- | -----------------------------------------------------------------------\n.\\\\Firmware\\\\Examples\\\\LPC-Link2      | CMSIS-DAP firmware using USB bulk transfers adapted to the NXP LPC-Link2 debug unit.\n.\\\\Firmware\\\\Examples\\\\MCU-LINK       | CMSIS-DAP firmware using USB bulk transfers adapted to the NXP MCU-LINK debug unit.\n\nThe CMSIS-DAP firmware is designed to execute on a debug unit that is using a Cortex-M processor-based microcontroller. To\ndeploy the firmware to a new debug unit copy an existing firmware adaptation to a new folder. For example, copy the folder\n.\\\\Firmware\\\\Examples\\\\MCU-LINK to a folder called .\\\\Firmware\\\\MyDebugUnit.\n\nTo following steps describe the adaptation of the CMSIS-DAP firmware to a new debug unit:\n1. \\ref DAP_ConfigMCU_gr :  Select the microcontroller and replace the CMSIS-Core (Cortex-M) files.\n2. \\ref DAP_ConfigIO_gr : Adapt the I/O ports and specify other parameters for the debug unit.\n3. \\ref DAP_ConfigUSB_gr : Adapt the USB peripheral to the microcontroller.\n4. \\ref DAP_USART_SWO_gr : Optionally, you may add a CMSIS-Driver USART to interface to SWO.\n5. \\ref DAP_USART_COM_gr : Optionally, you may add a CMSIS-Driver USART to interface to UART communication port.\n6. \\ref DAP_Vendor_gr : Optionally, you may add vendor specific commands to the debug unit.\n7. \\ref DAP_ConfigFlash_gr : Program the adapted firmware to the Flash ROM of the new debug unit.\n8. \\ref DAP_Validate_gr : Validate the CMSIS-DAP firmware of the new debug unit.\n@}\n**************************************************************************************************/\n\n/**\n\\defgroup DAP_ConfigMCU_gr Debug Unit Processor\n\\ingroup DAP_Config_gr\n@{\nCMSIS-DAP firmware runs on debug units with a Cortex-M microcontroller.\n\nThe CMSIS-DAP firmware is designed to execute on a debug unit that is using a Cortex-M processor-based microcontroller.\n\nThe following steps describe how to change the microcontroller in the CMSIS-DAP firmware project:\n\n1. In the µVision IDE, open the project file <b>.\\\\Firmware\\\\MyDebugUnit\\\\CMSIS_DAP.uvprojx</b>.\n2. Open the <b>Project - Options - Device</b> dialog and select the microcontroller of the new debug unit.\n4. Optionally, you may modify the project file <b>Target</b> name and the file <b>Abstract.txt</b> to reflect the new debug unit.\n\n\\image html \"MDK_Device.png\" \"Select the microcontroller\"\n\nIn MDK, changing the microcontroller adds relevant software components for the new target. However, depending on the\navailability you may need to replace some components with custom implementations.\n\n\\image html \"RTE.png\" \"Replace missing software components\"\n\n\n@}\n**************************************************************************************************/\n\n/**\n\\defgroup DAP_ConfigIO_gr Configure I/O ports and debug unit\n\\ingroup DAP_Config_gr\n@{\nDAP_config.h configures I/O ports and debug unit hardware parameters.\n\nThe CMSIS-DAP firmware configuration file \\b DAP_config.h provides the interface functions and configuration\nparameters for the hardware of the CMSIS-DAP debug unit.\n@}\n**************************************************************************************************/\n\n/**\n\\defgroup DAP_ConfigUSB_gr Configure USB peripheral\n\\ingroup DAP_Config_gr\n@{\nCMSIS-DAP firmware communicates via USB with the host computer. The USB communication is implemented via MDK-Middleware\ncomponents that access the USB peripheral of the microcontroller.\n\nThe CMSIS-DAP v2 firmware uses \\ref BulkUSB \"USB bulk endpoints\" that provide high-speed communication. In addition,\n\\ref USB_CDC is used to enable USB COM port.\n\nFor the USB interface it is important to provide correct configuration information for the USB peripheral as described in this section.\n\nThe following steps describe how to change and configure the USB peripheral in the CMSIS-DAP firmware project:\n\n1. In the <b>Project Window</b>, the group <b>USB</b> contains USB interface with the relevant configuration files.\n2. Open the file <b>usb_config_0.c</b> in the editor and select <b>Configuration Wizard</b> as edit mode; then change the following settings:\n  - <b>USB Device 0 - High-speed</b>: enable this option only for a high-speed USB peripheral; disable for full-speed USB.\n  - Update <b>Device Settings - Vendor ID</b> which is provided by the <a href=\"http://www.usb.org/developers/vendor/\" target=\"_blank\">USB Implementers Forum</a>.\n  - Update <b>Device Settings - Product ID</b> to provide a unique identification for the debug unit.\n  - Update <b>Device Settings - Device Release Number</b> to indicate the revision of the adaptation.\n  - Update <b>String Settings - Manufacturer String</b> to reflect the vendor of the debug unit. This setting should match the <b>Vendor ID</b>.\n  - Update <b>String Settings - Product String</b> to indicate the debug unit. Note that \"CMSIS-DAP\" must be part of that string to allow identification by debuggers (or part of interface string for USB composite device).\n  - Optionally each debug unit may provide a unique <b>Serial Number String</b>. If the <b>String Settings - Serial Number String</b> is not provided, only one debug unit can be connected at the same time to a host computer since it is impossible to identify multiple debug units.\n\n  \n\\note \n  - The USB Device setting high-speed / full-speed USB must be reflected in the \\b DAP_config.h file as described under \\ref DAP_Config_gr.\n  - The <b>String Settings - Product String</b> must contain \"CMSIS-DAP\" somewhere in the string. This is used by the debuggers to identify a CMSIS-DAP compliant debug unit that is connected to a host computer.\n\n<br>\n\\image html \"MDK_USB.png\" \"Adapt the USB Peripheral to the microcontroller\"\n\n\\page BulkUSB Communication via USB bulk endpoints\n\nCMSIS-DAP v2 uses USB bulk endpoints and is therefore faster than the deprecated v1. Optionally, support for streaming SWO\ntrace is provided via an additional USB endpoint.\n\nThis configuration requires custom class support with the interface setting:\n- Class Code: 0xFF (Vendor specific)\n- Subclass: 0x00\n- Protocol code: 0x00\n\n\\note This interface enables also <a href=\"https://wicg.github.io/webusb/\" target=\"_blank\">WebUSB</a> technology that is used in web browsers to connect to a debug adapter connected to your PC.\n\nDepending on the configuration, it uses the following USB endpoints which should be configured in the interface descriptor in this order:\n  - Endpoint 1: Bulk Out – used for commands received from host PC.\n  - Endpoint 2: Bulk In – used for responses send to host PC.\n  - Endpoint 3: Bulk In (optional) – used for streaming SWO trace (if enabled with \\ref SWO_STREAM).\n\n\\image html \"MDK_USB_Custom.png\" \"Configuration settings for the USB custom class\"\n\n\\note These settings allow support in Windows (8 and above), Mac OS, and Linux without further drivers. Some additional\nsettings are required to automatically install CMSIS-DAP enabled debug adapters in these operating systems.\n\n\n<b>Additional settings for Microsoft Windows</b>\n<br><br>\nFor automatic installation of a CMSIS-DAP v2 enabled debug adapter in Windows, use the following WinUSB GUID in the USB\ncustom class:\n\\code\n{CDB3B5AD-293B-4663-AA36-1AAE46463776}\n\\endcode\n\nThe picture below shows the WinUSB GIUD configuration of the USB custom class:\n\n\\image html \"MDK_USB_Custom_WinUSBGIUD.png\" \"Adapt CMSIS-DAP to the WinUSB class\"\n\n\\anchor wininf\n<b>USB Driver and *.inf file</b>\n<br><br>\nWindows 8 and above does not require a WinUSB driver provided that the USB firmware stack supports Microsoft descriptors. \nCMSIS-DAP v2 device should be configured as WCID (Windows Compatible ID) device which provides extra information to a Windows system\nto facilitate automated driver installation. \n<br><br>\nFor Windows 7, the CMSIS-DAP v2 device will install automatically if the PC is connected to the Internet and device\ninstallation settings are set to automatically download and install drivers for devices. The installed device will be seen\nin the Device Manager under Universal Serial Bus devices as a WinUSB Device.\n<br><br>\nIf no Internet connection is available or you want the device to show with a different name in the Device Manager, you\nshould provide an .inf file and sign it to generate .cat files. More information is available from Microsoft under the topic  \n<a href=\"https://technet.microsoft.com/en-us/library/dd919238(v=ws.10).aspx\" target=\"_blank\">Steps for Signing a Device Driver Package</a>.\n<br>\n\nThe following CMSIS_DAP_v2.inf file should be provided for an Windows 7 host PC.\n\n\\verbinclude Firmware/Template/CMSIS_DAP_v2.inf\n\n\\page USB_CDC Communication Device Class\n\nCMSIS-DAP v2 supports also a UART communication port optionally routed to a USB COM port which is implemented by a USB\nCommunication Device Class (CDC) device. \n<br><br>\n\nThe picture below shows the configuration of the USB CDC class.\n<br>\n\n\\image html \"MDK_USB_CDC.png\" \"Configuration of USB CDC class\"\n\n@}\n**************************************************************************************************/\n\n/**\n\\defgroup DAP_ConfigFlash_gr Flash program the firmware\n\\ingroup DAP_Config_gr\n@{\nThe CMSIS-DAP firmware is programmed into the Flash ROM of a debug unit.\n\nOnce the CMSIS-DAP firmware is configured, it needs to be programmed into the Flash ROM of the new debug unit. MDK provides\nFlash algorithms for many Cortex-M based microcontrollers and therefore you may use the Flash programming facilities that\n\n\nare provide in µVision. Once Flash programming is configured, you may use the µVision menu item <b>Flash - Download</b>.\n\n\\image html \"MDK_Flash.png\" \"Download CMSIS-DAP firmware to new debug unit using MDK\"\n@}\n**************************************************************************************************/\n/**\n\\defgroup DAP_USART_SWO_gr Connect SWO trace\n@{\n\\brief Optionally, you may add a CMSIS-Driver USART to interface to SWO.\n\\details\nA CMSIS-Driver USART can be used to capture the trace output on the SWO pin using a UART RX input on the\nmicrocontroller. UART Serial Wire Output (SWO) trace can be enabled and configured in the header DAP_Config.h.\n\\#define SWO_UART is used to enable the UART SWO and \\#define SWO_UART_DRIVER\nis used to configure USART Driver instance number (Driver_USART#).\n<br><br>\nRefer to \\ref DAP_Config_Debug_gr for more information.\n@}\n**************************************************************************************************/\n/**\n\\defgroup DAP_USART_COM_gr Connect UART communication port\n@{\n\\brief Optionally, you may add a CMSIS-Driver USART to interface to UART communication port.\n\\details\nA CMSIS-Driver USART can be used to receive data from the target and transmit data to the target using\nUART RX and TX pins on the microcontroller. The UART communication port can be enabled and configured in the header\nDAP_Config.h. \\#define DAP_UART is used to enable the UART communication port and \\#define DAP_UART_DRIVER\nis used to configure USART Driver instance number (Driver_USART#).\n<br><br>\nRefer to \\ref DAP_Config_Debug_gr for more information.\n@}\n**************************************************************************************************/\n\n/**\n\\defgroup DAP_Validate_gr Validate the debug unit operation\n@{\nA CMSIS-DAP conforming debug unit must be validated.\n\nA validation project for Arm Keil MDK is provided in the folder <b>.\\\\Firmware\\\\Validation\\\\MDK5</b>.\nThe <b>Validation.uvprojx</b> project contains a simple application that needs to be adapted to the target hardware\nconnected to the debug unit. Once the adaptation is complete, you may open a Command window and\ncall the batch file <b>test.bat</b> (optionally with the path to the µVision executable):\n\n\\image html \"MDK_Validation.png\" \"Validate debug unit using target hardware and Arm Keil MDK\"\n\nThe batch file will create a \\c test_results.txt and \\c test.log file in the project directory.\n@}\n**************************************************************************************************/\n\n/**\n\\defgroup DAP_Commands_gr CMSIS-DAP Commands\n**************************************************************************************************/\n\n/**\n\\defgroup DAP_Vendor_gr CMSIS-DAP Vendor Commands\n@{\nExtend CMSIS-DAP firmware with commands.\n\nThe CMSIS-DAP firmware may be extended with commands that are specific to a debug unit.\nVendor Commands may implement additional functionality such as interfaces to serial printf-style communication.\nThe RDDI-DAP interface offers the function \\c CMSIS_DAP_Commands to exchange information with vendor-specific commands.\n@}\n**************************************************************************************************/\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/BasicMathFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/BasicMathFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/BasicMathFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/BasicMathFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/BasicMathFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/BasicMathFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/BayesFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/BayesFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/BayesFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/BayesFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/BayesFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/BayesFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/ChangeLog_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/ChangeLog_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/ChangeLog_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/CommonTablesF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/CommonTablesF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/CommonTablesF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/CommonTables_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/CommonTables_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/CommonTables_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/ComplexMathFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/ComplexMathFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/ComplexMathFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/ComplexMathFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/ComplexMathFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/ComplexMathFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/ControllerFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/ControllerFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/ControllerFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/DistanceFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/DistanceFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/DistanceFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/DistanceFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/DistanceFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/DistanceFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/Examples_2ARM_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/Examples_2ARM_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/Examples_2ARM_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/FastMathFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/FastMathFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/FastMathFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/FastMathFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/FastMathFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/FastMathFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/FilteringFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/FilteringFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/FilteringFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/FilteringFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/FilteringFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/FilteringFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/InterpolationFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/InterpolationFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/InterpolationFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/InterpolationFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/InterpolationFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/InterpolationFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/MatrixFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/MatrixFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/MatrixFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/MatrixFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/MatrixFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/MatrixFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/QuaternionMathFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/QuaternionMathFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/QuaternionMathFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/SVMFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/SVMFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/SVMFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/SVMFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/SVMFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/SVMFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/Source_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/Source_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/Source_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/StatisticsFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/StatisticsFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/StatisticsFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/StatisticsFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/StatisticsFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/StatisticsFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/SupportFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/SupportFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/SupportFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/SupportFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/SupportFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/SupportFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/TransformFunctionsF16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/TransformFunctionsF16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/TransformFunctionsF16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/TransformFunctions_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/TransformFunctions_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/TransformFunctions_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/annotated.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/annotated.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/annotated.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__abs__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__abs__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__abs__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__abs__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__abs__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__abs__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__abs__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__no__idx__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__no__idx__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__no__idx__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__no__idx__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__no__idx__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__no__idx__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__no__idx__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmax__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmax__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__no__idx__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__no__idx__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__no__idx__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__no__idx__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__no__idx__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__no__idx__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__no__idx__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__absmin__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__absmin__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__add__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__add__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__add__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__add__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__add__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__add__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__add__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__and__u16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__and__u16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__and__u16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__and__u32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__and__u32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__and__u32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__and__u8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__and__u8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__and__u8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__atan2__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__atan2__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__atan2__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__atan2__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__atan2__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__atan2__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__atan2__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__atan2__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__atan2__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__atan2__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__atan2__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__atan2__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__barycenter__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__barycenter__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__barycenter__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__barycenter__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__barycenter__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__barycenter__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bayes__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bayes__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bayes__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bayes__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bayes__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bayes__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bayes__example_2train_8py.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2train_8py.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example_2train_8py.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bayes__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bayes__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bilinear__interp__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bilinear__interp__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bilinear__interp__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bilinear__interp__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bilinear__interp__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bilinear__interp__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__32x64__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__32x64__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__32x64__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__32x64__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__32x64__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__32x64__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__fast__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__fast__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__fast__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__fast__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__fast__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__fast__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df1__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df1__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df2T__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df2T__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df2T__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df2T__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df2T__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__df2T__init__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__init__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__df2T__init__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__stereo__df2T__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__stereo__df2T__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__stereo__df2T__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__stereo__df2T__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__stereo__df2T__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__stereo__df2T__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__stereo__df2T__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__stereo__df2T__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__stereo__df2T__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__biquad__cascade__stereo__df2T__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__stereo__df2T__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__biquad__cascade__stereo__df2T__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bitonic__sort__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bitonic__sort__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bitonic__sort__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bitreversal2_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bitreversal2_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bitreversal2_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bitreversal_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bitreversal_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bitreversal_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bitreversal__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bitreversal__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bitreversal__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__braycurtis__distance__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__braycurtis__distance__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__braycurtis__distance__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__braycurtis__distance__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__braycurtis__distance__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__braycurtis__distance__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__bubble__sort__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bubble__sort__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__bubble__sort__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__canberra__distance__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__canberra__distance__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__canberra__distance__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__canberra__distance__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__canberra__distance__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__canberra__distance__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__init__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix2__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix2__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix2__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix2__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix2__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix2__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix2__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix2__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix2__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix4__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix4__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix4__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix4__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix4__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix4__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix4__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix4__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix4__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix8__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix8__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix8__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cfft__radix8__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix8__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cfft__radix8__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__chebyshev__distance__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__chebyshev__distance__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__chebyshev__distance__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__chebyshev__distance__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__chebyshev__distance__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__chebyshev__distance__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__chebyshev__distance__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__chebyshev__distance__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__chebyshev__distance__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cityblock__distance__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cityblock__distance__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cityblock__distance__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cityblock__distance__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cityblock__distance__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cityblock__distance__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cityblock__distance__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cityblock__distance__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cityblock__distance__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__class__marks__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__class__marks__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__class__marks__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__class__marks__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__class__marks__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__class__marks__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__class__marks__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__class__marks__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__clip__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__clip__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__clip__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__clip__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__clip__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__clip__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__conj__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__conj__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__conj__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__conj__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__conj__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__conj__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__conj__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__conj__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__conj__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__conj__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__conj__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__conj__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__dot__prod__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__dot__prod__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__dot__prod__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__dot__prod__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__dot__prod__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__dot__prod__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__dot__prod__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__dot__prod__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__dot__prod__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__dot__prod__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__dot__prod__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__dot__prod__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__fast__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__fast__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__fast__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__squared__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__squared__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__squared__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__squared__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mag__squared__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mag__squared__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mult__cmplx__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mult__cmplx__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mult__cmplx__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mult__cmplx__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mult__cmplx__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__cmplx__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mult__real__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__real__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__real__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mult__real__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__real__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__real__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mult__real__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__real__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__real__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cmplx__mult__real__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__real__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cmplx__mult__real__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__common__tables_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__common__tables_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__common__tables_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__common__tables_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__common__tables_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__common__tables_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__common__tables__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__common__tables__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__common__tables__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__common__tables__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__common__tables__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__common__tables__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__const__structs_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__const__structs_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__const__structs_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__const__structs_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__const__structs_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__const__structs_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__const__structs__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__const__structs__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__const__structs__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__const__structs__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__const__structs__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__const__structs__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__fast__opt__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__fast__opt__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__fast__opt__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__fast__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__fast__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__fast__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__fast__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__fast__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__fast__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__opt__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__opt__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__opt__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__opt__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__opt__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__opt__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__partial__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__partial__fast__opt__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__fast__opt__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__fast__opt__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__partial__fast__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__fast__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__fast__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__partial__fast__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__fast__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__fast__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__partial__opt__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__opt__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__opt__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__partial__opt__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__opt__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__opt__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__partial__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__partial__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__partial__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__partial__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__conv__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__conv__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__convolution__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__convolution__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__convolution__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__convolution__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__convolution__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__convolution__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__convolution__example_2math__helper_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2math__helper_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2math__helper_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__convolution__example_2math__helper_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2math__helper_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example_2math__helper_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__convolution__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__convolution__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__copy__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__copy__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__copy__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__copy__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__copy__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__copy__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__copy__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__fast__opt__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__fast__opt__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__fast__opt__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__fast__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__fast__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__fast__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__fast__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__fast__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__fast__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__opt__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__opt__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__opt__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__opt__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__opt__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__opt__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlate__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlate__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlation__distance__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlation__distance__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlation__distance__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__correlation__distance__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlation__distance__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__correlation__distance__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cos__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cos__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cos__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cos__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cos__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cos__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cos__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cos__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cos__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cosine__distance__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cosine__distance__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cosine__distance__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cosine__distance__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cosine__distance__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cosine__distance__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__cosine__distance__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cosine__distance__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__cosine__distance__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dct4__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dct4__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dct4__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dct4__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dct4__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dct4__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dct4__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dice__distance_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dice__distance_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dice__distance_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__divide__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__divide__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__divide__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__divide__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__divide__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__divide__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dot__prod__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dot__prod__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dot__prod__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dot__prod__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dot__prod__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dot__prod__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dot__prod__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dotproduct__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dotproduct__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dotproduct__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dotproduct__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dotproduct__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dotproduct__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__dotproduct__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__dotproduct__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__entropy__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__entropy__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__entropy__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__entropy__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__entropy__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__entropy__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__entropy__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__entropy__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__entropy__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__euclidean__distance__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__euclidean__distance__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__euclidean__distance__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__euclidean__distance__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__euclidean__distance__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__euclidean__distance__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__euclidean__distance__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__euclidean__distance__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__euclidean__distance__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__f16__to__float_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__f16__to__float_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__f16__to__float_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__f16__to__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__f16__to__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__f16__to__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fft__bin__data_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__data_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__data_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fft__bin__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fft__bin__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fft__bin__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fft__bin__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fft__bin__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fft__bin__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fft__bin__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fft__bin__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fill__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fill__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fill__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fill__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fill__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fill__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fill__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__data_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__data_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__data_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__decimate__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__decimate__fast__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__fast__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__fast__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__decimate__fast__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__fast__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__fast__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__decimate__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__decimate__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__decimate__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__decimate__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__decimate__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__decimate__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__example_2math__helper_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2math__helper_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2math__helper_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__example_2math__helper_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2math__helper_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example_2math__helper_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__fast__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__fast__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__fast__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__fast__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__fast__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__fast__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__init__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__init__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__init__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__interpolate__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__interpolate__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__interpolate__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__interpolate__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__interpolate__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__interpolate__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__interpolate__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__lattice__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__lattice__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__lattice__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__lattice__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__lattice__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__lattice__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__lattice__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__sparse__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__sparse__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__sparse__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__sparse__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__sparse__init__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__init__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__init__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__sparse__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__sparse__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__fir__sparse__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__fir__sparse__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__float__to__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__float__to__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__float__to__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__float__to__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__float__to__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__float__to__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__float__to__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__float__to__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__float__to__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__float__to__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__float__to__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__float__to__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__gaussian__naive__bayes__predict__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__gaussian__naive__bayes__predict__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__gaussian__naive__bayes__predict__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__gaussian__naive__bayes__predict__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__gaussian__naive__bayes__predict__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__gaussian__naive__bayes__predict__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__data_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__data_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__data_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__example_2math__helper_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2math__helper_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2math__helper_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__example_2math__helper_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2math__helper_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example_2math__helper_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__graphic__equalizer__example__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__graphic__equalizer__example__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__hamming__distance_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__hamming__distance_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__hamming__distance_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__heap__sort__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__heap__sort__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__heap__sort__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__helium__utils_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__helium__utils_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__helium__utils_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__iir__lattice__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__iir__lattice__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__iir__lattice__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__iir__lattice__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__iir__lattice__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__iir__lattice__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__iir__lattice__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__insertion__sort__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__insertion__sort__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__insertion__sort__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__jaccard__distance_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__jaccard__distance_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__jaccard__distance_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__jensenshannon__distance__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__jensenshannon__distance__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__jensenshannon__distance__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__jensenshannon__distance__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__jensenshannon__distance__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__jensenshannon__distance__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__kullback__leibler__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__kullback__leibler__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__kullback__leibler__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__kullback__leibler__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__kullback__leibler__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__kullback__leibler__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__kullback__leibler__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__kullback__leibler__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__kullback__leibler__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__kulsinski__distance_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__kulsinski__distance_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__kulsinski__distance_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__levinson__durbin__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__levinson__durbin__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__levinson__durbin__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__levinson__durbin__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__levinson__durbin__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__levinson__durbin__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__levinson__durbin__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__levinson__durbin__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__levinson__durbin__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__data_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__data_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__data_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__example_2math__helper_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2math__helper_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2math__helper_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__example_2math__helper_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2math__helper_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example_2math__helper_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__linear__interp__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__linear__interp__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__norm__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__norm__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__norm__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__norm__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__norm__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__norm__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__norm__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__lms__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__lms__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__logsumexp__dot__prod__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__logsumexp__dot__prod__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__logsumexp__dot__prod__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__logsumexp__dot__prod__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__logsumexp__dot__prod__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__logsumexp__dot__prod__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__logsumexp__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__logsumexp__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__logsumexp__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__logsumexp__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__logsumexp__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__logsumexp__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__add__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__add__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__add__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__add__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__add__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__add__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__add__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__add__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__add__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__add__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__add__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__add__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cholesky__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cholesky__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cholesky__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cholesky__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cholesky__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cholesky__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cholesky__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cholesky__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cholesky__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cmplx__mult__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__mult__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__mult__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cmplx__mult__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__mult__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__mult__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cmplx__mult__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__mult__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__mult__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cmplx__mult__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__mult__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__mult__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cmplx__trans__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__trans__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__trans__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cmplx__trans__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__trans__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__trans__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cmplx__trans__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__trans__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__trans__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__cmplx__trans__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__trans__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__cmplx__trans__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__inverse__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__inverse__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__inverse__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__inverse__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__inverse__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__inverse__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__inverse__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__inverse__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__inverse__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__ldlt__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__ldlt__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__ldlt__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__ldlt__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__ldlt__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__ldlt__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__mult__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__mult__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__mult__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__mult__fast__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__fast__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__fast__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__mult__fast__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__fast__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__fast__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__mult__opt__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__opt__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__opt__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__mult__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__mult__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__mult__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__mult__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__scale__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__scale__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__scale__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__scale__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__scale__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__scale__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__scale__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__scale__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__scale__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__scale__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__scale__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__scale__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__solve__lower__triangular__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__lower__triangular__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__lower__triangular__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__solve__lower__triangular__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__lower__triangular__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__lower__triangular__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__solve__lower__triangular__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__lower__triangular__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__lower__triangular__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__solve__upper__triangular__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__upper__triangular__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__upper__triangular__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__solve__upper__triangular__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__upper__triangular__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__upper__triangular__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__solve__upper__triangular__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__upper__triangular__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__solve__upper__triangular__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__sub__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__sub__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__sub__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__sub__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__sub__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__sub__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__trans__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__trans__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__trans__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__trans__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__trans__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__trans__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__trans__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__vec__mult__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__vec__mult__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__vec__mult__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__vec__mult__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mat__vec__mult__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mat__vec__mult__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__math_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__math__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__math__memory_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math__memory_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math__memory_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__math__types_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math__types_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math__types_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__math__types__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math__types__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__math__types__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__matrix__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__matrix__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__matrix__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__matrix__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__matrix__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__matrix__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__matrix__example_2math__helper_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2math__helper_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2math__helper_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__matrix__example_2math__helper_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2math__helper_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example_2math__helper_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__matrix__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__matrix__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__no__idx__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__no__idx__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__no__idx__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__no__idx__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__no__idx__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__no__idx__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__no__idx__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__max__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__max__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mean__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mean__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mean__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mean__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mean__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mean__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mean__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__merge__sort__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__merge__sort__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__merge__sort__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__merge__sort__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__merge__sort__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__merge__sort__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mfcc__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mfcc__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mfcc__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mfcc__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mfcc__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mfcc__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mfcc__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mfcc__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mfcc__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__no__idx__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__no__idx__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__no__idx__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__no__idx__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__no__idx__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__no__idx__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__no__idx__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__min__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__min__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__minkowski__distance__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__minkowski__distance__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__minkowski__distance__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__minkowski__distance__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__minkowski__distance__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__minkowski__distance__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mse__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mse__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mse__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mse__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mse__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mse__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mse__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mult__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mult__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mult__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mult__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mult__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mult__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mult__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mve__tables_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mve__tables_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mve__tables_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mve__tables_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mve__tables_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mve__tables_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mve__tables__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mve__tables__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mve__tables__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__mve__tables__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mve__tables__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__mve__tables__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__negate__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__negate__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__negate__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__negate__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__negate__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__negate__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__negate__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__not__u16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__not__u16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__not__u16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__not__u32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__not__u32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__not__u32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__not__u8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__not__u8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__not__u8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__offset__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__offset__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__offset__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__offset__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__offset__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__offset__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__offset__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__or__u16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__or__u16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__or__u16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__or__u32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__or__u32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__or__u32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__or__u8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__or__u8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__or__u8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__pid__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__pid__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__pid__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__pid__reset__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__reset__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__reset__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__pid__reset__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__reset__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__reset__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__pid__reset__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__reset__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__pid__reset__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__power__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__power__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__power__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__power__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__power__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__power__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__power__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q15__to__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q15__to__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q15__to__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q15__to__float_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q15__to__float_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q15__to__float_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q15__to__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q15__to__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q15__to__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q15__to__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q15__to__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q15__to__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q31__to__float_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q31__to__float_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q31__to__float_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q31__to__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q31__to__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q31__to__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q31__to__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q31__to__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q31__to__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q7__to__float_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q7__to__float_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q7__to__float_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q7__to__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q7__to__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q7__to__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__q7__to__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q7__to__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__q7__to__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__quaternion2rotation__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion2rotation__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion2rotation__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__quaternion__conjugate__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__conjugate__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__conjugate__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__quaternion__inverse__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__inverse__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__inverse__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__quaternion__norm__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__norm__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__norm__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__quaternion__normalize__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__normalize__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__normalize__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__quaternion__product__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__product__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__product__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__quaternion__product__single__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__product__single__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quaternion__product__single__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__quick__sort__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quick__sort__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__quick__sort__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__fast__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__fast__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__fast__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__fast__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__fast__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__fast__init__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__init__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__fast__init__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__init__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__init__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__init__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__init__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__init__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__init__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rfft__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rfft__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rms__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rms__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rms__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rms__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rms__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rms__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rms__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rms__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rms__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rms__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rms__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rms__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rogerstanimoto__distance_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rogerstanimoto__distance_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rogerstanimoto__distance_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__rotation2quaternion__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rotation2quaternion__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__rotation2quaternion__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__russellrao__distance_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__russellrao__distance_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__russellrao__distance_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__scale__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__scale__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__scale__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__scale__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__scale__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__scale__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__scale__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__selection__sort__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__selection__sort__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__selection__sort__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__shift__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__shift__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__shift__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__shift__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__shift__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__shift__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__shift__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__shift__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__shift__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__data_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__data_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__data_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__example_2math__helper_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2math__helper_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2math__helper_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__example_2math__helper_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2math__helper_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example_2math__helper_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__signal__converge__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__signal__converge__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__cos__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__cos__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__cos__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__cos__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__cos__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__cos__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__cos__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__cos__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__cos__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__cos__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sin__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sin__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sokalmichener__distance_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sokalmichener__distance_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sokalmichener__distance_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sokalsneath__distance_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sokalsneath__distance_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sokalsneath__distance_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sort__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sort__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sort__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sort__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sort__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sort__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__spline__interp__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__spline__interp__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__spline__interp__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__spline__interp__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__spline__interp__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__spline__interp__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sqrt__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sqrt__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sqrt__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sqrt__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sqrt__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sqrt__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__std__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__std__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__std__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__std__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__std__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__std__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sub__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sub__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sub__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sub__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sub__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__sub__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__sub__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__example_2train_8py.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2train_8py.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example_2train_8py.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__linear__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__linear__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__linear__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__linear__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__linear__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__linear__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__linear__predict__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__linear__predict__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__linear__predict__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__linear__predict__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__linear__predict__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__linear__predict__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__polynomial__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__polynomial__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__polynomial__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__polynomial__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__polynomial__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__polynomial__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__polynomial__predict__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__polynomial__predict__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__polynomial__predict__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__polynomial__predict__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__polynomial__predict__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__polynomial__predict__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__rbf__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__rbf__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__rbf__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__rbf__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__rbf__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__rbf__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__rbf__predict__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__rbf__predict__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__rbf__predict__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__rbf__predict__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__rbf__predict__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__rbf__predict__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__sigmoid__init__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__sigmoid__init__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__sigmoid__init__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__sigmoid__init__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__sigmoid__init__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__sigmoid__init__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__sigmoid__predict__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__sigmoid__predict__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__sigmoid__predict__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__svm__sigmoid__predict__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__sigmoid__predict__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__svm__sigmoid__predict__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__var__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__var__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__var__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__var__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__var__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__var__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__variance__example_2ARMCM0__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM0__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM0__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__variance__example_2ARMCM3__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM3__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM3__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__variance__example_2ARMCM4__FP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM4__FP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM4__FP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__variance__example_2ARMCM55__FP__MVE__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM55__FP__MVE__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM55__FP__MVE__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__variance__example_2ARMCM7__SP__config_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM7__SP__config_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2ARMCM7__SP__config_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__variance__example_2Abstract_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2Abstract_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example_2Abstract_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__variance__example__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__variance__example__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vec__math_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vec__math_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vec__math_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vec__math__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vec__math__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vec__math__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vexp__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vexp__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vexp__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vexp__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vexp__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vexp__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vexp__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vexp__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vexp__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vinverse__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vinverse__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vinverse__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vlog__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vlog__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vlog__f64_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__f64_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__f64_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vlog__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__vlog__q31_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__q31_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__vlog__q31_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__weighted__sum__f16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__weighted__sum__f16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__weighted__sum__f16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__weighted__sum__f32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__weighted__sum__f32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__weighted__sum__f32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__xor__u16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__xor__u16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__xor__u16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__xor__u32_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__xor__u32_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__xor__u32_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__xor__u8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__xor__u8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__xor__u8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm__yule__distance_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__yule__distance_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm__yule__distance_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_bayes_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_bayes_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_bayes_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_class_marks_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_class_marks_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_class_marks_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_convolution_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_convolution_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_convolution_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_dotproduct_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_dotproduct_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_dotproduct_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_fft_bin_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_fft_bin_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_fft_bin_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_fir_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_fir_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_fir_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_graphic_equalizer_example_q31_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_graphic_equalizer_example_q31_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_graphic_equalizer_example_q31_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_linear_interp_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_linear_interp_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_linear_interp_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_matrix_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_matrix_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_matrix_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_signal_converge_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_signal_converge_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_signal_converge_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_sin_cos_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_sin_cos_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_sin_cos_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_svm_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_svm_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_svm_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/arm_variance_example_f32_8c-example.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_variance_example_f32_8c-example.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/arm_variance_example_f32_8c-example.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/basic__math__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/basic__math__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/basic__math__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/basic__math__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/basic__math__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/basic__math__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/bayes__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/bayes__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/bayes__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/bayes__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/bayes__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/bayes__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/classes.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/classes.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/classes.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/cmsis.css",
    "content": "/* The standard CSS for doxygen */\n\nbody, table, div, p, dl {\n\tfont-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\n\tfont-size: 13px;\n\tline-height: 1.3;\n}\n\n/* CMSIS styles */\n\n.style1 {\n\t\ttext-align: center;\n}\n.style2 {\n\t\tcolor: #0000FF;\n\t\tfont-weight: normal;\n}\n.style3 {\n\t\ttext-align: left;\n}\n.style4 {\n\t\tcolor: #008000;\n}\n.style5 {\n\t\tcolor: #0000FF;\n}\n.style6 {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n.mand {\n\t\tcolor: #0000FF;\n}\n.opt {\n\t\tcolor: #008000;\n}\n.cond {\n\t\tcolor: #990000;\n}\n\n.choice \n{\n\tbackground-color:#F7F9D0;\n}\n.seq \n{\n\tbackground-color:#C9DECB;\n}\n.group1\n{\n\tbackground-color:#F8F1F1;\n}\n.group2\n{\n\tbackground-color:#DCEDEA;\n}\n\n\nul ul {\n\t\tlist-style-type: disc;\n}\n\nul ul ul {\n\t\tlist-style-type: disc;\n}\n\nul.hierarchy {\n\t\tcolor: green;\n}\n\nem {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n\n\n\n/*  CMSIS Tables */\ntable.cmtab1 {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: justify;\n\twidth:70%;\n}\n\nth.cmtab1 {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n\theight: 28px;\n}\n\ntd.cmtab1 {\n\tpadding:1px;\n\ttext-align: left;\n}\n\ntable.cmtable {\n\tborder-collapse:collapse;\n\ttext-align: justify;\n}\n\ntable.cmtable td, table.cmtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.cmtable th {\n\tbackground-color: #EBEFF6;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n\ttext-align:left;\n}\n\ntd.MonoTxt {\n\tfont-family:\"Arial monospaced for SAP\";\n}\n\ntd.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.h2 \n{\n\tfont-size: 120%;\n\tfont-weight: bold;\n}\n\ndiv.new\n{\n\tbackground-color:#ccffcc; /* light green */\n}\n\ndiv.mod\n{\n\tbackground-color:#ffe6cc;  /* light amber */\n}\n\ndiv.del\n{\n\tbackground-color:#ffcccc;  /* light red */\n}\n\n/* @group Heading Levels */\n\nh1 {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2 {\n\tfont-size: 120%;\n}\n\nh3 {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3A568E;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4464A5;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9AAED5;\n\tcolor: #ffffff;\n\tborder: 1px double #849CCC;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3A568E;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #293C63;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2B4069;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #EBEFF6;\n\tcolor: #000000;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        width: 100%;\n        margin-bottom: 10px;\n        border: 1px solid #A7B8DA;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A7B8DA;\n        border-bottom: 1px solid #A7B8DA;\n        vertical-align: top;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A7B8DA;\n        width: 100%;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        font-size: 90%;\n        color: #233456;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A7B8DA;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tmargin-left: 5px;\n\tfont-size: 8pt;\n\tpadding-left: 5px;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C3CFE6;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 7px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5072B7;\n}\n\n.image\n{\n        text-align: left;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #8EA4D0;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#314877;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D7DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4464A5;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/complex__math__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/complex__math__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/complex__math__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/complex__math__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/complex__math__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/complex__math__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/controller__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/controller__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/controller__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/controller__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/controller__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/controller__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/deprecated.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/deprecated.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/deprecated.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/distance__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/distance__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/distance__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/distance__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/distance__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/distance__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/doxygen.css",
    "content": "/* The standard CSS for doxygen 1.8.6 */\n\nbody, table, div, p, dl {\n\tfont: 400 14px/22px Roboto,sans-serif;\n}\n\n/* @group Heading Levels */\n\nh1.groupheader {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont: 400 14px/28px Roboto,sans-serif;\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2.groupheader {\n\tborder-bottom: 1px solid #879ECB;\n\tcolor: #354C7B;\n\tfont-size: 150%;\n\tfont-weight: normal;\n\tmargin-top: 1.75em;\n\tpadding-top: 8px;\n\tpadding-bottom: 4px;\n\twidth: 100%;\n}\n\nh3.groupheader {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd {\n\tmargin-top: 2px;\n}\n\np.starttd {\n\tmargin-top: 0px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3D578C;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4665A2;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL 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13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\ndiv.line.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 10px cyan;\n}\n\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C4CFE5;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C4CFE5;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EEF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9CAFD4;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4A6AAA;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td, .fieldtable tr {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow, .fieldtable tr.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memSeparator {\n        border-bottom: 1px solid #DEE4F0;\n        line-height: 1px;\n        margin: 0px;\n        padding: 0px;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4665A2;\n        white-space: nowrap;\n\tfont-size: 80%;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4665A2;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n        display: table !important;\n        width: 100%;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A8B8D9;\n        border-left: 1px solid #A8B8D9;\n        border-right: 1px solid #A8B8D9;\n        padding: 6px 0px 6px 0px;\n        color: #253555;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E8F2;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A8B8D9;      \n        border-left: 1px solid #A8B8D9;      \n        border-right: 1px solid #A8B8D9; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n.paramname code {\n        line-height: 14px;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #728DC1;\n        border-top:1px solid #5373B4;\n        border-left:1px solid #5373B4;\n        border-right:1px solid #C4CFE5;\n        border-bottom:1px solid #C4CFE5;\n\ttext-shadow: none;\n\tcolor: white;\n\tmargin-right: 4px;\n\tpadding: 2px 3px;\n\tborder-radius: 3px;\n\tfont-size: 7pt;\n\twhite-space: nowrap;\n\tvertical-align: middle;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n\tpadding-top: 3px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.entry a img {\n        border: none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tpadding-top: 3px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3D578C;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #2A3D61;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #374F7F;\n\tcolor: #FFFFFF;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        /*width: 100%;*/\n        margin-bottom: 10px;\n        border: 1px solid #A8B8D9;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        vertical-align: top;\n}\n\n.fieldtable td.fieldname {\n        padding-top: 3px;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A8B8D9;\n        /*width: 100%;*/\n}\n\n.fieldtable td.fielddoc p:first-child {\n        margin-top: 0px;\n}       \n        \n.fieldtable td.fielddoc p:last-child {\n        margin-bottom: 2px;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E8F2;\n        font-size: 90%;\n        color: #253555;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A8B8D9;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\tbackground-position: 0 -5px;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#8AA0CC;\n\tborder:solid 1px #C2CDE4;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#364D7C;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n\tcolor: #283A5D;\n\tfont-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;\n\ttext-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n\ttext-decoration: none;        \n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6884BD;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#364D7C;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tfont-size: 8pt;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C4CFE5;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 10px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5373B4;\n}\n\n.image\n{\n        text-align: center;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.diagraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #90A5CE;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#334975;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D8DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4665A2;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n/* tooltip related style info */\n\n.ttc {\n        position: absolute;\n        display: none;\n}\n\n#powerTip {\n\tcursor: default;\n\twhite-space: nowrap;\n\tbackground-color: white;\n\tborder: 1px solid gray;\n\tborder-radius: 4px 4px 4px 4px;\n\tbox-shadow: 1px 1px 7px gray;\n\tdisplay: none;\n\tfont-size: smaller;\n\tmax-width: 80%;\n\topacity: 0.9;\n\tpadding: 1ex 1em 1em;\n\tposition: absolute;\n\tz-index: 2147483647;\n}\n\n#powerTip div.ttdoc {\n        color: grey;\n\tfont-style: italic;\n}\n\n#powerTip div.ttname a {\n        font-weight: bold;\n}\n\n#powerTip div.ttname {\n        font-weight: bold;\n}\n\n#powerTip div.ttdeci {\n        color: #006318;\n}\n\n#powerTip div {\n        margin: 0px;\n        padding: 0px;\n        font: 12px/16px Roboto,sans-serif;\n}\n\n#powerTip:before, #powerTip:after {\n\tcontent: \"\";\n\tposition: absolute;\n\tmargin: 0px;\n}\n\n#powerTip.n:after,  #powerTip.n:before,\n#powerTip.s:after,  #powerTip.s:before,\n#powerTip.w:after,  #powerTip.w:before,\n#powerTip.e:after,  #powerTip.e:before,\n#powerTip.ne:after, #powerTip.ne:before,\n#powerTip.se:after, #powerTip.se:before,\n#powerTip.nw:after, #powerTip.nw:before,\n#powerTip.sw:after, #powerTip.sw:before {\n\tborder: solid transparent;\n\tcontent: \" \";\n\theight: 0;\n\twidth: 0;\n\tposition: absolute;\n}\n\n#powerTip.n:after,  #powerTip.s:after,\n#powerTip.w:after,  #powerTip.e:after,\n#powerTip.nw:after, #powerTip.ne:after,\n#powerTip.sw:after, #powerTip.se:after {\n\tborder-color: rgba(255, 255, 255, 0);\n}\n\n#powerTip.n:before,  #powerTip.s:before,\n#powerTip.w:before,  #powerTip.e:before,\n#powerTip.nw:before, #powerTip.ne:before,\n#powerTip.sw:before, #powerTip.se:before {\n\tborder-color: rgba(128, 128, 128, 0);\n}\n\n#powerTip.n:after,  #powerTip.n:before,\n#powerTip.ne:after, #powerTip.ne:before,\n#powerTip.nw:after, #powerTip.nw:before {\n\ttop: 100%;\n}\n\n#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after {\n\tborder-top-color: #ffffff;\n\tborder-width: 10px;\n\tmargin: 0px -10px;\n}\n#powerTip.n:before {\n\tborder-top-color: #808080;\n\tborder-width: 11px;\n\tmargin: 0px -11px;\n}\n#powerTip.n:after, #powerTip.n:before {\n\tleft: 50%;\n}\n\n#powerTip.nw:after, #powerTip.nw:before {\n\tright: 14px;\n}\n\n#powerTip.ne:after, #powerTip.ne:before {\n\tleft: 14px;\n}\n\n#powerTip.s:after,  #powerTip.s:before,\n#powerTip.se:after, #powerTip.se:before,\n#powerTip.sw:after, #powerTip.sw:before {\n\tbottom: 100%;\n}\n\n#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after {\n\tborder-bottom-color: #ffffff;\n\tborder-width: 10px;\n\tmargin: 0px -10px;\n}\n\n#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before {\n\tborder-bottom-color: #808080;\n\tborder-width: 11px;\n\tmargin: 0px -11px;\n}\n\n#powerTip.s:after, #powerTip.s:before {\n\tleft: 50%;\n}\n\n#powerTip.sw:after, #powerTip.sw:before {\n\tright: 14px;\n}\n\n#powerTip.se:after, #powerTip.se:before {\n\tleft: 14px;\n}\n\n#powerTip.e:after, #powerTip.e:before {\n\tleft: 100%;\n}\n#powerTip.e:after {\n\tborder-left-color: #ffffff;\n\tborder-width: 10px;\n\ttop: 50%;\n\tmargin-top: -10px;\n}\n#powerTip.e:before {\n\tborder-left-color: #808080;\n\tborder-width: 11px;\n\ttop: 50%;\n\tmargin-top: -11px;\n}\n\n#powerTip.w:after, #powerTip.w:before {\n\tright: 100%;\n}\n#powerTip.w:after {\n\tborder-right-color: #ffffff;\n\tborder-width: 10px;\n\ttop: 50%;\n\tmargin-top: -10px;\n}\n#powerTip.w:before {\n\tborder-right-color: #808080;\n\tborder-width: 11px;\n\ttop: 50%;\n\tmargin-top: -11px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/dynsections.js",
    "content": "function toggleVisibility(linkObj)\n{\n var base = $(linkObj).attr('id');\n var summary = $('#'+base+'-summary');\n var content = $('#'+base+'-content');\n var trigger = $('#'+base+'-trigger');\n var src=$(trigger).attr('src');\n if (content.is(':visible')===true) {\n   content.hide();\n   summary.show();\n   $(linkObj).addClass('closed').removeClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');\n } else {\n   content.show();\n   summary.hide();\n   $(linkObj).removeClass('closed').addClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');\n } \n return false;\n}\n\nfunction updateStripes()\n{\n  $('table.directory tr').\n       removeClass('even').filter(':visible:even').addClass('even');\n}\nfunction toggleLevel(level)\n{\n  $('table.directory tr').each(function(){ \n    var l = this.id.split('_').length-1;\n    var i = $('#img'+this.id.substring(3));\n    var a = $('#arr'+this.id.substring(3));\n    if (l<level+1) {\n      i.attr('src','ftv2folderopen.png');\n      a.attr('src','ftv2mnode.png');\n      $(this).show();\n    } else if (l==level+1) {\n      i.attr('src','ftv2folderclosed.png');\n      a.attr('src','ftv2pnode.png');\n      $(this).show();\n    } else {\n      $(this).hide();\n    }\n  });\n  updateStripes();\n}\n\nfunction toggleFolder(id)\n{\n  //The clicked row\n  var currentRow = $('#row_'+id);\n  var currentRowImages = currentRow.find(\"img\");\n\n  //All rows after the clicked row\n  var rows = currentRow.nextAll(\"tr\");\n\n  //Only match elements AFTER this one (can't hide elements before)\n  var childRows = rows.filter(function() {\n    var re = new RegExp('^row_'+id+'\\\\d+_$', \"i\"); //only one sub\n    return this.id.match(re);\n  });\n\n  //First row is visible we are HIDING\n  if (childRows.filter(':first').is(':visible')===true) {\n    currentRowImages.filter(\"[id^=arr]\").attr('src', 'ftv2pnode.png');\n    currentRowImages.filter(\"[id^=img]\").attr('src', 'ftv2folderclosed.png');\n    rows.filter(\"[id^=row_\"+id+\"]\").hide();\n  } else { //We are SHOWING\n    //All sub images\n    var childImages = childRows.find(\"img\");\n    var childImg = childImages.filter(\"[id^=img]\");\n    var childArr = childImages.filter(\"[id^=arr]\");\n\n    currentRow.find(\"[id^=arr]\").attr('src', 'ftv2mnode.png'); //open row\n    currentRow.find(\"[id^=img]\").attr('src', 'ftv2folderopen.png'); //open row\n    childImg.attr('src','ftv2folderclosed.png'); //children closed\n    childArr.attr('src','ftv2pnode.png'); //children closed\n    childRows.show(); //show all children\n  }\n  updateStripes();\n}\n\n\nfunction toggleInherit(id)\n{\n  var rows = $('tr.inherit.'+id);\n  var img = $('tr.inherit_header.'+id+' img');\n  var src = $(img).attr('src');\n  if (rows.filter(':first').is(':visible')===true) {\n    rows.css('display','none');\n    $(img).attr('src',src.substring(0,src.length-8)+'closed.png');\n  } else {\n    rows.css('display','table-row'); // using show() causes jump in firefox\n    $(img).attr('src',src.substring(0,src.length-10)+'open.png');\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/examples.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/examples.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/examples.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/fast__math__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/fast__math__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/fast__math__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/fast__math__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/fast__math__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/fast__math__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/files.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/files.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/files.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/filtering__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/filtering__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/filtering__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/filtering__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/filtering__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/filtering__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/footer.js",
    "content": "function writeHeader() {\n    document.write('Version 1.10.1');\n};\n\nfunction writeFooter()  {\n    document.write('Generated on Tue Jun 28 2022 11:55:45 for CMSIS-DSP 1.10.1. Copyright &copy; 2022 Arm Limited (or its affiliates). All rights reserved.');\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_b.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_b.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_b.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_d.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_d.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_d.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_e.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_e.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_e.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_f.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_f.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_f.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_g.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_g.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_g.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_i.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_i.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_i.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_k.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_k.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_k.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_l.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_l.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_l.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_m.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_m.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_m.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_n.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_n.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_n.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_o.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_o.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_o.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_p.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_p.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_p.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_r.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_r.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_r.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_s.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_s.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_s.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_t.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_t.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_t.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_v.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_v.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_v.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_b.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_b.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_b.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_d.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_d.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_d.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_e.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_e.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_e.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_f.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_f.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_f.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_g.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_g.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_g.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_i.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_i.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_i.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_k.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_k.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_k.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_l.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_l.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_l.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_m.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_m.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_m.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_n.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_n.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_n.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_o.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_o.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_o.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_p.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_p.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_p.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_r.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_r.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_r.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_s.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_s.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_s.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_t.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_t.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_t.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_v.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_v.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_v.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_w.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_w.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_w.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_vars_y.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_y.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_vars_y.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_w.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_w.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_w.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/functions_y.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_y.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/functions_y.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_a.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_a.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_a.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_b.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_b.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_b.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_d.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_d.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_d.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_defs.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_defs.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_defs.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_e.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_e.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_e.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_enum.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_enum.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_enum.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_eval.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_eval.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_eval.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_f.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_f.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_f.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_a.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_a.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_a.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_b.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_b.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_b.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_d.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_d.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_d.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_e.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_e.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_e.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_f.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_f.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_f.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_g.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_g.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_g.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_i.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_i.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_i.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_j.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_j.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_j.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_k.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_k.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_k.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_l.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_l.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_l.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_m.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_m.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_m.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_n.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_n.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_n.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_o.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_o.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_o.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_p.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_p.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_p.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_q.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_q.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_q.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_r.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_r.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_r.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_s.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_s.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_s.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_t.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_t.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_t.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_v.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_v.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_v.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_w.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_w.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_w.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_func_y.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_y.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_func_y.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_g.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_g.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_g.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_i.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_i.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_i.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_j.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_j.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_j.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_k.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_k.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_k.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_l.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_l.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_l.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_m.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_m.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_m.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_n.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_n.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_n.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_o.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_o.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_o.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_p.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_p.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_p.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_q.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_q.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_q.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_r.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_r.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_r.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_s.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_s.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_s.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_t.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_t.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_t.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_type.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_type.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_type.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_u.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_u.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_u.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_v.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_v.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_v.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_b.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_b.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_b.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_d.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_d.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_d.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_e.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_e.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_e.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_f.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_f.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_f.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_g.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_g.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_g.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_i.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_i.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_i.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_l.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_l.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_l.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_m.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_m.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_m.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_n.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_n.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_n.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_o.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_o.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_o.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_p.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_p.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_p.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_r.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_r.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_r.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_s.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_s.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_s.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_t.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_t.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_t.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_v.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_v.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_v.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_w.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_w.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_w.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_vars_x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_vars_x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_w.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_w.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_w.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/globals_y.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_y.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/globals_y.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__AbsMax.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__AbsMax.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__AbsMax.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__AbsMin.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__AbsMin.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__AbsMin.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__And.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__And.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__And.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicAbs.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicAbs.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicAbs.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicAdd.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicAdd.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicAdd.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicClip.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicClip.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicClip.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicDotProd.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicDotProd.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicDotProd.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicMult.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicMult.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicMult.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicNegate.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicNegate.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicNegate.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicOffset.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicOffset.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicOffset.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicScale.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicScale.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicScale.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicShift.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicShift.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicShift.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BasicSub.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicSub.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BasicSub.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BayesExample.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BayesExample.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BayesExample.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BilinearInterpolate.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BilinearInterpolate.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BilinearInterpolate.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BiquadCascadeDF1.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BiquadCascadeDF1.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BiquadCascadeDF1.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BiquadCascadeDF1__32x64.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BiquadCascadeDF1__32x64.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BiquadCascadeDF1__32x64.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BiquadCascadeDF2T.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BiquadCascadeDF2T.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BiquadCascadeDF2T.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__BoolDist.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BoolDist.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__BoolDist.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__CFFT__CIFFT.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CFFT__CIFFT.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CFFT__CIFFT.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Canberra.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Canberra.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Canberra.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Chebyshev.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Chebyshev.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Chebyshev.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__ClassMarks.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__ClassMarks.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__ClassMarks.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__CmplxByCmplxMult.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CmplxByCmplxMult.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CmplxByCmplxMult.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__CmplxByRealMult.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CmplxByRealMult.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CmplxByRealMult.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__CmplxMatrixMult.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CmplxMatrixMult.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CmplxMatrixMult.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__ComplexFFT.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__ComplexFFT.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__ComplexFFT.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Conv.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Conv.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Conv.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__ConvolutionExample.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__ConvolutionExample.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__ConvolutionExample.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Corr.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Corr.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Corr.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Correlation.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Correlation.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Correlation.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__CosineDist.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CosineDist.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__CosineDist.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__DCT4__IDCT4.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__DCT4__IDCT4.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__DCT4__IDCT4.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__DCT4__IDCT4__Table.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__DCT4__IDCT4__Table.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__DCT4__IDCT4__Table.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__DotproductExample.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__DotproductExample.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__DotproductExample.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Entropy.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Entropy.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Entropy.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Euclidean.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Euclidean.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Euclidean.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__FIR.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__FIRLPF.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIRLPF.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIRLPF.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__FIR__Interpolate.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR__Interpolate.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR__Interpolate.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__FIR__Lattice.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR__Lattice.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR__Lattice.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__FIR__Sparse.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR__Sparse.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR__Sparse.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__FIR__decimate.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR__decimate.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FIR__decimate.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Fill.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Fill.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Fill.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__FloatDist.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FloatDist.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FloatDist.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__FrequencyBin.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FrequencyBin.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__FrequencyBin.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__GEQ5Band.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__GEQ5Band.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__GEQ5Band.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__IIR__Lattice.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__IIR__Lattice.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__IIR__Lattice.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__JensenShannon.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__JensenShannon.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__JensenShannon.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Kullback-Leibler.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Kullback-Leibler.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Kullback-Leibler.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__LD.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LD.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LD.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__LMS.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LMS.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LMS.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__LMS__NORM.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LMS__NORM.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LMS__NORM.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__LinearInterpExample.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LinearInterpExample.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LinearInterpExample.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__LinearInterpolate.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LinearInterpolate.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LinearInterpolate.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__LogSumExp.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LogSumExp.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__LogSumExp.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MFCC.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MFCC.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MFCC.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MSE.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MSE.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MSE.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Manhattan.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Manhattan.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Manhattan.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixAdd.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixAdd.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixAdd.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixChol.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixChol.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixChol.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixComplexTrans.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixComplexTrans.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixComplexTrans.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixExample.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixExample.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixExample.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixInit.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixInit.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixInit.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixInv.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixInv.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixInv.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixMult.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixMult.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixMult.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixScale.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixScale.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixScale.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixSub.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixSub.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixSub.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixTrans.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixTrans.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixTrans.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__MatrixVectMult.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixVectMult.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__MatrixVectMult.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Max.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Max.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Max.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Min.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Min.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Min.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Minkowski.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Minkowski.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Minkowski.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Not.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Not.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Not.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Or.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Or.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Or.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__PID.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__PID.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__PID.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__PartialConv.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__PartialConv.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__PartialConv.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__QuatConjugate.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatConjugate.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatConjugate.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__QuatConv.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatConv.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatConv.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__QuatInverse.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatInverse.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatInverse.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__QuatNorm.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatNorm.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatNorm.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__QuatNormalized.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatNormalized.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatNormalized.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__QuatProd.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatProd.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatProd.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__QuatProdSingle.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatProdSingle.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatProdSingle.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__QuatProdVect.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatProdVect.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatProdVect.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__QuatRot.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatRot.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__QuatRot.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__RMS.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__RMS.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__RMS.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__RealFFT.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__RealFFT.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__RealFFT.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__RealFFT__Table.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__RealFFT__Table.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__RealFFT__Table.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__RotQuat.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__RotQuat.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__RotQuat.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__SQRT.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SQRT.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SQRT.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__STD.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__STD.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__STD.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__SVMExample.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SVMExample.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SVMExample.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__SignalConvergence.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SignalConvergence.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SignalConvergence.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__SinCos.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SinCos.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SinCos.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__SinCosExample.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SinCosExample.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SinCosExample.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Sorting.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Sorting.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Sorting.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__SplineInterpolate.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SplineInterpolate.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__SplineInterpolate.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__VarianceExample.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__VarianceExample.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__VarianceExample.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__Xor.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Xor.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__Xor.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__atan2.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__atan2.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__atan2.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__barycenter.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__barycenter.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__barycenter.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__braycurtis.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__braycurtis.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__braycurtis.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__clarke.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__clarke.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__clarke.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__cmplx__conj.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cmplx__conj.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cmplx__conj.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__cmplx__dot__prod.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cmplx__dot__prod.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cmplx__dot__prod.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__cmplx__mag.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cmplx__mag.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cmplx__mag.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__cmplx__mag__squared.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cmplx__mag__squared.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cmplx__mag__squared.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__copy.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__copy.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__copy.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__cos.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cos.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__cos.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__divide.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__divide.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__divide.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__f16__to__x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__f16__to__x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__f16__to__x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__float__to__x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__float__to__x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__float__to__x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupBayes.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupBayes.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupBayes.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupCmplxMath.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupCmplxMath.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupCmplxMath.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupController.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupController.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupController.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupDistance.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupDistance.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupDistance.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupExamples.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupExamples.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupExamples.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupFastMath.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupFastMath.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupFastMath.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupFilters.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupFilters.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupFilters.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupInterpolation.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupInterpolation.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupInterpolation.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupMath.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupMath.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupMath.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupMatrix.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupMatrix.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupMatrix.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupQuaternionMath.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupQuaternionMath.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupQuaternionMath.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupSVM.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupSVM.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupSVM.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupStats.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupStats.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupStats.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupSupport.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupSupport.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupSupport.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__groupTransforms.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupTransforms.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__groupTransforms.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__inv__clarke.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__inv__clarke.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__inv__clarke.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__inv__park.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__inv__park.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__inv__park.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__linearsvm.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__linearsvm.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__linearsvm.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__mean.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__mean.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__mean.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__park.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__park.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__park.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__polysvm.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__polysvm.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__polysvm.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__power.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__power.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__power.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__q15__to__x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__q15__to__x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__q15__to__x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__q31__to__x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__q31__to__x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__q31__to__x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__q7__to__x.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__q7__to__x.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__q7__to__x.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__rbfsvm.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__rbfsvm.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__rbfsvm.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__sigmoidsvm.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__sigmoidsvm.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__sigmoidsvm.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__sin.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__sin.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__sin.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__typecast.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__typecast.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__typecast.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__variance.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__variance.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/group__variance.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/group__vlog.html",
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    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<meta http-equiv=\"Content-Type\" content=\"text/xhtml;charset=UTF-8\"/>\n<meta http-equiv=\"X-UA-Compatible\" content=\"IE=9\"/>\n<title>CMSIS DSP Software Library</title>\n<title>CMSIS-DSP: CMSIS DSP Software Library</title>\n<link href=\"tabs.css\" rel=\"stylesheet\" type=\"text/css\"/>\n<link href=\"cmsis.css\" rel=\"stylesheet\" type=\"text/css\" />\n<script type=\"text/javascript\" src=\"jquery.js\"></script>\n<script type=\"text/javascript\" src=\"dynsections.js\"></script>\n<script type=\"text/javascript\" src=\"printComponentTabs.js\"></script>\n<script type=\"text/javascript\" src=\"footer.js\"></script>\n<link href=\"navtree.css\" rel=\"stylesheet\" type=\"text/css\"/>\n<script type=\"text/javascript\" src=\"resize.js\"></script>\n<script type=\"text/javascript\" src=\"navtree.js\"></script>\n<script type=\"text/javascript\">\n  $(document).ready(initResizable);\n  $(window).load(resizeHeight);\n</script>\n<link href=\"search/search.css\" rel=\"stylesheet\" type=\"text/css\"/>\n<script type=\"text/javascript\" src=\"search/search.js\"></script>\n<script type=\"text/javascript\">\n  $(document).ready(function() { searchBox.OnSelectItem(0); });\n</script>\n</head>\n<body>\n<div id=\"top\"><!-- do not remove this div, it is closed by doxygen! -->\n<div id=\"titlearea\">\n<table cellspacing=\"0\" cellpadding=\"0\">\n <tbody>\n <tr style=\"height: 46px;\">\n  <td id=\"projectlogo\"><img alt=\"Logo\" src=\"CMSIS_Logo_Final.png\"/></td>\n  <td style=\"padding-left: 0.5em;\">\n   <div id=\"projectname\">CMSIS-DSP\n   &#160;<span id=\"projectnumber\"><script type=\"text/javascript\">\n     <!--\n     writeHeader.call(this);\n     //-->\n    </script> \n   </span>\n   </div>\n   <div id=\"projectbrief\">CMSIS DSP Software Library</div>\n  </td>\n </tr>\n </tbody>\n</table>\n</div>\n<!-- end header part -->\n<div id=\"CMSISnav\" class=\"tabs1\">\n    <ul class=\"tablist\">\n      <script type=\"text/javascript\">\n\t\t<!--\n\t\twriteComponentTabs.call(this);\n\t\t//-->\n      </script>\n\t  </ul>\n</div>\n<!-- Generated by Doxygen 1.8.6 -->\n<script type=\"text/javascript\">\nvar searchBox = new SearchBox(\"searchBox\", \"search\",false,'Search');\n</script>\n  <div id=\"navrow1\" class=\"tabs\">\n    <ul class=\"tablist\">\n      <li class=\"current\"><a href=\"index.html\"><span>Main&#160;Page</span></a></li>\n      <li><a href=\"pages.html\"><span>Usage&#160;and&#160;Description</span></a></li>\n      <li>\n        <div id=\"MSearchBox\" class=\"MSearchBoxInactive\">\n        <span class=\"left\">\n          <img id=\"MSearchSelect\" src=\"search/mag_sel.png\"\n               onmouseover=\"return searchBox.OnSearchSelectShow()\"\n               onmouseout=\"return searchBox.OnSearchSelectHide()\"\n               alt=\"\"/>\n          <input type=\"text\" id=\"MSearchField\" value=\"Search\" accesskey=\"S\"\n               onfocus=\"searchBox.OnSearchFieldFocus(true)\" \n               onblur=\"searchBox.OnSearchFieldFocus(false)\" \n               onkeyup=\"searchBox.OnSearchFieldChange(event)\"/>\n          </span><span class=\"right\">\n            <a id=\"MSearchClose\" href=\"javascript:searchBox.CloseResultsWindow()\"><img id=\"MSearchCloseImg\" border=\"0\" src=\"search/close.png\" alt=\"\"/></a>\n          </span>\n        </div>\n      </li>\n    </ul>\n  </div>\n</div><!-- top -->\n<div id=\"side-nav\" class=\"ui-resizable side-nav-resizable\">\n  <div id=\"nav-tree\">\n    <div id=\"nav-tree-contents\">\n      <div id=\"nav-sync\" class=\"sync\"></div>\n    </div>\n  </div>\n  <div id=\"splitbar\" style=\"-moz-user-select:none;\" \n       class=\"ui-resizable-handle\">\n  </div>\n</div>\n<script type=\"text/javascript\">\n$(document).ready(function(){initNavTree('index.html','');});\n</script>\n<div id=\"doc-content\">\n<!-- window showing the filter options -->\n<div id=\"MSearchSelectWindow\"\n     onmouseover=\"return searchBox.OnSearchSelectShow()\"\n     onmouseout=\"return searchBox.OnSearchSelectHide()\"\n     onkeydown=\"return searchBox.OnSearchSelectKey(event)\">\n<a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(0)\"><span class=\"SelectionMark\">&#160;</span>All</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(1)\"><span class=\"SelectionMark\">&#160;</span>Pages</a></div>\n\n<!-- iframe showing the search results (closed by default) -->\n<div id=\"MSearchResultsWindow\">\n<iframe src=\"javascript:void(0)\" frameborder=\"0\" \n        name=\"MSearchResults\" id=\"MSearchResults\">\n</iframe>\n</div>\n\n<div class=\"header\">\n  <div class=\"headertitle\">\n<div class=\"title\">CMSIS DSP Software Library </div>  </div>\n</div><!--header-->\n<div class=\"contents\">\n<div class=\"textblock\"><p><b>CMSIS-DSP</b> is now in its GitHub project at <a href=\"https://github.com/ARM-software/CMSIS-DSP\" target=\"_blank\">ARM-software/CMSIS-DSP</a>.</p>\n\nContent of this documentation is now <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/index.html\" target=\"_blank\"><b>provided here</b></a> and individual pages are redirected to the corresponding pages in CMSIS-DSP documentation.\n\n</div></div>\n</body>\n</html>\n"
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src=\"navtree.js\"></script>\n<script type=\"text/javascript\">\n  $(document).ready(initResizable);\n  $(window).load(resizeHeight);\n</script>\n<link href=\"search/search.css\" rel=\"stylesheet\" type=\"text/css\"/>\n<script type=\"text/javascript\" src=\"search/search.js\"></script>\n<script type=\"text/javascript\">\n  $(document).ready(function() { searchBox.OnSelectItem(0); });\n</script>\n</head>\n<body>\n<div id=\"top\"><!-- do not remove this div, it is closed by doxygen! -->\n<div id=\"titlearea\">\n<table cellspacing=\"0\" cellpadding=\"0\">\n <tbody>\n <tr style=\"height: 46px;\">\n  <td id=\"projectlogo\"><img alt=\"Logo\" src=\"CMSIS_Logo_Final.png\"/></td>\n  <td style=\"padding-left: 0.5em;\">\n   <div id=\"projectname\">CMSIS-DSP\n   &#160;<span id=\"projectnumber\"><script type=\"text/javascript\">\n     <!--\n     writeHeader.call(this);\n     //-->\n    </script> \n   </span>\n   </div>\n   <div id=\"projectbrief\">CMSIS DSP Software Library</div>\n  </td>\n </tr>\n </tbody>\n</table>\n</div>\n<!-- end header part -->\n<!-- Generated by Doxygen 1.8.6 -->\n<script type=\"text/javascript\">\nvar searchBox = new SearchBox(\"searchBox\", \"search\",false,'Search');\n</script>\n  <div id=\"navrow1\" class=\"tabs\">\n    <ul class=\"tablist\">\n      <li class=\"current\"><a href=\"index.html\"><span>Main&#160;Page</span></a></li>\n      <li><a href=\"pages.html\"><span>Usage&#160;and&#160;Description</span></a></li>\n      <li><a href=\"modules.html\"><span>Reference</span></a></li>\n      <li>\n        <div id=\"MSearchBox\" class=\"MSearchBoxInactive\">\n        <span class=\"left\">\n          <img id=\"MSearchSelect\" src=\"search/mag_sel.png\"\n               onmouseover=\"return searchBox.OnSearchSelectShow()\"\n               onmouseout=\"return searchBox.OnSearchSelectHide()\"\n               alt=\"\"/>\n          <input type=\"text\" id=\"MSearchField\" value=\"Search\" accesskey=\"S\"\n               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id=\"MSearchSelectWindow\"\n     onmouseover=\"return searchBox.OnSearchSelectShow()\"\n     onmouseout=\"return searchBox.OnSearchSelectHide()\"\n     onkeydown=\"return searchBox.OnSearchSelectKey(event)\">\n<a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(0)\"><span class=\"SelectionMark\">&#160;</span>All</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(1)\"><span class=\"SelectionMark\">&#160;</span>Data Structures</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(2)\"><span class=\"SelectionMark\">&#160;</span>Namespaces</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(3)\"><span class=\"SelectionMark\">&#160;</span>Files</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(4)\"><span class=\"SelectionMark\">&#160;</span>Functions</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(5)\"><span class=\"SelectionMark\">&#160;</span>Variables</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(6)\"><span class=\"SelectionMark\">&#160;</span>Typedefs</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(7)\"><span class=\"SelectionMark\">&#160;</span>Enumerations</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(8)\"><span class=\"SelectionMark\">&#160;</span>Enumerator</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(9)\"><span class=\"SelectionMark\">&#160;</span>Macros</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(10)\"><span class=\"SelectionMark\">&#160;</span>Groups</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(11)\"><span class=\"SelectionMark\">&#160;</span>Pages</a></div>\n\n<!-- iframe showing the search results (closed by default) -->\n<div id=\"MSearchResultsWindow\">\n<iframe src=\"javascript:void(0)\" frameborder=\"0\" \n        name=\"MSearchResults\" id=\"MSearchResults\">\n</iframe>\n</div>\n\n<div class=\"header\">\n  <div class=\"headertitle\">\n<div class=\"title\">CMSIS DSP Software Library </div>  </div>\n</div><!--header-->\n<div class=\"contents\">\n<div class=\"textblock\"><h1><a class=\"anchor\" id=\"intro\"></a>\nIntroduction</h1>\n<p>This user manual describes the CMSIS DSP software library, a suite of common signal processing functions for use on Cortex-M and Cortex-A processor based devices.</p>\n<p>The library is divided into a number of functions each covering a specific category:</p>\n<ul>\n<li>Basic math functions</li>\n<li>Fast math functions</li>\n<li>Complex math functions</li>\n<li>Filtering functions</li>\n<li>Matrix functions</li>\n<li>Transform functions</li>\n<li>Motor control functions</li>\n<li>Statistical functions</li>\n<li>Support functions</li>\n<li>Interpolation functions</li>\n<li>Support Vector Machine functions (SVM)</li>\n<li>Bayes classifier functions</li>\n<li>Distance functions</li>\n<li>Quaternion functions</li>\n</ul>\n<p>The library has generally separate functions for operating on 8-bit integers, 16-bit integers, 32-bit integer and 32-bit floating-point values.</p>\n<p>The library is providing vectorized versions of most algorthms for Helium and of most f32 algorithms for Neon.</p>\n<p>When using a vectorized version, provide a little bit of padding after the end of a buffer (3 words) because the vectorized code may read a little bit after the end of a buffer. You don't have to modify your buffers but just ensure that the end of buffer + padding is not outside of a memory region.</p>\n<h1><a class=\"anchor\" id=\"using\"></a>\nUsing the Library</h1>\n<p>The library is released in source form. It is strongly advised to compile the library using -Ofast to have the best performances.</p>\n<p>The library functions are declared in the public file <code><a class=\"el\" href=\"arm__math_8h.html\">arm_math.h</a></code> which is placed in the <code>Include</code> folder. Simply include this file. If you don't want to include everything, you can also rely on headers in Include/dsp folder and use only what you need.</p>\n<h1><a class=\"anchor\" id=\"example\"></a>\nExamples</h1>\n<p>The library ships with a number of examples which demonstrate how to use the library functions.</p>\n<h1><a class=\"anchor\" id=\"toolchain\"></a>\nToolchain Support</h1>\n<p>The library is now tested on Fast Models building with cmake. Core M0, M4, M7, M33, M55, A32 are tested.</p>\n<h1><a class=\"anchor\" id=\"preprocessor\"></a>\nPreprocessor Macros</h1>\n<p>Each library project have different preprocessor macros.</p>\n<ul>\n<li>ARM_MATH_BIG_ENDIAN:</li>\n</ul>\n<p>Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.</p>\n<ul>\n<li>ARM_MATH_MATRIX_CHECK:</li>\n</ul>\n<p>Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices</p>\n<ul>\n<li>ARM_MATH_ROUNDING:</li>\n</ul>\n<p>Define macro ARM_MATH_ROUNDING for rounding on support functions</p>\n<ul>\n<li>ARM_MATH_LOOPUNROLL:</li>\n</ul>\n<p>Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions</p>\n<ul>\n<li>ARM_MATH_NEON:</li>\n</ul>\n<p>Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. It is not enabled by default when Neon is available because performances are dependent on the compiler and target architecture.</p>\n<ul>\n<li>ARM_MATH_NEON_EXPERIMENTAL:</li>\n</ul>\n<p>Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of of some DSP functions. Experimental Neon versions currently do not have better performances than the scalar versions.</p>\n<ul>\n<li>ARM_MATH_HELIUM:</li>\n</ul>\n<p>It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16.</p>\n<ul>\n<li>ARM_MATH_HELIUM_EXPERIMENTAL:</li>\n</ul>\n<p>Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined. Enable some vector versions which may have worse performance than scalar depending on the core / compiler configuration.</p>\n<ul>\n<li>ARM_MATH_MVEF:</li>\n</ul>\n<p>Select Helium versions of the f32 algorithms. It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI.</p>\n<ul>\n<li>ARM_MATH_MVEI:</li>\n</ul>\n<p>Select Helium versions of the int and fixed point algorithms.</p>\n<ul>\n<li>ARM_MATH_MVE_FLOAT16:</li>\n</ul>\n<p>MVE Float16 implementations of some algorithms (Requires MVE extension).</p>\n<ul>\n<li>DISABLEFLOAT16:</li>\n</ul>\n<p>Disable float16 algorithms when __fp16 is not supported for a specific compiler / core configuration. This is only valid for scalar. When vector architecture is supporting f16 then it can't be disabled.</p>\n<ul>\n<li>ARM_MATH_AUTOVECTORIZE:</li>\n</ul>\n<p>With Helium or Neon, disable the use of vectorized code with C intrinsics and use pure C instead. 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this.bind((a.support.selectstart?\"selectstart\":\"mousedown\")+\".ui-disableSelection\",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(\".ui-disableSelection\")}});a.each([\"Width\",\"Height\"],function(g,e){var f=e===\"Width\"?[\"Left\",\"Right\"]:[\"Top\",\"Bottom\"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,\"padding\"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,\"border\"+this+\"Width\",true))||0}if(n){l-=parseFloat(a.curCSS(m,\"margin\"+this,true))||0}});return l}a.fn[\"inner\"+e]=function(i){if(i===d){return k[\"inner\"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+\"px\")})};a.fn[\"outer\"+e]=function(i,l){if(typeof i!==\"number\"){return k[\"outer\"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+\"px\")})}});function c(g,e){var j=g.nodeName.toLowerCase();if(\"area\"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!==\"map\"){return false}f=a(\"img[usemap=#\"+h+\"]\")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:\"a\"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,\"visibility\")===\"hidden\"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[\":\"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,\"tabindex\")))},tabbable:function(g){var e=a.attr(g,\"tabindex\"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement(\"div\"));f.offsetHeight;a.extend(f.style,{minHeight:\"100px\",height:\"auto\",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart=\"onselectstart\" in f;e.removeChild(f).style.display=\"none\"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h<j.length;h++){if(e.options[j[h][0]]){j[h][1].apply(e.element,f)}}}},contains:function(f,e){return document.compareDocumentPosition?f.compareDocumentPosition(e)&16:f!==e&&f.contains(e)},hasScroll:function(h,f){if(a(h).css(\"overflow\")===\"hidden\"){return false}var e=(f&&f===\"left\")?\"scrollLeft\":\"scrollTop\",g=false;if(h[e]>0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*!\n * jQuery UI Widget 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Widget\n */\n(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler(\"remove\")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b(\"*\",this).add([this]).each(function(){try{b(this).triggerHandler(\"remove\")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(\".\")[0],j;f=f.split(\".\")[1];j=g+\"-\"+f;if(!e){e=h;h=b.Widget}b.expr[\":\"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i===\"string\",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)===\"_\"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:\"widget\",widgetEventPrefix:\"\",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind(\"remove.\"+this.widgetName,function(){e.destroy()});this._create();this._trigger(\"create\");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind(\".\"+this.widgetName).removeData(this.widgetName);this.widget().unbind(\".\"+this.widgetName).removeAttr(\"aria-disabled\").removeClass(this.widgetBaseClass+\"-disabled ui-state-disabled\")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f===\"string\"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e===\"disabled\"){this.widget()[f?\"addClass\":\"removeClass\"](this.widgetBaseClass+\"-disabled ui-state-disabled\").attr(\"aria-disabled\",f)}return this},enable:function(){return this._setOption(\"disabled\",false)},disable:function(){return this._setOption(\"disabled\",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!\n * jQuery UI Mouse 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Mouse\n *\n * Depends:\n *\tjquery.ui.widget.js\n */\n(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget(\"ui.mouse\",{options:{cancel:\":input,option\",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind(\"mousedown.\"+this.widgetName,function(e){return d._mouseDown(e)}).bind(\"click.\"+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+\".preventClickEvent\")){b.removeData(e.target,d.widgetName+\".preventClickEvent\");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind(\".\"+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel==\"string\"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+\".preventClickEvent\")){b.removeData(f.target,this.widgetName+\".preventClickEvent\")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).bind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).unbind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+\".preventClickEvent\",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget(\"ui.resizable\",c.ui.mouse,{widgetEventPrefix:\"resize\",options:{alsoResize:false,animate:false,animateDuration:\"slow\",animateEasing:\"swing\",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:\"e,s,se\",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass(\"ui-resizable\");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||\"ui-resizable-helper\":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class=\"ui-wrapper\" style=\"overflow: hidden;\"></div>').css({position:this.element.css(\"position\"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css(\"top\"),left:this.element.css(\"left\")}));this.element=this.element.parent().data(\"resizable\",this.element.data(\"resizable\"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css(\"marginLeft\"),marginTop:this.originalElement.css(\"marginTop\"),marginRight:this.originalElement.css(\"marginRight\"),marginBottom:this.originalElement.css(\"marginBottom\")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css(\"resize\");this.originalElement.css(\"resize\",\"none\");this._proportionallyResizeElements.push(this.originalElement.css({position:\"static\",zoom:1,display:\"block\"}));this.originalElement.css({margin:this.originalElement.css(\"margin\")});this._proportionallyResize()}this.handles=k.handles||(!c(\".ui-resizable-handle\",this.element).length?\"e,s,se\":{n:\".ui-resizable-n\",e:\".ui-resizable-e\",s:\".ui-resizable-s\",w:\".ui-resizable-w\",se:\".ui-resizable-se\",sw:\".ui-resizable-sw\",ne:\".ui-resizable-ne\",nw:\".ui-resizable-nw\"});if(this.handles.constructor==String){if(this.handles==\"all\"){this.handles=\"n,e,s,w,se,sw,ne,nw\"}var l=this.handles.split(\",\");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e=\"ui-resizable-\"+j;var h=c('<div class=\"ui-resizable-handle '+e+'\"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if(\"se\"==j){h.addClass(\"ui-icon ui-icon-gripsmall-diagonal-se\")}this.handles[j]=\".ui-resizable-\"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=[\"padding\",/ne|nw|n/.test(n)?\"Top\":/se|sw|s/.test(n)?\"Bottom\":/^e$/.test(n)?\"Right\":\"Left\"].join(\"\");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(\".ui-resizable-handle\",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:\"se\"}});if(k.autoHide){this._handles.hide();c(this.element).addClass(\"ui-resizable-autohide\").hover(function(){if(k.disabled){return}c(this).removeClass(\"ui-resizable-autohide\");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass(\"ui-resizable-autohide\");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass(\"ui-resizable ui-resizable-disabled ui-resizable-resizing\").removeData(\"resizable\").unbind(\".resizable\").find(\".ui-resizable-handle\").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css(\"position\"),width:f.outerWidth(),height:f.outerHeight(),top:f.css(\"top\"),left:f.css(\"left\")})).remove()}this.originalElement.css(\"resize\",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(\".ui-draggable\")||(/absolute/).test(e.css(\"position\"))){e.css({position:\"absolute\",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css(\"left\")),h=b(this.helper.css(\"top\"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio==\"number\")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(\".ui-resizable-\"+this.axis).css(\"cursor\");c(\"body\").css(\"cursor\",i==\"auto\"?this.axis+\"-resize\":i);e.addClass(\"ui-resizable-resizing\");this._propagate(\"start\",g);return true},_mouseDrag:function(e){var h=this.helper,g=this.options,m={},q=this,j=this.originalMousePosition,n=this.axis;var r=(e.pageX-j.left)||0,p=(e.pageY-j.top)||0;var i=this._change[n];if(!i){return false}var l=i.apply(this,[e,r,p]),k=c.browser.msie&&c.browser.version<7,f=this.sizeDiff;this._updateVirtualBoundaries(e.shiftKey);if(this._aspectRatio||e.shiftKey){l=this._updateRatio(l,e)}l=this._respectSize(l,e);this._propagate(\"resize\",e);h.css({top:this.position.top+\"px\",left:this.position.left+\"px\",width:this.size.width+\"px\",height:this.size.height+\"px\"});if(!this._helper&&this._proportionallyResizeElements.length){this._proportionallyResize()}this._updateCache(l);this._trigger(\"resize\",e,this.ui());return false},_mouseStop:function(h){this.resizing=false;var i=this.options,m=this;if(this._helper){var g=this._proportionallyResizeElements,e=g.length&&(/textarea/i).test(g[0].nodeName),f=e&&c.ui.hasScroll(g[0],\"left\")?0:m.sizeDiff.height,k=e?0:m.sizeDiff.width;var n={width:(m.helper.width()-k),height:(m.helper.height()-f)},j=(parseInt(m.element.css(\"left\"),10)+(m.position.left-m.originalPosition.left))||null,l=(parseInt(m.element.css(\"top\"),10)+(m.position.top-m.originalPosition.top))||null;if(!i.animate){this.element.css(c.extend(n,{top:l,left:j}))}m.helper.height(m.size.height);m.helper.width(m.size.width);if(this._helper&&!i.animate){this._proportionallyResize()}}c(\"body\").css(\"cursor\",\"auto\");this.element.removeClass(\"ui-resizable-resizing\");this._propagate(\"stop\",h);if(this._helper){this.helper.remove()}return false},_updateVirtualBoundaries:function(g){var j=this.options,i,h,f,k,e;e={minWidth:a(j.minWidth)?j.minWidth:0,maxWidth:a(j.maxWidth)?j.maxWidth:Infinity,minHeight:a(j.minHeight)?j.minHeight:0,maxHeight:a(j.maxHeight)?j.maxHeight:Infinity};if(this._aspectRatio||g){i=e.minHeight*this.aspectRatio;f=e.minWidth/this.aspectRatio;h=e.maxHeight*this.aspectRatio;k=e.maxWidth/this.aspectRatio;if(i>e.minWidth){e.minWidth=i}if(f>e.minHeight){e.minHeight=f}if(h<e.maxWidth){e.maxWidth=h}if(k<e.maxHeight){e.maxHeight=k}}this._vBoundaries=e},_updateCache:function(e){var f=this.options;this.offset=this.helper.offset();if(a(e.left)){this.position.left=e.left}if(a(e.top)){this.position.top=e.top}if(a(e.height)){this.size.height=e.height}if(a(e.width)){this.size.width=e.width}},_updateRatio:function(h,g){var i=this.options,j=this.position,f=this.size,e=this.axis;if(a(h.height)){h.width=(h.height*this.aspectRatio)}else{if(a(h.width)){h.height=(h.width/this.aspectRatio)}}if(e==\"sw\"){h.left=j.left+(f.width-h.width);h.top=null}if(e==\"nw\"){h.top=j.top+(f.height-h.height);h.left=j.left+(f.width-h.width)}return h},_respectSize:function(l,g){var j=this.helper,i=this._vBoundaries,r=this._aspectRatio||g.shiftKey,q=this.axis,t=a(l.width)&&i.maxWidth&&(i.maxWidth<l.width),m=a(l.height)&&i.maxHeight&&(i.maxHeight<l.height),h=a(l.width)&&i.minWidth&&(i.minWidth>l.width),s=a(l.height)&&i.minHeight&&(i.minHeight>l.height);if(h){l.width=i.minWidth}if(s){l.height=i.minHeight}if(t){l.width=i.maxWidth}if(m){l.height=i.maxHeight}var f=this.originalPosition.left+this.originalSize.width,p=this.position.top+this.size.height;var k=/sw|nw|w/.test(q),e=/nw|ne|n/.test(q);if(h&&k){l.left=f-i.minWidth}if(t&&k){l.left=f-i.maxWidth}if(s&&e){l.top=p-i.minHeight}if(m&&e){l.top=p-i.maxHeight}var n=!l.width&&!l.height;if(n&&!l.left&&l.top){l.top=null}else{if(n&&!l.top&&l.left){l.left=null}}return l},_proportionallyResize:function(){var k=this.options;if(!this._proportionallyResizeElements.length){return}var g=this.helper||this.element;for(var f=0;f<this._proportionallyResizeElements.length;f++){var h=this._proportionallyResizeElements[f];if(!this.borderDif){var e=[h.css(\"borderTopWidth\"),h.css(\"borderRightWidth\"),h.css(\"borderBottomWidth\"),h.css(\"borderLeftWidth\")],j=[h.css(\"paddingTop\"),h.css(\"paddingRight\"),h.css(\"paddingBottom\"),h.css(\"paddingLeft\")];this.borderDif=c.map(e,function(l,n){var m=parseInt(l,10)||0,o=parseInt(j[n],10)||0;return m+o})}if(c.browser.msie&&!(!(c(g).is(\":hidden\")||c(g).parents(\":hidden\").length))){continue}h.css({height:(g.height()-this.borderDif[0]-this.borderDif[2])||0,width:(g.width()-this.borderDif[1]-this.borderDif[3])||0})}},_renderProxy:function(){var f=this.element,i=this.options;this.elementOffset=f.offset();if(this._helper){this.helper=this.helper||c('<div style=\"overflow:hidden;\"></div>');var e=c.browser.msie&&c.browser.version<7,g=(e?1:0),h=(e?2:-1);this.helper.addClass(this._helper).css({width:this.element.outerWidth()+h,height:this.element.outerHeight()+h,position:\"absolute\",left:this.elementOffset.left-g+\"px\",top:this.elementOffset.top-g+\"px\",zIndex:++i.zIndex});this.helper.appendTo(\"body\").disableSelection()}else{this.helper=this.element}},_change:{e:function(g,f,e){return{width:this.originalSize.width+f}},w:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{left:i.left+f,width:g.width-f}},n:function(h,f,e){var j=this.options,g=this.originalSize,i=this.originalPosition;return{top:i.top+e,height:g.height-e}},s:function(g,f,e){return{height:this.originalSize.height+e}},se:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},sw:function(g,f,e){return c.extend(this._change.s.apply(this,arguments),this._change.w.apply(this,[g,f,e]))},ne:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.e.apply(this,[g,f,e]))},nw:function(g,f,e){return c.extend(this._change.n.apply(this,arguments),this._change.w.apply(this,[g,f,e]))}},_propagate:function(f,e){c.ui.plugin.call(this,f,[e,this.ui()]);(f!=\"resize\"&&this._trigger(f,e,this.ui()))},plugins:{},ui:function(){return{originalElement:this.originalElement,element:this.element,helper:this.helper,position:this.position,size:this.size,originalSize:this.originalSize,originalPosition:this.originalPosition}}});c.extend(c.ui.resizable,{version:\"1.8.18\"});c.ui.plugin.add(\"resizable\",\"alsoResize\",{start:function(f,g){var e=c(this).data(\"resizable\"),i=e.options;var h=function(j){c(j).each(function(){var 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  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/matrix__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/matrix__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/matrix__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/matrix__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/matrix__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/matrix__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/matrix__utils_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/matrix__utils_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/matrix__utils_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/modules.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/modules.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/modules.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/namespacemembers.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/namespacemembers.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/namespacemembers.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/namespacemembers_vars.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/namespacemembers_vars.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/namespacemembers_vars.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/namespaces.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/namespaces.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/namespaces.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/namespacetrain.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/namespacetrain.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/namespacetrain.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/navtree.css",
    "content": "#nav-tree .children_ul {\n  margin:0;\n  padding:4px;\n}\n\n#nav-tree ul {\n  list-style:none outside none;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree li {\n  white-space:nowrap;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .plus {\n  margin:0px;\n}\n\n#nav-tree .selected {\n  background-image: url('tab_a.png');\n  background-repeat:repeat-x;\n  color: #fff;\n  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n\n#nav-tree img {\n  margin:0px;\n  padding:0px;\n  border:0px;\n  vertical-align: middle;\n}\n\n#nav-tree a {\n  text-decoration:none;\n  padding:0px;\n  margin:0px;\n  outline:none;\n}\n\n#nav-tree .label {\n  margin:0px;\n  padding:0px;\n  font: 12px 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;\n}\n\n#nav-tree .label a {\n  padding:2px;\n}\n\n#nav-tree .selected a {\n  text-decoration:none;\n  color:#fff;\n}\n\n#nav-tree .children_ul {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .item {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree {\n  padding: 0px 0px;\n  background-color: #FAFAFF; \n  font-size:14px;\n  overflow:auto;\n}\n\n#doc-content {\n  overflow:auto;\n  display:block;\n  padding:0px;\n  margin:0px;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#side-nav {\n  padding:0 6px 0 0;\n  margin: 0px;\n  display:block;\n  position: absolute;\n  left: 0px;\n  width: 250px;\n}\n\n.ui-resizable .ui-resizable-handle {\n  display:block;\n}\n\n.ui-resizable-e {\n  background:url(\"ftv2splitbar.png\") repeat scroll right center transparent;\n  cursor:e-resize;\n  height:100%;\n  right:0;\n  top:0;\n  width:6px;\n}\n\n.ui-resizable-handle {\n  display:none;\n  font-size:0.1px;\n  position:absolute;\n  z-index:1;\n}\n\n#nav-tree-contents {\n  margin: 6px 0px 0px 0px;\n}\n\n#nav-tree {\n  background-image:url('nav_h.png');\n  background-repeat:repeat-x;\n  background-color: #F9FAFC;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#nav-sync {\n  position:absolute;\n  top:5px;\n  right:24px;\n  z-index:0;\n}\n\n#nav-sync img {\n  opacity:0.3;\n}\n\n#nav-sync img:hover {\n  opacity:0.9;\n}\n\n@media print\n{\n  #nav-tree { display: none; }\n  div.ui-resizable-handle { display: none; position: relative; }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/navtree.js",
    "content": "var NAVTREE =\n[\n  [ \"CMSIS-DSP\", \"index.html\"]\n\n];\n\nvar NAVTREEINDEX =\n[\n\"index.html\"\n];\n\nvar SYNCONMSG = 'click to disable panel synchronisation';\nvar SYNCOFFMSG = 'click to enable panel synchronisation';\nvar SYNCONMSG = 'click to disable panel synchronisation';\nvar SYNCOFFMSG = 'click to enable panel synchronisation';\nvar navTreeSubIndices = new Array();\n\nfunction getData(varName)\n{\n  var i = varName.lastIndexOf('/');\n  var n = i>=0 ? varName.substring(i+1) : varName;\n  return eval(n.replace(/\\-/g,'_'));\n}\n\nfunction stripPath(uri)\n{\n  return uri.substring(uri.lastIndexOf('/')+1);\n}\n\nfunction stripPath2(uri)\n{\n  var i = uri.lastIndexOf('/');\n  var s = uri.substring(i+1);\n  var m = uri.substring(0,i+1).match(/\\/d\\w\\/d\\w\\w\\/$/);\n  return m ? uri.substring(i-6) : s;\n}\n\nfunction localStorageSupported()\n{\n  try {\n    return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem;\n  }\n  catch(e) {\n    return false;\n  }\n}\n\n\nfunction storeLink(link)\n{\n  if (!$(\"#nav-sync\").hasClass('sync') && localStorageSupported()) {\n      window.localStorage.setItem('navpath',link);\n  }\n}\n\nfunction deleteLink()\n{\n  if (localStorageSupported()) {\n    window.localStorage.setItem('navpath','');\n  } \n}\n\nfunction cachedLink()\n{\n  if (localStorageSupported()) {\n    return window.localStorage.getItem('navpath');\n  } else {\n    return '';\n  }\n}\n\nfunction getScript(scriptName,func,show)\n{\n  var head = document.getElementsByTagName(\"head\")[0]; \n  var script = document.createElement('script');\n  script.id = scriptName;\n  script.type = 'text/javascript';\n  script.onload = func; \n  script.src = scriptName+'.js'; \n  if ($.browser.msie && $.browser.version<=8) { \n    // script.onload does not work with older versions of IE\n    script.onreadystatechange = function() {\n      if (script.readyState=='complete' || script.readyState=='loaded') { \n        func(); if (show) showRoot(); \n      }\n    }\n  }\n  head.appendChild(script); \n}\n\nfunction createIndent(o,domNode,node,level)\n{\n  var level=-1;\n  var n = node;\n  while (n.parentNode) { level++; n=n.parentNode; }\n  if (node.childrenData) {\n    var imgNode = document.createElement(\"img\");\n    imgNode.style.paddingLeft=(16*level).toString()+'px';\n    imgNode.width  = 16;\n    imgNode.height = 22;\n    imgNode.border = 0;\n    node.plus_img = imgNode;\n    node.expandToggle = document.createElement(\"a\");\n    node.expandToggle.href = \"javascript:void(0)\";\n    node.expandToggle.onclick = function() {\n      if (node.expanded) {\n        $(node.getChildrenUL()).slideUp(\"fast\");\n        node.plus_img.src = node.relpath+\"ftv2pnode.png\";\n        node.expanded = false;\n      } else {\n        expandNode(o, node, false, false);\n      }\n    }\n    node.expandToggle.appendChild(imgNode);\n    domNode.appendChild(node.expandToggle);\n    imgNode.src = node.relpath+\"ftv2pnode.png\";\n  } else {\n    var span = document.createElement(\"span\");\n    span.style.display = 'inline-block';\n    span.style.width   = 16*(level+1)+'px';\n    span.style.height  = '22px';\n    span.innerHTML = '&#160;';\n    domNode.appendChild(span);\n  } \n}\n\nvar animationInProgress = false;\n\nfunction gotoAnchor(anchor,aname,updateLocation)\n{\n  var pos, docContent = $('#doc-content');\n  if (anchor.parent().attr('class')=='memItemLeft' ||\n      anchor.parent().attr('class')=='fieldtype' ||\n      anchor.parent().is(':header')) \n  {\n    pos = anchor.parent().position().top;\n  } else if (anchor.position()) {\n    pos = anchor.position().top;\n  }\n  if (pos) {\n    var dist = Math.abs(Math.min(\n               pos-docContent.offset().top,\n               docContent[0].scrollHeight-\n               docContent.height()-docContent.scrollTop()));\n    animationInProgress=true;\n    docContent.animate({\n      scrollTop: pos + docContent.scrollTop() - docContent.offset().top\n    },Math.max(50,Math.min(500,dist)),function(){\n      if (updateLocation) window.location.href=aname;\n      animationInProgress=false;\n    });\n  }\n}\n\nfunction newNode(o, po, text, link, childrenData, lastNode)\n{\n  var node = new Object();\n  node.children = Array();\n  node.childrenData = childrenData;\n  node.depth = po.depth + 1;\n  node.relpath = po.relpath;\n  node.isLast = lastNode;\n\n  node.li = document.createElement(\"li\");\n  po.getChildrenUL().appendChild(node.li);\n  node.parentNode = po;\n\n  node.itemDiv = document.createElement(\"div\");\n  node.itemDiv.className = \"item\";\n\n  node.labelSpan = document.createElement(\"span\");\n  node.labelSpan.className = \"label\";\n\n  createIndent(o,node.itemDiv,node,0);\n  node.itemDiv.appendChild(node.labelSpan);\n  node.li.appendChild(node.itemDiv);\n\n  var a = document.createElement(\"a\");\n  node.labelSpan.appendChild(a);\n  node.label = document.createTextNode(text);\n  node.expanded = false;\n  a.appendChild(node.label);\n  if (link) {\n    var url;\n    if (link.substring(0,1)=='^') {\n      url = link.substring(1);\n      link = url;\n    } else {\n      url = node.relpath+link;\n    }\n    a.className = stripPath(link.replace('#',':'));\n    if (link.indexOf('#')!=-1) {\n      var aname = '#'+link.split('#')[1];\n      var srcPage = stripPath($(location).attr('pathname'));\n      var targetPage = stripPath(link.split('#')[0]);\n      a.href = srcPage!=targetPage ? url : \"javascript:void(0)\"; \n      a.onclick = function(){\n        storeLink(link);\n        if (!$(a).parent().parent().hasClass('selected'))\n        {\n          $('.item').removeClass('selected');\n          $('.item').removeAttr('id');\n          $(a).parent().parent().addClass('selected');\n          $(a).parent().parent().attr('id','selected');\n        }\n        var anchor = $(aname);\n        gotoAnchor(anchor,aname,true);\n      };\n    } else {\n      a.href = url;\n      a.onclick = function() { storeLink(link); }\n    }\n  } else {\n    if (childrenData != null) \n    {\n      a.className = \"nolink\";\n      a.href = \"javascript:void(0)\";\n      a.onclick = node.expandToggle.onclick;\n    }\n  }\n\n  node.childrenUL = null;\n  node.getChildrenUL = function() {\n    if (!node.childrenUL) {\n      node.childrenUL = document.createElement(\"ul\");\n      node.childrenUL.className = \"children_ul\";\n      node.childrenUL.style.display = \"none\";\n      node.li.appendChild(node.childrenUL);\n    }\n    return node.childrenUL;\n  };\n\n  return node;\n}\n\nfunction showRoot()\n{\n  var headerHeight = $(\"#top\").height();\n  var footerHeight = $(\"#nav-path\").height();\n  var windowHeight = $(window).height() - headerHeight - footerHeight;\n  (function (){ // retry until we can scroll to the selected item\n    try {\n      var navtree=$('#nav-tree');\n      navtree.scrollTo('#selected',0,{offset:-windowHeight/2});\n    } catch (err) {\n      setTimeout(arguments.callee, 0);\n    }\n  })();\n}\n\nfunction expandNode(o, node, imm, showRoot)\n{\n  if (node.childrenData && !node.expanded) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        expandNode(o, node, imm, showRoot);\n      }, showRoot);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      } if (imm || ($.browser.msie && $.browser.version>8)) { \n        // somehow slideDown jumps to the start of tree for IE9 :-(\n        $(node.getChildrenUL()).show();\n      } else {\n        $(node.getChildrenUL()).slideDown(\"fast\");\n      }\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n    }\n  }\n}\n\nfunction glowEffect(n,duration)\n{\n  n.addClass('glow').delay(duration).queue(function(next){\n    $(this).removeClass('glow');next();\n  });\n}\n\nfunction highlightAnchor()\n{\n  var aname = $(location).attr('hash');\n  var anchor = $(aname);\n  if (anchor.parent().attr('class')=='memItemLeft'){\n    var rows = $('.memberdecls tr[class$=\"'+\n               window.location.hash.substring(1)+'\"]');\n    glowEffect(rows.children(),300); // member without details\n  } else if (anchor.parents().slice(2).prop('tagName')=='TR') {\n    glowEffect(anchor.parents('div.memitem'),1000); // enum value\n  } else if (anchor.parent().attr('class')=='fieldtype'){\n    glowEffect(anchor.parent().parent(),1000); // struct field\n  } else if (anchor.parent().is(\":header\")) {\n    glowEffect(anchor.parent(),1000); // section header\n  } else {\n    glowEffect(anchor.next(),1000); // normal member\n  }\n  gotoAnchor(anchor,aname,false);\n}\n\nfunction selectAndHighlight(hash,n)\n{\n  var a;\n  if (hash) {\n    var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1);\n    a=$('.item a[class$=\"'+link+'\"]');\n  }\n  if (a && a.length) {\n    a.parent().parent().addClass('selected');\n    a.parent().parent().attr('id','selected');\n    highlightAnchor();\n  } else if (n) {\n    $(n.itemDiv).addClass('selected');\n    $(n.itemDiv).attr('id','selected');\n  }\n  if ($('#nav-tree-contents .item:first').hasClass('selected')) {\n    $('#nav-sync').css('top','30px');\n  } else {\n    $('#nav-sync').css('top','5px');\n  }\n  showRoot();\n}\n\nfunction showNode(o, node, index, hash)\n{\n  if (node && node.childrenData) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        showNode(o,node,index,hash);\n      },true);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      }\n      $(node.getChildrenUL()).css({'display':'block'});\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n      var n = node.children[o.breadcrumbs[index]];\n      if (index+1<o.breadcrumbs.length) {\n        showNode(o,n,index+1,hash);\n      } else {\n        if (typeof(n.childrenData)==='string') {\n          var varName = n.childrenData;\n          getScript(n.relpath+varName,function(){\n            n.childrenData = getData(varName);\n            node.expanded=false;\n            showNode(o,node,index,hash); // retry with child node expanded\n          },true);\n        } else {\n          var rootBase = stripPath(o.toroot.replace(/\\..+$/, ''));\n          if (rootBase==\"index\" || rootBase==\"pages\" || rootBase==\"search\") {\n            expandNode(o, n, true, true);\n          }\n          selectAndHighlight(hash,n);\n        }\n      }\n    }\n  } else {\n    selectAndHighlight(hash);\n  }\n}\n\nfunction removeToInsertLater(element) {\n  var parentNode = element.parentNode;\n  var nextSibling = element.nextSibling;\n  parentNode.removeChild(element);\n  return function() {\n    if (nextSibling) {\n      parentNode.insertBefore(element, nextSibling);\n    } else {\n      parentNode.appendChild(element);\n    }\n  };\n}\n\nfunction getNode(o, po)\n{\n  var insertFunction = removeToInsertLater(po.li);\n  po.childrenVisited = true;\n  var l = po.childrenData.length-1;\n  for (var i in po.childrenData) {\n    var nodeData = po.childrenData[i];\n    po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],\n      i==l);\n  }\n  insertFunction();\n}\n\nfunction gotoNode(o,subIndex,root,hash,relpath)\n{\n  var nti = navTreeSubIndices[subIndex][root+hash];\n  o.breadcrumbs = $.extend(true, [], nti ? nti : navTreeSubIndices[subIndex][root]);\n  if (!o.breadcrumbs && root!=NAVTREE[0][1]) { // fallback: show index\n    navTo(o,NAVTREE[0][1],\"\",relpath);\n    $('.item').removeClass('selected');\n    $('.item').removeAttr('id');\n  }\n  if (o.breadcrumbs) {\n    o.breadcrumbs.unshift(0); // add 0 for root node\n    showNode(o, o.node, 0, hash);\n  }\n}\n\nfunction navTo(o,root,hash,relpath)\n{\n  var link = cachedLink();\n  if (link) {\n    var parts = link.split('#');\n    root = parts[0];\n    if (parts.length>1) hash = '#'+parts[1];\n    else hash='';\n  }\n  if (hash.match(/^#l\\d+$/)) {\n    var anchor=$('a[name='+hash.substring(1)+']');\n    glowEffect(anchor.parent(),1000); // line number\n    hash=''; // strip line number anchors\n    //root=root.replace(/_source\\./,'.'); // source link to doc link\n  }\n  var url=root+hash;\n  var i=-1;\n  while (NAVTREEINDEX[i+1]<=url) i++;\n  if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index\n  if (navTreeSubIndices[i]) {\n    gotoNode(o,i,root,hash,relpath)\n  } else {\n    getScript(relpath+'navtreeindex'+i,function(){\n      navTreeSubIndices[i] = eval('NAVTREEINDEX'+i);\n      if (navTreeSubIndices[i]) {\n        gotoNode(o,i,root,hash,relpath);\n      }\n    },true);\n  }\n}\n\nfunction showSyncOff(n,relpath)\n{\n    n.html('<img src=\"'+relpath+'sync_off.png\" title=\"'+SYNCOFFMSG+'\"/>');\n}\n\nfunction showSyncOn(n,relpath)\n{\n    n.html('<img src=\"'+relpath+'sync_on.png\" title=\"'+SYNCONMSG+'\"/>');\n}\n\nfunction toggleSyncButton(relpath)\n{\n  var navSync = $('#nav-sync');\n  if (navSync.hasClass('sync')) {\n    navSync.removeClass('sync');\n    showSyncOff(navSync,relpath);\n    storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash'));\n  } else {\n    navSync.addClass('sync');\n    showSyncOn(navSync,relpath);\n    deleteLink();\n  }\n}\n\nfunction initNavTree(toroot,relpath)\n{\n  var o = new Object();\n  o.toroot = toroot;\n  o.node = new Object();\n  o.node.li = document.getElementById(\"nav-tree-contents\");\n  o.node.childrenData = NAVTREE;\n  o.node.children = new Array();\n  o.node.childrenUL = document.createElement(\"ul\");\n  o.node.getChildrenUL = function() { return o.node.childrenUL; };\n  o.node.li.appendChild(o.node.childrenUL);\n  o.node.depth = 0;\n  o.node.relpath = relpath;\n  o.node.expanded = false;\n  o.node.isLast = true;\n  o.node.plus_img = document.createElement(\"img\");\n  o.node.plus_img.src = relpath+\"ftv2pnode.png\";\n  o.node.plus_img.width = 16;\n  o.node.plus_img.height = 22;\n\n  if (localStorageSupported()) {\n    var navSync = $('#nav-sync');\n    if (cachedLink()) {\n      showSyncOff(navSync,relpath);\n      navSync.removeClass('sync');\n    } else {\n      showSyncOn(navSync,relpath);\n    }\n    navSync.click(function(){ toggleSyncButton(relpath); });\n  }\n\n  $(window).load(function(){\n    navTo(o,toroot,window.location.hash,relpath);\n    showRoot();\n  });\n\n  $(window).bind('hashchange', function(){\n     if (window.location.hash && window.location.hash.length>1){\n       var a;\n       if ($(location).attr('hash')){\n         var clslink=stripPath($(location).attr('pathname'))+':'+\n                               $(location).attr('hash').substring(1);\n         a=$('.item a[class$=\"'+clslink+'\"]');\n       }\n       if (a==null || !$(a).parent().parent().hasClass('selected')){\n         $('.item').removeClass('selected');\n         $('.item').removeAttr('id');\n       }\n       var link=stripPath2($(location).attr('pathname'));\n       navTo(o,link,$(location).attr('hash'),relpath);\n     } else if (!animationInProgress) {\n       $('#doc-content').scrollTop(0);\n       $('.item').removeClass('selected');\n       $('.item').removeAttr('id');\n       navTo(o,toroot,window.location.hash,relpath);\n     }\n  })\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/navtreeindex0.js",
    "content": "var NAVTREEINDEX0 =\n{\n\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/none_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/none_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/none_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/pages.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/pages.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/pages.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">CMSIS-DSP resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/printComponentTabs.js",
    "content": "var strgURL =   location.pathname;                      // path of current component\n\n// constuctor for the array of objects\nfunction tabElement(id, folderName, tabTxt )  {\n\tthis.id = id;                                       // elementID as needed in html; \n\tthis.folderName = folderName;                       // folder name of the component \n    this.tabTxt = tabTxt;                               // Text displayed as menu on the web\n\tthis.currentListItem = '<li id=\"' + this.id + '\" class=\"current\"> <a href=\"../..' + this.folderName + 'index.html\"><span>' + this.tabTxt + '</span></a></li>';\n\tthis.listItem = '<li id=\"' + this.id + '\"> <a href=\"../..' + this.folderName + 'index.html\"><span>' + this.tabTxt + '</span></a></li>';\n};\n\n// array of objects\nvar arr = [];\n\n// fill array\n arr.push( new tabElement( \"GEN\",     \"/General/html/\",     \"General\")   );\n arr.push( new tabElement( \"CORE_A\",  \"/Core_A/html/\",      \"Core(A)\")   );\n arr.push( new tabElement( \"CORE_M\",  \"/Core/html/\",        \"Core(M)\")   );\n arr.push( new tabElement( \"DRV\",     \"/Driver/html/\",      \"Driver\")    );\n arr.push( new tabElement( \"DSP&ML\",  \"/DSP/html/\",         \"DSP\")       );\n arr.push( new tabElement( \"NN\",      \"/NN/html/\",          \"NN\")        );\n arr.push( new tabElement( \"RTOSv1\",  \"/RTOS/html/\",        \"RTOS v1\")   );\n arr.push( new tabElement( \"RTOSv2\",  \"/RTOS2/html/\",       \"RTOS v2\")   );\n arr.push( new tabElement( \"PACK\",    \"/Pack/html/\",        \"Pack\")      );\n arr.push( new tabElement( \"Build\",   \"/Build/html/\",       \"Build\")     );\n arr.push( new tabElement( \"SVD\",     \"/SVD/html/\",         \"SVD\")       );\n arr.push( new tabElement( \"DAP\",     \"/DAP/html/\",         \"DAP\")       );\n arr.push( new tabElement( \"ZONE\",    \"/Zone/html/\",        \"Zone\")      );\n \n// write tabs\n// called from the header file.\nfunction writeComponentTabs()  {\n  for ( var i=0; i < arr.length; i++ ) {\n    if (strgURL.search(arr[i].folderName) > 0) {                    // if this is the current folder\n      document.write(arr[i].currentListItem);                       // then print and hightlight the tab\n    } else {                                                      \n      document.write(arr[i].listItem);                              // else, print the tab\n    }                                                             \n  }\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/quaternion__math__functions_8h.html",
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    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html><head><title></title>\n<meta http-equiv=\"Content-Type\" content=\"text/xhtml;charset=UTF-8\"/>\n<meta name=\"generator\" content=\"Doxygen 1.8.6\">\n<link rel=\"stylesheet\" type=\"text/css\" href=\"search.css\"/>\n<script type=\"text/javascript\" src=\"pages_0.js\"></script>\n<script type=\"text/javascript\" src=\"search.js\"></script>\n</head>\n<body class=\"SRPage\">\n<div id=\"SRIndex\">\n<div class=\"SRStatus\" id=\"Loading\">Loading...</div>\n<div id=\"SRResults\"></div>\n<script type=\"text/javascript\"><!--\ncreateResults();\n--></script>\n<div class=\"SRStatus\" id=\"Searching\">Searching...</div>\n<div class=\"SRStatus\" id=\"NoMatches\">No Matches</div>\n<script type=\"text/javascript\"><!--\ndocument.getElementById(\"Loading\").style.display=\"none\";\ndocument.getElementById(\"NoMatches\").style.display=\"none\";\nvar searchResults = new SearchResults(\"searchResults\");\nsearchResults.Search();\n--></script>\n</div>\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/search/pages_0.js",
    "content": "var searchData=\n[\n  ['cmsis_20dsp_20software_20library',['CMSIS DSP Software Library',['../index.html',1,'']]]\n];\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/search/pages_1.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html><head><title></title>\n<meta http-equiv=\"Content-Type\" content=\"text/xhtml;charset=UTF-8\"/>\n<meta name=\"generator\" content=\"Doxygen 1.8.6\">\n<link rel=\"stylesheet\" type=\"text/css\" href=\"search.css\"/>\n<script type=\"text/javascript\" src=\"pages_1.js\"></script>\n<script type=\"text/javascript\" src=\"search.js\"></script>\n</head>\n<body class=\"SRPage\">\n<div id=\"SRIndex\">\n<div class=\"SRStatus\" id=\"Loading\">Loading...</div>\n<div id=\"SRResults\"></div>\n<script type=\"text/javascript\"><!--\ncreateResults();\n--></script>\n<div class=\"SRStatus\" id=\"Searching\">Searching...</div>\n<div class=\"SRStatus\" id=\"NoMatches\">No Matches</div>\n<script type=\"text/javascript\"><!--\ndocument.getElementById(\"Loading\").style.display=\"none\";\ndocument.getElementById(\"NoMatches\").style.display=\"none\";\nvar searchResults = new SearchResults(\"searchResults\");\nsearchResults.Search();\n--></script>\n</div>\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/search/pages_1.js",
    "content": "var searchData=\n[\n  ['deprecated_20list',['Deprecated List',['../deprecated.html',1,'']]]\n];\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/search/pages_2.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html><head><title></title>\n<meta http-equiv=\"Content-Type\" content=\"text/xhtml;charset=UTF-8\"/>\n<meta name=\"generator\" content=\"Doxygen 1.8.6\">\n<link rel=\"stylesheet\" type=\"text/css\" href=\"search.css\"/>\n<script type=\"text/javascript\" src=\"pages_2.js\"></script>\n<script type=\"text/javascript\" src=\"search.js\"></script>\n</head>\n<body class=\"SRPage\">\n<div id=\"SRIndex\">\n<div class=\"SRStatus\" id=\"Loading\">Loading...</div>\n<div id=\"SRResults\"></div>\n<script type=\"text/javascript\"><!--\ncreateResults();\n--></script>\n<div class=\"SRStatus\" id=\"Searching\">Searching...</div>\n<div class=\"SRStatus\" id=\"NoMatches\">No Matches</div>\n<script type=\"text/javascript\"><!--\ndocument.getElementById(\"Loading\").style.display=\"none\";\ndocument.getElementById(\"NoMatches\").style.display=\"none\";\nvar searchResults = new SearchResults(\"searchResults\");\nsearchResults.Search();\n--></script>\n</div>\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/search/pages_2.js",
    "content": "var searchData=\n[\n  ['revision_20history',['Revision History',['../ChangeLog_pg.html',1,'']]]\n];\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/search/search.css",
    "content": "/*---------------- Search Box */\n\n#FSearchBox {\n    float: left;\n}\n\n#searchli {\n    float: right;\n    display: block;\n    width: 170px;\n    height: 24px;\n}\n\n#MSearchBox {\n    white-space : nowrap;\n    position: absolute;\n    float: none;\n    display: inline;\n    margin-top: 3px;\n    right: 0px;\n    width: 170px;\n    z-index: 102;\n}\n\n#MSearchBox .left\n{\n    display:block;\n    position:absolute;\n    left:10px;\n    width:20px;\n    height:19px;\n    background:url('search_l.png') no-repeat;\n    background-position:right;\n}\n\n#MSearchSelect {\n    display:block;\n    position:absolute;\n    width:20px;\n    height:19px;\n}\n\n.left #MSearchSelect {\n    left:4px;\n}\n\n.right #MSearchSelect {\n    right:5px;\n}\n\n#MSearchField {\n    display:block;\n    position:absolute;\n    height:19px;\n    background:url('search_m.png') repeat-x;\n    border:none;\n    width:116px;\n    margin-left:20px;\n    padding-left:4px;\n    color: #909090;\n    outline: none;\n    font: 9pt Arial, Verdana, sans-serif;\n}\n\n#FSearchBox #MSearchField {\n    margin-left:15px;\n}\n\n#MSearchBox .right {\n    display:block;\n    position:absolute;\n    right:10px;\n    top:0px;\n    width:20px;\n    height:19px;\n    background:url('search_r.png') no-repeat;\n    background-position:left;\n}\n\n#MSearchClose {\n    display: none;\n    position: absolute;\n    top: 4px;\n    background : none;\n    border: none;\n    margin: 0px 4px 0px 0px;\n    padding: 0px 0px;\n    outline: none;\n}\n\n.left #MSearchClose {\n    left: 6px;\n}\n\n.right #MSearchClose {\n    right: 2px;\n}\n\n.MSearchBoxActive #MSearchField {\n    color: #000000;\n}\n\n/*---------------- Search filter selection */\n\n#MSearchSelectWindow {\n    display: none;\n    position: absolute;\n    left: 0; top: 0;\n    border: 1px solid #90A5CE;\n    background-color: #F9FAFC;\n    z-index: 1;\n    padding-top: 4px;\n    padding-bottom: 4px;\n    -moz-border-radius: 4px;\n    -webkit-border-top-left-radius: 4px;\n    -webkit-border-top-right-radius: 4px;\n    -webkit-border-bottom-left-radius: 4px;\n    -webkit-border-bottom-right-radius: 4px;\n    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\n.SelectItem {\n    font: 8pt Arial, Verdana, sans-serif;\n    padding-left:  2px;\n    padding-right: 12px;\n    border: 0px;\n}\n\nspan.SelectionMark {\n    margin-right: 4px;\n    font-family: monospace;\n    outline-style: none;\n    text-decoration: none;\n}\n\na.SelectItem {\n    display: block;\n    outline-style: none;\n    color: #000000; \n    text-decoration: none;\n    padding-left:   6px;\n    padding-right: 12px;\n}\n\na.SelectItem:focus,\na.SelectItem:active {\n    color: #000000; \n    outline-style: none;\n    text-decoration: none;\n}\n\na.SelectItem:hover {\n    color: #FFFFFF;\n    background-color: #3D578C;\n    outline-style: none;\n    text-decoration: none;\n    cursor: pointer;\n    display: block;\n}\n\n/*---------------- Search results window */\n\niframe#MSearchResults {\n    width: 60ex;\n    height: 15em;\n}\n\n#MSearchResultsWindow {\n    display: none;\n    position: absolute;\n    left: 0; top: 0;\n    border: 1px solid #000;\n    background-color: #EEF1F7;\n}\n\n/* ----------------------------------- */\n\n\n#SRIndex {\n    clear:both; \n    padding-bottom: 15px;\n}\n\n.SREntry {\n    font-size: 10pt;\n    padding-left: 1ex;\n}\n\n.SRPage .SREntry {\n    font-size: 8pt;\n    padding: 1px 5px;\n}\n\nbody.SRPage {\n    margin: 5px 2px;\n}\n\n.SRChildren {\n    padding-left: 3ex; padding-bottom: .5em \n}\n\n.SRPage .SRChildren {\n    display: none;\n}\n\n.SRSymbol {\n    font-weight: bold; \n    color: #425E97;\n    font-family: Arial, Verdana, sans-serif;\n    text-decoration: none;\n    outline: none;\n}\n\na.SRScope {\n    display: block;\n    color: #425E97; \n    font-family: Arial, Verdana, sans-serif;\n    text-decoration: none;\n    outline: none;\n}\n\na.SRSymbol:focus, a.SRSymbol:active,\na.SRScope:focus, a.SRScope:active {\n    text-decoration: underline;\n}\n\n.SRPage .SRStatus {\n    padding: 2px 5px;\n    font-size: 8pt;\n    font-style: italic;\n}\n\n.SRResult {\n    display: none;\n}\n\nDIV.searchresults {\n    margin-left: 10px;\n    margin-right: 10px;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/search/search.js",
    "content": "// Search script generated by doxygen\n// Copyright (C) 2009 by Dimitri van Heesch.\n\n// The code in this file is loosly based on main.js, part of Natural Docs,\n// which is Copyright (C) 2003-2008 Greg Valure\n// Natural Docs is licensed under the GPL.\n\nvar indexSectionsWithContent =\n{\n  0: \"abcdfioprsuxz\",\n  1: \"abcdfioprsuxz\"\n};\n\nvar indexSectionNames =\n{\n  0: \"all\",\n  1: \"pages\"\n};\n\nfunction convertToId(search)\n{\n  var result = '';\n  for (i=0;i<search.length;i++)\n  {\n    var c = search.charAt(i);\n    var cn = c.charCodeAt(0);\n    if (c.match(/[a-z0-9\\u0080-\\uFFFF]/))\n    {\n      result+=c;\n    }\n    else if (cn<16) \n    {\n      result+=\"_0\"+cn.toString(16);\n    }\n    else \n    {\n      result+=\"_\"+cn.toString(16);\n    }\n  }\n  return result;\n}\n\nfunction getXPos(item)\n{\n  var x = 0;\n  if (item.offsetWidth)\n  {\n    while (item && item!=document.body)\n    {\n      x   += item.offsetLeft;\n      item = item.offsetParent;\n    }\n  }\n  return x;\n}\n\nfunction getYPos(item)\n{\n  var y = 0;\n  if (item.offsetWidth)\n  {\n     while (item && item!=document.body)\n     {\n       y   += item.offsetTop;\n       item = item.offsetParent;\n     }\n  }\n  return y;\n}\n\n/* A class handling everything associated with the search panel.\n\n   Parameters:\n   name - The name of the global variable that will be \n          storing this instance.  Is needed to be able to set timeouts.\n   resultPath - path to use for external files\n*/\nfunction SearchBox(name, resultsPath, inFrame, label)\n{\n  if (!name || !resultsPath) {  alert(\"Missing parameters to SearchBox.\"); }\n   \n  // ---------- Instance variables\n  this.name                  = name;\n  this.resultsPath           = resultsPath;\n  this.keyTimeout            = 0;\n  this.keyTimeoutLength      = 500;\n  this.closeSelectionTimeout = 300;\n  this.lastSearchValue       = \"\";\n  this.lastResultsPage       = \"\";\n  this.hideTimeout           = 0;\n  this.searchIndex           = 0;\n  this.searchActive          = false;\n  this.insideFrame           = inFrame;\n  this.searchLabel           = label;\n\n  // ----------- DOM Elements\n\n  this.DOMSearchField = function()\n  {  return document.getElementById(\"MSearchField\");  }\n\n  this.DOMSearchSelect = function()\n  {  return document.getElementById(\"MSearchSelect\");  }\n\n  this.DOMSearchSelectWindow = function()\n  {  return document.getElementById(\"MSearchSelectWindow\");  }\n\n  this.DOMPopupSearchResults = function()\n  {  return document.getElementById(\"MSearchResults\");  }\n\n  this.DOMPopupSearchResultsWindow = function()\n  {  return document.getElementById(\"MSearchResultsWindow\");  }\n\n  this.DOMSearchClose = function()\n  {  return document.getElementById(\"MSearchClose\"); }\n\n  this.DOMSearchBox = function()\n  {  return document.getElementById(\"MSearchBox\");  }\n\n  // ------------ Event Handlers\n\n  // Called when focus is added or removed from the search field.\n  this.OnSearchFieldFocus = function(isActive)\n  {\n    this.Activate(isActive);\n  }\n\n  this.OnSearchSelectShow = function()\n  {\n    var searchSelectWindow = this.DOMSearchSelectWindow();\n    var searchField        = this.DOMSearchSelect();\n\n    if (this.insideFrame)\n    {\n      var left = getXPos(searchField);\n      var top  = getYPos(searchField);\n      left += searchField.offsetWidth + 6;\n      top += searchField.offsetHeight;\n\n      // show search selection popup\n      searchSelectWindow.style.display='block';\n      left -= searchSelectWindow.offsetWidth;\n      searchSelectWindow.style.left =  left + 'px';\n      searchSelectWindow.style.top  =  top  + 'px';\n    }\n    else\n    {\n      var left = getXPos(searchField);\n      var top  = getYPos(searchField);\n      top += searchField.offsetHeight;\n\n      // show search selection popup\n      searchSelectWindow.style.display='block';\n      searchSelectWindow.style.left =  left + 'px';\n      searchSelectWindow.style.top  =  top  + 'px';\n    }\n\n    // stop selection hide timer\n    if (this.hideTimeout) \n    {\n      clearTimeout(this.hideTimeout);\n      this.hideTimeout=0;\n    }\n    return false; // to avoid \"image drag\" default event\n  }\n\n  this.OnSearchSelectHide = function()\n  {\n    this.hideTimeout = setTimeout(this.name +\".CloseSelectionWindow()\",\n                                  this.closeSelectionTimeout);\n  }\n\n  // Called when the content of the search field is changed.\n  this.OnSearchFieldChange = function(evt)\n  {\n    if (this.keyTimeout) // kill running timer\n    {\n      clearTimeout(this.keyTimeout);\n      this.keyTimeout = 0;\n    }\n\n    var e  = (evt) ? evt : window.event; // for IE\n    if (e.keyCode==40 || e.keyCode==13)\n    {\n      if (e.shiftKey==1)\n      {\n        this.OnSearchSelectShow();\n        var win=this.DOMSearchSelectWindow(); \n        for (i=0;i<win.childNodes.length;i++)\n        {\n          var child = win.childNodes[i]; // get span within a\n          if (child.className=='SelectItem')\n          {\n            child.focus();\n            return;\n          }\n        }\n        return;\n      }\n      else if (window.frames.MSearchResults.searchResults)\n      {\n        var elem = window.frames.MSearchResults.searchResults.NavNext(0);\n        if (elem) elem.focus();\n      }\n    }\n    else if (e.keyCode==27) // Escape out of the search field\n    {\n      this.DOMSearchField().blur();\n      this.DOMPopupSearchResultsWindow().style.display = 'none';\n      this.DOMSearchClose().style.display = 'none';\n      this.lastSearchValue = '';\n      this.Activate(false);\n      return;\n    }\n\n    // strip whitespaces\n    var searchValue = this.DOMSearchField().value.replace(/ +/g, \"\");\n\n    if (searchValue != this.lastSearchValue) // search value has changed\n    {\n      if (searchValue != \"\") // non-empty search\n      {\n        // set timer for search update\n        this.keyTimeout = setTimeout(this.name + '.Search()',\n                                     this.keyTimeoutLength);\n      }\n      else // empty search field\n      {\n        this.DOMPopupSearchResultsWindow().style.display = 'none';\n        this.DOMSearchClose().style.display = 'none';\n        this.lastSearchValue = '';\n      }\n    }\n  }\n\n  this.SelectItemCount = function(id)\n  {\n    var count=0;\n    var win=this.DOMSearchSelectWindow(); \n    for (i=0;i<win.childNodes.length;i++)\n    {\n      var child = win.childNodes[i]; // get span within a\n      if (child.className=='SelectItem')\n      {\n        count++;\n      }\n    }\n    return count;\n  }\n\n  this.SelectItemSet = function(id)\n  {\n    var i,j=0;\n    var win=this.DOMSearchSelectWindow(); \n    for (i=0;i<win.childNodes.length;i++)\n    {\n      var child = win.childNodes[i]; // get span within a\n      if (child.className=='SelectItem')\n      {\n        var node = child.firstChild;\n        if (j==id)\n        {\n          node.innerHTML='&#8226;';\n        }\n        else\n        {\n          node.innerHTML='&#160;';\n        }\n        j++;\n      }\n    }\n  }\n\n  // Called when an search filter selection is made.\n  // set item with index id as the active item\n  this.OnSelectItem = function(id)\n  {\n    this.searchIndex = id;\n    this.SelectItemSet(id);\n    var searchValue = this.DOMSearchField().value.replace(/ +/g, \"\");\n    if (searchValue!=\"\" && this.searchActive) // something was found -> do a search\n    {\n      this.Search();\n    }\n  }\n\n  this.OnSearchSelectKey = function(evt)\n  {\n    var e = (evt) ? evt : window.event; // for IE\n    if (e.keyCode==40 && this.searchIndex<this.SelectItemCount()) // Down\n    {\n      this.searchIndex++;\n      this.OnSelectItem(this.searchIndex);\n    }\n    else if (e.keyCode==38 && this.searchIndex>0) // Up\n    {\n      this.searchIndex--;\n      this.OnSelectItem(this.searchIndex);\n    }\n    else if (e.keyCode==13 || e.keyCode==27)\n    {\n      this.OnSelectItem(this.searchIndex);\n      this.CloseSelectionWindow();\n      this.DOMSearchField().focus();\n    }\n    return false;\n  }\n\n  // --------- Actions\n\n  // Closes the results window.\n  this.CloseResultsWindow = function()\n  {\n    this.DOMPopupSearchResultsWindow().style.display = 'none';\n    this.DOMSearchClose().style.display = 'none';\n    this.Activate(false);\n  }\n\n  this.CloseSelectionWindow = function()\n  {\n    this.DOMSearchSelectWindow().style.display = 'none';\n  }\n\n  // Performs a search.\n  this.Search = function()\n  {\n    this.keyTimeout = 0;\n\n    // strip leading whitespace\n    var searchValue = this.DOMSearchField().value.replace(/^ +/, \"\");\n\n    var code = searchValue.toLowerCase().charCodeAt(0);\n    var idxChar = searchValue.substr(0, 1).toLowerCase();\n    if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair\n    {\n      idxChar = searchValue.substr(0, 2);\n    }\n\n    var resultsPage;\n    var resultsPageWithSearch;\n    var hasResultsPage;\n\n    var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar);\n    if (idx!=-1)\n    {\n       var hexCode=idx.toString(16);\n       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';\n       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);\n       hasResultsPage = true;\n    }\n    else // nothing available for this search term\n    {\n       resultsPage = this.resultsPath + '/nomatches.html';\n       resultsPageWithSearch = resultsPage;\n       hasResultsPage = false;\n    }\n\n    window.frames.MSearchResults.location = resultsPageWithSearch;  \n    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();\n\n    if (domPopupSearchResultsWindow.style.display!='block')\n    {\n       var domSearchBox = this.DOMSearchBox();\n       this.DOMSearchClose().style.display = 'inline';\n       if (this.insideFrame)\n       {\n         var domPopupSearchResults = this.DOMPopupSearchResults();\n         domPopupSearchResultsWindow.style.position = 'relative';\n         domPopupSearchResultsWindow.style.display  = 'block';\n         var width = document.body.clientWidth - 8; // the -8 is for IE :-(\n         domPopupSearchResultsWindow.style.width    = width + 'px';\n         domPopupSearchResults.style.width          = width + 'px';\n       }\n       else\n       {\n         var domPopupSearchResults = this.DOMPopupSearchResults();\n         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;\n         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;\n         domPopupSearchResultsWindow.style.display = 'block';\n         left -= domPopupSearchResults.offsetWidth;\n         domPopupSearchResultsWindow.style.top     = top  + 'px';\n         domPopupSearchResultsWindow.style.left    = left + 'px';\n       }\n    }\n\n    this.lastSearchValue = searchValue;\n    this.lastResultsPage = resultsPage;\n  }\n\n  // -------- Activation Functions\n\n  // Activates or deactivates the search panel, resetting things to \n  // their default values if necessary. \n  this.Activate = function(isActive)\n  {\n    if (isActive || // open it\n        this.DOMPopupSearchResultsWindow().style.display == 'block' \n       )\n    {\n      this.DOMSearchBox().className = 'MSearchBoxActive';\n\n      var searchField = this.DOMSearchField();\n\n      if (searchField.value == this.searchLabel) // clear \"Search\" term upon entry\n      {  \n        searchField.value = '';  \n        this.searchActive = true;\n      }\n    }\n    else if (!isActive) // directly remove the panel\n    {\n      this.DOMSearchBox().className = 'MSearchBoxInactive';\n      this.DOMSearchField().value   = this.searchLabel;\n      this.searchActive             = false;\n      this.lastSearchValue          = ''\n      this.lastResultsPage          = '';\n    }\n  }\n}\n\n// -----------------------------------------------------------------------\n\n// The class that handles everything on the search results page.\nfunction SearchResults(name)\n{\n    // The number of matches from the last run of <Search()>.\n    this.lastMatchCount = 0;\n    this.lastKey = 0;\n    this.repeatOn = false;\n\n    // Toggles the visibility of the passed element ID.\n    this.FindChildElement = function(id)\n    {\n      var parentElement = document.getElementById(id);\n      var element = parentElement.firstChild;\n\n      while (element && element!=parentElement)\n      {\n        if (element.nodeName == 'DIV' && element.className == 'SRChildren')\n        {\n          return element;\n        }\n\n        if (element.nodeName == 'DIV' && element.hasChildNodes())\n        {  \n           element = element.firstChild;  \n        }\n        else if (element.nextSibling)\n        {  \n           element = element.nextSibling;  \n        }\n        else\n        {\n          do\n          {\n            element = element.parentNode;\n          }\n          while (element && element!=parentElement && !element.nextSibling);\n\n          if (element && element!=parentElement)\n          {  \n            element = element.nextSibling;  \n          }\n        }\n      }\n    }\n\n    this.Toggle = function(id)\n    {\n      var element = this.FindChildElement(id);\n      if (element)\n      {\n        if (element.style.display == 'block')\n        {\n          element.style.display = 'none';\n        }\n        else\n        {\n          element.style.display = 'block';\n        }\n      }\n    }\n\n    // Searches for the passed string.  If there is no parameter,\n    // it takes it from the URL query.\n    //\n    // Always returns true, since other documents may try to call it\n    // and that may or may not be possible.\n    this.Search = function(search)\n    {\n      if (!search) // get search word from URL\n      {\n        search = window.location.search;\n        search = search.substring(1);  // Remove the leading '?'\n        search = unescape(search);\n      }\n\n      search = search.replace(/^ +/, \"\"); // strip leading spaces\n      search = search.replace(/ +$/, \"\"); // strip trailing spaces\n      search = search.toLowerCase();\n      search = convertToId(search);\n\n      var resultRows = document.getElementsByTagName(\"div\");\n      var matches = 0;\n\n      var i = 0;\n      while (i < resultRows.length)\n      {\n        var row = resultRows.item(i);\n        if (row.className == \"SRResult\")\n        {\n          var rowMatchName = row.id.toLowerCase();\n          rowMatchName = rowMatchName.replace(/^sr\\d*_/, ''); // strip 'sr123_'\n\n          if (search.length<=rowMatchName.length && \n             rowMatchName.substr(0, search.length)==search)\n          {\n            row.style.display = 'block';\n            matches++;\n          }\n          else\n          {\n            row.style.display = 'none';\n          }\n        }\n        i++;\n      }\n      document.getElementById(\"Searching\").style.display='none';\n      if (matches == 0) // no results\n      {\n        document.getElementById(\"NoMatches\").style.display='block';\n      }\n      else // at least one result\n      {\n        document.getElementById(\"NoMatches\").style.display='none';\n      }\n      this.lastMatchCount = matches;\n      return true;\n    }\n\n    // return the first item with index index or higher that is visible\n    this.NavNext = function(index)\n    {\n      var focusItem;\n      while (1)\n      {\n        var focusName = 'Item'+index;\n        focusItem = document.getElementById(focusName);\n        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')\n        {\n          break;\n        }\n        else if (!focusItem) // last element\n        {\n          break;\n        }\n        focusItem=null;\n        index++;\n      }\n      return focusItem;\n    }\n\n    this.NavPrev = function(index)\n    {\n      var focusItem;\n      while (1)\n      {\n        var focusName = 'Item'+index;\n        focusItem = document.getElementById(focusName);\n        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')\n        {\n          break;\n        }\n        else if (!focusItem) // last element\n        {\n          break;\n        }\n        focusItem=null;\n        index--;\n      }\n      return focusItem;\n    }\n\n    this.ProcessKeys = function(e)\n    {\n      if (e.type == \"keydown\") \n      {\n        this.repeatOn = false;\n        this.lastKey = e.keyCode;\n      }\n      else if (e.type == \"keypress\")\n      {\n        if (!this.repeatOn)\n        {\n          if (this.lastKey) this.repeatOn = true;\n          return false; // ignore first keypress after keydown\n        }\n      }\n      else if (e.type == \"keyup\")\n      {\n        this.lastKey = 0;\n        this.repeatOn = false;\n      }\n      return this.lastKey!=0;\n    }\n\n    this.Nav = function(evt,itemIndex) \n    {\n      var e  = (evt) ? evt : window.event; // for IE\n      if (e.keyCode==13) return true;\n      if (!this.ProcessKeys(e)) return false;\n\n      if (this.lastKey==38) // Up\n      {\n        var newIndex = itemIndex-1;\n        var focusItem = this.NavPrev(newIndex);\n        if (focusItem)\n        {\n          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);\n          if (child && child.style.display == 'block') // children visible\n          { \n            var n=0;\n            var tmpElem;\n            while (1) // search for last child\n            {\n              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);\n              if (tmpElem)\n              {\n                focusItem = tmpElem;\n              }\n              else // found it!\n              {\n                break;\n              }\n              n++;\n            }\n          }\n        }\n        if (focusItem)\n        {\n          focusItem.focus();\n        }\n        else // return focus to search field\n        {\n           parent.document.getElementById(\"MSearchField\").focus();\n        }\n      }\n      else if (this.lastKey==40) // Down\n      {\n        var newIndex = itemIndex+1;\n        var focusItem;\n        var item = document.getElementById('Item'+itemIndex);\n        var elem = this.FindChildElement(item.parentNode.parentNode.id);\n        if (elem && elem.style.display == 'block') // children visible\n        {\n          focusItem = document.getElementById('Item'+itemIndex+'_c0');\n        }\n        if (!focusItem) focusItem = this.NavNext(newIndex);\n        if (focusItem)  focusItem.focus();\n      }\n      else if (this.lastKey==39) // Right\n      {\n        var item = document.getElementById('Item'+itemIndex);\n        var elem = this.FindChildElement(item.parentNode.parentNode.id);\n        if (elem) elem.style.display = 'block';\n      }\n      else if (this.lastKey==37) // Left\n      {\n        var item = document.getElementById('Item'+itemIndex);\n        var elem = this.FindChildElement(item.parentNode.parentNode.id);\n        if (elem) elem.style.display = 'none';\n      }\n      else if (this.lastKey==27) // Escape\n      {\n        parent.searchBox.CloseResultsWindow();\n        parent.document.getElementById(\"MSearchField\").focus();\n      }\n      else if (this.lastKey==13) // Enter\n      {\n        return true;\n      }\n      return false;\n    }\n\n    this.NavChild = function(evt,itemIndex,childIndex)\n    {\n      var e  = (evt) ? evt : window.event; // for IE\n      if (e.keyCode==13) return true;\n      if (!this.ProcessKeys(e)) return false;\n\n      if (this.lastKey==38) // Up\n      {\n        if (childIndex>0)\n        {\n          var newIndex = childIndex-1;\n          document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();\n        }\n        else // already at first child, jump to parent\n        {\n          document.getElementById('Item'+itemIndex).focus();\n        }\n      }\n      else if (this.lastKey==40) // Down\n      {\n        var newIndex = childIndex+1;\n        var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);\n        if (!elem) // last child, jump to parent next parent\n        {\n          elem = this.NavNext(itemIndex+1);\n        }\n        if (elem)\n        {\n          elem.focus();\n        } \n      }\n      else if (this.lastKey==27) // Escape\n      {\n        parent.searchBox.CloseResultsWindow();\n        parent.document.getElementById(\"MSearchField\").focus();\n      }\n      else if (this.lastKey==13) // Enter\n      {\n        return true;\n      }\n      return false;\n    }\n}\n\nfunction setKeyActions(elem,action)\n{\n  elem.setAttribute('onkeydown',action);\n  elem.setAttribute('onkeypress',action);\n  elem.setAttribute('onkeyup',action);\n}\n\nfunction setClassAttr(elem,attr)\n{\n  elem.setAttribute('class',attr);\n  elem.setAttribute('className',attr);\n}\n\nfunction createResults()\n{\n  var results = document.getElementById(\"SRResults\");\n  for (var e=0; e<searchData.length; e++)\n  {\n    var id = searchData[e][0];\n    var srResult = document.createElement('div');\n    srResult.setAttribute('id','SR_'+id);\n    setClassAttr(srResult,'SRResult');\n    var srEntry = document.createElement('div');\n    setClassAttr(srEntry,'SREntry');\n    var srLink = document.createElement('a');\n    srLink.setAttribute('id','Item'+e);\n    setKeyActions(srLink,'return searchResults.Nav(event,'+e+')');\n    setClassAttr(srLink,'SRSymbol');\n    srLink.innerHTML = searchData[e][1][0];\n    srEntry.appendChild(srLink);\n    if (searchData[e][1].length==2) // single result\n    {\n      srLink.setAttribute('href',searchData[e][1][1][0]);\n      if (searchData[e][1][1][1])\n      {\n       srLink.setAttribute('target','_parent');\n      }\n      var srScope = document.createElement('span');\n      setClassAttr(srScope,'SRScope');\n      srScope.innerHTML = searchData[e][1][1][2];\n      srEntry.appendChild(srScope);\n    }\n    else // multiple results\n    {\n      srLink.setAttribute('href','javascript:searchResults.Toggle(\"SR_'+id+'\")');\n      var srChildren = document.createElement('div');\n      setClassAttr(srChildren,'SRChildren');\n      for (var c=0; c<searchData[e][1].length-1; c++)\n      {\n        var srChild = document.createElement('a');\n        srChild.setAttribute('id','Item'+e+'_c'+c);\n        setKeyActions(srChild,'return searchResults.NavChild(event,'+e+','+c+')');\n        setClassAttr(srChild,'SRScope');\n        srChild.setAttribute('href',searchData[e][1][c+1][0]);\n        if (searchData[e][1][c+1][1])\n        {\n         srChild.setAttribute('target','_parent');\n        }\n        srChild.innerHTML = searchData[e][1][c+1][2];\n        srChildren.appendChild(srChild);\n      }\n      srEntry.appendChild(srChildren);\n    }\n    srResult.appendChild(srEntry);\n    results.appendChild(srResult);\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/search/search.js.bak",
    "content": "// Search script generated by doxygen\n// Copyright (C) 2009 by Dimitri van Heesch.\n\n// The code in this file is loosly based on main.js, part of Natural Docs,\n// which is Copyright (C) 2003-2008 Greg Valure\n// Natural Docs is licensed under the GPL.\n\nvar indexSectionsWithContent =\n{\n  0: \"_abcdefghijklmnopqrstuvwxyz\",\n  1: \"a\",\n  2: \"t\",\n  3: \"abcdefhimnqstu\",\n  4: \"_acdgilmorstw\",\n  5: \"abcdefgiklmnoprstvwxyz\",\n  6: \"fqs\",\n  7: \"a\",\n  8: \"a\",\n  9: \"_abcdefghilmnopqrstuvx\",\n  10: \"abcdefghijklmnpqrstvw\",\n  11: \"cdr\"\n};\n\nvar indexSectionNames =\n{\n  0: \"all\",\n  1: \"classes\",\n  2: \"namespaces\",\n  3: \"files\",\n  4: \"functions\",\n  5: \"variables\",\n  6: \"typedefs\",\n  7: \"enums\",\n  8: \"enumvalues\",\n  9: \"defines\",\n  10: \"groups\",\n  11: \"pages\"\n};\n\nfunction convertToId(search)\n{\n  var result = '';\n  for (i=0;i<search.length;i++)\n  {\n    var c = search.charAt(i);\n    var cn = c.charCodeAt(0);\n    if (c.match(/[a-z0-9\\u0080-\\uFFFF]/))\n    {\n      result+=c;\n    }\n    else if (cn<16) \n    {\n      result+=\"_0\"+cn.toString(16);\n    }\n    else \n    {\n      result+=\"_\"+cn.toString(16);\n    }\n  }\n  return result;\n}\n\nfunction getXPos(item)\n{\n  var x = 0;\n  if (item.offsetWidth)\n  {\n    while (item && item!=document.body)\n    {\n      x   += item.offsetLeft;\n      item = item.offsetParent;\n    }\n  }\n  return x;\n}\n\nfunction getYPos(item)\n{\n  var y = 0;\n  if (item.offsetWidth)\n  {\n     while (item && item!=document.body)\n     {\n       y   += item.offsetTop;\n       item = item.offsetParent;\n     }\n  }\n  return y;\n}\n\n/* A class handling everything associated with the search panel.\n\n   Parameters:\n   name - The name of the global variable that will be \n          storing this instance.  Is needed to be able to set timeouts.\n   resultPath - path to use for external files\n*/\nfunction SearchBox(name, resultsPath, inFrame, label)\n{\n  if (!name || !resultsPath) {  alert(\"Missing parameters to SearchBox.\"); }\n   \n  // ---------- Instance variables\n  this.name                  = name;\n  this.resultsPath           = resultsPath;\n  this.keyTimeout            = 0;\n  this.keyTimeoutLength      = 500;\n  this.closeSelectionTimeout = 300;\n  this.lastSearchValue       = \"\";\n  this.lastResultsPage       = \"\";\n  this.hideTimeout           = 0;\n  this.searchIndex           = 0;\n  this.searchActive          = false;\n  this.insideFrame           = inFrame;\n  this.searchLabel           = label;\n\n  // ----------- DOM Elements\n\n  this.DOMSearchField = function()\n  {  return document.getElementById(\"MSearchField\");  }\n\n  this.DOMSearchSelect = function()\n  {  return document.getElementById(\"MSearchSelect\");  }\n\n  this.DOMSearchSelectWindow = function()\n  {  return document.getElementById(\"MSearchSelectWindow\");  }\n\n  this.DOMPopupSearchResults = function()\n  {  return document.getElementById(\"MSearchResults\");  }\n\n  this.DOMPopupSearchResultsWindow = function()\n  {  return document.getElementById(\"MSearchResultsWindow\");  }\n\n  this.DOMSearchClose = function()\n  {  return document.getElementById(\"MSearchClose\"); }\n\n  this.DOMSearchBox = function()\n  {  return document.getElementById(\"MSearchBox\");  }\n\n  // ------------ Event Handlers\n\n  // Called when focus is added or removed from the search field.\n  this.OnSearchFieldFocus = function(isActive)\n  {\n    this.Activate(isActive);\n  }\n\n  this.OnSearchSelectShow = function()\n  {\n    var searchSelectWindow = this.DOMSearchSelectWindow();\n    var searchField        = this.DOMSearchSelect();\n\n    if (this.insideFrame)\n    {\n      var left = getXPos(searchField);\n      var top  = getYPos(searchField);\n      left += searchField.offsetWidth + 6;\n      top += searchField.offsetHeight;\n\n      // show search selection popup\n      searchSelectWindow.style.display='block';\n      left -= searchSelectWindow.offsetWidth;\n      searchSelectWindow.style.left =  left + 'px';\n      searchSelectWindow.style.top  =  top  + 'px';\n    }\n    else\n    {\n      var left = getXPos(searchField);\n      var top  = getYPos(searchField);\n      top += searchField.offsetHeight;\n\n      // show search selection popup\n      searchSelectWindow.style.display='block';\n      searchSelectWindow.style.left =  left + 'px';\n      searchSelectWindow.style.top  =  top  + 'px';\n    }\n\n    // stop selection hide timer\n    if (this.hideTimeout) \n    {\n      clearTimeout(this.hideTimeout);\n      this.hideTimeout=0;\n    }\n    return false; // to avoid \"image drag\" default event\n  }\n\n  this.OnSearchSelectHide = function()\n  {\n    this.hideTimeout = setTimeout(this.name +\".CloseSelectionWindow()\",\n                                  this.closeSelectionTimeout);\n  }\n\n  // Called when the content of the search field is changed.\n  this.OnSearchFieldChange = function(evt)\n  {\n    if (this.keyTimeout) // kill running timer\n    {\n      clearTimeout(this.keyTimeout);\n      this.keyTimeout = 0;\n    }\n\n    var e  = (evt) ? evt : window.event; // for IE\n    if (e.keyCode==40 || e.keyCode==13)\n    {\n      if (e.shiftKey==1)\n      {\n        this.OnSearchSelectShow();\n        var win=this.DOMSearchSelectWindow(); \n        for (i=0;i<win.childNodes.length;i++)\n        {\n          var child = win.childNodes[i]; // get span within a\n          if (child.className=='SelectItem')\n          {\n            child.focus();\n            return;\n          }\n        }\n        return;\n      }\n      else if (window.frames.MSearchResults.searchResults)\n      {\n        var elem = window.frames.MSearchResults.searchResults.NavNext(0);\n        if (elem) elem.focus();\n      }\n    }\n    else if (e.keyCode==27) // Escape out of the search field\n    {\n      this.DOMSearchField().blur();\n      this.DOMPopupSearchResultsWindow().style.display = 'none';\n      this.DOMSearchClose().style.display = 'none';\n      this.lastSearchValue = '';\n      this.Activate(false);\n      return;\n    }\n\n    // strip whitespaces\n    var searchValue = this.DOMSearchField().value.replace(/ +/g, \"\");\n\n    if (searchValue != this.lastSearchValue) // search value has changed\n    {\n      if (searchValue != \"\") // non-empty search\n      {\n        // set timer for search update\n        this.keyTimeout = setTimeout(this.name + '.Search()',\n                                     this.keyTimeoutLength);\n      }\n      else // empty search field\n      {\n        this.DOMPopupSearchResultsWindow().style.display = 'none';\n        this.DOMSearchClose().style.display = 'none';\n        this.lastSearchValue = '';\n      }\n    }\n  }\n\n  this.SelectItemCount = function(id)\n  {\n    var count=0;\n    var win=this.DOMSearchSelectWindow(); \n    for (i=0;i<win.childNodes.length;i++)\n    {\n      var child = win.childNodes[i]; // get span within a\n      if (child.className=='SelectItem')\n      {\n        count++;\n      }\n    }\n    return count;\n  }\n\n  this.SelectItemSet = function(id)\n  {\n    var i,j=0;\n    var win=this.DOMSearchSelectWindow(); \n    for (i=0;i<win.childNodes.length;i++)\n    {\n      var child = win.childNodes[i]; // get span within a\n      if (child.className=='SelectItem')\n      {\n        var node = child.firstChild;\n        if (j==id)\n        {\n          node.innerHTML='&#8226;';\n        }\n        else\n        {\n          node.innerHTML='&#160;';\n        }\n        j++;\n      }\n    }\n  }\n\n  // Called when an search filter selection is made.\n  // set item with index id as the active item\n  this.OnSelectItem = function(id)\n  {\n    this.searchIndex = id;\n    this.SelectItemSet(id);\n    var searchValue = this.DOMSearchField().value.replace(/ +/g, \"\");\n    if (searchValue!=\"\" && this.searchActive) // something was found -> do a search\n    {\n      this.Search();\n    }\n  }\n\n  this.OnSearchSelectKey = function(evt)\n  {\n    var e = (evt) ? evt : window.event; // for IE\n    if (e.keyCode==40 && this.searchIndex<this.SelectItemCount()) // Down\n    {\n      this.searchIndex++;\n      this.OnSelectItem(this.searchIndex);\n    }\n    else if (e.keyCode==38 && this.searchIndex>0) // Up\n    {\n      this.searchIndex--;\n      this.OnSelectItem(this.searchIndex);\n    }\n    else if (e.keyCode==13 || e.keyCode==27)\n    {\n      this.OnSelectItem(this.searchIndex);\n      this.CloseSelectionWindow();\n      this.DOMSearchField().focus();\n    }\n    return false;\n  }\n\n  // --------- Actions\n\n  // Closes the results window.\n  this.CloseResultsWindow = function()\n  {\n    this.DOMPopupSearchResultsWindow().style.display = 'none';\n    this.DOMSearchClose().style.display = 'none';\n    this.Activate(false);\n  }\n\n  this.CloseSelectionWindow = function()\n  {\n    this.DOMSearchSelectWindow().style.display = 'none';\n  }\n\n  // Performs a search.\n  this.Search = function()\n  {\n    this.keyTimeout = 0;\n\n    // strip leading whitespace\n    var searchValue = this.DOMSearchField().value.replace(/^ +/, \"\");\n\n    var code = searchValue.toLowerCase().charCodeAt(0);\n    var idxChar = searchValue.substr(0, 1).toLowerCase();\n    if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair\n    {\n      idxChar = searchValue.substr(0, 2);\n    }\n\n    var resultsPage;\n    var resultsPageWithSearch;\n    var hasResultsPage;\n\n    var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar);\n    if (idx!=-1)\n    {\n       var hexCode=idx.toString(16);\n       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';\n       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);\n       hasResultsPage = true;\n    }\n    else // nothing available for this search term\n    {\n       resultsPage = this.resultsPath + '/nomatches.html';\n       resultsPageWithSearch = resultsPage;\n       hasResultsPage = false;\n    }\n\n    window.frames.MSearchResults.location = resultsPageWithSearch;  \n    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();\n\n    if (domPopupSearchResultsWindow.style.display!='block')\n    {\n       var domSearchBox = this.DOMSearchBox();\n       this.DOMSearchClose().style.display = 'inline';\n       if (this.insideFrame)\n       {\n         var domPopupSearchResults = this.DOMPopupSearchResults();\n         domPopupSearchResultsWindow.style.position = 'relative';\n         domPopupSearchResultsWindow.style.display  = 'block';\n         var width = document.body.clientWidth - 8; // the -8 is for IE :-(\n         domPopupSearchResultsWindow.style.width    = width + 'px';\n         domPopupSearchResults.style.width          = width + 'px';\n       }\n       else\n       {\n         var domPopupSearchResults = this.DOMPopupSearchResults();\n         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;\n         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;\n         domPopupSearchResultsWindow.style.display = 'block';\n         left -= domPopupSearchResults.offsetWidth;\n         domPopupSearchResultsWindow.style.top     = top  + 'px';\n         domPopupSearchResultsWindow.style.left    = left + 'px';\n       }\n    }\n\n    this.lastSearchValue = searchValue;\n    this.lastResultsPage = resultsPage;\n  }\n\n  // -------- Activation Functions\n\n  // Activates or deactivates the search panel, resetting things to \n  // their default values if necessary. \n  this.Activate = function(isActive)\n  {\n    if (isActive || // open it\n        this.DOMPopupSearchResultsWindow().style.display == 'block' \n       )\n    {\n      this.DOMSearchBox().className = 'MSearchBoxActive';\n\n      var searchField = this.DOMSearchField();\n\n      if (searchField.value == this.searchLabel) // clear \"Search\" term upon entry\n      {  \n        searchField.value = ''; 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 \n        }\n        else if (element.nextSibling)\n        {  \n           element = element.nextSibling;  \n        }\n        else\n        {\n          do\n          {\n            element = element.parentNode;\n          }\n          while (element && element!=parentElement && !element.nextSibling);\n\n          if (element && element!=parentElement)\n          {  \n            element = element.nextSibling;  \n          }\n        }\n      }\n    }\n\n    this.Toggle = function(id)\n    {\n      var element = this.FindChildElement(id);\n      if (element)\n      {\n        if (element.style.display == 'block')\n        {\n          element.style.display = 'none';\n        }\n        else\n        {\n          element.style.display = 'block';\n        }\n      }\n    }\n\n    // Searches for the passed string.  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  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__biquad__casd__df1__inst__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__biquad__casd__df1__inst__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__biquad__casd__df1__inst__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__biquad__casd__df1__inst__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__biquad__casd__df1__inst__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__biquad__casd__df1__inst__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__instance__f64.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__f64.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__f64.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__radix2__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix2__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix2__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__radix2__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix2__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix2__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__radix2__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix2__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix2__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__radix2__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix2__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix2__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__radix4__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix4__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix4__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__radix4__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix4__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix4__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__radix4__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix4__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix4__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__cfft__radix4__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix4__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__cfft__radix4__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__dct4__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__dct4__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__dct4__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__dct4__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__dct4__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__dct4__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__dct4__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__dct4__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__dct4__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__decimate__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__decimate__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__decimate__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__decimate__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__decimate__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__decimate__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__decimate__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__decimate__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__decimate__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__instance__f64.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__f64.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__f64.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__instance__q7.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__q7.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__instance__q7.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__interpolate__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__interpolate__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__interpolate__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__interpolate__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__interpolate__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__interpolate__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__interpolate__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__interpolate__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__interpolate__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__lattice__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__lattice__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__lattice__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__lattice__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__lattice__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__lattice__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__lattice__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__lattice__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__lattice__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__sparse__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__sparse__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__sparse__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__sparse__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__sparse__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__sparse__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__sparse__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__sparse__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__sparse__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__fir__sparse__instance__q7.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__sparse__instance__q7.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__fir__sparse__instance__q7.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__gaussian__naive__bayes__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__gaussian__naive__bayes__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__gaussian__naive__bayes__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__gaussian__naive__bayes__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__gaussian__naive__bayes__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__gaussian__naive__bayes__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__iir__lattice__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__iir__lattice__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__iir__lattice__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__iir__lattice__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__iir__lattice__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__iir__lattice__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__iir__lattice__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__iir__lattice__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__iir__lattice__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__linear__interp__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__linear__interp__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__linear__interp__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__linear__interp__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__linear__interp__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__linear__interp__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__lms__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__lms__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__lms__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__lms__norm__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__norm__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__norm__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__lms__norm__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__norm__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__norm__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__lms__norm__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__norm__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__lms__norm__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__matrix__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__matrix__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__matrix__instance__f64.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__f64.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__f64.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__matrix__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__matrix__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__matrix__instance__q7.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__q7.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__matrix__instance__q7.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__merge__sort__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__merge__sort__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__merge__sort__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__mfcc__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__mfcc__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__mfcc__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__mfcc__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__mfcc__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__mfcc__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__mfcc__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__mfcc__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__mfcc__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__mfcc__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__mfcc__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__mfcc__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__pid__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__pid__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__pid__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__pid__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__pid__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__pid__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__pid__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__pid__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__pid__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__rfft__fast__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__fast__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__fast__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__rfft__fast__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__fast__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__fast__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__rfft__fast__instance__f64.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__fast__instance__f64.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__fast__instance__f64.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__rfft__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__rfft__instance__q15.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__instance__q15.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__instance__q15.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__rfft__instance__q31.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__instance__q31.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__rfft__instance__q31.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__sort__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__sort__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__sort__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__spline__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__spline__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__spline__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__svm__linear__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__linear__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__linear__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__svm__linear__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__linear__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__linear__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__svm__polynomial__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__polynomial__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__polynomial__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__svm__polynomial__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__polynomial__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__polynomial__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__svm__rbf__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__rbf__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__rbf__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__svm__rbf__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__rbf__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__rbf__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__svm__sigmoid__instance__f16.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__sigmoid__instance__f16.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__sigmoid__instance__f16.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/structarm__svm__sigmoid__instance__f32.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__sigmoid__instance__f32.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/structarm__svm__sigmoid__instance__f32.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/support__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/support__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/support__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/support__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/support__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/support__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/svm__defines_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/svm__defines_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/svm__defines_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/svm__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/svm__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/svm__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/svm__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/svm__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/svm__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/tabs.css",
    "content": ".tabs, .tabs1, .tabs2, .tabs3 {\n    background-image: url('tab_b.png');\n    width: 100%;\n    z-index: 101;\n    font-size: 10px;\n}\n\n.tabs1 {\n    background-image: url('tab_topnav.png');\n    font-size: 12px;\n}\n\n.tabs2 {\n    font-size: 10px;\n}\n.tabs3 {\n    font-size: 9px;\n}\n\n.tablist {\n    margin: 0;\n    padding: 0;\n    display: table;\n    line-height: 24px;\n}\n\n.tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_b.png');\n    list-style: none;\n}\n\n.tabs1 .tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_topnav.png');\n    list-style: none;\n}\n\n.tablist a {\n    display: block;\n    padding: 0 20px;\n    font-weight: bold;\n    background-image:url('tab_s.png');\n    background-repeat:no-repeat;\n    background-position:right;\n    color: #283A5D;\n    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n    text-decoration: none;\n    outline: none;\n}\n\n.tabs3 .tablist a {\n    padding: 0 10px;\n}\n\n.tablist a:hover {\n    background-image: url('tab_h.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n    text-decoration: none;\n}\n\n.tablist li.current a {\n    background-image: url('tab_a.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/transform__functions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/transform__functions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/transform__functions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/transform__functions__f16_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/transform__functions__f16_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/transform__functions__f16_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/unionany32x2__t.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/unionany32x2__t.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/unionany32x2__t.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/unionany32x4__t.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/unionany32x4__t.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/unionany32x4__t.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/DSP/html/utils_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-DSP page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-DSP/v1.10.1/utils_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1/utils_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-DSP/v1.10.1\">CMSIS-DSP resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Doxygen_Templates/DoxygenLayout_forUser.xml",
    "content": "<doxygenlayout version=\"1.0\">\n  <!-- Navigation index tabs for HTML output -->\n  <navindex>\n    <tab type=\"mainpage\" visible=\"yes\" title=\"\"/>\n    <tab type=\"pages\" visible=\"yes\" title=\"Usage and Description\" intro=\"\"/>\n    <tab type=\"modules\" visible=\"yes\" title=\"Reference\" intro=\"\"/>\n    <tab type=\"namespaces\" visible=\"no\" title=\"Namespaces\">\n      <tab type=\"namespacelist\" visible=\"no\" title=\"\" intro=\"\"/>\n      <tab type=\"namespacemembers\" visible=\"no\" title=\"\" intro=\"\"/>\n    </tab>\n    <tab type=\"classes\" visible=\"no\" title=\"Data Structures\">\n      <tab type=\"classlist\" visible=\"yes\" title=\"\" intro=\"\"/>\n      <tab type=\"classindex\" visible=\"$ALPHABETICAL_INDEX\" title=\"\"/> \n      <tab type=\"hierarchy\" visible=\"yes\" title=\"\" intro=\"\"/>\n      <tab type=\"classmembers\" visible=\"yes\" title=\"\" intro=\"\"/>\n    </tab>\n    <tab type=\"files\" visible=\"no\" title=\"Files\">\n      <tab type=\"filelist\" visible=\"no\" title=\"\" intro=\"\"/>\n      <tab type=\"globals\" visible=\"no\" title=\"\" intro=\"\"/>\n    </tab>\n    <tab type=\"examples\" visible=\"no\" title=\"\" intro=\"\"/>  \n  </navindex>\n\n  <!-- Layout definition for a class page -->\n  <class>\n    <briefdescription visible=\"yes\"/>\n    <includes visible=\"$SHOW_INCLUDE_FILES\"/>\n    <inheritancegraph visible=\"$CLASS_GRAPH\"/>\n    <collaborationgraph visible=\"$COLLABORATION_GRAPH\"/>\n    <allmemberslink visible=\"yes\"/>\n    <memberdecl>\n      <nestedclasses visible=\"yes\" title=\"\"/>\n      <publictypes title=\"\"/>\n      <publicslots title=\"\"/>\n      <signals title=\"\"/>\n      <publicmethods title=\"\"/>\n      <publicstaticmethods title=\"\"/>\n      <publicattributes title=\"\"/>\n      <publicstaticattributes title=\"\"/>\n      <protectedtypes title=\"\"/>\n      <protectedslots title=\"\"/>\n      <protectedmethods title=\"\"/>\n      <protectedstaticmethods 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    "content": "/* The standard CSS for doxygen */\n\nbody, table, div, p, dl {\n\tfont-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\n\tfont-size: 13px;\n\tline-height: 1.3;\n}\n\n/* CMSIS styles */\n\n.style1 {\n\t\ttext-align: center;\n}\n.style2 {\n\t\tcolor: #0000FF;\n\t\tfont-weight: normal;\n}\n.style3 {\n\t\ttext-align: left;\n}\n.style4 {\n\t\tcolor: #008000;\n}\n.style5 {\n\t\tcolor: #0000FF;\n}\n.style6 {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n.mand {\n\t\tcolor: #0000FF;\n}\n.opt {\n\t\tcolor: #008000;\n}\n.cond {\n\t\tcolor: #990000;\n}\n\n.choice \n{\n\tbackground-color:#F7F9D0;\n}\n.seq \n{\n\tbackground-color:#C9DECB;\n}\n.group1\n{\n\tbackground-color:#F8F1F1;\n}\n.group2\n{\n\tbackground-color:#DCEDEA;\n}\n\n\nul ul {\n\t\tlist-style-type: disc;\n}\n\nul ul ul {\n\t\tlist-style-type: disc;\n}\n\nul.hierarchy {\n\t\tcolor: green;\n}\n\nem {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n\n\n\n/*  CMSIS Tables */\ntable.cmtab1 {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: justify;\n\twidth:70%;\n}\n\nth.cmtab1 {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n\theight: 28px;\n}\n\ntd.cmtab1 {\n\tpadding:1px;\n\ttext-align: left;\n}\n\ntable.cmtable {\n\tborder-collapse:collapse;\n\ttext-align: justify;\n}\n\ntable.cmtable td, table.cmtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.cmtable th {\n\tbackground-color: #EBEFF6;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n\ttext-align:left;\n}\n\ntd.MonoTxt {\n\tfont-family:\"Arial monospaced for SAP\";\n}\n\ntd.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.h2 \n{\n\tfont-size: 120%;\n\tfont-weight: bold;\n}\n\ndiv.new\n{\n\tbackground-color:#ccffcc; /* light green */\n}\n\ndiv.mod\n{\n\tbackground-color:#ffe6cc;  /* light amber */\n}\n\ndiv.del\n{\n\tbackground-color:#ffcccc;  /* light red */\n}\n\n/* @group Heading Levels */\n\nh1 {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2 {\n\tfont-size: 120%;\n}\n\nh3 {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3A568E;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4464A5;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9AAED5;\n\tcolor: #ffffff;\n\tborder: 1px double #849CCC;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: 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11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 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#FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 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right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4464A5;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Doxygen_Templates/cmsis_dap_header.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<meta http-equiv=\"Content-Type\" content=\"text/xhtml;charset=UTF-8\"/>\n<meta http-equiv=\"X-UA-Compatible\" content=\"IE=9\"/>\n<!--BEGIN PROJECT_NAME--><title>$projectname: $title</title><!--END PROJECT_NAME-->\n<!--BEGIN !PROJECT_NAME--><title>$title</title><!--END !PROJECT_NAME-->\n<link href=\"$relpath$tabs.css\" rel=\"stylesheet\" type=\"text/css\"/>\n<script type=\"text/javascript\" src=\"$relpath$jquery.js\"></script>\n<script type=\"text/javascript\" src=\"$relpath$dynsections.js\"></script>\n$treeview\n$search\n$mathjax\n<link href=\"$relpath$cmsis.css\" rel=\"stylesheet\" type=\"text/css\" />\n</head>\n<body>\n<div id=\"top\"><!-- do not remove this div, it is closed by doxygen! -->\n\n<!--BEGIN TITLEAREA-->\n<div id=\"titlearea\">\n<table cellspacing=\"0\" cellpadding=\"0\">\n <tbody>\n <tr style=\"height: 46px;\">\n  <!--BEGIN PROJECT_LOGO-->\n  <td id=\"projectlogo\"><img alt=\"Logo\" src=\"$relpath$$projectlogo\"/></td>\n  <!--END PROJECT_LOGO-->\n  <!--BEGIN PROJECT_NAME-->\n  <td style=\"padding-left: 0.5em;\">\n   <div id=\"projectname\">$projectname\n   <!--BEGIN PROJECT_NUMBER-->&#160;<span id=\"projectnumber\">$projectnumber</span><!--END PROJECT_NUMBER-->\n   </div>\n   <!--BEGIN PROJECT_BRIEF--><div id=\"projectbrief\">$projectbrief</div><!--END PROJECT_BRIEF-->\n  </td>\n  <!--END PROJECT_NAME-->\n  <!--BEGIN !PROJECT_NAME-->\n   <!--BEGIN PROJECT_BRIEF-->\n    <td style=\"padding-left: 0.5em;\">\n    <div id=\"projectbrief\">$projectbrief</div>\n    </td>\n   <!--END PROJECT_BRIEF-->\n  <!--END !PROJECT_NAME-->\n  <!--BEGIN DISABLE_INDEX-->\n   <!--BEGIN SEARCHENGINE-->\n   <td>$searchbox</td>\n   <!--END SEARCHENGINE-->\n  <!--END DISABLE_INDEX-->\n </tr>\n </tbody>\n</table>\n</div>\n<!--END TITLEAREA-->\n<!-- end header part -->\n<div id=\"CMSISnav\" class=\"tabs1\">\n    <ul class=\"tablist\">\n      <li class=\"current\"><a href=\"../../DAP/html/index.html\"><span>DAP</span></a></li>\n    </ul>\n</div>\n"
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Doxygen_Templates/cmsis_footer.html",
    "content": "<!-- start footer part -->\n<!--BEGIN GENERATE_TREEVIEW-->\n<div id=\"nav-path\" class=\"navpath\"><!-- id is needed for treeview function! -->\n  <ul>\n    $navpath\n    <li class=\"footer\">\n      <script type=\"text/javascript\">\n        <!--\n        writeFooter.call(this);\n        //-->\n      </script>    \n    </li>\n  </ul>\n</div>\n<!--END GENERATE_TREEVIEW-->\n<!--BEGIN !GENERATE_TREEVIEW-->\n<!--END !GENERATE_TREEVIEW-->\n</body>\n</html>\n"
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Doxygen_Templates/cmsis_footer.js",
    "content": "function writeFooter()  {\n    document.write('Generated on {datetime} for {projectName} {projectNumber} by Arm Ltd. All rights reserved.');\n};\n"
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Doxygen_Templates/navtree.css",
    "content": "#nav-tree .children_ul {\n  margin:0;\n  padding:4px;\n}\n\n#nav-tree ul {\n  list-style:none outside none;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree li {\n  white-space:nowrap;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .plus {\n  margin:0px;\n}\n\n#nav-tree .selected {\n  background-image: url('tab_a.png');\n  background-repeat:repeat-x;\n  color: #fff;\n  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n\n#nav-tree img {\n  margin:0px;\n  padding:0px;\n  border:0px;\n  vertical-align: middle;\n}\n\n#nav-tree a {\n  text-decoration:none;\n  padding:0px;\n  margin:0px;\n  outline:none;\n}\n\n#nav-tree .label {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .label a {\n  padding:2px;\n}\n\n#nav-tree .selected a {\n  text-decoration:none;\n  padding:2px;\n  margin:0px;\n  color:#fff;\n}\n\n#nav-tree .children_ul {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .item {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree {\n  padding: 0px 0px;\n  background-color: #FAFAFF; \n  font-size:14px;\n  overflow:auto;\n}\n\n#doc-content {\n  overflow:auto;\n  display:block;\n  padding:0px;\n  margin:0px;\n}\n\n#side-nav {\n  padding:0 6px 0 0;\n  margin: 0px;\n  display:block;\n  position: absolute;\n  left: 0px;\n  width: 300px;\n}\n\n.ui-resizable .ui-resizable-handle {\n  display:block;\n}\n\n.ui-resizable-e {\n  background:url(\"ftv2splitbar.png\") repeat scroll right center transparent;\n  cursor:e-resize;\n  height:100%;\n  right:0;\n  top:0;\n  width:6px;\n}\n\n.ui-resizable-handle {\n  display:none;\n  font-size:0.1px;\n  position:absolute;\n  z-index:1;\n}\n\n#nav-tree-contents {\n  margin: 6px 0px 0px 0px;\n}\n\n#nav-tree {\n  background-image:url('nav_h.png');\n  background-repeat:repeat-x;\n  background-color: #F9FAFC;\n}\n\n\n\n"
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    "content": "var strgURL =   location.pathname;                      // path of current component\n\n// constuctor for the array of objects\nfunction tabElement(id, folderName, tabTxt )  {\n\tthis.id = id;                                       // elementID as needed in html; \n\tthis.folderName = folderName;                       // folder name of the component \n    this.tabTxt = tabTxt;                               // Text displayed as menu on the web\n\tthis.currentListItem = '<li id=\"' + this.id + '\" class=\"current\"> <a href=\"../..' + this.folderName + 'index.html\"><span>' + this.tabTxt + '</span></a></li>';\n\tthis.listItem = '<li id=\"' + this.id + '\"> <a href=\"../..' + this.folderName + 'index.html\"><span>' + this.tabTxt + '</span></a></li>';\n};\n\n// array of objects\nvar arr = [];\n\n// fill array\n arr.push( new tabElement( \"GEN\",     \"/General/html/\",     \"General\")   );\n arr.push( new tabElement( \"CORE_A\",  \"/Core_A/html/\",      \"Core(A)\")   );\n arr.push( new tabElement( \"CORE_M\",  \"/Core/html/\",        \"Core(M)\")   );\n arr.push( new tabElement( \"DRV\",     \"/Driver/html/\",      \"Driver\")    );\n arr.push( new tabElement( \"DSP&ML\",  \"/DSP/html/\",         \"DSP\")       );\n arr.push( new tabElement( \"NN\",      \"/NN/html/\",          \"NN\")        );\n arr.push( new tabElement( \"RTOSv1\",  \"/RTOS/html/\",        \"RTOS v1\")   );\n arr.push( new tabElement( \"RTOSv2\",  \"/RTOS2/html/\",       \"RTOS v2\")   );\n arr.push( new tabElement( \"PACK\",    \"/Pack/html/\",        \"Pack\")      );\n arr.push( new tabElement( \"Build\",   \"/Build/html/\",       \"Build\")     );\n arr.push( new tabElement( \"SVD\",     \"/SVD/html/\",         \"SVD\")       );\n arr.push( new tabElement( \"DAP\",     \"/DAP/html/\",         \"DAP\")       );\n arr.push( new tabElement( \"ZONE\",    \"/Zone/html/\",        \"Zone\")      );\n \n// write tabs\n// called from the header file.\nfunction writeComponentTabs()  {\n  for ( var i=0; i < arr.length; i++ ) {\n    if (strgURL.search(arr[i].folderName) > 0) {                    // if this is the current folder\n      document.write(arr[i].currentListItem);                       // then print and hightlight the tab\n    } else {                                                      \n      document.write(arr[i].listItem);                              // else, print the tab\n    }                                                             \n  }\n};\n"
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    "content": ".tabs, .tabs1, .tabs2, .tabs3 {\n    background-image: url('tab_b.png');\n    width: 100%;\n    z-index: 101;\n    font-size: 10px;\n}\n\n.tabs1 {\n    background-image: url('tab_topnav.png');\n    font-size: 12px;\n}\n\n.tabs2 {\n    font-size: 10px;\n}\n.tabs3 {\n    font-size: 9px;\n}\n\n.tablist {\n    margin: 0;\n    padding: 0;\n    display: table;\n    line-height: 24px;\n}\n\n.tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_b.png');\n    list-style: none;\n}\n\n.tabs1 .tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_topnav.png');\n    list-style: none;\n}\n\n.tablist a {\n    display: block;\n    padding: 0 20px;\n    font-weight: bold;\n    background-image:url('tab_s.png');\n    background-repeat:no-repeat;\n    background-position:right;\n    color: #283A5D;\n    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n    text-decoration: none;\n    outline: none;\n}\n\n.tabs3 .tablist a {\n    padding: 0 10px;\n}\n\n.tablist a:hover {\n    background-image: url('tab_h.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n    text-decoration: none;\n}\n\n.tablist li.current a {\n    background-image: url('tab_a.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n"
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/Driver.dxy",
    "content": "# Doxyfile 1.8.6\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a double hash (##) is considered a comment and is placed in\n# front of the TAG it is preceding.\n#\n# All text after a single hash (#) is considered a comment and will be ignored.\n# The format is:\n# TAG = value [value, ...]\n# For lists, items can also be appended using:\n# TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\\\" \\\").\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the config file\n# that follow. The default is UTF-8 which is also the encoding used for all text\n# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv\n# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv\n# for the list of possible encodings.\n# The default value is: UTF-8.\n\nDOXYFILE_ENCODING      = UTF-8\n\n# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by\n# double-quotes, unless you are using Doxywizard) that should identify the\n# project for which the documentation is generated. This name is used in the\n# title of most generated pages and in a few other places.\n# The default value is: My Project.\n\nPROJECT_NAME           = \"CMSIS-Driver\"\n\n# The PROJECT_NUMBER tag can be used to enter a project or revision number. This\n# could be handy for archiving the generated documentation or if some version\n# control system is used.\n\nPROJECT_NUMBER         = \"Version 2.8.0\"\n\n# Using the PROJECT_BRIEF tag one can provide an optional one line description\n# for a project that appears at the top of each page and should give viewer a\n# quick idea about the purpose of the project. Keep the description short.\n\nPROJECT_BRIEF          = \"Peripheral Interface for Middleware and Application Code\"\n\n# With the PROJECT_LOGO tag one can specify an logo or icon that is included in\n# the documentation. The maximum height of the logo should not exceed 55 pixels\n# and the maximum width should not exceed 200 pixels. Doxygen will copy the logo\n# to the output directory.\n\nPROJECT_LOGO           = ../Doxygen_Templates/CMSIS_Logo_Final.png\n\n# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path\n# into which the generated documentation will be written. If a relative path is\n# entered, it will be relative to the location where doxygen was started. If\n# left blank the current directory will be used.\n\nOUTPUT_DIRECTORY       = ../../Documentation/Driver\n\n# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-\n# directories (in 2 levels) under the output directory of each output format and\n# will distribute the generated files over these directories. Enabling this\n# option can be useful when feeding doxygen a huge amount of source files, where\n# putting all generated files in the same directory would otherwise causes\n# performance problems for the file system.\n# The default value is: NO.\n\nCREATE_SUBDIRS         = NO\n\n# The OUTPUT_LANGUAGE tag is used to specify the language in which all\n# documentation generated by doxygen is written. Doxygen will use this\n# information to generate all constant output in the proper language.\n# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,\n# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),\n# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,\n# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),\n# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,\n# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,\n# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,\n# Ukrainian and Vietnamese.\n# The default value is: English.\n\nOUTPUT_LANGUAGE        = English\n\n# If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member\n# descriptions after the members that are listed in the file and class\n# documentation (similar to Javadoc). Set to NO to disable this.\n# The default value is: YES.\n\nBRIEF_MEMBER_DESC      = YES\n\n# If the REPEAT_BRIEF tag is set to YES doxygen will prepend the brief\n# description of a member or function before the detailed description\n#\n# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the\n# brief descriptions will be completely suppressed.\n# The default value is: YES.\n\nREPEAT_BRIEF           = YES\n\n# This tag implements a quasi-intelligent brief description abbreviator that is\n# used to form the text in various listings. Each string in this list, if found\n# as the leading text of the brief description, will be stripped from the text\n# and the result, after processing the whole list, is used as the annotated\n# text. Otherwise, the brief description is used as-is. If left blank, the\n# following values are used ($name is automatically replaced with the name of\n# the entity):The $name class, The $name widget, The $name file, is, provides,\n# specifies, contains, represents, a, an and the.\n\nABBREVIATE_BRIEF       = \"The $name class\" \\\n                         \"The $name widget\" \\\n                         \"The $name file\" \\\n                         is \\\n                         provides \\\n                         specifies \\\n                         contains \\\n                         represents \\\n                         a \\\n                         an \\\n                         the\n\n# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then\n# doxygen will generate a detailed section even if there is only a brief\n# description.\n# The default value is: NO.\n\nALWAYS_DETAILED_SEC    = NO\n\n# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all\n# inherited members of a class in the documentation of that class as if those\n# members were ordinary class members. Constructors, destructors and assignment\n# operators of the base classes will not be shown.\n# The default value is: NO.\n\nINLINE_INHERITED_MEMB  = NO\n\n# If the FULL_PATH_NAMES tag is set to YES doxygen will prepend the full path\n# before files name in the file list and in the header files. If set to NO the\n# shortest path that makes the file name unique will be used\n# The default value is: YES.\n\nFULL_PATH_NAMES        = NO\n\n# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.\n# Stripping is only done if one of the specified strings matches the left-hand\n# part of the path. The tag can be used to show relative paths in the file list.\n# If left blank the directory from which doxygen is run is used as the path to\n# strip.\n#\n# Note that you can specify absolute paths here, but also relative paths, which\n# will be relative from the directory where doxygen is started.\n# This tag requires that the tag FULL_PATH_NAMES is set to YES.\n\nSTRIP_FROM_PATH        = \n\n# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the\n# path mentioned in the documentation of a class, which tells the reader which\n# header file to include in order to use a class. If left blank only the name of\n# the header file containing the class definition is used. Otherwise one should\n# specify the list of include paths that are normally passed to the compiler\n# using the -I flag.\n\nSTRIP_FROM_INC_PATH    = \n\n# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but\n# less readable) file names. This can be useful is your file systems doesn't\n# support long names like on DOS, Mac, or CD-ROM.\n# The default value is: NO.\n\nSHORT_NAMES            = NO\n\n# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the\n# first line (until the first dot) of a Javadoc-style comment as the brief\n# description. If set to NO, the Javadoc-style will behave just like regular Qt-\n# style comments (thus requiring an explicit @brief command for a brief\n# description.)\n# The default value is: NO.\n\nJAVADOC_AUTOBRIEF      = NO\n\n# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first\n# line (until the first dot) of a Qt-style comment as the brief description. If\n# set to NO, the Qt-style will behave just like regular Qt-style comments (thus\n# requiring an explicit \\brief command for a brief description.)\n# The default value is: NO.\n\nQT_AUTOBRIEF           = NO\n\n# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a\n# multi-line C++ special comment block (i.e. a block of //! or /// comments) as\n# a brief description. This used to be the default behavior. The new default is\n# to treat a multi-line C++ comment block as a detailed description. Set this\n# tag to YES if you prefer the old behavior instead.\n#\n# Note that setting this tag to YES also means that rational rose comments are\n# not recognized any more.\n# The default value is: NO.\n\nMULTILINE_CPP_IS_BRIEF = YES\n\n# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the\n# documentation from any documented member that it re-implements.\n# The default value is: YES.\n\nINHERIT_DOCS           = NO\n\n# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a\n# new page for each member. If set to NO, the documentation of a member will be\n# part of the file/class/namespace that contains it.\n# The default value is: NO.\n\nSEPARATE_MEMBER_PAGES  = NO\n\n# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen\n# uses this value to replace tabs by spaces in code fragments.\n# Minimum value: 1, maximum value: 16, default value: 4.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that act as commands in\n# the documentation. An alias has the form:\n# name=value\n# For example adding\n# \"sideeffect=@par Side Effects:\\n\"\n# will allow you to put the command \\sideeffect (or @sideeffect) in the\n# documentation, which will result in a user-defined paragraph with heading\n# \"Side Effects:\". You can put \\n's in the value part of an alias to insert\n# newlines.\n\nALIASES                = \"token{1}=<span class=\\\"XML-Token\\\">\\1</span>\" \\\n                         \"kbd{1}=\\token{<kbd>\\1</kbd>}\" \\\n                         \"elem{1}=\\b \\<\\1>\"\n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding \"class=itcl::class\"\n# will allow you to use the command class in the itcl::class meaning.\n\nTCL_SUBST              = \n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources\n# only. Doxygen will then generate output that is more tailored for C. For\n# instance, some of the names that are used will be different. The list of all\n# members will be omitted, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_FOR_C  = YES\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or\n# Python sources only. Doxygen will then generate output that is more tailored\n# for that language. For instance, namespaces will be presented as packages,\n# qualified scopes will look different, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources. Doxygen will then generate output that is tailored for Fortran.\n# The default value is: NO.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for VHDL.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given\n# extension. Doxygen has a built-in mapping, but you can override or extend it\n# using this tag. The format is ext=language, where ext is a file extension, and\n# language is one of the parsers supported by doxygen: IDL, Java, Javascript,\n# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C.\n#\n# Note For files without extension you can use no_extension as a placeholder.\n#\n# Note that for custom extensions you also need to set FILE_PATTERNS otherwise\n# the files are not read by doxygen.\n\nEXTENSION_MAPPING      = \n\n# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments\n# according to the Markdown format, which allows for more readable\n# documentation. See http://daringfireball.net/projects/markdown/ for details.\n# The output of markdown processing is further processed by doxygen, so you can\n# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in\n# case of backward compatibilities issues.\n# The default value is: YES.\n\nMARKDOWN_SUPPORT       = YES\n\n# When enabled doxygen tries to link words that correspond to documented\n# classes, or namespaces to their corresponding documentation. Such a link can\n# be prevented in individual cases by by putting a % sign in front of the word\n# or globally by setting AUTOLINK_SUPPORT to NO.\n# The default value is: YES.\n\nAUTOLINK_SUPPORT       = YES\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should set this\n# tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string);\n# versus func(std::string) {}). This also make the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n# The default value is: NO.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n# The default value is: NO.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:\n# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen\n# will parse them like normal C++ but will assume all classes use public instead\n# of private inheritance when no explicit protection keyword is present.\n# The default value is: NO.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate\n# getter and setter methods for a property. Setting this option to YES will make\n# doxygen to replace the get and set methods by a property in the documentation.\n# This will only work if the methods are indeed getting or setting a simple\n# type. If this is not the case, or you want to show the methods anyway, you\n# should set this option to NO.\n# The default value is: YES.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n# The default value is: NO.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES to allow class member groups of the same type\n# (for instance a group of public functions) to be put as a subgroup of that\n# type (e.g. under the Public Functions section). Set it to NO to prevent\n# subgrouping. Alternatively, this can be done per class using the\n# \\nosubgrouping command.\n# The default value is: YES.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions\n# are shown inside the group in which they are included (e.g. using \\ingroup)\n# instead of on a separate page (for HTML and Man pages) or section (for LaTeX\n# and RTF).\n#\n# Note that this feature does not work in combination with\n# SEPARATE_MEMBER_PAGES.\n# The default value is: NO.\n\nINLINE_GROUPED_CLASSES = YES\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions\n# with only public data fields or simple typedef fields will be shown inline in\n# the documentation of the scope in which they are defined (i.e. file,\n# namespace, or group documentation), provided this scope is documented. If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = YES\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = NO\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = NO\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = YES\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = NO\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = YES\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = YES\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = YES\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = YES\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = \n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = YES\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         = \n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = . \\\n                         ../../Driver/Include/Driver_Common.h \\\n                         src/Driver_Common.c \\\n                         ../../Driver/Include/Driver_CAN.h \\\n                         src/Driver_CAN.c \\\n                         ../../Driver/Include/Driver_ETH.h \\\n                         src/Driver_ETH.c \\\n                         ../../Driver/Include/Driver_ETH_MAC.h \\\n                         src/Driver_ETH_MAC.c \\\n                         ../../Driver/Include/Driver_ETH_PHY.h \\\n                         src/Driver_ETH_PHY.c \\\n                         ../../Driver/Include/Driver_I2C.h \\\n                         src/Driver_I2C.c \\\n                         ../../Driver/Include/Driver_MCI.h \\\n                         src/Driver_MCI.c \\\n                         ../../Driver/Include/Driver_NAND.h \\\n                         src/Driver_NAND.c \\\n                         ../../Driver/Include/Driver_Flash.h \\\n                         src/Driver_Flash.c \\\n                         ../../Driver/Include/Driver_SAI.h \\\n                         src/Driver_SAI.c \\\n                         ../../Driver/Include/Driver_SPI.h \\\n                         src/Driver_SPI.c \\\n                         ../../Driver/Include/Driver_Storage.h \\\n                         src/Driver_Storage.c \\\n                         ../../Driver/Include/Driver_USART.h \\\n                         src/Driver_USART.c \\\n                         ../../Driver/Include/Driver_USBD.h \\\n                         src/Driver_USBD.c \\\n                         ../../Driver/Include/Driver_USBH.h \\\n                         src/Driver_USBH.c \\\n                         ../../Driver/Include/Driver_USB.h \\\n                         src/Driver_USB.c \\\n                         ../../Driver/VIO/Include/cmsis_vio.h \\\n                         src/VIO.txt \\\n                         ../../Driver/Include/Driver_WiFi.h \\\n                         src/Driver_WiFi.c \\\n                         src/General.txt\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          = *.c \\\n                         *.cpp \\\n                         *.c++ \\\n                         *.java \\\n                         *.h \\\n                         *.hh \\\n                         *.hpp \\\n                         *.h++ \\\n                         *.inc \\\n                         *.txt\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = NO\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = \n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = YES\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       = \n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        = \n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = ../../Driver/Include \\\n                         ./src\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           = \n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        = \n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS = \n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE = \n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = NO\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = YES\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = NO\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = YES\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          = ARM_\n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        = \n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../Doxygen_Templates/printComponentTabs.js \\\n                         ../Doxygen_Templates/search.css\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 100\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = \n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     = \n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               = \n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   = \n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  = \n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  = \n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           = \n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     = \n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       = \n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       = \n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     = \n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         = \n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           = \n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           = \n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      = \n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    = \n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             = \n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                = \n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen\n# Definitions (see http://autogen.sf.net) file that captures the structure of\n# the code including all documentation. Note that this feature is still\n# experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES doxygen will generate a Perl module\n# file that captures the structure of the code including all documentation.\n#\n# Note that this feature is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES doxygen will generate the necessary\n# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI\n# output from the Perl module output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be nicely\n# formatted so it can be parsed by a human reader. This is useful if you want to\n# understand what is going on. On the other hand, if this tag is set to NO the\n# size of the Perl module output will be much smaller and Perl will parse it\n# just the same.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_PRETTY         = YES\n\n# The names of the make variables in the generated doxyrules.make file are\n# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful\n# so different doxyrules.make files included by the same Makefile don't\n# overwrite each other's variables.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_MAKEVAR_PREFIX = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the preprocessor\n#---------------------------------------------------------------------------\n\n# If the ENABLE_PREPROCESSING tag is set to YES doxygen will evaluate all\n# C-preprocessor directives found in the sources and include files.\n# The default value is: YES.\n\nENABLE_PREPROCESSING   = YES\n\n# If the MACRO_EXPANSION tag is set to YES doxygen will expand all macro names\n# in the source code. If set to NO only conditional compilation will be\n# performed. Macro expansion can be done in a controlled way by setting\n# EXPAND_ONLY_PREDEF to YES.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nMACRO_EXPANSION        = NO\n\n# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then\n# the macro expansion is limited to the macros specified with the PREDEFINED and\n# EXPAND_AS_DEFINED tags.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_ONLY_PREDEF     = NO\n\n# If the SEARCH_INCLUDES tag is set to YES the includes files in the\n# INCLUDE_PATH will be searched if a #include is found.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSEARCH_INCLUDES        = YES\n\n# The INCLUDE_PATH tag can be used to specify one or more directories that\n# contain include files that are not input files but should be processed by the\n# preprocessor.\n# This tag requires that the tag SEARCH_INCLUDES is set to YES.\n\nINCLUDE_PATH           = \n\n# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard\n# patterns (like *.h and *.hpp) to filter out the header-files in the\n# directories. If left blank, the patterns specified with FILE_PATTERNS will be\n# used.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nINCLUDE_FILE_PATTERNS  = \n\n# The PREDEFINED tag can be used to specify one or more macro names that are\n# defined before the preprocessor is started (similar to the -D option of e.g.\n# gcc). The argument of the tag is a list of macros of the form: name or\n# name=definition (no spaces). If the definition and the \"=\" are omitted, \"=1\"\n# is assumed. To prevent a macro definition from being undefined via #undef or\n# recursively expanded use the := operator instead of the = operator.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nPREDEFINED             = __DOXYGEN__\n\n# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this\n# tag can be used to specify a list of macro names that should be expanded. The\n# macro definition that is found in the sources will be used. Use the PREDEFINED\n# tag if you want to use a different macro definition that overrules the\n# definition found in the source code.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_AS_DEFINED      = \n\n# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will\n# remove all refrences to function-like macros that are alone on a line, have an\n# all uppercase name, and do not end with a semicolon. Such function macros are\n# typically used for boiler-plate code, and will confuse the parser if not\n# removed.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSKIP_FUNCTION_MACROS   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to external references\n#---------------------------------------------------------------------------\n\n# The TAGFILES tag can be used to specify one or more tag files. For each tag\n# file the location of the external documentation should be added. The format of\n# a tag file without this location is as follows:\n# TAGFILES = file1 file2 ...\n# Adding location for the tag files is done as follows:\n# TAGFILES = file1=loc1 \"file2 = loc2\" ...\n# where loc1 and loc2 can be relative or absolute paths or URLs. See the\n# section \"Linking to external documentation\" for more information about the use\n# of tag files.\n# Note: Each tag file must have an unique name (where the name does NOT include\n# the path). If a tag file is not located in the directory in which doxygen is\n# run, you must also specify the path to the tagfile here.\n\nTAGFILES               = \n\n# When a file name is specified after GENERATE_TAGFILE, doxygen will create a\n# tag file that is based on the input files it reads. See section \"Linking to\n# external documentation\" for more information about the usage of tag files.\n\nGENERATE_TAGFILE       = \n\n# If the ALLEXTERNALS tag is set to YES all external class will be listed in the\n# class index. If set to NO only the inherited external classes will be listed.\n# The default value is: NO.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in\n# the modules index. If set to NO, only the current project's groups will be\n# listed.\n# The default value is: YES.\n\nEXTERNAL_GROUPS        = YES\n\n# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in\n# the related pages index. If set to NO, only the current project's pages will\n# be listed.\n# The default value is: YES.\n\nEXTERNAL_PAGES         = YES\n\n# The PERL_PATH should be the absolute path and name of the perl script\n# interpreter (i.e. the result of 'which perl').\n# The default file (with absolute path) is: /usr/bin/perl.\n\nPERL_PATH              = /usr/bin/perl\n\n#---------------------------------------------------------------------------\n# Configuration options related to the dot tool\n#---------------------------------------------------------------------------\n\n# If the CLASS_DIAGRAMS tag is set to YES doxygen will generate a class diagram\n# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to\n# NO turns the diagrams off. Note that this option also works with HAVE_DOT\n# disabled, but it is recommended to install and use dot, since it yields more\n# powerful graphs.\n# The default value is: YES.\n\nCLASS_DIAGRAMS         = NO\n\n# You can define message sequence charts within doxygen comments using the \\msc\n# command. Doxygen will then run the mscgen tool (see:\n# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the\n# documentation. The MSCGEN_PATH tag allows you to specify the directory where\n# the mscgen tool resides. If left empty the tool is assumed to be found in the\n# default search path.\n\nMSCGEN_PATH            = \n\n# You can include diagrams made with dia in doxygen documentation. Doxygen will\n# then run dia to produce the diagram and insert it in the documentation. The\n# DIA_PATH tag allows you to specify the directory where the dia binary resides.\n# If left empty dia is assumed to be found in the default search path.\n\nDIA_PATH               = \n\n# If set to YES, the inheritance and collaboration graphs will hide inheritance\n# and usage relations if the target is undocumented or is not a class.\n# The default value is: YES.\n\nHIDE_UNDOC_RELATIONS   = YES\n\n# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is\n# available from the path. This tool is part of Graphviz (see:\n# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent\n# Bell Labs. The other options in this section have no effect if this option is\n# set to NO\n# The default value is: NO.\n\nHAVE_DOT               = NO\n\n# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed\n# to run in parallel. When set to 0 doxygen will base this on the number of\n# processors available in the system. You can set it explicitly to a value\n# larger than 0 to get control over the balance between CPU load and processing\n# speed.\n# Minimum value: 0, maximum value: 32, default value: 0.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_NUM_THREADS        = 0\n\n# When you want a differently looking font n the dot files that doxygen\n# generates you can specify the font name using DOT_FONTNAME. You need to make\n# sure dot is able to find the font, which can be done by putting it in a\n# standard location or by setting the DOTFONTPATH environment variable or by\n# setting DOT_FONTPATH to the directory containing the font.\n# The default value is: Helvetica.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTNAME           = Helvetica\n\n# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of\n# dot graphs.\n# Minimum value: 4, maximum value: 24, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTSIZE           = 10\n\n# By default doxygen will tell dot to use the default font as specified with\n# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set\n# the path where dot can find it using this tag.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTPATH           = \n\n# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for\n# each documented class showing the direct and indirect inheritance relations.\n# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCLASS_GRAPH            = YES\n\n# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a\n# graph for each documented class showing the direct and indirect implementation\n# dependencies (inheritance, containment, and class references variables) of the\n# class with other documented classes.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCOLLABORATION_GRAPH    = YES\n\n# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for\n# groups, showing the direct groups dependencies.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGROUP_GRAPHS           = YES\n\n# If the UML_LOOK tag is set to YES doxygen will generate inheritance and\n# collaboration diagrams in a style similar to the OMG's Unified Modeling\n# Language.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LOOK               = NO\n\n# If the UML_LOOK tag is enabled, the fields and methods are shown inside the\n# class node. If there are many fields or methods and many nodes the graph may\n# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the\n# number of items for each type to make the size more manageable. Set this to 0\n# for no limit. Note that the threshold may be exceeded by 50% before the limit\n# is enforced. So when you set the threshold to 10, up to 15 fields may appear,\n# but if the number exceeds 15, the total amount of fields shown is limited to\n# 10.\n# Minimum value: 0, maximum value: 100, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LIMIT_NUM_FIELDS   = 10\n\n# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and\n# collaboration graphs will show the relations between templates and their\n# instances.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nTEMPLATE_RELATIONS     = NO\n\n# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to\n# YES then doxygen will generate a graph for each documented file showing the\n# direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDE_GRAPH          = YES\n\n# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are\n# set to YES then doxygen will generate a graph for each documented file showing\n# the direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDED_BY_GRAPH      = YES\n\n# If the CALL_GRAPH tag is set to YES then doxygen will generate a call\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable call graphs for selected\n# functions only using the \\callgraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALL_GRAPH             = NO\n\n# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable caller graphs for selected\n# functions only using the \\callergraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALLER_GRAPH           = NO\n\n# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical\n# hierarchy of all classes instead of a textual one.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGRAPHICAL_HIERARCHY    = YES\n\n# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the\n# dependencies a directory has on other directories in a graphical way. The\n# dependency relations are determined by the #include relations between the\n# files in the directories.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDIRECTORY_GRAPH        = YES\n\n# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images\n# generated by dot.\n# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order\n# to make the SVG files visible in IE 9+ (other browsers do not have this\n# requirement).\n# Possible values are: png, jpg, gif and svg.\n# The default value is: png.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_IMAGE_FORMAT       = png\n\n# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to\n# enable generation of interactive SVG images that allow zooming and panning.\n#\n# Note that this requires a modern browser other than Internet Explorer. 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    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_CAN.c",
    "content": "/**\n\\defgroup can_interface_gr CAN Interface\n\\brief Driver API for CAN Bus Peripheral (%Driver_CAN.h)\n\\details\n\nThe <b>Controller Area Network</b> Interface Bus (CAN) implements a multi-master serial bus for connecting\nmicrocontrollers and devices, also known as nodes, to communicate with each other in applications without a host computer.\nCAN is a message-based protocol, designed originally for automotive applications, but meanwhile used also in many other surroundings.\nThe complexity of the node can range from a simple I/O device up to an embedded computer with a CAN interface and sophisticated software.\nThe node may also be a gateway allowing a standard computer to communicate over a USB or Ethernet port to the devices on a CAN network.\nDevices are connected to the bus through a host processor, a CAN controller, and a CAN transceiver.\n\n\nThe CAN Driver API allows to implement CAN Interfaces that conform to the  \n<a href=\"http://www.bosch-semiconductors.com/\" target=\"_blank\">\nCAN specifications available from BOSCH</a>:\n  - CAN 2.0B: CAN Specification 2.0B (released Sep. 1991) which is now superseded by ISO 11898-1.\n  - CAN FD: CAN with Flexible Data Rate introduced in 2012 (released April 17th, 2012).\n\nWikipedia offers more information about the <a href=\"http://en.wikipedia.org/wiki/CAN_bus\" target=\"_blank\"><b>CAN Bus</b></a>.\n\n**CAN 2.0B**\nEvery CAN CMSIS-Driver supports the CAN 2.0B standard\n\nCAN 2.0B supports:\n  - message can contain up to 8 data bytes\n  - bitrates of up to 1Mbits/s\n  - \\ref Remote_Frame requests\n  \n\\anchor CAN_FD\n<b>CAN FD</b>\n\nSupport for CAN FD depends on the hardware.  \nA CMSIS-Driver that supports CAN FD has the capability \\ref ARM_CAN_CAPABILITIES data field \\b fd_mode = \\token{1}, which can be\nretrieved with the function \\ref ARM_CAN_GetCapabilities. \n\nCAN FD supports:\n   - message can contain up to 64 data bytes\n   - faster data transfers with faster bitrate used during the data phase \n\nCAN FD does not support \\ref Remote_Frame requests.\n\n<b>Block Diagram</b>\n\nThe CAN Driver API defines a <b>CAN</b> interface for middleware components. The CAN Driver supports multiple\nnodes, which are able to send and receive messages, but not simultaneously.\n\n\\image html CAN_Node.png  \"CAN Node Schematic\"\n\nCAN API\n-------\n\nThe following header files define the Application Programming Interface (API) for the CAN interface:\n  - \\b %Driver_CAN.h : Driver API for CAN Bus Peripheral\n\nThe driver implementation is a typical part of the Device Family Pack (DFP) that supports the\nperipherals of the microcontroller family.\n\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_CAN : access struct for CAN driver functions\n\n<b>Example Code</b>\n\nThe following example code shows the usage of the CAN interface.\n\n\\code\n\n#include <stdio.h>\n#include <string.h>\n#include \"cmsis_os.h\"\n \n#include \"Driver_CAN.h\"\n \n// CAN Driver Controller selector\n#define  CAN_CONTROLLER         1       // CAN Controller number\n \n#define _CAN_Driver_(n)         Driver_CAN##n\n#define  CAN_Driver_(n)        _CAN_Driver_(n)\nextern   ARM_DRIVER_CAN         CAN_Driver_(CAN_CONTROLLER);\n#define  ptrCAN               (&CAN_Driver_(CAN_CONTROLLER))\n \nuint32_t                        rx_obj_idx  = 0xFFFFFFFFU;\nuint8_t                         rx_data[8];\nARM_CAN_MSG_INFO                rx_msg_info;\nuint32_t                        tx_obj_idx  = 0xFFFFFFFFU;\nuint8_t                         tx_data[8];\nARM_CAN_MSG_INFO                tx_msg_info;\n \nstatic void Error_Handler (void) { while (1); }\n \nvoid CAN_SignalUnitEvent (uint32_t event) {}\n \nvoid CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event) {\n \n  if (obj_idx == rx_obj_idx) {                  // If receive object event\n    if (event == ARM_CAN_EVENT_RECEIVE) {       // If message was received successfully\n      if (ptrCAN->MessageRead(rx_obj_idx, &rx_msg_info, rx_data, 8U) > 0U) {\n                                                // Read received message\n        // process received message ...\n      }\n    }\n  }\n  if (obj_idx == tx_obj_idx) {                  // If transmit object event\n    if (event == ARM_CAN_EVENT_SEND_COMPLETE) { // If message was sent successfully\n      // acknowledge sent message ...\n    }\n  }\n}\n \nint main (void) {\n  ARM_CAN_CAPABILITIES     can_cap;\n  ARM_CAN_OBJ_CAPABILITIES can_obj_cap;\n  int32_t                  status;\n  uint32_t                 i, num_objects;\n \n  can_cap = ptrCAN->GetCapabilities (); // Get CAN driver capabilities\n  num_objects = can_cap.num_objects;    // Number of receive/transmit objects\n \n  status = ptrCAN->Initialize    (CAN_SignalUnitEvent, CAN_SignalObjectEvent);  // Initialize CAN driver\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n \n  status = ptrCAN->PowerControl  (ARM_POWER_FULL);                              // Power-up CAN controller\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n \n  status = ptrCAN->SetMode       (ARM_CAN_MODE_INITIALIZATION);                 // Activate initialization mode\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n \n  status = ptrCAN->SetBitrate    (ARM_CAN_BITRATE_NOMINAL,              // Set nominal bitrate\n                                  100000U,                              // Set bitrate to 100 kbit/s\n                                  ARM_CAN_BIT_PROP_SEG(5U)   |          // Set propagation segment to 5 time quanta\n                                  ARM_CAN_BIT_PHASE_SEG1(1U) |          // Set phase segment 1 to 1 time quantum (sample point at 87.5% of bit time)\n                                  ARM_CAN_BIT_PHASE_SEG2(1U) |          // Set phase segment 2 to 1 time quantum (total bit is 8 time quanta long)\n                                  ARM_CAN_BIT_SJW(1U));                 // Resynchronization jump width is same as phase segment 2\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n \n  for (i = 0U; i < num_objects; i++) {                                          // Find first available object for receive and transmit\n    can_obj_cap = ptrCAN->ObjectGetCapabilities (i);                            // Get object capabilities\n    if      ((rx_obj_idx == 0xFFFFFFFFU) && (can_obj_cap.rx == 1U)) { rx_obj_idx = i; }\n    else if ((tx_obj_idx == 0xFFFFFFFFU) && (can_obj_cap.tx == 1U)) { tx_obj_idx = i; break; }\n  }\n  if ((rx_obj_idx == 0xFFFFFFFFU) || (tx_obj_idx == 0xFFFFFFFFU)) { Error_Handler(); }\n \n  // Set filter to receive messages with extended ID 0x12345678 to receive object\n  status = ptrCAN->ObjectSetFilter(rx_obj_idx, ARM_CAN_FILTER_ID_EXACT_ADD, ARM_CAN_EXTENDED_ID(0x12345678U), 0U);\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n \n  status = ptrCAN->ObjectConfigure(tx_obj_idx, ARM_CAN_OBJ_TX);                 // Configure transmit object\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n \n  status = ptrCAN->ObjectConfigure(rx_obj_idx, ARM_CAN_OBJ_RX);                 // Configure receive object\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n  \n  status = ptrCAN->SetMode (ARM_CAN_MODE_NORMAL);                               // Activate normal operation mode\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n  \n  memset(&tx_msg_info, 0U, sizeof(ARM_CAN_MSG_INFO));                           // Clear message info structure\n  tx_msg_info.id = ARM_CAN_EXTENDED_ID(0x12345678U);                            // Set extended ID for transmit message\n  tx_data[0]     = 0xFFU;                                                       // Initialize transmit data\n  while (1) {\n    tx_data[0]++;                                                               // Increment transmit data\n    status = ptrCAN->MessageSend(tx_obj_idx, &tx_msg_info, tx_data, 1U);        // Send data message with 1 data byte\n    if (status != 1U) { Error_Handler(); }\n    for (i = 0U; i < 1000000U; i++) { __nop(); }                                // Wait a little while\n  }\n}\n\\endcode\n\n\n\\section can_objects CAN Message Objects\n\nThe CMSIS-Driver for the CAN interface provides multiple CAN message objects, which can be seen as individual communication channels.\nThe number of available CAN message objects depends on the CAN peripheral. The function \\ref ARM_CAN_GetCapabilities returns \nthe maximum number of available CAN message objects. The number is encoded in the structure \\ref ARM_CAN_CAPABILITIES in the data field \\em num_objects.\nCAN message objects are addressed with the functions listed below, whereby the parameter \\em obj_idx addresses an individual object.\nThe valid range for \\em obj_idx is \\token{[0 .. (\\em num_objects - 1)]}.\n\nFunction                           | Description\n:----------------------------------|:--------------------------------------------\n\\ref ARM_CAN_ObjectGetCapabilities | Retrieves message object capabilities such as receive, transmit, \\ref Remote_Frame automatic handling and \\ref can_filtering.\n\\ref ARM_CAN_ObjectSetFilter       | Allows to set-up CAN ID filtering for the message object.\n\\ref ARM_CAN_ObjectConfigure       | Allows to configure the message object for receive, transmit or \\ref Remote_Frame automatic handling.\n\\ref ARM_CAN_MessageRead           | Read received message from the message object.\n\\ref ARM_CAN_MessageSend           | Send CAN message or send \\ref Remote_Frame or set CAN message to be sent automatically on reception of matching \\ref Remote_Frame on the message object.\n\\ref ARM_CAN_SignalObjectEvent     | Callback function that signals a message transfer or a received message overrun.\n\nEach CAN message object may have different capabilities. Before using a CAN message object, call the \nfunction \\ref ARM_CAN_ObjectGetCapabilities to verify the available features.\n\n\n\\section can_filtering CAN Message Filtering\n\nThe CMSIS-Driver for the CAN interface supports ID filtering for the receiving message objects. The receiving CAN node examines the identifier \nto decide if it was relevant. This filtering is done by the CAN peripheral according the settings configured with the function \\ref ARM_CAN_ObjectSetFilter.\n\nThe function \\ref ARM_CAN_ObjectGetCapabilities retrieves the filter capabilities of the CAN message objects stored in \\ref ARM_CAN_OBJ_CAPABILITIES.\n\nData Fields                | CAN Messages Object can be filtered with ...\n:--------------------------|:--------------------------------------------\n\\em exact_filtering        | an exact ID value set by using the function \\ref ARM_CAN_ObjectSetFilter with \\em control = \\ref ARM_CAN_FILTER_ID_EXACT_ADD.\n\\em range_filtering        | a range ID value set by using the function \\ref ARM_CAN_ObjectSetFilter with \\em control = \\ref ARM_CAN_FILTER_ID_RANGE_ADD.\n\\em mask_filtering         | a mask ID value set by as using the function \\ref ARM_CAN_ObjectSetFilter with \\em control = \\ref ARM_CAN_FILTER_ID_MASKABLE_ADD.\n\\em multiple_filters       | ... several filters to capture multiple ID values, or ID value ranges.\n\n<b>CAN message filtering using an exact ID</b>\n\nExample: accept in message object #1 only frames with extended ID = 0x1567.\n\\code\n  status = ptrCAN->ObjectSetFilter (1, ARM_CAN_FILTER_ID_EXACT_ADD, ARM_CAN_EXTENDED_ID(0x1567), 0);\n  if (status != ARM_DRIVER_OK) ... // error handling\n\\endcode\n\nExample: accept in message object #2 frames with extended ID = 0x3167 and extended ID = 0x42123.\n\\code\n  status = ptrCAN->ObjectSetFilter (2, ARM_CAN_FILTER_ID_EXACT_ADD, ARM_CAN_EXTENDED_ID(0x3167), 0);\n  if (status != ARM_DRIVER_OK) ... // error handling\n  status = ptrCAN->ObjectSetFilter (2, ARM_CAN_FILTER_ID_EXACT_ADD, ARM_CAN_EXTENDED_ID(0x42123), 0);\n  if (status != ARM_DRIVER_OK) ... // error handling\n\\endcode\n\n<b>CAN message filtering using a range ID</b>\n\nExample: accept in message object #3 only frames with extended ID >= 0x1567 and extended ID <= 0x1577.\n\\code\n  status = ptrCAN->ObjectSetFilter (3, ARM_CAN_FILTER_ID_RANGE_ADD, ARM_CAN_EXTENDED_ID(0x1567), ARM_CAN_EXTENDED_ID(0x1577));\n  if (status != ARM_DRIVER_OK) ... // error handling\n\\endcode\n\n\n<b>CAN message filtering using a mask ID</b>\n\nUsing the function \\ref ARM_CAN_ObjectSetFilter with \\em control = \\ref ARM_CAN_FILTER_ID_MASKABLE_ADD allows to specify with \\em arg a mask value.\n - if a mask bit is \\token{0}, the corresponding \\em ID bit will be accepted, regardless of the value.\n - if a mask bit is \\token{1}, the corresponding \\em ID bit will be compared with the value of the ID filter bit; if they match the message will be accepted otherwise the frame is rejected.\n\nExample: accept in message object #0 only frames with extended IDs 0x1560 to 0x156F.\n\\code\n  status = ptrCAN->ObjectSetFilter (0, ARM_CAN_FILTER_ID_MASKABLE_ADD, ARM_CAN_EXTENDED_ID(0x1560), 0x1FFFFFF0);\n  if (status != ARM_DRIVER_OK) ... // error handling\n\\endcode\n\nExample: accept in message object #2 only frames with extended IDs 0x35603, 0x35613, 0x35623, and 0x35633.\n\\code\n  status = ptrCAN->ObjectSetFilter (2, ARM_CAN_FILTER_ID_MASKABLE_ADD, ARM_CAN_EXTENDED_ID(0x35603), 0x1FFFFFCF);\n  if (status != ARM_DRIVER_OK) ... // error handling\n\\endcode\n\nExample: accept any message in object #4 regardless of the ID.\n\\code\n  status = ptrCAN->ObjectSetFilter (4, ARM_CAN_FILTER_ID_MASKABLE_ADD, ARM_CAN_EXTENDED_ID(0), 0);\n  if (status != ARM_DRIVER_OK) ... // error handling\n\\endcode\n\n\\section Remote_Frame Remote Frame\n\nIn general, data transmission is performed on an autonomous basis with the data source node sending out Data Frames.\n\nHowever, sending a <b>Remote Frame</b> allows a destination node to request the data from the source node.\nThe examples below shows the data exchange using a <b>Remote Transmission Request (RTR)</b>.\n\n<b>Example for automatic Data Message response on RTR</b>\n\nFor automatic data message response on an RTR, the object is configured with the function \\ref ARM_CAN_ObjectConfigure \\em obj_cfg = \\ref ARM_CAN_OBJ_RX_RTR_TX_DATA.\n\nIn this case, the function \\ref ARM_CAN_MessageSend sets a data message that is transmitted when an RTR with a matching CAN ID is received.\nIf  \\ref ARM_CAN_MessageSend was not called before the RTR is received, the response is hardware dependent (either last data message is repeated \nor no data message is sent until \\ref ARM_CAN_MessageSend is called).\n\nAfter data transmission is completed, the driver calls a callback function \\ref ARM_CAN_SignalObjectEvent with \\em event = \\ref ARM_CAN_EVENT_SEND_COMPLETE \nand the related \\em obj_idx.\n\n<b>Example:</b>\n\\code\n  status = ptrCAN->ObjectSetFilter(0, ARM_CAN_FILTER_ID_EXACT_ADD, ARM_CAN_EXTENDED_ID(0x12345678U), 0U);\n  if (status != ARM_DRIVER_OK) ... // error handling\n  status = trCAN->ObjectConfigure(0, ARM_CAN_OBJ_RX_RTR_TX_DATA);\n  if (status != ARM_DRIVER_OK) ... // error handling\n\n  memset(&tx_msg_info, 0, sizeof(ARM_CAN_MSG_INFO));            // Clear transmit message structure\n  tx_msg_info.id  = ARM_CAN_EXTENDED_ID(0x12345678U);           // Set ID of message\n  data_buf[0] = '1';  data_buf[1] = '2';                        // Prepare data to transmit\n  data_buf[2] = '3';  data_buf[3] = '4';\n  data_buf[4] = '5';  data_buf[5] = '6';\n  data_buf[6] = '7';  data_buf[7] = '8';\n  ptrCAN->MessageSend(0, &tx_msg_info, data_buf, 8);            // Start send message that will be triggered on RTR reception\n\\endcode\n\n \n<b>Example for automatic Data Message reception using RTR</b>\n\nFor automatic data message reception on an RTR, the object is configured with the function \\ref ARM_CAN_ObjectConfigure \\em obj_cfg = \\ref ARM_CAN_OBJ_TX_RTR_RX_DATA. \n\nThe receiver or consumer requests data with transmission of an RTR with the \\ref ARM_CAN_MessageSend. This RTR requests from the transmitter or producer to send the data message.\nOnce the data message is received, the driver calls a callback function \\ref ARM_CAN_SignalObjectEvent with \\em event = \\ref ARM_CAN_EVENT_RECEIVE\nand the related \\em obj_idx. The received data message can then be read with the function \\ref ARM_CAN_MessageRead. \n\n<b>Example:</b>\n\\code\n  status = ptrCAN->ObjectSetFilter(0, ARM_CAN_FILTER_ID_EXACT_ADD, ARM_CAN_EXTENDED_ID(0x12345678U), 0U);\n  if (status != ARM_DRIVER_OK) ... // error handling\n  status = ptrCAN->ObjectConfigure(0, ARM_CAN_OBJ_TX_RTR_RX_DATA);\n  if (status != ARM_DRIVER_OK) ... // error handling\n  memset(&tx_msg_info, 0, sizeof(ARM_CAN_MSG_INFO));            // Clear transmit message structure\n  tx_msg_info.id  = ARM_CAN_EXTENDED_ID(0x12345678U);           // Set ID of message\n  tx_msg_info.rtr = 1;                                          // Set RTR flag of message to send RTR\n  tx_msg_info.dlc = 1;                                          // Set data length code of message to 1 to request 1 data byte\n  ptrCAN->MesageSend(0, &tx_msg_info, 0, 0);                    // Send RTR\n\n  // Wait for ARM_CAN_EVENT_RECEIVE\n  ptrCAN->MessageRead(0, &rx_msg_info, data_buf, 8);            // Read received message\n\\endcode\n\n\n@{\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_DRIVER_CAN\n\\details\nThe functions of the CAN are accessed by function pointers exposed by this structure. Refer to \\ref DriverFunctions for overview information.\n\nEach instance of a CAN provides such an access structure.\nThe instance is identified by a postfix number in the symbol name of the access structure, for example:\n - \\b Driver_CAN0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_CAN1 is the name of the access struct of the second instance (no. 1).\n\nA configuration setting in the middleware allows you to connect the middleware to a specific driver instance <b>Driver_CAN<i>n</i></b>.\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_CAN_CAPABILITIES\n\\details\nA CAN driver can be implemented with different capabilities encoded in the data fields of this structure.\n\n<b>Returned by:</b>\n  - \\ref ARM_CAN_GetCapabilities\n\n\\sa \\ref ARM_CAN_OBJ_CAPABILITIES for information about CAN objects.\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_CAN_STATUS\n\\details\nStructure with information about the status of the CAN unit state and errors.\nThe data fields encode the unit bus state, last error code, transmitter error count, and receiver error count.\n\n<b>Returned by:</b>\n  - \\ref ARM_CAN_GetStatus\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_CAN_MSG_INFO\n\\brief      CAN Message Information\n\\details\nStructure with information about the CAN message.\n\nIn CAN mode, the following \\ref ARM_CAN_MSG_INFO data fields are ignored: \\em edl, \\em brs, \\em esi. \\n\nIn CAN FD mode, the following \\ref ARM_CAN_MSG_INFO data field is ignored: \\em rtr.\n\n<b>Parameter for:</b>\n  - \\ref ARM_CAN_MessageSend\n  - \\ref ARM_CAN_MessageRead\n\n\\sa \\ref can_filtering\n\\sa \\ref Remote_Frame\n*****************************************************************************************************************/\n \n/**\n\\typedef    ARM_CAN_SignalUnitEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_CAN_SignalUnitEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_CAN_Initialize\n*******************************************************************************************************************/\n\n/**\n\\typedef    ARM_CAN_SignalObjectEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_CAN_SignalObjectEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_CAN_Initialize\n*******************************************************************************************************************/\n\n/**\n\\defgroup can_status_code_ctrls Status Error Codes\n\\ingroup can_interface_gr\n\\brief Status codes of the CAN driver.\n\\details\n\nThe following callback notification unit events are generated:\n@{\n\\def ARM_CAN_UNIT_STATE_INACTIVE\n\\def ARM_CAN_UNIT_STATE_ACTIVE\n\\def ARM_CAN_UNIT_STATE_PASSIVE\n\\def ARM_CAN_UNIT_STATE_BUS_OFF\n\\def ARM_CAN_LEC_NO_ERROR\n\\def ARM_CAN_LEC_BIT_ERROR\n\\def ARM_CAN_LEC_STUFF_ERROR\n\\def ARM_CAN_LEC_CRC_ERROR\n\\def ARM_CAN_LEC_FORM_ERROR\n\\def ARM_CAN_LEC_ACK_ERROR\n@}\n*******************************************************************************************************************/\n\n/**\n\\defgroup CAN_unit_events CAN Unit Events\n\\ingroup can_interface_gr\n\\brief Callback unit events notified via \\ref ARM_CAN_SignalUnitEvent.\n\\details\nThe CAN driver generates callback unit events that are notified via the function \\ref ARM_CAN_SignalUnitEvent.\n\nThe following callback notification unit events are generated:\n@{\n\\def ARM_CAN_EVENT_UNIT_INACTIVE\n\\sa \\ref ARM_CAN_SignalUnitEvent\n\\def ARM_CAN_EVENT_UNIT_ACTIVE\n\\sa \\ref ARM_CAN_SignalUnitEvent\n\\def ARM_CAN_EVENT_UNIT_WARNING\n\\sa \\ref ARM_CAN_SignalUnitEvent\n\\def ARM_CAN_EVENT_UNIT_PASSIVE\n\\sa \\ref ARM_CAN_SignalUnitEvent\n\\def ARM_CAN_EVENT_UNIT_BUS_OFF\n\\sa \\ref ARM_CAN_SignalUnitEvent\n@}\n*******************************************************************************************************************/\n\n/**\n\\defgroup CAN_events CAN Object Events\n\\brief Callback objects events notified via \\ref ARM_CAN_SignalObjectEvent.\n\\details\nThe CAN driver generates callback objects events that are notified via the function \\ref ARM_CAN_SignalObjectEvent.\n\nThe following callback notification object events are generated:\n@{\n\\def ARM_CAN_EVENT_SEND_COMPLETE\n\\sa \\ref ARM_CAN_SignalObjectEvent\n\\def ARM_CAN_EVENT_RECEIVE\n\\sa \\ref ARM_CAN_SignalObjectEvent\n\\def ARM_CAN_EVENT_RECEIVE_OVERRUN\n\\sa \\ref ARM_CAN_SignalObjectEvent\n@}\n*******************************************************************************************************************/\n\n/**\n\\defgroup can_control CAN Control Codes\n\\ingroup can_interface_gr\n\\brief   Codes to configure the CAN driver.\n\\details\n@{\nThe various CAN control codes define:\n\n  - \\ref can_identifer_ctrls          specify CAN identifier. Refer to \\ref ARM_CAN_ObjectConfigure.\n  - \\ref can_mode_ctrls               control CAN interface operation. Refer to \\ref ARM_CAN_Control.\n  - \\ref can_timeseg_ctrls            specify CAN bit rate and timing. Refer to \\ref ARM_CAN_SetBitrate.\n  - \\ref can_bus_mode_ctrls           specify CAN bus operating mode. Refer to \\ref ARM_CAN_SetMode.\n  - \\ref can_filter_operation_ctrls   specify CAN filter operations.  Refer to \\ref ARM_CAN_ObjectSetFilter.\n  - \\ref can_obj_config_ctrls         specify CAN object configuration modes. Refer to \\ref ARM_CAN_ObjectConfigure.\n*****************************************************************************************************************/\n\n/**\n\\defgroup can_identifer_ctrls CAN Identifier\n\\brief Set object to standard or extended.\n\\details\n\n@{\n\\def ARM_CAN_STANDARD_ID(id)\n\\sa \\ref ARM_CAN_ObjectConfigure\n\\def ARM_CAN_EXTENDED_ID(id)\n\\sa \\ref ARM_CAN_ObjectConfigure\n@}\n*******************************************************************************************************************/\n\n/**\n\\defgroup can_mode_ctrls CAN Operation Codes\n\\brief Set CAN operation modes.\n\\details\n\nThese controls set the CAN operation using the function \\ref ARM_CAN_Control.\n\n@{\n\\def ARM_CAN_SET_FD_MODE\n\\sa \\ref ARM_CAN_Control\n\\def ARM_CAN_ABORT_MESSAGE_SEND\n\\sa \\ref ARM_CAN_Control\n\\def ARM_CAN_ABORT_MESSAGE_SEND\n\\sa \\ref ARM_CAN_Control\n\\def ARM_CAN_CONTROL_RETRANSMISSION\n\\sa \\ref ARM_CAN_Control\n\\def ARM_CAN_SET_TRANSCEIVER_DELAY\n\\sa \\ref ARM_CAN_Control\n\n@}\n*****************************************************************************************************************/\n\n/**\n\\defgroup can_bus_mode_ctrls CAN Bus Communication Mode\n@{\n\\brief Set or initialize the CAN bus\n\\enum ARM_CAN_MODE \n\\details\nThe enumerations below initialize and set the bus communication mode.\n\n<b>Parameter for:</b>\n  - \\ref ARM_CAN_SetMode\n@}\n*/\n\n/**\n\\defgroup can_timeseg_ctrls CAN Bit Timing Codes\n@{\n\\brief Set bit timing\n\\details\nThe following codes are used with the function \\ref ARM_CAN_SetBitrate.\n\n\\def ARM_CAN_BIT_PROP_SEG(x)\n\\sa \\ref ARM_CAN_SetBitrate\n\\def ARM_CAN_BIT_PHASE_SEG1(x)\n\\sa \\ref ARM_CAN_SetBitrate\n\\def ARM_CAN_BIT_PHASE_SEG2(x)\n\\sa \\ref ARM_CAN_SetBitrate\n\\def ARM_CAN_BIT_SJW(x)\n\\sa \\ref ARM_CAN_SetBitrate\n\n*******************************************************************************************************************/\n\n/**\n\\enum ARM_CAN_BITRATE_SELECT \n\\brief Set the bit rate.\n\\details \nProvides the typedef for setting the bit rate. \n\n<b>Parameter for:</b>\n  - \\ref ARM_CAN_SetBitrate\n*******************************************************************************************************************/\n/**\n@}   \n*/\n\n/**\n\\defgroup can_filter_operation_ctrls CAN Filter Operation Codes\n@{\n\\brief Set CAN filter manipulation codes.\n\n\\enum ARM_CAN_FILTER_OPERATION\n\\details\n\n\\b ARM_CAN_FILTER_OPERATION provides the controls for setting the filter type.\nRefer to \\ref can_filtering for details.\n\n<b>Parameter for:</b>\n - \\ref ARM_CAN_ObjectSetFilter\n@}\n*****************************************************************************************************************/\n\n/**\n\\defgroup can_obj_config_ctrls CAN Object Configuration Codes\n@{\n\\brief CAN Object Configuration codes\n\\enum ARM_CAN_OBJ_CONFIG \n\\details \nProvides defined values for the configuration of CAN objects.\n\n<b>Parameter for:</b>\n  - \\ref ARM_CAN_ObjectConfigure\n@}\n**************************************************************************************************************************/\n\n/**\n@}\n*/   /* End Control Code */\n\n/**\n\\struct ARM_CAN_OBJ_CAPABILITIES\n@{\n\\details\nA CAN object can be implemented with different capabilities encoded in the \ndata fields of this structure.\n\n<b>Returned by</b>:\n - \\ref ARM_CAN_ObjectGetCapabilities\n\n\\sa \\ref ARM_CAN_ObjectConfigure\n\\sa \\ref ARM_CAN_MessageSend\n\\sa \\ref ARM_CAN_MessageRead\n\\sa \\ref ARM_CAN_MSG_INFO\n\\sa \\ref can_filtering\n@}\n*****************************************************************************************************************/\n\n\n//\n//   Functions\n//\nARM_DRIVER_VERSION ARM_CAN_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn       ARM_DRIVER_VERSION ARM_CAN_GetVersion (void)\n\\details\nThe function \\b ARM_CAN_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_CAN Driver_CAN0;\nARM_DRIVER_CAN *drv_info;\n\nvoid setup_can (void)  {\n  ARM_DRIVER_VERSION  version;\n\n  drv_info = &Driver_CAN0;\n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*******************************************************************************************************************/\n\nARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void)  {\n  return { 0 };\n}\n/**\n\\fn       ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void)\n\\details\nThe function \\b ARM_CAN_GetCapabilities returns information about the capabilities in this driver implementation.\nThe data fields of the structure \\ref ARM_CAN_CAPABILITIES encode various capabilities.\n\nExample:\n\\code\nextern ARM_DRIVER_CAN Driver_CAN0;\nARM_DRIVER_CAN *drv_info;\n\nvoid read_capabilities (void)  {\n  ARM_CAN_CAPABILITIES drv_capabilities;\n\n  drv_info = &Driver_CAN0;\n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n\n}\n\\endcode\n*******************************************************************************************************************/\n\n\nint32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event, ARM_CAN_SignalObjectEvent_t cb_object_event)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event, ARM_CAN_SignalObjectEvent_t cb_object_event)\n\\details\nThe function \\b initializes the CAN interface.\n\nThe function performs the following operations:\n  - Initializes the resources needed for the CAN interface, for example dynamic memory allocation, RTOS object allocation, and possibly hardware pin configuration.\n  - Registers the \\ref ARM_CAN_SignalUnitEvent callback function.\n  - Registers the \\ref ARM_CAN_SignalObjectEvent callback function.\n\nThe parameter \\em cb_unit_event is a pointer to the \\ref ARM_CAN_SignalUnitEvent callback function; use a NULL pointer\nwhen no callback signals are required.\n\nThe parameter \\em cb_object_event is a pointer to the \\ref ARM_CAN_SignalObjectEvent callback function; use a NULL pointer\nwhen no callback signals are required.\n\n\\b Example:\n - see \\ref can_interface_gr\n\n**************************************************************************************************************************/\n\n\nint32_t ARM_CAN_Uninitialize (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_CAN_Uninitialize (void)\n\\details\nThe function \\b ARM_CAN_Uninitialize de-initializes the resources of the CAN interface.\nIt is called to release the software resources used by the interface such as deallocate any RTOS objects, dynamic memory and pin de-configuration.\n*******************************************************************************************************************/\n\nint32_t ARM_CAN_PowerControl (ARM_POWER_STATE state)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_CAN_PowerControl controls the power modes of the CAN interface.\n\nThe parameter \\em state can be:\n    - ARM_POWER_FULL: Activate clocks and driver functionality as if peripheral was reset.\n    - ARM_POWER_OFF:  Unconditionally put peripheral into non-functional (reset) state.\n    - ARM_POWER_LOW:  Put peripheral into low power consumption state ready to wake up on bus event.\n\n**************************************************************************************************************************/\n\nuint32_t ARM_CAN_GetClock (void)  {\n  return ARM_DRIVER_OK;  \n}\n/**\n\\fn          uint32_t ARM_CAN_GetClock (void)\n\\details\nThe function \\b ARM_CAN_GetClock returns the CAN base clock frequency in \\token{[Hz]}.\nThis value may be used to validate the \\em bitrate for the function \\ref ARM_CAN_SetBitrate.\n\n<b>Example</b>:\n\\code\n  CAN_clock = ARM_CAN_GetClock();  // CAN base clock frequency\n\\endcode\n\n**************************************************************************************************************************/\n\nint32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn          int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments)\n\\details  \nThe function \\b ARM_CAN_SetBitrate sets the CAN communication bit rate.\n\nThe parameter \\em select selects the bit rate affected by function call as defined in \\ref ARM_CAN_BITRATE_SELECT and listed in the table below.\n\nParameter \\em select                         | CAN Mode Bit Rate\n:--------------------------------------------|:------------------------------\n\\ref ARM_CAN_BITRATE_NOMINAL                 | Select nominal (flexible data-rate arbitration) bitrate (CAN 2.0B)\n\\ref ARM_CAN_BITRATE_FD_DATA                 | Select flexible data-rate data bitrate (\\ref CAN_FD)\n\nThe parameter \\em bitrate is the bit rate for the selected CAN mode.\n\nThe parameter \\em bit_segments is used to setup the time quanta for sampling (see picture below).\nThe values listed in the table below are ORed and specify the various sampling segments.\nThe CAN controller samples each bit on the bus at the <i>Sample Point</i>.\n\n<table class=\"cmtable\" summary=\"\">\n<tr>\n  <th>Parameter \\em bit_segments</th>\n  <th>Bit</th>  \n  <th> for \\em select = \\ref ARM_CAN_BITRATE_NOMINAL \\n (CAN specification)</th>\n  <th> for \\em select = \\ref ARM_CAN_BITRATE_NOMINAL \\n (CAN FD specification)</th>\n  <th> for \\em select = \\ref ARM_CAN_BITRATE_FD_DATA \\n (CAN FD specification)</th>\n</tr>\n<tr>\n  <td>\\ref ARM_CAN_BIT_PROP_SEG(<i>x</i>) \\n\n      Propagation Time Segment \\n (PROP_SEG)\n  </td>\n  <td>0..7 </td>\n  <td>\\em x = \\token{[1..8]}</td>\n  <td>\\em x = \\token{[1..32] or more}</td>  \n  <td>\\em x = \\token{[0..8]}</td>  \n</tr>\n<tr>\n  <td>\\ref ARM_CAN_BIT_PHASE_SEG1(<i>x</i>) \\n\n       Phase Buffer Segment 1 \\n (PHASE_SEG1)\n  </td>\n  <td>8..15 </td>\n  <td>\\em x = \\token{[1..8]}</td>\n  <td>\\em x = \\token{[1..32] or more}</td>  \n  <td>\\em x = \\token{[1..8]}</td>  \n</tr>\n<tr>\n  <td rowspan=\"2\">\\ref ARM_CAN_BIT_PHASE_SEG2(<i>x</i>) \\n \n      Phase Buffer Segment 2 \\n (PHASE_SEG2)\n  </td>\n  <td rowspan=\"2\">16..23 </td>\n  <td>\\em x = \\token{[1..8]} </td>\n  <td>\\em x = \\token{[1..32] or more}</td>  \n  <td>\\em x = \\token{[1..8]}</td>  \n<tr>\n  <td colspan=\"3\">The maximum allowed value is \\token{x = MAX (PHASE_SEG1, IPT)}. \n                  IPT = Information Processing Time. Usually, IPT = \\token{2}. \n\t\t\t\t  Exceptions apply. Read the specifications of your CAN controller.</td>\n</tr>\n<tr>\n  <td rowspan=\"2\">\\ref ARM_CAN_BIT_SJW(<i>x</i>) \\n\n      (Re-)Synchronization Jump Width \\n (SJW).\n  </td>\n  <td rowspan=\"2\">24..31 </td>\n  <td>\\em x = \\token{[1..4]}</td>\n  <td>\\em x = \\token{[1..4]}</td>  \n  <td>\\em x = \\token{[1..4]}</td>  \n<tr>\n  <td colspan=\"3\">The maximum allowed value is \\token{x = MIN (MIN (PHASE_SEG1, PHASE_SEG2), 4)}. \n                  SJW is not allowed to be greater than either PHASE segment.\n  </td>\n</tr>\n</table>\n\n<p>\nThe picture shows a Nominal Bit Time with 10 time quanta.\n\\image html CAN_Bit_Timing.png  \"CAN Bit Timing\"\n</p>\n\nThe time quanta (N) per bit is:\n\\code\n  N = 1 + PROP_SEG + PHASE_SEG1 + PHASE_SEG2; // note SYNC_SEG is always 1\n\\endcode\n\nThe driver uses this value and the CAN clock to calculate a suitable prescaler value (P).\nIf the driver cannot achieve the requested \\em bitrate it returns with \\ref ARM_CAN_INVALID_BITRATE.\nThe formula for the \\em bitrate is:\n\\code\n  bitrate = (CAN_Clock / P) / N;\n\\endcode\n\n<b>Example</b>:\n\\code\nstatus = ptrCAN->SetBitrate    (ARM_CAN_BITRATE_NOMINAL,              // Set nominal bitrate\n                                125000U,                              // Set bitrate to 125 kbit/s\n                                ARM_CAN_BIT_PROP_SEG(5U)   |          // Set propagation segment to 5 time quanta\n                                ARM_CAN_BIT_PHASE_SEG1(1U) |          // Set phase segment 1 to 1 time quantum (sample point at 87.5% of bit time)\n                                ARM_CAN_BIT_PHASE_SEG2(1U) |          // Set phase segment 2 to 1 time quantum (total bit is 8 time quanta long)\n                                ARM_CAN_BIT_SJW(1U));                 // Resynchronization jump width is same as phase segment 2\n\\endcode\n\nIn this example, N = 8 and with a CAN_Clock = 8MHz the prescaler (P) is calculated by the driver to 8.\n**************************************************************************************************************************/\n\nint32_t ARM_CAN_SetMode (ARM_CAN_MODE mode)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn  int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode)\n\\details\nThe function \\b ARM_CAN_SetMode sets the CAN bus communication mode using the parameter \\em mode.\n\nThe table lists the values for \\em mode.\n\n<table class=\"cmtable\" summary=\"\">\n    <tr><th>Parameter \\em mode</th>                    \n        <th>Bus Communication Mode</th>\n        <th>supported when \\ref ARM_CAN_OBJ_CAPABILITIES data field</th>\n    </tr>\n    <tr><td>\\ref ARM_CAN_MODE_INITIALIZATION</td>    \n        <td>Initialization mode; Used to setup communication parameters for the reception \n    \t    objects and global filtering, while peripheral is not active on the bus.\n    \t    Refer to \\ref can_filtering for details.</td>\n    \t<td><i>always supported</i></td>\n    </tr>\n    <tr><td>\\ref ARM_CAN_MODE_NORMAL</td>\n        <td>Normal operation mode. Used when peripheral is in active mode to \n            receive, transmit, and acknowledge messages on the bus. Depending on the current unit state, \n    \t    it can generate error or overload messages. Verify the unit state with \\ref ARM_CAN_GetStatus.\n    \t<td><i>always supported</i></td>\n    </tr>\n    <tr><td>\\ref ARM_CAN_MODE_RESTRICTED</td>\n        <td>Restricted operation mode. Used for monitoring the bus communication non-intrusively \n            without transmitting.</td>\n    \t<td>\\em restricted_mode = \\token{1}</td>\n    </tr>\n    <tr><td>\\ref ARM_CAN_MODE_MONITOR</td>\n        <td>Bus monitoring mode.</td>\n    \t<td>\\em monitor_mode = \\token{1}</td>\n    </tr>\n    <tr><td>\\ref ARM_CAN_MODE_LOOPBACK_INTERNAL</td>\n        <td>Test mode; loopback of CAN transmission to its receiver. No transmission visible on CAN bus.</td>\n    \t<td>\\em internal_loopback = \\token{1}</td>\n    </tr>\n    <tr><td>\\ref ARM_CAN_MODE_LOOPBACK_EXTERNAL</td> \n        <td>Test mode; loopback of CAN transmission to its receiver. Transmission is visible on CAN bus.</td>\n    \t<td>\\em external_loopback = \\token{1}</td>\n    </tr>\n</table>\n**************************************************************************************************************************/\n\nARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx)  {\n   // your code\n   // return type ARM_CAN_OBJ_CAPABILITIES;\n}\n/**\n\\fn          ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx)\n\\details\nThe function \\b  ARM_CAN_ObjectGetCapabilities retrieves the capabilities of a CAN object. \nThe structure \\ref ARM_CAN_OBJ_CAPABILITIES stores the values.\n\nThe parameter \\em obj_idx is the message object index.\n\n\\sa ARM_CAN_ObjectConfigure\n\\sa ARM_CAN_ObjectSetFilter\n**************************************************************************************************************************/\n\nint32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn          int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg)\n\\details\nThe function \\b ARM_CAN_ObjectSetFilter sets or removes the filter for message reception. Refer to \\ref can_filtering for details on filtering. \n\nThe parameter \\em obj_idx is the message object index. \\n\nThe parameter \\em operation is the operation on the filter as listed in the table below and \nwhich are defined in the structure \\ref ARM_CAN_FILTER_OPERATION.\n\nParameter \\em operation                 |  Operation on Filter          | supported when \\ref ARM_CAN_OBJ_CAPABILITIES data field\n:---------------------------------------|:------------------------------|:------------------------------------------\n\\ref ARM_CAN_FILTER_ID_EXACT_ADD        | Add    exact ID filter        | \\em exact_filtering = \\token{1}\n\\ref ARM_CAN_FILTER_ID_EXACT_REMOVE     | Remove exact ID filter        | \\em exact_filtering = \\token{1}\n\\ref ARM_CAN_FILTER_ID_RANGE_ADD        | Add    range ID filter        | \\em range_filtering = \\token{1}\n\\ref ARM_CAN_FILTER_ID_RANGE_REMOVE     | Remove range ID filter        | \\em range_filtering = \\token{1}\n\\ref ARM_CAN_FILTER_ID_MASKABLE_ADD     | Add    maskable ID filter     | \\em mask_filtering = \\token{1}\n\\ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE  | Remove maskable ID filter     | \\em mask_filtering = \\token{1}\n\nThe parameter \\em id is the identifier of the filter or defines the start of the filter range (depends on the filter operation). \\n\nThe parameter \\em arg is the mask of the filter or defines the end of the filter range (depends on the filter operation).\n\n\\sa ARM_CAN_ObjectConfigure \n**************************************************************************************************************************/\n\nint32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg)\n\\details\nThe function \\b ARM_CAN_ObjectConfigure configures the message object, which can be a mailbox or FIFO.\nRefer to \\ref can_filtering for details.\n\nThe parameter \\em obj_idx specifies the message object index. \\n\nThe parameter \\em obj_cfg configures the \\b object with values as shown in the following table.\n\n<table class=\"cmtable\" summary=\"\">\n<tr>\n  <th>Parameter \\em obj_cfg</th>\n  <th>Object Configuration</th>\n  <th>supported when \\ref ARM_CAN_OBJ_CAPABILITIES data field</th>\n</tr>\n<tr>\n   <td>\\ref ARM_CAN_OBJ_INACTIVE</td>\n   <td>Deactivate object (default after \\ref ARM_CAN_Initialize)\n   </td>\n   <td><i>always supported</i></td>\n</tr>\n<tr>\n   <td>\\ref ARM_CAN_OBJ_RX</td>\n   <td>Receive object; read received message with \\ref ARM_CAN_MessageRead.\n   </td>\n   <td>\\em rx = \\token{1}</td>\n</tr>\n<tr>\n   <td>\\ref ARM_CAN_OBJ_TX </td>\n   <td>Transmit object; send message with \\ref ARM_CAN_MessageSend.\n   </td>\n   <td>\\em tx = \\token{1}</td>\n</tr>\n<tr>\n   <td>\\ref ARM_CAN_OBJ_RX_RTR_TX_DATA</td>\n   <td>\\ref Remote_Frame Receive; when \\b RTR is received data message is transmitted; set data message with \\ref ARM_CAN_MessageSend.\n   </td>\n   <td>\\em  rx_rtr_tx_data = \\token{1}</td>\n</tr>\n<tr>\n   <td>\\ref ARM_CAN_OBJ_TX_RTR_RX_DATA</td>\n   <td>\\ref Remote_Frame Transmit; a \\b RTR is sent with \\ref ARM_CAN_MessageSend to trigger object reception; read received data message with \\ref ARM_CAN_MessageRead.\n   </td>\n   <td>\\em  tx_rtr_rx_data = \\token{1}</td>\n</tr>\n</table>\n\nWhen the \\b object is deactivated, it is not used for data communication.\n\n\\sa ARM_CAN_ObjectSetFilter\n**************************************************************************************************************************/\n\nint32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn          int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size)\n\\details\nThe function \\b ARM_CAN_MessageSend sends a CAN message on the CAN bus, or sets data message that will be automatically returned upon RTR reception with matching CAN ID.\n\nOnly one message can be sent with a call to this function (for CAN up to \\token{8} bytes; for CAN FD up to \\token{64} bytes of data).\nA message transmission can be terminated with a call to the function \\ref ARM_CAN_Control with \\em control = \\ref ARM_CAN_ABORT_MESSAGE_SEND.\n\nThe parameter \\em obj_idx specifies the message object index. \n\nThe parameter \\em msg_info is a pointer to the structure \\ref ARM_CAN_MSG_INFO, which contains the following relevant data fields for sending message:\n    - \\em id:  Identifier of the message; bit \\token{31} specifies if this is an \\token{11-bit} or \\token{29-bit} identifier.\n    - \\em rtr: Specifies if Remote Transmission Request should be sent (\\em dlc is used for number of requested bytes), otherwise the data message will be sent. Refer to \\ref Remote_Frame for details.\n    - \\em edl: Specifies if Extended Data Length is used; for CAN FD, message can contain up to \\token{64} data bytes.\n    - \\em brs: Specifies if Bit Rate Switching is to be used; for CAN FD, the bit rate can be increased during data phase.\n    - \\em dlc: Data Length Code of requested data bytes when sending Remote Transmission Request.\n\nThe parameter \\em data is a pointer to the data buffer.\\n\nThe parameter \\em size is the number of data bytes to send.\\n\n\nThe function returns the number of bytes accepted to be sent or \\ref ARM_DRIVER_ERROR_BUSY if the hardware is not\nready to accept a new message for transmission.\n\nWhen the message is sent, the callback function \\ref ARM_CAN_SignalObjectEvent is called signalling \\ref ARM_CAN_EVENT_SEND_COMPLETE\non specified object.\n\n\\sa \\ref can_filtering\n\n<b>Example:</b>\n\n\\code\n  status = ptrCAN->ObjectConfigure(0, ARM_CAN_OBJ_TX);\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n \n  memset(&tx_msg_info, 0, sizeof(ARM_CAN_MSG_INFO));            // Clear transmit message structure\n  tx_msg_info.id  = ARM_CAN_EXTENDED_ID(0x12345678U);           // Set ID of message\n  data_buf[0] = '1';  data_buf[1] = '2';                        // Prepare data to transmit\n  data_buf[2] = '3';  data_buf[3] = '4';\n  data_buf[4] = '5';  data_buf[5] = '6';\n  data_buf[6] = '7';  data_buf[7] = '8';\n  status = ptrCAN->MesageSend(0, &tx_msg_info, data_buf, 8);    // Send message\n  if (status != ARM_DRIVER_OK ) { Error_Handler(); }\n\\endcode\n**************************************************************************************************************************/\n\nint32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn          int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size)\n\\details\nThe function \\b ARM_CAN_MessageRead reads the message received on the CAN bus, if \\em obj_idx was configured for reception or \nfor automatic Data Message reception using RTR and the callback function \\ref ARM_CAN_SignalObjectEvent was called \nsignalling \\ref ARM_CAN_EVENT_RECEIVE.\nIf the message was overrun by another received message, then the callback function \\ref ARM_CAN_SignalObjectEvent\nwill be called signalling \\ref ARM_CAN_EVENT_RECEIVE_OVERRUN.\n\nThe function can read a maximum of \\token{8} data bytes for CAN and \\token{64} bytes for CAN FD.\n\nThe parameter \\em obj_idx specifies the message object index. \\n\nThe parameter \\em msg_info is a pointer to the CAN information structure. \\n\nThe parameter \\em data is a pointer to the data buffer for reading data. \\n\nThe parameter \\em size is data buffer size in bytes and indicates the maximum number of bytes that can be read.\n\nThe function returns the number of read data in bytes or the \\ref execution_status.\n\nAll data fields of the structure \\ref ARM_CAN_MSG_INFO are updated as described below:\n    - id:  Identifier of the message that was received, bit \\token{31} specifies if it is a \\token{11-bit} identifier or \\token{29-bit} identifier.\n    - rtr: \\token{1} = Remote Frame Request was received (\\em dlc is number of requested bytes).  \\token{0} = data message\n    - edl: \\token{1} = CAN FD Extended Data Length message was received.  \\token{0} = not Extended Data Length message.\n    - brs: \\token{1} = CAN FD Bit Rate Switching was used for message transfer. \\token{0} = no Bit Rate Switching was used.\n    - esi: \\token{1} = CAN FD Error State Indicator is active for received message.  \\token{0} = Error State Indicator is not active.\n    - dlc: Data Length Code is the number of data bytes in the received message or number of data bytes requested by RTR.\n\nMessage reception can be disabled by de-configuring the receive object with the function \\ref ARM_CAN_ObjectConfigure.\n**************************************************************************************************************************/\n\nint32_t ARM_CAN_Control (uint32_t control, uint32_t arg)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn   int32_t ARM_CAN_Control (uint32_t control, uint32_t arg)\n\\details\nThe function \\b ARM_CAN_Control controls the CAN interface settings and executes various operations.\n\nThe parameter \\em control specifies various operations that are listed in the table below.\n\nThe parameters \\em arg provides, depending on the \\em control value, additional information or set values.\n\nParameter \\em control                        | Operation\n:--------------------------------------------|:------------------------------\n\\ref ARM_CAN_SET_FD_MODE                     | Select <a href=\"#CAN_FD\"><b>CAN FD</b></a> mode; \\em arg : \\token{0} = CAN 2.0B; \\token{1} = CAN FD.\n\\ref ARM_CAN_ABORT_MESSAGE_SEND              | Abort sending of CAN message;      \\em arg : object index\n\\ref ARM_CAN_CONTROL_RETRANSMISSION          | Enable/disable automatic retransmission; \\em arg : \\token{0 = disable, 1 = enable (default state)}\n\\ref ARM_CAN_SET_TRANSCEIVER_DELAY           | Set transceiver delay; \\em arg : delay in time quanta \n\nVerify the CAN interface capabilities with \\ref ARM_CAN_GetCapabilities.\n*******************************************************************************************************************/\n\nARM_CAN_STATUS ARM_CAN_GetStatus (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn            ARM_CAN_STATUS ARM_CAN_GetStatus (void)\n\\details\nThe function \\b ARM_CAN_GetStatus retrieves runtime information on CAN bus and CAN unit state.\n\nThe following defines give information about the current unit involvement in bus communication:\n\nUnit State                             | Description\n:--------------------------------------|:------------\n\\ref ARM_CAN_UNIT_STATE_INACTIVE       | Unit state: Not active on the bus. Unit is in initialization state.\n\\ref ARM_CAN_UNIT_STATE_ACTIVE         | Unit state: Active on the bus. Unit can generate active error frames.\n\\ref ARM_CAN_UNIT_STATE_PASSIVE        | Unit state: Error passive. Unit is interacting on the bus but does not send active error frames.\n\\ref ARM_CAN_UNIT_STATE_BUS_OFF        | Unit state: Bus-off. Unit does not participate on the bus but monitors it and can recover to active state.\n\nThe following defines are error codes of the last error that happened on the bus:\n\nLast Error Code                        | Description\n:--------------------------------------|:------------\n\\ref ARM_CAN_LEC_NO_ERROR              | No error. There was no error since last read of status or last successful transmit or receive.\n\\ref ARM_CAN_LEC_BIT_ERROR             | Bit error. The bit monitored is different than the bit sent (except during arbitration phase).\n\\ref ARM_CAN_LEC_STUFF_ERROR           | Bit stuffing error. There were 6 consecutive same bit levels on the bus.\n\\ref ARM_CAN_LEC_CRC_ERROR             | CRC error. CRC of received data is not as expected.\n\\ref ARM_CAN_LEC_FORM_ERROR            | Illegal fixed-form bit. Error in fixed form bits.\n\\ref ARM_CAN_LEC_ACK_ERROR             | Acknowledgment error. Message was not acknowledged by any receiver on the bus.\n\n*******************************************************************************************************************/\n\nvoid ARM_CAN_SignalUnitEvent (uint32_t event)  {\n // function body\n}\n/**\n\\fn      void ARM_CAN_SignalUnitEvent (uint32_t event)\n\\details\nThe function \\b ARM_CAN_SignalUnitEvent is a callback function registered by the function \\ref ARM_CAN_Initialize. \n\nThe parameter \\em event indicates unit event that occurred during driver operation.\n\nThe following callback notifications are generated:\n\nParameter \\em event                | Value |Description\n:----------------------------------|:-----:|:-------------------------------------------------\n\\ref ARM_CAN_EVENT_UNIT_INACTIVE   |   0   | Unit entered Inactive state.\n\\ref ARM_CAN_EVENT_UNIT_ACTIVE     |   1   | Unit entered Error Active state.\n\\ref ARM_CAN_EVENT_UNIT_WARNING    |   2   | Unit entered Error Warning state (one or both error counters >= \\token{96}).\n\\ref ARM_CAN_EVENT_UNIT_PASSIVE    |   3   | Unit entered Error Passive state.\n\\ref ARM_CAN_EVENT_UNIT_BUS_OFF    |   4   | Unit entered Bus-off state.\n\n\\sa \\ref ARM_CAN_GetStatus \n*******************************************************************************************************************/\n\nvoid ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event)  {\n  // function body\n}\n/**\n\\fn          void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event)\n\\details\nThe function \\b ARM_CAN_SignalObjectEvent is a callback function registered by the function \\ref ARM_CAN_Initialize and \nsignals a CAN message object event. \n\nThe parameter \\em obj_idx  is the index of the message object. \\n\nThe parameter \\em event indicates object event that occurred during driver operation. \n\nThe following events can be generated:\n\n Parameter \\em event                 | Bit | Description\n:------------------------------------|:---:|:-------------------------------------------------------------------------\n \\ref ARM_CAN_EVENT_SEND_COMPLETE    |  0  | Message was sent successfully by the \\em obj_idx object.\n \\ref ARM_CAN_EVENT_RECEIVE          |  1  | Message was received successfully by the \\em obj_idx object.\n \\ref ARM_CAN_EVENT_RECEIVE_OVERRUN  |  2  | Message was overwritten before it was read on the \\em obj_idx object.\n\n\\sa \\ref ARM_CAN_MessageSend\n\\sa \\ref ARM_CAN_MessageRead\n\\sa \\ref ARM_CAN_ObjectConfigure\n*******************************************************************************************************************/\n\n/**\n@}\n*/\n// End CAN Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_Common.c",
    "content": "/**\n\\defgroup common_drv_gr Common Driver Definitions\n\\brief Definitions common in all driver interfaces (%Driver_Common.h)\n\\details\nThe following definitions are common in all CMSIS-Driver interfaces. Refer to \\ref DriverFunctions\nfor a general overview.\n@{\n*/\n\n\n/**\n\\enum ARM_POWER_STATE\n\\details \nThe access structure of each CMSIS-Driver provides the function \\b PowerControl, which handles the power\nprofile for a peripheral using the parameter \\ref ARM_POWER_STATE. Depending on this parameter, \nthe peripheral will operate at full speed, detect just events, or is completely un-powered.\n\nRefer to \\ref CallSequence for more information.\n*/\n\n/**\n\\struct ARM_DRIVER_VERSION\n\\details\nThe access structure of each CMSIS-Driver provides the function \\b GetVersion, which returns in the struct ARM_DRIVER_VERSION:\n - API version, which is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version, which is the source code version of the actual driver implementation.\n\nThe version is encoded as 16-bit unsigned value (uint16_t) with:\n - high-byte: major version.\n - low-byte: minor version.\n\nFor example, version 1.12 is encoded as 0x10C.\n\n\n\\defgroup execution_status Status Error Codes\n\\ingroup common_drv_gr\n\\brief Negative return values of functions indicate errors occurred during execution. \n\\details \nMost functions return a status information using negative return values.\nThe following list provides the status error codes that are common in all drivers.\nThe drivers may return also status error codes that are specific to the peripheral.\n\\sa\n\\ref spi_execution_status for SPI driver;\n\\ref usart_execution_status for USART driver;\n\\ref nand_execution_status for NAND driver;\n@{\n\\def ARM_DRIVER_OK\nThe value 0 or positive values indicate that the function execution is completed without any errors.\nNote that positive values are used to provide for example the number of data items.\n\n\\def ARM_DRIVER_ERROR\nThe function did not execute correct and an unspecified error occurred during execution.\n\n\\def ARM_DRIVER_ERROR_BUSY\nThe function cannot be executed because the driver is busy with the execution of a conflicting operation.\n\n\\def ARM_DRIVER_ERROR_TIMEOUT\nThe function execution is terminated because a peripheral did not react within a specific timeout limit.\n\n\\def ARM_DRIVER_ERROR_UNSUPPORTED\nThe function requested an operation (for example by using an illegal control code) that is not supported.\n\n\\def ARM_DRIVER_ERROR_PARAMETER\nA function parameter is incorrect.\n\n\\def ARM_DRIVER_ERROR_SPECIFIC\nThis value indicates the start of status error codes that are specific to the peripheral driver.\n\\sa\n\\ref spi_execution_status for SPI driver;\n\\ref usart_execution_status for USART driver;\n@}\n*/\n\n/**\n@}\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_ETH.c",
    "content": "/**\n\\defgroup eth_interface_gr Ethernet Interface\n\\brief    Ethernet common definitions (%Driver_ETH.h)\n\n\\details\n<b>Ethernet</b> is a networking technology for exchanging data packages between computer systems. Several microcontrollers integrate \nan Ethernet MAC (Media Access Control) data-link layer that interfaces to an Ethernet PHY (Physical Interface Transceiver).\n\nWikipedia offers more information about \nthe <a href=\"http://en.wikipedia.org/wiki/Ethernet\" target=\"_blank\"><b>Ethernet</b></a>.\n\n\n<b>Block Diagram</b>\n\nThe Ethernet PHY connects typically to the Ethernet MAC using an MII (Media Independent Interface) or RMII (Reduced Media Independent Interface).\n\n\\n\n\\image html EthernetSchematic.png  \"Block Diagram of a typical Ethernet Interface\"\n\n\n<b>Ethernet API</b>\n\nThe following header files define the Application Programming Interface (API) for the <b>Ethernet</b> interface:\n - \\b %Driver_ETH.h : Common definitions of the Ethernet PHY and MAC part\n - \\b %Driver_ETH_MAC.h : API for the Ethernet MAC\n - \\b %Driver_ETH_PHY.h : API for the Ethernet PHY\n \nThe driver implementation of the Ethernet MAC is a typical part of a Device Family Pack (DFP) that supports the peripherals of the microcontroller family.\nThe driver implementation of the Ethernet PHY is a typical part of a \\b Network Software Pack, since PHY is typically not integrated into the microcontroller.\n\n\\note\nFor parameters, the value marked with (default) is the setting after the driver initialization.\n\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n - \\ref ARM_DRIVER_ETH_MAC : access struct for <b>Ethernet MAC</b> driver functions.\n - \\ref ARM_DRIVER_ETH_PHY : access struct for <b>Ethernet PHY</b> driver functions.\n\nBoth drivers are used in combination and usually the Ethernet MAC provides a media interface to the Ethernet PHY.\nA typical setup sequence for the drivers is shown below:\n\n<b>Example Code</b>\n\nThe following example code shows the usage of the Ethernet interface.\n\n\\code\nextern ARM_DRIVER_ETH_MAC Driver_ETH_MAC0;\nextern ARM_DRIVER_ETH_PHY Driver_ETH_PHY0;\n \nstatic ARM_DRIVER_ETH_MAC *mac;\nstatic ARM_DRIVER_ETH_PHY *phy;\nstatic ARM_ETH_MAC_ADDR          own_mac_address;\nstatic ARM_ETH_MAC_CAPABILITIES  capabilities;\n \nvoid ethernet_mac_notify (uint32_t event)  {\n  switch (event)  {\n     :\n  }  \n}\n \n \nvoid initialize_ethernet_interface (void) {\n  mac = &Driver_ETH_MAC0;\n  phy = &Driver_ETH_PHY0;\n \n  // Initialize Media Access Controller\n  capabilities = mac->GetCapabilities ();\n   \n  mac->Initialize (ethernet_mac_notify);\n  mac->PowerControl (ARM_POWER_FULL);\n \n  if (capabilities.mac_address == 0)  {\n    // populate own_mac_address with the address to use\n    mac->SetMacAddress(&own_mac_address);\n  }\n  else {\n    mac->GetMacAddress(&own_mac_address);\n  }\n \n  // Initialize Physical Media Interface\n  if (phy->Initialize (mac->PHY_Read, mac->PHY_Write) == ARM_DRIVER_OK) {\n    phy->PowerControl (ARM_POWER_FULL);\n    phy->SetInterface (capabilities.media_interface);\n    phy->SetMode (ARM_ETH_PHY_AUTO_NEGOTIATE);\n  }\n    :\n    :\n}\n \n \nstatic ARM_ETH_LINK_STATE ethernet_link;   // current link status\n \nvoid ethernet_check_link_status (void) {\n  ARM_ETH_LINK_STATE link;\n \n  link = phy->GetLinkState ();\n  if (link == ethernet_link) {    \n    return;                                // link state unchanged\n  }\n                                           // link state changed\n  ethernet_link = link;   \n  if (link == ARM_ETH_LINK_UP) {      // start transfer\n    ARM_ETH_LINK_INFO info = phy->GetLinkInfo ();\n    mac->Control(ARM_ETH_MAC_CONFIGURE,\n                 info.speed  << ARM_ETH_MAC_SPEED_Pos  |\n                 info.duplex << ARM_ETH_MAC_DUPLEX_Pos |\n                 ARM_ETH_MAC_ADDRESS_BROADCAST);\n    mac->Control(ARM_ETH_MAC_CONTROL_TX, 1);\n    mac->Control(ARM_ETH_MAC_CONTROL_RX, 1);\n  }\n  else {                                   // stop transfer\n    mac->Control(ARM_ETH_MAC_FLUSH, ARM_ETH_MAC_FLUSH_TX | ARM_ETH_MAC_FLUSH_RX);\n    mac->Control(ARM_ETH_MAC_CONTROL_TX, 0);\n    mac->Control(ARM_ETH_MAC_CONTROL_RX, 0);\n  }\n}\n\n\\endcode\n*/\n\n/**\n\\defgroup eth_interface_gr Ethernet Interface\n@{\n*/\n\n/**\n\\cond\n*/\n\n/**\n\\enum ARM_ETH_INTERFACE\n\\details\nEncodes the supported media interface between Ethernet MAC and Ethernet PHY. \n\nThe function \\ref ARM_ETH_MAC_GetCapabilities retrieves the media interface type encoded in the data field \\b media_interface of the struct\n \\ref ARM_ETH_MAC_CAPABILITIES. \n\n<b>Parameter for:</b>\n- \\ref ARM_ETH_PHY_SetInterface\n*/\n\n/**\n\\enum ARM_ETH_DUPLEX\n\\details \nLists the supported duplex operating types for MAC.\n\n<b>Parameter for:</b>\n  - \\ref ARM_ETH_MAC_SetMode\n*/\n\n\n/**\n\\typedef ARM_ETH_SPEED\n\\details \nLists the supported operating speeds for MAC.\n\n<b>Parameter for:</b>\n  - \\ref ARM_ETH_MAC_SetMode\n*/\n\n/**\n\\endcond\n*/\n\n\n/**\n\\typedef ARM_ETH_LINK_STATE\n\\details \nThe Ethernet Link status shows if the communication is currently established (up) or interrupted (down).\n\n<b>Returned by:</b>\n  - \\ref ARM_ETH_PHY_GetLinkState\n*/\n\n\n/**\n\\struct ARM_ETH_LINK_INFO\n\\details\nThe Ethernet Link information provides parameters about the current established communication.\n\n<b>Returned by:</b>\n  - \\ref ARM_ETH_PHY_GetLinkInfo\n*/\n\n\n/**\n\\struct ARM_ETH_MAC_ADDR\n\\details\nStores the MAC Address of the Ethernet interface as defined by IEEE 802. Wikipedia offers more information about \nthe <a href=\"http://en.wikipedia.org/wiki/MAC_address\" target=\"_blank\"><b>MAC Address</b></a>.\n\n<b>Parameter for:</b>\n  - \\ref ARM_ETH_MAC_GetMacAddress, \\ref ARM_ETH_MAC_SetMacAddress, \\ref ARM_ETH_MAC_SetAddressFilter\n*/\n\n/**\n@}\n*/ \n// End ETH Interface\n\n\n/**\n\\defgroup eth_interface_types1 Media Interface Types\n\\ingroup eth_interface_gr\n\\brief Ethernet Media Interface type\n\\details\nEncodes the supported media interface between Ethernet MAC and Ethernet PHY. \nThe function \\ref ARM_ETH_MAC_GetCapabilities retrieves the media interface type encoded in the data field \\b media_interface of the struct\n \\ref ARM_ETH_MAC_CAPABILITIES. \n\n<b>Parameter for:</b>\n- \\ref ARM_ETH_PHY_SetInterface\n\n@{\n\\def ARM_ETH_INTERFACE_MII \n\\sa ARM_ETH_PHY_SetInterface\n\\def ARM_ETH_INTERFACE_RMII\n\\sa ARM_ETH_PHY_SetInterface\n\\def ARM_ETH_INTERFACE_SMII\n\\sa ARM_ETH_PHY_SetInterface\n@}\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_ETH_MAC.c",
    "content": "/**\n\\defgroup   eth_mac_interface_gr Ethernet MAC Interface\n\\ingroup    eth_interface_gr\n\\brief      Driver API for Ethernet MAC Peripheral (%Driver_ETH_MAC.h)\n\\details \nThe following section describes the Ethernet MAC Interface as defined in the %Driver_ETH_MAC.h header file.\n@{\n*/\n\n/**\n\\struct     ARM_ETH_MAC_CAPABILITIES\n\\details\nAn Ethernet MAC driver can be implemented with different capabilities.  \nThe data fields of this struct encode the capabilities implemented by this driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_ETH_MAC_GetCapabilities\n*/\n\n/**\n\\struct     ARM_DRIVER_ETH_MAC\n\\details\nThe functions of the Ethernet MAC are accessed by function pointers. Refer to \\ref DriverFunctions for \noverview information.\n\nEach instance of an Ethernet MAC provides such an access struct. The instance is indicated by\na postfix in the symbol name of the access struct, for example:\n - \\b Driver_ETH_MAC0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_ETH_MAC1 is the name of the access struct of the second instance (no. 1).\n\nA configuration setting in the middleware allows connecting the middleware to a specific driver instance <b>Driver_ETH_MAC<i>n</i></b>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*/\n\n/**\n\\struct     ARM_ETH_MAC_TIME\n\\details\nThe two members of this struct provide fields to encode time values in the order \\token{Nano seconds} and \\token{seconds}.\n\nThe member \\em ns is also used as a correction factor for \\ref ARM_ETH_MAC_TIMER_ADJUST_CLOCK.\n\n<b>Used in:</b>\n  - \\ref ARM_ETH_MAC_GetRxFrameTime\n  - \\ref ARM_ETH_MAC_GetTxFrameTime\n  - \\ref ARM_ETH_MAC_ControlTimer\n\n*******************************************************************************************************************/\n\n/**\n\\typedef    ARM_ETH_MAC_SignalEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_ETH_MAC_SignalEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_ETH_MAC_Initialize\n*******************************************************************************************************************/\n\n/**\n\\defgroup ETH_MAC_events Ethernet MAC Events\n\\ingroup eth_mac_interface_gr\n\\brief The Ethernet MAC driver generates call back events that are notified via the function \\ref ARM_ETH_MAC_SignalEvent.\n\\details \nThis section provides the event values for the \\ref ARM_ETH_MAC_SignalEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def ARM_ETH_MAC_EVENT_RX_FRAME\n\\def ARM_ETH_MAC_EVENT_TX_FRAME\n\\def ARM_ETH_MAC_EVENT_WAKEUP\n\\def ARM_ETH_MAC_EVENT_TIMER_ALARM\n@}\n*/\n\n//\n// Function documentation\n//\n\nARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void)  {\n  ;\n}\n/**\n\\fn       ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void);\n\\details\nThe function \\b ARM_ETH_MAC_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_ETH_MAC Driver_ETH_MAC0;\nARM_DRIVER_ETH_MAC *mac;\n \nvoid setup_ethernet (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  mac = &Driver_ETH_MAC0;  \n  version = mac->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*******************************************************************************************************************/\n\nARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)  {\n  ;\n}\n/**\n\\fn       ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)\n\\details\nThe function \\b ARM_ETH_MAC_GetCapabilities retrieves information about capabilities in this driver implementation.\nThe data fields of the struct \\ref ARM_ETH_MAC_CAPABILITIES encode various capabilities, for example\nif a hardware is capable to create checksums in hardware or signal events using the \\ref ARM_ETH_MAC_SignalEvent \ncallback function.\n \nExample:\n\\code\nextern ARM_DRIVER_ETH_MAC Driver_ETH_MAC0;\nARM_DRIVER_ETH_MAC *mac;\n  \nvoid read_capabilities (void)  {\n  ARM_ETH_MAC_CAPABILITIES mac_capabilities;\n \n  mac = &Driver_ETH_MAC0;  \n  mac_capabilities = mac->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)  {\n  \n}\n/**\n\\fn     int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)\n\\details \nThe function \\b ARM_ETH_MAC_Initialize initializes the Ethernet MAC interface. \nIt is called when the middleware component starts operation.\n\nThe \\ref ARM_ETH_MAC_Initialize function performs the following operations:\n  - Initializes the resources needed for the Ethernet MAC peripheral.\n  - Registers the \\ref ARM_ETH_MAC_SignalEvent callback function.\n\nThe parameter \\em cb_event is a pointer to the \\ref ARM_ETH_MAC_SignalEvent callback function; use a NULL pointer \nwhen no callback signals are required.\n\n\\b Example:\n - see \\ref eth_interface_gr - Driver Functions\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_Uninitialize (void)  {\n  \n}\n/**\n\\fn       int32_t ARM_ETH_MAC_Uninitialize (void)\n\\details\nThe function \\b ARM_ETH_MAC_Uninitialize de-initializes the resources of Ethernet MAC interface.\n\nIt is called when the middleware component stops operation and releases the software resources \nused by the interface.\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)\n\\details     \nThe function \\b ARM_ETH_MAC_PowerControl allows you to configure the power modes of the Ethernet MAC interface.  \n\nThe parameter \\em state can be:\n - ARM_POWER_OFF: Ethernet MAC peripheral is turned off.\n - ARM_POWER_FULL: Ethernet MAC peripheral is turned on and fully operational.\n\nIf power \\em state specifies an unsupported mode, the function returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED as status information\nand the previous power state of the peripheral is unchanged. Multiple calls with the same \\em state generate no\nerror.\n\n\\b Example:\n - see \\ref eth_interface_gr - Driver Functions\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)\n\\details\nThe function \\b ARM_ETH_MAC_GetMacAddress retrieves the Ethernet MAC own address from the driver.\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)\n\\details\nThe function \\b ARM_ETH_MAC_SetMacAddress configures Ethernet MAC own address.\nThe Ethernet MAC accepts packets <a href=\"http://en.wikipedia.org/wiki/Ethernet_frame\" target=\"_blank\"><b>Ethernet frames</b></a> which contains \na MAC destination address that matches the address specified with \\em ptr_addr. \n\nThe Ethernet MAC receiver will accept also packets with addresses configured by \\ref ARM_ETH_MAC_SetAddressFilter function.\n\nMAC receiver can be configured to accept also packets with broadcast address, any multicast address or even all packets regardless of address (Promiscuity Mode). \nThis is configured by function \\ref ARM_ETH_MAC_Control with \\ref ARM_ETH_MAC_CONFIGURE as control parameter.\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)\n\\details\nThe function \\b ARM_ETH_MAC_SetAddressFilter configures Ethernet MAC receiver address filtering.\nThe Ethernet MAC accepts packets <a href=\"http://en.wikipedia.org/wiki/Ethernet_frame\" target=\"_blank\"><b>Ethernet frames</b></a> which contains \na MAC destination address of the list supplied with \\em ptr_addr.  The parameter \\em ptr_addr provides and array of Ethernet MAC addresses.  The number of addresses\nis supplied by \\em num_addr. Specifying \\em num_adr = 0 disables address filtering previously set with this function.\n\nThe Ethernet MAC receiver will accept packets addressed to its own address and packets with addresses configured by this function.\n\nMAC receiver can be configured to accept also packets with broadcast address, any multicast address or even all packets regardless of address (Promiscuity Mode). \nThis is configured by function \\ref ARM_ETH_MAC_Control with \\ref ARM_ETH_MAC_CONFIGURE as control parameter.\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)\n\\details\nThe function \\b ARM_ETH_MAC_SendFrame writes an <a href=\"http://en.wikipedia.org/wiki/Ethernet_frame\" target=\"_blank\"><b>Ethernet frame</b></a> to the Ethernet MAC transmit buffer.\n\nThe Ethernet MAC transmit engine must be enabled by using the function \\ref ARM_ETH_MAC_Control (ARM_ETH_MAC_CONTROL_TX, 1) before a call to this function.\n\nThe frame data addressed by \\em buf starts with MAC destination and ends with the last Payload data byte. The frame data is copied into \nthe transmit buffer of the Ethernet MAC interface. The function does not wait until the transmission over the Ethernet is complete, \nhowever the memory addressed by \\em buf is available for the next Ethernet frame after return.\n\nThe maximum value for \\em len is implied by the size restrictions of the Ethernet frame but is not verified.\nUsing an invalid value for \\em len may generate unpredicted results.\n\nThe parameter \\em flags specifies additional attributes for the function as shown in the following table. Multiple flags can be combined, for example:\nARM_ETH_MAC_TX_FRAME_EVENT | ARM_ETH_MAC_TX_FRAME_TIMESTAMP.\n\nFlag bit                               | Description\n:--------------------------------------|:-----------------------------------------\n\\ref ARM_ETH_MAC_TX_FRAME_FRAGMENT     | Indicates that it is a fragment of the frame. allows you to collect multiple fragments before the frame is sent.\n\\ref ARM_ETH_MAC_TX_FRAME_EVENT        | \\ref ARM_ETH_MAC_SignalEvent with \\em event bit \\ref ARM_ETH_MAC_EVENT_TX_FRAME set will be called when frame send is complete.\n\\ref ARM_ETH_MAC_TX_FRAME_TIMESTAMP    | Capture the time stamp of the frame. The time stamp can be obtained using the function \\ref ARM_ETH_MAC_GetTxFrameTime.\n\n\n\\b Example:\n\\code\n  status = mac->SendFrame (&frame->data[0], frame->length, 0);\n  if (status != ARM_DRIVER_OK)  {\n    // error handling\n  }\n\\endcode\n\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)\n\\details\nThe function \\b ARM_ETH_MAC_ReadFrame reads an <a href=\"http://en.wikipedia.org/wiki/Ethernet_frame\" target=\"_blank\"><b>Ethernet frame</b></a> from the Ethernet MAC receive buffer.\n\nThe Ethernet MAC receive engine must be enabled using the function \\ref ARM_ETH_MAC_Control (ARM_ETH_MAC_CONTROL_RX , 1) before a call to this function.\nThe \\em len of the Ethernet frame can be checked using the function \\ref ARM_ETH_MAC_GetRxFrameSize.\n\nThe frame data addressed by \\em buf starts with MAC destination and ends with the last Payload data byte. The frame data is read from \nthe receive buffer of the Ethernet MAC interface and the number of bytes written into the memory addressed by \\em buf is returned.\nA negative return value indicates an error whereby the status code is defined with driver common return codes.\n\nThe function \\ref ARM_ETH_MAC_ReadFrame may be called with \\em buf = NULL and \\em len = 0 to discard or release an frame. This is useful when an incorrect frame has been received or\nno memory is available to hold the Ethernet frame.\n\n\\b Example:\n\\code\n  size = mac->GetRxFrameSize ();\n  if ((size < 14) || (size > 1514)) {    // frame excludes CRC\n    mac->ReadFrame (NULL, 0);            // Frame error, release it\n  }\n  len = mac->ReadFrame (&frame->data[0], size);\n  if (len < 0)  {\n    // error handling\n  }\n\\endcode\n*******************************************************************************************************************/\n\nuint32_t ARM_ETH_MAC_GetRxFrameSize (void)  {\n  \n}\n/**\n\\fn uint32_t ARM_ETH_MAC_GetRxFrameSize (void)\n\\details\nThe function \\b ARM_ETH_MAC_GetRxFrameSize returns the size of a received \n<a href=\"http://en.wikipedia.org/wiki/Ethernet_frame\" target=\"_blank\"><b>Ethernet frame</b></a>.\nThis function is called before \\ref ARM_ETH_MAC_ReadFrame and supplies the value \\em len.\n\nThe frame size includes MAC destination and ends with the last Payload data byte.\nValue \\em 0 indicates that no Ethernet frame is available in the receive buffer.\nValues smaller than minimum size of Ethernet frame or larger than maximum size of Ethernet frame\nindicate an invalid frame which needs to be discarded by calling \\ref ARM_ETH_MAC_ReadFrame.\n\n\\b Example:\n  - see \\ref ARM_ETH_MAC_ReadFrame\n\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)\n\\details\nRetrieve time stamp of a received <a href=\"http://en.wikipedia.org/wiki/Ethernet_frame\" target=\"_blank\"><b>Ethernet frame</b></a>.\nThis function must be called before the frame is read using \\ref ARM_ETH_MAC_ReadFrame.\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)\n\\details\nThe function \\b returns the time stamp of a transmitted <a href=\"http://en.wikipedia.org/wiki/Ethernet_frame\" target=\"_blank\"><b>Ethernet frame</b></a>.\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)\n\\details\nThe function \\b ARM_ETH_MAC_Control controls the Ethernet MAC interface and executes various operations. \nAfter initialization, the Ethernet transceiver and receiver are disabled.\n\nThe parameter \\em control specifies an operation as defined in the table <b>Parameter \\em control</b>. \\n\nThe parameter \\em arg provides, depending on the operation, additional information or values.\n\nThe table lists values for the parameter \\em control.\n\nParameter \\em control                                | Operation\n:----------------------------------------------------|:--------------------------------------------\n\\ref ARM_ETH_MAC_CONFIGURE                           | Configure the Ethernet MAC interface; For \\em arg values, see table <b>Parameter \\em arg for CONFIGURE</b>\n\\ref ARM_ETH_MAC_CONTROL_TX                          | Enable or disable the transmitter; \\em arg :  \\token{0=disable; 1=enable}\n\\ref ARM_ETH_MAC_CONTROL_RX                          | Enable or disable the receiver; \\em arg :  \\token{0=disable; 1=enable}\n\\ref ARM_ETH_MAC_FLUSH                               | Flush a buffer; \\em arg : see table <b>Parameter \\em arg for FLUSH</b>\n\\ref ARM_ETH_MAC_SLEEP                               | Exit/Enter Sleep mode; \\em arg : \\token{0=exit; 1=enter and wait for Magic packet}\n\\ref ARM_ETH_MAC_VLAN_FILTER                         | Configure VLAN Filter for received frames;  \\em arg : See table <b>Parameter \\em arg for VLAN Filter</b>\n\n\nThe table <b>Parameter \\em arg for CONFIGURE</b> lists the \\em arg values for the \\em control \\b ARM_ETH_MAC_CONFIGURE.\nThe values can be ORed in the following way:\n\\code\n    mac->Control(ARM_ETH_MAC_CONFIGURE, ARM_ETH_MAC_SPEED_100M | ARM_ETH_MAC_DUPLEX_FULL | ARM_ETH_MAC_LOOPBACK);\n\\endcode\n\n<table class=\"cmtable\" summary=\"\">\n<tr><th colspan=\"4\">Parameter \\em arg CONFIGURE </th></tr>\n<tr><th>Parameter \\em arg                   </th><th>               Bit    </th><th>            Category     </th><th>Description                             </th></tr>\n<tr><td>\\ref ARM_ETH_MAC_SPEED_10M          </td><td rowspan=\"3\">   0..1   </td><td rowspan=\"3\">Link Speed   </td><td>Set the link speed to \\token{10 [Mbps]} </td></tr>\n<tr><td>\\ref ARM_ETH_MAC_SPEED_100M         </td>                                                                 <td>Set the link speed to \\token{100 [Mbps]}</td></tr>\n<tr><td>\\ref ARM_ETH_MAC_SPEED_1G           </td>                                                                 <td>Set the link speed to \\token{1  [Gbps]} </td></tr>\n<tr><td>\\ref ARM_ETH_MAC_DUPLEX_HALF        </td><td rowspan=\"2\">   2      </td><td rowspan=\"2\">Link Mode    </td><td>Set the link mode to half duplex        </td></tr>\n<tr><td>\\ref ARM_ETH_MAC_DUPLEX_FULL        </td>                                                                 <td>Set the link mode to full duplex        </td></tr>\n<tr><td>n.a.                                </td><td>               3      </td><td>            n.a.         </td><td>\\em reserved                            </td></tr>                      \n<tr><td>\\ref ARM_ETH_MAC_LOOPBACK           </td><td>               4      </td><td>    Loopback Test Mode   </td><td>Set the interface into a Loop-back test mode</td></tr>\n<tr><td>\\ref ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX</td><td>               5      </td><td>Receiver Checksum offload</td><td>Enable Receiver Checksum offload        </td></tr>\n<tr><td>\\ref ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX</td><td>               6      </td><td>Transmitter Checksum offload</td><td>Enable Transmitter Checksum offload  </td></tr>\n<tr><td>\\ref ARM_ETH_MAC_ADDRESS_BROADCAST  </td><td>               7      </td><td>Broadcast Frame address  </td><td>Accept frames with Broadcast address    </td></tr>\n<tr><td>\\ref ARM_ETH_MAC_ADDRESS_MULTICAST  </td><td>               8      </td><td>Multicast Frame address  </td><td>Accept frames with any Multicast address</td></tr>\n<tr><td>\\ref ARM_ETH_MAC_ADDRESS_ALL        </td><td>               9      </td><td>Any Frame address        </td><td>Accept frames with any address (Promiscuous Mode)</td></tr>\n</table>\n\nThe table <b>Parameter \\em arg for FLUSH</b> lists the \\em arg values for the \\em control \\b ARM_ETH_MAC_FLUSH.\nThe \\em arg values can be ORed. \n\n<table class=\"cmtable\" summary=\"\">\n<tr><th colspan=\"4\">Parameter \\em arg for FLUSH </th></tr>\n<tr><th>Parameter \\em arg          </th><th>    Bit    </th><th>     Category     </th><th> Description                  </th></tr>\n<tr><td>\\ref ARM_ETH_MAC_FLUSH_RX  </td><td>    1      </td><td>  Receive buffer  </td><td> Flush the Receive buffer     </td></tr>\n<tr><td>\\ref ARM_ETH_MAC_FLUSH_TX  </td><td>    2      </td><td>  Transmit buffer </td><td> Flush the Transmit buffer    </td></tr>\n</table>\n\nThe table <b>Parameter \\em arg for VLAN Filter</b> lists the \\em arg values for the \\em control \\b ARM_ETH_MAC_VLAN_FILTER.\nThe \\em arg values can be ORed. \n\n<table class=\"cmtable\" summary=\"\">\n<tr><th colspan=\"4\">Parameter \\em arg for VLAN Filter</th></tr>\n<tr><th>Parameter \\em arg                     </th><th>              Bit    </th><th>             Category    </th><th> Description                                </th></tr>\n<tr><td>\\em value                             </td><td>              0..15  </td><td>             VLAN Tag    </td><td> Set VLAN Tag value                         </td></tr>\n<tr><td>\\token{0}                             </td><td rowspan=\"2\">  16     </td><td rowspan=\"2\"> Use of VLAN </td><td> Compare the complete 16-bit VLAN Tag value </td></tr>\n<tr><td>\\ref ARM_ETH_MAC_VLAN_FILTER_ID_ONLY  </td>                                                                <td>Compare only the 12-bit VLAN Identifier     </td></tr>\n<tr><td>\\token{0}                             </td><td>              0..16  </td><td>             Disable     </td><td> Disable the VLAN Filter                    </td></tr>\n</table>\n\n\n\\b Example:\n\n\\code\n...\n                                         // start transfer\n    mac->Control(ARM_ETH_MAC_CONFIGURE, ARM_ETH_MAC_SPEED_100M | ARM_ETH_MAC_DUPLEX_FULL | ARM_ETH_MAC_ADDRESS_BROADCAST);\n    mac->Control(ARM_ETH_MAC_CONTROL_TX, 1);\n    mac->Control(ARM_ETH_MAC_CONTROL_RX, 1);\n\t \n...                                      // stop transfer\n    mac->Control(ARM_ETH_MAC_FLUSH, ARM_ETH_MAC_FLUSH_TX | ARM_ETH_MAC_FLUSH_RX);\n    mac->Control(ARM_ETH_MAC_CONTROL_TX, 0);\n    mac->Control(ARM_ETH_MAC_CONTROL_RX, 0);\n  }\n}\n\\endcode\n\nFor a complete example, refer to  \\ref eth_interface_gr - Driver Functions.\n\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)\n\\details\nThe function \\b ARM_ETH_MAC_ControlTimer controls the timer required for PTP (Precision Time Protocol).\n\nThe parameter \\em control receives \\b ARM_ETH_MAC_TIMER_xxx codes to manage the timer for a PTP enabled Ethernet MAC interface. \\n\nThe parameter \\em time is pointer to a structure that holds time information.\n\nMode Parameters: Timer Controls         | Description\n:---------------------------------------|:--------------------------------------------\n\\ref ARM_ETH_MAC_TIMER_GET_TIME         | Retrieve the current time and update the content \\ref ARM_ETH_MAC_TIME *time.\n\\ref ARM_ETH_MAC_TIMER_SET_TIME         | Set the new time using the values provided with \\ref ARM_ETH_MAC_TIME *time.\n\\ref ARM_ETH_MAC_TIMER_INC_TIME         | Increment the current time by using the values provided with \\ref ARM_ETH_MAC_TIME *time.\n\\ref ARM_ETH_MAC_TIMER_DEC_TIME         | Decrement the current time by using the values provided with \\ref ARM_ETH_MAC_TIME *time.\n\\ref ARM_ETH_MAC_TIMER_SET_ALARM        | Set the alarm time to the values provided with \\ref ARM_ETH_MAC_TIME *time.  \n\\ref ARM_ETH_MAC_TIMER_ADJUST_CLOCK     | Set the clock frequency; the value in time->ns is the <b>correction factor</b> in fractional format q31.\n\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)\n\\details\n\nRead Ethernet PHY Register through the Management Interface. The function is passed to \\ref ARM_ETH_PHY_Initialize.\nThe Ethernet PHY driver uses this function to read the value of PHY registers.\n\n\\b Example:\n - see \\ref eth_interface_gr - Driver Functions\n*******************************************************************************************************************/\n\nint32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)  {\n  \n}\n/**\n\\fn int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)\n\\details\nThe function \\b ARM_ETH_MAC_PHY_Write writes to a Ethernet PHY register through the Management Interface.  The function is passed to \\ref ARM_ETH_PHY_Initialize.\nThe Ethernet PHY driver uses this function to write data to PHY registers.\n\n\\b Example:\n - see \\ref eth_interface_gr - Driver Functions\n\n*******************************************************************************************************************/\n\nvoid ARM_ETH_MAC_SignalEvent (uint32_t event)  {\n  ;\n}\n/**\n\\fn void ARM_ETH_MAC_SignalEvent (uint32_t event)\n\\details\n\nThe function \\b ARM_ETH_MAC_SignalEvent is a callback function registered by the function\n\\ref ARM_ETH_MAC_Initialize. This function is typically called from interrupt service routines (ISR) to indicate that\na frame is processed or a special event occurred.\n\nThe parameter \\a event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nNot every event is necessarily generated by the driver. This depends on the implemented capabilities stored in the \ndata fields of the structure \\ref ARM_ETH_MAC_CAPABILITIES, which can be retrieved with the function \\ref ARM_ETH_MAC_GetCapabilities.\n\nThe following events can be generated:\n\nParameter \\em event                      | Bit | Description \n:----------------------------------------|:---:|:----------------------------------------\n\\ref ARM_ETH_MAC_EVENT_RX_FRAME          |  0  | Occurs after a frame is received. Frame can be read by calling \\ref ARM_ETH_MAC_ReadFrame.\n\\ref ARM_ETH_MAC_EVENT_TX_FRAME          |  1  | Occurs after call to \\ref ARM_ETH_MAC_SendFrame to indicate that the frame is transmitted.\n\\ref ARM_ETH_MAC_EVENT_WAKEUP            |  2  | Indicates that a Magic Packet is received while the driver is in Sleep mode (set by \\ref ARM_ETH_MAC_SLEEP using \\ref ARM_ETH_MAC_Control).\n\\ref ARM_ETH_MAC_EVENT_TIMER_ALARM       |  3  | Indicates that a Timer Alarm occurred that was set with \\ref ARM_ETH_MAC_TIMER_SET_ALARM using ARM_ETH_MAC_ControlTimer.\n\n*******************************************************************************************************************/\n\n\n/**\n\\defgroup eth_mac_control Ethernet MAC Control Codes\n\\ingroup eth_mac_interface_gr\n\\brief Configure and control the Ethernet MAC using the \\ref ARM_ETH_MAC_Control.\n\\details \n@{\nMany parameters of the Ethernet MAC driver are configured using the \\ref ARM_ETH_MAC_Control function.\n\nThe various Ethernet MAC control codes define:\n  \n  - \\ref eth_mac_ctrls                configures and controls the Ethernet MAC interface\n  - \\ref eth_mac_configuration_ctrls  specifies speed mode, link mode, checksum, and frame filtering modes\n  - \\ref eth_mac_flush_flag_ctrls     specify controls to flush a buffer\n  - \\ref eth_mac_vlan_filter_ctrls    specifies whether to compare only the VLAN Identifier\n\nRefer to the \\ref ARM_ETH_MAC_Control function for further details.\n*/\n\n/**\n\\defgroup eth_mac_ctrls Ethernet MAC Controls\n\\brief Configure and control the Ethernet MAC interface.\n\\details\n@{\n\\def ARM_ETH_MAC_CONFIGURE          \n\\sa ARM_ETH_MAC_Control\n\\def ARM_ETH_MAC_CONTROL_TX         \n\\sa ARM_ETH_MAC_Control\n\\def ARM_ETH_MAC_CONTROL_RX         \n\\sa ARM_ETH_MAC_Control\n\\def ARM_ETH_MAC_FLUSH              \n\\sa ARM_ETH_MAC_Control\n\\def ARM_ETH_MAC_SLEEP              \n\\sa ARM_ETH_MAC_Control\n\\def ARM_ETH_MAC_VLAN_FILTER        \n\\sa ARM_ETH_MAC_Control\n@}\n*/\n\n\n/**\n\\defgroup eth_mac_configuration_ctrls Ethernet MAC Configuration\n\\brief Specifies speed mode, link mode, checksum, and frame filtering modes.\n\\details\n@{\nThe function \\ref ARM_ETH_MAC_Control with \\em control = \\ref ARM_ETH_MAC_CONFIGURE configures the Ethernet MAC interface\nas specified with \\em arg listed bellow.\n\n\\def ARM_ETH_MAC_SPEED_10M           \n\\def ARM_ETH_MAC_SPEED_100M          \n\\def ARM_ETH_MAC_SPEED_1G            \n\\def ARM_ETH_MAC_DUPLEX_HALF         \n\\def ARM_ETH_MAC_DUPLEX_FULL         \n\\def ARM_ETH_MAC_LOOPBACK            \n\\def ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX \n\\def ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX \n\\def ARM_ETH_MAC_ADDRESS_BROADCAST   \n\\def ARM_ETH_MAC_ADDRESS_MULTICAST   \n\\def ARM_ETH_MAC_ADDRESS_ALL         \n@}\n*/\n\n/**\n\\defgroup eth_mac_flush_flag_ctrls  Ethernet MAC Flush Flags\n\\brief Specify controls to flush a buffer\n\\details\n@{\nThe function \\ref ARM_ETH_MAC_Control with \\em control = \\ref ARM_ETH_MAC_FLUSH flushes the buffer\nwhich is specified with \\em arg listed bellow.\n\n\\def ARM_ETH_MAC_FLUSH_RX           \n\\def ARM_ETH_MAC_FLUSH_TX           \n@}\n*/\n\n\n/**\n\\defgroup eth_mac_vlan_filter_ctrls   Ethernet MAC VLAN Filter Flag\n\\brief Specify whether to compare only the VLAN Identifier\n\\details\n@{\nThe function \\ref ARM_ETH_MAC_Control with \\em control = \\ref ARM_ETH_MAC_VLAN_FILTER configures the VLAN Filter for received frames as specified with \\em arg.\n\nBy default the complete VLAN Tag (16-bit) is compared. When \\ref ARM_ETH_MAC_VLAN_FILTER_ID_ONLY is specified then only the VLAN Identifier (12-bit) is compared.\n\nSpecifying \\em arg=0 disables the VLAN Filter. \n\n\\def ARM_ETH_MAC_VLAN_FILTER_ID_ONLY \n@}\n*/\n\n\n/**\n@} */  // end group eth_mac_control \n\n\n/**\n\\defgroup eth_mac_time_control Ethernet MAC Timer Control Codes\n\\ingroup eth_mac_interface_gr\n\\brief Control codes for \\ref ARM_ETH_MAC_ControlTimer function.\n\\details \nThe following timer controls are used as parameter \\em control for the \\ref ARM_ETH_MAC_ControlTimer function:\n@{\n\\def ARM_ETH_MAC_TIMER_GET_TIME     \n\\sa ARM_ETH_MAC_ControlTimer\n\\def ARM_ETH_MAC_TIMER_SET_TIME     \n\\sa ARM_ETH_MAC_ControlTimer\n\\def ARM_ETH_MAC_TIMER_INC_TIME     \n\\sa ARM_ETH_MAC_ControlTimer\n\\def ARM_ETH_MAC_TIMER_DEC_TIME     \n\\sa ARM_ETH_MAC_ControlTimer\n\\def ARM_ETH_MAC_TIMER_SET_ALARM    \n\\sa ARM_ETH_MAC_ControlTimer\n\\def ARM_ETH_MAC_TIMER_ADJUST_CLOCK \n\\sa ARM_ETH_MAC_ControlTimer\n@}\n*/\n\n\n/**\n\\defgroup eth_mac_frame_transmit_ctrls Ethernet MAC Frame Transmit Flags\n\\brief Specify frame transmit flags\n\\details\n@{\n\\def ARM_ETH_MAC_TX_FRAME_FRAGMENT  \n\\sa ARM_ETH_MAC_SendFrame\n\\def ARM_ETH_MAC_TX_FRAME_EVENT     \n\\sa ARM_ETH_MAC_SendFrame\n\\def ARM_ETH_MAC_TX_FRAME_TIMESTAMP \n\\sa ARM_ETH_MAC_SendFrame\n@}\n*/\n\n\n\n/**\n@}\n*/ \n// End ETH MAC Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_ETH_PHY.c",
    "content": "/**\n\\defgroup eth_phy_interface_gr Ethernet PHY Interface\n\\ingroup eth_interface_gr\n\\brief Driver API for Ethernet PHY Peripheral (%Driver_ETH_PHY.h)\n\\details The following section describes the Ethernet PHY Interface as defined in the %Driver_ETH_PHY.h header file.\n\nThe %Driver_ETH_PHY.h contains two \\#defines that are used to configure the connection between the PHY and the\nmicrocontroller device:\n- \\c ETH_PHY_NUM and\n- \\c ETH_PHY_ADDR\n\nUsually, the Serial Management Interface (\\b SMI) (using MDC and MDIO) is used to access the PHY’s internal registers to read\nthe state of the link (up/down), duplex mode, speed, and to restart auto-negotiation etc. SMI is a serial bus, which allows\nto connect up to 32 devices. Devices on the bus are accessed using a 5-bit device address. A default device address is\nhardware configurable by pin-strapping on the device (some pins are sampled when a reset is asserted or at power-up).\n\nThe device’s internal weak pull-up or pull-down resistors define a default device address. This address can be changed by\nconnecting strong pull-up or pull-down resistors externally. In this case, the \\c ETH_PHY_ADDR needs to be defined by the\nuser.\n\nIf a microcontroller device offers more than one Ethernet PHY driver, the user needs to set the correct \\c ETH_PHY_NUM in his\napplication.\n@{\n*/\n\n/**\n\\struct     ARM_DRIVER_ETH_PHY\n\\details\nThe functions of the Ethernet PHY are accessed by function pointers exposed by this structure. Refer to \\ref DriverFunctions for \noverview information.\n\nEach instance of an Ethernet PHY provides such an access struct. The instance is identified by\na postfix number in the symbol name of the access struct, for example:\n - \\b Driver_ETH_PHY0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_ETH_PHY1 is the name of the access struct of the second instance (no. 1).\n\n\nA configuration setting in the middleware allows connecting the middleware to a specific driver instance <b>Driver_ETH_PHY<i>n</i></b>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*****************************************************************************************************************/\n\n\n/**\n\\typedef    ARM_ETH_PHY_Read_t\n\\details\nProvides the typedef for the register read function \\ref ARM_ETH_MAC_PHY_Read.\n\n<b>Parameter for:</b>\n  - \\ref ARM_ETH_PHY_Initialize\n*******************************************************************************************************************/\n\n/**\n\\typedef    ARM_ETH_PHY_Write_t\n\\details\nProvides the typedef for the register write function \\ref ARM_ETH_MAC_PHY_Write.\n\n<b>Parameter for:</b>\n  - \\ref ARM_ETH_PHY_Initialize\n*******************************************************************************************************************/\n\n\n//\n// Functions\n//\n\nARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn     ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)\n\\details\nThe function \\b ARM_ETH_PHY_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_ETH_PHY Driver_ETH_PHY0;\nARM_DRIVER_ETH_PHY *drv_info;\n \nvoid setup_ethernet_phy (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_ETH_PHY0;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*****************************************************************************************************************/\n\nint32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write)  {\n  return 0;\n}\n/**\n\\fn       int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write)\n\\details\nThe function \\b ARM_ETH_PHY_Initialize initializes the Ethernet PHY interface. \nIt is called when the middleware component starts operation.\n\nThe \\ref ARM_ETH_PHY_Initialize function performs the following operations:\n  - Initializes the resources needed for Ethernet PHY peripheral.\n  - Registers the \\ref ARM_ETH_MAC_PHY_Read register read access function.\n  - Registers the \\ref ARM_ETH_MAC_PHY_Write register write access function.\n\n\\b Example:\n - see \\ref eth_interface_gr - Driver Functions\n\n*****************************************************************************************************************/\n\nint32_t ARM_ETH_PHY_Uninitialize (void)  {\n  return 0;\n}\n/**\n\\fn       int32_t ARM_ETH_PHY_Uninitialize (void)\n\\details\nThe function \\b ARM_ETH_PHY_Uninitialize de-initializes the resources of Ethernet PHY interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n*****************************************************************************************************************/\n\nint32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)\n\\details     \nThe function \\b ARM_ETH_PHY_PowerControl operates the power modes of the Ethernet PHY interface.  \n\nThe parameter \\em state sets the operation and can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. \n                          Can be called multiple times. If the peripheral is already in this mode the function performs \n\t\t\t\t\t\t  no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n\n\\b Example:\n - see \\ref eth_interface_gr - Driver Functions\n*****************************************************************************************************************/\n\nint32_t ARM_ETH_PHY_SetInterface (uint32_t interface)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_ETH_PHY_SetInterface (uint32_t interface)\n\n\\details\nThe function \\b ARM_ETH_PHY_SetInterface specifies the \\ref eth_interface_types1 that links the Ethernet MAC and Ethernet PHY. \nAfter initialization of the PHY interface, you can set the media type.\nThe function \\ref ARM_ETH_MAC_GetCapabilities retrieves the media interface type encoded in the data field \\b media_interface of the structure\n\\ref ARM_ETH_MAC_CAPABILITIES. \n\nThe parameter \\em interface can have the following values:\n\nParameter \\em interface       | Media Type\n:-----------------------------|:-------------------------\n\\ref ARM_ETH_INTERFACE_MII    | Media Independent Interface (MII)\n\\ref ARM_ETH_INTERFACE_RMII   | Reduced Media Independent Interface (RMII)\n\\ref ARM_ETH_INTERFACE_SMII   | Serial Media Independent Interface (SMII); \n\n\\note\nSome \\em interface values may be unsupported by a driver implementation. For example \\ref ARM_ETH_INTERFACE_SMII may return \\b ARM_DRIVER_ERROR_UNSUPPORTED.\n\n\\b Example:\n\\code\nstatic ARM_ETH_MAC_CAPABILITIES capabilities;\nstatic ARM_DRIVER_ETH_MAC *mac;\nstatic ARM_DRIVER_ETH_PHY *phy;\n \nmac = &Driver_ETH_MAC0;\nphy = &Driver_ETH_PHY0;\n \n// Initialize Media Access Controller\ncapabilities = mac->GetCapabilities ();\n...\nstatus = phy->SetInterface (capabilities.media_interface);\nif (status != ARM_DRIVER_OK) ...  // error handling\nstatus = phy->SetMode (ARM_ETH_PHY_AUTO_NEGOTIATE);\nif (status != ARM_DRIVER_OK) ...  // error handling\n...\n\\endcode\n*****************************************************************************************************************/\n\nint32_t ARM_ETH_PHY_SetMode (uint32_t mode)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_ETH_PHY_SetMode (uint32_t mode)\n\\details\nThe function \\b ARM_ETH_PHY_SetMode sets the operation mode parameters for the Ethernet PHY.\n\n\nThe table below lists the possible values for the parameter \\em mode. Values from different categories can be ORed as shown in this example code:\n\n\\code\nphy->SetMode (ARM_ETH_PHY_SPEED_100M | ARM_ETH_PHY_LOOPBACK | ARM_ETH_PHY_DUPLEX_HALF );\n\\endcode\n\\n\n\n<table class=\"cmtable\" summary=\"\">\n<tr><th>Parameter \\em mode              </th><th> bit              </th><th> Category              </th> <th>Description</th></tr>\n<tr><td>\\ref ARM_ETH_PHY_SPEED_10M      </td><td rowspan=\"3\"> 0..1 </td><td rowspan=\"3\">Link Speed </td> <td>Set the link speed to \\token{10 [Mbps]}     </td></tr>\n<tr><td>\\ref ARM_ETH_PHY_SPEED_100M     </td>                                                      <td>Set the link speed to \\token{100 [Mbps]}          </td></tr>\n<tr><td>\\ref ARM_ETH_PHY_SPEED_1G       </td>                                                      <td>Set the link speed to \\token{1  [Gbps]}           </td></tr>\n<tr><td>\\ref ARM_ETH_PHY_DUPLEX_HALF    </td><td rowspan=\"2\"> 2    </td><td rowspan=\"2\">Link Mode  </td> <td>Set the link mode to half duplex            </td></tr>\n<tr><td>\\ref ARM_ETH_PHY_DUPLEX_FULL    </td>                                                      <td>Set the link mode to full duplex                  </td></tr>\n<tr><td>\\ref ARM_ETH_PHY_AUTO_NEGOTIATE </td><td>           3      </td><td>Autonegotiation        </td> <td>Set the interface to Auto Negotiation mode of transmission parameters</td></tr>\n<tr><td>\\ref ARM_ETH_PHY_LOOPBACK       </td><td>           4      </td><td>Loopback               </td> <td>Set the interface into a Loop-back test mode      </td></tr>\n<tr><td>\\ref ARM_ETH_PHY_ISOLATE        </td><td>           5      </td><td>Isolation              </td> <td>Set to indicate electrical isolation of PHY interface from MII/RMII interface</td></tr>\n</table>\n\n\\note\nSome settings may be also taken from configuration pins (example \\ref ARM_ETH_PHY_ISOLATE). Check the effect of mode settings in the actual driver implementation.\n\\note\nSome \\em mode values may be unsupported by a driver implementation. For example \\ref ARM_ETH_PHY_SPEED_1G may return \\b ARM_DRIVER_ERROR_UNSUPPORTED.\n\n\n\\b Example:\n\\code\nstatic ARM_ETH_MAC_CAPABILITIES capabilities;\nstatic ARM_DRIVER_ETH_MAC *mac;\nstatic ARM_DRIVER_ETH_PHY *phy;\n \nmac = &Driver_ETH_MAC0;\nphy = &Driver_ETH_PHY0;\n \n// Initialize Media Access Controller\ncapabilities = mac->GetCapabilities ();\n...\nstatus = phy->SetInterface (capabilities.media_interface);\nif (status != ARM_DRIVER_OK) ...  // error handling\nstatus = phy->SetMode (ARM_ETH_PHY_SPEED_100M | ARM_ETH_PHY_DUPLEX_FULL | ARM_ETH_PHY_ISOLATE);\nif (status != ARM_DRIVER_OK) ...  // error handling\n...\n\\endcode\n\n\n\n*****************************************************************************************************************/\n\nARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)  {\n  return 0;\n}\n/**\n\\fn ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)\n\\details\nThe function \\b ARM_ETH_PHY_GetLinkState retrieves the connection status of the physical Ethernet link.\n\n\\b Example:\n - see \\ref eth_interface_gr - Driver Functions\n*****************************************************************************************************************/\n\nARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)  {\n  return 0;\n}\n/**\n\\fn ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)\n\\details\nThe function \\b ARM_ETH_PHY_GetLinkInfo retrieves information about the current established communication\nmode (half/full duplex) and communication speed. Information is only valid when link is up (see \\ref ARM_ETH_PHY_GetLinkState).\n\n\\b Example:\n - see \\ref eth_interface_gr - Driver Functions\n*****************************************************************************************************************/\n\n\n/**\n@}\n*/ \n// End ETH PHY Interface group; below the groups are included with \\ingroup\n\n\n/**\n\\defgroup eth_phy_mode_ctrls Ethernet PHY Mode\n\\ingroup eth_phy_interface_gr\n\\brief Specify operation modes of the Ethernet PHY interface\n\\details\n@{\n\\def ARM_ETH_PHY_SPEED_10M \n\\sa ARM_ETH_PHY_SetMode\n\\def ARM_ETH_PHY_SPEED_100M\n\\sa ARM_ETH_PHY_SetMode\n\\def ARM_ETH_PHY_SPEED_1G  \n\\sa ARM_ETH_PHY_SetMode\n\\def ARM_ETH_PHY_DUPLEX_HALF\n\\sa ARM_ETH_PHY_SetMode\n\\def ARM_ETH_PHY_DUPLEX_FULL\n\\sa ARM_ETH_PHY_SetMode\n\\def ARM_ETH_PHY_AUTO_NEGOTIATE\n\\sa ARM_ETH_PHY_SetMode\n\\def ARM_ETH_PHY_LOOPBACK      \n\\sa ARM_ETH_PHY_SetMode\n\\def ARM_ETH_PHY_ISOLATE       \n\\sa ARM_ETH_PHY_SetMode\n@}\n*/\n\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_Flash.c",
    "content": "/**\n\\defgroup flash_interface_gr Flash Interface\n\\brief    Driver API for Flash Device Interface (%Driver_Flash.h)\n\\details\n<a href=\"http://en.wikipedia.org/wiki/Flash_memory\" target=\"_blank\">Flash devices</a> based on NOR memory cells are the\npreferred technology for embedded applications requiring a discrete non-volatile memory device. The low read latency\ncharacteristic of these Flash devices allow a direct code execution\n(<a href=\"http://en.wikipedia.org/wiki/Execute_in_place\" target=\"_blank\">XIP</a>) and data storage in a single memory\nproduct.\n\n<b>Flash API</b>\n\nThe Flash API provides a generic API suitable for Flashes with NOR memory cells independent from the actual interface\nto the MCU (memory bus, SPI, ...). <a href=\"http://en.wikipedia.org/wiki/Flash_memory#Serial_flash\" target=\"_blank\">SPI</a>\nflashes are typically not named NOR flashes but have usually same flash cell properties. \n\nThe following header files define the Application Programming Interface (API) for the Flash interface:\n  - \\b %Driver_Flash.h : Driver API for Flash Device Interface\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_FLASH : access struct for Flash driver functions\n@{\n\nA typical setup sequence for the driver is shown below:\n\n<b>Example Code:</b>\n\n\\include Flash_Demo.c\n*/\n*******************************************************************************************************************/\n\n\n/**\n\\defgroup Flash_events Flash Events\n\\ingroup flash_interface_gr\n\\brief The Flash driver generates call back events that are notified via the function \\ref ARM_Flash_SignalEvent.\n\\details \nThis section provides the event values for the \\ref ARM_Flash_SignalEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def ARM_FLASH_EVENT_READY\n\\def ARM_FLASH_EVENT_ERROR\n@}\n*/\n\n\n/**\n\\struct     ARM_FLASH_SECTOR \n\\details  \nSpecifies sector start and end address.\n\n<b>Element of</b>:\n  - \\ref ARM_FLASH_INFO structure\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_FLASH_INFO \n\\details \nStores the characteristics of a Flash device. This includes sector layout, programming size and a default value for erased memory.\nThis information can be obtained from the Flash device datasheet and is used by the middleware in order to properly interact with the Flash device.\n\nSector layout is described by specifying the \\em sector_info which points to an array of sector information (start and end address) and by specifying the \\em sector_count which defines the number of sectors.\nThe element \\em sector_size is not used in this case and needs to be \\em 0.\nFlash sectors need not to be aligned continuously. Gaps are allowed in the device memory space in order to reserve sectors for other usage (for example application code).\n\nWhen the device has uniform sector size than the sector layout can be described by specifying the \\em sector_size which defines the size of a single sector and by specifying the \\em sector_count which defines the number of sectors.\nThe element \\em sector_info is not used in this case and needs to be \\em NULL.\n\nThe smallest programmable unit within a sector is specified by the \\em program_unit. It defines the granularity for programming data.\n\nOptimal programming page size is specified by the \\em page_size and defines the amount of data that should be programmed in one step to achieve maximum programming speed.\n\nContents of erased memory is specified by the \\em erased_value and is typically \\em 0xFF. This value can be used before erasing a sector to check if the sector is blank and erase can be skipped.\n\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_DRIVER_FLASH\n\\details \nThe functions of the Flash driver are accessed by function pointers exposed by this structure. Refer to \\ref DriverFunctions for overview information.\n\nEach instance of a Flash interface provides such an access structure. \nThe instance is identified by a postfix number in the symbol name of the access structure, for example:\n - \\b Driver_Flash0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_Flash1 is the name of the access struct of the second instance (no. 1).\n\nA middleware configuration setting allows connecting the middleware to a specific driver instance \\b %Driver_Flash<i>n</i>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_FLASH_CAPABILITIES \n\\details\nA Flash driver can be implemented with different capabilities. The data fields of this struct encode \nthe capabilities implemented by this driver.\n\nThe element \\em event_ready indicates that the driver is able to generate the \\ref ARM_FLASH_EVENT_READY event. In case that this event is not available it is possible to poll the driver status by calling the \\ref ARM_Flash_GetStatus and check the \\em busy flag.\n\nThe element \\em data_width specifies the data access size and also defines the data type (uint8_t, uint16_t or uint32_t) for the \\em data parameter in \\ref ARM_Flash_ReadData and \\ref ARM_Flash_ProgramData functions.\n\nThe element \\em erase_chip specifies that the \\ref ARM_Flash_EraseChip function is supported. Typically full chip erase is much faster than erasing the whole device sector per sector.\n\n<b>Returned by:</b>\n  - \\ref ARM_Flash_GetCapabilities\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_FLASH_STATUS\n\\details\nStructure with information about the status of the Flash.\n\nThe flag \\em busy indicates that the driver is busy executing read/program/erase operation.\n\nThe flag \\em error flag is cleared on start of read/program/erase operation and is set at the end of the current operation in case of error.\n\n<b>Returned by:</b>\n  - \\ref ARM_Flash_GetStatus\n*****************************************************************************************************************/\n\n/**\n\\typedef    ARM_Flash_SignalEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_Flash_SignalEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_Flash_Initialize\n*******************************************************************************************************************/\n\n\n//\n// Functions\n//\n\nARM_DRIVER_VERSION ARM_Flash_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)\n\\details\nThe function \\b ARM_Flash_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_FLASH Driver_Flash0;\nARM_DRIVER_FLASH *drv_info;\n \nvoid read_version (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_Flash0;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*******************************************************************************************************************/\n\nARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)  {\n  return { 0 };\n}\n/**\n\\fn ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)\n\\details\nThe function \\b ARM_Flash_GetCapabilities returns information about capabilities in this driver implementation.\nThe data fields of the struct \\ref ARM_FLASH_CAPABILITIES encode various capabilities, for example\nif a hardware is able to create signal events using the \\ref ARM_Flash_SignalEvent callback function.\n \nExample:\n\\code\nextern ARM_DRIVER_FLASH Driver_Flash0;\nARM_DRIVER_FLASH *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_FLASH_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_Flash0;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*******************************************************************************************************************/\n\nint32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)\n\\details\nThe function \\b ARM_Flash_Initialize initializes the Flash interface.\nIt is called when the middleware component starts operation.\n\nThe function performs the following operations:\n  - Initializes the resources needed for the Flash interface.\n  - Registers the \\ref ARM_Flash_SignalEvent callback function.\n\nThe parameter \\em cb_event is a pointer to the \\ref ARM_Flash_SignalEvent callback function; use a NULL pointer \nwhen no callback signals are required.\n\n\\b Example:\n - see \\ref flash_interface_gr - Driver Functions\n\n*******************************************************************************************************************/\n\nint32_t ARM_Flash_Uninitialize (void)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Flash_Uninitialize (void)\n\\details\nThe function \\b ARM_Flash_Uninitialize de-initializes the resources of Flash interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n*******************************************************************************************************************/\n\nint32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_Flash_PowerControl operates the power modes of the Flash interface.\n\nThe parameter \\em state can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. Can be called multiple times. \n                          If the peripheral is already in this mode, then the function performs no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n*******************************************************************************************************************/\n\nint32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)\n\\details  \nThis function \\b ARM_Flash_ReadData reads data from the Flash device.\n\nThe parameter \\em addr specifies the address from where to read data (needs to be aligned to data type size). \\n\nThe parameter \\em data specifies the pointer to a buffer storing the data read. \nThe data type is \\em uint8_t, \\em uint16_t or \\em uint32_t and is specified by the \\em data_width in \\ref ARM_FLASH_CAPABILITIES. \\n\nThe parameter \\em cnt specifies the number of data items to read.\n\nThe function executes in the following ways:\n - When the operation is non-blocking (typical for SPI Flash) then the function only starts the operation and returns with zero number of data items read. \n   When the operation is completed the \\ref ARM_FLASH_EVENT_READY event is generated (if supported and reported by \\ref ARM_Flash_GetCapabilities).\n   In case of errors the \\ref ARM_FLASH_EVENT_ERROR event is generated at the same time.   \n   Progress of the operation can also be monitored by calling the \\ref ARM_Flash_GetStatus function and checking the \\em busy flag.\n - When the operation is blocking (typical for memory mapped Flash) then the function returns after the data is read and returns the number of data items read.\n*******************************************************************************************************************/\n\nint32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)\n\\details  \nThis function \\b ARM_Flash_ProgramData programs data to the Flash device.\n\nThe parameter \\em addr specifies the address to where to program data (needs to be aligned to \\em program_unit specified in \\ref ARM_FLASH_INFO). \\n\nThe parameter \\em data specifies the pointer to a buffer containing data to be programmed. \nThe data type is \\em uint8_t, \\em uint16_t or \\em uint32_t and is specified by the \\em data_width in \\ref ARM_FLASH_CAPABILITIES. \\n\nThe parameter \\em cnt specifies the number of data items to program (data size needs to be a multiple of \\em program_unit).\n\nThe function executes in the following ways:\n - When the operation is non-blocking (typically) then the function only starts the operation and returns with zero number of data items programmed. \n   When the operation is completed the \\ref ARM_FLASH_EVENT_READY event is generated (if supported and reported by \\ref ARM_Flash_GetCapabilities).\n   In case of errors the \\ref ARM_FLASH_EVENT_ERROR event is generated at the same time.\n   Progress of the operation can also be monitored by calling the \\ref ARM_Flash_GetStatus function and checking the \\em busy flag.\n - When the operation is blocking then the function returns after the data is programmed and returns the number of data items programmed.\n*******************************************************************************************************************/\n\nint32_t ARM_Flash_EraseSector (uint32_t addr)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Flash_EraseSector (uint32_t addr)\n\\details  \nThis function \\b ARM_Flash_EraseSector erases a flash sector specified by the parameter <i>adr</i> (points to start of the sector).\n\nThe function is non-blocking and returns as soon as the driver has started the operation.\nWhen the operation is completed the \\ref ARM_FLASH_EVENT_READY event is generated (if supported and reported by \\ref ARM_Flash_GetCapabilities).\nIn case of errors the \\ref ARM_FLASH_EVENT_ERROR event is generated at the same time.\nProgress of the operation can also be monitored by calling the \\ref ARM_Flash_GetStatus function and checking the \\em busy flag.\n*******************************************************************************************************************/\n\nint32_t ARM_Flash_EraseChip (void)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Flash_EraseChip (void)\n\\details  \nThe optional function \\b ARM_Flash_EraseChip erases the complete device.\nIf the device does not support global erase or only a portion of the Flash memory space is used for storing files,\nthen the functions returns the error value \\ref ARM_DRIVER_ERROR_UNSUPPORTED.\nThe data field \\em eras_chip = \\token{1} of the structure \\ref ARM_FLASH_CAPABILITIES encodes that \\b ARM_Flash_EraseChip is supported.\nThe field can be verified with the function \\ref ARM_Flash_GetCapabilities.\n\nThe function is non-blocking and returns as soon as the driver has started the operation.\nWhen the operation is completed, the \\ref ARM_FLASH_EVENT_READY event is generated (if supported and reported by \\ref ARM_Flash_GetCapabilities).\nIn case of errors, the \\ref ARM_FLASH_EVENT_ERROR event is generated at the same time.\nProgress of the operation can also be monitored by calling the \\ref ARM_Flash_GetStatus function and checking the \\em busy flag.\n\n<b>See also:</b>\n - ARM_Flash_SignalEvent\n*******************************************************************************************************************/\n\nARM_FLASH_STATUS ARM_Flash_GetStatus (void)  {\n  return 0;\n}\n/**\n\\fn ARM_FLASH_STATUS ARM_Flash_GetStatus (void)\n\\details\nThe function \\b ARM_Flash_GetStatus returns the current Flash interface status stored in the structure \\ref ARM_FLASH_STATUS.\n*******************************************************************************************************************/\n\nARM_FLASH_INFO * ARM_Flash_GetInfo (void)  {\n  return NULL;\n}\n/**\n\\fn ARM_FLASH_INFO * ARM_Flash_GetInfo (void)\n\\details\nThe function \\b ARM_Flash_GetInfo returns information about the Flash device.\n*******************************************************************************************************************/\n\nvoid ARM_Flash_SignalEvent (uint32_t event)  {\n  return 0;\n}\n/**\n\\fn void ARM_Flash_SignalEvent (uint32_t event)\n\\details\n\nThe function \\b ARM_Flash_SignalEvent is a callback function registered by the function \\ref ARM_Flash_Initialize. \nThe function is called automatically after read/program/erase operation completes.\n\nThe parameter \\em event indicates one or more events that occurred during driver operation. Each event is coded in a separate bit and\ntherefore it is possible to signal multiple events in the event call back function. \n\nNot every event is necessarily generated by the driver. This depends on the implemented capabilities stored in the \ndata fields of the structure \\ref ARM_FLASH_CAPABILITIES, which can be retrieved with the function \\ref ARM_Flash_GetCapabilities.\n\nThe following events can be generated:\n\nParameter \\em event                 | Bit | Description \n:-----------------------------------|:---:|:-----------\n\\ref ARM_FLASH_EVENT_READY          |  0  | Occurs after read/program/erase operation completes.\n\\ref ARM_FLASH_EVENT_ERROR          |  1  | Occurs together with \\ref ARM_FLASH_EVENT_READY when operation completes with errors.\n\n<b>See also:</b>\n - \\ref ARM_Flash_EraseChip\n*******************************************************************************************************************/\n\n/**\n@}\n*/ \n// End Flash Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_I2C.c",
    "content": "/**\n\\defgroup i2c_interface_gr I2C Interface\n\\brief    Driver API for I2C Bus Peripheral (%Driver_I2C.h)\n\\details\n\nI<sup>2</sup>C (Inter-Integrated Circuit, referred to as I-squared-C, I-two-C, or IIC) is a multi-master serial single-ended bus and is mostly used \non single boards, but can also connect to components which are linked via cable. \n\nMost significant features of the I<sup>2</sup>C bus include:\n - Only two bus lines are required\n - I<sup>2</sup>C is a true multi-master bus. Simple master/slave relationships exist between all components\n - A baud rate is not required; the master device determines a bus clock\n - Each connected device is addressable by a unique address\n - Providing arbitration and collision detection\n\nFor more information about I<sup>2</sup>C refer to the following web pages:\n  - Wikipedia: <a href=\"http://en.wikipedia.org/wiki/I%C2%B2C\" target=\"_blank\">I<sup>2</sup>C</a>\n  - <a href=\"http://www.i2c-bus.org\" target=\"_blank\">www.i2c-bus.org</a>.\n\nDevices can operation in Master or Slave mode:\n\n - To operate in Master mode call the functions \\ref ARM_I2C_MasterTransmit or \\ref ARM_I2C_MasterReceive. These functions get as argument a <em>slave address</em>. \n \n - To operate in Slave mode set the <em>slave address</em> using the function \\ref ARM_I2C_Control. The functions \\ref ARM_I2C_SlaveTransmit or \\ref ARM_I2C_SlaveReceive are used to transfer data in Slave mode.\n\n<b>I<sup>2</sup>C Slave Address</b>\n \nDepending on the device, I<sup>2</sup>C supports 7-bit and 10-bit Slaves addresses. \nThe element <em>address_10_bit</em> in \\ref ARM_I2C_CAPABILITIES indicates that the driver is able to handle 10-bit addresses.\nA 10-bit Slave address is ORed with \\ref ARM_I2C_ADDRESS_10BIT.\n \nI<sup>2</sup>C also supports a General Call to all Slaves by using the slave address value \\token{0}.\nA General Call is recognized by Slaves have a slave address value \\ref ARM_I2C_ADDRESS_GC registered with the \nfunction \\ref ARM_I2C_Control.\n\n<b>Block Diagram</b>\n\nThe I2C driver allows you to connect low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. \n\n\\image html I2C_BlockDiagram.png  \"Master/Slave connected via I2C interface\"\n\n\n<b>I<sup>2</sup>C API</b>\n\nThe following header files define the Application Programming Interface (API) for the I<sup>2</sup>C interface:\n  - \\b %Driver_I2C.h : Driver API for I2C Bus Peripheral\n\nThe driver implementation is a typical part of the Device Family Pack (DFP) that supports the \nperipherals of the microcontroller family.\n\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_I2C : access struct for I2C driver functions\n\n\n\\anchor example <b>Example Code</b>\n\nThe following example code shows the usage of the I<sup>2</sup>C interface in Master mode.\n\n\\include I2C_Demo.c\n\nThe following example code shows the usage of the I<sup>2</sup>C interface in Slave mode.\n\n\\include I2C_SlaveDemo.c\n\n@{\n*/\n\n\n/**\n\\struct     ARM_DRIVER_I2C\n\\details\nThe functions of the I2C interface are accessed by function pointers exposed by this structure. Refer to \\ref DriverFunctions for \noverview information.\n\nEach instance of an I2C provides such an access structure. The instance is indicated by\na postfix in the symbol name of the access structure, for example:\n - \\b Driver_I2C0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_I2C1 is the name of the access struct of the second instance (no. 1).\n\n\nA configuration setting in the middleware allows connecting the middleware to a specific driver instance <b>%Driver_I2C<i>n</i></b>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_I2C_CAPABILITIES\n\\details\nAn I2C driver can be implemented with different capabilities.\nThe data fields of this struct encode the capabilities implemented by this driver.\n\nThe element \\em address_10_bit indicates that the driver is able to handle 10-bit addressing natively.\nUser can still emulate the 10-bit addressing in software if the driver does not support it.\n\n<b>Returned by:</b>\n  - \\ref ARM_I2C_GetCapabilities\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_I2C_STATUS\n\\details\nStructure with information about the status of the I2C.\n\nThe flag \\em busy indicates that the driver is busy executing Master/Slave Transmit/Receive operation.\n\nIt is set:\n - when Master operation starts: after calling \\ref ARM_I2C_MasterTransmit or \\ref ARM_I2C_MasterReceive\n - when Slave operation starts: after calling \\ref ARM_I2C_SlaveTransmit or \\ref ARM_I2C_SlaveReceive and after being addressed by a Master as the Slave\n\nIt is cleared when Master/Slave operation has finished.\n\nThe flag \\em mode indicates the current mode which is Master when Master Transmit/Receive is active or Slave otherwise.\n\nThe flag \\em direction indicates either Transmitter or Receiver mode. It is updated during Master/Slave operation when the Slave is addressed by a Master.\n\nThe flag \\em general_call indicates a General call (address \\token{0}) when in Slave mode.\n\nThe flag \\em arbitration_lost indicates that the Master has lost arbitration. The current Master operation is aborted.\n\nThe flag \\em bus_error indicates that a bus error has been detected. The current Master/Slave operation is aborted.\n\n<b>Returned by:</b>\n  - \\ref ARM_I2C_GetStatus\n*******************************************************************************************************************/\n\n/**\n\\typedef    ARM_I2C_SignalEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_I2C_SignalEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_I2C_Initialize\n*******************************************************************************************************************/\n\n/**\n\\defgroup I2C_events I2C Events\n\\ingroup i2c_interface_gr\n\\brief The I2C driver generates call back events that are notified via the function \\ref ARM_I2C_SignalEvent.\n\\details \nThis section provides the event values for the \\ref ARM_I2C_SignalEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def  ARM_I2C_EVENT_TRANSFER_DONE\n\\def  ARM_I2C_EVENT_TRANSFER_INCOMPLETE\n\\def  ARM_I2C_EVENT_SLAVE_TRANSMIT\n\\def  ARM_I2C_EVENT_SLAVE_RECEIVE\n\\def  ARM_I2C_EVENT_ADDRESS_NACK\n\\def  ARM_I2C_EVENT_GENERAL_CALL\n\\def  ARM_I2C_EVENT_ARBITRATION_LOST\n\\def  ARM_I2C_EVENT_BUS_ERROR\n\\def  ARM_I2C_EVENT_BUS_CLEAR\n@}\n*/\n\n\n//\n//  Functions\n//\n\nARM_DRIVER_VERSION ARM_I2C_GetVersion (void)  {\n  return { 0, 0 };\n};\n/**\n\\fn       ARM_DRIVER_VERSION ARM_I2C_GetVersion (void)\n\\details\nThe function \\b ARM_I2C_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_I2C Driver_I2C0;\nARM_DRIVER_I2C *drv_info;\n \nvoid setup_i2c (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_I2C0;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*******************************************************************************************************************/\n\nARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)  {\n  return { 0 };\n};\n/**\n\\fn       ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)\n\\details\nThe function \\b ARM_I2C_GetCapabilities returns information about capabilities of this driver implementation.\nThe data fields of the struct \\ref ARM_I2C_CAPABILITIES encodes the driver capabilities.\n \nExample:\n\\code\nextern ARM_DRIVER_I2C Driver_I2C0;\nARM_DRIVER_I2C *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_I2C_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_I2C0;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*******************************************************************************************************************/\n\nint32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event) {\n  return ARM_DRIVER_OK;\n};\n/**\n\\fn       int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)\n\\details \nThe function \\b ARM_I2C_Initialize initializes the I2C interface. \nIt is called when the middleware component starts operation.\n\nThe function performs the following operations:\n  - Initializes and the I/O resources for the I2C interface.\n  - Registers the \\ref ARM_I2C_SignalEvent callback function.\n\nThe parameter \\em cb_event is a pointer to the \\ref ARM_I2C_SignalEvent callback function.\nUse a NULL pointer when no callback events are required.\n\nCan be called multiple times. If the peripheral is already initialized the function performs no operation and \nreturns with \\ref ARM_DRIVER_OK. Refer to \\ref CallSequence for more information.\n\n\\sa ARM_I2C_PowerControl\n\\sa ARM_I2C_Uninitialize\n\n\\b Example:\n - refer to \\ref example \"Example Code\"\n \n*******************************************************************************************************************/\n\nint32_t ARM_I2C_Uninitialize (void)  {\n  return ARM_DRIVER_OK;\n};\n/**\n\\fn       int32_t ARM_I2C_Uninitialize (void)\n\\details\nThe function \\b ARM_I2C_Uninitialize releases the I/O resources of I2C interface.\n\nIt is called when the middleware component stops operation and releases the I/O resources used by the I2C interface.\nRefer to \\ref CallSequence for more information.\n\n\\sa ARM_I2C_Initialize\n\\sa ARM_I2C_PowerControl\n\n*******************************************************************************************************************/\n\nint32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)  {\n  return ARM_DRIVER_OK;\n};\n/**\n\\fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_I2C_PowerControl operates the power modes of the I2C interface.\n\nThe parameter \\em state can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. \n                          Can be called multiple times. If the peripheral is already in this mode, \n\t\t\t\t\t\t  then the function performs no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n\n\\sa ARM_I2C_Initialize\n\\sa ARM_I2C_Uninitialize\n\n*******************************************************************************************************************/\n\nint32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)  {\n  return ARM_DRIVER_OK;\n};\n/**\n\\fn int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)\n\\details\nThis function \\b ARM_I2C_MasterTransmit transmits data as Master to the selected Slave.\n\nThe operation consists of:\n - Master generates START condition\n - Master addresses the Slave as Master Transmitter\n - Master transmits data to the addressed Slave\n - Master generates STOP condition (if \\em xfer_pending is \"false\")\n\nThe parameter \\em addr is the address of the slave to transmit the data to. The value can be ORed with \\ref ARM_I2C_ADDRESS_10BIT to \nidentify a 10-bit address value. \\n\nThe parameter \\em data and \\em num specify the address of a data buffer and the number of bytes to transmit. \\n\nSet the parameter \\em xfer_pending to 'true' if another transfer operation follows. With \\em xfer_pending set to 'false' a STOP condition is generated.\n\nThe function is non-blocking and returns as soon as the driver has started the operation.\nDuring the operation it is not allowed to call any Master function again. Also the data buffer must stay allocated and the contents of data must not be modified. \nWhen transmit operation has finished the \\ref ARM_I2C_EVENT_TRANSFER_DONE event is generated.\nWhen not all the data is transferred then the \\ref ARM_I2C_EVENT_TRANSFER_INCOMPLETE flag is set at the same time.\n\nNumber of data bytes transmitted and acknowledged is returned by the function \\ref ARM_I2C_GetDataCount during and after the operation has finished.\n\nThe operation is aborted in the following cases (\\ref ARM_I2C_EVENT_TRANSFER_DONE event is generated together with):\n - selected slave has not acknowledged the address: \\ref ARM_I2C_EVENT_ADDRESS_NACK event\n - arbitration has been lost: \\ref ARM_I2C_EVENT_ARBITRATION_LOST event\n - bus error has been detected: \\ref ARM_I2C_EVENT_BUS_ERROR event\n\nStatus can be monitored by calling the \\ref ARM_I2C_GetStatus and checking the flags.\n\nTransmit operation can be aborted also by calling \\ref ARM_I2C_Control with the parameter \\em control \\ref ARM_I2C_ABORT_TRANSFER.\n*******************************************************************************************************************/\n\nint32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)  {\n  return ARM_DRIVER_OK;\n};\n/**\n\\fn int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)\n\\details\nThis function \\b ARM_I2C_MasterReceive is used to receive data as Master from the selected Slave.\n\nThe operation consists of:\n - Master generates START condition\n - Master addresses the Slave as Master Receiver\n - Master receives data from the addressed Slave\n - Master generates STOP condition (if \\em xfer_pending is \"false\")\n\nThe parameter \\em addr is the address of the slave to receive the data from. The value can be ORed with \\ref ARM_I2C_ADDRESS_10BIT to \nidentify a 10-bit address value. \\n\nThe parameter \\em data and \\em num specify the address of a data buffer and the number of bytes to receive. \\n\nSet the parameter \\em xfer_pending to 'true' if another transfer operation follows. With \\em xfer_pending set to 'false' a STOP condition is generated.\n\nThe function is non-blocking and returns as soon as the driver has started the operation.\nDuring the operation it is not allowed to call any Master function again. Also the data buffer must stay allocated. \nWhen receive operation has finished the \\ref ARM_I2C_EVENT_TRANSFER_DONE event is generated.\nWhen not all the data is transferred then the \\ref ARM_I2C_EVENT_TRANSFER_INCOMPLETE flag is set at the same time.\n\nNumber of data bytes received is returned by the function \\ref ARM_I2C_GetDataCount during and after the operation has finished.\n\nThe operation is aborted in the following cases (\\ref ARM_I2C_EVENT_TRANSFER_DONE event is generated together with):\n - selected slave has not acknowledged the address: \\ref ARM_I2C_EVENT_ADDRESS_NACK event\n - arbitration has been lost: \\ref ARM_I2C_EVENT_ARBITRATION_LOST event\n - bus error has been detected: \\ref ARM_I2C_EVENT_BUS_ERROR event\n\nStatus can be monitored by calling the \\ref ARM_I2C_GetStatus and checking the flags.\n\nReceive operation can be aborted also by calling \\ref ARM_I2C_Control with the parameter \\em control = \\ref ARM_I2C_ABORT_TRANSFER.\n*******************************************************************************************************************/\n\nint32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)  {\n  return ARM_DRIVER_OK;\n};\n/**\n\\fn int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)\n\\details\nThis function \\b ARM_I2C_SlaveTransmit is used to transmit data as Slave to the Master.\n\nThe parameter \\em data is a pointer to the data to transmit. \\n\nThe parameter \\em num specifies the number of bytes to transmit.\n\nThe function is non-blocking and returns as soon as the driver has registered the operation.\nThe actual operation will start after being addressed by the master as a Slave Transmitter. If the operation has not been registered at that point the \\ref ARM_I2C_EVENT_SLAVE_TRANSMIT event is generated.\nThe same event is also generated if the operation has finished (specified number of bytes transmitted) but more data is requested by the master.\n\nIt is not allowed to call this function again if the operation has started until it finishes. Also the data buffer must stay allocated and the contents of data must not be modified. \nWhen transmit operation has finished the \\ref ARM_I2C_EVENT_TRANSFER_DONE event is generated.\nWhen not all the data is transferred then the \\ref ARM_I2C_EVENT_TRANSFER_INCOMPLETE flag is set at the same time.\n\nNumber of data bytes transmitted is returned by the function \\ref ARM_I2C_GetDataCount during and after the operation has finished.\n\nIn case that a General call has been detected the \\ref ARM_I2C_EVENT_GENERAL_CALL flag is indicated together with the \\ref ARM_I2C_EVENT_TRANSFER_DONE event (also with \\ref ARM_I2C_EVENT_SLAVE_TRANSMIT event).\n\nIn case that bus error has been detected then the operation is aborted and the \\ref ARM_I2C_EVENT_BUS_ERROR event is generated together with \\ref ARM_I2C_EVENT_TRANSFER_DONE.\n\nSlave will only respond to its own address (or General call if enabled) that is specified by calling \\ref ARM_I2C_Control with \\ref ARM_I2C_OWN_ADDRESS as control parameter. \nUsing address \\token{0} disables the slave.\n\nStatus can be monitored by calling the \\ref ARM_I2C_GetStatus and checking the flags.\n\nTransmit operation can be canceled or aborted by calling \\ref ARM_I2C_Control with the parameter \\em control = \\ref ARM_I2C_ABORT_TRANSFER.\n*******************************************************************************************************************/\n\nint32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)  {\n  return ARM_DRIVER_OK;\n};\n/**\n\\fn int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)\n\\details\nThis function \\b ARM_I2C_SlaveReceive receives data as Slave from the Master.\n\nThe parameter \\em data is a pointer to the data to receive. \\n\nThe parameter \\em num specifies the number of bytes to receive.\n\nThe function is non-blocking and returns as soon as the driver has registered the operation.\nThe actual operation will start after being addressed by the master as a Slave Receiver. If the operation has not been registered at that point the \\ref ARM_I2C_EVENT_SLAVE_RECEIVE event is generated.\n\nIt is not allowed to call this function again if the operation has started until it finishes. Also the data buffer must stay allocated. \nWhen receive operation has finished the \\ref ARM_I2C_EVENT_TRANSFER_DONE event is generated.\nWhen not all the data is transferred then the \\ref ARM_I2C_EVENT_TRANSFER_INCOMPLETE flag is set at the same time.\n\nNumber of data bytes received and acknowledged is returned by the function \\ref ARM_I2C_GetDataCount during and after the operation has finished.\n\nIn case that a General call has been detected the \\ref ARM_I2C_EVENT_GENERAL_CALL flag is indicated together with the \\ref ARM_I2C_EVENT_TRANSFER_DONE event (also with \\ref ARM_I2C_EVENT_SLAVE_RECEIVE event).\n\nIn case that bus error has been detected then the operation is aborted and the \\ref ARM_I2C_EVENT_BUS_ERROR event is generated together with \\ref ARM_I2C_EVENT_TRANSFER_DONE.\n\nSlave will only respond to its own address (or General call if enabled) that is specified by calling \\ref ARM_I2C_Control with \\ref ARM_I2C_OWN_ADDRESS as control parameter. \nUsing address \\token{0} disables the slave.\n\nStatus can be monitored by calling the \\ref ARM_I2C_GetStatus and checking the flags.\n\nReceive operation can be canceled or aborted by calling \\ref ARM_I2C_Control with the parameter \\em control = \\ref ARM_I2C_ABORT_TRANSFER.\n*******************************************************************************************************************/\n\nint32_t ARM_I2C_GetDataCount (void)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_I2C_GetDataCount (void)\n\\details\nThe function \\b ARM_I2C_GetDataCount returns the number of currently transferred data bytes during and after:\n - \\ref ARM_I2C_MasterTransmit : number of data bytes transmitted and acknowledged\n - \\ref ARM_I2C_MasterReceive : number of data bytes received\n - \\ref ARM_I2C_SlaveTransmit : number of data bytes transmitted\n - \\ref ARM_I2C_SlaveReceive : number of data bytes received and acknowledged\n\nWhen the Slave is not yet addressed by the Master then \\token{-1} is returned.\n*****************************************************************************************************************/\n\nint32_t ARM_I2C_Control (uint32_t control, uint32_t arg)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_I2C_Control (uint32_t control, uint32_t arg)\n\\details\nThe function \\b ARM_I2C_Control operates the I2C interface and executes various operations. \n\nThe parameter \\em control specifies various operations as listed in the table below.  \\n\nThe parameter \\em arg provides, depending on the operation,  additional information. \\n\n\nParameter \\em control            | Operation\n:--------------------------------|:--------------------------------------------\n\\ref ARM_I2C_OWN_ADDRESS         | Set Own Slave Address; \\em arg = slave address\n\\ref ARM_I2C_BUS_SPEED           | Set Bus Speed; \\em arg = bus speed\n\\ref ARM_I2C_BUS_CLEAR           | Clear the bus by sending nine clock pulses\n\\ref ARM_I2C_ABORT_TRANSFER      | Aborts the data transfer between Master and Slave for Transmit or Receive \n\n<b>Set Own Slave Address</b>\n\nAfter initialization, the I2C Device has no slave address assigned and does not accept any requests from \nan I2C Master.\n\nThe \\em control operation \\ref ARM_I2C_OWN_ADDRESS sets the slave address with the parameter \\em arg.\nThe slave address can be ORed with \\ref ARM_I2C_ADDRESS_10BIT to indicate a 10-bit address.  \n\nThe slave address can be ORed with \\ref ARM_I2C_ADDRESS_GC to indicate that the slave accepts a General Call.\nIf the slave address value is only \\ref ARM_I2C_ADDRESS_GC, then the slave only accepts a General Call.\n\nThe slave address value \\token{0} disables Slave mode and clears any assigned slave address.\n\n**Examples:**\n\nSet the Slave address value \\token{0x45} as 7-bit address.\n\\code\n  I2Cdrv->Control      (ARM_I2C_OWN_ADDRESS, 0x45);\n\\endcode\n\nSet the Slave address value \\token{0x135} as 10-bit address and accept a General Call.\n\\code\n  I2Cdrv->Control      (ARM_I2C_OWN_ADDRESS, 0x135 | ARM_I2C_ADDRESS_10BIT | ARM_I2C_ADDRESS_GC);\n\\endcode\n\n<b>Bus Speed</b>\n\nThe \\em control operation \\ref ARM_I2C_BUS_SPEED sets the bus speed using the parameter \\em arg.\n\nParameter \\em arg                | Bus Speed\n:--------------------------------|:--------------------------------------------\n\\ref ARM_I2C_BUS_SPEED_STANDARD  | Standard Speed to (\\token{100 kHz})\n\\ref ARM_I2C_BUS_SPEED_FAST      | Fast Speed  (\\token{400kHz})\n\\ref ARM_I2C_BUS_SPEED_FAST_PLUS | Fast + Speed (\\token{1MHz})\n\\ref ARM_I2C_BUS_SPEED_HIGH      | High Speed  (\\token{3.4MHz})\n\n**Example:**\n\n\\code\n  I2Cdrv->Control      (ARM_I2C_BUS_SPEED, I2C_BUS_SPEED_FAST);\n\\endcode\n*****************************************************************************************************************/\n\nARM_I2C_STATUS ARM_I2C_GetStatus (void)  {\n  return { 0 };\n}\n/**\n\\fn ARM_I2C_STATUS ARM_I2C_GetStatus (void)\n\\details\nThe function \\b ARM_I2C_GetStatus returns the current I2C interface status.\n\nRefer to \\ref ARM_I2C_STATUS for details.\n*****************************************************************************************************************/\n\nvoid ARM_I2C_SignalEvent (uint32_t event)  {\n  // function body\n}\n/**\n\\fn void ARM_I2C_SignalEvent (uint32_t event)\n\\details\nThe function \\b ARM_I2C_SignalEvent is a callback function registered by the function \\ref ARM_I2C_Initialize..\nIt is called by the I2C driver to notify the application about \\ref I2C_events occured during operation.\n\nThe parameter \\a event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nThe following events can be generated:\n\nParameter \\em event                       |     Bit   | Description \n:---------------------------------------- |:---------:|:----------------------------------------------------------\n\\ref ARM_I2C_EVENT_TRANSFER_DONE          | 1UL&nbsp;<<&nbsp;0  | Occurs after Master/Slave Transmit/Receive operation has finished.\n\\ref ARM_I2C_EVENT_TRANSFER_INCOMPLETE    | 1UL << 1  | Occurs together with \\ref ARM_I2C_EVENT_TRANSFER_DONE when less data is transferred then requested.\n\\ref ARM_I2C_EVENT_SLAVE_TRANSMIT         | 1UL << 2  | Occurs when addressed as Slave Transmitter and \\ref ARM_I2C_SlaveTransmit has not been started.\n\\ref ARM_I2C_EVENT_SLAVE_RECEIVE          | 1UL << 3  | Occurs when addressed as Slave Receiver and \\ref ARM_I2C_SlaveReceive has not been started.\n\\ref ARM_I2C_EVENT_ADDRESS_NACK           | 1UL << 4  | Occurs in master mode when address is not acknowledged from slave.\n\\ref ARM_I2C_EVENT_GENERAL_CALL           | 1UL << 5  | Indicates General Call in slave mode together with \\ref ARM_I2C_EVENT_TRANSFER_DONE, \\ref ARM_I2C_EVENT_SLAVE_TRANSMIT and \\ref ARM_I2C_EVENT_SLAVE_RECEIVE.\n\\ref ARM_I2C_EVENT_ARBITRATION_LOST       | 1UL << 6  | Occurs in master mode when arbitration is lost.\n\\ref ARM_I2C_EVENT_BUS_ERROR              | 1UL << 7  | Occurs when bus error is detected.\n\\ref ARM_I2C_EVENT_BUS_CLEAR              | 1UL << 8  | Occurs after \\ref ARM_I2C_BUS_CLEAR Control operation has finished.\n\n**************************************************************************************************************************/\n\n\n/**\n\\defgroup i2c_control_gr I2C Control Codes\n\\ingroup i2c_interface_gr\n\\brief Many parameters of the I2C driver are configured using the \\ref ARM_I2C_Control function.\n@{\n\\details \nThe various I2C control codes define:\n  - \\ref i2c_control_codes           specify operation parameters and various controls\n  - \\ref i2c_bus_speed_ctrls         specify the I2C bus speed\n  \nRefer to the \\ref ARM_I2C_Control function for further details.\n*/\n\n/**\n\\defgroup i2c_control_codes I2C Control Codes\n\\ingroup i2c_control_gr\n\\brief Specify operation parameters and various controls.\n\\details\n@{\n\\def ARM_I2C_OWN_ADDRESS\n\\sa ARM_I2C_Control\n\\def ARM_I2C_BUS_SPEED\nSpeed is specified using the following values: \\ref i2c_bus_speed_ctrls\n\\sa ARM_I2C_Control\n\\def ARM_I2C_BUS_CLEAR\n\\sa ARM_I2C_Control\n\\def ARM_I2C_ABORT_TRANSFER\n\\sa ARM_I2C_Control\n@}\n*/\n\n/**\n\\defgroup i2c_bus_speed_ctrls I2C Bus Speed\n\\ingroup i2c_control_gr\n\\brief Specify the I2C bus speed.\n\\details\n@{\n\\def ARM_I2C_BUS_SPEED_STANDARD\n\\sa ARM_I2C_Control\n\\def ARM_I2C_BUS_SPEED_FAST\n\\sa ARM_I2C_Control\n\\def ARM_I2C_BUS_SPEED_FAST_PLUS\n\\sa ARM_I2C_Control\n\\def ARM_I2C_BUS_SPEED_HIGH\n\\sa ARM_I2C_Control\n@}\n*/\n/**\n@}\n*/ \n\n/**\n\\defgroup i2c_address_flags I2C Address Flags\n\\ingroup i2c_interface_gr\n\\brief Specify address flags\n\\details\nSpecifies the address type for the functions \\ref ARM_I2C_MasterReceive, \\ref ARM_I2C_MasterTransmit and \\ref ARM_I2C_OWN_ADDRESS.\n@{\n\\def ARM_I2C_ADDRESS_10BIT\n\\sa ARM_I2C_OWN_ADDRESS\n\\sa ARM_I2C_MasterTransmit\n\\sa ARM_I2C_MasterReceive\n\\def ARM_I2C_ADDRESS_GC     \n\\sa ARM_I2C_OWN_ADDRESS\n@}\n*/\n\n\n/**\n@}\n*/ \n// End I2C Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_MCI.c",
    "content": "/**\n\\defgroup mci_interface_gr MCI Interface\n\\brief    Driver API for Memory Card Interface using SD/MMC interface (%Driver_MCI.h)\n\n\\details\nThe <b>Memory Card Interface</b> (MCI) implements the hardware abstraction layer for Secure Digital (SD) and Multi Media Card (MMC)\nmemory that is typically used as file storage. For embedded systems, SD/MMC devices are available as memory cards in several \nforms (SD, miniSD, microSD, MMC, MMCmicro) or as non-removable device\nes that are directly soldered to the PCB (eMMC).  \n\n\\b References:\n- Wikipedia offers more information about the <a href=\"http://en.wikipedia.org/wiki/SD_card\" target=\"_blank\"><b>Secure Digital</b> memory</a>.\n- Wikipedia offers more information about the <a href=\"http://en.wikipedia.org/wiki/MultiMediaCard\" target=\"_blank\"><b>MultiMediaCard</b></a>.\n- The SD Association provides detailed documentation under <a href=\"http://www.sdcard.org\">www.sdcard.org</a>.\n- The MultiMediaCard Association (merged with JEDEC) provides detailed documentation under <a href=\"http://www.jedec.org\">www.jedec.org</a>.\n\n<b>Block Diagram</b>\n\nThe MCI driver allows you to exchange data of the SD/MMC memory via SD/MMC interface.\n\nThe following modes are supported by SD/MMC memory cards:\n\n- SPI bus mode: Serial Peripheral Interface Bus supported by most microcontrollers.\n- 1-bit SD/MMC Bus mode: proprietary data transfer protocol supported by SD/MMC interfaces.\n- 4-bit SD/MMC Bus mode: high-speed version of the SD/MMC interface using 4 data I/O pins. \n- 8-bit SD/MMC Bus mode: high-speed version of the SD/MMC interface using 8 data I/O pins. \n\n\\image html SPI_BusMode.png  \"SD memory connected via SPI interface\"\n<p>&nbsp;</p>\n\\image html SD_1BitBusMode.png  \"SD memory connected via 1-bit SD Bus Mode\"\n<p>&nbsp;</p>\n\\image html SD_4BitBusMode.png  \"SD memory connected via 4-bit SD Bus Mode\"\n\n\n<b>MCI API</b>\n\nThe following header files define the Application Programming Interface (API) for the MCI interface:\n  - \\b %Driver_MCI.h : Driver API for Memory Card Interface using SD/MMC interface\n\nThe driver implementation is a typical part of the Device Family Pack (DFP) that supports the \nperipherals of the microcontroller family.\n\n\\note\nFor parameters, the value marked with (default) is the setting after the driver initialization.\n\n \n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_MCI : access struct for MCI driver functions\n\n\n<b>Example Code</b>\n\nThe following example code shows the usage of the MCI interface.\n\n\\include MCI_Demo.c\n\n@{\n*/\n\n\n/*************   Structures ******************************************************************************************************/\n/** \n\\struct     ARM_DRIVER_MCI \n\\details \nThe functions of the MCI are accessed by function pointers exposed by this structure. Refer to \\ref DriverFunctions for overview information.\n\nEach instance of an MCI provides such an access structure. \nThe instance is identified by a postfix number in the symbol name of the access structure, for example:\n - \\b Driver_MCI0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_MCI1 is the name of the access struct of the second instance (no. 1).\n\nA configuration setting in the middleware allows connecting the middleware to a specific driver instance <b>Driver_MCI<i>n</i></b>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*******************************************************************************************************************/\n\n/** \n\\struct     ARM_MCI_CAPABILITIES \n\\details \nA MCI driver can be implemented with different capabilities.  \nThe data fields of this struct encode the capabilities implemented by this driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_MCI_GetCapabilities\n*******************************************************************************************************************/\n\n/**\n\\defgroup mci_event_gr MCI Events\n\\brief The MCI driver generates call back events that are notified via the function \\ref ARM_MCI_SignalEvent.\n\\details\nThis section provides the event values for the \\ref ARM_MCI_SignalEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def ARM_MCI_EVENT_CARD_INSERTED   \n\\sa \\ref ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_CARD_REMOVED    \n\\sa \\ref  ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_COMMAND_COMPLETE \n\\sa \\ref ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_COMMAND_TIMEOUT  \n\\sa \\ref ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_COMMAND_ERROR    \n\\sa \\ref ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_TRANSFER_COMPLETE\n\\sa \\ref ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_TRANSFER_TIMEOUT \n\\sa \\ref ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_TRANSFER_ERROR   \n\\sa \\ref ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_SDIO_INTERRUPT   \n\\sa \\ref ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_CCS              \n\\sa \\ref ARM_MCI_SignalEvent\n\\def ARM_MCI_EVENT_CCS_TIMEOUT      \n\\sa \\ref ARM_MCI_SignalEvent\n@}\n*******************************************************************************************************************/\n\n//open mci_contorl_gr\n/**  \n@{\n*/\n/**\n\\defgroup mci_control_gr MCI Control Codes\n\\ingroup mci_interface_gr\n\\brief Configure and control the MCI using the \\ref ARM_MCI_Control.\n\\details\n@{\nMany parameters of the MCI driver are configured using the \\ref ARM_MCI_Control function.\n\nThe various MCI control codes define:\n  - \\ref mci_mode_ctrls configures and controls the MCI interface\n  - \\ref mci_bus_speed_ctrls specifies the bus speed mode\n  - \\ref mci_bus_data_width_ctrls specifies the data bus width\n  - \\ref mci_cmd_line_ctrls specifies the CMD line mode\n  - \\ref mci_driver_strength_ctrls specifies the driver strength\n\nRefer to the function \\ref ARM_MCI_Control for further details.\n@}\n*******************************************************************************************************************/\n\n\n/**\n\\defgroup mci_mode_ctrls MCI Controls\n\\ingroup mci_control_gr\n\\brief Configure and control the MCI interface.\n\\details\nThe following codes are used as values for the parameter \\em control of the function \\ref ARM_MCI_Control to setup the MCI interface.\n@{\n\\def ARM_MCI_BUS_SPEED       \n\\def ARM_MCI_BUS_SPEED_MODE       \n\\def ARM_MCI_BUS_CMD_MODE         \n\\def ARM_MCI_BUS_DATA_WIDTH       \n\\def ARM_MCI_DRIVER_STRENGTH       \n\\def ARM_MCI_CONTROL_RESET         \n\\def ARM_MCI_CONTROL_CLOCK_IDLE    \n\\def ARM_MCI_UHS_TUNING_OPERATION \n\\def ARM_MCI_UHS_TUNING_RESULT\n\\def ARM_MCI_DATA_TIMEOUT          \n\\def ARM_MCI_CSS_TIMEOUT            \n\\def ARM_MCI_MONITOR_SDIO_INTERRUPT \n\\def ARM_MCI_CONTROL_READ_WAIT      \n\\def ARM_MCI_SUSPEND_TRANSFER       \n\\def ARM_MCI_RESUME_TRANSFER        \n@}\n*******************************************************************************************************************/\n\n\n/**\n\\defgroup mci_bus_speed_ctrls MCI Bus Speed Mode\n\\ingroup mci_control_gr\n\\brief Specify the bus speed mode.\n\\details\n@{\nThe function \\ref ARM_MCI_Control with \\em control = \\ref ARM_MCI_BUS_SPEED configures the bus speed of the MCI to the\nrequested bits/s specified with \\em arg.\n\nThe function \\ref ARM_MCI_Control with \\em control = \\ref ARM_MCI_BUS_SPEED_MODE configures the bus speed mode of the MCI\nas specified with \\em arg listed bellow.\n\nThe function \\ref ARM_MCI_GetCapabilities lists the supported bus speed modes. Initially, all SD cards use a 3.3 volt electrical interface. \nSome SD cards can switch to 1.8 volt operation. For example, the use of ultra-high-speed (UHS) \nSD cards requires 1.8 volt operation and a 4-bit bus data width. The data field \\em uhs_signaling of the structure ARM_MCI_CAPABILITIES encodes \nwhether the driver supports 1.8 volt UHS signaling.\n\n\\sa \n - \\ref mci_driver_strength_ctrls\n\nThe following codes are defined:\n\n\\def ARM_MCI_BUS_DEFAULT_SPEED     \n\\def ARM_MCI_BUS_HIGH_SPEED        \n\\def ARM_MCI_BUS_UHS_SDR12         \n\\def ARM_MCI_BUS_UHS_SDR25         \n\\def ARM_MCI_BUS_UHS_SDR50         \n\\def ARM_MCI_BUS_UHS_SDR104        \n\\def ARM_MCI_BUS_UHS_DDR50         \n@}\n*******************************************************************************************************************/\n\n\n/**\n\\defgroup mci_bus_data_width_ctrls MCI Bus Data Width\n\\ingroup mci_control_gr\n\\brief Specify the data bus width.\n\\details\n@{\nThe function \\ref ARM_MCI_Control with \\em control = \\ref ARM_MCI_BUS_DATA_WIDTH specifies with \\em arg the number of data I/O pins on the SD/MMC interface.\n\nFor high-speed memory cards, a 4-bit bus data width should be used (or 8-bit for eMMC). The data fields \\em data_width_4 and \\em data_width_8 \nof the structure ARM_MCI_CAPABILITIES encode whether the driver supports a specific bus data with.\n\nThe following codes are defined:\n\n\\def ARM_MCI_BUS_DATA_WIDTH_1        \n\\def ARM_MCI_BUS_DATA_WIDTH_4        \n\\def ARM_MCI_BUS_DATA_WIDTH_8        \n\\def ARM_MCI_BUS_DATA_WIDTH_4_DDR    \n\\def ARM_MCI_BUS_DATA_WIDTH_8_DDR    \n@}\n*******************************************************************************************************************/\n\n\n/**\n\\defgroup mci_cmd_line_ctrls MCI CMD Line Mode\n\\ingroup mci_control_gr\n\\brief Specify the CMD line mode (Push-Pull or Open Drain).\n\\details\n@{\nSet the CMD line type with the function \\ref ARM_MCI_Control. \nThe CMD line mode is push-pull (default) or open drain (needed for older MMC).\n\n\\def ARM_MCI_BUS_CMD_PUSH_PULL       \n\\def ARM_MCI_BUS_CMD_OPEN_DRAIN      \n@}\n*******************************************************************************************************************/\n\n\n/**\n\\defgroup mci_driver_strength_ctrls MCI Driver Strength\n\\ingroup mci_control_gr\n\\brief Specify the driver strength.\n\\details\n@{\nThe function \\ref ARM_MCI_Control with \\em control = \\ref ARM_MCI_DRIVER_STRENGTH specifies with \\em arg the driver type of the SD interface.\n\n\\sa\n  - \\ref mci_bus_speed_ctrls\n\nThe following codes are defined:\n\n\\def ARM_MCI_DRIVER_TYPE_A      \n\\def ARM_MCI_DRIVER_TYPE_B      \n\\def ARM_MCI_DRIVER_TYPE_C      \n\\def ARM_MCI_DRIVER_TYPE_D      \n@}\n*******************************************************************************************************************/\n\n/**\n@}\n*/   // close group mci_control_gr\n\n/**\n\\defgroup mci_send_command_flags_ctrls MCI Send Command Flags\n\\ingroup mci_interface_gr\n\\brief Specify various options for sending commands to the card and the expected response.\n\\details\n\\b ARM_MCI_xxx flags are sent with the function \\ref ARM_MCI_SendCommand as the parameter \\em flag. \nIt controls the behavior of the command sent to the card and provides information about the expected response from the card.\n\nThe following codes are defined:\n@{\n\\def ARM_MCI_RESPONSE_NONE           \n\\def ARM_MCI_RESPONSE_SHORT          \n\\def ARM_MCI_RESPONSE_SHORT_BUSY     \n\\def ARM_MCI_RESPONSE_LONG           \n\\def ARM_MCI_RESPONSE_INDEX          \n\\def ARM_MCI_RESPONSE_CRC            \n\\def ARM_MCI_WAIT_BUSY             \n\\def ARM_MCI_TRANSFER_DATA         \n\\def ARM_MCI_CARD_INITIALIZE       \n\\def ARM_MCI_INTERRUPT_COMMAND     \n\\def ARM_MCI_INTERRUPT_RESPONSE    \n\\def ARM_MCI_BOOT_OPERATION        \n\\def ARM_MCI_BOOT_ALTERNATIVE      \n\\def ARM_MCI_BOOT_ACK              \n\\def ARM_MCI_CCSD                  \n\\def ARM_MCI_CCS                   \n@}\n*******************************************************************************************************************/\n\n/**\n\\defgroup mci_transfer_ctrls MCI Transfer Controls\n\\ingroup mci_interface_gr\n\\brief  Specify data transfer mode.\n\\details\nData transfer codes specifies the transfer direction and type and are used with the function \\ref ARM_MCI_SetupTransfer as the parameter \\em mode.\n\nThe following codes are defined:\n@{\n\\def ARM_MCI_TRANSFER_READ          \n\\def ARM_MCI_TRANSFER_WRITE         \n\\def ARM_MCI_TRANSFER_BLOCK         \n\\def ARM_MCI_TRANSFER_STREAM        \n@}\n*******************************************************************************************************************/\n\n/**\n\\defgroup mci_card_power_ctrls MCI Card Power Controls\n\\ingroup mci_interface_gr\n\\brief Specify Memory Card Power supply voltage\n\\details\nSpecifies the power supply volatge for a memory card. Used with the function \\ref ARM_MCI_CardPower as the parameter \\em voltage.\n\nThe following codes are defined:\n@{\n\\def ARM_MCI_POWER_VDD_OFF      \n\\def ARM_MCI_POWER_VDD_3V3      \n\\def ARM_MCI_POWER_VDD_1V8      \n\\def ARM_MCI_POWER_VCCQ_OFF     \n\\def ARM_MCI_POWER_VCCQ_3V3     \n\\def ARM_MCI_POWER_VCCQ_1V8     \n\\def ARM_MCI_POWER_VCCQ_1V2     \n@}\n*******************************************************************************************************************/\n\n\n/**\n\\struct   ARM_MCI_STATUS\n\\details \nStructure with information about the status of the MCI.\n\n<b>Returned by:</b>\n  - \\ref ARM_MCI_GetStatus\n*******************************************************************************************************************/\n\n/**\n\\typedef    ARM_MCI_SignalEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_MCI_SignalEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_MCI_Initialize\n*******************************************************************************************************************/\n\n\n//\n//   Functions \n//\nARM_DRIVER_VERSION ARM_MCI_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn       ARM_DRIVER_VERSION ARM_MCI_GetVersion (void)\n\\details\nThe function \\b ARM_MCI_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_MCI Driver_MCI0;\nARM_DRIVER_MCI *drv_info;\n \nvoid setup_mci (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_MCI0;\n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*******************************************************************************************************************/\n\nARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)  {\n  return { 0 };\n}\n/**\n\\fn       ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)\n\\details\nThe function \\b ARM_MCI_GetCapabilities returns information about capabilities in this driver implementation.\nThe data fields of the structure \\ref ARM_MCI_CAPABILITIES encode various capabilities, for example\nsupported bus modes ...\n \nExample:\n\\code\nextern ARM_DRIVER_MCI Driver_MCI0;\nARM_DRIVER_MCI *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_MCI_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_MCI0;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*******************************************************************************************************************/\n\nint32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)\n\\details\nThe function \\b ARM_MCI_Initialize initializes the MCI interface. \nIt is called when the middleware component starts operation.\n\nThe function performs the following operations:\n  - Initializes the resources needed for the MCI interface.\n  - Registers the \\ref ARM_MCI_SignalEvent callback function.\n\nThe parameter \\em cb_event is a pointer to the \\ref ARM_MCI_SignalEvent callback function; use a NULL pointer \nwhen no callback signals are required.\n\n\\b Example:\n - see \\ref mci_interface_gr - Driver Functions\n\n*******************************************************************************************************************/\n\nint32_t ARM_MCI_Uninitialize (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_MCI_Uninitialize (void)\n\\details\nThe function \\b ARM_MCI_Uninitialize de-initializes the resources of I2C interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n*******************************************************************************************************************/\n\nint32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)\n\\details     \nThe function \\b ARM_MCI_PowerControl operates the power modes of the MCI interface.  \n\nThe parameter \\em state can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. Can be called multiple times. \n                          If the peripheral is already in this mode, then the function performs no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n*******************************************************************************************************************/\n\nint32_t ARM_MCI_CardPower (uint32_t voltage)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_MCI_CardPower (uint32_t voltage)\n\\details\nThe function \\b ARM_MCI_CardPower operates the memory card power supply voltage. \n\nThe parameter \\em voltage sets the voltage. Not every voltage might be supported by the driver implementation.\nThe structure \\ref ARM_MCI_CAPABILITIES encodes the supported voltage. Retrieve the information with the function \\ref ARM_MCI_GetCapabilities and\nverify the data fields.\n\nThe following values:\n\nParameter \\em voltage                 | Description                   | supported when ARM_MCI_CAPABILITIES\n:-------------------------------------|:------------------------------|-----------------------------------------\n\\ref ARM_MCI_POWER_VDD_OFF            | VDD (VCC) turned off          | <i>always supported</i>\n\\ref ARM_MCI_POWER_VDD_3V3            | VDD (VCC) = \\token{3.3V}      | data field \\em vdd = \\token{1}\n\\ref ARM_MCI_POWER_VDD_1V8            | VDD (VCC) = \\token{1.8V}      | data field \\em vdd_1v8 = \\token{1} \n\\ref ARM_MCI_POWER_VCCQ_OFF           | eMMC VCCQ turned off          | <i>always supported</i>\n\\ref ARM_MCI_POWER_VCCQ_3V3           | eMMC VCCQ = \\token{3.3V}      | data field \\em vccq = \\token{1}\n\\ref ARM_MCI_POWER_VCCQ_1V8           | eMMC VCCQ = \\token{1.8V}      | data field \\em vccq_1v8 = \\token{1}\n\\ref ARM_MCI_POWER_VCCQ_1V2           | eMMC VCCQ = \\token{1.2V}      | data field \\em vccq_1v2 = \\token{1}\n\n*******************************************************************************************************************/\n\nint32_t ARM_MCI_ReadCD (void)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_MCI_ReadCD (void)\n\\details\nThe function \\b ARM_MCI_ReadCD reads the status of the Card Detect (CD) pin.\n*******************************************************************************************************************/\n\nint32_t ARM_MCI_ReadWP (void)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_MCI_ReadWP (void)\n\\details\nThe function \\b ARM_MCI_ReadWP reads the status of the Write Protect (WP) pin.\n*******************************************************************************************************************/\n\nint32_t ARM_MCI_SendCommand (uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_MCI_SendCommand (uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response)\n\\details\nThe function \\b ARM_MCI_SendCommand \n - sends commands to the memory card \n - retrieve the response from the card \n - optionally, start the data transfer.\n\nThe parameter \\em cmd is the command sent to the card. \\n\nThe parameter \\em arg contains arguments for the command \\em cmd. \\n\nThe parameter \\em flags controls the behavior of the operation and takes predefined values listed in the table below. \\n\nThe parameter \\em response is a pointer to receive data.\n\nThe parameter \\em flags can have the following values:\n\nParameter \\em flags                   | Description\n:-------------------------------------|:------------\n\\ref ARM_MCI_RESPONSE_NONE            | No response expected (default)\n\\ref ARM_MCI_RESPONSE_SHORT           | Short response (\\token{48}-bit) expected\n\\ref ARM_MCI_RESPONSE_SHORT_BUSY      | Short response with busy signal (\\token{48}-bit) expected\n\\ref ARM_MCI_RESPONSE_LONG            | Long response (\\token{136}-bit) expected\n\\ref ARM_MCI_RESPONSE_INDEX           | Check command index in response\n\\ref ARM_MCI_RESPONSE_CRC             | Check CRC in response\n\\ref ARM_MCI_WAIT_BUSY                | Wait until busy before sending the command\n\\ref ARM_MCI_TRANSFER_DATA            | Activate Data transfer\n\\ref ARM_MCI_CARD_INITIALIZE          | Execute Memory Card initialization sequence\n\\ref ARM_MCI_INTERRUPT_COMMAND        | Send Interrupt command (CMD40 - MMC only)\n\\ref ARM_MCI_INTERRUPT_RESPONSE       | Send Interrupt response (CMD40 - MMC only)\n\\ref ARM_MCI_BOOT_OPERATION           | Execute Boot operation (MMC only)\n\\ref ARM_MCI_BOOT_ALTERNATIVE         | Execute Alternative Boot operation (MMC only)\n\\ref ARM_MCI_BOOT_ACK                 | Expect Boot Acknowledge (MMC only)\n\\ref ARM_MCI_CCSD                     | Send Command Completion Signal Disable (CCSD) for CE-ATA device\n\\ref ARM_MCI_CCS                      | Expect Command Completion Signal (CCS) for CE-ATA device\n\nCalling the function <b>ARM_MCI_SendCommand</b> only starts the operation.\nThe function is non-blocking and returns as soon as the driver has started the operation.\nIt is not allowed to call this function again until the operation is in progress.\n\nAfter the command is sent the response is retrieved if specified with <b>ARM_MCI_RESPONSE_xxx</b> flags.\nWhen the command completes successfully (requested response is received without errors) the \\ref ARM_MCI_EVENT_COMMAND_COMPLETE event is generated.\nIn case that response is requested but not received the \\ref ARM_MCI_EVENT_COMMAND_TIMEOUT event is generated instead.\nIn case of invalid response (or CRC error) the \\ref ARM_MCI_EVENT_COMMAND_ERROR event is generated instead.\nProgress of command operation can be monitored by calling the \\ref ARM_MCI_GetStatus and checking the \\em command_active flag.\n\nAfter the command operation the data transfer operation is started if specified with <b>ARM_MCI_TRANSFER_DATA</b> flag.\nThe data transfer needs to be configured before that by calling the \\ref ARM_MCI_SetupTransfer.\nWhen the data transfer completes successfully the \\ref ARM_MCI_EVENT_TRANSFER_COMPLETE event is generated.\nIn case that data transfer is not completed in-time (specified by \\ref ARM_MCI_DATA_TIMEOUT) the \\ref ARM_MCI_EVENT_TRANSFER_TIMEOUT event is generated instead.\nIn case of CRC errors the \\ref ARM_MCI_EVENT_TRANSFER_ERROR event is generated instead.\nProgress of data transfer operation can be monitored by calling the \\ref ARM_MCI_GetStatus and checking the \\em transfer_active flag.\n\n<b>See also:</b>\n - \\ref ARM_MCI_SignalEvent\n*******************************************************************************************************************/\n\nint32_t ARM_MCI_SetupTransfer (uint8_t  *data, uint32_t block_count, uint32_t block_size, uint32_t mode)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_MCI_SetupTransfer (uint8_t  *data, uint32_t block_count, uint32_t block_size, uint32_t mode) \n\\details\nThe function \\b ARM_MCI_SetupTransfer prepares the data transfer operation that is initiated \nby calling the function \\ref ARM_MCI_SendCommand with the parameter \\em flags = \\ref ARM_MCI_TRANSFER_DATA.\n\nThe parameter \\em data is a pointer to the data to transfer. \\n\nThe parameter \\em block_count is the number of blocks to transfer. \\n\nThe parameter \\em block_size is the size of a block. \\n\nThe parameter \\em mode sets the transfer mode and can have the values liste in the table below:\n\nTransfer Directions                   | Description\n:-------------------------------------|:------------\n\\ref ARM_MCI_TRANSFER_READ            | Read data from MCI\n\\ref ARM_MCI_TRANSFER_WRITE           | Write data to MCI\n\\ref ARM_MCI_TRANSFER_BLOCK (default) | Block Data transfer \n\\ref ARM_MCI_TRANSFER_STREAM          | Stream Data transfer (MMC only)\n                                    \n*******************************************************************************************************************/\n\nint32_t ARM_MCI_AbortTransfer (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_MCI_AbortTransfer (void)\n\\details\nThe function \\b ARM_MCI_AbortTransfer aborts the active data transfer operation initiated with \\ref ARM_MCI_SendCommand.\n*******************************************************************************************************************/\n\n\nint32_t ARM_MCI_Control (uint32_t control, uint32_t arg)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn            int32_t ARM_MCI_Control (uint32_t control, uint32_t arg)\n\\details\nTh function \\b ARM_MCI_Control controls the MCI interface and executes various operations.\n\nThe parameter \\em control specifies the operation.  \nValues for \\em control cannot be ORed, but must be called separately in the code. \\n\nThe parameter \\em arg provides, depending on the operation, additional information or sets values.\n\n\\note\nFor parameters, the values marked with (default) are the setting after the driver initialization.\n\nThe table lists values for the parameter \\em control.\n\nParameter \\em control                 | Operation\n:-------------------------------------|:------------\n\\ref ARM_MCI_BUS_SPEED                | Set the Bus Speed. The parameter \\em arg specifies the speed in bits/s; The function returns the bus speed configured in bits/s.\n\\ref ARM_MCI_BUS_SPEED_MODE           | Set the Bus Speed Mode. Predefined values for \\em arg are listed in the table <b>Bus Speed Mode</b>.\n\\ref ARM_MCI_BUS_CMD_MODE             | Set the CMD Line Mode. Predefined values for \\em arg are listed in the table <b>Bus CMD Line Mode</b>.\n\\ref ARM_MCI_BUS_DATA_WIDTH           | Set data bus width. Predefined values for \\em arg are encoded in <b>Bus Data Width</b>.\n\\ref ARM_MCI_DRIVER_STRENGTH          | Set driver strength. Predefined values for \\em arg are listed in the table <b>Driver Type</b>\n\\ref ARM_MCI_CONTROL_RESET            | Control optional RST_n Pin (eMMC). The parameter \\em arg can have the values \\token{[0:inactive(default); 1:active]}\n\\ref ARM_MCI_CONTROL_CLOCK_IDLE       | Control clock generation on CLK Pin when idle. The parameter \\em arg  can have the values \\token{[0:disabled; 1:enabled]}\n\\ref ARM_MCI_UHS_TUNING_OPERATION     | Sampling clock Tuning operation (SD UHS-I). The parameter \\em arg  can have the values  \\token{[0:reset; 1:execute]}\n\\ref ARM_MCI_UHS_TUNING_RESULT        | Sampling clock Tuning result (SD UHS-I). Returns \\token{[0:done; 1:in progress; -1:error]}\n\\ref ARM_MCI_DATA_TIMEOUT             | Set Data timeout;  The parameter \\em arg sets the timeout in bus cycles.\n\\ref ARM_MCI_CSS_TIMEOUT              | Set Command Completion Signal (CCS) timeout. The parameter \\em arg sets timeout in bus cycles.\n\\ref ARM_MCI_MONITOR_SDIO_INTERRUPT   | Monitor SD I/O interrupt. The parameter \\em arg  can have the values \\token{[0:disabled(default); 1:enabled]}. Monitoring is automatically disabled when an interrupt is recognized.\n\\ref ARM_MCI_CONTROL_READ_WAIT        | Control Read/Wait states for SD I/O. The parameter \\em arg  can have the values \\token{[0:disabled(default); 1:enabled]}.\n\\ref ARM_MCI_SUSPEND_TRANSFER         | Suspend Data transfer (SD I/O). Returns the number of remaining bytes to transfer.\n\\ref ARM_MCI_RESUME_TRANSFER          | Resume Data transfer (SD I/O).\n \n \n<b>Bus Speed Mode</b>\n \nThe function \\ref ARM_MCI_GetCapabilities lists the supported bus speed modes. Initially, all SD cards use a 3.3 volt electrical interface. \nSome SD cards can switch to 1.8 volt operation. For example, the use of ultra-high-speed (UHS) \nSD cards requires 1.8 volt operation and a 4-bit bus data width. The bit field ARM_MCI_CAPABILITIES.uhs_signaling encodes \nwhether the driver supports 1.8 volt UHS signaling.\n\nThe \\em control operation \\b ARM_MCI_BUS_SPEED_MODE  sets the bus speed mode using the parameter \\em arg.\n\nParameter \\em arg                                             | Bus Speed Mode\n:-------------------------------------------------------------|:------------------------------------------\n\\ref  ARM_MCI_BUS_DEFAULT_SPEED (default)                     | Set the bus speed for SD/MMC cards: Default Speed mode up to \\token{[25;26]MHz} \n\\ref  ARM_MCI_BUS_HIGH_SPEED                                  | Set the bus speed for SD/MMC: High    Speed mode up to \\token{[50;52]MHz}\n\\ref  ARM_MCI_BUS_UHS_SDR12                                   | Set the bus speed for SD: SDR12  (Single Data Rate) up to  \\token{25MHz,  12.5MB/s: UHS-I (Ultra High Speed) 1.8V signalling}\n\\ref  ARM_MCI_BUS_UHS_SDR25                                   | Set the bus speed for SD: SDR25  (Single Data Rate) up to  \\token{50MHz,  25  MB/s: UHS-I (Ultra High Speed) 1.8V signalling}\n\\ref  ARM_MCI_BUS_UHS_SDR50                                   | Set the bus speed for SD: SDR50  (Single Data Rate) up to \\token{100MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signalling}\n\\ref  ARM_MCI_BUS_UHS_SDR104                                  | Set the bus speed for SD: SDR104 (Single Data Rate) up to \\token{208MHz, 104  MB/s: UHS-I (Ultra High Speed) 1.8V signalling}\n\\ref  ARM_MCI_BUS_UHS_DDR50                                   | Set the bus speed for SD: DDR50  (Dual Data Rate)   up to  \\token{50MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signalling}\n \n \n<b>Bus CMD Line Mode</b> \n \nThe \\em control operation \\b ARM_MCI_BUS_CMD_MODE sets the bus command line mode using the parameter \\em arg.\n\nParameter \\em arg                                             | Bus CMD Line Mode  \n:-------------------------------------------------------------|:------------------------------------------\n\\ref ARM_MCI_BUS_CMD_PUSH_PULL  (default)                     | Set the Push-Pull CMD line\n\\ref ARM_MCI_BUS_CMD_OPEN_DRAIN                               | Set the Open Drain CMD line (MMC only)\n \n \n<b>Bus Data Width</b> \n \nSpecifies the bus data width (the number of data I/O pins on the SD/MMC interface).\n \nFor high speed memory cards, a 4-bit bus data width should be used (or 8-bit for eMMC). The bit fields ARM_MCI_CAPABILITIES.data_width_4 and\nARM_MCI_CAPABILITIES.data_width_8 encode whether the driver supports a specific bus data with.\n\nThe \\em control operation \\b ARM_MCI_BUS_DATA_WIDTH  sets the bus data width using the parameter \\em arg.\n\nParameter \\em arg                                             | Bus Data Width\n:-------------------------------------------------------------|:------------------------------------------\n\\ref ARM_MCI_BUS_DATA_WIDTH_1 (default)                       | Set the Bus data width to \\token{1 bit} \n\\ref ARM_MCI_BUS_DATA_WIDTH_4                                 | Set the Bus data width to \\token{4 bits}\n\\ref ARM_MCI_BUS_DATA_WIDTH_8                                 | Set the Bus data width to \\token{8 bits}\n\\ref ARM_MCI_BUS_DATA_WIDTH_4_DDR                             | Set the Bus data width to \\token{4 bits}, DDR (Dual Data Rate) - MMC only\n\\ref ARM_MCI_BUS_DATA_WIDTH_8_DDR                             | Set the Bus data width to \\token{8 bits}, DDR (Dual Data Rate) - MMC only\n \n \n<b>Driver Type</b> \n \nSpecifies the interface driver type.\n\nThe \\em control operation \\b ARM_MCI_DRIVER_STRENGTH  sets the interface driver type using the parameter \\em arg.\n\nParameter \\em arg                                             | Driver Type \n:-------------------------------------------------------------|:------------------------------------------\n\\ref ARM_MCI_DRIVER_TYPE_A                                    | Set the interface to SD UHS-I Driver Type A\n\\ref ARM_MCI_DRIVER_TYPE_B  (default)                         | Set the interface to SD UHS-I Driver Type B \n\\ref ARM_MCI_DRIVER_TYPE_C                                    | Set the interface to SD UHS-I Driver Type C\n\\ref ARM_MCI_DRIVER_TYPE_D                                    | Set the interface to SD UHS-I Driver Type D\n\n\\b Examples:\n\\code\n// Set Bus Speed to 25MHz\nMCIdrv->Control(ARM_MCI_BUS_SPEED, 25000000);\n \n// Set High Speed mode\nMCIdrv->Control(ARM_MCI_BUS_SPEED_MODE, ARM_MCI_BUS_HIGH_SPEED);\n \n// Configure CMD line as Open Drain (MMC only)\nMCIdrv->Control(ARM_MCI_BUS_CMD_MODE, ARM_MCI_BUS_CMD_OPEN_DRAIN);\n \n// Set Bus Data Width = 4bits\nMCIdrv->Control(ARM_MCI_BUS_DATA_WIDTH, ARM_MCI_BUS_DATA_WIDTH_4);\n \n// Set SD UHS-I Driver Type B\nMCIdrv->Control(ARM_MCI_DRIVER_STRENGTH, ARM_MCI_DRIVER_TYPE_B);\n \n// RTS_n Pin is not active by default\n// Assert RTS_n Pin (eMMC)\nMCIdrv->Control(ARM_MCI_CONTROL_RESET, 1);\n// De-assert RTS_n Pin (eMMC)\nMCIdrv->Control(ARM_MCI_CONTROL_RESET, 0);\n \n// Clock generation on CLK when Idle: hardware specific default behavior\n// Enable Clock generation on CLK when Idle\nMCIdrv->Control(ARM_MCI_CONTROL_CLOCK_IDLE, 1);\n// Disable Clock generation on CLK when Idle\nMCIdrv->Control(ARM_MCI_CONTROL_CLOCK_IDLE, 0);\n \n// UHS Tuning\nMCIdrv->Control(ARM_MCI_UHS_TUNING_OPERATION, 1);  // start tuning\ndo {\n  status = MCIdrv->Control(ARM_MCI_UHS_TUNING_RESULT, 0/*argument not used*/);\n  if (status == -1) { break; /* tuning failed */ }\n} while (status == 1);\n \n// Set Data Timeout to 12500000 bus cycles (0.5s @25MHz Bus Speed)\n// Default value is hardware specific (typically 2^32-1)\nMCIdrv->Control(ARM_MCI_DATA_TIMEOUT, 12500000);\n  \n// Set CSS Timeout to 1000000 bus cycles\n// Default value is hardware specific\nMCIdrv->Control(ARM_MCI_CSS_TIMEOUT, 1000000);\n \n// SD I/O Interrupt Monitoring is disabled by default\n// Enable SD I/O Interrupt Monitoring\nMCIdrv->Control(ARM_MCI_MONITOR_SDIO_INTERRUPT, 1);\n// Disable SD I/O Interrupt Monitoring\nMCIdrv->Control(ARM_MCI_MONITOR_SDIO_INTERRUPT, 0);\n \n// Read/Wait for SD I/O is disabled by default\n// Enable Read/Wait for SD I/O\nMCIdrv->Control(ARM_MCI_CONTROL_READ_WAIT, 1);\n// Disable Read/Wait for SD I/O\nMCIdrv->Control(ARM_MCI_CONTROL_READ_WAIT, 0);\n \n// Suspend Data transfer (SD I/O)\nMCIdrv->Control(ARM_MCI_SUSPEND_TRANSFER, 0/*argument not used*/);\n \n// Resume Data transfer (SD I/O)\nMCIdrv->Control(ARM_MCI_RESUME_TRANSFER, 0/*argument not used*/);\n\\endcode\n*******************************************************************************************************************/\n\nARM_MCI_STATUS ARM_MCI_GetStatus (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn            ARM_MCI_STATUS ARM_MCI_GetStatus (void)\n\\details\nThe function \\b ARM_MCI_GetStatus returns the current MCI interface status.\n*******************************************************************************************************************/\n\nvoid ARM_MCI_SignalEvent (uint32_t event)  {\n // function body\n}\n/**\n\\fn void ARM_MCI_SignalEvent (uint32_t event)\n\\details\nThe function \\b ARM_MCI_SignalEvent is a callback function registered by the function \\ref ARM_MCI_Initialize. \n\nThe parameter \\em event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nNot every event is necessarily generated by the driver. This depends on the implemented capabilities stored in the \ndata fields of the structure \\ref ARM_NAND_CAPABILITIES, which can be retrieved with the function \\ref ARM_NAND_GetCapabilities.\n\nThe following events can be generated:\n\nParameter \\em event                        |Bit | Description                                                           | supported when \\ref ARM_NAND_CAPABILITIES\n:------------------------------------------|---:|:----------------------------------------------------------------------|:---------------------------------------------\n\\ref ARM_MCI_EVENT_CARD_INSERTED           | 0  | Occurs after Memory Card inserted                                     | <i>always supported</i>\n\\ref ARM_MCI_EVENT_CARD_REMOVED            | 1  | Occurs after Memory Card removal                                      | <i>always supported</i>\n\\ref ARM_MCI_EVENT_COMMAND_COMPLETE        | 2  | Occurs after command completed successfully                           | <i>always supported</i>\n\\ref ARM_MCI_EVENT_COMMAND_TIMEOUT         | 3  | Occurs after command timeout                                          | <i>always supported</i>\n\\ref ARM_MCI_EVENT_COMMAND_ERROR           | 4  | Occurs after command response error (CRC error or invalid response)   | <i>always supported</i>\n\\ref ARM_MCI_EVENT_TRANSFER_COMPLETE       | 5  | Occurs after data transfer completed successfully                     | <i>always supported</i>\n\\ref ARM_MCI_EVENT_TRANSFER_TIMEOUT        | 6  | Occurs after data transfer timeout                                    | <i>always supported</i>\n\\ref ARM_MCI_EVENT_TRANSFER_ERROR          | 7  | Occurs after data transfer error (CRC failed)                         | <i>always supported</i>\n\\ref ARM_MCI_EVENT_SDIO_INTERRUPT          | 8  | Indicates SD I/O Interrupt                                            | data field \\em sdio_interrupt = \\token{1}\n\\ref ARM_MCI_EVENT_CCS                     | 9  | Indicates a Command Completion Signal (CCS)                           | data field \\em ccs = \\token{1}\n\\ref ARM_MCI_EVENT_CCS_TIMEOUT             |10  | Indicates a Command Completion Signal (CCS) Timeout                   | data field \\em css_timeout = \\token{1}\n\n<b>See also:</b>\n - \\ref ARM_MCI_SendCommand\n \n*******************************************************************************************************************/\n\n\n/**\n@}\n*/ \n// End MCI Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_NAND.c",
    "content": "/**\n\\defgroup nand_interface_gr NAND Interface\n\\brief    Driver API for NAND Flash Device Interface (%Driver_NAND.h).\n\n\\details\n<b>NAND</b> devices are a type of non-volatile storage and do not require power to hold data. \nWikipedia offers more information about \nthe <a href=\"http://en.wikipedia.org/wiki/Flash_memory#ARM_NAND_memories\" target=\"_blank\"><b>Flash Memories</b></a>, including NAND.\n\n<b>Block Diagram</b>\n\n<p>&nbsp;</p>\n\\image html NAND_Schematics.png \"Simplified NAND Flash Schematic\"\n<p>&nbsp;</p>\n\n\n<b>NAND API</b>\n\nThe following header files define the Application Programming Interface (API) for the NAND interface:\n  - \\b %Driver_NAND.h : Driver API for NAND Flash Device Interface\n\nThe driver implementation is a typical part of the Device Family Pack (DFP) that supports the \nperipherals of the microcontroller family.\n\nNAND Flash is organized in pages, grouped into blocks as the smallest erasable unit. The addressing\nof data is achieved by `byte_address = block * block_size + page_in_block * page_size + offset_in_page`.\nIn terms of this NAND API blocks and pages are referred to as `row` and the byte offset within the page as `col`.\nThus one can calculate the `byte_address = row * page_size + col`. The parameters `page_size` and `block_size` \nare device specific and must be handled by the driver user appropriately.\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_NAND : access struct for NAND driver functions\n\n@{\n\\anchor example <b>Example Code:</b>\n\n\\include NAND_Demo.c\n*/\n/*******************************************************************************************************************/\n\n\n/**\n\\defgroup nand_execution_status Status Error Codes\n\\ingroup common_drv_gr\n\\brief Negative values indicate errors (NAND has specific codes in addition to common \\ref execution_status). \n\\details \nThe NAND driver has additional status error codes that are listed below.\nNote that the NAND driver also returns the common \\ref execution_status. \n  \n@{\n\\def ARM_NAND_ERROR_ECC\nECC generation or correction failed during \\ref ARM_NAND_ReadData, \\ref ARM_NAND_WriteData or \\ref ARM_NAND_ExecuteSequence.\n@}\n*/\n\n\n/**\n\\defgroup NAND_events NAND Events\n\\ingroup nand_interface_gr\n\\brief The NAND driver generates call back events that are notified via the function \\ref ARM_NAND_SignalEvent.\n\\details \nThis section provides the event values for the \\ref ARM_NAND_SignalEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def ARM_NAND_EVENT_DEVICE_READY\n\\def ARM_NAND_EVENT_DRIVER_READY\n\\def ARM_NAND_EVENT_DRIVER_DONE \n\\def ARM_NAND_EVENT_ECC_ERROR   \n@}\n*/\n\n\n/**\n\\defgroup nand_driver_flag_codes NAND Flags\n\\ingroup nand_interface_gr\n\\brief Specify Flag codes.\n\\details\nThe defines can be used in the function \\ref ARM_NAND_ReadData and \\ref ARM_NAND_WriteData for the parameter \\em mode\nand in the function \\ref ARM_NAND_ExecuteSequence for the parameter \\em code.\n@{\n\\def ARM_NAND_DRIVER_DONE_EVENT   \n@}\n*/\n\n\n/**\n\\defgroup nand_control_gr NAND Control Codes\n\\ingroup nand_interface_gr\n\\brief Many parameters of the NAND driver are configured using the \\ref ARM_NAND_Control function.\n@{\n\\details \nRefer to the function \\ref ARM_NAND_Control for further details.\n*/\n\n/**\n\\defgroup nand_control_codes NAND Mode Controls\n\\ingroup nand_control_gr\n\\brief Specify operation modes of the NAND interface.\n\\details\nThese controls can be used in the function \\ref ARM_NAND_Control for the parameter \\em control.\n@{\n\\def ARM_NAND_BUS_MODE             \n\\def ARM_NAND_BUS_DATA_WIDTH       \n\\def ARM_NAND_DRIVER_STRENGTH      \n\\def ARM_NAND_DEVICE_READY_EVENT   \n\\def ARM_NAND_DRIVER_READY_EVENT   \n@}\n*/\n\n/**\n\\defgroup nand_bus_mode_codes NAND Bus Modes\n\\ingroup nand_control_gr\n\\brief Specify bus mode of the NAND interface.\n\\details\nThe defines can be used in the function \\ref ARM_NAND_Control for the parameter \\em arg and with the \\ref ARM_NAND_BUS_MODE as the \\em control code.\n@{\n\\def ARM_NAND_BUS_SDR               \n\\def ARM_NAND_BUS_DDR               \n\\def ARM_NAND_BUS_DDR2              \n\\def ARM_NAND_BUS_TIMING_MODE_0     \n\\def ARM_NAND_BUS_TIMING_MODE_1     \n\\def ARM_NAND_BUS_TIMING_MODE_2     \n\\def ARM_NAND_BUS_TIMING_MODE_3     \n\\def ARM_NAND_BUS_TIMING_MODE_4     \n\\def ARM_NAND_BUS_TIMING_MODE_5     \n\\def ARM_NAND_BUS_TIMING_MODE_6     \n\\def ARM_NAND_BUS_TIMING_MODE_7     \n\\def ARM_NAND_BUS_DDR2_DO_WCYC_0    \n\\def ARM_NAND_BUS_DDR2_DO_WCYC_1    \n\\def ARM_NAND_BUS_DDR2_DO_WCYC_2    \n\\def ARM_NAND_BUS_DDR2_DO_WCYC_4    \n\\def ARM_NAND_BUS_DDR2_DI_WCYC_0    \n\\def ARM_NAND_BUS_DDR2_DI_WCYC_1    \n\\def ARM_NAND_BUS_DDR2_DI_WCYC_2    \n\\def ARM_NAND_BUS_DDR2_DI_WCYC_4    \n\\def ARM_NAND_BUS_DDR2_VEN          \n\\def ARM_NAND_BUS_DDR2_CMPD         \n\\def ARM_NAND_BUS_DDR2_CMPR         \n@}\n*/\n\n/**\n\\defgroup nand_data_bus_width_codes NAND Data Bus Width\n\\ingroup nand_control_gr\n\\brief Specify data bus width of the NAND interface.\n\\details\nThe defines can be used in the function \\ref ARM_NAND_Control for the parameter \\em arg and with the \\ref ARM_NAND_BUS_DATA_WIDTH as the \\em control code.\n@{\n\\def ARM_NAND_BUS_DATA_WIDTH_8   \n\\def ARM_NAND_BUS_DATA_WIDTH_16  \n@}\n*/\n\n/**\n\\defgroup nand_driver_strength_codes NAND Driver Strength\n\\ingroup nand_control_gr\n\\brief Specify driver strength of the NAND interface.\n\\details\nThe defines can be used in the function \\ref ARM_NAND_Control for the parameter \\em arg and with the \\ref ARM_NAND_DRIVER_STRENGTH as the \\em control code.\n@{\n\\def ARM_NAND_DRIVER_STRENGTH_18 \n\\def ARM_NAND_DRIVER_STRENGTH_25 \n\\def ARM_NAND_DRIVER_STRENGTH_35 \n\\def ARM_NAND_DRIVER_STRENGTH_50 \n@}\n*/\n\n/**\n@}\n*/\n\n\n/**\n\\defgroup nand_driver_ecc_codes NAND ECC Codes\n\\ingroup nand_interface_gr\n\\brief Specify ECC codes.\n\\details\nThe defines can be used in the function \\ref ARM_NAND_ReadData and \\ref ARM_NAND_WriteData for the parameter \\em mode\nand in the function \\ref ARM_NAND_ExecuteSequence for the parameter \\em code.\n@{\n\\def ARM_NAND_ECC(n)\n\\def ARM_NAND_ECC0\n\\def ARM_NAND_ECC1\n@}\n*/\n\n\n/**\n\\defgroup nand_driver_seq_exec_codes NAND Sequence Execution Codes\n\\ingroup nand_interface_gr\n\\brief Specify execution codes\n\\details\nThe defines can be used in the function \\ref ARM_NAND_ExecuteSequence for the parameter \\em code.\n@{\n\\def ARM_NAND_CODE_SEND_CMD1       \n\\def ARM_NAND_CODE_SEND_ADDR_COL1  \n\\def ARM_NAND_CODE_SEND_ADDR_COL2  \n\\def ARM_NAND_CODE_SEND_ADDR_ROW1  \n\\def ARM_NAND_CODE_SEND_ADDR_ROW2  \n\\def ARM_NAND_CODE_SEND_ADDR_ROW3  \n\\def ARM_NAND_CODE_INC_ADDR_ROW    \n\\def ARM_NAND_CODE_WRITE_DATA      \n\\def ARM_NAND_CODE_SEND_CMD2       \n\\def ARM_NAND_CODE_WAIT_BUSY       \n\\def ARM_NAND_CODE_READ_DATA       \n\\def ARM_NAND_CODE_SEND_CMD3       \n\\def ARM_NAND_CODE_READ_STATUS     \n@}\n*/\n\n\n/*------------   Structures --------------------------------------------------------------------------------------*/\n/**\n\\struct     ARM_NAND_STATUS\n\\details\nStructure with information about the status of a NAND. The data fields encode flags for the driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_NAND_GetStatus\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_DRIVER_NAND \n\\details\nThe functions of the NAND driver are accessed by function pointers exposed by this structure. Refer to \\ref DriverFunctions for overview information.\n\nEach instance of a NAND interface provides such an access structure. \nThe instance is identified by a postfix number in the symbol name of the access structure, for example:\n - \\b Driver_NAND0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_NAND1 is the name of the access struct of the second instance (no. 1).\n\nA middleware configuration setting allows connecting the middleware to a specific driver instance <b>Driver_NAND<i>n</i></b>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_NAND_CAPABILITIES \n\\details\nA NAND driver can be implemented with different capabilities. The data fields of this struct encode \nthe capabilities implemented by this driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_NAND_GetCapabilities\n*******************************************************************************************************************/\n\n\n/**\n\\typedef    ARM_NAND_SignalEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_NAND_SignalEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_NAND_Initialize\n*******************************************************************************************************************/\n\n\n/**\n\\struct     ARM_NAND_ECC_INFO\n\n\\details\nStores the characteristics of a ECC (Error Correction Code) algorithm and provides the information about necessary\napplication data handling in order to protect stored data from NAND bit errors.\n\nECC algorithms applied on NAND memory typically operate on NAND device page level which is virtually divided to multiple\nmain and spare areas. Data from main and spare area is taken into account when generating ECC data which is also stored\ninto spare area. ECC codeword defines how much data will be protected and how much ECC data will be generated.\n\nTo describe how application data must be organized, ECC information structure specifies protection \\em type which\ndefines the protected part of data. As main and spare are of different size, two different algorithms could be\nprovided, we can describe them as ECC0 and ECC1. Type can then have the following values:\n\nType| Description \n:---|:-----------\n 0  | ECC algorithm not used\n 1  | ECC0 algorithm protects main data\n 2  | ECC0 algorithm protects main and spare data\n 3  | ECC0 algorithm protects main and ECC1 algorithm protects spare data\n\nVirtual page division is described with page layout (\\em page_layout), number of pages (\\em page_count) and\nvirtual page size (\\em page_size or \\em virtual_page_size). Virtual page size used by ECC algorithm can be defined\nby either \\em page_size or \\em virtual_page_size, depending on the \\em page_size values:\n\nValue| Main + Spare size\n:----|:-----------\n 0   | 512 + 16\n 1   | 1024 + 32\n 2   | 2048 + 64\n 3   | 4096 + 128\n 4   | 8192 + 256\n 8   | 512 + 28\n 9   | 1024 + 56\n 10  | 2048 + 112\n 11  | 4096 + 224\n 12  | 8192 + 448\n 15  | Not used, use virtual_page_size\n\nStructure member \\em virtual_page_size is an array of two 16-bit values. First field of array (i.e. \\em virtual_page_size[0])\ncontains main area size while second (i.e. \\em virtual_page_size[1]) contains spare area size. Number of virtual pages N\nis defined with \\em page_count and must be calculated as N = 2 ^ page_count.\n\nPage layout defines main and spare ordering and two different page layouts are possible. First ordering assumes that\nspare area follows after every main area, while in second case all main areas build one contiguous region followed by\ncontiguous region of spare areas. This is defined by member \\em page_layout:\n\nLayout| Description \n:-----|:-----------\n 0    | Single spare follows after single main: Main0,Spare0 ... MainN-1,SpareN-1\n 1    | Contiguous spare follows after contiguous main: Main0 ... MainN-1,Spare0 ... SpareN-1\n\nECC codeword size defines the size of data that is protected by ECC algorithm and is different for main and spare\narea. All structure members that define the codeword are therefore arrays of two 16-bit values. Codeword offset defines\nwhere ECC protected data starts in main (\\em codeword_offset[0]) or spare (\\em codeword_offset[1]) area, codeword\nsize (\\em codeword_size) defines the number of data that is protected i.e. data over which ECC is calculated and\ncodeword gap (\\em codeword_gap) defines the space between two consecutive codeword regions.\n\nGenerated ECC data is stored into spare area and is described similar as codeword, with offset from start of spare area\n(\\em ecc_offset), size of generated data (\\em ecc_size) and gap (\\em ecc_gap) between two consecutive ECC data regions.\n\nNumber of bits that ECC algorithm can correct per codeword is defined with \\em correctable_bits.\n\n<b>Parameter for:</b>\n  - \\ref ARM_NAND_InquireECC\n*****************************************************************************************************************/\n\n\n//\n//  Functions \n//\n\nARM_DRIVER_VERSION ARM_NAND_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn       ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)\n\\details\nThe function \\b ARM_NAND_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_NAND Driver_NAND0;\nARM_DRIVER_NAND *drv_info;\n \nvoid setup_nand (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_NAND0;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*******************************************************************************************************************/\n\nARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)  {\n  return { 0 };\n}\n/**\n\\fn       ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)\n\\details\nThe function \\b ARM_NAND_GetCapabilities retrieves information about capabilities in this driver implementation.\nThe data fields of the structure \\ref ARM_NAND_CAPABILITIES encode various capabilities, for example\nif a hardware is able to create signal events using the \\ref ARM_NAND_SignalEvent \ncallback function.\n \nExample:\n\\code\nextern ARM_DRIVER_NAND Driver_NAND0;\nARM_DRIVER_NAND *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_NAND_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_NAND0;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t  cb_event)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t  cb_event)\n\\details\nThe function \\b ARM_NAND_Initialize initializes the NAND interface. \nIt is called when the middleware component starts operation.\n\nThe function performs the following operations:\n  - Initializes the resources needed for the NAND interface.\n  - Registers the \\ref ARM_NAND_SignalEvent callback function.\n\nThe parameter \\em cb_event is a pointer to the \\ref ARM_NAND_SignalEvent callback function; use a NULL pointer \nwhen no callback signals are required.\n\n\\b Example:\n - see \\ref nand_interface_gr - Driver Functions\n\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_Uninitialize (void)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_Uninitialize (void)\n\\details\nThe function \\b ARM_NAND_Uninitialize de-initializes the resources of NAND interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_NAND_PowerControl controls the power modes of the NAND interface.  \n\nThe parameter \\em state sets the operation and can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. \n                          Can be called multiple times. If the peripheral is already in this mode the function performs \n\t\t\t\t\t\t  no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n*******************************************************************************************************************/\n\n\nint32_t ARM_NAND_DevicePower (uint32_t voltage)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_DevicePower (uint32_t voltage)\n\\details\nThe function \\b ARM_NAND_DevicePower controls the power supply of the NAND device.\n\nThe parameter \\em voltage sets the device supply voltage as defined in the table.\n\n\\b AMR_NAND_POWER_xxx_xxx specifies power settings.\n\nDevice Power Bits                | Description\n:--------------------------------|:--------------------------------------------\n\\ref ARM_NAND_POWER_VCC_OFF      | Set VCC Power off\n\\ref ARM_NAND_POWER_VCC_3V3      | Set VCC = 3.3V\n\\ref ARM_NAND_POWER_VCC_1V8      | Set VCC = 1.8V\n\\ref ARM_NAND_POWER_VCCQ_OFF     | Set VCCQ I/O Power off\n\\ref ARM_NAND_POWER_VCCQ_3V3     | Set VCCQ = 3.3V\n\\ref ARM_NAND_POWER_VCCQ_1V8     | Set VCCQ = 1.8V\n\\ref ARM_NAND_POWER_VPP_OFF      | Set VPP off\n\\ref ARM_NAND_POWER_VPP_ON       | Set VPP on\n\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)\n\\details\nThe function \\b ARM_NAND_WriteProtect controls the Write Protect (WPn) pin of a NAND device.\n\nThe parameter \\em dev_num is the device number. \\n \nThe parameter \\em enable specifies whether to enable or disable write protection.\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)\n\\details\nThe function \\b ARM_NAND_ChipEnable control the Chip Enable (CEn) pin of a NAND device.\n\nThe parameter \\em dev_num is the device number. \\n \nThe parameter \\em enable specifies whether to enable or disable the device.\n\nThis function is optional and supported only when the data field \\em ce_manual = \\token{1} in the structure \\ref ARM_NAND_CAPABILITIES.\nOtherwise, the Chip Enable (CEn) signal is controlled automatically by SendCommand/Address, Read/WriteData and ExecuteSequence \n(for example when the NAND device is connected to a memory bus).\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)\n\\details\nThe function \\b ARM_NAND_GetDeviceBusy returns the status of the Device Busy pin: [\\token{1=busy; 0=not busy or error}].\n\nThe parameter \\em dev_num is the device number.\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)\n\\details\nThe function \\b ARM_NAND_SendCommand sends a command to the NAND device.\n\nThe parameter \\em dev_num is the device number. \\n\nThe parameter \\em cmd is the command sent to the NAND device.\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)\n\\details\nSend an address to the NAND device.\nThe parameter \\em dev_num is the device number.\nThe parameter \\em addr is the address.\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)\n\\details\nThe function \\b ARM_NAND_ReadData reads data from a NAND device.\n\nThe parameter \\em dev_num is the device number. \\n\nThe parameter \\em data is a pointer to the buffer that stores the data read from a NAND device. \\n\nThe parameter \\em cnt is the number of data items to read. \\n\nThe parameter \\em mode defines the operation mode as listed in the table below.\n\nRead Data Mode                     | Description\n:----------------------------------|:--------------------------------------------\n\\ref ARM_NAND_ECC(n)               | Select ECC\n\\ref ARM_NAND_ECC0                 | Use ECC0 of selected ECC\n\\ref ARM_NAND_ECC1                 | Use ECC1 of selected ECC\n\\ref ARM_NAND_DRIVER_DONE_EVENT    | Generate \\ref ARM_NAND_EVENT_DRIVER_DONE\n\nThe data item size is defined by the data type, which depends on the configured data bus width.\n\nData type is:\n - \\em uint8_t for 8-bit data bus\n - \\em uint16_t for 16-bit data bus\n\nThe function executes in the following ways:\n - When the operation is blocking (typical for devices connected to memory bus when not using DMA), \n   then the function returns after all data is read and returns the number of data items read.\n - When the operation is non-blocking (typical for NAND controllers), then the function only starts the operation and returns with zero number of data items read.\n   After the operation is completed, the \\ref ARM_NAND_EVENT_DRIVER_DONE event is generated (if enabled by \\b ARM_NAND_DRIVER_DONE_EVENT).\n   Progress of the operation can also be monitored by calling the \\ref ARM_NAND_GetStatus function and checking the \\em busy data field.\n   Operation is automatically aborted if ECC is used and ECC correction fails, which generates the \\ref ARM_NAND_EVENT_ECC_ERROR event \n   (together with \\ref ARM_NAND_DRIVER_DONE_EVENT if enabled).\n\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)\n\\details\nThe function \\b ARM_NAND_WriteData writes data to a NAND device.\n\nThe parameter \\em dev_num is the device number. \\n\nThe parameter \\em data is a pointer to the buffer with data to write. \\n\nThe parameter \\em cnt is the number of data items to write. \\n\nThe parameter \\em mode defines the operation mode as listed in the table below.\n\nWrite Data Mode                    | Description\n:----------------------------------|:--------------------------------------------\n\\ref ARM_NAND_ECC(n)               | Select ECC\n\\ref ARM_NAND_ECC0                 | Use ECC0 of selected ECC\n\\ref ARM_NAND_ECC1                 | Use ECC1 of selected ECC\n\\ref ARM_NAND_DRIVER_DONE_EVENT    | Generate \\ref ARM_NAND_EVENT_DRIVER_DONE\n\nThe data item size is defined by the data type, which depends on the configured data bus width.\n\nData type is:\n - \\em uint8_t for 8-bit data bus\n - \\em uint16_t for 16-bit data bus\n\nThe function executes in the following ways:\n - When the operation is blocking (typical for devices connected to memory bus when not using DMA), \n   then the function returns after all data is written and returns the number of data items written.\n - When the operation is non-blocking (typical for NAND controllers), then the function only starts the operation \n   and returns with zero number of data items written. After the operation is completed, \n   the \\ref ARM_NAND_EVENT_DRIVER_DONE event is generated (if enabled by \\b ARM_NAND_DRIVER_DONE_EVENT).\n   Progress of the operation can also be monitored by calling the \\ref ARM_NAND_GetStatus function and checking the \\em busy data field.\n   Operation is automatically aborted if ECC is used and ECC generation fails, \n   which generates the \\ref ARM_NAND_EVENT_ECC_ERROR event (together with \\ref ARM_NAND_DRIVER_DONE_EVENT if enabled).\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,\n                                  uint32_t addr_col, uint32_t addr_row,\n                                  void *data, uint32_t data_cnt,\n                                  uint8_t *status, uint32_t *count)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd, uint32_t addr_col, uint32_t addr_row, void *data, uint32_t data_cnt, uint8_t *status, uint32_t *count)\n\\details\nThe function \\b ARM_NAND_ExecuteSequence executes a sequence of operations for a NAND device.\n\nThe parameter \\em dev_num is the device number. \\n\nThe parameter \\em code is the sequence encoding as defined in the table <b>Sequence execution Code</b>. \\n\nThe parameter \\em cmd is the command or a series of commands. \\n\nThe parameter \\em addr_col is the column address. \\n\nThe parameter \\em addr_row is the row address. \\n\nThe parameter \\em data is a pointer to the buffer that stores the data to or loads the data from. \\n\nThe parameter \\em data_cnt is the number of data items to read or write in one iteration. \\n\nThe parameter \\em status is a pointer to the buffer that stores the status read. \\n\nThe parameter \\em count is a pointer to the number of iterations. \\n\n\n\\b ARM_NAND_CODE_xxx specifies sequence execution codes.\n\nSequence Execution Code            | Description\n:----------------------------------|:--------------------------------------------\n\\ref ARM_NAND_CODE_SEND_CMD1       | Send Command 1 (cmd[7..0])\n\\ref ARM_NAND_CODE_SEND_ADDR_COL1  | Send Column Address 1 (addr_col[7..0])\n\\ref ARM_NAND_CODE_SEND_ADDR_COL2  | Send Column Address 2 (addr_col[15..8])\n\\ref ARM_NAND_CODE_SEND_ADDR_ROW1  | Send Row Address 1 (addr_row[7..0])\n\\ref ARM_NAND_CODE_SEND_ADDR_ROW2  | Send Row Address 2 (addr_row[15..8])\n\\ref ARM_NAND_CODE_SEND_ADDR_ROW3  | Send Row Address 3 (addr_row[23..16])\n\\ref ARM_NAND_CODE_INC_ADDR_ROW    | Auto-increment Row Address\n\\ref ARM_NAND_CODE_WRITE_DATA      | Write Data\n\\ref ARM_NAND_CODE_SEND_CMD2       | Send Command 2 (cmd[15..8])\n\\ref ARM_NAND_CODE_WAIT_BUSY       | Wait while R/Bn busy\n\\ref ARM_NAND_CODE_READ_DATA       | Read Data\n\\ref ARM_NAND_CODE_SEND_CMD3       | Send Command 3 (cmd[23..16])\n\\ref ARM_NAND_CODE_READ_STATUS     | Read Status byte and check FAIL bit (bit 0)\n\\ref ARM_NAND_ECC(n)               | Select ECC\n\\ref ARM_NAND_ECC0                 | Use ECC0 of selected ECC\n\\ref ARM_NAND_ECC1                 | Use ECC1 of selected ECC\n\\ref ARM_NAND_DRIVER_DONE_EVENT    | Generate \\ref ARM_NAND_EVENT_DRIVER_DONE\n\nThe data item size is defined by the data type, which depends on the configured data bus width.\n\nData type is:\n - \\em uint8_t for 8-bit data bus\n - \\em uint16_t for 16-bit data bus\n\nThe function is non-blocking and returns as soon as the driver has started executing the specified sequence.\nWhen the operation is completed, the \\ref ARM_NAND_EVENT_DRIVER_DONE event is generated (if enabled by \\b ARM_NAND_DRIVER_DONE_EVENT).\nProgress of the operation can also be monitored by calling the \\ref ARM_NAND_GetStatus function and checking the \\em busy data field.\n\nDriver executes the number of specified iterations where in each iteration \nitems specified by \\b ARM_NAND_CODE_xxx are executed in the order as listed in the table <b>Sequence execution Code</b>.\nThe parameter \\em count is holding the current number of iterations left.\n\nExecution is automatically aborted and \\ref ARM_NAND_EVENT_DRIVER_DONE event is generated (if enabled by \\b ARM_NAND_DRIVER_DONE_EVENT):\n - if Read Status is enabled and the FAIL bit (bit 0) is set\n - if ECC is used and ECC fails (also sets \\ref ARM_NAND_EVENT_ECC_ERROR event)\n\n\\note\n\\ref ARM_NAND_CODE_WAIT_BUSY can only be specified if the Device Ready event can be generated (reported by \\em event_device_ready in \\ref ARM_NAND_CAPABILITIES).\nThe event \\ref ARM_NAND_EVENT_DEVICE_READY is not generated during sequence execution but rather used internally by the driver.\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_AbortSequence (uint32_t dev_num)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_AbortSequence (uint32_t dev_num)\n\\details\nThe function \\b ARM_NAND_AbortSequence aborts execution of the current sequence for a NAND device.\n\nThe parameter \\em dev_num is the device number.\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)\n\\details\nThe function \\b ARM_NAND_Control controls the NAND interface and executes operations.\n\nThe parameter \\em dev_num is the device number. \\n\nThe parameter \\em control specifies the operation. \\n\nThe parameter \\em arg provides (depending on the \\em control) additional information or sets values.\n\nThe table lists the operations for the parameter \\em control.\n\nParameter \\em control            | Operation\n:--------------------------------|:--------------------------------------------\n\\ref ARM_NAND_BUS_MODE           | Set the bus mode. The parameter \\em arg sets the \\ref bus_mode_tab \"\\b Bus Mode\".\n\\ref ARM_NAND_BUS_DATA_WIDTH     | Set the data bus width. The parameter \\em arg sets the \\ref bus_data_width_tab \"\\b Bus Data Width\".\n\\ref ARM_NAND_DRIVER_STRENGTH    | Set the driver strength. The parameter \\em arg sets the \\ref driver_strength_tab \"\\b Driver Strength\".\n\\ref ARM_NAND_DRIVER_READY_EVENT | Control generation of callback event \\ref ARM_NAND_EVENT_DRIVER_READY. Enable: \\em arg = \\token{1}. Disable: \\em arg = \\token{0}.\n\\ref ARM_NAND_DEVICE_READY_EVENT | Control generation of callback event \\ref ARM_NAND_EVENT_DEVICE_READY; Enable: \\em arg = \\token{1}. Disable: \\em arg = \\token{0}.\n\n<b>See Also</b>\n- \\ref ARM_NAND_GetCapabilities returns information about supported operations, which are stored in the structure \\ref ARM_NAND_CAPABILITIES.\n- \\ref ARM_NAND_SignalEvent provides information about the callback events \\ref ARM_NAND_EVENT_DRIVER_READY and \\ref ARM_NAND_EVENT_DEVICE_READY\n\nThe table lists values for the parameter \\em arg used with the \\em control operation \\ref ARM_NAND_BUS_MODE, \\ref ARM_NAND_BUS_DATA_WIDTH, and\n\\ref ARM_NAND_DRIVER_STRENGTH. Values from different categories can be ORed.\n\n\\anchor bus_mode_tab\n<table class=\"cmtable\" summary=\"\">\n<tr><th> Parameter \\em arg  <br> for <i>control</i> = \\ref ARM_NAND_BUS_MODE   </th>\n    <th> Bit                  </th>\n\t<th> Category             </th>\n    <th> Description          </th>\n    <th width=\"30%\"> Supported when \\ref ARM_NAND_CAPABILITIES            </th></tr>\n<tr><td> \\ref ARM_NAND_BUS_TIMING_MODE_0 (default)            </td>\n    <td rowspan=\"8\" style=\"text-align:right\"> 0..3            </td>\n    <td rowspan=\"8\"> \\anchor bus_timing_tab  Bus Timing Mode  </td>\n\t<td>             \\token{0}                                </td>\n    <td rowspan=\"8\"> The maximum timing mode that can be applied to a specific \\ref bus_data_interface_tab  \"\\b Bus Data Interface\"\n\t                 is stored in the data fields: <br><br>\n\t\t\t\t\t <i>sdr_timing_mode</i> - for SDR <br>\n\t\t\t\t\t <i>ddr_timing_mode</i> - for NV-DDR <br>\n\t\t\t\t\t <i>ddr2_timing_mode</i> - for NV_DDR2                                 </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_TIMING_MODE_1            </td><td>  \\token{1}                    </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_TIMING_MODE_2            </td><td>  \\token{2}                    </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_TIMING_MODE_3            </td><td>  \\token{3}                    </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_TIMING_MODE_4            </td><td>  \\token{4} (SDR EDO capable)  </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_TIMING_MODE_5            </td><td>  \\token{5} (SDR EDO capable)  </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_TIMING_MODE_6            </td><td>  \\token{6} (NV-DDR2 only)     </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_TIMING_MODE_7            </td><td>  \\token{7} (NV-DDR2 only)     </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_SDR (default)      \\anchor bus_data_interface_tab      </td>\n    <td rowspan=\"3\" style=\"text-align:right\"> 4..7  </td>\n    <td rowspan=\"3\">   Bus Data Interface   </td>\n\t<td>             SDR  (Single Data Rate) - Traditional interface      </td>\n    <td>     <i>always supported</i>                </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR                      </td><td>  NV-DDR  (Double Data Rate)  </td><td>  data field <i>ddr</i> = \\token{1} </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR2                     </td><td>  NV-DDR2 (Double Data Rate)  </td><td>  data field <i>ddr2</i> = \\token{1} </td></tr>\n<tr><td style=\"white-space: nowrap\"> \\ref ARM_NAND_BUS_DDR2_DO_WCYC_0 (default) </td>\n    <td rowspan=\"4\" style=\"text-align:right\"> 8..11 </td>\n    <td rowspan=\"4\" style=\"white-space: nowrap\"> Data Output Warm-up   \\anchor bus_output_tab  </td>\n\t<td> Set the DDR2 Data Output Warm-up to \\token{0} cycles      </td>\n    <td rowspan=\"4\">  <b>Data Output Warm-up</b> cycles are dummy cycles for interface calibration with no incremental data transfer\n                      and apply to NV-DDR2 of the \\ref bus_data_interface_tab \"\\b Bus Data Interface\".\t\n\t</td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR2_DO_WCYC_1           </td><td> Set the DDR2 Data Output Warm-up to \\token{1} cycles </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR2_DO_WCYC_2           </td><td> Set the DDR2 Data Output Warm-up to \\token{2} cycles </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR2_DO_WCYC_4           </td><td> Set the DDR2 Data Output Warm-up to \\token{4} cycles </td></tr>\n<tr><td style=\"white-space: nowrap\"> \\ref ARM_NAND_BUS_DDR2_DI_WCYC_0 (default) \\anchor bus_input_tab</td>\n    <td rowspan=\"4\" style=\"text-align:right\"> 12..15 </td>\n    <td rowspan=\"4\" style=\"white-space: nowrap\">   Data Input Warm-up   </td>\n\t<td> Set the DDR2 Data Input Warm-up to \\token{0} cycles      </td>\n    <td rowspan=\"4\">  <b>Data Input Warm-up</b> cycles are dummy cycles for interface calibration with no incremental data transfer\n                      and apply to NV-DDR2 of the \\ref bus_data_interface_tab \"\\b Bus Data Interface\".\t\n\t</td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR2_DI_WCYC_1           </td><td> Set the DDR2 Data Input Warm-up to \\token{1} cycles </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR2_DI_WCYC_2           </td><td> Set the DDR2 Data Input Warm-up to \\token{2} cycles </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR2_DI_WCYC_4           </td><td> Set the DDR2 Data Input Warm-up to \\token{4} cycles </td></tr>\n<tr><td style=\"white-space: nowrap\"> \\ref ARM_NAND_BUS_DDR2_VEN \\anchor bus_misc_tab </td>\n    <td style=\"text-align:right\"> 16 </td>\n    <td rowspan=\"3\" style=\"white-space: nowrap\">   Miscellaneous   </td>\n\t<td> Set the DDR2 Enable external VREFQ as reference      </td>\n    <td rowspan=\"3\">  &nbsp;\n\t</td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR2_CMPD    </td><td style=\"text-align:right\"> 17 </td><td> Set the DDR2 Enable complementary DQS (DQS_c) signal </td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DDR2_CMPR    </td><td style=\"text-align:right\"> 18 </td><td> Set the DDR2 Enable complementary RE_n (RE_c) signal </td></tr>\n<tr><th> Parameter \\em arg  <br> for <i>control</i> = \\ref ARM_NAND_BUS_DATA_WIDTH   </th>\n    <th> Bit                  </th>\n\t<th> Category      \\anchor bus_data_width_tab       </th>\n    <th> Description          </th>\n    <th width=\"30%\"> Supported when \\ref ARM_NAND_CAPABILITIES            </th></tr>\n<tr><td style=\"white-space: nowrap\"> \\ref ARM_NAND_BUS_DATA_WIDTH_8 (default) </td>\n    <td rowspan=\"2\" style=\"text-align:right\"> 0..1 </td>\n    <td rowspan=\"2\" style=\"white-space: nowrap\">   Bus Data Width        </td>\n\t<td> Set to \\token{8 bit}        </td>\n    <td>  <i>always supported</i>\n\t</td></tr>\n<tr><td> \\ref ARM_NAND_BUS_DATA_WIDTH_16  </td><td> Set to \\token{16 bit}    </td><td> data field <i>data_width_16</i> = \\token{1}   </td></tr>\n<tr><th style=\"white-space: nowrap\"> Parameter \\em arg  <br> for <i>control</i> = \\ref ARM_NAND_DRIVER_STRENGTH   </th>\n    <th> Bit                  </th>\n\t<th> Category   \\anchor driver_strength_tab        </th>\n    <th> Description          </th>\n    <th width=\"30%\"> Supported when \\ref ARM_NAND_CAPABILITIES            </th></tr>\n<tr><td style=\"white-space: nowrap\"> \\ref ARM_NAND_DRIVER_STRENGTH_18 </td>\n    <td rowspan=\"4\" style=\"text-align:right\"> 0..3 </td>\n    <td rowspan=\"4\" style=\"white-space: nowrap\"> Driver Strength     </td>\n\t<td> Set the Driver Strength 2.0x = 18 Ohms     </td>\n    <td> data field <i>driver_strength_18</i> = \\token{1} \n\t</td></tr>\n<tr><td> \\ref ARM_NAND_DRIVER_STRENGTH_25            </td><td> Set the Driver Strength 1.4x = 25 Ohms </td><td> data field <i>driver_strength_25</i> = \\token{1} </td></tr>\n<tr><td> \\ref ARM_NAND_DRIVER_STRENGTH_35 (default)  </td><td> Set the Driver Strength 1.0x = 35 Ohms </td><td> <i>always supported</i>  </td></tr>\n<tr><td> \\ref ARM_NAND_DRIVER_STRENGTH_50            </td><td> Set the Driver Strength 0.7x = 50 Ohms </td><td> data field <i>driver_strength_50</i> = \\token{1} </td></tr>\n</table>\n\n<b>Example</b>\n\\code\nextern ARM_DRIVER_NAND Driver_NAND0;\n \nstatus = Driver_NAND0.Control (0, ARM_NAND_BUS_MODE, ARM_NAND_BUS_TIMING_MODE_5 | \n                                                     ARM_NAND_BUS_DDR2          | \n                                                     ARM_NAND_BUS_DDR2_VEN);\n\t\t\t\t\t\t\t\t\t\t\t    \nstatus = Driver_NAND0.Control (0, ARM_NAND_BUS_DATA_WIDTH,  ARM_NAND_BUS_DATA_WIDTH_16); \n \nstatus = Driver_NAND0.Control (0, ARM_NAND_DRIVER_STRENGTH, ARM_NAND_DRIVER_STRENGTH_50);\n\\endcode\n\n*******************************************************************************************************************/\n\nARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)  {\n  return 0;\n}\n/**\n\\fn ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)\n\\details\nThe function \\b ARM_NAND_GetStatus returns the current NAND device status.\n\nThe parameter \\em dev_num is the device number.\n*******************************************************************************************************************/\n\nint32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)\n\\details\nThe function \\b ARM_NAND_InquireECC reads error correction code information.\n\nThe parameter \\em index is the ECC index and is used to retrieve different ECC configurations. \\n\nThe parameter \\em info is a pointer of type \\ref ARM_NAND_ECC_INFO. The data fields store the information.\n\nWhen multiple different ECC configurations exist, ARM_NAND_ECC_INFO structure exists for each configuration. Parameter\n\\em index denotes which configuration will be retrieved. Value of index should start with zero to retrieve first ECC\nconfiguration and should be incremented in order to retrieve next ECC configuration. When index is out of range function\nARM_NAND_InquireECC returns with error.\n\nParameter \\em index is used by \\ref ARM_NAND_ECC(n) in \\ref ARM_NAND_ReadData, \\ref ARM_NAND_WriteData and\n\\ref ARM_NAND_ExecuteSequence to select suitable ECC configuration.\n\n<b>Example</b>\n\\code\nextern ARM_DRIVER_NAND Driver_NAND0; \n\nARM_NAND_ECC_INFO ecc;\nint32_t idx;\n \nidx = 0;\nwhile (Driver_NAND0.InquireECC (idx, &ecc) == ARM_DRIVER_OK) {\n  // Examine retrieved ECC configuration\n  if (ecc.type == 2) {\n    // Algorithm ECC0 protects Main+Spare\n  }\n  // ..\n  idx++;\n}\n\\endcode\n*******************************************************************************************************************/\n\nvoid ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)  {\n  return 0;\n}\n/**\n\\fn void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)\n\\details\nThe function \\b ARM_NAND_SignalEvent is a callback function registered by the function \\ref ARM_NAND_Initialize.\n\nThe parameter \\em dev_num is the device number. \\n\nThe parameter \\em event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nNot every event is necessarily generated by the driver. This depends on the implemented capabilities stored in the \ndata fields of the structure \\ref ARM_NAND_CAPABILITIES, which can be retrieved with the function \\ref ARM_NAND_GetCapabilities.\n\nThe following events can be generated:\n\nParameter \\em event               | Bit | Description\n:---------------------------------|-----|:---------------------------\n\\ref ARM_NAND_EVENT_DEVICE_READY  | 0   | Occurs when rising edge is detected on R/Bn (Ready/Busy) pin indicating that the device is ready.\n\\ref ARM_NAND_EVENT_DRIVER_READY  | 1   | Occurs to indicate that commands can be executed (after previously being busy and not able to start the requested operation).\n\\ref ARM_NAND_EVENT_DRIVER_DONE   | 2   | Occurs after an operation completes. An operation was successfully started before with \\ref ARM_NAND_ReadData, \\ref ARM_NAND_WriteData, \\ref ARM_NAND_ExecuteSequence.\n\\ref ARM_NAND_EVENT_ECC_ERROR     | 3   | Occurs when ECC generation failed or ECC correction failed. An operation was successfully started before with \\ref ARM_NAND_ReadData, \\ref ARM_NAND_WriteData, \\ref ARM_NAND_ExecuteSequence. \n\nThe event \\ref ARM_NAND_EVENT_DEVICE_READY occurs after complete execution of commands \n(initiated with the functions \\ref ARM_NAND_SendCommand, \\ref ARM_NAND_SendAddress, \\ref ARM_NAND_ReadData, \\ref ARM_NAND_WriteData, \\ref ARM_NAND_ExecuteSequence).\nIt is useful to indicate completion of complex operations (such as erase). \nThe event is only generated when \\ref ARM_NAND_GetCapabilities returns data field \\em event_device_ready = \\token{1}\nand was enabled by calling \\ref ARM_NAND_Control (\\ref ARM_NAND_DEVICE_READY_EVENT, 1).\nIf the event is not available, poll the \\em busy data field using the function \\ref ARM_NAND_GetStatus.\n\nThe event \\ref ARM_NAND_EVENT_DRIVER_READY occurs when previously a function \n(\\ref ARM_NAND_SendCommand, \\ref ARM_NAND_SendAddress, \\ref ARM_NAND_ReadData, \\ref ARM_NAND_WriteData, \\ref ARM_NAND_ExecuteSequence) \nreturned with \\ref ARM_DRIVER_ERROR_BUSY. It is useful when functions are called simultaneously from independent threads \n(for example to control multiple devices) and the threads have no knowledge about each other (driver rejects reentrant calls with return of \\ref ARM_DRIVER_ERROR_BUSY). \n\\em dev_num indicates the device that returned previously busy. \n*******************************************************************************************************************/\n\n/**\n@}\n*/ \n// End NAND Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_NAND_AddOn.txt",
    "content": "/*\nPurpose:    The text might be of interest in another place.\n            We have to decide whether we want to use it.\n            \n            Until a decision is made, do not delete the file.\n\nUsage:      Storage of text. Not used in doxygen.\n\nCreated:    March 21, 2014\nAuthor :    Bruno\nChanged:\n*/\n\n\n\n/**\n\\struct     ARM_NAND_DEVICE \n\\details\nStores the characteristics of a NAND Flash device. This includes the page layout configuration, NAND type, \ndevice number (chip select), number of blocks, pages, sectors, and error correction code.\n\n<b>Parameter for:</b>\n  - \\ref ARM_NAND_Initialize\n\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_NAND_ECC_INFO_x\n\\details \nStores the default NAND page layout definition (with \\ref spare_size and \\ref spare_offset),\nwhich contains a \\b Spare area after each sector. The struct \\b ARM_NAND_ECC_INFO defines the \\b Spare area.\n\nThe page size is defined as the sum of \\b User area plus \\b Spare area. \nEach page has a small number of associated \"spare\" bytes (typically 1/32 of the data size) to store the Error Correction Algorithms (ECC). \n\nThe following standard page sizes are available:\n\nPage Size| User + Spare Area\n---------|-------------------\n528      |  512 +  16 bytes\n2112     | 2048 +  64 bytes\n4224     | 4096 + 128 bytes\n8448     | 8192 + 256 bytes\n\n\n\\image html NAND_PageLayout.png \"Default Page Layout\"\n\n<p>&nbsp;</p>\n\\image html NAND_SpareArea.png \"Organization of the default 16-byte Spare area\"\n\nNAND devices require bad block management by the driver software or by a separate controller chip. \nFor example, SD cards have mechanisms that execute wear leveling and  bad block management.\nThe memory capacity shrinks as more blocks are marked bad.\nThe block size is a value specified as amount of flash pages. \n\nThe following block sizes are available:\n\nBlock Size| Pages\n----------|-------------------\n  8       |   8\n 16       |  16\n 32       |  32\n 64       |  64\n128       | 128\n256       | 256\n\n\\note\nNAND chip manufacturers document the order in which pages can be written. \nTypically, single pages of an erase block must be written in sequential order starting from the first. Random-order writes are prohibited or unspecified.\n\n<b>Parameter for:</b>\n  - \\ref ARM_NAND_DEVICE structure\n*******************************************************************************************************************/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_SAI.c",
    "content": "/* -----------------------------------------------------------------------------\n * Copyright (c) 2013-2014 ARM Ltd.\n *\n * This software is provided 'as-is', without any express or implied warranty.\n * In no event will the authors be held liable for any damages arising from\n * the use of this software. Permission is granted to anyone to use this\n * software for any purpose, including commercial applications, and to alter\n * it and redistribute it freely, subject to the following restrictions:\n *\n * 1. The origin of this software must not be misrepresented; you must not\n *    claim that you wrote the original software. If you use this software in\n *    a product, an acknowledgment in the product documentation would be\n *    appreciated but is not required.\n *\n * 2. Altered source versions must be plainly marked as such, and must not be\n *    misrepresented as being the original software.\n *\n * 3. This notice may not be removed or altered from any source distribution.\n *\n *\n * $Date:        9. Dec 2014\n * $Revision:    V1.00\n *\n * Project:      SAI (Serial Audio Interface) Driver definitions\n * -------------------------------------------------------------------------- */\n\n/**\n\\defgroup sai_interface_gr SAI Interface\n\\brief   Driver API for Serial Audio Interface (%Driver_SAI.h)\n\\details \nThe <b>Serial Audio Interface</b> (SAI) implements a synchronous serial bus interface for connecting digital audio devices. \nIt is by far the most common mechanism used to transfer two channels of audio data between devices within a system. \\b SAI\ncan transfer digital audio using various protocols:\n- \\ref Driver_SAI_I2S\n- \\ref Driver_SAI_MSB\n- \\ref Driver_SAI_LSB\n- \\ref Driver_SAI_PCM\n- \\ref Driver_SAI_AC97\n- \\ref Driver_SAI_User\n\n\n<b>Block Diagram</b>\n\n<p>&nbsp;</p>\n\\image html SAI_Schematics.png \"Simplified SAI Schematic\"\n<p>&nbsp;</p>\n\n\n<b>SAI API</b>\n\nThe following header files define the Application Programming Interface (API) for the SAI interface:\n  - \\b %Driver_SAI.h : Driver API for Serial Audio Interface\n\nThe driver implementation is a typical part of the\n<a class=\"el\" href=\"../../Pack/html/index.html\" target=\"_blank\">Device Family Pack (DFP)</a> that supports the peripherals of\nthe microcontroller family.\n\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_SAI : access struct for SAI driver functions\n  \n\\section Driver_SAI_I2S I2S\n<a href=\"https://en.wikipedia.org/wiki/I%C2%B2S\" target=\"_blank\">Integrated Interchip Sound</a> (\\b I2S) is a serial bus\ninterface that connects digital audio devices together. It was introduced by Philips (now\n<a href=\"http://www.nxp.com\" target=\"_blank\">NXP</a>) in the late 80's and last revised 1996. It uses pulse code modulation\nto exchange the audio data between the devices. The following timing diagram explains the operation:\n \n\\image html driver_sai_i2s.png\n\nI2S separates the clock (\\b SCK) from the serial data (\\b SD), resulting in a lower jitter. A complete audio data frame\nconsists of two slots, one for the left channel and one for the right. The slot size equals the data size.\nThe word select (\\b WS) line lets the device know whether the left channel (WS is low) or the right channel (WS is high) is\ncurrently being transmitted. WS has a 50% duty-cycle signal that has the same frequency as the sample frequency. It is an\nearly signal, meaning that the WS line changes one clock cycle before the actual data (SD) is transmitted (left or right).\nThe data on SD is always transmitted MSB first and can have a data size of 8 up to 32 bits.\n\nIn terms of the CMSIS-Driver for SAI, the I2S protocol can be described as follows:\n- Data Size: 8..32 (MSB first)\n- Clock Polarity: Drive on falling edge, Capture on rising edge\n- Frame Length: 2 * Data Size = 2 * Slot Size\n- Frame Sync Width: Frame Length / 2\n- Frame Sync Polarity: Active Low\n- Frame Sync Early\n- Slot Count: 2 (L R)\n- Slot Size: Data Size\n- Slot Offset: 0\n\n\n\\section Driver_SAI_MSB MSB Justified\n\\b MSB \\b Justified is much like \\ref Driver_SAI_I2S, with a few differences:\n\n\\image html driver_sai_msb.png\n\nUnlike I2S, in MSB Justified the word select (\\b WS) signals the left channel when it is active high and the right channel,\nwhen it is active low. The signal changes when the first actual \\b SD data is available. It might happen that a frame (left\nor right) is not fully filled with data. In this case, all data after the LSB is forced to zero.\n\nIn terms of the CMSIS-Driver for SAI, the MSB Justified protocol can be described as follows:\n- Data Size: 8..32 (MSB first)\n- Clock Polarity: Drive on falling edge, Capture on rising edge\n- Frame Length: 2 * Slot Size\n- Frame Sync Width: Frame Length / 2\n- Frame Sync Polarity: Active High\n- Slot Count: 2 (L R)\n- Slot Size: Data Size or higher (16/32)\n- Slot Offset: 0 (Zero padding after Data: Slot Size - Data Size)\n\n\\section Driver_SAI_LSB LSB Justified\n\\b LSB \\b Justified is much like \\ref Driver_SAI_MSB, with the single difference that the padding 0's are sent before the\nfirst actual data (MSB on \\b SD):\n\n\\image html driver_sai_lsb.png\n\nIn terms of the CMSIS-Driver for SAI, the LSB Justified protocol can be described as follows:\n- Data Size: 8..32 (MSB first)\n- Clock Polarity: Drive on falling edge, Capture on rising edge\n- Frame Length: 2*Slot Size\n- Frame Sync Width: Frame Length / 2\n- Frame Sync Polarity: Active High\n- Slot Count: 2\n- Slot Size: Data Size or higher (16/32)\n- Slot Offset: Slot Size - Data Size (Zero padding before Data: Slot Size - Data Size)\n\n\\section Driver_SAI_PCM PCM\n<a href=\"https://en.wikipedia.org/wiki/Pulse-code_modulation\" target=\"_blank\">Pulse Code Modulation</a> (\\b PCM) differs to\nthe previous protocols in a few ways:\n\n\\image html driver_sai_pcm.png\n\n- Only one channel is transferred.\n\n- There are two types of synchronization modes available:\n  - In \\b short \\b frame sync mode, the falling edge of \\b Frame \\b Sync indicates the start of the serial data \\b SD. \\b Frame \\b Sync is always\n    one clock cycle long.\n  - In \\b long \\b frame sync mode, the rising edge of \\b Frame \\b Sync indicates the start of the serial data \\b SD. \\b Frame \\b Sync stays active\n    high for 13 clock cycles.\n\nIn terms of the CMSIS-Driver for SAI, the PCM protocol can be described as follows:\\n\n\\b PCM \\b Short \\b Frame\n- Data Size: 8..32 (MSB first)\n- Clock Polarity: Drive on falling edge, Capture on rising edge\n- Frame Length: Slot Size\n- Frame Sync Width: 1\n- Frame Sync Polarity: Active High\n- Frame Sync Early\n- Slot Count: 1\n- Slot Size: Data Size or higher (16/32)\n- Slot Offset: 0\n\n\\b PCM \\b Long \\b Frame\n- Data Size: 16..32 (MSB first)\n- Clock Polarity: Drive on falling edge, Capture on rising edge\n- Frame Length: Slot Size\n- Frame Sync Width: 13\n- Frame Sync Polarity: Active High\n- Slot Count: 1\n- Slot Size: Data Size or higher (32)\n- Slot Offset: 0\n\n\\section Driver_SAI_AC97 AC'97\n<a href=\"https://en.wikipedia.org/wiki/AC'97\" target=\"_blank\">Audio Codec '97</a> was developed by\n<a href=\"http://www.intel.com\" target=\"_blank\">Intel</a>. It is composed of five wires: the clock (12.288 MHz), a sync\nsignal, a reset signal, and two data wires: sdata_out (contains the AC97 output) and sdata_in (contains the CODEC output).\nFor more information, consult the\n<a href=\"http://inst.eecs.berkeley.edu/~cs150/Documents/ac97_r23.pdf\" target=\"_blank\">standard documentation</a>.\n\n\\section Driver_SAI_User User Defined Protocol\nUsing the control structs of the CMSIS-Driver SAI, it is possible to create support for nearly all serial audio protocols\nthat are available today. \n\n\\image html driver_sai_user.png\n\nThe following properties can be configured for a user protocol:\n- Data Size in bits (8..32)\n- Data Bit Order: MSB first (default) or LSB first\n- Clock Polarity:\n  - Driver on falling edge, Capture on rising edge (default)\n  - Driver on rising edge, Capture on falling edge\n- Frame Length in bits\n- Frame Sync Width in bits (default=1)\n- Frame Sync Polarity: active high (default) or low\n- Frame Sync Early: Sync signal one bit before the first bit of frame\n- Slot Count: number of slots in frame (default=1)\n- Slot Size: equal to data size (default) or 16 or 32-bit\n- Slot Offset: offset of first data bit in slot (default=0)\n\nFor more information, refer to \\ref ARM_SAI_Control that explains the different configuration options in more detail.\n\n@{\n*/\n\n\n/** \n\\struct     ARM_DRIVER_SAI\n\\details\nThe functions of the SAI driver are accessed by function pointers exposed by this structure.\nRefer to \\ref DriverFunctions for overview information.\n\nEach instance of an SAI interface provides such an access structure. \nThe instance is identified by a postfix number in the symbol name of the access structure, for example:\n - \\b Driver_SAI0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_SAI1 is the name of the access struct of the second instance (no. 1).\n\nA middleware configuration setting allows connecting the middleware to a specific driver instance \\b %Driver_SAI<i>n</i>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_SAI_CAPABILITIES \n\\details\nAn SAI driver can be implemented with different capabilities (for example protocol support). The data fields of this\nstructure encode the capabilities implemented by this driver. If a certain hardware peripheral is not able to handle one\nof the protocols directly (not advertised using ARM_SAI_CAPABILITIES), then it might be possible to implement it using\nthe \\ref Driver_SAI_User (if supported).\n\n<b>Returned by:</b>\n  - \\ref ARM_SAI_GetCapabilities\n*****************************************************************************************************************/\n\n/**\n\\struct ARM_SAI_STATUS \n\\details\nStructure with information about the status of the SAI. The data fields encode busy flags and error flags.\n\n<b>Returned by:</b>\n  - \\ref ARM_SAI_GetStatus\n*****************************************************************************************************************/\n\n/**\n\\typedef    ARM_SAI_SignalEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_SAI_SignalEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_SAI_Initialize\n*******************************************************************************************************************/\n\n\n/****** SAI specific error codes *****/\n/**\n\\defgroup sai_execution_status Status Error Codes\n\\ingroup common_drv_gr\n\\brief Negative values indicate errors (SAI has specific codes in addition to common \\ref execution_status). \n\\details \nThe SAI driver has additional status error codes that are listed below.\n\\note\n- In case multiple errors exist, only the first encountered error will be reported.\n- errors ARM_SAI_ERROR_BIT_ORDER, ARM_SAI_ERROR_FRAME_SYNC_xxx, ARM_SAI_ERROR_SLOT_xxx will only be reported in \\ref Driver_SAI_User mode.\n- The SAI driver also returns the common \\ref execution_status.\n  \n@{\n\\def ARM_SAI_ERROR_SYNCHRONIZATION       \nThe \\b synchronization requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_PROTOCOL\nThe \\b protocol requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_DATA_SIZE     \nThe <b>data size</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_BIT_ORDER\nThe <b>bit order</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_MONO_MODE            \nThe <b>mono mode</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_COMPANDING   \nThe <b>companding</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_CLOCK_POLARITY \nThe <b>clock polarity</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_AUDIO_FREQ\nThe <b>audio frequency</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_MCLK_PIN\nThe <b>MCLK pin</b> setting requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_MCLK_PRESCALER       \nThe <b>MCLK prescaler</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_FRAME_LENGTH\nThe <b>frame length</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_FRAME_SYNC_WIDTH \nThe <b>frame sync width</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_FRAME_SYNC_POLARITY\nThe <b>frame sync polarity</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_FRAME_SYNC_EARLY      \nThe <b>frame sync early</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_SLOT_COUNT \nThe <b>slot count</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_SLOT_SIZE\nThe <b>slot size</b> requested with the function \\ref ARM_SAI_Control is not supported.\n\n\\def ARM_SAI_ERROR_SLOT_OFFESET\nThe <b>slot offset</b> requested with the function \\ref ARM_SAI_Control is not supported.\n@}\n*/\n\n\n/****** SAI Event *****/\n/**\n\\defgroup SAI_events SAI Events\n\\ingroup sai_interface_gr\n\\brief The SAI driver generates call back events that are notified via the function \\ref ARM_SAI_SignalEvent.\n\\details \nThis section provides the event values for the \\ref ARM_SAI_SignalEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def ARM_SAI_EVENT_SEND_COMPLETE    \n\\def ARM_SAI_EVENT_RECEIVE_COMPLETE \n\\def ARM_SAI_EVENT_TX_UNDERFLOW     \n\\def ARM_SAI_EVENT_RX_OVERFLOW      \n\\def ARM_SAI_EVENT_FRAME_ERROR      \n@}\n*/\n\n\n/**\n\\defgroup sai_control SAI Control Codes\n\\ingroup sai_interface_gr\n\\brief Many parameters of the SAI driver are configured using the \\ref ARM_SAI_Control function.\n\\details\n@{\nThe various SAI control codes define:\n  - \\ref sai_configure_control specifies SAI configuration\n  - \\ref sai_controls specifies SAI controls\n\nRefer to the \\ref ARM_SAI_Control function for further details.\n*/\n\n\n/**\n\\defgroup sai_configure_control SAI Configuration\n\\ingroup sai_control\n\\brief Specify Transmitter/Receiver configuration.\n\\details\n@{\nConfiguration is specified by ORing \\b ARM_SAI_CONFIGURE_<i>x</i> with the following parameters:\n - \\ref sai_mode_control\n - \\ref sai_sync_control\n - \\ref sai_protocol_control\n - \\ref sai_data_bits_control\n - \\ref sai_bit_order_control\n - \\ref sai_mono_control\n - \\ref sai_clock_pol_control\n - \\ref sai_companding_control\n - \\ref sai_mclk_pin_control\n\nAdditional configuration specified by \\em arg1:\n - \\ref sai_frame_control\n - \\ref sai_slot_control\n\nAdditional configuration specified by \\em arg2:\n - <b>Audio Frequency</b> (Master only)\n - \\ref sai_mclk_pres_control\n\n\\defgroup sai_mode_control SAI Mode\n\\ingroup sai_configure_control\n\\brief Defines Transmitter/Receiver mode.\n\\details\n@{\n\\def ARM_SAI_MODE_MASTER\n\\def ARM_SAI_MODE_SLAVE\n@}\n\n\\defgroup sai_sync_control SAI Synchronization\n\\ingroup sai_configure_control\n\\brief Defines Transmitter/Receiver synchronization.\n\\details\n@{\n\\def ARM_SAI_ASYNCHRONOUS\n\\def ARM_SAI_SYNCHRONOUS\n@}\n\n\\defgroup sai_protocol_control SAI Protocol\n\\ingroup sai_configure_control\n\\brief Defines Transmitter/Receiver protocol.\n\\details\n@{\n\\def ARM_SAI_PROTOCOL_USER\n\\def ARM_SAI_PROTOCOL_I2S\n\\def ARM_SAI_PROTOCOL_MSB_JUSTIFIED\n\\def ARM_SAI_PROTOCOL_LSB_JUSTIFIED\n\\def ARM_SAI_PROTOCOL_PCM_SHORT\n\\def ARM_SAI_PROTOCOL_PCM_LONG\n\\def ARM_SAI_PROTOCOL_AC97\n@}\n\n\\defgroup sai_data_bits_control SAI Data Size\n\\ingroup sai_configure_control\n\\brief Defines data size in bits (per channel/slot).\n\\details\n@{\n\\def ARM_SAI_DATA_SIZE(n)\n@}\n\n\\defgroup sai_bit_order_control SAI Bit Order\n\\ingroup sai_configure_control\n\\brief Defines the bit order.\n\\details\n@{\n\\def ARM_SAI_MSB_FIRST\n\\def ARM_SAI_LSB_FIRST\n@}\n\n\\defgroup sai_mono_control SAI Mono Mode\n\\ingroup sai_configure_control\n\\brief Defines mono mode.\n\\details\n@{\n\\def ARM_SAI_MONO_MODE\n@}\n\n\\defgroup sai_companding_control SAI Companding\n\\ingroup sai_configure_control\n\\brief Defines companding.\n\\details\n@{\n\\def ARM_SAI_COMPANDING_NONE\n\\def ARM_SAI_COMPANDING_A_LAW\n\\def ARM_SAI_COMPANDING_U_LAW\n@}\n\n\\defgroup sai_clock_pol_control SAI Clock Polarity\n\\ingroup sai_configure_control\n\\brief Defines clock polarity.\n\\details\n@{\n\\def ARM_SAI_CLOCK_POLARITY_0\n\\def ARM_SAI_CLOCK_POLARITY_1\n@}\n\n\\defgroup sai_frame_control SAI Frame\n\\ingroup sai_configure_control\n\\brief Defines frame.\n\\details\n@{\n\\def ARM_SAI_FRAME_LENGTH(n)\n\\def ARM_SAI_FRAME_SYNC_WIDTH(n)\n\\def ARM_SAI_FRAME_SYNC_POLARITY_HIGH\n\\def ARM_SAI_FRAME_SYNC_POLARITY_LOW\n\\def ARM_SAI_FRAME_SYNC_EARLY\n@}\n\n\\defgroup sai_slot_control SAI Slot\n\\ingroup sai_configure_control\n\\brief Defines data slots.\n\\details\n@{\n\\def ARM_SAI_SLOT_COUNT(n)\n\\def ARM_SAI_SLOT_SIZE_DEFAULT\n\\def ARM_SAI_SLOT_SIZE_16\n\\def ARM_SAI_SLOT_SIZE_32\n\\def ARM_SAI_SLOT_OFFSET(n)\n@}\n\n\\defgroup sai_mclk_pin_control SAI Master Clock Pin\n\\ingroup sai_configure_control\n\\brief Defines MCLK pin.\n\\details\n@{\n\\def ARM_SAI_MCLK_PIN_INACTIVE\n\\def ARM_SAI_MCLK_PIN_OUTPUT\n\\def ARM_SAI_MCLK_PIN_INPUT\n@}\n\n\\defgroup sai_mclk_pres_control SAI Master Clock Prescaler\n\\ingroup sai_configure_control\n\\brief Defines MCLK prescaler.\n\\details\n@{\n\\def ARM_SAI_MCLK_PRESCALER(n)\n@}\n\n@}\n*/\n\n\n/**\n\\defgroup sai_controls SAI Controls\n\\ingroup sai_control\n\\brief Specifies controls.\n\\details\n@{\n\\def ARM_SAI_CONFIGURE_TX\n\\sa ARM_SAI_Control\n\\def ARM_SAI_CONFIGURE_RX\n\\sa ARM_SAI_Control\n\\def ARM_SAI_CONTROL_TX\n\\sa ARM_SAI_Control; ARM_SAI_Send\n\\def ARM_SAI_CONTROL_RX\n\\sa ARM_SAI_Control; ARM_SAI_Receive\n\\def ARM_SAI_MASK_SLOTS_TX\n\\sa ARM_SAI_Control; ARM_SAI_Send\n\\def ARM_SAI_MASK_SLOTS_RX\n\\sa ARM_SAI_Control; ARM_SAI_Receive\n\\def ARM_SAI_ABORT_SEND\n\\sa ARM_SAI_Control; ARM_SAI_Send\n\\def ARM_SAI_ABORT_RECEIVE\n\\sa ARM_SAI_Control; ARM_SAI_Receive\n@}\n*/\n\n\n/**\n@}\n*/\n// end group SAI_control\n\n\n//\n// Function documentation\n//\n\nARM_DRIVER_VERSION ARM_SAI_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)\n\\details\nThe function \\b ARM_SAI_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_SAI Driver_SAI0;\nARM_DRIVER_SAI *drv_info;\n \nvoid setup_sai (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_SAI0;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)  {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*****************************************************************************************************************/\n\nARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)  {\n  return {0};\n}\n/**\n\\details\n\\fn ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)\nThe function \\b  ARM_SAI_GetCapabilities retrieves information about the capabilities in this driver implementation.\nThe data fields of the struct \\ref ARM_SAI_CAPABILITIES encode various capabilities, for example\nsupported protocols, or if a hardware is capable to create signal events using the \\ref ARM_SAI_SignalEvent \ncallback function.\n \n\\b Example:\n\\code\nextern ARM_DRIVER_SAI Driver_SAI0;\nARM_DRIVER_SAI *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_SAI_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_SAI0;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*****************************************************************************************************************/\n\nint32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)\n\\details\nThe function \\b ARM_SAI_Initialize initializes the SAI interface. It is called when the middleware component starts\noperation.\n\nThe function performs the following operations:\n  - Initializes the required resources of the SAI interface.\n  - Registers the \\ref ARM_SAI_SignalEvent callback function.\n\nThe parameter \\em cb_event is a pointer to the \\ref ARM_SAI_SignalEvent callback function; use a NULL pointer \nwhen no callback signals are required.\n*****************************************************************************************************************/\n\nint32_t ARM_SAI_Uninitialize (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SAI_Uninitialize (void)\n\\details\nThe function \\b ARM_SAI_Uninitialize de-initializes the resources of SAI interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n*****************************************************************************************************************/\n  \nint32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_SAI_PowerControl allows you to control the power modes of the SAI interface.  \n\nThe parameter \\em state sets the operation and can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. \n                          Can be called multiple times. If the peripheral is already in this mode the function performs \n\t\t\t\t\t\t  no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n*****************************************************************************************************************/\n\nint32_t ARM_SAI_Send (const void *data, uint32_t num)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SAI_Send (const void *data, uint32_t num) \n\\details\nThe function \\b ARM_SAI_Send sends data to the SAI transmitter.\n\nThe function parameters specify the buffer with \\a data and the number \\a num of items to send.\nThe item size is defined by the data type which depends on the configured number of data bits.\n\nData type is:\n - \\em uint8_t when configured for \\token{8} data bits\n - \\em uint16_t when configured for \\token{9..16} data bits\n - \\em uint32_t when configured for \\token{17..32} data bits\n\nTransmitter is enabled by calling \\ref ARM_SAI_Control with \\ref ARM_SAI_CONTROL_TX as the control parameter and \\token{1} as\nan argument. This starts the transmit engine which, generates a clock and frame sync signal in master mode and transmits the\ndata. In slave mode, clock and frame sync are generated by the external master. When mute is active, data is discarded and\nzero values are transmitted. \n \nCalling the function <b>ARM_SAI_Send</b> only starts the send operation. The function is non-blocking and returns as soon as\nthe driver has started the operation (the driver typically configures DMA or the interrupt system for continuous transfer).\nDuring the operation it is not allowed to call this function again. Also, the data buffer must stay allocated and the\ncontents of unsent data must not be modified. When the send operation is completed (requested number of items have been\nsent), the event \\ref ARM_SAI_EVENT_SEND_COMPLETE is generated. Progress of the send operation can be monitored by reading\nthe number of already sent items by calling the function \\ref ARM_SAI_GetTxCount. \n\nThe status of the transmitter can also be monitored by calling the function \\ref ARM_SAI_GetStatus and checking the \\em tx_busy flag,\nwhich indicates if a transmission is still in progress.\n\nIf the transmitter is enabled and data is to be sent but the send operation has not been started yet, then the event\n\\ref ARM_SAI_EVENT_TX_UNDERFLOW is generated.\n\nIf an invalid synchronization frame is detected in slave mode, then the event \\ref ARM_SAI_EVENT_FRAME_ERROR is generated (if\nsupported and reported by \\em event_frame_error in \\ref ARM_SAI_CAPABILITIES). \n\nThe send operation can be aborted by calling the function \\ref ARM_SAI_Control with the control parameter \\ref ARM_SAI_ABORT_SEND.\n*****************************************************************************************************************/\n\nint32_t ARM_SAI_Receive (void *data, uint32_t num)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SAI_Receive (void *data, uint32_t num)\n\\details\nThe function \\b ARM_SAI_Receive is used to receive data from the SAI receiver. The function parameters specify the buffer for\n\\a data and the number \\a num of items to receive. The item size is defined by the data type, which depends on the configured\nnumber of data bits.\n\nData type is:\n - \\em uint8_t when configured for \\token{8} data bits\n - \\em uint16_t when configured for \\token{9..16} data bits\n - \\em uint32_t when configured for \\token{17..32} data bits\n\nThe receiver is enabled by calling the function \\ref ARM_SAI_Control with the control parameter \\ref ARM_SAI_CONTROL_RX and the value \\token{1}\nfor the parameter \\em arg1. This starts the receive engine, which generates a clock and frame sync signal in master mode and receives\ndata. In slave mode, clock and frame sync are generated by the external master. \n \nCalling the function <b>ARM_SAI_Receive</b> only starts the receive operation. The function is non-blocking and returns as\nsoon as the driver has started the operation (the driver typically configures DMA or the interrupt system for continuous\ntransfer). During the operation, it is not allowed to call this function again. The data buffer must also stay allocated.\nWhen receive operation is completed (the requested number of items have been received), the\n\\ref ARM_SAI_EVENT_RECEIVE_COMPLETE event is generated. Progress of the receive operation can also be monitored by reading\nthe number of items already received by calling the function \\ref ARM_SAI_GetRxCount. \n\nThe status of the receiver can also be monitored by calling the function \\ref ARM_SAI_GetStatus and checking the \\em rx_busy flag, which\nindicates whether a reception is still in progress. \n\nWhen the receiver is enabled and data is received but the receive operation has not been started yet, then the event\n\\ref ARM_SAI_EVENT_RX_OVERFLOW is generated.\n\nIf an invalid synchronization frame is detected in slave mode, then the event \\ref ARM_SAI_EVENT_FRAME_ERROR is generated (if\nsupported and reported by \\em event_frame_error in \\ref ARM_SAI_CAPABILITIES). \n\nThe receive operation can be aborted by calling the function \\ref ARM_SAI_Control with the control parameter \\ref ARM_SAI_ABORT_RECEIVE.\n*****************************************************************************************************************/\n\nuint32_t ARM_SAI_GetTxCount (void)  {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_SAI_GetTxCount (void)\n\\details\nThe function \\b ARM_SAI_GetTxCount returns the number of the currently transmitted data items during an \\ref ARM_SAI_Send\noperation.\n*****************************************************************************************************************/\n\nuint32_t ARM_SAI_GetRxCount (void)  {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_SAI_GetRxCount (void)\n\\details\nThe function \\b ARM_SAI_GetRxCount returns the number of the currently received data items during an \\ref ARM_SAI_Receive\noperation.\n*****************************************************************************************************************/\n\nint32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)  {\n  return ARM_DRIVER_OK;\n}\n\n/**\n\\fn int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)\n\\details\nThe function \\b ARM_SAI_Control controls the SAI interface and executes various operations.\n\nThe parameter \\em control specifies the operation. Values are listed in the table <a href=\"#sai_contrl_tab\"><b>Parameter <i>control</i></b></a>.\\n\nThe parameter \\em arg1 provides,  depending on the operation,  additional information or sets values. \nRefer to table <a href=\"#sai_arg1_tab\"><b>Parameter <i>arg1</i></b></a>. \\n\nThe parameter \\em arg2 provides,  depending on the operation and/or \\em arg1,  additional information or sets values. \n\nThe driver provides a receiver/transmitter pair of signals. \nIn asynchronous operation mode, they operate completely independent from each other. \nIn synchronous operation mode, the synchronous channel uses the Clock (SCK) and Frame Sync (WS) signal from the asynchronous one\n(control category <a href=\"#sai_sync\"><b>Synchronization</b></a>).\n\nThe clock polarity can be set for every protocol, regardless whether it is already predefined for I2S, MSB/LSB Jusitified\n(control category <a href=\"#sai_clk_polarity\"><b>Clock Polarity</b></a>).\n\nA master clock provides a faster clock from which the frame can be derived (usually 256 x faster than the normal frame clock). \nYou can use a master clock only in master mode. A slave will always have only one clock \n(control category <a href=\"#master_clock\"><b>Master Clock pin (MCLK)</b></a>).\n\n\\anchor sai_contrl_tab\t\t\nThe table lists the operation values for \\em control. Values from different categories can be ORed.\n<table class=\"cmtable\" summary=\"\">\n<tr><th> Parameter \\em control              </th><th>                                       Bit </th><th>             Category      </th>\n    <th> Description                        </th></tr>\n<tr><td> \\ref ARM_SAI_CONFIGURE_TX          </td><td rowspan=\"8\" style=\"text-align:right\"> 0..7 </td><td rowspan=\"8\"> Operation    </td>\n    <td> Configure transmitter. \\em arg1 (see  <a href=\"#sai_arg1_tab\"><b>Parameter <i>arg1</i></b></a>) and \\em arg2 provide additional configuration.  </td></tr>\n<tr><td> \\ref ARM_SAI_CONFIGURE_RX          </td>\n    <td> Configure receiver. \\em arg1 (see  <a href=\"#sai_arg1_tab\"><b>Parameter <i>arg1</i></b></a>) and \\em arg2 provide additional configuration.  </td></tr>\n<tr><td> \\ref ARM_SAI_CONTROL_TX                </td>\n    <td> Enable or disable transmitter and control mute; \n\t\\em arg1.0 : \\token{0=disable (default); 1=enable;} \\em arg1.1 : \\token{mute} (see \\ref ARM_SAI_Send) </td></tr>\n<tr><td> \\ref ARM_SAI_CONTROL_RX            </td>\n    <td> Enable or disable receiver; \\em arg1.0 : \\token{0=disable (default); 1=enable} (see \\ref ARM_SAI_Receive)  </td></tr>\n<tr><td> \\ref ARM_SAI_MASK_SLOTS_TX         </td>\n    <td> Mask transmitter slots; \\em arg1 = \\token{mask} (bit: 0=active, 1=inactive); all configured slots are active by default.  </td></tr>\n<tr><td> \\ref ARM_SAI_MASK_SLOTS_RX         </td>\n    <td> Mask receiver slots; \\em arg1 = \\token{mask} (bit: 0=active, 1=inactive); all configured slots are active by default.  </td></tr>\n<tr><td> \\ref ARM_SAI_ABORT_SEND            </td>\n    <td> Abort send operation (see \\ref ARM_SAI_Send).  </td></tr>\n<tr><td> \\ref ARM_SAI_ABORT_RECEIVE         </td>\n    <td> Abort receive operation (see \\ref ARM_SAI_Receive).  </td></tr>\n<tr><td> \\ref ARM_SAI_MODE_MASTER           </td><td rowspan=\"2\" style=\"text-align:right\"> 8    </td><td rowspan=\"2\"> Mode             </td>\n    <td> Master mode. \\em arg2 specifies the audio frequency in [Hz].  You can also set the <a href=\"#master_clock\"><b>Master Clock pin</b></a>.</td></tr>\n<tr><td> \\ref ARM_SAI_MODE_SLAVE (default)  </td>\n    <td> Slave mode.  </td></tr>\n<tr><td> \\ref ARM_SAI_ASYNCHRONOUS (default)    \\anchor sai_sync </td><td rowspan=\"2\" style=\"text-align:right\">  9  </td><td rowspan=\"2\"> Synchronization </td>\n    <td> Asynchronous operation using own clock and sync signal.  </td></tr>\n<tr><td> \\ref ARM_SAI_SYNCHRONOUS               </td> \n    <td> Synchronous operation using clock and sync signal from other transmitter/receiver.  </td></tr>\n<tr><td> \\ref ARM_SAI_PROTOCOL_USER  (default)  </td><td rowspan=\"7\" style=\"text-align:right\"> 10..12 </td><td rowspan=\"7\"> Protocol     </td>\n    <td> User defined                           </td></tr>\n<tr><td> \\ref ARM_SAI_PROTOCOL_I2S              </td>\n    <td> I2C                                    </td></tr>\n<tr><td> \\ref ARM_SAI_PROTOCOL_MSB_JUSTIFIED    </td> \n    <td> MSB (left) justified                   </td></tr>\n<tr><td> \\ref ARM_SAI_PROTOCOL_LSB_JUSTIFIED    </td> \n    <td> LSB (right) justified                  </td></tr>\n<tr><td> \\ref ARM_SAI_PROTOCOL_PCM_SHORT        </td> \n    <td> PCM with short frame                   </td></tr>\n<tr><td> \\ref ARM_SAI_PROTOCOL_PCM_LONG         </td> \n    <td> PCM with long frame                    </td></tr>\n<tr><td> \\ref ARM_SAI_PROTOCOL_AC97             </td> \n    <td> AC'97                                  </td></tr>\n<tr><td> \\ref ARM_SAI_DATA_SIZE(n)              </td><td style=\"text-align:right\"> 13..17 </td><td> Data Size    </td>     \n    <td> Data size in bits; the range for \\em n is \\token{8..32}. See also: <a href=\"#frame_slot_size\"><b>Frame Slot Size</b></a>.    </td></tr>\n<tr><td> \\ref ARM_SAI_MSB_FIRST                 </td><td rowspan=\"2\" style=\"text-align:right\"> 18     </td><td rowspan=\"2\"> Bit Order    </td>     \n    <td> Data is transferred with MSB first.    </td></tr>\n<tr><td> \\ref ARM_SAI_LSB_FIRST                 </td>\n    <td> Data is transferred with LSB first (User protocol only, ignored otherwise).     </td></tr>\n<tr><td> \\ref ARM_SAI_MONO_MODE                 </td><td style=\"text-align:right\"> 19     </td><td> Mono Mode</td>      \n    <td> Only for I2S, MSB/LSB justified. \n\t     When using \\ref Driver_SAI_I2S in mono mode, only data for a single channel is sent to and received from the driver.\n         Hardware will duplicate the data for the second channel on transmit and ignore the second channel on receive.    </td></tr>\n<tr><td> \\ref ARM_SAI_COMPANDING_NONE (default) </td><td rowspan=\"3\" style=\"text-align:right\"> 20..22 </td><td rowspan=\"3\"> Companding    </td>\n    <td> No companding  </td></tr>\n<tr><td> \\ref ARM_SAI_COMPANDING_A_LAW          </td>   \n    <td> A-Law companding (8-bit data)          </td></tr>\n<tr><td> \\ref ARM_SAI_COMPANDING_U_LAW          </td>   \n    <td> u-Law companding (8-bit data)          </td></tr>\n<tr><td> \\ref ARM_SAI_CLOCK_POLARITY_0&nbsp;(default)  \\anchor sai_clk_polarity > </td><td rowspan=\"2\" style=\"text-align:right\">    23   </td><td rowspan=\"2\"> Clock Polarity </td>\n    <td> Drive on falling edge, capture on rising  edge. </td></tr>\n<tr><td> \\ref ARM_SAI_CLOCK_POLARITY_1         \\anchor master_clock </td>\n    <td> Drive on rising  edge, capture on falling edge. </td></tr>\n<tr><td> \\ref ARM_SAI_MCLK_PIN_INACTIVE&nbsp;(default)  </td><td rowspan=\"3\" style=\"text-align:right\"> 24..26 </td><td rowspan=\"3\"> Master Clock pin (MCLK) </td>\n    <td> MCLK not used.                         </td></tr>\n<tr><td> \\ref ARM_SAI_MCLK_PIN_OUTPUT           </td>   \n    <td> MCLK is output (Master mode only).     </td></tr>\n<tr><td> \\ref ARM_SAI_MCLK_PIN_INPUT            </td>   \n    <td> MCLK is input (Master mode only).      </td></tr>\n</table>\n\n\\anchor sai_arg1_tab\nThe parameter \\em arg1 provides frame-specific values depending on the \\em control operation. Values from different categories can be ORed.\n<table class=\"cmtable\" summary=\"\">\n<tr><th nowrap> Parameter \\em arg1       </th>\n    <th style=\"text-align:right\">   Bit  </th>\n\t<th> Category                        </th>\n    <th> Description                     </th></tr>\n<tr><td> \\ref ARM_SAI_FRAME_LENGTH(n)    </td>\n    <td style=\"text-align:right\">  0..9  </td>\n\t<td> Frame Length                    </td>\n    <td> Frame length in bits; the possible range for \\em n is \\token{8..1024}; default depends on protocol and data.    </td></tr>\n<tr><td> \\ref ARM_SAI_FRAME_SYNC_WIDTH(n)</td>\n    <td style=\"text-align:right\"> 10..17 </td>\n\t<td> Frame Sync Width                </td>\n    <td> Frame Sync width in bits; the possible range for \\em n is \\token{1..256}; \\token{default=1}; User protocol only, ignored otherwise.  </td></tr>\n<tr><td> \\ref ARM_SAI_FRAME_SYNC_POLARITY_HIGH   </td>\n    <td rowspan=\"2\" style=\"text-align:right\"> 18 </td>\n\t<td rowspan=\"2\" style=\"white-spaces:nowrap\"> Frame Sync Polarity  </td>\n    <td> Frame Sync is active high (default).    </td></tr>\n<tr><td> \\ref ARM_SAI_FRAME_SYNC_POLARITY_LOW    </td>\n    <td> Frame Sync is active low (User protocol only, ignored otherwise).   </td></tr>\n<tr><td> \\ref ARM_SAI_FRAME_SYNC_EARLY           </td>\n    <td style=\"text-align:right\">  19  </td>\n\t<td> Frame Sync Early              </td>\n    <td> Frame Sync one bit before the first bit of the frame (User protocol only, ignored otherwise).                   </td></tr>\n<tr><td> \\ref ARM_SAI_SLOT_COUNT(n)              </td>\n    <td style=\"text-align:right\"> 20..24         </td>\n\t<td> Frame Sync Count                        </td>\n    <td> Number of slots in frame; the possible range for \\em n is \\token{1..32}; default=\\token{1};  User protocol only, ignored otherwise.  </td></tr>\n<tr><td> \\ref ARM_SAI_SLOT_SIZE_DEFAULT   \\anchor frame_slot_size  </td>\n    <td rowspan=\"3\" style=\"text-align:right\"> 25..26                </td>\n\t<td rowspan=\"3\">  Frame Slot Size                               </td>\n    <td> Slot size is equal to data size (default).                 </td></tr>\n<tr><td> \\ref ARM_SAI_SLOT_SIZE_16                                  </td>\n    <td> Slot size is \\token{16 bits} (User protocol only, ignored otherwise).     </td></tr>\n<tr><td> \\ref ARM_SAI_SLOT_SIZE_32                                  </td>\n    <td> Slot size is \\token{32 bits} (User protocol only, ignored otherwise).     </td></tr>\n<tr><td> \\ref ARM_SAI_SLOT_OFFSET(n)     </td>\n    <td style=\"text-align:right\"> 27..31 </td>\n\t<td> Frame Slot Offset               </td>\n    <td> Offset of first data bit in slot; The range for \\em n is \\token{0..31}; default=\\token{0};  User protocol only, ignored otherwise.   </td></tr>\n</table>\n\n\n\\anchor mckl_prescaler\nDepending on the \\em control operation, the parameter \\em arg2 specifies the Master Clock (MCLK) prescaler and calculates the audio frequency automatically.\n\nParameter \\em arg2                       | MCLK Prescaler\n:----------------------------------------|:--------------------------------------------\n\\ref ARM_SAI_MCLK_PRESCALER(n)           | MCLK prescaler; Audio frequency = MCLK/n; the range for \\em n is \\token{1..4096}; default=\\token{1}.\n\n\n\\b Example\n\n\\code\nextern ARM_DRIVER_SAI Driver_SAI0;\n \n// configure Transmitter to Asynchronous Master: I2S Protocol, 16-bit data, 16kHz Audio frequency\nstatus = Driver_SAI0.Control(ARM_SAI_CONFIGURE_TX | \n                             ARM_SAI_MODE_MASTER  | \n                             ARM_SAI_ASYNCHRONOUS | \n                             ARM_SAI_PROTOCOL_I2S | \n                             ARM_SAI_DATA_SIZE(16), 0, 16000);\n \n// configure Receiver to Asynchronous Master: I2S Protocol, 16-bit data, 16kHz Audio frequency\nstatus = Driver_SAI0.Control(ARM_SAI_CONFIGURE_RX | \n                             ARM_SAI_MODE_MASTER  | \n                             ARM_SAI_ASYNCHRONOUS | \n                             ARM_SAI_PROTOCOL_I2S | \n                             ARM_SAI_DATA_SIZE(16), 0, 16000);\n \n// enable Transmitter\nstatus = Driver_SAI0.Control(ARM_SAI_CONTROL_TX, 1, 0);\n \n// enable Receiver\nstatus = Driver_SAI0.Control(ARM_SAI_CONTROL_RX, 1, 0);\n\\endcode\n\n*****************************************************************************************************************/\n\nARM_SAI_STATUS ARM_SAI_GetStatus (void)  {\n  return { 0 };\n}\n/**\n\\fn ARM_SAI_STATUS ARM_SAI_GetStatus (void)\n\\details\nThe function \\b ARM_SAI_GetStatus retrieves the current SAI interface status.\n*****************************************************************************************************************/\n\nvoid ARM_SAI_SignalEvent (uint32_t event)  {\n  // function body\n}\n/**\n\\fn void ARM_SAI_SignalEvent (uint32_t event)\n\\details\nThe function \\b ARM_SAI_SignalEvent is a callback function registered by the function \\ref ARM_SAI_Initialize. \n\nThe parameter \\em event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nThe following events can be generated:\n\nParameter \\em event                        | Bit | Description \n------------------------------------------ |:---:|:-----------\n\\ref ARM_SAI_EVENT_SEND_COMPLETE           |  0  | Occurs after call to \\ref ARM_SAI_Send to indicate that all the data has been sent (or queued in transmit buffers). The driver is ready for the next call to \\ref ARM_SAI_Send.\n\\ref ARM_SAI_EVENT_RECEIVE_COMPLETE        |  1  | Occurs after call to \\ref ARM_SAI_Receive to indicate that all the data has been received. The driver is ready for the next call to \\ref ARM_SAI_Receive.\n\\ref ARM_SAI_EVENT_TX_UNDERFLOW            |  2  | Occurs when data is to be sent but send operation has not been started. Data field \\em tx_underflow = \\token{1} of \\ref ARM_SAI_STATUS.\n\\ref ARM_SAI_EVENT_RX_OVERFLOW             |  3  | Occurs when data is received but receive operation has not been started. Data field \\em rx_underflow = \\token{1} of \\ref ARM_SAI_STATUS.\n\\ref ARM_SAI_EVENT_FRAME_ERROR             |  4  | Occurs in slave mode when invalid synchronization frame is detected. Data field \\em  event_frame_error = \\token{1} of \\ref ARM_SAI_STATUS.\n  \n*****************************************************************************************************************/\n\n/**\n@}\n*/ \n// End SAI Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_SPI.c",
    "content": "/**\n\\defgroup spi_interface_gr SPI Interface\n\\brief Driver API for SPI Bus Peripheral (%Driver_SPI.h)\n\\details \nThe <b>Serial Peripheral Interface Bus</b> (SPI) implements a synchronous serial bus for data exchange. In microcontroller (MCU) applications,\nthe interface is often used to connect peripheral components at board (PCB) level. SPI devices can operate as Master (SCLK and SS are outputs) or \nSlave (SCLK and SS are inputs). Wikipedia offers more information about \nthe <a href=\"http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus\" target=\"_blank\"><b>Serial Peripheral Interface Bus</b></a>.\n\n<b>Block Diagram</b>\n\nThe SPI Driver API defines a <b>SPI</b> interface for middleware components. The SPI Driver supports multiple\nslaves, but if only one slave is connected, then the Slave Select signal can be omitted.\n\n\n\\image html SPI_Master1Slaves.png  \"SPI Master connected to a single slave\"\n\n\n<p>&nbsp;</p>\n\\image html SPI_Master3Slaves.png  \"SPI Master connected to 3 slaves\"\n\nThe SPI Driver functions control the following SPI signal lines. \n\nSignal | Name                                | Description\n-------|-------------------------------------|------------------------------------------------------------------------------\nSS     | Slave Select (active low)           | Selects the slave. This signal can be part of the SPI peripheral or implemented using a GPIO pin.\nMOSI   | Master&nbsp;Out,&nbsp;Slave&nbsp;In | MOSI output of the Master connects to MOSI input of the Slave.\nSCLK   | Serial Clock                        | Serial clock output from Master. Controls the transfer speed and when data are sent and read.\nMISO   | Master&nbsp;In,&nbsp;Slave&nbsp;Out | MISO input of the Master connects to MISO output of the Slave.\n\n\n<b>SPI API</b>\n\nThe following header files define the Application Programming Interface (API) for the SPI interface:\n  - \\b %Driver_SPI.h : Driver API for SPI Bus Peripheral\n\nThe driver implementation is a typical part of the Device Family Pack (DFP) that supports the \nperipherals of the microcontroller family.\n\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_SPI : access struct for SPI driver functions\n\n  \n<b>Example Code</b>\n\nThe following example code shows the usage of the SPI interface.\n\n\\include SPI_Demo.c\n  \n@{\n*/\n\n\n/**\n\\struct     ARM_DRIVER_SPI \n\\details \nThe functions of the SPI driver are accessed by function pointers exposed by this structure.\nRefer to \\ref DriverFunctions for overview information.\n\nEach instance of a SPI interface provides such an access structure. \nThe instance is identified by a postfix number in the symbol name of the access structure, for example:\n - \\b Driver_SPI0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_SPI1 is the name of the access struct of the second instance (no. 1).\n\nA middleware configuration setting allows connecting the middleware to a specific driver instance \\b %Driver_SPI<i>n</i>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n**************************************************************************************************************************/\n\n/** \n\\struct     ARM_SPI_CAPABILITIES\n\\details\nA SPI driver can be implemented with different capabilities.\nThe data fields of this structure encode the capabilities implemented by this driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_SPI_GetCapabilities\n**************************************************************************************************************************/\n\n/**\n\\struct     ARM_SPI_STATUS\n\\details\nStructure with information about the status of the SPI. The data fields encode busy flag and error flags.\n\n<b>Returned by:</b>\n  - \\ref ARM_SPI_GetStatus\n*****************************************************************************************************************/\n\n\n/**\n\\typedef    ARM_SPI_SignalEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_SPI_SignalEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_SPI_Initialize\n*******************************************************************************************************************/\n\n/**\n\\defgroup spi_execution_status Status Error Codes\n\\ingroup common_drv_gr\n\\brief Negative values indicate errors (SPI has specific codes in addition to common \\ref execution_status). \n\\details \nThe SPI driver has additional status error codes that are listed below.\nNote that the SPI driver also returns the common \\ref execution_status. \n  \n@{\n\\def ARM_SPI_ERROR_MODE\nThe \\b mode requested with the function \\ref ARM_SPI_Control is not supported by this driver.\n\n\\def ARM_SPI_ERROR_FRAME_FORMAT\nThe <b>frame format</b> requested with the function \\ref ARM_SPI_Control is not supported by this driver.\n\n\\def ARM_SPI_ERROR_DATA_BITS\nThe number of <b>data bits</b> requested with the function \\ref ARM_SPI_Control is not supported by this driver.\n\n\\def ARM_SPI_ERROR_BIT_ORDER\nThe <b>bit order</b> requested with the function \\ref ARM_SPI_Control is not supported by this driver.\n\n\\def ARM_SPI_ERROR_SS_MODE\nThe <b>slave select mode</b> requested with the function \\ref ARM_SPI_Control is not supported by this driver.\n@}\n*/\n\n/**\n\\defgroup SPI_events SPI Events\n\\ingroup spi_interface_gr\n\\brief The SPI driver generates call back events that are notified via the function \\ref ARM_SPI_SignalEvent.\n\\details \nThis section provides the event values for the \\ref ARM_SPI_SignalEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def  ARM_SPI_EVENT_TRANSFER_COMPLETE\n\\def  ARM_SPI_EVENT_DATA_LOST\n\\def  ARM_SPI_EVENT_MODE_FAULT\n@}\n*/\n\n//\n//  Functions\n//\n\nARM_DRIVER_VERSION ARM_SPI_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn       ARM_DRIVER_VERSION ARM_SPI_GetVersion (void)\n\\details\nThe function \\b ARM_SPI_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_SPI Driver_SPI0;\nARM_DRIVER_SPI *drv_info;\n \nvoid setup_spi (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_SPI0;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n**************************************************************************************************************************/\n\nARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)  {\n  return { 0 };\n}\n/**\n\\fn       ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)\n\\details\nThe function \\b ARM_SPI_GetCapabilities returns information about the capabilities in this driver implementation.\nThe data fields of the structure \\ref ARM_SPI_CAPABILITIES encode various capabilities, for example\nsupported modes.\n \nExample:\n\\code\nextern ARM_DRIVER_SPI Driver_SPI0;\nARM_DRIVER_SPI *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_SPI_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_SPI0;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n\n**************************************************************************************************************************/\n\nint32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)\n\\details\nThe function \\b ARM_SPI_Initialize initializes the SPI interface. \n\nThe parameter \\em cb_event is a pointer to the \\ref ARM_SPI_SignalEvent callback function; use a NULL pointer \nwhen no callback signals are required.\n\nThe function is called when the middleware component starts operation and performs the following:\n  - Initializes the resources needed for the SPI interface.\n  - Registers the \\ref ARM_SPI_SignalEvent callback function.\n\n\n\\b Example:\n - see \\ref spi_interface_gr - Driver Functions\n\n**************************************************************************************************************************/\n\nint32_t ARM_SPI_Uninitialize (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_SPI_Uninitialize (void)\n\\details\nThe function \\b ARM_SPI_Uninitialize de-initializes the resources of SPI interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n**************************************************************************************************************************/\n\nint32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_SPI_PowerControl controls the power modes of the SPI interface.  \n\nThe parameter \\em state sets the operation and can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. \n                          Can be called multiple times. If the peripheral is already in this mode the function performs \n                          no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n**************************************************************************************************************************/\n\nint32_t ARM_SPI_Send (const void *data, uint32_t num)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SPI_Send (const void *data, uint32_t num)\n\\details \nThis function \\b ARM_SPI_Send is used to send data to the SPI transmitter (received data is ignored).\n\nThe parameter \\em data specifies the data buffer. \\n\nThe parameter \\em num specifies the number of items to send. \\n\nThe item size is defined by the data type, which depends on the configured number of data bits.\n\nData type is:\n - \\em uint8_t when configured for 1..8 data bits\n - \\em uint16_t when configured for 9..16 data bits\n - \\em uint32_t when configured for 17..32 data bits\n \nCalling the function \\b ARM_SPI_Send only starts the send operation.\nWhen in slave mode, the operation is only registered and started when the master starts the transfer.\nThe function is non-blocking and returns as soon as the driver has started the operation \n(driver typically configures DMA or the interrupt system for continuous transfer).\nDuring the operation it is not allowed to call this function or any other data transfer function again. \nAlso the data buffer must stay allocated and the contents of unsent data must not be modified.\nWhen send operation is completed (requested number of items sent), the \\ref ARM_SPI_EVENT_TRANSFER_COMPLETE event is generated.\nProgress of send operation can also be monitored by reading the number of items already sent by calling \\ref ARM_SPI_GetDataCount. \n\nStatus of the transmitter can also be monitored by calling the \\ref ARM_SPI_GetStatus and checking the \\em busy data field,\nwhich indicates if transmission is still in progress or pending. \n\nWhen in master mode and configured to monitor slave select and the slave select gets deactivated during transfer,\nthen the SPI mode changes to inactive and the \\ref ARM_SPI_EVENT_MODE_FAULT event is generated (instead of \\ref ARM_SPI_EVENT_TRANSFER_COMPLETE).\n\nWhen in slave mode but send/receive/transfer operation is not started and data is sent/requested by the master, \nthen the \\ref ARM_SPI_EVENT_DATA_LOST event is generated. \n\nSend operation can be aborted by calling \\ref ARM_SPI_Control with \\ref ARM_SPI_ABORT_TRANSFER as the control parameter.\n**************************************************************************************************************************/\n\nint32_t ARM_SPI_Receive (void *data, uint32_t num)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SPI_Receive (void *data, uint32_t num)\n\\details \nThe function \\b ARM_SPI_Receive is used to receive data \n(transmits the default value as specified by \\ref ARM_SPI_Control with \\ref ARM_SPI_SET_DEFAULT_TX_VALUE as control parameter). \n\nThe parameter \\em data specifies the data buffer. \\n\nThe parameter \\em num specifies the number of items to receive. \\n\nThe item size is defined by the data type, which depends on the configured number of data bits.\n\nData type is:\n - \\em uint8_t when configured for 1..8 data bits\n - \\em uint16_t when configured for 9..16 data bits\n - \\em uint32_t when configured for 17..32 data bits\n \nCalling the function \\b ARM_SPI_Receive only starts the receive operation.\nThe function is non-blocking and returns as soon as the driver has started the operation \n(driver typically configures DMA or the interrupt system for continuous transfer).\nWhen in slave mode, the operation is only registered and started when the master starts the transfer.\nDuring the operation it is not allowed to call this function or any other data transfer function again. Also the data buffer must stay allocated.\nWhen receive operation is completed (requested number of items received), the \\ref ARM_SPI_EVENT_TRANSFER_COMPLETE event is generated.\nProgress of receive operation can also be monitored by reading the number of items already received by calling \\ref ARM_SPI_GetDataCount. \n\nStatus of the receiver can also be monitored by calling the \\ref ARM_SPI_GetStatus and checking the \\em busy data field,\nwhich indicates if reception is still in progress or pending. \n\nWhen in master mode and configured to monitor slave select and the slave select gets deactivated during transfer,\nthen the SPI mode changes to inactive and the \\ref ARM_SPI_EVENT_MODE_FAULT event is generated (instead of \\ref ARM_SPI_EVENT_TRANSFER_COMPLETE).\n\nWhen in slave mode but send/receive/transfer operation is not started and data is sent/requested by the master, \nthen the \\ref ARM_SPI_EVENT_DATA_LOST event is generated. \n\nReceive operation can be aborted by calling \\ref ARM_SPI_Control with \\ref ARM_SPI_ABORT_TRANSFER as the control parameter.\n**************************************************************************************************************************/\n\nint32_t ARM_SPI_Transfer (const void *data_out, void *data_in, uint32_t num)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SPI_Transfer (const void *data_out, void *data_in, uint32_t num)\n\\details \nThe function \\b ARM_SPI_Transfer transfers data via SPI. It synchronously sends data to the SPI transmitter and receives data from the SPI receiver. \n\nThe parameter \\em data_out is a pointer to the buffer with data to send. \\n\nThe parameter \\em data_in is a pointer to the buffer which receives data. \\n\nThe parameter \\em num specifies the number of items to transfer. \\n\nThe item size is defined by the data type which depends on the configured number of data bits.\n\nData type is:\n - \\em uint8_t when configured for 1..8 data bits\n - \\em uint16_t when configured for 9..16 data bits\n - \\em uint32_t when configured for 17..32 data bits\n \nCalling the function \\b ARM_SPI_Transfer only starts the transfer operation.\nThe function is non-blocking and returns as soon as the driver has started the operation \n(driver typically configures DMA or the interrupt system for continuous transfer).\nWhen in slave mode, the operation is only registered and started when the master starts the transfer.\nDuring the operation it is not allowed to call this function or any other data transfer function again. \nAlso the data buffers must stay allocated and the contents of unsent data must not be modified.\nWhen transfer operation is completed (requested number of items transferred), the \\ref ARM_SPI_EVENT_TRANSFER_COMPLETE event is generated.\nProgress of transfer operation can also be monitored by reading the number of items already transferred by calling \\ref ARM_SPI_GetDataCount. \n\nStatus of the transmitter and receiver can also be monitored by calling the \\ref ARM_SPI_GetStatus and checking the \\em busy flag. \n\nWhen in master mode and configured to monitor slave select and the slave select gets deactivated during transfer,\nthen the SPI mode changes to inactive and the \\ref ARM_SPI_EVENT_MODE_FAULT event is generated (instead of \\ref ARM_SPI_EVENT_TRANSFER_COMPLETE).\n\nWhen in slave mode but send/receive/transfer operation is not started and data is sent/requested by the master,\n then the \\ref ARM_SPI_EVENT_DATA_LOST event is generated. \n\nTransfer operation can also be aborted by calling \\ref ARM_SPI_Control with \\ref ARM_SPI_ABORT_TRANSFER as the control parameter.\n**************************************************************************************************************************/\n\nuint32_t ARM_SPI_GetDataCount (void)  {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_SPI_GetDataCount (void)\n\\details\nThe function \\b ARM_SPI_GetDataCount returns the number of currently transferred data items \nduring \\ref ARM_SPI_Send, \\ref ARM_SPI_Receive and \\ref ARM_SPI_Transfer operation.\n*****************************************************************************************************************/\n\nint32_t ARM_SPI_Control (uint32_t control, uint32_t arg)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_SPI_Control (uint32_t control, uint32_t arg)\n\\details\nThe function \\b ARM_SPI_Control controls the SPI interface settings and executes various operations.\n\nThe parameter \\em control is a bit mask that specifies various operations. \n  - Controls form different categories can be ORed. \n  - If one control is omitted, then the default value of that category is used.\n  - Miscellaneous controls cannot be combined.  \n\nThe parameter \\em arg provides (depending on the parameter \\em control) additional information, for example the Bus Speed.\n\n\n<table class=\"cmtable\" summary=\"\">\n<tr><th> Parameter \\em control    </th>\n    <th style=\"text-align:right\"> Bit          </th>\n    <th> Category      </th>\n    <th> Description          \n\t</th></tr>\n<tr><td> \\ref ARM_SPI_MODE_INACTIVE       </td>\n    <td rowspan=\"3\" style=\"text-align:right\"> 0..7   </td>\n    <td rowspan=\"3\"> \\anchor spi_mode_tab Mode Controls    </td>\n    <td> Set SPI to inactive. \n\t</td></tr>\n<tr><td> \\ref ARM_SPI_MODE_MASTER         </td>\n    <td> Set the SPI Master (Output on MOSI, and the Input on MISO); \\em arg = Bus Speed in \\token{bps} \n\t</td></tr>\n<tr><td> \\ref ARM_SPI_MODE_SLAVE          </td>\n    <td> Set the SPI Slave  (Output on MISO, and the Input on MOSI)                                     \n\t</td></tr>\n<tr><td> \\ref ARM_SPI_CPOL0_CPHA0  (default)  </td>\n    <td rowspan=\"6\" style=\"text-align:right\"> 8..11 </td>\n    <td rowspan=\"6\"> Clock Polarity <br> (Frame Format) </td><td> CPOL=\\token{0} and CPHA=\\token{0}: Clock Polarity 0, Clock Phase 0 </td>\n\t</tr>\n<tr><td> \\ref ARM_SPI_CPOL0_CPHA1             </td>\n    <td> CPOL=\\token{0} and CPHA=\\token{1}: Clock Polarity 0, Clock Phase 1                 \n    </td></tr>  \n<tr><td> \\ref ARM_SPI_CPOL1_CPHA0             </td>\n    <td> CPOL=\\token{1} and CPHA=\\token{0}: Clock Polarity 1, Clock Phase 0                 \n\t</td></tr> \n<tr><td> \\ref ARM_SPI_CPOL1_CPHA1             </td>\n    <td> CPOL=\\token{1} and CPHA=\\token{1}: Clock Polarity 1, Clock Phase 1                 \n\t</td></tr> \n<tr><td> \\ref ARM_SPI_TI_SSI                  </td>\n    <td> Specifies that the frame format corresponds to the Texas Instruments Frame Format  \n\t</td></tr> \n<tr><td> \\ref ARM_SPI_MICROWIRE               </td>\n    <td> Specifies that the frame format corresponds to the National Semiconductor Microwire Frame Format \n\t</td></tr> \n<tr><td> \\ref ARM_SPI_DATA_BITS(n)       </td>\n    <td style=\"text-align:right\"> 12..17 </td>\n\t<td> Data Bits </td>\n    <td> Set the number of bits per SPI frame; range for \\em n = \\token{1..32}. \n         This is the minimum required parameter. \n    </td></tr> \n<tr><td> \\ref ARM_SPI_MSB_LSB   (default) </td>\n    <td rowspan=\"2\" style=\"text-align:right\"> 18 </td>\n    <td rowspan=\"2\"> Bit Order </td>\n    <td> Set the bit order from MSB to LSB   \n\t</td></tr>\n<tr><td> \\ref ARM_SPI_LSB_MSB             </td>\n    <td> Set the bit order from LSB to MSB   \n\t</td></tr>\n<tr><td nowrap>\\ref ARM_SPI_SS_MASTER_UNUSED   (default) </td>\n    <td rowspan=\"6\" style=\"text-align:right\"> 19..21 </td>\n    <td rowspan=\"6\"> Slave Select \n\t                 <br>when Master \n\t                 <div style=\"min-height:200px\">&nbsp;</div>\n                     Must be used with the corresponding master or slave controls from category <a href=\"#spi_mode_tab\"><b>Mode Controls</b></a>. \n\t                 <div style=\"min-height:200px\">&nbsp;</div>\n\t\t\t\t\t Slave Select \n\t\t\t\t\t <br>when Slave\n\t</td>\n    <td>Set the Slave Select mode for the master to  <b>Not used</b>. Used with Mode Control ARM_SPI_MODE_MASTER.\n\t    Master does not drive or monitor the SS line. For example, when connecting to a single slave, \n\t\twhich has the SS line connected to a fixed low level.  \n\t</td></tr>\n<tr><td>\\ref ARM_SPI_SS_MASTER_SW</td>\n    <td>Set the Slave Select mode for the master to  <b>Software controlled</b>. Used with Mode Control ARM_SPI_MODE_MASTER.\n\t    The Slave Select line is configured as output and controlled via the Miscellaneous Control \\ref ARM_SPI_CONTROL_SS. \n\t\tBy default, the line it is not active (high), and is not affected by transfer-, send-, or receive functions.\n    </td></tr>\n<tr><td>\\ref ARM_SPI_SS_MASTER_HW_OUTPUT</td>\n    <td>Set the Slave Select mode for the master to <b>Hardware controlled Output</b>. Used with Mode Control ARM_SPI_MODE_MASTER.\n\t    The Slave Select line is configured as output and controlled by hardware. \n\t\tThe line gets activated or deactivated automatically by the hardware for transfers and is not controlled by the Miscellaneous Control \\ref ARM_SPI_CONTROL_SS.\n\t\tWhen exactly the line is activated or deactivated is hardware dependent. Typically, the hardware will activate the line before starting the transfer \n\t\tand deactivate it after the transfer completes. Some hardware will keep the line active as long as the SPI stays master. \n\t\t\\note Some devices require that the SS signal is strictly defined regarding transfers. Refer to the documentation of your device.\n    </td></tr>\n<tr>\n    <td>\\ref ARM_SPI_SS_MASTER_HW_INPUT</td>\n    <td>Set the Slave Select mode for the master to <b>Hardware monitored Input</b>. Used with Mode Control ARM_SPI_MODE_MASTER.\n\t    Used in multi-master configuration where a master does not drive the Slave Select when driving the bus, but rather monitors it. \n\t\tWhen another master activates this line, the active master backs off. This is called Mode Fault. Slave Select is configured as input \n\t\tand hardware only monitors the line. When the line is activated externally while we are master, \n\t\tit presents a Mode Fault (\\ref ARM_SPI_EVENT_MODE_FAULT) and the SPI switches to inactive mode.\n    </td></tr>\n<tr><td>\\ref ARM_SPI_SS_SLAVE_HW (default)</td>\n    <td>Set the Slave Select mode for the slave to <b>Hardware monitored</b>. Used with Mode Control ARM_SPI_MODE_SLAVE.\n\t    Hardware monitors the Slave Select line and accepts transfers only when the line is active. Transfers are ignored while the Slave Select line is inactive.\n    </td></tr>\n<tr><td>\\ref ARM_SPI_SS_SLAVE_SW</td>\n    <td>Set the Slave Select mode for the slave to <b>Software controlled</b>. Used with Mode Control ARM_SPI_MODE_SLAVE.\n\t    Used only when the Slave Select line is not used. For example, when a single master and slave are connected in the system \n\t\tthen the Slave Select line is not needed. Software controls if the slave is responding or not (by default it is not responding). \n\t\tSoftware enables or disables transfers by using the Miscellaneous Control \\ref ARM_SPI_CONTROL_SS.\n    </td></tr>\n<tr><td> \\ref ARM_SPI_SET_BUS_SPEED  </td>\n    <td rowspan=\"5\" style=\"text-align:right\"> 0..21 </td>\n    <td rowspan=\"5\"> Miscellaneous Controls <br>(cannot be ORed)</td>\n    <td>Set the bus speed; \\em arg= Bus Speed in \\token{bps}\n    </td></tr>\n<tr><td> \\ref ARM_SPI_GET_BUS_SPEED         </td>\n    <td> Get the bus speed; Return values >= \\token{0} represent the bus speed in \\token{bps}. Negative values are \\ref spi_execution_status.\n    </td></tr>\n<tr><td> \\ref ARM_SPI_SET_DEFAULT_TX_VALUE  </td>\n    <td> Set the default transmission value; the parameter \\em arg sets the value\n    </td></tr>\n<tr><td> \\ref ARM_SPI_CONTROL_SS            </td>\n    <td> Control the Slave Select signal (SS); the values for the parameter \\em arg are: \\token{ARM_SPI_SS_INACTIVE; ARM_SPI_SS_ACTIVE} \n\t</td></tr>\n<tr><td> \\ref ARM_SPI_ABORT_TRANSFER        </td>\n    <td> Abort the current data transfer    \n\t</td></tr>\n</table>\n\n\n\n\\b Example \n\n\\code\n  extern ARM_DRIVER_SPI Driver_SPI0;\n  \n  // configure: SPI master | clock polarity=1, clock phase=1 | bits per frame=16 | bus speed : 1000000 \n  status = Driver_SPI0.Control(ARM_SPI_MODE_MASTER   | \n                               ARM_SPI_CPOL1_CPHA1   | \n                               ARM_SPI_DATA_BITS(16), 1000000);\n\\endcode\n*****************************************************************************************************************/\n\nARM_SPI_STATUS ARM_SPI_GetStatus (void)  {\n  return { 0 };\n}\n/**\n\\fn ARM_SPI_STATUS ARM_SPI_GetStatus (void)\n\\details\nThe function \\b ARM_SPI_GetStatus returns the current SPI interface status.\n*****************************************************************************************************************/\n\nvoid ARM_SPI_SignalEvent (uint32_t event)  {\n  // function body\n}\n/**\n\\fn void ARM_SPI_SignalEvent (uint32_t event)\n\\details\nThe function \\b ARM_SPI_SignalEvent is a callback function registered by the function \\ref ARM_SPI_Initialize. \n\nThe parameter \\em event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nNot every event is necessarily generated by the driver. This depends on the implemented capabilities stored in the \ndata fields of the structure \\ref ARM_SPI_CAPABILITIES, which can be retrieved with the function \\ref ARM_SPI_GetCapabilities.\n\nThe following events can be generated:\n\n<table class=\"cmtable\" summary=\"\">\n<tr>\n  <th> Parameter \\em event                  </th><th> Bit </th><th> Description </th>                                              \n  <th> supported when ARM_SPI_CAPABILITIES </th>\n</tr>\n<tr>\n  <td> \\ref ARM_SPI_EVENT_TRANSFER_COMPLETE </td><td>  0  </td><td> Occurs after call to \\ref ARM_SPI_Send, \\ref ARM_SPI_Receive, \n                                                                    or \\ref ARM_SPI_Transfer \n                                                                    to indicate that all the data has been transferred. \n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tThe driver is ready for the next transfer operation. </td>     \n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> \\ref ARM_SPI_EVENT_DATA_LOST         </td><td>  1  </td><td> Occurs in slave mode when data is requested/sent by master \n                                                                    but send/receive/transfer operation has not been started and \n                                                                    indicates that data is lost. Occurs also in master mode when\n                                                                    driver cannot transfer data fast enough.             </td>     \n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> \\ref ARM_SPI_EVENT_MODE_FAULT        </td><td>  2  </td><td> Occurs in master mode when Slave Select is deactivated and \n                                                                    indicates Master Mode Fault.  \n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tThe driver is ready for the next transfer operation. </td>     \n  <td> data field \\em event_mode_fault = \\token{1} </td>\n</tr>\n</table>\n**************************************************************************************************************************/\n\n\n/**\n\\defgroup SPI_control SPI Control Codes\n\\ingroup spi_interface_gr\n\\brief Many parameters of the SPI driver are configured using the \\ref ARM_SPI_Control function.\n\\details \n@{\nThe various SPI control codes define:\n  \n  - \\ref spi_mode_ctrls               specifies SPI mode\n  - \\ref spi_frame_format_ctrls       defines the frame format\n  - \\ref spi_data_bits_ctrls          defines the number of data bits\n  - \\ref spi_bit_order_ctrls          defines the bit order\n  - \\ref spi_slave_select_mode_ctrls  specifies slave select mode\n  - \\ref spi_misc_ctrls               specifies additional miscellaneous controls\n\nRefer to the \\ref ARM_SPI_Control function for further details.\n*/\n\n/**\n\\defgroup spi_mode_ctrls SPI Mode Controls\n\\ingroup SPI_control\n\\brief Specifies SPI mode.\n\\details\n@{\n\\def ARM_SPI_MODE_INACTIVE\n\\sa ARM_SPI_Control\n\\def ARM_SPI_MODE_MASTER\n\\sa ARM_SPI_Control\n\\def ARM_SPI_MODE_SLAVE\n\\sa ARM_SPI_Control\n@}\n*/\n\n/**\n\\defgroup spi_frame_format_ctrls SPI Frame Format \n\\ingroup SPI_control\n\\brief Defines the frame format.\n\\details\n@{\n\\def ARM_SPI_CPOL0_CPHA0\n\\sa ARM_SPI_Control\n\\def ARM_SPI_CPOL0_CPHA1\n\\sa ARM_SPI_Control\n\\def ARM_SPI_CPOL1_CPHA0\n\\sa ARM_SPI_Control\n\\def ARM_SPI_CPOL1_CPHA1\n\\sa ARM_SPI_Control\n\\def ARM_SPI_TI_SSI\n\\sa ARM_SPI_Control\n\\def ARM_SPI_MICROWIRE\n\\sa ARM_SPI_Control\n@}\n*/\n\n/**\n\\defgroup spi_data_bits_ctrls SPI Data Bits\n\\ingroup SPI_control\n\\brief Defines the number of data bits.\n\\details\n@{\n\\def ARM_SPI_DATA_BITS(n)\n\\sa ARM_SPI_Control\n@}\n*/\n\n/**\n\\defgroup spi_bit_order_ctrls  SPI Bit Order\n\\ingroup SPI_control\n\\brief Defines the bit order.\n\\details\n@{\n\\def ARM_SPI_MSB_LSB\n\\sa ARM_SPI_Control\n\\def ARM_SPI_LSB_MSB\n\\sa ARM_SPI_Control\n@}\n*/\n\n/**\n\\defgroup spi_slave_select_mode_ctrls  SPI Slave Select Mode\n\\ingroup SPI_control\n\\brief Specifies SPI slave select mode.\n\\details\n\\b SPI \\b Slave \\b Select \\b Mode configures the behavior of the \\b Slave \\b Select \\b (SS) signal. The configuration is\nseparate for \\b Master (ARM_SPI_SS_MASTER_*) and for \\b Slave (\\ref ARM_SPI_SS_SLAVE_HW, \\ref ARM_SPI_SS_SLAVE_SW). The\nactive configuration depends on the current state (Master/Slave).\n\n@{\n\\def ARM_SPI_SS_MASTER_UNUSED\nAn SPI master does not drive or monitor the SS line. For example, when connecting to a single slave, the SS line can be connected\nto a fixed low level.\n\\sa ARM_SPI_Control\n\\def ARM_SPI_SS_MASTER_SW\nSS is configured as an output and controlled via \\ref ARM_SPI_Control (\\ref ARM_SPI_CONTROL_SS). By default, it is not active\n(high). It is activated (low) by \\ref ARM_SPI_Control (\\ref ARM_SPI_CONTROL_SS, \\ref ARM_SPI_SS_ACTIVE) and deactivated by\n\\ref ARM_SPI_Control (\\ref ARM_SPI_CONTROL_SS, \\ref ARM_SPI_SS_INACTIVE). It is not affected by transfer/send/receive\nfunctions.\n\\sa ARM_SPI_Control\n\\def ARM_SPI_SS_MASTER_HW_OUTPUT\nHere, SS is configured as an output. It will be automatically activated/deactivated for the transfers by hardware (not\ncontrolled by \\ref ARM_SPI_Control (\\ref ARM_SPI_CONTROL_SS)). The activation/deactivation of the line is completely hardware\ndependent. Typically, the hardware will activate it before starting a transfer and deactivate it after a transfer completes.\nSome hardware will keep the line active as long as the SPI stays master. Due to different hardware behavior, this mode is\ntypically not useful because certain devices require that the SS signal is strictly defined with regards to transfers.\n\\sa ARM_SPI_Control\n\\def ARM_SPI_SS_MASTER_HW_INPUT\nThis is normally used in a multi-master configuration, where a master does not drive the SS line when driving the bus but only\nmonitors it. When another master activates this line, the active master backs off. This is called \\b mode \\b fault. SS is\nconfigured as input and the hardware only monitors it. When it is externally deactivated while being the master, it presents\na mode fault and the SPI switches to \\b inactive mode.\n\\sa ARM_SPI_Control\n\\def ARM_SPI_SS_SLAVE_HW\nHardware monitors the SS line and accepts transfers only when SS line is activate. Transfers while SS is not active are\nignored.\n\\sa ARM_SPI_Control\n\\def ARM_SPI_SS_SLAVE_SW\nUsed only when SS line is not used. For example, when a single master and slave are connected in a system, the SS line is not\nneeded (reduces the number of lines and pins used). Slave responses are controlled by software (by default, it is not\nresponding). Software enables/disables transfers by calling \\ref ARM_SPI_Control (\\ref ARM_SPI_CONTROL_SS, \\ref ARM_SPI_SS_ACTIVE / \\ref ARM_SPI_SS_INACTIVE).\n\\sa ARM_SPI_Control\n@}\n*/\n\n/**\n\\defgroup spi_misc_ctrls  SPI Miscellaneous Controls\n\\ingroup SPI_control\n\\brief Specifies additional miscellaneous controls.\n\\details\n@{\n\\def ARM_SPI_SET_BUS_SPEED\n\\sa ARM_SPI_Control\n\\def ARM_SPI_GET_BUS_SPEED\n\\sa ARM_SPI_Control\n\\def ARM_SPI_SET_DEFAULT_TX_VALUE\n\\sa ARM_SPI_Control\n\\def ARM_SPI_CONTROL_SS\n\\sa ARM_SPI_Control\n\\def ARM_SPI_ABORT_TRANSFER\n\\sa ARM_SPI_Control\n@}\n*/\n\n/**\n@} \n*/\n// end group SPI_control \n\n/**\n@}\n*/ \n// End SPI Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_Storage.c",
    "content": "/**\n\\defgroup storage_interface_gr Storage Interface\n\\brief    Driver API for Storage Device Interface (%Driver_Storage.h)\n\\details\nThis is an abstraction for a storage controller. It offers an interface to\naccess an address space of storage locations, comprising APIs for\ninitialization, erase, access, program, and status-fetch operations. It also\noffers APIs to iterate over the available Storage Blocks (\\ref\nARM_STORAGE_BLOCK), allowing the discovery of block attributes such as\nwrite/erase granularities. Using the Storage abstraction, it becomes possible to\nwrite generic algorithms, such as block copy, to operate on any conforming\nstorage device.\n\n\\note The storage abstraction layer is not responsible for storage management.\nAlgorithms such as block-allocation, wear-leveling, erase-before-write and other\nstorage-management policies are the responsibility of modules external to the\nstorage abstraction layer. In essence, the storage interface is the lowest\nabstraction upon which block management policies can be implemented.\n\nHere's a picture to help locate the storage abstraction in the software stack.\nThe part below the box labeled 'Storage abstraction layer' is implemented by a\nstorage driver.\n\n\\image html storage_sw_stack.png\n\n<b>Storage API</b>\n\nThe following header files define the Application Programming Interface (API) for the Flash interface:\n  - \\b %Driver_Storage.h : Driver API for Storage Device Interface\n\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref StorageDriverFunctions\n  - \\ref ARM_DRIVER_STORAGE : access struct for Storage driver functions\n\nA sample use for the driver can be found at: \\ref SampleUseOfStorageDriver\n*******************************************************************************************************************/\n\n\n\n/**\n\\addtogroup storage_interface_gr\n@{\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_STORAGE_BLOCK_ATTRIBUTES\n<b>Contained in:</b>\n  - \\ref ARM_STORAGE_BLOCK\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_STORAGE_BLOCK\n\\details Storage blocks combine to make up the address map of a storage controller.\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_STORAGE_INFO\n\\details\nIt describes the characteristics of a Storage device. This includes total\nstorage, programming size, a default value for erased memory etc. This\ninformation can be obtained from the Storage device datasheet and is used by the\nmiddleware in order to properly interact with the Storage device.\n\nTotal available storage (in bytes) is contained in \\em total_storage. Minimum\nprogramming size (in bytes) is described by \\em program_unit (applicable only if\nthe \\em programmable attribute is set for a block). It defines the granularity\nfor programming data. The offset of the start of a program-range and the size\nshould also be aligned with \\em program_unit.\n\\note: setting \\em program_unit to 0 has the effect of disabling the size and\nalignment restrictions (setting it to 1 also has the same effect).\n\nOptimal programming page-size (in bytes) is specified by \\em\noptimal_program_unit. Some storage controllers have internal buffers into which\nto receive data. Writing in chunks of \\em optimal_program_unit would achieve\nmaximum programming speed. Like with \\em program_unit, this is applicable only\nif the \\em programmable attribute is set for the underlying storage block(s).\n\n\\em program_cycles is a measure of endurance for reprogramming.\nA value of \\em ARM_STORAGE_PROGRAM_CYCLES_INFINITE may be used to signify\ninfinite or unknown endurance.\n\nContents of erased memory is specified by the \\em erased_value. It is usually\n\\token{1} to indicate erased bytes with state 0xFF.\n\n\\em memory_mapped can be set to \\token{1} to indicate that the storage device\nhas a mapping onto the processor's memory address space.\n\\note: For a memory-mapped block which isn't erasable but is programmable,\nwrites should be possible directly to the memory-mapped storage without going\nthrough the \\ref ARM_Storage_ProgramData operation.\n\nThe field \\em programmability holds a value to indicate storage programmability.\nSimilarly, \\em retention_level holds a for encoding data-retention levels for\nall storage blocks.\n\n\\note\nThese fields serve a different purpose than the ones contained in\n\\ref ARM_STORAGE_CAPABILITIES, which is another structure containing device-level\nmetadata. ARM_STORAGE_CAPABILITIES describes the API capabilities, whereas\nARM_STORAGE_INFO describes the device. Furthermore ARM_STORAGE_CAPABILITIES fits\nwithin a single word, and is designed to be passed around by value;\nARM_STORAGE_INFO, on the other hand, contains metadata which doesn't fit into a\nsingle word and requires the use of pointers to be moved around.\n\n<b>Returned by:</b>\n  - \\ref ARM_Storage_GetInfo\n*******************************************************************************************************************/\n\n/**\n\\struct ARM_DRIVER_STORAGE\n\\details\nThis is the set of operations constituting the Storage driver. Their\nimplementation is platform-specific, and needs to be supplied by the porting\neffort. The functions of the Storage driver are accessed by function pointers\nexposed by this structure. Refer to \\ref StorageDriverFunctions for overview\ninformation.\n\nEach instance of a Storage interface provides such an access structure.\nThe instance is identified by a postfix number in the symbol name of the access structure, for example:\n - \\b Driver_Storage0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_Storage1 is the name of the access struct of the second instance (no. 1).\n\nA middleware configuration setting allows connecting the middleware to a specific driver instance \\b %Driver_Flash<i>n</i>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*******************************************************************************************************************/\n\n/**\n\\defgroup StorageDriverFunctions Use of Storage APIs\n\nFunction pointers within \\ref ARM_DRIVER_STORAGE form the set of operations\nconstituting the Storage driver. Their implementation is platform-specific, and\nneeds to be supplied by the porting effort.\n\nSome of these APIs will always operate synchronously:\n- \\ref ARM_Storage_GetVersion\n- \\ref ARM_Storage_GetCapabilities\n- \\ref ARM_Storage_GetStatus\n- \\ref ARM_Storage_GetInfo\n- \\ref ARM_Storage_ResolveAddress\n- \\ref ARM_Storage_GetNextBlock and\n- \\ref ARM_Storage_GetBlock.\n\nThis means that control returns to the caller with a relevant status code only after the completion of the operation (or\nthe discovery of a failure condition).\n\nThe remainder of the APIs:\n- \\ref ARM_Storage_Initialize\n- \\ref ARM_Storage_Uninitialize\n- \\ref ARM_Storage_PowerControl\n- \\ref ARM_Storage_ReadData\n- \\ref ARM_Storage_ProgramData\n- \\ref ARM_Storage_Erase and\n- \\ref ARM_Storage_EraseAll\n\ncan function asynchronously if the underlying controller supports it; that is if ARM_STORAGE_CAPABILITIES::asynchronous_ops\nis set. In the case of asynchronous operation, the invocation returns early (with ARM_DRIVER_OK) and results in a completion\ncallback later. If ARM_STORAGE_CAPABILITIES::asynchronous_ops is not set, then all such APIs execute synchronously, and\ncontrol returns to the caller with a status code only after the completion of the operation (or the discovery of a failure\ncondition).\n\nIf ARM_STORAGE_CAPABILITIES::asynchronous_ops is set, a storage driver may\nstill choose to execute asynchronous operations in a synchronous manner. If\nso, the driver returns a positive value to indicate successful synchronous\ncompletion (or an error code in case of failure) and no further invocation of\ncompletion callback should be expected. The expected return value for\nsynchronous completion of such asynchronous operations varies depending on\nthe operation. For operations involving data access, it often equals the\namount of data transferred or affected. For non data-transfer operations,\nsuch as EraseAll or Initialize, it is usually 1.\n\nHere's a code snippet to suggest how asynchronous APIs might be used by\ncallers to handle both synchronous and asynchronous execution by the\nunderlying storage driver:\n\\code\n    ASSERT(ARM_DRIVER_OK == 0); // this is a precondition; it doesn't need to be put in code\n    \n    int32_t returnValue = drv->asynchronousAPI(...);\n         \n    if (returnValue < ARM_DRIVER_OK) {\n        // handle error.\n        \n    } else if (returnValue == ARM_DRIVER_OK) {\n        ASSERT(drv->GetCapabilities().asynchronous_ops == 1);\n        // handle early return from asynchronous execution; remainder of the work is done in the callback handler.\n        \n    } else {\n        ASSERT(returnValue == EXPECTED_RETURN_VALUE_FOR_SYNCHRONOUS_COMPLETION);\n        // handle synchronous completion.\n    }\n\\endcode\n\nTHis example is mixing synchronous and asynchronous APIs: \\ref SampleUseOfStorageDriver\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_STORAGE_CAPABILITIES\n\\details\nA Storage driver can be implemented with different capabilities. The data fields\nof this struct encode the API capabilities implemented by this driver.\n\nThe element \\em asynchronous_ops indicates if APIs like initialize, read, erase,\nprogram, etc. can operate in asynchronous mode. Having this bit set to 1 means\nthat the driver is capable of launching asynchronous operations; command\ncompletion for asynchronous operations is signaled by the invocation of a\ncompletion callback. If set to 1, drivers may still complete asynchronous\noperations synchronously as necessary--in which case they return a positive\nerror code to indicate synchronous completion.  If \\em asynchronous_ops is not\nset, then all such APIs execute synchronously, and control returns to the caller\nwith a status code only after the completion of the operation (or the discovery\nof a failure condition).\n\nThe element \\em erase_all specifies that the \\ref ARM_Storage_EraseAll function\nis supported. Typically full chip erase is much faster than erasing the whole\ndevice using \\em ARM_Storage_Erase.\n\n<b>Returned by:</b>\n  - \\ref ARM_Storage_GetCapabilities\n\n\\note\nThis data structure is designed to fit within a single word so that it can be\nfetched cheaply using a call to driver->GetCapabilities().\n*******************************************************************************************************************/\n\n/**\n\\struct     ARM_STORAGE_STATUS\n\\details\nStructure with information about the status of the Storage device.\n\nThe flag \\em busy indicates that the driver is busy executing read/program/erase operation.\n\nThe flag \\em error flag is cleared on start of read/program/erase operation and is set at the end of the current operation in case of error.\n\n<b>Returned by:</b>\n  - \\ref ARM_Storage_GetStatus\n*****************************************************************************************************************/\n\n/**\n\\enum       ARM_STORAGE_OPERATION\n\\details\nCommand opcodes for the Storage interface. Completion callbacks use these codes\nto refer to completing commands. Refer to \\ref ARM_Storage_Callback_t.\n*****************************************************************************************************************/\n\n/**\n\\typedef    ARM_Storage_Callback_t\n\\details\nProvides the typedef for the callback function \\ref ARM_Storage_Callback_t.\n\n\\param [in] status\n              A code to indicate the status of the completed operation. For data\n              transfer operations, the status field is overloaded in case of\n              success to return the count of bytes successfully transferred; this\n              can be done safely because error codes are negative values.\n\n\\param [in] operation\n              The command op-code. This value isn't essential, but it is expected that\n              this information could be a quick and useful filter for the handler.\n\n<b>Parameter for:</b>\n  - \\ref ARM_Storage_Initialize\n*******************************************************************************************************************/\n\n\n//\n// Functions\n//\n\nARM_DRIVER_VERSION ARM_Storage_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn ARM_DRIVER_VERSION ARM_Storage_GetVersion (void)\n\\details\nThe function \\b ARM_Storage_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION.\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_STORAGE *drv_info;\n \nvoid read_version (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n\n\\note This API returns synchronously--it does not result in an invocation\n   of a completion callback.\n\n\\note The function GetVersion() can be called any time to obtain the\n   required information from the driver (even before initialization). It\n   always returns the same information.\n*******************************************************************************************************************/\n\nARM_STOR_CAPABILITIES ARM_Storage_GetCapabilities (void)  {\n  return { 0 };\n}\n/**\n\\fn ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void)\n\n\\details\nThe function \\b ARM_Storage_GetCapabilities returns information about\ncapabilities in this driver implementation. The data fields of the struct\nARM_STORAGE_CAPABILITIES encode various capabilities, for example if the device\nis able to execute operations asynchronously.\n\nExample:\n\\code\nextern ARM_DRIVER_STORAGE *drv_info;\n \nvoid read_capabilities (void)  {\n  ARM_STORAGE_CAPABILITIES drv_capabilities;\n \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n\n}\n\\endcode\n\n\\note This API returns synchronously--it does not result in an invocation\n   of a completion callback.\n\n\\note The function GetCapabilities() can be called any time to obtain the\n   required information from the driver (even before initialization). It\n   always returns the same information.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback)\n\\details\nThe function \\b ARM_Storage_Initialize is called when the middleware component starts\noperation. In addition to bringing the controller to a ready state,\nInitialize() receives a callback handler to be invoked upon completion of\nasynchronous operations.\n\nARM_Storage_Initialize() needs to be called explicitly before\npowering the peripheral using ARM_Storage_PowerControl(), and before initiating other\naccesses to the storage controller.\n\nThe function performs the following operations:\n - Initializes the resources needed for the Storage interface.\n - Registers the \\ref ARM_Storage_Callback_t callback function.\n\nTo start working with a peripheral the functions ARM_Storage_Initialize and ARM_Storage_PowerControl() need to be called in this order:\n\\code\n   drv->Initialize (...);              // Allocate I/O pins\n   drv->PowerControl (ARM_POWER_FULL); // Power up peripheral, setup IRQ/DMA\n\\endcode\n\n- ARM_Storage_Initialize() typically allocates the I/O resources (pins) for the\n peripheral. The function can be called multiple times; if the I/O resources\n are already initialized it performs no operation and just returns with\n ARM_DRIVER_OK.\n\n- ARM_Storage_PowerControl (ARM_POWER_FULL) sets the peripheral registers including\n interrupt (NVIC) and optionally DMA. The function can be called multiple\n times; if the registers are already set it performs no operation and just\n returns with ARM_DRIVER_OK.\n\nTo stop working with a peripheral the functions ARM_Storage_PowerControl() and ARM_Storage_Uninitialize() need to be called in this order:\n\\code\n   drv->PowerControl (ARM_POWER_OFF); // Terminate any pending transfers, reset IRQ/DMA, power off peripheral\n   drv->Uninitialize (...);           // Release I/O pins\n\\endcode\n\nThe functions ARM_Storage_PowerControl() and ARM_Storage_Uninitialize() always execute and can be used\nto put the peripheral into a Safe State, for example after any data\ntransmission errors. To restart the peripheral in an error condition,\nyou should first execute the Stop Sequence and then the Start Sequence.\n\n\\note This API may execute asynchronously if\n   ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous\n   execution is optional even if 'asynchronous_ops' is set.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_Uninitialize (void)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_Uninitialize (void)\n\\details\nIt is called when the middleware component stops operation, and wishes to\nrelease the software resources used by the interface.\n\n\\note This API may execute asynchronously if\n   ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous\n   execution is optional even if 'asynchronous_ops' is set.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_Storage_PowerControl operates the power modes of the Storage interface.\n\nTo start working with a peripheral the functions Initialize and PowerControl need to be called in this order:\n\\code\n   drv->Initialize (...);                 // Allocate I/O pins\n   drv->PowerControl (ARM_POWER_FULL);    // Power up peripheral, setup IRQ/DMA\n\\endcode\n\n- ARM_Storage_Initialize() typically allocates the I/O resources (pins) for the\n peripheral. The function can be called multiple times; if the I/O resources\n are already initialized it performs no operation and just returns with\n ARM_DRIVER_OK.\n\n- PowerControl (ARM_POWER_FULL) sets the peripheral registers including\n interrupt (NVIC) and optionally DMA. The function can be called multiple\n times; if the registers are already set it performs no operation and just\n returns with ARM_DRIVER_OK.\n\nTo stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:\n\\code\n   drv->PowerControl (ARM_POWER_OFF);     // Terminate any pending transfers, reset IRQ/DMA, power off peripheral\n   drv->Uninitialize (...);               // Release I/O pins\n\\endcode\n\nThe functions ARM_Storage_PowerControl and ARM_Storage_Uninitialize always execute and can be used\nto put the peripheral into a Safe State, for example after any data\ntransmission errors. To restart the peripheral in an error condition,\nyou should first execute the Stop Sequence and then the Start Sequence.\n\nThe parameter \\em state can have the following values:\n  - \\ref ARM_POWER_FULL : set-up the Storage device for data transfers, enable interrupts (NVIC) and optionally DMA. Can be called multiple times.\n                          If the device is already in this mode, then the function performs no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n\n\\note This API may execute asynchronously if\n   ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous\n   execution is optional even if 'asynchronous_ops' is set.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size)\n\\details\nRead the contents of a range of storage memory into a buffer\nsupplied by the caller. The buffer is owned by the caller and should\nremain accessible for the lifetime of this command.\n\n\\note This API may execute asynchronously if\n   ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous\n   execution is optional even if 'asynchronous_ops' is set.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size)\n\\details\nWrite the contents of a given memory buffer into a range of\nstorage memory. In the case of flash memory, the destination range in\nstorage memory typically has its contents in an erased state from a\npreceding erase operation. The source memory buffer is owned by the\ncaller and should remain accessible for the lifetime of this command.\n\n\\note It is best for the middleware to write in units of\n   'optimal_program_unit' (\\ref ARM_STORAGE_INFO) of the device.\n\n\\note This API may execute asynchronously if\n   ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous\n   execution is optional even if 'asynchronous_ops' is set.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_Erase (uint64_t addr, uint32_t size)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size)\n\n\\details\nThis function erases a range of storage specified by [addr, addr +\nsize). Both 'addr' and 'addr + size' should align with the\n'erase_unit'(s) of the respective owning storage block(s) (see \\ref\nARM_STORAGE_BLOCK and \\ref ARM_STORAGE_BLOCK_ATTRIBUTES). The range to\nbe erased will have its contents returned to the un-programmed state--\ni.e. to \\ref ARM_STORAGE_INFO::erased_value, which\nis usually 1 to indicate the pattern of all ones: 0xFF.\n\n\\note This API may execute asynchronously if\n   ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous\n   execution is optional even if 'asynchronous_ops' is set.\n\n\\note Erase() may return a smaller (positive) value than the size of the\n   requested range. The returned value indicates the actual number of bytes\n   erased. It is the caller's responsibility to follow up with an appropriate\n   request to complete the operation.\n\n\\note in the case of a failed erase (except when\n   ARM_DRIVER_ERROR_PARAMETER, ARM_STORAGE_ERROR_PROTECTED, or\n   ARM_STORAGE_ERROR_NOT_ERASABLE is returned synchronously), the\n   requested range should be assumed to be in an unknown state. The\n   previous contents may not be retained.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_EraseAll (void)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_EraseAll (void)\n\\details\nThis optional function erases the complete device. If the device does not\nsupport global erase then the function returns the error value \\ref\nARM_DRIVER_ERROR_UNSUPPORTED. The data field \\em 'erase_all' =\n\\token{1} of the structure \\ref ARM_STORAGE_CAPABILITIES encodes that\n\\ref ARM_Storage_EraseAll is supported.\n\n\\note This API may execute asynchronously if\n   ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous\n   execution is optional even if 'asynchronous_ops' is set.\n*******************************************************************************************************************/\n\nARM_Storage_STATUS ARM_Storage_GetStatus (void)  {\n  return 0;\n}\n/**\n\\fn ARM_STORAGE_STATUS ARM_Storage_GetStatus (void)\n\\details\nGet the status of the current (or previous) command executed by the\nstorage controller; stored in the structure \\ref ARM_STORAGE_STATUS.\n\n\\note This API returns synchronously--it does not result in an invocation\n   of a completion callback.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info)  {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info)\n\\details\nGet information about the Storage device; stored in the structure \\ref ARM_STORAGE_INFO.\n\n\\note It is the caller's responsibility to ensure that the buffer passed in\n       is able to be initialized with a \\ref ARM_STORAGE_INFO.\n\n\\note This API returns synchronously--it does not result in an invocation\n   of a completion callback.\n*******************************************************************************************************************/\n\nuint32_t ARM_Storage_ResolveAddress(uint64_t addr) {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_Storage_ResolveAddress(uint64_t addr)\n\\details\nOnly applicable to devices with memory-mapped storage.\n\n\\note This API returns synchronously. The invocation should return quickly,\n   and result in a resolved address.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);\n\\details\nThis helper function fetches (an iterator to) the next block (or\nthe first block if 'prev_block' is passed in as NULL). In the failure\ncase, a terminating, invalid block iterator is filled into the out\nparameter: 'next_block'. In combination with \\ref\nARM_STORAGE_VALID_BLOCK, it can be used to iterate over the sequence\nof blocks within the storage map:\n\n\\code\n  ARM_STORAGE_BLOCK block;\n  for (drv->GetNextBlock(NULL, &block); ARM_STORAGE_VALID_BLOCK(&block); drv->GetNextBlock(&block, &block)) {\n      // make use of block\n  }\n\\endcode\n\n\\note This API returns synchronously--it does not result in an invocation\n    of a completion callback.\n*******************************************************************************************************************/\n\nint32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block);\n\\note This API returns synchronously--it does not result in an invocation\n    of a completion callback.\n*******************************************************************************************************************/\n\n/**\n@}\n*/\n\n/**\n\\defgroup SampleUseOfStorageDriver Sample Use of Storage Driver\n\\ingroup storage_interface_gr\n@{\n<b>Example Code:</b>\n\nThe following is a generic algorithm to erase\nand program one \\ref ARM_STORAGE_BLOCK_ATTRIBUTES::erase_unit worth of storage\nand then read it back to be verified. It handles both synchronous and\nasynchronous driver implementations.\n\n\\code\n// Copyright (c) 2006-2016, Arm Limited, All Rights Reserved\n// SPDX-License-Identifier: Apache-2.0\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\"); you may\n// not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n// http:// www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT\n// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n\n#include \"Driver_Storage.h\"\n#include <stdio.h>\n#include <string.h>\n \n#define TEST_ASSERT(Expr)                       if (!(Expr)) { printf(\"%s:%u: assertion failure\\n\", __FUNCTION__, __LINE__); while (1) ;}\n#define TEST_ASSERT_EQUAL(expected, actual)     if ((expected) != (actual)) {printf(\"%s:%u: assertion failure\\n\", __FUNCTION__, __LINE__); while (1) ;}\n#define TEST_ASSERT_NOT_EQUAL(expected, actual) if ((expected) == (actual)) {printf(\"%s:%u: assertion failure\\n\", __FUNCTION__, __LINE__); while (1) ;}\n \n// forward declarations\nvoid callbackHandler(int32_t status, ARM_STORAGE_OPERATION operation);\nvoid progressStateMachine(void);\n \nstatic enum {\n    NEEDS_INITIALIZATION,\n    NEEDS_ERASE,\n    NEEDS_PROGRAMMING,\n    NEEDS_READ,\n    NEEDS_VERIFICATION_FOLLOWING_READ,\n    FINISHED\n} state;\n \nextern ARM_DRIVER_STORAGE ARM_Driver_Storage_(0);\nARM_DRIVER_STORAGE *drv = &ARM_Driver_Storage_(0);\n \nstatic const unsigned BUFFER_SIZE = 16384;\nstatic uint8_t buffer[BUFFER_SIZE];\n \nvoid main(int argc __unused, char** argv __unused)\n{\n    state = NEEDS_INITIALIZATION;\n \n    progressStateMachine();\n    while (true) {\n        // WFE(); // optional low-power sleep\n    }\n}\n \nvoid progressStateMachine(void)\n{\n    int32_t rc;\n \n    static ARM_STORAGE_BLOCK firstBlock;\n    if (!ARM_STORAGE_VALID_BLOCK(&firstBlock)) {\n        // Get the first block. This block is entered only once.\n        rc = drv->GetNextBlock(NULL, &firstBlock); // get first block\n        TEST_ASSERT_EQUAL(ARM_DRIVER_OK, rc);\n    }\n    TEST_ASSERT(ARM_STORAGE_VALID_BLOCK(&firstBlock));\n    TEST_ASSERT(firstBlock.size > 0);\n \n    switch (state) {\n        case NEEDS_INITIALIZATION:\n            rc = drv->Initialize(callbackHandler);\n            TEST_ASSERT(rc >= ARM_DRIVER_OK);\n            if (rc == ARM_DRIVER_OK) {\n                TEST_ASSERT_EQUAL(1, drv->GetCapabilities().asynchronous_ops);\n                state = NEEDS_ERASE;\n                return; // there is pending asynchronous activity which will lead to a completion callback later.\n            }\n            TEST_ASSERT_EQUAL(1, rc); // synchronous completion\n \n            // intentional fall-through\n \n        case NEEDS_ERASE:\n            TEST_ASSERT(firstBlock.attributes.erase_unit > 0);\n            rc = drv->Erase(firstBlock.addr, firstBlock.attributes.erase_unit);\n            TEST_ASSERT(rc >= ARM_DRIVER_OK);\n            if (rc == ARM_DRIVER_OK) {\n                TEST_ASSERT_EQUAL(1, drv->GetCapabilities().asynchronous_ops);\n                state = NEEDS_PROGRAMMING;\n                return; // there is pending asynchronous activity which will lead to a completion callback later.\n            }\n            TEST_ASSERT_EQUAL(firstBlock.attributes.erase_unit, (uint32_t)rc); // synchronous completion\n \n            // intentional fall-through\n \n        case NEEDS_PROGRAMMING:\n            TEST_ASSERT(BUFFER_SIZE >= firstBlock.attributes.erase_unit);\n            #define PATTERN 0xAA\n            memset(buffer, PATTERN, firstBlock.attributes.erase_unit);\n            rc = drv->ProgramData(firstBlock.addr, buffer, firstBlock.attributes.erase_unit);\n            TEST_ASSERT(rc >= ARM_DRIVER_OK);\n            if (rc == ARM_DRIVER_OK) {\n                TEST_ASSERT_EQUAL(1, drv->GetCapabilities().asynchronous_ops);\n                state = NEEDS_READ;\n                return;  // there is pending asynchronous activity which will lead to a completion callback later.\n            }\n            TEST_ASSERT_EQUAL(firstBlock.attributes.erase_unit, (uint32_t)rc); // synchronous completion\n \n            // intentional fall-through\n \n        case NEEDS_READ:\n            rc = drv->ReadData(firstBlock.addr, buffer, firstBlock.attributes.erase_unit);\n            TEST_ASSERT(rc >= ARM_DRIVER_OK);\n            if (rc == ARM_DRIVER_OK) {\n                TEST_ASSERT_EQUAL(1, drv->GetCapabilities().asynchronous_ops);\n                state = NEEDS_VERIFICATION_FOLLOWING_READ;\n                return;  // there is pending asynchronous activity which will lead to a completion callback later.\n            }\n            TEST_ASSERT_EQUAL(firstBlock.attributes.erase_unit, (uint32_t)rc);\n \n            // intentional fall-through\n \n        case NEEDS_VERIFICATION_FOLLOWING_READ:\n            printf(\"verifying data\\r\\n\");\n            for (unsigned i = 0; i < firstBlock.attributes.erase_unit; i++) {\n                TEST_ASSERT_EQUAL(PATTERN, buffer[i]);\n            }\n            state = FINISHED;\n            printf(\"done\\r\\n\");\n            break;\n \n        case FINISHED:\n            break;\n    } // switch (state)\n}\n \nvoid callbackHandler(int32_t status, ARM_STORAGE_OPERATION operation)\n{\n    (void)status;\n    (void)operation;\n    switch (operation) {\n        case ARM_STORAGE_OPERATION_INITIALIZE:\n        case ARM_STORAGE_OPERATION_READ_DATA:\n        case ARM_STORAGE_OPERATION_PROGRAM_DATA:\n        case ARM_STORAGE_OPERATION_ERASE:\n            progressStateMachine();\n            break;\n \n        default:\n            printf(\"callbackHandler: unexpected callback for opcode %u with status %ld\\r\\n\", operation, status);\n            break;\n    }\n}\n\\endcode\n@}\n*******************************************************************************************************************/\n// End Storage Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_USART.c",
    "content": "/**\n\\defgroup usart_interface_gr USART Interface\n\\brief   Driver API for Universal Synchronous Asynchronous Receiver/Transmitter (%Driver_USART.h)\n\\details \nThe <b>Universal Synchronous Asynchronous Receiver/Transmitter</b> (USART) implements a synchronous and asynchronous serial bus for exchanging data. \nWhen only asynchronous mode is supported it is called Universal Asynchronous Receiver/Transmitter (UART).  \nAlmost all microcontrollers have a serial interface (UART/USART peripheral). A UART is a simple device to send data to a PC\nvia a terminal emulation program (Hyperterm, TeraTerm) or to another microcontroller.\nA UART takes bytes of data and transmits the individual bits in a sequential mode. At the destination, \na second UART reassembles the bits into complete bytes. Each UART contains a shift register for converting between serial and parallel transmission forms. \nWikipedia offers more information about  \nthe <a href=\"http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter\" target=\"_blank\"><b>Universal asynchronous receiver/transmitter</b></a>.\n\n\n<b>USART API</b>\n\nThe following header files define the Application Programming Interface (API) for the USART interface:\n  - \\b %Driver_USART.h : Driver API for Universal Synchronous Asynchronous Receiver/Transmitter\n\nThe driver implementation is a typical part of the Device Family Pack (DFP) that supports the \nperipherals of the microcontroller family.\n\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_USART : access struct for USART driver functions\n\n  \n<b>Example Code</b>\n\nThe following example code shows the usage of the USART interface for asynchronous communication.\n\n\\include USART_Demo.c\n\n@{\n*/\n\n/** \n\\struct     ARM_DRIVER_USART\n\\details\nThe functions of the USART driver are accessed by function pointers exposed by this structure.\nRefer to \\ref DriverFunctions for overview information.\n\nEach instance of an USART interface provides such an access structure. \nThe instance is identified by a postfix number in the symbol name of the access structure, for example:\n - \\b Driver_USART0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_USART1 is the name of the access struct of the second instance (no. 1).\n\nA middleware configuration setting allows connecting the middleware to a specific driver instance \\b %Driver_USART<i>n</i>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_USART_CAPABILITIES \n\\details\nAn USART driver can be implemented with different capabilities.\nThe data fields of this structure encode the capabilities implemented by this driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_USART_GetCapabilities\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_USART_STATUS\n\\details\nStructure with information about the status of the USART. The data fields encode busy flags and error flags.\n\n<b>Returned by:</b>\n  - \\ref ARM_USART_GetStatus\n*****************************************************************************************************************/\n\n/**\n\\enum     ARM_USART_MODEM_CONTROL\n\\details\nSpecifies values for controlling the modem control lines.\n\n<b>Parameter for:</b>\n  - \\ref ARM_USART_SetModemControl\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_USART_MODEM_STATUS \n\\details\nStructure with information about the status of modem lines. The data fields encode states of modem status lines.\n\n<b>Returned by:</b>\n  - \\ref ARM_USART_GetModemStatus\n*****************************************************************************************************************/\n\n\n/**\n\\typedef    ARM_USART_SignalEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_USART_SignalEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_USART_Initialize\n*******************************************************************************************************************/\n\n\n/**\n\\defgroup usart_execution_status Status Error Codes\n\\ingroup common_drv_gr\n\\brief Negative values indicate errors (USART has specific codes in addition to common \\ref execution_status). \n\\details \nThe USART driver has additional status error codes that are listed below.\nNote that the USART driver also returns the common \\ref execution_status. \n  \n@{\n\\def ARM_USART_ERROR_MODE\nThe \\b mode requested with the function \\ref ARM_USART_Control is not supported by this driver.\n\n\\def ARM_USART_ERROR_BAUDRATE\nThe <b>baud rate</b> requested with the function \\ref ARM_USART_Control is not supported by this driver.\n\n\\def ARM_USART_ERROR_DATA_BITS\nThe number of <b>data bits</b> requested with the function \\ref ARM_USART_Control is not supported by this driver.\n\n\\def ARM_USART_ERROR_PARITY\nThe <b>parity bit</b> requested with the function \\ref ARM_USART_Control is not supported by this driver.\n\n\\def ARM_USART_ERROR_STOP_BITS\nThe <b>stop bit</b> requested with the function \\ref ARM_USART_Control is not supported by this driver.\n\n\\def ARM_USART_ERROR_FLOW_CONTROL\nThe <b>flow control</b> requested with the function \\ref ARM_USART_Control is not supported by this driver.\n\n\\def ARM_USART_ERROR_CPOL\nThe <b>clock polarity</b> requested with the function \\ref ARM_USART_Control is not supported by this driver.\n\n\\def ARM_USART_ERROR_CPHA\nThe <b>clock phase</b> requested with the function \\ref ARM_USART_Control is not supported by this driver.\n@}\n*/\n\n\n/**\n\\defgroup USART_events USART Events\n\\ingroup usart_interface_gr\n\\brief The USART driver generates call back events that are notified via the function \\ref ARM_USART_SignalEvent.\n\\details \nThis section provides the event values for the \\ref ARM_USART_SignalEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def ARM_USART_EVENT_SEND_COMPLETE\n\\def ARM_USART_EVENT_RECEIVE_COMPLETE\n\\def ARM_USART_EVENT_TRANSFER_COMPLETE\n\\def ARM_USART_EVENT_TX_COMPLETE\n\\def ARM_USART_EVENT_TX_UNDERFLOW\n\\def ARM_USART_EVENT_RX_OVERFLOW\n\\def ARM_USART_EVENT_RX_TIMEOUT\n\\def ARM_USART_EVENT_RX_BREAK\n\\def ARM_USART_EVENT_RX_FRAMING_ERROR\n\\def ARM_USART_EVENT_RX_PARITY_ERROR\n\\def ARM_USART_EVENT_CTS\n\\def ARM_USART_EVENT_DSR\n\\def ARM_USART_EVENT_DCD\n\\def ARM_USART_EVENT_RI\n@}\n*/\n\n\n/**\n\\defgroup USART_control USART Control Codes\n\\ingroup usart_interface_gr\n\\brief Many parameters of the USART driver are configured using the \\ref ARM_USART_Control function.\n\\details\n@{\nThe various USART control codes define:\n  - \\ref usart_mode_control specifies USART mode\n  - \\ref usart_data_bits defines the number of data bits\n  - \\ref usart_parity_bit defines the parity bit\n  - \\ref usart_stop_bits defines the number of stop bits\n  - \\ref usart_flow_control specifies RTS/CTS flow control\n  - \\ref usart_clock_polarity defines the clock polarity for the synchronous mode\n  - \\ref usart_clock_phase defines the clock phase for the synchronous mode\n  - \\ref usart_misc_control specifies additional miscellaneous controls\n\nRefer to the \\ref ARM_USART_Control function for further details.\n\n*/\n\n\n/**\n\\defgroup usart_mode_control USART Mode Control\n\\ingroup USART_control\n\\brief Specify USART mode.\n\\details\n@{\n\\def ARM_USART_MODE_ASYNCHRONOUS\n\\sa ARM_USART_Control\n\\def ARM_USART_MODE_SYNCHRONOUS_MASTER\n\\sa ARM_USART_Control\n\\def ARM_USART_MODE_SYNCHRONOUS_SLAVE\n\\sa ARM_USART_Control\n\\def ARM_USART_MODE_SINGLE_WIRE\n\\sa ARM_USART_Control\n\\def ARM_USART_MODE_IRDA\n\\sa ARM_USART_Control\n\\def ARM_USART_MODE_SMART_CARD\n\\sa ARM_USART_Control\n@}\n*/\n\n\n/**\n\\defgroup usart_misc_control USART Miscellaneous Control\n\\ingroup USART_control\n\\brief Specifies additional miscellaneous controls.\n\\details\n@{\n\\def ARM_USART_SET_DEFAULT_TX_VALUE\n\\sa ARM_USART_Control;  ARM_USART_Receive;\n\\def ARM_USART_SET_IRDA_PULSE\n\\sa ARM_USART_Control\n\\def ARM_USART_SET_SMART_CARD_GUARD_TIME\n\\sa ARM_USART_Control\n\\def ARM_USART_SET_SMART_CARD_CLOCK\n\\sa ARM_USART_Control\n\\def ARM_USART_CONTROL_SMART_CARD_NACK\n\\sa ARM_USART_Control\n\\def ARM_USART_CONTROL_TX\n\\sa ARM_USART_Control;  ARM_USART_Send;  ARM_USART_Transfer\n\\def ARM_USART_CONTROL_RX\n\\sa ARM_USART_Control;  ARM_USART_Receive; ARM_USART_Transfer; \n\\def ARM_USART_CONTROL_BREAK\n\\sa ARM_USART_Control\n\\def ARM_USART_ABORT_SEND\n\\sa ARM_USART_Control;\n\\def ARM_USART_ABORT_RECEIVE\n\\sa ARM_USART_Control;\n\\def ARM_USART_ABORT_TRANSFER\n\\sa ARM_USART_Control;\n@}\n*/\n\n/**\n\\defgroup usart_data_bits  USART Data Bits\n\\ingroup USART_control\n\\brief Defines the number of data bits.\n\\details\n@{\n\\def ARM_USART_DATA_BITS_5\n\\sa ARM_USART_Control\n\\def ARM_USART_DATA_BITS_6\n\\sa ARM_USART_Control\n\\def ARM_USART_DATA_BITS_7\n\\sa ARM_USART_Control\n\\def ARM_USART_DATA_BITS_8\n\\sa ARM_USART_Control\n\\def ARM_USART_DATA_BITS_9\n\\sa ARM_USART_Control\n@}\n*/\n\n/**\n\\defgroup usart_parity_bit  USART Parity Bit\n\\ingroup USART_control\n\\brief Defines the parity bit.\n\\details\n@{\n\\def ARM_USART_PARITY_NONE\n\\sa ARM_USART_Control\n\\def ARM_USART_PARITY_EVEN\n\\sa ARM_USART_Control\n\\def ARM_USART_PARITY_ODD\n\\sa ARM_USART_Control\n@}\n*/\n\n/**\n\\defgroup usart_stop_bits  USART Stop Bits\n\\ingroup USART_control\n\\brief Defines the number of stop bits.\n\\details\n@{\n\\sa ARM_USART_Control\n\\def ARM_USART_STOP_BITS_1\n\\sa ARM_USART_Control\n\\def ARM_USART_STOP_BITS_2\n\\sa ARM_USART_Control\n\\def ARM_USART_STOP_BITS_1_5\n\\sa ARM_USART_Control\n\\def ARM_USART_STOP_BITS_0_5\n\\sa ARM_USART_Control\n@}\n*/\n\n/**\n\\defgroup usart_flow_control USART Flow Control\n\\ingroup USART_control\n\\brief Specifies RTS/CTS flow control.\n\\details\n@{\n\\def ARM_USART_FLOW_CONTROL_NONE\n\\sa ARM_USART_Control\n\\def ARM_USART_FLOW_CONTROL_RTS\n\\sa ARM_USART_Control\n\\def ARM_USART_FLOW_CONTROL_CTS\n\\sa ARM_USART_Control\n\\def ARM_USART_FLOW_CONTROL_RTS_CTS\n\\sa ARM_USART_Control\n@}\n*/\n\n/**\n\\defgroup usart_clock_polarity USART Clock Polarity\n\\ingroup USART_control\n\\brief Defines the clock polarity for the synchronous mode.\n\\details\n@{\n\\def ARM_USART_CPOL0\n\\sa ARM_USART_Control; ARM_USART_Receive; ARM_USART_Send;  ARM_USART_Transfer\n\\def ARM_USART_CPOL1\n\\sa ARM_USART_Control; ARM_USART_Receive; ARM_USART_Send;  ARM_USART_Transfer\n@}\n*/\n\n/**\n\\defgroup usart_clock_phase USART Clock Phase \n\\ingroup USART_control\n\\brief Defines the clock phase for the synchronous mode.\n\\details\n@{\n\\def ARM_USART_CPHA0\n\\sa ARM_USART_Control; ARM_USART_Receive; ARM_USART_Send;  ARM_USART_Transfer\n\\def ARM_USART_CPHA1\n\\sa ARM_USART_Control; ARM_USART_Receive; ARM_USART_Send;  ARM_USART_Transfer\n@}\n*/\n\n/**\n@}\n*/\n// end group USART_control\n\n\n//\n//   Functions\n//\n\nARM_DRIVER_VERSION ARM_USART_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn     ARM_DRIVER_VERSION ARM_USART_GetVersion (void)\n\\details\nThe function \\b ARM_USART_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_USART Driver_USART0;\nARM_DRIVER_USART *drv_info;\n \nvoid setup_usart (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_USART0;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)  {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*****************************************************************************************************************/\n\nARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)  {\n  return  { 0 } ;\n}\n/**\n\\fn       ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)\n\\details\nThe function \\b ARM_USART_GetCapabilities returns information about capabilities in this driver implementation.\nThe data fields of the structure \\ref ARM_USART_CAPABILITIES encode various capabilities, for example: \nsupported modes, if hardware and driver are capable of signaling events using the \\ref ARM_USART_SignalEvent \ncallback function ...\n \nExample:\n\\code\nextern ARM_DRIVER_USART Driver_USART0;\nARM_DRIVER_USART *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_USART_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_USART0;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*****************************************************************************************************************/\n\nint32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)\n\\details\nThe function \\b ARM_USART_Initialize initializes the USART interface. \nIt is called when the middleware component starts operation.\n\nThe function performs the following operations:\n  - Initializes the resources needed for the USART interface.\n  - Registers the \\ref ARM_USART_SignalEvent callback function.\n\nThe parameter \\em cb_event is a pointer to the \\ref ARM_USART_SignalEvent callback function; use a NULL pointer \nwhen no callback signals are required.\n\n\\b Example:\n - see \\ref usart_interface_gr - Driver Functions\n\n*****************************************************************************************************************/\n\nint32_t ARM_USART_Uninitialize (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_USART_Uninitialize (void)\n\\details\nThe function \\b ARM_USART_Uninitialize de-initializes the resources of USART interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n*****************************************************************************************************************/\n\nint32_t ARM_USART_PowerControl (ARM_POWER_STATE state)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_USART_PowerControl operates the power modes of the USART interface.  \n\nThe parameter \\em state sets the operation and can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. \n                          Can be called multiple times. If the peripheral is already in this mode the function performs \n\t\t\t\t\t\t  no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n\n*****************************************************************************************************************/\n\nint32_t ARM_USART_Send (const void *data, uint32_t num)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USART_Send (const void *data, uint32_t num) \n\\details\nThis functions \\b ARM_USART_Send is used in asynchronous mode to send data to the USART transmitter.\nIt can also be used in synchronous mode when sending data only (received data is ignored). \n\nTransmitter needs to be enabled by calling \\ref ARM_USART_Control with \\ref ARM_USART_CONTROL_TX as the control parameter and \\token{1} as argument. \n\nThe function parameters specify the buffer with data and the number of items to send.\nThe item size is defined by the data type which depends on the configured number of data bits.\n\nData type is:\n - \\em uint8_t when configured for 5..8 data bits\n - \\em uint16_t when configured for 9 data bits\n \nCalling the function <b>ARM_USART_Send</b> only starts the send operation.\nThe function is non-blocking and returns as soon as the driver has started the operation (driver typically configures DMA or the interrupt system for continuous transfer).\nWhen in synchronous slave mode the operation is only registered and started when the master starts the transfer.\nDuring the operation it is not allowed to call this function again or any other data transfer function when in synchronous mode. Also the data buffer must stay allocated and the contents of unsent data must not be modified.\nWhen send operation is completed (requested number of items sent) the \\ref ARM_USART_EVENT_SEND_COMPLETE event is generated.\nProgress of send operation can also be monitored by reading the number of items already sent by calling \\ref ARM_USART_GetTxCount. \n\nAfter send operation has completed there might still be some data left in the driver's hardware buffer which is still being transmitted.\nWhen all data has been physically transmitted the \\ref ARM_USART_EVENT_TX_COMPLETE event is generated (if supported and reported by \\em event_tx_complete in \\ref ARM_USART_CAPABILITIES).\nAt that point also the \\em tx_busy data field in \\ref ARM_USART_STATUS is cleared.\n\nStatus of the transmitter can be monitored by calling the \\ref ARM_USART_GetStatus and checking the \\em tx_busy flag\nwhich indicates if transmission is still in progress. \n\nWhen in synchronous slave mode and transmitter is enabled but send/receive/transfer operation is not started and data is requested by the master then the \\ref ARM_USART_EVENT_TX_UNDERFLOW event is generated. \n\nSend operation can be aborted by calling \\ref ARM_USART_Control with \\ref ARM_USART_ABORT_SEND as the control parameter.\n*****************************************************************************************************************/\n\nint32_t ARM_USART_Receive (void *data, uint32_t num)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USART_Receive (void *data, uint32_t num)\n\\details\nThis functions \\b ARM_USART_Receive is used in asynchronous mode to receive data from the USART receiver.\nIt can also be used in synchronous mode when receiving data only (transmits the default value as specified by \\ref ARM_USART_Control with \\ref ARM_USART_SET_DEFAULT_TX_VALUE as control parameter). \n\nReceiver needs to be enabled by calling \\ref ARM_USART_Control with \\ref ARM_USART_CONTROL_RX as the control parameter and \\token{1} as argument. \n\nThe function parameters specify the buffer for data and the number of items to receive.\nThe item size is defined by the data type which depends on the configured number of data bits.\n\nData type is:\n - \\em uint8_t when configured for 5..8 data bits\n - \\em uint16_t when configured for 9 data bits\n \nCalling the function <b>ARM_USART_Receive</b> only starts the receive operation.\nThe function is non-blocking and returns as soon as the driver has started the operation (driver typically configures DMA or the interrupt system for continuous transfer).\nWhen in synchronous slave mode the operation is only registered and started when the master starts the transfer.\nDuring the operation it is not allowed to call this function again or any other data transfer function when in synchronous mode. Also the data buffer must stay allocated.\nWhen receive operation is completed (requested number of items received) the \\ref ARM_USART_EVENT_RECEIVE_COMPLETE event is generated.\nProgress of receive operation can also be monitored by reading the number of items already received by calling \\ref ARM_USART_GetRxCount. \n\nStatus of the receiver can be monitored by calling the \\ref ARM_USART_GetStatus and checking the \\em rx_busy flag\nwhich indicates if reception is still in progress. \n\nDuring reception the following events can be generated (in asynchronous mode):\n - \\ref ARM_USART_EVENT_RX_TIMEOUT : Receive timeout between consecutive characters detected (optional)\n - \\ref ARM_USART_EVENT_RX_BREAK : Break detected (Framing error is not generated for Break condition)\n - \\ref ARM_USART_EVENT_RX_FRAMING_ERROR : Framing error detected\n - \\ref ARM_USART_EVENT_RX_PARITY_ERROR : Parity error detected\n - \\ref ARM_USART_EVENT_RX_OVERFLOW : Data overflow detected (also in synchronous slave mode)\n\n\\ref ARM_USART_EVENT_RX_OVERFLOW event is also generated when receiver is enabled but data is lost because \nreceive operation in asynchronous mode or receive/send/transfer operation in synchronous slave mode has not been started.\n\nReceive operation can be aborted by calling \\ref ARM_USART_Control with \\ref ARM_USART_ABORT_RECEIVE as the control parameter.\n*****************************************************************************************************************/\n\nint32_t ARM_USART_Transfer (const void *data_out, void *data_in, uint32_t num) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USART_Transfer (const void *data_out, void *data_in, uint32_t num) \n\\details\nThis functions \\b ARM_USART_Transfer is used in synchronous mode to transfer data via USART. It synchronously sends data to the USART transmitter and receives data from the USART receiver. \n\nTransmitter needs to be enabled by calling \\ref ARM_USART_Control with \\ref ARM_USART_CONTROL_TX as the control parameter and \\token{1} as argument. \nReceiver needs to be enabled by calling \\ref ARM_USART_Control with \\ref ARM_USART_CONTROL_RX as the control parameter and \\token{1} as argument. \n\nThe function parameters specify the buffer with data to send, the buffer for data to receive and the number of items to transfer.\nThe item size is defined by the data type which depends on the configured number of data bits.\n\nData type is:\n - \\em uint8_t when configured for 5..8 data bits\n - \\em uint16_t when configured for 9 data bits\n \nCalling the function <b>ARM_USART_Transfer</b> only starts the transfer operation.\nThe function is non-blocking and returns as soon as the driver has started the operation (driver typically configures DMA or the interrupt system for continuous transfer).\nWhen in synchronous slave mode the operation is only registered and started when the master starts the transfer.\nDuring the operation it is not allowed to call this function or any other data transfer function again. Also the data buffers must stay allocated and the contents of unsent data must not be modified.\nWhen transfer operation is completed (requested number of items transferred) the \\ref ARM_USART_EVENT_TRANSFER_COMPLETE event is generated.\nProgress of transfer operation can also be monitored by reading the number of items already transferred by calling \\ref ARM_USART_GetTxCount or \\ref ARM_USART_GetRxCount. \n\nStatus of the transmitter or receiver can be monitored by calling the \\ref ARM_USART_GetStatus and checking the \\em tx_busy or \\em rx_busy flag. \n\nWhen in synchronous slave mode also the following events can be generated:\n - \\ref ARM_USART_EVENT_TX_UNDERFLOW : transmitter is enabled but transfer operation is not started and data is requested by the master\n - \\ref ARM_USART_EVENT_RX_OVERFLOW : data lost during transfer or because receiver is enabled but transfer operation has not been started\n\nTransfer operation can also be aborted by calling \\ref ARM_USART_Control with \\ref ARM_USART_ABORT_TRANSFER as the control parameter.\n*****************************************************************************************************************/\n\nuint32_t ARM_USART_GetTxCount (void)  {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_USART_GetTxCount (void)\n\\details\nThe function \\b ARM_USART_GetTxCount returns the number of the currently transmitted data items during \\ref ARM_USART_Send and \\ref ARM_USART_Transfer operation.\n*****************************************************************************************************************/\n\nuint32_t ARM_USART_GetRxCount (void)  {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_USART_GetRxCount (void)\n\\details\nThe function \\b  ARM_USART_GetRxCount returns the number of the currently received data items during \\ref ARM_USART_Receive and \\ref ARM_USART_Transfer operation.\n*****************************************************************************************************************/\n\nint32_t ARM_USART_Control (uint32_t control, uint32_t arg)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg)\n\\details\nThe function \\b ARM_USART_Control control the USART interface settings and execute various operations.\n\nThe parameter \\em control sets the operation and is explained in the table below.\nValues from different categories can be ORed with the exception of \\ref usart_misc_tab \"Miscellaneous Operations\".\n\nThe parameter \\em arg provides, depending on the operation, additional information, for example the baudrate.\n\nThe table lists the available \\em control operations.\n\n<TABLE class=\"cmtable\" summary=\"\">\n<TR><TH>Parameter \\em control           </TH>  <TH style=\"text-align:right\"> Bit                 </TH>     <TH> Category </TH> <TH>Description </TH></TR>\n<TR><TD>\\ref ARM_USART_MODE_ASYNCHRONOUS</TD>         <td rowspan=\"6\" style=\"text-align:right\"> 0..7    </td>     <td rowspan=\"6\"> Operation Mode  </td><TD>Set to asynchronous UART mode. \\em arg specifies baudrate.</TD></TR>\n<TR><TD>\\ref ARM_USART_MODE_SYNCHRONOUS_MASTER</TD>   <TD>Set to synchronous master mode with clock signal generation. \\em arg specifies baudrate.</TD></TR>\n<TR><TD>\\ref ARM_USART_MODE_SYNCHRONOUS_SLAVE</TD>    <TD>Set to synchronous slave mode with external clock signal.</TD></TR>\n<TR><TD>\\ref ARM_USART_MODE_SINGLE_WIRE</TD>          <TD>Set to single-wire (half-duplex) mode. \\em arg specifies baudrate.</TD></TR>\n<TR><TD>\\ref ARM_USART_MODE_IRDA</TD>                 <TD>Set to Infra-red data mode. \\em arg specifies baudrate.</TD></TR>\n<TR><TD>\\ref ARM_USART_MODE_SMART_CARD</TD>           <TD>Set to Smart Card mode. \\em arg specifies baudrate.</TD></TR>\n<TR><TD>\\ref ARM_USART_DATA_BITS_5</TD>        <td rowspan=\"5\" style=\"text-align:right\"> 8..11    </td>     <td rowspan=\"5\"> Data Bits  </td><TD>Set to \\token{5} data bits</TD></TR>\n<TR><TD>\\ref ARM_USART_DATA_BITS_6</TD>           <TD>Set to \\token{6} data bits</TD></TR>\n<TR><TD>\\ref ARM_USART_DATA_BITS_7</TD>           <TD>Set to \\token{7} data bits</TD></TR>\n<TR><TD>\\ref ARM_USART_DATA_BITS_8</TD>           <TD>Set to \\token{8} data bits (default)</TD></TR>\n<TR><TD>\\ref ARM_USART_DATA_BITS_9</TD>           <TD>Set to \\token{9} data bits</TD></TR>\n<TR><TD>\\ref ARM_USART_PARITY_EVEN</TD>        <td rowspan=\"3\" style=\"text-align:right\"> 12..13 </td>  <td rowspan=\"3\"> Parity Bit  </td><TD>Set to Even Parity</TD></TR>\n<TR><TD>\\ref ARM_USART_PARITY_NONE</TD>           <TD>Set to No Parity (default)</TD></TR>\n<TR><TD>\\ref ARM_USART_PARITY_ODD</TD>            <TD>Set to Odd Parity</TD></TR>\n<TR><TD>\\ref ARM_USART_STOP_BITS_1</TD>        <td rowspan=\"4\" style=\"text-align:right\"> 14..15 </td>  <td rowspan=\"4\"> Stop Bit  </td><TD>Set to \\token{1} Stop bit (default)</TD></TR>\n<TR><TD>\\ref ARM_USART_STOP_BITS_2</TD>           <TD>Set to \\token{2} Stop bits</TD></TR>\n<TR><TD>\\ref ARM_USART_STOP_BITS_1_5</TD>         <TD>Set to \\token{1.5} Stop bits</TD></TR>\n<TR><TD>\\ref ARM_USART_STOP_BITS_0_5</TD>         <TD>Set to \\token{0.5} Stop bits</TD></TR>\n<TR><TD>\\ref ARM_USART_FLOW_CONTROL_NONE</TD>  <td rowspan=\"4\" style=\"text-align:right\"> 16..17 </td>  <td rowspan=\"4\"> Flow Control  </td><TD>No flow control signal (default)</TD></TR>\n<TR><TD>\\ref ARM_USART_FLOW_CONTROL_CTS</TD>      <TD>Set to use the CTS flow control signal</TD></TR> \n<TR><TD>\\ref ARM_USART_FLOW_CONTROL_RTS</TD>      <TD>Set to use the RTS flow control signal</TD></TR>\n<TR><TD>\\ref ARM_USART_FLOW_CONTROL_RTS_CTS</TD>  <TD>Set to use the RTS and CTS flow control signal</TD></TR> \n<TR><TD>\\ref ARM_USART_CPOL0</TD>              <td rowspan=\"2\" style=\"text-align:right\"> 18     </td>  <td rowspan=\"2\"> Clock Polarity  </td><TD>CPOL=\\token{0} (default) : data are captured on rising edge (low->high transition)</TD></TR> \n<TR><TD>\\ref ARM_USART_CPOL1</TD>                 <TD>CPOL=\\token{1} : data are captured on falling edge (high->low transition)</TD></TR> \n<TR><TD>\\ref ARM_USART_CPHA0</TD>              <td rowspan=\"2\" style=\"text-align:right\"> 19     </td>  <td rowspan=\"2\"> Clock Phase  </td><TD>CPHA=\\token{0} (default) : sample on first (leading) edge</TD></TR>\n<TR><TD>\\ref ARM_USART_CPHA1</TD>                 <TD>CPHA=\\token{1} : sample on second (trailing) edge</TD></TR>\n<TR><TD>\\ref ARM_USART_ABORT_RECEIVE</TD>      <td rowspan=\"11\" style=\"text-align:right\"> 0..19  </td>  <td rowspan=\"11\"> \\anchor usart_misc_tab Miscellaneous Operations <br>(cannot be ORed)  </td><TD>Abort receive operation (see also: \\ref ARM_USART_Receive)</TD></TR>\n<TR> <TD>\\ref ARM_USART_ABORT_SEND</TD>                 <TD>Abort  send operation   (see also: \\ref ARM_USART_Send)</TD></TR>\n<TR> <TD>\\ref ARM_USART_ABORT_TRANSFER</TD>             <TD>Abort transfer operation  (see also: \\ref ARM_USART_Transfer)</TD></TR>\n<TR> <TD>\\ref ARM_USART_CONTROL_BREAK</TD>              <TD>Enable or disable continuous Break transmission; \\em arg : \\token{0=disabled; 1=enabled}</TD></TR> \n<TR> <TD>\\ref ARM_USART_CONTROL_RX</TD>                 <TD>Enable or disable receiver; \\em arg : \\token{0=disabled; 1=enabled} (see also: \\ref ARM_USART_Receive; \\ref ARM_USART_Transfer)</TD></TR>\n<TR> <TD>\\ref ARM_USART_CONTROL_SMART_CARD_NACK</TD>    <TD>Enable or disable Smart Card NACK generation; \\em arg : \\token{0=disabled; 1=enabled}</TD></TR> \n<TR> <TD>\\ref ARM_USART_CONTROL_TX</TD>                 <TD>Enable or disable transmitter; \\em arg : \\token{0=disabled; 1=enabled} (see also: \\ref ARM_USART_Send; \\ref ARM_USART_Transfer)</TD></TR>\n<TR> <TD>\\ref ARM_USART_SET_DEFAULT_TX_VALUE</TD>       <TD>Set the default transmit value (synchronous receive only); \\em arg specifies the value. (see also: \\ref ARM_USART_Receive)</TD></TR>\n<TR> <TD>\\ref ARM_USART_SET_IRDA_PULSE</TD>             <TD>Set the IrDA pulse value in \\token{ns}; \\em arg : \\token{0=3/16 of bit period}</TD></TR>\n<TR> <TD>\\ref ARM_USART_SET_SMART_CARD_CLOCK</TD>       <TD>Set the Smart Card Clock in \\token{Hz}; \\em arg : \\token{0=Clock not set}</TD></TR>\n<TR> <TD>\\ref ARM_USART_SET_SMART_CARD_GUARD_TIME</TD>  <TD>Set the Smart Card guard time; \\em arg = number of bit periods</TD></TR>\n</TABLE>\n\n\\b Example\n\n\\code\n  extern ARM_DRIVER_USART Driver_USART0;\n  \n  // configure to UART mode: 8 bits, no parity, 1 stop bit, no flow control, 9600 bps\n  status = Driver_USART0.Control(ARM_USART_MODE_ASYNCHRONOUS | \n                                 ARM_USART_DATA_BITS_8 | \n                                 ARM_USART_PARITY_NONE | \n                                 ARM_USART_STOP_BITS_1 | \n                                 ARM_USART_FLOW_CONTROL_NONE, 9600);\n \n  // identical with above settings (default settings removed)\n  // configure to UART mode: 8 bits, no parity, 1 stop bit, flow control, 9600 bps\n  status = Driver_USART0.Control(ARM_USART_MODE_ASYNCHRONOUS, 9600);\n \n  // enable TX output\n  status = Driver_USART0.Control(ARM_USART_CONTROL_TX, 1);\n \n  // disable RX output\n  status = Driver_USART0.Control(ARM_USART_CONTROL_RX, 0);\n\\endcode\n*****************************************************************************************************************/\n\nARM_USART_STATUS ARM_USART_GetStatus (void)  {\n  return { 0 };\n}\n/**\n\\fn ARM_USART_STATUS ARM_USART_GetStatus (void)\n\\details\nThe function \\b ARM_USART_GetStatus retrieves the current USART interface status.\n\n*****************************************************************************************************************/\n\nint32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)\n\\details\nThe function \\b ARM_USART_SetModemControl activates or deactivates the selected USART modem control line. \n\nThe function \\ref ARM_USART_GetModemStatus returns information about status of the modem lines.\n\n*****************************************************************************************************************/\n\nARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)  {\n  return { 0 };\n}\n/**\n\\fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)\n\\details\nThe function \\b ARM_USART_GetModemStatus returns the current USART Modem Status lines state.\n\nThe function \\ref ARM_USART_SetModemControl sets the modem control lines of the USART.\n\n*****************************************************************************************************************/\n\nvoid ARM_USART_SignalEvent (uint32_t event)  {\n  // function body\n}\n/**\n\\fn void ARM_USART_SignalEvent (uint32_t event)\n\\details\nThe function \\b ARM_USART_SignalEvent is a callback function registered by the function \\ref ARM_USART_Initialize. \n\nThe parameter \\em event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nNot every event is necessarily generated by the driver. This depends on the implemented capabilities stored in the \ndata fields of the structure \\ref ARM_USART_CAPABILITIES, which can be retrieved with the function \\ref ARM_USART_GetCapabilities.\n\nThe following events can be generated:\n\n<table class=\"cmtable\" summary=\"\">\n<tr>\n  <th> Parameter \\em event                      </th><th> Bit </th><th> Description </th>                                              \n  <th> supported when ARM_USART_CAPABILITIES    </th>\n</tr>\n<tr>\n  <td> \\ref ARM_USART_EVENT_SEND_COMPLETE       </td><td>  0  </td><td> Occurs after call to \\ref ARM_USART_Send to indicate that all the data to be sent \n                                                                        was processed by the driver. All the data might have been already transmitted \n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tor parts of it are still queued in transmit buffers. The driver is ready for the next \n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tcall to \\ref ARM_USART_Send; however USART may still transmit data. </td>     \n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> \\ref ARM_USART_EVENT_RECEIVE_COMPLETE    </td><td>  1  </td><td> Occurs after call to \\ref ARM_USART_Receive to indicate that all the data has been \n                                                                        received. The driver is ready for the next call to \\ref ARM_USART_Receive. </td>     \n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> \\ref ARM_USART_EVENT_TRANSFER_COMPLETE   </td><td>  2  </td><td> Occurs after call to \\ref ARM_USART_Transfer to indicate that all the data has been \n                                                                        transferred. The driver is ready for the next call to \\ref ARM_USART_Transfer. </td>     \n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> \\ref ARM_USART_EVENT_TX_COMPLETE         </td><td>  3  </td><td> Occurs after call to \\ref ARM_USART_Send to indicate that all the data has been\n                                                                        physically transmitted on the wires. </td>\n  <td> data field \\em event_tx_complete = \\token{1} </td>\n</tr>\n<tr>\n  <td> \\ref ARM_USART_EVENT_TX_UNDERFLOW        </td><td>  4  </td><td> Occurs in synchronous slave mode when data is requested by the master but \n                                                                        send/receive/transfer operation has not been started. \n                                                                        Data field \\em  rx_underflow = \\token{1} of \\ref ARM_USART_STATUS. </td>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> \\ref ARM_USART_EVENT_RX_OVERFLOW         </td><td>  5  </td><td> Occurs when data is lost during receive/transfer operation or when data is lost \n                                                                        because receive operation in asynchronous mode or receive/send/transfer operation in \n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tsynchronous slave mode has not been started.\n                                                                        Data field \\em  rx_overflow = \\token{1} of \\ref ARM_USART_STATUS. </td>\n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> ARM_USART_EVENT_RX_TIMEOUT               </td><td>  6  </td><td> Occurs during receive when idle time is detected between consecutive characters \n                                                                        (idle time is hardware dependent).</td>     \n  <td> data field \\em event_rx_timeout = \\token{1}  </td>\n</tr>\n<tr>\n  <td> \\ref ARM_USART_EVENT_RX_BREAK            </td><td>  7  </td><td> Occurs when break is detected during receive. \n                                                                        Data field \\em  rx_break = \\token{1} of \\ref ARM_USART_STATUS. </td>     \n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> \\ref ARM_USART_EVENT_RX_FRAMING_ERROR    </td><td>  8  </td><td> Occurs when framing error is detected during receive. \n                                                                        Data field \\em  rx_framing_error = \\token{1} of \\ref ARM_USART_STATUS. </td>     \n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> \\ref ARM_USART_EVENT_RX_PARITY_ERROR     </td><td>  9  </td><td> Occurs when parity error is detected during receive.\n                                                                        Data field \\em  rx_parity_error = \\token{1} of \\ref ARM_USART_STATUS. </td>     \n  <td> <i>always supported</i> </td>\n</tr>\n<tr>\n  <td> ARM_USART_EVENT_CTS                      </td><td>  10 </td><td> Indicates that CTS modem line state has changed.\n                                                                        Data field \\em  cts of \\ref ARM_USART_MODEM_STATUS has changed. </td>     \n  <td> data field \\em event_cts = \\token{1} and <br>\n       data field \\em cts = \\token{1}           </td>\n</tr>\n<tr>\n  <td> ARM_USART_EVENT_DSR                      </td><td>  11 </td><td> Indicates that DSR modem line state has changed.\n                                                                        Data field \\em  dsr of \\ref ARM_USART_MODEM_STATUS has changed. </td>     \n  <td> data field \\em event_dsr = \\token{1} and <br>\n       data field \\em dsr = \\token{1}           </td>\n</tr>\n<tr>\n  <td> ARM_USART_EVENT_DCD                      </td><td>  12 </td><td> Indicates that DCD modem line state has changed.\n                                                                        Data field \\em  dcd of \\ref ARM_USART_MODEM_STATUS has changed. </td>     \n  <td> data field \\em event_dcd = \\token{1} and <br>\n       data field \\em dcd = \\token{1}           </td>\n</tr>\n<tr>\n  <td> ARM_USART_EVENT_RI                       </td><td>  13 </td><td> Indicates that RI modem line state has changed from active to inactive \n                                                                        (trailing edge on RI).\n                                                                        Data field \\em  ri of \\ref ARM_USART_MODEM_STATUS has changed from \\token{1} to \\token{0}. </td>     \n  <td> data field \\em event_ri = \\token{1} and  <br>\n       data field \\em ri = \\token{1}            </td>\n</tr>\n</table>\n*****************************************************************************************************************/\n\n/**\n@}\n*/ \n// End USART Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_USB.c",
    "content": "/**\n\\defgroup usb_interface_gr USB Interface\n\\brief   USB common definitions (%Driver_USB.h)\n\\details\nThe <b>Universal Serial Bus</b> (USB) implements a serial bus for data exchange. It is a host controlled, plug-and-play interface\nbetween a USB host and USB devices using a tiered star topology. \nIn microcontroller (MCU) applications, the interface is often used to connect a device to a host for data exchange or control purposes.\n\n - Wikipedia offers more information about the <a href=\"http://en.wikipedia.org/wiki/Universal_Serial_Bus\" target=\"_blank\"><b>Universal Serial Bus</b></a>.\n - The USB Implementers Forum provides detailed documentation under <a href=\"http://www.usb.org\"><b>www.usb.org</b></a>.\n\n\n<b>Block Diagram</b>\n\nTypically only one USB Device is connected to a USB Host. If several USB devices must be connected to the same USB host, then\nthe connection must be done via a USB hub.\n\n<p>\n\\image html USB_Schematics.png \"Simplified USB Schema\"\n</p>\n\n\n<b>USB API</b>\n\nThe following header files define the Application Programming Interface (API) for the USB interface:\n  - \\b %Driver_USB.h :  Common definitions of the USBD and USBH interface\n  - \\b %Driver_USBD.h : Driver API for USB Device Peripheral\n  - \\b %Driver_USBH.h : Driver API for USB Host Peripheral\n\nThe driver implementation is a typical part of the Device Family Pack (DFP) that supports the \nperipherals of the microcontroller family.\n\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_USBD : access struct for USBD driver functions\n  - \\ref ARM_DRIVER_USBH : access struct for USBH driver functions\n\n<hr>\n*/\n\n\n/**\n\\addtogroup usbd_interface_gr \n\\ingroup usb_interface_gr\n\\details\n\n<b>USB Device API</b>\n\nThe header file \\b Driver_USBD.h defines the API for the <b>USB Device Driver</b> interface used by middleware components.\nThe driver implementation itself is a typical part of the Device Family Pack, which provides entry points to the interface \nas function pointers in the struct \\ref ARM_DRIVER_USBD. This structure can be available several times in each interface to control multiple USBD interfaces.\n\nHeader file \\b Driver_USBD.h also defines callback routines that can be categorized as \n<b>device event callbacks</b> and <b>endpoint event callbacks</b>.\nCallbacks are called by the driver, in interrupt context when an appropriate event occurs, to signal device related events (\\ref USBD_dev_events)\nand endpoint related events (\\ref USBD_ep_events).\n\n\n<b>USB Device Function Call Sequence</b>\n\nTo use the USBD driver invoke the API functions in the following order:\n\n\\msc\n a [label=\"\", textcolor=\"indigo\", linecolor=\"indigo\", arclinecolor=\"red\"],\n b [label=\"\", textcolor=\"blue\", linecolor=\"blue\", arclinecolor=\"blue\"];\n\n a rbox a [label=\"Middleware\", linecolor=\"indigo\"],\n b rbox b [label=\"USBD Driver\", linecolor=\"blue\"];\n a=>b [label=\"ARM_USBD_Initialize\", URL=\"\\ref ARM_USBD_Initialize\"];\n a=>b [label=\"ARM_USBD_PowerControl (ARM_POWER_FULL)\", URL=\"\\ref ARM_USBD_Initialize\"];\n a=>b [label=\"ARM_USBD_DeviceConnect\", URL=\"\\ref ARM_USBD_DeviceConnect\"];\n a<=b [label=\"ARM_USBD_SignalDeviceEvent (ARM_USBD_EVENT_RESET)\", URL=\"\\ref ARM_USBD_SignalDeviceEvent\", linecolor=\"orange\"];\n a=>b [label=\"ARM_USBD_DeviceGetState\", URL=\"\\ref ARM_USBD_DeviceGetState\"];\n a=>b [label=\"ARM_USBD_EndpointConfigure\", URL=\"\\ref ARM_USBD_EndpointConfigure\", linecolor=\"green\"];\n --- [label=\"Repeat and use as needed\"];\n a=>b [label=\"ARM_USBD_EndpointTransfer\", URL=\"\\ref ARM_USBD_EndpointTransfer\", linecolor=\"green\"];\n a<=b [label=\"ARM_USBD_SignalEndpointEvent\", URL=\"\\ref ARM_USBD_SignalEndpointEvent\", linecolor=\"orange\"];\n a=>b [label=\"ARM_USBD_EndpointTransferGetResult\", URL=\"\\ref ARM_USBD_EndpointTransferGetResult\", linecolor=\"green\"];\n --- [label=\"Repeat End\"];\n a=>b [label=\"ARM_USBD_DeviceDisconnect\", URL=\"\\ref ARM_USBD_DeviceDisconnect\"];\n a=>b [label=\"ARM_USBD_PowerControl (ARM_POWER_OFF)\", URL=\"\\ref ARM_USBD_Initialize\"];\n a=>b [label=\"ARM_USBD_Uninitialize\", URL=\"\\ref ARM_USBD_Uninitialize\"];\n\\endmsc\n\n*/\n\n/**\n\\addtogroup usbh_interface_gr\n\\ingroup usb_interface_gr\n\\details\n<b>USB Host API</b>\n\nThe header file \\b Driver_USBH.h defines the API for the <b>USB Host Driver</b> interface used by middleware components.\nThe driver implementation itself is a typical part of the Device Family Pack, which provides entry points to the interface \nas function pointers in the struct \\ref ARM_DRIVER_USBH. This structure can be available several times in each interface to control multiple USBH interfaces.\n\n\\b Driver_USBH.h also defines callback routines, which are categorized in \n<b>port event callbacks</b> and <b>pipe event callbacks</b>.\nCallbacks are called by the driver, in interrupt context when an appropriate event occurs, to signal port related events (\\ref ARM_USBH_SignalPortEvent)\nand pipe related events (\\ref ARM_USBH_SignalPipeEvent). \n\n\\cond\n\n<b>USB Host Function Call Sequence</b>\n\nTo use the USBH driver invoke the API functions in the following order:\n\n\\msc\n a [label=\"\", textcolor=\"indigo\", linecolor=\"indigo\", arclinecolor=\"red\"],\n b [label=\"\", textcolor=\"blue\", linecolor=\"blue\", arclinecolor=\"blue\"];\n\n a rbox a [label=\"Middleware\", linecolor=\"indigo\"],\n b rbox b [label=\"USBH Driver\", linecolor=\"blue\"];\n a=>b [label=\"ARM_USBH_Initialize\", URL=\"\\ref ARM_USBD_Initialize\"];\n --- [label=\"Repeat and use as needed\"];\n --- [label=\"Repeat End\"];\n a=>b [label=\"ARM_USBH_Uninitialize\", URL=\"\\ref ARM_USBH_Uninitialize\"];\n\\endmsc\n\n <hr>\n\n\\endcond\n*/\n\n\n/**\n\\defgroup USB_speed USB Speed\n\\ingroup usb_interface_gr\n\\brief USB Speed definitions\n\\details\nThe following USB speed values are defined:\n@{\n\\def  ARM_USB_SPEED_LOW\n\\def  ARM_USB_SPEED_FULL\n\\def  ARM_USB_SPEED_HIGH\n@}\n*/\n\n/**\n\\defgroup USB_endpoint_type USB Endpoint Type\n\\ingroup usb_interface_gr\n\\brief USB Endpoint Type definitions\n\\details\nThe following USB Endpoint Type values are defined:\n@{\n\\def  ARM_USB_ENDPOINT_CONTROL\n\\def  ARM_USB_ENDPOINT_ISOCHRONOUS\n\\def  ARM_USB_ENDPOINT_BULK\n\\def  ARM_USB_ENDPOINT_INTERRUPT\n@}\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_USBD.c",
    "content": "/**\n\\defgroup   usbd_interface_gr USB Device Interface\n\\ingroup    usb_interface_gr\n\\brief      Driver API for USB Device Peripheral (%Driver_USBD.h)\n@{\n*/\n\n/** \n\\struct     ARM_DRIVER_USBD\n\\details\nThe functions of the USB Device driver are accessed by function pointers. Refer to \\ref DriverFunctions for \noverview information.\n\nEach instance of an USBD provides such an access struct. The instance is indicated by\na postfix in the symbol name of the access struct, for example:\n - \\b Driver_USBD0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_USBD1 is the name of the access struct of the second instance (no. 1).\n\n\nA configuration setting in the middleware allows connecting the middleware to a specific driver instance <b>Driver_USBD<i>n</i></b>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n\n\\note    The struct must remain unchanged.\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_USBD_CAPABILITIES \n\\details\nA USB Device driver can be implemented with different capabilities.\nThe data fields of this structure encode the capabilities implemented by this driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_USBD_GetCapabilities\n\n\\note    The struct must remain unchanged.\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_USBD_STATE \n\\details\nThis structure stores information about the state of the USB Device. The data fields encode the established speed,\nwhether the device is powered and active.\n\n<b>Returned by:</b>\n  - \\ref ARM_USBD_DeviceGetState\n*****************************************************************************************************************/\n\n/**\n\\typedef    ARM_USBD_SignalDeviceEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_USBD_SignalDeviceEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_USBD_Initialize\n*******************************************************************************************************************/\n\n/**\n\\typedef    ARM_USBD_SignalEndpointEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_USBD_SignalEndpointEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_USBD_Initialize\n*******************************************************************************************************************/\n\n/**\n\\defgroup USBD_dev_events USBD Device Events\n\\ingroup usbd_interface_gr\n\\brief The USB Device driver generates Device call back events that are notified via the function \\ref ARM_USBD_SignalDeviceEvent.\n\\details \nThis section provides the event values for the \\ref ARM_USBD_SignalDeviceEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def  ARM_USBD_EVENT_VBUS_ON\n\\def  ARM_USBD_EVENT_VBUS_OFF\n\\def  ARM_USBD_EVENT_RESET\n\\def  ARM_USBD_EVENT_HIGH_SPEED\n\\def  ARM_USBD_EVENT_SUSPEND\n\\def  ARM_USBD_EVENT_RESUME\n@}\n*/\n\n/**\n\\defgroup USBD_ep_events USBD Endpoint Events\n\\ingroup usbd_interface_gr\n\\brief The USB Device driver generates Endpoint call back events that are notified via the function \\ref ARM_USBD_SignalEndpointEvent.\n\\details \nThis section provides the event values for the \\ref ARM_USBD_SignalEndpointEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def  ARM_USBD_EVENT_SETUP\n\\def  ARM_USBD_EVENT_OUT\n\\def  ARM_USBD_EVENT_IN\n@}\n*/\n\n\n//\n// Functions\n//\n\nARM_DRIVER_VERSION ARM_USBD_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn     ARM_DRIVER_VERSION ARM_USBD_GetVersion (void)\n\\details\nThe function \\b ARM_USBD_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_USBD Driver_USBD0;\nARM_DRIVER_USBD *drv_info;\n \nvoid setup_usbd (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_USBD0;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*****************************************************************************************************************/\n\nARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void)  {\n  return { 0 };\n}\n/**\n\\fn       ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void)\n\\details\nThe function \\b ARM_USBD_GetCapabilities returns information about capabilities in this driver implementation.\nThe data fields of the structure \\ref ARM_USBD_CAPABILITIES encode various capabilities, for example\nif the hardware can create signal events using the \\ref ARM_USBD_SignalDeviceEvent callback function.\n \nExample:\n\\code\nextern ARM_DRIVER_USBD Driver_USBD0;\nARM_DRIVER_USBD *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_USBD_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_USBD0;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,\n                             ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t cb_device_event, ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)\n\\details\nThe function \\b ARM_USBD_Initialize initializes the USB Device interface. \nIt is called when the middleware component starts operation.\n\nThe function performs the following operations:\n  - Initializes the resources needed for the USBD interface.\n  - Registers the \\ref ARM_USBD_SignalDeviceEvent callback function.\n  - Registers the \\ref ARM_USBD_SignalEndpointEvent callback function.\n\nThe parameter \\em cb_device_event is a pointer to the \\ref ARM_USBD_SignalDeviceEvent callback function; use a NULL pointer \nwhen no device callback signals are required. \\n\nThe parameter \\em cb_endpoint_event is a pointer to the \\ref ARM_USBD_SignalEndpointEvent callback function.\n\n\\b Example:\n - see \\ref usbd_interface_gr - Driver Functions\n\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_Uninitialize (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_USBD_Uninitialize (void)\n\\details\nThe function \\b ARM_USBD_Uninitialize de-initializes the resources of USBD interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_PowerControl (ARM_POWER_STATE state)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_USBD_PowerControl operates the power modes of the USB Device interface.  \n\nThe parameter \\em state sets the operation and can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. \n                          Can be called multiple times. If the peripheral is already in this mode the function performs \n\t\t\t\t\t\t  no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_DeviceConnect (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_DeviceConnect (void)\n\\details\nThe function \\b ARM_USBD_DeviceConnect signals to the host that the device is connected.\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_DeviceDisconnect (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_DeviceDisconnect (void)\n\\details\nThe function \\b ARM_USBD_DeviceDisconnect signals to the host that the device is disconnected.\n*****************************************************************************************************************/\n\nARM_USBD_STATE ARM_USBD_DeviceGetState (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn ARM_USBD_STATE ARM_USBD_DeviceGetState (void)\n\\details\nRetrieves the current USB device state.\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_DeviceRemoteWakeup (void)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_DeviceRemoteWakeup (void)\n\\details\nThe function \\b ARM_USBD_DeviceRemoteWakeup signals remote wakeup to the host.\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr)\n\\details\nAssigns an address to the device.\n\\note This function is called after status stage of the Set Address request (after IN packet in status stage was sent with the old address).\n\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_ReadSetupPacket (uint8_t *setup)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup)\n\\details\nThe function \\b ARM_USBD_ReadSetupPacket reads the last SETUP packet (8 bytes) that was received over Control Endpoint (Endpoint 0)\nwhich is indicated by \\ref ARM_USBD_EVENT_SETUP event.\n\n<b>See also:</b>\n - \\ref ARM_USBD_SignalEndpointEvent\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_EndpointConfigure (uint8_t  ep_addr,\n                                    uint8_t  ep_type,\n                                    uint16_t ep_max_packet_size)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_EndpointConfigure (uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size)\n\\details       \nThe function \\b ARM_USBD_EndpointConfigure configures an endpoint for transfers.\n\n\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr)\n\\details\nThe function \\b ARM_USBD_EndpointUnconfigure de-configures the specified endpoint.\n\nThe parameter \\em ep_addr specifies the endpoint address. \n*****************************************************************************************************************/\n\nint32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall)\n\\details\nThe function \\b ARM_USBD_EndpointStall sets or clears stall condition for the specified endpoint.\n\nThe parameter \\em ep_addr specifies the endpoint address. \\n\nThe parameter \\em stall is a boolean parameter.\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)\n\\details\n\nThe function \\b ARM_USBD_EndpointTransfer reads from or writes data to an USB Endpoint.\n\nThe parameter \\em ep_addr specifies the endpoint address. \\n\nThe parameter \\em data is a buffer for data to read or data to write. \\n\nThe parameter \\em num is the number of bytes to transfer (must be multiple of endpoint maximum packet size for Read transfers).\n\nThe function is non-blocking and returns as soon as the driver starts the operation on the specified endpoint. \nDuring the operation it is not allowed to call this function again on the same endpoint. \nAlso the data buffer must stay allocated and the contents of data must not be modified.\n\nDirection in the endpoint address specifies the type of transfer:\n- Endpoint Read for OUT endpoint (direction = 0)\n- Endpoint Write for IN endpoint (direction = 1)\n\nEndpoint Read is finished when the requested number of data bytes have been received or when a short packet or ZLP (Zero-Length Packet) has been received.\nCompletion of operation is indicated by \\ref ARM_USBD_EVENT_OUT event. Number of successfully received data bytes can be retrieved \nby calling \\ref ARM_USBD_EndpointTransferGetResult.\n\nEndpoint Write is finished when the requested number of data bytes have been sent.\nCompletion of operation is indicated by \\ref ARM_USBD_EVENT_IN event. Number of successfully sent data bytes can be retrieved \nby calling \\ref ARM_USBD_EndpointTransferGetResult.\n\nTransfer operation can be aborted by calling \\ref ARM_USBD_EndpointTransferAbort.\n*****************************************************************************************************************/\n\nuint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr)  {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr)\n\\details\nThe function \\b ARM_USBD_EndpointTransferGetResult returns the number of successfully transferred data bytes started by \\ref ARM_USBD_EndpointTransfer.\n\nThe parameter \\em ep_addr specifies the endpoint address.\n*****************************************************************************************************************/\n\nint32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr)\n\\details\nThe function \\b ARM_USBD_EndpointTransferAbort aborts the transfer to an endpoint started by \\ref ARM_USBD_EndpointTransfer.\n\nThe parameter \\em ep_addr specifies the endpoint address.\n*****************************************************************************************************************/\n\nuint16_t ARM_USBD_GetFrameNumber (void)  {\n  return 0;\n}\n/**\n\\fn uint16_t ARM_USBD_GetFrameNumber (void)\n\\details\nRetrieves the sequential 11-bit frame number of the last Start of Frame (SOF) packet.\n*****************************************************************************************************************/\n\nvoid ARM_USBD_SignalDeviceEvent (uint32_t event)  {\n  // function body\n}\n/**\n\\fn void ARM_USBD_SignalDeviceEvent (uint32_t event)\n\\details\nThe function \\b ARM_USBD_SignalDeviceEvent is a callback function registered by the function \\ref ARM_USBD_Initialize. \n\nThe parameter \\em event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nNot every event is necessarily generated by the driver. This depends on the implemented capabilities stored in the \ndata fields of the structure \\ref ARM_USBD_CAPABILITIES, which can be retrieved with the function \\ref ARM_USBD_GetCapabilities.\n\nThe following events can be generated:\n\nEvent                           | Bit| Description                                        | supported when \\ref ARM_USBD_CAPABILITIES\n:-------------------------------|---:|:---------------------------------------------------|----------------------------------------------\n\\ref ARM_USBD_EVENT_VBUS_ON     | 0  | Occurs when valid VBUS voltage is detected.        | data field \\em  event_vbus_on = \\token{1}\n\\ref ARM_USBD_EVENT_VBUS_OFF    | 1  | Occurs when VBUS voltage is turned off.            | data field \\em  event_vbus_off = \\token{1}\n\\ref ARM_USBD_EVENT_RESET       | 2  | Occurs when USB Reset is detected.                 | <i>always supported</i>\n\\ref ARM_USBD_EVENT_HIGH_SPEED  | 3  | Occurs when USB Device is switched to High-speed.  | <i>always supported</i>\n\\ref ARM_USBD_EVENT_SUSPEND     | 4  | Occurs when USB Suspend is detected.               | <i>always supported</i>\n\\ref ARM_USBD_EVENT_RESUME      | 5  | Occurs when USB Resume is detected.                | <i>always supported</i>\n*****************************************************************************************************************/\n\nvoid ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t ep_event)  {\n  // function body\n}\n/**\n\\fn void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event)\n\\details\nThe function \\b ARM_USBD_SignalEndpointEvent is a callback function registered by the function \\ref ARM_USBD_Initialize. \n\nThe argument \\a ep_addr specifies the endpoint. \\n\nThe parameter \\em event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nThe following events can be generated:\n\nEvent                                    | Bit | Description \n:----------------------------------------|----:|:-----------\n\\ref ARM_USBD_EVENT_SETUP                |  0  | Occurs when SETUP packet is received over Control Endpoint.\n\\ref ARM_USBD_EVENT_OUT                  |  1  | Occurs when data is received over OUT Endpoint.\n\\ref ARM_USBD_EVENT_IN                   |  2  | Occurs when data is sent over IN Endpoint.\n*****************************************************************************************************************/\n\n/**\n@}\n*/ \n// End USBD Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_USBH.c",
    "content": "/**\n\\defgroup usbh_interface_gr USB Host Interface\n\\ingroup usb_interface_gr\n\\brief  Driver API for USB Host Peripheral (%Driver_USBH.h)\n*/\n\n/**\n\\defgroup usbh_host_gr USB Host\n\\ingroup usbh_interface_gr\n\\brief  Driver API for USB Host\n\n@{\n*/\n\n/** \n\\struct ARM_DRIVER_USBH\n\\details \nThe functions of the USB Host driver are accessed by function pointers. Refer to \\ref DriverFunctions for \noverview information.\n\nEach instance of an USBH provides such an access struct. The instance is indicated by\na postfix in the symbol name of the access struct, for example:\n - \\b Driver_USBH0 is the name of the access struct of the first instance (no. 0).\n - \\b Driver_USBH1 is the name of the access struct of the second instance (no. 1).\n\n\nA configuration setting in the middleware allows connecting the middleware to a specific driver instance <b>Driver_USBH<i>n</i></b>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n\n\\note    The struct must remain unchanged.\n*****************************************************************************************************************/\n\n/**\n\\struct ARM_USBH_CAPABILITIES \n\\details  \nA USB Host driver can be implemented with different capabilities.\nThe data fields of this structure encode the capabilities implemented by this driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_USBH_GetCapabilities\n\n\\note    The struct must remain unchanged.\n*****************************************************************************************************************/\n\n/**\n\\struct     ARM_USBH_PORT_STATE \n\\details  \nThis structure stores information about the state of the USB Host Port. The data fields encode whether a device \nis connected to the port, if port overcurrent is detected, and the port speed.\n\n<b>Returned by:</b>\n  - \\ref ARM_USBH_PortGetState\n*****************************************************************************************************************/\n\n/**\n\\typedef    uint32_t ARM_USBH_PIPE_HANDLE\n\\details \nEach pipe is identified through a unique number, which is created by the function \\ref ARM_USBH_PipeCreate.\n\n<b>Parameter for:</b>\n - \\ref ARM_USBH_PipeModify,\n   \\ref ARM_USBH_PipeDelete,\n   \\ref ARM_USBH_PipeReset,\n   \\ref ARM_USBH_PipeTransfer,\n   \\ref ARM_USBH_PipeTransferGetResult,\n   \\ref ARM_USBH_PipeTransferAbort,\n   \\ref ARM_USBH_SignalPipeEvent\n\n<b>Retruned by:</b>\n - \\ref ARM_USBH_PipeCreate\n*****************************************************************************************************************/\n\n/**\n\\typedef    ARM_USBH_SignalPortEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_USBH_SignalPortEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_USBH_Initialize\n*******************************************************************************************************************/\n\n/**\n\\typedef    ARM_USBH_SignalPipeEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_USBH_SignalPipeEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_USBH_Initialize\n*******************************************************************************************************************/\n\n/**\n\\defgroup USBH_port_events USBH Port Events\n\\ingroup usbh_host_gr\n\\brief The USB Host driver generates Port call back events that are notified via the function \\ref ARM_USBH_SignalPortEvent.\n\\details \nThis section provides the event values for the \\ref ARM_USBH_SignalPortEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def  ARM_USBH_EVENT_CONNECT\n\\def  ARM_USBH_EVENT_DISCONNECT\n\\def  ARM_USBH_EVENT_OVERCURRENT\n\\def  ARM_USBH_EVENT_RESET\n\\def  ARM_USBH_EVENT_SUSPEND\n\\def  ARM_USBH_EVENT_RESUME\n\\def  ARM_USBH_EVENT_REMOTE_WAKEUP\n@}\n*/\n\n/**\n\\defgroup USBH_pipe_events USBH Pipe Events\n\\ingroup usbh_host_gr\n\\brief The USB Host driver generates Pipe call back events that are notified via the function \\ref ARM_USBH_SignalPipeEvent.\n\\details \nThis section provides the event values for the \\ref ARM_USBH_SignalPipeEvent callback function.\n\nThe following call back notification events are generated:\n@{\n\\def  ARM_USBH_EVENT_TRANSFER_COMPLETE\n\\def  ARM_USBH_EVENT_HANDSHAKE_NAK\n\\def  ARM_USBH_EVENT_HANDSHAKE_NYET\n\\def  ARM_USBH_EVENT_HANDSHAKE_MDATA\n\\def  ARM_USBH_EVENT_HANDSHAKE_STALL\n\\def  ARM_USBH_EVENT_HANDSHAKE_ERR\n\\def  ARM_USBH_EVENT_BUS_ERROR\n@}\n*/\n\n/**\n\\defgroup USBH_packets USBH Packet Information\n\\ingroup usbh_host_gr\n\\brief Specify USB packet information used by the function \\ref ARM_USBH_PipeTransfer\n\\details \nThis section provides the packet information values (parameter \\em packet) for the \\ref ARM_USBH_PipeTransfer function.\n\nThe following values are defined:\n@{\n\\def  ARM_USBH_PACKET_SETUP\nGenerate SETUP transaction.\n\\def  ARM_USBH_PACKET_OUT\nGenerate OUT transaction.\n\\def  ARM_USBH_PACKET_IN\nGenerate IN transaction.\n\\def  ARM_USBH_PACKET_PING\nGenerate PING transaction (no data packet).\n\\def  ARM_USBH_PACKET_DATA0\nForce DATA0 PID (Packet Identifier) for the initial data packet. When not specified than the driver provides the initial value according to the current state.\n\\def  ARM_USBH_PACKET_DATA1\nForce DATA1 PID (Packet Identifier) for the initial data packet. When not specified than the driver provides the initial value according to the current state.\n\\def  ARM_USBH_PACKET_SSPLIT\nUsed when driver does not support automatic handling of SPLIT packets and indicates Start-Split packet.\nFor isochronous OUT it indicates that the High-speed data is in the middle of the Full-speed data payload.\n\\def  ARM_USBH_PACKET_SSPLIT_S\nUsed when driver does not support automatic handling of SPLIT packets and indicates Start-Split packet.\nValid only for isochronous OUT and indicates that the High-speed data is the start of the Full-speed data payload.\n\\def  ARM_USBH_PACKET_SSPLIT_E\nUsed when driver does not support automatic handling of SPLIT packets and indicates Start-Split packet.\nValid only for isochronous OUT and indicates that the High-speed data is the end of the Full-speed data payload.\n\\def  ARM_USBH_PACKET_SSPLIT_S_E\nUsed when driver does not support automatic handling of SPLIT packets and indicates Start-Split packet.\nValid only for isochronous OUT and indicates that the High-speed data is all of the Full-speed data payload.\n\\def  ARM_USBH_PACKET_CSPLIT\nUsed when driver does not support automatic handling of SPLIT packets and indicates Complete-Split packet.\n\\def  ARM_USBH_PACKET_PRE\nGenerate PRE (Preamble) for low-speed devices within a full/low-speed signaling environment. \n@}\n*/\n\n\n//\n// Functions\n//\n\nARM_DRIVER_VERSION ARM_USBH_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn       ARM_DRIVER_VERSION ARM_USBH_GetVersion (void)\n\\details\nThe function \\b ARM_USBH_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_USBH Driver_USBH0;\nARM_DRIVER_USBH *drv_info;\n \nvoid setup_usbh (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_USBH0;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*****************************************************************************************************************/\n\nARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void)  {\n  return { 0 };\n}\n/**\n\\fn       ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void)\n\\details\nThe function \\b ARM_USBH_GetCapabilities returns information about capabilities in this driver implementation.\nThe data fields of the structure \\ref ARM_USBH_CAPABILITIES encode various capabilities, for example\navailable HUB ports or if the hardware can generate signal events using the \\ref ARM_USBH_SignalPortEvent \ncallback function.\n \nExample:\n\\code\nextern ARM_DRIVER_USBH Driver_USBH0;\nARM_DRIVER_USBH *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_USBH_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_USBH0;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event,\n                             ARM_USBH_SignalPipeEvent_t cb_pipe_event)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event, ARM_USBH_SignalPipeEvent_t cb_pipe_event)\n\\details\nThe function \\b ARM_USBH_Initialize initializes the USB Host interface. \nIt is called when the middleware component starts operation.\n\nThe function performs the following operations:\n  - Initializes the resources needed for the USBH interface.\n  - Registers the \\ref ARM_USBH_SignalPortEvent callback function.\n  - Registers the \\ref ARM_USBH_SignalPipeEvent callback function.\n\nThe parameter \\em cb_port_event is a pointer to the \\ref ARM_USBH_SignalPortEvent callback function; use a NULL pointer \nwhen no port callback signals are required.\n\nThe parameter \\em cb_pipe_event is a pointer to the \\ref ARM_USBH_SignalPipeEvent callback function.\n\n\\b Example:\n - see \\ref usbh_interface_gr - Driver Functions\n\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_Uninitialize (void) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_USBH_Uninitialize (void)\n\\details\nThe function \\b ARM_USBH_Uninitialize de-initializes the resources of USB Host interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PowerControl (ARM_POWER_STATE state)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_USBH_PowerControl operates the power modes of the USB Host interface. \n\nThe parameter \\em state sets the operation and can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. \n                          Can be called multiple times. If the peripheral is already in this mode the function performs \n\t\t\t\t\t\t  no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus)\n\\details\nThe function \\b ARM_USBH_PortVbusOnOff controls the VBUS signal of the specified port.  \n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PortReset (uint8_t port)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PortReset (uint8_t port)\n\\details\nExecutes reset signalling on the specified port.\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PortSuspend (uint8_t port)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PortSuspend (uint8_t port)\n\\details\nThe function \\b ARM_USBH_PortSuspend auspends USB signaling on the specified port.\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PortResume (uint8_t port)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PortResume (uint8_t port)\n\\details\nThe function \\b ARM_USBH_PortResume resumes USB signaling on the specified port.\n*****************************************************************************************************************/\n\nARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port)  {\n  return 0;\n}\n/**\n\\fn ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port)\n\\details\nThe function \\b ARM_USBH_PortGetState returns the current state of the specified port.\n*****************************************************************************************************************/\n\nARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t  dev_addr,\n                                          uint8_t  dev_speed,\n                                          uint8_t  hub_addr,\n                                          uint8_t  hub_port,\n                                          uint8_t  ep_addr,\n                                          uint8_t  ep_type,\n                                          uint16_t ep_max_packet_size,\n                                          uint8_t  ep_interval)  {\n  return 0;\n}\n/**\n\\fn ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t dev_addr, uint8_t dev_speed, uint8_t hub_addr, uint8_t hub_port, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size, uint8_t ep_interval)\n\\details\nThe function \\b ARM_USBH_PipeCreate creates a pipe for transfers (allocates required resources and configures the pipe).\n\nThe parameters specify pipe information (connection between host and device endpoint):\n - device: address and speed\n - hub (optional): hub address and number of the hub port to which the device is connected \n - endpoint: address, type, maximum packet size and polling interval\n\nThe function returns an pipe handle that is used for all subsequent operations on that pipe.\nIn case of errors an invalid handle (\\em NULL) is returned.   \n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl,\n                             uint8_t              dev_addr,\n                             uint8_t              dev_speed,\n                             uint8_t              hub_addr,\n                             uint8_t              hub_port,\n                             uint16_t             ep_max_packet_size)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl, uint8_t dev_addr, uint8_t dev_speed, uint8_t hub_addr, uint8_t hub_port, uint16_t ep_max_packet_size)\n\\details\nThe function \\b ARM_USBH_PipeModify modifies a pipe configuration that was created with \\ref ARM_USBH_PipeCreate.\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl)\n\\details\nThe function \\b ARM_USBH_PipeDelete deletes a pipe that was created with \\ref ARM_USBH_PipeCreate (deactivates the pipe and releases used resources).\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl)\n\\details\nThe function \\b ARM_USBH_PipeReset clears Halt condition and resets data toggle on the specified pipe.\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl,\n                               uint32_t packet,       \n                               uint8_t *data,\n                               uint32_t num)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t packet, uint8_t *data, uint32_t num)\n\\details\nThe function \\b ARM_USBH_PipeTransfer generates packets for sending or receiving data from an USB Endpoint.\n\nThe function specifies the buffer with data to send or for data to receive and the number of bytes to transfer (must be multiple of device endpoint maximum packet size for receive).\nIt also specifies \\ref USBH_packets with parameter \\em packet.\n\nThe function is non-blocking and returns as soon as the driver starts the operation on the specified pipe. During the operation it is not allowed to call this function again on the same pipe. Also the data buffer must stay allocated and the contents of data must not be modified.\n\nOperation is completed when the the requested number of data bytes have been transferred and is indicated with \\ref ARM_USBH_EVENT_TRANSFER_COMPLETE event.\nIt can also finish earlier on reception of different handshake tokens which are also indicated through \\ref USBH_pipe_events.\n \nTransfer operation can be aborted by calling \\ref ARM_USBH_PipeTransferAbort.\n*****************************************************************************************************************/\n\nuint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl)  {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl)\n\\details       \nThe function \\b ARM_USBH_PipeTransferGetResult returns the number of successfully transferred data bytes started by \\ref ARM_USBH_PipeTransfer operation.\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl)\n\\details\n\nThe function \\b ARM_USBH_PipeTransferAbort aborts an active pipe transfer started by \\ref ARM_USBH_PipeTransfer.\n*****************************************************************************************************************/\n\nuint16_t ARM_USBH_GetFrameNumber (void)  {\n  return 0;\n}\n/**\n\\fn uint16_t ARM_USBH_GetFrameNumber (void)\n\\details\nThe function \\b ARM_USBH_GetFrameNumber returns the sequential 11-bit frame number of the last Start of Frame (SOF) packet.\n*****************************************************************************************************************/\n\nvoid ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event)  {\n  // function body\n}\n/**\n\\fn void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event)\n\\details\nThe function \\b ARM_USBH_SignalPortEvent is a callback function registered by the function \\ref ARM_USBH_Initialize. \n\nThe parameter \\em port specifies the root hub port number. \\n\nThe parameter \\em event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nNot every event is necessarily generated by the driver. This depends on the implemented capabilities stored in the \ndata fields of the structure \\ref ARM_USBH_CAPABILITIES, which can be retrieved with the function \\ref ARM_USBH_GetCapabilities.\n\nThe following events can be generated:\n\nParameter \\em event               | Bit | Description                                                                | supported when ARM_USBH_CAPABILITIES\n:---------------------------------|:---:|:---------------------------------------------------------------------------|---------------------------------------\n\\ref ARM_USBH_EVENT_CONNECT       |  0  | Occurs when USB Device connects to the Host.                               | data field \\em event_connect=\\token{1}\n\\ref ARM_USBH_EVENT_DISCONNECT    |  1  | Occurs when USB Device disconnects from the Host.                          | data field \\em event_disconnect=\\token{1}\n\\ref ARM_USBH_EVENT_OVERCURRENT   |  2  | Occurs when USB Overcurrent it detected.                                   | data field \\em event_overcurrent=\\token{1}\n\\ref ARM_USBH_EVENT_RESET         |  3  | Occurs when USB Reset is completed after calling \\ref ARM_USBH_PortReset.  | <i>always supported</i>\n\\ref ARM_USBH_EVENT_SUSPEND       |  4  | Occurs when USB Suspend is detected.                                       | <i>always supported</i>\n\\ref ARM_USBH_EVENT_RESUME        |  5  | Occurs when USB Resume is detected.                                        | <i>always supported</i>\n\\ref ARM_USBH_EVENT_REMOTE_WAKEUP |  6  | Occurs when USB Remote wakeup is detected.                                 | <i>always supported</i>\n*****************************************************************************************************************/\n\nvoid ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)  {\n  // function body\n}\n/**\n\\fn void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)\n\\details\nThe function \\b ARM_USBH_SignalPipeEvent is a callback function registered by the function \\ref ARM_USBH_Initialize. \n\nThe parameter \\em pipe_hndl specifies the pipe handle. \\n\nThe parameter \\em event indicates one or more events that occurred during driver operation.\nEach event is encoded in a separate bit and therefore it is possible to signal multiple events within the same call. \n\nThe following events can be generated:\n\nParameter \\em event                       | Bit| Description \n:-----------------------------------------|---:|:-----------\n\\ref ARM_USBH_EVENT_TRANSFER_COMPLETE     | 0  | Occurs after all the data has been transferred without errors.\n\\ref ARM_USBH_EVENT_HANDSHAKE_NAK         | 1  | Occurs when NAK Handshake is received before all the data is transferred.\n\\ref ARM_USBH_EVENT_HANDSHAKE_NYET        | 2  | Occurs when NYET Handshake is received before all the data is transferred.\n\\ref ARM_USBH_EVENT_HANDSHAKE_MDATA       | 3  | Occurs when MDATA Handshake is received before all the data is transferred.\n\\ref ARM_USBH_EVENT_HANDSHAKE_STALL       | 4  | Occurs when STALL Handshake is received before all the data is transferred.\n\\ref ARM_USBH_EVENT_HANDSHAKE_ERR         | 5  | Occurs when ERR Handshake is received before all the data is transferred.\n\\ref ARM_USBH_EVENT_BUS_ERROR             | 6  | Occurs when bus error is detected before all the data is transferred.\n\n<b>See also:</b>\n - ARM_USBH_PipeCreate\n*****************************************************************************************************************/\n\n/**\n@}\n*/ \n\n\n\n/**\n\\defgroup usbh_hci_gr USB OHCI/EHCI\n\\ingroup usbh_interface_gr\n\\brief  Driver API for USB OHCI/EHCI\n\\details\nOHCI and EHCI compliant interfaces have memory mapped registers that are used to control the USB host.\n\nOnly certain functionalities (interrupts, VBUS control, power control) require device specific interface which is provided through functions\nof the struct \\ref ARM_DRIVER_USBH_HCI (functionality accessed with the struct \\ref ARM_DRIVER_USBH is not needed). \n@{\n*/\n\n/** \n\\struct ARM_DRIVER_USBH_HCI\n\\details\nThe functions of the USB Host HCI (OHCI/EHCI) driver are accessed by function pointers. Refer to \\ref DriverFunctions for \noverview information.\n\nEach instance of an USBH provides such an access struct. The instance is indicated by\na postfix in the symbol name of the access struct, for example:\n - \\b Driver_USBH0_HCI is the name of the access struct of the first instance (no. 0).\n - \\b Driver_USBH1_HCI is the name of the access struct of the second instance (no. 1).\n\n\nA configuration setting in the middleware allows connecting the middleware to a specific driver instance <b>Driver_USBH<i>n</i>_HCI</b>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n\n\\note    The struct must remain unchanged.\n*/\n\n\n/**\n\\struct ARM_USBH_HCI_CAPABILITIES\n\\details\nA USB Host HCI (OHCI/EHCI) driver can be implemented with different capabilities.\nThe data fields of this structure encode the capabilities implemented by this driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_USBH_HCI_GetCapabilities\n\n\\note    The struct must remain unchanged.\n*****************************************************************************************************************/\n\n/**\n\\typedef    ARM_USBH_HCI_Interrupt_t\n\\details\nProvides the typedef for the interrupt handler \\ref ARM_USBH_HCI_Interrupt.\n\n<b>Parameter for:</b>\n  - \\ref ARM_USBH_HCI_Initialize\n*******************************************************************************************************************/\n\n\n//\n// Functions\n//\n\nARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void)  {\n  return { 0, 0 };\n}\n/**\n\\fn       ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void)\n\\details\nThe function \\b ARM_USBH_HCI_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION\n - API version is the version of the CMSIS-Driver specification used to implement this driver.\n - Driver version is source code version of the actual driver implementation.\n\nExample:\n\\code\nextern ARM_DRIVER_USBH Driver_USBH0_HCI;\nARM_DRIVER_USBH *drv_info;\n \nvoid setup_usbh (void)  {\n  ARM_DRIVER_VERSION  version;\n \n  drv_info = &Driver_USBH0_HCI;  \n  version = drv_info->GetVersion ();\n  if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*****************************************************************************************************************/\n\nARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void)  {\n  return { 0 };\n}\n/**\n\\fn       ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void)\n\\details\nThe function \\b ARM_USBH_HCI_GetCapabilities returns information about capabilities in this driver implementation.\nThe data fields of the structure \\ref ARM_USBH_HCI_CAPABILITIES encode various capabilities, for example\navailable HUB ports.\n \nExample:\n\\code\nextern ARM_DRIVER_USBH_HCI Driver_USBH0_HCI;\nARM_DRIVER_USBH_HCI *drv_info;\n  \nvoid read_capabilities (void)  {\n  ARM_USBH_HCI_CAPABILITIES drv_capabilities;\n \n  drv_info = &Driver_USBH0_HCI;  \n  drv_capabilities = drv_info->GetCapabilities ();\n  // interrogate capabilities\n \n}\n\\endcode\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)\n\\details\nThe function \\b ARM_USBH_HCI_Initialize initializes the USB Host HCI (OHCI/EHCI) interface. \nIt is called when the middleware component starts operation.\n\nThe function performs the following operations:\n  - Initializes the resources needed for the USBH interface.\n  - Registers the \\ref ARM_USBH_HCI_Interrupt interrupt handler.\n\nThe parameter \\em cb_interrupt is a pointer to the interrupt routine of the OHCI/EHCI peripheral\nthat needs to be registered. This function is called as ECHI Interrupt Service Handler.\n\n\\b Example:\n - see \\ref usbh_interface_gr - Driver Functions\n\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_HCI_Uninitialize (void) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn       int32_t ARM_USBH_HCI_Uninitialize (void)\n\\details\nThe function \\ref ARM_USBH_HCI_Uninitialize de-initializes the resources of USB Host HCI (OHCI/EHCI) interface.\n\nIt is called when the middleware component stops operation and releases the software resources used by the interface.\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_USBH_HCI_PowerControl operates the power modes of the USB Host HCI (OHCI/EHCI) interface.  \n\nThe parameter \\em state sets the operation and can have the following values:\n  - \\ref ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts (NVIC) and optionally DMA. \n                          Can be called multiple times. If the peripheral is already in this mode the function performs \n\t\t\t\t\t\t  no operation and returns with \\ref ARM_DRIVER_OK.\n  - \\ref ARM_POWER_LOW : may use power saving. Returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.\n  - \\ref ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.\n      \nRefer to \\ref CallSequence for more information.\n*****************************************************************************************************************/\n\nint32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)  {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)\n\\details\nThe function \\b  ARM_USBH_HCI_PortVbusOnOff controls the VBUS signal of the specified port.\nMost HCI complained USB Host controllers do not require this optional function.\nIt is only required when a external VBUS interface (for example via I/O pin) is required.\n\n*****************************************************************************************************************/\n\nvoid ARM_USBH_HCI_Interrupt (void)  {\n  // function body\n}\n/**\n\\fn void ARM_USBH_HCI_Interrupt (void)\n\\details\nThe function \\b ARM_USBH_HCI_Interrupt is called from the USBH HCI Interrupt Handler.\n*****************************************************************************************************************/\n\n/**\n@}\n*/ \n// End USBH Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Driver_WiFi.c",
    "content": "/**\n\\defgroup wifi_interface_gr WiFi Interface\n\\brief Driver API for WiFi (%Driver_WiFi.h)\n\\details \n\nWi-Fi is technology for radio wireless local area networking of devices. Wi-Fi compatible devices typically\nconnect to the Internet via a WLAN and a wireless access point (AP) also called hotspot.\n\nWikipedia offers more information about \nthe <a href=\"http://en.wikipedia.org/wiki/Ethernet\" target=\"_blank\"><b>WiFi</b></a>.\n\n<b>Driver Block Diagram</b>\n\n\\image html WiFi.png  \"Block Diagram of the WiFi interface\"\n\n<b>WiFi API</b>\n\nThe following header files define the Application Programming Interface (API) for the WiFi interface:\n  - \\b %Driver_WiFi.h : Driver API for WiFi\n\nThe CMSIS-Driver WiFi provides access to the following interfaces:\n\n - \\ref wifi_control_gr \"Control interface\": setup and control the WiFi module.\n - \\ref wifi_management_gr \"Management interface\": allows you to configure and manage the connection\n   to the WiFi access point (AP) or configure and manage the access point (AP).\n - \\ref wifi_socket_gr \"Socket interface\": provides the interface to an IP stack that is running\n   on the WiFi module. This IP stack handles data communication.\n - \\ref wifi_bypass_gr \"Bypass interface\": is an optional interface and enables the transmission of\n   Ethernet frames with the WiFi module. Using this interface requires the IP stack running on the microcontroller.\n\nThe WiFi interface usually requires CMSIS-RTOS features (i.e. mutex) and is often implemented\nwith a peripheral device that is connected to the system using the SPI or UART interface. However,\nthere are also some microcontroller devices with WiFi interface on the chip.\n\nThe implementation of the WiFi CMSIS-Driver is therefore generally provided as a separate software pack.\nIt is often implemented as wrapper to the SDK (Software Development Kit) of the WiFi chipset.\n\n\n<b>Driver Functions</b>\n\nThe driver functions are published in the access struct as explained in \\ref DriverFunctions\n  - \\ref ARM_DRIVER_WIFI : access struct for WiFi driver functions\n\n\n<b>Example Code</b>\n\n@{\n*/\n\n/**\n\\struct  ARM_DRIVER_WIFI\n\\details \nThe functions of the WiFi driver are accessed by function pointers exposed by this structure.\nRefer to \\ref DriverFunctions for overview information.\n\nEach instance of a WiFi interface provides such an access structure. \nThe instance is identified by a postfix number in the symbol name of the access structure, for example:\n - \\b Driver_WiFi0 is the name of the access struct of the first instance (no. \\token{0}).\n - \\b Driver_WiFi1 is the name of the access struct of the second instance (no. \\token{1}).\n\nA middleware configuration setting allows connecting the middleware to a specific driver instance \\b %Driver_WiFi<i>n</i>.\nThe default is \\token{0}, which connects a middleware to the first instance of a driver.\n*******************************************************************************************************************/\n\n\n/**\n\\defgroup wifi_control_gr WiFi Control\n\\ingroup wifi_interface_gr\n\\brief Control functions for the WiFi module\n\\details  \nThe \\ref wifi_control_gr functions setup and control the WiFi module.\n@{\n*/\n\n/** \n\\struct  ARM_WIFI_CAPABILITIES\n\\details\nA WiFi driver can be implemented with different capabilities.\nThe data fields of this structure encode the capabilities implemented by this driver.\n\n<b>Returned by:</b>\n  - \\ref ARM_WIFI_GetCapabilities\n*******************************************************************************************************************/\n\n/**\n\\typedef ARM_WIFI_SignalEvent_t\n\\details\nProvides the typedef for the callback function \\ref ARM_WIFI_SignalEvent.\n\n<b>Parameter for:</b>\n  - \\ref ARM_WIFI_Initialize\n*******************************************************************************************************************/\n\n/**\n\\defgroup wifi_event WiFi Events\n\\ingroup wifi_control_gr\n\\brief The WiFi driver generates call back events that are notified via the function \\ref ARM_WIFI_SignalEvent.\n\\details The following call back notification events are generated:\n@{\n\\def ARM_WIFI_EVENT_AP_CONNECT\n\\def ARM_WIFI_EVENT_AP_DISCONNECT\n\\def ARM_WIFI_EVENT_ETH_RX_FRAME\n@}\n*/\n\nARM_DRIVER_VERSION ARM_WIFI_GetVersion (void) {\n  return { 0, 0 };\n}\n/**\n\\fn ARM_DRIVER_VERSION ARM_WIFI_GetVersion (void)\n\\details\nThe function \\b ARM_WIFI_GetVersion returns version information of the driver implementation in \\ref ARM_DRIVER_VERSION.\n\nAPI version is the version of the CMSIS-Driver specification used to implement this driver.\nDriver version is source code version of the actual driver implementation.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\n \nvoid get_wifi_version (void)  {\n  ARM_DRIVER_VERSION version;\n \n  wifi= &Driver_WiFi0;  \n  version = wifi->GetVersion ();\n  if (version.api < 0x100U) {        // requires at minimum API version 1.0 or higher\n    // error handling\n    return;\n  }\n}\n\\endcode\n*/\n\nARM_WIFI_CAPABILITIES ARM_WIFI_GetCapabilities (void) {\n  return { 0 };\n}\n/**\n\\fn ARM_WIFI_CAPABILITIES ARM_WIFI_GetCapabilities (void)\n\\details\nThe function \\b ARM_WIFI_GetCapabilities retrieves information about capabilities in this driver implementation.\nThe data fields of the struct \\ref ARM_WIFI_CAPABILITIES encode various capabilities, for example\nif a WiFi module supports the Access Point mode or the bypass mode, or is capable to signal events using\nthe \\ref ARM_WIFI_SignalEvent callback function.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\n  \nvoid get_wifi_capabilities (void)  {\n  ARM_WIFI_CAPABILITIES capabilities;\n \n  wifi = &Driver_WiFi0;  \n  capabilities = wifi->GetCapabilities ();\n  // interrogate capabilities\n   :\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_Initialize (ARM_WIFI_SignalEvent_t cb_event) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_Initialize (ARM_WIFI_SignalEvent_t cb_event)\n\\details\nThe function \\b ARM_WIFI_Initialize initializes the WiFi module.\n\nIt is called when the middleware component starts operation.\n\nThe \\ref ARM_WIFI_Initialize function performs the following operations:\n  - Initializes the resources and peripherals required for the WiFi module.\n  - Registers the \\ref ARM_WIFI_SignalEvent callback function.\n\nThe parameter \\em cb_event is a pointer to the \\ref ARM_WIFI_SignalEvent callback function;\nuse a \\token{NULL} pointer when no callback signals are required.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\nstatic ARM_ETH_MAC_ADDR own_mac_address;\n \nvoid initialize_wifi (void) {\n  wifi = &Driver_WiFi0;\n \n  // Initialize and Power-on WiFi Module\n  wifi->Initialize (NULL);\n  wifi->PowerControl (ARM_POWER_FULL);\n \n  // Populate own_mac_address with the address to use\n  wifi->SetOption(ARM_WIFI_MAC, &own_mac_address, 6U);\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_Uninitialize (void) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_Uninitialize (void)\n\\details\nThe function \\b ARM_WIFI_Uninitialize de-initializes the resources of the WiFi module.\n\nIt is called when the middleware component stops operation and releases the software resources \nused by the module.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\n \nvoid uninitialize_wifi (void) {\n  wifi = &Driver_WiFi0;\n \n  // Power off and De-initialize WiFi Module\n  wifi->PowerControl (ARM_POWER_OFF);\n  wifi->Uninitialize ();\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_PowerControl (ARM_POWER_STATE state) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_PowerControl (ARM_POWER_STATE state)\n\\details\nThe function \\b ARM_WIFI_PowerControl allows you to configure the power modes of the WiFi module.\n\nThe parameter \\em state specifies the \\ref ARM_POWER_STATE.\n\nLow-power mode depends on additional options set by \\ref ARM_WIFI_SetOption :\n - Deep-sleep mode is entered when \\ref ARM_WIFI_LP_TIMER option is set to a value different than 0\n - Sleep mode is entered otherwise\n\n\\b Deep-sleep mode (only for station):\nModule turns off the radio and also internal CPU thus reducing power consumption to minimum,\nonly the timer is running that wakes-up the module after specified time.\nWhen timer expires the module reconnects to the access point.\n\nThis mode is used when power consumption is a priority (battery powered devices) and when WiFi\nis used in short intervals that do not occur very often\n(example: sending a temperature from a sensor to a cloud every 10 seconds).\n\n\\b Sleep mode (only for station):\nModule reduces power consumption by going into sleep and waking up periodically to listen for beacons.\n\nDelivery Traffic Indication Message (DTIM) interval can be configured with option \\ref ARM_WIFI_DTIM\n(station and access point) and beacon interval with option \\ref ARM_WIFI_BEACON (only for access point).\n\nDefault module intervals are used when those options are not explicitly set.\n\nIf power \\em state specifies an unsupported mode, the function returns \\ref ARM_DRIVER_ERROR_UNSUPPORTED as\nstatus information and the previous power state of the peripheral is unchanged. Multiple calls with the same\n\\em state generate no error.\n\n\\b Example:\n - see \\ref ARM_WIFI_Initialize\n - see \\ref ARM_WIFI_Uninitialize\n*/\n\nint32_t ARM_WIFI_GetModuleInfo (char *module_info, uint32_t max_len) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_GetModuleInfo (char *module_info, uint32_t max_len)\n\\details\nThe function \\b ARM_WIFI_GetModuleInfo retrieves string containing information about the WiFi module.\n\nThe information might include module name, firmware version, ...\n\n\\note Module must be initialized and powered before module information can be retrieved.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\n \nvoid initialize_wifi (void) {\n  char info[32];\n \n  wifi = &Driver_WiFi0;\n \n  // Initialize and Power-on WiFi Module\n  wifi->Initialize (NULL);\n  wifi->PowerControl (ARM_POWER_FULL);\n \n  // Retrieve module information\n  wifi->GetModuleInfo(&info, sizeof(info));\n}\n\\endcode\n*/\n\nvoid ARM_WIFI_SignalEvent (uint32_t event, void *arg) {\n}\n/**\n\\fn void ARM_WIFI_SignalEvent (uint32_t event, void *arg)\n\\details\nThe function \\b ARM_WIFI_SignalEvent is a callback function registered by the function \\ref ARM_WIFI_Initialize.\nIt is called by the WiFi driver to notify the application about WiFi Events occurred during operation.\n\nThe parameter \\em event indicates the event that occurred during driver operation.\n\nThe parameter \\em arg provides additional information about the event.\n\nThe following events can be generated:\n\nParameter \\em event                  | Description\n:------------------------------------|:------------------------------------------\n\\ref ARM_WIFI_EVENT_AP_CONNECT       | Occurs in access point mode when a station has connected to the access point.\n\\ref ARM_WIFI_EVENT_AP_DISCONNECT    | Occurs in access point mode when a station has disconnected from the access point.\n\\ref ARM_WIFI_EVENT_ETH_RX_FRAME     | Occurs in \\ref wifi_bypass_gr when an ethernet frame is received.\n*/\n\n/**\n@}\n*/\n// end group wifi_control_gr\n\n\n/**\n\\defgroup wifi_management_gr WiFi Management\n\\ingroup wifi_interface_gr\n\\brief Configure and manage the connection to a WiFi access point (AP) or configure and manage the access point (AP).\n\\details The \\ref wifi_management_gr functions are used to configure and manage the connection to a WiFi access point (AP)\nalso called hotspot when in station mode. They are also used to configure and manage the access point (AP) itself\nwhen in access point mode.\n@{\n*/\n\n/**\n\\defgroup WiFi_option WiFi Option Codes\n\\ingroup wifi_management_gr\n\\brief  WiFi Option Codes for \\ref ARM_WIFI_SetOption or \\ref ARM_WIFI_GetOption function.\n\\details \nMany parameters of the WiFi module are configured using the \\ref ARM_WIFI_SetOption or \\ref ARM_WIFI_GetOption function.\n@{\n\\def ARM_WIFI_BSSID\n\\details Specifies the BSSID of the access point to connect or the access point itself.\n\\sa WiFi_option\n\\def ARM_WIFI_TX_POWER\n\\details Specifies the transmit power in dBm.\n\\sa WiFi_option\n\\def ARM_WIFI_LP_TIMER\n\\details Specifies the low-power deep-sleep time in seconds for station (disabled when 0 - default).\n\\sa WiFi_option\n\\def ARM_WIFI_DTIM\n\\details Specifies the DTIM interval in number of beacons.\n\\sa WiFi_option\n\\def ARM_WIFI_BEACON\n\\details Specifies the beacon interval in milliseconds for access point.\n\\sa WiFi_option\n\\def ARM_WIFI_MAC\n\\details Specifies the MAC address.\n\\sa WiFi_option\n\\def ARM_WIFI_IP\n\\details Specifies the IP address.\n\\sa WiFi_option\n\\def ARM_WIFI_IP_SUBNET_MASK\n\\details Specifies the subnet mask.\n\\sa WiFi_option\n\\def ARM_WIFI_IP_GATEWAY\n\\details Specifies the gateway IP address.\n\\sa WiFi_option\n\\def ARM_WIFI_IP_DNS1\n\\details Specifies the IP address of the primary DNS server.\n\\sa WiFi_option\n\\def ARM_WIFI_IP_DNS2\n\\details Specifies the IP address of the secondary DNS server.\n\\sa WiFi_option\n\\def ARM_WIFI_IP_DHCP\n\\details Enables or disables the DHCP client for station or DHCP server for access point.\n\\sa WiFi_option\n\\def ARM_WIFI_IP_DHCP_POOL_BEGIN\n\\details Specifies the start IP address for DHCP server (access point).\n\\sa WiFi_option\n\\def ARM_WIFI_IP_DHCP_POOL_END\n\\details Specifies the end IP address for DHCP server (access point).\n\\sa WiFi_option\n\\def ARM_WIFI_IP_DHCP_LEASE_TIME\n\\details Specifies the lease time for DHCP server (access point).\n\\sa WiFi_option\n\\def ARM_WIFI_IP6_GLOBAL\n\\details Specifies the global IPv6 address.\n\\sa WiFi_option\n\\def ARM_WIFI_IP6_LINK_LOCAL\n\\details Specifies the link-local IPv6 address.\n\\sa WiFi_option\n\\def ARM_WIFI_IP6_SUBNET_PREFIX_LEN\n\\details Specifies the address prefix length.\n\\sa WiFi_option\n\\def ARM_WIFI_IP6_GATEWAY\n\\details Specifies the gateway IPv6 address.\n\\sa WiFi_option\n\\def ARM_WIFI_IP6_DNS1\n\\details Specifies the IPv6 address of the primary DNS server.\n\\sa WiFi_option\n\\def ARM_WIFI_IP6_DNS2\n\\details Specifies the IPv6 address of the secondary DNS server.\n\\sa WiFi_option\n\\def ARM_WIFI_IP6_DHCP_MODE\n\\details Specifies the operation mode of the DHCPv6 client.\n\\sa WiFi_option\n@}\n*/\n\n/**\n\\defgroup wifi_sec_type WiFi Security Type\n\\ingroup wifi_management_gr\n\\brief Specifies WiFi security type for \\ref ARM_WIFI_Activate.\n\\details\nThe WiFi security type defines the standard used to protect the wireless network from unauthorized access.\n@{\n\\def ARM_WIFI_SECURITY_OPEN\n\\details This is an open system which provides \\b no security.\n\\sa wifi_sec_type\n\\def ARM_WIFI_SECURITY_WEP\n\\details This security standard provides \\b weak level of security.\n\\sa wifi_sec_type\n\\def ARM_WIFI_SECURITY_WPA\n\\details This security standard provides \\b medium level of security.\n\\sa wifi_sec_type\n\\def ARM_WIFI_SECURITY_WPA2\n\\details This security standard provides \\b strong level of security.\n\\sa wifi_sec_type\n\\def ARM_WIFI_SECURITY_UNKNOWN\n\\details Unknown security standard (reported by \\ref ARM_WIFI_Scan).\n\\sa wifi_sec_type\n@}\n*/\n\n/**\n\\defgroup wifi_wps_method WiFi Protected Setup (WPS) Method\n\\ingroup wifi_management_gr\n\\brief Specifies WiFi WPS method for \\ref ARM_WIFI_Activate.\n\\details\nThe WiFi WPS method defines which WPS method is used.\n@{\n\\def ARM_WIFI_WPS_METHOD_NONE\n\\details WPS not used.\n\\sa wifi_wps_method\n\\def ARM_WIFI_WPS_METHOD_PBC\n\\details WPS with Push Button Configuration.\n\\sa wifi_wps_method\n\\def ARM_WIFI_WPS_METHOD_PIN\n\\details WPS with PIN.\n\\sa wifi_wps_method\n@}\n*/\n\n/**\n\\defgroup wifi_dhcp_v6_mode WiFi DHCPv6 Mode\n\\ingroup wifi_management_gr\n\\brief Specifies IPv6 Dynamic Host Configuration Protocol (DHCP) Mode.\n\\details\nThe WiFi DHCPv6 mode defines the DHCP mode in IPv6.\n@{\n\\def ARM_WIFI_IP6_DHCP_OFF\n\\details\nIn the static host configuration mode, the IPv6 address, the default gateway address,\nand the addresses of DNS servers are statically configured from the preset values.\n\\sa wifi_dhcp_v6_mode\n\\def ARM_WIFI_IP6_DHCP_STATELESS\n\\details\nIn the stateless DHCP configuration mode, the client obtains only extended information\nfrom a DHCPv6 server, such as DNS server addresses. Stateless auto-configuration of\nIPv6 allows the client device to self configure it's IPv6 addresses and routing based\non the router advertisements.\n\\sa wifi_dhcp_v6_mode\n\\def ARM_WIFI_IP6_DHCP_STATEFULL\n\\details\nIn the stateful DHCP configuration mode, the client connects to a DHCPv6 server for\na leased IPv6 address and DNS server addresses.\n\\sa wifi_dhcp_v6_mode\n@}\n*/\n\n/**\n\\struct  ARM_WIFI_CONFIG_t\n\\details\nProvides information needed to connect to the WiFi network for station or how to configure the access point (AP).\n\n<b>Used in:</b>\n  - \\ref ARM_WIFI_Activate\n*******************************************************************************************************************/\n\n/**\n\\struct  ARM_WIFI_SCAN_INFO_t\n\\details\nProvides information about the wireless networks that were detected when searching for available WiFi networks. The structure\ncontains the information needed to connect to the WiFi network. Of course, the access password is not included and must\nbe provided separately.\n\n<b>Used in:</b>\n  - \\ref ARM_WIFI_Scan\n*******************************************************************************************************************/\n\n/**\n\\struct  ARM_WIFI_NET_INFO_t\n\\details\nProvides information about the network that the station is connected to.\n\n<b>Used in:</b>\n  - \\ref ARM_WIFI_GetNetInfo\n*******************************************************************************************************************/\n\nint32_t ARM_WIFI_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len)\n\\details\nThe function \\b ARM_WIFI_SetOption sets the value of the specified option of the WiFi module.\n\nThe argument \\em interface specifies the interface (0 = Station, 1 = Access Point).\n\nThe argument \\em option specifies the option that is to be set (see below).\n\nThe argument \\em data points to a buffer containing the value of the option to be set\nand must be aligned to the data type of the corresponding option.\n\nThe argument \\em len specifies the length of the buffer \\em data and must be equal (or higher)\nto the length of the corresponding option.\n \nOption                                 | Description                            | Data          | Type/Length\n:--------------------------------------|:---------------------------------------|:--------------|:-----------\n\\ref ARM_WIFI_BSSID                    | BSSID of AP to connect or AP           | bssid         | uint8_t[6]\n\\ref ARM_WIFI_TX_POWER                 | Transmit power                         | power[dbm]    | uint32_t\n\\ref ARM_WIFI_LP_TIMER                 | Low-power deep-sleep time              | time[seconds] | uint32_t\n\\ref ARM_WIFI_DTIM                     | DTIM interval                          | dtim[beacons] | uint32_t\n\\ref ARM_WIFI_BEACON                   | Beacon interval                        | interval[ms]  | uint32_t\n\\ref ARM_WIFI_MAC                      | MAC address                            | mac           | uint8_t[6]\n\\ref ARM_WIFI_IP                       | IPv4 address                           | ip            | uint8_t[4]\n\\ref ARM_WIFI_IP_SUBNET_MASK           | IPv4 subnet mask                       | mask          | uint8_t[4]\n\\ref ARM_WIFI_IP_GATEWAY               | IPv4 gateway address                   | ip            | uint8_t[4]\n\\ref ARM_WIFI_IP_DNS1                  | IPv4 primary DNS server address        | ip            | uint8_t[4]\n\\ref ARM_WIFI_IP_DNS2                  | IPv4 secondary DNS server address      | ip            | uint8_t[4]\n\\ref ARM_WIFI_IP_DHCP                  | IPv4 DHCP client/server enable/disable | dhcp (0, 1)   | uint32_t\n\\ref ARM_WIFI_IP_DHCP_POOL_BEGIN       | IPv4 DHCP server begin address         | ip            | uint8_t[4]\n\\ref ARM_WIFI_IP_DHCP_POOL_END         | IPv4 DHCP server end address           | ip            | uint8_t[4]\n\\ref ARM_WIFI_IP_DHCP_LEASE_TIME       | IPv4 DHCP server lease time            | time[seconds] | uint32_t\n\\ref ARM_WIFI_IP6_GLOBAL               | IPv6 global address                    | ip6           | uint8_t[16]\n\\ref ARM_WIFI_IP6_LINK_LOCAL           | IPv6 link-local address                | ip6           | uint8_t[16]\n\\ref ARM_WIFI_IP6_SUBNET_PREFIX_LEN    | IPv6 subnet prefix length              | len (1..127)  | uint32_t\n\\ref ARM_WIFI_IP6_GATEWAY              | IPv6 gateway address                   | ip6           | uint8_t[16]\n\\ref ARM_WIFI_IP6_DNS1                 | IPv6 primary DNS server address        | ip6           | uint8_t[16]\n\\ref ARM_WIFI_IP6_DNS2                 | IPv6 secondary DNS server address      | ip6           | uint8_t[16]\n\\ref ARM_WIFI_IP6_DHCP_MODE            | IPv6 DHCP client mode                  | mode          | uint32_t\n\n\\b Example:\n\\code\nuint8_t ip[4];\n \nip[0] = 192U;\nip[1] = 168U;\nip[2] = 0U;\nip[3] = 1U;\n \n// Set IP static address of the Station\nwifi->SetOption (0U, ARM_WIFI_IP, &ip, sizeof(ip));\n\\endcode\n*/\n\nint32_t ARM_WIFI_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len)\n\\details\nThe function \\b ARM_WIFI_GetOption retrieves the current value of the specified option of\nthe WiFi module.\n\nThe argument \\em interface specifies the interface (0 = Station, 1 = Access Point).\n\nThe argument \\em option specifies the option that is to be retrieved (see \\ref ARM_WIFI_SetOption).\n\nThe argument \\em data points to a buffer that will be used to store the value of \nthe \\em option and must be aligned to the data type of the corresponding option.\n\nThe argument \\em len is a pointer to the length of the buffer at input and returns the length\nof the option information on the output.\n\n\\b Example:\n\\code\nuint8_t ip[4];          // IP address\nuint8_t mask[4];        // Subnet mask\nuint8_t gateway[4];     // Gateway address\n \n// Get IP address, Subnet mask and Gateway address of the Station\nwifi->GetOption (0U, ARM_WIFI_IP, &ip, sizeof(ip));\nwifi->GetOption (0U, ARM_WIFI_IP_SUBNET_MASK, &mask, sizeof(mask));\nwifi->GetOption (0U, ARM_WIFI_IP_GATEWAY, &gateway, sizeof(gateway));\n\\endcode\n*/\n\nint32_t ARM_WIFI_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num)\n\\details\nThe function \\b ARM_WIFI_Scan searches for available WiFi networks. Using this function,\nyou can determine which wireless networks are available for the connection. If the network is\nsecured, you must also know the password to connect.\n \nThe argument \\em scan_info is a pointer to an array of network information structures, where \nthe available network information will be returned.\n\nThe argument \\em max_num specifies maximum number of network information structures,\nthat can be stored to the \\em scan_info.\n\n\\b Example:\n\\code\nARM_WIFI_SCAN_INFO_t scan_info[8];\n \nnum = wifi->Scan (scan_info, 8U);\n \n// Print SSIDs of available WiFi networks\nfor (i = 0; i < num; i++) {\n  printf (\"%d. ssid=%s\\n\", i, scan_info[i].ssid);\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_Activate (uint32_t interface, const ARM_WIFI_CONFIG_t *config) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_Activate (uint32_t interface, const ARM_WIFI_CONFIG_t *config)\n\\details\nThe function \\b ARM_WIFI_Activate activates the specified interface.\n\nThe argument \\em interface specifies the interface (0 = Station, 1 = Access Point).\n\nWhen station interface is specified, the WiFi module connects to a wireless network.\n\nThe wireless network trying to connect to must be available,\notherwise the operation will fail after a timeout.\n\nAvailable wireless networks can be scanned by using the function \\ref ARM_WIFI_Scan.\n\nWhen access point interface is specified, the WiFi module creates a wireless network\nby activating the access point.\n\nThe argument \\em config is a pointer to the configuration \\ref ARM_WIFI_CONFIG_t\nwhich provides information needed to connect to a WiFi network for station interface\nor information used to configure the access point (AP) for access point interface.\n\n\\em ssid specifies the name of the network to connect to or the network to create.\n\n\\em pass specifies the password for accessing the wireless network.\n\n\\em security specifies the security type which will be used for the connection.\n\n\\em ch specifies the WiFi channel which will be used for the connection.\nValid channels for 2.4 GHz frequency are from \\token{1} to \\token{13}. If the value for \\em ch = \\token{0},\nthe system automatically selects the channel.\nFor station interface the channel of the AP being connected to is used.\nFor access point interface the module automatically selects the best channel for the WiFi connection.\n\n\\note\nOptionally BSSID parameter can be also set using \\ref ARM_WIFI_SetOption.\nIt allows connection to specific BSSID when connecting to an access point or specifies\nthe BSSID of the access point.\n\n\\em wps_method specifies if WiFi Protected Setup (WPS) is used and which method.\n\n\\em wps_pin specifies the PIN used with WPS (\\ref ARM_WIFI_WPS_METHOD_PIN).\n\nWith the \\b push-button method, you typically press the button, either real or virtual,\nboth at the access point and the station. No credentials are needed.\n\nWith \\b PIN method, you must provide the PIN code that you read from the label or screen\non the wireless device.\n\nWPS configuration for station is used when station connects to an access point.\nIt enables to connect without specifying SSID, Password, Security Type or WiFi Channel.\nThe actual network information can be retrieved once connected with \\ref ARM_WIFI_GetNetInfo.\n\nWPS configuration for access point is used when access point is activated.\nSubsequent activate calls re-trigger the WPS procedure.\n\n\\note\nWPS is typically activated by pressing the WPS button at the access point.\nDuring the discovery mode (usually 2 minutes or less) any wireless device may connect\nto the access point (PIN needs to match when PIN method is selected).\n\n\\b Example:\n\\code\nARM_WIFI_CONFIG_t wifi_config;\n \nwifi_config.ssid = \"GuestAccess\";\nwifi_config.pass = \"guest\";\nwifi_config.security = ARM_WIFI_SECURITY_WPA2;\nwifi_config.ch = 0U;\nwifi_config.wps_method = ARM_WIFI_WPS_METHOD_NONE;\n \n// Connect to wireless network\nstatus = wifi->Activate (0U, &wifi_config);\nif (status != ARM_DRIVER_OK) {\n  // error handling\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_Deactivate (uint32_t interface) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_Deactivate (uint32_t interface)\n\\details\nThe function \\b ARM_WIFI_Deactivate deactivates the specified interface.\n\nThe argument \\em interface specifies the interface (0 = Station, 1 = Access Point).\n\nWhen station interface is specified, the WiFi module disconnects from the wireless network.\n\nWhen access point interface is specified, the WiFi module deactivates the access point.\n\n\\b Example:\n - see \\ref ARM_WIFI_GetNetInfo\n*/\n\nuint32_t ARM_WIFI_IsConnected (void) {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_WIFI_IsConnected (void)\n\\details\nThe function \\b ARM_WIFI_IsConnected checks if the station is connected to a wireless network\nand returns the connection status.\n\nThe function returns a \\token{non-zero} value, if the station is connected. If the station\nis not connected, the function returns \\token{0}.\n\n\\b Example:\n - see \\ref ARM_WIFI_GetNetInfo\n*/\n\nint32_t ARM_WIFI_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info)\n\\details\nThe function \\b ARM_WIFI_GetNetInfo retrieves wireless network information of a connected station.\n\nIt can be used to retrieve network connection information for subsequent connections\nafter initially connecting using WPS.\n\n\\b Example:\n\\code\nARM_WIFI_CONFIG_t wifi_config;\nARM_WIFI_NET_INFO_t net_info;\n \nmemset(&wifi_config, 0, sizeof(wifi_config));\n \nwifi_config.wps_method = ARM_WIFI_WPS_METHOD_PBC;\n \n// Connect to wireless network (WPS)\nstatus = wifi->Activate (0U, &wifi_config);\nif (status != ARM_DRIVER_OK) {\n  // error handling\n}\n \n// Retrieve network information\nif (wifi->IsConnected ()) {\n  status = wifi->GetNetInfo (&net_info);\n  if (status != ARM_DRIVER_OK) {\n    // error handling\n  }\n  printf(\"SSID=%s, Password=%s\",net_info.ssid, net_info.pass);\n}\n \n// Disconnect from wireless network\nwifi->Deactivate (0U);\n\\endcode\n*/\n\n/**\n@}\n*/\n// end group wifi_management_gr\n\n\n/**\n\\defgroup wifi_bypass_gr WiFi Bypass Mode\n\\ingroup wifi_interface_gr\n\\brief Transfer Ethernet frames by WiFi module.\n\\details The \\ref wifi_bypass_gr functions are an optional interface and enable the transmission of\nEthernet frames with WiFi modules. The use of this interface requires that the TCP/IP stack is running\non the microcontroller (usually a third-party or open-source networking component). The internal TCP/IP\nstack of the WiFi module is therefore not used, and this usually means that the \\ref wifi_socket_gr\nfunctions can not be used.\n@{\n*/\n\nint32_t ARM_WIFI_BypassControl (uint32_t interface, uint32_t mode) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_BypassControl (uint32_t interface, uint32_t mode)\n\\details\nThe function \\b ARM_WIFI_BypassControl enables or disables the WiFi bypass mode.\n\nThe WiFi Bypass mode can only be enabled, if there is a bypass mode supported in the WiFi driver.\nYou can check this by checking the driver's capabilities.\n\n\\note\nBypass mode is enabled by default if the module does not support the Socket interface.\n\nThe argument \\em mode specifies the desired state of the WiFi Bypass mode, which is\nenabled or disabled.\n \n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\nstatic ARM_ETH_MAC_ADDR own_mac_address;\n \nstatic void wifi_notify (uint32_t event, ,void *arg) {\n  switch (event)  {\n     :\n  }  \n}\n \nvoid initialize_wifi_bypass (void) {\n  ARM_WIFI_CAPABILITIES capabilities;\n \n  wifi = &Driver_WiFi0;\n  capabilities = wifi->GetCapabilities ();\n  if (capabilities.bypass_mode == 0) {\n    // error handling \n  } \n \n  // Initialize and Power-on WiFi Interface\n  wifi->Initialize ((capabilities.eth_rx_frame_event) ? wifi_notify : NULL);\n  wifi->PowerControl (ARM_POWER_FULL);\n \n  // populate own_mac_address with the address to use for station\n  wifi->SetOption(0U, ARM_WIFI_MAC, &own_mac_address, 6U);\n \n  wifi->BypassControl (0U, 1U); // Enable bypass mode for station\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len)\n\\details\nThe function \\b ARM_WIFI_EthSendFrame writes an <b>Ethernet frame</b> to the WiFi transmit buffer.\n\nThe WiFi bypass mode must be enabled by using the function \\ref ARM_WIFI_BypassControl\nbefore a call to this function.\n\nThe frame data addressed by \\em frame starts with MAC destination and ends with the last\nPayload data byte. The frame data is copied into the transmit buffer of the WiFi interface.\n\nThe maximum value for \\em len is implied by the size restrictions of the Ethernet frame\nbut is not verified. Using an invalid value for \\em len may generate unpredicted results.\n\n\\b Example:\n\\code\nstatus = wifi->EthSendFrame (0U, &frame_data[0], frame_length);\nif (status != ARM_DRIVER_OK)  {\n  // error handling\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len)\n\\details\nThe function \\b ARM_WIFI_EthReadFrame reads an <b>Ethernet frame</b> from the WiFi interface\nin the bypass mode.\n\nThe \\em len of the Ethernet frame can be checked using the function \\ref ARM_WIFI_EthGetRxFrameSize.\n\nThe frame data addressed by \\em frame starts with MAC destination and ends with the last\nPayload data byte. The frame data is read from the receive buffer of the WiFi interface and\nthe number of bytes written into the memory addressed by \\em frame is returned.\nA negative return value indicates an error whereby the status code is defined with \ndriver common return codes.\n\nThe function \\ref ARM_WIFI_EthReadFrame may be called with \\em buf = \\token{NULL} and \\em len = \\token{0}\nto discard or release a frame. This is useful when an incorrect frame has been received or\nno memory is available to hold the Ethernet frame.\n \n\\b Example:\n\\code\nsize = wifi->EthGetRxFrameSize ();\nif ((size < 14) || (size > 1514)) {    // frame excludes CRC\n  wifi->EthReadFrame (NULL, 0);        // Frame error, release it\n}\nlen = wifi->ReadFrame (0U, &frame_data[0], size);\nif (len < 0)  {\n  // error handling\n}\n\\endcode\n*/\n\nuint32_t ARM_WIFI_EthGetRxFrameSize (uint32_t interface) {\n  return 0;\n}\n/**\n\\fn uint32_t ARM_WIFI_EthGetRxFrameSize (uint32_t interface)\n\\details\nThe function \\b ARM_WIFI_EthGetRxFrameSize returns the size of a received <b>Ethernet frame</b>\nin the bypass mode. This function can be called before \\ref ARM_WIFI_EthReadFrame and retrieves \nthe value \\em len.\n\nThe frame size includes MAC destination and ends with the last Payload data byte.\nValue \\token{0} indicates that no Ethernet frame is available in the receive buffer.\nValues smaller than minimum size of Ethernet frame or larger than maximum size of Ethernet frame\nindicate an invalid frame which needs to be discarded by calling \\ref ARM_WIFI_EthReadFrame.\n \n\\b Example:\n - see \\ref ARM_WIFI_EthReadFrame\n*/\n/**\n@}\n*/\n// end group wifi_bypass_gr\n\n\n/**\n\\defgroup wifi_socket_gr WiFi Socket\n\\ingroup wifi_interface_gr\n\\brief Socket interface to IP stack running on WiFi module\n\\details The \\ref wifi_socket_gr functions provide the interface to an IP stack that is running\non the WiFi module. This IP stack handles data communication with the network and provides the user\nwith a communication endpoint called sockets.\n@{\n*/\n\n/**\n\\defgroup wifi_addr_family WiFi Socket Address Family definitions\n\\ingroup wifi_socket_gr\n\\brief WiFi Socket Address Family definitions.\n\\details The WiFi Socket Address Family specifies the addressing scheme that an instance of the WiFi socket can use.\n@{\n\\def ARM_SOCKET_AF_INET\n\\details Internet Address Family version 4.\n\\def ARM_SOCKET_AF_INET6\n\\details Internet Address Family version 6.\n@}\n*/\n\n/**\n\\defgroup wifi_socket_type WiFi Socket Type definitions\n\\ingroup wifi_socket_gr\n\\brief WiFi Socket Type definitions.\n\\details The WiFi Socket Type specifies the type of the WiFi socket.\n@{\n\\def ARM_SOCKET_SOCK_STREAM\n\\details Stream Socket is connection-oriented, sequenced and reliable, implemented on top of the TCP protocol.\n\\def ARM_SOCKET_SOCK_DGRAM\n\\details Datagram Socket is connectionless, unreliable, using the UDP protocol.\n@}\n*/\n\n/**\n\\defgroup wifi_protocol WiFi Socket Protocol definitions\n\\ingroup WiFi_socket_gr\n\\brief WiFi Socket Protocol definitions.\n\\details The WiFi Socket Protocol specifies the Internet Protocol Type that the socket is using.\n@{\n\\def ARM_SOCKET_IPPROTO_TCP\n\\details Transmission Control Protocol.\n\\def ARM_SOCKET_IPPROTO_UDP\n\\details User Datagram Protocol.\n@}\n*/\n\n/**\n\\defgroup wifi_soc_opt WiFi Socket Option definitions\n\\ingroup WiFi_socket_gr\n\\brief WiFi Socket Option definitions.\n\\details The WiFi Socket Option specifies the socket option for which the value is to be set or obtained.\n@{\n\\def ARM_SOCKET_IO_FIONBIO\n\\details Enables or disables the non-blocking mode for the WiFi socket.\n\\sa wifi_soc_opt\n\\def ARM_SOCKET_SO_RCVTIMEO\n\\details Specifies the time limit for receiving in blocking mode. The time limit is in milliseconds.\n\\sa wifi_soc_opt\n\\def ARM_SOCKET_SO_SNDTIMEO\n\\details Specifies the time limit for sending in blocking mode. The time limit is in milliseconds.\n\\sa wifi_soc_opt\n\\def ARM_SOCKET_SO_KEEPALIVE\n\\details Enables or disables the keep-alive mode for the stream socket.\n\\sa wifi_soc_opt\n\\def ARM_SOCKET_SO_TYPE\n\\details Obtains the type of the Wifi socket.\n\\sa wifi_soc_opt\n@}\n*/\n\n/**\n\\defgroup wifi_soc_func WiFi Socket Function return codes\n\\ingroup WiFi_socket_gr\n\\brief WiFi Socket Function return codes.\n\\details This section lists all the return errors the WiFi socket functions will return.\nThe error codes are negative. This makes it easy to check an error when the return\ncode is less than \\token{0}.\n@{\n\\def ARM_SOCKET_ERROR\n\\sa wifi_soc_func\n\\def ARM_SOCKET_ESOCK\n\\sa wifi_soc_func\n\\def ARM_SOCKET_EINVAL\n\\sa wifi_soc_func\n\\def ARM_SOCKET_ENOTSUP\n\\sa wifi_soc_func\n\\def ARM_SOCKET_ENOMEM\n\\sa wifi_soc_func\n\\def ARM_SOCKET_EAGAIN\n\\sa wifi_soc_func\n\\def ARM_SOCKET_EINPROGRESS\n\\sa wifi_soc_func\n\\def ARM_SOCKET_ETIMEDOUT\n\\sa wifi_soc_func\n\\def ARM_SOCKET_EISCONN\n\\sa wifi_soc_func\n\\def ARM_SOCKET_ENOTCONN\n\\sa wifi_soc_func\n\\def ARM_SOCKET_ECONNREFUSED\n\\sa wifi_soc_func\n\\def ARM_SOCKET_ECONNRESET\n\\sa wifi_soc_func\n\\def ARM_SOCKET_ECONNABORTED\n\\sa wifi_soc_func\n\\def ARM_SOCKET_EALREADY\n\\sa wifi_soc_func\n\\def ARM_SOCKET_EADDRINUSE\n\\sa wifi_soc_func\n\\def ARM_SOCKET_EHOSTNOTFOUND\n\\sa wifi_soc_func\n@}\n*/\n\nint32_t ARM_WIFI_SocketCreate (int32_t af, int32_t type, int32_t protocol) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketCreate (int32_t af, int32_t type, int32_t protocol)\n\\details\nThe function \\b ARM_WIFI_SocketCreate creates a communication endpoint called a socket.\n\nThe argument \\em af specifies the address family. The following values are supported:\nFamily                       | Description\n:----------------------------|:-------------------------------------------------\n\\ref ARM_SOCKET_AF_INET      | Address Family Internet\n\\ref ARM_SOCKET_AF_INET6     | Address Family Internet version 6\n\nThe argument \\em type specifies the communication semantics. The following are the currently supported types:\nType                         | Description\n:----------------------------|:-------------------------------------------------\n\\ref ARM_SOCKET_SOCK_STREAM  | Provides a reliable connection based data stream that is full-duplex\n\\ref ARM_SOCKET_SOCK_DGRAM   | Provides connectionless communication that is unreliable\n\nThe argument \\em protocol specifies the protocol that must be used with the socket type:\nProtocol                     | Description\n:----------------------------|:-------------------------------------------------\n\\ref ARM_SOCKET_IPPROTO_TCP  | Must be used with ARM_SOCKET_SOCK_STREAM socket type\n\\ref ARM_SOCKET_IPPROTO_UDP  | Must be used with ARM_SOCKET_SOCK_DGRAM socket type\n\\token{0}                    | The system selects a matching protocol for the socket type\n\n\\b Example:\n - see \\ref ARM_WIFI_SocketListen, \\ref ARM_WIFI_SocketConnect\n*/\n\nint32_t ARM_WIFI_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)\n\\details\nThe function \\b ARM_WIFI_SocketBind assigns a name to an unnamed socket. The name represents the local address\nand port of the communication endpoint.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em ip is a pointer to the buffer containing the IP address octets of the local IP address.\n\nThe argument \\em ip_len specifies the length of the local IP address. The length is \\token{4} bytes\nfor the IPv4 address and \\token{16} bytes for the IPv6 address.\n\nThe argument \\em port specifies the local port. If the argument \\em port is \\token{0}, the function returns error,\nbecause this port is reserved.\n \n\\b Example:\n - see \\ref ARM_WIFI_SocketListen\n*/\n\nint32_t ARM_WIFI_SocketListen (int32_t socket, int32_t backlog) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketListen (int32_t socket, int32_t backlog)\n\\details\nThe function \\b ARM_WIFI_SocketListen sets the specified socket to listening mode, that is to the\nserver mode of operation. Before calling the \\b ARM_WIFI_SocketListen function, the \\ref ARM_WIFI_SocketBind\nfunction must be called.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em backlog specifies a maximum number of connection requests that can be queued.\n \n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\n \nvoid Echo_Server_Thread (void *arg) {\n  uint8_t ip[4] = { 0U, 0U, 0U, 0U };\n  int32_t sock, sd, res;\n  char dbuf[120];\n \n  while (1) {\n    wifi = &Driver_WiFi0;\n    sock = wifi->SocketCreate (ARM_SOCKET_AF_INET, ARM_SOCKET_SOCK_STREAM, ARM_SOCKET_IPPROTO_TCP);\n \n    wifi->SocketBind (sock, (uint8_t *)ip, sizeof(ip), 7U);\n    wifi->SocketListen (sock, 1);\n    sd = wifi->SocketAccept (sock, NULL, NULL, NULL);\n    wifi->SocketClose (sock);\n    sock = sd;\n \n    while (1) {\n      res = wifi->SocketRecv (sock, dbuf, sizeof(dbuf));\n      if (res < 0) {\n        break;                                      // Error occurred\n      }\n      if (res > 0) {\n        wifi->SocketSend (sock, dbuf, res);         // Echo the data\n      }\n    }\n    wifi->SocketClose (sock);\n  }\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)\n\\details\nThe function \\b ARM_WIFI_SocketAccept accepts a connection request queued for a listening socket.\nIf a connection request is pending, \\b ARM_WIFI_SocketAccept removes the request from the queue,\nand creates a new socket for the connection. The original listening socket remains open and continues\nto queue new connection requests. The \\em socket must be a socket of type \\b ARM_SOCKET_SOCK_STREAM.\n\nIn blocking mode, which is enabled by default, this function waits for a connection request. In\nnon blocking mode, you must call the \\b ARM_WIFI_SocketAccept function again if the error code\n\\c ARM_SOCKET_EAGAIN is returned.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em ip is a pointer to the buffer that will receive the IP address of the connection node.\nIf the \\em ip is \\token{NULL}, the IP address is not returned.\n\nThe argument \\em ip_len is a pointer to the IP address length. It should initially contain the amount of\nspace pointed to by \\em ip. On return it contains the actual length of the address returned in bytes.\n\nThe argument \\em port is a pointer to the buffer, that will receive the port number of the connection node.\nIf the \\em port is \\token{NULL}, the port number is not returned.\n\n\\b Example:\n - see \\ref ARM_WIFI_SocketListen\n*/\n\nint32_t ARM_WIFI_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)\n\\details\nThe function \\b ARM_WIFI_SocketConnect assigns the address of the peer communication endpoint. The function\nbehaves differently according to the type of socket:\n\n- \\b ARM_SOCKET_SOCK_STREAM: A connection is established between the endpoints.\n\n  In blocking mode, which is enabled by default, this function waits for a connection to be established.\n\n  In non blocking mode, the function returns the error code \\c ARM_SOCKET_EINPROGRESS and the connection\n  is established asynchronously. Subsequent calls to \\b ARM_WIFI_SocketConnect for the same socket,\n  before the connection is established, return the error code \\c ARM_SOCKET_EALREADY.  When the connection\n  is established, the call to \\b ARM_WIFI_SocketConnect returns the error code \\c ARM_SOCKET_EISCONN. \n\n- \\b ARM_SOCKET_SOCK_DGRAM: An address filter is established between the endpoints.\n\n  The address filter is changed with another \\b ARM_WIFI_SocketConnect function call. If the socket\n  is not yet bound, the system implicitly binds to a random dynamic port.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em ip is a pointer to the buffer containing the IP address octets of the endpoint node.\n\nThe argument \\em ip_len specifies the length of the IP address. The length is \\token{4} bytes\nfor the IPv4 address and \\token{16} bytes for the IPv6 address.\n\nThe argument \\em port specifies the port of the endpoint node. If the argument \\em port is \\token{0}, \nthe function returns error, because this port is reserved.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\n \nstatic const char message[] = { \"The quick brown fox jumps over the lazy dog.\" };\n  \nvoid Echo_Client_Thread (void *arg) {\n  uint8_t ip[4] = { 192U, 168U, 0U, 100U };\n  int32_t sock, res;\n  char dbuf[120];\n \n  while (1) {\n    wifi = &Driver_WiFi0;\n    sock = wifi->SocketCreate (ARM_SOCKET_AF_INET, ARM_SOCKET_SOCK_STREAM, ARM_SOCKET_IPPROTO_TCP);\n \n    res = wifi->SocketConnect (sock, (uint8_t *)ip, sizeof(ip), 7U);\n    if (res == 0) {\n      wifi->SocketSend (sock, message, sizeof(message));\n      res = wifi->SocketRecv (sock, dbuf, sizeof(dbuf));\n      if (res < 0) {\n        break;               // Error occured\n      }\n      if (res > 0) {\n        if (memcmp (dbuf, message, res) != 0) {\n          // error handling, message is not the same as sent\n        }\n      }    \n    }\n    wifi->SocketClose (sock);\n    osDelay (1000U);\n  }\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_SocketRecv (int32_t socket, void *buf, uint32_t len) {\n  return 1;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketRecv (int32_t socket, void *buf, uint32_t len)\n\\details\nThe function \\b ARM_WIFI_SocketRecv receives incoming data that has been queued for the socket.\nYou can use this function with both, the stream and the datagram socket. It reads as much\ninformation as currently available up to the size of the buffer specified.\n\nIn blocking mode, which is enabled by default, this function waits for received data. In non\nblocking mode, you must call the \\b ARM_WIFI_SocketRecv function again if the error code \n\\c ARM_SOCKET_EAGAIN is returned.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em buf is a pointer to the application data buffer for storing the data to.\nIf the available data is too large to fit in the supplied application buffer \\em buf, excess bytes\nare discarded in case of a datagram sockets. For stream sockets, the data is buffered internally\nso the application can retrieve all data by multiple calls of \\b ARM_WIFI_SocketRecv function.\n\nThe argument \\em len specifies the size of the application data buffer.\n\n\\note\nThe function can also be used to check if the socket has data available to read by specifying \\token{0}\nfor argument \\em len (argument \\em buf is ignored).\nThe function returns \\token{0} if data is available or error code otherwise.\nIn blocking mode, the function waits until data is available, in non blocking mode the function returns instantly.\n\n\n\\b Example:\n - see \\ref ARM_WIFI_SocketListen\n*/\n\nint32_t ARM_WIFI_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {\n  return 1;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port)\n\\details\nThe function \\b ARM_WIFI_SocketRecvFrom is used to receive data that has been queued for a socket.\nIt is normally used to receive messages on datagram sockets, but can also be used to receive a reliable,\nordered stream of data on a connected stream sockets. It reads as much information as currently available\nup to the size of the buffer specified.\n\nIn blocking mode, which is enabled by default, this function waits for received data. In non\nblocking mode, you must call the \\b ARM_WIFI_SocketRecv function again if the error code \n\\c ARM_SOCKET_EAGAIN is returned.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em buf is a pointer to the application data buffer for storing the data to.\nIf the available data is too large to fit in the supplied application buffer \\em buf, excess bytes\nare discarded in case of a datagram sockets. For stream sockets, the data is buffered internally\nso the application can retrieve all data by multiple calls of \\b ARM_WIFI_SocketRecv function.\n\nThe argument \\em len specifies the size of the application data buffer.\n\nThe argument \\em ip is a pointer to the buffer that will receive the IP address of the sender.\nIf the \\em ip is \\token{NULL}, the IP address is not returned.\n\nThe argument \\em ip_len is a pointer to the IP address length. It should initially contain the amount of\nspace pointed to by \\em ip. On return it contains the actual length of the address returned in bytes.\n\nThe argument \\em port is a pointer to the buffer, that will receive the port number of the sender.\nIf the \\em port is \\token{NULL}, the port number is not returned.\n\n\\note\nThe function can also be used to check if the socket has data available to read by specifying \\token{0}\nfor argument \\em len (arguments \\em buf, \\em ip, \\em ip_len and \\em port are ignored).\nThe function returns \\token{0} if data is available or error code otherwise.\nIn blocking mode, the function waits until data is available, in non blocking mode the function returns instantly.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\n \nvoid Echo_Server_Thread (void *arg) {\n  uint8_t ip[4];\n  uint16_t port;\n  int32_t sock, res;\n  uint32_t ip_len;\n  char dbuf[120];\n \n  while (1) {\n    wifi = &Driver_WiFi0;\n    sock = wifi->SocketCreate (ARM_SOCKET_AF_INET, ARM_SOCKET_SOCK_DGRAM, ARM_SOCKET_IPPROTO_UDP);\n \n    ip[0] = 0U;                 // Unspecified address\n    ip[1] = 0U;\n    ip[2] = 0U;\n    ip[3] = 0U;\n    port  = 7U;                 // Standard port for Echo service\n \n    wifi->SocketBind (sock, (uint8_t *)ip, sizeof(ip), port);\n \n    while (1) {\n      ip_len = sizeof(ip);\n      res = wifi->SocketRecvFrom (sock, dbuf, sizeof(dbuf), (uint8_t *)ip, &ip_len, &port);\n      if (res < 0) {\n        break;                  // Error occurred\n      }\n      if (res > 0) {            // Echo the data\n        wifi->SocketSendTo (sock, dbuf, res, (uint8_t *)ip, ip_len, port);\n      }    \n    }\n    wifi->SocketClose (sock);\n  }\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_SocketSend (int32_t socket, const void *buf, uint32_t len) {\n  return 1;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketSend (int32_t socket, const void *buf, uint32_t len)\n\\details\nThe function \\b ARM_WIFI_SocketSend is used to send data on an already connected socket. This function is\nnormally used to send a reliable, ordered stream of data bytes on a stream sockets. It can also be used\nto send messages on datagram sockets.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\a buf is a pointer to the application data buffer containing data to transmit. The buffer\ndata length is not limited in size. If the data length is too large for one packet, the \\b ARM_WIFI_SocketSend function\nwill fragment the data and send it in several successive data packets:\n- In blocking mode, which is enabled by default, this function returns after the data has been successfully queued for transmission.\n- In non blocking mode, the function returns immediately without blocking the system.\n\nThe argument \\a len specifies the length of data in bytes.\n\nReturn value, when positive, represents the number of bytes sent, which can be less than \\a len.\n\n\\note\nThe function can also be used to check if the socket is ready to send data by specifying \\token{0} \nfor argument \\em len (argument \\em buf is ignored).\nThe function returns \\token{0} if the socket is writable or error code otherwise.\n\n\\b Example:\n - see \\ref ARM_WIFI_SocketListen\n*/\n\nint32_t ARM_WIFI_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port) {\n  return 1;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port)\n\\details\nThe function \\b ARM_WIFI_SocketSendTo is used to send data. It is normally used to send messages\non a datagram sockets, but can also be used to send data on a connected stream sockets.\n\nIf the datagram socket is not yet bound, the system implicitly binds to a random dynamic port.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\a buf is a pointer to the application data buffer containing data to transmit. The buffer\ndata length is not limited in size. If the data length is too large for one packet, the \\b ARM_WIFI_SocketSend function\nwill fragment the data and send it in several successive data packets:\n- In blocking mode, which is enabled by default, this function returns after the data has been successfully queued for transmission.\n- In non blocking mode, the function returns immediately without blocking the system.\n\nThe argument \\a len specifies the length of data in bytes.\n\nThe argument \\em ip is a pointer to the buffer containing the IP address octets of the endpoint node.\n\nThe argument \\em ip_len specifies the length of the IP address. The length is \\token{4} bytes\nfor the IPv4 address and \\token{16} bytes for the IPv6 address.\n\nThe argument \\em port specifies the port of the endpoint node. If the argument \\em port is \\token{0}, \nthe function returns error, because this port is reserved.\n\nFor the stream sockets, arguments \\em ip, \\em ip_len and \\em port are ignored.\n\nReturn value, when positive, represents the number of bytes sent, which can be less than \\a len.\n\n\\note\nThe function can also be used to check if the socket is ready to send data by specifying \\token{0} \nfor argument \\em len (arguments \\em buf, \\em ip, \\em ip_len and \\em port are ignored).\nThe function returns \\token{0} if the socket is writable or error code otherwise.\n\n\\b Example:\n - see \\ref ARM_WIFI_SocketRecvFrom\n*/\n\nint32_t ARM_WIFI_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)\n\\details\nThe function \\b ARM_WIFI_SocketGetSockName retrieves the local IP address and port for a socket.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em ip is a pointer to the buffer that will receive the local IP address.\nIf the \\em ip is \\token{NULL}, the local IP address is not returned.\n\nThe argument \\em ip_len is a pointer to the IP address length. It should initially contain the amount of\nspace pointed to by \\em ip. On return it contains the actual length of the address returned in bytes.\n\nThe argument \\em port is a pointer to the buffer, that will receive the local port number.\nIf the \\em port is \\token{NULL}, the local port number is not returned.\n\n\\b Example:\n\\code\nstatic uint8_t  local_ip[4];    // Socket address and port\nstatic uint16_t local_port;\n \nstatic void get_socket_local_info (void) {\n  uint32_t ip_len;\n \n  ip_len = sizeof(local_ip);\n  wifi->SocketGetSockName (sock, (uint8_t *)local_ip, &ip_len, &local_port);\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)\n\\details\nThe function \\b ARM_WIFI_SocketGetPeerName retrieves the IP address and port of the peer to which\na socket is connected.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em ip is a pointer to the buffer that will receive the IP address of the peer.\nIf the \\em ip is \\token{NULL}, the IP address is not returned.\n\nThe argument \\em ip_len is a pointer to the IP address length. It should initially contain the amount of\nspace pointed to by \\em ip. On return it contains the actual length of the address returned in bytes.\n\nThe argument \\em port is a pointer to the buffer, that will receive the port number of the peer.\nIf the \\em port is \\token{NULL}, the port number is not returned.\n\n\\b Example:\n\\code\nstatic uint8_t  peer_ip[4];    // Socket address and port\nstatic uint16_t peer_port;\n \nstatic void get_socket_peer_info (void) {\n  uint32_t ip_len;\n \n  ip_len = sizeof(peer_ip);\n  wifi->SocketGetPeerName (sock, (uint8_t *)peer_ip, &ip_len, &peer_port);\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len)\n\\details\nThe function \\b ARM_WIFI_SocketGetOpt retrieves options for a socket.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em opt_id is the socket option for which the value is to be retrieved. The following\nsocket options are supported:\nOption                       | Description\n:----------------------------|:-------------------------------------------------\n\\ref ARM_SOCKET_SO_RCVTIMEO  | Timeout for receiving in blocking mode\n\\ref ARM_SOCKET_SO_SNDTIMEO  | Timeout for sending in blocking mode\n\\ref ARM_SOCKET_SO_KEEPALIVE | Keep-alive mode for the stream socket\n\\ref ARM_SOCKET_SO_TYPE      | Type of the socket (stream or datagram)\n\nThe argument \\em opt_val points to the buffer that will receive the value of the \\em opt_id.\n\nThe argument \\em opt_len contains the length of the buffer at the input and returns the length\nof the option information on the output.\n\n\\b Example:\n\\code\nuint32_t type;\n \nwifi->SocketGetOpt (sock, ARM_SOCKET_SO_TYPE, &type, sizeof(type));\nif (type == ARM_SOCKET_SOCK_STREAM) {\n  // Stream socket\n}\nif (type == ARM_SOCKET_SOCK_DGRAM) {\n  // Datagram socket\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len)\n\\details\nThe function \\b ARM_WIFI_SocketSetOpt sets options for a socket.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nThe argument \\em opt_id is the socket option for which the value is to be set. The following\nsocket options are supported:\nOption                       | Description\n:----------------------------|:-------------------------------------------------\n\\ref ARM_SOCKET_IO_FIONBIO   | Non-blocking mode for the socket\n\\ref ARM_SOCKET_SO_RCVTIMEO  | Timeout for receiving in blocking mode\n\\ref ARM_SOCKET_SO_SNDTIMEO  | Timeout for sending in blocking mode\n\\ref ARM_SOCKET_SO_KEEPALIVE | Keep-alive mode for the stream socket\n\nThe argument \\em opt_val points to the buffer containing the value of the \\em opt_id.\n\nThe argument \\em opt_len tells the exact length of the option.\n \n\\b Example:\n\\code\nuint32_t nonblocking = 0U;    // Blocking mode\nuint32_t timeout = 10000U;    // Timeout 10 seconds\n \nwifi->SocketSetOpt (sock, ARM_SOCKET_IO_FIONBIO, &nonblocking, sizeof(nonblocking));\nwifi->SocketSetOpt (sock, ARM_SOCKET_SO_RCVTIMEO, &timeout, sizeof(timeout)); \nwifi->SocketSetOpt (sock, ARM_SOCKET_SO_SNDTIMEO, &timeout, sizeof(timeout));\n\\endcode\n*/\n\nint32_t ARM_WIFI_SocketClose (int32_t socket) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketClose (int32_t socket)\n\\details\nThe function \\b ARM_WIFI_SocketClose closes an existing socket and releases the socket descriptor.\nFurther references to \\em socket fail with \\c ARM_SOCKET_EINVAL error code.\n\nThe argument \\em socket specifies a socket identification number returned from a previous call\nto \\ref ARM_WIFI_SocketCreate.\n\nIn blocking mode, which is enabled by default, this function will wait until a socket is closed.\nIn non blocking mode, you must call the \\b ARM_WIFI_SocketClose function again if the error code\n\\c ARM_SOCKET_EAGAIN is returned.\n\n\\b Example:\n - see \\ref ARM_WIFI_SocketListen\n*/\n\nint32_t ARM_WIFI_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len) {\n  return 0;\n}\n/**\n\\fn int32_t ARM_WIFI_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len)\n\\details\nThe function \\b ARM_WIFI_SocketGetHostByName retrieves host information corresponding to\na host name from a host database. It does this by sending DNS requests to the DNS server.\nThe IP address of the DNS server is specified in the network interface configuration or can be\nobtained from the DHCP server for the local area network.\n\nThe argument \\a name is a pointer to the \\token{null}-terminated name of the host to resolve.\n\nThe argument \\em af specifies the address family, that is, which type of IP address you want\nto resolve. The following values are supported:\nFamily                       | Description\n:----------------------------|:-------------------------------------------------\n\\ref ARM_SOCKET_AF_INET      | Resolve the IPv4 address\n\\ref ARM_SOCKET_AF_INET6     | Resolve the IPv6 address\n\nThe argument \\em ip is a pointer to the buffer that will receive the resolved IP address of the host.\nIf the argument \\em ip is \\token{NULL}, the function returns error.\n\nThe argument \\em ip_len is a pointer to the IP address length. It should initially contain the amount of\nspace pointed to by \\em ip. On return it contains the actual length of the address returned in bytes.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\n \nvoid ping_arm_com (void) {\n  uint8_t ip[4];\n  uint32_t ip_len;\n  int32_t res;\n \n  wifi = &Driver_WiFi0;\n  ip_len = sizeof(ip);\n  res = wifi->SocketGetHostByName (\"www.arm.com\", ARM_SOCKET_AF_INET, (uint8_t *)ip, &ip_len);\n  if (res == ARM_DRIVER_OK) {\n    res = wifi->Ping ((uint8_t *)ip, sizeof(ip));\n    if (res == ARM_DRIVER_OK) {\n      // \"www.arm.com\" responded to ping  \n    }\n  }\n  else {\n    // \"www.arm.com\" not resolved\n  }\n}\n\\endcode\n*/\n\nint32_t ARM_WIFI_Ping (const uint8_t *ip, uint32_t ip_len) {\n  return ARM_DRIVER_OK;\n}\n/**\n\\fn int32_t ARM_WIFI_Ping (const uint8_t *ip, uint32_t ip_len)\n\\details\nThe function \\b ARM_WIFI_Ping checks if the remote host is reachable. It does this by sending \nan echo request and waiting for an echo response. The function then returns the result\nof the operation. Check the \\ref ARM_WIFI_CAPABILITIES of the driver, if this function\nis supported in the driver implementation.\n\nThe argument \\em ip is a pointer to the buffer containing the IP address octets of the host to ping.\n\nThe argument \\em ip_len specifies the length of the IP address. The length is \\token{4} bytes\nfor the IPv4 address and \\token{16} bytes for the IPv6 address.\n \n\\note\nThe host availability check fails, if the remote host does not respond to echo requests,\nor intermediate routers do not forward the echo requests or echo responses.\n\n\\b Example:\n\\code\nextern ARM_DRIVER_WIFI Driver_WiFi0;\nstatic ARM_DRIVER_WIFI *wifi;\n \nvoid ping_host (void) {\n  uint8_t ip[4] = { 192U, 168U, 0U, 100U };\n  int32_t res;\n \n  wifi = &Driver_WiFi0;\n  res = wifi->Ping ((uint8_t *)ip, sizeof(ip));\n  if (res == ARM_DRIVER_OK) {\n    // Host responded\n  }\n}\n\\endcode\n*/\n/**\n@}\n*/\n// end group wifi_socket_gr\n\n\n/**\n@}\n*/\n// End WiFi Interface\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/Flash_Demo.c",
    "content": "#include \"Driver_Flash.h\"\n#include \"cmsis_os2.h\"                  // ARM::CMSIS:RTOS2:Keil RTX5\n   \n/* Flash driver instance */\nextern ARM_DRIVER_FLASH Driver_Flash0;\nstatic ARM_DRIVER_FLASH * flashDev = &Driver_Flash0;\n \n/* CMSIS-RTOS2 Thread Id */\nosThreadId_t Flash_Thread_Id;\n \n/* Flash signal event */\nvoid Flash_Callback(uint32_t event)\n{\n  if (event & ARM_FLASH_EVENT_READY) {\n    /* The read/program/erase operation is completed */\n    osThreadFlagsSet(Flash_Thread_Id, 1U);\n  }\n  if (event & ARM_FLASH_EVENT_ERROR) {\n    /* The read/program/erase operation is completed with errors */\n    /* Call debugger or replace with custom error handling */\n    __breakpoint(0);  \n  }\n} \n \n/* CMSIS-RTOS2 Thread */ \nvoid Flash_Thread (void *argument)\n{\n  /* Query drivers capabilities */\n  const ARM_FLASH_CAPABILITIES capabilities = flashDev->GetCapabilities();\n \n  /* Initialize Flash device */\n  if (capabilities.event_ready) {\n    flashDev->Initialize (&Flash_Callback);\n  } else {\n    flashDev->Initialize (NULL);\n  }\n  \n  /* Power-on Flash device */\n  flashDev->PowerControl (ARM_POWER_FULL);\n  \n  /* Read data taking data_width into account */\n  uint8_t buf[256U];\n  flashDev->ReadData (0x1000U, buf, sizeof(buf)>>capabilities.data_width);\n  \n  /* Wait operation to be completed */\n  if (capabilities.event_ready) {\n    osThreadFlagsWait (1U, osFlagsWaitAny, 100U);\n  } else {\n    osDelay(100U);\n  }\n  \n  /* Switch off gracefully */\n  flashDev->PowerControl (ARM_POWER_OFF);\n  flashDev->Uninitialize ();\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/General.txt",
    "content": "/**\n\\mainpage Overview\n\nThe CMSIS-Driver specification is a software API that describes peripheral driver interfaces for middleware stacks and user\napplications. The CMSIS-Driver API is designed to be generic and independent of a specific RTOS making it reusable across a\nwide range of supported microcontroller devices. The CMSIS-Driver API covers a wide range of use cases for the supported\nperipheral types, but can not take every potential use-case into account. Over time, it is indented to extend the\nCMSIS-Driver API with further groups to cover new use-cases.\n\nThe CMSIS Software Pack publishes the API Interface under the Component Class \\b CMSIS \\b Driver with header files and a\ndocumentation. These header files are the reference for the implementation of the standardized peripheral driver interfaces. \nThese implementations are published typically in the Device Family Pack of a related microcontroller family under the\nComponent Class \\b CMSIS \\b Driver. A Device Family Pack may contain additional interfaces in the Component Class \\b Device\nto extend the standard Peripheral Drivers covered by this CMSIS-Driver specification with additional device specific\ninterfaces for example for Memory BUS, GPIO, or DMA.\n\nThe standard peripheral driver interfaces connect microcontroller peripherals for example with middleware that implements\ncommunication stacks, file systems, or graphic user interfaces. Each peripheral driver interface may provide multiple\ninstances reflecting the multiple physical interfaces of the same type in a device. For example the two physical SPI\ninterfaces are reflected with a separate \\ref AccessStruct for SPI1 and SPI2. The \\ref AccessStruct is the interface of a\ndriver to the middleware component or the user application.\n\n\\image html driver.png  \"Peripheral Driver Interfaces and Middleware\"\n\nThe following CMSIS-Driver API groups are defined:\n  - \\ref can_interface_gr \"CAN\": Interface to CAN bus peripheral.\n  - \\ref eth_interface_gr \"Ethernet\": Interface to Ethernet MAC and PHY peripheral.\n  - \\ref i2c_interface_gr \"I2C\": Multi-master Serial Single-Ended Bus interface driver.\n  - \\ref mci_interface_gr \"MCI\": Memory Card Interface for SD/MMC memory.\n  - \\ref nand_interface_gr \"NAND\": NAND Flash Memory interface driver.\n  - \\ref flash_interface_gr \"Flash\": Flash Memory interface driver.\n  - \\ref sai_interface_gr \"SAI\": Serial audio interface driver (I2s, PCM, AC'97, TDM, MSB/LSB Justified).\n  - \\ref spi_interface_gr \"SPI\": Serial Peripheral Interface Bus driver.\n  - \\ref storage_interface_gr \"Storage\": Storage device interface driver.\n  - \\ref usart_interface_gr \"USART\": Universal Synchronous and Asynchronous Receiver/Transmitter interface driver.\n  - \\ref usb_interface_gr \"USB\": Interface driver for USB Host and USB Device communication.\n  - \\ref vio_interface_gr \"VIO\": API for virtual I/Os (VIO).\n  - \\ref wifi_interface_gr \"WiFi\": Interface driver for wireless communication.\n\nA list of current CMSIS-Driver implementations is available \\ref listOfImplementations \"here\".\n\n\\note Usually, WiFi chips and modules have their own networking stack incorporated. This means that payload data is sent via\na serial interface (SPI or USART) to the WiFi chip/module and the Ethernet frames are assembled inside. If you intend to use\na TCP/IP stack from a middleware component with a WiFi chip/module, make sure that the WiFi driver has a \\ref wifi_bypass_gr.\nThis allows to send the Ethernet frames assembled by the TCP/IP component transparently through the WiFi chip/module.\n\n<hr>\n\nCMSIS-Driver in ARM::CMSIS Pack\n-------------------------------\n\nThe following files relevant to CMSIS-Driver are present in the <b>ARM::CMSIS</b> Pack directories:\n| Directory                      | Content                                                                |\n|--------------------------------|------------------------------------------------------------------------|\n|\\b CMSIS/Documentation/Driver   | This documentation                                                     |\n|\\b CMSIS/Driver/Include         | Driver header files (Driver_<i>interface</i>.h, Driver_Common.h)       |\n|\\b CMSIS/Driver/DriverTemplates | Driver implementation template files (Driver_<i>interface</i>.c)       |\n\n<hr>\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page driver_revisionHistory Revision History of CMSIS-Driver\n\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>2.8.0</td>\n      <td>\n        - Changed: removed volatile from status related typedefs APIs\n        - Enhanced WiFi Interface API with support for polling Socket Receive/Send\n        - Added VIO API 0.1.0 (Preview)\n      </td>\n    </tr>\n    <tr>\n      <td>2.7.1</td>\n      <td>\n        - Finalized WiFi Interface API 1.0.0.\n      </td>\n    </tr>\n    <tr>\n      <td>2.7.0</td>\n      <td>\n        - Added WiFi Interface API 1.0.0-beta.\n        - Added custom driver selection to simplify implementation of new CMSIS-Driver.\n      </td>\n    </tr>\n    <tr>\n      <td>2.6.0</td>\n      <td>\n        - Enhanced CAN-Driver API with explicit BUSOFF state.\n        - Enhanced NAND-Driver API for ECC handling.\n      </td>\n    </tr>\n    <tr>\n      <td>2.05</td>\n      <td>\n        - Changed: All typedefs related to status have been made volatile. \n      </td>\n    </tr>\n    <tr>\n      <td>2.04</td>\n      <td>\n        - Added: template files for CAN interface driver.\n      </td>\n    </tr>\n    <tr>\n      <td>2.03</td>\n      <td>\n        - Added: CAN API for an interface to CAN peripherals\n        - Added: Overview of the \\ref driverValidation \"CMSIS-Driver Validation\" Software Pack.\n        - Enhanced: documentation and clarified behavior of the \\ref CallSequence.\n      </td>\n    </tr>\n    <tr>\n      <td>2.02</td>\n      <td>\n        - Minor API changes, for exact details refer to the header file of each driver.\n        - Added: Flash Interface, NAND interface.\n      </td>\n    </tr>\n    <tr>\n      <td>2.00</td>\n      <td>API with non-blocking data transfer, independent of CMSIS-RTOS.</td>\n    </tr>\n    <tr>\n      <td>1.10</td>\n      <td>Initial release</td>\n    </tr>\n</table>\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page listOfImplementations CMSIS-Driver Implementation List\n\nThe following table shows a list of current CMSIS-Driver implementations. It is regularly updated, so it is subject to change.\n\n[CAN]: \\ref can_interface_gr \"CAN\"\n[Ethernet MAC]: \\ref eth_mac_interface_gr \"Ethernet MAC\".\n[Ethernet PHY]: \\ref eth_phy_interface_gr \"Ethernet PHY\".\n[I2C]: \\ref i2c_interface_gr \"I2C\".\n[MCI]: \\ref mci_interface_gr \"MCI\".\n[NAND]: \\ref nand_interface_gr \"NAND\".\n[Flash]: \\ref flash_interface_gr \"Flash\".\n[SAI]: \\ref sai_interface_gr \"SAI\".\n[SPI]: \\ref spi_interface_gr \"SPI\".\n[Storage]: \\ref storage_interface_gr \"Storage\".\n[USART]: \\ref usart_interface_gr \"USART\".\n[USB Host]: \\ref usbh_interface_gr \"USB Host\".\n[USB Device]: \\ref usbd_interface_gr \"USB Device\".\n[VIO]: \\ref vio_interface_gr \"VIO\".\n[WiFi]: \\ref wifi_interface_gr \"WiFi\"\n\n<table class=\"cmtable\" summary=\"CMSIS-Driver Implementation List\">\n        <tr>\n            <th>Vendor</th>\n            <th>Device/Family</th>\n            <th>[CAN]</th>\n            <th>[Ethernet MAC]</th>\n            <th>[Ethernet PHY]</th>\n            <th>[I2C]</th>\n            <th>[MCI]</th>\n            <th>[NAND]</th>\n            <th>[Flash]</th>\n            <th>[SAI]</th>\n            <th>[SPI]</th>\n            <th>[Storage]</th>\n            <th>[USART]</th>\n            <th>[USB Host]</th>\n            <th>[USB Device]</th>\n            <th>[VIO]</th>\n            <th>[WiFi]</th>\n        </tr>\n        <tr>\n            <td>Arm</td>\n            <td>Musca-A1</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>Musca-B1</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>Musca-S1</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>SSE-200</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>SSE-300</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>SSE-310</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td>Espressif</td>\n            <td>ESP32</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>ESP8266</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n        </tr>\n        <tr>\n            <td>Infineon</td>\n            <td>S29GL064Nx2</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>XMC1000</td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>XMC4000</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td>Inventek</td>\n            <td>ISM43362</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n        </tr>\n        <tr>\n            <td>Microchip</td>\n            <td>KSZ8061RNA</td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>KSZ8061RNB</td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>KSZ8851SNL</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LAN8710A</td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LAN8720</td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LAN8742A</td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LAN8740A</td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LAN91C111</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LAN9220</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td>Micron</td>\n            <td>M29EW28F128</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>M29W640FB</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td>NXP</td>\n            <td>LPC1500</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC1700</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC1800</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC4000</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC4300</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>i.MXRT105x</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>i.MXRT1060</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>i.MXRT1064</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>K32L2A31A</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>K32L2A41A</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>K32L2B11A</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>K32L2B21A</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>K32L2B31A</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>K32L3A60</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC51U68</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54005</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54016</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54018M</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54018</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54102</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54113</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54114</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54605</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54606</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54607</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54608</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54616</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54618</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54628</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54S005</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54S016</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54S018M</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC54S018</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5502</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5504</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5506</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5512</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5514</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5516</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5526</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5528</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5534</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC5536</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC55S04</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC55S06</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC55S14</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC55S16</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC55S26</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC55S28</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC55S36</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC55S66</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>LPC55S69</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMX8MD6</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMX8MD7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMX8MQ5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMX8MQ6</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMX8MQ7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1011</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1015</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1021</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1024</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1051</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1052</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1061</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1061X</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1062</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1062X</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1064</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1165</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1166</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1173</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1175</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT1176</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT533S</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT555S</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT595S</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT633S</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MIMXRT685S</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK02F12810</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK11D5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK11DA5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK12D5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK21D5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK21DA5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK21F12</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK21FA12</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK22D5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK22F12810</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK22F12</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK22F25612</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK22F51212</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK22FA12</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK24F12</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK24F25612</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK26F18</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK27F15</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK27FA15</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK28F15</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK28FA15</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK63F12</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK64F12</td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK65F18</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK66F18</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK80F25615</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MK82F25615</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE02Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE04Z1284</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE04Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE06Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE12Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE13Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE14F16</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE14Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE14Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE15Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE15Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE16F16</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE16Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE17Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKE18F16</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL02Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL03Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL13Z644</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL17Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL17Z644</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL26Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL27Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL27Z644</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL28Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL33Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL33Z644</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL34Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL36Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL43Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL46Z4</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKL82Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKM14ZA5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKM33ZA5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKM34Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKM34ZA5</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKM35Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKS20F12</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKS22F12</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV10Z1287</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV10Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV11Z7</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV30F12810</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV31F12810</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV31F25612</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV31F51212</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV42F16</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV44F16</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV46F16</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV56F24</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>MKV58F24</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>S32K3</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td>Qualcomm</td>\n            <td>QCA400x</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n        </tr>\n        <tr>\n            <td>Redpine</td>\n            <td>RS13100</td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>RS14100</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td>Renesas</td>\n            <td>AT45DB641E</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>AT45DB642D</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>DA16200</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n        </tr>\n        <tr>\n            <td>STMicroelectronics</td>\n            <td>STM32F0xx</td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32F1xx</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32F2xx</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32F3xx</td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32F4xx</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32F7xx</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32G0xx</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32G4xx</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32H7xx</td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32L0xx</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32L1xx</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32L4xx</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32L5xx</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>STM32U5xx</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td></td>\n            <td>ST802RT1</td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td>Texas Instruments</td>\n            <td>DP82848C</td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n        </tr>\n        <tr>\n            <td>WizNet</td>\n            <td>WizFi360</td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td></td>\n            <td><center>&radic;</center></td>\n        </tr>\n</table>\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page theoryOperation Theory of Operation\n[TOC]\n\nThis section gives an overview of the general operation of CMSIS-Drivers. It explains the \\ref DriverFunctions that are\ncommon in all CMSIS-Drivers along with the \\ref CallSequence. The topic \\ref Data_Xfer_Functions describes how data\nread/write operations to the peripheral are implemented.\n\nEach CMSIS-Driver defines an \\ref AccessStruct for calling the various driver functions and each peripheral (that is accessed\nvia a CMSIS-Driver) has one \\ref DriverInstances \"Driver Instance\".\n\n\n\\section DriverFunctions Common Driver Functions\n\nEach CMSIS-Driver contains these functions:\n\n - \\b GetVersion: can be called at any time to obtain version information of the driver interface.\n \n - \\b GetCapabilities: can be called at any time to obtain capabilities of the driver interface.\n \n - \\b Initialize: must be called before powering the peripheral using \\b PowerControl. This function performs the following:\n     - allocate I/O resources.\n     - register an optional \\b SignalEvent callback function.\n\n - \\b SignalEvent: is an optional callback function that is registered with the \\b Initialize function. This callback\n   function is initiated from interrupt service routines and indicates hardware events or the completion of a data block\n   transfer operation.\n\n - \\b PowerControl: Controls the power profile of the peripheral and needs to be called after \\b Initialize. Typically, three\n   power options are available:\n     - \\c ARM_POWER_FULL: Peripheral is turned on and fully operational. The driver initializes the peripheral registers, interrupts, and (optionally) DMA.\n     - \\c ARM_POWER_LOW: (optional) Peripheral is in low power mode and partially operational; usually, it can detect\n       external events and wake-up.\n     - \\c ARM_POWER_OFF: Peripheral is turned off and not operational (pending operations are terminated). This is the state\n       after device reset.\n \n - \\b Uninitialize: Complementary function to Initialize. Releases the I/O pin resources used by the interface.\n\n - \\b Control: Several drivers provide a control function to configure communication parameters or execute miscellaneous\n   control functions.\n\nThe section \\ref CallSequence contains more information on the operation of each function. Additional functions are specific\nto each driver interface and are described in the individual sections of each driver.\n\n\\subsection ProcessorMode Cortex-M Processor Mode\n\nThe CMSIS-Driver functions access peripherals and interrupts and are designed to execute in \\b Privileged mode.\nWhen calling CMSIS-Driver functions from RTOS threads, it should be ensure that these threads execute in \\b Privileged mode.\n\n\n\\section CallSequence Function Call Sequence\n\nFor normal operation of the driver, the API functions \\b GetVersion, \\b GetCapabilities, \\b Initialize, \\b PowerControl, \\b Uninitialize are \ncalled in the following order:\n\n\\msc\n a [label=\"\", textcolor=\"indigo\", linecolor=\"indigo\", arclinecolor=\"indigo\"],\n b [label=\"\", textcolor=\"blue\", linecolor=\"blue\", arclinecolor=\"blue\"];\n\n a rbox a [label=\"Middleware\", linecolor=\"indigo\"],\n b rbox b [label=\"Driver\", linecolor=\"blue\"];\n --- [label=\"Verify API version\"];\n a=>b [label=\"GetVersion ()\", textcolor=\"gray\", linecolor=\"gray\"];\n --- [label=\"Obtain driver features\"];\n a=>b [label=\"GetCapabilities (...)\", textcolor=\"gray\", linecolor=\"gray\"];\n ---  [label=\"Setup software resources\"];\n a=>b [label=\"Initialize (...)\", textcolor=\"red\", linecolor=\"red\"];\n --- [label=\"Setup the peripheral\"];\n a=>b  [label=\"PowerControl (ARM_POWER_FULL)\", textcolor=\"red\", linecolor=\"red\"];\n --- [label=\"Operate with the peripheral\"];\n a=>b [label=\"Data Transfer Functions\"];\n a<=b  [label=\"SignalEvent (...)\"];\n --- [label=\"Wait for external hardware events\"];\n a=>b  [label=\"PowerControl (ARM_POWER_LOW)\"];\n a<=b  [label=\"SignalEvent (...)\"];\n --- [label=\"Stop working with peripheral\"];\n a=>b [label=\"PowerControl (ARM_POWER_OFF)\", textcolor=\"red\", linecolor=\"red\"];\n a=>b [label=\"Uninitialize (...)\", textcolor=\"red\", linecolor=\"red\"];\n\\endmsc\n\nThe functions \\b GetVersion and \\b GetCapabilities can be called any time to obtain the required information from the driver.\nThese functions return always the same information.\n\n\n\\subsection CS_start Start Sequence\n\nTo start working with a peripheral the functions \\b Initialize and \\b PowerControl need to be called in this order:\n\\code\n  drv->Initialize (...);                 // Allocate I/O pins\n  drv->PowerControl (ARM_POWER_FULL);    // Power up peripheral, setup IRQ/DMA\n\\endcode\n\n- \\b Initialize typically allocates the I/O resources (pins) for the peripheral. The function can be called multiple times;\n  if the I/O resources are already initialized it performs no operation and just returns with \\ref ARM_DRIVER_OK.\n- \\b PowerControl (\\c ARM_POWER_FULL) sets the peripheral registers including interrupt (NVIC) and optionally DMA.\n  The function can be called multiple times; if the registers are already set it performs no operation and just returns with \\ref ARM_DRIVER_OK.\n  \n\\subsection CS_stop Stop Sequence\n\nTo stop working with a peripheral the functions \\b PowerControl and \\b Uninitialize need to be called in this order:\n\\code\n  drv->PowerControl (ARM_POWER_OFF);     // Terminate any pending transfers, reset IRQ/DMA, power off peripheral\n  drv->Uninitialize (...);               // Release I/O pins\n\\endcode\nThe functions \\b PowerControl and \\b Uninitialize always execute and can be used to put the peripheral into a <b>Safe State</b>,\nfor example after any data transmission errors.  To restart the peripheral in a error condition, you should first execute\nthe \\ref CS_stop and then the \\ref CS_start.\n\n- \\b PowerControl (\\c ARM_POWER_OFF) terminates any pending data transfers with the peripheral, disables the peripheral and \n  leaves it in a defined mode (typically the reset state).\n    - when DMA is used it is disabled (including the interrupts)\n    - peripheral interrupts are disabled on NVIC level\n    - the peripheral is reset using a dedicated reset mechanism (if available) or by clearing the peripheral registers\n    - pending peripheral interrupts are cleared on NVIC level\n    - driver variables are cleared\n- \\b Uninitialize always releases I/O pin resources.\n\n\\section Share_IO Shared I/O Pins\n\nAll CMSIS-Driver provide a \\ref CS_start and \\ref CS_stop. Therefore two different drivers can share the same I/O pins, \nfor example UART1 and SPI1 can have overlapping I/O pins. In this case the communication channels can be used as shown below:\n\n\\code \n  SPI1drv->Initialize (...);                // Start SPI1\n  SPI1drv->PowerControl (ARM_POWER_FULL);\n   ...                                      // Do operations with SPI1\n  SPI1drv->PowerControl (ARM_POWER_OFF);    // Stop SPI1\n  SPI1drv->Uninitialize ();\n   ...\n  USART1drv->Initialize (...);              // Start USART1\n  USART1drv->PowerControl (ARM_POWER_FULL);\n   ...                                      // Do operations with USART1\n  USART1drv->PowerControl (ARM_POWER_OFF);  // Stop USART1\n  USART1drv->Uninitialize ();\n\\endcode\n \n\\section Data_Xfer_Functions Data Transfer Functions\n\nA CMSIS-Driver implements non-blocking functions to transfer data to a peripheral. This means that the driver configures the\nread or write access to the peripheral and instantly returns to the calling application.  The function names for data\ntransfer end with:\n - \\b Send to write data to a peripheral.\n - \\b Receive to read data from a peripheral.\n - \\b Transfer to indicate combined read/write operations to a peripheral.\n\nDuring a data transfer, the application can query the number of transferred data items using functions named\n<b>Get<i>xxx</i>Count</b>. On completion of a data transfer, the driver calls a callback function with a specific event code.\n\nDuring the data exchange with the peripheral, the application can decide to:\n - Wait (using an RTOS scheduler) for the callback completion event. The RTOS is controlled by the application code which\n   makes the driver itself RTOS independent.\n - Use polling functions that return the number of transferred data items to show progress information or partly read or fill\n   data transfer buffers.\n - Prepare another data transfer buffer for the next data transfer.\n \nThe following diagram shows the basic communication flow when using the \\b _Send function in an application.\n\n\\image html Non_blocking_transmit_small.png  \"Non-blocking Send Function\"\n\n\\section AccessStruct Access Struct\n\nA CMSIS-Driver publishes an \\ref AccessStruct with the data type name ARM_DRIVER_xxxx that gives to access the driver\nfunctions.\n\n\\b Code \\b Example: \\b Function \\b Access \\b of \\b the \\b SPI \\b driver\n\\code\ntypedef struct _ARM_DRIVER_SPI {\n  ARM_DRIVER_VERSION   (*GetVersion)      (void);\n  ARM_SPI_CAPABILITIES (*GetCapabilities) (void);\n  int32_t              (*Initialize)      (ARM_SPI_SignalEvent_t cb_event);\n  int32_t              (*Uninitialize)    (void);\n  int32_t              (*PowerControl)    (ARM_POWER_STATE state);\n  int32_t              (*Send)            (const void *data, uint32_t num);\n  int32_t              (*Receive)         (      void *data, uint32_t num);\n  int32_t              (*Transfer)        (const void *data_out, void *data_in, uint32_t num);\n  uint32_t             (*GetDataCount)    (void);\n  int32_t              (*Control)         (uint32_t control, uint32_t arg);\n  ARM_SPI_STATUS       (*GetStatus)       (void);\n} const ARM_DRIVER_SPI;\n\\endcode\n\n\\subsection DriverInstances Driver Instances\n\nA device may offer several peripherals of the same type. For such devices, the CMSIS-Driver publishes multiple instances\nof the \\ref AccessStruct. The name of each driver instance reflects the names of the peripheral available in the device.\n\n\\b Code \\b Example: \\ref AccessStruct \\b for \\b three \\b SPIs \\b in \\b a \\b microcontroller \\b device.\n\\code\nARM_DRIVER_SPI Driver_SPI1;     // access functions for SPI1 interface\nARM_DRIVER_SPI Driver_SPI2;     // access functions for SPI2 interface\nARM_DRIVER_SPI Driver_SPI3;     // access functions for SPI3 interface\n\\endcode\n\nThe access functions can be passed to middleware to specify the driver instance that the middleware should use for communication.\n\n\\b Naming \\b Convention\n\nThe access structs need to follow this naming convention: the keyword \"Driver\" followed by an underscore \"_\", the interface\nname \"IFNAME\" (usually in upper case letters), and the instance number \"n\". Here's the full list of access struct names for\nall drivers (n to be replaced with the actual instance number):\n\\code\nDriver_CANn\nDriver_ETH_MACn\nDriver_ETH_PHYn\nDriver_Flashn\nDriver_I2Cn\nDriver_MCIn\nDriver_NANDn\nDriver_SAIn\nDriver_SPIn\nDriver_Storagen\nDriver_USARTn\nDriver_USBDn\nDriver_USBHn\nDriver_WiFin\n\\endcode\n\n\n\\b Example:\n\\code\nvoid init_middleware (ARM_DRIVER_SPI *Drv_spi) ...\n\\\\ inside the middleware the SPI driver functions are called with:\n\\\\   Drv_spi->function (...);\n\\endcode\n \n\\code\n\\\\ setup middleware\ninit_middleware (&Driver_SPI1);      // connect middleware to SPI1 interface\n  :\ninit_middleware (&Driver_SPI2);      // connect middleware to SPI2 interface\n\\endcode\n\n\n\\section DriverConfiguration Driver Configuration\n\nFor a device family, the drivers may be configurable. The \\ref referenceImplementation stores configuration options in a\ncentral file with the name \\b RTE_Device.h. However, the configuration of the drivers itself is not part of the CMSIS-Driver\nspecification.\n\n\\section CodeExample Code Example\n\nThe following example code shows the usage of the SPI interface.\n\n\\include SPI_Demo.c\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page referenceImplementation Reference Implementation\n\nThe API of the CMSIS-Drivers is published in the \\ref DriverHeaderFiles.\n\nTo simplify the development of a CMSIS-Driver both \\ref DriverTemplates and \\ref DriverExamples are provided.\n\nARM offers also a Software Pack for CMSIS-Driver Validation as described in \\ref driverValidation.\n\n\\section DriverHeaderFiles Driver Header Files\n\nThe API of each CMSIS-Driver is published in a header file. It is recommended to include the header file that is part of the\nCMSIS specification in the implementation file of the CMSIS-Driver. \n\nThe following header files are available in the directory <b>.\\\\CMSIS\\\\Driver\\\\Include</b>.\n\n| Header File          | Description\n|----------------------|-------------------------\n| %Driver_Common.h     | \\ref common_drv_gr\n| %Driver_CAN.h        | \\ref can_interface_gr\n| %Driver_ETH.h        | \\ref eth_interface_gr\n| %Driver_ETH_MAC.h    | \\ref eth_mac_interface_gr\n| %Driver_ETH_PHY.h    | \\ref eth_phy_interface_gr\n| %Driver_Flash.h      | \\ref flash_interface_gr\n| %Driver_I2C.h        | \\ref i2c_interface_gr\n| %Driver_MCI.h        | \\ref mci_interface_gr\n| %Driver_NAND.h       | \\ref nand_interface_gr\n| %Driver_SPI.h        | \\ref spi_interface_gr\n| %Driver_Storage.h    | \\ref storage_interface_gr\n| %Driver_SAI.h        | \\ref sai_interface_gr\n| %Driver_USART.h      | \\ref usart_interface_gr\n| %Driver_USB.h        | \\ref usb_interface_gr\n| %Driver_USBD.h       | \\ref usbd_interface_gr\n| %Driver_USBH.h       | \\ref usbh_interface_gr\n| %Driver_WiFi.h       | \\ref wifi_interface_gr\n\n\n\\section DriverTemplates Driver Template Files\n\nDriver template files are code skeletons that provide the structure of a CMSIS-Driver.  The following templates are \navailable in the directory <b>.\\\\CMSIS\\\\Driver\\\\DriverTemplates</b>.\n\n| Source File       | Description\n|-------------------|------------------------------------\n| %Driver_CAN.c     | \\ref can_interface_gr\n| %Driver_ETH_MAC.c | \\ref eth_mac_interface_gr\n| %Driver_ETH_PHY.c | \\ref eth_mac_interface_gr\n| %Driver_Flash.c   | \\ref flash_interface_gr\n| %Driver_I2C.c     | \\ref i2c_interface_gr\n| %Driver_MCI.c     | \\ref mci_interface_gr\n| %Driver_SAI.c     | \\ref sai_interface_gr\n| %Driver_SPI.c     | \\ref spi_interface_gr\n| %Driver_Storage.c | \\ref storage_interface_gr\n| %Driver_USART.c   | \\ref usart_interface_gr\n| %Driver_USBD.c    | \\ref usbd_interface_gr\n| %Driver_USBH.c    | \\ref usbh_interface_gr\n\n\n\\section DriverExamples Driver Examples\n\nThe driver examples are full working CMSIS-Drivers that may be adapted to a different hardware. Examples are currently\navailable for the NXP LPC1800 series and provide the implementation of a complete CMSIS-Driver. The following examples are \navailable in the directory <b>.\\\\CMSIS\\\\Pack\\\\Example\\\\CMSIS_Driver</b>.\n\n| Source File       | Header File       | Description\n|-------------------|-------------------|-------------------------------\n| %EMAC_LPC18xx.c   | %EMAC_LPC18xx.h   | \\ref eth_mac_interface_gr\n| %SSP_LPC18xx.c    | %SSP_LPC18xx.h    | \\ref spi_interface_gr\n| %I2C_LPC18xx.c    | %I2C_LPC18xx.h    | \\ref i2c_interface_gr\n| %I2S_LPC18xx.c    | %I2S_LPC18xx.h    | \\ref sai_interface_gr\n| %MCI_LPC18xx.c    | %MCI_LPC18xx.h    | \\ref mci_interface_gr\n| %USART_LPC18xx.c  | %USART_LPC18xx.h  | \\ref usart_interface_gr\n| %USBn_LPC18xx.c   | %USB_LPC18xx.h    | common files for \\ref usbd_interface_gr and \\ref usbh_interface_gr\n| %USBDn_LPC18xx.c  | <i>none</i>       | \\ref usbd_interface_gr\n| %USBHn_LPC18xx.c  | <i>none</i>       | \\ref usbh_interface_gr\n\n\nThese CMSIS-Drivers use additional modules for GPIO and DMA control:\n\n| Source File       | Header File      | Description\n|-------------------|------------------|---------------------------------------\n| %GPIO_LPC18xx.c   | %GPIO_LPC18xx.h  | GPIO Interface for LPC1800 series\n| %GPDMA_LPC18xx.c  | <i>none</i>      | DMA Interface for LPC1800 series\n| %SCU_LPC18xx.c    | %SCU_LPC18xx.h   | SCU Interface for LPC1800 series\n\nThe CMSIS-Drivers for the LPC1800 device have also many configuration options that are controls using \\#define statements in\nthe file <b>.\\\\CMSIS\\\\Pack\\\\Example\\\\CMSIS_Driver\\\\Config\\\\RTE_Device.h</b>. Using this file, the I/O pin and DMA assignment\ncan be set among other parameters such as USB speed and PHY interfaces. \n\nFurther driver reference implementations are available in Device Family Packs (DFP) labeled with version 2.0.0 or higher. \n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page driverValidation Driver Validation\n\nThe <a href=\"https://www.keil.com/pack/\" target=_blank>Software Pack</a> named <b>ARM::CMSIS-Driver_Validation</b> contains the following:\n\n - Source code of a CMSIS-Driver Validation Suite along with configuration file.\n - Documentation of the CMSIS-Driver Validation Suite.\n - Examples that shows the usage of the CMSIS-Driver Validation Suite on various target platforms.\n\nThe CMSIS-Driver Validation Suite performs the following tests:\n - Generic Validation of API function calls\n - Validation of Configuration Parameters\n - Validation of Communication with loopback tests\n - Validation of Communication Parameters such as baudrate\n - Validation of Event functions\n\nThe following CMSIS-Drivers can be tested with the current release:\n - \\ref can_interface_gr : with loop back test of communication.\n - \\ref eth_interface_gr : MAC and PHY with loop back test of communication.\n - \\ref i2c_interface_gr : only API and setup; does not test data transfer.\n - \\ref mci_interface_gr : only API and setup; does not test data transfer.\n - \\ref spi_interface_gr : with loop back test of communication.\n - \\ref usart_interface_gr : with loop back test of communication.\n - \\ref usbd_interface_gr : only API and setup; does not test data transfer.\n - \\ref usbh_interface_gr : only API and setup; does not test data transfer.\n - \\ref wifi_interface_gr : extensive tests for WiFi Driver.\n \nThe Driver Validation output can be printed to a console or saved in an XML file, via standard output (usually ITM).\n \n\\section test_output Sample Test Output\n\\verbatim\nCMSIS-Driver USART Test Report   Dec  6 2019   11:44:30 \n\nTEST 01: USART_GetCapabilities            PASSED\nTEST 02: USART_Initialization             PASSED\nTEST 03: USART_PowerControl               \n  DV_USART.c (301): [WARNING] Low power is not supported\n                                          PASSED\nTEST 04: USART_Config_PolarityPhase       PASSED\nTEST 05: USART_Config_DataBits            \n  DV_USART.c (387): [WARNING] Data Bits = 9 are not supported\n                                          PASSED\nTEST 06: USART_Config_StopBits            \n  DV_USART.c (425): [WARNING] Stop Bits = 1.5 are not supported\n  DV_USART.c (429): [WARNING] Stop Bits = 0.5 are not supported\n                                          PASSED\nTEST 07: USART_Config_Parity              PASSED\nTEST 08: USART_Config_Baudrate            PASSED\nTEST 09: USART_Config_CommonParams        PASSED\nTEST 10: USART_Send                       PASSED\nTEST 11: USART_AsynchronousReceive        PASSED\nTEST 12: USART_Loopback_CheckBaudrate     PASSED\nTEST 13: USART_Loopback_Transfer          PASSED\nTEST 14: USART_CheckInvalidInit           PASSED\n\nTest Summary: 14 Tests, 14 Passed, 0 Failed.\nTest Result: PASSED\n\\endverbatim\n\n\\section loop_back_setup Setup for Loop Back Communication\n\nTo perform loop back communication tests it is required to connect the input and the output of the peripherals as shown in this table:\n\nPeripheral       | Loop Back Configuration\n:----------------|:----------------------------\nEthernet         | Connect TX+ (Pin 1) with RX+ (Pin 3), TX- (Pin 2) with RX- (Pin 6)\nSPI              | Connect MISO to MOSI\nUSART            | Connect TX with RX\n\nThe following picture shows the necessary external loop back connections for the Keil MCBSTM32F400 evaluation board:\n - SPI: PB14 (SPI2_MISO) and PB15 (SPI2_MOSI)\n - USART: PB6 (USART1_TX) and PB7 (USART1_RX)\n - Ethernet: Pin 1 (TX+) and Pin 3 (RX+), Pin 2 (TX-) and Pin 6 (RX-) \n\n\\image html image006.png  \"Connections for Loop Back Communication Tests on Keil MCBSTM32F400\"\n\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/I2C_Demo.c",
    "content": "#include \"Driver_I2C.h\"\n \n#define EEPROM_I2C_ADDR       0x51      /* EEPROM I2C address */\n \n/* I2C driver instance */\nextern ARM_DRIVER_I2C            Driver_I2C0;\nstatic ARM_DRIVER_I2C *I2Cdrv = &Driver_I2C0;\n \nstatic volatile uint32_t I2C_Event;\n \n/* I2C Signal Event function callback */\nvoid I2C_SignalEvent (uint32_t event) {\n \n  /* Save received events */\n  I2C_Event |= event;\n \n  /* Optionally, user can define specific actions for an event */\n \n  if (event & ARM_I2C_EVENT_TRANSFER_INCOMPLETE) {\n    /* Less data was transferred than requested */\n  }\n \n  if (event & ARM_I2C_EVENT_TRANSFER_DONE) {\n    /* Transfer or receive is finished */\n  }\n \n  if (event & ARM_I2C_EVENT_ADDRESS_NACK) {\n    /* Slave address was not acknowledged */\n  }\n \n  if (event & ARM_I2C_EVENT_ARBITRATION_LOST) {\n    /* Master lost bus arbitration */\n  }\n \n  if (event & ARM_I2C_EVENT_BUS_ERROR) {\n    /* Invalid start/stop position detected */\n  }\n \n  if (event & ARM_I2C_EVENT_BUS_CLEAR) {\n    /* Bus clear operation completed */\n  }\n \n  if (event & ARM_I2C_EVENT_GENERAL_CALL) {\n    /* Slave was addressed with a general call address */\n  }\n \n  if (event & ARM_I2C_EVENT_SLAVE_RECEIVE) {\n    /* Slave addressed as receiver but SlaveReceive operation is not started */\n  }\n \n  if (event & ARM_I2C_EVENT_SLAVE_TRANSMIT) {\n    /* Slave addressed as transmitter but SlaveTransmit operation is not started */\n  }\n}\n\n/* Read I2C connected EEPROM (event driven example) */\nint32_t EEPROM_Read_Event (uint16_t addr, uint8_t *buf, uint32_t len) {\n  uint8_t a[2];\n \n  a[0] = (uint8_t)(addr >> 8);\n  a[1] = (uint8_t)(addr & 0xFF);\n\n  /* Clear event flags before new transfer */\n  I2C_Event = 0U;\n \n  I2Cdrv->MasterTransmit (EEPROM_I2C_ADDR, a, 2, true);\n \n  /* Wait until transfer completed */\n  while ((I2C_Event & ARM_I2C_EVENT_TRANSFER_DONE) == 0U);\n  /* Check if all data transferred */\n  if ((I2C_Event & ARM_I2C_EVENT_TRANSFER_INCOMPLETE) != 0U) return -1;\n \n  /* Clear event flags before new transfer */\n  I2C_Event = 0U;\n \n  I2Cdrv->MasterReceive (EEPROM_I2C_ADDR, buf, len, false);\n \n  /* Wait until transfer completed */\n  while ((I2C_Event & ARM_I2C_EVENT_TRANSFER_DONE) == 0U);\n  /* Check if all data transferred */\n  if ((I2C_Event & ARM_I2C_EVENT_TRANSFER_INCOMPLETE) != 0U) return -1;\n \n  return 0;\n}\n\n/* Read I2C connected EEPROM (pooling example) */\nint32_t EEPROM_Read_Pool (uint16_t addr, uint8_t *buf, uint32_t len) {\n  uint8_t a[2];\n \n  a[0] = (uint8_t)(addr >> 8);\n  a[1] = (uint8_t)(addr & 0xFF);\n \n  I2Cdrv->MasterTransmit (EEPROM_I2C_ADDR, a, 2, true);\n \n  /* Wait until transfer completed */\n  while (I2Cdrv->GetStatus().busy);\n  /* Check if all data transferred */\n  if (I2Cdrv->GetDataCount () != len) return -1;\n \n  I2Cdrv->MasterReceive (EEPROM_I2C_ADDR, buf, len, false);\n \n  /* Wait until transfer completed */\n  while (I2Cdrv->GetStatus().busy);\n  /* Check if all data transferred */\n  if (I2Cdrv->GetDataCount () != len) return -1;\n \n  return 0;\n}\n \n/* Initialize I2C connected EEPROM */\nint32_t EEPROM_Initialize (bool pooling) {\n  int32_t status;\n  uint8_t val;\n \n  if (pooling == true) {\n    I2Cdrv->Initialize (NULL);\n  } else {\n    I2Cdrv->Initialize (I2C_SignalEvent);\n  }\n  I2Cdrv->PowerControl (ARM_POWER_FULL);\n  I2Cdrv->Control      (ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_FAST);\n  I2Cdrv->Control      (ARM_I2C_BUS_CLEAR, 0);\n \n  /* Check if EEPROM can be accessed */\n  if (pooling == true) {\n    status = EEPROM_Read_Pool (0x00, &val, 1);\n  } else {\n    status = EEPROM_Read_Event (0x00, &val, 1);\n  }\n \n  return (status);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/I2C_SlaveDemo.c",
    "content": "#include \"Driver_I2C.h\"\n \n/* I2C driver instance */\nextern ARM_DRIVER_I2C            Driver_I2C0; \nstatic ARM_DRIVER_I2C *I2Cdrv = &Driver_I2C0;\n \nstatic volatile uint32_t I2C_Event;\n \n/* I2C Signal Event function callback */\nstatic void I2C_SignalEvent (uint32_t event) {\n  I2C_Event |= event;\n}\n \nint main (void) {\n  uint8_t cnt = 0;\n \n  /* Initialize I2C peripheral */\n  I2Cdrv->Initialize(I2C_SignalEvent);\n \n  /* Power-on I2C peripheral */\n  I2Cdrv->PowerControl(ARM_POWER_FULL);\n \n  /* Configure I2C bus */\n  I2Cdrv->Control(ARM_I2C_OWN_ADDRESS, 0x78);\n \n  I2C_Event = 0;\n\n  while (1) {\n    /* Receive chunk */\n    I2Cdrv->SlaveReceive(&cnt, 1);\n    while ((I2C_Event & ARM_I2C_EVENT_TRANSFER_DONE) == 0);\n    /* Clear transfer done flag */\n    I2C_Event &= ~ARM_I2C_EVENT_TRANSFER_DONE;\n \n    /* Transmit chunk back */\n    I2Cdrv->SlaveTransmit(&cnt, 1);\n    while ((I2C_Event & ARM_I2C_EVENT_TRANSFER_DONE) == 0);\n    /* Clear transfer done flag */\n    I2C_Event &= ~ARM_I2C_EVENT_TRANSFER_DONE;\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/MCI_Demo.c",
    "content": "\n#include \"Driver_MCI.h\"\n\n\n/* Usage example: ARM_MCI_Initialize ----------------------------------------*/\n\n// ARM_MCI_SignalEvent callback function prototype\nvoid MCI_SignalEvent_Callback (uint32_t event);\n\nvoid init_driver (ARM_DRIVER_MCI *drv) {\n  int32_t status;\n  \n  status = drv->Initialize (&MCI_SignalEvent_Callback);\n  \n  if (status != ARM_DRIVER_OK) {\n    // Initialization and event callback registration failed\n  }\n}\n\n/* Usage example: ARM_MCI_Uninitialize --------------------------------------*/\n\nvoid uninit_driver (ARM_DRIVER_MCI *drv) {\n  int32_t status;\n  \n  status = drv->Uninitialize ();\n  \n  if (status == ARM_DRIVER_OK) {\n    // Driver successfully uninitialized\n  }\n}\n\n/* Usage example: ARM_MCI_PowerControl --------------------------------------*/\n\nvoid control_driver_power (ARM_DRIVER_MCI *drv, bool enable) {\n  int32_t status;\n  \n  if (enable == true) {\n    status = drv->PowerControl (ARM_POWER_FULL);\n  }\n  else {\n    status = drv->PowerControl (ARM_POWER_OFF);\n  }\n  \n  if (status == ARM_DRIVER_OK) {\n    // Driver power enabled/disabled\n  }\n}\n\n/* Usage example: ARM_MCI_CardPower -----------------------------------------*/\n\nARM_MCI_CAPABILITIES drv_capabilities;\n\nvoid set_card_vdd_3v3 (ARM_DRIVER_MCI *drv) {\n  int32_t status;\n  \n  if (drv_capabilities.vdd == 1U) {\n    // Power switching to 3.3V supported\n    status = drv->CardPower (ARM_MCI_POWER_VDD_3V3);\n    \n    if (status == ARM_DRIVER_OK) {\n      // Card power set to 3.3V\n    }\n  }\n}\n\n/* Usage example: ARM_MCI_ReadCD --------------------------------------------*/\n\nvoid read_card_detect_state (ARM_DRIVER_MCI *drv) {\n  int32_t status;\n  \n  status = drv->ReadCD();\n  \n  if (status == 1) {\n    // Memory card is detected\n  }\n  else {\n    if (status == 0) {\n      // Memory card is not detected\n    }\n    else {\n      // Error reading card detect pin state\n    }\n  }\n}\n\n/* Usage example: ARM_MCI_ReadWP --------------------------------------------*/\n\nvoid read_write_protect_state (ARM_DRIVER_MCI *drv) {\n  int32_t status;\n  \n  status = drv->ReadWP();\n  \n  if (status == 1) {\n    // Memory card write protection is enabled\n  }\n  else {\n    if (status == 0) {\n      // Memory card write protection is disabled\n    }\n    else {\n      // Error reading write protect pin state\n    }\n  }\n}\n\n/* Usage example: ARM_MCI_SendCommand ---------------------------------------*/\n\nvolatile uint32_t MCI_Events;\n\nvoid MCI_SignalEvent_Callback (uint32_t event) {\n  // Save current event\n  MCI_Events |= event;\n}\n\nvoid send_CMD0 (ARM_DRIVER_MCI *drv) {\n  int32_t  status;\n  uint32_t cmd;\n\n  MCI_Events = 0U; //Clear MCI driver event flags\n  cmd = 0U;        // Set GO_IDLE_STATE command code\n\n  status = drv->SendCommand (cmd, 0U, ARM_MCI_CARD_INITIALIZE | ARM_MCI_RESPONSE_NONE, NULL);\n\n  if (status == ARM_DRIVER_OK) {\n    /* Wait for event */\n    while ((MCI_Events & ARM_MCI_EVENT_COMMAND_COMPLETE) == 0U);\n    // Command was successfully sent to memory card\n    // ..\n  }\n  else {\n    // Error\n  }\n}\n\n/* Usage example: ARM_MCI_SetupTransfer -------------------------------------*/\n\nvolatile uint32_t MCI_Events;\n\nvoid MCI_SignalEvent_Callback (uint32_t event) {\n  MCI_Events |= event;  // Save current event\n}\n\nvoid read_sector (ARM_DRIVER_MCI *drv, uint8_t *buf, uint32_t sz) {\n  int32_t status;\n  uint32_t cmd, arg;\n  uint32_t resp;\n\n  if (sz < 512U) {\n    // Invalid buffer size, sector consists of 512 bytes\n    //...\n  }\n\n  status = drv->SetupTransfer (buf, 1U, 512U, ARM_MCI_TRANSFER_READ | ARM_MCI_TRANSFER_BLOCK);\n\n  if (status == ARM_DRIVER_OK) {\n    MCI_Events = 0U; //Clear MCI driver event flags\n\n    cmd = 17U;       // Set READ_SINGLE_BLOCK command\n    arg = 0U;        // Set sector number\n\n    status  = drv->SendCommand (cmd, arg, ARM_MCI_RESPONSE_SHORT | ARM_MCI_RESPONSE_CRC | ARM_MCI_TRANSFER_DATA, &resp);\n\n    if (status == ARM_DRIVER_OK) {\n      /* Wait for event */\n      while ((MCI_Events & ARM_MCI_EVENT_COMMAND_COMPLETE) == 0U);\n      // Command was successfully sent to memory card\n      if ((resp & 0x03U) == 0U) {\n        // Sector number is valid, wait until data transfer completes\n        while ((MCI_Events & ARM_MCI_EVENT_TRANSFER_COMPLETE) == 0U);\n        // Data was successfully read from memory card\n        // ...\n      }\n    }\n  }\n}\n\n/* Usage example: ARM_MCI_AbortTransfer -------------------------------------*/\n\nvoid abort_data_transfer (ARM_DRIVER_MCI *drv) {\n  ARM_MCI_STATUS drv_status;\n\n  drv_status = drv->GetStatus();\n  \n  if (drv_status.transfer_active == 1U) {\n    // Data transfer is active, abort the transfer\n    if (drv->AbortTransfer() == ARM_DRIVER_OK) {\n      // Transfer aborted\n      // ...\n    }\n  }\n}\n\n/* Usage example: ARM_MCI_GetStatus -----------------------------------------*/\n\nvoid check_transfer_status (ARM_DRIVER_MCI *drv) {\n  ARM_MCI_STATUS drv_status;\n\n  drv_status = drv->GetStatus();\n\n  if (drv_status.transfer_active == 1U) {\n    // Data transfer is active\n  }\n  \n  if (drv_status.transfer_timeout == 1U) {\n    // Data not received, timeout expired\n  }\n  \n  if (drv_status.transfer_error == 1U) {\n    // Data transfer ended with error\n  }\n}\n\n/* Usage example: ARM_MCI_SignalEvent ---------------------------------------*/\n\nvoid MCI_SignalEvent_Callback (uint32_t event) {\n  if ((event & ARM_MCI_EVENT_CARD_INSERTED) != 0U) {\n    // Memory card was inserted into socket\n  }\n  if ((event & ARM_MCI_EVENT_CARD_REMOVED) != 0U) {\n    // Memory card was removed from socket\n  }\n\n  if ((event & ARM_MCI_EVENT_COMMAND_COMPLETE) != 0U) {\n    // Command was successfully sent to memory card\n  }\n  if ((event & ARM_MCI_EVENT_COMMAND_TIMEOUT) != 0U) {\n    // Command response was not received in time\n  }\n  if ((event & ARM_MCI_EVENT_COMMAND_ERROR) != 0U) {\n    // Command response was invalid\n  }\n\n  if ((event & ARM_MCI_EVENT_TRANSFER_COMPLETE) != 0U) {\n    // Data successfully transferred from/to memory card\n  }\n  if ((event & ARM_MCI_EVENT_TRANSFER_TIMEOUT) != 0U) {\n    // Data not transferred from/to memory card, timeout expired\n  }\n  if ((event & ARM_MCI_EVENT_TRANSFER_ERROR) != 0U) {\n    // Data transfer ended with errors\n  }\n  \n  if ((event & ARM_MCI_EVENT_SDIO_INTERRUPT) != 0U) {\n    // SD I/O card sent interrupt request\n  }\n  \n  if ((event & ARM_MCI_EVENT_CCS) != 0U) {\n    // CE-ATA command completion signal received\n  }\n  if ((event & ARM_MCI_EVENT_CCS_TIMEOUT) != 0U) {\n    // CE-ATA command completion signal wait timeout expired\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/NAND_Demo.c",
    "content": "#include \"Driver_NAND.h\"\n \n/* ONFI commands */\n#define ONFI_CMD_READ_1ST               0x00   ///< Read 1st Cycle\n#define ONFI_CMD_PROGRAM_2ND            0x10   ///< Page Program 2nd Cycle\n#define ONFI_CMD_READ_2ND               0x30   ///< Read 2nd Cycle\n#define ONFI_CMD_PROGRAM_1ST            0x80   ///< Page Program 1st Cycle\n#define ONFI_CMD_RESET                  0xFF   ///< Reset Command\n \n/* NAND Signal Event callback function */\nvolatile uint32_t NAND_Events;\nvoid NAND_SignalEventCallback (uint32_t dev_num, uint32_t event) {\n  if (dev_num == 0) {\n    NAND_Events |= event;\n  }\n  else {\n    // ..\n  }\n}\n \n/* NAND device Power ON */\nvoid PowerOn (ARM_DRIVER_NAND *drv, uint32_t dev_num) {\n  ARM_NAND_CAPABILITIES capabilities;\n \n  // Query drivers capabilities\n  capabilities = drv->GetCapabilities();\n \n  // Initialize NAND device\n  drv->Initialize (NAND_SignalEventCallback);\n \n  // Power-on NAND driver\n  drv->PowerControl (ARM_POWER_FULL);\n \n  // Turn ON device power\n  uint32_t volt = 0U;\n \n  if (capabilities.vcc)      { volt |= ARM_NAND_POWER_VCC_3V3;  }\n  if (capabilities.vcc_1v8)  { volt |= ARM_NAND_POWER_VCC_1V8;  }\n  if (capabilities.vccq)     { volt |= ARM_NAND_POWER_VCCQ_3V3; }\n  if (capabilities.vccq_1v8) { volt |= ARM_NAND_POWER_VCCQ_1V8; }\n \n  if (volt != 0U) {  \n    drv->DevicePower (volt);\n  }\n \n  // Setting bus mode\n  drv->Control (0U, ARM_NAND_BUS_MODE, ARM_NAND_BUS_SDR);\n \n  // Setting bus data width\n  drv->Control (0U, ARM_NAND_BUS_DATA_WIDTH, ARM_NAND_BUS_DATA_WIDTH_8);\n \n  // Enable chip manually if needed\n  if (capabilities.ce_manual) {\n    drv->ChipEnable (dev_num, true);\n  }\n \n  // Send ONFI Reset command */\n  drv->SendCommand (dev_num, ONFI_CMD_RESET);\n}\n \n/* NAND device Power OFF */\nvoid PowerOff (ARM_DRIVER_NAND *drv, uint32_t dev_num) {\n  ARM_NAND_CAPABILITIES capabilities;\n \n  // Query drivers capabilities\n  capabilities = drv->GetCapabilities();\n \n  // Disable chip manually if needed\n  if (capabilities.ce_manual) {\n    drv->ChipEnable (0U, false);\n  }\n \n  // Switch OFF gracefully\n  uint32_t volt = 0U;\n \n  if (capabilities.vcc)  { volt |= ARM_NAND_POWER_VCC_OFF;  }\n  if (capabilities.vccq) { volt |= ARM_NAND_POWER_VCCQ_OFF; }\n  if (volt) {\n    drv->DevicePower (volt);\n  }\n  drv->PowerControl (ARM_POWER_OFF);\n  drv->Uninitialize ();\n}\n \n/* Read NAND page. */\nvoid ReadPage (ARM_DRIVER_NAND *drv, uint32_t row, uint8_t *data, uint32_t cnt) {\n  uint32_t dev_num = 0;   // Device number\n  uint32_t mode;\n \n  // Send Read 1st command\n  drv->SendCommand (dev_num, ONFI_CMD_READ_1ST);\n \n  // Send address (column: 2 cycles, row: 3 cycles)\n  drv->SendAddress (dev_num, 0x00);\n  drv->SendAddress (dev_num, 0x00);\n  drv->SendAddress (dev_num, (uint8_t)(row));\n  drv->SendAddress (dev_num, (uint8_t)(row >>  8));\n  drv->SendAddress (dev_num, (uint8_t)(row >> 16));\n \n  // Send Read 2nd command\n  drv->SendCommand (dev_num, ONFI_CMD_READ_2ND);\n \n  // Wait until device ready\n  while (drv->GetDeviceBusy(dev_num) == 1) { ; }\n \n  // Use ECC algorithm number 2, ECC0 (ECC over main+spare)\n  mode = ARM_NAND_ECC(2) | ARM_NAND_ECC0;\n \n  // Transfer data from the NAND chip\n  if (drv->ReadData (dev_num, data, cnt, mode | ARM_NAND_DRIVER_DONE_EVENT) != cnt) {\n    // Wait until driver done event received\n    while ((NAND_Events & ARM_NAND_DRIVER_DONE_EVENT) == 0) { ; }\n    // Read page completed\n \n    if ((NAND_Events & ARM_NAND_EVENT_ECC_ERROR) != 0) {\n      // ECC correction failed\n    }\n  }\n}\n \n/* Write NAND page (ExecuteSequence interface). */\nvoid WritePage_Seq (ARM_DRIVER_NAND *drv, uint32_t row, const uint8_t *data, uint32_t cnt) {\n  uint32_t dev_num = 0;   // Device number\n  uint32_t cmd;\n  uint32_t code;\n  uint32_t seq;\n \n  // Prepare commands to send\n  cmd = ONFI_CMD_PROGRAM_1ST | (ONFI_CMD_PROGRAM_2ND << 8);\n \n  // Construct sequence code:\n  // - Send command 1\n  // - Send 2 cycles of column address and 3 cycles of row address\n  // - Write data from memory to device\n  // - Send command 2\n  code = ARM_NAND_CODE_SEND_CMD1      |\n         ARM_NAND_CODE_SEND_ADDR_COL1 |\n         ARM_NAND_CODE_SEND_ADDR_COL2 |\n         ARM_NAND_CODE_SEND_ADDR_ROW1 |\n         ARM_NAND_CODE_SEND_ADDR_ROW2 |\n         ARM_NAND_CODE_SEND_ADDR_ROW3 |\n         ARM_NAND_CODE_WRITE_DATA     |\n         ARM_NAND_CODE_SEND_CMD2      ;\n \n  // - Use ECC algorithm number 2, ECC0 (ECC over main+spare)\n  code |= ARM_NAND_ECC(2) | ARM_NAND_ECC0;\n \n  // Number of iterations in a sequence\n  seq = 1;\n \n  drv->ExecuteSequence (dev_num,        // Device number\n                        code,           // Sequence code\n                        cmd,            // Command(s)\n                        0,              // Column address\n                        row,            // Row address\n                        (void *)data,   // Data buffer\n                        cnt,            // Number of data items (per iteration)\n                        NULL,           // Device status will not be read\n                        &seq);          // Number of iterations\n \n  // Wait until done\n  while (drv->GetStatus(dev_num).busy != 0) { ; }\n \n  // Page write completed\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/SPI_Demo.c",
    "content": "#include \"Driver_SPI.h\"\n#include \"cmsis_os.h\"                   // ARM::CMSIS:RTOS:Keil RTX\n \n \nvoid mySPI_Thread(void const *argument);\nosThreadId tid_mySPI_Thread;\n \n \n/* SPI Driver */\nextern ARM_DRIVER_SPI Driver_SPI0;\n \n \nvoid mySPI_callback(uint32_t event)\n{\n    switch (event)\n    {\n    case ARM_SPI_EVENT_TRANSFER_COMPLETE:\n        /* Success: Wakeup Thread */\n        osSignalSet(tid_mySPI_Thread, 0x01);\n        break;\n    case ARM_SPI_EVENT_DATA_LOST:\n        /*  Occurs in slave mode when data is requested/sent by master\n            but send/receive/transfer operation has not been started\n            and indicates that data is lost. Occurs also in master mode\n            when driver cannot transfer data fast enough. */\n        __breakpoint(0);  /* Error: Call debugger or replace with custom error handling */\n        break;\n    case ARM_SPI_EVENT_MODE_FAULT:\n        /*  Occurs in master mode when Slave Select is deactivated and\n            indicates Master Mode Fault. */\n        __breakpoint(0);  /* Error: Call debugger or replace with custom error handling */\n        break;\n    }\n}\n \n/* Test data buffers */\nconst uint8_t testdata_out[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; \nuint8_t       testdata_in [8];\n \nvoid mySPI_Thread(void const* arg)\n{\n    ARM_DRIVER_SPI* SPIdrv = &Driver_SPI0;\n    osEvent evt;\n \n#ifdef DEBUG\n    ARM_DRIVER_VERSION   version;\n    ARM_SPI_CAPABILITIES drv_capabilities;\n \n    version = SPIdrv->GetVersion();\n    if (version.api < 0x200) /* requires at minimum API version 2.00 or higher */\n    {                        /* error handling                                 */\n        return;\n    }\n \n    drv_capabilities = SPIdrv->GetCapabilities();\n    if (drv_capabilities.event_mode_fault == 0)\n    {                        /* error handling */\n        return;\n    }\n#endif\n \n    /* Initialize the SPI driver */\n    SPIdrv->Initialize(mySPI_callback);\n    /* Power up the SPI peripheral */\n    SPIdrv->PowerControl(ARM_POWER_FULL);\n    /* Configure the SPI to Master, 8-bit mode @10000 kBits/sec */\n    SPIdrv->Control(ARM_SPI_MODE_MASTER | ARM_SPI_CPOL1_CPHA1 | ARM_SPI_MSB_LSB | ARM_SPI_SS_MASTER_SW | ARM_SPI_DATA_BITS(8), 10000000);\n \n    /* SS line = INACTIVE = HIGH */\n    SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE);\n \n    /* thread loop */\n    while (1)\n    {\n        /* SS line = ACTIVE = LOW */\n        SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE);\n        /* Transmit some data */\n        SPIdrv->Send(testdata_out, sizeof(testdata_out));\n        /* Wait for completion */\n        evt = osSignalWait(0x01, 100);\n        if (evt.status == osEventTimeout) {\n            __breakpoint(0); /* Timeout error: Call debugger */\n        }\n        /* SS line = INACTIVE = HIGH */\n        SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE);\n\n        /* SS line = ACTIVE = LOW */\n        SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE);\n        /* Receive 8 bytes of reply */\n        SPIdrv->Receive(testdata_in, 8);\n        evt = osSignalWait(0x01, 100);\n        if (evt.status == osEventTimeout) {\n            __breakpoint(0); /* Timeout error: Call debugger */\n        }\n        /* SS line = INACTIVE = HIGH */\n        SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE);\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/USART_Demo.c",
    "content": "#include \"Driver_USART.h\"\n#include \"cmsis_os.h\"                   /* ARM::CMSIS:RTOS:Keil RTX */\n#include <stdio.h>\n#include <string.h>\n \nvoid myUART_Thread(void const *argument);\nosThreadId tid_myUART_Thread;\n \n/* USART Driver */\nextern ARM_DRIVER_USART Driver_USART3;\n \n \nvoid myUSART_callback(uint32_t event)\n{\n  uint32_t mask;\n\n  mask = ARM_USART_EVENT_RECEIVE_COMPLETE  |\n         ARM_USART_EVENT_TRANSFER_COMPLETE |\n         ARM_USART_EVENT_SEND_COMPLETE     |\n         ARM_USART_EVENT_TX_COMPLETE       ;\n\n  if (event & mask) {\n    /* Success: Wakeup Thread */\n    osSignalSet(tid_myUART_Thread, 0x01);\n  }\n\n  if (event & ARM_USART_EVENT_RX_TIMEOUT) {\n    __breakpoint(0);  /* Error: Call debugger or replace with custom error handling */\n  }\n\n  if (event & (ARM_USART_EVENT_RX_OVERFLOW | ARM_USART_EVENT_TX_UNDERFLOW)) {\n    __breakpoint(0);  /* Error: Call debugger or replace with custom error handling */\n  }\n}\n\n \n/* CMSIS-RTOS Thread - UART command thread */\nvoid myUART_Thread(const void* args)\n{\n    static ARM_DRIVER_USART * USARTdrv = &Driver_USART3;\n    ARM_DRIVER_VERSION     version;\n    ARM_USART_CAPABILITIES drv_capabilities;\n    char                   cmd;\n \n  #ifdef DEBUG\n    version = USARTdrv->GetVersion();\n    if (version.api < 0x200)   /* requires at minimum API version 2.00 or higher */\n    {                          /* error handling */\n        return;\n    }\n    drv_capabilities = USARTdrv->GetCapabilities();\n    if (drv_capabilities.event_tx_complete == 0)\n    {                          /* error handling */\n        return;\n    }\n  #endif\n \n    /*Initialize the USART driver */\n    USARTdrv->Initialize(myUSART_callback);\n    /*Power up the USART peripheral */\n    USARTdrv->PowerControl(ARM_POWER_FULL);\n    /*Configure the USART to 4800 Bits/sec */\n    USARTdrv->Control(ARM_USART_MODE_ASYNCHRONOUS |\n                      ARM_USART_DATA_BITS_8 |\n                      ARM_USART_PARITY_NONE |\n                      ARM_USART_STOP_BITS_1 |\n                      ARM_USART_FLOW_CONTROL_NONE, 4800);\n     \n    /* Enable Receiver and Transmitter lines */\n    USARTdrv->Control (ARM_USART_CONTROL_TX, 1);\n    USARTdrv->Control (ARM_USART_CONTROL_RX, 1);\n \n    USARTdrv->Send(\"\\nPress Enter to receive a message\", 34);\n    osSignalWait(0x01, osWaitForever);\n     \n    while (1)\n    {\n        USARTdrv->Receive(&cmd, 1);          /* Get byte from UART */\n        osSignalWait(0x01, osWaitForever);\n        if (cmd == 13)                       /* CR, send greeting  */\n        {\n          USARTdrv->Send(\"\\nHello World!\", 12);\n          osSignalWait(0x01, osWaitForever);\n        }\n \n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Driver/src/VIO.txt",
    "content": "/**\n\\defgroup vio_interface_gr VIO\n\\brief API for Virtual I/O (VIO) (%cmsis_vio.h)\n\\details \n\nThe VIO software component is a virtual I/O abstraction for peripherals that are typically used in example projects. It\nenables developers to move from an evaluation kit to custom hardware and helps to scale project examples at large to many\ndevelopment boards:\n\n\\image html vioRationale.png \"Virtual I/O provides a generic API for examples and testing\"\n\n<b>VIO API</b>\n\nThe following header file defines the Application Programming Interface (API) for VIO:\n  - \\b %cmsis_vio.h : API for VIO\n\n<b>VIO User Code Templates</b>\n\nThe VIO software component contains two user code templates with different purposes:\n  - VIO:Custom: This file is an empty stub with all functions that are defined in the header file that can be used to\n    implement the VIO layer for the hardware that is used in the application.\n  - VIO:Virtual: This file uses a fixed memory location to emulate the VIO functionality and can be used off-the-shelf.\n\n<b>VIO Memory Location Structure</b>\n\nFor testing purposes, it is required to have fixed memory locations that are used to read/store values. In the VIO:Virtual\ntemplate file (\\b %vio.c), an exemplary implementation is shown:\n\n\\code\n// Input, output variables\n__USED uint32_t      vioSignalIn;                                       // Memory for incoming signal\n__USED uint32_t      vioSignalOut;                                      // Memory for outgoing signal\n__USED char          vioPrintMem[VIO_PRINTMEM_NUM][VIO_PRINT_MAX_SIZE]; // Memory for the last value for each level\n__USED int32_t       vioValue   [VIO_VALUE_NUM];                        // Memory for value used in vioGetValue/vioSetValue\n__USED vioValueXYZ_t vioValueXYZ[VIO_VALUEXYZ_NUM];                     // Memory for XYZ value for 3-D vector\n__USED vioAddrIPv4_t vioAddrIPv4[VIO_IPV4_ADDRESS_NUM];                 // Memory for IPv4 address value used in vioSetIPv4/vioGetIPv4\n__USED vioAddrIPv6_t vioAddrIPv6[VIO_IPV6_ADDRESS_NUM];                 // Memory for IPv6 address value used in vioSetIPv6/vioGetIPv6\n\\endcode\n\nUse these memory locations to monitor or set the variables as required in the application.\n\nTwo defines are available that help to disconnect the actual peripherals and enable virtual I/Os: \\c CMSIS_VIN and\n\\c CMSIS_VOUT. They help to write code that can be used in testing environments without real hardware access. The following\nimplementation example shows such code:\n\n<b>Code Example (VIO Implementation)</b>\n\\code\n// Initialize test input, output.\nvoid vioInit (void) {\n  uint32_t i;\n#if !defined CMSIS_VIN\n// Add user variables here:\n \n#endif\n#if !defined CMSIS_VOUT\n// Add user variables here:\n \n#endif\n \n  vioSignalIn  = 0U;\n  vioSignalOut = 0U;\n \n  memset (vioPrintMem, 0, sizeof(vioPrintMem));\n  memset (vioValue,    0, sizeof(vioValue));\n  memset (vioValueXYZ, 0, sizeof(vioValueXYZ));\n  memset (vioAddrIPv4, 0, sizeof(vioAddrIPv4));\n  memset (vioAddrIPv6, 0, sizeof(vioAddrIPv6));\n \n#if !defined CMSIS_VOUT\n// Add user code here:\n// <code vioInit output>\n \n  BSP_LED_Init(LED_BLUE);\n  BSP_LED_Init(LED_RED);\n  BSP_LED_Init(LED_GREEN);\n// </code>\n#endif\n \n#if !defined CMSIS_VIN\n// Add user code here:\n// <code vioInit input>\n \n  BSP_PB_Init(BUTTON_USER, BUTTON_MODE_GPIO);\n// </code>\n#endif\n \n  return;\n}\n\\endcode\n\n<b>Memory display in IDEs</b>\n\nArm Keil MDK uses the provided SCVD file to display the VIO signals in Component Viewer:\n\n\\image html vioComponentViewer.png\n\n@{\n*/\n\n/**\n\\defgroup vioDefines_gr  Defines and Structs\n\\ingroup vio_interface_gr\n\\brief Documents the defines and structs of the VIO API.\n\\details\n@{\n    Test.\n*/\n\n/**\n\\defgroup vioSignals_gr  Signals\n\\ingroup vioDefines_gr\n\\brief Signal related defines.\n\\details\n@{\n\\def vioLED0\n\\def vioLED1\n\\def vioLED2\n\\def vioLED3\n\\def vioLED4\n\\def vioLED5\n\\def vioLED6\n\\def vioLED7\n\\def vioLEDon\n\\def vioLEDoff\n\\def vioBUTTON0  \n\\def vioBUTTON1  \n\\def vioBUTTON2  \n\\def vioBUTTON3  \n\\def vioJOYup    \n\\def vioJOYdown  \n\\def vioJOYleft  \n\\def vioJOYright \n\\def vioJOYselect\n\\def vioJOYall   \n@}\n*/\n\n/**\n\\defgroup vioValues_gr  Values\n\\ingroup vioDefines_gr\n\\brief Value related defines.\n\\details\n@{\n\\def vioAIN0 \n\\def vioAIN1 \n\\def vioAIN2 \n\\def vioAIN3 \n\\def vioAOUT0\n/** \n\\struct     vioValueXYZ_t\n\\details\nStructure holding three-dimensional values for gyroscopes, accelerometers, etc.\n\n<b>Parameter for:</b>\n  - \\ref vioGetXYZ\n  - \\ref vioSetXYZ\n***************************************************************************************************************************/\n@}\n*/\n\n/**\n\\defgroup vioIDs_gr  IDs\n\\ingroup vioDefines_gr\n\\brief ID related defines.\n\\details\n@{\n\\def vioAIN0 \n\\def vioAIN1 \n\\def vioAIN2 \n\\def vioAIN3 \n\\def vioAOUT0\n\\def vioMotionGyro    \n\\def vioMotionAccelero\n\\def vioMotionMagneto \n@}\n*/\n\n/**\n\\defgroup vioPrintLevels_gr  Print Levels\n\\ingroup vioDefines_gr\n\\brief Print level related defines.\n\\details\n@{\n\\def vioLevelNone   \n\\def vioLevelHeading\n\\def vioLevelMessage\n\\def vioLevelError\n@}\n*/\n\n/**\n\\defgroup vioIPAddr_gr  IP Addresses\n\\ingroup vioDefines_gr\n\\brief IP address related structs.\n\\details\n@{\n\\struct     vioAddrIPv4_t\n\\details\nStructure holding IPv4 addresses.\n\n<b>Parameter for:</b>\n  - \\ref vioGetIPv4\n  - \\ref vioSetIPv4\n\n\\struct     vioAddrIPv6_t\n\\details\nStructure holding IPv6 addresses.\n\n<b>Parameter for:</b>\n  - \\ref vioGetIPv6\n  - \\ref vioSetIPv6\n@}\n*/\n\n/**\n@}\n*/\n// end group vioDefines_gr\n\n\n\nvoid vioInit (void) {};\n/**\n\\fn void vioInit (void)\n\\details\nThe function \\b vioInit initializes the VIO interface. Use it to initialize any connected hardware that is used to\nmap VIO signals. \n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n \n  // System Initialization\n  SystemCoreClockUpdate();\n  vioInit();\n  // ...\n \n}\n\\endcode\n***************************************************************************************************************************/\n\nint32_t vioPrint (uint32_t level, const char *format, ...) {\n  return (0);\n};\n/**\n\\fn int32_t vioPrint (uint32_t level, const char *format, ...)\n\\details\nThe function \\b vioPrint prints a formatted string to a test terminal. Formatting of the output follows the rules of \nstandard C language printf().\n\nRefer to \\ref vioPrintLevels_gr for information about the possible \\a levels.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n  int x = 3;\n \n  vioInit();\n  vioPrint(vioLevelNone,    \"Test [None]\"); \n  vioPrint(vioLevelHeading, \"Test [Heading] = Network Connector Message\"); \n  vioPrint(vioLevelMessage, \"Test [Message] = Connection failed\"); \n  vioPrint(vioLevelError,   \"Test [Error]   = %d\", x); \n}\n\\endcode\n***************************************************************************************************************************/\n\nvoid vioSetSignal (uint32_t mask, uint32_t signal) {};\n/**\n\\fn void vioSetSignal (uint32_t mask, uint32_t signal)\n\\details\nThe function \\b vioSetSignal set a \\a signal to an output specified by \\a mask. Use this function to map VIOs to actual\nhardware for displaying signals on a target board.\n\nRefer to \\ref vioSignals_gr for information about the possible \\a mask and \\a signal values.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n \n  vioInit();\n  vioSetSignal(vioLED0, vioLEDon);\n  // ...\n  vioSetSignal(vioLED0, vioLEDoff);\n}\n\\endcode\n***************************************************************************************************************************/\n\nuint32_t vioGetSignal (uint32_t mask) {\n  return (0);\n};\n/**\n\\fn uint32_t vioGetSignal (uint32_t mask)\n\\details\nThe function \\b vioGetSignal retrieves a signal from an input identified by \\a mask. Use this function to read data from any\ninput that is provided.\n\nRefer to \\ref vioSignals_gr for information about the possible \\a mask values.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n  uint32_t state;\n  uint32_t last = 0U;\n \n  vioInit();\n  for (;;) {\n    state = (vioGetSignal (vioBUTTON0)); // Get pressed button state\n    if (state != last){\n      if (state == vioBUTTON0){\n        // do something\n      }\n    }\n    last = state;\n  }\n}\n\\endcode\n***************************************************************************************************************************/\n\nvoid vioSetValue (uint32_t id, int32_t value) {};\n/**\n\\fn void vioSetValue (uint32_t id, int32_t value)\n\\details\nThe function \\b vioSetValue set the \\a value to the output identified by \\a id. Use this function to set states of I/Os for\nexample.\n\nRefer to \\ref vioValues_gr for information about \\a value and \\ref vioIDs_gr for \\a id.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n \n  vioInit();\n  vioSetValue(vioAOUT0, 1024);\n}\n\\endcode\n***************************************************************************************************************************/\n\nint32_t vioGetValue (uint32_t id) {\n  return (0);\n};\n/**\n\\fn int32_t vioGetValue (uint32_t id)\n\\details\nThe function \\b vioGetValue retrieves a value from the input identified by \\a id. Use this function to read data from inputs.\n\nRefer to \\ref vioIDs_gr for information about \\a id.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n  uint32_t button;\n \n  vioInit();\n  button = vioGetValue(vioBUTTON0);\n}\n\\endcode\n***************************************************************************************************************************/\n\nvoid vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ) {\n  return (0);\n};\n/**\n\\fn void vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ)\n\\details\nThe function \\b vioSetXYZ sets a three-dimensional value \\a valueXYZ to the output identified by \\a id. Use this function to\napply a 3d value to an output.\n\nRefer to \\ref vioValues_gr for information about the \\a valueXYZ and \\ref vioIDs_gr for \\a id.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n  vioValueXYZ_t xyz = {123, 456, 789};\n \n  vioInit();\n  vioSetXYZ(0, xyz);\n}\n\\endcode\n***************************************************************************************************************************/\n\nvioValueXYZ_t vioGetXYZ (uint32_t id) {\n  return (0);\n};\n/**\n\\fn vioValueXYZ_t vioGetXYZ (uint32_t id)\n\\details\nThe function \\b vioGetXYZ retrieves a three-dimensional value from the input identified by \\a id. Use this function to get a\n3d value.\n\nRefer to \\ref vioIDs_gr for information about \\a id.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n  volatile vioValueXYZ_t xyz;\n \n  vioInit();\n  xyz = vioGetXYZ(vioMotionGyro);\n}\n\\endcode\n***************************************************************************************************************************/\n\nvoid vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4) {};\n/**\n\\fn void vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4)\n\\details\nThe function \\b vioSetIPv4 sets an IPv4 address specified by \\a addrIPv4 to an interface identified by \\a id. Use this\nfunction to assign an IPv4 address to an interface.\n\nRefer to \\ref vioIDs_gr for information about \\a id and \\ref vioIPAddr_gr for \\a addrIPv4.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n  vioAddrIPv4_t addrIPv4 = {192U, 168U, 111U, 123U};\n \n  vioInit();\n  vioSetIPv4 (0, addrIPv4);\n}\n\\endcode\n***************************************************************************************************************************/\n\nvioAddrIPv4_t vioGetIPv4 (uint32_t id) {\n  return (0);\n};\n/**\n\\fn vioAddrIPv4_t vioGetIPv4 (uint32_t id)\n\\details\nThe function \\b vioGetIPv4 retrieves the IPv4 addrIPv4 from an interface identified by \\a id. Use this function to read an\nIPv4 address.\n\nRefer to \\ref vioIDs_gr for information about \\a id.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n  vioAddrIPv4_t addrIPv4;\n \n  vioInit();\n  addrIPv4 = vioGetIPv4(0);\n}\n\\endcode\n***************************************************************************************************************************/\n\nvoid vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6) {};\n/**\n\\fn void vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6)\n\\details\nThe function \\b vioSetIPv6 sets an IPv6 address specified by \\a addrIPv6 to an interface identified by \\a id. Use this\nfunction to assign an IPv6 address to an interface.\n\nRefer to \\ref vioIDs_gr for information about \\a id and \\ref vioIPAddr_gr for \\a addrIPv6.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n  vioAddrIPv6_t addrIPv6 = {1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,\n                           9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U};\n \n  vioInit();\n  vioSetIPv6 (0, addrIPv6);\n}\n\\endcode\n***************************************************************************************************************************/\n\nvioAddrIPv6_t vioGetIPv6 (uint32_t id) {\n  return (0);\n};\n/**\n\\fn vioAddrIPv6_t vioGetIPv6 (uint32_t id)\n\\details\nThe function \\b vioGetIPv6 retrieves the IPv6 addrIPv6 from an interface identified by \\a id. Use this function to read an\nIPv6 address.\n\nRefer to \\ref vioIDs_gr for information about \\a id.\n\n\\b Code \\b Example:\n\\code\n#include \"cmsis_vio.h\"                  // ::CMSIS Driver:VIO\n \nint main (void) {\n  vioAddrIPv6_t addrIPv6;\n \n  vioInit();\n  addrIPv6 = vioGetIPv6(0);\n}\n\\endcode\n***************************************************************************************************************************/\n\n/**\n@}\n*/\n// End VIO Interface\n"
  },
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    "content": "# Doxyfile 1.8.6\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a double hash (##) is considered a comment and is placed in\n# front of the TAG it is preceding.\n#\n# All text after a single hash (#) is considered a comment and will be ignored.\n# The format is:\n# TAG = value [value, ...]\n# For lists, items can also be appended using:\n# TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\\\" \\\").\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the config file\n# that follow. The default is UTF-8 which is also the encoding used for all text\n# before the first occurrence of this tag. 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By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. 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If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = NO\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = YES\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = YES\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = YES\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = \n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 0\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = NO\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = NO\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         = \n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = .\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          = *.c \\\n                         *.cc \\\n                         *.cxx \\\n                         *.cpp \\\n                         *.c++ \\\n                         *.d \\\n                         *.java \\\n                         *.ii \\\n                         *.ixx \\\n                         *.ipp \\\n                         *.i++ \\\n                         *.inl \\\n                         *.h \\\n                         *.hh \\\n                         *.hxx \\\n                         *.hpp \\\n                         *.h++ \\\n                         *.idl \\\n                         *.odl \\\n                         *.cs \\\n                         *.php \\\n                         *.php3 \\\n                         *.inc \\\n                         *.m \\\n                         *.mm \\\n                         *.dox \\\n                         *.py \\\n                         *.f90 \\\n                         *.f \\\n                         *.for \\\n                         *.vhd \\\n                         *.vhdl \\\n                         *.txt\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = YES\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = NO\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       = \n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        = \n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = \n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           = \n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        = \n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS = \n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE = \n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = YES\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = YES\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = YES\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = NO\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        = \n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         \"../../../LICENSE.txt\" \\\n                         ../Doxygen_Templates/printComponentTabs.js\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 100\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = \n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     = \n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               = \n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   = \n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  = \n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  = \n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           = \n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 0\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     = \n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       = \n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = NO\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       = \n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     = \n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         = \n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           = \n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           = \n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      = \n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. 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See section \"Linking to\n# external documentation\" for more information about the usage of tag files.\n\nGENERATE_TAGFILE       = \n\n# If the ALLEXTERNALS tag is set to YES all external class will be listed in the\n# class index. If set to NO only the inherited external classes will be listed.\n# The default value is: NO.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in\n# the modules index. If set to NO, only the current project's groups will be\n# listed.\n# The default value is: YES.\n\nEXTERNAL_GROUPS        = YES\n\n# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in\n# the related pages index. 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    "path": "external/CMSIS_5/CMSIS/DoxyGen/General/src/introduction.txt",
    "content": "/**\n\\mainpage Introduction\n\nThe <b>CMSIS</b> is a set of tools, APIs, frameworks, and work flows that help to simplify software re-use, reduce the\nlearning curve for microcontroller developers, speed-up project build and debug, and thus reduce the time to market for new\napplications.\n\nCMSIS started as a vendor-independent hardware abstraction layer Arm&reg; Cortex&reg;-M based processors and was later\nextended to support entry-level Arm Cortex-A based processors. To simplify access, CMSIS defines generic tool interfaces and\nenables consistent device support by providing simple software interfaces to the processor and the peripherals.\n\nCMSIS is defined in close cooperation with various silicon and software vendors and provides a common approach to interface\nto peripherals, real-time operating systems, and middleware components. It is intended to enable the combination of software\ncomponents from multiple vendors.\n\nCMSIS is open-source and collaboratively developed on\n<a href=\"https://github.com/ARM-software/CMSIS_5\" target=\"_blank\">GitHub</a>.\n\n\\section CM_Components CMSIS Components\n\n| CMSIS-... | Target Processors   | Description  |\n|:----------|:--------------------|:-------------|\n|<a href=\"../../Core/html/index.html\"><b>Core(M)</b></a>|   All Cortex-M, SecurCore | Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.|\n|<a href=\"../../Core_A/html/index.html\"><b>Core(A)</b></a>| Cortex-A5/A7/A9 | Standardized API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.|\n|<a href=\"../../Driver/html/index.html\"><b>Driver</b></a>|  All Cortex | Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.|\n|<a href=\"../../DSP/html/index.html\"><b>DSP</b></a>|        All Cortex-M | DSP library collection with over 60 functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P.|\n|<a href=\"../../NN/html/index.html\"><b>NN</b></a>|          All Cortex-M | Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.|\n|<a href=\"../../RTOS/html/index.html\"><b>RTOS v1</b></a>|   Cortex-M0/M0+/M3/M4/M7 | Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.|\n|<a href=\"../../RTOS2/html/index.html\"><b>RTOS v2</b></a>|  All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. |\n|<a href=\"../../Pack/html/index.html\"><b>Pack</b></a>|      All Cortex-M, SecurCore, Cortex-A5/A7/A9 | Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM). <br/>Is part of the <a href=\"https://www.open-cmsis-pack.org\" target=\"_blank\"><b>Open CMSIS Pack project</b></a>. |\n|<a href=\"../../Build/html/index.html\"><b>Build</b></a>|      All Cortex-M, SecurCore, Cortex-A5/A7/A9 | A set of tools, software frameworks, and work flows that improve productivity, for example with Continuous Integration (CI).<br/>Is replaced with the <a href=\"https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools\" target=\"_blank\"><b>CMSIS-Toolbox</b></a>. |\n|<a href=\"../../SVD/html/index.html\"><b>SVD</b></a>|        All Cortex-M, SecurCore | Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.|\n|<a href=\"../../DAP/html/index.html\"><b>DAP</b></a>|        All Cortex | Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. |\n|<a href=\"../../Zone/html/index.html\"><b>Zone</b></a>|      All Cortex-M | Defines methods to describe system resources and to partition these resources into multiple projects and execution areas. |\n\n\n\\section Motivation Motivation\n\nCMSIS has been created to help the industry in standardization. It enables consistent software layers and device support\nacross a wide range of development tools and microcontrollers. CMSIS is not a huge software layer that introduces overhead\nand does not define standard peripherals. The silicon industry can therefore support the wide variations of Arm Cortex\nprocessor-based devices with this common standard.\n\n\\image html Overview.png \"CMSIS Structure\"\n\nThe benefits of the CMSIS are:\n\n - CMSIS reduces the learning curve, development costs, and time-to-market. Developers can write software quicker through a\n   variety of easy-to-use, standardized software interfaces.\n - Consistent software interfaces improve the software portability and re-usability. Generic software libraries and\n   interfaces provide consistent software framework.\n - It provides interfaces for debug connectivity, debug peripheral views, software delivery, and device support to reduce\n   time-to-market for new microcontroller deployment.\n - It allows to use the compiler of your choice, as it is compiler independent and thus supported by mainstream compilers.\n - It enhances program debugging with peripheral information for debuggers and ITM channels for printf-style output.\n - CMSIS is delivered in CMSIS-Pack format which enables fast software delivery, simplifies updates, and enables consistent\n   integration into development tools.\n - CMSIS-Zone will simplify system resource and partitioning as it manages the configuration of multiple processors, memory\n   areas, and peripherals.\n - Continuous integration is common practice for most software developers nowadays. CMSIS-Build supports these workflows\n   and makes continuous testing and validation easier.\n\n\n\\section CodingRules Coding Rules\n\nThe CMSIS uses the following essential coding rules and conventions:\n - Compliant with ANSI C (C99) and C++ (C++03).\n - Uses ANSI C standard data types defined in \\b <stdint.h>.\n - Variables and parameters have a complete data type.\n - Expressions for \\c \\#define constants are enclosed in parenthesis.\n - Conforms to MISRA 2012 (but does not claim MISRA compliance). MISRA rule violations are documented.\n\nIn addition, the CMSIS recommends the following conventions for identifiers:\n - \\b CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.\n - \\b CamelCase names to identify function names and interrupt functions.\n - \\b Namespace_ prefixes avoid clashes with user identifiers and provide functional groups (i.e. for peripherals, RTOS, or DSP Library).\n\nThe CMSIS is documented within the source files with:\n \\li Comments that use the C or C++ style.\n \\li <a href=\"https://www.doxygen.nl/\" target=\"_blank\">Doxygen</a> compliant <b>function comments</b> that provide:\n    - brief function overview.\n    - detailed description of the function.\n    - detailed parameter explanation.\n    - detailed information about return values.\n\nDoxygen\tcomment example:\n\\verbatim\n/**\n * @brief  Enable Interrupt in NVIC Interrupt Controller\n * @param  IRQn  interrupt number that specifies the interrupt\n * @return none.\n * Enable the specified interrupt in the NVIC Interrupt Controller.\n * Other settings of the interrupt such as priority are not affected.\n */\n\\endverbatim\n\n\n\\section Validation Validation\n\nThe various components of CMSIS are validated using mainstream compilers. To get a diverse coverage, Arm Compiler v5 (based\non EDG front-end), Arm Compiler v6 (based on LLVM front-end), and GCC are used in the various tests. For each component, the\nsection \\b \"Validation\" describes the scope of the various verification steps.\n\nCMSIS components are compatible with a range of C and C++ language standards. The CMSIS components comply with the\n<a href=\"https://developer.arm.com/documentation/ihi0036/d\" target=\"_blank\">Application Binary Interface (ABI) for the Arm\nArchitecture</a> (exception CMSIS-RTOS v1). This ensures C API interfaces that support inter-operation between various\ntoolchains.\n\nAs CMSIS defines API interfaces and functions that scale to a wide range of processors and devices, the scope of\nthe run-time test coverage is limited. However, several components are validated using dedicated test suites\n(<a href=\"../../Driver/html/driverValidation.html\">CMSIS-Driver</a>,\n<a href=\"../../RTOS/html/rtosValidation.html\">CMSIS-RTOS v1</a>, and\n<a href=\"../../RTOS2/html/rtosValidation.html\">CMSIS-RTOS v2</a>).\n\nThe CMSIS source code is checked for MISRA C:2012 conformance using PC-Lint. MISRA deviations are documented with\nreasonable effort, however Arm does not claim MISRA compliance as there is today for example no guideline enforcement\nplan. The CMSIS source code is not checked for MISRA C++:2008 conformance as there is a risk that it is incompatible\nwith C language standards, specifically warnings that may be generated by the various C compilers.\n\n\n\\section License License\n\nCMSIS is provided free of charge by Arm under the <a href=\"LICENSE.txt\">Apache 2.0 License</a>.\n\n\n\\section CM_Pack_Content CMSIS Software Pack\n\nCMSIS itself is delivered in <a href=\"../../Pack/html/index.html\">CMSIS-Pack</a> format. The <b>ARM::CMSIS</b> pack contains\nthe following:\n\nFile/Directory    |Content\n:-----------------|:---------------------------------------------------------------------------------\n\\b ARM.CMSIS.pdsc |Package description file in CMSIS-Pack format.\n\\b LICENSE.txt    |CMSIS License Agreement (Apache 2.0)\n\\b CMSIS          |\\ref CM_Components \"CMSIS components\" (see also table below)\n\\b Device         |CMSIS reference implementations of Arm Cortex processor based devices\n\nCMSIS Directory\n---------------\n\nDirectory                 |Content\n:-------------------------|:----------------------------------------------------------------------------------------------------------------------------------------\n\\b Core                   |User code templates for <a href=\"../../Core/html/index.html\"><b>CMSIS-Core (Cortex-M)</b></a> related files, referenced in ARM.CMSIS.pdsc\n\\b Core_A                 |User code templates for <a href=\"../../Core_A/html/index.html\"><b>CMSIS-Core (Cortex-A)</b></a> related files, referenced in ARM.CMSIS.pdsc\n\\b DAP                    |<a href=\"../../DAP/html/index.html\"><b>CMSIS-DAP</b></a> Debug Access Port source code and reference implementations\n\\b Documentation          |This documentation\n\\b Driver                 |Header files for the <a href=\"../../Driver/html/index.html\"><b>CMSIS-Driver</b></a> peripheral interface API\n\\b DSP                    |<a href=\"../../DSP/html/index.html\"><b>CMSIS-DSP</b></a> software library source code\n\\b Include                |Include files for <a href=\"../../Core/html/index.html\"><b>CMSIS-Core (Cortex-M)</b></a> and <a href=\"../../DSP/html/index.html\"><b>CMSIS-DSP</b></a>\n\\b NN                     |<a href=\"../../NN/html/index.html\"><b>CMSIS-NN</b></a> software library source code\n\\b Pack                   |<a href=\"../../Pack/html/index.html\"><b>CMSIS-Pack</b></a>\n\\b RTOS                   |<a href=\"../../RTOS/html/index.html\"><b>CMSIS-RTOS Version 1</b></a> along with RTX4 reference implementation\n\\b RTOS2                  |<a href=\"../../RTOS2/html/index.html\"><b>CMSIS-RTOS Version 2</b></a> along with RTX5 reference implementation\n\\b SVD                    |<a href=\"../../SVD/html/index.html\"><b>CMSIS-SVD</b></a>\n\\b Utilities              |PACK.xsd (<a href=\"../../Pack/html/packFormat.html#PackSchema\"><b>CMSIS-Pack</b> schema file</a>), PackChk.exe (checking tool for software packs), \\n CMSIS-SVD.xsd (<a href=\"../../SVD/html/schema_1_2_gr.html\"><b>CMSIS-SVD</b> schema file</a>), SVDConv.exe (conversion tool for SVD files), \\n CPRJ.xsd (<a href=\"../../Build/html/projectDescriptionSchema.html\"><b>CMSIS-Build</b> schema file</a>)\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page cm_revisionHistory Revision History\n\n\nThe following table shows the overall high-level history of the various CMSIS releases.\nIn addition, each CMSIS component has its own release history:\n\n- <a href=\"../../Core/html/core_revisionHistory.html\"><b>Core (Cortex-M) Revision History</b></a>\n- <a href=\"../../Core_A/html/rev_histCoreA.html\"><b>Core (Cortex-A) Revision History</b></a>\n- <a href=\"../../Driver/html/driver_revisionHistory.html\"><b>Driver Revision History</b></a>\n- <a href=\"../../DSP/html/ChangeLog_pg.html\"><b>DSP Revision History (Change Log)</b></a>\n- <a href=\"../../NN/html/ChangeLog_pg.html\"><b>NN Revision History (Change Log)</b></a>\n- <a href=\"../../RTOS/html/rtos_revisionHistory.html\"><b>RTOS v1 Revision History</b></a>\n- <a href=\"../../RTOS2/html/rtos_revisionHistory.html\"><b>RTOS v2 Revision History</b></a>\n- <a href=\"../../Pack/html/pack_revisionHistory.html\"><b>Pack Revision History</b></a>\n- <a href=\"../../SVD/html/svd_revisionHistory.html\"><b>SVD Revision History</b></a>\n- <a href=\"../../DAP/html/dap_revisionHistory.html\"><b>DAP Revision History</b></a>\n- <a href=\"../../Zone/html/zone_revisionHistory.html\"><b>Zone Revision History</b></a>\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>5.9.0</td>\n      <td>\n       - CMSIS-Core(M): 5.6.0 (see revision history for details)\n         - Arm Cortex-M85 cpu support\n         - Arm China STAR-MC1 cpu support\n         - Updated system_ARMCM55.c\n       - CMSIS-Core(A): 1.2.1 (unchanged)\n       - CMSIS-Driver: 2.8.0 (unchanged)\n       - CMSIS-DSP: 1.10.0 (see revision history for details)\n       - CMSIS-NN: 3.1.0 (see revision history for details)\n         - Support for int16 convolution and fully connected for reference implementation\n         - Support for DSP extension optimization for int16 convolution and fully connected\n         - Support dilation for int8 convolution\n         - Support dilation for int8 depthwise convolution\n         - Support for int16 depthwise conv for reference implementation including dilation\n         - Support for int16 average and max pooling for reference implementation\n         - Support for elementwise add and mul int16 scalar version\n         - Support for softmax int16 scalar version\n         - Support for SVDF with 8 bit state tensor\n       - CMSIS-RTOS2: 2.1.3 (unchanged)\n          - RTX 5.5.4 (see revision history for details)\n       - CMSIS-Pack: deprecated (moved to Open-CMSIS-Pack)\n       - CMSIS-Build: deprecated (moved to CMSIS-Toolbox in Open-CMSIS-Pack)\n       - CMSIS-SVD: 1.3.9 (see revision history for details)\n       - CMSIS-DAP: 2.1.1 (see revision history for details)\n         - Allow default clock frequency to use fast clock mode\n       - CMSIS-Zone: 1.0.0 (unchanged)\n       - Devices\n         - Support for Cortex-M85\n       - Utilities\n          - SVDConv 3.3.42\n          - PackChk 1.3.95\n      </td>\n    </tr>    \n    <tr>\n      <td>5.8.0</td>\n      <td>\n        - CMSIS-Build 0.10.0 (beta)\n          - Enhancements (see revision history for details)\n        - CMSIS-Core (Cortex-M) 5.5.0\n          - Updated GCC LinkerDescription, GCC Assembler startup\n          - Added ARMv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC\n          - Changed C-Startup to default Startup.\n        - CMSIS-Core (Cortex-A) 1.2.1\n        - CMSIS-Driver 2.8.0 (unchanged)\n        - CMSIS-DSP 1.9.0\n          - Purged pre-built libs from Git\n        - CMSIS-NN 3.0.0\n          - Major interface change for functions compatible with TensorFlow Lite for Microcontroller\n          - Added optimization for SVDF kernel\n          - Improved MVE performance for fully Connected and max pool operator\n          - NULL bias support for fully connected operator in non-MVE case(Can affect performance)\n          - Expanded existing unit test suite along with support for FVP\n        - CMSIS-RTOS 2.1.3 (unchanged)\n          - RTX 5.5.3 (see revision history for details)\n        - CMSIS-Pack 1.7.2\n          - Support for Microchip XC32 compiler\n          - Support for Custom Datapath Extension\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 2.0.0 (unchanged)\n        - CMSIS-Zone 1.0.0 (unchanged)\n        - Devices\n        - Utilities\n          - SVDConv 3.3.35\n          - PackChk 1.3.89\n      </td>\n    </tr>\n    <tr>\n      <td>5.7.0</td>\n      <td>\n        - CMSIS-Build 0.9.0 (beta)\n          - Draft for CMSIS Project description (CPRJ)\n        - CMSIS-Core (Cortex-M) 5.4.0\n          - Cortex-M55 cpu support\n          - Enhanced MVE support for Armv8.1-MML\n          - Fixed device config define checks.\n          - L1 Cache functions for Armv7-M and later\n        - CMSIS-Core (Cortex-A) 1.2.0\n          - Fixed GIC_SetPendingIRQ to use GICD_SGIR\n          - Added missing DSP intrinsics\n          - Reworked assembly intrinsics: volatile, barriers and clobber\n        - CMSIS-Driver 2.8.0\n          - Added VIO API 0.1.0 (preview)\n        - CMSIS-DSP 1.8.0\n          - Added new functions and function groups\n          - Added MVE support\n        - CMSIS-NN 1.3.0\n          - Added MVE support\n          - Further optimizations for kernels using DSP extension\n        - CMSIS-RTOS 2.1.3 (unchanged)\n          - RTX 5.5.2 (see revision history for details)\n        - CMSIS-Pack 1.6.3\n          - deprecating all types specific to cpdsc format. Cpdsc is replaced by Cprj with dedicated schema.\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 2.0.0 (unchanged)\n        - CMSIS-Zone 1.0.0\n        - Devices\n          - ARMCM55 device\n          - ARMv81MML startup code recognizing __MVE_USED macro\n          - Refactored vector table references for all Cortex-M devices\n          - Reworked ARMCM* C-StartUp files.\n          - Include L1 Cache functions in ARMv8MML/ARMv81MML devices\n        - Utilities\n          Attention: Linux binaries moved to Linux64 folder!\n          - SVDConv 3.3.35\n          - PackChk 1.3.89\n      </td>\n    </tr>\n    <tr>\n      <td>5.6.0</td>\n      <td>\n        - CMSIS-Core (Cortex-M) 5.3.0\n          - Added provisions for compiler-independent C startup code.\n        - CMSIS-Core (Cortex-A) 1.1.4\n          - Fixed __FPU_Enable.\n        - CMSIS-Driver 2.7.1\n          - Finalized WiFi Interface API 1.0.0\n        - CMSIS-DSP 1.7.0 (see revision history for details)\n          - New Neon versions of f32 functions\n          - Compilation flags for FFTs\n        - CMSIS-NN 1.2.0 (unchanged)\n        - CMSIS-RTOS1 1.03 (unchanged)\n          - RTX 4.82.0 (see revision history for details)\n        - CMSIS-RTOS 2.1.3 (unchanged)\n          - RTX 5.5.1 (see revision history for details)\n        - CMSIS-Pack 1.6.0 (unchanged)\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 2.0.0 (unchanged)\n        - CMSIS-Zone 0.12.0 (preview)\n          - Completely reworked\n        - Devices\n          - Generalized C startup code for all Cortex-M family devices.\n          - Updated Cortex-A memory regions and system configuration files.\n        - Utilities\n          - SVDConv 3.3.27\n          - PackChk 1.3.82 (unchanged)\n      </td>\n    </tr>\n    <tr>\n      <td>5.5.1</td>\n      <td>\n        - CMSIS-Core (Cortex-M) 5.2.1\n          - Fixed compilation issue in cmsis_armclang_ltm.h\n        - CMSIS-Core (Cortex-A) 1.1.3 (unchanged)\n        - CMSIS-Driver 2.7.0 (unchanged)\n        - CMSIS-DSP 1.6.0 (unchanged)\n        - CMSIS-NN 1.1.0 (unchanged)\n        - CMSIS-RTOS 2.1.3 (unchanged)\n          - RTX 5.5.0 (unchanged)\n        - CMSIS-Pack 1.6.0 (unchanged)\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 2.0.0 (unchanged)\n        - CMSIS-Zone 0.9.0 (unchanged)\n      </td>\n    </tr>\n    <tr>\n      <td>5.5.0</td>\n      <td>\n        - CMSIS-Core (Cortex-M) 5.2.0\n          - Reworked Stack/Heap configuration for ARM startup files.\n          - Added Cortex-M35P device support.\n          - Added generic Armv8.1-M Mainline device support.\n        - CMSIS-Core (Cortex-A) 1.1.3 Minor fixes.\n        - CMSIS-DSP 1.6.0\n          - reworked DSP library source files\n            - added macro ARM_MATH_LOOPUNROLL\n            - removed macro UNALIGNED_SUPPORT_DISABLE\n            - added const-correctness\n            - replaced SIMD pointer construct with memcopy solution\n            - replaced macro combination \"CMSIS_INLINE __STATIC_INLINE with \"__STATIC_FORCEINLINE\"\n          - reworked DSP library documentation\n          - Changed DSP folder structure\n            - moved DSP libraries to ./DSP/Lib\n          - moved DSP libraries to folder ./DSP/Lib\n          - ARM DSP Libraries are built with ARMCLANG\n          - Added DSP Libraries Source variant\n        - CMSIS-NN 1.1.0 (unchanged)\n        - CMSIS-Driver 2.7.0\n          - Added WiFi Interface API 1.0.0-beta\n          - Added custom driver selection to simplify implementation of new CMSIS-Driver\n        - CMSIS-RTOS 2.1.3\n          - RTX 5.5.0 (see revision history)\n        - CMSIS-Pack 1.6.0\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 2.0.0 (unchanged)\n        - CMSIS-Zone 0.9.0 (Preview)\n        - Devices\n          - Added Cortex-M35P and ARMv81MML device templates.\n          - Fixed C-Startup Code for GCC (aligned with other compilers)\n            - Moved call to SystemInit before memory initialization.\n        - Utilities\n          - SVDConv 3.3.25\n          - PackChk 1.3.82\n      </td>\n    </tr>\n    <tr>\n      <td>5.4.0</td>\n      <td>\n        - CMSIS-Core (Cortex-M) 5.1.2 Minor fixes and slight enhancements, e.g. beta for Cortex-M1.\n        - CMSIS-Core (Cortex-A) 1.1.2 Minor fixes.\n        - CMSIS-Driver 2.6.0 (unchanged)\n        - CMSIS-DSP 1.5.2 (unchanged)\n        - CMSIS-NN 1.1.0 Added new math function (see revision history)\n        - CMSIS-RTOS 2.1.3 Relaxed interrupt usage.\n          - RTX 5.4.0 (see revision history)\n        - CMSIS-Pack 1.5.0 (unchanged)\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 2.0.0 (unchanged)\n        - CMSIS-Zone 0.0.1 (unchanged)\n      </td>\n    </tr>\n    <tr>\n      <td>5.3.0</td>\n      <td>\n        - CMSIS-Core (Cortex-M) 5.1.1\n        - CMSIS-Core (Cortex-A) 1.1.1\n        - CMSIS-Driver 2.6.0 (unchanged)\n        - CMSIS-DSP 1.5.2 (unchanged)\n        - CMSIS-NN 1.0.0 Initial contribution of Neural Network Library.\n        - CMSIS-RTOS 2.1.2 (unchanged)\n        - CMSIS-Pack 1.5.0 (unchanged)\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 2.0.0 Communication via WinUSB to achieve high-speed transfer rates.\n        - CMSIS-Zone 0.0.1 (unchanged)\n      </td>\n    </tr>\n    <tr>\n      <td>5.2.0</td>\n      <td>\n        - CMSIS-Core (Cortex-M) 5.1.0 MPU functions for ARMv8-M, cmsis_iccarm.h replacing cmsis_iar.h\n        - CMSIS-Core (Cortex-A) 1.1.0 cmsis_iccarm.h, additional physical timer access functions\n        - CMSIS-Driver 2.6.0 Enhanced CAN and NAND driver interface.\n        - CMSIS-DSP 1.5.2 Fixed diagnostics and moved SSAT/USST intrinsics to CMSIS-Core.\n        - CMSIS-RTOS 2.1.2 Relaxed some ISR-callable restrictions.\n        - CMSIS-Pack 1.5.0 (unchanged)\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 1.2.0 (unchanged)\n        - CMSIS-Zone 0.0.1 (unchanged)\n      </td>\n    </tr>\n    <tr>\n      <td>5.1.1</td>\n      <td>\n        - CMSIS-Core (Cortex-M) (unchanged)\n        - CMSIS-Core (Cortex-A) (unchanged)\n        - CMSIS-Driver 2.05 (unchanged)\n        - CMSIS-DSP 1.5.2 (unchanged)\n        - CMSIS-RTOS 2.1.1 Fixed RTX5 pre-built libraries for Cortex-M.\n        - CMSIS-Pack 1.5.0 (unchanged)\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 1.1.0 (unchanged)\n        - CMSIS-Zone 0.0.1 (unchanged)\n      </td>\n    </tr>\n    <tr>\n      <td>5.1.0</td>\n      <td>\n        - CMSIS-Core (Cortex-M) 5.0.2 several minor corrections and enhancements\n        - CMSIS-Core (Cortex-A) 1.0.0 implements a basic run-time system for Cortex-A5/A7/A9\n        - CMSIS-Driver 2.05 status typedef made volatile\n        - CMSIS-DSP 1.5.2 fixed GNU Compiler specific diagnostics\n        - CMSIS-RTOS 2.1.1 added support for Cortex-A5/A7/A9 to RTX5\n        - CMSIS-Pack 1.5.0 added SDF format specification\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 1.1.0 (unchanged)\n        - CMSIS-Zone 0.0.1 (Preview) format to describe system resources and tool for partitioning of resources\n      </td>\n    </tr>\n    <tr>\n      <td>5.0.1</td>\n      <td>\n        - CMSIS-Core 5.0.1 added __PACKED_STRUCT macro and uVisor support\n        - CMSIS-Driver 2.05 updated all typedefs related to status now being volatile.\n        - CMSIS-DSP 1.5.1 added ARMv8M DSP libraries\n        - CMSIS-RTOS 2.1.0 added support for critical and uncritical sections\n        - CMSIS-Pack 1.4.8 add Pack Index File specification\n        - CMSIS-SVD 1.3.3 (unchanged)\n        - CMSIS-DAP 1.1.0 (unchanged)\n      </td>\n    </tr>\n\t<tr>\n      <td>5.0.0</td>\n      <td>\n        Added support for: <a href=\"http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php\" target=\"_blank\"><b>ARMv8-M architecture</b></a> including TrustZone for ARMv8-M and Cortex-M23, Cortex-M33 processors\n        - CMSIS-Core (Cortex-M) 5.0.0 added support for ARMv8-M and Cortex-M23, Cortex-M33 processors\n        - CMSIS-Driver 2.04.0 (unchanged)\n        - CMSIS-DSP 1.4.9 minor corrections and performance improvements\n        - CMSIS-RTOS 2.0.0 new API with RTX 5.0.0 reference implementation and corrections in RTX 4.8.2\n        - CMSIS-Pack 1.4.4 introducing CPDSC project description\n        - CMSIS-SVD 1.3.3 several enhancements and rework of documentation\n        - CMSIS-DAP 1.1.0 (unchanged)\n      </td>\n    </tr>\n    <tr>\n      <td>4.5.0</td>\n      <td>\n        Maintenance release that is fixing defects. See component's revision history for more details.\n        See component's revision history for more details.\n        - CMSIS-Core (Cortex-M) 4.30.0\n        - CMSIS-DAP 1.1.0 (unchanged)\n        - CMSIS-Driver 2.04.0\n        - CMSIS-DSP 1.4.7\n        - CMSIS-Pack 1.4.1\n        - CMSIS-RTOS RTX 4.80.0\n        - CMSIS-SVD 1.3.1\n      </td>\n    </tr>\n    <tr>\n      <td>4.4.0</td>\n      <td>\n        Feature release adding CMSIS-DAP (see extended End User Licence Agreement) and CMSIS-Driver for CAN.\n        See component's revision history for more details.\n        - CMSIS-Core (Cortex-M) 4.20.0\n        - CMSIS-DAP 1.1.0\n        - CMSIS-Driver 2.03.0\n        - CMSIS-DSP 1.4.5  (unchanged)\n        - CMSIS-RTOS RTX 4.79.0\n        - CMSIS-Pack 1.4.0\n        - CMSIS-SVD 1.3.0\n      </td>\n    </tr>\n    <tr>\n      <td>4.3.0</td>\n      <td>\n        Maintenance release adding SAI CMSIS-Driver and fixing defects. See component's revision history for more details.\n        - CMSIS-Core (Cortex-M) 4.10.0\n        - CMSIS-Driver 2.02.0\n        - CMSIS-DSP 1.4.5\n        - CMSIS-RTOS RTX 4.78.0\n        - CMSIS-Pack 1.3.3\n        - CMSIS-SVD (unchanged)\n      </td>\n    </tr>\n    <tr>\n      <td>4.2</td>\n      <td>Introducing processor support for Cortex-M7.\n      </td>\n    </tr>\n    <tr>\n      <td>4.1</td>\n      <td>Enhancements in CMSIS-Pack and CMSIS-Driver.\\n\n      Added: PackChk validation utility\\n\n      Removed support for GNU: Sourcery G++ Lite Edition for ARM</td>\n    </tr>\n    <tr>\n      <td>4.0</td>\n      <td>First release in CMSIS-Pack format.\\n Added specifications for CMSIS-Pack, CMSIS-Driver</td>\n    </tr>\n    <tr>\n      <td>3.30</td>\n      <td>Maintenance release with enhancements in each component</td>\n    </tr>\n    <tr>\n      <td>3.20</td>\n      <td>Maintenance release with enhancements in each component</td>\n    </tr>\n    <tr>\n      <td>3.01</td>\n      <td>Added support for Cortex-M0+ processors</td>\n    </tr>\n    <tr>\n      <td>3.00</td>\n      <td>Added support for SC000 and SC300 processors\\n\n      Added support for GNU GCC Compiler\\n\n      Added CMSIS-RTOS API</td>\n    </tr>\n    <tr>\n      <td>2.10</td>\n      <td>Added CMSIS-DSP Library</td>\n    </tr>\n    <tr>\n      <td>2.0</td>\n      <td>Added support for Cortex-M4 processor</td>\n    </tr>\n    <tr>\n      <td>1.30</td>\n      <td>Reworked CMSIS startup concept</td>\n    </tr>\n    <tr>\n      <td>1.01</td>\n      <td>Added support for Cortex-M0 processor</td>\n    </tr>\n    <tr>\n      <td>1.00</td>\n      <td>Initial release of CMSIS-Core (Cortex-M) for Cortex-M3 processor</td>\n    </tr>\n</table>\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/How2Doc.txt",
    "content": "Rules for CMSIS API Function documentation\n===========================================\n\nThis document describes how to generate Doxygen-style documentation for middleware \"Components\".\nIt explains how the Doxygen documentation under \"Reference\" is provided in header (*.h), \ntext (*.txt), template (*.c), and config files.\n\nFolder structure:\n  .\\MW\\component\\Include      *.h files\n  .\\MW\\component\\Template     *.c user code templates\n  .\\MW\\component\\Config       *.c or *.h config files\n  .\\MW\\Doc\\component          *.txt files\n  .\\MW\\Doc\\component\\images   graphic files used by *.txt files\n  \nFiles: Middleware components have the following files that are used to generate the API documentation:\n\n  - *.h files: one or more header files which expose data types and functions (the API). Doxygen uses the *.h files \n    that are in .\\MW\\component\\include folder.\n\n  - *.txt files: documentation files that group functions and explain overall the API. Each *.h file should have a *.txt\n    file with the same name, i.e. rl_usb.h => rl_usb.txt; a exception is permitted when a template is used to explain \n  API functions.\n \n  - *.c templates: show the usage of some middleware functionality and may be included in the Doxygen documentation.\n    *.c templates with '%Instance%' are copied to .\\MW\\Doc\\component and '%Instance%' is replaced with 'n', otherwise\n  Doxygen uses the *.c templates in folder .\\MW\\component\\Template. If a template is used in documentation \n  the related *.txt file has the same name as the template, i.e. USBD_User_HID.c => USBD_User_HID.txt.\n  \n  - *.c or *.h config files should be self-explaining using <i> tags. config files will not be replicated\n    in Doxygen *.txt files, but the high-level usage will be explained. The impact of parameters to middleware\n  needs therefore be part of the config files.\n\nSource files (*.c and *.h) should NOT use <TAB> character. Instead of <TAB> <space> characters are used.\n\n\nAPI Documentation in .\\Include\\*.h files\n----------------------------------------\n\nExample:\n\nThe following snippet shows a sample documentation (correct).  In general functions are grouped and\na short descriptive line is added before a group of functions.  In case that functions are only \nrelevant for the documentation (i.e. available in multiple instances), they are included in \n#ifdef __DOXYGEN__  /  #endif sections.\n\n{code}\n/// \\brief Called during \\ref USBD_Initialize to initialize the USB Device class.\n/// \\return     none\nextern void USBD_HIDn_Initialize (void);\n\n//  ==== USB Host Human Interface Device Functions ====\n\n/// \\brief Get status of the Human Interface Device.\n/// \\param[in]     index         instance index of HID.\n/// \\return        true          device is configured and initialized.\n/// \\return        false         device not ready.\nextern bool USBH_HID_GetStatus (uint8_t index);\n\n/// \\brief Read data received from Human Interface Device.\n/// \\param[in]     index         instance index of HID.\n/// \\param[out]    ptr_data      data to be read.\n/// \\return        value >= 0    number of bytes read.\n/// \\return        value -1      communication error.\nextern int USBH_HID_Read (uint8_t index, uint8_t *ptr_data);\n\n/// \\brief Write data to Human Interface Device.\n/// \\param[in]     index         instance index of HID.\n/// \\param[in]     ptr_data      data to be written.\n/// \\param[in]     data_len      number of data bytes to be written.\n/// \\return        number of bytes written.\nextern int USBH_HID_Write (uint8_t index, uint8_t *ptr_data, uint16_t data_len);\n\n/// \\brief Get last error that happened on the Human Interface Device.\n/// \\param[in]     index         instance index of HID.\n/// \\return        error code.\nextern uint32_t USBH_HID_GetLastError (uint8_t index);\n\n/// \\brief Retrieve state change since last call of HID Mouse.\n/// \\param[in]     index         instance index of HID.\n/// \\param[out]    button        pointer to variable that receives button state.\n/// \\param[out]    x             pointer to variable that receives x position change.\n/// \\param[out]    y             pointer to variable that receives y position change.\n/// \\param[out]    wheel         pointer to variable that receives wheel change.\n/// \\return        true          state change since last call.\n/// \\return        false         no state change since last call.\nextern bool USBH_HID_GetMouseData (uint8_t index, uint8_t *button, int8_t *x, int8_t *y, int8_t *wheel);\n\n//  ==== USB Device Human Interface Device Functions ====\n\n#ifdef __DOXYGEN__\n// following functions are available for each instance of a HID class.\n// generic prefix USBD_HIDn is USBD_HID0 for HID class instance 0.\n\n/// \\brief Prepare HID report data to be sent.\n/// \\param[in]   rtype  Report type\n///                - HID_REPORT_INPUT   = Input report requested.\n///                - HID_REPORT_FEATURE = Feature report requested.\n/// \\param[in]   rid  Report ID (0 if only one report exists)\n/// \\param[out]  buf  Buffer for report data to be sent.\n/// \\param[in]   req  Request type\n///                - USBD_HID_REQ_EP_CTRL       = Control endpoint request.\n///                - USBD_HID_REQ_PERIOD_UPDATE = Idle period expiration request.\n///                - USBD_HID_REQ_EP_INT        = Previously sent report on interrupt endpoint request.\n/// \\return      value >= 0  number of data bytes prepared\n/// \\return      value < 0   error code\nint32_t USBD_HIDn_GetReport (uint8_t rtype, uint8_t rid, uint8_t *buf, uint8_t req);\n\n{code}\n\nThis section contains things that should be NOT DONE:\n\n/// \\brief Prepares HID report data to be sent\n*** NO '.' to terminate brief documentation.\n\n\n/// \\brief Prepares HID report data to be sent.\n*** NO 's' after a verb in brief documentation.\n\n\n/// \\brief Retrieve a state change since last call of the HID Mouse.\n*** NO 'a' or 'the' in brief text.\n\n\n/// \\return        true  when state change since last call, false otherwise.\n*** Confusing return statement, separate into two lines (looks also better):\n/// \\return        \n///              - true  = when state change since last call\n///              - false = otherwise.\n\n\n/// \\return        0        no communication error.\n/// \\return        - 1      communication error.\n*** Confusing, may generate a bullet point, use instead \"value\" in front of plain numbers, correct is:\n/// \\return        value 0    no communication error.\n/// \\return        value -1   communication error.\n\n\n/// \\param[in]   req  Request type:\n///                USBD_HID_REQ_EP_CTRL       = Control endpoint request.\n///                USBD_HID_REQ_PERIOD_UPDATE = Idle period expiration request.\n///                USBD_HID_REQ_EP_INT        = Previously sent report on interrupt endpoint request.\n*** Missing '-' in front of parameter details => hard to read in documentation.\n\n\n/// \\param[in]     stat     error status and line states\n///                          - bit 6 - bOverRun\n///                          - bit 5 - bParity\n*** Missing ':' after states and bit numbers, correct is:\n/// \\param[in]     stat     error status and line states:\n///                          - bit 6: bOverRun\n///                          - bit 5: bParity\n\n\n/// \\param[in]    ptr_data   pointer to data buffer where information is written.\n*** Wrong, should be param[out].\n*** Redundant:  a data buffer is always a pointer, better is:\n/// \\param[out]    ptr_data   data buffer that receives information.\n\n\n/// \\fn bool USBH_HID_GetStatus (uint8_t index);\n/// \\brief Get status of the Human Interface Device.\n/// \\param[in]     index         instance index of HID.\n/// \\return        true          device is configured and initialized.\n/// \\return        false         device not ready.\nextern bool USBH_HID_GetStatus (uint8_t index);\nWrong: \\fn not needed\n\n\n/* USB Host Speed constants                                                   */\nenum { \n  USBH_LS  = 0,                         /* Low speed                          */\n  USBH_FS,                              /* Full speed                         */\n  USBH_HS                               /* High speed                         */\n};\nWrong, should be Doxygen style. Correct is:\n/// USB Host Speed constants\nenum { \n  USBH_LS  = 0,                         ///< Low speed\n  USBH_FS,                              ///< Full speed\n  USBH_HS                               ///< High speed\n};\n\n\ntypedef struct {                        ///< Hw Endpoint settings structure\n  osThreadId   thread_id;               ///< Thread ID of thread that uses URB\n  USBH_URB     urb;                     ///< URB used for endpoint communication} USBH_EP;\nWrong: '/// comment' before 'struct {'\nBad:  repeat of Thread ID and URB does not add value; avoid abbreviations like 'Hw' \n\nBetter is:\n/// Hardware Endpoint Settings for communication functions\ntypedef struct {                        \n  osThreadId   thread_id;               ///< thread using USB Request Block (urb)\n  USBH_URB     urb;                     ///< USB Request Block for endpoint communication\n\n\n\nAPI Documentation in *.txt files\n--------------------------------\n\nA *.txt file that relates to a *.h contains:\n - Functional group assignments using \\defgroup along with \\brief description\n - Under \\details an overview description for each functional group (should contain a useful code example)\n - For each function in the header file a detailed description\n\n\nIMPORTANT: \nText *.txt files that document the user API of a component are located in .\\MW\\Doc\\component.\nOnly for *.h files that provide user API, there is exactly one text file with the same name.\nDefines/Functions that are internally used by a Component have no *.txt file.\n\nExample:\n  .\\MW\\component\\Include\\rl_usb.h    =>   .\\MW\\Doc\\component\\rl_usb.txt\n\nThe file documents each function that is exposed in *.h header file (and only those functions).\nIn case that functions are described in other files (i.e. USB Class Templates) there is a reference.\n\nFunctional Group assignments uses this syntax:\n---------------------------\n/**\n\\defgroup           a group definition \n[\\ingroup]          optionally within a group\n\\brief              brief description of the group\n\\details\ndescription\n*/\n\n/**\n\\addtogroup  a group definition\n@{\n*/\n\nBelow \\addtogroup the documentation for related functions is provided. This section\nends with @}\n\nFunction documentation uses this syntax:\n--------\n/**\n\\fn        functionName( args )\n\\details\n[\\note]\n[<b>Code Example</b>\n\\code | \\snippet]\n*/\n\nSee rl_usb.txt for examples\nNo ';' at the end of the function declaration. Otherwise function description gets ignored.\n\n\n\nComments in doxygen code blocks should be marked with //   and not /* ... */, which leads to errors.\n-------------------------------------------------------\nExample:   Wrong:\n\\code\nvoid ftp_server_notify (uint8_t event) {\n  /* Notify the user application about events in FTP server.*/\n  ...\n}\n\\endcode\n\nExample:   correct:\n\\code\nvoid ftp_server_notify (uint8_t event) {\n  // Notify the user application about events in FTP server.\n  ...\n}\n\\endcode\n\n\n\nCross references (between components)\n-------------------------------------\n\nWithin a single component (same .dxy configuration) one can easily created cross references.\nKnown symbol names are automatically assumed as a reference by Doxygen. Pages, sections and\nsubsections can be referenced using \"\\ref\" notation.\n\nCross references do not work between different components, though. Doxygen offers the possibility\nto import so called tags (symbol and section names) from an another external documentation.\nUnfortunately this creates output that crashes the MDK DoxyIndex importer. Hence cross references\nneeds to be placed manually using <a href=\"[url]\">...</a> notation, for the time being.\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/ActivationFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/ActivationFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/ActivationFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/BasicMathFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/BasicMathFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/BasicMathFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/ChangeLog_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/ChangeLog_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/ChangeLog_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/ConcatenationFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/ConcatenationFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/ConcatenationFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/ConvolutionFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/ConvolutionFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/ConvolutionFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/FullyConnectedFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/FullyConnectedFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/FullyConnectedFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/NNSupportFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/NNSupportFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/NNSupportFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/PoolingFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/PoolingFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/PoolingFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/ReshapeFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/ReshapeFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/ReshapeFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/SVDFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/SVDFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/SVDFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/SoftmaxFunctions_2CMakeLists_8txt.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/SoftmaxFunctions_2CMakeLists_8txt.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/SoftmaxFunctions_2CMakeLists_8txt.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/annotated.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/annotated.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/annotated.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/annotated.js",
    "content": "var annotated =\n[\n    [ \"arm_nn_double\", \"structarm__nn__double.html\", \"structarm__nn__double\" ],\n    [ \"arm_nn_long_long\", \"unionarm__nn__long__long.html\", \"unionarm__nn__long__long\" ],\n    [ \"arm_nnword\", \"unionarm__nnword.html\", \"unionarm__nnword\" ],\n    [ \"cmsis_nn_activation\", \"structcmsis__nn__activation.html\", \"structcmsis__nn__activation\" ],\n    [ \"cmsis_nn_context\", \"structcmsis__nn__context.html\", \"structcmsis__nn__context\" ],\n    [ \"cmsis_nn_conv_params\", \"structcmsis__nn__conv__params.html\", \"structcmsis__nn__conv__params\" ],\n    [ \"cmsis_nn_dims\", \"structcmsis__nn__dims.html\", \"structcmsis__nn__dims\" ],\n    [ \"cmsis_nn_dw_conv_params\", \"structcmsis__nn__dw__conv__params.html\", \"structcmsis__nn__dw__conv__params\" ],\n    [ \"cmsis_nn_fc_params\", \"structcmsis__nn__fc__params.html\", \"structcmsis__nn__fc__params\" ],\n    [ \"cmsis_nn_per_channel_quant_params\", \"structcmsis__nn__per__channel__quant__params.html\", \"structcmsis__nn__per__channel__quant__params\" ],\n    [ \"cmsis_nn_per_tensor_quant_params\", \"structcmsis__nn__per__tensor__quant__params.html\", \"structcmsis__nn__per__tensor__quant__params\" ],\n    [ \"cmsis_nn_pool_params\", \"structcmsis__nn__pool__params.html\", \"structcmsis__nn__pool__params\" ],\n    [ \"cmsis_nn_softmax_lut_s16\", \"structcmsis__nn__softmax__lut__s16.html\", \"structcmsis__nn__softmax__lut__s16\" ],\n    [ \"cmsis_nn_svdf_params\", \"structcmsis__nn__svdf__params.html\", \"structcmsis__nn__svdf__params\" ],\n    [ \"cmsis_nn_tile\", \"structcmsis__nn__tile.html\", \"structcmsis__nn__tile\" ]\n];"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__avgpool__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__avgpool__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__avgpool__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__avgpool__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__avgpool__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__avgpool__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__concatenation__s8__w_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__concatenation__s8__w_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__concatenation__s8__w_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__concatenation__s8__x_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__concatenation__s8__x_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__concatenation__s8__x_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__concatenation__s8__y_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__concatenation__s8__y_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__concatenation__s8__y_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__concatenation__s8__z_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__concatenation__s8__z_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__concatenation__s8__z_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__1__x__n__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__1__x__n__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__1__x__n__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__1x1__HWC__q7__fast__nonsquare_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__1x1__HWC__q7__fast__nonsquare_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__1x1__HWC__q7__fast__nonsquare_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__1x1__s8__fast_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__1x1__s8__fast_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__1x1__s8__fast_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__HWC__q15__basic_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q15__basic_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q15__basic_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__HWC__q15__fast_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q15__fast_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q15__fast_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__HWC__q15__fast__nonsquare_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q15__fast__nonsquare_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q15__fast__nonsquare_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__HWC__q7__RGB_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__RGB_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__RGB_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__HWC__q7__basic_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__basic_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__basic_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__HWC__q7__basic__nonsquare_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__basic__nonsquare_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__basic__nonsquare_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__HWC__q7__fast_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__fast_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__fast_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__HWC__q7__fast__nonsquare_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__fast__nonsquare_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__HWC__q7__fast__nonsquare_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__fast__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__fast__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__fast__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__wrapper__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__wrapper__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__wrapper__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__convolve__wrapper__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__wrapper__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__convolve__wrapper__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__conv__3x3__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__3x3__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__3x3__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__conv__fast__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__fast__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__fast__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__conv__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__conv__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__conv__s8__opt_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__s8__opt_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__s8__opt_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__conv__u8__basic__ver1_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__u8__basic__ver1_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__u8__basic__ver1_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__conv__wrapper__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__wrapper__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__wrapper__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__conv__wrapper__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__wrapper__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__conv__wrapper__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__separable__conv__HWC__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__separable__conv__HWC__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__separable__conv__HWC__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__depthwise__separable__conv__HWC__q7__nonsquare_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__separable__conv__HWC__q7__nonsquare_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__depthwise__separable__conv__HWC__q7__nonsquare_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__elementwise__add__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__elementwise__add__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__elementwise__add__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__elementwise__add__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__elementwise__add__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__elementwise__add__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__elementwise__mul__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__elementwise__mul__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__elementwise__mul__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__elementwise__mul__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__elementwise__mul__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__elementwise__mul__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__fully__connected__mat__q7__vec__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__mat__q7__vec__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__mat__q7__vec__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__fully__connected__mat__q7__vec__q15__opt_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__mat__q7__vec__q15__opt_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__mat__q7__vec__q15__opt_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__fully__connected__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__fully__connected__q15__opt_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__q15__opt_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__q15__opt_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__fully__connected__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__fully__connected__q7__opt_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__q7__opt_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__q7__opt_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__fully__connected__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__fully__connected__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__fully__connected__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__max__pool__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__max__pool__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__max__pool__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__max__pool__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__max__pool__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__max__pool__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__accumulate__q7__to__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__accumulate__q7__to__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__accumulate__q7__to__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__activations__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__activations__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__activations__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__activations__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__activations__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__activations__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__add__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__add__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__add__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__depthwise__conv__nt__t__padded__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__depthwise__conv__nt__t__padded__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__depthwise__conv__nt__t__padded__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__depthwise__conv__nt__t__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__depthwise__conv__nt__t__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__depthwise__conv__nt__t__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__depthwise__conv__nt__t__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__depthwise__conv__nt__t__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__depthwise__conv__nt__t__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__depthwise__conv__s8__core_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__depthwise__conv__s8__core_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__depthwise__conv__s8__core_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mat__mul__core__1x__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mul__core__1x__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mul__core__1x__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mat__mul__core__4x__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mul__core__4x__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mul__core__4x__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mat__mul__kernel__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mul__kernel__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mul__kernel__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mat__mult__kernel__q7__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__kernel__q7__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__kernel__q7__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mat__mult__kernel__q7__q15__reordered_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__kernel__q7__q15__reordered_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__kernel__q7__q15__reordered_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mat__mult__kernel__s8__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__kernel__s8__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__kernel__s8__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mat__mult__nt__t__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__nt__t__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__nt__t__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mat__mult__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mat__mult__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__math__types_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__math__types_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__math__types_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mult__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mult__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mult__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__mult__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mult__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__mult__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__softmax__common__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__softmax__common__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__softmax__common__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__tables_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__tables_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__tables_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__types_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__types_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__types_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__vec__mat__mult__t__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__vec__mat__mult__t__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__vec__mat__mult__t__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__vec__mat__mult__t__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__vec__mat__mult__t__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__vec__mat__mult__t__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nn__vec__mat__mult__t__svdf__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__vec__mat__mult__t__svdf__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nn__vec__mat__mult__t__svdf__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nnfunctions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nnfunctions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nnfunctions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nnsupportfunctions_8h.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nnsupportfunctions_8h.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nnsupportfunctions_8h.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__nntables_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nntables_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__nntables_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__pool__q7__HWC_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__pool__q7__HWC_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__pool__q7__HWC_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__q7__to__q15__no__shift_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__q7__to__q15__no__shift_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__q7__to__q15__no__shift_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__q7__to__q15__reordered__no__shift_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__q7__to__q15__reordered__no__shift_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__q7__to__q15__reordered__no__shift_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__q7__to__q15__reordered__with__offset_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__q7__to__q15__reordered__with__offset_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__q7__to__q15__reordered__with__offset_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__q7__to__q15__with__offset_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__q7__to__q15__with__offset_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__q7__to__q15__with__offset_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__relu6__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__relu6__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__relu6__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__relu__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__relu__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__relu__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__relu__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__relu__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__relu__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__reshape__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__reshape__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__reshape__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__softmax__q15_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__q15_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__q15_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__softmax__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__softmax__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__softmax__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__softmax__s8__s16_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__s8__s16_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__s8__s16_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__softmax__u8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__u8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__u8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__softmax__with__batch__q7_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__with__batch__q7_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__softmax__with__batch__q7_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__svdf__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__svdf__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__svdf__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/arm__svdf__state__s16__s8_8c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__svdf__state__s16__s8_8c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/arm__svdf__state__s16__s8_8c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/classes.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/classes.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/classes.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/cmsis.css",
    "content": "/* The standard CSS for doxygen */\n\nbody, table, div, p, dl {\n\tfont-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\n\tfont-size: 13px;\n\tline-height: 1.3;\n}\n\n/* CMSIS styles */\n\n.style1 {\n\t\ttext-align: center;\n}\n.style2 {\n\t\tcolor: #0000FF;\n\t\tfont-weight: normal;\n}\n.style3 {\n\t\ttext-align: left;\n}\n.style4 {\n\t\tcolor: #008000;\n}\n.style5 {\n\t\tcolor: #0000FF;\n}\n.style6 {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n.mand {\n\t\tcolor: #0000FF;\n}\n.opt {\n\t\tcolor: #008000;\n}\n.cond {\n\t\tcolor: #990000;\n}\n\n.choice \n{\n\tbackground-color:#F7F9D0;\n}\n.seq \n{\n\tbackground-color:#C9DECB;\n}\n.group1\n{\n\tbackground-color:#F8F1F1;\n}\n.group2\n{\n\tbackground-color:#DCEDEA;\n}\n\n\nul ul {\n\t\tlist-style-type: disc;\n}\n\nul ul ul {\n\t\tlist-style-type: disc;\n}\n\nul.hierarchy {\n\t\tcolor: green;\n}\n\nem {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n\n\n\n/*  CMSIS Tables */\ntable.cmtab1 {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: justify;\n\twidth:70%;\n}\n\nth.cmtab1 {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n\theight: 28px;\n}\n\ntd.cmtab1 {\n\tpadding:1px;\n\ttext-align: left;\n}\n\ntable.cmtable {\n\tborder-collapse:collapse;\n\ttext-align: justify;\n}\n\ntable.cmtable td, table.cmtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.cmtable th {\n\tbackground-color: #EBEFF6;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n\ttext-align:left;\n}\n\ntd.MonoTxt {\n\tfont-family:\"Arial monospaced for SAP\";\n}\n\ntd.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.h2 \n{\n\tfont-size: 120%;\n\tfont-weight: bold;\n}\n\ndiv.new\n{\n\tbackground-color:#ccffcc; /* light green */\n}\n\ndiv.mod\n{\n\tbackground-color:#ffe6cc;  /* light amber */\n}\n\ndiv.del\n{\n\tbackground-color:#ffcccc;  /* light red */\n}\n\n/* @group Heading Levels */\n\nh1 {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2 {\n\tfont-size: 120%;\n}\n\nh3 {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3A568E;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4464A5;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9AAED5;\n\tcolor: #ffffff;\n\tborder: 1px double #849CCC;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3A568E;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #293C63;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2B4069;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #EBEFF6;\n\tcolor: #000000;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        width: 100%;\n        margin-bottom: 10px;\n        border: 1px solid #A7B8DA;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A7B8DA;\n        border-bottom: 1px solid #A7B8DA;\n        vertical-align: top;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A7B8DA;\n        width: 100%;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        font-size: 90%;\n        color: #233456;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A7B8DA;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tmargin-left: 5px;\n\tfont-size: 8pt;\n\tpadding-left: 5px;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C3CFE6;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 7px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5072B7;\n}\n\n.image\n{\n        text-align: left;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #8EA4D0;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#314877;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D7DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4464A5;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/cmsis_footer.js",
    "content": "function writeFooter()  {\n    document.write('Generated on Mon Dec  5 2022 07:22:56 for CMSIS-NN Version 4.0.0 by Arm Ltd. All rights reserved.');\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/doxygen.css",
    "content": "/* The standard CSS for doxygen 1.8.6 */\n\nbody, table, div, p, dl {\n\tfont: 400 14px/22px Roboto,sans-serif;\n}\n\n/* @group Heading Levels */\n\nh1.groupheader {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont: 400 14px/28px Roboto,sans-serif;\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2.groupheader {\n\tborder-bottom: 1px solid #879ECB;\n\tcolor: #354C7B;\n\tfont-size: 150%;\n\tfont-weight: normal;\n\tmargin-top: 1.75em;\n\tpadding-top: 8px;\n\tpadding-bottom: 4px;\n\twidth: 100%;\n}\n\nh3.groupheader {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd {\n\tmargin-top: 2px;\n}\n\np.starttd {\n\tmargin-top: 0px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3D578C;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4665A2;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9CAFD4;\n\tcolor: #ffffff;\n\tborder: 1px double #869DCA;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited, a.line, a.line:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C4CFE5;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tmin-height: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\ndiv.line.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 10px cyan;\n}\n\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C4CFE5;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C4CFE5;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EEF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9CAFD4;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4A6AAA;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td, .fieldtable tr {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow, .fieldtable tr.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memSeparator {\n        border-bottom: 1px solid #DEE4F0;\n        line-height: 1px;\n        margin: 0px;\n        padding: 0px;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4665A2;\n        white-space: nowrap;\n\tfont-size: 80%;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4665A2;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n        display: table !important;\n        width: 100%;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A8B8D9;\n        border-left: 1px solid #A8B8D9;\n        border-right: 1px solid #A8B8D9;\n        padding: 6px 0px 6px 0px;\n        color: #253555;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E8F2;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A8B8D9;      \n        border-left: 1px solid #A8B8D9;      \n        border-right: 1px solid #A8B8D9; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n.paramname code {\n        line-height: 14px;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #728DC1;\n        border-top:1px solid #5373B4;\n        border-left:1px solid #5373B4;\n        border-right:1px solid #C4CFE5;\n        border-bottom:1px solid #C4CFE5;\n\ttext-shadow: none;\n\tcolor: white;\n\tmargin-right: 4px;\n\tpadding: 2px 3px;\n\tborder-radius: 3px;\n\tfont-size: 7pt;\n\twhite-space: nowrap;\n\tvertical-align: middle;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n\tpadding-top: 3px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.entry a img {\n        border: none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tpadding-top: 3px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3D578C;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #2A3D61;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #374F7F;\n\tcolor: #FFFFFF;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        /*width: 100%;*/\n        margin-bottom: 10px;\n        border: 1px solid #A8B8D9;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        vertical-align: top;\n}\n\n.fieldtable td.fieldname {\n        padding-top: 3px;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A8B8D9;\n        /*width: 100%;*/\n}\n\n.fieldtable td.fielddoc p:first-child {\n        margin-top: 0px;\n}       \n        \n.fieldtable td.fielddoc p:last-child {\n        margin-bottom: 2px;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E8F2;\n        font-size: 90%;\n        color: #253555;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A8B8D9;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\tbackground-position: 0 -5px;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#8AA0CC;\n\tborder:solid 1px #C2CDE4;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#364D7C;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n\tcolor: #283A5D;\n\tfont-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;\n\ttext-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n\ttext-decoration: none;        \n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6884BD;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#364D7C;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tfont-size: 8pt;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C4CFE5;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 10px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5373B4;\n}\n\n.image\n{\n        text-align: center;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.diagraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #90A5CE;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#334975;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D8DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4665A2;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n/* tooltip related style info */\n\n.ttc {\n        position: absolute;\n        display: none;\n}\n\n#powerTip {\n\tcursor: default;\n\twhite-space: nowrap;\n\tbackground-color: white;\n\tborder: 1px solid gray;\n\tborder-radius: 4px 4px 4px 4px;\n\tbox-shadow: 1px 1px 7px gray;\n\tdisplay: none;\n\tfont-size: smaller;\n\tmax-width: 80%;\n\topacity: 0.9;\n\tpadding: 1ex 1em 1em;\n\tposition: absolute;\n\tz-index: 2147483647;\n}\n\n#powerTip div.ttdoc {\n        color: grey;\n\tfont-style: italic;\n}\n\n#powerTip div.ttname a {\n        font-weight: bold;\n}\n\n#powerTip div.ttname {\n        font-weight: bold;\n}\n\n#powerTip div.ttdeci {\n        color: #006318;\n}\n\n#powerTip div {\n        margin: 0px;\n        padding: 0px;\n        font: 12px/16px Roboto,sans-serif;\n}\n\n#powerTip:before, #powerTip:after {\n\tcontent: \"\";\n\tposition: absolute;\n\tmargin: 0px;\n}\n\n#powerTip.n:after,  #powerTip.n:before,\n#powerTip.s:after,  #powerTip.s:before,\n#powerTip.w:after,  #powerTip.w:before,\n#powerTip.e:after,  #powerTip.e:before,\n#powerTip.ne:after, #powerTip.ne:before,\n#powerTip.se:after, #powerTip.se:before,\n#powerTip.nw:after, #powerTip.nw:before,\n#powerTip.sw:after, #powerTip.sw:before {\n\tborder: solid transparent;\n\tcontent: \" \";\n\theight: 0;\n\twidth: 0;\n\tposition: absolute;\n}\n\n#powerTip.n:after,  #powerTip.s:after,\n#powerTip.w:after,  #powerTip.e:after,\n#powerTip.nw:after, #powerTip.ne:after,\n#powerTip.sw:after, #powerTip.se:after {\n\tborder-color: rgba(255, 255, 255, 0);\n}\n\n#powerTip.n:before,  #powerTip.s:before,\n#powerTip.w:before,  #powerTip.e:before,\n#powerTip.nw:before, #powerTip.ne:before,\n#powerTip.sw:before, #powerTip.se:before {\n\tborder-color: rgba(128, 128, 128, 0);\n}\n\n#powerTip.n:after,  #powerTip.n:before,\n#powerTip.ne:after, #powerTip.ne:before,\n#powerTip.nw:after, #powerTip.nw:before {\n\ttop: 100%;\n}\n\n#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after {\n\tborder-top-color: #ffffff;\n\tborder-width: 10px;\n\tmargin: 0px -10px;\n}\n#powerTip.n:before {\n\tborder-top-color: #808080;\n\tborder-width: 11px;\n\tmargin: 0px -11px;\n}\n#powerTip.n:after, #powerTip.n:before {\n\tleft: 50%;\n}\n\n#powerTip.nw:after, #powerTip.nw:before {\n\tright: 14px;\n}\n\n#powerTip.ne:after, #powerTip.ne:before {\n\tleft: 14px;\n}\n\n#powerTip.s:after,  #powerTip.s:before,\n#powerTip.se:after, #powerTip.se:before,\n#powerTip.sw:after, #powerTip.sw:before {\n\tbottom: 100%;\n}\n\n#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after {\n\tborder-bottom-color: #ffffff;\n\tborder-width: 10px;\n\tmargin: 0px -10px;\n}\n\n#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before {\n\tborder-bottom-color: #808080;\n\tborder-width: 11px;\n\tmargin: 0px -11px;\n}\n\n#powerTip.s:after, #powerTip.s:before {\n\tleft: 50%;\n}\n\n#powerTip.sw:after, #powerTip.sw:before {\n\tright: 14px;\n}\n\n#powerTip.se:after, #powerTip.se:before {\n\tleft: 14px;\n}\n\n#powerTip.e:after, #powerTip.e:before {\n\tleft: 100%;\n}\n#powerTip.e:after {\n\tborder-left-color: #ffffff;\n\tborder-width: 10px;\n\ttop: 50%;\n\tmargin-top: -10px;\n}\n#powerTip.e:before {\n\tborder-left-color: #808080;\n\tborder-width: 11px;\n\ttop: 50%;\n\tmargin-top: -11px;\n}\n\n#powerTip.w:after, #powerTip.w:before {\n\tright: 100%;\n}\n#powerTip.w:after {\n\tborder-right-color: #ffffff;\n\tborder-width: 10px;\n\ttop: 50%;\n\tmargin-top: -10px;\n}\n#powerTip.w:before {\n\tborder-right-color: #808080;\n\tborder-width: 11px;\n\ttop: 50%;\n\tmargin-top: -11px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/dynsections.js",
    "content": "function toggleVisibility(linkObj)\n{\n var base = $(linkObj).attr('id');\n var summary = $('#'+base+'-summary');\n var content = $('#'+base+'-content');\n var trigger = $('#'+base+'-trigger');\n var src=$(trigger).attr('src');\n if (content.is(':visible')===true) {\n   content.hide();\n   summary.show();\n   $(linkObj).addClass('closed').removeClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');\n } else {\n   content.show();\n   summary.hide();\n   $(linkObj).removeClass('closed').addClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');\n } \n return false;\n}\n\nfunction updateStripes()\n{\n  $('table.directory tr').\n       removeClass('even').filter(':visible:even').addClass('even');\n}\nfunction toggleLevel(level)\n{\n  $('table.directory tr').each(function(){ \n    var l = this.id.split('_').length-1;\n    var i = $('#img'+this.id.substring(3));\n    var a = $('#arr'+this.id.substring(3));\n    if (l<level+1) {\n      i.attr('src','ftv2folderopen.png');\n      a.attr('src','ftv2mnode.png');\n      $(this).show();\n    } else if (l==level+1) {\n      i.attr('src','ftv2folderclosed.png');\n      a.attr('src','ftv2pnode.png');\n      $(this).show();\n    } else {\n      $(this).hide();\n    }\n  });\n  updateStripes();\n}\n\nfunction toggleFolder(id)\n{\n  //The clicked row\n  var currentRow = $('#row_'+id);\n  var currentRowImages = currentRow.find(\"img\");\n\n  //All rows after the clicked row\n  var rows = currentRow.nextAll(\"tr\");\n\n  //Only match elements AFTER this one (can't hide elements before)\n  var childRows = rows.filter(function() {\n    var re = new RegExp('^row_'+id+'\\\\d+_$', \"i\"); //only one sub\n    return this.id.match(re);\n  });\n\n  //First row is visible we are HIDING\n  if (childRows.filter(':first').is(':visible')===true) {\n    currentRowImages.filter(\"[id^=arr]\").attr('src', 'ftv2pnode.png');\n    currentRowImages.filter(\"[id^=img]\").attr('src', 'ftv2folderclosed.png');\n    rows.filter(\"[id^=row_\"+id+\"]\").hide();\n  } else { //We are SHOWING\n    //All sub images\n    var childImages = childRows.find(\"img\");\n    var childImg = childImages.filter(\"[id^=img]\");\n    var childArr = childImages.filter(\"[id^=arr]\");\n\n    currentRow.find(\"[id^=arr]\").attr('src', 'ftv2mnode.png'); //open row\n    currentRow.find(\"[id^=img]\").attr('src', 'ftv2folderopen.png'); //open row\n    childImg.attr('src','ftv2folderclosed.png'); //children closed\n    childArr.attr('src','ftv2pnode.png'); //children closed\n    childRows.show(); //show all children\n  }\n  updateStripes();\n}\n\n\nfunction toggleInherit(id)\n{\n  var rows = $('tr.inherit.'+id);\n  var img = $('tr.inherit_header.'+id+' img');\n  var src = $(img).attr('src');\n  if (rows.filter(':first').is(':visible')===true) {\n    rows.css('display','none');\n    $(img).attr('src',src.substring(0,src.length-8)+'closed.png');\n  } else {\n    rows.css('display','table-row'); // using show() causes jump in firefox\n    $(img).attr('src',src.substring(0,src.length-10)+'open.png');\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/files.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/files.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/files.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/functions.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/functions.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/functions.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/functions_vars.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/functions_vars.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/functions_vars.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_a.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_a.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_a.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_d.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_d.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_d.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_defs.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_defs.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_defs.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_e.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_e.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_e.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_enum.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_enum.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_enum.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_eval.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_eval.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_eval.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_f.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_f.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_f.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_a.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_a.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_a.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_c.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_c.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_c.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_d.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_d.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_d.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_e.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_e.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_e.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_f.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_f.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_f.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_l.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_l.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_l.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_m.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_m.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_m.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_n.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_n.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_n.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_q.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_q.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_q.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_r.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_r.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_r.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_s.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_s.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_s.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_func_t.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_t.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_func_t.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_l.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_l.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_l.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_m.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_m.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_m.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_n.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_n.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_n.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_o.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_o.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_o.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_p.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_p.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_p.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_q.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_q.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_q.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_r.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_r.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_r.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_s.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_s.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_s.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_t.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_t.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_t.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_type.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_type.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_type.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_u.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_u.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_u.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/globals_vars.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_vars.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/globals_vars.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__Acti.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Acti.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Acti.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__BasicMath.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__BasicMath.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__BasicMath.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__Concatenation.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Concatenation.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Concatenation.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__FC.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__FC.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__FC.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__NNBasicMath.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__NNBasicMath.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__NNBasicMath.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__NNConv.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__NNConv.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__NNConv.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__Pooling.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Pooling.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Pooling.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__Reshape.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Reshape.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Reshape.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__SVDF.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__SVDF.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__SVDF.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__Softmax.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Softmax.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/group__Softmax.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/group__groupNN.html",
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by,bA,bv,e,bw=0;if(bz&&bx.nodeType===1){bA=bz.toLowerCase().split(af);e=bA.length;for(;bw<e;bw++){bv=bA[bw];if(bv){by=b.propFix[bv]||bv;b.attr(bx,bv,\"\");bx.removeAttribute(F?bv:by);if(ao.test(bv)&&by in bx){bx[by]=false}}}}},attrHooks:{type:{set:function(e,bv){if(g.test(e.nodeName)&&e.parentNode){b.error(\"type property can't be changed\")}else{if(!b.support.radioValue&&bv===\"radio\"&&b.nodeName(e,\"input\")){var bw=e.value;e.setAttribute(\"type\",bv);if(bw){e.value=bw}return bv}}}},value:{get:function(bv,e){if(be&&b.nodeName(bv,\"button\")){return be.get(bv,e)}return e in bv?bv.value:null},set:function(bv,bw,e){if(be&&b.nodeName(bv,\"button\")){return be.set(bv,bw,e)}bv.value=bw}}},propFix:{tabindex:\"tabIndex\",readonly:\"readOnly\",\"for\":\"htmlFor\",\"class\":\"className\",maxlength:\"maxLength\",cellspacing:\"cellSpacing\",cellpadding:\"cellPadding\",rowspan:\"rowSpan\",colspan:\"colSpan\",usemap:\"useMap\",frameborder:\"frameBorder\",contenteditable:\"contentEditable\"},prop:function(bz,bx,bA){var bw,e,by,bv=bz.nodeType;if(!bz||bv===3||bv===8||bv===2){return}by=bv!==1||!b.isXMLDoc(bz);if(by){bx=b.propFix[bx]||bx;e=b.propHooks[bx]}if(bA!==L){if(e&&\"set\" in e&&(bw=e.set(bz,bA,bx))!==L){return bw}else{return(bz[bx]=bA)}}else{if(e&&\"get\" in e&&(bw=e.get(bz,bx))!==null){return bw}else{return bz[bx]}}},propHooks:{tabIndex:{get:function(bv){var e=bv.getAttributeNode(\"tabindex\");return e&&e.specified?parseInt(e.value,10):D.test(bv.nodeName)||l.test(bv.nodeName)&&bv.href?0:L}}}});b.attrHooks.tabindex=b.propHooks.tabIndex;aY={get:function(bv,e){var bx,bw=b.prop(bv,e);return bw===true||typeof bw!==\"boolean\"&&(bx=bv.getAttributeNode(e))&&bx.nodeValue!==false?e.toLowerCase():L},set:function(bv,bx,e){var bw;if(bx===false){b.removeAttr(bv,e)}else{bw=b.propFix[e]||e;if(bw in bv){bv[bw]=true}bv.setAttribute(e,e.toLowerCase())}return e}};if(!F){aF={name:true,id:true};be=b.valHooks.button={get:function(bw,bv){var e;e=bw.getAttributeNode(bv);return e&&(aF[bv]?e.nodeValue!==\"\":e.specified)?e.nodeValue:L},set:function(bw,bx,bv){var e=bw.getAttributeNode(bv);if(!e){e=av.createAttribute(bv);bw.setAttributeNode(e)}return(e.nodeValue=bx+\"\")}};b.attrHooks.tabindex.set=be.set;b.each([\"width\",\"height\"],function(bv,e){b.attrHooks[e]=b.extend(b.attrHooks[e],{set:function(bw,bx){if(bx===\"\"){bw.setAttribute(e,\"auto\");return bx}}})});b.attrHooks.contenteditable={get:be.get,set:function(bv,bw,e){if(bw===\"\"){bw=\"false\"}be.set(bv,bw,e)}}}if(!b.support.hrefNormalized){b.each([\"href\",\"src\",\"width\",\"height\"],function(bv,e){b.attrHooks[e]=b.extend(b.attrHooks[e],{get:function(bx){var bw=bx.getAttribute(e,2);return bw===null?L:bw}})})}if(!b.support.style){b.attrHooks.style={get:function(e){return e.style.cssText.toLowerCase()||L},set:function(e,bv){return(e.style.cssText=\"\"+bv)}}}if(!b.support.optSelected){b.propHooks.selected=b.extend(b.propHooks.selected,{get:function(bv){var e=bv.parentNode;if(e){e.selectedIndex;if(e.parentNode){e.parentNode.selectedIndex}}return null}})}if(!b.support.enctype){b.propFix.enctype=\"encoding\"}if(!b.support.checkOn){b.each([\"radio\",\"checkbox\"],function(){b.valHooks[this]={get:function(e){return e.getAttribute(\"value\")===null?\"on\":e.value}}})}b.each([\"radio\",\"checkbox\"],function(){b.valHooks[this]=b.extend(b.valHooks[this],{set:function(e,bv){if(b.isArray(bv)){return(e.checked=b.inArray(b(e).val(),bv)>=0)}}})});var bd=/^(?:textarea|input|select)$/i,n=/^([^\\.]*)?(?:\\.(.+))?$/,J=/\\bhover(\\.\\S+)?\\b/,aO=/^key/,bf=/^(?:mouse|contextmenu)|click/,T=/^(?:focusinfocus|focusoutblur)$/,U=/^(\\w*)(?:#([\\w\\-]+))?(?:\\.([\\w\\-]+))?$/,Y=function(e){var bv=U.exec(e);if(bv){bv[1]=(bv[1]||\"\").toLowerCase();bv[3]=bv[3]&&new RegExp(\"(?:^|\\\\s)\"+bv[3]+\"(?:\\\\s|$)\")}return bv},j=function(bw,e){var bv=bw.attributes||{};return((!e[1]||bw.nodeName.toLowerCase()===e[1])&&(!e[2]||(bv.id||{}).value===e[2])&&(!e[3]||e[3].test((bv[\"class\"]||{}).value)))},bt=function(e){return b.event.special.hover?e:e.replace(J,\"mouseenter$1 mouseleave$1\")};b.event={add:function(bx,bC,bJ,bA,by){var bD,bB,bK,bI,bH,bF,e,bG,bv,bz,bw,bE;if(bx.nodeType===3||bx.nodeType===8||!bC||!bJ||!(bD=b._data(bx))){return}if(bJ.handler){bv=bJ;bJ=bv.handler}if(!bJ.guid){bJ.guid=b.guid++}bK=bD.events;if(!bK){bD.events=bK={}}bB=bD.handle;if(!bB){bD.handle=bB=function(bL){return typeof b!==\"undefined\"&&(!bL||b.event.triggered!==bL.type)?b.event.dispatch.apply(bB.elem,arguments):L};bB.elem=bx}bC=b.trim(bt(bC)).split(\" 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bw){b.event.remove(bJ,bz+bE[bF],bv,bH,true)}continue}by=b.event.special[bz]||{};bz=(bH?by.delegateType:by.bindType)||bz;bD=bw[bz]||[];bA=bD.length;bC=bC?new RegExp(\"(^|\\\\.)\"+bC.split(\".\").sort().join(\"\\\\.(?:.*\\\\.)?\")+\"(\\\\.|$)\"):null;for(bG=0;bG<bD.length;bG++){e=bD[bG];if((bB||bL===e.origType)&&(!bv||bv.guid===e.guid)&&(!bC||bC.test(e.namespace))&&(!bH||bH===e.selector||bH===\"**\"&&e.selector)){bD.splice(bG--,1);if(e.selector){bD.delegateCount--}if(by.remove){by.remove.call(bJ,e)}}}if(bD.length===0&&bA!==bD.length){if(!by.teardown||by.teardown.call(bJ,bC)===false){b.removeEvent(bJ,bz,bI.handle)}delete bw[bz]}}if(b.isEmptyObject(bw)){bK=bI.handle;if(bK){bK.elem=null}b.removeData(bJ,[\"events\",\"handle\"],true)}},customEvent:{getData:true,setData:true,changeData:true},trigger:function(bv,bD,bA,bJ){if(bA&&(bA.nodeType===3||bA.nodeType===8)){return}var bG=bv.type||bv,bx=[],e,bw,bC,bH,bz,by,bF,bE,bB,bI;if(T.test(bG+b.event.triggered)){return}if(bG.indexOf(\"!\")>=0){bG=bG.slice(0,-1);bw=true}if(bG.indexOf(\".\")>=0){bx=bG.split(\".\");bG=bx.shift();bx.sort()}if((!bA||b.event.customEvent[bG])&&!b.event.global[bG]){return}bv=typeof bv===\"object\"?bv[b.expando]?bv:new b.Event(bG,bv):new b.Event(bG);bv.type=bG;bv.isTrigger=true;bv.exclusive=bw;bv.namespace=bx.join(\".\");bv.namespace_re=bv.namespace?new RegExp(\"(^|\\\\.)\"+bx.join(\"\\\\.(?:.*\\\\.)?\")+\"(\\\\.|$)\"):null;by=bG.indexOf(\":\")<0?\"on\"+bG:\"\";if(!bA){e=b.cache;for(bC in e){if(e[bC].events&&e[bC].events[bG]){b.event.trigger(bv,bD,e[bC].handle.elem,true)}}return}bv.result=L;if(!bv.target){bv.target=bA}bD=bD!=null?b.makeArray(bD):[];bD.unshift(bv);bF=b.event.special[bG]||{};if(bF.trigger&&bF.trigger.apply(bA,bD)===false){return}bB=[[bA,bF.bindType||bG]];if(!bJ&&!bF.noBubble&&!b.isWindow(bA)){bI=bF.delegateType||bG;bH=T.test(bI+bG)?bA:bA.parentNode;bz=null;for(;bH;bH=bH.parentNode){bB.push([bH,bI]);bz=bH}if(bz&&bz===bA.ownerDocument){bB.push([bz.defaultView||bz.parentWindow||bb,bI])}}for(bC=0;bC<bB.length&&!bv.isPropagationStopped();bC++){bH=bB[bC][0];bv.type=bB[bC][1];bE=(b._data(bH,\"events\")||{})[bv.type]&&b._data(bH,\"handle\");if(bE){bE.apply(bH,bD)}bE=by&&bH[by];if(bE&&b.acceptData(bH)&&bE.apply(bH,bD)===false){bv.preventDefault()}}bv.type=bG;if(!bJ&&!bv.isDefaultPrevented()){if((!bF._default||bF._default.apply(bA.ownerDocument,bD)===false)&&!(bG===\"click\"&&b.nodeName(bA,\"a\"))&&b.acceptData(bA)){if(by&&bA[bG]&&((bG!==\"focus\"&&bG!==\"blur\")||bv.target.offsetWidth!==0)&&!b.isWindow(bA)){bz=bA[by];if(bz){bA[by]=null}b.event.triggered=bG;bA[bG]();b.event.triggered=L;if(bz){bA[by]=bz}}}}return bv.result},dispatch:function(e){e=b.event.fix(e||bb.event);var bz=((b._data(this,\"events\")||{})[e.type]||[]),bA=bz.delegateCount,bG=[].slice.call(arguments,0),by=!e.exclusive&&!e.namespace,bH=[],bC,bB,bK,bx,bF,bE,bv,bD,bI,bw,bJ;bG[0]=e;e.delegateTarget=this;if(bA&&!e.target.disabled&&!(e.button&&e.type===\"click\")){bx=b(this);bx.context=this.ownerDocument||this;for(bK=e.target;bK!=this;bK=bK.parentNode||this){bE={};bD=[];bx[0]=bK;for(bC=0;bC<bA;bC++){bI=bz[bC];bw=bI.selector;if(bE[bw]===L){bE[bw]=(bI.quick?j(bK,bI.quick):bx.is(bw))}if(bE[bw]){bD.push(bI)}}if(bD.length){bH.push({elem:bK,matches:bD})}}}if(bz.length>bA){bH.push({elem:this,matches:bz.slice(bA)})}for(bC=0;bC<bH.length&&!e.isPropagationStopped();bC++){bv=bH[bC];e.currentTarget=bv.elem;for(bB=0;bB<bv.matches.length&&!e.isImmediatePropagationStopped();bB++){bI=bv.matches[bB];if(by||(!e.namespace&&!bI.namespace)||e.namespace_re&&e.namespace_re.test(bI.namespace)){e.data=bI.data;e.handleObj=bI;bF=((b.event.special[bI.origType]||{}).handle||bI.handler).apply(bv.elem,bG);if(bF!==L){e.result=bF;if(bF===false){e.preventDefault();e.stopPropagation()}}}}}return e.result},props:\"attrChange attrName relatedNode srcElement altKey bubbles cancelable ctrlKey currentTarget eventPhase metaKey relatedTarget shiftKey target timeStamp view which\".split(\" \"),fixHooks:{},keyHooks:{props:\"char charCode key keyCode\".split(\" \"),filter:function(bv,e){if(bv.which==null){bv.which=e.charCode!=null?e.charCode:e.keyCode}return bv}},mouseHooks:{props:\"button buttons clientX clientY fromElement offsetX offsetY pageX pageY screenX screenY toElement\".split(\" \"),filter:function(bx,bw){var by,bz,e,bv=bw.button,bA=bw.fromElement;if(bx.pageX==null&&bw.clientX!=null){by=bx.target.ownerDocument||av;bz=by.documentElement;e=by.body;bx.pageX=bw.clientX+(bz&&bz.scrollLeft||e&&e.scrollLeft||0)-(bz&&bz.clientLeft||e&&e.clientLeft||0);bx.pageY=bw.clientY+(bz&&bz.scrollTop||e&&e.scrollTop||0)-(bz&&bz.clientTop||e&&e.clientTop||0)}if(!bx.relatedTarget&&bA){bx.relatedTarget=bA===bx.target?bw.toElement:bA}if(!bx.which&&bv!==L){bx.which=(bv&1?1:(bv&2?3:(bv&4?2:0)))}return bx}},fix:function(bw){if(bw[b.expando]){return bw}var bv,bz,e=bw,bx=b.event.fixHooks[bw.type]||{},by=bx.props?this.props.concat(bx.props):this.props;bw=b.Event(e);for(bv=by.length;bv;){bz=by[--bv];bw[bz]=e[bz]}if(!bw.target){bw.target=e.srcElement||av}if(bw.target.nodeType===3){bw.target=bw.target.parentNode}if(bw.metaKey===L){bw.metaKey=bw.ctrlKey}return bx.filter?bx.filter(bw,e):bw},special:{ready:{setup:b.bindReady},load:{noBubble:true},focus:{delegateType:\"focusin\"},blur:{delegateType:\"focusout\"},beforeunload:{setup:function(bw,bv,e){if(b.isWindow(this)){this.onbeforeunload=e}},teardown:function(bv,e){if(this.onbeforeunload===e){this.onbeforeunload=null}}}},simulate:function(bw,by,bx,bv){var bz=b.extend(new b.Event(),bx,{type:bw,isSimulated:true,originalEvent:{}});if(bv){b.event.trigger(bz,null,by)}else{b.event.dispatch.call(by,bz)}if(bz.isDefaultPrevented()){bx.preventDefault()}}};b.event.handle=b.event.dispatch;b.removeEvent=av.removeEventListener?function(bv,e,bw){if(bv.removeEventListener){bv.removeEventListener(e,bw,false)}}:function(bv,e,bw){if(bv.detachEvent){bv.detachEvent(\"on\"+e,bw)}};b.Event=function(bv,e){if(!(this instanceof b.Event)){return new b.Event(bv,e)}if(bv&&bv.type){this.originalEvent=bv;this.type=bv.type;this.isDefaultPrevented=(bv.defaultPrevented||bv.returnValue===false||bv.getPreventDefault&&bv.getPreventDefault())?i:bk}else{this.type=bv}if(e){b.extend(this,e)}this.timeStamp=bv&&bv.timeStamp||b.now();this[b.expando]=true};function bk(){return false}function i(){return true}b.Event.prototype={preventDefault:function(){this.isDefaultPrevented=i;var bv=this.originalEvent;if(!bv){return}if(bv.preventDefault){bv.preventDefault()}else{bv.returnValue=false}},stopPropagation:function(){this.isPropagationStopped=i;var bv=this.originalEvent;if(!bv){return}if(bv.stopPropagation){bv.stopPropagation()}bv.cancelBubble=true},stopImmediatePropagation:function(){this.isImmediatePropagationStopped=i;this.stopPropagation()},isDefaultPrevented:bk,isPropagationStopped:bk,isImmediatePropagationStopped:bk};b.each({mouseenter:\"mouseover\",mouseleave:\"mouseout\"},function(bv,e){b.event.special[bv]={delegateType:e,bindType:e,handle:function(bz){var bB=this,bA=bz.relatedTarget,by=bz.handleObj,bw=by.selector,bx;if(!bA||(bA!==bB&&!b.contains(bB,bA))){bz.type=by.origType;bx=by.handler.apply(this,arguments);bz.type=e}return bx}}});if(!b.support.submitBubbles){b.event.special.submit={setup:function(){if(b.nodeName(this,\"form\")){return false\n}b.event.add(this,\"click._submit keypress._submit\",function(bx){var bw=bx.target,bv=b.nodeName(bw,\"input\")||b.nodeName(bw,\"button\")?bw.form:L;if(bv&&!bv._submit_attached){b.event.add(bv,\"submit._submit\",function(e){if(this.parentNode&&!e.isTrigger){b.event.simulate(\"submit\",this.parentNode,e,true)}});bv._submit_attached=true}})},teardown:function(){if(b.nodeName(this,\"form\")){return false}b.event.remove(this,\"._submit\")}}}if(!b.support.changeBubbles){b.event.special.change={setup:function(){if(bd.test(this.nodeName)){if(this.type===\"checkbox\"||this.type===\"radio\"){b.event.add(this,\"propertychange._change\",function(e){if(e.originalEvent.propertyName===\"checked\"){this._just_changed=true}});b.event.add(this,\"click._change\",function(e){if(this._just_changed&&!e.isTrigger){this._just_changed=false;b.event.simulate(\"change\",this,e,true)}})}return false}b.event.add(this,\"beforeactivate._change\",function(bw){var bv=bw.target;if(bd.test(bv.nodeName)&&!bv._change_attached){b.event.add(bv,\"change._change\",function(e){if(this.parentNode&&!e.isSimulated&&!e.isTrigger){b.event.simulate(\"change\",this.parentNode,e,true)}});bv._change_attached=true}})},handle:function(bv){var e=bv.target;if(this!==e||bv.isSimulated||bv.isTrigger||(e.type!==\"radio\"&&e.type!==\"checkbox\")){return bv.handleObj.handler.apply(this,arguments)}},teardown:function(){b.event.remove(this,\"._change\");return bd.test(this.nodeName)}}}if(!b.support.focusinBubbles){b.each({focus:\"focusin\",blur:\"focusout\"},function(bx,e){var bv=0,bw=function(by){b.event.simulate(e,by.target,b.event.fix(by),true)};b.event.special[e]={setup:function(){if(bv++===0){av.addEventListener(bx,bw,true)}},teardown:function(){if(--bv===0){av.removeEventListener(bx,bw,true)}}}})}b.fn.extend({on:function(bw,e,bz,by,bv){var bA,bx;if(typeof bw===\"object\"){if(typeof e!==\"string\"){bz=e;e=L}for(bx in bw){this.on(bx,e,bz,bw[bx],bv)}return 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bw=this[0],bv=this.offsetParent(),bx=this.offset(),e=ad.test(bv[0].nodeName)?{top:0,left:0}:bv.offset();bx.top-=parseFloat(b.css(bw,\"marginTop\"))||0;bx.left-=parseFloat(b.css(bw,\"marginLeft\"))||0;e.top+=parseFloat(b.css(bv[0],\"borderTopWidth\"))||0;e.left+=parseFloat(b.css(bv[0],\"borderLeftWidth\"))||0;return{top:bx.top-e.top,left:bx.left-e.left}},offsetParent:function(){return this.map(function(){var e=this.offsetParent||av.body;while(e&&(!ad.test(e.nodeName)&&b.css(e,\"position\")===\"static\")){e=e.offsetParent}return e})}});b.each([\"Left\",\"Top\"],function(bv,e){var bw=\"scroll\"+e;b.fn[bw]=function(bz){var bx,by;if(bz===L){bx=this[0];if(!bx){return null}by=aK(bx);return by?(\"pageXOffset\" in by)?by[bv?\"pageYOffset\":\"pageXOffset\"]:b.support.boxModel&&by.document.documentElement[bw]||by.document.body[bw]:bx[bw]}return this.each(function(){by=aK(this);if(by){by.scrollTo(!bv?bz:b(by).scrollLeft(),bv?bz:b(by).scrollTop())}else{this[bw]=bz}})}});function aK(e){return b.isWindow(e)?e:e.nodeType===9?e.defaultView||e.parentWindow:false}b.each([\"Height\",\"Width\"],function(bv,e){var bw=e.toLowerCase();b.fn[\"inner\"+e]=function(){var bx=this[0];return bx?bx.style?parseFloat(b.css(bx,bw,\"padding\")):this[bw]():null};b.fn[\"outer\"+e]=function(by){var bx=this[0];return bx?bx.style?parseFloat(b.css(bx,bw,by?\"margin\":\"border\")):this[bw]():null};b.fn[bw]=function(bz){var bA=this[0];if(!bA){return bz==null?null:this}if(b.isFunction(bz)){return this.each(function(bE){var bD=b(this);bD[bw](bz.call(this,bE,bD[bw]()))})}if(b.isWindow(bA)){var bB=bA.document.documentElement[\"client\"+e],bx=bA.document.body;return bA.document.compatMode===\"CSS1Compat\"&&bB||bx&&bx[\"client\"+e]||bB}else{if(bA.nodeType===9){return Math.max(bA.documentElement[\"client\"+e],bA.body[\"scroll\"+e],bA.documentElement[\"scroll\"+e],bA.body[\"offset\"+e],bA.documentElement[\"offset\"+e])}else{if(bz===L){var bC=b.css(bA,bw),by=parseFloat(bC);return b.isNumeric(by)?by:bC}else{return this.css(bw,typeof bz===\"string\"?bz:bz+\"px\")}}}}});bb.jQuery=bb.$=b;if(typeof define===\"function\"&&define.amd&&define.amd.jQuery){define(\"jquery\",[],function(){return b\n})}})(window);\n/*!\n * jQuery UI 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI\n */\n(function(a,d){a.ui=a.ui||{};if(a.ui.version){return}a.extend(a.ui,{version:\"1.8.18\",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}});a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(e,f){return typeof e===\"number\"?this.each(function(){var g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css(\"position\")))||(/absolute/).test(this.css(\"position\"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,\"position\",1))&&(/(auto|scroll)/).test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0)}return(/fixed/).test(this.css(\"position\"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css(\"zIndex\",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css(\"position\");if(e===\"absolute\"||e===\"relative\"||e===\"fixed\"){g=parseInt(f.css(\"zIndex\"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?\"selectstart\":\"mousedown\")+\".ui-disableSelection\",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(\".ui-disableSelection\")}});a.each([\"Width\",\"Height\"],function(g,e){var f=e===\"Width\"?[\"Left\",\"Right\"]:[\"Top\",\"Bottom\"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,\"padding\"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,\"border\"+this+\"Width\",true))||0}if(n){l-=parseFloat(a.curCSS(m,\"margin\"+this,true))||0}});return l}a.fn[\"inner\"+e]=function(i){if(i===d){return k[\"inner\"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+\"px\")})};a.fn[\"outer\"+e]=function(i,l){if(typeof i!==\"number\"){return k[\"outer\"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+\"px\")})}});function c(g,e){var j=g.nodeName.toLowerCase();if(\"area\"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!==\"map\"){return false}f=a(\"img[usemap=#\"+h+\"]\")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:\"a\"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,\"visibility\")===\"hidden\"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[\":\"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,\"tabindex\")))},tabbable:function(g){var e=a.attr(g,\"tabindex\"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement(\"div\"));f.offsetHeight;a.extend(f.style,{minHeight:\"100px\",height:\"auto\",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart=\"onselectstart\" in f;e.removeChild(f).style.display=\"none\"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h<j.length;h++){if(e.options[j[h][0]]){j[h][1].apply(e.element,f)}}}},contains:function(f,e){return document.compareDocumentPosition?f.compareDocumentPosition(e)&16:f!==e&&f.contains(e)},hasScroll:function(h,f){if(a(h).css(\"overflow\")===\"hidden\"){return false}var e=(f&&f===\"left\")?\"scrollLeft\":\"scrollTop\",g=false;if(h[e]>0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*!\n * jQuery UI Widget 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Widget\n */\n(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler(\"remove\")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b(\"*\",this).add([this]).each(function(){try{b(this).triggerHandler(\"remove\")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(\".\")[0],j;f=f.split(\".\")[1];j=g+\"-\"+f;if(!e){e=h;h=b.Widget}b.expr[\":\"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i===\"string\",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)===\"_\"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:\"widget\",widgetEventPrefix:\"\",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind(\"remove.\"+this.widgetName,function(){e.destroy()});this._create();this._trigger(\"create\");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind(\".\"+this.widgetName).removeData(this.widgetName);this.widget().unbind(\".\"+this.widgetName).removeAttr(\"aria-disabled\").removeClass(this.widgetBaseClass+\"-disabled ui-state-disabled\")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f===\"string\"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e===\"disabled\"){this.widget()[f?\"addClass\":\"removeClass\"](this.widgetBaseClass+\"-disabled ui-state-disabled\").attr(\"aria-disabled\",f)}return this},enable:function(){return this._setOption(\"disabled\",false)},disable:function(){return this._setOption(\"disabled\",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!\n * jQuery UI Mouse 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Mouse\n *\n * Depends:\n *\tjquery.ui.widget.js\n */\n(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget(\"ui.mouse\",{options:{cancel:\":input,option\",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind(\"mousedown.\"+this.widgetName,function(e){return d._mouseDown(e)}).bind(\"click.\"+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+\".preventClickEvent\")){b.removeData(e.target,d.widgetName+\".preventClickEvent\");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind(\".\"+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel==\"string\"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+\".preventClickEvent\")){b.removeData(f.target,this.widgetName+\".preventClickEvent\")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).bind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).unbind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+\".preventClickEvent\",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget(\"ui.resizable\",c.ui.mouse,{widgetEventPrefix:\"resize\",options:{alsoResize:false,animate:false,animateDuration:\"slow\",animateEasing:\"swing\",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:\"e,s,se\",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass(\"ui-resizable\");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||\"ui-resizable-helper\":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class=\"ui-wrapper\" style=\"overflow: hidden;\"></div>').css({position:this.element.css(\"position\"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css(\"top\"),left:this.element.css(\"left\")}));this.element=this.element.parent().data(\"resizable\",this.element.data(\"resizable\"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css(\"marginLeft\"),marginTop:this.originalElement.css(\"marginTop\"),marginRight:this.originalElement.css(\"marginRight\"),marginBottom:this.originalElement.css(\"marginBottom\")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css(\"resize\");this.originalElement.css(\"resize\",\"none\");this._proportionallyResizeElements.push(this.originalElement.css({position:\"static\",zoom:1,display:\"block\"}));this.originalElement.css({margin:this.originalElement.css(\"margin\")});this._proportionallyResize()}this.handles=k.handles||(!c(\".ui-resizable-handle\",this.element).length?\"e,s,se\":{n:\".ui-resizable-n\",e:\".ui-resizable-e\",s:\".ui-resizable-s\",w:\".ui-resizable-w\",se:\".ui-resizable-se\",sw:\".ui-resizable-sw\",ne:\".ui-resizable-ne\",nw:\".ui-resizable-nw\"});if(this.handles.constructor==String){if(this.handles==\"all\"){this.handles=\"n,e,s,w,se,sw,ne,nw\"}var l=this.handles.split(\",\");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e=\"ui-resizable-\"+j;var h=c('<div class=\"ui-resizable-handle '+e+'\"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if(\"se\"==j){h.addClass(\"ui-icon ui-icon-gripsmall-diagonal-se\")}this.handles[j]=\".ui-resizable-\"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=[\"padding\",/ne|nw|n/.test(n)?\"Top\":/se|sw|s/.test(n)?\"Bottom\":/^e$/.test(n)?\"Right\":\"Left\"].join(\"\");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(\".ui-resizable-handle\",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:\"se\"}});if(k.autoHide){this._handles.hide();c(this.element).addClass(\"ui-resizable-autohide\").hover(function(){if(k.disabled){return}c(this).removeClass(\"ui-resizable-autohide\");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass(\"ui-resizable-autohide\");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass(\"ui-resizable ui-resizable-disabled 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  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/modules.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/modules.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/modules.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/modules.js",
    "content": "var modules =\n[\n    [ \"Neural Network Functions\", \"group__groupNN.html\", \"group__groupNN\" ],\n    [ \"Neural Network Data Conversion Functions\", \"group__nndata__convert.html\", \"group__nndata__convert\" ],\n    [ \"Basic Math Functions for Neural Network Computation\", \"group__NNBasicMath.html\", \"group__NNBasicMath\" ]\n];"
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  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/navtree.css",
    "content": "#nav-tree .children_ul {\n  margin:0;\n  padding:4px;\n}\n\n#nav-tree ul {\n  list-style:none outside none;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree li {\n  white-space:nowrap;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .plus {\n  margin:0px;\n}\n\n#nav-tree .selected {\n  background-image: url('tab_a.png');\n  background-repeat:repeat-x;\n  color: #fff;\n  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n\n#nav-tree img {\n  margin:0px;\n  padding:0px;\n  border:0px;\n  vertical-align: middle;\n}\n\n#nav-tree a {\n  text-decoration:none;\n  padding:0px;\n  margin:0px;\n  outline:none;\n}\n\n#nav-tree .label {\n  margin:0px;\n  padding:0px;\n  font: 12px 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;\n}\n\n#nav-tree .label a {\n  padding:2px;\n}\n\n#nav-tree .selected a {\n  text-decoration:none;\n  color:#fff;\n}\n\n#nav-tree .children_ul {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .item {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree {\n  padding: 0px 0px;\n  background-color: #FAFAFF; \n  font-size:14px;\n  overflow:auto;\n}\n\n#doc-content {\n  overflow:auto;\n  display:block;\n  padding:0px;\n  margin:0px;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#side-nav {\n  padding:0 6px 0 0;\n  margin: 0px;\n  display:block;\n  position: absolute;\n  left: 0px;\n  width: 250px;\n}\n\n.ui-resizable .ui-resizable-handle {\n  display:block;\n}\n\n.ui-resizable-e {\n  background:url(\"ftv2splitbar.png\") repeat scroll right center transparent;\n  cursor:e-resize;\n  height:100%;\n  right:0;\n  top:0;\n  width:6px;\n}\n\n.ui-resizable-handle {\n  display:none;\n  font-size:0.1px;\n  position:absolute;\n  z-index:1;\n}\n\n#nav-tree-contents {\n  margin: 6px 0px 0px 0px;\n}\n\n#nav-tree {\n  background-image:url('nav_h.png');\n  background-repeat:repeat-x;\n  background-color: #F9FAFC;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#nav-sync {\n  position:absolute;\n  top:5px;\n  right:24px;\n  z-index:0;\n}\n\n#nav-sync img {\n  opacity:0.3;\n}\n\n#nav-sync img:hover {\n  opacity:0.9;\n}\n\n@media print\n{\n  #nav-tree { display: none; }\n  div.ui-resizable-handle { display: none; position: relative; }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/navtree.js",
    "content": "var NAVTREE =\n[\n  [ \"CMSIS-NN\", \"index.html\" ]\n];\n\nvar NAVTREEINDEX =\n[\n\"ChangeLog_pg.html\"\n];\n\nvar SYNCONMSG = 'click to disable panel synchronisation';\nvar SYNCOFFMSG = 'click to enable panel synchronisation';\nvar SYNCONMSG = 'click to disable panel synchronisation';\nvar SYNCOFFMSG = 'click to enable panel synchronisation';\nvar navTreeSubIndices = new Array();\n\nfunction getData(varName)\n{\n  var i = varName.lastIndexOf('/');\n  var n = i>=0 ? varName.substring(i+1) : varName;\n  return eval(n.replace(/\\-/g,'_'));\n}\n\nfunction stripPath(uri)\n{\n  return uri.substring(uri.lastIndexOf('/')+1);\n}\n\nfunction stripPath2(uri)\n{\n  var i = uri.lastIndexOf('/');\n  var s = uri.substring(i+1);\n  var m = uri.substring(0,i+1).match(/\\/d\\w\\/d\\w\\w\\/$/);\n  return m ? uri.substring(i-6) : s;\n}\n\nfunction localStorageSupported()\n{\n  try {\n    return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem;\n  }\n  catch(e) {\n    return false;\n  }\n}\n\n\nfunction storeLink(link)\n{\n  if (!$(\"#nav-sync\").hasClass('sync') && localStorageSupported()) {\n      window.localStorage.setItem('navpath',link);\n  }\n}\n\nfunction deleteLink()\n{\n  if (localStorageSupported()) {\n    window.localStorage.setItem('navpath','');\n  }\n}\n\nfunction cachedLink()\n{\n  if (localStorageSupported()) {\n    return window.localStorage.getItem('navpath');\n  } else {\n    return '';\n  }\n}\n\nfunction getScript(scriptName,func,show)\n{\n  var head = document.getElementsByTagName(\"head\")[0];\n  var script = document.createElement('script');\n  script.id = scriptName;\n  script.type = 'text/javascript';\n  script.onload = func;\n  script.src = scriptName+'.js';\n  if ($.browser.msie && $.browser.version<=8) {\n    // script.onload does not work with older versions of IE\n    script.onreadystatechange = function() {\n      if (script.readyState=='complete' || script.readyState=='loaded') {\n        func(); if (show) showRoot();\n      }\n    }\n  }\n  head.appendChild(script);\n}\n\nfunction createIndent(o,domNode,node,level)\n{\n  var level=-1;\n  var n = node;\n  while (n.parentNode) { level++; n=n.parentNode; }\n  if (node.childrenData) {\n    var imgNode = document.createElement(\"img\");\n    imgNode.style.paddingLeft=(16*level).toString()+'px';\n    imgNode.width  = 16;\n    imgNode.height = 22;\n    imgNode.border = 0;\n    node.plus_img = imgNode;\n    node.expandToggle = document.createElement(\"a\");\n    node.expandToggle.href = \"javascript:void(0)\";\n    node.expandToggle.onclick = function() {\n      if (node.expanded) {\n        $(node.getChildrenUL()).slideUp(\"fast\");\n        node.plus_img.src = node.relpath+\"ftv2pnode.png\";\n        node.expanded = false;\n      } else {\n        expandNode(o, node, false, false);\n      }\n    }\n    node.expandToggle.appendChild(imgNode);\n    domNode.appendChild(node.expandToggle);\n    imgNode.src = node.relpath+\"ftv2pnode.png\";\n  } else {\n    var span = document.createElement(\"span\");\n    span.style.display = 'inline-block';\n    span.style.width   = 16*(level+1)+'px';\n    span.style.height  = '22px';\n    span.innerHTML = '&#160;';\n    domNode.appendChild(span);\n  }\n}\n\nvar animationInProgress = false;\n\nfunction gotoAnchor(anchor,aname,updateLocation)\n{\n  var pos, docContent = $('#doc-content');\n  if (anchor.parent().attr('class')=='memItemLeft' ||\n      anchor.parent().attr('class')=='fieldtype' ||\n      anchor.parent().is(':header'))\n  {\n    pos = anchor.parent().position().top;\n  } else if (anchor.position()) {\n    pos = anchor.position().top;\n  }\n  if (pos) {\n    var dist = Math.abs(Math.min(\n               pos-docContent.offset().top,\n               docContent[0].scrollHeight-\n               docContent.height()-docContent.scrollTop()));\n    animationInProgress=true;\n    docContent.animate({\n      scrollTop: pos + docContent.scrollTop() - docContent.offset().top\n    },Math.max(50,Math.min(500,dist)),function(){\n      if (updateLocation) window.location.href=aname;\n      animationInProgress=false;\n    });\n  }\n}\n\nfunction newNode(o, po, text, link, childrenData, lastNode)\n{\n  var node = new Object();\n  node.children = Array();\n  node.childrenData = childrenData;\n  node.depth = po.depth + 1;\n  node.relpath = po.relpath;\n  node.isLast = lastNode;\n\n  node.li = document.createElement(\"li\");\n  po.getChildrenUL().appendChild(node.li);\n  node.parentNode = po;\n\n  node.itemDiv = document.createElement(\"div\");\n  node.itemDiv.className = \"item\";\n\n  node.labelSpan = document.createElement(\"span\");\n  node.labelSpan.className = \"label\";\n\n  createIndent(o,node.itemDiv,node,0);\n  node.itemDiv.appendChild(node.labelSpan);\n  node.li.appendChild(node.itemDiv);\n\n  var a = document.createElement(\"a\");\n  node.labelSpan.appendChild(a);\n  node.label = document.createTextNode(text);\n  node.expanded = false;\n  a.appendChild(node.label);\n  if (link) {\n    var url;\n    if (link.substring(0,1)=='^') {\n      url = link.substring(1);\n      link = url;\n    } else {\n      url = node.relpath+link;\n    }\n    a.className = stripPath(link.replace('#',':'));\n    if (link.indexOf('#')!=-1) {\n      var aname = '#'+link.split('#')[1];\n      var srcPage = stripPath($(location).attr('pathname'));\n      var targetPage = stripPath(link.split('#')[0]);\n      a.href = srcPage!=targetPage ? url : \"javascript:void(0)\";\n      a.onclick = function(){\n        storeLink(link);\n        if (!$(a).parent().parent().hasClass('selected'))\n        {\n          $('.item').removeClass('selected');\n          $('.item').removeAttr('id');\n          $(a).parent().parent().addClass('selected');\n          $(a).parent().parent().attr('id','selected');\n        }\n        var anchor = $(aname);\n        gotoAnchor(anchor,aname,true);\n      };\n    } else {\n      a.href = url;\n      a.onclick = function() { storeLink(link); }\n    }\n  } else {\n    if (childrenData != null)\n    {\n      a.className = \"nolink\";\n      a.href = \"javascript:void(0)\";\n      a.onclick = node.expandToggle.onclick;\n    }\n  }\n\n  node.childrenUL = null;\n  node.getChildrenUL = function() {\n    if (!node.childrenUL) {\n      node.childrenUL = document.createElement(\"ul\");\n      node.childrenUL.className = \"children_ul\";\n      node.childrenUL.style.display = \"none\";\n      node.li.appendChild(node.childrenUL);\n    }\n    return node.childrenUL;\n  };\n\n  return node;\n}\n\nfunction showRoot()\n{\n  var headerHeight = $(\"#top\").height();\n  var footerHeight = $(\"#nav-path\").height();\n  var windowHeight = $(window).height() - headerHeight - footerHeight;\n  (function (){ // retry until we can scroll to the selected item\n    try {\n      var navtree=$('#nav-tree');\n      navtree.scrollTo('#selected',0,{offset:-windowHeight/2});\n    } catch (err) {\n      setTimeout(arguments.callee, 0);\n    }\n  })();\n}\n\nfunction expandNode(o, node, imm, showRoot)\n{\n  if (node.childrenData && !node.expanded) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        expandNode(o, node, imm, showRoot);\n      }, showRoot);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      } if (imm || ($.browser.msie && $.browser.version>8)) {\n        // somehow slideDown jumps to the start of tree for IE9 :-(\n        $(node.getChildrenUL()).show();\n      } else {\n        $(node.getChildrenUL()).slideDown(\"fast\");\n      }\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n    }\n  }\n}\n\nfunction glowEffect(n,duration)\n{\n  n.addClass('glow').delay(duration).queue(function(next){\n    $(this).removeClass('glow');next();\n  });\n}\n\nfunction highlightAnchor()\n{\n  var aname = $(location).attr('hash');\n  var anchor = $(aname);\n  if (anchor.parent().attr('class')=='memItemLeft'){\n    var rows = $('.memberdecls tr[class$=\"'+\n               window.location.hash.substring(1)+'\"]');\n    glowEffect(rows.children(),300); // member without details\n  } else if (anchor.parents().slice(2).prop('tagName')=='TR') {\n    glowEffect(anchor.parents('div.memitem'),1000); // enum value\n  } else if (anchor.parent().attr('class')=='fieldtype'){\n    glowEffect(anchor.parent().parent(),1000); // struct field\n  } else if (anchor.parent().is(\":header\")) {\n    glowEffect(anchor.parent(),1000); // section header\n  } else {\n    glowEffect(anchor.next(),1000); // normal member\n  }\n  gotoAnchor(anchor,aname,false);\n}\n\nfunction selectAndHighlight(hash,n)\n{\n  var a;\n  if (hash) {\n    var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1);\n    a=$('.item a[class$=\"'+link+'\"]');\n  }\n  if (a && a.length) {\n    a.parent().parent().addClass('selected');\n    a.parent().parent().attr('id','selected');\n    highlightAnchor();\n  } else if (n) {\n    $(n.itemDiv).addClass('selected');\n    $(n.itemDiv).attr('id','selected');\n  }\n  if ($('#nav-tree-contents .item:first').hasClass('selected')) {\n    $('#nav-sync').css('top','30px');\n  } else {\n    $('#nav-sync').css('top','5px');\n  }\n  showRoot();\n}\n\nfunction showNode(o, node, index, hash)\n{\n  if (node && node.childrenData) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        showNode(o,node,index,hash);\n      },true);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      }\n      $(node.getChildrenUL()).css({'display':'block'});\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n      var n = node.children[o.breadcrumbs[index]];\n      if (index+1<o.breadcrumbs.length) {\n        showNode(o,n,index+1,hash);\n      } else {\n        if (typeof(n.childrenData)==='string') {\n          var varName = n.childrenData;\n          getScript(n.relpath+varName,function(){\n            n.childrenData = getData(varName);\n            node.expanded=false;\n            showNode(o,node,index,hash); // retry with child node expanded\n          },true);\n        } else {\n          var rootBase = stripPath(o.toroot.replace(/\\..+$/, ''));\n          if (rootBase==\"index\" || rootBase==\"pages\" || rootBase==\"search\") {\n            expandNode(o, n, true, true);\n          }\n          selectAndHighlight(hash,n);\n        }\n      }\n    }\n  } else {\n    selectAndHighlight(hash);\n  }\n}\n\nfunction removeToInsertLater(element) {\n  var parentNode = element.parentNode;\n  var nextSibling = element.nextSibling;\n  parentNode.removeChild(element);\n  return function() {\n    if (nextSibling) {\n      parentNode.insertBefore(element, nextSibling);\n    } else {\n      parentNode.appendChild(element);\n    }\n  };\n}\n\nfunction getNode(o, po)\n{\n  var insertFunction = removeToInsertLater(po.li);\n  po.childrenVisited = true;\n  var l = po.childrenData.length-1;\n  for (var i in po.childrenData) {\n    var nodeData = po.childrenData[i];\n    po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],\n      i==l);\n  }\n  insertFunction();\n}\n\nfunction gotoNode(o,subIndex,root,hash,relpath)\n{\n  var nti = navTreeSubIndices[subIndex][root+hash];\n  o.breadcrumbs = $.extend(true, [], nti ? nti : navTreeSubIndices[subIndex][root]);\n  if (!o.breadcrumbs && root!=NAVTREE[0][1]) { // fallback: show index\n    navTo(o,NAVTREE[0][1],\"\",relpath);\n    $('.item').removeClass('selected');\n    $('.item').removeAttr('id');\n  }\n  if (o.breadcrumbs) {\n    o.breadcrumbs.unshift(0); // add 0 for root node\n    showNode(o, o.node, 0, hash);\n  }\n}\n\nfunction navTo(o,root,hash,relpath)\n{\n  var link = cachedLink();\n  if (link) {\n    var parts = link.split('#');\n    root = parts[0];\n    if (parts.length>1) hash = '#'+parts[1];\n    else hash='';\n  }\n  if (hash.match(/^#l\\d+$/)) {\n    var anchor=$('a[name='+hash.substring(1)+']');\n    glowEffect(anchor.parent(),1000); // line number\n    hash=''; // strip line number anchors\n    //root=root.replace(/_source\\./,'.'); // source link to doc link\n  }\n  var url=root+hash;\n  var i=-1;\n  while (NAVTREEINDEX[i+1]<=url) i++;\n  if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index\n  if (navTreeSubIndices[i]) {\n    gotoNode(o,i,root,hash,relpath)\n  } else {\n    getScript(relpath+'navtreeindex'+i,function(){\n      navTreeSubIndices[i] = eval('NAVTREEINDEX'+i);\n      if (navTreeSubIndices[i]) {\n        gotoNode(o,i,root,hash,relpath);\n      }\n    },true);\n  }\n}\n\nfunction showSyncOff(n,relpath)\n{\n    n.html('<img src=\"'+relpath+'sync_off.png\" title=\"'+SYNCOFFMSG+'\"/>');\n}\n\nfunction showSyncOn(n,relpath)\n{\n    n.html('<img src=\"'+relpath+'sync_on.png\" title=\"'+SYNCONMSG+'\"/>');\n}\n\nfunction toggleSyncButton(relpath)\n{\n  var navSync = $('#nav-sync');\n  if (navSync.hasClass('sync')) {\n    navSync.removeClass('sync');\n    showSyncOff(navSync,relpath);\n    storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash'));\n  } else {\n    navSync.addClass('sync');\n    showSyncOn(navSync,relpath);\n    deleteLink();\n  }\n}\n\nfunction initNavTree(toroot,relpath)\n{\n  var o = new Object();\n  o.toroot = toroot;\n  o.node = new Object();\n  o.node.li = document.getElementById(\"nav-tree-contents\");\n  o.node.childrenData = NAVTREE;\n  o.node.children = new Array();\n  o.node.childrenUL = document.createElement(\"ul\");\n  o.node.getChildrenUL = function() { return o.node.childrenUL; };\n  o.node.li.appendChild(o.node.childrenUL);\n  o.node.depth = 0;\n  o.node.relpath = relpath;\n  o.node.expanded = false;\n  o.node.isLast = true;\n  o.node.plus_img = document.createElement(\"img\");\n  o.node.plus_img.src = relpath+\"ftv2pnode.png\";\n  o.node.plus_img.width = 16;\n  o.node.plus_img.height = 22;\n\n  if (localStorageSupported()) {\n    var navSync = $('#nav-sync');\n    if (cachedLink()) {\n      showSyncOff(navSync,relpath);\n      navSync.removeClass('sync');\n    } else {\n      showSyncOn(navSync,relpath);\n    }\n    navSync.click(function(){ toggleSyncButton(relpath); });\n  }\n\n  $(window).load(function(){\n    navTo(o,toroot,window.location.hash,relpath);\n    showRoot();\n  });\n\n  $(window).bind('hashchange', function(){\n     if (window.location.hash && window.location.hash.length>1){\n       var a;\n       if ($(location).attr('hash')){\n         var clslink=stripPath($(location).attr('pathname'))+':'+\n                               $(location).attr('hash').substring(1);\n         a=$('.item a[class$=\"'+clslink+'\"]');\n       }\n       if (a==null || !$(a).parent().parent().hasClass('selected')){\n         $('.item').removeClass('selected');\n         $('.item').removeAttr('id');\n       }\n       var link=stripPath2($(location).attr('pathname'));\n       navTo(o,link,$(location).attr('hash'),relpath);\n     } else if (!animationInProgress) {\n       $('#doc-content').scrollTop(0);\n       $('.item').removeClass('selected');\n       $('.item').removeAttr('id');\n       navTo(o,toroot,window.location.hash,relpath);\n     }\n  })\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/navtreeindex0.js",
    "content": "var NAVTREEINDEX0 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  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/tabs.css",
    "content": ".tabs, .tabs1, .tabs2, .tabs3 {\n    background-image: url('tab_b.png');\n    width: 100%;\n    z-index: 101;\n    font-size: 10px;\n}\n\n.tabs1 {\n    background-image: url('tab_topnav.png');\n    font-size: 12px;\n}\n\n.tabs2 {\n    font-size: 10px;\n}\n.tabs3 {\n    font-size: 9px;\n}\n\n.tablist {\n    margin: 0;\n    padding: 0;\n    display: table;\n    line-height: 24px;\n}\n\n.tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_b.png');\n    list-style: none;\n}\n\n.tabs1 .tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_topnav.png');\n    list-style: none;\n}\n\n.tablist a {\n    display: block;\n    padding: 0 20px;\n    font-weight: bold;\n    background-image:url('tab_s.png');\n    background-repeat:no-repeat;\n    background-position:right;\n    color: #283A5D;\n    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n    text-decoration: none;\n    outline: none;\n}\n\n.tabs3 .tablist a {\n    padding: 0 10px;\n}\n\n.tablist a:hover {\n    background-image: url('tab_h.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n    text-decoration: none;\n}\n\n.tablist li.current a {\n    background-image: url('tab_a.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/todo.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/todo.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/todo.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/unionarm__nn__long__long.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/unionarm__nn__long__long.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/unionarm__nn__long__long.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/unionarm__nn__long__long.js",
    "content": "var unionarm__nn__long__long =\n[\n    [ \"long_long\", \"unionarm__nn__long__long.html#a4dbadc95589c36dcfdb4ec2f21bd2a72\", null ],\n    [ \"word\", \"unionarm__nn__long__long.html#a911c83d212457726d888e0c845a01155\", null ]\n];"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/unionarm__nnword.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding CMSIS-NN page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://arm-software.github.io/CMSIS-NN/v4.0.0/unionarm__nnword.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0/unionarm__nnword.html\">here</a> or try to find corresponding topic described in <a href=\"https://arm-software.github.io/CMSIS-NN/v4.0.0\">CMSIS-NN resources</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/NN/html/unionarm__nnword.js",
    "content": "var unionarm__nnword =\n[\n    [ \"bytes\", \"unionarm__nnword.html#ac7cff6480a8e29d95f29b73cb1267249\", null ],\n    [ \"half_words\", \"unionarm__nnword.html#a9b5e49e4e2c4b7203e07b305386bb2ba\", null ],\n    [ \"word\", \"unionarm__nnword.html#a35c7b2ae25e35e0ddcd9ec0a1a6f8d18\", null ]\n];"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/algorithmFunc.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/algorithmFunc.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/algorithmFunc.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/bash_script.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/bash_script.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/bash_script.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/cmsis.css",
    "content": "/* The standard CSS for doxygen */\n\nbody, table, div, p, dl {\n\tfont-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\n\tfont-size: 13px;\n\tline-height: 1.3;\n}\n\n/* CMSIS styles */\n\n.style1 {\n\t\ttext-align: center;\n}\n.style2 {\n\t\tcolor: #0000FF;\n\t\tfont-weight: normal;\n}\n.style3 {\n\t\ttext-align: left;\n}\n.style4 {\n\t\tcolor: #008000;\n}\n.style5 {\n\t\tcolor: #0000FF;\n}\n.style6 {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n.mand {\n\t\tcolor: #0000FF;\n}\n.opt {\n\t\tcolor: #008000;\n}\n.cond {\n\t\tcolor: #990000;\n}\n\n.choice \n{\n\tbackground-color:#F7F9D0;\n}\n.seq \n{\n\tbackground-color:#C9DECB;\n}\n.group1\n{\n\tbackground-color:#F8F1F1;\n}\n.group2\n{\n\tbackground-color:#DCEDEA;\n}\n\n\nul ul {\n\t\tlist-style-type: disc;\n}\n\nul ul ul {\n\t\tlist-style-type: disc;\n}\n\nul.hierarchy {\n\t\tcolor: green;\n}\n\nem {\n\t\tcolor: #000000;\n\t\tfont-style:italic;\n}\n\n\n\n/*  CMSIS Tables */\ntable.cmtab1 {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: justify;\n\twidth:70%;\n}\n\nth.cmtab1 {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n\theight: 28px;\n}\n\ntd.cmtab1 {\n\tpadding:1px;\n\ttext-align: left;\n}\n\ntable.cmtable {\n\tborder-collapse:collapse;\n\ttext-align: justify;\n}\n\ntable.cmtable td, table.cmtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.cmtable th {\n\tbackground-color: #EBEFF6;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n\ttext-align:left;\n}\n\ntd.MonoTxt {\n\tfont-family:\"Arial monospaced for SAP\";\n}\n\ntd.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.XML-Token \n{\n\tazimuth: 180;\n\tfont-style:italic;\n\tcolor:Maroon;\n\tz-index:20;\n\t\n}\n\nspan.h2 \n{\n\tfont-size: 120%;\n\tfont-weight: bold;\n}\n\ndiv.new\n{\n\tbackground-color:#ccffcc; /* light green */\n}\n\ndiv.mod\n{\n\tbackground-color:#ffe6cc;  /* light amber */\n}\n\ndiv.del\n{\n\tbackground-color:#ffcccc;  /* light red */\n}\n\n/* @group Heading Levels */\n\nh1 {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2 {\n\tfont-size: 120%;\n}\n\nh3 {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd, p.starttd {\n\tmargin-top: 2px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3A568E;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4464A5;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9AAED5;\n\tcolor: #ffffff;\n\tborder: 1px double #849CCC;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px;\n        margin: 4px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C3CFE6;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n}\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C3CFE6;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C3CFE6;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EDF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9AAED5;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A2B4D8;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4769AD;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memItemLeft, .memItemRight, .memTemplParams {\n\tborder-top: 1px solid #C3CFE6;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4464A5;\n        white-space: nowrap;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4464A5;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A2B4D8;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A7B8DA;\n        border-left: 1px solid #A7B8DA;\n        border-right: 1px solid #A7B8DA;\n        padding: 6px 0px 6px 0px;\n        color: #233456;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A7B8DA;      \n        border-left: 1px solid #A7B8DA;      \n        border-right: 1px solid #A7B8DA; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #708CC4;\n        border-top:1px solid #5072B7;\n        border-left:1px solid #5072B7;\n        border-right:1px solid #C3CFE6;\n        border-bottom:1px solid #C3CFE6;\n\ttext-shadow: none;\n        color: white;\n        margin-right: 4px;\n        padding: 2px 3px;\n        border-radius: 3px;\n        font-size: 7pt;\n\twhite-space: nowrap;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3A568E;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #293C63;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2B4069;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #EBEFF6;\n\tcolor: #000000;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        width: 100%;\n        margin-bottom: 10px;\n        border: 1px solid #A7B8DA;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A7B8DA;\n        border-bottom: 1px solid #A7B8DA;\n        vertical-align: top;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A7B8DA;\n        width: 100%;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E7F3;\n        font-size: 90%;\n        color: #233456;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A7B8DA;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#889FCE;\n\tborder:solid 1px #C1CDE5;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#344D7E;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6583BF;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#344D7E;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tmargin-left: 5px;\n\tfont-size: 8pt;\n\tpadding-left: 5px;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C3CFE6;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 7px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5072B7;\n}\n\n.image\n{\n        text-align: left;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #8EA4D0;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#314877;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D7DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4464A5;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/cmsis_footer.js",
    "content": "function writeFooter()  {\n    document.write('Generated on Wed Apr 13 2022 14:13:49 for CMSIS-Pack Version 1.7.2 by Arm Ltd. All rights reserved.');\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/configWizard.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/configWizard.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/configWizard.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/coresight_setup.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/coresight_setup.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/coresight_setup.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/cp_Editors.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/cp_Editors.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/cp_Editors.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/cp_PackTutorial.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/cp_PackTutorial.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/cp_PackTutorial.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/cp_Packs.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/cp_Packs.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/cp_Packs.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/cp_ZIPTool.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/cp_ZIPTool.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/cp_ZIPTool.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/createPackPublish.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/createPackPublish.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/createPackPublish.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/createPackUtil.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/createPackUtil.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/createPackUtil.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/dbg_debug_sqns.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_debug_sqns.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_debug_sqns.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/dbg_setup_access.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_setup_access.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_setup_access.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/dbg_setup_tutorial.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_setup_tutorial.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_setup_tutorial.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/dbg_sqns_ds.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_sqns_ds.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_sqns_ds.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/dbg_sqns_ide.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_sqns_ide.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_sqns_ide.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/dbg_sqns_uvision.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_sqns_uvision.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/dbg_sqns_uvision.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/debug_description.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/debug_description.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/debug_description.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/doxygen.css",
    "content": "/* The standard CSS for doxygen 1.8.6 */\n\nbody, table, div, p, dl {\n\tfont: 400 14px/22px Roboto,sans-serif;\n}\n\n/* @group Heading Levels */\n\nh1.groupheader {\n\tfont-size: 150%;\n}\n\n.title {\n\tfont: 400 14px/28px Roboto,sans-serif;\n\tfont-size: 150%;\n\tfont-weight: bold;\n\tmargin: 10px 2px;\n}\n\nh2.groupheader {\n\tborder-bottom: 1px solid #879ECB;\n\tcolor: #354C7B;\n\tfont-size: 150%;\n\tfont-weight: normal;\n\tmargin-top: 1.75em;\n\tpadding-top: 8px;\n\tpadding-bottom: 4px;\n\twidth: 100%;\n}\n\nh3.groupheader {\n\tfont-size: 100%;\n}\n\nh1, h2, h3, h4, h5, h6 {\n\t-webkit-transition: text-shadow 0.5s linear;\n\t-moz-transition: text-shadow 0.5s linear;\n\t-ms-transition: text-shadow 0.5s linear;\n\t-o-transition: text-shadow 0.5s linear;\n\ttransition: text-shadow 0.5s linear;\n\tmargin-right: 15px;\n}\n\nh1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {\n\ttext-shadow: 0 0 15px cyan;\n}\n\ndt {\n\tfont-weight: bold;\n}\n\ndiv.multicol {\n\t-moz-column-gap: 1em;\n\t-webkit-column-gap: 1em;\n\t-moz-column-count: 3;\n\t-webkit-column-count: 3;\n}\n\np.startli, p.startdd {\n\tmargin-top: 2px;\n}\n\np.starttd {\n\tmargin-top: 0px;\n}\n\np.endli {\n\tmargin-bottom: 0px;\n}\n\np.enddd {\n\tmargin-bottom: 4px;\n}\n\np.endtd {\n\tmargin-bottom: 2px;\n}\n\n/* @end */\n\ncaption {\n\tfont-weight: bold;\n}\n\nspan.legend {\n        font-size: 70%;\n        text-align: center;\n}\n\nh3.version {\n        font-size: 90%;\n        text-align: center;\n}\n\ndiv.qindex, div.navtab{\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: center;\n}\n\ndiv.qindex, div.navpath {\n\twidth: 100%;\n\tline-height: 140%;\n}\n\ndiv.navtab {\n\tmargin-right: 15px;\n}\n\n/* @group Link Styling */\n\na {\n\tcolor: #3D578C;\n\tfont-weight: normal;\n\ttext-decoration: none;\n}\n\n.contents a:visited {\n\tcolor: #4665A2;\n}\n\na:hover {\n\ttext-decoration: underline;\n}\n\na.qindex {\n\tfont-weight: bold;\n}\n\na.qindexHL {\n\tfont-weight: bold;\n\tbackground-color: #9CAFD4;\n\tcolor: #ffffff;\n\tborder: 1px double #869DCA;\n}\n\n.contents a.qindexHL:visited {\n        color: #ffffff;\n}\n\na.el {\n\tfont-weight: bold;\n}\n\na.elRef {\n}\n\na.code, a.code:visited, a.line, a.line:visited {\n\tcolor: #4665A2; \n}\n\na.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited {\n\tcolor: #4665A2; \n}\n\n/* @end */\n\ndl.el {\n\tmargin-left: -1cm;\n}\n\npre.fragment {\n        border: 1px solid #C4CFE5;\n        background-color: #FBFCFD;\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n        overflow: auto;\n        word-wrap: break-word;\n        font-size:  9pt;\n        line-height: 125%;\n        font-family: monospace, fixed;\n        font-size: 105%;\n}\n\ndiv.fragment {\n        padding: 4px 6px;\n        margin: 4px 8px 4px 2px;\n\tbackground-color: #FBFCFD;\n\tborder: 1px solid #C4CFE5;\n}\n\ndiv.line {\n\tfont-family: monospace, fixed;\n        font-size: 13px;\n\tmin-height: 13px;\n\tline-height: 1.0;\n\ttext-wrap: unrestricted;\n\twhite-space: -moz-pre-wrap; /* Moz */\n\twhite-space: -pre-wrap;     /* Opera 4-6 */\n\twhite-space: -o-pre-wrap;   /* Opera 7 */\n\twhite-space: pre-wrap;      /* CSS3  */\n\tword-wrap: break-word;      /* IE 5.5+ */\n\ttext-indent: -53px;\n\tpadding-left: 53px;\n\tpadding-bottom: 0px;\n\tmargin: 0px;\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\ndiv.line.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 10px cyan;\n}\n\n\nspan.lineno {\n\tpadding-right: 4px;\n\ttext-align: right;\n\tborder-right: 2px solid #0F0;\n\tbackground-color: #E8E8E8;\n        white-space: pre;\n}\nspan.lineno a {\n\tbackground-color: #D8D8D8;\n}\n\nspan.lineno a:hover {\n\tbackground-color: #C8C8C8;\n}\n\ndiv.ah {\n\tbackground-color: black;\n\tfont-weight: bold;\n\tcolor: #ffffff;\n\tmargin-bottom: 3px;\n\tmargin-top: 3px;\n\tpadding: 0.2em;\n\tborder: solid thin #333;\n\tborder-radius: 0.5em;\n\t-webkit-border-radius: .5em;\n\t-moz-border-radius: .5em;\n\tbox-shadow: 2px 2px 3px #999;\n\t-webkit-box-shadow: 2px 2px 3px #999;\n\t-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n\tbackground-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));\n\tbackground-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);\n}\n\ndiv.groupHeader {\n\tmargin-left: 16px;\n\tmargin-top: 12px;\n\tfont-weight: bold;\n}\n\ndiv.groupText {\n\tmargin-left: 16px;\n\tfont-style: italic;\n}\n\nbody {\n\tbackground-color: white;\n\tcolor: black;\n        margin: 0;\n}\n\ndiv.contents {\n\tmargin-top: 10px;\n\tmargin-left: 12px;\n\tmargin-right: 8px;\n}\n\ntd.indexkey {\n\tbackground-color: #EBEFF6;\n\tfont-weight: bold;\n\tborder: 1px solid #C4CFE5;\n\tmargin: 2px 0px 2px 0;\n\tpadding: 2px 10px;\n        white-space: nowrap;\n        vertical-align: top;\n}\n\ntd.indexvalue {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #C4CFE5;\n\tpadding: 2px 10px;\n\tmargin: 2px 0px;\n}\n\ntr.memlist {\n\tbackground-color: #EEF1F7;\n}\n\np.formulaDsp {\n\ttext-align: center;\n}\n\nimg.formulaDsp {\n\t\n}\n\nimg.formulaInl {\n\tvertical-align: middle;\n}\n\ndiv.center {\n\ttext-align: center;\n        margin-top: 0px;\n        margin-bottom: 0px;\n        padding: 0px;\n}\n\ndiv.center img {\n\tborder: 0px;\n}\n\naddress.footer {\n\ttext-align: right;\n\tpadding-right: 12px;\n}\n\nimg.footer {\n\tborder: 0px;\n\tvertical-align: middle;\n}\n\n/* @group Code Colorization */\n\nspan.keyword {\n\tcolor: #008000\n}\n\nspan.keywordtype {\n\tcolor: #604020\n}\n\nspan.keywordflow {\n\tcolor: #e08000\n}\n\nspan.comment {\n\tcolor: #800000\n}\n\nspan.preprocessor {\n\tcolor: #806020\n}\n\nspan.stringliteral {\n\tcolor: #002080\n}\n\nspan.charliteral {\n\tcolor: #008080\n}\n\nspan.vhdldigit { \n\tcolor: #ff00ff \n}\n\nspan.vhdlchar { \n\tcolor: #000000 \n}\n\nspan.vhdlkeyword { \n\tcolor: #700070 \n}\n\nspan.vhdllogic { \n\tcolor: #ff0000 \n}\n\nblockquote {\n        background-color: #F7F8FB;\n        border-left: 2px solid #9CAFD4;\n        margin: 0 24px 0 4px;\n        padding: 0 12px 0 16px;\n}\n\n/* @end */\n\n/*\n.search {\n\tcolor: #003399;\n\tfont-weight: bold;\n}\n\nform.search {\n\tmargin-bottom: 0px;\n\tmargin-top: 0px;\n}\n\ninput.search {\n\tfont-size: 75%;\n\tcolor: #000080;\n\tfont-weight: normal;\n\tbackground-color: #e8eef2;\n}\n*/\n\ntd.tiny {\n\tfont-size: 75%;\n}\n\n.dirtab {\n\tpadding: 4px;\n\tborder-collapse: collapse;\n\tborder: 1px solid #A3B4D7;\n}\n\nth.dirtab {\n\tbackground: #EBEFF6;\n\tfont-weight: bold;\n}\n\nhr {\n\theight: 0px;\n\tborder: none;\n\tborder-top: 1px solid #4A6AAA;\n}\n\nhr.footer {\n\theight: 1px;\n}\n\n/* @group Member Descriptions */\n\ntable.memberdecls {\n\tborder-spacing: 0px;\n\tpadding: 0px;\n}\n\n.memberdecls td, .fieldtable tr {\n\t-webkit-transition-property: background-color, box-shadow;\n\t-webkit-transition-duration: 0.5s;\n\t-moz-transition-property: background-color, box-shadow;\n\t-moz-transition-duration: 0.5s;\n\t-ms-transition-property: background-color, box-shadow;\n\t-ms-transition-duration: 0.5s;\n\t-o-transition-property: background-color, box-shadow;\n\t-o-transition-duration: 0.5s;\n\ttransition-property: background-color, box-shadow;\n\ttransition-duration: 0.5s;\n}\n\n.memberdecls td.glow, .fieldtable tr.glow {\n\tbackground-color: cyan;\n\tbox-shadow: 0 0 15px cyan;\n}\n\n.mdescLeft, .mdescRight,\n.memItemLeft, .memItemRight,\n.memTemplItemLeft, .memTemplItemRight, .memTemplParams {\n\tbackground-color: #F9FAFC;\n\tborder: none;\n\tmargin: 4px;\n\tpadding: 1px 0 0 8px;\n}\n\n.mdescLeft, .mdescRight {\n\tpadding: 0px 8px 4px 8px;\n\tcolor: #555;\n}\n\n.memSeparator {\n        border-bottom: 1px solid #DEE4F0;\n        line-height: 1px;\n        margin: 0px;\n        padding: 0px;\n}\n\n.memItemLeft, .memTemplItemLeft {\n        white-space: nowrap;\n}\n\n.memItemRight {\n\twidth: 100%;\n}\n\n.memTemplParams {\n\tcolor: #4665A2;\n        white-space: nowrap;\n\tfont-size: 80%;\n}\n\n/* @end */\n\n/* @group Member Details */\n\n/* Styles for detailed member documentation */\n\n.memtemplate {\n\tfont-size: 80%;\n\tcolor: #4665A2;\n\tfont-weight: normal;\n\tmargin-left: 9px;\n}\n\n.memnav {\n\tbackground-color: #EBEFF6;\n\tborder: 1px solid #A3B4D7;\n\ttext-align: center;\n\tmargin: 2px;\n\tmargin-right: 15px;\n\tpadding: 2px;\n}\n\n.mempage {\n\twidth: 100%;\n}\n\n.memitem {\n\tpadding: 0;\n\tmargin-bottom: 10px;\n\tmargin-right: 5px;\n        -webkit-transition: box-shadow 0.5s linear;\n        -moz-transition: box-shadow 0.5s linear;\n        -ms-transition: box-shadow 0.5s linear;\n        -o-transition: box-shadow 0.5s linear;\n        transition: box-shadow 0.5s linear;\n        display: table !important;\n        width: 100%;\n}\n\n.memitem.glow {\n         box-shadow: 0 0 15px cyan;\n}\n\n.memname {\n        font-weight: bold;\n        margin-left: 6px;\n}\n\n.memname td {\n\tvertical-align: bottom;\n}\n\n.memproto, dl.reflist dt {\n        border-top: 1px solid #A8B8D9;\n        border-left: 1px solid #A8B8D9;\n        border-right: 1px solid #A8B8D9;\n        padding: 6px 0px 6px 0px;\n        color: #253555;\n        font-weight: bold;\n        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E8F2;\n        /* opera specific markup */\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        /* firefox specific markup */\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        -moz-border-radius-topright: 4px;\n        -moz-border-radius-topleft: 4px;\n        /* webkit specific markup */\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        -webkit-border-top-right-radius: 4px;\n        -webkit-border-top-left-radius: 4px;\n\n}\n\n.memdoc, dl.reflist dd {\n        border-bottom: 1px solid #A8B8D9;      \n        border-left: 1px solid #A8B8D9;      \n        border-right: 1px solid #A8B8D9; \n        padding: 6px 10px 2px 10px;\n        background-color: #FBFCFD;\n        border-top-width: 0;\n        background-image:url('nav_g.png');\n        background-repeat:repeat-x;\n        background-color: #FFFFFF;\n        /* opera specific markup */\n        border-bottom-left-radius: 4px;\n        border-bottom-right-radius: 4px;\n        box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n        /* firefox specific markup */\n        -moz-border-radius-bottomleft: 4px;\n        -moz-border-radius-bottomright: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;\n        /* webkit specific markup */\n        -webkit-border-bottom-left-radius: 4px;\n        -webkit-border-bottom-right-radius: 4px;\n        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\ndl.reflist dt {\n        padding: 5px;\n}\n\ndl.reflist dd {\n        margin: 0px 0px 10px 0px;\n        padding: 5px;\n}\n\n.paramkey {\n\ttext-align: right;\n}\n\n.paramtype {\n\twhite-space: nowrap;\n}\n\n.paramname {\n\tcolor: #602020;\n\twhite-space: nowrap;\n}\n.paramname em {\n\tfont-style: normal;\n}\n.paramname code {\n        line-height: 14px;\n}\n\n.params, .retval, .exception, .tparams {\n        margin-left: 0px;\n        padding-left: 0px;\n}       \n\n.params .paramname, .retval .paramname {\n        font-weight: bold;\n        vertical-align: top;\n}\n        \n.params .paramtype {\n        font-style: italic;\n        vertical-align: top;\n}       \n        \n.params .paramdir {\n        font-family: \"courier new\",courier,monospace;\n        vertical-align: top;\n}\n\ntable.mlabels {\n\tborder-spacing: 0px;\n}\n\ntd.mlabels-left {\n\twidth: 100%;\n\tpadding: 0px;\n}\n\ntd.mlabels-right {\n\tvertical-align: bottom;\n\tpadding: 0px;\n\twhite-space: nowrap;\n}\n\nspan.mlabels {\n        margin-left: 8px;\n}\n\nspan.mlabel {\n        background-color: #728DC1;\n        border-top:1px solid #5373B4;\n        border-left:1px solid #5373B4;\n        border-right:1px solid #C4CFE5;\n        border-bottom:1px solid #C4CFE5;\n\ttext-shadow: none;\n\tcolor: white;\n\tmargin-right: 4px;\n\tpadding: 2px 3px;\n\tborder-radius: 3px;\n\tfont-size: 7pt;\n\twhite-space: nowrap;\n\tvertical-align: middle;\n}\n\n\n\n/* @end */\n\n/* these are for tree view when not used as main index */\n\ndiv.directory {\n        margin: 10px 0px;\n        border-top: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        width: 100%;\n}\n\n.directory table {\n        border-collapse:collapse;\n}\n\n.directory td {\n        margin: 0px;\n        padding: 0px;\n\tvertical-align: top;\n}\n\n.directory td.entry {\n        white-space: nowrap;\n        padding-right: 6px;\n\tpadding-top: 3px;\n}\n\n.directory td.entry a {\n        outline:none;\n}\n\n.directory td.entry a img {\n        border: none;\n}\n\n.directory td.desc {\n        width: 100%;\n        padding-left: 6px;\n\tpadding-right: 6px;\n\tpadding-top: 3px;\n\tborder-left: 1px solid rgba(0,0,0,0.05);\n}\n\n.directory tr.even {\n\tpadding-left: 6px;\n\tbackground-color: #F7F8FB;\n}\n\n.directory img {\n\tvertical-align: -30%;\n}\n\n.directory .levels {\n        white-space: nowrap;\n        width: 100%;\n        text-align: right;\n        font-size: 9pt;\n}\n\n.directory .levels span {\n        cursor: pointer;\n        padding-left: 2px;\n        padding-right: 2px;\n\tcolor: #3D578C;\n}\n\ndiv.dynheader {\n        margin-top: 8px;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\naddress {\n\tfont-style: normal;\n\tcolor: #2A3D61;\n}\n\ntable.doxtable {\n\tborder-collapse:collapse;\n        margin-top: 4px;\n        margin-bottom: 4px;\n}\n\ntable.doxtable td, table.doxtable th {\n\tborder: 1px solid #2D4068;\n\tpadding: 3px 7px 2px;\n}\n\ntable.doxtable th {\n\tbackground-color: #374F7F;\n\tcolor: #FFFFFF;\n\tfont-size: 110%;\n\tpadding-bottom: 4px;\n\tpadding-top: 5px;\n}\n\ntable.fieldtable {\n        /*width: 100%;*/\n        margin-bottom: 10px;\n        border: 1px solid #A8B8D9;\n        border-spacing: 0px;\n        -moz-border-radius: 4px;\n        -webkit-border-radius: 4px;\n        border-radius: 4px;\n        -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;\n        -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n        box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15);\n}\n\n.fieldtable td, .fieldtable th {\n        padding: 3px 7px 2px;\n}\n\n.fieldtable td.fieldtype, .fieldtable td.fieldname {\n        white-space: nowrap;\n        border-right: 1px solid #A8B8D9;\n        border-bottom: 1px solid #A8B8D9;\n        vertical-align: top;\n}\n\n.fieldtable td.fieldname {\n        padding-top: 3px;\n}\n\n.fieldtable td.fielddoc {\n        border-bottom: 1px solid #A8B8D9;\n        /*width: 100%;*/\n}\n\n.fieldtable td.fielddoc p:first-child {\n        margin-top: 0px;\n}       \n        \n.fieldtable td.fielddoc p:last-child {\n        margin-bottom: 2px;\n}\n\n.fieldtable tr:last-child td {\n        border-bottom: none;\n}\n\n.fieldtable th {\n        background-image:url('nav_f.png');\n        background-repeat:repeat-x;\n        background-color: #E2E8F2;\n        font-size: 90%;\n        color: #253555;\n        padding-bottom: 4px;\n        padding-top: 5px;\n        text-align:left;\n        -moz-border-radius-topleft: 4px;\n        -moz-border-radius-topright: 4px;\n        -webkit-border-top-left-radius: 4px;\n        -webkit-border-top-right-radius: 4px;\n        border-top-left-radius: 4px;\n        border-top-right-radius: 4px;\n        border-bottom: 1px solid #A8B8D9;\n}\n\n\n.tabsearch {\n\ttop: 0px;\n\tleft: 10px;\n\theight: 36px;\n\tbackground-image: url('tab_b.png');\n\tz-index: 101;\n\toverflow: hidden;\n\tfont-size: 13px;\n}\n\n.navpath ul\n{\n\tfont-size: 11px;\n\tbackground-image:url('tab_b.png');\n\tbackground-repeat:repeat-x;\n\tbackground-position: 0 -5px;\n\theight:30px;\n\tline-height:30px;\n\tcolor:#8AA0CC;\n\tborder:solid 1px #C2CDE4;\n\toverflow:hidden;\n\tmargin:0px;\n\tpadding:0px;\n}\n\n.navpath li\n{\n\tlist-style-type:none;\n\tfloat:left;\n\tpadding-left:10px;\n\tpadding-right:15px;\n\tbackground-image:url('bc_s.png');\n\tbackground-repeat:no-repeat;\n\tbackground-position:right;\n\tcolor:#364D7C;\n}\n\n.navpath li.navelem a\n{\n\theight:32px;\n\tdisplay:block;\n\ttext-decoration: none;\n\toutline: none;\n\tcolor: #283A5D;\n\tfont-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;\n\ttext-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n\ttext-decoration: none;        \n}\n\n.navpath li.navelem a:hover\n{\n\tcolor:#6884BD;\n}\n\n.navpath li.footer\n{\n        list-style-type:none;\n        float:right;\n        padding-left:10px;\n        padding-right:15px;\n        background-image:none;\n        background-repeat:no-repeat;\n        background-position:right;\n        color:#364D7C;\n        font-size: 8pt;\n}\n\n\ndiv.summary\n{\n\tfloat: right;\n\tfont-size: 8pt;\n\tpadding-right: 5px;\n\twidth: 50%;\n\ttext-align: right;\n}       \n\ndiv.summary a\n{\n\twhite-space: nowrap;\n}\n\ndiv.ingroups\n{\n\tfont-size: 8pt;\n\twidth: 50%;\n\ttext-align: left;\n}\n\ndiv.ingroups a\n{\n\twhite-space: nowrap;\n}\n\ndiv.header\n{\n        background-image:url('nav_h.png');\n        background-repeat:repeat-x;\n\tbackground-color: #F9FAFC;\n\tmargin:  0px;\n\tborder-bottom: 1px solid #C4CFE5;\n}\n\ndiv.headertitle\n{\n\tpadding: 5px 5px 5px 10px;\n}\n\ndl\n{\n        padding: 0 0 0 10px;\n}\n\n/* dl.note, dl.warning, dl.attention, dl.pre, dl.post, dl.invariant, dl.deprecated, dl.todo, dl.test, dl.bug */\ndl.section\n{\n\tmargin-left: 0px;\n\tpadding-left: 0px;\n}\n\ndl.note\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #D0C000;\n}\n\ndl.warning, dl.attention\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #FF0000;\n}\n\ndl.pre, dl.post, dl.invariant\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00D000;\n}\n\ndl.deprecated\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #505050;\n}\n\ndl.todo\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #00C0E0;\n}\n\ndl.test\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #3030E0;\n}\n\ndl.bug\n{\n        margin-left:-7px;\n        padding-left: 3px;\n        border-left:4px solid;\n        border-color: #C08050;\n}\n\ndl.section dd {\n\tmargin-bottom: 6px;\n}\n\n\n#projectlogo\n{\n\ttext-align: center;\n\tvertical-align: bottom;\n\tborder-collapse: separate;\n}\n \n#projectlogo img\n{ \n\tborder: 0px none;\n}\n \n#projectname\n{\n\tfont: 300% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 2px 0px;\n}\n    \n#projectbrief\n{\n\tfont: 120% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#projectnumber\n{\n\tfont: 50% Tahoma, Arial,sans-serif;\n\tmargin: 0px;\n\tpadding: 0px;\n}\n\n#titlearea\n{\n\tpadding: 0px;\n\tmargin: 0px;\n\twidth: 100%;\n\tborder-bottom: 1px solid #5373B4;\n}\n\n.image\n{\n        text-align: center;\n}\n\n.dotgraph\n{\n        text-align: center;\n}\n\n.mscgraph\n{\n        text-align: center;\n}\n\n.diagraph\n{\n        text-align: center;\n}\n\n.caption\n{\n\tfont-weight: bold;\n}\n\ndiv.zoom\n{\n\tborder: 1px solid #90A5CE;\n}\n\ndl.citelist {\n        margin-bottom:50px;\n}\n\ndl.citelist dt {\n        color:#334975;\n        float:left;\n        font-weight:bold;\n        margin-right:10px;\n        padding:5px;\n}\n\ndl.citelist dd {\n        margin:2px 0;\n        padding:5px 0;\n}\n\ndiv.toc {\n        padding: 14px 25px;\n        background-color: #F4F6FA;\n        border: 1px solid #D8DFEE;\n        border-radius: 7px 7px 7px 7px;\n        float: right;\n        height: auto;\n        margin: 0 20px 10px 10px;\n        width: 200px;\n}\n\ndiv.toc li {\n        background: url(\"bdwn.png\") no-repeat scroll 0 5px transparent;\n        font: 10px/1.2 Verdana,DejaVu Sans,Geneva,sans-serif;\n        margin-top: 5px;\n        padding-left: 10px;\n        padding-top: 2px;\n}\n\ndiv.toc h3 {\n        font: bold 12px/1.2 Arial,FreeSans,sans-serif;\n\tcolor: #4665A2;\n        border-bottom: 0 none;\n        margin: 0;\n}\n\ndiv.toc ul {\n        list-style: none outside none;\n        border: medium none;\n        padding: 0px;\n}       \n\ndiv.toc li.level1 {\n        margin-left: 0px;\n}\n\ndiv.toc li.level2 {\n        margin-left: 15px;\n}\n\ndiv.toc li.level3 {\n        margin-left: 30px;\n}\n\ndiv.toc li.level4 {\n        margin-left: 45px;\n}\n\n.inherit_header {\n        font-weight: bold;\n        color: gray;\n        cursor: pointer;\n\t-webkit-touch-callout: none;\n\t-webkit-user-select: none;\n\t-khtml-user-select: none;\n\t-moz-user-select: none;\n\t-ms-user-select: none;\n\tuser-select: none;\n}\n\n.inherit_header td {\n        padding: 6px 0px 2px 5px;\n}\n\n.inherit {\n        display: none;\n}\n\ntr.heading h2 {\n        margin-top: 12px;\n        margin-bottom: 4px;\n}\n\n/* tooltip related style info */\n\n.ttc {\n        position: absolute;\n        display: none;\n}\n\n#powerTip {\n\tcursor: default;\n\twhite-space: nowrap;\n\tbackground-color: white;\n\tborder: 1px solid gray;\n\tborder-radius: 4px 4px 4px 4px;\n\tbox-shadow: 1px 1px 7px gray;\n\tdisplay: none;\n\tfont-size: smaller;\n\tmax-width: 80%;\n\topacity: 0.9;\n\tpadding: 1ex 1em 1em;\n\tposition: absolute;\n\tz-index: 2147483647;\n}\n\n#powerTip div.ttdoc {\n        color: grey;\n\tfont-style: italic;\n}\n\n#powerTip div.ttname a {\n        font-weight: bold;\n}\n\n#powerTip div.ttname {\n        font-weight: bold;\n}\n\n#powerTip div.ttdeci {\n        color: #006318;\n}\n\n#powerTip div {\n        margin: 0px;\n        padding: 0px;\n        font: 12px/16px Roboto,sans-serif;\n}\n\n#powerTip:before, #powerTip:after {\n\tcontent: \"\";\n\tposition: absolute;\n\tmargin: 0px;\n}\n\n#powerTip.n:after,  #powerTip.n:before,\n#powerTip.s:after,  #powerTip.s:before,\n#powerTip.w:after,  #powerTip.w:before,\n#powerTip.e:after,  #powerTip.e:before,\n#powerTip.ne:after, #powerTip.ne:before,\n#powerTip.se:after, #powerTip.se:before,\n#powerTip.nw:after, #powerTip.nw:before,\n#powerTip.sw:after, #powerTip.sw:before {\n\tborder: solid transparent;\n\tcontent: \" \";\n\theight: 0;\n\twidth: 0;\n\tposition: absolute;\n}\n\n#powerTip.n:after,  #powerTip.s:after,\n#powerTip.w:after,  #powerTip.e:after,\n#powerTip.nw:after, #powerTip.ne:after,\n#powerTip.sw:after, #powerTip.se:after {\n\tborder-color: rgba(255, 255, 255, 0);\n}\n\n#powerTip.n:before,  #powerTip.s:before,\n#powerTip.w:before,  #powerTip.e:before,\n#powerTip.nw:before, #powerTip.ne:before,\n#powerTip.sw:before, #powerTip.se:before {\n\tborder-color: rgba(128, 128, 128, 0);\n}\n\n#powerTip.n:after,  #powerTip.n:before,\n#powerTip.ne:after, #powerTip.ne:before,\n#powerTip.nw:after, #powerTip.nw:before {\n\ttop: 100%;\n}\n\n#powerTip.n:after, #powerTip.ne:after, #powerTip.nw:after {\n\tborder-top-color: #ffffff;\n\tborder-width: 10px;\n\tmargin: 0px -10px;\n}\n#powerTip.n:before {\n\tborder-top-color: #808080;\n\tborder-width: 11px;\n\tmargin: 0px -11px;\n}\n#powerTip.n:after, #powerTip.n:before {\n\tleft: 50%;\n}\n\n#powerTip.nw:after, #powerTip.nw:before {\n\tright: 14px;\n}\n\n#powerTip.ne:after, #powerTip.ne:before {\n\tleft: 14px;\n}\n\n#powerTip.s:after,  #powerTip.s:before,\n#powerTip.se:after, #powerTip.se:before,\n#powerTip.sw:after, #powerTip.sw:before {\n\tbottom: 100%;\n}\n\n#powerTip.s:after, #powerTip.se:after, #powerTip.sw:after {\n\tborder-bottom-color: #ffffff;\n\tborder-width: 10px;\n\tmargin: 0px -10px;\n}\n\n#powerTip.s:before, #powerTip.se:before, #powerTip.sw:before {\n\tborder-bottom-color: #808080;\n\tborder-width: 11px;\n\tmargin: 0px -11px;\n}\n\n#powerTip.s:after, #powerTip.s:before {\n\tleft: 50%;\n}\n\n#powerTip.sw:after, #powerTip.sw:before {\n\tright: 14px;\n}\n\n#powerTip.se:after, #powerTip.se:before {\n\tleft: 14px;\n}\n\n#powerTip.e:after, #powerTip.e:before {\n\tleft: 100%;\n}\n#powerTip.e:after {\n\tborder-left-color: #ffffff;\n\tborder-width: 10px;\n\ttop: 50%;\n\tmargin-top: -10px;\n}\n#powerTip.e:before {\n\tborder-left-color: #808080;\n\tborder-width: 11px;\n\ttop: 50%;\n\tmargin-top: -11px;\n}\n\n#powerTip.w:after, #powerTip.w:before {\n\tright: 100%;\n}\n#powerTip.w:after {\n\tborder-right-color: #ffffff;\n\tborder-width: 10px;\n\ttop: 50%;\n\tmargin-top: -10px;\n}\n#powerTip.w:before {\n\tborder-right-color: #808080;\n\tborder-width: 11px;\n\ttop: 50%;\n\tmargin-top: -11px;\n}\n\n@media print\n{\n  #top { display: none; }\n  #side-nav { display: none; }\n  #nav-path { display: none; }\n  body { overflow:visible; }\n  h1, h2, h3, h4, h5, h6 { page-break-after: avoid; }\n  .summary { display: none; }\n  .memitem { page-break-inside: avoid; }\n  #doc-content\n  {\n    margin-left:0 !important;\n    height:auto !important;\n    width:auto !important;\n    overflow:inherit;\n    display:inline;\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/dynsections.js",
    "content": "function toggleVisibility(linkObj)\n{\n var base = $(linkObj).attr('id');\n var summary = $('#'+base+'-summary');\n var content = $('#'+base+'-content');\n var trigger = $('#'+base+'-trigger');\n var src=$(trigger).attr('src');\n if (content.is(':visible')===true) {\n   content.hide();\n   summary.show();\n   $(linkObj).addClass('closed').removeClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');\n } else {\n   content.show();\n   summary.hide();\n   $(linkObj).removeClass('closed').addClass('opened');\n   $(trigger).attr('src',src.substring(0,src.length-10)+'open.png');\n } \n return false;\n}\n\nfunction updateStripes()\n{\n  $('table.directory tr').\n       removeClass('even').filter(':visible:even').addClass('even');\n}\nfunction toggleLevel(level)\n{\n  $('table.directory tr').each(function(){ \n    var l = this.id.split('_').length-1;\n    var i = $('#img'+this.id.substring(3));\n    var a = $('#arr'+this.id.substring(3));\n    if (l<level+1) {\n      i.attr('src','ftv2folderopen.png');\n      a.attr('src','ftv2mnode.png');\n      $(this).show();\n    } else if (l==level+1) {\n      i.attr('src','ftv2folderclosed.png');\n      a.attr('src','ftv2pnode.png');\n      $(this).show();\n    } else {\n      $(this).hide();\n    }\n  });\n  updateStripes();\n}\n\nfunction toggleFolder(id)\n{\n  //The clicked row\n  var currentRow = $('#row_'+id);\n  var currentRowImages = currentRow.find(\"img\");\n\n  //All rows after the clicked row\n  var rows = currentRow.nextAll(\"tr\");\n\n  //Only match elements AFTER this one (can't hide elements before)\n  var childRows = rows.filter(function() {\n    var re = new RegExp('^row_'+id+'\\\\d+_$', \"i\"); //only one sub\n    return this.id.match(re);\n  });\n\n  //First row is visible we are HIDING\n  if (childRows.filter(':first').is(':visible')===true) {\n    currentRowImages.filter(\"[id^=arr]\").attr('src', 'ftv2pnode.png');\n    currentRowImages.filter(\"[id^=img]\").attr('src', 'ftv2folderclosed.png');\n    rows.filter(\"[id^=row_\"+id+\"]\").hide();\n  } else { //We are SHOWING\n    //All sub images\n    var childImages = childRows.find(\"img\");\n    var childImg = childImages.filter(\"[id^=img]\");\n    var childArr = childImages.filter(\"[id^=arr]\");\n\n    currentRow.find(\"[id^=arr]\").attr('src', 'ftv2mnode.png'); //open row\n    currentRow.find(\"[id^=img]\").attr('src', 'ftv2folderopen.png'); //open row\n    childImg.attr('src','ftv2folderclosed.png'); //children closed\n    childArr.attr('src','ftv2pnode.png'); //children closed\n    childRows.show(); //show all children\n  }\n  updateStripes();\n}\n\n\nfunction toggleInherit(id)\n{\n  var rows = $('tr.inherit.'+id);\n  var img = $('tr.inherit_header.'+id+' img');\n  var src = $(img).attr('src');\n  if (rows.filter(':first').is(':visible')===true) {\n    rows.css('display','none');\n    $(img).attr('src',src.substring(0,src.length-8)+'closed.png');\n  } else {\n    rows.css('display','table-row'); // using show() causes jump in firefox\n    $(img).attr('src',src.substring(0,src.length-10)+'open.png');\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/element_dominate.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_dominate.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_dominate.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/element_keywords.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_keywords.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_keywords.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/element_releases.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_releases.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_releases.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/element_repository.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_repository.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_repository.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/element_requirements_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_requirements_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_requirements_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/element_taxonomy.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_taxonomy.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/element_taxonomy.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/flashAlgorithm.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/flashAlgorithm.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/flashAlgorithm.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/index.html",
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-->\n<div id=\"titlearea\">\n<table cellspacing=\"0\" cellpadding=\"0\">\n <tbody>\n <tr style=\"height: 46px;\">\n  <td id=\"projectlogo\"><img alt=\"Logo\" src=\"CMSIS_Logo_Final.png\"/></td>\n  <td style=\"padding-left: 0.5em;\">\n   <div id=\"projectname\">CMSIS-Pack\n   &#160;<span id=\"projectnumber\">Version 1.7.2</span>\n   </div>\n   <div id=\"projectbrief\">Delivery Mechanism for Software Packs</div>\n  </td>\n </tr>\n </tbody>\n</table>\n</div>\n<!-- end header part -->\n<div id=\"CMSISnav\" class=\"tabs1\">\n    <ul class=\"tablist\">\n      <script type=\"text/javascript\">\n\t\t<!--\n\t\twriteComponentTabs.call(this);\n\t\t//-->\n      </script>\n\t  </ul>\n</div>\n<!-- Generated by Doxygen 1.8.6 -->\n<script type=\"text/javascript\">\nvar searchBox = new SearchBox(\"searchBox\", \"search\",false,'Search');\n</script>\n  <div id=\"navrow1\" class=\"tabs\">\n    <ul class=\"tablist\">\n      <li class=\"current\"><a href=\"index.html\"><span>Main&#160;Page</span></a></li>\n      <li><a href=\"pages.html\"><span>Usage&#160;and&#160;Description</span></a></li>\n      <li>\n        <div id=\"MSearchBox\" class=\"MSearchBoxInactive\">\n        <span class=\"left\">\n          <img id=\"MSearchSelect\" src=\"search/mag_sel.png\"\n               onmouseover=\"return searchBox.OnSearchSelectShow()\"\n               onmouseout=\"return searchBox.OnSearchSelectHide()\"\n               alt=\"\"/>\n          <input type=\"text\" id=\"MSearchField\" value=\"Search\" accesskey=\"S\"\n               onfocus=\"searchBox.OnSearchFieldFocus(true)\" \n               onblur=\"searchBox.OnSearchFieldFocus(false)\" \n               onkeyup=\"searchBox.OnSearchFieldChange(event)\"/>\n          </span><span class=\"right\">\n            <a id=\"MSearchClose\" href=\"javascript:searchBox.CloseResultsWindow()\"><img id=\"MSearchCloseImg\" border=\"0\" src=\"search/close.png\" alt=\"\"/></a>\n          </span>\n        </div>\n      </li>\n    </ul>\n  </div>\n</div><!-- top -->\n<div id=\"side-nav\" class=\"ui-resizable side-nav-resizable\">\n  <div id=\"nav-tree\">\n    <div id=\"nav-tree-contents\">\n      <div id=\"nav-sync\" class=\"sync\"></div>\n    </div>\n  </div>\n  <div id=\"splitbar\" style=\"-moz-user-select:none;\" \n       class=\"ui-resizable-handle\">\n  </div>\n</div>\n<script type=\"text/javascript\">\n$(document).ready(function(){initNavTree('index.html','');});\n</script>\n<div id=\"doc-content\">\n<!-- window showing the filter options -->\n<div id=\"MSearchSelectWindow\"\n     onmouseover=\"return searchBox.OnSearchSelectShow()\"\n     onmouseout=\"return searchBox.OnSearchSelectHide()\"\n     onkeydown=\"return searchBox.OnSearchSelectKey(event)\">\n<a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(0)\"><span class=\"SelectionMark\">&#160;</span>All</a><a class=\"SelectItem\" href=\"javascript:void(0)\" onclick=\"searchBox.OnSelectItem(1)\"><span class=\"SelectionMark\">&#160;</span>Pages</a></div>\n\n<!-- iframe showing the search results (closed by default) -->\n<div id=\"MSearchResultsWindow\">\n<iframe src=\"javascript:void(0)\" frameborder=\"0\" \n        name=\"MSearchResults\" id=\"MSearchResults\">\n</iframe>\n</div>\n\n<div class=\"header\">\n  <div class=\"headertitle\">\n<div class=\"title\">CMSIS-Pack Documentation</div>  </div>\n</div><!--header-->\n<div class=\"contents\">\n<div class=\"textblock\"><p><b>CMSIS-Pack</b> is now part of the <b>Open-CMSIS-Pack</b> project at <a href=\"https://www.open-cmsis-pack.org\" target=\"_blank\">www.open-cmsis-pack.org</a>.</p>\n\nContent of this documentation is now <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/index.html\" target=\"_blank\"><b>provided here</b></a> and individual pages are redirected to the corresponding pages in Open-CMSIS-Pack specification.\n\n</div></div>\n</body>\n</html>\n"
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bw=this[0],bv=this.offsetParent(),bx=this.offset(),e=ad.test(bv[0].nodeName)?{top:0,left:0}:bv.offset();bx.top-=parseFloat(b.css(bw,\"marginTop\"))||0;bx.left-=parseFloat(b.css(bw,\"marginLeft\"))||0;e.top+=parseFloat(b.css(bv[0],\"borderTopWidth\"))||0;e.left+=parseFloat(b.css(bv[0],\"borderLeftWidth\"))||0;return{top:bx.top-e.top,left:bx.left-e.left}},offsetParent:function(){return this.map(function(){var e=this.offsetParent||av.body;while(e&&(!ad.test(e.nodeName)&&b.css(e,\"position\")===\"static\")){e=e.offsetParent}return e})}});b.each([\"Left\",\"Top\"],function(bv,e){var bw=\"scroll\"+e;b.fn[bw]=function(bz){var bx,by;if(bz===L){bx=this[0];if(!bx){return null}by=aK(bx);return by?(\"pageXOffset\" in by)?by[bv?\"pageYOffset\":\"pageXOffset\"]:b.support.boxModel&&by.document.documentElement[bw]||by.document.body[bw]:bx[bw]}return this.each(function(){by=aK(this);if(by){by.scrollTo(!bv?bz:b(by).scrollLeft(),bv?bz:b(by).scrollTop())}else{this[bw]=bz}})}});function aK(e){return b.isWindow(e)?e:e.nodeType===9?e.defaultView||e.parentWindow:false}b.each([\"Height\",\"Width\"],function(bv,e){var bw=e.toLowerCase();b.fn[\"inner\"+e]=function(){var bx=this[0];return bx?bx.style?parseFloat(b.css(bx,bw,\"padding\")):this[bw]():null};b.fn[\"outer\"+e]=function(by){var bx=this[0];return bx?bx.style?parseFloat(b.css(bx,bw,by?\"margin\":\"border\")):this[bw]():null};b.fn[bw]=function(bz){var bA=this[0];if(!bA){return bz==null?null:this}if(b.isFunction(bz)){return this.each(function(bE){var bD=b(this);bD[bw](bz.call(this,bE,bD[bw]()))})}if(b.isWindow(bA)){var bB=bA.document.documentElement[\"client\"+e],bx=bA.document.body;return bA.document.compatMode===\"CSS1Compat\"&&bB||bx&&bx[\"client\"+e]||bB}else{if(bA.nodeType===9){return Math.max(bA.documentElement[\"client\"+e],bA.body[\"scroll\"+e],bA.documentElement[\"scroll\"+e],bA.body[\"offset\"+e],bA.documentElement[\"offset\"+e])}else{if(bz===L){var bC=b.css(bA,bw),by=parseFloat(bC);return b.isNumeric(by)?by:bC}else{return this.css(bw,typeof bz===\"string\"?bz:bz+\"px\")}}}}});bb.jQuery=bb.$=b;if(typeof define===\"function\"&&define.amd&&define.amd.jQuery){define(\"jquery\",[],function(){return b\n})}})(window);\n/*!\n * jQuery UI 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI\n */\n(function(a,d){a.ui=a.ui||{};if(a.ui.version){return}a.extend(a.ui,{version:\"1.8.18\",keyCode:{ALT:18,BACKSPACE:8,CAPS_LOCK:20,COMMA:188,COMMAND:91,COMMAND_LEFT:91,COMMAND_RIGHT:93,CONTROL:17,DELETE:46,DOWN:40,END:35,ENTER:13,ESCAPE:27,HOME:36,INSERT:45,LEFT:37,MENU:93,NUMPAD_ADD:107,NUMPAD_DECIMAL:110,NUMPAD_DIVIDE:111,NUMPAD_ENTER:108,NUMPAD_MULTIPLY:106,NUMPAD_SUBTRACT:109,PAGE_DOWN:34,PAGE_UP:33,PERIOD:190,RIGHT:39,SHIFT:16,SPACE:32,TAB:9,UP:38,WINDOWS:91}});a.fn.extend({propAttr:a.fn.prop||a.fn.attr,_focus:a.fn.focus,focus:function(e,f){return typeof e===\"number\"?this.each(function(){var g=this;setTimeout(function(){a(g).focus();if(f){f.call(g)}},e)}):this._focus.apply(this,arguments)},scrollParent:function(){var e;if((a.browser.msie&&(/(static|relative)/).test(this.css(\"position\")))||(/absolute/).test(this.css(\"position\"))){e=this.parents().filter(function(){return(/(relative|absolute|fixed)/).test(a.curCSS(this,\"position\",1))&&(/(auto|scroll)/).test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0)}else{e=this.parents().filter(function(){return(/(auto|scroll)/).test(a.curCSS(this,\"overflow\",1)+a.curCSS(this,\"overflow-y\",1)+a.curCSS(this,\"overflow-x\",1))}).eq(0)}return(/fixed/).test(this.css(\"position\"))||!e.length?a(document):e},zIndex:function(h){if(h!==d){return this.css(\"zIndex\",h)}if(this.length){var f=a(this[0]),e,g;while(f.length&&f[0]!==document){e=f.css(\"position\");if(e===\"absolute\"||e===\"relative\"||e===\"fixed\"){g=parseInt(f.css(\"zIndex\"),10);if(!isNaN(g)&&g!==0){return g}}f=f.parent()}}return 0},disableSelection:function(){return this.bind((a.support.selectstart?\"selectstart\":\"mousedown\")+\".ui-disableSelection\",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(\".ui-disableSelection\")}});a.each([\"Width\",\"Height\"],function(g,e){var f=e===\"Width\"?[\"Left\",\"Right\"]:[\"Top\",\"Bottom\"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,\"padding\"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,\"border\"+this+\"Width\",true))||0}if(n){l-=parseFloat(a.curCSS(m,\"margin\"+this,true))||0}});return l}a.fn[\"inner\"+e]=function(i){if(i===d){return k[\"inner\"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+\"px\")})};a.fn[\"outer\"+e]=function(i,l){if(typeof i!==\"number\"){return k[\"outer\"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+\"px\")})}});function c(g,e){var j=g.nodeName.toLowerCase();if(\"area\"===j){var i=g.parentNode,h=i.name,f;if(!g.href||!h||i.nodeName.toLowerCase()!==\"map\"){return false}f=a(\"img[usemap=#\"+h+\"]\")[0];return !!f&&b(f)}return(/input|select|textarea|button|object/.test(j)?!g.disabled:\"a\"==j?g.href||e:e)&&b(g)}function b(e){return !a(e).parents().andSelf().filter(function(){return a.curCSS(this,\"visibility\")===\"hidden\"||a.expr.filters.hidden(this)}).length}a.extend(a.expr[\":\"],{data:function(g,f,e){return !!a.data(g,e[3])},focusable:function(e){return c(e,!isNaN(a.attr(e,\"tabindex\")))},tabbable:function(g){var e=a.attr(g,\"tabindex\"),f=isNaN(e);return(f||e>=0)&&c(g,!f)}});a(function(){var e=document.body,f=e.appendChild(f=document.createElement(\"div\"));f.offsetHeight;a.extend(f.style,{minHeight:\"100px\",height:\"auto\",padding:0,borderWidth:0});a.support.minHeight=f.offsetHeight===100;a.support.selectstart=\"onselectstart\" in f;e.removeChild(f).style.display=\"none\"});a.extend(a.ui,{plugin:{add:function(f,g,j){var h=a.ui[f].prototype;for(var e in j){h.plugins[e]=h.plugins[e]||[];h.plugins[e].push([g,j[e]])}},call:function(e,g,f){var j=e.plugins[g];if(!j||!e.element[0].parentNode){return}for(var h=0;h<j.length;h++){if(e.options[j[h][0]]){j[h][1].apply(e.element,f)}}}},contains:function(f,e){return document.compareDocumentPosition?f.compareDocumentPosition(e)&16:f!==e&&f.contains(e)},hasScroll:function(h,f){if(a(h).css(\"overflow\")===\"hidden\"){return false}var e=(f&&f===\"left\")?\"scrollLeft\":\"scrollTop\",g=false;if(h[e]>0){return true}h[e]=1;g=(h[e]>0);h[e]=0;return g},isOverAxis:function(f,e,g){return(f>e)&&(f<(e+g))},isOver:function(j,f,i,h,e,g){return a.ui.isOverAxis(j,i,e)&&a.ui.isOverAxis(f,h,g)}})})(jQuery);/*!\n * jQuery UI Widget 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Widget\n */\n(function(b,d){if(b.cleanData){var c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler(\"remove\")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b(\"*\",this).add([this]).each(function(){try{b(this).triggerHandler(\"remove\")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(\".\")[0],j;f=f.split(\".\")[1];j=g+\"-\"+f;if(!e){e=h;h=b.Widget}b.expr[\":\"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof i===\"string\",h=Array.prototype.slice.call(arguments,1),j=this;i=!g&&h.length?b.extend.apply(null,[true,i].concat(h)):i;if(g&&i.charAt(0)===\"_\"){return j}if(g){this.each(function(){var k=b.data(this,f),l=k&&b.isFunction(k[i])?k[i].apply(k,h):k;if(l!==k&&l!==d){j=l;return false}})}else{this.each(function(){var k=b.data(this,f);if(k){k.option(i||{})._init()}else{b.data(this,f,new e(i,this))}})}return j}};b.Widget=function(e,f){if(arguments.length){this._createWidget(e,f)}};b.Widget.prototype={widgetName:\"widget\",widgetEventPrefix:\"\",options:{disabled:false},_createWidget:function(f,g){b.data(g,this.widgetName,this);this.element=b(g);this.options=b.extend(true,{},this.options,this._getCreateOptions(),f);var e=this;this.element.bind(\"remove.\"+this.widgetName,function(){e.destroy()});this._create();this._trigger(\"create\");this._init()},_getCreateOptions:function(){return b.metadata&&b.metadata.get(this.element[0])[this.widgetName]},_create:function(){},_init:function(){},destroy:function(){this.element.unbind(\".\"+this.widgetName).removeData(this.widgetName);this.widget().unbind(\".\"+this.widgetName).removeAttr(\"aria-disabled\").removeClass(this.widgetBaseClass+\"-disabled ui-state-disabled\")},widget:function(){return this.element},option:function(f,g){var e=f;if(arguments.length===0){return b.extend({},this.options)}if(typeof f===\"string\"){if(g===d){return this.options[f]}e={};e[f]=g}this._setOptions(e);return this},_setOptions:function(f){var e=this;b.each(f,function(g,h){e._setOption(g,h)});return this},_setOption:function(e,f){this.options[e]=f;if(e===\"disabled\"){this.widget()[f?\"addClass\":\"removeClass\"](this.widgetBaseClass+\"-disabled ui-state-disabled\").attr(\"aria-disabled\",f)}return this},enable:function(){return this._setOption(\"disabled\",false)},disable:function(){return this._setOption(\"disabled\",true)},_trigger:function(e,f,g){var j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*!\n * jQuery UI Mouse 1.8.18\n *\n * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about)\n * Dual licensed under the MIT or GPL Version 2 licenses.\n * http://jquery.org/license\n *\n * http://docs.jquery.com/UI/Mouse\n *\n * Depends:\n *\tjquery.ui.widget.js\n */\n(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget(\"ui.mouse\",{options:{cancel:\":input,option\",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind(\"mousedown.\"+this.widgetName,function(e){return d._mouseDown(e)}).bind(\"click.\"+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+\".preventClickEvent\")){b.removeData(e.target,d.widgetName+\".preventClickEvent\");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind(\".\"+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel==\"string\"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+\".preventClickEvent\")){b.removeData(f.target,this.widgetName+\".preventClickEvent\")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).bind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return !this._mouseStarted},_mouseUp:function(d){b(document).unbind(\"mousemove.\"+this.widgetName,this._mouseMoveDelegate).unbind(\"mouseup.\"+this.widgetName,this._mouseUpDelegate);if(this._mouseStarted){this._mouseStarted=false;if(d.target==this._mouseDownEvent.target){b.data(d.target,this.widgetName+\".preventClickEvent\",true)}this._mouseStop(d)}return false},_mouseDistanceMet:function(d){return(Math.max(Math.abs(this._mouseDownEvent.pageX-d.pageX),Math.abs(this._mouseDownEvent.pageY-d.pageY))>=this.options.distance)},_mouseDelayMet:function(d){return this.mouseDelayMet},_mouseStart:function(d){},_mouseDrag:function(d){},_mouseStop:function(d){},_mouseCapture:function(d){return true}})})(jQuery);(function(c,d){c.widget(\"ui.resizable\",c.ui.mouse,{widgetEventPrefix:\"resize\",options:{alsoResize:false,animate:false,animateDuration:\"slow\",animateEasing:\"swing\",aspectRatio:false,autoHide:false,containment:false,ghost:false,grid:false,handles:\"e,s,se\",helper:false,maxHeight:null,maxWidth:null,minHeight:10,minWidth:10,zIndex:1000},_create:function(){var f=this,k=this.options;this.element.addClass(\"ui-resizable\");c.extend(this,{_aspectRatio:!!(k.aspectRatio),aspectRatio:k.aspectRatio,originalElement:this.element,_proportionallyResizeElements:[],_helper:k.helper||k.ghost||k.animate?k.helper||\"ui-resizable-helper\":null});if(this.element[0].nodeName.match(/canvas|textarea|input|select|button|img/i)){this.element.wrap(c('<div class=\"ui-wrapper\" style=\"overflow: hidden;\"></div>').css({position:this.element.css(\"position\"),width:this.element.outerWidth(),height:this.element.outerHeight(),top:this.element.css(\"top\"),left:this.element.css(\"left\")}));this.element=this.element.parent().data(\"resizable\",this.element.data(\"resizable\"));this.elementIsWrapper=true;this.element.css({marginLeft:this.originalElement.css(\"marginLeft\"),marginTop:this.originalElement.css(\"marginTop\"),marginRight:this.originalElement.css(\"marginRight\"),marginBottom:this.originalElement.css(\"marginBottom\")});this.originalElement.css({marginLeft:0,marginTop:0,marginRight:0,marginBottom:0});this.originalResizeStyle=this.originalElement.css(\"resize\");this.originalElement.css(\"resize\",\"none\");this._proportionallyResizeElements.push(this.originalElement.css({position:\"static\",zoom:1,display:\"block\"}));this.originalElement.css({margin:this.originalElement.css(\"margin\")});this._proportionallyResize()}this.handles=k.handles||(!c(\".ui-resizable-handle\",this.element).length?\"e,s,se\":{n:\".ui-resizable-n\",e:\".ui-resizable-e\",s:\".ui-resizable-s\",w:\".ui-resizable-w\",se:\".ui-resizable-se\",sw:\".ui-resizable-sw\",ne:\".ui-resizable-ne\",nw:\".ui-resizable-nw\"});if(this.handles.constructor==String){if(this.handles==\"all\"){this.handles=\"n,e,s,w,se,sw,ne,nw\"}var l=this.handles.split(\",\");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e=\"ui-resizable-\"+j;var h=c('<div class=\"ui-resizable-handle '+e+'\"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if(\"se\"==j){h.addClass(\"ui-icon ui-icon-gripsmall-diagonal-se\")}this.handles[j]=\".ui-resizable-\"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var m=[\"padding\",/ne|nw|n/.test(n)?\"Top\":/se|sw|s/.test(n)?\"Bottom\":/^e$/.test(n)?\"Right\":\"Left\"].join(\"\");q.css(m,p);this._proportionallyResize()}if(!c(this.handles[n]).length){continue}}};this._renderAxis(this.element);this._handles=c(\".ui-resizable-handle\",this.element).disableSelection();this._handles.mouseover(function(){if(!f.resizing){if(this.className){var i=this.className.match(/ui-resizable-(se|sw|ne|nw|n|e|s|w)/i)}f.axis=i&&i[1]?i[1]:\"se\"}});if(k.autoHide){this._handles.hide();c(this.element).addClass(\"ui-resizable-autohide\").hover(function(){if(k.disabled){return}c(this).removeClass(\"ui-resizable-autohide\");f._handles.show()},function(){if(k.disabled){return}if(!f.resizing){c(this).addClass(\"ui-resizable-autohide\");f._handles.hide()}})}this._mouseInit()},destroy:function(){this._mouseDestroy();var e=function(g){c(g).removeClass(\"ui-resizable ui-resizable-disabled ui-resizable-resizing\").removeData(\"resizable\").unbind(\".resizable\").find(\".ui-resizable-handle\").remove()};if(this.elementIsWrapper){e(this.element);var f=this.element;f.after(this.originalElement.css({position:f.css(\"position\"),width:f.outerWidth(),height:f.outerHeight(),top:f.css(\"top\"),left:f.css(\"left\")})).remove()}this.originalElement.css(\"resize\",this.originalResizeStyle);e(this.originalElement);return this},_mouseCapture:function(f){var g=false;for(var e in this.handles){if(c(this.handles[e])[0]==f.target){g=true}}return !this.options.disabled&&g},_mouseStart:function(g){var j=this.options,f=this.element.position(),e=this.element;this.resizing=true;this.documentScroll={top:c(document).scrollTop(),left:c(document).scrollLeft()};if(e.is(\".ui-draggable\")||(/absolute/).test(e.css(\"position\"))){e.css({position:\"absolute\",top:f.top,left:f.left})}this._renderProxy();var k=b(this.helper.css(\"left\")),h=b(this.helper.css(\"top\"));if(j.containment){k+=c(j.containment).scrollLeft()||0;h+=c(j.containment).scrollTop()||0}this.offset=this.helper.offset();this.position={left:k,top:h};this.size=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalSize=this._helper?{width:e.outerWidth(),height:e.outerHeight()}:{width:e.width(),height:e.height()};this.originalPosition={left:k,top:h};this.sizeDiff={width:e.outerWidth()-e.width(),height:e.outerHeight()-e.height()};this.originalMousePosition={left:g.pageX,top:g.pageY};this.aspectRatio=(typeof j.aspectRatio==\"number\")?j.aspectRatio:((this.originalSize.width/this.originalSize.height)||1);var i=c(\".ui-resizable-\"+this.axis).css(\"cursor\");c(\"body\").css(\"cursor\",i==\"auto\"?this.axis+\"-resize\":i);e.addClass(\"ui-resizable-resizing\");this._propagate(\"start\",g);return true},_mouseDrag:function(e){var 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  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/navtree.css",
    "content": "#nav-tree .children_ul {\n  margin:0;\n  padding:4px;\n}\n\n#nav-tree ul {\n  list-style:none outside none;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree li {\n  white-space:nowrap;\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .plus {\n  margin:0px;\n}\n\n#nav-tree .selected {\n  background-image: url('tab_a.png');\n  background-repeat:repeat-x;\n  color: #fff;\n  text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n\n#nav-tree img {\n  margin:0px;\n  padding:0px;\n  border:0px;\n  vertical-align: middle;\n}\n\n#nav-tree a {\n  text-decoration:none;\n  padding:0px;\n  margin:0px;\n  outline:none;\n}\n\n#nav-tree .label {\n  margin:0px;\n  padding:0px;\n  font: 12px 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif;\n}\n\n#nav-tree .label a {\n  padding:2px;\n}\n\n#nav-tree .selected a {\n  text-decoration:none;\n  color:#fff;\n}\n\n#nav-tree .children_ul {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree .item {\n  margin:0px;\n  padding:0px;\n}\n\n#nav-tree {\n  padding: 0px 0px;\n  background-color: #FAFAFF; \n  font-size:14px;\n  overflow:auto;\n}\n\n#doc-content {\n  overflow:auto;\n  display:block;\n  padding:0px;\n  margin:0px;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#side-nav {\n  padding:0 6px 0 0;\n  margin: 0px;\n  display:block;\n  position: absolute;\n  left: 0px;\n  width: 250px;\n}\n\n.ui-resizable .ui-resizable-handle {\n  display:block;\n}\n\n.ui-resizable-e {\n  background:url(\"ftv2splitbar.png\") repeat scroll right center transparent;\n  cursor:e-resize;\n  height:100%;\n  right:0;\n  top:0;\n  width:6px;\n}\n\n.ui-resizable-handle {\n  display:none;\n  font-size:0.1px;\n  position:absolute;\n  z-index:1;\n}\n\n#nav-tree-contents {\n  margin: 6px 0px 0px 0px;\n}\n\n#nav-tree {\n  background-image:url('nav_h.png');\n  background-repeat:repeat-x;\n  background-color: #F9FAFC;\n  -webkit-overflow-scrolling : touch; /* iOS 5+ */\n}\n\n#nav-sync {\n  position:absolute;\n  top:5px;\n  right:24px;\n  z-index:0;\n}\n\n#nav-sync img {\n  opacity:0.3;\n}\n\n#nav-sync img:hover {\n  opacity:0.9;\n}\n\n@media print\n{\n  #nav-tree { display: none; }\n  div.ui-resizable-handle { display: none; position: relative; }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/navtree.js",
    "content": "var NAVTREE =\n[\n  [ \"CMSIS-Pack\", \"index.html\"]\n\n];\n\nvar NAVTREEINDEX =\n[\n\"index.html\"\n];\n\nvar SYNCONMSG = 'click to disable panel synchronisation';\nvar SYNCOFFMSG = 'click to enable panel synchronisation';\nvar SYNCONMSG = 'click to disable panel synchronisation';\nvar SYNCOFFMSG = 'click to enable panel synchronisation';\nvar navTreeSubIndices = new Array();\n\nfunction getData(varName)\n{\n  var i = varName.lastIndexOf('/');\n  var n = i>=0 ? varName.substring(i+1) : varName;\n  return eval(n.replace(/\\-/g,'_'));\n}\n\nfunction stripPath(uri)\n{\n  return uri.substring(uri.lastIndexOf('/')+1);\n}\n\nfunction stripPath2(uri)\n{\n  var i = uri.lastIndexOf('/');\n  var s = uri.substring(i+1);\n  var m = uri.substring(0,i+1).match(/\\/d\\w\\/d\\w\\w\\/$/);\n  return m ? uri.substring(i-6) : s;\n}\n\nfunction localStorageSupported()\n{\n  try {\n    return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem;\n  }\n  catch(e) {\n    return false;\n  }\n}\n\n\nfunction storeLink(link)\n{\n  if (!$(\"#nav-sync\").hasClass('sync') && localStorageSupported()) {\n      window.localStorage.setItem('navpath',link);\n  }\n}\n\nfunction deleteLink()\n{\n  if (localStorageSupported()) {\n    window.localStorage.setItem('navpath','');\n  } \n}\n\nfunction cachedLink()\n{\n  if (localStorageSupported()) {\n    return window.localStorage.getItem('navpath');\n  } else {\n    return '';\n  }\n}\n\nfunction getScript(scriptName,func,show)\n{\n  var head = document.getElementsByTagName(\"head\")[0]; \n  var script = document.createElement('script');\n  script.id = scriptName;\n  script.type = 'text/javascript';\n  script.onload = func; \n  script.src = scriptName+'.js'; \n  if ($.browser.msie && $.browser.version<=8) { \n    // script.onload does not work with older versions of IE\n    script.onreadystatechange = function() {\n      if (script.readyState=='complete' || script.readyState=='loaded') { \n        func(); if (show) showRoot(); \n      }\n    }\n  }\n  head.appendChild(script); \n}\n\nfunction createIndent(o,domNode,node,level)\n{\n  var level=-1;\n  var n = node;\n  while (n.parentNode) { level++; n=n.parentNode; }\n  if (node.childrenData) {\n    var imgNode = document.createElement(\"img\");\n    imgNode.style.paddingLeft=(16*level).toString()+'px';\n    imgNode.width  = 16;\n    imgNode.height = 22;\n    imgNode.border = 0;\n    node.plus_img = imgNode;\n    node.expandToggle = document.createElement(\"a\");\n    node.expandToggle.href = \"javascript:void(0)\";\n    node.expandToggle.onclick = function() {\n      if (node.expanded) {\n        $(node.getChildrenUL()).slideUp(\"fast\");\n        node.plus_img.src = node.relpath+\"ftv2pnode.png\";\n        node.expanded = false;\n      } else {\n        expandNode(o, node, false, false);\n      }\n    }\n    node.expandToggle.appendChild(imgNode);\n    domNode.appendChild(node.expandToggle);\n    imgNode.src = node.relpath+\"ftv2pnode.png\";\n  } else {\n    var span = document.createElement(\"span\");\n    span.style.display = 'inline-block';\n    span.style.width   = 16*(level+1)+'px';\n    span.style.height  = '22px';\n    span.innerHTML = '&#160;';\n    domNode.appendChild(span);\n  } \n}\n\nvar animationInProgress = false;\n\nfunction gotoAnchor(anchor,aname,updateLocation)\n{\n  var pos, docContent = $('#doc-content');\n  if (anchor.parent().attr('class')=='memItemLeft' ||\n      anchor.parent().attr('class')=='fieldtype' ||\n      anchor.parent().is(':header')) \n  {\n    pos = anchor.parent().position().top;\n  } else if (anchor.position()) {\n    pos = anchor.position().top;\n  }\n  if (pos) {\n    var dist = Math.abs(Math.min(\n               pos-docContent.offset().top,\n               docContent[0].scrollHeight-\n               docContent.height()-docContent.scrollTop()));\n    animationInProgress=true;\n    docContent.animate({\n      scrollTop: pos + docContent.scrollTop() - docContent.offset().top\n    },Math.max(50,Math.min(500,dist)),function(){\n      if (updateLocation) window.location.href=aname;\n      animationInProgress=false;\n    });\n  }\n}\n\nfunction newNode(o, po, text, link, childrenData, lastNode)\n{\n  var node = new Object();\n  node.children = Array();\n  node.childrenData = childrenData;\n  node.depth = po.depth + 1;\n  node.relpath = po.relpath;\n  node.isLast = lastNode;\n\n  node.li = document.createElement(\"li\");\n  po.getChildrenUL().appendChild(node.li);\n  node.parentNode = po;\n\n  node.itemDiv = document.createElement(\"div\");\n  node.itemDiv.className = \"item\";\n\n  node.labelSpan = document.createElement(\"span\");\n  node.labelSpan.className = \"label\";\n\n  createIndent(o,node.itemDiv,node,0);\n  node.itemDiv.appendChild(node.labelSpan);\n  node.li.appendChild(node.itemDiv);\n\n  var a = document.createElement(\"a\");\n  node.labelSpan.appendChild(a);\n  node.label = document.createTextNode(text);\n  node.expanded = false;\n  a.appendChild(node.label);\n  if (link) {\n    var url;\n    if (link.substring(0,1)=='^') {\n      url = link.substring(1);\n      link = url;\n    } else {\n      url = node.relpath+link;\n    }\n    a.className = stripPath(link.replace('#',':'));\n    if (link.indexOf('#')!=-1) {\n      var aname = '#'+link.split('#')[1];\n      var srcPage = stripPath($(location).attr('pathname'));\n      var targetPage = stripPath(link.split('#')[0]);\n      a.href = srcPage!=targetPage ? url : \"javascript:void(0)\"; \n      a.onclick = function(){\n        storeLink(link);\n        if (!$(a).parent().parent().hasClass('selected'))\n        {\n          $('.item').removeClass('selected');\n          $('.item').removeAttr('id');\n          $(a).parent().parent().addClass('selected');\n          $(a).parent().parent().attr('id','selected');\n        }\n        var anchor = $(aname);\n        gotoAnchor(anchor,aname,true);\n      };\n    } else {\n      a.href = url;\n      a.onclick = function() { storeLink(link); }\n    }\n  } else {\n    if (childrenData != null) \n    {\n      a.className = \"nolink\";\n      a.href = \"javascript:void(0)\";\n      a.onclick = node.expandToggle.onclick;\n    }\n  }\n\n  node.childrenUL = null;\n  node.getChildrenUL = function() {\n    if (!node.childrenUL) {\n      node.childrenUL = document.createElement(\"ul\");\n      node.childrenUL.className = \"children_ul\";\n      node.childrenUL.style.display = \"none\";\n      node.li.appendChild(node.childrenUL);\n    }\n    return node.childrenUL;\n  };\n\n  return node;\n}\n\nfunction showRoot()\n{\n  var headerHeight = $(\"#top\").height();\n  var footerHeight = $(\"#nav-path\").height();\n  var windowHeight = $(window).height() - headerHeight - footerHeight;\n  (function (){ // retry until we can scroll to the selected item\n    try {\n      var navtree=$('#nav-tree');\n      navtree.scrollTo('#selected',0,{offset:-windowHeight/2});\n    } catch (err) {\n      setTimeout(arguments.callee, 0);\n    }\n  })();\n}\n\nfunction expandNode(o, node, imm, showRoot)\n{\n  if (node.childrenData && !node.expanded) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        expandNode(o, node, imm, showRoot);\n      }, showRoot);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      } if (imm || ($.browser.msie && $.browser.version>8)) { \n        // somehow slideDown jumps to the start of tree for IE9 :-(\n        $(node.getChildrenUL()).show();\n      } else {\n        $(node.getChildrenUL()).slideDown(\"fast\");\n      }\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n    }\n  }\n}\n\nfunction glowEffect(n,duration)\n{\n  n.addClass('glow').delay(duration).queue(function(next){\n    $(this).removeClass('glow');next();\n  });\n}\n\nfunction highlightAnchor()\n{\n  var aname = $(location).attr('hash');\n  var anchor = $(aname);\n  if (anchor.parent().attr('class')=='memItemLeft'){\n    var rows = $('.memberdecls tr[class$=\"'+\n               window.location.hash.substring(1)+'\"]');\n    glowEffect(rows.children(),300); // member without details\n  } else if (anchor.parents().slice(2).prop('tagName')=='TR') {\n    glowEffect(anchor.parents('div.memitem'),1000); // enum value\n  } else if (anchor.parent().attr('class')=='fieldtype'){\n    glowEffect(anchor.parent().parent(),1000); // struct field\n  } else if (anchor.parent().is(\":header\")) {\n    glowEffect(anchor.parent(),1000); // section header\n  } else {\n    glowEffect(anchor.next(),1000); // normal member\n  }\n  gotoAnchor(anchor,aname,false);\n}\n\nfunction selectAndHighlight(hash,n)\n{\n  var a;\n  if (hash) {\n    var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1);\n    a=$('.item a[class$=\"'+link+'\"]');\n  }\n  if (a && a.length) {\n    a.parent().parent().addClass('selected');\n    a.parent().parent().attr('id','selected');\n    highlightAnchor();\n  } else if (n) {\n    $(n.itemDiv).addClass('selected');\n    $(n.itemDiv).attr('id','selected');\n  }\n  if ($('#nav-tree-contents .item:first').hasClass('selected')) {\n    $('#nav-sync').css('top','30px');\n  } else {\n    $('#nav-sync').css('top','5px');\n  }\n  showRoot();\n}\n\nfunction showNode(o, node, index, hash)\n{\n  if (node && node.childrenData) {\n    if (typeof(node.childrenData)==='string') {\n      var varName    = node.childrenData;\n      getScript(node.relpath+varName,function(){\n        node.childrenData = getData(varName);\n        showNode(o,node,index,hash);\n      },true);\n    } else {\n      if (!node.childrenVisited) {\n        getNode(o, node);\n      }\n      $(node.getChildrenUL()).css({'display':'block'});\n      if (node.isLast) {\n        node.plus_img.src = node.relpath+\"ftv2mlastnode.png\";\n      } else {\n        node.plus_img.src = node.relpath+\"ftv2mnode.png\";\n      }\n      node.expanded = true;\n      var n = node.children[o.breadcrumbs[index]];\n      if (index+1<o.breadcrumbs.length) {\n        showNode(o,n,index+1,hash);\n      } else {\n        if (typeof(n.childrenData)==='string') {\n          var varName = n.childrenData;\n          getScript(n.relpath+varName,function(){\n            n.childrenData = getData(varName);\n            node.expanded=false;\n            showNode(o,node,index,hash); // retry with child node expanded\n          },true);\n        } else {\n          var rootBase = stripPath(o.toroot.replace(/\\..+$/, ''));\n          if (rootBase==\"index\" || rootBase==\"pages\" || rootBase==\"search\") {\n            expandNode(o, n, true, true);\n          }\n          selectAndHighlight(hash,n);\n        }\n      }\n    }\n  } else {\n    selectAndHighlight(hash);\n  }\n}\n\nfunction removeToInsertLater(element) {\n  var parentNode = element.parentNode;\n  var nextSibling = element.nextSibling;\n  parentNode.removeChild(element);\n  return function() {\n    if (nextSibling) {\n      parentNode.insertBefore(element, nextSibling);\n    } else {\n      parentNode.appendChild(element);\n    }\n  };\n}\n\nfunction getNode(o, po)\n{\n  var insertFunction = removeToInsertLater(po.li);\n  po.childrenVisited = true;\n  var l = po.childrenData.length-1;\n  for (var i in po.childrenData) {\n    var nodeData = po.childrenData[i];\n    po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],\n      i==l);\n  }\n  insertFunction();\n}\n\nfunction gotoNode(o,subIndex,root,hash,relpath)\n{\n  var nti = navTreeSubIndices[subIndex][root+hash];\n  o.breadcrumbs = $.extend(true, [], nti ? nti : navTreeSubIndices[subIndex][root]);\n  if (!o.breadcrumbs && root!=NAVTREE[0][1]) { // fallback: show index\n    navTo(o,NAVTREE[0][1],\"\",relpath);\n    $('.item').removeClass('selected');\n    $('.item').removeAttr('id');\n  }\n  if (o.breadcrumbs) {\n    o.breadcrumbs.unshift(0); // add 0 for root node\n    showNode(o, o.node, 0, hash);\n  }\n}\n\nfunction navTo(o,root,hash,relpath)\n{\n  var link = cachedLink();\n  if (link) {\n    var parts = link.split('#');\n    root = parts[0];\n    if (parts.length>1) hash = '#'+parts[1];\n    else hash='';\n  }\n  if (hash.match(/^#l\\d+$/)) {\n    var anchor=$('a[name='+hash.substring(1)+']');\n    glowEffect(anchor.parent(),1000); // line number\n    hash=''; // strip line number anchors\n    //root=root.replace(/_source\\./,'.'); // source link to doc link\n  }\n  var url=root+hash;\n  var i=-1;\n  while (NAVTREEINDEX[i+1]<=url) i++;\n  if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index\n  if (navTreeSubIndices[i]) {\n    gotoNode(o,i,root,hash,relpath)\n  } else {\n    getScript(relpath+'navtreeindex'+i,function(){\n      navTreeSubIndices[i] = eval('NAVTREEINDEX'+i);\n      if (navTreeSubIndices[i]) {\n        gotoNode(o,i,root,hash,relpath);\n      }\n    },true);\n  }\n}\n\nfunction showSyncOff(n,relpath)\n{\n    n.html('<img src=\"'+relpath+'sync_off.png\" title=\"'+SYNCOFFMSG+'\"/>');\n}\n\nfunction showSyncOn(n,relpath)\n{\n    n.html('<img src=\"'+relpath+'sync_on.png\" title=\"'+SYNCONMSG+'\"/>');\n}\n\nfunction toggleSyncButton(relpath)\n{\n  var navSync = $('#nav-sync');\n  if (navSync.hasClass('sync')) {\n    navSync.removeClass('sync');\n    showSyncOff(navSync,relpath);\n    storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash'));\n  } else {\n    navSync.addClass('sync');\n    showSyncOn(navSync,relpath);\n    deleteLink();\n  }\n}\n\nfunction initNavTree(toroot,relpath)\n{\n  var o = new Object();\n  o.toroot = toroot;\n  o.node = new Object();\n  o.node.li = document.getElementById(\"nav-tree-contents\");\n  o.node.childrenData = NAVTREE;\n  o.node.children = new Array();\n  o.node.childrenUL = document.createElement(\"ul\");\n  o.node.getChildrenUL = function() { return o.node.childrenUL; };\n  o.node.li.appendChild(o.node.childrenUL);\n  o.node.depth = 0;\n  o.node.relpath = relpath;\n  o.node.expanded = false;\n  o.node.isLast = true;\n  o.node.plus_img = document.createElement(\"img\");\n  o.node.plus_img.src = relpath+\"ftv2pnode.png\";\n  o.node.plus_img.width = 16;\n  o.node.plus_img.height = 22;\n\n  if (localStorageSupported()) {\n    var navSync = $('#nav-sync');\n    if (cachedLink()) {\n      showSyncOff(navSync,relpath);\n      navSync.removeClass('sync');\n    } else {\n      showSyncOn(navSync,relpath);\n    }\n    navSync.click(function(){ toggleSyncButton(relpath); });\n  }\n\n  $(window).load(function(){\n    navTo(o,toroot,window.location.hash,relpath);\n    showRoot();\n  });\n\n  $(window).bind('hashchange', function(){\n     if (window.location.hash && window.location.hash.length>1){\n       var a;\n       if ($(location).attr('hash')){\n         var clslink=stripPath($(location).attr('pathname'))+':'+\n                               $(location).attr('hash').substring(1);\n         a=$('.item a[class$=\"'+clslink+'\"]');\n       }\n       if (a==null || !$(a).parent().parent().hasClass('selected')){\n         $('.item').removeClass('selected');\n         $('.item').removeAttr('id');\n       }\n       var link=stripPath2($(location).attr('pathname'));\n       navTo(o,link,$(location).attr('hash'),relpath);\n     } else if (!animationInProgress) {\n       $('#doc-content').scrollTop(0);\n       $('.item').removeClass('selected');\n       $('.item').removeAttr('id');\n       navTo(o,toroot,window.location.hash,relpath);\n     }\n  })\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/navtreeindex0.js",
    "content": "var NAVTREEINDEX0 =\n{\n\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/packChk.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/packChk.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/packChk.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/packFormat.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/packFormat.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/packFormat.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/packIndexFile.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/packIndexFile.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/packIndexFile.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pack_revisionHistory.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pack_revisionHistory.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pack_revisionHistory.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pages.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pages.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pages.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pdsc_apis_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_apis_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_apis_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pdsc_boards_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_boards_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_boards_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pdsc_components_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_components_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_components_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pdsc_conditions_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_conditions_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_conditions_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pdsc_devices_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_devices_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_devices_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pdsc_examples_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_examples_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_examples_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pdsc_family_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_family_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_family_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pdsc_generators_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_generators_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_generators_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/pdsc_package_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_package_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/pdsc_package_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/printComponentTabs.js",
    "content": "var strgURL =   location.pathname;                      // path of current component\n\n// constuctor for the array of objects\nfunction tabElement(id, folderName, tabTxt )  {\n\tthis.id = id;                                       // elementID as needed in html; \n\tthis.folderName = folderName;                       // folder name of the component \n    this.tabTxt = tabTxt;                               // Text displayed as menu on the web\n\tthis.currentListItem = '<li id=\"' + this.id + '\" class=\"current\"> <a href=\"../..' + this.folderName + 'index.html\"><span>' + this.tabTxt + '</span></a></li>';\n\tthis.listItem = '<li id=\"' + this.id + '\"> <a href=\"../..' + this.folderName + 'index.html\"><span>' + this.tabTxt + '</span></a></li>';\n};\n\n// array of objects\nvar arr = [];\n\n// fill array\n arr.push( new tabElement( \"GEN\",     \"/General/html/\",     \"General\")   );\n arr.push( new tabElement( \"CORE_A\",  \"/Core_A/html/\",      \"Core(A)\")   );\n arr.push( new tabElement( \"CORE_M\",  \"/Core/html/\",        \"Core(M)\")   );\n arr.push( new tabElement( \"DRV\",     \"/Driver/html/\",      \"Driver\")    );\n arr.push( new tabElement( \"DSP&ML\",  \"/DSP/html/\",         \"DSP\")       );\n arr.push( new tabElement( \"NN\",      \"/NN/html/\",          \"NN\")        );\n arr.push( new tabElement( \"RTOSv1\",  \"/RTOS/html/\",        \"RTOS v1\")   );\n arr.push( new tabElement( \"RTOSv2\",  \"/RTOS2/html/\",       \"RTOS v2\")   );\n arr.push( new tabElement( \"PACK\",    \"/Pack/html/\",        \"Pack\")      );\n arr.push( new tabElement( \"Build\",   \"/Build/html/\",       \"Build\")     );\n arr.push( new tabElement( \"SVD\",     \"/SVD/html/\",         \"SVD\")       );\n arr.push( new tabElement( \"DAP\",     \"/DAP/html/\",         \"DAP\")       );\n arr.push( new tabElement( \"ZONE\",    \"/Zone/html/\",        \"Zone\")      );\n \n// write tabs\n// called from the header file.\nfunction writeComponentTabs()  {\n  for ( var i=0; i < arr.length; i++ ) {\n    if (strgURL.search(arr[i].folderName) > 0) {                    // if this is the current folder\n      document.write(arr[i].currentListItem);                       // then print and hightlight the tab\n    } else {                                                      \n      document.write(arr[i].listItem);                              // else, print the tab\n    }                                                             \n  }\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/resize.js",
    "content": "var cookie_namespace = 'doxygen'; \nvar sidenav,navtree,content,header;\n\nfunction readCookie(cookie) \n{\n  var myCookie = cookie_namespace+\"_\"+cookie+\"=\";\n  if (document.cookie) \n  {\n    var index = document.cookie.indexOf(myCookie);\n    if (index != -1) \n    {\n      var valStart = index + myCookie.length;\n      var valEnd = document.cookie.indexOf(\";\", valStart);\n      if (valEnd == -1) \n      {\n        valEnd = document.cookie.length;\n      }\n      var val = document.cookie.substring(valStart, valEnd);\n      return val;\n    }\n  }\n  return 0;\n}\n\nfunction writeCookie(cookie, val, expiration) \n{\n  if (val==undefined) return;\n  if (expiration == null) \n  {\n    var date = new Date();\n    date.setTime(date.getTime()+(10*365*24*60*60*1000)); // default expiration is one week\n    expiration = date.toGMTString();\n  }\n  document.cookie = cookie_namespace + \"_\" + cookie + \"=\" + val + \"; expires=\" + expiration+\"; path=/\";\n}\n \nfunction resizeWidth() \n{\n  var windowWidth = $(window).width() + \"px\";\n  var sidenavWidth = $(sidenav).outerWidth();\n  content.css({marginLeft:parseInt(sidenavWidth)+\"px\"}); \n  writeCookie('width',sidenavWidth, null);\n}\n\nfunction restoreWidth(navWidth)\n{\n  var windowWidth = $(window).width() + \"px\";\n  content.css({marginLeft:parseInt(navWidth)+6+\"px\"});\n  sidenav.css({width:navWidth + \"px\"});\n}\n\nfunction resizeHeight() \n{\n  var headerHeight = header.outerHeight();\n  var footerHeight = footer.outerHeight();\n  var windowHeight = $(window).height() - headerHeight - footerHeight;\n  content.css({height:windowHeight + \"px\"});\n  navtree.css({height:windowHeight + \"px\"});\n  sidenav.css({height:windowHeight + \"px\",top: headerHeight+\"px\"});\n}\n\nfunction initResizable()\n{\n  header  = $(\"#top\");\n  sidenav = $(\"#side-nav\");\n  content = $(\"#doc-content\");\n  navtree = $(\"#nav-tree\");\n  footer  = $(\"#nav-path\");\n  $(\".side-nav-resizable\").resizable({resize: function(e, ui) { resizeWidth(); } });\n  $(window).resize(function() { resizeHeight(); });\n  var width = readCookie('width');\n  if (width) { restoreWidth(width); } else { resizeWidth(); }\n  resizeHeight();\n  var url = location.href;\n  var i=url.indexOf(\"#\");\n  if (i>=0) window.location.hash=url.substr(i);\n  var _preventDefault = function(evt) { evt.preventDefault(); };\n  $(\"#splitbar\").bind(\"dragstart\", _preventDefault).bind(\"selectstart\", _preventDefault);\n  $(document).bind('touchmove',function(e){\n    var device = navigator.userAgent.toLowerCase();\n    var ios = device.match(/(iphone|ipod|ipad)/);\n    if (ios) {\n      try {\n        var target = e.target;\n        while (target) {\n          if ($(target).css('-webkit-overflow-scrolling')=='touch') return;\n          target = target.parentNode;\n        }\n        e.preventDefault();\n      } catch(err) {\n        e.preventDefault();\n      }\n    }\n  });\n}\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/sdf_pg.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the corresponding Open-CMSIS-Pack page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/sdf_pg.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/sdf_pg.html\">here</a> or try to find corresponding topic described in <a href=\"https://www.open-cmsis-pack.org\">Open-CMSIS-Pack resources</a>.\n\n</body>\n</html>"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/search/nomatches.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html><head><title></title>\n<meta http-equiv=\"Content-Type\" content=\"text/xhtml;charset=UTF-8\"/>\n<link rel=\"stylesheet\" type=\"text/css\" href=\"search.css\"/>\n<script type=\"text/javascript\" src=\"search.js\"></script>\n</head>\n<body class=\"SRPage\">\n<div id=\"SRIndex\">\n<div class=\"SRStatus\" id=\"NoMatches\">No Matches</div>\n</div>\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/search/search.css",
    "content": "/*---------------- Search Box */\n\n#FSearchBox {\n    float: left;\n}\n\n#searchli {\n    float: right;\n    display: block;\n    width: 170px;\n    height: 24px;\n}\n\n#MSearchBox {\n    white-space : nowrap;\n    position: absolute;\n    float: none;\n    display: inline;\n    margin-top: 3px;\n    right: 0px;\n    width: 170px;\n    z-index: 102;\n}\n\n#MSearchBox .left\n{\n    display:block;\n    position:absolute;\n    left:10px;\n    width:20px;\n    height:19px;\n    background:url('search_l.png') no-repeat;\n    background-position:right;\n}\n\n#MSearchSelect {\n    display:block;\n    position:absolute;\n    width:20px;\n    height:19px;\n}\n\n.left #MSearchSelect {\n    left:4px;\n}\n\n.right #MSearchSelect {\n    right:5px;\n}\n\n#MSearchField {\n    display:block;\n    position:absolute;\n    height:19px;\n    background:url('search_m.png') repeat-x;\n    border:none;\n    width:116px;\n    margin-left:20px;\n    padding-left:4px;\n    color: #909090;\n    outline: none;\n    font: 9pt Arial, Verdana, sans-serif;\n}\n\n#FSearchBox #MSearchField {\n    margin-left:15px;\n}\n\n#MSearchBox .right {\n    display:block;\n    position:absolute;\n    right:10px;\n    top:0px;\n    width:20px;\n    height:19px;\n    background:url('search_r.png') no-repeat;\n    background-position:left;\n}\n\n#MSearchClose {\n    display: none;\n    position: absolute;\n    top: 4px;\n    background : none;\n    border: none;\n    margin: 0px 4px 0px 0px;\n    padding: 0px 0px;\n    outline: none;\n}\n\n.left #MSearchClose {\n    left: 6px;\n}\n\n.right #MSearchClose {\n    right: 2px;\n}\n\n.MSearchBoxActive #MSearchField {\n    color: #000000;\n}\n\n/*---------------- Search filter selection */\n\n#MSearchSelectWindow {\n    display: none;\n    position: absolute;\n    left: 0; top: 0;\n    border: 1px solid #90A5CE;\n    background-color: #F9FAFC;\n    z-index: 1;\n    padding-top: 4px;\n    padding-bottom: 4px;\n    -moz-border-radius: 4px;\n    -webkit-border-top-left-radius: 4px;\n    -webkit-border-top-right-radius: 4px;\n    -webkit-border-bottom-left-radius: 4px;\n    -webkit-border-bottom-right-radius: 4px;\n    -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);\n}\n\n.SelectItem {\n    font: 8pt Arial, Verdana, sans-serif;\n    padding-left:  2px;\n    padding-right: 12px;\n    border: 0px;\n}\n\nspan.SelectionMark {\n    margin-right: 4px;\n    font-family: monospace;\n    outline-style: none;\n    text-decoration: none;\n}\n\na.SelectItem {\n    display: block;\n    outline-style: none;\n    color: #000000; \n    text-decoration: none;\n    padding-left:   6px;\n    padding-right: 12px;\n}\n\na.SelectItem:focus,\na.SelectItem:active {\n    color: #000000; \n    outline-style: none;\n    text-decoration: none;\n}\n\na.SelectItem:hover {\n    color: #FFFFFF;\n    background-color: #3D578C;\n    outline-style: none;\n    text-decoration: none;\n    cursor: pointer;\n    display: block;\n}\n\n/*---------------- Search results window */\n\niframe#MSearchResults {\n    width: 60ex;\n    height: 15em;\n}\n\n#MSearchResultsWindow {\n    display: none;\n    position: absolute;\n    left: 0; top: 0;\n    border: 1px solid #000;\n    background-color: #EEF1F7;\n}\n\n/* ----------------------------------- */\n\n\n#SRIndex {\n    clear:both; \n    padding-bottom: 15px;\n}\n\n.SREntry {\n    font-size: 10pt;\n    padding-left: 1ex;\n}\n\n.SRPage .SREntry {\n    font-size: 8pt;\n    padding: 1px 5px;\n}\n\nbody.SRPage {\n    margin: 5px 2px;\n}\n\n.SRChildren {\n    padding-left: 3ex; padding-bottom: .5em \n}\n\n.SRPage .SRChildren {\n    display: none;\n}\n\n.SRSymbol {\n    font-weight: bold; \n    color: #425E97;\n    font-family: Arial, Verdana, sans-serif;\n    text-decoration: none;\n    outline: none;\n}\n\na.SRScope {\n    display: block;\n    color: #425E97; \n    font-family: Arial, Verdana, sans-serif;\n    text-decoration: none;\n    outline: none;\n}\n\na.SRSymbol:focus, a.SRSymbol:active,\na.SRScope:focus, a.SRScope:active {\n    text-decoration: underline;\n}\n\n.SRPage .SRStatus {\n    padding: 2px 5px;\n    font-size: 8pt;\n    font-style: italic;\n}\n\n.SRResult {\n    display: none;\n}\n\nDIV.searchresults {\n    margin-left: 10px;\n    margin-right: 10px;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/search/search.js",
    "content": "// Search script generated by doxygen\n// Copyright (C) 2009 by Dimitri van Heesch.\n\n// The code in this file is loosly based on main.js, part of Natural Docs,\n// which is Copyright (C) 2003-2008 Greg Valure\n// Natural Docs is licensed under the GPL.\n\nvar indexSectionsWithContent =\n{\n  0: \"abcdfioprsuxz\",\n  1: \"abcdfioprsuxz\"\n};\n\nvar indexSectionNames =\n{\n  0: \"all\",\n  1: \"pages\"\n};\n\nfunction convertToId(search)\n{\n  var result = '';\n  for (i=0;i<search.length;i++)\n  {\n    var c = search.charAt(i);\n    var cn = c.charCodeAt(0);\n    if (c.match(/[a-z0-9\\u0080-\\uFFFF]/))\n    {\n      result+=c;\n    }\n    else if (cn<16) \n    {\n      result+=\"_0\"+cn.toString(16);\n    }\n    else \n    {\n      result+=\"_\"+cn.toString(16);\n    }\n  }\n  return result;\n}\n\nfunction getXPos(item)\n{\n  var x = 0;\n  if (item.offsetWidth)\n  {\n    while (item && item!=document.body)\n    {\n      x   += item.offsetLeft;\n      item = item.offsetParent;\n    }\n  }\n  return x;\n}\n\nfunction getYPos(item)\n{\n  var y = 0;\n  if (item.offsetWidth)\n  {\n     while (item && item!=document.body)\n     {\n       y   += item.offsetTop;\n       item = item.offsetParent;\n     }\n  }\n  return y;\n}\n\n/* A class handling everything associated with the search panel.\n\n   Parameters:\n   name - The name of the global variable that will be \n          storing this instance.  Is needed to be able to set timeouts.\n   resultPath - path to use for external files\n*/\nfunction SearchBox(name, resultsPath, inFrame, label)\n{\n  if (!name || !resultsPath) {  alert(\"Missing parameters to SearchBox.\"); }\n   \n  // ---------- Instance variables\n  this.name                  = name;\n  this.resultsPath           = resultsPath;\n  this.keyTimeout            = 0;\n  this.keyTimeoutLength      = 500;\n  this.closeSelectionTimeout = 300;\n  this.lastSearchValue       = \"\";\n  this.lastResultsPage       = \"\";\n  this.hideTimeout           = 0;\n  this.searchIndex           = 0;\n  this.searchActive          = false;\n  this.insideFrame           = inFrame;\n  this.searchLabel           = label;\n\n  // ----------- DOM Elements\n\n  this.DOMSearchField = function()\n  {  return document.getElementById(\"MSearchField\");  }\n\n  this.DOMSearchSelect = function()\n  {  return document.getElementById(\"MSearchSelect\");  }\n\n  this.DOMSearchSelectWindow = function()\n  {  return document.getElementById(\"MSearchSelectWindow\");  }\n\n  this.DOMPopupSearchResults = function()\n  {  return document.getElementById(\"MSearchResults\");  }\n\n  this.DOMPopupSearchResultsWindow = function()\n  {  return document.getElementById(\"MSearchResultsWindow\");  }\n\n  this.DOMSearchClose = function()\n  {  return document.getElementById(\"MSearchClose\"); }\n\n  this.DOMSearchBox = function()\n  {  return document.getElementById(\"MSearchBox\");  }\n\n  // ------------ Event Handlers\n\n  // Called when focus is added or removed from the search field.\n  this.OnSearchFieldFocus = function(isActive)\n  {\n    this.Activate(isActive);\n  }\n\n  this.OnSearchSelectShow = function()\n  {\n    var searchSelectWindow = this.DOMSearchSelectWindow();\n    var searchField        = this.DOMSearchSelect();\n\n    if (this.insideFrame)\n    {\n      var left = getXPos(searchField);\n      var top  = getYPos(searchField);\n      left += searchField.offsetWidth + 6;\n      top += searchField.offsetHeight;\n\n      // show search selection popup\n      searchSelectWindow.style.display='block';\n      left -= searchSelectWindow.offsetWidth;\n      searchSelectWindow.style.left =  left + 'px';\n      searchSelectWindow.style.top  =  top  + 'px';\n    }\n    else\n    {\n      var left = getXPos(searchField);\n      var top  = getYPos(searchField);\n      top += searchField.offsetHeight;\n\n      // show search selection popup\n      searchSelectWindow.style.display='block';\n      searchSelectWindow.style.left =  left + 'px';\n      searchSelectWindow.style.top  =  top  + 'px';\n    }\n\n    // stop selection hide timer\n    if (this.hideTimeout) \n    {\n      clearTimeout(this.hideTimeout);\n      this.hideTimeout=0;\n    }\n    return false; // to avoid \"image drag\" default event\n  }\n\n  this.OnSearchSelectHide = function()\n  {\n    this.hideTimeout = setTimeout(this.name +\".CloseSelectionWindow()\",\n                                  this.closeSelectionTimeout);\n  }\n\n  // Called when the content of the search field is changed.\n  this.OnSearchFieldChange = function(evt)\n  {\n    if (this.keyTimeout) // kill running timer\n    {\n      clearTimeout(this.keyTimeout);\n      this.keyTimeout = 0;\n    }\n\n    var e  = (evt) ? evt : window.event; // for IE\n    if (e.keyCode==40 || e.keyCode==13)\n    {\n      if (e.shiftKey==1)\n      {\n        this.OnSearchSelectShow();\n        var win=this.DOMSearchSelectWindow(); \n        for (i=0;i<win.childNodes.length;i++)\n        {\n          var child = win.childNodes[i]; // get span within a\n          if (child.className=='SelectItem')\n          {\n            child.focus();\n            return;\n          }\n        }\n        return;\n      }\n      else if (window.frames.MSearchResults.searchResults)\n      {\n        var elem = window.frames.MSearchResults.searchResults.NavNext(0);\n        if (elem) elem.focus();\n      }\n    }\n    else if (e.keyCode==27) // Escape out of the search field\n    {\n      this.DOMSearchField().blur();\n      this.DOMPopupSearchResultsWindow().style.display = 'none';\n      this.DOMSearchClose().style.display = 'none';\n      this.lastSearchValue = '';\n      this.Activate(false);\n      return;\n    }\n\n    // strip whitespaces\n    var searchValue = this.DOMSearchField().value.replace(/ +/g, \"\");\n\n    if (searchValue != this.lastSearchValue) // search value has changed\n    {\n      if (searchValue != \"\") // non-empty search\n      {\n        // set timer for search update\n        this.keyTimeout = setTimeout(this.name + '.Search()',\n                                     this.keyTimeoutLength);\n      }\n      else // empty search field\n      {\n        this.DOMPopupSearchResultsWindow().style.display = 'none';\n        this.DOMSearchClose().style.display = 'none';\n        this.lastSearchValue = '';\n      }\n    }\n  }\n\n  this.SelectItemCount = function(id)\n  {\n    var count=0;\n    var win=this.DOMSearchSelectWindow(); \n    for (i=0;i<win.childNodes.length;i++)\n    {\n      var child = win.childNodes[i]; // get span within a\n      if (child.className=='SelectItem')\n      {\n        count++;\n      }\n    }\n    return count;\n  }\n\n  this.SelectItemSet = function(id)\n  {\n    var i,j=0;\n    var win=this.DOMSearchSelectWindow(); \n    for (i=0;i<win.childNodes.length;i++)\n    {\n      var child = win.childNodes[i]; // get span within a\n      if (child.className=='SelectItem')\n      {\n        var node = child.firstChild;\n        if (j==id)\n        {\n          node.innerHTML='&#8226;';\n        }\n        else\n        {\n          node.innerHTML='&#160;';\n        }\n        j++;\n      }\n    }\n  }\n\n  // Called when an search filter selection is made.\n  // set item with index id as the active item\n  this.OnSelectItem = function(id)\n  {\n    this.searchIndex = id;\n    this.SelectItemSet(id);\n    var searchValue = this.DOMSearchField().value.replace(/ +/g, \"\");\n    if (searchValue!=\"\" && this.searchActive) // something was found -> do a search\n    {\n      this.Search();\n    }\n  }\n\n  this.OnSearchSelectKey = function(evt)\n  {\n    var e = (evt) ? evt : window.event; // for IE\n    if (e.keyCode==40 && this.searchIndex<this.SelectItemCount()) // Down\n    {\n      this.searchIndex++;\n      this.OnSelectItem(this.searchIndex);\n    }\n    else if (e.keyCode==38 && this.searchIndex>0) // Up\n    {\n      this.searchIndex--;\n      this.OnSelectItem(this.searchIndex);\n    }\n    else if (e.keyCode==13 || e.keyCode==27)\n    {\n      this.OnSelectItem(this.searchIndex);\n      this.CloseSelectionWindow();\n      this.DOMSearchField().focus();\n    }\n    return false;\n  }\n\n  // --------- Actions\n\n  // Closes the results window.\n  this.CloseResultsWindow = function()\n  {\n    this.DOMPopupSearchResultsWindow().style.display = 'none';\n    this.DOMSearchClose().style.display = 'none';\n    this.Activate(false);\n  }\n\n  this.CloseSelectionWindow = function()\n  {\n    this.DOMSearchSelectWindow().style.display = 'none';\n  }\n\n  // Performs a search.\n  this.Search = function()\n  {\n    this.keyTimeout = 0;\n\n    // strip leading whitespace\n    var searchValue = this.DOMSearchField().value.replace(/^ +/, \"\");\n\n    var code = searchValue.toLowerCase().charCodeAt(0);\n    var idxChar = searchValue.substr(0, 1).toLowerCase();\n    if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair\n    {\n      idxChar = searchValue.substr(0, 2);\n    }\n\n    var resultsPage;\n    var resultsPageWithSearch;\n    var hasResultsPage;\n\n    var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar);\n    if (idx!=-1)\n    {\n       var hexCode=idx.toString(16);\n       resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html';\n       resultsPageWithSearch = resultsPage+'?'+escape(searchValue);\n       hasResultsPage = true;\n    }\n    else // nothing available for this search term\n    {\n       resultsPage = this.resultsPath + '/nomatches.html';\n       resultsPageWithSearch = resultsPage;\n       hasResultsPage = false;\n    }\n\n    window.frames.MSearchResults.location = resultsPageWithSearch;  \n    var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow();\n\n    if (domPopupSearchResultsWindow.style.display!='block')\n    {\n       var domSearchBox = this.DOMSearchBox();\n       this.DOMSearchClose().style.display = 'inline';\n       if (this.insideFrame)\n       {\n         var domPopupSearchResults = this.DOMPopupSearchResults();\n         domPopupSearchResultsWindow.style.position = 'relative';\n         domPopupSearchResultsWindow.style.display  = 'block';\n         var width = document.body.clientWidth - 8; // the -8 is for IE :-(\n         domPopupSearchResultsWindow.style.width    = width + 'px';\n         domPopupSearchResults.style.width          = width + 'px';\n       }\n       else\n       {\n         var domPopupSearchResults = this.DOMPopupSearchResults();\n         var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth;\n         var top  = getYPos(domSearchBox) + 20;  // domSearchBox.offsetHeight + 1;\n         domPopupSearchResultsWindow.style.display = 'block';\n         left -= domPopupSearchResults.offsetWidth;\n         domPopupSearchResultsWindow.style.top     = top  + 'px';\n         domPopupSearchResultsWindow.style.left    = left + 'px';\n       }\n    }\n\n    this.lastSearchValue = searchValue;\n    this.lastResultsPage = resultsPage;\n  }\n\n  // -------- Activation Functions\n\n  // Activates or deactivates the search panel, resetting things to \n  // their default values if necessary. \n  this.Activate = function(isActive)\n  {\n    if (isActive || // open it\n        this.DOMPopupSearchResultsWindow().style.display == 'block' \n       )\n    {\n      this.DOMSearchBox().className = 'MSearchBoxActive';\n\n      var searchField = this.DOMSearchField();\n\n      if (searchField.value == this.searchLabel) // clear \"Search\" term upon entry\n      {  \n        searchField.value = '';  \n        this.searchActive = true;\n      }\n    }\n    else if (!isActive) // directly remove the panel\n    {\n      this.DOMSearchBox().className = 'MSearchBoxInactive';\n      this.DOMSearchField().value   = this.searchLabel;\n      this.searchActive             = false;\n      this.lastSearchValue          = ''\n      this.lastResultsPage          = '';\n    }\n  }\n}\n\n// -----------------------------------------------------------------------\n\n// The class that handles everything on the search results page.\nfunction SearchResults(name)\n{\n    // The number of matches from the last run of <Search()>.\n    this.lastMatchCount = 0;\n    this.lastKey = 0;\n    this.repeatOn = false;\n\n    // Toggles the visibility of the passed element ID.\n    this.FindChildElement = function(id)\n    {\n      var parentElement = document.getElementById(id);\n      var element = parentElement.firstChild;\n\n      while (element && element!=parentElement)\n      {\n        if (element.nodeName == 'DIV' && element.className == 'SRChildren')\n        {\n          return element;\n        }\n\n        if (element.nodeName == 'DIV' && element.hasChildNodes())\n        {  \n           element = element.firstChild;  \n        }\n        else if (element.nextSibling)\n        {  \n           element = element.nextSibling;  \n        }\n        else\n        {\n          do\n          {\n            element = element.parentNode;\n          }\n          while (element && element!=parentElement && !element.nextSibling);\n\n          if (element && element!=parentElement)\n          {  \n            element = element.nextSibling;  \n          }\n        }\n      }\n    }\n\n    this.Toggle = function(id)\n    {\n      var element = this.FindChildElement(id);\n      if (element)\n      {\n        if (element.style.display == 'block')\n        {\n          element.style.display = 'none';\n        }\n        else\n        {\n          element.style.display = 'block';\n        }\n      }\n    }\n\n    // Searches for the passed string.  If there is no parameter,\n    // it takes it from the URL query.\n    //\n    // Always returns true, since other documents may try to call it\n    // and that may or may not be possible.\n    this.Search = function(search)\n    {\n      if (!search) // get search word from URL\n      {\n        search = window.location.search;\n        search = search.substring(1);  // Remove the leading '?'\n        search = unescape(search);\n      }\n\n      search = search.replace(/^ +/, \"\"); // strip leading spaces\n      search = search.replace(/ +$/, \"\"); // strip trailing spaces\n      search = search.toLowerCase();\n      search = convertToId(search);\n\n      var resultRows = document.getElementsByTagName(\"div\");\n      var matches = 0;\n\n      var i = 0;\n      while (i < resultRows.length)\n      {\n        var row = resultRows.item(i);\n        if (row.className == \"SRResult\")\n        {\n          var rowMatchName = row.id.toLowerCase();\n          rowMatchName = rowMatchName.replace(/^sr\\d*_/, ''); // strip 'sr123_'\n\n          if (search.length<=rowMatchName.length && \n             rowMatchName.substr(0, search.length)==search)\n          {\n            row.style.display = 'block';\n            matches++;\n          }\n          else\n          {\n            row.style.display = 'none';\n          }\n        }\n        i++;\n      }\n      document.getElementById(\"Searching\").style.display='none';\n      if (matches == 0) // no results\n      {\n        document.getElementById(\"NoMatches\").style.display='block';\n      }\n      else // at least one result\n      {\n        document.getElementById(\"NoMatches\").style.display='none';\n      }\n      this.lastMatchCount = matches;\n      return true;\n    }\n\n    // return the first item with index index or higher that is visible\n    this.NavNext = function(index)\n    {\n      var focusItem;\n      while (1)\n      {\n        var focusName = 'Item'+index;\n        focusItem = document.getElementById(focusName);\n        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')\n        {\n          break;\n        }\n        else if (!focusItem) // last element\n        {\n          break;\n        }\n        focusItem=null;\n        index++;\n      }\n      return focusItem;\n    }\n\n    this.NavPrev = function(index)\n    {\n      var focusItem;\n      while (1)\n      {\n        var focusName = 'Item'+index;\n        focusItem = document.getElementById(focusName);\n        if (focusItem && focusItem.parentNode.parentNode.style.display=='block')\n        {\n          break;\n        }\n        else if (!focusItem) // last element\n        {\n          break;\n        }\n        focusItem=null;\n        index--;\n      }\n      return focusItem;\n    }\n\n    this.ProcessKeys = function(e)\n    {\n      if (e.type == \"keydown\") \n      {\n        this.repeatOn = false;\n        this.lastKey = e.keyCode;\n      }\n      else if (e.type == \"keypress\")\n      {\n        if (!this.repeatOn)\n        {\n          if (this.lastKey) this.repeatOn = true;\n          return false; // ignore first keypress after keydown\n        }\n      }\n      else if (e.type == \"keyup\")\n      {\n        this.lastKey = 0;\n        this.repeatOn = false;\n      }\n      return this.lastKey!=0;\n    }\n\n    this.Nav = function(evt,itemIndex) \n    {\n      var e  = (evt) ? evt : window.event; // for IE\n      if (e.keyCode==13) return true;\n      if (!this.ProcessKeys(e)) return false;\n\n      if (this.lastKey==38) // Up\n      {\n        var newIndex = itemIndex-1;\n        var focusItem = this.NavPrev(newIndex);\n        if (focusItem)\n        {\n          var child = this.FindChildElement(focusItem.parentNode.parentNode.id);\n          if (child && child.style.display == 'block') // children visible\n          { \n            var n=0;\n            var tmpElem;\n            while (1) // search for last child\n            {\n              tmpElem = document.getElementById('Item'+newIndex+'_c'+n);\n              if (tmpElem)\n              {\n                focusItem = tmpElem;\n              }\n              else // found it!\n              {\n                break;\n              }\n              n++;\n            }\n          }\n        }\n        if (focusItem)\n        {\n          focusItem.focus();\n        }\n        else // return focus to search field\n        {\n           parent.document.getElementById(\"MSearchField\").focus();\n        }\n      }\n      else if (this.lastKey==40) // Down\n      {\n        var newIndex = itemIndex+1;\n        var focusItem;\n        var item = document.getElementById('Item'+itemIndex);\n        var elem = this.FindChildElement(item.parentNode.parentNode.id);\n        if (elem && elem.style.display == 'block') // children visible\n        {\n          focusItem = document.getElementById('Item'+itemIndex+'_c0');\n        }\n        if (!focusItem) focusItem = this.NavNext(newIndex);\n        if (focusItem)  focusItem.focus();\n      }\n      else if (this.lastKey==39) // Right\n      {\n        var item = document.getElementById('Item'+itemIndex);\n        var elem = this.FindChildElement(item.parentNode.parentNode.id);\n        if (elem) elem.style.display = 'block';\n      }\n      else if (this.lastKey==37) // Left\n      {\n        var item = document.getElementById('Item'+itemIndex);\n        var elem = this.FindChildElement(item.parentNode.parentNode.id);\n        if (elem) elem.style.display = 'none';\n      }\n      else if (this.lastKey==27) // Escape\n      {\n        parent.searchBox.CloseResultsWindow();\n        parent.document.getElementById(\"MSearchField\").focus();\n      }\n      else if (this.lastKey==13) // Enter\n      {\n        return true;\n      }\n      return false;\n    }\n\n    this.NavChild = function(evt,itemIndex,childIndex)\n    {\n      var e  = (evt) ? evt : window.event; // for IE\n      if (e.keyCode==13) return true;\n      if (!this.ProcessKeys(e)) return false;\n\n      if (this.lastKey==38) // Up\n      {\n        if (childIndex>0)\n        {\n          var newIndex = childIndex-1;\n          document.getElementById('Item'+itemIndex+'_c'+newIndex).focus();\n        }\n        else // already at first child, jump to parent\n        {\n          document.getElementById('Item'+itemIndex).focus();\n        }\n      }\n      else if (this.lastKey==40) // Down\n      {\n        var newIndex = childIndex+1;\n        var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex);\n        if (!elem) // last child, jump to parent next parent\n        {\n          elem = this.NavNext(itemIndex+1);\n        }\n        if (elem)\n        {\n          elem.focus();\n        } \n      }\n      else if (this.lastKey==27) // Escape\n      {\n        parent.searchBox.CloseResultsWindow();\n        parent.document.getElementById(\"MSearchField\").focus();\n      }\n      else if (this.lastKey==13) // Enter\n      {\n        return true;\n      }\n      return false;\n    }\n}\n\nfunction setKeyActions(elem,action)\n{\n  elem.setAttribute('onkeydown',action);\n  elem.setAttribute('onkeypress',action);\n  elem.setAttribute('onkeyup',action);\n}\n\nfunction setClassAttr(elem,attr)\n{\n  elem.setAttribute('class',attr);\n  elem.setAttribute('className',attr);\n}\n\nfunction createResults()\n{\n  var results = document.getElementById(\"SRResults\");\n  for (var e=0; e<searchData.length; e++)\n  {\n    var id = searchData[e][0];\n    var srResult = document.createElement('div');\n    srResult.setAttribute('id','SR_'+id);\n    setClassAttr(srResult,'SRResult');\n    var srEntry = document.createElement('div');\n    setClassAttr(srEntry,'SREntry');\n    var srLink = document.createElement('a');\n    srLink.setAttribute('id','Item'+e);\n    setKeyActions(srLink,'return searchResults.Nav(event,'+e+')');\n    setClassAttr(srLink,'SRSymbol');\n    srLink.innerHTML = searchData[e][1][0];\n    srEntry.appendChild(srLink);\n    if (searchData[e][1].length==2) // single result\n    {\n      srLink.setAttribute('href',searchData[e][1][1][0]);\n      if (searchData[e][1][1][1])\n      {\n       srLink.setAttribute('target','_parent');\n      }\n      var srScope = document.createElement('span');\n      setClassAttr(srScope,'SRScope');\n      srScope.innerHTML = searchData[e][1][1][2];\n      srEntry.appendChild(srScope);\n    }\n    else // multiple results\n    {\n      srLink.setAttribute('href','javascript:searchResults.Toggle(\"SR_'+id+'\")');\n      var srChildren = document.createElement('div');\n      setClassAttr(srChildren,'SRChildren');\n      for (var c=0; c<searchData[e][1].length-1; c++)\n      {\n        var srChild = document.createElement('a');\n        srChild.setAttribute('id','Item'+e+'_c'+c);\n        setKeyActions(srChild,'return searchResults.NavChild(event,'+e+','+c+')');\n        setClassAttr(srChild,'SRScope');\n        srChild.setAttribute('href',searchData[e][1][c+1][0]);\n        if (searchData[e][1][c+1][1])\n        {\n         srChild.setAttribute('target','_parent');\n        }\n        srChild.innerHTML = searchData[e][1][c+1][2];\n        srChildren.appendChild(srChild);\n      }\n      srEntry.appendChild(srChildren);\n    }\n    srResult.appendChild(srEntry);\n    results.appendChild(srResult);\n  }\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Pack/html/tabs.css",
    "content": ".tabs, .tabs1, .tabs2, .tabs3 {\n    background-image: url('tab_b.png');\n    width: 100%;\n    z-index: 101;\n    font-size: 10px;\n}\n\n.tabs1 {\n    background-image: url('tab_topnav.png');\n    font-size: 12px;\n}\n\n.tabs2 {\n    font-size: 10px;\n}\n.tabs3 {\n    font-size: 9px;\n}\n\n.tablist {\n    margin: 0;\n    padding: 0;\n    display: table;\n    line-height: 24px;\n}\n\n.tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_b.png');\n    list-style: none;\n}\n\n.tabs1 .tablist li {\n    float: left;\n    display: table-cell;\n    background-image: url('tab_topnav.png');\n    list-style: none;\n}\n\n.tablist a {\n    display: block;\n    padding: 0 20px;\n    font-weight: bold;\n    background-image:url('tab_s.png');\n    background-repeat:no-repeat;\n    background-position:right;\n    color: #283A5D;\n    text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);\n    text-decoration: none;\n    outline: none;\n}\n\n.tabs3 .tablist a {\n    padding: 0 10px;\n}\n\n.tablist a:hover {\n    background-image: url('tab_h.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n    text-decoration: none;\n}\n\n.tablist li.current a {\n    background-image: url('tab_a.png');\n    background-repeat:repeat-x;\n    color: #fff;\n    text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS/rtos.dxy",
    "content": "# Doxyfile 1.8.6\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a double hash (##) is considered a comment and is placed in\n# front of the TAG it is preceding.\n#\n# All text after a single hash (#) is considered a comment and will be ignored.\n# The format is:\n# TAG = value [value, ...]\n# For lists, items can also be appended using:\n# TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\\\" \\\").\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the config file\n# that follow. The default is UTF-8 which is also the encoding used for all text\n# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv\n# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv\n# for the list of possible encodings.\n# The default value is: UTF-8.\n\nDOXYFILE_ENCODING      = UTF-8\n\n# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by\n# double-quotes, unless you are using Doxywizard) that should identify the\n# project for which the documentation is generated. This name is used in the\n# title of most generated pages and in a few other places.\n# The default value is: My Project.\n\nPROJECT_NAME           = \"CMSIS-RTOS\"\n\n# The PROJECT_NUMBER tag can be used to enter a project or revision number. This\n# could be handy for archiving the generated documentation or if some version\n# control system is used.\n\nPROJECT_NUMBER         = \"Version 1.03\"\n\n# Using the PROJECT_BRIEF tag one can provide an optional one line description\n# for a project that appears at the top of each page and should give viewer a\n# quick idea about the purpose of the project. Keep the description short.\n\nPROJECT_BRIEF          = \"Real-Time Operating System: API and RTX Reference Implementation.\"\n\n# With the PROJECT_LOGO tag one can specify an logo or icon that is included in\n# the documentation. The maximum height of the logo should not exceed 55 pixels\n# and the maximum width should not exceed 200 pixels. Doxygen will copy the logo\n# to the output directory.\n\nPROJECT_LOGO           = ../Doxygen_Templates/CMSIS_Logo_Final.png\n\n# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path\n# into which the generated documentation will be written. If a relative path is\n# entered, it will be relative to the location where doxygen was started. If\n# left blank the current directory will be used.\n\nOUTPUT_DIRECTORY       = ../../Documentation/RTOS\n\n# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-\n# directories (in 2 levels) under the output directory of each output format and\n# will distribute the generated files over these directories. Enabling this\n# option can be useful when feeding doxygen a huge amount of source files, where\n# putting all generated files in the same directory would otherwise causes\n# performance problems for the file system.\n# The default value is: NO.\n\nCREATE_SUBDIRS         = NO\n\n# The OUTPUT_LANGUAGE tag is used to specify the language in which all\n# documentation generated by doxygen is written. Doxygen will use this\n# information to generate all constant output in the proper language.\n# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,\n# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),\n# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,\n# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),\n# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,\n# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,\n# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,\n# Ukrainian and Vietnamese.\n# The default value is: English.\n\nOUTPUT_LANGUAGE        = English\n\n# If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member\n# descriptions after the members that are listed in the file and class\n# documentation (similar to Javadoc). Set to NO to disable this.\n# The default value is: YES.\n\nBRIEF_MEMBER_DESC      = YES\n\n# If the REPEAT_BRIEF tag is set to YES doxygen will prepend the brief\n# description of a member or function before the detailed description\n#\n# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the\n# brief descriptions will be completely suppressed.\n# The default value is: YES.\n\nREPEAT_BRIEF           = NO\n\n# This tag implements a quasi-intelligent brief description abbreviator that is\n# used to form the text in various listings. Each string in this list, if found\n# as the leading text of the brief description, will be stripped from the text\n# and the result, after processing the whole list, is used as the annotated\n# text. Otherwise, the brief description is used as-is. If left blank, the\n# following values are used ($name is automatically replaced with the name of\n# the entity):The $name class, The $name widget, The $name file, is, provides,\n# specifies, contains, represents, a, an and the.\n\nABBREVIATE_BRIEF       = \"The $name class\" \\\n                         \"The $name widget\" \\\n                         \"The $name file\" \\\n                         is \\\n                         provides \\\n                         specifies \\\n                         contains \\\n                         represents \\\n                         a \\\n                         an \\\n                         the\n\n# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then\n# doxygen will generate a detailed section even if there is only a brief\n# description.\n# The default value is: NO.\n\nALWAYS_DETAILED_SEC    = NO\n\n# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all\n# inherited members of a class in the documentation of that class as if those\n# members were ordinary class members. Constructors, destructors and assignment\n# operators of the base classes will not be shown.\n# The default value is: NO.\n\nINLINE_INHERITED_MEMB  = NO\n\n# If the FULL_PATH_NAMES tag is set to YES doxygen will prepend the full path\n# before files name in the file list and in the header files. If set to NO the\n# shortest path that makes the file name unique will be used\n# The default value is: YES.\n\nFULL_PATH_NAMES        = NO\n\n# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.\n# Stripping is only done if one of the specified strings matches the left-hand\n# part of the path. The tag can be used to show relative paths in the file list.\n# If left blank the directory from which doxygen is run is used as the path to\n# strip.\n#\n# Note that you can specify absolute paths here, but also relative paths, which\n# will be relative from the directory where doxygen is started.\n# This tag requires that the tag FULL_PATH_NAMES is set to YES.\n\nSTRIP_FROM_PATH        = \n\n# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the\n# path mentioned in the documentation of a class, which tells the reader which\n# header file to include in order to use a class. If left blank only the name of\n# the header file containing the class definition is used. Otherwise one should\n# specify the list of include paths that are normally passed to the compiler\n# using the -I flag.\n\nSTRIP_FROM_INC_PATH    = \n\n# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but\n# less readable) file names. This can be useful is your file systems doesn't\n# support long names like on DOS, Mac, or CD-ROM.\n# The default value is: NO.\n\nSHORT_NAMES            = NO\n\n# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the\n# first line (until the first dot) of a Javadoc-style comment as the brief\n# description. If set to NO, the Javadoc-style will behave just like regular Qt-\n# style comments (thus requiring an explicit @brief command for a brief\n# description.)\n# The default value is: NO.\n\nJAVADOC_AUTOBRIEF      = NO\n\n# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first\n# line (until the first dot) of a Qt-style comment as the brief description. If\n# set to NO, the Qt-style will behave just like regular Qt-style comments (thus\n# requiring an explicit \\brief command for a brief description.)\n# The default value is: NO.\n\nQT_AUTOBRIEF           = NO\n\n# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a\n# multi-line C++ special comment block (i.e. a block of //! or /// comments) as\n# a brief description. This used to be the default behavior. The new default is\n# to treat a multi-line C++ comment block as a detailed description. Set this\n# tag to YES if you prefer the old behavior instead.\n#\n# Note that setting this tag to YES also means that rational rose comments are\n# not recognized any more.\n# The default value is: NO.\n\nMULTILINE_CPP_IS_BRIEF = YES\n\n# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the\n# documentation from any documented member that it re-implements.\n# The default value is: YES.\n\nINHERIT_DOCS           = NO\n\n# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a\n# new page for each member. If set to NO, the documentation of a member will be\n# part of the file/class/namespace that contains it.\n# The default value is: NO.\n\nSEPARATE_MEMBER_PAGES  = NO\n\n# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen\n# uses this value to replace tabs by spaces in code fragments.\n# Minimum value: 1, maximum value: 16, default value: 4.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that act as commands in\n# the documentation. An alias has the form:\n# name=value\n# For example adding\n# \"sideeffect=@par Side Effects:\\n\"\n# will allow you to put the command \\sideeffect (or @sideeffect) in the\n# documentation, which will result in a user-defined paragraph with heading\n# \"Side Effects:\". You can put \\n's in the value part of an alias to insert\n# newlines.\n\nALIASES                = \n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding \"class=itcl::class\"\n# will allow you to use the command class in the itcl::class meaning.\n\nTCL_SUBST              = \n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources\n# only. Doxygen will then generate output that is more tailored for C. For\n# instance, some of the names that are used will be different. The list of all\n# members will be omitted, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_FOR_C  = YES\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or\n# Python sources only. Doxygen will then generate output that is more tailored\n# for that language. For instance, namespaces will be presented as packages,\n# qualified scopes will look different, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources. Doxygen will then generate output that is tailored for Fortran.\n# The default value is: NO.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for VHDL.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given\n# extension. Doxygen has a built-in mapping, but you can override or extend it\n# using this tag. The format is ext=language, where ext is a file extension, and\n# language is one of the parsers supported by doxygen: IDL, Java, Javascript,\n# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C.\n#\n# Note For files without extension you can use no_extension as a placeholder.\n#\n# Note that for custom extensions you also need to set FILE_PATTERNS otherwise\n# the files are not read by doxygen.\n\nEXTENSION_MAPPING      = \n\n# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments\n# according to the Markdown format, which allows for more readable\n# documentation. See http://daringfireball.net/projects/markdown/ for details.\n# The output of markdown processing is further processed by doxygen, so you can\n# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in\n# case of backward compatibilities issues.\n# The default value is: YES.\n\nMARKDOWN_SUPPORT       = YES\n\n# When enabled doxygen tries to link words that correspond to documented\n# classes, or namespaces to their corresponding documentation. Such a link can\n# be prevented in individual cases by by putting a % sign in front of the word\n# or globally by setting AUTOLINK_SUPPORT to NO.\n# The default value is: YES.\n\nAUTOLINK_SUPPORT       = YES\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should set this\n# tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string);\n# versus func(std::string) {}). This also make the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n# The default value is: NO.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n# The default value is: NO.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:\n# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen\n# will parse them like normal C++ but will assume all classes use public instead\n# of private inheritance when no explicit protection keyword is present.\n# The default value is: NO.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate\n# getter and setter methods for a property. Setting this option to YES will make\n# doxygen to replace the get and set methods by a property in the documentation.\n# This will only work if the methods are indeed getting or setting a simple\n# type. If this is not the case, or you want to show the methods anyway, you\n# should set this option to NO.\n# The default value is: YES.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n# The default value is: NO.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES to allow class member groups of the same type\n# (for instance a group of public functions) to be put as a subgroup of that\n# type (e.g. under the Public Functions section). Set it to NO to prevent\n# subgrouping. Alternatively, this can be done per class using the\n# \\nosubgrouping command.\n# The default value is: YES.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions\n# are shown inside the group in which they are included (e.g. using \\ingroup)\n# instead of on a separate page (for HTML and Man pages) or section (for LaTeX\n# and RTF).\n#\n# Note that this feature does not work in combination with\n# SEPARATE_MEMBER_PAGES.\n# The default value is: NO.\n\nINLINE_GROUPED_CLASSES = YES\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions\n# with only public data fields or simple typedef fields will be shown inline in\n# the documentation of the scope in which they are defined (i.e. file,\n# namespace, or group documentation), provided this scope is documented. If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = YES\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = NO\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = NO\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = YES\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = NO\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = NO\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = NO\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = \n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = YES\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         = \n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = . \\\n                         src/RTX/cmsis_os_rtx_extensions.h \\\n                         ../../RTOS/RTX/Templates/RTX_Conf_CM.c \\\n                         ../../RTOS/Template/cmsis_os.h\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          = *.c \\\n                         *.cc \\\n                         *.cxx \\\n                         *.cpp \\\n                         *.c++ \\\n                         *.java \\\n                         *.ii \\\n                         *.ixx \\\n                         *.ipp \\\n                         *.i++ \\\n                         *.inl \\\n                         *.h \\\n                         *.hh \\\n                         *.hxx \\\n                         *.hpp \\\n                         *.h++ \\\n                         *.idl \\\n                         *.odl \\\n                         *.cs \\\n                         *.php \\\n                         *.php3 \\\n                         *.inc \\\n                         *.m \\\n                         *.mm \\\n                         *.dox \\\n                         *.py \\\n                         *.f90 \\\n                         *.f \\\n                         *.for \\\n                         *.vhd \\\n                         *.vhdl \\\n                         *.txt\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = YES\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = YES\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       = \n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        = \n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = ../../RTOS\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           = \n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        = \n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS = \n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE = \n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = NO\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = NO\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = NO\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = YES\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        = \n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../Doxygen_Templates/printComponentTabs.js \\\n                         ../../RTOS/CMSIS_RTOS_Tutorial.pdf\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 100\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = \n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     = \n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               = \n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   = \n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  = \n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  = \n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           = \n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     = \n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       = \n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       = \n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     = \n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         = \n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           = \n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           = \n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      = \n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    = \n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             = \n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                = \n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. 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    "content": "//  ==== RTX Extensions ====\n\n/// Suspend the RTX task scheduler.\n/// \\return number of ticks, for how long the system can sleep or power-down.\nuint32_t os_suspend (void);\n\n/// Resume the RTX task scheduler.\n/// \\param[in]     sleep_time    specifies how long the system was in sleep or power-down mode.\nvoid os_resume (uint32_t sleep_time);\n\n/// OS idle demon (running when no other thread is ready to run).\n__NO_RETURN void os_idle_demon (void);\n\n/// OS error callback (called when a runtime error is detected).\n/// \\param[in]     error_code    actual error code that has been detected.\n__NO_RETURN void os_error (uint32_t error_code);\n"
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    "content": "/* ----------------------------------------------------------------------  \n* Copyright (C) 2016 Arm Limited. All rights reserved.  \n*  \n* $Date:        14. April 2016\n* $Revision:    1.02\n*  \n* Project:      CMSIS-RTOS API\n* Title:        cmsis_os.txt\n*  \n* Description:  Documentation file for the CMSIS-RTOS API.\n*  \n* Version 0.03\n*    Initial Proposal Phase\n* Version 1.01\n*    Rework as described in Hist.txt\n* Version 1.02\n*    Rework as described in Hist.txt\n* Version 1.03\n*    Documentation rework for CMSIS 5\n* -------------------------------------------------------------------- */ \n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\mainpage\n\nThis manual describes the \\b CMSIS-RTOS \\b API \\b Version \\b 1 and the reference implementation\n\\ref rtxImplementation \"CMSIS-RTOS RTX\" which is designed for Cortex-M processor-based devices. The RTOS kernel can be used\nfor creating applications that perform multiple tasks simultaneously. These tasks are executed by threads that operate in a\nquasi-parallel fashion.\n\nWhile it is certainly possible to create real-time applications without an RTOS (by executing one or more tasks in a loop),\nthere are numerous scheduling, maintenance, and timing issues that can be solved better with an RTOS. For example, an RTOS\nenables flexible scheduling of system resources like CPU and memory, and offers methods to communicate between threads.\n\nCMSIS-RTOS API programs are written using standard C/C++ constructs and are compiled with the ARMCC, GCC, or IAR Compiler.\nThe \\ref cmsis_os_h \"cmsis_os.h header file\" defines functions and macros that allow declaring tasks and accessing all RTOS\nfeatures easily.\n\nThis manual contains the following sections:\n - \\subpage rtos_revisionHistory : Documents changes made in each version for CMSIS-RTOS API and RTX.\n - \\subpage genRTOSIF : Provides an overview about the CMSIS-RTOS API.\n - \\subpage usingOS : Provides generic instructions for using a CMSIS-RTOS API compliant implementation. \n - \\subpage functionOverview : Lists the CMSIS-RTOS API functions including RTX-specific extensions.\n - \\subpage rtosValidation : Describes the Software Pack that can be used to validate a CMSIS-RTOS implementation.\n - \\subpage rtxImplementation : Documents the open-source implementation CMSIS-RTOS RTX.\n\n\\note An extended version of the CMSIS-RTOS API is available in <a class=\"el\" href=\"../../RTOS2/html/index.html\">CMSIS-RTOS v2</a>.\n\n<hr>\n\nCMSIS-RTOS in ARM::CMSIS Pack\n-----------------------------\n\nThe following files relevant to CMSIS-RTOS are present in the <b>ARM::CMSIS</b> Pack directories:\n|File/Folder                  | Content                                                                |\n|-----------------------------|------------------------------------------------------------------------|\n|\\b CMSIS/Documentation/RTOS  | This documentation                                                     |\n|\\b CMSIS/Documentation/RTOS2 | CMSIS-RTOS API Version 2 documentation                                 |\n|\\b CMSIS/RTOS/Template       | \\ref cmsis_os_h                                                        |\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page rtos_revisionHistory Revision History\n\n\n\\section GenRTOSRev CMSIS-RTOS API\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>V1.03 - only documentation changes</td>\n      <td>\n      Incorporated documentation for reference implementation CMSIS-RTOS RTX.\n     </td>\n    </tr>\n    <tr>\n      <td>V1.02 - only documentation changes</td>\n      <td>\n      Added: Overview of the \\ref rtosValidation \"CMSIS-RTOS Validation\" Software Pack.\\n\n\t  Clarified: Behaviour of \\ref CMSIS_RTOS_TimeOutValue.\n     </td>\n    </tr>\n    <tr>\n      <td>V1.02</td>\n      <td>Added: New control functions for short timeouts in microsecond resolution \\ref osKernelSysTick, \\ref osKernelSysTickFrequency, \\ref osKernelSysTickMicroSec.\\n\n      Removed: osSignalGet.\n     </td>\n    </tr>\n    <tr>\n      <td>V1.01</td>\n      <td>Added capabilities for C++, kernel initialization and object deletion.\\n\n      Prepared for C++ class interface. In this context to \\em const attribute has been moved from osXxxxDef_t typedefs to the osXxxxDef macros.\\n\n      Added: \\ref osTimerDelete, \\ref osMutexDelete, \\ref osSemaphoreDelete.\\n\n      Added: \\ref osKernelInitialize that prepares the Kernel for object creation.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>\n      V1.00</td>\n      <td>First official Release.\\n\n      Added: \\ref osKernelStart; starting 'main' as a thread is now an optional feature.\\n\n      Semaphores have now the standard behavior.\\n\n      \\ref osTimerCreate does no longer start the timer. Added: \\ref osTimerStart (replaces osTimerRestart).\\n\n      Changed: osThreadPass is renamed to \\ref osThreadYield.\n      </td>\n    </tr>\n    <tr>\n      <td>V0.02</td>\n      <td>Preview Release.</td>\n    </tr>\n</table>\n\n\n\\section RTXRevisionHistory CMSIS-RTOS RTX\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>V4.82</td>\n      <td>\n       Corrected: Recursive Mutex 16-bit lock counter is now checked to not overflow.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>V4.81</td>\n      <td>\n       Added provisions for Arm Compiler 6.\\n\n       Corrected: Message Queue behavior when osMessagePut timed out due to full queue and osMessageGet was called from ISR.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>V4.80</td>\n      <td>\n       Restored time delay parameter 'millisec' old behavior (before V4.79) for software compatibility.\\n\n       Corrected: implicit mutex release when mutex owner thread is terminated.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>V4.79</td>\n      <td>\n       Corrected: time delay parameter ‘millisec’ in all functions (osDelay, osSignalWait, …) is now treated as lower bound – wait for at least time given (before it could have been up to 1ms less).\\n\n       Corrected: Lazy Context switching for Cortex-M4 with FPU could lead to a crash when thread which used FPU was terminated.\\n\n       Corrected: osMailCAlloc only cleared the allocated memory block if it was available without waiting.\\n\n       Corrected: osThreadCreate function returns NULL when trying to create more concurrent threads than defined in the configuration.\\n\n       Improved source code MISRA compliance.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>V4.78</td>\n      <td>       \n       Corrected: osTimerStart function accepts full 32-bit range for time delay value in milisec.\\n\n       Added: User Timer Callback Queue overflow reported through os_error(OS_ERROR_TIMER_OVF).\\n\n      </td>\n    </tr>\n    <tr>\n      <td>V4.77</td>\n      <td>       \n       Added: Stack usage watermark.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>V4.76</td>\n      <td>       \n       Optimized Service calls in GCC libraries.\\n\n       Corrected: Stack/Heap regions can be used with scatter loading.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>V4.75</td>\n      <td>       \n       Corrected: Service calls for Cortex-M4 with Floating Point for GCC.\\n\n       Corrected: \\ref osSignalClear returns 0x80000000 when called from interrupt service routines.\\n\n       Corrected: C standard library memory functions (malloc, free, ...) can be called between calls to \\ref osKernelInitialize and \\ref osKernelStart.\\n\n       Corrected: Interrupt Priority Group can be configured between calls to \\ref osKernelInitialize and \\ref osKernelStart.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>V4.74</td>\n      <td>       \n       Corrected: \\ref osKernelInitialize and \\ref osKernelStart when called from main which is already a thread.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>V4.73</td>\n      <td>       \n       Corrected: mutex priority inversion when thread owns more than one mutex.\\n\n       Added: RTX extensions os_suspend and os_resume.\\n\n       Added: RTX os_error template.\n      </td>\n    </tr>\n    <tr>\n      <td>V4.72</td>\n      <td>Corrected: object initialization when defined inside function (allocated on stack and not as static memory).</td>\n    </tr>\n    <tr>\n      <td>V4.71</td>\n      <td>Corrected: osMailFree behaviour when osMailAlloc timed out.</td>\n    </tr>\n    <tr>\n      <td>V4.70</td>\n      <td>Added: New control functions for short timeouts in microsecond resolution \\ref osKernelSysTick, \\ref osKernelSysTickFrequency, \\ref osKernelSysTickMicroSec.\\n\n      Removed: osSignalGet.\n      </td>\n    </tr>\n    <tr>\n      <td>V4.61</td>\n      <td>Enhanced: \\ref osTimerCreate can now be called after \\ref osKernelInitialize (before only after \\ref osKernelStart).\\n\n       Corrected: Initialization of alternative kernel timer for Cortex-M0/M0+/M1 (when SysTick timer is not used).\\n\n       Corrected: Message/Mail Queue behavior when timeout expires.\n      </td>\n    </tr>\n    <tr>\n      <td>V4.51</td>\n      <td>Corrected: problem with \\ref osKernelInitialize when after the call high priority threads are defined.</td>\n    </tr>\n    <tr>\n      <td>V4.50</td>\n      <td>Based on CMSIS-RTOS API Version 1.01 and the classic RTX V4.50 Kernel.\\n\n          Added: \\ref osTimerDelete, \\ref osMutexDelete, \\ref osSemaphoreDelete.\\n\n          Added: \\ref osKernelInitialize that prepares the Kernel for object creation.\\n\n          Added: support for Low Power Cortex-M applications based on new configuration functions: \\b os_suspend, \\b os_resume.\\n\n          Added: support for peripheral timer to be used as OS tick timer instead of Core SysTick timer.\\n\n          Corrected: stack checking did not work for os_tsk_delete_self function Preview Release.\n      </td>\n    </tr>\n    <tr>\n      <td>V4.20</td>\n      <td>Initial CMSIS-RTOS adaption of the RTX Kernel.\n      </td>\n    </tr>\n</table>\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page usingOS Using a CMSIS-RTOS Implementation\n\nA CMSIS-RTOS implementation is typically provided as a library. To add the RTOS functionality to an existing CMSIS-based\napplication, the RTOS library (and typically a configuration file) needs to be added.  The available functionality of the\nRTOS library is defined in the header file \\b cmsis_os.h that is specific for each CMSIS-RTOS implementation.\n\n\\image html \"CMSIS_RTOS_Files.png\" \"CMSIS-RTOS File Structure\"\n\nDepending on the CMSIS-RTOS implementation, execution may start with the \\b main function as the first thread. This has the\nbenefit that an application programmer may use other middleware libraries that create threads internally, but the remaining\npart of the user application just uses the \\b main thread. Therefore, the usage of the RTOS can be invisible to the\napplication programmer, but libraries can use CMSIS-RTOS features.\n\nOnce the files are added to a project, the user can start working with the CMSIS-RTOS functions.  A code example is provided\nbelow:\n \n<b>Code Example</b>\n\\code\n#include \"cmsis_os.h\"                            // CMSIS-RTOS header file\n \nvoid job1 (void const *argument)  {              // thread function 'job1'\n  while (1)  {\n      :                                          // execute some code\n    osDelay (10);                                // delay execution for 10 milliseconds\n  }\n}\n \nosThreadDef(job1, osPriorityAboveNormal, 1, 0);  // define job1 as thread function\n \nvoid job2 (void const *argument)  {              // thread function 'job2'\n  osThreadCreate(osThread(job1),NULL);           // create job1 thread\n  while (1)   {\n    :                                            // execute some code\n  }\n}\n \nosThreadDef(job2, osPriorityNormal, 1, 0);       // define job2 as thread function\n \nvoid job3 (void const *argument)  {              // thread function 'job3'\n  while (1)   {\n      :                                          // execute some code\n    osDelay (20);                                // delay execution for 20 milliseconds\n  }\n}\n \nosThreadDef(job3, osPriorityNormal, 1, 0);       // define job3 as thread function\n \nint main (void) {                                // program execution starts here\n  osKernelInitialize ();                         // initialize RTOS kernel\n    :                                            // setup and initialize peripherals\n  osThreadCreate (osThread(job2));\n  osThreadCreate (osThread(job3));\n  osKernelStart ();                              // start kernel with job2 execution\n}\n\\endcode\n\n\\section cmsis_os_h Header File Template: cmsis_os.h\n\nThe file \\b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).\nEach RTOS that is compliant with CMSIS-RTOS shall provide a specific \\b cmsis_os.h header file that represents\nits implementation.\n\nThe file cmsis_os.h contains:\n - CMSIS-RTOS API function definitions\n - struct definitions for parameters and return types\n - status and priority values used by CMSIS-RTOS API functions\n - macros for defining threads and other kernel objects\n\n\n<b>Name conventions and header file modifications</b>\n\nAll definitions are prefixed with \\b os to give an unique name space for CMSIS-RTOS functions.\nDefinitions that are prefixed \\b os_ are not used in the application code but local to this header file.\nAll definitions and functions that belong to a module are grouped and have a common prefix, i.e. \\b osThread.\n\nDefinitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS\nimplementation. These definitions can be specific to the underlying RTOS kernel.\n\nDefinitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is\nno longer compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS\nimplementation.\n\n<b>Define and reference object definitions</b>\n\nWith <b>\\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header\nfile that is used throughout a project as shown below:\n\n<i>Header File</i>\n\\code\n#include <cmsis_os.h>                                         // CMSIS RTOS header file\n\n// Thread definition\nextern void thread_sample (void const *argument);             // function prototype\nosThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);\n\n// Pool definition\nosPoolDef(MyPool, 10, long);\n\\endcode\n\n\nThis header file defines all objects when included in a C/C++ source file. When <b>\\#define osObjectsExternal</b> is\npresent before the header file, the objects are defined as external symbols. A single consistent header file can therefore be\nused throughout the whole project.\n\n<i>Example</i>\n\\code\n#include \"osObjects.h\"     // Definition of the CMSIS-RTOS objects\n\\endcode\n\n\\code\n#define osObjectsExternal  // Objects will be defined as external symbols\n#include \"osObjects.h\"     // Reference to the CMSIS-RTOS objects\n\\endcode\n\n<b>Header file %cmsis_os.h</b>\n\n\\include Template/cmsis_os.h\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page functionOverview Function Overview\n\nThe following list provides a brief overview of all CMSIS-RTOS functions.  Functions marked with $ are optional.\nA specific CMSIS-RTOS implementation may not provide all functions, but this is clearly indicated with \\b osFeatureXXXX\ndefines.\n\n\\note Functions that are not supported by the \\ref rtxImplementation, are marked with a (*).\n\n - \\ref CMSIS_RTOS_KernelCtrl\n   - \\ref osKernelInitialize : Initialize the RTOS kernel.\n   - \\ref osKernelStart : Start the RTOS kernel.\n   - \\ref osKernelRunning : Query if the RTOS kernel is running.\n   - \\ref osKernelSysTick : Get RTOS kernel system timer counter.\n   - \\ref osKernelSysTickFrequency : RTOS kernel system timer frequency in Hz.\n   - \\ref osKernelSysTickMicroSec : Convert microseconds value to RTOS kernel system timer value.\n\n - \\ref CMSIS_RTOS_ThreadMgmt\n   - \\ref osThreadCreate : Start execution of a thread function.\n   - \\ref osThreadTerminate : Stop execution of a thread function.\n   - \\ref osThreadYield : Pass execution to next ready thread function.\n   - \\ref osThreadGetId : Get the thread identifier to reference this thread.\n   - \\ref osThreadSetPriority : Change the execution priority of a thread function.\n   - \\ref osThreadGetPriority : Obtain the current execution priority of a thread function.\n\n - \\ref CMSIS_RTOS_Wait\n   - \\ref osDelay : Wait for a specified time.\n   - \\ref osWait : Wait for any event of the type Signal, Message, or Mail.(*)\n\n - \\ref CMSIS_RTOS_TimerMgmt \n   - \\ref osTimerCreate : Define attributes of the timer callback function.\n   - \\ref osTimerStart : Start or restart the timer with a time value.\n   - \\ref osTimerStop : Stop the timer.\n   - \\ref osTimerDelete : Delete a timer.\n\n - \\ref CMSIS_RTOS_SignalMgmt\n   - \\ref osSignalSet : Set signal flags of a thread.\n   - \\ref osSignalClear : Reset signal flags of a thread.\n   - \\ref osSignalWait : Suspend execution until specific signal flags are set.\n\n - \\ref CMSIS_RTOS_MutexMgmt\n   - \\ref osMutexCreate : Define and initialize a mutex.\n   - \\ref osMutexWait : Obtain a mutex or Wait until it becomes available.\n   - \\ref osMutexRelease : Release a mutex.\n   - \\ref osMutexDelete : Delete a mutex.\n\n - \\ref CMSIS_RTOS_SemaphoreMgmt\n   - \\ref osSemaphoreCreate : Define and initialize a semaphore.\n   - \\ref osSemaphoreWait : Obtain a semaphore token or Wait until it becomes available.\n   - \\ref osSemaphoreRelease : Release a semaphore token.\n   - \\ref osSemaphoreDelete : Delete a semaphore.\n\n - \\ref CMSIS_RTOS_PoolMgmt\n   - \\ref osPoolCreate : Define and initialize a fix-size memory pool. \n   - \\ref osPoolAlloc : Allocate a memory block.\n   - \\ref osPoolCAlloc : Allocate a memory block and zero-set this block.\n   - \\ref osPoolFree : Return a memory block to the memory pool.\n\n - \\ref CMSIS_RTOS_Message\n   - \\ref osMessageCreate : Define and initialize a message queue.\n   - \\ref osMessagePut : Put a message into a message queue.\n   - \\ref osMessageGet : Get a message or suspend thread execution until message arrives.\n\n - \\ref CMSIS_RTOS_Mail\n   - \\ref osMailCreate : Define and initialize a mail queue with fix-size memory blocks.\n   - \\ref osMailAlloc : Allocate a memory block.\n   - \\ref osMailCAlloc : Allocate a memory block and zero-set this block.\n   - \\ref osMailPut : Put a memory block into a mail queue.\n   - \\ref osMailGet : Get a mail or suspend thread execution until mail arrives.\n   - \\ref osMailFree : Return a memory block to the mail queue.\n\n - \\ref RTX_Global_Functions \"RTX Specific Functions\"\n   - \\ref os_idle_demon : System thread running when no other thread is ready to run.\n   - \\ref os_suspend : Suspend the RTX task scheduler.\n   - \\ref os_resume : Resume the RTX task scheduler.\n   - \\ref os_tick_init : Initialize an alternative hardware timer as RTX kernel timer.\n   - \\ref os_tick_val : Get alternative hardware timer's current value.\n   - \\ref os_tick_ovf : Get alternative hardware timer's  overflow flag.\n   - \\ref os_tick_irqack : Acknowledge alternative hardware timer interrupt.\n   - \\ref os_error : Called when a runtime error is detected.\n\n\\section CMSIS_RTOS_TimeOutValue Timout Value   \n\nThe timeout value specifies the number of timer ticks until a timeout or time delay elapses. The value is an upper bound and \ndepends on the actual time elapsed since the last timer tick. \n\nFor a value of \\b 1 the system waits until the next timer tick occurs. That means that the actual timeout value can be one\ntimer tick less than the specified timeout value. \n\n\\image html TimerValues.png \"Timer Values\"\n\n\\section CMSIS_RTOS_ISR_Calls Calls from Interrupt Service Routines \n\nThe following CMSIS-RTOS functions can be called from threads and Interrupt Service Routines (ISR):\n  - \\ref osKernelRunning\n  - \\ref osSignalSet\n  - \\ref osSemaphoreRelease\n  - \\ref osPoolAlloc, \\ref osPoolCAlloc, \\ref osPoolFree\n  - \\ref osMessagePut, \\ref osMessageGet\n  - \\ref osMailAlloc, \\ref osMailCAlloc, \\ref osMailGet, \\ref osMailPut, \\ref osMailFree\n\nFunctions that cannot be called from an ISR are verifying the interrupt status and return, in case they are called\nfrom an ISR context, the status code \\b osErrorISR. In some implementations, this condition might be caught using the HARD\nFAULT vector.\n\nSome CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISRs at the same time.\nIf this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \\b osErrorISRRecursive.\n   \n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page genRTOSIF Generic RTOS Interface\n\nThe CMSIS-RTOS API is a generic RTOS interface for Arm&reg; Cortex&reg;-M processor-based devices. CMSIS-RTOS provides a\nstandardized API for software components that require RTOS functionality and gives therefore serious benefits to the users\nand the software industry.\n - CMSIS-RTOS provides basic features that are required in many applications or technologies such as UML or Java (JVM).\n - The unified feature set of the CMSIS-RTOS API simplifies sharing of software components and reduces learning efforts.\n - Middleware components that use the CMSIS-RTOS API are RTOS agnostic. CMSIS-RTOS compliant middleware is easier to adapt.\n - Standard project templates (such as motor control) of the CMSIS-RTOS API may be shipped with freely available CMSIS-RTOS\n   implementations.\n\n\n\\note The CMSIS-RTOS API defines a minimum feature set. Implementations with extended features may be provided by RTOS\n      vendors.\n\n\\image html \"API_Structure.png\" \"CMSIS-RTOS API Structure\"\n\nA typical CMSIS-RTOS API implementation interfaces to an existing real-time Kernel. The CMSIS-RTOS API provides the following\nattributes and functionalities:\n - Function names, identifiers, and parameters are descriptive and easy to understand. The functions are powerful and\n   flexible which reduces the number of functions exposed to the user. \n - \\ref CMSIS_RTOS_ThreadMgmt allows you to define, create, and control threads.\n - Interrupt Service Routines (ISR) can \\ref CMSIS_RTOS_ISR_Calls \"call some CMSIS-RTOS functions\". When a CMSIS-RTOS function cannot be\n   called from ISR context, it rejects the invocation.\n - Three different thread event types support communication between multiple threads and/or ISR:\n   - \\b Signal: is a flag that may be used to indicate specific conditions to a thread. Signals can be modified in an ISR or\n     set from other threads. \n   - \\b Message: is a 32-bit value that can be sent to a thread or an ISR. Messages are buffered in a queue. The message type\n     and queue size is defined in a descriptor.\n   - \\b Mail: is a fixed-size memory block that can be sent to a thread or an ISR. Mails are buffered in a queue and memory\n     allocation is provided. The mail type and queue size is defined in a descriptor.\n - \\ref CMSIS_RTOS_MutexMgmt and \\ref CMSIS_RTOS_SemaphoreMgmt are incorporated.\n - CPU time can be schedule with the following functionalities:\n   - A \\a timeout parameter is incorporated in many CMSIS-RTOS functions to avoid system lockup. When a timeout is specified,\n     the system waits until a resource is available or an event occurs. While waiting, other threads are scheduled.\n   - The \\ref osDelay function puts a thread into the state \\b WAITING for a specified period of time.\n   - The generic \\ref osWait function waits for events that are assigned to a thread.\n   - The \\ref osThreadYield provides co-operative thread switching and passes execution to another thread of the same\n     priority.\n\nThe CMSIS-RTOS API is designed to optionally incorporate multi-processor systems and/or access protection via the Cortex-M\nMemory Protection Unit (MPU).\n\nIn some RTOS implementations threads may execute on different processors and \\b Mail and \\b Message queues can therefore\nreside in shared memory resources.\n\nThe CMSIS-RTOS API encourages the software industry to evolve existing RTOS implementations. Kernel objects are defined and\naccessed using macros. This allows differentiation. RTOS implementations can be different and optimized in various aspects\ntowards the Cortex-M processors. Optional features may be for example\n - Generic \\b wait function; i.e. with support of time intervals.\n - Support of the Cortex-M Memory Protection Unit (MPU).\n - Zero-copy mail queue.\n - Support of multi-processor systems.\n - Support of a DMA controller.\n - Deterministic context switching.\n - Round-robin context switching.\n - Deadlock avoidance, for example with priority inversion.\n - Zero interrupt latency by using the Cortex-M3/M4 instructions LDREX and STREX.\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page rtosValidation RTOS Validation\n\nArm offers a <a class=el href=\"https://www.keil.com/pack\" target=\"_blank\">Software Pack</a> for the CMSIS-RTOS Validation.\nThe <b>ARM::CMSIS-RTOS_Validation</b> Pack contains the following:\n\n - Source code of a CMSIS-RTOS Validation Suite along with configuration file.\n - Documentation of the CMSIS-RTOS Validation Suite.\n - Example that shows the usage of the CMSIS-RTOS Validation Suite using simulation.\n\nThe CMSIS-RTOS Validation Suite is currently available in beta release and performs generic validation of various\nRTOS features. The test cases verify the functional behaviour, test invalid parameters and call management \nfunctions from ISR.\n\nThe following CMSIS-RTOS features can be tested with the current release:\n - Thread : Create multiple threads, terminate, restart, yield, change priority \n - Timer : Create periodic and one-shot timers\n - GenWait : Call generic wait functions (osDelay and osWait)\n - WaitFunc : Measure wait ticks (delay, mail, message, mutex, semaphore, signal)\n \nMoreover the following inter-thread communication functions can be tested: \n - Signal : Verify signal events\n - Memory Pool : Verify memory allocation\n - Message Queue : Exchange messages between threads\n - Mail Queue : Exchange data between threads\n - Mutex : Synchronize resource access \n - Semaphore : Access shared resources \n \nThe RTOS Validation output can be printed to a console, output via ITM printf, or output to a memory buffer.\n \n\\section test_output Sample Test Output\n\\verbatim\nCMSIS-RTOS Test Suite   Oct 21 2015   16:39:16 \n\nTEST 01: TC_ThreadCreate                  PASSED\nTEST 02: TC_ThreadMultiInstance           PASSED\nTEST 03: TC_ThreadTerminate               PASSED\n  :\n  :\nTEST 08: TC_ThreadChainedCreate           PASSED\nTEST 09: TC_ThreadYield                   NOT EXECUTED\nTEST 10: TC_ThreadParam                   PASSED\n  :\n  :\nTEST 60: TC_MailFromISRToThread           PASSED\n\nTest Summary: 60 Tests, 59 Executed, 59 Passed, 0 Failed, 0 Warnings.\nTest Result: PASSED\n\\endverbatim\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page rtxImplementation RTX Implementation\n\nThis version of RTX implements the CMSIS-RTOS API, which is a generic RTOS interface for Cortex-M processor-based devices.\nThe CMSIS-RTOS API provides a standardized interface for software components that require RTOS functionality.\nThis RTX implementation gives therefore serious benefits to the users and the software industry.\n\n - The unified feature set of the CMSIS-RTOS API simplifies sharing of software components and reduces learning efforts.\n - Middleware components that use the CMSIS-RTOS API are RTOS agnostic and CMSIS-RTOS compliant middleware is easier to\n   adapt.\n - This RTX implementation is available under the Apache-2.0 license and can be freely distributed with project templates.\n \nThe CMSIS-RTOS RTX manages the resources of the microcontroller system and implements the concept of parallel threads that\nrun concurrently. There are many advantages of using the CMSIS-RTOS RTX kernel.\n\nApplications frequently require several concurrent activities. RTX can manage multiple concurrent activities at the time when \nthey are needed. Each activity gets a separate thread which executes a specific task and this simplifies the overall \nprogram structure. The CMSIS-RTOS RTX system is scalable and additional threads can be added easily at a later time. \nThreads have a priority allowing faster execution of time-critical parts of an user application.\n\nThe CMSIS-RTOS RTX offers services needed in many real-time applications, for example, periodical activation of timer\nfunctions, memory management, and message exchange between threads with time limits.\n\n\\image html \"RTX_Structure.png\" \"CMSIS-RTOS RTX Structure\"\n\nCompared to the classic Keil RTX version, the CMSIS-RTOS RTX library is extended with the CMSIS API interface module (source\nfile rt_cmsis.c) which implements the function translation. The header file cmsis_os.h provides the API to the CMSIS-RTOS RTX\nfor the user application. Refer to \\ref using for more information.\n\nCMSIS-RTOS RTX has several options that are configured with the \\ref RTX_Conf_CM \"RTX_Conf_CM.c\" file. Refer to\n\\ref configure for more information.\n\nAttributes of the CMSIS-RTOS RTX implementation:\n - Provides the complete functions specified for a CMSIS-RTOS with the exception of the function \\ref osWait.\n - Interrupt Service Routines (ISR) \\ref isr_function_calls \"may call some CMSIS-RTOS RTX functions\".\n - Configurations options for Thread Stack. Refer to \\ref threadConfig for more information.\n - Fully deterministic context switching and deadlock avoidance. Refer to \\ref PriorityInversion for more information.\n - Optional Round-Robin Thread switching with configurable time-slices. Refer to \\ref threadConfig for more information.\n\n\nThe following sections provide further details:\n - \\subpage theory : provides general information about the operation of CMSIS-RTOS RTX.\n - \\subpage dirstructfiles : explains the directories and files that are supplied as part of CMSIS-RTOS RTX.\n - \\subpage technicalData : lists hardware requirements and limitations such as number of concurrent threads.\n - \\subpage misraCompliance : describes the violations to the MISRA standard.\n - \\subpage using : Provides instructions for writing and debugging applications with CMSIS-RTOS RTX. \n - \\subpage configure : Describes configuration parameters of CMSIS-RTOS RTX. \n - \\subpage exampleRTX_Tutorial : Is an in-depth tutorial that can be used with any hardware to get a better understanding of\n   the concepts and use cases of a real-time operating system.\n - \\subpage creating_RTX_LIB : Describes how to build your own CMSIS-RTOS RTX library.\n*/\n\n\n/* ========================================================================================================================== */\n/** \n\\page theory Theory of Operation\n\nThis section describes how CMSIS-RTOS RTX manages the resources of the target system. Many aspects of the CMSIS-RTOS RTX\nkernel can be configured. Information about configuration options is mentioned where applicable.\n\n\n\\section osFeature Settings for osFeature_xxx in cmsis_os.h\n\nCMSIS-RTOS RTX uses the following \\#defines.\n\n| osFeature_xxx \\#define      | RTX Setting | Meaning                                            |\n|-----------------------------|-------------|----------------------------------------------------|\n| \\ref osFeature_MainThread   |  1          | main can be a thread\n| \\ref osFeature_Pool         |  1          | Memory Pools are available\n| \\ref osFeature_MailQ        |  1          | Mail Queues are available\n| \\ref osFeature_MessageQ     |  1          | Message Queues are available\n| \\ref osFeature_Signals      |  16         | 16 Signal Flags are available per thread\n| \\ref osFeature_Semaphore    |  65535      | Maximum count for \\ref osSemaphoreCreate function\n| \\ref osFeature_Wait         |  0          | \\ref osWait is not available\n| \\ref osFeature_SysTick      |  1          | \\ref osKernelSysTick functions are available\n\n\n\\section KernelTimer RTX Kernel Timer Tick and Thread Management\n\nBy default, CMSIS-RTOS RTX uses the Cortex-M\n<a href=\"../../Core/html/group__SysTick__gr.html\" target=\"_blank\">SysTick</a> timer to generate\nperiodic interrupts for the RTX kernel timer tick. CMSIS-RTOS provides \\ref CMSIS_RTOS_TimerMgmt functions and several\nCMSIS-RTOS functions have a timeout parameter. This periodic RTX kernel timer tick interrupt is used to derive the required\ntime interval. CMSIS-RTOS RTX also provides configuration options for a alternative timer and tick-less operation. Refer to\n\\ref timerTick for more information.\n\nTo handle timeout and time delays for threads, the CMSIS-RTOS RTX thread management is controlled by the RTX kernel timer\ntick interrupt. The thread context switch itself is implemented in the HAL_CMx.x hardware abstraction layer source files. The\nthread context contains all CPU registers (R0 - R12), the return address (LR), the program counter (PC), and the processor\nstatus register (xPSR). For the Cortex-M4 FPU and Cortex-M7 FPU the floating point status and registers (S0 - S32, FPSCR) are\nalso part of the thread context.\n\nWhen a thread switch occurs:\n - the thread context of the current running thread is stored on the local stack of this thread.\n - the stack pointer is switched to the next running thread.\n - the thread context of this next running thread is restored and this thread starts to run.\n\n\\note \n- For Cortex-M0, Cortex-M3, Cortex-M4, and Cortex-M7 the thread context requires 64 bytes on the local stack.\n- For Cortex-M4 FPU and Cortex-M7 FPU the thread context requires 200 bytes on the local stack. For devices with Cortex-M4\n  FPU and Cortex-M7 FPU the default stack space should be increased to a minimum of 300 bytes.\n\nEach thread is provided with an separate stack that holds the thread context and stack space for automatic variables and\nreturn addresses for function call nesting. The stack sizes of the RTX threads are flexible configurable as explained in the\nsection \\ref threadConfig. RTX even offers a configurable checking for stack overflows. Refer to \\ref stackCheck for more\ninformation.\n\n\\section RTX_Threads CMSIS-RTOS RTX Threads\n\nAt startup time, the CMSIS-RTOS RTX creates the following threads:\n - \\b main : the 'main' function of the application code is started as thread with the \\ref osPriorityNormal.\n - \\b os_idle_demon : this thread executes when no other thread is in \\b RUNNING state. The code of that thread is provided\n   in the \\ref RTX_Conf_CM \"RTX_Conf_CM.c\" file and is typically used to put the system into a power-saving mode.\n - \\b osTimerThread : this thread executes the \\ref CMSIS_RTOS_TimerMgmt callback functions. This thread can be disabled;\n   refer to \\ref UserTimer for configuration options.\n\n\\section PriorityInversion Priority Inversion on Resource Sharing\n\nThe CMSIS-RTOS RTX employs a priority-based preemptive scheduler which ensures that from all the threads that are in the\n\\b READY state, the thread with the highest priority gets executed and becomes the \\b RUNNING thread. Because threads share\nresources, events that are outside of the control of the RTX scheduler can prevent the highest priority thread from running\nwhen it should. If this happens, a critical deadline could be missed, causing the system to fail. Priority inversion is the\nterm of a scenario in which the highest-priority ready task fails to run when it should.\n\nThreads typically share resources to communicate and process data by using the CMSIS-RTOS \\ref CMSIS_RTOS_MutexMgmt. At any\ntime, two or more threads share a resource, such as a memory buffer or a serial port, one of them may have a higher priority.\nIt is expected that the higher-priority thread runs as soon as it is in the \\b READY state. However, if the lower-priority\nthread is using a shared resource of a higher-priority thread, this higher-priority thread must wait until the lower-priority\nthread releases the shared resource.\n\nTo prevent priority inversions, the CMSIS-RTOS RTX implements a <b>priority inheritance</b> method for the\n\\ref CMSIS_RTOS_MutexMgmt. A lower-priority thread inherit the priority of any higher-priority thread that is waiting with\n\\ref osMutexWait on a shared resource. During the time the higher-priority thread is in \\b WAITING state, the lower-priority\nthread runs at the same priority of a higher-priority pending thread. When the lower-priority thread stops to share a\nresource with \\ref osMutexRelease, the original priority is assigned to this thread again.\n\n\\section isr_function_calls Function calls from Interrupt Service Routines (ISR)\n\nThe following CMSIS-RTOS functions can be called from threads <i>and</i> Interrupt Service Routines (ISR):\n  - \\ref osKernelRunning\n  - \\ref osSignalSet\n  - \\ref osSemaphoreRelease\n  - \\ref osPoolAlloc, \\ref osPoolCAlloc, \\ref osPoolFree\n  - \\ref osMessagePut, \\ref osMessageGet\n  - \\ref osMailAlloc, \\ref osMailCAlloc, \\ref osMailGet, \\ref osMailPut, \\ref osMailFree\n\nFunctions that cannot be called from an ISR are verifying the interrupt status and return the status code \\b osErrorISR in\ncase that they are called from an ISR context.\n*/\n\n\n/* ========================================================================================================================== */\n/** \n\\page dirstructfiles Directory Structure and File Overview\n\nThe following section provides an overview of the directory structure and the files that are relevant for the user's for\nCMSIS-RTOS RTX.\n\n\\section Folders CMSIS-RTOS RTX Directory Structure\n\nThe CMSIS-RTOS RTX is delivered in source code and several examples are provided. \n\n<table class=\"cmtable\" summary=\"CMSIS-RTOS RTX Library Files\">\n    <tr>\n      <th>Directory</th>\n      <th>Content</th>\n    </tr>\n    <tr>\n      <td>INC</td>\n      <td>The include files for CMSIS-RTOS RTX. cmsis_os.h is the central include file for user applications.</td>\n    </tr>\n    <tr>\n      <td>LIB</td>\n      <td>CMSIS-RTOS RTX library files for ARMCC, GCC, and IAR Compiler.</td>\n    </tr>\n    <tr>\n      <td>SRC</td>\n      <td>Source code of CMSIS-RTOS RTX library along with project files for ARMCC, GCC, and IAR Compiler.</td>\n    </tr>\n    <tr>\n      <td>Templates</td>\n      <td>CMSIS-RTOS RTX configuration file (\\ref RTX_Conf_CM \"RTX_Conf_CM.c\").</td>\n    </tr>\n    <tr>\n      <td>UserCode Templates</td>\n      <td>Template files for creating application projects with CMSIS-RTOS RTX.</td>\n    </tr>\n</table>\n\n\\section libFiles CMSIS-RTOS RTX Library Files\n\nThe CMSIS-RTOS RTX Library is available pre-compiled for ARMCC, GCC, and IAR C/C++ Compilers and supports all Cortex-M\nprocessor variants in every configuration.\n\n<table class=\"cmtable\" summary=\"CMSIS-RTOS RTX Library Files\">\n    <tr>\n      <th>Library File</th>\n      <th>Processor Configuration</th>\n    </tr>\n    <tr>\n      <td>LIB/ARM/RTX_CM0.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Cortex-M0 and M1, little-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/ARM/RTX_CM0_B.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Cortex-M0 and M1, big-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/ARM/RTX_CM3.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Cortex-M3, M4, and M7 without FPU, little-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/ARM/RTX_CM3_B.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Cortex-M3, M4, and M7 without FPU, big-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/ARM/RTX_CM4.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Cortex-M4 and M7 with FPU, little-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/ARM/RTX_CM4_B.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Cortex-M4 and M7 with FPU, big-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/GCC/libRTX_CM0.a</td>\n      <td>CMSIS-RTOS RTX Library for GCC Compiler, Cortex-M0 and M1, little-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/GCC/libRTX_CM0_B.a</td>\n      <td>CMSIS-RTOS RTX Library for GCC Compiler, Cortex-M0 and M1, big-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/GCC/libRTX_CM3.a</td>\n      <td>CMSIS-RTOS RTX Library for GCC Compiler, Cortex-M3, M4, and M7 without FPU, little-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/GCC/libRTX_CM3_B.a</td>\n      <td>CMSIS-RTOS RTX Library for GCC Compiler, Cortex-M3, M4, and M7 without FPU, big-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/GCC/libRTX_CM4.a</td>\n      <td>CMSIS-RTOS RTX Library for GCC Compiler, Cortex-M4 and M7 with FPU, little-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/GCC/libRTX_CM4_B.a</td>\n      <td>CMSIS-RTOS RTX Library for GCC Compiler, Cortex-M4 and M7 with FPU, big-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/IAR/RTX_CM0.lib</td>\n      <td>CMSIS-RTOS RTX Library for IAR Compiler, Cortex-M0 and M1, little-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/IAR/RTX_CM0_B.lib</td>\n      <td>CMSIS-RTOS RTX Library for IAR Compiler, Cortex-M0 and M1, big-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/IAR/RTX_CM3.lib</td>\n      <td>CMSIS-RTOS RTX Library for IAR Compiler, Cortex-M3, M4, and M7 without FPU, little-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/IAR/RTX_CM3_B.lib</td>\n      <td>CMSIS-RTOS RTX Library for IAR Compiler, Cortex-M3, M4, and M7 without FPU, big-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/IAR/RTX_CM4.lib</td>\n      <td>CMSIS-RTOS RTX Library for IAR Compiler, Cortex-M4 and M7 with FPU, little-endian.</td>\n    </tr>\n    <tr>\n      <td>LIB/IAR/RTX_CM4_B.lib</td>\n      <td>CMSIS-RTOS RTX Library for IAR Compiler, Cortex-M4 and M7 with FPU, big-endian.</td>\n    </tr>\n</table>\n\n\\section RTX_Conf_CM Configuration File RTX_Conf_CM.c\n\n\\include RTX/Templates/RTX_Conf_CM.c\n*/\n\n\n/* ========================================================================================================================== */\n/** \n\\page technicalData Technical Data\n\nThis section lists the technical data of CMSIS-RTOS RTX.\n\n<table class=\"cmtable\">\n    <tr>\n      <th>Description</th>\n      <th>Limitations</th>\n    </tr>\n\n    <tr>\n      <td>Defined Tasks</td>\n      <td>Unlimited</td>\n    </tr>\n\n    <tr>\n      <td>Active Threads</td>\n      <td>250 max</td>\n    </tr>\n\n    <tr>\n      <td>Mailboxes</td>\n      <td>Unlimited</td>\n    </tr>\n\n    <tr>\n      <td>Semaphores</td>\n      <td>Unlimited</td>\n    </tr>\n\n    <tr>\n      <td>Mutexes</td>\n      <td>Unlimited</td>\n    </tr>\n\n    <tr>\n      <td>Signals</td>\n      <td>16 per thread</td>\n    </tr>\n\n    <tr>\n      <td>Timer Callbacks</td>\n      <td>Unlimited</td>\n    </tr>\n\n    <tr>\n      <td>Code Space</td>\n      <td>< 5.0 Kbytes</td>\n    </tr>\n\n    <tr>\n      <td>RAM Space for Kernel</td>\n      <td>300 bytes + 128 bytes Main Stack</td>\n    </tr>\n\n    <tr>\n      <td>RAM Space for a Thread</td>\n      <td>StackSize + 52 bytes</td>\n    </tr>\n\n    <tr>\n      <td>RAM Space for a Mailbox</td>\n      <td>MaxMessages * 4 + 16 bytes</td>\n    </tr>\n\n    <tr>\n      <td>RAM Space for a Semaphore</td>\n      <td>8 bytes</td>\n    </tr>\n\n    <tr>\n      <td>RAM Space for a Mutex</td>\n      <td>12 bytes</td>\n    </tr>\n\n    <tr>\n      <td>RAM Space for a User Timer</td>\n      <td>24 bytes</td>\n    </tr>\n\n    <tr>\n      <td>Hardware Requirements</td>\n      <td>SysTick timer or other hardware timer</td>\n    </tr>\n\n    <tr>\n      <td>Thread context switch time</td>\n      <td>< 2.6 usec @ 72 MHz</td>\n    </tr>\n\n    <tr>\n      <td>Interrupt lockout time</td>\n      <td>Not disabled</td>\n    </tr>\n</table>\n\n\\note\n- Unlimited means that the RTX kernel does not impose any limitations on the number. However, the available system memory\n  resources limit the number of items you can create.\n- RAM requirements depend on the number of concurrently running threads.  \n- The code and RAM size is calculated for ARMCC Compiler when using the <b>MicroLib</b> runtime library.\n\n\\section osWait\nThe generic wait function \\b osWait is currently not supported by CMSIS-RTOS RTX.\n*/\n\n\n/* ========================================================================================================================== */\n/** \n\\page misraCompliance MISRA-C:2004 Compliance Exceptions\nCMSIS-RTOS RTX tries to be MISRA-C compliant as much as possible. However, there are some violations in order to simplify\nthe overall code logic and to generate more efficient code.\n\nCMSIS-RTOS RTX generates the following notes, warnings and infos for MISRA-C:2004 rules:\n- Rule 1.1, required, Rule 2.2, required: Non-ANSI reserved word or construct: '//'\n- Rule 1.2, required: Both sides have side effects\n- Rule 1.2, required: Unusual pointer cast (incompatible indirect types)\n- Rule 8.1, required: Function defined without a prototype in scope\n- Rule 11.1, required, Rule 11.3, advisory: cast from pointer to unsigned int\n- Rule 11.1, required, Rule 11.3, advisory: cast from unsigned int to pointer\n- Rule 11.4, advisory: cast from pointer to pointer\n- Rule 12.11, advisory: Overflow in computing constant for operation: 'unsigned shift left'\n- Rule 13.7, required, Rule 14.1, required: Constant value Boolean\n- Rule 14.4, required: Use of goto is deprecated\n- Rule 14.7, required: Return statement before end of function\n- Rule 16.10, required: Ignoring return value of function\n- Rule 17.2, required, Rule 17.3, required: Relational or subtract operator applied to pointers\n- Rule 19.4, required, Rule 19.10, required: Expression-like macro not parenthesized\n- Rule 19.15, required: Repeated include file\n\nCMSIS-RTOS RTX violates the following MISRA-C:2004 rules:\n- Required Rule 8.5: object/function definition in header file \n- Required Rule 10.1: Prohibited Implicit Conversion: Non-constant argument to function\n- Required Rule 10.1: Implicit conversion of complex integer expression\n- Required Rule 10.3: Cast of complex integer expression to larger type\n- Required Rule 10.3: Cast of complex expression changes signedness\n- Required Rule 11.5: attempt to cast away const/volatile from a pointer or reference\n- Required Rule 12.4: side effects on right hand of logical operator: '&&'\n- Required Rule 12.4: side effects on right hand of logical operator: '||'\n- Required Rule 12.5: non-primary expression used with logical operator\n- Required Rule 14.3: null statement not in line by itself\n- Required Rule 14.8: left brace expected for while, do...while and for\n- Required Rule 14.9: left brace expected for if and else\n- Required Rule 15.3: default missing from switch statement\n- Required Rule 16.9: function identifier used without '&' or parenthesized parameter list \n- Required Rule 17.4: pointer arithmetic other than array indexing used\n- Required Rule 18.4: declaration of union type or object of union type: '{...}' \n- Required Rule 19.12: Multiple use of '#/##' operators in definition of macro \n- Required Rule 20.2: Re-use of C90 identifier pattern\n- Advisory Rule 12.1: dependence placed on C's operator precedence; operators: '+' and '-'\n- Advisory Rule 12.13: increment or decrement combined with another operator\n- Advisory Rule 19.13: '#/##' operator used in macro\n- Advisory Rule 19.7: Function-like macro defined\n*/\n\n\n/* ========================================================================================================================== */\n/** \n\\page using Create an RTX Project\n\nExample projects using CMSIS-RTOS RTX are available for various development boards. To make use of these examples, you need\nto install a Device Family Pack in µVision and use Pack Installer to open a CMSIS-RTOS Blinky project. If you wish to start a\nCMSIS-RTOS RTX from scratch, follow these steps:\n- Create a new project and select a device.\n- In the Manage Run-Time Environment window that opens, select <b>CMSIS\\::CORE</b> and <b>CMSIS\\::RTOS (API)\\::Keil RTX</b>.\n  If the <b>Validation Output</b> requires other components to be present, try to use the \\b Resolve button:\n\n   \\image html manage_rte_output.png\n\n- Click \\b OK. In the \\b Project window, you will see the files that have been automatically added to you project, such as\n  \\b %RTX_Conf_CM.c and the system and startup files:\n\n   \\image html project_window.png\n   \n- You can add template files to the project by right-clicking on <b>Source Group 1</b> and selecting\n  <b>Add New Item to 'Source Group 1'</b>. In the new window, click on <b>User Code Template</b>. On the right-hand side\n  you will see all available template files for CMSIS-RTOS RTX:\n  \n   \\image html add_item.png\n\n- Finally, \\ref configure \"configure\" RTX to the application's needs using the \\b %RTX_Conf_CM.c file.\n\n\\section DefRefObj Define and Reference Object Definitions\n\nWith \\c \\#define \\c osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file\nthat is used throughout a project. If you are using the \\b CMSIS-RTOS \\b 'main' \\b function user code template, such a header\nfile (called \\c osObjects.h) will be added automatically to the project:\n\n\\b Code \\b Example\n\\code\n/*----------------------------------------------------------------------------\n * osObjects.h: CMSIS-RTOS global object definitions for an application\n *----------------------------------------------------------------------------\n *\n * This header file defines global RTOS objects used throughout a project\n *\n * #define osObjectsPublic indicates that objects are defined; without that\n * definition the objects are defined as external symbols.\n *\n *--------------------------------------------------------------------------*/\n \n#ifndef __osObjects\n#define __osObjects\n \n#if (!defined (osObjectsPublic))\n#define osObjectsExternal          // define RTOS objects with extern attribute\n#endif\n \n#include <cmsis_os.h>              // CMSIS RTOS header file\n \n// global 'thread' functions -------------------------------------------------\nextern void  thread_sample (void const *argument);       // function prototype\nosThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);\n \n// global 'memory pools' -----------------------------------------------------\nosPoolDef(MyPool, 10, long);\n \n#endif  // __osObjects\n\\endcode\n\nThis header file defines all objects when included in a C/C++ source file. When \\c \\#define \\c osObjectsExternal is present\nbefore the header file, the objects are defined as external symbols. A single consistent header file can therefore be used\nthroughout the whole project.\n\n\\b Code \\b Example\n\\code\n#include \"osObjects.h\"   // Definition of the CMSIS-RTOS objects\n\\endcode\n\n\n\\section UsingIRQs Using IRQ Interrupts\n\nThe CMSIS-RTOS RTX kernel uses the following interrupts:\n- Timer interrupt (SysTick or alternative peripheral timer) to generate periodic timer ticks\n- SVC (Supervisor Call) when calling the majority of RTX functions from \\b Thread mode\n- PendSV (request for system-level service) when calling certain RTX functions from \\b Handler mode\n\nInterrupts can be used without limitation. Interrupt priority grouping can be used with some restrictions:\n- IRQ interrupts are never disabled by RTX Kernel for Armv7-M architectures (Cortex-M3/M4/M7).\n- Software interrupt 0 is used by RTX and cannot be used in an application.\n- RTX uses its own SVC Handler which is automatically linked from the library. \\ref svcFunctions explains how to use a custom\n  SVC table.\n- When interrupt \\b priority \\b grouping is used, the PRIGROUP must be set before the \\ref osKernelInitialize() function is\n  called (usually in the SystemInit() function in the system_<i>device</i>.c file). The kernel reads the value of PRIGROUP to\n  correctly set internal interrupt pre-emption priorities.\n- Allowed values for \\b PRIGROUP are from 0 to 6. The PRIGROUP value 7 will cause RTX to fail.\n- The lowest two pre-emption priorities are reserved for RTX kernel, all remaining pre-emption priorities are available to\n  be used in an application.\n- Do not change the priority used by the RTX kernel. If this cannot be avoided, ensure that the preempt priority of\n  SysTick/PendSV is lower than SVC.\n- Check the <b>main stack size</b> configured from the device startup file if you see sporadic crashes of your application.\n  Supervisor Calls (SVCs) are used when calling RTX functions from Thread mode. All SVC calls use the main stack.\n*/\n\n\n/* ========================================================================================================================== */\n/**\n\\page configure Configure RTX\n\nThe file \\ref RTX_Conf_CM \"RTX_Conf_CM.c\" is used to define the configuration parameters of CMSIS-RTOS RTX. This file must be\npart of every project that is using the CMSIS-RTOS RTX kernel.\n\nThe configuration file uses\n<b>Configuration Wizard Annotations</b>. Refer to <b>Pack - Configuration Wizard Annotations</b> for details.\nDepending on the development tool that is used, this might lead to a more user friendly graphical representation of the\nsettings. The following is a screenshot of the same configuration file using µVision's Configuration Wizard view:\n\n\\image html config_wizard.png \"RTX_Conf_CM.c in Configuration Wizard View\"\n\nThe configuration options are explained on these pages:\n- \\subpage threadConfig\n- \\subpage timerTick\n- \\subpage systemConfig\n\nOther configuration options not covered by the Configuration Wizard are explained here:\n- \\subpage lowPower\n- \\subpage svcFunctions\n*/\n\n/* ========================================================================================================================== */\n/**\n\\page threadConfig Thread Configuration\n\nThe CMSIS-RTOS RTX provides several parameters for the thread configuration.\n - \\ref stackConfig\n - \\ref stackCheck\n - \\ref processorMode\n\n\\section stackConfig Configuration of Thread count and Stack Space\n\n\\ref osThreadDef defines a thread function. The parameter \\a stacksz specifies thereby the stack requirements of this\nthread function. CMSIS-RTOS RTX defines two methods for defining the stack requirements:\n - when \\a stacksz is 0, a fixed-size memory pool is used to for the thread stack.  In this case \\b OS_STKSIZE specifies the\n   stack size for the thread function.\n - when \\a stacksz is not 0, the thread stack is allocated from a user space. The size of this user space is specified with\n   \\b OS_PRIVSTKSIZE.\n\nThe CMSIS-RTOS RTX kernel uses a separate stack for each thread it creates. However, before the kernel is started by the\n\\ref osKernelInitialize() function, the main stack size that is configured in the file startup_<i>device</i>.s is used.\n\nMain stack is also used when:\n- the user application calls the majority of RTX functions from Thread mode (ending up in an SVC call)\n- running from handlers (user interrupt of exception handlers like SVCm PendSV, Faults, etc.)\n\n|Name                                                               |\\#define         |Description|\n|-------------------------------------------------------------------|-----------------|-----------|\n|Number of concurrent running user threads                          |\\c OS_TASKCNT    |Indicates the maximum number of threads that will run at the same time (including main).|\n|Default Thread stack size [bytes]                                  |\\c OS_STKSIZE    |Specifies the default stack size (in words) for threads that are defined with osThreadDef \\a stacksz = 0.|\n|Main Thread stack size [bytes]                                     |\\c OS_MAINSTKSIZE|Is the stack requirement (in words) for the main function that is started by default as an RTOS thread.|\n|Number of threads with user-provided stack size                    |\\c OS_PRIVCNT    |Indicates the number of threads that are defined with \\ref osThreadDef \\a stacksz != 0 (excluding main). \\a stacksz specifies the stack size requirement of that thread.|\n|Total stack size [bytes] for threads with user-provided stack size |\\c OS_PRIVSTKSIZE|Is the combined stack requirement (in words) of all threads that are defined with with \\ref osThreadDef \\a stacksz != 0 (excluding main).|\n|\\ref stackCheck                                            |\\c OS_STKCHECK   |If a stack overflow is detected at a thread switch, the function \\b os_error with error code = 1 is called.  By default, this function is implemented as endless loop and will practically stop code execution.|\n|\\ref stackUsage                                              |\\c OS_STKINIT    |Initializes the thread stack with a watermark pattern that can be used to determine the maximum stack usage within each thread.|\n|\\ref processorMode                                |\\c OS_RUNPRIV    |Controls the processor mode (privileged/unprivileged)|\n\n\\section stackCheck Stack Overflow Checking\n\nCMSIS-RTOS RTX implements a software stack overflow checking that traps stack overruns. Stack is used for return addresses\nand automatic variables and extensive usage or incorrect stack configuration may cause a stack overflow. Software stack\noverflow checking is controlled with the <b>\\#define OS_STKCHECK</b>.\n\nIf a stack overflow is detected, the function \\b os_error with error code = 1 is called.  By default, this function is\nimplemented as endless loop and will practically stop code execution.\n\n\\section stackUsage Stack Usage Watermark\n\nThe total stack size of an application needs to be as small as possible in a memory restricted embedded system. To be able to\nset the smallest stack size for every thread, the developer needs to know the maximum stack usage over the runtime of the\napplication.\n\nThe \\b Stack \\b Usage \\b Watermark feature support this by initializing the thread stack with a watermark pattern (0xCC) when\na thread is created. This allows the debugger to determine the maximum stack usage for each thread.\n\n\\image html stack_usage_watermark.png \"System and Thread Viewer showing current and maximum stack usage\"\n\nStack usage watermark is controlled with the <b>\\#define OS_STKINIT</b>. Setting this \\c \\#define increases significantly the\nexecution time of \\ref osThreadCreate (depending on thread stack size).\n\n\\section processorMode Processor Mode for Thread Execution\n\nCMSIS-RTOS RTX allows to execute threads in unprivileged or privileged processor mode. The processor mode is controlled with\nthe <b>\\#define OS_RUNPRIV</b>.\n\nIn unprivileged processor mode, the software:\n - has limited access to the MSR and MRS instructions, and cannot use the CPS instruction.\n - cannot access the system timer, NVIC, or system control block.\n - might have restricted access to memory or peripherals.\n\nIn privileged processor mode the software can use all the instructions and has access to all resources.\n\n\\note It is recommended to use the privileged processor mode.\n*/\n\n/* ========================================================================================================================== */\n/**\n\\page timerTick RTX Kernel Tick Timer Configuration\n\nThe CMSIS-RTOS RTX functions provide delays in units of milliseconds that are derived from the RTX Timer Tick.\nIt is therefore recommended to configure the RTX Timer Tick to generate a 1 millisecond interval. \nConfiguring a longer RTX Timer Tick may reduce energy consumption, but has impacts on the granularity of the timeouts.\n\n|Name                                            |\\#define         |Description|\n|------------------------------------------------|-----------------|-----------|\n| Use Cortex-M SysTick timer as RTX Kernel Timer |\\c OS_SYSTICK    | Selects the Cortex-M SysTick timer as RTX kernel timer. In this case, the RTX kernel configures the SysTick timer clock source as processor clock. Therefore the value <b>OS_CLOCK</b> should be identical with the value of the CMSIS variable <b>SystemCoreClock</b>.|\n| RTOS Kernel Timer input clock frequency [Hz]   |\\c OS_CLOCK      |Specifies the Cortex-M processor clock frequency in Hz. This value is used to calculate the RTX kernel timer reload value.|\n| RTX Timer tick interval value [us]             |\\c OS_TICK       |Specifies the RTX Timer Tick interval in microseconds (us). This value is used to calculate timeout values. When the SysTick core timer is enabled the value is also used to configure the SysTick timer. It is recommended to configure the RTX Timer tick to 1000 us which results in a timeout granularity of 1 millisecond.|\n\n\\section AltTimer Usage of an Alternate Timer as RTX Kernel Timer\n\nWith <b>\\#define OS_SYSTICK 0</b> an alternative timer is selected as RTX kernel timer.\n\nFour functions in the \\ref RTX_Conf_CM \"RTX_Conf_CM.c\" file need to be adapted for using an alternative hardware timer.\n\n - \\ref os_tick_init provides the initialization function for the alternative hardware timer.\n - \\ref os_tick_val returns the current value of the alternative hardware timer.\n - \\ref os_tick_ovf returns the overflow flag of the alternative hardware timer.\n - \\ref os_tick_irqack is an interrupt acknowledge function that is called to confirm the alternative hardware timer\n   interrupt.\n - \\ref OS_Tick_Handler needs to be called as the hardware timer interrupt function; the startup code should be modified to\n   this function.\n\n<b>Configuration Code:</b>\n\\code\n#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer\n \n/*--------------------------- os_tick_init ----------------------------------*/\n \n/// \\brief Initializes an alternative hardware timer as RTX kernel timer\n/// \\return                             IRQ number of the alternative hardware timer\nint os_tick_init (void) {\n  return (-1);  /* Return IRQ number of timer (0..239) */\n}\n \n/*--------------------------- os_tick_val -----------------------------------*/\n \n/// \\brief Get alternative hardware timer's current value (0 .. OS_TRV)\n/// \\return                             Current value of the alternative hardware timer\nuint32_t os_tick_val (void) {\n  return (0);\n}\n \n/*--------------------------- os_tick_ovf -----------------------------------*/\n \n/// \\brief Get alternative hardware timer's  overflow flag\n/// \\return                             Overflow flag\\n\n///                                     - 1 : overflow\n///                                     - 0 : no overflow\nuint32_t os_tick_ovf (void) {\n  return (0);\n}\n \n/*--------------------------- os_tick_irqack --------------------------------*/\n \n/// \\brief Acknowledge alternative hardware timer interrupt\nvoid os_tick_irqack (void) {\n  /* ... */\n}\n \n#endif   // (OS_SYSTICK == 0)\n\\endcode\n\n\\anchor OS_Tick_Handler\nOS_Tick_Handler\n---------------\nThe function \\b OS_Tick_Handler handles the RTX tick interval interrupts. It is used if you are using an alternate timer as\nthe RTX tick timer.\n\nThe \\b OS_Tick_Handler is an interrupt handler function, which runs the OS task scheduler. It is called by the Nested\nVectored Interrupt Controller (NVIC) on the alternate timer's interrupt, and cannot be called as a regular C-function. It\nmust be entered into the Interrupt Table in startup file. The default Cortex-M interrupt vector must be replaced by\n\\b OS_Tick_Handler.\n\n\\code\n; Vector Table Mapped to Address 0 at Reset\n \n                AREA    RESET, DATA, READONLY\n                EXPORT  __Vectors\n \n                IMPORT  OS_Tick_Handler\n \n__Vectors       DCD     __initial_sp              ; Top of Stack\n                DCD     Reset_Handler             ; Reset Handler\n                DCD     NMI_Handler               ; NMI Handler\n                DCD     HardFault_Handler         ; Hard Fault Handler\n                DCD     MemManage_Handler         ; MPU Fault Handler\n                DCD     BusFault_Handler          ; Bus Fault Handler\n                DCD     UsageFault_Handler        ; Usage Fault Handler\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     SVC_Handler               ; SVC Handler\n                DCD     DebugMon_Handler          ; Debug Monitor Handler\n                DCD     0                         ; Reserved\n                DCD     PendSV_Handler            ; PendSV Handler\n                DCD     SysTick_Handler           ; SysTick Handler\n \n                ; External Interrupts\n                DCD     WDT_IRQHandler            ; 16: Watchdog Timer\n                DCD     TIMER0_IRQHandler         ; 17: Timer0\n                ...\n                DCD     I2S_IRQHandler            ; 43: I2S\n                DCD     ENET_IRQHandler           ; 44: Ethernet\n                DCD     OS_Tick_Handler           ; 45: Repetitive Interrupt Timer\n                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM\n                ...\n\\endcode\n*/\n\n/* ========================================================================================================================== */\n/**\n\\page systemConfig System Configuration\n\nThe CMSIS-RTOS RTX provides system-wide settings for:\n - \\ref RoundRobin\n - \\ref UserTimer\n \n\\section RoundRobin Settings for Round-Robin Thread Switching\n\nCMSIS-RTOS RTX may be configured to use round-robin multitasking thread switching. Round-robin allows quasi-parallel\nexecution of several threads of the \\a same priority. Threads are not really executed concurrently, but are scheduled where\nthe available CPU time is divided into time slices and CMSIS-RTOS RTX assigns a time slice to each thread. Because the time\nslice is typically short (only a few milliseconds), it appears as though threads execute simultaneously.\n\nRound-robin thread switching functions as follows:\n- the tick is preloaded with the timeout value when a thread switch occurs\n- the tick is decremented (if not already zero) each system tick if the same thread is still executing\n- when the tick reaches 0 it indicates that a timeout has occurred. If there is another thread ready with the \\a same\n  priority, then the system switches to that thread and the tick is preloaded with timeout again.\n\nIn other words, threads execute for the duration of their time slice (unless a thread's time slice is given up). Then, RTX\nswitches to the next thread that is in \\b READY state and has the same priority. If no other thread with the same priority is\nready to run, the current running thread resumes it execution.\n\n\\note When switching to higher priority threads, the round-robin timeout value is reset.\n\nRound-Robin multitasking is controlled with the <b>\\#define OS_ROBIN</b>. The time slice period is configured (in RTX Timer\nticks) with the <b>\\#define OS_ROBINTOUT</b>.\n\n<b>Code Example:</b>\n\nThe following example shows a simple CMSIS-RTOS RTX program that uses Round-Robin Multitasking. \nThe two threads in this program are counter loops. RTX starts executing job 1, which is the function named job1.\nThis function creates another task called job2. After job1 executes for its time slice, RTX switches to job2. \nAfter job2 executes for its time slice, RTX switches back to job1. This process repeats indefinitely.\n\n\\code\n#include \"cmsis_os.h\"                      // CMSIS-RTOS header file\n \nint counter1;\nint counter2;\n \nvoid job1 (void const *arg) {\n  while (1) {                              // loop forever\n    counter1++;                            // update the counter\n  }\n}\n \nvoid job2 (void const *arg) {\n  while (1) {                              // loop forever\n    counter2++;                            // update the counter\n  }\n}\n \nosThreadDef (job1, osPriorityAboveNormal, 1, 0);\nosThreadDef (job2, osPriorityAboveNormal, 1, 0);\n \nint main (void) {\n  osKernelInitialize ();                   // setup kernel\n  osThreadCreate (osThread(job1), NULL);   // create threads\n  osThreadCreate (osThread(job2), NULL); \n  osKernelStart ();                        // start kernel\n}\n\\endcode\n\n\\note\nRather than waiting for a thread time slice to expire, use CMSIS-RTOS functions to signal to the RTX kernel that it can\nswitch to another task. The function \\ref osThreadYield passes control to other threads without Round-Robin Multitasking.\n\n\n\\section UserTimer User Timer Management\n\nCMSIS-RTOS RTX supports \\ref CMSIS_RTOS_TimerMgmt which provides timer callback functions. The \\ref CMSIS_RTOS_TimerMgmt is\nconfigured with the following \\a \\#defines:\n\n|Name                            |\\#define        |Description|\n|--------------------------------|----------------|-----------|\n|User Timers                     |\\c OS_TIMERS    | Enables the \\ref CMSIS_RTOS_TimerMgmt.  When disabled, the \\b osTimerThread is not created.|\n|Timer Thread Priority           |\\c OS_TIMERPRIO | Specifies the priority of the osTimerThread that executes the timer callback functions.|\n|Timer Thread stack size [bytes] |\\c OS_TIMERSTKSZ| Specifies the stack size (in words) for the the \\b osTimerThread.|\n|Timer Callback Queue size       |\\c OS_TIMERCBQS | Specifies the maximum number of concurrent timer callbacks.|\n\n \\note\n Refer to \\ref RTX_Threads for more information about the \\b osTimerThread.\n \n\\section ISRFIFO ISR FIFO Queue size\nISR functions store requests to this buffer, when they are called from the interrupt handler. The default value for\n<b>\\#define OS_FIFOSZ</b> is 16.\n*/\n\n/* ========================================================================================================================== */\n/**\n\\page lowPower Configuration for Low-Power Modes\n\nThe system thread \\b os_idle_demon can be use to switch the system into a low-power mode.  The easiest form to enter a\nlow-power mode is the execution of the \\c __WFE function that puts the processor into a sleep mode where it waits for an\nevent.\n\n<b>Configuration Example:</b>\n\n\\code\n#include \"device.h\"                     /* Device definitions                 */\n \nvoid os_idle_demon (void) {\n  /* The idle demon is a system thread, running when no other thread is       */\n  /* ready to run.                                                            */\n \n  for (;;) {\n    __WFE();                            /* Enter sleep mode                   */\n  }\n}\n\\endcode\n\n\\note\n\\c __WFE() is not available at every Cortex-M implementation. Check device manuals for availability.\n\n\\section TickLess Tick-less operation\n\nCMSIS-RTOS RTX provides extension for tick-less operation which is useful for applications that use extensively low-power\nmodes where the SysTick timer is also disabled. To provide a time-tick in such power-saving modes a wake-up timer is used to\nderive timer intervals. The RTX functions \\ref os_suspend and \\ref os_resume control the tick-less operation.\n\nUsing this functions allows the RTX thread scheduler to stop the periodic kernel tick interrupt. When all active threads\nare suspended, the system enters power-down and calculates how long it can stay in this power-down mode. In the power-down\nmode the processor and potentially peripherals can be switched off. Only a wake-up timer must remain powered, because this\ntimer is responsible to wake-up the system after the power-down period expires.\n\nThe tick-less operation is controlled from the \\ref os_idle_demon thread. The wake-up timeout value is set before the system\nenters the power-down mode. The function \\ref os_suspend calculates the wake-up timeout measured in RTX Timer Ticks; this\nvalue is used to setup the wake-up timer that runs during the power-down mode of the system.\n\nOnce the system resumes operation (either by a wake-up time out or other interrupts) the RTX thread scheduler is started with\nthe function \\ref os_resume. The parameter \\a sleep_time specifies the time (in RTX Timer Ticks) that the system was in\npower-down mode.\n\n\\b Code \\b Example\n\\code\n#include \"LPC11Uxx.h\"                   /* LPC11Uxx definitions               */\n \nvoid os_idle_demon (void) {\n  /* The idle demon is a system thread, running when no other thread is       */\n  /* ready to run.                                                            */\n  unsigned int sleep;\n  unsigned int tc;\n \n  LPC_SYSCON->SYSAHBCLKCTRL |=  (1UL << 15) |  /* Enable clock for WWDT       */\n                                (1UL << 19);   /* Enable clock for Pin IRQ    */\n \n  LPC_SYSCON->PINTSEL[0]     =   1;            /* P0.1 selected as INT0 IRQ   */\n  LPC_SYSCON->STARTERP0     |=  (1UL <<  0);   /* Enable INT0 wake-up         */\n  LPC_SYSCON->STARTERP1     |=  (1UL << 12);   /* Enable WWDT wake-up         */\n \n  LPC_SYSCON->WDTOSCCTRL     =  (3   <<  0) |  /* WDOSC DIVSEL=3              */\n                                (2   <<  5);   /* WDOSC FREQ=0.8MHz           */\n  LPC_SYSCON->PDRUNCFG      &= ~(1UL <<  6);   /* Power-up WDT Oscillator     */\n  LPC_SYSCON->PDSLEEPCFG    &= ~(1UL <<  6);   /* Power WDT Oscillator in PD  */\n \n  LPC_WWDT->CLKSEL           =  (1UL <<  0) |  /* Select WDOSC as Clock       */\n                                (1UL << 31);   /* Lock selection              */\n  LPC_WWDT->WARNINT          =   1000;         /* WDT Warning IRQ value       */\n  LPC_WWDT->MOD              =  (1UL <<  0);   /* Enable WDT                  */\n \n  NVIC_EnableIRQ(FLEX_INT0_IRQn);              /* Enable INT0 IRQ (wake-up)   */\n  NVIC_EnableIRQ(WDT_IRQn);                    /* Enable WWDT IRQ (wake-up)   */\n \n  for (;;) {\n  /* HERE: include optional user code to be executed when no task runs.*/\n    sleep = os_suspend();                      /* Suspend RTX thread scheduler */\n \n    if (sleep) {                               /* How long can we sleep?       */\n      /* \"sleep\" is in RTX Timer Ticks which is 10ms in this configuration     */\n       \n      /* Setup WDT wake-up: WDT ticks @25kHz (FREQ/2/(DIVSEL+1)/4) */\n      tc = (sleep * 250) + 1000;\n      LPC_WWDT->TC   = tc;\n      LPC_WWDT->FEED = 0xAA;\n      LPC_WWDT->FEED = 0x55;\n \n      /* Enter Power-down mode */\n      LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG;  /* Power after wake-up   */\n      LPC_PMU->PCON = 0x02;                    /* Select Power-down mode       */\n      SCB->SCR = (1UL << 2);                   /* Set SLEEPDEEP                */\n      __WFE();                                 /* Enter Power-down mode        */\n      \n      /* After Wake-up */\n      sleep = (tc - LPC_WWDT->TV) / 250;\n    }\n \n    os_resume(sleep);                          /* Resume RTX thread scheduler  */\n  }\n}\n\\endcode\n\n\\note\n\\c __WFE() is not available at every Cortex-M implementation. Check device manuals for availability.\n*/\n\n/* ========================================================================================================================== */\n/**\n\\page svcFunctions SVC Functions\nSupervisor Calls (SVC) are exceptions targeted at software and operating systems for generating system function calls. They\nare sometimes called software interrupts. For example, instead of allowing user programs to directly access hardware, an\noperating system may provide access to hardware through an SVC. So when a user program wants to use certain hardware, it\ngenerates the SVC exception using SVC instructions, and then the software exception handler in the operating system is\nexecuted and provides the requested service to the user application. In this way, access to hardware is under the control of\nthe OS, which can provide a more robust system by preventing the user applications from directly accessing the hardware.\n\nSVC can also make software more portable because the user application does not need to know the programming details of the\nunderlying hardware. The user program will only need to know the application programming interface (API) function ID and\nparameters; the actual hardware-level programming is handled by device drivers.\n\nSVCs run in \\b Privileged \\b Handler mode of the \\b Cortex-M core. SVC functions accept arguments and can return values.\nThe functions are used in the same way as other functions; however, differences are hidden to the user. The ARMCC handles the\ndifferences and generates code instructions to call SVC functions. SVC functions are called by executing the SVC instruction.\nWhen executing SVC instructions, the controller changes to the Privileged Handler Mode.\n\nInterrupts are <b>not disabled</b> in this mode. To protect SVC function from interrupts, you need to include the\ndisable/enable intrinsic functions \\b __disable_irq() and \\b __enable_irq() in your code.\n\nYou can use SVC functions to access \\b protected \\b peripherals, for example, to configure NVIC and interrupts. \nThis is required if you run tasks in unprivileged (protected) mode and you need to change interrupts from the task.\n\nTo implement SVC functions in your CMSIS-RTOS RTX kernel project, you need to:\n-#  Copy the file \\b SVC_Table.s to your project folder and include it into your project. This file is available as a source\n    code template. \n-#  Declare a function with a \\b __svc(x) attribute. Use the first SVC number, starting from 1, that is free.\n    \\code\n    void __svc(1)  inc_5bit (U32 *cp);\n    \\endcode\n-#  Write a function implementation and convert the function name into a \\b __SVC_x function name. \n    Later, this name is referenced by the linker from the \\b SVC_Table.s module.\n    You also need to disable/enable interrupts.\n    \\code\n    void __SVC_1            (U32 *cp) {\n      // A protected function to increment a 5-bit counter. \n      __disable_irq();\n      *cp = (*cp + 1) & 0x1F;\n      __enable_irq();\n    }\n    \\endcode\n-#  Add the function \\b __SVC_x to the SVC function table in the \\b SVC_Table.s module.\n    First import it from other modules:\n    \\code\n    ; Import user SVC functions here.\n                   IMPORT  __SVC_1\n    \\endcode\n    Then, add a reference to it into the table:\n    \\code\n    ; Insert user SVC functions here. SVC 0 used by RTL Kernel.\n                DCD     __SVC_1                 ; user SVC function\n    \\endcode\n-#  Your \\b SVC function should now look like this:\n    \\code\n    void __svc(1)  inc_5bit (U32 *cp);\n    void __SVC_1            (U32 *cp) {\n      // A protected function to increment a 5-bit counter. \n      __disable_irq();\n      *cp = (*cp + 1) & 0x1F;\n      __enable_irq();\n    }\n    \\endcode\n    \n\\note\n- SVC function \\b 0 is \\b reserved for the CMSIS-RTOS RTX kernel.\n- Do not leave gaps when numbering SVC functions. They must occupy a \\b continuous range of numbers starting from 1.\n- SVC functions can still be interrupted.\n- CMSIS-RTOS RTX must not be called before the main() function.\n*/\n\n/* ========================================================================================================================== */\n/** \n\\page exampleRTX_Tutorial RTX Tutorial\n\nThe tutorial is an excerpt of Trevor Martin's book\n<a href=\"http://store.elsevier.com/product.jsp?isbn=9780080982960&pagename=search\" target=\"_blank\">The Designer's Guide to the Cortex-M Processor Family</a>.\nIt is accompanied by a Pack file that contains the example projects that are discussed in the tutorial.\n\nThe tutorial is available as a Software Pack from\n<a href=\"https://www.keil.com/dd2/pack\" target=\"_blank\">https://www.keil.com/dd2/pack</a>. On the page, browse to \\b Hitex and\nselect the Pack described as \"An Introduction to using CMSIS RTOS for Cortex-M Microcontrollers\". Download and install the\nPack which contains all example projects referenced in the\n<a class=\"el\" href=\"CMSIS_RTOS_Tutorial.pdf\">CMSIS_RTOS_Tutorial.pdf</a>.\n*/\n\n\n/* ========================================================================================================================== */\n/** \n\\page creating_RTX_LIB Building the RTX Library\n\nThe CMSIS Pack contains a µVision project for building the set of CMSIS-RTOS RTX libraries. This project can also be used as\na reference for building the CMSIS-RTOS RTX libraries using a tool-chain of your choice.\n\n-# Open the project \\b RTX_Lib_CM.uvproj from the pack folder <b>CMSIS/RTOS/RTX/SRC/ARM/</b> in uVision.\n-# Select the project target that matches your device's processor core. \n   \\n The project provides target configuration for all supported Cortex-M targets supported by RTX. \n\\n Note: The targets <b>CMF4_LE</b> (Little Endian) and <b>CMF4_BE</b> (Big Endian) shall be used for Cortex-M4 as well as\n   Cortex-M7 based devices with FPU.\n-# You can find out about the required preprocessor defines in the dialogs <b>Options for Target - C/C++</b> and\n   <b>Options for Target - Asm</b>.\n-# From the <b>Project</b> window you find the list of source files required for a complete library build.\n\n\\image html own_lib_projwin.png \"Project with files for Cortex-M4 cores\"\n*/\n\n\n/* ========================================================================================================================== */\n// Reference \n/** \n * \\addtogroup CMSIS_RTOS CMSIS-RTOS API\n * \\brief This section describes the CMSIS-RTOS API. \n * \\details The CMSIS-RTOS is a generic API layer that interfaces to an existing RTOS kernel.\n *  @{\n */\n\n/// @} \n\n\n/** \n\\addtogroup RTX_Global_Functions RTX Specific Functions\n\\brief This section describes the functions that are specific to CMSIS-RTOS RTX. \n\\details \nThe RTX kernel can be customized for different application requirements:\n- If you are depending on the \\ref lowPower \"lowest power consumption\" possible, you need to adapt the function\n  \\ref os_idle_demon to send the system to sleep mode as often as possible. In addition, use the\n  \\ref TickLess \"low power RTX extensions\" \\ref os_suspend and \\ref os_resume to suspend the RTX scheduler and to stop the\n  SysTick timer.\n- If you need to specify an \\ref AltTimer \"alternate hardware timer\" as the system tick timer, you need to\n  -# implement the functions \\ref os_tick_init, \\ref os_tick_ovf, \\ref os_tick_val, and optionally the function\n     \\ref os_tick_irqack.\n  -# replace the alternate timer interrupt vector with the \\ref OS_Tick_Handler in the Interrupt Vector Table in startup\n     file.\n- If you try to find a \\b runtime \\b error, use the function \\ref os_error to debug the error.\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn void os_idle_demon (void)\nThe function \\b os_idle_demon is executed by the RTX kernel, when no other threads are ready to run. By default, this task\nis an empty end-less loop that does nothing. It only waits until another task becomes ready to run. You may change the code\nof the \\b os_idle_demon function to put the CPU into a power-saving or idle mode.\n\nThe default stack size for this task is defined in the file \\b \\#RTX_Conf_CM.c. Refer to \\ref threadConfig entry <b>Default Thread stack size [bytes]</b>.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\nvoid os_idle_demon (void) {\n \n  for (;;) {\n  __WFI(); // wait for interrupt\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn int os_tick_init (void)\nThe function \\b os_tick_init initializes an alternate hardware timer as the system tick timer and starts it. If you setup\nOS_SYSTICK to 0, this function will be available for adding the alternate timer. It returns the interrupt number of the\nalternative hardware timer.\n\n\\note - When using an alternate timer, you must enter the \\ref OS_Tick_Handler in the interrupt vector table in the startup\nfile.\n\n\\note - Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\n#include \"LPC43xx.h\"                    // Device header\n \nint os_tick_init (void) {\n  // Initialize hardware timer as system tick timer. \n \n  LPC_CCU1->CLK_M4_RITIMER_CFG = (1UL << 0);\n \n  LPC_RITIMER->COMPVAL = OS_TRV;     // Set match value\n  LPC_RITIMER->COUNTER = 0;          // Set count value to 0\n  LPC_RITIMER->CTRL    = (1UL << 3) |    // Timer enable\n                         (1UL << 2) |    // Timer enable for debug\n                         (1UL << 1) |    // Timer enable clear on match\n                         (1UL << 0);     // Clear interrupt flag\n  \n  return (M0_RITIMER_OR_WWDT_IRQn);  // Return IRQ number of timer (0..239) \n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn uint32_t os_tick_val (void)\nThe function \\b os_tick_val returns the current value of the alternate hardware timer specified by os_tick_init.\n\n\\note - When using an alternate timer, you must enter the \\ref OS_Tick_Handler in the interrupt vector table in the startup\nfile.\n\\note - Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\n#include \"LPC43xx.h\"                    // Device header\n \nuint32_t os_tick_val (void) {\n \n  return (LPC_RITIMER->COUNTER);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn uint32_t os_tick_ovf (void)\nThe function \\b os_tick_ovf returns the overflow flag of the alternate hardware timer specified by os_tick_init.\n\n\\note - When using an alternate timer, you must enter the \\ref OS_Tick_Handler in the interrupt vector table in the startup\nfile.\n\\note - Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\n#include \"LPC43xx.h\"                    // Device header\n \nuint32_t os_tick_ovf (void) {\n \n  return (LPC_RITIMER->CTRL);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn void os_tick_irqack (void)\nThe function \\b os_tick_irqack acknowledges the peripheral timer interrupt.\n\n\\note - When using an alternate timer, you must enter the \\ref OS_Tick_Handler in the interrupt vector table in the startup\nfile.\n\\note - Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\n#include \"LPC43xx.h\"                    // Device header\n \nvoid os_tick_irqack (void) {\n \n  LPC_RITIMER->CTRL |= (1UL << 0);    // Clear interrupt flag\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn void os_error (uint32_t error_code)\nSome system error conditions can be detected during runtime. If the RTX kernel detects a runtime error, it calls the runtime\nerror function \\b os_error.\n\nThe argument \\a error_code passes the actual error code to this function:\n\n|Error Code        |Description|\n|------------------|-----------|\n|OS_ERROR_STACK_OVF|The stack checking has detected a stack overflow for the currently running thread.|\n|OS_ERROR_FIFO_OVF |The ISR FIFO Queue buffer overflow is detected.|\n|OS_ERROR_MBX_OVF  |A mailbox overflow is detected for the function \\ref osMessagePut or \\ref osMailPut.|\n|OS_ERROR_TIMER_OVF|The User Timer Callback Queue overflow is detected.|\n\nThe function \\b os_error must contain an infinite loop to prevent further program execution. You can use an emulator to step\nover infinite loop and trace into the code introducing a runtime error. For the overflow errors this means you need to\nincrease the size of the object causing an overflow.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\nvoid os_error (uint32_t error_code) {\n \n  // HERE: include optional code to be executed on runtime error. \n  switch (error_code) {\n \n    case OS_ERROR_STACK_OVF:\n      // Stack overflow detected for the currently running task. \n      // Thread can be identified by calling svcThreadGetId().   \n      break;\n \n    case OS_ERROR_FIFO_OVF:\n      // ISR FIFO Queue buffer overflow detected. \n      break;\n \n    case OS_ERROR_MBX_OVF:\n      // Mailbox overflow detected. \n      break;\n \n    case OS_ERROR_TIMER_OVF:\n      // User Timer Callback Queue overflow detected. \n      break;\n  }\n  for (;;);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn uint32_t os_suspend (void)\nThe function \\b os_suspend suspends the RTX task scheduler. The function calculates the time, for how long the system is\nallowed to power-down, and locks the task scheduler. When the function returns, the task switches are disabled. For normal\nRTX operation, after calling \\b os_suspend, you must call the \\ref os_resume function to re-enable the OS task scheduler.\n\n\\note\n- You can call this function from the idle task only.\n- When the system is in power-down, the system tick timer is not running.\n- Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\nThe low power RTX is controlled from the \\ref os_idle_demon. The peripheral wake-up timer must be initialized before the\nsystem enters an endless loop. \\b os_suspend calculates the timeout until the first suspended task becomes ready, and returns\nthe timeout to the user:\n\n\\code\n  for (;;) {\n  sleep = os_suspend();\n\\endcode\n\nThe user sets-up a peripheral timer to sleep timeout and starts the timer. The timeout is measured in system ticks.\n\n\\code\nif (sleep) {\n  // Setup the wake-up timer ... \n\\endcode\n\nWhen the wake-up timer is set-up and running, the user puts the system in power-down mode. The wake-up timer must run also in\npower-down mode. All other peripherals and the CPU may power-down to reduce power.\n\n\\code\n  // Power-down the system ... \n  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\n  __WFE();\n\\endcode\n\nThe wake-up timer, when expired, generates the interrupt and wakes-up the system. Hence, it must run also in power-down mode.\nThe system resumes operation and needs to call the function \\ref os_resume. This function restores the RTX and re-enables the\nscheduler.\n\n\\code\n  // After Wake-up \n  sleep = (tc - LPC_WWDT->TV) / 250;\n}\nos_resume(sleep);\n\\endcode\n\nIf, for any reason, the system does not wake up immediately after the wake-up interrupt, the actual sleep time is checked and\nadjusted.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn void os_resume (uint32_t sleep_time)\nThe function \\b os_resume resumes the RTX task scheduler. You must call this function after you have called \\ref os_suspend\nto re-enable the task scheduler.\n\nThe argument \\a sleep_time specifies how long the system was in sleep or power-down mode. It is measured in number of system\nintervals.\n\n\\note\n- You can call this function from the idle task only.\n- When the system is in power-down, the system tick timer is not running.\n- Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\nSee \\ref os_suspend for a \\b Code \\b Example.\n*/\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Kernel Control Functions ====\n/** \n\\addtogroup CMSIS_RTOS_KernelCtrl Kernel Information and Control\n\\ingroup CMSIS_RTOS\n\\brief Provide version/system information and start the RTOS Kernel.\n\\details \nThe Kernel Information and Control function group allows to:\n  - obtain information about the system and the underlying kernel.\n  - obtain version information about the CMSIS-RTOS API.\n  - initialize of the RTOS kernel for creating objects.\n  - start the RTOS kernel and thread switching.\n  - check the execution status of the RTOS kernel.\n\nThe function \\b main is a special thread function that may be started at system initialization. In this case it has the\ninitial priority \\a osPriorityNormal.\n\nWhen reaching \\b main, it is necessary to:\n-# Call osKernelInitialize() to initialize the CMSIS-RTOS Kernel\n-# Setup device peripherals and create other RTOS objects using the \\b os*Create functions.\n-# Start the Kernel and begin thread switching by calling osKernelStart().\n\n<b>Code Example</b>\n\\code\nint main (void) {\n  osKernelInitialize ();                    // initialize CMSIS-RTOS\n \n  // initialize peripherals here\n \n  // create 'thread' functions that start executing,\n  // example: tid_name = osThreadCreate (osThread(name), NULL);\n \n  osKernelStart ();                         // start thread execution \n}\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFeature_MainThread\nA CMSIS-RTOS implementation may support to start thread execution with the function 'main'.\n - When \\ref osFeature_MainThread is 1 the RTOS offers to start with 'main'. The RTOS kernel is in this case already started.\n - When \\ref osFeature_MainThread is 0 the RTOS requires explicit start with \\ref osKernelStart.\n\n\\ref rtxImplementation \"CMSIS-RTOS RTX\" Setting: \\b osFeature_MainThread is 1\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFeature_SysTick\nA CMSIS-RTOS implementation may provide access to the RTOS kernel system timer. \n - When \\ref osFeature_SysTick is 1 access to the RTOS kernel system timer is provided with \\ref osKernelSysTick, \n   \\ref osKernelSysTickFrequency, and \\ref osKernelSysTickMicroSec.\n - When \\ref osFeature_SysTick is 0 access to the RTOS kernel system timer is not implemented.\n\n\\ref rtxImplementation \"CMSIS-RTOS RTX\" Setting: \\b osFeature_SysTick is 1\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osCMSIS\nVersion information of the CMSIS-RTOS API whereby major version is in bits [31:16] and sub version in bits [15:0].\nThe value 0x10000 represents version 1.00.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osCMSIS_KERNEL\nIdentifies the underlying RTOS kernel and version number.  The actual name of that define depends on the RTOS Kernel used in the implementation.\nFor example, \\b osCMSIS_FreeRTOS identifies the FreeRTOS kernel and the value indicates the version number of that kernel whereby the major version\nis in bits [31:16] and sub version in bits [15:0]. The value 0x10000 represents version 1.00.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osKernelSystemId\nDefines a string that identifies the underlying RTOS Kernel and provides version information.  The length of that string is limited to 21 bytes.\nA valid identification string is for example, <b>\"FreeRTOS V1.00\"</b>.\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osKernelInitialize (void)\nInitialize of the RTOS Kernel to allow peripheral setup and creation of other RTOS objects with the functions:\n   - \\ref osThreadCreate : Create a thread function.\n   - \\ref osTimerCreate : Define attributes of the timer callback function.\n   - \\ref osMutexCreate : Define and initialize a mutex.\n   - \\ref osSemaphoreCreate : Define and initialize a semaphore.\n   - \\ref osPoolCreate : Define and initialize a fix-size memory pool. \n   - \\ref osMessageCreate : Define and initialize a message queue.\n   - \\ref osMailCreate : Define and initialize a mail queue with fix-size memory blocks.\n\nThe RTOS kernel does not start thread switching until the function \\ref osKernelStart is called.\n\n\\note \nIn case that the RTOS Kernel starts thread execution with the function \\em main the function osKernelInitialize stops thread switching.\nThis allows you to setup the system to a defined state before thread switching is resumed with \\ref osKernelStart.\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nint main (void)  {\n  if (!osKernelRunning ())  {                    // if kernel is not running, initialize the kernel\n    if (osKernelInitialize () != osOK)  {        // check osStatus for other possible valid values\n      // exit with an error message\n    }\n  }\n  :\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osKernelStart (void)\nStart the RTOS Kernel and begin thread switching.\n\n\\note\nWhen the CMSIS-RTOS starts thread execution with the function \\em main this function resumes thread switching. The \\em main thread will continue executing\nafter \\ref osKernelStart.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the RTOS kernel has been successfully started.\n - \\em osErrorISR: \\ref osKernelStart cannot be called from interrupt service routines.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nint main (void)  {\n  if (osKernelInitialize () != osOK)  {          // check osStatus for other possible valid values\n    // exit with an error message\n  }\n \n  if (!osKernelRunning ())  {                    // is the kernel running ?\n    if (osKernelStart () != osOK)  {             // start the kernel\n                                                 // kernel could not be started\n    }\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn int32_t osKernelRunning (void)\nIdentifies if the RTOS kernel is started. For systems with the option to start the \\em main function as a thread this allows you to identify\nthat the RTOS kernel is already running.\n\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nint main (void) {                                // program execution starts here\n  if (osKernelRunning ())  {                    \n    :                                            // main is already a thread function\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn uint32_t osKernelSysTick (void)\n\nGet the value of the Kernel SysTick timer for time comparison. The value is a rolling \n32-bit counter that is typically composed of the kernel system interrupt timer value\nand an counter that counts these interrupts. \n\nThis function allows the implementation of timeout checks. These are for example\nrequired when checking for a busy status in a device or peripheral initialization routine.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n\nvoid SetupDevice (void)  {\n  uint32_t tick;\n  \n  tick = osKernelSysTick();                      // get start value of the Kernel system tick\n  Device.Setup ();                               // initialize a device or peripheral\n  do {                                           // poll device busy status for 100 microseconds\n    if (!Device.Busy) break;                     // check if device is correctly initialized\n  } while ((osKernelSysTick() - tick) < osKernelSysTickMicroSec(100));  \n  if (Device.Busy)  {              \n    ;                                            // in case device still busy, signal error\n  }\n                                                 // start interacting with device\n}\n\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osKernelSysTickFrequency\n\nSpecifies the frequency of the Kernel SysTick timer in Hz. The value is typically\nuse to scale a time value and is for example used in \\ref osKernelSysTickMicroSec.\n\n\\sa osKernelSysTick\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osKernelSysTickMicroSec\n\nAllows you to scale a microsecond value to the frequency of the Kernel SysTick timer.\nThis macro is typically used to check for short timeouts in polling loops.\n\n\\sa osKernelSysTick\n*/\n/// @}\n\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Thread Management Functions ====\n/** \n@addtogroup CMSIS_RTOS_ThreadMgmt Thread Management\n@ingroup CMSIS_RTOS\n@brief Define, create, and control thread functions.\n@details \nThe Thread Management function group allows defining, creating, and controlling thread functions in the system. The function\n\\b main is a special thread function that is started at system initialization and has the initial priority\n\\a osPriorityNormal.\n\n\\anchor ThreadStates\nThreads can be in the following states:\n - \\b RUNNING: The thread that is currently running is in the \\b RUNNING state. Only one thread at a time can be in this\n   state.\n - \\b READY: Threads which are ready to run are in the \\b READY state. Once the \\b RUNNING thread has terminated or is\n   \\b WAITING, the next \\b READY thread with the highest priority becomes the \\b RUNNING thread.\n - \\b WAITING: Threads that are waiting for an event to occur are in the \\b WAITING state.\n - \\b INACTIVE: Threads that are not created or terminated are in the \\b INACTIVE state. These threads typically consume no\n   system resources.\n\n\\image html \"ThreadStatus.png\" \"Thread State and State Transitions\"\n\nA CMSIS-RTOS assumes that threads are scheduled as shown in the figure <b>Thread State and State Transitions</b>. The thread\nstates change as follows:\n - A thread is created using the function \\ref osThreadCreate. This puts the thread into the \\b READY or \\b RUNNING state\n   (depending on the thread priority).\n - CMSIS-RTOS is pre-emptive. The active thread with the highest priority becomes the \\b RUNNING thread provided it does not\n   wait for any event. The initial priority of a thread is defined with the \\ref osThreadDef but may be changed during\n   execution using the function \\ref osThreadSetPriority.\n - The \\b RUNNING thread transfers into the \\b WAITING state when it is waiting for an event.\n - Active threads can be terminated any time using the function \\ref osThreadTerminate. Threads can terminate also by just\n   returning from the thread function. Threads that are terminated are in the \\b INACTIVE state and typically do not consume\n   any dynamic memory resources.  \n\n@{\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osThreadDef(name, priority, instances, stacksz)\nDefine the attributes of a thread functions that can be created by the function \\ref osThreadCreate using \\ref osThread. The\nargument \\a instances defines the number of times that \\ref osThreadCreate can be called for the same \\b osThreadDef.\n\n\\b Code \\b Example\n\\code\n#include \"cmsis_os.h\"\n \nvoid Thread (void const *arg);                             // function prototype for a Thread\nosThreadDef (Thread, osPriorityNormal, 3, 0);              // define Thread and specify to allow three instances\n \nvoid ThreadCreate_example (void) {\n  osThreadId id1, id2, id3;\n  \n  id1 = osThreadCreate (osThread (Thread), NULL);          // create the thread with id1\n  id2 = osThreadCreate (osThread (Thread), NULL);          // create the thread with id2\n  id3 = osThreadCreate (osThread (Thread), NULL);          // create the thread with id3\n  if (id1 == NULL) {                                       // handle thread creation for id1\n    // Failed to create the thread with id1\n  }\n  if (id2 == NULL) {                                       // handle thread creation for id2\n    // Failed to create the thread with id2\n  }\n  if (id3 == NULL) {                                       // handle thread creation for id3\n    // Failed to create the thread with id3\n  }\n  :\n  osThreadTerminate (id1);                                  // stop the thread with id1\n  osThreadTerminate (id2);                                  // stop the thread with id2\n  osThreadTerminate (id3);                                  // stop the thread with id3\n}\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osThread(name)\nAccess to the thread definition for the function \\ref osThreadCreate.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\typedef osPriority\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\nThe \\ref osPriority value specifies the priority for a thread. The default thread priority should be \\a osPriorityNormal.\nIf a Thread is active that has a higher priority than the currently executing thread, then a thread switch occurs immediately\nto execute the new task.\n\nTo prevent from a priority inversion, a CMSIS-RTOS compliant OS may optionally implement a <b>priority inheritance</b> method.\nA priority inversion occurs when a high priority thread is waiting for a resource or event that is controlled by a thread\nwith a lower priority. \n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)\nStart a thread function by adding it to the Active Threads list and set it to state \\b READY. \nThe thread function receives the \\a argument pointer as function argument when the function is started.\nWhen the priority of the created thread function is higher than the current \\b RUNNING thread, \nthe created thread function starts instantly and becomes the new \\b RUNNING thread.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Thread_1 (void const *arg);                           // function prototype for Thread_1\nosThreadDef (Thread_1, osPriorityNormal, 1, 0);            // define Thread_1\n \nvoid ThreadCreate_example (void) {\n  osThreadId id;\n  \n  id = osThreadCreate (osThread (Thread_1), NULL);         // create the thread\n  if (id == NULL) {                                        // handle thread creation\n    // Failed to create a thread\n  }\n  :\n  osThreadTerminate (id);                                  // stop the thread\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osThreadId osThreadGetId (void)\nGet the thread ID of the current running thread.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note Must not be used inside the idle daemon. This would lead to undefined behavior.\n\n<b>Code Example</b>\n\\code{.c}\nvoid ThreadGetId_example (void)  {\n  osThreadId id;                                           // id for the currently running thread\n   \n  id = osThreadGetId ();\n  if (id == NULL) {\n    // Failed to get the id; not in a thread\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osThreadTerminate  (osThreadId thread_id)\nRemove the thread function from the active thread list. If the thread is currently RUNNING the execution will stop.\n\n\\note In case that \\ref osThreadTerminate terminates the currently running task, the function never returns and other threads that are in the READY state are started.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the specified thread has been successfully terminated.\n - \\em osErrorParameter: thread_id is incorrect.\n - \\em osErrorResource: thread_id refers to a thread that is not an active thread.\n - \\em osErrorISR: \\ref osThreadTerminate cannot be called from interrupt service routines.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note Avoid calling the function with a \\em thread_id that does not exist or has been terminated already.\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Thread_1 (void const *arg);                           // function prototype for Thread_1\nosThreadDef (Thread_1, osPriorityNormal, 1, 0);            // define Thread_1\n\nvoid ThreadTerminate_example (void) {\n  osStatus status;\n  osThreadId id;\n \n  id = osThreadCreate (osThread (Thread_1), NULL);         // create the thread\n  :  \n  status = osThreadTerminate (id);                         // stop the thread\n  if (status == osOK) {\n    // Thread was terminated successfully\n  }\n  else {\n    // Failed to terminate a thread\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)\nChange the priority of an active thread.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the priority of the specified thread has been successfully changed.\n - \\em osErrorParameter: thread_id is incorrect.\n - \\em osErrorValue: incorrect priority value.\n - \\em osErrorResource: thread_id refers to a thread that is not an active thread.\n - \\em osErrorISR: \\ref osThreadSetPriority cannot be called from interrupt service routines.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n \n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Thread_1 (void const *arg)  {                         // Thread function\n  osThreadId id;                                           // id for the currently running thread\n  osPriority pr;                                           // thread priority\n  osStatus   status;                                       // status of the executed function\n   \n  :  \n  id = osThreadGetId ();                                   // Obtain ID of current running thread\n   \n  if (id != NULL) {\n    status = osThreadSetPriority (id, osPriorityBelowNormal);\n    if (status == osOK)  {\n      // Thread priority changed to BelowNormal\n    }\n    else {\n      // Failed to set the priority\n    }\n  }\n  else  {\n    // Failed to get the id\n  }\n  :  \n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osPriority osThreadGetPriority (osThreadId thread_id)\nGet the priority of an active thread. In case of a failure the value \\b osPriorityError is returned.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Thread_1 (void const *arg)  {                         // Thread function\n  osThreadId id;                                           // id for the currently running thread\n  osPriority priority;                                     // thread priority\n   \n  id = osThreadGetId ();                                   // Obtain ID of current running thread\n   \n  if (id != NULL)  {\n    priority = osThreadGetPriority (id);\n  }\n  else  {\n    // Failed to get the id\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osThreadYield  (void)\nPass control to the next thread that is in state \\b READY. If there is no other thread in the state \\b READY, \nthe current thread continues execution and no thread switching occurs.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the function has been correctly executed.\n - \\em osErrorISR: \\ref osThreadYield cannot be called from interrupt service routines.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Thread_1 (void const *arg)  {                         // Thread function\n  osStatus   status;                                       // status of the executed function\n  :\n  while (1)  {\n    status = osThreadYield();                              // \n    if (status != osOK)  {\n      // thread switch not occurred, not in a thread function\n    }\n  }\n}\n\\endcode\n*/\n\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Generic Wait Functions ====\n/** \n\\addtogroup CMSIS_RTOS_Wait Generic Wait Functions\n\\ingroup CMSIS_RTOS\n\\brief Wait for a time period or unspecified events.\n\\details \nThe Generic Wait function group provides means for a time delay and allow to wait for unspecified events.\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFeature_Wait\nA CMSIS-RTOS implementation may support the generic wait function \\ref osWait.\n - When \\ref osFeature_Wait is 1 a generic wait function \\ref osWait is available.\n - When \\ref osFeature_Wait is 0 no generic wait function \\ref osWait is available.\n\n\\ref rtxImplementation \"CMSIS-RTOS RTX\" Setting: \\b osFeature_Wait is 0\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osDelay (uint32_t millisec)\nWait for a specified time period in \\a millisec.\n\nThe \\ref CMSIS_RTOS_TimeOutValue \"millisec\" value specifies the number of timer ticks and is therefore an upper bound. The exact time delay depends\non the actual time elapsed since the last timer tick. \n\nFor a value of <b>1</b>, the system waits until the next timer tick occurs. That means that the actual time delay may be up to one timer tick less.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osEventTimeout: the time delay is executed.\n - \\em osErrorISR: \\ref osDelay cannot be called from interrupt service routines.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n \n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Thread_1 (void const *arg)  {               // Thread function\n  osStatus status;                               // capture the return status\n  uint32_t delayTime;                            // delay time in milliseconds\n \n  delayTime = 1000;                              // delay 1 second\n  :\n  status = osDelay (delayTime);                  // suspend thread execution\n    // handle error code\n  :  \n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osEvent osWait (uint32_t millisec)\n\nWait for any event of the type Signal, Message, Mail for a specified time period in \\a millisec.\nWhile the system waits, the thread that is calling this function is put into the state \\b WAITING.\nWhen \\a millisec is set to \\b osWaitForever, the function will wait for an infinite time until an event occurs.\n\nThe osWait function puts a thread into the state \\b WAITING and waits for any of the following events:\n - A \\b signal sent to that thread explicitly\n - A \\b message from a message object that is registered to that thread\n - A \\b mail from a mail object that is registered to that thread\n\n\\note This function is optional and may not be provided by all CMSIS-RTOS implementations.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osEventSignal: a signal event occurred and is returned.\n - \\em osEventMessage: a message event occurred and is returned.\n - \\em osEventMail: a mail event occurred and is returned.\n - \\em osEventTimeout: the time delay is executed.\n - \\em osErrorISR: \\ref osDelay cannot be called from interrupt service routines.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Thread_1 (void const *arg)  {               // Thread function\n  osEvent  Event;                                // capture the event\n  uint32_t waitTime;                             // wait time in milliseconds\n  \n  :\n  waitTime = osWaitForever;                      // special \"wait\" value\n  Event = osWait (waitTime);                     // wait forever and until an event occurred\n  switch (Event.status)  {\n    case osEventSignal:                          // Signal arrived\n        :                                        // Event.value.signals contains the signal flags\n      break;\n \n    case osEventMessage:                         // Message arrived\n        :                                        // Event.value.p contains the message pointer\n        :                                        // Event.def.message_id contains the message Id\n      break;\n \n    case osEventMail:                            // Mail arrived\n        :                                        // Event.value.p contains the mail pointer\n        :                                        // Event.def.mail_id contains the mail Id\n      break;\n \n    case osEventTimeout:                         // Timeout occurred\n      break;\n \n    default:                                     // Error occurred\n      break;\n  }\n  :\n}\n\\endcode\n*/\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Timer Management Functions ====\n/** \n\\addtogroup CMSIS_RTOS_TimerMgmt Timer Management\n\\ingroup CMSIS_RTOS\n\\brief Create and control timer and timer callback functions.\n\\details \nIn addition to the \\ref CMSIS_RTOS_Wait CMSIS-RTOS also supports virtual timer objects. These timer objects can\ntrigger the execution of a function (not threads). When a timer expires, a callback function is executed to run associated\ncode with the timer. The timer number is passed as a parameter to the callback function. Each timer can be configured as a\none-shot or a  periodic timer. A periodic timer repeats its operation until it is \\ref osTimerDelete \"deleted\" or\n\\ref osTimerStop \"stopped\". All timers can be \\ref osTimerStart \"started, restarted\", or \\ref osTimerStop \"stopped\".\n\nTimers are handled in the thread \\b osTimerThread. Callback functions run under control of this thread and may use other\nCMSIS-RTOS API calls.\n\nThe figure below shows the behavior of a periodic timer.  For one-shot timers, the timer stops after execution of the\ncallback function.\n\n\\image html \"Timer.png\" \"Behavior of a Periodic Timer\"\n\nWorking with Timers\n--------------------\nThe following steps are required to use a timer:\n-# Define the timers:\n\\code\nosTimerDef(one_shot, start_machine);  // when the timer expires, the function start_machine is called\nosTimerDef(periodic, toggle_power);   // when the timer expires, the function toggle_power is called\nosTimerId one_shot_id, periodic_id;\n\\endcode\n-# Instantiate and start the timers in an RTOS thread:\n\\code\none_shot_id = osTimerCreate(osTimer(one_shot), osTimerOnce, (void *)0);      // creates a one-shot timer;\n                                                                             // (void*)0 is passed as an argument to the callback function\nperiodic_id = osTimerCreate(osTimer(periodic), osTimerPeriodic, (void *)5);  // creates a periodic timer;\n                                                                             // (void*)5 is passed as an argument to the callback function\nosTimerStart(one_shot_id, 500);\nosTimerStart(periodic, 1500);\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osTimerDef(name, function)\nDefine the attributes of a timer.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osTimer(name)\nAccess to the timer definition for the function \\ref osTimerCreate.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\note MUST REMAIN UNCHANGED: \\b os_timer_type shall be consistent in every CMSIS-RTOS.\nThe \\ref os_timer_type specifies the a repeating (periodic) or one-shot timer for the function \\ref osTimerCreate.\n*/\ntypedef enum {} os_timer_type;\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument)\nCreate a one-shot or periodic timer and associate it with a callback function argument.\nThe timer is in stopped until it is started with \\ref osTimerStart.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Timer1_Callback  (void const *arg);                   // prototypes for timer callback function\nvoid Timer2_Callback  (void const *arg);                   \n \nosTimerDef (Timer1, Timer1_Callback);                      // define timers\nosTimerDef (Timer2, Timer2_Callback);\n \nuint32_t  exec1;                                           // argument for the timer call back function\nuint32_t  exec2;                                           // argument for the timer call back function\n \nvoid TimerCreate_example (void)  {\n  osTimerId id1;                                           // timer id\n  osTimerId id2;                                           // timer id\n \n  // Create one-shoot timer\n  exec1 = 1;\n  id1 = osTimerCreate (osTimer(Timer1), osTimerOnce, &exec1);\n  if (id1 != NULL)  {\n    // One-shoot timer created\n  }\n \n  // Create periodic timer\n  exec2 = 2;\n  id2 = osTimerCreate (osTimer(Timer2), osTimerPeriodic, &exec2);\n  if (id2 != NULL)  {\n    // Periodic timer created\n  }\n  :\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osTimerStart  (osTimerId timer_id, uint32_t millisec)\nStart or restart the timer.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the specified timer has been started or restarted.\n - \\em osErrorISR: \\ref osTimerStart cannot be called from interrupt service routines.\n - \\em osErrorParameter: \\a timer_id is incorrect.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n \n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Time_Callback  (void const *arg)  {                   // timer callback function\n                                                           // arg contains &exec\n                                                           // called every second after osTimerStart\n} \n \nosTimerDef (Timer, Time_Callback);                         // define timer\nuint32_t  exec;                                            // argument for the timer call back function\n \nvoid TimerStart_example (void)  {\n  osTimerId id;                                            // timer id\n  uint32_t  timerDelay;                                    // timer value\n  osStatus  status;                                        // function return status\n \n  // Create periodic timer\n  exec = 1;\n  id = osTimerCreate (osTimer(Timer), osTimerPeriodic, &exec);\n  if (id)  {\n    timerDelay = 1000;\n    status = osTimerStart (id, timerDelay);                // start timer\n    if (status != osOK)  {\n      // Timer could not be started\n    } \n  }\n  :\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osTimerStop  (osTimerId timer_id)\nStop the timer.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the specified timer has been stopped.\n - \\em osErrorISR: \\ref osTimerStop cannot be called from interrupt service routines.\n - \\em osErrorParameter: \\a timer_id is incorrect.\n - \\em osErrorResource: the timer is not started.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nvoid Timer_Callback  (void const *arg);                    // prototype for timer callback function\nosTimerDef (Timer, Timer_Callback);                        // define timer\n \nvoid TimerStop_example (void)  {\n  osTimerId id;                                            // timer id\n  osStatus status;                                         // function return status\n \n  // Create periodic timer\n  exec = 1;\n  id = osTimerCreate (osTimer(Timer2), osTimerPeriodic, NULL);\n  osTimerStart (id, 1000);                                 // start timer\n  :\n  status = osTimerStop (id);                               // stop timer\n  if (status != osOK)  {\n    // Timer could not be stopped\n  } \n  :\n  osTimerStart (id, 1000);                                 // start timer again\n  :\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osTimerDelete  (osTimerId timer_id)\nDelete the timer object.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the specified timer has been deleted.\n - \\em osErrorISR: \\ref osTimerDelete cannot be called from interrupt service routines.\n - \\em osErrorParameter: \\a timer_id is incorrect.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n\nvoid Timer_Callback  (void const *arg);                    // prototype for timer callback function\nosTimerDef (Timer, Timer_Callback);                        // define timer\n \nvoid TimerDelete_example (void)  {\n  osTimerId id;                                            // timer id\n  osStatus status;                                         // function return status  \n \n  // Create periodic timer\n  exec = 1;\n  id = osTimerCreate (osTimer(Timer2), osTimerPeriodic, NULL);\n  osTimerStart (id, 1000UL);                               // start timer\n  :\n  status = osTimerDelete (id);                             // stop and delete timer\n  if (status != osOK)  {\n    // Timer could not be deleted\n  } \n  :\n}\n\\endcode\n*/\n/// @}\n\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Inter-Thread Communication Functions ====\n/** \n\\addtogroup CMSIS_RTOS_InterThread Inter-Thread Communication and Resource Sharing\n\\ingroup CMSIS_RTOS\n\\brief Functions for inter-thread communication.\n\\details\nIn most applications, threads need to \\b communicate \\b with \\b each \\b other or \\b access \\b shared \\b resources together.\nThere are many ways to exchange data between threads, for example using shared data, polling loops and message passing.\n\nMany resources in a microcontroller can be considered as \\b serially-reusable. This means that they can be used repeatedly by\ndifferent threads, but only by \\b one \\b thread \\b at \\b a \\b time (for example communication peripherals such as \\b UARTs,\n\\b memory, and \\b files that need to be modified).\n\n\nThe CMSIS-RTOS API provides different means to pass messages between threads to make inter-thread communication more\nefficient. Also, resource sharing is inherently supported. The following methods are available to the user:\nInter-Thread Communication\n--------------------------\n- \\ref CMSIS_RTOS_SignalMgmt\n- \\ref CMSIS_RTOS_Message\n- \\ref CMSIS_RTOS_PoolMgmt\n- \\ref CMSIS_RTOS_Mail\n\nResource Sharing\n----------------\n- \\ref CMSIS_RTOS_MutexMgmt\n- \\ref CMSIS_RTOS_SemaphoreMgmt\n*/\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Signal Management Functions ====\n/** \n\\addtogroup CMSIS_RTOS_SignalMgmt Signal Events\n\\ingroup CMSIS_RTOS_InterThread\n\\brief Synchronize threads using signals.\n\\details \nSignals are used to trigger execution states between threads. The signal management functions in CMSIS-RTOS allow you to\ncontrol or wait for signal flags. Each thread has up to 31 assigned signal flags. The maximum number of signal flags is\ndefined in the cmsis_os.h file (<b>\\#define osFeature_Signals</b>).\n\nA thread\n- can wait for signals to be set (using \\ref osSignalWait). Using this function, it enters the\n  \\ref ThreadStates \"WAITING\" state. The \\ref osSignalWait parameter \\a signals defines the signals that are required to put\n  the thread back into \\b READY state.\n- may set one or more flags in any other given thread (using \\ref osSignalSet).\n- may clear its own signals or the signals of other threads (using \\ref osSignalClear).\n\nWhen a thread wakes up and resumes execution, its signal flags are automatically cleared. \n\nWorking with Signals\n--------------------\nHere is a simple example that shows how two thread can communicate with each others using signals:\n\n\\image html simple_signal.png \"Simple signal event communication\"\n\nThe following steps are required to use signals:\n-# In the thread (for example thread ID \\c tid_thread1) that is supposed to wait for a signal, call the wait function:\n\\code\nosSignalWait (0x0001, osWaitForever); // wait forever for the signal 0x0001\n\\endcode\n-# In another thread (or threads) that are supposed to wake the waiting thread up call:\n\\code\nosSignalSet (tid_thread1, 0x0001);    // set the signal 0x0001 for thread tid_thread1\nosDelay (1000);                       // wait for 1 second\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFeature_Signals\nThe CMSIS-RTOS API may support a variable number of signal flags. This define specifies the number of signal flags available\nper thread. The maximum value is 32 signal flags per thread.\n\n\\ref rtxImplementation \"CMSIS-RTOS RTX\" Setting: \\b osFeature_Signals is 16\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn int32_t osSignalSet (osThreadId thread_id, int32_t signals)\nSet the signal flags of an active thread. This function may be used also within interrupt service routines.\n\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>Code Example</b>\n\\code{.c}\nvoid Thread_2 (void const *arg);\n \nosThreadDef (Thread_2, osPriorityHigh, 1, 0);\n \nstatic void EX_Signal_1 (void)  {\n  int32_t signals;\n  uint32_t exec;\n  osThreadId thread_id;\n  \n  thread_id = osThreadCreate (osThread(Thread_2), NULL);\n  if (thread_id == NULL)  {\n    // Failed to create a thread.\n  }\n  else  {\n    signals = osSignalSet (thread_id, 0x00000005);         // Send signals to the created thread\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn int32_t osSignalClear (osThreadId thread_id, int32_t signals)\nClear the signal flags of an active thread.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\nvoid Thread_2 (void const *arg);\n\nosThreadDef (Thread_2, osPriorityHigh, 1, 0);\n \nstatic void EX_Signal_1 (void)  {\n  int32_t  signals;\n  osThreadId thread_id;\n  \n  thread_id = osThreadCreate (osThread(Thread_2), NULL);\n  if (thread_id == NULL)  {\n    // Failed to create a thread.\n  }\n  else  {\nf    :\n    signals = osSignalClear (thread_id, 0x01);\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osEvent osSignalWait (int32_t signals, uint32_t millisec)\nSuspend the execution of the current \\b RUNNING thread until all specified signal flags with the parameter \\a signals are set.\nWhen the parameter \\a signals is 0 the current \\b RUNNING thread is suspended until any signal is set. \nWhen these signal flags are already set, the function returns instantly. Otherwise the thread is put into the state \\b WAITING. \nSignal flags that are reported as event are automatically cleared.\n\nThe argument \\a millisec specifies how long the system waits for the specified signal flags.\nWhile the system waits the thread calling this function is put into the state \\b WAITING.\nThe timeout value can have the following values:\n - when \\a millisec is 0, the function returns instantly.\n - when \\a millisec is set to \\b osWaitForever the function will wait for an infinite time until a specified signal is set.\n - all other values specify a time in millisecond for a timeout.\n \n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: no signal received when the timeout value \\em millisec was 0.\n - \\em osEventTimeout: signal not occurred within timeout\n - \\em osEventSignal: signal occurred, \\em value.signals contains the signal flags; these signal flags are cleared.\n - \\em osErrorValue:  the value \\a signals is outside of the permitted range.\n - \\em osErrorISR: \\ref osSignalWait cannot be called from interrupt service routines.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\nvoid Thread_2 (void const *arg);\n  \nosThreadDef (Thread_2, osPriorityHigh, 1, 0);\n   \nstatic void EX_Signal_1 (void)  {\n  osThreadId thread_id;\n  osEvent evt;\n    \n  thread_id = osThreadCreate (osThread(Thread_2), NULL);\n  if (thread_id == NULL)  {\n    // Failed to create a thread.\n  }\n  else  {\n    :\n    // wait for a signal\n    evt = osSignalWait (0x01, 100);\n    if (evt.status == osEventSignal)  {\n          // handle event status\n    }\n  }\n}\n\\endcode\n*/\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Message Queue Management Functions ====\n/** \n@addtogroup CMSIS_RTOS_Message Message Queue\n@ingroup CMSIS_RTOS_InterThread\n@brief Exchange messages between threads in a FIFO-like operation.\n@details \n\\b Message \\b passing is another basic communication model between threads. In the message passing model, one thread sends\ndata explicitly, while another thread receives it. The operation is more like some kind of I/O rather than a direct access to\ninformation to be shared. In CMSIS-RTOS, this mechanism is called s \\b message \\b queue. The data is passed from one thread\nto another in a FIFO-like operation. Using message queue functions, you can control, send, receive, or wait for messages. The\ndata to be passed can be of integer or pointer type:\n\n\\image html \"MessageQueue.png\" \"CMSIS-RTOS Message Queue\"\n\nCompared to a \\ref CMSIS_RTOS_PoolMgmt, message queues are less efficient in general, but solve a broader range of problems.\nSometimes, threads do not have a common address space or the use of shared memory raises problems, such as mutual exclusion.\n\nWorking with Message Queues\n---------------------------\nFollow these steps to create and use a message queue:\n-# Setup the message queue:\n\\code\nosMessageQDef(message_q, 5, uint32_t); // Declare a message queue\nosMessageQId (message_q_id);           // Declare an ID for the message queue\n\\endcode\n-# Then, create the message queue in a thread:\n\\code\nmessage_q_id = osMessageCreate(osMessageQ(message_q), NULL);\n\\endcode\n-# Fill the message queue with data:\n\\code\nuint32_t data = 512;\n \nosMailPut(message_q_id, data, osWaitForever);\n\\endcode\n-# From the receiving thread access the data using:\n\\code\nosEvent event = osMessageGet(message_q_id, osWaitForever);\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFeature_MessageQ\nA CMSIS-RTOS implementation may support message queues. \n - When \\ref osFeature_MailQ is 1 message queues are supported.\n - When \\ref osFeature_MailQ is 0 no message queues are supported.\n\n\\ref rtxImplementation \"CMSIS-RTOS RTX\" Setting: \\b osFeature_MessageQ is 1\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osMessageQDef(name, queue_sz, type)\nDefine the attributes of a message queue created by the function \\ref osMessageCreate using \\ref osMessageQ.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osMessageQ(name)\nAccess to the message queue definition for the function \\ref osMessageCreate.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);\nCreate and initialize a message queue. The parameter \\em thread_id registers the receiving thread for a message and is \nneeded for the general \\ref osWait function to deliver the message. \n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nosThreadId tid_thread1;                          // ID for thread 1\nosThreadId tid_thread2;                          // for thread 2\n \ntypedef struct {                                 // Message object structure\n  float    voltage;                              // AD result of measured voltage\n  float    current;                              // AD result of measured current\n  int      counter;                              // A counter value\n} T_MEAS;\n \nosPoolDef(mpool, 16, T_MEAS);                    // Define memory pool\nosPoolId  mpool;\nosMessageQDef(MsgBox, 16, &T_MEAS);              // Define message queue\nosMessageQId  MsgBox;\n \nvoid send_thread (void const *argument);         // forward reference\nvoid recv_thread (void const *argument);         // forward reference\n                                                 // Thread definitions\nosThreadDef(send_thread, osPriorityNormal, 1, 0);\nosThreadDef(recv_thread, osPriorityNormal, 1, 2000);\n \n//\n//  Thread 1: Send thread\n//\nvoid send_thread (void const *argument) {\n  T_MEAS    *mptr;\n \n  mptr = osPoolAlloc(mpool);                     // Allocate memory for the message\n  mptr->voltage = 223.72;                        // Set the message content\n  mptr->current = 17.54;\n  mptr->counter = 120786;\n  osMessagePut(MsgBox, (uint32_t)mptr, osWaitForever);  // Send Message\n  osDelay(100);\n \n  mptr = osPoolAlloc(mpool);                     // Allocate memory for the message\n  mptr->voltage = 227.23;                        // Prepare a 2nd message\n  mptr->current = 12.41;\n  mptr->counter = 170823;\n  osMessagePut(MsgBox, (uint32_t)mptr, osWaitForever);  // Send Message\n  osThreadYield();                               // Cooperative multitasking\n                                                 // We are done here, exit this thread\n}\n \n//\n//  Thread 2: Receive thread\n//\nvoid recv_thread (void const *argument) {\n  T_MEAS  *rptr;\n  osEvent  evt;\n   \n  for (;;) {\n    evt = osMessageGet(MsgBox, osWaitForever);  // wait for message\n    if (evt.status == osEventMessage) {\n      rptr = evt.value.p;\n      printf (\"\\nVoltage: %.2f V\\n\", rptr->voltage);\n      printf (\"Current: %.2f A\\n\", rptr->current);\n      printf (\"Number of cycles: %d\\n\", rptr->counter);\n      osPoolFree(mpool, rptr);                  // free memory allocated for message\n    }\n  }\n}\n \nvoid StartApplication (void) {\n  mpool = osPoolCreate(osPool(mpool));                 // create memory pool\n  MsgBox = osMessageCreate(osMessageQ(MsgBox), NULL);  // create msg queue\n   \n  tid_thread1 = osThreadCreate(osThread(send_thread), NULL);\n  tid_thread2 = osThreadCreate(osThread(recv_thread), NULL);\n  :\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)\nPut the message \\a info in a message queue specified by \\a queue_id. \n\nWhen the message queue is full, the system retries for a specified time with \\a millisec. \nWhile the system retries the thread that is calling this function is put into the state \\b WAITING.\nThe \\a millisec timeout can have the following values:\n - when \\a millisec is 0, the function returns instantly.\n - when \\a millisec is set to \\b osWaitForever the function will wait for an infinite time until a message queue slot becomes available.\n - all other values specify a time in millisecond for a timeout.\n\n\\note The parameter \\a millisec must be 0 for using this function in an ISR.\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the message is put into the queue.\n - \\em osErrorResource: no memory in the queue was available.\n - \\em osErrorTimeoutResource: no memory in the queue was available during the given time limit.\n - \\em osErrorParameter: a parameter is invalid or outside of a permitted range.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)\nSuspend the execution of the current \\b RUNNING thread until a message arrives. When a message is already in the queue,\nthe function returns instantly with the message information.\n\nThe argument \\a millisec specifies how long the system waits for a message to become available.\nWhile the system waits the thread that is calling this function is put into the state \\b WAITING.\nThe \\a millisec timeout value can have the following values:\n - when \\a millisec is 0, the function returns instantly.\n - when \\a millisec is set to \\b osWaitForever the function will wait for an infinite time until a message arrives.\n - all other values specify a time in millisecond for a timeout.\n \n\\note The parameter \\a millisec must be 0 for using this function in an ISR.\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: no message is available in the queue and no timeout was specified.\n - \\em osEventTimeout: no message has arrived during the given timeout period.\n - \\em osEventMessage: message received, \\em value.p contains the pointer to message.\n - \\em osErrorParameter: a parameter is invalid or outside of a permitted range.\n*/\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Memory Pool Management Functions ====\n/** \n\\addtogroup CMSIS_RTOS_PoolMgmt Memory Pool\n\\ingroup CMSIS_RTOS_InterThread\n\\brief Manage thread-safe fixed-size blocks of dynamic memory.\n\\details\n\\b Memory \\b pools are fixed-size blocks of memory that are thread-safe. They operate much faster than the dynamically\nallocated heap and do not suffer from fragmentation. Being thread-safe, they can be accessed from threads and ISRs alike.\n\n\\b Shared \\b memory is one of the basic models to exchange information between threads. Using memory pools for exchanging\ndata, you can share more complex objects between threads if compared to a \\ref CMSIS_RTOS_Message. Memory pool management\nfunctions are used to define and manage such fixed-sized memory pools.\n\nWorking with Memory Pools\n-------------------------\nFollow these steps to create and use a memory pool:\n-# Declare a data structure that combines a number of elements:\n\\code\ntypedef struct {\n  uint32_t length;\n  uint32_t width;\n  uint32_t height;\n  uint32_t weight;\n} properties_t;\n\\endcode\n-# Declare a memory pool of these objects as a block of memory:\n\\code\nosPoolDef (object_pool, 10, properties_t);  // Declare memory pool\nosPoolId  (object_pool_id);                 // Memory pool ID\n\\endcode\n-# Then, create the memory pool in a thread:\n\\code\nobject_pool_id = osPoolCreate(osPool(object_pool));\n\\endcode\n-# Allocate the pool within a thread and fill it with data:\n\\code\nproperties_t *object_data;\n*object_data = (properties_t *) osPoolAlloc(object_pool_id);\n \nobject_data->length = 100;\nobject_data->width  = 10;\nobject_data->height = 23;\nobject_data->weight = 1000;\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFeature_Pool\nA CMSIS-RTOS implementation may support fixed-size memory pools. \n - When \\ref osFeature_Pool is 1 memory pools are supported.\n - When \\ref osFeature_Pool is 0 no memory pools are supported.\n \n\\ref rtxImplementation \"CMSIS-RTOS RTX\" Setting: \\b osFeature_Pool is 1\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osPoolDef(name)\nDefine a memory pool that is referenced by \\ref osPool.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osPool(name)\nAccess a memory pool for the functions \\ref osPoolCreate.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osPoolId osPoolCreate (const osPoolDef_t *pool_def);\nCreate and initialize a memory pool.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \ntypedef struct {\n  uint8_t Buf[32];\n  uint8_t Idx;\n} MEM_BLOCK;\n \nosPoolDef (MemPool, 8, MEM_BLOCK);\n  \nvoid CreateMemoryPool (void)  {\nosPoolId MemPool_Id;\n \n  MemPool_Id = osPoolCreate (osPool (MemPool));\n  if (MemPool_Id != NULL)  {\n    // memory pool created\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn void *osPoolAlloc (osPoolId pool_id)\nAllocate a memory block from the memory pool.\n\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \ntypedef struct {\n  uint8_t Buf[32];\n  uint8_t Idx;\n} MEM_BLOCK;\n \nosPoolDef (MemPool, 8, MEM_BLOCK);\n \nvoid AlocMemoryPoolBlock (void)  {\n  osPoolId   MemPool_Id;\n  MEM_BLOCK *addr;\n \n  MemPool_Id = osPoolCreate (osPool (MemPool));\n  if (MemPool_Id != NULL)  {\n    :\n    // allocate a memory block\n    addr = (MEM_BLOCK *)osPoolAlloc (MemPool_Id);\n    \n    if (addr != NULL) {\n      // memory block was allocated\n      :\n    }\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn void *osPoolCAlloc (osPoolId pool_id)\nAllocate a memory block from the memory pool. The block is initialized to zero.\n\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \ntypedef struct {\n  uint8_t Buf[32];\n  uint8_t Idx;\n} MEM_BLOCK;\n \nosPoolDef (MemPool, 8, MEM_BLOCK);\n \nvoid CAlocMemoryPoolBlock (void)  {\n  osPoolId   MemPool_Id;\n  MEM_BLOCK *addr;\n \n  MemPool_Id = osPoolCreate (osPool (MemPool));\n  if (MemPool_Id != NULL)  {\n    :\n    // allocate a memory block\n    addr = (MEM_BLOCK *)osPoolCAlloc (MemPool_Id);\n    \n    if (addr != NULL) {\n      // memory block was allocated\n      :\n    }\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osPoolFree (osPoolId pool_id, void *block)\nReturn a memory block to a memory pool.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the memory block is released.\n - \\em osErrorValue: \\a block does not belong to the memory pool.\n - \\em osErrorParameter: a parameter is invalid or outside of a permitted range.\n\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \ntypedef struct {\n  uint8_t Buf[32];\n  uint8_t Idx;\n} MEM_BLOCK;\n \nosPoolDef (MemPool, 8, MEM_BLOCK);\n  \nvoid CAlocMemoryPoolBlock (void)  {\n  osPoolId   MemPool_Id;\n  MEM_BLOCK *addr;\n  osStatus   status;\n  \n  MemPool_Id = osPoolCreate (osPool (MemPool));\n  if (MemPool_Id != NULL)  {\n    addr = (MEM_BLOCK *)osPoolCAlloc (MemPool_Id);\n    if (addr != NULL) {\n      :\n      // return a memory block back to pool\n      status = osPoolFree (MemPool_Id, addr);\n      if (status==osOK)  {\n        // handle status code\n      }\n    }\n  }\n}\n\\endcode\n*/\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Mail Queue Management Functions ====\n/** \n\\addtogroup CMSIS_RTOS_Mail Mail Queue\n\\ingroup CMSIS_RTOS_InterThread\n\\brief Exchange data between threads using a queue of memory blocks.\n\\details\n\nA \\b mail \\b queue resembles a \\ref CMSIS_RTOS_Message, but the data that is being transferred consists of memory blocks that\nneed to be allocated (before putting data in) and freed (after taking data out). The mail queue uses a\n\\ref CMSIS_RTOS_PoolMgmt to create formatted memory blocks and passes pointers to these blocks in a message queue. This\nallows the data to stay in an allocated memory block while only a pointer is moved between the separate threads. This is an\nadvantage over \\ref CMSIS_RTOS_Message \"messages\" that can transfer only a 32-bit value or a pointer. Using the mail queue\nfunctions, you can control, send, receive, or wait for mail.\n\n\\image html \"MailQueue.png\" \"CMSIS-RTOS Mail Queue\"\n\nWorking with Mail Queues\n---------------------------\nFollow these steps to create and use a mail queue:\n-# Declare a data structure that combines a number of elements:\n\\code\ntypedef struct {\n  uint32_t length;\n  uint32_t width;\n  uint32_t height;\n  uint32_t weight;\n} properties_t;\n\\endcode\n-# Declare a mail queue made up of these objects:\n\\code\nosMailQDef (object_pool_q, 10, properties_t);  // Declare mail queue\nosMailQId  (object_pool_q_id);                 // Mail queue ID\n\\endcode\n-# Then, create the mail pool in a thread:\n\\code\nobject_pool_q_id = osMailCreate(osMailQ(object_pool_q), NULL);\n\\endcode\n-# Allocate the mail queue within a thread and fill it with data:\n\\code\nproperties_t *object_data;\n*object_data = (properties_t *) osMailAlloc(object_pool_q_id, osWaitForever);\n \nobject_data->length = 100;\nobject_data->width = 10;\nobject_data->height = 23;\nobject_data->weight = 1000;\n\\endcode\n-# Pass the pointer to the mail queue to another thread:\n\\code\nosMailPut(object_pool_q_id, object_data);\n\\endcode\n-# Access the data in another thread:\n\\code\nosEvent event = osMailGet(properties_q_id, osWaitForever);\nproperties_t *received = (properties_t *)event.value.p;       // \".p\" indicates that the message is a pointer\nmy_length(received->length);\n\\endcode\n-# Once the data has been used, the memory block must be freed so that the memory pool can be reused\n\\code\nosMailFree(object_pool_q_id, received);\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFeature_MailQ\nA CMSIS-RTOS implementation may support mail queues. \n - When \\ref osFeature_MailQ is 1 mail queues are supported.\n - When \\ref osFeature_MailQ is 0 no mail queues are supported.\n\n\\ref rtxImplementation \"CMSIS-RTOS RTX\" Setting: \\b osFeature_MailQ is 1\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osMailQDef(name, queue_sz, type, thread)\nDefine the attributes of a mail queue that can by the function \\ref osMailCreate using \\ref osMailQ.\n\n\\note\nThe parameter \\em thread registers the receiving thread for a mail and is \nneeded for the general \\ref osWait function to deliver the mail. \n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osMailQ(name)\nAccess to the mail queue definition for the function \\ref osMailCreate.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id)\nInitialize and create a mail queue.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n \nosThreadId tid_thread1;                          // ID for thread 1\nosThreadId tid_thread2;                          // ID for thread 2\n \ntypedef struct {                                 // Mail object structure\n  float    voltage;                              // AD result of measured voltage\n  float    current;                              // AD result of measured current\n  int      counter;                              // A counter value\n} T_MEAS;\n \nosMailQDef(mail, 16, T_MEAS);                    // Define mail queue\nosMailQId  mail;\n \nvoid send_thread (void const *argument);         // forward reference\nvoid recv_thread (void const *argument);\n \nosThreadDef(send_thread, osPriorityNormal, 1, 0);     // thread definitions\nosThreadDef(recv_thread, osPriorityNormal, 1, 2000);\n \n//\n//  Thread 1: Send thread\n//\nvoid send_thread (void const *argument) {\n  T_MEAS *mptr;\n \n  mptr = osMailAlloc(mail, osWaitForever);       // Allocate memory\n  mptr->voltage = 223.72;                        // Set the mail content\n  mptr->current = 17.54;\n  mptr->counter = 120786;\n  osMailPut(mail, mptr);                         // Send Mail\n  osDelay(100);\n   \n  mptr = osMailAlloc(mail, osWaitForever);       // Allocate memory\n  mptr->voltage = 227.23;                        // Prepare 2nd mail\n  mptr->current = 12.41;\n  mptr->counter = 170823;\n  osMailPut(mail, mptr);                         // Send Mail\n  osThreadYield();                               // Cooperative multitasking\n                                                 // We are done here, exit this thread\n}\n \n//\n//  Thread 2: Receive thread\n//\nvoid recv_thread (void const *argument) {\n  T_MEAS  *rptr;\n  osEvent  evt;\n   \n  for (;;) {\n    evt = osMailGet(mail, osWaitForever);        // wait for mail\n    if (evt.status == osEventMail) {\n      rptr = evt.value.p;\n      printf (\"\\nVoltage: %.2f V\\n\", rptr->voltage);\n      printf (\"Current: %.2f A\\n\", rptr->current);\n      printf (\"Number of cycles: %d\\n\", rptr->counter);\n      osMailFree(mail, rptr);                    // free memory allocated for mail\n    }\n  }\n}\n \nvoid StartApplication (void) {\n  mail = osMailCreate(osMailQ(mail), NULL);      // create mail queue\n \n  tid_thread1 = osThreadCreate(osThread(send_thread), NULL);\n  tid_thread2 = osThreadCreate(osThread(recv_thread), NULL);\n  :\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn void *osMailAlloc (osMailQId queue_id, uint32_t millisec)\nAllocate a memory block from the mail queue that is filled with the mail information.\n\nThe argument \\a queue_id specifies a mail queue identifier that is obtain with \\ref osMailCreate.\n\nThe argument \\a millisec specifies how long the system waits for a mail slot to become available.\nWhile the system waits the thread calling this function is put into the state \\b WAITING.\nThe \\a millisec timeout can have the following values:\n - when \\a millisec is 0, the function returns instantly.\n - when \\a millisec is set to \\b osWaitForever the function will wait for an infinite time until a mail slot can be allocated.\n - all other values specify a time in millisecond for a timeout.\n \n\\note The parameter \\a millisec must be 0 for using this function in an ISR.\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\nA NULL pointer is returned when no memory slot can be obtained or \\a queue specifies an illegal parameter.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn void *osMailCAlloc (osMailQId queue_id, uint32_t millisec)\nAllocate a memory block from the mail queue that is filled with the mail information. The memory block returned is cleared.\n\nThe argument \\a queue_id specifies a mail queue identifier that is obtain with \\ref osMailCreate.\n\nThe argument \\a millisec specifies how long the system waits for a mail slot to become available.\nWhile the system waits the thread that is calling this function is put into the state \\b WAITING.\nThe \\a millisec timeout can have the following values:\n - when \\a millisec is 0, the function returns instantly.\n - when \\a millisec is set to \\b osWaitForever the function will wait for an infinite time until a mail slot can be allocated.\n - all other values specify a time in millisecond for a timeout.\n \n\\note The parameter \\a millisec must be 0 for using this function in an ISR.\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\nA NULL pointer is returned when no memory block can be obtained or \\a queue specifies an illegal parameter.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osMailPut (osMailQId queue_id, void *mail)\nPut the memory block specified with \\a mail into the mail queue specified by \\a queue. \n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the message is put into the queue.\n - \\em osErrorValue: \\a mail was previously not allocated as memory slot.\n - \\em osErrorParameter: a parameter is invalid or outside of a permitted range.\n \n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osEvent osMailGet (osMailQId queue_id, uint32_t millisec)\nSuspend the execution of the current \\b RUNNING thread until a mail arrives. When a mail is already in the queue,\nthe function returns instantly with the mail information.\n\nThe argument \\a millisec specifies how long the system waits for a mail to arrive.\nWhile the system waits the thread that is calling this function is put into the state \\b WAITING.\nThe \\a millisec timeout can have the following values:\n - when \\a millisec is 0, the function returns instantly.\n - when \\a millisec is set to \\b osWaitForever the function will wait for an infinite time until a mail arrives.\n - all other values specify a time in millisecond for a timeout.\n \n\\note The parameter \\a millisec must be 0 for using this function in an ISR.\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: no mail is available in the queue and no timeout was specified\n - \\em osEventTimeout: no mail has arrived during the given timeout period.\n - \\em osEventMail: mail received, \\em value.p contains the pointer to mail content.\n - \\em osErrorParameter: a parameter is invalid or outside of a permitted range.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osMailFree (osMailQId queue_id, void *mail)\nFree the memory block specified by \\a mail and return it to the mail queue.\n\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the \\a mail block is released.\n - \\em osErrorValue: \\a mail block does not belong to the mail queue pool.\n - \\em osErrorParameter: the value to the parameter \\a queue_id is incorrect.\n\n*/\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Mutex Management Functions ====\n/** \n\\addtogroup CMSIS_RTOS_MutexMgmt Mutexes\n\\ingroup CMSIS_RTOS_InterThread\n\\brief Synchronize resource access using Mutual Exclusion (Mutex).\n\\details \n<b>Mutual exclusion</b> (widely known as \\b Mutex) is used in various operating systems for resource management. Many\nresources in a microcontroller device can be used repeatedly, but only by one thread at a time (for example communication\nchannels, memory, and files). Mutexes are used to protect access to a shared resource. A mutex is created and then passed\nbetween the threads (they can acquire and release the mutex).\n\n\\image html \"Mutex.png\" \"CMSIS-RTOS Mutex\"\n\nA mutex is a special version of a \\ref CMSIS_RTOS_SemaphoreMgmt \"semaphore\". Like the semaphore, it is a container for\ntokens. But instead of being able to have multiple tokens, a mutex can only carry one (representing the resource). Thus, a\nmutex token is binary and bounded. The advantage of a mutex is that it introduces thread ownership. When a thread acquires a\nmutex and becomes its owner, subsequent mutex acquires from that thread will succeed immediately without any latency. Thus,\nmutex acquires/releases can be nested.\n\n\\note\n- Mutex management functions cannot be called from interrupt service routines (ISR), unlike a binary semaphore that can be\n  released from an ISR.\n- CMSIS-RTOS uses <a href=\"https://en.wikipedia.org/wiki/Reentrant_mutex\" target=\"_blank\">reentrant/recursive mutexes</a>\n  only.\n\nWorking with Mutexes\n--------------------\nTo use mutexes, you need to follow these steps for creating and using them:\n-# Declare the mutex container and initialize the mutex:\n\\code\nosMutexDef (uart_mutex);    // Declare mutex\nosMutexId  (uart_mutex_id); // Mutex ID\n\\endcode\n-# Create the mutex in a thread:\n\\code\nuart_mutex_id = osMutexCreate(osMutex(uart_mutex));\n\\endcode\n-# Acquire the mutex when peripheral access is required:\n\\code\nosMutexWait(uart_mutex_id, osWaitForever);\n\\endcode\n-# When finished with the peripheral access, release the mutex:\n\\code\nosMutexRelease(uart_mutex_id);\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osMutexDef(name)\nDefine a mutex object that is referenced by \\ref osMutex.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osMutex(name)\nAccess to mutex object for the functions \\ref osMutexCreate.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osMutexId osMutexCreate (const osMutexDef_t *mutex_def)\nCreate and initialize a Mutex object.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n  \nosMutexDef (MutexIsr);                                     // Mutex name definition\n  \nvoid CreateMutex (void)  {\nosMutexId mutex_id;   \n \n  mutex_id = osMutexCreate  (osMutex (MutexIsr));\n  if (mutex_id != NULL)  {\n    // Mutex object created\n  }   \n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)\nWait until a Mutex becomes available. If no other thread has obtained the Mutex, the function instantly returns and blocks the mutex object. \n\nThe argument \\a millisec specifies how long the system waits for a mutex.\nWhile the system waits the thread that is calling this function is put into the state \\b WAITING.\nThe \\a millisec timeout can have the following values:\n - when \\a millisec is 0, the function returns instantly.\n - when \\a millisec is set to \\b osWaitForever the function will wait for an infinite time until the mutex becomes available.\n - all other values specify a time in millisecond for a timeout.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the mutex has been obtained.\n - \\em osErrorTimeoutResource: the mutex could not be obtained in the given time.\n - \\em osErrorResource: the mutex could not be obtained when no timeout was specified.\n - \\em osErrorParameter: the parameter \\a mutex_id is incorrect.\n - \\em osErrorISR: \\ref osMutexWait cannot be called from interrupt service routines.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n \n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n  \nosMutexDef (MutexIsr);\n  \nvoid WaitMutex (void)  {\nosMutexId mutex_id;   \nosStatus status;\n \n  mutex_id = osMutexCreate  (osMutex (MutexIsr));\n  if (mutex_id != NULL)  {\n    status  = osMutexWait    (mutex_id, 0);\n    if (status != osOK)  {\n      // handle failure code\n    }\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osMutexRelease (osMutexId mutex_id)\nRelease a Mutex that was obtained with \\ref osMutexWait. Other threads that currently wait for the same mutex will be now put into the state \\b READY.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the mutex has been correctly released.\n - \\em osErrorResource: the mutex was not obtained before.\n - \\em osErrorParameter: the parameter \\a mutex_id is incorrect.\n - \\em osErrorISR: \\ref osMutexRelease cannot be called from interrupt service routines.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n \n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n  \nosMutexDef (MutexIsr);                                     // Mutex name definition \nosMutexId mutex_id;                                        // Mutex id populated by the function CreateMutex()\nosMutexId CreateMutex (void);                              // function prototype that creates the Mutex\n \nvoid ReleaseMutex (osMutexId mutex_id)  {\nosStatus status;\n  \n  if (mutex_id != NULL)  {\n    status = osMutexRelease(mutex_id);\n    if (status != osOK)  {\n      // handle failure code\n    }\n  }\n}\n\\endcode\n*/\n \n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osMutexDelete (osMutexId mutex_id)\nDelete a Mutex object.  The function releases internal memory obtained for Mutex handling.  After this call the \\a mutex_id is no longer valid and cannot be\nused. The Mutex may be created again using the function \\ref osMutexCreate.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the mutex object has been deleted.\n - \\em osErrorISR: \\ref osMutexDelete cannot be called from interrupt service routines.\n - \\em osErrorResource: all tokens have already been released.\n - \\em osErrorParameter: the parameter \\a mutex_id is incorrect.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n \n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n  \nosMutexDef (MutexIsr);                                     // Mutex name definition \nosMutexId mutex_id;                                        // Mutex id populated by the function CreateMutex()\nosMutexId CreateMutex (void);                              // function prototype that creates the Mutex\n \nvoid DeleteMutex (osMutexId mutex_id)  {\nosStatus status;\n  \n  if (mutex_id != NULL)  {\n    status = osMutexDelete(mutex_id);\n    if (status != osOK)  {\n      // handle failure code\n    }\n  }\n}\n\\endcode\n*/\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Semaphore Management Functions ====\n/** \n\\addtogroup CMSIS_RTOS_SemaphoreMgmt Semaphores\n\\ingroup CMSIS_RTOS_InterThread\n\\brief Access shared resources simultaneously from different threads.\n\\details \nSemaphores are used to manage and protect access to shared resources. Semaphores are very similar to\n\\ref CMSIS_RTOS_MutexMgmt \"Mutexes\". Whereas a Mutex permits just one thread to access a shared resource at a\ntime, a semaphore can be used to permit a fixed number of threads to access a pool of shared resources. Using semaphores,\naccess to a group of identical peripherals can be managed (for example multiple DMA channels).\n\n\\image html \"Semaphore.png\" \"CMSIS-RTOS Semaphore\"\n\nA semaphore object should be initialized to the maximum number of available tokens. This number of available resources is\nspecified as parameter of the \\ref osSemaphoreCreate function. Each time a semaphore token is obtained with\n\\ref osSemaphoreWait, the semaphore count is decremented. When the semaphore count is 0, no semaphore token can be obtained.\nThe thread that tries to obtain the semaphore token needs to wait until the next token is free. Semaphores are released with\n\\ref osSemaphoreRelease incrementing the semaphore count.\n\n\\note Semaphore tokens can be acquired from threads and released from threads and ISRs.\n\nWorking with Semaphores\n--------------------\nFollow these steps to create and use a semaphore:\n-# Declare the semaphore container and initialize the semaphore:\n\\code\nosSemaphoreDef (my_semaphore);    // Declare semaphore\nosSemaphoreId  (my_semaphore_id); // Semaphore ID\n\\endcode\n-# Initialize the semaphore container with a number of tokens within a thread:\n\\code\nmy_semaphore_id = osSemaphoreCreate(osSemaphore(my_semaphore), 4);  // Create semaphore with 4 tokens\n\\endcode\n\\b Important: semaphore tokens can be created and destroyed as threads run. This means that can initialize a semaphore with\nzero tokens and then use one thread to add/create tokens to the semaphore while a second thread removes them. In this way you\ncan distinguish between producer and consumer threads.\n-# Acquire a token from the semaphore container:\n\\code\nosSemaphoreWait(my_semaphore_id, osWaitForever);\n\\endcode\n-# When finished using the semaphore resource, send the token back to the semaphore container:\n\\code\nosSemaphoreRelease(my_semaphore_id);\n\\endcode\n\nSemaphore Use Cases\n-------------------\nDue to their flexibility, semaphores cover a wide range of synchronizing applications. At the same time, they are perhaps the\nmost challenging RTOS object to understand. The following explains a use case for semaphores, taken from the book\n<a href=\"http://www.greenteapress.com/semaphores/\" target=\"_blank\">The Little Book Of Semaphores</a> by Allen B. Downey which\nis available for free download.\n\n<b>Non-binary Semaphore (Multiplex)</b>\n\nA multiplex limits the number of threads that can access a critical section of code. For example, this could be a function\naccessing DMA resources which can only support a limited number of calls.\n\nTo allow multiple threads to run the function, initialize a semaphore to the maximum number of threads that can be allowed.\nThe number of tokens in the semaphore represents the number of additional threads that may enter. If this number is zero,\nthen the next thread trying to access the function will have to wait until one of the other threads exits and releases its\ntoken. When all threads have exited the token number is back to n. Ths following example shows the code for one of the\nthreads that might access the resource:\n\n\\code\nosSemaphoreDef(multiplex);\nosSemaphoreId (multiplex_id);\n \nvoid thread_n (void)\n  {\n    multiplex_id = osSemaphoreCreate(osSemaphore(multiplex), 3);\n    while(1)\n      {\n        osSemaphoreWait(multiplex_id, osWaitForever);\n        // do something\n        osSemaphoreRelease(multiplex_id);\n      }\n  }\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFeature_Semaphore\nA CMSIS-RTOS implementation may support semaphores. The value \\ref osFeature_Semaphore indicates the maximum index count for\na semaphore.\n\n\\ref rtxImplementation \"CMSIS-RTOS RTX\" Setting: \\b osFeature_Semaphore is 65535\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osSemaphoreDef(name)\nDefine a semaphore object that is referenced by \\ref osSemaphore.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osSemaphore(name)\nAccess to semaphore object for the functions \\ref osSemaphoreCreate.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)\nCreate and initialize a Semaphore object that is used to manage access to shared resources. The parameter \\em count specifies the number of available resources. \nThe \\em count value 1 creates a binary semaphore.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os.h\"\n   \nosThreadId tid_thread1;                          // ID for thread 1\nosThreadId tid_thread2;                          // ID for thread 2\n  \nosSemaphoreId semaphore;                         // Semaphore ID\nosSemaphoreDef(semaphore);                       // Semaphore definition\n   \n//\n//   Thread 1 - High Priority - Active every 3ms\n//\nvoid thread1 (void const *argument) {\n  int32_t value;\n\n  while (1) {\n    osDelay(3);                                  // Pass control to other tasks for 3ms\n    val = osSemaphoreWait (semaphore, 1);        // Wait 1ms for the free semaphore\n    if (val > 0) {\n                                                 // If there was no time-out the semaphore was acquired\n      :                                          // OK, the interface is free now, use it.\n      osSemaphoreRelease (semaphore);            // Return a token back to a semaphore\n    }\n  }\n}\n  \n//\n//   Thread 2 - Normal Priority - looks for a free semaphore and uses\n//                                the resource whenever it is available\n//\nvoid thread2 (void const *argument) {\n  while (1) {\n    osSemaphoreWait (semaphore, osWaitForever);  // Wait indefinitely for a free semaphore\n                                                 // OK, the interface is free now, use it.\n    :\n    osSemaphoreRelease (semaphore);              // Return a token back to a semaphore.\n  }\n}\n  \n// Thread definitions \nosThreadDef(thread1, osPriorityHigh,   1, 0);\nosThreadDef(thread2, osPriorityNormal, 1, 0);\n   \nvoid StartApplication (void) {\n  semaphore = osSemaphoreCreate(osSemaphore(semaphore), 1);\n\n  tid_thread1 = osThreadCreate(osThread(thread1), NULL);\n  tid_thread2 = osThreadCreate(osThread(thread2), NULL);\n  :\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)\nWait until a Semaphore token becomes available. When no Semaphore token is available, the function waits for the time specified with the parameter \\em millisec.\n\nThe argument \\a millisec specifies how long the system waits for a Semaphore token to become available.\nWhile the system waits the thread that is calling this function is put into the state \\b WAITING.\nThe \\a millisec timeout can have the following values:\n - when \\a millisec is 0, the function returns instantly.\n - when \\a millisec is set to \\b osWaitForever the function will wait for an infinite time until the Semaphore token becomes available.\n - all other values specify a time in millisecond for a timeout.\n\nThe return value indicates the number of available tokens (the semaphore count value). If 0 is returned, then no semaphore was available.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)\nRelease a Semaphore token.  This increments the count of available semaphore tokens.\n\n\\note \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" can call this function.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the semaphore has been released.\n - \\em osErrorResource: all tokens have already been released.\n - \\em osErrorParameter: the parameter \\a semaphore_id is incorrect.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn osStatus osSemaphoreDelete (osSemaphoreId semaphore_id)\nDelete a Semaphore object.  The function releases internal memory obtained for Semaphore handling.  After this call the \\a semaphore_id is no longer valid and cannot be\nused. The Semaphore may be created again using the function \\ref osSemaphoreCreate.\n\n<b>\\ref CMSIS_RTOS_Status</b>\\n\n - \\em osOK: the semaphore object has been deleted.\n - \\em osErrorISR: \\ref osSemaphoreDelete cannot be called from interrupt service routines.\n - \\em osErrorResource: the semaphore object could not be deleted.\n - \\em osErrorParameter: the parameter \\a semaphore_id is incorrect.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n/// @}\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n// ==== Enumeration, structures, defines ====\n/**\n\\addtogroup CMSIS_RTOS_Definitions Generic Data Types and Definitions\n\\ingroup CMSIS_RTOS\n\\brief Data Type Definitions used by the CMSIS-RTOS API functions.\n\\details The Data Type section lists all data types that are used to exchange information with CMSIS-RTOS functions.\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\struct osEvent\n\\details The \\b osEvent structure describes the events returned by CMSIS-RTOS functions.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\struct os_mailQ\n\\details The \\b osEvent structure describes the events returned by CMSIS-RTOS functions.\n*/\n/// @} \n\n\n// ==== Status and Error Codes ====\n/** @addtogroup CMSIS_RTOS_Status Status and Error Codes\n *  @brief Status and Error Codes returned by CMSIS-RTOS API functions.\n *  @details The Status and Error Codes section lists all the return values that the CMSIS-RTOS functions will return.\n *\n *\n *  @ingroup CMSIS_RTOS\n *  @{\n */\n\n/**\n\\note MUST REMAIN UNCHANGED: \\b osStatus shall be consistent in every CMSIS-RTOS.\n\\details The \\ref osStatus enumeration defines the event status and error codes that are returned by the CMSIS-RTOS functions.\n*/\ntypedef enum {} osStatus;\n\n\n/// @} \n"
  },
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    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/rtos.dxy",
    "content": "# Doxyfile 1.8.6\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a double hash (##) is considered a comment and is placed in\n# front of the TAG it is preceding.\n#\n# All text after a single hash (#) is considered a comment and will be ignored.\n# The format is:\n# TAG = value [value, ...]\n# For lists, items can also be appended using:\n# TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\\\" \\\").\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the config file\n# that follow. The default is UTF-8 which is also the encoding used for all text\n# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv\n# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv\n# for the list of possible encodings.\n# The default value is: UTF-8.\n\nDOXYFILE_ENCODING      = UTF-8\n\n# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by\n# double-quotes, unless you are using Doxywizard) that should identify the\n# project for which the documentation is generated. This name is used in the\n# title of most generated pages and in a few other places.\n# The default value is: My Project.\n\nPROJECT_NAME           = \"CMSIS-RTOS2\"\n\n# The PROJECT_NUMBER tag can be used to enter a project or revision number. This\n# could be handy for archiving the generated documentation or if some version\n# control system is used.\n\nPROJECT_NUMBER         = \"Version 2.2.0\"\n\n# Using the PROJECT_BRIEF tag one can provide an optional one line description\n# for a project that appears at the top of each page and should give viewer a\n# quick idea about the purpose of the project. Keep the description short.\n\nPROJECT_BRIEF          = \"Real-Time Operating System: API and RTX Reference Implementation\"\n\n# With the PROJECT_LOGO tag one can specify an logo or icon that is included in\n# the documentation. The maximum height of the logo should not exceed 55 pixels\n# and the maximum width should not exceed 200 pixels. Doxygen will copy the logo\n# to the output directory.\n\nPROJECT_LOGO           = ../Doxygen_Templates/CMSIS_Logo_Final.png\n\n# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path\n# into which the generated documentation will be written. If a relative path is\n# entered, it will be relative to the location where doxygen was started. If\n# left blank the current directory will be used.\n\nOUTPUT_DIRECTORY       = ../../Documentation/RTOS2\n\n# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-\n# directories (in 2 levels) under the output directory of each output format and\n# will distribute the generated files over these directories. Enabling this\n# option can be useful when feeding doxygen a huge amount of source files, where\n# putting all generated files in the same directory would otherwise causes\n# performance problems for the file system.\n# The default value is: NO.\n\nCREATE_SUBDIRS         = NO\n\n# The OUTPUT_LANGUAGE tag is used to specify the language in which all\n# documentation generated by doxygen is written. Doxygen will use this\n# information to generate all constant output in the proper language.\n# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,\n# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),\n# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,\n# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),\n# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,\n# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,\n# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,\n# Ukrainian and Vietnamese.\n# The default value is: English.\n\nOUTPUT_LANGUAGE        = English\n\n# If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member\n# descriptions after the members that are listed in the file and class\n# documentation (similar to Javadoc). Set to NO to disable this.\n# The default value is: YES.\n\nBRIEF_MEMBER_DESC      = YES\n\n# If the REPEAT_BRIEF tag is set to YES doxygen will prepend the brief\n# description of a member or function before the detailed description\n#\n# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the\n# brief descriptions will be completely suppressed.\n# The default value is: YES.\n\nREPEAT_BRIEF           = NO\n\n# This tag implements a quasi-intelligent brief description abbreviator that is\n# used to form the text in various listings. Each string in this list, if found\n# as the leading text of the brief description, will be stripped from the text\n# and the result, after processing the whole list, is used as the annotated\n# text. Otherwise, the brief description is used as-is. If left blank, the\n# following values are used ($name is automatically replaced with the name of\n# the entity):The $name class, The $name widget, The $name file, is, provides,\n# specifies, contains, represents, a, an and the.\n\nABBREVIATE_BRIEF       = \"The $name class\" \\\n                         \"The $name widget\" \\\n                         \"The $name file\" \\\n                         is \\\n                         provides \\\n                         specifies \\\n                         contains \\\n                         represents \\\n                         a \\\n                         an \\\n                         the\n\n# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then\n# doxygen will generate a detailed section even if there is only a brief\n# description.\n# The default value is: NO.\n\nALWAYS_DETAILED_SEC    = NO\n\n# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all\n# inherited members of a class in the documentation of that class as if those\n# members were ordinary class members. Constructors, destructors and assignment\n# operators of the base classes will not be shown.\n# The default value is: NO.\n\nINLINE_INHERITED_MEMB  = NO\n\n# If the FULL_PATH_NAMES tag is set to YES doxygen will prepend the full path\n# before files name in the file list and in the header files. If set to NO the\n# shortest path that makes the file name unique will be used\n# The default value is: YES.\n\nFULL_PATH_NAMES        = NO\n\n# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.\n# Stripping is only done if one of the specified strings matches the left-hand\n# part of the path. The tag can be used to show relative paths in the file list.\n# If left blank the directory from which doxygen is run is used as the path to\n# strip.\n#\n# Note that you can specify absolute paths here, but also relative paths, which\n# will be relative from the directory where doxygen is started.\n# This tag requires that the tag FULL_PATH_NAMES is set to YES.\n\nSTRIP_FROM_PATH        = \n\n# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the\n# path mentioned in the documentation of a class, which tells the reader which\n# header file to include in order to use a class. If left blank only the name of\n# the header file containing the class definition is used. Otherwise one should\n# specify the list of include paths that are normally passed to the compiler\n# using the -I flag.\n\nSTRIP_FROM_INC_PATH    = \n\n# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but\n# less readable) file names. This can be useful is your file systems doesn't\n# support long names like on DOS, Mac, or CD-ROM.\n# The default value is: NO.\n\nSHORT_NAMES            = NO\n\n# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the\n# first line (until the first dot) of a Javadoc-style comment as the brief\n# description. If set to NO, the Javadoc-style will behave just like regular Qt-\n# style comments (thus requiring an explicit @brief command for a brief\n# description.)\n# The default value is: NO.\n\nJAVADOC_AUTOBRIEF      = NO\n\n# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first\n# line (until the first dot) of a Qt-style comment as the brief description. If\n# set to NO, the Qt-style will behave just like regular Qt-style comments (thus\n# requiring an explicit \\brief command for a brief description.)\n# The default value is: NO.\n\nQT_AUTOBRIEF           = NO\n\n# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a\n# multi-line C++ special comment block (i.e. a block of //! or /// comments) as\n# a brief description. This used to be the default behavior. The new default is\n# to treat a multi-line C++ comment block as a detailed description. Set this\n# tag to YES if you prefer the old behavior instead.\n#\n# Note that setting this tag to YES also means that rational rose comments are\n# not recognized any more.\n# The default value is: NO.\n\nMULTILINE_CPP_IS_BRIEF = YES\n\n# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the\n# documentation from any documented member that it re-implements.\n# The default value is: YES.\n\nINHERIT_DOCS           = NO\n\n# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a\n# new page for each member. If set to NO, the documentation of a member will be\n# part of the file/class/namespace that contains it.\n# The default value is: NO.\n\nSEPARATE_MEMBER_PAGES  = NO\n\n# The TAB_SIZE tag can be used to set the number of spaces in a tab. \n# Doxygen uses this value to replace tabs by spaces in code fragments.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that acts \n# as commands in the documentation. An alias has the form \"name=value\". \n# For example adding \"sideeffect=\\par Side Effects:\\n\" will allow you to \n# put the command \\sideeffect (or @sideeffect) in the documentation, which \n# will result in a user-defined paragraph with heading \"Side Effects:\". \n# You can put \\n's in the value part of an alias to insert newlines.\n\nALIASES                = \"token{1}=<span class=\\\"XML-Token\\\">\\1</span>\" \\\n                         \"div{1}=<hr><div class=\\\"\\1\\\">\" \\\n                         \"enddiv= </div>\" \\\n                         \"func{1}=<kbd>\\1</kbd> <br>\" \\\n                         \"copybrief{1}=<br> \\copybrief \\1 <br>\" \\\n                         \"none=\\em none <br>\"\n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding \"class=itcl::class\"\n# will allow you to use the command class in the itcl::class meaning.\n\nTCL_SUBST              = \n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources\n# only. Doxygen will then generate output that is more tailored for C. For\n# instance, some of the names that are used will be different. The list of all\n# members will be omitted, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_FOR_C  = YES\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or\n# Python sources only. Doxygen will then generate output that is more tailored\n# for that language. For instance, namespaces will be presented as packages,\n# qualified scopes will look different, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources. Doxygen will then generate output that is tailored for Fortran.\n# The default value is: NO.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for VHDL.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given\n# extension. Doxygen has a built-in mapping, but you can override or extend it\n# using this tag. The format is ext=language, where ext is a file extension, and\n# language is one of the parsers supported by doxygen: IDL, Java, Javascript,\n# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C.\n#\n# Note For files without extension you can use no_extension as a placeholder.\n#\n# Note that for custom extensions you also need to set FILE_PATTERNS otherwise\n# the files are not read by doxygen.\n\nEXTENSION_MAPPING      = \n\n# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments\n# according to the Markdown format, which allows for more readable\n# documentation. See http://daringfireball.net/projects/markdown/ for details.\n# The output of markdown processing is further processed by doxygen, so you can\n# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in\n# case of backward compatibilities issues.\n# The default value is: YES.\n\nMARKDOWN_SUPPORT       = YES\n\n# When enabled doxygen tries to link words that correspond to documented\n# classes, or namespaces to their corresponding documentation. Such a link can\n# be prevented in individual cases by by putting a % sign in front of the word\n# or globally by setting AUTOLINK_SUPPORT to NO.\n# The default value is: YES.\n\nAUTOLINK_SUPPORT       = YES\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should set this\n# tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string);\n# versus func(std::string) {}). This also make the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n# The default value is: NO.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n# The default value is: NO.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:\n# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen\n# will parse them like normal C++ but will assume all classes use public instead\n# of private inheritance when no explicit protection keyword is present.\n# The default value is: NO.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate\n# getter and setter methods for a property. Setting this option to YES will make\n# doxygen to replace the get and set methods by a property in the documentation.\n# This will only work if the methods are indeed getting or setting a simple\n# type. If this is not the case, or you want to show the methods anyway, you\n# should set this option to NO.\n# The default value is: YES.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n# The default value is: NO.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES to allow class member groups of the same type\n# (for instance a group of public functions) to be put as a subgroup of that\n# type (e.g. under the Public Functions section). Set it to NO to prevent\n# subgrouping. Alternatively, this can be done per class using the\n# \\nosubgrouping command.\n# The default value is: YES.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions\n# are shown inside the group in which they are included (e.g. using \\ingroup)\n# instead of on a separate page (for HTML and Man pages) or section (for LaTeX\n# and RTF).\n#\n# Note that this feature does not work in combination with\n# SEPARATE_MEMBER_PAGES.\n# The default value is: NO.\n\nINLINE_GROUPED_CLASSES = YES\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions\n# with only public data fields or simple typedef fields will be shown inline in\n# the documentation of the scope in which they are defined (i.e. file,\n# namespace, or group documentation), provided this scope is documented. If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = YES\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = NO\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = NO\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = YES\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = NO\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = YES\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = NO\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = NO\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = NO\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = ARMv8M \\\n                         ARMCA \\\n                         ARMSC\n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = YES\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         = \n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = . \\\n                         ./src/mainpage.txt \\\n                         ./src/history.txt \\\n                         ./src/cmsis_os2.txt \\\n                         ./src/cmsis_os2_ProcessIsolation.txt \\\n                         ./src/cmsis_os2_Kernel.txt \\\n                         ./src/cmsis_os2_Thread.txt \\\n                         ./src/cmsis_os2_ThreadFlags.txt \\\n                         ./src/cmsis_os2_Event.txt \\\n                         ./src/cmsis_os2_Wait.txt \\\n                         ./src/cmsis_os2_Timer.txt \\\n                         ./src/cmsis_os2_Mutex.txt \\\n                         ./src/cmsis_os2_Sema.txt \\\n                         ./src/cmsis_os2_MemPool.txt \\\n                         ./src/cmsis_os2_Message.txt \\\n                         ./src/cmsis_os2_Status.txt \\\n                         ./src/cmsis_os2_Migration.txt \\\n                         ./src/cmsis_os2_MigrationGuide.txt \\\n                         ./src/cmsis_os2_tick.txt \\\n                         ./src/cmsis_os2_Tutorial.txt \\\n                         ./src/validation.txt \\\n                         ./src/rtx_os.txt \\\n                         ./src/rtx_evr.txt \\\n                         ../../RTOS2/Include/cmsis_os2.h \\\n                         ../../RTOS2/Include/os_tick.h \\\n                         ../../RTOS2/RTX/Include/rtx_os.h \\\n                         ../../RTOS2/RTX/Include/rtx_evr.h \n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          = *.c \\\n                         *.cc \\\n                         *.cxx \\\n                         *.cpp \\\n                         *.c++ \\\n                         *.java \\\n                         *.ii \\\n                         *.ixx \\\n                         *.ipp \\\n                         *.i++ \\\n                         *.inl \\\n                         *.h \\\n                         *.hh \\\n                         *.hxx \\\n                         *.hpp \\\n                         *.h++ \\\n                         *.idl \\\n                         *.odl \\\n                         *.cs \\\n                         *.php \\\n                         *.php3 \\\n                         *.inc \\\n                         *.m \\\n                         *.mm \\\n                         *.dox \\\n                         *.py \\\n                         *.f90 \\\n                         *.f \\\n                         *.for \\\n                         *.vhd \\\n                         *.vhdl \\\n                         *.txt\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = NO\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = YES\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       = \n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        = \n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = ../../RTOS2/Include \\\n                         ../../RTOS2 \\\n                         ../../RTOS2/RTX/Include \\\n                         ../../RTOS2/Template\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           = \n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        = \n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS = \n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE = \n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = NO\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = YES\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = YES\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = YES\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        = \n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../Doxygen_Templates/printComponentTabs.js \\\n                         ../Doxygen_Templates/search.css\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 103\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = \n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     = \n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               = \n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   = \n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  = \n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  = \n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           = \n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     = \n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       = \n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       = \n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     = \n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         = \n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           = \n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           = \n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      = \n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    = \n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             = \n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                = \n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen\n# Definitions (see http://autogen.sf.net) file that captures the structure of\n# the code including all documentation. Note that this feature is still\n# experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES doxygen will generate a Perl module\n# file that captures the structure of the code including all documentation.\n#\n# Note that this feature is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES doxygen will generate the necessary\n# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI\n# output from the Perl module output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be nicely\n# formatted so it can be parsed by a human reader. This is useful if you want to\n# understand what is going on. On the other hand, if this tag is set to NO the\n# size of the Perl module output will be much smaller and Perl will parse it\n# just the same.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_PRETTY         = YES\n\n# The names of the make variables in the generated doxyrules.make file are\n# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful\n# so different doxyrules.make files included by the same Makefile don't\n# overwrite each other's variables.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_MAKEVAR_PREFIX = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the preprocessor\n#---------------------------------------------------------------------------\n\n# If the ENABLE_PREPROCESSING tag is set to YES doxygen will evaluate all\n# C-preprocessor directives found in the sources and include files.\n# The default value is: YES.\n\nENABLE_PREPROCESSING   = YES\n\n# If the MACRO_EXPANSION tag is set to YES doxygen will expand all macro names\n# in the source code. If set to NO only conditional compilation will be\n# performed. Macro expansion can be done in a controlled way by setting\n# EXPAND_ONLY_PREDEF to YES.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nMACRO_EXPANSION        = NO\n\n# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then\n# the macro expansion is limited to the macros specified with the PREDEFINED and\n# EXPAND_AS_DEFINED tags.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_ONLY_PREDEF     = NO\n\n# If the SEARCH_INCLUDES tag is set to YES the includes files in the\n# INCLUDE_PATH will be searched if a #include is found.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSEARCH_INCLUDES        = YES\n\n# The INCLUDE_PATH tag can be used to specify one or more directories that\n# contain include files that are not input files but should be processed by the\n# preprocessor.\n# This tag requires that the tag SEARCH_INCLUDES is set to YES.\n\nINCLUDE_PATH           = \n\n# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard\n# patterns (like *.h and *.hpp) to filter out the header-files in the\n# directories. If left blank, the patterns specified with FILE_PATTERNS will be\n# used.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nINCLUDE_FILE_PATTERNS  = \n\n# The PREDEFINED tag can be used to specify one or more macro names that are\n# defined before the preprocessor is started (similar to the -D option of e.g.\n# gcc). The argument of the tag is a list of macros of the form: name or\n# name=definition (no spaces). If the definition and the \"=\" are omitted, \"=1\"\n# is assumed. To prevent a macro definition from being undefined via #undef or\n# recursively expanded use the := operator instead of the = operator.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nPREDEFINED             = OS_EVR_MEMORY:=1 \\\n                         OS_EVR_KERNEL:=1 \\\n                         OS_EVR_THREAD:=1 \\\n                         OS_EVR_TIMER:=1 \\\n                         OS_EVR_EVFLAGS:=1 \\\n                         OS_EVR_MUTEX:=1 \\\n                         OS_EVR_SEMAPHORE:=1 \\\n                         OS_EVR_MEMPOOL:=1 \\\n                         OS_EVR_MSGQUEUE:=1\n                         \n\n# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this\n# tag can be used to specify a list of macro names that should be expanded. The\n# macro definition that is found in the sources will be used. Use the PREDEFINED\n# tag if you want to use a different macro definition that overrules the\n# definition found in the source code.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_AS_DEFINED      = \n\n# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will\n# remove all refrences to function-like macros that are alone on a line, have an\n# all uppercase name, and do not end with a semicolon. Such function macros are\n# typically used for boiler-plate code, and will confuse the parser if not\n# removed.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSKIP_FUNCTION_MACROS   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to external references\n#---------------------------------------------------------------------------\n\n# The TAGFILES tag can be used to specify one or more tag files. For each tag\n# file the location of the external documentation should be added. The format of\n# a tag file without this location is as follows:\n# TAGFILES = file1 file2 ...\n# Adding location for the tag files is done as follows:\n# TAGFILES = file1=loc1 \"file2 = loc2\" ...\n# where loc1 and loc2 can be relative or absolute paths or URLs. See the\n# section \"Linking to external documentation\" for more information about the use\n# of tag files.\n# Note: Each tag file must have an unique name (where the name does NOT include\n# the path). If a tag file is not located in the directory in which doxygen is\n# run, you must also specify the path to the tagfile here.\n\nTAGFILES               = \n\n# When a file name is specified after GENERATE_TAGFILE, doxygen will create a\n# tag file that is based on the input files it reads. See section \"Linking to\n# external documentation\" for more information about the usage of tag files.\n\nGENERATE_TAGFILE       = \n\n# If the ALLEXTERNALS tag is set to YES all external class will be listed in the\n# class index. If set to NO only the inherited external classes will be listed.\n# The default value is: NO.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in\n# the modules index. If set to NO, only the current project's groups will be\n# listed.\n# The default value is: YES.\n\nEXTERNAL_GROUPS        = YES\n\n# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in\n# the related pages index. If set to NO, only the current project's pages will\n# be listed.\n# The default value is: YES.\n\nEXTERNAL_PAGES         = YES\n\n# The PERL_PATH should be the absolute path and name of the perl script\n# interpreter (i.e. the result of 'which perl').\n# The default file (with absolute path) is: /usr/bin/perl.\n\nPERL_PATH              = /usr/bin/perl\n\n#---------------------------------------------------------------------------\n# Configuration options related to the dot tool\n#---------------------------------------------------------------------------\n\n# If the CLASS_DIAGRAMS tag is set to YES doxygen will generate a class diagram\n# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to\n# NO turns the diagrams off. Note that this option also works with HAVE_DOT\n# disabled, but it is recommended to install and use dot, since it yields more\n# powerful graphs.\n# The default value is: YES.\n\nCLASS_DIAGRAMS         = YES\n\n# You can define message sequence charts within doxygen comments using the \\msc\n# command. Doxygen will then run the mscgen tool (see:\n# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the\n# documentation. The MSCGEN_PATH tag allows you to specify the directory where\n# the mscgen tool resides. If left empty the tool is assumed to be found in the\n# default search path.\n\nMSCGEN_PATH            = \n\n# You can include diagrams made with dia in doxygen documentation. Doxygen will\n# then run dia to produce the diagram and insert it in the documentation. The\n# DIA_PATH tag allows you to specify the directory where the dia binary resides.\n# If left empty dia is assumed to be found in the default search path.\n\nDIA_PATH               = \n\n# If set to YES, the inheritance and collaboration graphs will hide inheritance\n# and usage relations if the target is undocumented or is not a class.\n# The default value is: YES.\n\nHIDE_UNDOC_RELATIONS   = YES\n\n# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is\n# available from the path. This tool is part of Graphviz (see:\n# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent\n# Bell Labs. The other options in this section have no effect if this option is\n# set to NO\n# The default value is: NO.\n\nHAVE_DOT               = NO\n\n# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed\n# to run in parallel. When set to 0 doxygen will base this on the number of\n# processors available in the system. You can set it explicitly to a value\n# larger than 0 to get control over the balance between CPU load and processing\n# speed.\n# Minimum value: 0, maximum value: 32, default value: 0.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_NUM_THREADS        = 0\n\n# When you want a differently looking font n the dot files that doxygen\n# generates you can specify the font name using DOT_FONTNAME. You need to make\n# sure dot is able to find the font, which can be done by putting it in a\n# standard location or by setting the DOTFONTPATH environment variable or by\n# setting DOT_FONTPATH to the directory containing the font.\n# The default value is: Helvetica.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTNAME           = Helvetica\n\n# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of\n# dot graphs.\n# Minimum value: 4, maximum value: 24, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTSIZE           = 10\n\n# By default doxygen will tell dot to use the default font as specified with\n# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set\n# the path where dot can find it using this tag.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTPATH           = \n\n# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for\n# each documented class showing the direct and indirect inheritance relations.\n# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCLASS_GRAPH            = YES\n\n# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a\n# graph for each documented class showing the direct and indirect implementation\n# dependencies (inheritance, containment, and class references variables) of the\n# class with other documented classes.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCOLLABORATION_GRAPH    = YES\n\n# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for\n# groups, showing the direct groups dependencies.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGROUP_GRAPHS           = YES\n\n# If the UML_LOOK tag is set to YES doxygen will generate inheritance and\n# collaboration diagrams in a style similar to the OMG's Unified Modeling\n# Language.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LOOK               = NO\n\n# If the UML_LOOK tag is enabled, the fields and methods are shown inside the\n# class node. If there are many fields or methods and many nodes the graph may\n# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the\n# number of items for each type to make the size more manageable. Set this to 0\n# for no limit. Note that the threshold may be exceeded by 50% before the limit\n# is enforced. So when you set the threshold to 10, up to 15 fields may appear,\n# but if the number exceeds 15, the total amount of fields shown is limited to\n# 10.\n# Minimum value: 0, maximum value: 100, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LIMIT_NUM_FIELDS   = 10\n\n# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and\n# collaboration graphs will show the relations between templates and their\n# instances.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nTEMPLATE_RELATIONS     = NO\n\n# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to\n# YES then doxygen will generate a graph for each documented file showing the\n# direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDE_GRAPH          = YES\n\n# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are\n# set to YES then doxygen will generate a graph for each documented file showing\n# the direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDED_BY_GRAPH      = YES\n\n# If the CALL_GRAPH tag is set to YES then doxygen will generate a call\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable call graphs for selected\n# functions only using the \\callgraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALL_GRAPH             = NO\n\n# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable caller graphs for selected\n# functions only using the \\callergraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALLER_GRAPH           = NO\n\n# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical\n# hierarchy of all classes instead of a textual one.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGRAPHICAL_HIERARCHY    = YES\n\n# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the\n# dependencies a directory has on other directories in a graphical way. The\n# dependency relations are determined by the #include relations between the\n# files in the directories.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDIRECTORY_GRAPH        = YES\n\n# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images\n# generated by dot.\n# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order\n# to make the SVG files visible in IE 9+ (other browsers do not have this\n# requirement).\n# Possible values are: png, jpg, gif and svg.\n# The default value is: png.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_IMAGE_FORMAT       = png\n\n# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to\n# enable generation of interactive SVG images that allow zooming and panning.\n#\n# Note that this requires a modern browser other than Internet Explorer. Tested\n# and working are Firefox, Chrome, Safari, and Opera.\n# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make\n# the SVG files visible. Older versions of IE do not have SVG support.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINTERACTIVE_SVG        = NO\n\n# The DOT_PATH tag can be used to specify the path where the dot tool can be\n# found. If left blank, it is assumed the dot tool can be found in the path.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_PATH               = \n\n# The DOTFILE_DIRS tag can be used to specify one or more directories that\n# contain dot files that are included in the documentation (see the \\dotfile\n# command).\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOTFILE_DIRS           = \n\n# The MSCFILE_DIRS tag can be used to specify one or more directories that\n# contain msc files that are included in the documentation (see the \\mscfile\n# command).\n\nMSCFILE_DIRS           = \n\n# The DIAFILE_DIRS tag can be used to specify one or more directories that\n# contain dia files that are included in the documentation (see the \\diafile\n# command).\n\nDIAFILE_DIRS           = \n\n# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes\n# that will be shown in the graph. If the number of nodes in a graph becomes\n# larger than this value, doxygen will truncate the graph, which is visualized\n# by representing a node as a red box. Note that doxygen if the number of direct\n# children of the root node in a graph is already larger than\n# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note that\n# the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.\n# Minimum value: 0, maximum value: 10000, default value: 50.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_GRAPH_MAX_NODES    = 50\n\n# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the graphs\n# generated by dot. A depth value of 3 means that only nodes reachable from the\n# root by following a path via at most 3 edges will be shown. Nodes that lay\n# further from the root node will be omitted. Note that setting this option to 1\n# or 2 may greatly reduce the computation time needed for large code bases. Also\n# note that the size of a graph can be further restricted by\n# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.\n# Minimum value: 0, maximum value: 1000, default value: 0.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nMAX_DOT_GRAPH_DEPTH    = 0\n\n# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent\n# background. This is disabled by default, because dot on Windows does not seem\n# to support this out of the box.\n#\n# Warning: Depending on the platform used, enabling this option may lead to\n# badly anti-aliased labels on the edges of a graph (i.e. they become hard to\n# read).\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_TRANSPARENT        = NO\n\n# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output\n# files in one run (i.e. multiple -o and -T options on the command line). This\n# makes dot run faster, but since only newer versions of dot (>1.8.10) support\n# this, this feature is disabled by default.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_MULTI_TARGETS      = NO\n\n# If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page\n# explaining the meaning of the various boxes and arrows in the dot generated\n# graphs.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGENERATE_LEGEND        = YES\n\n# If the DOT_CLEANUP tag is set to YES doxygen will remove the intermediate dot\n# files that are used to generate the various graphs.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_CLEANUP            = YES\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/rtos_CM0-7.dxy",
    "content": "# Doxyfile 1.8.6\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a double hash (##) is considered a comment and is placed in\n# front of the TAG it is preceding.\n#\n# All text after a single hash (#) is considered a comment and will be ignored.\n# The format is:\n# TAG = value [value, ...]\n# For lists, items can also be appended using:\n# TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\\\" \\\").\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the config file\n# that follow. The default is UTF-8 which is also the encoding used for all text\n# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv\n# built into libc) for the transcoding. See http://www.gnu.org/software/libiconv\n# for the list of possible encodings.\n# The default value is: UTF-8.\n\nDOXYFILE_ENCODING      = UTF-8\n\n# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by\n# double-quotes, unless you are using Doxywizard) that should identify the\n# project for which the documentation is generated. This name is used in the\n# title of most generated pages and in a few other places.\n# The default value is: My Project.\n\nPROJECT_NAME           = \"CMSIS-RTOS2\"\n\n# The PROJECT_NUMBER tag can be used to enter a project or revision number. This\n# could be handy for archiving the generated documentation or if some version\n# control system is used.\n\nPROJECT_NUMBER         = \"Version 2.1.3\"\n\n# Using the PROJECT_BRIEF tag one can provide an optional one line description\n# for a project that appears at the top of each page and should give viewer a\n# quick idea about the purpose of the project. Keep the description short.\n\nPROJECT_BRIEF          = \"Real-Time Operating System: API and RTX Reference Implementation\"\n\n# With the PROJECT_LOGO tag one can specify an logo or icon that is included in\n# the documentation. The maximum height of the logo should not exceed 55 pixels\n# and the maximum width should not exceed 200 pixels. Doxygen will copy the logo\n# to the output directory.\n\nPROJECT_LOGO           = ../Doxygen_Templates/CMSIS_Logo_Final.png\n\n# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path\n# into which the generated documentation will be written. If a relative path is\n# entered, it will be relative to the location where doxygen was started. If\n# left blank the current directory will be used.\n\nOUTPUT_DIRECTORY       = ../../Documentation/RTOS2\n\n# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create 4096 sub-\n# directories (in 2 levels) under the output directory of each output format and\n# will distribute the generated files over these directories. Enabling this\n# option can be useful when feeding doxygen a huge amount of source files, where\n# putting all generated files in the same directory would otherwise causes\n# performance problems for the file system.\n# The default value is: NO.\n\nCREATE_SUBDIRS         = NO\n\n# The OUTPUT_LANGUAGE tag is used to specify the language in which all\n# documentation generated by doxygen is written. Doxygen will use this\n# information to generate all constant output in the proper language.\n# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,\n# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),\n# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian,\n# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages),\n# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian,\n# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian,\n# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish,\n# Ukrainian and Vietnamese.\n# The default value is: English.\n\nOUTPUT_LANGUAGE        = English\n\n# If the BRIEF_MEMBER_DESC tag is set to YES doxygen will include brief member\n# descriptions after the members that are listed in the file and class\n# documentation (similar to Javadoc). Set to NO to disable this.\n# The default value is: YES.\n\nBRIEF_MEMBER_DESC      = YES\n\n# If the REPEAT_BRIEF tag is set to YES doxygen will prepend the brief\n# description of a member or function before the detailed description\n#\n# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the\n# brief descriptions will be completely suppressed.\n# The default value is: YES.\n\nREPEAT_BRIEF           = NO\n\n# This tag implements a quasi-intelligent brief description abbreviator that is\n# used to form the text in various listings. Each string in this list, if found\n# as the leading text of the brief description, will be stripped from the text\n# and the result, after processing the whole list, is used as the annotated\n# text. Otherwise, the brief description is used as-is. If left blank, the\n# following values are used ($name is automatically replaced with the name of\n# the entity):The $name class, The $name widget, The $name file, is, provides,\n# specifies, contains, represents, a, an and the.\n\nABBREVIATE_BRIEF       = \"The $name class\" \\\n                         \"The $name widget\" \\\n                         \"The $name file\" \\\n                         is \\\n                         provides \\\n                         specifies \\\n                         contains \\\n                         represents \\\n                         a \\\n                         an \\\n                         the\n\n# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then\n# doxygen will generate a detailed section even if there is only a brief\n# description.\n# The default value is: NO.\n\nALWAYS_DETAILED_SEC    = NO\n\n# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all\n# inherited members of a class in the documentation of that class as if those\n# members were ordinary class members. Constructors, destructors and assignment\n# operators of the base classes will not be shown.\n# The default value is: NO.\n\nINLINE_INHERITED_MEMB  = NO\n\n# If the FULL_PATH_NAMES tag is set to YES doxygen will prepend the full path\n# before files name in the file list and in the header files. If set to NO the\n# shortest path that makes the file name unique will be used\n# The default value is: YES.\n\nFULL_PATH_NAMES        = NO\n\n# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.\n# Stripping is only done if one of the specified strings matches the left-hand\n# part of the path. The tag can be used to show relative paths in the file list.\n# If left blank the directory from which doxygen is run is used as the path to\n# strip.\n#\n# Note that you can specify absolute paths here, but also relative paths, which\n# will be relative from the directory where doxygen is started.\n# This tag requires that the tag FULL_PATH_NAMES is set to YES.\n\nSTRIP_FROM_PATH        = \n\n# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the\n# path mentioned in the documentation of a class, which tells the reader which\n# header file to include in order to use a class. If left blank only the name of\n# the header file containing the class definition is used. Otherwise one should\n# specify the list of include paths that are normally passed to the compiler\n# using the -I flag.\n\nSTRIP_FROM_INC_PATH    = \n\n# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but\n# less readable) file names. This can be useful is your file systems doesn't\n# support long names like on DOS, Mac, or CD-ROM.\n# The default value is: NO.\n\nSHORT_NAMES            = NO\n\n# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the\n# first line (until the first dot) of a Javadoc-style comment as the brief\n# description. If set to NO, the Javadoc-style will behave just like regular Qt-\n# style comments (thus requiring an explicit @brief command for a brief\n# description.)\n# The default value is: NO.\n\nJAVADOC_AUTOBRIEF      = NO\n\n# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first\n# line (until the first dot) of a Qt-style comment as the brief description. If\n# set to NO, the Qt-style will behave just like regular Qt-style comments (thus\n# requiring an explicit \\brief command for a brief description.)\n# The default value is: NO.\n\nQT_AUTOBRIEF           = NO\n\n# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a\n# multi-line C++ special comment block (i.e. a block of //! or /// comments) as\n# a brief description. This used to be the default behavior. The new default is\n# to treat a multi-line C++ comment block as a detailed description. Set this\n# tag to YES if you prefer the old behavior instead.\n#\n# Note that setting this tag to YES also means that rational rose comments are\n# not recognized any more.\n# The default value is: NO.\n\nMULTILINE_CPP_IS_BRIEF = YES\n\n# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the\n# documentation from any documented member that it re-implements.\n# The default value is: YES.\n\nINHERIT_DOCS           = NO\n\n# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a\n# new page for each member. If set to NO, the documentation of a member will be\n# part of the file/class/namespace that contains it.\n# The default value is: NO.\n\nSEPARATE_MEMBER_PAGES  = NO\n\n# The TAB_SIZE tag can be used to set the number of spaces in a tab. \n# Doxygen uses this value to replace tabs by spaces in code fragments.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that acts \n# as commands in the documentation. An alias has the form \"name=value\". \n# For example adding \"sideeffect=\\par Side Effects:\\n\" will allow you to \n# put the command \\sideeffect (or @sideeffect) in the documentation, which \n# will result in a user-defined paragraph with heading \"Side Effects:\". \n# You can put \\n's in the value part of an alias to insert newlines.\n\nALIASES                = \"token{1}=<span class=\\\"XML-Token\\\">\\1</span>\" \\\n                         \"div{1}=<hr><div class=\\\"\\1\\\">\" \\\n                         \"enddiv= </div>\" \\\n                         \"func{1}=<kbd>\\1</kbd> <br>\" \\\n                         \"copybrief{1}=<br> \\copybrief \\1 <br>\" \\\n                         \"none=\\em none <br>\"\n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding \"class=itcl::class\"\n# will allow you to use the command class in the itcl::class meaning.\n\nTCL_SUBST              = \n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources\n# only. Doxygen will then generate output that is more tailored for C. For\n# instance, some of the names that are used will be different. The list of all\n# members will be omitted, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_FOR_C  = YES\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or\n# Python sources only. Doxygen will then generate output that is more tailored\n# for that language. For instance, namespaces will be presented as packages,\n# qualified scopes will look different, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources. Doxygen will then generate output that is tailored for Fortran.\n# The default value is: NO.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for VHDL.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given\n# extension. Doxygen has a built-in mapping, but you can override or extend it\n# using this tag. The format is ext=language, where ext is a file extension, and\n# language is one of the parsers supported by doxygen: IDL, Java, Javascript,\n# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C.\n#\n# Note For files without extension you can use no_extension as a placeholder.\n#\n# Note that for custom extensions you also need to set FILE_PATTERNS otherwise\n# the files are not read by doxygen.\n\nEXTENSION_MAPPING      = \n\n# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments\n# according to the Markdown format, which allows for more readable\n# documentation. See http://daringfireball.net/projects/markdown/ for details.\n# The output of markdown processing is further processed by doxygen, so you can\n# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in\n# case of backward compatibilities issues.\n# The default value is: YES.\n\nMARKDOWN_SUPPORT       = YES\n\n# When enabled doxygen tries to link words that correspond to documented\n# classes, or namespaces to their corresponding documentation. Such a link can\n# be prevented in individual cases by by putting a % sign in front of the word\n# or globally by setting AUTOLINK_SUPPORT to NO.\n# The default value is: YES.\n\nAUTOLINK_SUPPORT       = YES\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should set this\n# tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string);\n# versus func(std::string) {}). This also make the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n# The default value is: NO.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n# The default value is: NO.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:\n# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen\n# will parse them like normal C++ but will assume all classes use public instead\n# of private inheritance when no explicit protection keyword is present.\n# The default value is: NO.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate\n# getter and setter methods for a property. Setting this option to YES will make\n# doxygen to replace the get and set methods by a property in the documentation.\n# This will only work if the methods are indeed getting or setting a simple\n# type. If this is not the case, or you want to show the methods anyway, you\n# should set this option to NO.\n# The default value is: YES.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n# The default value is: NO.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES to allow class member groups of the same type\n# (for instance a group of public functions) to be put as a subgroup of that\n# type (e.g. under the Public Functions section). Set it to NO to prevent\n# subgrouping. Alternatively, this can be done per class using the\n# \\nosubgrouping command.\n# The default value is: YES.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions\n# are shown inside the group in which they are included (e.g. using \\ingroup)\n# instead of on a separate page (for HTML and Man pages) or section (for LaTeX\n# and RTF).\n#\n# Note that this feature does not work in combination with\n# SEPARATE_MEMBER_PAGES.\n# The default value is: NO.\n\nINLINE_GROUPED_CLASSES = YES\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions\n# with only public data fields or simple typedef fields will be shown inline in\n# the documentation of the scope in which they are defined (i.e. file,\n# namespace, or group documentation), provided this scope is documented. If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = YES\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = NO\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = NO\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = YES\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = NO\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = YES\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = NO\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = NO\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = NO\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = \n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = YES\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         = \n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = . \\\n                         ./src/mainpage.txt \\\n                         ./src/history.txt \\\n                         ./src/cmsis_os2.txt \\\n                         ./src/cmsis_os2_Kernel.txt \\\n                         ./src/cmsis_os2_Thread.txt \\\n                         ./src/cmsis_os2_ThreadFlags.txt \\\n                         ./src/cmsis_os2_Event.txt \\\n                         ./src/cmsis_os2_Wait.txt \\\n                         ./src/cmsis_os2_Timer.txt \\\n                         ./src/cmsis_os2_Mutex.txt \\\n                         ./src/cmsis_os2_Sema.txt \\\n                         ./src/cmsis_os2_MemPool.txt \\\n                         ./src/cmsis_os2_Message.txt \\\n                         ./src/cmsis_os2_Status.txt \\\n                         ./src/cmsis_os2_Migration.txt \\\n                         ./src/cmsis_os2_MigrationGuide.txt \\\n                         ./src/cmsis_os2_tick.txt \\\n                         ./src/validation.txt \\\n                         ./src/rtx_os.txt \\\n                         ./src/rtx_evr.txt \\\n                         ../../RTOS2/Include/cmsis_os2.h \\\n                         ../../RTOS2/Include/os_tick.h \\\n                         ../../RTOS2/RTX/Include/rtx_os.h \\\n                         ../../RTOS2/RTX/Include/rtx_evr.h \n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          = *.c \\\n                         *.cc \\\n                         *.cxx \\\n                         *.cpp \\\n                         *.c++ \\\n                         *.java \\\n                         *.ii \\\n                         *.ixx \\\n                         *.ipp \\\n                         *.i++ \\\n                         *.inl \\\n                         *.h \\\n                         *.hh \\\n                         *.hxx \\\n                         *.hpp \\\n                         *.h++ \\\n                         *.idl \\\n                         *.odl \\\n                         *.cs \\\n                         *.php \\\n                         *.php3 \\\n                         *.inc \\\n                         *.m \\\n                         *.mm \\\n                         *.dox \\\n                         *.py \\\n                         *.f90 \\\n                         *.f \\\n                         *.for \\\n                         *.vhd \\\n                         *.vhdl \\\n                         *.txt\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = NO\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = YES\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       = \n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        = \n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = ../../RTOS2/Include \\\n                         ../../RTOS2 \\\n                         ../../RTOS2/RTX/Include \\\n                         ../../RTOS2/Template\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           = \n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        = \n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS = \n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE = \n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = NO\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = YES\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = YES\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = YES\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        = \n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../Doxygen_Templates/printComponentTabs.js \\\n                         ../Doxygen_Templates/search.css\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 103\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = \n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     = \n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               = \n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   = \n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  = \n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  = \n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           = \n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     = \n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       = \n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       = \n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     = \n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         = \n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           = \n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           = \n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      = \n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    = \n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             = \n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                = \n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen\n# Definitions (see http://autogen.sf.net) file that captures the structure of\n# the code including all documentation. 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    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt",
    "content": "/**\n\\page genRTOS2IF Generic RTOS Interface\n\nCMSIS-RTOS2 is a generic API that is agnostic of the underlying RTOS kernel. Application programmers call CMSIS-RTOS2 API\nfunctions in the user code to ensure maximum portability from one RTOS to another. Middleware using CMSIS-RTOS2 API takes\nadvantages of this approach by avoiding unnecessary porting efforts.\n\n\\image html \"API_Structure.png\" \"CMSIS-RTOS API Structure\"\n\nA typical CMSIS-RTOS2 API implementation interfaces to an existing real-time kernel. The CMSIS-RTOS2 API provides the\nfollowing attributes and functionalities:\n - Function names, identifiers, and parameters are descriptive and easy to understand. The functions are powerful and\n   flexible which reduces the number of functions exposed to the user. \n - \\ref CMSIS_RTOS_ThreadMgmt allows you to define, create, and control threads.\n - Interrupt Service Routines (ISR) can \\ref CMSIS_RTOS_ISR_Calls \"call some CMSIS-RTOS functions\". When a CMSIS-RTOS\n   function cannot be called from an ISR context, it rejects the invocation and returns an error code.\n - Three different event types support communication between multiple threads and/or ISR:\n   - \\ref CMSIS_RTOS_ThreadFlagsMgmt \"Thread Flags\": may be used to indicate specific conditions to a thread.\n   - \\ref CMSIS_RTOS_EventFlags \"Event Flags\": may be used to indicate events to a thread or ISR.\n   - \\ref CMSIS_RTOS_Message \"Messages\": can be sent to a thread or an ISR. Messages are buffered in a queue.\n - \\ref CMSIS_RTOS_MutexMgmt and \\ref CMSIS_RTOS_SemaphoreMgmt are incorporated.\n - CPU time can be scheduled with the following functionalities:\n   - A \\a timeout parameter is incorporated in many CMSIS-RTOS functions to avoid system lockup. When a timeout is specified,\n     the system waits until a resource is available or an event occurs. While waiting, other threads are scheduled.\n   - The \\ref osDelay and \\ref osDelayUntil functions put a thread into the \\b WAITING state for a specified period of time.\n   - The \\ref osThreadYield provides co-operative thread switching and passes execution to another thread of the same\n     priority.\n - \\ref CMSIS_RTOS_TimerMgmt  functions are used to trigger the execution of functions.\n\nThe CMSIS-RTOS2 API is designed to optionally incorporate multi-processor systems and/or access protection via the Cortex-M\nMemory Protection Unit (MPU).\n\nIn some RTOS implementations threads may execute on different processors, thus \\b message queues may reside in shared memory\nresources.\n\nThe CMSIS-RTOS2 API encourages the software industry to evolve existing RTOS implementations. RTOS implementations can be\ndifferent and optimized in various aspects towards the Cortex-M processors. Optional features may be for example\n - Support of the Cortex-M Memory Protection Unit (MPU).\n - Support of multi-processor systems.\n - Support of a DMA controller.\n - Deterministic context switching.\n - Round-robin context switching.\n - Deadlock avoidance, for example with priority inversion.\n - Zero interrupt latency by using Armv7-M instructions LDREX and STREX.\n\n\\section cmsis_os2_h cmsis_os2.h header file\n\nThe file \\b %cmsis_os2.h is a standard header file that interfaces to every CMSIS-RTOS2 compliant real-time operating\nsystems (RTOS). Each implementation is provided the same \\b cmsis_os2.h which defines the interface to the \\ref rtos_api2.\n\nUsing the \\b cmsis_os2.h along with dynamic object allocation allows to create source code or libraries that require no\nmodifications when using on a different CMSIS-RTOS2 implementation.\n\n\\section usingOS2 Using a CMSIS-RTOS2 Implementation\n\nA CMSIS-RTOS2 component may be provided as library or source code (the picture below shows a library). \nA CMSIS-based application is extended with RTOS functionality by adding a CMSIS-RTOS2 component (and typically some configuration files).\nThe \\ref cmsis_os2_h gives access to RTOS API functions and is the only interface header required when dynamic object allocation is used.\nThis enables portable application that works with every RTOS kernel event without re-compilation of the source code when the kernel is \nchanged.\n\nStatic object allocation requires access to RTOS object control block definitions. An implementation specific header file (<i>rtos</i>.h in \nthe picture below) provides access to such definitions. The section For RTX v5 these definitions are provided in the header file %rtx_os.h that contains this definitions for RTX v5.\n\n\n\\image html \"CMSIS_RTOS_Files.png\" \"CMSIS-RTOS File Structure\"\n\nOnce the files are added to a project, the user can start working with the CMSIS-RTOS functions.  A code example is provided\nbelow:\n \n<b>Code Example</b>\n\\code\n/*----------------------------------------------------------------------------\n * CMSIS-RTOS 'main' function template\n *---------------------------------------------------------------------------*/\n \n#include \"RTE_Components.h\"\n#include  CMSIS_device_header\n#include \"cmsis_os2.h\"\n \n/*----------------------------------------------------------------------------\n * Application main thread\n *---------------------------------------------------------------------------*/\nvoid app_main (void *argument) {\n \n  // ...\n  for (;;) {}\n}\n \nint main (void) {\n \n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n \n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  osKernelStart();                      // Start thread execution\n  for (;;) {}\n}\n\\endcode\n\n\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page rtx5_impl RTX v5 Implementation\n\nKeil RTX version 5 (RTX5) implements the CMSIS-RTOS2 as a native RTOS interface for Arm Cortex-M processor-based devices.\nA translation layer to CMSIS-RTOS API v1 is provided. Therefore, RTX5 can be used in applications that where previously based\non RTX version 4 and CMSIS-RTOS version 1 with minimal effort.\n\nThe following sections provide further details:\n - \\subpage cre_rtx_proj explains how to setup an RTX v5 project in Keil MDK.\n - \\subpage theory_of_operation provides general information about the operation of CMSIS-RTOS RTX v5.\n - \\subpage config_rtx5 describes configuration parameters of CMSIS-RTOS RTX v5.\n\\ifnot FuSaRTS\n - \\subpage creating_RTX5_LIB explains how to build your own CMSIS-RTOS RTX v5 library.\n\\endif\n - \\subpage rtos2_tutorial is an introduction into the usage of Keil RTX5 based on real-life examples.\n - \\subpage technicalData5 lists hardware, software, and resource requirements, supplied files, and supported tool chains.\n - \\subpage misraCompliance5 describes the violations to the MISRA standard.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page cre_rtx_proj Create an RTX5 Project\n\n\\if FuSaRTS\nFuSa RTX5 installation and project setup are explained in \\ref fusa_rtx_installation.\n\n\\endif\n\n\\ifnot FuSaRTS\nThe steps to create a microcontroller application using RTX5 are:\n- Create a new project and select a microcontroller device.\n- In the Manage Run-Time Environment window, select <b>CMSIS\\::CORE</b> and <b>CMSIS\\::RTOS2 (API)\\::Keil RTX5</b>. You can\n  choose to either add RTX as a library (Variant: \\b Library) or to add the full source code (Variant: \\b Source - required\n  if using the <a href=\"https://www.keil.com/pack/doc/compiler/EventRecorder/html/index.html\" target=\"_blank\"><b>Event Recorder</b></a>):\n\n   \\image html manage_rte_output.png\n\n- If the <b>Validation Output</b> requires other components to be present, try to use the \\b Resolve button.\n- Click \\b OK. In the \\b Project window, you will see the files that have been automatically added to you project, such as\n  \\b %RTX_Config.h, \\b %RTX_Config.c, the library or the source code files, as well as the system and startup files:\n\n   \\image html project_window.png\n\n- If using the Variant: \\b Source as stated above, you have to assure to use at least C99 compiler mode (Project Options -> C/C++ -> C99 Mode).   \n- You can add template files to the project by right-clicking on <b>Source Group 1</b> and selecting\n  <b>Add New Item to 'Source Group 1'</b>. In the new window, click on <b>User Code Template</b>. On the right-hand side\n  you will see all available template files for CMSIS-RTOS RTX:\n  \n   \\image html add_item.png\n\n- \\ref config_rtx5 \"Configure\" RTX5 to the application's needs using the \\b %RTX_Config.h file.\n\n\\endif\n\n\\if ARMCA \\section cre_rtx_cortexa Additional requirements for RTX on Cortex-A\n\nCortex-A based microcontrollers are less unified with respect to the interrupt and timer implementations used compared to \nM-class devices. Thus RTX requires additional components when an A-class device is used, namely\n<a href=\"../../Core_A/html/group__irq__ctrl__gr.html\"><b>IRQ Controller (API)</b></a> and \\ref CMSIS_RTOS_TickAPI \"OS Tick (API)\"\nimplementations. \n\n\\image html manage_rte_cortex-a.png\n\nThe default implementations provided along with CMSIS are \n- Arm <a href=\"../../Core_A/html/group__GIC__functions.html\">Generic Interrupt Controller (GIC)</a>\n- Arm Cortex-A5, Cortex-A9 <a href=\"../../Core_A/html/group__PTM__timer__functions.html\">Private Timer (PTIM)</a>\n- Arm Cortex-A7 <a href=\"../../Core_A/html/group__PL1__timer__functions.html\">Generic Physical Timer (GTIM)</a>\n\nFor devices not implementing GIC, PTIM nor GTIM please refer to the according device family pack and select the\nproper implementations.\n\n\\endif\n\n\\section cre_UsingIRQs Using Interrupts on Cortex-M\n\nOn Cortex-M processors, the RTX5 kernel uses the following interrupt exceptions.  The table below also lists the \npriorities that must be assigned to these interrupts.\n\nHandler | Priority | Interrupt/Exception\n:-------|:---------|:----------------------------\nSysTick | lowest   | Kernel system timer interrupt to generate periodic timer ticks\nPendSV  | lowest   | PendSV (request for system-level service) when calling certain RTX functions from \\b Handler mode\nSVC     | lowest+1 | Supervisor Call used to enter the RTOS kernel from \\b Thread mode\n\nOther device interrupts can be used without limitation. For Arm Cortex-M3/M4/M7 \\if ARMv8M /M23/M33/M35P \\endif  processors, interrupts are never disabled by RTX Kernel.\n\n<b>Usage of interrupt priority grouping</b>\n- The interrupt priority grouping should be configured using the CMSIS-Core function NVIC_SetPriorityGrouping before calling the function \n  \\ref osKernelStart(). The RTX kernel uses the priority group value to setup the priority for SysTick and PendSV interrupts.\n- The RTX kernel sets the priority for the interrupts/exceptions listed in above table and uses the lowest two priority levels.\n- Do not change the priority used by the RTX kernel. If this cannot be avoided, ensure that the preempt priority of\n  SysTick/PendSV is lower than SVC.\n- Permitted priority group values are 0 to 6. The priority group value 7 will cause RTX to fail as there is only one priority level available.\n- The <b>main stack</b> is used to run the RTX functionality. It is therefore required to configure sufficient stack for the RTX kernel execution.\n\n<b>Code Example</b>\n\\code\nosKernelInitialize();                            // initialize RTX\nNVIC_SetPriorityGrouping (3);                    // setup priority grouping\ntread_id = osThreadNew(tread_func, NULL, NULL);  // create some threads\nosKernelStart ();                                // start RTX kernel\n\\endcode\n\n\\section cre_rtx_proj_specifics Add support for RTX specific functions\nIf you require some of the \\ref rtx5_specific \"RTX specific functions\" in your application code, \\#include the\n\\ref rtx_os_h \"header file rtx_os.h\". This enables \\ref lowPower \"low-power\" and \\ref TickLess \"tick-less\" operation modes.\n\n\\section cre_rtx_proj_er Add Event Recorder Visibility\n\n\\ifnot FuSaRTS\nRTX5 interfaces to the <a href=\"https://www.keil.com/pack/doc/compiler/EventRecorder/html/index.html\" target=\"_blank\"><b>Event Recorder</b></a> \nto provide event information which helps you to understand and analyze the operation.\n\n- To use the Event Recorder together with RTX5, select the software component <b>Compiler:Event Recorder</b>.\n- Select the \\b Source variant of the software component <b>CMSIS:RTOS2 (API):Keil RTX5</b>.\n\n  \\image html event_recorder_rte.png \"Component selection for Event Recorder\"\n  \n- Enable the related settings under \\ref evtrecConfig.\n- Build the application code and download it to the debug hardware.\n\\endif\nOnce the target application generates event information, it can be viewed in the µVision debugger using the \\b Event \\b Recorder.\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page theory_of_operation Theory of Operation\n\nMany aspects of the kernel are configurable and the configuration options are mentioned where applicable.\n\n\\section SystemStartup System Startup\n\nSince main is no longer a thread RTX5 does not interfere with the system startup until main is reached.\nOnce the execution reaches \\c main() there is a recommended order to initialize the hardware and start the kernel. This is\nalso reflected in the user code template file \"CMSIS-RTOS2 'main' function\" supplied with the RTX5 component.\n\nYour application's \\c main() should implement at least the following in the given order:\n-# Initialization and configuration of hardware including peripherals, memory, pins, clocks and the interrupt system.\n-# Update the system core clock using the respective\n   <a href=../../Core/html/group__system__init__gr.html>CMSIS-Core (Cortex-M)</a>  \\if ARMCA or <a href=../../Core_A/html/group__system__init__gr.html>CMSIS-Core (Cortex-A)</a> \\endif function.\n-# Initialize the CMSIS-RTOS kernel using \\ref osKernelInitialize.\n-# Optionally, create one thread (for example \\c app_main), which is used as a main thread using \\ref osThreadNew. This\n   thread should take care of creating and starting objects, once it is run by the scheduler. Alternatively, threads can be\n   created in \\c main() directly.\n-# Start the RTOS scheduler using \\ref osKernelStart which also configures the system tick timer and initializes RTOS\n   specific interrupts. This function does not return in case of successful execution. Therefore, any application code after\n   \\b osKernelStart will not be executed.\n\n\\note\n- Modifying priorities and groupings in the NVIC by the application after the above sequence is not recommended.\n- Before executing \\ref osKernelStart, only the functions \\ref osKernelGetInfo, \\ref osKernelGetState, and object creation\n  functions (osXxxNew) may be called.\n\n\n\\section Scheduler \n\nRTX5 implements a low-latency preemptive scheduler. Major parts of RTX5 are executed in handler mode such as\n  - \\ref SysTick_Handler used for time-based scheduling.\n  - \\ref SVC_Handler used for lock-based scheduling.\n  - \\ref PendSV_Handler used for interrupt-based scheduling.\n\nIn order to be low-latency with respect to ISR execution those system exceptions are configured to use the\nlowest priority groups available. The priorities are configured such that no preemption happens between them. Thus\nno interrupt critical sections (i.e. interrupt locks) are needed to protect the scheduler.\n\n\\image html scheduling.png \"Thread scheduling and interrupt execution\"\n\nThe scheduler combines priority and round-robin based context switches. The example depicted in the image above contains\nfour threads (1, 2, 3, and 4). Threads 1 and 2 share the same priority, thread 3 has a higher one and thread 4 the highest\n(\\ref osThreadAttr_t::priority). As long as threads 3 and 4 are blocked the scheduler switches between thread 1 and 2 on\na time-slice basis (round-robin). The time-slice for round-robin scheduling can be configured, see Round-Robin Timeout in \\ref systemConfig.\n\nThread 2 unblocks thread 3 by an arbitrary RTOS-call (executed in \\ref CMSIS_RTOS_svcFunctions \"SVC\" handler mode) at time\nindex 2. The scheduler switches to thread 3 immediately because thread 3 has the highest priority. Thread 4 is still blocked.\n\nAt time index 4 an interrupt (ISR) occurs and preempts the SysTick_Handler. RTX does not add any latency to the interrupt\nservice execution. The ISR routine uses an RTOS-call that unblocks thread 4. Instead of switching to thread 4 immediately\nthe PendSV flag is set to defer the context switching. The PendSV_Handler is executed right after the SysTick_Handler returns\nand the deferred context switch to thread 4 is carried out. As soon as highest priority thread 4 blocks again by using\na blocking RTOS-call execution is switched back to thread 3 immediately during time index 5.\n\nAt time index 5 thread 3 uses a blocking RTOS-call as well. Thus the scheduler switches back to thread 2 for time index 6.\nAt time index 7 the scheduler uses the round-robin mechanism to switch to thread 1 and so on.\n\n\\section MemoryAllocation Memory Allocation \n\nRTX5 objects (thread, mutex, semaphore, timer, message queue, thread and event flags, as well as memory pool) require\ndedicated RAM memory. Objects can be created using os<i>Object</i>New() calls and deleted using os<i>Object</i>Delete()\ncalls. The related object memory needs to be available during the lifetime of the object.\n\nRTX5 offers three different memory allocation methods for objects:\n  - \\ref GlobalMemoryPool uses a single global memory pool for all objects. It is easy to configure, but may have \n    the disadvantage for memory fragmentation when objects with different sizes are created and destroyed.\n  - \\ref ObjectMemoryPool uses a fixed-size memory pool for each object type. The method is time deterministic\n     and avoids memory fragmentation.\n  - \\ref StaticObjectMemory reserves memory during compile time and completely avoids that a system can be out of memory.\n    This is typically a required for some safety critical systems.\n\nIt possible to intermix all the memory allocation methods in the same application.\n\n\\subsection GlobalMemoryPool Global Memory Pool\n\nThe global memory pool allocates all objects from a memory area. This method of memory allocation is the default\nconfiguration setting of RTX5.\n\n\\image html MemAllocGlob.png \"Global Memory Pool for all objects\"\n\nWhen the memory pool does not provide sufficient memory, the creation of the object fails and the related\nos<i>Object</i>New() function returns \\token{NULL}.\n\nEnabled in \\ref systemConfig.\n\n\\subsection ObjectMemoryPool Object-specific Memory Pools\n\nObject-specific memory pools avoids memory fragmentation with a dedicated fixed-size memory management for each object type.\nThis type of memory pools are fully time deterministic, which means that object creation and destruction takes always the\nsame fixed amount of time. As a fixed-size memory pool is specific to an object type, the handling of out-of-memory\nsituations is simplified.\n\n\\image html MemAllocSpec.png \"One memory pool per object type\"\n\nObject-specific memory pools are selectively enabled for each object type, e.g: mutex or thread using the RTX configuration\nfile:\n - Enabled in \\ref threadConfig for thread objects.\n - Enabled in \\ref timerConfig for timer objects.\n - Enabled in \\ref eventFlagsConfig for event objects.\n - Enabled in \\ref mutexConfig for mutex objects.\n - Enabled in \\ref semaphoreConfig for semaphore.\n - Enabled in \\ref memPoolConfig for memory pools.\n - Enabled in \\ref msgQueueConfig for message objects.\n\nWhen the memory pool does not provide sufficient memory, the creation of the object fails and the related\nos<i>Object</i>New() function returns \\token{NULL}.\n\n\\subsection StaticObjectMemory Static Object Memory\nIn contrast to the dynamic memory allocations, the static memory allocation requires compile-time allocation of object memory. \n\n\\image html MemAllocStat.png \"Statically allocated memory for all objects\"\n\nStatic memory allocation can be achieved by providing user-defined memory using attributes at object creation,\nsee \\ref CMSIS_RTOS_MemoryMgmt_Manual. Please take special note of the following restrictions:\n\nMemory type                                  | Requirements\n---------------------------------------------|-------------------------------------------------------------------------------\nControl Block (osXxxAttr_t::cb_mem)          | 4-Byte alignment. Size defined by \\ref osRtxThreadCbSize, \\ref osRtxTimerCbSize, \\ref osRtxEventFlagsCbSize, \\ref osRtxMutexCbSize, \\ref osRtxSemaphoreCbSize, \\ref osRtxMemoryPoolCbSize, \\ref osRtxMessageQueueCbSize.\nThread Stack (osThreadAttr_t::stack_mem)     | 8-Byte alignment. Size is application specific, i.e. amount of stack variables and frames.\nMemory Pool (osMemoryPoolAttr_t::mp_mem)     | 4-Byte alignment. Size calculated with \\ref osRtxMemoryPoolMemSize.\nMessage Queue (osMessageQueueAttr_t::mq_mem) | 4-Byte alignment. Size calculated with \\ref osRtxMessageQueueMemSize.\n\n\nIn order to allow RTX5 aware debugging, i.e. Component Viewer, to recognize control blocks these\nneeds to be placed in individual memory sections, i.e. using `__attribute__((section(...)))`.\n\nRTX Object    | Linker Section \n--------------|------------------------\nThread        | `.bss.os.thread.cb`\nTimer         | `.bss.os.timer.cb`\nEvent Flags   | `.bss.os.evflags.cb`\nMutex         | `.bss.os.mutex.cb`\nSemaphore     | `.bss.os.semaphore.cb`\nMemory Pool   | `.bss.os.mempool.cb`\nMessage Queue | `.bss.os.msgqueue.cb`\n\nIt must be assured that these sections are placed into contiguous memory. This can fail,\ni.e. sections end up being split over multiple memory segments, when assigning compilation\nunits to memory segments, manually.\n\nThe following code example shows how to create an OS object using static memory.\n\n<b> Code Example:</b> \n\\code{.c}\n/*----------------------------------------------------------------------------\n * CMSIS-RTOS 'main' function template\n *---------------------------------------------------------------------------*/\n\n#include \"RTE_Components.h\"\n#include  CMSIS_device_header\n#include \"cmsis_os2.h\"\n \n//include rtx_os.h for types of RTX objects\n#include \"rtx_os.h\"\n \n//The thread function instanced in this example\nvoid worker(void *arg)\n{\n  while(1) \n  {\n    //work\n    osDelay(10000);\n  }  \n}\n \n// Define objects that are statically allocated for worker thread 1\n__attribute__((section(\".bss.os.thread.cb\")))\nosRtxThread_t worker_thread_tcb_1;\n \n// Reserve two areas for the stacks of worker thread 1\n// uint64_t makes sure the memory alignment is 8\nuint64_t worker_thread_stk_1[64];\n \n// Define the attributes which are used for thread creation\n// Optional const saves RAM memory and includes the values in periodic ROM tests \nconst osThreadAttr_t worker_attr_1 = {\n  \"wrk1\",\n  osThreadJoinable,\n  &worker_thread_tcb_1,\n  sizeof(worker_thread_tcb_1),\n  &worker_thread_stk_1[0],\n  sizeof(worker_thread_stk_1),\n  osPriorityAboveNormal,\n  0\n};\n \n// Define ID object for thread\nosThreadId_t th1;\n \n/*----------------------------------------------------------------------------\n * Application main thread\n *---------------------------------------------------------------------------*/\nvoid app_main (void *argument) {\n  uint32_t param = NULL;\n \n  // Create an instance of the worker thread with static resources (TCB and stack)\n  th1 = osThreadNew(worker, &param, &worker_attr_1);\n \n  for (;;) {}\n}\n \nint main (void) {\n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n\n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  osKernelStart();                      // Start thread execution\n  for (;;) {}\n}\n\\endcode\n\n\n\\section ThreadStack Thread Stack Management\n\nFor Cortex-M processors without floating point unit the thread context requires 64 bytes on the local stack.\n\n\\note For Cortex-M4/M7 with FP the thread context requires 200 bytes on the local stack. For these devices the default stack\nspace should be increased to a minimum of 300 bytes.\n\nEach thread is provided with a separate stack that holds the thread context and stack space for automatic variables and\nreturn addresses for function call nesting. The stack sizes of RTX threads are flexibly configurable as explained in the\nsection \\ref threadConfig. RTX offers a configurable checking for stack overflows and stack utilization. \n\n\n\\section lowPower Low-Power Operation\n\nThe system thread \\b osRtxIdleThread can be use to switch the system into a low-power mode. The easiest form to enter a\nlow-power mode is the execution of the \\c __WFE function that puts the processor into a sleep mode where it waits for an\nevent.\n\n<b>Code Example:</b>\n\\code\n#include \"RTE_Components.h\"\n#include CMSIS_device_header            /* Device definitions                 */\n \nvoid osRtxIdleThread (void) {\n  /* The idle demon is a system thread, running when no other thread is       */\n  /* ready to run.                                                            */\n \n  for (;;) {\n    __WFE();                            /* Enter sleep mode                   */\n  }\n}\n\\endcode\n\n\\note\n\\c __WFE() is not available in every Cortex-M implementation. Check device manuals for availability.\n\n\n\\section kernelTimer RTX Kernel Timer Tick\n\nRTX uses the generic \\ref CMSIS_RTOS_TickAPI to configure and control its periodic Kernel Tick.\n\nTo use an alternative timer as the Kernel Tick Timer one simply needs to implement a custom version\nof the \\ref CMSIS_RTOS_TickAPI.\n\n\\note The OS Tick implementation provided must assure that the used timer interrupt uses the same (low) priority group \nas the service interrupts, i.e. interrupts used by RTX must not preempt each other. Refer to the \\ref Scheduler section\nfor more details.\n\n\\subsection TickLess Tick-less Low-Power Operation\n\nRTX5 provides extension for tick-less operation which is useful for applications that use extensively low-power modes where\nthe SysTick timer is also disabled. To provide a time-tick in such power-saving modes, a wake-up timer is used to\nderive timer intervals. The CMSIS-RTOS2 functions \\ref osKernelSuspend and \\ref osKernelResume control the tick-less\noperation.\n\nUsing this functions allows the RTX5 thread scheduler to stop the periodic kernel tick interrupt. When all active threads\nare suspended, the system enters power-down and calculates how long it can stay in this power-down mode. In the power-down\nmode the processor and peripherals can be switched off. Only a wake-up timer must remain powered, because this timer is\nresponsible to wake-up the system after the power-down period expires.\n\nThe tick-less operation is controlled from the \\b osRtxIdleThread thread. The wake-up timeout value is set before the system\nenters the power-down mode. The function \\ref osKernelSuspend calculates the wake-up timeout measured in RTX Timer Ticks;\nthis value is used to setup the wake-up timer that runs during the power-down mode of the system.\n\nOnce the system resumes operation (either by a wake-up time out or other interrupts) the RTX5 thread scheduler is started\nwith the function \\ref osKernelResume. The parameter \\a sleep_time specifies the time (in RTX Timer Ticks) that the system\nwas in power-down mode.\n\n<b>Code Example:</b>\n\\code\n#include \"msp.h\"                        // Device header\n\n/*----------------------------------------------------------------------------\n *      MSP432 Low-Power Extension Functions\n *---------------------------------------------------------------------------*/\nstatic void MSP432_LP_Entry(void) {\n  /* Enable PCM rude mode, which allows to device to enter LPM3 without waiting for peripherals */\n  PCM->CTL1 = PCM_CTL1_KEY_VAL | PCM_CTL1_FORCE_LPM_ENTRY;       \n  /* Enable all SRAM bank retentions prior to going to LPM3  */\n  SYSCTL->SRAM_BANKRET |= SYSCTL_SRAM_BANKRET_BNK7_RET;\n  __enable_interrupt();\n  NVIC_EnableIRQ(RTC_C_IRQn);\n  /* Do not wake up on exit from ISR */\n  SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;\n  /* Setting the sleep deep bit */\n  SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk);\t\n}\n \nstatic volatile unsigned int tc;\nstatic volatile unsigned int tc_wakeup;\n \nvoid RTC_C_IRQHandler(void)\n{\n  if (tc++ > tc_wakeup) \n  {\n    SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;    \n    NVIC_DisableIRQ(RTC_C_IRQn);\n    NVIC_ClearPendingIRQ(RTC_C_IRQn);\n    return;\n  }\n  if (RTC_C->PS0CTL & RTC_C_PS0CTL_RT0PSIFG)\n  {\n    RTC_C->CTL0 = RTC_C_KEY_VAL;                 // Unlock RTC key protected registers\n    RTC_C->PS0CTL &= ~RTC_C_PS0CTL_RT0PSIFG;\n    RTC_C->CTL0 = 0;\n    SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk);\n  }\n}\n \nuint32_t g_enable_sleep = 0;\n  \nvoid osRtxIdleThread (void) {\n  \n  for (;;) {\n    tc_wakeup = osKernelSuspend();\n    /* Is there some time to sleep? */\n    if (tc_wakeup > 0) {\n      tc = 0;\n      /* Enter the low power state */\n      MSP432_LP_Entry();\n      __WFE();\n    }\n    /* Adjust the kernel ticks with the amount of ticks slept */\n    osKernelResume (tc);\n  }\n}\n\\endcode\n\n\\note\n\\c __WFE() is not available in every Arm Cortex-M implementation. Check device manuals for availability. \nThe alternative using \\c __WFI() has other issues, please take note of https://www.keil.com/support/docs/3591.htm as well.\n\n\\section rtx_os_h RTX5 Header File\n\nEvery implementation of the CMSIS-RTOS2 API can bring its own additional features. RTX5 adds a couple of\n\\ref rtx5_specific \"functions\" for the idle more, for error notifications, and special system timer functions. It also is\nusing macros for control block and memory sizes.\n\nIf you require some of the RTX specific functions in your application code, \\#include the header file \\b %rtx_os.h:\n\n\\include rtx_os.h\n\n\n\\section CMSIS_RTOS_TimeOutValue Timeout Value   \n\nTimeout values are an argument to several \\b osXxx functions to allow time for resolving a request. A timeout value of \\b 0\nmeans that the RTOS does not wait and the function returns instantly, even when no resource is available. A timeout value of\n\\ref osWaitForever means that the RTOS waits infinitely until a resource becomes available. Or one forces the thread to resume\nusing \\ref osThreadResume which is discouraged.\n \nThe timeout value specifies the number of timer ticks until the time delay elapses. The value is an upper bound and \ndepends on the actual time elapsed since the last timer tick. \n\nExamples:\n  - timeout value \\b 0 : the system does not wait, even when no resource is available the RTOS function returns instantly. \n  - timeout value \\b 1 : the system waits until the next timer tick occurs; depending on the previous timer tick, it may be a\n    very short wait time.\n  - timeout value \\b 2 : actual wait time is between 1 and 2 timer ticks.\n  - timeout value \\ref osWaitForever : system waits infinite until a resource becomes available. \n  \n\\image html TimerValues.png \"Example of timeout using osDelay()\"\n\n\n\\section CMSIS_RTOS_ISR_Calls Calls from Interrupt Service Routines \n\nThe following CMSIS-RTOS2 functions can be called from threads and Interrupt Service Routines (ISR):\n  - \\ref osKernelGetInfo, \\ref osKernelGetState,\n    \\ref osKernelGetTickCount, \\ref osKernelGetTickFreq, \\ref osKernelGetSysTimerCount, \\ref osKernelGetSysTimerFreq\n  - \\ref osThreadGetName, \\ref osThreadGetId, \\ref osThreadFlagsSet\n  - \\ref osTimerGetName\n  - \\ref osEventFlagsGetName, \\ref osEventFlagsSet, \\ref osEventFlagsClear, \\ref osEventFlagsGet, \\ref osEventFlagsWait\n  - \\ref osMutexGetName\n  - \\ref osSemaphoreGetName, \\ref osSemaphoreAcquire, \\ref osSemaphoreRelease, \\ref osSemaphoreGetCount\n  - \\ref osMemoryPoolGetName, \\ref osMemoryPoolAlloc, \\ref osMemoryPoolFree,\n    \\ref osMemoryPoolGetCapacity, \\ref osMemoryPoolGetBlockSize, \\ref osMemoryPoolGetCount, \\ref osMemoryPoolGetSpace\n  - \\ref osMessageQueueGetName, \\ref osMessageQueuePut, \\ref osMessageQueueGet, \\ref osMessageQueueGetCapacity,\n    \\ref osMessageQueueGetMsgSize, \\ref osMessageQueueGetCount, \\ref osMessageQueueGetSpace\n\nFunctions that cannot be called from an ISR are verifying the interrupt status and return the status code \\b osErrorISR, in\ncase they are called from an ISR context. In some implementations, this condition might be caught using the HARD_FAULT\nvector.\n\n\\note\n- RTX does not disable interrupts during critical sections for Armv7-M and Armv8-M architecture based devices, but rather\n  uses atomic operations.\n- Therefore, there is no need to configure interrupt priorities of interrupt service routines that use RTOS functions.\n\n\n\\section CMSIS_RTOS_svcFunctions SVC Functions\n\nSupervisor Calls (SVC) are exceptions targeted at software and operating systems for generating system function calls. They\nare sometimes called software interrupts. For example, instead of allowing user programs to directly access hardware, an\noperating system may provide access to hardware through an SVC. So when a user program wants to use certain hardware, it\ngenerates the exception using SVC instructions. The software exception handler in the operating system executes and provides\nthe requested service to the user application. In this way, access to hardware is under the control of the OS, which can\nprovide a more robust system by preventing the user applications from directly accessing the hardware.\n\nSVCs can also make software more portable because the user application does not need to know the programming details of the\nunderlying hardware. The user program will only need to know the application programming interface (API) function ID and\nparameters; the actual hardware-level programming is handled by device drivers.\n\nSVCs run in \\b privileged \\b handler mode of the Arm Cortex-M core. SVC functions accept arguments and can return values.\nThe functions are used in the same way as other functions; however, they are executed indirectly through the SVC instruction.\nWhen executing SVC instructions, the controller changes to the privileged handler mode.\n\nInterrupts are \\b not \\b disabled in this mode. To protect SVC functions from interrupts, you need to include the\ndisable/enable intrinsic functions \\c __disable_irq() and \\c __enable_irq() in your code.\n\nYou can use SVC functions to access \\b protected \\b peripherals, for example, to configure NVIC and interrupts. \nThis is required if you run threads in unprivileged (protected) mode and you need to change interrupts from the within the\nthread.\n\nTo implement SVC functions in your Keil RTX5 project, you need to:\n-# Add the SVC User Table file \\b svc_user.c to your project folder and include it into your project. This file is available\n   as a user code template.\n-# Write a function implementation. Example:\n   \\code\n   uint32_t svc_atomic_inc32 (uint32_t *mem) {\n     // A protected function to increment a counter. \n     uint32_t val;\n      \n     __disable_irq();\n     val  = *mem;\n     (*mem) = val + 1U;\n     __enable_irq();\n      \n     return (val);\n   }\n   \\endcode\n-# Add the function to the SVC function table in the \\b svc_user.c module:\n   \\code\n   void * const osRtxUserSVC[1+USER_SVC_COUNT] = {\n     (void *)USER_SVC_COUNT,\n     (void *)svc_atomic_inc32,\n   };\n   \\endcode\n-# Increment the number of user SVC functions:\n   \\code\n   #define USER_SVC_COUNT  1       // Number of user SVC functions\n   \\endcode\n-# Declare a function wrapper to be called by the user to execute the SVC call.\\n\n   \\b Code \\b Example (Arm Compiler 6)\n   \\code\n   __STATIC_FORCEINLINE uint32_t atomic_inc32 (uint32_t *mem) {\n     register uint32_t val;\n\t  \n     __ASM volatile (\n       \"svc 1\" : \"=l\" (val) : \"l\" (mem) : \"cc\", \"memory\"\n     );\n     return (val);\n   }\n   \\endcode\n   \n   \\b Code \\b Example (Arm Compiler 5 using \\c __svc(x) attribute)\n   \\code\n   uint32_t atomic_inc32 (uint32_t *mem) __svc(1);\n   \\endcode\n    \n\\note\n- The SVC function \\token{0} is \\b reserved for the Keil RTX5 kernel.\n- Do not leave gaps when numbering SVC functions. They must occupy a \\b continuous range of numbers starting from 1.\n- SVC functions can still be interrupted.\n\n\n\\section cre_rtx_proj_clib_arm Arm C library multi-threading protection\n\n\\ifnot FuSaRTS\nRTX5 provides an interface to the\n<a href=\"https://developer.arm.com/docs/dui0475/m/the-arm-c-and-c-libraries/multithreaded-support-in-arm-c-libraries\" target=\"_blank\">\n<b>Arm C libraries</b></a> to ensure static data protection in a multi-threaded application.\n\nThe Arm C libraries use static data to store errno, floating-point status word for software floating-point operations, \na pointer to the base of the heap, and other variables. The Arm C micro-library (i.e. microlib) does not support protection\nfor multi-threaded applications. See the <a href=\"https://developer.arm.com/docs/dui0475/m/the-arm-c-micro-library/differences-between-microlib-and-the-default-c-library\" target=\"_blank\"> \n<b>limitations and differences</b></a> between microlib and the default C library.\n\nBy default, RTX5 uses the Arm C libraries multi-thread protection for:\n- all user threads if \\ref threadConfig \"Object specific Memory allocation\" is enabled.\n- the number of threads defined by <b>OS_THREAD_LIBSPACE_NUM</b> if \\ref threadConfig \"Object specific Memory allocation\" is\n  disabled. The definition <b>OS_THREAD_LIBSPACE_NUM</b> defines the number of threads that can safely call Arm C library\n  functions and can be found in \"RTX_Config.h\" file or can be defined on the global scope.\n\nThe default, Arm C libraries use mutex functions to\n<a href=\"https://developer.arm.com/docs/dui0475/m/the-arm-c-and-c-libraries/multithreaded-support-in-arm-c-libraries/management-of-locks-in-multithreaded-applications\" target=\"_blank\">\n<b>protect shared resources from concurrent access</b></a>. RTX5 implements these functions and uses resources from the\n\\ref systemConfig \"Global Dynamic Memory\" to allocate mutex objects.\n\\endif\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page config_rtx5 Configure RTX v5\n\nThe file \"RTX_Config.h\" defines the configuration parameters of CMSIS-RTOS RTX and must be part of every project that is\nusing the CMSIS-RTOS RTX kernel. The configuration options are explained in detail in the following sections:\n- \\ref systemConfig covers system-wide settings for the global memory pool, tick frequency, ISR event buffer and round-robin thread switching as well as process isolation-related features.\n- \\ref threadConfig provides several parameters to configure the \\ref CMSIS_RTOS_ThreadMgmt functions.\n- \\ref timerConfig provides several parameters to configure the \\ref CMSIS_RTOS_TimerMgmt functions.\n- \\ref eventFlagsConfig provides several parameters to configure the \\ref CMSIS_RTOS_EventFlags functions.\n- \\ref mutexConfig provides several parameters to configure the \\ref CMSIS_RTOS_MutexMgmt functions.\n- \\ref semaphoreConfig provides several parameters to configure the \\ref CMSIS_RTOS_SemaphoreMgmt functions.\n- \\ref memPoolConfig provides several parameters to configure the \\ref CMSIS_RTOS_PoolMgmt functions.\n- \\ref msgQueueConfig provides several parameters to configure the \\ref CMSIS_RTOS_Message functions.\n- \\ref evtrecConfig provides several parameters to configure RTX for usage with <a href=\"https://www.keil.com/pack/doc/compiler/EventRecorder/html/index.html\" target=\"_blank\"><b>Event Recorder</b></a>.\n\nThe file \"RTX_Config.c\" contains default implementations of the functions \\ref osRtxIdleThread and \\ref osRtxErrorNotify. Both functions\ncan simply be overwritten with a customized behavior by redefining them as part of the user code.\n\nThe configuration file uses <b>Configuration Wizard Annotations</b>. Refer to <b>Pack - Configuration Wizard Annotations</b> for details.\nDepending on the development tool, the annotations might lead to a more user-friendly graphical representation of the\nsettings. The picture below shows the µVision \\b Configuration \\b Wizard view in MDK:\n\n\\image html config_wizard.png \"RTX_Config.h in Configuration Wizard View\"\n\nAlternatively one can provide configuration options using the compiler command line.\n\nFor example one can customize the used tick frequency to 100us by (overwriting) the configuration using\n\\code\ncc -DOS_TICK_FREQ=100\n\\endcode\n\n\\section systemConfig System Configuration\n\nThe system configuration covers system-wide settings for the global memory pool, tick frequency, ISR event buffer and\nround-robin thread switching.\n\n<b>System Configuration Options</b>\n\\image html config_wizard_system.png \"RTX_Config.h: System Configuration\"\n\nName                                        | \\#define                 | Description\n--------------------------------------------|--------------------------|----------------------------------------------------------------\n\\ref systemConfig_glob_mem                  | \\c OS_DYNAMIC_MEM_SIZE   | Defines the combined global dynamic memory size for the \\ref GlobalMemoryPool. Default value is \\token{32768}. Value range is \\token{[0-1073741824]} bytes, in multiples of \\token{8} bytes.\nKernel Tick Frequency (Hz)                  | \\c OS_TICK_FREQ          | Defines base time unit for delays and timeouts in Hz. Default value is \\token{1000} (1000 Hz = 1 ms period).\n\\ref systemConfig_rr                        | \\c OS_ROBIN_ENABLE       | Enables Round-Robin Thread switching. Default value is \\token{1} (enabled).\n&nbsp;&nbsp;&nbsp;Round-Robin Timeout       | \\c OS_ROBIN_TIMEOUT      | Defines how long a thread will execute before a thread switch. Default value is \\token{5}. Value range is \\token{[1-1000]}.\n\\ref safetyConfig_safety                    | \\c OS_SAFETY_FEATURES    | Enables safety-related features as configured in this group. Default value is \\token{1} (enabled).\n&nbsp;&nbsp;&nbsp;Safety class              | \\c OS_SAFETY_CLASS       | Enables \\ref rtos_process_isolation_safety_class functionality. Default value is \\token{1} (enabled).\n&nbsp;&nbsp;&nbsp;MPU Protected Zone        | \\c OS_EXECUTION_ZONE     | Enables \\ref rtos_process_isolation_mpu. Default value is \\token{1} (enabled).\n&nbsp;&nbsp;&nbsp;Thread Watchdog           | \\c OS_THREAD_WATCHDOG    | Enables \\ref rtos_process_isolation_thread_wdt functionality. Default value is \\token{1} (enabled).\n&nbsp;&nbsp;&nbsp;Object Pointer checking   | \\c OS_OBJ_PTR_CHECK | Enables verification of object pointer alignment and memory region. Default value is \\token{0} (disabled).\n&nbsp;&nbsp;&nbsp;SVC Function Pointer checking | \\c OS_SVC_PTR_CHECK | Enables verification of SVC function pointer alignment and memory region. Default value is \\token{0} (disabled).\n\\ref systemConfig_isr_fifo                  | \\c OS_ISR_FIFO_QUEUE     | RTOS Functions called from ISR store requests to this buffer. Default value is \\token{16 entries}. Value range is \\token{[4-256]} entries in multiples of \\token{4}.\n\\ref systemConfig_usage_counters            | \\c OS_OBJ_MEM_USAGE      | Enables object memory usage counters to evaluate the maximum memory pool requirements individually for each RTOS object type. Default value is \\token{0} (disabled).\n\n\\subsection systemConfig_glob_mem Global Dynamic Memory size [bytes]\nRefer to \\ref GlobalMemoryPool.\n\n\n\\subsection systemConfig_rr Round-Robin Thread Switching\n\nRTX5 may be configured to use round-robin multitasking thread switching. Round-robin allows quasi-parallel execution of\nseveral threads of the \\a same priority. Threads are not really executed concurrently, but are scheduled where the available\nCPU time is divided into time slices and RTX5 assigns a time slice to each thread. Because the time slice is typically short\n(only a few milliseconds), it appears as though threads execute simultaneously.\n\nRound-robin thread switching functions as follows:\n- the tick is preloaded with the timeout value when a thread switch occurs\n- the tick is decremented (if not already zero) each system tick if the same thread is still executing\n- when the tick reaches 0 it indicates that a timeout has occurred. If there is another thread ready with the \\a same\n  priority, then the system switches to that thread and the tick is preloaded with timeout again.\n\nIn other words, threads execute for the duration of their time slice (unless a thread's time slice is given up). Then, RTX\nswitches to the next thread that is in \\b READY state and has the same priority. If no other thread with the same priority is\nready to run, the current running thread resumes it execution.\n\nRound-Robin multitasking is controlled with the <b>\\#define OS_ROBIN_ENABLE</b>. The time slice period is configured (in RTX\ntimer ticks) with the <b>\\#define OS_ROBIN_TIMEOUT</b>.\n\n\\subsection safetyConfig_safety Safety features (Source variant only)\n\nSafety features group in \\ref systemConfig enables individual selection of safety-related functionalities.\nIt requires that RTX is used in the source variant.\n\nIt also includes:\n- Thread functions: \\ref osThreadProtectPrivileged\n\n<b>MPU Protected Zone</b><br>\nEnables \\ref rtos_process_isolation_mpu functionality in the system. This includes:\n- Thread attributes: \\ref osThreadZone\n- Thread functions: \\ref osThreadGetZone, \\ref osThreadTerminateZone\n- Zone Management: \\ref osZoneSetup_Callback\n\nWhen enabled, the MPU Protected Zone values also need to be specified for the threads created by the kernel:\n- For Idle thread in \\ref threadConfig\n- For Timer thread in \\ref timerConfig\n\n<b>Safety class</b><br>\nEnables \\ref rtos_process_isolation_safety_class functionality in the system RTOS. This includes:\n- Object attributes: \\ref osSafetyClass\n- Kernel functions: \\ref osKernelProtect, \\ref osKernelDestroyClass\n- Thread functions: \\ref osThreadGetClass, \\ref osThreadSuspendClass, \\ref osThreadResumeClass\n\nWhen enabled, the safety class values need to be specified for threads created  by the kernel:\n- For Idle thread in \\ref threadConfig\n- For Timer thread in \\ref timerConfig\n\n<b>Thread Watchdog</b><br>\nEnables \\ref rtos_process_isolation_thread_wdt functionality in the system RTOS. This includes:\n- Thread functions: \\ref osThreadFeedWatchdog\n- Handler functions: \\ref osWatchdogAlarm_Handler\n\n<b>Object Pointer checking</b><br>\nEnables verification of object pointer alignment and memory region.\n\nBefore accessing RTX objects the RTX kernel verifies that obtained object pointer is valid (at least not \\token{NULL}). When <i>Object Pointer checking</i> is enabled the kernel will additionally verify that\nthe control block of the object is located in the memory section allocated for such object type, and that it is correctly aligned within that memory section.\n\nIf static memory allocation is used, the user shall place the control blocks of the objects into the correct named memory sections as described in \\ref StaticObjectMemory.\nFor object-specific and dynamic memory allocations the kernel will place the objects correctly.\n\n<b>SVC Function Pointer checking</b><br>\nEnables verification of SVC function pointer alignment and memory region.\n\nMany kernel functions are executed in SVC context. Corresponding function pointers are placed by the kernel into a special named memory section. If <i>SVC Function Pointer checking</i> is enabled the kernel before calling an SVC function will additionally verify that its pointer is located in the expected memory section and is correctly aligned within that memory region.\n\n\\subsection systemConfig_isr_fifo ISR FIFO Queue\nThe RTX functions (\\ref CMSIS_RTOS_ISR_Calls), when called from and interrupt handler, store the request type and optional\nparameter to the ISR FIFO queue buffer to be processed later, after the interrupt handler exits.\n\nThe scheduler is activated immediately after the IRQ handler has finished its execution to process the requests stored to the\nFIFO queue buffer. The required size of this buffer depends on the number of functions that are called within the interrupt\nhandler. An insufficient queue size will be caught by \\b osRtxErrorNotify with error code \\b osRtxErrorISRQueueOverflow.\n\n\n\\subsection systemConfig_usage_counters Object Memory Usage Counters\n\nObject memory usage counters help to evaluate the maximum memory pool requirements for each object type, just like stack\nwatermarking does for threads. The initial setup starts with a global memory pool for all object types. Consecutive runs of\nthe application with object memory usage counters enabled, help to introduce object specific memory pools for each object\ntype. Normally, this is required for applications that require a functional safety certification as global memory pools are\nnot allowed in this case.\n\n\n\\section threadConfig Thread Configuration\n\nThe RTX5 provides several parameters to configure the \\ref CMSIS_RTOS_ThreadMgmt functions.\n\n<b>Thread Configuration Options</b>\n\\image html config_wizard_threads.png \"RTX_Config.h: Thread Configuration\"\n\n<br> \nOption                                                   | \\#define               | Description\n:--------------------------------------------------------------------------|:-------------------------------|:---------------------------------------------------------------\nObject specific Memory allocation                        | \\c OS_THREAD_OBJ_MEM   | Enables object specific memory allocation. See \\ref ObjectMemoryPool.\nNumber of user Threads                                   | \\c OS_THREAD_NUM       | Defines maximum number of user threads that can be active at the same time. Applies to user threads with system provided memory for control blocks. Default value is \\token{1}. Value range is \\token{[1-1000]}.\nNumber of user Threads with default Stack size  | \\c OS_THREAD_DEF_STACK_NUM     | Defines maximum number of user threads with default stack size and applies to user threads with \\token{0} stack size specified. Value range is \\token{[0-1000]}.\nTotal Stack size [bytes] for user Threads with user-provided Stack size    | \\c OS_THREAD_USER_STACK_SIZE | Defines the combined stack size for user threads with user-provided stack size. Default value is \\token{0}. Value range is \\token{[0-1073741824]} Bytes, in multiples of \\token{8}. \nDefault Thread Stack size [bytes]                        | \\c OS_STACK_SIZE    | Defines stack size for threads with zero stack size specified. Default value is \\token{3072}. Value range is \\token{[96-1073741824]} Bytes, in multiples of \\token{8}. \nIdle Thread Stack size [bytes]                           | \\c OS_IDLE_THREAD_STACK_SIZE              | Defines stack size for Idle thread. Default value is \\token{512}. Value range is \\token{[72-1073741824]} bytes, in multiples of \\token{8}. \nIdle Thread TrustZone Module ID                          | \\c OS_IDLE_THREAD_TZ_MOD_ID    | Defines the \\ref osThreadAttr_t::tz_module \"TrustZone Module ID\" the Idle Thread shall use. This needs to be set to a non-zero value if the Idle Thread need to call secure functions. Default value is \\token{0}.\nIdle Thread Safety Class                                 | \\c OS_IDLE_THREAD_CLASS        | Defines the the \\ref rtos_process_isolation_safety_class \"Safety Class\" for the Idle thread. Applied only if Safety Class functionality is enabled in \\ref systemConfig. Default value is \\token{0}.\nIdle Thread Zone                                         | \\c OS_IDLE_THREAD_ZONE         | Defines the \\ref rtos_process_isolation_mpu \"MPU Protected Zone\" for the Idle thread. Applied only if MPU protected Zone functionality is enabled in \\ref systemConfig. Default value is \\token{0}.\nStack overrun checking                                   | \\c OS_STACK_CHECK   | Enable stack overrun checks at thread switch. \nStack usage watermark                                    | \\c OS_STACK_WATERMARK    | Initialize thread stack with watermark pattern for analyzing stack usage. Enabling this option increases significantly the execution time of thread creation.\nProcessor mode for Thread execution                      | \\c OS_PRIVILEGE_MODE     | Controls the default processor mode when not specified through thread attributes \\ref osThreadUnprivileged or \\ref osThreadPrivileged. Default value is \\token{Unprivileged} mode. Value range is \\token{[0=Unprivileged; 1=Privileged]} mode.\n\n\\subsection threadConfig_countstack Configuration of Thread Count and Stack Space\n\nThe RTX5 kernel uses a separate stack space for each thread and provides two methods for defining the stack requirements:\n - <b>Static allocation</b>: when \\ref osThreadAttr_t::stack_mem and \\ref osThreadAttr_t::stack_size specify a memory area\n   which is used for the thread stack. \\b Attention: The stack memory provided must be 64-bit aligned, i.e. by using uint64_t for declaration.\n - <b>Dynamic allocation</b>: when \\ref osThreadAttr_t is NULL or \\ref osThreadAttr_t::stack_mem is NULL, the system\n   allocates the stack memory from:\n     - Object-specific Memory Pool (default Stack size) when \"Object specific Memory allocation\" is enabled and \"Number of\n       user Threads with default Stack size\" is not \\token{0} and \\ref osThreadAttr_t::stack_size is \\token{0} (or\n       \\ref osThreadAttr_t is NULL).\n     - Object-specific Memory Pool (user-provided Stack size) when \"Object specific Memory allocation\" is enabled and \"Total\n       Stack size for user...\"  is not \\token{0} and \\ref osThreadAttr_t::stack_size is not \\token{0}.\n     - Global Memory Pool when \"Object specific Memory allocation\" is disabled or (\\ref osThreadAttr_t::stack_size is not\n       \\token{0} and \"Total Stack size for user...\" is \\token{0}) or (\\ref osThreadAttr_t::stack_size is \\token{0} and\n       \"Number of user Threads with default Stack size\" is \\token{0}).\n\n\\ref osThreadAttr_t is a parameter of the function \\ref osThreadNew.\n\n\\note\nBefore the RTX kernel is started by the \\ref osKernelStart() function, the main stack defined in startup_<i>device</i>.s is\nused. The main stack is also used for:\n - user application calls to RTX functions in \\b thread \\b mode using SVC calls\n - interrupt/exception handlers.\n \n\\subsection threadConfig_ovfcheck Stack Overflow Checking\nRTX5 implements a software stack overflow checking that traps stack overruns. Stack is used for return addresses and\nautomatic variables. Extensive usage or incorrect stack configuration may cause a stack overflow. Software stack overflow\nchecking is controlled with the define \\c OS_STACK_CHECK.\n \nIf a stack overflow is detected, the function \\ref osRtxErrorNotify with error code \\ref osRtxErrorStackOverflow is called. By\ndefault, this function is implemented as an endless loop and will practically stop code execution.\n\n\\subsection threadConfig_watermark Stack Usage Watermark\nRTX5 initializes thread stack with a watermark pattern (0xCC) when a thread is created. This allows the debugger to determine\nthe maximum stack usage for each thread. It is typically used during development but removed from the final application.\nStack usage watermark is controlled with the define \\c OS_STACK_WATERMARK.\n  \nEnabling this option significantly increases the execution time of \\ref osThreadNew (depends on thread stack size).\n \n\\subsection threadConfig_procmode Processor Mode for Thread Execution\nRTX5 allows to execute threads in unprivileged or privileged processor mode. The processor mode is configured for all threads with the\ndefine \\c OS_PRIVILEGE_MODE.\n\nIt is also possible to specify the privilege level for individual threads. For that use \\ref osThreadUnprivileged and \\ref osThreadPrivileged defines in the \\e attr_bits of \\ref osThreadAttr_t argument when creating a thread with \\ref osThreadNew.\n \nIn \\b unprivileged processor mode, the application software:\n- has limited access to the MSR and MRS instructions, and cannot use the CPS instruction.\n- cannot access the system timer, NVIC, or system control block.\n- might have restricted access to memory or peripherals.\n\nIn \\b privileged processor mode, the application software can use all the instructions and has access to all resources.\n\n\n\\section timerConfig Timer Configuration\n\nRTX5 provides several parameters to configure the \\ref CMSIS_RTOS_TimerMgmt functions.\n\n<b>Timer Configuration Options</b>\n\\image html config_wizard_timer.png \"RTX_Config.h: Timer Configuration\"\n\nName                                   | \\#define                 | Description\n---------------------------------------|--------------------------------|----------------------------------------------------------------\nObject specific Memory allocation      | \\c OS_TIMER_OBJ_MEM      | Enables object specific memory allocation. \nNumber of Timer objects                | \\c OS_TIMER_NUM          | Defines maximum number of objects that can be active at the same time. Applies to objects with system provided memory for control blocks. Value range is \\token{[1-1000]}.\nTimer Thread Priority                  | \\c OS_TIMER_THREAD_PRIO        | Defines priority for timer thread. Default value is \\token{40}. Value range is \\token{[8-48]}, in multiples of \\token{8}. The numbers have the following priority correlation: \\token{8=Low}; \\token{16=Below Normal}; \\token{24=Normal}; \\token{32=Above Normal}; \\token{40=High}; \\token{48=Realtime} \nTimer Thread Stack size [bytes]        | \\c OS_TIMER_THREAD_STACK_SIZE  | Defines stack size for Timer thread. May be set to 0 when timers are not used. Default value is \\token{512}. Value range is \\token{[0-1073741824]}, in multiples of \\token{8}.\nTimer Thread TrustZone Module ID       | \\c OS_TIMER_THREAD_TZ_MOD_ID   | Defines the \\ref osThreadAttr_t::tz_module \"TrustZone Module ID\" the Timer Thread shall use. This needs to be set to a non-zero value if any Timer Callbacks need to call secure functions. Default value is \\token{0}.\nTimer Thread Safety Class              | \\c OS_TIMER_THREAD_CLASS        | Defines the the \\ref rtos_process_isolation_safety_class \"Safety Class\" for the Timer thread. Applied only if Safety class functionality is enabled in \\ref systemConfig. Default value is \\token{0}.\nTimer Thread Zone                      | \\c OS_TIMER_THREAD_ZONE         | Defines the \\ref rtos_process_isolation_mpu \"MPU Protected Zone\" for the Timer thread. Applied only if MPU protected Zone functionality is enabled in \\ref systemConfig. Default value is \\token{0}.\nTimer Callback Queue entries           | \\c OS_TIMER_CB_QUEUE           | Number of concurrent active timer callback functions. May be set to 0 when timers are not used. Default value is \\token{4}. Value range is \\token{[0-256]}.\n\n\\subsection timerConfig_obj Object-specific memory allocation\nSee \\ref ObjectMemoryPool.\n\n\\subsection timerConfig_user User Timer Thread\nThe RTX5 function \\b osRtxTimerThread executes callback functions when a time period expires. The priority of the timer\nsubsystem within the complete RTOS system is inherited from the priority of the \\b osRtxTimerThread. This is configured by\n\\c OS_TIMER_THREAD_PRIO. Stack for callback functions is supplied by \\b osRtxTimerThread. \\c OS_TIMER_THREAD_STACK_SIZE must\nsatisfy the stack requirements of the callback function with the highest stack usage. \n\n\n\\section eventFlagsConfig Event Flags Configuration\n\nRTX5 provides several parameters to configure the \\ref CMSIS_RTOS_EventFlags functions.\n\n<b>Event Configuration Options</b>\n\\image html config_wizard_eventFlags.png \"RTX_Config.h: Event Flags Configuration\"\n\nName                                   | \\#define                 | Description\n---------------------------------------|--------------------------|----------------------------------------------------------------\nObject specific Memory allocation      | \\c OS_EVFLAGS_OBJ_MEM    | Enables object specific memory allocation. See \\ref ObjectMemoryPool.\nNumber of Event Flags objects          | \\c OS_EVFLAGS_NUM        | Defines maximum number of objects that can be active at the same time. Applies to objects with system provided memory for control blocks. Value range is \\token{[1-1000]}.\n\n\\subsection eventFlagsConfig_obj Object-specific memory allocation\nWhen object-specific memory is used, the pool size for all Event objects is specified by \\c OS_EVFLAGS_NUM. Refer to\n\\ref ObjectMemoryPool.\n\n\n\\section mutexConfig Mutex Configuration\nRTX5 provides several parameters to configure the \\ref CMSIS_RTOS_MutexMgmt functions.\n\n<b>Mutex Configuration Options</b>\n\\image html config_wizard_mutex.png \"RTX_Config.h: Mutex Configuration\"\n\n\nName                                   | \\#define                 | Description\n---------------------------------------|--------------------------|----------------------------------------------------------------\nObject specific Memory allocation      | \\c OS_MUTEX_OBJ_MEM      | Enables object specific memory allocation. See \\ref ObjectMemoryPool.\nNumber of Mutex objects                | \\c OS_MUTEX_NUM          | Defines maximum number of objects that can be active at the same time. Applies to objects with system provided memory for control blocks. Value range is \\token{[1-1000]}.\n\n\\subsection mutexConfig_obj Object-specific Memory Allocation\nWhen object-specific memory is used, the pool size for all Mutex objects is specified by \\c OS_MUTEX_NUM. Refer to\n\\ref ObjectMemoryPool.\n\n\n\\section semaphoreConfig Semaphore Configuration\n\nRTX5 provides several parameters to configure the \\ref CMSIS_RTOS_SemaphoreMgmt functions.\n\n<b>Semaphore Configuration Options</b>\n\\image html config_wizard_semaphore.png \"RTX_Config.h: Semaphore Configuration\"\n\n\nName                                   | \\#define                 | Description\n---------------------------------------|--------------------------|----------------------------------------------------------------\nObject specific Memory allocation      | \\c OS_SEMAPHORE_OBJ_MEM  | Enables object specific memory allocation. See \\ref ObjectMemoryPool.\nNumber of Semaphore objects            | \\c OS_SEMAPHORE_NUM      | Defines maximum number of objects that can be active at the same time. Applies to objects with system provided memory for control blocks. Value range is \\token{[1-1000]}.\n\n\\subsection semaphoreConfig_obj Object-specific memory allocation\nWhen Object-specific Memory is used, the pool size for all Semaphore objects is specified by \\c OS_SEMAPHORE_NUM. Refer to\n\\ref ObjectMemoryPool.\n\n\n\\section memPoolConfig Memory Pool Configuration\n\nRTX5 provides several parameters to configure the \\ref CMSIS_RTOS_PoolMgmt functions.\n\n<b>Memory Pool Configuration Options</b>\n\\image html config_wizard_memPool.png \"RTX_Config.h: Memory Pool Configuration\"\n\nName                                   | \\#define                 | Description\n---------------------------------------|--------------------------|----------------------------------------------------------------\nObject specific Memory allocation      | \\c OS_MEMPOOL_OBJ_MEM    | Enables object specific memory allocation. See \\ref ObjectMemoryPool.\nNumber of Memory Pool objects          | \\c OS_MEMPOOL_NUM        | Defines maximum number of objects that can be active at the same time. Applies to objects with system provided memory for control blocks. Value range is \\token{[1-1000]}.\nData Storage Memory size [bytes]       | \\c OS_MEMPOOL_DATA_SIZE  | Defines the combined data storage memory size. Applies to objects with system provided memory for data storage. Default value is \\token{0}. Value range is \\token{[0-1073741824]}, in multiples of \\token{8}.\n\n\\subsection memPoolConfig_obj Object-specific memory allocation\nWhen object-specific memory is used, the number of pools for all MemoryPool objects is specified by \\c OS_MEMPOOL_NUM. The\ntotal storage size reserved for all pools is configured in \\c OS_MEMPOOL_DATA_SIZE. Refer to \\ref ObjectMemoryPool.\n\n\n\\section msgQueueConfig Message Queue Configuration\n\nRTX5 provides several parameters to configure the \\ref CMSIS_RTOS_Message functions.\n\n<b>MessageQueue Configuration Options</b>\n\\image html config_wizard_msgQueue.png \"RTX_Config.h: Message Queue Configuration\"\n\nName                                   | \\#define                 | Description\n---------------------------------------|--------------------------|----------------------------------------------------------------\nObject specific Memory allocation      | \\c OS_MSGQUEUE_OBJ_MEM   | Enables object specific memory allocation. See \\ref ObjectMemoryPool.\nNumber of Message Queue objects        | \\c OS_MSGQUEUE_NUM       | Defines maximum number of objects that can be active at the same time. Applies to objects with system provided memory for control blocks. Value range is \\token{[1-1000]}.\nData Storage Memory size [bytes]       | \\c OS_MSGQUEUE_DATA_SIZE | Defines the combined data storage memory size. Applies to objects with system provided memory for data storage. Default value is \\token{0}. Value range is \\token{[0-1073741824]}, in multiples of \\token{8}.\n\n\\subsection msgQueueConfig_obj Object-specific memory allocation\nWhen Object-specific Memory is used, the number of queues for all Message Queue objects is specified by \\c OS_MSGQUEUE_NUM.\nThe total storage size reserved for all queues is configured in \\c OS_MSGQUEUE_DATA_SIZE. Refer to \\ref ObjectMemoryPool.\n\n\n\\section evtrecConfig Event Recorder Configuration\n\nThis section describes the configuration settings for the <a href=\"https://www.keil.com/pack/doc/compiler/EventRecorder/html/index.html\" target=\"_blank\">Event Recorder</a>\nannotations. The usage requires the source variant of RTX5; refer to \\ref cre_rtx_proj_er for more information.\n\n\\subsection evtrecConfigGlobIni Global Configuration\nInitialize Event Recorder during the \\ref osKernelInitialize and optionally start event recording.\n\n\\image html config_wizard_evtrecGlobIni.png \"RTX_Config.h: Global Configuration\"\n\n<br/>\n\nName                  | \\#define        | Description\n----------------------|-----------------|----------------------------------------------------------------\nGlobal Initialization | \\c OS_EVR_INIT  | Initialize Event Recorder during \\ref osKernelInitialize.\nStart Recording       | \\c OS_EVR_START | Start event recording after initialization.\n\n\\note\n- If <b>Global Initialization (\\c OS_EVR_INIT)</b> is set, an explicit call to \\c EventRecorderInitialize is not required.\n- If <b>Start Recording (\\c OS_EVR_START)</b> is set, an explicit call to \\c EventRecorderStart is not required. You may call the function \\c EventRecorderStop to stop recording.\n\n\n<b>Global Event Filter Setup</b>\n\nThese event filter settings are applied to all software component numbers, including MDK middleware and user components.\n\n\\image html config_wizard_evtrecGlobEvtFiltSetup.png \"RTX_Config.h: Global Event Filter Setup\"\n\n<br/>\n\nName                      | \\#define         | Description\n--------------------------|------------------|----------------------------------------------------------------\nError events              | \\c OS_EVR_LEVEL  | Enable error events.\nAPI function call events  | \\c OS_EVR_LEVEL  | Enable API function call events.\nOperation events          | \\c OS_EVR_LEVEL  | Enable operation events.\nDetailed operation events | \\c OS_EVR_LEVEL  | Enable detailed operation events.\n\n\\note\nYou may disable event recording for specific software components by calling the function \\c EventRecorderDisable.\n\n<b>RTOS Event Filter Setup</b>\n\nThese event filter settings are applied to specific RTX component groups with sub-options for:\n- Error events\n- API function call events\n- Operation events\n- Detailed operation events\n\nThe generation of events must be enabled as explained under \\ref evtrecConfigEvtGen.\n\n\n\\image html config_wizard_evtrecRTOSEvtFilterSetup.png \"RTX_Config.h: RTOS Event Filter Setup\"\n\n<br/>\n\nName              | \\#define                   | Description\n------------------|----------------------------|----------------------------------------------------------------\nMemory Management | \\c OS_EVR_MEMORY_LEVEL     | Recording level for Memory Management events.\nKernel            | \\c OS_EVR_KERNEL_LEVEL     | Recording level for Kernel events.\nThread            | \\c OS_EVR_THREAD_LEVEL     | Recording level for Thread events.\nGeneric Wait      | \\c OS_EVR_WAIT_LEVEL       | Recording level for Generic Wait events.\nThread Flags      | \\c OS_EVR_THFLAGS_LEVEL    | Recording level for Thread Flags events.\nEvent Flags       | \\c OS_EVR_EVFLAGS_LEVEL    | Recording level for Event Flags events.\nTimer             | \\c OS_EVR_TIMER_LEVEL      | Recording level for Timer events.\nMutex             | \\c OS_EVR_MUTEX_LEVEL      | Recording level for Mutex events.\nSemaphore         | \\c OS_EVR_SEMAPHORE_LEVEL  | Recording level for Semaphore events.\nMemory Pool       | \\c OS_EVR_MEMPOOL_LEVEL    | Recording level for Memory Pool events.\nMessage Queue     | \\c OS_EVR_MSGQUEUE_LEVEL   | Recording level for Message Queue events.\n \n\n\\subsection evtrecConfigEvtGen RTOS Event Generation\n\nEnable the event generation for specific RTX component groups. This requires the RTX source variant (refer to \\ref cre_rtx_proj_er for more information).\n\n\\image html config_wizard_evtrecGeneration.png \"RTX_Config.h: Event generation configuration\"\n\n<br/>\n\nName              | \\#define                 | Description\n------------------|--------------------------|----------------------------------------------------------------\nMemory Management | \\c OS_EVR_MEMORY         | Enables Memory Management events generation.\nKernel            | \\c OS_EVR_KERNEL         | Enables Kernel events generation.\nThread            | \\c OS_EVR_THREAD         | Enables Thread events generation.\nGeneric Wait      | \\c OS_EVR_WAIT           | Enables Generic Wait events generation.\nThread Flags      | \\c OS_EVR_THFLAGS        | Enables Thread Flags events generation.\nEvent Flags       | \\c OS_EVR_EVFLAGS        | Enables Event Flags events generation.\nTimer             | \\c OS_EVR_TIMER          | Enables Timer events generation.\nMutex             | \\c OS_EVR_MUTEX          | Enables Mutex events generation.\nSemaphore         | \\c OS_EVR_SEMAPHORE      | Enables Semaphore events generation.\nMemory Pool       | \\c OS_EVR_MEMPOOL        | Enables Memory Pool events generation.\nMessage Queue     | \\c OS_EVR_MSGQUEUE       | Enables Message Queue events generation.\n\n\\note\nIf event generation for a component is disabled, the code that generates the related events is not included. Thus, \\ref evtrecConfigGlobIni \"filters\" for this\ncomponent will have no effect and the debugger is unable to display any events for the related component group.\n\n\n\\subsection systemConfig_event_recording Manual event configuration\n\nTo disable the generation of events for a specific RTX API call, use the following \\#define settings (from <b>rtx_evr.h</b>) and add these manually \nto the <b>RTX_Config.h</b> file:\n\n\\b Memory \\b events \\n\n\\c EVR_RTX_MEMORY_INIT_DISABLE, \\c EVR_RTX_MEMORY_ALLOC_DISABLE, \\c EVR_RTX_MEMORY_FREE_DISABLE,\n\\c EVR_RTX_MEMORY_BLOCK_INIT_DISABLE, \\c EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE, \\c EVR_RTX_MEMORY_BLOCK_FREE_DISABLE\n\n\\b Kernel \\b events \\n\n\\c EVR_RTX_KERNEL_ERROR_DISABLE, \\c EVR_RTX_KERNEL_INITIALIZE_DISABLE, \\c EVR_RTX_KERNEL_INITIALIZED_DISABLE,\n\\c EVR_RTX_KERNEL_GET_INFO_DISABLE, \\c EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE, \\c EVR_RTX_KERNEL_GET_STATE_DISABLE,\n\\c EVR_RTX_KERNEL_START_DISABLE, \\c EVR_RTX_KERNEL_STARTED_DISABLE, \\c EVR_RTX_KERNEL_LOCK_DISABLE,\n\\c EVR_RTX_KERNEL_LOCKED_DISABLE, \\c EVR_RTX_KERNEL_UNLOCK_DISABLE, \\c EVR_RTX_KERNEL_UNLOCKED_DISABLE,\n\\c EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE, \\c EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE, \\c EVR_RTX_KERNEL_SUSPEND_DISABLE,\n\\c EVR_RTX_KERNEL_SUSPENDED_DISABLE, \\c EVR_RTX_KERNEL_RESUME_DISABLE, \\c EVR_RTX_KERNEL_RESUMED_DISABLE,\n\\c EVR_RTX_KERNEL_PROTECT_DISABLE, \\c EVR_RTX_KERNEL_PROTECTED_DISABLE,\n\\c EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE, \\c EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE,\n\\c EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE, \\c EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE,\n\\c EVR_RTX_KERNEL_DESTROY_CLASS_DISABLE, \\c EVR_RTX_KERNEL_ERROR_NOTIFY_DISABLE\n\n\\b Thread \\b events \\n\n\\c EVR_RTX_THREAD_ERROR_DISABLE, \\c EVR_RTX_THREAD_NEW_DISABLE, \\c EVR_RTX_THREAD_CREATED_DISABLE,\n\\c EVR_RTX_THREAD_GET_NAME_DISABLE, \\c EVR_RTX_THREAD_GET_ID_DISABLE, \\c EVR_RTX_THREAD_GET_STATE_DISABLE,\n\\c EVR_RTX_THREAD_GET_CLASS_DISABLE, \\c EVR_RTX_THREAD_GET_ZONE_DISABLE,\n\\c EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE, \\c EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE, \\c EVR_RTX_THREAD_SET_PRIORITY_DISABLE,\n\\c EVR_RTX_THREAD_PRIORITY_UPDATED_DISABLE, \\c EVR_RTX_THREAD_GET_PRIORITY_DISABLE, \\c EVR_RTX_THREAD_YIELD_DISABLE,\n\\c EVR_RTX_THREAD_SUSPEND_DISABLE, \\c EVR_RTX_THREAD_SUSPENDED_DISABLE, \\c EVR_RTX_THREAD_RESUME_DISABLE,\n\\c EVR_RTX_THREAD_RESUMED_DISABLE, \\c EVR_RTX_THREAD_DETACH_DISABLE, \\c EVR_RTX_THREAD_DETACHED_DISABLE,\n\\c EVR_RTX_THREAD_JOIN_DISABLE, \\c EVR_RTX_THREAD_JOIN_PENDING_DISABLE, \\c EVR_RTX_THREAD_JOINED_DISABLE,\n\\c EVR_RTX_THREAD_BLOCKED_DISABLE, \\c EVR_RTX_THREAD_UNBLOCKED_DISABLE, \\c EVR_RTX_THREAD_PREEMPTED_DISABLE,\n\\c EVR_RTX_THREAD_SWITCHED_DISABLE, \\c EVR_RTX_THREAD_EXIT_DISABLE, \\c EVR_RTX_THREAD_TERMINATE_DISABLE,\n\\c EVR_RTX_THREAD_DESTROYED_DISABLE, \\c EVR_RTX_THREAD_GET_COUNT_DISABLE, \\c EVR_RTX_THREAD_ENUMERATE_DISABLE,\n\\c EVR_RTX_THREAD_FEED_WATCHDOG_DISABLE, \\c EVR_RTX_THREAD_FEED_WATCHDOG_DONE_DISABLE, \\c EVR_RTX_THREAD_WATCHDOG_EXPIRED_DISABLE,\n\\c EVR_RTX_THREAD_PROTECT_PRIVILEGED_DISABLE, \\c EVR_RTX_THREAD_PRIVILEGED_PROTECTED_DISABLE,\n\\c EVR_RTX_THREAD_SUSPEND_CLASS_DISABLE, \\c EVR_RTX_THREAD_RESUME_CLASS_DISABLE, \\c EVR_RTX_THREAD_TERMINATE_ZONE_DISABLE\n\n\\b Generic \\b wait \\b events \\n\n\\c EVR_RTX_DELAY_ERROR_DISABLE, \\c EVR_RTX_DELAY_DISABLE, \\c EVR_RTX_DELAY_UNTIL_DISABLE,\n\\c EVR_RTX_DELAY_STARTED_DISABLE, \\c EVR_RTX_DELAY_UNTIL_STARTED_DISABLE, \\c EVR_RTX_DELAY_COMPLETED_DISABLE \n\n\\b Thread \\b flag \\b events \\n\n\\c EVR_RTX_THREAD_FLAGS_ERROR_DISABLE, \\c EVR_RTX_THREAD_FLAGS_SET_DISABLE, \\c EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE,\n\\c EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE, \\c EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE, \\c EVR_RTX_THREAD_FLAGS_GET_DISABLE,\n\\c EVR_RTX_THREAD_FLAGS_WAIT_DISABLE, \\c EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE, \\c EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE,\n\\c EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE, \\c EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE\n\n\\b Event \\b flag \\b events \\n\n\\c EVR_RTX_EVENT_FLAGS_ERROR_DISABLE, \\c EVR_RTX_EVENT_FLAGS_NEW_DISABLE, \\c EVR_RTX_EVENT_FLAGS_CREATED_DISABLE,\n\\c EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE, \\c EVR_RTX_EVENT_FLAGS_SET_DISABLE, \\c EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE,\n\\c EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE, \\c EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE, \\c EVR_RTX_EVENT_FLAGS_GET_DISABLE,\n\\c EVR_RTX_EVENT_FLAGS_WAIT_DISABLE, \\c EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE,\n\\c EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE, \\c EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE,\n\\c EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE, \\c EVR_RTX_EVENT_FLAGS_DELETE_DISABLE,\n\\c EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE\n\n\\b Timer \\b events \\n\n\\c EVR_RTX_TIMER_ERROR_DISABLE, \\c EVR_RTX_TIMER_CALLBACK_DISABLE, \\c EVR_RTX_TIMER_NEW_DISABLE,\n\\c EVR_RTX_TIMER_CREATED_DISABLE, \\c EVR_RTX_TIMER_GET_NAME_DISABLE, \\c EVR_RTX_TIMER_START_DISABLE,\n\\c EVR_RTX_TIMER_STARTED_DISABLE, \\c EVR_RTX_TIMER_STOP_DISABLE, \\c EVR_RTX_TIMER_STOPPED_DISABLE,\n\\c EVR_RTX_TIMER_IS_RUNNING_DISABLE, \\c EVR_RTX_TIMER_DELETE_DISABLE, \\c EVR_RTX_TIMER_DESTROYED_DISABLE\n\n\\b Mutex \\b events \\n\n\\c EVR_RTX_MUTEX_ERROR_DISABLE, \\c EVR_RTX_MUTEX_NEW_DISABLE, \\c EVR_RTX_MUTEX_CREATED_DISABLE,\n\\c EVR_RTX_MUTEX_GET_NAME_DISABLE, \\c EVR_RTX_MUTEX_ACQUIRE_DISABLE, \\c EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE,\n\\c EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE, \\c EVR_RTX_MUTEX_ACQUIRED_DISABLE, \\c EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE,\n\\c EVR_RTX_MUTEX_RELEASE_DISABLE, \\c EVR_RTX_MUTEX_RELEASED_DISABLE, \\c EVR_RTX_MUTEX_GET_OWNER_DISABLE,\n\\c EVR_RTX_MUTEX_DELETE_DISABLE, \\c EVR_RTX_MUTEX_DESTROYED_DISABLE\n\n\\b Semaphore \\b events \\n\n\\c EVR_RTX_SEMAPHORE_ERROR_DISABLE, \\c EVR_RTX_SEMAPHORE_NEW_DISABLE, \\c EVR_RTX_SEMAPHORE_CREATED_DISABLE,\n\\c EVR_RTX_SEMAPHORE_GET_NAME_DISABLE, \\c EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE, \\c EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE,\n\\c EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE, \\c EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE,\n\\c EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE, \\c EVR_RTX_SEMAPHORE_RELEASE_DISABLE, \\c EVR_RTX_SEMAPHORE_RELEASED_DISABLE,\n\\c EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE, \\c EVR_RTX_SEMAPHORE_DELETE_DISABLE, \\c EVR_RTX_SEMAPHORE_DESTROYED_DISABLE\n\n\\b Memory \\b pool \\b events \\n\n\\c EVR_RTX_MEMORY_POOL_ERROR_DISABLE, \\c EVR_RTX_MEMORY_POOL_NEW_DISABLE, \\c EVR_RTX_MEMORY_POOL_CREATED_DISABLE,\n\\c EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE, \\c EVR_RTX_MEMORY_POOL_ALLOC_DISABLE, \\c EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE,\n\\c EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE, \\c EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE,\n\\c EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE, \\c EVR_RTX_MEMORY_POOL_FREE_DISABLE, \\c EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE,\n\\c EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE, \\c EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE,\n\\c EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE, \\c EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE,\n\\c EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE, \\c EVR_RTX_MEMORY_POOL_DELETE_DISABLE, \\c EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE\n\n\\b Message \\b queue \\b events \\n\n\\c EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_GET_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE,\n\\c EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE, \\c EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE\n\n\n*/\n\n\n/* ========================================================================================================================== */\n/** \n\\ifnot FuSaRTS\n\\page creating_RTX5_LIB Building the RTX5 Library\n\nThe CMSIS Pack contains a µVision project for building the complete set of RTX5 libraries. This project can also be used as\na reference for building the RTX5 libraries using a tool-chain of your choice.\n\n-# Open the project \\b RTX_CM.uvprojx from the pack folder <b>CMSIS/RTOS2/RTX/Library/ARM/MDK</b> in µVision.\n-# Select the project target that matches your device's processor core. \n   \\n The project provides target configuration for all supported Cortex-M targets supported by RTX5.\n-# You can find out about the required preprocessor defines in the dialogs <b>Options for Target - C/C++</b> and\n   <b>Options for Target - Asm</b>. Note the need to use at least the C99 compiler mode when building RTX from source.\n-# From the <b>Project</b> window you find the list of source files required for a complete library build.\n-# Build the library of your choice using \\b Project - \\b Build \\b Target (or press F7).\n\n\\image html own_lib_projwin.png \"Project with files for Armv8-M Mainline\"\n\\endif\n*/\n\n\n\n/* ========================================================================================================================== */\n/** \n\\page technicalData5 Technical Data\n\nThe following section contains technical information about RTX v5.\n\n - \\subpage pHardwareRequirements lists the resource requirements of the RTX v5 kernel along with hardware dependencies.\n - \\subpage pStackRequirements lists the memory requirements for the main stack when running the RTX v5 kernel. \n - \\subpage pControlBlockSizes provides memory size information for \\ref StaticObjectMemory \"object-specific control block memory allocation\".\n - \\subpage pDirectory_Files is an overview of the supplied files that belong to RTX v5\n - \\subpage pToolchains details about the compiler support \\ifnot FuSaRTS which includes ArmCC (MDK, DS-5), IAR EW-ARM, and GCC. \\endif\n\n\n\\page pHardwareRequirements Hardware Requirements\n\nThe following section lists the hardware requirements for RTX v5 on the various supported target processors:\n\n\\section tpProcessor Processor Requirements\n\nRTX assumes a fully functionable processor and uses the following hardware features. It does not implement any confidence test for processor validation which should be provided by an user-supplied software test library.\n\n\n\\if ARMv8M \\subsection tpCortexM0_M0P_M23 Cortex-M0/M0+/M23 target processor\n\\endif\n\n\\ifnot ARMv8M \\subsection tpCortexM0_M0P_M23 Cortex-M0/M0+ target processor\n\\endif\n\nHardware Requirement       | Description\n:--------------------------|:------------------------------------------------------\nSysTick timer              | The SysTick timer generates the kernel tick interrupts and the interface is implemented in %os_systick.c using the \\ref CMSIS_RTOS_TickAPI\nException Handler          | RTX implements exception handlers for SVC, PendSV, and SysTick interrupt\nCore Registers             | The processor status is read using the following core registers: CONTROL, IPSR, PRIMASK\nSystem Control Block (SBC) | To control and setup the processor exceptions including PendSV and SVC\nInterrupt Control          | The CMSIS-Core functions __disable_irq and __enable_irq to control the interrupt system via the CPSR core register.\n\nThe RTX implements interfaces to the processor hardware in following files: \n - <b>%irq_armv6m.S</b> defines exception handlers for Cortex-M0/M0+\n\\if ARMv8M\n - <b>%irq_armv8mbl.S</b> defines exception handlers for Cortex-M23\n\\endif \n - <b>%rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.\n - <b>%os_tick.h</b> is the \\ref CMSIS_RTOS_TickAPI that defines the interface functions to the SysTick timer.\n\n\\note\n - The CMSIS-Core variable \\c SystemCoreClock is used by RTX to configure the SysTick timer. \n\n\\if ARMv8M \\subsection tpCortexM3_M4_M7_M33_M35P Cortex-M3/M4/M7/M33/M35P target processor\n\\endif \n\n\\ifnot ARMv8M \\subsection tpCortexM3_M4_M7_M33_M35P Cortex-M3/M4/M7 target processor\n\\endif \n\nRTX assumes a fully function-able processor and uses the following hardware features:\n\nHardware Item       | Requirement Description\n:--------------------------|:------------------------------------------------------\nSysTick timer              | The \\b SysTick timer shall be available in the processor. \nSystem Exceptions          | The RTX requires \\b SVC, \\b PendSV, and \\b SysTick exceptions and implements corresponding exception handlers.\nCore Registers             | The RTX uses \\b CONTROL, \\b IPSR , \\b PRIMASK and \\b BASEPRI core registers for reading processor status. \nSystem Control Block (SCB) | The RTX uses \\b SCB registers to control and setup the processor system exceptions including PendSV and SVC.\nNVIC Interface             | CMSIS-Core function \\b NVIC_GetPriorityGrouping is used by the RTX to setup interrupt priorities.\nLDREX, STREX instructions  | Exclusive access instructions \\b LDREX and \\b STREX are used to implement atomic execution without disabling interrupts.\n\nThe interface files to the processor hardware are: \n - <b>%irq_armv7m.S</b> defines exception handlers for Cortex-M3 and Cortex-M4/M7.\n\\if ARMv8M \n - <b>%irq_armv8mml.S</b> defines exception handlers for Cortex-M33/M35P\n\\endif\n - <b>%rtx_core_cm.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.\n - <b>%os_tick.h</b> is the \\ref CMSIS_RTOS_TickAPI that defines the interface functions to the SysTick timer.\n\n\\note\n - The CMSIS-Core variable \\c SystemCoreClock is used by RTX to configure the SysTick timer.\n\n\\if ARMCA \\subsection tpCortexA5_A7_A9 Cortex-A5/A7/A9 target processor\n\n\nHardware Requirement       | Description\n:--------------------------|:------------------------------------------------------\nTimer Peripheral           | An arbitrary timer peripheral generates the kernel tick interrupts. The interfaces for Cortex-A Generic Timer and Private Timer are implemented in %os_tick_gtim.c and %os_tick_ptim.c using the \\ref CMSIS_RTOS_TickAPI\nException Handler          | RTX implements exception handlers for SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction interrupt.\nCore Registers             | The processor status is read using the following core registers: CPSR, CPACR and FPSCR.\nLDREX, STREX instruction   | Atomic execution avoids the requirement to disable interrupts and is implemented via exclusive access instructions.\nInterrupt Controller       | An interrupt controller interface is required to setup and control Timer Peripheral interrupt. The interface for Arm GIC (Generic Interrupt Controller) is implemented in %irq_ctrl_gic.c using the <a class=\"el\" href=\"../../Core_A/html/group__irq__ctrl__gr.html\">IRQ Controller API</a>.\n\nThe interface files to the processor hardware are: \n - <b>%irq_armv7a.S</b> defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.\n - <b>%rtx_core_ca.h</b> defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.\n - <b>%os_tick.h</b> is the \\ref CMSIS_RTOS_TickAPI that defines the interface functions to the timer peripheral.\n - <b>%irq_ctrl.h</b> is the <a class=\"el\" href=\"../../Core_A/html/group__irq__ctrl__gr.html\">IRQ Controller API</a> that defines the interface functions to the interrupt controller.\n\n\\note\n - The CMSIS-Core variable \\c SystemCoreClock is used by RTX to configure the timer peripheral.\n\\endif\n\n\\section rMemory Memory Requirements\nRTX requires RAM memory that is accessible with contiguous linear addressing.  When memory is split across multiple memory banks, some systems \ndo not accept multiple load or store operations on this memory blocks. \n\nRTX does not implement any confidence test for memory validation. This should be implemented by an user-supplied software test library.\n\n\n\\page pStackRequirements Stack Requirements\n\nKeil RTX v5 kernel functions are executed in handler mode (using PendSV/SysTick/SVC) and the tables below lists the maximum stack requirements for the Main Stack (MSP) that the user\nshould consider. \n\nThe stack for the \\ref osKernelStart function is referred as \"Startup\" and RTX v5 uses 32 bytes (with Arm Compiler). However the user should also consider additional stack that\nmight be allocated by the 'main' function of the embedded application. The following picture shows a worst-case memory allocation of the Main Stack.\n\n\\image html \"KernelStackUsage.png\" \"Main Stack usage of RTX v5 applications\"\n\nThe stack requirements depend on the compiler and the optimization level.  RTX v5 supports event annotations and this configuration impacts also the stack requirement.\n\n\\ifnot FuSaRTS\n<b>Arm Compiler ARMCC V6.10</b>: Main Stack requirements for PendSV/SysTick/SVC\n\nOptimization         | RTX Kernel  | RTX Kernel + Event Recorder\n:--------------------|:------------|:--------------------------------\n-O1 (Debug)          | 152 bytes   | 280 bytes   \n-Os (Balanced)       | 120 bytes   | 256 bytes\n-Oz (Size)           | 112 bytes   | 248 bytes\n\n<b>Arm Compiler ARMCC V5.06</b>: Main Stack requirements for PendSV/SysTick/SVC\n\nOptimization         | RTX Kernel  | RTX Kernel + Event Recorder\n:--------------------|:------------|:--------------------------------\n-O0 (Debug)          | 176 bytes   | 360 bytes   \n-O1                  | 112 bytes   | 248 bytes\n-O2                  | 112 bytes   | 256 bytes\n-O3                  | 112 bytes   | 248 bytes\n\n\\endif\n\n\\page pControlBlockSizes Control Block Sizes\n\nKeil RTX v5 specific control block definitions (including sizes) as well as memory pool and message queue memory requirements\nare defined in the header file <b>rtx_os.h</b>:\n\nIf you provide memory for the RTOS objects, you need to know the size that is required for each object control block.\nThe memory of the control block is provided by the parameter \\em attr of the related \\em osXxxxNew function.\nThe element \\em cb_mem is the memory address, \\em cb_size is the size of the control block memory.\n\nRefer to \\ref StaticObjectMemory for more information.\n\nThe following table lists the control block sizes:\n\nCategory                      | Control Block Size Attribute      | Size       | \\#define symbol\n:-----------------------------|:----------------------------------|:-----------|:--------------------\n\\ref CMSIS_RTOS_ThreadMgmt    | \\ref osThreadAttr_t::cb_mem       | 80 bytes   | \\ref osRtxThreadCbSize\n\\ref CMSIS_RTOS_TimerMgmt     | \\ref osTimerAttr_t::cb_mem        | 32 bytes   | \\ref osRtxTimerCbSize\n\\ref CMSIS_RTOS_EventFlags    | \\ref osEventFlagsAttr_t::cb_mem   | 16 bytes   | \\ref osRtxEventFlagsCbSize\n\\ref CMSIS_RTOS_MutexMgmt     | \\ref osMutexAttr_t::cb_mem        | 28 bytes   | \\ref osRtxMutexCbSize\n\\ref CMSIS_RTOS_SemaphoreMgmt | \\ref osSemaphoreAttr_t::cb_mem    | 16 bytes   | \\ref osRtxSemaphoreCbSize\n\\ref CMSIS_RTOS_PoolMgmt      | \\ref osMemoryPoolAttr_t::cb_mem   | 36 bytes   | \\ref osRtxMemoryPoolCbSize\n\\ref CMSIS_RTOS_Message       | \\ref osMessageQueueAttr_t::cb_mem | 52 bytes   | \\ref osRtxMessageQueueCbSize\n\n\n\\page pDirectory_Files Directory Structure and File Overview\n\nThe following section provides an overview of the directory structure and the files that are relevant for the user's for\nCMSIS-RTOS RTX v5. The following directory references start below the CMSIS pack installation path, for example\nARM/CMSIS/<i>version</i>/CMSIS/RTOS2.\n\n\\section Folders RTX v5 Directory Structure\n\nThe CMSIS-RTOS RTX v5 is delivered in source code and several examples are provided. \n\n<table class=\"cmtable\" summary=\"CMSIS-RTOS RTX Library Files\">\n    <tr>\n      <th>Directory</th>\n      <th>Content</th>\n    </tr>\n    <tr>\n      <td>Include</td>\n      <td>Header files: \\b %cmsis_os2.h for \\ref rtos_api2 and \\b %os_tick.h for \\ref rtos_os_tick_api.</td>\n    </tr>\n    <tr>\n      <td>Source</td>\n      <td>Generic <b>OS tick</b> implementations for various processors based on \\ref rtos_os_tick_api.</td>\n    </tr>\n\\ifnot FuSaRTS\n    <tr>\n      <td>Template</td>\n      <td><a class=\"el\" href=\"../../RTOS/html/index.html\">CMSIS-RTOS API v1</a> template source and header file.</td>\n    </tr>\n\\endif\n    <tr>\n      <td>RTX</td>\n      <td>Directory with RTX specific files and folders. Also contains the component viewer description file.</td>\n    </tr>\n    <tr>\n      <td>RTX/Config</td>\n      <td>CMSIS-RTOS RTX configuration files \\b %RTX_Config.h and \\b %RTX_Config.c.</td>\n    </tr>\n\\ifnot FuSaRTS\n    <tr>\n      <td>RTX/Examples</td>\n      <td>Example projects that can be directly used in development tools.</td>\n    </tr>\n\\endif\n    <tr>\n      <td>RTX/Include</td>\n      <td>RTX v5 specific include files.</td>\n    </tr>\n\\ifnot FuSaRTS\n    <tr>\n      <td>RTX/Include1</td>\n      <td>CMSIS-RTOS v1 API header file.</td>\n    </tr>\n    <tr>\n      <td>RTX/Library</td>\n      <td>Pre-built libraries (see next table for details).</td>\n    </tr>\n\\endif\t\n    <tr>\n      <td>RTX/Source</td>\n      <td>Source code.</td>\n    </tr>\n    <tr>\n      <td>RTX/Template</td>\n      <td>User code templates for creating application projects with CMSIS-RTOS RTX v5.</td>\n    </tr>\n</table>\n\n\\ifnot FuSaRTS \n\\section libFiles RTX v5 Library Files\n\nThe CMSIS-RTOS RTX Library is available pre-compiled for ARMCC and GCC compilers and supports all Cortex-M\nprocessor variants in every configuration  \\if ARMv8M , including Arm Cortex-M23, Cortex-M33 and Cortex-M35P\\endif.\n\n\\ifnot FuSaRTS <table class=\"cmtable\" summary=\"CMSIS-RTOS RTX Library Files\">\n    <tr>\n      <th>Library File</th>\n      <th>Processor Configuration</th>\n    </tr>\n    <tr>\n      <td>Library/ARM/RTX_CM0.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Cortex-M0 and M1, little-endian.</td>\n    </tr>\n    <tr>\n      <td>Library/ARM/RTX_CM3.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Cortex-M3, M4, and M7 without FPU, little-endian.</td>\n    </tr>\n    <tr>\n      <td>Library/ARM/RTX_CM4F.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Cortex-M4 and M7 with FPU, little-endian.</td>\n    </tr>\n\\if ARMv8M\n    <tr>\n      <td>Library/ARM/RTX_V8MB.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Baseline.</td>\n    </tr>\n    <tr>\n      <td>Library/ARM/RTX_V8MBN.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Baseline, non-secure.</td>\n    </tr>\n    <tr>\n      <td>Library/ARM/RTX_V8MM.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline.</td>\n    </tr>\n    <tr>\n      <td>Library/ARM/RTX_V8MMF.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline with FPU.</td>\n    </tr>\n    <tr>\n      <td>Library/ARM/RTX_V8MMFN.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline with FPU, non-secure.</td>\n    </tr>\n    <tr>\n      <td>Library/ARM/RTX_V8MMN.lib</td>\n      <td>CMSIS-RTOS RTX Library for ARMCC Compiler, Armv8-M Mainline, non-secure.</td>\n    </tr>\n\\endif\n\\ifnot FuSaRTS\n    <tr>\n      <td>Library/GCC/libRTX_CM0.a</td>\n      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Cortex-M0 and M1, little-endian.</td>\n    </tr>\n    <tr>\n      <td>Library/GCC/libRTX_CM3.a</td>\n      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Cortex-M3, M4, and M7 without FPU, little-endian.</td>\n    </tr>\n    <tr>\n      <td>Library/GCC/libRTX_CM4F.a</td>\n      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Cortex-M4 and M7 with FPU, little-endian.</td>\n    </tr>\n\\endif\n\\if ARMv8M\t\n    <tr>\n      <td>Library/GCC/libRTX_V8MB.a</td>\n      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Baseline.</td>\n    </tr>\n    <tr>\n      <td>Library/GCC/libRTX_V8MBN.a</td>\n      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Baseline, non-secure.</td>\n    </tr>\n    <tr>\n      <td>Library/GCC/libRTX_V8MM.a</td>\n      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline.</td>\n    </tr>\n    <tr>\n      <td>Library/GCC/libRTX_V8MMF.a</td>\n      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline with FPU.</td>\n    </tr>\n    <tr>\n      <td>Library/GCC/libRTX_V8MMFN.a</td>\n      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline with FPU, non-secure.</td>\n    </tr>\n    <tr>\n      <td>Library/GCC/libRTX_V8MMN.a</td>\n      <td>CMSIS-RTOS libRTX Library for GCC Compiler, Armv8-M Mainline, non-secure.</td>\n    </tr>\n\\endif\n</table>\n\\endif\n\\endif\n*/\n\n\n/**\n\\page pToolchains Supported Toolchains\n\n\\if FuSaRTS\nFuSa RTX5 RTOS is validated using the compiler version referenced in <a href=\"../../Safety/html/index.html#safety_product_overview_toolchain\"><b>Tested and Verified Toolchains</b></a> section for the Arm FuSa Run-time System.\n\\endif\n\n\\ifnot FuSaRTS\n\nKeil RTX5 is developed and tested using the common toolchains and development environments.\n\n\\section technicalData_Toolchain_ARM Arm Compiler (Arm/Keil MDK, uVision5)\n\nRTX5 is initially developed and optimized using Arm Compiler and Arm/Keil MDK.\nThe current release is tested with the following versions:\n<ul>\n <li>Arm Compiler 5.06 Update 7</li>\n <li>Arm Compiler 6.6.4 (Long Term Maintenance)</li>\n <li>Arm Compiler 6.19</li>\n <li>RTOS-aware debugging with uVision 5.38</li>\n</ul>\n\n\n\\section technicalData_Toolchain_IAR IAR Embedded Workbench\n\nRTX5 has been ported to the IAR Embedded Workbench. The following releases are known to work:\n<ul>\n <li>IAR Embedded Workbench 7.7 (<a href=\"https://github.com/ARM-software/CMSIS_5/issues/201\">community report</a>)</li>\n <li>IAR Embedded Workbench 7.80.4</li>\n <li><b>IAR Embedded Workbench 8.20.1</b></li>\n</ul>\n\n\\section technicalData_Toolchain_GCC GNU Compiler Collection\n\nRTX5 has also been ported to support GCC, maintenance mainly relays on community contribution.\nActive development is currently tested with:\n<ul>\n <li>GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)</li>\n</ul>\n\n\\endif\n*/\n\n\n/* ========================================================================================================================== */\n/** \n\\page CodingRules Coding Rules\n\n\\ifnot FuSaRTS\nCMSIS components use <a href=\"../../General/html/index.html#CodingRules\"><b>general coding rules</b></a> across the various components.\n\\endif \n\n\\if FuSaRTS\nFuSa RTX RTOS uses <a href=\"../../Safety/html/index.html#CodingRules\"><b>general coding rules</b></a>.\n\\endif \n\nThe CMSIS-RTOS2 API is using the following <b>Namespace</b> prefixes:\n  - <b>os</b> for all definitions and function names.\n  - <b>os</b> with postfix <b>_t</b> for all typedefs.\n  \nThe CMSIS-RTOS2 RTX v5 implementation is using the following <b>Namespace</b> prefixes for public symbol definitions:\n  - <b>osRtx</b> for all general definitions and function names that relate to the RTX kernel.\n  - <b>osRtx</b> with postfix <b>_t</b> for all typedefs.\n  - <b>OS_Tick_</b> for interface functions to the hardware system tick timer.\n  - <b>EvrRtx</b> for event function annotations that interface to the Event Recorder.\n*/\n\n/* ========================================================================================================================== */\n/** \n\\page misraCompliance5 MISRA C:2012 Compliance \nThe RTX5 C source files use <b><a class=el href=\"http://www.misra.org.uk/\" target=\"_blank\">MISRA C:2012</a></b> guidelines as underlying coding standard.\n\nFor MISRA validation, <b><a class=el href=\"http://www.gimpel.com/\" target=\"_blank\">PC-lint</a></b> V9.00L is used with configuration for Arm Compiler V6.19.\nThe PC-Lint validation setup is part of the project file <b>.\\\\CMSIS\\\\RTOS2\\\\RTX\\\\Library\\\\ARM\\\\MDK\\\\RTX_CM.uvprojx</b> as shown below. \nRefer to <b><a class=el href=\"https://www.keil.com/support/man/docs/uv4/uv4_ut_pclint_validation.htm\" target=\"_blank\">Setup for PC-Lint</a></b> for more information.\n\n\\image html \"PC-Lint.png\" \"Running PC-Lint within MDK - uVision\"\n\nThe PC-Lint configuration uses the following Options under <b>Tools - PC-Lint Setup...</b>:\n - Config File: co-ARMCC-6.lnt (20-Mar-2017) with additional options:\n\\code\n   -esym(526,__builtin_*)\n   -esym(628,__builtin_*)\n   -esym(718,__builtin_*)\n   -esym(746,__builtin_*)\n   -sem(__CLZ, pure)\n   +doffsetof(t,m)=((size_t)&((t*)0)->m)\n   -emacro((413,923,9078),offsetof)\n\\endcode\n - Included Project Information: \n   - Enable: Add 'Include' paths\n   - Enable: Add 'Software Packs' paths\n   - Enable: Verify 'Software Packs' includes\n   - Enable: Add 'Preprocessor' symbols\n   - Enable: Add 'Define' symbols\n - MISRA  Rules Setup and Configuration: \n   - MISRQ_C_2012_Config.lnt; all rules enabled\n   - includes definition file: au-misra3.lnt (12-Jun-2014)\n - Additional Lint Commands (for both single and multiple files):\n\\code\n   -emacro(835,osRtxConfigPrivilegedMode)\n\\endcode\n\nThe C source code is annotated with PC-Lint control comments to allows MISRA deviations.\nThese deviations with the underlying design decisions are described in the following.\n   \nDeviations\n----------\n\nThe RTX source code has the following deviations from MISRA:\n  - \\ref MISRA_1\n  - \\ref MISRA_2\n  - \\ref MISRA_3\n  - \\ref MISRA_4\n  - \\ref MISRA_5\n  - \\ref MISRA_6\n  - \\ref MISRA_7\n  - \\ref MISRA_8\n  - \\ref MISRA_9\n  - \\ref MISRA_10\n  - \\ref MISRA_11\n  - \\ref MISRA_12\n  - \\ref MISRA_13\n\nAll source code deviations are clearly marked and in summary these deviations affect the following MISRA rules:\n - [MISRA 2012 Directive  4.9,  advisory]: A function should be used in preference to a function-like macro where yet are interchangeable\n - [MISRA 2012 Rule       1.3,  required]: There shall be no occurrence of undefined or critical unspecified behavior\n - [MISRA 2012 Rule      10.3,  required]: Expression assigned to a narrower or different essential type\n - [MISRA 2012 Rule      10.5,  advisory]: Impermissible cast; cannot cast from 'essentially unsigned' to 'essentially enum\\<i\\>'\n - [MISRA 2012 Rule      11.1,  required]: Conversions shall not be performed between a pointer to a function and any other type\n - [MISRA 2012 Rule      11.3,  required]: A cast shall not be performed between a pointer to object type and a pointer to a different object type\n - [MISRA 2012 Rule      11.4,  advisory]: A conversion should not be performed between a pointer to object and an integer type\n - [MISRA 2012 Rule      11.5,  advisory]: A conversion should not be performed from pointer to void into pointer to object\n - [MISRA 2012 Rule      11.6,  required]: A cast shall not be performed between pointer to void and an arithmetic type\n - [MISRA 2012 Rule      15.5,  advisory]: A function should have a single point of exit at the end\n - [MISRA 2012 Rule      20.10, advisory]: The # and ## preprocessor operators should not be used\n\nIn the following all deviations are described in detail.\n\n\\section MISRA_1 [MISRA Note 1]: Return statements for parameter checking\n\nReturn statements are used at the beginning of several functions to validate parameter values and object states.\nThe function returns immediately without any side-effects and typically an error status is set. This structure\nkeeps the source code better structured and easier to understand.\n\nThis design decision implies the following MISRA deviation:\n - [MISRA 2012 Rule      15.5,  advisory]: A function should have a single point of exit at the end\n\nAll locations in the source code are marked with: \n\\code\n  //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n\\endcode \n\n\n\\section MISRA_2 [MISRA Note 2]: Object identifiers are void pointers\n\nCMSIS-RTOS is independent of an underlying RTOS implementation. The object identifiers are therefore defined as void pointers to:\n  - allow application programs that are agnostic from an underlying RTOS implementation.\n  - avoid accidentally accesses an RTOS control block from an application program.\n\nThis design decisions imply the following MISRA deviations:\n - [MISRA 2012 Rule      11.3,  required]: A cast shall not be performed between a pointer to object type and a pointer to a different object type\n - [MISRA 2012 Rule      11.5,  advisory]: A conversion should not be performed from pointer to void into pointer to object\n\nAll locations in the source code are marked with: \n\\code\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 2]\n\\endcode \n\nIn the RTX5 implementation the required pointer conversions are implemented in the header file rtx_lib.h with the following inline functions:\n\n\\code\nosRtxThread_t       *osRtxThreadId (osThread_t thread_id);\nosRtxTimer_t        *osRtxTimerId (osTimer_t timer_id);\nosRtxEventFlags_t   *osRtxEventFlagsId (osEventFlags_t ef_id);\nosRtxMutex_t        *osRtxMutexId (osMutex_t mutex_id);\nosRtxSemaphore_t    *osRtxSemaphoreId (osSemaphore_t semaphore_id);\nosRtxMemoryPool_t   *osRtxMemoryPoolId (osMemoryPoolId_t mp_id);\nosRtxMessageQueue_t *osRtxMessageQueueId(osMessageQueueId_t mq_id);\n\\endcode\n\n\\section MISRA_3 [MISRA Note 3]: Conversion to unified object control blocks\n\nRTX uses a unified object control block structure that contains common object members.\nThe unified control blocks use a fixed layout at the beginning of the structure and starts always with an object identifier.\nThis allows common object functions that receive a pointer to a unified object control block and reference only the\npointer or the members in the fixed layout. Using common object functions and data (for example the ISR queue) reduces \ncode complexity and keeps the source code better structured.  Refer also to \\ref MISRA_4\n\nThis design decisions imply the following MISRA deviations:\n - [MISRA 2012 Rule      11.3,  required]: A cast shall not be performed between a pointer to object type and a pointer to a different object type\n - [MISRA 2012 Rule      11.5,  advisory]: A conversion should not be performed from pointer to void into pointer to object\n\nAll locations in the source code are marked with: \n\\code\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 3]\n\\endcode \n\n\nIn the RTX5 implementation the required pointer conversions are implemented in the header file \\em rtx_lib.h with the following inline function:\n\n\\code\nosRtxObject_t *osRtxObject (void *object);\n\\endcode\n\n\n\\section MISRA_4 [MISRA Note 4]: Conversion from unified object control blocks\n\nRTX uses a unified object control block structure that contains common object members. Refer to \\ref MISRA_3 for more information.\nTo process specific control block data, pointer conversions are required.\n\nThis design decisions imply the following MISRA deviations:\n - [MISRA 2012 Rule       1.3,  required]: There shall be no occurrence of undefined or critical unspecified behavior\n - [MISRA 2012 Rule      11.3,  required]: A cast shall not be performed between a pointer to object type and a pointer to a different object type\nIn addition PC-Lint issues:\n - Info  826: Suspicious pointer-to-pointer conversion (area too small)\n\nAll locations in the source code are marked with: \n\\code\n  //lint -e{740} -e{826} -e{9087} \"cast from pointer to generic object to specific object\" [MISRA Note 4]\n\\endcode \n\nIn the RTX5 source code the required pointer conversions are implemented in the header file \\em rtx_lib.h with the following inline functions:\n\n\\code\nosRtxThread_t       *osRtxThreadObject (osRtxObject_t *object);\nosRtxTimer_t        *osRtxTimerObject (osRtxObject_t *object);\nosRtxEventFlags_t   *osRtxEventFlagsObject (osRtxObject_t *object);\nosRtxMutex_t        *osRtxMutexObject (osRtxObject_t *object);\nosRtxSemaphore_t    *osRtxSemaphoreObject (osRtxObject_t *object);\nosRtxMemoryPool_t   *osRtxMemoryPoolObject (osRtxObject_t *object);\nosRtxMessageQueue_t *osRtxMessageQueueObject (osRtxObject_t *object);\nosRtxMessage_t      *osRtxMessageObject (osRtxObject_t *object);\n\\endcode\n\n\\section MISRA_5 [MISRA Note 5]: Conversion to object types\n\nThe RTX5 kernel has common memory management functions that use void pointers. These memory allocation functions return \na void pointer which is correctly aligned for object types.\n\nThis design decision implies the following MISRA deviations:\n - [MISRA 2012 Rule      11.5,  advisory]: A conversion should not be performed from pointer to void into pointer to object\n\nAll locations in the source code are marked with: \n\\code\n  //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n\\endcode \n\nCode example:\n\n\\code \n  os_thread_t  *thread;\n   :\n  //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n  thread = osRtxMemoryPoolAlloc(osRtxInfo.mpi.thread);\n\\endcode\n\n\\section MISRA_6 [MISRA Note 6]: Conversion from user provided storage\n\nCMSIS-RTOS2 and RTX5 support user provided storage for object control blocks, stack, and data storage.\nThe API uses void pointers to define the location of this user provided storage. It is therefore\nrequired to cast the void pointer to underlying storage types. Alignment restrictions of user provided storage \nare checked before accessing memory. Refer also to \\ref MISRA_7.\n\nThis design decisions imply the following MISRA deviations:\n - [MISRA 2012 Rule      11.3,  required]: A cast shall not be performed between a pointer to object type and a pointer to a different object type\n - [MISRA 2012 Rule      11.5,  advisory]: A conversion should not be performed from pointer to void into pointer to object\n\nAll locations in the source code are marked with: \n\\code\n  //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n\\endcode \n\nCode example:\n\\code\nstatic osTimerId_t svcRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {\n  os_timer_t *timer;\n    :\n  if (attr != NULL) {\n    :\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    timer = attr->cb_mem;\n    :\n\\endcode\n\n\\section MISRA_7 [MISRA Note 7]: Check for proper pointer alignment\n\nRTX5 verifies the alignment of user provided storage for object control blocks, stack, and data storage.\nRefer also to \\ref MISRA_6 for more information.\n\nThis design decision implies the following MISRA deviations:\n - [MISRA 2012 Rule      11.4,  advisory]: A conversion should not be performed between a pointer to object and an integer type\n - [MISRA 2012 Rule      11.6,  required]: A cast shall not be performed between pointer to void and an arithmetic type\n\nAll locations in the source code are marked with: \n\\code\n  //lint -e{923} -e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n\\endcode\n\nCode example:\n\\code\nstatic osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {\n    :\n  void         *stack_mem;\n    :\n  if (stack_mem != NULL) {\n    //lint -e{923} \"cast from pointer to unsigned int\" [MISRA Note 7]\n    if ((((uint32_t)stack_mem & 7U) != 0U) || (stack_size == 0U)) {\n    :\n\\endcode\n\n\\section MISRA_8 [MISRA Note 8]: Memory allocation management\n\nRTX5 implements memory allocation functions which require pointer arithmetic to manage memory.\nThe structure with the type \\em mem_block_t that is used to menage memory allocation blocks is defined in \\em rtx_memory.c\n\nThis design decision implies the following MISRA deviations:\n - [MISRA 2012 Rule      11.4,  advisory]: A conversion should not be performed between a pointer to object and an integer type\n - [MISRA 2012 Rule      11.6,  required]: A cast shall not be performed between pointer to void and an arithmetic type\n\nAll locations in the source code are marked with: \n\\code\n  //lint -e{923} -e{9078} \"cast from pointer to unsigned int\" [MISRA Note 8]\n\\endcode\n\nThe required pointer arithmetic is implemented in \\em rtx_memory.c with the following function:\n\\code\n__STATIC_INLINE mem_block_t *MemBlockPtr (void *mem, uint32_t offset) {\n  uint32_t     addr;\n  mem_block_t *ptr;\n\n  //lint --e{923} --e{9078} \"cast between pointer and unsigned int\" [MISRA Note 8]\n  addr = (uint32_t)mem + offset;\n  ptr  = (mem_block_t *)addr;\n\n  return ptr;\n}\n\\endcode\n\n\\section MISRA_9 [MISRA Note 9]: Pointer conversions for register access\n\nThe CMSIS-Core peripheral register blocks are accessed using a structure. The memory address of this structure \nis specified as unsigned integer number. Pointer conversions are required to access the specific registers.\n\nThis design decision implies the following MISRA deviations:\n - [MISRA 2012 Rule      11.4,  advisory]: A conversion should not be performed between a pointer to object and an integer type\n - [MISRA 2012 Rule      11.6,  required]: A cast shall not be performed between pointer to void and an arithmetic type\n\nAll locations in the source code are marked with: \n\\code\n  //lint -emacro((923,9078),SCB) \"cast from unsigned long to pointer\" [MISRA Note 9]\n\\endcode\n\n\nCode example:\n\\code\n#define SCS_BASE  (0xE000E000UL)\n#define SCB      ((SCB_Type *)SCB_BASE)\ntypedef struct {...} SCB_Type;\n\nSCB->... = ...;\n\\endcode\n\n\\section MISRA_10 [MISRA Note 10]: SVC calls use function-like macros\n\nRTX5 is using SVC (Service Calls) to switch between thread mode (for user code execution) and handler mode (for RTOS kernel execution).\nThe SVC function call mechanism is implemented with assembly instructions to construct the code for SVC.\nThe source code uses C macros and are designed as C function-like macros to generate parameter passing\nfor variables depending on macro parameters. An alternative replacement code would be complex.\nThe C macros use multiple '##' operators however it has been verified that the order of evaluation is irrelevant \nand result of macro expansion is always predictable.\n\nThis design decision implies the following MISRA deviations:\n - [MISRA 2012 Directive  4.9,  advisory]: A function should be used in preference to a function-like macro where yet are interchangeable\n - [MISRA 2012 Rule       1.3,  required]: There shall be no occurrence of undefined or critical unspecified behavior\n - [MISRA 2012 Rule      20.10, advisory]: The # and ## preprocessor operators should not be used\n\nThe relevant source code is in the file \\em rtx_core_cm.h and is marked with: \n\\code\n  //lint -save -e9023 -e9024 -e9026 \"Function-like macros using '#/##'\" [MISRA Note 10]\n\\endcode\n\n\n\\section MISRA_11 [MISRA Note 11]: SVC calls use assembly code\n\nThe SVC (Service Call) functions are constructed as a mix of C and inline assembly as it is required to access CPU registers\nfor parameter passing. The function parameters are mapped to the CPU registers R0..R3 and SVC function number to \nCPU register R12 (or R7). For assembly inter-working the function parameters are casted to unsigned int values.\n\nThe function return value after SVC call is mapped to the CPU register R0. Return value is casted from unsigned int \nto the target value. \n\nIt has been verified that this method has no side-effects and is well defined.\n\nThis design decision implies the following MISRA deviations:\n - [MISRA 2012 Rule      10.3,  required]: Expression assigned to a narrower or different essential type\n - [MISRA 2012 Rule      10.5,  advisory]: Impermissible cast; cannot cast from 'essentially unsigned' to 'essentially enum\\<i\\>'\n - [MISRA 2012 Rule      11.1,  required]: Conversions shall not be performed between a pointer to a function and any other type\n - [MISRA 2012 Rule      11.4,  advisory]: A conversion should not be performed between a pointer to object and an integer type\n - [MISRA 2012 Rule      11.6,  required]: A cast shall not be performed between pointer to void and an arithmetic type\n\nSVC functions are marked as library modules and not processed by PC-lint. The relevant source code is marked with: \n\\code\n  //lint ++flb \"Library Begin\" [MISRA Note 11]\n    :\n  //lint --flb \"Library End\"\n\\endcode\n\nCode example:\n\\code\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_1(Delay,      osStatus_t, uint32_t)\nSVC0_1(DelayUntil, osStatus_t, uint32_t)\n//lint --flb \"Library End\"\n\\endcode\n\nPC-lint does not process ASM input/output operand lists and therefore falsely identifies issues:\n - Last value assigned to variable not used\n - Symbol not subsequently referenced\n\\todo: what has been done to mitigate that?\n\n\n\\section MISRA_12 [MISRA Note 12]: Usage of exclusive access instructions\n\nThe RTX5 implementation uses the CPU instructions LDREX and STREX (when supported by the processor) to implement atomic operations.\n\nThese atomic operations eliminate the requirement for interrupt lock-outs. The atomic operations are implemented using inline assembly.\n\nPC-lint cannot process assembler instructions including the input/output operand lists and therefore falsely identifies issues:\n - Symbol not initialized\n - Symbol not subsequently referenced\n - Symbol not referenced\n - Pointer parameter could be declared as pointing to const\n\nIt has been verified that atomic operations have no side-effects and are well defined.\n\nThe functions that implement atomic instructions are marked as library modules and not processed by PC-lint. The relevant source code is marked with: \n\\code\n  //lint ++flb \"Library Begin\" [MISRA Note 12]\n    :\n  //lint --flb \"Library End\"\n\\endcode\n\n\n\\section MISRA_13 [MISRA Note 13]: Usage of Event Recorder\n\nThe Event Recorder is a generic event logger and the related functions are called to record an event.\nThe function parameters are 32-bit id, 32-bit values, pointer to void (data) and are recorded as 32-bit numbers.\nThe parameters for the Event Recorder may require cast operations to unsigned int which however has no side-effects \nand is well defined. \n\nThe return value indicates success or failure. There is no need to check the return value since no action is \ntaken when an Event Recorder function fail. The EventID macro (part of external Event Recorder) constructs the \nID based on input parameters which are shifted, masked with '&' and combined with '|'.\nZero value input parameters are valid and cause zero used with '&' and '|'.\n\nThe usage of the Event Recorder implies the following MISRA deviations:\n - [MISRA 2012 Rule      11.1,  required]: Conversions shall not be performed between a pointer to a function and any other type\n - [MISRA 2012 Rule      11.4,  advisory]: A conversion should not be performed between a pointer to object and an integer type\n - [MISRA 2012 Rule      11.6,  required]: A cast shall not be performed between pointer to void and an arithmetic type\nIn addition PC-Lint issues:\n - Info  835: A zero has been given as left argument to operator '&'\n - Info  845: The right argument to operator '|' is certain to be 0\n\nThe functions that call the Event Recorder are in the module \\em rtx_evr.c and the related PC-Lint messages are disabled with:\n\\code\n  //lint -e923 -e9074 -e9078 -emacro((835,845),EventID) [MISRA Note 13]\n\\endcode\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page functionOverview Function Overview\n\nCMSIS-RTOS2 provides following API interfaces:\n  - \\subpage rtos_api2 is the C function interface that supports dynamic object creation \\if ARMv8M and Armv8-M (Arm Cortex-M23,\n    Cortex-M33 and Cortex-M35P) \\endif.\n\\ifnot FuSaRTS\t\n  - <a class=\"el\" href=\"../../RTOS/html/functionOverview.html\">CMSIS-RTOS C API v1</a> is a C function API that is backward\n    compatible with CMSIS-RTOS v1.\n  - \\subpage rtos_apicpp is a C++ class function API (future extension).\n\nIt is possible to intermix the different API variants in the same application and even in the same C/C++ source module.\nHowever, the functions of the <a class=\"el\" href=\"../../RTOS/html/functionOverview.html\">CMSIS-RTOS C API v1</a> may be deprecated in future versions of CMSIS-RTOS.\n\\endif\n\nCMSIS-RTOS2 defines also a generic system timer interface that works across the supported Arm Cortex processors:\n  - \\subpage rtos_os_tick_api is the interface to a kernel system timer.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page rtos_api2 CMSIS-RTOS C API v2\n\nOverview of all CMSIS-RTOS C API v2 functions that are implemented in the \\subpage cmsis_os2_h. \n\n\\section rtos_api2_basics Common Design Concepts\n\nAll RTOS objects share a common design concept. The overall life-cycle of\nan object can be summarized as created -> in use -> destroyed.\n\n<b>Create Objects</b>\n\nAn object is created by calling its `osXxxNew` function. The new function returns an identifier\nthat can be used to operate with the new object. The actual state of an object is typically stored\nin an object specific control block. The memory layout (and size needed) for the control\nblock is implementation specific. One should not make any specific assumptions about the control\nblock. The control block layout might change and hence should be seen as an implementation\ninternal detail.\n\nIn order to expose control about object specific options all `osXxxNew` functions provide an\noptional `attr` argument, which can be left as \\token{NULL} by default. It takes a pointer to\nan object specific attribute structure, commonly containing the fields\n - `name` to attach a human readable name to the object for identification,\n - `attr_bits` to control object-specific options,\n - `cb_mem` to provide memory for the control block manually, and\n - `cb_size` to quantify the memory size provided for the control block.\n\nThe `name` attribute is only used for object identification, e.g. using RTOS-aware debugging. The\nattached string is not used for any other purposes internally.\n\nThe `cb_mem` and `cb_size` attributes can be used to provide memory for the control block manually\ninstead of relying on the implementation internal memory allocation. One has to assure that the\namount of memory pointed to by `cb_mem` is sufficient for the objects control block structure. If\nthe size given as `cb_size` is not sufficient the `osXxxNew` function returns with an error, i.e.\nreturning \\token{NULL}. Furthermore providing control block memory manually is less portable. Thus\none has to take care about implementation specific alignment and placement requirements for instance.\nRefer to \\ref CMSIS_RTOS_MemoryMgmt for further details.\n\n<b>Object Usage</b>\n\nAfter an object has been created successfully it can be used until it is destroyed. The actions\ndefined for an object depends on its type. Commonly all the `osXxxDoSomething` access function\nrequire the reference to the object to work with as the first `xxx_id` parameter.\n\nThe access function can be assumed to apply some sort of sanity checking on the id parameter. So\nthat it is assured one cannot accidentally call an access function with a \\token{NULL} object\nreference. Furthermore the concrete object type is verified, i.e. one cannot call access functions\nof one object type with a reference to another object type.\n\nAll further parameter checks applied are either object and action specific or may even be implementation\nspecific. Thus one should always check action function return values for `osErrorParameter` to assure the\nprovided arguments were accepted.\n\nAs a rule of thumb only non-blocking access function can be used from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" (ISR).\nThis incorporates `osXxxWait` functions (and similar) limited to be called with parameter `timeout`\nset to \\token{0}, i.e. usage of try-semantics.\n\n<b>Object Destruction</b>\n\nObjects that are not needed anymore can be destructed on demand to free the control block memory. Objects\nare not destructed implicitly. Thus one can assume an object id to be valid until `osXxxDelete` is called\nexplicitly. The delete function finally frees the control block memory. In case of user provided control\nblock memory, see above, the memory must be freed manually as well. \n\nThe only exception one has to take care of are Threads which do not have an explicit `osThreadDelete` function.\nThreads can either be `detached` or `joinable`. Detached threads are automatically destroyed on termination,\ni.e. call to \\ref osThreadTerminate or \\ref osThreadExit or return from thread function. On the other hand joinable\nthreads are kept alive until one explicitly calls \\ref osThreadJoin.\n\n\\section rtos_api2_functions Function Reference\n\n - \\ref CMSIS_RTOS_KernelCtrl\n   - \\ref osKernelGetInfo : \\copybrief osKernelGetInfo\n   - \\ref osKernelGetState : \\copybrief osKernelGetState\n   - \\ref osKernelGetSysTimerCount : \\copybrief osKernelGetSysTimerCount\n   - \\ref osKernelGetSysTimerFreq : \\copybrief osKernelGetSysTimerFreq\n   - \\ref osKernelInitialize : \\copybrief osKernelInitialize\n   - \\ref osKernelLock : \\copybrief osKernelLock\n   - \\ref osKernelUnlock : \\copybrief osKernelUnlock\n   - \\ref osKernelRestoreLock : \\copybrief osKernelRestoreLock\n   - \\ref osKernelResume : \\copybrief osKernelResume\n   - \\ref osKernelStart : \\copybrief osKernelStart\n   - \\ref osKernelSuspend : \\copybrief osKernelSuspend\n   - \\ref osKernelGetTickCount : \\copybrief osKernelGetTickCount\n   - \\ref osKernelGetTickFreq : \\copybrief osKernelGetTickFreq\n   - \\ref osKernelDestroyClass : \\copybrief osKernelDestroyClass\n   - \\ref osKernelProtect : \\copybrief osKernelProtect\n   - \\ref osFaultResume : \\copybrief osFaultResume\n<br><br>\n - \\ref CMSIS_RTOS_ThreadMgmt\n   - \\ref osThreadDetach : \\copybrief osThreadDetach\n   - \\ref osThreadEnumerate : \\copybrief osThreadEnumerate\n   - \\ref osThreadExit : \\copybrief osThreadExit\n   - \\ref osThreadGetCount : \\copybrief osThreadGetCount\n   - \\ref osThreadGetId : \\copybrief osThreadGetId\n   - \\ref osThreadGetName : \\copybrief osThreadGetName\n   - \\ref osThreadGetPriority : \\copybrief osThreadGetPriority\n   - \\ref osThreadGetStackSize : \\copybrief osThreadGetStackSize\n   - \\ref osThreadGetStackSpace : \\copybrief osThreadGetStackSpace\n   - \\ref osThreadGetState : \\copybrief osThreadGetState\n   - \\ref osThreadJoin : \\copybrief osThreadJoin\n   - \\ref osThreadNew : \\copybrief osThreadNew\n   - \\ref osThreadResume : \\copybrief osThreadResume\n   - \\ref osThreadSetPriority : \\copybrief osThreadSetPriority\n   - \\ref osThreadSuspend : \\copybrief osThreadSuspend\n   - \\ref osThreadTerminate : \\copybrief osThreadTerminate\n   - \\ref osThreadYield : \\copybrief osThreadYield\n   - \\ref osThreadGetClass : \\copybrief osThreadGetClass\n   - \\ref osThreadGetZone : \\copybrief osThreadGetZone\n   - \\ref osThreadFeedWatchdog : \\copybrief osThreadFeedWatchdog\n   - \\ref osThreadProtectPrivileged : \\copybrief osThreadProtectPrivileged\n   - \\ref osThreadResumeClass : \\copybrief osThreadResumeClass\n   - \\ref osThreadSuspendClass : \\copybrief osThreadSuspendClass\n   - \\ref osThreadTerminateZone : \\copybrief osThreadTerminateZone\n   - \\ref osWatchdogAlarm_Handler : \\copybrief osWatchdogAlarm_Handler\n   - \\ref osZoneSetup_Callback : \\copybrief osZoneSetup_Callback\n<br><br>\n - \\ref CMSIS_RTOS_ThreadFlagsMgmt\n   - \\ref osThreadFlagsSet : \\copybrief osThreadFlagsSet\n   - \\ref osThreadFlagsClear : \\copybrief osThreadFlagsClear\n   - \\ref osThreadFlagsGet : \\copybrief osThreadFlagsGet\n   - \\ref osThreadFlagsWait : \\copybrief osThreadFlagsWait\n<br><br>\n - \\ref CMSIS_RTOS_EventFlags\n   - \\ref osEventFlagsGetName : \\copybrief osEventFlagsGetName\n   - \\ref osEventFlagsNew : \\copybrief osEventFlagsNew\n   - \\ref osEventFlagsDelete : \\copybrief osEventFlagsDelete\n   - \\ref osEventFlagsSet : \\copybrief osEventFlagsSet\n   - \\ref osEventFlagsClear : \\copybrief osEventFlagsClear\n   - \\ref osEventFlagsGet : \\copybrief osEventFlagsGet\n   - \\ref osEventFlagsWait : \\copybrief osEventFlagsWait\n<br><br>\n - \\ref CMSIS_RTOS_Wait\n   - \\ref osDelay : \\copybrief osDelay\n   - \\ref osDelayUntil : \\copybrief osDelayUntil\n<br><br>\n - \\ref CMSIS_RTOS_TimerMgmt\n   - \\ref osTimerDelete : \\copybrief osTimerDelete\n   - \\ref osTimerGetName : \\copybrief osTimerGetName\n   - \\ref osTimerIsRunning : \\copybrief osTimerIsRunning\n   - \\ref osTimerNew : \\copybrief osTimerNew\n   - \\ref osTimerStart : \\copybrief osTimerStart\n   - \\ref osTimerStop : \\copybrief osTimerStop\n<br><br>\n - \\ref CMSIS_RTOS_MutexMgmt\n   - \\ref osMutexAcquire : \\copybrief osMutexAcquire\n   - \\ref osMutexDelete : \\copybrief osMutexDelete\n   - \\ref osMutexGetName : \\copybrief osMutexGetName\n   - \\ref osMutexGetOwner : \\copybrief osMutexGetOwner\n   - \\ref osMutexNew : \\copybrief osMutexNew\n   - \\ref osMutexRelease : \\copybrief osMutexRelease\n<br><br>\n - \\ref CMSIS_RTOS_SemaphoreMgmt\n   - \\ref osSemaphoreAcquire : \\copybrief osSemaphoreAcquire\n   - \\ref osSemaphoreDelete : \\copybrief osSemaphoreDelete\n   - \\ref osSemaphoreGetCount : \\copybrief osSemaphoreGetCount\n   - \\ref osSemaphoreGetName : \\copybrief osSemaphoreGetName\n   - \\ref osSemaphoreNew : \\copybrief osSemaphoreNew\n   - \\ref osSemaphoreRelease : \\copybrief osSemaphoreRelease\n<br><br>\n - \\ref CMSIS_RTOS_PoolMgmt\n   - \\ref osMemoryPoolAlloc : \\copybrief osMemoryPoolAlloc\n   - \\ref osMemoryPoolDelete : \\copybrief osMemoryPoolDelete\n   - \\ref osMemoryPoolFree : \\copybrief osMemoryPoolFree\n   - \\ref osMemoryPoolGetBlockSize : \\copybrief osMemoryPoolGetBlockSize\n   - \\ref osMemoryPoolGetCapacity : \\copybrief osMemoryPoolGetCapacity\n   - \\ref osMemoryPoolGetCount : \\copybrief osMemoryPoolGetCount\n   - \\ref osMemoryPoolGetName : \\copybrief osMemoryPoolGetName\n   - \\ref osMemoryPoolGetSpace : \\copybrief osMemoryPoolGetSpace\n   - \\ref osMemoryPoolNew : \\copybrief osMemoryPoolNew\n<br><br>\n - \\ref CMSIS_RTOS_Message\n   - \\ref osMessageQueueDelete : \\copybrief osMessageQueueDelete\n   - \\ref osMessageQueueGet : \\copybrief osMessageQueueGet\n   - \\ref osMessageQueueGetCapacity : \\copybrief osMessageQueueGetCapacity\n   - \\ref osMessageQueueGetCount : \\copybrief osMessageQueueGetCount\n   - \\ref osMessageQueueGetMsgSize : \\copybrief osMessageQueueGetMsgSize\n   - \\ref osMessageQueueGetName : \\copybrief osMessageQueueGetName\n   - \\ref osMessageQueueGetSpace : \\copybrief osMessageQueueGetSpace\n   - \\ref osMessageQueueNew : \\copybrief osMessageQueueNew\n   - \\ref osMessageQueuePut : \\copybrief osMessageQueuePut\n   - \\ref osMessageQueueReset : \\copybrief osMessageQueueReset\n \n\\todo restructure\n - \\ref rtx5_specific\n   - \\ref osRtxErrorNotify : \\copybrief osRtxErrorNotify\n   - \\ref osRtxIdleThread : \\copybrief osRtxIdleThread\n\nThe following CMSIS-RTOS C API v2 functions can be called from threads and \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\"\n(ISR):\n   - \\ref osKernelGetInfo, \\ref osKernelGetState,\n     \\ref osKernelGetTickCount, \\ref osKernelGetTickFreq, \\ref osKernelGetSysTimerCount, \\ref osKernelGetSysTimerFreq\n   - \\ref osThreadGetName, \\ref osThreadGetId, \\ref osThreadFlagsSet\n   - \\ref osTimerGetName\n   - \\ref osEventFlagsGetName, \\ref osEventFlagsSet, \\ref osEventFlagsClear, \\ref osEventFlagsGet, \\ref osEventFlagsWait\n   - \\ref osMutexGetName\n   - \\ref osSemaphoreGetName, \\ref osSemaphoreAcquire, \\ref osSemaphoreRelease, \\ref osSemaphoreGetCount\n   - \\ref osMemoryPoolGetName, \\ref osMemoryPoolAlloc, \\ref osMemoryPoolFree,\n     \\ref osMemoryPoolGetCapacity, \\ref osMemoryPoolGetBlockSize, \\ref osMemoryPoolGetCount, \\ref osMemoryPoolGetSpace\n   - \\ref osMessageQueueGetName, \\ref osMessageQueuePut, \\ref osMessageQueueGet, \\ref osMessageQueueGetCapacity,\n     \\ref osMessageQueueGetMsgSize, \\ref osMessageQueueGetCount, \\ref osMessageQueueGetSpace\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\ifnot FuSaRTS\n\\page rtos_apicpp CMSIS-RTOS C++ API\n\nA C++11/C++14 interface is planned for the future.\n\\endif\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page rtos_os_tick_api OS Tick API\n\nThe CMSIS OS Tick API may be used by an RTOS implementation to be easily portable across the different Cortex-M and Cortex-A processors.\nIt provides a generic interface to a kernel system tick timer and defines the following functions:\n\n - The Reference for \\ref CMSIS_RTOS_TickAPI provides details about these functions:\n   - \\ref OS_Tick_Setup : \\copybrief OS_Tick_Setup\n   - \\ref OS_Tick_Enable : \\copybrief OS_Tick_Enable\n   - \\ref OS_Tick_Disable : \\copybrief OS_Tick_Disable\n   - \\ref OS_Tick_AcknowledgeIRQ : \\copybrief OS_Tick_AcknowledgeIRQ\n   - \\ref OS_Tick_GetIRQn : \\copybrief OS_Tick_GetIRQn\n   - \\ref OS_Tick_GetClock : \\copybrief OS_Tick_GetClock\n   - \\ref OS_Tick_GetInterval : \\copybrief OS_Tick_GetInterval\n   - \\ref OS_Tick_GetCount : \\copybrief OS_Tick_GetCount\n   - \\ref OS_Tick_GetOverflow : \\copybrief OS_Tick_GetOverflow\n\n*/\n\n\n/* ======================================================================================================================== */\n// Group creation for Reference \n/* \n\\addtogroup CMSIS_RTOS1 CMSIS-RTOS API v1\n\\brief This section describes the CMSIS-RTOS API v1. \n\\details \nThe CMSIS-RTOS is a generic API layer that interfaces to an existing RTOS kernel.\n\nCMSIS-RTOS2 provides an translation layer for the\n<a class=\"el\" href=\"../../RTOS/html/index.html\">CMSIS-RTOS API v1</a> that simplifies migration.\n\nRefer to the <a class=\"el\" href=\"../../RTOS/html/modules.html\">Reference</a> guide of the CMSIS-RTOS API v1 for details.\n*/\n\n// Group creation for Reference \n/** \n\\addtogroup CMSIS_RTOS CMSIS-RTOS API v2\n\\brief C interface of \\ref rtos_api2 defined in cmsis_os2.h\n\\details \nThe CMSIS-RTOS2 is a generic API layer that interfaces to an RTOS kernel.\n\nThe complete API interface is defined in the \\ref cmsis_os2_h. When using dynamic memory allocation for objects, source code\nor libraries require no modifications when using on a different CMSIS-RTOS2 implementation.\n\nRefer to \\ref rtos_api2_basics for further details.\n*/\n\n/**\n\\addtogroup CMSIS_RTOS_MemoryMgmt Memory Management\n\\ingroup CMSIS_RTOS\n\\brief Information about memory management possibilities\n\\details\nThe \\ref CMSIS_RTOS offers two options for memory management the user can choose. For object storage one can either use\n - \\ref CMSIS_RTOS_MemoryMgmt_Automatic (fully portable), or\n - \\ref CMSIS_RTOS_MemoryMgmt_Manual (implementation specific).\n \nIn order to affect the memory allocation scheme all RTOS objects that can be created on request, i.e. those having a `osXxxNew`\nfunction, accept an optional `osXxxAttr_t attr` argument on creation. As a rule of thumb the object attributes at least have\nmembers to assign custom control block memory, i.e. `cb_mem` and `cb_size` members. By default, i.e. `attr` is `NULL`\nor `cb_mem` is `NULL`, \\ref CMSIS_RTOS_MemoryMgmt_Automatic is used. Providing a pointer to user memory in `cb_mem` switches\nto \\ref CMSIS_RTOS_MemoryMgmt_Manual.\n\n\\note For detailed information about memory allocation strategies provided in RTX5 refer to \\ref MemoryAllocation.\n\n\\section CMSIS_RTOS_MemoryMgmt_Automatic Automatic Dynamic Allocation\n\nThe automatic allocation is the default and viable for many use-cases. Moreover it is fully portable across different\nimplementations of the \\ref CMSIS_RTOS. The common drawback of dynamic memory allocation is the possibility of memory\nfragmentation and exhaustion. Given that all needed objects are created once upon system initialization and never\ndeleted at runtime this class of runtime failures can be prevented, though.\n\nThe actual allocation strategy used is implementation specific, i.e. whether global heap or preallocated memory pools are used.\n\n<b> Code Example:</b> \n\\code{.c}\n#include \"cmsis_os2.h\"                          // implementation agnostic\n  \nosMutexId_t mutex_id;\nosMutexId_t mutex2_id;\n  \nconst osMutexAttr_t Thread_Mutex_attr = {\n  \"myThreadMutex\",                              // human readable mutex name\n  osMutexRecursive | osMutexPrioInherit,        // attr_bits\n  NULL,                                         // memory for control block (default)\n  0U                                            // size for control block (default)\n};\n  \nvoid CreateMutex (void)  {\n  mutex_id = osMutexNew(NULL);                  // use default values for all attributes\n  mutex2_id = osMutexNew(&Thread_Mutex_attr);   // use attributes from defined structure\n  :\n}\n\\endcode\n\nThe Mutexes in this example are created using automatic memory allocation.\n\n\\section CMSIS_RTOS_MemoryMgmt_Manual Manual User-defined Allocation\n\nOne can get fine grained control over memory allocation by providing user-defined memory.\nThe actual requirements such user-defined memory are implementation specific. Thus one\nneeds to carefully refer to the size and alignment rules of the implementation used, e.g.\nfor RTX see \\ref StaticObjectMemory.\n\n<b> Code Example:</b> \n\\code{.c}\n#include \"rtx_os.h\"                             // implementation specific\n  \nosMutexId_t mutex_id;\n  \nstatic osRtxMutex_t mutex_cb __attribute__((section(\".bss.os.mutex.cb\")));  // Placed on .bss.os.mutex.cb section for RTX5 aware debugging\n  \nconst osMutexAttr_t Thread_Mutex_attr = {\n  \"myThreadMutex\",                              // human readable mutex name\n  osMutexRecursive | osMutexPrioInherit,        // attr_bits\n  &mutex_cb,                                    // memory for control block (user-defined)\n  sizeof(mutex_cb)                              // size for control block (user-defined)\n};\n  \nvoid CreateMutex (void)  {\n  mutex_id = osMutexNew(&Thread_Mutex_attr);    // use attributes from defined structure\n  :\n}\n\\endcode\n\nThe above example uses user-defined memory for the mutex control block. Depending on the actual\nimplementation used one needs to include the specific header file, `rtx_os.h` in this case.\n\n*/\n\n// Group creation for Reference \n/** \n\\addtogroup CMSIS_RTOS CMSIS-RTOS API v2\n\\brief C interface of \\ref rtos_api2 defined in <b>%cmsis_os2.h</b>\n\\details \nThe CMSIS-RTOS2 is a generic API layer that interfaces to an RTOS kernel.\n\nThe complete API interface is defined in the \\ref cmsis_os2_h. When using dynamic memory allocation for objects, source code\nor libraries require no modifications when using on a different CMSIS-RTOS2 implementation.\n\nRefer to \\ref rtos_api2_basics for further details.\n*/\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Event.txt",
    "content": "\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Event Flag Management ====\n/** \n\\addtogroup CMSIS_RTOS_EventFlags Event Flags\n\\ingroup CMSIS_RTOS\n\\brief Synchronize threads using event flags.\n\\details \nThe event flags management functions in CMSIS-RTOS allow you to control or wait for event flags. Each signal has up to 31\nevent flags.\n\nA thread\n- can wait for event flags to be set (using \\ref osEventFlagsWait). Using this function, it enters the\n  \\ref ThreadStates \"BLOCKED\" state.\n- may set one or more flags in any other given thread (using \\ref osEventFlagsSet).\n- may clear its own signals or the signals of other threads (using \\ref osEventFlagsClear).\n\nWhen a thread wakes up and resumes execution, its signal flags are automatically cleared (unless event flags option\n\\ref osFlagsNoClear is specified).\n\n\\note The functions \\ref osEventFlagsSet, \\ref osEventFlagsClear, \\ref osEventFlagsGet, and \\ref osEventFlagsWait can be\ncalled from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note Refer to \\ref eventFlagsConfig for RTX5 configuration options.\n\nWorking with Events\n--------------------\nHere is a simple example that shows how two thread can communicate with each others using event flags:\n\n\\image html simple_signal.png \"Simple event communication\"\n\nThe following steps are required to use event flags:\n-# In the thread that is supposed to send a event with id sig1_id, call the set function:\n\\code\nosDelay(1000U);                                           // wait for 1 second\nosEventFlagsSet(sig1_id, 0x0001U);                        // set the flag 0x0001U for event sig1_id\n\\endcode\n-# In another thread (or threads) that are supposed to wait for the event, call the wait function:\n\\code\nosEventFlagsWait(sig1_id, 0x0001U, NULL, osWaitForever);  // wait forever for any flag\n\\endcode\n\nThe following complete example code can be directly used with the \"CMSIS-RTOS2 main template\" and is also provided as a\nstand-alone template for RTX5:\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *  Event Flags creation & usage\n *---------------------------------------------------------------------------*/\n \n#define FLAGS_MSK1 0x00000001U\n \nosEventFlagsId_t evt_id;                        // event flags id\n \nosThreadId_t tid_Thread_EventSender;            // thread id 1\nosThreadId_t tid_Thread_EventReceiver;          // thread id 2\n \nvoid Thread_EventSender   (void *argument);     // thread function 1\nvoid Thread_EventReceiver (void *argument);     // thread function 2\n \nint Init_Events (void) {\n \n  evt_id = osEventFlagsNew(NULL);\n  if (evt_id == NULL) {\n    ; // Event Flags object not created, handle failure\n  }\n \n  tid_Thread_EventSender = osThreadNew(Thread_EventSender, NULL, NULL);\n  if (tid_Thread_EventSender == NULL) {\n    return(-1);\n  }\n  tid_Thread_EventReceiver = osThreadNew(Thread_EventReceiver, NULL, NULL);\n  if (tid_Thread_EventReceiver == NULL) {\n    return(-1);\n  }\n\n  return(0);\n}\n \nvoid Thread_EventSender (void *argument) {\n \n  while (1) {    \n    osEventFlagsSet(evt_id, FLAGS_MSK1);\n    osThreadYield();                            // suspend thread\n  }\n}\n \nvoid Thread_EventReceiver (void *argument) {\n  uint32_t flags;\n \n  while (1) {\n    flags = osEventFlagsWait(evt_id, FLAGS_MSK1, osFlagsWaitAny, osWaitForever);\n    //handle event\n  }\n}\n\\endcode\n\n\n@{\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\typedef osEventFlagsId_t \n\\details\nReturned by:\n- \\ref osEventFlagsNew\n*/ \n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\struct osEventFlagsAttr_t \n\\details\nAttributes to configure an event flag set.\n\nRefer to \\ref CMSIS_RTOS_MemoryMgmt for details about usage of\n - osEventFlagsAttr_t::cb_mem\n - osEventFlagsAttr_t::cb_size\n*/ \n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr)\n\\details\nThe function \\b osEventFlagsNew creates a new event flags object that is used to send events across threads and returns the\npointer to the event flags object identifier or \\token{NULL} in case of an error. It can be safely called before the RTOS is\nstarted (call to \\ref osKernelStart), but not before it is initialized (call to \\ref osKernelInitialize).\n\nThe parameter \\a attr sets the event flags attributes (refer to \\ref osEventFlagsAttr_t).  Default attributes will be used if\nset to \\token{NULL}, i.e. kernel memory allocation is used for the event control block.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \nosEventFlagsId_t evt_id;                        // message queue id\n \nint Init_Events (void) {\n \n  evt_id = osEventFlagsNew(NULL);\n  if (evt_id == NULL) {\n    ; // Event Flags object not created, handle failure\n    return(-1);\n  }\n\n  return(0);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags)\n\\details\nThe function \\b osEventFlagsSet sets the event flags specified by the parameter \\a flags in an event flags object specified\nby parameter \\a ef_id. \n\nThe threads with highest priority waiting for the flag(s) set will be notified to resume from \\ref ThreadStates \"BLOCKED\" state.\nThe function returns the event flags stored in the event control block or an error code (highest bit is set, refer to\n\\ref flags_error_codes). Further threads may be wakened in priority order when the option \\b osFlagsNoClear is given to the\n\\ref osEventFlagsWait call.\n\nPossible \\ref flags_error_codes return values:\n    - \\em osFlagsErrorUnknown: unspecified error.\n    - \\em osFlagsErrorParameter: parameter \\a ef_id does not identify a valid event flags object or \\em flags has highest bit set. \n    - \\em osFlagsErrorResource: the event flags object is in an invalid state.\n    - \\em osFlagsErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified event flags object.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \nosEventFlagsId_t evt_id;                        // event flags id\n \nvoid Thread_EventSender (void *argument) {\n \n  while (1) {    \n    osEventFlagsSet(evt_id, 0x00000001U);\n    osThreadYield();                            // suspend thread\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags)\n\\details\nThe function \\b osEventFlagsClear clears the event flags specified by the parameter \\a flags in an event flags object\nspecified by parameter \\a ef_id. The function returns the event flags before clearing or an error code (highest bit is set, \nrefer to \\ref flags_error_codes).\n\nPossible \\ref flags_error_codes return values:\n    - \\em osFlagsErrorUnknown: unspecified error.\n    - \\em osFlagsErrorParameter: parameter \\a ef_id does not identify a valid event flags object or \\em flags has highest bit set. \n    - \\em osFlagsErrorResource: the event flags object is in an invalid state.\n    - \\em osFlagsErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified event flags object.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osEventFlagsGet (osEventFlagsId_t ef_id)\n\\details\nThe function \\b osEventFlagsGet returns the event flags currently set in an event flags object specified by parameter\n\\a ef_id or \\token{0} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout)\n\\details\nThe function \\b osEventFlagsWait suspends the execution of the currently \\ref ThreadStates \"RUNNING\" thread until any or all event flags\nspecified by the parameter \\a flags in the event object specified by parameter \\a ef_id are set. When these event flags are\nalready set, the function returns instantly. Otherwise, the thread is put into the state \\ref ThreadStates \"BLOCKED\". \n\nThe \\em options parameter specifies the wait condition:\n|Option              |                                                       |\n|--------------------|-------------------------------------------------------|\n|\\b osFlagsWaitAny   |   Wait for any flag (default).                        |\n|\\b osFlagsWaitAll   |   Wait for all flags.                                 |\n|\\b osFlagsNoClear   |   Do not clear flags which have been specified to wait for.  |\n\nIf \\c osFlagsNoClear is set in the options \\ref osEventFlagsClear can be used to clear flags manually.\n\nThe parameter \\a timeout specifies how long the system waits for event flags. While the system waits, the thread\nthat is calling this function is put into the \\ref ThreadStates \"BLOCKED\" state. The parameter \\ref CMSIS_RTOS_TimeOutValue\n\"timeout\" can have the following values:\n - when \\a timeout is \\token{0}, the function returns instantly (i.e. try semantics).\n - when \\a timeout is set to \\b osWaitForever the function will wait for an infinite time until the event flags become\n   available (i.e. wait semantics).\n - all other values specify a time in kernel ticks for a timeout (i.e. timed-wait semantics).\n\nThe function returns the event flags before clearing or an error code (highest bit is set, refer to \\ref flags_error_codes).\n\nPossible \\ref flags_error_codes return values:\n    - \\em osFlagsErrorUnknown: unspecified error.\n    - \\em osFlagsErrorTimeout: awaited flags have not been set in the given time.\n    - \\em osFlagsErrorResource: awaited flags have not been set when no \\a timeout was specified.\n    - \\em osFlagsErrorParameter: parameter \\a ef_id does not identify a valid event flags object or \\em flags has highest bit set. \n    - \\em osFlagsErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified event flags object.\n\n\\note May be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" if the parameter \\a timeout is set to\n\\token{0}.\n\n\\b Code \\b Example\n\\code\n#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \nosEventFlagsId_t evt_id;                        // event flags id\n \nvoid Thread_EventReceiver (void *argument) {\n  uint32_t flags;\n \n  while (1) {\n    flags = osEventFlagsWait(evt_id, 0x00000001U, osFlagsWaitAny, osWaitForever);\n    //handle event\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id)\n\\details\nThe function \\b osEventFlagsDelete deletes the event flags object specified by parameter \\a ef_id and releases the internal\nmemory obtained for the event flags handling. After this call, the \\em ef_id is no longer valid and cannot be used. This can\ncause starvation of threads that are waiting for flags of this event object. The \\em ef_id may be created again using the\nfunction \\ref osEventFlagsNew.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the specified event flags object has been deleted.\n - \\em osErrorISR: \\b osEventFlagsDelete cannot be called from interrupt service routines.\n - \\em osErrorParameter: parameter \\a ef_id is \\token{NULL} or invalid.\n - \\em osErrorResource: the event flags object is in an invalid state.\n - \\em osFlagsErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified event flags object.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn const char *osEventFlagsGetName (osEventFlagsId_t ef_id)\n\\details\nThe function \\b osEventFlagsGetName returns the pointer to the name string of the event flags object identified by parameter\n\\a ef_id or \\token{NULL} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \nosEventFlagsId_t evt_id;                        // event flasg id\n \nvoid EvtFlagsGetName_example (void)  {\n  char *name;\n   \n  name = osEventFlagsGetName(evt_id);\n  if (name == NULL) {\n    // Failed to get the event flags object name\n  }\n}\n\\endcode\n*/\n\n/// @}\n\n// these struct members must stay outside the group to avoid double entries in documentation\n/**\n\\var osEventFlagsAttr_t::attr_bits\n\\details\nReserved for future use (must be set to '0' for future compatibility).\n\n\\var osEventFlagsAttr_t::cb_mem\n\\details\nPointer to a memory for the event flag control block object. Refer to \\ref StaticObjectMemory for more information.\n\nDefault: \\token{NULL} to use \\ref CMSIS_RTOS_MemoryMgmt_Automatic for the event flag control block.\n\n\\var osEventFlagsAttr_t::cb_size\n\\details\nThe size (in bytes) of memory block passed with \\ref cb_mem. For RTX, the minimum value is defined with \\ref osRtxEventFlagsCbSize (higher values are permitted).\n\nDefault: \\token{0} as the default is no memory provided with \\ref cb_mem.\n\n\\var osEventFlagsAttr_t::name\n\\details\nPointer to a constant string with a human readable name (displayed during debugging) of the event flag object.\n\nDefault: \\token{NULL} no name specified.\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Kernel.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Kernel Control ====\n/** \n\\addtogroup CMSIS_RTOS_KernelCtrl Kernel Information and Control\n\\ingroup CMSIS_RTOS\n\\brief Provides version/system information and starts/controls the RTOS Kernel.\n\\details \nThe kernel Information and Control function group allows to:\n  - obtain information about the system and the underlying kernel.\n  - obtain version information about the CMSIS-RTOS API.\n  - initialize of the RTOS kernel for creating objects.\n  - start the RTOS kernel and thread switching.\n  - check the execution status of the RTOS kernel.\n\n\\note The kernel information and control functions cannot be called from\n\\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note The kernel initialization for RTX5 is documented in \\ref SystemStartup.\n\n<b>Code Example</b>\n\\code\n/*----------------------------------------------------------------------------\n * Application main thread\n *---------------------------------------------------------------------------*/\nvoid app_main (void *argument) {\n \n  // ...\n  for (;;) {}\n}\n \nint main (void) {\n \n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n \n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  osKernelStart();                      // Start thread execution\n  for (;;) {}\n}\n\\endcode\n@{\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\struct osVersion_t\n\\details\nIdentifies the underlying RTOS kernel and API version number. The version is represented in a combined decimal number in the\nformat: major.minor.rev: mmnnnrrrr \n\nUse \\ref osKernelGetInfo to retrieve the version numbers.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\enum osKernelState_t\n\\details\nState of the kernel as retrieved by \\ref osKernelGetState. In case \\b osKernelGetState fails or if it is called from an ISR,\nit will return \\c osKernelError, otherwise it returns the kernel state.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osKernelInitialize (void)\n\\details\nThe function \\b osKernelInitialize initializes the RTOS Kernel. Before it is successfully executed, only the functions\n\\ref osKernelGetInfo and \\ref osKernelGetState may be called.\n \nPossible \\ref osStatus_t return values:\n- \\em osOK in case of success.\n- \\em osError if an unspecific error occurred.\n- \\em osErrorISR if called from an \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routine\".\n- \\em osErrorNoMemory if no memory could be reserved for the operation.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b> Code Example</b>\n\\code\n#include \"RTE_Components.h\"\n#include  CMSIS_device_header\n#include \"cmsis_os2.h\"\n \n/*----------------------------------------------------------------------------\n * Application main thread\n *---------------------------------------------------------------------------*/\nvoid app_main (void *argument) {\n \n  // ...\n  for (;;) {}\n}\n \nint main (void) {\n \n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n \n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  osKernelStart();                      // Start thread execution\n  for (;;) {}\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size)\n\\details\nThe function \\b  osKernelGetInfo retrieves the API and kernel version of the underlying RTOS kernel and a human readable\nidentifier string for the kernel. It can be safely called before the RTOS is initialized or started (call to\n\\ref osKernelInitialize or \\ref osKernelStart).\n\nPossible \\ref osStatus_t return values:\n- \\em osOK in case of success.\n- \\em osError if an unspecific error occurred.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\nvoid info (void) {\n  char infobuf[100];\n  osVersion_t osv;\n  osStatus_t status;\n \n  status = osKernelGetInfo(&osv, infobuf, sizeof(infobuf));\n  if(status == osOK) {\n    printf(\"Kernel Information: %s\\r\\n\", infobuf);\n    printf(\"Kernel Version    : %d\\r\\n\", osv.kernel);\n    printf(\"Kernel API Version: %d\\r\\n\", osv.api);\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osKernelState_t osKernelGetState (void)\n\\details\nThe function \\b osKernelGetState returns the current state of the kernel and can be safely called before the RTOS is\ninitialized or started (call to \\ref osKernelInitialize or \\ref osKernelStart). In case it fails it will return \\c osKernelError,\notherwise it returns the kernel state (refer to \\ref osKernelState_t for the list of kernel states).\n\nPossible \\ref osKernelState_t return values:\n- \\ref osKernelError if an unspecific error occurred.\n- the actual kernel state otherwise.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\nint main (void) {\n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n  if(osKernelGetState() == osKernelInactive) {     // Is the kernel initialized?\n     osKernelInitialize();                         // Initialize CMSIS-RTOS kernel\n  }\n  ;\n}\n\\endcode\n\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osKernelStart (void)\n\\details\nThe function \\b osKernelStart starts the RTOS kernel and begins thread switching. It will not return to its calling function\nin case of success. Before it is successfully executed, only the functions \\ref osKernelGetInfo, \\ref osKernelGetState, and\nobject creation functions (\\b osXxxNew) may be called.\n\nAt least one initial thread should be created prior osKernelStart, see \\ref osThreadNew.\n\nPossible \\ref osStatus_t return values:\n- \\em osError if an unspecific error occurred.\n- \\em osErrorISR if called from an \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routine\".\n \n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\nint main (void) {\n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n  if(osKernelGetState() == osKernelInactive) {\n    osKernelInitialize();\n  }\n  ; // ... Start Threads\n  if (osKernelGetState() == osKernelReady) {        // If kernel is ready to run...\n    osKernelStart();                                // ... start thread execution\n    }\n  \n  while(1);                                         // only reached in case of error\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t osKernelLock (void)\n\\details\nThe function \\b osKernelLock allows to lock all task switches. It returns the previous value of the lock state (\\token{1} if\nit was locked, \\token{0} if it was unlocked), or a negative number representing an error code otherwise (refer to\n\\ref osStatus_t).\n\nPossible \\ref osStatus_t return values:\n- \\em osError if an unspecific error occurred.\n- \\em osErrorISR if called from an \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routine\".\n- \\em osErrorSafetyClass if the calling thread safety class is lower than the kernel protect safety class.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n  int32_t state = osKernelLock();\n  // ... critical code\n  osKernelRestore(state);\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t osKernelUnlock (void)\n\\details\nThe function \\b osKernelUnlock resumes from \\ref osKernelLock. It returns the previous value of the lock state (\\token{1} if\nit was locked, \\token{0} if it was unlocked), or a negative number representing an error code otherwise (refer to\n\\ref osStatus_t).\n\nPossible \\ref osStatus_t return values:\n- \\em osError if an unspecific error occurred.\n- \\em osErrorISR if called from an \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routine\".\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n  int32_t sl = osKernelLock();\n  // ... critical code\n  {\n    int32_t su = osKernelUnlock();\n    // ... uncritical code\n    osKernelRestoreLock(su);\n  }\n  // ... critical code\n  osKernelRestoreLock(sl);\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t osKernelRestoreLock (int32_t lock)\n\\details\nThe function \\b osKernelRestoreLock restores the previous lock state after \\ref osKernelLock or \\ref osKernelUnlock.\n\nThe argument \\a lock specifies the lock state as obtained by \\ref osKernelLock or \\ref osKernelUnlock.\n\nThe function returns the new value of the lock state (\\token{1} if it was locked, \\token{0} if it was unlocked), or a\nnegative number representing an error code otherwise (refer to \\ref osStatus_t).\n\nPossible \\ref osStatus_t return values:\n- \\em osError if an unspecific error occurred.\n- \\em osErrorISR if called from interrupt other than fault or \\ref osWatchdogAlarm_Handler.\n- \\em osErrorSafetyClass if the calling thread safety class is lower than the kernel protect safety class.\n\n<b>Code Example</b>\n\\code\n  int32_t sl = osKernelLock();\n  // ... critical code\n  {\n    int32_t su = osKernelUnlock();\n    // ... uncritical code\n    osKernelRestoreLock(su);\n  }\n  // ... critical code\n  osKernelRestoreLock(sl);\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osKernelSuspend (void)\n\\details\nCMSIS-RTOS provides extension for tick-less operation which is useful for applications that use extensively low-power modes\nwhere the SysTick timer is also disabled. To provide a time-tick in such power-saving modes a wake-up timer is used to derive\ntimer intervals. The function \\b osKernelSuspend suspends the RTX kernel scheduler and thus enables sleep modes.\n\nThe return value can be used to determine the amount of system ticks until the next tick-based kernel event will occur, i.e.\na delayed thread becomes ready again. It is recommended to set up the low power timer to generate a wake-up interrupt based\non this return value.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\nvoid osRtxIdleThread (void) {\n                                               /* The idle thread is running\n                                                  when no other thread is ready\n                                                  to run.                      */\n  unsigned int sleep;\n \n  for (;;) {\n                                               /* HERE: include optional user\n                                                  code to be executed when no\n                                                  task runs.                   */\n    sleep = osKernelSuspend();                 /* Suspend RTX thread scheduler */\n \n    if (sleep) {                               /* How long can we sleep?       */\n                                               /* \"sleep\" is in RTX Timer Ticks\n                                                  which is 1ms in this\n                                                  configuration                */\n       \n                                               /* Setup wake-up e.g. watchdog  */\n \n      __WFE();                                 /* Enter Power-down mode        */\n      \n                                               /* After Wake-up                */\n      sleep = tc;                              /* Adjust with cycles slept     */  \n    }\n \n    osKernelResume(sleep);                     /* Resume thread scheduler      */\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn void osKernelResume (uint32_t sleep_ticks)\n\\details\nCMSIS-RTOS provides extension for tick-less operation which is useful for applications that use extensively low-power modes\nwhere the SysTick timer is also disabled. To provide a time-tick in such power-saving modes a wake-up timer is used to derive\ntimer intervals. The function \\b osKernelResume enables the RTX kernel scheduler and thus wakes up the system from sleep\nmode.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\nvoid osRtxIdleThread (void) {\n                                               /* The idle thread is running\n                                                  when no other thread is ready\n                                                  to run.                      */\n  unsigned int sleep;\n \n  for (;;) {\n                                               /* HERE: include optional user\n                                                  code to be executed when no\n                                                  task runs.                   */\n    sleep = osKernelSuspend();                 /* Suspend RTX thread scheduler */\n \n    if (sleep) {                               /* How long can we sleep?       */\n                                               /* \"sleep\" is in RTX Timer Ticks\n                                                  which is 1ms in this\n                                                  configuration                */\n       \n                                               /* Setup wake-up e.g. watchdog  */\n \n      __WFE();                                 /* Enter Power-down mode        */\n      \n                                               /* After Wake-up                */\n      sleep = tc;                              /* Adjust with cycles slept     */  \n    }\n \n    osKernelResume(sleep);                     /* Resume thread scheduler      */\n  }\n}\n\\endcode\n\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osKernelGetTickCount (void)\n\\details\nThe function \\b osKernelGetTickCount returns the current RTOS kernel tick count.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Thread_1 (void *arg)  {                // Thread function\n  uint32_t tick;\n\n  tick = osKernelGetTickCount();            // retrieve the number of system ticks\n  for (;;) {\n    tick += 1000;                           // delay 1000 ticks periodically\n    osDelayUntil(tick);\n    // ...\n  }\n}\\endcode\n\nDue to the limited value range used for the tick count it may overflow during runtime,\ni.e. after 2<sup>32</sup> ticks which are roughly 49days @ 1ms. Typically one has not to\ntake special care of this unless a monotonic counter is needed. For such a case an additional\n64bit tick counter can be implemented as follows. The given example needs GetTick() called at\nleast twice per tick overflow to work properly.\n\n\\b Code \\b Example\n\\code\nuint64_t GetTick(void) {\n  static uint32_t tick_h = 0U;\n  static uint32_t tick_l = 0U;\n         uint32_t tick;\n\n  tick = osKernelGetTickCount();\n  if (tick < tick_l) {\n    tick_h++;\n  }\n  tick_l = tick;\n\n  return (((uint64_t)tick_h << 32) | tick_l);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osKernelGetTickFreq (void)\n\\details\nThe function \\b osKernelGetTickFreq returns the frequency of the current RTOS kernel tick.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osKernelGetSysTimerCount (void)\n\\details\nThe function \\b osKernelGetSysTimerCount returns the current RTOS kernel system timer as a 32-bit value. \nThe value is a rolling 32-bit counter that is composed of the kernel system interrupt timer value\nand the counter that counts these interrupts (RTOS kernel ticks).\n\nThis function allows the implementation of very short timeout checks below the RTOS tick granularity.\nSuch checks might be required when checking for a busy status in a device or peripheral initialization\nroutine, see code example below.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code{.c}\n#include \"cmsis_os2.h\"\n \nvoid SetupDevice (void)  {\n  uint32_t tick;\n  \n  // Calculating 100us timeout in system timer ticks\n  const uint32_t timeout = 100U * osKernelGetSysTimerFreq() / 1000000u;\n  \n  tick = osKernelGetSysTimerCount();             // get start value of the Kernel system tick\n  Device.Setup ();                               // initialize a device or peripheral\n  do {                                           // poll device busy status for 100 microseconds\n    if (!Device.Busy) break;                     // check if device is correctly initialized\n  } while ((osKernelGetSysTimerCount() - tick) < timeout));\n  if (Device.Busy)  {              \n    ;                                            // in case device still busy, signal error\n  }\n                                                 // start interacting with device\n}\n\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osKernelGetSysTimerFreq (void)\n\\details\nThe function \\b osKernelGetSysTimerFreq returns the frequency of the current RTOS kernel system timer.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osKernelProtect (uint32_t safety_class);\n\\details\nThe function \\b osKernelProtect configures kernel access protection. After its successful execution, only threads with\nsafety class equal or higher than the \\a safety_class specified in the argument can execute kernel control functions.\n- \\ref osKernelLock\n- \\ref osKernelUnlock\n- \\ref osKernelRestoreLock\n- \\ref osKernelSuspend\n- \\ref osKernelResume\n- \\ref osKernelProtect\n\nPossible \\ref osStatus_t return values:\n- \\em osOK in case of success.\n- \\em osErrorParameter if \\a safety_class is invalid.\n- \\em osError if kernel is not in ready or running state.\n- \\em osErrorISR if called from an \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routine\".\n- \\em osErrorSafetyClass if the calling thread safety class is lower than the kernel protect safety class.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example:</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid ProtectKernelControlFunctions (void) {\n  osStatus_t status;\n \n  status = osKernelProtect(4U); // Enable Kernel Control for threads with safety class 4 or higher\n  // verify status value here.\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osKernelDestroyClass (uint32_t safety_class, uint32_t mode);\n\\details\nThe function \\b osKernelDestroyClass destroys RTOS objects based on safety class assignment. \\a safety_class provides the reference safety class value, while \\a mode is considered as a bitmap that additionally specifies the safety classes to be destroyed.\n\nIf \\ref osSafetyWithSameClass is set in \\a mode than the RTOS objects with safety class value equal to \\a safety_class will be destroyed.\n<br>\nIf \\ref osSafetyWithLowerClass is set in \\a mode than the RTOS objects with safety class value lower than \\a safety_class will be destroyed.\n\nPossible \\ref osStatus_t return values:\n- \\em osOK in case of success.\n- \\em osErrorParameter if \\a safety_class is invalid.\n- \\em osErrorResource if no other \\ref ThreadStates \"READY\" thread exists.\n- \\em osErrorISR if called from interrupt other than \\ref osWatchdogAlarm_Handler.\n- \\em osErrorSafetyClass if the calling thread safety class is lower than the kernel protect safety class.\n\n<b>Code Example:</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid DestroyNonCriticalClasses (void) {\n  osStatus_t status;\n \n  status = osKernelDestroyClass(4U, osSafetyWithSameClass | osSafetyWithLowerClass); // Destroy objects with safety class 4 or lower\n  // verify status value here.\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn void osFaultResume (void);\n\\details\nResume normal RTOS operation when exiting exception faults.\n\n<b>Code Example:</b>\n\\code\nvoid HardFault_Handler (void) {\n  __ASM volatile (\n    \"...                          \\n\\t\" // Enter assembly and handle faults\n    \"...                          \\n\\t\"\n    \"ldr  r0,=osFaultResume       \\n\\t\" // Before exiting the handler load and\n    \"bx   r0                      \\n\\t\" // jump to osFaultResume\n  );\n}\n\\endcode\n*/\n\n/// @}\n\n// these struct members must stay outside the group to avoid double entries in documentation\n/**\n\\var osKernelState_t::osKernelInactive\n\\details\nThe kernel is not ready yet. \\ref osKernelInitialize needs to be executed successfully.\n\n\\var osKernelState_t::osKernelReady\n\\details\nThe kernel is not yet running. \\ref osKernelStart transfers the kernel to the running state.\n\n\\var osKernelState_t::osKernelRunning\n\\details\nThe kernel is initialized and running.\n\n\\var osKernelState_t::osKernelLocked\n\\details\nThe kernel was locked with \\ref osKernelLock. The functions \\ref osKernelUnlock or \\ref osKernelRestoreLock unlocks it.\n\n\\var osKernelState_t::osKernelSuspended\n\\details\nThe kernel was suspended using \\ref osKernelSuspend. The function \\ref osKernelResume returns to normal operation.\n\n\\var osKernelState_t::osKernelError\n\\details\nAn error occurred.\n\n\\var osKernelState_t::osKernelReserved\n\\details\nReserved. \n*/\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_MemPool.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Memory Pool Management ====\n/** \n\\addtogroup CMSIS_RTOS_PoolMgmt Memory Pool\n\\ingroup CMSIS_RTOS\n\\brief Manage thread-safe fixed-size blocks of dynamic memory.\n\\details\n\\b Memory \\b Pools are fixed-size blocks of memory that are thread-safe. They operate much faster than the dynamically\nallocated heap and do not suffer from fragmentation. Being thread-safe, they can be accessed from threads and ISRs alike.\n\nA Memory Pool can be seen as a linked list of available (unused) memory blocks of fixed and equal size. Allocating memory\nfrom a pool (using \\ref osMemoryPoolAlloc) simply unchains a block from the list and hands over control to the user. Freeing\nmemory to the pool (using \\ref osMemoryPoolFree) simply rechains the block into the list.\n\n\\image html \"mempool.png\" \"CMSIS-RTOS Memory Pools\"\n\n\\note One must not write to freed block. It is up to the implementation to reuse the memory of unused blocks for internal\ncontrol data, i.e. linked list pointers.\n\n\\b Shared \\b memory is one of the basic models to exchange information between threads. Using memory pools for exchanging\ndata, you can share more complex objects between threads if compared to a \\ref CMSIS_RTOS_Message. Memory pool management\nfunctions are used to define and manage such fixed-sized memory pools.\n\n\\note The functions \\ref osMemoryPoolAlloc, \\ref osMemoryPoolFree, \\ref osMemoryPoolGetCapacity,\n\\ref osMemoryPoolGetBlockSize, \\ref osMemoryPoolGetCount, \\ref osMemoryPoolGetSpace can be called from\n\\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note Refer to \\ref memPoolConfig for RTX5 configuration options.\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\typedef osMemoryPoolId_t\n\\details \nReturned by:\n- \\ref osMemoryPoolNew\n*/\n\n/** \n\\struct osMemoryPoolAttr_t\n\\details\nAttributes to configure a memory pool.\n\nRefer to \\ref CMSIS_RTOS_MemoryMgmt for details about usage of\n - osMemoryPoolAttr_t::cb_mem\n - osMemoryPoolAttr_t::cb_size\n - osMemoryPoolAttr_t::mp_mem\n - osMemoryPoolAttr_t::mp_size\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr)\n\\details\nThe function \\b osMemoryPoolNew creates and initializes a memory pool object and returns the pointer to the memory pool\nobject identifier or \\token{NULL} in case of an error. It can be safely called before the RTOS is\nstarted (call to \\ref osKernelStart), but not before it is initialized (call to \\ref osKernelInitialize).\n\nThe total amount of memory needed is at least <code>block_count * block_size</code>. Memory from the pool can only be\nallocated/freed in fixed portions of \\c block_size.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\n#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *      Memory Pool creation & usage\n *---------------------------------------------------------------------------*/\n \n#define MEMPOOL_OBJECTS 16                      // number of Memory Pool Objects\n \ntypedef struct {                                // object data type\n  uint8_t Buf[32];\n  uint8_t Idx;\n} MEM_BLOCK_t;\n \nosMemoryPoolId_t mpid_MemPool;                  // memory pool id\n \nosThreadId_t tid_Thread_MemPool;                // thread id\n \nvoid Thread_MemPool (void *argument);           // thread function\n \nint Init_MemPool (void) {\n \n  mpid_MemPool = osMemoryPoolNew(MEMPOOL_OBJECTS, sizeof(MEM_BLOCK_t), NULL);\n  if (mpid_MemPool == NULL) {\n    ; // MemPool object not created, handle failure\n  }\n \n  tid_Thread_MemPool = osThreadNew(Thread_MemPool, NULL, NULL);\n  if (tid_Thread_MemPool == NULL) {\n    return(-1);\n  }\n \n  return(0);\n}\n \nvoid Thread_MemPool (void *argument) {\n  MEM_BLOCK_t *pMem;\n  osStatus_t status;\n \n  while (1) {\n    ; // Insert thread code here...\n \n    pMem = (MEM_BLOCK_t *)osMemoryPoolAlloc(mpid_MemPool, 0U);  // get Mem Block\n    if (pMem != NULL) {                                         // Mem Block was available\n      pMem->Buf[0] = 0x55U;                                     // do some work...\n      pMem->Idx    = 0U;\n \n      status = osMemoryPoolFree(mpid_MemPool, pMem);            // free mem block\n      switch (status)  {\n        case osOK:\n          break;\n        case osErrorParameter:\n          break;\n        case osErrorNoMemory:\n          break;\n        default:\n          break;\n      }\n    }\n \n    osThreadYield();                                            // suspend thread\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id)\n\\details\nThe function \\b osMemoryPoolGetName returns the pointer to the name string of the memory pool identified by parameter \\a\nmp_id or \\token{NULL} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout)\n\\details\nThe blocking function \\b osMemoryPoolAlloc allocates the memory pool parameter \\a mp_id and returns a pointer to the address\nof the allocated memory or \\token{0} in case of an error.\n\nThe parameter \\a timeout specifies how long the system waits to allocate the memory. While the system waits, the thread\nthat is calling this function is put into the \\ref ThreadStates \"BLOCKED\" state. The thread will become \\ref ThreadStates \"READY\"\nas soon as at least one block of memory gets available.\n\nThe parameter \\ref CMSIS_RTOS_TimeOutValue \"timeout\" can have the following values:\n - when \\a timeout is \\token{0}, the function returns instantly (i.e. try semantics).\n - when \\a timeout is set to \\b osWaitForever the function will wait for an infinite time until the memory is allocated (i.e. wait semantics).\n - all other values specify a time in kernel ticks for a timeout (i.e. timed-wait semantics).\n\nThe result is the pointer to the memory block allocated, or NULL if no memory is available.\n\n\\note It is in the responsibility of the user to respect the block size, i.e. not access memory beyond the blocks limit.\n \n\\note May be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" if the parameter \\a timeout is set to\n\\token{0}.\n\n\\b Code \\b Example\n\nRefer to \\ref osMemoryPoolNew.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block)\n\\details\nThe function \\b osMemoryPoolFree frees the memory pool block specified by the parameter \\a block in the memory pool object\nspecified by the parameter \\a mp_id. The memory block is put back to the list of available blocks.\n\nIf another thread is waiting for memory to become available the thread is put to \\ref ThreadStates \"READY\" state.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the memory has been freed.\n - \\em osErrorParameter: parameter \\a mp_id is \\token{NULL} or invalid, \\a block points to invalid memory.\n - \\em osErrorResource: the memory pool is in an invalid state.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified memory pool.\n\n\\note \\b osMemoryPoolFree may perform certain checks on the \\a block pointer given. But using \\b osMemoryPoolFree \nwith a pointer other than one received from \\ref osMemoryPoolAlloc has \\b UNPREDICTED behaviour.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\nRefer to \\ref osMemoryPoolNew.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id)\n\\details\nThe function \\b osMemoryPoolGetCapacity returns the maximum number of memory blocks in the memory pool object specified by\nparameter \\a mp_id or \\token{0} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id)\n\\details\nThe function \\b osMemoryPoolGetBlockSize returns the memory block size in bytes in the memory pool object specified by\nparameter \\a mp_id or \\token{0} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id)\n\\details\nThe function \\b osMemoryPoolGetCount returns the number of memory blocks used in the memory pool object specified by\nparameter \\a mp_id or \\token{0} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id)\n\\details\nThe function \\b osMemoryPoolGetSpace returns the number of memory blocks available in the memory pool object specified by\nparameter \\a mp_id or \\token{0} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id)\n\\details\nThe function \\b osMemoryPoolDelete deletes a memory pool object specified by parameter \\a mp_id. It releases internal\nmemory obtained for memory pool handling. After this call, the \\a mp_id is no longer valid and cannot be used. The\nmemory pool may be created again using the function \\ref osMemoryPoolNew.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the memory pool object has been deleted.\n - \\em osErrorParameter: parameter \\a mp_id is \\token{NULL} or invalid.\n - \\em osErrorResource: the memory pool is in an invalid state.\n - \\em osErrorISR: \\b osMemoryPoolDelete cannot be called from interrupt service routines.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified memory pool.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n/// @}\n\n// these struct members must stay outside the group to avoid double entries in documentation\n/**\n\\var osMemoryPoolAttr_t::attr_bits\n\\details\nReserved for future use (set to '0').\\n\nDefault: \\token{0}.\n\n\\var osMemoryPoolAttr_t::cb_mem\n\\details\nPointer to a memory location for the memory pool control block object. This can optionally be used for custom memory management systems.\\n\nDefault: \\token{NULL} (uses kernel memory management).\n\n\\var osMemoryPoolAttr_t::cb_size\n\\details\nThe size of the memory block passed with \\ref cb_mem. Must be the size of a memory pool control block object or larger.\n\n\\var osMemoryPoolAttr_t::name\n\\details\nPointer to a string with a human readable name of the memory pool object.\\n\nDefault: \\token{NULL}.\n\n\\var osMemoryPoolAttr_t::mp_mem\n\\details\nPointer to a memory location for the data of the memory pool object.\\n\nDefault: \\token{NULL}.\n\n\\var osMemoryPoolAttr_t::mp_size\n\\details\nThe size of the memory passed with \\ref mp_mem.\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Message.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Message Queue Management ====\n/** \n@addtogroup CMSIS_RTOS_Message Message Queue\n@ingroup CMSIS_RTOS\n@brief Exchange messages between threads in a FIFO-like operation.\n@details \n\\b Message \\b passing is another basic communication model between threads. In the message passing model, one thread sends\ndata explicitly, while another thread receives it. The operation is more like some kind of I/O rather than a direct access to\ninformation to be shared. In CMSIS-RTOS, this mechanism is called s \\b message \\b queue. The data is passed from one thread\nto another in a FIFO-like operation. Using message queue functions, you can control, send, receive, or wait for messages. The\ndata to be passed can be of integer or pointer type:\n\n\\image html \"MessageQueue.png\" \"CMSIS-RTOS Message Queue\"\n\nCompared to a \\ref CMSIS_RTOS_PoolMgmt, message queues are less efficient in general, but solve a broader range of problems.\nSometimes, threads do not have a common address space or the use of shared memory raises problems, such as mutual exclusion.\n\n\\note The functions \\ref osMessageQueuePut, \\ref osMessageQueueGet, \\ref osMessageQueueGetCapacity,\n\\ref osMessageQueueGetMsgSize, \\ref osMessageQueueGetCount, \\ref osMessageQueueGetSpace can be called from\n\\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note Refer to \\ref msgQueueConfig for RTX5 configuration options.\n@{\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osMessageQueueId_t\n\\details\nReturned by:\n- \\ref osMessageQueueNew\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\struct osMessageQueueAttr_t\n\\details\nSpecifies the following attributes for the \\ref osMessageQueueNew function.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr)\n\\details\nThe function \\ref osMessageQueueNew creates and initializes a  message queue object.\nThe function returns a message queue object identifier or \\token{NULL} in case of an error. \n\nThe function can be called after kernel initialization with \\ref osKernelInitialize. It is possible to \ncreate message queue objects before the RTOS kernel is started with \\ref osKernelStart.\n\nThe total amount of memory required for the message queue data is at least <code>msg_count * msg_size</code>.\nThe \\em msg_size is rounded up to a double even number to ensure 32-bit alignment of the memory blocks.\n\nThe memory blocks allocated from the message queue have a fixed size defined with the parameter \\c msg_size.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\nRefer to \\ref osMessageQueuePut\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn const char *osMessageQueueGetName (osMessageQueueId_t mq_id)\n\\details\nThe function \\b osMessageQueueGetName returns the pointer to the name string of the message queue identified by parameter \\a\nmq_id or \\token{NULL} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout)\n\\details\nThe blocking function \\b osMessageQueuePut puts the message pointed to by \\a msg_ptr into the the message queue specified\nby parameter \\a mq_id. The parameter \\a msg_prio is used to sort message according their priority (higher numbers indicate\na higher priority) on insertion.\n\nThe parameter \\a timeout specifies how long the system waits to put the message into the queue. While the system waits, the\nthread that is calling this function is put into the \\ref ThreadStates \"BLOCKED\" state. The parameter \\ref CMSIS_RTOS_TimeOutValue \"timeout\"\ncan have the following values:\n - when \\a timeout is \\token{0}, the function returns instantly (i.e. try semantics).\n - when \\a timeout is set to \\b osWaitForever the function will wait for an infinite time until the message is delivered (i.e. wait semantics).\n - all other values specify a time in kernel ticks for a timeout (i.e. timed-wait semantics).\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the message has been put into the queue.\n - \\em osErrorTimeout: the message could not be put into the queue in the given time (wait-timed semantics).\n - \\em osErrorResource: not enough space in the queue (try semantics).\n - \\em osErrorParameter: parameter \\em mq_id is \\token{NULL} or invalid, non-zero timeout specified in an ISR.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified message queue.\n\n\\note May be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" if the parameter \\a timeout is set to\n\\token{0}.\n\n<b>Code Example:</b>\n\\code\n#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *      Message Queue creation & usage\n *---------------------------------------------------------------------------*/\n \n#define MSGQUEUE_OBJECTS 16                     // number of Message Queue Objects\n \ntypedef struct {                                // object data type\n  uint8_t Buf[32];\n  uint8_t Idx;\n} MSGQUEUE_OBJ_t;\n \nosMessageQueueId_t mid_MsgQueue;                // message queue id\n \nosThreadId_t tid_Thread_MsgQueue1;              // thread id 1\nosThreadId_t tid_Thread_MsgQueue2;              // thread id 2\n \nvoid Thread_MsgQueue1 (void *argument);         // thread function 1\nvoid Thread_MsgQueue2 (void *argument);         // thread function 2\n \nint Init_MsgQueue (void) {\n \n  mid_MsgQueue = osMessageQueueNew(MSGQUEUE_OBJECTS, sizeof(MSGQUEUE_OBJ_t), NULL);\n  if (mid_MsgQueue == NULL) {\n    ; // Message Queue object not created, handle failure\n  }\n \n  tid_Thread_MsgQueue1 = osThreadNew(Thread_MsgQueue1, NULL, NULL);\n  if (tid_Thread_MsgQueue1 == NULL) {\n    return(-1);\n  }\n  tid_Thread_MsgQueue2 = osThreadNew(Thread_MsgQueue2, NULL, NULL);\n  if (tid_Thread_MsgQueue2 == NULL) {\n    return(-1);\n  }\n \n  return(0);\n}\n \nvoid Thread_MsgQueue1 (void *argument) {\n  MSGQUEUE_OBJ_t msg;\n \n  while (1) {\n    ; // Insert thread code here...\n    msg.Buf[0] = 0x55U;                                         // do some work...\n    msg.Idx    = 0U;\n    osMessageQueuePut(mid_MsgQueue, &msg, 0U, 0U);\n    osThreadYield();                                            // suspend thread\n  }\n}\n \nvoid Thread_MsgQueue2 (void *argument) {\n  MSGQUEUE_OBJ_t msg;\n  osStatus_t status;\n \n  while (1) {\n    ; // Insert thread code here...\n    status = osMessageQueueGet(mid_MsgQueue, &msg, NULL, 0U);   // wait for message\n    if (status == osOK) {\n      ; // process data\n    }\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout)\n\\details\nThe function \\b osMessageQueueGet retrieves a message from the message queue specified by the parameter \\a mq_id and saves it\nto the buffer pointed to by the parameter \\a msg_ptr. The message priority is stored to parameter \\a msg_prio if not token{NULL}.\n\nThe parameter \\a timeout specifies how long the system waits to retrieve the message from the queue. While the system waits,\nthe thread that is calling this function is put into the \\ref ThreadStates \"BLOCKED\" state. The parameter\n\\ref CMSIS_RTOS_TimeOutValue \"timeout\" can have the following values:\n - when \\a timeout is \\token{0}, the function returns instantly (i.e. try semantics).\n - when \\a timeout is set to \\b osWaitForever the function will wait for an infinite time until the message is retrieved (i.e. wait semantics).\n - all other values specify a time in kernel ticks for a timeout (i.e. timed-wait semantics).\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the message has been retrieved from the queue.\n - \\em osErrorTimeout: the message could not be retrieved from the queue in the given time (timed-wait semantics).\n - \\em osErrorResource: nothing to get from the queue (try semantics).\n - \\em osErrorParameter: parameter \\em mq_id is \\token{NULL} or invalid, non-zero timeout specified in an ISR.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified message queue.\n\n\\note May be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" if the parameter \\a timeout is set to\n\\token{0}.\n\n<b>Code Example</b>\n\nRefer to \\ref osMessageQueuePut\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id)\n\\details\nThe function \\b osMessageQueueGetCapacity returns the maximum number of messages in the message queue object specified by\nparameter \\a mq_id or \\token{0} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id)\n\\details\nThe function \\b osMessageQueueGetMsgSize returns the maximum message size in bytes for the message queue object specified by\nparameter \\a mq_id or \\token{0} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id)\n\\details\nThe function \\b osMessageQueueGetCount returns the number of queued messages in the message queue object specified by\nparameter \\a mq_id or \\token{0} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id)\n\\details\nThe function \\b osMessageQueueGetSpace returns the number available slots for messages in the message queue object specified\nby parameter \\a mq_id or \\token{0} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id)\n\\details\nThe function \\b osMessageQueueReset resets the message queue specified by the parameter \\a mq_id.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the message queue has been rest.\n - \\em osErrorParameter: parameter \\em mq_id is \\token{NULL} or invalid.\n - \\em osErrorResource: the message queue is in an invalid state.\n - \\em osErrorISR: \\b osMessageQueueReset cannot be called from interrupt service routines.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified message queue.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id)\n\\details\nThe function \\b osMessageQueueDelete deletes a message queue object specified by parameter \\a mq_id. It releases internal\nmemory obtained for message queue handling. After this call, the \\a mq_id is no longer valid and cannot be used. The\nmessage queue may be created again using the function \\ref osMessageQueueNew.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the message queue object has been deleted.\n - \\em osErrorParameter: parameter \\em mq_id is \\token{NULL} or invalid.\n - \\em osErrorResource: the message queue is in an invalid state.\n - \\em osErrorISR: \\b osMessageQueueDelete cannot be called from interrupt service routines.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified message queue.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n/// @}\n\n// these struct members must stay outside the group to avoid double entries in documentation\n/**\n\\var osMessageQueueAttr_t::attr_bits\n\\details\nReserved for future use (must be set to '0' for future compatibility).\n\n\\var osMessageQueueAttr_t::cb_mem\n\\details\nPointer to a memory for the message queue control block object. Refer to \\ref StaticObjectMemory for more information.\n\nDefault: \\token{NULL} to use \\ref CMSIS_RTOS_MemoryMgmt_Automatic for the message queue control block.\n\n\\var osMessageQueueAttr_t::cb_size\n\\details\nThe size (in bytes) of memory block passed with \\ref cb_mem. For RTX, the minimum value is defined with \\ref osRtxMessageQueueCbSize (higher values are permitted).\n\nDefault: \\token{0} as the default is no memory provided with \\ref cb_mem.\n\n\\var osMessageQueueAttr_t::name\n\\details\nPointer to a constant string with a human readable name (displayed during debugging) of the message queue object.\n\nDefault: \\token{NULL} no name specified.\n\n\\var osMessageQueueAttr_t::mq_mem\n\\details\nPointer to a memory for the message queue data. Refer to \\ref StaticObjectMemory for more information.\n\nDefault: \\token{NULL} to use \\ref CMSIS_RTOS_MemoryMgmt_Automatic for the memory pool data.\n\n\\var osMessageQueueAttr_t::mq_size\n\\details\nThe size (in bytes) of memory block passed with \\ref mq_mem. The minimum memory block size is <code>msg_count * msg_size</code> (parameters of the \\ref osMessageQueueNew function). The \\em msg_size is rounded up to a double even number to ensure 32-bit alignment of the memory blocks.\n\nDefault: 0 as the default is no memory provided with \\ref mq_mem.\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Migration.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page os2Migration Migration from API v1 to API v2\n\nTo use the API version 2 functions follow the steps described in:\n - \\subpage os2MigrationGuide - Steps to migrate from API version 1 to API version 2\n - \\subpage os2MigrationFunctions - List of function differences\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n       Functions \n\\endif\n\\page os2MigrationFunctions Detailed API Function Differences \n\nThis section lists the CMSIS-RTOS API v1 and API v2 functions along with the differences in functionality.\nThe list is sorted alphabetically by API v2 function names and is structured the following way:\n\n  - RTOS API v2 function prototype\n  - RTOS API v1 function prototype that is equivalent or provides similar functionality\n  - Brief description of the RTOS v2 function.\n  - Description of the difference.\n\nThe background color indicates:\n  - <div class=\"new\">Green: New functions in API v2 that are not available in API v1 </div>\n  \n  - <div class=\"mod\">Amber: Functions that are modified or replaced in API v2 compared to API v1 </div>\n  \n  - <div class=\"del\">Red: Functions in API v1 that are deprecated in API v2 </div>\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n       Kernel Information and Control  \n\\endif\n\n\\section mig_kernel Kernel Information and Control\n\n\\div{new}\n\\func{osStatus_t #osKernelGetInfo (osVersion_t* version, char* id_buf, uint32_t id_size)}\n\\none\n\\copybrief{osKernelGetInfo}\nNew function #osKernelGetInfo.\n\\enddiv\n\n\\div{mod} \n\\func{osKernelState_t #osKernelGetState (void)}\n\\func{int32_t &nbsp; &nbsp; &nbsp; &nbsp; osKernelRunning (void)}\n\\copybrief{osKernelGetState}\n - The function \\b osKernelGetState replaces the RTOS v1 function \\b osKernelRunning.\n - Return type changed to \\ref osKernelState_t.\n\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osKernelGetTickCount (void)}\n\\none\n\\copybrief{osKernelGetTickCount}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osKernelGetTickFreq (void)}\n\\none\n\\copybrief{osKernelGetTickFreq}\n - The function \\b osKernelGetTickFreq replaces the RTOS v1 macro \\b osKernelTickMicroSec.\n\n\\enddiv\n\n\\div{mod}\n\\func{uint32_t #osKernelGetSysTimerCount (void)}\n\\func{uint32_t osKernelSysTick (void)}\n\\copybrief{osKernelGetSysTimerCount}\n - The function \\b osKernelGetSysTimerCount replaces the RTOS v1 function \\b osKernelSysTick.\n\n\\enddiv\n\n\\div{new}\n\\func{uint64_t #osKernelGetSysTimerFreq (void)}\n\\none\n\\copybrief{osKernelGetSysTimerFreq}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osKernelInitialize (void)}\n\\func{osStatus &nbsp; osKernelInitialize (void)}\n\\copybrief{osKernelInitialize}\n - Return type changed to \\ref osStatus_t.\n\n\\enddiv\n\n\\div{new}\n\\func{int32_t #osKernelLock (void)}\n\\none\n\\copybrief{osKernelLock}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{int32_t #osKernelUnlock (void)}\n\\none\n\\copybrief{osKernelUnlock}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{void #osKernelRestoreLock (void)}\n\\none\n\\copybrief{osKernelRestoreLock}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osKernelStart (void)}\n\\func{osStatus &nbsp; osKernelStart (void)}\n\\copybrief{osKernelStart}\n - Return type changed to \\ref osStatus_t.\n\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osKernelSuspend (void)}\n\\none\n\\copybrief{osKernelSuspend}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{void #osKernelResume (uint32_t sleep_time)}\n\\none\n\\copybrief{osKernelResume}\nNew function.\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Thread Management  =======\n\\endif \n\n\\section mig_threadMgmt Thread Management\n\n\\div{new}\n\\func{osStatus_t #osThreadDetach (osThreadId_t thread_id)}\n\\none\n\\copybrief{osThreadDetach}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items)}\n\\none\n\\copybrief{osThreadEnumerate}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{__NO_RETURN void #osThreadExit (void)}\n\\none\n\\copybrief{osThreadExit}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osThreadGetCount (osThreadId_t thread_id)}\n\\none\n\\copybrief{osThreadGetCount}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{const char *#osThreadGetName (osThreadId_t thread_id)}\n\\none\n\\copybrief{osThreadGetName}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osThreadId_t #osThreadGetId (void)}\n\\func{osThreadId &nbsp; osThreadGetId (void)}\n\\copybrief{osThreadGetId}\n - Return type changed to #osThreadId_t.\n\n\\enddiv\n\n\\div{mod}\n\\func{osPriority_t #osThreadGetPriority (osThreadId_t thread_id)}\n\\func{osPriority &nbsp; osThreadGetPriority (osThreadId thread_id)}\n\\copybrief{osThreadGetPriority}\n - Return type changed to #osPriority_t. \n - Parameter type changed to #osThreadId_t.\n\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osThreadGetStackSize (osThreadId_t thread_id)}\n\\none\n\\copybrief{osThreadGetStackSize}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osThreadGetStackSpace (osThreadId_t thread_id)}\n\\none\n\\copybrief{osThreadGetStackSpace}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{osThreadState_t #osThreadGetState (osThreadId_t thread_id)}\n\\none\n\\copybrief{osThreadGetState}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{osStatus_t #osThreadJoin (osThreadId_t thread_id)}\n\\none\n\\copybrief{osThreadJoin}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osThreadId_t #osThreadNew (osThreadFunc_t function, void *argument, const osThreadAttr_t *attr)}\n\\func{osThreadId &nbsp; osThreadCreate (const osThreadDef_t *thread_def, void *argument)} \n\\copybrief{osThreadNew}\n - The function \\b osThreadNew replaces the RTOS v1 function \\b osThreadCreate.\n - Options are now passed using a \\ref osThreadAttr_t struct, replacing the \\b osThreadDef macro. \n - New function prototype is <kbd>void func (void *arg)</kbd>, before: <kbd>void func (const void *arg)</kbd>.\n\n\\enddiv\n\n\\div{new}\n\\func{osStatus_t #osThreadResume (osThreadId_t thread_id)}\n\\none\n\\copybrief{osThreadResume}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority)}\n\\func{osStatus &nbsp; osThreadSetPriority (osThreadId thread_id, osPriority priority)}\n\\copybrief{osThreadSetPriority}\n - Return type changed to #osStatus_t. \n - Parameter types changed to #osThreadId_t and #osPriority_t.\n\n\\enddiv\n\n\\div{new}\n\\func{osStatus_t #osThreadSuspend (osThreadId_t thread_id)}\n\\none\n\\copybrief{osThreadSuspend}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osThreadTerminate (osThreadId_t thread_id)}\n\\func{osStatus &nbsp; osThreadTerminate (osThreadId thread_id)}\n\\copybrief{osThreadTerminate}\n - Return type changed to #osStatus_t. \n - Parameter type changed to #osThreadId_t.\n\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osThreadYield (void)}\n\\func{osStatus &nbsp; osThreadYield (void)}\n\\copybrief{osThreadYield}\n - Return type changed to #osStatus_t.\n\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Thread Flags  =======\n\\endif \n\n\\section mig_threadFlags Thread Flags\n\\details\nNew section to synchronize threads using flags. Thread flags and the more flexible \\ref mig_eventFlags are replacing the RTOS v1 <b>Signal Events</b>. Refer to \\ref mig_signalEvents for a list of deprecated functions.\nRefer to \\ref CMSIS_RTOS_ThreadFlagsMgmt for details.\n\n\\div{new}\n\\func{uint32_t #osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags)}\n\\none\n\\copybrief{osThreadFlagsSet}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osThreadFlagsClear (uint32_t flags)}\n\\none\n\\copybrief{osThreadFlagsClear}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osThreadFlagsGet (void)}\n\\none\n\\copybrief{osThreadFlagsGet}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout)}\n\\none\n\\copybrief{osThreadFlagsWait}\nNew function.\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Event Flags  =======\n\\endif \n\n\\section mig_eventFlags Event Flags\n\\details\nNew section to synchronize events using flags. Event flags and thread flags are replacing the RTOS v1 <b>Signal Events</b>.\nAll functions listed in the RTOS v1 <b>Signal Events</b> have been deprecated.\nRefer to \\ref mig_signalEvents for a list of deprecated functions.\nRefer to \\ref CMSIS_RTOS_EventFlags for details about the new function.\n\n\\div{new}\n\\func{uint32_t #osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags)}\n\\none\n\\copybrief{osEventFlagsClear}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{const char *#osEventFlagsGetName (osEventFlagsId_t ef_id)}\n\\none\n\\copybrief{osEventFlagsGetName}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{osStatus_t #osEventFlagsDelete (osEventFlagsId_t ef_id)}\n\\none\n\\copybrief{osEventFlagsDelete}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osEventFlagsGet (osEventFlagsId_t ef_id)}\n\\none\n\\copybrief{osEventFlagsGet}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{osEventFlagsId_t #osEventFlagsNew (const osEventFlagsAttr_t *attr)}\n\\none\n\\copybrief{osEventFlagsNew}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags)}\n\\none\n\\copybrief{osEventFlagsSet}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout)}\n\\none\n\\copybrief{osEventFlagsWait}\nNew function.\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Generic Wait Functions  =======\n\\endif\n\n\\section mig_wait Generic Wait Functions\n\\details\nRefer to \\ref CMSIS_RTOS_Wait for details.\n\n\\div{mod}\n\\func{osStatus_t #osDelay (uint32_t ticks)}\n\\func{osStatus &nbsp; osDelay (uint32_t timeout)}\n\\copybrief{osDelay}\n - The return type changed to #osStatus_t. \n \n\\enddiv\n\n\\div{new}\n\\func{osStatus_t #osDelayUntil (uint32_t ticks)}\n\\none\n\\copybrief{osDelayUntil}\nNew function.\n\\enddiv\n\n\\div{del}\n\\none\n\\func{osEvent osWait (uint32_t millisec)}\n\\n\nDeprecated.\n\\enddiv\n\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Timer Management  =======\n\\endif\n\n\\section mig_timer Timer Management\n\\details\nRefer to \\ref CMSIS_RTOS_TimerMgmt for details.\n\n\\div{mod}\n\\func{osStatus_t #osTimerDelete (osTimerId_t timer_id)}\n\\func{osStatus &nbsp; osTimerDelete (osTimerId timer_id)}\n\\copybrief{osTimerDelete}\n - The return type changed to #osStatus_t. \n - The parameter type has changed to #osTimerId_t.\n\n\\enddiv\n\n\\div{new}\n\\func{const char *#osTimerGetName (osTimerId_t timer_id)}\n\\none\n\\copybrief{osTimerGetName}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osTimerIsRunning (osTimerId_t timer_id)}\n\\none\n\\copybrief{osTimerIsRunning}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osTimerId_t #osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr)}\n\\func{osTimerId &nbsp; osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument)}\n\\copybrief{osTimerNew}\n - The function \\b osTimerNew replaces the RTOS v1 function \\b osTimerCreate.\n - The return type changed to #osTimerId_t. \n - The parameter list and types have changed.\n\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osTimerStart (osTimerId_t timer_id, uint32_t ticks)}\n\\func{osStatus &nbsp; osTimerStart (osTimerId timer_id, uint32_t timeout)}\n\\copybrief{osTimerStart}\n - The return type changed to #osStatus_t. \n - The first parameter type has changed to #osTimerId_t.\n\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osTimerStop (osTimerId_t timer_id)}\n\\func{osStatus &nbsp; osTimerStop (osTimerId timer_id)}\n\\copybrief{osTimerStop}\n - The return type changed to #osStatus_t. \n - The parameter type has changed to #osTimerId_t.\n\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Mutexes  =======\n\\endif\n\n\\section mig_mutex Mutexes\nRefer to \\ref CMSIS_RTOS_MutexMgmt for details.\n\n\\div{mod}\n\\func{osStatus_t #osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout)}\n\\func{osStatus &nbsp; osMutexWait (osMutexId mutex_id, uint32_t timeout)}\n\\copybrief{osMutexAcquire}\n - The function \\b osMutexAcquire replaces the RTOS v1 function \\b osMutexWait.\n - Return type changed to \\ref osStatus_t. \n - First parameter type changed to \\ref osMutexId_t.\n\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osMutexDelete (osMutexId_t mutex_id)}\n\\func{osStatus &nbsp; osMutexDelete (osMutexId mutex_id)}\n\\copybrief{osMutexDelete}\n - The return type changed to \\ref osStatus_t. \n - The parameter type changed to \\ref osMutexId_t.\n\n\\enddiv\n\n\\div{new}\n\\func{const char *#osMutexGetName (osMutexId_t mutex_id)}\n\\none\n\\copybrief{osMutexGetName}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{osThreadId_t #osMutexGetOwner (osMutexId_t mutex_id)}\n\\none\n\\copybrief{osMutexGetOwner}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osMutexId_t #osMutexNew (const osMutexAttr_t *attr)}\n\\func{osMutexId &nbsp; osMutexCreate (const osMutexDef_t *mutex_def)}\n\\copybrief{osMutexNew}\n - The function \\b osMutexNew replaces the RTOS v1 function \\b osMutexCreate.\n - The return type changed to \\ref osMutexId_t. \n - The parameter type changed to \\ref osMutexAttr_t.\n\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osMutexRelease (osMutexId_t mutex_id)}\n\\func{osStatus &nbsp; osMutexRelease (osMutexId mutex_id)}\n\\copybrief{osMutexRelease}\n - The return type changed to \\ref osStatus_t. \n - The parameter type changed to \\ref osMutexId_t.\n\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  SEMAPHORES  =======\n\\endif\n\n\\section mig_sem Semaphores\nRefer to \\ref CMSIS_RTOS_SemaphoreMgmt for details.\n\n\\div{new}\n\\func{osStatus_t #osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout)}\n\\none\n\\copybrief{osSemaphoreAcquire}\nNew function. Replaces \\c osSemaphoreWait.\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osSemaphoreDelete (osSemaphoreId_t semaphore_id)}\n\\func{osStatus &nbsp; osSemaphoreDelete (osSemaphoreId semaphore_id)}\n\\copybrief{osSemaphoreDelete}\n - The return type changed to #osStatus_t. \n - The parameter type has changed to #osSemaphoreId_t.\n\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osSemaphoreGetCount (osSemaphoreId_t semaphore_id)}\n\\none\n\\copybrief{osSemaphoreGetCount}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{const char *#osSemaphoreGetName (osSemaphoreId_t semaphore_id)}\n\\none\n\\copybrief{osSemaphoreGetName}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osSemaphoreId_t #osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr)}\n\\func{osSemaphoreId &nbsp; osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)}\n\\copybrief{osSemaphoreNew}\n - The function \\b osSemaphoreNew replaces the RTOS v1 function \\b osSemaphoreCreate.\n - The return type changed to #osSemaphoreId_t. \n - The parameter list and types have changed.\n\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osSemaphoreRelease (osSemaphoreId_t semaphore_id)}\n\\func{osStatus &nbsp; osSemaphoreRelease (osSemaphoreId semaphore_id)}\n\\copybrief{osSemaphoreRelease}\n - The return type changed to #osStatus_t. \n - The parameter type has changed to #osSemaphoreId_t.\n\n\\enddiv\n\n\\div{del}\n\\none\n\\func{int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t timeout)}\n\\n\nDeprecated. Replaced by #osSemaphoreAcquire.\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Memory Pool  =======\n\\endif\n\n\\section mig_memPool Memory Pool\n\n\\div{mod}\n\\func{void * #osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout)}\n\\func{void * osPoolAlloc &nbsp;(osPoolId pool_id)} \n\\copybrief{osMemoryPoolAlloc}\n - The function \\b osMemoryPoolAlloc replaces both RTOS v1 functions \\b osPoolAlloc.\n - The parameter list and types changed.\n\n\\enddiv\n\n\\div{new}\n\\func{osStatus_t #osMemoryPoolDelete (osMemoryPoolId_t mp_id)}\n\\none\n\\copybrief{osMemoryPoolDelete}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osMemoryPoolFree (osMemoryPoolId_t mp_id, void * block)}\n\\func{osStatus &nbsp; osPoolFree (osPoolId pool_id, void * block)} \n\\copybrief{osMemoryPoolFree}\n - The function \\b osMemoryPoolFree replaces the RTOS v1 function \\b osPoolFree.\n - The first parameter type \\b osMemoryPoolId_t replaces the ROTS v1 type \\b osPoolId.\n\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id)}\n\\none\n\\copybrief{osMemoryPoolGetBlockSize}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id)}\n\\none\n\\copybrief{osMemoryPoolGetCapacity}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osMemoryPoolGetCount (osMemoryPoolId_t mp_id)}\n\\none\n\\copybrief{osMemoryPoolGetCount}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{const char *#osMemoryPoolGetName (osMemoryPoolId_t mp_id)}\n\\none\n\\copybrief{osMemoryPoolGetName}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osMemoryPoolGetSpace (osMemoryPoolId_t mp_id)}\n\\none\n\\copybrief{osMemoryPoolGetSpace}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osMemoryPoolId_t #osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr)}\n\\func{osPoolId &nbsp; &nbsp; &nbsp; &nbsp; osPoolCreate (const osPoolDef_t * pool_def)}\n\\copybrief{osMemoryPoolGetSpace}\n - The function \\b osMemoryPoolNew replaces the RTOS v1 function \\b osPoolCreate. \n - The return type changed to #osMemoryPoolId_t.\n - Parameter list and parameter types have changed.\n\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Message Queue  =======\n\\endif\n\n\\section mig_msgQueue Message Queue\nIn general, messages are now using fixed size memory instead of being 32-bit values. Refer to \\ref CMSIS_RTOS_Message for\ndetails. \n\n\\div{new}\n\\func{osStatus_t #osMessageQueueDelete (osMessageQueueId_t mq_id)}\n\\none\n\\copybrief{osMessageQueueDelete}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout)}\n\\func{osEvent &nbsp;&nbsp; osMessageGet (osMessageQId queue_id, uint32_t timeout)}\n\\copybrief{osMessageQueueGet}\n - The function \\b osMessageQueueGet replaces the RTOS v1 function \\b osMessageGet.\n - The return type changed to #osStatus_t. \n - The parameter list and parameter types have changed. \n\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osMessageQueueGetCapacity (osMessageQueueId_t mq_id)}\n\\none\n\\copybrief{osMessageQueueGetCapacity}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osMessageQueueGetCount (osMessageQueueId_t mq_id)}\n\\none\n\\copybrief{osMessageQueueGetCount}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osMessageQueueGetMsgSize (osMessageQueueId_t mq_id)}\n\\none\n\\copybrief{osMessageQueueGetMsgSize}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{const char *#osMessageQueueGetName (osMessageQueueId_t mq_id)}\n\\none\n\\copybrief{osMessageQueueGetName}\nNew function.\n\\enddiv\n\n\\div{new}\n\\func{uint32_t #osMessageQueueGetSpace (osMessageQueueId_t mq_id)}\n\\none\n\\copybrief{osMessageQueueGetSpace}\nNew function.\n\\enddiv\n\n\\div{mod}\n\\func{osMessageQueueId_t #osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr)}\n\\func{osMessageQId &nbsp; &nbsp; &nbsp; osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)}\n\\copybrief{osMessageQueueNew}\n - The function \\b osMessageQueueNew replaces the RTOS v1 function \\b osMessageCreate.\n - The return type changed to #osMessageQueueId_t. \n - The parameter list and parameter types have changed. \n\n\\enddiv\n\n\\div{mod}\n\\func{osStatus_t #osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout)}\n\\func{osStatus &nbsp; osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t timeout)}\n\\copybrief{osMessageQueuePut}\n - The function \\b osMessageQueuePut replaces the RTOS v1 function \\b osMessagePut.\n - The return type changed to #osStatus_t. \n - The parameter list and parameter types have changed. \n\n\\enddiv\n\n\\div{new}\n\\func{osStatus_t #osMessageQueueReset (osMessageQueueId_t mq_id)}\n\\none\n\\copybrief{osMessageQueueReset}\nNew function.\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Mail Queue  =======\n\\endif\n\n\\section mig_mailQueue Mail Queue\nThe <b>Mail Queue</b> RTOS v1 functions have been deprecated.\nUse the functionality of the \\ref CMSIS_RTOS_Message instead. \nDifferences are listed under \\ref mig_msgQueue.\n\n\\div{del}\n\\none\n\\func{void * osMailAlloc (osMailQId queue_id, uint32_t timeout)}\n\\n\nDeprecated.\n\\enddiv\n\n\\div{del}\n\\none\n\\func{void * osMailCAlloc (osMailQId queue_id, uint32_t timeout)}\n\\n\nDeprecated.\n\\enddiv\n\n\\div{del}\n\\none\n\\func{osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id)}\n\\n\nDeprecated.\n\\enddiv\n\n\\div{del}\n\\none\n\\func{osStatus osMailFree (osMailQId queue_id, void *mail)}\n\\n\nDeprecated.\n\\enddiv\n\n\\div{del}\n\\none\n\\func{osEvent osMailGet (osMailQId queue_id, uint32_t timeout)}\n\\n\nDeprecated.\n\\enddiv\n\n\\div{del}\n\\none\n\\func{osStatus osMailPut (osMailQId queue_id, void *mail)}\n\\n\nDeprecated.\n\\enddiv\n\n\n\\if NEVER_ENABLE\n=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====\n======  Signal Events  =======\n\\endif\n\n\\section mig_signalEvents Signal Events\n\\details\nThe section RTOS v1 <b>Signal Events</b> has been deprecated. Use the functions listed under \\ref mig_threadFlags instead.\n\n\\div{del}\n\\none\n\\func{int32_t osSignalClear (osThreadId thread_id, int32_t signals)}\n\\n\nDeprecated.\n\\enddiv\n\n\\div{del}\n\\none\n\\func{int32_t osSignalSet (osThreadId thread_id, int32_t signals)}\n\\n\nDeprecated.\n\\enddiv\n\n\\div{del}\n\\none\n\\func{osEvent osSignalWait (int32_t signals, uint32_t timeout)}\n\\n\nDeprecated.\n\\enddiv\n*/"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_MigrationGuide.txt",
    "content": "\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page os2MigrationGuide RTX Migration Guide\n\nRTX5 supplies both API layers: CMSIS-RTOS v1 and CMSIS-RTOS v2. This allows a gradient transition from version 1 to 2. A\nmodified v1 header and a special v1 compatibility module enable existing code to run on a v2 implementation with almost no\nmodifications.\n\nOnly a few incompatibilities and limitations exist:\n- Kernel startup\\n\n  - The function \\c osKernelRunning has been removed in CMSIS-RTOS v2, use osKernelGetState() instead.\n  - Function \\c main was usually a running thread in CMSIS-RTOS v1 implementations, which is not the case in CMSIS-RTOS v2\n    anymore. The Kernel was running even without calling corresponding APIs to initialize and start the Kernel explicitly.\n    In CMSIS-RTOS v2 the Kernel needs be initialized by calling osKernelInitialize() and must be started by calling\n    osKernelStart().\n- OS tick\\n\n  RTX5 uses the \\ref CMSIS_RTOS_TickAPI to configure the tick interrupts. The interval calculation is typically based on\n  \\c SystemCoreClock variable. Thus one has to assure this variable is set correctly before calling \\ref osKernelStart.\n- The function \\c osWait is deprecated.\n- Error code incompatibility\\n\n  CMSIS-RTOS v1 used two different error codes for invalid parameters: \\c osErrorParameter and \\c osErrorValue. The new\n  version only uses a common \\ref osErrorParameter code. Therefore, code relying on osErrorValue is not compatible. The\n  following functions are affected:\n  - \\ref osThreadSetPriority returns \\ref osErrorParameter instead of osErrorValue when priority is out of range\n  - \\ref osMemoryPoolFree (previously \\c osPoolFree) returns \\ref osErrorParameter instead of osErrorValue when block to be\n    returned is invalid\n- The \\ref osDelay return code has changed from osErrorTimeout to \\ref osOK.\n\nThe level of migration depends on the project's phase in its life cycle:\n- The \\ref MigL1 \"first level\" of migration is to migrate to RTX5 without changing the API level.\n- The \\ref MigL2 \"second level\" in the transition is to use v2 API functions and v1 API functions in mixed variation.\n- The \\ref MigL3 \"third level\" is the full transition to the API v2. It is non-trivial and requires some additional\n  development effort to migrate all API v1 calls to v2.\n\n\n\\section MigL1 Level 1 Migration - Upgrade to RTX5 on API v1\n\nUpgrade to RTX Version 5 from any 4.x version using the API v1 compatibility layer. Configure an existing project as follows:\n\n- Open \\b Manage \\b Run-Time \\b Environment window\n- Expand \\b CMSIS software component.\n- Expand \\b RTOS \\b (API), uncheck \\b Keil \\b RTX, and select \\b Keil \\b RTX5.\n- Expand \\b RTOS2 \\b (API) and select \\b Keil \\b RTX5.\n- Resolve missing components.\n\n\\image html \"RTX5_Migrate1.PNG\" \"Component Selection for RTX5\"\n\n- Click OK.\n- Expand \\b CMSIS group in the \\b Project window:\n- Open \\b %RTX_Config.h and adapt the configuration to suit the application including (refer to \\ref config_rtx5):\n  - System Configuration->Global Dynamic Memory size\n  - Kernel Tick Frequency\n  - Thread Configuration->Default Thread Stack size\n- Rename function <tt>int main (void)</tt> to <tt>void app_main (void *arg)</tt>.\n- Create a new function <tt>int main (void)</tt> which implements at least:\n  - System initialization and configuration\n  - Update <a href=\"../../Core/html/group__system__init__gr.html\">SystemCoreClock</a>\n  - Initialize CMSIS-RTOS kernel\n  - Creates new thread app_main\n  - Start RTOS scheduler\n\n<b>Example - Application Main Thread</b>\n\\code\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n \n/* Renamed main() function */\nvoid app_main (void const *argument) {\n  // contents of old \"main\"\n}\n \nosThreadDef(app_main, osPriorityNormal, 1, 0);\n \nint main (void) {\n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n  osKernelInitialize();\n  osThreadCreate(osThread(app_main), NULL);\n  osKernelStart();\n  for (;;);\n}\n\\endcode\n\n\\note In RTOS API v1 all timings were specified in milliseconds. RTX5 defines all times in kernel ticks.\nTo match both it is recommended to set the Kernel Tick Frequency to 1000 Hz in the \\ref systemConfig.\n\nTo validate the correct operation of your RTOS after migration you can temporarily integrate the \\ref rtosValidation\ncomponent into your project.\n\n\n\\section MigL2 Level 2 Migration - Use API v2 and v1 alongside in RTX5\n\nImplementing new features in your project is ideally done using the new API. Both API versions are offered in RTX5 and can\nexist along-side.\n \nThe component selection is identical to Migration Level 1.\n\nInclude \"cmsis_os2.h\" in all modules where access to API v2 functions is required.\n\n\\code\n#include \"cmsis_os.h\"                   // ARM::CMSIS:RTOS:Keil RTX5\n#include \"cmsis_os2.h\"                  // ARM::CMSIS:RTOS2:Keil RTX5\n\\endcode\n\nThe following snippet shows how threads - created with both API versions - live along-side:\n\n\\code\n/*----------------------------------------------------------------------------\n *      Thread 4 'phaseD': Phase D output   - API v2 thread\n *---------------------------------------------------------------------------*/\nvoid phaseD (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On (LED_D);\n    signal_func(tid_phaseA);                                     /* call common signal function   */\n    Switch_Off(LED_D);\n  }\n}\n \n/*----------------------------------------------------------------------------\n *      Thread 5 'clock': Signal Clock  - API v1 thread\n *---------------------------------------------------------------------------*/\nvoid clock (void const *argument) {\n  for (;;) {\n    osSignalWait(0x0100, osWaitForever);    /*  Wait for event send by API v2 function osThreadFlagsSet() */\n    Switch_On (LED_CLK);\n    osDelay(80);                            /* delay ticks                    */\n    Switch_Off(LED_CLK);\n  }\n}\n \n/* Define the API v1 thread */\nosThreadDef(clock,  osPriorityNormal, 1, 0);\n \n/*----------------------------------------------------------------------------\n *      Main: Initialize and start RTX Kernel\n *---------------------------------------------------------------------------*/\nvoid app_main (void *argument) {\n\n  ; //...\n  /* Create the API v2 thread */\n  tid_phaseD = osThreadNew(phaseD, NULL, NULL);\n  /* Create the API v1 thread */\n  tid_clock  = osThreadCreate(osThread(clock),  NULL);\n \n  osThreadFlagsSet(tid_phaseA, 0x0001);          /* set signal to phaseA thread   */\n \n  osDelay(osWaitForever);\n  while(1);\n}\n\\endcode\n \nThe full example \"RTX5 Migration\" is part of the CMSIS5 pack and available from the pack installer.\n\n\n\\section MigL3 Level 3 Migration - Full transition to API v2\nMigrating fully to APIv2 reduces the overhead of the translation layer and simplifies the project.\nThere is some effort to replace and re-test all API Version 1 calls.\nThe following steps are recommended as a rough guide-line:\n- Open Manage Run-Time Environment window:\n- Expand CMSIS Software Component:\n- Expand RTOS (API) Software Component and de-select Keil RTX5\n- Click OK\n- Exchange all occurrences of\n  \\code\n  #include \"cmsis_os.h\"  \n  \\endcode\n  with\n  \\code\n  #include \"cmsis_os2.h\"  \n  \\endcode\n- Identify all references to the API v1 and replace with the appropriate calls in v2. You might want to use the Error List\n  window in uVision to identify the related code passages quickly. \n\n\\note See \\ref os2MigrationFunctions for details in differences.\n\nGenerally there are no longer os*Def macros to declare OS objects. \n\n\\note\n- Signal Events have been replaced. Use the functions listed under Thread Flags and Event Flags instead. \n- The Mail Queue RTOS v1 functions have been deprecated. Use the functionality of the Message Queue instead. Differences are\n  listed under \\ref mig_msgQueue.\n*/\n "
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Mutex.txt",
    "content": "// \n// close group struct osMutexAttr_t\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Mutex Management ====\n/** \n\\addtogroup CMSIS_RTOS_MutexMgmt Mutex Management\n\\ingroup CMSIS_RTOS\n\\brief Synchronize resource access using Mutual Exclusion (Mutex).\n\\details \n<b>Mutual exclusion</b> (widely known as \\b Mutex) is used in various operating systems for resource management. Many\nresources in a microcontroller device can be used repeatedly, but only by one thread at a time (for example communication\nchannels, memory, and files). Mutexes are used to protect access to a shared resource. A mutex is created and then passed\nbetween the threads (they can acquire and release the mutex).\n\n\\image html \"Mutex.png\" \"CMSIS-RTOS Mutex\"\n\nA mutex is a special version of a \\ref CMSIS_RTOS_SemaphoreMgmt \"semaphore\". Like the semaphore, it is a container for\ntokens. But instead of being able to have multiple tokens, a mutex can only carry one (representing the resource). Thus, a\nmutex token is binary and bounded, i.e. it is either \\em available, or \\em blocked by a owning thread. The advantage of a\nmutex is that it introduces thread ownership. When a thread acquires a mutex and becomes its owner, subsequent mutex acquires\nfrom that thread will succeed immediately without any latency (if \\ref osMutexRecursive is specified). Thus, mutex acquires/releases\ncan be nested.\n\n\\image html \"mutex_states.png\" \"CMSIS-RTOS Mutex States\"\n\n\\note Mutex management functions cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" (ISR), unlike a\nbinary semaphore that can be released from an ISR.\n\\note Refer to \\ref mutexConfig for RTX5 configuration options.  \n  \n@{\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osMutexRecursive\n\\details\nRecursive flag in osMutexAttr_t.\n\nThe same thread can consume a mutex multiple times without locking itself.\nEach time the owning thread acquires the mutex the lock count is incremented. The mutex must\nbe released multiple times as well until the lock count reaches zero. At reaching zero the\nmutex is actually released and can be acquired by other threads.\n\n\\note The maximum amount of recursive locks possible is implementation specific, i.e. the type size used for the lock count.\nIf the maximum amount of recursive locks is depleted mutex acquire might fail.\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nosMutexId_t mutex_id; \n \nconst osMutexAttr_t Thread_Mutex_attr = {\n  \"myThreadMutex\",     // human readable mutex name\n  osMutexRecursive,    // attr_bits\n  NULL,                // memory for control block   \n  0U                   // size for control block\n};\n \n// must be called from a thread context\nvoid UseMutexRecursively(int count) {\n  osStatus_t result = osMutexAcquire(mutex_id, osWaitForever);  // lock count is incremented, might fail when lock count is depleted\n  if (result == osOK) {\n    if (count < 10) {\n      UseMutexRecursively(count + 1);\n    }\n    osMutexRelease(mutex_id); // lock count is decremented, actually releases the mutex on lock count zero\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osMutexPrioInherit\n\\details\nPriority inheritance flag in osMutexAttr_t.\n\nA mutex using priority inheritance protocol transfers a waiting threads priority to the\ncurrent mutex owner if the owners thread priority is lower. This assures that a low priority\nthread does not block a high priority thread.\n\nOtherwise a low priority thread might hold a mutex but is not granted execution time due to\nanother mid priority thread. Without priority inheritance the high priority thread waiting\nfor the mutex would be blocked by the mid priority thread, called priority inversion.\n\n<b>Code Example</b>\n\nThis example reveals a blocked high priority thread if \\ref osMutexPrioInherit is removed.\n\n\\code\n#include \"cmsis_os2.h\"\n \nosMutexId_t mutex_id;  \n \nconst osMutexAttr_t Thread_Mutex_attr = {\n  \"myThreadMutex\",     // human readable mutex name\n  osMutexPrioInherit,  // attr_bits\n  NULL,                // memory for control block   \n  0U                   // size for control block\n};\n \nvoid HighPrioThread(void *argument) {\n  osDelay(1000U); // wait 1s until start actual work\n  while(1) {\n    osMutexAcquire(mutex_id, osWaitForever); // try to acquire mutex\n    // do stuff\n    osMutexRelease(mutex_id);\n  }\n}\n \nvoid MidPrioThread(void *argument) {\n  osDelay(1000U); // wait 1s until start actual work\n  while(1) {\n    // do non blocking stuff\n  }\n}\n \nvoid LowPrioThread(void *argument) {\n  while(1) {\n    osMutexAcquire(mutex_id, osWaitForever);\n    osDelay(5000U); // block mutex for 5s\n    osMutexRelease(mutex_id);\n    osDelay(5000U); // sleep for 5s\n  }\n}\n\\endcode\n\nDuring the first second the high and mid priority threads are delayed. Thus the low priority\nthread can start its work, acquires the mutex and delays while holding it.\n\nAfter the first second the high and mid priority threads become ready. Thus the high priority\nthread gets precedence and tries to acquire the mutex. Because the mutex is already owned by\nthe low priority thread the high priority thread gets blocked.\n\nFinally the mid priority thread gets executed and start doing a lot of non-blocking stuff,\ni.e. it does not call any blocking RTOS functionality.\n\nWithout \\ref osMutexPrioInherit we would stuck here forever. Even if the low priority thread\ngets ready after 5s. Due to its low priority the mid priority thread always gets precedence.\nThe effect called priority inversion leads to the mid priority thread blocking the high\npriority thread indirectly.\n\nUsing \\ref osMutexPrioInherit as shown in the example code we get rid of this situation. Due\nto the priority inheritance protocol the low priority thread inherits the high priority\nwhile holding the mutex. Thus the low priority thread gets precedence over the mid priority\nthread until it release the mutex. On osMutexRelease the high priority thread get ready and\nis scheduled immediately.\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osMutexRobust\n\\details\nRobust flag in osMutexAttr_t.\n\nRobust mutexes are automatically released if the owning thread is terminated (either by\n\\ref osThreadExit or \\ref osThreadTerminate). Non-robust mutexes are not released and the user must\nassure mutex release manually.\n\n<b>Code Example</b>\n\nThis example reveals a blocked mutex if osMutexRobust is removed.\n\n\\code\n#include \"cmsis_os2.h\"\n \nosMutexId_t mutex_id;\n \nconst osMutexAttr_t Thread_Mutex_attr = {\n  \"myThreadMutex\",     // human readable mutex name\n  osMutexRobust,       // attr_bits\n  NULL,                // memory for control block   \n  0U                   // size for control block\n};\n \nvoid Thread(void *argument) {\n  osMutexAcquire(mutex_id, osWaitForever);\n  osThreadExit();\n}\n\\endcode\n\nDue to \\ref osMutexRobust the mutex gets released automatically. A non-robust mutex would stay locked and cannot be released anymore.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\typedef osMutexId_t\n\\details\nReturned by:\n- \\ref osMutexNew\n*/ \n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\struct osMutexAttr_t\n\\details\nSpecifies the following attributes for the \\ref osMutexNew function.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osMutexId_t osMutexNew (const osMutexAttr_t *attr)\n\\details\nThe function \\b osMutexNew creates and initializes a new mutex object and returns the pointer to the mutex object identifier\nor \\token{NULL} in case of an error. It can be safely called before the RTOS is\nstarted (call to \\ref osKernelStart), but not before it is initialized (call to \\ref osKernelInitialize).\n\nThe parameter \\a attr sets the mutex object attributes (refer to \\ref osMutexAttr_t). Default attributes will be used if set\nto \\token{NULL}.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nosMutexId_t mutex_id;  \n \nconst osMutexAttr_t Thread_Mutex_attr = {\n  \"myThreadMutex\",                          // human readable mutex name\n  osMutexRecursive | osMutexPrioInherit,    // attr_bits\n  NULL,                                     // memory for control block   \n  0U                                        // size for control block\n};\n \nvoid CreateMutex (void)  {\n  mutex_id = osMutexNew(&Thread_Mutex_attr);\n  if (mutex_id != NULL)  {\n    // Mutex object created\n  }\n}\n\\endcode\n*/\n\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn const char *osMutexGetName (osMutexId_t mutex_id)\n\\details\nThe function \\b osMutexGetName returns the pointer to the name string of the mutex identified by parameter \\a mutex_id or\n\\token{NULL} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout)\n\\details\nThe blocking function \\b osMutexAcquire waits until a mutex object specified by parameter \\a mutex_id becomes available. If\nno other thread has obtained the mutex, the function instantly returns and blocks the mutex object. \n\nThe parameter \\a timeout specifies how long the system waits to acquire the mutex. While the system waits, the thread that is\ncalling this function is put into the \\ref ThreadStates \"BLOCKED\" state. The parameter \\ref CMSIS_RTOS_TimeOutValue \"timeout\"\ncan have the following values:\n - when \\a timeout is \\token{0}, the function returns instantly (i.e. try semantics).\n - when \\a timeout is set to \\b osWaitForever the function will wait for an infinite time until the mutex becomes available (i.e. wait semantics).\n - all other values specify a time in kernel ticks for a timeout (i.e. timed-wait semantics).\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the mutex has been obtained.\n - \\em osErrorTimeout: the mutex could not be obtained in the given time.\n - \\em osErrorResource: the mutex could not be obtained when no \\a timeout was specified.\n - \\em osErrorParameter: parameter \\em mutex_id is \\token{NULL} or invalid.\n - \\em osErrorISR: cannot be called from interrupt service routines.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified mutex.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid WaitMutex (void) {\n  osMutexId_t mutex_id;\n  osStatus_t  status;\n \n  mutex_id = osMutexNew(NULL);\n  if (mutex_id != NULL) {\n    status = osMutexAcquire(mutex_id, 0U);\n    if (status != osOK)  {\n      // handle failure code\n    }\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osMutexRelease (osMutexId_t mutex_id)\n\\details\nThe function \\b osMutexRelease releases a mutex specified by parameter \\a mutex_id. Other threads that currently wait for\nthis mutex will be put into the \\ref ThreadStates \"READY\" state.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the mutex has been correctly released.\n - \\em osErrorResource: the mutex could not be released (mutex was not acquired or running thread is not the owner).\n - \\em osErrorParameter: parameter \\em mutex_id is \\token{NULL} or invalid.\n - \\em osErrorISR: \\b osMutexRelease cannot be called from interrupt service routines.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nosMutexId_t mutex_id;                                        // Mutex id populated by the function osMutexNew()\n \nvoid ReleaseMutex (osMutexId_t mutex_id) {\n  osStatus_t status;\n \n  if (mutex_id != NULL)  {\n    status = osMutexRelease(mutex_id);\n    if (status != osOK)  {\n      // handle failure code\n    }\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osThreadId_t osMutexGetOwner (osMutexId_t mutex_id)\n\\details\nThe function \\b osMutexGetOwner returns the thread ID of the thread that acquired a mutex specified by parameter \\a\nmutex_id. In case of an error or if the mutex is not blocked by any thread, it returns \\token{NULL}.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osMutexDelete (osMutexId_t mutex_id)\n\\details\nThe function \\b osMutexDelete deletes a mutex object specified by parameter \\a mutex_id. It releases internal memory obtained\nfor mutex handling. After this call, the \\a mutex_id is no longer valid and cannot be used. The mutex may be created again\nusing the function \\ref osMutexNew.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the mutex object has been deleted.\n - \\em osErrorParameter: parameter \\em mutex_id is \\token{NULL} or invalid.\n - \\em osErrorResource: the mutex is in an invalid state.\n - \\em osErrorISR: \\b osMutexDelete cannot be called from interrupt service routines.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified mutex.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nosMutexId_t mutex_id;                           // Mutex id populated by the function osMutexNew()\n \nvoid DeleteMutex (osMutexId_t mutex_id)  {\n  osStatus_t status;\n \n  if (mutex_id != NULL)  {\n    status = osMutexDelete(mutex_id);\n    if (status != osOK)  {\n      // handle failure code\n    }\n  }\n}\n\\endcode\n*/\n/// @}\n\n// these struct members must stay outside the group to avoid double entries in documentation\n/**\n\\var osMutexAttr_t::attr_bits\n\\details\nThe following bit masks can be used to set options:\n - \\ref osMutexRecursive : a thread can consume the mutex multiple times without locking itself.\n - \\ref osMutexPrioInherit : the owner thread inherits the priority of a (higher priority) waiting thread.\n - \\ref osMutexRobust : the mutex is automatically released when owner thread is terminated.\n\nUse logical \\em 'OR' operation to select multiple options, for example:\n\\code\nosMutexRecursive | osMutexPrioInherit;\n\\endcode\n\nDefault: \\token{0} which specifies:\n - <i>non recursive mutex</i>: a thread cannot consume the mutex multiple times.\n - <i>non priority raising</i>: the priority of an owning thread is not changed.\n - <i>mutex is not automatically release</i>: the mutex object must be always is automatically released when owner thread is terminated.\n\n*/\n/**\n\\var osMutexAttr_t::cb_mem\n\\details\nPointer to a memory for the mutex control block object. Refer to \\ref StaticObjectMemory for more information.\n\nDefault: \\token{NULL} to use \\ref CMSIS_RTOS_MemoryMgmt_Automatic for the mutex control block.\n*/\n/**\n\\var osMutexAttr_t::cb_size\n\\details\nThe size (in bytes) of memory block passed with \\ref cb_mem. For RTX, the minimum value is defined with \\ref osRtxMutexCbSize (higher values are permitted).\n\nDefault: \\token{0} as the default is no memory provided with \\ref cb_mem.\n*/\n/**\n\\var osMutexAttr_t::name\n\\details\nPointer to a constant string with a human readable name (displayed during debugging) of the mutex object.\n\nDefault: \\token{NULL} no name specified.\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_ProcessIsolation.txt",
    "content": "/**\n\\addtogroup CMSIS_RTOS_ProcessIsolation Process Isolation\n\\ingroup CMSIS_RTOS CMSIS_RTOSv2\n@{\n\nThis chapter explains mechanisms available for process isolation support in CMSIS-RTOS2 API.\n\\if FuSaRTS\nSee \\ref fusa_process_isolation for a summary of other related pages such as RTX configuration and safety user requirements.\n\\endif\n\nCMSIS-RTOS2 API defines a set of features to protect critical parts of an application against software flaws that may exist in other parts of an application.\n\n\\par\n- <b>\\ref rtos_process_isolation_mpu</b> for memory access protection in the system.\n<br>\nRTOS threads can access only memory regions and peripherals based on their MPU Protected Zone assignment. Non-privileged thread code cannot accidentally modify critical RTOS kernel data or memory belonging to other zones.\n\n\\par\n- <b>\\ref rtos_process_isolation_safety_class</b> for access protection to RTOS objects.\n<br>\nThe RTOS objects with a higher safety class assigned to them cannot be modified via RTOS API functions from threads that have lower safety class assigned.\n\n\\par\n- <b>\\ref rtos_process_isolation_thread_wdt</b> to verify execution times of threads.\n<br>\nEach thread can maintain own thread watchdog and in case of timing violations, corresponding thread watchdog alarm will be triggered.\n\n\\par\n- <b>\\ref rtos_process_isolation_faults</b> in case of a detected failure (for example thread watchdog alarm or MPU Fault).\n<br>\nThe RTOS provides functions to block execution of malfunctioning components and with that dedicate system resources for operation of the safety critical threads.\n\n\\if FuSaRTS\nSection \\ref fusa_process_isolation lists safety requirements for Process Isolation functions.\n\\endif\n\n\\addtogroup rtos_process_isolation_mpu MPU Protected Zones\n\\details\nMemory Protection Unit (MPU) is available on many Cortex-M devices and allows  restricted access to memory regions and peripherals. <a href=\"../../Core/html/index.html#ref_man_sec\"><b>The Cortex-M Reference Manuals</b></a> provide detailed information about the MPU.\n\nAn MPU Protected Zone is a set of multiple memory regions and peripherals with specified access rights. One or more RTOS threads can be assigned to an MPU Protected Zone.\n\nThe figure below illustrates the concept for MPU Protected Zones that isolate  various threads.\n\n\\image html rtos_mpu.png \"Process isolation with MPU in RTX RTOS\"\n\nSections below explains how to use MPU Protected Zones.\n- \\ref rtos_process_isolation_mpu_refs\n- \\ref rtos_process_isolation_mpu_def\n- \\ref rtos_process_isolation_mpu_load\n- \\ref rtos_process_isolation_mpu_objects\n- \\ref rtos_process_isolation_mpu_fault\n\n\\section rtos_process_isolation_mpu_refs Function references\n\nSummary of functions that implement MPU Protected Zone functionality:\n\n- \\ref osThreadNew : \\copybrief osThreadNew\n- \\ref osThreadZone : \\copybrief osThreadZone\n- \\ref osThreadGetZone : \\copybrief osThreadGetZone\n- \\ref osThreadTerminateZone : \\copybrief osThreadTerminateZone\n- \\ref osZoneSetup_Callback : \\copybrief osZoneSetup_Callback\n\n\\section rtos_process_isolation_mpu_def Define MPU Protected Zones\n\nIn the architectural design phase an application is logically split into functionalities with the same integrity level (same safety requirements). They can safely operate within the same MPU Protected Zone and hence access same memory areas and peripherals. \n\nMPU protected zones are defined in an MPU table where each row describes an individual MPU zone and each cell in the row specifies an MPU region within that zone. For details see section <a href=\"../../Core/html/group__mpu__functions.html\"><b>MPU Functions</b></a> in CMSIS-Core(M) documentation.\n\n<a href=\"https://arm-software.github.io/CMSIS_5/Zone/html/index.html\" target=\"_blank\"><b>CMSIS-Zone</b></a> provides a utility that allows graphic configuration of MPU protected zones and generates MPU table in the CMSIS format.\n\n\\note\nInterrupt handlers bypass the MPU protection. For this reason, it is required that all interrupt handlers are verified according to the highest integrity level to exclude unintended memory accesses.\n\n\\subsection rtx_process_isolation_mpu_id Zone Identifiers\nZone ID is used to refer to a specific MPU protected zone. Zone ID value equals to the row index (starting from 0) in the MPU table that describes corresponding MPU Protected Zone.\nAn MPU Protected Zone is assigned to one or more RTOS threads. This is done by providing the Zone ID value in thread attributes \\ref osThreadAttr_t when creating the thread with the \\ref osThreadNew function.\n\n\\b Example:\n\n\\code\n/* ThreadA thread attributes */\nconst osThreadAttr_t thread_A_attr = {\n  .name       = \"ThreadA\",       // human readable thread name\n  .attr_bits  = osThreadZone(3U) // assign thread to MPU protected zone 3\n};\nosThreadNew(ThreadA, NULL, &thread_A_attr);\n\\endcode\n\n\\section rtos_process_isolation_mpu_load Load MPU Protected Zone\n\nWhen switching threads the RTOS kernel compares Zone IDs of the currently running thread and the next thread to be executed. If the Zone Ids are different then a callback function \\ref osZoneSetup_Callback is called. This function shall be implemented in the user application code to actually switch to the new MPU Protected Zone. In the function the user should load the MPU Protected Zone according to the Zone Id provided in the argument.\n\n\\b Example:\n\\code\n/* Update MPU settings for newly activating Zone */\nvoid osZoneSetup_Callback (uint32_t zone) {\n\n  if (zone >= ZONES_NUM) {\n    // Here issue an error for incorrect zone value\n  }\n\n  ARM_MPU_Load(mpu_table[zone], MPU_REGIONS);\n}\n\\endcode\n\n\\section rtos_process_isolation_mpu_objects RTOS Objects and MPU Protection\nTo access RTOS objects from the application RTOS APIs rely on a numeric xxx_id parameter associated with the object as explained in \\ref rtos_api2. For example\n\n\\code\nosEventFlagsId_t evt_flags;\nevt_flags = osEventFlagsNew(NULL);\nosEventFlagsSet(evt_flags, 1);\n\\endcode\n\nThe allocation of an RTOS object to the memory in a specific MPU Protected Zone does not provide access restriction. The access restriction can be bypassed if another thread calls the CMSIS-RTOS2 API with the object ID of the RTOS object as argument. The CMSIS-RTOS2 function is executed in handler mode and therefore can access and modify the RTOS object without raising a Memory Fault.\nTo enable access control for RTOS objects the \\ref rtos_process_isolation_safety_class concept is introduced in CMSIS-RTOS2.\n\n\\section rtos_process_isolation_mpu_fault Handle Memory Access Faults\n\nA memory access fault is triggered when a thread tries to access memory or peripherals outside of the MPU Protected Zone loaded while the thread is running. In such case Memory Management Interrupt (<a href=\"../../Core/html/group__NVIC__gr.html \"><b>MemoryManagement_IRQn</b></a>) is triggered by the processor and its handling function is executed according to the exception vector table specified in the device startup file (by default \\token{MemManage_Handler(void)} ).\n\nThe \\e MemManage_Handler() interrupt handler is application specific and needs to be implemented by the user. In the handler it is possible to identify the thread that caused the memory access fault, the corresponding zone id and the safety class. This information can be used to define actions for entering a safe state. \\ref rtos_process_isolation_faults provides more details on the available system recovery possibilities.\n\n\\addtogroup rtos_process_isolation_safety_class Safety Classes\n\n\\ref rtos_process_isolation_mpu_objects explains that MPU Protected Zones do not provide full access protection to RTOS objects accessed via CMSIS-RTOS2 API. The concept of a safety class fills this gap.\n\nEvery RTOS object, including thread is assigned with a numeric safety class value. A thread cannot modify an RTOS object if its safety class value is higher than the safety class value of the thread.\nFor example, it is not possible to change the priority or suspend a thread that has a higher safety class value than the thread that is currently executed.\n\n\\section rtos_process_isolation_safety_class_refs Function references\n\nSummary of functions and macros that implement safety classes:\n\n- \\ref osSafetyClass : \\copybrief osSafetyClass\n- \\ref osThreadGetClass : \\copybrief osThreadGetClass\n- \\ref osSafetyWithSameClass : \\copybrief osSafetyWithSameClass\n- \\ref osSafetyWithLowerClass : \\copybrief osSafetyWithLowerClass\n- \\ref osKernelProtect : \\copybrief osKernelProtect\n- \\ref osThreadSuspendClass : \\copybrief osThreadSuspendClass\n- \\ref osThreadResumeClass : \\copybrief osThreadResumeClass\n- \\ref osKernelDestroyClass  : \\copybrief osKernelDestroyClass\n\n\\ref rtos_process_isolation_safety_class_assign lists CMSIS-RTOS2 API functions that support safety class assignment when creating RTOS objects.\n\\ref rtos_process_isolation_safety_class_error lists CMSIS-RTOS2 API functions that verify safety class assignment before execution.\n\\section rtos_process_isolation_safety_class_assign Assign Safety Class to an RTOS Object\n\nIt is possible to create any objects regardless of the safety class after the kernel initialize with \\ref osKernelInitialize, but before the kernel is started with \\ref osKernelStart. This allows to setup a system before actually starting the RTOS kernel.\n\nThreads of a higher safety class can create RTOS objects that belong to a lower or same safety class. For the object types listed below, the \\e attr_bits can have an optional safety class value that is assigned when the RTOS object is created with the \\e <i>os<Object>New</i> function. The macro \\ref osSafetyClass encodes the value for the \\e attr_bits field in the attr struct. For example:\n\n\\code\nconst osEventFlagsAttr_t evt_flags_attr = {\n  .attr_bits = osSafetyClass(SAFETY_CLASS_SAFE_MODE_OPERATION)\n};\nosEventFlagsId_t evt_flags;\nevt_flags = osEventFlagsNew(&evt_flags_attr);\n\\endcode\n\nThe following object types support safety class assignment when creating an object with corresponding \\e os<Object>New function:\n\n- \\ref osThreadAttr_t \\copybrief osThreadAttr_t Used in the \\ref osThreadNew function.\n- \\ref osEventFlagsAttr_t \\copybrief  osEventFlagsAttr_t Used in the \\ref osThreadNew function.\n- \\ref osTimerAttr_t \\copybrief osTimerAttr_t Used in the \\ref osTimerNew function.\n- \\ref osMutexAttr_t \\copybrief osMutexAttr_t Used in the \\ref osMutexNew function.\n- \\ref osSemaphoreAttr_t \\copybrief osSemaphoreAttr_t Used in the \\ref osSemaphoreNew function.\n- \\ref osMemoryPoolAttr_t \\copybrief osMemoryPoolAttr_t Used in the \\ref osMemoryPoolNew function.\n- \\ref osMessageQueueAttr_t \\copybrief osMessageQueueAttr_t Used in the \\ref osMessageQueueNew function.\n\nIf safety class is not provided when creating the RTOS object then it inherits the safety class of the current running thread that creates the object. If the object is created before kernel is started and no safety class is provided, then it receives default safety class 0. This simplifies integration of third-party code that can be classified as non-safety critical.\n\n\\section rtos_process_isolation_safety_class_error Handle Object Access Violation\n\nRTOS API call returns error code \\ref osErrorSafetyClass if the requested object manipulation cannot be performed because the target object has higher safety class than the safety class of the running thread. For example:\n\\code\nstatus = osEventFlagsSet(evt_flags, 1);\nif (status == osErrorSafetyClass)\n{\n  //handle the safety class error\n}\n\\endcode\n\nFollowing functions compare the safety class of the running thread with the safety class of the target object.\n\nIn \\ref CMSIS_RTOS_KernelCtrl functions:\n\nComparison is done with safety class configured with \\ref osKernelProtect\n- \\ref osKernelLock\n- \\ref osKernelRestoreLock\n- \\ref osKernelSuspend\n- \\ref osKernelProtect\n- \\ref osKernelDestroyClass\n\nIn \\ref CMSIS_RTOS_ThreadMgmt functions:\n- \\ref osThreadNew\n- \\ref osThreadSetPriority\n- \\ref osThreadSuspend\n- \\ref osThreadResume\n- \\ref osThreadDetach\n- \\ref osThreadJoin\n- \\ref osThreadTerminate\n- \\ref osThreadSuspendClass\n- \\ref osThreadResumeClass\n\nIn \\ref CMSIS_RTOS_ThreadFlagsMgmt functions:\n- \\ref osThreadFlagsSet\n\nIn \\ref CMSIS_RTOS_EventFlags functions:\n- \\ref osEventFlagsNew\n- \\ref osEventFlagsSet\n- \\ref osEventFlagsClear\n- \\ref osEventFlagsWait\n- \\ref osEventFlagsDelete\n\nIn \\ref CMSIS_RTOS_TimerMgmt functions:\n- \\ref osTimerNew\n- \\ref osTimerStart\n- \\ref osTimerStop\n- \\ref osTimerDelete\n\nIn \\ref CMSIS_RTOS_MutexMgmt functions:\n- \\ref osMutexNew\n- \\ref osMutexAcquire\n- \\ref osMutexDelete\n\nIn \\ref CMSIS_RTOS_SemaphoreMgmt functions:\n- \\ref osSemaphoreNew\n- \\ref osSemaphoreAcquire\n- \\ref osSemaphoreRelease\n- \\ref osSemaphoreDelete\n\nIn \\ref CMSIS_RTOS_PoolMgmt functions:\n- \\ref osMemoryPoolNew\n- \\ref osMemoryPoolAlloc\n- \\ref osMemoryPoolFree\n- \\ref osMemoryPoolDelete\n\nIn \\ref CMSIS_RTOS_Message functions:\n- \\ref osMessageQueueNew\n- \\ref osMessageQueuePut\n- \\ref osMessageQueueGet\n- \\ref osMessageQueueReset\n- \\ref osMessageQueueDelete\n\n\\addtogroup rtos_process_isolation_thread_wdt Thread Watchdogs\n\nCMSIS-RTOS defines <b>Thread Watchdogs</b> that allow to control timing constraints for thread execution (<a href=\"https://en.wikipedia.org/wiki/Temporal_isolation\" target=\"_blank\"><b>temporal isolation</b></a>).\n\nEach thread has an independent watchdog timer that is started with the function \\ref osThreadFeedWatchdog(uint32_t ticks). The \\token{ticks} value specifies the timeout before it expires.  Within this time interval the function \\ref osThreadFeedWatchdog must be called again within the thread to restart the watchdog timer.\n\nIf the thread watchdog is not restarted during the specified amount of ticks the Watchdog Alarm  callback \\ref osWatchdogAlarm_Handler(osThreadId_t thread_id) is triggered and can be used to recover the system or proceed to the system shutdown.\n\nFigure below explains the concept with an example:\n\n\\image html thread_watchdogs.png \"Example use of Thread Watchdogs\"\n\n\\ref rtos_process_isolation_faults provides more details on the available possibilities for system recovery.\n\\note If the application suspends a thread from scheduling by calling \\ref osThreadSuspend or \\ref osThreadSuspendClass, the thread watchdog still continues to run, and it is expected to expire and trigger \\ref osWatchdogAlarm_Handler because the thread will not be serviced as expected.\n\\note Hence it may be necessary to differentiate handling of thread watchdogs that expired unexpectedly from the thread watchdog alarms of intentionally suspended threads.\n\n\\section rtos_process_isolation_thread_wdt_refs Function references\n\nSummary of functions that implement thread watchdog functionality\n\n- \\ref osThreadFeedWatchdog : \\copybrief osThreadFeedWatchdog\n- \\ref osWatchdogAlarm_Handler : \\copybrief osWatchdogAlarm_Handler\n\n\\addtogroup rtos_process_isolation_faults Fault Handling\n\nWhen a failure, or an error is detected in a system (for example \\ref rtos_process_isolation_mpu_fault \"memory access fault\", \\ref rtos_process_isolation_thread_wdt \"thread watchdog alarm\", or others) CMSIS-RTOS2 API allows to stop further execution of selected RTOS threads. This can be used to block malfunctioning components or free computing resources and so enable execution of the safety critical threads. \n\nFollowing approaches are available:\n - function \\ref osThreadTerminateZone can be called in case of a fault exception. It will terminate all threads from the specified MPU Protected Zone (for example, can be the zone that has caused the fault). The function cannot be called in thread context or interrupts other than faults. Note that \\ref osFaultResume can be called at the end of the handling code to return program execution into a known context and let kernel schedule the next thread ready for execution.\n - function \\ref osThreadSuspendClass can be called in case of a thread watchdog alarm or other errors handled in thread context. It allows to suspend operation of threads based on the safety class assignment. Function \\ref osThreadResumeClass can be used to resume operation of threads based on their safety class. \\ref rtos_process_isolation_thread_wdt contains an example that demonstrates fault handling concept for thread watchdogs.\n\nFunction \\ref osKernelDestroyClass fully removes RTOS objects of specific safety classes from the system. This can be useful to do before restarting operation of terminated or suspended threads.\n\n\\section rtos_process_isolation_faults_refs Function references\n\nFollowing CMSIS-RTOS2 functions and macros support fault handling:\n\n- \\ref osThreadGetZone : \\copybrief osThreadGetZone\n- \\ref osThreadTerminateZone : \\copybrief osThreadTerminateZone\n- \\ref osThreadGetClass : \\copybrief osThreadGetClass\n- \\ref osSafetyWithSameClass : \\copybrief osSafetyWithSameClass\n- \\ref osSafetyWithLowerClass : \\copybrief osSafetyWithLowerClass\n- \\ref osThreadSuspendClass : \\copybrief osThreadSuspendClass\n- \\ref osThreadResumeClass : \\copybrief osThreadResumeClass\n- \\ref osKernelDestroyClass : \\copybrief osKernelDestroyClass\n- \\ref osFaultResume : \\copybrief osFaultResume\n- \\ref osWatchdogAlarm_Handler : \\copybrief osFaultResume\n\n// @}\n\n*/\n// end\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Sema.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Semaphore Management ====\n/** \n\\addtogroup CMSIS_RTOS_SemaphoreMgmt Semaphores\n\\ingroup CMSIS_RTOS\n\\brief Access shared resources simultaneously from different threads.\n\\details \nSemaphores are used to manage and protect access to shared resources. Semaphores are very similar to\n\\ref CMSIS_RTOS_MutexMgmt \"Mutexes\". Whereas a Mutex permits just one thread to access a shared resource at a\ntime, a semaphore can be used to permit a fixed number of threads/ISRs to access a pool of shared resources. Using\nsemaphores, access to a group of identical peripherals can be managed (for example multiple DMA channels).\n\n\\image html \"Semaphore.png\" \"CMSIS-RTOS Semaphore\"\n\nA semaphore object should be initialized to the maximum number of available tokens. This number of available resources is\nspecified as parameter of the \\ref osSemaphoreNew function. Each time a semaphore token is obtained with \\ref osSemaphoreAcquire\n(in \\em available state), the semaphore count is decremented. When the semaphore count is 0 (i.e. \\em depleted state), no\nmore semaphore tokens can be obtained. The thread/ISR that tries to obtain the semaphore token needs to wait until the next\ntoken is free. Semaphores are released with \\ref osSemaphoreRelease incrementing the semaphore count.\n\n\\image html \"semaphore_states.png\" \"CMSIS-RTOS Semaphore States\"\n\n\\note The functions \\ref osSemaphoreAcquire, \\ref osSemaphoreGetCount, and \\ref osSemaphoreRelease can be called from\n\\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\note Refer to \\ref semaphoreConfig for RTX5 configuration options.\n\nSemaphore Use Cases\n-------------------\nDue to their flexibility, semaphores cover a wide range of synchronizing applications. At the same time, they are perhaps the\nmost challenging RTOS object to understand. The following explains a use case for semaphores, taken from the book\n<a href=\"http://www.greenteapress.com/semaphores/\" target=\"_blank\">The Little Book Of Semaphores</a> by Allen B. Downey which\nis available for free download.\n\n<b>Non-binary Semaphore (Multiplex)</b>\n\nA multiplex limits the number of threads that can access a critical section of code. For example, this could be a function\naccessing DMA resources which can only support a limited number of calls.\n\nTo allow multiple threads to run the function, initialize a semaphore to the maximum number of threads that can be allowed.\nThe number of tokens in the semaphore represents the number of additional threads that may enter. If this number is zero,\nthen the next thread trying to access the function will have to wait until one of the other threads exits and releases its\ntoken. When all threads have exited the token number is back to n. The following example shows the code for one of the\nthreads that might access the resource:\n\n\\code\nosSemaphoreId_t multiplex_id;\n \nvoid thread_n (void) {\n \n  multiplex_id = osSemaphoreNew(3U, 3U, NULL);\n  while(1) {\n    osSemaphoreAcquire(multiplex_id, osWaitForever);\n    // do something\n    osSemaphoreRelease(multiplex_id);\n  }\n}\n\\endcode\n\n<b>Producer/Consumer Semaphore</b>\n\nThe producer-consumer problem can be solved using two semaphores.\n\nA first semaphore (\\token{empty_id}) counts down the available (empty) buffers, i.e.\nthe producer thread can wait for available buffer slots by acquiring from this one.\n\nA second semaphore (\\token{filled_id}) counts up the used (filled) buffers, i.e.\nthe consumer thread can wait for available data by acquiring from this one.\n\nIt is crucial for the correct behaviour that the threads acquire and release on both\nsemaphores in the given sequence. According to this example one can have multiple\nproducer and/or consumer threads running concurrently.\n\n\\code\n#define BUFFER_SIZE 10U\n \nosSemaphoreId_t empty_id = osSemaphoreNew(BUFFER_SIZE, BUFFER_SIZE, NULL);\nosSemaphoreId_t filled_id = osSemaphoreNew(BUFFER_SIZE, 0U, NULL);\n \nvoid producer_thread (void) {\n  while(1) {\n    osSemaphoreAcquire(empty_id, osWaitForever);\n    // produce data\n    osSemaphoreRelease(filled_id);\n  }\n}\n\nvoid consumer_thread (void) {\n \n  while(1){\n    osSemaphoreAcquire(filled_id, osWaitForever);\n    // consume data\n    osSemaphoreRelease(empty_id);\n  }\n}\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\typedef  osSemaphoreId_t\n\\details\nReturned by:\n- \\ref osSemaphoreNew\n*/\n\n/**\n\\struct osSemaphoreAttr_t\n\\details\nSpecifies the following attributes for the \\ref osSemaphoreNew function.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr)\n\\details\nThe function \\b osSemaphoreNew creates and initializes a semaphore object that is used to manage access to shared resources\nand returns the pointer to the semaphore object identifier or \\token{NULL} in case of an error. It can be safely called\nbefore the RTOS is started (call to \\ref osKernelStart), but not before it is initialized (call to \\ref osKernelInitialize).\n\nThe parameter \\em max_count specifies the maximum number of available tokens. A \\em max_count value of 1 creates a binary\nsemaphore.\n\nThe parameter \\em initial_count sets the initial number of available tokens.\n\nThe parameter \\em attr specifies additional semaphore attributes. Default attributes will be used if set to \\token{NULL}.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \nosSemaphoreId_t sid_Semaphore;                  // semaphore id\n \nosThreadId_t tid_Thread_Semaphore;              // thread id\n \nvoid Thread_Semaphore (void *argument);         // thread function\n \nint Init_Semaphore (void) {\n \n  sid_Semaphore = osSemaphoreNew(2U, 2U, NULL);\n  if (sid_Semaphore == NULL) {\n    ; // Semaphore object not created, handle failure\n  }\n \n  tid_Thread_Semaphore = osThreadNew(Thread_Semaphore, NULL, NULL);\n  if (tid_Thread_Semaphore == NULL) {\n    return(-1);\n  }\n \n  return(0);\n}\n \nvoid Thread_Semaphore (void *argument) {\n  osStatus_t val;\n \n  while (1) {\n    ; // Insert thread code here...\n \n    val = osSemaphoreAcquire(sid_Semaphore, 10U);       // wait for max. 10 ticks for semaphore token to get available\n    switch (val) {\n      case osOK:\n        ; // Use protected code here...\n        osSemaphoreRelease(sid_Semaphore);              // return a token back to a semaphore\n        break;\n      case osErrorResource:\n        break;\n      case osErrorParameter:\n        break;\n      default:\n        break;\n    }\n \n    osThreadYield();                                    // suspend thread\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id)\n\\details\nThe function \\b osSemaphoreGetName returns the pointer to the name string of the semaphore identified by parameter \\a\nsemaphore_id or \\token{NULL} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout)\n\\details\nThe blocking function \\b osSemaphoreAcquire waits until a token of the semaphore object specified by parameter\n\\a semaphore_id becomes available. If a token is available, the function instantly returns and decrements the token count. \n\nThe parameter \\a timeout specifies how long the system waits to acquire the token. While the system waits, the thread\nthat is calling this function is put into the \\ref ThreadStates \"BLOCKED\" state. The parameter \\ref CMSIS_RTOS_TimeOutValue\n\"timeout\" can have the following values:\n - when \\a timeout is \\token{0}, the function returns instantly (i.e. try semantics).\n - when \\a timeout is set to \\b osWaitForever the function will wait for an infinite time until the semaphore becomes\n   available (i.e. wait semantics).\n - all other values specify a time in kernel ticks for a timeout (i.e. timed-wait semantics).\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the token has been obtained and the token count decremented.\n - \\em osErrorTimeout: the token could not be obtained in the given time.\n - \\em osErrorResource: the token could not be obtained when no \\a timeout was specified.\n - \\em osErrorParameter: the parameter \\a semaphore_id is \\token{NULL} or invalid.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified semaphore.\n\n\\note May be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\" if the parameter \\a timeout is set to\n\\token{0}.\n \n<b>Code Example</b>\n\nRefer to \\ref osSemaphoreNew.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id)\n\\details\nThe function \\b osSemaphoreRelease releases a token of the semaphore object specified by parameter \\a semaphore_id. Tokens\ncan only be released up to the maximum count specified at creation time, see \\ref osSemaphoreNew. Other threads that\ncurrently wait for a token of this semaphore object will be put into the \\ref ThreadStates \"READY\" state.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the token has been released and the count incremented.\n - \\em osErrorResource: the token could not be released (maximum token count has been reached).\n - \\em osErrorParameter: the parameter \\a semaphore_id is \\token{NULL} or invalid.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified semaphore.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\nRefer to \\ref osSemaphoreNew.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id)\n\\details\nThe function \\b osSemaphoreGetCount returns the number of available tokens of the semaphore object specified by parameter\n\\a semaphore_id. In case of an error it returns \\token{0}.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id)\n\\details\nThe function \\b osSemaphoreDelete deletes a semaphore object specified by parameter \\a semaphore_id. It releases internal\nmemory obtained for semaphore handling. After this call, the \\a semaphore_id is no longer valid and cannot be used. The\nsemaphore may be created again using the function \\ref osSemaphoreNew.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the semaphore object has been deleted.\n - \\em osErrorParameter: the parameter \\a semaphore_id is \\token{NULL} or invalid.\n - \\em osErrorResource: the semaphore is in an invalid state.\n - \\em osErrorISR: \\b osSemaphoreDelete cannot be called from interrupt service routines.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified semaphore.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n/// @}\n\n// these struct members must stay outside the group to avoid double entries in documentation\n/**\n\\var osSemaphoreAttr_t::attr_bits\n\\details\nReserved for future use (must be set to '0' for future compatibility).\n\n\\var osSemaphoreAttr_t::cb_mem\n\\details\nPointer to a memory for the semaphore control block object. Refer to \\ref StaticObjectMemory for more information.\n\nDefault: \\token{NULL} to use \\ref CMSIS_RTOS_MemoryMgmt_Automatic for the semaphore control block.\n\n\\var osSemaphoreAttr_t::cb_size\n\\details\nThe size (in bytes) of memory block passed with \\ref cb_mem. For RTX, the minimum value is defined with \\ref osRtxSemaphoreCbSize (higher values are permitted).\n\nDefault: \\token{0} as the default is no memory provided with \\ref cb_mem.\n\n\\var osSemaphoreAttr_t::name\n\\details\nPointer to a constant string with a human readable name (displayed during debugging) of the semaphore object.\n\nDefault: \\token{NULL} no name specified.\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Status.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n// ==== Definitions ====\n/**\n\\addtogroup CMSIS_RTOS_Definitions Definitions\n\\ingroup CMSIS_RTOS\n\\brief Constants and enumerations used by many CMSIS-RTOS functions.\n\\details The following constants and enumerations are used by many CMSIS-RTOS function calls.\n@{\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\typedef osStatus_t\n\\details\nThe \\b osStatus_t enumeration defines the event status and error codes that are returned by many CMSIS-RTOS functions.\n*/\n\n/**\n\\def osWaitForever\n\\details A special \\ref CMSIS_RTOS_TimeOutValue that informs the RTOS to wait infinite until a resource becomes available.\nIt applies to the following functions: \n - \\ref osDelay : \\copybrief osDelay\n - \\ref osThreadFlagsWait : \\copybrief osThreadFlagsWait \n - \\ref osEventFlagsWait : \\copybrief osEventFlagsWait\n - \\ref osMutexAcquire : \\copybrief osMutexAcquire\n - \\ref osSemaphoreAcquire : \\copybrief osSemaphoreAcquire\n - \\ref osMemoryPoolAlloc : \\copybrief osMemoryPoolAlloc\n - \\ref osMessageQueuePut : \\copybrief osMessageQueuePut\n - \\ref osMessageQueueGet : \\copybrief osMessageQueueGet\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFlagsWaitAny\n\nReference: \n - \\ref osEventFlagsWait\n - \\ref osThreadFlagsWait\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFlagsWaitAll\n\nReference: \n - \\ref osEventFlagsWait\n - \\ref osThreadFlagsWait\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFlagsNoClear\n\nReference: \n - \\ref osEventFlagsWait\n - \\ref osThreadFlagsWait\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osSafetyClass(n)\n\\param         n        safety class value.\n\\brief  Safety class value in attribute bit field format.\n\\details\n\nThe preprocessor macro \\b osSafetyClass constructs attribute bitmask with safety class bits set to \\a n.\n\n<b>Code Example:</b>\n\\code\n/* Event Flags object attributes */\nconst osEventFlagsAttr_t ef_attr = {\n  .name       = \"EventFlags1\",    // human readable object name\n  .attr_bits  = osSafetyClass(2U) // assign object to safety class 2\n};\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osSafetyWithSameClass\n\\details\nDefinition for RTOS objects with the same safety class. Can be used as mode argument in the following functions:\n - \\ref osThreadSuspendClass : \\copybrief osThreadSuspendClass\n - \\ref osThreadResumeClass : \\copybrief osThreadResumeClass\n - \\ref osKernelDestroyClass : \\copybrief osKernelDestroyClass\n\n\\def osSafetyWithLowerClass\n\\details\nDefinition for RTOS objects with lower safety class.  Can be used as mode argument in the following functions:\n - \\ref osThreadSuspendClass : \\copybrief osThreadSuspendClass\n - \\ref osThreadResumeClass : \\copybrief osThreadResumeClass\n - \\ref osKernelDestroyClass : \\copybrief osKernelDestroyClass\n*/\n\n/// @}\n/**\n\\addtogroup flags_error_codes Flags Functions Error Codes\n\\ingroup CMSIS_RTOS_Definitions\n\\brief Constants used by \\ref CMSIS_RTOS_ThreadFlagsMgmt and \\ref CMSIS_RTOS_EventFlags to return error codes.\n\\details In case of an error, flags functions (\\ref CMSIS_RTOS_ThreadFlagsMgmt and\n\\ref CMSIS_RTOS_EventFlags) return error codes. To indicate that an error has occurred, the highest bit of\nthe return value is be set. You can check the exact error using the codes shown below.\n@{\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFlagsErrorUnknown\n\\details Generic error. It is returned when no other error can be applied. \n\nReference: \n - \\ref osThreadFlagsSet\n - \\ref osThreadFlagsClear\n - \\ref osThreadFlagsWait\n - \\ref osEventFlagsSet\n - \\ref osEventFlagsClear\n - \\ref osEventFlagsWait\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFlagsErrorTimeout\n\\details This error is returned if a timeout was specified and the specified flags were not set, when the\ntimeout occurred.\n\nReference: \n - \\ref osThreadFlagsSet\n - \\ref osThreadFlagsClear\n - \\ref osThreadFlagsWait\n - \\ref osEventFlagsSet\n - \\ref osEventFlagsClear\n - \\ref osEventFlagsWait\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFlagsErrorResource\n\\details This error is returned when you try to get a flag that was not set \\a and timeout 0 was\nspecified. Is also returned when the specified object identifier is corrupt or invalid.\n\nReference: \n - \\ref osThreadFlagsSet\n - \\ref osThreadFlagsClear\n - \\ref osThreadFlagsWait\n - \\ref osEventFlagsSet\n - \\ref osEventFlagsClear\n - \\ref osEventFlagsWait\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFlagsErrorParameter\n\\details This error is returned when a given parameter is wrong.\n\nReference: \n - \\ref osThreadFlagsSet\n - \\ref osThreadFlagsClear\n - \\ref osThreadFlagsWait\n - \\ref osEventFlagsSet\n - \\ref osEventFlagsClear\n - \\ref osEventFlagsWait\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\def osFlagsErrorISR\n\\details This error is returned when a non-ISR-callable function was called from an ISR.\n\nReference: \n - \\ref osThreadFlagsSet\n - \\ref osThreadFlagsClear\n - \\ref osThreadFlagsWait\n - \\ref osEventFlagsSet\n - \\ref osEventFlagsClear\n - \\ref osEventFlagsWait\n*/\n\n/// @} \n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Thread.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Thread Management ====\n/** \n\\addtogroup CMSIS_RTOS_ThreadMgmt Thread Management\n\\ingroup CMSIS_RTOS CMSIS_RTOSv2\n\\brief Define, create, and control thread functions.\n\\details \nThe Thread Management function group allows defining, creating, and controlling thread functions in the system.\n\n\\note Thread management functions cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\anchor ThreadStates\nThread states\n-------------\nThreads can be in the following states:\n\n - \\b RUNNING: The thread that is currently running is in the \\ref ThreadStates \"RUNNING\" state. Only one thread at a time can be in this\n   state.\n - \\b READY: Threads which are ready to run are in the \\ref ThreadStates \"READY\" state. Once the \\ref ThreadStates \"RUNNING\" thread has terminated, or is\n   \\ref ThreadStates \"BLOCKED\", the next \\ref ThreadStates \"READY\" thread with the highest priority becomes the \\ref ThreadStates \"RUNNING\" thread.\n - \\b BLOCKED: Threads that are blocked either delayed, waiting for an event to occur or suspended are in the \\ref ThreadStates \"BLOCKED\"\n   state.\n - \\b TERMINATED: When \\ref osThreadTerminate is called, threads are \\ref ThreadStates \"TERMINATED\" with resources not yet released (applies to \\ref joinable_threads \"joinable threads).\n - \\b INACTIVE: Threads that are not created or have been terminated with all resources released are in the \\ref ThreadStates \"INACTIVE\" state.\n \n\\image html \"ThreadStatus.png\" \"Thread State and State Transitions\"\n\n\nA CMSIS-RTOS assumes that threads are scheduled as shown in the figure <b>Thread State and State Transitions</b>. The thread\nstates change as follows:\n - A thread is created using the function \\ref osThreadNew. This puts the thread into the \\ref ThreadStates \"READY\" or \\ref ThreadStates \"RUNNING\" state\n   (depending on the thread priority).\n - CMSIS-RTOS is preemptive. The active thread with the highest priority becomes the \\ref ThreadStates \"RUNNING\" thread provided it does not\n   wait for any event. The initial priority of a thread is defined with the \\ref osThreadAttr_t but may be changed during\n   execution using the function \\ref osThreadSetPriority.\n - The \\ref ThreadStates \"RUNNING\" thread transfers into the \\ref ThreadStates \"BLOCKED\" state when it is delayed, waiting for an event or suspended.\n - Active threads can be terminated any time using the function \\ref osThreadTerminate. Threads can terminate also by just\n   returning from the thread function. Threads that are terminated are in the \\ref ThreadStates \"INACTIVE\" state and typically do not consume\n   any dynamic memory resources. \n\n\\note \nRefer to \\ref threadConfig for RTX5 configuration options.\n\n\\anchor thread_examples\nThread Examples\n===============\nThe following examples show various scenarios to create threads:\n \n<b>Example 1 - Create a simple thread</b> \n\nCreate a thread out of the function thread1 using all default values for thread attributes and memory from the\n\\ref GlobalMemoryPool.\n \n\\code\n__NO_RETURN void thread1 (void *argument) {\n  // ...\n  for (;;) {}\n}\n \nint main (void) {\n  osKernelInitialize();\n  ;\n  osThreadNew(thread1, NULL, NULL);     // Create thread with default settings\n  ;\n  osKernelStart(); \n}\n\\endcode\n\n<b>Example 2 - Create thread with stack non-default stack size</b>\n \nSimilar to the simple thread all attributes are default. The stack is dynamically allocated from the \\ref GlobalMemoryPool\n \n\\ref osThreadAttr_t.stack_size is used to pass the stack size in Bytes to \\ref osThreadNew.\n\n\\code\n__NO_RETURN void thread1 (void *argument) {\n  // ...\n  for (;;) {}\n}\n \nconst osThreadAttr_t thread1_attr = {\n  .stack_size = 1024                            // Create the thread stack with a size of 1024 bytes\n};\n \nint main (void) {\n  ;  \n  osThreadNew(thread1, NULL, &thread1_attr);    // Create thread with custom sized stack memory\n  ;\n}\n\\endcode\n\n<b>Example 3 - Create thread with statically allocated stack</b>\n \nSimilar to the simple thread all attributes are default. The stack is statically allocated using the \\c uint64_t array\n\\c thread1_stk_1. This allocates 64*8 Bytes (=512 Bytes) with an alignment of 8 Bytes (mandatory for Cortex-M stack memory). \n \n\\ref osThreadAttr_t.stack_mem holds a pointer to the stacks lowest address. \n \n\\ref osThreadAttr_t.stack_size is used to pass the stack size in Bytes to \\ref osThreadNew.\n\n\\code\n__NO_RETURN void thread1 (void *argument) {\n  // ...\n  for (;;) {}\n}\n \nstatic uint64_t thread1_stk_1[64];\n \nconst osThreadAttr_t thread1_attr = {\n  .stack_mem  = &thread1_stk_1[0],\n  .stack_size = sizeof(thread1_stk_1)\n};\n \nint main (void) {\n  ;  \n  osThreadNew(thread1, NULL, &thread1_attr);    // Create thread with statically allocated stack memory\n  ;\n}\n\\endcode\n\n<b>Example 4 - Thread with statically allocated task control block</b>\n \nTypically this method is chosen together with a statically allocated stack as shown in Example 2. \n\\code \n#include \"cmsis_os2.h\"\n \n//include rtx_os.h for types of RTX objects\n#include \"rtx_os.h\"\n\n__NO_RETURN void thread1 (void *argument) {\n  // ...\n  for (;;) {}\n}\n \nstatic osRtxThread_t thread1_tcb;\n \nconst osThreadAttr_t thread1_attr = {\n  .cb_mem  = &thread1_tcb,\n  .cb_size = sizeof(thread1_tcb),\n};\n \nint main (void) {\n  ;\n  osThreadNew(thread1, NULL, &thread1_attr);    // Create thread with custom tcb memory\n  ;\n}\n\\endcode\n\n<b>Example 5 - Create thread with a different priority</b> \n \nThe default priority of RTX is \\ref osPriorityNormal. Often you want to run a task with a higher or lower priority. Using the\n\\ref osThreadAttr_t control structure you can set any initial priority required.\n\n\\code\n__NO_RETURN void thread1 (void *argument) {\n  // ...\n  for (;;) {}\n}\n \nconst osThreadAttr_t thread1_attr = {\n  .priority = osPriorityHigh                    //Set initial thread priority to high   \n};\n \nint main (void) {\n  ;\n  osThreadNew(thread1, NULL, &thread1_attr);\n  ;\n}\n\\endcode\n\n\\anchor joinable_threads\n<b>Example 6 - Joinable threads</b>\n \nIn this example a master thread creates four threads with the \\ref osThreadJoinable attribute. These will do some work and\nreturn using the \\ref osThreadExit call after finished. \\ref osThreadJoin is used to synchronize the thread termination. \n\n\n\\code \n__NO_RETURN void worker (void *argument) {\n  ; // work a lot on data[] \n  osDelay(1000U);\n  osThreadExit();\n}\n \n__NO_RETURN void thread1 (void *argument) {\n  osThreadAttr_t worker_attr;\n  osThreadId_t worker_ids[4];\n  uint8_t data[4][10];\n\n  memset(&worker_attr, 0, sizeof(worker_attr));\n  worker_attr.attr_bits = osThreadJoinable;\n \n  worker_ids[0] = osThreadNew(worker, &data[0][0], &worker_attr);\n  worker_ids[1] = osThreadNew(worker, &data[1][0], &worker_attr);\n  worker_ids[2] = osThreadNew(worker, &data[2][0], &worker_attr);\n  worker_ids[3] = osThreadNew(worker, &data[3][0], &worker_attr);\n \n  osThreadJoin(worker_ids[0]);\n  osThreadJoin(worker_ids[1]);\n  osThreadJoin(worker_ids[2]);\n  osThreadJoin(worker_ids[3]);\n \n  osThreadExit(); \n}\n\\endcode\n   \n@{\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\enum osThreadState_t\n\\details\nState of a thread as retrieved by \\ref osThreadGetState. In case \\b osThreadGetState fails or if it is called from an ISR, it\nwill return \\c osThreadError, otherwise it returns the thread state.\n\n\\var osThreadState_t::osThreadInactive\n\\details The thread is created but not actively used, or has been terminated (returned for static control block allocation, when memory pools are used \\ref osThreadError is returned as the control block is no longer valid)\n\n\\var osThreadState_t::osThreadReady\n\\details The thread is ready for execution but not currently running.\n\n\\var osThreadState_t::osThreadRunning\n\\details The thread is currently running.\n\n\\var osThreadState_t::osThreadBlocked\n\\details The thread is currently blocked (delayed, waiting for an event or suspended).\n\n\\var osThreadState_t::osThreadTerminated\n\\details The thread is terminated and all its resources are not yet freed (applies to \\ref joinable_threads \"joinable threads).\n\n\\var osThreadState_t::osThreadError\n\\details The thread does not exist (has raised an error condition) and cannot be scheduled.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\enum osPriority_t\n\\details\n\nThe \\b osPriority_t value specifies the priority for a thread. The default thread priority should be \\a osPriorityNormal.\nIf an active thread becomes ready that has a higher priority than the currently running thread then a thread switch occurs\nimmediately. The system continues executing the thread with the higher priority.\n\nTo prevent from a priority inversion, a CMSIS-RTOS compliant OS may optionally implement a <b>priority inheritance</b>\nmethod. A priority inversion occurs when a high priority thread is waiting for a resource or event that is controlled by a\nthread with a lower priority. Thus causing the high priority thread potentially being blocked forever by another thread\nwith lower priority. To come over this issue the low priority thread controlling the resource should be treated as having\nthe higher priority until it releases the resource.\n\n\\note Priority inheritance only applies to mutexes.\n\n\\var osPriority_t::osPriorityIdle\n\\details This lowest priority should not be used for any other thread. \n\n\\var osPriority_t::osPriorityISR \n\\details This highest priority might be used by the RTOS implementation but must not be used for any user thread.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\typedef void (*osThreadFunc_t) (void *argument)\n\\details Entry function for threads. Setting up a new thread (\\ref osThreadNew) will start execution with a call into this\nentry function. The optional argument can be used to hand over arbitrary user data to the thread, i.e. to identify the thread\nor for runtime parameters.\n\n\\param[in] argument Arbitrary user data set on \\ref osThreadNew.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\typedef osThreadId_t\n\\details Returned by:\n- \\ref osThreadNew\n- \\ref osThreadGetId\n- \\ref osThreadEnumerate\n- \\ref osMutexGetOwner\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\struct osThreadAttr_t\n\\details\nSpecifies the following attributes for the \\ref osThreadNew function.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osThreadJoinable\n\\details\nBitmask for a thread that can be joined.\nIntended for use in \\e attr_bits of \\ref osThreadAttr_t type argument for \\ref osThreadNew function.\n\nA thread in this state can be joined using \\ref osThreadJoin.\n*/\n\n/**\n\\def osThreadDetached\n\\details\nBitmask for a thread that cannot be joined.\nIntended for use in \\e attr_bits of \\ref osThreadAttr_t type argument for \\ref osThreadNew function.\n\nA thread in this state cannot be joined using \\ref osThreadJoin.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osThreadUnprivileged\n\\details\nBitmask for a thread that runs in unprivileged mode.\nIntended for use in \\e attr_bits of \\ref osThreadAttr_t type argument for \\ref osThreadNew function.\n\nIn \\b unprivileged processor mode, a thread:\n- has limited access to the MSR and MRS instructions, and cannot use the CPS instruction.\n- cannot access the system timer, NVIC, or system control block.\n- might have restricted access to memory or peripherals.\n\n\\note Ignored on processors that only run in privileged mode.\n\nRefer to the target processor User's Guide for details.\n*/\n\n/**\n\\def osThreadPrivileged\n\\details\nBitmask for a thread that runs in privileged mode.\nIntended for use in \\e attr_bits of \\ref osThreadAttr_t type argument for \\ref osThreadNew function.\n\nIn \\b privileged processor mode, the application software can use all the instructions and has access to all resources.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osThreadZone(n)\n\\param  n MPU Protected Zone value.\n\\brief  MPU zone value in attribute bit field format.\n\\details\n\nThe preprocessor macro \\b osThreadZone constructs attribute bitmask with MPU zone bits set to \\a n.\n\n<b>Code Example:</b>\n\\code\n/* ThreadB thread attributes */\nconst osThreadAttr_t thread_B_attr = {\n  .name      = \"ThreadB\",       // human readable thread name\n  .attr_bits = osThreadZone(3U) // assign thread to MPU zone 3\n};\n\\endcode\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr)\n\\details\nThe function \\b osThreadNew starts a thread function by adding it to the list of active threads and sets it to state\n\\ref ThreadStates \"READY\". Arguments for the thread function are passed using the parameter pointer \\a *argument. When the priority of the\ncreated thread function is higher than the current \\ref ThreadStates \"RUNNING\" thread, the created thread function starts instantly and\nbecomes the new \\ref ThreadStates \"RUNNING\" thread. Thread attributes are defined with the parameter pointer \\a attr. Attributes include\nsettings for thread priority, stack size, or memory allocation.\n\nThe function can be safely called before the RTOS is\nstarted (call to \\ref osKernelStart), but not before it is initialized (call to \\ref osKernelInitialize).\n\nThe function \\b osThreadNew returns the pointer to the thread object identifier or \\token{NULL} in case of an error.\n\n\\note Cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\nRefer to the \\ref thread_examples \"Thread Examples\" section.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn const char *osThreadGetName (osThreadId_t thread_id)\n\\details\nThe function \\b osThreadGetName returns the pointer to the name string of the thread identified by parameter \\a thread_id or\n\\token{NULL} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\nvoid ThreadGetName_example (void) {\n  osThreadId_t thread_id = osThreadGetId();\n  const char* name = osThreadGetName(thread_id);\n  if (name == NULL) {\n    // Failed to get the thread name; not in a thread\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osThreadGetClass (osThreadId_t thread_id);\n\\details\nThe function \\b osThreadGetClass returns safety class assigned to the thread identified by parameter \\a thread_id. In case of an\nerror, it returns \\ref osErrorId.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osThreadGetZone (osThreadId_t thread_id);\n\\details\nThe function \\b osThreadGetZone returns the MPU Protected Zone value assigned to the thread identified by parameter \\a thread_id.\nIn case of an error, it returns \\ref osErrorId.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osThreadId_t osThreadGetId (void)\n\\details\nThe function \\b osThreadGetId returns the thread object ID of the currently running thread or NULL in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\nvoid ThreadGetId_example (void) {\n  osThreadId_t id;                              // id for the currently running thread\n   \n  id = osThreadGetId();\n  if (id == NULL) {\n    // Failed to get the id\n  }\n}\n\\endcode\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osThreadState_t osThreadGetState (osThreadId_t thread_id)\n\\details\nThe function \\b osThreadGetState returns the state of the thread identified by parameter \\a thread_id. In case it fails or\nif it is called from an ISR, it will return \\c osThreadError, otherwise it returns the thread state (refer to\n\\ref osThreadState_t for the list of thread states).\n \n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority)\n\\details\nThe function \\b osThreadSetPriority changes the priority of an active thread specified by the parameter \\a thread_id to the\npriority specified by the parameter \\a priority. \n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the priority of the specified thread has been changed successfully.\n    - \\em osErrorParameter: \\a thread_id is \\token{NULL} or invalid or \\a priority is incorrect.\n    - \\em osErrorResource: the thread is in an invalid state.\n    - \\em osErrorISR: the function \\b osThreadSetPriority cannot be called from interrupt service routines.\n    - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified thread.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Thread_1 (void const *arg) {               // Thread function\n  osThreadId_t id;                              // id for the currently running thread\n  osStatus_t   status;                          // status of the executed function\n \n  :\n  id = osThreadGetId();                         // Obtain ID of current running thread\n \n  status = osThreadSetPriority(id, osPriorityBelowNormal);  // Set thread priority\n  if (status == osOK) {\n    // Thread priority changed to BelowNormal\n  }\n  else {\n    // Failed to set the priority\n  }\n  :\n}\n\\endcode\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osPriority_t osThreadGetPriority (osThreadId_t thread_id)\n\\details\nThe function \\b osThreadGetPriority returns the priority of an active thread specified by the parameter \\a thread_id.\n\nPossible \\ref osPriority_t return values:\n    - \\em priority: the priority of the specified thread.\n    - \\em osPriorityError: priority cannot be determined or is illegal. It is also returned when the function is called from\n      \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Thread_1 (void const *arg) {               // Thread function\n  osThreadId_t id;                              // id for the currently running thread\n  osPriority_t priority;                        // thread priority\n   \n  id = osThreadGetId();                         // Obtain ID of current running thread\n  priority = osThreadGetPriority(id);           // Obtain the thread priority\n}\n\\endcode\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadYield (void)\n\\details\nThe function \\b osThreadYield passes control to the next thread with the same priority that is in the \\ref ThreadStates \"READY\" state. \nIf there is no other thread with the same priority in state \\ref ThreadStates \"READY\", then the current thread continues execution and\nno thread switch occurs. \\b osThreadYield does not set the thread to state \\ref ThreadStates \"BLOCKED\". Thus no thread with a lower\npriority will be scheduled even if threads in state \\ref ThreadStates \"READY\" are available.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: control has been passed to the next thread successfully.\n    - \\em osError: an unspecified error has occurred.\n    - \\em osErrorISR: the function \\b osThreadYield cannot be called from interrupt service routines.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note This function <b>has no impact</b> when called when the kernel is locked, see \\ref osKernelLock.\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Thread_1 (void const *arg) {               // Thread function\n  osStatus_t status;                            // status of the executed function\n  :\n  while (1) {\n    status = osThreadYield();\n    if (status != osOK) {\n      // an error occurred\n    }\n  }\n}\n\\endcode\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadSuspend (osThreadId_t thread_id)\n\\details\nThe function \\b osThreadSuspend suspends the execution of the thread identified by parameter \\em thread_id. The thread is put\ninto the \\ref ThreadStates \"BLOCKED\" state (\\ref osThreadBlocked). Suspending the running thread will cause a context switch to another\nthread in \\ref ThreadStates \"READY\" state immediately. The suspended thread is not executed until explicitly resumed with the function \\ref osThreadResume. \n\nThreads that are already \\ref ThreadStates \"BLOCKED\" are removed from any wait list and become ready when they are resumed.\nThus it is not recommended to suspend an already blocked thread.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the thread has been suspended successfully.\n    - \\em osErrorParameter: \\a thread_id is \\token{NULL} or invalid.\n    - \\em osErrorResource: the thread is in an invalid state.\n    - \\em osErrorISR: the function \\b osThreadSuspend cannot be called from interrupt service routines.\n    - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified thread.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note This function <b>must not</b> be called to suspend the running thread when the kernel is locked, i.e. \\ref osKernelLock.\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadResume (osThreadId_t thread_id)\n\\details\nThe function \\b osThreadResume puts the thread identified by parameter \\em thread_id (which has to be in \\ref ThreadStates \"BLOCKED\" state)\nback to the \\ref ThreadStates \"READY\" state. If the resumed thread has a higher priority than the running thread a context switch occurs immediately.\n\nThe thread becomes ready regardless of the reason why the thread was blocked. Thus it is not recommended to resume a thread not suspended\nby \\ref osThreadSuspend.\n\nFunctions that will put a thread into \\ref ThreadStates \"BLOCKED\" state are:\n\\ref osEventFlagsWait and \\ref osThreadFlagsWait,\n\\ref osDelay and \\ref osDelayUntil,\n\\ref osMutexAcquire and \\ref osSemaphoreAcquire,\n\\ref osMessageQueueGet,\n\\ref osMemoryPoolAlloc,\n\\ref osThreadJoin,\n\\ref osThreadSuspend.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the thread has been resumed successfully.\n    - \\em osErrorParameter: \\a thread_id is \\token{NULL} or invalid.\n    - \\em osErrorResource: the thread is in an invalid state.\n    - \\em osErrorISR: the function \\b osThreadResume cannot be called from interrupt service routines.\n    - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified thread.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note This function <b>may be</b> called when kernel is locked (\\ref osKernelLock). Under this circumstances\n\ta potential context switch is delayed until the kernel gets unlocked, i.e. \\ref osKernelUnlock or \\ref osKernelRestoreLock.\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadDetach (osThreadId_t thread_id)\n\\details\nThe function \\b osThreadDetach changes the attribute of a thread (specified by \\em thread_id) to \\ref osThreadDetached.\nDetached threads are not joinable with \\ref osThreadJoin. When a detached thread is terminated, all resources are returned to\nthe system. The behavior of \\ref osThreadDetach on an already detached thread is undefined.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the attribute of the specified thread has been changed to detached successfully.\n    - \\em osErrorParameter: \\a thread_id is \\token{NULL} or invalid.\n    - \\em osErrorResource: the thread is in an invalid state.\n    - \\em osErrorISR: the function \\b osThreadDetach cannot be called from interrupt service routines.\n    - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified thread.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadJoin (osThreadId_t thread_id)\n\\details\nThe function \\b osThreadJoin waits for the thread specified by \\em thread_id to terminate. If that thread has already\nterminated, then \\ref osThreadJoin returns immediately. The thread must be joinable. By default threads are created with the\nattribute \\ref osThreadDetached.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: if the thread has already been terminated and joined or once the thread has been terminated and the join\n      operations succeeds.\n    - \\em osErrorParameter: \\a thread_id is \\token{NULL} or invalid.\n    - \\em osErrorResource: the thread is in an invalid state (ex: not joinable).\n    - \\em osErrorISR: the function \\b osThreadJoin cannot be called from interrupt service routines.\n    - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified thread.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\". <br>\n\\note Only one thread shall call \\b osThreadJoin to join the target thread. If multiple threads try to join simultaneously with the same thread,\n       the results are undefined.\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn __NO_RETURN void osThreadExit (void)\n\\details\n\nThe function \\b osThreadExit terminates the calling thread. This allows the thread to be synchronized with \\ref osThreadJoin.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\n__NO_RETURN void worker (void *argument) {\n  // do something\n  osDelay(1000U);\n  osThreadExit();\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadTerminate (osThreadId_t thread_id)\n\\details\nThe function \\b osThreadTerminate removes the thread specified by parameter \\a thread_id from the list of active threads. If\nthe thread is currently \\ref ThreadStates \"RUNNING\", the thread terminates and the execution continues with the next \\ref ThreadStates \"READY\" thread. If no\nsuch thread exists, the function will not terminate the running thread, but return \\em osErrorResource.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the specified thread has been removed from the active thread list successfully.\n    - \\em osErrorParameter: \\a thread_id is \\token{NULL} or invalid.\n    - \\em osErrorResource: the thread is in an invalid state or no other \\ref ThreadStates \"READY\" thread exists.\n    - \\em osErrorISR: the function \\b osThreadTerminate cannot be called from interrupt service routines.\n    - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified thread.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\\note Avoid calling the function with a \\em thread_id that does not exist or has been terminated already.\n\\note \\b osThreadTerminate destroys non-joinable threads and removes their thread_id from the system. Subsequent access to the\nthread_id (for example \\ref osThreadGetState) will return an \\ref osThreadError. Joinable threads will not be destroyed and\nreturn the status \\ref osThreadTerminated until they are joined with \\ref osThreadJoin.\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Thread_1 (void *arg);                      // function prototype for Thread_1\n \nvoid ThreadTerminate_example (void) {\n  osStatus_t status;\n  osThreadId_t id;\n \n  id = osThreadNew(Thread_1, NULL, NULL);       // create the thread\n                                                // do something\n  status = osThreadTerminate(id);               // stop the thread\n  if (status == osOK) {\n                                                // Thread was terminated successfully\n  }\n  else {\n                                                // Failed to terminate a thread\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osThreadGetStackSize (osThreadId_t thread_id)\n\\details\nThe function \\b osThreadGetStackSize returns the stack size of the thread specified by parameter \\a thread_id. In case of an\nerror, it returns \\token{0}.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osThreadGetStackSpace (osThreadId_t thread_id); \n\\details\nThe function \\b osThreadGetStackSpace returns the size of unused stack space for the thread specified by parameter\n\\a thread_id. Stack watermark recording during execution needs to be enabled (refer to \\ref threadConfig). In case of an\nerror, it returns \\token{0}.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osThreadGetCount (void)\n\\details\nThe function \\b osThreadGetCount returns the number of active threads or \\token{0} in case of an error.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items)\n\\details\nThe function \\b osThreadEnumerate returns the number of enumerated threads or \\token{0} in case of an error.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadFeedWatchdog (uint32_t ticks);\n\\details\nThe function \\b osThreadFeedWatchdog restarts watchdog of the current running thread. If the thread watchdog is not fed again within the \\a ticks interval\n\\ref osWatchdogAlarm_Handler will be called.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the watchdog timer was restarted successfully.\n    - \\em osError: cannot be executed (kernel not running).\n    - \\em osErrorISR: the function \\b osThreadFeedWatchdog cannot be called from interrupt service routines.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example:</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Thread_1 (void const *arg) {          // Thread function\n  osStatus_t status;                       // Status of the executed function\n  :\n  while (1) {\n    status = osThreadFeedWatchdog(500U);   // Feed thread watchdog for 500 ticks\n    // verify status value here\n    :\n  }\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadProtectPrivileged (void);\n\\details\nThe function \\b osThreadProtectPrivileged disables creation of new privileged threads. After its successful execution, no new\nthreads with privilege execution mode (\\ref osThreadPrivileged attribute) can be created.\nKernel shall be in ready state or running when \\b osThreadProtectPrivileged is called.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the creation of new privileged threads is disabled.\n    - \\em osError: cannot be executed (kernel not ready).\n    - \\em osErrorISR: the function \\b osThreadProtectPrivileged cannot be called from interrupt service routines.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example:</b>\n\\code\n#include \"cmsis_os2.h\"\n \nint main (void) {\n  osStatus_t status;\n  :\n  status = osKernelInitialize();        // Initialize CMSIS-RTOS2 kernel\n  // verify status value here.\n  :                                     // Create privileged threads\n  status = osThreadProtectPrivileged(); // Disable creation of new privileged threads.\n  // verify status value here.\n  :                                     // Start the kernel\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadSuspendClass (uint32_t safety_class, uint32_t mode);\n\\details\nThe function \\b osThreadSuspendClass suspends execution of threads based on safety class assignment. \\a safety_class provides the reference safety class value, while \\a mode is considered as a bitmap that additionally specifies the safety classes to be suspended.\n\nIf \\ref osSafetyWithSameClass is set in \\a mode than the threads with safety class value equal to \\a safety_class will be suspended.\n<br>\nIf \\ref osSafetyWithLowerClass is set in \\a mode than the threads with safety class value lower than \\a safety_class will be suspended.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the threads with specified safety class have been suspended successfully.\n    - \\em osErrorParameter: \\a safety_class is invalid.\n    - \\em osErrorResource: no other \\ref ThreadStates \"READY\" thread exists.\n    - \\em osErrorISR: the function \\b osThreadSuspendClass is called from interrupt other than \\ref osWatchdogAlarm_Handler.\n    - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class specified by \\a safety_class and \\a mode.\n\n<b>Code Example:</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid SuspendNonCriticalClasses (void) {\n  osStatus_t status;\n \n  status = osThreadSuspendClass(4U, osSafetyWithSameClass | osSafetyWithLowerClass); // Suspends threads with safety class 4 or lower\n  // verify status value here.\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadResumeClass (uint32_t safety_class, uint32_t mode);\n\\details\nThe function \\b osThreadResumeClass resumes execution of threads based on safety class assignment. \\a safety_class provides the reference safety class value, while \\a mode is considered as a bitmap that additionally specifies the safety classes to be resumed.\n\nIf \\ref osSafetyWithSameClass is set in \\a mode than the threads with safety class value equal to \\a safety_class will be resumed.\n<br>\nIf \\ref osSafetyWithLowerClass is set in \\a mode than the threads with safety class value lower than \\a safety_class will be resumed.\n\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the threads with specified safety class have been resumed successfully.\n    - \\em osErrorParameter: \\a safety_class is invalid.\n    - \\em osErrorISR: the function \\b osThreadResumeClass is called from interrupt other than \\ref osWatchdogAlarm_Handler.\n    - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class specified by \\a safety_class and \\a mode.\n\n<b>Code Example:</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid ResumeNonCriticalClasses (void) {\n  osStatus_t status;\n \n  status = osThreadResumeClass(4U, osSafetyWithSameClass | osSafetyWithLowerClass); // Resumes threads with safety class 4 or lower\n  // verify status value here.\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn osStatus_t osThreadTerminateZone (uint32_t zone);\n\\details\nThe function \\b osThreadTerminateZone terminates execution of threads assigned to the MPU Protected Zone as given by \\a zone parameter.\n\nPossible \\ref osStatus_t return values:\n    - \\em osOK: the threads within the specified MPU Protected Zone have been terminated successfully.\n    - \\em osErrorParameter: \\a zone is invalid.\n    - \\em osErrorResource: no other \\ref ThreadStates \"READY\" thread exists.\n    - \\em osErrorISR: the function \\b osThreadTerminateZone is called from interrupt other than fault.\n    - \\em osError: the function \\b osThreadTerminateZone is called from thread.\n\n\\note \\b osThreadTerminateZone destroys non-joinable threads and removes their thread IDs from the system. Subsequent access to a terminated thread via its thread ID (for example \\ref osThreadGetState) will return an \\ref osThreadError. Joinable threads will not be destroyed and return the status \\ref osThreadTerminated until they are joined with \\ref osThreadJoin.\n\n<b>Code Example:</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid TerminateFaultedThreads (void) {  // to be called from an exception fault context\n  osStatus_t status;\n \n  status = osThreadTerminateZone(3U); // Terminates threads assigned to MPU Protected Zone 3\n  // verify status value here.\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t osWatchdogAlarm_Handler (osThreadId_t thread_id);\n\\details\nThe callback function \\b osWatchdogAlarm_Handler is called by the kernel when a thread watchdog expires.\nParameter \\a thread_id identifies the thread which has the expired thread watchdog.\nThe function needs to be implemented in user application.\n\nReturn new reload value to restart the watchdog. Return \\token{0} to stop the thread watchdog.\n\n\\note The callback function is called from interrupt.\n\n\\note\nWhen multiple watchdogs expire in the same tick, this function is called for each thread with highest safety class first.\n\n<b>Code Example:</b>\n\\code\n#include \"cmsis_os2.h\"\n \nuint32_t osWatchdogAlarm_Handler (osThreadId_t thread_id) {\n  uint32_t safety_class;\n  uint32_t next_interval;\n\n  safety_class = osThreadGetClass(thread_id);\n  \n  /* Handle the watchdog depending on how safety-critical is the thread */\n  if (safety_class < ...){\n    :\n  } else {\n    :\n  }\n \n  return next_interval;\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn void osZoneSetup_Callback (uint32_t zone);\n\\details\nThe callback function \\b osZoneSetup_Callback is called by the kernel when MPU Protected Zone changes.\nThe function shall be implemented in user application.\n\n<b>Code Example:</b>\n\\code\n/* Update MPU settings for newly activating Zone */\nvoid osZoneSetup_Callback (uint32_t zone) {\n \n  if (zone >= ZONES_NUM) {\n    //Issue an error for incorrect zone value\n  }\n \n  ARM_MPU_Disable();\n  ARM_MPU_Load(mpu_table[zone], MPU_REGIONS);\n  ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);\n}\n\\endcode\n\n\\c ZONES_NUM is the total amount of zones allocated by the application.\nFor \\c ARM_MPU_... functions refer to <a href=\"../../Core/html/group__mpu__functions.html\"><b>MPU Functions</b></a> in CMSIS-Core documentation.\n*/\n\n/// @}\n\n\n// these struct members must stay outside the group to avoid double entries in documentation\n/**\n\n\\var osThreadAttr_t::attr_bits\n\\details\nThe following bit masks can be used to set options:\n - \\ref osThreadDetached : create thread in a detached mode (default).\n - \\ref osThreadJoinable : create thread in \\ref joinable_threads \"joinable mode\".  \n - \\ref osThreadUnprivileged : create thread to execute in unprivileged mode.\n - \\ref osThreadPrivileged : create thread to execute in privileged mode.  \n - \\ref osThreadZone (m) : create thread assigned to MPU zone \\token{m}.\n - \\ref osSafetyClass (n) : create thread with safety class \\token{n} assigned to it.\n\nDefault: \\token{0} no options set. Safety class and MPU Zone are inherited from running thread. Thread privilege mode is set based on configuration \\ref threadConfig_procmode.\n\n\\var osThreadAttr_t::cb_mem\n\\details\nPointer to a memory for the thread control block object. Refer to \\ref StaticObjectMemory for more information.\n\nDefault: \\token{NULL} to use \\ref CMSIS_RTOS_MemoryMgmt_Automatic for the thread control block.\n\n\\var osThreadAttr_t::cb_size\n\\details\nThe size (in bytes) of memory block passed with \\ref cb_mem. For RTX, the minimum value is defined with \\ref osRtxThreadCbSize (higher values are permitted).\n\nDefault: \\token{0} as the default is no memory provided with \\ref cb_mem.\n\n\\var osThreadAttr_t::name\n\\details\nPointer to a constant string with a human readable name (displayed during debugging) of the thread object.\n\nDefault: \\token{NULL} no name specified (debugger may display function name instead).\n\n\\var osThreadAttr_t::priority\n\\details\nSpecifies the initial thread priority with a value from #osPriority_t.\n\nDefault: \\token{osPriorityNormal}.\n\n\\var osThreadAttr_t::reserved\n\\details\nReserved for future use.\n\n\\var osThreadAttr_t::stack_mem\n\\details\nPointer to a memory location for the thread stack (64-bit aligned). \n\nDefault: \\token{NULL} to allocate stack from a fixed-size memory pool using \\ref ThreadStack.\n\n\\var osThreadAttr_t::stack_size\n\\details\nThe size (in bytes) of the stack specified by \\ref stack_mem.\n\nDefault: \\token{0} as the default is no memory provided with \\ref stack_mem.\n\n\\var osThreadAttr_t::tz_module\n\\details\n\\if (ARMv8M)\nTrustZone Thread Context Management Identifier to allocate context memory for threads. The RTOS kernel that runs in\nnon-secure state calls the interface functions defined by the header file TZ_context.h. Can safely be set to zero\nfor threads not using secure calls at all. \nSee <a href=\"../../Core/html/group__context__trustzone__functions.html\">TrustZone RTOS Context Management</a>.\n\nDefault: \\token{0} not thread context specified.\n\\else\nApplicable only for devices on Armv8-M architecture. Ignored on others.\n\\endif\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_ThreadFlags.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Thread Flags Management ====\n/** \n\\addtogroup CMSIS_RTOS_ThreadFlagsMgmt Thread Flags\n\\ingroup CMSIS_RTOS\n\\brief Synchronize threads using flags.\n\\details\nThread Flags are a more specialized version of the Event Flags. See \\ref CMSIS_RTOS_EventFlags.\nWhile Event Flags can be used to globally signal a number of threads, thread flags are only send to a single specific thread.\nEvery thread instance can receive thread flags without any additional allocation of a thread flags object.\n\n\\note Thread flag management functions cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\", except\nfor \\ref osThreadFlagsSet.\n\n<b>Usage Example</b>\n\nThe following (incomplete) code excerpt sketches the usage principals for <b>Thread Flags</b>.\n\nThe behavior is the following:\n-\tapp_main starts executing\n-\tstatement A sets thread flags to 0x02 (flags = 0x02 – after set)\n-\tapp_main enters delay\n-\texecution switches to threadX\n-\tstatement B waits for flag 0x01 and blocks since flag is not set\n-\texecution switches to app_main\n-\tstatement C sets thread flags to 0x07\n-\tthreadX wakes-up and clears flag 0x01, thread flags = 0x06, return value set to 0x07 (before clear), note: all this happens during statement C\n-\tstatement C returns with flags = 0x06\n-\tapp_main enters delay\n-\texecution switches to threadX\n-\tstatement B returns with flagsX = 0x07\n \n\\code\n#include \"cmsis_os2.h\"\n \nosThreadId_t tid;\nuint32_t     flagsX;\nuint32_t     flags;\n \nvoid threadX (void *argument) {\n  \n  osDelay(1U);\n  for (;;) {\n    flagsX = osThreadFlagsWait(0x0001U, osFlagsWaitAny, osWaitForever); /* B */\n  }\n}\n \nvoid app_main (void *argument) {\n \n  tid = osThreadNew(threadX, NULL, NULL);\n \n  flags = osThreadFlagsSet(tid, 0x0002U); /* A */\n  osDelay(2U);\n  flags = osThreadFlagsSet(tid, 0x0005U); /* C */\n  osDelay(2U);\n \n  for(;;);\n}\n\\endcode\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags )\nThe function \\b osThreadFlagsSet sets the thread flags for a thread specified by parameter \\em thread_id. The thread returns\nthe flags stored in the thread control block, or an error code if highest bit is set (refer to \\ref flags_error_codes).\nRefer to \\b Usage \\b Examples below to understand how the return value is computed.\n\nThe target thread waiting for a flag to be set will resume from \\ref ThreadStates \"BLOCKED\" state.\n\nPossible \\ref flags_error_codes return values:\n    - \\em osFlagsErrorUnknown: unspecified error.\n    - \\em osFlagsErrorParameter: parameter \\em thread_id is not a valid thread or \\em flags has highest bit set.\n    - \\em osFlagsErrorResource: the thread is in invalid state.\n    - \\em osFlagsErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified thread.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n\\b Code \\b Example\n\\code\n/*----------------------------------------------------------------------------\n *      Function 'signal_func' called from multiple threads\n *---------------------------------------------------------------------------*/\nvoid signal_func (osThreadId_t tid)  {\n  osThreadFlagsSet(tid_clock, 0x0100U);     /* set signal to clock thread    */\n  osDelay(500U);                            /* delay 500ms                   */\n  osThreadFlagsSet(tid_clock, 0x0100U);     /* set signal to clock thread    */\n  osDelay(500U);                            /* delay 500ms                   */\n  osThreadFlagsSet(tid, 0x0001U);           /* set signal to thread 'thread' */\n  osDelay(500U);                            /* delay 500ms                   */\n}\n\\endcode\n\n\\b Usage \\b Examples\n\nThe following diagram assumes that in the control block of Thread1 the flag 1 is already set. Thread2 now sets flag 2 and\nThread1 returns the updated value immediately:\n\n\\msc\n a [label=\"\",    textcolor=\"indigo\", linecolor=\"indigo\", arclinecolor=\"red\"],\n b [label=\"\",    textcolor=\"blue\",   linecolor=\"blue\",   arclinecolor=\"blue\"];\n \n a note a [label=\"Thread1\",       textbgcolour=\"#FFCCCF\"],\n b note b [label=\"Thread2\",       textbgcolour=\"#E0E0FF\"];\n \n a box a [label = \"Flags == 1\"];\n a<-b [label = \"osThreadFlagsSet(2)\"];\n a>>b [label = \"return(3)\"];\n a->a [label = \"while(1)\"];\n\\endmsc\n\nDepending on thread scheduling, the flag status can be modified before returning: \n\n\\msc\n a [label=\"\",    textcolor=\"indigo\", linecolor=\"indigo\", arclinecolor=\"red\"],\n b [label=\"\",    textcolor=\"blue\",   linecolor=\"blue\",   arclinecolor=\"blue\"];\n \n a note a [label=\"Thread1\",       textbgcolour=\"#FFCCCF\"],\n b note b [label=\"Thread2\",       textbgcolour=\"#E0E0FF\"];\n \n b box b [label = \"Flags == 0\"];\n b->b [label = \"osThreadFlagsWait(1)\"];\n b box b [label = \"thread state = blocked\"];\n a->b [label = \"osThreadFlagsSet(1)\"];\n b box b [label = \"Flags == 1\"];\n b box b [label = \"thread state = ready\"];\n b box b [label = \"Flags == 0*\"];\n --- [label = \"If Thread2 priority > Thread1 priority, it gets scheduled immediately\"];\n b->b [label = \"return(1)\"];\n b->b [label = \"osThreadFlagsWait(1)\"];\n b box b [label = \"thread state = blocked\"];\n --- [label = \"endif\"];\n b->a [label = \"return(0)\"];\n\\endmsc\n\\note * In this case \\ref osThreadFlagsWait auto-clears the flag.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn uint32_t osThreadFlagsClear (uint32_t flags)\n\\details\nThe function \\b osThreadFlagsClear clears the specified flags for the currently running thread. It returns the\nflags before clearing, or an error code if highest bit is set (refer to \\ref flags_error_codes).\n\nPossible \\ref flags_error_codes return values:\n    - \\em osFlagsErrorUnknown: unspecified error, i.e. not called from a running threads context.\n    - \\em osFlagsErrorParameter: parameter \\em flags has highest bit set.\n    - \\em osFlagsErrorISR: the function \\b osThreadFlagsClear cannot be called from interrupt service routines.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn uint32_t osThreadFlagsGet (void)\n\\details\nThe function \\b osThreadFlagsGet returns the flags currently set for the currently running thread. \nIf called without a active and currently running thread \\b osThreadFlagsGet return zero.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \\fn uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout)\nThe function \\b osThreadFlagsWait suspends the execution of the currently \\ref ThreadStates \"RUNNING\" thread until any or all of the thread\nflags specified with the parameter \\a flags are set. When these thread flags are already set, the function returns instantly.\nOtherwise the thread is put into the state \\ref ThreadStates \"BLOCKED\".\n\nThe parameter \\em options specifies the wait condition:\n|Option              |                                                       |\n|--------------------|-------------------------------------------------------|\n|\\b osFlagsWaitAny   |   Wait for any flag (default).                        |\n|\\b osFlagsWaitAll   |   Wait for all flags.                                 |\n|\\b osFlagsNoClear   |   Do not clear flags which have been specified to wait for.  |\n\nIf \\c osFlagsNoClear is set in the options \\ref osThreadFlagsClear can be used to clear flags manually.\nOtherwise \\b osThreadFlagsWait automatically clears the flags waited for.\n\nThe parameter \\ref CMSIS_RTOS_TimeOutValue \"timeout\" represents a number of timer ticks and is an upper bound. The\nexact time delay depends on the actual time elapsed since the last timer tick. \n\nThe function returns the flags before clearing, or an error code if highest bit is set (refer to \\ref flags_error_codes).\n\nPossible \\ref flags_error_codes return values:\n    - \\em osFlagsErrorUnknown: unspecified error, i.e. not called from a running threads context.\n    - \\em osFlagsErrorTimeout: awaited flags have not been set in the given time.\n    - \\em osFlagsErrorResource: awaited flags have not been set when no \\a timeout was specified.\n    - \\em osFlagsErrorParameter: Parameter \\em flags has highest bit set.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Thread (void* arg) {\n  ;\n  osThreadFlagsWait(0x00000001U, osFlagsWaitAny, osWaitForever); // Wait forever until thread flag 1 is set.\n  ;\n  osThreadFlagsWait(0x00000003U, osFlagsWaitAny, osWaitForever); // Wait forever until either thread flag 0 or 1 is set.\n  ;\n  osThreadFlagsWait(0x00000003U, osFlagsWaitAll, 10U); // Wait for 10 timer ticks until thread flags 0 and 1 are set. Timeout afterwards.\n  ;\n  osThreadFlagsWait(0x00000003U, osFlagsWaitAll | osFlagsNoClear, osWaitForever); // Same as the above, but the flags will not be cleared.\n}\n\\endcode\n*/\n/// @}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Timer.txt",
    "content": "\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Timer Management Functions ====\n/** \n\\addtogroup CMSIS_RTOS_TimerMgmt Timer Management\n\\ingroup CMSIS_RTOS\n\\brief Create and control timer and timer callback functions.\n\\details \nIn addition to the \\ref CMSIS_RTOS_Wait CMSIS-RTOS also supports virtual timer objects. These timer objects can\ntrigger the execution of a function (not threads). When a timer expires, a callback function is executed to run associated\ncode with the timer. Each timer can be configured as a one-shot or a  periodic timer. A periodic timer repeats its operation\nuntil it is \\ref osTimerDelete \"deleted\" or \\ref osTimerStop \"stopped\". All timers can be\n\\ref osTimerStart \"started, restarted\", or \\ref osTimerStop \"stopped\".\n\n\\note RTX handles Timers in the thread \\b osRtxTimerThread. Callback functions run under control of this thread and may use\nother CMSIS-RTOS API calls. The \\b osRtxTimerThread is configured in \\ref timerConfig.\n\\note Timer management functions cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\nThe figure below shows the behavior of a periodic timer. For one-shot timers, the timer stops after execution of the\ncallback function.\n\n\\image html \"Timer.png\" \"Behavior of a Periodic Timer\"\n\n\nWorking with Timers\n--------------------\nThe following steps are required to use a software timer:\n-# Define the timers:\n\\code\nosTimerId_t one_shot_id, periodic_id;\n\\endcode\n-# Define callback functions:\n\\code\nstatic void one_shot_Callback (void *argument) {\n  int32_t arg = (int32_t)argument; // cast back argument '0' \n  // do something, i.e. set thread/event flags\n}\nstatic void periodic_Callback (void *argument) {\n  int32_t arg = (int32_t)argument; // cast back argument '5'\n  // do something, i.e. set thread/event flags\n}\n\\endcode\n-# Instantiate and start the timers:\n\\code\n// creates a one-shot timer:\none_shot_id = osTimerNew(one_shot_Callback, osTimerOnce, (void *)0, NULL);     // (void*)0 is passed as an argument\n                                                                               // to the callback function\n// creates a periodic timer:\nperiodic_id = osTimerNew(periodic_Callback, osTimerPeriodic, (void *)5, NULL); // (void*)5 is passed as an argument\n                                                                               // to the callback function\nosTimerStart(one_shot_id, 500U);\nosTimerStart(periodic_id, 1500U);\n \n// start the one-shot timer again after it has triggered the first time:\nosTimerStart(one_shot_id, 500U);\n \n// when timers are not needed any longer free the resources:\nosTimerDelete(one_shot_id);\nosTimerDelete(periodic_id);\n\\endcode\n\n@{\n*/\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\enum osTimerType_t\n\\details\nThe \\ref osTimerType_t specifies the a repeating (periodic) or one-shot timer for the function \\ref osTimerNew.\n\n\\var osTimerType_t::osTimerOnce\n\\details\nThe timer is not automatically restarted once it has elapsed. It can be restarted manually using \\ref osTimerStart as needed.\n\n\\var osTimerType_t::osTimerPeriodic\n\\details \nThe timer repeats automatically and triggers the callback continuously while running, see \\ref osTimerStart and \\ref osTimerStop.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\typedef osTimerId_t \n\\details\nInstances of this type hold a reference to a timer object. \\n\nReturned by:\n- \\ref osTimerNew\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\typedef void (*osTimerFunc_t) (void *argument)\n\\details\nThe timer callback function is called every time the timer elapses.\n\nThe callback might be executed either in a dedicated timer thread or in interrupt context. Thus it is recommended to only\nuse ISR callable functions from the timer callback.\n\n\\param[in] argument The argument provided to \\ref osTimerNew.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\struct osTimerAttr_t \n\\details\nSpecifies the following attributes for the \\ref osTimerNew function.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr)\n\\details\nThe function \\b osTimerNew creates an one-shot or periodic timer and associates it with a callback function with \\a argument.\nThe timer is in stopped state until it is started with \\ref osTimerStart. The function can be safely called before the RTOS\nis started (call to \\ref osKernelStart), but not before it is initialized (call to \\ref osKernelInitialize).\n\nThe function \\b osTimerNew returns the pointer to the timer object identifier or \\token{NULL} in case of an error.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Timer1_Callback (void *arg);               // prototypes for timer callback function\nvoid Timer2_Callback (void *arg);               // prototypes for timer callback function\n \nuint32_t exec1;                                 // argument for the timer call back function\nuint32_t exec2;                                 // argument for the timer call back function\n \nvoid TimerCreate_example (void)  {\n  osTimerId_t id1;                              // timer id\n  osTimerId_t id2;                              // timer id\n \n  // Create one-shoot timer\n  exec1 = 1U;\n  id1 = osTimerNew(Timer1_Callback, osTimerOnce, &exec1, NULL);\n  if (id1 != NULL) {\n    // One-shoot timer created\n  }\n \n  // Create periodic timer\n  exec2 = 2U;\n  id2 = osTimerNew(Timer2_Callback, osTimerPeriodic, &exec2, NULL);\n  if (id2 != NULL) {\n    // Periodic timer created\n  }\n  :\n}\n\\endcode\n*/\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn const char *osTimerGetName (osTimerId_t timer_id)\n\\details\nThe function \\b osTimerGetName returns the pointer to the name string of the timer identified by parameter \\a timer_id or\n\\token{NULL} in case of an error.\n\n\\note This function may be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks)\n\\details\nThe function \\b osTimerStart starts or restarts a timer specified by the parameter \\a timer_id. The parameter \\a ticks\nspecifies the value of the timer in \\ref CMSIS_RTOS_TimeOutValue \"time ticks\".\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the specified timer has been started or restarted.\n - \\em osErrorISR: \\b osTimerStart cannot be called from interrupt service routines.\n - \\em osErrorParameter: parameter \\a timer_id is either \\token{NULL} or invalid or \\a ticks is incorrect.\n - \\em osErrorResource: the timer is in an invalid state.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified timer.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Timer_Callback (void *arg) {               // timer callback function\n                                                // arg contains &exec\n                                                // called every second after osTimerStart\n}\n \nuint32_t exec;                                  // argument for the timer call back function\n \nvoid TimerStart_example (void) {\n  osTimerId_t id;                               // timer id\n  uint32_t    timerDelay;                       // timer value\n  osStatus_t  status;                           // function return status\n \n  // Create periodic timer\n  exec = 1U;\n  id = osTimerNew(Timer_Callback, osTimerPeriodic, &exec, NULL);\n  if (id != NULL)  {\n    timerDelay = 1000U;\n    status = osTimerStart(id, timerDelay);       // start timer\n    if (status != osOK) {\n      // Timer could not be started\n    }\n  }\n  ;\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osTimerStop (osTimerId_t timer_id)\n\\details\nThe function \\b osTimerStop stops a timer specified by the parameter \\a timer_id.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the specified timer has been stopped.\n - \\em osErrorISR: \\b osTimerStop cannot be called from interrupt service routines.\n - \\em osErrorParameter: parameter \\a timer_id is either \\token{NULL} or invalid.\n - \\em osErrorResource: the timer is not running (you can only stop a running timer).\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified timer.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Timer_Callback (void *arg);                // prototype for timer callback function\n \nuint32_t exec;                                  // argument for the timer call back function\n \nvoid TimerStop_example (void) {\n  osTimerId_t id;                               // timer id\n  osStatus_t  status;                           // function return status\n \n  // Create periodic timer\n  exec = 1U;\n  id = osTimerNew(Timer_Callback, osTimerPeriodic, &exec, NULL);\n  osTimerStart(id, 1000U);                      // start timer\n  :\n  status = osTimerStop(id);                     // stop timer\n  if (status != osOK) {\n    // Timer could not be stopped\n  }\n  ;\n  osTimerStart(id, 1000U);                      // start timer again\n  ;\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osTimerIsRunning (osTimerId_t timer_id)\n\\details\nThe function \\b osTimerIsRunning checks whether a timer specified by parameter \\a timer_id is running. It returns \\token{1}\nif the timer is running and \\token{0} if the timer is stopped or an error occurred.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osTimerDelete (osTimerId_t timer_id)\n\\details\nThe function \\b osTimerDelete deletes the timer specified by parameter \\a timer_id.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the specified timer has been deleted.\n - \\em osErrorISR: \\b osTimerDelete cannot be called from interrupt service routines.\n - \\em osErrorParameter: parameter \\a timer_id is either \\token{NULL} or invalid.\n - \\em osErrorResource: the timer is in an invalid state.\n - \\em osErrorSafetyClass: the calling thread safety class is lower than the safety class of the specified timer.\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Timer_Callback (void *arg);                // prototype for timer callback function\n \nuint32_t exec;                                  // argument for the timer call back function\n \nvoid TimerDelete_example (void) {\n  osTimerId_t id;                               // timer id\n  osStatus_t  status;                           // function return status  \n \n  // Create periodic timer\n  exec = 1U;\n  id = osTimerNew(Timer_Callback, osTimerPeriodic, &exec, NULL);\n  osTimerStart(id, 1000U);                      // start timer\n  ;\n  status = osTimerDelete(id);                   // stop and delete timer\n  if (status != osOK) {\n    // Timer could not be deleted\n  } \n  ;\n}\n\\endcode\n*/\n/// @}\n\n// these struct members must stay outside the group to avoid double entries in documentation\n/**\n\\var osTimerAttr_t::attr_bits\n\\details\nReserved for future use (must be set to '0' for future compatibility).\n\n\\var osTimerAttr_t::cb_mem\n\\details\nPointer to a memory for the timer control block object. Refer to \\ref StaticObjectMemory for more information.\n\nDefault: \\token{NULL} to use \\ref CMSIS_RTOS_MemoryMgmt_Automatic for the timer control block.\n\n\\var osTimerAttr_t::cb_size\n\\details\nThe size (in bytes) of memory block passed with \\ref cb_mem. For RTX, the minimum value is defined with \\ref osRtxTimerCbSize (higher values are permitted).\n\nDefault: \\token{0} as the default is no memory provided with \\ref cb_mem.\n\n\\var osTimerAttr_t::name\n\\details\nPointer to a constant string with a human readable name (displayed during debugging) of the timer object.\n\nDefault: \\token{NULL} no name specified.\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Tutorial.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page rtos2_tutorial Tutorial\n\nThis tutorial is an introduction to using a small footprint real-time operating system on an Arm Cortex-M microcontroller.\nIf you are used to writing procedural-based 'C' code on small 8-/16-bit microcontrollers, you may be doubtful about the need\nfor such an operating system. If you are not familiar with using an RTOS in real-time embedded systems, you should read this\nchapter before dismissing the idea. The use of an RTOS represents a more sophisticated design approach, inherently fostering\nstructured code development which is enforced by the RTOS application programming interface (API). \n\nThe RTOS structure allows you to take a more object-orientated design approach, while still programming in 'C'. The RTOS\nalso provides you with multithreaded support on a small microcontroller. These two features actually create quite a shift in\ndesign philosophy, moving us away from thinking about procedural ‘C’ code and flow charts. Instead we consider the\nfundamental program threads and the flow of data between them. The use of an RTOS also has several additional benefits which\nmay not be immediately obvious. Since an RTOS based project is composed of well-defined threads, it helps to improve project\nmanagement, code reuse, and software testing.\n\nThe tradeoff for this is that an RTOS has additional memory requirements and increased interrupt latency. Typically, the\nKeil RTX5 RTOS will require 500 bytes of RAM and 5k bytes of code, but remember that some of the RTOS code would be\nreplicated in your program anyway. We now have a generation of small low-cost microcontrollers that have enough on-chip\nmemory and processing power to support the use of an RTOS. Developing using this approach is therefore much more accessible.\n\nWe will first look at setting up an introductory RTOS project for a Cortex-M based microcontroller. Next, we\nwill go through each of the RTOS primitives and how they influence the design of our application code. Finally, when we have\na clear understanding of the RTOS features, we will take a closer look at the RTOS configuration options. If you are used to\nprogramming a microcontroller without using an RTOS i.e. bare metal, there are two key things to understand as you work\nthrough this tutorial. In the first section, we will focus on creating and managing Threads. The key concept here is to\nconsider them running as parallel concurrent objects. In the second section, we will look at how to communicate between\nthreads. In this section the key concept is synchronization of the concurrent threads.\n\n\n\\section rtos2_tutorial_pre Prerequisites\n\nIt is assumed that you have Keil MDK installed on your PC. For download and installation instructions, please visit\nthe <a href=\"https://www2.keil.com/mdk5/install/\" target=\"_blank\">Getting Started</a> page. Once you have set up the tool,\nopen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Devices</b> tab to look for the <b>STM32F103</b> device.\n- On the <b>Packs</b> tab, download and install the latest <b>Keil:STM32F1xx_DFP</b> pack and the latest\n  <b>Hitex:CMSIS_RTOS2_Turorial</b> pack.\n\n\\note It is assumed that you are familiar with Arm Keil MDK and have basic 'C' programming knowledge.\n\n\n\\section rtos2_tutorial_first_steps First Steps with Keil RTX5\n\nThe RTOS itself consists of a scheduler which supports round-robin, pre-emptive and co-operative multitasking of program\nthreads, as well as time and memory management services. Inter-thread communication is supported by additional RTOS objects,\nincluding signal thread and event flags, semaphores, mutex, message passing and a memory pool system. As we will see,\ninterrupt handling can also be accomplished by prioritized threads which are scheduled by the RTOS kernel.\n\n\\image html rtos_components.png\n\n\n\\section rtos2_tutorial_access Accessing the CMSIS-RTOS2 API\n\nTo access any of the CMSIS-RTOS2 features in our application code, it is necessary to include the following header file.\n\\code\n#include <cmsis_os2.h>\n\\endcode\nThis header file is maintained by Arm as part of the CMSIS-RTOS2 standard. For Keil RTX5, this is the default API. Other\nRTOS will have their own proprietary API but may provide a wrapper layer to implement the CMSIS-RTOS2 API so they can be\nused where compatibility with the CMSIS standard is required.\n\n\n\\section rtos2_tutorial_threads Threads\n\nThe building blocks of a typical 'C' program are functions which we call to perform a specific procedure and which then\nreturn to the calling function. In CMSIS-RTOS2, the basic unit of execution is a \"Thread\". A Thread is very similar to a 'C'\nprocedure but has some very fundamental differences.\n\\code\nunsigned int procedure (void) {\n  ...\n\treturn(ch);      \t\t\n}\n \nvoid thread (void) {\n  while(1) {\n    ...\n\t}\n}\t\n \n__NO_RETURN void Thread1(void*argument) {\n  while(1) {\n    ...\n  }\n}\n\\endcode\nWhile we always return from our 'C' function, once started an RTOS thread must contain a loop so that it never terminates\nand thus runs forever. You can think of a thread as a mini self-contained program that runs within the RTOS. With the Arm\nCompiler, it is possible to optimize a thread by using a \\c __NO_RETURN macro. This attribute reduces the cost of calling a\nfunction that never returns.\n\nAn RTOS program is made up of a number of threads, which are controlled by the RTOS scheduler. This scheduler uses the\nSysTick timer to generate a periodic interrupt as a time base. The scheduler will allot a certain amount of execution time\nto each thread. So \\c thread1 will run for 5 ms then be de-scheduled to allow \\c thread2 to run for a similar period;\n\\c thread2 will give way to \\c thread3 and finally control passes back to \\c thread1. By allocating these slices of runtime\nto each thread in a round-robin fashion, we get the appearance of all three threads running in parallel to each other. \n\nConceptually we can think of each thread as performing a specific functional unit of our program with all threads running\nsimultaneously. This leads us to a more object-orientated design, where each functional block can be coded and tested in\nisolation and then integrated into a fully running program. This not only imposes a structure on the design of our final\napplication but also aids debugging, as a particular bug can be easily isolated to a specific thread. It also aids code\nreuse in later projects. When a thread is created, it is also allocated its own thread ID. This is a variable which acts as\na handle for each thread and is used when we want to manage the activity of the thread.\n\\code\nosThreadId_t id1, id2, id3;\n\\endcode\nIn order to make the thread-switching process happen, we have the code overhead of the RTOS and we have to dedicate a CPU\nhardware timer to provide the RTOS time reference. In addition, each time we switch running threads, we have to save the\nstate of all the thread variables to a thread stack. Also, all the runtime information about a thread is stored in a thread\ncontrol block, which is managed by the RTOS kernel. Thus the “context switch time”, that is, the time to save the current\nthread state and load up and start the next thread, is a crucial figure and will depend on both the RTOS kernel and the\ndesign of the underlying hardware.\n\nThe Thread Control Block contains information about the status of a thread. Part of this information is its run state. In a\ngiven system, only one thread can be running and all the others will be suspended but ready to run. The RTOS has various\nmethods of inter-thread communication (signals, semaphores, messages). Here, a thread may be suspended to wait to be\nsignaled by another thread or interrupt before it resumes its ready state, whereupon it can be placed into running state by\nthe RTOS scheduler.\n\n| State   | Description |\n|---------|-------------|\n| Running | The currently running thread |\n| Ready   | Threads ready to run |\n| Wait    | Blocked threads waiting for an OS event |\n\nAt any given moment a single thread may be running. The remaining threads will be ready to run and will be scheduled by the\nkernel. Threads may also be waiting pending an OS event. When this occurs they will return to the ready state and be\nscheduled by the kernel.\n\n\n\\section rtos2_tutorial_start Starting the RTOS\n\nTo build a simple RTOS, program we declare each thread as a standard 'C' function and also declare a thread ID variable for\neach function.\n\\code\nvoid thread1 (void);\t\nvoid thread2 (void);\n \nosThreadId thrdID1, thrdID2;\n\\endcode\nOnce the processor leaves the reset vector, we will enter the \\c main() function as normal. Once in \\c main(), we must call\n\\ref osKernelInitialize() to setup the RTOS. It is not possible to call any RTOS function before the\n\\ref osKernelInitialize() function has successfully completed. Once \\ref osKernelInitialize() has completed, we can create\nfurther threads and other RTOS objects. This can be done by creating a launcher thread, in the example below this is called\n\\c app_main(). Inside the \\c app_main() thread, we create all the RTOS threads and objects we need to start our application\nrunning. As we will see later, it is also possible to dynamically create and destroy RTOS objects as the application is\nrunning. Next, we can call \\ref osKernelStart() to start the RTOS and the scheduler task switching. You can run any\ninitializing code you want before starting the RTOS to setup peripherals and initialize the hardware.\n\\code\nvoid app_main(void *argument) {\n  T_led_ID1 = osThreadNew(led_Thread1, NULL, &ThreadAttr_LED1);\n  T_led_ID2 = osThreadNew(led_Thread2, NULL, &ThreadAttr_LED2);\n  osDelay(osWaitForever);\n  while (1)\n    ;\n}\n \nvoid main(void) {\n  IODIR1 = 0x00FF0000;               // Do any C code you want\n  osKernelInitialize();              // Initialize the kernel\n  osThreadNew(app_main, NULL, NULL); // Create the app_main() launcher thread\n  osKernelStart();                   // Start the RTOS\n}\n\\endcode\nWhen threads are created they are also assigned a priority. If there are a number of threads ready to run and they all have\nthe same priority, they will be allotted run time in a round-robin fashion. However, if a thread with a higher priority\nbecomes ready to run, the RTOS scheduler will de-schedule the currently running thread and start the high priority thread\nrunning. This is called pre-emptive priority-based scheduling. When assigning priorities, you have to be careful because the\nhigh priority thread will continue to run until it enters a waiting state or until a thread of equal or higher priority is\nready to run.\n\n\\subsection rtos2_tutorial_ex1 Exercise 1 - A First CMSIS-RTOS2 Project\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 01 First Project</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\section rtos2_tutorial_thread_create Creating Threads\n\nOnce the RTOS is running, there are a number of system calls that are used to manage and control the active threads. The\ndocumentation lists \\ref CMSIS_RTOS_ThreadMgmt \"all thread management functions\".\n\nAs we saw in the first example, the \\c app_main() thread is used as a launcher thread to create the application threads.\nThis is done in two stages. First a thread structure is defined; this allows us to define the thread operating parameters.\n\\code\nosThreadId thread1_id; // thread handle\n \nstatic const osThreadAttr_t threadAttr_thread1 = {\n\t“Name_String \",\t     //Human readable Name for debugger\n    Attribute_bits Control_Block_Memory,\n    Control_Block_Size,\n    Stack_Memory,\n    Stack_Size,\n    Priority,\n    TrustZone_ID,\n    reserved};\n\\endcode\nThe thread structure requires us to define the name of the thread function, its thread priority, any special attribute bits,\nits TrustZone_ID and its memory allocation. This is quite a lot of detail to go through but we will cover everything by the\nend of this application note. Once the thread structure has been defined, the thread can be created using the\n\\ref osThreadNew() API call. Then the thread is created from within the application code, this is often the within the\n\\c app_main() thread but a thread can be created at any point within any thread.\n\\code\nthread1_id = osThreadNew(name_Of_C_Function, argument,&threadAttr_thread1);\n\\endcode\nThis creates the thread and starts it running. It is also possible to pass a parameter to the thread when it starts.\n\\code\nuint32_t startupParameter = 0x23;\nthread1_id = osThreadNew(name_Of_C_Function, (uint32_t)startupParameter,&threadAttr_thread1);\n\\endcode\n\n\n\\subsection rtos2_tutorial_ex2 Exercise 2 - Creating and Managing Threads \n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 02 Threads</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\section rtos2_tutorial_thread_mgmt Thread Management and Priority\n\nWhen a thread is created it is assigned a priority level. The RTOS scheduler uses a thread’s priority to decide which thread\nshould be scheduled to run. If a number of threads are ready to run, the thread with the highest priority will be placed in\nthe run state. If a high priority thread becomes ready to run it will preempt a running thread of lower priority.\nImportantly, a high priority thread running on the CPU will not stop running unless it blocks on an RTOS API call or is\npreempted by a higher priority thread. A thread's priority is defined in the thread structure and the following priority\ndefinitions are available. The default priority is \\ref osPriorityNormal. The \\ref osPriority_t value specifies the priority\nfor a thread.\n\nOnce the threads are running, there are a small number of RTOS system calls which are used to manage the running threads. It\nis also then possible to elevate or lower a thread’s priority either from another function or from within its own code.\n\\code\nosStatus   osThreadSetPriority(threadID, priority);\nosPriority osThreadGetPriority(threadID);\n\\endcode\nAs well as creating threads, it is also possible for a thread to delete another active thread from the RTOS. Again, we use\nthe thread ID rather than the function name of the thread.\n\\code\nosStatus = osThreadTerminate (threadID1);\n\\endcode\t\t\nIf a thread wants to terminate itself then there is a dedicated exit function.\n\\code\nosThreadExit (void)\n\\endcode\nFinally, there is a special case of thread switching where the running thread passes control to the next ready thread of the\nsame priority. This is used to implement a third form of scheduling called co-operative thread switching.\n\\code\nosStatus osThreadYield();\t\t//switch to next ready to run thread at the same priority\n\\endcode\n\n\n\\section rtos2_tutorial_ex2_mem_mgmt Memory Management\n\nWhen each thread is created, it is assigned its own stack for storing data during the context switch. This should not be\nconfused with the native Cortex-M processor stack; it is really a block of memory that is allocated to the thread. A\ndefault stack size is defined in the RTOS configuration file (we will see this later) and this amount of memory will be\nallocated to each thread unless we override it to allocate a custom size. The default stack size will be assigned to a\nthread if the stack size value in the thread definition structure is set to zero. If necessary a thread can be given\nadditional memory resources by defining a bigger stack size in the thread structure. Keil RTX5 supports several memory\nmodels to assign this thread memory. The default model is a global memory pool. In this model each RTOS object that is\ncreated (threads, message queues, semaphores etc.) are allocated memory from a single block of memory.\n \nIf an object is destroyed the memory it has been assigned is returned to the memory pool. This has the advantage of memory\nreuse but also introduces the possible problem of memory fragmentation.\n\nThe size of the global memory pool is defined in the configuration file:\n\\code\n#define OS_DYNAMIC_MEM_SIZE         4096\n\\endcode \t\nAnd the default stack size for each thread is defined in the threads section:\n\\code\n#define OS_STACK_SIZE               256\n\\endcode \nIt is also possible to define object specific memory pools for each different type of RTOS object. In this model you define\nthe maximum number of a specific object type and its memory requirements. The RTOS then calculates and reserves the required\nmemory usage.\n \nThe object specific model is again defined in the RTOS configuration file by enabling the \"object specific memory\" option\nprovided in each section of the configuration file:\n\\code\n#define OS_SEMAPHORE_OBJ_MEM        1\n#define OS_SEMAPHORE_NUM            1\n\\endcode\nIn the case of simple object which requires a fixed memory allocation we just need to define the maximum number of a given\nobject type. In the case of more complex objects such as threads we will need to define the required memory usage:\n\\code\n#define OS_THREAD_OBJ_MEM           1\n#define OS_THREAD_NUM               1\n#define OS_THREAD_DEF_STACK_NUM     0\n#define OS_THREAD_USER_STACK_SIZE   1024\n\\endcode \nTo use the object specific memory allocation model with threads we must provide details of the overall thread memory usage.\nFinally it is possible to statically allocate the thread stack memory. This is important for safety related systems where\nmemory usage has to be rigorously defined.\n\n\n\\subsection rtos2_tutorial_ex3 Exercise 3 - Memory Model\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 03 Memory Model</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\n\\section rtos2_tutorial_multi_inst Multiple Instances\n\nOne of the interesting possibilities of an RTOS is that you can create multiple running instances of the same base thread\ncode. For example, you could write a thread to control a UART and then create two running instances of the same thread code.\nHere, each instance of the UART code could manage a different UART. Then we can create two instances of the thread assigned\nto different thread handles. A parameter is also passed to allow each instance to identify which UART it is responsible for.\n\\code\n#define UART1 (void *) 1UL\n#define UART2 (void *) 2UL\n \nThreadID_1_0 = osThreadNew (thread1, UART1, &ThreadAttr_Task1);\nThreadID_1_1 = osThreadNew (thread1, UART0, &ThreadAttr_Task1);\n\\endcode\n\n\n\\subsection rtos2_tutorial_multi_inst_ex4 Exercise 4 - Multiple Instances\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 04 Multiple Instances</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\section rtos2_tutorial_thread_join Joinable Threads\n\nA new feature in CMSIS-RTOS2 is the ability to create threads in a 'joinable' state. This allows a thead to be created and\nexecuted as a standard thread. In addition, a second thread can join it by calling \\ref osThreadJoin(). This will cause the\nsecond thread to deschedule and remain in a waiting state until the thread which has been joined is terminated. This allows\na temporary joinable thread to be created, which would acquire a block of memory from the global memory pool, this thread\ncould perform some processing and then terminate, releasing the memory back to the memory pool. A joinable thread can be\ncreated by setting the joinable attribute bit in the thread attributes structure as shown below:\n\\code\nstatic const osThreadAttr_t ThreadAttr_worker = {\n\t.attr_bits = osThreadJoinable\n};\n\\endcode\nOnce the thread has been created, it will execute following the same rules as 'normal' threads. Any other thread can then\njoin it by using the OS call:\n\\code\nosThreadJoin(<joinable_thread_handle>);\n\\endcode\nOnce \\ref osThreadJoin() has been called, the thread will deschedule and enter a waiting state until the joinable thread has\nterminated.\n\n\n\\subsection rtos2_tutorial_ex4 Exercise 5 - Joinable Threads\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 05 Join</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\section rtos2_tutorial_time_mgmt Time Management\n\nAs well as running your application code as threads, the RTOS also provides some timing services which can be accessed\nthrough RTOS system calls. \n\n\n\\subsection rtos2_tutorial_time_delay Time Delay\n\nThe most basic of these timing services is a simple timer delay function. This is an easy way of providing timing delays\nwithin your application. Although the RTOS kernel size is quoted as 5 KB, features such as delay loops and simple scheduling\nloops are often part of a non-RTOS application and would consume code bytes anyway, so the overhead of the RTOS can be less\nthan it immediately appears.\n\\code\nvoid osDelay (uint32_t ticks)\n\\endcode\nThis call will place the calling thread into the WAIT_DELAY state for the specified number of milliseconds. The scheduler\nwill pass execution to the next thread in the READY state. \n \nWhen the timer expires, the thread will leave the WAIT_DELAY  state and move to the READY state. The thread will resume\nrunning when the scheduler moves it to the RUNNING state. If the thread then continues executing without any further\nblocking OS calls, it will be descheduled at the end of its time slice and be placed in the ready state, assuming another\nthread of the same priority is ready to run.\n\n\n\\subsection rtos2_tutorial_abs_time_delay Absolute Time Delay\n\nIn addition to the \\ref osDelay() function which gives a relative time delay starting from the instant it is called, there\nis also a delay function which halts a thread until a specific point in time:\n\\code\nosStatus osDelayUntil (uint32_t ticks)\t \n\\endcode\nThe \\ref osDelayUntil() function will halt a thread until a specific value of kernel timer ticks is reached. There are a\nnumber of kernel functions that allow you to read both the current SysTick count and the kernel ticks count.\n\n| Kernel timer functions |\n|------------------------|\n| uint64_t \\ref osKernelGetTickCount(void)     |\n| uint32_t \\ref osKernelGetTickFreq(void)      |\n| uint32_t \\ref osKernelGetSysTimerCount(void) |\n| uint32_t \\ref osKernelGetSysTimerFreq(void)  |\n\n\n\\subsection rtos2_tutorial_ex6 Exercise 6 - Time Management\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 06 Time Management</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsection rtos2_tutorial_virtual_timers Virtual Timers\n\nThe CMSIS-RTOS API can be used to define any number of virtual timers which act as count down timers. When they expire, they\nwill run a user call-back function to perform a specific action. Each timer can be configured as a one shot or repeat timer.\nA virtual timer is created by first defining a timer structure:\n\\code\nstatic const struct osTimerAttr_t timerAttr_timer0 = {\n  const char* name;      ///< name of the timer\n  uint32_t    attr_bits; ///< attribute bits\n  void*       cb_mem;    ///< memory for control block\n  uint32_t    cb_size;   ///< size of provided memory for control block\n}\n\\endcode\nThis defines a name for the timer. The timer must then be instantiated by an RTOS\nthread providing a pointer to the callback function and its parameter.:\n\\code\nosTimerId_t timer0_handle;\ntimer0_handle = osTimerNew(&callback, osTimerPeriodic,(void *)<parameter>, &timerAttr_timer0);\n\\endcode\nThis creates the timer and defines it as a periodic timer or a single shot timer (\\ref osTimerOnce()). The next parameter\npasses an argument to the call back function when the timer expires:\n\\code\nosTimerStart (timer0_handle,0x100);\n\\endcode\nThe timer can then be started at any point in a thread the timer start function invokes the timer by its handle and defines\na count period in kernel ticks.\n\n\n\\subsection rtos2_tutorial_ex7 Exercise 7 - Virtual Timer\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 07 Virtual Timers</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsection rtos2_tutorial_idle_thread Idle Thread\n\nThe final timer service provided by the RTOS isn't really a timer, but this is probably the best place to discuss it. If\nduring our RTOS program we have no thread running and no thread ready to run (e.g. they are all waiting on delay functions),\nthen the RTOS will start to run the Idle Thread. This thread is automatically created when the RTOS starts and runs at the\nlowest priority. The Idle Thread function is located in the RTX_Config.c file:\n\\code \n__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n \n  for (;;) {}\n}\n\\endcode\nYou can add any code to this thread, but it has to obey the same rules as user threads. The simplest use of the idle demon\nis to place the microcontroller into a low-power mode when it is not doing anything.\n\\code \n__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n \n  for (;;) {\n    __WFE();\n  }\n}\n\\endcode\nWhat happens next depends on the power mode selected in the microcontroller. At a minimum, the CPU will halt until an\ninterrupt is generated by the SysTick timer and execution of the scheduler will resume. If there is a thread ready to run,\nthen execution of the application code will resume. Otherwise, the idle demon will be reentered and the system will go back\nto sleep.\n\n\n\\subsection rtos2_tutorial_ex8 Exercise 8 - Idle Thread\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 08 Idle Thread</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\section rtos2_tutorial_interthread_com Inter-thread Communication\n\nSo far, we have seen how application code can be defined as independent threads and how we can access the timing services\nprovided by the RTOS. In a real application, we need to be able to communicate between threads in order to make an\napplication useful. To this end, a typical RTOS supports several different communication objects which can be used to link\nthe threads together to form a meaningful program. The CMSIS-RTOS2 API supports inter-thread communication with thread and\nevent flags, semaphores, mutexes, mailboxes and message queues. In the first section, the key concept was concurrency. In\nthis section, the key concept is synchronizing the activity of multiple threads.\n\n\n\\subsection rtos2_tutorial_thread_flags Thread Flags\n\nKeil RTX5 supports up to thirty two thread flags for each thread. These thread flags are stored in the thread control block.\nIt is possible to halt the execution of a thread until a particular thread flag or group of thread flags are set by another\nthread in the system.\n\nThe \\ref osThreadFlagsWait() system calls will suspend execution of the thread and place it into the wait_evnt state.\nExecution of the thread will not start until at least one the flags set in the \\ref osThreadFlagsWait() API call have been\nset. It is also possible to define a periodic timeout after which the waiting thread will move back to the ready state, so\nthat it can resume execution when selected by the scheduler. A value of \\ref osWaitForever (0xFFFF) defines an infinite\ntimeout period.\n\\code\nosEvent osThreadFlagsWait (int32_t flags,int32_t options,uint32_t timeout);\n\\endcode\nThe thread flag options are as follows:\n| Options             | Description |\n|---------------------|-------------|\n| \\ref osFlagsWaitAny | Wait for any flag to be set(default) |\n| \\ref osFlagsWaitAll | Wait for all flags to be set |\n| \\ref osFlagsNoClear | Do not clear flags that have been specified to wait for |\n\nIf a pattern of flags is specified, the thread will resume execution when any one of the specified flags is set (Logic OR).\nIf the \\ref osFlagsWaitAll option is used, then all the flags in the pattern must be set (Logic AND). Any thread can set a\nflag on any other thread and a thread may clear its own flags:\n\\code\nint32_t osThredFlagsSet (osThreadId_t  thread_id, int32_t flags);\nint32_t osThreadFlagsClear (int32_t signals);\n\\endcode\n\n\n\\subsubsection rtos2_tutorial_ex9 Exercise 9 - Thread Flags\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 09 Thread Flags</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsection rtos2_tutorial_event_flags Event Flags\n\nEvent flags operate in a similar fashion to thread flags but must be created and then act as a global RTOS object that can\nbe used by all the running threads.\n \nFirst, we need to create a set of event flags, this is a similar process to creating a thread. We define an event flag\nattribute structure. The attribute structure defines an ASCII name string, attribute bits, and memory detention. If we are\nusing the static memory model.\n\\code\nosEventFlagsAttr_t {\n  const char *name;   ///< name of the event flags\n  uint32_t attr_bits; ///< attribute bits (none)\n  void *cb_mem;       ///< memory for control block\n  uint32_t cb_size;   ///< size of provided memory for control block\n};\n\\endcode\nNext we need a handle to control access the event flags:\n\\code\nosEventFlagsId_t EventFlag_LED;\n\\endcode\nThen we can create the event flag object:\n\\code\nEventFlag_LED = osEventFlagsNew(&EventFlagAttr_LED);\n\\endcode\nRefer to \\ref CMSIS_RTOS_EventFlags for more information.\n\n\n\\subsubsection rtos2_tutorial_ex10 Exercise 10 - Event Flags\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 10 Event Flags</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsection rtos2_tutorial_semaphores Semaphores\n\nLike thread flags, semaphores are a method of synchronizing activity between two or more threads. Put simply, a semaphore is\na container that holds a number of tokens. As a thread executes, it will reach an RTOS call to acquire a semaphore token. If\nthe semaphore contains one or more tokens, the thread will continue executing and the number of tokens in the semaphore will\nbe decremented by one. If there are currently no tokens in the semaphore, the thread will be placed in a waiting state until\na token becomes available. At any point in its execution, a thread may add a token to the semaphore causing its token count\nto increment by one.\n\nThe diagram above illustrates the use of a semaphore to synchronize two threads. First, the semaphore must be created and\ninitialized with an initial token count. In this case the semaphore is initialized with a single token. Both threads will\nrun and reach a point in their code where they will attempt to acquire a token from the semaphore. The first thread to reach\nthis point will acquire the token from the semaphore and continue execution. The second thread will also attempt to acquire\na token, but as the semaphore is empty it will halt execution and be placed into a waiting state until a semaphore token is\navailable. \n\nMeanwhile, the executing thread can release a token back to the semaphore. When this happens, the waiting thread will\nacquire the token and leave the waiting state for the ready state. Once in the ready state the scheduler will place the\nthread into the run state so that thread execution can continue. While semaphores have a simple set of OS calls they can be\none of the more difficult OS objects to fully understand. In this section, we will first look at how to add semaphores to an\nRTOS program and then go on to look at the most useful semaphore applications.\n\nTo use a semaphore in the CMSIS-RTOS you must first declare a semaphore attributes:\n\\code\nosSemaphoreAttr_t {\n  const char *name;   ///< name of the semaphore\n  uint32_t attr_bits; ///< attribute bits (none)\n  void *cb_mem;       ///< memory for control block\n  uint32_t cb_size;   ///< size of provided memory for control block\n};\n\\endcode\nNext declare the semaphore handle:\n\\code\nosSemaphoreId_t sem1;\n\\endcode\nThen within a thread the semaphore container can be initialised with a number of tokens:\n\\code\nsem1 = osSemaphoreNew(maxTokenCount,initalTokencount,&osSemaphoreAttr_t);\n\\endcode\nIt is important to understand that semaphore tokens may also be created and destroyed as threads run. So for example you can\ninitialise a semaphore with zero tokens and then use one thread to create tokens into the semaphore while another thread\nremoves them. This allows you to design threads as producer and consumer threads.\n\nOnce the semaphore is initialized, tokens may be acquired and sent to the semaphore in a similar fashion to event flags. The\n\\ref osSemaphoreAcquire() call is used to block a thread until a semaphore token is available. A timeout period may also be\nspecified with 0xFFFF being an infinite wait.\n\\code\nosStatus osSemaphoreAcquire(osSemaphoreId_t semaphore_id, uint32_t ticks);\n\\endcode\nOnce the thread has finished using the semaphore resource, it can send a token to the semaphore container:\n\\code\nosStatus osSemaphoreRelease(osSemaphoreId_t semaphore_id);\n\\endcode\nAll semaphore functions are listed in the \\ref CMSIS_RTOS_SemaphoreMgmt \"reference\".\n\n\n\\subsubsection rtos2_tutorial_sem_usage Using Semaphores\n\nAlthough semaphores have a simple set of OS calls, they have a wide range of synchronizing applications. This makes them\nperhaps the most challenging RTOS object to understand. In this section we, will look at the most common uses of semaphores.\nThese are taken from free book\n<a href=\"https://greenteapress.com/wp/semaphores/\" target=\"_blank\">\"The Little Book Of Semaphores\" by Allen B. Downey</a>.\n\n\n\\subsubsection rtos2_tutorial_sem_sig Signalling\n\nSynchronizing the execution of two threads is the simplest use of a semaphore:\n\\code\nosSemaphoreId_t sem1;\nstatic const osSemaphoreAttr_t semAttr_SEM1 = {\n    .name = \"SEM1\",\n};\n \nvoid thread1(void) {\n  sem1 = osSemaphoreNew(5, 0, &semAttr_SEM1);\n  while (1) {\n    FuncA();\n    osSemaphoreRelease(sem1)\n  }\n}\n \nvoid task2(void) {\n\n  while (1) {\n    osSemaphoreAcquire(sem1, osWaitForever) FuncB();\n  }\n}\n\\endcode\nIn this case the semaphore is used to ensure that the code in \\c FuncA() is executed before the code in \\c FuncB().\n\n\n\\subsubsection rtos2_tutorial_ex11 Exercise 11 - Semaphore Signalling\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 11 Semaphore Signalling</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsubsection rtos2_tutorial_sem_multi Multiplex\n\nA multiplex is used to limit the number of threads that can access a critical section of code. For example, this could be a\nroutine that accesses memory resources and can only support a limited number of calls.\n\\code\nosSemaphoreId_t multiplex;\nstatic const osSemaphoreAttr_t semAttr_Multiplex = {\n    .name = \"SEM1\",\n};\n \nvoid thread1(void) {\n  multiplex = osSemaphoreCreate(5, 5, &semAttr_Multiplex);\n  while (1) {\n    osSemaphoreAcquire(multiplex, osWaitForever);\n    processBuffer();\n    osSemaphoreRelease(multiplex);\n  }\n}\n\\endcode\nIn this example we initialise the multiplex semaphore with five tokens. Before a thread can call the \\c processBuffer()\nfunction, it must acquire a semaphore token. Once the function has completed, the token is sent back to the semaphore. If\nmore than five threads are attempting to call \\c processBuffer(), the sixth must wait until a thread has finished with\n\\c processBuffer() and returns its token. Thus, the multiplex semaphore ensures that a maximum of five threads can call the\n\\c processBuffer() function \"simultaneously\".\n\n\n\\subsubsection rtos2_tutorial_ex12 Exercise 12 - Multiplex\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 12 Multiplex</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsubsection rtos2_tutorial_sem_rend Rendezvous\n\nA more generalised form of semaphore signalling is a rendezvous. A rendezvous ensures that two threads reach a certain point\nof execution. Neither may continue until both have reached the rendezvous point.\n\\code\nosSemaphoreId_t arrived1, arrived2;\nstatic const osSemaphoreAttr_t semAttr_Arrived1 = {\n    .name = \"Arr1\",\n};\n \nstatic const osSemaphoreAttr_t semAttr_Arrived2 = {\n    .name = \"Arr2\",\n};\n \nvoid thread1(void) {\n  arrived1 = osSemaphoreNew(2, 0);\n  arrived1 = osSemaphoreNew(2, 0);\n  while (1) {\n    FuncA1();\n    osSemaphoreRelease(arrived1);\n    osSemaphoreAcquire(arrived2, osWaitForever);\n    FuncA2();\n  }\n}\n \nvoid thread2(void) {\n  while (1) {\n    FuncB1();\n    os_sem_Release(arrived2);\n    os_sem_Acquire(arrived1, osWaitForever);\n    FuncB2();\n  }\n}\n\\endcode\nIn the above case, the two semaphores will ensure that both threads will rendezvous and then proceed to execute \\c FuncA2()\nand \\c FuncB2().\n\n\\subsubsection rtos2_tutorial_sem_rend_ex13 Exercise 13 - Rendezvous\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 13 Rendezvous</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsubsection rtos2_tutorial_sem_barr_turn Barrier Turnstile\n\nAlthough a rendezvous is very useful for synchronising the execution of code, it only works for two functions. A barrier is\na more generalised form of rendezvous which works to synchronise multiple threads.\n\\code\nosSemaphoreId_t count, barrier;\nstatic const osSemaphoreAttr_t semAttr_Counter = {\n    .name = \"Counter\",\n};\n \nstatic const osSemaphoreAttr_t semAttr_Barier = {\n    .name = \"Barrier\",\n};\n \nunsigned int count;\n \nvoid thread1(void) {\n  Turnstile_In = osSemaphoreNew(5, 0, &semAttr_SEM_In);\n  Turnstile_Out = osSemaphoreNew(5, 1, &semAttr_SEM_Out);\n  Mutex = osSemaphoreNew(1, 1, &semAttr_Mutex);\n  while (1) {\n    osSemaphoreAcquire(Mutex, osWaitForever); // Allow one task at a time to\n                                              // access the first turnstile\n    count = count + 1; // Increment count\n    if (count == 5) {\n      osSemaphoreAcquire(Turnstile_Out,\n                         osWaitForever); // Lock the second turnstile\n      osSemaphoreRelease(Turnstile_In);  // Unlock the first turnstile\n    }\n    osSemaphoreRelease(Mutex); // Allow other tasks to access the turnstile\n    osSemaphoreAcquire(Turnstile_In, osWaitForever); // Turnstile Gate\n    osSemaphoreRelease(Turnstile_In);\n    critical_Function();\n  }\n}\n\\endcode\nIn this code, we use a global variable to count the number of threads which have arrived at the barrier. As each function\narrives at the barrier it will wait until it can acquire a token from the counter semaphore. Once acquired, the count\nvariable will be incremented by one. Once we have incremented the count variable, a token is sent to the counter semaphore\nso that other waiting threads can proceed. Next, the barrier code reads the count variable. If this is equal to the number\nof threads which are waiting to arrive at the barrier, we send a token to the barrier semaphore. \n\nIn the example above we are synchronising five threads. The first four threads will increment the count variable and then\nwait at the barrier semaphore. The fifth and last thread to arrive will increment the count variable and send a token to the\nbarrier semaphore. This will allow it to immediately acquire a barrier semaphore token and continue execution. After passing\nthrough the barrier, it immediately sends another token to the barrier semaphore. This allows one of the other waiting\nthreads to resume execution. This thread places another token in the barrier semaphore which triggers another waiting thread\nand so on. This final section of the barrier code is called a turnstile because it allows one thread at a time to pass the\nbarrier. In our model of concurrent execution this means that each thread waits at the barrier until the last arrives then\nthe all resume simultaneously. In the following exercise we create five instances of one thread containing barrier code.\nHowever, the barrier could be used to synchronise five unique threads.\n\n\n\\subsubsection rtos2_tutorial_ex14 Exercise 14 - Semaphore Barrier\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 14 Barrier</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsubsection rtos2_tutorial_sem_caveats Semaphore Caveats\n\nSemaphores are an extremely useful feature of any RTOS. However semaphores can be misused. You must always remember that the\nnumber of tokens in a semaphore is not fixed. During the runtime of a program semaphore tokens may be created and destroyed.\nSometimes this is useful, but if your code depends on having a fixed number of tokens available to a semaphore you must be\nvery careful to always return tokens back to it. You should also rule out the possibility of accidently creating additional\nnew tokens.\n\n\n\\subsection rtos2_tutorial_mutex Mutex\n\nMutex stands for “Mutual Exclusion”. In reality, a mutex is a specialized version of semaphore. Like a semaphore, a mutex is\na container for tokens. The difference is that a mutex can only contain one token which cannot be created or destroyed. The\nprinciple use of a mutex is to control access to a chip resource such as a peripheral. For this reason a mutex token is\nbinary and bounded. Apart from this it really works in the same way as a semaphore. First of all we must declare the mutex\ncontainer and initialize the mutex:\n\\code\nosMutexId_t uart_mutex;\n \nosMutexAttr_t {\n  const char *name;   ///< name of the mutex\n  uint32_t attr_bits; ///< attribute bits\n  void *cb_mem;       ///< memory for control block\n  uint32_t cb_size;   ///< size of provided memory for control block\n};\n\\endcode\nWhen a mutex is created its functionality can be modified by setting the following attribute bits:\n| Bitmask                 | Description |\n|-------------------------|-------------|\n| \\ref osMutexRecursive   | The same thread can consume a mutex multiple times without locking itself.        |\n| \\ref osMutexPrioInherit | While a thread owns the mutex it cannot be preempted by a higher priority thread. |\n| \\ref osMutexRobust      | Notify threads that acquire a mutex that the previous owner was terminated.       |\n\nOnce declared the mutex must be created in a thread.\n\\code\nuart_mutex = osMutexNew(&MutexAttr);\n\\endcode\nThen any thread needing to access the peripheral must first acquire the mutex token:\n\\code\nosMutexAcquire(osMutexId_t mutex_id,uint32_t ticks);\n\\endcode\nFinally, when we are finished with the peripheral the mutex must be released:\n\\code\nosMutexRelease(osMutexId_t mutex_id);\n\\endcode\nMutex use is much more rigid than semaphore use, but is a much safer mechanism when controlling absolute access to\nunderlying chip registers.\n\n\n\\subsubsection rtos2_tutorial_ex15 Exercise 15 - Mutex\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 15 Mutex</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsubsection rtos2_tutorial_mutex_caveats Mutex Caveats\n\nClearly, you must take care to return the mutex token when you are finished with the chip resource, or you will have\neffectively prevented any other thread from accessing it. You must also be extremely careful about using the\n\\ref osThreadTerminate() call on functions which control a mutex token. Keil RTX5 is designed to be a small footprint RTOS\nso that it can run on even the very small Cortex-M microcontrollers. Consequently, there is no thread deletion safety. This\nmeans that if you delete a thread which is controlling a mutex token, you will destroy the mutex token and prevent any\nfurther access to the guarded peripheral.\n\n\n\\subsection rtos2_tutorial_data_exchange Data Exchange\n\nSo far, all of the inter-thread communication methods have only been used to trigger execution of threads; they do not\nupport the exchange of program data between threads. Clearly, in a real program we will need to move data between threads.\nThis could be done by reading and writing to globally declared variables. In anything but a very simple program, trying to\nguarantee data integrity would be extremely difficult and prone to unforeseen errors. The exchange of data between threads\nneeds a more formal asynchronous method of communication. \n\nCMSIS-RTOS provides two methods of data transfer between threads. The first method is a message queue which creates a\nbuffered data 'pipe' between two threads. The message queue is designed to transfer integer values.\n\nThe second form of data transfer is a mail queue. This is very similar to a message queue except that it transfers blocks of\ndata rather than a single integer.\n\nMessage and mail queues both provide a method for transferring data between threads. This allows you to view your design as\na collection of objects (threads) interconnected by data flows. The data flow is implemented by message and mail queues.\nThis provides both a buffered transfer of data and a well defined communication interface between threads. Starting with a\nsystem level design based on threads connected by mail and message queues allows you to code different subsystems of your\nproject, especially useful if you are working in a team. Also as each thread has well defined inputs and outputs it is easy\nto isolate for testing and code reuse.\n\n\n\\subsubsection rtos2_tutorial_msg_queue Message Queue\n\nTo setup a message queue we first need to allocate the memory resources:\n\\code\nosMessageQId_t Q_LED;\n \nosMessageQueueAttr_t {\n  const char *name;   ///< name of the message queue\n  uint32_t attr_bits; ///< attribute bits\n  void *cb_mem;       ///< memory for control block\n  uint32_t cb_size;   ///< size of provided memory for control block\n  void *mq_mem;       ///< memory for data storage\n  uint32_t mq_size;   ///< size of provided memory for data storage\n};\n\\endcode\nOnce the message queue handle and attributes have been declared we can create the message queue in a thread:\n\\code\nQ_LED = osMessageNew(DepthOfMesageQueue,WidthOfMessageQueue,&osMessageQueueAttr);\n\\endcode\nOnce the message queue has been created we can put data into the queue from one thread:\n\\code\nosMessageQueuePut(Q_LED,&dataIn,messagePrioriy,osWaitForever);\n\\endcode\nand then read if from the queue in another:\n\\code\nresult = osMessageQueueGet(Q_LED,&dataOut,messagePriority,osWaitForever);\n\\endcode\n\n\n\\subsubsection rtos2_tutorial_ex16 Exercise 16 - Message Queue\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 16 Message Queue</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsubsection rtos2_tutorial_ext_msg_queue Extended Message Queue\n\nIn the last example we defined a word wide message queue. If you need to send a larger amount of data it is also possible to\ndefine a message queue where each slot can hold more complex data. First, we can define a structure to hold our message\ndata:\n\\code\ntypedef struct {\n  uint32_t duration;\n  uint32_t ledNumber;\n  uint8_t priority;\n} message_t;\n\\endcode\nThen we can define a message queue which is formatted to receive this type of message:\n\\code\nQ_LED = osMessageQueueNew(16,sizeof(message_t),&queueAttr_Q_LED );\t\n\\endcode\n\n\n\\subsubsection rtos2_tutorial_ex17 Exercise 17 - Message Queue\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 17 Extended Message Queue</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\subsubsection rtos2_tutorial_mem_pool Memory Pool\n\nWe can design a message queue to support the transfer of large amounts of data. However, this method has an overhead in that\nwe are \"moving\" the data in the queue. In this section, we will look at designing a more efficient \"zero copy\" mailbox where\nthe data remains static. CMSIS-RTOS2 supports the dynamic allocation of memory in the form of a fixed block memory pool.\nFirst, we can declare the memory pool attributes:\n\\code\nosMemoryPoolAttr_t {\n  const char *name;   ///< name of the memory pool\n  uint32_t attr_bits; ///< attribute bits\n  void *cb_mem;       ///< memory for control block\n  uint32_t cb_size;   ///< size of provided memory for control block\n  void *mp_mem;       ///< memory for data storage\n  uint32_t mp_size;   ///< size of provided memory for data storage\n} osMemoryPoolAttr_t;\n\\endcode\nAnd a handle for the memory pool:\n\\code\nosMemoryPoolId_t mpool;\n\\endcode\nFor the memory pool itself, we need to declare a structure which contains the memory elements we require in each memory pool\nlot:\n\\code\ntypedef struct {\n  uint8_t LED0;\n  uint8_t LED1;\n  uint8_t LED2;\n  uint8_t LED3;\n} memory_block_t;\n\\endcode\nThen we can create a memory pool in our application code:\n\\code\nmpool = osMemoryPoolNew(16, sizeof(message_t),&memorypoolAttr_mpool);\n\\endcode\nNow we can allocate a memory pool slot within a thread:\n\\code\nmemory_block_t *led_data;\n*led_data = (memory_block_t *) osMemoryPoolAlloc(mPool,osWaitForever);\n\\endcode\nand then populate it with data:\n\\code\n\tled_data->LED0 = 0;\n\tled_data->LED1 = 1;\n\tled_data->LED2 = 2;\n\tled_data->LED3 = 3;\n\\endcode\nIt is then possible to place the pointer to the memory block in a message queue:\n\\code\nosMessagePut(Q_LED,(uint32_t)led_data,osWaitForever);\n\\endcode\nThe data can now be accessed by another task:\n\\code\nosEvent event;\nmemory_block_t *received;\nevent = osMessageGet(Q_LED, osWatiForever);\n*received = (memory_block *)event.value.p;\nled_on(received->LED0);\n\\endcode\nOnce the data in the memory block has been used, the block must be released back to the memory pool for reuse.\n\\code\nosPoolFree(led_pool,received);\n\\endcode\nTo create a zero copy mail box system, we can combine a memory pool to store the data with a message queue which is used to\ntransfer a pointer o the allocated memory pool slot. This way the message data stays static and we pass a pointer between\nthreads.\n\n\n\\subsubsection rtos2_tutorial_ex18 Exercise 18 - Zero Copy Mailbox\n\nOpen <a href=\"https://www2.keil.com/mdk5/packinstaller\" target=\"_blank\">Pack Installer</a>:\n- Use the <b>Search</b> box on the <b>Boards</b> tab to look for the <b>CMSIS_RTOS_Tutorial (V2.1)</b> \"board\".\n- On the <b>Examples</b> tab, copy <b>Ex 18 Zero Copy Mailbox</b> to your PC and start Keil MDK.\n- In the project folder, you will find a file called \"Instructions.pdf\" that explains the setup and the steps you need to\n  take to successfully finish the exercise.\n\n\n\\section rtos2_tutorial_config Configuration\n\nSo far we have looked at the CMSIS-RTOS2 API. This includes thread management functions, time management and inter-thread\ncommunication. Now that we have a clear idea of exactly what the RTOS kernel is capable of, we can take a more detailed look\nat the configuration file.\n\nRTX_Config.h is the central configuration file for all of the Cortex-M based microcontrollers.  Like the other configuration\nfiles, it is a template file which presents all the necessary configurations as a set of menu options (when viewed in\nConfiguration Wizard view).\n\n\n\\subsection rtos2_tutorial_config_sys System Configuration\n\nBefore we discuss the settings in the system configuration section, it is worth mentioning what is missing. In earlier\nversions of CMSIS-RTOS, it was necessary to define the CPU frequency as part of the RTOS configuration. In CMSIS-RTOS2, the\nCPU frequency is now taken from the \"SystemCoreClock\" variable which is set as part of the CMSIS-Core system startup code.\nIf you are working with a new microcontroller you will need to check that this value is being set correctly.\n\nAs we have seen earlier, we can set the amount of memory allocated to the \"Global Dynamic Memory Pool\". Next, we can define\nthe tick frequency in Hertz. This defines the SysTick interrupt rate and is set to 1 ms by default. Generally, I would leave\nthis frequency at its default setting. However, processor clock speeds are getting ever faster. If you are using a high\nperformance device you may consider using a faster tick rate.\n\n\"Round Robin Thread\" switching is also enabled by default in this section. Again, I would recommend leaving these settings\nin their default state unless you have a strong requirement to change them. The system configuration settings also allow us\nto control the range of messages sent to the event recorder as the RTOS runs.\n\nFinally, if we are setting thread flags from an interrupt they are held in a queue until they are processed. Depending on\nyour application you may need to increase the size of this queue.\n\n\n\\subsection rtos2_tutorial_config_thread Thread Configuration\n\nIn the Thread Configuration section, we define the basic resources which will be required by the CMSIS-RTOS2 threads. For\neach thread we allocate a \"default thread stack space\" (by default, this is 200 bytes). As you create threads, this memory\nwill be allocated from the Global Dynamic Mmemory Pool. However, if we enable Object specific memory allocation the RTOS\nwill define a memory region which is dedicated to thread usage only. If you switch to object specific memory allocation, it\nis necessary to provide details about the number and size of threads memory so the RTOS can calculate the maximum memory\nrequirement.\n\nFor object specific memory allocation, we must define the maximum number of user threads (don’t count the idle\nor timer threads) which will be running. We must also define the number of threads which have a default stack size and also\nthe total amount of memory required by threads with custom tack sizes. Once we have defined the memory used by user threads,\nwe can allocate memory to the idle thread. During development, CMSIS-RTOS can trap stack overflows. When this option is\nenabled, an overflow of a thread stack space will cause the RTOS kernel to call the \\ref osRtxErrorNotify() function which\nis located in the RTX_Config.c file. This function gets an error code and then sits in an infinite loop. The stack checking\noption is intended for use during debugging and should be disabled on the final application to minimize the kernel overhead.\nHowever, it is possible to modify the \\ref osRtxErrorNotify() function if enhanced error protection is required in the final\nrelease.\n\\code\n// OS Error Callback function\n__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {\n  (void)object_id;\n\n  switch (code) {\n    case osRtxErrorStackUnderflow:\n      // Stack overflow detected for thread (thread_id=object_id)\n      break;\n    case osRtxErrorISRQueueOverflow:\n      // ISR Queue overflow detected when inserting object (object_id)\n      break;\n    case osRtxErrorTimerQueueOverflow:\n      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)\n      break;\n    case osRtxErrorClibSpace:\n      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM\n      break;\n    case osRtxErrorClibMutex:\n      // Standard C/C++ library mutex initialization failed\n      break;\n    default:\n      // Reserved\n      break;\n  }\n  for (;;) {}\n//return 0U;\n}\n\\endcode\nIt is also possible to monitor the maximum stack memory usage during run time. If you check the \"Stack Usage Watermark\"\noption, a pattern (0xCC) is written into each stack space. During runtime, this watermark is used to calculate the maximum\nmemory usage. In Arm Keil MDK, this figure is reported in the threads section of the View - Watch Window - RTX RTOS window.\n \nThis section also allows us to select whether the threads are running in privileged or unprivileged mode. The last option\nallows us to define the processor operating mode for the user threads. If you want an easy life, leave this set to\n\"privileged mode\" and you will have full access to all the processor features. However, if you are writing a safety critical\nor secure application then \"unprivileged mode\" can be used to prevent thread access to critical processor registers limiting\nrun time errors or attempts at intrusion.\n\n\n\\subsection rtos2_tutorial_config_sys_timer System Timer Configuration\n\nThe default timer for use with CMSIS-RTOS is the Cortex-M SysTick timer which is present on nearly all Cortex-M processors.\nThe input to the SysTick timer will generally be the CPU clock. It is possible to use a different timer by overloading the\nkernel timer functions as outlined explained in the \\ref CMSIS_RTOS_TickAPI documentation.\n\n\n\\section rtos2_tutorial_conclusion Conclusion\n\nIn this tutorial, we have worked our way through the CMSIS-RTOS2 API and introduced some of the key concepts associated with\nusing an RTOS. The only real way to learn how to develop with an RTOS is to actually use one in a real project. \n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_Wait.txt",
    "content": "\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== Generic Wait Functions ====\n/** \n\\addtogroup CMSIS_RTOS_Wait Generic Wait Functions\n\\ingroup CMSIS_RTOS\n\\brief Wait for a certain period of time.\n\\details \nThe generic wait functions provide means for a time delay.\n\n\\note Generic wait functions cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osDelay (uint32_t ticks)\n\\details\nThe function \\b osDelay waits for a time period specified in kernel \\a ticks. For a value of \\token{1} the system waits\nuntil the next timer tick occurs. The actual time delay may be up to one timer tick less than specified, i.e. calling \n\\c osDelay(1) right before the next system tick occurs the thread is rescheduled immediately.\n\nThe delayed thread is put into the \\ref ThreadStates \"BLOCKED\" state and a context switch occurs immediately. The thread\nis automatically put back to the \\ref ThreadStates \"READY\" state after the given amount of ticks has elapsed. If the thread\nwill have the highest priority in \\ref ThreadStates \"READY\" state it will be scheduled immediately.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the time delay is executed.\n - \\em osErrorParameter: the time cannot be handled (zero value).\n - \\em osErrorISR: \\ref osDelay cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n - \\em osError: \\ref osDelay cannot be executed (kernel not running or no \\ref ThreadStates \"READY\" thread exists).\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Thread_1 (void *arg) {             // Thread function\n  osStatus_t status;                    // capture the return status\n  uint32_t   delayTime;                 // delay time in milliseconds\n \n  delayTime = 1000U;                    // delay 1 second\n  status = osDelay(delayTime);          // suspend thread execution\n}\n\\endcode\n*/ \n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn osStatus_t osDelayUntil (uint32_t ticks)\n\\details\nThe function \\b osDelayUntil waits until an absolute time (specified in kernel \\a ticks) is reached.\n\nThe corner case when the kernel tick counter overflows is handled by \\b osDelayUntil. Thus it is absolutely legal\nto provide a value which is lower than the current tick value, i.e. returned by \\ref osKernelGetTickCount. Typically\nas a user you do not have to take care about the overflow. The only limitation you have to have in mind is that the\nmaximum delay is limited to (2<sup>31</sup>)-1 ticks.\n\nThe delayed thread is put into the \\ref ThreadStates \"BLOCKED\" state and a context switch occurs immediately. The thread\nis automatically put back to the \\ref ThreadStates \"READY\" state when the given time is reached. If the thread will\nhave the highest priority in \\ref ThreadStates \"READY\" state it will be scheduled immediately.\n\nPossible \\ref osStatus_t return values:\n - \\em osOK: the time delay is executed.\n - \\em osErrorParameter: the time cannot be handled (out of bounds).\n - \\em osErrorISR: \\ref osDelayUntil cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n - \\em osError: \\ref osDelayUntil cannot be executed (kernel not running or no \\ref ThreadStates \"READY\" thread exists).\n\n\\note This function \\b cannot be called from \\ref CMSIS_RTOS_ISR_Calls \"Interrupt Service Routines\".\n\n<b>Code Example</b>\n\\code\n#include \"cmsis_os2.h\"\n \nvoid Thread_1 (void *arg) {             // Thread function\n  uint32_t tick;\n \n  tick = osKernelGetTickCount();        // retrieve the number of system ticks\n  for (;;) {\n    tick += 1000U;                      // delay 1000 ticks periodically\n    osDelayUntil(tick);\n    // ...\n  }\n}\n\\endcode\n*/\n/// @}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/cmsis_os2_tick.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n//  ==== OS Tick API ====\n/** \n\\addtogroup CMSIS_RTOS_TickAPI OS Tick API\n\\brief System tick timer interface for periodic RTOS Kernel Ticks defined in <b>%os_tick.h</b>\n\\details \n\nThe <b>OS Tick API</b> is an interface to a system timer that generates the Kernel Ticks.\n\nAll Cortex-M processors provide an unified System Tick Timer that is typically used to generate the RTOS Kernel Tick. \n\n\\if ARMCA\nThe Cortex-A processors do not implement an unified system timer and required a device specific implementation. \n\\endif\n\nCMSIS-RTOS2 provides in the directory \\ref directory \"CMSIS/RTOS2/Source\" several OS Tick implementations that can be used by any RTOS kernel.\n\nFilename                 | OS Tick Implementation for...\n:------------------------|:-----------------------------------------------------------------------\n\\b %os_systick.c         | Cortex-M SysTick timer\n\\if ARMCA\n\\b %os_tick_gtim.c       | Cortex-A Generic Timer (available in some devices)\n\\b %os_tick_ptim.c       | Cortex-A Private Timer (available in some devices)\n\\endif\n\n\\note The above OS Tick source files implement \\c weak functions which may be overwritten by user-specific implementations.\n\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t  OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)\n\\details \n\nSetup OS Tick timer to generate periodic RTOS Kernel Ticks.\n\nThe timer should be configured to generate periodic interrupts at frequency specified by \\em freq.\nThe parameter \\em handler defines the interrupt handler function that is called.\n\nThe timer should only be initialized and configured but must not be started to create interrupts.\nThe RTOS kernel calls the function \\ref OS_Tick_Enable to start the timer interrupts.\n\n<b>Cortex-M SysTick implementation:</b>\n\\code\n#ifndef SYSTICK_IRQ_PRIORITY\n#define SYSTICK_IRQ_PRIORITY    0xFFU\n#endif\n\nstatic uint8_t PendST;\n\nint32_t  OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {\n  (void)handler;\n  uint32_t load;\n \n  if (freq == 0U) {\n    return (-1);\n  }\n \n  load = (SystemCoreClock / freq) - 1U;\n  if (load > 0x00FFFFFFU) {\n    return (-1);\n  }\n \n  NVIC_SetPriority(SysTick_IRQn, SYSTICK_IRQ_PRIORITY);\n \n  SysTick->CTRL =  SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk;\n  SysTick->LOAD =  load;\n  SysTick->VAL  =  0U;\n \n  PendST = 0U;\n\n  return (0);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn void  OS_Tick_Enable (void)\n\\details \nEnable OS Tick timer interrupt.\n\nEnable and start the OS Tick timer to generate periodic RTOS Kernel Tick interrupts.\n\n<b>Cortex-M SysTick implementation:</b>\n\\code\nvoid  OS_Tick_Enable (void) {\n\n  if (PendST != 0U) {\n    PendST = 0U;\n    SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;\n  }\n\n  SysTick->CTRL |=  SysTick_CTRL_ENABLE_Msk;\n\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn void  OS_Tick_Disable (void)\n\\details \nDisable OS Tick timer interrupt.\n\nStop the OS Tick timer and disable generation of RTOS Kernel Tick interrupts.\n\n<b>Cortex-M SysTick implementation:</b>\n\\code\nvoid  OS_Tick_Disable (void) {\n\n  SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;\n\n  if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) {\n    SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;\n    PendST = 1U;\n  }\n\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn void  OS_Tick_AcknowledgeIRQ (void)\n\\details \nAcknowledge execution of OS Tick timer interrupt.\n\nAcknowledge the execution of the OS Tick timer interrupt function, for example clear the pending flag.\n\n<b>Cortex-M SysTick implementation:</b>\n\n\\code\nvoid  OS_Tick_AcknowledgeIRQ (void) {\n\n  (void)SysTick->CTRL;\n\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn int32_t OS_Tick_GetIRQn (void)\n\\details \nGet OS Tick timer IRQ number.\n\nReturn the numeric value that identifies the interrupt called by the OS Tick timer.\n\n<b>Cortex-M SysTick implementation:</b>\n\n\\code\nint32_t  OS_Tick_GetIRQn (void) {\n  return ((int32_t)SysTick_IRQn);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t OS_Tick_GetClock (void)\n\\details \nGet OS Tick timer clock frequency.\n\nReturn the input clock frequency of the OS Tick timer. This is the increment rate of the counter value returned by the function \\ref OS_Tick_GetCount.\nThis function is used to by the function \\ref osKernelGetSysTimerFreq.\n\n<b>Cortex-M SysTick implementation:</b>\n\n\\code\nuint32_t OS_Tick_GetClock (void) {\n  return (SystemCoreClock);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t OS_Tick_GetInterval (void)\n\\details \nGet OS Tick timer interval reload value. \n\nReturn the number of counter ticks between to periodic OS Tick timer interrupts.\n\n<b>Cortex-M SysTick implementation:</b>\n\n\\code\nuint32_t OS_Tick_GetInterval (void) {\n  return (SysTick->LOAD + 1U);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn uint32_t OS_Tick_GetCount (void)\n\\details \n\nGet OS Tick timer counter value.\n\nReturn the current value of the OS Tick counter: 0 ... (reload value -1). The reload value is returned by the function \\ref OS_Tick_GetInterval.\nThe OS Tick timer counter value is used to by the function \\ref osKernelGetSysTimerCount.\n\n<b>Cortex-M SysTick implementation:</b>\n\n\\code\nuint32_t OS_Tick_GetCount (void) {\n  uint32_t val;\n  uint32_t count;\n \n  val = SysTick->VAL;\n  if (val != 0U) {\n    count = (SysTick->LOAD - val) + 1U;\n  } else {\n    count = 0U;\n  }\n \n  return (count);\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\fn OS_Tick_GetOverflow (void)\n\\details \nGet OS Tick timer overflow status.\n\nReturn the state of OS Tick timer interrupt pending bit that indicates timer overflows to adjust SysTimer calculations.\n\n<b>Cortex-M SysTick implementation:</b>\n\n\\code\nuint32_t OS_Tick_GetOverflow (void) {\n  return ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) >> SCB_ICSR_PENDSTSET_Pos);\n}\n\\endcode\n*/\n\n/** @} */ /* group CMSIS_RTOS_TickAPI */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/history.txt",
    "content": "/**\n\\page rtos_revisionHistory Revision History\n\n\\section GenRTOS2Rev CMSIS-RTOS API Version 2\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>V2.2.0</td>\n      <td>\n        Added support for Process Isolation (Functional Safety):\n         - Kernel Management: \\ref osKernelProtect, \\ref osKernelDestroyClass\n         - Thread Management: \\ref osThreadGetClass, \\ref osThreadGetZone,<br>\n           \\ref osThreadSuspendClass, \\ref osThreadResumeClass, \\ref osThreadTerminateZone,<br>\n           \\ref osThreadFeedWatchdog, \\ref osThreadProtectPrivileged\n         - Thread attributes: \\ref osThreadZone, \\ref osThreadUnprivileged, \\ref osThreadPrivileged\n         - Object attributes: \\ref osSafetyClass\n         - Handler functions: \\ref osWatchdogAlarm_Handler\n         - Zone Management: \\ref osZoneSetup_Callback\n         - Exception Faults: \\ref osFaultResume\n\n        Additional functions allowed to be called from Interrupt Service Routines:\n         - \\ref osThreadGetName, \\ref osEventFlagsGetName, \\ref osTimerGetName, \\ref osMutexGetName, \\ref osSemaphoreGetName, \\ref osMemoryPoolGetName, \\ref osMessageQueueGetName\n      </td>\n    </tr>\n    <tr>\n      <td>V2.1.3</td>\n      <td>\n        Additional functions allowed to be called from Interrupt Service Routines:\n         - \\ref osThreadGetId\n     </td>\n    </tr>\n    <tr>\n      <td>V2.1.2</td>\n      <td>\n        Additional functions allowed to be called from Interrupt Service Routines:\n         - \\ref osKernelGetInfo, \\ref osKernelGetState\n     </td>\n    </tr>\n    <tr>\n      <td>V2.1.1</td>\n      <td>\n        Additional functions allowed to be called from Interrupt Service Routines:\n         - \\ref osKernelGetTickCount, \\ref osKernelGetTickFreq\n         \n        Changed Kernel Tick type to uint32_t:\n         - updated: \\ref osKernelGetTickCount, \\ref osDelayUntil\n     </td>\n    </tr>\n    <tr>\n      <td>V2.1.0</td>\n      <td>\n        Support for critical and uncritical sections (nesting safe):\n         - updated: \\ref osKernelLock, \\ref osKernelUnlock\n         - added: \\ref osKernelRestoreLock\n\n        Updated \\ref CMSIS_RTOS_ThreadFlagsMgmt \"Thread Flags\" and \\ref CMSIS_RTOS_EventFlags \"Event Flags\":\n         - changed flags parameter and return type from int32_t to uint32_t\n     </td>\n    </tr>\n    <tr>\n      <td>V2.0.0</td>\n      <td>\n        New API Version 2.0 available. \n         - See \\ref rtos_api2 for a detailed function reference.\n         - See \\ref os2Migration for details on the migration process from API Version 1.\n     </td>\n    </tr>\n    <tr>\n      <td>V1.02 - only documentation changes</td>\n      <td>\n      Added: Overview of the \\ref rtosValidation \"CMSIS-RTOS Validation\" Software Pack.\\n\n      Clarified: Behavior of \\ref CMSIS_RTOS_TimeOutValue.\n     </td>\n    </tr>\n    <tr>\n      <td>V1.02</td>\n      <td>Added: New control functions for short timeouts in microsecond resolution \\b osKernelSysTick,\n      \\b osKernelSysTickFrequency, \\b osKernelSysTickMicroSec.\\n\n      Removed: osSignalGet.\n     </td>\n    </tr>fv\n    <tr>\n      <td>V1.01</td>\n      <td>Added capabilities for C++, kernel initialization and object deletion.\\n\n      Prepared for C++ class interface. In this context to \\em const attribute has been moved from osXxxxDef_t typedefs to\n      the osXxxxDef macros.\\n\n      Added: \\ref osTimerDelete, \\ref osMutexDelete, \\ref osSemaphoreDelete.\\n\n      Added: \\ref osKernelInitialize that prepares the kernel for object creation.\\n\n      </td>\n    </tr>\n    <tr>\n      <td>\n      V1.00</td>\n      <td>First official Release.\\n\n      Added: \\ref osKernelStart; starting 'main' as a thread is now an optional feature.\\n\n      Semaphores have now the standard behavior.\\n\n      \\b osTimerCreate does no longer start the timer. Added: \\ref osTimerStart (replaces osTimerRestart).\\n\n      Changed: osThreadPass is renamed to \\ref osThreadYield.\n      </td>\n    </tr>\n    <tr>\n      <td>V0.02</td>\n      <td>Preview Release.</td>\n    </tr>\n</table>\n\n\n\\section RTX5RevisionHistory CMSIS-RTOS RTX Version 5\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>V5.7.0</td>\n      <td>\n       - Based on CMSIS-RTOS API V2.2.0.\n       - Added support for Process Isolation: MPU Protected Zones, Safety Classes, Thread Watchdogs.\n       - Reduced component variants: Library (Library_NS replacement), Source (Source_NS replacement).\n      </td>\n    </tr>\n    <tr>\n      <td>V5.5.5</td>\n      <td>\n       - Added de-allocation of Arm C library thread data (libspace) when thread is terminated.\n       - Updated SysTick implementation for OS Tick (initial count value).\n       - Added Thread Entry wrapper (compatible with GDB stack unwind).\n      </td>\n    </tr>\n    <tr>\n      <td>V5.5.4</td>\n      <td>\n       - Fixed potential register R1 corruption when calling OS functions from threads multiple times with same arguments (when using high level compiler optimizations).\n       - Fixed timer interval when periodic timer is restarted.\n       - Added Floating-point initialization for Arm C Library.\n       - Minor code optimizations in osMessageQueuePut/Get.\n      </td>\n    </tr>\n    <tr>\n      <td>V5.5.3</td>\n      <td>\n       - CVE-2021-27431 vulnerability mitigation.\n       - Added OS Initialization for IAR.\n       - Fixed osDelay/osDelayUntil error handling.\n       - Fixed Round-Robin (timeout value is not reset when switching to higher priority threads).\n       - Fixed osThreadJoin (when terminating thread which is waiting to be joined).\n       - Fixed Message Queue Data allocation size when using object specific memory allocation.\n       - Fixed Mutex priority inversion (when mixing mutexes with and without priority inherit).\n       - Enhanced stack overrun checking.\n       - Updated osKernelResume handling (processing past sleep ticks).\n       - Updated configuration (Event Recorder).\n       - Reorganized and optimized IRQ modules.\n      </td>\n    </tr>\n    <tr>\n      <td>V5.5.2</td>\n      <td>\n       - Added support for Cortex-M55.\n       - Fixed thread priority restore on mutex acquire timeout (when priority inherit is used).\n       - Enhanced support for Armv8-M (specifying thread TrustZone module identifier is optional).\n       - Updated configuration default values (Global Dynamic Memory and Thread Stack).\n      </td>\n    </tr>\n    <tr>\n      <td>V5.5.1</td>\n      <td>\n       - Fixed osMutexRelease issue (thread owning multiple mutexes).\n       - Improved osThreadJoin robustness (user programing errors).\n      </td>\n    </tr>\n    <tr>\n      <td>V5.5.0</td>\n      <td>\n       - Updated and enhanced generated events (reorganized components).\n       - Updated configuration (Event Recorder).\n       - Updated Component Viewer (improved performance).\n       - Minor code optimizations.\n      </td>\n    </tr>\n    <tr>\n      <td>V5.4.0</td>\n      <td>\n       - Based on CMSIS-RTOS API V2.1.3.\n       - Added support for Event Recorder initialization and filter setup.\n       - Added support to use RTOS as Event Recorder Time Stamp source.\n       - Fixed osDelayUntil longest delay (limited to 2^31-1).\n       - Fixed optimization issue when using GCC optimization level 3.\n       - Fixed osMemoryPoolAlloc to avoid potential race condition.\n       - Restructured exception handling for Cortex-A devices.\n       - Minor code optimizations (removed unnecessary checks).\n      </td>\n    </tr>\n    <tr>\n      <td>V5.3.0</td>\n      <td>\n       - Added Object Memory usage counters.\n       - Added support for additional external configuration file.\n       - Added user configurable names for system threads (Idle and Timer).\n       - Added support for OS sections when using ARMCC5.\n       - Added callback for MPU integration (experimental)\n       - Increased default thread stack sizes to 256 bytes.\n       - Fixed stack context display for running thread in SCVD.\n       - Enhanced MISRA Compliance.\n      </td>\n    </tr>\n    <tr>\n      <td>V5.2.3</td>\n      <td>\n       - Based on CMSIS-RTOS API V2.1.2.\n       - Added TrustZone Module Identifier configuration for Idle and Timer Thread.\n       - Moved SVC/PendSV handler priority setup from osKernelInitialize to osKernelStart (User Priority Grouping can be updated after osKernelInitialize but before osKernelStart).\n       - Corrected SysTick and PendSV handlers for ARMv8-M Baseline.\n       - Corrected memory allocation for stack and data when \"Object specific Memory allocation\" configuration is used.\n       - Added support for ARMv8-M IAR compiler.\n      </td>\n    </tr>\n    <tr>\n      <td>V5.2.2</td>\n      <td>\n       - Corrected IRQ and SVC exception handlers for Cortex-A.\n      </td>\n    </tr>\n    <tr>\n      <td>V5.2.1</td>\n      <td>\n       - Corrected SysTick and SVC Interrupt Priority for Cortex-M.\n      </td>\n    </tr>\n    <tr>\n      <td>V5.2.0</td>\n      <td>\n       - Based on CMSIS-RTOS API V2.1.1.\n       - Added support for Cortex-A.\n       - Using OS Tick API for RTX Kernel Timer Tick.\n       - Fixed potential corruption of terminated threads list.\n       - Corrected MessageQueue to use actual message length (before padding).\n       - Corrected parameters for ThreadEnumerate and MessageQueueInserted events.\n       - Timer Thread creation moved to osKernelStart.\n      </td>\n    </tr>\n    <tr>\n      <td>V5.1.0</td>\n      <td>\n       - Based on CMSIS-RTOS API V2.1.0.\n       - Added support for Event recording.\n       - Added support for IAR compiler.\n       - Updated configuration files: RTX_Config.h for the configuration settings and RTX_config.c for implementing the \\ref rtx5_specific.\n       - osRtx name-space for RTX specific symbols.\n      </td>\n    </tr>\n    <tr>\n      <td>V5.0.0</td>\n      <td>\n       Initial release compliant to CMSIS-RTOS2.\\n\n      </td>\n    </tr>\n</table>\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/mainpage.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\mainpage\n\nThe <b>CMSIS-RTOS v2 (CMSIS-RTOS2)</b> provides generic RTOS interfaces for Arm&reg; Cortex&reg; processor-based\ndevices. It provides a standardized API for software components that require RTOS functionality and gives therefore serious\nbenefits to the users and the software industry:\n - CMSIS-RTOS2 provides basic features that are required in many applications.\n - The unified feature set of the CMSIS-RTOS2 reduces learning efforts and simplifies sharing of software components.\n - Middleware components that use the CMSIS-RTOS2 are RTOS agnostic and are easier to adapt.\n - Standard project templates of the CMSIS-RTOS2 may be shipped with freely available CMSIS-RTOS2 implementations.\n\n\\note The CMSIS-RTOS API Version 2 defines a minimum feature set. Implementations with extended features may be provided by\n      the RTOS vendors.\n\nThe CMSIS-RTOS2 manages the resources of the microcontroller system and implements the concept of parallel threads that run\nconcurrently.\n\nApplications frequently require several concurrent activities. CMSIS-RTOS2 can manage multiple concurrent activities at the\ntime when they are needed. Each activity gets a separate thread which executes a specific task and this simplifies the\noverall program structure. The CMSIS-RTOS2 system is scalable and additional threads can be added easily at a later time.\nThreads have a priority allowing faster execution of time-critical parts of a user application.\n\nThe CMSIS-RTOS2 offers services needed in many real-time applications, for example, periodical activation of timer functions, \nmemory management, and message exchange between threads with time limits.\n\nThe CMSIS-RTOS2 addresses the following new requirements:\n - Dynamic object creation no longer requires static memory, static memory buffers are now optional.\n\\if ARMv8M\n - Support for Armv8-M architecture that provides a secure and non-secure state of code execution.\n\\endif \n - Provisions for message passing in multi-core systems.\n - Full support of C++ run-time environments.\n - C interface which is binary compatible across\n   <a href=\"http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html\">ABI compatible compilers</a>.\n\nAs a consequence of these requirements the CMSIS-RTOS2 has the following fundamental modifications:\n - The functions osXxxxNew replace osXxxxCreate functions; osXxxxNew and osXxxxDelete create and destroy objects.\n - The C function \\c main is no longer started as a thread (this was an optional feature in CMSIS-RTOS v1).\n - Functions that return osEvent have been replaced.\n\nCMSIS-RTOS2 provides an translation layer to <a class=\"el\" href=\"../../RTOS/html/index.html\">CMSIS-RTOS v1</a>. It\nis possible to intermix \\ref rtos_api2 and <a class=\"el\" href=\"../../RTOS/html/functionOverview.html\">CMSIS-RTOS C API v1</a>\nwithin the same application. Over time, you may migrate to the new API as explained in \\ref os2Migration.\n\nCMSIS-RTOS2 is not POSIX compliant, but has provisions to enable a C++11/C++14 interface.\n\nThe following sections provide further details about CMSIS-RTOS2 and the RTX reference implementation.\n - \\subpage rtos_revisionHistory documents changes made in each version for CMSIS-RTOS v2 and RTX v5.\n - \\subpage genRTOS2IF provides an overview about the APIs available with CMSIS-RTOS v2.\n - \\subpage functionOverview lists the CMSIS-RTOS2 API functions and the header file %cmsis_os2.h.\n\\ifnot FuSaRTS\n - \\subpage rtosValidation describes the validation suite that is publicly available.\n - \\subpage os2Migration shows how to use CMSIS-RTOS2 in existing projects and lists function differences to CMSIS-RTOS v1.\n\\endif\n - \\subpage rtx5_impl provides general information about the operation and usage of RTX v5.\n\\if FuSaRTS\n - \\subpage rtx_safety provides comprehensive instructions for highly reliable applications.\n\\endif\n\n\n<hr>\n\nCMSIS-RTOS2 in ARM::CMSIS Pack\n------------------------------\n\\anchor directory\n\nThe following files relevant to CMSIS-RTOS2 are present in the <b>ARM::CMSIS</b> Pack directories:\nDirectory                    | Content                                                                \n:----------------------------|:-----------------------------------------------------------------------\n\\b CMSIS/Documentation/RTOS2 | This documentation                                                     \n\\b CMSIS/RTOS2/Include       | \\ref cmsis_os2_h                                                 \n\\b CMSIS/RTOS2/RTX           | CMSIS-RTOS2 reference implementation based on RTX version 5\n\\b CMSIS/RTOS2/Source        | Generic <b>OS tick</b> implementations for various processors based on \\ref rtos_os_tick_api\n\\b CMSIS/RTOS2/Template      | Compatibility layer to <a class=\"el\" href=\"../../RTOS/html/index.html\">CMSIS-RTOS v1</a>\n*/\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/rtx_evr.txt",
    "content": "/** \n\\defgroup rtx_evr Event functions\n\\ingroup rtx5_specific \n\\brief RTX5 Event Recorder functions\n\\details\nRTX5 interfaces to the <a href=\"https://www.keil.com/pack/doc/compiler/EventRecorder/html/index.html\" target=\"_blank\"><b>Event Recorder</b></a> \nto provide event information which helps you to understand and analyze the operation.\n\nTo use the Event Recorder together with RTX5, it is required to create an image that generates event information. \nThe steps are described under \\ref cre_rtx_proj_er.\n\n@{\n*/\n\n/**\n\\defgroup rtx_evr_memory Memory Functions\n\\brief Events generated memory functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result)\n\\details\nThe event \\b MemoryInit is generated when initialization of a variable size memory block completes.\n\n\\b Value in the Event Recorder shows:\n  - \\b mem : memory address of memory pool.\n  - \\b size : size of a memory pool in bytes.\n  - \\b result : execution status: 1 - success, 0 - failure.\n*/\n\n/**\n\\fn void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block)\n\\details\nThe event \\b MemoryAlloc is generated when allocation of a variable size memory block completes.\n\n\\b Value in the Event Recorder shows:\n  - \\b mem : memory address of memory pool.\n  - \\b size : size of a memory block in bytes.\n  - \\b type : memory block type: 0 - generic, 1 - control block\n  - \\b block : memory address of allocated memory block or 0 in case of no memory is available.\n*/\n\n/**\n\\fn void EvrRtxMemoryFree (void *mem, void *block, uint32_t result)\n\\details\nThe event \\b MemoryFree is generated when deallocation of a variable size memory block completes.\n\n\\b Value in the Event Recorder shows:\n  - \\b mem : memory address of memory pool.\n  - \\b block : memory address of block to be returned to the memory pool.\n  - \\b result : execution status: 1 - success, 0 - failure.\n*/\n\n/**\n\\fn void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem)\n\\details\nThe event \\b MemoryBlockInit is generated when initialization of a fixed size memory block completes.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_info : memory address of memory pool info.\n  - \\b block_count : maximum number of memory blocks in memory pool.\n  - \\b block_size : size of a memory block in bytes.\n  - \\b block_mem : memory address of memory for block storage.\n*/\n\n/**\n\\fn void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block)\n\\details\nThe event \\b MemoryBlockAlloc is generated when allocation of a fixed size memory block completes.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_info : memory address of memory pool info.\n  - \\b block : memory address of the allocated memory block or 0 in case of no memory is available.\n*/\n\n/**\n\\fn void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status)\n\\details\nThe event \\b MemoryBlockFree is generated when deallocation of a fixed size memory block completes.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_info : memory address of memory pool info.\n  - \\b block : memory address of the allocated memory block to be returned to the memory pool.\n  - \\b status : execution status \\ref osStatus_t\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_kernel Kernel Functions\n\\brief Events generated by kernel functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxKernelError (int32_t status)\n\\details\nThe event \\b KernelError is generated when \\ref CMSIS_RTOS_KernelCtrl routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxKernelInitialize (void)\n\\details\nThe event \\b KernelInitialize is generated when the function \\ref osKernelInitialize is called.\n*/\n\n/**\n\\fn void EvrRtxKernelInitialized (void)\n\\details\nThe event \\b KernelInitialized is generated when the function \\ref osKernelInitialize successfully initializes the RTOS kernel.\n*/\n\n/**\n\\fn void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size)\n\\details\nThe event \\b KernelGetInfo is generated when the function \\ref osKernelGetInfo is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b version : memory address of buffer for retrieving version information.\n  - \\b id_buf : memory address of buffer for retrieving kernel identification string.\n  - \\b id_size : size of id_buf in bytes.\n*/\n\n/**\n\\fn void EvrRtxKernelInfoRetrieved (const osVersion_t *version, const char *id_buf, uint32_t id_size)\n\\details\nThe event \\b KernelInfoRetrieved is generated when the function \\ref osKernelGetInfo successfully retrieves kernel information.\n\n\\b Value in the Event Recorder shows:\n  - \\b ver_api : API version.\n  - \\b ver_kernel : kernel version.\n  - \\b id : kernel identification string (Detail).\n*/\n\n/**\n\\fn void EvrRtxKernelGetState (osKernelState_t state)\n\\details\nThe event \\b KernelGetState is generated when the function \\ref osKernelGetState is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b state : retrieved current \\ref osKernelState_t \"RTOS Kernel state\".\n*/\n\n/**\n\\fn void EvrRtxKernelStart (void)\n\\details\nThe event \\b KernelStart is generated when the function \\ref osKernelStart is called.\n*/\n\n/**\n\\fn void EvrRtxKernelStarted (void)\n\\details\nThe event \\b KernelStarted is generated when the function \\ref osKernelStart successfully starts the RTOS kernel execution.\n*/\n\n/**\n\\fn void EvrRtxKernelLock (void)\n\\details\nThe event \\b KernelLock is generated when the function \\ref osKernelLock is called.\n*/\n\n/**\n\\fn void EvrRtxKernelLocked (int32_t lock)\n\\details\nThe event \\b KernelLocked is generated when the functions \\ref osKernelLock successfully completes its execution.\n\n\\b Value in the Event Recorder shows:\n  - \\b lock : previous lock state (1 - locked, 0 - not locked).\n*/\n\n/**\n\\fn void EvrRtxKernelUnlock (void)\n\\details\nThe event \\b KernelUnlock is generated when the function \\ref osKernelUnlock is called.\n*/\n\n/**\n\\fn void EvrRtxKernelUnlocked (int32_t lock)\n\\details\nThe event \\b KernelUnlocked is generated when the function \\ref osKernelUnlock successfully completes its execution.\n\n\\b Value in the Event Recorder shows:\n  - \\b lock : previous lock state (1 - locked, 0 - not locked).\n*/\n\n/**\n\\fn void EvrRtxKernelRestoreLock (int32_t lock)\n\\details\nThe event \\b KernelRestoreLock is generated when the function \\ref osKernelRestoreLock is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b lock : lock state obtained by \\ref osKernelLock or \\ref osKernelUnlock.\n*/\n\n/**\n\\fn void EvrRtxKernelLockRestored (int32_t lock)\n\\details\nThe event \\b KernelLockRestored is generated when the function \\ref osKernelRestoreLock successfully completes its execution.\n\n\\b Value in the Event Recorder shows:\n  - \\b lock : new lock state (1 - locked, 0 - not locked).\n*/\n\n/**\n\\fn void EvrRtxKernelSuspend (void)\n\\details\nThe event \\b KernelSuspend is generated when the function \\ref osKernelSuspend is called.\n*/\n\n/**\n\\fn void EvrRtxKernelSuspended (uint32_t sleep_ticks)\n\\details\nThe event \\b KernelSuspended is generated when the function \\ref osKernelSuspend successfully suspends RTOS kernel execution.\n\n\\b Value in the Event Recorder shows:\n  - \\b sleep_ticks : time in ticks, for how long the system can sleep or power-down.\n*/\n\n/**\n\\fn void EvrRtxKernelResume (uint32_t sleep_ticks)\n\\details\nThe event \\b KernelResume is generated when the function \\ref osKernelResume is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b sleep_ticks : time in ticks, for how long the system was in sleep or power-down mode.\n*/\n\n/**\n\\fn void EvrRtxKernelResumed (void)\n\\details\nThe event \\b KernelResumed is generated when the function \\ref osKernelResume successfully resumes RTOS kernel execution.\n*/\n\n/**\n\\fn void EvrRtxKernelProtect (uint32_t safety_class)\n\\details\nThe event \\b KernelProtect is generated when the function \\ref osKernelProtect is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b safety_class : safety class value.\n*/\n\n/**\n\\fn void EvrRtxKernelProtected (void)\n\\details\nThe event \\b KernelProtected is generated when the function \\ref osKernelProtect successfully applies kernel safety class protection.\n*/\n\n/**\n\\fn void EvrRtxKernelGetTickCount (uint32_t count)\n\\details\nThe event \\b KernelGetTickCount is generated when the function \\ref osKernelGetTickCount is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b count : retrieved kernel current tick count.\n*/\n\n/**\n\\fn void EvrRtxKernelGetTickFreq (uint32_t freq)\n\\details\nThe event \\b KernelGetTickFreq is generated when the function \\ref osKernelGetTickFreq called.\n\n\\b Value in the Event Recorder shows:\n  - \\b freq : retrieved frequency of the kernel tick in Hz.\n*/\n\n/**\n\\fn void EvrRtxKernelGetSysTimerCount (uint32_t count)\n\\details\nThe event \\b KernelGetSysTimerCount is generated when the function \\ref osKernelGetSysTimerCount is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b count : retrieved kernel current system timer count as 32-bit value.\n*/\n\n/**\n\\fn void EvrRtxKernelGetSysTimerFreq (uint32_t freq)\n\\details\nThe event \\b KernelGetSysTimerFreq is generated when the function \\ref osKernelGetSysTimerFreq is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b freq : retrieved frequency of the system timer in Hz.\n*/\n\n/**\n\\fn void EvrRtxKernelErrorNotify (uint32_t code, void *object_id)\n\\details\nThe event \\b KernelErrorNotify is generated when the function \\ref osRtxErrorNotify is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b code : error code. \n  - \\b object_id : object that caused the error.\n*/\n\n/**\n\\fn void EvrRtxKernelDestroyClass (uint32_t safety_class, uint32_t mode)\n\\details\nThe event \\b KernelDestroyClass is generated when the function \\ref osKernelDestroyClass is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b safety_class : safety class value. \n  - \\b mode : operation mode.\n*/\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_thread Thread Functions\n\\brief Events generated by thread functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxThreadError (osThreadId_t thread_id, int32_t status)\n\\details\nThe event \\b ThreadError is generated when \\ref CMSIS_RTOS_ThreadMgmt routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr)\n\\details\nThe event \\b ThreadNew is generated when the function \\ref osThreadNew is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b func : memory address of thread function. \n  - \\b argument : memory address of thread function start argument.\n  - \\b attr : memory address of Thread attributes or 0 when they are not specified.\n*/\n\n/**\n\\fn void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name)\n\\details\nThe event \\b ThreadCreated is generated when the function \\ref osThreadNew successfully creates a thread object.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name)\n\\details\nThe event \\b ThreadGetName is generated when the function \\ref osThreadGetName is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b name : retrieved memory address of name string (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxThreadGetClass (osThreadId_t thread_id, uint32_t safety_class)\n\\details\nThe event \\b ThreadGetClass is generated when the function \\ref osThreadGetClass is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b safety_class : retrieved safety class value (osErrorId in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxThreadGetZone (osThreadId_t thread_id, uint32_t zone)\n\\details\nThe event \\b ThreadGetZone is generated when the function \\ref osThreadGetZone is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b zone : retrieved MPU Protected Zone value (osErrorId in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxThreadGetId (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadGetId is generated when the function \\ref osThreadGetId is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : retrieved thread (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state)\n\\details\nThe event \\b ThreadGetState is generated when the function \\ref osThreadGetState is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b state : retrieved current thread state.\n*/\n\n/**\n\\fn void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size)\n\\details\nThe event \\b ThreadGetStackSize is generated when the function \\ref osThreadGetStackSize is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b stack_size : retrieved remaining stack space in bytes (0 in case of a failure). \n*/\n\n/**\n\\fn void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space)\n\\details\nThe event \\b ThreadGetStackSpace is generated when the function \\ref osThreadGetStackSpace is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b stack_space : retrieved remaining stack space in bytes (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority)\n\\details\nThe event \\b ThreadSetPriority is generated when the function \\ref osThreadSetPriority is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b priority : new priority value for the thread function. \n*/\n\n/**\n\\fn void EvrRtxThreadPriorityUpdated (osThreadId_t thread_id, osPriority_t priority)\n\\details\nThe event \\b ThreadPriorityUpdated is generated when the function \\ref osThreadSetPriority successfully updated the specified thread priority.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b priority : new priority value for the thread function. \n*/\n\n/**\n\\fn void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority)\n\\details\nThe event \\b ThreadGetPriority is generated when the function \\ref osThreadGetPriority is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b priority : current priority value of the specified thread.\n*/\n\n/**\n\\fn void EvrRtxThreadYield (void)\n\\details\nThe event \\b ThreadYield is generated when the function \\ref osThreadYield is called.\n*/\n\n/**\n\\fn void EvrRtxThreadSuspend (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadSuspend is generated when the function \\ref osThreadSuspend is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadSuspended (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadSuspended is generated when the function \\ref osThreadSuspend successfully suspends the specified thread.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadResume (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadResume is generated when the function \\ref osThreadResume is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadResumed (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadResumed is generated when the function \\ref osThreadResume successfully resumes the specified thread.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadDetach (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadDetach is generated when the function \\ref osThreadDetach is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadDetached (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadDetached is generated when the function \\ref osThreadDetach successfully detaches the specified thread.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadJoin (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadJoin is generated when the function \\ref osThreadJoin is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadJoinPending (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadJoinPending is generated when the function \\ref osThreadJoin suspends current running thread until the specified thread terminates.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadJoined (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadJoined is generated when the function \\ref osThreadJoin successfully joins the specified thread.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout)\n\\details\nThe event \\b ThreadBlocked is generated when the current running thread execution is blocked.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val)\n\\details\nThe event \\b ThreadUnblocked is generated when the blocked thread execution is unblocked.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b ret_val : \n*/\n\n/**\n\\fn void EvrRtxThreadPreempted (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadPreempted is generated when current running thread execution is preempted.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadSwitched (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadSwitched is generated when current running thread execution switches.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadExit (void)\n\\details\nThe event \\b ThreadExit is generated when the function \\ref osThreadExit is called.\n*/\n\n/**\n\\fn void EvrRtxThreadTerminate (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadTerminate is generated when the function \\ref osThreadTerminate is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadDestroyed (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadDestroyed is generated when the function \\ref osThreadExit or \\ref osThreadTerminate successfully terminates the thread.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadFeedWatchdog (uint32_t ticks)\n\\details\n\nThe event \\b ThreadFeedWatchdog is generated when the function \\ref osThreadFeedWatchdog is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b ticks : watchdog timeout in number of kernel ticks.\n*/\n\n/**\n\\fn void EvrRtxThreadFeedWatchdogDone (void)\n\\details\nThe event \\b ThreadFeedWatchdogDone is generated when the function \\ref osThreadFeedWatchdog successfully feeds the watchdog timer.\n*/\n\n/**\n\\fn void EvrRtxThreadProtectPrivileged (void)\n\\details\nThe event \\b ThreadProtectPrivileged is generated when the function \\ref osThreadProtectPrivileged is called.\n*/\n\n/**\n\\fn void EvrRtxThreadPrivilegedProtected (void)\n\\details\nThe event \\b ThreadPrivilegedProtected is generated when the function \\ref osThreadProtectPrivileged successfully applies the new privileged thread creation protection.\n*/\n\n/**\n\\fn void EvrRtxThreadGetCount (uint32_t count)\n\\details\nThe event \\b ThreadGetCount is generated when the function \\ref osThreadGetCount is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b count : retrieved number of active threads (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count)\n\\details\nThe event \\b ThreadEnumerate is generated when the function \\ref osThreadEnumerate is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_array : memory address of array for retrieving thread IDs.\n  - \\b array_items : maximum number of items in thread_array.\n  - \\b count : number of enumerated threads (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxThreadSuspendClass (uint32_t safety_class, uint32_t mode)\n\\details\nThe event \\b ThreadSuspendClass is generated when the function \\ref osThreadSuspendClass is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b safety_class : safety class value.\n  - \\b mode : operation mode.\n*/\n\n/**\n\\fn void EvrRtxThreadResumeClass (uint32_t safety_class, uint32_t mode)\n\\details\nThe event \\b ThreadResumeClass is generated when the function \\ref osThreadResumeClass is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b safety_class : safety class value.\n  - \\b mode : operation mode.\n*/\n\n/**\n\\fn void EvrRtxThreadTerminateZone (uint32_t zone)\n\\details\nThe event \\b ThreadTerminateZone is generated when the function \\ref osThreadTerminateZone is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b zone : MPU Protected Zone value.\n*/\n\n/**\n\\fn void EvrRtxThreadWatchdogExpired (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadWatchdogExpired is generated when the thread watchdog timer expires.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_wait Generic Wait Functions\n\\brief Events generated by generic wait functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxDelayError (int32_t status)\n\\details\nThe event \\b DelayError is generated when \\ref CMSIS_RTOS_Wait routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxDelay (uint32_t ticks)\n\\details\nThe event \\b Delay is generated when the function \\ref osDelay is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b ticks : \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value. \n*/\n\n/**\n\\fn void EvrRtxDelayUntil (uint32_t ticks)\n\\details\nThe event \\b DelayUntil is generated when the function \\ref osDelayUntil is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b ticks : absolute delay time in ticks.\n*/\n\n/**\n\\fn void EvrRtxDelayStarted (uint32_t ticks)\n\\details\nThe event \\b DelayStarted is generated when \\ref osDelay delay starts.\n\n\\b Value in the Event Recorder shows:\n  - \\b ticks : \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value. \n*/\n\n/**\n\\fn void EvrRtxDelayUntilStarted (uint32_t ticks)\n\\details\nThe event \\b DelayUntilStarted is generated when \\ref osDelayUntil delay starts.\n\n\\b Value in the Event Recorder shows:\n  - \\b ticks : \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value. \n*/\n\n/**\n\\fn void EvrRtxDelayCompleted (osThreadId_t thread_id)\n\\details\nThe event \\b DelayCompleted is generated when \\ref osDelay or \\ref osDelayUntil delay expires.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_thread_flags Thread Flags Functions\n\\brief Events generated by thread flags functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsError (osThreadId_t thread_id, int32_t status)\n\\details\nThe event \\b ThreadFlagsError is generated when \\ref CMSIS_RTOS_ThreadFlagsMgmt routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags)\n\\details\nThe event \\b ThreadFlagsSet is generated when the function \\ref osThreadFlagsSet is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b flags : flags that shall be set.\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags)\n\\details\nThe event \\b ThreadFlagsSetDone is generated when thread flags are successfully set.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n  - \\b thread_flags : thread flags after setting.\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsClear (uint32_t flags)\n\\details\nThe event \\b ThreadFlagsClear is generated when the function \\ref osThreadFlagsClear is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b flags : flags that shall be cleared. \n*/\n\n/**\n\\fn void EvrRtxThreadFlagsClearDone (uint32_t thread_flags)\n\\details\nThe event \\b ThreadFlagsClearDone is generated when the function \\ref osThreadFlagsClear successfully clears thread flags.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_flags : thread flags before clearing.\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsGet (uint32_t thread_flags)\n\\details\nThe event \\b ThreadFlagsGet is generated when the function \\ref osThreadFlagsGet is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_flags : current thread flags.\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout)\n\\details\nThe event \\b ThreadFlagsWait is generated when the function \\ref osThreadFlagsWait is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b flags : flags to wait for.\n  - \\b options : flags options (refer to \\ref osThreadFlagsWait \"thread flags options\").\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout)\n\\details\nThe event \\b ThreadFlagsWaitPending is generated when the function \\ref osThreadFlagsWait starts waiting for thread flags to become signaled.\n\n\\b Value in the Event Recorder shows:\n  - \\b flags : flags to wait for.\n  - \\b options : flags options (refer to \\ref osThreadFlagsWait \"thread flags options\").\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsWaitTimeout (osThreadId_t thread_id)\n\\details\nThe event \\b ThreadFlagsWaitTimeout is generated when wait for thread flags to become signaled is aborted due to expired wait timeout.\n\n\\b Value in the Event Recorder shows:\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags, osThreadId_t thread_id)\n\\details\nThe event \\b ThreadFlagsWaitCompleted is generated when waiting for thread flags ends because requested flags were signaled.\n\n\\b Value in the Event Recorder shows:\n  - \\b flags : flags thread was waiting for.\n  - \\b option : flags options (refer to \\ref osThreadFlagsWait \"thread flags options\").\n  - \\b thread_flags : thread flags before clearing.\n  - \\b thread_id : thread ID.\n*/\n\n/**\n\\fn void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options)\n\\details\nThe event \\b ThreadFlagsWaitNotCompleted is generated when the function \\ref osThreadFlagsWait returns without timeout and specified thread flags were not signaled.\n\n\\b Value in the Event Recorder shows:\n  - \\b flags : flags thread was waiting for.\n  - \\b options : flags options (refer to \\ref osThreadFlagsWait \"thread flags options\").\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_event_flags Event Flags Functions\n\\brief Events generated by event flag functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status)\n\\details\nThe event \\b EventFlagsError is generated when \\ref CMSIS_RTOS_EventFlags routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr)\n\\details\nThe event \\b EventFlagsNew is generated when the function \\ref osEventFlagsNew is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b attr : memory address of Event Flags attributes or 0 when they are not specified.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name)\n\\details\nThe event \\b EventFlagsCreated is generated when the function \\ref osEventFlagsNew successfully creates a event flags object.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name)\n\\details\nThe event \\b EventFlagsGetName is generated when the function \\ref osEventFlagsGetName is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b name : retrieved memory address of name string (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags)\n\\details\nThe event \\b EventFlagsSet is generated when the function \\ref osEventFlagsSet is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b flags : flags that shall be set.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags)\n\\details\nThe event \\b EventFlagsSetDone is generated when event flags are successfully set.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b event_flags : event flags after setting.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags)\n\\details\nThe event \\b EventFlagsClear is generated when the function \\ref osEventFlagsClear is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b flags : flags that shall be cleared.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags)\n\\details\nThe event \\b EventFlagsClearDone is generated when the function \\ref osEventFlagsClear successfully clears the event flags.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b event_flags : event flags before clearing.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags)\n\\details\nThe event \\b EventFlagsGet is generated when the function \\ref osEventFlagsGet is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b event_flags : retrieved current event flags.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout)\n\\details\nThe event \\b EventFlagsWait is generated when the function \\ref osEventFlagsWait is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b flags : flags to wait for. \n  - \\b options : flags options (refer to \\ref osEventFlagsWait \"event flags options\").\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout)\n\\details\nThe event \\b EventFlagsWaitPending is generated when the function \\ref osEventFlagsWait starts waiting for event flags to become signaled.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b flags : flags to wait for.\n  - \\b options : flags options (refer to \\ref osEventFlagsWait \"event flags options\").\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id)\n\\details\nThe event \\b EventFlagsWaitTimeout is generated when wait for event flags to become signaled is aborted due to expired wait timeout.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags)\n\\details\nThe event \\b EventFlagsWaitCompleted is generated when waiting for event flags ends because requested flags were signaled.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b flags : flags to wait for.\n  - \\b options : flags option (refer to \\ref osEventFlagsWait \"event flags options\").\n  - \\b event_flags : event flags before clearing or 0 if specified flags have not been set.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options)\n\\details\nThe event \\b EventFlagsWaitNotCompleted is generated when the function \\ref osEventFlagsWait returns without timeout and specified event flags were not signaled.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n  - \\b flags : flags to wait for.\n  - \\b options : flags options (refer to \\ref osEventFlagsWait \"event flags options\").\n*/\n\n/**\n\\fn void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id)\n\\details\nThe event \\b EventFlagsDelete is generated when the function \\ref osEventFlagsDelete is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n*/\n\n/**\n\\fn void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id)\n\\details\nThe event \\b EventFlagsDestroyed is generated when the function \\ref osEventFlagsDelete successfully deletes the event flags object.\n\n\\b Value in the Event Recorder shows:\n  - \\b ef_id : event flags ID.\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_timer Timer Functions\n\\brief Events generated by timer functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxTimerError (osTimerId_t timer_id, int32_t status)\n\\details\nThe event \\b TimerError is generated when \\ref CMSIS_RTOS_TimerMgmt routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxTimerCallback (osTimerFunc_t func, void *argument)\n\\details\nThe event \\b TimerCallback is generated when the timer callback function is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b func : start address of a timer call back function. \n  - \\b argument : memory address of argument to the timer call back function.\n*/\n\n/**\n\\fn void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr)\n\\details\nThe event \\b TimerNew is generated when the function \\ref osTimerNew is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b func : start address of a timer call back function.\n  - \\b type : timer type: osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n  - \\b argument : memory address of argument to the timer call back function.\n  - \\b attr : memory address of Timer attributes or 0 when they are not specified.\n*/\n\n/**\n\\fn void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name)\n\\details\nThe event \\b TimerCreated is generated when the function \\ref osTimerNew successfully creates a timer object.\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n*/\n\n/**\n\\fn void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name)\n\\details\nThe event \\b TimerGetName is generated when the function \\ref osTimerGetName is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n  - \\b name : retrieved memory address of name string (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks)\n\\details\nThe event \\b TimerStart is generated when the function \\ref osTimerStart is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n  - \\b ticks : \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value of the timer.\n*/\n\n/**\n\\fn void EvrRtxTimerStarted (osTimerId_t timer_id)\n\\details\nThe event \\b TimerStarted is generated when the function \\ref osTimerStart successfully starts or restarts the timer operation.\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n*/\n\n/**\n\\fn void EvrRtxTimerStop (osTimerId_t timer_id)\n\\details\nThe event \\b TimerStop is generated when the function \\ref osTimerStop is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n*/\n\n/**\n\\fn void EvrRtxTimerStopped (osTimerId_t timer_id)\n\\details\nThe event \\b TimerStopped is generated when the function \\ref osTimerStop successfully stops the timer operation.\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n*/\n\n/**\n\\fn void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running)\n\\details\nThe event \\b TimerIsRunning is generated when the function \\ref osTimerIsRunning is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n  - \\b running : timer running state: 0 not running, 1 running.\n*/\n\n/**\n\\fn void EvrRtxTimerDelete (osTimerId_t timer_id)\n\\details\nThe event \\b TimerDelete is generated when the function \\ref osTimerDelete is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n*/\n\n/**\n\\fn void EvrRtxTimerDestroyed (osTimerId_t timer_id)\n\\details\nThe event \\b TimerDestroyed is generated when the function \\ref osTimerDelete successfully deletes the timer object.\n\n\\b Value in the Event Recorder shows:\n  - \\b timer_id : timer ID.\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_mutex Mutex Functions\n\\brief Events generated by mutex functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status)\n\\details\nThe event \\b MutexError is generated when \\ref CMSIS_RTOS_MutexMgmt routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxMutexNew (const osMutexAttr_t *attr)\n\\details\nThe event \\b MutexNew is generated when the function \\ref osMutexNew is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b attr : memory address of Mutex attributes or 0 when they are not specified.\n*/\n\n/**\n\\fn void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name)\n\\details\nThe event \\b MutexCreated is generated when the function \\ref osMutexNew successfully creates a mutex object.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n*/\n\n/**\n\\fn void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name)\n\\details\nThe event \\b MutexGetName is generated when the function \\ref osMutexGetName is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n  - \\b name : retrieved memory address of name string (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout)\n\\details\nThe event \\b MutexAcquire is generated when the function \\ref osMutexAcquire is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout)\n\\details\nThe event \\b MutexAcquirePending is generated when the function \\ref osMutexAcquire blocks current running thread and waits for mutex to become available.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id)\n\\details\nThe event \\b MutexAcquireTimeout is generated when wait for mutex to become available is aborted due to expired wait timeout.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n*/\n\n/**\n\\fn void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock)\n\\details\nThe event \\b MutexAcquired is generated when the function \\ref osMutexAcquire successfully acquires a mutex.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n  - \\b lock : current lock counter state.\n*/\n\n/**\n\\fn void EvrRtxMutexNotAcquired (osMutexId_t mutex_id)\n\\details\nThe event \\b MutexNotAcquired is generated when the function \\ref osMutexAcquire returns without timeout and mutex was not acquired.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n*/\n\n/**\n\\fn void EvrRtxMutexRelease (osMutexId_t mutex_id)\n\\details\nThe event \\b MutexRelease is generated when the function \\ref osMutexRelease is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n*/\n\n/**\n\\fn void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock)\n\\details\nThe event \\b MutexReleased is generated when the function \\ref osMutexRelease successfully releases a mutex.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n  - \\b lock : current lock counter state.\n*/\n\n/**\n\\fn void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id)\n\\details\nThe event \\b MutexGetOwner is generated when the function \\ref osMutexGetOwner is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n  - \\b thread_id : retrieved owner thread ID (0 in case of a failure or when mutex is not locked)\n*/\n\n/**\n\\fn void EvrRtxMutexDelete (osMutexId_t mutex_id)\n\\details\nThe event \\b MutexDelete is generated when the function \\ref osMutexDelete is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n*/\n\n/**\n\\fn void EvrRtxMutexDestroyed (osMutexId_t mutex_id)\n\\details\nThe event \\b MutexDestroyed is generated when the function \\ref osMutexDelete successfully deletes the mutex object.\n\n\\b Value in the Event Recorder shows:\n  - \\b mutex_id : mutex ID.\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_semaphore Semaphore Functions\n\\brief Events generated by semaphore functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status)\n\\details\nThe event \\b SemaphoreError is generated when \\ref CMSIS_RTOS_SemaphoreMgmt routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr)\n\\details\nThe event \\b SemaphoreNew is generated when the function \\ref osSemaphoreNew is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b max_count : maximum number of available tokens. \n  - \\b initial_count : initial number of available tokens.\n  - \\b attr : memory address of Semaphore attributes or 0 when they are not specified.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name)\n\\details\nThe event \\b SemaphoreCreated is generated when the function \\ref osSemaphoreNew successfully creates a semaphore object.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name)\n\\details\nThe event \\b SemaphoreGetName is generated when the function \\ref osSemaphoreGetName is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n  - \\b name : retrieved memory address of name string (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout)\n\\details\nThe event \\b SemaphoreAcquire is generated when the function \\ref osSemaphoreAcquire is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout)\n\\details\nThe event \\b SemaphoreAcquirePending is generated when the function \\ref osSemaphoreAcquire blocks current running thread and waits for semaphore token to become available.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id)\n\\details\nThe event \\b SemaphoreAcquireTimeout is generated when wait for semaphore to become available is aborted due to expired wait timeout.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens)\n\\details\nThe event \\b SemaphoreAcquired is generated when the function \\ref osSemaphoreAcquire successfully acquires the semaphore token.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n  - \\b tokens : available tokens.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id)\n\\details\nThe event \\b SemaphoreNotAcquired is generated when the function \\ref osMutexAcquire returns without timeout and semaphore token was not acquired.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id)\n\\details\nThe event \\b SemaphoreRelease is generated when the function \\ref osSemaphoreRelease is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens)\n\\details\nThe event \\b SemaphoreReleased is generated when the function \\ref osSemaphoreRelease successfully releases the semaphore token.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n  - \\b tokens : available tokens.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count)\n\\details\nThe event \\b SemaphoreGetCount is generated when the function \\ref osSemaphoreGetCount is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n  - \\b count : retrieved current number of available tokens. \n*/\n\n/**\n\\fn void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id)\n\\details\nThe event \\b SemaphoreDelete is generated when the function \\ref osSemaphoreDelete is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n*/\n\n/**\n\\fn void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id)\n\\details\nThe event \\b SemaphoreDestroyed is generated when the function \\ref osSemaphoreDelete successfully deletes the semaphore object.\n\n\\b Value in the Event Recorder shows:\n  - \\b semaphore_id : semaphore ID.\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_memory_pool Memory Pool Functions\n\\brief Events generated by memory pool functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status)\n\\details\nThe event \\b MemoryPoolError is generated when \\ref CMSIS_RTOS_PoolMgmt routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr)\n\\details\nThe event \\b MemoryPoolNew is generated when the function \\ref osMemoryPoolNew is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b block_count : maximum number of memory blocks in memory pool.\n  - \\b block_size : memory block size in bytes.\n  - \\b attr : memory address of Memory Pool attributes or 0 when they are not specified.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name)\n\\details\nThe event \\b MemoryPoolCreated is generated when the function \\ref osMemoryPoolNew successfully creates a memory pool object.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name)\n\\details\nThe event \\b MemoryPoolGetName is generated when the function \\ref osMemoryPoolGetName is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b name : retrieved memory address of name string (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout)\n\\details\nThe event \\b MemoryPoolAlloc is generated when the function \\ref osMemoryPoolAlloc is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout)\n\\details\nThe event \\b MemoryPoolAllocPending is generated when the function \\ref osMemoryPoolAlloc blocks current running thread and waits for memory block to become available.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id)\n\\details\nThe event \\b MemoryPoolAllocTimeout is generated when wait for memory pool to become available is aborted due to expired wait timeout.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block)\n\\details\nThe event \\b MemoryPoolAllocated is generated when the function \\ref osMemoryPoolAlloc successfully allocates the memory block.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b block : memory address of the allocated memory block.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id)\n\\details\nThe event \\b MemoryPoolAllocFailed is generated when the function \\ref osMemoryPoolAlloc fails to allocate the memory block due to out of available memory.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block)\n\\details\nThe event \\b MemoryPoolFree is generated when the function \\ref osMemoryPoolFree is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b block : memory address of the memory block to be returned to the memory pool.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block)\n\\details\nThe event \\b MemoryPoolDeallocated is generated when the function \\ref osMemoryPoolFree successfully deallocates the memory block.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b block : memory address of the memory block returned to the memory pool. \n*/\n\n/**\n\\fn void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block)\n\\details\nThe event \\b MemoryPoolFreeFailed is generated when the function \\ref osMemoryPoolFree fails to deallocate the memory block.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b block : memory address of the memory block to be returned to the memory pool.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity)\n\\details\nThe event \\b MemoryPoolGetCapacity is generated when the function \\ref osMemoryPoolGetCapacity is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b capacity : retrieved maximum number of memory blocks (0 in case of a failure). \n*/\n\n/**\n\\fn void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size)\n\\details\nThe event \\b MemoryPoolGetBlockSize is generated when the function \\ref osMemoryPoolGetBlockSize is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b block_size : retrieved memory block size in bytes (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count)\n\\details\nThe event \\b MemoryPoolGetCount is generated when the function \\ref osMemoryPoolGetCount is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b count : retrieved number of memory block used (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space)\n\\details\nThe event \\b MemoryPoolGetSpace is generated when the function \\ref osMemoryPoolGetSpace is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n  - \\b space : retrieved number of memory blocks available (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id)\n\\details\nThe event \\b MemoryPoolDelete is generated when the function \\ref osMemoryPoolDelete is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n*/\n\n/**\n\\fn void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id)\n\\details\nThe event \\b MemoryPoolDestroyed is generated when the function \\ref osMemoryPoolDelete successfully deletes the memory pool object.\n\n\\b Value in the Event Recorder shows:\n  - \\b mp_id : memory pool ID.\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx_evr_message_queue Message Queue Functions\n\\brief Events generated by message queue functions \n\\details\n@{\n*/\n\n/**\n\\fn void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status)\n\\details\nThe event \\b MessageQueueError is generated when \\ref CMSIS_RTOS_Message routines complete their execution due to an error.\n\nThe status parameter indicates the execution status and can be one of the \\ref osStatus_t \"osStatus_t codes\" or one\nof the extended execution status codes which are summarized in the table below.\n\n|      Extended Status Code       | Description |\n|:--------------------------------|:------------|\n| osRtxErrorKernelNotReady        | Kernel scheduler is not in Ready state. |\n| osRtxErrorKernelNotRunning      | Kernel scheduler is not executing - there is no running thread. |\n| osRtxErrorInvalidControlBlock   | Object control block with invalid alignment or size was specified. |\n| osRtxErrorInvalidDataMemory     | Object data memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidThreadStack    | Thread stack memory with invalid alignment or size was specified. |\n| osRtxErrorInvalidPriority       | Invalid thread priority was specified. |\n| osRtxErrorInvalidPrivilegedMode | Privileged thread cannot be created - kernel protect privileged is active. |\n| osRtxErrorThreadNotJoinable     | Specified thread is not joinable. |\n| osRtxErrorMutexNotOwned         | Specified mutex is not owned by the current running thread. |\n| osRtxErrorMutexNotLocked        | Specified mutex is not locked. |\n| osRtxErrorMutexLockLimit        | Maximum number of recursive mutex locks reached. |\n| osRtxErrorSemaphoreCountLimit   | Semaphore count limit reached. |\n| osRtxErrorTZ_InitContext_S      | Secure context memory system initialization failed. |\n| osRtxErrorTZ_AllocContext_S     | Secure context memory allocation failed. |\n| osRtxErrorTZ_FreeContext_S      | Secure context memory deallocation failed. |\n| osRtxErrorTZ_LoadContext_S      | Secure context load failed. |\n| osRtxErrorTZ_SaveContext_S      | Secure context save failed. |\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b status : execution status code.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr)\n\\details\nThe event \\b MessageQueueNew is generated when the function \\ref osMessageQueueNew is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b msg_count : maximum number of messages in queue.\n  - \\b msg_size : maximum message size in bytes.\n  - \\b attr : memory address of Message Queue attributes or 0 when they are not specified.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name)\n\\details\nThe event \\b MessageQueueCreated is generated when the function \\ref osMessageQueueNew successfully creates a message queue object.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name)\n\\details\nThe event \\b MessageQueueGetName is generated when the function \\ref osMessageQueueGetName is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b name : retrieved memory address of name string (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout)\n\\details\nThe event \\b MessageQueuePut is generated when the function \\ref osMessageQueuePut is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_ptr : memory address of message buffer.\n  - \\b msg_prio : message priority.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout)\n\\details\nThe event \\b MessageQueuePutPending is generated when the function \\ref osMessageQueuePut starts waiting to put message into the queue.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_ptr : memory address of message buffer.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id)\n\\details\nThe event \\b MessageQueuePutTimeout is generated when the function \\ref osMessageQueuePut fails to insert a message into the queue until timeout expires.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr)\n\\details\nThe event \\b MessageQueueInsertPending is generated when the function \\ref osMessageQueuePut is called from ISR and message is registered to be put into the queue. \n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_ptr : memory address of message buffer.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr)\n\\details\nThe event \\b MessageQueueInserted is generated when a message is successfully inserted into the queue.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_ptr : memory address of message buffer.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr)\n\\details\nThe event \\b MessageQueueNotInserted is generated when the function \\ref osMessageQueuePut fails to insert a message into the queue.\nUsually this happens when queue is out of memory.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_ptr : memory address of message buffer.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout)\n\\details\nThe event \\b MessageQueueGet is generated when the function \\ref osMessageQueueGet is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_ptr : memory address of buffer for message.\n  - \\b msg_prio : memory address of buffer for message priority.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout)\n\\details\nThe event \\b MessageQueueGetPending is generated when the function \\ref osMessageQueueGet starts waiting for message to be retrieved from the queue.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_ptr : memory address of buffer for message.\n  - \\b timeout : \\ref CMSIS_RTOS_TimeOutValue.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id)\n\\details\nThe event \\b MessageQueueGetTimeout is generated when the function \\ref osMessageQueueGet is called and there is no message available in queue until timeout expires.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr)\n\\details\nThe event \\b MessageQueueRetrieved is generated when message is retrieved from the message queue.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_ptr : memory address of buffer for message.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr)\n\\details\nThe event \\b MessageQueueNotRetrieved is generated when the function \\ref osMessageQueueGet is called without the wait timeout and there is no message available in queue.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_ptr : memory address of buffer for message.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity)\n\\details\nThe event \\b MessageQueueGetCapacity is generated when the function \\ref osMessageQueueGetCapacity is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b capacity : retrieved maximum number of messages (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size)\n\\details\nThe event \\b MessageQueueGetMsgSize is generated when the function \\ref osMessageQueueGetMsgSize is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b msg_size : retrieved maximum message size in bytes (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count)\n\\details\nThe event \\b MessageQueueGetCount is generated when the function \\ref osMessageQueueGetCount is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b count : retrieved number of queued messages (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space)\n\\details\nThe event \\b MessageQueueGetSpace is generated when the function \\ref osMessageQueueGetSpace is called and its execution result is known.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n  - \\b space : retrieved number of available slots for messages (0 in case of a failure).\n*/\n\n/**\n\\fn void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id)\n\\details\nThe event \\b MessageQueueReset is generated when the function \\ref osMessageQueueReset is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id)\n\\details\nThe event \\b MessageQueueResetDone is generated when the function \\ref osMessageQueueReset successfully completes message queue reset.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id)\n\\details\nThe event \\b MessageQueueDelete is generated when the function \\ref osMessageQueueDelete is called.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n*/\n\n/**\n\\fn void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id)\n\\details\nThe event \\b MessageQueueDestroyed is generated when the function \\ref osMessageQueueDelete successfully deletes the message queue object.\n\n\\b Value in the Event Recorder shows:\n  - \\b mq_id : message queue ID.\n*/\n\n/**\n@}\n*/\n\n/**\n@} \n*/\n// end group Event Recorder\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/rtx_os.txt",
    "content": "\n/** \n\\addtogroup rtx5_specific RTX v5 Specific API\n\\brief RTX v5 implementation specific definitions and functions defined in <b>%rtx_os.h</b>.\n\\details\n\nThe RTX5 kernel can be customized for different application requirements:\n\n- The function \\ref osRtxIdleThread implements the idle thread and allows set the system into sleep modes for \\ref lowPower or\n  \\ref TickLess for ultra-low power operation.\n  \n- The function \\ref osRtxErrorNotify may be extended to handle system runtime errors.\n\nRTX5 interfaces to the <a href=\"https://www.keil.com/pack/doc/compiler/EventRecorder/html/index.html\" target=\"_blank\"><b>Event Recorder</b></a> \nand provides event information that helps to analyze the operation. Refer to \\ref rtx_evr for more information.\n\n\n@{\n*/\n\n/**\n\\defgroup rtx5_specific_defines Macros\n\\brief RTX5 macros\n\\details\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxThreadCbSize\n\\brief Thread Control Block size\n\\details\nThis macro exposes the minimum amount of memory needed for an RTX5 Thread Control Block,\nsee osThreadAttr_t::cb_mem and \\ref osThreadAttr_t::cb_size.\n\nExample:\n\\code\n// Used-defined memory for thread control block\nstatic uint32_t thread_cb[osRtxThreadCbSize/4U];\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxTimerCbSize\n\\brief Timer Control Block size\n\\details\nThis macro exposes the minimum amount of memory needed for an RTX5 Timer Control Block,\nsee osTimerAttr_t::cb_mem and \\ref osTimerAttr_t::cb_size.\n\nExample:\n\\code\n// Used-defined memory for timer control block\nstatic uint32_t timer_cb[osRtxTimerCbSize/4U];\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxEventFlagsCbSize\n\\brief Event Flags Control Block size\n\\details\nThis macro exposes the minimum amount of memory needed for an RTX5 Event Flags Control Block,\nsee osEventFlagsAttr_t::cb_mem and \\ref osEventFlagsAttr_t::cb_size.\n\nExample:\n\\code\n// Used-defined memory for event flags control block\nstatic uint32_t evflags_cb[osRtxEventFlagsCbSize/4U];\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxMutexCbSize\n\\brief Mutex Control Block size\n\\details\nThis macro exposes the minimum amount of memory needed for an RTX5 Mutex Control Block,\nsee osMutexAttr_t::cb_mem and \\ref osMutexAttr_t::cb_size.\n\nExample:\n\\code\n// Used-defined memory for mutex control block\nstatic uint32_t mutex_cb[osRtxMutexCbSize/4U];\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxSemaphoreCbSize\n\\brief Semaphore Control Block size\n\\details\nThis macro exposes the minimum amount of memory needed for an RTX5 Semaphore Control Block,\nsee osSemaphoreAttr_t::cb_mem and osSemaphoreAttr_t::cb_size.\n\nExample:\n\\code\n// Used-defined memory for semaphore control block\nstatic uint32_t sema_cb[osRtxSemaphoreCbSize/4U];\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxMemoryPoolCbSize\n\\brief Memory Pool Control Block size\n\\details\nThis macro exposes the minimum amount of memory needed for an RTX5 Memory Pool Control Block,\nsee osMemoryPoolAttr_t::cb_mem and osMemoryPoolAttr_t::cb_size.\n\nExample:\n\\code\n// Used-defined memory for memory pool control block\nstatic uint32_t mempool_cb[osRtxMemoryPoolCbSize/4U];\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxMessageQueueCbSize\n\\brief Message Queue Control Block size\n\\details\nThis macro exposes the minimum amount of memory needed for an RTX5 Message Queue Control Block,\nsee osMessageQueueAttr_t::cb_mem and osMessageQueueAttr_t::cb_size.\n\nExample:\n\\code\n// Used-defined memory for message queue control block\nstatic uint32_t msgqueue_cb[osRtxMessageQueueCbSize/4U];\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxMemoryPoolMemSize\n\\brief Memory Pool Memory size\n\\details\nThis macro exposes the minimum amount of memory needed for an RTX5 Memory Pool Memory,\nsee osMemoryPoolAttr_t::mp_mem and osMemoryPoolAttr_t::mp_size.\n\nExample:\n\\code\n// Maximum number of objects\n#define OBJ_COUNT 8U\n \n// Object type\ntypedef struct {\n   uint32_t value1;\n   uint8_t  value2;\n} object_t;\n \n// Used-defined memory for memory pool memory\nstatic uint32_t mempool_mem[osRtxMemoryPoolMemSize(OBJ_COUNT, sizeof(object_t))/4U];\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxMessageQueueMemSize\n\\brief Message Queue Memory size\n\\details\nThis macro exposes the minimum amount of memory needed for an RTX5 Message Queue Memory,\nsee osMessageQueueAttr_t::mq_mem and osMessageQueueAttr_t::mq_size.\n\nExample:\n\\code\n// Maximum number of messages\n#define MSG_COUNT 16U\n \n// Message data type\ntypedef struct {\n   uint32_t value1;\n   uint8_t  value2;\n} msg_item_t;\n \n// Used-defined memory for message queue\nstatic uint32_t mq_mem[osRtxMessageQueueMemSize(MSG_COUNT, sizeof(msg_item_t))/4U];\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxErrorStackUnderflow\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxErrorStackOverflow\n\\brief Stack overflow, i.e. stack pointer below its lower memory limit for descending stacks.\n\\details\nThis error identifier is used with \\ref osRtxErrorNotify when RTX5 detects a thread stack overflow.\nThe object_id announced along this error can be used to identify the affected thread.\n\n\\ref threadConfig_watermark used together with larger stack sizes can help to figure out actual\nmemory requirements for threads.\n\n\\attention Whenever this error identifier is signaled memory corruption has already happened. \n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxErrorISRQueueOverflow\n\\brief ISR Queue overflow detected when inserting object.\n\\details\nThis error identifier is used with \\ref osRtxErrorNotify when RTX5 detects an overflow of the\ninterrupt post processing message queue. The object_id can be used to identify the affected\nobject.\n\n\\attention Whenever this error identifier is signaled the system state is already inconsistent.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxErrorTimerQueueOverflow\n\\brief User Timer Callback Queue overflow detected for timer.\n\\details\nThis error identifier is used with \\ref osRtxErrorNotify when RTX5 detects an overflow of the\ntimer callback queue. The object_id can be used to identify the affected timer.\n\n\\attention Whenever this error identifier is signaled a timer callback is already lost.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxErrorClibSpace\n\\brief Standard C/C++ library libspace not available.\n\\details\nThis error identifier is used with \\ref osRtxErrorNotify when RTX5 detects usage of libspace\nbut not enough memory was reserved using \\c OS_THREAD_LIBSPACE_NUM.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxErrorClibMutex\n\\brief Standard C/C++ library mutex initialization failed.\n\\details\nThis error identifier is used with \\ref osRtxErrorNotify when RTX5 fails to create mutexes needed\nto lock global C/C++ library resources.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\def osRtxErrorSVC\n\\brief Invalid SVC function called.\n\\details\nThis error identifier is used with \\ref osRtxErrorNotify when RTX5 detects SVC function pointer that is not properly aligned\nor is located outside of the RTX5 SVC function table.\n*/\n\n/**\n@}\n*/\n\n/**\n\\defgroup rtx5_specific_functions Functions\n\\brief RTX5 functions \n\\details\n@{\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn uint32_t osRtxErrorNotify (uint32_t code, void *object_id);\n\\param[in] code The code to identify the error condition.\n\\param[in] object_id A reference to any RTX object to identify the object that caused the issue, can be \\token{NULL}.\n\\details\nSome system error conditions can be detected during runtime. If the RTX kernel detects a runtime error, it calls the runtime\nerror function \\b osRtxErrorNotify for an object specified by parameter \\a object_id.\n\nThe parameter \\a code passes the actual error code to this function:\n| Error Code                        | Description                                                                       |\n|-----------------------------------|-----------------------------------------------------------------------------------|\n| \\ref osRtxErrorStackOverflow      | Stack overflow detected for thread (thread_id=object_id)                          |\n| \\ref osRtxErrorISRQueueOverflow   | ISR Queue overflow detected when inserting object (object_id)                     |\n| \\ref osRtxErrorTimerQueueOverflow | User Timer Callback Queue overflow detected for timer (timer_id=object_id)        |\n| \\ref osRtxErrorClibSpace          | Standard C/C++ library libspace not available: increase \\c OS_THREAD_LIBSPACE_NUM |\n| \\ref osRtxErrorClibMutex          | Standard C/C++ library mutex initialization failed                                |\n| \\ref osRtxErrorSVC                | Invalid SVC function called (function=object_id)                                  |\n\nThe function \\b osRtxErrorNotify must contain an infinite loop to prevent further program execution. You can use an emulator\nto step over the infinite loop and trace into the code introducing a runtime error. For the overflow errors this means you\nneed to increase the size of the object causing an overflow.\n\n<b>Code Example</b>\n\\code\n#include \"rtx_os.h\"\n \nuint32_t osRtxErrorNotify (uint32_t code, void *object_id) {\n  (void)object_id;\n \n  switch (code) {\n    case osRtxErrorStackOverflow:\n      // Stack overflow detected for thread (thread_id=object_id)\n      break;\n    case osRtxErrorISRQueueOverflow:\n      // ISR Queue overflow detected when inserting object (object_id)\n      break;\n    case osRtxErrorTimerQueueOverflow:\n      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)\n      break;\n    case osRtxErrorClibSpace:\n      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM\n      break;\n    case osRtxErrorClibMutex:\n      // Standard C/C++ library mutex initialization failed\n      break;\n    case osRtxErrorSVC:\n      // Invalid SVC function called (function=object_id)\n      break;\n    default:\n      break;\n  }\n  for (;;) {}\n//return 0U;\n}\n\\endcode\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/** \n\\fn void osRtxIdleThread (void *argument);\n\\param[in] argument Unused parameter, always set to \\token{NULL}.\n\\details\nThe function \\b osRtxIdleThread is executed by the RTX kernel when no other threads are ready to run.\n\nBy default, this thread is an empty end-less loop that does nothing. It only waits until another task\nbecomes ready to run. You may change the code of the \\b osRtxIdleThread function to put the CPU into\na power-saving or idle mode, see \\ref TickLess.\n\nThe default stack size for this thread is defined in the file RTX_Config.h. Refer to \\ref threadConfig.\n\n\\attention\nThe idle thread should never be blocked nor terminated!\n<b>Do not</b> call\n<ul>\n  <li>blocking functions,</li>\n  <li>\\ref osThreadTerminate, or </li>\n  <li>\\ref osThreadExit</li>\n</ul>\nand <b>do not</b> return from this function when providing a user defined implementation.\n\n<b>Code Example</b>\n\\code\n#include \"rtx_os.h\"\n \n__NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n\n  for (;;) {}\n}\n\\endcode\n*/ \n\n/**\n@}\n*/\n\n/// @}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/RTOS2/src/validation.txt",
    "content": "/**\n\\page rtosValidation RTOS Validation\n\n<a href=\"https://github.com/ARM-software/CMSIS-RTOS2_Validation\" target=\"_blank\"><b>CMSIS-RTOS2 Validation</b></a> framework is available to verify operation of CMSIS-RTOS2 implementations. The test cases validate the functional behavior, test invalid parameters and call management functions from Interrupt Service Routines (ISRs). The test projects are provided based on the <a href=\" https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools\" target=\"_blank\">CMSIS-Toolbox</a> and integrate well into CI workflows.\n\nFor details about the scope and usage, please, refer to the <a href=\"https://arm-software.github.io/CMSIS-RTOS2_Validation/main/index.html\" target=\"_blank\">CMSIS-RTOS2 Validation manual</a>.\n\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/SVD/src/ARM_ExampleT0.h",
    "content": "/* ================                     TIMER0                     ================ */\ntypedef struct {                                    /*!< TIMER0 Structure                                                      */\n  __IO uint32_t  CR;                                /*!< Control Register                                                      */\n  __IO uint16_t  SR;                                /*!< Status Register                                                       */\n  __I  uint16_t  RESERVED0[5];\n  __IO uint16_t  INT;                               /*!< Interrupt Register                                                    */\n  __I  uint16_t  RESERVED1[7];\n  __IO uint32_t  COUNT;                             /*!< The Counter Register reflects the actual Value of the Timer/Counter   */\n  __IO uint32_t  MATCH;                             /*!< The Match Register stores the compare Value for the MATCH condition   */\n  \n  union {\n    __O  uint32_t  PRESCALE_WR;                     /*!< The Prescale Register stores the Value for the prescaler. The\n                                                         cont event gets divided by this value                                 */\n    __I  uint32_t  PRESCALE_RD;                     /*!< The Prescale Register stores the Value for the prescaler. The\n                                                         cont event gets divided by this value                                 */\n  };\n  __I  uint32_t  RESERVED2[9];\n  __IO uint32_t  RELOAD[4];                         /*!< The Reload Register stores the Value the COUNT Register gets\n                                                         reloaded on a when a condition was met.                               */\n} TIMER0_Type;\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/SVD/src/ARM_ExampleT0Struct.h",
    "content": "/* ================                     TIMER0                     ================ */\ntypedef struct {                                    /*!< TIMER0 Structure                                                      */\n  \n  union {\n    __IO uint32_t  CR;                              /*!< Control Register                                                      */\n    \n    struct {\n      __IO uint32_t  EN         :  1;               /*!< Enable                                                                */\n      __O  uint32_t  RST        :  1;               /*!< Reset Timer                                                           */\n      __IO uint32_t  CNT        :  2;               /*!< Counting direction                                                    */\n      __IO uint32_t  MODE       :  3;               /*!< Operation Mode                                                        */\n      __IO uint32_t  PSC        :  1;               /*!< Use Prescaler                                                         */\n      __IO uint32_t  CNTSRC     :  4;               /*!< Timer / Counter Source Divider                                        */\n      __IO uint32_t  CAPSRC     :  4;               /*!< Timer / Counter Capture Source                                        */\n      __IO uint32_t  CAPEDGE    :  2;               /*!< Capture Edge, select which Edge should result in a counter increment\n                                                         or decrement                                                          */\n           uint32_t             :  2;\n      __IO uint32_t  TRGEXT     :  2;               /*!< Triggers an other Peripheral                                          */\n           uint32_t             :  2;\n      __IO uint32_t  RELOAD     :  2;               /*!< Select RELOAD Register n to reload Timer on condition                 */\n      __IO uint32_t  IDR        :  2;               /*!< Selects, if Reload Register number is incremented, decremented\n                                                         or not modified                                                       */\n           uint32_t             :  3;\n      __IO uint32_t  S          :  1;               /*!< Starts and Stops the Timer / Counter                                  */\n    } CR_b;                                         /*!< BitSize                                                               */\n  };\n  \n  union {\n    __IO uint16_t  SR;                              /*!< Status Register                                                       */\n    \n    struct {\n      __I  uint16_t  RUN        :  1;               /*!< Shows if Timer is running or not                                      */\n           uint16_t             :  7;\n      __IO uint16_t  MATCH      :  1;               /*!< Shows if the MATCH was hit                                            */\n      __IO uint16_t  UN         :  1;               /*!< Shows if an underflow occured. This flag is sticky                    */\n      __IO uint16_t  OV         :  1;               /*!< Shows if an overflow occured. This flag is sticky                     */\n           uint16_t             :  1;\n      __I  uint16_t  RST        :  1;               /*!< Shows if Timer is in RESET state                                      */\n           uint16_t             :  1;\n      __I  uint16_t  RELOAD     :  2;               /*!< Shows the currently active RELOAD Register                            */\n    } SR_b;                                         /*!< BitSize                                                               */\n  };\n  __I  uint16_t  RESERVED0[5];\n  \n  union {\n    __IO uint16_t  INT;                             /*!< Interrupt Register                                                    */\n    \n    struct {\n      __IO uint16_t  EN         :  1;               /*!< Interrupt Enable                                                      */\n           uint16_t             :  3;\n      __IO uint16_t  MODE       :  3;               /*!< Interrupt Mode, selects on which condition the Timer should\n                                                         generate an Interrupt                                                 */\n    } INT_b;                                        /*!< BitSize                                                               */\n  };\n  __I  uint16_t  RESERVED1[7];\n  __IO uint32_t  COUNT;                             /*!< The Counter Register reflects the actual Value of the Timer/Counter   */\n  __IO uint32_t  MATCH;                             /*!< The Match Register stores the compare Value for the MATCH condition   */\n  \n  union {\n    __O  uint32_t  PRESCALE_WR;                     /*!< The Prescale Register stores the Value for the prescaler. The\n                                                         cont event gets divided by this value                                 */\n    __I  uint32_t  PRESCALE_RD;                     /*!< The Prescale Register stores the Value for the prescaler. The\n                                                         cont event gets divided by this value                                 */\n  };\n  __I  uint32_t  RESERVED2[9];\n  __IO uint32_t  RELOAD[4];                         /*!< The Reload Register stores the Value the COUNT Register gets\n                                                         reloaded on a when a condition was met.                               */\n} TIMER0_Type;\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/SVD/src/svd.txt",
    "content": "/**\n\\mainpage System View Description\n\nIntroduction\n------------\nThe CMSIS System View Description format(CMSIS-SVD) formalizes the description of the system\ncontained in Arm Cortex-M processor-based microcontrollers, in particular, the memory mapped\nregisters of peripherals.\nThe detail contained in system view descriptions is comparable to the data in device \nreference manuals. The information ranges from high level functional \ndescriptions of a peripheral all the way down to the definition and purpose of an individual bit\nfield in a memory mapped register. \n\nCMSIS-SVD files are developed and maintained by silicon vendors.\nSilicon vendors distribute their descriptions as part of CMSIS Device Family Packs.\nTool vendors use CMSIS-SVD files for providing device-specific debug views of peripherals in \ntheir debugger. Last but not least, CMSIS-compliant device header files are generated from CMSIS-SVD\nfiles.\n\nCMSIS-SVD Benefits\n------------------\n- For Software Developers:\n  - Consistency between device header file and what is being displayed by the debugger.\n  - Detailed information about peripherals, registers, fields, and bit values as well as named \n    interrupts from within the debugger, without the need to reference device documentation.\n  - Convenient access to new and updated descriptions as part of the silicon vendor's CMSIS Device\n    Family Packs as the packs are made availabl by silicon vendors.\n  - Improved software development efficiency.\n\n- For Silicon Vendors:\n  - A tool vendor independent file format enables early device support by a wide range of toolchains\n    with limited effort.\n  - The XML-based format helps ease the integration into in-house design flows.\n  - Automated generation of CMSIS compliant device header files.\n  - Full control throughout the life cycle of the CMSIS-SVD files from creation to maintenance.\n\n- For Tool Vendors:\n  - Unified file format across silicon vendors helps the efficiency of supporting a wide range of \n    devices in a timely manner.\n  - Silicon vendors can provide early review access to the device support via restricted access to\n    CMSIS Device Family Packs.\n  - Updated descriptions are available over the web simplifying the maintenance of device support.\n\nLanguage Specification and Conventions\n---------------------------------------\n- \\ref svd_Format_pg\n\n\nCMSIS-SVD in ARM::CMSIS Pack\n----------------------------\n\nThe following files relevant to CMSIS-SVD are present in the <b>ARM::CMSIS</b> Pack directories:\n\n|File/Folder                   |Content                                                                \n|------------------------------|-----------------------------------------------------------------------\n|\\b CMSIS\\\\Documentation\\\\SVD  | This documentation                                                    \n|\\b CMSIS\\\\Utilities           | Exemplary SVD file (\\ref svd_Example_pg \"ARM_Example.svd\") and generated header file (ARM_Example.h).\n<p>&nbsp;</p>\n<hr>\n*/\n\n/* ************************************************************************************************ */\n/**\n\\page svd_revisionHistory Revision History\n\nFrom a schema perspective, CMSIS-SVD Version 1.1, 1.2 and 1.3 are fully backward compatible to\nversion 1.0. \n\n<table class=\"cmtable\" summary=\"Revision History table\">\n<tr>\n  <th>Version</th>\n  <th>Description</th>\n</tr>\n<tr>\n  <td>V1.3.9</td>\n  <td> \n       - Added CM85 as enumeration value for \\ref elem_cpu_sc \"cpuNameType\".</td>\n</tr>\n<tr>\n  <td>V1.3.8</td>\n  <td> \n       - Added SMC1 as enumeration value for \\ref elem_cpu_sc \"cpuNameType\".</td>\n</tr>\n<tr>\n  <td>V1.3.7</td>\n  <td> \n       - Added CM55 as enumeration value for \\ref elem_cpu_sc \"cpuNameType\".</td>\n</tr>\n<tr>\n  <td>V1.3.6</td>\n  <td> \n       - Added ARMV81MML as enumeration value for \\ref elem_cpu_sc \"cpuNameType\".</td>\n</tr>\n<tr>\n  <td>V1.3.5</td>\n  <td> \n       - Added CM35P as enumeration value for \\ref elem_cpu_sc \"cpuNameType\".</td>\n</tr>\n<tr>\n  <td>V1.3.4</td>\n  <td> \n       - Added information about the Linux version of \\ref svd_SVDConv_pg. </td>\n</tr>\n<tr>\n  <td>V1.3.3</td>\n  <td> \n       - Updated file header to Apache 2.0 License.\n       - Added \\em dimableIdentifierType, as a copy of previous \\em identifierType adding \"%s\".\n       - Updated \\em identifierType to only allow names without \"%s\" included.\n       - Removed \\em enumerationNameType.\n       - Added \\tagem{headerEnumName} to \\refelem{enumeratedValues} and to \\refelem{dimArrayIndex} for \\refelem{peripheral} \n         arrays, overwriting hierarchically generated names.\n       - Added \\tagem{dimName} to \\ref dimElementGroup_gr \"dimElementGroup\". Only valid in \\refelem{cluster} context, ignored otherwise.</td>\n</tr>\n<tr>\n  <td>V1.3.2</td>\n  <td> \n       - Extended command line of \\ref svd_SVDConv_pg for partition.h file generation.\n       - added \\refelem{dimArrayIndex} to \\refelem{peripheral}, \\refelem{cluster}, and \\refelem{register} \n         to describe enumeration of array indices.</td>\n</tr>\n<tr>\n  <td>V1.3.1</td>\n  <td> \n       - Added \\refelem{protection} element; extended with protection option \\token{p=privileged}.\n       - Added \\refelem{protection} element to \\refelem{addressBlock}.\n       - Fixed \\refelem{peripheral} name type to \\em identifierType to support \"%s\" for peripheral arrays.\n       - Added Cortex-A class enumeration to \\refelem{cpu}.\n       - added \\refelem{dimArrayIndex} to \\refelem{peripheral}, \\refelem{cluster}, and \\refelem{register} to describe enumeration of array indices.</td>\n</tr>\n<tr>\n  <td>V1.3</td>\n  <td> \n       - Extended \\refelem{peripheral} with \\tagem{dim} to support arrays. \n       - Added nesting of \\refelem{cluster} to support hierarchical register structures.\n       - Extended \\refelem{cpu} with description of the \\refelem{sauRegionsConfig} (Secure Attribution Unit).\n       - Extended \\ref registerPropertiesGroup_gr \"register properties\" with  \\refelem{protection} to reflect security aspects.</td>\n</tr>\n<tr>\n  <td>V1.2</td>\n  <td>Added optional elements for Cortex-M7 in \\ref elem_cpu \"CPU\": \n        - \\tagem{fpuDP}\n        - \\tagem{icachePresent}\n        - \\tagem{dcachePresent}\n        - \\tagem{itcmPresent}\n        - \\tagem{dtcmPresent}</td>\n</tr>\n<tr>\n  <td>V1.1</td>\n  <td>Many of the features added in version 1.1 are required for generating CMSIS-Core device header files from a CMSIS SVD description. \n      It is expected that all CMSIS-SVD descriptions will comply with version 1.1 by now.</td>\n</tr>\n<tr>\n  <td>V1.0</td>\n  <td>Initial version.</td>\n</tr>\n</table>\n\n<p>&nbsp;</p>\n<hr>\n*/\n\n\n/* ************************************************************************************************ */\n/**\n\\page svd_validate_file_pg SVD File Validation and Usage\n\nThe description quality is key to success of the CMSIS-SVD format. Aspects of\nquality are:\n  - Syntactical and structural compliance with the specified CMSIS-SVD format.\n  - Consistency and correctness.\n  - Completeness.\n  - Level of detail.\n\n<div class=\"title\">Validation</div>\nAutomated validations are done on two levels:\n\n-# <b>The CMSIS-SVD Schema File</b>: \nXML tools use the schema file for checking the syntactical and structural correctness of an XML file that\nclaims compliance with a certain format. The schema file <em>CMSIS-SVD.xsd</em> is located in \nthe folder <b>.\\\\CMSIS\\\\Utilities</b> of the \\b ARM::CMSIS Pack. \n\\n\\n\n-# <b>SVD Conversion Utility:</b> The conversion utility \\ref svd_SVDConv_pg checks the semantics and consistency of the data contained in a CMSIS-SVD file. \n\\b SVDConv is included in the CMSIS distribution. \n\n<div class=\"title\">Usage</div>\nCMSIS-SVD files can be used to generate:\n -# CMSIS-compliant device header files from a CMSIS-SVD description. Refer to the conversion tool \\ref svd_SVDConv_pg for details.\n  CMSIS device header files are developed and maintained by the silicon vendors. Therefore, the expectation is that this conversion is only of interest to\n  these parties.\n -# Debug dialogs that communicate with a debugger. See below.\n \n<b>System Views</b>\n\\n\\n A number of tool vendors support the CMSIS-SVD format with their products.\n  Refer to the tools documentation to find out how to use CMSIS-SVD descriptions with the debugger of your choice.\n  Please regularly check for updates to the CMSIS Device Family Packs from the silicon vendor to\n  to use the latest versions of the CMSIS-SVD files.\n  \\n \\n\n  <b>Generated Debug Dialog:</b>\n  \\image html \"SystemViewer_Generated.PNG\" \"uVision Debug Window generated from ARM_Example.svd\"\n\\n \n\n*/\n\n/* ************************************************************************************************ */\n/**\n\\page svd_Example_pg SVD File Example\n\\verbinclude \"ARM_Example.svd\"\n*/\n\n/* ************************************************************************************************ */\n/**\n\\page svd_SVDConv_pg SVDConv utility\n\n\\b SVDConv is a command-line utility to validate CMSIS-SVD files and to generate CMSIS-compliant device header files.\n\\b SVDConv is distributed with the \\b ARM::CMSIS Pack (in the CMSIS\\\\Utilities directory) together with the \\b CMSIS-SVD.xsd schema file. \n\\b SVDConv is available for Windows and Linux operating systems.\n\n\\b SVDConv performs the following operations:\n  - Checks the syntactical and structural compliance with the specified CMSIS-SVD format.\n  - Checks the consistency, correctness, and completeness of the CMSIS-SVD file against the CMSIS-SVD schema file.\n  - Generates CMSIS-compliant device header files, which can be used for software development.\n  \n\\note Consider using \\-\\-strict option to receive all pedantic warnings. Some rules are skipped by default due to\n  backward compatibility reasons. All newly developed/updated SVD files should rather respect all rules.\n\n\nOperation\n---------\n\\b SVDConv is invoked form the command line. The general command format is:\n\\code\nSVDConv.exe <SVD_file> <options>\n\\endcode\n\n<p>&nbsp;</p>\n\n<table class=\"cmtable\" summary=\"SVDConv Args\">\n  <tr>\n    <th>\\<options></th>\n    <th>Short Name</th>\n    <th>Description</th>\n  </tr>\n  <tr>\n    <td> <i>none</i> </td>\n    <td>Validation</td>\n    <td>Perform a validation check of the SVD file. Errors and warnings are printed on screen.\n  </td>\n  </tr>\n  <tr>\n    <td> -b </td>\n    <td>Log File</td>\n    <td>Specify the log file name for writing messages. Default: screen.\n    </td>\n  </tr>\n  <tr>\n    <td> -o </td>\n    <td>Output Path</td>\n    <td>Specify an output path for the generated device header file or log file. Default: current directory.\n    </td>\n  </tr>\n  <tr>\n    <td> \\-\\-generate=header </td>\n    <td>Generate Device Header File</td>\n    <td>Generates the device header file. The name of the generated file is derived from the value of the tag \\<devicename\\> in the CMSIS-SVD file. \n    Refer to \\refelem{device}.\n    </td>\n  </tr>\n  <tr>\n    <td> \\-\\-generate=partition </td>\n    <td>Generate Partition file for Cortex-M Security Extensions (Armv8-M)</td>\n    <td>Generates the device partition file. The name of the generated file is composed of <em>partition_</em> and the value of the device <em>\\<name\\></em>\n    (for example, <em>partition_CMSDK_ARMv8MBL.h</em>).\n    Refer to \\ref elem_device. The content of the file uses Configuration Wizard annotations and is derived \n    from the SAU-specific information of the \\ref elem_sauRegionsConfig and the interrupts specified in the \\ref elem_peripherals.</td>\n  </tr>\n  <tr>\n    <td> \\-\\-fields=enum </td>\n    <td>Bit-field Enums</td>\n    <td>Generates enum lists for each field value description contained in the CMSIS-SVD input file. \n        Must be used in combination with <i>\\-\\-generate=header</i>.</td>\n  </tr>\n  <tr>\n    <td> \\-\\-fields=macro </td>\n    <td>Bit-field Macros</td>\n    <td>Generates position and mask C-Macros for each field description contained in the CMSIS-SVD input file. \n    Must be used in combination with <i>\\-\\-generate=header</i>.</td>\n  </tr>\n  <tr>\n    <td> \\-\\-fields=struct </td>\n    <td>Bit-field Structs</td>\n    <td>Generates bit fields for each field description contained in the CMSIS-SVD input file. \n        Must be used in combination with <i>\\-\\-generate=header</i>.</td>\n  </tr>\n  <tr>\n    <td> \\-\\-fields=struct-ansic </td>\n    <td>ANSI Bit-field Structs</td>\n    <td>Generates MISRA-compliant structures for each bitfield. The generated code <b>is not CMSIS-compliant</b>!\n    Must be used in combination with <i>\\-\\-generate=header</i>.</td>\n  </tr>\n  <tr>\n    <td> \\-\\-strict</td>\n    <td>Strict error checking</td>\n    <td>\\b RECOMMENDED! Applies strict error checking and generates a lot more messages.</td>\n  </tr>\n</table>\n\nReturn Codes\n-------------\n\n\\b SVDConv returns the following codes:\n\\n\nCode | Description             | Action\n:---:|:------------------------|:--------------------\n  0  | OK                      | No action required. Validation and conversion performed without errors.\n  1  | WARNINGS                | Warnings should be checked an possibly removed. The header file is created and could be used.\n  2  | ERRORS                  | Errors in the SVD description file. Important elements are missing and must be corrected.\n  3  | Error in command line   | Check and correct the command line arguments.\n\n<b>Examples</b> \\n\n-# Retrieve help information on screen.\n   \\code \n     SVDConv \n   \\endcode\n   \\n\n-# Perform a consistency check by passing only the SVD file name. Errors and warnings are printed on screen. \n   \\code \n     SVDConv ARM_Example.svd \n   \\endcode\n   \\n\n   The result is printed on screen:\n   \\verbatim\n   MVCM3110.svd(1688) : info\n   <description> missing for value '2 : MODE2'\n   MVCM3110.svd(1692) : info\n   <description> missing for value '3 : MODE3'\n   MVCM3110.svd(1696) : info\n   <description> missing for value '4 : MODE4'\n   Area of improvements:\n   * Description contains 267 <fields> defined without associated <enumeratedValues>\n   Found 0 Errors and 1 Warnings\n   Return Code: 1 (WARNINGS)\n   \\endverbatim\n   \\n\n-# Generate the header file. Performs a consistency check. Errors and warnings are printed on screen. \n   \\code \n     SVDConv ARM_Example.svd --generate=header\n   \\endcode\n   \\n\n   Code snippet from the generated header file showing the structure for \\b TIMER0.\n   \\n\n   \\include \"ARM_ExampleT0.h\"\n   \\n\n-# Generate the header file containing bit fields. Performs a consistency check. Errors and warnings are printed on screen. \n   \\code \n     SVDConv ARM_Example.svd --generate=header --fields=struct\n   \\endcode\n   \\n\n   Code snippet from the generated header file showing the structure for \\b TIMER0.\n   \\n Compare to the code snippet above.\n   \\include \"ARM_ExampleT0Struct.h\"\n\n\\section svdconvMessages Error and Warning Messages\n\nThe following table shows the errors and warnings issued by svdconv.\n\nHelp messages\n-----------------\n\n<table class=\"cmtable\" summary=\"svdconv Invocation Msgs\">\n  <tr>\n    <th>Message Number</th>\n    <th>Type</th>\n    <th>Message Text</th>\n    <th>Details/Action</th>\n  </tr>\n  <tr><td>M020</td> <td>TEXT</td><td>\\em SVD_STRING_OPTIONS</td><td>Displays programm help.</td></tr>\n  <tr><td>M021</td> <td>TEXT</td><td>\\em 'DESCR' \\em 'VER' \\n \n                                     \\em 'COPYRIGHT'</td><td>Displays module name 'DESCR', version 'VER' and copyright information 'COPYRIGHT'.</td></tr>\n  <tr><td>M022</td> <td>TEXT</td><td>Found \\em 'ERR' Error(s) and \\em 'WARN' Warning(s).</td><td>Displays the number of errors/warnings.</td></tr>\n  <tr><td>M023</td> <td>TEXT</td><td>Phase \\em 'CHECK'</td><td>Information about the check phase.</td></tr>    \n  <tr><td>M024</td> <td>TEXT</td><td>Arguments: \\em 'OPTS'</td><td>Specify arguments.</td></tr>\n</table>\n\nInformative messages\n-----------------\n\n<table class=\"cmtable\" summary=\"Info Messages\">\n  <tr>\n    <th>Message Number</th>\n    <th>Type</th>\n    <th>Message Text</th>\n    <th>Details/Action</th>\n  </tr>\n  <tr><td>M040</td> <td>Info</td><td>\\em 'NAME': \\em 'TIME' ms. Passed</td><td></td></tr>\n  <tr><td>M041</td> <td>Info</td><td>Overall time: \\em 'TIME' ms.</td><td></td></tr>\n  <tr><td>M050</td> <td>Info</td><td>Current Working Directory: \\em 'PATH'</td><td></td></tr>\n  <tr><td>M051</td> <td>Info</td><td>Reading SVD File: \\em 'PATH'</td><td></td></tr>\n  <tr><td>M061</td> <td>Info</td><td>Checking SVD Description</td><td></td></tr>\n</table>\n\nInvocation errors\n-----------------\n\n<table class=\"cmtable\" summary=\"Internal and Invocation Errors\">\n  <tr>\n    <th>Message Number</th>\n    <th>Type</th>\n    <th>Message Text</th>\n    <th>Action</th>\n  </tr>\n  <tr><td>M101</td> <td>ERROR</td><td>Unknown error!</td><td>Please contact support.</td></tr>\n  <tr><td>M102</td> <td>ERROR</td><td>MFC initialization failed</td><td>Please contact support.</td></tr>\n  <tr><td>M103</td> <td>ERROR</td><td>Internal Error: \\em 'REF'</td><td>Please contact support.</td></tr>\n  <tr><td>M104</td> <td>CRITICAL</td><td>\\em 'MSG'</td><td>Please contact support.</td></tr>\n  <tr><td>M105</td> <td>ERROR</td><td>Cannot add Register to group sorter: \\em 'NAME'</td><td></td></tr>\n  <tr><td>M106</td> <td>ERROR</td><td>Command \\em 'NAME' failed: \\em 'NUM': \\em 'MSG'</td><td></td></tr>\n  <tr><td>M107</td> <td>ERROR</td><td>Lost xml file stream.</td><td>Check SVD file.</td></tr>\n  <tr><td>M108</td> <td>ERROR</td><td>SfrDis not supported.</td>Disassembly not supported.<td></td></tr>\n  <tr><td>M109</td> <td>ERROR</td><td>Cannot find \\em 'NAME'</td><td>Check specified file.</td></tr>\n  <tr><td>M111</td> <td>PROGRESS</td><td>\\em 'NAME' failed</td><td>Check specified file.</td></tr>\n  <tr><td>M120</td> <td>ERROR</td><td>Invalid arguments!</td><td>Provide a list of valid arguments.</td></tr>\n  <tr><td>M121</td> <td>ERROR</td><td>File not found \\em 'NAME'</td>Check specified file.<td></td></tr>\n  <tr><td>M122</td> <td>ERROR</td><td>Name of command file should follow \\em '@'</td><td>Check specified command.</td></tr>\n  <tr><td>M123</td> <td>ERROR</td><td>File not found: \\em 'PATH'!</td><td>Check speficied path.</td></tr>\n  <tr><td>M124</td> <td>ERROR</td><td>Cannot execute SfrCC2: \\em 'PATH'!\"</td><td>Check path to SfrCC2.</td></tr>\n  <tr><td>M125</td> <td>WARNING</td><td>SfrCC2 report: \\n\n                                        \\em 'MSG' \\n\n\t\t\t\t\t\t\t\t\t\tSfrCC2 report end.</td><td></td></tr>\n  <tr><td>M126</td> <td>WARNING</td><td>SfrDis: \\em 'MSG'</td><td></td></tr>\n  <tr><td>M127</td> <td>ERROR</td><td>SfrCC2 reports errors!</td><td>Check SVD file.</td></tr>\n  <tr><td>M128</td> <td>WARNING</td><td>SfrCC2 reports warnings!</td><td>Check SVD file.</td></tr>\n  <tr><td>M129</td> <td>ERROR</td><td>Option unknown: \\em 'OPT'</td><td>Check given option \\em 'OPT'.</td></tr>\n  <tr><td>M130</td> <td>ERROR</td><td>Cannot create file \\em 'NAME'</td><td>Check user rights.</td></tr>\n  <tr><td>M132</td> <td>ERROR</td><td>SfrCC2 report: \\n\n                                      \\em 'MSG' \\n\n\t\t\t\t\t\t\t\t\t  SfrCC2 report end.\"</td><td></td></tr>\n</table>\n\nValidation errors\n-----------------\n\n<table class=\"cmtable\" summary=\"Validation Errors\">\n  <tr>\n    <th>Message Number</th>\n    <th>Type</th>\n    <th>Message Text</th>\n    <th>Action</th>\n  </tr>\n  <tr><td>M201</td> <td>ERROR</td><td>Tag \\<\\em 'TAG'> unknown or not allowed on this level.\"</td><td>Check tag</td></tr>\n  <tr><td>M202</td> <td>ERROR</td><td>Parse error: \\<\\em 'TAG'> = \\em 'VALUE'</td><td>Check tag/value.</td></tr>\n  <tr><td>M203</td> <td>ERROR</td><td>Value already set: \\<\\em 'TAG'> = \\em 'VALUE'</td><td>Check tag/value.</td></tr>\n  <tr><td>M204</td> <td>ERROR</td><td>Parse Error: \\em 'VALUE'</td><td>Check value.</td></tr>\n  <tr><td>M205</td> <td>WARNING</td><td>Tag \\<\\em 'TAG'> empty</td><td>Assign value to tag.</td></tr>\n  <tr><td>M206</td> <td>ERROR</td><td>DerivedFrom not found: \\em 'NAME'</td><td>Check derivate.</td></tr>\n  <tr><td>M207</td> <td>ERROR</td><td>Expression marker found but no \\<dim> specified: \\em 'NAME'</td><td>Specify dimension.</td></tr>\n  <tr><td>M208</td> <td>ERROR</td><td>Ignoring \\<dimIndex> because specified \\<name> requires Array generation.</td><td>Generate an array.</td></tr>\n  <tr><td>M209</td> <td>WARNING</td><td>CPU section not set. This is required for CMSIS Headerfile generation and debug support.</td><td>Add CPU section.</td></tr>\n  <tr><td>M210</td> <td>WARNING</td><td>Use new Format CMSIS-SVD >= V1.1 and add \\<CPU\\> Section.</td><td>Update schema and add CPU section.</td></tr>\n  <tr><td>M211</td> <td>ERROR</td><td>Ignoring \\em 'LEVEL' \\em 'NAME' (see previous message)</td><td></td></tr>\n  <tr><td>M212</td> <td>ERROR</td><td>Address Block \\<usage> parse error: \\em 'NAME'</td><td>Correct address block.</td></tr>\n  <tr><td>M213</td> <td>ERROR</td><td>Expression for \\em 'NAME' incomplete, <\\em 'TAG'> missing.</td><td>Add tag.</td></tr>\n  <tr><td>M214</td> <td>ERROR</td><td>Peripheral \\em 'NAME' \\<dim> single-instantiation is not supported (use Array instead).</td><td>Correct Reg%s to Reg[%s].</td></tr>\n  <tr><td>M215</td> <td>WARNING</td><td>Size of \\<dim> is only one element for \\em 'NAME', is this intended?</td><td>Check single element.</td></tr>\n  <tr><td>M216</td> <td>WARNING</td><td>Unsupported character found in \\em 'NAME' : \\em 'HEX'.</td><td>Correct name.</td></tr>\n  <tr><td>M217</td> <td>WARNING</td><td>Forbidden Trigraph '??%CHAR%' found in \\em 'NAME'.</td><td></td></tr>\n  <tr><td>M218</td> <td>WARNING</td><td>Unsupported ESC sequence found in \\em 'NAME' : \\em 'CHAR'.</td><td>Correct escape sequence.</td></tr>\n  <tr><td>M219</td> <td>ERROR</td><td>C Code generation error: \\em 'MSG'</td><td></td></tr>\n  <tr><td>M220</td> <td>WARNING</td><td>C Code generation warning: \\em 'MSG'</td><td></td></tr>\n  <tr><td>M221</td> <td>WARNING</td><td>Input filename must end with .svd: \\em 'NAME'</td><td>Correct input filename extension.</td></tr>\n  <tr><td>M222</td> <td>WARNING</td><td>Input filename has no extension: \\em 'NAME'</td><td>Correct input filename extension.</td></tr>\n  <tr><td>M223</td> <td>ERROR</td><td>Input File Name \\em 'INFILE' does not match the tag \\<name> in the \\<device> section: \\em 'NAME%'</td><td>Correct the MCU name.</td></tr>\n  <tr><td>M224</td> <td>WARNING</td><td>Deprecated: \\em 'NAME' Use \\em 'NAME2' instead</td><td>Update SVD file.</td></tr>\n  <tr><td>M225</td> <td>ERROR</td><td>Upper/lower case error: \\em 'NAME', should be \\em 'NAME2'\"</td><td>Update SVD file.</td></tr>\n  <tr><td>M226</td> <td>ERROR</td><td>SFD Code generation error: \\em 'MSG'</td><td></td></tr>\n  <tr><td>M227</td> <td>WARNING</td><td>SFD Code generation warning: \\em 'MSG'</td><td></td></tr>\n  <tr><td>M228</td> <td>ERROR</td><td>Enumerated Value Container: Only one Item allowed on this Level!</td><td>Remove additional items.</td></tr>\n  <tr><td>M229</td> <td>ERROR</td><td>Register \\em 'NAME' is not an array, \\<dimArrayIndex> is not applicable</td><td>Correct SVD.</td></tr>\n  <tr><td>M230</td> <td>ERROR</td><td>Value \\em 'NAME':\\em 'NUM' out of Range for \\em 'LEVEL' \\em 'NAME2'[\\em 'NUM2'].</td><td>Correct SVD.</td></tr>\n  <tr><td>M231</td> <td>ERROR</td><td>Value \\<isDefault> not allowed for \\em 'LEVEL'.</td><td>Correct SVD.</td></tr>\n  <tr><td>M232</td> <td>ERROR</td><td>Tag \\<\\em 'TAG'> name \\em 'NAME' must not have specifier \\em 'CHAR'. Ignoring entry.\"</td><td>Correct SVD.</td></tr>\n  <tr><td>M233</td> <td>ERROR</td><td>Parse error: \\<\\em 'TAG'> = \\em 'VALUE'</td><td>Correct SVD.</td></tr>\n  <tr><td>M234</td> <td>ERROR</td><td>No valid items found for \\em 'LEVEL' \\em 'NAME'</td><td>Correct SVD.</td></tr>\n  <tr><td>M235</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME' cannot be an array.</td><td>Correct SVD.</td></tr>\n  <tr><td>M236</td> <td>ERROR</td><td>Expression for \\<\\em 'TAG'> \\em 'NAME' not allowed.</td><td>Correct SVD.</td></tr>\n  <tr><td>M237</td> <td>ERROR</td><td>Nameless \\em 'LEVEL' must have \\<\\em 'TAG'>.</td><td>Correct SVD.</td></tr>\n  <tr><td>M238</td> <td>ERROR</td><td>\\em 'LEVEL' must not have \\<\\em 'TAG'>.\"</td><td>Correct SVD.</td></tr>\n  <tr><td>M239</td> <td>ERROR</td><td>Dimed \\em 'LEVEL' \\em 'NAME' must have an expression.</td><td>Correct SVD.</td></tr>\n  <tr><td>M240</td> <td>ERROR</td><td>Tag \\<\\em 'TAG'> unknown or not allowed on \\em 'LEVEL2':\\em 'LEVEL'.</td><td>Correct SVD.</td></tr>\n  <tr><td>M241</td> <td>ERROR</td><td>Parse Error: \\em 'VALUE' invalid for Array generation</td><td>Correct SVD.</td></tr>\n  <tr><td>M242</td> <td>WARNING</td><td>\\em 'LEVEL' \\em 'NAME' \\<dimArrayIndex> found, but no \\<dim></td><td>Correct SVD.</td></tr>\n  <tr><td>M243</td> <td>WARNING</td><td>\\em 'LEVEL' \\em 'NAME' \\<dimArrayIndex> found, but \\<dim> does not describe an array</td><td>Correct SVD.</td></tr>\n</table>\n\nData Check Errors\n-----------------\n\n<table class=\"cmtable\" summary=\"Data Check Errors\">\n  <tr>\n    <th>Message Number</th>\n    <th>Type</th>\n    <th>Message Text</th>\n    <th>Action</th>\n  </tr>\n  <tr><td>M301</td> <td>ERROR</td><td>Interrupt number \\em 'NUM' : \\em 'NAME' already defined: \\em 'NAME2' \\em 'LINE'</td><td></td></tr>\n  <tr><td>M302</td> <td>ERROR</td><td>Size of Register \\em 'NAME':\\em 'NUM' must be 8, 16 or 32 Bits</td><td></td></tr>         \n  <tr><td>M303</td> <td>WARNING</td><td>Register name \\em 'NAME' is prefixed with Peripheral name \\em 'NAME2'</td><td>RegName = USART_CR ==> USART->USART_CR</td></tr>\n  <tr><td>M304</td> <td>WARNING</td><td>Interrupt number overwrite: \\em 'NUM' : \\em 'NAME' \\em 'LINE'</td><td></td></tr>              \n  <tr><td>M305</td> <td>ERROR</td><td>Name not C compliant: \\em 'NAME' : \\em 'HEX', replaced by '_'</td><td></td></tr>            \n  <tr><td>M306</td> <td>ERROR</td><td>Schema Version not set for \\<device>.</td><td></td></tr>                               \n  <tr><td>M307</td> <td>ERROR</td><td>Name is equal to Value: \\em 'NAME'</td><td></td></tr>                                   \n  <tr><td>M308</td> <td>ERROR</td><td>Number of \\<dimIndex> Elements \\em 'NUM' is different to number of \\<dim> instances \\em 'NUM2'</td><td></td></tr>\n  <tr><td>M309</td> <td>ERROR</td><td>Field \\em 'NAME': Offset error: \\em 'NUM'</td><td></td></tr>                   \n  <tr><td>M310</td> <td>ERROR</td><td>Field \\em 'NAME': BitWidth error: \\em 'NUM'</td><td></td></tr>                 \n  <tr><td>M311</td> <td>ERROR</td><td>Field \\em 'NAME': Calculation: MSB or LSB == -1</td><td></td></tr>         \n  <tr><td>M312</td> <td>ERROR</td><td>Address Block missing for Peripheral \\em 'NAME'</td><td></td></tr>         \n  <tr><td>M313</td> <td>ERROR</td><td>Field \\em 'NAME': LSB > MSB: BitWith calculates to \\em 'NUM'</td><td></td></tr>\n  <tr><td>M314</td> <td>ERROR</td><td>Address Block: \\<offset> or \\<size> not set.</td><td></td></tr>            \n  <tr><td>M315</td> <td>ERROR</td><td>Address Block: \\<size> is zero.</td><td></td></tr>                        \n  <tr><td>M316</td> <td>ERROR</td><td>\\em 'LEVEL' \\<name> not set.</td><td></td></tr>             \n  <tr><td>M317</td> <td>WARNING</td><td>\\em 'LEVEL' \\<description> not set.</td><td></td></tr>                                \n  <tr><td>M318</td> <td>WARNING</td><td>\\em 'LEVEL' \\em 'NAME' \\<\\em 'TAG'> is equal to \\<name></td><td></td></tr>                   \n  <tr><td>M319</td> <td>WARNING</td><td>\\em 'LEVEL' \\<\\em 'TAG'> \\em 'NAME' ends with newline, is this intended?</td><td></td></tr> \n  <tr><td>M320</td> <td>WARNING</td><td>\\em 'LEVEL' \\<description> \\em 'NAME' is not very descriptive</td><td></td></tr>       \n  <tr><td>M321</td> <td>WARNING</td><td>\\em 'LEVEL' \\<\\em 'ITEM'> \\em 'NAME' starts with '_', is this intended?</td><td></td></tr> \n  <tr><td>M322</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'ITEM' \\em 'NAME' is meaningless text. Deleted.</td><td></td></tr>          \n  <tr><td>M323</td> <td>WARNING</td><td>\\em 'LEVEL' \\<\\em 'ITEM'> \\em 'NAME' contains text \\em 'TEXT'</td><td></td></tr>             \n  <tr><td>M324</td> <td>ERROR</td><td>Field \\em 'NAME' \\em 'BITRANGE' does not fit into Register \\em 'NAME2':\\em 'NUM' \\em 'LINE'</td><td></td></tr>\n  <tr><td>M325</td> <td>ERROR</td><td>CPU Revision is not set\"</td><td></td></tr>                                                   \n  <tr><td>M326</td> <td>ERROR</td><td>Endianess is not set, using default (little)</td><td></td></tr>                         \n  <tr><td>M327</td> <td>ERROR</td><td>NVIC Prio Bits not set or wrong value, must be 2..8. Using default (4)</td><td></td></tr>\n  <tr><td>M328</td> <td>WARNING</td><td>\\em 'LEVEL' \\em 'NAME' has no Registers, ignoring \\em 'LEVEL'.</td><td></td></tr>                 \n  <tr><td>M329</td> <td>ERROR</td><td>CPU Type is not set, using default (Cortex-M3)</td><td></td></tr>                         \n  <tr><td>M330</td> <td>ERROR</td><td>Interrupt \\em 'NAME' Number not set.</td><td></td></tr>                                     \n  <tr><td>M331</td> <td>ERROR</td><td>Interrupt \\em 'NAME' Number \\em 'NUM' greater 239.</td><td></td></tr>                         \n  <tr><td>M332</td> <td>WARNING</td><td>\\em 'LEVEL' \\em 'NAME' has only one Register.</td><td></td></tr>                              \n  <tr><td>M333</td> <td>ERROR</td><td>Duplicate \\<enumeratedValue> \\em 'NUM': \\em 'NAME' (\\em 'USAGE'), already used by \\em 'NAME2' (\\em 'USAGE2') \\em 'LINE'</td><td></td></tr>\n  <tr><td>M334</td> <td>WARNING</td><td>\\em 'LEVEL' \\<\\em 'ITEM'> \\em 'NAME' is very long, use \\<description> and a shorter \\<name></td><td></td></tr>\n  <tr><td>M335</td> <td>ERROR</td><td>Value \\em 'NAME':\\em 'NUM' does not fit into field \\em 'NAME2' \\em 'BITRANGE'.</td><td></td></tr>\n  <tr><td>M336</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME' already defined \\em 'LINE'</td><td></td></tr>                           \n  <tr><td>M337</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME' already defined \\em 'LINE'</td><td></td></tr>                           \n  <tr><td>M338</td> <td>ERROR</td><td>Field \\em 'NAME' \\em 'BITRANGE' (\\em 'ACCESS') overlaps \\em 'NAME2' \\em 'BITRANGE2' (\\em 'ACCESS2') \\em 'LINE'</td><td></td></tr>\n  <tr><td>M339</td> <td>ERROR</td><td>Register \\em 'NAME' (\\em 'ACCESS') (\\@\\em 'ADDRSIZE') has same address or overlaps \\em 'NAME2' (\\em 'ACCESS2') (\\@\\em 'ADDRSIZE2') \\em 'LINE'</td><td></td></tr>\n  <tr><td>M340</td> <td>ERROR</td><td>No Devices found.</td><td></td></tr>                                              \n  <tr><td>M341</td> <td>ERROR</td><td>More than one devices found, only one is allowed per SVD File.</td><td></td></tr> \n  <tr><td>M342</td> <td>ERROR</td><td>Dim-extended \\em 'LEVEL' \\em 'NAME' must not have \\<headerStructName></td><td></td></tr> \n  <tr><td>M343</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME' (\\@\\em 'ADDR') has same address as \\em 'NAME2' \\em 'LINE'</td><td></td></tr> \n  <tr><td>M344</td> <td>ERROR</td><td>Register \\em 'NAME' (\\@\\em 'ADDRSIZE') is outside or does not fit any \\<addressBlock> specified for Peripheral \\em 'NAME2' \\n\n                                      \\em 'TEXT'</td><td></td></tr>\n  <tr><td>M345</td> <td>ERROR</td><td>Field \\em 'NAME' \\em 'BITRANGE' does not fit into Register \\em 'NAME2':\\em 'NUM'</td><td></td></tr>\n  <tr><td>M346</td> <td>WARNING</td><td>Register \\em 'NAME' (\\@\\em 'ADDR') offset is equal or is greater than it's Peripheral base address \\em 'NAME2' (\\@\\em 'ADDR2'), is this intended?</td><td></td></tr>\n  <tr><td>M347</td> <td>WARNING</td><td>Field \\em 'NAME' (width \\< 6Bit) without any \\<enumeratedValue> found.</td><td></td></tr>  \n  <tr><td>M348</td> <td>ERROR</td><td>Alternate \\em 'LEVEL' \\em 'NAME' does not exist at \\em 'LEVEL' address (\\@\\em 'ADDR')</td><td></td></tr>\n  <tr><td>M349</td> <td>ERROR</td><td>Alternate \\em 'LEVEL' \\em 'NAME' is equal to \\em 'LEVEL' name \\em 'NAME2'</td><td></td></tr>         \n  <tr><td>M350</td> <td>WARNING</td><td>Peripheral \\em 'NAME' (\\@\\em 'ADDR') is not 4Byte-aligned.</td><td></td></tr>                 \n  <tr><td>M351</td> <td>WARNING</td><td>Peripheral \\em 'TYPE' \\em 'NAME' is equal to Peripheral name.</td><td></td></tr>             \n  <tr><td>M352</td> <td>WARNING</td><td>AddressBlock of Peripheral \\em 'NAME' (\\@\\em 'ADDR') \\em 'TEXT' overlaps \\em 'NAME2' (\\@\\em 'ADDR2') \\em 'TEXT2' \\em 'LINE'</td><td></td></tr>\n  <tr><td>M353</td> <td>WARNING</td><td>Peripheral group name \\em 'NAME' should not end with '_'</td><td></td></tr>\n  <tr><td>M354</td> <td>ERROR</td><td>Interrupt '\\em 'NUM':\\em 'NAME' specifies a Core Interrupt. Core Interrupts must not be defined, they are set through \\<cpu>\\<name>.</td><td></td></tr>\n  <tr><td>M355</td> <td>ERROR</td><td>No Interrupts found on pos. 0..15. External (Vendor-)Interrupts possibly defined on position 16+. External Interrupts must start on position 0</td><td></td></tr>\n  <tr><td>M356</td> <td>WARNING</td><td>No Interrupt definitions found.</td><td></td></tr>\n  <tr><td>M357</td> <td>ERROR</td><td>Core Interrupts found. Interrupt Numbers are wrong. Internal Interrupts must not be described, External Interrupts must start at 0.</td><td></td></tr>\n  <tr><td>M358</td> <td>ERROR</td><td>AddressBlock of Peripheral \\em 'NAME' \\em 'TEXT' overlaps AddressBlock \\em 'TEXT2' in same peripheral \\em 'LINE'</td><td></td></tr>\n  <tr><td>M359</td> <td>ERROR</td><td>Address Block: \\<usage> not set.</td><td></td></tr>                                      \n  <tr><td>M360</td> <td>ERROR</td><td>Address Block: found \\<\\em 'TAG'> (\\em 'HEXNUM') > \\em 'HEXNUM2'.</td><td></td></tr>                 \n  <tr><td>M361</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'ITEM' \\em 'NAME': 'RESERVED' items must not be defined.</td><td></td></tr>       \n  <tr><td>M362</td> <td>WARNING</td><td>\\em 'LEVEL' \\em 'ITEM' \\em 'NAME': 'RESERVED' items must not be defined.</td><td></td></tr>     \n  <tr><td>M363</td> <td>ERROR</td><td>CPU: \\<sauNumRegions> not set.</td><td></td></tr>                                        \n  <tr><td>M364</td> <td>ERROR</td><td>CPU: \\<sauNumRegions> value \\em 'NUM' greater than SAU max num (\\em 'NUM2')</td><td></td></tr>\n  <tr><td>M365</td> <td>WARNING</td><td>Register \\em 'NAME' (\\em 'ACCESS') (\\@\\em 'ADDRSIZE') has same address or overlaps \\em 'NAME2' (\\em 'ACCESS2') (\\@\\em 'ADDRSIZE2') \\em 'LINE'</td><td></td></tr>\n  <tr><td>M366</td> <td>ERROR</td><td>Register \\em 'NAME' size (\\em 'NUM'Bit) is greater than \\<dimIncrement> * \\<addressBitsUnits> (\\em 'NUM2'Bit).</td><td></td></tr>\n  <tr><td>M367</td> <td>WARNING</td><td>Access Type: Field \\em 'NAME' (\\em 'ACCESS') does not match Register \\em 'NAME2' (\\em 'ACCESS2')</td><td></td></tr>\n  <tr><td>M368</td> <td>WARNING</td><td>\\em 'LEVEL' \\em 'NAME' (\\@\\em 'ADDR') has same address as \\em 'NAME2' \\em 'LINE'</td><td></td></tr>\n  <tr><td>M369</td> <td>ERROR</td><td>Enumerated Value \\em 'NAME': \\<value> not set.</td><td></td></tr>                      \n  <tr><td>M370</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME': \\<offset> not set.</td><td></td></tr>                              \n  <tr><td>M371</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME' \\<headerStructName> is equal to hirachical name</td><td></td></tr>  \n  <tr><td>M372</td> <td>ERROR</td><td>\\em 'LEVEL' \\<\\em 'TAG'> \\em 'NAME' already defined \\em 'LINE'</td><td></td></tr>                  \n  <tr><td>M373</td> <td>ERROR</td><td>\\em 'LEVEL' \\<\\em 'TAG'> \\em 'NAME' already defined \\em 'LINE'</td><td></td></tr>                  \n  <tr><td>M374</td> <td>WARNING</td><td>\\<enumeratedValues\\> can be one \\<enumeratedValues> container for all \\<enumeratedValue\\>s, where \\<usage> can be read, write, or read-write or two \\<enumeratedValues> containers, where one is set to \\<usage> read and the other is set to \\<usage> write</td><td></td></tr>\n  <tr><td>M375</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME' (\\<enumeratedValues\\> \\em 'NAME2'): Too many \\<enumeratedValues> container specified.</td><td></td></tr>\n  <tr><td>M376</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME' (\\<enumeratedValues\\> \\em 'NAME2'): \\em 'USAGE' container already defined in \\em 'LINE'.</td><td></td></tr>\n  <tr><td>M377</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME' (\\<enumeratedValues\\> \\em 'NAME2'): \\em 'USAGE' container conflicts with \\em 'NAME3' \\em 'LINE'.</td><td></td></tr>\n  <tr><td>M378</td> <td>ERROR</td><td>Register Array: Register \\em 'NAME' size (\\em 'NUM'Bit) does not match \\<dimIncrement\\> (\\em 'NUM2'Bit).</td><td></td></tr>\n  <tr><td>M379</td> <td>ERROR</td><td>XBin Number \\em 'NAME' too large, skipping evaluation.</td><td></td></tr>\n  <tr><td>M380</td> <td>ERROR</td><td>AddressBlock of Peripheral \\em 'NAME' (\\@\\em 'ADDR') \\em 'TEXT' does not fit into 32Bit Address Space.</td><td></td></tr>\n  <tr><td>M381</td> <td>ERROR</td><td>Interrupt \\em 'NAME' Number \\em 'NUM' greater or equal deviceNumInterrupts (\\em 'NUM2').</td><td></td></tr>\n  <tr><td>M382</td> <td>ERROR</td><td>\\em 'LEVEL' \\em 'NAME': \\em 'NAME2' \\em 'HEXNUM' does not fit into \\em 'LEVEL' width: \\em 'NUM' Bit.</td><td></td></tr>\n</table>\n\nData modification errors\n-----------------\n\n<table class=\"cmtable\" summary=\"SfrCC2 related Data modification Errors\">\n  <tr>\n    <th>Message Number</th>\n    <th>Type</th>\n    <th>Message Text</th>\n    <th>Action</th>\n  </tr>\n  <tr><td>M517</td> <td>WARNING</td><td>SFD Code generation: Forbidden Trigraph '??%CHAR%' found in \\em 'NAME'.</td><td></td></tr>\n  <tr><td>M516</td> <td>WARNING</td><td>SFD Code generation: Unsupported character found in \\em 'NAME' : \\em 'HEX'.</td><td></td></tr>\n  <tr><td>M518</td> <td>WARNING</td><td>SFD Code generation: Unsupported ESC sequence found in \\em 'NAME' : \\em 'CHAR'.</td><td></td></tr>\n</table>\n*/\n\n\n/* ************************************************************************************************ */\n/**\n\\page svd_Format_pg SVD Description (*.svd) Format\n\nThe CMSIS-SVD format is based on XML and was influenced by IP-XACT.\nDue to the much wider scope and complexity of IP-XACT, it was decided to specify a separate \nformat focused and tailored towards the description of the programmer's view of a device.\n\n<strong>CMSIS-SVD XML Hierarchy</strong>\n\n   \\image html CMSIS_SVD_Schema_Gen.png \"CMSIS-SVD Hierarchy Levels\"\n\nOne CMSIS-SVD file contains the description of a single device. A device consists of a processor and at least\none peripheral. Each peripheral contains at least one register. A register may consist of one or more fields.\nThe range of values for a field may be further described with enumerated values.\n\n- \\subpage svd_xml_conventions_gr \"File Conventions:\"\nOutlines the main conventions for writing an SVD description file.\n\\n\\n\n- \\subpage svd_Example_pg \nProvides an example outlining the SVD XML structure.\n\\n\\n\n- \\subpage elem_device \"Device Level:\"\nThe top level of a System View Description is the device. On this level, information is captured that \nis specific to the device as a whole. For example, the device name, description, or version. The minimal \naddressable unit as well as the bit-width of the data bus are required by the debugger to perform the\ncorrect target accesses. \\n\nDefault values for register attributes like register size, reset value, and access permissions can be set for the \nwhole device on this level and are implicitly inherited by the lower levels of the description. If however specified\non a lower level, the default setting from a higher level will get overruled.\n\\n\\n\n- \\subpage elem_cpu \"CPU Level:\"\nThe CPU section describes the processor included in the microcontroller device.\nThis section is mandatory if the SVD file is used to generate the device header file.\n\\n\\n\n- \\subpage elem_peripherals \"Peripherals Level:\"\nA peripheral is a named collection of registers. A peripheral is mapped to a defined <em>base address</em> within the \ndevice's address space. A peripheral allocates one or more exclusive address blocks relative to its base address, \nsuch that all described registers fit into the allocated address blocks. Allocated addresses without an associated\nregister description are automatically considered reserved. The peripheral can be assigned to a group of\nperipherals and may be associated with one or more interrupts.\n\\n\\n\n- \\subpage elem_registers \"Registers Level:\"\nA register is a named, programmable resource that belongs to a peripheral. Registers are mapped to a defined address in\nthe address space of the device. An address is specified relative to the peripheral base address. \nThe description of a register documents the purpose and function of the resource. A debugger requires information\nabout the permitted access to a resource as well as side effects triggered by read and write accesses respectively.\n\\n\\n\n- \\subpage elem_fields \"Fields Level:\"\nRegisters may be partitioned into chunks of bits of distinct functionality. A chunk\nis referred to as <em>field</em>. The field names within a single register must be unique.\nOnly architecturally defined fields shall be described. Any bits not being explicitly described are treated as reserved.\nThey are not displayed in the System Viewer and are padded in the bit fields of the device header file.\nThe case-insensitive field named <b>&quot;reserved&quot;</b> is treated as a keyword and each field with this name\nis ignored.\n\\n\\n\n- \\subpage elem_enumeratedValues \"Enumerated Values Level:\"\nAn enumeration maps an unsigned integer constant to a descriptive identifier and, optionally, to a description string.\nEnumerations are used in C to enhance the readability of source code. Similarly, it can be used by debuggers to\nprovide more instructive information to the programmer, avoiding a lookup in the device documentation.\n\\n\\n\n- \\subpage elem_special \"Special Elements:\"\nSpecific elements that occur in various other elements are described in this section.\n\\n\\n \n- <b>Vendor Extensions:</b>\nThe CMSIS-SVD format includes a section named \\tagem{vendorExtensions} positioned after the closing tag \\tagem{/peripherals}.\nThis allows silicon vendors and tool partners to extend the description beyond the current specification.\n\n\n<b>Multiple Instantiation</b>\n\nCMSIS-SVD supports the reuse of whole sections of the description. The attribute \\em derivedFrom for\n\\refelem{peripheral}, \\refelem{register}, and \\refelem{field} specifies the source of the section to be copied from.\nIndividual tags can be used to redefine specific elements within a copied section. \n\n<b>Array of Elements</b>\n\nA powerfull construct in data structures of the C programming language is the array. An \narray is a series of data elements of the same type selected via an index. CMSIS-SVD supports arrays\nfor \\refelem{peripheral}, \\refelem{cluster}, and \\refelem{register}.\n\n<b>Peripheral Grouping</b>\n\nPeripherals that provide similar functionality (Simple Timer, Complex Timer) can be grouped with the element \\tagem{groupName}. \nPeripheral groups help structuring the list of peripherals in the debugger.\nAll peripherals associated with the same group name are collectively listed under this group \nin the order they were specified in the SVD file. \n\n<b>Descriptions</b>\n\nOn each level, the tag \\tagem{description} provides verbose information about the respective element. \nThe description field plays an important part in improving software development productivity as it gives \ninstant access to information that otherwise would need to be looked up in the device documentation.\n\nAll multiple whitespace characters (space, tab, linefeed, carriage return) may be removed from the description\nby any tool for further processing (i.e. SVDConv does). In order to preserve explicit linebreaks one has to\nuse the linefeed escape sequence (i.e. \\\\n).\n\n&nbsp;\n*/\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/SVD/src/svd_schema.txt",
    "content": "/* ************************************************************************************************ */\n/**\n\\page svd_xml_conventions_gr File Conventions\n\nThe section outlines the main conventions for writing the SVD description file.\n\n    \\section Names\n    All <b>name</b> tags must comp\nly with the ANSI C identifier naming restrictions. In particular, they\n    must not contain any spaces or special characters. This is necessary to support the generation of device header files\n    thus providing consistency between the names being shown by the debugger and the symbols being used in the CMSIS\n    compliant target software.\n\n    \\section Constants\n    Number constants shall be entered in hexadecimal, decimal, or binary format.\n        \\li The Hexadecimal format is indicated by a leading <b>\\token{0x}</b>. \n        \\li The Binary format is indicated by a leading <b>\\token{#}</b>.\n        \\li All other formats are interpreted as decimal numbers.\n        \\li\tThe element \\tagem{enumeratedValue}.\\tagem{value} can be used to define constants.\n        \n    \\section Comments \n    Comments have the standard XML format. \n        \\li Start a comment with <b>\\token{\\<!\\-\\-}</b>.\n        \\li End a comment with <b>\\token{\\-\\-\\>}</b>.\n\n    \\section _ Empty Tags\n      - Single tags are not supported (for example, \\tagem{name\\\\}).\n      - The tag content must not consist of an empty string. Omit optional tags instead.\n\n    \\remarks\n        The latest \\ref schema_1_2_gr is provided alongside this document.\n\n*/\n\n\n/* ************************************************************************************************ */\n/** \n\\page elem_device /device element\n\nThe element \\tagem{device} provides the outermost frame of the description. \n    - Only one \\tagem{device} section is allowed per file. All other elements are described within this scope. \n    - A \\tagem{device} contains one or more peripherals, but one \\tagem{cpu} description.\n    - Optional elements such as \\tagem{size}, \\tagem{access}, or \\tagem{resetValue} defined on this level \n      represent default values for registers and can be refined at lower levels.\n\n<b>Example</b>\n\\code\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\">\n  <vendor>ARM Ltd.</vendor>\n  <vendorID>ARM</vendorID>\n  <name>ARM_Cortex_M4</name>\n  <series>ARMCM4</series>\n  <version>0.1</version>\n  <description>Arm Cortex-M4 based Microcontroller demonstration device</description>\n  <licenseText>\n    Arm Limited (Arm) is supplying this software for use with Cortex-M \\n\n    processor based microcontrollers.  This file can be freely distributed \\n\n    within development tools that are supporting such Arm based processors. \\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED \\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF \\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. \\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR \\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n  ...\n  <headerSystemFilename>system_ARMCM4</headeSystemFilename>\n  <headerDefinitionsPrefix>ARM_</headerDefinitionsPrefix>\n  <addressUnitBits>8</addressUnitBits>\n  <width>32</width>\n  <size>32</size>\n  <access>read-write</access>\n  <resetValue>0</resetValue>\n  <resetMask>0xffffffff</resetMask>\n  <peripherals>\n    ...\n  </peripherals>\n</device>\n\\endcode\n\nThis example describes a device from the vendor \\token{ARM Ltd.} using \\token{ARM} as short name. \nThe device belongs to the device family \\token{ARMCM4}. The device description is at version \\token{0.1} and uniquely identifies the device by the name \\token{ARM_Cortex_M4}. The legal disclaimer in the header files generated from\nthis description is captured and formatted in accordance to the standard Arm CMSIS disclaimer. The CMSIS system file included by the\ngenerated device header file is named \\token{system_ARMCM4.h} and all type definitions will be prepended with \\token{ARM_}.\n\nThe peripherals are memory mapped in a byte-addressable address space with a bus width of \\token{32} bits. \nThe default size of the registers contained in the peripherals is set to \\token{32} bits. \nUnless redefined for specific peripherals, all registers or fields are \\token{read-write} accessible. \nA reset value of \\token{0}, valid for all \\token{32} bits as specified by the reset mask, \nis set for all registers unless redefined at a lower level.\n\n\\anchor elem_device_sc\n\\b /device \n<table class=\"cmtable\" summary=\"Device Level Schema\">\n  <tr>\n    <th>Parent Level</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>root</td>\n    <td colspan=\"3\">None; Document root</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>xmlns:xs</td>\n    <td>Specify the underlying XML schema to which the CMSIS-SVD schema is compliant. \n    Has to be set to: \\token{\"http://www.w3.org/2001/XMLSchema-instance\"}.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>xs:noNamespaceSchemaLocation</td>\n    <td>Specify the file path and file name of the CMSIS-SVD Schema. For example, \\token{CMSIS-SVD.xsd}.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>schemaVersion</td>\n    <td>Specify the compliant CMSIS-SVD schema version (for example, \\token{1.1}).</td>\n    <td>xs:decimal</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>vendor</td>\n    <td>Specify the vendor of the device using the full name. </td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>vendorID</td>\n    <td>Specify the vendor abbreviation without spaces or special characters. This information is used \n        to define the directory. </td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The string identifies the device or device series. Device names are required to be unique.</td>\n    <td>xs:string </td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>series</td>\n    <td>Specify the name of the device series. </td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>version</td>\n    <td>Define the version of the SVD file. Silicon vendors maintain the description \n    throughout the life-cycle of the device and ensure that all updated and released copies \n    have a unique version string. Higher numbers indicate a more recent version. </td>\n  </tr>\n    <td>xs:string </td>\n    <td>1..1 </td>\n  <tr>\n    <td>description </td>\n    <td>Describe the main features of the device (for example CPU, clock frequency, peripheral overview).</td>\n    <td>xs:string </td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>licenseText </td>\n    <td>The text will be copied into the header section of the generated device header file and shall contain the legal disclaimer. \n        New lines can be inserted by using \\token{\\\\n}. This section is mandatory if the SVD file is used for generating the device header file.</td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>\\refelem{cpu} </td>\n    <td>Describe the processor included in the device.</td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>headerSystemFilename </td>\n    <td>Specify the file name (without extension) of the device-specific system include file (<kbd>system_<device>.h</kbd>; See CMSIS-Core description). \n        The header file generator customizes the include statement referencing the CMSIS system file within the CMSIS device header file. \n        By default, the filename is <kbd>system_<i>device-name</i>.h</kbd>. In cases where a device series shares a single system header file, \n        the name of the series shall be used instead of the individual device name. </td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>headerDefinitionsPrefix </td>\n    <td>This string is prepended to all type definition names generated in the CMSIS-Core device header file. \n        This is used if the vendor's software requires vendor-specific types in order to avoid name clashes with other definied types.</td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>addressUnitBits </td>\n    <td>Define the number of data bits uniquely selected by each address. \n    The value for Cortex-M-based devices is  \\token{8} (byte-addressable).\n    </td>\n    <td>scaledNonNegativeInteger </td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>width </td>\n    <td>Define the number of data bit-width of the maximum single data transfer supported \n    by the bus infrastructure. This information is relevant for debuggers when accessing \n    registers, because it might be required to issue multiple accesses for resources of a bigger size. \n    The expected value for Cortex-M-based devices is \\token{32}.</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group2\">\n     <td>&nbsp;</td>\n     <td colspan=\"3\" style=\"white-space:pre-wrap;\">Refer to \\ref registerPropertiesGroup_gr for details about the colored elements listed below.</td>\n  </tr>\n  <tr class=\"group2\">\n    <td>size</td>\n    <td>Default bit-width of any register contained in the device.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1</td>\n  </tr>\n  <tr class=\"group2\">\n    <td>access</td>\n    <td>Default access rights for all registers.</td>\n    <td>accessType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>protection</td>\n    <td>Default access protection for all registers.</td>\n    <td>protectionStringType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>resetValue </td>\n    <td>Default value for all registers at RESET.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>resetMask</td>\n    <td>Define which register bits have a defined reset value.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>\\refelem{peripherals}</td>\n    <td>Group to define peripherals. </td>\n    <td>&nbsp;</td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>vendorExtensions </td>\n    <td>The content and format of this section is unspecified. \n    Silicon vendors may choose to provide additional information. By default, this section \n    is ignored when constructing CMSIS files. It is up to the silicon vendor to specify \n    a schema for this section.\n    </td>\n    <td>xs:anyType (restriction) </td>\n    <td>0..1 </td>\n  </tr>\n</table>\n*/\n\n/* ************************************************************************************************ */\n/**\n\\page elem_cpu /device/cpu element\n\nThe CPU section describes the processor included in the microcontroller device.\nThis section is mandatory if the SVD file is used to generate the device header file.\n\n<b>Example</b>\n\\code\n<device>\n  ...\n  <cpu>\n    <name>CM7</name> \n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <!-- has double precision FPU -->\n    <fpuPresent>true</fpuPresent>\n    <fpuDP>true</fpuDP>\n    <!-- has instruction and data cache -->\n    <icachePresent>true</icachePresent>\n    <dcachePresent>true</dcachePresent>\n    <!-- has no instruction nor data tighly coupled memory -->\n    <itcmPresent>false</itcmPresent>\n    <dtcmPresent>false</dtcmPresent>\n    <nvicPrioBits>4</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig> \n  </cpu>\n  ...\n<device>\n\\endcode\n\nThis example describes a device based on a \\token{Cortex-M7} core of HW revision \\token{r0p0}, \nwith fixed \\token{little} endian memory scheme, including \\token{Memory Protection Unit} and \n\\token{double precision hardware Floating Point Unit}. It has a \\token{data cache} and no \\token{instruction} nor\na tightly coupled memory. The Nested Vectored Interrupt Controller uses \\token{4} bits \nto configure the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by Arm.\n\n\\anchor elem_cpu_sc\n\\b  /device/cpu\n<table class=\"cmtable\" summary=\"CPU Section Elements\">\n    <tr>\n        <th style=\"white-space:nowrap\">Parent Element</th>\n        <th colspan=\"3\">Element Chain</th>\n    </tr>\n    <tr>\n        <td>\\ref elem_device \"device\"</td>\n        <td colspan=\"3\">\\ref elem_device \"/device\"</td>\n    </tr>\n    <tr>\n        <th style=\"white-space:nowrap\">Child Elements</th>\n        <th>Description</th>\n        <th>Type</th>\n        <th>Occurrence</th>\n    </tr>\n    <tr>\n        <td>name</td>\n        <td>The predefined tokens are:\n        - \\token{CM0}: Arm Cortex-M0 \n        - \\token{CM0PLUS}: Arm Cortex-M0+\n        - \\token{CM0+}: Arm Cortex-M0+\n        - \\token{CM1}: Arm Cortex-M1 \n        - \\token{CM3}: Arm Cortex-M3\n        - \\token{CM4}: Arm Cortex-M4\n        - \\token{CM7}: Arm Cortex-M7\n        - \\token{CM23}: Arm Cortex-M23\n        - \\token{CM33}: Arm Cortex-M33\n        - \\token{CM35P}: Arm Cortex-M35P\n        - \\token{CM55}: Arm Cortex-M55\n        - \\token{CM85}: Arm Cortex-M85\n        - \\token{SC000}: Arm Secure Core SC000\n        - \\token{SC300}: Arm Secure Core SC300\n        - \\token{CA5}: Arm Cortex-A5\n        - \\token{CA7}: Arm Cortex-A7\n        - \\token{CA8}: Arm Cortex-A8\n        - \\token{CA9}: Arm Cortex-A9\n        - \\token{CA15}: Arm Cortex-A15\n        - \\token{CA17}: Arm Cortex-A17\n        - \\token{CA53}: Arm Cortex-A53\n        - \\token{CA57}: Arm Cortex-A57\n        - \\token{CA72}: Arm Cortex-A72\n        - \\token{SMC1}: Arm China STAR-MC1\n        - \\token{other}: other processor architectures\n        </td>\n        <td>cpuNameType</td>\n        <td>1..1 </td>\n    </tr> \n    <tr>\n        <td>revision</td>\n        <td>Define the HW revision of the processor. The version format is \\token{r<em>N</em>p<em>M</em>} (N,M = [0 - 99]). </td>\n        <td>revisionType</td>\n        <td>1..1 </td>\n    </tr>\n    <tr>\n        <td>endian </td>\n        <td>Define the endianness of the processor being one of:\n         - \\token{little}: little endian memory (least significant byte gets allocated at the lowest address).\n         - \\token{big}: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).\n         - \\token{selectable}: little and big endian are configurable for the device and become active after the next reset.\n         - \\token{other}: the endianness is neither little nor big endian.\n        </td>\n        <td>endianType </td>\n        <td>1..1 </td>\n    </tr>\n    <tr>\n        <td>mpuPresent </td>\n        <td>Indicate whether the processor is equipped with a memory protection unit (MPU). This tag is either set to \\token{true} or \\token{false}, \\token{1} or \\token{0}.</td>\n        <td>boolean </td>\n        <td>1..1 </td>\n    </tr>\n    <tr>\n        <td>fpuPresent </td>\n        <td>Indicate whether the processor is equipped with a hardware floating point unit (FPU). Cortex-M4, Cortex-M7, Cortex-M33 and Cortex-M35P are the only available Cortex-M processor with an optional FPU. This tag is either set to \\token{true} or \\token{false}, \\token{1} or \\token{0}.</td>\n        <td>boolean </td>\n        <td>1..1 </td>\n    </tr>\n    <tr>\n        <td>fpuDP </td>\n        <td>Indicate whether the processor is equipped with a double precision floating point unit. This element is valid only when \\tagem{fpuPresent} is set to \\token{true}. Currently, only Cortex-M7 processors can have a double precision floating point unit.</td>\n        <td>boolean</td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>dspPresent </td>\n        <td>Indicates whether the processor implements the optional SIMD DSP extensions (DSP). Cortex-M33 and Cortex-M35P are the only available Cortex-M processor with an optional DSP extension. For ARMv7M SIMD DSP extensions are\n        a mandatory part of Cortex-M4 and Cortex-M7. This tag is either set to \\token{true} or \\token{false}, \\token{1} or \\token{0}.</td>. This element is mandatory for Cortex-M33, Cortex-M35P and future processors with optional\n        SIMD DSP instruction set.\n        <td>boolean </td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>icachePresent</td>\n        <td>Indicate whether the processor has an instruction cache. Note: only for Cortex-M7-based devices. </td>\n        <td>boolean </td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>dcachePresent</td>\n        <td>Indicate whether the processor has a data cache. Note: only for Cortex-M7-based devices. </td>\n        <td>boolean </td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>itcmPresent</td>\n        <td>Indicate whether the processor has an instruction tightly coupled memory. \n            Note: only an option for Cortex-M7-based devices. </td>\n        <td>boolean </td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>dtcmPresent</td>\n        <td>Indicate whether the processor has a data tightly coupled memory. Note: only for Cortex-M7-based devices. </td>\n        <td>boolean </td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>vtorPresent </td>\n        <td>Indicate whether the Vector Table Offset Register (VTOR) is implemented in Cortex-M0+ based devices. \n            This tag is either set to \\token{true} or \\token{false}, \\token{1} or \\token{0}. \n            If not specified, then VTOR is assumed to be present.</td>\n        <td>boolean </td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>nvicPrioBits </td>\n        <td>Define the number of bits available in the Nested Vectored Interrupt Controller (NVIC) for configuring priority.</td>\n        <td>scaledNonNegativeInteger </td>\n        <td>1..1 </td>\n    </tr>\n    <tr>\n        <td>vendorSystickConfig</td>\n        <td>Indicate whether the processor implements a vendor-specific System Tick Timer. If \\token{false}, then the Arm-defined System Tick Timer is available. If \\token{true}, then a vendor-specific System Tick Timer must be implemented. This tag is either set to \\token{true} or \\token{false}, \\token{1} or \\token{0}.</td>\n        <td>boolean </td>\n        <td>1..1 </td>\n    </tr>\n    <tr>\n        <td>deviceNumInterrupts</td>\n        <td>Add \\token{1} to the highest interrupt number and specify this number in here. You can start to enumerate interrupts from \\token{0}.\n            Gaps might exist between interrupts. For example, you have defined interrupts with the numbers \\token{1}, \\token{2}, and \\token{8}. \n            Add \\token{9 :(8+1)} into this field.</td>\n        <td>scaledNonNegativeInteger</td>\n        <td>0..1 </td>\n   </tr>        \n    <tr>\n        <td>sauNumRegions</td>\n        <td>Indicate the amount of regions in the Security Attribution Unit (SAU).\n            If the value is greater than zero, then the device has a SAU and the \n            number indicates the maximum amount of available address regions.\n        </td>\n        <td>scaledNonNegativeInteger </td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>\\refelem{sauRegionsConfig}</td>\n        <td>If the Secure Attribution Unit is preconfigured by HW or Firmware, then the settings are described here.</td>\n        <td>SauRegionsConfigType</td>\n        <td>0..1 </td>\n    </tr>        \n</table>\n\n\\delim_sec\n\n\\section elem_sauRegionsConfig /device/cpu/sauRegionsConfig element\n\nSet the configuration for the Secure Attribution Unit (SAU) when they are preconfigured by HW or Firmware.\n\n<b>Example</b>\n\\code\n<device>\n  ...\n  <sauRegionsConfig protectionWhenDisabled=\"n\">\n    <region>\n      ...\n    </region>\n    ...\n    <region>\n      ...\n    </region>\n  </sauRegionsConfig>\n  ...\n</device>\n\\endcode\n\nThe example defines two Secure Attribution Units, which are enabled by default. When \nthe SAU regions are disabled, the protection level is non-secure (\\token{n}).\n\n\\anchor elem_sauRegionsConfig_sc\n\\b /device/cpu/sauRegionsConfig\n<table class=\"cmtable\" summary=\"sauRegionsConfig tab elements\">\n    <tr>\n        <th style=\"white-space:nowrap\">Parent Element</th>\n        <th colspan=\"3\">Element Chain</th>\n    </tr>\n    <tr>\n        <td>\\refelem{cpu}</td>\n        <td colspan=\"3\">\\ref elem_cpu</td>\n    </tr>\n    <tr>\n        <th style=\"white-space:nowrap\">Attributes</th>\n        <th>Description</th>\n        <th>Type</th>\n        <th>Use</th>\n    </tr>\n    <tr>\n        <td>enabled</td>\n        <td>Specify whether the Secure Attribution Units are enabled. The following values can be used:\n            \\token{true},\\token{false},\\token{1}, and \\token{0}.\n        </td>\n        <td>xs:boolean</td>\n        <td>optional</td>\n    </tr>\n    <tr>\n        <td>\\ref elem_protection \"protectionWhenDisabled\"</td>\n        <td>Set the protection mode for disabled regions. \n           When the complete SAU is disabled, the whole memory is treated either \\token{\"s\"}=secure or \\token{\"n\"}=non-secure.\n           This value is inherited by the \\tagem{region} element. Refer to element \\refelem{protection} for details and predefined values.\n        </td>\n        <td>xs:string</td>\n        <td>optional</td>\n    </tr>\n    <tr>\n        <th style=\"white-space:nowrap\">Child Elements</th>\n        <th>Description</th>\n        <th>Type</th>\n        <th>Occurrence</th>\n    </tr>\n    <tr>\n        <td>\\refelem{region}</td>\n        <td>Group to configure SAU regions.</td>\n        <td>xs:string</td>\n        <td>0..*</td>\n    </tr>\n</table>\n\n\\delim_sec\n \n\\section elem_region /device/cpu/sauRegionsConfig/region element\n\nDefine the regions of the Secure Attribution Unit (SAU). The protection level is inherited from the attribute \n\\tagem{protectionWhenDisabled} of the enclosing element \\refelem{sauRegionsConfig}.\n\n\\b Example:\n\\code\n<sauRegionsConfig>\n  <region name=\"SAU1\">\n    <base>0x10001000</base>\n    <limit>0x10005000</limit>\n    <access>n</access>\n  </region>\n  <region enabled=\"false\" name=\"SAU2\">\n    <base>0x10006000</base>\n    <limit>0x10008000</limit>\n    <access>c</access>\n  </region>\n</sauRegionsConfig>\n\\endcode\n\nThe example defines two secure regions with the names \\em SAU1 and \\em SAU2.\nSAU1 has the address boundries \\token{0x10001000} and \\token{0x10005000}. The region has non-secure access rights.\nSAU2 has the address boundries \\token{0x10006000} and \\token{0x10008000}. The region has secure callable access rights.\n\n\\anchor elem_region_sc \n\\b /device/cpu/sauRegionsConfig/region\n<table class=\"cmtable\" summary=\"region tab elements\">\n    <tr>\n        <th style=\"white-space:nowrap\">Parent Element</th>\n        <th colspan=\"3\">Element Chain</th>\n    </tr>\n    <tr>\n        <td>\\ref elem_sauRegionsConfig \"sauRegionsConfig\"</td>\n        <td colspan=\"3\">\\ref elem_sauRegionsConfig </td>\n    </tr>\n    <tr>\n        <th style=\"white-space:nowrap\">Attributes</th>\n        <th>Description</th>\n        <th>Type</th>\n        <th>Use</th>\n    </tr>\n    <tr>\n        <td>enabled</td>\n        <td>Specify whether the Secure Attribution Units are enabled. The following values can be used:\n            \\token{true} and \\token{false}, or \\token{1} and \\token{0}. Default value is \\token{true}.</td>\n        <td>xs:boolean</td>\n        <td>optional</td>\n    </tr>\n    <tr>\n        <td>name</td>\n        <td>Identifiy the region with a name. </td>\n        <td>xs:string</td>\n        <td>optional</td>\n    </tr>\n    <tr>\n        <th style=\"white-space:nowrap\">Child Elements</th>\n        <th>Description</th>\n        <th>Type</th>\n        <th>Occurrence</th>\n    </tr>\n    <tr>\n        <td>base</td>\n        <td>Base address of the region.</td>\n        <td>scaledNonNegativeInteger</td>\n        <td>1..1</td>\n    </tr>\n    <tr>\n        <td>limit</td>\n        <td>Limit address of the region.</td>\n        <td>scaledNonNegativeInteger</td>\n        <td>1..1</td>\n    </tr>\n    <tr>\n        <td>access</td>\n        <td>Use one of the following predefined values to define the acces type of a region:\n            \\n - \\token{n} : non-secure\n            \\n - \\token{c} : secure callable</td>\n        <td>xs:string</td>\n        <td>1..1</td>\n    </tr>\n</table>\n*/\n\n\n\n/* ************************************************************************************************ */\n/**\n\\page elem_peripherals /device/peripherals element \n\nAll peripherals of a device are enclosed within the tag \\tagem{peripherals}. \n\n\n\\b Example:\n\\code\n<device>\n  ...\n  <peripherals>\n     ...\n  </peripherals>\n<device>\n\\endcode\n\n\\anchor elem_peripherals_sc \n\\b /device/peripherals\n<table class=\"cmtable\" summary=\"Peripherals Level\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref elem_device \"device\"</td>\n    <td colspan=\"3\">\\ref elem_device</td>\n  </tr>\n  <tr>\n    <th style=\"white-space:nowrap\">Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\subpage elem_peripheral \"peripheral\"</td>\n    <td>Define the sequence of peripherals.</td>\n    <td>peripheralType</td>\n    <td>1..*</td>\n    </tr>\n</table>\n\n\\delim_sec\n\n\\section elem_peripheral /device/peripherals/peripheral element\n\nAt least one peripheral has to be defined. \n- Each peripheral describes all registers belonging to that peripheral. \n- The address range allocated by a peripheral is defined through one or more address blocks. \n- An address block and register addresses are specified relative to the base address of a peripheral. \nThe address block information can be used for constructing a memory map for the device peripherals.\n\nStarting version 1.3 of the SVD specification, arrays of peripherals can be specified. \nThe single peripheral description gets duplicated automatically into an array. \nThe number of array elements is specified by the \\tagem{dim} element. To define arrays, the \\tagem{name} needs \nthe format <em>myPeripheral[%%s]</em>. The tag \\tagem{dimIncrement} specifies the address offset between two \nperipherals. To create copies of a peripheral using different names, you must use the \\em derivedFrom attribute.\n\n\\remarks  The memory map does not contain any information about physical memory. The memory of a\ndevice is described as part of the CMSIS-Pack device description.\n\n\\b Example:\n\\code\n<peripherals>\n  <peripheral>\n    <name>Timer1</name>\n    <version>1.0</version>\n    <description>Timer 1 is a standard timer ... </description>\n    <baseAddress>0x40002000</baseAddress>\n    <addressBlock>\n      <offset>0x0</offset>\n      <size>0x400</size>\n      <usage>registers</usage>\n      <protection>s</protection>\n    </addressBlock>\n    <interrupt><name>TIM0_INT</name><value>34</value></interrupt>\n    <registers>\n      ...\n    </registers>\n  </peripheral>\n\n  <peripheral>\n    <name>Timer1_Alt</name>\n    <version>1.0</version>\n    <description>Alternate Timer 1 is a special timer execution mode ... </description>\n    <baseAddress>0x40002000</baseAddress>\n    <alternatePeripheral>Timer1</alternatePeripheral>\n    ...\n  </peripheral>\n</peripherals>\n\\endcode\n\nTwo timer peripheral descriptions are specified for the same memory block. No redefined addresses will be reported for both peripherals.\n\n\\anchor elem_peripheral_sc\n\\b /device/peripherals/peripheral\n<table class=\"cmtable\" summary=\"Peripheral Level Schema\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref elem_peripherals \"peripherals\"</td>\n    <td colspan=\"3\">\\ref elem_peripherals</td>\n  </tr>\n  <tr>\n    <th style=\"white-space:nowrap\">Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>derivedFrom</td>\n    <td>Specify the peripheral name from which to inherit data.\n        Elements specified subsequently override inherited values. </td>\n    <td>dimableIdentifierType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <th style=\"white-space:nowrap\">Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr class=\"group1\">\n    <td>&nbsp;</td>\n    <td colspan=\"3\">Refer to \\ref dimElementGroup_gr for details about the colored elements.</td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dim</td>\n    <td>Define the number of elements in an array.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimIncrement</td>\n    <td>Specify the address increment, in \\token{Bytes}, between two neighboring array members in the address map.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimIndex</td>\n    <td>Do not define on peripheral level. By default, \\tagem{dimIndex} is an integer value starting at \\token{0}.</td>\n    <td>dimIndexType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimName</td>\n    <td>Specify the name of the C-type structure. If not defined, then the entry of the \\tagem{name} element is used.</td>\n    <td>idnetifierType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>\\refelem{dimArrayIndex}</td>\n    <td>Grouping element to create enumerations in the header file.</td>\n    <td>dimArrayIndexType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>name </td>\n    <td>The string identifies the peripheral. Peripheral names are required to be unique for a device. \n        The name needs to be an ANSI C identifier to generate the header file. \n        You can use the placeholder <em>[%%s]</em> to create arrays.</td>\n    <td>dimableIdentifierType</td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>version </td>\n    <td>The string specifies the version of this peripheral description. </td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>description </td>\n    <td>The string provides an overview of the purpose and functionality of the peripheral.</td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>alternatePeripheral</td>\n    <td>All address blocks in the memory space of a device are assigned to a unique peripheral by default. If multiple\n\t\tperipherals describe the same address blocks, then this needs to be specified explicitly. A peripheral redefining an address block needs to\n\t\tspecify the name of the peripheral that is listed first in the description.</td>\n    <td>dimaleIdentifierType </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>groupName </td>\n    <td>Define a name under which the System Viewer is showing this peripheral.</td>\n    <td>xs:Name </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>prependToName </td>\n    <td>Define a string as prefix. All register names of this peripheral get this prefix.</td>\n    <td>identifierType </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>appendToName </td>\n    <td>Define a string as suffix. All register names of this peripheral get this suffix.</td>\n    <td>identifierType </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>headerStructName</td>\n    <td>Specify the base name of C structures. The headerfile generator uses the name of a peripheral as the base name for the C structure type. \n        If \\tagem{headerStructName} element is specfied, then this string is used instead of the peripheral name; useful when multiple peripherals get derived and a generic type name should be used.</td>\n    <td>dimableIdentifierType </td>\n    <td>0..1 </td>\n  </tr>\t\n  <tr>\n    <td>disableCondition </td>\n    <td>Define a C-language compliant logical expression returning a TRUE or FALSE result. \n        If TRUE, refreshing the display for this peripheral is disabled and related accesses by the debugger are suppressed. \n        \\n \\n Only constants and references to other registers contained in the description are allowed:  \n        \\tagem{peripheral}->\\tagem{register}->\\tagem{field}, for example, (System->ClockControl->apbEnable == 0). \n        The following operators are allowed in the expression [&&,||, ==, !=, >>, <<, &, |].\n        \\attention\n        Use this feature only in cases where accesses from the debugger to registers of \n        un-clocked peripherals result in severe debugging failures. SVD is intended to provide \n        static information and does not include any run-time computation or functions. \n        Such capabilities can be added by the tools, and is beyond the scope of this \n        description language.</td>\n    <td>stringType </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>baseAddress </td>\n    <td>Lowest address reserved or used by the peripheral.</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>&nbsp;</td>\n    <td colspan=\"3\" style=\"white-space:pre-wrap;\">Refer to \\ref registerPropertiesGroup_gr for details about the colored elements.</td>\n  </tr>\n  <tr class=\"group2\">\n    <td>size</td>\n    <td>Define the default bit-width of any register contained in the device (implicit inheritance).</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1</td>\n  </tr>\n  <tr class=\"group2\">\n    <td>access</td>\n    <td>Define default access rights for all registers.</td>\n    <td>accessType</td>\n    <td>0..1</td>\n  </tr>\n  <tr class=\"group2\">\n    <td>protection</td>\n    <td>Define default protection rights for all registers.</td>\n    <td>protectionStringType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>resetValue </td>\n    <td>Define the default value for all registers at RESET.</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>resetMask</td>\n    <td>Identify which register bits have a defined reset value.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>\\refelem{addressBlock}</td>\n    <td>Specify an address range uniquely mapped to this peripheral. A peripheral must \n        have at least one address block, but can allocate multiple distinct address ranges. \n        If a peripheral is derived from another peripheral, the addressBlock is not mandatory.</td>\n    <td>addressBlockType</td>\n    <td>0/1..*</td>\n  </tr>\n  <tr>\n    <td>\\refelem{interrupt}</td>\n    <td>A peripheral can have multiple associated interrupts. This entry allows the debugger \n        to show interrupt names instead of interrupt numbers.</td>\n    <td>interruptType </td>\n    <td>0..* </td>\n  </tr>\n  <tr>\n    <td>\\refelem{registers} </td>\n    <td>Group to enclose register definitions.</td>\n    <td>registersType</td>\n    <td>0..1 </td>\n  </tr>\n</table>\n\n\\delim_sec\n\n\\section elem_addressBlock /device/peripherals/peripheral/addressBlock element\n\nSpecify an address range uniquely mapped to this peripheral. A peripheral must \nhave at least one address block. If a peripheral is derived form another peripheral, the \\tagem{addressBlock} is not mandatory.\n\n\\b /device/peripherals/peripheral/addressBlock \n<table class=\"cmtable\" summary=\"addressBlock Type Table\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref elem_peripheral \"peripheral\"</td>\n    <td colspan=\"3\">\\ref elem_peripheral</td>\n  </tr>\n  <tr>\n    <th style=\"white-space:nowrap\">Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>offset </td>\n    <td>Specifies the start address of an address block relative to the peripheral \\em baseAddress.</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>1..1</td>\n  </tr>\n  <tr>\n    <td>size</td>\n    <td>Specifies the number of addressUnitBits being covered by this address block. \n        The end address of an address block results from the sum of baseAddress, offset, and (size - 1).</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>1..1</td>\n  </tr>\n  <tr>\n    <td>usage</td>\n    <td>The following predefined values can be used: \n         - \\token{registers}\n         - \\token{buffer}\n         - \\token{reserved}.</td>\n    <td>enumerated token </td>\n    <td>1..1</td>\n  </tr>\n  <tr>\n    <td>\\ref elem_protection \"protection\"</td>\n    <td>Set the protection level for an address block.</td>\n    <td>protectionStringType </td>\n    <td>0..1</td>\n  </tr>\n</table>\n\n\\delim_sec\n\n\\section elem_interrupt /device/peripherals/peripheral/interrupt element\n\nA peripheral can have multiple interrupts. This entry allows the debugger to show interrupt names instead of interrupt numbers.\n\n\\anchor elem_interrupt_sc\n\\b /device/peripherals/peripheral/interrupt\n<table class=\"cmtable\" summary=\"interrupt Type Table\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref elem_peripheral \"peripheral\"</td>\n    <td colspan=\"3\">\\ref elem_peripheral</td>\n  </tr>\n  <tr>\n    <th style=\"white-space:nowrap\">Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>name </td>\n    <td>The string represents the interrupt name.</td>\n    <td>stringType </td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>description</td>\n    <td>The string describes the interrupt.</td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>value </td>\n    <td>Represents the enumeration index value associated to the interrupt.</td>\n    <td>xs:integer </td>\n    <td>1..1 </td> \n  </tr>\n</table>\n*/\n\n/**\n\\page elem_registers /device/peripherals/peripheral/registers element\n\nAll registers of a peripheral are enclosed between the \\tagem{registers} opening and closing tags.\nClusters define a set of registers. You can either use the \\tagem{cluster} or the \\tagem{register} element.\n\n\\b Example:\n\\code\n...\n<peripheral>\n  <registers>\n    ...\n  </registers>\n</peripheral>\n...\n\\endcode\n\n\\anchor elem_registers_sc \n\\b /device/peripherals/peripheral/registers\n<table class=\"cmtable\" summary=\"Registers Type Table\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref elem_peripheral \"peripheral\"</td>\n    <td colspan=\"3\">\\ref elem_peripheral</td>\n  </tr>\n  <tr>\n    <th style=\"white-space:nowrap\">Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr class=\"choice\">\n    <td>\\ref elem_cluster \"cluster\"</td>\n    <td>Define the sequence of register clusters.</td>\n    <td>clusterType </td>\n    <td>0..*</td>\n  </tr>\n  <tr class=\"choice\">\n    <td>\\ref elem_register \"register\"</td>\n    <td>Define the sequence of registers.</td>\n    <td>registerType </td>\n    <td>1..*</td>\n  </tr>\n</table>\n\n\\delim_sec\n\n\\section elem_cluster /device/pripherals/peripheral/registers/.../cluster element\n\n<b>Cluster</b> describes a sequence of neighboring registers within a peripheral. A \\tagem{cluster} specifies\nthe <i>addressOffset</i> relative to the <i>baseAddress</i> of the grouping element. All \\tagem{register}\nelements within a \\tagem{cluster} specify their <i>addressOffset</i> relative to the cluster base address\n(\\tagem{peripheral.baseAddress} + \\tagem{cluster.addressOffset}).\n\nMultiple \\tagem{register} and \\tagem{cluster} sections may occur in any order.\nSince version 1.3 of the specification, the nesting of \\tagem{cluster} elements is supported. \nNested clusters express hierarchical structures of registers. It is predominantely targeted\nat the generation of device header files to create a C-data structure within the\nperipheral structure instead of a flat list of registers.\nNote, you can also specify an array of a cluster using the \\tagem{dim} element.\n\n\\anchor elem_cluster_sc\n<b>/device/pripherals/peripheral/registers/.../cluster</b>\n<table class=\"cmtable\" summary=\"Cluster Level Schema\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref elem_registers \"registers\"</td>\n    <td colspan=\"3\">\\ref elem_registers</td>\n  </tr>\n  <tr>\n    <td>\\ref elem_cluster \"cluster\"</td>\n    <td colspan=\"3\">\\ref elem_cluster</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>derivedFrom</td>\n\n    <td>Specify the cluster name from which to inherit data.\n        Elements specified subsequently override inherited values. \n        <br><b>Usage:</b>\n        - Always use the full qualifying path, which must start with the peripheral \\tagem{name}, when deriving from another scope. \n          (for example, in periperhal \\token{B}, derive from \\token{peripheralA.clusterX}). \n        - You can use the cluster \\tagem{name} when both clusters are in the same scope.\n        - No relative paths will work.\n        <br><b>Remarks:</b> When deriving a cluster, it is mandatory to specify at least \n        the \\tagem{name}, the \\tagem{description}, and the \\tagem{addressOffset}.</td>\n    <td>registerType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr class=\"group1\">\n    <td>&nbsp;</td>\n    <td colspan=\"3\">Refer to \\ref dimElementGroup_gr for details.</td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dim</td>\n    <td>Define the number of elements in an array of clusters. </td>\n    <td>scaledNonNegativeInteger </td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimIncrement</td>\n    <td>Specify the address increment, in \\token{Bytes}, between two neighboring clusters of the cluster array.</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimIndex</td>\n    <td>Specify the strings that substitute the placeholder <em>[%%s]</em> within the cluster \\tagem{name}. \n        Use the placeholder <em>%%s</em> in \\tagem{name} when \\tagem{dimIndex} is specified.</td>\n    <td>dimIndexType </td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimName</td>\n    <td>Specify the name of the C-type structure.  If not defined, then the entry of the \\tagem{name} element is used.</td>\n    <td>identifierType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>\\refelem{dimArrayIndex}</td>\n    <td>Grouping element to create enumerations in the header file.</td>\n    <td>dimArrayIndexType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>String to identify the cluster. Cluster names are required to be unique \n        within the scope of a peripheral. A list of cluster names can be build using the placeholder <em>%%s</em>.\n        Use the placeholder <em>[%%s]</em> at the end of the identifier to generate arrays in the header file.\n        The placeholder <em>[%%s]</em> cannot be used together with \\tagem{dimIndex}.</td>\n    <td>dimableIdentifierType</a> </td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>description</td>\n    <td>String describing the details of the register cluster.</td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>alternateCluster </td>\n    <td>Specify the name of the original cluster if this cluster provides an alternative description.</td>\n    <td>dimableIdentifierType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>headerStructName</td>\n    <td>Specify the struct type name created in the device header file. If not specified, then the name of the cluster is used.</td>\n    <td>identifierType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>addressOffset</td>\n    <td>Cluster address relative to the \\tagem{baseAddress} of the peripheral.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>&nbsp;</td>\n    <td colspan=\"3\">Refer to \\ref registerPropertiesGroup_gr for details.</td>\n  </tr>\n  <tr class=\"group2\">\n    <td>size</td>\n    <td>Define the default bit-width of any device register (implicit inheritance).</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>0..1 </td>\n  </tr> \n  <tr class=\"group2\">\n    <td>access</td>\n    <td>Define access rights.</td>\n    <td>accessType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>protection</td>\n    <td>Specify the security privilege to access an address region.</td>\n    <td>protectionStringType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>resetValue </td>\n    <td>Define the default value for all registers at RESET.</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>resetMask</td>\n    <td>Identify register bits that have a defined reset value.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>\\refelem{register}</td>\n    <td>Define a sequence of register within a cluster.</td>\n    <td>registerType</td>\n    <td>0..* </td>\n  </tr>\n  <tr>\n    <td>\\refelem{cluster}</td>\n    <td>Element to nest cluster definitions.</td>\n    <td>clusterType</td>\n    <td>0..* </td>\n  </tr>\n</table>\n\n\n\\delim_sec\n\n\\section elem_register /device/peripherals/peripheral/registers/.../register element\n\nThe description of registers is the most essential part of SVD. If the elements \\tagem{size}, \\tagem{access}, \\tagem{resetValue}, and \\tagem{resetMask}\nhave not been specified on a higher level, then these elements are mandatory on register level. \n\nA register can represent a single value or can be subdivided into individual bit-fields of specific functionality and semantics.\nFrom a schema perspective, the element \\tagem{fields} is optional, however, from a specification perspective, \n\\tagem{fields} are mandatory when they are described in the device documentation.\n\nYou can define register arrays where the single description gets duplicated automatically. \nThe size of the array is specified by the \\tagem{dim} element. Register names get composed by the element \\tagem{name} and\nthe index-specific string defined in \\tagem{dimIndex}. The element \\tagem{dimIncrement} specifies the address offset between two registers.\n\n\\b Example:\n\\code\n...\n<register>\n  <name>TimerCtrl0</name>\n  <description>Timer Control Register</description>\n  <addressOffset>0x0</addressOffset>\n  <access>read-write</access>\n  <resetValue>0x00008001</resetValue>\n  <resetMask>0x0000ffff</resetMask>\n  <size>32</size>\n</register>\n\n<register derivedFrom=\"TimerCtrl0\">\n  <name>TimerCtrl1</name>\n  <description>Derived Timer</description>\n  <addressOffset>0x4</addressOffset>\n</register>\n...\n\\endcode\n\nThis example describes two registers, \\b TimerCtrl0 and \\b TimerCtrl1. The values defined for \\b TimerCtrl0 are inherited by the derived register \n\\b TimerCtrl1, except for the value in \\tagem{addressOffset}.\n\n\\b Example:\n\\code\n...\n<register>\n    <name>TIM_MODEA</name>\n    <description>In mode A this register acts as a reload value</description>\n    <addressOffset>0xC</addressOffset>\n</register>\n<register>\n    <name>TIM_MODEB</name>\n    <description>In mode B this register acts as the compare value</description>\n    <alternateRegister>TIM_MODEA</alternateRegister>\n    <addressOffset>0xC</addressOffset>\n</register>\n<register>\n    <name>DMA_DATA</name>\n    <description>This register contains the address of the data being transferred</description>\n    <dataType>uint32_t *</dataType>\n    <addressOffset>0xf0</addressOffset>\n</register>\n...\n\\endcode\n\nThis example describes two registers, \\b TIM_MODEA and \\b TIM_MODEB. Both have the same address offset. Based on the configured operation\nmodel being A or B, the register acts as reload or compare value. The register DMA_DATA is specified as a pointer to unsigned word data. \nThe code generated for the device header file is:\n\n\\code\ntypedef struct {\n  union {\n    __IO   uint32_t TIM_MODEA;\n    __IO   uint32_t TIM_MODEB;\n    };\n  __IO uint32_t * DMA_DATA; \n  ...\n} <peripheral:name>_Type;\n\n\\endcode\n\n\n\\anchor elem_register_sc \n<b>/device/peripherals/peripheral/registers/.../register</b>\n<table class=\"cmtable\" summary=\"Register Level Schema\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\refelem{cluster}</td>\n    <td colspan=\"3\">\\ref elem_cluster</td>\n  </tr>\n  <tr>\n    <td>\\refelem{registers}</td>\n    <td colspan=\"3\">\\ref elem_registers</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>derivedFrom</td>\n\n    <td>Specify the register name from which to inherit data.\n        Elements specified subsequently override inherited values. \n        <br><b>Usage:</b>\n        - Always use the full qualifying path, which must start with the peripheral \\tagem{name}, when deriving from another scope. \n          (for example, in periperhal \\token{B}, derive from \\token{peripheralA.registerX}. \n        - You can use the register \\tagem{name} only when both registers are in the same scope.\n        - No relative paths will work.\n        <br><b>Remarks:</b> When deriving, it is mandatory to specify at least \n        the \\tagem{name}, the \\tagem{description}, and the \\tagem{addressOffset}.</td>\n    <td>xs:Name</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr class=\"group1\">\n    <td>&nbsp;</td>\n    <td colspan=\"3\">Refer to \\ref dimElementGroup_gr for details.</td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dim</td>\n    <td>Define the number of elements in an array of registers. If \\tagem{dimIncrement} is specified, this element becomes mandatory.</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimIncrement</td>\n    <td>Specify the address increment, in \\token{Bytes}, between two neighboring registers.</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimIndex</td>\n    <td>Specify the substrings that replaces the <em>%%s</em> placeholder within \\em name and \\em displayName.\n        By default, the index is a decimal value starting with 0 for the first register. \n        \\em dimIndex should not be used together with the placeholder <em>[%%s]</em>, but rather with <em>%%s</em>.</td>\n    <td>dimIndexType </td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimName</td>\n    <td>Specify the name of the C-type structure.  If not defined, then the entry of the \\tagem{name} element is used.</td>\n    <td>identifyerType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>\\refelem{dimArrayIndex}</td>\n    <td>Grouping element to create enumerations in the header file.</td>\n    <td>dimArrayIndexType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>String to identify the register. Register names are required to be unique \n        within the scope of a peripheral. You can use the placeholder <em>%%s</em>, which is replaced by the \\em dimIndex substring.\n        Use the placeholder <em>[%%s]</em> only at the end of the identifier to generate arrays in the header file.\n        The placeholder <em>[%%s]</em> cannot be used together with \\em dimIndex.</td>\n    <td>registerNameType</a> </td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>displayName</td>\n    <td>When specified, then this string can be used by a graphical frontend to visualize the register. \n        Otherwise the \\em name element is displayed. \\em displayName may contain special characters and white spaces. \n        You can use the placeholder <em>%%s</em>, which is replaced by the \\em dimIndex substring. \n        Use the placeholder <em>[%%s]</em> only at the end of the identifier.\n        The placeholder <em>[%%s]</em> cannot be used together with \\em dimIndex.</td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>description</td>\n    <td>String describing the details of the register.</td>\n    <td>xs:string </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>alternateGroup </td>\n    <td>Specifies a group name associated with all alternate register that have the same name. \n        At the same time, it indicates that there is a register definition allocating the same absolute address in the address space.</td>\n    <td>xs:Name </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>alternateRegister</td>\n    <td>This tag can reference a register that has been defined above to current location in the description and that  describes \n        the memory location already. This tells the SVDConv's address checker that the redefinition of this particular register is\n        intentional. The register name needs to be unique within the scope of the current peripheral. \n        A register description is defined either for a unique address location or could be a redefinition of an already described address. \n        In the latter case, the register can be either marked <em>alternateRegister</em>\n        and needs to have a unique name, or it can have the same register name but is assigned to a register subgroup through \n        the tag <em>alternateGroup</em> (specified in version 1.0).</td>\n    <td>identifierType </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>addressOffset</td>\n    <td>Define the address offset relative to the enclosing element.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>&nbsp;</td>\n    <td colspan=\"3\" style=\"white-space:pre-wrap;\">Refer to \\ref registerPropertiesGroup_gr for details about the colored elements.</td>\n  </tr>\n  <tr class=\"group2\">\n    <td>size</td>\n    <td>Defines the default bit-width of any register contained in the device (implicit inheritance).</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1</td>\n  </tr>\n  <tr class=\"group2\">\n    <td>access</td>\n    <td>Defines the default access rights for all registers.</td>\n    <td>accessType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>protection</td>\n    <td>Defines the protection rights for all registers.</td>\n    <td>protectionStringType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>resetValue </td>\n    <td>Defines the default value for all registers at RESET.</td>\n    <td>scaledNonNegativeInteger </td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group2\">\n    <td>resetMask</td>\n    <td>Identifies which register bits have a defined reset value.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>dataType</td>\n    <td>It can be useful to assign a specific native C datatype to a register. This helps avoiding\n        type casts. For example, if a 32 bit register shall act as a pointer to a 32 bit unsigned data item, then <i>dataType</i> can be set to \"uint32_t *\".\n        The following simple data types are predefined:\n        - \\token{uint8_t}: unsigned byte\n        - \\token{uint16_t}: unsigned half word\n        - \\token{uint32_t}: unsigned word\n        - \\token{uint64_t}: unsigned double word\n        - \\token{int8_t}: signed byte\n        - \\token{int16_t}: signed half word\n        - \\token{int32_t}: signed world\n        - \\token{int64_t}: signed double word\n        - \\token{uint8_t *}: pointer to unsigned byte\n        - \\token{uint16_t *}: pointer to unsigned half word\n        - \\token{uint32_t *}: pointer to unsigned word\n        - \\token{uint64_t *}: pointer to unsigned double word\n        - \\token{int8_t *}: pointer to signed byte\n        - \\token{int16_t *}: pointer to signed half word\n        - \\token{int32_t *}: pointer to signed world\n        - \\token{int64_t *}: pointer to signed double word\n    <td>dataTypeType </td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>modifiedWriteValues</td>\n    <td>Element to describe the manipulation of data written to a register. If not specified,\n            the value written to the field is the value stored in the field. The other options define bitwise operations:\n            \\li \\token{oneToClear}: write data bits of one shall clear (set to zero) \n            the corresponding bit in the register.\n            \\li \\token{oneToSet}: write data bits of one shall set (set to one) \n            the corresponding bit in the register.\n            \\li \\token{oneToToggle}: write data bits of one shall toggle (invert) \n            the corresponding bit in the register.\n            \\li \\token{zeroToClear}: write data bits of zero shall clear (set to zero)\n            the corresponding bit in the register.\n            \\li \\token{zeroToSet}: write data bits of zero shall set (set to one) \n            the corresponding bit in the register.\n            \\li \\token{zeroToToggle}: write data bits of zero shall toggle (invert) \n            the corresponding bit in the register.\n            \\li \\token{clear}: after a write operation all bits in the field are cleared (set to zero).\n            \\li \\token{set}: after a write operation all bits in the field are set (set to one).\n            \\li \\token{modify}: after a write operation all bit in the field may be modified (default). </td>\n    <td>modifiedWriteValuesType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>\\refelem{writeConstraint}</td>\n    <td>Three mutually exclusive options exist to set write-constraints.</td>\n    <td>writeConstraintType</td>\n    <td>0..1</td>\n  </tr>    \n  <tr>\n    <td>readAction </td>\n    <td>If set, it specifies the side effect following a read operation. If not set, the register is not modified. The defined side effects are:\n        \\li \\token{clear}: The register is cleared (set to zero) following a read operation.\n        \\li \\token{set}: The register is set (set to ones) following a read operation.\n        \\li \\token{modify}: The register is modified in some way after a read operation.\n        \\li \\token{modifyExternal}: One or more dependent resources other than the current register \n             are immediately affected by a read operation (it is recommended that the register description specifies these dependencies).\n\n        Debuggers are not expected to read this register location unless explicitly instructed by the user.</td>\n    <td>readActionType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>\\refelem{fields}</td>\n    <td>In case a register is subdivided into bit fields, it should be reflected in the SVD description file to create \n        bit-access macros and bit-field structures in the header file.</td>\n    <td>fieldsType</td>\n    <td>0..1 </td>\n  </tr>\n</table>\n\n\\delim_sec\n\n\\section elem_writeConstraint /device/peripherals/peripheral/registers/.../register/.../writeConstraint element\n\nDefine constraints for writing values to a field. You can choose between three options, which are mutualy exclusive.\n\n\\b Example:\n\\code\n<register>\n  ...\n  <writeConstraint>\n    <useEnumeratedValues>true</useEnumeratedValues>\n  </writeConstraint>\n  ...\n  <field>\n    <name>F_ONE</name>\n    ...\n    <writeConstraint>\n      <range>\n        <minimum>2</minimum>\n        <maximum>4</maximum>\n      </range>\n    </writeConstraint>\n    ...\n  <field>\n  <field>\n    <name>F_TWO</name>\n    ...\n    <writeConstraint>\n      <writeAsRead>true</writeAsRead>\n    </writeConstraint>\n    ...\n  <field>\n  <field>\n    <name>F_N</name>\n    ...\n  <field>\n  ... \n<register>  \n\\endcode\n\nThe example shows write constraints defined on different levels. The write constrains on \\tagem{register} level are propagated as default\nto all subsequent fields, especially to field \\b F_N. Field \\b F_ONE overwrites the default and sets the write range between \\token{2..4}.\nOther values cannot be written to this field. Field \\b F_TWO overwrites the default and allows to write only the last read value.\n\n\\anchor elem_writeConstraint_sc\n<b>/device/peripherals/peripheral/registers/.../register/.../writeConstraint</b>\n<table class=\"cmtable\" summary=\"Write Constraints table\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\refelem{register}</td>\n    <td colspan=\"3\">\\ref elem_register</td>\n  </tr>\n  <tr>\n    <td>\\refelem{field}</td>\n    <td colspan=\"3\">\\ref elem_field</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr class=\"choice\">\n    <td>writeAsRead</td>\n    <td>If \\token{true}, only the last read value can be written.</td>\n    <td>xs:boolean</td>\n    <td>0..1</td>\n  </tr>    \n  <tr class=\"choice\">\n    <td>useEnumeratedValues</td>\n    <td>If \\token{true}, only the values listed in the \\refelem{enumeratedValues} list can be written.\n    <td>xs:boolean</td>\n    <td>0..1</td>\n  </tr>    \n  <tr class=\"choice\">\n    <td>range</td>\n    <td>Contains the following two elements:</td>\n    <td>&nbsp;</td>\n    <td>0..1</td>\n  </tr>    \n  <tr class=\"choice\">\n    <td align=\"right\">minimum</td>\n    <td>Specify the smallest number to be written to the field.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>1..1</td>\n  </tr>    \n  <tr class=\"choice\">\n    <td align=\"right\">maximum</td>\n    <td>Specify the largest number to be written to the field.</td>\n    <td>scaledNonNegativeInteger</td>\n     <td>1..1</td>\n  </tr>    \n</table>\n\n\\delim_sec\n\n\\section elem_fields /device/peripherals/peripheral/registers/.../register/fields element\n\nGrouping element to define bit-field properties of a register.\n\n\\b Example:\n\\code\n...\n<fields>\n  ...\n  <field>\n    <name>TimerCtrl0_IntSel</name>\n    <description>Select interrupt line that is triggered by timer overflow.</description>\n    <bitOffset>1</bitOffset>\n    <bitWidth>3</bitWidth>\n    <access>read-write</access>\n    <modifiedWriteValues>oneToSet</modifiedWriteValues>\n    <writeConstraint>\n      <range>\n        <minimum>0</minimum>\n        <maximum>5</maximum>\n      </range>\n    </writeConstraint>\n    <readAction>clear</readAction>\n  <field>\n  ...\n  <field>\n    <name>BIT1</name> \n    <description>test</description>\n    <bitRange>[7:0]</bitRange> \n    <access>read-write</access>\n  </field>\n  ... \n</fields>\n...\n\\endcode\n\nThe example creates two bit-files \\b TimerCtrl0_IntSel and \\b BIT1. The bit-field \\b TimerCtrl0_IntSel has an bit offset of \\token{1} and a depth\nof \\token{3} bits, with unrestricted read and write access, a reset value of \\token{0} and a write constraint of \\token{oneToSet}, which means that only the written bit is changed. The value allowed to be written to the field range between \\token{0-5}. After a read operation, all bits are set to \\token{zero}.\n\nThe bit-field \\b BIT1, described as a test field, has the size of \\token{8} bits and can be unlimited read and written.\n\n\\anchor elem_fields_sc \n<b>/device/peripherals/peripheral/registers/.../register/fields</b>\n<table class=\"cmtable\" summary=\"Fields Level Schema\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\refelem{register}</td>\n    <td colspan=\"3\">\\ref elem_register</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\refelem{field}</td>\n    <td>Define the bit-field properties of a register.</td>\n    <td>fieldType </td>\n    <td>1..* </td>\n  </tr>\n</table>\n\n\\delim_sec\n\n\\section elem_field /device/peripherals/peripheral/registers/.../fields/field element\n\nAll fields of a register are enclosed between the \\tagem{fields} opening and closing tags.\n\t\nA bit-field has a name that is unique within the register. The \nposition and size within the register can be decsribed in two ways: \n - by the combination of the least significant bit's position (lsb) and the most significant bit's position (msb), or \n - the lsb and the bit-width of the field. \n\nA field may define an \\em enumeratedValue in order to make the display more intuitive to read. \n\n\n\\anchor elem_field_sc \n<b>/device/peripherals/peripheral/registers/.../fields/field</b>\n<table class=\"cmtable\" summary=\"Field Level Schema\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\refelem{fields}</td>\n    <td colspan=\"3\">\\ref elem_fields</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>derivedFrom</td>\n    <td>Specify the field name from which to inherit data.\n        Elements specified subsequently override inherited values. \n        <br><b>Usage:</b>\n        - Always use the full qualifying path, which must start with the peripheral \\tagem{name}, when deriving from another scope. \n          (for example, in periperhal \\token{A} and \\token{registerX}, derive from \\token{peripheralA.registerYY.fieldYY}. \n        - You can use the field \\tagem{name} only when both fields are in the same scope.\n        - No relative paths will work.\n        <br><b>Remarks:</b> When deriving, it is mandatory to specify at least \n        the \\tagem{name} and \\tagem{description}.</td>\n    <td>xs:Name</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr class=\"group1\">\n    <td>&nbsp;</td>\n    <td colspan=\"3\">Refer to \\ref dimElementGroup_gr for details.</td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dim</td>\n    <td>Defines the number of elements in a list.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimIncrement</td>\n    <td>Specify the address increment, in \\token{bits}, between two neighboring list members in the address map.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>1..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimIndex</td>\n    <td>Specify the strings that substitue the placeholder <em>%%s</em> within  \\tagem{name} and \\tagem{displayName}.</td>\n    <td>dimIndexType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>dimName</td>\n    <td>Specify the name of the C-type structure. If not defined, then the entry in the \\tagem{name} element is used.</td>\n    <td>identifierType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr class=\"group1\">\n    <td>\\refelem{dimArrayIndex}</td>\n    <td>Grouping element to create enumerations in the header file.</td>\n    <td>dimArrayIndexType</td>\n    <td>0..1 </td>\n  </tr>\n    <tr>\n        <td>name</td>\n        <td>Name string used to identify the field. Field names must be unique within a register.</td>\n        <td>dimableIdentifierType</td>\n        <td>1..1 </td>\n    </tr>\n    <tr>\n        <td>description</td>\n        <td>String describing the details of the register.</td>\n        <td>stringType</td>\n        <td>0..1 </td>\n    </tr>\n    <tr  class=\"choice\">\n        <td><em>Choice of</em></td>\n        <td colspan=\"2\">Three mutually exclusive options exist to describe the bit-range:</td>\n        <td>1..1</td>\n    </tr>\n    <tr  class=\"choice\">\n        <td colspan=\"4\"><em>1. bitRangeLsbMsbStyle</em> </td>\n    </tr>\n    <tr  class=\"choice\">\n        <td align=\"right\">bitOffset</td>\n        <td>Value defining the position of the least significant bit of the field within the register.</td>\n        <td>scaledNonNegativeInteger</td>\n        <td>1..1 </td>\n    </tr>\n    <tr  class=\"choice\">\n        <td align=\"right\">bitWidth </td>\n        <td>Value defining the bit-width of the bitfield within the register. </td>\n        <td>scaledNonNegativeInteger</td>\n        <td>0..1 </td>\n    </tr>\n    <tr  class=\"choice\">\n        <td colspan=\"4\"><em>2. bitRangeOffsetWidthStyle</em></td>\n    </tr>\n    <tr  class=\"choice\">\n        <td align=\"right\">lsb </td>\n        <td>Value defining the bit position of the least significant bit within the register.</td>\n        <td>scaledNonNegativeInteger</td>\n        <td>1..1 </td>\n    </tr>\n    <tr  class=\"choice\">\n        <td align=\"right\">msb </td>\n        <td>Value defining the bit position of the most significant bit within the register. </td>\n        <td>scaledNonNegativeInteger</td>\n        <td>1..1</td>\n    </tr>\n    <tr class=\"choice\" >\n        <td colspan=\"4\"><em>3. bitRangePattern</em></td>\n    </tr>\n    <tr  class=\"choice\">\n        <td align=\"right\">bitRange </td>\n        <td>A string in the format: \"[<msb>:<lsb>]\"</td>\n        <td>bitRangeType </td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>\\ref elem_access \"access\"</td>\n        <td>Predefined strings set the access type. The element can be omitted if access rights get inherited from parent elements.</td>\n        <td>accessType</td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>modifiedWriteValues</td>\n        <td>Describe the manipulation of data written to a field. If not specified, the value \n        written to the field is the value stored in the field. The other options are bitwise operations:\n  \\li \\token{oneToClear}: write data bit of one shall clear (set to zero) the corresponding bit in the field.\n  \\li \\token{oneToSet}: write data bit of one shall set (set to one) the corresponding bit in the field.\n  \\li \\token{oneToToggle}: write data bit of one shall toggle (invert) the corresponding bit in the field.\n  \\li \\token{zeroToClear}: write data bit of zero shall clear (set to zero) the corresponding bit in the field.\n  \\li \\token{zeroToSet}: write data bit of zero shall set (set to one) the corresponding bit in the field.\n  \\li \\token{zeroToToggle}: write data bit of zero shall toggle (invert) the corresponding bit in the field.\n  \\li \\token{clear}: after a write operation all bits in the field are cleared (set to zero).\n  \\li \\token{set}: after a write operation all bits in the field are set (set to one).\n  \\li \\token{modify}: after a write operation all bit in the field may be modified (default). </td>\n        <td>modifiedWriteValuesType</td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>\\refelem{writeConstraint}</td>\n        <td>Three mutually exclusive options exist to set write-constraints.</td>\n        <td>writeConstraintType</td>\n        <td>0..1</td>\n    </tr>    \n    <tr>\n        <td>readAction</td>\n        <td>If set, it specifies the side effect following a read operation. If not set, the field \n        is not modified after a read. The defined side effects are:\n  \\li \\token{clear}: The field is cleared (set to zero) following a read operation.\n  \\li \\token{set}: The field is set (set to ones) following a read operation.\n  \\li \\token{modify}: The field is modified in some way after a read operation.\n  \\li \\token{modifyExternal}: One or more dependent resources \n  other than the current field are immediately affected by a read operation (it is recommended that the field \n  description specifies these dependencies). \n\n  Debuggers are not expected to read this field location unless explicitly instructed by the user.</td>\n        <td>readActionType</td>\n        <td>0..1 </td>register\n    </tr>\n    <tr>\n        <td>\\refelem{enumeratedValues}</td>\n        <td>Next lower level of description.</td>\n        <td>enumerationType</td>\n    <td>0..2</td>\n    </tr>\n</table>\n\n\\delim_sec\n\n\\section elem_enumeratedValues /device/peripherals/peripheral/registers/.../field/enumeratedValues element\n\nThe concept of enumerated values creates a map between unsigned integers and an identifier string.\nIn addition, a description string can be associated with each entry in the map.\n\n<pre>\n  0 <-> disabled -> \"The clock source clk0 is turned off.\"\n  1 <-> enabled  -> \"The clock source clk1 is running.\"\n  2 <-> reserved -> \"Reserved values. Do not use.\"\n  3 <-> reserved -> \"Reserved values. Do not use.\"\n</pre>\n\nThis information generates an <em>enum</em> in the device header file. The debugger may use \nthis information to display the identifier string as well as the description. Just like symbolic constants\nmaking source code more readable, the system view in the debugger becomes more instructive. The detailed description \ncan provide reference manual level details within the debugger.\n\n\\b Example:\n\n\\code\n<enumeratedValues>\n\n    <name>TimerIntSelect</name>\n    <usage>read-write</usage>\n\n    <enumeratedValue>\n        <name>disabled</name>\n        <description>The clock source clk0 is turned off.</description>\n        <value>0</value>\n    </enumeratedValue>\n\n    <enumeratedValue>\n        <name>enabled</name>\n        <description>The clock source clk1 is running.</description>\n        <value>1</value>\n    </enumeratedValue>\n\n    <enumeratedValue>\n        <name>reserved</name>\n        <description>Reserved values. Do not use.</description>\n        <isDefault>true</isDefault>\n    </enumeratedValue>\n\n</enumeratedValues>\n\\endcode\n\n\n\\anchor elem_enumeratedValues_sc\n<b>/device/peripherals/peripheral/registers/.../field/enumeratedValues</b>\n<table class=\"cmtable\" summary=\"Enumerated Values Level Schema\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\refelem{field}</td>\n    <td colspan=\"3\">\\ref elem_field</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>derivedFrom</td>\n    <td>Makes a copy from a previously defined \\em enumeratedValues section. \n        No modifications are allowed. An \\em enumeratedValues entry is referenced by its name. \n        If the name is not unique throughout the description, it needs to be further qualified \n        by specifying the associated field, register, and peripheral as required. For example:\n<pre>\n    field:                           clk.dis_en_enum\n    register + field:                ctrl.clk.dis_en_enum\n    peripheral + register + field:   timer0.ctrl.clk.dis_en_enum\n</pre>\n    </td>\n    <td>xs:Name</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>Identifier for the whole enumeration section.</td>\n    <td>xs:Name</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>headerEnumName</td>\n    <td>Identifier for the enumeration section. Overwrites the hierarchical enumeration type in the device header file. \n        User is responsible for uniqueness across description.</td>\n    <td>identifierType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>usage</td>\n    <td>Possible values are \\token{read<em>,</em> write<em>, or</em> read-write}. \n        This allows specifying two different enumerated values depending whether it is to be used \n        for a read or a write access. If not specified, the default value \\token{read-write} is used.</td>\n    <td>enumUsageType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>\\refelem{enumeratedValue}</td>\n    <td>Describes a single entry in the enumeration. The number of required items depends on the \n        bit-width of the associated field.</td>\n    <td>enumeratedValueType</td>\n    <td>1..*</td>\n  </tr>\n</table>\n\n\\delim_sec\n\n\\section elem_enumeratedValue /device/peripherals/peripheral/registers/.../enumeratedValue element\n\nAn \\em enumeratedValue defines a map between an unsigned integer and a string.\n\n\\anchor elem_enumeratedValue_sc\n<b>/device/peripherals/peripheral/registers/.../enumeratedValue</b>\n<table class=\"cmtable\" summary=\"Enumerated Value\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\refelem{enumeratedValues}</td>\n    <td colspan=\"3\">\\ref elem_enumeratedValues</td>\n  </tr>\n  <tr>\n    <td>\\refelem{dimArrayIndex}</td>\n    <td colspan=\"3\">\\ref elem_dimArrayIndex</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>String describing the semantics of the value. Can be displayed instead of the value.</td>\n    <td>identifierType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>description</td>\n    <td>Extended string describing the value.</td>\n    <td>xs:string</td>\n    <td>0..1</td>\n  </tr>\n  <tr class=\"choice\">\n    <td colspan=\"3\"><em>choice of</em></td>\n     <td>1..1</td>\n  </tr>\n  <tr class=\"choice\">\n    <td align=\"right\">value</td>\n    <td>Defines the constant for the bit-field as decimal, hexadecimal (0x...) or binary (0b... or #...) number. E.g.:\n<pre>\n      \\<value>15\\</value>\n      \\<value>0xf\\</value>\n      \\<value>0b1111\\</value>\n      \\<value>#1111\\</value>\n</pre>\n    In addition the binary format supports <em>'do not care'</em> bits represented by <b>\\token{x}</b>.\n    E.g. specifying value 14 and 15 as:\n    <pre>\n      \\<value>0b111x\\</value>\n      \\<value>#111x\\</value>\n    </pre>  \n    </td>\n    <td style=\"white-space:nowrap\">scaledNonNegativeInteger</td>\n    <td>0..1</td>\n  </tr>\n  <tr class=\"choice\">\n    <td align=\"right\">isDefault</td>\n    <td>Defines the name and description for all other values that are not listed explicitly.</td>\n    <td>xs:boolean</td>\n    <td>0..1</td>\n  </tr>\n</table>\n*/\n\n/**\n\\page elem_special Special Elements\n\nThis section describes elements that occur on various levels and specifies the general rules.\nSpecific requirements are mentioned in the place where these elements occur.\n\n - \\ref dimElementGroup_gr \"dimElementGroup\"  - Elements that can be used to define arrays and lists in the code.\n - \\ref registerPropertiesGroup_gr \"registerPropertiesGroup\" - Register properties. Higher level definitions use as default values for lower level descriptions.\n\n\\delim_sec\n\n\\section dimElementGroup_gr dimElementGroup\n\nThe elements below appear on various levels and can be used to define arrays and lists in the code. \nSingle descriptions get duplicated automatically into an array or a list. \nThe subsequent is true for all elements of type \\em dimableIdentifierType.\n\n - To create arrays, use the placeholder <em>[%%s]</em> at the end of a \\tagem{name} and \\tagem{displayName}.\n   <span style=\"color:red\">Do not define \\tagem{dimIndex} in this case!</span>\n - To create lists, use the placeholder <em>%%s</em> anywhere within or at the end of a \\tagem{name} and \\tagem{displayName}.\n\n\\note\nSome of the \\tagem{name} and \\tagem{displayName} elements can use both placeholders (<em>[%%s]</em>, <em>%%s</em>), others just one. \nRefer to \\refelem{peripheral}, \\refelem{register}, \\refelem{cluster}, and \\refelem{field} for details.\n\n\n<table class=\"cmtable\" summary=\"dimElementGroup Description\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\refelem{peripheral}</td>\n    <td colspan=\"3\">\\ref elem_peripheral </td>\n  </tr>\n  <tr>\n    <td>\\refelem{register}</td>\n    <td colspan=\"3\">\\ref elem_register </td>\n  </tr>\n  <tr>\n    <td>\\refelem{cluster}</td>\n    <td colspan=\"3\">\\ref elem_cluster </td>\n  </tr>\n  <tr>\n    <td>\\refelem{field}</td>\n    <td colspan=\"3\">\\ref elem_field</td>\n  </tr>\n  <tr>\n    <th style=\"white-space:nowrap\">Grouped Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>dim</td>\n    <td>Defines the number of elements in an array or list.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>dimIncrement</td>\n    <td>Specify the address increment between two neighboring array or list members in the address map.</td>\n    <td>scaledNonNegativeInteger</td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>dimIndex</td>\n    <td>Specify the strings that substitue the placeholder <em>%%s</em> within  \\tagem{name} and \\tagem{displayName}.\n        By default, \\tagem{dimIndex} is a value starting with \\token{0}.\n        \\n\\b Remark: Do not define \\tagem{dimIndex} when using the placeholder <em>[%%s]</em> in \\tagem{name} or \\tagem{displayName}.</td>\n    <td>dimIndexType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>dimName</td>\n    <td>Specify the name of the C-type structure. If not defined, then the entry in the \\tagem{name} element is used.</td>\n    <td>identifierType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>\\refelem{dimArrayIndex}</td>\n    <td>Grouping element to create enumerations in the header file.</td>\n    <td>dimArrayIndexType</td>\n    <td>0..1 </td>\n  </tr>\n</table>\n  \n\\b Example:\nThe examples creates definitions for registers.\n\n\\code{.xml}\n...\n<register>\n    <dim>6</dim> \n    <dimIncrement>4</dimIncrement> \n    <dimIndex>A,B,C,D,E,Z</dimIndex> \n    <name>GPIO_%s_CTRL</name> \n...\n</register>\n\\endcode\n\nThe code above generates the list:\n=> GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, GPIO_Z_CTRL\n\n\n\\code{.xml}\n...\n<register>\n    <dim>4</dim> \n    <dimIncrement>4</dimIncrement> \n    <dimIndex>3-6</dimIndex> \n    <name>IRQ%s</name> \n...\n</register>\n\\endcode\n\nThe example above generates the list: => IRQ3, IRQ4, IRQ5, IRQ6\n\n\n\\code{.xml}\n...\n<register>\n    <dim>4</dim> \n    <dimIncrement>4</dimIncrement> \n    <name>MyArr[%s]</name> \n...\n</register>\n\\endcode\n\nThe example above generates the array: => MyArr[4]\n\n\\delim_sec\n\n\\subsection elem_dimArrayIndex /device/peripherals/peripheral/.../dimArrayIndex element\n\nThis information is used for generating an <em>enum</em> in the device header file. The debugger may use \nthis information to display the identifier string as well as the description. Just like symbolic constants\nmaking source code more readable, the system view in the debugger becomes more instructive.\n\n\\b Example:\n\\code\n...\n<dimArrayIndex>\n  <headerEnumName>FSMC_EnumArray</headerEnumName>\n  <enumeratedValue>\n    <name>UART0</name>\n    <description>UART0 Peripheral</description>\n    <value>0</value>\n  </enumeratedValue>\n  <enumeratedValue>\n    <name>TIMER0</name>\n    <description>TIMER0 Peripheral</description>\n    <value>1</value>\n  </enumeratedValue>\n</dimArrayIndex>\n...\n\\endcode\n\n\\anchor elem_dimArrayIndex_sc\n<b>/device/peripherals/peripheral/.../dimArrayIndex</b>\n<table class=\"cmtable\" summary=\"dimArrayIndex Table\">\n  <tr>\n    <th style=\"white-space:nowrap\">Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\refelem{peripheral}</td>\n    <td colspan=\"3\">\\ref elem_peripheral </td>\n  </tr>\n  <tr>\n    <td>\\refelem{register}</td>\n    <td colspan=\"3\">\\ref elem_register </td>\n  </tr>\n  <tr>\n    <td>\\refelem{cluster}</td>\n    <td colspan=\"3\">\\ref elem_cluster </td>\n  </tr>\n  <tr>\n    <th style=\"white-space:nowrap\">Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>headerEnumName</td>\n    <td>Specify the base name of enumerations.  Overwrites the hierarchical enumeration type in the device header file. \n        User is responsible for uniqueness across description.\n        The headerfile generator uses the name of a peripheral or cluster as the base name for enumeration types. \n        If \\tagem{headerEnumName} element is specfied, then this string is used.\n\n</td>\n    <td>identifierType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>\\refelem{enumeratedValue}</td>\n    <td>Specify the values contained in the enumeration.</td>\n    <td>enumeratedValueType</td>\n    <td>1..* </td>\n  </tr>\n</table>\n\n\\delim_sec \n\n\\section registerPropertiesGroup_gr registerPropertiesGroup\n\nThe following elements are available on various levels. \nElement values defined on a lower level overwrite element values defined on a more general level.\nFor example, \\tagem{register}.\\tagem{size} overwrites \\tagem{peripheral}.\\tagem{size}.\nElements not defined on a more general level, must be defined at \\tagem{register} level at the latest.\n\nSpecial requirements are described on the level where the element occurs. Click on the parent element in the table below for details.\n\n\\b Example:\n\\code\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\">\n  <name>ARM_Cortex_M3</name>\n  <version>0.1</version>\n  <description>Arm Cortex-M3 based Microcontroller demonstration device</description>\n  <addressUnitBits>8</addressUnitBits>\n  <width>32</width>\n  <size>32</size>\n  <access>read-write</access>\n  <protection>s</protection>\n  ...\n  <peripherals>\n    ...\n  </peripherals>\n</device>\n\\endcode\n\nDefault settings have been defined for \\tagem{width}, \\tagem{size}, \\tagem{access}, and \\tagem{protection} on device level. \nThese settings can be refined on subsequent levels.\n\n\\anchor elem_register_sc\n<b>Register Properties</b>\n<table class=\"cmtable\" summary=\"Register Properties Group Elements\">\n    <tr>\n        <th style=\"white-space:nowrap\">Parent Element</th>\n        <th colspan=\"3\">Element Chain</th>\n    </tr>\n    <tr>\n        <td>\\refelem{device}</td>\n        <td colspan=\"3\">\\ref elem_device </td>\n    </tr>\n    <tr>\n        <td>\\refelem{peripheral}</td>\n        <td colspan=\"3\">\\ref elem_peripheral </td>\n    </tr>\n    <tr>\n        <td>\\refelem{register}</td>\n        <td colspan=\"3\">\\ref elem_register </td>\n    </tr>\n    <tr>\n        <td>\\refelem{cluster}</td>\n        <td colspan=\"3\">\\ref elem_cluster </td>\n    </tr>\n    <tr>\n        <th>&nbsp;</th>\n        <th colspan=\"3\">\\token{Below: Parent elements that have a reference to a single element of this block}</th>\n    </tr>\n    <tr>\n        <td>\\refelem{field}</td>\n        <td colspan=\"3\">\\ref elem_field  (only for element \\tagem{access})</td>\n    </tr>\n    <tr>\n        <td>\\refelem{sauRegionsConfig}</td>\n        <td colspan=\"3\">\\ref elem_sauRegionsConfig (element \\tagem{protection} for attribute \\tagem{protectionWhenDisabled})</td>\n    </tr>\n    <tr>\n        <td>\\refelem{addressBlock}</td>\n        <td colspan=\"3\">\\ref elem_addressBlock  (only for element \\tagem{protection})</td>\n    </tr>\n    <tr>\n        <th style=\"white-space:nowrap\">Elements</th>\n        <th>Description</th>\n        <th>Type</th>\n        <th>Occurrence</th>\n    </tr>\n    <tr>\n        <td>size</td>\n        <td>Define the default bit-width of any device register (implicit inheritance). \n        The value can be redefined on any lower level using the \\tagem{size} element there.\n        </td>\n        <td>scaledNonNegativeInteger </td>\n        <td>0..1 </td>\n    </tr> \n    <tr>\n        <td>\\anchor elem_access access</td>\n        <td>Define access rights. Access rights can be redefined at any lower level. Use one of the following predefined values:\n        - \\token{read-only}:  Read access is permitted. Write operations have an undefined result.\n        - \\token{write-only}: Read operations have an undefined result. Write access is permitted. \n        - \\token{read-write}: Read and write accesses are permitted. Writes affect the state of the register \n                              and reads return the register value.\n        - \\token{writeOnce}:  Read operations have an undefined results. Only the first write after reset has an effect. \n        - \\token{read-writeOnce}: Read access is always permitted. Only the first write access after a reset \n                                  will have an effect on the content. Other write operations have an undefined result.\n        </td>\n        <td>accessType</td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n      <td>\\anchor elem_protection protection</td>\n      <td>Specify the security privilege to access an address region. This information is relevant for the\n            programmer as well as the debugger when no universal access permissions have been granted.\n            If no specific information is provided, an address region is accessible in any mode.  \n            The following values can be used to protect accesses by the programmer or debugger:\n           - \\token{\"s\"} - secure permission required for access\n           - \\token{\"n\"} - non-secure or secure permission required for access\n           - \\token{\"p\"} - privileged permission required for access</td>\n      </td>\n      <td>protectionStringType</td>\n      <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>resetValue </td>\n        <td>Define the default value for all registers at RESET.\n            The value can be redefined on any lower level using the \\tagem{resetValue}\n            element there. The actual reset value is calculated from the \\tagem{resetValue} and the \n            \\tagem{resetMask}. The mask is used to specify bits with an undefined reset value.</td>\n        <td>scaledNonNegativeInteger </td>\n        <td>0..1 </td>\n    </tr>\n    <tr>\n        <td>resetMask</td>\n        <td>Identify register bits that have a defined reset value. These bit positions are set to \\token{1}.\n            Bit positions with an undefined reset value are set to \\token{0}.</td>\n        <td>scaledNonNegativeInteger</td>\n        <td>0..1 </td>\n    </tr>\n</table>\n*/\n\n/* ************************************************************************************************ */\n/**\n\\page schema_1_2_gr CMSIS-SVD Schema File\n\\verbinclude \"CMSIS-SVD.xsd\"\n\n*/\n"
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If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = NO\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = YES\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = YES\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = YES\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = YES\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = NO\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = YES\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = YES\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = YES\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = \n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = NO\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = NO\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         = \n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = \"./src\"\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          = *.xsd \\\n                         *.xml \\\n                         *.txt \\\n                         *.svd\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = YES\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = NO\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       = \n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        = \n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = . \\\n                         ../../Utilities/\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = ./src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           = \n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        = \n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS = \n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE = \n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = YES\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = YES\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = YES\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = NO\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        = \n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../../Utilities/CMSIS-SVD.xsd \\\n                         ../Doxygen_Templates/printComponentTabs.js\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 100\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = YES\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = \n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     = \n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               = \n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   = \n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  = \n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  = \n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           = \n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     = \n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       = \n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       = \n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     = \n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         = \n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           = \n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           = \n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      = \n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    = \n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             = \n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                = \n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen\n# Definitions (see http://autogen.sf.net) file that captures the structure of\n# the code including all documentation. Note that this feature is still\n# experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES doxygen will generate a Perl module\n# file that captures the structure of the code including all documentation.\n#\n# Note that this feature is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES doxygen will generate the necessary\n# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI\n# output from the Perl module output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be nicely\n# formatted so it can be parsed by a human reader. This is useful if you want to\n# understand what is going on. On the other hand, if this tag is set to NO the\n# size of the Perl module output will be much smaller and Perl will parse it\n# just the same.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_PRETTY         = YES\n\n# The names of the make variables in the generated doxyrules.make file are\n# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful\n# so different doxyrules.make files included by the same Makefile don't\n# overwrite each other's variables.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_MAKEVAR_PREFIX = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the preprocessor\n#---------------------------------------------------------------------------\n\n# If the ENABLE_PREPROCESSING tag is set to YES doxygen will evaluate all\n# C-preprocessor directives found in the sources and include files.\n# The default value is: YES.\n\nENABLE_PREPROCESSING   = YES\n\n# If the MACRO_EXPANSION tag is set to YES doxygen will expand all macro names\n# in the source code. If set to NO only conditional compilation will be\n# performed. Macro expansion can be done in a controlled way by setting\n# EXPAND_ONLY_PREDEF to YES.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nMACRO_EXPANSION        = NO\n\n# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then\n# the macro expansion is limited to the macros specified with the PREDEFINED and\n# EXPAND_AS_DEFINED tags.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_ONLY_PREDEF     = NO\n\n# If the SEARCH_INCLUDES tag is set to YES the includes files in the\n# INCLUDE_PATH will be searched if a #include is found.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSEARCH_INCLUDES        = YES\n\n# The INCLUDE_PATH tag can be used to specify one or more directories that\n# contain include files that are not input files but should be processed by the\n# preprocessor.\n# This tag requires that the tag SEARCH_INCLUDES is set to YES.\n\nINCLUDE_PATH           = src\n\n# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard\n# patterns (like *.h and *.hpp) to filter out the header-files in the\n# directories. If left blank, the patterns specified with FILE_PATTERNS will be\n# used.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nINCLUDE_FILE_PATTERNS  = *.xsd\n\n# The PREDEFINED tag can be used to specify one or more macro names that are\n# defined before the preprocessor is started (similar to the -D option of e.g.\n# gcc). The argument of the tag is a list of macros of the form: name or\n# name=definition (no spaces). If the definition and the \"=\" are omitted, \"=1\"\n# is assumed. To prevent a macro definition from being undefined via #undef or\n# recursively expanded use the := operator instead of the = operator.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nPREDEFINED             = \n\n# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this\n# tag can be used to specify a list of macro names that should be expanded. The\n# macro definition that is found in the sources will be used. Use the PREDEFINED\n# tag if you want to use a different macro definition that overrules the\n# definition found in the source code.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_AS_DEFINED      = \n\n# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will\n# remove all refrences to function-like macros that are alone on a line, have an\n# all uppercase name, and do not end with a semicolon. Such function macros are\n# typically used for boiler-plate code, and will confuse the parser if not\n# removed.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSKIP_FUNCTION_MACROS   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to external references\n#---------------------------------------------------------------------------\n\n# The TAGFILES tag can be used to specify one or more tag files. For each tag\n# file the location of the external documentation should be added. The format of\n# a tag file without this location is as follows:\n# TAGFILES = file1 file2 ...\n# Adding location for the tag files is done as follows:\n# TAGFILES = file1=loc1 \"file2 = loc2\" ...\n# where loc1 and loc2 can be relative or absolute paths or URLs. See the\n# section \"Linking to external documentation\" for more information about the use\n# of tag files.\n# Note: Each tag file must have an unique name (where the name does NOT include\n# the path). If a tag file is not located in the directory in which doxygen is\n# run, you must also specify the path to the tagfile here.\n\nTAGFILES               = \n\n# When a file name is specified after GENERATE_TAGFILE, doxygen will create a\n# tag file that is based on the input files it reads. See section \"Linking to\n# external documentation\" for more information about the usage of tag files.\n\nGENERATE_TAGFILE       = \n\n# If the ALLEXTERNALS tag is set to YES all external class will be listed in the\n# class index. If set to NO only the inherited external classes will be listed.\n# The default value is: NO.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in\n# the modules index. If set to NO, only the current project's groups will be\n# listed.\n# The default value is: YES.\n\nEXTERNAL_GROUPS        = YES\n\n# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in\n# the related pages index. If set to NO, only the current project's pages will\n# be listed.\n# The default value is: YES.\n\nEXTERNAL_PAGES         = YES\n\n# The PERL_PATH should be the absolute path and name of the perl script\n# interpreter (i.e. the result of 'which perl').\n# The default file (with absolute path) is: /usr/bin/perl.\n\nPERL_PATH              = /usr/bin/perl\n\n#---------------------------------------------------------------------------\n# Configuration options related to the dot tool\n#---------------------------------------------------------------------------\n\n# If the CLASS_DIAGRAMS tag is set to YES doxygen will generate a class diagram\n# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to\n# NO turns the diagrams off. Note that this option also works with HAVE_DOT\n# disabled, but it is recommended to install and use dot, since it yields more\n# powerful graphs.\n# The default value is: YES.\n\nCLASS_DIAGRAMS         = YES\n\n# You can define message sequence charts within doxygen comments using the \\msc\n# command. Doxygen will then run the mscgen tool (see:\n# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the\n# documentation. The MSCGEN_PATH tag allows you to specify the directory where\n# the mscgen tool resides. If left empty the tool is assumed to be found in the\n# default search path.\n\nMSCGEN_PATH            = \n\n# You can include diagrams made with dia in doxygen documentation. Doxygen will\n# then run dia to produce the diagram and insert it in the documentation. The\n# DIA_PATH tag allows you to specify the directory where the dia binary resides.\n# If left empty dia is assumed to be found in the default search path.\n\nDIA_PATH               = \n\n# If set to YES, the inheritance and collaboration graphs will hide inheritance\n# and usage relations if the target is undocumented or is not a class.\n# The default value is: YES.\n\nHIDE_UNDOC_RELATIONS   = YES\n\n# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is\n# available from the path. This tool is part of Graphviz (see:\n# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent\n# Bell Labs. The other options in this section have no effect if this option is\n# set to NO\n# The default value is: NO.\n\nHAVE_DOT               = NO\n\n# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed\n# to run in parallel. When set to 0 doxygen will base this on the number of\n# processors available in the system. You can set it explicitly to a value\n# larger than 0 to get control over the balance between CPU load and processing\n# speed.\n# Minimum value: 0, maximum value: 32, default value: 0.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_NUM_THREADS        = 0\n\n# When you want a differently looking font n the dot files that doxygen\n# generates you can specify the font name using DOT_FONTNAME. You need to make\n# sure dot is able to find the font, which can be done by putting it in a\n# standard location or by setting the DOTFONTPATH environment variable or by\n# setting DOT_FONTPATH to the directory containing the font.\n# The default value is: Helvetica.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTNAME           = Helvetica\n\n# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of\n# dot graphs.\n# Minimum value: 4, maximum value: 24, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTSIZE           = 10\n\n# By default doxygen will tell dot to use the default font as specified with\n# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set\n# the path where dot can find it using this tag.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTPATH           = \n\n# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for\n# each documented class showing the direct and indirect inheritance relations.\n# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCLASS_GRAPH            = YES\n\n# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a\n# graph for each documented class showing the direct and indirect implementation\n# dependencies (inheritance, containment, and class references variables) of the\n# class with other documented classes.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCOLLABORATION_GRAPH    = YES\n\n# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for\n# groups, showing the direct groups dependencies.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGROUP_GRAPHS           = YES\n\n# If the UML_LOOK tag is set to YES doxygen will generate inheritance and\n# collaboration diagrams in a style similar to the OMG's Unified Modeling\n# Language.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LOOK               = NO\n\n# If the UML_LOOK tag is enabled, the fields and methods are shown inside the\n# class node. If there are many fields or methods and many nodes the graph may\n# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the\n# number of items for each type to make the size more manageable. Set this to 0\n# for no limit. Note that the threshold may be exceeded by 50% before the limit\n# is enforced. So when you set the threshold to 10, up to 15 fields may appear,\n# but if the number exceeds 15, the total amount of fields shown is limited to\n# 10.\n# Minimum value: 0, maximum value: 100, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LIMIT_NUM_FIELDS   = 10\n\n# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and\n# collaboration graphs will show the relations between templates and their\n# instances.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nTEMPLATE_RELATIONS     = NO\n\n# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to\n# YES then doxygen will generate a graph for each documented file showing the\n# direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDE_GRAPH          = YES\n\n# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are\n# set to YES then doxygen will generate a graph for each documented file showing\n# the direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDED_BY_GRAPH      = YES\n\n# If the CALL_GRAPH tag is set to YES then doxygen will generate a call\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable call graphs for selected\n# functions only using the \\callgraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALL_GRAPH             = NO\n\n# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable caller graphs for selected\n# functions only using the \\callergraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALLER_GRAPH           = NO\n\n# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical\n# hierarchy of all classes instead of a textual one.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGRAPHICAL_HIERARCHY    = YES\n\n# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the\n# dependencies a directory has on other directories in a graphical way. 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Tested\n# and working are Firefox, Chrome, Safari, and Opera.\n# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make\n# the SVG files visible. Older versions of IE do not have SVG support.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINTERACTIVE_SVG        = NO\n\n# The DOT_PATH tag can be used to specify the path where the dot tool can be\n# found. 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  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Zone/src/ErrorMessages.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page ErrorMessages Error Messages \n\nThe following table explains the output messages issued by CMSIS-Zone utility.\n\nMessage                                                                                                   | Description\n:---------------------------------------------------------------------------------------------------------|:-----------------------\nError Z101: \\<name\\>: Invalid memory size                                                                 | Size of the memory region is invalid or negative\nError Z102: \\<name\\>: Memory size exceeds parent region size                                              | Size of the sub-memory region exceeds the available memory in the parent \nError Z103: \\<name\\>: Invalid memory offset                                                               | Offset of the sub-memory region is invalid or negative\nError Z104: \\<name\\>: Memory offset is outside parent boundary                                            | Offset of the sub-memory region is outside of the available memory in the parent\nError Z105: \\<name\\>: Memory exceeds parent region boundary                                               | The sub-memory region exceeds the limits of physical memory space in the parent\nError Z106: \\<name\\>: Memory region cannot be arranged: no physical slot is available                     | The memory region cannot be arranged as there is no physical memory space available\nError Z107: \\<name\\>: Memory region fully overlaps with region \\<name\\>                                   | The sub-memory region overlaps with another memory region\nError Z108: \\<name\\>: Memory region partially overlaps with region \\<name\\>                               | The sub-memory region overlaps with another memory region\nError Z110: \\<name\\>: Number of available MPU slots is exceeded                                           | There are not enough MPU regions to allocate the required resources\nError Z111: No MPU slot can be allocated according to ArmV7 requirements                                  | There are not enough MPU regions to allocate the required resources\nError Z112: \\<name\\>: Memory size is rounded up to align with ArmV7 MPU requirements                      | The Memory size of the region is increased due to MPU alignment restrictions\nError Z120: No startup memory region is specified                                                         | There is not memory region for the reset vector (startup) defined\nError Z121: Multiple startup memory regions are specified                                                 | There is more then one region for the reset vector (startup) defined\nError Z201: \\<name\\>: Memory region is missing                                                            | The memory region in the assignment *.azone file is missing in the resource *.rzone file\nError Z202: \\<name\\>: Peripheral group is missing                                                         | The peripheral group in the assignment *.azone file is missing in the resource *.rzone file\nError Z203: \\<name\\>: Peripheral is missing                                                               | The peripheral in the assignment *.azone file is missing in the resource *.rzone file\nError Z401: \\<name\\>: Device description is missing                                                       | The device specification in the resource *.rzone file is incomplete\nError Z402: \\<name\\>: Device pack is not specified                                                        | The device specification in the resource *.rzone file is incomplete\nError Z403: \\<name\\>: Device pack specification is invalid                                                | The device specification in the resource *.rzone file is incomplete \nError Z404: \\<name\\>: Resource file is missing                                                            | The resource *.rzone file referenced by the assignment *.azone file is missing\nError Z405: \\<name\\>: Error reading resource file                                                         | The resource *.rzone file has an incorrect format\nError Z406: \\<name\\>: Processor description is missing                                                    | The processor specification in the resource *.rzone file is incomplete\nError Z407: \\<name\\>: Processor description: missing or invalid DnumInterrupts attribute for TrustZone device | The processor specification in the resource *.rzone file is incomplete\nError Z408: \\<name\\>: Processor description: missing or invalid DnumSauRegions attribute for TrustZone device | The processor specification in the resource *.rzone file is incomplete\nError Z501: \\<name\\>: Creating sub-zone files failed                                                      | The sub-zone resource files cannot be created\nError Z601: \\<name\\>: creating FreeMarker model failed                                                    | The FreeMarker model *.fzone file cannot be created \nError Z602: \\<name\\>: processing template file failed                                                     | The FreeMarker model template file cannot be processed \nError Z603: \\<name\\>: processing template file failed                                                     | The FreeMarker model template file cannot be processed \nError Z604: \\<name\\>: folder contains no template files                                                   | There are no FreeMarker model template files\n\n*/"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Zone/src/GenDataModel.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page GenDataModel Generator Data Model \n\nThe <b>Generator Data Model</b> defines the resource and partition data structure for code generators.\nThis data structure is connected to a FreeMarker template engine and file templates allow to generate\nvarious files that can be used to configure development tools or hardware components.\n\n\\image html generator.png \"FreeMarker Template Engine\"\n\n\\section fp_toplevel FreeMarker top-level format\n\n\\subpage fm_system provides memory layout and TrustZone configuration of the complete system. \n\\subpage fm_zone setup information of a zone (or system partition) along with related peripherals.\n\n\\section fm_basics FreeMarker basics\n\nThe variable types relevant for CMSIS-Zone are:\n\n\\b scalar: variable that stores a single value of a scalar type\nscalar-types:\n- string\n- int\n- bool\n\n\\b hash: variable that that stores one or more variables with a unique lookup name\n\n\\b sequence: variable that stores sub-variables without names but instead are selected via index (myVariable[index])\n\nA variable is accessed using the dollar character followed by a variable or expression in brackets:\n\\code\n${...}\n\\endcode\nOutput the name of the zone:\n\\code\n${zone.name}\n\\endcode\n\nA sequence gets iterated:\n\\code\n<#list zone.memory as mem>\n   Memory region name $mem.name\n</#list>\n\\endcode\n\nPrinting a sorted list of all available memory entries by start address\n\\code\n<#list zone.memory?sort_by(\"start\") as mem>\n  ${mem.start} ${mem.name}\n</#list>\n\\endcode\n\n\n\n\\page fm_system system element\n\nThe \\ref fm_system provides the memory layout and the TrustZone configuration of the complete system. \nThis information can be used for example, to create a linker script that defines the memory setup of the SoC system.\n\n<table class=\"cmtable\" summary=\"Element: system\">\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>\\subpage fm_processor \".processor\"</td>\n    <td>A sequence of all processor elements available in the system resource file.</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_memory \".memory\"</td>\n    <td>A sequence of all memory regions available in the system resource file.</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_peripheral \".peripheral\"</td>\n    <td>A sequence of all peripherals available in the system resource file.</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_sau \".sau\"</td>\n    <td>A sequence of all SAU regions for initialization.</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_interrupt \".interrupt\"</td>\n    <td>A sequence of all interrupt sources available.</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_mpc_setup \".mpc_setup\"</td>\n    <td>Contains the device specific configuration registers for the setup of the Memory Protection Controller (MPC).</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_reg_setup \".reg_setup\"</td>\n    <td>Contains the device specific configuration registers for the setup of the peripherals.</td>\n    <td>sequence</td>\n  </tr>\n</table>\n  \n\\page fm_zone zone element\n\nThe \\ref fm_zone provides the setup information of a zone (or system partition) along with related peripherals.\nThis information can be used for example, to create the MPU setup that is required for various execution zones along with\nthe related linker setup.\n\n<table class=\"cmtable\" summary=\"Element: zone\">\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>.name</td>\n    <td>The name of the zone (or system partition).</td>\n    <td>string</td>\n  </tr>\n  <tr>\n    <td>.Pname</td>\n    <td>Name of the processor core.</td>\n    <td>RestrictedString</td>\n  </tr>\n  <tr>\n    <td>.class</td>\n    <td>Class information for execution zones.</td>\n    <td>string</td>\n  </tr>\n  <tr>\n    <td>.security</td>\n    <td>The \\ref security \"security\" setting for this zone in the following separate fields.</td>\n    <td>SecurityType</td>\n  </tr>\n  <tr>\n    <td>.security.s</td>\n    <td>Zone is executed in \\em \"secure\" state.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.security.n</td>\n    <td>Zone is executed in \\em \"non-secure\" state.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.privilege</td>\n    <td>The \\ref privilege \"privilege type\" settings for this zone in the following separate fields.</td>\n    <td>PrivilegeType</td>\n  </tr>\n  <tr>\n    <td>.privilege.p</td>\n    <td>Zone is executed in privileged level.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.privilege.u</td>\n    <td>Zone is executed in unprivileged level.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_memory \".memory\"</td>\n    <td>A sequence of all memory regions that are accessible in the zone (or system partition).</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_peripheral \".peripheral\"</td>\n    <td>A sequence of all peripherals that are accessible in the zone (or system partition).</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_interrupt \".interrupt\"</td>\n    <td>A sequence of all interrupt sources that belong to peripherals that are accessible in the zone (or system partition).</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>\\subpage fm_mpu_setup \".mpu_setup\"</td>\n    <td>A sequence of configuration information for the Memory Protection Unit (MPU).</td>\n    <td>sequence</td>\n  </tr>\n</table>\n\n\n*/\n\n\n/**************************************************************************************************/\n/**\n\\page fm_processor processor[n] sequence element\n\nThe \\ref fm_processor provides a sequence of processor elements that are in the system.\n\n<table class=\"cmtable\" summary=\"Element: processor[n]\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"2\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref fm_system \"system\"</td>\n    <td colspan=3>\\ref fm_system</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>.processor[<i>n</i>].Pname</td>\n    <td>Name of the processor core.</td>\n    <td>RestrictedString</td>\n  </tr>\n  <tr>\n    <td>.processor[<i>n</i>].DnumInterrupts</td>\n    <td>Number of NVIC interrupts sources available to the processor core (excludes exception vectors).</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.processor[<i>n</i>].DnumSauRegions</td>\n    <td>Number of regions in the Security Attribution Unit (SAU) of the processor core.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n</table>\n*/\n\n\n/**************************************************************************************************/\n/**\n\\page fm_memory memory[n] sequence element\n\nThe \\ref fm_memory provides a sequence of memory information.\n\n<table class=\"cmtable\" summary=\"Element: memory[n]\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"2\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref fm_system \"system\"</td>\n    <td colspan=3>\\ref fm_system</td>\n  </tr>\n  <tr>\n    <td>\\ref fm_zone \"zone\"</td>\n    <td colspan=3>\\ref fm_zone</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>]</td>\n    <td>Sequence of memory region information.</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].name</td>\n    <td>The name of this memory region.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].type</td>\n    <td>The type of memory in this region (\"RAM\" or \"ROM\").</td>\n    <td>MemoryTypeEnum</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].start</td>\n    <td>The logical start address of the memory region in the address map.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].physical</td>\n    <td>The physical start address of the memory region in the address map.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].size</td>\n    <td>The size (in bytes) of the memory region.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].security</td>\n    <td>The \\ref security \"security\" setting for this memory region.</td>\n    <td>SecurityType</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].security.c</td>\n    <td>Memory has non-secure callable attribute set.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].security.s</td>\n    <td>Memory is access from \\em \"secure\" state.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].security.n</td>\n    <td>Memory is access from \\em \"non-secure\" state.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].access</td>\n    <td>The \\ref access \"access\" permissions for this memory region in the following separate fields.</td>\n    <td>AccessType</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].access.r</td>\n    <td>The \\em read \\ref access \"access\" permission.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].access.w</td>\n    <td>The \\em write \\ref access \"access\" permission.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].access.x</td>\n    <td>The \\em execution \\ref access \"access\" permission.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].access.p</td>\n    <td>The \\em peripheral \\ref access \"access\" information.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].privilege</td>\n    <td>The \\ref privilege \"privilege type\" settings for this memory region in the following separate fields.</td>\n    <td>PrivilegeType</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].privilege.p</td>\n    <td>The \\em privileged \\em level setting of \\ref privilege \"privilege type\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].privilege.u</td>\n    <td>The \\em unprivileged \\em level setting of \\ref privilege \"privilege type\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].startup</td>\n    <td>\"1\" specifies that this region is used for the startup code of the application. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].uninit</td>\n    <td>\"1\" specifies that this region is not zero initialized during startup. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].shared</td>\n    <td>\"1\" specifies that this region is used by multiple zones. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].dma</td>\n    <td>\"1\" specifies that this region is accessed by a DMA controller. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].info</td>\n    <td>Brief description of the memory region.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.memory[<i>n</i>].linker_control</td>\n    <td>Brief description of the memory region.</td>\n    <td>xs:string</td>\n  </tr>\n</table>\n*/\n\n/**************************************************************************************************/\n/**\n\\page fm_sau sau[n] sequence element\n\nThe \\ref fm_sau lists all SAU regions for initialization in this system.\n\nIt lists all SAU regions that require either non-secure access or non-secure callable attribute.\nThe SAU region list is generated from:\n  - setup information from \\ref xml_si_region\n  - memory regions that are assigned to zones with non-secure domain.\n  - memory regions that are configured as secure, non-secure callable.\n\n<table class=\"cmtable\" summary=\"Element: sau[n]\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"2\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref fm_system \"system\"</td>\n    <td colspan=3>\\ref fm_system</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>.sau[<i>n</i>].start</td>\n    <td>The logical start address for the region.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.sau[<i>n</i>].end</td>\n    <td>The logical end address for the region.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.sau[<i>n</i>].nsc</td>\n    <td>If set to 1 the region is secure, non-secure callable.</td>\n    <td>SecurityTypeEnum/xs:string</td>\n  </tr>\n  <tr>\n    <td>.sau[<i>n</i>].info</td>\n    <td>List of memory regions or info from \\ref xml_si_region.</td>\n    <td>xs:string</td>\n  </tr>\n</table>\n*/\n\n\n/**************************************************************************************************/\n/**\n\\page fm_interrupt interrupt[n] sequence element\n\nThe \\ref fm_interrupt lists all interrupt sources available in the system.\n\n<table class=\"cmtable\" summary=\"Element: interrupt[n]\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"2\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref fm_system \"system\"</td>\n    <td colspan=3>\\ref fm_system</td>\n  </tr>s\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>.interrupt[<i>n</i>].name</td>\n    <td>The name of this interrupt.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.interrupt[<i>n</i>].irqn</td>\n    <td>The interrupt number.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.interrupt[<i>n</i>].security</td>\n    <td>The \\ref security \"security\" setting for this interrupt.</td>\n    <td>SecurityTypeEnum/xs:string</td>\n  </tr>\n  <tr>\n    <td>.interrupt[<i>n</i>].security.s</td>\n    <td>Peripheral with related interrupt is assigned to \\em \"secure\" state.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.interrupt[<i>n</i>].security.n</td>\n    <td>Peripheral with related interrupt is assigned to \\em \"non-secure\" state.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.interrupt[<i>n</i>].info</td>\n    <td>Brief description of the interrupt source.</td>\n    <td>xs:string</td>\n  </tr>\n</table>\n*/\n\n/**************************************************************************************************/\n/**\n\\page fm_mpc_setup mpc_setup[n] element\n\nThe \\ref fm_mpc_setup contains a sequence of device specific configuration for the setup of the Memory Protection Controller (MPC).\n\n<table class=\"cmtable\" summary=\"Element: mpc_setup[n]\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"2\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref fm_system \"system\"</td>\n    <td colspan=3>\\ref fm_system</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>.mpc_setup[<i>n</i>].name</td>\n    <td>The name of the base register that controls the MPC.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.mpc_setup[<i>n</i>].memory</td>\n    <td>The name of the physical memory region that is connected via the MPC.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.mpc_setup[<i>n</i>].blk_size</td>\n    <td>The block size information that CMSIS-Zone used for LUT generation.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.mpc_setup[<i>n</i>].S_bit[<i>m</i>]</td>\n    <td>A list of bit values for Secure attribute that are used to compose the LUT.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.mpc_setup[<i>n</i>].P_bit[<i>m</i>]</td>\n    <td>A list of bit values for Privileged attribute that are used to compose the LUT.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.mpc_setup[<i>n</i>].bits_comment[<i>m</i>]</td>\n    <td>The memory region information for source code comments that relate to S_bits or P_bits.</td>\n    <td>xs:string</td>\n  </tr>\n</table>\n*/\n\n/**************************************************************************************************/\n/**\n\\page fm_reg_setup reg_setup[n] element\n\nThe \\ref fm_reg_setup contains a sequence of device specific configuration for the setup of the interrupts.\n\n<table class=\"cmtable\" summary=\"Element: reg_setup[n]\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"2\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref fm_system \"system\"</td>\n    <td colspan=3>\\ref fm_system</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>.reg_setup[<i>n</i>].name</td>\n    <td>The name of the register or array that holds the configuration information.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.reg_setup[<i>n</i>].index</td>\n    <td>The index value for the register array.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.reg_setup[<i>n</i>].peripheral[<i>m</i>]</td>\n    <td>An array with the peripheral names that setup belongs too.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.reg_setup[<i>n</i>].slot[<i>m</i>]</td>\n    <td>An array with the slot names that setup belongs too. The value is empty when setup is not related to a slot</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.reg_setup[<i>n</i>].value[<i>m</i>]</td>\n    <td>An array with register setup values (corresponds to .peripheral[<i>m</i>] and .slot[<i>m</i>] above).</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n</table>\n*/\n\n\n/**************************************************************************************************/\n/**\n\\page fm_peripheral peripheral[n] element\n\nThe \\ref fm_peripheral contains a sequence of all peripherals that are accessible in the zone (or system partition).\n\n<table class=\"cmtable\" summary=\"Element: peripheral[n]\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"2\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref fm_system \"system\"</td>\n    <td colspan=2>\\ref fm_system</td>\n  </tr>\n  <tr>\n    <td>\\ref fm_zone \"zone\"</td>\n    <td colspan=2>\\ref fm_zone</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].name</td>\n    <td>The name of the peripheral.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].group</td>\n    <td>The name of the peripheral group that this peripheral belongs too.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].start</td>\n    <td>The logical start address of the peripheral in the address map.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].size</td>\n    <td>The size (in bytes) of the peripheral.</td>\n    <td>NonNegativeInteger</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].security</td>\n    <td>The \\ref security \"security\" setting for this peripheral.</td>\n    <td>SecurityType</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].security.s</td>\n    <td>Peripheral is assigned to \\em \"secure\" state.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].security.n</td>\n    <td>Peripheral is assigned to \\em \"non-secure\" state.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].access</td>\n    <td>The \\ref access \"access\" permissions for this peripheral in the following separate fields.</td>\n    <td>AccessType</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].access.r</td>\n    <td>The \\em read \\ref access \"access\" permission.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].access.w</td>\n    <td>The \\em write \\ref access \"access\" permission.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].access.x</td>\n    <td>The \\em execution \\ref access \"access\" permission.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].access.p</td>\n    <td>The \\em peripheral \\ref access \"access\" information.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].privilege</td>\n    <td>The \\ref privilege \"privilege type\" settings for this peripheral in the following separate fields.</td>\n    <td>PrivilegeType</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].privilege.p</td>\n    <td>The \\em privileged \\em level setting of \\ref privilege \"privilege type\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].privilege.u</td>\n    <td>The \\em unprivileged \\em level setting of \\ref privilege \"privilege type\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].shared</td>\n    <td>\"1\" specifies that this peripheral is used by multiple zones. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].dma</td>\n    <td>\"1\" specifies that this peripheral is accessed by a DMA controller. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>.peripheral[<i>n</i>].info</td>\n    <td>Brief description of the peripheral region.</td>\n    <td>xs:string</td>\n  </tr>\n</table>\n*/\n\n/**************************************************************************************************/\n/**\n\\page fm_mpu_setup mpu_setup element\n\nThe \\ref fm_mpu_setup contains the configuration information for the Memory Protection Unit (MPU).\n\n<table class=\"cmtable\" summary=\"Element: mpu_setup\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"2\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref fm_system \"zone\"</td>\n    <td colspan=3>\\ref fm_zone</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n  </tr>\n  <tr>\n    <td>mpu_setup.type</td>\n    <td>Implementation of the MPU (\"v7M\" or \"v8M\").</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>]</td>\n    <td>Sequence of MPU region settings.</td>\n    <td>sequence</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].start</td>\n    <td>The base address of the region.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].end</td>\n    <td>The end address of the region.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].access.r</td>\n    <td>The \\em read \\ref access \"access\" permission setting for the region.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].access.w</td>\n    <td>The \\em write \\ref access \"access\" permission setting for the region.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].access.x</td>\n    <td>The \\em execution \\ref access \"access\" permission setting for the region.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].access.p</td>\n    <td>The \\em peripheral \\ref access \"access\" information setting for the region.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].privileged</td>\n    <td>'1' indicates that the region is set to Privileged mode.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].shared</td>\n    <td>'1' indicates that the region is shared across various processors.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].dma</td>\n    <td>'1' indicates that the region is accessed by a DMA controller.</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].rom</td>\n    <td>'1' indicates that the memory type of that region is ROM ('0' for RAM or peripheral).</td>\n    <td>xs:boolean</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].addr_v7M</td>\n    <td>Only for v7M: Region base address field value for v7M register MPU_RBAR.</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].size_v7M</td>\n    <td>Only for v7M: Block size field value for v7M register MPU_RASR (examples: 4=32bytes, 9=1KB, 19=1MB).</td>\n    <td>xs:string</td>\n  </tr>\n  <tr>\n    <td>mpu_setup.region[<i>n</i>].srd_v7M</td>\n    <td>Only for v7M: Subregion disable value for v7M register MPU_RASR.</td>\n    <td>xs:string</td>\n  </tr>\n  \n  \n</table>\n*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Zone/src/Overview.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\mainpage\n\n\\section Overview Overview\n\nEmbedded systems frequently integrate specify hardware for access protection or system isolation. For example, a Cortex-M33 processor based system may incorporate:\n - SAU (Secure Attribute Unit) to create a secure execution partition with controlled access from a non-secure execution partition.\n - MPC (Memory Protection Controller) to control the system-wide access permissions to memory.\n - PPC (Peripheral Protection Controller) to control the system-wide access permissions to peripherals.\n - MPU (Memory Protection Unit) to create execution compartments and protect other system parts from illegal access.\n\nEmbedded systems may also integrate multiple processors that share system resources (memory and peripherals). In an AMP\n(Asymmetric Multiprocessor System) it is required to assign or partition the available resources to various processors\nthat execute independent parts of the application software.\n\n\\b CMSIS-Zone helps you to manage this complexity and allows to partition an embedded system into <b>project zones</b>\nand/or <b>execution zones</b>.\n\nA <b>project zone</b> defines the memory resources and peripherals for a sub-project that execute on the system.\nTypical examples are boot-loader and user application, however also the secure and non-secure parts of a Cortex-M TrustZone\nsystem is defined using project zones.\n\nAn <b>execution zone</b> is a software compartment that is protected using a MPU.\nIt defines the access rights to memory and peripherals for a isolated part of the system. This ensures that for example a\ncommunication stack (with design flaws) cannot tamper the data or peripherals of other critical parts in a system.\n\n\\b CMSIS-Zone includes a utility that allows you to manage these zones. The input to this utility is a resource (*.rzone) file the defines the system resources\nincluding memory and peripherals.\n\nFor these resources the user interface of the CMSIS-Zone utility allows:\n  - to setup of overall system-wide access permissions to memory and peripherals.\n  - to define project zones (optional with processor selection and/or security mode) or execution zones (optional with privilege level).\n  - to assign memory and peripherals to these project or execution zones.\n\nThis system configuration is stored in an assignment (*.azone) file.  With the \\b Generate function of\nthe CMSIS-Zone utility, the resource and configuration data can be used to generate:\n  - source code for the setup of protection hardware such as SAU, MPC, PPC, MPU.\n  - configuration files for software development tools (i.e. linker scatter file).\n  - sub-system resource (*.rzone) files that list <b>project zone</b> resources available for sub-projects.\n\nThe following diagram shows the development work flow when using the \\b CMSIS-Zone management tool.\n\n\\image html Partitioning_Workflow.png  \"CMSIS-Zone development workflow\"\n\n\nIt is possible to uses these steps multiple times which allows to split a complex SoC design with multiple processors into\nsmaller sub-systems. For example a multi-core device can be partitioned in steps:\n  - Step 1: split the multi-processor system into single processor sub-systems.\n  - Step 2: create the partitions for secure and non-secure execution.\n  - Step 3: configure MPU protected execution zones.\n\nThe following SoC diagram exemplifies step 1 and step 2 of this workflow.\n\n\\image html Partitioning_Hardware.png  \"Hardware partitioning in multiple steps\"\n\n\\section ManualSections Manual Sections\n\nThe following sections explain:\n- \\ref zoneToolUsage describes the tool features and explains the usage on several examples.\n- \\ref zoneFormat (XML based) that stores resource (*.rzone) and assignment (*.azone) information.\n- \\ref GenDataModel which is used to create tool set-up files and hardware configuration files.\n- \\ref ErrorMessages explains the output messages issued by CMSIS-Zone utility.\n\n\\section mainIntroVideo Introduction Video\n\nThis video show how to use the \\ref zoneToolUsage :\n\n\\htmlonly\n<video preload=\"none\" controls=\"\" poster=\"https://community.arm.com/cfs-file/__key/telligent-evolution-videotranscoding-securefilestorage/communityserver-blogs-components-weblogfiles-00-00-00-21-12/Nuvoton_5F00_Zone.mp4.jpg\" width=\"880\" height=\"495\">\n      <source type=\"video/mp4\" src=\"https://community.arm.com/cfs-file/__key/telligent-evolution-videotranscoding-securefilestorage/communityserver-blogs-components-weblogfiles-00-00-00-21-12/Nuvoton_5F00_Zone.mp4.mp4\">\n      <source type=\"video/webm\" src=\"https://community.arm.com/cfs-file/__key/telligent-evolution-videotranscoding-securefilestorage/communityserver-blogs-components-weblogfiles-00-00-00-21-12/Nuvoton_5F00_Zone.mp4.webm\">\n  </video>\n\\endhtmlonly\n\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zone_revisionHistory Revision History of CMSIS-Zone\n\n<table class=\"cmtable\" summary=\"Revision History\">\n    <tr>\n      <th>Version</th>\n      <th>Description</th>\n    </tr>\n    <tr>\n      <td>1.1.0</td>\n      <td>\n        <ul>\n          <li>MPU support for Arm V7 architecture</li>\n          <li>upgrade handling of data in .azone, .rzone and .fzone files according to changes in CMSIS-Zone specification</li>\n        </ul>\n      </td>\n    </tr>    <tr>\n      <td>1.0.0</td>\n      <td>\n        <ul>\n          <li>Initial release including the main functionality.</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>0.9.5 (Preview)</td>\n      <td>\n        <ul>\n          <li>generation of \\ref fm_mpu_setup in .fzone files (currently limited to Armv8 architecture)</li>\n          <li>support for \\ref xml_configure in .azone files: show and assign memory regions and peripherals according to the settings</li>\n          <li>Setup page in the editor to view zone properties and configure settings</li>\n          <li>bug fixes</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>0.9.4 (Preview)</td>\n      <td>\n        <ul>\n          <li>look and feed: icons and colors</li>\n          <li>improved error processing and reporting</li>\n          <li>bug fixes</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>0.9.2 (Preview)</td>\n      <td>\n        <ul>\n          <li>additional flags for memory regions: init, DMA, startup</li>\n          <li>fixes and enhancements in MPC and SAU handling</li>\n          <li>enhanced algorithm for memory region arrangement with MPC</li>\n          <li>possibility to save altered permissions for top-level memory regions and peripherals</li>\n          <li>individual configuration of peripheral channels and pins</li>\n          <li>improved new CMSIS Zone project wizard: it is possible to specify an available .rzone file instead of device</li>\n          <li>UI enhancements and bugfixes</li>\n        </ul>\n      </td>\n    </tr>\n    <tr>\n      <td>0.9.0-alpha (Preview)</td>\n      <td>Alpha with completely revised workflow.</td>\n    </tr>\n    <tr>\n      <td>0.0.3 (Preview 3)</td>\n      <td>Initial specification draft</td>\n    </tr>\n</table>\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page UseCases CMSIS-Zone Use Cases\n\n\\b CMSIS-Zone simplifies to manage the complexity and the configuration of modern embedded systems that frequently include\nmultiple processors and/or memory protection hardware. It helps to split the embedded application various projects which\ncreates the need to partition system resources. And it simplifies the consistent configuration of access rights across the\nsystem, for example when using an MPU (memory protection unit).\n\nThe following section describes several use cases that benefit from \\b CMSIS-Zone.\n\n\n\\section UseCase_MPU MPU Protection\n\nFocused on a single core microcontroller one might want to utilize the memory protection unit (MPU) capabilities\nto segregate parts of an application. Thus the need to partition the system resources accordingly arises.\n\n\\image html mpu.png  \"MPU Protection\"\n\n\n\\section UseCase_TrustZone TrustZone Partitioning\n\nTrustZone extensions add another degree of segregation which must be handled consistently.\nIn this case one has to handle MPU settings per security context and SAU configuration.\n\n\\image html trustzone.png  \"TrustZone Partitioning and MPU Protection\"\n\n\n\\section UseCase_MultiCore Multi-Core Partitioning\n\nBeside traditional single cores asymmetric and hybrid multi-core devices contribute to increasing development complexity\nfor embedded systems. Having multiple cores running different parts of an application concurrently needs a well defined\nresource assignment to prevent undesired misbehavior.\n\n\\image html multicore.png  \"Multi-Core Partitioning\"\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zoneToolUsage CMSIS-Zone Utility\n\nThe section describes the CMSIS-Zone Utility which is currently a stand-alone Eclipse implementation that allows you to:\n  - \\ref zTUIMemView \"View the memory and peripheral resources\" of a complete system or sub-system.\n  - \\ref zTUIMemAdd \"Partition memory blocks\" into smaller regions and define access permissions for these regions.\n  - \\ref zTUIPerProp \"Define access permissions\" for peripherals.\n  - \\ref zTUIPerSlotConf \"Configure access rights of peripheral slots\" (for example for DMA channels or I/O pins).\n  - \\ref zTUIZonePart \"Split memory and peripheral resources into zones\" (used for sub-projects or process separation in RTOS\n    systems).\n  - \\ref zTUIGenerate \"Generate\" configuration files for tool and hardware setup, as well as\n  - \\ref zTUIGenerate \"Generate\" resource files for sub-systems that allow further partitioning.\n\nThis section describes:\n - \\subpage zTInstall shows how to install the utility.\n - \\subpage zTUI introduces the GUI of the CMSIS-Zone Utility.\n - \\subpage zTInteractiveMode explains how to create projects and zones using the GUI.\n - \\subpage zTCLI demonstrates how to work with the command line interface.\n - \\subpage zTExamples contains ready-to-use projects for various devices.\n\n\\note\n\nIt is assumed that you are familiar with Eclipse and\n<a href=\"https://arm-software.github.io/CMSIS_5/Pack/html/index.html\" target=\"_blank\">CMSIS-Packs</a>. The relevant device\nfamily pcks for your target device need to be installed on your computer.\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTInstall Installation\n\nThe CMSIS-Zone utility is part of the <a href=\"https://github.com/ARM-software/cmsis-pack-eclipse/releases/latest\" target=\"_blank\"><b>CMSIS-Pack Eclipse Plug-ins</b></a>.\n\nFollow the instructions on the release page to install the tool.\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTUI User Interface\n\nThe CMSIS-Zone Utility user interface offers menus, toolbars, dialog boxes, and windows to manage the various aspects of your\nproject.\n\n\n\\section zTGUI CMSIS-Zone GUI\n\nThe utility's GUI provides menus for selecting commands and toolbar buttons in the \\ref zTGUIZoneEditor window:\n\n\\image html GUI.png\n\n\n\\section zTProjEx Project Explorer\n\nProjects that are currently available in the Eclipse workspace are shown in the <b>Project Explorer</b>. When creating a new\nproject, you will first find the \\ref rzone \".rzone\" and the \\ref azone \".azone\" files here. Later, generator files and\ngenerated files are shown as well:\n\n\\image html ProjectExplorerWindow.png \"Project Explorer window showing a complex project\"\n\nIn the <b>Project Explorer</b> window, you manage the project files. The following files are shown:\n\n| File name                        | Description                                                          |\n|----------------------------------|----------------------------------------------------------------------|\n| \\c project.azone                 | Project-level \\ref azone \".azone\" file                               |\n| \\c project.rzone                 | Project-level \\ref rzone \".rzone\" file                               |\n| \\c zone.azone                    | Zone-level \\ref azone \".azone\" file                                  |\n| \\c zone.rzone                    | Zone-level \\ref rzone \".rzone\" file                                  |\n| <tt>*.ftl</tt>                   | Freemarker template file used to \\ref GenDataModel \"generate\" output |\n| \\c helper.ftlinc                 | Helper file to generate Freemarker output                            |\n| <tt>*.sct,</tt> \\c partition_*.h | Generated output files                                               |\n\n\n\\section zTGUIZoneEditor Zone Editor\n\nThe <b>Zone Editor</b> shows \\ref azone \".azone\" files in two different views: \\b Resource \\b map and \\b Zone \\b map.\n\nThe \\b Resource \\b map shows all resources available to that system or sub-system. By default, it shows the selected device,\nas well as lists of memories and peripherals:\n\n\\image html resource_map.png\n\nThe \\b Zone \\b map shows the same resources, but mapped to zones that have been created for the device:\n\n\\image html zone_map.png\n\nResources assigned to a zone are marked with colors:\n| Color | Meaning |\n|-------|---------|\n| Green | Resource is assigned to one zone |\n| Amber | Resource is assigned to multiple zones |\n\n\n\\subsection zTGUIButtons Toolbar Buttons\n\nThe <b>Zone Editor</b> window contains toolbar buttons that offer direct access to functionality of the utility:\n\n\\image html Buttons.png\n\n| Button                         | Description                                     |\n|--------------------------------|-------------------------------------------------|\n| Tree View                      | Shows the resources as a tree                   |\n| List View                      | Shows the resources as a simple list            |\n| Arrange memory regions         | Arranges memory regions according to their sizes |\n| \\ref zTUICreate \"Add new zone\" | Adds a new zone to the zone map                 |\n| \\ref zTUIGenerate \"Generate\"   | Generates CMSIS-Zone output files               |\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTInteractiveMode Interactive Mode\n\nThe following section explains the interactive mode of the CMSIS-Zone Utility.\nThe following steps are explained:\n\n - \\subpage zTUICreateProject that allows to manage system resources.\n - \\subpage zTUIMemPerRes allows to create sub-memory regions and defines properties such as access permissions.\n - \\subpage zTUIZonePart that assigns available resources to sub-projects or execution compartments.\n - \\subpage zTUIGenerate for device configuration and linker settings.\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTUICreateProject Create a CMSIS-Zone Project\n\nGo to <b>File - New - Project</b> and select <b>CMSIS - CMSIS-Zone Project</b>:\n\n\\image html zone_project.png\n\nClick \\b Next. In the next window, enter a \\b Project \\b name:\n\n\\image html SetProjectName.png\n\nClick \\b Next.\n\n\\section zTUICreateProjectVar1 Variant 1: Using an existing *.rzone file\n\nIn the next window, select <b>Use existing resource file (*.rzone)</b> and browse to the location of the\n*.rzone file:\n\n\\image html SpecifyRzoneFile.png\n\nClick \\b Finish. The new project is created and an empty *.azone file is added.\n\n\n\\section zTUICreateProjectVar2 Variant 2: Creating an *.rzone file using the SVD file from the device family pack\n\nIn the next window, use <b>Select device to create resource file from device description</b>:\n\n\\image html SelectDeviceFrom.png\n\nNext, select your device from the list of installed device family packs:\n\n\\image html SelectDevice.png\n\nClick \\b Finish. The new project and the *.rzone file are created and an empty *.azone file is added.\n\n\\note\n\nMake sure that you have set the path to your pack installation directory correctly. Go to <b> Window -> Preferences </b> and\ncheck the entry for the <b>CMSIS Pack root folder</b> (usually set to \\c \\%localappdata%\\\\Arm\\\\Packs):\n\n\\image html window_preferences.png\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTUIMemPerRes Memory and Peripheral Resources\n\nThe available memory can be further divided into \\ref zTUIMemAdd \"smaller regions\" that are later assigned to zones,\nfor example a zone for loader and zone for application.\n\nFor memory and peripherals \\ref zTUIPerProp \"properties\" such as access permission, privilege, and security level can be configured.\nThese settings can be for example used to generate source code files that configure the device at run-time.\n\n\n\\section zTUIMemView View memory and peripheral resources\n\nInitially, this uses the information in the *.rzone file which defines the generic access permissions for memory and\nperipherals. The CMSIS-Zone Editor shows the \\b Resource \\b Map of the given device:\n\n\\image html lpc55_resource_map.png\n\nHere, you can see all resources that are available on the device.You see \\b Memory, \\b Peripherals, \\b Cores, and \\b Info\nrelated to the resources. \\ref zTGUIZoneEditor \"Colored resources\" are assigned to a zone.\n\n\n\\section zTUIMemAdd Create Memory Regions\n\nTo create a new memory region, right-click on the memory that you want to divide and select <b>Add memory region</b>:\n\n\\image html AddMemoryBlock.png\n\nIn the dialog a name derived from the parent memory region is provided. Change this region name as needed and specify the\nsize. In this dialog, you change permissions, privilege, or security level for the memory region. When\ndone, click \\b Finish:\n\n\\image html NewMemoryBlockWiz.png\n\nThe new memory region is immediately shown in the zone map. Depending on the security level, you may be able to assign this\nnew region only to certain zones. For example, secure memory regions cannot be assigned to a non-secure zone.\n\n\\image html IRAM1_1Display.png\n\nThe information about the memory regions is stored in the \\ref xml_amemory element of the *.azone file.\n\n\n\\section zTUIMemDel Delete Memory Regions\n\nTo delete a memory region, right-click on the memory region select <b>Delete memory region</b>:\n\n\\image html DelMemoryRegion.png\n\n\n\\section zTUIPerProp Resource Properties\n\nTo change the properties of a resource, such as a peripheral for example, right-click the resource and select \\b Properties:\n\n\\image html res_prop.png\n\nThen, you can set these properties:\n\n\\image html peripheral_properties.png\n\n\\b General\n- \\c Shared: the resource can be accessed by more than one zone\n- \\c Startup: locate the vector table to this region\n- \\c No zero init: preserve RAM content at startup\n- \\c DMA: enable direct memory access\n\n\\b Permissions\n\n- \\c peripheral: mark this as a peripheral\n- \\c read\n- \\c write\n- \\c execute\n\n\\b Privilege\n\n- \\c not specified\n- \\c privileged\n- \\c unprivileged\n\n\\b Security\n- \\c not specified\n- \\c non-secure\n- \\c non-secure callable\n- \\c secure\n\nThe information about the peripherals is stored in the \\ref xml_aperipheral element of the *.azone file.\n\n\\section zTUIPerSlotConf Configure peripheral slot access rights\n\nPeripherals can have so called slots that can be configured separately. Depending on the peripheral, the slots have different\nnames in the Zone Editor. For example, for DMA they are called \\b Channels:\n\n\\image html dma_channel_config.png\n\nFor GPIOs, they are called \\b Pins:\n\n\\image html gpio_pins_config.png\n\nIn the dialog, you can set security and privilege levels:\n\n\\image html dma_gpio_config.png\n\nThe information about the slots is stored in the \\ref xml_aslot element of the *.azone file.\n\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTUIZonePart Zone Partitioning\n\nEvery CMSIS-Zone project consists of one or more zones. The basic flow to create zones is as follows:\n- In case of multi-core devices, create a zone for each processor.\n- Then create at least one zone for each processor to be able to assign memories and peripherals. If your device contains\n  Arm Cortex-M cores supporting TrustZone for Armv8-M, create a secure and a non-secure partition for each of these cores.\n\n\n\\section zTUICreate Create Zones\n\nTo split a multi-processor system into single-processor sub-systems, you need to create new zones. Switch to the \\b Zones tab\nand click the <b>Add new zone</b> button:\n\n\\image html AddNewZoneButton.png\n\nIn the new window, you need to specify a name for the zone, select the applicable core, and choose the security level\n(secure/non-secure).\n\nIn the \\ref zTEMuscaA1 \"Musca-A1\" example, a new zone called \"CM33_0\" was created and attached to processor core 0 without any\nsecurity attribute (not specified):\n\n\\image html NewZoneCM33_0.png\n\nSimilarly, an additional zone called \"CM33_1\" was created and attached to processor core 1, without security attribute.\n\n\\b Save your settings:\n\n\\image html  SaveButton.png\n\n\\note\n\nAdding zones only works for the currently opened \\ref azone \".azone\" file.\nThe information about the zones is stored in the \\ref xml_zones element of the *.azone file.\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTUIGenerate Generate output files\n\nThe CMSIS-Zone utility can generate files that represent the configuration of the system. These files can be used\nin the project source files or tool configuration files.\n\nother toolchains for further development. The generator process creates:\n- Configuration files for tool and hardware setup, that are defined by \\ref GenDataModel \".ftl files\" in the project \\c ftl\n  directory.\n- Files that represent \\ref  zTUICreate \"sub-systems\" (\\ref rzone \".rzone\" and \\ref azone \".azone\") that can be partitioned\n  further (restart the process).\n\nTo start the generation, press the <b>Generate</b> button or use the menu item <b>CMSIS Zone - Generate</b>:\n\n\\image html GenCodeButton.png\n\nCheck \\ref zTProjEx to observe the changes. In the project, the generated \\c .azone and \\c .rzone files appear and the \\c ftl_gen directory contains the\nfiles defined by the \\c ftl template files:\n\n\\image html gen_output.png\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTCLI Command Line Mode\n\nAs the \\ref rzone \".rzone\" and \\ref azone \".azone\" files are XML based, it is possible to create or modify the files in external tools\nwithout using the \\ref zTInteractiveMode. To generate output files the CMSIS-Zone Utility can be started in\nheadless mode. The command line format is:\n\n<tt>eclipsec.exe -noSplash  -consoleLog --launcher.suppressErrors -application com.arm.cmsis.zone.ui.headlessgen -azone FILENME.azone  -ftl FTL_DIR -ftl_gen FTL_GEN_DIR</tt>\n\n\\b  Where\n\n| Parameter                                            | Description                                                    | Required |\n|:-----------------------------------------------------|:---------------------------------------------------------------|:---------|\n| \\c -noSplash                                         | Suppresses Eclipse's splash screen                             | [required] |\n| \\c -launcher.suppressErrors                          | Suppresses error dialog                                        | [optional] |\n| \\c -consoleLog                                       | Suppresses diagnostic messages                                 | [optional] |\n| \\c -application \\c com.arm.cmsis.zone.ui.headlessgen | Specifies the plug-in to be called                             | [required] |\n| \\c -azone \\c FILNAME.azone                           | Specifies the .azone file to be processed                      | [required] |\n| \\c -ftl \\c FTL_DIR                                   | Relative or absolute directory with templates to process       | [optional - by default, \\c ftl directory under the azone's file path is used] |\n| \\c -ftl_gen \\c FTL_GEN_DIR                           | Relative or absolute output directory to write generated files | [optional - by default, \\c ftl_gen directory under the azone's file path is used] |\n| \\c -help                                             | Shows command line parameter information                       | [optional] |\n\n<!--\\b Examples\n\\code\neclipsec.exe -noSplash -application com.arm.cmsis.zone.ui.headlessgen -azone Musca-A1.azone\n\\endcode-->\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTExamples Examples\n\nThe following projects are available in the CMSIS-Zone repository on GitHub: https://github.com/ARM-software/CMSIS-Zone/tree/main/Examples.\nThese examples demonstrate the usage of the CMSIS-Zone utility.\n\n| Example                    | Description                                                    |\n|:---------------------------|:---------------------------------------------------------------|\n| \\subpage zTEMuscaA1        | Musca A1 (Cortex-M33) project with TrustZone setup             |\n| \\subpage zTEMuscaS1        | Musca S1 (Cortex-M33) project with TrustZone setup             |\n| \\subpage zTEM2351          | Single processor Cortex-M23 project with TrustZone setup       |\n| \\subpage zTELPC55          | Single processor Cortex-M33 project with TrustZone setup       |\n| \\subpage zTESTM32L5        | Single processor Cortex-M33 project with TrustZone setup       |\n| \\subpage zTESAML11         | Single processor Cortex-M23 project with TrustZone setup       |\n| \\subpage zTEMCB400         | Single processor Cortex-M3 project with MPU setup              |\n\n\n\\section zTExImport Import examples\n\nImport the examples to Eclipse using the following flow:\n- Go to <b>File - Import</b> and select <b>General - Existing Projects into Workspace</b>:\n\n\\image html import_from_file.png\n\nClick \\b Next.\n\nBrowse to the root directory, for example \"Examples\\LPC55S69\\Zone\", and select the project that you want to import. The import\nprojects window shows the available projects:\n\n\\image html import_projects.png\n\nClick \\b Finish. The project is imported and opened in the \\ref zTProjEx.\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTEMuscaA1 Arm Musca-A1\n\nThis example shows how to do the \\ref UseCase_TrustZone. It is split into a secure and non-secure part. Using\nCMSIS-Zone, it generates:\n - A header file that contains \\#defines to control the various linker scatter files (and might be used in other parts of the\n   application).\n - Memory protection controller (MPC) setup.\n - Peripheral protection controller (PPC) and related interrupt setup.\n - Secure attribution unit (SAU) setup.\n\n\n\\section zTEMusca_Eclipse Using the CMSIS-Zone project\n\n  - \\ref zTExImport \"Import\" the project \"Examples\\Musca-A1\\Zone\" into the CMSIS-Zone utility\n  - \\ref zTProjEx \"Open\" the Musca-A1.azone file\n  - \\ref zTUIGenerate \"Generate\" the related output files\n\nThe Musca-A1.azone file of that project has the following configuration settings:\n  - \\ref zTUICreate \"Added the zones\" \\c SecureFW and \\c NonsecureFW\n  - \\ref zTUIMemAdd \"Created the memory regions\" \\c SecureRAM, \\c NonsecureRAM, \\c ScureCode, \\c Veneer, and \\c NonsecureCode\n  - Selected various memory regions and peripherals for using in the different zones.\n\n\\image html muscaA1_zones.png\n\nThe zones use different Flash and SRAM regions for code and data. Peripherals, such as the system and IO configuration, as\nwell as UART0 are available in the secure world only. To generate the output, click on the \\ref zTUIGenerate \"Generate\"\nbutton in the Zone Editor tool bar. This creates the following files in the \\c ftl_gen directory:\n\n| Template File        | Generated File   | Description |\n|:---------------------|:-----------------|:-------------|\n| dump_fzone.txt.ftl   | dump_fzone.txt   | Contains the complete model  |\n| helper.ftlinc        | N/A              | Helper template file with FTL functions. |\n| mem_layout.h.ftl     | mem_layout.h     | Header file that contains the memory region definitions, for example for the linker scatter file. |\n| tz_sau_nvic.c.ftl    | tz_sau_nvic.c    | Configuration of the secure attribution unit (SAU) and the NVIC interrupt assignment. |\n| tz_mpc_ppc.c.ftl     | tz_mpc_ppc.c     | Configuration of the memory (MPC) and peripheral (PPC) protection controller. |\n\nThese files can be used in any IDE to create the final application.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTEMuscaS1 Arm Musca-S1\n\nThis example shows how to do the \\ref UseCase_TrustZone. It is split into a secure and non-secure part. Using\nCMSIS-Zone, it generates:\n - A header file that contains \\#defines to control the various linker scatter files (and might be used in other parts of the\n   application).\n - Memory protection controller (MPC) setup.\n - Peripheral protection controller (PPC) and related interrupt setup.\n - Secure attribution unit (SAU) setup.\n\n\n\\section zTEMusca_Eclipse Using the CMSIS-Zone project\n\n  - \\ref zTExImport \"Import\" the project \"Examples\\Musca-AS\\Zone\" into the CMSIS-Zone utility\n  - \\ref zTProjEx \"Open\" the Musca-AS.azone file\n  - \\ref zTUIGenerate \"Generate\" the related output files\n\nThe Musca-AS.azone file of that project has the following configuration settings:\n  - \\ref zTUICreate \"Added the zones\" \\c SecureFW and \\c NonsecureFW\n  - \\ref zTUIMemAdd \"Created the memory regions\" \\c SecureRAM, \\c NonsecureRAM, \\c ScureCode, \\c Veneer, and \\c NonsecureCode\n  - Selected various memory regions and peripherals for using in the different zones.\n\n\\image html muscaS1_zones.png\n\nThe zones use different Flash and SRAM regions for code and data. Peripherals, such as the system and IO configuration, as\nwell as UART0 are available in the secure world only. To generate the output, click on the \\ref zTUIGenerate \"Generate\"\nbutton in the Zone Editor tool bar. This creates the following files in the \\c ftl_gen directory:\n\n| Template File        | Generated File   | Description |\n|:---------------------|:-----------------|:-------------|\n| dump_fzone.txt.ftl   | dump_fzone.txt   | Contains the complete model  |\n| helper.ftlinc        | N/A              | Helper template file with FTL functions. |\n| mem_layout.h.ftl     | mem_layout.h     | Header file that contains the memory region definitions, for example for the linker scatter file. |\n| tz_sau_nvic.c.ftl    | tz_sau_nvic.c    | Configuration of the secure attribution unit (SAU) and the NVIC interrupt assignment. |\n| tz_mpc_ppc.c.ftl     | tz_mpc_ppc.c     | Configuration of the memory (MPC) and peripheral (PPC) protection controller. |\n\nThese files can be used in any IDE to create the final application.\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTEM2351 Nuvoton NuMicro M2351\n\nThis single processor demo application shows how to do the \\ref UseCase_TrustZone. It is split into a secure and non-secure\npart. Some peripherals are assigned to either the secure or the non-secure zone to demonstrate the generation of PPC setup\nand interrupt configuration in the partition.h template. Using CMSIS-Zone, it generates:\n - A header file that contains \\#defines to control the various linker scatter files (and might be used in other parts of the\n   application).\n - Secure attribution unit (SAU) setup.\n\nThe application itself shows how to implement calls between the secure and the non-secure part and how to use this to blink an\nLED.\n\n\n\\section zTEM2351_Eclipse Using the CMSIS-Zone project\n\n  - \\ref zTExImport \"Import\" the project \"Examples\\M2351\\Zone\" into the CMSIS-Zone utility\n  - \\ref zTProjEx \"Open\" the M2351.azone file\n  - \\ref zTUIGenerate \"Generate\" the related output files\n\nThe M2351.azone file of that project has the following configuration settings:\n  - \\ref zTUICreate \"Added the zones\" \\c Secure and \\c NonSecure\n  - \\ref zTUIMemAdd \"Created the memory regions\" \\c CODE_NS, \\c CODE_S, \\c Veneer, \\c DATA_NS, and \\c DATA_S\n  - Selected various memory regions and peripherals for using in the different zones:\n    \\image html m2351_zones.png\n\nThe zones use different Flash and SRAM regions for code and data. To generate the output, click on the\n\\ref zTUIGenerate \"Generate\" button in the Zone Editor tool bar. This creates the following files in the \\c ftl_gen\ndirectory:\n\n| Template File        | Generated File   | Description |\n|:---------------------|:-----------------|:-------------|\n| helper.ftlinc        | N/A              | Helper template file with FTL functions. |\n| mem_layout.h.ftl     | mem_layout.h     | Header file that contains the memory region definitions, for example for the linker scatter file. |\n| partition_gen.h.ftl  | partition_gen.h  | Configuration of the secure attribution unit (SAU) and the NVIC interrupt assignment. |\n| scatter_ns.sct.ftl   | scatter_ns.sct   | Example scatter file for the non-secure zone. |\n| scatter_s.sct.ftl    | scatter_s.sct    | Example scatter file for the secure zone. |\n\nThese files can be used in any IDE to create the final application. In the following, the usage in Arm Keil MDK is described.\n\n\n\\section zTEM2351_MDK Using the MDK project\n\nThe example project can be loaded, built and debugged in µVision by performing the following steps:\n\n-# Navigate to Examples/M2351/MDK\n-# Open the multi-project workspace TrustZone.uvmpw\n-# Optional: Update the generated files by executing the copy_gen.bat scripts in Secure\\\\mdk and NonSecure\\\\mdk\n   folders.\n-# Run the batch build in MDK. Both projects, Secure and NonSecure need to be compiled in order.\n-# Set \\c Secure as active project.\n-# Connect the NuMaker-PFM-M2351 board using a Micro-USB cable at ICEJ.\n-# Open <b>Options for Target - Debug</b> and make sure that the NULink Debugger is selected.\n-# Launch a debug session and watch LEDG and LEDY blinking.\n\n\n\\section zTEM2351_MDK_Setup MDK project setup\n\nThe multiproject workspace contains the \\c Secure project and the \\c NonSecure project:\n\n\\image html m2351_proj_window.png\n\nThe projects use the files generated in CMSIS-Zone as follows:\n\n| File               | Used in           | Description |\n|:-------------------|:------------------|:------------|\n| mem_layout.h       | Secure, NonSecure | Input for the scatter files. |\n| partition_gen.h    | Secure            | Configuration of the secure attribution unit (SAU) and the NVIC interrupt assignment. |\n| scatter_ns.sct     | NonSecure         | Scatter file for non-secure zone (initally based on generated file). |\n| scatter_s.sct      | Secure            | Scatter file for secure zone (initally based on generated file). |\n\nThe scatter files \\c scatter_s.sct and \\c scatter_ns.sct are using a preinclude to mem_layout.h to get the information about\nthe different memory regions.\n\n\\note\nIf you want to learn more about the general project layout for an Armv8-M project using TrustZone, refer to\n<a href=\"https://www.keil.com/appnotes/docs/apnt_291.asp\" target=\"_blank\">Application Note 291</a>.\n\n\\subsection zTEM2351_hwsScatter scatter_s.sct\n\nAs explained previously, the \\#defines in \\c mem_layout.h can be used to create generic scatter files that are easy\nto update once changes in the CMSIS-Zone project happen. Using the \\b mem_layout.h file from CMSIS-Zone, the following\nscatter file is used in the \\c Sections project:\n\n\\code\n#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -I../ -xc\n\n#include \"mem_layout.h\"\n\n; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n#define STACK_SIZE 0x400\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n#define HEAP_SIZE 0xC00\n\n; *-------------- <<< end of configuration section >>> -----------------------\nLR_CODE_S REGION_CODE_S_START REGION_CODE_S_SIZE {\n  ER_CODE_S REGION_CODE_S_START REGION_CODE_S_SIZE {\n    * (RESET,+FIRST)\n    * (InRoot$$Sections)\n    .ANY (+RO +XO)\n  }\n  RW_DATA_S REGION_DATA_S_START REGION_DATA_S_SIZE-HEAP_SIZE-STACK_SIZE {\n    .ANY (+RW +ZI)\n  }\n#if HEAP_SIZE>0\n  ARM_LIB_HEAP REGION_DATA_S_START+REGION_DATA_S_SIZE-HEAP_SIZE-STACK_SIZE EMPTY HEAP_SIZE {\n  }\n#endif\n#if STACK_SIZE>0\n  ARM_LIB_STACK REGION_DATA_S_START+REGION_DATA_S_SIZE-STACK_SIZE EMPTY STACK_SIZE {\n  }\n#endif\n}\nLR_VENEER REGION_VENEER_START REGION_VENEER_SIZE {\n  ER_VENEER REGION_VENEER_START REGION_VENEER_SIZE {\n    *(Veneer$$CMSE)\n  }\n}\n\\endcode\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTELPC55 NXP LPC55S69\n\nThis single processor demo application shows how to do the \\ref UseCase_TrustZone. It is split into a secure and non-secure\npart. Using CMSIS-Zone, it generates:\n - A header file that contains \\#defines to control the various linker scatter files (and might be used in other parts of the\n   application).\n - Memory protection controller (MPC) setup.\n - Peripheral protection controller (PPC) and related interrupt setup.\n - Secure attribution unit (SAU) setup.\n\nThe application itself shows how to implement calls between the secure and the non-secure part.\n\n\n\\section zTELPC55_Eclipse Using the CMSIS-Zone project\n\n  - \\ref zTExImport \"Import\" the project \"Examples\\LPC55S69\\Zone\" into the CMSIS-Zone utility\n  - \\ref zTProjEx \"Open\" the LPC55S69.azone file\n  - \\ref zTUIGenerate \"Generate\" the related output files\n\nThe LPC55S69.azone file of that project has the following configuration settings:\n  - \\ref zTUICreate \"Added the zones\" \\c hello_world_s and \\c hello_worls_ns\n  - \\ref zTUIMemAdd \"Created the memory regions\" \\c CODE_NS, \\c Config, \\c CODE_S, \\c Veneer, \\c DATA_NS, and \\c DATA_S\n  - Selected various memory regions and peripherals for using in the different zones:\n    \\image html lpc55_zones.png\n\nThe zones use different Flash and SRAM regions for code and data, but share Flash configuration registers. Peripherals, such\nas the system and IO configuration, as well as an UART are available in the secure world only. To generate the output, click\non the \\ref zTUIGenerate \"Generate\" button in the Zone Editor tool bar. This creates the following files in the \\c ftl_gen\ndirectory:\n\n| Template File        | Generated File   | Description |\n|:---------------------|:-----------------|:-------------|\n| dump_fzone.txt.ftl   | dump_fzone.txt   | Contains the complete model  |\n| helper.ftlinc        | N/A              | Helper template file with FTL functions. |\n| mem_layout.h.ftl     | mem_layout.h     | Header file that contains the memory region definitions, for example for the linker scatter file. |\n| scatter_ns.sct.ftl   | scatter_ns.sct   | Example scatter file for the non-secure zone (currently not used in MDK). |\n| scatter_s.sct.ftl    | scatter_s.sct    | Example scatter file for the secure zone (currently not used in MDK). |\n| tzm_config_mpc.c.ftl | tzm_config_mpc.c | Setup of the memory protection controller (MPC). |\n| tzm_config_ppc.c.ftl | tzm_config_ppc.c | Setup of the peripheral protection controller (PPC). |\n| tzm_config_sau.c.ftl | tzm_config_sau.c | Configuration of the secure attribution unit (SAU) and the NVIC interrupt assignment. |\n\nThese files can be used in any IDE to create the final application. In the following, the usage in Arm Keil MDK is described.\n\n\n\\section zTELPC55_MDK Using the MDK project\n\nThe example project can be loaded, built and debugged in µVision by performing the following steps:\n\n-# Navigate to Examples/LPC55S69/MDK\n-# Open the multi-project workspace hello_world.uvmpw\n-# Optional: Update the generated files by executing the copy_gen.bat scripts in hello_world_s\\\\mdk and hello_world_ns\\\\mdk\n   folders.\n-# Run the batch build in MDK. Both projects, hello_world_s and hello_world_ns need to be compiled in order.\n-# Set hello_world_s as active project.\n-# Connect the LPC55S69-EVK using a Micro-USB cable at Debug Link (P6).\n-# Open <b>Options for Target - Debug</b> and make sure that the CMSIS-DAP ARMv8-M Debugger is selected and the LPC-LINK2 is\n   used.\n-# Optional: Open a serial terminal program (i.e. PuTTY) on the virtual serial port provided in parallel to the debugger\n   (e.g. USB Serial Device). Configure the port to 115200/8N1.\n-# Launch a debug session and watch the serial console output:\n   \\image html hello_world_output.png\n\n\\section zTELPC55_MDK_Setup MDK project setup\n\nThe multiproject workspace contains the secure \\c hello_world_s project and the non-secure \\c hello_world_ns project:\n\n\\image html hello_world_proj_window.png\n\nThe projects use the files generated in CMSIS-Zone as follows:\n\n| File               | Used in | Description |\n|:-------------------|:--------|:------------|\n| mem_layout.h       | hello_world_s, hello_world_ns | Input for the scatter files. |\n| tzm_config_mpc.c   | hello_world_s | Functions called from tzm_config.c |\n| tzm_config_ppc.c   | hello_world_s | Functions called from tzm_config.c |\n| tzm_config_sau.c   | hello_world_s | Functions called from tzm_config.c |\n\nThe scatter files \\c hello_world_s.sct and \\c hello_world_ns.sct are based on the original scatter files from NXP and are\nusing a preinclude to mem_layout.h to get the information about the different memory regions.\n\n\\note\nIf you want to learn more about the general project layout for an Armv8-M project using TrustZone, refer to\n<a href=\"https://www.keil.com/appnotes/docs/apnt_291.asp\" target=\"_blank\">Application Note 291</a>.\n\n\\subsection zTELPC55_hwsScatter hello_world_s.sct\n\nAs explained previously, the \\#defines in \\c mem_layout.h can be used to create generic scatter files that are easy\nto update once changes in the CMSIS-Zone project happen. Using the \\b mem_layout.h file from CMSIS-Zone, the following\nscatter file is used in the secure \\c hello_world project:\n\n\\code\n; Use Arm compiler 6 to pre-process the scatter file and pull in the defines from the mem_layout.h file:\n#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -I../ -xc\n\n#include \"mem_layout.h\"\n\n; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n#define STACK_SIZE 0x400\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n#define HEAP_SIZE 0xC00\n\n; *-------------- <<< end of configuration section >>> -----------------------\n\nLR_CODE_S REGION_CODE_S_START REGION_CODE_S_SIZE {\n  ER_CODE_S REGION_CODE_S_START REGION_CODE_S_SIZE {\n    * (RESET,+FIRST)\n    * (InRoot$$Sections)\n    .ANY (+RO, +XO)\n  }\n  RW_DATA_S REGION_DATA_S_START REGION_DATA_S_SIZE-HEAP_SIZE-STACK_SIZE {\n    .ANY (+RW +ZI)\n  }\n#if HEAP_SIZE>0\n  ARM_LIB_HEAP REGION_DATA_S_START+REGION_DATA_S_SIZE-HEAP_SIZE-STACK_SIZE EMPTY HEAP_SIZE {\n  }\n#endif\n#if STACK_SIZE>0\n  ARM_LIB_STACK REGION_DATA_S_START+REGION_DATA_S_SIZE-STACK_SIZE EMPTY STACK_SIZE {\n  }\n#endif\n}\nLR_VENEER REGION_VENEER_START REGION_VENEER_SIZE {\n  ER_VENEER REGION_VENEER_START REGION_VENEER_SIZE {\n    *(Veneer$$CMSE)\n  }\n}\n\\endcode\n\n\\subsection zTELPC55_TZSetup TrustZone Setup at Startup\n\nDuring the system initialization, the function \\b SystemInitHook is called. This is used when application specific code needs\nto be called as close to the reset entry as possible. In this example, this function calls \\b BOARD_InitTrustZone, which\ncalls the three TZM_Config_* functions:\n\n\\image html lpc55_system_startup.png\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTESTM32L5 STMicroelectronics STM32L5\n\nThis single processor demo application shows how to do the \\ref UseCase_TrustZone. It is split into a secure and non-secure\npart. Using CMSIS-Zone, it generates:\n - A header file that contains \\#defines to control the various linker scatter files (and might be used in other parts of the\n   application).\n - The SystemIsolation_Config.c header file that contains memory protection controller (MPC) and peripheral protection\n   controller (PPC) and related interrupt setup.\n - The partition_gen.h header file that contains the secure attribution unit (SAU) setup and the NVIC configuration for secure/non-secure.\n\nThe application itself shows how to implement calls between the secure and the non-secure part.\n\n\n\\section zTESTM32L5_Eclipse Using the CMSIS-Zone project\n\n  - \\ref zTExImport \"Import\" the project \"Examples\\STM32L5\\Zone\" into the CMSIS-Zone utility\n  - \\ref zTProjEx \"Open\" the STM32L5.azone file\n  - \\ref zTUIGenerate \"Generate\" the related output files\n\nThe STM32L5.azone file of that project has the following configuration settings:\n  - \\ref zTUICreate \"Added the zones\" \\c blinky_s and \\c blinky_ns\n  - \\ref zTUIMemAdd \"Created the memory regions\" \\c CODE_NS, \\c CODE_S, \\c Veneer, \\c DATA_NS, and \\c DATA_S\n  - Selected various memory regions and peripherals for using in the different zones:\n    \\image html STM32L5_zones.png\n\nThe zones use different Flash and SRAM regions for code and data, but share Flash configuration registers. Peripherals, such\nas the system and IO configuration, as well as an UART are available in the secure world only. To generate the output, click\non the \\ref zTUIGenerate \"Generate\" button in the Zone Editor tool bar. This creates the following files in the \\c ftl_gen\ndirectory:\n\n| Template File        | Generated File   | Description |\n|:---------------------|:-----------------|:-------------|\n| dump_fzone.txt.ftl   | dump_fzone.txt   | Contains the complete model  |\n| helper.ftlinc        | N/A              | Helper template file with FTL functions. |\n| mem_layout.h.ftl     | mem_layout.h     | Header file that contains the memory region definitions, for example for the linker scatter file. |\n| partition_gen.h.ftl  | partition_gen.h  | Configuration of the secure attribution unit (SAU) and the NVIC interrupt assignment. |\n| SystemIsolation_Config.c.ftl | SystemIsolation_Config.c | Setup of the MPC and PPC. |\n| scatter_ns.sct.ftl   | scatter_ns.sct   | Example scatter file for non-secure zone. |\n| scatter_s.sct.ftl    | scatter_s.sct    | Example scatter file for secure zone. |\n\nThese files can be used in any IDE to create the final application. In the following, the usage in Arm Keil MDK is described.\n\n\n\\section zTESTM32L5_MDK Using the MDK project\n\nThe example project can be loaded, built and debugged in µVision by performing the following steps:\n\n-# Navigate to Examples/STM32L5/MDK\n-# Open the multi-project workspace blinky.uvmpw\n-# Optional: Update the generated files by executing the copy_gen.bat scripts in blinky_s\\\\mdk and blinky_ns\\\\mdk\n   folders.\n-# Run the batch build in MDK. Both projects, blinky_s and blinky_ns need to be compiled in order.\n\n\n\\section zTESTM32L5_MDK_Setup MDK project setup\n\nThe multiproject workspace contains the secure \\c blinky_s project and the non-secure \\c blinky_ns project:\n\n\\image html blinky_window.png\n\nThe projects use the files generated in CMSIS-Zone as follows:\n\n| File                       | Used in     | Description |\n|:---------------------------|:------------|:------------|\n| mem_layout.h               | blinky_s, blinky_ns | Input for the linker scatter files. |\n| partition_gen.h            | blinky_s    | Configuration of the secure attribution unit (SAU) and the NVIC interrupt assignment. This file is included in the partition_stm32l5xx.h header file. |\n| SystemIsolation_Config.c   | blinky_s    | Setup of the MPC and PPC. |\n| blinky_ns.sct              | blinky_ns   | Scatter file for non-secure zone (initally based on generated file). |\n| blinky_s.sct               | blinky_s    | Scatter file for secure zone (initally based on generated file). |\n\\note\nIf you want to learn more about the general project layout for an Armv8-M project using TrustZone, refer to\n<a href=\"https://www.keil.com/appnotes/docs/apnt_291.asp\" target=\"_blank\">Application Note 291</a>.\n\n\\subsection zTESTM32L5_hwsScatter blinky_s.sct\n\nAs explained previously, the \\#defines in \\c mem_layout.h can be used to create generic scatter files that are easy\nto update once changes in the CMSIS-Zone project happen. Using the \\b mem_layout.h file from CMSIS-Zone, the following\nscatter file is used in the secure \\c blinky project, which is based on the generated scatterf file (scatter_s.sct):\n\n\\code\n; Use Arm compiler 6 to pre-process the scatter file and pull in the defines from the mem_layout.h file:\n#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -I../ -xc\n\n#include \"mem_layout.h\"\n\n; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n#define STACK_SIZE 0x400\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n#define HEAP_SIZE 0xC00\n\n; *-------------- <<< end of configuration section >>> -----------------------\nLR_CODE_S REGION_CODE_S_START REGION_CODE_S_SIZE {\n  ER_CODE_S REGION_CODE_S_START REGION_CODE_S_SIZE {\n    * (RESET,+FIRST)\n    * (InRoot$$Sections)\n    .ANY (+RO +XO)\n  }\n  RW_DATA_S REGION_DATA_S_START REGION_DATA_S_SIZE-HEAP_SIZE-STACK_SIZE {\n    .ANY (+RW +ZI)\n  }\n#if HEAP_SIZE>0\n  ARM_LIB_HEAP REGION_DATA_S_START+REGION_DATA_S_SIZE-HEAP_SIZE-STACK_SIZE EMPTY HEAP_SIZE {\n  }\n#endif\n#if STACK_SIZE>0\n  ARM_LIB_STACK REGION_DATA_S_START+REGION_DATA_S_SIZE-STACK_SIZE EMPTY STACK_SIZE {\n  }\n#endif\n}\nLR_Veneer REGION_VENEER_START REGION_VENEER_SIZE {\n  ER_Veneer REGION_VENEER_START REGION_VENEER_SIZE {\n    *(Veneer$$CMSE)\n  }\n}\n\\endcode\n\nThe partition_gen.h header file contains Configuration Wizard annotation so that it can be viewed in a graphical window:\n\n\\image html partition_h_l5.png\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTESAML11 Microchip SAML11\n\nThis single processor demo application shows how to do the \\ref UseCase_TrustZone. It is split into a secure and non-secure\npart. Using CMSIS-Zone, it generates:\n - A header file that contains \\#defines to control the various linker scatter files (and might be used in other parts of the\n   application).\n - The SystemIsolation_Config.c header file that contains memory protection controller (MPC) and peripheral protection\n   controller (PPC) and related interrupt setup.\n - The partition_gen.h header file that contains the secure attribution unit (SAU) setup and the NVIC configuration for secure/non-secure.\n\nThe application itself shows how to implement calls between the secure and the non-secure part.\n\n\n\\section zTESAML11_Eclipse Using the CMSIS-Zone project\n\n  - \\ref zTExImport \"Import\" the project \"Examples\\SAML11\\Zone\" into the CMSIS-Zone utility\n  - \\ref zTProjEx \"Open\" the SAML11.azone file\n  - \\ref zTUIGenerate \"Generate\" the related output files\n\nThe SAML11.azone file of that project has the following configuration settings:\n  - \\ref zTUICreate \"Added the zones\" \\c sApp and \\c nsApp\n  - \\ref zTUIMemAdd \"Created the memory regions\" \\c APP_NS, \\c APP_S, \\c APP_NSC, \\c DATA_NS, \\c DATA_S, \\c RAM_NS, and \\c RAM_NS\n  - Selected various memory regions and peripherals for using in the different zones:\n    \\image html SAML11_zones.png\n\nThe zones use different Flash and SRAM regions for code and data. To generate the output, click\non the \\ref zTUIGenerate \"Generate\" button in the Zone Editor tool bar. This creates the following files in the \\c ftl_gen\ndirectory:\n\n| Template File        | Generated File   | Description |\n|:---------------------|:-----------------|:-------------|\n| dump_fzone.txt.ftl   | dump_fzone.txt   | Contains the complete model  |\n| flash.dbgconf.ftl    | flash.dbgconf    | Flash algorithm configuration for security settings |\n| flash.dbgconf.lst.ftl| flash.dbgconf.lst| Flash algorithm configuration for security settings |\n| helper.ftlinc        | N/A              | Helper template file with FTL functions. |\n| scatter_ns.sct.ftl   | scatter_ns.sct   | Example scatter file for non-secure zone. |\n| scatter_s.sct.ftl    | scatter_s.sct    | Example scatter file for secure zone. |\n\nThese files can be used in any IDE to create the final application. In the following, the usage in Arm Keil MDK is described.\n\n\\section zTESAML11_MDK Using the MDK project\n\nThe example project can be loaded, built and debugged in µVision by performing the following steps:\n\n-# Navigate to Examples/SAML11/MDK\n-# Open the multi-project workspace NoRTOS.uvmpw\n-# Run the batch build in MDK. Both projects, sApp and nsApp need to be compiled in order.\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zTEMCB400 Keil MCBSTM32F400 Evaluation Board\n\nThis single processor demo application shows how to do the \\ref UseCase_MPU. Using CMSIS-Zone, it generates:\n - A header file that contains \\#defines to control the various linker scatter files (and might be used in other parts of the\n   application).\n - The MPU configuration table source and header files. These contain MPU register settings used during thread switching\n   to update accessible memory regions.\n\nThe application itself shows how to isolate network stack threads from the user application.\n\n\n\\section zTEMCB400_Eclipse Using the CMSIS-Zone project\n\n  - \\ref zTExImport \"Import\" the project \"Examples\\MCBSTM32F400\\Zone\" into the CMSIS-Zone utility\n  - \\ref zTProjEx \"Open\" the MCBSTM32F400.azone file\n  - \\ref zTUIGenerate \"Generate\" the related output files\n\nThe MCBSTM32F400.azone file of that project has the following configuration settings:\n  - Project mode is set to \\c Execution.\n  - \\ref zTUICreate \"Added the zones\" \\c Net, \\c Main, \\c RTX, \\c Blinky, \\c Timer, \\c Idle\n  - \\ref zTUIMemAdd \"Created the memory regions\" \\c CODE, \\c RAM_SHARED, \\c RAM_NET, \\c RAM_MAIN, \\c RAM_PRIVILEGED,\n    \\c RAM_EVR, \\c RAM_BSD, \\c RAM_LED, \\c RAM_ADC, \\c RAM_TIMER, and \\c RAM_IDLE\n  - Selected various memory regions and peripherals for using in the different zones:\n    \\image html MCB400_zones.png\n\nThe zones use common Flash region for all the application code but different SRAM regions to segregate thread data.\nTo generate the output, click on the \\ref zTUIGenerate \"Generate\" button in the Zone Editor tool bar. This creates\nthe following files in the \\c ftl_gen directory:\n\n| Template File        | Generated File   | Description |\n|:---------------------|:-----------------|:-------------|\n| dump_fzone.txt.ftl   | dump_fzone.txt   | Contains the complete model  |\n| helper.ftlinc        | N/A              | Helper template file with FTL functions. |\n| mem_layout.h.ftl     | mem_layout.h     | Header file that contains the memory region definitions, for example for the linker scatter file. |\n| mputable.c.ftl       | mputable.c       | MPU Table data definition. |\n| mputable.h.ftl       | mputable.h       | MPU Table data declaration. |\n| scatter.sct.ftl      | scatter.sct      | Example scatter file for MPU protection. |\n\n\nThese files can be used in any IDE to create the final application. In the following, the usage in Arm Keil MDK is described.\n\n\\section zTEMCB400_MDK Using the MDK project\n\nThe example project can be loaded, built and debugged in µVision by performing the following steps:\n\n-# Navigate to Examples/MCBSTM32F400/MDK\n-# Open the project workspace Blinky_Net.uvprojx\n-# Optional: Update the generated files by executing the copy_gen.bat script.\n-# Run the build in MDK.\n\n\n\\section zTEMCB400_MDK_Setup MDK project setup\n\nThe projects Blinky_Net use the files generated in CMSIS-Zone as follows:\n\n| File                       | Description |\n|:---------------------------|:------------|\n| mem_layout.h               | Input for the linker scatter files. |\n| mputable.c                 | MPU Table data definition. |\n| mputable.h                 | MPU Table data declaration. |\n| scatter.sct                | Initial template for scatter file. |\n\n\\subsection zTEMCB400_hwsScatter scatter.sct\n\nAs explained previously, the \\#defines in \\c mem_layout.h can be used to create generic scatter files that are easy\nto update once changes in the CMSIS-Zone project happen. Using the \\b mem_layout.h file from CMSIS-Zone, the following\nscatter file is used in the \\c Blinky_Net project, which is based on the generated scatter file template (scatter.sct):\n\n\\code\n#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc\n\n#include \"mem_layout.h\"\n\nLR_CODE REGION_CODE_START REGION_CODE_SIZE {\n  ER_CODE REGION_CODE_START REGION_CODE_SIZE {\n    *.o (RESET,+FIRST)\n    * (InRoot$$Sections)\n    .ANY (+RO, +XO)\n  }\n  RW_RAM_PRIVILEGED REGION_RAM_PRIVILEGED_START REGION_RAM_PRIVILEGED_SIZE {\n     Net_Config.o (.bss.os.*.cb)\n    .ANY (+RW +ZI)\n  }\n  RW_RAM_SHARED REGION_RAM_SHARED_START REGION_RAM_SHARED_SIZE {\n    system_stm32f4xx.o (.data.SystemCoreClock)\n;   *.o (.data.shared)\n    *.o (.bss.shared)\n  }\n  RW_RAM_EVR REGION_RAM_EVR_START UNINIT REGION_RAM_EVR_SIZE {\n    EventRecorder.o (+ZI)\n  }\n  RW_RAM_BSD REGION_RAM_BSD_START REGION_RAM_BSD_SIZE {\n    bsd.o (+RW +ZI)\n  }\n  RW_RAM_NET REGION_RAM_NET_START REGION_RAM_NET_SIZE {\n    *Net*.lib (+RW +ZI)\n    Net_Config.o (.bss*)\n    emac_stm32f4xx.o (+RW +ZI)\n    phy_ksz8081rna.o (+RW +ZI)\n    phy_st802rt1.o (+RW +ZI)\n  }\n  RW_RAM_TIMER REGION_RAM_TIMER_START REGION_RAM_TIMER_SIZE {\n    timer.o (+RW +ZI)\n    *.o (.bss.os.thread.stack.rtx.timer)\n  }\n  RW_RAM_ADC REGION_RAM_ADC_START REGION_RAM_ADC_SIZE {\n    adc.o (+RW +ZI)\n    adc_mcbstm32f400.o (+RW +ZI)\n  }\n  RW_RAM_LED REGION_RAM_LED_START REGION_RAM_LED_SIZE {\n    led.o (+RW +ZI)\n  }\n  RW_RAM_MAIN REGION_RAM_MAIN_START REGION_RAM_MAIN_SIZE {\n    app.o (+RW +ZI)\n  }\n  RW_RAM_IDLE REGION_RAM_IDLE_START REGION_RAM_IDLE_SIZE {\n    RTX_Config.o (+RW +ZI)\n    *.o (.bss.os.thread.stack.rtx.idle)\n  }\n}\n\\endcode\n\nThe data segments of segregated software components have been allocated to distinct memory regions.\n*/"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/Zone/src/XML_Format.txt",
    "content": "/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page zoneFormat Zone Description Format \n\nThe <b>Zone Description Format</b> is a tool agnostic storage format and is split into:\n\n - <b>Resource File (*.rzone)</b> that describes the system resources available. \n - <b>Assignment File (*.azone)</b> that describes the resource partitioning.\n\nThe combination of both <b>Resource File</b> and <b>Assignment File</b> can be used to create a new derived <b>Resource File</b> that only\ncontains the resources available for this project. It is therefore possible to split the resources incrementally as needed.\n\nA <b>Resource File (*.rzone)</b> can therefore describe: \n - A complete embedded system including device with one or more processors, external memory and/or external peripheral components.\n - TrustZone definition and initial setting for Secure Attribute Unit\n - A resource partition for an independent software project (i.e. boot loader, user application, secure partition) that implement the application for the system.\n\nAn <b>Assignment File (*.azone)</b> allows to specify either:\n - The partitioning of a system into multiple independent software projects.\n - The configuration of a Memory Protection Unit (MPU) for functional segregation of a software project. \n \n\\note It is impossible to use a single <b>Assignment File</b> for both, partitioning of software projects and MPU configuration.\n\n\n\\section XML_Format_Schema Overall XML structure\n\nThe CMSIS-Zone utility uses two XML files to store system and configuration information. The structure these XML files\nis described with schema files that are located in the ARM.CMSIS pack in the directory .\\\\CMSIS\\\\Utilities.\n\n File type  | Schema file   | Description\n:-----------|:--------------|:-------------\n\\ref rzone \"*.rzone\"     | rzone.xsd     | Stores the system resources (processors, memory, peripherals) available.\n\\ref azone \"*.azone\"     | azone.xsd     | Stores the system partitioning which includes assignments and memory splits for a related .rzone file.\n*.fzone     | fzone.xsd     | CMSIS-Zone data input file for FreeMarker as explained in \\ref GenDataModel.\n\n\\note It is important to understand the relationship between *.rzone and *.azone files. While the *.rzone file contains all\nthe information about the available resources in a system or sub-system, the *.azone file contains all the information about\nthe system partitioning. If the *.rzone file changes (for example because the partitioning of a sub-system\nhas changed), you will not loose the work done on the partitioning of that sub-system. If resources are removed, the\n\\ref zTGUI will notify you about this and you can make the required changes.\n\n\n\\anchor rzone\nTop-level .rzone XML elements\n=============================\n - \\subpage xml_rzone_pg \"<rzone>\" is the root element of the *.rzone file.\n - \\ref xml_creator \"<creator>\" describes the creation for this *.rzone file.\n - \\ref xml_device \"<device>\" describes the device that is part of the system. It may contain one or more processors.\n - \\ref xml_resources \"<resources>\" describes the memory and peripheral resources of the system.\n\n\nStructure of .rzone XML file\n----------------------------\n\n\\code\n<rzone>                  // root element of system zone file\n  <creator>              // describes how this rzone file was created\n  \n  <device>               // device information\n    <package/>           // software pack that defines device\n    <processor/>         // processor information\n  </device>\n  \n  <resources>            // physical resources off-chip \n    <sau_init>           // fixed SAU settings required for system\n      <region/>          // region setting for SAU\n    </sau_init>\n\t\n    <memories>           // memories section  \n      <memory>           // memory resource\n      <mpc>              // memory protection controller information\n    </memories>\n    \n    <peripherals>        // peripheral resources off-chip\n      { <group> }        // peripheral group (optional)\n      <peripheral>       // peripheral description\n         <slot>          // optional slot description (pin or DMA channel)\n           <interrupt/>  // optional interrupts for slot\n           <setup/>      // optional register setup for slot\n\t\t </slot>\n         <interrupt/>    // optional interrupts for peripheral\n         <setup/>        // optional register setup for peripheral\n      </peripheral>\n      { </group> }       // peripheral group (optional)\n    </peripherals>\n  </resources>\n</rzone>\n\\endcode\n\n\\anchor azone\nTop-level .azone XML elements\n=============================\n - \\subpage xml_azone_pg \"<azone>\" is the root element of the *.azone file.\n - \\ref xml_configure \"<configure>\" controls the behavior of the CMSIS-Zone utility (project or MPU assignments).\n - \\ref xml_partition \"<partition>\" defines memory partitions that split available system memory.\n - \\ref xml_zones \"<zones>\" defines the assignment of memory, block, and peripherals.\n\n\\code\n<azone>\n  <rzone>                // Refers related .rzone file\n  <configure>            // CMSIS-Zone utility UI behavior\n  \n  <partition>            // memory partition information\n    <memory>             // memory split information \n  </partition>\n  \n  <zones>                // zone assignments\n    <zone>               // project zone name\n      <assign>           // used peripheral or memory\n        <interrupt/>     // for peripherals optional interrupt usage\n      </assign>\n    </zone>\n  </zones>\n</azone>\n\\endcode\n\n\\anchor security\nSecurity Type\n=============\nThe attribute \\em security defines the security setting for a memory or peripheral region.\nOnly one of the settings is allow:\n - \\<empty\\> security not defined (default) \n - 'n'  non-secure\n - 'c'  secure on non-secure callable  \n - 's'  secure\n \n\\anchor access\nAccess Type\n===========\nThe attribute \\em access defines the access permission for a memory or peripheral region.\nMultiple settings are allow:\n - 'r'  read  \n - 'w'  write\n - 'x'  execute\n - 'p'  peripheral</td>\n\n\\anchor privilege\nPrivilege Type\n==============\nThe attribute \\em privilege defines the privilege level that is required for memory/peripheral access or code execution in a MPU zone.\nOnly one of the settings is allow:\n  - \\<empty\\> privilege level not specified\n  - 'u' unprivileged level\n  - 'p' privileged level\n*/\n\n/**************************************************************************************************/\n/**\n\\page xml_rzone_pg /rzone element\n\nThe \\ref xml_rzone_pg element is the root element of the .rzone file which describes the resources (processors, memory, peripherals) available.\n\n\n<table class=\"cmtable\" summary=\"Element: rzone\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>root</td>\n    <td colspan=3>Document root</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>schemaVersion</td>\n    <td>CMSIS-Zone schema version used for describing the *.rzone file.</td>\n    <td>VersionType</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>xmlns:xs</td>\n    <td>Is set to: \\token{\"http://www.w3.org/2001/XMLSchema-instance\"} to indicate compliance to the XML format.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>xs:noNamespaceSchemaLocation</td>\n    <td>File name of the schema file. For example, \\token{\"rzone.xsd\"}.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\subpage xml_creator \"creator\"</td>\n    <td>Specifies how a derived .rzone file was created.</td>\n    <td>CreatorType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>\\subpage xml_device \"device\"</td>\n    <td>Device that includes one or more processing element (PE).</td>\n    <td>DeviceType</td>\n    <td>1..1 </td>\n  </tr>\n  <tr>\n    <td>\\subpage xml_resources \"resources\"</td>\n    <td>Physical resources (memory and peripherals) that are available in the system.</td>\n    <td>SResourceType</td>\n    <td>1..1 </td>\n  </tr>\n</table>\n*/\n\n\n/**************************************************************************************************/\n/**\n\\page xml_creator /rzone/creator element\n\nThe \\ref xml_creator specifies how a derived .rzone file was created.\n\n<table class=\"cmtable\" summary=\"Element: device\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_rzone_pg \"rzone\"</td>\n    <td colspan=3>\\ref xml_rzone_pg</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>tool</td>\n    <td>Identification of the tool that generated this *.rzone file.  (i.e. \"CMSIS-Zone V1.1.0\")</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>rzone</td>\n    <td>Name of the .rzone file which contained top level resources.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>azone</td>\n    <td>Name of the .azone file which contained related assignments.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the zone.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" setting for this *.rzone file.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n\n</table>\n*/\n\n\n/**************************************************************************************************/\n/**\n\\page xml_device /rzone/device element\n\nThe \\ref xml_device specifies the device of the system that integrates the processors.\n\n<table class=\"cmtable\" summary=\"Element: device\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_rzone_pg \"rzone\"</td>\n    <td colspan=3>\\ref xml_rzone_pg</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>Dvendor</td>\n    <td>The devices vendor identifier.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>Dname</td>\n    <td>Specifies the name of the device. Only alphabetical characters, decimal digits, '-' and '_' are allowed.</td>\n    <td>RestrictedString</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the device.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_package \"package\"</td>\n    <td>Optional reference to the Software Pack this device is provided by.</td>\n    <td>complexType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_processor \"processor\"</td>\n    <td>Processing elements and associated features embedded in the device.</td>\n    <td>complexType</td>\n    <td>1..*</td>\n  </tr>\n</table>\n\n\n\\section xml_package /rzone/device/package element\n\nThe \\ref xml_package refers to the Software Pack that provides the Device Family Pack (DFP) for the \\ref xml_device \"device\". \n\n<table class=\"cmtable\" summary=\"Element: package\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_device \"device\"</td>\n    <td colspan=3>\\ref xml_device</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The unique pack name.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>url</td>\n    <td>The URL the pack can be obtained from.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>vendor</td>\n    <td>The pack vendor name.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>version</td>\n    <td>The pack version.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the Software Pack.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>    \n</table>\n\n\n\\section xml_processor /rzone/device/processor element\n\nThe \\ref xml_processor defines the processing elements integrated in the \\ref xml_device \"device\".\nThe information in this element is identical with CMSIS-Pack, except that it provides an additional 'info' attribute.\n\n<table class=\"cmtable\" summary=\"Element: processor\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_device \"device\"</td>\n    <td colspan=3>\\ref xml_device</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>Pname</td>\n    <td>Processor identifier. This attribute <b>is mandatory for devices that embed multiple processors</b>. \n    </td>\n    <td>RestrictedString</td>\n    <td>required for all multi-core devices</td>\n  </tr>\n  <tr>\n    <td>Punits</td>\n    <td>Specifies the number of processor units in a symmetric multi-processor core (MPCore). Defaults to single-core CPU (\\token{1}) when left empty.</td>\n    <td>InstancesType</td>\n    <td>required for all multi-core devices</td>\n  </tr>\n  <tr>\n    <td>Dcore</td>\n    <td>Specifies the processor core.</td>\n    <td>DcoreEnum</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>Dfpu</td>\n    <td>Specifies whether a hardware Floating Point Unit is present in the processor.</td>\n    <td>DfpuEnum</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>Dmpu</td>\n    <td>Specifies whether a Memory Protection Unit is present in the processor.</td>\n    <td>DmpuEnum</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>Dtz</td>\n    <td>Specifies whether an Armv8-M based device implements TrustZone.</td>\n    <td>DtzEnum</td>\n    <td>required for ARMv8-M based devices</td>\n  </tr>\n  <tr>\n    <td>Ddsp</td>\n    <td>Specifies whether a device supports the DSP instructions set.</td>\n    <td>DdspEnum</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>Dendian</td>\n    <td>Specifies the endianess of the processor.</td>\n    <td>DendianEnum</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>Dclock</td>\n    <td>Specifies the max clock frequency of the processor subsystem</td>\n    <td>xs:unsignedInt</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>DcoreVersion</td>\n    <td>Hardware revision of the processor core</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>DnumInterrupts</td>\n    <td>Number of NVIC interrupt sources available to the processor core (excludes exception vectors).</td>\n    <td>NonNegativeInteger</td>\n    <td>required for Armv8-M with TrustZone</td>\n  </tr>\n  <tr>\n    <td>DnumMpuRegions</td>\n    <td>Number of regions in the Memory Protection Unit (MPU) of the processor core. (Default: 8 when Dmpu is enabled)</td>\n    <td>NonNegativeInteger</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>DnumSauRegions</td>\n    <td>Number of regions in the Security Attribution Unit (SAU) of the processor core.</td>\n    <td>NonNegativeInteger</td>\n    <td>required for Armv8-M with TrustZone</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the processor.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n</table>\n\n*/\n\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page xml_resources /rzone/resources element\n\nThe \\ref xml_resources defines the memory and peripheral regions that are available.\n\n<table class=\"cmtable\" summary=\"Element: resources\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_rzone_pg \"rzone\"</td>\n    <td colspan=3>\\ref xml_rzone_pg</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\subpage xml_sau_init \"sau_init\"</td>\n    <td>Fixed SAU settings required for this system, i.e. to access peripherals.</td>\n    <td>SauInitType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>\\subpage xml_memories \"memories\"</td>\n    <td>List of all memory regions available in this system. Some memory region might restrict the availability to specific processors.</td>\n    <td>complexType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>\\subpage xml_peripherals \"peripherals\"</td>\n    <td>List of all peripherals available for this system.</td>\n    <td>complexType</td>\n    <td>0..1</td>\n  </tr>\n</table>\n\n*/\n\n/**************************************************************************************************/\n/**\n\\page xml_sau_init /rzone/resources/sau_init element\n\nThe \\ref xml_sau_init specifies fixed Secure Attribute Unit (SAU) settings required for this system, for example a configuration that is required to access peripherals.\n\n<table class=\"cmtable\" summary=\"Element: sau_init\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_resources \"resources\"</td>\n    <td colspan=3>\\ref xml_resources</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_si_region \"region\"</td>\n    <td>Region settings for the SAU.</td>\n    <td>complexType</td>\n    <td>1..*</td>\n  </tr>\n</table>\n\n\n\\section xml_si_region /rzone/sau_init/region element\n\nThe \\ref xml_si_region contains the region setting for SAU initialization. \n\n<table class=\"cmtable\" summary=\"Element: region\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_sau_init \"sau_init\"</td>\n    <td colspan=3>\\ref xml_sau_init</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>Pname</td>\n    <td>The processor that requires this setting. If omitted all processors get this setting.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>start</td>\n    <td>The logical start address for the region.</td>\n    <td>NonNegativeInteger</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>size</td>\n    <td>The size for the region.</td>\n    <td>NonNegativeInteger</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" attributes for this memory region.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of region setting (for comments in source code).</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n</table>\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page xml_memories /rzone/resources/memories element\n\nThe \\ref xml_memories contains:\n  - a list of all memory regions available in this system.\n  - a list of all Memory Protection Controllers (MPC) in this system.  \nSome memory region or MPC might restrict the availability to specific processors.\n\n\n<b>Example</b>\n\\code\n<resources>\n  <memories>\n    <memory name=\"ExtMem1\"    start=\"0x00000000\" physical=\"0x00000000\" size=\"0x00010000\" access=\"rwx\" security=\"\"  type=\"RAM\" info=\"External memory 1 / remap\" external=\"true\" />\n    <memory name=\"Flash_NS\"   start=\"0x08000000\"                       size=\"0x00080000\" access=\"rx\"  security=\"\"  type=\"ROM\" info=\"Flash Memory (non secure)\"                 />\n    <mpc    name=\"IOTKIT_MPCSSRAM0\" start=\"0x08000000\"                 size=\"0x00100000\" type=\"sp\"    blk_size=\"0x20000\"      info=\"MPC for extended Flash\"                    />\n    <memory name=\"Flash_S\"    start=\"0x0c000000\" physical=\"0x08001000\" size=\"0x00080000\" access=\"rx\"  security=\"c\" type=\"ROM\" info=\"Flash Memory (secure)\"                     />\n\n    <memory name=\"SRAM1_C_NS\" start=\"0x0A000000\"                       size=\"0x00030000\" access=\"rwx\" security=\"\"  type=\"RAM\" info=\"SRAM1 Code (non secure)\"   />\n    <memory name=\"SRAM1_C_S\"  start=\"0x0E000000\" physical=\"0x0A000000\" size=\"0x00030000\" access=\"rwx\" security=\"c\" type=\"RAM\" info=\"SRAM1 Code (secure)\" linker_control=\"*sram1\" />\n    <memory name=\"SRAM1_S\"    start=\"0x30000000\" physical=\"0x0A000000\" size=\"0x00030000\" access=\"rw\"  security=\"s\" type=\"RAM\" info=\"SRAM1 (secure)\"            />\n    <memory name=\"SRAM1_NS\"   start=\"0x20000000\" physical=\"0x0A000000\" size=\"0x00030000\" access=\"rw\"  security=\"\"  type=\"RAM\" info=\"SRAM1 (non secure)\"        />\n\n    <memory name=\"FMC_Bank1\"  start=\"0x60000000\"                       size=\"0x00000000\" access=\"rw\" security=\"\"   type=\"RAM\" info=\"Memory Controller bank 1\"  />\n  </memories>\n  :\n</resources>\n\\endcode\n\n\n<table class=\"cmtable\" summary=\"Element: memories\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_resources \"resources\"</td>\n    <td colspan=3>\\ref xml_resources</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_rmemory \"memory\"</td>\n    <td>Lists a logical memory region with physical mapping. Memory might restricted to processors, access, or security modes.</td>\n    <td>complexType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_rmpc \"mpc\"</td>\n    <td>Specifies a Memory Protection Controller (MPC) for a physical address range.</td>\n    <td>complexType</td>\n    <td>0..1</td>\n  </tr>\n</table>\n\n\\section xml_rmemory /rzone/resources/memories/memory element\n\nThe \\ref xml_rmemory lists a logical memory region with physical mapping. Memory might restricted to processors, access, or security modes.\n\n<table class=\"cmtable\" summary=\"Element: memory\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_memories \"memories\"</td>\n    <td colspan=3>\\ref xml_memories</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name of this memory region which must be unique in this *.rzone file.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>type</td>\n    <td>The type of memory in this region (\"RAM\" or \"ROM\").</td>\n    <td>PhysicalTypeEnum</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>start</td>\n    <td>The logical start address of the memory region in the address map.</td>\n    <td>NonNegativeInteger</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>physical</td>\n    <td>The physical start address of the memory region in the address map.  If physical is not specified the start address value is used.</td>\n    <td>NonNegativeInteger</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>size</td>\n    <td>The size of the memory region in bytes.</td>\n    <td>NonNegativeInteger</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>access</td>\n    <td>\\ref access \"Access\" permissions for this memory region.</td>\n    <td>\\ref access \"AccessType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" attributes for this memory region.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>\\ref privilege \"Privilege level\" for this memory region.</td>\n    <td>\\ref privilege \"PrivilegeType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>startup</td>\n    <td>\"1\" specifies that this region is used for the startup code of the application. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>uninit</td>\n    <td>\"1\" specifies that this region is not zero initialized during startup. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>shared</td>\n    <td>\"1\" specifies that this region is used by multiple zones. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>dma</td>\n    <td>\"1\" specifies that this region is accessed by a DMA controller. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>external</td>\n    <td>\"1\" specifies that this region is provided by an external component that is not part of the device. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>Pname</td>\n    <td>The processor that can access this memory region. If omitted all processors of the system have access.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the memory region.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n  <tr>\n    <td>linker_control</td>\n    <td>Linker control settings for the memory region.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n</table>\n\n\n\\section xml_rmpc /rzone/resources/memories/mpc element\n\nThe \\ref xml_rmpc element specifies a Memory Protection Controller (MPC) for a physical memory address region.  \nThe MPC region must not necessarily overlap a physical memory space which means it can be larger or smaller.\n\n<table class=\"cmtable\" summary=\"Element: mpc\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_memories \"memories\"</td>\n    <td colspan=3>\\ref xml_memories</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The base register name of the MPC.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>start</td>\n    <td>The physical start address of the memory address region that is protected by the MPC.</td>\n    <td>NonNegativeInteger</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>size</td>\n    <td>The size of the memory address region in bytes.</td>\n    <td>NonNegativeInteger</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>blk_size</td>\n    <td>The size (in bytes) of each memory block.  This value is also the alignment requirement for the memory blocks.\n\t    The number of LUT bits is: <i>memory size</i> / <i>blk_size</i>.</td>\n    <td>NonNegativeInteger</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>type</td>\n    <td>Specifies the permissions that the MPC verifies for the memory access:\\n\n\t  - type=\"s\" : (default) only the Secure attribute is verified.\n\t  - type=\"p\" : only the Privileged attribute is verified.\n\t  - type=\"sp\" : both the Secure are Privileged attribute are verified.\n    <td>MpcTypeEnum</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the MPC region.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n</table>\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page xml_peripherals /rzone/resources/peripherals element\n\nThe \\ref xml_peripherals contains a list of all peripherals available in the system. It also restricts the availability to specific processors or security modes.\n\n<b>Example</b>\n\\code\n<resources>\n  :\n  <peripherals>\n    <peripheral name=\"ADC0\" start=\"0x40080000\" size=\"0x1000\" access=\"rwp\" info=\"Analog/Digital Converter 0 (12-bit)\"/>\n    :\n    <group name=\"TIM\" info=\"Timer Group\">\n      <peripheral name=\"TIM1\"      start=\"0x40012c00\" start_s=\"0x50012c00\" size=\"0x400\" access=\"rw\">\n        <interrupt name=\"TIM1_BRK\" irqn=\"41\" info=\"Timer 1 Break\"/>\n        <interrupt name=\"TIM1_UP\"  irqn=\"42\" info=\"Timer 1 Update\"/>\n        <interrupt name=\"TIM1_BRK\" irqn=\"43\" info=\"Timer 1 Trigger and Commutation\"/>\n        <interrupt name=\"TIM1_CC\"  irqn=\"44\" info=\"Timer 1 Capture and Compare\"/>\n      </peripheral>\n      <peripheral  name=\"TIM2\"    start=\"0x40000000\" start_s=\"0x50000000\" size=\"0x400\" access=\"rw\">\n        <interrupt name=\"TIM2\"    irqn=\"45\" info=\"Timer2 Global Interrupt\"/>\n      </peripheral>\n    </group>\n  </peripherals>\n</resources>\n\\endcode\n&nbsp;\n\n<table class=\"cmtable\" summary=\"Element: peripherals\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_resources \"resources\"</td>\n    <td colspan=3>\\ref xml_resources</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_group \"group\"</td>\n    <td>Logical grouping of peripherals.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_peripheral \"peripheral\"</td>\n    <td>Peripheral definitions.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n</table>\n\n\\section xml_group /rzone/resources/peripherals/group element\n\nThe \\ref xml_group can be used to logically group peripherals according to functionality or bus topology.\n\n<table class=\"cmtable\" summary=\"Element: group\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_peripherals \"peripherals\"</td>\n    <td colspan=3>\\ref xml_peripherals</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name for the peripheral group must be be unique within a processor (specified by Pname).</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>start</td>\n    <td>The logical start address of the peripheral group in both secure and non-secure mode.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>start_s</td>\n    <td>The logical start address of the peripheral group in secure mode only.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>physical</td>\n    <td>The physical start address of the peripheral group (in case that peripheral is shared in multi-processor system on different address).</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>size</td>\n    <td>The physical size of the peripheral group in bytes.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>shared</td>\n    <td>\"1\" specifies that this peripheral group is used by multiple zones. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>dma</td>\n    <td>\"1\" specifies that this peripheral group is accessed by a DMA controller. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>external</td>\n    <td>\"1\" specifies that this peripheral group is provided by an external component that is not part of the device. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>Pname</td>\n    <td>The processor that can access this peripheral group. If omitted all processors of the system have access.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>access</td>\n    <td>\\ref access \"Access\" permissions for this peripheral group.</td>\n    <td>\\ref access \"AccessType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" attributes for this peripheral group.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>\\ref privilege \"Privilege level\" for this peripheral group.</td>\n    <td>\\ref privilege \"PrivilegeType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the peripheral group.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_peripheral \"peripheral\"</td>\n    <td>Peripheral definitions.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_p_setup \"setup\"</td>\n    <td>Setup information for the peripheral group.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n</table>\n\n\\section xml_peripheral /rzone/resources/peripherals/.../peripheral element\n\nThe \\ref xml_peripheral is used to define an address mapping for one peripheral.\n\n<table class=\"cmtable\" summary=\"Element: peripheral\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_peripherals \"peripherals\"</td>\n    <td colspan=3>\\ref xml_peripherals</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_group \"group\"</td>\n    <td colspan=3>\\ref xml_group</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name of the peripheral. The combination group / name must be be unique within a processor (specified by Pname).</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>start</td>\n    <td>The logical start address of the peripheral in both secure and non-secure mode.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>start_s</td>\n    <td>The logical start address of the peripheral in secure mode only.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>physical</td>\n    <td>The physical start address of the peripheral (in case that peripheral is shared in multi-processor system on different address).</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>offset</td>\n    <td>Specifies an offset for the peripheral for the \\ref xml_group values. The values \\em start, \\em start_s, \\em physical are taken from the \\ref xml_group element if not overwritten.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>size</td>\n    <td>The physical size of the peripheral in bytes.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>shared</td>\n    <td>\"1\" specifies that this peripheral group is used by multiple zones. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>dma</td>\n    <td>\"1\" specifies that this peripheral group is accessed by a DMA controller. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>external</td>\n    <td>\"1\" specifies that this peripheral is provided by an external component that is not part of the device. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>Pname</td>\n    <td>The processor that can access this peripheral. If omitted all processors of the system have access.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>access</td>\n    <td>\\ref access \"Access\" permissions for this peripheral.</td>\n    <td>\\ref access \"AccessType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" attributes for this peripheral.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>\\ref privilege \"Privilege level\" for this peripheral.</td>\n    <td>\\ref privilege \"PrivilegeType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the peripheral.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n  <tr>\n    <td>slot_name</td>\n    <td>Attribute name of the slot (i.e. Pins or Channels). Used in context menu or dialog heading.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n  <tr>\n    <td>slot_type</td>\n    <td>Specifies the values that are configured for the slots:\\n\n\t  - type=\"s\" : (default) only the secure attribute is configured.\n\t  - type=\"p\" : only the Privileged attribute is configured.\n\t  - type=\"sp\" : both the Secure are Privileged attribute are configured.\n    <td>SlotTypeEnum</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_slot \"slot\"</td>\n    <td>Configuration of security or privileged attribute for slots (typically channels or pins).</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_interrupt \"interrupt\"</td>\n    <td>Interrupts generated by this peripheral.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_p_setup \"setup\"</td>\n    <td>Setup information for the peripheral.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n</table>\n\n\n\\section xml_slot /rzone/resources/peripherals/.../peripheral/slot element\n\nThe \\ref xml_slot is specific to a channel or pin of a peripheral. It specifies the configuration for interrupts or setup registers that belong to that slot (which is typically a channels or pins).\n\n<table class=\"cmtable\" summary=\"Element: interrupt\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_peripheral \"peripheral\"</td>\n    <td colspan=3>\\ref xml_peripheral</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name of the slot (typically channel or pin name).</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>secure</td>\n    <td>Setting of the secure attribute (default=\"0\").</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>Setting of the privilege attribute (default=\"0\").</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_interrupt \"interrupt\"</td>\n    <td>Interrupts generated by this peripheral.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_p_setup \"setup\"</td>\n    <td>Setup information for the peripheral.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n</table>\n\n\n\\section xml_interrupt /rzone/resources/peripherals/.../interrupt element\n\nThe \\ref xml_interrupt defines the interrupts that are generated by a peripheral or slot.\n\n<table class=\"cmtable\" summary=\"Element: interrupt\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_peripheral \"peripheral\"</td>\n    <td colspan=3>\\ref xml_peripheral</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name of the interrupt.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>irqn</td>\n    <td>The interrupt number.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the peripheral.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n</table>\n\n\\section xml_p_setup /rzone/resources/peripherals/.../setup element\n\nThe \\ref xml_p_setup defines the setup information for this peripheral, slot, or peripheral group. The attributes \\em security and \\em privilege specifies conditions.\nWhen the peripheral is specified for on the the conditions, the \\em value is assigned to the \\em register name (with an optional \\em index).\n\n<table class=\"cmtable\" summary=\"Element: peripheral\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_peripheral \"peripheral\"</td>\n    <td colspan=3>\\ref xml_peripheral</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_group \"group\"</td>\n    <td colspan=3>\\ref xml_group</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name of the register.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>index</td>\n    <td>An index value for the register.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>value</td>\n    <td>The value that should be written to the register when the \\em security or \\em privilege condition matches with the peripheral configuration.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" condition for this setup value.  Security can be \"s\" or \"n\".  When a peripheral matches that security setting the value will be written.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>\\ref privilege \"Privilege level\" condition for this setup value. Privilege can be \"u\" or \"p\".  When a peripheral matches that privilege setting the value will be written. When both Security and Privilege is specified, both conditions must match.</td>\n    <td>\\ref privilege \"PrivilegeType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the setup value.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n</table>\n\n*/\n\n/**************************************************************************************************/\n/**\n\\page xml_azone_pg /azone element\n\nThe \\ref xml_azone_pg element is the root element of the .azone file which stores partitioning of the system or the configuration of a MPU.\n\n<table class=\"cmtable\" summary=\"Root Element: azone\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>root</td>\n    <td colspan=3>Document root</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>schemaVersion</td>\n    <td>CMSIS-Zone schema version used for describing the azone file.</td>\n    <td>VersionType</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>xmlns:xs</td>\n    <td>Is set to: \\token{\"http://www.w3.org/2001/XMLSchema-instance\"} to indicate compliance to the XML format.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>xs:noNamespaceSchemaLocation</td>\n    <td>File name of the schema file. For example, \\token{\"azone.xsd\"}.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\subpage xml_arzone \"rzone\"</td>\n    <td>Reference to rzone file</td>\n    <td>RZoneType</td>\n    <td>0..1</td>\n  </tr>\n  <tr>\n    <td>\\subpage xml_configure \"configure\"</td>\n    <td>Control the operation of the CMSIS-Zone utility</td>\n    <td>ConfigureType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>\\subpage xml_partition \"partition\"</td>\n    <td>Partition information for memory block splits</td>\n    <td>RegionsType</td>\n    <td>0..1 </td>\n  </tr>\n  <tr>\n    <td>\\subpage xml_zones \"zones\"</td>\n    <td>Zone assignments of processor, memory, and peripheral resources</td>\n    <td>ZonesType</td>\n    <td>0..1 </td>\n  </tr>\n</table>\n*/\n\n/**************************************************************************************************/\n/**\n\\page xml_arzone /azone/rzone element\n\nThe \\ref xml_arzone specifies the filename of the related *.rzone file.  If this element is omitted the *.azone and *.rzone file have the same base name.\n\n<b>Example</b>\n\\code\n<rzone name=\"MySystem.rzone\">\n\\endcode\n&nbsp;\n\n<table class=\"cmtable\" summary=\"Element: rzone\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_azone_pg \"azone\"</td>\n    <td colspan=3>\\ref xml_azone_pg</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>Name of the related *.rzone file</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n</table>\n*/\n\n/**************************************************************************************************/\n/**\n\\page xml_configure /azone/configure element\n\nThe \\ref xml_configure allows to control the operation of the CMSIS-Zone utility.\n\n<b>Example</b>\n\\code\n<configure mode=\"MPU\">     // CMSIS-Zone utility UI behavior\n  <type name=\"RAM\"        show=\"1\" select=\"0\" />\n  <type name=\"ROM\"        show=\"0\" select=\"1\" />\n  <type name=\"Peripheral\" show=\"0\" select=\"0\" />\n</configure>\n\\endcode\n&nbsp;\n\n<table class=\"cmtable\" summary=\"Element: configure\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_azone_pg \"azone\"</td>\n    <td colspan=3>\\ref xml_azone_pg</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>mode</td>\n    <td>Operation mode (\"Project\" or \"MPU\")</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_ctype \"type\"</td>\n    <td>UI behavior for memory or peripheral selection depending on the operation \\em mode</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n</table>\n\n\n\n\\section xml_ctype /azone/configure/type element\n\nThe \\ref xml_ctype defines UI behavior of the CMSIS-Zone utility for a memory or peripheral selection  depending on the operation \\em mode.\n\n<table class=\"cmtable\" summary=\"Element: type\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_configure \"configure\"</td>\n    <td colspan=3>\\ref xml_configure</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>Refers item type (\"RAM\", \"ROM\", or \"Peripheral\") that this element specifies.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>show</td>\n    <td>\"0\" specifies that the item type is hidden during configuration in the UI of the CMSIS-Zone utility (default is \"1\").</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>select</td>\n    <td>\"1\" specifies that all resources with the item type are selected  (default is \"0\").</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n</table>\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page xml_partition /azone/partition element\n\nThe \\ref xml_partition contains a list of memory partitions that are created with the CMSIS-Zone utility.\nThese memory partitions are based on parent memory definitions specified by \\ref xml_memories.\n\n<b>Example</b>\n\\code\n  <partition>\n    <memory parent=\"Flash_NS\" name=\"ROM_NS\" offset=\"0x00000000\" size=\"0x40000\" fixed=\"1\" access=\"rx\" info=\"application code\" />\n    <memory parent=\"Flash_S\"  name=\"ROM_S\"  offset=\"0x00040000\" size=\"0x40000\" access=\"x\"  info=\"boot code />\n    <memory parent=\"SRAM1_NS\" name=\"RAM_NS\" offset=\"0x00000000\" size=\"0x20000\" />\n    <memory parent=\"SRAM1_S\"  name=\"RAM_S\"  offset=\"0x00010000\" size=\"0x20000\" />\n  </partition>\n\\endcode\n&nbsp;\n\n<table class=\"cmtable\" summary=\"Element: partition\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_azone_pg \"azone\"</td>\n    <td colspan=3>\\ref xml_azone_pg</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_amemory \"memory\"</td>\n    <td>Defines a new memory sub-region that is related to a parent region in the *.rzone file.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n  <tr>\n    <td>\\ref xml_aperipheral \"peripheral\"</td>\n    <td>Defines a settings for a peripheral.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n</table>\n\n\\section xml_amemory /azone/partition/memory element\n\nThe \\ref xml_amemory defines a new memory sub-region that is related to a parent region in the *.rzone file.\n\n<table class=\"cmtable\" summary=\"Element: memory\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_partition \"partition\"</td>\n    <td colspan=3>\\ref xml_partition</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>parent</td>\n    <td>The name of the parent region in the related *.rzone file.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name of a new memory partition.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>size</td>\n    <td>The physical memory size this block allocates.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>offset</td>\n    <td>The address offset of this memory partition.  If fixed=\"1\" the memory block cannot be re-ordered within the region.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>access</td>\n    <td>\\ref access \"Access\" permissions for this memory block.</td>\n    <td>\\ref access \"AccessType\"</td>\n    <td>optional</td>\n  </tr>\n   <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" attributes for this memory block.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>\\ref privilege \"Privilege level\" for this memory block.</td>\n    <td>\\ref privilege \"PrivilegeType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>startup</td>\n    <td>\"1\" specifies that this region is used for the startup code of the application. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>fixed</td>\n    <td>\"1\" indicates a fixed offset within that region. \"0\" (default) allows to re-arrange the block within the region.</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>uninit</td>\n    <td>\"1\" specifies that this region is not zero initialized during startup. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>shared</td>\n    <td>\"1\" specifies that this region is used by multiple zones. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>dma</td>\n    <td>\"1\" specifies that this region is accessed by a DMA controller. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the memory block.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n  <tr>\n    <td>linker_control</td>\n    <td>Linker control settings for the memory region.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n</table>\n\n\\section xml_aperipheral /azone/partition/peripheral element\n\nThe \\ref xml_aperipheral defines settings for a peripheral in a related *.rzone file.\n\n<table class=\"cmtable\" summary=\"Element: peripheral\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_partition \"partition\"</td>\n    <td colspan=3>\\ref xml_partition</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name of the peripheral. The combination group / name must be be unique within a processor (specified by Pname).</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>group</td>\n    <td>The group name of the peripheral. The combination group / name must be be unique within a processor (specified by Pname).</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>start</td>\n    <td>The logical start address of the peripheral in both secure and non-secure mode.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>start_s</td>\n    <td>The logical start address of the peripheral in secure mode only.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>shared</td>\n    <td>\"1\" specifies that this peripheral group is used by multiple zones. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>dma</td>\n    <td>\"1\" specifies that this peripheral group is accessed by a DMA controller. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>external</td>\n    <td>\"1\" specifies that this peripheral is provided by an external component that is not part of the device. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>access</td>\n    <td>\\ref access \"Access\" permissions for this peripheral.</td>\n    <td>\\ref access \"AccessType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" attributes for this peripheral.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>\\ref privilege \"Privilege level\" for this peripheral.</td>\n    <td>\\ref privilege \"PrivilegeType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_aslot \"slot\"</td>\n    <td>Defines a settings for a slot.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n</table>\n\n\\section xml_aslot /azone/partition/peripheral/slot element\n\nThe \\ref xml_aslot defines settings for a slot in a related *.rzone file.\n\n<table class=\"cmtable\" summary=\"Element: slot\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_aperipheral \"peripheral\"</td>\n    <td colspan=3>\\ref xml_aperipheral</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name of the slot. The combination group / peripheral / name must be be unique within a processor (specified by Pname).</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>secure</td>\n    <td>Overwrites the setting of the secure attribute in the *.rzone file.</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>Overwrites the setting of the privilege attribute in the *.rzone file.</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n</table>\n\n\n*/\n\n/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/\n/**\n\\page xml_zones /azone/zones element\n\nThe \\ref xml_zones contains all zone definitions.\n\n<b>Example</b>\n\\code\n<zones>\n  <zone name=\"Network\">\n    <assign region=\"RAM1\" block=\"Network\"        access=\"rw\"/>\n    <assign group=\"UART\" peripheral=\"USART0\"     access=\"rw\" />\n    :\n  </zone>\n  :\n</zones>\n\\endcode\n&nbsp;\n\n<table class=\"cmtable\" summary=\"Element: zones\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_azone_pg \"azone\"</td>\n    <td colspan=3>\\ref xml_azone_pg</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\subpage xml_zone \"zone\"</td>\n    <td>Zone definitions</td>\n    <td>complexType</td>\n    <td>1..*</td>\n  </tr>\n</table>\n\n\\section xml_zone /azone/zones/zone element\n\nThe \\ref xml_zone defines the name of a zone.\n\n<table class=\"cmtable\" summary=\"Element: zone\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_zones \"zones\"</td>\n    <td colspan=3>\\ref xml_zones</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The unique name for this zone.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description of the zone.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>Pname</td>\n    <td>The processor that can access the memory and peripherals of this zone. If omitted all processors of the system have access.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security level\" for code execution in this zone.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>\\ref privilege \"Privilege level\" for code execution in this zone.</td>\n    <td>\\ref privilege \"PrivilegeType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>class</td>\n    <td>Class information for execution zones.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_assign \"assign\"</td>\n    <td>Resource Assignments</td>\n    <td>complexType</td>\n    <td>1..*</td>\n  </tr>\n</table>\n\n\n\\section xml_assign /azone/zones/zone/assign element\n\nThe \\ref xml_assign defines the resource assignments of that zone.\n\n<table class=\"cmtable\" summary=\"Element: assign\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_zone \"zone\"</td>\n    <td colspan=3>\\ref xml_zone</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>memory</td>\n    <td>Name of a memory region or memory partition.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>group</td>\n    <td>Name of a peripheral group.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>peripheral</td>\n    <td>Name of a peripheral.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>access</td>\n    <td>\\ref access \"Access\" permissions for this assignment.</td>\n    <td>\\ref access \"AccessType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>Pname</td>\n    <td>The processor that can access this assignment. If omitted the processors of the zone have access.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" attributes for this assignment.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>\\ref privilege \"Privilege level\" for this assignment.</td>\n    <td>\\ref privilege \"PrivilegeType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>uninit</td>\n    <td>\"1\" specifies that this region is not zero initialized during startup. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>dma</td>\n    <td>\"1\" specifies that this region is accessed by a DMA controller. Default value is \"0\".</td>\n    <td>xs:boolean</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <th>Child Elements</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Occurrence</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_ainterrupt \"interrupt\"</td>\n    <td>Interrupt assignments for peripherals.</td>\n    <td>complexType</td>\n    <td>0..*</td>\n  </tr>\n</table>\n\n\n\\section xml_ainterrupt /azone/zones/zone/assign/interrupt element\n\nThe \\ref xml_ainterrupt defines the interrupt execution for a peripheral.\n\n<table class=\"cmtable\" summary=\"Element: interrupt\">\n  <tr>\n    <th>Parent Element</th>\n    <th colspan=\"3\">Element Chain</th>\n  </tr>\n  <tr>\n    <td>\\ref xml_zone \"assign\"</td>\n    <td colspan=3>\\ref xml_assign</td>\n  </tr>\n  <tr>\n    <th>Attributes</th>\n    <th>Description</th>\n    <th>Type</th>\n    <th>Use</th>\n  </tr>\n  <tr>\n    <td>name</td>\n    <td>The name of the interrupt.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>value</td>\n    <td>The interrupt number.</td>\n    <td>xs:string</td>\n    <td>required</td>\n  </tr>\n  <tr>\n    <td>info</td>\n    <td>Brief description for this setting.</td>\n    <td>xs:string</td>\n    <td>optional</td>\n  </tr>  \n  <tr>\n    <td>security</td>\n    <td>\\ref security \"Security\" setting for the interrupt.</td>\n    <td>\\ref security \"SecurityType\"</td>\n    <td>optional</td>\n  </tr>\n  <tr>\n    <td>privilege</td>\n    <td>\\ref privilege \"Privilege level\" setting for the interrupt.</td>\n    <td>\\ref privilege \"PrivilegeType\"</td>\n    <td>optional</td>\n  </tr>\n</table>\n\n*/\n\n"
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The tag can be used to show relative paths in the file list.\n# If left blank the directory from which doxygen is run is used as the path to\n# strip.\n#\n# Note that you can specify absolute paths here, but also relative paths, which\n# will be relative from the directory where doxygen is started.\n# This tag requires that the tag FULL_PATH_NAMES is set to YES.\n\nSTRIP_FROM_PATH        = \n\n# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the\n# path mentioned in the documentation of a class, which tells the reader which\n# header file to include in order to use a class. If left blank only the name of\n# the header file containing the class definition is used. Otherwise one should\n# specify the list of include paths that are normally passed to the compiler\n# using the -I flag.\n\nSTRIP_FROM_INC_PATH    = \n\n# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but\n# less readable) file names. This can be useful is your file systems doesn't\n# support long names like on DOS, Mac, or CD-ROM.\n# The default value is: NO.\n\nSHORT_NAMES            = NO\n\n# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the\n# first line (until the first dot) of a Javadoc-style comment as the brief\n# description. If set to NO, the Javadoc-style will behave just like regular Qt-\n# style comments (thus requiring an explicit @brief command for a brief\n# description.)\n# The default value is: NO.\n\nJAVADOC_AUTOBRIEF      = NO\n\n# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first\n# line (until the first dot) of a Qt-style comment as the brief description. If\n# set to NO, the Qt-style will behave just like regular Qt-style comments (thus\n# requiring an explicit \\brief command for a brief description.)\n# The default value is: NO.\n\nQT_AUTOBRIEF           = NO\n\n# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a\n# multi-line C++ special comment block (i.e. a block of //! or /// comments) as\n# a brief description. This used to be the default behavior. The new default is\n# to treat a multi-line C++ comment block as a detailed description. Set this\n# tag to YES if you prefer the old behavior instead.\n#\n# Note that setting this tag to YES also means that rational rose comments are\n# not recognized any more.\n# The default value is: NO.\n\nMULTILINE_CPP_IS_BRIEF = YES\n\n# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the\n# documentation from any documented member that it re-implements.\n# The default value is: YES.\n\nINHERIT_DOCS           = NO\n\n# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce a\n# new page for each member. If set to NO, the documentation of a member will be\n# part of the file/class/namespace that contains it.\n# The default value is: NO.\n\nSEPARATE_MEMBER_PAGES  = NO\n\n# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen\n# uses this value to replace tabs by spaces in code fragments.\n# Minimum value: 1, maximum value: 16, default value: 4.\n\nTAB_SIZE               = 8\n\n# This tag can be used to specify a number of aliases that act as commands in\n# the documentation. An alias has the form:\n# name=value\n# For example adding\n# \"sideeffect=@par Side Effects:\\n\"\n# will allow you to put the command \\sideeffect (or @sideeffect) in the\n# documentation, which will result in a user-defined paragraph with heading\n# \"Side Effects:\". You can put \\n's in the value part of an alias to insert\n# newlines.\n\nALIASES                = \"token{1}=<span class=\\\"XML-Token\\\">\\1</span>\"\n\n# This tag can be used to specify a number of word-keyword mappings (TCL only).\n# A mapping has the form \"name=value\". For example adding \"class=itcl::class\"\n# will allow you to use the command class in the itcl::class meaning.\n\nTCL_SUBST              = \n\n# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources\n# only. Doxygen will then generate output that is more tailored for C. For\n# instance, some of the names that are used will be different. The list of all\n# members will be omitted, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_FOR_C  = YES\n\n# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or\n# Python sources only. Doxygen will then generate output that is more tailored\n# for that language. For instance, namespaces will be presented as packages,\n# qualified scopes will look different, etc.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_JAVA   = NO\n\n# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran\n# sources. Doxygen will then generate output that is tailored for Fortran.\n# The default value is: NO.\n\nOPTIMIZE_FOR_FORTRAN   = NO\n\n# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL\n# sources. Doxygen will then generate output that is tailored for VHDL.\n# The default value is: NO.\n\nOPTIMIZE_OUTPUT_VHDL   = NO\n\n# Doxygen selects the parser to use depending on the extension of the files it\n# parses. With this tag you can assign which parser to use for a given\n# extension. Doxygen has a built-in mapping, but you can override or extend it\n# using this tag. The format is ext=language, where ext is a file extension, and\n# language is one of the parsers supported by doxygen: IDL, Java, Javascript,\n# C#, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL. For instance to make\n# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C\n# (default is Fortran), use: inc=Fortran f=C.\n#\n# Note For files without extension you can use no_extension as a placeholder.\n#\n# Note that for custom extensions you also need to set FILE_PATTERNS otherwise\n# the files are not read by doxygen.\n\nEXTENSION_MAPPING      = \n\n# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments\n# according to the Markdown format, which allows for more readable\n# documentation. See http://daringfireball.net/projects/markdown/ for details.\n# The output of markdown processing is further processed by doxygen, so you can\n# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in\n# case of backward compatibilities issues.\n# The default value is: YES.\n\nMARKDOWN_SUPPORT       = YES\n\n# When enabled doxygen tries to link words that correspond to documented\n# classes, or namespaces to their corresponding documentation. Such a link can\n# be prevented in individual cases by by putting a % sign in front of the word\n# or globally by setting AUTOLINK_SUPPORT to NO.\n# The default value is: YES.\n\nAUTOLINK_SUPPORT       = YES\n\n# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want\n# to include (a tag file for) the STL sources as input, then you should set this\n# tag to YES in order to let doxygen match functions declarations and\n# definitions whose arguments contain STL classes (e.g. func(std::string);\n# versus func(std::string) {}). This also make the inheritance and collaboration\n# diagrams that involve STL classes more complete and accurate.\n# The default value is: NO.\n\nBUILTIN_STL_SUPPORT    = NO\n\n# If you use Microsoft's C++/CLI language, you should set this option to YES to\n# enable parsing support.\n# The default value is: NO.\n\nCPP_CLI_SUPPORT        = NO\n\n# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:\n# http://www.riverbankcomputing.co.uk/software/sip/intro) sources only. Doxygen\n# will parse them like normal C++ but will assume all classes use public instead\n# of private inheritance when no explicit protection keyword is present.\n# The default value is: NO.\n\nSIP_SUPPORT            = NO\n\n# For Microsoft's IDL there are propget and propput attributes to indicate\n# getter and setter methods for a property. Setting this option to YES will make\n# doxygen to replace the get and set methods by a property in the documentation.\n# This will only work if the methods are indeed getting or setting a simple\n# type. If this is not the case, or you want to show the methods anyway, you\n# should set this option to NO.\n# The default value is: YES.\n\nIDL_PROPERTY_SUPPORT   = YES\n\n# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC\n# tag is set to YES, then doxygen will reuse the documentation of the first\n# member in the group (if any) for the other members of the group. By default\n# all members of a group must be documented explicitly.\n# The default value is: NO.\n\nDISTRIBUTE_GROUP_DOC   = NO\n\n# Set the SUBGROUPING tag to YES to allow class member groups of the same type\n# (for instance a group of public functions) to be put as a subgroup of that\n# type (e.g. under the Public Functions section). Set it to NO to prevent\n# subgrouping. Alternatively, this can be done per class using the\n# \\nosubgrouping command.\n# The default value is: YES.\n\nSUBGROUPING            = YES\n\n# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions\n# are shown inside the group in which they are included (e.g. using \\ingroup)\n# instead of on a separate page (for HTML and Man pages) or section (for LaTeX\n# and RTF).\n#\n# Note that this feature does not work in combination with\n# SEPARATE_MEMBER_PAGES.\n# The default value is: NO.\n\nINLINE_GROUPED_CLASSES = NO\n\n# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions\n# with only public data fields or simple typedef fields will be shown inline in\n# the documentation of the scope in which they are defined (i.e. file,\n# namespace, or group documentation), provided this scope is documented. If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = NO\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = YES\n\n# If the EXTRACT_PRIVATE tag is set to YES all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = YES\n\n# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = YES\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. When set to YES local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO these classes will be included in the various overviews. This option has\n# no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# (class|struct|union) declarations. If set to NO these declarations will be\n# included in the documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file\n# names in lower-case letters. If set to YES upper-case letters are also\n# allowed. This is useful if you have classes or files whose names only differ\n# in case and if your file system supports case sensitive file names. Windows\n# and Mac users are advised to set this option to NO.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = YES\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = NO\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = NO\n\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable ( YES) or disable ( NO) the\n# todo list. This list is created by putting \\todo commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = YES\n\n# The GENERATE_TESTLIST tag can be used to enable ( YES) or disable ( NO) the\n# test list. This list is created by putting \\test commands in the\n# documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = NO\n\n# The GENERATE_BUGLIST tag can be used to enable ( YES) or disable ( NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = NO\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable ( YES) or disable ( NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       = \n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 1\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES the list\n# will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = YES\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    = \n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            = ../Doxygen_Templates/DoxygenLayout_forUser.xml\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. Do not use file names with spaces, bibtex cannot handle them. See\n# also \\cite for info how to create references.\n\nCITE_BIB_FILES         = \n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = YES\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error ( stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES, then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as not documenting some parameters\n# in a documented function, or documenting parameters that don't exist or using\n# markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO doxygen will only warn about wrong or incomplete parameter\n# documentation, but not about the absence of documentation.\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr).\n\nWARN_LOGFILE           = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces.\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = src/Overview.txt \\\n                         src/XML_Format.txt \\\n                         src/GenDataModel.txt \\\n\t\t\t\t\t\t src/ErrorMessages.txt\n\t\t\t\t\t\t \n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see: http://www.gnu.org/software/libiconv) for the list of\n# possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank the\n# following patterns are tested:*.c, *.cc, *.cxx, *.cpp, *.c++, *.java, *.ii,\n# *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, *.hh, *.hxx, *.hpp,\n# *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, *.m, *.markdown,\n# *.md, *.mm, *.dox, *.py, *.f90, *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf,\n# *.qsf, *.as and *.js.\n\nFILE_PATTERNS          = \n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = NO\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                = system*.c \\\n                         startup*.s \\\n                         src/exclude/\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = NO\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       = \n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# AClass::ANamespace, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        = \n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           = \n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             = src/images\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n\nINPUT_FILTER           = \n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n\nFILTER_PATTERNS        = \n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER ) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS = \n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE = \n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = YES\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# function all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = YES\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = YES\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES, then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = NO\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see http://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the config file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = NO\n\n# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in\n# which the alphabetical index list will be split.\n# Minimum value: 1, maximum value: 20, default value: 5.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nCOLS_IN_ALPHA_INDEX    = 5\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            = ../Doxygen_Templates/cmsis_header.html\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            = ../Doxygen_Templates/cmsis_footer.html\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        = \n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional user-\n# defined cascading style sheet that is included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefor more robust against future updates.\n# Doxygen will copy the style sheet file to the output directory. For an example\n# see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  = ../Doxygen_Templates/cmsis.css\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       = ../Doxygen_Templates/tabs.css \\\n                         ../Doxygen_Templates/tab_topnav.png \\\n                         ../Doxygen_Templates/search.css \\\n                         ../Doxygen_Templates/check.png \\\n                         ../Doxygen_Templates/printComponentTabs.js\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the stylesheet and background images according to\n# this color. Hue is specified as an angle on a colorwheel, see\n# http://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use grayscales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 100\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see: http://developer.apple.com/tools/xcode/), introduced with\n# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a\n# Makefile in the HTML output directory. Running make will produce the docset in\n# that directory and running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html\n# for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on\n# Windows.\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               = CMSIS_Core.chm\n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler ( hhc.exe). If non-empty\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           = \"C:/Program Files/HTML Help Workshop/hhc.exe\"\n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated (\n# YES) or that it should be included in the master .chm file ( NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index ( hhk), content ( hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     = \n\n# The BINARY_TOC flag controls whether a binary table of contents is generated (\n# YES) or a normal table of contents ( NO) in the .chm file.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               = \n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual-\n# folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   = \n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom-\n# filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  = \n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  = \n\n# The QHG_LOCATION tag can be used to specify the location of Qt's\n# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the\n# generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           = \n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom stylesheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine-tune the look of the index. As an example, the default style\n# sheet generated by doxygen has an example that shows how to put an image at\n# the root of the tree instead of the PROJECT_NAME. Since the tree basically has\n# the same information as the tab index, you could consider setting\n# DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 1\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# http://www.mathjax.org) which uses client side Javascript for the rendering\n# instead of using prerendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = NO\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. See the MathJax site (see:\n# http://docs.mathjax.org/en/latest/output.html) for more details.\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility), NativeMML (i.e. MathML) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from http://www.mathjax.org before deployment.\n# The default value is: http://cdn.mathjax.org/mathjax/latest.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://www.mathjax.org/mathjax\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     = \n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       = \n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using Javascript. There\n# are two flavours of web server based searching depending on the\n# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for\n# searching and an index file used by the script. When EXTERNAL_SEARCH is\n# enabled the indexing and searching needs to be provided by external tools. See\n# the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer ( doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see: http://xapian.org/). See the section \"External Indexing and\n# Searching\" for details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       = \n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     = \n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when enabling USE_PDFLATEX this option is only used for generating\n# bitmaps for formulas in the HTML output, but not in the Makefile that is\n# written to the output directory.\n# The default file is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# If the COMPACT_LATEX tag is set to YES doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = NO\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. To get the times font for\n# instance you can specify\n# EXTRA_PACKAGES=times\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         = \n\n# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the\n# generated LaTeX document. The header should contain everything until the first\n# chapter. If it is left blank doxygen will generate a standard header. See\n# section \"Doxygen usage\" for information on how to let doxygen write the\n# default header to a separate file.\n#\n# Note: Only use a user-defined header if you know what you are doing! The\n# following commands have a special meaning inside the header: $title,\n# $datetime, $date, $doxygenversion, $projectname, $projectnumber. Doxygen will\n# replace them by respectively the title of the page, the current date and time,\n# only the current date, the version number of doxygen, the project name (see\n# PROJECT_NAME), or the project number (see PROJECT_NUMBER).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           = \n\n# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the\n# generated LaTeX document. The footer should contain everything after the last\n# chapter. If it is left blank doxygen will generate a standard footer.\n#\n# Note: Only use a user-defined footer if you know what you are doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           = \n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      = \n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the LATEX_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate\n# the PDF file directly from the LaTeX files. Set this option to YES to get a\n# higher quality PDF documentation.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help. This option is also used\n# when generating formulas in HTML.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source\n# code with syntax highlighting in the LaTeX output.\n#\n# Note that which sources are shown also depends on other settings such as\n# SOURCE_BROWSER.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_SOURCE_CODE      = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# http://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = NO\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = NO\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's config\n# file, i.e. a series of assignments. You only have to provide replacements,\n# missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    = \n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's config file. A template extensions file can be generated\n# using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = NO\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# The XML_SCHEMA tag can be used to specify a XML schema, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_SCHEMA             = \n\n# The XML_DTD tag can be used to specify a XML DTD, which can be used by a\n# validating XML parser to check the syntax of the XML files.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_DTD                = \n\n# If the XML_PROGRAMLISTING tag is set to YES doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES doxygen will generate an AutoGen\n# Definitions (see http://autogen.sf.net) file that captures the structure of\n# the code including all documentation. Note that this feature is still\n# experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES doxygen will generate a Perl module\n# file that captures the structure of the code including all documentation.\n#\n# Note that this feature is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES doxygen will generate the necessary\n# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI\n# output from the Perl module output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be nicely\n# formatted so it can be parsed by a human reader. This is useful if you want to\n# understand what is going on. On the other hand, if this tag is set to NO the\n# size of the Perl module output will be much smaller and Perl will parse it\n# just the same.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_PRETTY         = YES\n\n# The names of the make variables in the generated doxyrules.make file are\n# prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. This is useful\n# so different doxyrules.make files included by the same Makefile don't\n# overwrite each other's variables.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_MAKEVAR_PREFIX = \n\n#---------------------------------------------------------------------------\n# Configuration options related to the preprocessor\n#---------------------------------------------------------------------------\n\n# If the ENABLE_PREPROCESSING tag is set to YES doxygen will evaluate all\n# C-preprocessor directives found in the sources and include files.\n# The default value is: YES.\n\nENABLE_PREPROCESSING   = YES\n\n# If the MACRO_EXPANSION tag is set to YES doxygen will expand all macro names\n# in the source code. If set to NO only conditional compilation will be\n# performed. Macro expansion can be done in a controlled way by setting\n# EXPAND_ONLY_PREDEF to YES.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nMACRO_EXPANSION        = NO\n\n# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES then\n# the macro expansion is limited to the macros specified with the PREDEFINED and\n# EXPAND_AS_DEFINED tags.\n# The default value is: NO.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_ONLY_PREDEF     = NO\n\n# If the SEARCH_INCLUDES tag is set to YES the includes files in the\n# INCLUDE_PATH will be searched if a #include is found.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSEARCH_INCLUDES        = YES\n\n# The INCLUDE_PATH tag can be used to specify one or more directories that\n# contain include files that are not input files but should be processed by the\n# preprocessor.\n# This tag requires that the tag SEARCH_INCLUDES is set to YES.\n\nINCLUDE_PATH           = \n\n# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard\n# patterns (like *.h and *.hpp) to filter out the header-files in the\n# directories. If left blank, the patterns specified with FILE_PATTERNS will be\n# used.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nINCLUDE_FILE_PATTERNS  = \n\n# The PREDEFINED tag can be used to specify one or more macro names that are\n# defined before the preprocessor is started (similar to the -D option of e.g.\n# gcc). The argument of the tag is a list of macros of the form: name or\n# name=definition (no spaces). If the definition and the \"=\" are omitted, \"=1\"\n# is assumed. To prevent a macro definition from being undefined via #undef or\n# recursively expanded use the := operator instead of the = operator.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nPREDEFINED             = \n\n# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then this\n# tag can be used to specify a list of macro names that should be expanded. The\n# macro definition that is found in the sources will be used. Use the PREDEFINED\n# tag if you want to use a different macro definition that overrules the\n# definition found in the source code.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nEXPAND_AS_DEFINED      = \n\n# If the SKIP_FUNCTION_MACROS tag is set to YES then doxygen's preprocessor will\n# remove all refrences to function-like macros that are alone on a line, have an\n# all uppercase name, and do not end with a semicolon. Such function macros are\n# typically used for boiler-plate code, and will confuse the parser if not\n# removed.\n# The default value is: YES.\n# This tag requires that the tag ENABLE_PREPROCESSING is set to YES.\n\nSKIP_FUNCTION_MACROS   = YES\n\n#---------------------------------------------------------------------------\n# Configuration options related to external references\n#---------------------------------------------------------------------------\n\n# The TAGFILES tag can be used to specify one or more tag files. For each tag\n# file the location of the external documentation should be added. The format of\n# a tag file without this location is as follows:\n# TAGFILES = file1 file2 ...\n# Adding location for the tag files is done as follows:\n# TAGFILES = file1=loc1 \"file2 = loc2\" ...\n# where loc1 and loc2 can be relative or absolute paths or URLs. See the\n# section \"Linking to external documentation\" for more information about the use\n# of tag files.\n# Note: Each tag file must have an unique name (where the name does NOT include\n# the path). If a tag file is not located in the directory in which doxygen is\n# run, you must also specify the path to the tagfile here.\n\nTAGFILES               = \n\n# When a file name is specified after GENERATE_TAGFILE, doxygen will create a\n# tag file that is based on the input files it reads. See section \"Linking to\n# external documentation\" for more information about the usage of tag files.\n\nGENERATE_TAGFILE       = \n\n# If the ALLEXTERNALS tag is set to YES all external class will be listed in the\n# class index. If set to NO only the inherited external classes will be listed.\n# The default value is: NO.\n\nALLEXTERNALS           = NO\n\n# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed in\n# the modules index. If set to NO, only the current project's groups will be\n# listed.\n# The default value is: YES.\n\nEXTERNAL_GROUPS        = YES\n\n# If the EXTERNAL_PAGES tag is set to YES all external pages will be listed in\n# the related pages index. If set to NO, only the current project's pages will\n# be listed.\n# The default value is: YES.\n\nEXTERNAL_PAGES         = YES\n\n# The PERL_PATH should be the absolute path and name of the perl script\n# interpreter (i.e. the result of 'which perl').\n# The default file (with absolute path) is: /usr/bin/perl.\n\nPERL_PATH              = /usr/bin/perl\n\n#---------------------------------------------------------------------------\n# Configuration options related to the dot tool\n#---------------------------------------------------------------------------\n\n# If the CLASS_DIAGRAMS tag is set to YES doxygen will generate a class diagram\n# (in HTML and LaTeX) for classes with base or super classes. Setting the tag to\n# NO turns the diagrams off. Note that this option also works with HAVE_DOT\n# disabled, but it is recommended to install and use dot, since it yields more\n# powerful graphs.\n# The default value is: YES.\n\nCLASS_DIAGRAMS         = YES\n\n# You can define message sequence charts within doxygen comments using the \\msc\n# command. Doxygen will then run the mscgen tool (see:\n# http://www.mcternan.me.uk/mscgen/)) to produce the chart and insert it in the\n# documentation. The MSCGEN_PATH tag allows you to specify the directory where\n# the mscgen tool resides. If left empty the tool is assumed to be found in the\n# default search path.\n\nMSCGEN_PATH            = \n\n# You can include diagrams made with dia in doxygen documentation. Doxygen will\n# then run dia to produce the diagram and insert it in the documentation. The\n# DIA_PATH tag allows you to specify the directory where the dia binary resides.\n# If left empty dia is assumed to be found in the default search path.\n\nDIA_PATH               = \n\n# If set to YES, the inheritance and collaboration graphs will hide inheritance\n# and usage relations if the target is undocumented or is not a class.\n# The default value is: YES.\n\nHIDE_UNDOC_RELATIONS   = YES\n\n# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is\n# available from the path. This tool is part of Graphviz (see:\n# http://www.graphviz.org/), a graph visualization toolkit from AT&T and Lucent\n# Bell Labs. The other options in this section have no effect if this option is\n# set to NO\n# The default value is: NO.\n\nHAVE_DOT               = NO\n\n# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is allowed\n# to run in parallel. When set to 0 doxygen will base this on the number of\n# processors available in the system. You can set it explicitly to a value\n# larger than 0 to get control over the balance between CPU load and processing\n# speed.\n# Minimum value: 0, maximum value: 32, default value: 0.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_NUM_THREADS        = 0\n\n# When you want a differently looking font n the dot files that doxygen\n# generates you can specify the font name using DOT_FONTNAME. You need to make\n# sure dot is able to find the font, which can be done by putting it in a\n# standard location or by setting the DOTFONTPATH environment variable or by\n# setting DOT_FONTPATH to the directory containing the font.\n# The default value is: Helvetica.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTNAME           = Helvetica\n\n# The DOT_FONTSIZE tag can be used to set the size (in points) of the font of\n# dot graphs.\n# Minimum value: 4, maximum value: 24, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTSIZE           = 10\n\n# By default doxygen will tell dot to use the default font as specified with\n# DOT_FONTNAME. If you specify a different font using DOT_FONTNAME you can set\n# the path where dot can find it using this tag.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_FONTPATH           = \n\n# If the CLASS_GRAPH tag is set to YES then doxygen will generate a graph for\n# each documented class showing the direct and indirect inheritance relations.\n# Setting this tag to YES will force the CLASS_DIAGRAMS tag to NO.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCLASS_GRAPH            = YES\n\n# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a\n# graph for each documented class showing the direct and indirect implementation\n# dependencies (inheritance, containment, and class references variables) of the\n# class with other documented classes.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCOLLABORATION_GRAPH    = YES\n\n# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for\n# groups, showing the direct groups dependencies.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGROUP_GRAPHS           = YES\n\n# If the UML_LOOK tag is set to YES doxygen will generate inheritance and\n# collaboration diagrams in a style similar to the OMG's Unified Modeling\n# Language.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LOOK               = NO\n\n# If the UML_LOOK tag is enabled, the fields and methods are shown inside the\n# class node. If there are many fields or methods and many nodes the graph may\n# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the\n# number of items for each type to make the size more manageable. Set this to 0\n# for no limit. Note that the threshold may be exceeded by 50% before the limit\n# is enforced. So when you set the threshold to 10, up to 15 fields may appear,\n# but if the number exceeds 15, the total amount of fields shown is limited to\n# 10.\n# Minimum value: 0, maximum value: 100, default value: 10.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nUML_LIMIT_NUM_FIELDS   = 10\n\n# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and\n# collaboration graphs will show the relations between templates and their\n# instances.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nTEMPLATE_RELATIONS     = NO\n\n# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to\n# YES then doxygen will generate a graph for each documented file showing the\n# direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDE_GRAPH          = YES\n\n# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are\n# set to YES then doxygen will generate a graph for each documented file showing\n# the direct and indirect include dependencies of the file with other documented\n# files.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINCLUDED_BY_GRAPH      = YES\n\n# If the CALL_GRAPH tag is set to YES then doxygen will generate a call\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable call graphs for selected\n# functions only using the \\callgraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALL_GRAPH             = NO\n\n# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller\n# dependency graph for every global function or class method.\n#\n# Note that enabling this option will significantly increase the time of a run.\n# So in most cases it will be better to enable caller graphs for selected\n# functions only using the \\callergraph command.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nCALLER_GRAPH           = NO\n\n# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical\n# hierarchy of all classes instead of a textual one.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGRAPHICAL_HIERARCHY    = YES\n\n# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the\n# dependencies a directory has on other directories in a graphical way. The\n# dependency relations are determined by the #include relations between the\n# files in the directories.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDIRECTORY_GRAPH        = YES\n\n# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images\n# generated by dot.\n# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order\n# to make the SVG files visible in IE 9+ (other browsers do not have this\n# requirement).\n# Possible values are: png, jpg, gif and svg.\n# The default value is: png.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_IMAGE_FORMAT       = png\n\n# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to\n# enable generation of interactive SVG images that allow zooming and panning.\n#\n# Note that this requires a modern browser other than Internet Explorer. Tested\n# and working are Firefox, Chrome, Safari, and Opera.\n# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make\n# the SVG files visible. Older versions of IE do not have SVG support.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nINTERACTIVE_SVG        = NO\n\n# The DOT_PATH tag can be used to specify the path where the dot tool can be\n# found. If left blank, it is assumed the dot tool can be found in the path.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_PATH               = \n\n# The DOTFILE_DIRS tag can be used to specify one or more directories that\n# contain dot files that are included in the documentation (see the \\dotfile\n# command).\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOTFILE_DIRS           = \n\n# The MSCFILE_DIRS tag can be used to specify one or more directories that\n# contain msc files that are included in the documentation (see the \\mscfile\n# command).\n\nMSCFILE_DIRS           = \n\n# The DIAFILE_DIRS tag can be used to specify one or more directories that\n# contain dia files that are included in the documentation (see the \\diafile\n# command).\n\nDIAFILE_DIRS           = \n\n# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes\n# that will be shown in the graph. If the number of nodes in a graph becomes\n# larger than this value, doxygen will truncate the graph, which is visualized\n# by representing a node as a red box. Note that doxygen if the number of direct\n# children of the root node in a graph is already larger than\n# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note that\n# the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.\n# Minimum value: 0, maximum value: 10000, default value: 50.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_GRAPH_MAX_NODES    = 50\n\n# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the graphs\n# generated by dot. A depth value of 3 means that only nodes reachable from the\n# root by following a path via at most 3 edges will be shown. Nodes that lay\n# further from the root node will be omitted. Note that setting this option to 1\n# or 2 may greatly reduce the computation time needed for large code bases. Also\n# note that the size of a graph can be further restricted by\n# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.\n# Minimum value: 0, maximum value: 1000, default value: 0.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nMAX_DOT_GRAPH_DEPTH    = 0\n\n# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent\n# background. This is disabled by default, because dot on Windows does not seem\n# to support this out of the box.\n#\n# Warning: Depending on the platform used, enabling this option may lead to\n# badly anti-aliased labels on the edges of a graph (i.e. they become hard to\n# read).\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_TRANSPARENT        = NO\n\n# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output\n# files in one run (i.e. multiple -o and -T options on the command line). This\n# makes dot run faster, but since only newer versions of dot (>1.8.10) support\n# this, this feature is disabled by default.\n# The default value is: NO.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_MULTI_TARGETS      = NO\n\n# If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page\n# explaining the meaning of the various boxes and arrows in the dot generated\n# graphs.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nGENERATE_LEGEND        = YES\n\n# If the DOT_CLEANUP tag is set to YES doxygen will remove the intermediate dot\n# files that are used to generate the various graphs.\n# The default value is: YES.\n# This tag requires that the tag HAVE_DOT is set to YES.\n\nDOT_CLEANUP            = YES\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/gen_doc.sh",
    "content": "#!/bin/bash\n# Version: 1.0\n# Date: 2021-05-05\n# This bash script generates CMSIS Documentation:\n#\n# Pre-requisites:\n# - bash shell (for Windows: install git for Windows)\n# - doxygen 1.8.6\n# - mscgen 0.20\n\nset -o pipefail\n\nDIRNAME=$(dirname $(readlink -f $0))\nDOXYGEN=$(which doxygen)\nMSCGEN=$(which mscgen)\nREGEN=0\nALLPARTS=($(find ${DIRNAME} -mindepth 1 -maxdepth 1 -type d -exec basename {} \\;))\nPARTS=()\n\nif [[ -z \"$*\" ]]; then\n    REGEN=1\nelse\n    for part in \"$*\"; do\n        if [[ \" ${ALLPARTS[@]} \" =~ \" $part \" ]]; then\n            PARTS+=($part)\n        fi\n    done\nfi\n\nif [[ ! -f \"${DOXYGEN}\" ]]; then\n    echo \"Doxygen not found!\" >&2\n    echo \"Did you miss to add it to PATH?\"\n    exit 1\nelse\n    version=$(\"${DOXYGEN}\" --version)\n    echo \"DOXYGEN is ${DOXYGEN} at version ${version}\"\n    if [[ \"${version}\" != \"1.8.6\" ]]; then\n        echo \" >> Version is different from 1.8.6 !\" >&2\n    fi\nfi\n\nif [[ ! -f \"${MSCGEN}\" ]]; then\n    echo \"mscgen not found!\" >&2\n    echo \"Did you miss to add it to PATH?\"\n    exit 1\nelse\n    version=$(\"${MSCGEN}\" 2>/dev/null | grep \"Mscgen version\" | sed -r -e 's/Mscgen version ([^,]+),.*/\\1/')\n    echo \"MSCGEN is ${MSCGEN} at version ${version}\"\n    if [[ \"${version}\" != \"0.20\" ]]; then\n        echo \" >> Version is different from 0.20 !\" >&2\n    fi\nfi\n\nfunction doxygen {\n    partname=$(basename $(dirname $1))\n    if [[ $REGEN != 0 ]] || [[ \" ${PARTS[@]} \" =~ \" ${partname} \" ]]; then\n        pushd \"$(dirname $1)\" > /dev/null\n        echo \"${DOXYGEN} $1\"\n        \"${DOXYGEN}\" $(basename \"$1\")\n        popd > /dev/null\n\n        if [[ $2 != 0 ]]; then\n            cp -f \"${DIRNAME}/Doxygen_Templates/search.css\" \"${DIRNAME}/../Documentation/${partname}/html/search/\"\n        fi\n\n        projectName=$(grep -E \"PROJECT_NAME\\s+=\" $1 | sed -r -e 's/[^\"]*\"([^\"]+)\"/\\1/')\n        projectNumber=$(grep -E \"PROJECT_NUMBER\\s+=\" $1 | sed -r -e 's/[^\"]*\"([^\"]+)\"/\\1/')\n        datetime=$(date -u +'%a %b %e %Y %H:%M:%S')\n        sed -e \"s/{datetime}/${datetime}/\" \"${DIRNAME}/Doxygen_Templates/cmsis_footer.js\" \\\n          | sed -e \"s/{projectName}/${projectName}/\" \\\n          | sed -e \"s/{projectNumber}/${projectNumber}/\" \\\n          > \"${DIRNAME}/../Documentation/${partname}/html/cmsis_footer.js\"\n    fi\n}\n\nif [[ $REGEN != 0 ]]; then\n    echo \"Cleaning existing documentation ...\"\n    find \"${DIRNAME}/../Documentation/\" -mindepth 1 -maxdepth 1 -type d -exec rm -rf {} +\nfi\n\necho \"Generating documentation ...\"\necho \"Copying Build html\"\nmkdir -p \"${DIRNAME}/../Documentation/Build/\"\ncp -r \"${DIRNAME}/Build/html/\" \"${DIRNAME}/../Documentation/Build/\"\ndoxygen \"${DIRNAME}/Core/core.dxy\" 1\ndoxygen \"${DIRNAME}/Core_A/core_A.dxy\" 1\ndoxygen \"${DIRNAME}/DAP/dap.dxy\" 1\ndoxygen \"${DIRNAME}/Driver/Driver.dxy\" 1\necho \"Copying DSP html\"\nmkdir -p \"${DIRNAME}/../Documentation/DSP/\"\ncp -r \"${DIRNAME}/DSP/html\" \"${DIRNAME}/../Documentation/DSP/\"\ndoxygen \"${DIRNAME}/General/general.dxy\" 0\ndoxygen \"${DIRNAME}/DAP/dap.dxy\" 1\necho \"Copying NN html\"\nmkdir -p \"${DIRNAME}/../Documentation/NN/\"\ncp -r \"${DIRNAME}/NN/html\" \"${DIRNAME}/../Documentation/NN/\"\necho \"Copying Pack html\"\nmkdir -p \"${DIRNAME}/../Documentation/Pack/\"\ncp -r \"${DIRNAME}/Pack/html\" \"${DIRNAME}/../Documentation/Pack/\"\ndoxygen \"${DIRNAME}/RTOS/rtos.dxy\" 1\ndoxygen \"${DIRNAME}/RTOS2/rtos.dxy\" 1\ndoxygen \"${DIRNAME}/SVD/svd.dxy\" 0\ndoxygen \"${DIRNAME}/Zone/zone.dxy\" 1\n\nexit 0\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/DoxyGen/index.html",
    "content": "<!DOCTYPE html PUBLIC \"-//W3C//DTD XHTML 1.0 Transitional//EN\" \"http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd\">\n<html xmlns=\"http://www.w3.org/1999/xhtml\">\n<head>\n<title>Redirect to the CMSIS main page after 0 seconds</title>\n<meta http-equiv=\"refresh\" content=\"0; URL=../Documentation/General/html/index.html\">\n<meta name=\"keywords\" content=\"automatic redirection\">\n</head>\n\n<body>\n\nIf the automatic redirection is failing, click <a href=\"../Documentation/General/html/index.html\">open CMSIS Documentation</a>.\n\n</body>\n</html>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_CAN.c",
    "content": "/*\n * Copyright (c) 2015-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_CAN.h\"\n\n#define ARM_CAN_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) // CAN driver version\n\n// Driver Version\nstatic const ARM_DRIVER_VERSION can_driver_version = { ARM_CAN_API_VERSION, ARM_CAN_DRV_VERSION };\n\n// Driver Capabilities\nstatic const ARM_CAN_CAPABILITIES can_driver_capabilities = {\n  32U,  // Number of CAN Objects available\n  0U,   // Does not support reentrant calls to ARM_CAN_MessageSend, ARM_CAN_MessageRead, ARM_CAN_ObjectConfigure and abort message sending used by ARM_CAN_Control.\n  0U,   // Does not support CAN with Flexible Data-rate mode (CAN_FD)\n  0U,   // Does not support restricted operation mode\n  0U,   // Does not support bus monitoring mode\n  0U,   // Does not support internal loopback mode\n  0U,   // Does not support external loopback mode\n  0U    // Reserved (must be zero)\n};\n\n// Object Capabilities\nstatic const ARM_CAN_OBJ_CAPABILITIES can_object_capabilities = {\n  1U,   // Object supports transmission\n  1U,   // Object supports reception\n  0U,   // Object does not support RTR reception and automatic Data transmission\n  0U,   // Object does not support RTR transmission and automatic Data reception\n  0U,   // Object does not allow assignment of multiple filters to it\n  0U,   // Object does not support exact identifier filtering\n  0U,   // Object does not support range identifier filtering\n  0U,   // Object does not support mask identifier filtering\n  0U,   // Object can not buffer messages\n  0U    // Reserved (must be zero)\n};\n\nstatic uint8_t                     can_driver_powered     = 0U;\nstatic uint8_t                     can_driver_initialized = 0U;\nstatic ARM_CAN_SignalUnitEvent_t   CAN_SignalUnitEvent    = NULL;\nstatic ARM_CAN_SignalObjectEvent_t CAN_SignalObjectEvent  = NULL;\n\n//\n//   Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_CAN_GetVersion (void) {\n  // Return driver version\n  return can_driver_version;\n}\n\nstatic ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void) {\n  // Return driver capabilities\n  return can_driver_capabilities;\n}\n\nstatic int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,\n                                   ARM_CAN_SignalObjectEvent_t cb_object_event) {\n\n  if (can_driver_initialized != 0U) { return ARM_DRIVER_OK; }\n\n  CAN_SignalUnitEvent   = cb_unit_event;\n  CAN_SignalObjectEvent = cb_object_event;\n\n  // Add code for pin, memory, RTX objects initialization\n  // ..\n\n  can_driver_initialized = 1U;\n\n  return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_CAN_Uninitialize (void) {\n\n  // Add code for pin, memory, RTX objects de-initialization\n  // ..\n\n  can_driver_initialized = 0U;\n\n  return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state) {\n  switch (state) {\n    case ARM_POWER_OFF:\n      can_driver_powered = 0U;\n      // Add code to disable interrupts and put peripheral into reset mode,\n      // and if possible disable clock\n      // ..\n\n      break;\n\n    case ARM_POWER_FULL:\n      if (can_driver_initialized == 0U) { return ARM_DRIVER_ERROR; }\n      if (can_driver_powered     != 0U) { return ARM_DRIVER_OK;    }\n\n      // Add code to enable clocks, reset variables enable interrupts\n      // and put peripheral into operational\n      // ..\n\n      can_driver_powered = 1U;\n      break;\n\n    case ARM_POWER_LOW:\n      return ARM_DRIVER_ERROR_UNSUPPORTED;\n  }\n\n  return ARM_DRIVER_OK;\n}\n\nstatic uint32_t ARM_CAN_GetClock (void) {\n\n  // Add code to return peripheral clock frequency\n  // ..\n}\n\nstatic int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) {\n\n  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }\n\n  // Add code to setup peripheral parameters to generate specified bitrate\n  // with specified bit segments\n  // ..\n\n  return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode) {\n\n  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }\n\n  switch (mode) {\n    case ARM_CAN_MODE_INITIALIZATION:\n      // Add code to put peripheral into initialization mode\n      // ..\n      break;\n    case ARM_CAN_MODE_NORMAL:\n      // Add code to put peripheral into normal operation mode\n      // ..\n      break;\n    case ARM_CAN_MODE_RESTRICTED:\n      // Add code to put peripheral into restricted operation mode\n      // ..\n      break;\n    case ARM_CAN_MODE_MONITOR:\n      // Add code to put peripheral into bus monitoring mode\n      // ..\n      break;\n    case ARM_CAN_MODE_LOOPBACK_INTERNAL:\n      // Add code to put peripheral into internal loopback mode\n      // ..\n      break;\n    case ARM_CAN_MODE_LOOPBACK_EXTERNAL:\n      // Add code to put peripheral into external loopback mode\n      // ..\n      break;\n  }\n\n  return ARM_DRIVER_OK;\n}\n\nstatic ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx) {\n  // Return object capabilities\n  return can_object_capabilities;\n}\n\nstatic int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) {\n\n  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }\n\n  switch (operation) {\n    case ARM_CAN_FILTER_ID_EXACT_ADD:\n      // Add code to setup peripheral to receive messages with specified exact ID\n      break;\n    case ARM_CAN_FILTER_ID_MASKABLE_ADD:\n      // Add code to setup peripheral to receive messages with specified maskable ID\n      break;\n    case ARM_CAN_FILTER_ID_RANGE_ADD:\n      // Add code to setup peripheral to receive messages within specified range of IDs\n      break;\n    case ARM_CAN_FILTER_ID_EXACT_REMOVE:\n      // Add code to remove specified exact ID from being received by peripheral\n      break;\n    case ARM_CAN_FILTER_ID_MASKABLE_REMOVE:\n      // Add code to remove specified maskable ID from being received by peripheral\n      break;\n    case ARM_CAN_FILTER_ID_RANGE_REMOVE:\n      // Add code to remove specified range of IDs from being received by peripheral\n      break;\n  }\n\n  return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) {\n\n  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }\n\n  switch (obj_cfg) {\n    case ARM_CAN_OBJ_INACTIVE:\n      // Deactivate object\n      // ..\n      break;\n    case ARM_CAN_OBJ_RX_RTR_TX_DATA:\n      // Setup object to automatically return data when RTR with it's ID is received\n      // ..\n      break;\n    case ARM_CAN_OBJ_TX_RTR_RX_DATA:\n      // Setup object to send RTR and receive data response\n      // ..\n      break;\n    case ARM_CAN_OBJ_TX:\n      // Setup object to be used for sending messages\n      // ..\n      break;\n    case ARM_CAN_OBJ_RX:\n      // Setup object to be used for receiving messages\n      // ..\n      break;\n  }\n\n  return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) {\n\n  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }\n\n  // Add code to send requested message\n  // ..\n\n  return ((int32_t)size);\n}\n\nstatic int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) {\n\n  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR;  }\n\n  // Add code to read previously received message\n  // (reception was started when object was configured for reception)\n  // ..\n\n  return ((int32_t)size);\n}\n\nstatic int32_t ARM_CAN_Control (uint32_t control, uint32_t arg) {\n\n  if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }\n\n  switch (control & ARM_CAN_CONTROL_Msk) {\n    case ARM_CAN_ABORT_MESSAGE_SEND:\n      // Add code to abort message pending to be sent\n      // ..\n      break;\n    case ARM_CAN_SET_FD_MODE:\n      // Add code to enable Flexible Data-rate mode\n      // ..\n      break;\n    case ARM_CAN_SET_TRANSCEIVER_DELAY:\n      // Add code to set transceiver delay\n      // ..\n      break;\n    default:\n      // Handle unknown control code\n      return ARM_DRIVER_ERROR_UNSUPPORTED;\n  }\n\n  return ARM_DRIVER_OK;\n}\n\nstatic ARM_CAN_STATUS ARM_CAN_GetStatus (void) {\n\n  // Add code to return device bus and error status\n  // ..\n}\n\n\n// IRQ handlers\n// Add interrupt routines to handle transmission, reception, error and status interrupts\n// ..\n\n// CAN driver functions structure\n\nextern \\\nARM_DRIVER_CAN Driver_CAN0;\nARM_DRIVER_CAN Driver_CAN0 = {\n  ARM_CAN_GetVersion,\n  ARM_CAN_GetCapabilities,\n  ARM_CAN_Initialize,\n  ARM_CAN_Uninitialize,\n  ARM_CAN_PowerControl,\n  ARM_CAN_GetClock,\n  ARM_CAN_SetBitrate,\n  ARM_CAN_SetMode,\n  ARM_CAN_ObjectGetCapabilities,\n  ARM_CAN_ObjectSetFilter,\n  ARM_CAN_ObjectConfigure,\n  ARM_CAN_MessageSend,\n  ARM_CAN_MessageRead,\n  ARM_CAN_Control,\n  ARM_CAN_GetStatus\n};\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_MAC.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"Driver_ETH_MAC.h\"\n\n#define ARM_ETH_MAC_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = {\n    ARM_ETH_MAC_API_VERSION,\n    ARM_ETH_MAC_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_ETH_MAC_CAPABILITIES DriverCapabilities = {\n    0, /* 1 = IPv4 header checksum verified on receive */\n    0, /* 1 = IPv6 checksum verification supported on receive */\n    0, /* 1 = UDP payload checksum verified on receive */\n    0, /* 1 = TCP payload checksum verified on receive */\n    0, /* 1 = ICMP payload checksum verified on receive */\n    0, /* 1 = IPv4 header checksum generated on transmit */\n    0, /* 1 = IPv6 checksum generation supported on transmit */\n    0, /* 1 = UDP payload checksum generated on transmit */\n    0, /* 1 = TCP payload checksum generated on transmit */\n    0, /* 1 = ICMP payload checksum generated on transmit */\n    0, /* Ethernet Media Interface type */\n    0, /* 1 = driver provides initial valid MAC address */\n    0, /* 1 = callback event \\ref ARM_ETH_MAC_EVENT_RX_FRAME generated */\n    0, /* 1 = callback event \\ref ARM_ETH_MAC_EVENT_TX_FRAME generated */\n    0, /* 1 = wakeup event \\ref ARM_ETH_MAC_EVENT_WAKEUP generated */\n    0, /* 1 = Precision Timer supported */\n    0  /* Reserved (must be zero) */\n};\n\n//\n//  Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion(void)\n{\n  return DriverVersion;\n}\n\nstatic ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities(void)\n{\n  return DriverCapabilities;\n}\n\nstatic int32_t ARM_ETH_MAC_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_Uninitialize(void)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_PowerControl(ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_ETH_MAC_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_SendFrame(const uint8_t *frame, uint32_t len, uint32_t flags)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_ReadFrame(uint8_t *frame, uint32_t len)\n{\n}\n\nstatic uint32_t ARM_ETH_MAC_GetRxFrameSize(void)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_GetRxFrameTime(ARM_ETH_MAC_TIME *time)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_GetTxFrameTime(ARM_ETH_MAC_TIME *time)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_Control(uint32_t control, uint32_t arg)\n{\n    switch (control)\n    {\n    case ARM_ETH_MAC_CONFIGURE:\n\n        switch (arg & ARM_ETH_MAC_SPEED_Msk)\n        {\n        case ARM_ETH_MAC_SPEED_10M:\n            break;\n        case ARM_ETH_SPEED_100M:\n            break;\n        default:\n            return ARM_DRIVER_ERROR_UNSUPPORTED;\n        }\n\n        switch (arg & ARM_ETH_MAC_DUPLEX_Msk)\n        {\n        case ARM_ETH_MAC_DUPLEX_FULL:\n            break;\n        }\n\n        if (arg & ARM_ETH_MAC_LOOPBACK)\n        {\n        }\n\n        if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) ||\n            (arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX))\n        {\n            return ARM_DRIVER_ERROR_UNSUPPORTED;\n        }\n\n        if (!(arg & ARM_ETH_MAC_ADDRESS_BROADCAST))\n        {\n        }\n\n        if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST)\n        {\n        }\n\n        if (arg & ARM_ETH_MAC_ADDRESS_ALL)\n        {\n        }\n\n        break;\n\n    case ARM_ETH_MAC_CONTROL_TX:\n        break;\n\n    case ARM_ETH_MAC_CONTROL_RX:\n        break;\n\n    case ARM_ETH_MAC_FLUSH:\n        if (arg & ARM_ETH_MAC_FLUSH_RX)\n        {\n        }\n        if (arg & ARM_ETH_MAC_FLUSH_TX)\n        {\n        }\n        break;\n\n    case ARM_ETH_MAC_SLEEP:\n        break;\n\n    case ARM_ETH_MAC_VLAN_FILTER:\n        break;\n\n    default:\n        return ARM_DRIVER_ERROR_UNSUPPORTED;\n    }\n}\n\nstatic int32_t ARM_ETH_MAC_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_PHY_Read(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)\n{\n}\n\nstatic int32_t ARM_ETH_MAC_PHY_Write(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)\n{\n}\n\nstatic void ARM_ETH_MAC_SignalEvent(uint32_t event)\n{\n}\n\n// End ETH MAC Interface\n\nextern \\\nARM_DRIVER_ETH_MAC Driver_ETH_MAC0;\nARM_DRIVER_ETH_MAC Driver_ETH_MAC0 =\n{\n    ARM_ETH_MAC_GetVersion,\n    ARM_ETH_MAC_GetCapabilities,\n    ARM_ETH_MAC_Initialize,\n    ARM_ETH_MAC_Uninitialize,\n    ARM_ETH_MAC_PowerControl,\n    ARM_ETH_MAC_GetMacAddress,\n    ARM_ETH_MAC_SetMacAddress,\n    ARM_ETH_MAC_SetAddressFilter,\n    ARM_ETH_MAC_SendFrame,\n    ARM_ETH_MAC_ReadFrame,\n    ARM_ETH_MAC_GetRxFrameSize,\n    ARM_ETH_MAC_GetRxFrameTime,\n    ARM_ETH_MAC_GetTxFrameTime,\n    ARM_ETH_MAC_ControlTimer,\n    ARM_ETH_MAC_Control,\n    ARM_ETH_MAC_PHY_Read,\n    ARM_ETH_MAC_PHY_Write\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_ETH_PHY.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_ETH_PHY.h\"\n\n#define ARM_ETH_PHY_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = {\n    ARM_ETH_PHY_API_VERSION,\n    ARM_ETH_PHY_DRV_VERSION\n};\n\n//\n// Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion(void)\n{\n  return DriverVersion;\n}\n\nstatic int32_t ARM_ETH_PHY_Initialize(ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write)\n{\n}\n\nstatic int32_t ARM_ETH_PHY_Uninitialize(void)\n{\n}\n\nstatic int32_t ARM_ETH_PHY_PowerControl(ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_ETH_PHY_SetInterface(uint32_t interface)\n{\n    switch (interface)\n    {\n    case ARM_ETH_INTERFACE_MII:\n        break;\n    case ARM_ETH_INTERFACE_RMII:\n        break;\n    default:\n        return ARM_DRIVER_ERROR_UNSUPPORTED;\n    }\n}\n\nstatic int32_t ARM_ETH_PHY_SetMode(uint32_t mode)\n{\n    switch (mode & ARM_ETH_PHY_SPEED_Msk)\n    {\n    case ARM_ETH_PHY_SPEED_10M:\n        break;\n    case ARM_ETH_PHY_SPEED_100M:\n        break;\n    default:\n        return ARM_DRIVER_ERROR_UNSUPPORTED;\n    }\n\n    switch (mode & ARM_ETH_PHY_DUPLEX_Msk)\n    {\n    case ARM_ETH_PHY_DUPLEX_HALF:\n        break;\n    case ARM_ETH_PHY_DUPLEX_FULL:\n        break;\n    }\n\n    if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE)\n    {\n    }\n\n    if (mode & ARM_ETH_PHY_LOOPBACK)\n    {\n    }\n\n    if (mode & ARM_ETH_PHY_ISOLATE)\n    {\n    }\n}\n\nstatic ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState(void)\n{\n}\n\nstatic ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo(void)\n{\n}\n\nextern \\\nARM_DRIVER_ETH_PHY Driver_ETH_PHY0;\nARM_DRIVER_ETH_PHY Driver_ETH_PHY0 =\n{\n    ARM_ETH_PHY_GetVersion,\n    ARM_ETH_PHY_Initialize,\n    ARM_ETH_PHY_Uninitialize,\n    ARM_ETH_PHY_PowerControl,\n    ARM_ETH_PHY_SetInterface,\n    ARM_ETH_PHY_SetMode,\n    ARM_ETH_PHY_GetLinkState,\n    ARM_ETH_PHY_GetLinkInfo,\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Flash.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_Flash.h\"\n\n#define ARM_FLASH_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Sector Information */\n#ifdef FLASH_SECTORS\nstatic ARM_FLASH_SECTOR FLASH_SECTOR_INFO[FLASH_SECTOR_COUNT] = {\n    FLASH_SECTORS\n};\n#else\n#define FLASH_SECTOR_INFO    NULL\n#endif\n\n/* Flash Information */\nstatic ARM_FLASH_INFO FlashInfo = {\n    0, /* FLASH_SECTOR_INFO  */\n    0, /* FLASH_SECTOR_COUNT */\n    0, /* FLASH_SECTOR_SIZE  */\n    0, /* FLASH_PAGE_SIZE    */\n    0, /* FLASH_PROGRAM_UNIT */\n    0, /* FLASH_ERASED_VALUE */\n  { 0, 0, 0 }  /* Reserved (must be zero) */\n};\n\n/* Flash Status */\nstatic ARM_FLASH_STATUS FlashStatus;\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = {\n    ARM_FLASH_API_VERSION,\n    ARM_FLASH_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_FLASH_CAPABILITIES DriverCapabilities = {\n    0, /* event_ready */\n    0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */\n    0, /* erase_chip */\n    0  /* reserved (must be zero) */\n};\n\n//\n// Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)\n{\n  return DriverVersion;\n}\n\nstatic ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)\n{\n  return DriverCapabilities;\n}\n\nstatic int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)\n{\n}\n\nstatic int32_t ARM_Flash_Uninitialize(void)\n{\n}\n\nstatic int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)\n{\n}\n\nstatic int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt)\n{\n}\n\nstatic int32_t ARM_Flash_EraseSector(uint32_t addr)\n{\n}\n\nstatic int32_t ARM_Flash_EraseChip(void)\n{\n}\n\nstatic ARM_FLASH_STATUS ARM_Flash_GetStatus(void)\n{\n  return FlashStatus;\n}\n\nstatic ARM_FLASH_INFO * ARM_Flash_GetInfo(void)\n{\n  return &FlashInfo;\n}\n\nstatic void ARM_Flash_SignalEvent(uint32_t event)\n{\n}\n\n// End Flash Interface\n\nextern \\\nARM_DRIVER_FLASH Driver_Flash0;\nARM_DRIVER_FLASH Driver_Flash0 = {\n    ARM_Flash_GetVersion,\n    ARM_Flash_GetCapabilities,\n    ARM_Flash_Initialize,\n    ARM_Flash_Uninitialize,\n    ARM_Flash_PowerControl,\n    ARM_Flash_ReadData,\n    ARM_Flash_ProgramData,\n    ARM_Flash_EraseSector,\n    ARM_Flash_EraseChip,\n    ARM_Flash_GetStatus,\n    ARM_Flash_GetInfo\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_I2C.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_I2C.h\"\n\n#define ARM_I2C_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = {\n    ARM_I2C_API_VERSION,\n    ARM_I2C_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_I2C_CAPABILITIES DriverCapabilities = {\n    0  /* supports 10-bit addressing */\n};\n\n//\n//  Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_I2C_GetVersion(void)\n{\n  return DriverVersion;\n}\n\nstatic ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities(void)\n{\n  return DriverCapabilities;\n}\n\nstatic int32_t ARM_I2C_Initialize(ARM_I2C_SignalEvent_t cb_event)\n{\n}\n\nstatic int32_t ARM_I2C_Uninitialize(void)\n{\n}\n\nstatic int32_t ARM_I2C_PowerControl(ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_I2C_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)\n{\n}\n\nstatic int32_t ARM_I2C_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)\n{\n}\n\nstatic int32_t ARM_I2C_SlaveTransmit(const uint8_t *data, uint32_t num)\n{\n}\n\nstatic int32_t ARM_I2C_SlaveReceive(uint8_t *data, uint32_t num)\n{\n}\n\nstatic int32_t ARM_I2C_GetDataCount(void)\n{\n}\n\nstatic int32_t ARM_I2C_Control(uint32_t control, uint32_t arg)\n{\n    switch (control)\n    {\n    case ARM_I2C_OWN_ADDRESS:\n        break;\n\n    case ARM_I2C_BUS_SPEED:\n        switch (arg)\n        {\n        case ARM_I2C_BUS_SPEED_STANDARD:\n            break;\n        case ARM_I2C_BUS_SPEED_FAST:\n            break;\n        case ARM_I2C_BUS_SPEED_FAST_PLUS:\n            break;\n        default:\n            return ARM_DRIVER_ERROR_UNSUPPORTED;\n        }\n        break;\n\n    case ARM_I2C_BUS_CLEAR:\n        break;\n\n    case ARM_I2C_ABORT_TRANSFER:\n        break;\n\n    default:\n        return ARM_DRIVER_ERROR_UNSUPPORTED;\n    }\n}\n\nstatic ARM_I2C_STATUS ARM_I2C_GetStatus(void)\n{\n}\n\nstatic void ARM_I2C_SignalEvent(uint32_t event)\n{\n    // function body\n}\n\n// End I2C Interface\n\nextern \\\nARM_DRIVER_I2C Driver_I2C0;\nARM_DRIVER_I2C Driver_I2C0 = {\n    ARM_I2C_GetVersion,\n    ARM_I2C_GetCapabilities,\n    ARM_I2C_Initialize,\n    ARM_I2C_Uninitialize,\n    ARM_I2C_PowerControl,\n    ARM_I2C_MasterTransmit,\n    ARM_I2C_MasterReceive,\n    ARM_I2C_SlaveTransmit,\n    ARM_I2C_SlaveReceive,\n    ARM_I2C_GetDataCount,\n    ARM_I2C_Control,\n    ARM_I2C_GetStatus\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_MCI.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_MCI.h\"\n\n#define ARM_MCI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = {\n    ARM_MCI_API_VERSION,\n    ARM_MCI_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_MCI_CAPABILITIES DriverCapabilities = {\n    0, /* cd_state          */\n    0, /* cd_event          */\n    0, /* wp_state          */\n    0, /* vdd               */\n    0, /* vdd_1v8           */\n    0, /* vccq              */\n    0, /* vccq_1v8          */\n    0, /* vccq_1v2          */\n    0, /* data_width_4      */\n    0, /* data_width_8      */\n    0, /* data_width_4_ddr  */\n    0, /* data_width_8_ddr  */\n    0, /* high_speed        */\n    0, /* uhs_signaling     */\n    0, /* uhs_tuning        */\n    0, /* uhs_sdr50         */\n    0, /* uhs_sdr104        */\n    0, /* uhs_ddr50         */\n    0, /* uhs_driver_type_a */\n    0, /* uhs_driver_type_c */\n    0, /* uhs_driver_type_d */\n    0, /* sdio_interrupt    */\n    0, /* read_wait         */\n    0, /* suspend_resume    */\n    0, /* mmc_interrupt     */\n    0, /* mmc_boot          */\n    0, /* rst_n             */\n    0, /* ccs               */\n    0, /* ccs_timeout       */\n    0  /* Reserved          */\n};\n\n//\n//   Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_MCI_GetVersion(void)\n{\n  return DriverVersion;\n}\n\nstatic ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities(void)\n{\n  return DriverCapabilities;\n}\n\nstatic int32_t ARM_MCI_Initialize(ARM_MCI_SignalEvent_t cb_event)\n{\n}\n\nstatic int32_t ARM_MCI_Uninitialize(void)\n{\n}\n\nstatic int32_t ARM_MCI_PowerControl(ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_MCI_CardPower(uint32_t voltage)\n{\n    switch (voltage & ARM_MCI_POWER_VDD_Msk)\n    {\n    case ARM_MCI_POWER_VDD_OFF:\n        return ARM_DRIVER_OK;\n\n    case ARM_MCI_POWER_VDD_3V3:\n        return ARM_DRIVER_OK;\n\n    default:\n        break;\n    }\n    return ARM_DRIVER_ERROR;\n}\n\nstatic int32_t ARM_MCI_ReadCD(void)\n{\n}\n\nstatic int32_t ARM_MCI_ReadWP(void)\n{\n}\n\nstatic int32_t ARM_MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response)\n{\n}\n\nstatic int32_t ARM_MCI_SetupTransfer(uint8_t  *data, uint32_t block_count, uint32_t block_size, uint32_t mode)\n{\n}\n\nstatic int32_t ARM_MCI_AbortTransfer(void)\n{\n}\n\nstatic int32_t ARM_MCI_Control(uint32_t control, uint32_t arg)\n{\n    switch (control)\n    {\n    case ARM_MCI_BUS_SPEED:\n        break;\n\n    case ARM_MCI_BUS_SPEED_MODE:\n        break;\n\n    case ARM_MCI_BUS_CMD_MODE:\n        /* Implement external pull-up control to support MMC cards in open-drain mode */\n        /* Default mode is push-pull and is configured in Driver_MCI0.Initialize()    */\n        if (arg == ARM_MCI_BUS_CMD_PUSH_PULL)\n        {\n            /* Configure external circuit to work in push-pull mode */\n        }\n        else if (arg == ARM_MCI_BUS_CMD_OPEN_DRAIN)\n        {\n            /* Configure external circuit to work in open-drain mode */\n        }\n        else\n        {\n            return ARM_DRIVER_ERROR_UNSUPPORTED;\n        }\n        break;\n\n    case ARM_MCI_BUS_DATA_WIDTH:\n        switch (arg)\n        {\n        case ARM_MCI_BUS_DATA_WIDTH_1:\n            break;\n        case ARM_MCI_BUS_DATA_WIDTH_4:\n            break;\n        case ARM_MCI_BUS_DATA_WIDTH_8:\n            break;\n        default:\n            return ARM_DRIVER_ERROR_UNSUPPORTED;\n        }\n        break;\n\n    case ARM_MCI_CONTROL_RESET:\n        break;\n\n    case ARM_MCI_CONTROL_CLOCK_IDLE:\n        break;\n\n    case ARM_MCI_DATA_TIMEOUT:\n        break;\n\n    case ARM_MCI_MONITOR_SDIO_INTERRUPT:\n        break;\n\n    case ARM_MCI_CONTROL_READ_WAIT:\n        break;\n\n    case ARM_MCI_DRIVER_STRENGTH:\n    default: return ARM_DRIVER_ERROR_UNSUPPORTED;\n    }\n}\n\nstatic ARM_MCI_STATUS ARM_MCI_GetStatus(void)\n{\n}\n\nstatic void ARM_MCI_SignalEvent(uint32_t event)\n{\n    // function body\n}\n\n// End MCI Interface\n\nextern \\\nARM_DRIVER_MCI Driver_MCI0;\nARM_DRIVER_MCI Driver_MCI0 = {\n    ARM_MCI_GetVersion,\n    ARM_MCI_GetCapabilities,\n    ARM_MCI_Initialize,\n    ARM_MCI_Uninitialize,\n    ARM_MCI_PowerControl,\n    ARM_MCI_CardPower,\n    ARM_MCI_ReadCD,\n    ARM_MCI_ReadWP,\n    ARM_MCI_SendCommand,\n    ARM_MCI_SetupTransfer,\n    ARM_MCI_AbortTransfer,\n    ARM_MCI_Control,\n    ARM_MCI_GetStatus\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_NAND.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_NAND.h\"\n\n#define ARM_NAND_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)   /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = {\n  ARM_NAND_API_VERSION,\n  ARM_NAND_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_NAND_CAPABILITIES DriverCapabilities = {\n  0,                 /* Signal Device Ready event (R/Bn rising edge)                        */\n  0,                 /* Supports re-entrant operation (SendCommand/Address, Read/WriteData) */\n  0,                 /* Supports Sequence operation (ExecuteSequence, AbortSequence)        */\n  0,                 /* Supports VCC Power Supply Control                                   */\n  0,                 /* Supports 1.8 VCC Power Supply                                       */\n  0,                 /* Supports VCCQ I/O Power Supply Control                              */\n  0,                 /* Supports 1.8 VCCQ I/O Power Supply                                  */\n  0,                 /* Supports VPP High Voltage Power Supply Control                      */\n  0,                 /* Supports WPn (Write Protect) Control                                */\n  0,                 /* Number of CEn (Chip Enable) lines: ce_lines + 1                     */\n  0,                 /* Supports manual CEn (Chip Enable) Control                           */\n  0,                 /* Supports R/Bn (Ready/Busy) Monitoring                               */\n  0,                 /* Supports 16-bit data                                                */\n  0,                 /* Supports NV-DDR  Data Interface (ONFI)                              */\n  0,                 /* Supports NV-DDR2 Data Interface (ONFI)                              */\n  0,                 /* Fastest (highest) SDR     Timing Mode supported (ONFI)              */\n  0,                 /* Fastest (highest) NV_DDR  Timing Mode supported (ONFI)              */\n  0,                 /* Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)              */\n  0,                 /* Supports Driver Strength 2.0x = 18 Ohms                             */\n  0,                 /* Supports Driver Strength 1.4x = 25 Ohms                             */\n  0,                 /* Supports Driver Strength 0.7x = 50 Ohms                             */\n#if (ARM_NAND_API_VERSION > 0x201U)\n  0                  /* Reserved (must be zero)                                             */\n#endif\n};\n\n/* Exported functions */\n\nstatic ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) {\n  return DriverVersion;\n}\n\nstatic ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void) {\n  return DriverCapabilities;\n}\n\nstatic int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_Uninitialize (void) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state) {\n\n  switch ((int32_t)state) {\n    case ARM_POWER_OFF:\n      return ARM_DRIVER_ERROR_UNSUPPORTED;\n\n    case ARM_POWER_LOW:\n      return ARM_DRIVER_ERROR_UNSUPPORTED;\n\n    case ARM_POWER_FULL:\n      return ARM_DRIVER_ERROR_UNSUPPORTED;\n\n    default:\n      return ARM_DRIVER_ERROR_UNSUPPORTED;\n  }\n  return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_NAND_DevicePower (uint32_t voltage) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,\n                                         uint32_t addr_col, uint32_t addr_row,\n                                         void *data, uint32_t data_cnt,\n                                         uint8_t *status, uint32_t *count) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_AbortSequence (uint32_t dev_num) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg) {\n\n  switch (control) {\n    case ARM_NAND_BUS_MODE:\n      return ARM_DRIVER_ERROR_UNSUPPORTED;\n\n    case ARM_NAND_BUS_DATA_WIDTH:\n      return ARM_DRIVER_ERROR_UNSUPPORTED; \n\n    case ARM_NAND_DEVICE_READY_EVENT:\n      return ARM_DRIVER_ERROR_UNSUPPORTED;\n\n    default:\n      return ARM_DRIVER_ERROR_UNSUPPORTED;\n  }\n\n  return ARM_DRIVER_ERROR;\n}\n\nstatic ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num) {\n  ARM_NAND_STATUS stat;\n\n  stat.busy      = 0U;\n  stat.ecc_error = 0U;\n\n  return stat;\n}\n\nstatic int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\n/* NAND Driver Control Block */\nextern \\\nARM_DRIVER_NAND Driver_NAND0;\nARM_DRIVER_NAND Driver_NAND0 = {\n  ARM_NAND_GetVersion,\n  ARM_NAND_GetCapabilities,\n  ARM_NAND_Initialize,\n  ARM_NAND_Uninitialize,\n  ARM_NAND_PowerControl,\n  ARM_NAND_DevicePower,\n  ARM_NAND_WriteProtect,\n  ARM_NAND_ChipEnable,\n  ARM_NAND_GetDeviceBusy,\n  ARM_NAND_SendCommand,\n  ARM_NAND_SendAddress,\n  ARM_NAND_ReadData,\n  ARM_NAND_WriteData,\n  ARM_NAND_ExecuteSequence,\n  ARM_NAND_AbortSequence,\n  ARM_NAND_Control,\n  ARM_NAND_GetStatus,\n  ARM_NAND_InquireECC\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SAI.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_SAI.h\"\n\n#define ARM_SAI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = {\n    ARM_SAI_API_VERSION,\n    ARM_SAI_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_SAI_CAPABILITIES DriverCapabilities = {\n    1, /* supports asynchronous Transmit/Receive */\n    0, /* supports synchronous Transmit/Receive */\n    0, /* supports user defined Protocol */\n    1, /* supports I2S Protocol */\n    0, /* supports MSB/LSB justified Protocol */\n    0, /* supports PCM short/long frame Protocol */\n    0, /* supports AC'97 Protocol */\n    0, /* supports Mono mode */\n    0, /* supports Companding */\n    0, /* supports MCLK (Master Clock) pin */\n    0, /* supports Frame error event: \\ref ARM_SAI_EVENT_FRAME_ERROR */\n    0  /* reserved (must be zero) */\n};\n\n//\n//  Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)\n{\n  return DriverVersion;\n}\n\nstatic ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)\n{\n  return DriverCapabilities;\n}\n\nstatic int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)\n{\n}\n\nstatic int32_t ARM_SAI_Uninitialize (void)\n{\n}\n\nstatic int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_SAI_Send (const void *data, uint32_t num)\n{\n}\n\nstatic int32_t ARM_SAI_Receive (void *data, uint32_t num)\n{\n}\n\nstatic uint32_t ARM_SAI_GetTxCount (void)\n{\n}\n\nstatic uint32_t ARM_SAI_GetRxCount (void)\n{\n}\n\nstatic int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)\n{\n}\n\nstatic ARM_SAI_STATUS ARM_SAI_GetStatus (void)\n{\n}\n\nstatic void ARM_SAI_SignalEvent(uint32_t event)\n{\n    // function body\n}\n\n// End SAI Interface\n\nextern \\\nARM_DRIVER_SAI Driver_SAI0;\nARM_DRIVER_SAI Driver_SAI0 = {\n    ARM_SAI_GetVersion,\n    ARM_SAI_GetCapabilities,\n    ARM_SAI_Initialize,\n    ARM_SAI_Uninitialize,\n    ARM_SAI_PowerControl,\n    ARM_SAI_Send,\n    ARM_SAI_Receive,\n    ARM_SAI_GetTxCount,\n    ARM_SAI_GetRxCount,\n    ARM_SAI_Control,\n    ARM_SAI_GetStatus\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_SPI.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_SPI.h\"\n\n#define ARM_SPI_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = {\n    ARM_SPI_API_VERSION,\n    ARM_SPI_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_SPI_CAPABILITIES DriverCapabilities = {\n    0, /* Reserved (must be zero) */\n    0, /* TI Synchronous Serial Interface */\n    0, /* Microwire Interface */\n    0, /* Signal Mode Fault event: \\ref ARM_SPI_EVENT_MODE_FAULT */\n    0  /* Reserved (must be zero) */\n};\n\n//\n//  Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_SPI_GetVersion(void)\n{\n  return DriverVersion;\n}\n\nstatic ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities(void)\n{\n  return DriverCapabilities;\n}\n\nstatic int32_t ARM_SPI_Initialize(ARM_SPI_SignalEvent_t cb_event)\n{\n}\n\nstatic int32_t ARM_SPI_Uninitialize(void)\n{\n}\n\nstatic int32_t ARM_SPI_PowerControl(ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_SPI_Send(const void *data, uint32_t num)\n{\n}\n\nstatic int32_t ARM_SPI_Receive(void *data, uint32_t num)\n{\n}\n\nstatic int32_t ARM_SPI_Transfer(const void *data_out, void *data_in, uint32_t num)\n{\n}\n\nstatic uint32_t ARM_SPI_GetDataCount(void)\n{\n}\n\nstatic int32_t ARM_SPI_Control(uint32_t control, uint32_t arg)\n{\n    switch (control & ARM_SPI_CONTROL_Msk)\n    {\n    default:\n        return ARM_DRIVER_ERROR_UNSUPPORTED;\n\n    case ARM_SPI_MODE_INACTIVE:             // SPI Inactive\n        return ARM_DRIVER_OK;\n\n    case ARM_SPI_MODE_MASTER:               // SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps\n        break;\n\n    case ARM_SPI_MODE_SLAVE:                // SPI Slave  (Output on MISO, Input on MOSI)\n        break;\n\n    case ARM_SPI_SET_BUS_SPEED:             // Set Bus Speed in bps; arg = value\n        break;\n\n    case ARM_SPI_GET_BUS_SPEED:             // Get Bus Speed in bps\n        break;\n\n    case ARM_SPI_SET_DEFAULT_TX_VALUE:      // Set default Transmit value; arg = value\n        break;\n\n    case ARM_SPI_CONTROL_SS:                // Control Slave Select; arg = 0:inactive, 1:active\n        break;\n\n    case ARM_SPI_ABORT_TRANSFER:            // Abort current data transfer\n        break;\n    }\n}\n\nstatic ARM_SPI_STATUS ARM_SPI_GetStatus(void)\n{\n}\n\nstatic void ARM_SPI_SignalEvent(uint32_t event)\n{\n    // function body\n}\n\n// End SPI Interface\n\nextern \\\nARM_DRIVER_SPI Driver_SPI0;\nARM_DRIVER_SPI Driver_SPI0 = {\n    ARM_SPI_GetVersion,\n    ARM_SPI_GetCapabilities,\n    ARM_SPI_Initialize,\n    ARM_SPI_Uninitialize,\n    ARM_SPI_PowerControl,\n    ARM_SPI_Send,\n    ARM_SPI_Receive,\n    ARM_SPI_Transfer,\n    ARM_SPI_GetDataCount,\n    ARM_SPI_Control,\n    ARM_SPI_GetStatus\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_Storage.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#include \"Driver_Storage.h\"\n\n#define ARM_STORAGE_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = {\n    ARM_STORAGE_API_VERSION,\n    ARM_STORAGE_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_STORAGE_CAPABILITIES DriverCapabilities = {\n    0,  /* Asynchronous Mode */\n    0,  /* Supports EraseAll operation */\n    0   /* Reserved */\n};\n\n\n//\n// Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_Storage_GetVersion (void)  {\n  return DriverVersion;\n}\n\nstatic ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void)  {\n  return DriverCapabilities;\n}\n\nstatic int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback)  {\n}\n\nstatic int32_t ARM_Storage_Uninitialize (void)  {\n}\n\nstatic int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size)  {\n}\n\nstatic int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size)  {\n}\n\nstatic int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size)  {\n}\n\nstatic int32_t ARM_Storage_EraseAll (void)  {\n}\n\nstatic ARM_STORAGE_STATUS ARM_Storage_GetStatus (void)  {\n}\n\nstatic int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info)  {\n}\n\nstatic uint32_t ARM_Storage_ResolveAddress(uint64_t addr) {\n}\n\nstatic int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block) {\n}\n\nstatic int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block) {\n}\n\n// End Storage Interface\n\nextern \\\nARM_DRIVER_STORAGE Driver_Storage0;\nARM_DRIVER_STORAGE Driver_Storage0 = {\n    ARM_Storage_GetVersion,\n    ARM_Storage_GetCapabilities,\n    ARM_Storage_Initialize,\n    ARM_Storage_Uninitialize,\n    ARM_Storage_PowerControl,\n    ARM_Storage_ReadData,\n    ARM_Storage_ProgramData,\n    ARM_Storage_Erase,\n    ARM_Storage_EraseAll,\n    ARM_Storage_GetStatus,\n    ARM_Storage_GetInfo,\n    ARM_Storage_ResolveAddress,\n    ARM_Storage_GetNextBlock,\n    ARM_Storage_GetBlock\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USART.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"Driver_USART.h\"\n\n#define ARM_USART_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)  /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION DriverVersion = { \n    ARM_USART_API_VERSION,\n    ARM_USART_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_USART_CAPABILITIES DriverCapabilities = {\n    1, /* supports UART (Asynchronous) mode */\n    0, /* supports Synchronous Master mode */\n    0, /* supports Synchronous Slave mode */\n    0, /* supports UART Single-wire mode */\n    0, /* supports UART IrDA mode */\n    0, /* supports UART Smart Card mode */\n    0, /* Smart Card Clock generator available */\n    0, /* RTS Flow Control available */\n    0, /* CTS Flow Control available */\n    0, /* Transmit completed event: \\ref ARM_USART_EVENT_TX_COMPLETE */\n    0, /* Signal receive character timeout event: \\ref ARM_USART_EVENT_RX_TIMEOUT */\n    0, /* RTS Line: 0=not available, 1=available */\n    0, /* CTS Line: 0=not available, 1=available */\n    0, /* DTR Line: 0=not available, 1=available */\n    0, /* DSR Line: 0=not available, 1=available */\n    0, /* DCD Line: 0=not available, 1=available */\n    0, /* RI Line: 0=not available, 1=available */\n    0, /* Signal CTS change event: \\ref ARM_USART_EVENT_CTS */\n    0, /* Signal DSR change event: \\ref ARM_USART_EVENT_DSR */\n    0, /* Signal DCD change event: \\ref ARM_USART_EVENT_DCD */\n    0, /* Signal RI change event: \\ref ARM_USART_EVENT_RI */\n    0  /* Reserved (must be zero) */\n};\n\n//\n//   Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_USART_GetVersion(void)\n{\n  return DriverVersion;\n}\n\nstatic ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)\n{\n  return DriverCapabilities;\n}\n\nstatic int32_t ARM_USART_Initialize(ARM_USART_SignalEvent_t cb_event)\n{\n}\n\nstatic int32_t ARM_USART_Uninitialize(void)\n{\n}\n\nstatic int32_t ARM_USART_PowerControl(ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_USART_Send(const void *data, uint32_t num)\n{\n}\n\nstatic int32_t ARM_USART_Receive(void *data, uint32_t num)\n{\n}\n\nstatic int32_t ARM_USART_Transfer(const void *data_out, void *data_in, uint32_t num)\n{\n}\n\nstatic uint32_t ARM_USART_GetTxCount(void)\n{\n}\n\nstatic uint32_t ARM_USART_GetRxCount(void)\n{\n}\n\nstatic int32_t ARM_USART_Control(uint32_t control, uint32_t arg)\n{\n}\n\nstatic ARM_USART_STATUS ARM_USART_GetStatus(void)\n{\n}\n\nstatic int32_t ARM_USART_SetModemControl(ARM_USART_MODEM_CONTROL control)\n{\n}\n\nstatic ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus(void)\n{\n}\n\nstatic void ARM_USART_SignalEvent(uint32_t event)\n{\n    // function body\n}\n\n// End USART Interface\n\nextern \\\nARM_DRIVER_USART Driver_USART0;\nARM_DRIVER_USART Driver_USART0 = {\n    ARM_USART_GetVersion,\n    ARM_USART_GetCapabilities,\n    ARM_USART_Initialize,\n    ARM_USART_Uninitialize,\n    ARM_USART_PowerControl,\n    ARM_USART_Send,\n    ARM_USART_Receive,\n    ARM_USART_Transfer,\n    ARM_USART_GetTxCount,\n    ARM_USART_GetRxCount,\n    ARM_USART_Control,\n    ARM_USART_GetStatus,\n    ARM_USART_SetModemControl,\n    ARM_USART_GetModemStatus\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBD.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_USBD.h\"\n\n#define ARM_USBD_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION usbd_driver_version = { \n    ARM_USBD_API_VERSION,\n    ARM_USBD_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_USBD_CAPABILITIES usbd_driver_capabilities = {\n    0, /* vbus_detection */\n    0, /* event_vbus_on */\n    0, /* event_vbus_off */\n    0  /* reserved */\n};\n\n//\n// Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_USBD_GetVersion(void)\n{\n  return usbd_driver_version;\n}\n\nstatic ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities(void)\n{\n  return usbd_driver_capabilities;\n}\n\nstatic int32_t ARM_USBD_Initialize(ARM_USBD_SignalDeviceEvent_t cb_device_event,\n                                   ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)\n{\n}\n\nstatic int32_t ARM_USBD_Uninitialize(void)\n{\n}\n\nstatic int32_t ARM_USBD_PowerControl(ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_USBD_DeviceConnect(void)\n{\n}\n\nstatic int32_t ARM_USBD_DeviceDisconnect(void)\n{\n}\n\nstatic ARM_USBD_STATE ARM_USBD_DeviceGetState(void)\n{\n}\n\nstatic int32_t ARM_USBD_DeviceRemoteWakeup(void)\n{\n}\n\nstatic int32_t ARM_USBD_DeviceSetAddress(uint8_t dev_addr)\n{\n}\n\nstatic int32_t ARM_USBD_ReadSetupPacket(uint8_t *setup)\n{\n}\n\nstatic int32_t ARM_USBD_EndpointConfigure(uint8_t  ep_addr,\n                                          uint8_t  ep_type,\n                                          uint16_t ep_max_packet_size)\n{\n}\n\nstatic int32_t ARM_USBD_EndpointUnconfigure(uint8_t ep_addr)\n{\n}\n\nstatic int32_t ARM_USBD_EndpointStall(uint8_t ep_addr, bool stall)\n{\n}\n\nstatic int32_t ARM_USBD_EndpointTransfer(uint8_t ep_addr, uint8_t *data, uint32_t num)\n{\n}\n\nstatic uint32_t ARM_USBD_EndpointTransferGetResult(uint8_t ep_addr)\n{\n}\n\nstatic int32_t ARM_USBD_EndpointTransferAbort(uint8_t ep_addr)\n{\n}\n\nstatic uint16_t ARM_USBD_GetFrameNumber(void)\n{\n}\n\nstatic void ARM_USBD_SignalDeviceEvent(uint32_t event)\n{\n    // function body\n}\n\nstatic void ARM_USBD_SignalEndpointEvent(uint8_t ep_addr, uint32_t ep_event)\n{\n    // function body\n}\n\n// End USBD Interface\n\nextern \\\nARM_DRIVER_USBD Driver_USBD0;\nARM_DRIVER_USBD Driver_USBD0 =\n{\n    ARM_USBD_GetVersion,\n    ARM_USBD_GetCapabilities,\n    ARM_USBD_Initialize,\n    ARM_USBD_Uninitialize,\n    ARM_USBD_PowerControl,\n    ARM_USBD_DeviceConnect,\n    ARM_USBD_DeviceDisconnect,\n    ARM_USBD_DeviceGetState,\n    ARM_USBD_DeviceRemoteWakeup,\n    ARM_USBD_DeviceSetAddress,\n    ARM_USBD_ReadSetupPacket,\n    ARM_USBD_EndpointConfigure,\n    ARM_USBD_EndpointUnconfigure,\n    ARM_USBD_EndpointStall,\n    ARM_USBD_EndpointTransfer,\n    ARM_USBD_EndpointTransferGetResult,\n    ARM_USBD_EndpointTransferAbort,\n    ARM_USBD_GetFrameNumber\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_USBH.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"Driver_USBH.h\"\n\n/* USB Host Driver */\n\n#define ARM_USBH_DRV_VERSION    ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */\n\n/* Driver Version */\nstatic const ARM_DRIVER_VERSION usbh_driver_version = { \n    ARM_USBH_API_VERSION,\n    ARM_USBH_DRV_VERSION\n};\n\n/* Driver Capabilities */\nstatic const ARM_USBH_CAPABILITIES usbd_driver_capabilities = {\n    0x0001, /* Root HUB available Ports Mask   */\n    0,      /* Automatic SPLIT packet handling */\n    0,      /* Signal Connect event */\n    0,      /* Signal Disconnect event */\n    0,      /* Signal Overcurrent event */\n    0       /* Reserved (must be zero) */\n};\n\n//\n// Functions\n//\n\nstatic ARM_DRIVER_VERSION ARM_USBH_GetVersion(void)\n{\n  return usbh_driver_version;\n}\n\nstatic ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities(void)\n{\n  return usbd_driver_capabilities;\n}\n\nstatic int32_t ARM_USBH_Initialize(ARM_USBH_SignalPortEvent_t cb_port_event,\n                                   ARM_USBH_SignalPipeEvent_t cb_pipe_event)\n{\n}\n\nstatic int32_t ARM_USBH_Uninitialize(void)\n{\n}\n\nstatic int32_t ARM_USBH_PowerControl(ARM_POWER_STATE state)\n{\n    switch (state)\n    {\n    case ARM_POWER_OFF:\n        break;\n\n    case ARM_POWER_LOW:\n        break;\n\n    case ARM_POWER_FULL:\n        break;\n    }\n    return ARM_DRIVER_OK;\n}\n\nstatic int32_t ARM_USBH_PortVbusOnOff(uint8_t port, bool vbus)\n{\n}\n\nstatic int32_t ARM_USBH_PortReset(uint8_t port)\n{\n}\n\nstatic int32_t ARM_USBH_PortSuspend(uint8_t port)\n{\n}\n\nstatic int32_t ARM_USBH_PortResume(uint8_t port)\n{\n}\n\nstatic ARM_USBH_PORT_STATE ARM_USBH_PortGetState(uint8_t port)\n{\n}\n\nstatic ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate(uint8_t  dev_addr,\n                                                uint8_t  dev_speed,\n                                                uint8_t  hub_addr,\n                                                uint8_t  hub_port,\n                                                uint8_t  ep_addr,\n                                                uint8_t  ep_type,\n                                                uint16_t ep_max_packet_size,\n                                                uint8_t  ep_interval)\n{\n}\n\nstatic int32_t ARM_USBH_PipeModify(ARM_USBH_PIPE_HANDLE pipe_hndl,\n                            uint8_t  dev_addr,\n                            uint8_t  dev_speed,\n                            uint8_t  hub_addr,\n                            uint8_t  hub_port,\n                            uint16_t ep_max_packet_size)\n{\n}\n\nstatic int32_t ARM_USBH_PipeDelete(ARM_USBH_PIPE_HANDLE pipe_hndl)\n{\n}\n\nstatic int32_t ARM_USBH_PipeReset(ARM_USBH_PIPE_HANDLE pipe_hndl)\n{\n}\n\nstatic int32_t ARM_USBH_PipeTransfer(ARM_USBH_PIPE_HANDLE pipe_hndl,\n                              uint32_t packet,\n                              uint8_t *data,\n                              uint32_t num)\n{\n}\n\nstatic uint32_t ARM_USBH_PipeTransferGetResult(ARM_USBH_PIPE_HANDLE pipe_hndl)\n{\n}\n\nstatic int32_t ARM_USBH_PipeTransferAbort(ARM_USBH_PIPE_HANDLE pipe_hndl)\n{\n}\n\nstatic uint16_t ARM_USBH_GetFrameNumber(void)\n{\n}\n\nstatic void ARM_USBH_SignalPortEvent(uint8_t port, uint32_t event)\n{\n    // function body\n}\n\nstatic void ARM_USBH_SignalPipeEvent(ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)\n{\n    // function body\n}\n\n// End USBH Interface\n\nextern \\\nARM_DRIVER_USBH Driver_USBH0;\nARM_DRIVER_USBH Driver_USBH0 = {\n  ARM_USBH_GetVersion,\n  ARM_USBH_GetCapabilities,\n  ARM_USBH_Initialize,\n  ARM_USBH_Uninitialize,\n  ARM_USBH_PowerControl,\n  ARM_USBH_PortVbusOnOff,\n  ARM_USBH_PortReset,\n  ARM_USBH_PortSuspend,\n  ARM_USBH_PortResume,\n  ARM_USBH_PortGetState,\n  ARM_USBH_PipeCreate,\n  ARM_USBH_PipeModify,\n  ARM_USBH_PipeDelete,\n  ARM_USBH_PipeReset,\n  ARM_USBH_PipeTransfer,\n  ARM_USBH_PipeTransferGetResult,\n  ARM_USBH_PipeTransferAbort,\n  ARM_USBH_GetFrameNumber\n};\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/DriverTemplates/Driver_WiFi.c",
    "content": "/*\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"Driver_WiFi.h\"\n\n#define ARM_WIFI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)        // Driver version\n\n// Driver Version\nstatic const ARM_DRIVER_VERSION driver_version = {\n  ARM_WIFI_API_VERSION,\n  ARM_WIFI_DRV_VERSION \n};\n\n// Driver Capabilities\nstatic const ARM_WIFI_CAPABILITIES driver_capabilities = { \n  0U,                                   // Station supported\n  0U,                                   // Access Point supported\n  0U,                                   // Concurrent Station and Access Point not supported\n  0U,                                   // WiFi Protected Setup (WPS) for Station supported\n  0U,                                   // WiFi Protected Setup (WPS) for Access Point not supported\n  0U,                                   // Access Point: event generated on Station connect\n  0U,                                   // Access Point: event not generated on Station disconnect\n  0U,                                   // Event not generated on Ethernet frame reception in bypass mode\n  0U,                                   // Bypass or pass-through mode (Ethernet interface) not supported\n  0U,                                   // IP (UDP/TCP) (Socket interface) supported\n  0U,                                   // IPv6 (Socket interface) not supported\n  0U,                                   // Ping (ICMP) supported\n  0U                                    // Reserved (must be zero)\n};\nstatic ARM_DRIVER_VERSION ARM_WiFi_GetVersion (void) {\n  return driver_version;\n}\n\nstatic ARM_WIFI_CAPABILITIES ARM_WiFi_GetCapabilities (void) { \n  return driver_capabilities;\n}\n\nstatic int32_t ARM_WiFi_Initialize (ARM_WIFI_SignalEvent_t cb_event) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_Uninitialize (void) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_PowerControl (ARM_POWER_STATE state) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_GetModuleInfo (char *module_info, uint32_t max_len) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\nstatic int32_t ARM_WiFi_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_Activate (uint32_t interface, const ARM_WIFI_CONFIG_t *config) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_Deactivate (uint32_t interface) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic uint32_t ARM_WiFi_IsConnected (void) {\n  return 0U;\n}\n\nstatic int32_t ARM_WiFi_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_BypassControl (uint32_t interface, uint32_t mode) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len){\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len){\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic uint32_t ARM_WiFi_EthGetRxFrameSize (uint32_t interface){\n  return 0U;\n}\n\nstatic int32_t ARM_WiFi_SocketCreate (int32_t af, int32_t type, int32_t protocol) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketListen (int32_t socket, int32_t backlog) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketRecv (int32_t socket, void *buf, uint32_t len) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketSend (int32_t socket, const void *buf, uint32_t len) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketClose (int32_t socket) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\nstatic int32_t ARM_WiFi_Ping (const uint8_t *ip, uint32_t ip_len) {\n  return ARM_DRIVER_ERROR_UNSUPPORTED;\n}\n\n/* WiFi Driver Control Block */\nextern \\\nARM_DRIVER_WIFI Driver_WiFi0;\nARM_DRIVER_WIFI Driver_WiFi0 = { \n  ARM_WiFi_GetVersion,\n  ARM_WiFi_GetCapabilities,\n  ARM_WiFi_Initialize,\n  ARM_WiFi_Uninitialize,\n  ARM_WiFi_PowerControl,\n  ARM_WiFi_GetModuleInfo,\n  ARM_WiFi_SetOption,\n  ARM_WiFi_GetOption,\n  ARM_WiFi_Scan,\n  ARM_WiFi_Activate,\n  ARM_WiFi_Deactivate,\n  ARM_WiFi_IsConnected,\n  ARM_WiFi_GetNetInfo,\n  ARM_WiFi_BypassControl,\n  ARM_WiFi_EthSendFrame,\n  ARM_WiFi_EthReadFrame,\n  ARM_WiFi_EthGetRxFrameSize,\n  ARM_WiFi_SocketCreate,\n  ARM_WiFi_SocketBind,\n  ARM_WiFi_SocketListen,\n  ARM_WiFi_SocketAccept,\n  ARM_WiFi_SocketConnect,\n  ARM_WiFi_SocketRecv,\n  ARM_WiFi_SocketRecvFrom,\n  ARM_WiFi_SocketSend,\n  ARM_WiFi_SocketSendTo,\n  ARM_WiFi_SocketGetSockName,\n  ARM_WiFi_SocketGetPeerName,\n  ARM_WiFi_SocketGetOpt,\n  ARM_WiFi_SocketSetOpt,\n  ARM_WiFi_SocketClose,\n  ARM_WiFi_SocketGetHostByName,\n  ARM_WiFi_Ping\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_CAN.h",
    "content": "/*\n * Copyright (c) 2015-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        31. March 2020\n * $Revision:    V1.3\n *\n * Project:      CAN (Controller Area Network) Driver definitions\n */\n\n/* History:\n *  Version 1.3\n *    Removed volatile from ARM_CAN_STATUS\n *  Version 1.2\n *    Added ARM_CAN_UNIT_STATE_BUS_OFF unit state and\n *    ARM_CAN_EVENT_UNIT_INACTIVE unit event\n *  Version 1.1\n *    ARM_CAN_STATUS made volatile\n *  Version 1.0\n *    Initial release\n */\n\n#ifndef DRIVER_CAN_H_\n#define DRIVER_CAN_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,3)  /* API version */\n\n\n#define _ARM_Driver_CAN_(n)      Driver_CAN##n\n#define  ARM_Driver_CAN_(n) _ARM_Driver_CAN_(n)\n\n\n/****** CAN Bitrate selection codes *****/\ntypedef enum _ARM_CAN_BITRATE_SELECT {\n  ARM_CAN_BITRATE_NOMINAL,              ///< Select nominal (flexible data-rate arbitration) bitrate\n  ARM_CAN_BITRATE_FD_DATA               ///< Select flexible data-rate data bitrate\n} ARM_CAN_BITRATE_SELECT;\n\n/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/\n#define ARM_CAN_BIT_PROP_SEG_Pos        0UL       ///< bits 7..0\n#define ARM_CAN_BIT_PROP_SEG_Msk       (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos)\n#define ARM_CAN_BIT_PROP_SEG(x)      (((x)     << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk)\n\n/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/\n#define ARM_CAN_BIT_PHASE_SEG1_Pos      8UL       ///< bits 15..8\n#define ARM_CAN_BIT_PHASE_SEG1_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos)\n#define ARM_CAN_BIT_PHASE_SEG1(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk)\n\n/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/\n#define ARM_CAN_BIT_PHASE_SEG2_Pos      16UL      ///< bits 23..16\n#define ARM_CAN_BIT_PHASE_SEG2_Msk     (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos)\n#define ARM_CAN_BIT_PHASE_SEG2(x)    (((x)     << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk)\n\n/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/\n#define ARM_CAN_BIT_SJW_Pos             24UL      ///< bits 28..24\n#define ARM_CAN_BIT_SJW_Msk            (0x1FUL << ARM_CAN_BIT_SJW_Pos)\n#define ARM_CAN_BIT_SJW(x)           (((x)     << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk)\n\n/****** CAN Mode codes *****/\ntypedef enum _ARM_CAN_MODE {\n  ARM_CAN_MODE_INITIALIZATION,          ///< Initialization mode\n  ARM_CAN_MODE_NORMAL,                  ///< Normal operation mode\n  ARM_CAN_MODE_RESTRICTED,              ///< Restricted operation mode\n  ARM_CAN_MODE_MONITOR,                 ///< Bus monitoring mode\n  ARM_CAN_MODE_LOOPBACK_INTERNAL,       ///< Loopback internal mode\n  ARM_CAN_MODE_LOOPBACK_EXTERNAL        ///< Loopback external mode\n} ARM_CAN_MODE;\n\n/****** CAN Filter Operation codes *****/\ntypedef enum _ARM_CAN_FILTER_OPERATION {\n  ARM_CAN_FILTER_ID_EXACT_ADD,          ///< Add    exact id filter\n  ARM_CAN_FILTER_ID_EXACT_REMOVE,       ///< Remove exact id filter\n  ARM_CAN_FILTER_ID_RANGE_ADD,          ///< Add    range id filter\n  ARM_CAN_FILTER_ID_RANGE_REMOVE,       ///< Remove range id filter\n  ARM_CAN_FILTER_ID_MASKABLE_ADD,       ///< Add    maskable id filter\n  ARM_CAN_FILTER_ID_MASKABLE_REMOVE     ///< Remove maskable id filter\n} ARM_CAN_FILTER_OPERATION;\n\n/****** CAN Object Configuration codes *****/\ntypedef enum _ARM_CAN_OBJ_CONFIG {\n  ARM_CAN_OBJ_INACTIVE,                 ///< CAN object inactive\n  ARM_CAN_OBJ_TX,                       ///< CAN transmit object\n  ARM_CAN_OBJ_RX,                       ///< CAN receive object\n  ARM_CAN_OBJ_RX_RTR_TX_DATA,           ///< CAN object that on RTR reception automatically transmits Data Frame\n  ARM_CAN_OBJ_TX_RTR_RX_DATA            ///< CAN object that transmits RTR and automatically receives Data Frame\n} ARM_CAN_OBJ_CONFIG;\n\n/**\n\\brief CAN Object Capabilities\n*/\ntypedef struct _ARM_CAN_OBJ_CAPABILITIES {\n  uint32_t tx               : 1;        ///< Object supports transmission\n  uint32_t rx               : 1;        ///< Object supports reception\n  uint32_t rx_rtr_tx_data   : 1;        ///< Object supports RTR reception and automatic Data Frame transmission\n  uint32_t tx_rtr_rx_data   : 1;        ///< Object supports RTR transmission and automatic Data Frame reception\n  uint32_t multiple_filters : 1;        ///< Object allows assignment of multiple filters to it\n  uint32_t exact_filtering  : 1;        ///< Object supports exact identifier filtering\n  uint32_t range_filtering  : 1;        ///< Object supports range identifier filtering\n  uint32_t mask_filtering   : 1;        ///< Object supports mask identifier filtering\n  uint32_t message_depth    : 8;        ///< Number of messages buffers (FIFO) for that object\n  uint32_t reserved         : 16;       ///< Reserved (must be zero)\n} ARM_CAN_OBJ_CAPABILITIES;\n\n/****** CAN Control Function Operation codes *****/\n#define ARM_CAN_CONTROL_Pos             0UL\n#define ARM_CAN_CONTROL_Msk            (0xFFUL << ARM_CAN_CONTROL_Pos)\n#define ARM_CAN_SET_FD_MODE            (1UL    << ARM_CAN_CONTROL_Pos)          ///< Set FD operation mode;                   arg: 0 = disable, 1 = enable\n#define ARM_CAN_ABORT_MESSAGE_SEND     (2UL    << ARM_CAN_CONTROL_Pos)          ///< Abort sending of CAN message;            arg = object\n#define ARM_CAN_CONTROL_RETRANSMISSION (3UL    << ARM_CAN_CONTROL_Pos)          ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state)\n#define ARM_CAN_SET_TRANSCEIVER_DELAY  (4UL    << ARM_CAN_CONTROL_Pos)          ///< Set transceiver delay;                   arg = delay in time quanta\n\n/****** CAN ID Frame Format codes *****/\n#define ARM_CAN_ID_IDE_Pos              31UL\n#define ARM_CAN_ID_IDE_Msk             (1UL    << ARM_CAN_ID_IDE_Pos)\n\n/****** CAN Identifier encoding *****/\n#define ARM_CAN_STANDARD_ID(id)        (id & 0x000007FFUL)                      ///< CAN identifier in standard format (11-bits)\n#define ARM_CAN_EXTENDED_ID(id)       ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits)\n\n/**\n\\brief CAN Message Information\n*/\ntypedef struct _ARM_CAN_MSG_INFO {\n  uint32_t id;                          ///< CAN identifier with frame format specifier (bit 31)\n  uint32_t rtr              : 1;        ///< Remote transmission request frame\n  uint32_t edl              : 1;        ///< Flexible data-rate format extended data length\n  uint32_t brs              : 1;        ///< Flexible data-rate format with bitrate switch \n  uint32_t esi              : 1;        ///< Flexible data-rate format error state indicator\n  uint32_t dlc              : 4;        ///< Data length code\n  uint32_t reserved         : 24;\n} ARM_CAN_MSG_INFO;\n\n/****** CAN specific error code *****/\n#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1)          ///< Bitrate selection not supported\n#define ARM_CAN_INVALID_BITRATE        (ARM_DRIVER_ERROR_SPECIFIC - 2)          ///< Requested bitrate not supported\n#define ARM_CAN_INVALID_BIT_PROP_SEG   (ARM_DRIVER_ERROR_SPECIFIC - 3)          ///< Propagation segment value not supported\n#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4)          ///< Phase segment 1 value not supported\n#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5)          ///< Phase segment 2 value not supported\n#define ARM_CAN_INVALID_BIT_SJW        (ARM_DRIVER_ERROR_SPECIFIC - 6)          ///< SJW value not supported\n#define ARM_CAN_NO_MESSAGE_AVAILABLE   (ARM_DRIVER_ERROR_SPECIFIC - 7)          ///< Message is not available\n\n/****** CAN Status codes *****/\n#define ARM_CAN_UNIT_STATE_INACTIVE    (0U)             ///< Unit state: Not active on bus (initialization)\n#define ARM_CAN_UNIT_STATE_ACTIVE      (1U)             ///< Unit state: Active on bus (can generate active error frame)\n#define ARM_CAN_UNIT_STATE_PASSIVE     (2U)             ///< Unit state: Error passive (can not generate active error frame)\n#define ARM_CAN_UNIT_STATE_BUS_OFF     (3U)             ///< Unit state: Bus-off (can recover to active state)\n#define ARM_CAN_LEC_NO_ERROR           (0U)             ///< Last error code: No error\n#define ARM_CAN_LEC_BIT_ERROR          (1U)             ///< Last error code: Bit error\n#define ARM_CAN_LEC_STUFF_ERROR        (2U)             ///< Last error code: Bit stuffing error\n#define ARM_CAN_LEC_CRC_ERROR          (3U)             ///< Last error code: CRC error\n#define ARM_CAN_LEC_FORM_ERROR         (4U)             ///< Last error code: Illegal fixed-form bit\n#define ARM_CAN_LEC_ACK_ERROR          (5U)             ///< Last error code: Acknowledgment error\n\n/**\n\\brief CAN Status\n*/\ntypedef struct _ARM_CAN_STATUS {\n  uint32_t unit_state       : 4;        ///< Unit bus state\n  uint32_t last_error_code  : 4;        ///< Last error code\n  uint32_t tx_error_count   : 8;        ///< Transmitter error count\n  uint32_t rx_error_count   : 8;        ///< Receiver error count\n  uint32_t reserved         : 8;\n} ARM_CAN_STATUS;\n\n\n/****** CAN Unit Event *****/\n#define ARM_CAN_EVENT_UNIT_INACTIVE    (0U)             ///< Unit entered Inactive state\n#define ARM_CAN_EVENT_UNIT_ACTIVE      (1U)             ///< Unit entered Error Active state\n#define ARM_CAN_EVENT_UNIT_WARNING     (2U)             ///< Unit entered Error Warning state (one or both error counters >= 96)\n#define ARM_CAN_EVENT_UNIT_PASSIVE     (3U)             ///< Unit entered Error Passive state\n#define ARM_CAN_EVENT_UNIT_BUS_OFF     (4U)             ///< Unit entered Bus-off state\n\n/****** CAN Send/Receive Event *****/\n#define ARM_CAN_EVENT_SEND_COMPLETE    (1UL << 0)       ///< Send complete\n#define ARM_CAN_EVENT_RECEIVE          (1UL << 1)       ///< Message received\n#define ARM_CAN_EVENT_RECEIVE_OVERRUN  (1UL << 2)       ///< Received message overrun\n\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_CAN_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n\n  \\fn          ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_CAN_CAPABILITIES\n\n  \\fn          int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t   cb_unit_event,\n                                           ARM_CAN_SignalObjectEvent_t cb_object_event)\n  \\brief       Initialize CAN interface and register signal (callback) functions.\n  \\param[in]   cb_unit_event   Pointer to \\ref ARM_CAN_SignalUnitEvent callback function\n  \\param[in]   cb_object_event Pointer to \\ref ARM_CAN_SignalObjectEvent callback function\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_CAN_Uninitialize (void)\n  \\brief       De-initialize CAN interface.\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control CAN interface power.\n  \\param[in]   state  Power state\n                 - \\ref ARM_POWER_OFF :  power off: no operation possible\n                 - \\ref ARM_POWER_LOW :  low power mode: retain state, detect and signal wake-up events\n                 - \\ref ARM_POWER_FULL : power on: full operation at maximum performance\n  \\return      \\ref execution_status\n\n  \\fn          uint32_t ARM_CAN_GetClock (void)\n  \\brief       Retrieve CAN base clock frequency.\n  \\return      base clock frequency\n\n  \\fn          int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments)\n  \\brief       Set bitrate for CAN interface.\n  \\param[in]   select       Bitrate selection\n                 - \\ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate\n                 - \\ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate\n  \\param[in]   bitrate      Bitrate\n  \\param[in]   bit_segments Bit segments settings\n                 - \\ref ARM_CAN_BIT_PROP_SEG(x) :   number of time quanta for propagation time segment\n                 - \\ref ARM_CAN_BIT_PHASE_SEG1(x) : number of time quanta for phase buffer segment 1\n                 - \\ref ARM_CAN_BIT_PHASE_SEG2(x) : number of time quanta for phase buffer Segment 2\n                 - \\ref ARM_CAN_BIT_SJW(x) :        number of time quanta for (re-)synchronization jump width\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode)\n  \\brief       Set operating mode for CAN interface.\n  \\param[in]   mode   Operating mode\n                 - \\ref ARM_CAN_MODE_INITIALIZATION :    initialization mode\n                 - \\ref ARM_CAN_MODE_NORMAL :            normal operation mode\n                 - \\ref ARM_CAN_MODE_RESTRICTED :        restricted operation mode\n                 - \\ref ARM_CAN_MODE_MONITOR :           bus monitoring mode\n                 - \\ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode\n                 - \\ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode\n  \\return      \\ref execution_status\n\n  \\fn          ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx)\n  \\brief       Retrieve capabilities of an object.\n  \\param[in]   obj_idx  Object index\n  \\return      \\ref ARM_CAN_OBJ_CAPABILITIES\n\n  \\fn          int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg)\n  \\brief       Add or remove filter for message reception.\n  \\param[in]   obj_idx      Object index of object that filter should be or is assigned to\n  \\param[in]   operation    Operation on filter\n                 - \\ref ARM_CAN_FILTER_ID_EXACT_ADD :       add    exact id filter\n                 - \\ref ARM_CAN_FILTER_ID_EXACT_REMOVE :    remove exact id filter\n                 - \\ref ARM_CAN_FILTER_ID_RANGE_ADD :       add    range id filter\n                 - \\ref ARM_CAN_FILTER_ID_RANGE_REMOVE :    remove range id filter\n                 - \\ref ARM_CAN_FILTER_ID_MASKABLE_ADD :    add    maskable id filter\n                 - \\ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter\n  \\param[in]   id           ID or start of ID range (depending on filter type)\n  \\param[in]   arg          Mask or end of ID range (depending on filter type)\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg)\n  \\brief       Configure object.\n  \\param[in]   obj_idx  Object index\n  \\param[in]   obj_cfg  Object configuration state\n                 - \\ref ARM_CAN_OBJ_INACTIVE :       deactivate object\n                 - \\ref ARM_CAN_OBJ_RX :             configure object for reception\n                 - \\ref ARM_CAN_OBJ_TX :             configure object for transmission\n                 - \\ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame\n                 - \\ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size)\n  \\brief       Send message on CAN bus.\n  \\param[in]   obj_idx  Object index\n  \\param[in]   msg_info Pointer to CAN message information\n  \\param[in]   data     Pointer to data buffer\n  \\param[in]   size     Number of data bytes to send\n  \\return      value >= 0  number of data bytes accepted to send\n  \\return      value < 0   \\ref execution_status\n\n  \\fn          int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size)\n  \\brief       Read message received on CAN bus.\n  \\param[in]   obj_idx  Object index\n  \\param[out]  msg_info Pointer to read CAN message information\n  \\param[out]  data     Pointer to data buffer for read data\n  \\param[in]   size     Maximum number of data bytes to read\n  \\return      value >= 0  number of data bytes read\n  \\return      value < 0   \\ref execution_status\n\n  \\fn          int32_t ARM_CAN_Control (uint32_t control, uint32_t arg)\n  \\brief       Control CAN interface.\n  \\param[in]   control  Operation\n                 - \\ref ARM_CAN_SET_FD_MODE :            set FD operation mode\n                 - \\ref ARM_CAN_ABORT_MESSAGE_SEND :     abort sending of CAN message\n                 - \\ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission\n                 - \\ref ARM_CAN_SET_TRANSCEIVER_DELAY :  set transceiver delay\n  \\param[in]   arg      Argument of operation\n  \\return      \\ref execution_status\n\n  \\fn          ARM_CAN_STATUS ARM_CAN_GetStatus (void)\n  \\brief       Get CAN status.\n  \\return      CAN status \\ref ARM_CAN_STATUS\n\n  \\fn          void ARM_CAN_SignalUnitEvent (uint32_t event)\n  \\brief       Signal CAN unit event.\n  \\param[in]   event \\ref CAN_unit_events\n  \\return      none\n\n  \\fn          void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event)\n  \\brief       Signal CAN object event.\n  \\param[in]   obj_idx  Object index\n  \\param[in]   event \\ref CAN_events\n  \\return      none\n*/\n\ntypedef void (*ARM_CAN_SignalUnitEvent_t)   (uint32_t event);                   ///< Pointer to \\ref ARM_CAN_SignalUnitEvent   : Signal CAN Unit Event.\ntypedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \\ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event.\n\n\n/**\n\\brief CAN Device Driver Capabilities.\n*/\ntypedef struct _ARM_CAN_CAPABILITIES {\n  uint32_t num_objects            : 8;  ///< Number of \\ref can_objects available\n  uint32_t reentrant_operation    : 1;  ///< Support for reentrant calls to \\ref ARM_CAN_MessageSend, \\ref ARM_CAN_MessageRead, \\ref ARM_CAN_ObjectConfigure and abort message sending used by \\ref ARM_CAN_Control\n  uint32_t fd_mode                : 1;  ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \\ref ARM_CAN_Control)\n  uint32_t restricted_mode        : 1;  ///< Support for restricted operation mode (set by \\ref ARM_CAN_SetMode)\n  uint32_t monitor_mode           : 1;  ///< Support for bus monitoring mode (set by \\ref ARM_CAN_SetMode)\n  uint32_t internal_loopback      : 1;  ///< Support for internal loopback mode (set by \\ref ARM_CAN_SetMode)\n  uint32_t external_loopback      : 1;  ///< Support for external loopback mode (set by \\ref ARM_CAN_SetMode)\n  uint32_t reserved               : 18; ///< Reserved (must be zero)\n} ARM_CAN_CAPABILITIES;\n\n\n/**\n\\brief Access structure of the CAN Driver.\n*/\ntypedef struct _ARM_DRIVER_CAN {\n  ARM_DRIVER_VERSION       (*GetVersion)            (void);                             ///< Pointer to \\ref ARM_CAN_GetVersion            : Get driver version.\n  ARM_CAN_CAPABILITIES     (*GetCapabilities)       (void);                             ///< Pointer to \\ref ARM_CAN_GetCapabilities       : Get driver capabilities.\n  int32_t                  (*Initialize)            (ARM_CAN_SignalUnitEvent_t   cb_unit_event,                     \n                                                     ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \\ref ARM_CAN_Initialize : Initialize CAN interface.\n  int32_t                  (*Uninitialize)          (void);                             ///< Pointer to \\ref ARM_CAN_Uninitialize          : De-initialize CAN interface.\n  int32_t                  (*PowerControl)          (ARM_POWER_STATE          state);   ///< Pointer to \\ref ARM_CAN_PowerControl          : Control CAN interface power.\n  uint32_t                 (*GetClock)              (void);                             ///< Pointer to \\ref ARM_CAN_GetClock              : Retrieve CAN base clock frequency.\n  int32_t                  (*SetBitrate)            (ARM_CAN_BITRATE_SELECT   select,\n                                                     uint32_t                 bitrate,\n                                                     uint32_t                 bit_segments);       ///< Pointer to \\ref ARM_CAN_SetBitrate : Set bitrate for CAN interface.\n  int32_t                  (*SetMode)               (ARM_CAN_MODE             mode);    ///< Pointer to \\ref ARM_CAN_SetMode               : Set operating mode for CAN interface.\n  ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t                 obj_idx); ///< Pointer to \\ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object.\n  int32_t                  (*ObjectSetFilter)       (uint32_t                 obj_idx,\n                                                     ARM_CAN_FILTER_OPERATION operation,\n                                                     uint32_t                 id,\n                                                     uint32_t                 arg);     ///< Pointer to \\ref ARM_CAN_ObjectSetFilter       : Add or remove filter for message reception.\n  int32_t                  (*ObjectConfigure)       (uint32_t                 obj_idx,\n                                                     ARM_CAN_OBJ_CONFIG       obj_cfg); ///< Pointer to \\ref ARM_CAN_ObjectConfigure       : Configure object.\n  int32_t                  (*MessageSend)           (uint32_t                 obj_idx,\n                                                     ARM_CAN_MSG_INFO        *msg_info,\n                                                     const uint8_t           *data,\n                                                     uint8_t                  size);    ///< Pointer to \\ref ARM_CAN_MessageSend           : Send message on CAN bus.\n  int32_t                  (*MessageRead)           (uint32_t                 obj_idx,\n                                                     ARM_CAN_MSG_INFO        *msg_info,\n                                                     uint8_t                 *data,\n                                                     uint8_t                  size);    ///< Pointer to \\ref ARM_CAN_MessageRead           : Read message received on CAN bus.\n  int32_t                  (*Control)               (uint32_t                 control,\n                                                     uint32_t                 arg);     ///< Pointer to \\ref ARM_CAN_Control               : Control CAN interface.\n  ARM_CAN_STATUS           (*GetStatus)             (void);                             ///< Pointer to \\ref ARM_CAN_GetStatus             : Get CAN status.\n} const ARM_DRIVER_CAN;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_CAN_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_Common.h",
    "content": "/*\n * Copyright (c) 2013-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        2. Feb 2017\n * $Revision:    V2.0\n *\n * Project:      Common Driver definitions\n */\n\n/* History:\n *  Version 2.0\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *    Added General return codes definitions\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_COMMON_H_\n#define DRIVER_COMMON_H_\n\n#include <stddef.h>\n#include <stdint.h>\n#include <stdbool.h>\n\n#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))\n\n/**\n\\brief Driver Version\n*/\ntypedef struct _ARM_DRIVER_VERSION {\n  uint16_t api;                         ///< API version\n  uint16_t drv;                         ///< Driver version\n} ARM_DRIVER_VERSION;\n\n/* General return codes */\n#define ARM_DRIVER_OK                 0 ///< Operation succeeded \n#define ARM_DRIVER_ERROR             -1 ///< Unspecified error\n#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy\n#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred\n#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported\n#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error\n#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors \n\n/**\n\\brief General power states\n*/ \ntypedef enum _ARM_POWER_STATE {\n  ARM_POWER_OFF,                        ///< Power off: no operation possible\n  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events\n  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance\n} ARM_POWER_STATE;\n\n#endif /* DRIVER_COMMON_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        24. January 2020\n * $Revision:    V2.2\n *\n * Project:      Ethernet PHY and MAC Driver common definitions\n */\n\n/* History:\n *  Version 2.2\n *    Removed volatile from ARM_ETH_LINK_INFO\n *  Version 2.1\n *    ARM_ETH_LINK_INFO made volatile\n *  Version 2.0\n *    Removed ARM_ETH_STATUS enumerator\n *    Removed ARM_ETH_MODE enumerator\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_ETH_H_\n#define DRIVER_ETH_H_\n\n#include \"Driver_Common.h\"\n\n/**\n\\brief Ethernet Media Interface type\n*/\n#define ARM_ETH_INTERFACE_MII           (0U)    ///< Media Independent Interface (MII)\n#define ARM_ETH_INTERFACE_RMII          (1U)    ///< Reduced Media Independent Interface (RMII)\n#define ARM_ETH_INTERFACE_SMII          (2U)    ///< Serial Media Independent Interface (SMII)\n\n/**\n\\brief Ethernet link speed\n*/\n#define ARM_ETH_SPEED_10M               (0U)    ///< 10 Mbps link speed\n#define ARM_ETH_SPEED_100M              (1U)    ///< 100 Mbps link speed\n#define ARM_ETH_SPEED_1G                (2U)    ///< 1 Gpbs link speed\n\n/**\n\\brief Ethernet duplex mode\n*/\n#define ARM_ETH_DUPLEX_HALF             (0U)    ///< Half duplex link\n#define ARM_ETH_DUPLEX_FULL             (1U)    ///< Full duplex link\n\n/**\n\\brief Ethernet link state\n*/\ntypedef enum _ARM_ETH_LINK_STATE {\n  ARM_ETH_LINK_DOWN,                    ///< Link is down\n  ARM_ETH_LINK_UP                       ///< Link is up\n} ARM_ETH_LINK_STATE;\n\n/**\n\\brief Ethernet link information\n*/\ntypedef struct _ARM_ETH_LINK_INFO {\n  uint32_t speed    : 2;                ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit\n  uint32_t duplex   : 1;                ///< Duplex mode: 0= Half, 1= Full\n  uint32_t reserved : 29;\n} ARM_ETH_LINK_INFO;\n\n/**\n\\brief Ethernet MAC Address\n*/\ntypedef struct _ARM_ETH_MAC_ADDR {\n  uint8_t b[6];                         ///< MAC Address (6 bytes), MSB first\n} ARM_ETH_MAC_ADDR;\n\n#endif /* DRIVER_ETH_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_MAC.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        24. January 2020\n * $Revision:    V2.2\n *\n * Project:      Ethernet MAC (Media Access Control) Driver definitions\n */\n\n/* History:\n *  Version 2.2\n *    Removed volatile from ARM_ETH_LINK_INFO\n *  Version 2.1\n *    Added ARM_ETH_MAC_SLEEP Control\n *  Version 2.0\n *    Changed MAC Address handling:\n *      moved from ARM_ETH_MAC_Initialize\n *      to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress\n *    Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter\n *    Extended ARM_ETH_MAC_SendFrame function with flags\n *    Added ARM_ETH_MAC_Control function:\n *      more control options (Broadcast, Multicast, Checksum offload, VLAN, ...)\n *      replaces ARM_ETH_MAC_SetMode\n *      replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx\n *    Added optional event on transmitted frame\n *    Added support for PTP (Precision Time Protocol) through new functions:\n *       ARM_ETH_MAC_ControlTimer\n *       ARM_ETH_MAC_GetRxFrameTime\n *       ARM_ETH_MAC_GetTxFrameTime\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *    Changed return values of some functions to int32_t\n *  Version 1.10\n *    Name space prefix ARM_ added\n *  Version 1.01\n *    Renamed capabilities items for checksum offload\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_ETH_MAC_H_\n#define DRIVER_ETH_MAC_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_ETH.h\"\n\n#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */\n\n\n#define _ARM_Driver_ETH_MAC_(n)      Driver_ETH_MAC##n\n#define  ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n)\n\n\n/****** Ethernet MAC Control Codes *****/\n\n#define ARM_ETH_MAC_CONFIGURE           (0x01UL)    ///< Configure MAC; arg = configuration\n#define ARM_ETH_MAC_CONTROL_TX          (0x02UL)    ///< Transmitter; arg: 0=disabled (default), 1=enabled\n#define ARM_ETH_MAC_CONTROL_RX          (0x03UL)    ///< Receiver; arg: 0=disabled (default), 1=enabled\n#define ARM_ETH_MAC_FLUSH               (0x04UL)    ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_...\n#define ARM_ETH_MAC_SLEEP               (0x05UL)    ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit\n#define ARM_ETH_MAC_VLAN_FILTER         (0x06UL)    ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)\n\n/*----- Ethernet MAC Configuration -----*/\n#define ARM_ETH_MAC_SPEED_Pos            0\n#define ARM_ETH_MAC_SPEED_Msk           (3UL                 << ARM_ETH_MAC_SPEED_Pos)\n#define ARM_ETH_MAC_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_MAC_SPEED_Pos)  ///< 10 Mbps link speed\n#define ARM_ETH_MAC_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_MAC_SPEED_Pos)  ///< 100 Mbps link speed\n#define ARM_ETH_MAC_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_MAC_SPEED_Pos)  ///< 1 Gpbs link speed\n#define ARM_ETH_MAC_DUPLEX_Pos           2\n#define ARM_ETH_MAC_DUPLEX_Msk          (1UL                 << ARM_ETH_MAC_DUPLEX_Pos)\n#define ARM_ETH_MAC_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link\n#define ARM_ETH_MAC_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link\n#define ARM_ETH_MAC_LOOPBACK            (1UL << 4)  ///< Loop-back test mode\n#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5)  ///< Receiver Checksum offload\n#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6)  ///< Transmitter Checksum offload\n#define ARM_ETH_MAC_ADDRESS_BROADCAST   (1UL << 7)  ///< Accept frames with Broadcast address\n#define ARM_ETH_MAC_ADDRESS_MULTICAST   (1UL << 8)  ///< Accept frames with any Multicast address\n#define ARM_ETH_MAC_ADDRESS_ALL         (1UL << 9)  ///< Accept frames with any address (Promiscuous Mode)\n\n/*----- Ethernet MAC Flush Flags -----*/\n#define ARM_ETH_MAC_FLUSH_RX            (1UL << 0)  ///< Flush Receive buffer\n#define ARM_ETH_MAC_FLUSH_TX            (1UL << 1)  ///< Flush Transmit buffer\n\n/*----- Ethernet MAC VLAN Filter Flag -----*/\n#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit)\n\n\n/****** Ethernet MAC Frame Transmit Flags *****/\n#define ARM_ETH_MAC_TX_FRAME_FRAGMENT   (1UL << 0)  ///< Indicate frame fragment\n#define ARM_ETH_MAC_TX_FRAME_EVENT      (1UL << 1)  ///< Generate event when frame is transmitted\n#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP  (1UL << 2)  ///< Capture frame time stamp\n\n\n/****** Ethernet MAC Timer Control Codes *****/\n#define ARM_ETH_MAC_TIMER_GET_TIME      (0x01UL)    ///< Get current time\n#define ARM_ETH_MAC_TIMER_SET_TIME      (0x02UL)    ///< Set new time\n#define ARM_ETH_MAC_TIMER_INC_TIME      (0x03UL)    ///< Increment current time\n#define ARM_ETH_MAC_TIMER_DEC_TIME      (0x04UL)    ///< Decrement current time\n#define ARM_ETH_MAC_TIMER_SET_ALARM     (0x05UL)    ///< Set alarm time\n#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK  (0x06UL)    ///< Adjust clock frequency; time->ns: correction factor * 2^31\n\n\n/**\n\\brief Ethernet MAC Time\n*/\ntypedef struct _ARM_ETH_MAC_TIME {\n  uint32_t ns;                          ///< Nano seconds\n  uint32_t sec;                         ///< Seconds\n} ARM_ETH_MAC_TIME;\n\n\n/****** Ethernet MAC Event *****/\n#define ARM_ETH_MAC_EVENT_RX_FRAME      (1UL << 0)  ///< Frame Received\n#define ARM_ETH_MAC_EVENT_TX_FRAME      (1UL << 1)  ///< Frame Transmitted\n#define ARM_ETH_MAC_EVENT_WAKEUP        (1UL << 2)  ///< Wake-up (on Magic Packet)\n#define ARM_ETH_MAC_EVENT_TIMER_ALARM   (1UL << 3)  ///< Timer Alarm\n\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn          ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_ETH_MAC_CAPABILITIES\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)\n  \\brief       Initialize Ethernet MAC Device.\n  \\param[in]   cb_event  Pointer to \\ref ARM_ETH_MAC_SignalEvent\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_Uninitialize (void)\n  \\brief       De-initialize Ethernet MAC Device.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control Ethernet MAC Device Power.\n  \\param[in]   state  Power state\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)\n  \\brief       Get Ethernet MAC Address.\n  \\param[in]   ptr_addr  Pointer to address\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)\n  \\brief       Set Ethernet MAC Address.\n  \\param[in]   ptr_addr  Pointer to address\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr,\n                                                           uint32_t          num_addr)\n  \\brief       Configure Address Filter.\n  \\param[in]   ptr_addr  Pointer to addresses\n  \\param[in]   num_addr  Number of addresses to configure\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)\n  \\brief       Send Ethernet frame.\n  \\param[in]   frame  Pointer to frame buffer with data to send\n  \\param[in]   len    Frame buffer length in bytes\n  \\param[in]   flags  Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...)\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)\n  \\brief       Read data of received Ethernet frame.\n  \\param[in]   frame  Pointer to frame buffer for data to read into\n  \\param[in]   len    Frame buffer length in bytes\n  \\return      number of data bytes read or execution status\n                 - value >= 0: number of data bytes read\n                 - value < 0: error occurred, value is execution status as defined with \\ref execution_status \n*/\n/**\n  \\fn          uint32_t ARM_ETH_MAC_GetRxFrameSize (void)\n  \\brief       Get size of received Ethernet frame.\n  \\return      number of bytes in received frame\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)\n  \\brief       Get time of received Ethernet frame.\n  \\param[in]   time  Pointer to time structure for data to read into\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)\n  \\brief       Get time of transmitted Ethernet frame.\n  \\param[in]   time  Pointer to time structure for data to read into\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)\n  \\brief       Control Ethernet Interface.\n  \\param[in]   control  Operation\n  \\param[in]   arg      Argument of operation (optional)\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)\n  \\brief       Control Precision Timer.\n  \\param[in]   control  Operation\n  \\param[in]   time     Pointer to time structure\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)\n  \\brief       Read Ethernet PHY Register through Management Interface.\n  \\param[in]   phy_addr  5-bit device address\n  \\param[in]   reg_addr  5-bit register address\n  \\param[out]  data      Pointer where the result is written to\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)\n  \\brief       Write Ethernet PHY Register through Management Interface.\n  \\param[in]   phy_addr  5-bit device address\n  \\param[in]   reg_addr  5-bit register address\n  \\param[in]   data      16-bit data to write\n  \\return      \\ref execution_status\n*/\n\n/**\n  \\fn          void ARM_ETH_MAC_SignalEvent (uint32_t event)\n  \\brief       Callback function that signals a Ethernet Event.\n  \\param[in]   event  event notification mask\n  \\return      none\n*/\n\ntypedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event);  ///< Pointer to \\ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event.\n\n\n/**\n\\brief Ethernet MAC Capabilities\n*/\ntypedef struct _ARM_ETH_MAC_CAPABILITIES {\n  uint32_t checksum_offload_rx_ip4  : 1;        ///< 1 = IPv4 header checksum verified on receive\n  uint32_t checksum_offload_rx_ip6  : 1;        ///< 1 = IPv6 checksum verification supported on receive\n  uint32_t checksum_offload_rx_udp  : 1;        ///< 1 = UDP payload checksum verified on receive\n  uint32_t checksum_offload_rx_tcp  : 1;        ///< 1 = TCP payload checksum verified on receive\n  uint32_t checksum_offload_rx_icmp : 1;        ///< 1 = ICMP payload checksum verified on receive\n  uint32_t checksum_offload_tx_ip4  : 1;        ///< 1 = IPv4 header checksum generated on transmit\n  uint32_t checksum_offload_tx_ip6  : 1;        ///< 1 = IPv6 checksum generation supported on transmit\n  uint32_t checksum_offload_tx_udp  : 1;        ///< 1 = UDP payload checksum generated on transmit\n  uint32_t checksum_offload_tx_tcp  : 1;        ///< 1 = TCP payload checksum generated on transmit\n  uint32_t checksum_offload_tx_icmp : 1;        ///< 1 = ICMP payload checksum generated on transmit\n  uint32_t media_interface          : 2;        ///< Ethernet Media Interface type\n  uint32_t mac_address              : 1;        ///< 1 = driver provides initial valid MAC address\n  uint32_t event_rx_frame           : 1;        ///< 1 = callback event \\ref ARM_ETH_MAC_EVENT_RX_FRAME generated\n  uint32_t event_tx_frame           : 1;        ///< 1 = callback event \\ref ARM_ETH_MAC_EVENT_TX_FRAME generated\n  uint32_t event_wakeup             : 1;        ///< 1 = wakeup event \\ref ARM_ETH_MAC_EVENT_WAKEUP generated\n  uint32_t precision_timer          : 1;        ///< 1 = Precision Timer supported\n  uint32_t reserved                 : 15;       ///< Reserved (must be zero)\n} ARM_ETH_MAC_CAPABILITIES;\n\n\n/**\n\\brief Access structure of the Ethernet MAC Driver\n*/\ntypedef struct _ARM_DRIVER_ETH_MAC {\n  ARM_DRIVER_VERSION       (*GetVersion)      (void);                                                ///< Pointer to \\ref ARM_ETH_MAC_GetVersion : Get driver version.\n  ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void);                                                ///< Pointer to \\ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities.\n  int32_t                  (*Initialize)      (ARM_ETH_MAC_SignalEvent_t cb_event);                  ///< Pointer to \\ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device.\n  int32_t                  (*Uninitialize)    (void);                                                ///< Pointer to \\ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device.\n  int32_t                  (*PowerControl)    (ARM_POWER_STATE state);                               ///< Pointer to \\ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power.\n  int32_t                  (*GetMacAddress)   (      ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \\ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address.\n  int32_t                  (*SetMacAddress)   (const ARM_ETH_MAC_ADDR *ptr_addr);                    ///< Pointer to \\ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address.\n  int32_t                  (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \\ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter.\n  int32_t                  (*SendFrame)       (const uint8_t *frame, uint32_t len, uint32_t flags);  ///< Pointer to \\ref ARM_ETH_MAC_SendFrame : Send Ethernet frame.\n  int32_t                  (*ReadFrame)       (      uint8_t *frame, uint32_t len);                  ///< Pointer to \\ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame.\n  uint32_t                 (*GetRxFrameSize)  (void);                                                ///< Pointer to \\ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame.\n  int32_t                  (*GetRxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \\ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame.\n  int32_t                  (*GetTxFrameTime)  (ARM_ETH_MAC_TIME *time);                              ///< Pointer to \\ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame.\n  int32_t                  (*ControlTimer)    (uint32_t control, ARM_ETH_MAC_TIME *time);            ///< Pointer to \\ref ARM_ETH_MAC_ControlTimer : Control Precision Timer.\n  int32_t                  (*Control)         (uint32_t control, uint32_t arg);                      ///< Pointer to \\ref ARM_ETH_MAC_Control : Control Ethernet Interface.\n  int32_t                  (*PHY_Read)        (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);  ///< Pointer to \\ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface.\n  int32_t                  (*PHY_Write)       (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data);  ///< Pointer to \\ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface.\n} const ARM_DRIVER_ETH_MAC;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_ETH_MAC_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_ETH_PHY.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        24. January 2020\n * $Revision:    V2.2\n *\n * Project:      Ethernet PHY (Physical Transceiver) Driver definitions\n */\n\n/* History:\n *  Version 2.2\n *    Removed volatile from ARM_ETH_LINK_INFO\n *  Version 2.1\n *    ARM_ETH_LINK_INFO made volatile\n *  Version 2.0\n *    changed parameter \"mode\" in function ARM_ETH_PHY_SetMode\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *    Changed return values of some functions to int32_t\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_ETH_PHY_H_\n#define DRIVER_ETH_PHY_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_ETH.h\"\n\n#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2)  /* API version */\n\n\n#define _ARM_Driver_ETH_PHY_(n)      Driver_ETH_PHY##n\n#define  ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n)\n\n\n/****** Ethernet PHY Mode *****/\n#define ARM_ETH_PHY_SPEED_Pos            0\n#define ARM_ETH_PHY_SPEED_Msk           (3UL                 << ARM_ETH_PHY_SPEED_Pos)\n#define ARM_ETH_PHY_SPEED_10M           (ARM_ETH_SPEED_10M   << ARM_ETH_PHY_SPEED_Pos)  ///< 10 Mbps link speed\n#define ARM_ETH_PHY_SPEED_100M          (ARM_ETH_SPEED_100M  << ARM_ETH_PHY_SPEED_Pos)  ///< 100 Mbps link speed\n#define ARM_ETH_PHY_SPEED_1G            (ARM_ETH_SPEED_1G    << ARM_ETH_PHY_SPEED_Pos)  ///< 1 Gpbs link speed\n#define ARM_ETH_PHY_DUPLEX_Pos           2\n#define ARM_ETH_PHY_DUPLEX_Msk          (1UL                 << ARM_ETH_PHY_DUPLEX_Pos)\n#define ARM_ETH_PHY_DUPLEX_HALF         (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link\n#define ARM_ETH_PHY_DUPLEX_FULL         (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link\n#define ARM_ETH_PHY_AUTO_NEGOTIATE      (1UL << 3)                                      ///< Auto Negotiation mode\n#define ARM_ETH_PHY_LOOPBACK            (1UL << 4)                                      ///< Loop-back test mode\n#define ARM_ETH_PHY_ISOLATE             (1UL << 5)                                      ///< Isolate PHY from MII/RMII interface\n\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn          int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t  fn_read,\n                                               ARM_ETH_PHY_Write_t fn_write)\n  \\brief       Initialize Ethernet PHY Device.\n  \\param[in]   fn_read   Pointer to \\ref ARM_ETH_MAC_PHY_Read\n  \\param[in]   fn_write  Pointer to \\ref ARM_ETH_MAC_PHY_Write\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_PHY_Uninitialize (void)\n  \\brief       De-initialize Ethernet PHY Device.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control Ethernet PHY Device Power.\n  \\param[in]   state  Power state\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_PHY_SetInterface (uint32_t interface)\n  \\brief       Set Ethernet Media Interface.\n  \\param[in]   interface  Media Interface type\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_ETH_PHY_SetMode (uint32_t mode)\n  \\brief       Set Ethernet PHY Device Operation mode.\n  \\param[in]   mode  Operation Mode\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)\n  \\brief       Get Ethernet PHY Device Link state.\n  \\return      current link status \\ref ARM_ETH_LINK_STATE\n*/\n/**\n  \\fn          ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)\n  \\brief       Get Ethernet PHY Device Link information.\n  \\return      current link parameters \\ref ARM_ETH_LINK_INFO\n*/\n\n\ntypedef int32_t (*ARM_ETH_PHY_Read_t)  (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \\ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register.\ntypedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t  data); ///< Pointer to \\ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register.\n\n\n/**\n\\brief Access structure of the Ethernet PHY Driver\n*/\ntypedef struct _ARM_DRIVER_ETH_PHY {\n  ARM_DRIVER_VERSION (*GetVersion)   (void);                          ///< Pointer to \\ref ARM_ETH_PHY_GetVersion : Get driver version.\n  int32_t            (*Initialize)   (ARM_ETH_PHY_Read_t  fn_read,\n                                      ARM_ETH_PHY_Write_t fn_write);  ///< Pointer to \\ref ARM_ETH_PHY_Initialize : Initialize PHY Device.\n  int32_t            (*Uninitialize) (void);                          ///< Pointer to \\ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device.\n  int32_t            (*PowerControl) (ARM_POWER_STATE state);         ///< Pointer to \\ref ARM_ETH_PHY_PowerControl : Control PHY Device Power.\n  int32_t            (*SetInterface) (uint32_t interface);            ///< Pointer to \\ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface.\n  int32_t            (*SetMode)      (uint32_t mode);                 ///< Pointer to \\ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode.\n  ARM_ETH_LINK_STATE (*GetLinkState) (void);                          ///< Pointer to \\ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state.\n  ARM_ETH_LINK_INFO  (*GetLinkInfo)  (void);                          ///< Pointer to \\ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information.\n} const ARM_DRIVER_ETH_PHY;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_ETH_PHY_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_Flash.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        24. January 2020\n * $Revision:    V2.3\n *\n * Project:      Flash Driver definitions\n */\n\n/* History:\n *  Version 2.3\n *    Removed volatile from ARM_FLASH_STATUS\n *  Version 2.2\n *    Padding bytes added to ARM_FLASH_INFO\n *  Version 2.1\n *    ARM_FLASH_STATUS made volatile\n *  Version 2.0\n *    Renamed driver NOR -> Flash (more generic)\n *    Non-blocking operation\n *    Added Events, Status and Capabilities\n *    Linked Flash information (GetInfo)\n *  Version 1.11\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_FLASH_H_\n#define DRIVER_FLASH_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */\n\n\n#define _ARM_Driver_Flash_(n)      Driver_Flash##n\n#define  ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n)\n\n\n#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 }\n\n/**\n\\brief Flash Sector information\n*/\ntypedef struct _ARM_FLASH_SECTOR {\n  uint32_t start;                       ///< Sector Start address\n  uint32_t end;                         ///< Sector End address (start+size-1)\n} const ARM_FLASH_SECTOR;\n\n/**\n\\brief Flash information\n*/\ntypedef struct _ARM_FLASH_INFO {\n  ARM_FLASH_SECTOR *sector_info;        ///< Sector layout information (NULL=Uniform sectors)\n  uint32_t          sector_count;       ///< Number of sectors\n  uint32_t          sector_size;        ///< Uniform sector size in bytes (0=sector_info used) \n  uint32_t          page_size;          ///< Optimal programming page size in bytes\n  uint32_t          program_unit;       ///< Smallest programmable unit in bytes\n  uint8_t           erased_value;       ///< Contents of erased memory (usually 0xFF)\n  uint8_t           reserved[3];        ///< Reserved (must be zero)\n} const ARM_FLASH_INFO;\n\n\n/**\n\\brief Flash Status\n*/\ntypedef struct _ARM_FLASH_STATUS {\n  uint32_t busy     : 1;                ///< Flash busy flag\n  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)\n  uint32_t reserved : 30;\n} ARM_FLASH_STATUS;\n\n\n/****** Flash Event *****/\n#define ARM_FLASH_EVENT_READY           (1UL << 0)  ///< Flash Ready\n#define ARM_FLASH_EVENT_ERROR           (1UL << 1)  ///< Read/Program/Erase Error\n\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn          ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_FLASH_CAPABILITIES\n*/\n/**\n  \\fn          int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)\n  \\brief       Initialize the Flash Interface.\n  \\param[in]   cb_event  Pointer to \\ref ARM_Flash_SignalEvent\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_Flash_Uninitialize (void)\n  \\brief       De-initialize the Flash Interface.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control the Flash interface power.\n  \\param[in]   state  Power state\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)\n  \\brief       Read data from Flash.\n  \\param[in]   addr  Data address.\n  \\param[out]  data  Pointer to a buffer storing the data read from Flash.\n  \\param[in]   cnt   Number of data items to read.\n  \\return      number of data items read or \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)\n  \\brief       Program data to Flash.\n  \\param[in]   addr  Data address.\n  \\param[in]   data  Pointer to a buffer containing the data to be programmed to Flash.\n  \\param[in]   cnt   Number of data items to program.\n  \\return      number of data items programmed or \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_Flash_EraseSector (uint32_t addr)\n  \\brief       Erase Flash Sector.\n  \\param[in]   addr  Sector address\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_Flash_EraseChip (void)\n  \\brief       Erase complete Flash.\n               Optional function for faster full chip erase.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          ARM_FLASH_STATUS ARM_Flash_GetStatus (void)\n  \\brief       Get Flash status.\n  \\return      Flash status \\ref ARM_FLASH_STATUS\n*/\n/**\n  \\fn          ARM_FLASH_INFO * ARM_Flash_GetInfo (void)\n  \\brief       Get Flash information.\n  \\return      Pointer to Flash information \\ref ARM_FLASH_INFO\n*/\n\n/**\n  \\fn          void ARM_Flash_SignalEvent (uint32_t event)\n  \\brief       Signal Flash event.\n  \\param[in]   event  Event notification mask\n  \\return      none\n*/\n\ntypedef void (*ARM_Flash_SignalEvent_t) (uint32_t event);    ///< Pointer to \\ref ARM_Flash_SignalEvent : Signal Flash Event.\n\n\n/**\n\\brief Flash Driver Capabilities.\n*/\ntypedef struct _ARM_FLASH_CAPABILITIES {\n  uint32_t event_ready  : 1;            ///< Signal Flash Ready event\n  uint32_t data_width   : 2;            ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit\n  uint32_t erase_chip   : 1;            ///< Supports EraseChip operation\n  uint32_t reserved     : 28;           ///< Reserved (must be zero)\n} ARM_FLASH_CAPABILITIES;\n\n\n/**\n\\brief Access structure of the Flash Driver\n*/\ntypedef struct _ARM_DRIVER_FLASH {\n  ARM_DRIVER_VERSION     (*GetVersion)     (void);                                          ///< Pointer to \\ref ARM_Flash_GetVersion : Get driver version.\n  ARM_FLASH_CAPABILITIES (*GetCapabilities)(void);                                          ///< Pointer to \\ref ARM_Flash_GetCapabilities : Get driver capabilities.\n  int32_t                (*Initialize)     (ARM_Flash_SignalEvent_t cb_event);              ///< Pointer to \\ref ARM_Flash_Initialize : Initialize Flash Interface.\n  int32_t                (*Uninitialize)   (void);                                          ///< Pointer to \\ref ARM_Flash_Uninitialize : De-initialize Flash Interface.\n  int32_t                (*PowerControl)   (ARM_POWER_STATE state);                         ///< Pointer to \\ref ARM_Flash_PowerControl : Control Flash Interface Power.\n  int32_t                (*ReadData)       (uint32_t addr,       void *data, uint32_t cnt); ///< Pointer to \\ref ARM_Flash_ReadData : Read data from Flash.\n  int32_t                (*ProgramData)    (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \\ref ARM_Flash_ProgramData : Program data to Flash.\n  int32_t                (*EraseSector)    (uint32_t addr);                                 ///< Pointer to \\ref ARM_Flash_EraseSector : Erase Flash Sector.\n  int32_t                (*EraseChip)      (void);                                          ///< Pointer to \\ref ARM_Flash_EraseChip : Erase complete Flash.\n  ARM_FLASH_STATUS       (*GetStatus)      (void);                                          ///< Pointer to \\ref ARM_Flash_GetStatus : Get Flash status.\n  ARM_FLASH_INFO *       (*GetInfo)        (void);                                          ///< Pointer to \\ref ARM_Flash_GetInfo : Get Flash information.\n} const ARM_DRIVER_FLASH;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_FLASH_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_I2C.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        31. March 2020\n * $Revision:    V2.4\n *\n * Project:      I2C (Inter-Integrated Circuit) Driver definitions\n */\n\n/* History:\n *  Version 2.4\n *    Removed volatile from ARM_I2C_STATUS\n *  Version 2.3\n *    ARM_I2C_STATUS made volatile\n *  Version 2.2\n *    Removed function ARM_I2C_MasterTransfer in order to simplify drivers\n *      and added back parameter \"xfer_pending\" to functions\n *      ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive\n *  Version 2.1\n *    Added function ARM_I2C_MasterTransfer and removed parameter \"xfer_pending\"\n *      from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive\n *    Added function ARM_I2C_GetDataCount\n *    Removed flag \"address_nack\" from ARM_I2C_STATUS\n *    Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE\n *      with event ARM_I2C_EVENT_TRANSFER_DONE\n *    Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE\n *    Removed parameter \"arg\" from function ARM_I2C_SignalEvent\n *  Version 2.0\n *    New simplified driver:\n *      complexity moved to upper layer (especially data handling)\n *      more unified API for different communication interfaces\n *    Added:\n *      Slave Mode\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_I2C_H_\n#define DRIVER_I2C_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */\n\n\n#define _ARM_Driver_I2C_(n)      Driver_I2C##n\n#define  ARM_Driver_I2C_(n) _ARM_Driver_I2C_(n)\n\n\n/****** I2C Control Codes *****/\n\n#define ARM_I2C_OWN_ADDRESS             (0x01UL)    ///< Set Own Slave Address; arg = address \n#define ARM_I2C_BUS_SPEED               (0x02UL)    ///< Set Bus Speed; arg = speed\n#define ARM_I2C_BUS_CLEAR               (0x03UL)    ///< Execute Bus clear: send nine clock pulses\n#define ARM_I2C_ABORT_TRANSFER          (0x04UL)    ///< Abort Master/Slave Transmit/Receive\n\n/*----- I2C Bus Speed -----*/\n#define ARM_I2C_BUS_SPEED_STANDARD      (0x01UL)    ///< Standard Speed (100kHz)\n#define ARM_I2C_BUS_SPEED_FAST          (0x02UL)    ///< Fast Speed     (400kHz)\n#define ARM_I2C_BUS_SPEED_FAST_PLUS     (0x03UL)    ///< Fast+ Speed    (  1MHz)\n#define ARM_I2C_BUS_SPEED_HIGH          (0x04UL)    ///< High Speed     (3.4MHz)\n\n\n/****** I2C Address Flags *****/\n\n#define ARM_I2C_ADDRESS_10BIT           (0x0400UL)  ///< 10-bit address flag\n#define ARM_I2C_ADDRESS_GC              (0x8000UL)  ///< General Call flag\n\n\n/**\n\\brief I2C Status\n*/\ntypedef struct _ARM_I2C_STATUS {\n  uint32_t busy             : 1;        ///< Busy flag\n  uint32_t mode             : 1;        ///< Mode: 0=Slave, 1=Master\n  uint32_t direction        : 1;        ///< Direction: 0=Transmitter, 1=Receiver\n  uint32_t general_call     : 1;        ///< General Call indication (cleared on start of next Slave operation)\n  uint32_t arbitration_lost : 1;        ///< Master lost arbitration (cleared on start of next Master operation)\n  uint32_t bus_error        : 1;        ///< Bus error detected (cleared on start of next Master/Slave operation)\n  uint32_t reserved         : 26;\n} ARM_I2C_STATUS;\n\n\n/****** I2C Event *****/\n#define ARM_I2C_EVENT_TRANSFER_DONE       (1UL << 0)  ///< Master/Slave Transmit/Receive finished\n#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1)  ///< Master/Slave Transmit/Receive incomplete transfer\n#define ARM_I2C_EVENT_SLAVE_TRANSMIT      (1UL << 2)  ///< Addressed as Slave Transmitter but transmit operation is not set.\n#define ARM_I2C_EVENT_SLAVE_RECEIVE       (1UL << 3)  ///< Addressed as Slave Receiver but receive operation is not set.\n#define ARM_I2C_EVENT_ADDRESS_NACK        (1UL << 4)  ///< Address not acknowledged from Slave\n#define ARM_I2C_EVENT_GENERAL_CALL        (1UL << 5)  ///< Slave addressed with general call address\n#define ARM_I2C_EVENT_ARBITRATION_LOST    (1UL << 6)  ///< Master lost arbitration\n#define ARM_I2C_EVENT_BUS_ERROR           (1UL << 7)  ///< Bus error detected (START/STOP at illegal position)\n#define ARM_I2C_EVENT_BUS_CLEAR           (1UL << 8)  ///< Bus clear finished\n\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_I2C_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n\n  \\fn          ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_I2C_CAPABILITIES\n\n  \\fn          int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)\n  \\brief       Initialize I2C Interface.\n  \\param[in]   cb_event  Pointer to \\ref ARM_I2C_SignalEvent\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_I2C_Uninitialize (void)\n  \\brief       De-initialize I2C Interface.\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control I2C Interface Power.\n  \\param[in]   state  Power state\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)\n  \\brief       Start transmitting data as I2C Master.\n  \\param[in]   addr          Slave address (7-bit or 10-bit)\n  \\param[in]   data          Pointer to buffer with data to transmit to I2C Slave\n  \\param[in]   num           Number of data bytes to transmit\n  \\param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)\n  \\brief       Start receiving data as I2C Master.\n  \\param[in]   addr          Slave address (7-bit or 10-bit)\n  \\param[out]  data          Pointer to buffer for data to receive from I2C Slave\n  \\param[in]   num           Number of data bytes to receive\n  \\param[in]   xfer_pending  Transfer operation is pending - Stop condition will not be generated\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)\n  \\brief       Start transmitting data as I2C Slave.\n  \\param[in]   data  Pointer to buffer with data to transmit to I2C Master\n  \\param[in]   num   Number of data bytes to transmit\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)\n  \\brief       Start receiving data as I2C Slave.\n  \\param[out]  data  Pointer to buffer for data to receive from I2C Master\n  \\param[in]   num   Number of data bytes to receive\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_I2C_GetDataCount (void)\n  \\brief       Get transferred data count.\n  \\return      number of data bytes transferred; -1 when Slave is not addressed by Master\n\n  \\fn          int32_t ARM_I2C_Control (uint32_t control, uint32_t arg)\n  \\brief       Control I2C Interface.\n  \\param[in]   control  Operation\n  \\param[in]   arg      Argument of operation (optional)\n  \\return      \\ref execution_status\n\n  \\fn          ARM_I2C_STATUS ARM_I2C_GetStatus (void)\n  \\brief       Get I2C status.\n  \\return      I2C status \\ref ARM_I2C_STATUS\n\n  \\fn          void ARM_I2C_SignalEvent (uint32_t event)\n  \\brief       Signal I2C Events.\n  \\param[in]   event  \\ref I2C_events notification mask\n*/\n\ntypedef void (*ARM_I2C_SignalEvent_t) (uint32_t event);  ///< Pointer to \\ref ARM_I2C_SignalEvent : Signal I2C Event.\n\n\n/**\n\\brief I2C Driver Capabilities.\n*/\ntypedef struct _ARM_I2C_CAPABILITIES {\n  uint32_t address_10_bit : 1;          ///< supports 10-bit addressing\n  uint32_t reserved       : 31;         ///< Reserved (must be zero)\n} ARM_I2C_CAPABILITIES;\n\n\n/**\n\\brief Access structure of the I2C Driver.\n*/\ntypedef struct _ARM_DRIVER_I2C {\n  ARM_DRIVER_VERSION   (*GetVersion)     (void);                                                                ///< Pointer to \\ref ARM_I2C_GetVersion : Get driver version.\n  ARM_I2C_CAPABILITIES (*GetCapabilities)(void);                                                                ///< Pointer to \\ref ARM_I2C_GetCapabilities : Get driver capabilities.\n  int32_t              (*Initialize)     (ARM_I2C_SignalEvent_t cb_event);                                      ///< Pointer to \\ref ARM_I2C_Initialize : Initialize I2C Interface.\n  int32_t              (*Uninitialize)   (void);                                                                ///< Pointer to \\ref ARM_I2C_Uninitialize : De-initialize I2C Interface.\n  int32_t              (*PowerControl)   (ARM_POWER_STATE state);                                               ///< Pointer to \\ref ARM_I2C_PowerControl : Control I2C Interface Power.\n  int32_t              (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \\ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master.\n  int32_t              (*MasterReceive)  (uint32_t addr,       uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \\ref ARM_I2C_MasterReceive : Start receiving data as I2C Master.\n  int32_t              (*SlaveTransmit)  (               const uint8_t *data, uint32_t num);                    ///< Pointer to \\ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave.\n  int32_t              (*SlaveReceive)   (                     uint8_t *data, uint32_t num);                    ///< Pointer to \\ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave.\n  int32_t              (*GetDataCount)   (void);                                                                ///< Pointer to \\ref ARM_I2C_GetDataCount : Get transferred data count.\n  int32_t              (*Control)        (uint32_t control, uint32_t arg);                                      ///< Pointer to \\ref ARM_I2C_Control : Control I2C Interface.\n  ARM_I2C_STATUS       (*GetStatus)      (void);                                                                ///< Pointer to \\ref ARM_I2C_GetStatus : Get I2C status.\n} const ARM_DRIVER_I2C;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_I2C_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_MCI.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        31. March 2020\n * $Revision:    V2.4\n *\n * Project:      MCI (Memory Card Interface) Driver definitions\n */\n\n/* History:\n *  Version 2.4\n *    Removed volatile from ARM_MCI_STATUS\n *  Version 2.3\n *    ARM_MCI_STATUS made volatile\n *  Version 2.2\n *    Added timeout and error flags to ARM_MCI_STATUS\n *    Added support for controlling optional RST_n pin (eMMC)\n *    Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK)\n *    Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT\n *  Version 2.1\n *    Decoupled SPI mode from MCI driver\n *    Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP\n *  Version 2.0\n *    Added support for:\n *      SD UHS-I (Ultra High Speed)\n *      SD I/O Interrupt\n *      Read Wait (SD I/O)\n *      Suspend/Resume (SD I/O)\n *      MMC Interrupt\n *      MMC Boot\n *      Stream Data transfer (MMC)\n *      VCCQ Power Supply Control (eMMC)\n *      Command Completion Signal (CCS) for CE-ATA\n *    Added ARM_MCI_Control function\n *    Added ARM_MCI_GetStatus function\n *    Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions\n *      (replaced by ARM_MCI_Control)\n *    Changed ARM_MCI_CardPower function (voltage parameter)\n *    Changed ARM_MCI_SendCommnad function (flags parameter)\n *    Changed ARM_MCI_SetupTransfer function (mode parameter)\n *    Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *    Changed return values of some functions to int32_t\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_MCI_H_\n#define DRIVER_MCI_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */\n\n\n#define _ARM_Driver_MCI_(n)      Driver_MCI##n\n#define  ARM_Driver_MCI_(n) _ARM_Driver_MCI_(n)\n\n\n/****** MCI Send Command Flags *****/\n#define ARM_MCI_RESPONSE_Pos             0\n#define ARM_MCI_RESPONSE_Msk            (3UL << ARM_MCI_RESPONSE_Pos)\n#define ARM_MCI_RESPONSE_NONE           (0UL << ARM_MCI_RESPONSE_Pos)   ///< No response expected (default)\n#define ARM_MCI_RESPONSE_SHORT          (1UL << ARM_MCI_RESPONSE_Pos)   ///< Short response (48-bit)\n#define ARM_MCI_RESPONSE_SHORT_BUSY     (2UL << ARM_MCI_RESPONSE_Pos)   ///< Short response with busy signal (48-bit)\n#define ARM_MCI_RESPONSE_LONG           (3UL << ARM_MCI_RESPONSE_Pos)   ///< Long response (136-bit)\n\n#define ARM_MCI_RESPONSE_INDEX          (1UL << 2)  ///< Check command index in response\n#define ARM_MCI_RESPONSE_CRC            (1UL << 3)  ///< Check CRC in response\n\n#define ARM_MCI_WAIT_BUSY               (1UL << 4)  ///< Wait until busy before sending the command\n\n#define ARM_MCI_TRANSFER_DATA           (1UL << 5)  ///< Activate Data transfer\n\n#define ARM_MCI_CARD_INITIALIZE         (1UL << 6)  ///< Execute Memory Card initialization sequence\n\n#define ARM_MCI_INTERRUPT_COMMAND       (1UL << 7)  ///< Send Interrupt command (CMD40 - MMC only)\n#define ARM_MCI_INTERRUPT_RESPONSE      (1UL << 8)  ///< Send Interrupt response (CMD40 - MMC only)\n\n#define ARM_MCI_BOOT_OPERATION          (1UL << 9)  ///< Execute Boot operation (MMC only)\n#define ARM_MCI_BOOT_ALTERNATIVE        (1UL << 10) ///< Execute Alternative Boot operation (MMC only)\n#define ARM_MCI_BOOT_ACK                (1UL << 11) ///< Expect Boot Acknowledge (MMC only)\n\n#define ARM_MCI_CCSD                    (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device\n#define ARM_MCI_CCS                     (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device\n\n\n/****** MCI Setup Transfer Mode *****/\n#define ARM_MCI_TRANSFER_READ           (0UL << 0)  ///< Data Read Transfer (from MCI)\n#define ARM_MCI_TRANSFER_WRITE          (1UL << 0)  ///< Data Write Transfer (to MCI)\n#define ARM_MCI_TRANSFER_BLOCK          (0UL << 1)  ///< Block Data transfer (default)\n#define ARM_MCI_TRANSFER_STREAM         (1UL << 1)  ///< Stream Data transfer (MMC only)\n\n\n/****** MCI Control Codes *****/\n#define ARM_MCI_BUS_SPEED               (0x01UL)    ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s\n#define ARM_MCI_BUS_SPEED_MODE          (0x02UL)    ///< Set Bus Speed Mode as specified with arg\n#define ARM_MCI_BUS_CMD_MODE            (0x03UL)    ///< Set CMD Line Mode as specified with arg\n#define ARM_MCI_BUS_DATA_WIDTH          (0x04UL)    ///< Set Bus Data Width as specified with arg\n#define ARM_MCI_DRIVER_STRENGTH         (0x05UL)    ///< Set SD UHS-I Driver Strength as specified with arg \n#define ARM_MCI_CONTROL_RESET           (0x06UL)    ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active \n#define ARM_MCI_CONTROL_CLOCK_IDLE      (0x07UL)    ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled\n#define ARM_MCI_UHS_TUNING_OPERATION    (0x08UL)    ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute\n#define ARM_MCI_UHS_TUNING_RESULT       (0x09UL)    ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error\n#define ARM_MCI_DATA_TIMEOUT            (0x0AUL)    ///< Set Data timeout; arg = timeout in bus cycles\n#define ARM_MCI_CSS_TIMEOUT             (0x0BUL)    ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles\n#define ARM_MCI_MONITOR_SDIO_INTERRUPT  (0x0CUL)    ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled\n#define ARM_MCI_CONTROL_READ_WAIT       (0x0DUL)    ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled\n#define ARM_MCI_SUSPEND_TRANSFER        (0x0EUL)    ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer\n#define ARM_MCI_RESUME_TRANSFER         (0x0FUL)    ///< Resume Data transfer (SD I/O)\n\n/*----- MCI Bus Speed Mode -----*/\n#define ARM_MCI_BUS_DEFAULT_SPEED       (0x00UL)    ///< SD/MMC: Default Speed mode up to 25/26MHz\n#define ARM_MCI_BUS_HIGH_SPEED          (0x01UL)    ///< SD/MMC: High    Speed mode up to 50/52MHz\n#define ARM_MCI_BUS_UHS_SDR12           (0x02UL)    ///< SD: SDR12  (Single Data Rate) up to  25MHz,  12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling\n#define ARM_MCI_BUS_UHS_SDR25           (0x03UL)    ///< SD: SDR25  (Single Data Rate) up to  50MHz,  25  MB/s: UHS-I (Ultra High Speed) 1.8V signaling\n#define ARM_MCI_BUS_UHS_SDR50           (0x04UL)    ///< SD: SDR50  (Single Data Rate) up to 100MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling\n#define ARM_MCI_BUS_UHS_SDR104          (0x05UL)    ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104  MB/s: UHS-I (Ultra High Speed) 1.8V signaling\n#define ARM_MCI_BUS_UHS_DDR50           (0x06UL)    ///< SD: DDR50  (Dual Data Rate)   up to  50MHz,  50  MB/s: UHS-I (Ultra High Speed) 1.8V signaling\n\n/*----- MCI CMD Line Mode -----*/\n#define ARM_MCI_BUS_CMD_PUSH_PULL       (0x00UL)    ///< Push-Pull CMD line (default)\n#define ARM_MCI_BUS_CMD_OPEN_DRAIN      (0x01UL)    ///< Open Drain CMD line (MMC only)\n\n/*----- MCI Bus Data Width -----*/\n#define ARM_MCI_BUS_DATA_WIDTH_1        (0x00UL)    ///< Bus data width: 1 bit (default)\n#define ARM_MCI_BUS_DATA_WIDTH_4        (0x01UL)    ///< Bus data width: 4 bits\n#define ARM_MCI_BUS_DATA_WIDTH_8        (0x02UL)    ///< Bus data width: 8 bits\n#define ARM_MCI_BUS_DATA_WIDTH_4_DDR    (0x03UL)    ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only\n#define ARM_MCI_BUS_DATA_WIDTH_8_DDR    (0x04UL)    ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only\n\n/*----- MCI Driver Strength -----*/\n#define ARM_MCI_DRIVER_TYPE_A           (0x01UL)    ///< SD UHS-I Driver Type A\n#define ARM_MCI_DRIVER_TYPE_B           (0x00UL)    ///< SD UHS-I Driver Type B (default)\n#define ARM_MCI_DRIVER_TYPE_C           (0x02UL)    ///< SD UHS-I Driver Type C\n#define ARM_MCI_DRIVER_TYPE_D           (0x03UL)    ///< SD UHS-I Driver Type D\n\n\n/****** MCI Card Power *****/\n#define ARM_MCI_POWER_VDD_Pos            0\n#define ARM_MCI_POWER_VDD_Msk           (0x0FUL << ARM_MCI_POWER_VDD_Pos)\n#define ARM_MCI_POWER_VDD_OFF           (0x01UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) turned off\n#define ARM_MCI_POWER_VDD_3V3           (0x02UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 3.3V\n#define ARM_MCI_POWER_VDD_1V8           (0x03UL << ARM_MCI_POWER_VDD_Pos)   ///< VDD (VCC) = 1.8V\n#define ARM_MCI_POWER_VCCQ_Pos           4\n#define ARM_MCI_POWER_VCCQ_Msk          (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)\n#define ARM_MCI_POWER_VCCQ_OFF          (0x01UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ turned off\n#define ARM_MCI_POWER_VCCQ_3V3          (0x02UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 3.3V\n#define ARM_MCI_POWER_VCCQ_1V8          (0x03UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.8V\n#define ARM_MCI_POWER_VCCQ_1V2          (0x04UL << ARM_MCI_POWER_VCCQ_Pos)  ///< eMMC VCCQ = 1.2V\n\n\n/**\n\\brief MCI Status\n*/\ntypedef struct _ARM_MCI_STATUS {\n  uint32_t command_active   : 1;        ///< Command active flag\n  uint32_t command_timeout  : 1;        ///< Command timeout flag (cleared on start of next command)\n  uint32_t command_error    : 1;        ///< Command error flag (cleared on start of next command)\n  uint32_t transfer_active  : 1;        ///< Transfer active flag\n  uint32_t transfer_timeout : 1;        ///< Transfer timeout flag (cleared on start of next command)\n  uint32_t transfer_error   : 1;        ///< Transfer error flag (cleared on start of next command)\n  uint32_t sdio_interrupt   : 1;        ///< SD I/O Interrupt flag (cleared on start of monitoring)\n  uint32_t ccs              : 1;        ///< CCS flag (cleared on start of next command)\n  uint32_t reserved         : 24;\n} ARM_MCI_STATUS;\n\n\n/****** MCI Card Event *****/\n#define ARM_MCI_EVENT_CARD_INSERTED     (1UL << 0)  ///< Memory Card inserted\n#define ARM_MCI_EVENT_CARD_REMOVED      (1UL << 1)  ///< Memory Card removed\n#define ARM_MCI_EVENT_COMMAND_COMPLETE  (1UL << 2)  ///< Command completed\n#define ARM_MCI_EVENT_COMMAND_TIMEOUT   (1UL << 3)  ///< Command timeout\n#define ARM_MCI_EVENT_COMMAND_ERROR     (1UL << 4)  ///< Command response error (CRC error or invalid response)\n#define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5)  ///< Data transfer completed\n#define ARM_MCI_EVENT_TRANSFER_TIMEOUT  (1UL << 6)  ///< Data transfer timeout\n#define ARM_MCI_EVENT_TRANSFER_ERROR    (1UL << 7)  ///< Data transfer CRC failed\n#define ARM_MCI_EVENT_SDIO_INTERRUPT    (1UL << 8)  ///< SD I/O Interrupt\n#define ARM_MCI_EVENT_CCS               (1UL << 9)  ///< Command Completion Signal (CCS)\n#define ARM_MCI_EVENT_CCS_TIMEOUT       (1UL << 10) ///< Command Completion Signal (CCS) Timeout\n\n\n// Function documentation\n/**\n  \\fn            ARM_DRIVER_VERSION ARM_MCI_GetVersion (void)\n  \\brief         Get driver version.\n  \\return        \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn            ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)\n  \\brief         Get driver capabilities.\n  \\return        \\ref ARM_MCI_CAPABILITIES\n*/\n/**\n  \\fn            int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)\n  \\brief         Initialize the Memory Card Interface\n  \\param[in]     cb_event  Pointer to \\ref ARM_MCI_SignalEvent\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_MCI_Uninitialize (void)\n  \\brief         De-initialize Memory Card Interface.\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)\n  \\brief         Control Memory Card Interface Power.\n  \\param[in]     state   Power state \\ref ARM_POWER_STATE\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_MCI_CardPower (uint32_t voltage)\n  \\brief         Set Memory Card Power supply voltage.\n  \\param[in]     voltage  Memory Card Power supply voltage\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_MCI_ReadCD (void)\n  \\brief         Read Card Detect (CD) state.\n  \\return        1:card detected, 0:card not detected, or error\n*/\n/**\n  \\fn            int32_t ARM_MCI_ReadWP (void)\n  \\brief         Read Write Protect (WP) state.\n  \\return        1:write protected, 0:not write protected, or error\n*/\n/**\n  \\fn            int32_t ARM_MCI_SendCommand (uint32_t  cmd,\n                                              uint32_t  arg,\n                                              uint32_t  flags,\n                                              uint32_t *response)\n  \\brief         Send Command to card and get the response.\n  \\param[in]     cmd       Memory Card command\n  \\param[in]     arg       Command argument\n  \\param[in]     flags     Command flags\n  \\param[out]    response  Pointer to buffer for response\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_MCI_SetupTransfer (uint8_t *data,\n                                                uint32_t block_count,\n                                                uint32_t block_size,\n                                                uint32_t mode)\n  \\brief         Setup read or write transfer operation.\n  \\param[in,out] data         Pointer to data block(s) to be written or read\n  \\param[in]     block_count  Number of blocks\n  \\param[in]     block_size   Size of a block in bytes\n  \\param[in]     mode         Transfer mode\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_MCI_AbortTransfer (void)\n  \\brief         Abort current read/write data transfer.\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_MCI_Control (uint32_t control, uint32_t arg)\n  \\brief         Control MCI Interface.\n  \\param[in]     control  Operation\n  \\param[in]     arg      Argument of operation (optional)\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            ARM_MCI_STATUS ARM_MCI_GetStatus (void)\n  \\brief         Get MCI status.\n  \\return        MCI status \\ref ARM_MCI_STATUS\n*/\n\n/**\n  \\fn            void ARM_MCI_SignalEvent (uint32_t event)\n  \\brief         Callback function that signals a MCI Card Event.\n  \\param[in]     event \\ref mci_event_gr\n  \\return        none\n*/\n\ntypedef void (*ARM_MCI_SignalEvent_t) (uint32_t event);  ///< Pointer to \\ref ARM_MCI_SignalEvent : Signal MCI Card Event.\n\n\n/**\n\\brief  MCI Driver Capabilities.\n*/\ntypedef struct _ARM_MCI_CAPABILITIES {\n  uint32_t cd_state          : 1;       ///< Card Detect State available\n  uint32_t cd_event          : 1;       ///< Signal Card Detect change event\n  uint32_t wp_state          : 1;       ///< Write Protect State available\n  uint32_t vdd               : 1;       ///< Supports VDD Card Power Supply Control\n  uint32_t vdd_1v8           : 1;       ///< Supports 1.8 VDD Card Power Supply\n  uint32_t vccq              : 1;       ///< Supports VCCQ Card Power Supply Control (eMMC)\n  uint32_t vccq_1v8          : 1;       ///< Supports 1.8 VCCQ Card Power Supply (eMMC)\n  uint32_t vccq_1v2          : 1;       ///< Supports 1.2 VCCQ Card Power Supply (eMMC)\n  uint32_t data_width_4      : 1;       ///< Supports 4-bit data\n  uint32_t data_width_8      : 1;       ///< Supports 8-bit data\n  uint32_t data_width_4_ddr  : 1;       ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only\n  uint32_t data_width_8_ddr  : 1;       ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only\n  uint32_t high_speed        : 1;       ///< Supports SD/MMC High Speed Mode\n  uint32_t uhs_signaling     : 1;       ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling \n  uint32_t uhs_tuning        : 1;       ///< Supports SD UHS-I tuning \n  uint32_t uhs_sdr50         : 1;       ///< Supports SD UHS-I SDR50  (Single Data Rate) up to  50MB/s\n  uint32_t uhs_sdr104        : 1;       ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s\n  uint32_t uhs_ddr50         : 1;       ///< Supports SD UHS-I DDR50  (Dual   Data Rate) up to  50MB/s\n  uint32_t uhs_driver_type_a : 1;       ///< Supports SD UHS-I Driver Type A\n  uint32_t uhs_driver_type_c : 1;       ///< Supports SD UHS-I Driver Type C\n  uint32_t uhs_driver_type_d : 1;       ///< Supports SD UHS-I Driver Type D \n  uint32_t sdio_interrupt    : 1;       ///< Supports SD I/O Interrupt \n  uint32_t read_wait         : 1;       ///< Supports Read Wait (SD I/O)\n  uint32_t suspend_resume    : 1;       ///< Supports Suspend/Resume (SD I/O)\n  uint32_t mmc_interrupt     : 1;       ///< Supports MMC Interrupt \n  uint32_t mmc_boot          : 1;       ///< Supports MMC Boot \n  uint32_t rst_n             : 1;       ///< Supports RST_n Pin Control (eMMC)\n  uint32_t ccs               : 1;       ///< Supports Command Completion Signal (CCS) for CE-ATA\n  uint32_t ccs_timeout       : 1;       ///< Supports Command Completion Signal (CCS) timeout for CE-ATA\n  uint32_t reserved          : 3;       ///< Reserved (must be zero)\n} ARM_MCI_CAPABILITIES;\n\n\n/**\n\\brief  Access structure of the MCI Driver.\n*/\ntypedef struct _ARM_DRIVER_MCI {\n  ARM_DRIVER_VERSION   (*GetVersion)     (void);                           ///< Pointer to \\ref ARM_MCI_GetVersion : Get driver version.\n  ARM_MCI_CAPABILITIES (*GetCapabilities)(void);                           ///< Pointer to \\ref ARM_MCI_GetCapabilities : Get driver capabilities.\n  int32_t              (*Initialize)     (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \\ref ARM_MCI_Initialize : Initialize MCI Interface.\n  int32_t              (*Uninitialize)   (void);                           ///< Pointer to \\ref ARM_MCI_Uninitialize : De-initialize MCI Interface.\n  int32_t              (*PowerControl)   (ARM_POWER_STATE state);          ///< Pointer to \\ref ARM_MCI_PowerControl : Control MCI Interface Power.\n  int32_t              (*CardPower)      (uint32_t voltage);               ///< Pointer to \\ref ARM_MCI_CardPower : Set card power supply voltage.\n  int32_t              (*ReadCD)         (void);                           ///< Pointer to \\ref ARM_MCI_ReadCD : Read Card Detect (CD) state.\n  int32_t              (*ReadWP)         (void);                           ///< Pointer to \\ref ARM_MCI_ReadWP : Read Write Protect (WP) state.\n  int32_t              (*SendCommand)    (uint32_t cmd, \n                                          uint32_t arg, \n                                          uint32_t flags,\n                                          uint32_t *response);             ///< Pointer to \\ref ARM_MCI_SendCommand : Send Command to card and get the response.\n  int32_t              (*SetupTransfer)  (uint8_t *data,\n                                          uint32_t block_count,\n                                          uint32_t block_size,\n                                          uint32_t mode);                  ///< Pointer to \\ref ARM_MCI_SetupTransfer : Setup data transfer operation.\n  int32_t              (*AbortTransfer)  (void);                           ///< Pointer to \\ref ARM_MCI_AbortTransfer : Abort current data transfer.\n  int32_t              (*Control)        (uint32_t control, uint32_t arg); ///< Pointer to \\ref ARM_MCI_Control : Control MCI Interface.\n  ARM_MCI_STATUS       (*GetStatus)      (void);                           ///< Pointer to \\ref ARM_MCI_GetStatus : Get MCI status.\n} const ARM_DRIVER_MCI;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_MCI_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_NAND.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        31. March 2020\n * $Revision:    V2.4\n *\n * Project:      NAND Flash Driver definitions\n */\n\n/* History:\n *  Version 2.4\n *    Removed volatile from ARM_NAND_STATUS\n *  Version 2.3\n *    Extended ARM_NAND_ECC_INFO structure\n *  Version 2.2\n *    ARM_NAND_STATUS made volatile\n *  Version 2.1\n *    Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions\n *  Version 2.0\n *    New simplified driver:\n *      complexity moved to upper layer (command agnostic)\n *    Added support for:\n *      NV-DDR & NV-DDR2 Interface (ONFI specification)\n *      VCC, VCCQ and VPP Power Supply Control\n *      WP (Write Protect) Control\n *  Version 1.11\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_NAND_H_\n#define DRIVER_NAND_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */\n\n\n#define _ARM_Driver_NAND_(n)      Driver_NAND##n\n#define  ARM_Driver_NAND_(n) _ARM_Driver_NAND_(n)\n\n\n/****** NAND Device Power *****/\n#define ARM_NAND_POWER_VCC_Pos           0\n#define ARM_NAND_POWER_VCC_Msk          (0x07UL << ARM_NAND_POWER_VCC_Pos)\n#define ARM_NAND_POWER_VCC_OFF          (0x01UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC Power off\n#define ARM_NAND_POWER_VCC_3V3          (0x02UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 3.3V\n#define ARM_NAND_POWER_VCC_1V8          (0x03UL << ARM_NAND_POWER_VCC_Pos)  ///< VCC = 1.8V\n#define ARM_NAND_POWER_VCCQ_Pos          3\n#define ARM_NAND_POWER_VCCQ_Msk         (0x07UL << ARM_NAND_POWER_VCCQ_Pos)\n#define ARM_NAND_POWER_VCCQ_OFF         (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off\n#define ARM_NAND_POWER_VCCQ_3V3         (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V\n#define ARM_NAND_POWER_VCCQ_1V8         (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V\n#define ARM_NAND_POWER_VPP_OFF          (1UL << 6)                          ///< VPP off\n#define ARM_NAND_POWER_VPP_ON           (1UL << 7)                          ///< VPP on\n\n\n/****** NAND Control Codes *****/\n#define ARM_NAND_BUS_MODE               (0x01UL)    ///< Set Bus Mode as specified with arg\n#define ARM_NAND_BUS_DATA_WIDTH         (0x02UL)    ///< Set Bus Data Width as specified with arg\n#define ARM_NAND_DRIVER_STRENGTH        (0x03UL)    ///< Set Driver Strength as specified with arg\n#define ARM_NAND_DEVICE_READY_EVENT     (0x04UL)    ///< Generate \\ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled \n#define ARM_NAND_DRIVER_READY_EVENT     (0x05UL)    ///< Generate \\ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled \n\n/*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/\n#define ARM_NAND_BUS_INTERFACE_Pos       4\n#define ARM_NAND_BUS_INTERFACE_Msk      (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)\n#define ARM_NAND_BUS_SDR                (0x00UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface:    SDR  (Single Data Rate) - Traditional interface (default)\n#define ARM_NAND_BUS_DDR                (0x01UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR  (Double Data Rate)\n#define ARM_NAND_BUS_DDR2               (0x02UL << ARM_NAND_BUS_INTERFACE_Pos)    ///< Data Interface: NV-DDR2 (Double Data Rate)\n#define ARM_NAND_BUS_TIMING_MODE_Pos     0\n#define ARM_NAND_BUS_TIMING_MODE_Msk    (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)\n#define ARM_NAND_BUS_TIMING_MODE_0      (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 0 (default)\n#define ARM_NAND_BUS_TIMING_MODE_1      (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 1\n#define ARM_NAND_BUS_TIMING_MODE_2      (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 2\n#define ARM_NAND_BUS_TIMING_MODE_3      (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 3\n#define ARM_NAND_BUS_TIMING_MODE_4      (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 4 (SDR EDO capable)\n#define ARM_NAND_BUS_TIMING_MODE_5      (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 5 (SDR EDO capable)\n#define ARM_NAND_BUS_TIMING_MODE_6      (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 6 (NV-DDR2 only)\n#define ARM_NAND_BUS_TIMING_MODE_7      (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos)  ///< Timing Mode 7 (NV-DDR2 only)\n#define ARM_NAND_BUS_DDR2_DO_WCYC_Pos    8\n#define ARM_NAND_BUS_DDR2_DO_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)\n#define ARM_NAND_BUS_DDR2_DO_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default)\n#define ARM_NAND_BUS_DDR2_DO_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1\n#define ARM_NAND_BUS_DDR2_DO_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2\n#define ARM_NAND_BUS_DDR2_DO_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4\n#define ARM_NAND_BUS_DDR2_DI_WCYC_Pos    12\n#define ARM_NAND_BUS_DDR2_DI_WCYC_Msk   (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)\n#define ARM_NAND_BUS_DDR2_DI_WCYC_0     (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default)\n#define ARM_NAND_BUS_DDR2_DI_WCYC_1     (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1\n#define ARM_NAND_BUS_DDR2_DI_WCYC_2     (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2\n#define ARM_NAND_BUS_DDR2_DI_WCYC_4     (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4\n#define ARM_NAND_BUS_DDR2_VEN           (1UL << 16)                               ///< DDR2 Enable external VREFQ as reference\n#define ARM_NAND_BUS_DDR2_CMPD          (1UL << 17)                               ///< DDR2 Enable complementary DQS (DQS_c) signal\n#define ARM_NAND_BUS_DDR2_CMPR          (1UL << 18)                               ///< DDR2 Enable complementary RE_n (RE_c) signal\n\n/*----- NAND Data Bus Width -----*/\n#define ARM_NAND_BUS_DATA_WIDTH_8       (0x00UL)   ///< Bus Data Width:  8 bit (default)\n#define ARM_NAND_BUS_DATA_WIDTH_16      (0x01UL)   ///< Bus Data Width: 16 bit\n\n/*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/\n#define ARM_NAND_DRIVER_STRENGTH_18     (0x00UL)   ///< Driver Strength 2.0x = 18 Ohms\n#define ARM_NAND_DRIVER_STRENGTH_25     (0x01UL)   ///< Driver Strength 1.4x = 25 Ohms\n#define ARM_NAND_DRIVER_STRENGTH_35     (0x02UL)   ///< Driver Strength 1.0x = 35 Ohms (default)\n#define ARM_NAND_DRIVER_STRENGTH_50     (0x03UL)   ///< Driver Strength 0.7x = 50 Ohms\n\n\n/****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/\n#define ARM_NAND_ECC_INDEX_Pos           0\n#define ARM_NAND_ECC_INDEX_Msk          (0xFFUL << ARM_NAND_ECC_INDEX_Pos)\n#define ARM_NAND_ECC(n)                 ((n) & ARM_NAND_ECC_INDEX_Msk)     ///< Select ECC\n#define ARM_NAND_ECC0                   (1UL << 8)                         ///< Use ECC0 of selected ECC\n#define ARM_NAND_ECC1                   (1UL << 9)                         ///< Use ECC1 of selected ECC\n\n/****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/\n#define ARM_NAND_DRIVER_DONE_EVENT      (1UL << 16) ///< Generate \\ref ARM_NAND_EVENT_DRIVER_DONE\n\n/****** NAND Sequence Execution Code *****/\n#define ARM_NAND_CODE_SEND_CMD1         (1UL << 17) ///< Send Command 1\n#define ARM_NAND_CODE_SEND_ADDR_COL1    (1UL << 18) ///< Send Column Address 1\n#define ARM_NAND_CODE_SEND_ADDR_COL2    (1UL << 19) ///< Send Column Address 2\n#define ARM_NAND_CODE_SEND_ADDR_ROW1    (1UL << 20) ///< Send Row Address 1\n#define ARM_NAND_CODE_SEND_ADDR_ROW2    (1UL << 21) ///< Send Row Address 2\n#define ARM_NAND_CODE_SEND_ADDR_ROW3    (1UL << 22) ///< Send Row Address 3\n#define ARM_NAND_CODE_INC_ADDR_ROW      (1UL << 23) ///< Auto-increment Row Address\n#define ARM_NAND_CODE_WRITE_DATA        (1UL << 24) ///< Write Data\n#define ARM_NAND_CODE_SEND_CMD2         (1UL << 25) ///< Send Command 2\n#define ARM_NAND_CODE_WAIT_BUSY         (1UL << 26) ///< Wait while R/Bn busy\n#define ARM_NAND_CODE_READ_DATA         (1UL << 27) ///< Read Data\n#define ARM_NAND_CODE_SEND_CMD3         (1UL << 28) ///< Send Command 3\n#define ARM_NAND_CODE_READ_STATUS       (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0)\n\n/*----- NAND Sequence Execution Code: Command -----*/\n#define ARM_NAND_CODE_CMD1_Pos           0\n#define ARM_NAND_CODE_CMD1_Msk          (0xFFUL << ARM_NAND_CODE_CMD1_Pos)\n#define ARM_NAND_CODE_CMD2_Pos           8\n#define ARM_NAND_CODE_CMD2_Msk          (0xFFUL << ARM_NAND_CODE_CMD2_Pos)\n#define ARM_NAND_CODE_CMD3_Pos           16\n#define ARM_NAND_CODE_CMD3_Msk          (0xFFUL << ARM_NAND_CODE_CMD3_Pos)\n\n/*----- NAND Sequence Execution Code: Column Address -----*/\n#define ARM_NAND_CODE_ADDR_COL1_Pos      0\n#define ARM_NAND_CODE_ADDR_COL1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)\n#define ARM_NAND_CODE_ADDR_COL2_Pos      8\n#define ARM_NAND_CODE_ADDR_COL2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)\n\n/*----- NAND Sequence Execution Code: Row Address -----*/\n#define ARM_NAND_CODE_ADDR_ROW1_Pos      0\n#define ARM_NAND_CODE_ADDR_ROW1_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)\n#define ARM_NAND_CODE_ADDR_ROW2_Pos      8\n#define ARM_NAND_CODE_ADDR_ROW2_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)\n#define ARM_NAND_CODE_ADDR_ROW3_Pos      16\n#define ARM_NAND_CODE_ADDR_ROW3_Msk     (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)\n\n\n/****** NAND specific error codes *****/\n#define ARM_NAND_ERROR_ECC              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< ECC generation/correction failed\n\n\n/**\n\\brief NAND ECC (Error Correction Code) Information\n*/\ntypedef struct _ARM_NAND_ECC_INFO {\n  uint32_t type             :  2;       ///< Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare\n  uint32_t page_layout      :  1;       ///< Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1|\n  uint32_t page_count       :  3;       ///< Number of virtual pages: N = 2 ^ page_count\n  uint32_t page_size        :  4;       ///< Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description)\n  uint32_t reserved         : 14;       ///< Reserved (must be zero)\n  uint32_t correctable_bits :  8;       ///< Number of correctable bits (based on 512 byte codeword size)\n  uint16_t codeword_size     [2];       ///< Number of bytes over which ECC is calculated\n  uint16_t ecc_size          [2];       ///< ECC size in bytes (rounded up)\n  uint16_t ecc_offset        [2];       ///< ECC offset in bytes (where ECC starts in Spare)\n  /* Extended description */\n  uint16_t virtual_page_size [2];       ///< Virtual Page size in bytes (Main/Spare)\n  uint16_t codeword_offset   [2];       ///< Codeword offset in bytes (where ECC protected data starts in Main/Spare)\n  uint16_t codeword_gap      [2];       ///< Codeword gap in bytes till next protected data\n  uint16_t ecc_gap           [2];       ///< ECC gap in bytes till next generated ECC\n} ARM_NAND_ECC_INFO;\n\n\n/**\n\\brief NAND Status\n*/\ntypedef struct _ARM_NAND_STATUS {\n  uint32_t busy      : 1;               ///< Driver busy flag\n  uint32_t ecc_error : 1;               ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence)\n  uint32_t reserved  : 30;\n} ARM_NAND_STATUS;\n\n\n/****** NAND Event *****/\n#define ARM_NAND_EVENT_DEVICE_READY     (1UL << 0)  ///< Device Ready: R/Bn rising edge\n#define ARM_NAND_EVENT_DRIVER_READY     (1UL << 1)  ///< Driver Ready\n#define ARM_NAND_EVENT_DRIVER_DONE      (1UL << 2)  ///< Driver operation done\n#define ARM_NAND_EVENT_ECC_ERROR        (1UL << 3)  ///< ECC could not correct data\n\n\n// Function documentation\n/**\n  \\fn            ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)\n  \\brief         Get driver version.\n  \\return        \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn            ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)\n  \\brief         Get driver capabilities.\n  \\return        \\ref ARM_NAND_CAPABILITIES\n*/\n/**\n  \\fn            int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event)\n  \\brief         Initialize the NAND Interface.\n  \\param[in]     cb_event  Pointer to \\ref ARM_NAND_SignalEvent\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_Uninitialize (void)\n  \\brief         De-initialize the NAND Interface.\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)\n  \\brief         Control the NAND interface power.\n  \\param[in]     state  Power state\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_DevicePower (uint32_t voltage)\n  \\brief         Set device power supply voltage.\n  \\param[in]     voltage  NAND Device supply voltage\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)\n  \\brief         Control WPn (Write Protect).\n  \\param[in]     dev_num  Device number\n  \\param[in]     enable\n                - \\b false Write Protect off\n                - \\b true  Write Protect on\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)\n  \\brief         Control CEn (Chip Enable).\n  \\param[in]     dev_num  Device number\n  \\param[in]     enable\n                - \\b false Chip Enable off\n                - \\b true  Chip Enable on\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)\n  \\brief         Get Device Busy pin state.\n  \\param[in]     dev_num  Device number\n  \\return        1=busy, 0=not busy, or error\n*/\n/**\n  \\fn            int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)\n  \\brief         Send command to NAND device.\n  \\param[in]     dev_num  Device number\n  \\param[in]     cmd      Command\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)\n  \\brief         Send address to NAND device.\n  \\param[in]     dev_num  Device number\n  \\param[in]     addr     Address\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)\n  \\brief         Read data from NAND device.\n  \\param[in]     dev_num  Device number\n  \\param[out]    data     Pointer to buffer for data to read from NAND device\n  \\param[in]     cnt      Number of data items to read\n  \\param[in]     mode     Operation mode\n  \\return        number of data items read or \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)\n  \\brief         Write data to NAND device.\n  \\param[in]     dev_num  Device number\n  \\param[out]    data     Pointer to buffer with data to write to NAND device\n  \\param[in]     cnt      Number of data items to write\n  \\param[in]     mode     Operation mode\n  \\return        number of data items written or \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,\n                                                   uint32_t addr_col, uint32_t addr_row,\n                                                   void *data, uint32_t data_cnt,\n                                                   uint8_t *status, uint32_t *count)\n  \\brief         Execute sequence of operations.\n  \\param[in]     dev_num  Device number\n  \\param[in]     code     Sequence code\n  \\param[in]     cmd      Command(s)\n  \\param[in]     addr_col Column address\n  \\param[in]     addr_row Row address\n  \\param[in,out] data     Pointer to data to be written or read \n  \\param[in]     data_cnt Number of data items in one iteration\n  \\param[out]    status   Pointer to status read\n  \\param[in,out] count    Number of iterations\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_AbortSequence (uint32_t dev_num)\n  \\brief         Abort sequence execution.\n  \\param[in]     dev_num  Device number\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)\n  \\brief         Control NAND Interface.\n  \\param[in]     dev_num  Device number\n  \\param[in]     control  Operation\n  \\param[in]     arg      Argument of operation\n  \\return        \\ref execution_status\n*/\n/**\n  \\fn            ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)\n  \\brief         Get NAND status.\n  \\param[in]     dev_num  Device number\n  \\return        NAND status \\ref ARM_NAND_STATUS\n*/\n/**\n  \\fn            int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)\n  \\brief         Inquire about available ECC.\n  \\param[in]     index   Inquire ECC index\n  \\param[out]    info    Pointer to ECC information \\ref ARM_NAND_ECC_INFO retrieved\n  \\return        \\ref execution_status\n*/\n\n/**\n  \\fn            void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)\n  \\brief         Signal NAND event.\n  \\param[in]     dev_num  Device number\n  \\param[in]     event    Event notification mask\n  \\return        none\n*/\n\ntypedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event);    ///< Pointer to \\ref ARM_NAND_SignalEvent : Signal NAND Event.\n\n\n/**\n\\brief NAND Driver Capabilities.\n*/\ntypedef struct _ARM_NAND_CAPABILITIES {\n  uint32_t event_device_ready  : 1;     ///< Signal Device Ready event (R/Bn rising edge)\n  uint32_t reentrant_operation : 1;     ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData)\n  uint32_t sequence_operation  : 1;     ///< Supports Sequence operation (ExecuteSequence, AbortSequence)\n  uint32_t vcc                 : 1;     ///< Supports VCC Power Supply Control\n  uint32_t vcc_1v8             : 1;     ///< Supports 1.8 VCC Power Supply\n  uint32_t vccq                : 1;     ///< Supports VCCQ I/O Power Supply Control\n  uint32_t vccq_1v8            : 1;     ///< Supports 1.8 VCCQ I/O Power Supply\n  uint32_t vpp                 : 1;     ///< Supports VPP High Voltage Power Supply Control\n  uint32_t wp                  : 1;     ///< Supports WPn (Write Protect) Control\n  uint32_t ce_lines            : 4;     ///< Number of CEn (Chip Enable) lines: ce_lines + 1\n  uint32_t ce_manual           : 1;     ///< Supports manual CEn (Chip Enable) Control\n  uint32_t rb_monitor          : 1;     ///< Supports R/Bn (Ready/Busy) Monitoring\n  uint32_t data_width_16       : 1;     ///< Supports 16-bit data\n  uint32_t ddr                 : 1;     ///< Supports NV-DDR  Data Interface (ONFI)\n  uint32_t ddr2                : 1;     ///< Supports NV-DDR2 Data Interface (ONFI)\n  uint32_t sdr_timing_mode     : 3;     ///< Fastest (highest) SDR     Timing Mode supported (ONFI)\n  uint32_t ddr_timing_mode     : 3;     ///< Fastest (highest) NV_DDR  Timing Mode supported (ONFI)\n  uint32_t ddr2_timing_mode    : 3;     ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)\n  uint32_t driver_strength_18  : 1;     ///< Supports Driver Strength 2.0x = 18 Ohms\n  uint32_t driver_strength_25  : 1;     ///< Supports Driver Strength 1.4x = 25 Ohms\n  uint32_t driver_strength_50  : 1;     ///< Supports Driver Strength 0.7x = 50 Ohms\n  uint32_t reserved            : 2;     ///< Reserved (must be zero)\n} ARM_NAND_CAPABILITIES;\n\n\n/**\n\\brief Access structure of the NAND Driver.\n*/\ntypedef struct _ARM_DRIVER_NAND {\n  ARM_DRIVER_VERSION    (*GetVersion)     (void);                                                             ///< Pointer to \\ref ARM_NAND_GetVersion : Get driver version.\n  ARM_NAND_CAPABILITIES (*GetCapabilities)(void);                                                             ///< Pointer to \\ref ARM_NAND_GetCapabilities : Get driver capabilities.\n  int32_t               (*Initialize)     (ARM_NAND_SignalEvent_t cb_event);                                  ///< Pointer to \\ref ARM_NAND_Initialize : Initialize NAND Interface.\n  int32_t               (*Uninitialize)   (void);                                                             ///< Pointer to \\ref ARM_NAND_Uninitialize : De-initialize NAND Interface.\n  int32_t               (*PowerControl)   (ARM_POWER_STATE state);                                            ///< Pointer to \\ref ARM_NAND_PowerControl : Control NAND Interface Power.\n  int32_t               (*DevicePower)    (uint32_t voltage);                                                 ///< Pointer to \\ref ARM_NAND_DevicePower : Set device power supply voltage.\n  int32_t               (*WriteProtect)   (uint32_t dev_num, bool enable);                                    ///< Pointer to \\ref ARM_NAND_WriteProtect : Control WPn (Write Protect).\n  int32_t               (*ChipEnable)     (uint32_t dev_num, bool enable);                                    ///< Pointer to \\ref ARM_NAND_ChipEnable : Control CEn (Chip Enable).\n  int32_t               (*GetDeviceBusy)  (uint32_t dev_num);                                                 ///< Pointer to \\ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state.\n  int32_t               (*SendCommand)    (uint32_t dev_num, uint8_t cmd);                                    ///< Pointer to \\ref ARM_NAND_SendCommand : Send command to NAND device.\n  int32_t               (*SendAddress)    (uint32_t dev_num, uint8_t addr);                                   ///< Pointer to \\ref ARM_NAND_SendAddress : Send address to NAND device.\n  int32_t               (*ReadData)       (uint32_t dev_num,       void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \\ref ARM_NAND_ReadData : Read data from NAND device.\n  int32_t               (*WriteData)      (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode);  ///< Pointer to \\ref ARM_NAND_WriteData : Write data to NAND device.\n  int32_t               (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd,\n                                           uint32_t addr_col, uint32_t addr_row,\n                                           void *data, uint32_t data_cnt,\n                                           uint8_t *status, uint32_t *count);                                 ///< Pointer to \\ref ARM_NAND_ExecuteSequence : Execute sequence of operations.\n  int32_t               (*AbortSequence)  (uint32_t dev_num);                                                 ///< Pointer to \\ref ARM_NAND_AbortSequence : Abort sequence execution. \n  int32_t               (*Control)        (uint32_t dev_num, uint32_t control, uint32_t arg);                 ///< Pointer to \\ref ARM_NAND_Control : Control NAND Interface.\n  ARM_NAND_STATUS       (*GetStatus)      (uint32_t dev_num);                                                 ///< Pointer to \\ref ARM_NAND_GetStatus : Get NAND status.\n  int32_t               (*InquireECC)     ( int32_t index, ARM_NAND_ECC_INFO *info);                          ///< Pointer to \\ref ARM_NAND_InquireECC : Inquire about available ECC. \n} const ARM_DRIVER_NAND;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_NAND_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_SAI.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        31. March 2020\n * $Revision:    V1.2\n *\n * Project:      SAI (Serial Audio Interface) Driver definitions\n */\n\n/* History:\n *  Version 1.2\n *    Removed volatile from ARM_SAI_STATUS\n *  Version 1.1\n *    ARM_SAI_STATUS made volatile\n *  Version 1.0\n *    Initial release\n */\n\n#ifndef DRIVER_SAI_H_\n#define DRIVER_SAI_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2)  /* API version */\n\n\n#define _ARM_Driver_SAI_(n)      Driver_SAI##n\n#define  ARM_Driver_SAI_(n) _ARM_Driver_SAI_(n)\n\n\n/****** SAI Control Codes *****/\n\n#define ARM_SAI_CONTROL_Msk             (0xFFUL)\n#define ARM_SAI_CONFIGURE_TX            (0x01UL)    ///< Configure Transmitter;  arg1 and arg2 provide additional configuration\n#define ARM_SAI_CONFIGURE_RX            (0x02UL)    ///< Configure Receiver;     arg1 and arg2 provide additional configuration\n#define ARM_SAI_CONTROL_TX              (0x03UL)    ///< Control Transmitter;    arg1.0: 0=disable (default), 1=enable; arg1.1: mute\n#define ARM_SAI_CONTROL_RX              (0x04UL)    ///< Control Receiver;       arg1.0: 0=disable (default), 1=enable\n#define ARM_SAI_MASK_SLOTS_TX           (0x05UL)    ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default\n#define ARM_SAI_MASK_SLOTS_RX           (0x06UL)    ///< Mask Receiver    slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default\n#define ARM_SAI_ABORT_SEND              (0x07UL)    ///< Abort \\ref ARM_SAI_Send\n#define ARM_SAI_ABORT_RECEIVE           (0x08UL)    ///< Abort \\ref ARM_SAI_Receive\n\n/*----- SAI Control Codes: Configuration Parameters: Mode -----*/\n#define ARM_SAI_MODE_Pos                 8\n#define ARM_SAI_MODE_Msk                (1UL << ARM_SAI_MODE_Pos)\n#define ARM_SAI_MODE_MASTER             (1UL << ARM_SAI_MODE_Pos)               ///< Master Mode\n#define ARM_SAI_MODE_SLAVE              (0UL << ARM_SAI_MODE_Pos)               ///< Slave Mode (default)\n\n/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/\n#define ARM_SAI_SYNCHRONIZATION_Pos      9\n#define ARM_SAI_SYNCHRONIZATION_Msk     (1UL << ARM_SAI_SYNCHRONIZATION_Pos)\n#define ARM_SAI_ASYNCHRONOUS            (0UL << ARM_SAI_SYNCHRONIZATION_Pos)    ///< Asynchronous (default)\n#define ARM_SAI_SYNCHRONOUS             (1UL << ARM_SAI_SYNCHRONIZATION_Pos)    ///< Synchronous\n\n/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/\n#define ARM_SAI_PROTOCOL_Pos             10\n#define ARM_SAI_PROTOCOL_Msk            (7UL << ARM_SAI_PROTOCOL_Pos)\n#define ARM_SAI_PROTOCOL_USER           (0UL << ARM_SAI_PROTOCOL_Pos)           ///< User defined (default) \n#define ARM_SAI_PROTOCOL_I2S            (1UL << ARM_SAI_PROTOCOL_Pos)           ///< I2S\n#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED  (2UL << ARM_SAI_PROTOCOL_Pos)           ///< MSB (left) justified \n#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED  (3UL << ARM_SAI_PROTOCOL_Pos)           ///< LSB (right) justified\n#define ARM_SAI_PROTOCOL_PCM_SHORT      (4UL << ARM_SAI_PROTOCOL_Pos)           ///< PCM with short frame\n#define ARM_SAI_PROTOCOL_PCM_LONG       (5UL << ARM_SAI_PROTOCOL_Pos)           ///< PCM with long frame\n#define ARM_SAI_PROTOCOL_AC97           (6UL << ARM_SAI_PROTOCOL_Pos)           ///< AC'97\n\n/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/\n#define ARM_SAI_DATA_SIZE_Pos            13\n#define ARM_SAI_DATA_SIZE_Msk                      (0x1FUL  << ARM_SAI_DATA_SIZE_Pos)\n#define ARM_SAI_DATA_SIZE(n)            ((((n)-1UL)&0x1FUL) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32)\n\n/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/\n#define ARM_SAI_BIT_ORDER_Pos            18\n#define ARM_SAI_BIT_ORDER_Msk           (1UL << ARM_SAI_BIT_ORDER_Pos)\n#define ARM_SAI_MSB_FIRST               (0UL << ARM_SAI_BIT_ORDER_Pos)          ///< Data is transferred with MSB first (default)\n#define ARM_SAI_LSB_FIRST               (1UL << ARM_SAI_BIT_ORDER_Pos)          ///< Data is transferred with LSB first; User Protocol only (ignored otherwise)\n\n/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/\n#define ARM_SAI_MONO_MODE               (1UL << 19)                             ///< Mono Mode (only for I2S, MSB/LSB justified)\n\n/*----- SAI Control Codes:Configuration Parameters: Companding -----*/\n#define ARM_SAI_COMPANDING_Pos           20\n#define ARM_SAI_COMPANDING_Msk          (3UL << ARM_SAI_COMPANDING_Pos)\n#define ARM_SAI_COMPANDING_NONE         (0UL << ARM_SAI_COMPANDING_Pos)         ///< No companding (default)\n#define ARM_SAI_COMPANDING_A_LAW        (2UL << ARM_SAI_COMPANDING_Pos)         ///< A-Law companding\n#define ARM_SAI_COMPANDING_U_LAW        (3UL << ARM_SAI_COMPANDING_Pos)         ///< u-Law companding\n\n/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/\n#define ARM_SAI_CLOCK_POLARITY_Pos       23\n#define ARM_SAI_CLOCK_POLARITY_Msk      (1UL << ARM_SAI_CLOCK_POLARITY_Pos)\n#define ARM_SAI_CLOCK_POLARITY_0        (0UL << ARM_SAI_CLOCK_POLARITY_Pos)     ///< Drive on falling edge, Capture on rising  edge (default)\n#define ARM_SAI_CLOCK_POLARITY_1        (1UL << ARM_SAI_CLOCK_POLARITY_Pos)     ///< Drive on rising  edge, Capture on falling edge\n\n/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/\n#define ARM_SAI_MCLK_PIN_Pos             24\n#define ARM_SAI_MCLK_PIN_Msk            (3UL << ARM_SAI_MCLK_PIN_Pos)\n#define ARM_SAI_MCLK_PIN_INACTIVE       (0UL << ARM_SAI_MCLK_PIN_Pos)           ///< MCLK not used (default)\n#define ARM_SAI_MCLK_PIN_OUTPUT         (1UL << ARM_SAI_MCLK_PIN_Pos)           ///< MCLK is output (Master only)\n#define ARM_SAI_MCLK_PIN_INPUT          (2UL << ARM_SAI_MCLK_PIN_Pos)           ///< MCLK is input  (Master only)\n\n\n/****** SAI Configuration (arg1) *****/\n\n/*----- SAI Configuration (arg1): Frame Length -----*/\n#define ARM_SAI_FRAME_LENGTH_Pos          0\n#define ARM_SAI_FRAME_LENGTH_Msk                    (0x3FFUL  << ARM_SAI_FRAME_LENGTH_Pos)\n#define ARM_SAI_FRAME_LENGTH(n)          ((((n)-1UL)&0x3FFUL) << ARM_SAI_FRAME_LENGTH_Pos)  ///< Frame length in bits (8..1024); default depends on protocol and data\n\n/*----- SAI Configuration (arg1): Frame Sync Width -----*/\n#define ARM_SAI_FRAME_SYNC_WIDTH_Pos      10\n#define ARM_SAI_FRAME_SYNC_WIDTH_Msk                (0xFFUL  << ARM_SAI_FRAME_SYNC_WIDTH_Pos)\n#define ARM_SAI_FRAME_SYNC_WIDTH(n)      ((((n)-1UL)&0xFFUL) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise)\n\n/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/\n#define ARM_SAI_FRAME_SYNC_POLARITY_Pos   18\n#define ARM_SAI_FRAME_SYNC_POLARITY_Msk  (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)\n#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)           ///< Frame Sync is active high (default); User Protocol only (ignored otherwise)\n#define ARM_SAI_FRAME_SYNC_POLARITY_LOW  (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)           ///< Frame Sync is active low; User Protocol only (ignored otherwise)\n\n/*----- SAI Configuration (arg1): Frame Sync Early -----*/\n#define ARM_SAI_FRAME_SYNC_EARLY         (1UL << 19)                                        ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise)\n\n/*----- SAI Configuration (arg1): Slot Count -----*/\n#define ARM_SAI_SLOT_COUNT_Pos            20\n#define ARM_SAI_SLOT_COUNT_Msk                      (0x1FUL  << ARM_SAI_SLOT_COUNT_Pos)\n#define ARM_SAI_SLOT_COUNT(n)            ((((n)-1UL)&0x1FUL) << ARM_SAI_SLOT_COUNT_Pos)     ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise)\n\n/*----- SAI Configuration (arg1): Slot Size -----*/\n#define ARM_SAI_SLOT_SIZE_Pos             25\n#define ARM_SAI_SLOT_SIZE_Msk            (3UL << ARM_SAI_SLOT_SIZE_Pos)\n#define ARM_SAI_SLOT_SIZE_DEFAULT        (0UL << ARM_SAI_SLOT_SIZE_Pos)                     ///< Slot size is equal to data size (default)\n#define ARM_SAI_SLOT_SIZE_16             (1UL << ARM_SAI_SLOT_SIZE_Pos)                     ///< Slot size = 16 bits; User Protocol only (ignored otherwise)\n#define ARM_SAI_SLOT_SIZE_32             (3UL << ARM_SAI_SLOT_SIZE_Pos)                     ///< Slot size = 32 bits; User Protocol only (ignored otherwise)\n\n/*----- SAI Configuration (arg1): Slot Offset -----*/\n#define ARM_SAI_SLOT_OFFSET_Pos           27\n#define ARM_SAI_SLOT_OFFSET_Msk               (0x1FUL  << ARM_SAI_SLOT_OFFSET_Pos)\n#define ARM_SAI_SLOT_OFFSET(n)           (((n)&0x1FUL) << ARM_SAI_SLOT_OFFSET_Pos)          ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise)\n\n/****** SAI Configuration (arg2) *****/\n\n/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/\n#define ARM_SAI_AUDIO_FREQ_Msk          (0x0FFFFFUL)                                        ///< Audio frequency mask\n\n/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/\n#define ARM_SAI_MCLK_PRESCALER_Pos       20\n#define ARM_SAI_MCLK_PRESCALER_Msk      (0xFFFUL << ARM_SAI_MCLK_PRESCALER_Pos)\n#define ARM_SAI_MCLK_PRESCALER(n)       ((((n)-1UL)&0xFFFUL) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1)\n\n\n/****** SAI specific error codes *****/\n#define ARM_SAI_ERROR_SYNCHRONIZATION       (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Synchronization not supported\n#define ARM_SAI_ERROR_PROTOCOL              (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Protocol not supported\n#define ARM_SAI_ERROR_DATA_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified Data size not supported\n#define ARM_SAI_ERROR_BIT_ORDER             (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported\n#define ARM_SAI_ERROR_MONO_MODE             (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Mono mode not supported\n#define ARM_SAI_ERROR_COMPANDING            (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Companding not supported\n#define ARM_SAI_ERROR_CLOCK_POLARITY        (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock polarity not supported\n#define ARM_SAI_ERROR_AUDIO_FREQ            (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Audio frequency not supported\n#define ARM_SAI_ERROR_MCLK_PIN              (ARM_DRIVER_ERROR_SPECIFIC - 9)     ///< Specified MCLK Pin setting not supported\n#define ARM_SAI_ERROR_MCLK_PRESCALER        (ARM_DRIVER_ERROR_SPECIFIC - 10)    ///< Specified MCLK Prescaler not supported\n#define ARM_SAI_ERROR_FRAME_LENGTH          (ARM_DRIVER_ERROR_SPECIFIC - 11)    ///< Specified Frame length not supported\n#define ARM_SAI_ERROR_FRAME_LENGHT          (ARM_DRIVER_ERROR_SPECIFIC - 11)    ///< Specified Frame length not supported @deprecated use \\ref ARM_SAI_ERROR_FRAME_LENGTH instead\n#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH      (ARM_DRIVER_ERROR_SPECIFIC - 12)    ///< Specified Frame Sync width not supported\n#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY   (ARM_DRIVER_ERROR_SPECIFIC - 13)    ///< Specified Frame Sync polarity not supported\n#define ARM_SAI_ERROR_FRAME_SYNC_EARLY      (ARM_DRIVER_ERROR_SPECIFIC - 14)    ///< Specified Frame Sync early not supported\n#define ARM_SAI_ERROR_SLOT_COUNT            (ARM_DRIVER_ERROR_SPECIFIC - 15)    ///< Specified Slot count not supported\n#define ARM_SAI_ERROR_SLOT_SIZE             (ARM_DRIVER_ERROR_SPECIFIC - 16)    ///< Specified Slot size not supported\n#define ARM_SAI_ERROR_SLOT_OFFESET          (ARM_DRIVER_ERROR_SPECIFIC - 17)    ///< Specified Slot offset not supported\n\n\n/**\n\\brief SAI Status\n*/\ntypedef struct _ARM_SAI_STATUS {\n  uint32_t tx_busy          : 1;        ///< Transmitter busy flag\n  uint32_t rx_busy          : 1;        ///< Receiver busy flag\n  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)\n  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)\n  uint32_t frame_error      : 1;        ///< Sync Frame error detected (cleared on start of next send/receive operation)\n  uint32_t reserved         : 27;\n} ARM_SAI_STATUS;\n\n\n/****** SAI Event *****/\n#define ARM_SAI_EVENT_SEND_COMPLETE     (1UL << 0)  ///< Send completed\n#define ARM_SAI_EVENT_RECEIVE_COMPLETE  (1UL << 1)  ///< Receive completed\n#define ARM_SAI_EVENT_TX_UNDERFLOW      (1UL << 2)  ///< Transmit data not available\n#define ARM_SAI_EVENT_RX_OVERFLOW       (1UL << 3)  ///< Receive data overflow\n#define ARM_SAI_EVENT_FRAME_ERROR       (1UL << 4)  ///< Sync Frame error in Slave mode (optional)\n\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n\n  \\fn          ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_SAI_CAPABILITIES\n\n  \\fn          int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)\n  \\brief       Initialize SAI Interface.\n  \\param[in]   cb_event  Pointer to \\ref ARM_SAI_SignalEvent\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_SAI_Uninitialize (void)\n  \\brief       De-initialize SAI Interface.\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control SAI Interface Power.\n  \\param[in]   state  Power state\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_SAI_Send (const void *data, uint32_t num)\n  \\brief       Start sending data to SAI transmitter.\n  \\param[in]   data  Pointer to buffer with data to send to SAI transmitter\n  \\param[in]   num   Number of data items to send\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_SAI_Receive (void *data, uint32_t num)\n  \\brief       Start receiving data from SAI receiver.\n  \\param[out]  data  Pointer to buffer for data to receive from SAI receiver\n  \\param[in]   num   Number of data items to receive\n  \\return      \\ref execution_status\n\n  \\fn          uint32_t ARM_SAI_GetTxCount (void)\n  \\brief       Get transmitted data count.\n  \\return      number of data items transmitted\n\n  \\fn          uint32_t ARM_SAI_GetRxCount (void)\n  \\brief       Get received data count.\n  \\return      number of data items received\n\n  \\fn          int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)\n  \\brief       Control SAI Interface.\n  \\param[in]   control  Operation\n  \\param[in]   arg1     Argument 1 of operation (optional)\n  \\param[in]   arg2     Argument 2 of operation (optional)\n  \\return      common \\ref execution_status and driver specific \\ref sai_execution_status\n\n  \\fn          ARM_SAI_STATUS ARM_SAI_GetStatus (void)\n  \\brief       Get SAI status.\n  \\return      SAI status \\ref ARM_SAI_STATUS\n\n  \\fn          void ARM_SAI_SignalEvent (uint32_t event)\n  \\brief       Signal SAI Events.\n  \\param[in]   event \\ref SAI_events notification mask\n  \\return      none\n*/\n\ntypedef void (*ARM_SAI_SignalEvent_t) (uint32_t event);  ///< Pointer to \\ref ARM_SAI_SignalEvent : Signal SAI Event.\n\n\n/**\n\\brief SAI Driver Capabilities.\n*/\ntypedef struct _ARM_SAI_CAPABILITIES {\n  uint32_t asynchronous          : 1;   ///< supports asynchronous Transmit/Receive\n  uint32_t synchronous           : 1;   ///< supports synchronous Transmit/Receive\n  uint32_t protocol_user         : 1;   ///< supports user defined Protocol\n  uint32_t protocol_i2s          : 1;   ///< supports I2S Protocol\n  uint32_t protocol_justified    : 1;   ///< supports MSB/LSB justified Protocol\n  uint32_t protocol_pcm          : 1;   ///< supports PCM short/long frame Protocol\n  uint32_t protocol_ac97         : 1;   ///< supports AC'97 Protocol\n  uint32_t mono_mode             : 1;   ///< supports Mono mode\n  uint32_t companding            : 1;   ///< supports Companding\n  uint32_t mclk_pin              : 1;   ///< supports MCLK (Master Clock) pin\n  uint32_t event_frame_error     : 1;   ///< supports Frame error event: \\ref ARM_SAI_EVENT_FRAME_ERROR\n  uint32_t reserved              : 21;  ///< Reserved (must be zero)\n} ARM_SAI_CAPABILITIES;\n\n\n/**\n\\brief Access structure of the SAI Driver.\n*/\ntypedef struct _ARM_DRIVER_SAI {\n  ARM_DRIVER_VERSION   (*GetVersion)      (void);                                            ///< Pointer to \\ref ARM_SAI_GetVersion : Get driver version.\n  ARM_SAI_CAPABILITIES (*GetCapabilities) (void);                                            ///< Pointer to \\ref ARM_SAI_GetCapabilities : Get driver capabilities.\n  int32_t              (*Initialize)      (ARM_SAI_SignalEvent_t cb_event);                  ///< Pointer to \\ref ARM_SAI_Initialize : Initialize SAI Interface.\n  int32_t              (*Uninitialize)    (void);                                            ///< Pointer to \\ref ARM_SAI_Uninitialize : De-initialize SAI Interface.\n  int32_t              (*PowerControl)    (ARM_POWER_STATE state);                           ///< Pointer to \\ref ARM_SAI_PowerControl : Control SAI Interface Power.\n  int32_t              (*Send)            (const void *data, uint32_t num);                  ///< Pointer to \\ref ARM_SAI_Send : Start sending data to SAI Interface.\n  int32_t              (*Receive)         (      void *data, uint32_t num);                  ///< Pointer to \\ref ARM_SAI_Receive : Start receiving data from SAI Interface.\n  uint32_t             (*GetTxCount)      (void);                                            ///< Pointer to \\ref ARM_SAI_GetTxCount : Get transmitted data count.\n  uint32_t             (*GetRxCount)      (void);                                            ///< Pointer to \\ref ARM_SAI_GetRxCount : Get received data count.\n  int32_t              (*Control)         (uint32_t control, uint32_t arg1, uint32_t arg2);  ///< Pointer to \\ref ARM_SAI_Control : Control SAI Interface.\n  ARM_SAI_STATUS       (*GetStatus)       (void);                                            ///< Pointer to \\ref ARM_SAI_GetStatus : Get SAI status.\n} const ARM_DRIVER_SAI;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_SAI_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_SPI.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        31. March 2020\n * $Revision:    V2.3\n *\n * Project:      SPI (Serial Peripheral Interface) Driver definitions\n */\n\n/* History:\n *  Version 2.3\n *    Removed Simplex Mode (deprecated)\n *    Removed volatile from ARM_SPI_STATUS\n *  Version 2.2\n *    ARM_SPI_STATUS made volatile\n *  Version 2.1\n *    Renamed status flag \"tx_rx_busy\" to \"busy\"\n *  Version 2.0\n *    New simplified driver:\n *      complexity moved to upper layer (especially data handling)\n *      more unified API for different communication interfaces\n *    Added:\n *      Slave Mode\n *      Half-duplex Modes\n *      Configurable number of data bits\n *      Support for TI Mode and Microwire\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.01\n *    Added \"send_done_event\" to Capabilities\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_SPI_H_\n#define DRIVER_SPI_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */\n\n\n#define _ARM_Driver_SPI_(n)      Driver_SPI##n\n#define  ARM_Driver_SPI_(n) _ARM_Driver_SPI_(n)\n\n\n/****** SPI Control Codes *****/\n\n#define ARM_SPI_CONTROL_Pos              0\n#define ARM_SPI_CONTROL_Msk             (0xFFUL << ARM_SPI_CONTROL_Pos)\n\n/*----- SPI Control Codes: Mode -----*/\n#define ARM_SPI_MODE_INACTIVE           (0x00UL << ARM_SPI_CONTROL_Pos)     ///< SPI Inactive\n#define ARM_SPI_MODE_MASTER             (0x01UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps\n#define ARM_SPI_MODE_SLAVE              (0x02UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output on MISO, Input on MOSI)\n#define ARM_SPI_MODE_MASTER_SIMPLEX     (0x03UL << ARM_SPI_CONTROL_Pos)     ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps @deprecated Simplex Mode has been removed\n#define ARM_SPI_MODE_SLAVE_SIMPLEX      (0x04UL << ARM_SPI_CONTROL_Pos)     ///< SPI Slave  (Output/Input on MISO) @deprecated Simplex Mode has been removed\n\n/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/\n#define ARM_SPI_FRAME_FORMAT_Pos         8\n#define ARM_SPI_FRAME_FORMAT_Msk        (7UL << ARM_SPI_FRAME_FORMAT_Pos)\n#define ARM_SPI_CPOL0_CPHA0             (0UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 0 (default)\n#define ARM_SPI_CPOL0_CPHA1             (1UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 0, Clock Phase 1\n#define ARM_SPI_CPOL1_CPHA0             (2UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 0\n#define ARM_SPI_CPOL1_CPHA1             (3UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Clock Polarity 1, Clock Phase 1\n#define ARM_SPI_TI_SSI                  (4UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< Texas Instruments Frame Format\n#define ARM_SPI_MICROWIRE               (5UL << ARM_SPI_FRAME_FORMAT_Pos)   ///< National Semiconductor Microwire Frame Format\n\n/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/\n#define ARM_SPI_DATA_BITS_Pos            12\n#define ARM_SPI_DATA_BITS_Msk           (0x3FUL << ARM_SPI_DATA_BITS_Pos)\n#define ARM_SPI_DATA_BITS(n)            (((n) & 0x3FUL) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits\n\n/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/\n#define ARM_SPI_BIT_ORDER_Pos            18\n#define ARM_SPI_BIT_ORDER_Msk           (1UL << ARM_SPI_BIT_ORDER_Pos)\n#define ARM_SPI_MSB_LSB                 (0UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from MSB to LSB (default)\n#define ARM_SPI_LSB_MSB                 (1UL << ARM_SPI_BIT_ORDER_Pos)      ///< SPI Bit order from LSB to MSB\n\n/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/\n#define ARM_SPI_SS_MASTER_MODE_Pos       19\n#define ARM_SPI_SS_MASTER_MODE_Msk      (3UL << ARM_SPI_SS_MASTER_MODE_Pos)\n#define ARM_SPI_SS_MASTER_UNUSED        (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default)\n#define ARM_SPI_SS_MASTER_SW            (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled\n#define ARM_SPI_SS_MASTER_HW_OUTPUT     (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output\n#define ARM_SPI_SS_MASTER_HW_INPUT      (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input\n#define ARM_SPI_SS_SLAVE_MODE_Pos        21\n#define ARM_SPI_SS_SLAVE_MODE_Msk       (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)\n#define ARM_SPI_SS_SLAVE_HW             (0UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Hardware monitored (default)\n#define ARM_SPI_SS_SLAVE_SW             (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)  ///< SPI Slave Select when Slave: Software controlled\n\n\n/*----- SPI Control Codes: Miscellaneous Controls  -----*/\n#define ARM_SPI_SET_BUS_SPEED           (0x10UL << ARM_SPI_CONTROL_Pos)     ///< Set Bus Speed in bps; arg = value\n#define ARM_SPI_GET_BUS_SPEED           (0x11UL << ARM_SPI_CONTROL_Pos)     ///< Get Bus Speed in bps\n#define ARM_SPI_SET_DEFAULT_TX_VALUE    (0x12UL << ARM_SPI_CONTROL_Pos)     ///< Set default Transmit value; arg = value\n#define ARM_SPI_CONTROL_SS              (0x13UL << ARM_SPI_CONTROL_Pos)     ///< Control Slave Select; arg: 0=inactive, 1=active \n#define ARM_SPI_ABORT_TRANSFER          (0x14UL << ARM_SPI_CONTROL_Pos)     ///< Abort current data transfer\n\n\n/****** SPI Slave Select Signal definitions *****/\n#define ARM_SPI_SS_INACTIVE              0UL                                ///< SPI Slave Select Signal Inactive\n#define ARM_SPI_SS_ACTIVE                1UL                                ///< SPI Slave Select Signal Active\n\n\n/****** SPI specific error codes *****/\n#define ARM_SPI_ERROR_MODE              (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported\n#define ARM_SPI_ERROR_FRAME_FORMAT      (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified Frame Format not supported\n#define ARM_SPI_ERROR_DATA_BITS         (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported\n#define ARM_SPI_ERROR_BIT_ORDER         (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Bit order not supported\n#define ARM_SPI_ERROR_SS_MODE           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified Slave Select Mode not supported\n\n\n/**\n\\brief SPI Status\n*/\ntypedef struct _ARM_SPI_STATUS {\n  uint32_t busy       : 1;              ///< Transmitter/Receiver busy flag\n  uint32_t data_lost  : 1;              ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)\n  uint32_t mode_fault : 1;              ///< Mode fault detected; optional (cleared on start of transfer operation)\n  uint32_t reserved   : 29;\n} ARM_SPI_STATUS;\n\n\n/****** SPI Event *****/\n#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0)  ///< Data Transfer completed\n#define ARM_SPI_EVENT_DATA_LOST         (1UL << 1)  ///< Data lost: Receive overflow / Transmit underflow\n#define ARM_SPI_EVENT_MODE_FAULT        (1UL << 2)  ///< Master Mode Fault (SS deactivated when Master)\n\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_SPI_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n\n  \\fn          ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_SPI_CAPABILITIES\n\n  \\fn          int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)\n  \\brief       Initialize SPI Interface.\n  \\param[in]   cb_event  Pointer to \\ref ARM_SPI_SignalEvent\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_SPI_Uninitialize (void)\n  \\brief       De-initialize SPI Interface.\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control SPI Interface Power.\n  \\param[in]   state  Power state\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_SPI_Send (const void *data, uint32_t num)\n  \\brief       Start sending data to SPI transmitter.\n  \\param[in]   data  Pointer to buffer with data to send to SPI transmitter\n  \\param[in]   num   Number of data items to send\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_SPI_Receive (void *data, uint32_t num)\n  \\brief       Start receiving data from SPI receiver.\n  \\param[out]  data  Pointer to buffer for data to receive from SPI receiver\n  \\param[in]   num   Number of data items to receive\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_SPI_Transfer (const void *data_out,\n                                               void *data_in,\n                                         uint32_t    num)\n  \\brief       Start sending/receiving data to/from SPI transmitter/receiver.\n  \\param[in]   data_out  Pointer to buffer with data to send to SPI transmitter\n  \\param[out]  data_in   Pointer to buffer for data to receive from SPI receiver\n  \\param[in]   num       Number of data items to transfer\n  \\return      \\ref execution_status\n\n  \\fn          uint32_t ARM_SPI_GetDataCount (void)\n  \\brief       Get transferred data count.\n  \\return      number of data items transferred\n\n  \\fn          int32_t ARM_SPI_Control (uint32_t control, uint32_t arg)\n  \\brief       Control SPI Interface.\n  \\param[in]   control  Operation\n  \\param[in]   arg      Argument of operation (optional)\n  \\return      common \\ref execution_status and driver specific \\ref spi_execution_status\n\n  \\fn          ARM_SPI_STATUS ARM_SPI_GetStatus (void)\n  \\brief       Get SPI status.\n  \\return      SPI status \\ref ARM_SPI_STATUS\n\n  \\fn          void ARM_SPI_SignalEvent (uint32_t event)\n  \\brief       Signal SPI Events.\n  \\param[in]   event \\ref SPI_events notification mask\n  \\return      none\n*/\n\ntypedef void (*ARM_SPI_SignalEvent_t) (uint32_t event);  ///< Pointer to \\ref ARM_SPI_SignalEvent : Signal SPI Event.\n\n\n/**\n\\brief SPI Driver Capabilities.\n*/\ntypedef struct _ARM_SPI_CAPABILITIES {\n  uint32_t simplex          : 1;        ///< supports Simplex Mode (Master and Slave) @deprecated Reserved (must be zero)\n  uint32_t ti_ssi           : 1;        ///< supports TI Synchronous Serial Interface\n  uint32_t microwire        : 1;        ///< supports Microwire Interface\n  uint32_t event_mode_fault : 1;        ///< Signal Mode Fault event: \\ref ARM_SPI_EVENT_MODE_FAULT\n  uint32_t reserved         : 28;       ///< Reserved (must be zero)\n} ARM_SPI_CAPABILITIES;\n\n\n/**\n\\brief Access structure of the SPI Driver.\n*/\ntypedef struct _ARM_DRIVER_SPI {\n  ARM_DRIVER_VERSION   (*GetVersion)      (void);                             ///< Pointer to \\ref ARM_SPI_GetVersion : Get driver version.\n  ARM_SPI_CAPABILITIES (*GetCapabilities) (void);                             ///< Pointer to \\ref ARM_SPI_GetCapabilities : Get driver capabilities.\n  int32_t              (*Initialize)      (ARM_SPI_SignalEvent_t cb_event);   ///< Pointer to \\ref ARM_SPI_Initialize : Initialize SPI Interface.\n  int32_t              (*Uninitialize)    (void);                             ///< Pointer to \\ref ARM_SPI_Uninitialize : De-initialize SPI Interface.\n  int32_t              (*PowerControl)    (ARM_POWER_STATE state);            ///< Pointer to \\ref ARM_SPI_PowerControl : Control SPI Interface Power.\n  int32_t              (*Send)            (const void *data, uint32_t num);   ///< Pointer to \\ref ARM_SPI_Send : Start sending data to SPI Interface.\n  int32_t              (*Receive)         (      void *data, uint32_t num);   ///< Pointer to \\ref ARM_SPI_Receive : Start receiving data from SPI Interface.\n  int32_t              (*Transfer)        (const void *data_out,\n                                                 void *data_in,\n                                           uint32_t    num);                  ///< Pointer to \\ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI.\n  uint32_t             (*GetDataCount)    (void);                             ///< Pointer to \\ref ARM_SPI_GetDataCount : Get transferred data count.\n  int32_t              (*Control)         (uint32_t control, uint32_t arg);   ///< Pointer to \\ref ARM_SPI_Control : Control SPI Interface.\n  ARM_SPI_STATUS       (*GetStatus)       (void);                             ///< Pointer to \\ref ARM_SPI_GetStatus : Get SPI status.\n} const ARM_DRIVER_SPI;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_SPI_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_Storage.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        24. January 2020\n * $Revision:    V1.2\n *\n * Project:      Storage Driver definitions\n */\n\n/* History:\n *  Version 1.2\n *    Removed volatile from ARM_STORAGE_STATUS\n *  Version 1.1\n *    ARM_STORAGE_STATUS made volatile\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_STORAGE_H_\n#define DRIVER_STORAGE_H_\n\n#ifdef  __cplusplus\nextern \"C\" {\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2)  /* API version */\n\n\n#define _ARM_Driver_Storage_(n)      Driver_Storage##n\n#define  ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)\n\n#define ARM_STORAGE_INVALID_OFFSET  (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's\n                                                            ///  address space). A storage block may never start at this address.\n\n#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL)          ///< Invalid address within the processor's memory address space.\n                                                            ///  Refer to memory-mapped storage, i.e. \\ref ARM_DRIVER_STORAGE::ResolveAddress().\n\n/****** Storage specific error codes *****/\n#define ARM_STORAGE_ERROR_NOT_ERASABLE      (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.\n#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE  (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.\n#define ARM_STORAGE_ERROR_PROTECTED         (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.\n\n/**\n * \\brief Attributes of the storage range within a storage block.\n */\ntypedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {\n  uint32_t erasable      :  1;   ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.\n                                 ///   @note if 'erasable' is 0 (i.e. the 'erase' operation isn't available) then\n                                 ///   'erase_unit' (see below) is immaterial and should be 0.\n  uint32_t programmable  :  1;   ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.\n                                 ///    Writes are typically achieved through the ProgramData operation (following an erase);\n                                 ///    if storage isn't erasable (see 'erasable' above) but is memory-mapped\n                                 ///    (i.e. 'memory_mapped'), it can be written directly using memory-store operations.\n  uint32_t executable    :  1;   ///< This storage block can hold program data; the processor can fetch and execute code\n                                 ///    sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \\ref ARM_STORAGE_INFO).\n  uint32_t protectable   :  1;   ///< The entire block can be protected from program and erase operations. Once protection\n                                 ///    is enabled for a block, its 'erasable' and 'programmable' bits are turned off.\n  uint32_t reserved      : 28;\n  uint32_t erase_unit;           ///< Minimum erase size in bytes.\n                                 ///    The offset of the start of the erase-range should also be aligned with this value.\n                                 ///    Applicable if the 'erasable' attribute is set for the block.\n                                 ///    @note if 'erasable' (see above) is 0 (i.e. the 'erase' operation isn't available) then\n                                 ///    'erase_unit' is immaterial and should be 0.\n  uint32_t protection_unit;      ///< Minimum protectable size in bytes. Applicable if the 'protectable'\n                                 ///    attribute is set for the block. This should be a divisor of the block's size. A\n                                 ///    block can be considered to be made up of consecutive, individually-protectable fragments.\n} ARM_STORAGE_BLOCK_ATTRIBUTES;\n\n/**\n * \\brief A storage block is a range of memory with uniform attributes.\n */\ntypedef struct _ARM_STORAGE_BLOCK {\n  uint64_t                     addr;       ///< This is the start address of the storage block. It is\n                                           ///    expressed as an offset from the start of the storage map\n                                           ///    maintained by the owning storage controller.\n  uint64_t                     size;       ///< This is the size of the storage block, in units of bytes.\n                                           ///    Together with addr, it describes a range [addr, addr+size).\n  ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.\n} ARM_STORAGE_BLOCK;\n\n/**\n * The check for a valid ARM_STORAGE_BLOCK.\n */\n#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))\n\n/**\n * \\brief Values for encoding storage memory-types with respect to programmability.\n *\n * Please ensure that the maximum of the following memory types doesn't exceed 16; we\n * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.\n */\n#define ARM_STORAGE_PROGRAMMABILITY_RAM       (0U)\n#define ARM_STORAGE_PROGRAMMABILITY_ROM       (1U)  ///< Read-only memory.\n#define ARM_STORAGE_PROGRAMMABILITY_WORM      (2U)  ///< write-once-read-only-memory (WORM).\n#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE  (3U)  ///< re-programmable based on erase. Supports multiple writes.\n\n/**\n * Values for encoding data-retention levels for storage blocks.\n *\n * Please ensure that the maximum of the following retention types doesn't exceed 16; we\n * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.\n */\n#define ARM_RETENTION_WHILE_DEVICE_ACTIVE     (0U)  ///< Data is retained only during device activity.\n#define ARM_RETENTION_ACROSS_SLEEP            (1U)  ///< Data is retained across processor sleep.\n#define ARM_RETENTION_ACROSS_DEEP_SLEEP       (2U)  ///< Data is retained across processor deep-sleep.\n#define ARM_RETENTION_BATTERY_BACKED          (3U)  ///< Data is battery-backed. Device can be powered off.\n#define ARM_RETENTION_NVM                     (4U)  ///< Data is retained in non-volatile memory.\n\n/**\n * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.\n */\ntypedef struct _ARM_STORAGE_SECURITY_FEATURES {\n  uint32_t acls                :  1; ///< Protection against internal software attacks using ACLs.\n  uint32_t rollback_protection :  1; ///< Roll-back protection. Set to true if the creator of the storage\n                                     ///    can ensure that an external attacker can't force an\n                                     ///    older firmware to run or to revert back to a previous state.\n  uint32_t tamper_proof        :  1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).\n  uint32_t internal_flash      :  1; ///< Internal flash.\n  uint32_t reserved1           : 12;\n\n  /**\n   * Encode support for hardening against various classes of attacks.\n   */\n  uint32_t software_attacks     :  1; ///< device software (malware running on the device).\n  uint32_t board_level_attacks  :  1; ///< board level attacks (debug probes, copy protection fuses.)\n  uint32_t chip_level_attacks   :  1; ///< chip level attacks (tamper-protection).\n  uint32_t side_channel_attacks :  1; ///< side channel attacks.\n  uint32_t reserved2            : 12;\n} ARM_STORAGE_SECURITY_FEATURES;\n\n#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */\n\n/**\n * Device level metadata regarding the Storage implementation.\n */\ntypedef struct _ARM_STORAGE_INFO {\n  uint64_t                      total_storage;        ///< Total available storage, in bytes.\n  uint32_t                      program_unit;         ///< Minimum programming size in bytes.\n                                                      ///    The offset of the start of the program-range should also be aligned with this value.\n                                                      ///    Applicable only if the 'programmable' attribute is set for a block.\n                                                      ///    @note setting program_unit to 0 has the effect of disabling the size and alignment\n                                                      ///    restrictions (setting it to 1 also has the same effect).\n  uint32_t                      optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers\n                                                      ///    have internal buffers into which to receive data. Writing in chunks of\n                                                      ///    'optimal_program_unit' would achieve maximum programming speed.\n                                                      ///    Applicable only if the 'programmable' attribute is set for the underlying block(s).\n  uint32_t                      program_cycles;       ///< A measure of endurance for reprogramming.\n                                                      ///    Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.\n  uint32_t                      erased_value    :  1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).\n  uint32_t                      memory_mapped   :  1; ///< This storage device has a mapping onto the processor's memory address space.\n                                                      ///    @note For a memory-mapped block which isn't erasable but is programmable (i.e. if\n                                                      ///    'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to\n                                                      ///    the memory-mapped storage without going through the ProgramData operation.\n  uint32_t                      programmability :  4; ///< A value to indicate storage programmability.\n  uint32_t                      retention_level :  4;\n  uint32_t                      reserved        : 22;\n  ARM_STORAGE_SECURITY_FEATURES security;             ///< \\ref ARM_STORAGE_SECURITY_FEATURES\n} ARM_STORAGE_INFO;\n\n/**\n\\brief Operating status of the storage controller.\n*/\ntypedef struct _ARM_STORAGE_STATUS {\n  uint32_t busy     : 1;                ///< Controller busy flag\n  uint32_t error    : 1;                ///< Read/Program/Erase error flag (cleared on start of next operation)\n  uint32_t reserved : 30;\n} ARM_STORAGE_STATUS;\n\n/**\n * \\brief Storage Driver API Capabilities.\n */\ntypedef struct _ARM_STORAGE_CAPABILITIES {\n  uint32_t asynchronous_ops :  1; ///< Used to indicate if APIs like initialize,\n                                  ///    read, erase, program, etc. can operate in asynchronous mode.\n                                  ///    Setting this bit to 1 means that the driver is capable\n                                  ///    of launching asynchronous operations; command completion is\n                                  ///    signaled by the invocation of a completion callback. If\n                                  ///    set to 1, drivers may still complete asynchronous\n                                  ///    operations synchronously as necessary (in which case they\n                                  ///    return a positive error code to indicate synchronous completion).\n  uint32_t erase_all        :  1; ///< Supports EraseAll operation.\n  uint32_t reserved         : 30; ///< Reserved (must be zero)\n} ARM_STORAGE_CAPABILITIES;\n\n/**\n * Command opcodes for Storage.\n */\ntypedef enum _ARM_STORAGE_OPERATION {\n  ARM_STORAGE_OPERATION_GET_VERSION,\n  ARM_STORAGE_OPERATION_GET_CAPABILITIES,\n  ARM_STORAGE_OPERATION_INITIALIZE,\n  ARM_STORAGE_OPERATION_UNINITIALIZE,\n  ARM_STORAGE_OPERATION_POWER_CONTROL,\n  ARM_STORAGE_OPERATION_READ_DATA,\n  ARM_STORAGE_OPERATION_PROGRAM_DATA,\n  ARM_STORAGE_OPERATION_ERASE,\n  ARM_STORAGE_OPERATION_ERASE_ALL,\n  ARM_STORAGE_OPERATION_GET_STATUS,\n  ARM_STORAGE_OPERATION_GET_INFO,\n  ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,\n  ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,\n  ARM_STORAGE_OPERATION_GET_BLOCK\n} ARM_STORAGE_OPERATION;\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_Storage_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn          ARM_STORAGE_CAPABILITIES ARM_Storage_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_STORAGE_CAPABILITIES\n*/\n/**\n  \\fn          int32_t ARM_Storage_Initialize (ARM_Storage_Callback_t callback)\n  \\brief       Initialize the Storage interface.\n  \\param [in]  callback Pointer to \\ref ARM_Storage_Callback_t.\n               Caller-defined callback to be invoked upon command completion\n               for asynchronous APIs (including the completion of\n               initialization). Use a NULL pointer when no callback\n               signals are required.\n  \\return      If asynchronous activity is launched, invocation\n               ARM_DRIVER_OK, and the caller can expect to receive a callback in the\n               future with a status value of ARM_DRIVER_OK or an error-code. In the\n               case of synchronous execution, control returns after completion with a\n               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.\n*/\n/**\n  \\fn          int32_t ARM_Storage_Uninitialize (void)\n  \\brief       De-initialize the Storage Interface.\n  \\return      If asynchronous activity is launched, an invocation returns\n               ARM_DRIVER_OK, and the caller can expect to receive a callback in the\n               future with a status value of ARM_DRIVER_OK or an error-code. In the\n               case of synchronous execution, control returns after completion with a\n               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.\n*/\n/**\n  \\fn          int32_t ARM_Storage_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control the Storage interface power.\n  \\param[in]   state  Power state\n  \\return      If asynchronous activity is launched, an invocation returns\n               ARM_DRIVER_OK, and the caller can expect to receive a callback in the\n               future with a status value of ARM_DRIVER_OK or an error-code. In the\n               case of synchronous execution, control returns after completion with a\n               value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.\n*/\n/**\n  \\fn          int32_t ARM_Storage_ReadData (uint64_t addr, void *data, uint32_t size)\n  \\brief       Read data from Storage.\n  \\param[in]   addr  Data address.\n  \\param[out]  data  Pointer to a buffer storing the data read from Storage.\n  \\param[in]   size  Number of bytes to read. The data buffer\n               should be at least as large as this size.\n  \\return      If asynchronous activity is launched, an invocation returns\n               ARM_DRIVER_OK, and the caller can expect to receive a callback in the\n               future with the number of successfully transferred bytes passed in as\n               the 'status' parameter. In the case of synchronous execution, control\n               returns after completion with a positive transfer-count. Return values\n               less than ARM_DRIVER_OK (0) signify errors.\n*/\n/**\n  \\fn          int32_t ARM_Storage_ProgramData (uint64_t addr, const void *data, uint32_t size)\n  \\brief       Program data to Storage.\n  \\param [in] addr This is the start address of the range to be written into. It\n               needs to be aligned to the device's \\em program_unit\n               specified in \\ref ARM_STORAGE_INFO.\n  \\param [in] data The source of the write operation. The buffer is owned by the\n               caller and should remain accessible for the lifetime of this\n               command.\n  \\param [in] size The number of bytes requested to be written. The buffer\n               should be at least as large as this size. \\note 'size' should\n               be a multiple of the device's 'program_unit' (see \\ref\n               ARM_STORAGE_INFO).\n  \\return      If asynchronous activity is launched, an invocation returns\n               ARM_DRIVER_OK, and the caller can expect to receive a callback in the\n               future with the number of successfully transferred bytes passed in as\n               the 'status' parameter. In the case of synchronous execution, control\n               returns after completion with a positive transfer-count. Return values\n               less than ARM_DRIVER_OK (0) signify errors.\n*/\n/**\n  \\fn          int32_t ARM_Storage_Erase (uint64_t addr, uint32_t size)\n  \\brief       Erase Storage range.\n  \\param [in]  addr This is the start-address of the range to be erased. It must\n               start at an 'erase_unit' boundary of the underlying block.\n  \\param [in]  size Size (in bytes) of the range to be erased. 'addr + size'\n               must be aligned with the 'erase_unit' of the underlying\n               block.\n  \\return      If the range to be erased doesn't align with the erase_units of the\n               respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is\n               returned. If any part of the range is protected,\n               ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the range\n               is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All\n               such sanity-check failures result in the error code being\n               returned synchronously and the storage bytes within the range\n               remain unaffected. Otherwise the function executes in the\n               following ways: If asynchronous activity is launched, an\n               invocation returns ARM_DRIVER_OK, and the caller can expect to\n               receive a callback in the future with the number of successfully\n               erased bytes passed in as the 'status' parameter. In the case of\n               synchronous execution, control returns after completion with a\n               positive erase-count. Return values less than ARM_DRIVER_OK (0)\n               signify errors.\n*/\n/**\n  \\fn          int32_t ARM_Storage_EraseAll (void)\n  \\brief       Erase complete Storage.\n  \\return      If any part of the storage range is protected,\n               ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the\n               storage range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is\n               returned. All such sanity-check failures result in the error code\n               being returned synchronously and the storage bytes within the\n               range remain unaffected. Otherwise the function executes in the\n               following ways: If asynchronous activity is launched, an\n               invocation returns ARM_DRIVER_OK, and the caller can expect to\n               receive a callback in the future with ARM_DRIVER_OK passed in as\n               the 'status' parameter. In the case of synchronous execution,\n               control returns after completion with a value of 1. Return values\n               less than ARM_DRIVER_OK (0) signify errors.\n*/\n/**\n  \\fn          ARM_STORAGE_STATUS ARM_Storage_GetStatus (void)\n  \\brief       Get Storage status.\n  \\return      Storage status \\ref ARM_STORAGE_STATUS\n*/\n/**\n  \\fn          int32_t ARM_Storage_GetInfo (ARM_STORAGE_INFO *info)\n  \\brief       Get Storage information.\n  \\param[out]  info  A caller-supplied buffer capable of being filled in with an \\ref ARM_STORAGE_INFO.\n  \\return      ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level\n               metadata about the storage controller is filled into the supplied\n               buffer, else an appropriate error value.\n*/\n/**\n  \\fn          uint32_t ARM_Storage_ResolveAddress(uint64_t addr)\n  \\brief       Resolve an address relative to the storage controller into a memory address.\n  \\param[in]   addr The address for which we want a resolution to the processor's physical address space. It is an offset from the\n               start of the storage map maintained by the owning storage\n               controller.\n  \\return      The resolved address in the processor's address space, else ARM_STORAGE_INVALID_ADDRESS.\n*/\n/**\n  \\fn          int32_t ARM_Storage_GetNextBlock(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);\n  \\brief       Advance to the successor of the current block (iterator).\n  \\param[in]   prev_block An existing block (iterator) within the same storage\n               controller. The memory buffer holding this block is owned\n               by the caller. This pointer may be NULL; if so, the\n               invocation fills in the first block into the out parameter:\n               'next_block'.\n  \\param[out]  next_block A caller-owned buffer large enough to be filled in with\n               the following ARM_STORAGE_BLOCK. It is legal to provide the\n               same buffer using 'next_block' as was passed in with 'prev_block'. It\n               is also legal to pass a NULL into this parameter if the\n               caller isn't interested in populating a buffer with the next\n               block, i.e. if the caller only wishes to establish the\n               presence of a next block.\n  \\return      ARM_DRIVER_OK if a valid next block is found (or first block, if\n               prev_block is passed as NULL); upon successful operation, the contents\n               of the next (or first) block are filled into the buffer pointed to by\n               the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is\n               guaranteed to be true. Upon reaching the end of the sequence of blocks\n               (iterators), or in case the driver is unable to fetch information about\n               the next (or first) block, an error (negative) value is returned and an\n               invalid StorageBlock is populated into the supplied buffer. If\n               prev_block is NULL, the first block is returned.\n*/\n/**\n  \\fn          int32_t ARM_Storage_GetBlock(uint64_t addr, ARM_STORAGE_BLOCK *block);\n  \\brief       Find the storage block (iterator) encompassing a given storage address.\n  \\param[in]   addr Storage address in bytes.\n  \\param[out]  block A caller-owned buffer large enough to be filled in with the\n               ARM_STORAGE_BLOCK encapsulating the given address. This value\n               can also be passed in as NULL if the caller isn't interested\n               in populating a buffer with the block, if the caller only\n               wishes to establish the presence of a containing storage\n               block.\n  \\return      ARM_DRIVER_OK if a containing storage-block is found. In this case,\n               if block is non-NULL, the buffer pointed to by it is populated with\n               the contents of the storage block, i.e. if block is valid and a block is\n               found, ARM_STORAGE_VALID_BLOCK(block) would return true following this\n               call. If there is no storage block containing the given offset, or in\n               case the driver is unable to resolve an address to a storage-block, an\n               error (negative) value is returned and an invalid StorageBlock is\n               populated into the supplied buffer.\n*/\n\n/**\n * Provides the typedef for the callback function \\ref ARM_Storage_Callback_t.\n */\ntypedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);\n\n/**\n * The set of operations constituting the Storage driver.\n */\ntypedef struct _ARM_DRIVER_STORAGE {\n  ARM_DRIVER_VERSION       (*GetVersion)     (void);                                           ///< Pointer to \\ref ARM_Storage_GetVersion : Get driver version.\n  ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);                                           ///< Pointer to \\ref ARM_Storage_GetCapabilities : Get driver capabilities.\n  int32_t                  (*Initialize)     (ARM_Storage_Callback_t callback);                ///< Pointer to \\ref ARM_Storage_Initialize : Initialize the Storage Interface.\n  int32_t                  (*Uninitialize)   (void);                                           ///< Pointer to \\ref ARM_Storage_Uninitialize : De-initialize the Storage Interface.\n  int32_t                  (*PowerControl)   (ARM_POWER_STATE state);                          ///< Pointer to \\ref ARM_Storage_PowerControl : Control the Storage interface power.\n  int32_t                  (*ReadData)       (uint64_t addr, void *data, uint32_t size);       ///< Pointer to \\ref ARM_Storage_ReadData : Read data from Storage.\n  int32_t                  (*ProgramData)    (uint64_t addr, const void *data, uint32_t size); ///< Pointer to \\ref ARM_Storage_ProgramData : Program data to Storage.\n  int32_t                  (*Erase)          (uint64_t addr, uint32_t size);                   ///< Pointer to \\ref ARM_Storage_Erase : Erase Storage range.\n  int32_t                  (*EraseAll)       (void);                                           ///< Pointer to \\ref ARM_Storage_EraseAll : Erase complete Storage.\n  ARM_STORAGE_STATUS       (*GetStatus)      (void);                                           ///< Pointer to \\ref ARM_Storage_GetStatus : Get Storage status.\n  int32_t                  (*GetInfo)        (ARM_STORAGE_INFO *info);                         ///< Pointer to \\ref ARM_Storage_GetInfo : Get Storage information.\n  uint32_t                 (*ResolveAddress) (uint64_t addr);                                  ///< Pointer to \\ref ARM_Storage_ResolveAddress : Resolve a storage address.\n  int32_t                  (*GetNextBlock)   (const ARM_STORAGE_BLOCK* prev, ARM_STORAGE_BLOCK *next); ///< Pointer to \\ref ARM_Storage_GetNextBlock : fetch successor for current block.\n  int32_t                  (*GetBlock)       (uint64_t addr, ARM_STORAGE_BLOCK *block);        ///< Pointer to \\ref ARM_Storage_GetBlock :\n} const ARM_DRIVER_STORAGE;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_STORAGE_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_USART.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        31. March 2020\n * $Revision:    V2.4\n *\n * Project:      USART (Universal Synchronous Asynchronous Receiver Transmitter)\n *               Driver definitions\n */\n\n/* History:\n *  Version 2.4\n *    Removed volatile from ARM_USART_STATUS and ARM_USART_MODEM_STATUS\n *  Version 2.3\n *    ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile\n *  Version 2.2\n *    Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions \n *  Version 2.1\n *    Removed optional argument parameter from Signal Event\n *  Version 2.0\n *    New simplified driver:\n *      complexity moved to upper layer (especially data handling)\n *      more unified API for different communication interfaces\n *      renamed driver UART -> USART (Asynchronous & Synchronous)\n *    Added modes:\n *      Synchronous\n *      Single-wire\n *      IrDA\n *      Smart Card  \n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.01\n *    Added events:\n *      ARM_UART_EVENT_TX_EMPTY,     ARM_UART_EVENT_RX_TIMEOUT\n *      ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD\n *    Added functions: SetTxThreshold, SetRxThreshold\n *    Added \"rx_timeout_event\" to capabilities\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_USART_H_\n#define DRIVER_USART_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4)  /* API version */\n\n\n#define _ARM_Driver_USART_(n)      Driver_USART##n\n#define  ARM_Driver_USART_(n) _ARM_Driver_USART_(n)\n\n\n/****** USART Control Codes *****/\n\n#define ARM_USART_CONTROL_Pos                0\n#define ARM_USART_CONTROL_Msk               (0xFFUL << ARM_USART_CONTROL_Pos)\n\n/*----- USART Control Codes: Mode -----*/\n#define ARM_USART_MODE_ASYNCHRONOUS         (0x01UL << ARM_USART_CONTROL_Pos)   ///< UART (Asynchronous); arg = Baudrate\n#define ARM_USART_MODE_SYNCHRONOUS_MASTER   (0x02UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Master (generates clock signal); arg = Baudrate\n#define ARM_USART_MODE_SYNCHRONOUS_SLAVE    (0x03UL << ARM_USART_CONTROL_Pos)   ///< Synchronous Slave (external clock signal)\n#define ARM_USART_MODE_SINGLE_WIRE          (0x04UL << ARM_USART_CONTROL_Pos)   ///< UART Single-wire (half-duplex); arg = Baudrate\n#define ARM_USART_MODE_IRDA                 (0x05UL << ARM_USART_CONTROL_Pos)   ///< UART IrDA; arg = Baudrate\n#define ARM_USART_MODE_SMART_CARD           (0x06UL << ARM_USART_CONTROL_Pos)   ///< UART Smart Card; arg = Baudrate\n\n/*----- USART Control Codes: Mode Parameters: Data Bits -----*/\n#define ARM_USART_DATA_BITS_Pos              8\n#define ARM_USART_DATA_BITS_Msk             (7UL << ARM_USART_DATA_BITS_Pos)\n#define ARM_USART_DATA_BITS_5               (5UL << ARM_USART_DATA_BITS_Pos)    ///< 5 Data bits\n#define ARM_USART_DATA_BITS_6               (6UL << ARM_USART_DATA_BITS_Pos)    ///< 6 Data bit\n#define ARM_USART_DATA_BITS_7               (7UL << ARM_USART_DATA_BITS_Pos)    ///< 7 Data bits\n#define ARM_USART_DATA_BITS_8               (0UL << ARM_USART_DATA_BITS_Pos)    ///< 8 Data bits (default)\n#define ARM_USART_DATA_BITS_9               (1UL << ARM_USART_DATA_BITS_Pos)    ///< 9 Data bits\n\n/*----- USART Control Codes: Mode Parameters: Parity -----*/\n#define ARM_USART_PARITY_Pos                 12\n#define ARM_USART_PARITY_Msk                (3UL << ARM_USART_PARITY_Pos)\n#define ARM_USART_PARITY_NONE               (0UL << ARM_USART_PARITY_Pos)       ///< No Parity (default)\n#define ARM_USART_PARITY_EVEN               (1UL << ARM_USART_PARITY_Pos)       ///< Even Parity\n#define ARM_USART_PARITY_ODD                (2UL << ARM_USART_PARITY_Pos)       ///< Odd Parity\n\n/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/\n#define ARM_USART_STOP_BITS_Pos              14\n#define ARM_USART_STOP_BITS_Msk             (3UL << ARM_USART_STOP_BITS_Pos)\n#define ARM_USART_STOP_BITS_1               (0UL << ARM_USART_STOP_BITS_Pos)    ///< 1 Stop bit (default)\n#define ARM_USART_STOP_BITS_2               (1UL << ARM_USART_STOP_BITS_Pos)    ///< 2 Stop bits\n#define ARM_USART_STOP_BITS_1_5             (2UL << ARM_USART_STOP_BITS_Pos)    ///< 1.5 Stop bits\n#define ARM_USART_STOP_BITS_0_5             (3UL << ARM_USART_STOP_BITS_Pos)    ///< 0.5 Stop bits\n\n/*----- USART Control Codes: Mode Parameters: Flow Control -----*/\n#define ARM_USART_FLOW_CONTROL_Pos           16\n#define ARM_USART_FLOW_CONTROL_Msk          (3UL << ARM_USART_FLOW_CONTROL_Pos)\n#define ARM_USART_FLOW_CONTROL_NONE         (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)\n#define ARM_USART_FLOW_CONTROL_RTS          (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control\n#define ARM_USART_FLOW_CONTROL_CTS          (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control\n#define ARM_USART_FLOW_CONTROL_RTS_CTS      (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control\n\n/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/\n#define ARM_USART_CPOL_Pos                   18\n#define ARM_USART_CPOL_Msk                  (1UL << ARM_USART_CPOL_Pos)\n#define ARM_USART_CPOL0                     (0UL << ARM_USART_CPOL_Pos)         ///< CPOL = 0 (default)\n#define ARM_USART_CPOL1                     (1UL << ARM_USART_CPOL_Pos)         ///< CPOL = 1\n\n/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/\n#define ARM_USART_CPHA_Pos                   19\n#define ARM_USART_CPHA_Msk                  (1UL << ARM_USART_CPHA_Pos)\n#define ARM_USART_CPHA0                     (0UL << ARM_USART_CPHA_Pos)         ///< CPHA = 0 (default)\n#define ARM_USART_CPHA1                     (1UL << ARM_USART_CPHA_Pos)         ///< CPHA = 1\n\n\n/*----- USART Control Codes: Miscellaneous Controls  -----*/\n#define ARM_USART_SET_DEFAULT_TX_VALUE      (0x10UL << ARM_USART_CONTROL_Pos)   ///< Set default Transmit value (Synchronous Receive only); arg = value\n#define ARM_USART_SET_IRDA_PULSE            (0x11UL << ARM_USART_CONTROL_Pos)   ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period  \n#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Guard Time; arg = number of bit periods\n#define ARM_USART_SET_SMART_CARD_CLOCK      (0x13UL << ARM_USART_CONTROL_Pos)   ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated\n#define ARM_USART_CONTROL_SMART_CARD_NACK   (0x14UL << ARM_USART_CONTROL_Pos)   ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled\n#define ARM_USART_CONTROL_TX                (0x15UL << ARM_USART_CONTROL_Pos)   ///< Transmitter; arg: 0=disabled, 1=enabled\n#define ARM_USART_CONTROL_RX                (0x16UL << ARM_USART_CONTROL_Pos)   ///< Receiver; arg: 0=disabled, 1=enabled\n#define ARM_USART_CONTROL_BREAK             (0x17UL << ARM_USART_CONTROL_Pos)   ///< Continuous Break transmission; arg: 0=disabled, 1=enabled\n#define ARM_USART_ABORT_SEND                (0x18UL << ARM_USART_CONTROL_Pos)   ///< Abort \\ref ARM_USART_Send\n#define ARM_USART_ABORT_RECEIVE             (0x19UL << ARM_USART_CONTROL_Pos)   ///< Abort \\ref ARM_USART_Receive\n#define ARM_USART_ABORT_TRANSFER            (0x1AUL << ARM_USART_CONTROL_Pos)   ///< Abort \\ref ARM_USART_Transfer\n\n\n\n/****** USART specific error codes *****/\n#define ARM_USART_ERROR_MODE                (ARM_DRIVER_ERROR_SPECIFIC - 1)     ///< Specified Mode not supported\n#define ARM_USART_ERROR_BAUDRATE            (ARM_DRIVER_ERROR_SPECIFIC - 2)     ///< Specified baudrate not supported\n#define ARM_USART_ERROR_DATA_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 3)     ///< Specified number of Data bits not supported\n#define ARM_USART_ERROR_PARITY              (ARM_DRIVER_ERROR_SPECIFIC - 4)     ///< Specified Parity not supported\n#define ARM_USART_ERROR_STOP_BITS           (ARM_DRIVER_ERROR_SPECIFIC - 5)     ///< Specified number of Stop bits not supported\n#define ARM_USART_ERROR_FLOW_CONTROL        (ARM_DRIVER_ERROR_SPECIFIC - 6)     ///< Specified Flow Control not supported\n#define ARM_USART_ERROR_CPOL                (ARM_DRIVER_ERROR_SPECIFIC - 7)     ///< Specified Clock Polarity not supported\n#define ARM_USART_ERROR_CPHA                (ARM_DRIVER_ERROR_SPECIFIC - 8)     ///< Specified Clock Phase not supported\n\n\n/**\n\\brief USART Status\n*/\ntypedef struct _ARM_USART_STATUS {\n  uint32_t tx_busy          : 1;        ///< Transmitter busy flag\n  uint32_t rx_busy          : 1;        ///< Receiver busy flag\n  uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)\n  uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)\n  uint32_t rx_break         : 1;        ///< Break detected on receive (cleared on start of next receive operation)\n  uint32_t rx_framing_error : 1;        ///< Framing error detected on receive (cleared on start of next receive operation)\n  uint32_t rx_parity_error  : 1;        ///< Parity error detected on receive (cleared on start of next receive operation)\n  uint32_t reserved         : 25;\n} ARM_USART_STATUS;\n\n/**\n\\brief USART Modem Control\n*/\ntypedef enum _ARM_USART_MODEM_CONTROL {\n  ARM_USART_RTS_CLEAR,                  ///< Deactivate RTS\n  ARM_USART_RTS_SET,                    ///< Activate RTS\n  ARM_USART_DTR_CLEAR,                  ///< Deactivate DTR\n  ARM_USART_DTR_SET                     ///< Activate DTR\n} ARM_USART_MODEM_CONTROL;\n\n/**\n\\brief USART Modem Status\n*/\ntypedef struct _ARM_USART_MODEM_STATUS {\n  uint32_t cts      : 1;                ///< CTS state: 1=Active, 0=Inactive\n  uint32_t dsr      : 1;                ///< DSR state: 1=Active, 0=Inactive\n  uint32_t dcd      : 1;                ///< DCD state: 1=Active, 0=Inactive\n  uint32_t ri       : 1;                ///< RI  state: 1=Active, 0=Inactive\n  uint32_t reserved : 28;\n} ARM_USART_MODEM_STATUS;\n\n\n/****** USART Event *****/\n#define ARM_USART_EVENT_SEND_COMPLETE       (1UL << 0)  ///< Send completed; however USART may still transmit data\n#define ARM_USART_EVENT_RECEIVE_COMPLETE    (1UL << 1)  ///< Receive completed\n#define ARM_USART_EVENT_TRANSFER_COMPLETE   (1UL << 2)  ///< Transfer completed\n#define ARM_USART_EVENT_TX_COMPLETE         (1UL << 3)  ///< Transmit completed (optional)\n#define ARM_USART_EVENT_TX_UNDERFLOW        (1UL << 4)  ///< Transmit data not available (Synchronous Slave)\n#define ARM_USART_EVENT_RX_OVERFLOW         (1UL << 5)  ///< Receive data overflow\n#define ARM_USART_EVENT_RX_TIMEOUT          (1UL << 6)  ///< Receive character timeout (optional)\n#define ARM_USART_EVENT_RX_BREAK            (1UL << 7)  ///< Break detected on receive\n#define ARM_USART_EVENT_RX_FRAMING_ERROR    (1UL << 8)  ///< Framing error detected on receive\n#define ARM_USART_EVENT_RX_PARITY_ERROR     (1UL << 9)  ///< Parity error detected on receive\n#define ARM_USART_EVENT_CTS                 (1UL << 10) ///< CTS state changed (optional)\n#define ARM_USART_EVENT_DSR                 (1UL << 11) ///< DSR state changed (optional)\n#define ARM_USART_EVENT_DCD                 (1UL << 12) ///< DCD state changed (optional)\n#define ARM_USART_EVENT_RI                  (1UL << 13) ///< RI  state changed (optional)\n\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_USART_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n\n  \\fn          ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)\n  \\brief       Get driver capabilities\n  \\return      \\ref ARM_USART_CAPABILITIES\n\n  \\fn          int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)\n  \\brief       Initialize USART Interface.\n  \\param[in]   cb_event  Pointer to \\ref ARM_USART_SignalEvent\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_USART_Uninitialize (void)\n  \\brief       De-initialize USART Interface.\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control USART Interface Power.\n  \\param[in]   state  Power state\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_USART_Send (const void *data, uint32_t num)\n  \\brief       Start sending data to USART transmitter.\n  \\param[in]   data  Pointer to buffer with data to send to USART transmitter\n  \\param[in]   num   Number of data items to send\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_USART_Receive (void *data, uint32_t num)\n  \\brief       Start receiving data from USART receiver.\n  \\param[out]  data  Pointer to buffer for data to receive from USART receiver\n  \\param[in]   num   Number of data items to receive\n  \\return      \\ref execution_status\n\n  \\fn          int32_t ARM_USART_Transfer (const void *data_out,\n                                                 void *data_in,\n                                           uint32_t    num)\n  \\brief       Start sending/receiving data to/from USART transmitter/receiver.\n  \\param[in]   data_out  Pointer to buffer with data to send to USART transmitter\n  \\param[out]  data_in   Pointer to buffer for data to receive from USART receiver\n  \\param[in]   num       Number of data items to transfer\n  \\return      \\ref execution_status\n\n  \\fn          uint32_t ARM_USART_GetTxCount (void)\n  \\brief       Get transmitted data count.\n  \\return      number of data items transmitted\n\n  \\fn          uint32_t ARM_USART_GetRxCount (void)\n  \\brief       Get received data count.\n  \\return      number of data items received\n\n  \\fn          int32_t ARM_USART_Control (uint32_t control, uint32_t arg)\n  \\brief       Control USART Interface.\n  \\param[in]   control  Operation\n  \\param[in]   arg      Argument of operation (optional)\n  \\return      common \\ref execution_status and driver specific \\ref usart_execution_status\n\n  \\fn          ARM_USART_STATUS ARM_USART_GetStatus (void)\n  \\brief       Get USART status.\n  \\return      USART status \\ref ARM_USART_STATUS\n\n  \\fn          int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)\n  \\brief       Set USART Modem Control line state.\n  \\param[in]   control  \\ref ARM_USART_MODEM_CONTROL\n  \\return      \\ref execution_status \n\n  \\fn          ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)\n  \\brief       Get USART Modem Status lines state.\n  \\return      modem status \\ref ARM_USART_MODEM_STATUS\n\n  \\fn          void ARM_USART_SignalEvent (uint32_t event)\n  \\brief       Signal USART Events.\n  \\param[in]   event  \\ref USART_events notification mask\n  \\return      none\n*/\n\ntypedef void (*ARM_USART_SignalEvent_t) (uint32_t event);  ///< Pointer to \\ref ARM_USART_SignalEvent : Signal USART Event.\n\n\n/**\n\\brief USART Device Driver Capabilities.\n*/\ntypedef struct _ARM_USART_CAPABILITIES {\n  uint32_t asynchronous       : 1;      ///< supports UART (Asynchronous) mode \n  uint32_t synchronous_master : 1;      ///< supports Synchronous Master mode\n  uint32_t synchronous_slave  : 1;      ///< supports Synchronous Slave mode\n  uint32_t single_wire        : 1;      ///< supports UART Single-wire mode\n  uint32_t irda               : 1;      ///< supports UART IrDA mode\n  uint32_t smart_card         : 1;      ///< supports UART Smart Card mode\n  uint32_t smart_card_clock   : 1;      ///< Smart Card Clock generator available\n  uint32_t flow_control_rts   : 1;      ///< RTS Flow Control available\n  uint32_t flow_control_cts   : 1;      ///< CTS Flow Control available\n  uint32_t event_tx_complete  : 1;      ///< Transmit completed event: \\ref ARM_USART_EVENT_TX_COMPLETE\n  uint32_t event_rx_timeout   : 1;      ///< Signal receive character timeout event: \\ref ARM_USART_EVENT_RX_TIMEOUT\n  uint32_t rts                : 1;      ///< RTS Line: 0=not available, 1=available\n  uint32_t cts                : 1;      ///< CTS Line: 0=not available, 1=available\n  uint32_t dtr                : 1;      ///< DTR Line: 0=not available, 1=available\n  uint32_t dsr                : 1;      ///< DSR Line: 0=not available, 1=available\n  uint32_t dcd                : 1;      ///< DCD Line: 0=not available, 1=available\n  uint32_t ri                 : 1;      ///< RI Line: 0=not available, 1=available\n  uint32_t event_cts          : 1;      ///< Signal CTS change event: \\ref ARM_USART_EVENT_CTS\n  uint32_t event_dsr          : 1;      ///< Signal DSR change event: \\ref ARM_USART_EVENT_DSR\n  uint32_t event_dcd          : 1;      ///< Signal DCD change event: \\ref ARM_USART_EVENT_DCD\n  uint32_t event_ri           : 1;      ///< Signal RI change event: \\ref ARM_USART_EVENT_RI\n  uint32_t reserved           : 11;     ///< Reserved (must be zero)\n} ARM_USART_CAPABILITIES;\n\n\n/**\n\\brief Access structure of the USART Driver.\n*/\ntypedef struct _ARM_DRIVER_USART {\n  ARM_DRIVER_VERSION     (*GetVersion)      (void);                              ///< Pointer to \\ref ARM_USART_GetVersion : Get driver version.\n  ARM_USART_CAPABILITIES (*GetCapabilities) (void);                              ///< Pointer to \\ref ARM_USART_GetCapabilities : Get driver capabilities.\n  int32_t                (*Initialize)      (ARM_USART_SignalEvent_t cb_event);  ///< Pointer to \\ref ARM_USART_Initialize : Initialize USART Interface.\n  int32_t                (*Uninitialize)    (void);                              ///< Pointer to \\ref ARM_USART_Uninitialize : De-initialize USART Interface.\n  int32_t                (*PowerControl)    (ARM_POWER_STATE state);             ///< Pointer to \\ref ARM_USART_PowerControl : Control USART Interface Power.\n  int32_t                (*Send)            (const void *data, uint32_t num);    ///< Pointer to \\ref ARM_USART_Send : Start sending data to USART transmitter.\n  int32_t                (*Receive)         (      void *data, uint32_t num);    ///< Pointer to \\ref ARM_USART_Receive : Start receiving data from USART receiver.\n  int32_t                (*Transfer)        (const void *data_out,\n                                                   void *data_in,\n                                             uint32_t    num);                   ///< Pointer to \\ref ARM_USART_Transfer : Start sending/receiving data to/from USART.\n  uint32_t               (*GetTxCount)      (void);                              ///< Pointer to \\ref ARM_USART_GetTxCount : Get transmitted data count.\n  uint32_t               (*GetRxCount)      (void);                              ///< Pointer to \\ref ARM_USART_GetRxCount : Get received data count.\n  int32_t                (*Control)         (uint32_t control, uint32_t arg);    ///< Pointer to \\ref ARM_USART_Control : Control USART Interface.\n  ARM_USART_STATUS       (*GetStatus)       (void);                              ///< Pointer to \\ref ARM_USART_GetStatus : Get USART status.\n  int32_t                (*SetModemControl) (ARM_USART_MODEM_CONTROL control);   ///< Pointer to \\ref ARM_USART_SetModemControl : Set USART Modem Control line state.\n  ARM_USART_MODEM_STATUS (*GetModemStatus)  (void);                              ///< Pointer to \\ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.\n} const ARM_DRIVER_USART;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_USART_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_USB.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        24. January 2020\n * $Revision:    V2.0\n *\n * Project:      USB Driver common definitions\n */\n\n/* History:\n *  Version 2.0\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.01\n *    Added PID Types\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_USB_H_\n#define DRIVER_USB_H_\n\n#include \"Driver_Common.h\"\n\n/* USB Role */\n#define ARM_USB_ROLE_NONE               (0U)\n#define ARM_USB_ROLE_HOST               (1U)\n#define ARM_USB_ROLE_DEVICE             (2U)\n\n/* USB Pins */\n#define ARM_USB_PIN_DP                  (1U << 0) ///< USB D+ pin\n#define ARM_USB_PIN_DM                  (1U << 1) ///< USB D- pin\n#define ARM_USB_PIN_VBUS                (1U << 2) ///< USB VBUS pin\n#define ARM_USB_PIN_OC                  (1U << 3) ///< USB OverCurrent pin\n#define ARM_USB_PIN_ID                  (1U << 4) ///< USB ID pin\n\n/* USB Speed */\n#define ARM_USB_SPEED_LOW               (0U)      ///< Low-speed USB\n#define ARM_USB_SPEED_FULL              (1U)      ///< Full-speed USB\n#define ARM_USB_SPEED_HIGH              (2U)      ///< High-speed USB\n\n/* USB PID Types */\n#define ARM_USB_PID_OUT                 (1U)\n#define ARM_USB_PID_IN                  (9U)\n#define ARM_USB_PID_SOF                 (5U)\n#define ARM_USB_PID_SETUP               (13U)\n#define ARM_USB_PID_DATA0               (3U)\n#define ARM_USB_PID_DATA1               (11U)\n#define ARM_USB_PID_DATA2               (7U)\n#define ARM_USB_PID_MDATA               (15U)\n#define ARM_USB_PID_ACK                 (2U)\n#define ARM_USB_PID_NAK                 (10U)\n#define ARM_USB_PID_STALL               (14U)\n#define ARM_USB_PID_NYET                (6U)\n#define ARM_USB_PID_PRE                 (12U)\n#define ARM_USB_PID_ERR                 (12U)\n#define ARM_USB_PID_SPLIT               (8U)\n#define ARM_USB_PID_PING                (4U)\n#define ARM_USB_PID_RESERVED            (0U)\n\n/* USB Endpoint Address (bEndpointAddress) */\n#define ARM_USB_ENDPOINT_NUMBER_MASK    (0x0FU)\n#define ARM_USB_ENDPOINT_DIRECTION_MASK (0x80U)\n\n/* USB Endpoint Type */\n#define ARM_USB_ENDPOINT_CONTROL        (0U)     ///< Control Endpoint\n#define ARM_USB_ENDPOINT_ISOCHRONOUS    (1U)     ///< Isochronous Endpoint\n#define ARM_USB_ENDPOINT_BULK           (2U)     ///< Bulk Endpoint\n#define ARM_USB_ENDPOINT_INTERRUPT      (3U)     ///< Interrupt Endpoint\n\n/* USB Endpoint Maximum Packet Size (wMaxPacketSize) */\n#define ARM_USB_ENDPOINT_MAX_PACKET_SIZE_MASK           (0x07FFU)\n#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_MASK   (0x1800U)\n#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_1      (0x0000U)\n#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_2      (0x0800U)\n#define ARM_USB_ENDPOINT_MICROFRAME_TRANSACTIONS_3      (0x1000U)\n\n#endif /* DRIVER_USB_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_USBD.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        31. March 2020\n * $Revision:    V2.3\n *\n * Project:      USB Device Driver definitions\n */\n\n/* History:\n *  Version 2.3\n *    Removed volatile from ARM_USBD_STATE\n *  Version 2.2\n *    ARM_USBD_STATE made volatile\n *  Version 2.1\n *    Added ARM_USBD_ReadSetupPacket function\n *  Version 2.0\n *    Removed ARM_USBD_DeviceConfigure function\n *    Removed ARM_USBD_SET_ADDRESS_STAGE parameter from ARM_USBD_DeviceSetAddress function\n *    Removed ARM_USBD_EndpointReadStart function\n *    Replaced ARM_USBD_EndpointRead and ARM_USBD_EndpointWrite functions with ARM_USBD_EndpointTransfer\n *    Added ARM_USBD_EndpointTransferGetResult function\n *    Renamed ARM_USBD_EndpointAbort function to ARM_USBD_EndpointTransferAbort\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *    Changed return values of some functions to int32_t\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_USBD_H_\n#define DRIVER_USBD_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_USB.h\"\n\n#define ARM_USBD_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */\n\n\n#define _ARM_Driver_USBD_(n)      Driver_USBD##n\n#define  ARM_Driver_USBD_(n) _ARM_Driver_USBD_(n)\n\n\n/**\n\\brief USB Device State\n*/\ntypedef struct _ARM_USBD_STATE {\n  uint32_t vbus     : 1;                ///< USB Device VBUS flag\n  uint32_t speed    : 2;                ///< USB Device speed setting (ARM_USB_SPEED_xxx)\n  uint32_t active   : 1;                ///< USB Device active flag\n  uint32_t reserved : 28;\n} ARM_USBD_STATE;\n\n\n/****** USB Device Event *****/\n#define ARM_USBD_EVENT_VBUS_ON          (1UL << 0)      ///< USB Device VBUS On\n#define ARM_USBD_EVENT_VBUS_OFF         (1UL << 1)      ///< USB Device VBUS Off\n#define ARM_USBD_EVENT_RESET            (1UL << 2)      ///< USB Reset occurred\n#define ARM_USBD_EVENT_HIGH_SPEED       (1UL << 3)      ///< USB switch to High Speed occurred\n#define ARM_USBD_EVENT_SUSPEND          (1UL << 4)      ///< USB Suspend occurred\n#define ARM_USBD_EVENT_RESUME           (1UL << 5)      ///< USB Resume occurred\n\n/****** USB Endpoint Event *****/\n#define ARM_USBD_EVENT_SETUP            (1UL << 0)      ///< SETUP Packet\n#define ARM_USBD_EVENT_OUT              (1UL << 1)      ///< OUT Packet(s)\n#define ARM_USBD_EVENT_IN               (1UL << 2)      ///< IN Packet(s)\n\n\n#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_USBD_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn          ARM_USBD_CAPABILITIES ARM_USBD_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_USBD_CAPABILITIES\n*/\n/**\n  \\fn          int32_t ARM_USBD_Initialize (ARM_USBD_SignalDeviceEvent_t   cb_device_event,\n                                            ARM_USBD_SignalEndpointEvent_t cb_endpoint_event)\n  \\brief       Initialize USB Device Interface.\n  \\param[in]   cb_device_event    Pointer to \\ref ARM_USBD_SignalDeviceEvent\n  \\param[in]   cb_endpoint_event  Pointer to \\ref ARM_USBD_SignalEndpointEvent\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_Uninitialize (void)\n  \\brief       De-initialize USB Device Interface.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control USB Device Interface Power.\n  \\param[in]   state  Power state\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_DeviceConnect (void)\n  \\brief       Connect USB Device.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_DeviceDisconnect (void)\n  \\brief       Disconnect USB Device.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          ARM_USBD_STATE ARM_USBD_DeviceGetState (void)\n  \\brief       Get current USB Device State.\n  \\return      Device State \\ref ARM_USBD_STATE\n*/\n/**\n  \\fn          int32_t ARM_USBD_DeviceRemoteWakeup (void)\n  \\brief       Trigger USB Remote Wakeup.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_DeviceSetAddress (uint8_t dev_addr)\n  \\brief       Set USB Device Address.\n  \\param[in]   dev_addr  Device Address\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_ReadSetupPacket (uint8_t *setup)\n  \\brief       Read setup packet received over Control Endpoint.\n  \\param[out]  setup  Pointer to buffer for setup packet\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_EndpointConfigure (uint8_t  ep_addr,\n                                                   uint8_t  ep_type,\n                                                   uint16_t ep_max_packet_size)\n  \\brief       Configure USB Endpoint.\n  \\param[in]   ep_addr  Endpoint Address\n                - ep_addr.0..3: Address\n                - ep_addr.7:    Direction\n  \\param[in]   ep_type  Endpoint Type (ARM_USB_ENDPOINT_xxx)\n  \\param[in]   ep_max_packet_size Endpoint Maximum Packet Size\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_EndpointUnconfigure (uint8_t ep_addr)\n  \\brief       Unconfigure USB Endpoint.\n  \\param[in]   ep_addr  Endpoint Address\n                - ep_addr.0..3: Address\n                - ep_addr.7:    Direction\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_EndpointStall (uint8_t ep_addr, bool stall)\n  \\brief       Set/Clear Stall for USB Endpoint.\n  \\param[in]   ep_addr  Endpoint Address\n                - ep_addr.0..3: Address\n                - ep_addr.7:    Direction\n  \\param[in]   stall  Operation\n                - \\b false Clear\n                - \\b true Set\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBD_EndpointTransfer (uint8_t ep_addr, uint8_t *data, uint32_t num)\n  \\brief       Read data from or Write data to USB Endpoint.\n  \\param[in]   ep_addr  Endpoint Address\n                - ep_addr.0..3: Address\n                - ep_addr.7:    Direction\n  \\param[out]  data Pointer to buffer for data to read or with data to write\n  \\param[in]   num  Number of data bytes to transfer\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          uint32_t ARM_USBD_EndpointTransferGetResult (uint8_t ep_addr)\n  \\brief       Get result of USB Endpoint transfer.\n  \\param[in]   ep_addr  Endpoint Address\n                - ep_addr.0..3: Address\n                - ep_addr.7:    Direction\n  \\return      number of successfully transferred data bytes\n*/\n/**\n  \\fn          int32_t ARM_USBD_EndpointTransferAbort (uint8_t ep_addr)\n  \\brief       Abort current USB Endpoint transfer.\n  \\param[in]   ep_addr  Endpoint Address\n                - ep_addr.0..3: Address\n                - ep_addr.7:    Direction\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          uint16_t ARM_USBD_GetFrameNumber (void)\n  \\brief       Get current USB Frame Number.\n  \\return      Frame Number\n*/\n\n/**\n  \\fn          void ARM_USBD_SignalDeviceEvent (uint32_t event)\n  \\brief       Signal USB Device Event.\n  \\param[in]   event \\ref USBD_dev_events\n  \\return      none\n*/\n/**\n  \\fn          void ARM_USBD_SignalEndpointEvent (uint8_t ep_addr, uint32_t event)\n  \\brief       Signal USB Endpoint Event.\n  \\param[in]   ep_addr  Endpoint Address\n                - ep_addr.0..3: Address\n                - ep_addr.7:    Direction\n  \\param[in]   event \\ref USBD_ep_events\n  \\return      none\n*/\n\ntypedef void (*ARM_USBD_SignalDeviceEvent_t)   (uint32_t event);                    ///< Pointer to \\ref ARM_USBD_SignalDeviceEvent : Signal USB Device Event.\ntypedef void (*ARM_USBD_SignalEndpointEvent_t) (uint8_t ep_addr, uint32_t event);   ///< Pointer to \\ref ARM_USBD_SignalEndpointEvent : Signal USB Endpoint Event.\n\n\n/**\n\\brief USB Device Driver Capabilities.\n*/\ntypedef struct _ARM_USBD_CAPABILITIES {\n  uint32_t vbus_detection  : 1;         ///< VBUS detection\n  uint32_t event_vbus_on   : 1;         ///< Signal VBUS On event\n  uint32_t event_vbus_off  : 1;         ///< Signal VBUS Off event\n  uint32_t reserved        : 29;        ///< Reserved (must be zero)\n} ARM_USBD_CAPABILITIES;\n\n\n/**\n\\brief Access structure of the USB Device Driver.\n*/\ntypedef struct _ARM_DRIVER_USBD {\n  ARM_DRIVER_VERSION    (*GetVersion)                (void);                                              ///< Pointer to \\ref ARM_USBD_GetVersion : Get driver version.\n  ARM_USBD_CAPABILITIES (*GetCapabilities)           (void);                                              ///< Pointer to \\ref ARM_USBD_GetCapabilities : Get driver capabilities.\n  int32_t               (*Initialize)                (ARM_USBD_SignalDeviceEvent_t   cb_device_event,                     \n                                                      ARM_USBD_SignalEndpointEvent_t cb_endpoint_event);  ///< Pointer to \\ref ARM_USBD_Initialize : Initialize USB Device Interface. \n  int32_t               (*Uninitialize)              (void);                                              ///< Pointer to \\ref ARM_USBD_Uninitialize : De-initialize USB Device Interface.\n  int32_t               (*PowerControl)              (ARM_POWER_STATE state);                             ///< Pointer to \\ref ARM_USBD_PowerControl : Control USB Device Interface Power.\n  int32_t               (*DeviceConnect)             (void);                                              ///< Pointer to \\ref ARM_USBD_DeviceConnect : Connect USB Device.\n  int32_t               (*DeviceDisconnect)          (void);                                              ///< Pointer to \\ref ARM_USBD_DeviceDisconnect : Disconnect USB Device.\n  ARM_USBD_STATE        (*DeviceGetState)            (void);                                              ///< Pointer to \\ref ARM_USBD_DeviceGetState : Get current USB Device State.\n  int32_t               (*DeviceRemoteWakeup)        (void);                                              ///< Pointer to \\ref ARM_USBD_DeviceRemoteWakeup : Trigger USB Remote Wakeup.\n  int32_t               (*DeviceSetAddress)          (uint8_t dev_addr);                                  ///< Pointer to \\ref ARM_USBD_DeviceSetAddress : Set USB Device Address.\n  int32_t               (*ReadSetupPacket)           (uint8_t *setup);                                    ///< Pointer to \\ref ARM_USBD_ReadSetupPacket : Read setup packet received over Control Endpoint.\n  int32_t               (*EndpointConfigure)         (uint8_t ep_addr,\n                                                      uint8_t ep_type,\n                                                      uint16_t ep_max_packet_size);                       ///< Pointer to \\ref ARM_USBD_EndpointConfigure : Configure USB Endpoint.\n  int32_t               (*EndpointUnconfigure)       (uint8_t ep_addr);                                   ///< Pointer to \\ref ARM_USBD_EndpointUnconfigure : Unconfigure USB Endpoint.\n  int32_t               (*EndpointStall)             (uint8_t ep_addr, bool stall);                       ///< Pointer to \\ref ARM_USBD_EndpointStall : Set/Clear Stall for USB Endpoint.\n  int32_t               (*EndpointTransfer)          (uint8_t ep_addr, uint8_t *data, uint32_t num);      ///< Pointer to \\ref ARM_USBD_EndpointTransfer : Read data from or Write data to USB Endpoint.\n  uint32_t              (*EndpointTransferGetResult) (uint8_t ep_addr);                                   ///< Pointer to \\ref ARM_USBD_EndpointTransferGetResult : Get result of USB Endpoint transfer.\n  int32_t               (*EndpointTransferAbort)     (uint8_t ep_addr);                                   ///< Pointer to \\ref ARM_USBD_EndpointTransferAbort : Abort current USB Endpoint transfer.\n  uint16_t              (*GetFrameNumber)            (void);                                              ///< Pointer to \\ref ARM_USBD_GetFrameNumber : Get current USB Frame Number.\n} const ARM_DRIVER_USBD;\n\n#endif /* __DOXYGEN_MW__ */\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_USBD_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_USBH.h",
    "content": "/*\n * Copyright (c) 2013-2020 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n  *\n * $Date:        31. March 2020\n * $Revision:    V2.3\n *\n * Project:      USB Host Driver definitions\n*/\n\n/* History:\n *  Version 2.3\n *    Removed volatile from ARM_USBH_PORT_STATE\n *  Version 2.2\n *    ARM_USBH_PORT_STATE made volatile\n *  Version 2.1\n *    Renamed structure ARM_USBH_EP_HANDLE to ARM_USBH_PIPE_HANDLE\n *    Renamed functions ARM_USBH_Endpoint... to ARM_USBH_Pipe...\n *    Renamed function ARM_USBH_SignalEndpointEvent to ARM_USBH_SignalPipeEvent\n *  Version 2.0\n *    Replaced function ARM_USBH_PortPowerOnOff with ARM_USBH_PortVbusOnOff\n *    Changed function ARM_USBH_EndpointCreate parameters\n *    Replaced function ARM_USBH_EndpointConfigure with ARM_USBH_EndpointModify\n *    Replaced function ARM_USBH_EndpointClearHalt with ARM_USBH_EndpointReset\n *    Replaced function ARM_USBH_URB_Submit with ARM_USBH_EndpointTransfer\n *    Replaced function ARM_USBH_URB_Abort with ARM_USBH_EndpointTransferAbort\n *    Added function ARM_USBH_EndpointTransferGetResult\n *    Added function ARM_USBH_GetFrameNumber\n *    Changed prefix ARM_DRV -> ARM_DRIVER\n *  Version 1.20\n *    Added API for OHCI/EHCI Host Controller Interface (HCI)\n *  Version 1.10\n *    Namespace prefix ARM_ added\n *  Version 1.00\n *    Initial release\n */\n\n#ifndef DRIVER_USBH_H_\n#define DRIVER_USBH_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_USB.h\"\n\n#define ARM_USBH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3)  /* API version */\n\n\n#define _ARM_Driver_USBH_(n)      Driver_USBH##n\n#define  ARM_Driver_USBH_(n) _ARM_Driver_USBH_(n)\n\n\n/**\n\\brief USB Host Port State\n*/\ntypedef struct _ARM_USBH_PORT_STATE {\n  uint32_t connected   : 1;             ///< USB Host Port connected flag\n  uint32_t overcurrent : 1;             ///< USB Host Port overcurrent flag\n  uint32_t speed       : 2;             ///< USB Host Port speed setting (ARM_USB_SPEED_xxx)\n  uint32_t reserved    : 28;\n} ARM_USBH_PORT_STATE;\n\n/**\n\\brief USB Host Pipe Handle\n*/\ntypedef uint32_t ARM_USBH_PIPE_HANDLE;\n#define ARM_USBH_EP_HANDLE ARM_USBH_PIPE_HANDLE  /* Legacy name */\n\n\n/****** USB Host Packet Information *****/\n#define ARM_USBH_PACKET_TOKEN_Pos         0\n#define ARM_USBH_PACKET_TOKEN_Msk        (0x0FUL << ARM_USBH_PACKET_TOKEN_Pos)\n#define ARM_USBH_PACKET_SETUP            (0x01UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< SETUP Packet\n#define ARM_USBH_PACKET_OUT              (0x02UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< OUT Packet\n#define ARM_USBH_PACKET_IN               (0x03UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< IN Packet\n#define ARM_USBH_PACKET_PING             (0x04UL << ARM_USBH_PACKET_TOKEN_Pos)  ///< PING Packet\n\n#define ARM_USBH_PACKET_DATA_Pos          4\n#define ARM_USBH_PACKET_DATA_Msk         (0x0FUL << ARM_USBH_PACKET_DATA_Pos)\n#define ARM_USBH_PACKET_DATA0            (0x01UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA0 PID\n#define ARM_USBH_PACKET_DATA1            (0x02UL << ARM_USBH_PACKET_DATA_Pos)   ///< DATA1 PID\n\n#define ARM_USBH_PACKET_SPLIT_Pos         8\n#define ARM_USBH_PACKET_SPLIT_Msk        (0x0FUL << ARM_USBH_PACKET_SPLIT_Pos)\n#define ARM_USBH_PACKET_SSPLIT           (0x08UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet\n#define ARM_USBH_PACKET_SSPLIT_S         (0x09UL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data Start\n#define ARM_USBH_PACKET_SSPLIT_E         (0x0AUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data End\n#define ARM_USBH_PACKET_SSPLIT_S_E       (0x0BUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< SSPLIT Packet: Data All\n#define ARM_USBH_PACKET_CSPLIT           (0x0CUL << ARM_USBH_PACKET_SPLIT_Pos)  ///< CSPLIT Packet\n\n#define ARM_USBH_PACKET_PRE              (1UL << 12)                            ///< PRE Token\n\n\n/****** USB Host Port Event *****/\n#define ARM_USBH_EVENT_CONNECT           (1UL << 0)     ///< USB Device Connected to Port\n#define ARM_USBH_EVENT_DISCONNECT        (1UL << 1)     ///< USB Device Disconnected from Port\n#define ARM_USBH_EVENT_OVERCURRENT       (1UL << 2)     ///< USB Device caused Overcurrent\n#define ARM_USBH_EVENT_RESET             (1UL << 3)     ///< USB Reset completed\n#define ARM_USBH_EVENT_SUSPEND           (1UL << 4)     ///< USB Suspend occurred\n#define ARM_USBH_EVENT_RESUME            (1UL << 5)     ///< USB Resume occurred\n#define ARM_USBH_EVENT_REMOTE_WAKEUP     (1UL << 6)     ///< USB Device activated Remote Wakeup\n\n/****** USB Host Pipe Event *****/\n#define ARM_USBH_EVENT_TRANSFER_COMPLETE (1UL << 0)     ///< Transfer completed\n#define ARM_USBH_EVENT_HANDSHAKE_NAK     (1UL << 1)     ///< NAK Handshake received\n#define ARM_USBH_EVENT_HANDSHAKE_NYET    (1UL << 2)     ///< NYET Handshake received\n#define ARM_USBH_EVENT_HANDSHAKE_MDATA   (1UL << 3)     ///< MDATA Handshake received\n#define ARM_USBH_EVENT_HANDSHAKE_STALL   (1UL << 4)     ///< STALL Handshake received\n#define ARM_USBH_EVENT_HANDSHAKE_ERR     (1UL << 5)     ///< ERR Handshake received\n#define ARM_USBH_EVENT_BUS_ERROR         (1UL << 6)     ///< Bus Error detected\n\n\n#ifndef __DOXYGEN_MW__                  // exclude from middleware documentation\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_USBH_GetVersion (void)\n  \\brief       Get driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn          ARM_USBH_CAPABILITIES ARM_USBH_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_USBH_CAPABILITIES\n*/\n/**\n  \\fn          int32_t ARM_USBH_Initialize (ARM_USBH_SignalPortEvent_t cb_port_event,\n                                            ARM_USBH_SignalPipeEvent_t cb_pipe_event)\n  \\brief       Initialize USB Host Interface.\n  \\param[in]   cb_port_event  Pointer to \\ref ARM_USBH_SignalPortEvent\n  \\param[in]   cb_pipe_event  Pointer to \\ref ARM_USBH_SignalPipeEvent\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_Uninitialize (void)\n  \\brief       De-initialize USB Host Interface.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control USB Host Interface Power.\n  \\param[in]   state  Power state\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_PortVbusOnOff (uint8_t port, bool vbus)\n  \\brief       Root HUB Port VBUS on/off.\n  \\param[in]   port  Root HUB Port Number\n  \\param[in]   vbus\n                - \\b false VBUS off\n                - \\b true  VBUS on\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_PortReset (uint8_t port)\n  \\brief       Do Root HUB Port Reset.\n  \\param[in]   port  Root HUB Port Number\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_PortSuspend (uint8_t port)\n  \\brief       Suspend Root HUB Port (stop generating SOFs).\n  \\param[in]   port  Root HUB Port Number\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_PortResume (uint8_t port)\n  \\brief       Resume Root HUB Port (start generating SOFs).\n  \\param[in]   port  Root HUB Port Number\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          ARM_USBH_PORT_STATE ARM_USBH_PortGetState (uint8_t port)\n  \\brief       Get current Root HUB Port State.\n  \\param[in]   port  Root HUB Port Number\n  \\return      Port State \\ref ARM_USBH_PORT_STATE\n*/\n/**\n  \\fn          ARM_USBH_PIPE_HANDLE ARM_USBH_PipeCreate (uint8_t  dev_addr,\n                                                         uint8_t  dev_speed,\n                                                         uint8_t  hub_addr,\n                                                         uint8_t  hub_port,\n                                                         uint8_t  ep_addr,\n                                                         uint8_t  ep_type,\n                                                         uint16_t ep_max_packet_size,\n                                                         uint8_t  ep_interval)\n  \\brief       Create Pipe in System.\n  \\param[in]   dev_addr   Device Address\n  \\param[in]   dev_speed  Device Speed\n  \\param[in]   hub_addr   Hub Address\n  \\param[in]   hub_port   Hub Port\n  \\param[in]   ep_addr    Endpoint Address\n                - ep_addr.0..3: Address\n                - ep_addr.7:    Direction\n  \\param[in]   ep_type    Endpoint Type (ARM_USB_ENDPOINT_xxx)\n  \\param[in]   ep_max_packet_size Endpoint Maximum Packet Size\n  \\param[in]   ep_interval        Endpoint Polling Interval\n  \\return      Pipe Handle \\ref ARM_USBH_PIPE_HANDLE\n*/\n/**\n  \\fn          int32_t ARM_USBH_PipeModify (ARM_USBH_PIPE_HANDLE pipe_hndl,\n                                            uint8_t              dev_addr,\n                                            uint8_t              dev_speed,\n                                            uint8_t              hub_addr,\n                                            uint8_t              hub_port,\n                                            uint16_t             ep_max_packet_size)\n  \\brief       Modify Pipe in System.\n  \\param[in]   pipe_hndl  Pipe Handle\n  \\param[in]   dev_addr   Device Address\n  \\param[in]   dev_speed  Device Speed\n  \\param[in]   hub_addr   Hub Address\n  \\param[in]   hub_port   Hub Port\n  \\param[in]   ep_max_packet_size Endpoint Maximum Packet Size\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_PipeDelete (ARM_USBH_PIPE_HANDLE pipe_hndl)\n  \\brief       Delete Pipe from System.\n  \\param[in]   pipe_hndl  Pipe Handle\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_PipeReset (ARM_USBH_PIPE_HANDLE pipe_hndl)\n  \\brief       Reset Pipe.\n  \\param[in]   pipe_hndl  Pipe Handle\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_PipeTransfer (ARM_USBH_PIPE_HANDLE pipe_hndl,\n                                              uint32_t             packet,\n                                              uint8_t             *data,\n                                              uint32_t             num)\n  \\brief       Transfer packets through USB Pipe.\n  \\param[in]   pipe_hndl  Pipe Handle\n  \\param[in]   packet     Packet information\n  \\param[in]   data       Pointer to buffer with data to send or for data to receive\n  \\param[in]   num        Number of data bytes to transfer\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          uint32_t ARM_USBH_PipeTransferGetResult (ARM_USBH_PIPE_HANDLE pipe_hndl)\n  \\brief       Get result of USB Pipe transfer.\n  \\param[in]   pipe_hndl  Pipe Handle\n  \\return      number of successfully transferred data bytes\n*/\n/**\n  \\fn          int32_t ARM_USBH_PipeTransferAbort (ARM_USBH_PIPE_HANDLE pipe_hndl)\n  \\brief       Abort current USB Pipe transfer.\n  \\param[in]   pipe_hndl  Pipe Handle\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          uint16_t ARM_USBH_GetFrameNumber (void)\n  \\brief       Get current USB Frame Number.\n  \\return      Frame Number\n*/\n\n/**\n  \\fn          void ARM_USBH_SignalPortEvent (uint8_t port, uint32_t event)\n  \\brief       Signal Root HUB Port Event.\n  \\param[in]   port  Root HUB Port Number\n  \\param[in]   event \\ref USBH_port_events\n  \\return      none\n*/\n/**\n  \\fn          void ARM_USBH_SignalPipeEvent (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event)\n  \\brief       Signal Pipe Event.\n  \\param[in]   pipe_hndl  Pipe Handle\n  \\param[in]   event  \\ref USBH_pipe_events\n  \\return      none\n*/\n\ntypedef void (*ARM_USBH_SignalPortEvent_t) (uint8_t port, uint32_t event);                    ///< Pointer to \\ref ARM_USBH_SignalPortEvent : Signal Root HUB Port Event.\ntypedef void (*ARM_USBH_SignalPipeEvent_t) (ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event);  ///< Pointer to \\ref ARM_USBH_SignalPipeEvent : Signal Pipe Event.\n#define ARM_USBH_SignalEndpointEvent_t ARM_USBH_SignalPipeEvent_t  /* Legacy name */\n\n\n/**\n\\brief USB Host Driver Capabilities.\n*/\ntypedef struct _ARM_USBH_CAPABILITIES {\n  uint32_t port_mask          : 15;     ///< Root HUB available Ports Mask\n  uint32_t auto_split         :  1;     ///< Automatic SPLIT packet handling\n  uint32_t event_connect      :  1;     ///< Signal Connect event\n  uint32_t event_disconnect   :  1;     ///< Signal Disconnect event\n  uint32_t event_overcurrent  :  1;     ///< Signal Overcurrent event\n  uint32_t reserved           : 13;     ///< Reserved (must be zero)\n} ARM_USBH_CAPABILITIES;\n\n\n/**\n\\brief Access structure of USB Host Driver.\n*/\ntypedef struct _ARM_DRIVER_USBH {\n  ARM_DRIVER_VERSION    (*GetVersion)            (void);                                     ///< Pointer to \\ref ARM_USBH_GetVersion : Get driver version.\n  ARM_USBH_CAPABILITIES (*GetCapabilities)       (void);                                     ///< Pointer to \\ref ARM_USBH_GetCapabilities : Get driver capabilities.\n  int32_t               (*Initialize)            (ARM_USBH_SignalPortEvent_t cb_port_event,            \n                                                  ARM_USBH_SignalPipeEvent_t cb_pipe_event); ///< Pointer to \\ref ARM_USBH_Initialize : Initialize USB Host Interface.\n  int32_t               (*Uninitialize)          (void);                                     ///< Pointer to \\ref ARM_USBH_Uninitialize : De-initialize USB Host Interface.\n  int32_t               (*PowerControl)          (ARM_POWER_STATE state);                    ///< Pointer to \\ref ARM_USBH_PowerControl : Control USB Host Interface Power.\n  int32_t               (*PortVbusOnOff)         (uint8_t port, bool vbus);                  ///< Pointer to \\ref ARM_USBH_PortVbusOnOff : Root HUB Port VBUS on/off.\n  int32_t               (*PortReset)             (uint8_t port);                             ///< Pointer to \\ref ARM_USBH_PortReset : Do Root HUB Port Reset.\n  int32_t               (*PortSuspend)           (uint8_t port);                             ///< Pointer to \\ref ARM_USBH_PortSuspend : Suspend Root HUB Port (stop generating SOFs).\n  int32_t               (*PortResume)            (uint8_t port);                             ///< Pointer to \\ref ARM_USBH_PortResume : Resume Root HUB Port (start generating SOFs).\n  ARM_USBH_PORT_STATE   (*PortGetState)          (uint8_t port);                             ///< Pointer to \\ref ARM_USBH_PortGetState : Get current Root HUB Port State.\n  ARM_USBH_PIPE_HANDLE  (*PipeCreate)            (uint8_t dev_addr,\n                                                  uint8_t dev_speed,\n                                                  uint8_t hub_addr,\n                                                  uint8_t hub_port,\n                                                  uint8_t ep_addr,\n                                                  uint8_t ep_type,\n                                                  uint16_t ep_max_packet_size,\n                                                  uint8_t ep_interval);                      ///< Pointer to \\ref ARM_USBH_PipeCreate : Create Pipe in System.\n  int32_t               (*PipeModify)            (ARM_USBH_PIPE_HANDLE pipe_hndl,\n                                                  uint8_t dev_addr,\n                                                  uint8_t dev_speed,\n                                                  uint8_t hub_addr,\n                                                  uint8_t hub_port,\n                                                  uint16_t ep_max_packet_size);              ///< Pointer to \\ref ARM_USBH_PipeModify : Modify Pipe in System.\n  int32_t               (*PipeDelete)            (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \\ref ARM_USBH_PipeDelete : Delete Pipe from System.\n  int32_t               (*PipeReset)             (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \\ref ARM_USBH_PipeReset : Reset Pipe.\n  int32_t               (*PipeTransfer)          (ARM_USBH_PIPE_HANDLE pipe_hndl, \n                                                  uint32_t packet,\n                                                  uint8_t *data,\n                                                  uint32_t num);                             ///< Pointer to \\ref ARM_USBH_PipeTransfer : Transfer packets through USB Pipe.\n  uint32_t              (*PipeTransferGetResult) (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \\ref ARM_USBH_PipeTransferGetResult : Get result of USB Pipe transfer.\n  int32_t               (*PipeTransferAbort)     (ARM_USBH_PIPE_HANDLE pipe_hndl);           ///< Pointer to \\ref ARM_USBH_PipeTransferAbort : Abort current USB Pipe transfer.\n  uint16_t              (*GetFrameNumber)        (void);                                     ///< Pointer to \\ref ARM_USBH_GetFrameNumber : Get current USB Frame Number.                    \n} const ARM_DRIVER_USBH;\n\n\n// HCI (OHCI/EHCI)\n\n// Function documentation\n/**\n  \\fn          ARM_DRIVER_VERSION ARM_USBH_HCI_GetVersion (void)\n  \\brief       Get USB Host HCI (OHCI/EHCI) driver version.\n  \\return      \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn          ARM_USBH_HCI_CAPABILITIES ARM_USBH_HCI_GetCapabilities (void)\n  \\brief       Get driver capabilities.\n  \\return      \\ref ARM_USBH_HCI_CAPABILITIES\n*/\n/**\n  \\fn          int32_t ARM_USBH_HCI_Initialize (ARM_USBH_HCI_Interrupt_t *cb_interrupt)\n  \\brief       Initialize USB Host HCI (OHCI/EHCI) Interface.\n  \\param[in]   cb_interrupt Pointer to Interrupt Handler Routine\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_HCI_Uninitialize (void)\n  \\brief       De-initialize USB Host HCI (OHCI/EHCI) Interface.\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_HCI_PowerControl (ARM_POWER_STATE state)\n  \\brief       Control USB Host HCI (OHCI/EHCI) Interface Power.\n  \\param[in]   state Power state\n  \\return      \\ref execution_status\n*/\n/**\n  \\fn          int32_t ARM_USBH_HCI_PortVbusOnOff (uint8_t port, bool vbus)\n  \\brief       USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.\n  \\param[in]   port  Root HUB Port Number\n  \\param[in]   vbus\n                - \\b false VBUS off\n                - \\b true  VBUS on\n  \\return      \\ref execution_status\n*/\n\n/**\n  \\fn          void ARM_USBH_HCI_Interrupt (void)\n  \\brief       USB Host HCI Interrupt Handler.\n  \\return      none\n*/\n\ntypedef void (*ARM_USBH_HCI_Interrupt_t) (void);  ///< Pointer to Interrupt Handler Routine.\n\n\n/**\n\\brief USB Host HCI (OHCI/EHCI) Driver Capabilities.\n*/\ntypedef struct _ARM_USBH_HCI_CAPABILITIES {\n  uint32_t port_mask : 15;              ///< Root HUB available Ports Mask\n  uint32_t reserved  : 17;              ///< Reserved (must be zero)\n} ARM_USBH_HCI_CAPABILITIES;\n\n\n/**\n  \\brief Access structure of USB Host HCI (OHCI/EHCI) Driver.\n*/\ntypedef struct _ARM_DRIVER_USBH_HCI {\n  ARM_DRIVER_VERSION        (*GetVersion)      (void);                                  ///< Pointer to \\ref ARM_USBH_HCI_GetVersion : Get USB Host HCI (OHCI/EHCI) driver version.\n  ARM_USBH_HCI_CAPABILITIES (*GetCapabilities) (void);                                  ///< Pointer to \\ref ARM_USBH_HCI_GetCapabilities : Get driver capabilities.\n  int32_t                   (*Initialize)      (ARM_USBH_HCI_Interrupt_t cb_interrupt); ///< Pointer to \\ref ARM_USBH_HCI_Initialize : Initialize USB Host HCI (OHCI/EHCI) Interface.\n  int32_t                   (*Uninitialize)    (void);                                  ///< Pointer to \\ref ARM_USBH_HCI_Uninitialize : De-initialize USB Host HCI (OHCI/EHCI) Interface.\n  int32_t                   (*PowerControl)    (ARM_POWER_STATE state);                 ///< Pointer to \\ref ARM_USBH_HCI_PowerControl : Control USB Host HCI (OHCI/EHCI) Interface Power.\n  int32_t                   (*PortVbusOnOff)   (uint8_t port, bool vbus);               ///< Pointer to \\ref ARM_USBH_HCI_PortVbusOnOff : USB Host HCI (OHCI/EHCI) Root HUB Port VBUS on/off.\n} const ARM_DRIVER_USBH_HCI;\n\n#endif /* __DOXYGEN_MW__ */\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_USBH_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/Include/Driver_WiFi.h",
    "content": "/*\n * Copyright (c) 2019-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * $Date:        30. March 2022\n * $Revision:    V1.1\n *\n * Project:      WiFi (Wireless Fidelity Interface) Driver definitions\n */\n\n/* History:\n *  Version 1.1\n *    Extended Socket Receive/RecvFrom/Send/SendTo (support for polling)\n *  Version 1.0\n *    Initial release\n */\n\n#ifndef DRIVER_WIFI_H_\n#define DRIVER_WIFI_H_\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"Driver_Common.h\"\n\n#define ARM_WIFI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,1)  /* API version */\n\n\n#define _ARM_Driver_WiFi_(n)      Driver_WiFi##n\n#define  ARM_Driver_WiFi_(n) _ARM_Driver_WiFi_(n)\n\n\n/****** WiFi SetOption/GetOption Function Option Codes *****/\n#define ARM_WIFI_BSSID                      1U          ///< Station/AP Set/Get BSSID of AP to connect or of AP;        data = &bssid,    len =  6, uint8_t[6]\n#define ARM_WIFI_TX_POWER                   2U          ///< Station/AP Set/Get transmit power;                         data = &power,    len =  4, uint32_t: 0 .. 20 [dBm]\n#define ARM_WIFI_LP_TIMER                   3U          ///< Station    Set/Get low-power deep-sleep time;              data = &time,     len =  4, uint32_t [seconds]: 0 = disable (default)\n#define ARM_WIFI_DTIM                       4U          ///< Station/AP Set/Get DTIM interval;                          data = &dtim,     len =  4, uint32_t [beacons]\n#define ARM_WIFI_BEACON                     5U          ///<         AP Set/Get beacon interval;                        data = &interval, len =  4, uint32_t [ms]\n#define ARM_WIFI_MAC                        6U          ///< Station/AP Set/Get MAC;                                    data = &mac,      len =  6, uint8_t[6]\n#define ARM_WIFI_IP                         7U          ///< Station/AP Set/Get IPv4 static/assigned address;           data = &ip,       len =  4, uint8_t[4]\n#define ARM_WIFI_IP_SUBNET_MASK             8U          ///< Station/AP Set/Get IPv4 subnet mask;                       data = &mask,     len =  4, uint8_t[4]\n#define ARM_WIFI_IP_GATEWAY                 9U          ///< Station/AP Set/Get IPv4 gateway address;                   data = &ip,       len =  4, uint8_t[4]\n#define ARM_WIFI_IP_DNS1                    10U         ///< Station/AP Set/Get IPv4 primary   DNS address;             data = &ip,       len =  4, uint8_t[4]\n#define ARM_WIFI_IP_DNS2                    11U         ///< Station/AP Set/Get IPv4 secondary DNS address;             data = &ip,       len =  4, uint8_t[4]\n#define ARM_WIFI_IP_DHCP                    12U         ///< Station/AP Set/Get IPv4 DHCP client/server enable/disable; data = &dhcp,     len =  4, uint32_t: 0 = disable, non-zero = enable (default)\n#define ARM_WIFI_IP_DHCP_POOL_BEGIN         13U         ///<         AP Set/Get IPv4 DHCP pool begin address;           data = &ip,       len =  4, uint8_t[4]\n#define ARM_WIFI_IP_DHCP_POOL_END           14U         ///<         AP Set/Get IPv4 DHCP pool end address;             data = &ip,       len =  4, uint8_t[4]\n#define ARM_WIFI_IP_DHCP_LEASE_TIME         15U         ///<         AP Set/Get IPv4 DHCP lease time;                   data = &time,     len =  4, uint32_t [seconds]\n#define ARM_WIFI_IP6_GLOBAL                 16U         ///< Station/AP Set/Get IPv6 global address;                    data = &ip6,      len = 16, uint8_t[16]\n#define ARM_WIFI_IP6_LINK_LOCAL             17U         ///< Station/AP Set/Get IPv6 link local address;                data = &ip6,      len = 16, uint8_t[16]\n#define ARM_WIFI_IP6_SUBNET_PREFIX_LEN      18U         ///< Station/AP Set/Get IPv6 subnet prefix length;              data = &len,      len =  4, uint32_t: 1 .. 127\n#define ARM_WIFI_IP6_GATEWAY                19U         ///< Station/AP Set/Get IPv6 gateway address;                   data = &ip6,      len = 16, uint8_t[16]\n#define ARM_WIFI_IP6_DNS1                   20U         ///< Station/AP Set/Get IPv6 primary   DNS address;             data = &ip6,      len = 16, uint8_t[16]\n#define ARM_WIFI_IP6_DNS2                   21U         ///< Station/AP Set/Get IPv6 secondary DNS address;             data = &ip6,      len = 16, uint8_t[16]\n#define ARM_WIFI_IP6_DHCP_MODE              22U         ///< Station/AP Set/Get IPv6 DHCPv6 client mode;                data = &mode,     len =  4, uint32_t: ARM_WIFI_IP6_DHCP_xxx (default Off)\n\n/****** WiFi Security Type *****/\n#define ARM_WIFI_SECURITY_OPEN              0U          ///< Open\n#define ARM_WIFI_SECURITY_WEP               1U          ///< Wired Equivalent Privacy (WEP) with Pre-Sheared Key (PSK)\n#define ARM_WIFI_SECURITY_WPA               2U          ///< WiFi Protected Access (WPA) with PSK\n#define ARM_WIFI_SECURITY_WPA2              3U          ///< WiFi Protected Access II (WPA2) with PSK\n#define ARM_WIFI_SECURITY_UNKNOWN           255U        ///< Unknown\n\n/****** WiFi Protected Setup (WPS) Method *****/\n#define ARM_WIFI_WPS_METHOD_NONE            0U          ///< Not used\n#define ARM_WIFI_WPS_METHOD_PBC             1U          ///< Push Button Configuration\n#define ARM_WIFI_WPS_METHOD_PIN             2U          ///< PIN\n\n/****** WiFi IPv6 Dynamic Host Configuration Protocol (DHCP) Mode *****/\n#define ARM_WIFI_IP6_DHCP_OFF               0U          ///< Static Host Configuration (default)\n#define ARM_WIFI_IP6_DHCP_STATELESS         1U          ///< Dynamic Host Configuration stateless DHCPv6\n#define ARM_WIFI_IP6_DHCP_STATEFULL         2U          ///< Dynamic Host Configuration statefull DHCPv6\n\n/****** WiFi Event *****/\n#define ARM_WIFI_EVENT_AP_CONNECT          (1UL << 0)   ///< Access Point: Station has connected;           arg = &mac, mac (uint8_t[6])\n#define ARM_WIFI_EVENT_AP_DISCONNECT       (1UL << 1)   ///< Access Point: Station has disconnected;        arg = &mac, mac (uint8_t[6])\n#define ARM_WIFI_EVENT_ETH_RX_FRAME        (1UL << 4)   ///< Ethernet Frame Received (in bypass mode only); arg = interface (0 = Station, 1 = Access Point)\n\n\n/**\n\\brief WiFi Configuration\n*/\ntypedef struct ARM_WIFI_CONFIG_s {\n  const char   *ssid;                                   ///< Pointer to Service Set Identifier (SSID) null-terminated string\n  const char   *pass;                                   ///< Pointer to Password null-terminated string\n        uint8_t security;                               ///< Security type (ARM_WIFI_SECURITY_xxx)\n        uint8_t ch;                                     ///< WiFi Channel (0 = auto, otherwise = exact channel)\n        uint8_t reserved;                               ///< Reserved\n        uint8_t wps_method;                             ///< WiFi Protected Setup (WPS) method (ARM_WIFI_WPS_METHOD_xxx)\n  const char   *wps_pin;                                ///< Pointer to WiFi Protected Setup (WPS) PIN null-terminated string\n} ARM_WIFI_CONFIG_t;\n\n/**\n\\brief WiFi Scan Information\n*/\ntypedef struct ARM_WIFI_SCAN_INFO_s {\n  char    ssid[32+1];                                   ///< Service Set Identifier (SSID) null-terminated string\n  uint8_t bssid[6];                                     ///< Basic Service Set Identifier (BSSID)\n  uint8_t security;                                     ///< Security type (ARM_WIFI_SECURITY_xxx)\n  uint8_t ch;                                           ///< WiFi Channel\n  uint8_t rssi;                                         ///< Received Signal Strength Indicator\n} ARM_WIFI_SCAN_INFO_t;\n\n/**\n\\brief WiFi Network Information\n*/\ntypedef struct ARM_WIFI_NET_INFO_s {\n  char    ssid[32+1];                                   ///< Service Set Identifier (SSID) null-terminated string\n  char    pass[64+1];                                   ///< Password null-terminated string\n  uint8_t security;                                     ///< Security type (ARM_WIFI_SECURITY_xxx)\n  uint8_t ch;                                           ///< WiFi Channel\n  uint8_t rssi;                                         ///< Received Signal Strength Indicator\n} ARM_WIFI_NET_INFO_t;\n\n/****** Socket Address Family definitions *****/\n#define ARM_SOCKET_AF_INET                  1           ///< IPv4\n#define ARM_SOCKET_AF_INET6                 2           ///< IPv6\n\n/****** Socket Type definitions *****/\n#define ARM_SOCKET_SOCK_STREAM              1           ///< Stream socket\n#define ARM_SOCKET_SOCK_DGRAM               2           ///< Datagram socket\n\n/****** Socket Protocol definitions *****/\n#define ARM_SOCKET_IPPROTO_TCP              1           ///< TCP\n#define ARM_SOCKET_IPPROTO_UDP              2           ///< UDP\n\n/****** Socket Option definitions *****/\n#define ARM_SOCKET_IO_FIONBIO               1           ///< Non-blocking I/O (Set only, default = 0); opt_val = &nbio, opt_len = sizeof(nbio), nbio (integer): 0=blocking, non-blocking otherwise\n#define ARM_SOCKET_SO_RCVTIMEO              2           ///< Receive timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout)\n#define ARM_SOCKET_SO_SNDTIMEO              3           ///< Send timeout in ms (default = 0); opt_val = &timeout, opt_len = sizeof(timeout)\n#define ARM_SOCKET_SO_KEEPALIVE             4           ///< Keep-alive messages (default = 0); opt_val = &keepalive, opt_len = sizeof(keepalive), keepalive (integer): 0=disabled, enabled otherwise\n#define ARM_SOCKET_SO_TYPE                  5           ///< Socket Type (Get only); opt_val = &socket_type, opt_len = sizeof(socket_type), socket_type (integer): ARM_SOCKET_SOCK_xxx\n\n/****** Socket Function return codes *****/\n#define ARM_SOCKET_ERROR                   (-1)         ///< Unspecified error\n#define ARM_SOCKET_ESOCK                   (-2)         ///< Invalid socket\n#define ARM_SOCKET_EINVAL                  (-3)         ///< Invalid argument\n#define ARM_SOCKET_ENOTSUP                 (-4)         ///< Operation not supported\n#define ARM_SOCKET_ENOMEM                  (-5)         ///< Not enough memory\n#define ARM_SOCKET_EAGAIN                  (-6)         ///< Operation would block or timed out\n#define ARM_SOCKET_EINPROGRESS             (-7)         ///< Operation in progress\n#define ARM_SOCKET_ETIMEDOUT               (-8)         ///< Operation timed out\n#define ARM_SOCKET_EISCONN                 (-9)         ///< Socket is connected\n#define ARM_SOCKET_ENOTCONN                (-10)        ///< Socket is not connected\n#define ARM_SOCKET_ECONNREFUSED            (-11)        ///< Connection rejected by the peer\n#define ARM_SOCKET_ECONNRESET              (-12)        ///< Connection reset by the peer\n#define ARM_SOCKET_ECONNABORTED            (-13)        ///< Connection aborted locally\n#define ARM_SOCKET_EALREADY                (-14)        ///< Connection already in progress\n#define ARM_SOCKET_EADDRINUSE              (-15)        ///< Address in use\n#define ARM_SOCKET_EHOSTNOTFOUND           (-16)        ///< Host not found\n\n\n// Function documentation\n/**\n  \\fn            ARM_DRIVER_VERSION ARM_WIFI_GetVersion (void)\n  \\brief         Get driver version.\n  \\return        \\ref ARM_DRIVER_VERSION\n*/\n/**\n  \\fn            ARM_WIFI_CAPABILITIES ARM_WIFI_GetCapabilities (void)\n  \\brief         Get driver capabilities.\n  \\return        \\ref ARM_WIFI_CAPABILITIES\n*/\n/**\n  \\fn            int32_t ARM_WIFI_Initialize (ARM_WIFI_SignalEvent_t cb_event)\n  \\brief         Initialize WiFi Module.\n  \\param[in]     cb_event Pointer to \\ref ARM_WIFI_SignalEvent_t\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n*/\n/**\n  \\fn            int32_t ARM_WIFI_Uninitialize (void)\n  \\brief         De-initialize WiFi Module.\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n*/\n/**\n  \\fn            int32_t ARM_WIFI_PowerControl (ARM_POWER_STATE state)\n  \\brief         Control WiFi Module Power.\n  \\param[in]     state     Power state\n                   - \\ref ARM_POWER_OFF                : Power off: no operation possible\n                   - \\ref ARM_POWER_LOW                : Low-power mode: sleep or deep-sleep depending on \\ref ARM_WIFI_LP_TIMER option set\n                   - \\ref ARM_POWER_FULL               : Power on: full operation at maximum performance\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid state)\n*/\n/**\n  \\fn            int32_t ARM_WIFI_GetModuleInfo (char *module_info, uint32_t max_len)\n  \\brief         Get Module information.\n  \\param[out]    module_info Pointer to character buffer were info string will be returned\n  \\param[in]     max_len     Maximum length of string to return (including null terminator)\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL module_info pointer or max_len equals to 0)\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SetOption (uint32_t interface, uint32_t option, const void *data, uint32_t len)\n  \\brief         Set WiFi Module Options.\n  \\param[in]     interface Interface (0 = Station, 1 = Access Point)\n  \\param[in]     option    Option to set\n  \\param[in]     data      Pointer to data relevant to selected option\n  \\param[in]     len       Length of data (in bytes)\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL data pointer or len less than option specifies)\n*/\n/**\n  \\fn            int32_t ARM_WIFI_GetOption (uint32_t interface, uint32_t option, void *data, uint32_t *len)\n  \\brief         Get WiFi Module Options.\n  \\param[in]     interface Interface (0 = Station, 1 = Access Point)\n  \\param[in]     option    Option to get\n  \\param[out]    data      Pointer to memory where data for selected option will be returned\n  \\param[in,out] len       Pointer to length of data (input/output)\n                   - input: maximum length of data that can be returned (in bytes)\n                   - output: length of returned data (in bytes)\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL data or len pointer, or *len less than option specifies)\n*/\n/**\n  \\fn            int32_t ARM_WIFI_Scan (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num)\n  \\brief         Scan for available networks in range.\n  \\param[out]    scan_info Pointer to array of ARM_WIFI_SCAN_INFO_t structures where available Scan Information will be returned\n  \\param[in]     max_num   Maximum number of Network Information structures to return\n  \\return        number of ARM_WIFI_SCAN_INFO_t structures returned or error code\n                   - value >= 0                        : Number of ARM_WIFI_SCAN_INFO_t structures returned\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL scan_info pointer or max_num equal to 0)\n*/\n/**\n  \\fn            int32_t ARM_WIFI_Activate (uint32_t interface, const ARM_WIFI_CONFIG_t *config)\n  \\brief         Activate interface (Connect to a wireless network or activate an access point).\n  \\param[in]     interface Interface (0 = Station, 1 = Access Point)\n  \\param[in]     config    Pointer to ARM_WIFI_CONFIG_t structure where Configuration parameters are located\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_TIMEOUT     : Timeout occurred\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported (security type, channel autodetect or WPS not supported)\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface, NULL config pointer or invalid configuration)\n*/\n/**\n  \\fn            int32_t ARM_WIFI_Deactivate (uint32_t interface)\n  \\brief         Deactivate interface (Disconnect from a wireless network or deactivate an access point).\n  \\param[in]     interface Interface (0 = Station, 1 = Access Point)\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface)\n*/\n/**\n  \\fn            uint32_t ARM_WIFI_IsConnected (void)\n  \\brief         Get station connection status.\n  \\return        station connection status\n                   - value != 0: Station connected\n                   - value = 0: Station not connected\n*/\n/**\n  \\fn            int32_t ARM_WIFI_GetNetInfo (ARM_WIFI_NET_INFO_t *net_info)\n  \\brief         Get station Network Information.\n  \\param[out]    net_info  Pointer to ARM_WIFI_NET_INFO_t structure where station Network Information will be returned\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed (station not connected)\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL net_info pointer)\n*/\n/**\n  \\fn            int32_t ARM_WIFI_BypassControl (uint32_t interface, uint32_t mode)\n  \\brief         Enable or disable bypass (pass-through) mode. Transmit and receive Ethernet frames (IP layer bypassed and WiFi/Ethernet translation).\n  \\param[in]     interface Interface (0 = Station, 1 = Access Point)\n  \\param[in]     mode\n                   - value = 1: all packets bypass internal IP stack\n                   - value = 0: all packets processed by internal IP stack\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or mode)\n*/\n/**\n  \\fn            int32_t ARM_WIFI_EthSendFrame (uint32_t interface, const uint8_t *frame, uint32_t len)\n  \\brief         Send Ethernet frame (in bypass mode only).\n  \\param[in]     interface Interface (0 = Station, 1 = Access Point)\n  \\param[in]     frame    Pointer to frame buffer with data to send\n  \\param[in]     len      Frame buffer length in bytes\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_BUSY        : Driver is busy\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL frame pointer)\n*/\n/**\n  \\fn            int32_t ARM_WIFI_EthReadFrame (uint32_t interface, uint8_t *frame, uint32_t len)\n  \\brief         Read data of received Ethernet frame (in bypass mode only).\n  \\param[in]     interface Interface (0 = Station, 1 = Access Point)\n  \\param[in]     frame    Pointer to frame buffer for data to read into\n  \\param[in]     len      Frame buffer length in bytes\n  \\return        number of data bytes read or error code\n                   - value >= 0                        : Number of data bytes read\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (invalid interface or NULL frame pointer)\n*/\n/**\n  \\fn            uint32_t ARM_WIFI_EthGetRxFrameSize (uint32_t interface)\n  \\brief         Get size of received Ethernet frame (in bypass mode only).\n  \\param[in]     interface Interface (0 = Station, 1 = Access Point)\n  \\return        number of bytes in received frame\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketCreate (int32_t af, int32_t type, int32_t protocol)\n  \\brief         Create a communication socket.\n  \\param[in]     af       Address family\n  \\param[in]     type     Socket type\n  \\param[in]     protocol Socket protocol\n  \\return        status information\n                   - Socket identification number (>=0)\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument\n                   - \\ref ARM_SOCKET_ENOTSUP           : Operation not supported\n                   - \\ref ARM_SOCKET_ENOMEM            : Not enough memory\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketBind (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)\n  \\brief         Assign a local address to a socket.\n  \\param[in]     socket   Socket identification number\n  \\param[in]     ip       Pointer to local IP address\n  \\param[in]     ip_len   Length of 'ip' address in bytes\n  \\param[in]     port     Local port number\n  \\return        status information\n                   - 0                                 : Operation successful\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument (address or socket already bound)\n                   - \\ref ARM_SOCKET_EADDRINUSE        : Address already in use\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketListen (int32_t socket, int32_t backlog)\n  \\brief         Listen for socket connections.\n  \\param[in]     socket   Socket identification number\n  \\param[in]     backlog  Number of connection requests that can be queued\n  \\return        status information\n                   - 0                                 : Operation successful\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument (socket not bound)\n                   - \\ref ARM_SOCKET_ENOTSUP           : Operation not supported\n                   - \\ref ARM_SOCKET_EISCONN           : Socket is already connected\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketAccept (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)\n  \\brief         Accept a new connection on a socket.\n  \\param[in]     socket   Socket identification number\n  \\param[out]    ip       Pointer to buffer where address of connecting socket shall be returned (NULL for none)\n  \\param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)\n                   - length of supplied 'ip' on input\n                   - length of stored 'ip' on output\n  \\param[out]    port     Pointer to buffer where port of connecting socket shall be returned (NULL for none)\n  \\return        status information\n                   - socket identification number of accepted socket (>=0)\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument (socket not in listen mode)\n                   - \\ref ARM_SOCKET_ENOTSUP           : Operation not supported (socket type does not support accepting connections)\n                   - \\ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer\n                   - \\ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally\n                   - \\ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketConnect (int32_t socket, const uint8_t *ip, uint32_t ip_len, uint16_t port)\n  \\brief         Connect a socket to a remote host.\n  \\param[in]     socket   Socket identification number\n  \\param[in]     ip       Pointer to remote IP address\n  \\param[in]     ip_len   Length of 'ip' address in bytes\n  \\param[in]     port     Remote port number\n  \\return        status information\n                   - 0                                 : Operation successful\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument\n                   - \\ref ARM_SOCKET_EALREADY          : Connection already in progress\n                   - \\ref ARM_SOCKET_EINPROGRESS       : Operation in progress\n                   - \\ref ARM_SOCKET_EISCONN           : Socket is connected\n                   - \\ref ARM_SOCKET_ECONNREFUSED      : Connection rejected by the peer\n                   - \\ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally\n                   - \\ref ARM_SOCKET_EADDRINUSE        : Address already in use\n                   - \\ref ARM_SOCKET_ETIMEDOUT         : Operation timed out\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketRecv (int32_t socket, void *buf, uint32_t len)\n  \\brief         Receive data or check if data is available on a connected socket.\n  \\param[in]     socket   Socket identification number\n  \\param[out]    buf      Pointer to buffer where data should be stored\n  \\param[in]     len      Length of buffer (in bytes), set len = 0 to check if data is available\n  \\return        status information\n                   - number of bytes received (>=0), if len != 0\n                   - 0                                 : Data is available (len = 0)\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)\n                   - \\ref ARM_SOCKET_ENOTCONN          : Socket is not connected\n                   - \\ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer\n                   - \\ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally\n                   - \\ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketRecvFrom (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port)\n  \\brief         Receive data or check if data is available on a socket.\n  \\param[in]     socket   Socket identification number\n  \\param[out]    buf      Pointer to buffer where data should be stored\n  \\param[in]     len      Length of buffer (in bytes), set len = 0 to check if data is available\n  \\param[out]    ip       Pointer to buffer where remote source address shall be returned (NULL for none)\n  \\param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)\n                   - length of supplied 'ip' on input\n                   - length of stored 'ip' on output\n  \\param[out]    port     Pointer to buffer where remote source port shall be returned (NULL for none)\n  \\return        status information\n                   - number of bytes received (>=0), if len != 0\n                   - 0                                 : Data is available (len = 0)\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)\n                   - \\ref ARM_SOCKET_ENOTCONN          : Socket is not connected\n                   - \\ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer\n                   - \\ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally\n                   - \\ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketSend (int32_t socket, const void *buf, uint32_t len)\n  \\brief         Send data or check if data can be sent on a connected socket.\n  \\param[in]     socket   Socket identification number\n  \\param[in]     buf      Pointer to buffer containing data to send\n  \\param[in]     len      Length of data (in bytes), set len = 0 to check if data can be sent\n  \\return        status information\n                   - number of bytes sent (>=0), if len != 0\n                   - 0                                 : Data can be sent (len = 0)\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)\n                   - \\ref ARM_SOCKET_ENOTCONN          : Socket is not connected\n                   - \\ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer\n                   - \\ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally\n                   - \\ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketSendTo (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port)\n  \\brief         Send data or check if data can be sent on a socket.\n  \\param[in]     socket   Socket identification number\n  \\param[in]     buf      Pointer to buffer containing data to send\n  \\param[in]     len      Length of data (in bytes), set len = 0 to check if data can be sent\n  \\param[in]     ip       Pointer to remote destination IP address\n  \\param[in]     ip_len   Length of 'ip' address in bytes\n  \\param[in]     port     Remote destination port number\n  \\return        status information\n                   - number of bytes sent (>=0), if len != 0\n                   - 0                                 : Data can be sent (len = 0)\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)\n                   - \\ref ARM_SOCKET_ENOTCONN          : Socket is not connected\n                   - \\ref ARM_SOCKET_ECONNRESET        : Connection reset by the peer\n                   - \\ref ARM_SOCKET_ECONNABORTED      : Connection aborted locally\n                   - \\ref ARM_SOCKET_EAGAIN            : Operation would block or timed out (may be called again)\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketGetSockName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)\n  \\brief         Retrieve local IP address and port of a socket.\n  \\param[in]     socket   Socket identification number\n  \\param[out]    ip       Pointer to buffer where local address shall be returned (NULL for none)\n  \\param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)\n                   - length of supplied 'ip' on input\n                   - length of stored 'ip' on output\n  \\param[out]    port     Pointer to buffer where local port shall be returned (NULL for none)\n  \\return        status information\n                   - 0                                 : Operation successful\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketGetPeerName (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port)\n  \\brief         Retrieve remote IP address and port of a socket.\n  \\param[in]     socket   Socket identification number\n  \\param[out]    ip       Pointer to buffer where remote address shall be returned (NULL for none)\n  \\param[in,out] ip_len   Pointer to length of 'ip' (or NULL if 'ip' is NULL)\n                   - length of supplied 'ip' on input\n                   - length of stored 'ip' on output\n  \\param[out]    port     Pointer to buffer where remote port shall be returned (NULL for none)\n  \\return        status information\n                   - 0                                 : Operation successful\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument (pointer to buffer or length)\n                   - \\ref ARM_SOCKET_ENOTCONN          : Socket is not connected\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketGetOpt (int32_t socket, int32_t opt_id, void *opt_val, uint32_t *opt_len)\n  \\brief         Get socket option.\n  \\param[in]     socket   Socket identification number\n  \\param[in]     opt_id   Option identifier\n  \\param[out]    opt_val  Pointer to the buffer that will receive the option value\n  \\param[in,out] opt_len  Pointer to length of the option value\n                   - length of buffer on input\n                   - length of data on output\n  \\return        status information\n                   - 0                                 : Operation successful\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument\n                   - \\ref ARM_SOCKET_ENOTSUP           : Operation not supported\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketSetOpt (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t opt_len)\n  \\brief         Set socket option.\n  \\param[in]     socket   Socket identification number\n  \\param[in]     opt_id   Option identifier\n  \\param[in]     opt_val  Pointer to the option value\n  \\param[in]     opt_len  Length of the option value in bytes\n  \\return        status information\n                   - 0                                 : Operation successful\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument\n                   - \\ref ARM_SOCKET_ENOTSUP           : Operation not supported\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketClose (int32_t socket)\n  \\brief         Close and release a socket.\n  \\param[in]     socket   Socket identification number\n  \\return        status information\n                   - 0                                 : Operation successful\n                   - \\ref ARM_SOCKET_ESOCK             : Invalid socket\n                   - \\ref ARM_SOCKET_EAGAIN            : Operation would block (may be called again)\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_SocketGetHostByName (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len)\n  \\brief         Retrieve host IP address from host name.\n  \\param[in]     name     Host name\n  \\param[in]     af       Address family\n  \\param[out]    ip       Pointer to buffer where resolved IP address shall be returned\n  \\param[in,out] ip_len   Pointer to length of 'ip'\n                   - length of supplied 'ip' on input\n                   - length of stored 'ip' on output\n  \\return        status information\n                   - 0                                 : Operation successful\n                   - \\ref ARM_SOCKET_EINVAL            : Invalid argument\n                   - \\ref ARM_SOCKET_ENOTSUP           : Operation not supported\n                   - \\ref ARM_SOCKET_ETIMEDOUT         : Operation timed out\n                   - \\ref ARM_SOCKET_EHOSTNOTFOUND     : Host not found\n                   - \\ref ARM_SOCKET_ERROR             : Unspecified error\n*/\n/**\n  \\fn            int32_t ARM_WIFI_Ping (const uint8_t *ip, uint32_t ip_len)\n  \\brief         Probe remote host with Ping command.\n  \\param[in]     ip       Pointer to remote host IP address\n  \\param[in]     ip_len   Length of 'ip' address in bytes\n  \\return        execution status\n                   - \\ref ARM_DRIVER_OK                : Operation successful\n                   - \\ref ARM_DRIVER_ERROR             : Operation failed\n                   - \\ref ARM_DRIVER_ERROR_TIMEOUT     : Timeout occurred\n                   - \\ref ARM_DRIVER_ERROR_UNSUPPORTED : Operation not supported\n                   - \\ref ARM_DRIVER_ERROR_PARAMETER   : Parameter error (NULL ip pointer or ip_len different than 4 or 16)\n*/\n/**\n  \\fn            void ARM_WIFI_SignalEvent (uint32_t event, void *arg)\n  \\brief         Signal WiFi Events.\n  \\param[in]     event    \\ref wifi_event notification mask\n  \\param[in]     arg      Pointer to argument of signaled event\n  \\return        none\n*/\n\ntypedef void (*ARM_WIFI_SignalEvent_t) (uint32_t event, void *arg); ///< Pointer to \\ref ARM_WIFI_SignalEvent : Signal WiFi Event.\n\n\n/**\n\\brief WiFi Driver Capabilities.\n*/\ntypedef struct _ARM_WIFI_CAPABILITIES {\n  uint32_t station               : 1;   ///< Station\n  uint32_t ap                    : 1;   ///< Access Point\n  uint32_t station_ap            : 1;   ///< Concurrent Station and Access Point\n  uint32_t wps_station           : 1;   ///< WiFi Protected Setup (WPS) for Station\n  uint32_t wps_ap                : 1;   ///< WiFi Protected Setup (WPS) for Access Point\n  uint32_t event_ap_connect      : 1;   ///< Access Point: event generated on Station connect\n  uint32_t event_ap_disconnect   : 1;   ///< Access Point: event generated on Station disconnect\n  uint32_t event_eth_rx_frame    : 1;   ///< Event generated on Ethernet frame reception in bypass mode\n  uint32_t bypass_mode           : 1;   ///< Bypass or pass-through mode (Ethernet interface)\n  uint32_t ip                    : 1;   ///< IP (UDP/TCP) (Socket interface)\n  uint32_t ip6                   : 1;   ///< IPv6 (Socket interface)\n  uint32_t ping                  : 1;   ///< Ping (ICMP)\n  uint32_t reserved              : 20;  ///< Reserved (must be zero)\n} ARM_WIFI_CAPABILITIES;\n\n/**\n\\brief Access structure of the WiFi Driver.\n*/\ntypedef struct _ARM_DRIVER_WIFI {\n  ARM_DRIVER_VERSION    (*GetVersion)                  (void);\n  ARM_WIFI_CAPABILITIES (*GetCapabilities)             (void);\n  int32_t               (*Initialize)                  (ARM_WIFI_SignalEvent_t cb_event);\n  int32_t               (*Uninitialize)                (void);\n  int32_t               (*PowerControl)                (ARM_POWER_STATE state);\n  int32_t               (*GetModuleInfo)               (char *module_info, uint32_t max_len);\n  int32_t               (*SetOption)                   (uint32_t interface, uint32_t option, const void *data, uint32_t  len);\n  int32_t               (*GetOption)                   (uint32_t interface, uint32_t option,       void *data, uint32_t *len);\n  int32_t               (*Scan)                        (ARM_WIFI_SCAN_INFO_t scan_info[], uint32_t max_num);\n  int32_t               (*Activate)                    (uint32_t interface, const ARM_WIFI_CONFIG_t *config);\n  int32_t               (*Deactivate)                  (uint32_t interface);\n  uint32_t              (*IsConnected)                 (void);\n  int32_t               (*GetNetInfo)                  (ARM_WIFI_NET_INFO_t *net_info);\n  int32_t               (*BypassControl)               (uint32_t interface, uint32_t mode);\n  int32_t               (*EthSendFrame)                (uint32_t interface, const uint8_t *frame, uint32_t len);\n  int32_t               (*EthReadFrame)                (uint32_t interface,       uint8_t *frame, uint32_t len);\n  uint32_t              (*EthGetRxFrameSize)           (uint32_t interface);\n  int32_t               (*SocketCreate)                (int32_t af, int32_t type, int32_t protocol);\n  int32_t               (*SocketBind)                  (int32_t socket, const uint8_t *ip, uint32_t  ip_len, uint16_t  port);\n  int32_t               (*SocketListen)                (int32_t socket, int32_t backlog);\n  int32_t               (*SocketAccept)                (int32_t socket,       uint8_t *ip, uint32_t *ip_len, uint16_t *port);\n  int32_t               (*SocketConnect)               (int32_t socket, const uint8_t *ip, uint32_t  ip_len, uint16_t  port);\n  int32_t               (*SocketRecv)                  (int32_t socket, void *buf, uint32_t len);\n  int32_t               (*SocketRecvFrom)              (int32_t socket, void *buf, uint32_t len, uint8_t *ip, uint32_t *ip_len, uint16_t *port);\n  int32_t               (*SocketSend)                  (int32_t socket, const void *buf, uint32_t len);\n  int32_t               (*SocketSendTo)                (int32_t socket, const void *buf, uint32_t len, const uint8_t *ip, uint32_t ip_len, uint16_t port);\n  int32_t               (*SocketGetSockName)           (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port);\n  int32_t               (*SocketGetPeerName)           (int32_t socket, uint8_t *ip, uint32_t *ip_len, uint16_t *port);\n  int32_t               (*SocketGetOpt)                (int32_t socket, int32_t opt_id,       void *opt_val, uint32_t *opt_len);\n  int32_t               (*SocketSetOpt)                (int32_t socket, int32_t opt_id, const void *opt_val, uint32_t  opt_len);\n  int32_t               (*SocketClose)                 (int32_t socket);\n  int32_t               (*SocketGetHostByName)         (const char *name, int32_t af, uint8_t *ip, uint32_t *ip_len);\n  int32_t               (*Ping)                        (const uint8_t *ip, uint32_t ip_len);\n} const ARM_DRIVER_WIFI;\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* DRIVER_WIFI_H_ */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/VIO/Include/cmsis_vio.h",
    "content": "/******************************************************************************\n * @file     cmsis_vio.h\n * @brief    CMSIS Virtual I/O header file\n * @version  V0.1.0\n * @date     23. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2019-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_VIO_H\n#define __CMSIS_VIO_H\n\n#include <stdint.h>\n\n/*******************************************************************************\n * Generic I/O mapping recommended for CMSIS-VIO\n * Note: not every I/O must be physically available\n */\n \n// vioSetSignal: mask values \n#define vioLED0             (1U << 0)   ///< \\ref vioSetSignal \\a mask parameter: LED 0 (for 3-color: red)\n#define vioLED1             (1U << 1)   ///< \\ref vioSetSignal \\a mask parameter: LED 1 (for 3-color: green)\n#define vioLED2             (1U << 2)   ///< \\ref vioSetSignal \\a mask parameter: LED 2 (for 3-color: blue)\n#define vioLED3             (1U << 3)   ///< \\ref vioSetSignal \\a mask parameter: LED 3\n#define vioLED4             (1U << 4)   ///< \\ref vioSetSignal \\a mask parameter: LED 4\n#define vioLED5             (1U << 5)   ///< \\ref vioSetSignal \\a mask parameter: LED 5\n#define vioLED6             (1U << 6)   ///< \\ref vioSetSignal \\a mask parameter: LED 6\n#define vioLED7             (1U << 7)   ///< \\ref vioSetSignal \\a mask parameter: LED 7\n\n// vioSetSignal: signal values\n#define vioLEDon            (0xFFU)     ///< \\ref vioSetSignal \\a signal parameter: pattern to turn any LED on\n#define vioLEDoff           (0x00U)     ///< \\ref vioSetSignal \\a signal parameter: pattern to turn any LED off\n\n// vioGetSignal: mask values and return values\n#define vioBUTTON0          (1U << 0)   ///< \\ref vioGetSignal \\a mask parameter: Push button 0\n#define vioBUTTON1          (1U << 1)   ///< \\ref vioGetSignal \\a mask parameter: Push button 1\n#define vioBUTTON2          (1U << 2)   ///< \\ref vioGetSignal \\a mask parameter: Push button 2\n#define vioBUTTON3          (1U << 3)   ///< \\ref vioGetSignal \\a mask parameter: Push button 3\n#define vioJOYup            (1U << 4)   ///< \\ref vioGetSignal \\a mask parameter: Joystick button: up\n#define vioJOYdown          (1U << 5)   ///< \\ref vioGetSignal \\a mask parameter: Joystick button: down\n#define vioJOYleft          (1U << 6)   ///< \\ref vioGetSignal \\a mask parameter: Joystick button: left\n#define vioJOYright         (1U << 7)   ///< \\ref vioGetSignal \\a mask parameter: Joystick button: right\n#define vioJOYselect        (1U << 8)   ///< \\ref vioGetSignal \\a mask parameter: Joystick button: select\n#define vioJOYall           (vioJOYup    | \\\n                             vioJOYdown  | \\\n                             vioJOYleft  | \\\n                             vioJOYright | \\\n                             vioJOYselect)  ///< \\ref vioGetSignal \\a mask Joystick button: all\n\n// vioSetValue / vioGetValue: id values\n#define vioAIN0             (0U)        ///< \\ref vioSetValue / \\ref vioGetValue \\a id parameter: Analog input value 0\n#define vioAIN1             (1U)        ///< \\ref vioSetValue / \\ref vioGetValue \\a id parameter: Analog input value 1\n#define vioAIN2             (2U)        ///< \\ref vioSetValue / \\ref vioGetValue \\a id parameter: Analog input value 2\n#define vioAIN3             (3U)        ///< \\ref vioSetValue / \\ref vioGetValue \\a id parameter: Analog input value 3\n#define vioAOUT0            (3U)        ///< \\ref vioSetValue / \\ref vioGetValue \\a id parameter: Analog output value 0\n\n// vioSetXYZ / vioGetXZY: id values\n#define vioMotionGyro       (0U)        ///< \\ref vioSetXYZ / \\ref vioGetXYZ \\a id parameter: for Gyroscope\n#define vioMotionAccelero   (1U)        ///< \\ref vioSetXYZ / \\ref vioGetXYZ \\a id parameter: for Accelerometer\n#define vioMotionMagneto    (2U)        ///< \\ref vioSetXYZ / \\ref vioGetXYZ \\a id parameter: for Magnetometer\n\n// vioPrint: levels\n#define vioLevelNone        (0U)        ///< \\ref vioPrint \\a level parameter: None\n#define vioLevelHeading     (1U)        ///< \\ref vioPrint \\a level parameter: Heading\n#define vioLevelMessage     (2U)        ///< \\ref vioPrint \\a level parameter: Message\n#define vioLevelError       (3U)        ///< \\ref vioPrint \\a level parameter: Error\n\n/// 3-D vector value\ntypedef struct {\n  int32_t   X;                          ///< X coordinate\n  int32_t   Y;                          ///< Y coordinate\n  int32_t   Z;                          ///< Z coordinate\n} vioValueXYZ_t;\n\n/// IPv4 Internet Address\ntypedef struct {\n  uint8_t   addr[4];                    ///< IPv4 address value used in \\ref vioSetIPv4 / \\ref vioGetIPv4 \n} vioAddrIPv4_t;\n\n/// IPv6 Internet Address\ntypedef struct {\n  uint8_t   addr[16];                   ///< IPv6 address value used in \\ref vioSetIPv6 / \\ref vioGetIPv6\n} vioAddrIPv6_t;\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n/// Initialize test input, output.\n/// \\return none.\nvoid vioInit (void);\n\n/// Print formated string to test terminal.\n/// \\param[in]     level        level (vioLevel...).\n/// \\param[in]     format       formated string to print.\n/// \\param[in]     ...          optional arguments (depending on format string).\n/// \\return number of characters written or -1 in case of error.\nint32_t vioPrint (uint32_t level, const char *format, ...);\n\n/// Set signal output.\n/// \\param[in]     mask         bit mask of signals to set.\n/// \\param[in]     signal       signal value to set.\n/// \\return none.\nvoid vioSetSignal (uint32_t mask, uint32_t signal);\n\n/// Get signal input.\n/// \\param[in]     mask         bit mask of signals to read.\n/// \\return signal value.\nuint32_t vioGetSignal (uint32_t mask);\n\n/// Set value output.\n/// \\param[in]     id           output identifier.\n/// \\param[in]     value        value to set.\n/// \\return none.\nvoid vioSetValue (uint32_t id, int32_t value);\n\n/// Get value input.\n/// \\param[in]     id           input identifier.\n/// \\return  value retrieved from input.\nint32_t vioGetValue (uint32_t id);\n\n/// Set XYZ value output.\n/// \\param[in]     id           output identifier.\n/// \\param[in]     valueXYZ     XYZ data to set.\n/// \\return none.\nvoid vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ);\n\n/// Get XYZ value input.\n/// \\param[in]     id           input identifier.\n/// \\return  XYZ data retrieved from XYZ peripheral.\nvioValueXYZ_t vioGetXYZ (uint32_t id);\n\n/// Set IPv4 address output.\n/// \\param[in]     id           output identifier.\n/// \\param[in]     addrIPv4     pointer to IPv4 address.\n/// \\return none.\nvoid vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4);\n\n/// Get IPv4 address input.\n/// \\param[in]     id           input identifier.\n/// \\return IPv4 address retrieved from peripheral.\nvioAddrIPv4_t vioGetIPv4 (uint32_t id);\n\n/// Set IPv6 address output.\n/// \\param[in]     id           output identifier.\n/// \\param[in]     addrIPv6     pointer to IPv6 address.\n/// \\return none.\nvoid vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6);\n\n/// Get IPv6 address from peripheral.\n/// \\param[in]     id           input identifier.\n/// \\return IPv6 address retrieved from peripheral.\nvioAddrIPv6_t vioGetIPv6 (uint32_t id);\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif /* __CMSIS_VIO_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/VIO/Source/vio.c",
    "content": "/******************************************************************************\n * @file     vio.c\n * @brief    Virtual I/O implementation template\n * @version  V1.0.0\n * @date     23. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2019-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <stdio.h>\n#include <string.h>\n#include <stdarg.h>\n#include \"cmsis_vio.h\"\n\n#include \"RTE_Components.h\"             // Component selection\n#include CMSIS_device_header\n\n#if !defined CMSIS_VOUT || !defined CMSIS_VIN\n// Add user includes here:\n\n#endif\n\n// VIO input, output definitions\n#define VIO_PRINT_MAX_SIZE      64U     // maximum size of print memory\n#define VIO_PRINTMEM_NUM         4U     // number of print memories\n#define VIO_VALUE_NUM            3U     // number of values\n#define VIO_VALUEXYZ_NUM         3U     // number of XYZ values\n#define VIO_IPV4_ADDRESS_NUM     2U     // number of IPv4 addresses\n#define VIO_IPV6_ADDRESS_NUM     2U     // number of IPv6 addresses\n\n// VIO input, output variables\n__USED uint32_t      vioSignalIn;                                       // Memory for incoming signal\n__USED uint32_t      vioSignalOut;                                      // Memory for outgoing signal\n__USED char          vioPrintMem[VIO_PRINTMEM_NUM][VIO_PRINT_MAX_SIZE]; // Memory for the last value for each level\n__USED int32_t       vioValue   [VIO_VALUE_NUM];                        // Memory for value used in vioGetValue/vioSetValue\n__USED vioValueXYZ_t vioValueXYZ[VIO_VALUEXYZ_NUM];                     // Memory for XYZ value for 3-D vector\n__USED vioAddrIPv4_t vioAddrIPv4[VIO_IPV4_ADDRESS_NUM];                 // Memory for IPv4 address value used in vioSetIPv4/vioGetIPv4\n__USED vioAddrIPv6_t vioAddrIPv6[VIO_IPV6_ADDRESS_NUM];                 // Memory for IPv6 address value used in vioSetIPv6/vioGetIPv6\n\n#if !defined CMSIS_VOUT\n// Add global user types, variables, functions here:\n\n#endif\n\n#if !defined CMSIS_VIN\n// Add global user types, variables, functions here:\n\n#endif\n\n// Initialize test input, output.\nvoid vioInit (void) {\n#if !defined CMSIS_VOUT\n// Add user variables here:\n\n#endif\n#if !defined CMSIS_VIN\n// Add user variables here:\n\n#endif\n\n  vioSignalIn  = 0U;\n  vioSignalOut = 0U;\n\n  memset (vioPrintMem, 0, sizeof(vioPrintMem));\n  memset (vioValue,    0, sizeof(vioValue));\n  memset (vioValueXYZ, 0, sizeof(vioValueXYZ));\n  memset (vioAddrIPv4, 0, sizeof(vioAddrIPv4));\n  memset (vioAddrIPv6, 0, sizeof(vioAddrIPv6));\n\n#if !defined CMSIS_VOUT\n// Add user code here:\n\n#endif\n\n#if !defined CMSIS_VIN\n// Add user code here:\n\n#endif\n}\n\n// Print formated string to test terminal.\nint32_t vioPrint (uint32_t level, const char *format, ...) {\n  va_list args;\n  int32_t ret;\n#if !defined CMSIS_VOUT\n// Add user variables here:\n\n#endif\n\n  if (level > vioLevelError) {\n    return (-1);\n  }\n\n  if (level > VIO_PRINTMEM_NUM) {\n    return (-1);\n  }\n\n  va_start(args, format);\n\n  ret = vsnprintf((char *)vioPrintMem[level], sizeof(vioPrintMem[level]), format, args);\n\n  va_end(args);\n\n#if !defined CMSIS_VOUT\n// Add user code here:\n\n#endif\n\n  return (ret);\n}\n\n// Set signal output.\nvoid vioSetSignal (uint32_t mask, uint32_t signal) {\n#if !defined CMSIS_VOUT\n// Add user variables here:\n\n#endif\n\n  vioSignalOut &= ~mask;\n  vioSignalOut |=  mask & signal;\n\n#if !defined CMSIS_VOUT\n// Add user code here:\n\n#endif\n}\n\n// Get signal input.\nuint32_t vioGetSignal (uint32_t mask) {\n  uint32_t signal;\n#if !defined CMSIS_VIN\n// Add user variables here:\n\n#endif\n\n#if !defined CMSIS_VIN\n// Add user code here:\n\n//   vioSignalIn = ...;\n#endif\n\n  signal = vioSignalIn;\n\n  return (signal & mask);\n}\n\n// Set value output.\nvoid vioSetValue (uint32_t id, int32_t value) {\n  uint32_t index = id;\n#if !defined CMSIS_VOUT\n// Add user variables here:\n\n#endif\n\n  if (index >= VIO_VALUE_NUM) {\n    return;                             /* return in case of out-of-range index */\n  }\n\n  vioValue[index] = value;\n\n#if !defined CMSIS_VOUT\n// Add user code here:\n\n#endif\n}\n\n// Get value input.\nint32_t vioGetValue (uint32_t id) {\n  uint32_t index = id;\n  int32_t  value = 0;\n#if !defined CMSIS_VIN\n// Add user variables here:\n\n#endif\n\n  if (index >= VIO_VALUE_NUM) {\n    return value;                       /* return default in case of out-of-range index */\n  }\n\n#if !defined CMSIS_VIN\n// Add user code here:\n\n//   vioValue[index] = ...;\n#endif\n\n  value = vioValue[index];\n\n  return value;\n}\n\n// Set XYZ value output.\nvoid vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ) {\n  uint32_t index = id;\n#if !defined CMSIS_VOUT\n// Add user variables here:\n\n#endif\n\n  if (index >= VIO_VALUEXYZ_NUM) {\n    return;                             /* return in case of out-of-range index */\n  }\n\n  vioValueXYZ[index] = valueXYZ;\n\n#if !defined CMSIS_VOUT\n// Add user code here:\n\n#endif\n}\n\n// Get XYZ value input.\nvioValueXYZ_t vioGetXYZ (uint32_t id) {\n  uint32_t index = id;\n  vioValueXYZ_t valueXYZ = {0, 0, 0};\n#if !defined CMSIS_VIN\n// Add user variables here:\n\n#endif\n\n  if (index >= VIO_VALUEXYZ_NUM) {\n    return valueXYZ;                    /* return default in case of out-of-range index */\n  }\n\n#if !defined CMSIS_VIN\n// Add user code here:\n\n//   vioValueXYZ[index] = ...;\n#endif\n\n  valueXYZ = vioValueXYZ[index];\n\n  return valueXYZ;\n}\n\n// Set IPv4 address output.\nvoid vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4) {\n  uint32_t index = id;\n#if !defined CMSIS_VOUT\n// Add user variables here:\n\n#endif\n\n  if (index >= VIO_IPV4_ADDRESS_NUM) {\n    return;                             /* return in case of out-of-range index */\n  }\n\n  vioAddrIPv4[index] = addrIPv4;\n\n#if !defined CMSIS_VOUT\n// Add user code here:\n\n#endif\n}\n\n// Get IPv4 address input.\nvioAddrIPv4_t vioGetIPv4 (uint32_t id) {\n  uint32_t index = id;\n  vioAddrIPv4_t addrIPv4 = {0U, 0U, 0U, 0U};\n#if !defined CMSIS_VIN\n// Add user variables here:\n\n#endif\n\n  if (index >= VIO_IPV4_ADDRESS_NUM) {\n    return addrIPv4;                    /* return default in case of out-of-range index */\n  }\n\n#if !defined CMSIS_VIN\n// Add user code here:\n\n//   vioAddrIPv4[index] = ...;\n#endif\n\n  addrIPv4 = vioAddrIPv4[index];\n\n  return addrIPv4;\n}\n\n// Set IPv6 address output.\nvoid vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6) {\n  uint32_t index = id;\n#if !defined CMSIS_VOUT\n// Add user variables here:\n\n#endif\n\n  if (index >= VIO_IPV6_ADDRESS_NUM) {\n    return;                             /* return in case of out-of-range index */\n  }\n\n  vioAddrIPv6[index] = addrIPv6;\n\n#if !defined CMSIS_VOUT\n// Add user code here:\n\n#endif\n}\n\n// Get IPv6 address input.\nvioAddrIPv6_t vioGetIPv6 (uint32_t id) {\n  uint32_t index = id;\n  vioAddrIPv6_t addrIPv6 = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U,\n                            0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U};\n#if !defined CMSIS_VIN\n// Add user variables here:\n\n#endif\n\n  if (index >= VIO_IPV6_ADDRESS_NUM) {\n    return addrIPv6;                    /* return default in case of out-of-range index */\n  }\n\n#if !defined CMSIS_VIN\n// Add user code here:\n\n//   vioAddrIPv6[index] = ...;\n#endif\n\n  addrIPv6 = vioAddrIPv6[index];\n\n  return addrIPv6;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/VIO/Source/vio_memory.c",
    "content": "/******************************************************************************\n * @file     vio_memory.c\n * @brief    Virtual I/O implementation using memory only\n * @version  V1.0.0\n * @date     23. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2019-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <stdio.h>\n#include <string.h>\n#include <stdarg.h>\n#include \"cmsis_vio.h\"\n\n#include \"RTE_Components.h\"             // Component selection\n#include CMSIS_device_header\n\n// VIO input, output definitions\n#define VIO_PRINT_MAX_SIZE      64U     // maximum size of print memory\n#define VIO_PRINTMEM_NUM         4U     // number of print memories\n#ifndef VIO_VALUE_NUM\n#define VIO_VALUE_NUM            3U     // number of values\n#endif\n#ifndef VIO_VALUEXYZ_NUM\n#define VIO_VALUEXYZ_NUM         3U     // number of XYZ values\n#endif\n#ifndef VIO_IPV4_ADDRESS_NUM\n#define VIO_IPV4_ADDRESS_NUM     2U     // number of IPv4 addresses\n#endif\n#ifndef VIO_IPV6_ADDRESS_NUM\n#define VIO_IPV6_ADDRESS_NUM     2U     // number of IPv6 addresses\n#endif\n\n// VIO input, output variables\n__USED uint32_t      vioSignalIn;\n__USED uint32_t      vioSignalOut;\n__USED char          vioPrintMem[VIO_PRINTMEM_NUM][VIO_PRINT_MAX_SIZE];\n__USED int32_t       vioValue   [VIO_VALUE_NUM];\n__USED vioValueXYZ_t vioValueXYZ[VIO_VALUEXYZ_NUM];\n__USED vioAddrIPv4_t vioAddrIPv4[VIO_IPV4_ADDRESS_NUM];\n__USED vioAddrIPv6_t vioAddrIPv6[VIO_IPV6_ADDRESS_NUM];\n\n// Initialize test input, output.\nvoid vioInit (void) {\n\n  vioSignalIn  = 0U;\n  vioSignalOut = 0U;\n\n  memset (vioPrintMem, 0, sizeof(vioPrintMem));\n  memset (vioValue,    0, sizeof(vioValue));\n  memset (vioValueXYZ, 0, sizeof(vioValueXYZ));\n  memset (vioAddrIPv4, 0, sizeof(vioAddrIPv4));\n  memset (vioAddrIPv6, 0, sizeof(vioAddrIPv6));\n}\n\n// Print formated string to test terminal.\nint32_t vioPrint (uint32_t level, const char *format, ...) {\n  va_list args;\n  int32_t ret;\n\n  if (level > vioLevelError) {\n    return (-1);\n  }\n\n  if (level > VIO_PRINTMEM_NUM) {\n    return (-1);\n  }\n\n  va_start(args, format);\n\n  ret = vsnprintf((char *)vioPrintMem[level], sizeof(vioPrintMem[level]), format, args);\n\n  va_end(args);\n\n  return (ret);\n}\n\n// Set signal output.\nvoid vioSetSignal (uint32_t mask, uint32_t signal) {\n\n  vioSignalOut &= ~mask;\n  vioSignalOut |=  mask & signal;\n}\n\n// Get signal input.\nuint32_t vioGetSignal (uint32_t mask) {\n  uint32_t signal;\n\n  signal = vioSignalIn;\n\n  return (signal & mask);\n}\n\n// Set value output.\nvoid vioSetValue (uint32_t id, int32_t value) {\n  uint32_t index = id;\n\n  if (index >= VIO_VALUE_NUM) {\n    return;                             /* return in case of out-of-range index */\n  }\n\n  vioValue[index] = value;\n}\n\n// Get value input.\nint32_t vioGetValue (uint32_t id) {\n  uint32_t index = id;\n  int32_t  value = 0;\n\n  if (index >= VIO_VALUE_NUM) {\n    return value;                       /* return default in case of out-of-range index */\n  }\n\n  value = vioValue[index];\n\n  return value;\n}\n\n// Set XYZ value output.\nvoid vioSetXYZ (uint32_t id, vioValueXYZ_t valueXYZ) {\n  uint32_t index = id;\n\n  if (index >= VIO_VALUEXYZ_NUM) {\n    return;                             /* return in case of out-of-range index */\n  }\n\n  vioValueXYZ[index] = valueXYZ;\n}\n\n// Get XYZ value input.\nvioValueXYZ_t vioGetXYZ (uint32_t id) {\n  uint32_t index = id;\n  vioValueXYZ_t valueXYZ = {0, 0, 0};\n\n  if (index >= VIO_VALUEXYZ_NUM) {\n    return valueXYZ;                    /* return default in case of out-of-range index */\n  }\n\n  valueXYZ = vioValueXYZ[index];\n\n  return valueXYZ;\n}\n\n// Set IPv4 address output.\nvoid vioSetIPv4 (uint32_t id, vioAddrIPv4_t addrIPv4) {\n  uint32_t index = id;\n\n  if (index >= VIO_IPV4_ADDRESS_NUM) {\n    return;                             /* return in case of out-of-range index */\n  }\n\n  vioAddrIPv4[index] = addrIPv4;\n}\n\n// Get IPv4 address input.\nvioAddrIPv4_t vioGetIPv4 (uint32_t id) {\n  uint32_t index = id;\n  vioAddrIPv4_t addrIPv4 = {0U, 0U, 0U, 0U};\n\n  if (index >= VIO_IPV4_ADDRESS_NUM) {\n    return addrIPv4;                    /* return default in case of out-of-range index */\n  }\n\n  addrIPv4 = vioAddrIPv4[index];\n\n  return addrIPv4;\n}\n\n// Set IPv6 address output.\nvoid vioSetIPv6 (uint32_t id, vioAddrIPv6_t addrIPv6) {\n  uint32_t index = id;\n\n  if (index >= VIO_IPV6_ADDRESS_NUM) {\n    return;                             /* return in case of out-of-range index */\n  }\n\n  vioAddrIPv6[index] = addrIPv6;\n}\n\n// Get IPv6 address input.\nvioAddrIPv6_t vioGetIPv6 (uint32_t id) {\n  uint32_t index = id;\n  vioAddrIPv6_t addrIPv6 = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U,\n                            0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U};\n\n  if (index >= VIO_IPV6_ADDRESS_NUM) {\n    return addrIPv6;                    /* return default in case of out-of-range index */\n  }\n\n  addrIPv6 = vioAddrIPv6[index];\n\n  return addrIPv6;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Driver/VIO/cmsis_vio.scvd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<component_viewer schemaVersion=\"1.2.0\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"Component_Viewer.xsd\">\n<component name=\"CMSIS-Driver VIO\" version=\"1.0.0\"/>\n\n  <typedefs>\n    <typedef name=\"vioPrintMem_t\" size=\"64\">\n      <member name=\"mem\" type=\"uint8_t\" size=\"64\" offset=\"0\"/>\n    </typedef>\n\n    <typedef name=\"vioValueXYZ_t\" size=\"12\">\n      <member name=\"X\" type=\"int32_t\" offset=\"0\"/>\n      <member name=\"Y\" type=\"int32_t\" offset=\"4\"/>\n      <member name=\"Z\" type=\"int32_t\" offset=\"8\"/>\n    </typedef>\n\n    <typedef name=\"vioAddrIPv4_t\" size=\"4\">\n      <member name=\"addr\" type=\"uint8_t\" size=\"4\"  offset=\"0\"/>\n    </typedef>\n\n    <typedef name=\"vioAddrIPv6_t\" size=\"16\">\n      <member name=\"addr\" type=\"uint8_t\" size=\"16\" offset=\"0\"/>\n    </typedef>\n\n  </typedefs>\n\n  <objects>\n    <object name=\"VIO Object\">\n      <var name=\"i\" type=\"int32_t\" value=\"0\"/>\n\n      <read     name=\"SignalIn\"    type=\"uint32_t\"      symbol=\"vioSignalIn\"/>\n      <read     name=\"SignalOut\"   type=\"uint32_t\"      symbol=\"vioSignalOut\"/>\n      <readlist name=\"PrintMem\"    type=\"vioPrintMem_t\" symbol=\"vioPrintMem\" count=\"4\"/>\n      <read     name=\"Value\"       type=\"int32_t\"       symbol=\"vioValue\"    size=\"__size_of(&quot;vioValue&quot;)\"/>\n      <readlist name=\"ValueXYZ\"    type=\"vioValueXYZ_t\" symbol=\"vioValueXYZ\" count=\"__size_of(&quot;vioValueXYZ&quot;)\"/>\n      <readlist name=\"IPv4Address\" type=\"vioAddrIPv4_t\" symbol=\"vioAddrIPv4\" count=\"__size_of(&quot;vioAddrIPv4&quot;)\"/>\n      <readlist name=\"IPv6Address\" type=\"vioAddrIPv6_t\" symbol=\"vioAddrIPv6\" count=\"__size_of(&quot;vioAddrIPv6&quot;)\"/>\n\n      <out name=\"CMSIS-Driver VIO\">\n        <item property=\"Signal Bits (Input)\"  value=\"%x[SignalIn]\"/>\n        <item property=\"Signal Bits (Output)\" value=\"%x[SignalOut]\"/>\n\n        <item property=\"Print Memory Array\">\n           <list name=\"i\" start=\"0\" limit=\"PrintMem._count\">\n             <item property=\"Print Memory[%d[i]]\" value=\"%t[PrintMem[i].mem]\"/>\n           </list>\n        </item>\n\n        <item property=\"Value Array\">\n           <list name=\"i\" start=\"0\" limit=\"Value._count\">\n             <item property=\"Value[%d[i]]\"  value=\"%d[Value[i]]\"/>\n           </list>\n        </item>\n\n        <item property=\"ValueXYZ Array\">\n           <list name=\"i\" start=\"0\" limit=\"ValueXYZ._count\">\n             <item property=\"ValueXYZ[%d[i]]\" value=\"X: %d[ValueXYZ[i].X] Y: %d[ValueXYZ[i].Y] Z: %d[ValueXYZ[i].Z]\"/>\n           </list>\n        </item>\n\n        <item property=\"IP4 Address Array\">\n           <list name=\"i\" start=\"0\" limit=\"IPv4Address._count\">\n             <item property=\"IP4 Address[%d[i]]\" value=\"%I[IPv4Address[i].addr]\"/>\n           </list>\n        </item>\n\n        <item property=\"IP6 Address Array\">\n           <list name=\"i\" start=\"0\" limit=\"IPv6Address._count\">\n             <item property=\"IP6 Address[%d[i]]\" value=\"%J[IPv6Address[i].addr]\"/>\n           </list>\n        </item>\n\n      </out>\n\n    </object>\n\n  </objects>\n\n</component_viewer>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/NN/README.md",
    "content": "# CMSIS-NN\n\n![GitHub release (latest by date including pre-releases)](https://img.shields.io/github/v/release/ARM-software/CMSIS-NN?include_prereleases) ![GitHub](https://img.shields.io/github/license/ARM-software/CMSIS-NN)\n\nThis CMSIS component has been moved into its own realm, please find it at [ARM-software/CMSIS-NN](https://github.com/ARM-software/CMSIS-NN). \nUsers of pre-TFLM quantization API's can use the [5.9.0](https://github.com/ARM-software/CMSIS_5/releases/tag/5.9.0) release of CMSIS_5 for that.\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Pack/Bash/Include/component.h",
    "content": ""
  },
  {
    "path": "external/CMSIS_5/CMSIS/Pack/Bash/License.txt",
    "content": "Placeholder for license.\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Pack/Bash/MyVendor.MyPack.pdsc.txt",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<package xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"PACK.xsd\" schemaVersion=\"1.6.0\">\n  <name>MyPack</name>\n  <vendor>MyVendor</vendor>\n  <description>MyVendor Pack</description>\n  <!-- empty until the pack gets published -->\n  <url> </url>\n  <license>License.txt</license>\n  <releases>\n    <release version=\"1.0.0\" date=\"2019-08-16\">\n      Initial Release\n    </release>\n  </releases>\n\n  <conditions>\n    <condition id=\"MyComponent-CM3\">\n    <description>This ensures that MyComponent is only available for Cortex-M3</description>\n    <require Dcore=\"Cortex-M3\"/>\n    </condition>\t\n  </conditions>\n\n  <components>\n    <component Cclass=\"MyClass\" Cgroup=\"MyComponent\" Cversion=\"1.0.0\" condition=\"MyComponent-CM3\">\n      <description>MyComponent</description>\n      <files>\n        <file category=\"sourceC\" name=\"Source/component.c\"/>\n        <file category=\"header\"  name=\"Include/component.h\"/>\n        <file category=\"doc\" name=\"README.md\"/>\n      </files>\n    </component>\n  </components>\n\n</package>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Pack/Bash/README.md",
    "content": "Placeholder for ReadMe.\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Pack/Bash/Source/component.c",
    "content": ""
  },
  {
    "path": "external/CMSIS_5/CMSIS/Pack/Bash/gen_pack.sh",
    "content": "#!/bin/bash\n# Version: 1.1 \n# Date: 2020-04-29\n# This bash script generates a CMSIS Software Pack:\n#\n# Pre-requisites:\n# - bash shell (for Windows: install git for Windows)\n# - 7z in path (zip archiving utility)\n#   e.g. Ubuntu: sudo apt-get install p7zip-full p7zip-rar) \n# - PackChk in path with execute permission\n#   (see CMSIS-Pack: CMSIS/Utilities/<os>/PackChk)\n# - xmllint in path (XML schema validation)\n#   e.g. Ubuntu: sudo apt-get install libxml2-utils\n#   Windows: download from https://www.zlatkovic.com/pub/libxml/\n\n############### EDIT BELOW ###############\n# Extend Path environment variable locally\n#\nif [ `uname -s` = \"Linux\" ]\n  then\n  CMSIS_PACK_PATH=\"/home/$USER/.arm/Packs/ARM/CMSIS/5.7.0/\"\n  PATH_TO_ADD=\"$CMSIS_PACK_PATH/CMSIS/Utilities/Linux64/\"\nelse\n  CMSIS_PACK_PATH=\"$LOCALAPPDATA/Arm/Packs/ARM/CMSIS/5.7.0\"\n  PATH_TO_ADD=\"/C/Program Files/7-Zip/:$CMSIS_PACK_PATH/CMSIS/Utilities/Win32/:/C/xmllint/\"\nfi\n[[ \":$PATH:\" != *\":$PATH_TO_ADD}:\"* ]] && PATH=\"${PATH}:${PATH_TO_ADD}\"\necho $PATH_TO_ADD appended to PATH\necho \" \"\n\n# Pack warehouse directory - destination \nPACK_WAREHOUSE=output/\n\n# Temporary pack build directory\nPACK_BUILD=build/\n\n# Specify directories included in pack relative to base directory\n# All directories:\nPACK_DIRS=`ls -d */`\n# Do not include the build directory if it is local\nPACK_DIRS=${PACK_DIRS//$PACK_BUILD/}\nPACK_DIRS=${PACK_DIRS//$PACK_WAREHOUSE/}\n\n# alternative: specify directory names to be added to pack base directory\n# PACK_DIRS=\"\n#  Source\n#  Include\n#\"\n  \n# Specify file names to be added to pack base directory\nPACK_BASE_FILES=\"\n  License.txt\n  README.md\n\"\n\n############ DO NOT EDIT BELOW ###########\necho Starting CMSIS-Pack Generation: `date`\n# Zip utility check \nZIP=7z\ntype -a $ZIP\nerrorlevel=$?\nif [ $errorlevel -gt 0 ]\n  then\n  echo \"Error: No 7zip Utility found\"\n  echo \"Action: Add 7zip to your path\"\n  echo \" \"\n  exit\nfi\n\n# Pack checking utility check\nPACKCHK=PackChk\ntype -a $PACKCHK\nerrorlevel=$?\nif [ $errorlevel != 0 ]\n  then\n  echo \"Error: No PackChk Utility found\"\n  echo \"Action: Add PackChk to your path\"\n  echo \"Hint: Included in CMSIS Pack:\"\n  echo \"<pack_root_dir>/ARM/CMSIS/<version>/CMSIS/Utilities/<os>/\"\n  echo \" \"\n  exit\nfi\necho \" \"\n\n# XML syntax checking utility check\nXMLLINT=xmllint\ntype -a $XMLLINT\nerrorlevel=$?\nif [ $errorlevel != 0 ]\n  then\n  echo \"Error: No xmllint found\"\n  echo \"Action: Add xmllint to your path\"\n  echo \" \"\n  exit\nfi\necho \" \"\n\n# Locate Package Description file\n# check whether there is more than one pdsc file\nNUM_PDSCS=`ls -1 *.pdsc | wc -l`\nPACK_DESCRIPTION_FILE=`ls *.pdsc`\nif [ $NUM_PDSCS -lt 1 ]\n  then\n  echo \"Error: No *.pdsc file found in current directory\"\n  echo \" \"\nelif [ $NUM_PDSCS -gt 1 ]\n  then\n  echo \"Error: Only one PDSC file allowed in directory structure:\"\n  echo \"Found:\"\n  echo \"$PACK_DESCRIPTION_FILE\"\n  echo \"Action: Delete unused pdsc files\"\n  echo \" \"\n  exit\nfi\n\nSAVEIFS=$IFS\nIFS=.\nset $PACK_DESCRIPTION_FILE\n# Pack Vendor\nPACK_VENDOR=$1\n# Pack Name\nPACK_NAME=$2\necho Generating Pack Version: for $PACK_VENDOR.$PACK_NAME\necho \" \"\nIFS=$SAVEIFS\n\n#if $PACK_BUILD directory does not exist, create it.\nif [ ! -d $PACK_BUILD ]; then\n  mkdir -p $PACK_BUILD\nfi\n\n# Copy files into build base directory: $PACK_BUILD\n# pdsc file is mandatory in base directory:\ncp -f  ./$PACK_VENDOR.$PACK_NAME.pdsc ${PACK_BUILD}\n\n# directories\necho Adding directories to pack:\necho $PACK_DIRS\necho \" \"\nfor d in ${PACK_DIRS}\ndo\n  cp -r \"$d\" ${PACK_BUILD}\ndone\n\n# files for base directory\necho Adding files to pack:\necho $PACK_BASE_FILES\necho \" \"\nfor f in $PACK_BASE_FILES\ndo \n  cp -f  \"$f\" $PACK_BUILD/ \ndone\n\n# Run Schema Check (for Linux only):\n# sudo apt-get install libxml2-utils\n\necho Running schema check for $PACK_VENDOR.$PACK_NAME.pdsc\n$XMLLINT --noout --schema ${CMSIS_PACK_PATH}/CMSIS/Utilities/PACK.xsd $PACK_BUILD/$PACK_VENDOR.$PACK_NAME.pdsc\nerrorlevel=$?\nif [ $errorlevel -ne 0 ]; then\n  echo \"build aborted: Schema check of $PACK_VENDOR.$PACK_NAME.pdsc against PACK.xsd failed\"\n  echo \" \"\n  exit\nfi\n\n# Run Pack Check and generate PackName file with version\n$PACKCHK $PACK_BUILD/$PACK_VENDOR.$PACK_NAME.pdsc -n PackName.txt -x M362\nerrorlevel=$?\nif [ $errorlevel -ne 0 ]; then\n  echo \"build aborted: pack check failed\"\n  echo \" \"\n  exit\nfi\n\nPACKNAME=`cat PackName.txt`\nrm -rf PackName.txt\n\n# Archiving\n# $ZIP a $PACKNAME\necho creating pack file $PACKNAME\n#if $PACK_WAREHOUSE directory does not exist create it\nif [ ! -d $PACK_WAREHOUSE ]; then\n  mkdir -p $PACK_WAREHOUSE\nfi\npushd $PACK_WAREHOUSE\nPACK_WAREHOUSE=`pwd`\npopd\npushd $PACK_BUILD\n\"$ZIP\" a $PACK_WAREHOUSE/$PACKNAME -tzip\npopd\nerrorlevel=$?\nif [ $errorlevel -ne 0 ]; then\n  echo \"build aborted: archiving failed\"\n  exit\nfi\n\necho \"build of pack succeeded\"\n# Clean up\necho \"cleaning up ...\"\n\nrm -rf $PACK_BUILD\necho \" \"\n\necho Completed CMSIS-Pack Generation: `date`\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/INC/RTX_CM_lib.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RTX_CM_LIB.H\n *      Purpose: RTX Kernel System Configuration\n *      Rev.:    V4.82\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2019 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n\n *---------------------------------------------------------------------------*/\n\n#if   defined (__CC_ARM)\n#pragma O3\n#define __USED __attribute__((used))\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define __USED __attribute__((used))\n#elif defined (__GNUC__)\n#pragma GCC optimize (\"O3\")\n#define __USED __attribute__((used))\n#elif defined (__ICCARM__)\n#define __USED __root\n#endif\n\n\n/*----------------------------------------------------------------------------\n *      Definitions\n *---------------------------------------------------------------------------*/\n\n#define _declare_box(pool,size,cnt)  uint32_t pool[(((size)+3)/4)*(cnt) + 3]\n#define _declare_box8(pool,size,cnt) uint64_t pool[(((size)+7)/8)*(cnt) + 2]\n\n#define OS_TCB_SIZE     52\n#define OS_TMR_SIZE     8\n\n#if (( defined(__CC_ARM)                                          || \\\n      (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \\\n      !defined(__MICROLIB))\n\ntypedef void    *OS_ID;\ntypedef uint32_t OS_TID;\ntypedef uint32_t OS_MUT[4];\ntypedef uint32_t OS_RESULT;\n\n#define runtask_id()    rt_tsk_self()\n#define mutex_init(m)   rt_mut_init(m)\n#define mutex_wait(m)   os_mut_wait(m,0xFFFFU)\n#define mutex_rel(m)    os_mut_release(m)\n\nextern uint8_t   os_running;\nextern OS_TID    rt_tsk_self    (void);\nextern void      rt_mut_init    (OS_ID mutex);\nextern OS_RESULT rt_mut_release (OS_ID mutex);\nextern OS_RESULT rt_mut_wait    (OS_ID mutex, uint16_t timeout);\n\n#if defined(__CC_ARM)\n#define os_mut_wait(mutex,timeout) _os_mut_wait((uint32_t)rt_mut_wait,mutex,timeout)\n#define os_mut_release(mutex)      _os_mut_release((uint32_t)rt_mut_release,mutex)\nOS_RESULT _os_mut_release (uint32_t p, OS_ID mutex)                   __svc_indirect(0);\nOS_RESULT _os_mut_wait    (uint32_t p, OS_ID mutex, uint16_t timeout) __svc_indirect(0);\n#else\n__attribute__((always_inline))\nstatic __inline OS_RESULT os_mut_release (OS_ID mutex) {\n  register uint32_t __rf __asm(\"r12\") = (uint32_t)rt_mut_release;\n  register uint32_t __r0 __asm(\"r0\")  = (uint32_t)mutex;\n  __asm volatile                                                               \\\n  (                                                                            \\\n    \"svc 0\"                                                                    \\\n    :            \"=r\" (__r0)                                                   \\\n    : \"r\" (__rf), \"r\" (__r0)                                                   \\\n    : \"r1\", \"r2\"                                                               \\\n  );\n  return (OS_RESULT)__r0;\n}\n__attribute__((always_inline))\nstatic __inline OS_RESULT os_mut_wait (OS_ID mutex, uint16_t timeout) {\n  register uint32_t __rf __asm(\"r12\") = (uint32_t)rt_mut_wait;\n  register uint32_t __r0 __asm(\"r0\")  = (uint32_t)mutex;\n  register uint32_t __r1 __asm(\"r1\")  = (uint32_t)timeout;\n  __asm volatile                                                               \\\n  (                                                                            \\\n    \"svc 0\"                                                                    \\\n    :            \"=r\" (__r0)                                                   \\\n    : \"r\" (__rf), \"r\" (__r0), \"r\" (__r1)                                       \\\n    : \"r2\"                                                                     \\\n  );\n  return (OS_RESULT)__r0;\n}\n#endif\n\n#endif\n\n\n/*----------------------------------------------------------------------------\n *      Global Variables\n *---------------------------------------------------------------------------*/\n\n#if (OS_TASKCNT == 0)\n#error \"Invalid number of concurrent running threads!\"\n#endif\n\n#if (OS_PRIVCNT >= OS_TASKCNT)\n#error \"Too many threads with user-provided stack size!\"\n#endif\n\n#if (OS_TIMERS != 0)\n#define OS_TASK_CNT (OS_TASKCNT + 1)\n#define OS_PRIV_CNT (OS_PRIVCNT + 2)\n#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE+OS_TIMERSTKSZ))\n#else\n#define OS_TASK_CNT  OS_TASKCNT\n#define OS_PRIV_CNT (OS_PRIVCNT + 1)\n#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE))\n#endif\n\n#ifndef OS_STKINIT\n#define OS_STKINIT  0\n#endif\n\nextern uint16_t const os_maxtaskrun;\nextern uint32_t const os_stackinfo;\nextern uint32_t const os_rrobin;\nextern uint32_t const os_trv;\nextern uint8_t  const os_flags;\n\nuint16_t const os_maxtaskrun = OS_TASK_CNT;\nuint32_t const os_stackinfo  = (OS_STKINIT<<28) | (OS_STKCHECK<<24) | (OS_PRIV_CNT<<16) | (OS_STKSIZE*4);\nuint32_t const os_rrobin     = (OS_ROBIN << 16) | OS_ROBINTOUT;\nuint32_t const os_tickfreq   = OS_CLOCK;\nuint16_t const os_tickus_i   = OS_CLOCK/1000000;\nuint16_t const os_tickus_f   = (((uint64_t)(OS_CLOCK-1000000*(OS_CLOCK/1000000)))<<16)/1000000;\nuint32_t const os_trv        = OS_TRV;\nuint8_t  const os_flags      = OS_RUNPRIV;\n\n/* Export following defines to uVision debugger. */\nextern uint32_t const CMSIS_RTOS_API_Version;\n__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;\nextern uint32_t const CMSIS_RTOS_RTX_Version;\n__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;\nextern uint32_t const os_clockrate;\n__USED uint32_t const os_clockrate = OS_TICK;\nextern uint32_t const os_timernum;\n__USED uint32_t const os_timernum  = 0U;\n\n/* Memory pool for TCB allocation    */\nextern\nuint32_t       mp_tcb[];\n_declare_box  (mp_tcb, OS_TCB_SIZE, OS_TASK_CNT);\nextern\nuint16_t const mp_tcb_size;\nuint16_t const mp_tcb_size = sizeof(mp_tcb);\n\n/* Memory pool for System stack allocation (+os_idle_demon). */\nextern\nuint64_t       mp_stk[];\n_declare_box8 (mp_stk, OS_STKSIZE*4, OS_TASK_CNT-OS_PRIV_CNT+1);\nextern\nuint32_t const mp_stk_size;\nuint32_t const mp_stk_size = sizeof(mp_stk);\n\n/* Memory pool for user specified stack allocation (+main, +timer) */\nextern\nuint64_t       os_stack_mem[];\nuint64_t       os_stack_mem[2+OS_PRIV_CNT+(OS_STACK_SZ/8)];\nextern\nuint32_t const os_stack_sz;\nuint32_t const os_stack_sz = sizeof(os_stack_mem);\n\n#ifndef OS_FIFOSZ\n#define OS_FIFOSZ       16\n#endif\n\n/* Fifo Queue buffer for ISR requests.*/\nextern\nuint32_t       os_fifo[];\nuint32_t       os_fifo[OS_FIFOSZ*2+1];\nextern\nuint8_t  const os_fifo_size;\nuint8_t  const os_fifo_size = OS_FIFOSZ;\n\n/* An array of Active task pointers. */\nextern\nvoid *os_active_TCB[];\nvoid *os_active_TCB[OS_TASK_CNT];\n\n/* User Timers Resources */\n#if (OS_TIMERS != 0)\nextern void osTimerThread (void const *argument);\nextern const osThreadDef_t os_thread_def_osTimerThread;\nosThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 1, 4*OS_TIMERSTKSZ);\nextern\nosThreadId osThreadId_osTimerThread;\nosThreadId osThreadId_osTimerThread;\nextern uint32_t os_messageQ_q_osTimerMessageQ[];\nextern const osMessageQDef_t os_messageQ_def_osTimerMessageQ;\nosMessageQDef(osTimerMessageQ, OS_TIMERCBQS, void *);\nextern\nosMessageQId osMessageQId_osTimerMessageQ;\nosMessageQId osMessageQId_osTimerMessageQ;\n#else\nextern\nconst osThreadDef_t os_thread_def_osTimerThread;\nconst osThreadDef_t os_thread_def_osTimerThread = { NULL, osPriorityNormal, 0U, 0U };\nextern\nosThreadId osThreadId_osTimerThread;\nosThreadId osThreadId_osTimerThread;\nextern uint32_t os_messageQ_q_osTimerMessageQ[];\nextern const osMessageQDef_t os_messageQ_def_osTimerMessageQ;\nosMessageQDef(osTimerMessageQ, 0U, void *);\nextern\nosMessageQId osMessageQId_osTimerMessageQ;\nosMessageQId osMessageQId_osTimerMessageQ;\n#endif\n\n/* Legacy RTX User Timers not used */\nextern\nuint32_t       os_tmr; \nuint32_t       os_tmr = 0U; \nextern\nuint32_t const *m_tmr;\nuint32_t const *m_tmr = NULL;\nextern\nuint16_t const mp_tmr_size;\nuint16_t const mp_tmr_size = 0U;\n\n#if (( defined(__CC_ARM)                                          || \\\n      (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \\\n      !defined(__MICROLIB))\n/* A memory space for arm standard library. */\nstatic uint32_t std_libspace[OS_TASK_CNT][96/4];\nstatic OS_MUT   std_libmutex[OS_MUTEXCNT];\nstatic uint32_t nr_mutex;\nextern void  *__libspace_start;\n#endif\n\n\n/*----------------------------------------------------------------------------\n *      RTX Optimizations (empty functions)\n *---------------------------------------------------------------------------*/\n\n#if OS_ROBIN == 0\nextern\nvoid rt_init_robin (void);\nvoid rt_init_robin (void) {;}\nextern\nvoid rt_chk_robin  (void);\nvoid rt_chk_robin  (void) {;}\n#endif\n\n#if OS_STKCHECK == 0\nextern\nvoid rt_stk_check  (void);\nvoid rt_stk_check  (void) {;}\n#endif\n\n\n/*----------------------------------------------------------------------------\n *      Standard Library multithreading interface\n *---------------------------------------------------------------------------*/\n\n#if (( defined(__CC_ARM)                                          || \\\n      (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \\\n      !defined(__MICROLIB))\n\n/*--------------------------- __user_perthread_libspace ---------------------*/\n\nvoid *__user_perthread_libspace (void);\nvoid *__user_perthread_libspace (void) {\n  /* Provide a separate libspace for each task. */\n  uint32_t idx;\n\n  idx = (os_running != 0U) ? runtask_id () : 0U;\n  if (idx == 0U) {\n    /* RTX not running yet. */\n    return (&__libspace_start);\n  }\n  return ((void *)&std_libspace[idx-1]);\n}\n\n/*--------------------------- _mutex_initialize -----------------------------*/\n\nint _mutex_initialize (OS_ID *mutex);\nint _mutex_initialize (OS_ID *mutex) {\n  /* Allocate and initialize a system mutex. */\n\n  if (nr_mutex >= OS_MUTEXCNT) {\n    /* If you are here, you need to increase the number OS_MUTEXCNT. */\n    for (;;);\n  }\n  *mutex = &std_libmutex[nr_mutex++];\n  mutex_init (*mutex);\n  return (1);\n}\n\n\n/*--------------------------- _mutex_acquire --------------------------------*/\n\n__attribute__((used))\nvoid _mutex_acquire (OS_ID *mutex);\nvoid _mutex_acquire (OS_ID *mutex) {\n  /* Acquire a system mutex, lock stdlib resources. */\n  if (os_running) {\n    /* RTX running, acquire a mutex. */\n    mutex_wait (*mutex);\n  }\n}\n\n\n/*--------------------------- _mutex_release --------------------------------*/\n\n__attribute__((used))\nvoid _mutex_release (OS_ID *mutex);\nvoid _mutex_release (OS_ID *mutex) {\n  /* Release a system mutex, unlock stdlib resources. */\n  if (os_running) {\n    /* RTX running, release a mutex. */\n    mutex_rel (*mutex);\n  }\n}\n\n#endif\n\n\n/*----------------------------------------------------------------------------\n *      ARMCC6 Wrappers for ARMCC5 Binary\n *---------------------------------------------------------------------------*/\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n\ntypedef uint32_t __attribute__((vector_size(8)))  vect64_t;\n\n#undef osSignalWait\n\n__attribute__((pcs(\"aapcs\")))\nvect64_t  osSignalWait (int32_t signals, uint32_t millisec);\n\nosEvent __osSignalWait (int32_t signals, uint32_t millisec) {\n  vect64_t v;\n  osEvent  e;\n  \n  v = osSignalWait(signals, millisec);\n  e.status  = v[0];\n  e.value.v = v[1];\n\n  return e;\n}\n\n#undef osMessageGet\n\n__attribute__((pcs(\"aapcs\")))\nvect64_t  osMessageGet (osMessageQId queue_id, uint32_t millisec);\n\nosEvent __osMessageGet (osMessageQId queue_id, uint32_t millisec) {\n  vect64_t v;\n  osEvent  e;\n  \n  v = osMessageGet(queue_id, millisec);\n  e.status  = v[0];\n  e.value.v = v[1];\n\n  return e;\n}\n\n#undef osMailGet\n\n__attribute__((pcs(\"aapcs\")))\nvect64_t  osMailGet (osMailQId queue_id, uint32_t millisec);\n\nosEvent __osMailGet (osMailQId queue_id, uint32_t millisec) {\n  vect64_t v;\n  osEvent  e;\n  \n  v = osMailGet(queue_id, millisec);\n  e.status  = v[0];\n  e.value.v = v[1];\n\n  return e;\n}\n\n#endif\n\n/*----------------------------------------------------------------------------\n *      RTX Startup\n *---------------------------------------------------------------------------*/\n\n/* Main Thread definition */\nextern int main (void);\nextern\nconst osThreadDef_t os_thread_def_main;\nconst osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 1U, 4*OS_MAINSTKSIZE };\n\n\n#if defined (__CC_ARM)\n\n#ifdef __MICROLIB\n__attribute__((section(\".ARM.Collect$$$$000000FF\")))\nvoid _main_init (void);\nvoid _main_init (void) {\n  osKernelInitialize();\n  osThreadCreate(&os_thread_def_main, NULL);\n  osKernelStart();\n  for (;;);\n}\n#else\n__asm void _platform_post_lib_init (void) {\n\n  IMPORT  os_thread_def_main\n  IMPORT  osKernelInitialize\n  IMPORT  osKernelStart\n  IMPORT  osThreadCreate\n  IMPORT  exit\n\n  ADD     SP,#0x10\n  BL      osKernelInitialize\n  LDR     R0,=os_thread_def_main\n  MOVS    R1,#0\n  BL      osThreadCreate\n  BL      osKernelStart\n  BL      exit\n\n  ALIGN\n}\n#endif\n\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n\n#ifdef __MICROLIB\n__attribute__((noreturn, section(\".ARM.Collect$$$$000000FF\")))\nvoid _main_init (void);\nvoid _main_init (void) {\n#else\n__asm(\" .global __ARM_use_no_argv\\n\");\n__attribute__((noreturn))\nvoid _platform_post_lib_init (void);\nvoid _platform_post_lib_init (void) {\n#endif\n  osKernelInitialize();\n  osThreadCreate(&os_thread_def_main, NULL);\n  osKernelStart();\n  for (;;);\n}\n\n#elif defined (__GNUC__)\n\n#ifdef __CS3__\n\n/* CS3 start_c routine.\n *\n * Copyright (c) 2006, 2007 CodeSourcery Inc\n *\n * The authors hereby grant permission to use, copy, modify, distribute,\n * and license this software and its documentation for any purpose, provided\n * that existing copyright notices are retained in all copies and that this\n * notice is included verbatim in any distributions. No written agreement,\n * license, or royalty fee is required for any of the authorized uses.\n * Modifications to this software may be copyrighted by their authors\n * and need not follow the licensing terms described here, provided that\n * the new terms are clearly indicated on the first page of each file where\n * they apply.\n */\n\n#include \"cs3.h\"\n\nextern void __libc_init_array (void);\n\n__attribute ((noreturn)) void __cs3_start_c (void){\n  unsigned regions = __cs3_region_num;\n  const struct __cs3_region *rptr = __cs3_regions;\n\n  /* Initialize memory */\n  for (regions = __cs3_region_num, rptr = __cs3_regions; regions--; rptr++) {\n    long long *src = (long long *)rptr->init;\n    long long *dst = (long long *)rptr->data;\n    unsigned limit = rptr->init_size;\n    unsigned count;\n\n    if (src != dst)\n      for (count = 0; count != limit; count += sizeof (long long))\n        *dst++ = *src++;\n    else \n      dst = (long long *)((char *)dst + limit);\n    limit = rptr->zero_size;\n    for (count = 0; count != limit; count += sizeof (long long))\n      *dst++ = 0;\n  }\n\n  /* Run initializers.  */\n  __libc_init_array ();\n\n  osKernelInitialize();\n  osThreadCreate(&os_thread_def_main, NULL);\n  osKernelStart();\n  for (;;);\n}\n\n#else\n\n__attribute__((naked)) void software_init_hook (void) {\n  __asm (\n    \".syntax unified\\n\"\n    \".thumb\\n\"\n    \"movs r0,#0\\n\"\n    \"movs r1,#0\\n\"\n    \"mov  r4,r0\\n\"\n    \"mov  r5,r1\\n\"\n    \"ldr  r0,= __libc_fini_array\\n\"\n    \"bl   atexit\\n\"\n    \"bl   __libc_init_array\\n\"\n    \"mov  r0,r4\\n\"\n    \"mov  r1,r5\\n\"\n    \"bl   osKernelInitialize\\n\"\n    \"ldr  r0,=os_thread_def_main\\n\"\n    \"movs r1,#0\\n\"\n    \"bl   osThreadCreate\\n\"\n    \"bl   osKernelStart\\n\"\n    \"bl   exit\\n\"\n  );\n}\n\n#endif\n\n#elif defined (__ICCARM__)\n\nextern int  __low_level_init(void);\nextern void __iar_data_init3(void);\nextern void exit(int arg);\n\n__noreturn __stackless void __cmain(void) {\n  int a;\n  \n  if (__low_level_init() != 0) {\n    __iar_data_init3();\n  }\n  osKernelInitialize();\n  osThreadCreate(&os_thread_def_main, NULL);\n  a = osKernelStart();\n  exit(a);\n}\n\n#endif\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/INC/cmsis_os.h",
    "content": "/* ----------------------------------------------------------------------\n * $Date:        5. February 2013\n * $Revision:    V1.02\n *\n * Project:      CMSIS-RTOS API\n * Title:        cmsis_os.h RTX header file\n *\n * Version 0.02\n *    Initial Proposal Phase\n * Version 0.03\n *    osKernelStart added, optional feature: main started as thread\n *    osSemaphores have standard behavior\n *    osTimerCreate does not start the timer, added osTimerStart\n *    osThreadPass is renamed to osThreadYield\n * Version 1.01\n *    Support for C++ interface\n *     - const attribute removed from the osXxxxDef_t typedef's\n *     - const attribute added to the osXxxxDef macros\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\n *    Added: osKernelInitialize\n * Version 1.02\n *    Control functions for short timeouts in microsecond resolution:\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\n *    Removed: osSignalGet \n *----------------------------------------------------------------------------\n *\n * Copyright (c) 2013-2017 ARM LIMITED. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n\n#ifndef _CMSIS_OS_H\n#define _CMSIS_OS_H\n\n#define osCMSIS           0x10002U     ///< CMSIS-RTOS API version (main [31:16] .sub [15:0])\n\n#define osCMSIS_RTX     ((4<<16)|82)   ///< RTOS identification and version (main [31:16] .sub [15:0])\n\n#define osKernelSystemId \"RTX V4.82\"   ///< RTOS identification string\n\n\n#define osFeature_MainThread   1       ///< main can be thread\n#define osFeature_Pool         1       ///< Memory Pools available\n#define osFeature_MailQ        1       ///< Mail Queues available\n#define osFeature_MessageQ     1       ///< Message Queues available\n#define osFeature_Signals      16      ///< 16 Signal Flags available per thread\n#define osFeature_Semaphore    65535   ///< Maximum count for \\ref osSemaphoreCreate function\n#define osFeature_Wait         0       ///< osWait not available\n#define osFeature_SysTick      1       ///< osKernelSysTick functions available\n\n#if defined(__CC_ARM)\n#define os_InRegs __value_in_regs      // Compiler specific: force struct in registers\n#else\n#define os_InRegs\n#endif\n\n#if   defined(__CC_ARM)\n#define __NO_RETURN __declspec(noreturn)\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define __NO_RETURN __attribute__((noreturn))\n#elif defined(__GNUC__)\n#define __NO_RETURN __attribute__((noreturn))\n#elif defined(__ICCARM__)\n#define __NO_RETURN __noreturn\n#else\n#define __NO_RETURN\n#endif\n\n#include <stdint.h>\n#include <stddef.h>\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n\n// ==== Enumeration, structures, defines ====\n\n/// Priority used for thread control.\ntypedef enum  {\n  osPriorityIdle          = -3,          ///< priority: idle (lowest)\n  osPriorityLow           = -2,          ///< priority: low\n  osPriorityBelowNormal   = -1,          ///< priority: below normal\n  osPriorityNormal        =  0,          ///< priority: normal (default)\n  osPriorityAboveNormal   = +1,          ///< priority: above normal\n  osPriorityHigh          = +2,          ///< priority: high\n  osPriorityRealtime      = +3,          ///< priority: realtime (highest)\n  osPriorityError         =  0x84,       ///< system cannot determine priority or thread has illegal priority\n  os_priority_reserved    =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.\n} osPriority;\n\n/// Timeout value.\n#define osWaitForever     0xFFFFFFFFU    ///< wait forever timeout value\n\n/// Status code values returned by CMSIS-RTOS functions.\ntypedef enum  {\n  osOK                    =     0,       ///< function completed; no error or event occurred.\n  osEventSignal           =  0x08,       ///< function completed; signal event occurred.\n  osEventMessage          =  0x10,       ///< function completed; message event occurred.\n  osEventMail             =  0x20,       ///< function completed; mail event occurred.\n  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.\n  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.\n  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.\n  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.\n  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.\n  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.\n  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorValue            =  0x86,       ///< value of a parameter is out of range.\n  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.\n  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.\n} osStatus;\n\n\n/// Timer type value for the timer definition.\ntypedef enum  {\n  osTimerOnce             =     0,       ///< one-shot timer\n  osTimerPeriodic         =     1        ///< repeating timer\n} os_timer_type;\n\n/// Entry point of a thread.\ntypedef void (*os_pthread) (void const *argument);\n\n/// Entry point of a timer call back function.\ntypedef void (*os_ptimer) (void const *argument);\n\n// >>> the following data type definitions may shall adapted towards a specific RTOS\n\n/// Thread ID identifies the thread (pointer to a thread control block).\ntypedef struct os_thread_cb *osThreadId;\n\n/// Timer ID identifies the timer (pointer to a timer control block).\ntypedef struct os_timer_cb *osTimerId;\n\n/// Mutex ID identifies the mutex (pointer to a mutex control block).\ntypedef struct os_mutex_cb *osMutexId;\n\n/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).\ntypedef struct os_semaphore_cb *osSemaphoreId;\n\n/// Pool ID identifies the memory pool (pointer to a memory pool control block).\ntypedef struct os_pool_cb *osPoolId;\n\n/// Message ID identifies the message queue (pointer to a message queue control block).\ntypedef struct os_messageQ_cb *osMessageQId;\n\n/// Mail ID identifies the mail queue (pointer to a mail queue control block).\ntypedef struct os_mailQ_cb *osMailQId;\n\n\n/// Thread Definition structure contains startup information of a thread.\ntypedef struct os_thread_def  {\n  os_pthread               pthread;    ///< start address of thread function\n  osPriority             tpriority;    ///< initial thread priority\n  uint32_t               instances;    ///< maximum number of instances of that thread function\n  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size\n} osThreadDef_t;\n\n/// Timer Definition structure contains timer parameters.\ntypedef struct os_timer_def  {\n  os_ptimer                 ptimer;    ///< start address of a timer function\n  void                      *timer;    ///< pointer to internal data\n} osTimerDef_t;\n\n/// Mutex Definition structure contains setup information for a mutex.\ntypedef struct os_mutex_def  {\n  void                      *mutex;    ///< pointer to internal data\n} osMutexDef_t;\n\n/// Semaphore Definition structure contains setup information for a semaphore.\ntypedef struct os_semaphore_def  {\n  void                  *semaphore;    ///< pointer to internal data\n} osSemaphoreDef_t;\n\n/// Definition structure for memory block allocation.\ntypedef struct os_pool_def  {\n  uint32_t                 pool_sz;    ///< number of items (elements) in the pool\n  uint32_t                 item_sz;    ///< size of an item\n  void                       *pool;    ///< pointer to memory for pool\n} osPoolDef_t;\n\n/// Definition structure for message queue.\ntypedef struct os_messageQ_def  {\n  uint32_t                queue_sz;    ///< number of elements in the queue\n  void                       *pool;    ///< memory array for messages\n} osMessageQDef_t;\n\n/// Definition structure for mail queue.\ntypedef struct os_mailQ_def  {\n  uint32_t                queue_sz;    ///< number of elements in the queue\n  uint32_t                 item_sz;    ///< size of an item\n  void                       *pool;    ///< memory array for mail\n} osMailQDef_t;\n\n/// Event structure contains detailed information about an event.\ntypedef struct  {\n  osStatus                 status;     ///< status code: event or error information\n  union  {\n    uint32_t                    v;     ///< message as 32-bit value\n    void                       *p;     ///< message or mail as void pointer\n    int32_t               signals;     ///< signal flags\n  } value;                             ///< event value\n  union  {\n    osMailQId             mail_id;     ///< mail id obtained by \\ref osMailCreate\n    osMessageQId       message_id;     ///< message id obtained by \\ref osMessageCreate\n  } def;                               ///< event definition\n} osEvent;\n\n\n//  ==== Kernel Control Functions ====\n\n/// Initialize the RTOS Kernel for creating objects.\n/// \\return status code that indicates the execution status of the function.\nosStatus osKernelInitialize (void);\n\n/// Start the RTOS Kernel.\n/// \\return status code that indicates the execution status of the function.\nosStatus osKernelStart (void);\n\n/// Check if the RTOS kernel is already started.\n/// \\return 0 RTOS is not started, 1 RTOS is started.\nint32_t osKernelRunning(void);\n\n#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available\n\n/// \\cond INTERNAL_VARIABLES\nextern uint32_t const os_tickfreq;\nextern uint16_t const os_tickus_i;\nextern uint16_t const os_tickus_f;\n/// \\endcond\n\n/// Get the RTOS kernel system timer counter.\n/// \\return RTOS kernel system timer as 32-bit value \nuint32_t osKernelSysTick (void);\n\n/// The RTOS kernel system timer frequency in Hz.\n/// \\note Reflects the system timer setting and is typically defined in a configuration file.\n#define osKernelSysTickFrequency os_tickfreq\n\n/// Convert a microseconds value to a RTOS kernel system timer value.\n/// \\param         microsec     time value in microseconds.\n/// \\return time value normalized to the \\ref osKernelSysTickFrequency\n/*\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)\n*/\n#define osKernelSysTickMicroSec(microsec) ((microsec * os_tickus_i) + ((microsec * os_tickus_f) >> 16))\n\n#endif    // System Timer available\n\n//  ==== Thread Management ====\n\n/// Create a Thread Definition with function, priority, and stack requirements.\n/// \\param         name         name of the thread function.\n/// \\param         priority     initial priority of the thread function.\n/// \\param         instances    number of possible thread instances.\n/// \\param         stacksz      stack size (in bytes) requirements for the thread function.\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osThreadDef(name, priority, instances, stacksz)  \\\nextern const osThreadDef_t os_thread_def_##name\n#else                            // define the object\n#define osThreadDef(name, priority, instances, stacksz)  \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ (name), (priority), (instances), (stacksz)  }\n#endif\n\n/// Access a Thread definition.\n/// \\param         name          name of the thread definition object.\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osThread(name)  \\\n&os_thread_def_##name\n\n/// Create a thread and add it to Active Threads and set it to state READY.\n/// \\param[in]     thread_def    thread definition referenced with \\ref osThread.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);\n\n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId osThreadGetId (void);\n\n/// Terminate execution of a thread and remove it from Active Threads.\n/// \\param[in]     thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus osThreadTerminate (osThreadId thread_id);\n\n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\nosStatus osThreadYield (void);\n\n/// Change priority of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);\n\n/// Get current priority of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return current priority value of the thread function.\nosPriority osThreadGetPriority (osThreadId thread_id);\n\n\n//  ==== Generic Wait Functions ====\n\n/// Wait for Timeout (Time Delay).\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"Time delay\" value\n/// \\return status code that indicates the execution status of the function.\nosStatus osDelay (uint32_t millisec);\n\n#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available\n\n/// Wait for Signal, Message, Mail, or Timeout.\n/// \\param[in] millisec          \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return event that contains signal, message, or mail information or error code.\nos_InRegs osEvent osWait (uint32_t millisec);\n\n#endif  // Generic Wait available\n\n\n//  ==== Timer Management Functions ====\n/// Define a Timer object.\n/// \\param         name          name of the timer object.\n/// \\param         function      name of the timer call back function.\n#if defined (osObjectsExternal)  // object is external\n#define osTimerDef(name, function)  \\\nextern const osTimerDef_t os_timer_def_##name\n#else                            // define the object\n#define osTimerDef(name, function)  \\\nuint32_t os_timer_cb_##name[6]; \\\nconst osTimerDef_t os_timer_def_##name = \\\n{ (function), (os_timer_cb_##name) }\n#endif\n\n/// Access a Timer definition.\n/// \\param         name          name of the timer object.\n#define osTimer(name) \\\n&os_timer_def_##name\n\n/// Create a timer.\n/// \\param[in]     timer_def     timer object referenced with \\ref osTimer.\n/// \\param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer call back function.\n/// \\return timer ID for reference by other functions or NULL in case of error.\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);\n\n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"Time delay\" value of the timer.\n/// \\return status code that indicates the execution status of the function.\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec);\n\n/// Stop the timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\nosStatus osTimerStop (osTimerId timer_id);\n\n/// Delete a timer that was created by \\ref osTimerCreate.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\nosStatus osTimerDelete (osTimerId timer_id);\n\n\n//  ==== Signal Management ====\n\n/// Set the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that should be set.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\nint32_t osSignalSet (osThreadId thread_id, int32_t signals);\n\n/// Clear the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that shall be cleared.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.\nint32_t osSignalClear (osThreadId thread_id, int32_t signals);\n\n/// Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\n/// \\param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event flag information or error code.\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define   osSignalWait __osSignalWait\nosEvent __osSignalWait (int32_t signals, uint32_t millisec);\n#else\nos_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);\n#endif\n\n\n//  ==== Mutex Management ====\n\n/// Define a Mutex.\n/// \\param         name          name of the mutex object.\n#if defined (osObjectsExternal)  // object is external\n#define osMutexDef(name)  \\\nextern const osMutexDef_t os_mutex_def_##name\n#else                            // define the object\n#define osMutexDef(name)  \\\nuint32_t os_mutex_cb_##name[4] = { 0 }; \\\nconst osMutexDef_t os_mutex_def_##name = { (os_mutex_cb_##name) }\n#endif\n\n/// Access a Mutex definition.\n/// \\param         name          name of the mutex object.\n#define osMutex(name)  \\\n&os_mutex_def_##name\n\n/// Create and Initialize a Mutex object.\n/// \\param[in]     mutex_def     mutex definition referenced with \\ref osMutex.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def);\n\n/// Wait until a Mutex becomes available.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);\n\n/// Release a Mutex that was obtained by \\ref osMutexWait.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMutexRelease (osMutexId mutex_id);\n\n/// Delete a Mutex that was created by \\ref osMutexCreate.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMutexDelete (osMutexId mutex_id);\n\n\n//  ==== Semaphore Management Functions ====\n\n#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available\n\n/// Define a Semaphore object.\n/// \\param         name          name of the semaphore object.\n#if defined (osObjectsExternal)  // object is external\n#define osSemaphoreDef(name)  \\\nextern const osSemaphoreDef_t os_semaphore_def_##name\n#else                            // define the object\n#define osSemaphoreDef(name)  \\\nuint32_t os_semaphore_cb_##name[2] = { 0 }; \\\nconst osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) }\n#endif\n\n/// Access a Semaphore definition.\n/// \\param         name          name of the semaphore object.\n#define osSemaphore(name)  \\\n&os_semaphore_def_##name\n\n/// Create and Initialize a Semaphore object used for managing resources.\n/// \\param[in]     semaphore_def semaphore definition referenced with \\ref osSemaphore.\n/// \\param[in]     count         number of available resources.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);\n\n/// Wait until a Semaphore token becomes available.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return number of available tokens, or -1 in case of incorrect parameters.\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);\n\n/// Release a Semaphore token.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id);\n\n/// Delete a Semaphore that was created by \\ref osSemaphoreCreate.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id);\n\n#endif     // Semaphore available\n\n\n//  ==== Memory Pool Management Functions ====\n\n#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available\n\n/// \\brief Define a Memory Pool.\n/// \\param         name          name of the memory pool.\n/// \\param         no            maximum number of blocks (objects) in the memory pool.\n/// \\param         type          data type of a single block (object).\n#if defined (osObjectsExternal)  // object is external\n#define osPoolDef(name, no, type)   \\\nextern const osPoolDef_t os_pool_def_##name\n#else                            // define the object\n#define osPoolDef(name, no, type)   \\\nuint32_t os_pool_m_##name[3+((sizeof(type)+3)/4)*(no)]; \\\nconst osPoolDef_t os_pool_def_##name = \\\n{ (no), sizeof(type), (os_pool_m_##name) }\n#endif\n\n/// \\brief Access a Memory Pool definition.\n/// \\param         name          name of the memory pool\n#define osPool(name) \\\n&os_pool_def_##name\n\n/// Create and Initialize a memory pool.\n/// \\param[in]     pool_def      memory pool definition referenced with \\ref osPool.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\nosPoolId osPoolCreate (const osPoolDef_t *pool_def);\n\n/// Allocate a memory block from a memory pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolAlloc (osPoolId pool_id);\n\n/// Allocate a memory block from a memory pool and set memory block to zero.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolCAlloc (osPoolId pool_id);\n\n/// Return an allocated memory block back to a specific memory pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\param[in]     block         address of the allocated memory block that is returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\nosStatus osPoolFree (osPoolId pool_id, void *block);\n\n#endif   // Memory Pool Management available\n\n\n//  ==== Message Queue Management Functions ====\n\n#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available\n\n/// \\brief Create a Message Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of messages in the queue.\n/// \\param         type          data type of a single message element (for debugger).\n#if defined (osObjectsExternal)  // object is external\n#define osMessageQDef(name, queue_sz, type)   \\\nextern const osMessageQDef_t os_messageQ_def_##name\n#else                            // define the object\n#define osMessageQDef(name, queue_sz, type)   \\\nuint32_t os_messageQ_q_##name[4+(queue_sz)] = { 0 }; \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), (os_messageQ_q_##name) }\n#endif\n\n/// \\brief Access a Message Queue Definition.\n/// \\param         name          name of the queue\n#define osMessageQ(name) \\\n&os_messageQ_def_##name\n\n/// Create and Initialize a Message Queue.\n/// \\param[in]     queue_def     queue definition referenced with \\ref osMessageQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);\n\n/// Put a Message to a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     info          message information.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);\n\n/// Get a Message or Wait for a Message from a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define   osMessageGet __osMessageGet\nosEvent __osMessageGet (osMessageQId queue_id, uint32_t millisec);\n#else\nos_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);\n#endif\n\n#endif     // Message Queues available\n\n\n//  ==== Mail Queue Management Functions ====\n\n#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available\n\n/// \\brief Create a Mail Queue Definition.\n/// \\param         name          name of the queue\n/// \\param         queue_sz      maximum number of messages in queue\n/// \\param         type          data type of a single message element\n#if defined (osObjectsExternal)  // object is external\n#define osMailQDef(name, queue_sz, type) \\\nextern const osMailQDef_t os_mailQ_def_##name\n#else                            // define the object\n#define osMailQDef(name, queue_sz, type) \\\nuint32_t os_mailQ_q_##name[4+(queue_sz)] = { 0 }; \\\nuint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \\\nvoid *   os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \\\nconst osMailQDef_t os_mailQ_def_##name =  \\\n{ (queue_sz), sizeof(type), (os_mailQ_p_##name) }\n#endif\n\n/// \\brief Access a Mail Queue Definition.\n/// \\param         name          name of the queue\n#define osMailQ(name)  \\\n&os_mailQ_def_##name\n\n/// Create and Initialize mail queue.\n/// \\param[in]     queue_def     reference to the mail queue definition obtain with \\ref osMailQ\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return mail queue ID for reference by other functions or NULL in case of error.\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);\n\n/// Allocate a memory block from a mail.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec);\n\n/// Allocate a memory block from a mail and set memory block to zero.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec);\n\n/// Put a mail to a queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          memory block previously allocated with \\ref osMailAlloc or \\ref osMailCAlloc.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailPut (osMailQId queue_id, void *mail);\n\n/// Get a mail from a queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return event that contains mail information or error code.\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define   osMailGet __osMailGet\nosEvent __osMailGet (osMailQId queue_id, uint32_t millisec);\n#else\nos_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);\n#endif\n\n/// Free a memory block from a mail.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to the memory block that was obtained with \\ref osMailGet.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailFree (osMailQId queue_id, void *mail);\n\n#endif  // Mail Queues available\n\n\n//  ==== RTX Extensions ====\n\n/// Suspend the RTX task scheduler.\n/// \\return number of ticks, for how long the system can sleep or power-down.\nuint32_t os_suspend (void);\n\n/// Resume the RTX task scheduler.\n/// \\param[in]     sleep_time    specifies how long the system was in sleep or power-down mode.\nvoid os_resume (uint32_t sleep_time);\n\n/// OS idle demon (running when no other thread is ready to run).\n__NO_RETURN void os_idle_demon (void);\n\n/// OS error callback (called when a runtime error is detected).\n/// \\param[in]     error_code    actual error code that has been detected.\n__NO_RETURN void os_error (uint32_t error_code);\n\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif  // _CMSIS_OS_H\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/LIB/fetch_libs.sh",
    "content": "#!/bin/bash\n\nVERSION=4.82.0\nif [ -z \"$JENKINS_FAMILY_ENV\" ]; then\n    ARTIFACTORY_URL=https://artifactory.eu02.arm.com:443/artifactory/mcu.promoted\nelse\n    ARTIFACTORY_URL=https://eu-west-1.artifactory.aws.arm.com:443/artifactory/mcu.promoted\nfi\n\nif [ -z \"$ARTIFACTORY_API_KEY\" ]; then\n  echo \"Please set your Artifactory in ARTIFACTORY_API_KEY\"\n  echo \"\"\n  echo \"1. Browse to $(dirname $(dirname $ARTIFACTORY_URL))/ui/admin/artifactory/user_profile\"\n  echo \"2. Copy the API Key\"\n  echo \"3. Add 'export ARTIFACTORY_API_KEY=\\\"<API Key>\\\"' to ~/.bashrc\"\n  exit 1\nfi\n\nset -o pipefail\n\nfunction usage {\n  echo \"$(basename $0) [-h|--help] [-f|--force]\"\n  echo \"\"\n  echo \"Arguments:\"\n  echo \"  -h|--help   Print this usage message and exit.\"\n  echo \"  -f|--force  Force (re)download.\"\n  echo \"\"\n  echo \"Environment:\"\n  echo \" curl\"\n  echo \" sha256sum\"\n  echo \"\"\n}\n\nPOSITIONAL=()\nwhile [[ $# -gt 0 ]]\ndo\n  key=\"$1\"\n\n  case $key in\n    '-h'|'--help')\n      usage\n      exit 1\n    ;;\n    '-f'|'--force')\n      FORCE=1\n    ;;\n    *)    # unknown option\n      POSITIONAL+=(\"$1\") # save it in an array for later\n    ;;\n  esac\n  shift # past argument\ndone\nset -- \"${POSITIONAL[@]}\" # restore positional parameters\n\npushd $(dirname $0) > /dev/null\n\nARCHIVE_NAME=\"RTX-${VERSION}.zip\"\nARCHIVE_URL=\"${ARTIFACTORY_URL}/CMSIS_5/Libraries/${ARCHIVE_NAME}\"\necho \"Fetching ${ARCHIVE_URL}...\"\n\nif [[ $FORCE == 1 ]]; then\n    rm ${ARCHIVE_NAME}\nfi\n\nif [[ -f ${ARCHIVE_NAME} ]]; then\n    sha256sum=$(curl -s -I -H \"X-JFrog-Art-Api:${ARTIFACTORY_API_KEY}\" \"${ARCHIVE_URL}\" | grep \"X-Checksum-Sha256\" | cut -d\" \" -f2)\n    if echo \"${sha256sum} *${ARCHIVE_NAME}\" | sha256sum -c --status; then\n        echo \"Already up-to-date\"\n    else\n        rm ${ARCHIVE_NAME}\n    fi\nfi\n\nif [[ ! -f ${ARCHIVE_NAME} ]]; then\n    curl -C - -H \"X-JFrog-Art-Api:${ARTIFACTORY_API_KEY}\" -O \"${ARCHIVE_URL}\"\nfi\n\nunzip -u ${ARCHIVE_NAME}\n\nexit 0\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM0.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM0.C\n *      Purpose: Hardware Abstraction Layer for Cortex-M0\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_HAL_CM.h\"\n#include \"rt_Task.h\"\n#include \"rt_MemBox.h\"\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_set_PSP ------------------------------------*/\n\n__asm void rt_set_PSP (U32 stack) {\nMSR PSP, R0\nBX LR\n}\n\n\n/*--------------------------- rt_get_PSP ------------------------------------*/\n\n__asm U32 rt_get_PSP (void) {\nMRS R0, PSP\nBX LR\n}\n\n\n/*--------------------------- os_set_env ------------------------------------*/\n\n__asm void os_set_env (void) {\n/* Switch to Unprivileged/Privileged Thread mode, use PSP. */\nMOV R0, SP;\nPSP = MSP\nMSR PSP, R0\nLDR R0,\n=__cpp(&os_flags)\nLDRB R0,\n[R0]\nLSLS R0,\n#31\nBNE PrivilegedE\nMOVS R0,\n#0x03;\nUnprivileged Thread\nmode,\nuse PSP\nMSR CONTROL, R0\nBX LR\nPrivilegedE\n        MOVS\nR0,#0x02;\nPrivileged Thread\nmode,\nuse PSP\nMSR CONTROL, R0\nBX LR\n\nALIGN\n}\n\n\n/*--------------------------- _alloc_box ------------------------------------*/\n\n__asm void *_alloc_box (void *box_mem) {\n/* Function wrapper for Unprivileged/Privileged mode. */\nLDR R3,\n=\n__cpp(rt_alloc_box)\nMOV R12, R3\nMRS R3, IPSR\nLSLS R3,\n#24\nBNE PrivilegedA\nMRS R3, CONTROL\nLSLS R3,\n#31\nBEQ PrivilegedA\nSVC     0\nBX LR\nPrivilegedA\n        BX\nR12\n\n        ALIGN\n}\n\n\n/*--------------------------- _free_box -------------------------------------*/\n\n__asm U32 _free_box (void *box_mem, void *box) {\n/* Function wrapper for Unprivileged/Privileged mode. */\nLDR R3,\n=\n__cpp(rt_free_box)\nMOV R12, R3\nMRS R3, IPSR\nLSLS R3,\n#24\nBNE PrivilegedF\nMRS R3, CONTROL\nLSLS R3,\n#31\nBEQ PrivilegedF\nSVC     0\nBX LR\nPrivilegedF\n        BX\nR12\n\n        ALIGN\n}\n\n\n/*-------------------------- SVC_Handler ------------------------------------*/\n\n__asm void SVC_Handler (void) {\nPRESERVE8\n\n        IMPORT\nSVC_Count\n        IMPORT\nSVC_Table\n        IMPORT\nrt_stk_check\n\n        MRS\nR0,\nPSP;\nRead PSP\nLDR R1,\n[R0,#24];\nRead Saved\nPC from\nStack\n        SUBS\nR1,R1,#2;\nPoint to\nSVC Instruction\nLDRB R1,\n[R1];\nLoad SVC\nNumber\n        CMP\nR1,#0\nBNE SVC_User;\nUser SVC\nNumber > 0\n\nMOV LR, R4\nLDMIA R0,\n{\nR0-R3,R4};\nRead R0\n-R3,\nR12 from\nstack\n        MOV\nR12,\nR4\n        MOV\nR4,\nLR\n        BLX\nR12;\nCall SVC\nFunction\n\n        MRS\nR3,\nPSP;\nRead PSP\nSTMIA R3\n!,{\nR0-R2}; Store return\nvalues\n\n        LDR\nR3,=__cpp(&os_tsk)\nLDMIA R3\n!,{\nR1,R2}; os_tsk.run, os_tsk.\nnext\n        CMP\nR1,\nR2\n        BEQ\nSVC_Exit;\nno task\nswitch\n\nSUBS R3,\n#8\nCMP R1,\n#0;\nRuntask deleted\n?\nBEQ SVC_Next\n\nMRS R0, PSP;\nRead PSP\nSUBS R0, R0,\n#32;\nAdjust Start\nAddress\n        STR\nR0,[R1,#TCB_TSTACK];\nUpdate os_tsk\n.run->\ntsk_stack\n        STMIA\nR0!,{\nR4-R7};\nSave old\ncontext (R4\n-R7)\nMOV R4, R8\nMOV R5, R9\nMOV R6, R10\nMOV R7, R11\nSTMIA R0\n!,{\nR4-R7};\nSave old\ncontext (R8\n-R11)\n\nPUSH    {\nR2,R3}\nBL rt_stk_check;\nCheck for\nStack overflow\nPOP     {\nR2,R3}\n\nSVC_Next\n        STR\nR2,[R3]; os_tsk.\nrun = os_tsk.next\n\nLDR R0,\n[R2,#TCB_TSTACK]; os_tsk.next->\ntsk_stack\n        ADDS\nR0,R0,#16;\nAdjust Start\nAddress\n        LDMIA\nR0!,{\nR4-R7};\nRestore new\nContext (R8\n-R11)\nMOV R8, R4\nMOV R9, R5\nMOV R10, R6\nMOV R11, R7\nMSR PSP, R0;\nWrite PSP\nSUBS R0, R0,\n#32;\nAdjust Start\nAddress\n        LDMIA\nR0!,{\nR4-R7};\nRestore new\nContext (R4\n-R7)\n\nSVC_Exit\n        MOVS\nR0,#:NOT:0xFFFFFFFD;\nSet EXC_RETURN\nvalue\n        MVNS\nR0,\nR0\n        BX\nR0;\nRETI to\nThread Mode, use\nPSP\n\n/*------------------- User SVC ------------------------------*/\n\nSVC_User\nPUSH    {\nR4,LR};\nSave Registers\nLDR R2,\n=\nSVC_Count\n        LDR\nR2,[R2]\nCMP R1, R2\nBHI SVC_Done;\nOverflow\n\n        LDR\nR4,=SVC_Table-4\nLSLS R1, R1,\n#2\nLDR R4,\n[R4,R1];\nLoad SVC\nFunction Address\nMOV LR, R4\n\nLDMIA R0,\n{\nR0-R3,R4};\nRead R0\n-R3,\nR12 from\nstack\n        MOV\nR12,\nR4\n        BLX\nLR;\nCall SVC\nFunction\n\n        MRS\nR4,\nPSP;\nRead PSP\nSTMIA R4\n!,{\nR0-R3}; Function return\nvalues\n        SVC_Done\nPOP     {\nR4,PC};\nRETI\n\n        ALIGN\n}\n\n\n/*-------------------------- PendSV_Handler ---------------------------------*/\n\n__asm void PendSV_Handler (void) {\nPRESERVE8\n\n        BL\n__cpp(rt_pop_req)\n\nSys_Switch\n        LDR\nR3,=__cpp(&os_tsk)\nLDMIA R3\n!,{\nR1,R2}; os_tsk.run, os_tsk.\nnext\n        CMP\nR1,\nR2\n        BEQ\nSys_Exit;\nno task\nswitch\n\nSUBS R3,\n#8\n\nMRS R0, PSP;\nRead PSP\nSUBS R0, R0,\n#32;\nAdjust Start\nAddress\n        STR\nR0,[R1,#TCB_TSTACK];\nUpdate os_tsk\n.run->\ntsk_stack\n        STMIA\nR0!,{\nR4-R7};\nSave old\ncontext (R4\n-R7)\nMOV R4, R8\nMOV R5, R9\nMOV R6, R10\nMOV R7, R11\nSTMIA R0\n!,{\nR4-R7};\nSave old\ncontext (R8\n-R11)\n\nPUSH    {\nR2,R3}\nBL rt_stk_check;\nCheck for\nStack overflow\nPOP     {\nR2,R3}\n\nSTR R2,\n[R3]; os_tsk.\nrun = os_tsk.next\n\nLDR R0,\n[R2,#TCB_TSTACK]; os_tsk.next->\ntsk_stack\n        ADDS\nR0,R0,#16;\nAdjust Start\nAddress\n        LDMIA\nR0!,{\nR4-R7};\nRestore new\nContext (R8\n-R11)\nMOV R8, R4\nMOV R9, R5\nMOV R10, R6\nMOV R11, R7\nMSR PSP, R0;\nWrite PSP\nSUBS R0, R0,\n#32;\nAdjust Start\nAddress\n        LDMIA\nR0!,{\nR4-R7};\nRestore new\nContext (R4\n-R7)\n\nSys_Exit\n        MOVS\nR0,#:NOT:0xFFFFFFFD;\nSet EXC_RETURN\nvalue\n        MVNS\nR0,\nR0\n        BX\nR0;\nRETI to\nThread Mode, use\nPSP\n\n        ALIGN\n}\n\n\n/*-------------------------- SysTick_Handler --------------------------------*/\n\n__asm void SysTick_Handler (void) {\nPRESERVE8\n\n        BL\n__cpp(rt_systick)\nB Sys_Switch\n\nALIGN\n}\n\n\n/*-------------------------- OS_Tick_Handler --------------------------------*/\n\n__asm void OS_Tick_Handler (void) {\nPRESERVE8\n\n        BL\n__cpp(os_tick_irqack)\n\nBL __cpp(rt_systick)\n\nB Sys_Switch\n\nALIGN\n}\n\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM3.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM3.C\n *      Purpose: Hardware Abstraction Layer for Cortex-M3\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_HAL_CM.h\"\n#include \"rt_Task.h\"\n#include \"rt_MemBox.h\"\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_set_PSP ------------------------------------*/\n\n__asm void rt_set_PSP (U32 stack) {\nMSR PSP, R0\nBX LR\n}\n\n\n/*--------------------------- rt_get_PSP ------------------------------------*/\n\n__asm U32 rt_get_PSP (void) {\nMRS R0, PSP\nBX LR\n}\n\n\n/*--------------------------- os_set_env ------------------------------------*/\n\n__asm void os_set_env (void) {\n/* Switch to Unprivileged/Privileged Thread mode, use PSP. */\nMOV R0, SP;\nPSP = MSP\nMSR PSP, R0\nLDR R0,\n=__cpp(&os_flags)\nLDRB R0,\n[R0]\nLSLS R0,\n#31\nMOVNE R0,\n#0x02;\nPrivileged Thread\nmode,\nuse PSP\nMOVEQ R0,\n#0x03;\nUnprivileged Thread\nmode,\nuse PSP\nMSR CONTROL, R0\nBX LR\n\nALIGN\n}\n\n\n/*--------------------------- _alloc_box ------------------------------------*/\n\n__asm void *_alloc_box (void *box_mem) {\n/* Function wrapper for Unprivileged/Privileged mode. */\nLDR R12,\n=\n__cpp(rt_alloc_box)\nMRS R3, IPSR\nLSLS R3,\n#24\nBXNE R12\nMRS R3, CONTROL\nLSLS R3,\n#31\nBXEQ R12\nSVC     0\nBX LR\n\nALIGN\n}\n\n\n/*--------------------------- _free_box -------------------------------------*/\n\n__asm U32 _free_box (void *box_mem, void *box) {\n/* Function wrapper for Unprivileged/Privileged mode. */\nLDR R12,\n=\n__cpp(rt_free_box)\nMRS R3, IPSR\nLSLS R3,\n#24\nBXNE R12\nMRS R3, CONTROL\nLSLS R3,\n#31\nBXEQ R12\nSVC     0\nBX LR\n\nALIGN\n}\n\n\n/*-------------------------- SVC_Handler ------------------------------------*/\n\n__asm void SVC_Handler (void) {\nPRESERVE8\n\n        IMPORT\nSVC_Count\n        IMPORT\nSVC_Table\n        IMPORT\nrt_stk_check\n\n#ifdef  IFX_XMC4XXX\nEXPORT  SVC_Handler_Veneer\nSVC_Handler_Veneer\n#endif\n\n        MRS\nR0,\nPSP;\nRead PSP\nLDR R1,\n[R0,#24];\nRead Saved\nPC from\nStack\n        LDRB\nR1,[R1,#-2];\nLoad SVC\nNumber\n        CBNZ\nR1,\nSVC_User\n\n        LDM\nR0,{\nR0-R3,R12};\nRead R0\n-R3,\nR12 from\nstack\n        BLX\nR12;\nCall SVC\nFunction\n\n        MRS\nR12,\nPSP;\nRead PSP\nSTM R12,\n{\nR0-R2}; Store return\nvalues\n\n        LDR\nR3,=\n\n__cpp(\n\n&os_tsk)\nLDM R3,\n{\nR1,R2}; os_tsk.run, os_tsk.\nnext\n        CMP\nR1,\nR2\n        BEQ\nSVC_Exit;\nno task\nswitch\n\nCBZ R1, SVC_Next;\nRuntask deleted\n?\nSTMDB R12\n!,{\nR4-R11};\nSave Old\ncontext\n        STR\nR12,[R1,#TCB_TSTACK];\nUpdate os_tsk\n.run->\ntsk_stack\n\n        PUSH{R2, R3}\nBL rt_stk_check;\nCheck for\nStack overflow\nPOP     {\nR2,R3}\n\nSVC_Next\n        STR\nR2,[R3]; os_tsk.\nrun = os_tsk.next\n\nLDR R12,\n[R2,#TCB_TSTACK]; os_tsk.next->\ntsk_stack\n        LDMIA\nR12!,{\nR4-R11};\nRestore New\nContext\n        MSR\nPSP,\nR12;\nWrite PSP\n\nSVC_Exit\n        MVN\nLR,#:NOT:0xFFFFFFFD;\nset EXC_RETURN\nvalue\n#ifdef  IFX_XMC4XXX\nPUSH    {LR}\nPOP     {PC}\n#else\n        BX\nLR\n#endif\n\n/*------------------- User SVC ------------------------------*/\n\nSVC_User\nPUSH    {\nR4,LR};\nSave Registers\nLDR R2,\n=\nSVC_Count\n        LDR\nR2,[R2]\nCMP R1, R2\nBHI SVC_Done;\nOverflow\n\n        LDR\nR4,=SVC_Table-4\nLDR R4,\n[R4,R1,LSL #2];\nLoad SVC\nFunction Address\n\nLDM R0,\n{\nR0-R3,R12};\nRead R0\n-R3,\nR12 from\nstack\n        BLX\nR4;\nCall SVC\nFunction\n\n        MRS\nR12,\nPSP\n        STM\nR12,{\nR0-R3}; Function return\nvalues\n        SVC_Done\nPOP     {\nR4,PC};\nRETI\n\n        ALIGN\n}\n\n\n/*-------------------------- PendSV_Handler ---------------------------------*/\n\n__asm void PendSV_Handler (void) {\nPRESERVE8\n\n#ifdef  IFX_XMC4XXX\nEXPORT  PendSV_Handler_Veneer\nPendSV_Handler_Veneer\n#endif\n\n        BL\n__cpp(rt_pop_req)\n\nSys_Switch\n        LDR\nR3,=\n\n__cpp(\n\n&os_tsk)\nLDM R3,\n{\nR1,R2}; os_tsk.run, os_tsk.\nnext\n        CMP\nR1,\nR2\n        BEQ\nSys_Exit\n\n        MRS\nR12,\nPSP;\nRead PSP\nSTMDB R12\n!,{\nR4-R11};\nSave Old\ncontext\n        STR\nR12,[R1,#TCB_TSTACK];\nUpdate os_tsk\n.run->\ntsk_stack\n\n        PUSH{R2, R3}\nBL rt_stk_check;\nCheck for\nStack overflow\nPOP     {\nR2,R3}\n\nSTR R2,\n[R3]; os_tsk.\nrun = os_tsk.next\n\nLDR R12,\n[R2,#TCB_TSTACK]; os_tsk.next->\ntsk_stack\n        LDMIA\nR12!,{\nR4-R11};\nRestore New\nContext\n        MSR\nPSP,\nR12;\nWrite PSP\n\nSys_Exit\n        MVN\nLR,#:NOT:0xFFFFFFFD;\nset EXC_RETURN\nvalue\n#ifdef  IFX_XMC4XXX\nPUSH    {LR}\nPOP     {PC}\n#else\n        BX\nLR;\nReturn to\nThread Mode\n#endif\n\nALIGN\n}\n\n\n/*-------------------------- SysTick_Handler --------------------------------*/\n\n__asm void SysTick_Handler (void) {\nPRESERVE8\n\n#ifdef  IFX_XMC4XXX\nEXPORT  SysTick_Handler_Veneer\nSysTick_Handler_Veneer\n#endif\n\n        BL\n__cpp(rt_systick)\nB Sys_Switch\n\nALIGN\n}\n\n\n/*-------------------------- OS_Tick_Handler --------------------------------*/\n\n__asm void OS_Tick_Handler (void) {\nPRESERVE8\n\n        BL\n__cpp(os_tick_irqack)\n\nBL __cpp(rt_systick)\n\nB Sys_Switch\n\nALIGN\n}\n\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM4.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM4.C\n *      Purpose: Hardware Abstraction Layer for Cortex-M4\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_HAL_CM.h\"\n#include \"rt_Task.h\"\n#include \"rt_MemBox.h\"\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_set_PSP ------------------------------------*/\n\n__asm void rt_set_PSP (U32 stack) {\nMSR PSP, R0\nBX LR\n}\n\n\n/*--------------------------- rt_get_PSP ------------------------------------*/\n\n__asm U32 rt_get_PSP (void) {\nMRS R0, PSP\nBX LR\n}\n\n\n/*--------------------------- os_set_env ------------------------------------*/\n\n__asm void os_set_env (void) {\n/* Switch to Unprivileged/Privileged Thread mode, use PSP. */\nMOV R0, SP;\nPSP = MSP\nMSR PSP, R0\nLDR R0,\n=__cpp(&os_flags)\nLDRB R0,\n[R0]\nLSLS R0,\n#31\nMOVNE R0,\n#0x02;\nPrivileged Thread\nmode,\nuse PSP\nMOVEQ R0,\n#0x03;\nUnprivileged Thread\nmode,\nuse PSP\nMSR CONTROL, R0\nBX LR\n\nALIGN\n}\n\n\n/*--------------------------- _alloc_box ------------------------------------*/\n\n__asm void *_alloc_box (void *box_mem) {\n/* Function wrapper for Unprivileged/Privileged mode. */\nLDR R12,\n=\n__cpp(rt_alloc_box)\nMRS R3, IPSR\nLSLS R3,\n#24\nBXNE R12\nMRS R3, CONTROL\nLSLS R3,\n#31\nBXEQ R12\nSVC     0\nBX LR\n\nALIGN\n}\n\n\n/*--------------------------- _free_box -------------------------------------*/\n\n__asm U32 _free_box (void *box_mem, void *box) {\n/* Function wrapper for Unprivileged/Privileged mode. */\nLDR R12,\n=\n__cpp(rt_free_box)\nMRS R3, IPSR\nLSLS R3,\n#24\nBXNE R12\nMRS R3, CONTROL\nLSLS R3,\n#31\nBXEQ R12\nSVC     0\nBX LR\n\nALIGN\n}\n\n\n/*-------------------------- SVC_Handler ------------------------------------*/\n\n__asm void SVC_Handler (void) {\nPRESERVE8\n\n        IMPORT\nSVC_Count\n        IMPORT\nSVC_Table\n        IMPORT\nrt_stk_check\n\n#ifdef  IFX_XMC4XXX\nEXPORT  SVC_Handler_Veneer\nSVC_Handler_Veneer\n#endif\n\n        MRS\nR0,\nPSP;\nRead PSP\nLDR R1,\n[R0,#24];\nRead Saved\nPC from\nStack\n        LDRB\nR1,[R1,#-2];\nLoad SVC\nNumber\n        CBNZ\nR1,\nSVC_User\n\n        LDM\nR0,{\nR0-R3,R12};\nRead R0\n-R3,\nR12 from\nstack\n        PUSH{R4, LR};\nSave EXC_RETURN\nBLX R12;\nCall SVC\nFunction\n        POP{R4, LR};\nRestore EXC_RETURN\n\nMRS R12, PSP;\nRead PSP\nSTM R12,\n{\nR0-R2}; Store return\nvalues\n\n        LDR\nR3,=\n\n__cpp(\n\n&os_tsk)\nLDM R3,\n{\nR1,R2}; os_tsk.run, os_tsk.\nnext\n        CMP\nR1,\nR2\n#ifdef  IFX_XMC4XXX\nPUSHEQ  {LR}\nPOPEQ   {PC}\n#else\n        BXEQ\nLR;\nRETI,\nno task\nswitch\n#endif\n\nCBNZ R1, SVC_ContextSave;\nRuntask not\ndeleted?\n\nTST LR,\n#0x10;\nis it\nextended frame\n?\nBNE SVC_ContextRestore\nLDR R1,\n=0xE000EF34\nLDR R0,\n[R1];\nLoad FPCCR\nBIC R0,\n#1;\n\nClear LSPACT(Lazy state)\n        STR R0, [R1]; Store FPCCR\n\nB SVC_ContextRestore\n\nSVC_ContextSave\n        TST\nLR,#0x10;\nis it\nextended frame\n?\nVSTMDBEQ R12\n!,{\nS16-S31}; yes,\nstack also\nVFP hi\n-\nregs\n        MOVEQ\nR0,#0x01; os_tsk->\nstack_frame val\nMOVNE R0,\n#0x00\nSTRB R0,\n[R1,#TCB_STACKF]; os_tsk.run->\nstack_frame = val\nSTMDB R12\n!,{\nR4-R11};\nSave Old\ncontext\n        STR\nR12,[R1,#TCB_TSTACK];\nUpdate os_tsk\n.run->\ntsk_stack\n\n        PUSH{R2, R3}\nBL rt_stk_check;\nCheck for\nStack overflow\nPOP     {\nR2,R3}\n\nSVC_ContextRestore\n        STR\nR2,[R3]; os_tsk.\nrun = os_tsk.next\n\nLDR R12,\n[R2,#TCB_TSTACK]; os_tsk.next->\ntsk_stack\n        LDMIA\nR12!,{\nR4-R11};\nRestore New\nContext\n        LDRB\nR0,[R2,#TCB_STACKF];\nStack Frame\nCMP R0,\n#0; Basic/\nExtended Stack\nFrame\n        MVNEQ\nLR,#:NOT:0xFFFFFFFD;\nset EXC_RETURN\nvalue\n        MVNNE\nLR,#:NOT:0xFFFFFFED\nVLDMIANE R12\n!,{\nS16-S31};\nrestore VFP\nhi-\nregisters\n        MSR\nPSP,\nR12;\nWrite PSP\n\nSVC_Exit\n#ifdef  IFX_XMC4XXX\nPUSH    {LR}\nPOP     {PC}\n#else\n        BX\nLR\n#endif\n\n/*------------------- User SVC ------------------------------*/\n\nSVC_User\nPUSH    {\nR4,LR};\nSave Registers\nLDR R2,\n=\nSVC_Count\n        LDR\nR2,[R2]\nCMP R1, R2\nBHI SVC_Done;\nOverflow\n\n        LDR\nR4,=SVC_Table-4\nLDR R4,\n[R4,R1,LSL #2];\nLoad SVC\nFunction Address\n\nLDM R0,\n{\nR0-R3,R12};\nRead R0\n-R3,\nR12 from\nstack\n        BLX\nR4;\nCall SVC\nFunction\n\n        MRS\nR12,\nPSP\n        STM\nR12,{\nR0-R3}; Function return\nvalues\n        SVC_Done\nPOP     {\nR4,PC};\nRETI\n\n        ALIGN\n}\n\n\n/*-------------------------- PendSV_Handler ---------------------------------*/\n\n__asm void PendSV_Handler (void) {\nPRESERVE8\n\n#ifdef  IFX_XMC4XXX\nEXPORT  PendSV_Handler_Veneer\nPendSV_Handler_Veneer\n#endif\n\n        PUSH{R4, LR};\nSave EXC_RETURN\n\nBL __cpp(rt_pop_req)\n\n        Sys_Switch\n        POP{R4, LR}; Restore EXC_RETURN\n\nLDR R3,\n=\n\n__cpp(\n\n&os_tsk)\nLDM R3,\n{\nR1,R2}; os_tsk.run, os_tsk.\nnext\n        CMP\nR1,\nR2\n#ifdef  IFX_XMC4XXX\nPUSHEQ  {LR}\nPOPEQ   {PC}\n#else\n        BXEQ\nLR;\nRETI,\nno task\nswitch\n#endif\n\nMRS R12, PSP;\nRead PSP\nTST LR,\n#0x10;\nis it\nextended frame\n?\nVSTMDBEQ R12\n!,{\nS16-S31}; yes,\nstack also\nVFP hi\n-\nregs\n        MOVEQ\nR0,#0x01; os_tsk->\nstack_frame val\nMOVNE R0,\n#0x00\nSTRB R0,\n[R1,#TCB_STACKF]; os_tsk.run->\nstack_frame = val\nSTMDB R12\n!,{\nR4-R11};\nSave Old\ncontext\n        STR\nR12,[R1,#TCB_TSTACK];\nUpdate os_tsk\n.run->\ntsk_stack\n\n        PUSH{R2, R3}\nBL rt_stk_check;\nCheck for\nStack overflow\nPOP     {\nR2,R3}\n\nSTR R2,\n[R3]; os_tsk.\nrun = os_tsk.next\n\nLDR R12,\n[R2,#TCB_TSTACK]; os_tsk.next->\ntsk_stack\n        LDMIA\nR12!,{\nR4-R11};\nRestore New\nContext\n        LDRB\nR0,[R2,#TCB_STACKF];\nStack Frame\nCMP R0,\n#0; Basic/\nExtended Stack\nFrame\n        MVNEQ\nLR,#:NOT:0xFFFFFFFD;\nset EXC_RETURN\nvalue\n        MVNNE\nLR,#:NOT:0xFFFFFFED\nVLDMIANE R12\n!,{\nS16-S31};\nrestore VFP\nhi-\nregs\n        MSR\nPSP,\nR12;\nWrite PSP\n\nSys_Exit\n#ifdef  IFX_XMC4XXX\nPUSH    {LR}\nPOP     {PC}\n#else\n        BX\nLR;\nReturn to\nThread Mode\n#endif\n\nALIGN\n}\n\n\n/*-------------------------- SysTick_Handler --------------------------------*/\n\n__asm void SysTick_Handler (void) {\nPRESERVE8\n\n#ifdef  IFX_XMC4XXX\nEXPORT  SysTick_Handler_Veneer\nSysTick_Handler_Veneer\n#endif\n\n        PUSH{R4, LR};\nSave EXC_RETURN\n\nBL __cpp(rt_systick)\n\nB Sys_Switch\n\nALIGN\n}\n\n\n/*-------------------------- OS_Tick_Handler --------------------------------*/\n\n__asm void OS_Tick_Handler (void) {\nPRESERVE8\n\n        PUSH{R4, LR};\nSave EXC_RETURN\n\nBL __cpp(os_tick_irqack)\n\nBL __cpp(rt_systick)\n\nB Sys_Switch\n\nALIGN\n}\n\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/ARM/RTX_Lib_CM.uvoptx",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectOpt xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_optx.xsd\">\n\n  <SchemaVersion>1.0</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Extensions>\n    <cExt>*.c</cExt>\n    <aExt>*.s*; *.src; *.a*</aExt>\n    <oExt>*.obj</oExt>\n    <lExt>*.lib</lExt>\n    <tExt>*.txt; *.h; *.inc</tExt>\n    <pExt>*.plm</pExt>\n    <CppX>*.cpp</CppX>\n    <nMigrate>0</nMigrate>\n  </Extensions>\n\n  <DaveTm>\n    <dwLowDateTime>0</dwLowDateTime>\n    <dwHighDateTime>0</dwHighDateTime>\n  </DaveTm>\n\n  <Target>\n    <TargetName>CM0_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>1</RunSim>\n        <RunTarget>0</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM0_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>1</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>0</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <nTsel>0</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>-UU0101L5E -O14 -S0 -C0 -N00(\"ARM Cortex-M3\") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM0$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>1</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <Lin2Executable></Lin2Executable>\n      <Lin2ConfigFile></Lin2ConfigFile>\n      <bLin2Auto>0</bLin2Auto>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>CM0_BE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>1</RunSim>\n        <RunTarget>0</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM0_BE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>0</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <nTsel>1</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>-UU0101L5E -O14 -S0 -C0 -N00(\"ARM Cortex-M3\") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM0$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>1</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <Lin2Executable></Lin2Executable>\n      <Lin2ConfigFile></Lin2ConfigFile>\n      <bLin2Auto>0</bLin2Auto>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>CM3_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>1</RunSim>\n        <RunTarget>0</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM3_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>0</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <nTsel>1</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>-UU0101L5E -O14 -S0 -C0 -N00(\"ARM Cortex-M3\") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>1</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <Lin2Executable></Lin2Executable>\n      <Lin2ConfigFile></Lin2ConfigFile>\n      <bLin2Auto>0</bLin2Auto>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>CM3_BE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>1</RunSim>\n        <RunTarget>0</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM3_BE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>0</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <nTsel>1</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>-UU0101L5E -O14 -S0 -C0 -N00(\"ARM Cortex-M3\") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>1</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <Lin2Executable></Lin2Executable>\n      <Lin2ConfigFile></Lin2ConfigFile>\n      <bLin2Auto>0</bLin2Auto>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>CM3_LE_IFX</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>1</RunSim>\n        <RunTarget>0</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM3_LE_IFX\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>0</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <nTsel>1</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>-UU0101L5E -O14 -S0 -C0 -N00(\"ARM Cortex-M3\") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>1</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <Lin2Executable></Lin2Executable>\n      <Lin2ConfigFile></Lin2ConfigFile>\n      <bLin2Auto>0</bLin2Auto>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>CM3X_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>1</RunSim>\n        <RunTarget>0</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM3X_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>0</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <nTsel>1</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>-UU0101L5E -O14 -S0 -C0 -N00(\"ARM Cortex-M3\") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>1</viewmode>\n        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<LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>0</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        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     <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>0</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>0</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <nTsel>1</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>-UU0101L5E -O14 -S0 -C0 -N00(\"ARM Cortex-M3\") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE 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        <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.s</FilePath>\n            </File>\n   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<CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    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       <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM4.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM0_BE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM0</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M0\") CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM0$Device\\ARM\\ARMCM0\\Include\\ARMCM0.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM0$Device\\ARM\\SVD\\ARMCM0.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM0_BE\\</OutputDirectory>\n          <OutputName>RTX_CM0_B</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM0_BE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM0_BE\\RTX_CM0_B.lib ..\\..\\LIB\\ARM</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  </SimDllArguments>\n          <SimDlgDll>DARMCM1.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> </TargetDllArguments>\n          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>2</DriverSelection>\n          </Flash1>\n          <bUseTDR>0</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>1</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>0</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M0\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>1</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>4</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>0</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <useXO>0</useXO>\n            <v6Lang>0</v6Lang>\n            <v6LangP>0</v6LangP>\n            <vShortEn>0</vShortEn>\n            <vShortWch>0</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CORTEX_M0 __CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <uClangAs>0</uClangAs>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n      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        <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.s</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM0.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM3.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM4.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM3_LE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM3</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M3\") CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM3$Device\\ARM\\ARMCM3\\Include\\ARMCM3.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM3$Device\\ARM\\SVD\\ARMCM3.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM3_LE\\</OutputDirectory>\n          <OutputName>RTX_CM3</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM3_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM3_LE\\RTX_CM3.lib ..\\..\\LIB\\ARM</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>2</DriverSelection>\n          </Flash1>\n          <bUseTDR>0</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>0</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M3\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>1</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>4</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>0</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <useXO>0</useXO>\n            <v6Lang>0</v6Lang>\n            <v6LangP>0</v6LangP>\n            <vShortEn>0</vShortEn>\n            <vShortWch>0</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls>--diag_suppress 3731</MiscControls>\n              <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <uClangAs>0</uClangAs>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.s</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM0.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM3.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM4.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM3_BE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM3</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M3\") CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM3$Device\\ARM\\ARMCM3\\Include\\ARMCM3.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM3$Device\\ARM\\SVD\\ARMCM3.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM3_BE\\</OutputDirectory>\n          <OutputName>RTX_CM3_B</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM3_BE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM3_BE\\RTX_CM3_B.lib ..\\..\\LIB\\ARM</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>2</DriverSelection>\n          </Flash1>\n          <bUseTDR>0</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>1</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>0</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M3\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>1</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>4</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>0</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <useXO>0</useXO>\n            <v6Lang>0</v6Lang>\n            <v6LangP>0</v6LangP>\n            <vShortEn>0</vShortEn>\n            <vShortWch>0</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls>--diag_suppress 3731</MiscControls>\n              <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <uClangAs>0</uClangAs>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.s</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM0.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM3.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM4.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM3_LE_IFX</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM3</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M3\") CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM3$Device\\ARM\\ARMCM3\\Include\\ARMCM3.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM3$Device\\ARM\\SVD\\ARMCM3.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM3_LE_IFX\\</OutputDirectory>\n          <OutputName>RTX_CM3_IFX</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM3_LE_IFX\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM3_LE_IFX\\RTX_CM3_IFX.lib ..\\..\\LIB\\ARM</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>2</DriverSelection>\n          </Flash1>\n          <bUseTDR>0</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>0</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M3\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>1</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>4</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>0</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <useXO>0</useXO>\n            <v6Lang>0</v6Lang>\n            <v6LangP>0</v6LangP>\n            <vShortEn>0</vShortEn>\n            <vShortWch>0</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls>--diag_suppress 3731</MiscControls>\n              <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <uClangAs>0</uClangAs>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.s</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM0.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM3.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define>IFX_XMC4XXX</Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM4.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM3X_LE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM3</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M3\") CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM3$Device\\ARM\\ARMCM3\\Include\\ARMCM3.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM3$Device\\ARM\\SVD\\ARMCM3.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM3X_LE\\</OutputDirectory>\n          <OutputName>RTX_CM3X</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM3X_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM3X_LE\\RTX_CM3X.lib ..\\..\\LIB\\ARM</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>0</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>2</DriverSelection>\n          </Flash1>\n          <bUseTDR>0</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>0</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M3\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>1</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>4</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>0</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <useXO>0</useXO>\n            <v6Lang>0</v6Lang>\n            <v6LangP>0</v6LangP>\n            <vShortEn>0</vShortEn>\n            <vShortWch>0</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG NO_EXCLUSIVE_ACCESS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <uClangAs>0</uClangAs>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.s</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM0.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM3.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM4.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM4F_LE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM4_FP</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M4\") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM4_FP$Device\\ARM\\ARMCM4\\Include\\ARMCM4_FP.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM4_FP$Device\\ARM\\SVD\\ARMCM4.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM4F_LE\\</OutputDirectory>\n          <OutputName>RTX_CM4</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM4F_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM4F_LE\\RTX_CM4.lib ..\\..\\LIB\\ARM</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>4097</DriverSelection>\n          </Flash1>\n          <bUseTDR>0</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>0</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M4\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>2</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>1</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x80000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x80000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>4</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>0</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <useXO>0</useXO>\n            <v6Lang>0</v6Lang>\n            <v6LangP>0</v6LangP>\n            <vShortEn>0</vShortEn>\n            <vShortWch>0</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls>--diag_suppress 3731</MiscControls>\n              <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <uClangAs>0</uClangAs>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.s</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM0.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM3.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM4.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM4F_BE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM4_FP</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M4\") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM4_FP$Device\\ARM\\ARMCM4\\Include\\ARMCM4_FP.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM4_FP$Device\\ARM\\SVD\\ARMCM4.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM4F_BE\\</OutputDirectory>\n          <OutputName>RTX_CM4_B</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM4F_BE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM4F_BE\\RTX_CM4_B.lib ..\\..\\LIB\\ARM</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>4097</DriverSelection>\n          </Flash1>\n          <bUseTDR>0</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>1</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>0</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M4\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>2</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>1</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x80000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x80000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>4</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>0</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <useXO>0</useXO>\n            <v6Lang>0</v6Lang>\n            <v6LangP>0</v6LangP>\n            <vShortEn>0</vShortEn>\n            <vShortWch>0</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls>--diag_suppress 3731</MiscControls>\n              <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <uClangAs>0</uClangAs>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.s</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM0.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM3.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM4.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM4F_LE_IFX</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM4_FP</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M4\") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM4_FP$Device\\ARM\\ARMCM4\\Include\\ARMCM4_FP.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM4_FP$Device\\ARM\\SVD\\ARMCM4.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM4F_LE_IFX\\</OutputDirectory>\n          <OutputName>RTX_CM4_IFX</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM4F_LE_IFX\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM4F_LE_IFX\\RTX_CM4_IFX.lib ..\\..\\LIB\\ARM</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>4097</DriverSelection>\n          </Flash1>\n          <bUseTDR>0</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>0</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M4\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>2</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>1</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x80000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x80000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>4</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>0</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <useXO>0</useXO>\n            <v6Lang>0</v6Lang>\n            <v6LangP>0</v6LangP>\n            <vShortEn>0</vShortEn>\n            <vShortWch>0</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls>--diag_suppress 3731</MiscControls>\n              <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <uClangAs>0</uClangAs>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.s</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.s</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM0.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM3.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\HAL_CM4.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Cads>\n                    <interw>2</interw>\n                    <Optim>0</Optim>\n                    <oTime>2</oTime>\n                    <SplitLS>2</SplitLS>\n                    <OneElfS>2</OneElfS>\n                    <Strict>2</Strict>\n                    <EnumInt>2</EnumInt>\n                    <PlainCh>2</PlainCh>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <uSurpInc>2</uSurpInc>\n                    <uC99>2</uC99>\n                    <useXO>2</useXO>\n                    <v6Lang>0</v6Lang>\n                    <v6LangP>0</v6LangP>\n                    <vShortEn>0</vShortEn>\n                    <vShortWch>0</vShortWch>\n                    <v6Lto>0</v6Lto>\n                    <v6WtE>0</v6WtE>\n                    <v6Rtti>2</v6Rtti>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define>IFX_XMC4XXX</Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\</IncludePath>\n                    </VariousControls>\n                  </Cads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis/>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"4.1.0\" condition=\"CMSIS Core\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"4.3.0\"/>\n        <targetInfos>\n          <targetInfo name=\"CM0_BE\"/>\n          <targetInfo name=\"CM0_LE\"/>\n          <targetInfo name=\"CM3X_LE\"/>\n          <targetInfo name=\"CM3_BE\"/>\n          <targetInfo name=\"CM3_LE\"/>\n          <targetInfo name=\"CM3_LE_IFX\"/>\n          <targetInfo name=\"CM4F_BE\"/>\n          <targetInfo name=\"CM4F_LE\"/>\n          <targetInfo name=\"CM4F_LE_IFX\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files/>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s",
    "content": ";/*----------------------------------------------------------------------------\n; *      CMSIS-RTOS  -  RTX\n; *----------------------------------------------------------------------------\n; *      Name:    SVC_TABLE.S\n; *      Purpose: Pre-defined SVC Table for Cortex-M\n; *      Rev.:    V4.70\n; *----------------------------------------------------------------------------\n; *\n; * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *---------------------------------------------------------------------------*/\n\n\n                AREA    SVC_TABLE, CODE, READONLY\n\n                EXPORT  SVC_Count\n\nSVC_Cnt         EQU    (SVC_End-SVC_Table)/4\nSVC_Count       DCD     SVC_Cnt\n\n; Import user SVC functions here.\n;               IMPORT  __SVC_1\n\n                EXPORT  SVC_Table\nSVC_Table\n; Insert user SVC functions here. SVC 0 used by RTL Kernel.\n;               DCD     __SVC_1                 ; user SVC function\n\nSVC_End\n\n                END\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM0.S",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM0.S\n *      Purpose: Hardware Abstraction Layer for Cortex-M0\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n        .syntax unified\n\n        .equ    TCB_TSTACK, 40\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n        .thumb\n\n        .section \".text\"\n        .align  2\n\n\n/*--------------------------- rt_set_PSP ------------------------------------*/\n\n#       void rt_set_PSP (U32 stack);\n\n        .thumb_func\n        .type   rt_set_PSP, %function\n        .global rt_set_PSP\nrt_set_PSP:\n        .fnstart\n        .cantunwind\n\n        MSR     PSP,R0\n        BX      LR\n\n        .fnend\n        .size   rt_set_PSP, .-rt_set_PSP\n\n\n/*--------------------------- rt_get_PSP ------------------------------------*/\n\n#       U32 rt_get_PSP (void);\n\n        .thumb_func\n        .type   rt_get_PSP, %function\n        .global rt_get_PSP\nrt_get_PSP:\n        .fnstart\n        .cantunwind\n\n        MRS     R0,PSP\n        BX      LR\n\n        .fnend\n        .size   rt_get_PSP, .-rt_get_PSP\n\n\n/*--------------------------- os_set_env ------------------------------------*/\n\n#       void os_set_env (void);\n        /* Switch to Unprivileged/Privileged Thread mode, use PSP. */\n\n        .thumb_func\n        .type   os_set_env, %function\n        .global os_set_env\nos_set_env:\n        .fnstart\n        .cantunwind\n\n        MOV     R0,SP                   /* PSP = MSP */\n        MSR     PSP,R0\n        LDR     R0,=os_flags\n        LDRB    R0,[R0]\n        LSLS    R0,#31\n        BNE     PrivilegedE\n        MOVS    R0,#0x03                /* Unprivileged Thread mode, use PSP */\n        MSR     CONTROL,R0\n        BX      LR\nPrivilegedE:\n        MOVS    R0,#0x02                /* Privileged Thread mode, use PSP */\n        MSR     CONTROL,R0\n        BX      LR\n\n        .fnend\n        .size   os_set_env, .-os_set_env\n\n\n/*--------------------------- _alloc_box ------------------------------------*/\n\n#      void *_alloc_box (void *box_mem);\n       /* Function wrapper for Unprivileged/Privileged mode. */\n\n        .thumb_func\n        .type   _alloc_box, %function\n        .global _alloc_box\n_alloc_box:\n        .fnstart\n        .cantunwind\n\n        LDR     R3,=rt_alloc_box\n        MOV     R12,R3\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        BNE     PrivilegedA\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        BEQ     PrivilegedA\n        SVC     0\n        BX      LR\nPrivilegedA:\n        BX      R12\n\n        .fnend\n        .size   _alloc_box, .-_alloc_box\n\n\n/*--------------------------- _free_box -------------------------------------*/\n\n#       U32 _free_box (void *box_mem, void *box);\n        /* Function wrapper for Unprivileged/Privileged mode. */\n\n        .thumb_func\n        .type   _free_box, %function\n        .global _free_box\n_free_box:\n        .fnstart\n        .cantunwind\n\n        LDR     R3,=rt_free_box\n        MOV     R12,R3\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        BNE     PrivilegedF\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        BEQ     PrivilegedF\n        SVC     0\n        BX      LR\nPrivilegedF:\n        BX      R12\n\n        .fnend\n        .size   _free_box, .-_free_box\n\n\n/*-------------------------- SVC_Handler ------------------------------------*/\n\n#       void SVC_Handler (void);\n\n        .thumb_func\n        .type   SVC_Handler, %function\n        .global SVC_Handler\nSVC_Handler:\n        .fnstart\n        .cantunwind\n\n        MRS     R0,PSP                  /* Read PSP */\n        LDR     R1,[R0,#24]             /* Read Saved PC from Stack */\n        SUBS    R1,R1,#2                /* Point to SVC Instruction */\n        LDRB    R1,[R1]                 /* Load SVC Number */\n        CMP     R1,#0\n        BNE     SVC_User                /* User SVC Number > 0 */\n\n        MOV     LR,R4\n        LDMIA   R0,{R0-R3,R4}           /* Read R0-R3,R12 from stack */\n        MOV     R12,R4\n        MOV     R4,LR\n        BLX     R12                     /* Call SVC Function */\n\n        MRS     R3,PSP                  /* Read PSP */\n        STMIA   R3!,{R0-R2}             /* Store return values */\n\n        LDR     R3,=os_tsk\n        LDMIA   R3!,{R1,R2}             /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        BEQ     SVC_Exit                /* no task switch */\n\n        SUBS    R3,#8\n        CMP     R1,#0                   /* Runtask deleted? */\n        BEQ     SVC_Next\n\n        MRS     R0,PSP                  /* Read PSP */\n        SUBS    R0,R0,#32               /* Adjust Start Address */\n        STR     R0,[R1,#TCB_TSTACK]     /* Update os_tsk.run->tsk_stack */       \n        STMIA   R0!,{R4-R7}             /* Save old context (R4-R7) */\n        MOV     R4,R8\n        MOV     R5,R9\n        MOV     R6,R10\n        MOV     R7,R11\n        STMIA   R0!,{R4-R7}             /* Save old context (R8-R11) */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\nSVC_Next:\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R0,[R2,#TCB_TSTACK]     /* os_tsk.next->tsk_stack */\n        ADDS    R0,R0,#16               /* Adjust Start Address */\n        LDMIA   R0!,{R4-R7}             /* Restore new Context (R8-R11) */\n        MOV     R8,R4\n        MOV     R9,R5\n        MOV     R10,R6\n        MOV     R11,R7\n        MSR     PSP,R0                  /* Write PSP */\n        SUBS    R0,R0,#32               /* Adjust Start Address */\n        LDMIA   R0!,{R4-R7}             /* Restore new Context (R4-R7) */\n\nSVC_Exit:\n        MOVS    R0,#~0xFFFFFFFD         /* Set EXC_RETURN value */\n        MVNS    R0,R0\n        BX      R0                      /* RETI to Thread Mode, use PSP */\n\n        /*------------------- User SVC ------------------------------*/\n\nSVC_User:\n        PUSH    {R4,LR}                 /* Save Registers */\n        LDR     R2,=SVC_Count\n        LDR     R2,[R2]\n        CMP     R1,R2\n        BHI     SVC_Done                /* Overflow */\n\n        LDR     R4,=SVC_Table-4\n        LSLS    R1,R1,#2\n        LDR     R4,[R4,R1]              /* Load SVC Function Address */\n        MOV     LR,R4\n\n        LDMIA   R0,{R0-R3,R4}           /* Read R0-R3,R12 from stack */\n        MOV     R12,R4\n        BLX     LR                      /* Call SVC Function */\n\n        MRS     R4,PSP                  /* Read PSP */\n        STMIA   R4!,{R0-R3}             /* Function return values */\nSVC_Done:\n        POP     {R4,PC}                 /* RETI */\n\n        .fnend\n        .size   SVC_Handler, .-SVC_Handler\n        \n\n/*-------------------------- PendSV_Handler ---------------------------------*/\n\n#       void PendSV_Handler (void);\n\n        .thumb_func\n        .type   PendSV_Handler, %function\n        .global PendSV_Handler\n        .global Sys_Switch\nPendSV_Handler:\n        .fnstart\n        .cantunwind\n\n        BL      rt_pop_req\n\nSys_Switch:\n        LDR     R3,=os_tsk\n        LDMIA   R3!,{R1,R2}             /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        BEQ     Sys_Exit                /* no task switch */\n\n        SUBS    R3,#8\n\n        MRS     R0,PSP                  /* Read PSP */\n        SUBS    R0,R0,#32               /* Adjust Start Address */\n        STR     R0,[R1,#TCB_TSTACK]     /* Update os_tsk.run->tsk_stack */\n        STMIA   R0!,{R4-R7}             /* Save old context (R4-R7) */\n        MOV     R4,R8\n        MOV     R5,R9\n        MOV     R6,R10\n        MOV     R7,R11\n        STMIA   R0!,{R4-R7}             /* Save old context (R8-R11) */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R0,[R2,#TCB_TSTACK]     /* os_tsk.next->tsk_stack */\n        ADDS    R0,R0,#16               /* Adjust Start Address */\n        LDMIA   R0!,{R4-R7}             /* Restore new Context (R8-R11) */\n        MOV     R8,R4\n        MOV     R9,R5\n        MOV     R10,R6\n        MOV     R11,R7\n        MSR     PSP,R0                  /* Write PSP */\n        SUBS    R0,R0,#32               /* Adjust Start Address */\n        LDMIA   R0!,{R4-R7}             /* Restore new Context (R4-R7) */\n\nSys_Exit:\n        MOVS    R0,#~0xFFFFFFFD         /* Set EXC_RETURN value */\n        MVNS    R0,R0\n        BX      R0                      /* RETI to Thread Mode, use PSP */\n\n        .fnend\n        .size   PendSV_Handler, .-PendSV_Handler\n\n\n/*-------------------------- SysTick_Handler --------------------------------*/\n\n#       void SysTick_Handler (void);\n\n        .thumb_func\n        .type   SysTick_Handler, %function\n        .global SysTick_Handler\nSysTick_Handler:\n        .fnstart\n        .cantunwind\n\n        BL      rt_systick\n        B       Sys_Switch\n\n        .fnend\n        .size   SysTick_Handler, .-SysTick_Handler\n\n\n/*-------------------------- OS_Tick_Handler --------------------------------*/\n\n#       void OS_Tick_Handler (void);\n\n        .thumb_func\n        .type   OS_Tick_Handler, %function\n        .global OS_Tick_Handler\nOS_Tick_Handler:\n        .fnstart\n        .cantunwind\n\n        BL      os_tick_irqack\n        BL      rt_systick\n        B       Sys_Switch\n\n        .fnend\n        .size   OS_Tick_Handler, .-OS_Tick_Handler\n\n\n        .end\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM3.S",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM3.S\n *      Purpose: Hardware Abstraction Layer for Cortex-M3\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n        .syntax unified\n\n        .equ    TCB_TSTACK, 40\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n        .thumb\n\n        .section \".text\"\n        .align  2\n\n\n/*--------------------------- rt_set_PSP ------------------------------------*/\n\n#       void rt_set_PSP (U32 stack);\n\n        .thumb_func\n        .type   rt_set_PSP, %function\n        .global rt_set_PSP\nrt_set_PSP:\n        .fnstart\n        .cantunwind\n\n        MSR     PSP,R0\n        BX      LR\n\n        .fnend\n        .size   rt_set_PSP, .-rt_set_PSP\n\n\n/*--------------------------- rt_get_PSP ------------------------------------*/\n\n#       U32 rt_get_PSP (void);\n\n        .thumb_func\n        .type   rt_get_PSP, %function\n        .global rt_get_PSP\nrt_get_PSP:\n        .fnstart\n        .cantunwind\n\n        MRS     R0,PSP\n        BX      LR\n\n        .fnend\n        .size   rt_get_PSP, .-rt_get_PSP\n\n\n/*--------------------------- os_set_env ------------------------------------*/\n\n#       void os_set_env (void);\n        /* Switch to Unprivileged/Privileged Thread mode, use PSP. */\n\n        .thumb_func\n        .type   os_set_env, %function\n        .global os_set_env\nos_set_env:\n        .fnstart\n        .cantunwind\n\n        MOV     R0,SP                   /* PSP = MSP */\n        MSR     PSP,R0\n        LDR     R0,=os_flags\n        LDRB    R0,[R0]\n        LSLS    R0,#31\n        ITE     NE\n        MOVNE   R0,#0x02                /* Privileged Thread mode, use PSP */\n        MOVEQ   R0,#0x03                /* Unprivileged Thread mode, use PSP */\n        MSR     CONTROL,R0\n        BX      LR\n\n        .fnend\n        .size   os_set_env, .-os_set_env\n\n\n/*--------------------------- _alloc_box ------------------------------------*/\n\n#      void *_alloc_box (void *box_mem);\n       /* Function wrapper for Unprivileged/Privileged mode. */\n\n        .thumb_func\n        .type   _alloc_box, %function\n        .global _alloc_box\n_alloc_box:\n        .fnstart\n        .cantunwind\n\n        LDR     R12,=rt_alloc_box\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        IT      NE\n        BXNE    R12\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        IT      EQ\n        BXEQ    R12\n        SVC     0\n        BX      LR\n\n        .fnend\n        .size   _alloc_box, .-_alloc_box\n\n\n/*--------------------------- _free_box -------------------------------------*/\n\n#       U32 _free_box (void *box_mem, void *box);\n        /* Function wrapper for Unprivileged/Privileged mode. */\n\n        .thumb_func\n        .type   _free_box, %function\n        .global _free_box\n_free_box:\n        .fnstart\n        .cantunwind\n\n        LDR     R12,=rt_free_box\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        IT      NE\n        BXNE    R12\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        IT      EQ\n        BXEQ    R12\n        SVC     0\n        BX      LR\n\n        .fnend\n        .size   _free_box, .-_free_box\n\n\n/*-------------------------- SVC_Handler ------------------------------------*/\n\n#       void SVC_Handler (void);\n\n        .thumb_func\n        .type   SVC_Handler, %function\n        .global SVC_Handler\nSVC_Handler:\n        .ifdef  IFX_XMC4XXX\n        .global SVC_Handler_Veneer\nSVC_Handler_Veneer:\n        .endif\n        .fnstart\n        .cantunwind\n\n        MRS     R0,PSP                  /* Read PSP */\n        LDR     R1,[R0,#24]             /* Read Saved PC from Stack */\n        LDRB    R1,[R1,#-2]             /* Load SVC Number */\n        CBNZ    R1,SVC_User\n\n        LDM     R0,{R0-R3,R12}          /* Read R0-R3,R12 from stack */\n        BLX     R12                     /* Call SVC Function */\n\n        MRS     R12,PSP                 /* Read PSP */\n        STM     R12,{R0-R2}             /* Store return values */\n\n        LDR     R3,=os_tsk\n        LDM     R3,{R1,R2}              /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        BEQ     SVC_Exit                /* no task switch */\n\n        CBZ     R1,SVC_Next             /* Runtask deleted? */\n        STMDB   R12!,{R4-R11}           /* Save Old context */\n        STR     R12,[R1,#TCB_TSTACK]    /* Update os_tsk.run->tsk_stack */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\nSVC_Next:\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R12,[R2,#TCB_TSTACK]    /* os_tsk.next->tsk_stack */\n        LDMIA   R12!,{R4-R11}           /* Restore New Context */\n        MSR     PSP,R12                 /* Write PSP */\n\nSVC_Exit:\n        MVN     LR,#~0xFFFFFFFD         /* set EXC_RETURN value */\n        .ifdef  IFX_XMC4XXX\n        PUSH    {LR}\n        POP     {PC}\n        .else\n        BX      LR\n        .endif\n\n        /*------------------- User SVC ------------------------------*/\n\nSVC_User:\n        PUSH    {R4,LR}                 /* Save Registers */\n        LDR     R2,=SVC_Count\n        LDR     R2,[R2]\n        CMP     R1,R2\n        BHI     SVC_Done                /* Overflow */\n\n        LDR     R4,=SVC_Table-4\n        LDR     R4,[R4,R1,LSL #2]       /* Load SVC Function Address */\n\n        LDM     R0,{R0-R3,R12}          /* Read R0-R3,R12 from stack */\n        BLX     R4                      /* Call SVC Function */\n\n        MRS     R12,PSP\n        STM     R12,{R0-R3}             /* Function return values */\nSVC_Done:\n        POP     {R4,PC}                 /* RETI */\n\n        .fnend\n        .size   SVC_Handler, .-SVC_Handler\n        \n\n/*-------------------------- PendSV_Handler ---------------------------------*/\n\n#       void PendSV_Handler (void);\n\n        .thumb_func\n        .type   PendSV_Handler, %function\n        .global PendSV_Handler\n        .global Sys_Switch\nPendSV_Handler:\n        .ifdef  IFX_XMC4XXX\n        .global PendSV_Handler_Veneer\nPendSV_Handler_Veneer:\n        .endif\n        .fnstart\n        .cantunwind\n\n        BL      rt_pop_req\n\nSys_Switch:\n        LDR     R3,=os_tsk\n        LDM     R3,{R1,R2}              /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        BEQ     Sys_Exit\n\n        MRS     R12,PSP                 /* Read PSP */\n        STMDB   R12!,{R4-R11}           /* Save Old context */\n        STR     R12,[R1,#TCB_TSTACK]    /* Update os_tsk.run->tsk_stack */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R12,[R2,#TCB_TSTACK]    /* os_tsk.next->tsk_stack */\n        LDMIA   R12!,{R4-R11}           /* Restore New Context */\n        MSR     PSP,R12                 /* Write PSP */\n\nSys_Exit:\n        MVN     LR,#~0xFFFFFFFD         /* set EXC_RETURN value */\n        .ifdef  IFX_XMC4XXX\n        PUSH    {LR}\n        POP     {PC}\n        .else\n        BX      LR                      /* Return to Thread Mode */\n        .endif\n\n        .fnend\n        .size   PendSV_Handler, .-PendSV_Handler\n\n\n/*-------------------------- SysTick_Handler --------------------------------*/\n\n#       void SysTick_Handler (void);\n\n        .thumb_func\n        .type   SysTick_Handler, %function\n        .global SysTick_Handler\nSysTick_Handler:\n        .ifdef  IFX_XMC4XXX\n        .global SysTick_Handler_Veneer\nSysTick_Handler_Veneer:\n        .endif\n        .fnstart\n        .cantunwind\n\n        BL      rt_systick\n        B       Sys_Switch\n\n        .fnend\n        .size   SysTick_Handler, .-SysTick_Handler\n\n\n/*-------------------------- OS_Tick_Handler --------------------------------*/\n\n#       void OS_Tick_Handler (void);\n\n        .thumb_func\n        .type   OS_Tick_Handler, %function\n        .global OS_Tick_Handler\nOS_Tick_Handler:\n        .fnstart\n        .cantunwind\n\n        BL      os_tick_irqack\n        BL      rt_systick\n        B       Sys_Switch\n\n        .fnend\n        .size   OS_Tick_Handler, .-OS_Tick_Handler\n\n\n        .end\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM4.S",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM4.S\n *      Purpose: Hardware Abstraction Layer for Cortex-M4\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n        .syntax unified\n\n        .equ    TCB_STACKF, 37\n        .equ    TCB_TSTACK, 40\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n        .thumb\n\n        .section \".text\"\n        .align  2\n\n\n/*--------------------------- rt_set_PSP ------------------------------------*/\n\n#       void rt_set_PSP (U32 stack);\n\n        .thumb_func\n        .type   rt_set_PSP, %function\n        .global rt_set_PSP\nrt_set_PSP:\n        .fnstart\n        .cantunwind\n\n        MSR     PSP,R0\n        BX      LR\n\n        .fnend\n        .size   rt_set_PSP, .-rt_set_PSP\n\n\n/*--------------------------- rt_get_PSP ------------------------------------*/\n\n#       U32 rt_get_PSP (void);\n\n        .thumb_func\n        .type   rt_get_PSP, %function\n        .global rt_get_PSP\nrt_get_PSP:\n        .fnstart\n        .cantunwind\n\n        MRS     R0,PSP\n        BX      LR\n\n        .fnend\n        .size   rt_get_PSP, .-rt_get_PSP\n\n\n/*--------------------------- os_set_env ------------------------------------*/\n\n#       void os_set_env (void);\n        /* Switch to Unprivileged/Privileged Thread mode, use PSP. */\n\n        .thumb_func\n        .type   os_set_env, %function\n        .global os_set_env\nos_set_env:\n        .fnstart\n        .cantunwind\n\n        MOV     R0,SP                   /* PSP = MSP */\n        MSR     PSP,R0\n        LDR     R0,=os_flags\n        LDRB    R0,[R0]\n        LSLS    R0,#31\n        ITE     NE\n        MOVNE   R0,#0x02                /* Privileged Thread mode, use PSP */\n        MOVEQ   R0,#0x03                /* Unprivileged Thread mode, use PSP */\n        MSR     CONTROL,R0\n        BX      LR\n\n        .fnend\n        .size   os_set_env, .-os_set_env\n\n\n/*--------------------------- _alloc_box ------------------------------------*/\n\n#      void *_alloc_box (void *box_mem);\n       /* Function wrapper for Unprivileged/Privileged mode. */\n\n        .thumb_func\n        .type   _alloc_box, %function\n        .global _alloc_box\n_alloc_box:\n        .fnstart\n        .cantunwind\n\n        LDR     R12,=rt_alloc_box\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        IT      NE\n        BXNE    R12\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        IT      EQ\n        BXEQ    R12\n        SVC     0\n        BX      LR\n\n        .fnend\n        .size   _alloc_box, .-_alloc_box\n\n\n/*--------------------------- _free_box -------------------------------------*/\n\n#       U32 _free_box (void *box_mem, void *box);\n        /* Function wrapper for Unprivileged/Privileged mode. */\n\n        .thumb_func\n        .type   _free_box, %function\n        .global _free_box\n_free_box:\n        .fnstart\n        .cantunwind\n\n        LDR     R12,=rt_free_box\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        IT      NE\n        BXNE    R12\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        IT      EQ\n        BXEQ    R12\n        SVC     0\n        BX      LR\n\n        .fnend\n        .size   _free_box, .-_free_box\n\n\n/*-------------------------- SVC_Handler ------------------------------------*/\n\n#       void SVC_Handler (void);\n\n        .thumb_func\n        .type   SVC_Handler, %function\n        .global SVC_Handler\nSVC_Handler:\n        .ifdef  IFX_XMC4XXX\n        .global SVC_Handler_Veneer\nSVC_Handler_Veneer:\n        .endif\n        .fnstart\n        .cantunwind\n\n        MRS     R0,PSP                  /* Read PSP */\n        LDR     R1,[R0,#24]             /* Read Saved PC from Stack */\n        LDRB    R1,[R1,#-2]             /* Load SVC Number */\n        CBNZ    R1,SVC_User\n\n        LDM     R0,{R0-R3,R12}          /* Read R0-R3,R12 from stack */\n        PUSH    {R4,LR}                 /* Save EXC_RETURN */\n        BLX     R12                     /* Call SVC Function */\n        POP     {R4,LR}                 /* Restore EXC_RETURN */\n\n        MRS     R12,PSP                 /* Read PSP */\n        STM     R12,{R0-R2}             /* Store return values */\n\n        LDR     R3,=os_tsk\n        LDM     R3,{R1,R2}              /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        .ifdef  IFX_XMC4XXX\n        ITT     EQ\n        PUSHEQ  {LR}\n        POPEQ   {PC}\n        .else\n        IT      EQ\n        BXEQ    LR                      /* RETI, no task switch */\n        .endif\n\n        CBNZ    R1,SVC_ContextSave      /* Runtask not deleted? */\n\n        TST     LR,#0x10                /* is it extended frame? */\n        BNE     SVC_ContextRestore\n        LDR     R1,=0xE000EF34\n        LDR     R0,[R1]                 /* Load FPCCR */\n        BIC     R0,#1                   /* Clear LSPACT (Lazy state) */\n        STR     R0,[R1]                 /* Store FPCCR */\n        B       SVC_ContextRestore\n\nSVC_ContextSave:\n        TST     LR,#0x10                /* is it extended frame? */\n        ITTE    EQ\n        VSTMDBEQ R12!,{S16-S31}         /* yes, stack also VFP hi-regs */\n        MOVEQ   R0,#0x01                /* os_tsk->stack_frame val */\n        MOVNE   R0,#0x00\n        STRB    R0,[R1,#TCB_STACKF]     /* os_tsk.run->stack_frame = val */\n        STMDB   R12!,{R4-R11}           /* Save Old context */\n        STR     R12,[R1,#TCB_TSTACK]    /* Update os_tsk.run->tsk_stack */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\nSVC_ContextRestore:\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R12,[R2,#TCB_TSTACK]    /* os_tsk.next->tsk_stack */\n        LDMIA   R12!,{R4-R11}           /* Restore New Context */\n        LDRB    R0,[R2,#TCB_STACKF]     /* Stack Frame */\n        CMP     R0,#0                   /* Basic/Extended Stack Frame */\n        ITEE    EQ\n        MVNEQ   LR,#~0xFFFFFFFD         /* set EXC_RETURN value */\n        MVNNE   LR,#~0xFFFFFFED\n        VLDMIANE R12!,{S16-S31}         /* restore VFP hi-registers */\n        MSR     PSP,R12                 /* Write PSP */\n\nSVC_Exit:\n        .ifdef  IFX_XMC4XXX\n        PUSH    {LR}\n        POP     {PC}\n        .else\n        BX      LR\n        .endif\n\n        /*------------------- User SVC ------------------------------*/\n\nSVC_User:\n        PUSH    {R4,LR}                 /* Save Registers */\n        LDR     R2,=SVC_Count\n        LDR     R2,[R2]\n        CMP     R1,R2\n        BHI     SVC_Done                /* Overflow */\n\n        LDR     R4,=SVC_Table-4\n        LDR     R4,[R4,R1,LSL #2]       /* Load SVC Function Address */\n\n        LDM     R0,{R0-R3,R12}          /* Read R0-R3,R12 from stack */\n        BLX     R4                      /* Call SVC Function */\n\n        MRS     R12,PSP\n        STM     R12,{R0-R3}             /* Function return values */\nSVC_Done:\n        POP     {R4,PC}                 /* RETI */\n\n        .fnend\n        .size   SVC_Handler, .-SVC_Handler\n        \n\n/*-------------------------- PendSV_Handler ---------------------------------*/\n\n#       void PendSV_Handler (void);\n\n        .thumb_func\n        .type   PendSV_Handler, %function\n        .global PendSV_Handler\n        .global Sys_Switch\nPendSV_Handler:\n        .ifdef  IFX_XMC4XXX\n        .global PendSV_Handler_Veneer\nPendSV_Handler_Veneer:\n        .endif\n        .fnstart\n        .cantunwind\n\n        PUSH    {R4,LR}                 /* Save EXC_RETURN */\n        BL      rt_pop_req\n\nSys_Switch:\n        POP     {R4,LR}                 /* Restore EXC_RETURN */\n\n        LDR     R3,=os_tsk\n        LDM     R3,{R1,R2}              /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        .ifdef  IFX_XMC4XXX\n        ITT     EQ\n        PUSHEQ  {LR}\n        POPEQ   {PC}\n        .else\n        IT      EQ\n        BXEQ    LR                      /* RETI, no task switch */\n        .endif\n\n        MRS     R12,PSP                 /* Read PSP */\n        TST     LR,#0x10                /* is it extended frame? */\n        ITTE    EQ\n        VSTMDBEQ R12!,{S16-S31}         /* yes, stack also VFP hi-regs */\n        MOVEQ   R0,#0x01                /* os_tsk->stack_frame val */\n        MOVNE   R0,#0x00\n        STRB    R0,[R1,#TCB_STACKF]     /* os_tsk.run->stack_frame = val */\n        STMDB   R12!,{R4-R11}           /* Save Old context */\n        STR     R12,[R1,#TCB_TSTACK]    /* Update os_tsk.run->tsk_stack */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R12,[R2,#TCB_TSTACK]    /* os_tsk.next->tsk_stack */\n        LDMIA   R12!,{R4-R11}           /* Restore New Context */\n        LDRB    R0,[R2,#TCB_STACKF]     /* Stack Frame */\n        CMP     R0,#0                   /* Basic/Extended Stack Frame */\n        ITEE    EQ\n        MVNEQ   LR,#~0xFFFFFFFD         /* set EXC_RETURN value */\n        MVNNE   LR,#~0xFFFFFFED\n        VLDMIANE R12!,{S16-S31}         /* restore VFP hi-registers */\n        MSR     PSP,R12                 /* Write PSP */\n\nSys_Exit:\n        .ifdef  IFX_XMC4XXX\n        PUSH    {LR}\n        POP     {PC}\n        .else\n        BX      LR                      /* Return to Thread Mode */\n        .endif\n\n        .fnend\n        .size   PendSV_Handler, .-PendSV_Handler\n\n\n/*-------------------------- SysTick_Handler --------------------------------*/\n\n#       void SysTick_Handler (void);\n\n        .thumb_func\n        .type   SysTick_Handler, %function\n        .global SysTick_Handler\nSysTick_Handler:\n        .ifdef  IFX_XMC4XXX\n        .global SysTick_Handler_Veneer\nSysTick_Handler_Veneer:\n        .endif\n        .fnstart\n        .cantunwind\n\n        PUSH    {R4,LR}                 /* Save EXC_RETURN */\n        BL      rt_systick\n        B       Sys_Switch\n\n        .fnend\n        .size   SysTick_Handler, .-SysTick_Handler\n\n\n/*-------------------------- OS_Tick_Handler --------------------------------*/\n\n#       void OS_Tick_Handler (void);\n\n        .thumb_func\n        .type   OS_Tick_Handler, %function\n        .global OS_Tick_Handler\nOS_Tick_Handler:\n        .fnstart\n        .cantunwind\n\n        PUSH    {R4,LR}                 /* Save EXC_RETURN */\n        BL      os_tick_irqack\n        BL      rt_systick\n        B       Sys_Switch\n\n        .fnend\n        .size   OS_Tick_Handler, .-OS_Tick_Handler\n\n\n        .end\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/GCC/RTX_Lib_CM.uvoptx",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectOpt xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_optx.xsd\">\n\n  <SchemaVersion>1.0</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Extensions>\n    <cExt>*.c</cExt>\n    <aExt>*.s*; *.src; *.a*</aExt>\n    <oExt>*.obj</oExt>\n    <lExt>*.lib</lExt>\n    <tExt>*.txt; *.h; *.inc</tExt>\n    <pExt>*.plm</pExt>\n    <CppX>*.cpp</CppX>\n    <nMigrate>0</nMigrate>\n  </Extensions>\n\n  <DaveTm>\n    <dwLowDateTime>0</dwLowDateTime>\n    <dwHighDateTime>0</dwHighDateTime>\n  </DaveTm>\n\n  <Target>\n    <TargetName>CM0_LE</TargetName>\n    <ToolsetNumber>0x3</ToolsetNumber>\n    <ToolsetName>ARM-GNU</ToolsetName>\n    <TargetOption>\n      <CLKARM>12000000</CLKARM>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>120</PageWidth>\n        <PageLength>65</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM0_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        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         <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM0_BE\\</OutputDirectory>\n          <OutputName>RTX_CM0_B</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM0_BE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>0</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM0_BE\\libRTX_CM0_B.a ..\\..\\LIB\\GCC\\</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  </SimDllArguments>\n          <SimDlgDll>DARMCM1.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> </TargetDllArguments>\n          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>0</Capability>\n            <DriverSelection>-1</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArm>\n          <ArmMisc>\n            <asLst>0</asLst>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>1</BigEnd>\n            <GCPUTYP>\"Cortex-M0\"</GCPUTYP>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <IRAM2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </IRAM2>\n              <IROM2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </IROM2>\n            </OnChipMemories>\n          </ArmMisc>\n          <Carm>\n            <arpcs>0</arpcs>\n            <stkchk>0</stkchk>\n            <reentr>0</reentr>\n            <interw>0</interw>\n            <bigend>0</bigend>\n            <Strict>0</Strict>\n            <Optim>5</Optim>\n            <wLevel>2</wLevel>\n            <uThumb>1</uThumb>\n            <VariousControls>\n              <MiscControls>-ffunction-sections -Wno-maybe-uninitialized</MiscControls>\n              <Define>__CORTEX_M0 __CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Carm>\n          <Aarm>\n            <bBE>0</bBE>\n            <interw>0</interw>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CORTEX_M0 __CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aarm>\n          <LDarm>\n            <umfTarg>1</umfTarg>\n            <enaGarb>1</enaGarb>\n            <noStart>1</noStart>\n            <noStLib>0</noStLib>\n            <uMathLib>0</uMathLib>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <BSSAddressRange></BSSAddressRange>\n            <IncludeLibs></IncludeLibs>\n            <IncludeDir></IncludeDir>\n            <Misc></Misc>\n            <ScatterFile></ScatterFile>\n          </LDarm>\n        </TargetArm>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Carm>\n                    <arpcs>2</arpcs>\n                    <stkchk>2</stkchk>\n                    <reentr>2</reentr>\n                    <interw>2</interw>\n                    <bigend>2</bigend>\n                    <Strict>0</Strict>\n                    <Optim>0</Optim>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Carm>\n                </FileArm>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.S</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\HAL_CM0.S</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM3.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\HAL_CM3.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Aarm>\n                    <bBE>2</bBE>\n                    <interw>2</interw>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aarm>\n                </FileArm>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\HAL_CM4.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Aarm>\n                    <bBE>2</bBE>\n                    <interw>2</interw>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aarm>\n                </FileArm>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM3_LE</TargetName>\n      <ToolsetNumber>0x3</ToolsetNumber>\n      <ToolsetName>ARM-GNU</ToolsetName>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM3</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M3\") CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM3$Device\\ARM\\ARMCM3\\Include\\ARMCM3.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM3$Device\\ARM\\SVD\\ARMCM3.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM3_LE\\</OutputDirectory>\n          <OutputName>RTX_CM3</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM3_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>0</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM3_LE\\libRTX_CM3.a ..\\..\\LIB\\GCC\\</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>0</Capability>\n            <DriverSelection>-1</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArm>\n          <ArmMisc>\n            <asLst>0</asLst>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <GCPUTYP>\"Cortex-M3\"</GCPUTYP>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <IRAM2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </IRAM2>\n              <IROM2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </IROM2>\n            </OnChipMemories>\n          </ArmMisc>\n          <Carm>\n            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<IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aarm>\n                </FileArm>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM3_LE_IFX</TargetName>\n      <ToolsetNumber>0x3</ToolsetNumber>\n      <ToolsetName>ARM-GNU</ToolsetName>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM3</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M3\") CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM3$Device\\ARM\\ARMCM3\\Include\\ARMCM3.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM3$Device\\ARM\\SVD\\ARMCM3.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            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   <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM3_LE_IFX\\libRTX_CM3_IFX.a ..\\..\\LIB\\GCC\\</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>0</Capability>\n            <DriverSelection>-1</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArm>\n          <ArmMisc>\n            <asLst>0</asLst>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <GCPUTYP>\"Cortex-M3\"</GCPUTYP>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <IRAM2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </IRAM2>\n              <IROM2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </IROM2>\n            </OnChipMemories>\n          </ArmMisc>\n          <Carm>\n            <arpcs>0</arpcs>\n            <stkchk>0</stkchk>\n            <reentr>0</reentr>\n            <interw>0</interw>\n            <bigend>0</bigend>\n            <Strict>0</Strict>\n            <Optim>5</Optim>\n            <wLevel>2</wLevel>\n            <uThumb>1</uThumb>\n            <VariousControls>\n              <MiscControls>-ffunction-sections -Wno-maybe-uninitialized</MiscControls>\n              <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Carm>\n          <Aarm>\n            <bBE>0</bBE>\n            <interw>0</interw>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>__CORTEX_M3 __CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aarm>\n          <LDarm>\n            <umfTarg>1</umfTarg>\n            <enaGarb>1</enaGarb>\n            <noStart>1</noStart>\n            <noStLib>0</noStLib>\n            <uMathLib>0</uMathLib>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <BSSAddressRange></BSSAddressRange>\n            <IncludeLibs></IncludeLibs>\n            <IncludeDir></IncludeDir>\n            <Misc></Misc>\n            <ScatterFile></ScatterFile>\n          </LDarm>\n        </TargetArm>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Carm>\n                    <arpcs>2</arpcs>\n                    <stkchk>2</stkchk>\n                    <reentr>2</reentr>\n                    <interw>2</interw>\n                    <bigend>2</bigend>\n                    <Strict>0</Strict>\n                    <Optim>0</Optim>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Carm>\n                </FileArm>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.S</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\HAL_CM0.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Aarm>\n                    <bBE>2</bBE>\n                    <interw>2</interw>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aarm>\n                </FileArm>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\HAL_CM3.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Aarm>\n                    <bBE>2</bBE>\n                    <interw>2</interw>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define>IFX_XMC4XXX</Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aarm>\n                </FileArm>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\HAL_CM4.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Aarm>\n                    <bBE>2</bBE>\n                    <interw>2</interw>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aarm>\n                </FileArm>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>CM4F_LE</TargetName>\n      <ToolsetNumber>0x3</ToolsetNumber>\n      <ToolsetName>ARM-GNU</ToolsetName>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM4_FP</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.0.0-Beta13</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE(\"Cortex-M4\") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM4_FP$Device\\ARM\\ARMCM4\\Include\\ARMCM4_FP.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM4_FP$Device\\ARM\\SVD\\ARMCM4.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\CM4F_LE\\</OutputDirectory>\n          <OutputName>RTX_CM4</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>0</BrowseInformation>\n          <ListingPath>.\\CM4F_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>0</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM4F_LE\\libRTX_CM4.a ..\\..\\LIB\\GCC\\</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          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<SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  -MPU</SimDllArguments>\n          <SimDlgDll>DCM.DLL</SimDlgDll>\n          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<bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArm>\n          <ArmMisc>\n            <asLst>0</asLst>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <GCPUTYP>\"Cortex-M4\"</GCPUTYP>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>2</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x80000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <IRAM2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </IRAM2>\n              <IROM2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </IROM2>\n            </OnChipMemories>\n          </ArmMisc>\n          <Carm>\n            <arpcs>0</arpcs>\n            <stkchk>0</stkchk>\n            <reentr>0</reentr>\n            <interw>0</interw>\n            <bigend>0</bigend>\n            <Strict>0</Strict>\n            <Optim>5</Optim>\n            <wLevel>2</wLevel>\n            <uThumb>1</uThumb>\n            <VariousControls>\n              <MiscControls>-mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -Wno-maybe-uninitialized</MiscControls>\n              <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Carm>\n          <Aarm>\n            <bBE>0</bBE>\n            <interw>0</interw>\n            <VariousControls>\n              <MiscControls>-mfpu=fpv4-sp-d16 -mfloat-abi=hard</MiscControls>\n              <Define>__CORTEX_M4F __CMSIS_RTOS</Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aarm>\n          <LDarm>\n            <umfTarg>1</umfTarg>\n            <enaGarb>1</enaGarb>\n            <noStart>1</noStart>\n            <noStLib>0</noStLib>\n            <uMathLib>0</uMathLib>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <BSSAddressRange></BSSAddressRange>\n            <IncludeLibs></IncludeLibs>\n            <IncludeDir></IncludeDir>\n            <Misc>-mfpu=fpv4-sp-d16 -mfloat-abi=hard</Misc>\n            <ScatterFile></ScatterFile>\n          </LDarm>\n        </TargetArm>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Kernel</GroupName>\n          <Files>\n            <File>\n              <FileName>rt_CMSIS.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_CMSIS.c</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  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<Strict>0</Strict>\n                    <Optim>0</Optim>\n                    <wLevel>0</wLevel>\n                    <uThumb>2</uThumb>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath>..\\..\\INC</IncludePath>\n                    </VariousControls>\n                  </Carm>\n                </FileArm>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>rt_Task.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Task.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_System.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_System.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Event.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Event.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_List.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_List.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mailbox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Mailbox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Time.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Time.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Robin.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Robin.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_MemBox.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_MemBox.c</FilePath>\n            </File>\n            <File>\n              <FileName>rt_Memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../rt_Memory.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>HAL</GroupName>\n          <Files>\n            <File>\n              <FileName>SVC_Table.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\SVC_Table.S</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>../HAL_CM.c</FilePath>\n            </File>\n            <File>\n              <FileName>HAL_CM0.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\HAL_CM0.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Aarm>\n                    <bBE>2</bBE>\n                    <interw>2</interw>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aarm>\n                </FileArm>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM3.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\HAL_CM3.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Aarm>\n                    <bBE>2</bBE>\n                    <interw>2</interw>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aarm>\n                </FileArm>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>HAL_CM4.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>.\\HAL_CM4.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>2</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArm>\n                  <Aarm>\n                    <bBE>2</bBE>\n                    <interw>2</interw>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define>IFX_XMC4XXX</Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aarm>\n                </FileArm>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis/>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"4.1.0\" condition=\"CMSIS Core\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"4.3.0\"/>\n        <targetInfos>\n          <targetInfo name=\"CM0_BE\"/>\n          <targetInfo name=\"CM0_LE\"/>\n          <targetInfo name=\"CM3_BE\"/>\n          <targetInfo name=\"CM3_LE\"/>\n          <targetInfo name=\"CM3_LE_IFX\"/>\n          <targetInfo name=\"CM4F_BE\"/>\n          <targetInfo name=\"CM4F_LE\"/>\n          <targetInfo name=\"CM4F_LE_IFX\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files/>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S",
    "content": ";/*----------------------------------------------------------------------------\n; *      CMSIS-RTOS - RTX\n; *----------------------------------------------------------------------------\n; *      Name:    SVC_TABLE.S\n; *      Purpose: Pre-defined SVC Table for Cortex-M\n; *      Rev.:    V4.70\n; *----------------------------------------------------------------------------\n; *\n; * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *---------------------------------------------------------------------------*/\n\n\n        .section \".svc_table\"\n\n        .global  SVC_Table\nSVC_Table:\n/* Insert user SVC functions here. SVC 0 used by RTL Kernel. */\n#       .long   __SVC_1                 /* user SVC function */\nSVC_End:\n\n        .global  SVC_Count\nSVC_Count:\n        .long   (SVC_End-SVC_Table)/4\n\n\n        .end\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/HAL_CM.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM.C\n *      Purpose: Hardware Abstraction Layer for Cortex-M\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_HAL_CM.h\"\n\n\n/*----------------------------------------------------------------------------\n *      Global Variables\n *---------------------------------------------------------------------------*/\n\n#ifdef DBG_MSG\nBIT dbg_msg;\n#endif\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_init_stack ---------------------------------*/\n\nvoid rt_init_stack(P_TCB p_TCB, FUNCP task_body) {\n    /* Prepare TCB and saved context for a first time start of a task. */\n    U32 *stk, i, size;\n\n    /* Prepare a complete interrupt frame for first task start */\n    size = p_TCB->priv_stack >> 2;\n    if (size == 0U) {\n        size = (U16) os_stackinfo >> 2;\n    }\n\n    /* Write to the top of stack. */\n    stk = &p_TCB->stack[size];\n\n    /* Auto correct to 8-byte ARM stack alignment. */\n    if ((U32) stk & 0x04U) {\n        stk--;\n    }\n\n    stk -= 16;\n\n    /* Default xPSR and initial PC */\n    stk[15] = INITIAL_xPSR;\n    stk[14] = (U32) task_body;\n\n    /* Clear R4-R11,R0-R3,R12,LR registers. */\n    for (i = 0U; i < 14U; i++) {\n        stk[i] = 0U;\n    }\n\n    /* Assign a void pointer to R0. */\n    stk[8] = (U32) p_TCB->msg;\n\n    /* Initial Task stack pointer. */\n    p_TCB->tsk_stack = (U32) stk;\n\n    /* Task entry point. */\n    p_TCB->ptask = task_body;\n\n    /* Initialize stack with magic pattern. */\n    if (os_stackinfo & 0x10000000U) {\n        if (size > (16U + 1U)) {\n            for (i = ((size - 16U) / 2U) - 1U; i; i--) {\n                stk -= 2U;\n                stk[1] = MAGIC_PATTERN;\n                stk[0] = MAGIC_PATTERN;\n            }\n            if (--stk > p_TCB->stack) {\n                *stk = MAGIC_PATTERN;\n            }\n        }\n    }\n\n    /* Set a magic word for checking of stack overflow. */\n    p_TCB->stack[0] = MAGIC_WORD;\n}\n\n\n/*--------------------------- rt_ret_val ----------------------------------*/\n\nstatic __inline U32 *rt_ret_regs(P_TCB p_TCB) {\n    /* Get pointer to task return value registers (R0..R3) in Stack */\n#if defined(__TARGET_FPU_VFP)\n    if (p_TCB->stack_frame) {\n      /* Extended Stack Frame: R4-R11,S16-S31,R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR */\n      return (U32 *)(p_TCB->tsk_stack + (8U*4U) + (16U*4U));\n    } else {\n      /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */\n      return (U32 *)(p_TCB->tsk_stack + (8U*4U));\n    }\n#else\n    /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */\n    return (U32 *) (p_TCB->tsk_stack + (8U * 4U));\n#endif\n}\n\nvoid rt_ret_val(P_TCB p_TCB, U32 v0) {\n    U32 *ret;\n\n    ret = rt_ret_regs(p_TCB);\n    ret[0] = v0;\n}\n\nvoid rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {\n    U32 *ret;\n\n    ret = rt_ret_regs(p_TCB);\n    ret[0] = v0;\n    ret[1] = v1;\n}\n\n\n/*--------------------------- dbg_init --------------------------------------*/\n\n#ifdef DBG_MSG\nvoid dbg_init (void) {\n  if (((DEMCR & DEMCR_TRCENA) != 0U)     && \n      ((ITM_CONTROL & ITM_ITMENA) != 0U) &&\n      ((ITM_ENABLE & (1UL << 31)) != 0U)) {\n    dbg_msg = __TRUE;\n  }\n}\n#endif\n\n/*--------------------------- dbg_task_notify -------------------------------*/\n\n#ifdef DBG_MSG\nvoid dbg_task_notify (P_TCB p_tcb, BOOL create) {\n  while (ITM_PORT31_U32 == 0U);\n  ITM_PORT31_U32 = (U32)p_tcb->ptask;\n  while (ITM_PORT31_U32 == 0U);\n  ITM_PORT31_U16 = (U16)((create << 8) | p_tcb->task_id);\n}\n#endif\n\n/*--------------------------- dbg_task_switch -------------------------------*/\n\n#ifdef DBG_MSG\nvoid dbg_task_switch (U32 task_id) {\n  while (ITM_PORT31_U32 == 0U);\n  ITM_PORT31_U8 = (U8)task_id;\n}\n#endif\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM0.s",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM0.S\n *      Purpose: Hardware Abstraction Layer for Cortex-M0\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n        NAME    HAL_CM0.S\n\n        #define TCB_TSTACK 40\n\n        EXTERN  os_flags\n        EXTERN  os_tsk\n        EXTERN  rt_alloc_box\n        EXTERN  rt_free_box\n        EXTERN  rt_stk_check\n        EXTERN  rt_pop_req\n        EXTERN  rt_systick\n        EXTERN  os_tick_irqack\n        EXTERN  SVC_Table\n        EXTERN  SVC_Count\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n        SECTION .text:CODE:NOROOT(2)\n        THUMB\n\n/*--------------------------- rt_set_PSP ------------------------------------*/\n\n;       void rt_set_PSP (U32 stack);\n\n        PUBLIC  rt_set_PSP\nrt_set_PSP:\n\n        MSR     PSP,R0\n        BX      LR\n\n\n/*--------------------------- rt_get_PSP ------------------------------------*/\n\n;       U32 rt_get_PSP (void);\n\n        PUBLIC  rt_get_PSP\nrt_get_PSP:\n\n        MRS     R0,PSP\n        BX      LR\n\n\n/*--------------------------- os_set_env ------------------------------------*/\n\n;       void os_set_env (void);\n        /* Switch to Unprivileged/Privileged Thread mode, use PSP. */\n\n        PUBLIC  os_set_env\nos_set_env:\n\n        MOV     R0,SP                   /* PSP = MSP */\n        MSR     PSP,R0\n        LDR     R0,=os_flags\n        LDRB    R0,[R0]\n        LSLS    R0,#31\n        BNE     PrivilegedE\n        MOVS    R0,#0x03                /* Unprivileged Thread mode, use PSP */\n        MSR     CONTROL,R0\n        BX      LR\nPrivilegedE:\n        MOVS    R0,#0x02                /* Privileged Thread mode, use PSP */\n        MSR     CONTROL,R0\n        BX      LR\n\n\n/*--------------------------- _alloc_box ------------------------------------*/\n\n;      void *_alloc_box (void *box_mem);\n       /* Function wrapper for Unprivileged/Privileged mode. */\n\n        PUBLIC  _alloc_box\n_alloc_box:\n\n        LDR     R3,=rt_alloc_box\n        MOV     R12,R3\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        BNE     PrivilegedA\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        BEQ     PrivilegedA\n        SVC     0\n        BX      LR\nPrivilegedA:\n        BX      R12\n\n\n/*--------------------------- _free_box -------------------------------------*/\n\n;       U32 _free_box (void *box_mem, void *box);\n        /* Function wrapper for Unprivileged/Privileged mode. */\n\n        PUBLIC  _free_box\n_free_box:\n\n        LDR     R3,=rt_free_box\n        MOV     R12,R3\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        BNE     PrivilegedF\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        BEQ     PrivilegedF\n        SVC     0\n        BX      LR\nPrivilegedF:\n        BX      R12\n\n\n/*-------------------------- SVC_Handler ------------------------------------*/\n\n;       void SVC_Handler (void);\n\n        PUBLIC  SVC_Handler\nSVC_Handler:\n\n        MRS     R0,PSP                  /* Read PSP */\n        LDR     R1,[R0,#24]             /* Read Saved PC from Stack */\n        SUBS    R1,R1,#2                /* Point to SVC Instruction */\n        LDRB    R1,[R1]                 /* Load SVC Number */\n        CMP     R1,#0\n        BNE     SVC_User                /* User SVC Number > 0 */\n\n        MOV     LR,R4\n        LDMIA   R0,{R0-R3,R4}           /* Read R0-R3,R12 from stack */\n        MOV     R12,R4\n        MOV     R4,LR\n        BLX     R12                     /* Call SVC Function */\n\n        MRS     R3,PSP                  /* Read PSP */\n        STMIA   R3!,{R0-R2}             /* Store return values */\n\n        LDR     R3,=os_tsk\n        LDMIA   R3!,{R1,R2}             /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        BEQ     SVC_Exit                /* no task switch */\n\n        SUBS    R3,#8\n        CMP     R1,#0                   /* Runtask deleted? */\n        BEQ     SVC_Next\n\n        MRS     R0,PSP                  /* Read PSP */\n        SUBS    R0,R0,#32               /* Adjust Start Address */\n        STR     R0,[R1,#TCB_TSTACK]     /* Update os_tsk.run->tsk_stack */       \n        STMIA   R0!,{R4-R7}             /* Save old context (R4-R7) */\n        MOV     R4,R8\n        MOV     R5,R9\n        MOV     R6,R10\n        MOV     R7,R11\n        STMIA   R0!,{R4-R7}             /* Save old context (R8-R11) */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\nSVC_Next:\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R0,[R2,#TCB_TSTACK]     /* os_tsk.next->tsk_stack */\n        ADDS    R0,R0,#16               /* Adjust Start Address */\n        LDMIA   R0!,{R4-R7}             /* Restore new Context (R8-R11) */\n        MOV     R8,R4\n        MOV     R9,R5\n        MOV     R10,R6\n        MOV     R11,R7\n        MSR     PSP,R0                  /* Write PSP */\n        SUBS    R0,R0,#32               /* Adjust Start Address */\n        LDMIA   R0!,{R4-R7}             /* Restore new Context (R4-R7) */\n\nSVC_Exit:\n        MOVS    R0,#~0xFFFFFFFD         /* Set EXC_RETURN value */\n        MVNS    R0,R0\n        BX      R0                      /* RETI to Thread Mode, use PSP */\n\n        /*------------------- User SVC ------------------------------*/\n\nSVC_User:\n        PUSH    {R4,LR}                 /* Save Registers */\n        LDR     R2,=SVC_Count\n        LDR     R2,[R2]\n        CMP     R1,R2\n        BHI     SVC_Done                /* Overflow */\n\n        LDR     R4,=SVC_Table-4\n        LSLS    R1,R1,#2\n        LDR     R4,[R4,R1]              /* Load SVC Function Address */\n        MOV     LR,R4\n\n        LDMIA   R0,{R0-R3,R4}           /* Read R0-R3,R12 from stack */\n        MOV     R12,R4\n        BLX     LR                      /* Call SVC Function */\n\n        MRS     R4,PSP                  /* Read PSP */\n        STMIA   R4!,{R0-R3}             /* Function return values */\nSVC_Done:\n        POP     {R4,PC}                 /* RETI */\n        \n\n/*-------------------------- PendSV_Handler ---------------------------------*/\n\n;       void PendSV_Handler (void);\n\n        PUBLIC  PendSV_Handler\nPendSV_Handler:\n\n        BL      rt_pop_req\n\nSys_Switch:\n        LDR     R3,=os_tsk\n        LDMIA   R3!,{R1,R2}             /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        BEQ     Sys_Exit                /* no task switch */\n\n        SUBS    R3,#8\n\n        MRS     R0,PSP                  /* Read PSP */\n        SUBS    R0,R0,#32               /* Adjust Start Address */\n        STR     R0,[R1,#TCB_TSTACK]     /* Update os_tsk.run->tsk_stack */\n        STMIA   R0!,{R4-R7}             /* Save old context (R4-R7) */\n        MOV     R4,R8\n        MOV     R5,R9\n        MOV     R6,R10\n        MOV     R7,R11\n        STMIA   R0!,{R4-R7}             /* Save old context (R8-R11) */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R0,[R2,#TCB_TSTACK]     /* os_tsk.next->tsk_stack */\n        ADDS    R0,R0,#16               /* Adjust Start Address */\n        LDMIA   R0!,{R4-R7}             /* Restore new Context (R8-R11) */\n        MOV     R8,R4\n        MOV     R9,R5\n        MOV     R10,R6\n        MOV     R11,R7\n        MSR     PSP,R0                  /* Write PSP */\n        SUBS    R0,R0,#32               /* Adjust Start Address */\n        LDMIA   R0!,{R4-R7}             /* Restore new Context (R4-R7) */\n\nSys_Exit:\n        MOVS    R0,#~0xFFFFFFFD         /* Set EXC_RETURN value */\n        MVNS    R0,R0\n        BX      R0                      /* RETI to Thread Mode, use PSP */\n\n\n/*-------------------------- SysTick_Handler --------------------------------*/\n\n;       void SysTick_Handler (void);\n\n        PUBLIC  SysTick_Handler\nSysTick_Handler:\n\n        BL      rt_systick\n        B       Sys_Switch\n\n\n/*-------------------------- OS_Tick_Handler --------------------------------*/\n\n;       void OS_Tick_Handler (void);\n\n        PUBLIC  OS_Tick_Handler\nOS_Tick_Handler:\n\n        BL      os_tick_irqack\n        BL      rt_systick\n        B       Sys_Switch\n\n\n        END\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM3.s",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM3.S\n *      Purpose: Hardware Abstraction Layer for Cortex-M3\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n        NAME    HAL_CM3.S\n\n        #define TCB_TSTACK 40\n\n        EXTERN  os_flags\n        EXTERN  os_tsk\n        EXTERN  rt_alloc_box\n        EXTERN  rt_free_box\n        EXTERN  rt_stk_check\n        EXTERN  rt_pop_req\n        EXTERN  rt_systick\n        EXTERN  os_tick_irqack\n        EXTERN  SVC_Table\n        EXTERN  SVC_Count\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n        SECTION .text:CODE:NOROOT(2)\n        THUMB\n\n/*--------------------------- rt_set_PSP ------------------------------------*/\n\n;       void rt_set_PSP (U32 stack);\n\n        PUBLIC  rt_set_PSP\nrt_set_PSP:\n\n        MSR     PSP,R0\n        BX      LR\n\n\n/*--------------------------- rt_get_PSP ------------------------------------*/\n\n;       U32 rt_get_PSP (void);\n\n        PUBLIC  rt_get_PSP\nrt_get_PSP:\n\n        MRS     R0,PSP\n        BX      LR\n\n\n/*--------------------------- os_set_env ------------------------------------*/\n\n;       void os_set_env (void);\n        /* Switch to Unprivileged/Privileged Thread mode, use PSP. */\n\n        PUBLIC  os_set_env\nos_set_env:\n\n        MOV     R0,SP                   /* PSP = MSP */\n        MSR     PSP,R0\n        LDR     R0,=os_flags\n        LDRB    R0,[R0]\n        LSLS    R0,#31\n        ITE     NE\n        MOVNE   R0,#0x02                /* Privileged Thread mode, use PSP */\n        MOVEQ   R0,#0x03                /* Unprivileged Thread mode, use PSP */\n        MSR     CONTROL,R0\n        BX      LR\n\n\n/*--------------------------- _alloc_box ------------------------------------*/\n\n;      void *_alloc_box (void *box_mem);\n       /* Function wrapper for Unprivileged/Privileged mode. */\n\n        PUBLIC  _alloc_box\n_alloc_box:\n\n        LDR     R12,=rt_alloc_box\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        IT      NE\n        BXNE    R12\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        IT      EQ\n        BXEQ    R12\n        SVC     0\n        BX      LR\n\n\n/*--------------------------- _free_box -------------------------------------*/\n\n;       U32 _free_box (void *box_mem, void *box);\n        /* Function wrapper for Unprivileged/Privileged mode. */\n\n        PUBLIC  _free_box\n_free_box:\n\n        LDR     R12,=rt_free_box\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        IT      NE\n        BXNE    R12\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        IT      EQ\n        BXEQ    R12\n        SVC     0\n        BX      LR\n\n\n/*-------------------------- SVC_Handler ------------------------------------*/\n\n;       void SVC_Handler (void);\n\n        PUBLIC  SVC_Handler\nSVC_Handler:\n\n        MRS     R0,PSP                  /* Read PSP */\n        LDR     R1,[R0,#24]             /* Read Saved PC from Stack */\n        LDRB    R1,[R1,#-2]             /* Load SVC Number */\n        CBNZ    R1,SVC_User\n\n        LDM     R0,{R0-R3,R12}          /* Read R0-R3,R12 from stack */\n        BLX     R12                     /* Call SVC Function */\n\n        MRS     R12,PSP                 /* Read PSP */\n        STM     R12,{R0-R2}             /* Store return values */\n\n        LDR     R3,=os_tsk\n        LDM     R3,{R1,R2}              /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        BEQ     SVC_Exit                /* no task switch */\n\n        CBZ     R1,SVC_Next             /* Runtask deleted? */\n        STMDB   R12!,{R4-R11}           /* Save Old context */\n        STR     R12,[R1,#TCB_TSTACK]    /* Update os_tsk.run->tsk_stack */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\nSVC_Next:\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R12,[R2,#TCB_TSTACK]    /* os_tsk.next->tsk_stack */\n        LDMIA   R12!,{R4-R11}           /* Restore New Context */\n        MSR     PSP,R12                 /* Write PSP */\n\nSVC_Exit:\n        MVN     LR,#~0xFFFFFFFD         /* set EXC_RETURN value */\n        BX      LR\n\n        /*------------------- User SVC ------------------------------*/\n\nSVC_User:\n        PUSH    {R4,LR}                 /* Save Registers */\n        LDR     R2,=SVC_Count\n        LDR     R2,[R2]\n        CMP     R1,R2\n        BHI     SVC_Done                /* Overflow */\n\n        LDR     R4,=SVC_Table-4\n        LDR     R4,[R4,R1,LSL #2]       /* Load SVC Function Address */\n\n        LDM     R0,{R0-R3,R12}          /* Read R0-R3,R12 from stack */\n        BLX     R4                      /* Call SVC Function */\n\n        MRS     R12,PSP\n        STM     R12,{R0-R3}             /* Function return values */\nSVC_Done:\n        POP     {R4,PC}                 /* RETI */\n        \n\n/*-------------------------- PendSV_Handler ---------------------------------*/\n\n;       void PendSV_Handler (void);\n\n        PUBLIC  PendSV_Handler\nPendSV_Handler:\n\n        BL      rt_pop_req\n\nSys_Switch:\n        LDR     R3,=os_tsk\n        LDM     R3,{R1,R2}              /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        BEQ     Sys_Exit\n\n        MRS     R12,PSP                 /* Read PSP */\n        STMDB   R12!,{R4-R11}           /* Save Old context */\n        STR     R12,[R1,#TCB_TSTACK]    /* Update os_tsk.run->tsk_stack */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R12,[R2,#TCB_TSTACK]    /* os_tsk.next->tsk_stack */\n        LDMIA   R12!,{R4-R11}           /* Restore New Context */\n        MSR     PSP,R12                 /* Write PSP */\n\nSys_Exit:\n        MVN     LR,#~0xFFFFFFFD         /* set EXC_RETURN value */\n        BX      LR                      /* Return to Thread Mode */\n\n\n/*-------------------------- SysTick_Handler --------------------------------*/\n\n;       void SysTick_Handler (void);\n\n        PUBLIC  SysTick_Handler\nSysTick_Handler:\n\n        BL      rt_systick\n        B       Sys_Switch\n\n\n/*-------------------------- OS_Tick_Handler --------------------------------*/\n\n;       void OS_Tick_Handler (void);\n\n        PUBLIC  OS_Tick_Handler\nOS_Tick_Handler:\n\n        BL      os_tick_irqack\n        BL      rt_systick\n        B       Sys_Switch\n\n\n        END\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM4.s",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    HAL_CM4.S\n *      Purpose: Hardware Abstraction Layer for Cortex-M4\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n        NAME    HAL_CM4.S\n\n        #define TCB_STACKF 37\n        #define TCB_TSTACK 40\n\n        EXTERN  os_flags\n        EXTERN  os_tsk\n        EXTERN  rt_alloc_box\n        EXTERN  rt_free_box\n        EXTERN  rt_stk_check\n        EXTERN  rt_pop_req\n        EXTERN  rt_systick\n        EXTERN  os_tick_irqack\n        EXTERN  SVC_Table\n        EXTERN  SVC_Count\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n        SECTION .text:CODE:NOROOT(2)\n        THUMB\n\n/*--------------------------- rt_set_PSP ------------------------------------*/\n\n;       void rt_set_PSP (U32 stack);\n\n        PUBLIC  rt_set_PSP\nrt_set_PSP:\n\n        MSR     PSP,R0\n        BX      LR\n\n\n/*--------------------------- rt_get_PSP ------------------------------------*/\n\n;       U32 rt_get_PSP (void);\n\n        PUBLIC  rt_get_PSP\nrt_get_PSP:\n\n        MRS     R0,PSP\n        BX      LR\n\n\n/*--------------------------- os_set_env ------------------------------------*/\n\n;       void os_set_env (void);\n        /* Switch to Unprivileged/Privileged Thread mode, use PSP. */\n\n        PUBLIC  os_set_env\nos_set_env:\n\n        MOV     R0,SP                   /* PSP = MSP */\n        MSR     PSP,R0\n        LDR     R0,=os_flags\n        LDRB    R0,[R0]\n        LSLS    R0,#31\n        ITE     NE\n        MOVNE   R0,#0x02                /* Privileged Thread mode, use PSP */\n        MOVEQ   R0,#0x03                /* Unprivileged Thread mode, use PSP */\n        MSR     CONTROL,R0\n        BX      LR\n\n\n/*--------------------------- _alloc_box ------------------------------------*/\n\n;      void *_alloc_box (void *box_mem);\n       /* Function wrapper for Unprivileged/Privileged mode. */\n\n        PUBLIC  _alloc_box\n_alloc_box:\n\n        LDR     R12,=rt_alloc_box\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        IT      NE\n        BXNE    R12\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        IT      EQ\n        BXEQ    R12\n        SVC     0\n        BX      LR\n\n\n/*--------------------------- _free_box -------------------------------------*/\n\n;       U32 _free_box (void *box_mem, void *box);\n        /* Function wrapper for Unprivileged/Privileged mode. */\n\n        PUBLIC  _free_box\n_free_box:\n\n        LDR     R12,=rt_free_box\n        MRS     R3,IPSR\n        LSLS    R3,#24\n        IT      NE\n        BXNE    R12\n        MRS     R3,CONTROL\n        LSLS    R3,#31\n        IT      EQ\n        BXEQ    R12\n        SVC     0\n        BX      LR\n\n\n/*-------------------------- SVC_Handler ------------------------------------*/\n\n;       void SVC_Handler (void);\n\n        PUBLIC  SVC_Handler\nSVC_Handler:\n\n        MRS     R0,PSP                  /* Read PSP */\n        LDR     R1,[R0,#24]             /* Read Saved PC from Stack */\n        LDRB    R1,[R1,#-2]             /* Load SVC Number */\n        CBNZ    R1,SVC_User\n\n        LDM     R0,{R0-R3,R12}          /* Read R0-R3,R12 from stack */\n        PUSH    {R4,LR}                 /* Save EXC_RETURN */\n        BLX     R12                     /* Call SVC Function */\n        POP     {R4,LR}                 /* Restore EXC_RETURN */\n\n        MRS     R12,PSP                 /* Read PSP */\n        STM     R12,{R0-R2}             /* Store return values */\n\n        LDR     R3,=os_tsk\n        LDM     R3,{R1,R2}              /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        IT      EQ\n        BXEQ    LR                      /* RETI, no task switch */\n\n        CBNZ    R1,SVC_ContextSave      /* Runtask not deleted? */\n\n        TST     LR,#0x10                /* is it extended frame? */\n        BNE     SVC_ContextRestore\n        LDR     R1,=0xE000EF34\n        LDR     R0,[R1]                 /* Load FPCCR */\n        BIC     R0,R0,#1                /* Clear LSPACT (Lazy state) */\n        STR     R0,[R1]                 /* Store FPCCR */\n        B       SVC_ContextRestore\n\nSVC_ContextSave:\n        TST     LR,#0x10                /* is it extended frame? */\n        ITTE    EQ\n        VSTMDBEQ R12!,{S16-S31}         /* yes, stack also VFP hi-regs */\n        MOVEQ   R0,#0x01                /* os_tsk->stack_frame val */\n        MOVNE   R0,#0x00\n        STRB    R0,[R1,#TCB_STACKF]     /* os_tsk.run->stack_frame = val */\n        STMDB   R12!,{R4-R11}           /* Save Old context */\n        STR     R12,[R1,#TCB_TSTACK]    /* Update os_tsk.run->tsk_stack */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\nSVC_ContextRestore:\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R12,[R2,#TCB_TSTACK]    /* os_tsk.next->tsk_stack */\n        LDMIA   R12!,{R4-R11}           /* Restore New Context */\n        LDRB    R0,[R2,#TCB_STACKF]     /* Stack Frame */\n        CMP     R0,#0                   /* Basic/Extended Stack Frame */\n        ITEE    EQ\n        MVNEQ   LR,#~0xFFFFFFFD         /* set EXC_RETURN value */\n        MVNNE   LR,#~0xFFFFFFED\n        VLDMIANE R12!,{S16-S31}         /* restore VFP hi-registers */\n        MSR     PSP,R12                 /* Write PSP */\n\nSVC_Exit:\n        BX      LR\n\n        /*------------------- User SVC ------------------------------*/\n\nSVC_User:\n        PUSH    {R4,LR}                 /* Save Registers */\n        LDR     R2,=SVC_Count\n        LDR     R2,[R2]\n        CMP     R1,R2\n        BHI     SVC_Done                /* Overflow */\n\n        LDR     R4,=SVC_Table-4\n        LDR     R4,[R4,R1,LSL #2]       /* Load SVC Function Address */\n\n        LDM     R0,{R0-R3,R12}          /* Read R0-R3,R12 from stack */\n        BLX     R4                      /* Call SVC Function */\n\n        MRS     R12,PSP\n        STM     R12,{R0-R3}             /* Function return values */\nSVC_Done:\n        POP     {R4,PC}                 /* RETI */\n        \n\n/*-------------------------- PendSV_Handler ---------------------------------*/\n\n;       void PendSV_Handler (void);\n\n        PUBLIC  PendSV_Handler\nPendSV_Handler:\n\n        PUSH    {R4,LR}                 /* Save EXC_RETURN */\n        BL      rt_pop_req\n\nSys_Switch:\n        POP     {R4,LR}                 /* Restore EXC_RETURN */\n\n        LDR     R3,=os_tsk\n        LDM     R3,{R1,R2}              /* os_tsk.run, os_tsk.next */\n        CMP     R1,R2\n        IT      EQ\n        BXEQ    LR                      /* RETI, no task switch */\n\n        MRS     R12,PSP                 /* Read PSP */\n        TST     LR,#0x10                /* is it extended frame? */\n        ITTE    EQ\n        VSTMDBEQ R12!,{S16-S31}         /* yes, stack also VFP hi-regs */\n        MOVEQ   R0,#0x01                /* os_tsk->stack_frame val */\n        MOVNE   R0,#0x00\n        STRB    R0,[R1,#TCB_STACKF]     /* os_tsk.run->stack_frame = val */\n        STMDB   R12!,{R4-R11}           /* Save Old context */\n        STR     R12,[R1,#TCB_TSTACK]    /* Update os_tsk.run->tsk_stack */\n\n        PUSH    {R2,R3}\n        BL      rt_stk_check            /* Check for Stack overflow */\n        POP     {R2,R3}\n\n        STR     R2,[R3]                 /* os_tsk.run = os_tsk.next */\n\n        LDR     R12,[R2,#TCB_TSTACK]    /* os_tsk.next->tsk_stack */\n        LDMIA   R12!,{R4-R11}           /* Restore New Context */\n        LDRB    R0,[R2,#TCB_STACKF]     /* Stack Frame */\n        CMP     R0,#0                   /* Basic/Extended Stack Frame */\n        ITEE    EQ\n        MVNEQ   LR,#~0xFFFFFFFD         /* set EXC_RETURN value */\n        MVNNE   LR,#~0xFFFFFFED\n        VLDMIANE R12!,{S16-S31}         /* restore VFP hi-registers */\n        MSR     PSP,R12                 /* Write PSP */\n\nSys_Exit:\n        BX      LR                      /* Return to Thread Mode */\n\n\n/*-------------------------- SysTick_Handler --------------------------------*/\n\n;       void SysTick_Handler (void);\n\n        PUBLIC  SysTick_Handler\nSysTick_Handler:\n\n        PUSH    {R4,LR}                 /* Save EXC_RETURN */\n        BL      rt_systick\n        B       Sys_Switch\n\n\n/*-------------------------- OS_Tick_Handler --------------------------------*/\n\n;       void OS_Tick_Handler (void);\n\n        PUBLIC  OS_Tick_Handler\nOS_Tick_Handler:\n\n        PUSH    {R4,LR}                 /* Save EXC_RETURN */\n        BL      os_tick_irqack\n        BL      rt_systick\n        B       Sys_Switch\n\n\n        END\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/IAR/RTX_Lib_CM.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>CM0_LE</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>31</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>ExePath</name>\n                    <state>CM0_LE</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>CM0_LE</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>CM0_LE</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>6.30.3.53229</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>8.32.3.20186</state>\n                </option>\n                <option>\n                    <name>GeneralEnableMisra</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraVerbose</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    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     <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    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<state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>__CMSIS_RTOS</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n              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<name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        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</data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n            </data>\n        </settings>\n        <settings>\n            <name>BICOMP</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild>cmd.exe /C copy \"$TARGET_PATH$\" \"$PROJ_DIR$\\..\\..\\LIB\\IAR\\RTX_CM0.a\"</postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>22</version>\n                <wantNonLocal>1</wantNonLocal>\n              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<name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n            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             <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n           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<option>\n                    <name>ObjPath</name>\n                    <state>CM0_BE</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>CM0_BE</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>6.30.3.53229</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>8.32.3.20186</state>\n                </option>\n                <option>\n                    <name>GeneralEnableMisra</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraVerbose</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraRules98</name>\n                    <version>0</version>\n                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                </option>\n                <option>\n                    <name>GeneralMisraVer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraRules04</name>\n                    <version>0</version>\n                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>27</version>\n                    <state>34</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>27</version>\n                    <state>34</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                  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              <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state>__CORTEX_M0</state>\n                    <state>__CMSIS_RTOS</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state>Pa082</state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CompilerMisraOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CompilerMisraRules98</name>\n                    <version>0</version>\n                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                </option>\n                <option>\n                    <name>CompilerMisraRules04</name>\n                    <version>0</version>\n                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    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<name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        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         <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n           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<option>\n                    <name>ObjPath</name>\n                    <state>CM3_LE</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>CM3_LE</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>6.30.3.53229</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>8.32.3.20186</state>\n                </option>\n                <option>\n                    <name>GeneralEnableMisra</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraVerbose</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    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<name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>27</version>\n                    <state>38</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                  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              <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state>__CORTEX_M3</state>\n                    <state>__CMSIS_RTOS</state>\n                    <state>DBG_MSG</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CompilerMisraOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CompilerMisraRules98</name>\n                    <version>0</version>\n             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<state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>10</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state>__CMSIS_RTOS</state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                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      <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n            </data>\n        </settings>\n        <settings>\n            <name>BICOMP</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild>cmd.exe /C copy \"$TARGET_PATH$\" \"$PROJ_DIR$\\..\\..\\LIB\\IAR\\RTX_CM3.a\"</postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>22</version>\n                <wantNonLocal>1</wantNonLocal>\n              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<state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>D:\\GitHub\\ARM-software\\CMSIS_5\\CMSIS\\RTOS\\RTX\\SRC\\IAR\\CM3_LE\\RTX_Lib_CM.a</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>BILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <configuration>\n        <name>CM3_BE</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>31</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>ExePath</name>\n                    <state>CM3_BE</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>CM3_BE</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>CM3_BE</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>6.30.3.53229</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>8.32.3.20186</state>\n                </option>\n                <option>\n                    <name>GeneralEnableMisra</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraVerbose</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraRules98</name>\n                    <version>0</version>\n                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                </option>\n                <option>\n                    <name>GeneralMisraVer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraRules04</name>\n                    <version>0</version>\n                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>27</version>\n                    <state>38</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>27</version>\n                    <state>38</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>27</version>\n                    <state>38</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>35</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDefines</name>\n                    <state>__CORTEX_M3</state>\n                    <state>__CMSIS_RTOS</state>\n                    <state>DBG_MSG</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n        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<state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n       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<state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    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      <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        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</data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n            </data>\n        </settings>\n        <settings>\n            <name>BICOMP</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild>cmd.exe /C copy \"$TARGET_PATH$\" \"$PROJ_DIR$\\..\\..\\LIB\\IAR\\RTX_CM3_B.a\"</postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>22</version>\n                <wantNonLocal>1</wantNonLocal>\n            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<state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>D:\\GitHub\\ARM-software\\CMSIS_5\\CMSIS\\RTOS\\RTX\\SRC\\IAR\\CM3_BE\\RTX_Lib_CM.a</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>BILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <configuration>\n        <name>CM4F_LE</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>31</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>ExePath</name>\n                    <state>CM4F_LE</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>CM4F_LE</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>CM4F_LE</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>6.30.3.53229</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>8.32.3.20186</state>\n                </option>\n                <option>\n                    <name>GeneralEnableMisra</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraVerbose</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GeneralMisraRules98</name>\n                    <version>0</version>\n                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                </option>\n                <option>\n                    <name>GeneralMisraVer</name>\n                    <state>0</state>\n                </option>\n              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<state></state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    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<option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>10</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n         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       <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n   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<name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n             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        <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>D:\\GitHub\\ARM-software\\CMSIS_5\\CMSIS\\RTOS\\RTX\\SRC\\IAR\\CM4F_BE\\RTX_Lib_CM.a</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>BILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data />\n        </settings>\n    </configuration>\n    <group>\n        <name>HAL</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\HAL_CM.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\HAL_CM0.s</name>\n            <excluded>\n                <configuration>CM3_LE</configuration>\n                <configuration>CM3_BE</configuration>\n                <configuration>CM4F_LE</configuration>\n                <configuration>CM4F_BE</configuration>\n            </excluded>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\HAL_CM3.s</name>\n            <excluded>\n                <configuration>CM0_LE</configuration>\n                <configuration>CM0_BE</configuration>\n                <configuration>CM4F_LE</configuration>\n                <configuration>CM4F_BE</configuration>\n            </excluded>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\HAL_CM4.s</name>\n            <excluded>\n                <configuration>CM0_LE</configuration>\n                <configuration>CM0_BE</configuration>\n                <configuration>CM3_LE</configuration>\n                <configuration>CM3_BE</configuration>\n            </excluded>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\SVC_Table.s</name>\n        </file>\n    </group>\n    <group>\n        <name>Kernel</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_CMSIS.c</name>\n            <configuration>\n                <name>CM0_LE</name>\n                <settings>\n                    <name>ICCARM</name>\n                    <data>\n                        <version>35</version>\n                        <wantNonLocal>1</wantNonLocal>\n                        <debug>0</debug>\n                        <option>\n                            <name>CCOptimizationNoSizeConstraints</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDefines</name>\n                            <state>__CORTEX_M0</state>\n                            <state>__CMSIS_RTOS</state>\n                            <state>DBG_MSG</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocComments</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocLine</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMnemonics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMessages</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEnableRemarks</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagSuppress</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagRemark</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarning</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagError</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCObjPrefix</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCAllowList</name>\n                            <version>1</version>\n                            <state>11111110</state>\n                        </option>\n                        <option>\n                            <name>CCDebugInfo</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IEndianMode</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptionsCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptions</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCLangConformance</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCSignedPlainChar</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCRequirePrototypes</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarnAreErr</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCompilerRuntimeInfo</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IFpuProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>OutputFile</name>\n                            <state>$FILE_BNAME$.o</state>\n                        </option>\n                        <option>\n                            <name>CCLibConfigHeader</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>PreInclude</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraOverride</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCIncludePath2</name>\n                            <state>$PROJ_DIR$\\..\\..\\INC</state>\n                        </option>\n                        <option>\n                            <name>CCStdIncCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCodeSection</name>\n                            <state>.text</state>\n                        </option>\n                        <option>\n                            <name>IProcessorMode2</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevel</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategy</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevelSlave</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules98</name>\n                            <version>0</version>\n                            <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules04</name>\n                            <version>0</version>\n                            <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRopi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRwpi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndNoDynInit</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccLang</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCDialect</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccAllowVLA</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccStaticDestr</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccCppInlineSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCmsis</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccFloatSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCNoLiteralPool</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategySlave</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCGuardCalls</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutputBom</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncInput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccExceptions2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccRTTI2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>OICompilerExtraOption</name>\n                            <state>1</state>\n                        </option>\n                    </data>\n                </settings>\n            </configuration>\n            <configuration>\n                <name>CM0_BE</name>\n                <settings>\n                    <name>ICCARM</name>\n                    <data>\n                        <version>35</version>\n                        <wantNonLocal>1</wantNonLocal>\n                        <debug>0</debug>\n                        <option>\n                            <name>CCOptimizationNoSizeConstraints</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDefines</name>\n                            <state>__CORTEX_M0</state>\n                            <state>__CMSIS_RTOS</state>\n                            <state>DBG_MSG</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocComments</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocLine</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMnemonics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMessages</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEnableRemarks</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagSuppress</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagRemark</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarning</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagError</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCObjPrefix</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCAllowList</name>\n                            <version>1</version>\n                            <state>11111110</state>\n                        </option>\n                        <option>\n                            <name>CCDebugInfo</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IEndianMode</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptionsCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptions</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCLangConformance</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCSignedPlainChar</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCRequirePrototypes</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarnAreErr</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCompilerRuntimeInfo</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IFpuProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>OutputFile</name>\n                            <state>$FILE_BNAME$.o</state>\n                        </option>\n                        <option>\n                            <name>CCLibConfigHeader</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>PreInclude</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraOverride</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCIncludePath2</name>\n                            <state>$PROJ_DIR$\\..\\..\\INC</state>\n                        </option>\n                        <option>\n                            <name>CCStdIncCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCodeSection</name>\n                            <state>.text</state>\n                        </option>\n                        <option>\n                            <name>IProcessorMode2</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevel</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategy</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevelSlave</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules98</name>\n                            <version>0</version>\n                            <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules04</name>\n                            <version>0</version>\n                            <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRopi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRwpi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndNoDynInit</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccLang</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCDialect</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccAllowVLA</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccStaticDestr</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccCppInlineSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCmsis</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccFloatSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCNoLiteralPool</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategySlave</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCGuardCalls</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutputBom</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncInput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccExceptions2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccRTTI2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>OICompilerExtraOption</name>\n                            <state>1</state>\n                        </option>\n                    </data>\n                </settings>\n            </configuration>\n            <configuration>\n                <name>CM3_LE</name>\n                <settings>\n                    <name>ICCARM</name>\n                    <data>\n                        <version>35</version>\n                        <wantNonLocal>1</wantNonLocal>\n                        <debug>0</debug>\n                        <option>\n                            <name>CCOptimizationNoSizeConstraints</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDefines</name>\n                            <state>__CORTEX_M3</state>\n                            <state>__CMSIS_RTOS</state>\n                            <state>DBG_MSG</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocComments</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocLine</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMnemonics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMessages</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEnableRemarks</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagSuppress</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagRemark</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarning</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagError</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCObjPrefix</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCAllowList</name>\n                            <version>1</version>\n                            <state>11111110</state>\n                        </option>\n                        <option>\n                            <name>CCDebugInfo</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IEndianMode</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptionsCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptions</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCLangConformance</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCSignedPlainChar</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCRequirePrototypes</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarnAreErr</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCompilerRuntimeInfo</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IFpuProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>OutputFile</name>\n                            <state>$FILE_BNAME$.o</state>\n                        </option>\n                        <option>\n                            <name>CCLibConfigHeader</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>PreInclude</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraOverride</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCIncludePath2</name>\n                            <state>$PROJ_DIR$\\..\\..\\INC</state>\n                        </option>\n                        <option>\n                            <name>CCStdIncCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCodeSection</name>\n                            <state>.text</state>\n                        </option>\n                        <option>\n                            <name>IProcessorMode2</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevel</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategy</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevelSlave</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules98</name>\n                            <version>0</version>\n                            <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules04</name>\n                            <version>0</version>\n                            <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRopi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRwpi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndNoDynInit</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccLang</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCDialect</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccAllowVLA</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccStaticDestr</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccCppInlineSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCmsis</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccFloatSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCNoLiteralPool</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategySlave</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCGuardCalls</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutputBom</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncInput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccExceptions2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccRTTI2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>OICompilerExtraOption</name>\n                            <state>1</state>\n                        </option>\n                    </data>\n                </settings>\n            </configuration>\n            <configuration>\n                <name>CM3_BE</name>\n                <settings>\n                    <name>ICCARM</name>\n                    <data>\n                        <version>35</version>\n                        <wantNonLocal>1</wantNonLocal>\n                        <debug>0</debug>\n                        <option>\n                            <name>CCOptimizationNoSizeConstraints</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDefines</name>\n                            <state>__CORTEX_M3</state>\n                            <state>__CMSIS_RTOS</state>\n                            <state>DBG_MSG</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocComments</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocLine</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMnemonics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMessages</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEnableRemarks</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagSuppress</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagRemark</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarning</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagError</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCObjPrefix</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCAllowList</name>\n                            <version>1</version>\n                            <state>11111110</state>\n                        </option>\n                        <option>\n                            <name>CCDebugInfo</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IEndianMode</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptionsCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptions</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCLangConformance</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCSignedPlainChar</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCRequirePrototypes</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarnAreErr</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCompilerRuntimeInfo</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IFpuProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>OutputFile</name>\n                            <state>$FILE_BNAME$.o</state>\n                        </option>\n                        <option>\n                            <name>CCLibConfigHeader</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>PreInclude</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraOverride</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCIncludePath2</name>\n                            <state>$PROJ_DIR$\\..\\..\\INC</state>\n                        </option>\n                        <option>\n                            <name>CCStdIncCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCodeSection</name>\n                            <state>.text</state>\n                        </option>\n                        <option>\n                            <name>IProcessorMode2</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevel</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategy</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevelSlave</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules98</name>\n                            <version>0</version>\n                            <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules04</name>\n                            <version>0</version>\n                            <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRopi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRwpi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndNoDynInit</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccLang</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCDialect</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccAllowVLA</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccStaticDestr</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccCppInlineSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCmsis</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccFloatSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCNoLiteralPool</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategySlave</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCGuardCalls</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutputBom</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncInput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccExceptions2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccRTTI2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>OICompilerExtraOption</name>\n                            <state>1</state>\n                        </option>\n                    </data>\n                </settings>\n            </configuration>\n            <configuration>\n                <name>CM4F_LE</name>\n                <settings>\n                    <name>ICCARM</name>\n                    <data>\n                        <version>35</version>\n                        <wantNonLocal>1</wantNonLocal>\n                        <debug>0</debug>\n                        <option>\n                            <name>CCOptimizationNoSizeConstraints</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDefines</name>\n                            <state>__CORTEX_M4F</state>\n                            <state>__CMSIS_RTOS</state>\n                            <state>DBG_MSG</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocComments</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocLine</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMnemonics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMessages</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEnableRemarks</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagSuppress</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagRemark</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarning</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagError</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCObjPrefix</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCAllowList</name>\n                            <version>1</version>\n                            <state>11111110</state>\n                        </option>\n                        <option>\n                            <name>CCDebugInfo</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IEndianMode</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptionsCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptions</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCLangConformance</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCSignedPlainChar</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCRequirePrototypes</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarnAreErr</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCompilerRuntimeInfo</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IFpuProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>OutputFile</name>\n                            <state>$FILE_BNAME$.o</state>\n                        </option>\n                        <option>\n                            <name>CCLibConfigHeader</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>PreInclude</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraOverride</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCIncludePath2</name>\n                            <state>$PROJ_DIR$\\..\\..\\INC</state>\n                        </option>\n                        <option>\n                            <name>CCStdIncCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCodeSection</name>\n                            <state>.text</state>\n                        </option>\n                        <option>\n                            <name>IProcessorMode2</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevel</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategy</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevelSlave</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules98</name>\n                            <version>0</version>\n                            <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules04</name>\n                            <version>0</version>\n                            <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRopi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRwpi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndNoDynInit</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccLang</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCDialect</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccAllowVLA</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccStaticDestr</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccCppInlineSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCmsis</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccFloatSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCNoLiteralPool</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategySlave</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCGuardCalls</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutputBom</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncInput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccExceptions2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccRTTI2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>OICompilerExtraOption</name>\n                            <state>1</state>\n                        </option>\n                    </data>\n                </settings>\n            </configuration>\n            <configuration>\n                <name>CM4F_BE</name>\n                <settings>\n                    <name>ICCARM</name>\n                    <data>\n                        <version>35</version>\n                        <wantNonLocal>1</wantNonLocal>\n                        <debug>0</debug>\n                        <option>\n                            <name>CCOptimizationNoSizeConstraints</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDefines</name>\n                            <state>__CORTEX_M4F</state>\n                            <state>__CMSIS_RTOS</state>\n                            <state>DBG_MSG</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocComments</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPreprocLine</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMnemonics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListCMessages</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssFile</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCListAssSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEnableRemarks</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagSuppress</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagRemark</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarning</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCDiagError</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCObjPrefix</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCAllowList</name>\n                            <version>1</version>\n                            <state>11111110</state>\n                        </option>\n                        <option>\n                            <name>CCDebugInfo</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IEndianMode</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptionsCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IExtraOptions</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CCLangConformance</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCSignedPlainChar</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCRequirePrototypes</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCDiagWarnAreErr</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCompilerRuntimeInfo</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IFpuProcessor</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>OutputFile</name>\n                            <state>$FILE_BNAME$.o</state>\n                        </option>\n                        <option>\n                            <name>CCLibConfigHeader</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>PreInclude</name>\n                            <state></state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraOverride</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCIncludePath2</name>\n                            <state>$PROJ_DIR$\\..\\..\\INC</state>\n                        </option>\n                        <option>\n                            <name>CCStdIncCheck</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCCodeSection</name>\n                            <state>.text</state>\n                        </option>\n                        <option>\n                            <name>IProcessorMode2</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevel</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategy</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptLevelSlave</name>\n                            <state>3</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules98</name>\n                            <version>0</version>\n                            <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CompilerMisraRules04</name>\n                            <version>0</version>\n                            <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRopi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndRwpi</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCPosIndNoDynInit</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccLang</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCDialect</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccAllowVLA</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccStaticDestr</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccCppInlineSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccCmsis</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>IccFloatSemantics</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCNoLiteralPool</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCOptStrategySlave</name>\n                            <version>0</version>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCGuardCalls</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncSource</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>CCEncOutputBom</name>\n                            <state>1</state>\n                        </option>\n                        <option>\n                            <name>CCEncInput</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccExceptions2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>IccRTTI2</name>\n                            <state>0</state>\n                        </option>\n                        <option>\n                            <name>OICompilerExtraOption</name>\n                            <state>1</state>\n                        </option>\n                    </data>\n                </settings>\n            </configuration>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_Event.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_List.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_Mailbox.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_MemBox.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_Memory.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_Mutex.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_Robin.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_Semaphore.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_System.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_Task.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_Time.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\rt_Timer.c</name>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/IAR/RTX_Lib_CM.eww",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<workspace>\n    <project>\n        <path>$WS_DIR$\\RTX_Lib_CM.ewp</path>\n    </project>\n    <batchBuild>\n        <batchDefinition>\n            <name>RTX_Lib_CM</name>\n            <member>\n                <project>RTX_Lib_CM</project>\n                <configuration>CM0_LE</configuration>\n            </member>\n            <member>\n                <project>RTX_Lib_CM</project>\n                <configuration>CM0_BE</configuration>\n            </member>\n            <member>\n                <project>RTX_Lib_CM</project>\n                <configuration>CM3_LE</configuration>\n            </member>\n            <member>\n                <project>RTX_Lib_CM</project>\n                <configuration>CM3_BE</configuration>\n            </member>\n            <member>\n                <project>RTX_Lib_CM</project>\n                <configuration>CM4F_LE</configuration>\n            </member>\n            <member>\n                <project>RTX_Lib_CM</project>\n                <configuration>CM4F_BE</configuration>\n            </member>\n        </batchDefinition>\n    </batchBuild>\n</workspace>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s",
    "content": ";/*----------------------------------------------------------------------------\n; *      CMSIS-RTOS  -  RTX\n; *----------------------------------------------------------------------------\n; *      Name:    SVC_TABLE.S\n; *      Purpose: Pre-defined SVC Table for Cortex-M\n; *      Rev.:    V4.70\n; *----------------------------------------------------------------------------\n; *\n; * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH\n; * All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *---------------------------------------------------------------------------*/\n\n\n                NAME    SVC_TABLE\n                SECTION .text:CONST (2)\n\n                PUBLIC  SVC_Count\n\nSVC_Cnt         EQU    (SVC_End-SVC_Table)/4\nSVC_Count       DCD     SVC_Cnt\n\n; Import user SVC functions here.\n;               IMPORT  __SVC_1\n\n                PUBLIC  SVC_Table\nSVC_Table\n; Insert user SVC functions here. SVC 0 used by RTL Kernel.\n;               DCD     __SVC_1                 ; user SVC function\n\nSVC_End\n\n                END\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/RTX_Config.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RTX_CONFIG.H\n *      Purpose: Exported functions of RTX_Config.c\n *      Rev.:    V4.81\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include <stdint.h>\n\n/* Error Codes */\n#define OS_ERR_STK_OVF          1U\n#define OS_ERR_FIFO_OVF         2U\n#define OS_ERR_MBX_OVF          3U\n#define OS_ERR_TIMER_OVF        4U\n\n/* Definitions */\n#define BOX_ALIGN_8                   0x80000000U\n#define _declare_box(pool,size,cnt)   U32 pool[(((size)+3)/4)*(cnt) + 3]\n#define _declare_box8(pool,size,cnt)  U64 pool[(((size)+7)/8)*(cnt) + 2]\n#define _init_box8(pool,size,bsize)   _init_box (pool,size,(bsize) | BOX_ALIGN_8)\n\n/* Variables */\nextern U32 mp_tcb[];\nextern U64 mp_stk[];\nextern U32 os_fifo[];\nextern void *os_active_TCB[];\n\n/* Constants */\nextern U16 const os_maxtaskrun;\nextern U32 const os_trv;\nextern U8  const os_flags;\nextern U32 const os_stackinfo;\nextern U32 const os_rrobin;\nextern U32 const os_clockrate;\nextern U32 const os_timernum;\nextern U16 const mp_tcb_size;\nextern U32 const mp_stk_size;\nextern U32 const *m_tmr;\nextern U16 const mp_tmr_size;\nextern U8  const os_fifo_size;\n\n/* Functions */\nextern void os_idle_demon   (void);\nextern S32  os_tick_init    (void);\nextern U32  os_tick_val     (void);\nextern U32  os_tick_ovf     (void);\nextern void os_tick_irqack  (void);\nextern void os_tmr_call     (U16 info);\nextern void os_error        (uint32_t err_code);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_CMSIS.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    rt_CMSIS.c\n *      Purpose: CMSIS RTOS API\n *      Rev.:    V4.82\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#define __CMSIS_GENERIC\n\n#if defined (__CORTEX_M4) || defined (__CORTEX_M4F)\n#include \"core_cm4.h\"\n#elif defined (__CORTEX_M3)\n#include \"core_cm3.h\"\n#elif defined (__CORTEX_M0)\n#include \"core_cm0.h\"\n#else\n#error \"Missing __CORTEX_Mx definition\"\n#endif\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_Task.h\"\n#include \"rt_Event.h\"\n#include \"rt_List.h\"\n#include \"rt_Time.h\"\n#include \"rt_Mutex.h\"\n#include \"rt_Semaphore.h\"\n#include \"rt_Mailbox.h\"\n#include \"rt_MemBox.h\"\n#include \"rt_Memory.h\"\n#include \"rt_HAL_CM.h\"\n\n#define os_thread_cb OS_TCB\n\n#include \"cmsis_os.h\"\n\n#if (osFeature_Signals != 16)\n#error Invalid \"osFeature_Signals\" value!\n#endif\n#if (osFeature_Semaphore > 65535)\n#error Invalid \"osFeature_Semaphore\" value!\n#endif\n#if (osFeature_Wait != 0)\n#error osWait not supported!\n#endif\n\n\n// ==== Enumeration, structures, defines ====\n\n// Service Calls defines\n\n#if defined (__CC_ARM)          /* ARM Compiler */\n\n#define __NO_RETURN __declspec(noreturn)\n\n#define osEvent_type       osEvent\n#define osEvent_ret_status ret\n#define osEvent_ret_value  ret\n#define osEvent_ret_msg    ret\n#define osEvent_ret_mail   ret\n\n#define osCallback_type    osCallback\n#define osCallback_ret     ret\n\n#define SVC_0_1(f,t,...)                                                       \\\n__svc_indirect(0) t  _##f (t(*)());                                            \\\n                  t     f (void);                                              \\\n__attribute__((always_inline))                                                 \\\nstatic __inline   t __##f (void) {                                             \\\n  return _##f(f);                                                              \\\n}\n\n#define SVC_1_0(f,t,t1,...)                                                    \\\n__svc_indirect(0) t  _##f (t(*)(t1),t1);                                       \\\n                  t     f (t1 a1);                                             \\\n__attribute__((always_inline))                                                 \\\nstatic __inline   t __##f (t1 a1) {                                            \\\n  _##f(f,a1);                                                                  \\\n}\n\n#define SVC_1_1(f,t,t1,...)                                                    \\\n__svc_indirect(0) t  _##f (t(*)(t1),t1);                                       \\\n                  t     f (t1 a1);                                             \\\n__attribute__((always_inline))                                                 \\\nstatic __inline   t __##f (t1 a1) {                                            \\\n  return _##f(f,a1);                                                           \\\n}\n\n#define SVC_2_1(f,t,t1,t2,...)                                                 \\\n__svc_indirect(0) t  _##f (t(*)(t1,t2),t1,t2);                                 \\\n                  t     f (t1 a1, t2 a2);                                      \\\n__attribute__((always_inline))                                                 \\\nstatic __inline   t __##f (t1 a1, t2 a2) {                                     \\\n  return _##f(f,a1,a2);                                                        \\\n}\n\n#define SVC_3_1(f,t,t1,t2,t3,...)                                              \\\n__svc_indirect(0) t  _##f (t(*)(t1,t2,t3),t1,t2,t3);                           \\\n                  t     f (t1 a1, t2 a2, t3 a3);                               \\\n__attribute__((always_inline))                                                 \\\nstatic __inline   t __##f (t1 a1, t2 a2, t3 a3) {                              \\\n  return _##f(f,a1,a2,a3);                                                     \\\n}\n\n#define SVC_4_1(f,t,t1,t2,t3,t4,...)                                           \\\n__svc_indirect(0) t  _##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4);                     \\\n                  t     f (t1 a1, t2 a2, t3 a3, t4 a4);                        \\\n__attribute__((always_inline))                                                 \\\nstatic __inline   t __##f (t1 a1, t2 a2, t3 a3, t4 a4) {                       \\\n  return _##f(f,a1,a2,a3,a4);                                                  \\\n}\n\n#define SVC_1_2 SVC_1_1 \n#define SVC_1_3 SVC_1_1 \n#define SVC_2_3 SVC_2_1 \n\n#elif defined (__GNUC__)        /* GNU Compiler */\n\n#define __NO_RETURN __attribute__((noreturn))\n\ntypedef uint32_t __attribute__((vector_size(8))) ret64;\ntypedef uint32_t __attribute__((vector_size(16))) ret128;\n\n#define RET_pointer    __r0\n#define RET_int32_t    __r0\n#define RET_uint32_t   __r0\n#define RET_osStatus   __r0\n#define RET_osPriority __r0\n#define RET_osEvent    {(osStatus)__r0, {(uint32_t)__r1}, {(void *)__r2}}\n#define RET_osCallback {(void *)__r0, (void *)__r1}\n\n#define osEvent_type       __attribute__((pcs(\"aapcs\"))) ret128\n#define osEvent_ret_status (ret128){ret.status}\n#define osEvent_ret_value  (ret128){ret.status, ret.value.v}\n#define osEvent_ret_msg    (ret128){ret.status, ret.value.v, (uint32_t)ret.def.message_id}\n#define osEvent_ret_mail   (ret128){ret.status, ret.value.v, (uint32_t)ret.def.mail_id}\n\n#define osCallback_type    __attribute__((pcs(\"aapcs\"))) ret64\n#define osCallback_ret     (ret64) {(uint32_t)ret.fp, (uint32_t)ret.arg}\n\n#define SVC_ArgN(n) \\\n  register int __r##n __asm(\"r\"#n);\n\n#define SVC_ArgR(n, t, a) \\\n  register t   __r##n __asm(\"r\"#n) = a;\n\n#define SVC_Arg0()                                                             \\\n  SVC_ArgN(0)                                                                  \\\n  SVC_ArgN(1)                                                                  \\\n  SVC_ArgN(2)                                                                  \\\n  SVC_ArgN(3)\n\n#define SVC_Arg1(t1)                                                           \\\n  SVC_ArgR(0,t1,a1)                                                            \\\n  SVC_ArgN(1)                                                                  \\\n  SVC_ArgN(2)                                                                  \\\n  SVC_ArgN(3)\n\n#define SVC_Arg2(t1, t2)                                                        \\\n  SVC_ArgR(0,t1,a1)                                                            \\\n  SVC_ArgR(1,t2,a2)                                                            \\\n  SVC_ArgN(2)                                                                  \\\n  SVC_ArgN(3)\n\n#define SVC_Arg3(t1, t2, t3)                                                     \\\n  SVC_ArgR(0,t1,a1)                                                            \\\n  SVC_ArgR(1,t2,a2)                                                            \\\n  SVC_ArgR(2,t3,a3)                                                            \\\n  SVC_ArgN(3)\n\n#define SVC_Arg4(t1, t2, t3, t4)                                                  \\\n  SVC_ArgR(0,t1,a1)                                                            \\\n  SVC_ArgR(1,t2,a2)                                                            \\\n  SVC_ArgR(2,t3,a3)                                                            \\\n  SVC_ArgR(3,t4,a4)\n\n#if (defined (__CORTEX_M0))\n#define SVC_Call(f)                                                            \\\n  __asm volatile                                                               \\\n  (                                                                            \\\n    \"ldr r7,=\"#f\"\\n\\t\"                                                         \\\n    \"mov r12,r7\\n\\t\"                                                           \\\n    \"svc 0\"                                                                    \\\n    :               \"=r\" (__r0), \"=r\" (__r1), \"=r\" (__r2), \"=r\" (__r3)         \\\n    :                \"r\" (__r0),  \"r\" (__r1),  \"r\" (__r2),  \"r\" (__r3)         \\\n    : \"r7\", \"r12\", \"lr\", \"cc\"                                                  \\\n  );\n#else\n#define SVC_Call(f)                                                            \\\n  __asm volatile                                                               \\\n  (                                                                            \\\n    \"ldr r12,=\"#f\"\\n\\t\"                                                        \\\n    \"svc 0\"                                                                    \\\n    :               \"=r\" (__r0), \"=r\" (__r1), \"=r\" (__r2), \"=r\" (__r3)         \\\n    :                \"r\" (__r0),  \"r\" (__r1),  \"r\" (__r2),  \"r\" (__r3)         \\\n    : \"r12\", \"lr\", \"cc\"                                                        \\\n  );\n#endif\n\n#define SVC_0_1(f, t, rv)                                                        \\\n__attribute__((always_inline))                                                 \\\nstatic inline  t __##f (void) {                                                \\\n  SVC_Arg0();                                                                  \\\n  SVC_Call(f);                                                                 \\\n  return (t) rv;                                                               \\\n}\n\n#define SVC_1_0(f, t, t1)                                                        \\\n__attribute__((always_inline))                                                 \\\nstatic inline  t __##f (t1 a1) {                                               \\\n  SVC_Arg1(t1);                                                                \\\n  SVC_Call(f);                                                                 \\\n}\n\n#define SVC_1_1(f, t, t1, rv)                                                     \\\n__attribute__((always_inline))                                                 \\\nstatic inline  t __##f (t1 a1) {                                               \\\n  SVC_Arg1(t1);                                                                \\\n  SVC_Call(f);                                                                 \\\n  return (t) rv;                                                               \\\n}\n\n#define SVC_2_1(f, t, t1, t2, rv)                                                  \\\n__attribute__((always_inline))                                                 \\\nstatic inline  t __##f (t1 a1, t2 a2) {                                        \\\n  SVC_Arg2(t1,t2);                                                             \\\n  SVC_Call(f);                                                                 \\\n  return (t) rv;                                                               \\\n}\n\n#define SVC_3_1(f, t, t1, t2, t3, rv)                                               \\\n__attribute__((always_inline))                                                 \\\nstatic inline  t __##f (t1 a1, t2 a2, t3 a3) {                                 \\\n  SVC_Arg3(t1,t2,t3);                                                          \\\n  SVC_Call(f);                                                                 \\\n  return (t) rv;                                                               \\\n}\n\n#define SVC_4_1(f, t, t1, t2, t3, t4, rv)                                            \\\n__attribute__((always_inline))                                                 \\\nstatic inline  t __##f (t1 a1, t2 a2, t3 a3, t4 a4) {                          \\\n  SVC_Arg4(t1,t2,t3,t4);                                                       \\\n  SVC_Call(f);                                                                 \\\n  return (t) rv;                                                               \\\n}\n\n#define SVC_1_2 SVC_1_1\n#define SVC_1_3 SVC_1_1\n#define SVC_2_3 SVC_2_1\n\n#elif defined (__ICCARM__)      /* IAR Compiler */\n\n#define __NO_RETURN __noreturn\n\n#define RET_osEvent        \"=r\"(ret.status), \"=r\"(ret.value), \"=r\"(ret.def)\n#define RET_osCallback     \"=r\"(ret.fp), \"=r\"(ret.arg)\n\n#define osEvent_type       osEvent\n#define osEvent_ret_status ret\n#define osEvent_ret_value  ret\n#define osEvent_ret_msg    ret\n#define osEvent_ret_mail   ret\n\n#define osCallback_type    uint64_t\n#define osCallback_ret     ((uint64_t)ret.fp | ((uint64_t)ret.arg)<<32)\n\n#define SVC_Setup(f)                                                           \\\n  __asm(                                                                       \\\n    \"mov r12,%0\\n\"                                                             \\\n    :: \"r\"(&f): \"r12\"                                                          \\\n  );\n\n#define SVC_Ret3()                                                             \\\n  __asm(                                                                       \\\n    \"ldr r0,[sp,#0]\\n\"                                                         \\\n    \"ldr r1,[sp,#4]\\n\"                                                         \\\n    \"ldr r2,[sp,#8]\\n\"                                                         \\\n  );\n\n#define SVC_0_1(f,t,...)                                                       \\\nt f (void);                                                                    \\\n_Pragma(\"swi_number=0\") __swi t _##f (void);                                   \\\nstatic inline t __##f (void) {                                                 \\\n  SVC_Setup(f);                                                                \\\n  return _##f();                                                               \\\n}\n\n#define SVC_1_0(f,t,t1,...)                                                    \\\nt f (t1 a1);                                                                   \\\n_Pragma(\"swi_number=0\") __swi t _##f (t1 a1);                                  \\\nstatic inline t __##f (t1 a1) {                                                \\\n  SVC_Setup(f);                                                                \\\n  _##f(a1);                                                                    \\\n}\n\n#define SVC_1_1(f,t,t1,...)                                                    \\\nt f (t1 a1);                                                                   \\\n_Pragma(\"swi_number=0\") __swi t _##f (t1 a1);                                  \\\nstatic inline t __##f (t1 a1) {                                                \\\n  SVC_Setup(f);                                                                \\\n  return _##f(a1);                                                             \\\n}\n\n#define SVC_2_1(f,t,t1,t2,...)                                                 \\\nt f (t1 a1, t2 a2);                                                            \\\n_Pragma(\"swi_number=0\") __swi t _##f (t1 a1, t2 a2);                           \\\nstatic inline t __##f (t1 a1, t2 a2) {                                         \\\n  SVC_Setup(f);                                                                \\\n  return _##f(a1,a2);                                                          \\\n}\n\n#define SVC_3_1(f,t,t1,t2,t3,...)                                              \\\nt f (t1 a1, t2 a2, t3 a3);                                                     \\\n_Pragma(\"swi_number=0\") __swi t _##f (t1 a1, t2 a2, t3 a3);                    \\\nstatic inline t __##f (t1 a1, t2 a2, t3 a3) {                                  \\\n  SVC_Setup(f);                                                                \\\n  return _##f(a1,a2,a3);                                                       \\\n}\n\n#define SVC_4_1(f,t,t1,t2,t3,t4,...)                                           \\\nt f (t1 a1, t2 a2, t3 a3, t4 a4);                                              \\\n_Pragma(\"swi_number=0\") __swi t _##f (t1 a1, t2 a2, t3 a3, t4 a4);             \\\nstatic inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) {                           \\\n  SVC_Setup(f);                                                                \\\n  return _##f(a1,a2,a3,a4);                                                    \\\n}\n\n#define SVC_1_2(f,t,t1,rr)                                                     \\\nuint64_t f (t1 a1);                                                            \\\n_Pragma(\"swi_number=0\") __swi uint64_t _##f (t1 a1);                           \\\nstatic inline t __##f (t1 a1) {                                                \\\n  t ret;                                                                       \\\n  SVC_Setup(f);                                                                \\\n  _##f(a1);                                                                    \\\n  __asm(\"\" : rr : :);                                                          \\\n  return ret;                                                                  \\\n}\n\n#define SVC_1_3(f,t,t1,rr)                                                     \\\nt f (t1 a1);                                                                   \\\nvoid f##_ (t1 a1) {                                                            \\\n  f(a1);                                                                       \\\n  SVC_Ret3();                                                                  \\\n}                                                                              \\\n_Pragma(\"swi_number=0\") __swi void _##f (t1 a1);                               \\\nstatic inline t __##f (t1 a1) {                                                \\\n  t ret;                                                                       \\\n  SVC_Setup(f##_);                                                             \\\n  _##f(a1);                                                                    \\\n  __asm(\"\" : rr : :);                                                          \\\n  return ret;                                                                  \\\n}\n\n#define SVC_2_3(f,t,t1,t2,rr)                                                  \\\nt f (t1 a1, t2 a2);                                                            \\\nvoid f##_ (t1 a1, t2 a2) {                                                     \\\n  f(a1,a2);                                                                    \\\n  SVC_Ret3();                                                                  \\\n}                                                                              \\\n_Pragma(\"swi_number=0\") __swi void _##f (t1 a1, t2 a2);                        \\\nstatic inline t __##f (t1 a1, t2 a2) {                                         \\\n  t ret;                                                                       \\\n  SVC_Setup(f##_);                                                             \\\n  _##f(a1,a2);                                                                 \\\n  __asm(\"\" : rr : :);                                                          \\\n  return ret;                                                                  \\\n}\n\n#endif\n\n\n// Callback structure\ntypedef struct {\n    void *fp;             // Function pointer\n    void *arg;            // Function argument\n} osCallback;\n\n\n// OS Section definitions\n#ifdef OS_SECTIONS_LINK_INFO\nextern const uint32_t  os_section_id$$Base;\nextern const uint32_t  os_section_id$$Limit;\n#endif\n\n// OS Stack Memory for Threads definitions\nextern uint64_t os_stack_mem[];\nextern const uint32_t os_stack_sz;\n\n// OS Timers external resources\nextern const osThreadDef_t os_thread_def_osTimerThread;\nextern osThreadId osThreadId_osTimerThread;\nextern const osMessageQDef_t os_messageQ_def_osTimerMessageQ;\nextern osMessageQId osMessageQId_osTimerMessageQ;\n\n\n// ==== Helper Functions ====\n\n/// Convert timeout in millisec to system ticks\nstatic uint16_t rt_ms2tick(uint32_t millisec) {\n    uint32_t tick;\n\n    if (millisec == 0U) { return 0x0U; }                  // No timeout\n    if (millisec == osWaitForever) { return 0xFFFFU; }    // Indefinite timeout\n    if (millisec > 4000000U) { return 0xFFFEU; }          // Max ticks supported\n\n    tick = ((1000U * millisec) + os_clockrate - 1U) / os_clockrate;\n    if (tick > 0xFFFEU) { return 0xFFFEU; }\n\n    return (uint16_t) tick;\n}\n\n/// Convert Thread ID to TCB pointer\nstatic P_TCB rt_tid2ptcb(osThreadId thread_id) {\n    P_TCB ptcb;\n\n    if (thread_id == NULL) { return NULL; }\n\n    if ((uint32_t) thread_id & 3U) { return NULL; }\n\n#ifdef OS_SECTIONS_LINK_INFO\n    if ((os_section_id$$Base != 0U) && (os_section_id$$Limit != 0U)) {\n      if (thread_id  < (osThreadId)os_section_id$$Base)  { return NULL; }\n      if (thread_id >= (osThreadId)os_section_id$$Limit) { return NULL; }\n    }\n#endif\n\n    ptcb = thread_id;\n\n    if (ptcb->cb_type != TCB) { return NULL; }\n\n    return ptcb;\n}\n\n/// Convert ID pointer to Object pointer\nstatic void *rt_id2obj(void *id) {\n\n    if ((uint32_t) id & 3U) { return NULL; }\n\n#ifdef OS_SECTIONS_LINK_INFO\n    if ((os_section_id$$Base != 0U) && (os_section_id$$Limit != 0U)) {\n      if (id  < (void *)os_section_id$$Base)  { return NULL; }\n      if (id >= (void *)os_section_id$$Limit) { return NULL; }\n    }\n#endif\n\n    return id;\n}\n\n\n// ==== Kernel Control ====\n\nuint8_t os_initialized;                         // Kernel Initialized flag\nuint8_t os_running;                             // Kernel Running flag\n\n// Kernel Control Service Calls declarations\nSVC_0_1(svcKernelInitialize, osStatus, RET_osStatus)\n\nSVC_0_1(svcKernelStart, osStatus, RET_osStatus)\n\nSVC_0_1(svcKernelRunning, int32_t, RET_int32_t)\n\nSVC_0_1(svcKernelSysTick, uint32_t, RET_uint32_t)\n\nstatic void sysThreadError(osStatus status);\n\nosThreadId svcThreadCreate(const osThreadDef_t *thread_def, void *argument);\n\nosMessageQId svcMessageCreate(const osMessageQDef_t *queue_def, osThreadId thread_id);\n\n// Kernel Control Service Calls\n\n/// Initialize the RTOS Kernel for creating objects\nosStatus svcKernelInitialize(void) {\n    uint32_t ret;\n\n    if (os_initialized == 0U) {\n\n        // Init Thread Stack Memory (must be 8-byte aligned)\n        if (((uint32_t) os_stack_mem & 7U) != 0U) { return osErrorNoMemory; }\n        ret = rt_init_mem(os_stack_mem, os_stack_sz);\n        if (ret != 0U) { return osErrorNoMemory; }\n\n        rt_sys_init();                              // RTX System Initialization\n    }\n\n    os_tsk.run->prio = 255U;                      // Highest priority\n\n    if (os_initialized == 0U) {\n        // Create OS Timers resources (Message Queue & Thread)\n        osMessageQId_osTimerMessageQ = svcMessageCreate(&os_messageQ_def_osTimerMessageQ, NULL);\n        osThreadId_osTimerThread = svcThreadCreate(&os_thread_def_osTimerThread, NULL);\n    }\n\n    sysThreadError(osOK);\n\n    os_initialized = 1U;\n    os_running = 0U;\n\n    return osOK;\n}\n\n/// Start the RTOS Kernel\nosStatus svcKernelStart(void) {\n\n    if (os_running) { return osOK; }\n\n    rt_tsk_prio(0U, os_tsk.run->prio_base);       // Restore priority\n    if (os_tsk.run->task_id == 0xFFU) {           // Idle Thread\n        __set_PSP(os_tsk.run->tsk_stack + (8U * 4U)); // Setup PSP\n    }\n    if (os_tsk.next == NULL) {                    // Force context switch\n        os_tsk.next = os_tsk.run;\n        os_tsk.run = NULL;\n    }\n\n    rt_sys_start();\n\n    os_running = 1U;\n\n    return osOK;\n}\n\n/// Check if the RTOS kernel is already started\nint32_t svcKernelRunning(void) {\n    return (int32_t) os_running;\n}\n\n/// Get the RTOS kernel system timer counter\nuint32_t svcKernelSysTick(void) {\n    uint32_t tick, tick0;\n\n    tick = os_tick_val();\n    if (os_tick_ovf()) {\n        tick0 = os_tick_val();\n        if (tick0 < tick) { tick = tick0; }\n        tick += (os_trv + 1U) * (os_time + 1U);\n    } else {\n        tick += (os_trv + 1U) * os_time;\n    }\n\n    return tick;\n}\n\n// Kernel Control Public API\n\n/// Initialize the RTOS Kernel for creating objects\nosStatus osKernelInitialize(void) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    if ((__get_CONTROL() & 1U) == 0U) {           // Privileged mode\n        return svcKernelInitialize();\n    } else {\n        return __svcKernelInitialize();\n    }\n}\n\n/// Start the RTOS Kernel\nosStatus osKernelStart(void) {\n    uint32_t stack[8];\n\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    switch (__get_CONTROL() & 0x03U) {\n        case 0x00U:                                 // Privileged Thread mode & MSP\n            __set_PSP((uint32_t) (stack + 8));         // Initial PSP\n            if (os_flags & 1U) {\n                __set_CONTROL(0x02U);                   // Set Privileged Thread mode & PSP\n            } else {\n                __set_CONTROL(0x03U);                   // Set Unprivileged Thread mode & PSP\n            }\n            __DSB();\n            __ISB();\n            break;\n        case 0x01U:                                 // Unprivileged Thread mode & MSP\n            return osErrorOS;\n        case 0x02U:                                 // Privileged Thread mode & PSP\n            if ((os_flags & 1U) == 0U) {              // Unprivileged Thread mode requested\n                __set_CONTROL(0x03U);                   // Set Unprivileged Thread mode & PSP\n                __DSB();\n                __ISB();\n            }\n            break;\n        case 0x03U:                                 // Unprivileged Thread mode & PSP\n            if (os_flags & 1U) { return osErrorOS; } // Privileged Thread mode requested\n            break;\n    }\n    return __svcKernelStart();\n}\n\n/// Check if the RTOS kernel is already started\nint32_t osKernelRunning(void) {\n    if ((__get_IPSR() != 0U) || ((__get_CONTROL() & 1U) == 0U)) {\n        // in ISR or Privileged\n        return (int32_t) os_running;\n    } else {\n        return __svcKernelRunning();\n    }\n}\n\n/// Get the RTOS kernel system timer counter\nuint32_t osKernelSysTick(void) {\n    if (__get_IPSR() != 0U) { return 0U; }        // Not allowed in ISR\n    return __svcKernelSysTick();\n}\n\n\n// ==== Thread Management ====\n\n/// Set Thread Error (for Create functions which return IDs)\nstatic void sysThreadError(osStatus status) {\n    // To Do\n}\n\n__NO_RETURN void osThreadExit(void);\n\n// Thread Service Calls declarations\nSVC_2_1(svcThreadCreate, osThreadId, const osThreadDef_t *, void *, RET_pointer)\n\nSVC_0_1(svcThreadGetId, osThreadId, RET_pointer)\n\nSVC_1_1(svcThreadTerminate, osStatus, osThreadId, RET_osStatus)\n\nSVC_0_1(svcThreadYield, osStatus, RET_osStatus)\n\nSVC_2_1(svcThreadSetPriority, osStatus, osThreadId, osPriority, RET_osStatus)\n\nSVC_1_1(svcThreadGetPriority, osPriority, osThreadId, RET_osPriority)\n\n// Thread Service Calls\n\n/// Create a thread and add it to Active Threads and set it to state READY\nosThreadId svcThreadCreate(const osThreadDef_t *thread_def, void *argument) {\n    P_TCB ptcb;\n    OS_TID tsk;\n    void *stk;\n\n    if ((thread_def == NULL) ||\n        (thread_def->pthread == NULL) ||\n        (thread_def->tpriority < osPriorityIdle) ||\n        (thread_def->tpriority > osPriorityRealtime)) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    if (thread_def->stacksize != 0U) {            // Custom stack size\n        stk = rt_alloc_mem(                         // Allocate stack\n                os_stack_mem,\n                thread_def->stacksize\n        );\n        if (stk == NULL) {\n            sysThreadError(osErrorNoMemory);          // Out of memory\n            return NULL;\n        }\n    } else {                                      // Default stack size\n        stk = NULL;\n    }\n\n    tsk = rt_tsk_create(                          // Create task\n            (FUNCP) thread_def->pthread,                 // Task function pointer\n            (uint32_t)\n                    (thread_def->tpriority - osPriorityIdle + 1) |  // Task priority\n            (thread_def->stacksize << 8),               // Task stack size in bytes\n            stk,                                        // Pointer to task's stack\n            argument                                    // Argument to the task\n    );\n\n    if (tsk == 0U) {                              // Invalid task ID\n        if (stk != NULL) {\n            rt_free_mem(os_stack_mem, stk);           // Free allocated stack\n        }\n        sysThreadError(osErrorNoMemory);            // Create task failed (Out of memory)\n        return NULL;\n    }\n\n    ptcb = (P_TCB) os_active_TCB[tsk - 1U];        // TCB pointer\n\n    *((uint32_t *) ptcb->tsk_stack + 13) = (uint32_t) osThreadExit;\n\n    return ptcb;\n}\n\n/// Return the thread ID of the current running thread\nosThreadId svcThreadGetId(void) {\n    OS_TID tsk;\n\n    tsk = rt_tsk_self();\n    if (tsk == 0U) { return NULL; }\n    return (P_TCB) os_active_TCB[tsk - 1U];\n}\n\n/// Terminate execution of a thread and remove it from ActiveThreads\nosStatus svcThreadTerminate(osThreadId thread_id) {\n    OS_RESULT res;\n    P_TCB ptcb;\n    void *stk;\n\n    ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer\n    if (ptcb == NULL) {\n        return osErrorParameter;\n    }\n\n    stk = ptcb->priv_stack ? ptcb->stack : NULL;  // Private stack\n\n    res = rt_tsk_delete(ptcb->task_id);           // Delete task\n\n    if (res == OS_R_NOK) {\n        return osErrorResource;                     // Delete task failed\n    }\n\n    if (stk != NULL) {\n        rt_free_mem(os_stack_mem, stk);             // Free private stack\n    }\n\n    return osOK;\n}\n\n/// Pass control to next thread that is in state READY\nosStatus svcThreadYield(void) {\n    rt_tsk_pass();                                // Pass control to next task\n    return osOK;\n}\n\n/// Change priority of an active thread\nosStatus svcThreadSetPriority(osThreadId thread_id, osPriority priority) {\n    OS_RESULT res;\n    P_TCB ptcb;\n\n    ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer\n    if (ptcb == NULL) {\n        return osErrorParameter;\n    }\n\n    if ((priority < osPriorityIdle) || (priority > osPriorityRealtime)) {\n        return osErrorValue;\n    }\n\n    res = rt_tsk_prio(                            // Change task priority\n            ptcb->task_id,                              // Task ID\n            (uint8_t) (priority - osPriorityIdle + 1)    // New task priority\n    );\n\n    if (res == OS_R_NOK) {\n        return osErrorResource;                     // Change task priority failed\n    }\n\n    return osOK;\n}\n\n/// Get current priority of an active thread\nosPriority svcThreadGetPriority(osThreadId thread_id) {\n    P_TCB ptcb;\n\n    ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer\n    if (ptcb == NULL) {\n        return osPriorityError;\n    }\n\n    return (osPriority) (ptcb->prio - 1 + osPriorityIdle);\n}\n\n\n// Thread Public API\n\n/// Create a thread and add it to Active Threads and set it to state READY\nosThreadId osThreadCreate(const osThreadDef_t *thread_def, void *argument) {\n    if (__get_IPSR() != 0U) {\n        return NULL;                                // Not allowed in ISR\n    }\n    if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {\n        // Privileged and not running\n        return svcThreadCreate(thread_def, argument);\n    } else {\n        return __svcThreadCreate(thread_def, argument);\n    }\n}\n\n/// Return the thread ID of the current running thread\nosThreadId osThreadGetId(void) {\n    if (__get_IPSR() != 0U) {\n        return NULL;                                // Not allowed in ISR\n    }\n    return __svcThreadGetId();\n}\n\n/// Terminate execution of a thread and remove it from ActiveThreads\nosStatus osThreadTerminate(osThreadId thread_id) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcThreadTerminate(thread_id);\n}\n\n/// Pass control to next thread that is in state READY\nosStatus osThreadYield(void) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcThreadYield();\n}\n\n/// Change priority of an active thread\nosStatus osThreadSetPriority(osThreadId thread_id, osPriority priority) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcThreadSetPriority(thread_id, priority);\n}\n\n/// Get current priority of an active thread\nosPriority osThreadGetPriority(osThreadId thread_id) {\n    if (__get_IPSR() != 0U) {\n        return osPriorityError;                     // Not allowed in ISR\n    }\n    return __svcThreadGetPriority(thread_id);\n}\n\n/// INTERNAL - Not Public\n/// Auto Terminate Thread on exit (used implicitly when thread exists)\n__NO_RETURN void osThreadExit(void) {\n    __svcThreadTerminate(__svcThreadGetId());\n    for (;;);                                     // Should never come here\n}\n\n\n// ==== Generic Wait Functions ====\n\n// Generic Wait Service Calls declarations\nSVC_1_1(svcDelay, osStatus, uint32_t, RET_osStatus)\n\n#if osFeature_Wait != 0\nSVC_1_3(svcWait,  os_InRegs osEvent,  uint32_t, RET_osEvent)\n#endif\n\n// Generic Wait Service Calls\n\n/// Wait for Timeout (Time Delay)\nosStatus svcDelay(uint32_t millisec) {\n    if (millisec == 0U) { return osOK; }\n    rt_dly_wait(rt_ms2tick(millisec));\n    return osEventTimeout;\n}\n\n/// Wait for Signal, Message, Mail, or Timeout\n#if osFeature_Wait != 0\nos_InRegs osEvent_type svcWait (uint32_t millisec) {\n  osEvent ret;\n\n  if (millisec == 0U) {\n    ret.status = osOK;\n    return osEvent_ret_status;\n  }\n\n  /* To Do: osEventSignal, osEventMessage, osEventMail */\n  rt_dly_wait(rt_ms2tick(millisec));\n  ret.status = osEventTimeout;\n\n  return osEvent_ret_status;\n}\n#endif\n\n\n// Generic Wait API\n\n/// Wait for Timeout (Time Delay)\nosStatus osDelay(uint32_t millisec) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcDelay(millisec);\n}\n\n/// Wait for Signal, Message, Mail, or Timeout\nos_InRegs osEvent osWait(uint32_t millisec) {\n    osEvent ret;\n\n#if osFeature_Wait == 0\n    ret.status = osErrorOS;\n    return ret;\n#else\n    if (__get_IPSR() != 0U) {                     // Not allowed in ISR\n      ret.status = osErrorISR;\n      return ret;\n    }\n    return __svcWait(millisec);\n#endif\n}\n\n\n// ==== Timer Management ====\n\n// Timer definitions\n#define osTimerInvalid  0U\n#define osTimerStopped  1U\n#define osTimerRunning  2U\n\n// Timer structures \n\ntypedef struct os_timer_cb_ {                   // Timer Control Block\n    struct os_timer_cb_ *next;                    // Pointer to next active Timer\n    uint8_t state;                    // Timer State\n    uint8_t type;                    // Timer Type (Periodic/One-shot)\n    uint16_t reserved;                    // Reserved\n    uint32_t tcnt;                    // Timer Delay Count\n    uint32_t icnt;                    // Timer Initial Count\n    void *arg;                    // Timer Function Argument\n    const osTimerDef_t *timer;                    // Pointer to Timer definition\n} os_timer_cb;\n\n// Timer variables\nos_timer_cb *os_timer_head;                     // Pointer to first active Timer\n\n\n// Timer Helper Functions\n\n// Insert Timer into the list sorted by time\nstatic void rt_timer_insert(os_timer_cb *pt, uint32_t tcnt) {\n    os_timer_cb *p, *prev;\n\n    prev = NULL;\n    p = os_timer_head;\n    while (p != NULL) {\n        if (tcnt < p->tcnt) { break; }\n        tcnt -= p->tcnt;\n        prev = p;\n        p = p->next;\n    }\n    pt->next = p;\n    pt->tcnt = tcnt;\n    if (p != NULL) {\n        p->tcnt -= pt->tcnt;\n    }\n    if (prev != NULL) {\n        prev->next = pt;\n    } else {\n        os_timer_head = pt;\n    }\n}\n\n// Remove Timer from the list\nstatic int32_t rt_timer_remove(os_timer_cb *pt) {\n    os_timer_cb *p, *prev;\n\n    prev = NULL;\n    p = os_timer_head;\n    while (p != NULL) {\n        if (p == pt) { break; }\n        prev = p;\n        p = p->next;\n    }\n    if (p == NULL) { return -1; }\n    if (prev != NULL) {\n        prev->next = pt->next;\n    } else {\n        os_timer_head = pt->next;\n    }\n    if (pt->next != NULL) {\n        pt->next->tcnt += pt->tcnt;\n    }\n\n    return 0;\n}\n\n\n// Timer Service Calls declarations\nSVC_3_1(svcTimerCreate, osTimerId, const osTimerDef_t *, os_timer_type, void *, RET_pointer)\n\nSVC_2_1(svcTimerStart, osStatus, osTimerId, uint32_t, RET_osStatus)\n\nSVC_1_1(svcTimerStop, osStatus, osTimerId, RET_osStatus)\n\nSVC_1_1(svcTimerDelete, osStatus, osTimerId, RET_osStatus)\n\nSVC_1_2 (svcTimerCall, os_InRegs osCallback, osTimerId, RET_osCallback)\n\n// Timer Management Service Calls\n\n/// Create timer\nosTimerId svcTimerCreate(const osTimerDef_t *timer_def, os_timer_type type, void *argument) {\n    os_timer_cb *pt;\n\n    if ((timer_def == NULL) || (timer_def->ptimer == NULL)) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    pt = timer_def->timer;\n    if (pt == NULL) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    if ((type != osTimerOnce) && (type != osTimerPeriodic)) {\n        sysThreadError(osErrorValue);\n        return NULL;\n    }\n\n    if (osThreadId_osTimerThread == NULL) {\n        sysThreadError(osErrorResource);\n        return NULL;\n    }\n\n    if (pt->state != osTimerInvalid) {\n        sysThreadError(osErrorResource);\n        return NULL;\n    }\n\n    pt->next = NULL;\n    pt->state = osTimerStopped;\n    pt->type = (uint8_t) type;\n    pt->arg = argument;\n    pt->timer = timer_def;\n\n    return (osTimerId) pt;\n}\n\n/// Start or restart timer\nosStatus svcTimerStart(osTimerId timer_id, uint32_t millisec) {\n    os_timer_cb *pt;\n    uint32_t tcnt;\n\n    pt = rt_id2obj(timer_id);\n    if (pt == NULL) {\n        return osErrorParameter;\n    }\n\n    if (millisec == 0U) { return osErrorValue; }\n\n    tcnt = (uint32_t) (((1000U * (uint64_t) millisec) + os_clockrate - 1U) / os_clockrate);\n\n    switch (pt->state) {\n        case osTimerRunning:\n            if (rt_timer_remove(pt) != 0) {\n                return osErrorResource;\n            }\n            break;\n        case osTimerStopped:\n            pt->state = osTimerRunning;\n            pt->icnt = tcnt;\n            break;\n        default:\n            return osErrorResource;\n    }\n\n    rt_timer_insert(pt, tcnt);\n\n    return osOK;\n}\n\n/// Stop timer\nosStatus svcTimerStop(osTimerId timer_id) {\n    os_timer_cb *pt;\n\n    pt = rt_id2obj(timer_id);\n    if (pt == NULL) {\n        return osErrorParameter;\n    }\n\n    if (pt->state != osTimerRunning) { return osErrorResource; }\n\n    pt->state = osTimerStopped;\n\n    if (rt_timer_remove(pt) != 0) {\n        return osErrorResource;\n    }\n\n    return osOK;\n}\n\n/// Delete timer\nosStatus svcTimerDelete(osTimerId timer_id) {\n    os_timer_cb *pt;\n\n    pt = rt_id2obj(timer_id);\n    if (pt == NULL) {\n        return osErrorParameter;\n    }\n\n    switch (pt->state) {\n        case osTimerRunning:\n            rt_timer_remove(pt);\n            break;\n        case osTimerStopped:\n            break;\n        default:\n            return osErrorResource;\n    }\n\n    pt->state = osTimerInvalid;\n\n    return osOK;\n}\n\n/// Get timer callback parameters\nos_InRegs osCallback_type svcTimerCall(osTimerId timer_id) {\n    os_timer_cb *pt;\n    osCallback ret;\n\n    pt = rt_id2obj(timer_id);\n    if (pt == NULL) {\n        ret.fp = NULL;\n        ret.arg = NULL;\n        return osCallback_ret;\n    }\n\n    ret.fp = (void *) pt->timer->ptimer;\n    ret.arg = pt->arg;\n\n    return osCallback_ret;\n}\n\nosStatus isrMessagePut(osMessageQId queue_id, uint32_t info, uint32_t millisec);\n\n/// Timer Tick (called each SysTick)\nvoid sysTimerTick(void) {\n    os_timer_cb *pt, *p;\n    osStatus status;\n\n    p = os_timer_head;\n    if (p == NULL) { return; }\n\n    p->tcnt--;\n    while ((p != NULL) && (p->tcnt == 0U)) {\n        pt = p;\n        p = p->next;\n        os_timer_head = p;\n        status = isrMessagePut(osMessageQId_osTimerMessageQ, (uint32_t) pt, 0U);\n        if (status != osOK) {\n            os_error(OS_ERR_TIMER_OVF);\n        }\n        if (pt->type == (uint8_t) osTimerPeriodic) {\n            rt_timer_insert(pt, pt->icnt);\n        } else {\n            pt->state = osTimerStopped;\n        }\n    }\n}\n\n/// Get user timers wake-up time \nuint32_t sysUserTimerWakeupTime(void) {\n\n    if (os_timer_head) {\n        return os_timer_head->tcnt;\n    }\n    return 0xFFFFFFFFU;\n}\n\n/// Update user timers on resume\nvoid sysUserTimerUpdate(uint32_t sleep_time) {\n\n    while ((os_timer_head != NULL) && (sleep_time != 0U)) {\n        if (sleep_time >= os_timer_head->tcnt) {\n            sleep_time -= os_timer_head->tcnt;\n            os_timer_head->tcnt = 1U;\n            sysTimerTick();\n        } else {\n            os_timer_head->tcnt -= sleep_time;\n            break;\n        }\n    }\n}\n\n\n// Timer Management Public API\n\n/// Create timer\nosTimerId osTimerCreate(const osTimerDef_t *timer_def, os_timer_type type, void *argument) {\n    if (__get_IPSR() != 0U) {\n        return NULL;                                // Not allowed in ISR\n    }\n    if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {\n        // Privileged and not running\n        return svcTimerCreate(timer_def, type, argument);\n    } else {\n        return __svcTimerCreate(timer_def, type, argument);\n    }\n}\n\n/// Start or restart timer\nosStatus osTimerStart(osTimerId timer_id, uint32_t millisec) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcTimerStart(timer_id, millisec);\n}\n\n/// Stop timer\nosStatus osTimerStop(osTimerId timer_id) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcTimerStop(timer_id);\n}\n\n/// Delete timer\nosStatus osTimerDelete(osTimerId timer_id) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcTimerDelete(timer_id);\n}\n\n/// INTERNAL - Not Public\n/// Get timer callback parameters (used by OS Timer Thread)\nos_InRegs osCallback osTimerCall(osTimerId timer_id) {\n    return __svcTimerCall(timer_id);\n}\n\n\n// Timer Thread\n__NO_RETURN void osTimerThread(void const *argument) {\n    osCallback cb;\n    osEvent evt;\n\n    for (;;) {\n        evt = osMessageGet(osMessageQId_osTimerMessageQ, osWaitForever);\n        if (evt.status == osEventMessage) {\n            cb = osTimerCall(evt.value.p);\n            if (cb.fp != NULL) {\n                (*(os_ptimer) cb.fp)(cb.arg);\n            }\n        }\n    }\n}\n\n\n// ==== Signal Management ====\n\n// Signal Service Calls declarations\nSVC_2_1(svcSignalSet, int32_t, osThreadId, int32_t, RET_int32_t)\n\nSVC_2_1(svcSignalClear, int32_t, osThreadId, int32_t, RET_int32_t)\n\nSVC_2_3 (svcSignalWait, os_InRegs osEvent, int32_t, uint32_t, RET_osEvent)\n\n// Signal Service Calls\n\n/// Set the specified Signal Flags of an active thread\nint32_t svcSignalSet(osThreadId thread_id, int32_t signals) {\n    P_TCB ptcb;\n    int32_t sig;\n\n    ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer\n    if (ptcb == NULL) {\n        return (int32_t) 0x80000000U;\n    }\n\n    if ((uint32_t) signals & (0xFFFFFFFFU << osFeature_Signals)) {\n        return (int32_t) 0x80000000U;\n    }\n\n    sig = (int32_t) ptcb->events;                  // Previous signal flags\n\n    rt_evt_set((uint16_t) signals, ptcb->task_id); // Set event flags\n\n    return sig;\n}\n\n/// Clear the specified Signal Flags of an active thread\nint32_t svcSignalClear(osThreadId thread_id, int32_t signals) {\n    P_TCB ptcb;\n    int32_t sig;\n\n    ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer\n    if (ptcb == NULL) {\n        return (int32_t) 0x80000000U;\n    }\n\n    if ((uint32_t) signals & (0xFFFFFFFFU << osFeature_Signals)) {\n        return (int32_t) 0x80000000U;\n    }\n\n    sig = (int32_t) ptcb->events;                  // Previous signal flags\n\n    rt_evt_clr((uint16_t) signals, ptcb->task_id); // Clear event flags\n\n    return sig;\n}\n\n/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread\nos_InRegs osEvent_type svcSignalWait(int32_t signals, uint32_t millisec) {\n    OS_RESULT res;\n    osEvent ret;\n\n    if ((uint32_t) signals & (0xFFFFFFFFU << osFeature_Signals)) {\n        ret.status = osErrorValue;\n        return osEvent_ret_status;\n    }\n\n    if (signals != 0) {                           // Wait for all specified signals\n        res = rt_evt_wait((uint16_t) signals, rt_ms2tick(millisec), __TRUE);\n    } else {                                      // Wait for any signal\n        res = rt_evt_wait(0xFFFFU, rt_ms2tick(millisec), __FALSE);\n    }\n\n    if (res == OS_R_EVT) {\n        ret.status = osEventSignal;\n        ret.value.signals = (signals != 0) ? signals : (int32_t) os_tsk.run->waits;\n    } else {\n        ret.status = (millisec != 0U) ? osEventTimeout : osOK;\n        ret.value.signals = 0;\n    }\n\n    return osEvent_ret_value;\n}\n\n\n// Signal ISR Calls\n\n/// Set the specified Signal Flags of an active thread\nint32_t isrSignalSet(osThreadId thread_id, int32_t signals) {\n    P_TCB ptcb;\n    int32_t sig;\n\n    ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer\n    if (ptcb == NULL) {\n        return (int32_t) 0x80000000U;\n    }\n\n    if ((uint32_t) signals & (0xFFFFFFFFU << osFeature_Signals)) {\n        return (int32_t) 0x80000000U;\n    }\n\n    sig = (int32_t) ptcb->events;                  // Previous signal flags\n\n    isr_evt_set((uint16_t) signals, ptcb->task_id);// Set event flags\n\n    return sig;\n}\n\n\n// Signal Public API\n\n/// Set the specified Signal Flags of an active thread\nint32_t osSignalSet(osThreadId thread_id, int32_t signals) {\n    if (__get_IPSR() != 0U) {                     // in ISR\n        return isrSignalSet(thread_id, signals);\n    } else {                                      // in Thread\n        return __svcSignalSet(thread_id, signals);\n    }\n}\n\n/// Clear the specified Signal Flags of an active thread\nint32_t osSignalClear(osThreadId thread_id, int32_t signals) {\n    if (__get_IPSR() != 0U) {\n        return (int32_t) 0x80000000U;                // Not allowed in ISR\n    }\n    return __svcSignalClear(thread_id, signals);\n}\n\n/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread\nos_InRegs osEvent osSignalWait(int32_t signals, uint32_t millisec) {\n    osEvent ret;\n\n    if (__get_IPSR() != 0U) {                     // Not allowed in ISR\n        ret.status = osErrorISR;\n        return ret;\n    }\n    return __svcSignalWait(signals, millisec);\n}\n\n\n// ==== Mutex Management ====\n\n// Mutex Service Calls declarations\nSVC_1_1(svcMutexCreate, osMutexId, const osMutexDef_t *, RET_pointer)\n\nSVC_2_1(svcMutexWait, osStatus, osMutexId, uint32_t, RET_osStatus)\n\nSVC_1_1(svcMutexRelease, osStatus, osMutexId, RET_osStatus)\n\nSVC_1_1(svcMutexDelete, osStatus, osMutexId, RET_osStatus)\n\n// Mutex Service Calls\n\n/// Create and Initialize a Mutex object\nosMutexId svcMutexCreate(const osMutexDef_t *mutex_def) {\n    OS_ID mut;\n\n    if (mutex_def == NULL) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    mut = mutex_def->mutex;\n    if (mut == NULL) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    if (((P_MUCB) mut)->cb_type != 0U) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    rt_mut_init(mut);                             // Initialize Mutex\n\n    return mut;\n}\n\n/// Wait until a Mutex becomes available\nosStatus svcMutexWait(osMutexId mutex_id, uint32_t millisec) {\n    OS_ID mut;\n    OS_RESULT res;\n\n    mut = rt_id2obj(mutex_id);\n    if (mut == NULL) {\n        return osErrorParameter;\n    }\n\n    if (((P_MUCB) mut)->cb_type != MUCB) {\n        return osErrorParameter;\n    }\n\n    res = rt_mut_wait(mut, rt_ms2tick(millisec)); // Wait for Mutex\n\n    if (res == OS_R_TMO) {\n        return ((millisec != 0U) ? osErrorTimeoutResource : osErrorResource);\n    }\n    if (res == OS_R_NOK) {\n        return osErrorResource;\n    }\n\n    return osOK;\n}\n\n/// Release a Mutex that was obtained with osMutexWait\nosStatus svcMutexRelease(osMutexId mutex_id) {\n    OS_ID mut;\n    OS_RESULT res;\n\n    mut = rt_id2obj(mutex_id);\n    if (mut == NULL) {\n        return osErrorParameter;\n    }\n\n    if (((P_MUCB) mut)->cb_type != MUCB) {\n        return osErrorParameter;\n    }\n\n    res = rt_mut_release(mut);                    // Release Mutex\n\n    if (res == OS_R_NOK) {\n        return osErrorResource;                     // Thread not owner or Zero Counter\n    }\n\n    return osOK;\n}\n\n/// Delete a Mutex that was created by osMutexCreate\nosStatus svcMutexDelete(osMutexId mutex_id) {\n    OS_ID mut;\n\n    mut = rt_id2obj(mutex_id);\n    if (mut == NULL) {\n        return osErrorParameter;\n    }\n\n    if (((P_MUCB) mut)->cb_type != MUCB) {\n        return osErrorParameter;\n    }\n\n    rt_mut_delete(mut);                           // Release Mutex\n\n    return osOK;\n}\n\n\n// Mutex Public API\n\n/// Create and Initialize a Mutex object\nosMutexId osMutexCreate(const osMutexDef_t *mutex_def) {\n    if (__get_IPSR() != 0U) {\n        return NULL;                                // Not allowed in ISR\n    }\n    if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {\n        // Privileged and not running\n        return svcMutexCreate(mutex_def);\n    } else {\n        return __svcMutexCreate(mutex_def);\n    }\n}\n\n/// Wait until a Mutex becomes available\nosStatus osMutexWait(osMutexId mutex_id, uint32_t millisec) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcMutexWait(mutex_id, millisec);\n}\n\n/// Release a Mutex that was obtained with osMutexWait\nosStatus osMutexRelease(osMutexId mutex_id) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcMutexRelease(mutex_id);\n}\n\n/// Delete a Mutex that was created by osMutexCreate\nosStatus osMutexDelete(osMutexId mutex_id) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcMutexDelete(mutex_id);\n}\n\n\n// ==== Semaphore Management ====\n\n// Semaphore Service Calls declarations\nSVC_2_1(svcSemaphoreCreate, osSemaphoreId, const osSemaphoreDef_t *, int32_t, RET_pointer)\n\nSVC_2_1(svcSemaphoreWait, int32_t, osSemaphoreId, uint32_t, RET_int32_t)\n\nSVC_1_1(svcSemaphoreRelease, osStatus, osSemaphoreId, RET_osStatus)\n\nSVC_1_1(svcSemaphoreDelete, osStatus, osSemaphoreId, RET_osStatus)\n\n// Semaphore Service Calls\n\n/// Create and Initialize a Semaphore object\nosSemaphoreId svcSemaphoreCreate(const osSemaphoreDef_t *semaphore_def, int32_t count) {\n    OS_ID sem;\n\n    if (semaphore_def == NULL) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    sem = semaphore_def->semaphore;\n    if (sem == NULL) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    if (((P_SCB) sem)->cb_type != 0U) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    if (count > osFeature_Semaphore) {\n        sysThreadError(osErrorValue);\n        return NULL;\n    }\n\n    rt_sem_init(sem, (uint16_t) count);            // Initialize Semaphore\n\n    return sem;\n}\n\n/// Wait until a Semaphore becomes available\nint32_t svcSemaphoreWait(osSemaphoreId semaphore_id, uint32_t millisec) {\n    OS_ID sem;\n    OS_RESULT res;\n\n    sem = rt_id2obj(semaphore_id);\n    if (sem == NULL) {\n        return -1;\n    }\n\n    if (((P_SCB) sem)->cb_type != SCB) {\n        return -1;\n    }\n\n    res = rt_sem_wait(sem, rt_ms2tick(millisec)); // Wait for Semaphore\n\n    if (res == OS_R_TMO) { return 0; }            // Timeout\n\n    return (int32_t) (((P_SCB) sem)->tokens + 1U);\n}\n\n/// Release a Semaphore\nosStatus svcSemaphoreRelease(osSemaphoreId semaphore_id) {\n    OS_ID sem;\n\n    sem = rt_id2obj(semaphore_id);\n    if (sem == NULL) {\n        return osErrorParameter;\n    }\n\n    if (((P_SCB) sem)->cb_type != SCB) {\n        return osErrorParameter;\n    }\n\n    if ((int32_t) ((P_SCB) sem)->tokens == osFeature_Semaphore) {\n        return osErrorResource;\n    }\n\n    rt_sem_send(sem);                             // Release Semaphore\n\n    return osOK;\n}\n\n/// Delete a Semaphore that was created by osSemaphoreCreate\nosStatus svcSemaphoreDelete(osSemaphoreId semaphore_id) {\n    OS_ID sem;\n\n    sem = rt_id2obj(semaphore_id);\n    if (sem == NULL) {\n        return osErrorParameter;\n    }\n\n    if (((P_SCB) sem)->cb_type != SCB) {\n        return osErrorParameter;\n    }\n\n    rt_sem_delete(sem);                           // Delete Semaphore\n\n    return osOK;\n}\n\n\n// Semaphore ISR Calls\n\n/// Release a Semaphore\nosStatus isrSemaphoreRelease(osSemaphoreId semaphore_id) {\n    OS_ID sem;\n\n    sem = rt_id2obj(semaphore_id);\n    if (sem == NULL) {\n        return osErrorParameter;\n    }\n\n    if (((P_SCB) sem)->cb_type != SCB) {\n        return osErrorParameter;\n    }\n\n    if ((int32_t) ((P_SCB) sem)->tokens == osFeature_Semaphore) {\n        return osErrorResource;\n    }\n\n    isr_sem_send(sem);                            // Release Semaphore\n\n    return osOK;\n}\n\n\n// Semaphore Public API\n\n/// Create and Initialize a Semaphore object\nosSemaphoreId osSemaphoreCreate(const osSemaphoreDef_t *semaphore_def, int32_t count) {\n    if (__get_IPSR() != 0U) {\n        return NULL;                                // Not allowed in ISR\n    }\n    if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {\n        // Privileged and not running\n        return svcSemaphoreCreate(semaphore_def, count);\n    } else {\n        return __svcSemaphoreCreate(semaphore_def, count);\n    }\n}\n\n/// Wait until a Semaphore becomes available\nint32_t osSemaphoreWait(osSemaphoreId semaphore_id, uint32_t millisec) {\n    if (__get_IPSR() != 0U) {\n        return -1;                                  // Not allowed in ISR\n    }\n    return __svcSemaphoreWait(semaphore_id, millisec);\n}\n\n/// Release a Semaphore\nosStatus osSemaphoreRelease(osSemaphoreId semaphore_id) {\n    if (__get_IPSR() != 0U) {                     // in ISR\n        return isrSemaphoreRelease(semaphore_id);\n    } else {                                      // in Thread\n        return __svcSemaphoreRelease(semaphore_id);\n    }\n}\n\n/// Delete a Semaphore that was created by osSemaphoreCreate\nosStatus osSemaphoreDelete(osSemaphoreId semaphore_id) {\n    if (__get_IPSR() != 0U) {\n        return osErrorISR;                          // Not allowed in ISR\n    }\n    return __svcSemaphoreDelete(semaphore_id);\n}\n\n\n// ==== Memory Management Functions ====\n\n// Memory Management Helper Functions\n\n// Clear Memory Box (Zero init)\nstatic void rt_clr_box(void *box_mem, void *box) {\n    uint32_t *p, n;\n\n    if ((box_mem != NULL) && (box != NULL)) {\n        p = box;\n        for (n = ((P_BM) box_mem)->blk_size; n; n -= 4U) {\n            *p++ = 0U;\n        }\n    }\n}\n\n// Memory Management Service Calls declarations\nSVC_1_1(svcPoolCreate, osPoolId, const osPoolDef_t *, RET_pointer)\n\nSVC_1_1(sysPoolAlloc, void *, osPoolId, RET_pointer)\n\nSVC_2_1(sysPoolFree, osStatus, osPoolId, void *, RET_osStatus)\n\n// Memory Management Service & ISR Calls\n\n/// Create and Initialize memory pool\nosPoolId svcPoolCreate(const osPoolDef_t *pool_def) {\n    uint32_t blk_sz;\n\n    if ((pool_def == NULL) ||\n        (pool_def->pool_sz == 0U) ||\n        (pool_def->item_sz == 0U) ||\n        (pool_def->pool == NULL)) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    blk_sz = (pool_def->item_sz + 3U) & (uint32_t) ~3U;\n\n    _init_box(pool_def->pool, sizeof(struct OS_BM) + (pool_def->pool_sz * blk_sz), blk_sz);\n\n    return pool_def->pool;\n}\n\n/// Allocate a memory block from a memory pool\nvoid *sysPoolAlloc(osPoolId pool_id) {\n    void *mem;\n\n    if (pool_id == NULL) {\n        return NULL;\n    }\n\n    mem = rt_alloc_box(pool_id);\n\n    return mem;\n}\n\n/// Return an allocated memory block back to a specific memory pool\nosStatus sysPoolFree(osPoolId pool_id, void *block) {\n    uint32_t res;\n\n    if (pool_id == NULL) {\n        return osErrorParameter;\n    }\n\n    res = rt_free_box(pool_id, block);\n    if (res != 0) {\n        return osErrorValue;\n    }\n\n    return osOK;\n}\n\n\n// Memory Management Public API\n\n/// Create and Initialize memory pool\nosPoolId osPoolCreate(const osPoolDef_t *pool_def) {\n    if (__get_IPSR() != 0U) {\n        return NULL;                                // Not allowed in ISR\n    }\n    if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {\n        // Privileged and not running\n        return svcPoolCreate(pool_def);\n    } else {\n        return __svcPoolCreate(pool_def);\n    }\n}\n\n/// Allocate a memory block from a memory pool\nvoid *osPoolAlloc(osPoolId pool_id) {\n    if ((__get_IPSR() != 0U) || ((__get_CONTROL() & 1U) == 0U)) {     // in ISR or Privileged\n        return sysPoolAlloc(pool_id);\n    } else {                                      // in Thread\n        return __sysPoolAlloc(pool_id);\n    }\n}\n\n/// Allocate a memory block from a memory pool and set memory block to zero\nvoid *osPoolCAlloc(osPoolId pool_id) {\n    void *mem;\n\n    if ((__get_IPSR() != 0U) || ((__get_CONTROL() & 1U) == 0U)) {     // in ISR or Privileged\n        mem = sysPoolAlloc(pool_id);\n    } else {                                      // in Thread\n        mem = __sysPoolAlloc(pool_id);\n    }\n\n    rt_clr_box(pool_id, mem);\n\n    return mem;\n}\n\n/// Return an allocated memory block back to a specific memory pool\nosStatus osPoolFree(osPoolId pool_id, void *block) {\n    if ((__get_IPSR() != 0U) || ((__get_CONTROL() & 1U) == 0U)) {     // in ISR or Privileged\n        return sysPoolFree(pool_id, block);\n    } else {                                      // in Thread\n        return __sysPoolFree(pool_id, block);\n    }\n}\n\n\n// ==== Message Queue Management Functions ====\n\n// Message Queue Management Service Calls declarations\nSVC_2_1(svcMessageCreate, osMessageQId, const osMessageQDef_t *, osThreadId, RET_pointer)\n\nSVC_3_1(svcMessagePut, osStatus, osMessageQId, uint32_t, uint32_t, RET_osStatus)\n\nSVC_2_3 (svcMessageGet, os_InRegs osEvent, osMessageQId, uint32_t, RET_osEvent)\n\n// Message Queue Service Calls\n\n/// Create and Initialize Message Queue\nosMessageQId svcMessageCreate(const osMessageQDef_t *queue_def, osThreadId thread_id) {\n\n    if ((queue_def == NULL) ||\n        (queue_def->queue_sz == 0U) ||\n        (queue_def->pool == NULL)) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    if (((P_MCB) queue_def->pool)->cb_type != 0U) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    rt_mbx_init(queue_def->pool, (uint16_t) (4U * (queue_def->queue_sz + 4U)));\n\n    return queue_def->pool;\n}\n\n/// Put a Message to a Queue\nosStatus svcMessagePut(osMessageQId queue_id, uint32_t info, uint32_t millisec) {\n    OS_RESULT res;\n\n    if (queue_id == NULL) {\n        return osErrorParameter;\n    }\n\n    if (((P_MCB) queue_id)->cb_type != MCB) {\n        return osErrorParameter;\n    }\n\n    res = rt_mbx_send(queue_id, (void *) info, rt_ms2tick(millisec));\n\n    if (res == OS_R_TMO) {\n        return ((millisec != 0U) ? osErrorTimeoutResource : osErrorResource);\n    }\n\n    return osOK;\n}\n\n/// Get a Message or Wait for a Message from a Queue\nos_InRegs osEvent_type svcMessageGet(osMessageQId queue_id, uint32_t millisec) {\n    OS_RESULT res;\n    osEvent ret;\n\n    if (queue_id == NULL) {\n        ret.status = osErrorParameter;\n        return osEvent_ret_status;\n    }\n\n    if (((P_MCB) queue_id)->cb_type != MCB) {\n        ret.status = osErrorParameter;\n        return osEvent_ret_status;\n    }\n\n    res = rt_mbx_wait(queue_id, &ret.value.p, rt_ms2tick(millisec));\n\n    if (res == OS_R_TMO) {\n        ret.status = (millisec != 0U) ? osEventTimeout : osOK;\n        return osEvent_ret_value;\n    }\n\n    ret.status = osEventMessage;\n\n    return osEvent_ret_value;\n}\n\n\n// Message Queue ISR Calls\n\n/// Put a Message to a Queue\nosStatus isrMessagePut(osMessageQId queue_id, uint32_t info, uint32_t millisec) {\n\n    if ((queue_id == NULL) || (millisec != 0U)) {\n        return osErrorParameter;\n    }\n\n    if (((P_MCB) queue_id)->cb_type != MCB) {\n        return osErrorParameter;\n    }\n\n    if (rt_mbx_check(queue_id) == 0U) {           // Check if Queue is full\n        return osErrorResource;\n    }\n\n    isr_mbx_send(queue_id, (void *) info);\n\n    return osOK;\n}\n\n/// Get a Message or Wait for a Message from a Queue\nos_InRegs osEvent isrMessageGet(osMessageQId queue_id, uint32_t millisec) {\n    OS_RESULT res;\n    osEvent ret;\n\n    if ((queue_id == NULL) || (millisec != 0U)) {\n        ret.status = osErrorParameter;\n        return ret;\n    }\n\n    if (((P_MCB) queue_id)->cb_type != MCB) {\n        ret.status = osErrorParameter;\n        return ret;\n    }\n\n    res = isr_mbx_receive(queue_id, &ret.value.p);\n\n    if (res != OS_R_MBX) {\n        ret.status = osOK;\n        return ret;\n    }\n\n    ret.status = osEventMessage;\n\n    return ret;\n}\n\n\n// Message Queue Management Public API\n\n/// Create and Initialize Message Queue\nosMessageQId osMessageCreate(const osMessageQDef_t *queue_def, osThreadId thread_id) {\n    if (__get_IPSR() != 0U) {\n        return NULL;                                // Not allowed in ISR\n    }\n    if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {\n        // Privileged and not running\n        return svcMessageCreate(queue_def, thread_id);\n    } else {\n        return __svcMessageCreate(queue_def, thread_id);\n    }\n}\n\n/// Put a Message to a Queue\nosStatus osMessagePut(osMessageQId queue_id, uint32_t info, uint32_t millisec) {\n    if (__get_IPSR() != 0U) {                     // in ISR\n        return isrMessagePut(queue_id, info, millisec);\n    } else {                                      // in Thread\n        return __svcMessagePut(queue_id, info, millisec);\n    }\n}\n\n/// Get a Message or Wait for a Message from a Queue\nos_InRegs osEvent osMessageGet(osMessageQId queue_id, uint32_t millisec) {\n    if (__get_IPSR() != 0U) {                     // in ISR\n        return isrMessageGet(queue_id, millisec);\n    } else {                                      // in Thread\n        return __svcMessageGet(queue_id, millisec);\n    }\n}\n\n\n// ==== Mail Queue Management Functions ====\n\n// Mail Queue Management Service Calls declarations\nSVC_2_1(svcMailCreate, osMailQId, const osMailQDef_t *, osThreadId, RET_pointer)\n\nSVC_3_1(sysMailAlloc, void *, osMailQId, uint32_t, uint32_t, RET_pointer)\n\nSVC_3_1(sysMailFree, osStatus, osMailQId, void *, uint32_t, RET_osStatus)\n\n// Mail Queue Management Service & ISR Calls\n\n/// Create and Initialize mail queue\nosMailQId svcMailCreate(const osMailQDef_t *queue_def, osThreadId thread_id) {\n    uint32_t blk_sz;\n    P_MCB pmcb;\n    void *pool;\n\n    if ((queue_def == NULL) ||\n        (queue_def->queue_sz == 0U) ||\n        (queue_def->item_sz == 0U) ||\n        (queue_def->pool == NULL)) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    pmcb = *(((void **) queue_def->pool) + 0);\n    pool = *(((void **) queue_def->pool) + 1);\n\n    if ((pool == NULL) || (pmcb == NULL) || (pmcb->cb_type != 0U)) {\n        sysThreadError(osErrorParameter);\n        return NULL;\n    }\n\n    blk_sz = (queue_def->item_sz + 3U) & (uint32_t) ~3U;\n\n    _init_box(pool, sizeof(struct OS_BM) + (queue_def->queue_sz * blk_sz), blk_sz);\n\n    rt_mbx_init(pmcb, (uint16_t) (4U * (queue_def->queue_sz + 4U)));\n\n    return queue_def->pool;\n}\n\n/// Allocate a memory block from a mail\nvoid *sysMailAlloc(osMailQId queue_id, uint32_t millisec, uint32_t isr) {\n    P_MCB pmcb;\n    void *pool;\n    void *mem;\n\n    if (queue_id == NULL) {\n        return NULL;\n    }\n\n    pmcb = *(((void **) queue_id) + 0);\n    pool = *(((void **) queue_id) + 1);\n\n    if ((pool == NULL) || (pmcb == NULL)) {\n        return NULL;\n    }\n\n    if ((isr != 0U) && (millisec != 0U)) {\n        return NULL;\n    }\n\n    mem = rt_alloc_box(pool);\n\n    if ((mem == NULL) && (millisec != 0U)) {\n        // Put Task to sleep when Memory not available\n        if (pmcb->p_lnk != NULL) {\n            rt_put_prio((P_XCB) pmcb, os_tsk.run);\n        } else {\n            pmcb->p_lnk = os_tsk.run;\n            os_tsk.run->p_lnk = NULL;\n            os_tsk.run->p_rlnk = (P_TCB) pmcb;\n            // Task is waiting to allocate a message\n            pmcb->state = 3U;\n        }\n        rt_block(rt_ms2tick(millisec), WAIT_MBX);\n    }\n\n    return mem;\n}\n\n/// Free a memory block from a mail\nosStatus sysMailFree(osMailQId queue_id, void *mail, uint32_t isr) {\n    P_MCB pmcb;\n    P_TCB ptcb;\n    void *pool;\n    void *mem;\n    uint32_t res;\n\n    if (queue_id == NULL) {\n        return osErrorParameter;\n    }\n\n    pmcb = *(((void **) queue_id) + 0);\n    pool = *(((void **) queue_id) + 1);\n\n    if ((pmcb == NULL) || (pool == NULL)) {\n        return osErrorParameter;\n    }\n\n    res = rt_free_box(pool, mail);\n\n    if (res != 0U) {\n        return osErrorValue;\n    }\n\n    if ((pmcb->p_lnk != NULL) && (pmcb->state == 3U)) {\n        // Task is waiting to allocate a message\n        if (isr != 0U) {\n            rt_psq_enq(pmcb, (U32) pool);\n            rt_psh_req();\n        } else {\n            mem = rt_alloc_box(pool);\n            if (mem != NULL) {\n                ptcb = rt_get_first((P_XCB) pmcb);\n                rt_ret_val(ptcb, (U32) mem);\n                rt_rmv_dly(ptcb);\n                rt_dispatch(ptcb);\n            }\n        }\n    }\n\n    return osOK;\n}\n\n\n// Mail Queue Management Public API\n\n/// Create and Initialize mail queue\nosMailQId osMailCreate(const osMailQDef_t *queue_def, osThreadId thread_id) {\n    if (__get_IPSR() != 0U) {\n        return NULL;                                // Not allowed in ISR\n    }\n    if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {\n        // Privileged and not running\n        return svcMailCreate(queue_def, thread_id);\n    } else {\n        return __svcMailCreate(queue_def, thread_id);\n    }\n}\n\n/// Allocate a memory block from a mail\nvoid *osMailAlloc(osMailQId queue_id, uint32_t millisec) {\n    if (__get_IPSR() != 0U) {                     // in ISR\n        return sysMailAlloc(queue_id, millisec, 1U);\n    } else {                                      // in Thread\n        return __sysMailAlloc(queue_id, millisec, 0U);\n    }\n}\n\n/// Allocate a memory block from a mail and set memory block to zero\nvoid *osMailCAlloc(osMailQId queue_id, uint32_t millisec) {\n    void *pool;\n    void *mem;\n\n    if (__get_IPSR() != 0U) {                     // in ISR\n        mem = sysMailAlloc(queue_id, millisec, 1U);\n    } else {                                      // in Thread\n        mem = __sysMailAlloc(queue_id, millisec, 0U);\n    }\n\n    pool = *(((void **) queue_id) + 1);\n\n    rt_clr_box(pool, mem);\n\n    return mem;\n}\n\n/// Free a memory block from a mail\nosStatus osMailFree(osMailQId queue_id, void *mail) {\n    if (__get_IPSR() != 0U) {                     // in ISR\n        return sysMailFree(queue_id, mail, 1U);\n    } else {                                      // in Thread\n        return __sysMailFree(queue_id, mail, 0U);\n    }\n}\n\n/// Put a mail to a queue\nosStatus osMailPut(osMailQId queue_id, void *mail) {\n    if (queue_id == NULL) {\n        return osErrorParameter;\n    }\n    if (mail == NULL) {\n        return osErrorValue;\n    }\n    return osMessagePut(*((void **) queue_id), (uint32_t) mail, 0U);\n}\n\n/// Get a mail from a queue\nos_InRegs osEvent osMailGet(osMailQId queue_id, uint32_t millisec) {\n    osEvent ret;\n\n    if (queue_id == NULL) {\n        ret.status = osErrorParameter;\n        return ret;\n    }\n\n    ret = osMessageGet(*((void **) queue_id), millisec);\n    if (ret.status == osEventMessage) ret.status = osEventMail;\n\n    return ret;\n}\n\n\n//  ==== RTX Extensions ====\n\n// Service Calls declarations\nSVC_0_1(rt_suspend, uint32_t, RET_uint32_t)\n\nSVC_1_0(rt_resume, void, uint32_t)\n\n\n// Public API\n\n/// Suspends the OS task scheduler\nuint32_t os_suspend(void) {\n    return __rt_suspend();\n}\n\n/// Resumes the OS task scheduler\nvoid os_resume(uint32_t sleep_time) {\n    __rt_resume(sleep_time);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Event.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_EVENT.C\n *      Purpose: Implements waits and wake-ups for event flags\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_Event.h\"\n#include \"rt_List.h\"\n#include \"rt_Task.h\"\n#include \"rt_HAL_CM.h\"\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_evt_wait -----------------------------------*/\n\nOS_RESULT rt_evt_wait(U16 wait_flags, U16 timeout, BOOL and_wait) {\n    /* Wait for one or more event flags with optional time-out.                */\n    /* \"wait_flags\" identifies the flags to wait for.                          */\n    /* \"timeout\" is the time-out limit in system ticks (0xffff if no time-out) */\n    /* \"and_wait\" specifies the AND-ing of \"wait_flags\" as condition to be met */\n    /* to complete the wait. (OR-ing if set to 0).                             */\n    U32 block_state;\n\n    if (and_wait) {\n        /* Check for AND-connected events */\n        if ((os_tsk.run->events & wait_flags) == wait_flags) {\n            os_tsk.run->events &= ~wait_flags;\n            return (OS_R_EVT);\n        }\n        block_state = WAIT_AND;\n    } else {\n        /* Check for OR-connected events */\n        if (os_tsk.run->events & wait_flags) {\n            os_tsk.run->waits = os_tsk.run->events & wait_flags;\n            os_tsk.run->events &= ~wait_flags;\n            return (OS_R_EVT);\n        }\n        block_state = WAIT_OR;\n    }\n    /* Task has to wait */\n    os_tsk.run->waits = wait_flags;\n    rt_block(timeout, (U8) block_state);\n    return (OS_R_TMO);\n}\n\n\n/*--------------------------- rt_evt_set ------------------------------------*/\n\nvoid rt_evt_set(U16 event_flags, OS_TID task_id) {\n    /* Set one or more event flags of a selectable task. */\n    P_TCB p_tcb;\n\n    p_tcb = os_active_TCB[task_id - 1U];\n    if (p_tcb == NULL) {\n        return;\n    }\n    p_tcb->events |= event_flags;\n    event_flags = p_tcb->waits;\n    /* If the task is not waiting for an event, it should not be put */\n    /* to ready state. */\n    if (p_tcb->state == WAIT_AND) {\n        /* Check for AND-connected events */\n        if ((p_tcb->events & event_flags) == event_flags) {\n            goto wkup;\n        }\n    }\n    if (p_tcb->state == WAIT_OR) {\n        /* Check for OR-connected events */\n        if (p_tcb->events & event_flags) {\n            p_tcb->waits &= p_tcb->events;\n            wkup:\n            p_tcb->events &= ~event_flags;\n            rt_rmv_dly(p_tcb);\n            p_tcb->state = READY;\n#ifdef __CMSIS_RTOS\n            rt_ret_val2(p_tcb, 0x08U/*osEventSignal*/, p_tcb->waits);\n#else\n            rt_ret_val(p_tcb, OS_R_EVT);\n#endif\n            rt_dispatch(p_tcb);\n        }\n    }\n}\n\n\n/*--------------------------- rt_evt_clr ------------------------------------*/\n\nvoid rt_evt_clr(U16 clear_flags, OS_TID task_id) {\n    /* Clear one or more event flags (identified by \"clear_flags\") of a */\n    /* selectable task (identified by \"task\"). */\n    P_TCB task = os_active_TCB[task_id - 1U];\n\n    if (task == NULL) {\n        return;\n    }\n    task->events &= ~clear_flags;\n}\n\n\n/*--------------------------- isr_evt_set -----------------------------------*/\n\nvoid isr_evt_set(U16 event_flags, OS_TID task_id) {\n    /* Same function as \"os_evt_set\", but to be called by ISRs. */\n    P_TCB p_tcb = os_active_TCB[task_id - 1U];\n\n    if (p_tcb == NULL) {\n        return;\n    }\n    rt_psq_enq(p_tcb, event_flags);\n    rt_psh_req();\n}\n\n\n/*--------------------------- rt_evt_get ------------------------------------*/\n\nU16 rt_evt_get(void) {\n    /* Get events of a running task after waiting for OR connected events. */\n    return (os_tsk.run->waits);\n}\n\n\n/*--------------------------- rt_evt_psh ------------------------------------*/\n\nvoid rt_evt_psh(P_TCB p_CB, U16 set_flags) {\n    /* Check if task has to be waken up */\n    U16 event_flags;\n\n    p_CB->events |= set_flags;\n    event_flags = p_CB->waits;\n    if (p_CB->state == WAIT_AND) {\n        /* Check for AND-connected events */\n        if ((p_CB->events & event_flags) == event_flags) {\n            goto rdy;\n        }\n    }\n    if (p_CB->state == WAIT_OR) {\n        /* Check for OR-connected events */\n        if (p_CB->events & event_flags) {\n            p_CB->waits &= p_CB->events;\n            rdy:\n            p_CB->events &= ~event_flags;\n            rt_rmv_dly(p_CB);\n            p_CB->state = READY;\n#ifdef __CMSIS_RTOS\n            rt_ret_val2(p_CB, 0x08U/*osEventSignal*/, p_CB->waits);\n#else\n            rt_ret_val(p_CB, OS_R_EVT);\n#endif\n            rt_put_prio(&os_rdy, p_CB);\n        }\n    }\n}\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Event.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_EVENT.H\n *      Purpose: Implements waits and wake-ups for event flags\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Functions */\nextern OS_RESULT rt_evt_wait (U16 wait_flags,  U16 timeout, BOOL and_wait);\nextern void      rt_evt_set  (U16 event_flags, OS_TID task_id);\nextern void      rt_evt_clr  (U16 clear_flags, OS_TID task_id);\nextern void      isr_evt_set (U16 event_flags, OS_TID task_id);\nextern U16       rt_evt_get  (void);\nextern void      rt_evt_psh  (P_TCB p_CB, U16 set_flags);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_HAL_CM.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_HAL_CM.H\n *      Purpose: Hardware Abstraction Layer for Cortex-M definitions\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Definitions */\n#define INITIAL_xPSR    0x01000000U\n#define DEMCR_TRCENA    0x01000000U\n#define ITM_ITMENA      0x00000001U\n#define MAGIC_WORD      0xE25A2EA5U\n#define MAGIC_PATTERN   0xCCCCCCCCU\n\n#if defined (__CC_ARM)          /* ARM Compiler */\n\n#if ((defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) && !defined(NO_EXCLUSIVE_ACCESS))\n #define __USE_EXCLUSIVE_ACCESS\n#else\n #undef  __USE_EXCLUSIVE_ACCESS\n#endif\n\n#ifndef __CMSIS_GENERIC\n#define __DMB() do {\\\n                   __schedule_barrier();\\\n                   __dmb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0)\n#endif\n\n#elif defined (__GNUC__)        /* GNU Compiler */\n\n#undef  __USE_EXCLUSIVE_ACCESS\n\n#if defined (__CORTEX_M0)\n#define __TARGET_ARCH_6S_M\n#endif\n\n#if defined (__VFP_FP__) && !defined(__SOFTFP__)\n#define __TARGET_FPU_VFP\n#endif\n\n#define __inline inline\n#define __weak   __attribute__((weak))\n\n#ifndef __CMSIS_GENERIC\n\n__attribute__((always_inline)) static inline void __enable_irq(void)\n{\n  __asm volatile (\"cpsie i\");\n}\n\n__attribute__((always_inline)) static inline U32 __disable_irq(void)\n{\n  U32 result;\n\n  __asm volatile (\"mrs %0, primask\" : \"=r\" (result));\n  __asm volatile (\"cpsid i\");\n  return(result & 1);\n}\n\n__attribute__((always_inline)) static inline void __DMB(void)\n{\n  __asm volatile (\"dmb 0xF\":::\"memory\");\n}\n\n#endif\n\n__attribute__(( always_inline)) static inline U8 __clz(U32 value)\n{\n  U8 result;\n  \n  __asm volatile (\"clz %0, %1\" : \"=r\" (result) : \"r\" (value));\n  return(result);\n}\n\n#elif defined (__ICCARM__)      /* IAR Compiler */\n\n#undef  __USE_EXCLUSIVE_ACCESS\n\n#if (__CORE__ == __ARM6M__)\n#define __TARGET_ARCH_6S_M 1\n#endif\n\n#if defined __ARMVFP__\n#define __TARGET_FPU_VFP 1\n#endif\n\n#define __inline inline\n\n#ifndef __CMSIS_GENERIC\n\nstatic inline void __enable_irq(void)\n{\n  __asm volatile (\"cpsie i\");\n}\n\nstatic inline U32 __disable_irq(void)\n{\n  U32 result;\n  \n  __asm volatile (\"mrs %0, primask\" : \"=r\" (result));\n  __asm volatile (\"cpsid i\");\n  return(result & 1);\n}\n\n#endif\n\nstatic inline U8 __clz(U32 value)\n{\n  U8 result;\n  \n  __asm volatile (\"clz %0, %1\" : \"=r\" (result) : \"r\" (value));\n  return(result);\n}\n\n#endif\n\n/* NVIC registers */\n#define NVIC_ST_CTRL    (*((volatile U32 *)0xE000E010U))\n#define NVIC_ST_RELOAD  (*((volatile U32 *)0xE000E014U))\n#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018U))\n#define NVIC_ISER         ((volatile U32 *)0xE000E100U)\n#define NVIC_ICER         ((volatile U32 *)0xE000E180U)\n#if defined(__TARGET_ARCH_6S_M)\n#define NVIC_IP           ((volatile U32 *)0xE000E400U)\n#else\n#define NVIC_IP           ((volatile U8  *)0xE000E400U)\n#endif\n#define NVIC_INT_CTRL   (*((volatile U32 *)0xE000ED04U))\n#define NVIC_AIR_CTRL   (*((volatile U32 *)0xE000ED0CU))\n#define NVIC_SYS_PRI2   (*((volatile U32 *)0xE000ED1CU))\n#define NVIC_SYS_PRI3   (*((volatile U32 *)0xE000ED20U))\n\n#define OS_PEND_IRQ()   NVIC_INT_CTRL  = (1UL<<28)\n#define OS_PENDING      ((NVIC_INT_CTRL >> 26) & 5U)\n#define OS_UNPEND(fl)   NVIC_INT_CTRL  = (U32)(fl = (U8)OS_PENDING) << 25\n#define OS_PEND(fl,p)   NVIC_INT_CTRL  = (U32)(fl | (U8)(p<<2)) << 26\n#define OS_LOCK()       NVIC_ST_CTRL   =  0x0005U\n#define OS_UNLOCK()     NVIC_ST_CTRL   =  0x0007U\n\n#define OS_X_PENDING    ((NVIC_INT_CTRL >> 28) & 1U)\n#define OS_X_UNPEND(fl) NVIC_INT_CTRL  = (U32)(fl = (U8)OS_X_PENDING) << 27\n#define OS_X_PEND(fl,p) NVIC_INT_CTRL  = (U32)(fl | p) << 28\n#if defined(__TARGET_ARCH_6S_M)\n#define OS_X_INIT(n)    NVIC_IP[n>>2] |=  (U32)0xFFU << ((n & 0x03U) << 3); \\\n                        NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)\n#else\n#define OS_X_INIT(n)    NVIC_IP[n] = 0xFFU; \\\n                        NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)\n#endif\n#define OS_X_LOCK(n)    NVIC_ICER[n>>5] = (U32)1U << (n & 0x1FU)\n#define OS_X_UNLOCK(n)  NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)\n\n/* Core Debug registers */\n#define DEMCR           (*((volatile U32 *)0xE000EDFCU))\n\n/* ITM registers */\n#define ITM_CONTROL     (*((volatile U32 *)0xE0000E80U))\n#define ITM_ENABLE      (*((volatile U32 *)0xE0000E00U))\n#define ITM_PORT30_U32  (*((volatile U32 *)0xE0000078U))\n#define ITM_PORT31_U32  (*((volatile U32 *)0xE000007CU))\n#define ITM_PORT31_U16  (*((volatile U16 *)0xE000007CU))\n#define ITM_PORT31_U8   (*((volatile U8  *)0xE000007CU))\n\n/* Variables */\nextern BIT dbg_msg;\n\n/* Functions */\n#ifdef __USE_EXCLUSIVE_ACCESS\n #define rt_inc(p)     while(__strex((__ldrex(p)+1U),p))\n #define rt_dec(p)     while(__strex((__ldrex(p)-1U),p))\n#else\n #define rt_inc(p)     __disable_irq();(*p)++;__enable_irq();\n #define rt_dec(p)     __disable_irq();(*p)--;__enable_irq();\n#endif\n\n__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {\n  U32 cnt,c2;\n#ifdef __USE_EXCLUSIVE_ACCESS\n  do {\n    if ((cnt = __ldrex(count)) == size) {\n      __clrex();\n      return (cnt); }\n  } while (__strex(cnt+1U, count));\n  do {\n    c2 = (cnt = __ldrex(first)) + 1U;\n    if (c2 == size) { c2 = 0U; }\n  } while (__strex(c2, first));\n#else\n  __disable_irq();\n  if ((cnt = *count) < size) {\n    *count = (U8)(cnt+1U);\n    c2 = (cnt = *first) + 1U;\n    if (c2 == size) { c2 = 0U; }\n    *first = (U8)c2; \n  }\n  __enable_irq ();\n#endif\n  return (cnt);\n}\n\n__inline static void rt_systick_init (void) {\n  NVIC_ST_RELOAD  = os_trv;\n  NVIC_ST_CURRENT = 0U;\n  NVIC_ST_CTRL    = 0x0007U;\n  NVIC_SYS_PRI3  |= 0xFF000000U;\n}\n\n__inline static U32 rt_systick_val (void) {\n  return (os_trv - NVIC_ST_CURRENT);\n}\n\n__inline static U32 rt_systick_ovf (void) {\n  return ((NVIC_INT_CTRL >> 26) & 1U);\n}\n\n__inline static void rt_svc_init (void) {\n#if !defined(__TARGET_ARCH_6S_M)\n  U32 sh,prigroup;\n#endif\n  NVIC_SYS_PRI3 |= 0x00FF0000U;\n#if defined(__TARGET_ARCH_6S_M)\n  NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000U;\n#else\n  sh       = 8U - __clz(~((NVIC_SYS_PRI3 << 8) & 0xFF000000U));\n  prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07U);\n  if (prigroup >= sh) {\n    sh = prigroup + 1U;\n  }\n  NVIC_SYS_PRI2 = ((0xFEFFFFFFU << sh) & 0xFF000000U) | (NVIC_SYS_PRI2 & 0x00FFFFFFU);\n#endif\n}\n\nextern void rt_set_PSP (U32 stack);\nextern U32  rt_get_PSP (void);\nextern void os_set_env (void);\nextern void *_alloc_box (void *box_mem);\nextern U32  _free_box (void *box_mem, void *box);\n\nextern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);\nextern void rt_ret_val  (P_TCB p_TCB, U32 v0);\nextern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);\n\nextern void dbg_init (void);\nextern void dbg_task_notify (P_TCB p_tcb, BOOL create);\nextern void dbg_task_switch (U32 task_id);\n\n#ifdef DBG_MSG\n#define DBG_INIT() dbg_init()\n#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)\n#define DBG_TASK_SWITCH(task_id)      if (dbg_msg && (os_tsk.next!=os_tsk.run)) \\\n                                        dbg_task_switch(task_id)\n#else\n#define DBG_INIT()\n#define DBG_TASK_NOTIFY(p_tcb,create)\n#define DBG_TASK_SWITCH(task_id)\n#endif\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_List.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_LIST.C\n *      Purpose: Functions for the management of different lists\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_List.h\"\n#include \"rt_Task.h\"\n#include \"rt_Time.h\"\n#include \"rt_HAL_CM.h\"\n\n/*----------------------------------------------------------------------------\n *      Global Variables\n *---------------------------------------------------------------------------*/\n\n/* List head of chained ready tasks */\nstruct OS_XCB os_rdy;\n/* List head of chained delay tasks */\nstruct OS_XCB os_dly;\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_put_prio -----------------------------------*/\n\nvoid rt_put_prio(P_XCB p_CB, P_TCB p_task) {\n    /* Put task identified with \"p_task\" into list ordered by priority.       */\n    /* \"p_CB\" points to head of list; list has always an element at end with  */\n    /* a priority less than \"p_task->prio\".                                   */\n    P_TCB p_CB2;\n    U32 prio;\n    BOOL sem_mbx = __FALSE;\n\n    if ((p_CB->cb_type == SCB) || (p_CB->cb_type == MCB) || (p_CB->cb_type == MUCB)) {\n        sem_mbx = __TRUE;\n    }\n    prio = p_task->prio;\n    p_CB2 = p_CB->p_lnk;\n    /* Search for an entry in the list */\n    while ((p_CB2 != NULL) && (prio <= p_CB2->prio)) {\n        p_CB = (P_XCB) p_CB2;\n        p_CB2 = p_CB2->p_lnk;\n    }\n    /* Entry found, insert the task into the list */\n    p_task->p_lnk = p_CB2;\n    p_CB->p_lnk = p_task;\n    if (sem_mbx) {\n        if (p_CB2 != NULL) {\n            p_CB2->p_rlnk = p_task;\n        }\n        p_task->p_rlnk = (P_TCB) p_CB;\n    } else {\n        p_task->p_rlnk = NULL;\n    }\n}\n\n\n/*--------------------------- rt_get_first ----------------------------------*/\n\nP_TCB rt_get_first(P_XCB p_CB) {\n    /* Get task at head of list: it is the task with highest priority. */\n    /* \"p_CB\" points to head of list. */\n    P_TCB p_first;\n\n    p_first = p_CB->p_lnk;\n    p_CB->p_lnk = p_first->p_lnk;\n    if ((p_CB->cb_type == SCB) || (p_CB->cb_type == MCB) || (p_CB->cb_type == MUCB)) {\n        if (p_first->p_lnk != NULL) {\n            p_first->p_lnk->p_rlnk = (P_TCB) p_CB;\n            p_first->p_lnk = NULL;\n        }\n        p_first->p_rlnk = NULL;\n    } else {\n        p_first->p_lnk = NULL;\n    }\n    return (p_first);\n}\n\n\n/*--------------------------- rt_put_rdy_first ------------------------------*/\n\nvoid rt_put_rdy_first(P_TCB p_task) {\n    /* Put task identified with \"p_task\" at the head of the ready list. The   */\n    /* task must have at least a priority equal to highest priority in list.  */\n    p_task->p_lnk = os_rdy.p_lnk;\n    p_task->p_rlnk = NULL;\n    os_rdy.p_lnk = p_task;\n}\n\n\n/*--------------------------- rt_get_same_rdy_prio --------------------------*/\n\nP_TCB rt_get_same_rdy_prio(void) {\n    /* Remove a task of same priority from ready list if any exists. Other-   */\n    /* wise return NULL.                                                      */\n    P_TCB p_first;\n\n    p_first = os_rdy.p_lnk;\n    if (p_first->prio == os_tsk.run->prio) {\n        os_rdy.p_lnk = os_rdy.p_lnk->p_lnk;\n        return (p_first);\n    }\n    return (NULL);\n}\n\n\n/*--------------------------- rt_resort_prio --------------------------------*/\n\nvoid rt_resort_prio(P_TCB p_task) {\n    /* Re-sort ordered lists after the priority of 'p_task' has changed.      */\n    P_TCB p_CB;\n\n    if (p_task->p_rlnk == NULL) {\n        if (p_task->state == READY) {\n            /* Task is chained into READY list. */\n            p_CB = (P_TCB) &os_rdy;\n            goto res;\n        }\n    } else {\n        p_CB = p_task->p_rlnk;\n        while (p_CB->cb_type == TCB) {\n            /* Find a header of this task chain list. */\n            p_CB = p_CB->p_rlnk;\n        }\n        res:\n        rt_rmv_list(p_task);\n        rt_put_prio((P_XCB) p_CB, p_task);\n    }\n}\n\n\n/*--------------------------- rt_put_dly ------------------------------------*/\n\nvoid rt_put_dly(P_TCB p_task, U16 delay) {\n    /* Put a task identified with \"p_task\" into chained delay wait list using */\n    /* a delay value of \"delay\".                                              */\n    P_TCB p;\n    U32 delta, idelay = delay;\n\n    p = (P_TCB) &os_dly;\n    if (p->p_dlnk == NULL) {\n        /* Delay list empty */\n        delta = 0U;\n        goto last;\n    }\n    delta = os_dly.delta_time;\n    while (delta < idelay) {\n        if (p->p_dlnk == NULL) {\n            /* End of list found */\n            last:\n            p_task->p_dlnk = NULL;\n            p->p_dlnk = p_task;\n            p_task->p_blnk = p;\n            p->delta_time = (U16) (idelay - delta);\n            p_task->delta_time = 0U;\n            return;\n        }\n        p = p->p_dlnk;\n        delta += p->delta_time;\n    }\n    /* Right place found */\n    p_task->p_dlnk = p->p_dlnk;\n    p->p_dlnk = p_task;\n    p_task->p_blnk = p;\n    if (p_task->p_dlnk != NULL) {\n        p_task->p_dlnk->p_blnk = p_task;\n    }\n    p_task->delta_time = (U16) (delta - idelay);\n    p->delta_time -= p_task->delta_time;\n}\n\n\n/*--------------------------- rt_dec_dly ------------------------------------*/\n\nvoid rt_dec_dly(void) {\n    /* Decrement delta time of list head: remove tasks having a value of zero.*/\n    P_TCB p_rdy;\n\n    if (os_dly.p_dlnk == NULL) {\n        return;\n    }\n    os_dly.delta_time--;\n    while ((os_dly.delta_time == 0U) && (os_dly.p_dlnk != NULL)) {\n        p_rdy = os_dly.p_dlnk;\n        if (p_rdy->p_rlnk != NULL) {\n            /* Task is really enqueued, remove task from semaphore/mailbox */\n            /* timeout waiting list. */\n            p_rdy->p_rlnk->p_lnk = p_rdy->p_lnk;\n            if (p_rdy->p_lnk != NULL) {\n                p_rdy->p_lnk->p_rlnk = p_rdy->p_rlnk;\n                p_rdy->p_lnk = NULL;\n            }\n            p_rdy->p_rlnk = NULL;\n        }\n        rt_put_prio(&os_rdy, p_rdy);\n        os_dly.delta_time = p_rdy->delta_time;\n        if (p_rdy->state == WAIT_ITV) {\n            /* Calculate the next time for interval wait. */\n            p_rdy->delta_time = p_rdy->interval_time + (U16) os_time;\n        }\n        p_rdy->state = READY;\n        os_dly.p_dlnk = p_rdy->p_dlnk;\n        if (p_rdy->p_dlnk != NULL) {\n            p_rdy->p_dlnk->p_blnk = (P_TCB) &os_dly;\n            p_rdy->p_dlnk = NULL;\n        }\n        p_rdy->p_blnk = NULL;\n    }\n}\n\n\n/*--------------------------- rt_rmv_list -----------------------------------*/\n\nvoid rt_rmv_list(P_TCB p_task) {\n    /* Remove task identified with \"p_task\" from ready, semaphore or mailbox  */\n    /* waiting list if enqueued.                                              */\n    P_TCB p_b;\n\n    if (p_task->p_rlnk != NULL) {\n        /* A task is enqueued in semaphore / mailbox waiting list. */\n        p_task->p_rlnk->p_lnk = p_task->p_lnk;\n        if (p_task->p_lnk != NULL) {\n            p_task->p_lnk->p_rlnk = p_task->p_rlnk;\n        }\n        return;\n    }\n\n    p_b = (P_TCB) &os_rdy;\n    while (p_b != NULL) {\n        /* Search the ready list for task \"p_task\" */\n        if (p_b->p_lnk == p_task) {\n            p_b->p_lnk = p_task->p_lnk;\n            return;\n        }\n        p_b = p_b->p_lnk;\n    }\n}\n\n\n/*--------------------------- rt_rmv_dly ------------------------------------*/\n\nvoid rt_rmv_dly(P_TCB p_task) {\n    /* Remove task identified with \"p_task\" from delay list if enqueued.      */\n    P_TCB p_b;\n\n    p_b = p_task->p_blnk;\n    if (p_b != NULL) {\n        /* Task is really enqueued */\n        p_b->p_dlnk = p_task->p_dlnk;\n        if (p_task->p_dlnk != NULL) {\n            /* 'p_task' is in the middle of list */\n            p_b->delta_time += p_task->delta_time;\n            p_task->p_dlnk->p_blnk = p_b;\n            p_task->p_dlnk = NULL;\n        } else {\n            /* 'p_task' is at the end of list */\n            p_b->delta_time = 0U;\n        }\n        p_task->p_blnk = NULL;\n    }\n}\n\n\n/*--------------------------- rt_psq_enq ------------------------------------*/\n\nvoid rt_psq_enq(OS_ID entry, U32 arg) {\n    /* Insert post service request \"entry\" into ps-queue. */\n    U32 idx;\n\n    idx = rt_inc_qi(os_psq->size, &os_psq->count, &os_psq->first);\n    if (idx < os_psq->size) {\n        os_psq->q[idx].id = entry;\n        os_psq->q[idx].arg = arg;\n    } else {\n        os_error(OS_ERR_FIFO_OVF);\n    }\n}\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_List.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_LIST.H\n *      Purpose: Functions for the management of different lists\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Definitions */\n\n/* Values for 'cb_type' */\n#define TCB             0U\n#define MCB             1U\n#define SCB             2U\n#define MUCB            3U\n#define HCB             4U\n\n/* Variables */\nextern struct OS_XCB os_rdy;\nextern struct OS_XCB os_dly;\n\n/* Functions */\nextern void  rt_put_prio      (P_XCB p_CB, P_TCB p_task);\nextern P_TCB rt_get_first     (P_XCB p_CB);\nextern void  rt_put_rdy_first (P_TCB p_task);\nextern P_TCB rt_get_same_rdy_prio (void);\nextern void  rt_resort_prio   (P_TCB p_task);\nextern void  rt_put_dly       (P_TCB p_task, U16 delay);\nextern void  rt_dec_dly       (void);\nextern void  rt_rmv_list      (P_TCB p_task);\nextern void  rt_rmv_dly       (P_TCB p_task);\nextern void  rt_psq_enq       (OS_ID entry, U32 arg);\n\n/* This is a fast macro generating in-line code */\n#define rt_rdy_prio(void) (os_rdy.p_lnk->prio)\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Mailbox.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_MAILBOX.C\n *      Purpose: Implements waits and wake-ups for mailbox messages\n *      Rev.:    V4.81\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_List.h\"\n#include \"rt_Mailbox.h\"\n#include \"rt_MemBox.h\"\n#include \"rt_Task.h\"\n#include \"rt_HAL_CM.h\"\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_mbx_init -----------------------------------*/\n\nvoid rt_mbx_init(OS_ID mailbox, U16 mbx_size) {\n    /* Initialize a mailbox */\n    P_MCB p_MCB = mailbox;\n\n    p_MCB->cb_type = MCB;\n    p_MCB->state = 0U;\n    p_MCB->isr_st = 0U;\n    p_MCB->p_lnk = NULL;\n    p_MCB->first = 0U;\n    p_MCB->last = 0U;\n    p_MCB->count = 0U;\n    p_MCB->size = (U16) ((mbx_size - (sizeof(struct OS_MCB) - (sizeof(void *))))\n                         / sizeof(void *));\n}\n\n\n/*--------------------------- rt_mbx_send -----------------------------------*/\n\nOS_RESULT rt_mbx_send(OS_ID mailbox, void *p_msg, U16 timeout) {\n    /* Send message to a mailbox */\n    P_MCB p_MCB = mailbox;\n    P_TCB p_TCB;\n\n    if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 1U)) {\n        /* A task is waiting for message */\n        p_TCB = rt_get_first((P_XCB) p_MCB);\n#ifdef __CMSIS_RTOS\n        rt_ret_val2(p_TCB, 0x10U/*osEventMessage*/, (U32)p_msg);\n#else\n        *p_TCB->msg = p_msg;\n        rt_ret_val(p_TCB, OS_R_MBX);\n#endif\n        rt_rmv_dly(p_TCB);\n        rt_dispatch(p_TCB);\n    } else {\n        /* Store message in mailbox queue */\n        if (p_MCB->count == p_MCB->size) {\n            /* No free message entry, wait for one. If message queue is full, */\n            /* then no task is waiting for message. The 'p_MCB->p_lnk' list   */\n            /* pointer can now be reused for send message waits task list.    */\n            if (timeout == 0U) {\n                return (OS_R_TMO);\n            }\n            if (p_MCB->p_lnk != NULL) {\n                rt_put_prio((P_XCB) p_MCB, os_tsk.run);\n            } else {\n                p_MCB->p_lnk = os_tsk.run;\n                os_tsk.run->p_lnk = NULL;\n                os_tsk.run->p_rlnk = (P_TCB) p_MCB;\n                /* Task is waiting to send a message */\n                p_MCB->state = 2U;\n            }\n            os_tsk.run->msg = p_msg;\n            rt_block(timeout, WAIT_MBX);\n            return (OS_R_TMO);\n        }\n        /* Yes, there is a free entry in a mailbox. */\n        p_MCB->msg[p_MCB->first] = p_msg;\n        rt_inc (&p_MCB->count);\n        if (++p_MCB->first == p_MCB->size) {\n            p_MCB->first = 0U;\n        }\n    }\n    return (OS_R_OK);\n}\n\n\n/*--------------------------- rt_mbx_wait -----------------------------------*/\n\nOS_RESULT rt_mbx_wait(OS_ID mailbox, void **message, U16 timeout) {\n    /* Receive a message; possibly wait for it */\n    P_MCB p_MCB = mailbox;\n    P_TCB p_TCB;\n\n    /* If a message is available in the fifo buffer */\n    /* remove it from the fifo buffer and return. */\n    if (p_MCB->count) {\n        *message = p_MCB->msg[p_MCB->last];\n        if (++p_MCB->last == p_MCB->size) {\n            p_MCB->last = 0U;\n        }\n        if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2U)) {\n            /* A task is waiting to send message */\n            p_TCB = rt_get_first((P_XCB) p_MCB);\n#ifdef __CMSIS_RTOS\n            rt_ret_val(p_TCB, 0U/*osOK*/);\n#else\n            rt_ret_val(p_TCB, OS_R_OK);\n#endif\n            p_MCB->msg[p_MCB->first] = p_TCB->msg;\n            if (++p_MCB->first == p_MCB->size) {\n                p_MCB->first = 0U;\n            }\n            rt_rmv_dly(p_TCB);\n            rt_dispatch(p_TCB);\n        } else {\n            rt_dec (&p_MCB->count);\n        }\n        return (OS_R_OK);\n    }\n    /* No message available: wait for one */\n    if (timeout == 0U) {\n        return (OS_R_TMO);\n    }\n    if (p_MCB->p_lnk != NULL) {\n        rt_put_prio((P_XCB) p_MCB, os_tsk.run);\n    } else {\n        p_MCB->p_lnk = os_tsk.run;\n        os_tsk.run->p_lnk = NULL;\n        os_tsk.run->p_rlnk = (P_TCB) p_MCB;\n        /* Task is waiting to receive a message */\n        p_MCB->state = 1U;\n    }\n    rt_block(timeout, WAIT_MBX);\n#ifndef __CMSIS_RTOS\n    os_tsk.run->msg = message;\n#endif\n    return (OS_R_TMO);\n}\n\n\n/*--------------------------- rt_mbx_check ----------------------------------*/\n\nOS_RESULT rt_mbx_check(OS_ID mailbox) {\n    /* Check for free space in a mailbox. Returns the number of messages     */\n    /* that can be stored to a mailbox. It returns 0 when mailbox is full.   */\n    P_MCB p_MCB = mailbox;\n\n    return ((U32) (p_MCB->size - p_MCB->count));\n}\n\n\n/*--------------------------- isr_mbx_send ----------------------------------*/\n\nvoid isr_mbx_send(OS_ID mailbox, void *p_msg) {\n    /* Same function as \"os_mbx_send\", but to be called by ISRs. */\n    P_MCB p_MCB = mailbox;\n\n    rt_psq_enq(p_MCB, (U32) p_msg);\n    rt_psh_req();\n}\n\n\n/*--------------------------- isr_mbx_receive -------------------------------*/\n\nOS_RESULT isr_mbx_receive(OS_ID mailbox, void **message) {\n    /* Receive a message in the interrupt function. The interrupt function   */\n    /* should not wait for a message since this would block the rtx os.      */\n    P_MCB p_MCB = mailbox;\n\n    if (p_MCB->count) {\n        /* A message is available in the fifo buffer. */\n        *message = p_MCB->msg[p_MCB->last];\n        if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2U)) {\n            /* A task is locked waiting to send message */\n            rt_psq_enq(p_MCB, 0U);\n            rt_psh_req();\n        }\n        rt_dec (&p_MCB->count);\n        if (++p_MCB->last == p_MCB->size) {\n            p_MCB->last = 0U;\n        }\n        return (OS_R_MBX);\n    }\n    return (OS_R_OK);\n}\n\n\n/*--------------------------- rt_mbx_psh ------------------------------------*/\n\nvoid rt_mbx_psh(P_MCB p_CB, void *p_msg) {\n    /* Store the message to the mailbox queue or pass it to task directly. */\n    P_TCB p_TCB;\n    void *mem;\n\n    if (p_CB->p_lnk != NULL)\n        switch (p_CB->state) {\n#ifdef __CMSIS_RTOS\n            case 3:\n              /* Task is waiting to allocate memory, remove it from the waiting list */\n              mem = rt_alloc_box(p_msg);\n              if (mem == NULL) { break; }\n              p_TCB = rt_get_first ((P_XCB)p_CB);\n              rt_ret_val(p_TCB, (U32)mem);\n              p_TCB->state = READY;\n              rt_rmv_dly (p_TCB);\n              rt_put_prio (&os_rdy, p_TCB);\n              break;\n#endif\n            case 2:\n                /* Task is waiting to send a message, remove it from the waiting list */\n                p_TCB = rt_get_first((P_XCB) p_CB);\n#ifdef __CMSIS_RTOS\n                rt_ret_val(p_TCB, 0U/*osOK*/);\n#else\n                rt_ret_val(p_TCB, OS_R_OK);\n#endif\n                p_CB->msg[p_CB->first] = p_TCB->msg;\n                rt_inc (&p_CB->count);\n                if (++p_CB->first == p_CB->size) {\n                    p_CB->first = 0U;\n                }\n                p_TCB->state = READY;\n                rt_rmv_dly(p_TCB);\n                rt_put_prio(&os_rdy, p_TCB);\n                break;\n            case 1:\n                /* Task is waiting for a message, pass the message to the task directly */\n                p_TCB = rt_get_first((P_XCB) p_CB);\n#ifdef __CMSIS_RTOS\n                rt_ret_val2(p_TCB, 0x10U/*osEventMessage*/, (U32)p_msg);\n#else\n                *p_TCB->msg = p_msg;\n                rt_ret_val(p_TCB, OS_R_MBX);\n#endif\n                p_TCB->state = READY;\n                rt_rmv_dly(p_TCB);\n                rt_put_prio(&os_rdy, p_TCB);\n                break;\n            default:\n                break;\n        }\n    else {\n        /* No task is waiting for a message, store it to the mailbox queue */\n        if (p_CB->count < p_CB->size) {\n            p_CB->msg[p_CB->first] = p_msg;\n            rt_inc (&p_CB->count);\n            if (++p_CB->first == p_CB->size) {\n                p_CB->first = 0U;\n            }\n        } else {\n            os_error(OS_ERR_MBX_OVF);\n        }\n    }\n}\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Mailbox.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_MAILBOX.H\n *      Purpose: Implements waits and wake-ups for mailbox messages\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Functions */\nextern void      rt_mbx_init  (OS_ID mailbox, U16 mbx_size);\nextern OS_RESULT rt_mbx_send  (OS_ID mailbox, void *p_msg,    U16 timeout);\nextern OS_RESULT rt_mbx_wait  (OS_ID mailbox, void **message, U16 timeout);\nextern OS_RESULT rt_mbx_check (OS_ID mailbox);\nextern void      isr_mbx_send (OS_ID mailbox, void *p_msg);\nextern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);\nextern void      rt_mbx_psh   (P_MCB p_CB,    void *p_msg);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_MemBox.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_MEMBOX.C\n *      Purpose: Interface functions for fixed memory block management system\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_MemBox.h\"\n#include \"rt_HAL_CM.h\"\n\n/*----------------------------------------------------------------------------\n *      Global Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- _init_box -------------------------------------*/\n\nU32 _init_box(void *box_mem, U32 box_size, U32 blk_size) {\n    /* Initialize memory block system, returns 0 if OK, 1 if fails. */\n    void *end;\n    void *blk;\n    void *next;\n    U32 sizeof_bm;\n\n    /* Create memory structure. */\n    if (blk_size & BOX_ALIGN_8) {\n        /* Memory blocks 8-byte aligned. */\n        blk_size = ((blk_size & ~BOX_ALIGN_8) + 7U) & ~(U32) 7U;\n        sizeof_bm = (sizeof(struct OS_BM) + 7U) & ~(U32) 7U;\n    } else {\n        /* Memory blocks 4-byte aligned. */\n        blk_size = (blk_size + 3U) & ~(U32) 3U;\n        sizeof_bm = sizeof(struct OS_BM);\n    }\n    if (blk_size == 0U) {\n        return (1U);\n    }\n    if ((blk_size + sizeof_bm) > box_size) {\n        return (1U);\n    }\n    /* Create a Memory structure. */\n    blk = ((U8 *) box_mem) + sizeof_bm;\n    ((P_BM) box_mem)->free = blk;\n    end = ((U8 *) box_mem) + box_size;\n    ((P_BM) box_mem)->end = end;\n    ((P_BM) box_mem)->blk_size = blk_size;\n\n    /* Link all free blocks using offsets. */\n    end = ((U8 *) end) - blk_size;\n    while (1) {\n        next = ((U8 *) blk) + blk_size;\n        if (next > end) { break; }\n        *((void **) blk) = next;\n        blk = next;\n    }\n    /* end marker */\n    *((void **) blk) = 0U;\n    return (0U);\n}\n\n/*--------------------------- rt_alloc_box ----------------------------------*/\n\nvoid *rt_alloc_box(void *box_mem) {\n    /* Allocate a memory block and return start address. */\n    void **free;\n#ifndef __USE_EXCLUSIVE_ACCESS\n    U32 irq_mask;\n\n    irq_mask = (U32) __disable_irq();\n    free = ((P_BM) box_mem)->free;\n    if (free) {\n        ((P_BM) box_mem)->free = *free;\n    }\n    if (irq_mask == 0U) { __enable_irq(); }\n#else\n    do {\n      if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0U) {\n        __clrex();\n        break;\n      }\n    } while (__strex((U32)*free, &((P_BM) box_mem)->free));\n#endif\n    return (free);\n}\n\n\n/*--------------------------- _calloc_box -----------------------------------*/\n\nvoid *_calloc_box(void *box_mem) {\n    /* Allocate a 0-initialized memory block and return start address. */\n    void *free;\n    U32 *p;\n    U32 i;\n\n    free = _alloc_box(box_mem);\n    if (free) {\n        p = free;\n        for (i = ((P_BM) box_mem)->blk_size; i; i -= 4U) {\n            *p = 0U;\n            p++;\n        }\n    }\n    return (free);\n}\n\n\n/*--------------------------- rt_free_box -----------------------------------*/\n\nU32 rt_free_box(void *box_mem, void *box) {\n    /* Free a memory block, returns 0 if OK, 1 if box does not belong to box_mem */\n#ifndef __USE_EXCLUSIVE_ACCESS\n    U32 irq_mask;\n#endif\n\n    if ((box < box_mem) || (box >= ((P_BM) box_mem)->end)) {\n        return (1U);\n    }\n\n#ifndef __USE_EXCLUSIVE_ACCESS\n    irq_mask = (U32) __disable_irq();\n    *((void **) box) = ((P_BM) box_mem)->free;\n    ((P_BM) box_mem)->free = box;\n    if (irq_mask == 0U) { __enable_irq(); }\n#else\n    do {\n      do {\n        *((void **)box) = ((P_BM) box_mem)->free;\n        __DMB();\n      } while (*(void**)box != (void *)__ldrex(&((P_BM) box_mem)->free));\n    } while (__strex ((U32)box, &((P_BM) box_mem)->free));\n#endif\n    return (0U);\n}\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_MemBox.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_MEMBOX.H\n *      Purpose: Interface functions for fixed memory block management system\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Functions */\n#define rt_init_box     _init_box\n#define rt_calloc_box   _calloc_box\nextern U32     _init_box   (void *box_mem, U32 box_size, U32 blk_size);\nextern void *rt_alloc_box  (void *box_mem);\nextern void *  _calloc_box (void *box_mem);\nextern U32   rt_free_box   (void *box_mem, void *box);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Memory.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_MEMORY.C\n *      Purpose: Interface functions for Dynamic Memory Management System\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"rt_Memory.h\"\n\n\n/* Functions */\n\n// Initialize Dynamic Memory pool\n//   Parameters:\n//     pool:    Pointer to memory pool\n//     size:    Size of memory pool in bytes\n//   Return:    0 - OK, 1 - Error\n\nU32 rt_init_mem(void *pool, U32 size) {\n    MEMP *ptr;\n\n    if ((pool == NULL) || (size < sizeof(MEMP))) { return (1U); }\n\n    ptr = (MEMP *) pool;\n    ptr->next = (MEMP *) ((U32) pool + size - sizeof(MEMP *));\n    ptr->next->next = NULL;\n    ptr->len = 0U;\n\n    return (0U);\n}\n\n// Allocate Memory from Memory pool\n//   Parameters:\n//     pool:    Pointer to memory pool\n//     size:    Size of memory in bytes to allocate\n//   Return:    Pointer to allocated memory\n\nvoid *rt_alloc_mem(void *pool, U32 size) {\n    MEMP *p, *p_search, *p_new;\n    U32 hole_size;\n\n    if ((pool == NULL) || (size == 0U)) { return NULL; }\n\n    /* Add header offset to 'size' */\n    size += sizeof(MEMP);\n    /* Make sure that block is 4-byte aligned  */\n    size = (size + 3U) & ~(U32) 3U;\n\n    p_search = (MEMP *) pool;\n    while (1) {\n        hole_size = (U32) p_search->next - (U32) p_search;\n        hole_size -= p_search->len;\n        /* Check if hole size is big enough */\n        if (hole_size >= size) { break; }\n        p_search = p_search->next;\n        if (p_search->next == NULL) {\n            /* Failed, we are at the end of the list */\n            return NULL;\n        }\n    }\n\n    if (p_search->len == 0U) {\n        /* No block is allocated, set the Length of the first element */\n        p_search->len = size;\n        p = (MEMP *) (((U32) p_search) + sizeof(MEMP));\n    } else {\n        /* Insert new list element into the memory list */\n        p_new = (MEMP *) ((U32) p_search + p_search->len);\n        p_new->next = p_search->next;\n        p_new->len = size;\n        p_search->next = p_new;\n        p = (MEMP *) (((U32) p_new) + sizeof(MEMP));\n    }\n\n    return (p);\n}\n\n// Free Memory and return it to Memory pool\n//   Parameters:\n//     pool:    Pointer to memory pool\n//     mem:     Pointer to memory to free\n//   Return:    0 - OK, 1 - Error\n\nU32 rt_free_mem(void *pool, void *mem) {\n    MEMP *p_search, *p_prev, *p_return;\n\n    if ((pool == NULL) || (mem == NULL)) { return (1U); }\n\n    p_return = (MEMP *) ((U32) mem - sizeof(MEMP));\n\n    /* Set list header */\n    p_prev = NULL;\n    p_search = (MEMP *) pool;\n    while (p_search != p_return) {\n        p_prev = p_search;\n        p_search = p_search->next;\n        if (p_search == NULL) {\n            /* Valid Memory block not found */\n            return (1U);\n        }\n    }\n\n    if (p_prev == NULL) {\n        /* First block to be released, only set length to 0 */\n        p_search->len = 0U;\n    } else {\n        /* Discard block from chain list */\n        p_prev->next = p_search->next;\n    }\n\n    return (0U);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Memory.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_MEMORY.H\n *      Purpose: Interface functions for Dynamic Memory Management System\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Types */\ntypedef struct mem {              /* << Memory Pool management struct >>     */\n  struct mem *next;               /* Next Memory Block in the list           */\n  U32         len;                /* Length of data block                    */\n} MEMP;\n\n/* Functions */\nextern U32   rt_init_mem  (void *pool, U32  size);\nextern void *rt_alloc_mem (void *pool, U32  size);\nextern U32   rt_free_mem  (void *pool, void *mem);\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Mutex.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_MUTEX.C\n *      Purpose: Implements mutex synchronization objects\n *      Rev.:    V4.82\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_List.h\"\n#include \"rt_Task.h\"\n#include \"rt_Mutex.h\"\n#include \"rt_HAL_CM.h\"\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_mut_init -----------------------------------*/\n\nvoid rt_mut_init(OS_ID mutex) {\n    /* Initialize a mutex object */\n    P_MUCB p_MCB = mutex;\n\n    p_MCB->cb_type = MUCB;\n    p_MCB->level = 0U;\n    p_MCB->p_lnk = NULL;\n    p_MCB->owner = NULL;\n    p_MCB->p_mlnk = NULL;\n}\n\n\n/*--------------------------- rt_mut_delete ---------------------------------*/\n\n#ifdef __CMSIS_RTOS\nOS_RESULT rt_mut_delete (OS_ID mutex) {\n  /* Delete a mutex object */\n  P_MUCB p_MCB = mutex;\n  P_TCB  p_TCB;\n  P_MUCB p_mlnk;\n  U8     prio;\n\n  if (p_MCB->level != 0U) {\n\n    p_TCB = p_MCB->owner;\n\n    /* Remove mutex from task mutex owner list. */\n    p_mlnk = p_TCB->p_mlnk;\n    if (p_mlnk == p_MCB) {\n      p_TCB->p_mlnk = p_MCB->p_mlnk;\n    }\n    else {\n      while (p_mlnk) {\n        if (p_mlnk->p_mlnk == p_MCB) {\n          p_mlnk->p_mlnk = p_MCB->p_mlnk;\n          break;\n        }\n        p_mlnk = p_mlnk->p_mlnk;\n      }\n    }\n\n    /* Restore owner task's priority. */\n    prio = p_TCB->prio_base;\n    p_mlnk = p_TCB->p_mlnk;\n    while (p_mlnk) {\n      if ((p_mlnk->p_lnk != NULL) && (p_mlnk->p_lnk->prio > prio)) {\n        /* A task with higher priority is waiting for mutex. */\n        prio = p_mlnk->p_lnk->prio;\n      }\n      p_mlnk = p_mlnk->p_mlnk;\n    }\n    if (p_TCB->prio != prio) {\n      p_TCB->prio = prio;\n      if (p_TCB != os_tsk.run) {\n        rt_resort_prio (p_TCB);\n      }\n    }\n\n  }\n\n  while (p_MCB->p_lnk != NULL) {\n    /* A task is waiting for mutex. */\n    p_TCB = rt_get_first ((P_XCB)p_MCB);\n    rt_ret_val(p_TCB, 0U/*osOK*/);\n    rt_rmv_dly(p_TCB);\n    p_TCB->state = READY;\n    rt_put_prio (&os_rdy, p_TCB);\n  }\n\n  if ((os_rdy.p_lnk != NULL) && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {\n    /* preempt running task */\n    rt_put_prio (&os_rdy, os_tsk.run);\n    os_tsk.run->state = READY;\n    rt_dispatch (NULL);\n  }\n\n  p_MCB->cb_type = 0U;\n\n  return (OS_R_OK);\n}\n#endif\n\n\n/*--------------------------- rt_mut_release --------------------------------*/\n\nOS_RESULT rt_mut_release(OS_ID mutex) {\n    /* Release a mutex object */\n    P_MUCB p_MCB = mutex;\n    P_TCB p_TCB;\n    P_MUCB p_mlnk;\n    U8 prio;\n\n    if ((p_MCB->level == 0U) || (p_MCB->owner != os_tsk.run)) {\n        /* Unbalanced mutex release or task is not the owner */\n        return (OS_R_NOK);\n    }\n    if (--p_MCB->level != 0U) {\n        return (OS_R_OK);\n    }\n\n    /* Remove mutex from task mutex owner list. */\n    p_mlnk = os_tsk.run->p_mlnk;\n    if (p_mlnk == p_MCB) {\n        os_tsk.run->p_mlnk = p_MCB->p_mlnk;\n    } else {\n        while (p_mlnk) {\n            if (p_mlnk->p_mlnk == p_MCB) {\n                p_mlnk->p_mlnk = p_MCB->p_mlnk;\n                break;\n            }\n            p_mlnk = p_mlnk->p_mlnk;\n        }\n    }\n\n    /* Restore owner task's priority. */\n    prio = os_tsk.run->prio_base;\n    p_mlnk = os_tsk.run->p_mlnk;\n    while (p_mlnk) {\n        if ((p_mlnk->p_lnk != NULL) && (p_mlnk->p_lnk->prio > prio)) {\n            /* A task with higher priority is waiting for mutex. */\n            prio = p_mlnk->p_lnk->prio;\n        }\n        p_mlnk = p_mlnk->p_mlnk;\n    }\n    os_tsk.run->prio = prio;\n\n    if (p_MCB->p_lnk != NULL) {\n        /* A task is waiting for mutex. */\n        p_TCB = rt_get_first((P_XCB) p_MCB);\n#ifdef __CMSIS_RTOS\n        rt_ret_val(p_TCB, 0U/*osOK*/);\n#else\n        rt_ret_val(p_TCB, OS_R_MUT);\n#endif\n        rt_rmv_dly(p_TCB);\n        /* A waiting task becomes the owner of this mutex. */\n        p_MCB->level = 1U;\n        p_MCB->owner = p_TCB;\n        p_MCB->p_mlnk = p_TCB->p_mlnk;\n        p_TCB->p_mlnk = p_MCB;\n        /* Priority inversion, check which task continues. */\n        if (os_tsk.run->prio >= rt_rdy_prio()) {\n            rt_dispatch(p_TCB);\n        } else {\n            /* Ready task has higher priority than running task. */\n            rt_put_prio(&os_rdy, os_tsk.run);\n            rt_put_prio(&os_rdy, p_TCB);\n            os_tsk.run->state = READY;\n            p_TCB->state = READY;\n            rt_dispatch(NULL);\n        }\n    } else {\n        /* Check if own priority lowered by priority inversion. */\n        if (rt_rdy_prio() > os_tsk.run->prio) {\n            rt_put_prio(&os_rdy, os_tsk.run);\n            os_tsk.run->state = READY;\n            rt_dispatch(NULL);\n        }\n    }\n    return (OS_R_OK);\n}\n\n\n/*--------------------------- rt_mut_wait -----------------------------------*/\n\nOS_RESULT rt_mut_wait(OS_ID mutex, U16 timeout) {\n    /* Wait for a mutex, continue when mutex is free. */\n    P_MUCB p_MCB = mutex;\n\n    if (p_MCB->level == 0U) {\n        p_MCB->owner = os_tsk.run;\n        p_MCB->p_mlnk = os_tsk.run->p_mlnk;\n        os_tsk.run->p_mlnk = p_MCB;\n        p_MCB->level = 1U;\n        return (OS_R_OK);\n    }\n    if (p_MCB->owner == os_tsk.run) {\n        /* OK, running task is the owner of this mutex. */\n        if (p_MCB->level == 0xFFFFU) {\n            return (OS_R_NOK);\n        }\n        p_MCB->level++;\n        return (OS_R_OK);\n    }\n    /* Mutex owned by another task, wait until released. */\n    if (timeout == 0U) {\n        return (OS_R_TMO);\n    }\n    /* Raise the owner task priority if lower than current priority. */\n    /* This priority inversion is called priority inheritance.       */\n    if (p_MCB->owner->prio < os_tsk.run->prio) {\n        p_MCB->owner->prio = os_tsk.run->prio;\n        rt_resort_prio(p_MCB->owner);\n    }\n    if (p_MCB->p_lnk != NULL) {\n        rt_put_prio((P_XCB) p_MCB, os_tsk.run);\n    } else {\n        p_MCB->p_lnk = os_tsk.run;\n        os_tsk.run->p_lnk = NULL;\n        os_tsk.run->p_rlnk = (P_TCB) p_MCB;\n    }\n    rt_block(timeout, WAIT_MUT);\n    return (OS_R_TMO);\n}\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Mutex.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_MUTEX.H\n *      Purpose: Implements mutex synchronization objects\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Functions */\nextern void      rt_mut_init    (OS_ID mutex);\nextern OS_RESULT rt_mut_delete  (OS_ID mutex);\nextern OS_RESULT rt_mut_release (OS_ID mutex);\nextern OS_RESULT rt_mut_wait    (OS_ID mutex, U16 timeout);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Robin.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_ROBIN.C\n *      Purpose: Round Robin Task switching\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_List.h\"\n#include \"rt_Task.h\"\n#include \"rt_Time.h\"\n#include \"rt_Robin.h\"\n#include \"rt_HAL_CM.h\"\n\n/*----------------------------------------------------------------------------\n *      Global Variables\n *---------------------------------------------------------------------------*/\n\nstruct OS_ROBIN os_robin;\n\n\n/*----------------------------------------------------------------------------\n *      Global Functions\n *---------------------------------------------------------------------------*/\n\n/*--------------------------- rt_init_robin ---------------------------------*/\n\n__weak void rt_init_robin(void) {\n    /* Initialize Round Robin variables. */\n    os_robin.task = NULL;\n    os_robin.tout = (U16) os_rrobin;\n}\n\n/*--------------------------- rt_chk_robin ----------------------------------*/\n\n__weak void rt_chk_robin(void) {\n    /* Check if Round Robin timeout expired and switch to the next ready task.*/\n    P_TCB p_new;\n\n    if (os_robin.task != os_rdy.p_lnk) {\n        /* New task was suspended, reset Round Robin timeout. */\n        os_robin.task = os_rdy.p_lnk;\n        os_robin.time = (U16) os_time + os_robin.tout - 1U;\n    }\n    if (os_robin.time == (U16) os_time) {\n        /* Round Robin timeout has expired, swap Robin tasks. */\n        os_robin.task = NULL;\n        p_new = rt_get_first(&os_rdy);\n        rt_put_prio((P_XCB) &os_rdy, p_new);\n    }\n}\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Robin.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_ROBIN.H\n *      Purpose: Round Robin Task switching definitions\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Variables */\nextern struct OS_ROBIN os_robin;\n\n/* Functions */\nextern void rt_init_robin (void);\nextern void rt_chk_robin  (void);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Semaphore.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_SEMAPHORE.C\n *      Purpose: Implements binary and counting semaphores\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_List.h\"\n#include \"rt_Task.h\"\n#include \"rt_Semaphore.h\"\n#include \"rt_HAL_CM.h\"\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_sem_init -----------------------------------*/\n\nvoid rt_sem_init(OS_ID semaphore, U16 token_count) {\n    /* Initialize a semaphore */\n    P_SCB p_SCB = semaphore;\n\n    p_SCB->cb_type = SCB;\n    p_SCB->p_lnk = NULL;\n    p_SCB->tokens = token_count;\n}\n\n\n/*--------------------------- rt_sem_delete ---------------------------------*/\n\n#ifdef __CMSIS_RTOS\nOS_RESULT rt_sem_delete (OS_ID semaphore) {\n  /* Delete semaphore */\n  P_SCB p_SCB = semaphore;\n  P_TCB p_TCB;\n\n  while (p_SCB->p_lnk != NULL) {\n    /* A task is waiting for token */\n    p_TCB = rt_get_first ((P_XCB)p_SCB);\n    rt_ret_val(p_TCB, 0U);\n    rt_rmv_dly(p_TCB);\n    p_TCB->state = READY;\n    rt_put_prio (&os_rdy, p_TCB);\n  }\n\n  if ((os_rdy.p_lnk != NULL) && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {\n    /* preempt running task */\n    rt_put_prio (&os_rdy, os_tsk.run);\n    os_tsk.run->state = READY;\n    rt_dispatch (NULL);\n  }\n\n  p_SCB->cb_type = 0U;\n\n  return (OS_R_OK);\n}\n#endif\n\n\n/*--------------------------- rt_sem_send -----------------------------------*/\n\nOS_RESULT rt_sem_send(OS_ID semaphore) {\n    /* Return a token to semaphore */\n    P_SCB p_SCB = semaphore;\n    P_TCB p_TCB;\n\n    if (p_SCB->p_lnk != NULL) {\n        /* A task is waiting for token */\n        p_TCB = rt_get_first((P_XCB) p_SCB);\n#ifdef __CMSIS_RTOS\n        rt_ret_val(p_TCB, 1U);\n#else\n        rt_ret_val(p_TCB, OS_R_SEM);\n#endif\n        rt_rmv_dly(p_TCB);\n        rt_dispatch(p_TCB);\n    } else {\n        /* Store token. */\n        p_SCB->tokens++;\n    }\n    return (OS_R_OK);\n}\n\n\n/*--------------------------- rt_sem_wait -----------------------------------*/\n\nOS_RESULT rt_sem_wait(OS_ID semaphore, U16 timeout) {\n    /* Obtain a token; possibly wait for it */\n    P_SCB p_SCB = semaphore;\n\n    if (p_SCB->tokens) {\n        p_SCB->tokens--;\n        return (OS_R_OK);\n    }\n    /* No token available: wait for one */\n    if (timeout == 0U) {\n        return (OS_R_TMO);\n    }\n    if (p_SCB->p_lnk != NULL) {\n        rt_put_prio((P_XCB) p_SCB, os_tsk.run);\n    } else {\n        p_SCB->p_lnk = os_tsk.run;\n        os_tsk.run->p_lnk = NULL;\n        os_tsk.run->p_rlnk = (P_TCB) p_SCB;\n    }\n    rt_block(timeout, WAIT_SEM);\n    return (OS_R_TMO);\n}\n\n\n/*--------------------------- isr_sem_send ----------------------------------*/\n\nvoid isr_sem_send(OS_ID semaphore) {\n    /* Same function as \"os_sem_send\", but to be called by ISRs */\n    P_SCB p_SCB = semaphore;\n\n    rt_psq_enq(p_SCB, 0U);\n    rt_psh_req();\n}\n\n\n/*--------------------------- rt_sem_psh ------------------------------------*/\n\nvoid rt_sem_psh(P_SCB p_CB) {\n    /* Check if task has to be waken up */\n    P_TCB p_TCB;\n\n    if (p_CB->p_lnk != NULL) {\n        /* A task is waiting for token */\n        p_TCB = rt_get_first((P_XCB) p_CB);\n        rt_rmv_dly(p_TCB);\n        p_TCB->state = READY;\n#ifdef __CMSIS_RTOS\n        rt_ret_val(p_TCB, 1U);\n#else\n        rt_ret_val(p_TCB, OS_R_SEM);\n#endif\n        rt_put_prio(&os_rdy, p_TCB);\n    } else {\n        /* Store token */\n        p_CB->tokens++;\n    }\n}\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Semaphore.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_SEMAPHORE.H\n *      Purpose: Implements binary and counting semaphores\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Functions */\nextern void      rt_sem_init  (OS_ID semaphore, U16 token_count);\nextern OS_RESULT rt_sem_delete(OS_ID semaphore);\nextern OS_RESULT rt_sem_send  (OS_ID semaphore);\nextern OS_RESULT rt_sem_wait  (OS_ID semaphore, U16 timeout);\nextern void      isr_sem_send (OS_ID semaphore);\nextern void      rt_sem_psh (P_SCB p_CB);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_System.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_SYSTEM.C\n *      Purpose: System Task Manager\n *      Rev.:    V4.82\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_Task.h\"\n#include \"rt_System.h\"\n#include \"rt_Event.h\"\n#include \"rt_List.h\"\n#include \"rt_Mailbox.h\"\n#include \"rt_Semaphore.h\"\n#include \"rt_Time.h\"\n#include \"rt_Timer.h\"\n#include \"rt_Robin.h\"\n#include \"rt_HAL_CM.h\"\n\n/*----------------------------------------------------------------------------\n *      Global Variables\n *---------------------------------------------------------------------------*/\n\nS32 os_tick_irqn;\n\n/*----------------------------------------------------------------------------\n *      Local Variables\n *---------------------------------------------------------------------------*/\n\nstatic volatile BIT os_lock;\nstatic volatile BIT os_psh_flag;\nstatic U8 pend_flags;\n\n/*----------------------------------------------------------------------------\n *      Global Functions\n *---------------------------------------------------------------------------*/\n\n#define RL_RTX_VER      0x482\n\n#if defined (__CC_ARM)\n__asm void $$RTX$$version (void) {\n   /* Export a version number symbol for a version control. */\n\n                EXPORT  __RL_RTX_VER\n\n__RL_RTX_VER    EQU     RL_RTX_VER\n}\n#endif\n\n\n/*--------------------------- rt_suspend ------------------------------------*/\n\nextern U32 sysUserTimerWakeupTime(void);\n\nU32 rt_suspend(void) {\n    /* Suspend OS scheduler */\n    U32 delta = 0xFFFFU;\n#ifdef __CMSIS_RTOS\n    U32 sleep;\n#endif\n\n    rt_tsk_lock();\n\n    if (os_dly.p_dlnk) {\n        delta = os_dly.delta_time;\n    }\n#ifdef __CMSIS_RTOS\n    sleep = sysUserTimerWakeupTime();\n    if (sleep < delta) { delta = sleep; }\n#else\n    if (os_tmr.next) {\n        if (os_tmr.tcnt < delta) delta = os_tmr.tcnt;\n    }\n#endif\n\n    return (delta);\n}\n\n\n/*--------------------------- rt_resume -------------------------------------*/\n\nextern void sysUserTimerUpdate(U32 sleep_time);\n\nvoid rt_resume(U32 sleep_time) {\n    /* Resume OS scheduler after suspend */\n    P_TCB next;\n    U32 delta;\n\n    os_tsk.run->state = READY;\n    rt_put_rdy_first(os_tsk.run);\n\n    os_robin.task = NULL;\n\n    /* Update delays. */\n    if (os_dly.p_dlnk) {\n        delta = sleep_time;\n        if (delta >= os_dly.delta_time) {\n            delta -= os_dly.delta_time;\n            os_time += os_dly.delta_time;\n            os_dly.delta_time = 1U;\n            while (os_dly.p_dlnk) {\n                rt_dec_dly();\n                if (delta == 0U) { break; }\n                delta--;\n                os_time++;\n            }\n        } else {\n            os_time += delta;\n            os_dly.delta_time -= (U16) delta;\n        }\n    } else {\n        os_time += sleep_time;\n    }\n\n    /* Check the user timers. */\n#ifdef __CMSIS_RTOS\n    sysUserTimerUpdate(sleep_time);\n#else\n    if (os_tmr.next) {\n        delta = sleep_time;\n        if (delta >= os_tmr.tcnt) {\n            delta -= os_tmr.tcnt;\n            os_tmr.tcnt = 1U;\n            while (os_tmr.next) {\n                rt_tmr_tick();\n                if (delta == 0U) { break; }\n                delta--;\n            }\n        } else {\n            os_tmr.tcnt -= delta;\n        }\n    }\n#endif\n\n    /* Switch back to highest ready task */\n    next = rt_get_first(&os_rdy);\n    rt_switch_req(next);\n\n    rt_tsk_unlock();\n}\n\n\n/*--------------------------- rt_tsk_lock -----------------------------------*/\n\nvoid rt_tsk_lock(void) {\n    /* Prevent task switching by locking out scheduler */\n    if (os_tick_irqn < 0) {\n        OS_LOCK();\n        os_lock = __TRUE;\n        OS_UNPEND(pend_flags);\n    } else {\n        OS_X_LOCK((U32) os_tick_irqn);\n        os_lock = __TRUE;\n        OS_X_UNPEND(pend_flags);\n    }\n}\n\n\n/*--------------------------- rt_tsk_unlock ---------------------------------*/\n\nvoid rt_tsk_unlock(void) {\n    /* Unlock scheduler and re-enable task switching */\n    if (os_tick_irqn < 0) {\n        OS_UNLOCK();\n        os_lock = __FALSE;\n        OS_PEND(pend_flags, os_psh_flag);\n        os_psh_flag = __FALSE;\n    } else {\n        OS_X_UNLOCK((U32) os_tick_irqn);\n        os_lock = __FALSE;\n        OS_X_PEND(pend_flags, os_psh_flag);\n        os_psh_flag = __FALSE;\n    }\n}\n\n\n/*--------------------------- rt_psh_req ------------------------------------*/\n\nvoid rt_psh_req(void) {\n    /* Initiate a post service handling request if required. */\n    if (os_lock == __FALSE) {\n        OS_PEND_IRQ();\n    } else {\n        os_psh_flag = __TRUE;\n    }\n}\n\n\n/*--------------------------- rt_pop_req ------------------------------------*/\n\nvoid rt_pop_req(void) {\n    /* Process an ISR post service requests. */\n    struct OS_XCB *p_CB;\n    P_TCB next;\n    U32 idx;\n\n    os_tsk.run->state = READY;\n    rt_put_rdy_first(os_tsk.run);\n\n    idx = os_psq->last;\n    while (os_psq->count) {\n        p_CB = os_psq->q[idx].id;\n        if (p_CB->cb_type == TCB) {\n            /* Is of TCB type */\n            rt_evt_psh((P_TCB) p_CB, (U16) os_psq->q[idx].arg);\n        } else if (p_CB->cb_type == MCB) {\n            /* Is of MCB type */\n            rt_mbx_psh((P_MCB) p_CB, (void *) os_psq->q[idx].arg);\n        } else {\n            /* Must be of SCB type */\n            rt_sem_psh((P_SCB) p_CB);\n        }\n        if (++idx == os_psq->size) { idx = 0U; }\n        rt_dec (&os_psq->count);\n    }\n    os_psq->last = (U8) idx;\n\n    next = rt_get_first(&os_rdy);\n    rt_switch_req(next);\n}\n\n\n/*--------------------------- os_tick_init ----------------------------------*/\n\n__weak S32 os_tick_init(void) {\n    /* Initialize SysTick timer as system tick timer. */\n    rt_systick_init();\n    return (-1);  /* Return IRQ number of SysTick timer */\n}\n\n/*--------------------------- os_tick_val -----------------------------------*/\n\n__weak U32 os_tick_val(void) {\n    /* Get SysTick timer current value (0 .. OS_TRV). */\n    return rt_systick_val();\n}\n\n/*--------------------------- os_tick_ovf -----------------------------------*/\n\n__weak U32 os_tick_ovf(void) {\n    /* Get SysTick timer overflow flag */\n    return rt_systick_ovf();\n}\n\n/*--------------------------- os_tick_irqack --------------------------------*/\n\n__weak void os_tick_irqack(void) {\n    /* Acknowledge timer interrupt. */\n}\n\n\n/*--------------------------- rt_systick ------------------------------------*/\n\nextern void sysTimerTick(void);\n\nvoid rt_systick(void) {\n    /* Check for system clock update, suspend running task. */\n    P_TCB next;\n\n    os_tsk.run->state = READY;\n    rt_put_rdy_first(os_tsk.run);\n\n    /* Check Round Robin timeout. */\n    rt_chk_robin();\n\n    /* Update delays. */\n    os_time++;\n    rt_dec_dly();\n\n    /* Check the user timers. */\n#ifdef __CMSIS_RTOS\n    sysTimerTick();\n#else\n    rt_tmr_tick();\n#endif\n\n    /* Switch back to highest ready task */\n    next = rt_get_first(&os_rdy);\n    rt_switch_req(next);\n}\n\n/*--------------------------- rt_stk_check ----------------------------------*/\n\n__weak void rt_stk_check(void) {\n    /* Check for stack overflow. */\n    if ((os_tsk.run->tsk_stack < (U32) os_tsk.run->stack) ||\n        (os_tsk.run->stack[0] != MAGIC_WORD)) {\n        os_error(OS_ERR_STK_OVF);\n    }\n}\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_System.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_SYSTEM.H\n *      Purpose: System Task Manager definitions\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Variables */\n#define os_psq  ((P_PSQ)&os_fifo)\nextern S32 os_tick_irqn;\n\n/* Functions */\nextern U32  rt_suspend    (void);\nextern void rt_resume     (U32 sleep_time);\nextern void rt_tsk_lock   (void);\nextern void rt_tsk_unlock (void);\nextern void rt_psh_req    (void);\nextern void rt_pop_req    (void);\nextern void rt_systick    (void);\nextern void rt_stk_check  (void);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Task.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_TASK.C\n *      Purpose: Task functions and system start up.\n *      Rev.:    V4.80\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_System.h\"\n#include \"rt_Task.h\"\n#include \"rt_List.h\"\n#include \"rt_MemBox.h\"\n#include \"rt_Robin.h\"\n#include \"rt_HAL_CM.h\"\n\n/*----------------------------------------------------------------------------\n *      Global Variables\n *---------------------------------------------------------------------------*/\n\n/* Running and next task info. */\nstruct OS_TSK os_tsk;\n\n/* Task Control Blocks of idle demon */\nstruct OS_TCB os_idle_TCB;\n\n\n/*----------------------------------------------------------------------------\n *      Local Functions\n *---------------------------------------------------------------------------*/\n\nstatic OS_TID rt_get_TID(void) {\n    U32 tid;\n\n    for (tid = 1U; tid <= os_maxtaskrun; tid++) {\n        if (os_active_TCB[tid - 1U] == NULL) {\n            return ((OS_TID) tid);\n        }\n    }\n    return (0U);\n}\n\n\n/*--------------------------- rt_init_context -------------------------------*/\n\nstatic void rt_init_context(P_TCB p_TCB, U8 priority, FUNCP task_body) {\n    /* Initialize general part of the Task Control Block. */\n    p_TCB->cb_type = TCB;\n    p_TCB->state = READY;\n    p_TCB->prio = priority;\n    p_TCB->prio_base = priority;\n    p_TCB->p_lnk = NULL;\n    p_TCB->p_rlnk = NULL;\n    p_TCB->p_dlnk = NULL;\n    p_TCB->p_blnk = NULL;\n    p_TCB->p_mlnk = NULL;\n    p_TCB->delta_time = 0U;\n    p_TCB->interval_time = 0U;\n    p_TCB->events = 0U;\n    p_TCB->waits = 0U;\n    p_TCB->stack_frame = 0U;\n\n    if (p_TCB->priv_stack == 0U) {\n        /* Allocate the memory space for the stack. */\n        p_TCB->stack = rt_alloc_box(mp_stk);\n    }\n    rt_init_stack(p_TCB, task_body);\n}\n\n\n/*--------------------------- rt_switch_req ---------------------------------*/\n\nvoid rt_switch_req(P_TCB p_next) {\n    /* Switch to next task (identified by \"p_next\"). */\n    os_tsk.next = p_next;\n    p_next->state = RUNNING;\n    DBG_TASK_SWITCH(p_next->task_id);\n}\n\n\n/*--------------------------- rt_dispatch -----------------------------------*/\n\nvoid rt_dispatch(P_TCB next_TCB) {\n    /* Dispatch next task if any identified or dispatch highest ready task    */\n    /* \"next_TCB\" identifies a task to run or has value NULL (=no next task)  */\n    if (next_TCB == NULL) {\n        /* Running task was blocked: continue with highest ready task */\n        next_TCB = rt_get_first(&os_rdy);\n        rt_switch_req(next_TCB);\n    } else {\n        /* Check which task continues */\n        if (next_TCB->prio > os_tsk.run->prio) {\n            /* preempt running task */\n            rt_put_rdy_first(os_tsk.run);\n            os_tsk.run->state = READY;\n            rt_switch_req(next_TCB);\n        } else {\n            /* put next task into ready list, no task switch takes place */\n            next_TCB->state = READY;\n            rt_put_prio(&os_rdy, next_TCB);\n        }\n    }\n}\n\n\n/*--------------------------- rt_block --------------------------------------*/\n\nvoid rt_block(U16 timeout, U8 block_state) {\n    /* Block running task and choose next ready task.                         */\n    /* \"timeout\" sets a time-out value or is 0xffff (=no time-out).           */\n    /* \"block_state\" defines the appropriate task state */\n    P_TCB next_TCB;\n\n    if (timeout) {\n        if (timeout < 0xFFFFU) {\n            rt_put_dly(os_tsk.run, timeout);\n        }\n        os_tsk.run->state = block_state;\n        next_TCB = rt_get_first(&os_rdy);\n        rt_switch_req(next_TCB);\n    }\n}\n\n\n/*--------------------------- rt_tsk_pass -----------------------------------*/\n\nvoid rt_tsk_pass(void) {\n    /* Allow tasks of same priority level to run cooperatively.*/\n    P_TCB p_new;\n\n    p_new = rt_get_same_rdy_prio();\n    if (p_new != NULL) {\n        rt_put_prio((P_XCB) &os_rdy, os_tsk.run);\n        os_tsk.run->state = READY;\n        rt_switch_req(p_new);\n    }\n}\n\n\n/*--------------------------- rt_tsk_self -----------------------------------*/\n\nOS_TID rt_tsk_self(void) {\n    /* Return own task identifier value. */\n    if (os_tsk.run == NULL) {\n        return (0U);\n    }\n    return ((OS_TID) os_tsk.run->task_id);\n}\n\n\n/*--------------------------- rt_tsk_prio -----------------------------------*/\n\nOS_RESULT rt_tsk_prio(OS_TID task_id, U8 new_prio) {\n    /* Change execution priority of a task to \"new_prio\". */\n    P_TCB p_task;\n\n    if (task_id == 0U) {\n        /* Change execution priority of calling task. */\n        os_tsk.run->prio = new_prio;\n        os_tsk.run->prio_base = new_prio;\n        run:\n        if (rt_rdy_prio() > new_prio) {\n            rt_put_prio(&os_rdy, os_tsk.run);\n            os_tsk.run->state = READY;\n            rt_dispatch(NULL);\n        }\n        return (OS_R_OK);\n    }\n\n    /* Find the task in the \"os_active_TCB\" array. */\n    if ((task_id > os_maxtaskrun) || (os_active_TCB[task_id - 1U] == NULL)) {\n        /* Task with \"task_id\" not found or not started. */\n        return (OS_R_NOK);\n    }\n    p_task = os_active_TCB[task_id - 1U];\n    p_task->prio = new_prio;\n    p_task->prio_base = new_prio;\n    if (p_task == os_tsk.run) {\n        goto run;\n    }\n    rt_resort_prio(p_task);\n    if (p_task->state == READY) {\n        /* Task enqueued in a ready list. */\n        p_task = rt_get_first(&os_rdy);\n        rt_dispatch(p_task);\n    }\n    return (OS_R_OK);\n}\n\n\n/*--------------------------- rt_tsk_create ---------------------------------*/\n\nOS_TID rt_tsk_create(FUNCP task, U32 prio_stksz, void *stk, void *argv) {\n    /* Start a new task declared with \"task\". */\n    P_TCB task_context;\n    U32 i;\n\n    /* Priority 0 is reserved for idle task! */\n    if ((prio_stksz & 0xFFU) == 0U) {\n        prio_stksz += 1U;\n    }\n    task_context = rt_alloc_box(mp_tcb);\n    if (task_context == NULL) {\n        return (0U);\n    }\n    /* If \"size != 0\" use a private user provided stack. */\n    task_context->stack = stk;\n    task_context->priv_stack = (U16) (prio_stksz >> 8);\n    /* Pass parameter 'argv' to 'rt_init_context' */\n    task_context->msg = argv;\n    /* For 'size == 0' system allocates the user stack from the memory pool. */\n    rt_init_context(task_context, (U8) (prio_stksz & 0xFFU), task);\n\n    /* Find a free entry in 'os_active_TCB' table. */\n    i = rt_get_TID();\n    if (i == 0U) {\n        return (0U);\n    }\n    os_active_TCB[i - 1U] = task_context;\n    task_context->task_id = (U8) i;\n    DBG_TASK_NOTIFY(task_context, __TRUE);\n    rt_dispatch(task_context);\n    return ((OS_TID) i);\n}\n\n\n/*--------------------------- rt_tsk_delete ---------------------------------*/\n\nOS_RESULT rt_tsk_delete(OS_TID task_id) {\n    /* Terminate the task identified with \"task_id\". */\n    P_TCB task_context;\n    P_TCB p_TCB;\n    P_MUCB p_MCB, p_MCB0;\n\n    if ((task_id == 0U) || (task_id == os_tsk.run->task_id)) {\n        /* Terminate itself. */\n        os_tsk.run->state = INACTIVE;\n        os_tsk.run->tsk_stack = rt_get_PSP();\n        rt_stk_check();\n        p_MCB = os_tsk.run->p_mlnk;\n        while (p_MCB) {\n            /* Release mutexes owned by this task */\n            if (p_MCB->p_lnk) {\n                /* A task is waiting for mutex. */\n                p_TCB = rt_get_first((P_XCB) p_MCB);\n#ifdef __CMSIS_RTOS\n                rt_ret_val (p_TCB, 0U/*osOK*/);\n#else\n                rt_ret_val(p_TCB, OS_R_MUT);\n#endif\n                rt_rmv_dly(p_TCB);\n                p_TCB->state = READY;\n                rt_put_prio(&os_rdy, p_TCB);\n                /* A waiting task becomes the owner of this mutex. */\n                p_MCB0 = p_MCB->p_mlnk;\n                p_MCB->level = 1U;\n                p_MCB->owner = p_TCB;\n                p_MCB->p_mlnk = p_TCB->p_mlnk;\n                p_TCB->p_mlnk = p_MCB;\n                p_MCB = p_MCB0;\n            } else {\n                p_MCB0 = p_MCB->p_mlnk;\n                p_MCB->level = 0U;\n                p_MCB->owner = NULL;\n                p_MCB->p_mlnk = NULL;\n                p_MCB = p_MCB0;\n            }\n        }\n        os_active_TCB[os_tsk.run->task_id - 1U] = NULL;\n        rt_free_box(mp_stk, os_tsk.run->stack);\n        os_tsk.run->stack = NULL;\n        DBG_TASK_NOTIFY(os_tsk.run, __FALSE);\n        rt_free_box(mp_tcb, os_tsk.run);\n        os_tsk.run = NULL;\n        rt_dispatch(NULL);\n        /* The program should never come to this point. */\n    } else {\n        /* Find the task in the \"os_active_TCB\" array. */\n        if ((task_id > os_maxtaskrun) || (os_active_TCB[task_id - 1U] == NULL)) {\n            /* Task with \"task_id\" not found or not started. */\n            return (OS_R_NOK);\n        }\n        task_context = os_active_TCB[task_id - 1U];\n        rt_rmv_list(task_context);\n        rt_rmv_dly(task_context);\n        p_MCB = task_context->p_mlnk;\n        while (p_MCB) {\n            /* Release mutexes owned by this task */\n            if (p_MCB->p_lnk) {\n                /* A task is waiting for mutex. */\n                p_TCB = rt_get_first((P_XCB) p_MCB);\n#ifdef __CMSIS_RTOS\n                rt_ret_val (p_TCB, 0U/*osOK*/);\n#else\n                rt_ret_val(p_TCB, OS_R_MUT);\n#endif\n                rt_rmv_dly(p_TCB);\n                p_TCB->state = READY;\n                rt_put_prio(&os_rdy, p_TCB);\n                /* A waiting task becomes the owner of this mutex. */\n                p_MCB0 = p_MCB->p_mlnk;\n                p_MCB->level = 1U;\n                p_MCB->owner = p_TCB;\n                p_MCB->p_mlnk = p_TCB->p_mlnk;\n                p_TCB->p_mlnk = p_MCB;\n                p_MCB = p_MCB0;\n            } else {\n                p_MCB0 = p_MCB->p_mlnk;\n                p_MCB->level = 0U;\n                p_MCB->owner = NULL;\n                p_MCB->p_mlnk = NULL;\n                p_MCB = p_MCB0;\n            }\n        }\n        os_active_TCB[task_id - 1U] = NULL;\n        rt_free_box(mp_stk, task_context->stack);\n        task_context->stack = NULL;\n        DBG_TASK_NOTIFY(task_context, __FALSE);\n        rt_free_box(mp_tcb, task_context);\n        if (rt_rdy_prio() > os_tsk.run->prio) {\n            /* Ready task has higher priority than running task. */\n            os_tsk.run->state = READY;\n            rt_put_prio(&os_rdy, os_tsk.run);\n            rt_dispatch(NULL);\n        }\n    }\n    return (OS_R_OK);\n}\n\n\n/*--------------------------- rt_sys_init -----------------------------------*/\n\n#ifdef __CMSIS_RTOS\nvoid rt_sys_init (void) {\n#else\n\nvoid rt_sys_init(FUNCP first_task, U32 prio_stksz, void *stk) {\n#endif\n    /* Initialize system and start up task declared with \"first_task\". */\n    U32 i;\n\n    DBG_INIT();\n\n    /* Initialize dynamic memory and task TCB pointers to NULL. */\n    for (i = 0U; i < os_maxtaskrun; i++) {\n        os_active_TCB[i] = NULL;\n    }\n    rt_init_box(mp_tcb, (U32) mp_tcb_size, sizeof(struct OS_TCB));\n    rt_init_box(mp_stk, mp_stk_size, BOX_ALIGN_8 | (U16) (os_stackinfo));\n    rt_init_box((U32 *) m_tmr, (U32) mp_tmr_size, sizeof(struct OS_TMR));\n\n    /* Set up TCB of idle demon */\n    os_idle_TCB.task_id = 255U;\n    os_idle_TCB.priv_stack = 0U;\n    rt_init_context(&os_idle_TCB, 0U, os_idle_demon);\n\n    /* Set up ready list: initially empty */\n    os_rdy.cb_type = HCB;\n    os_rdy.p_lnk = NULL;\n    /* Set up delay list: initially empty */\n    os_dly.cb_type = HCB;\n    os_dly.p_dlnk = NULL;\n    os_dly.p_blnk = NULL;\n    os_dly.delta_time = 0U;\n\n    /* Fix SP and system variables to assume idle task is running */\n    /* Transform main program into idle task by assuming idle TCB */\n#ifndef __CMSIS_RTOS\n    rt_set_PSP(os_idle_TCB.tsk_stack + 32U);\n#endif\n    os_tsk.run = &os_idle_TCB;\n    os_tsk.run->state = RUNNING;\n\n    /* Initialize ps queue */\n    os_psq->first = 0U;\n    os_psq->last = 0U;\n    os_psq->size = os_fifo_size;\n\n    rt_init_robin();\n\n#ifndef __CMSIS_RTOS\n    /* Initialize SVC and PendSV */\n    rt_svc_init();\n\n    /* Initialize and start system clock timer */\n    os_tick_irqn = os_tick_init();\n    if (os_tick_irqn >= 0) {\n        OS_X_INIT((U32) os_tick_irqn);\n    }\n\n    /* Start up first user task before entering the endless loop */\n    rt_tsk_create(first_task, prio_stksz, stk, NULL);\n#endif\n}\n\n\n/*--------------------------- rt_sys_start ----------------------------------*/\n\n#ifdef __CMSIS_RTOS\nvoid rt_sys_start (void) {\n  /* Start system */\n\n  /* Initialize SVC and PendSV */\n  rt_svc_init ();\n\n  /* Initialize and start system clock timer */\n  os_tick_irqn = os_tick_init ();\n  if (os_tick_irqn >= 0) {\n    OS_X_INIT((U32)os_tick_irqn);\n  }\n}\n#endif\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Task.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_TASK.H\n *      Purpose: Task functions and system start up.\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Definitions */\n\n/* Values for 'state'   */\n#define INACTIVE        0U\n#define READY           1U\n#define RUNNING         2U\n#define WAIT_DLY        3U\n#define WAIT_ITV        4U\n#define WAIT_OR         5U\n#define WAIT_AND        6U\n#define WAIT_SEM        7U\n#define WAIT_MBX        8U\n#define WAIT_MUT        9U\n\n/* Return codes */\n#define OS_R_TMO        0x01U\n#define OS_R_EVT        0x02U\n#define OS_R_SEM        0x03U\n#define OS_R_MBX        0x04U\n#define OS_R_MUT        0x05U\n\n#define OS_R_OK         0x00U\n#define OS_R_NOK        0xFFU\n\n/* Variables */\nextern struct OS_TSK os_tsk;\nextern struct OS_TCB os_idle_TCB;\n\n/* Functions */\nextern void      rt_switch_req (P_TCB p_next);\nextern void      rt_dispatch   (P_TCB next_TCB);\nextern void      rt_block      (U16 timeout, U8 block_state);\nextern void      rt_tsk_pass   (void);\nextern OS_TID    rt_tsk_self   (void);\nextern OS_RESULT rt_tsk_prio   (OS_TID task_id, U8 new_prio);\nextern OS_TID    rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv);\nextern OS_RESULT rt_tsk_delete (OS_TID task_id);\n#ifdef __CMSIS_RTOS\nextern void      rt_sys_init   (void);\nextern void      rt_sys_start  (void);\n#else\nextern void      rt_sys_init   (FUNCP first_task, U32 prio_stksz, void *stk);\n#endif\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Time.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_TIME.C\n *      Purpose: Delay and interval wait functions\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_Task.h\"\n#include \"rt_Time.h\"\n\n/*----------------------------------------------------------------------------\n *      Global Variables\n *---------------------------------------------------------------------------*/\n\n/* Free running system tick counter */\nU32 os_time;\n\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n\n/*--------------------------- rt_time_get -----------------------------------*/\n\nU32 rt_time_get(void) {\n    /* Get system time tick */\n    return (os_time);\n}\n\n\n/*--------------------------- rt_dly_wait -----------------------------------*/\n\nvoid rt_dly_wait(U16 delay_time) {\n    /* Delay task by \"delay_time\" */\n    rt_block(delay_time, WAIT_DLY);\n}\n\n\n/*--------------------------- rt_itv_set ------------------------------------*/\n\nvoid rt_itv_set(U16 interval_time) {\n    /* Set interval length and define start of first interval */\n    os_tsk.run->interval_time = interval_time;\n    os_tsk.run->delta_time = interval_time + (U16) os_time;\n}\n\n\n/*--------------------------- rt_itv_wait -----------------------------------*/\n\nvoid rt_itv_wait(void) {\n    /* Wait for interval end and define start of next one */\n    U16 delta;\n\n    delta = os_tsk.run->delta_time - (U16) os_time;\n    os_tsk.run->delta_time += os_tsk.run->interval_time;\n    if ((delta & 0x8000U) == 0U) {\n        rt_block(delta, WAIT_ITV);\n    }\n}\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Time.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_TIME.H\n *      Purpose: Delay and interval wait functions definitions\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Variables */\nextern U32 os_time;\n\n/* Functions */\nextern U32  rt_time_get (void);\nextern void rt_dly_wait (U16 delay_time);\nextern void rt_itv_set  (U16 interval_time);\nextern void rt_itv_wait (void);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Timer.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_TIMER.C\n *      Purpose: User timer functions\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"rt_TypeDef.h\"\n#include \"RTX_Config.h\"\n#include \"rt_Timer.h\"\n#include \"rt_MemBox.h\"\n\n#ifndef __CMSIS_RTOS\n\n\n/*----------------------------------------------------------------------------\n *      Global Variables\n *---------------------------------------------------------------------------*/\n\n/* User Timer list pointer */\nstruct OS_XTMR os_tmr;\n\n/*----------------------------------------------------------------------------\n *      Functions\n *---------------------------------------------------------------------------*/\n\n/*--------------------------- rt_tmr_tick -----------------------------------*/\n\nvoid rt_tmr_tick(void) {\n    /* Decrement delta count of timer list head. Timers having the value of   */\n    /* zero are removed from the list and the callback function is called.    */\n    P_TMR p;\n\n    if (os_tmr.next == NULL) {\n        return;\n    }\n    os_tmr.tcnt--;\n    while ((os_tmr.tcnt == 0U) && ((p = os_tmr.next) != NULL)) {\n        /* Call a user provided function to handle an elapsed timer */\n        os_tmr_call(p->info);\n        os_tmr.tcnt = p->tcnt;\n        os_tmr.next = p->next;\n        rt_free_box((U32 *) m_tmr, p);\n    }\n}\n\n/*--------------------------- rt_tmr_create ---------------------------------*/\n\nOS_ID rt_tmr_create(U16 tcnt, U16 info) {\n    /* Create an user timer and put it into the chained timer list using      */\n    /* a timeout count value of \"tcnt\". User parameter \"info\" is used as a    */\n    /* parameter for the user provided callback function \"os_tmr_call ()\".    */\n    P_TMR p_tmr, p;\n    U32 delta, itcnt = tcnt;\n\n    if ((tcnt == 0U) || (m_tmr == NULL)) {\n        return (NULL);\n    }\n    p_tmr = rt_alloc_box((U32 *) m_tmr);\n    if (!p_tmr) {\n        return (NULL);\n    }\n    p_tmr->info = info;\n    p = (P_TMR) &os_tmr;\n    delta = p->tcnt;\n    while ((delta < itcnt) && (p->next != NULL)) {\n        p = p->next;\n        delta += p->tcnt;\n    }\n    /* Right place found, insert timer into the list */\n    p_tmr->next = p->next;\n    p_tmr->tcnt = (U16) (delta - itcnt);\n    p->next = p_tmr;\n    p->tcnt -= p_tmr->tcnt;\n    return (p_tmr);\n}\n\n/*--------------------------- rt_tmr_kill -----------------------------------*/\n\nOS_ID rt_tmr_kill(OS_ID timer) {\n    /* Remove user timer from the chained timer list. */\n    P_TMR p, p_tmr;\n\n    p_tmr = (P_TMR) timer;\n    p = (P_TMR) &os_tmr;\n    /* Search timer list for requested timer */\n    while (p->next != p_tmr) {\n        if (p->next == NULL) {\n            /* Failed, \"timer\" is not in the timer list */\n            return (p_tmr);\n        }\n        p = p->next;\n    }\n    /* Timer was found, remove it from the list */\n    p->next = p_tmr->next;\n    p->tcnt += p_tmr->tcnt;\n    rt_free_box((U32 *) m_tmr, p_tmr);\n    /* Timer killed */\n    return (NULL);\n}\n\n\n#endif\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_Timer.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_TIMER.H\n *      Purpose: User timer functions\n *      Rev.:    V4.70\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Variables */\nextern struct OS_XTMR os_tmr;\n\n/* Functions */\nextern void  rt_tmr_tick   (void);\nextern OS_ID rt_tmr_create (U16 tcnt, U16 info);\nextern OS_ID rt_tmr_kill   (OS_ID timer);\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/SRC/rt_TypeDef.h",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RT_TYPEDEF.H\n *      Purpose: Type Definitions\n *      Rev.:    V4.79\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2017 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n/* Types */\ntypedef char               S8;\ntypedef unsigned char      U8;\ntypedef short              S16;\ntypedef unsigned short     U16;\ntypedef int                S32;\ntypedef unsigned int       U32;\ntypedef long long          S64;\ntypedef unsigned long long U64;\ntypedef unsigned char      BIT;\ntypedef unsigned int       BOOL;\ntypedef void               (*FUNCP)(void);\n\ntypedef U32     OS_TID;\ntypedef void    *OS_ID;\ntypedef U32     OS_RESULT;\n\ntypedef struct OS_TCB {\n  /* General part: identical for all implementations.                        */\n  U8     cb_type;                 /* Control Block Type                      */\n  U8     state;                   /* Task state                              */\n  U8     prio;                    /* Execution priority                      */\n  U8     task_id;                 /* Task ID value for optimized TCB access  */\n  struct OS_TCB *p_lnk;           /* Link pointer for ready/sem. wait list   */\n  struct OS_TCB *p_rlnk;          /* Link pointer for sem./mbx lst backwards */\n  struct OS_TCB *p_dlnk;          /* Link pointer for delay list             */\n  struct OS_TCB *p_blnk;          /* Link pointer for delay list backwards   */\n  U16    delta_time;              /* Time until time out                     */\n  U16    interval_time;           /* Time interval for periodic waits        */\n  U16    events;                  /* Event flags                             */\n  U16    waits;                   /* Wait flags                              */\n  void   **msg;                   /* Direct message passing when task waits  */\n  struct OS_MUCB *p_mlnk;         /* Link pointer for mutex owner list       */\n  U8     prio_base;               /* Base priority                           */\n\n  /* Hardware dependant part: specific for CM processor                      */\n  U8     stack_frame;             /* Stack frame: 0=Basic, 1=Extended,       */\n                                  /* (2=VFP/D16 stacked, 4=NEON/D32 stacked) */\n  U16    priv_stack;              /* Private stack size, 0= system assigned  */\n  U32    tsk_stack;               /* Current task Stack pointer (R13)        */\n  U32    *stack;                  /* Pointer to Task Stack memory block      */\n\n  /* Task entry point used for uVision debugger                              */\n  FUNCP  ptask;                   /* Task entry address                      */\n} *P_TCB;\n#define TCB_STACKF      37        /* 'stack_frame' offset                    */\n#define TCB_TSTACK      40        /* 'tsk_stack' offset                      */\n\ntypedef struct OS_PSFE {          /* Post Service Fifo Entry                 */\n  void  *id;                      /* Object Identification                   */\n  U32    arg;                     /* Object Argument                         */\n} *P_PSFE;\n\ntypedef struct OS_PSQ {           /* Post Service Queue                      */\n  U8     first;                   /* FIFO Head Index                         */\n  U8     last;                    /* FIFO Tail Index                         */\n  U8     count;                   /* Number of stored items in FIFO          */\n  U8     size;                    /* FIFO Size                               */\n  struct OS_PSFE q[1];            /* FIFO Content                            */\n} *P_PSQ;\n\ntypedef struct OS_TSK {\n  P_TCB  run;                     /* Current running task                    */\n  P_TCB  next;                    /* Scheduled task to run                   */\n} *P_TSK;\n\ntypedef struct OS_ROBIN {         /* Round Robin Control                     */\n  P_TCB  task;                    /* Round Robin task                        */\n  U16    time;                    /* Round Robin switch time                 */\n  U16    tout;                    /* Round Robin timeout                     */\n} *P_ROBIN;\n\ntypedef struct OS_XCB {\n  U8     cb_type;                 /* Control Block Type                      */\n  struct OS_TCB *p_lnk;           /* Link pointer for ready/sem. wait list   */\n  struct OS_TCB *p_rlnk;          /* Link pointer for sem./mbx lst backwards */\n  struct OS_TCB *p_dlnk;          /* Link pointer for delay list             */\n  struct OS_TCB *p_blnk;          /* Link pointer for delay list backwards   */\n  U16    delta_time;              /* Time until time out                     */\n} *P_XCB;\n\ntypedef struct OS_MCB {\n  U8     cb_type;                 /* Control Block Type                      */\n  U8     state;                   /* State flag variable                     */\n  U8     isr_st;                  /* State flag variable for isr functions   */\n  struct OS_TCB *p_lnk;           /* Chain of tasks waiting for message      */\n  U16    first;                   /* Index of the message list begin         */\n  U16    last;                    /* Index of the message list end           */\n  U16    count;                   /* Actual number of stored messages        */\n  U16    size;                    /* Maximum number of stored messages       */\n  void   *msg[1];                 /* FIFO for Message pointers 1st element   */\n} *P_MCB;\n\ntypedef struct OS_SCB {\n  U8     cb_type;                 /* Control Block Type                      */\n  U8     mask;                    /* Semaphore token mask                    */\n  U16    tokens;                  /* Semaphore tokens                        */\n  struct OS_TCB *p_lnk;           /* Chain of tasks waiting for tokens       */\n} *P_SCB;\n\ntypedef struct OS_MUCB {\n  U8     cb_type;                 /* Control Block Type                      */\n  U16    level;                   /* Call nesting level                      */\n  struct OS_TCB *p_lnk;           /* Chain of tasks waiting for mutex        */\n  struct OS_TCB *owner;           /* Mutex owner task                        */\n  struct OS_MUCB *p_mlnk;         /* Chain of mutexes by owner task          */\n} *P_MUCB;\n\ntypedef struct OS_XTMR {\n  struct OS_TMR  *next;\n  U16    tcnt;\n} *P_XTMR;\n\ntypedef struct OS_TMR {\n  struct OS_TMR  *next;           /* Link pointer to Next timer              */\n  U16    tcnt;                    /* Timer delay count                       */\n  U16    info;                    /* User defined call info                  */\n} *P_TMR;\n\ntypedef struct OS_BM {\n  void *free;                     /* Pointer to first free memory block      */\n  void *end;                      /* Pointer to memory block end             */\n  U32  blk_size;                  /* Memory block size                       */\n} *P_BM;\n\n/* Definitions */\n#define __TRUE          1U\n#define __FALSE         0U\n#define NULL            ((void *) 0)\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c",
    "content": "/*----------------------------------------------------------------------------\n *      CMSIS-RTOS  -  RTX\n *----------------------------------------------------------------------------\n *      Name:    RTX_Conf_CM.C\n *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M\n *      Rev.:    V4.70.1\n *----------------------------------------------------------------------------\n *\n * Copyright (c) 1999-2009 KEIL, 2009-2016 ARM Germany GmbH. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n\n#include \"cmsis_os.h\"\n\n\n/*----------------------------------------------------------------------------\n *      RTX User configuration part BEGIN\n *---------------------------------------------------------------------------*/\n\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n//\n// <h>Thread Configuration\n// =======================\n//\n//   <o>Number of concurrent running user threads <1-250>\n//   <i> Defines max. number of user threads that will run at the same time.\n//   <i> Default: 6\n#ifndef OS_TASKCNT\n#define OS_TASKCNT     6\n#endif\n\n//   <o>Default Thread stack size [bytes] <64-4096:8><#/4>\n//   <i> Defines default stack size for threads with osThreadDef stacksz = 0\n//   <i> Default: 200\n#ifndef OS_STKSIZE\n#define OS_STKSIZE     50      // this stack size value is in words\n#endif\n\n//   <o>Main Thread stack size [bytes] <64-32768:8><#/4>\n//   <i> Defines stack size for main thread.\n//   <i> Default: 200\n#ifndef OS_MAINSTKSIZE\n#define OS_MAINSTKSIZE 50      // this stack size value is in words\n#endif\n\n//   <o>Number of threads with user-provided stack size <0-250>\n//   <i> Defines the number of threads with user-provided stack size.\n//   <i> Default: 0\n#ifndef OS_PRIVCNT\n#define OS_PRIVCNT     0\n#endif\n\n//   <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>\n//   <i> Defines the combined stack size for threads with user-provided stack size.\n//   <i> Default: 0\n#ifndef OS_PRIVSTKSIZE\n#define OS_PRIVSTKSIZE 0       // this stack size value is in words\n#endif\n\n//   <q>Stack overflow checking\n//   <i> Enable stack overflow checks at thread switch.\n//   <i> Enabling this option increases slightly the execution time of a thread switch.\n#ifndef OS_STKCHECK\n#define OS_STKCHECK    1\n#endif\n\n//   <q>Stack usage watermark\n//   <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.\n//   <i> Enabling this option increases significantly the execution time of osThreadCreate.\n#ifndef OS_STKINIT\n#define OS_STKINIT      0\n#endif\n\n//   <o>Processor mode for thread execution \n//     <0=> Unprivileged mode \n//     <1=> Privileged mode\n//   <i> Default: Privileged mode\n#ifndef OS_RUNPRIV\n#define OS_RUNPRIV     1\n#endif\n\n// </h>\n\n// <h>RTX Kernel Timer Tick Configuration\n// ======================================\n//   <q> Use Cortex-M SysTick timer as RTX Kernel Timer\n//   <i> Cortex-M processors provide in most cases a SysTick timer that can be used as \n//   <i> as time-base for RTX.\n#ifndef OS_SYSTICK\n#define OS_SYSTICK     1\n#endif\n//\n//   <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>\n//   <i> Defines the input frequency of the RTOS Kernel Timer.  \n//   <i> When the Cortex-M SysTick timer is used, the input clock \n//   <i> is on most systems identical with the core clock.\n#ifndef OS_CLOCK\n#define OS_CLOCK       12000000\n#endif\n\n//   <o>RTX Timer tick interval value [us] <1-1000000>\n//   <i> The RTX Timer tick interval value is used to calculate timeout values.\n//   <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.\n//   <i> Default: 1000  (1ms)\n#ifndef OS_TICK\n#define OS_TICK        1000\n#endif\n\n// </h>\n\n// <h>System Configuration\n// =======================\n//\n// <e>Round-Robin Thread switching\n// ===============================\n//\n// <i> Enables Round-Robin Thread switching.\n#ifndef OS_ROBIN\n#define OS_ROBIN       1\n#endif\n\n//   <o>Round-Robin Timeout [ticks] <1-1000>\n//   <i> Defines how long a thread will execute before a thread switch.\n//   <i> Default: 5\n#ifndef OS_ROBINTOUT\n#define OS_ROBINTOUT   5\n#endif\n\n// </e>\n\n// <e>User Timers\n// ==============\n//   <i> Enables user Timers\n#ifndef OS_TIMERS\n#define OS_TIMERS      1\n#endif\n\n//   <o>Timer Thread Priority\n//                        <1=> Low\n//     <2=> Below Normal  <3=> Normal  <4=> Above Normal\n//                        <5=> High\n//                        <6=> Realtime (highest)\n//   <i> Defines priority for Timer Thread\n//   <i> Default: High\n#ifndef OS_TIMERPRIO\n#define OS_TIMERPRIO   5\n#endif\n\n//   <o>Timer Thread stack size [bytes] <64-4096:8><#/4>\n//   <i> Defines stack size for Timer thread.\n//   <i> Default: 200\n#ifndef OS_TIMERSTKSZ\n#define OS_TIMERSTKSZ  50     // this stack size value is in words\n#endif\n\n//   <o>Timer Callback Queue size <1-32>\n//   <i> Number of concurrent active timer callback functions.\n//   <i> Default: 4\n#ifndef OS_TIMERCBQS\n#define OS_TIMERCBQS   4\n#endif\n\n// </e>\n\n//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries\n//                         <12=> 12 entries  <16=> 16 entries\n//                         <24=> 24 entries  <32=> 32 entries\n//                         <48=> 48 entries  <64=> 64 entries\n//                         <96=> 96 entries\n//   <i> ISR functions store requests to this buffer,\n//   <i> when they are called from the interrupt handler.\n//   <i> Default: 16 entries\n#ifndef OS_FIFOSZ\n#define OS_FIFOSZ      16\n#endif\n\n// </h>\n\n//------------- <<< end of configuration section >>> -----------------------\n\n// Standard library system mutexes\n// ===============================\n//  Define max. number system mutexes that are used to protect \n//  the arm standard runtime library. For microlib they are not used.\n#ifndef OS_MUTEXCNT\n#define OS_MUTEXCNT    8\n#endif\n\n/*----------------------------------------------------------------------------\n *      RTX User configuration part END\n *---------------------------------------------------------------------------*/\n\n#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)\n\n\n/*----------------------------------------------------------------------------\n *      Global Functions\n *---------------------------------------------------------------------------*/\n\n/*--------------------------- os_idle_demon ---------------------------------*/\n\n/// \\brief The idle demon is running when no other thread is ready to run\nvoid os_idle_demon(void) {\n\n    for (;;) {\n        /* HERE: include optional user code to be executed when no thread runs.*/\n    }\n}\n\n#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer\n\n/*--------------------------- os_tick_init ----------------------------------*/\n \n/// \\brief Initializes an alternative hardware timer as RTX kernel timer\n/// \\return                             IRQ number of the alternative hardware timer\nint os_tick_init (void) {\n  return (-1);  /* Return IRQ number of timer (0..239) */\n}\n \n/*--------------------------- os_tick_val -----------------------------------*/\n \n/// \\brief Get alternative hardware timer's current value (0 .. OS_TRV)\n/// \\return                             Current value of the alternative hardware timer\nuint32_t os_tick_val (void) {\n  return (0);\n}\n \n/*--------------------------- os_tick_ovf -----------------------------------*/\n \n/// \\brief Get alternative hardware timer's  overflow flag\n/// \\return                             Overflow flag\\n\n///                                     - 1 : overflow\n///                                     - 0 : no overflow\nuint32_t os_tick_ovf (void) {\n  return (0);\n}\n \n/*--------------------------- os_tick_irqack --------------------------------*/\n \n/// \\brief Acknowledge alternative hardware timer interrupt\nvoid os_tick_irqack (void) {\n  /* ... */\n}\n\n#endif   // (OS_SYSTICK == 0)\n\n/*--------------------------- os_error --------------------------------------*/\n\n/* OS Error Codes */\n#define OS_ERROR_STACK_OVF      1\n#define OS_ERROR_FIFO_OVF       2\n#define OS_ERROR_MBX_OVF        3\n#define OS_ERROR_TIMER_OVF      4\n\nextern osThreadId svcThreadGetId(void);\n\n/// \\brief Called when a runtime error is detected\n/// \\param[in]   error_code   actual error code that has been detected\nvoid os_error(uint32_t error_code) {\n\n    /* HERE: include optional code to be executed on runtime error. */\n    switch (error_code) {\n        case OS_ERROR_STACK_OVF:\n            /* Stack overflow detected for the currently running task. */\n            /* Thread can be identified by calling svcThreadGetId().   */\n            break;\n        case OS_ERROR_FIFO_OVF:\n            /* ISR FIFO Queue buffer overflow detected. */\n            break;\n        case OS_ERROR_MBX_OVF:\n            /* Mailbox overflow detected. */\n            break;\n        case OS_ERROR_TIMER_OVF:\n            /* User Timer Callback Queue overflow detected. */\n            break;\n        default:\n            break;\n    }\n    for (;;);\n}\n\n\n/*----------------------------------------------------------------------------\n *      RTX Configuration Functions\n *---------------------------------------------------------------------------*/\n\n#include \"RTX_CM_lib.h\"\n\n/*----------------------------------------------------------------------------\n * end of file\n *---------------------------------------------------------------------------*/\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c",
    "content": "\n#include \"cmsis_os.h\"                                           // CMSIS RTOS header file\n\n/*----------------------------------------------------------------------------\n *      Mail Queue creation & usage\n *---------------------------------------------------------------------------*/\n\nvoid Thread_MailQueue1(void const *argument);                  // thread function 1\nvoid Thread_MailQueue2(void const *argument);                  // thread function 2\nosThreadId tid_Thread_MailQueue1;                               // thread id 1\nosThreadId tid_Thread_MailQueue2;                               // thread id 2\nosThreadDef (Thread_MailQueue1, osPriorityNormal, 1, 0);        // thread object 1\nosThreadDef (Thread_MailQueue2, osPriorityNormal, 1, 0);        // thread object 2\n\n#define MAILQUEUE_OBJECTS      16                               // number of Message Queue Objects\ntypedef struct {                                                // object data type\n    uint8_t Buf[32];\n    uint8_t Idx;\n} MAILQUEUE_OBJ_t;\n\nosMailQId qid_MailQueue;                                        // mail queue id\nosMailQDef (MailQueue, MAILQUEUE_OBJECTS, MAILQUEUE_OBJ_t);     // mail queue object\n\n\nint Init_MailQueue(void) {\n\n    qid_MailQueue = osMailCreate(osMailQ(MailQueue), NULL);      // create mail queue\n    if (!qid_MailQueue) { ; // Mail Queue object not created, handle failure\n    }\n\n    tid_Thread_MailQueue1 = osThreadCreate(osThread(Thread_MailQueue1), NULL);\n    if (!tid_Thread_MailQueue1) return (-1);\n    tid_Thread_MailQueue2 = osThreadCreate(osThread(Thread_MailQueue2), NULL);\n    if (!tid_Thread_MailQueue2) return (-1);\n\n    return (0);\n}\n\nvoid Thread_MailQueue1(void const *argument) {\n    MAILQUEUE_OBJ_t *pMail = 0;\n\n    while (1) { ; // Insert thread code here...\n        pMail = osMailAlloc(qid_MailQueue, osWaitForever);         // Allocate memory\n        if (pMail) {\n            pMail->Buf[0] = 0xff;                                     // Set the mail content\n            pMail->Idx = 0;\n            osMailPut(qid_MailQueue, pMail);                         // Send Mail\n        }\n\n        osThreadYield();                                           // suspend thread\n    }\n}\n\nvoid Thread_MailQueue2(void const *argument) {\n    MAILQUEUE_OBJ_t *pMail = 0;\n    osEvent evt;\n\n    while (1) { ; // Insert thread code here...\n        evt = osMailGet(qid_MailQueue, osWaitForever);             // wait for mail\n        if (evt.status == osEventMail) {\n            pMail = evt.value.p;\n            if (pMail) { ; // process data\n                osMailFree(qid_MailQueue, pMail);                      // free memory allocated for mail\n            }\n        }\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c",
    "content": "\n#include \"cmsis_os.h\"                                           // CMSIS RTOS header file\n\n/*----------------------------------------------------------------------------\n *      Memory Pool creation & usage\n *---------------------------------------------------------------------------*/\n\n#define MEMPOOL_OBJECTS      16                                 // number of Memory Pool Objects\n\ntypedef struct {                                                // object data type\n    uint8_t Buf[32];\n    uint8_t Idx;\n} MEM_BLOCK_t;\n\nvoid Thread_MemPool(void const *argument);                     // thread function\nosThreadId tid_Thread_MemPool;                                  // thread id\nosThreadDef (Thread_MemPool, osPriorityNormal, 1, 0);           // thread object\n\nosPoolId mpid_MemPool;                                          // memory pool id\nosPoolDef (MemPool, MEMPOOL_OBJECTS, MEM_BLOCK_t);              // memory pool object\n\n\nint Init_MemPool(void) {\n\n    mpid_MemPool = osPoolCreate(osPool (MemPool));               // create Mem Pool\n    if (!mpid_MemPool) { ; // MemPool object not created, handle failure\n    }\n\n    tid_Thread_MemPool = osThreadCreate(osThread(Thread_MemPool), NULL);\n    if (!tid_Thread_MemPool) return (-1);\n\n    return (0);\n}\n\nvoid Thread_MemPool(void const *argument) {\n    osStatus status;\n    MEM_BLOCK_t *pMem = 0;\n\n    while (1) { ; // Insert thread code here...\n\n        pMem = (MEM_BLOCK_t *) osPoolCAlloc(mpid_MemPool);          // get Mem Block\n        if (pMem) {                                                 // Mem Block was available\n            pMem->Buf[0] = 0x55;                                      // do some work...\n            pMem->Idx = 0;\n\n            status = osPoolFree(mpid_MemPool, pMem);                 // free mem block\n            switch (status) {\n                case osOK:\n                    break;\n                case osErrorParameter:\n                    break;\n                case osErrorValue:\n                    break;\n                default:\n                    break;\n            }\n        }\n\n        osThreadYield();                                           // suspend thread\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c",
    "content": "\n#include \"cmsis_os.h\"                                           // CMSIS RTOS header file\n\n/*----------------------------------------------------------------------------\n *      Message Queue creation & usage\n *---------------------------------------------------------------------------*/\n\nvoid Thread_MsgQueue1(void const *argument);                   // thread function 1\nvoid Thread_MsgQueue2(void const *argument);                   // thread function 2\nosThreadId tid_Thread_MsgQueue1;                                // thread id 1\nosThreadId tid_Thread_MsgQueue2;                                // thread id 2\nosThreadDef (Thread_MsgQueue1, osPriorityNormal, 1, 0);         // thread object 1\nosThreadDef (Thread_MsgQueue2, osPriorityNormal, 1, 0);         // thread object 2\n\n#define MSGQUEUE_OBJECTS      16                                // number of Message Queue Objects\n\ntypedef struct {                                                // object data type\n    uint8_t Buf[32];\n    uint8_t Idx;\n} MEM_BLOCK_t;\n\ntypedef struct {                                                // object data type\n    uint8_t Buf[32];\n    uint8_t Idx;\n} MSGQUEUE_OBJ_t;\n\nosPoolId mpid_MemPool2;                                         // memory pool id\nosPoolDef (MemPool2, MSGQUEUE_OBJECTS, MEM_BLOCK_t);            // memory pool object\n\nosMessageQId mid_MsgQueue;                                      // message queue id\nosMessageQDef (MsgQueue, MSGQUEUE_OBJECTS, MSGQUEUE_OBJ_t);     // message queue object\n\n\nint Init_MsgQueue(void) {\n\n    mpid_MemPool2 = osPoolCreate(osPool (MemPool2));             // create Mem Pool\n    if (!mpid_MemPool2) { ; // MemPool object not created, handle failure\n    }\n\n    mid_MsgQueue = osMessageCreate(osMessageQ(MsgQueue), NULL);  // create msg queue\n    if (!mid_MsgQueue) { ; // Message Queue object not created, handle failure\n    }\n\n    tid_Thread_MsgQueue1 = osThreadCreate(osThread(Thread_MsgQueue1), NULL);\n    if (!tid_Thread_MsgQueue1) return (-1);\n    tid_Thread_MsgQueue2 = osThreadCreate(osThread(Thread_MsgQueue2), NULL);\n    if (!tid_Thread_MsgQueue2) return (-1);\n\n    return (0);\n}\n\nvoid Thread_MsgQueue1(void const *argument) {\n    MEM_BLOCK_t *pMsg = 0;\n\n    while (1) { ; // Insert thread code here...\n        pMsg = (MEM_BLOCK_t *) osPoolCAlloc(mpid_MemPool2);         // get Mem Block\n        if (pMsg) {                                                 // Mem Block was available\n            pMsg->Buf[0] = 0x55;                                      // do some work...\n            pMsg->Idx = 0;\n            osMessagePut(mid_MsgQueue, (uint32_t) pMsg, osWaitForever); // Send Message\n        }\n\n        osThreadYield();                                           // suspend thread\n    }\n}\n\nvoid Thread_MsgQueue2(void const *argument) {\n    osEvent evt;\n    MEM_BLOCK_t *pMsg = 0;\n\n    while (1) { ; // Insert thread code here...\n        evt = osMessageGet(mid_MsgQueue, osWaitForever);           // wait for message\n        if (evt.status == osEventMessage) {\n            pMsg = evt.value.p;\n            if (pMsg) { ; // process data\n                osPoolFree(mpid_MemPool2, pMsg);                       // free memory allocated for message\n            }\n        }\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c",
    "content": "\n#include \"cmsis_os.h\"                                           // CMSIS RTOS header file\n\n/*----------------------------------------------------------------------------\n *      Mutex creation & usage\n *---------------------------------------------------------------------------*/\n\nvoid Thread_Mutex(void const *argument);                       // thread function\nosThreadId tid_Thread_Mutex;                                    // thread id\nosThreadDef (Thread_Mutex, osPriorityNormal, 1, 0);             // thread object\n\nosMutexId mid_Thread_Mutex;                                     // mutex id\nosMutexDef (SampleMutex);                                       // mutex name definition\n\n\nint Init_Mutex(void) {\n\n    mid_Thread_Mutex = osMutexCreate(osMutex (SampleMutex));\n    if (!tid_Thread_Mutex) { ; // Mutex object not created, handle failure\n    }\n\n    tid_Thread_Mutex = osThreadCreate(osThread(Thread_Mutex), NULL);\n    if (!tid_Thread_Mutex) return (-1);\n\n    return (0);\n}\n\nvoid Thread_Mutex(void const *argument) {\n    osStatus status;\n\n    while (1) { ; // Insert thread code here...\n\n        status = osMutexWait(mid_Thread_Mutex, NULL);\n        switch (status) {\n            case osOK:; // Use protected code here...\n                osMutexRelease(mid_Thread_Mutex);\n                break;\n            case osErrorTimeoutResource:\n                break;\n            case osErrorResource:\n                break;\n            case osErrorParameter:\n                break;\n            case osErrorISR:\n                break;\n            default:\n                break;\n        }\n\n        osThreadYield();                                           // suspend thread\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c",
    "content": "\n#include \"cmsis_os.h\"                                           // CMSIS RTOS header file\n\n/*----------------------------------------------------------------------------\n *      Semaphore creation & usage\n *---------------------------------------------------------------------------*/\n\nvoid Thread_Semaphore(void const *argument);                   // thread function\nosThreadId tid_Thread_Semaphore;                                // thread id\nosThreadDef (Thread_Semaphore, osPriorityNormal, 1, 0);         // thread object\n\nosSemaphoreId sid_Thread_Semaphore;                             // semaphore id\nosSemaphoreDef (SampleSemaphore);                               // semaphore object\n\n\nint Init_Semaphore(void) {\n\n    sid_Thread_Semaphore = osSemaphoreCreate(osSemaphore(SampleSemaphore), 1);\n    if (!sid_Thread_Semaphore) { ; // Semaphore object not created, handle failure\n    }\n\n    tid_Thread_Semaphore = osThreadCreate(osThread(Thread_Semaphore), NULL);\n    if (!tid_Thread_Semaphore) return (-1);\n\n    return (0);\n}\n\nvoid Thread_Semaphore(void const *argument) {\n    int32_t val;\n\n    while (1) { ; // Insert thread code here...\n\n        val = osSemaphoreWait(sid_Thread_Semaphore, 10);           // wait 10 mSec\n        switch (val) {\n            case osOK:; // Use protected code here...\n                osSemaphoreRelease(sid_Thread_Semaphore);              // Return a token back to a semaphore\n                break;\n            case osErrorResource:\n                break;\n            case osErrorParameter:\n                break;\n            default:\n                break;\n        }\n\n        osThreadYield();                                           // suspend thread\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c",
    "content": "\n#include \"cmsis_os.h\"                                           // CMSIS RTOS header file\n\n/*----------------------------------------------------------------------------\n *      Thread 1 'Thread_Name': Sample thread\n *---------------------------------------------------------------------------*/\n\nvoid Thread(void const *argument);                             // thread function\nosThreadId tid_Thread;                                          // thread id\nosThreadDef (Thread, osPriorityNormal, 1, 0);                   // thread object\n\nint Init_Thread(void) {\n\n    tid_Thread = osThreadCreate(osThread(Thread), NULL);\n    if (!tid_Thread) return (-1);\n\n    return (0);\n}\n\nvoid Thread(void const *argument) {\n\n    while (1) { ; // Insert thread code here...\n        osThreadYield();                                           // suspend thread\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c",
    "content": "\n#include \"cmsis_os.h\"                                           // CMSIS RTOS header file\n\n/*----------------------------------------------------------------------------\n *      Timer: Sample timer functions\n *---------------------------------------------------------------------------*/\n\n\n/*----- One-Shoot Timer Example -----*/\nstatic void Timer1_Callback(void const *arg);                  // prototype for timer callback function\n\nstatic osTimerId id1;                                           // timer id\nstatic uint32_t exec1;                                         // argument for the timer call back function\nstatic osTimerDef (Timer1, Timer1_Callback);                    // define timers\n\n// One-Shoot Timer Function\nstatic void Timer1_Callback(void const *arg) {\n    // add user code here\n}\n\n\n/*----- Periodic Timer Example -----*/\nstatic void Timer2_Callback(void const *arg);                  // prototype for timer callback function\n\nstatic osTimerId id2;                                           // timer id\nstatic uint32_t exec2;                                         // argument for the timer call back function\nstatic osTimerDef (Timer2, Timer2_Callback);\n\n// Periodic Timer Example\nstatic void Timer2_Callback(void const *arg) {\n    // add user code here\n}\n\n\n// Example: Create and Start timers\nvoid Init_Timers(void) {\n    osStatus status;                                              // function return status\n\n    // Create one-shoot timer\n    exec1 = 1;\n    id1 = osTimerCreate(osTimer(Timer1), osTimerOnce, &exec1);\n    if (id1 != NULL) {    // One-shot timer created\n        // start timer with delay 100ms\n        status = osTimerStart(id1, 100);\n        if (status != osOK) {\n            // Timer could not be started\n        }\n    }\n\n    // Create periodic timer\n    exec2 = 2;\n    id2 = osTimerCreate(osTimer(Timer2), osTimerPeriodic, &exec2);\n    if (id2 != NULL) {    // Periodic timer created\n        // start timer with periodic 1000ms interval\n        status = osTimerStart(id2, 1000);\n        if (status != osOK) {\n            // Timer could not be started\n        }\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/UserCodeTemplates/main.c",
    "content": "/*----------------------------------------------------------------------------\n * CMSIS-RTOS 'main' function template\n *---------------------------------------------------------------------------*/\n\n#define osObjectsPublic                     // define objects in main module\n\n#include \"osObjects.h\"                      // RTOS object definitions\n\n\n/*\n * main: initialize and start the system\n */\nint main(void) {\n    osKernelInitialize();                    // initialize CMSIS-RTOS\n\n    // initialize peripherals here\n\n    // create 'thread' functions that start executing,\n    // example: tid_name = osThreadCreate (osThread(name), NULL);\n\n    osKernelStart();                         // start thread execution\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h",
    "content": "/*----------------------------------------------------------------------------\n * osObjects.h: CMSIS-RTOS global object definitions for an application\n *----------------------------------------------------------------------------\n *\n * This header file defines global RTOS objects used throughout a project\n *\n * #define osObjectsPublic indicates that objects are defined; without that\n * definition the objects are defined as external symbols.\n *\n *--------------------------------------------------------------------------*/\n\n\n#ifndef __osObjects\n#define __osObjects\n\n#if (!defined (osObjectsPublic))\n#define osObjectsExternal           // define RTOS objects with extern attribute\n#endif\n\n#include \"cmsis_os.h\"               // CMSIS RTOS header file\n\n\n// global 'thread' functions ---------------------------------------------------\n/* \nExample:\nextern void sample_name (void const *argument);         // thread function\n\nosThreadId tid_sample_name;                             // thread id\nosThreadDef (sample_name, osPriorityNormal, 1, 0);      // thread object\n*/\n\n\n// global 'semaphores' ----------------------------------------------------------\n/* \nExample:\nosSemaphoreId sid_sample_name;                          // semaphore id\nosSemaphoreDef (sample_name);                           // semaphore object\n*/\n\n\n// global 'memory pools' --------------------------------------------------------\n/* \nExample:\ntypedef struct sample_name type_sample_name;            // object data type\n\nosPoolId mpid_sample_name;                              // memory pool id\nosPoolDef (sample_name, 16, type_sample_name);          // memory pool object\n*/\n\n\n// global 'message queues' -------------------------------------------------------\n/* \nExample:\ntypedef struct sample_name type_sample_name;            // object data type\n\nosMessageQId mid_sample_name;                           // message queue id\nosMessageQDef (sample_name, 16, type_sample_name);      // message queue object\n*/\n\n\n// global 'mail queues' ----------------------------------------------------------\n/* \nExample:\ntypedef struct sample_name type_sample_name;            // object data type\n\nosMailQId qid_sample_name;                              // mail queue id\nosMailQDef (sample_name, 16, type_sample_name);         // mail queue object\n*/\n\n#endif  // __osObjects\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/Mail.h",
    "content": "/* Copyright (c) 2012 mbed.org */\n#ifndef MAIL_H\n#define MAIL_H \n\n#include <stdint.h>\n#include <string.h>\n\n#include \"cmsis_os.h\"\n\nnamespace rtos {\n\n/*! The Mail class allow to control, send, receive, or wait for mail.\n A mail is a memory block that is send to a thread or interrupt service routine.\n  \\tparam  T         data type of a single message element.\n  \\tparam  queue_sz  maximum number of messages in queue.\n*/\ntemplate<typename T, uint32_t queue_sz>\nclass Mail {\npublic:\n    /*! Create and Initialise Mail queue. */\n    Mail() {\n    #ifdef CMSIS_OS_RTX\n        memset(_mail_q, 0, sizeof(_mail_q));\n        _mail_p[0] = _mail_q;\n        \n        memset(_mail_m, 0, sizeof(_mail_m));\n        _mail_p[1] = _mail_m;\n        \n        _mail_def.pool = _mail_p;\n        _mail_def.queue_sz = queue_sz;\n        _mail_def.item_sz = sizeof(T);\n    #endif\n        _mail_id = osMailCreate(&_mail_def, NULL);\n    }\n    \n    /*! Allocate a memory block of type T\n      \\param   millisec  timeout value or 0 in case of no time-out. (default: 0).\n      \\return  pointer to memory block that can be filled with mail or NULL in case error.\n    */\n    T* alloc(uint32_t millisec=0) {\n        return (T*)osMailAlloc(_mail_id, millisec);\n    }\n    \n    /*! Allocate a memory block of type T and set memory block to zero. \n      \\param   millisec  timeout value or 0 in case of no time-out.  (default: 0).\n      \\return  pointer to memory block that can be filled with mail or NULL in case error.\n    */\n    T* calloc(uint32_t millisec=0) {\n        return (T*)osMailCAlloc(_mail_id, millisec);\n    }\n    \n    /*! Put a mail in the queue.\n      \\param   mptr  memory block previously allocated with Mail::alloc or Mail::calloc.\n      \\return  status code that indicates the execution status of the function. \n    */\n    osStatus put(T *mptr) {\n        return osMailPut(_mail_id, (void*)mptr);\n    }\n    \n    /*! Get a mail from a queue.\n      \\param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).\n      \\return  event that contains mail information or error code.\n    */\n    osEvent get(uint32_t millisec=osWaitForever) {\n        return osMailGet(_mail_id, millisec);\n    }\n    \n    /*! Free a memory block from a mail.\n      \\param   mptr  pointer to the memory block that was obtained with Mail::get. \n      \\return  status code that indicates the execution status of the function.\n    */\n    osStatus free(T *mptr) {\n        return osMailFree(_mail_id, (void*)mptr);\n    }\n\nprivate:\n    osMailQId    _mail_id;\n    osMailQDef_t _mail_def;\n#ifdef CMSIS_OS_RTX\n    uint32_t     _mail_q[4+(queue_sz)];\n    uint32_t     _mail_m[3+((sizeof(T)+3)/4)*(queue_sz)];\n    void        *_mail_p[2];\n#endif\n};\n\n}\n\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/MemoryPool.h",
    "content": "/* Copyright (c) 2012 mbed.org */\n#ifndef MEMORYPOOL_H\n#define MEMORYPOOL_H \n\n#include <stdint.h>\n#include <string.h>\n\n#include \"cmsis_os.h\"\n\nnamespace rtos {\n\n/*! Define and manage fixed-size memory pools of objects of a given type.\n  \\tparam  T         data type of a single object (element).\n  \\tparam  queue_sz  maximum number of objects (elements) in the memory pool.\n*/\ntemplate<typename T, uint32_t pool_sz>\nclass MemoryPool {\npublic:\n    /*! Create and Initialize a memory pool. */\n    MemoryPool() {\n    #ifdef CMSIS_OS_RTX\n        memset(_pool_m, 0, sizeof(_pool_m));\n        _pool_def.pool = _pool_m;\n        \n        _pool_def.pool_sz = pool_sz;\n        _pool_def.item_sz =  sizeof(T);\n    #endif\n        _pool_id = osPoolCreate(&_pool_def);\n    }\n    \n    /*! Allocate a memory block of type T from a memory pool.\n      \\return  address of the allocated memory block or NULL in case of no memory available.\n    */\n    T* alloc(void) {\n        return (T*)osPoolAlloc(_pool_id);\n    }\n    \n    /*! Allocate a memory block of type T from a memory pool and set memory block to zero.\n      \\return  address of the allocated memory block or NULL in case of no memory available. \n    */\n    T* calloc(void) {\n        return (T*)osPoolCAlloc(_pool_id);\n    }\n    \n    /*! Return an allocated memory block back to a specific memory pool.\n      \\param   address of the allocated memory block that is returned to the memory pool.\n      \\return  status code that indicates the execution status of the function. \n    */\n    osStatus free(T *block) {\n        return osPoolFree(_pool_id, (void*)block);\n    }\n\nprivate:\n    osPoolId    _pool_id;\n    osPoolDef_t _pool_def;\n#ifdef CMSIS_OS_RTX\n    uint32_t    _pool_m[3+((sizeof(T)+3)/4)*(pool_sz)];\n#endif\n};\n\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/Mutex.cpp",
    "content": "#include \"Mutex.h\"\n\n#include <string.h>\n//#include \"error.h\"\n\nnamespace rtos {\n\nMutex::Mutex() {\n#ifdef CMSIS_OS_RTX\n    memset(_mutex_data, 0, sizeof(_mutex_data));\n    _osMutexDef.mutex = _mutex_data;\n#endif\n    _osMutexId = osMutexCreate(&_osMutexDef);\n    if (_osMutexId == NULL) {\n//        error(\"Error initializing the mutex object\\n\");\n    }\n}\n\nosStatus Mutex::lock(uint32_t millisec) {\n    return osMutexWait(_osMutexId, millisec);\n}\n\nbool Mutex::trylock() {\n    return (osMutexWait(_osMutexId, 0) == osOK);\n}\n\nosStatus Mutex::unlock() {\n    return osMutexRelease(_osMutexId);\n}\n\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/Mutex.h",
    "content": "/* Copyright (c) 2012 mbed.org */\n#ifndef MUTEX_H\n#define MUTEX_H \n\n#include <stdint.h>\n#include \"cmsis_os.h\"\n\nnamespace rtos {\n\n/*! The Mutex class is used to synchronise the execution of threads.\n This is for example used to protect access to a shared resource.\n*/\nclass Mutex {\npublic:\n    /*! Create and Initialize a Mutex object */\n    Mutex();\n    \n    /*! Wait until a Mutex becomes available.\n      \\param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever)\n      \\return  status code that indicates the execution status of the function.\n     */ \n    osStatus lock(uint32_t millisec=osWaitForever);\n    \n    /*! Try to lock the mutex, and return immediately\n      \\return  true if the mutex was acquired, false otherwise.\n     */\n    bool trylock();\n    \n    /*! Unlock the mutex that has previously been locked by the same thread\n      \\return  status code that indicates the execution status of the function. \n     */\n    osStatus unlock();\n\nprivate:\n    osMutexId _osMutexId;\n    osMutexDef_t _osMutexDef;\n#ifdef CMSIS_OS_RTX\n    int32_t _mutex_data[3];\n#endif\n};\n\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/Queue.h",
    "content": "/* Copyright (c) 2012 mbed.org */\n#ifndef QUEUE_H\n#define QUEUE_H \n\n#include <stdint.h>\n#include <string.h>\n\n#include \"cmsis_os.h\"\n#include \"error.h\"\n\nnamespace rtos {\n\n/*! The Queue class allow to control, send, receive, or wait for messages.\n A message can be a integer or pointer value  to a certain type T that is send\n to a thread or interrupt service routine.\n  \\tparam  T         data type of a single message element.\n  \\tparam  queue_sz  maximum number of messages in queue.\n*/\ntemplate<typename T, uint32_t queue_sz>\nclass Queue {\npublic:\n    /*! Create and initialise a message Queue. */\n    Queue() {\n    #ifdef CMSIS_OS_RTX\n        memset(_queue_q, 0, sizeof(_queue_q));\n        _queue_def.pool = _queue_q;\n        _queue_def.queue_sz = queue_sz;\n    #endif\n        _queue_id = osMessageCreate(&_queue_def, NULL);\n        if (_queue_id == NULL) {\n            error(\"Error initialising the queue object\\n\");\n        }\n    }\n    \n    /*! Put a message in a Queue.\n      \\param   data      message pointer.\n      \\param   millisec  timeout value or 0 in case of no time-out. (default: 0)\n      \\return  status code that indicates the execution status of the function. \n    */\n    osStatus put(T* data, uint32_t millisec=0) {\n        return osMessagePut(_queue_id, (uint32_t)data, millisec);\n    }\n    \n    /*! Get a message or Wait for a message from a Queue.\n      \\param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).\n      \\return  event information that includes the message and the status code.\n    */\n    osEvent get(uint32_t millisec=osWaitForever) {\n        return osMessageGet(_queue_id, millisec);\n    }\n\nprivate:\n    osMessageQId    _queue_id;\n    osMessageQDef_t _queue_def;\n#ifdef CMSIS_OS_RTX\n    uint32_t        _queue_q[4+(queue_sz)];\n#endif\n};\n\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/RtosTimer.cpp",
    "content": "#include \"RtosTimer.h\"\n\n#include <string.h>\n\n#include \"cmsis_os.h\"\n//#include \"error.h\"\n\nnamespace rtos {\n\nRtosTimer::RtosTimer(void (*periodic_task)(void const *argument), os_timer_type type, void *argument) {\n#ifdef CMSIS_OS_RTX\n    _timer.ptimer = periodic_task;\n    \n    memset(_timer_data, 0, sizeof(_timer_data));\n    _timer.timer = _timer_data;\n#endif\n    _timer_id = osTimerCreate(&_timer, type, argument);\n}\n\nosStatus RtosTimer::start(uint32_t millisec) {\n    return osTimerStart(_timer_id, millisec);\n}\n\nosStatus RtosTimer::stop(void) {\n    return osTimerStop(_timer_id);\n}\n\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/RtosTimer.h",
    "content": "/* Copyright (c) 2012 mbed.org */\n#ifndef TIMER_H\n#define TIMER_H \n\n#include <stdint.h>\n#include \"cmsis_os.h\"\n\nnamespace rtos {\n\n/*! The RtosTimer class allow creating and and controlling of timer functions in the system.\n A timer function is called when a time period expires whereby both on-shot and\n periodic timers are possible. A timer can be started, restarted, or stopped.\n\n Timers are handled in the thread osTimerThread.\n Callback functions run under control of this thread and may use CMSIS-RTOS API calls. \n*/\nclass RtosTimer {\npublic:\n    /*! Create and Start timer.\n      \\param   task      name of the timer call back function.\n      \\param   type      osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)\n      \\param   argument  argument to the timer call back function. (default: NULL)\n    */\n    RtosTimer(void (*task)(void const *argument),\n          os_timer_type type=osTimerPeriodic,\n          void *argument=NULL);\n    \n    /*! Stop the timer.\n      \\return  status code that indicates the execution status of the function. \n    */\n    osStatus stop(void);\n    \n    /*! start a timer.\n      \\param   millisec  time delay value of the timer.\n      \\return  status code that indicates the execution status of the function. \n    */\n    osStatus start(uint32_t millisec);\n\nprivate:\n    osTimerId _timer_id;\n    osTimerDef_t _timer;\n#ifdef CMSIS_OS_RTX\n    uint32_t _timer_data[5];\n#endif\n};\n\n}\n\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/Semaphore.cpp",
    "content": "#include \"Semaphore.h\"\n\n#include <string.h>\n//#include \"error.h\"\n\nnamespace rtos {\n\nSemaphore::Semaphore(int32_t count) {\n#ifdef CMSIS_OS_RTX\n    memset(_semaphore_data, 0, sizeof(_semaphore_data));\n    _osSemaphoreDef.semaphore = _semaphore_data;\n#endif\n    _osSemaphoreId = osSemaphoreCreate(&_osSemaphoreDef, count);\n}\n\nint32_t Semaphore::wait(uint32_t millisec) {\n    return osSemaphoreWait(_osSemaphoreId, millisec);\n}\n\nosStatus Semaphore::release(void) {\n    return osSemaphoreRelease(_osSemaphoreId);\n}\n\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/Semaphore.h",
    "content": "/* Copyright (c) 2012 mbed.org */\n#ifndef SEMAPHORE_H\n#define SEMAPHORE_H \n\n#include <stdint.h>\n#include \"cmsis_os.h\"\n\nnamespace rtos {\n\n/*! The Semaphore class is used to manage and protect access to a set of shared resources. */\nclass Semaphore {\npublic:\n    /*! Create and Initialize a Semaphore object used for managing resources. \n      \\param number of available resources; maximum index value is (count-1).\n    */\n    Semaphore(int32_t count);\n    \n    /*! Wait until a Semaphore resource becomes available. \n      \\param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).\n      \\return  number of available tokens, or -1 in case of incorrect parameters\n    */\n    int32_t wait(uint32_t millisec=osWaitForever);\n    \n    /*! Release a Semaphore resource that was obtain with Semaphore::wait.\n      \\return  status code that indicates the execution status of the function. \n    */\n    osStatus release(void);\n\nprivate:\n    osSemaphoreId _osSemaphoreId;\n    osSemaphoreDef_t _osSemaphoreDef;\n#ifdef CMSIS_OS_RTX\n    uint32_t _semaphore_data[2];\n#endif\n};\n\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/Thread.cpp",
    "content": "#include \"Thread.h\"\n\nnamespace rtos {\n\nThread::Thread(void (*task)(void const *argument),\n               void *argument,\n               osPriority priority,\n               uint32_t stacksize) {\n    // The actual fields of os_thread_def are implementation specific in every CMSIS-RTOS\n#ifdef CMSIS_OS_RTX\n    _thread_def.pthread = task;\n    _thread_def.tpriority = priority;\n    _thread_def.instances = 1;\n    _thread_def.stacksize = stacksize;\n#endif\n    _tid = osThreadCreate(&_thread_def, argument);\n}\n\nosStatus Thread::terminate() {\n    return osThreadTerminate(_tid);\n}\n\nosStatus Thread::set_priority(osPriority priority) {\n    return osThreadSetPriority(_tid, priority);\n}\n\nosPriority Thread::get_priority() {\n    return osThreadGetPriority(_tid);\n}\n\nint32_t Thread::signal_set(int32_t signals) {\n    return osSignalSet(_tid, signals);\n}\n\nosEvent Thread::signal_wait(int32_t signals, uint32_t millisec) {\n    return osSignalWait(signals, millisec);\n}\n\nosStatus Thread::wait(uint32_t millisec) {\n    return osDelay(millisec);\n}\n\nosStatus Thread::yield() {\n    return osThreadYield();\n}\n\nosThreadId Thread::gettid() {\n    return osThreadGetId();\n}\n\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/Thread.h",
    "content": "/* Copyright (c) 2012 mbed.org */\n#ifndef THREAD_H\n#define THREAD_H \n\n#include <stdint.h>\n#include \"cmsis_os.h\"\n\n#define DEFAULT_STACK_SIZE 0x1000\n\nnamespace rtos {\n\n/*! The Thread class allow defining, creating, and controlling thread functions in the system. */\nclass Thread {\npublic:\n    /*! Create a new thread, and start it executing the specified function.\n      \\param   task      function to be executed by this thread.\n      \\param   argument  pointer that is passed to the thread function as start argument. (default: NULL).\n      \\param   priority  initial priority of the thread function. (default: osPriorityNormal).\n      \\param   stacksz   stack size (in bytes) requirements for the thread function. (default: DEFAULT_STACK_SIZE).\n    */\n    Thread(void (*task)(void const *argument),\n           void *argument=NULL,\n           osPriority priority=osPriorityNormal,\n           uint32_t stacksize=DEFAULT_STACK_SIZE);\n    \n    /*! Terminate execution of a thread and remove it from Active Threads\n      \\return  status code that indicates the execution status of the function.\n    */\n    osStatus terminate();\n    \n    /*! Set priority of an active thread\n      \\param   priority  new priority value for the thread function.\n      \\return  status code that indicates the execution status of the function.\n    */\n    osStatus set_priority(osPriority priority);\n    \n    /*! Get priority of an active thread\n      \\ return  current priority value of the thread function.\n    */\n    osPriority get_priority();\n    \n    /*! Set the specified Signal Flags of an active thread.\n      \\param   signals  specifies the signal flags of the thread that should be set.\n      \\return  previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\n    */\n    int32_t signal_set(int32_t signals);\n    \n    /*! Wait for one or more Signal Flags to become signaled for the current RUNNING thread. \n      \\param   signals   wait until all specified signal flags set or 0 for any single signal flag.\n      \\param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).\n      \\return  event flag information or error code.\n    */\n    static osEvent signal_wait(int32_t signals, uint32_t millisec=osWaitForever);\n    \n    \n    /*! Wait for a specified time period in millisec:\n      \\param   millisec  time delay value\n      \\return  status code that indicates the execution status of the function. \n    */\n    static osStatus wait(uint32_t millisec);\n    \n    /*! Pass control to next thread that is in state READY.\n      \\return  status code that indicates the execution status of the function.\n    */\n    static osStatus yield();\n    \n    /*! Get the thread id of the current running thread.\n      \\return  thread ID for reference by other functions or NULL in case of error.\n    */\n    static osThreadId gettid();\n\nprivate:\n    osThreadId _tid;\n    osThreadDef_t _thread_def;\n};\n\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/CPP/rtos.h",
    "content": "/* mbed Microcontroller Library\n * Copyright (c) 2006-2012 ARM Limited. All rights reserved.\n */\n#ifndef RTOS_H\n#define RTOS_H\n\n#include \"Thread.h\"\n#include \"Mutex.h\"\n#include \"RtosTimer.h\"\n#include \"Semaphore.h\"\n#include \"Mail.h\"\n#include \"MemoryPool.h\"\n#include \"Queue.h\"\n\nusing namespace rtos;\n\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/Hist.txt",
    "content": "This file describes the changes of the CMSIS-RTOS API interface for internal use\n================================================================================\n\nchanges V1.0 -> V1.01\n=====================\n\nPreparation for C++ class interface\n===================================\n---> const attribute moved to macros (to support C++ interface).\nconst attribute removed from typedef's (to allow C++ class interface).\nosThreadDef_t, osTimerDef_t, osMutexDef_t, osSemaphoreDef_t, osPoolDef_t, osMessageQDef_t, osMailQDef_t.\n\nconst added to the osXxxxDef macros:\nosThreadDef, osTimerDef, osMutexDef, osSemaphoreDef, osPoolDef, osMessageQDef, osMailQDef\n\nAllow to remove Timer/Mutex/Semaphore objects\n=============================================\nAdded: osTimerDelete, osMutexDelete, osSemaphoreDelete\n\n\nAdded function that initializes (but does not start) the osKernel\n=================================================================\nAdded: osKernelInitialize\nosKernelStart changed to osKernelStart (void)\n\n====================================================================\n\nVersion 1.02\n  Control functions for short timeouts in microsecond resolution:\n  Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTick_uSec\n  Removed: osSignalGet \n\nStill open for discussion\n=========================\nAdding Low Power extensions\nWe have added Low Power extensions to RTX a while ago.\nhttp://www.keil.com/support/man/docs/rlarm/rlarm_ar_low_power.htm\n\nWe should look into this solution (os_suspend/os_resume) and add this functionality to CMSIS RTOS by extending the API. Probably  we can use the same two functions (renamed to fit CMSIS RTOS) but we need to check if this fits (for example  os_resume parameter is in system ticks  same as in os_time_get)\n"
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    "path": "external/CMSIS_5/CMSIS/RTOS/Template/cmsis_os.h",
    "content": "/* ----------------------------------------------------------------------\n * $Date:        5. February 2013\n * $Revision:    V1.02\n *\n * Project:      CMSIS-RTOS API\n * Title:        cmsis_os.h template header file\n *\n * Version 0.02\n *    Initial Proposal Phase\n * Version 0.03\n *    osKernelStart added, optional feature: main started as thread\n *    osSemaphores have standard behavior\n *    osTimerCreate does not start the timer, added osTimerStart\n *    osThreadPass is renamed to osThreadYield\n * Version 1.01\n *    Support for C++ interface\n *     - const attribute removed from the osXxxxDef_t typedef's\n *     - const attribute added to the osXxxxDef macros\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\n *    Added: osKernelInitialize\n * Version 1.02\n *    Control functions for short timeouts in microsecond resolution:\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\n *    Removed: osSignalGet \n *----------------------------------------------------------------------------\n *\n * Copyright (c) 2013-2017 ARM LIMITED\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *---------------------------------------------------------------------------*/\n \n \n#ifndef _CMSIS_OS_H\n#define _CMSIS_OS_H\n \n/// \\note MUST REMAIN UNCHANGED: \\b osCMSIS identifies the CMSIS-RTOS API version.\n#define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])\n \n/// \\note CAN BE CHANGED: \\b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.\n#define osCMSIS_KERNEL    0x10000\t   ///< RTOS identification and version (main [31:16] .sub [15:0])\n \n/// \\note MUST REMAIN UNCHANGED: \\b osKernelSystemId shall be consistent in every CMSIS-RTOS.\n#define osKernelSystemId \"KERNEL V1.00\"   ///< RTOS identification string\n \n/// \\note MUST REMAIN UNCHANGED: \\b osFeature_xxx shall be consistent in every CMSIS-RTOS.\n#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available\n#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available\n#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available\n#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available\n#define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread\n#define osFeature_Semaphore    30      ///< maximum count for \\ref osSemaphoreCreate function\n#define osFeature_Wait         1       ///< osWait function: 1=available, 0=not available\n#define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available\n \n#include <stdint.h>\n#include <stddef.h>\n \n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n \n \n// ==== Enumeration, structures, defines ====\n \n/// Priority used for thread control.\n/// \\note MUST REMAIN UNCHANGED: \\b osPriority shall be consistent in every CMSIS-RTOS.\ntypedef enum  {\n  osPriorityIdle          = -3,          ///< priority: idle (lowest)\n  osPriorityLow           = -2,          ///< priority: low\n  osPriorityBelowNormal   = -1,          ///< priority: below normal\n  osPriorityNormal        =  0,          ///< priority: normal (default)\n  osPriorityAboveNormal   = +1,          ///< priority: above normal\n  osPriorityHigh          = +2,          ///< priority: high\n  osPriorityRealtime      = +3,          ///< priority: realtime (highest)\n  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority\n} osPriority;\n \n/// Timeout value.\n/// \\note MUST REMAIN UNCHANGED: \\b osWaitForever shall be consistent in every CMSIS-RTOS.\n#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value\n \n/// Status code values returned by CMSIS-RTOS functions.\n/// \\note MUST REMAIN UNCHANGED: \\b osStatus shall be consistent in every CMSIS-RTOS.\ntypedef enum  {\n  osOK                    =     0,       ///< function completed; no error or event occurred.\n  osEventSignal           =  0x08,       ///< function completed; signal event occurred.\n  osEventMessage          =  0x10,       ///< function completed; message event occurred.\n  osEventMail             =  0x20,       ///< function completed; mail event occurred.\n  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.\n  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.\n  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.\n  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.\n  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.\n  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.\n  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorValue            =  0x86,       ///< value of a parameter is out of range.\n  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.\n  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.\n} osStatus;\n \n \n/// Timer type value for the timer definition.\n/// \\note MUST REMAIN UNCHANGED: \\b os_timer_type shall be consistent in every CMSIS-RTOS.\ntypedef enum  {\n  osTimerOnce             =     0,       ///< one-shot timer\n  osTimerPeriodic         =     1        ///< repeating timer\n} os_timer_type;\n \n/// Entry point of a thread.\n/// \\note MUST REMAIN UNCHANGED: \\b os_pthread shall be consistent in every CMSIS-RTOS.\ntypedef void (*os_pthread) (void const *argument);\n \n/// Entry point of a timer call back function.\n/// \\note MUST REMAIN UNCHANGED: \\b os_ptimer shall be consistent in every CMSIS-RTOS.\ntypedef void (*os_ptimer) (void const *argument);\n \n// >>> the following data type definitions may shall adapted towards a specific RTOS\n \n/// Thread ID identifies the thread (pointer to a thread control block).\n/// \\note CAN BE CHANGED: \\b os_thread_cb is implementation specific in every CMSIS-RTOS.\ntypedef struct os_thread_cb *osThreadId;\n \n/// Timer ID identifies the timer (pointer to a timer control block).\n/// \\note CAN BE CHANGED: \\b os_timer_cb is implementation specific in every CMSIS-RTOS.\ntypedef struct os_timer_cb *osTimerId;\n \n/// Mutex ID identifies the mutex (pointer to a mutex control block).\n/// \\note CAN BE CHANGED: \\b os_mutex_cb is implementation specific in every CMSIS-RTOS.\ntypedef struct os_mutex_cb *osMutexId;\n \n/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).\n/// \\note CAN BE CHANGED: \\b os_semaphore_cb is implementation specific in every CMSIS-RTOS.\ntypedef struct os_semaphore_cb *osSemaphoreId;\n \n/// Pool ID identifies the memory pool (pointer to a memory pool control block).\n/// \\note CAN BE CHANGED: \\b os_pool_cb is implementation specific in every CMSIS-RTOS.\ntypedef struct os_pool_cb *osPoolId;\n \n/// Message ID identifies the message queue (pointer to a message queue control block).\n/// \\note CAN BE CHANGED: \\b os_messageQ_cb is implementation specific in every CMSIS-RTOS.\ntypedef struct os_messageQ_cb *osMessageQId;\n \n/// Mail ID identifies the mail queue (pointer to a mail queue control block).\n/// \\note CAN BE CHANGED: \\b os_mailQ_cb is implementation specific in every CMSIS-RTOS.\ntypedef struct os_mailQ_cb *osMailQId;\n \n \n/// Thread Definition structure contains startup information of a thread.\n/// \\note CAN BE CHANGED: \\b os_thread_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_thread_def  {\n  os_pthread               pthread;    ///< start address of thread function\n  osPriority             tpriority;    ///< initial thread priority\n  uint32_t               instances;    ///< maximum number of instances of that thread function\n  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size\n} osThreadDef_t;\n \n/// Timer Definition structure contains timer parameters.\n/// \\note CAN BE CHANGED: \\b os_timer_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_timer_def  {\n  os_ptimer                 ptimer;    ///< start address of a timer function\n} osTimerDef_t;\n \n/// Mutex Definition structure contains setup information for a mutex.\n/// \\note CAN BE CHANGED: \\b os_mutex_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_mutex_def  {\n  uint32_t                   dummy;    ///< dummy value.\n} osMutexDef_t;\n \n/// Semaphore Definition structure contains setup information for a semaphore.\n/// \\note CAN BE CHANGED: \\b os_semaphore_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_semaphore_def  {\n  uint32_t                   dummy;    ///< dummy value.\n} osSemaphoreDef_t;\n \n/// Definition structure for memory block allocation.\n/// \\note CAN BE CHANGED: \\b os_pool_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_pool_def  {\n  uint32_t                 pool_sz;    ///< number of items (elements) in the pool\n  uint32_t                 item_sz;    ///< size of an item\n  void                       *pool;    ///< pointer to memory for pool\n} osPoolDef_t;\n \n/// Definition structure for message queue.\n/// \\note CAN BE CHANGED: \\b os_messageQ_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_messageQ_def  {\n  uint32_t                queue_sz;    ///< number of elements in the queue\n  uint32_t                 item_sz;    ///< size of an item\n  void                       *pool;    ///< memory array for messages\n} osMessageQDef_t;\n \n/// Definition structure for mail queue.\n/// \\note CAN BE CHANGED: \\b os_mailQ_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_mailQ_def  {\n  uint32_t                queue_sz;    ///< number of elements in the queue\n  uint32_t                 item_sz;    ///< size of an item\n  void                       *pool;    ///< memory array for mail\n} osMailQDef_t;\n \n/// Event structure contains detailed information about an event.\n/// \\note MUST REMAIN UNCHANGED: \\b os_event shall be consistent in every CMSIS-RTOS.\n///       However the struct may be extended at the end.\ntypedef struct  {\n  osStatus                 status;     ///< status code: event or error information\n  union  {\n    uint32_t                    v;     ///< message as 32-bit value\n    void                       *p;     ///< message or mail as void pointer\n    int32_t               signals;     ///< signal flags\n  } value;                             ///< event value\n  union  {\n    osMailQId             mail_id;     ///< mail id obtained by \\ref osMailCreate\n    osMessageQId       message_id;     ///< message id obtained by \\ref osMessageCreate\n  } def;                               ///< event definition\n} osEvent;\n \n \n//  ==== Kernel Control Functions ====\n \n/// Initialize the RTOS Kernel for creating objects.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelInitialize shall be consistent in every CMSIS-RTOS.\nosStatus osKernelInitialize (void);\n \n/// Start the RTOS Kernel.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelStart shall be consistent in every CMSIS-RTOS.\nosStatus osKernelStart (void);\n \n/// Check if the RTOS kernel is already started.\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelRunning shall be consistent in every CMSIS-RTOS.\n/// \\return 0 RTOS is not started, 1 RTOS is started.\nint32_t osKernelRunning(void);\n \n#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available\n \n/// Get the RTOS kernel system timer counter \n/// \\note MUST REMAIN UNCHANGED: \\b osKernelSysTick shall be consistent in every CMSIS-RTOS.\n/// \\return RTOS kernel system timer as 32-bit value \nuint32_t osKernelSysTick (void);\n \n/// The RTOS kernel system timer frequency in Hz\n/// \\note Reflects the system timer setting and is typically defined in a configuration file.\n#define osKernelSysTickFrequency 100000000\n \n/// Convert a microseconds value to a RTOS kernel system timer value.\n/// \\param         microsec     time value in microseconds.\n/// \\return time value normalized to the \\ref osKernelSysTickFrequency\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)\n \n#endif    // System Timer available\n \n//  ==== Thread Management ====\n \n/// Create a Thread Definition with function, priority, and stack requirements.\n/// \\param         name         name of the thread function.\n/// \\param         priority     initial priority of the thread function.\n/// \\param         instances    number of possible thread instances.\n/// \\param         stacksz      stack size (in bytes) requirements for the thread function.\n/// \\note CAN BE CHANGED: The parameters to \\b osThreadDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osThreadDef(name, priority, instances, stacksz)  \\\nextern const osThreadDef_t os_thread_def_##name\n#else                            // define the object\n#define osThreadDef(name, priority, instances, stacksz)  \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ (name), (priority), (instances), (stacksz)  }\n#endif\n \n/// Access a Thread definition.\n/// \\param         name          name of the thread definition object.\n/// \\note CAN BE CHANGED: The parameter to \\b osThread shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osThread(name)  \\\n&os_thread_def_##name\n \n/// Create a thread and add it to Active Threads and set it to state READY.\n/// \\param[in]     thread_def    thread definition referenced with \\ref osThread.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\return thread ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadCreate shall be consistent in every CMSIS-RTOS.\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);\n \n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadGetId shall be consistent in every CMSIS-RTOS.\nosThreadId osThreadGetId (void);\n \n/// Terminate execution of a thread and remove it from Active Threads.\n/// \\param[in]     thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadTerminate shall be consistent in every CMSIS-RTOS.\nosStatus osThreadTerminate (osThreadId thread_id);\n \n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadYield shall be consistent in every CMSIS-RTOS.\nosStatus osThreadYield (void);\n \n/// Change priority of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadSetPriority shall be consistent in every CMSIS-RTOS.\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);\n \n/// Get current priority of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return current priority value of the thread function.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadGetPriority shall be consistent in every CMSIS-RTOS.\nosPriority osThreadGetPriority (osThreadId thread_id);\n \n \n//  ==== Generic Wait Functions ====\n \n/// Wait for Timeout (Time Delay).\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value\n/// \\return status code that indicates the execution status of the function.\nosStatus osDelay (uint32_t millisec);\n \n#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available\n \n/// Wait for Signal, Message, Mail, or Timeout.\n/// \\param[in] millisec          \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return event that contains signal, message, or mail information or error code.\n/// \\note MUST REMAIN UNCHANGED: \\b osWait shall be consistent in every CMSIS-RTOS.\nosEvent osWait (uint32_t millisec);\n \n#endif  // Generic Wait available\n \n \n//  ==== Timer Management Functions ====\n/// Define a Timer object.\n/// \\param         name          name of the timer object.\n/// \\param         function      name of the timer call back function.\n/// \\note CAN BE CHANGED: The parameter to \\b osTimerDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osTimerDef(name, function)  \\\nextern const osTimerDef_t os_timer_def_##name\n#else                            // define the object\n#define osTimerDef(name, function)  \\\nconst osTimerDef_t os_timer_def_##name = \\\n{ (function) }\n#endif\n \n/// Access a Timer definition.\n/// \\param         name          name of the timer object.\n/// \\note CAN BE CHANGED: The parameter to \\b osTimer shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osTimer(name) \\\n&os_timer_def_##name\n \n/// Create a timer.\n/// \\param[in]     timer_def     timer object referenced with \\ref osTimer.\n/// \\param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer call back function.\n/// \\return timer ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerCreate shall be consistent in every CMSIS-RTOS.\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);\n \n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value of the timer.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerStart shall be consistent in every CMSIS-RTOS.\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec);\n \n/// Stop the timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerStop shall be consistent in every CMSIS-RTOS.\nosStatus osTimerStop (osTimerId timer_id);\n \n/// Delete a timer that was created by \\ref osTimerCreate.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerDelete shall be consistent in every CMSIS-RTOS.\nosStatus osTimerDelete (osTimerId timer_id);\n \n \n//  ==== Signal Management ====\n \n/// Set the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that should be set.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\n/// \\note MUST REMAIN UNCHANGED: \\b osSignalSet shall be consistent in every CMSIS-RTOS.\nint32_t osSignalSet (osThreadId thread_id, int32_t signals);\n \n/// Clear the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that shall be cleared.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.\n/// \\note MUST REMAIN UNCHANGED: \\b osSignalClear shall be consistent in every CMSIS-RTOS.\nint32_t osSignalClear (osThreadId thread_id, int32_t signals);\n \n/// Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\n/// \\param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event flag information or error code.\n/// \\note MUST REMAIN UNCHANGED: \\b osSignalWait shall be consistent in every CMSIS-RTOS.\nosEvent osSignalWait (int32_t signals, uint32_t millisec);\n \n \n//  ==== Mutex Management ====\n \n/// Define a Mutex.\n/// \\param         name          name of the mutex object.\n/// \\note CAN BE CHANGED: The parameter to \\b osMutexDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osMutexDef(name)  \\\nextern const osMutexDef_t os_mutex_def_##name\n#else                            // define the object\n#define osMutexDef(name)  \\\nconst osMutexDef_t os_mutex_def_##name = { 0 }\n#endif\n \n/// Access a Mutex definition.\n/// \\param         name          name of the mutex object.\n/// \\note CAN BE CHANGED: The parameter to \\b osMutex shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osMutex(name)  \\\n&os_mutex_def_##name\n \n/// Create and Initialize a Mutex object.\n/// \\param[in]     mutex_def     mutex definition referenced with \\ref osMutex.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexCreate shall be consistent in every CMSIS-RTOS.\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def);\n \n/// Wait until a Mutex becomes available.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexWait shall be consistent in every CMSIS-RTOS.\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);\n \n/// Release a Mutex that was obtained by \\ref osMutexWait.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexRelease shall be consistent in every CMSIS-RTOS.\nosStatus osMutexRelease (osMutexId mutex_id);\n \n/// Delete a Mutex that was created by \\ref osMutexCreate.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexDelete shall be consistent in every CMSIS-RTOS.\nosStatus osMutexDelete (osMutexId mutex_id);\n \n \n//  ==== Semaphore Management Functions ====\n \n#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available\n \n/// Define a Semaphore object.\n/// \\param         name          name of the semaphore object.\n/// \\note CAN BE CHANGED: The parameter to \\b osSemaphoreDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osSemaphoreDef(name)  \\\nextern const osSemaphoreDef_t os_semaphore_def_##name\n#else                            // define the object\n#define osSemaphoreDef(name)  \\\nconst osSemaphoreDef_t os_semaphore_def_##name = { 0 }\n#endif\n \n/// Access a Semaphore definition.\n/// \\param         name          name of the semaphore object.\n/// \\note CAN BE CHANGED: The parameter to \\b osSemaphore shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osSemaphore(name)  \\\n&os_semaphore_def_##name\n \n/// Create and Initialize a Semaphore object used for managing resources.\n/// \\param[in]     semaphore_def semaphore definition referenced with \\ref osSemaphore.\n/// \\param[in]     count         number of available resources.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);\n \n/// Wait until a Semaphore token becomes available.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return number of available tokens, or -1 in case of incorrect parameters.\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreWait shall be consistent in every CMSIS-RTOS.\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);\n \n/// Release a Semaphore token.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id);\n \n/// Delete a Semaphore that was created by \\ref osSemaphoreCreate.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id);\n \n#endif     // Semaphore available\n \n \n//  ==== Memory Pool Management Functions ====\n \n#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available\n \n/// \\brief Define a Memory Pool.\n/// \\param         name          name of the memory pool.\n/// \\param         no            maximum number of blocks (objects) in the memory pool.\n/// \\param         type          data type of a single block (object).\n/// \\note CAN BE CHANGED: The parameter to \\b osPoolDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osPoolDef(name, no, type)   \\\nextern const osPoolDef_t os_pool_def_##name\n#else                            // define the object\n#define osPoolDef(name, no, type)   \\\nconst osPoolDef_t os_pool_def_##name = \\\n{ (no), sizeof(type), NULL }\n#endif\n \n/// \\brief Access a Memory Pool definition.\n/// \\param         name          name of the memory pool\n/// \\note CAN BE CHANGED: The parameter to \\b osPool shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osPool(name) \\\n&os_pool_def_##name\n \n/// Create and Initialize a memory pool.\n/// \\param[in]     pool_def      memory pool definition referenced with \\ref osPool.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolCreate shall be consistent in every CMSIS-RTOS.\nosPoolId osPoolCreate (const osPoolDef_t *pool_def);\n \n/// Allocate a memory block from a memory pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolAlloc shall be consistent in every CMSIS-RTOS.\nvoid *osPoolAlloc (osPoolId pool_id);\n \n/// Allocate a memory block from a memory pool and set memory block to zero.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolCAlloc shall be consistent in every CMSIS-RTOS.\nvoid *osPoolCAlloc (osPoolId pool_id);\n \n/// Return an allocated memory block back to a specific memory pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\param[in]     block         address of the allocated memory block that is returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolFree shall be consistent in every CMSIS-RTOS.\nosStatus osPoolFree (osPoolId pool_id, void *block);\n \n#endif   // Memory Pool Management available\n \n \n//  ==== Message Queue Management Functions ====\n \n#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available\n \n/// \\brief Create a Message Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of messages in the queue.\n/// \\param         type          data type of a single message element (for debugger).\n/// \\note CAN BE CHANGED: The parameter to \\b osMessageQDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osMessageQDef(name, queue_sz, type)   \\\nextern const osMessageQDef_t os_messageQ_def_##name\n#else                            // define the object\n#define osMessageQDef(name, queue_sz, type)   \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), sizeof (type)  }\n#endif\n \n/// \\brief Access a Message Queue Definition.\n/// \\param         name          name of the queue\n/// \\note CAN BE CHANGED: The parameter to \\b osMessageQ shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osMessageQ(name) \\\n&os_messageQ_def_##name\n \n/// Create and Initialize a Message Queue.\n/// \\param[in]     queue_def     queue definition referenced with \\ref osMessageQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMessageCreate shall be consistent in every CMSIS-RTOS.\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);\n \n/// Put a Message to a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     info          message information.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMessagePut shall be consistent in every CMSIS-RTOS.\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);\n \n/// Get a Message or Wait for a Message from a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\n/// \\note MUST REMAIN UNCHANGED: \\b osMessageGet shall be consistent in every CMSIS-RTOS.\nosEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);\n \n#endif     // Message Queues available\n \n \n//  ==== Mail Queue Management Functions ====\n \n#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available\n \n/// \\brief Create a Mail Queue Definition.\n/// \\param         name          name of the queue\n/// \\param         queue_sz      maximum number of messages in queue\n/// \\param         type          data type of a single message element\n/// \\note CAN BE CHANGED: The parameter to \\b osMailQDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osMailQDef(name, queue_sz, type) \\\nextern const osMailQDef_t os_mailQ_def_##name\n#else                            // define the object\n#define osMailQDef(name, queue_sz, type) \\\nconst osMailQDef_t os_mailQ_def_##name =  \\\n{ (queue_sz), sizeof (type) }\n#endif\n \n/// \\brief Access a Mail Queue Definition.\n/// \\param         name          name of the queue\n/// \\note CAN BE CHANGED: The parameter to \\b osMailQ shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osMailQ(name)  \\\n&os_mailQ_def_##name\n \n/// Create and Initialize mail queue.\n/// \\param[in]     queue_def     reference to the mail queue definition obtain with \\ref osMailQ\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return mail queue ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailCreate shall be consistent in every CMSIS-RTOS.\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);\n \n/// Allocate a memory block from a mail.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailAlloc shall be consistent in every CMSIS-RTOS.\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec);\n \n/// Allocate a memory block from a mail and set memory block to zero.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailCAlloc shall be consistent in every CMSIS-RTOS.\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec);\n \n/// Put a mail to a queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          memory block previously allocated with \\ref osMailAlloc or \\ref osMailCAlloc.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailPut shall be consistent in every CMSIS-RTOS.\nosStatus osMailPut (osMailQId queue_id, void *mail);\n \n/// Get a mail from a queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return event that contains mail information or error code.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailGet shall be consistent in every CMSIS-RTOS.\nosEvent osMailGet (osMailQId queue_id, uint32_t millisec);\n \n/// Free a memory block from a mail.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to the memory block that was obtained with \\ref osMailGet.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailFree shall be consistent in every CMSIS-RTOS.\nosStatus osMailFree (osMailQId queue_id, void *mail);\n \n#endif  // Mail Queues available\n \n \n#ifdef  __cplusplus\n}\n#endif\n \n#endif  // _CMSIS_OS_H\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/my_objects.h",
    "content": "#include \"cmsis_os.h\"                               // CMSIS RTOS header file\n\nextern void thread_sample (void const *argument);   // prototype\n\ntypedef struct  a {\n  char y[100];\n} a_element;\n\nosThreadDef   (thread_sample, osPriorityBelowNormal, 2, 100);\n\nosPoolDef(MyPool, 10, struct a);\nosMessageQDef(MyMessage, 10, a_element *);\nosMailQDef(MyMail, 10, a_element);\n\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/os_sample.c",
    "content": "/* ----------------------------------------------------------------------  \n * Copyright (C) 2011 ARM Limited. All rights reserved.  \n *  \n * $Date:        30. November 2011\n * $Revision:    V0.02\n *  \n * Project: \t CMSIS-RTOS API\n * Title:\t     os_sample.c\n *  \n * Description:\t This file shows the usage of the CMSIS-RTOS API.\n *  \n *  \n * Version 0.02\n *    Initial Proposal Phase \n * -------------------------------------------------------------------- */ \n\n\n#include \"my_objects.h\"              // Define CMSIS OS Objects\n\n// dummy functions since there is no OS today\n\n/// Add a thread to ActiveThreads and set it to state READY\nosThreadId  osThreadCreate (const osThreadDef_t *thread_def, void *argument)  { return osOK; }\n\n/// Terminate execution of a thread and remove it from ActiveThreads\nosStatus osThreadTerminate (osThreadId thread_id)   { return osOK; }\n\n/// Change prority of an existing thread  \nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)   { return osOK; }\n\n/// Get current prority of an existing thread  \nosPriority osThreadGetPriority (osThreadId thread_id)   { return osPriorityNormal; }\n\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { return NULL; }\n\nosThreadId osThreadGetId (void)  {  return 0; }\n\n\nosStatus status;\nosThreadId thread_sample1;\nosThreadId thread_sample2;\n\nosMessageQDef(TcpMessageQ0, 10, a_element *);\nosMessageQDef(TcpMessageQ1, 10, a_element *);\nosMessageQDef(TcpMessageQ2, 10, a_element *);\nosMessageQDef(TcpMessageQ3, 10, a_element *);\n\nconst osMessageQDef_t *TcpMessageQDef[4]\n#if 1\n =  {\n  osMessageQ(TcpMessageQ0),\n  osMessageQ(TcpMessageQ1),\n  osMessageQ(TcpMessageQ2),\n  osMessageQ(TcpMessageQ3),\n}\n#endif\n;\n\nosMessageQId TcpMessageQ[4];\n\nvoid CreateMessageQueues (void)  {\n  uint32_t i;\n\n  for (i = 0; i < 4; i++)  {\n    TcpMessageQ[i] = osMessageCreate (TcpMessageQDef[i], NULL);\n  }\n}   \n\n\nint main (void)  {\n  thread_sample1 = osThreadCreate (osThread (thread_sample), NULL);\n  thread_sample2 = osThreadCreate (osThread (thread_sample), NULL);\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/os_sample1.c",
    "content": "/* ----------------------------------------------------------------------  \n * Copyright (C) 2011 ARM Limited. All rights reserved.  \n *  \n * $Date:        30. November 2011\n * $Revision:    V0.02\n *  \n * Project: \t    CMSIS-RTOS API\n * Title:\t    os_sample1.c\n *  \n * Description:\tThis file shows the usage of the CMSIS-RTOS API.\n *  \n * Version 0.02\n *    Initial Proposal Phase \n * -------------------------------------------------------------------- */ \n\n\n#define osObjectsExternal\n#include \"my_objects.h\"              // Reference CMSIS OS Objects\n\n\nvoid thread_sample (void const *argument)  {\n  osThreadId my_thread;\n  osPriority my_priority;\n  int i = 1000;\n\n  my_thread = osThreadGetId();\n  my_priority = osThreadGetPriority (my_thread);  // Get priority of own thread\n  while (i > 0)  {\n    osThreadSetPriority (my_thread, osPriorityAboveNormal);\n    i--;\n  }\n  osThreadSetPriority (my_thread, my_priority);\n  osThreadTerminate (my_thread);                  // terminate own thread\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/startup_LPC177x_8x.s",
    "content": ";/*****************************************************************************\n; * @file:    startup_LPC177x_8x.s\n; * @purpose: CMSIS Cortex-M3 Core Device Startup File\n; *           for the NXP LPC177x_8x Device Series \n; * @version: V1.20\n; * @date:    07. October 2010\n; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n; *\n; * Copyright (C) 2010 ARM Limited. All rights reserved.\n; * ARM Limited (ARM) is supplying this software for use with Cortex-M3\n; * processor based microcontrollers.  This file can be freely distributed\n; * within development tools that are supporting such ARM based processors.\n; *\n; * THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n; *\n; *****************************************************************************/\n\n\n; <h> Stack Configuration\n;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n\nStack_Size      EQU     0x00000200\n\n                AREA    STACK, NOINIT, READWRITE, ALIGN=3\nStack_Mem       SPACE   Stack_Size\n__initial_sp\n\n\n; <h> Heap Configuration\n;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n\nHeap_Size       EQU     0x00000000\n\n                AREA    HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE   Heap_Size\n__heap_limit\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA    RESET, DATA, READONLY\n                EXPORT  __Vectors\n\n__Vectors       DCD     __initial_sp              ; Top of Stack\n                DCD     Reset_Handler             ; Reset Handler\n                DCD     NMI_Handler               ; NMI Handler\n                DCD     HardFault_Handler         ; Hard Fault Handler\n                DCD     MemManage_Handler         ; MPU Fault Handler\n                DCD     BusFault_Handler          ; Bus Fault Handler\n                DCD     UsageFault_Handler        ; Usage Fault Handler\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     0                         ; Reserved\n                DCD     SVC_Handler               ; SVCall Handler\n                DCD     DebugMon_Handler          ; Debug Monitor Handler\n                DCD     0                         ; Reserved\n                DCD     PendSV_Handler            ; PendSV Handler\n                DCD     SysTick_Handler           ; SysTick Handler\n\n                ; External Interrupts\n                DCD     WDT_IRQHandler            ; 16: Watchdog Timer\n                DCD     TIMER0_IRQHandler         ; 17: Timer0\n                DCD     TIMER1_IRQHandler         ; 18: Timer1\n                DCD     TIMER2_IRQHandler         ; 19: Timer2\n                DCD     TIMER3_IRQHandler         ; 20: Timer3\n                DCD     UART0_IRQHandler          ; 21: UART0\n                DCD     UART1_IRQHandler          ; 22: UART1\n                DCD     UART2_IRQHandler          ; 23: UART2\n                DCD     UART3_IRQHandler          ; 24: UART3\n                DCD     PWM1_IRQHandler           ; 25: PWM1\n                DCD     I2C0_IRQHandler           ; 26: I2C0\n                DCD     I2C1_IRQHandler           ; 27: I2C1\n                DCD     I2C2_IRQHandler           ; 28: I2C2\n                DCD     SPIFI_IRQHandler          ; 29: SPIFI\n                DCD     SSP0_IRQHandler           ; 30: SSP0\n                DCD     SSP1_IRQHandler           ; 31: SSP1\n                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)\n                DCD     RTC_IRQHandler            ; 33: Real Time Clock\n                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0\n                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1\n                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2\n                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3\n                DCD     ADC_IRQHandler            ; 38: A/D Converter\n                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect\n                DCD     USB_IRQHandler            ; 40: USB\n                DCD     CAN_IRQHandler            ; 41: CAN\n                DCD     DMA_IRQHandler            ; 42: General Purpose DMA\n                DCD     I2S_IRQHandler            ; 43: I2S\n                DCD     ENET_IRQHandler           ; 44: Ethernet\n                DCD     MCI_IRQHandler            ; 45: SD/MMC card I/F\n                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM\n                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface\n                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)\n\t\t\t\tDCD\t\tUSBActivity_IRQHandler    ; 49: USB Activity interrupt to wakeup\n\t\t\t\tDCD\t\tCANActivity_IRQHandler    ; 50: CAN Activity interrupt to wakeup\n\t\t\t\tDCD\t\tUART4_IRQHandler          ; 51: UART4\n\t\t\t\tDCD\t\tSSP2_IRQHandler           ; 52: SSP2\n\t\t\t\tDCD\t\tLCD_IRQHandler            ; 53: LCD\n\t\t\t\tDCD\t\tGPIO_IRQHandler           ; 54: GPIO\n\t\t\t\tDCD\t\tPWM0_IRQHandler           ; 55: PWM0\n\t\t\t\tDCD\t\tEEPROM_IRQHandler         ; 56: EEPROM\n\n\n                IF      :LNOT::DEF:NO_CRP\n                AREA    |.ARM.__at_0x02FC|, CODE, READONLY\nCRP_Key         DCD     0xFFFFFFFF\n                ENDIF\n\n\n                AREA    |.text|, CODE, READONLY\n\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT  Reset_Handler             [WEAK]\n\t\t\t\tIMPORT  SystemInit\n                IMPORT  __main\n\t\t\t\tLDR     R0, =SystemInit\n                BLX     R0\n                LDR     R0, =__main\n                BX      R0\n                ENDP\n\n\n; Dummy Exception Handlers (infinite loops which can be modified)\n\nNMI_Handler     PROC\n                EXPORT  NMI_Handler               [WEAK]\n                B       .\n                ENDP\nHardFault_Handler\\\n                PROC\n                EXPORT  HardFault_Handler         [WEAK]\n                B       .\n                ENDP\nMemManage_Handler\\\n                PROC\n                EXPORT  MemManage_Handler         [WEAK]\n                B       .\n                ENDP\nBusFault_Handler\\\n                PROC\n                EXPORT  BusFault_Handler          [WEAK]\n                B       .\n                ENDP\nUsageFault_Handler\\\n                PROC\n                EXPORT  UsageFault_Handler        [WEAK]\n                B       .\n                ENDP\nSVC_Handler     PROC\n                EXPORT  SVC_Handler               [WEAK]\n                B       .\n                ENDP\nDebugMon_Handler\\\n                PROC\n                EXPORT  DebugMon_Handler          [WEAK]\n                B       .\n                ENDP\nPendSV_Handler  PROC\n                EXPORT  PendSV_Handler            [WEAK]\n                B       .\n                ENDP\nSysTick_Handler PROC\n                EXPORT  SysTick_Handler           [WEAK]\n                B       .\n                ENDP\n\nDefault_Handler PROC\n\n                EXPORT  WDT_IRQHandler            [WEAK]\n                EXPORT  TIMER0_IRQHandler         [WEAK]\n                EXPORT  TIMER1_IRQHandler         [WEAK]\n                EXPORT  TIMER2_IRQHandler         [WEAK]\n                EXPORT  TIMER3_IRQHandler         [WEAK]\n                EXPORT  UART0_IRQHandler          [WEAK]\n                EXPORT  UART1_IRQHandler          [WEAK]\n                EXPORT  UART2_IRQHandler          [WEAK]\n                EXPORT  UART3_IRQHandler          [WEAK]\n                EXPORT  PWM1_IRQHandler           [WEAK]\n                EXPORT  I2C0_IRQHandler           [WEAK]\n                EXPORT  I2C1_IRQHandler           [WEAK]\n                EXPORT  I2C2_IRQHandler           [WEAK]\n                EXPORT  SPIFI_IRQHandler          [WEAK]\n                EXPORT  SSP0_IRQHandler           [WEAK]\n                EXPORT  SSP1_IRQHandler           [WEAK]\n                EXPORT  PLL0_IRQHandler           [WEAK]\n                EXPORT  RTC_IRQHandler            [WEAK]\n                EXPORT  EINT0_IRQHandler          [WEAK]\n                EXPORT  EINT1_IRQHandler          [WEAK]\n                EXPORT  EINT2_IRQHandler          [WEAK]\n                EXPORT  EINT3_IRQHandler          [WEAK]\n                EXPORT  ADC_IRQHandler            [WEAK]\n                EXPORT  BOD_IRQHandler            [WEAK]\n                EXPORT  USB_IRQHandler            [WEAK]\n                EXPORT  CAN_IRQHandler            [WEAK]\n                EXPORT  DMA_IRQHandler            [WEAK]\n                EXPORT  I2S_IRQHandler            [WEAK]\n                EXPORT  ENET_IRQHandler           [WEAK]\n                EXPORT  MCI_IRQHandler            [WEAK]\n                EXPORT  MCPWM_IRQHandler          [WEAK]\n                EXPORT  QEI_IRQHandler            [WEAK]\n                EXPORT  PLL1_IRQHandler           [WEAK]\n\t\t\t\tEXPORT  USBActivity_IRQHandler    [WEAK]\n\t\t\t\tEXPORT  CANActivity_IRQHandler    [WEAK]\n\t\t\t\tEXPORT  UART4_IRQHandler          [WEAK]\n\t\t\t\tEXPORT  SSP2_IRQHandler           [WEAK]\n\t\t\t\tEXPORT  LCD_IRQHandler            [WEAK]\n\t\t\t\tEXPORT  GPIO_IRQHandler           [WEAK]\n\t\t\t\tEXPORT  PWM0_IRQHandler           [WEAK]\n\t\t\t\tEXPORT  EEPROM_IRQHandler         [WEAK]\n\nWDT_IRQHandler\nTIMER0_IRQHandler\nTIMER1_IRQHandler\nTIMER2_IRQHandler\nTIMER3_IRQHandler\nUART0_IRQHandler\nUART1_IRQHandler\nUART2_IRQHandler\nUART3_IRQHandler\nPWM1_IRQHandler\nI2C0_IRQHandler\nI2C1_IRQHandler\nI2C2_IRQHandler\nSPIFI_IRQHandler            \nSSP0_IRQHandler\nSSP1_IRQHandler\nPLL0_IRQHandler\nRTC_IRQHandler\nEINT0_IRQHandler\nEINT1_IRQHandler\nEINT2_IRQHandler\nEINT3_IRQHandler\nADC_IRQHandler\nBOD_IRQHandler\nUSB_IRQHandler\nCAN_IRQHandler\nDMA_IRQHandler\nI2S_IRQHandler\nENET_IRQHandler\nMCI_IRQHandler          \nMCPWM_IRQHandler\nQEI_IRQHandler\nPLL1_IRQHandler\nUSBActivity_IRQHandler\nCANActivity_IRQHandler\nUART4_IRQHandler\nSSP2_IRQHandler\nLCD_IRQHandler\nGPIO_IRQHandler\nPWM0_IRQHandler\nEEPROM_IRQHandler\n\n                B       .\n\n                ENDP\n\n\n                ALIGN\n\n\n; User Initial Stack & Heap\n\n                IF      :DEF:__MICROLIB\n\n                EXPORT  __initial_sp\n                EXPORT  __heap_base\n                EXPORT  __heap_limit\n\n                ELSE\n\n                IMPORT  __use_two_region_memory\n                EXPORT  __user_initial_stackheap\n__user_initial_stackheap\n\n                LDR     R0, =  Heap_Mem\n                LDR     R1, =(Stack_Mem + Stack_Size)\n                LDR     R2, = (Heap_Mem +  Heap_Size)\n                LDR     R3, = Stack_Mem\n                BX      LR\n\n                ALIGN\n\n                ENDIF\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS/Template/system_LPC177x_8x.c",
    "content": "/***********************************************************************//**\n * @file\t\tsystem_LPC177x_8x.c\n * @brief       CMSIS Cortex-M3 Device Peripheral Access Layer Source File\n *              for the NXP LPC177x_8x Device Series\n * @version     V1.11\n * @date        10. November. 2010\n * @author\t\tNXP MCU SW Application Team\n **************************************************************************\n * Software that is described herein is for illustrative purposes only\n * which provides customers with programming information regarding the\n * products. This software is supplied \"AS IS\" without any warranties.\n * NXP Semiconductors assumes no responsibility or liability for the\n * use of the software, conveys no license or title under any patent,\n * copyright, or mask work right to the product. NXP Semiconductors\n * reserves the right to make changes in the software without\n * notification. NXP Semiconductors also make no representation or\n * warranty that such application will be suitable for the specified\n * use without further testing or modification.\n **********************************************************************/\n\n\n#include <stdint.h>\n#include \"LPC177x_8x.h\"\n#include \"system_LPC177x_8x.h\"\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n/*--------------------- Clock Configuration ----------------------------------\n//\n// <e> Clock Configuration\n//   <h> System Controls and Status Register (SCS)\n//     <o1.0>       EMC_SHIFT: EMC Shift enable\n//                     <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit\n//                     <1=> Static CS addresses start at LSB 0 regardless of memory width\n//     <o1.1>       EMC_RESET: EMC Reset disable\n//                     <0=> EMC will be reset by any chip reset\n//                     <1=> Portions of EMC will only be reset by POR or BOR\n//     <o1.2>       EMC_BURST: EMC Burst disable\n//     <o1.3>       MCIPWR_LEVEL: SD card interface signal SD_PWR Active Level selection\n//                     <0=> SD_PWR is active low\n//                     <1=> SD_PWR is active high\n//     <o1.4>       OSCRANGE: Main Oscillator Range Select\n//                     <0=>  1 MHz to 20 MHz\n//                     <1=> 15 MHz to 25 MHz\n//     <o1.5>       OSCEN: Main Oscillator enable\n//   </h>\n//\n//   <h> Clock Source Select Register (CLKSRCSEL)\n//     <o2.0>       CLKSRC: sysclk and PLL0 clock source selection\n//                     <0=> Internal RC oscillator\n//                     <1=> Main oscillator\n//   </h>\n//\n//   <e3> PLL0 Configuration (Main PLL)\n//     <h> PLL0 Configuration Register (PLL0CFG)\n//                     <i> PLL out clock = (F_cco / (2 * P))\n//                     <i> F_cco = (F_in * M * 2 * P)\n//                     <i> F_in  must be in the range of 1 MHz to 25 MHz\n//                     <i> F_cco must be in the range of 9.75 MHz to 160 MHz\n//       <o4.0..4>   MSEL: PLL Multiplier Selection\n//                     <i> M Value\n//                     <1-32><#-1>\n//       <o4.5..6> PSEL: PLL Divider Selection\n//                     <i> P Value\n//                     <0=> 1\n//                     <1=> 2\n//                     <2=> 4\n//                     <3=> 8\n//     </h>\n//   </e>\n//\n//   <e5> PLL1 Configuration (Alt PLL)\n//     <h> PLL1 Configuration Register (PLL1CFG)\n//                     <i> PLL out clock = (F_cco / (2 * P))\n//                     <i> F_cco = (F_in * M * 2 * P)\n//                     <i> F_in  must be in the range of 1 MHz to 25 MHz\n//                     <i> F_cco must be in the range of 9.75 MHz to 160 MHz\n//       <o6.0..4>   MSEL: PLL Multiplier Selection\n//                     <i> M Value\n//                     <1-32><#-1>\n//       <o6.5..6> PSEL: PLL Divider Selection\n//                     <i> P Value\n//                     <0=> 1\n//                     <1=> 2\n//                     <2=> 4\n//                     <3=> 8\n//     </h>\n//   </e>\n//\n//   <h> CPU Clock Selection Register (CCLKSEL)\n//     <o7.0..4>    CCLKDIV: CPU clock (CCLK) divider\n//                     <i> 0: The divider is turned off. No clock will be provided to the CPU\n//                     <i> n: The input clock is divided by n to produce the CPU clock\n//                     <0-31>\n//     <o7.8>       CCLKSEL: CPU clock divider input clock selection\n//                     <0=> sysclk clock\n//                     <1=> PLL0 clock\n//   </h>\n//\n//   <h> USB Clock Selection Register (USBCLKSEL)\n//     <o8.0..4>    USBDIV: USB clock (source PLL0) divider selection\n//                     <0=> USB clock off\n//                     <4=> PLL0 / 4 (PLL0 must be 192Mhz)\n//                     <6=> PLL0 / 6 (PLL0 must be 288Mhz)\n//     <o8.8..9>    USBSEL: USB clock divider input clock selection\n//                     <i> When CPU clock is selected, the USB can be accessed\n//                     <i> by software but cannot perform USB functions\n//                     <0=> CPU clock\n//                     <1=> PLL0 clock\n//                     <2=> PLL1 clock\n//   </h>\n//\n//   <h> EMC Clock Selection Register (EMCCLKSEL)\n//     <o9.0>       EMCDIV: EMC clock selection\n//                     <0=> CPU clock\n//                     <1=> CPU clock / 2\n//   </h>\n//\n//   <h> Peripheral Clock Selection Register (PCLKSEL)\n//     <o10.0..4>   PCLKDIV: APB Peripheral clock divider\n//                     <i> 0: The divider is turned off. No clock will be provided to APB peripherals\n//                     <i> n: The input clock is divided by n to produce the APB peripheral clock\n//                     <0-31>\n//   </h>\n//\n//   <h> Power Control for Peripherals Register (PCONP)\n//     <o11.0>      PCLCD: LCD controller power/clock enable\n//     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable\n//     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable\n//     <o11.3>      PCUART0: UART 0 power/clock enable\n//     <o11.4>      PCUART1: UART 1 power/clock enable\n//     <o11.5>      PCPWM0: PWM0 power/clock enable\n//     <o11.6>      PCPWM1: PWM1 power/clock enable\n//     <o11.7>      PCI2C0: I2C 0 interface power/clock enable\n//     <o11.8>      PCUART4: UART 4 power/clock enable\n//     <o11.9>      PCRTC: RTC and Event Recorder power/clock enable\n//     <o11.10>     PCSSP1: SSP 1 interface power/clock enable\n//     <o11.11>     PCEMC: External Memory Controller power/clock enable\n//     <o11.12>     PCADC: A/D converter power/clock enable\n//     <o11.13>     PCCAN1: CAN controller 1 power/clock enable\n//     <o11.14>     PCCAN2: CAN controller 2 power/clock enable\n//     <o11.15>     PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable\n//     <o11.17>     PCMCPWM: Motor Control PWM power/clock enable\n//     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable\n//     <o11.19>     PCI2C1: I2C 1 interface power/clock enable\n//     <o11.20>     PCSSP2: SSP 2 interface power/clock enable\n//     <o11.21>     PCSSP0: SSP 0 interface power/clock enable\n//     <o11.22>     PCTIM2: Timer 2 power/clock enable\n//     <o11.23>     PCTIM3: Timer 3 power/clock enable\n//     <o11.24>     PCUART2: UART 2 power/clock enable\n//     <o11.25>     PCUART3: UART 3 power/clock enable\n//     <o11.26>     PCI2C2: I2C 2 interface power/clock enable\n//     <o11.27>     PCI2S: I2S interface power/clock enable\n//     <o11.28>     PCSDC: SD Card interface power/clock enable\n//     <o11.29>     PCGPDMA: GPDMA function power/clock enable\n//     <o11.30>     PCENET: Ethernet block power/clock enable\n//     <o11.31>     PCUSB: USB interface power/clock enable\n//   </h>\n//\n//   <h> Clock Output Configuration Register (CLKOUTCFG)\n//     <o12.0..3>   CLKOUTSEL: Clock Source for CLKOUT Selection\n//                     <0=> CPU clock\n//                     <1=> Main Oscillator\n//                     <2=> Internal RC Oscillator\n//                     <3=> USB clock\n//                     <4=> RTC Oscillator\n//                     <5=> unused\n//                     <6=> Watchdog Oscillator\n//     <o12.4..7>   CLKOUTDIV: Output Clock Divider\n//                     <1-16><#-1>\n//     <o12.8>      CLKOUT_EN: CLKOUT enable\n//   </h>\n//\n// </e>\n*/\n#define CLOCK_SETUP           1\n#define SCS_Val               0x00000021\n#define CLKSRCSEL_Val         0x00000001\n#define PLL0_SETUP            1\n#define PLL0CFG_Val           0x00000009\n#define PLL1_SETUP            1\n#define PLL1CFG_Val           0x00000023\n#define CCLKSEL_Val           (0x00000001|(1<<8))\n#define USBCLK_SETUP\t\t  1\n#define USBCLKSEL_Val         (0x00000001|(0x02<<8))\n#define EMCCLKSEL_Val         0x00000001\n#define PCLKSEL_Val           0x00000002\n#define PCONP_Val             0x042887DE\n#define CLKOUTCFG_Val         0x00000100\n\n\n/*--------------------- Flash Accelerator Configuration ----------------------\n//\n// <e> Flash Accelerator Configuration\n//   <o1.12..15> FLASHTIM: Flash Access Time\n//               <0=> 1 CPU clock (for CPU clock up to 20 MHz)\n//               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)\n//               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)\n//               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)\n//               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)\n//               <5=> 6 CPU clocks (for any CPU clock)\n// </e>\n*/\n#define FLASH_SETUP           1\n#define FLASHCFG_Val          0x00005000\n\n/*----------------------------------------------------------------------------\n  Check the register settings\n *----------------------------------------------------------------------------*/\n#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))\n#define CHECK_RSVD(val, mask)                     (val & mask)\n\n/* Clock Configuration -------------------------------------------------------*/\n#if (CHECK_RSVD((SCS_Val),       ~0x0000003F))\n   #error \"SCS: Invalid values of reserved bits!\"\n#endif\n\n#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))\n   #error \"CLKSRCSEL: Value out of range!\"\n#endif\n\n#if (CHECK_RSVD((PLL0CFG_Val),   ~0x0000007F))\n   #error \"PLL0CFG: Invalid values of reserved bits!\"\n#endif\n\n#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))\n   #error \"PLL1CFG: Invalid values of reserved bits!\"\n#endif\n\n#if (CHECK_RSVD((CCLKSEL_Val),   ~0x0000011F))\n   #error \"CCLKSEL: Invalid values of reserved bits!\"\n#endif\n\n#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))\n   #error \"USBCLKSEL: Invalid values of reserved bits!\"\n#endif\n\n#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))\n   #error \"EMCCLKSEL: Invalid values of reserved bits!\"\n#endif\n\n#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))\n   #error \"PCLKSEL: Invalid values of reserved bits!\"\n#endif\n\n#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))\n   #error \"PCONP: Invalid values of reserved bits!\"\n#endif\n\n#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))\n   #error \"CLKOUTCFG: Invalid values of reserved bits!\"\n#endif\n\n/* Flash Accelerator Configuration -------------------------------------------*/\n#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))\n   #warning \"FLASHCFG: Invalid values of reserved bits!\"\n#endif\n\n\n/*----------------------------------------------------------------------------\n  DEFINES\n *----------------------------------------------------------------------------*/\n/* pll_out_clk = F_cco / (2  P)\n   F_cco = pll_in_clk  M  2  P */\n#define __M                   ((PLL0CFG_Val & 0x1F) + 1)\n#define __PLL0_CLK(__F_IN)    (__F_IN * __M)\n#define __CCLK_DIV            (CCLKSEL_Val & 0x1F)\n#define __PCLK_DIV\t\t\t  (PCLKSEL_Val & 0x1F)\n#define __ECLK_DIV\t\t\t  ((EMCCLKSEL_Val & 0x01) + 1)\n\n/* Determine core clock frequency according to settings */\n#if (CLOCK_SETUP)                       /* Clock Setup                        */\n\n  #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)\n   #error \"Main Oscillator is selected as clock source but is not enabled!\"\n  #endif\n\n  #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)\n   #error \"Main PLL is selected as clock source but is not enabled!\"\n  #endif\n\n  #if ((CCLKSEL_Val & 0x100) == 0)      /* cclk = sysclk */\n    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */\n        #define __CORE_CLK (IRC_OSC / __CCLK_DIV)\n\t\t#define __PER_CLK  (IRC_OSC/  __PCLK_DIV)\n        #define __EMC_CLK  (IRC_OSC/  __ECLK_DIV)\n    #else                               /* sysclk = osc_clk */\n        #define __CORE_CLK (OSC_CLK / __CCLK_DIV)\n        #define __PER_CLK  (OSC_CLK/  __PCLK_DIV)\n        #define __EMC_CLK  (OSC_CLK/  __ECLK_DIV)\n    #endif\n  #else                                 /* cclk = pll_clk */\n    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */\n        #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)\n        #define __PER_CLK  (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)\n        #define __EMC_CLK  (__PLL0_CLK(IRC_OSC) / __ECLK_DIV)\n    #else                               /* sysclk = osc_clk */\n        #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)\n        #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)\n\t\t#define __EMC_CLK  (__PLL0_CLK(OSC_CLK) / __ECLK_DIV)\n    #endif\n  #endif\n\n#else\n        #define __CORE_CLK (IRC_OSC)\n        #define __PER_CLK  (IRC_OSC)\n        #define __EMC_CLK  (IRC_OSC)\n#endif\n\n/*----------------------------------------------------------------------------\n  Clock Variable definitions\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/\nuint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk)  */\nuint32_t EMCClock\t\t = __EMC_CLK; /*!< EMC Clock Frequency \t\t\t\t  */\nuint32_t USBClock \t\t = (48000000UL);\t\t  /*!< USB Clock Frequency - this value will\n\t\t\t\t\t\t\t\t\tbe updated after call SystemCoreClockUpdate, should be 48MHz*/\n\n\n/*----------------------------------------------------------------------------\n  Clock functions\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */\n{\n  /* Determine clock frequency according to clock register values             */\n  if ((LPC_SC->CCLKSEL &0x100) == 0) {            /* cclk = sysclk    */\n    if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */\n          SystemCoreClock = (IRC_OSC / (LPC_SC->CCLKSEL & 0x1F));\n          PeripheralClock = (IRC_OSC / (LPC_SC->PCLKSEL & 0x1F));\n          EMCClock        = (IRC_OSC / ((LPC_SC->EMCCLKSEL & 0x01)+1));\n    }\n    else {                                        /* sysclk = osc_clk */\n      if ((LPC_SC->SCS & 0x40) == 0) {\n          SystemCoreClock = 0;                      /* this should never happen! */\n          PeripheralClock = 0;\n          EMCClock        = 0;\n      }\n      else {\n          SystemCoreClock = (OSC_CLK / (LPC_SC->CCLKSEL & 0x1F));\n          PeripheralClock = (OSC_CLK / (LPC_SC->PCLKSEL & 0x1F));\n          EMCClock        = (OSC_CLK / ((LPC_SC->EMCCLKSEL & 0x01)+1));\n      }\n    }\n  }\n  else {                                          /* cclk = pll_clk */\n    if ((LPC_SC->PLL0STAT & 0x100) == 0) {        /* PLL0 not enabled */\n          SystemCoreClock = 0;                      /* this should never happen! */\n          PeripheralClock = 0;\n          EMCClock \t\t  = 0;\n    }\n    else {\n      if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */\n          SystemCoreClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));\n          PeripheralClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));\n          EMCClock        = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));\n      }\n      else {                                        /* sysclk = osc_clk */\n        if ((LPC_SC->SCS & 0x40) == 0) {\n          SystemCoreClock = 0;                      /* this should never happen! */\n          PeripheralClock = 0;\n          EMCClock \t\t  = 0;\n        }\n        else {\n          SystemCoreClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));\n          PeripheralClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));\n          EMCClock        = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));\n        }\n      }\n    }\n  }\n  /* ---update USBClock------------------*/\n  if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider\n  {\n\t  switch (LPC_SC->USBCLKSEL & 0x1F)\n\t  {\n\t  case 0:\n\t\t  USBClock = 0; //no clock will be provided to the USB subsystem\n\t\t  break;\n\t  case 4:\n\t  case 6:\n\t\t  if(LPC_SC->CLKSRCSEL & 0x01)\t//pll_clk_in = main_osc\n\t\t\t  USBClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));\n\t\t  else //pll_clk_in = irc_clk\n\t\t\t  USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));\n\t\t  break;\n\t  default:\n\t\t  USBClock = 0;  /* this should never happen! */\n\t  }\n  }\n  else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)\n  {\n\t  if(LPC_SC->CLKSRCSEL & 0x01)\t//pll1_clk_in = main_osc\n\t  \t\tUSBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));\n\t  else //pll1_clk_in = irc_clk\n\t  \t\tUSBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));\n  }\n  else\n\t  USBClock = 0; /* this should never happen! */\n}\n\n  /* Determine clock frequency according to clock register values             */\n\n/**\n * Initialize the system\n *\n * @param  none\n * @return none\n *\n * @brief  Setup the microcontroller system.\n *         Initialize the System.\n */\nvoid SystemInit (void)\n{\n#if (CLOCK_SETUP)                       /* Clock Setup                        */\n  LPC_SC->SCS       = SCS_Val;\n  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */\n    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */\n  }\n\n  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for sysclk/PLL0*/\n\n#if (PLL0_SETUP)\n  LPC_SC->PLL0CFG   = PLL0CFG_Val;\n  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */\n  LPC_SC->PLL0FEED  = 0xAA;\n  LPC_SC->PLL0FEED  = 0x55;\n  while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0                    */\n#endif\n\n#if (PLL1_SETUP)\n  LPC_SC->PLL1CFG   = PLL1CFG_Val;\n  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */\n  LPC_SC->PLL1FEED  = 0xAA;\n  LPC_SC->PLL1FEED  = 0x55;\n  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */\n#endif\n\n  LPC_SC->CCLKSEL   = CCLKSEL_Val;      /* Setup Clock Divider                */\n  LPC_SC->USBCLKSEL = USBCLKSEL_Val;    /* Setup USB Clock Divider            */\n  LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;    /* EMC Clock Selection                */\n  LPC_SC->PCLKSEL   = PCLKSEL_Val;      /* Peripheral Clock Selection         */\n  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */\n  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */\n#endif\n\n#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */\n  LPC_SC->FLASHCFG  = FLASHCFG_Val|0x03A;\n#endif\n#ifdef  __RAM_MODE__\n  SCB->VTOR  = 0x10000000 & 0x3FFFFF80;\n#else\n  SCB->VTOR  = 0x00000000 & 0x3FFFFF80;\n#endif\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/Include/cmsis_os2.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        3. April 2023\n * $Revision:    V2.2.0\n *\n * Project:      CMSIS-RTOS2 API\n * Title:        cmsis_os2.h header file\n *\n * Version 2.2.0\n *    Added support for Process Isolation (Functional Safety):\n *    - Kernel Management: osKernelProtect, osKernelDestroyClass\n *    - Thread Management: osThreadGetClass, osThreadGetZone,\n *                         osThreadSuspendClass, osThreadResumeClass\n *                         osThreadTerminateZone,\n *                         osThreadFeedWatchdog,\n *                         osThreadProtectPrivileged\n *    - Thread attributes: osThreadZone, osThreadUnprivileged/osThreadPrivileged\n *    - Object attributes: osSafetyClass\n *    - Handler functions: osWatchdogAlarm_Handler\n *    - Zone Management: osZoneSetup_Callback\n *    - Exception Faults: osFaultResume\n *    Additional functions allowed to be called from Interrupt Service Routines:\n *    - osThreadGetName, osTimerGetName, osEventFlagsGetName, osMutexGetName,\n *      osSemaphoreGetName, osMemoryPoolGetName, osMessageQueueGetName\n * Version 2.1.3\n *    Additional functions allowed to be called from Interrupt Service Routines:\n *    - osThreadGetId\n * Version 2.1.2\n *    Additional functions allowed to be called from Interrupt Service Routines:\n *    - osKernelGetInfo, osKernelGetState\n * Version 2.1.1\n *    Additional functions allowed to be called from Interrupt Service Routines:\n *    - osKernelGetTickCount, osKernelGetTickFreq\n *    Changed Kernel Tick type to uint32_t:\n *    - updated: osKernelGetTickCount, osDelayUntil\n * Version 2.1.0\n *    Support for critical and uncritical sections (nesting safe):\n *    - updated: osKernelLock, osKernelUnlock\n *    - added: osKernelRestoreLock\n *    Updated Thread and Event Flags:\n *    - changed flags parameter and return type from int32_t to uint32_t\n * Version 2.0.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n \n#ifndef CMSIS_OS2_H_\n#define CMSIS_OS2_H_\n \n#ifndef __NO_RETURN\n#if   defined(__CC_ARM)\n#define __NO_RETURN __declspec(noreturn)\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define __NO_RETURN __attribute__((__noreturn__))\n#elif defined(__GNUC__)\n#define __NO_RETURN __attribute__((__noreturn__))\n#elif defined(__ICCARM__)\n#define __NO_RETURN __noreturn\n#else\n#define __NO_RETURN\n#endif\n#endif\n \n#include <stdint.h>\n#include <stddef.h>\n \n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n \n \n//  ==== Enumerations, structures, defines ====\n \n/// Version information.\ntypedef struct {\n  uint32_t                       api;   ///< API version (major.minor.rev: mmnnnrrrr dec).\n  uint32_t                    kernel;   ///< Kernel version (major.minor.rev: mmnnnrrrr dec).\n} osVersion_t;\n \n/// Kernel state.\ntypedef enum {\n  osKernelInactive        =  0,         ///< Inactive.\n  osKernelReady           =  1,         ///< Ready.\n  osKernelRunning         =  2,         ///< Running.\n  osKernelLocked          =  3,         ///< Locked.\n  osKernelSuspended       =  4,         ///< Suspended.\n  osKernelError           = -1,         ///< Error.\n  osKernelReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osKernelState_t;\n \n/// Thread state.\ntypedef enum {\n  osThreadInactive        =  0,         ///< Inactive.\n  osThreadReady           =  1,         ///< Ready.\n  osThreadRunning         =  2,         ///< Running.\n  osThreadBlocked         =  3,         ///< Blocked.\n  osThreadTerminated      =  4,         ///< Terminated.\n  osThreadError           = -1,         ///< Error.\n  osThreadReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osThreadState_t;\n \n/// Priority values.\ntypedef enum {\n  osPriorityNone          =  0,         ///< No priority (not initialized).\n  osPriorityIdle          =  1,         ///< Reserved for Idle thread.\n  osPriorityLow           =  8,         ///< Priority: low\n  osPriorityLow1          =  8+1,       ///< Priority: low + 1\n  osPriorityLow2          =  8+2,       ///< Priority: low + 2\n  osPriorityLow3          =  8+3,       ///< Priority: low + 3\n  osPriorityLow4          =  8+4,       ///< Priority: low + 4\n  osPriorityLow5          =  8+5,       ///< Priority: low + 5\n  osPriorityLow6          =  8+6,       ///< Priority: low + 6\n  osPriorityLow7          =  8+7,       ///< Priority: low + 7\n  osPriorityBelowNormal   = 16,         ///< Priority: below normal\n  osPriorityBelowNormal1  = 16+1,       ///< Priority: below normal + 1\n  osPriorityBelowNormal2  = 16+2,       ///< Priority: below normal + 2\n  osPriorityBelowNormal3  = 16+3,       ///< Priority: below normal + 3\n  osPriorityBelowNormal4  = 16+4,       ///< Priority: below normal + 4\n  osPriorityBelowNormal5  = 16+5,       ///< Priority: below normal + 5\n  osPriorityBelowNormal6  = 16+6,       ///< Priority: below normal + 6\n  osPriorityBelowNormal7  = 16+7,       ///< Priority: below normal + 7\n  osPriorityNormal        = 24,         ///< Priority: normal\n  osPriorityNormal1       = 24+1,       ///< Priority: normal + 1\n  osPriorityNormal2       = 24+2,       ///< Priority: normal + 2\n  osPriorityNormal3       = 24+3,       ///< Priority: normal + 3\n  osPriorityNormal4       = 24+4,       ///< Priority: normal + 4\n  osPriorityNormal5       = 24+5,       ///< Priority: normal + 5\n  osPriorityNormal6       = 24+6,       ///< Priority: normal + 6\n  osPriorityNormal7       = 24+7,       ///< Priority: normal + 7\n  osPriorityAboveNormal   = 32,         ///< Priority: above normal\n  osPriorityAboveNormal1  = 32+1,       ///< Priority: above normal + 1\n  osPriorityAboveNormal2  = 32+2,       ///< Priority: above normal + 2\n  osPriorityAboveNormal3  = 32+3,       ///< Priority: above normal + 3\n  osPriorityAboveNormal4  = 32+4,       ///< Priority: above normal + 4\n  osPriorityAboveNormal5  = 32+5,       ///< Priority: above normal + 5\n  osPriorityAboveNormal6  = 32+6,       ///< Priority: above normal + 6\n  osPriorityAboveNormal7  = 32+7,       ///< Priority: above normal + 7\n  osPriorityHigh          = 40,         ///< Priority: high\n  osPriorityHigh1         = 40+1,       ///< Priority: high + 1\n  osPriorityHigh2         = 40+2,       ///< Priority: high + 2\n  osPriorityHigh3         = 40+3,       ///< Priority: high + 3\n  osPriorityHigh4         = 40+4,       ///< Priority: high + 4\n  osPriorityHigh5         = 40+5,       ///< Priority: high + 5\n  osPriorityHigh6         = 40+6,       ///< Priority: high + 6\n  osPriorityHigh7         = 40+7,       ///< Priority: high + 7\n  osPriorityRealtime      = 48,         ///< Priority: realtime\n  osPriorityRealtime1     = 48+1,       ///< Priority: realtime + 1\n  osPriorityRealtime2     = 48+2,       ///< Priority: realtime + 2\n  osPriorityRealtime3     = 48+3,       ///< Priority: realtime + 3\n  osPriorityRealtime4     = 48+4,       ///< Priority: realtime + 4\n  osPriorityRealtime5     = 48+5,       ///< Priority: realtime + 5\n  osPriorityRealtime6     = 48+6,       ///< Priority: realtime + 6\n  osPriorityRealtime7     = 48+7,       ///< Priority: realtime + 7\n  osPriorityISR           = 56,         ///< Reserved for ISR deferred thread.\n  osPriorityError         = -1,         ///< System cannot determine priority or illegal priority.\n  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osPriority_t;\n \n/// Entry point of a thread.\ntypedef void (*osThreadFunc_t) (void *argument);\n \n/// Timer callback function.\ntypedef void (*osTimerFunc_t) (void *argument);\n \n/// Timer type.\ntypedef enum {\n  osTimerOnce             = 0,          ///< One-shot timer.\n  osTimerPeriodic         = 1           ///< Repeating timer.\n} osTimerType_t;\n \n// Timeout value.\n#define osWaitForever           0xFFFFFFFFU ///< Wait forever timeout value.\n \n// Flags options (\\ref osThreadFlagsWait and \\ref osEventFlagsWait).\n#define osFlagsWaitAny          0x00000000U ///< Wait for any flag (default).\n#define osFlagsWaitAll          0x00000001U ///< Wait for all flags.\n#define osFlagsNoClear          0x00000002U ///< Do not clear flags which have been specified to wait for.\n \n// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).\n#define osFlagsError            0x80000000U ///< Error indicator.\n#define osFlagsErrorUnknown     0xFFFFFFFFU ///< osError (-1).\n#define osFlagsErrorTimeout     0xFFFFFFFEU ///< osErrorTimeout (-2).\n#define osFlagsErrorResource    0xFFFFFFFDU ///< osErrorResource (-3).\n#define osFlagsErrorParameter   0xFFFFFFFCU ///< osErrorParameter (-4).\n#define osFlagsErrorISR         0xFFFFFFFAU ///< osErrorISR (-6).\n#define osFlagsErrorSafetyClass 0xFFFFFFF9U ///< osErrorSafetyClass (-7).\n \n// Thread attributes (attr_bits in \\ref osThreadAttr_t).\n#define osThreadDetached        0x00000000U ///< Thread created in detached mode (default)\n#define osThreadJoinable        0x00000001U ///< Thread created in joinable mode\n#define osThreadUnprivileged    0x00000002U ///< Thread runs in unprivileged mode\n#define osThreadPrivileged      0x00000004U ///< Thread runs in privileged mode\n \n#define osThreadZone_Pos        8U                            ///< MPU protected zone position\n#define osThreadZone_Msk        (0x3FUL << osThreadZone_Pos)  ///< MPU protected zone mask\n#define osThreadZone_Valid      (0x80UL << osThreadZone_Pos)  ///< MPU protected zone valid flag\n#define osThreadZone(n)         ((((n) << osThreadZone_Pos) & osThreadZone_Msk) | \\\n                                 osThreadZone_Valid)          ///< MPU protected zone\n \n// Mutex attributes (attr_bits in \\ref osMutexAttr_t).\n#define osMutexRecursive        0x00000001U ///< Recursive mutex.\n#define osMutexPrioInherit      0x00000002U ///< Priority inherit protocol.\n#define osMutexRobust           0x00000008U ///< Robust mutex.\n \n// Object attributes (attr_bits in all objects)\n#define osSafetyClass_Pos       16U                           ///< Safety class position\n#define osSafetyClass_Msk       (0x0FUL << osSafetyClass_Pos) ///< Safety class mask\n#define osSafetyClass_Valid     (0x10UL << osSafetyClass_Pos) ///< Safety class valid flag\n#define osSafetyClass(n)        ((((n) << osSafetyClass_Pos) & osSafetyClass_Msk) | \\\n                                 osSafetyClass_Valid)         ///< Safety class\n \n// Safety mode (\\ref osThreadSuspendClass, \\ref osThreadResumeClass and \\ref osKernelDestroyClass).\n#define osSafetyWithSameClass   0x00000001U ///< Objects with same safety class.\n#define osSafetyWithLowerClass  0x00000002U ///< Objects with lower safety class.\n \n// Error indication (returned by \\ref osThreadGetClass and \\ref osThreadGetZone).\n#define osErrorId               0xFFFFFFFFU ///< osError (-1).\n \n/// Status code values returned by CMSIS-RTOS functions.\ntypedef enum {\n  osOK                    =  0,         ///< Operation completed successfully.\n  osError                 = -1,         ///< Unspecified RTOS error: run-time error but no other error message fits.\n  osErrorTimeout          = -2,         ///< Operation not completed within the timeout period.\n  osErrorResource         = -3,         ///< Resource not available.\n  osErrorParameter        = -4,         ///< Parameter error.\n  osErrorNoMemory         = -5,         ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorISR              = -6,         ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osErrorSafetyClass      = -7,         ///< Operation denied because of safety class violation.\n  osStatusReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osStatus_t;\n \n \n/// \\details Thread ID identifies the thread.\ntypedef void *osThreadId_t;\n \n/// \\details Timer ID identifies the timer.\ntypedef void *osTimerId_t;\n \n/// \\details Event Flags ID identifies the event flags.\ntypedef void *osEventFlagsId_t;\n \n/// \\details Mutex ID identifies the mutex.\ntypedef void *osMutexId_t;\n \n/// \\details Semaphore ID identifies the semaphore.\ntypedef void *osSemaphoreId_t;\n \n/// \\details Memory Pool ID identifies the memory pool.\ntypedef void *osMemoryPoolId_t;\n \n/// \\details Message Queue ID identifies the message queue.\ntypedef void *osMessageQueueId_t;\n \n \n#ifndef TZ_MODULEID_T\n#define TZ_MODULEID_T\n/// \\details Data type that identifies secure software modules called by a process.\ntypedef uint32_t TZ_ModuleId_t;\n#endif\n \n \n/// Attributes structure for thread.\ntypedef struct {\n  const char                   *name;   ///< name of the thread\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n  void                   *stack_mem;    ///< memory for stack\n  uint32_t                stack_size;   ///< size of stack\n  osPriority_t              priority;   ///< initial thread priority (default: osPriorityNormal)\n  TZ_ModuleId_t            tz_module;   ///< TrustZone module identifier\n  uint32_t                  reserved;   ///< reserved (must be 0)\n} osThreadAttr_t;\n \n/// Attributes structure for timer.\ntypedef struct {\n  const char                   *name;   ///< name of the timer\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osTimerAttr_t;\n \n/// Attributes structure for event flags.\ntypedef struct {\n  const char                   *name;   ///< name of the event flags\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osEventFlagsAttr_t;\n \n/// Attributes structure for mutex.\ntypedef struct {\n  const char                   *name;   ///< name of the mutex\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osMutexAttr_t;\n \n/// Attributes structure for semaphore.\ntypedef struct {\n  const char                   *name;   ///< name of the semaphore\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osSemaphoreAttr_t;\n \n/// Attributes structure for memory pool.\ntypedef struct {\n  const char                   *name;   ///< name of the memory pool\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n  void                      *mp_mem;    ///< memory for data storage\n  uint32_t                   mp_size;   ///< size of provided memory for data storage \n} osMemoryPoolAttr_t;\n \n/// Attributes structure for message queue.\ntypedef struct {\n  const char                   *name;   ///< name of the message queue\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n  void                      *mq_mem;    ///< memory for data storage\n  uint32_t                   mq_size;   ///< size of provided memory for data storage \n} osMessageQueueAttr_t;\n \n \n//  ==== Kernel Management Functions ====\n \n/// Initialize the RTOS Kernel.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelInitialize (void);\n \n///  Get RTOS Kernel Information.\n/// \\param[out]    version       pointer to buffer for retrieving version information.\n/// \\param[out]    id_buf        pointer to buffer for retrieving kernel identification string.\n/// \\param[in]     id_size       size of buffer for kernel identification string.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);\n \n/// Get the current RTOS Kernel state.\n/// \\return current RTOS Kernel state.\nosKernelState_t osKernelGetState (void);\n \n/// Start the RTOS Kernel scheduler.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelStart (void);\n \n/// Lock the RTOS Kernel scheduler.\n/// \\return previous lock state (1 - locked, 0 - not locked, error code if negative).\nint32_t osKernelLock (void);\n \n/// Unlock the RTOS Kernel scheduler.\n/// \\return previous lock state (1 - locked, 0 - not locked, error code if negative).\nint32_t osKernelUnlock (void);\n \n/// Restore the RTOS Kernel scheduler lock state.\n/// \\param[in]     lock          lock state obtained by \\ref osKernelLock or \\ref osKernelUnlock.\n/// \\return new lock state (1 - locked, 0 - not locked, error code if negative).\nint32_t osKernelRestoreLock (int32_t lock);\n \n/// Suspend the RTOS Kernel scheduler.\n/// \\return time in ticks, for how long the system can sleep or power-down.\nuint32_t osKernelSuspend (void);\n \n/// Resume the RTOS Kernel scheduler.\n/// \\param[in]     sleep_ticks   time in ticks for how long the system was in sleep or power-down mode.\nvoid osKernelResume (uint32_t sleep_ticks);\n \n/// Protect the RTOS Kernel scheduler access.\n/// \\param[in]     safety_class  safety class.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelProtect (uint32_t safety_class);\n \n/// Destroy objects for specified safety classes.\n/// \\param[in]     safety_class  safety class.\n/// \\param[in]     mode          safety mode.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelDestroyClass (uint32_t safety_class, uint32_t mode); \n \n/// Get the RTOS kernel tick count.\n/// \\return RTOS kernel current tick count.\nuint32_t osKernelGetTickCount (void);\n \n/// Get the RTOS kernel tick frequency.\n/// \\return frequency of the kernel tick in hertz, i.e. kernel ticks per second.\nuint32_t osKernelGetTickFreq (void);\n \n/// Get the RTOS kernel system timer count.\n/// \\return RTOS kernel current system timer count as 32-bit value.\nuint32_t osKernelGetSysTimerCount (void);\n \n/// Get the RTOS kernel system timer frequency.\n/// \\return frequency of the system timer in hertz, i.e. timer ticks per second.\nuint32_t osKernelGetSysTimerFreq (void);\n \n \n//  ==== Thread Management Functions ====\n \n/// Create a thread and add it to Active Threads.\n/// \\param[in]     func          thread function.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\param[in]     attr          thread attributes; NULL: default values.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);\n \n/// Get name of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return name as null-terminated string.\nconst char *osThreadGetName (osThreadId_t thread_id);\n \n/// Get safety class of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return safety class of the specified thread.\nuint32_t osThreadGetClass (osThreadId_t thread_id);\n \n/// Get MPU protected zone of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return MPU protected zone of the specified thread.\nuint32_t osThreadGetZone (osThreadId_t thread_id);\n \n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId_t osThreadGetId (void);\n \n/// Get current thread state of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return current thread state of the specified thread.\nosThreadState_t osThreadGetState (osThreadId_t thread_id);\n \n/// Get stack size of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return stack size in bytes.\nuint32_t osThreadGetStackSize (osThreadId_t thread_id);\n \n/// Get available stack space of a thread based on stack watermark recording during execution.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return remaining stack space in bytes.\nuint32_t osThreadGetStackSpace (osThreadId_t thread_id);\n \n/// Change priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);\n \n/// Get current priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return current priority value of the specified thread.\nosPriority_t osThreadGetPriority (osThreadId_t thread_id);\n \n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadYield (void);\n \n/// Suspend execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadSuspend (osThreadId_t thread_id);\n \n/// Resume execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadResume (osThreadId_t thread_id);\n \n/// Detach a thread (thread storage can be reclaimed when thread terminates).\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadDetach (osThreadId_t thread_id);\n \n/// Wait for specified thread to terminate.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadJoin (osThreadId_t thread_id);\n \n/// Terminate execution of current running thread.\n__NO_RETURN void osThreadExit (void);\n \n/// Terminate execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadTerminate (osThreadId_t thread_id);\n \n/// Feed watchdog of the current running thread.\n/// \\param[in]     ticks         \\ref kernelTimer \"time ticks\" value until the thread watchdog expires, or 0 to stop the watchdog\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadFeedWatchdog (uint32_t ticks);\n \n/// Protect creation of privileged threads.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadProtectPrivileged (void);\n \n/// Suspend execution of threads for specified safety classes.\n/// \\param[in]     safety_class  safety class.\n/// \\param[in]     mode          safety mode.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadSuspendClass (uint32_t safety_class, uint32_t mode);\n \n/// Resume execution of threads for specified safety classes.\n/// \\param[in]     safety_class  safety class.\n/// \\param[in]     mode          safety mode.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadResumeClass (uint32_t safety_class, uint32_t mode);\n \n/// Terminate execution of threads assigned to a specified MPU protected zone.\n/// \\param[in]     zone          MPU protected zone.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadTerminateZone (uint32_t zone);\n \n/// Get number of active threads.\n/// \\return number of active threads.\nuint32_t osThreadGetCount (void);\n \n/// Enumerate active threads.\n/// \\param[out]    thread_array  pointer to array for retrieving thread IDs.\n/// \\param[in]     array_items   maximum number of items in array for retrieving thread IDs.\n/// \\return number of enumerated threads.\nuint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);\n \n \n//  ==== Thread Flags Functions ====\n \n/// Set the specified Thread Flags of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\param[in]     flags         specifies the flags of the thread that shall be set.\n/// \\return thread flags after setting or error code if highest bit set.\nuint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);\n \n/// Clear the specified Thread Flags of current running thread.\n/// \\param[in]     flags         specifies the flags of the thread that shall be cleared.\n/// \\return thread flags before clearing or error code if highest bit set.\nuint32_t osThreadFlagsClear (uint32_t flags);\n \n/// Get the current Thread Flags of current running thread.\n/// \\return current thread flags.\nuint32_t osThreadFlagsGet (void);\n \n/// Wait for one or more Thread Flags of the current running thread to become signaled.\n/// \\param[in]     flags         specifies the flags to wait for.\n/// \\param[in]     options       specifies flags options (osFlagsXxxx).\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return thread flags before clearing or error code if highest bit set.\nuint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);\n \n \n//  ==== Generic Wait Functions ====\n \n/// Wait for Timeout (Time Delay).\n/// \\param[in]     ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osDelay (uint32_t ticks);\n \n/// Wait until specified time.\n/// \\param[in]     ticks         absolute time in ticks\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osDelayUntil (uint32_t ticks);\n \n \n//  ==== Timer Management Functions ====\n \n/// Create and Initialize a timer.\n/// \\param[in]     func          function pointer to callback function.\n/// \\param[in]     type          \\ref osTimerOnce for one-shot or \\ref osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer callback function.\n/// \\param[in]     attr          timer attributes; NULL: default values.\n/// \\return timer ID for reference by other functions or NULL in case of error.\nosTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);\n \n/// Get name of a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return name as null-terminated string.\nconst char *osTimerGetName (osTimerId_t timer_id);\n \n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\param[in]     ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value of the timer.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);\n \n/// Stop a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osTimerStop (osTimerId_t timer_id);\n \n/// Check if a timer is running.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return 0 not running, 1 running.\nuint32_t osTimerIsRunning (osTimerId_t timer_id);\n \n/// Delete a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osTimerDelete (osTimerId_t timer_id);\n \n \n//  ==== Event Flags Management Functions ====\n \n/// Create and Initialize an Event Flags object.\n/// \\param[in]     attr          event flags attributes; NULL: default values.\n/// \\return event flags ID for reference by other functions or NULL in case of error.\nosEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);\n \n/// Get name of an Event Flags object.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\return name as null-terminated string.\nconst char *osEventFlagsGetName (osEventFlagsId_t ef_id);\n \n/// Set the specified Event Flags.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\param[in]     flags         specifies the flags that shall be set.\n/// \\return event flags after setting or error code if highest bit set.\nuint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);\n \n/// Clear the specified Event Flags.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\param[in]     flags         specifies the flags that shall be cleared.\n/// \\return event flags before clearing or error code if highest bit set.\nuint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);\n \n/// Get the current Event Flags.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\return current event flags.\nuint32_t osEventFlagsGet (osEventFlagsId_t ef_id);\n \n/// Wait for one or more Event Flags to become signaled.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\param[in]     flags         specifies the flags to wait for.\n/// \\param[in]     options       specifies flags options (osFlagsXxxx).\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event flags before clearing or error code if highest bit set.\nuint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);\n \n/// Delete an Event Flags object.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);\n \n \n//  ==== Mutex Management Functions ====\n \n/// Create and Initialize a Mutex object.\n/// \\param[in]     attr          mutex attributes; NULL: default values.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\nosMutexId_t osMutexNew (const osMutexAttr_t *attr);\n \n/// Get name of a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return name as null-terminated string.\nconst char *osMutexGetName (osMutexId_t mutex_id);\n \n/// Acquire a Mutex or timeout if it is locked.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);\n \n/// Release a Mutex that was acquired by \\ref osMutexAcquire.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMutexRelease (osMutexId_t mutex_id);\n \n/// Get Thread which owns a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return thread ID of owner thread or NULL when mutex was not acquired.\nosThreadId_t osMutexGetOwner (osMutexId_t mutex_id);\n \n/// Delete a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMutexDelete (osMutexId_t mutex_id);\n \n \n//  ==== Semaphore Management Functions ====\n \n/// Create and Initialize a Semaphore object.\n/// \\param[in]     max_count     maximum number of available tokens.\n/// \\param[in]     initial_count initial number of available tokens.\n/// \\param[in]     attr          semaphore attributes; NULL: default values.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\nosSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);\n \n/// Get name of a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return name as null-terminated string.\nconst char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);\n \n/// Acquire a Semaphore token or timeout if no tokens are available.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);\n \n/// Release a Semaphore token up to the initial maximum count.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);\n \n/// Get current Semaphore token count.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return number of tokens available.\nuint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);\n \n/// Delete a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);\n \n \n//  ==== Memory Pool Management Functions ====\n \n/// Create and Initialize a Memory Pool object.\n/// \\param[in]     block_count   maximum number of memory blocks in memory pool.\n/// \\param[in]     block_size    memory block size in bytes.\n/// \\param[in]     attr          memory pool attributes; NULL: default values.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\nosMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);\n \n/// Get name of a Memory Pool object.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return name as null-terminated string.\nconst char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);\n \n/// Allocate a memory block from a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return address of the allocated memory block or NULL in case of no memory is available.\nvoid *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);\n \n/// Return an allocated memory block back to a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\param[in]     block         address of the allocated memory block to be returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);\n \n/// Get maximum number of memory blocks in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return maximum number of memory blocks.\nuint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);\n \n/// Get memory block size in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return memory block size in bytes.\nuint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);\n \n/// Get number of memory blocks used in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return number of memory blocks used.\nuint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);\n \n/// Get number of memory blocks available in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return number of memory blocks available.\nuint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);\n \n/// Delete a Memory Pool object.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);\n \n \n//  ==== Message Queue Management Functions ====\n \n/// Create and Initialize a Message Queue object.\n/// \\param[in]     msg_count     maximum number of messages in queue.\n/// \\param[in]     msg_size      maximum message size in bytes.\n/// \\param[in]     attr          message queue attributes; NULL: default values.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\nosMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);\n \n/// Get name of a Message Queue object.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return name as null-terminated string.\nconst char *osMessageQueueGetName (osMessageQueueId_t mq_id);\n \n/// Put a Message into a Queue or timeout if Queue is full.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\param[in]     msg_ptr       pointer to buffer with message to put into a queue.\n/// \\param[in]     msg_prio      message priority.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);\n \n/// Get a Message from a Queue or timeout if Queue is empty.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\param[out]    msg_ptr       pointer to buffer for message to get from a queue.\n/// \\param[out]    msg_prio      pointer to buffer for message priority or NULL.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);\n \n/// Get maximum number of messages in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return maximum number of messages.\nuint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);\n \n/// Get maximum message size in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return maximum message size in bytes.\nuint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);\n \n/// Get number of queued messages in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return number of queued messages.\nuint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);\n \n/// Get number of available slots for messages in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return number of available slots for messages.\nuint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);\n \n/// Reset a Message Queue to initial empty state.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);\n \n/// Delete a Message Queue object.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);\n \n \n//  ==== Handler Functions ====\n \n/// Handler for expired thread watchdogs.\n/// \\param[in]     thread_id thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return new watchdog reload value or 0 to stop the watchdog.\nuint32_t osWatchdogAlarm_Handler (osThreadId_t thread_id);\n \n \n// ==== Zone Management Function ====\n \n/// Setup MPU protected zone (called when zone changes).\n/// \\param[in]     zone          zone number.\nvoid osZoneSetup_Callback (uint32_t zone);\n \n \n//  ==== Exception Faults ====\n \n/// Resume normal operation when exiting exception faults\nvoid osFaultResume (void);\n \n \n#ifdef  __cplusplus\n}\n#endif\n \n#endif  // CMSIS_OS2_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/Include/os_tick.h",
    "content": "/**************************************************************************//**\n * @file     os_tick.h\n * @brief    CMSIS OS Tick header file\n * @version  V1.0.2\n * @date     19. March 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2021 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef OS_TICK_H\n#define OS_TICK_H\n\n#include <stdint.h>\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n/// IRQ Handler.\n#ifndef IRQHANDLER_T\n#define IRQHANDLER_T\ntypedef void (*IRQHandler_t) (void);\n#endif\n\n/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks\n/// \\param[in]     freq         tick frequency in Hz\n/// \\param[in]     handler      tick IRQ handler\n/// \\return 0 on success, -1 on error.\nint32_t  OS_Tick_Setup (uint32_t freq, IRQHandler_t handler);\n\n/// Enable OS Tick timer interrupt\nvoid     OS_Tick_Enable (void);\n\n/// Disable OS Tick timer interrupt\nvoid     OS_Tick_Disable (void);\n\n/// Acknowledge execution of OS Tick timer interrupt\nvoid     OS_Tick_AcknowledgeIRQ (void);\n\n/// Get OS Tick timer IRQ number\n/// \\return OS Tick IRQ number\nint32_t  OS_Tick_GetIRQn (void);\n\n/// Get OS Tick timer clock frequency\n/// \\return OS Tick timer clock frequency in Hz\nuint32_t OS_Tick_GetClock (void);\n\n/// Get OS Tick timer interval reload value\n/// \\return OS Tick timer interval reload value\nuint32_t OS_Tick_GetInterval (void);\n\n/// Get OS Tick timer counter value\n/// \\return OS Tick timer counter value\nuint32_t OS_Tick_GetCount (void);\n\n/// Get OS Tick timer overflow status\n/// \\return OS Tick overflow status (1 - overflow, 0 - no overflow).\nuint32_t OS_Tick_GetOverflow (void);\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif  /* OS_TICK_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Config/RTX_Config.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.2.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration\n *\n * -----------------------------------------------------------------------------\n */\n \n#include \"cmsis_compiler.h\"\n#include \"rtx_os.h\"\n \n// OS Idle Thread\n__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n\n  for (;;) {}\n}\n \n// OS Error Callback function\n__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {\n  (void)object_id;\n\n  switch (code) {\n    case osRtxErrorStackOverflow:\n      // Stack overflow detected for thread (thread_id=object_id)\n      break;\n    case osRtxErrorISRQueueOverflow:\n      // ISR Queue overflow detected when inserting object (object_id)\n      break;\n    case osRtxErrorTimerQueueOverflow:\n      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)\n      break;\n    case osRtxErrorClibSpace:\n      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM\n      break;\n    case osRtxErrorClibMutex:\n      // Standard C/C++ library mutex initialization failed\n      break;\n    case osRtxErrorSVC:\n      // Invalid SVC function called (function=object_id)\n      break;\n    default:\n      // Reserved\n      break;\n  }\n  for (;;) {}\n//return 0U;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Config/RTX_Config.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.6.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration definitions\n *\n * -----------------------------------------------------------------------------\n */\n \n#ifndef RTX_CONFIG_H_\n#define RTX_CONFIG_H_\n \n#ifdef   _RTE_\n#include \"RTE_Components.h\"\n#ifdef    RTE_RTX_CONFIG_H\n#include  RTE_RTX_CONFIG_H\n#endif\n#endif\n \n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n \n// <h>System Configuration\n// =======================\n \n//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>\n//   <i> Defines the combined global dynamic memory size.\n//   <i> Default: 32768\n#ifndef OS_DYNAMIC_MEM_SIZE\n#define OS_DYNAMIC_MEM_SIZE         32768\n#endif\n \n//   <o>Kernel Tick Frequency [Hz] <1-1000000>\n//   <i> Defines base time unit for delays and timeouts.\n//   <i> Default: 1000 (1ms tick)\n#ifndef OS_TICK_FREQ\n#define OS_TICK_FREQ                1000\n#endif\n \n//   <e>Round-Robin Thread switching\n//   <i> Enables Round-Robin Thread switching.\n#ifndef OS_ROBIN_ENABLE\n#define OS_ROBIN_ENABLE             1\n#endif\n \n//     <o>Round-Robin Timeout <1-1000>\n//     <i> Defines how many ticks a thread will execute before a thread switch.\n//     <i> Default: 5\n#ifndef OS_ROBIN_TIMEOUT\n#define OS_ROBIN_TIMEOUT            5\n#endif\n \n//   </e>\n \n//   <e>Safety features (Source variant only)\n//   <i> Enables FuSa related features.\n//   <i> Requires RTX Source variant.\n//   <i> Enables:\n//   <i>  - selected features from this group\n//   <i>  - Thread functions: osThreadProtectPrivileged\n#ifndef OS_SAFETY_FEATURES\n#define OS_SAFETY_FEATURES          0\n#endif\n \n//     <q>Safety Class\n//     <i> Threads assigned to lower classes cannot modify higher class threads.\n//     <i> Enables:\n//     <i>  - Object attributes: osSafetyClass\n//     <i>  - Kernel functions: osKernelProtect, osKernelDestroyClass\n//     <i>  - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass\n#ifndef OS_SAFETY_CLASS\n#define OS_SAFETY_CLASS             1\n#endif\n \n//     <q>MPU Protected Zone\n//     <i> Access protection via MPU (Spatial isolation).\n//     <i> Enables:\n//     <i>  - Thread attributes: osThreadZone\n//     <i>  - Thread functions: osThreadGetZone, osThreadTerminateZone\n//     <i>  - Zone Management: osZoneSetup_Callback\n#ifndef OS_EXECUTION_ZONE\n#define OS_EXECUTION_ZONE           1\n#endif\n \n//     <q>Thread Watchdog\n//     <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).\n//     <i> Enables:\n//     <i>  - Thread functions: osThreadFeedWatchdog\n//     <i>  - Handler functions: osWatchdogAlarm_Handler\n#ifndef OS_THREAD_WATCHDOG\n#define OS_THREAD_WATCHDOG          1\n#endif\n \n//     <q>Object Pointer checking\n//     <i> Check object pointer alignment and memory region.\n#ifndef OS_OBJ_PTR_CHECK\n#define OS_OBJ_PTR_CHECK            0\n#endif\n \n//     <q>SVC Function Pointer checking\n//     <i> Check SVC function pointer alignment and memory region.\n//     <i> User needs to define a linker execution region RTX_SVC_VENEERS\n//     <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)\n#ifndef OS_SVC_PTR_CHECK\n#define OS_SVC_PTR_CHECK            0\n#endif\n \n//   </e>\n \n//   <o>ISR FIFO Queue\n//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries\n//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries\n//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries\n//   <i> RTOS Functions called from ISR store requests to this buffer.\n//   <i> Default: 16 entries\n#ifndef OS_ISR_FIFO_QUEUE\n#define OS_ISR_FIFO_QUEUE           16\n#endif\n \n//   <q>Object Memory usage counters\n//   <i> Enables object memory usage counters (requires RTX source variant).\n#ifndef OS_OBJ_MEM_USAGE\n#define OS_OBJ_MEM_USAGE            0\n#endif\n \n// </h>\n \n// <h>Thread Configuration\n// =======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_THREAD_OBJ_MEM\n#define OS_THREAD_OBJ_MEM           0\n#endif\n \n//     <o>Number of user Threads <1-1000>\n//     <i> Defines maximum number of user threads that can be active at the same time.\n//     <i> Applies to user threads with system provided memory for control blocks.\n#ifndef OS_THREAD_NUM\n#define OS_THREAD_NUM               1\n#endif\n \n//     <o>Number of user Threads with default Stack size <0-1000>\n//     <i> Defines maximum number of user threads with default stack size.\n//     <i> Applies to user threads with zero stack size specified.\n#ifndef OS_THREAD_DEF_STACK_NUM\n#define OS_THREAD_DEF_STACK_NUM     0\n#endif\n \n//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>\n//     <i> Defines the combined stack size for user threads with user-provided stack size.\n//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.\n//     <i> Default: 0\n#ifndef OS_THREAD_USER_STACK_SIZE\n#define OS_THREAD_USER_STACK_SIZE   0\n#endif\n \n//   </e>\n \n//   <o>Default Thread Stack size [bytes] <96-1073741824:8>\n//   <i> Defines stack size for threads with zero stack size specified.\n//   <i> Default: 3072\n#ifndef OS_STACK_SIZE\n#define OS_STACK_SIZE               3072\n#endif\n \n//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>\n//   <i> Defines stack size for Idle thread.\n//   <i> Default: 512\n#ifndef OS_IDLE_THREAD_STACK_SIZE\n#define OS_IDLE_THREAD_STACK_SIZE   512\n#endif\n \n//   <o>Idle Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_IDLE_THREAD_TZ_MOD_ID\n#define OS_IDLE_THREAD_TZ_MOD_ID    0\n#endif\n \n//   <o>Idle Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_CLASS\n#define OS_IDLE_THREAD_CLASS        0\n#endif\n \n//   <o>Idle Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_ZONE\n#define OS_IDLE_THREAD_ZONE         0\n#endif\n \n//   <q>Stack overrun checking\n//   <i> Enables stack overrun check at thread switch (requires RTX source variant).\n//   <i> Enabling this option increases slightly the execution time of a thread switch.\n#ifndef OS_STACK_CHECK\n#define OS_STACK_CHECK              1\n#endif\n \n//   <q>Stack usage watermark\n//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.\n//   <i> Enabling this option increases significantly the execution time of thread creation.\n#ifndef OS_STACK_WATERMARK\n#define OS_STACK_WATERMARK          0\n#endif\n \n//   <o>Default Processor mode for Thread execution\n//     <0=> Unprivileged mode\n//     <1=> Privileged mode\n//   <i> Default: Unprivileged mode\n#ifndef OS_PRIVILEGE_MODE\n#define OS_PRIVILEGE_MODE           0\n#endif\n \n// </h>\n \n// <h>Timer Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_TIMER_OBJ_MEM\n#define OS_TIMER_OBJ_MEM            0\n#endif\n \n//     <o>Number of Timer objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_TIMER_NUM\n#define OS_TIMER_NUM                1\n#endif\n \n//   </e>\n \n//   <o>Timer Thread Priority\n//      <8=> Low\n//     <16=> Below Normal  <24=> Normal  <32=> Above Normal\n//     <40=> High\n//     <48=> Realtime\n//   <i> Defines priority for timer thread\n//   <i> Default: High\n#ifndef OS_TIMER_THREAD_PRIO\n#define OS_TIMER_THREAD_PRIO        40\n#endif\n \n//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>\n//   <i> Defines stack size for Timer thread.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 512\n#ifndef OS_TIMER_THREAD_STACK_SIZE\n#define OS_TIMER_THREAD_STACK_SIZE  512\n#endif\n \n//   <o>Timer Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_TIMER_THREAD_TZ_MOD_ID\n#define OS_TIMER_THREAD_TZ_MOD_ID   0\n#endif\n \n//   <o>Timer Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_CLASS\n#define OS_TIMER_THREAD_CLASS       0\n#endif\n \n//   <o>Timer Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_ZONE\n#define OS_TIMER_THREAD_ZONE        0\n#endif\n \n//   <o>Timer Callback Queue entries <0-256>\n//   <i> Number of concurrent active timer callback functions.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 4\n#ifndef OS_TIMER_CB_QUEUE\n#define OS_TIMER_CB_QUEUE           4\n#endif\n \n// </h>\n \n// <h>Event Flags Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_EVFLAGS_OBJ_MEM\n#define OS_EVFLAGS_OBJ_MEM          0\n#endif\n \n//     <o>Number of Event Flags objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_EVFLAGS_NUM\n#define OS_EVFLAGS_NUM              1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Mutex Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MUTEX_OBJ_MEM\n#define OS_MUTEX_OBJ_MEM            0\n#endif\n \n//     <o>Number of Mutex objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MUTEX_NUM\n#define OS_MUTEX_NUM                1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Semaphore Configuration\n// ==========================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_SEMAPHORE_OBJ_MEM\n#define OS_SEMAPHORE_OBJ_MEM        0\n#endif\n \n//     <o>Number of Semaphore objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_SEMAPHORE_NUM\n#define OS_SEMAPHORE_NUM            1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Memory Pool Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MEMPOOL_OBJ_MEM\n#define OS_MEMPOOL_OBJ_MEM          0\n#endif\n \n//     <o>Number of Memory Pool objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MEMPOOL_NUM\n#define OS_MEMPOOL_NUM              1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MEMPOOL_DATA_SIZE\n#define OS_MEMPOOL_DATA_SIZE        0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Message Queue Configuration\n// ==============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MSGQUEUE_OBJ_MEM\n#define OS_MSGQUEUE_OBJ_MEM         0\n#endif\n \n//     <o>Number of Message Queue objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MSGQUEUE_NUM\n#define OS_MSGQUEUE_NUM             1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MSGQUEUE_DATA_SIZE\n#define OS_MSGQUEUE_DATA_SIZE       0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Event Recorder Configuration\n// ===============================\n \n//   <e>Global Initialization\n//   <i> Initialize Event Recorder during 'osKernelInitialize'.\n#ifndef OS_EVR_INIT\n#define OS_EVR_INIT                 0\n#endif\n \n//     <q>Start recording\n//     <i> Start event recording after initialization.\n#ifndef OS_EVR_START\n#define OS_EVR_START                1\n#endif\n \n//     <h>Global Event Filter Setup\n//     <i> Initial recording level applied to all components.\n//       <o.0>Error events\n//       <o.1>API function call events\n//       <o.2>Operation events\n//       <o.3>Detailed operation events\n//     </h>\n#ifndef OS_EVR_LEVEL\n#define OS_EVR_LEVEL                0x00U\n#endif\n \n//     <h>RTOS Event Filter Setup\n//     <i> Recording levels for RTX components.\n//     <i> Only applicable if events for the respective component are generated.\n \n//       <e.7>Memory Management\n//       <i> Recording level for Memory Management events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMORY_LEVEL\n#define OS_EVR_MEMORY_LEVEL         0x81U\n#endif\n \n//       <e.7>Kernel\n//       <i> Recording level for Kernel events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_KERNEL_LEVEL\n#define OS_EVR_KERNEL_LEVEL         0x81U\n#endif\n \n//       <e.7>Thread\n//       <i> Recording level for Thread events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THREAD_LEVEL\n#define OS_EVR_THREAD_LEVEL         0x85U\n#endif\n \n//       <e.7>Generic Wait\n//       <i> Recording level for Generic Wait events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_WAIT_LEVEL\n#define OS_EVR_WAIT_LEVEL           0x81U\n#endif\n \n//       <e.7>Thread Flags\n//       <i> Recording level for Thread Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THFLAGS_LEVEL\n#define OS_EVR_THFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Event Flags\n//       <i> Recording level for Event Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_EVFLAGS_LEVEL\n#define OS_EVR_EVFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Timer\n//       <i> Recording level for Timer events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_TIMER_LEVEL\n#define OS_EVR_TIMER_LEVEL          0x81U\n#endif\n \n//       <e.7>Mutex\n//       <i> Recording level for Mutex events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MUTEX_LEVEL\n#define OS_EVR_MUTEX_LEVEL          0x81U\n#endif\n \n//       <e.7>Semaphore\n//       <i> Recording level for Semaphore events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_SEMAPHORE_LEVEL\n#define OS_EVR_SEMAPHORE_LEVEL      0x81U\n#endif\n \n//       <e.7>Memory Pool\n//       <i> Recording level for Memory Pool events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMPOOL_LEVEL\n#define OS_EVR_MEMPOOL_LEVEL        0x81U\n#endif\n \n//       <e.7>Message Queue\n//       <i> Recording level for Message Queue events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MSGQUEUE_LEVEL\n#define OS_EVR_MSGQUEUE_LEVEL       0x81U\n#endif\n \n//     </h>\n \n//   </e>\n \n//   <h>RTOS Event Generation\n//   <i> Enables event generation for RTX components (requires RTX source variant).\n \n//     <q>Memory Management\n//     <i> Enables Memory Management event generation.\n#ifndef OS_EVR_MEMORY\n#define OS_EVR_MEMORY               1\n#endif\n \n//     <q>Kernel\n//     <i> Enables Kernel event generation.\n#ifndef OS_EVR_KERNEL\n#define OS_EVR_KERNEL               1\n#endif\n \n//     <q>Thread\n//     <i> Enables Thread event generation.\n#ifndef OS_EVR_THREAD\n#define OS_EVR_THREAD               1\n#endif\n \n//     <q>Generic Wait\n//     <i> Enables Generic Wait event generation.\n#ifndef OS_EVR_WAIT\n#define OS_EVR_WAIT                 1\n#endif\n \n//     <q>Thread Flags\n//     <i> Enables Thread Flags event generation.\n#ifndef OS_EVR_THFLAGS\n#define OS_EVR_THFLAGS              1\n#endif\n \n//     <q>Event Flags\n//     <i> Enables Event Flags event generation.\n#ifndef OS_EVR_EVFLAGS\n#define OS_EVR_EVFLAGS              1\n#endif\n \n//     <q>Timer\n//     <i> Enables Timer event generation.\n#ifndef OS_EVR_TIMER\n#define OS_EVR_TIMER                1\n#endif\n \n//     <q>Mutex\n//     <i> Enables Mutex event generation.\n#ifndef OS_EVR_MUTEX\n#define OS_EVR_MUTEX                1\n#endif\n \n//     <q>Semaphore\n//     <i> Enables Semaphore event generation.\n#ifndef OS_EVR_SEMAPHORE\n#define OS_EVR_SEMAPHORE            1\n#endif\n \n//     <q>Memory Pool\n//     <i> Enables Memory Pool event generation.\n#ifndef OS_EVR_MEMPOOL\n#define OS_EVR_MEMPOOL              1\n#endif\n \n//     <q>Message Queue\n//     <i> Enables Message Queue event generation.\n#ifndef OS_EVR_MSGQUEUE\n#define OS_EVR_MSGQUEUE             1\n#endif\n \n//   </h>\n \n// </h>\n \n// Number of Threads which use standard C/C++ library libspace\n// (when thread specific memory allocation is not used).\n#if (OS_THREAD_OBJ_MEM == 0)\n#ifndef OS_THREAD_LIBSPACE_NUM\n#define OS_THREAD_LIBSPACE_NUM      4\n#endif\n#else\n#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM\n#endif\n \n//------------- <<< end of configuration section >>> ---------------------------\n \n#endif  // RTX_CONFIG_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Config/handlers.c",
    "content": "/*\n * Copyright (c) 2013-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Exception handlers (C functions)\n *\n * -----------------------------------------------------------------------------\n */\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n\n//Fault Status Register (IFSR/DFSR) definitions\n#define FSR_ALIGNMENT_FAULT                  0x01   //DFSR only. Fault on first lookup\n#define FSR_INSTRUCTION_CACHE_MAINTENANCE    0x04   //DFSR only - async/external\n#define FSR_SYNC_EXT_TTB_WALK_FIRST          0x0c   //sync/external\n#define FSR_SYNC_EXT_TTB_WALK_SECOND         0x0e   //sync/external\n#define FSR_SYNC_PARITY_TTB_WALK_FIRST       0x1c   //sync/external\n#define FSR_SYNC_PARITY_TTB_WALK_SECOND      0x1e   //sync/external\n#define FSR_TRANSLATION_FAULT_FIRST          0x05   //MMU Fault - internal\n#define FSR_TRANSLATION_FAULT_SECOND         0x07   //MMU Fault - internal\n#define FSR_ACCESS_FLAG_FAULT_FIRST          0x03   //MMU Fault - internal\n#define FSR_ACCESS_FLAG_FAULT_SECOND         0x06   //MMU Fault - internal\n#define FSR_DOMAIN_FAULT_FIRST               0x09   //MMU Fault - internal\n#define FSR_DOMAIN_FAULT_SECOND              0x0b   //MMU Fault - internal\n#define FSR_PERMISSION_FAULT_FIRST           0x0f   //MMU Fault - internal\n#define FSR_PERMISSION_FAULT_SECOND          0x0d   //MMU Fault - internal\n#define FSR_DEBUG_EVENT                      0x02   //internal\n#define FSR_SYNC_EXT_ABORT                   0x08   //sync/external\n#define FSR_TLB_CONFLICT_ABORT               0x10   //sync/external\n#define FSR_LOCKDOWN                         0x14   //internal\n#define FSR_COPROCESSOR_ABORT                0x1a   //internal\n#define FSR_SYNC_PARITY_ERROR                0x19   //sync/external\n#define FSR_ASYNC_EXTERNAL_ABORT             0x16   //DFSR only - async/external\n#define FSR_ASYNC_PARITY_ERROR               0x18   //DFSR only - async/external\n\nvoid CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {\n    uint32_t FS = (DFSR & (1U << 10U)) >> 6U | (DFSR & 0x0FU); //Store Fault Status\n    (void)DFAR;\n    (void)LR;\n  \n    switch(FS) {\n        //Synchronous parity errors - retry\n        case FSR_SYNC_PARITY_ERROR:\n        case FSR_SYNC_PARITY_TTB_WALK_FIRST:\n        case FSR_SYNC_PARITY_TTB_WALK_SECOND:\n            return;\n\n        //Your code here. Value in DFAR is invalid for some fault statuses.\n        case FSR_ALIGNMENT_FAULT:\n        case FSR_INSTRUCTION_CACHE_MAINTENANCE:\n        case FSR_SYNC_EXT_TTB_WALK_FIRST:\n        case FSR_SYNC_EXT_TTB_WALK_SECOND:\n        case FSR_TRANSLATION_FAULT_FIRST:\n        case FSR_TRANSLATION_FAULT_SECOND:\n        case FSR_ACCESS_FLAG_FAULT_FIRST:\n        case FSR_ACCESS_FLAG_FAULT_SECOND:\n        case FSR_DOMAIN_FAULT_FIRST:\n        case FSR_DOMAIN_FAULT_SECOND:\n        case FSR_PERMISSION_FAULT_FIRST:\n        case FSR_PERMISSION_FAULT_SECOND:\n        case FSR_DEBUG_EVENT:\n        case FSR_SYNC_EXT_ABORT:\n        case FSR_TLB_CONFLICT_ABORT:\n        case FSR_LOCKDOWN:\n        case FSR_COPROCESSOR_ABORT:\n        case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid\n        case FSR_ASYNC_PARITY_ERROR:   //DFAR invalid\n        default:\n            while(1);\n    }\n}\n\nvoid CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {\n    uint32_t FS = (IFSR & (1U << 10U)) >> 6U | (IFSR & 0x0FU); //Store Fault Status\n    (void)IFAR;\n    (void)LR;\n    \n    switch(FS) {\n        //Synchronous parity errors - retry\n        case FSR_SYNC_PARITY_ERROR:\n        case FSR_SYNC_PARITY_TTB_WALK_FIRST:\n        case FSR_SYNC_PARITY_TTB_WALK_SECOND:\n            return;\n\n        //Your code here. Value in IFAR is invalid for some fault statuses.\n        case FSR_SYNC_EXT_TTB_WALK_FIRST:\n        case FSR_SYNC_EXT_TTB_WALK_SECOND:\n        case FSR_TRANSLATION_FAULT_FIRST:\n        case FSR_TRANSLATION_FAULT_SECOND:\n        case FSR_ACCESS_FLAG_FAULT_FIRST:\n        case FSR_ACCESS_FLAG_FAULT_SECOND:\n        case FSR_DOMAIN_FAULT_FIRST:\n        case FSR_DOMAIN_FAULT_SECOND:\n        case FSR_PERMISSION_FAULT_FIRST:\n        case FSR_PERMISSION_FAULT_SECOND:\n        case FSR_DEBUG_EVENT: //IFAR invalid\n        case FSR_SYNC_EXT_ABORT:\n        case FSR_TLB_CONFLICT_ABORT:\n        case FSR_LOCKDOWN:\n        case FSR_COPROCESSOR_ABORT:\n        default:\n            while(1);\n    }\n}\n\n\n//returns amount to decrement lr by\n//this will be 0 when we have emulated the instruction and want to execute the next instruction\n//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)\n//this will be 4 when we have performed some maintenance and want to retry the instruction in Arm   (state == 4)\nuint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {\n    const uint32_t THUMB = 2U;\n    const uint32_t ARM = 4U;\n    (void)LR;\n    //Lazy VFP/NEON initialisation and switching\n\n    // (Arm Architecture Reference Manual section A7.5) VFP data processing instruction?\n    // (Arm Architecture Reference Manual section A7.6) VFP/NEON register load/store instruction?\n    // (Arm Architecture Reference Manual section A7.8) VFP/NEON register data transfer instruction?\n    // (Arm Architecture Reference Manual section A7.9) VFP/NEON 64-bit register data transfer instruction?\n    if ((state == ARM   && ((opcode & 0x0C000000U) >> 26U == 0x03U)) ||\n        (state == THUMB && ((opcode & 0xEC000000U) >> 26U == 0x3BU))) {\n        if (((opcode & 0x00000E00U) >> 9U) == 5U) {\n            __FPU_Enable();\n            return state;\n        }\n    }\n\n    // (Arm Architecture Reference Manual section A7.4) NEON data processing instruction?\n    if ((state == ARM   && ((opcode & 0xFE000000U) >> 24U == 0xF2U)) ||\n        (state == THUMB && ((opcode & 0xEF000000U) >> 24U == 0xEFU)) ||\n    // (Arm Architecture Reference Manual section A7.7) NEON load/store instruction?\n        (state == ARM   && ((opcode >> 24U) == 0xF4U)) ||\n        (state == THUMB && ((opcode >> 24U) == 0xF9U))) {\n            __FPU_Enable();\n            return state;\n    }\n\n    //Add code here for other Undef cases\n    while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/Abstract.txt",
    "content": "The RTX_Blinky project is a simple RTX Kernel based example\nfor a simulated Cortex-M3 device\n\nExample functionality:\n - Clock Settings:\n   - XTAL    =  50 MHz\n   - Core    =  25 MHz\n\nThe simple RTX Kernel based example simulates the step-motor \ndriver. Four LEDs are blinking simulating the activation of \nthe four output driver stages\nThe simulation does not provide LEDs, so the state changes\nare output on the Debug printf window:\n\n- phase A\n- phase B\n- phase C\n- phase D\n\nThis example simulates Half step driver mode and\nCW rotation direction.\n\n\nThe BLINKY example program is available for one target:\n\n  Simulation:          configured for a simulated on-chip Flash\n\nThe example is compatible with other Cortex-M class devices.\nSimply open the project settings, navigate to Device tab and\nselect another Cortex-M class device.\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/Blinky.c",
    "content": "/* -------------------------------------------------------------------------- \n * Copyright (c) 2013-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    Blinky.c\n *      Purpose: RTX example program\n *\n *---------------------------------------------------------------------------*/\n\n#include <stdio.h>\n\n#include \"cmsis_os2.h\"                  // ARM::CMSIS:RTOS2:Keil RTX5\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\nosThreadId_t tid_phaseA;                /* Thread id of thread: phase_a      */\nosThreadId_t tid_phaseB;                /* Thread id of thread: phase_b      */\nosThreadId_t tid_phaseC;                /* Thread id of thread: phase_c      */\nosThreadId_t tid_phaseD;                /* Thread id of thread: phase_d      */\nosThreadId_t tid_clock;                 /* Thread id of thread: clock        */\n\nstruct phases_t {\n  int_fast8_t phaseA;\n  int_fast8_t phaseB;\n  int_fast8_t phaseC;\n  int_fast8_t phaseD;\n} g_phases;\n\n\n/*----------------------------------------------------------------------------\n *      Switch LED on\n *---------------------------------------------------------------------------*/\nvoid Switch_On (unsigned char led) {\n  printf(\"LED On:  #%d\\n\\r\", led);\n}\n\n/*----------------------------------------------------------------------------\n *      Switch LED off\n *---------------------------------------------------------------------------*/\nvoid Switch_Off (unsigned char led) {\n  printf(\"LED Off: #%d\\n\\r\", led);\n}\n\n\n/*----------------------------------------------------------------------------\n *      Function 'signal_func' called from multiple threads\n *---------------------------------------------------------------------------*/\nvoid signal_func (osThreadId_t tid)  {\n  osThreadFlagsSet(tid_clock, 0x0100);      /* set signal to clock thread    */\n  osDelay(500);                             /* delay 500ms                   */\n  osThreadFlagsSet(tid_clock, 0x0100);      /* set signal to clock thread    */\n  osDelay(500);                             /* delay 500ms                   */\n  osThreadFlagsSet(tid, 0x0001);            /* set signal to thread 'thread' */\n  osDelay(500);                             /* delay 500ms                   */\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 1 'phaseA': Phase A output\n *---------------------------------------------------------------------------*/\nvoid phaseA (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny ,osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(0);\n    g_phases.phaseA = 1;\n    signal_func(tid_phaseB);                                     /* call common signal function   */\n    g_phases.phaseA = 0;\n    Switch_Off(0);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 2 'phaseB': Phase B output\n *---------------------------------------------------------------------------*/\nvoid phaseB (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(1);\n    g_phases.phaseB = 1;\n    signal_func(tid_phaseC);                /* call common signal function   */\n    g_phases.phaseB = 0;\n    Switch_Off(1);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 3 'phaseC': Phase C output\n *---------------------------------------------------------------------------*/\nvoid phaseC (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(2);\n    g_phases.phaseC = 1;\n    signal_func(tid_phaseD);                /* call common signal function   */\n    g_phases.phaseC = 0;\n    Switch_Off(2);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 4 'phaseD': Phase D output\n *---------------------------------------------------------------------------*/\nvoid phaseD (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(3);\n    g_phases.phaseD = 1;\n    signal_func(tid_phaseA);                /* call common signal function   */\n    g_phases.phaseD = 0;\n    Switch_Off(3);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 5 'clock': Signal Clock\n *---------------------------------------------------------------------------*/\nvoid clock (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0100, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0100 */\n    osDelay(80);                            /* delay  80ms                   */\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Main: Initialize and start RTX Kernel\n *---------------------------------------------------------------------------*/\nvoid app_main (void *argument) {\n\n  tid_phaseA = osThreadNew(phaseA, NULL, NULL);\n  tid_phaseB = osThreadNew(phaseB, NULL, NULL);\n  tid_phaseC = osThreadNew(phaseC, NULL, NULL);\n  tid_phaseD = osThreadNew(phaseD, NULL, NULL);\n  tid_clock  = osThreadNew(clock,  NULL, NULL);\n\n  osThreadFlagsSet(tid_phaseA, 0x0001);     /* set signal to phaseA thread   */\n\n  osDelay(osWaitForever);\n}\n\nint main (void) {\n\n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  if (osKernelGetState() == osKernelReady) {\n    osKernelStart();                    // Start thread execution\n  }\n\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/Blinky.uvguix",
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    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/Blinky.uvprojx",
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<StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>7</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>3</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>1</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>3</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>0</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile>.\\RTE\\Device\\ARMCM3\\ARMCM3_ac6.sct</ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Source Files</GroupName>\n          <Files>\n            <File>\n              <FileName>Blinky.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\Blinky.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Documentation</GroupName>\n          <Files>\n            <File>\n              <FileName>Abstract.txt</FileName>\n              <FileType>5</FileType>\n              <FilePath>.\\Abstract.txt</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Compiler</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Device</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis>\n      <api Capiversion=\"2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" exclusive=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.0.0-Beta11\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </api>\n    </apis>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"ARMv6_7_8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n      <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n      <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n      <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"Event Recorder\" Cvariant=\"DAP\" Cvendor=\"Keil\" Cversion=\"1.5.1\" condition=\"Cortex-M Device\">\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.7.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n      <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"I/O\" Csub=\"STDOUT\" Cvariant=\"EVR\" Cvendor=\"Keil\" Cversion=\"1.2.0\" condition=\"ARMCC Cortex-M with EVR\">\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.7.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files>\n      <file attr=\"config\" category=\"source\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.c\" version=\"5.2.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.c</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.h\" version=\"5.6.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.h</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"Config\\EventRecorderConf.h\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Compiler\\EventRecorderConf.h</instance>\n        <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"Event Recorder\" Cvariant=\"DAP\" Cvendor=\"Keil\" Cversion=\"1.5.1\" condition=\"Cortex-M Device\"/>\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.7.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"linkerScript\" condition=\"ARMCC6\" name=\"Device\\ARM\\ARMCM3\\Source\\ARM\\ARMCM3_ac6.sct\" version=\"1.0.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\ARMCM3_ac6.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM3\\Source\\startup_ARMCM3.c\" version=\"2.0.3\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\startup_ARMCM3.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM3\\Source\\system_ARMCM3.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\system_ARMCM3.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/RTE/CMSIS/RTX_Config.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.2.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration\n *\n * -----------------------------------------------------------------------------\n */\n \n#include \"cmsis_compiler.h\"\n#include \"rtx_os.h\"\n \n// OS Idle Thread\n__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n\n  for (;;) {}\n}\n \n// OS Error Callback function\n__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {\n  (void)object_id;\n\n  switch (code) {\n    case osRtxErrorStackOverflow:\n      // Stack overflow detected for thread (thread_id=object_id)\n      break;\n    case osRtxErrorISRQueueOverflow:\n      // ISR Queue overflow detected when inserting object (object_id)\n      break;\n    case osRtxErrorTimerQueueOverflow:\n      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)\n      break;\n    case osRtxErrorClibSpace:\n      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM\n      break;\n    case osRtxErrorClibMutex:\n      // Standard C/C++ library mutex initialization failed\n      break;\n    case osRtxErrorSVC:\n      // Invalid SVC function called (function=object_id)\n      break;\n    default:\n      // Reserved\n      break;\n  }\n  for (;;) {}\n//return 0U;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/RTE/CMSIS/RTX_Config.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.6.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration definitions\n *\n * -----------------------------------------------------------------------------\n */\n \n#ifndef RTX_CONFIG_H_\n#define RTX_CONFIG_H_\n \n#ifdef   _RTE_\n#include \"RTE_Components.h\"\n#ifdef    RTE_RTX_CONFIG_H\n#include  RTE_RTX_CONFIG_H\n#endif\n#endif\n \n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n \n// <h>System Configuration\n// =======================\n \n//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>\n//   <i> Defines the combined global dynamic memory size.\n//   <i> Default: 32768\n#ifndef OS_DYNAMIC_MEM_SIZE\n#define OS_DYNAMIC_MEM_SIZE         4096\n#endif\n \n//   <o>Kernel Tick Frequency [Hz] <1-1000000>\n//   <i> Defines base time unit for delays and timeouts.\n//   <i> Default: 1000 (1ms tick)\n#ifndef OS_TICK_FREQ\n#define OS_TICK_FREQ                1000\n#endif\n \n//   <e>Round-Robin Thread switching\n//   <i> Enables Round-Robin Thread switching.\n#ifndef OS_ROBIN_ENABLE\n#define OS_ROBIN_ENABLE             1\n#endif\n \n//     <o>Round-Robin Timeout <1-1000>\n//     <i> Defines how many ticks a thread will execute before a thread switch.\n//     <i> Default: 5\n#ifndef OS_ROBIN_TIMEOUT\n#define OS_ROBIN_TIMEOUT            5\n#endif\n \n//   </e>\n \n//   <e>Safety features (Source variant only)\n//   <i> Enables FuSa related features.\n//   <i> Requires RTX Source variant.\n//   <i> Enables:\n//   <i>  - selected features from this group\n//   <i>  - Thread functions: osThreadProtectPrivileged\n#ifndef OS_SAFETY_FEATURES\n#define OS_SAFETY_FEATURES          0\n#endif\n \n//     <q>Safety Class\n//     <i> Threads assigned to lower classes cannot modify higher class threads.\n//     <i> Enables:\n//     <i>  - Object attributes: osSafetyClass\n//     <i>  - Kernel functions: osKernelProtect, osKernelDestroyClass\n//     <i>  - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass\n#ifndef OS_SAFETY_CLASS\n#define OS_SAFETY_CLASS             1\n#endif\n \n//     <q>MPU Protected Zone\n//     <i> Access protection via MPU (Spatial isolation).\n//     <i> Enables:\n//     <i>  - Thread attributes: osThreadZone\n//     <i>  - Thread functions: osThreadGetZone, osThreadTerminateZone\n//     <i>  - Zone Management: osZoneSetup_Callback\n#ifndef OS_EXECUTION_ZONE\n#define OS_EXECUTION_ZONE           1\n#endif\n \n//     <q>Thread Watchdog\n//     <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).\n//     <i> Enables:\n//     <i>  - Thread functions: osThreadFeedWatchdog\n//     <i>  - Handler functions: osWatchdogAlarm_Handler\n#ifndef OS_THREAD_WATCHDOG\n#define OS_THREAD_WATCHDOG          1\n#endif\n \n//     <q>Object Pointer checking\n//     <i> Check object pointer alignment and memory region.\n#ifndef OS_OBJ_PTR_CHECK\n#define OS_OBJ_PTR_CHECK            0\n#endif\n \n//     <q>SVC Function Pointer checking\n//     <i> Check SVC function pointer alignment and memory region.\n//     <i> User needs to define a linker execution region RTX_SVC_VENEERS\n//     <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)\n#ifndef OS_SVC_PTR_CHECK\n#define OS_SVC_PTR_CHECK            0\n#endif\n \n//   </e>\n \n//   <o>ISR FIFO Queue\n//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries\n//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries\n//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries\n//   <i> RTOS Functions called from ISR store requests to this buffer.\n//   <i> Default: 16 entries\n#ifndef OS_ISR_FIFO_QUEUE\n#define OS_ISR_FIFO_QUEUE           16\n#endif\n \n//   <q>Object Memory usage counters\n//   <i> Enables object memory usage counters (requires RTX source variant).\n#ifndef OS_OBJ_MEM_USAGE\n#define OS_OBJ_MEM_USAGE            0\n#endif\n \n// </h>\n \n// <h>Thread Configuration\n// =======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_THREAD_OBJ_MEM\n#define OS_THREAD_OBJ_MEM           0\n#endif\n \n//     <o>Number of user Threads <1-1000>\n//     <i> Defines maximum number of user threads that can be active at the same time.\n//     <i> Applies to user threads with system provided memory for control blocks.\n#ifndef OS_THREAD_NUM\n#define OS_THREAD_NUM               1\n#endif\n \n//     <o>Number of user Threads with default Stack size <0-1000>\n//     <i> Defines maximum number of user threads with default stack size.\n//     <i> Applies to user threads with zero stack size specified.\n#ifndef OS_THREAD_DEF_STACK_NUM\n#define OS_THREAD_DEF_STACK_NUM     0\n#endif\n \n//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>\n//     <i> Defines the combined stack size for user threads with user-provided stack size.\n//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.\n//     <i> Default: 0\n#ifndef OS_THREAD_USER_STACK_SIZE\n#define OS_THREAD_USER_STACK_SIZE   0\n#endif\n \n//   </e>\n \n//   <o>Default Thread Stack size [bytes] <96-1073741824:8>\n//   <i> Defines stack size for threads with zero stack size specified.\n//   <i> Default: 3072\n#ifndef OS_STACK_SIZE\n#define OS_STACK_SIZE               512\n#endif\n \n//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>\n//   <i> Defines stack size for Idle thread.\n//   <i> Default: 512\n#ifndef OS_IDLE_THREAD_STACK_SIZE\n#define OS_IDLE_THREAD_STACK_SIZE   512\n#endif\n \n//   <o>Idle Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_IDLE_THREAD_TZ_MOD_ID\n#define OS_IDLE_THREAD_TZ_MOD_ID    0\n#endif\n \n//   <o>Idle Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_CLASS\n#define OS_IDLE_THREAD_CLASS        0\n#endif\n \n//   <o>Idle Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_ZONE\n#define OS_IDLE_THREAD_ZONE         0\n#endif\n \n//   <q>Stack overrun checking\n//   <i> Enables stack overrun check at thread switch (requires RTX source variant).\n//   <i> Enabling this option increases slightly the execution time of a thread switch.\n#ifndef OS_STACK_CHECK\n#define OS_STACK_CHECK              1\n#endif\n \n//   <q>Stack usage watermark\n//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.\n//   <i> Enabling this option increases significantly the execution time of thread creation.\n#ifndef OS_STACK_WATERMARK\n#define OS_STACK_WATERMARK          0\n#endif\n \n//   <o>Default Processor mode for Thread execution\n//     <0=> Unprivileged mode\n//     <1=> Privileged mode\n//   <i> Default: Unprivileged mode\n#ifndef OS_PRIVILEGE_MODE\n#define OS_PRIVILEGE_MODE           0\n#endif\n \n// </h>\n \n// <h>Timer Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_TIMER_OBJ_MEM\n#define OS_TIMER_OBJ_MEM            0\n#endif\n \n//     <o>Number of Timer objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_TIMER_NUM\n#define OS_TIMER_NUM                1\n#endif\n \n//   </e>\n \n//   <o>Timer Thread Priority\n//      <8=> Low\n//     <16=> Below Normal  <24=> Normal  <32=> Above Normal\n//     <40=> High\n//     <48=> Realtime\n//   <i> Defines priority for timer thread\n//   <i> Default: High\n#ifndef OS_TIMER_THREAD_PRIO\n#define OS_TIMER_THREAD_PRIO        40\n#endif\n \n//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>\n//   <i> Defines stack size for Timer thread.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 512\n#ifndef OS_TIMER_THREAD_STACK_SIZE\n#define OS_TIMER_THREAD_STACK_SIZE  512\n#endif\n \n//   <o>Timer Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_TIMER_THREAD_TZ_MOD_ID\n#define OS_TIMER_THREAD_TZ_MOD_ID   0\n#endif\n \n//   <o>Timer Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_CLASS\n#define OS_TIMER_THREAD_CLASS       0\n#endif\n \n//   <o>Timer Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_ZONE\n#define OS_TIMER_THREAD_ZONE        0\n#endif\n \n//   <o>Timer Callback Queue entries <0-256>\n//   <i> Number of concurrent active timer callback functions.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 4\n#ifndef OS_TIMER_CB_QUEUE\n#define OS_TIMER_CB_QUEUE           4\n#endif\n \n// </h>\n \n// <h>Event Flags Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_EVFLAGS_OBJ_MEM\n#define OS_EVFLAGS_OBJ_MEM          0\n#endif\n \n//     <o>Number of Event Flags objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_EVFLAGS_NUM\n#define OS_EVFLAGS_NUM              1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Mutex Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MUTEX_OBJ_MEM\n#define OS_MUTEX_OBJ_MEM            0\n#endif\n \n//     <o>Number of Mutex objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MUTEX_NUM\n#define OS_MUTEX_NUM                1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Semaphore Configuration\n// ==========================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_SEMAPHORE_OBJ_MEM\n#define OS_SEMAPHORE_OBJ_MEM        0\n#endif\n \n//     <o>Number of Semaphore objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_SEMAPHORE_NUM\n#define OS_SEMAPHORE_NUM            1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Memory Pool Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MEMPOOL_OBJ_MEM\n#define OS_MEMPOOL_OBJ_MEM          0\n#endif\n \n//     <o>Number of Memory Pool objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MEMPOOL_NUM\n#define OS_MEMPOOL_NUM              1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MEMPOOL_DATA_SIZE\n#define OS_MEMPOOL_DATA_SIZE        0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Message Queue Configuration\n// ==============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MSGQUEUE_OBJ_MEM\n#define OS_MSGQUEUE_OBJ_MEM         0\n#endif\n \n//     <o>Number of Message Queue objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MSGQUEUE_NUM\n#define OS_MSGQUEUE_NUM             1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MSGQUEUE_DATA_SIZE\n#define OS_MSGQUEUE_DATA_SIZE       0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Event Recorder Configuration\n// ===============================\n \n//   <e>Global Initialization\n//   <i> Initialize Event Recorder during 'osKernelInitialize'.\n#ifndef OS_EVR_INIT\n#define OS_EVR_INIT                 1\n#endif\n \n//     <q>Start recording\n//     <i> Start event recording after initialization.\n#ifndef OS_EVR_START\n#define OS_EVR_START                1\n#endif\n \n//     <h>Global Event Filter Setup\n//     <i> Initial recording level applied to all components.\n//       <o.0>Error events\n//       <o.1>API function call events\n//       <o.2>Operation events\n//       <o.3>Detailed operation events\n//     </h>\n#ifndef OS_EVR_LEVEL\n#define OS_EVR_LEVEL                0x00U\n#endif\n \n//     <h>RTOS Event Filter Setup\n//     <i> Recording levels for RTX components.\n//     <i> Only applicable if events for the respective component are generated.\n \n//       <e.7>Memory Management\n//       <i> Recording level for Memory Management events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMORY_LEVEL\n#define OS_EVR_MEMORY_LEVEL         0x81U\n#endif\n \n//       <e.7>Kernel\n//       <i> Recording level for Kernel events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_KERNEL_LEVEL\n#define OS_EVR_KERNEL_LEVEL         0x81U\n#endif\n \n//       <e.7>Thread\n//       <i> Recording level for Thread events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THREAD_LEVEL\n#define OS_EVR_THREAD_LEVEL         0x85U\n#endif\n \n//       <e.7>Generic Wait\n//       <i> Recording level for Generic Wait events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_WAIT_LEVEL\n#define OS_EVR_WAIT_LEVEL           0x81U\n#endif\n \n//       <e.7>Thread Flags\n//       <i> Recording level for Thread Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THFLAGS_LEVEL\n#define OS_EVR_THFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Event Flags\n//       <i> Recording level for Event Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_EVFLAGS_LEVEL\n#define OS_EVR_EVFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Timer\n//       <i> Recording level for Timer events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_TIMER_LEVEL\n#define OS_EVR_TIMER_LEVEL          0x81U\n#endif\n \n//       <e.7>Mutex\n//       <i> Recording level for Mutex events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MUTEX_LEVEL\n#define OS_EVR_MUTEX_LEVEL          0x81U\n#endif\n \n//       <e.7>Semaphore\n//       <i> Recording level for Semaphore events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_SEMAPHORE_LEVEL\n#define OS_EVR_SEMAPHORE_LEVEL      0x81U\n#endif\n \n//       <e.7>Memory Pool\n//       <i> Recording level for Memory Pool events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMPOOL_LEVEL\n#define OS_EVR_MEMPOOL_LEVEL        0x81U\n#endif\n \n//       <e.7>Message Queue\n//       <i> Recording level for Message Queue events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MSGQUEUE_LEVEL\n#define OS_EVR_MSGQUEUE_LEVEL       0x81U\n#endif\n \n//     </h>\n \n//   </e>\n \n//   <h>RTOS Event Generation\n//   <i> Enables event generation for RTX components (requires RTX source variant).\n \n//     <q>Memory Management\n//     <i> Enables Memory Management event generation.\n#ifndef OS_EVR_MEMORY\n#define OS_EVR_MEMORY               1\n#endif\n \n//     <q>Kernel\n//     <i> Enables Kernel event generation.\n#ifndef OS_EVR_KERNEL\n#define OS_EVR_KERNEL               1\n#endif\n \n//     <q>Thread\n//     <i> Enables Thread event generation.\n#ifndef OS_EVR_THREAD\n#define OS_EVR_THREAD               1\n#endif\n \n//     <q>Generic Wait\n//     <i> Enables Generic Wait event generation.\n#ifndef OS_EVR_WAIT\n#define OS_EVR_WAIT                 1\n#endif\n \n//     <q>Thread Flags\n//     <i> Enables Thread Flags event generation.\n#ifndef OS_EVR_THFLAGS\n#define OS_EVR_THFLAGS              1\n#endif\n \n//     <q>Event Flags\n//     <i> Enables Event Flags event generation.\n#ifndef OS_EVR_EVFLAGS\n#define OS_EVR_EVFLAGS              1\n#endif\n \n//     <q>Timer\n//     <i> Enables Timer event generation.\n#ifndef OS_EVR_TIMER\n#define OS_EVR_TIMER                1\n#endif\n \n//     <q>Mutex\n//     <i> Enables Mutex event generation.\n#ifndef OS_EVR_MUTEX\n#define OS_EVR_MUTEX                1\n#endif\n \n//     <q>Semaphore\n//     <i> Enables Semaphore event generation.\n#ifndef OS_EVR_SEMAPHORE\n#define OS_EVR_SEMAPHORE            1\n#endif\n \n//     <q>Memory Pool\n//     <i> Enables Memory Pool event generation.\n#ifndef OS_EVR_MEMPOOL\n#define OS_EVR_MEMPOOL              1\n#endif\n \n//     <q>Message Queue\n//     <i> Enables Message Queue event generation.\n#ifndef OS_EVR_MSGQUEUE\n#define OS_EVR_MSGQUEUE             1\n#endif\n \n//   </h>\n \n// </h>\n \n// Number of Threads which use standard C/C++ library libspace\n// (when thread specific memory allocation is not used).\n#if (OS_THREAD_OBJ_MEM == 0)\n#ifndef OS_THREAD_LIBSPACE_NUM\n#define OS_THREAD_LIBSPACE_NUM      4\n#endif\n#else\n#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM\n#endif\n \n//------------- <<< end of configuration section >>> ---------------------------\n \n#endif  // RTX_CONFIG_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/RTE/Compiler/EventRecorderConf.h",
    "content": "/*------------------------------------------------------------------------------\n * MDK - Component ::Event Recorder\n * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.\n *------------------------------------------------------------------------------\n * Name:    EventRecorderConf.h\n * Purpose: Event Recorder Configuration\n * Rev.:    V1.1.0\n *----------------------------------------------------------------------------*/\n\n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n\n// <h>Event Recorder\n\n//   <o>Number of Records\n//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024\n//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768\n//     <65536=>65536\n//   <i>Configures size of Event Record Buffer (each record is 16 bytes)\n//   <i>Must be 2^n (min=8, max=65536)\n#define EVENT_RECORD_COUNT      64U\n\n//   <o>Time Stamp Source\n//      <0=> DWT Cycle Counter  <1=> SysTick  <2=> CMSIS-RTOS2 System Timer\n//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)\n//   <i>Selects source for 32-bit time stamp\n#define EVENT_TIMESTAMP_SOURCE  2\n\n//   <o>Time Stamp Clock Frequency [Hz] <0-1000000000>\n//   <i>Defines initial time stamp clock frequency (0 when not used)\n#define EVENT_TIMESTAMP_FREQ    25000000U\n\n// </h>\n\n//------------- <<< end of configuration section >>> ---------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/RTE/Device/ARMCM3/ARMCM3_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00040000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Event Recorder Configuration -------------------------\n; <h> Event Recorder Configuration\n;   <o> Event Recorder RAM Size (in Bytes) <0x0-0xFFFFFFFF:16>\n;   <i> Memory requirement = 256 + (16 x Number_of_Records)\n;   <i> (defined by EVENT_RECORD_COUNT in EventRecorderConf.h)\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_EVR_SIZE  0x00000800\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  Stack, Heap and Event Recorder boundary definitions\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after previous section, 8 byte aligned */\n#define __RAM_EVR_BASE (AlignExpr(+0, 4))           /* starts after previous section, 4 byte aligned */\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __RAM_EVR_SIZE - __HEAP_SIZE - __STACK_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __RAM_EVR_SIZE > 0\n  RW_EVR __RAM_EVR_BASE UNINIT __RAM_EVR_SIZE {     ; Event Recorder RAM region\n    EventRecorder.o (+ZI)\n  }\n#endif\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/RTE/Device/ARMCM3/startup_ARMCM3.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM3.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M3 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM3)\n  #include \"ARMCM3.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Blinky/RTE/Device/ARMCM3/system_ARMCM3.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM3.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM3 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM3.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MemPool/Abstract.txt",
    "content": "The MemPool project is a simple RTX Kernel based example\nfor a simulated Cortex-M3 device\n\nExample functionality:\n - Clock Settings:\n   - XTAL    =  12 MHz\n   - Core    =  12 MHz\n\nThe simple RTX Kernel based example shows how to use a \nmemory pool for dynamic object allocation.\n\nThe MemPool example program is available for one target:\n\n  Simulation:          configured for a simulated on-chip Flash\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MemPool/MemPool.uvguix",
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         <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M3\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>1</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <RvdsMve>0</RvdsMve>\n            <RvdsCdeCp>0</RvdsCdeCp>\n            <nBranchProt>0</nBranchProt>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>1</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>0</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>7</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>3</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>1</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>3</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>0</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile>.\\RTE\\Device\\ARMCM3\\ARMCM3_ac6.sct</ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Source Group 1</GroupName>\n          <Files>\n            <File>\n              <FileName>main.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\main.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Documentation</GroupName>\n          <Files>\n            <File>\n              <FileName>Abstract.txt</FileName>\n              <FileType>5</FileType>\n              <FilePath>.\\Abstract.txt</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Compiler</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Device</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis>\n      <api Capiversion=\"2.1.1\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" exclusive=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.1.1-dev1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </api>\n    </apis>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.4.0\" condition=\"ARMv6_7_8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.7.0\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n      <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n      <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.7.0\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n      <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"Event Recorder\" Cvariant=\"DAP\" Cvendor=\"Keil\" Cversion=\"1.4.0\" condition=\"Cortex-M Device\">\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.4.9\" url=\"http://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.6.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n      <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"I/O\" Csub=\"STDOUT\" Cvariant=\"EVR\" Cvendor=\"Keil\" Cversion=\"1.2.0\" condition=\"ARMCC Cortex-M with EVR\">\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.4.9\" url=\"http://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.6.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files>\n      <file attr=\"config\" category=\"source\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.c\" version=\"5.2.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.c</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.h\" version=\"5.6.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.h</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"Config\\EventRecorderConf.h\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Compiler\\EventRecorderConf.h</instance>\n        <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"Event Recorder\" Cvariant=\"DAP\" Cvendor=\"Keil\" Cversion=\"1.5.1\" condition=\"Cortex-M Device\"/>\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.7.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"linkerScript\" condition=\"ARMCC6\" name=\"Device\\ARM\\ARMCM3\\Source\\ARM\\ARMCM3_ac6.sct\" version=\"1.0.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\ARMCM3_ac6.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM3\\Source\\startup_ARMCM3.c\" version=\"2.0.3\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\startup_ARMCM3.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM3\\Source\\system_ARMCM3.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\system_ARMCM3.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/CMSIS/RTX_Config.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.2.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration\n *\n * -----------------------------------------------------------------------------\n */\n \n#include \"cmsis_compiler.h\"\n#include \"rtx_os.h\"\n \n// OS Idle Thread\n__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n\n  for (;;) {}\n}\n \n// OS Error Callback function\n__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {\n  (void)object_id;\n\n  switch (code) {\n    case osRtxErrorStackOverflow:\n      // Stack overflow detected for thread (thread_id=object_id)\n      break;\n    case osRtxErrorISRQueueOverflow:\n      // ISR Queue overflow detected when inserting object (object_id)\n      break;\n    case osRtxErrorTimerQueueOverflow:\n      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)\n      break;\n    case osRtxErrorClibSpace:\n      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM\n      break;\n    case osRtxErrorClibMutex:\n      // Standard C/C++ library mutex initialization failed\n      break;\n    case osRtxErrorSVC:\n      // Invalid SVC function called (function=object_id)\n      break;\n    default:\n      // Reserved\n      break;\n  }\n  for (;;) {}\n//return 0U;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/CMSIS/RTX_Config.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.6.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration definitions\n *\n * -----------------------------------------------------------------------------\n */\n \n#ifndef RTX_CONFIG_H_\n#define RTX_CONFIG_H_\n \n#ifdef   _RTE_\n#include \"RTE_Components.h\"\n#ifdef    RTE_RTX_CONFIG_H\n#include  RTE_RTX_CONFIG_H\n#endif\n#endif\n \n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n \n// <h>System Configuration\n// =======================\n \n//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>\n//   <i> Defines the combined global dynamic memory size.\n//   <i> Default: 32768\n#ifndef OS_DYNAMIC_MEM_SIZE\n#define OS_DYNAMIC_MEM_SIZE         4096\n#endif\n \n//   <o>Kernel Tick Frequency [Hz] <1-1000000>\n//   <i> Defines base time unit for delays and timeouts.\n//   <i> Default: 1000 (1ms tick)\n#ifndef OS_TICK_FREQ\n#define OS_TICK_FREQ                1000\n#endif\n \n//   <e>Round-Robin Thread switching\n//   <i> Enables Round-Robin Thread switching.\n#ifndef OS_ROBIN_ENABLE\n#define OS_ROBIN_ENABLE             1\n#endif\n \n//     <o>Round-Robin Timeout <1-1000>\n//     <i> Defines how many ticks a thread will execute before a thread switch.\n//     <i> Default: 5\n#ifndef OS_ROBIN_TIMEOUT\n#define OS_ROBIN_TIMEOUT            5\n#endif\n \n//   </e>\n \n//   <e>Safety features (Source variant only)\n//   <i> Enables FuSa related features.\n//   <i> Requires RTX Source variant.\n//   <i> Enables:\n//   <i>  - selected features from this group\n//   <i>  - Thread functions: osThreadProtectPrivileged\n#ifndef OS_SAFETY_FEATURES\n#define OS_SAFETY_FEATURES          0\n#endif\n \n//     <q>Safety Class\n//     <i> Threads assigned to lower classes cannot modify higher class threads.\n//     <i> Enables:\n//     <i>  - Object attributes: osSafetyClass\n//     <i>  - Kernel functions: osKernelProtect, osKernelDestroyClass\n//     <i>  - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass\n#ifndef OS_SAFETY_CLASS\n#define OS_SAFETY_CLASS             1\n#endif\n \n//     <q>MPU Protected Zone\n//     <i> Access protection via MPU (Spatial isolation).\n//     <i> Enables:\n//     <i>  - Thread attributes: osThreadZone\n//     <i>  - Thread functions: osThreadGetZone, osThreadTerminateZone\n//     <i>  - Zone Management: osZoneSetup_Callback\n#ifndef OS_EXECUTION_ZONE\n#define OS_EXECUTION_ZONE           1\n#endif\n \n//     <q>Thread Watchdog\n//     <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).\n//     <i> Enables:\n//     <i>  - Thread functions: osThreadFeedWatchdog\n//     <i>  - Handler functions: osWatchdogAlarm_Handler\n#ifndef OS_THREAD_WATCHDOG\n#define OS_THREAD_WATCHDOG          1\n#endif\n \n//     <q>Object Pointer checking\n//     <i> Check object pointer alignment and memory region.\n#ifndef OS_OBJ_PTR_CHECK\n#define OS_OBJ_PTR_CHECK            0\n#endif\n \n//     <q>SVC Function Pointer checking\n//     <i> Check SVC function pointer alignment and memory region.\n//     <i> User needs to define a linker execution region RTX_SVC_VENEERS\n//     <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)\n#ifndef OS_SVC_PTR_CHECK\n#define OS_SVC_PTR_CHECK            0\n#endif\n \n//   </e>\n \n//   <o>ISR FIFO Queue\n//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries\n//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries\n//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries\n//   <i> RTOS Functions called from ISR store requests to this buffer.\n//   <i> Default: 16 entries\n#ifndef OS_ISR_FIFO_QUEUE\n#define OS_ISR_FIFO_QUEUE           16\n#endif\n \n//   <q>Object Memory usage counters\n//   <i> Enables object memory usage counters (requires RTX source variant).\n#ifndef OS_OBJ_MEM_USAGE\n#define OS_OBJ_MEM_USAGE            0\n#endif\n \n// </h>\n \n// <h>Thread Configuration\n// =======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_THREAD_OBJ_MEM\n#define OS_THREAD_OBJ_MEM           0\n#endif\n \n//     <o>Number of user Threads <1-1000>\n//     <i> Defines maximum number of user threads that can be active at the same time.\n//     <i> Applies to user threads with system provided memory for control blocks.\n#ifndef OS_THREAD_NUM\n#define OS_THREAD_NUM               1\n#endif\n \n//     <o>Number of user Threads with default Stack size <0-1000>\n//     <i> Defines maximum number of user threads with default stack size.\n//     <i> Applies to user threads with zero stack size specified.\n#ifndef OS_THREAD_DEF_STACK_NUM\n#define OS_THREAD_DEF_STACK_NUM     0\n#endif\n \n//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>\n//     <i> Defines the combined stack size for user threads with user-provided stack size.\n//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.\n//     <i> Default: 0\n#ifndef OS_THREAD_USER_STACK_SIZE\n#define OS_THREAD_USER_STACK_SIZE   0\n#endif\n \n//   </e>\n \n//   <o>Default Thread Stack size [bytes] <96-1073741824:8>\n//   <i> Defines stack size for threads with zero stack size specified.\n//   <i> Default: 3072\n#ifndef OS_STACK_SIZE\n#define OS_STACK_SIZE               512\n#endif\n \n//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>\n//   <i> Defines stack size for Idle thread.\n//   <i> Default: 512\n#ifndef OS_IDLE_THREAD_STACK_SIZE\n#define OS_IDLE_THREAD_STACK_SIZE   512\n#endif\n \n//   <o>Idle Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_IDLE_THREAD_TZ_MOD_ID\n#define OS_IDLE_THREAD_TZ_MOD_ID    0\n#endif\n \n//   <o>Idle Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_CLASS\n#define OS_IDLE_THREAD_CLASS        0\n#endif\n \n//   <o>Idle Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_ZONE\n#define OS_IDLE_THREAD_ZONE         0\n#endif\n \n//   <q>Stack overrun checking\n//   <i> Enables stack overrun check at thread switch (requires RTX source variant).\n//   <i> Enabling this option increases slightly the execution time of a thread switch.\n#ifndef OS_STACK_CHECK\n#define OS_STACK_CHECK              1\n#endif\n \n//   <q>Stack usage watermark\n//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.\n//   <i> Enabling this option increases significantly the execution time of thread creation.\n#ifndef OS_STACK_WATERMARK\n#define OS_STACK_WATERMARK          0\n#endif\n \n//   <o>Default Processor mode for Thread execution\n//     <0=> Unprivileged mode\n//     <1=> Privileged mode\n//   <i> Default: Unprivileged mode\n#ifndef OS_PRIVILEGE_MODE\n#define OS_PRIVILEGE_MODE           0\n#endif\n \n// </h>\n \n// <h>Timer Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_TIMER_OBJ_MEM\n#define OS_TIMER_OBJ_MEM            0\n#endif\n \n//     <o>Number of Timer objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_TIMER_NUM\n#define OS_TIMER_NUM                1\n#endif\n \n//   </e>\n \n//   <o>Timer Thread Priority\n//      <8=> Low\n//     <16=> Below Normal  <24=> Normal  <32=> Above Normal\n//     <40=> High\n//     <48=> Realtime\n//   <i> Defines priority for timer thread\n//   <i> Default: High\n#ifndef OS_TIMER_THREAD_PRIO\n#define OS_TIMER_THREAD_PRIO        40\n#endif\n \n//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>\n//   <i> Defines stack size for Timer thread.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 512\n#ifndef OS_TIMER_THREAD_STACK_SIZE\n#define OS_TIMER_THREAD_STACK_SIZE  512\n#endif\n \n//   <o>Timer Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_TIMER_THREAD_TZ_MOD_ID\n#define OS_TIMER_THREAD_TZ_MOD_ID   0\n#endif\n \n//   <o>Timer Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_CLASS\n#define OS_TIMER_THREAD_CLASS       0\n#endif\n \n//   <o>Timer Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_ZONE\n#define OS_TIMER_THREAD_ZONE        0\n#endif\n \n//   <o>Timer Callback Queue entries <0-256>\n//   <i> Number of concurrent active timer callback functions.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 4\n#ifndef OS_TIMER_CB_QUEUE\n#define OS_TIMER_CB_QUEUE           4\n#endif\n \n// </h>\n \n// <h>Event Flags Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_EVFLAGS_OBJ_MEM\n#define OS_EVFLAGS_OBJ_MEM          0\n#endif\n \n//     <o>Number of Event Flags objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_EVFLAGS_NUM\n#define OS_EVFLAGS_NUM              1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Mutex Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MUTEX_OBJ_MEM\n#define OS_MUTEX_OBJ_MEM            0\n#endif\n \n//     <o>Number of Mutex objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MUTEX_NUM\n#define OS_MUTEX_NUM                1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Semaphore Configuration\n// ==========================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_SEMAPHORE_OBJ_MEM\n#define OS_SEMAPHORE_OBJ_MEM        0\n#endif\n \n//     <o>Number of Semaphore objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_SEMAPHORE_NUM\n#define OS_SEMAPHORE_NUM            1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Memory Pool Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MEMPOOL_OBJ_MEM\n#define OS_MEMPOOL_OBJ_MEM          0\n#endif\n \n//     <o>Number of Memory Pool objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MEMPOOL_NUM\n#define OS_MEMPOOL_NUM              1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MEMPOOL_DATA_SIZE\n#define OS_MEMPOOL_DATA_SIZE        0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Message Queue Configuration\n// ==============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MSGQUEUE_OBJ_MEM\n#define OS_MSGQUEUE_OBJ_MEM         0\n#endif\n \n//     <o>Number of Message Queue objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MSGQUEUE_NUM\n#define OS_MSGQUEUE_NUM             1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MSGQUEUE_DATA_SIZE\n#define OS_MSGQUEUE_DATA_SIZE       0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Event Recorder Configuration\n// ===============================\n \n//   <e>Global Initialization\n//   <i> Initialize Event Recorder during 'osKernelInitialize'.\n#ifndef OS_EVR_INIT\n#define OS_EVR_INIT                 1\n#endif\n \n//     <q>Start recording\n//     <i> Start event recording after initialization.\n#ifndef OS_EVR_START\n#define OS_EVR_START                1\n#endif\n \n//     <h>Global Event Filter Setup\n//     <i> Initial recording level applied to all components.\n//       <o.0>Error events\n//       <o.1>API function call events\n//       <o.2>Operation events\n//       <o.3>Detailed operation events\n//     </h>\n#ifndef OS_EVR_LEVEL\n#define OS_EVR_LEVEL                0x00U\n#endif\n \n//     <h>RTOS Event Filter Setup\n//     <i> Recording levels for RTX components.\n//     <i> Only applicable if events for the respective component are generated.\n \n//       <e.7>Memory Management\n//       <i> Recording level for Memory Management events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMORY_LEVEL\n#define OS_EVR_MEMORY_LEVEL         0x81U\n#endif\n \n//       <e.7>Kernel\n//       <i> Recording level for Kernel events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_KERNEL_LEVEL\n#define OS_EVR_KERNEL_LEVEL         0x81U\n#endif\n \n//       <e.7>Thread\n//       <i> Recording level for Thread events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THREAD_LEVEL\n#define OS_EVR_THREAD_LEVEL         0x85U\n#endif\n \n//       <e.7>Generic Wait\n//       <i> Recording level for Generic Wait events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_WAIT_LEVEL\n#define OS_EVR_WAIT_LEVEL           0x81U\n#endif\n \n//       <e.7>Thread Flags\n//       <i> Recording level for Thread Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THFLAGS_LEVEL\n#define OS_EVR_THFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Event Flags\n//       <i> Recording level for Event Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_EVFLAGS_LEVEL\n#define OS_EVR_EVFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Timer\n//       <i> Recording level for Timer events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_TIMER_LEVEL\n#define OS_EVR_TIMER_LEVEL          0x81U\n#endif\n \n//       <e.7>Mutex\n//       <i> Recording level for Mutex events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MUTEX_LEVEL\n#define OS_EVR_MUTEX_LEVEL          0x81U\n#endif\n \n//       <e.7>Semaphore\n//       <i> Recording level for Semaphore events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_SEMAPHORE_LEVEL\n#define OS_EVR_SEMAPHORE_LEVEL      0x81U\n#endif\n \n//       <e.7>Memory Pool\n//       <i> Recording level for Memory Pool events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMPOOL_LEVEL\n#define OS_EVR_MEMPOOL_LEVEL        0x81U\n#endif\n \n//       <e.7>Message Queue\n//       <i> Recording level for Message Queue events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MSGQUEUE_LEVEL\n#define OS_EVR_MSGQUEUE_LEVEL       0x81U\n#endif\n \n//     </h>\n \n//   </e>\n \n//   <h>RTOS Event Generation\n//   <i> Enables event generation for RTX components (requires RTX source variant).\n \n//     <q>Memory Management\n//     <i> Enables Memory Management event generation.\n#ifndef OS_EVR_MEMORY\n#define OS_EVR_MEMORY               1\n#endif\n \n//     <q>Kernel\n//     <i> Enables Kernel event generation.\n#ifndef OS_EVR_KERNEL\n#define OS_EVR_KERNEL               1\n#endif\n \n//     <q>Thread\n//     <i> Enables Thread event generation.\n#ifndef OS_EVR_THREAD\n#define OS_EVR_THREAD               1\n#endif\n \n//     <q>Generic Wait\n//     <i> Enables Generic Wait event generation.\n#ifndef OS_EVR_WAIT\n#define OS_EVR_WAIT                 1\n#endif\n \n//     <q>Thread Flags\n//     <i> Enables Thread Flags event generation.\n#ifndef OS_EVR_THFLAGS\n#define OS_EVR_THFLAGS              1\n#endif\n \n//     <q>Event Flags\n//     <i> Enables Event Flags event generation.\n#ifndef OS_EVR_EVFLAGS\n#define OS_EVR_EVFLAGS              1\n#endif\n \n//     <q>Timer\n//     <i> Enables Timer event generation.\n#ifndef OS_EVR_TIMER\n#define OS_EVR_TIMER                1\n#endif\n \n//     <q>Mutex\n//     <i> Enables Mutex event generation.\n#ifndef OS_EVR_MUTEX\n#define OS_EVR_MUTEX                1\n#endif\n \n//     <q>Semaphore\n//     <i> Enables Semaphore event generation.\n#ifndef OS_EVR_SEMAPHORE\n#define OS_EVR_SEMAPHORE            1\n#endif\n \n//     <q>Memory Pool\n//     <i> Enables Memory Pool event generation.\n#ifndef OS_EVR_MEMPOOL\n#define OS_EVR_MEMPOOL              1\n#endif\n \n//     <q>Message Queue\n//     <i> Enables Message Queue event generation.\n#ifndef OS_EVR_MSGQUEUE\n#define OS_EVR_MSGQUEUE             1\n#endif\n \n//   </h>\n \n// </h>\n \n// Number of Threads which use standard C/C++ library libspace\n// (when thread specific memory allocation is not used).\n#if (OS_THREAD_OBJ_MEM == 0)\n#ifndef OS_THREAD_LIBSPACE_NUM\n#define OS_THREAD_LIBSPACE_NUM      4\n#endif\n#else\n#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM\n#endif\n \n//------------- <<< end of configuration section >>> ---------------------------\n \n#endif  // RTX_CONFIG_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/Compiler/EventRecorderConf.h",
    "content": "/*------------------------------------------------------------------------------\n * MDK - Component ::Event Recorder\n * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.\n *------------------------------------------------------------------------------\n * Name:    EventRecorderConf.h\n * Purpose: Event Recorder Configuration\n * Rev.:    V1.1.0\n *----------------------------------------------------------------------------*/\n\n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n\n// <h>Event Recorder\n\n//   <o>Number of Records\n//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024\n//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768\n//     <65536=>65536\n//   <i>Configures size of Event Record Buffer (each record is 16 bytes)\n//   <i>Must be 2^n (min=8, max=65536)\n#define EVENT_RECORD_COUNT      64U\n\n//   <o>Time Stamp Source\n//      <0=> DWT Cycle Counter  <1=> SysTick  <2=> CMSIS-RTOS2 System Timer\n//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)\n//   <i>Selects source for 32-bit time stamp\n#define EVENT_TIMESTAMP_SOURCE  2\n\n//   <o>Time Stamp Clock Frequency [Hz] <0-1000000000>\n//   <i>Defines initial time stamp clock frequency (0 when not used)\n#define EVENT_TIMESTAMP_FREQ    0U\n\n// </h>\n\n//------------- <<< end of configuration section >>> ---------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/Device/ARMCM3/ARMCM3_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00040000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Event Recorder Configuration -------------------------\n; <h> Event Recorder Configuration\n;   <o> Event Recorder RAM Size (in Bytes) <0x0-0xFFFFFFFF:16>\n;   <i> Memory requirement = 256 + (16 x Number_of_Records)\n;   <i> (defined by EVENT_RECORD_COUNT in EventRecorderConf.h)\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_EVR_SIZE  0x00000800\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  Stack, Heap and Event Recorder boundary definitions\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after previous section, 8 byte aligned */\n#define __RAM_EVR_BASE (AlignExpr(+0, 4))           /* starts after previous section, 4 byte aligned */\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __RAM_EVR_SIZE - __HEAP_SIZE - __STACK_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __RAM_EVR_SIZE > 0\n  RW_EVR __RAM_EVR_BASE UNINIT __RAM_EVR_SIZE {     ; Event Recorder RAM region\n    EventRecorder.o (+ZI)\n  }\n#endif\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/Device/ARMCM3/startup_ARMCM3.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM3.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M3 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM3)\n  #include \"ARMCM3.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MemPool/RTE/Device/ARMCM3/system_ARMCM3.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM3.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM3 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM3.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MemPool/main.c",
    "content": "/* -------------------------------------------------------------------------- \n * Copyright (c) 2013-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    main.c\n *      Purpose: RTX example program\n *\n *---------------------------------------------------------------------------*/\n\n#include <stdio.h>\n\n#include \"RTE_Components.h\"\n#include  CMSIS_device_header\n#include \"cmsis_os2.h\"\n\nvoid app_main (void *argument);\nvoid app_msg (void *argument);\n\ntypedef struct msg_s {\n  uint8_t cmd;\n  uint8_t len;\n  uint8_t data[8];\n} msg_t;\n\nstatic osMessageQueueId_t msgQueue;\nstatic osMemoryPoolId_t memPool;\n\nstatic const osThreadAttr_t msgAttr = {\n  .stack_size = 400U\n};\n\n/*----------------------------------------------------------------------------\n * Application main thread\n *---------------------------------------------------------------------------*/\n\nvoid app_main (void *argument) {\n  (void)argument;\n\n  osStatus_t status;\n  uint32_t cnt = 0UL;\n  msg_t* msg;\n\n  while (1) {\n    // Allocate memory for the message\n    msg = osMemoryPoolAlloc(memPool, osWaitForever);\n    if (msg == NULL) {\n      printf(\"app_msg: osMemoryPoolAlloc failed.\\n\");\n      continue;\n    }\n\n    // Produce a new message and put it to the queue\n    ++cnt;\n    msg->cmd = 1U;\n    msg->len = 4U;\n    *((uint32_t*)(msg->data)) = cnt;\n    status = osMessageQueuePut(msgQueue, &msg, 0U, osWaitForever);\n    if (status != osOK) {\n      printf(\"app_main: osMessageQueuePut failed.\\n\");\n    }\n\n    // Defer message creation\n    osDelay(osMessageQueueGetCount(msgQueue)*100U);\n  }\n}\n\n/*----------------------------------------------------------------------------\n * Application message receiver thread\n *---------------------------------------------------------------------------*/\n\nvoid app_msg (void *argument) {\n  (void)argument;\n\n  osStatus_t status;\n  uint32_t cnt;\n  msg_t* msg;\n\n  while (1) {\n    // Defer message processing\n    osDelay(osMessageQueueGetSpace(msgQueue)*100U);\n\n    // Wait forever until a message could be received\n    status = osMessageQueueGet(msgQueue, &msg, NULL, osWaitForever);\n    if (status != osOK) {\n      printf(\"app_msg: osMessageQueueGet failed.\\n\");\n    } else {\n      if (msg->len == 4U) {\n        cnt = *((uint32_t*)(msg->data));\n      }\n      printf(\"app_msg: received [cmd = %d, data = 0x%0X]\\n\", msg->cmd, cnt);\n      \n      // Free memory of the message\n      status = osMemoryPoolFree(memPool, msg);\n      if (status != osOK) {\n        printf(\"app_msg: osMemoryPoolFree failed.\\n\");\n      }\n    }\n  }\n}\n\n/*----------------------------------------------------------------------------\n * Main entry\n *---------------------------------------------------------------------------*/\n\nint main (void) {\n\n  // System Initialization\n  SystemCoreClockUpdate();\n\n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  osThreadNew(app_msg, NULL, &msgAttr); // Create message receiver thread\n\n  // Create message queue used to pass pointers to msg_t\n  msgQueue = osMessageQueueNew(10U, sizeof(msg_t*), NULL);\n  \n  // Create memory pool for actual message objects\n  memPool = osMemoryPoolNew(10U, sizeof(msg_t), NULL);\n\n  osKernelStart();                      // Start thread execution\n  for (;;) {}\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Abstract.txt",
    "content": "The RTX_Blinky project is a simple RTX Kernel based example\nfor a simulated Cortex-M3 device\n\nExample functionality:\n - Clock Settings:\n   - XTAL    =  50 MHz\n   - Core    =  25 MHz\n\nThe simple RTX Kernel based example simulates the step-motor \ndriver. Four LEDs are blinking simulating the activation of \nthe four output driver stages\nThe simulation does not provide LEDs, so the state changes\nare output on the Debug printf window:\n\n- phase A\n- phase B\n- phase C\n- phase D\n\nThis example simulates Half step driver mode and\nCW rotation direction.\n\n\nThe BLINKY example program is available for one target:\n\n  Simulation:          configured for a simulated on-chip Flash\n\nThe example is compatible with other Cortex-M class devices.\nSimply open the project settings, navigate to Device tab and\nselect another Cortex-M class device.\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.c",
    "content": "/* -------------------------------------------------------------------------- \n * Copyright (c) 2013-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    Blinky.c\n *      Purpose: RTX example program\n *\n *---------------------------------------------------------------------------*/\n\n#include <stdio.h>\n\n#include \"cmsis_os.h\"                   // ARM::CMSIS:RTOS:Keil RTX5\n#include \"cmsis_os2.h\"                  // ARM::CMSIS:RTOS2:Keil RTX5\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\nosThreadId_t tid_phaseA;                /* Thread id of thread: phase_a      */\nosThreadId_t tid_phaseB;                /* Thread id of thread: phase_b      */\nosThreadId_t tid_phaseC;                /* Thread id of thread: phase_c      */\nosThreadId_t tid_phaseD;                /* Thread id of thread: phase_d      */\nosThreadId_t tid_clock;                 /* Thread id of thread: clock        */\n\nstruct phases_t {\n  int_fast8_t phaseA;\n  int_fast8_t phaseB;\n  int_fast8_t phaseC;\n  int_fast8_t phaseD;\n} g_phases;\n\n\n/*----------------------------------------------------------------------------\n *      Switch LED on\n *---------------------------------------------------------------------------*/\nvoid Switch_On (unsigned char led) {\n  printf(\"LED On:  #%d\\n\\r\", led);\n}\n\n/*----------------------------------------------------------------------------\n *      Switch LED off\n *---------------------------------------------------------------------------*/\nvoid Switch_Off (unsigned char led) {\n  printf(\"LED Off: #%d\\n\\r\", led);\n}\n\n\n/*----------------------------------------------------------------------------\n *      Function 'signal_func' called from multiple threads\n *---------------------------------------------------------------------------*/\nvoid signal_func (osThreadId_t tid)  {\n  osThreadFlagsSet(tid_clock, 0x0100);      /* set signal to clock thread    */\n  osDelay(500);                             /* delay 500ms                   */\n  osThreadFlagsSet(tid_clock, 0x0100);      /* set signal to clock thread    */\n  osDelay(500);                             /* delay 500ms                   */\n  osThreadFlagsSet(tid, 0x0001);            /* set signal to thread 'thread' */\n  osDelay(500);                             /* delay 500ms                   */\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 1 'phaseA': Phase A output\n *---------------------------------------------------------------------------*/\nvoid phaseA (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny ,osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(0);\n    g_phases.phaseA = 1;\n    signal_func(tid_phaseB);                                     /* call common signal function   */\n    g_phases.phaseA = 0;\n    Switch_Off(0);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 2 'phaseB': Phase B output\n *---------------------------------------------------------------------------*/\nvoid phaseB (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(1);\n    g_phases.phaseB = 1;\n    signal_func(tid_phaseC);                /* call common signal function   */\n    g_phases.phaseB = 0;\n    Switch_Off(1);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 3 'phaseC': Phase C output\n *---------------------------------------------------------------------------*/\nvoid phaseC (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(2);\n    g_phases.phaseC = 1;\n    signal_func(tid_phaseD);                /* call common signal function   */\n    g_phases.phaseC = 0;\n    Switch_Off(2);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 4 'phaseD': Phase D output\n *---------------------------------------------------------------------------*/\nvoid phaseD (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(3);\n    g_phases.phaseD = 1;\n    signal_func(tid_phaseA);                /* call common signal function   */\n    g_phases.phaseD = 0;\n    Switch_Off(3);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 5 'clock': Signal Clock\n *---------------------------------------------------------------------------*/\nvoid clock (void const *argument) {\n  for (;;) {\n    osSignalWait(0x0100, osWaitForever);    /* wait for an event flag 0x0100 */\n    osDelay(80);                            /* delay  80ms                   */\n  }\n}\n\n/* Define the API v1 thread */\nosThreadDef(clock,  osPriorityNormal, 1, 0);\n\n/*----------------------------------------------------------------------------\n *      Main: Initialize and start RTX Kernel\n *---------------------------------------------------------------------------*/\nvoid app_main (void *argument) {\n\n  tid_phaseA = osThreadNew(phaseA, NULL, NULL);\n  tid_phaseB = osThreadNew(phaseB, NULL, NULL);\n  tid_phaseC = osThreadNew(phaseC, NULL, NULL);\n  tid_phaseD = osThreadNew(phaseD, NULL, NULL);\n  tid_clock  = osThreadCreate(osThread(clock),  NULL);\n\n  osThreadFlagsSet(tid_phaseA, 0x0001);     /* set signal to phaseA thread   */\n\n  osDelay(osWaitForever);\n}\n\nint main (void) {\n\n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  if (osKernelGetState() == osKernelReady) {\n    osKernelStart();                    // Start thread execution\n  }\n\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvguix",
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  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/Blinky.uvprojx",
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<StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>7</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>3</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>1</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>3</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>0</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile>.\\RTE\\Device\\ARMCM3\\ARMCM3_ac6.sct</ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Source Files</GroupName>\n          <Files>\n            <File>\n              <FileName>Blinky.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\Blinky.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Documentation</GroupName>\n          <Files>\n            <File>\n              <FileName>Abstract.txt</FileName>\n              <FileType>5</FileType>\n              <FilePath>.\\Abstract.txt</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Compiler</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Device</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis>\n      <api Capiversion=\"1.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS\" exclusive=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.0.0-Beta15\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </api>\n      <api Capiversion=\"2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" exclusive=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.0.0-Beta11\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </api>\n    </apis>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.4.0\" condition=\"ARMv6_7_8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n      <component Capiversion=\"1.0.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS\" Csub=\"Keil RTX5\" Cvendor=\"ARM\" Cversion=\"5.5.3\" condition=\"RTOS RTX5\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n      <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Library\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n      <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n      <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"Event Recorder\" Cvariant=\"DAP\" Cvendor=\"Keil\" Cversion=\"1.4.0\" condition=\"Cortex-M Device\">\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.6.3\" url=\"http://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.6.3\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n      <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"I/O\" Csub=\"STDOUT\" Cvariant=\"EVR\" Cvendor=\"Keil\" Cversion=\"1.2.0\" condition=\"ARMCC Cortex-M with EVR\">\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.6.3\" url=\"http://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.6.3\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files>\n      <file attr=\"config\" category=\"source\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.c\" version=\"5.2.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.c</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Library\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.h\" version=\"5.6.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.h</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Library\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"Config\\EventRecorderConf.h\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Compiler\\EventRecorderConf.h</instance>\n        <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"Event Recorder\" Cvariant=\"DAP\" Cvendor=\"Keil\" Cversion=\"1.5.1\" condition=\"Cortex-M Device\"/>\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.7.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"linkerScript\" condition=\"ARMCC6\" name=\"Device\\ARM\\ARMCM3\\Source\\ARM\\ARMCM3_ac6.sct\" version=\"1.0.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\ARMCM3_ac6.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM3\\Source\\startup_ARMCM3.c\" version=\"2.0.3\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\startup_ARMCM3.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM3\\Source\\system_ARMCM3.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\system_ARMCM3.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulation\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/CMSIS/RTX_Config.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.2.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration\n *\n * -----------------------------------------------------------------------------\n */\n \n#include \"cmsis_compiler.h\"\n#include \"rtx_os.h\"\n \n// OS Idle Thread\n__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n\n  for (;;) {}\n}\n \n// OS Error Callback function\n__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {\n  (void)object_id;\n\n  switch (code) {\n    case osRtxErrorStackOverflow:\n      // Stack overflow detected for thread (thread_id=object_id)\n      break;\n    case osRtxErrorISRQueueOverflow:\n      // ISR Queue overflow detected when inserting object (object_id)\n      break;\n    case osRtxErrorTimerQueueOverflow:\n      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)\n      break;\n    case osRtxErrorClibSpace:\n      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM\n      break;\n    case osRtxErrorClibMutex:\n      // Standard C/C++ library mutex initialization failed\n      break;\n    case osRtxErrorSVC:\n      // Invalid SVC function called (function=object_id)\n      break;\n    default:\n      // Reserved\n      break;\n  }\n  for (;;) {}\n//return 0U;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/CMSIS/RTX_Config.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.6.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration definitions\n *\n * -----------------------------------------------------------------------------\n */\n \n#ifndef RTX_CONFIG_H_\n#define RTX_CONFIG_H_\n \n#ifdef   _RTE_\n#include \"RTE_Components.h\"\n#ifdef    RTE_RTX_CONFIG_H\n#include  RTE_RTX_CONFIG_H\n#endif\n#endif\n \n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n \n// <h>System Configuration\n// =======================\n \n//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>\n//   <i> Defines the combined global dynamic memory size.\n//   <i> Default: 32768\n#ifndef OS_DYNAMIC_MEM_SIZE\n#define OS_DYNAMIC_MEM_SIZE         4096\n#endif\n \n//   <o>Kernel Tick Frequency [Hz] <1-1000000>\n//   <i> Defines base time unit for delays and timeouts.\n//   <i> Default: 1000 (1ms tick)\n#ifndef OS_TICK_FREQ\n#define OS_TICK_FREQ                1000\n#endif\n \n//   <e>Round-Robin Thread switching\n//   <i> Enables Round-Robin Thread switching.\n#ifndef OS_ROBIN_ENABLE\n#define OS_ROBIN_ENABLE             1\n#endif\n \n//     <o>Round-Robin Timeout <1-1000>\n//     <i> Defines how many ticks a thread will execute before a thread switch.\n//     <i> Default: 5\n#ifndef OS_ROBIN_TIMEOUT\n#define OS_ROBIN_TIMEOUT            5\n#endif\n \n//   </e>\n \n//   <e>Safety features (Source variant only)\n//   <i> Enables FuSa related features.\n//   <i> Requires RTX Source variant.\n//   <i> Enables:\n//   <i>  - selected features from this group\n//   <i>  - Thread functions: osThreadProtectPrivileged\n#ifndef OS_SAFETY_FEATURES\n#define OS_SAFETY_FEATURES          0\n#endif\n \n//     <q>Safety Class\n//     <i> Threads assigned to lower classes cannot modify higher class threads.\n//     <i> Enables:\n//     <i>  - Object attributes: osSafetyClass\n//     <i>  - Kernel functions: osKernelProtect, osKernelDestroyClass\n//     <i>  - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass\n#ifndef OS_SAFETY_CLASS\n#define OS_SAFETY_CLASS             1\n#endif\n \n//     <q>MPU Protected Zone\n//     <i> Access protection via MPU (Spatial isolation).\n//     <i> Enables:\n//     <i>  - Thread attributes: osThreadZone\n//     <i>  - Thread functions: osThreadGetZone, osThreadTerminateZone\n//     <i>  - Zone Management: osZoneSetup_Callback\n#ifndef OS_EXECUTION_ZONE\n#define OS_EXECUTION_ZONE           1\n#endif\n \n//     <q>Thread Watchdog\n//     <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).\n//     <i> Enables:\n//     <i>  - Thread functions: osThreadFeedWatchdog\n//     <i>  - Handler functions: osWatchdogAlarm_Handler\n#ifndef OS_THREAD_WATCHDOG\n#define OS_THREAD_WATCHDOG          1\n#endif\n \n//     <q>Object Pointer checking\n//     <i> Check object pointer alignment and memory region.\n#ifndef OS_OBJ_PTR_CHECK\n#define OS_OBJ_PTR_CHECK            0\n#endif\n \n//     <q>SVC Function Pointer checking\n//     <i> Check SVC function pointer alignment and memory region.\n//     <i> User needs to define a linker execution region RTX_SVC_VENEERS\n//     <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)\n#ifndef OS_SVC_PTR_CHECK\n#define OS_SVC_PTR_CHECK            0\n#endif\n \n//   </e>\n \n//   <o>ISR FIFO Queue\n//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries\n//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries\n//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries\n//   <i> RTOS Functions called from ISR store requests to this buffer.\n//   <i> Default: 16 entries\n#ifndef OS_ISR_FIFO_QUEUE\n#define OS_ISR_FIFO_QUEUE           16\n#endif\n \n//   <q>Object Memory usage counters\n//   <i> Enables object memory usage counters (requires RTX source variant).\n#ifndef OS_OBJ_MEM_USAGE\n#define OS_OBJ_MEM_USAGE            0\n#endif\n \n// </h>\n \n// <h>Thread Configuration\n// =======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_THREAD_OBJ_MEM\n#define OS_THREAD_OBJ_MEM           0\n#endif\n \n//     <o>Number of user Threads <1-1000>\n//     <i> Defines maximum number of user threads that can be active at the same time.\n//     <i> Applies to user threads with system provided memory for control blocks.\n#ifndef OS_THREAD_NUM\n#define OS_THREAD_NUM               1\n#endif\n \n//     <o>Number of user Threads with default Stack size <0-1000>\n//     <i> Defines maximum number of user threads with default stack size.\n//     <i> Applies to user threads with zero stack size specified.\n#ifndef OS_THREAD_DEF_STACK_NUM\n#define OS_THREAD_DEF_STACK_NUM     0\n#endif\n \n//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>\n//     <i> Defines the combined stack size for user threads with user-provided stack size.\n//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.\n//     <i> Default: 0\n#ifndef OS_THREAD_USER_STACK_SIZE\n#define OS_THREAD_USER_STACK_SIZE   0\n#endif\n \n//   </e>\n \n//   <o>Default Thread Stack size [bytes] <96-1073741824:8>\n//   <i> Defines stack size for threads with zero stack size specified.\n//   <i> Default: 3072\n#ifndef OS_STACK_SIZE\n#define OS_STACK_SIZE               512\n#endif\n \n//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>\n//   <i> Defines stack size for Idle thread.\n//   <i> Default: 512\n#ifndef OS_IDLE_THREAD_STACK_SIZE\n#define OS_IDLE_THREAD_STACK_SIZE   512\n#endif\n \n//   <o>Idle Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_IDLE_THREAD_TZ_MOD_ID\n#define OS_IDLE_THREAD_TZ_MOD_ID    0\n#endif\n \n//   <o>Idle Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_CLASS\n#define OS_IDLE_THREAD_CLASS        0\n#endif\n \n//   <o>Idle Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_ZONE\n#define OS_IDLE_THREAD_ZONE         0\n#endif\n \n//   <q>Stack overrun checking\n//   <i> Enables stack overrun check at thread switch (requires RTX source variant).\n//   <i> Enabling this option increases slightly the execution time of a thread switch.\n#ifndef OS_STACK_CHECK\n#define OS_STACK_CHECK              1\n#endif\n \n//   <q>Stack usage watermark\n//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.\n//   <i> Enabling this option increases significantly the execution time of thread creation.\n#ifndef OS_STACK_WATERMARK\n#define OS_STACK_WATERMARK          0\n#endif\n \n//   <o>Default Processor mode for Thread execution\n//     <0=> Unprivileged mode\n//     <1=> Privileged mode\n//   <i> Default: Unprivileged mode\n#ifndef OS_PRIVILEGE_MODE\n#define OS_PRIVILEGE_MODE           0\n#endif\n \n// </h>\n \n// <h>Timer Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_TIMER_OBJ_MEM\n#define OS_TIMER_OBJ_MEM            0\n#endif\n \n//     <o>Number of Timer objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_TIMER_NUM\n#define OS_TIMER_NUM                1\n#endif\n \n//   </e>\n \n//   <o>Timer Thread Priority\n//      <8=> Low\n//     <16=> Below Normal  <24=> Normal  <32=> Above Normal\n//     <40=> High\n//     <48=> Realtime\n//   <i> Defines priority for timer thread\n//   <i> Default: High\n#ifndef OS_TIMER_THREAD_PRIO\n#define OS_TIMER_THREAD_PRIO        40\n#endif\n \n//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>\n//   <i> Defines stack size for Timer thread.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 512\n#ifndef OS_TIMER_THREAD_STACK_SIZE\n#define OS_TIMER_THREAD_STACK_SIZE  512\n#endif\n \n//   <o>Timer Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_TIMER_THREAD_TZ_MOD_ID\n#define OS_TIMER_THREAD_TZ_MOD_ID   0\n#endif\n \n//   <o>Timer Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_CLASS\n#define OS_TIMER_THREAD_CLASS       0\n#endif\n \n//   <o>Timer Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_ZONE\n#define OS_TIMER_THREAD_ZONE        0\n#endif\n \n//   <o>Timer Callback Queue entries <0-256>\n//   <i> Number of concurrent active timer callback functions.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 4\n#ifndef OS_TIMER_CB_QUEUE\n#define OS_TIMER_CB_QUEUE           4\n#endif\n \n// </h>\n \n// <h>Event Flags Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_EVFLAGS_OBJ_MEM\n#define OS_EVFLAGS_OBJ_MEM          0\n#endif\n \n//     <o>Number of Event Flags objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_EVFLAGS_NUM\n#define OS_EVFLAGS_NUM              1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Mutex Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MUTEX_OBJ_MEM\n#define OS_MUTEX_OBJ_MEM            0\n#endif\n \n//     <o>Number of Mutex objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MUTEX_NUM\n#define OS_MUTEX_NUM                1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Semaphore Configuration\n// ==========================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_SEMAPHORE_OBJ_MEM\n#define OS_SEMAPHORE_OBJ_MEM        0\n#endif\n \n//     <o>Number of Semaphore objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_SEMAPHORE_NUM\n#define OS_SEMAPHORE_NUM            1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Memory Pool Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MEMPOOL_OBJ_MEM\n#define OS_MEMPOOL_OBJ_MEM          0\n#endif\n \n//     <o>Number of Memory Pool objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MEMPOOL_NUM\n#define OS_MEMPOOL_NUM              1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MEMPOOL_DATA_SIZE\n#define OS_MEMPOOL_DATA_SIZE        0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Message Queue Configuration\n// ==============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MSGQUEUE_OBJ_MEM\n#define OS_MSGQUEUE_OBJ_MEM         0\n#endif\n \n//     <o>Number of Message Queue objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MSGQUEUE_NUM\n#define OS_MSGQUEUE_NUM             1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MSGQUEUE_DATA_SIZE\n#define OS_MSGQUEUE_DATA_SIZE       0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Event Recorder Configuration\n// ===============================\n \n//   <e>Global Initialization\n//   <i> Initialize Event Recorder during 'osKernelInitialize'.\n#ifndef OS_EVR_INIT\n#define OS_EVR_INIT                 1\n#endif\n \n//     <q>Start recording\n//     <i> Start event recording after initialization.\n#ifndef OS_EVR_START\n#define OS_EVR_START                1\n#endif\n \n//     <h>Global Event Filter Setup\n//     <i> Initial recording level applied to all components.\n//       <o.0>Error events\n//       <o.1>API function call events\n//       <o.2>Operation events\n//       <o.3>Detailed operation events\n//     </h>\n#ifndef OS_EVR_LEVEL\n#define OS_EVR_LEVEL                0x00U\n#endif\n \n//     <h>RTOS Event Filter Setup\n//     <i> Recording levels for RTX components.\n//     <i> Only applicable if events for the respective component are generated.\n \n//       <e.7>Memory Management\n//       <i> Recording level for Memory Management events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMORY_LEVEL\n#define OS_EVR_MEMORY_LEVEL         0x81U\n#endif\n \n//       <e.7>Kernel\n//       <i> Recording level for Kernel events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_KERNEL_LEVEL\n#define OS_EVR_KERNEL_LEVEL         0x81U\n#endif\n \n//       <e.7>Thread\n//       <i> Recording level for Thread events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THREAD_LEVEL\n#define OS_EVR_THREAD_LEVEL         0x85U\n#endif\n \n//       <e.7>Generic Wait\n//       <i> Recording level for Generic Wait events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_WAIT_LEVEL\n#define OS_EVR_WAIT_LEVEL           0x81U\n#endif\n \n//       <e.7>Thread Flags\n//       <i> Recording level for Thread Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THFLAGS_LEVEL\n#define OS_EVR_THFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Event Flags\n//       <i> Recording level for Event Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_EVFLAGS_LEVEL\n#define OS_EVR_EVFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Timer\n//       <i> Recording level for Timer events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_TIMER_LEVEL\n#define OS_EVR_TIMER_LEVEL          0x81U\n#endif\n \n//       <e.7>Mutex\n//       <i> Recording level for Mutex events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MUTEX_LEVEL\n#define OS_EVR_MUTEX_LEVEL          0x81U\n#endif\n \n//       <e.7>Semaphore\n//       <i> Recording level for Semaphore events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_SEMAPHORE_LEVEL\n#define OS_EVR_SEMAPHORE_LEVEL      0x81U\n#endif\n \n//       <e.7>Memory Pool\n//       <i> Recording level for Memory Pool events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMPOOL_LEVEL\n#define OS_EVR_MEMPOOL_LEVEL        0x81U\n#endif\n \n//       <e.7>Message Queue\n//       <i> Recording level for Message Queue events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MSGQUEUE_LEVEL\n#define OS_EVR_MSGQUEUE_LEVEL       0x81U\n#endif\n \n//     </h>\n \n//   </e>\n \n//   <h>RTOS Event Generation\n//   <i> Enables event generation for RTX components (requires RTX source variant).\n \n//     <q>Memory Management\n//     <i> Enables Memory Management event generation.\n#ifndef OS_EVR_MEMORY\n#define OS_EVR_MEMORY               1\n#endif\n \n//     <q>Kernel\n//     <i> Enables Kernel event generation.\n#ifndef OS_EVR_KERNEL\n#define OS_EVR_KERNEL               1\n#endif\n \n//     <q>Thread\n//     <i> Enables Thread event generation.\n#ifndef OS_EVR_THREAD\n#define OS_EVR_THREAD               1\n#endif\n \n//     <q>Generic Wait\n//     <i> Enables Generic Wait event generation.\n#ifndef OS_EVR_WAIT\n#define OS_EVR_WAIT                 1\n#endif\n \n//     <q>Thread Flags\n//     <i> Enables Thread Flags event generation.\n#ifndef OS_EVR_THFLAGS\n#define OS_EVR_THFLAGS              1\n#endif\n \n//     <q>Event Flags\n//     <i> Enables Event Flags event generation.\n#ifndef OS_EVR_EVFLAGS\n#define OS_EVR_EVFLAGS              1\n#endif\n \n//     <q>Timer\n//     <i> Enables Timer event generation.\n#ifndef OS_EVR_TIMER\n#define OS_EVR_TIMER                1\n#endif\n \n//     <q>Mutex\n//     <i> Enables Mutex event generation.\n#ifndef OS_EVR_MUTEX\n#define OS_EVR_MUTEX                1\n#endif\n \n//     <q>Semaphore\n//     <i> Enables Semaphore event generation.\n#ifndef OS_EVR_SEMAPHORE\n#define OS_EVR_SEMAPHORE            1\n#endif\n \n//     <q>Memory Pool\n//     <i> Enables Memory Pool event generation.\n#ifndef OS_EVR_MEMPOOL\n#define OS_EVR_MEMPOOL              1\n#endif\n \n//     <q>Message Queue\n//     <i> Enables Message Queue event generation.\n#ifndef OS_EVR_MSGQUEUE\n#define OS_EVR_MSGQUEUE             1\n#endif\n \n//   </h>\n \n// </h>\n \n// Number of Threads which use standard C/C++ library libspace\n// (when thread specific memory allocation is not used).\n#if (OS_THREAD_OBJ_MEM == 0)\n#ifndef OS_THREAD_LIBSPACE_NUM\n#define OS_THREAD_LIBSPACE_NUM      4\n#endif\n#else\n#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM\n#endif\n \n//------------- <<< end of configuration section >>> ---------------------------\n \n#endif  // RTX_CONFIG_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Compiler/EventRecorderConf.h",
    "content": "/*------------------------------------------------------------------------------\n * MDK - Component ::Event Recorder\n * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.\n *------------------------------------------------------------------------------\n * Name:    EventRecorderConf.h\n * Purpose: Event Recorder Configuration\n * Rev.:    V1.1.0\n *----------------------------------------------------------------------------*/\n\n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n\n// <h>Event Recorder\n\n//   <o>Number of Records\n//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024\n//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768\n//     <65536=>65536\n//   <i>Configures size of Event Record Buffer (each record is 16 bytes)\n//   <i>Must be 2^n (min=8, max=65536)\n#define EVENT_RECORD_COUNT      64U\n\n//   <o>Time Stamp Source\n//      <0=> DWT Cycle Counter  <1=> SysTick  <2=> CMSIS-RTOS2 System Timer\n//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)\n//   <i>Selects source for 32-bit time stamp\n#define EVENT_TIMESTAMP_SOURCE  2\n\n//   <o>Time Stamp Clock Frequency [Hz] <0-1000000000>\n//   <i>Defines initial time stamp clock frequency (0 when not used)\n#define EVENT_TIMESTAMP_FREQ    25000000U\n\n// </h>\n\n//------------- <<< end of configuration section >>> ---------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/ARMCM3_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00040000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Event Recorder Configuration -------------------------\n; <h> Event Recorder Configuration\n;   <o> Event Recorder RAM Size (in Bytes) <0x0-0xFFFFFFFF:16>\n;   <i> Memory requirement = 256 + (16 x Number_of_Records)\n;   <i> (defined by EVENT_RECORD_COUNT in EventRecorderConf.h)\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_EVR_SIZE  0x00000800\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  Stack, Heap and Event Recorder boundary definitions\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after previous section, 8 byte aligned */\n#define __RAM_EVR_BASE (AlignExpr(+0, 4))           /* starts after previous section, 4 byte aligned */\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __RAM_EVR_SIZE - __HEAP_SIZE - __STACK_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __RAM_EVR_SIZE > 0\n  RW_EVR __RAM_EVR_BASE UNINIT __RAM_EVR_SIZE {     ; Event Recorder RAM region\n    EventRecorder.o (+ZI)\n  }\n#endif\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/startup_ARMCM3.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM3.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M3 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM3)\n  #include \"ARMCM3.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/Migration/RTE/Device/ARMCM3/system_ARMCM3.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM3.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM3 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM3.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MsgQueue/Abstract.txt",
    "content": "The MsgQueue project is a simple RTX Kernel based example\nfor a simulated Cortex-M3 device\n\nExample functionality:\n - Clock Settings:\n   - XTAL    =  12 MHz\n   - Core    =  12 MHz\n\nThe simple RTX Kernel based example shows how to use a \nmessage queue to send data from one thread to another.\nThe message receiver thread prints the message contents\nto the debug output window.\n\nThe MsgQueue example program is available for one target:\n\n  Simulation:          configured for a simulated on-chip Flash\n"
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         <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M3\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>1</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <RvdsMve>0</RvdsMve>\n            <RvdsCdeCp>0</RvdsCdeCp>\n            <nBranchProt>0</nBranchProt>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>1</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>0</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>7</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>3</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>1</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>3</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>0</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile>.\\RTE\\Device\\ARMCM3\\ARMCM3_ac6.sct</ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Source Group 1</GroupName>\n          <Files>\n            <File>\n              <FileName>main.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\main.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Documentation</GroupName>\n          <Files>\n            <File>\n              <FileName>Abstract.txt</FileName>\n              <FileType>5</FileType>\n              <FilePath>.\\Abstract.txt</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Compiler</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Device</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis>\n      <api Capiversion=\"2.1.1\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" exclusive=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.1.1-dev1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </api>\n    </apis>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.4.0\" condition=\"ARMv6_7_8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.7.0\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n      <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n      <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.7.0\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n      <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"Event Recorder\" Cvariant=\"DAP\" Cvendor=\"Keil\" Cversion=\"1.4.0\" condition=\"Cortex-M Device\">\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.4.9\" url=\"http://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.6.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n      <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"I/O\" Csub=\"STDOUT\" Cvariant=\"EVR\" Cvendor=\"Keil\" Cversion=\"1.2.0\" condition=\"ARMCC Cortex-M with EVR\">\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.4.9\" url=\"http://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.6.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files>\n      <file attr=\"config\" category=\"source\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.c\" version=\"5.2.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.c</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.h\" version=\"5.6.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.h</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"Config\\EventRecorderConf.h\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Compiler\\EventRecorderConf.h</instance>\n        <component Cbundle=\"ARM Compiler\" Cclass=\"Compiler\" Cgroup=\"Event Recorder\" Cvariant=\"DAP\" Cvendor=\"Keil\" Cversion=\"1.5.1\" condition=\"Cortex-M Device\"/>\n        <package name=\"ARM_Compiler\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"Keil\" version=\"1.7.2\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"linkerScript\" condition=\"ARMCC6\" name=\"Device\\ARM\\ARMCM3\\Source\\ARM\\ARMCM3_ac6.sct\" version=\"1.0.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\ARMCM3_ac6.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM3\\Source\\startup_ARMCM3.c\" version=\"2.0.3\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\startup_ARMCM3.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM3\\Source\\system_ARMCM3.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM3\\system_ARMCM3.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.0.3\" condition=\"ARMCM3 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"Simulator\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MsgQueue/RTE/CMSIS/RTX_Config.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.2.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration\n *\n * -----------------------------------------------------------------------------\n */\n \n#include \"cmsis_compiler.h\"\n#include \"rtx_os.h\"\n \n// OS Idle Thread\n__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n\n  for (;;) {}\n}\n \n// OS Error Callback function\n__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {\n  (void)object_id;\n\n  switch (code) {\n    case osRtxErrorStackOverflow:\n      // Stack overflow detected for thread (thread_id=object_id)\n      break;\n    case osRtxErrorISRQueueOverflow:\n      // ISR Queue overflow detected when inserting object (object_id)\n      break;\n    case osRtxErrorTimerQueueOverflow:\n      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)\n      break;\n    case osRtxErrorClibSpace:\n      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM\n      break;\n    case osRtxErrorClibMutex:\n      // Standard C/C++ library mutex initialization failed\n      break;\n    case osRtxErrorSVC:\n      // Invalid SVC function called (function=object_id)\n      break;\n    default:\n      // Reserved\n      break;\n  }\n  for (;;) {}\n//return 0U;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MsgQueue/RTE/CMSIS/RTX_Config.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.6.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration definitions\n *\n * -----------------------------------------------------------------------------\n */\n \n#ifndef RTX_CONFIG_H_\n#define RTX_CONFIG_H_\n \n#ifdef   _RTE_\n#include \"RTE_Components.h\"\n#ifdef    RTE_RTX_CONFIG_H\n#include  RTE_RTX_CONFIG_H\n#endif\n#endif\n \n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n \n// <h>System Configuration\n// =======================\n \n//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>\n//   <i> Defines the combined global dynamic memory size.\n//   <i> Default: 32768\n#ifndef OS_DYNAMIC_MEM_SIZE\n#define OS_DYNAMIC_MEM_SIZE         4096\n#endif\n \n//   <o>Kernel Tick Frequency [Hz] <1-1000000>\n//   <i> Defines base time unit for delays and timeouts.\n//   <i> Default: 1000 (1ms tick)\n#ifndef OS_TICK_FREQ\n#define OS_TICK_FREQ                1000\n#endif\n \n//   <e>Round-Robin Thread switching\n//   <i> Enables Round-Robin Thread switching.\n#ifndef OS_ROBIN_ENABLE\n#define OS_ROBIN_ENABLE             1\n#endif\n \n//     <o>Round-Robin Timeout <1-1000>\n//     <i> Defines how many ticks a thread will execute before a thread switch.\n//     <i> Default: 5\n#ifndef OS_ROBIN_TIMEOUT\n#define OS_ROBIN_TIMEOUT            5\n#endif\n \n//   </e>\n \n//   <e>Safety features (Source variant only)\n//   <i> Enables FuSa related features.\n//   <i> Requires RTX Source variant.\n//   <i> Enables:\n//   <i>  - selected features from this group\n//   <i>  - Thread functions: osThreadProtectPrivileged\n#ifndef OS_SAFETY_FEATURES\n#define OS_SAFETY_FEATURES          0\n#endif\n \n//     <q>Safety Class\n//     <i> Threads assigned to lower classes cannot modify higher class threads.\n//     <i> Enables:\n//     <i>  - Object attributes: osSafetyClass\n//     <i>  - Kernel functions: osKernelProtect, osKernelDestroyClass\n//     <i>  - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass\n#ifndef OS_SAFETY_CLASS\n#define OS_SAFETY_CLASS             1\n#endif\n \n//     <q>MPU Protected Zone\n//     <i> Access protection via MPU (Spatial isolation).\n//     <i> Enables:\n//     <i>  - Thread attributes: osThreadZone\n//     <i>  - Thread functions: osThreadGetZone, osThreadTerminateZone\n//     <i>  - Zone Management: osZoneSetup_Callback\n#ifndef OS_EXECUTION_ZONE\n#define OS_EXECUTION_ZONE           1\n#endif\n \n//     <q>Thread Watchdog\n//     <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).\n//     <i> Enables:\n//     <i>  - Thread functions: osThreadFeedWatchdog\n//     <i>  - Handler functions: osWatchdogAlarm_Handler\n#ifndef OS_THREAD_WATCHDOG\n#define OS_THREAD_WATCHDOG          1\n#endif\n \n//     <q>Object Pointer checking\n//     <i> Check object pointer alignment and memory region.\n#ifndef OS_OBJ_PTR_CHECK\n#define OS_OBJ_PTR_CHECK            0\n#endif\n \n//     <q>SVC Function Pointer checking\n//     <i> Check SVC function pointer alignment and memory region.\n//     <i> User needs to define a linker execution region RTX_SVC_VENEERS\n//     <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)\n#ifndef OS_SVC_PTR_CHECK\n#define OS_SVC_PTR_CHECK            0\n#endif\n \n//   </e>\n \n//   <o>ISR FIFO Queue\n//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries\n//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries\n//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries\n//   <i> RTOS Functions called from ISR store requests to this buffer.\n//   <i> Default: 16 entries\n#ifndef OS_ISR_FIFO_QUEUE\n#define OS_ISR_FIFO_QUEUE           16\n#endif\n \n//   <q>Object Memory usage counters\n//   <i> Enables object memory usage counters (requires RTX source variant).\n#ifndef OS_OBJ_MEM_USAGE\n#define OS_OBJ_MEM_USAGE            0\n#endif\n \n// </h>\n \n// <h>Thread Configuration\n// =======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_THREAD_OBJ_MEM\n#define OS_THREAD_OBJ_MEM           0\n#endif\n \n//     <o>Number of user Threads <1-1000>\n//     <i> Defines maximum number of user threads that can be active at the same time.\n//     <i> Applies to user threads with system provided memory for control blocks.\n#ifndef OS_THREAD_NUM\n#define OS_THREAD_NUM               1\n#endif\n \n//     <o>Number of user Threads with default Stack size <0-1000>\n//     <i> Defines maximum number of user threads with default stack size.\n//     <i> Applies to user threads with zero stack size specified.\n#ifndef OS_THREAD_DEF_STACK_NUM\n#define OS_THREAD_DEF_STACK_NUM     0\n#endif\n \n//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>\n//     <i> Defines the combined stack size for user threads with user-provided stack size.\n//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.\n//     <i> Default: 0\n#ifndef OS_THREAD_USER_STACK_SIZE\n#define OS_THREAD_USER_STACK_SIZE   0\n#endif\n \n//   </e>\n \n//   <o>Default Thread Stack size [bytes] <96-1073741824:8>\n//   <i> Defines stack size for threads with zero stack size specified.\n//   <i> Default: 3072\n#ifndef OS_STACK_SIZE\n#define OS_STACK_SIZE               512\n#endif\n \n//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>\n//   <i> Defines stack size for Idle thread.\n//   <i> Default: 512\n#ifndef OS_IDLE_THREAD_STACK_SIZE\n#define OS_IDLE_THREAD_STACK_SIZE   512\n#endif\n \n//   <o>Idle Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_IDLE_THREAD_TZ_MOD_ID\n#define OS_IDLE_THREAD_TZ_MOD_ID    0\n#endif\n \n//   <o>Idle Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_CLASS\n#define OS_IDLE_THREAD_CLASS        0\n#endif\n \n//   <o>Idle Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_ZONE\n#define OS_IDLE_THREAD_ZONE         0\n#endif\n \n//   <q>Stack overrun checking\n//   <i> Enables stack overrun check at thread switch (requires RTX source variant).\n//   <i> Enabling this option increases slightly the execution time of a thread switch.\n#ifndef OS_STACK_CHECK\n#define OS_STACK_CHECK              1\n#endif\n \n//   <q>Stack usage watermark\n//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.\n//   <i> Enabling this option increases significantly the execution time of thread creation.\n#ifndef OS_STACK_WATERMARK\n#define OS_STACK_WATERMARK          0\n#endif\n \n//   <o>Default Processor mode for Thread execution\n//     <0=> Unprivileged mode\n//     <1=> Privileged mode\n//   <i> Default: Unprivileged mode\n#ifndef OS_PRIVILEGE_MODE\n#define OS_PRIVILEGE_MODE           0\n#endif\n \n// </h>\n \n// <h>Timer Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_TIMER_OBJ_MEM\n#define OS_TIMER_OBJ_MEM            0\n#endif\n \n//     <o>Number of Timer objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_TIMER_NUM\n#define OS_TIMER_NUM                1\n#endif\n \n//   </e>\n \n//   <o>Timer Thread Priority\n//      <8=> Low\n//     <16=> Below Normal  <24=> Normal  <32=> Above Normal\n//     <40=> High\n//     <48=> Realtime\n//   <i> Defines priority for timer thread\n//   <i> Default: High\n#ifndef OS_TIMER_THREAD_PRIO\n#define OS_TIMER_THREAD_PRIO        40\n#endif\n \n//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>\n//   <i> Defines stack size for Timer thread.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 512\n#ifndef OS_TIMER_THREAD_STACK_SIZE\n#define OS_TIMER_THREAD_STACK_SIZE  512\n#endif\n \n//   <o>Timer Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_TIMER_THREAD_TZ_MOD_ID\n#define OS_TIMER_THREAD_TZ_MOD_ID   0\n#endif\n \n//   <o>Timer Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_CLASS\n#define OS_TIMER_THREAD_CLASS       0\n#endif\n \n//   <o>Timer Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_ZONE\n#define OS_TIMER_THREAD_ZONE        0\n#endif\n \n//   <o>Timer Callback Queue entries <0-256>\n//   <i> Number of concurrent active timer callback functions.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 4\n#ifndef OS_TIMER_CB_QUEUE\n#define OS_TIMER_CB_QUEUE           4\n#endif\n \n// </h>\n \n// <h>Event Flags Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_EVFLAGS_OBJ_MEM\n#define OS_EVFLAGS_OBJ_MEM          0\n#endif\n \n//     <o>Number of Event Flags objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_EVFLAGS_NUM\n#define OS_EVFLAGS_NUM              1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Mutex Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MUTEX_OBJ_MEM\n#define OS_MUTEX_OBJ_MEM            0\n#endif\n \n//     <o>Number of Mutex objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MUTEX_NUM\n#define OS_MUTEX_NUM                1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Semaphore Configuration\n// ==========================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_SEMAPHORE_OBJ_MEM\n#define OS_SEMAPHORE_OBJ_MEM        0\n#endif\n \n//     <o>Number of Semaphore objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_SEMAPHORE_NUM\n#define OS_SEMAPHORE_NUM            1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Memory Pool Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MEMPOOL_OBJ_MEM\n#define OS_MEMPOOL_OBJ_MEM          0\n#endif\n \n//     <o>Number of Memory Pool objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MEMPOOL_NUM\n#define OS_MEMPOOL_NUM              1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MEMPOOL_DATA_SIZE\n#define OS_MEMPOOL_DATA_SIZE        0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Message Queue Configuration\n// ==============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MSGQUEUE_OBJ_MEM\n#define OS_MSGQUEUE_OBJ_MEM         0\n#endif\n \n//     <o>Number of Message Queue objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MSGQUEUE_NUM\n#define OS_MSGQUEUE_NUM             1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MSGQUEUE_DATA_SIZE\n#define OS_MSGQUEUE_DATA_SIZE       0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Event Recorder Configuration\n// ===============================\n \n//   <e>Global Initialization\n//   <i> Initialize Event Recorder during 'osKernelInitialize'.\n#ifndef OS_EVR_INIT\n#define OS_EVR_INIT                 1\n#endif\n \n//     <q>Start recording\n//     <i> Start event recording after initialization.\n#ifndef OS_EVR_START\n#define OS_EVR_START                1\n#endif\n \n//     <h>Global Event Filter Setup\n//     <i> Initial recording level applied to all components.\n//       <o.0>Error events\n//       <o.1>API function call events\n//       <o.2>Operation events\n//       <o.3>Detailed operation events\n//     </h>\n#ifndef OS_EVR_LEVEL\n#define OS_EVR_LEVEL                0x00U\n#endif\n \n//     <h>RTOS Event Filter Setup\n//     <i> Recording levels for RTX components.\n//     <i> Only applicable if events for the respective component are generated.\n \n//       <e.7>Memory Management\n//       <i> Recording level for Memory Management events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMORY_LEVEL\n#define OS_EVR_MEMORY_LEVEL         0x81U\n#endif\n \n//       <e.7>Kernel\n//       <i> Recording level for Kernel events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_KERNEL_LEVEL\n#define OS_EVR_KERNEL_LEVEL         0x81U\n#endif\n \n//       <e.7>Thread\n//       <i> Recording level for Thread events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THREAD_LEVEL\n#define OS_EVR_THREAD_LEVEL         0x85U\n#endif\n \n//       <e.7>Generic Wait\n//       <i> Recording level for Generic Wait events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_WAIT_LEVEL\n#define OS_EVR_WAIT_LEVEL           0x81U\n#endif\n \n//       <e.7>Thread Flags\n//       <i> Recording level for Thread Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THFLAGS_LEVEL\n#define OS_EVR_THFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Event Flags\n//       <i> Recording level for Event Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_EVFLAGS_LEVEL\n#define OS_EVR_EVFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Timer\n//       <i> Recording level for Timer events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_TIMER_LEVEL\n#define OS_EVR_TIMER_LEVEL          0x81U\n#endif\n \n//       <e.7>Mutex\n//       <i> Recording level for Mutex events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MUTEX_LEVEL\n#define OS_EVR_MUTEX_LEVEL          0x81U\n#endif\n \n//       <e.7>Semaphore\n//       <i> Recording level for Semaphore events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_SEMAPHORE_LEVEL\n#define OS_EVR_SEMAPHORE_LEVEL      0x81U\n#endif\n \n//       <e.7>Memory Pool\n//       <i> Recording level for Memory Pool events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMPOOL_LEVEL\n#define OS_EVR_MEMPOOL_LEVEL        0x81U\n#endif\n \n//       <e.7>Message Queue\n//       <i> Recording level for Message Queue events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MSGQUEUE_LEVEL\n#define OS_EVR_MSGQUEUE_LEVEL       0x81U\n#endif\n \n//     </h>\n \n//   </e>\n \n//   <h>RTOS Event Generation\n//   <i> Enables event generation for RTX components (requires RTX source variant).\n \n//     <q>Memory Management\n//     <i> Enables Memory Management event generation.\n#ifndef OS_EVR_MEMORY\n#define OS_EVR_MEMORY               1\n#endif\n \n//     <q>Kernel\n//     <i> Enables Kernel event generation.\n#ifndef OS_EVR_KERNEL\n#define OS_EVR_KERNEL               1\n#endif\n \n//     <q>Thread\n//     <i> Enables Thread event generation.\n#ifndef OS_EVR_THREAD\n#define OS_EVR_THREAD               1\n#endif\n \n//     <q>Generic Wait\n//     <i> Enables Generic Wait event generation.\n#ifndef OS_EVR_WAIT\n#define OS_EVR_WAIT                 1\n#endif\n \n//     <q>Thread Flags\n//     <i> Enables Thread Flags event generation.\n#ifndef OS_EVR_THFLAGS\n#define OS_EVR_THFLAGS              1\n#endif\n \n//     <q>Event Flags\n//     <i> Enables Event Flags event generation.\n#ifndef OS_EVR_EVFLAGS\n#define OS_EVR_EVFLAGS              1\n#endif\n \n//     <q>Timer\n//     <i> Enables Timer event generation.\n#ifndef OS_EVR_TIMER\n#define OS_EVR_TIMER                1\n#endif\n \n//     <q>Mutex\n//     <i> Enables Mutex event generation.\n#ifndef OS_EVR_MUTEX\n#define OS_EVR_MUTEX                1\n#endif\n \n//     <q>Semaphore\n//     <i> Enables Semaphore event generation.\n#ifndef OS_EVR_SEMAPHORE\n#define OS_EVR_SEMAPHORE            1\n#endif\n \n//     <q>Memory Pool\n//     <i> Enables Memory Pool event generation.\n#ifndef OS_EVR_MEMPOOL\n#define OS_EVR_MEMPOOL              1\n#endif\n \n//     <q>Message Queue\n//     <i> Enables Message Queue event generation.\n#ifndef OS_EVR_MSGQUEUE\n#define OS_EVR_MSGQUEUE             1\n#endif\n \n//   </h>\n \n// </h>\n \n// Number of Threads which use standard C/C++ library libspace\n// (when thread specific memory allocation is not used).\n#if (OS_THREAD_OBJ_MEM == 0)\n#ifndef OS_THREAD_LIBSPACE_NUM\n#define OS_THREAD_LIBSPACE_NUM      4\n#endif\n#else\n#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM\n#endif\n \n//------------- <<< end of configuration section >>> ---------------------------\n \n#endif  // RTX_CONFIG_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MsgQueue/RTE/Compiler/EventRecorderConf.h",
    "content": "/*------------------------------------------------------------------------------\n * MDK - Component ::Event Recorder\n * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved.\n *------------------------------------------------------------------------------\n * Name:    EventRecorderConf.h\n * Purpose: Event Recorder Configuration\n * Rev.:    V1.1.0\n *----------------------------------------------------------------------------*/\n\n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n\n// <h>Event Recorder\n\n//   <o>Number of Records\n//     <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024\n//     <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768\n//     <65536=>65536\n//   <i>Configures size of Event Record Buffer (each record is 16 bytes)\n//   <i>Must be 2^n (min=8, max=65536)\n#define EVENT_RECORD_COUNT      64U\n\n//   <o>Time Stamp Source\n//      <0=> DWT Cycle Counter  <1=> SysTick  <2=> CMSIS-RTOS2 System Timer\n//      <3=> User Timer (Normal Reset)  <4=> User Timer (Power-On Reset)\n//   <i>Selects source for 32-bit time stamp\n#define EVENT_TIMESTAMP_SOURCE  2\n\n//   <o>Time Stamp Clock Frequency [Hz] <0-1000000000>\n//   <i>Defines initial time stamp clock frequency (0 when not used)\n#define EVENT_TIMESTAMP_FREQ    0U\n\n// </h>\n\n//------------- <<< end of configuration section >>> ---------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MsgQueue/RTE/Device/ARMCM3/ARMCM3_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00040000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Event Recorder Configuration -------------------------\n; <h> Event Recorder Configuration\n;   <o> Event Recorder RAM Size (in Bytes) <0x0-0xFFFFFFFF:16>\n;   <i> Memory requirement = 256 + (16 x Number_of_Records)\n;   <i> (defined by EVENT_RECORD_COUNT in EventRecorderConf.h)\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_EVR_SIZE  0x00000800\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  Stack, Heap and Event Recorder boundary definitions\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after previous section, 8 byte aligned */\n#define __RAM_EVR_BASE (AlignExpr(+0, 4))           /* starts after previous section, 4 byte aligned */\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __RAM_EVR_SIZE - __HEAP_SIZE - __STACK_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __RAM_EVR_SIZE > 0\n  RW_EVR __RAM_EVR_BASE UNINIT __RAM_EVR_SIZE {     ; Event Recorder RAM region\n    EventRecorder.o (+ZI)\n  }\n#endif\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MsgQueue/RTE/Device/ARMCM3/startup_ARMCM3.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM3.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M3 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM3)\n  #include \"ARMCM3.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MsgQueue/RTE/Device/ARMCM3/system_ARMCM3.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM3.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM3 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM3.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/MsgQueue/main.c",
    "content": "/* -------------------------------------------------------------------------- \n * Copyright (c) 2013-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    main.c\n *      Purpose: RTX example program\n *\n *---------------------------------------------------------------------------*/\n\n#include <stdio.h>\n\n#include \"RTE_Components.h\"\n#include  CMSIS_device_header\n#include \"cmsis_os2.h\"\n\nvoid app_main (void *argument);\nvoid app_msg (void *argument);\n\ntypedef struct msg_s {\n  uint8_t cmd;\n  uint8_t len;\n  uint8_t data[8];\n} msg_t;\n\nstatic osMessageQueueId_t msgQueue;\n\nstatic const osThreadAttr_t msgAttr = {\n  .stack_size = 400U\n};\n\n/*----------------------------------------------------------------------------\n * Application main thread\n *---------------------------------------------------------------------------*/\n\nvoid app_main (void *argument) {\n  (void)argument;\n\n  osStatus_t status;\n  uint32_t cnt = 0UL;\n  msg_t msg = {\n    .cmd = 1U,\n    .len = 4U,\n    .data = { 0U }\n  };\n\n  while (1) {\n    // Produce a new message and put it to the queue\n    ++cnt;\n    *((uint32_t*)msg.data) = cnt;\n    status = osMessageQueuePut(msgQueue, &msg, 0U, osWaitForever);\n    if (status != osOK) {\n      printf(\"app_main: osMessageQueuePut failed.\\n\");\n    }\n\n    // Defer message creation\n    osDelay(osMessageQueueGetCount(msgQueue)*100U);\n  }\n}\n\n/*----------------------------------------------------------------------------\n * Application message receiver thread\n *---------------------------------------------------------------------------*/\n\nvoid app_msg (void *argument) {\n  (void)argument;\n\n  osStatus_t status;\n  uint32_t cnt;\n  msg_t msg;\n\n  while (1) {\n    // Defer message processing\n    osDelay(osMessageQueueGetSpace(msgQueue)*100U);\n\n    // Wait forever until a message could be received\n    status = osMessageQueueGet(msgQueue, &msg, NULL, osWaitForever);\n    if (status != osOK) {\n      printf(\"app_msg: osMessageQueueGet failed.\\n\");\n    } else {\n      if (msg.len == 4U) {\n        cnt = *((uint32_t*)msg.data);\n      }\n      printf(\"app_msg: received [cmd = %d, data = 0x%0X]\\n\", msg.cmd, cnt);\n    }\n  }\n}\n\n/*----------------------------------------------------------------------------\n * Main entry\n *---------------------------------------------------------------------------*/\n\nint main (void) {\n\n  // System Initialization\n  SystemCoreClockUpdate();\n\n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  osThreadNew(app_msg, NULL, &msgAttr); // Create message receiver thread\n\n  // Create message queue for up to 10 messages of type msg_t\n  msgQueue = osMessageQueueNew(10, sizeof(msg_t), NULL);\n  \n  osKernelStart();                      // Start thread execution\n  for (;;) {}\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/ARMCM33_DSP_FP_TZ_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=0                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/Abstract.txt",
    "content": ""
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_ns/CM33_ns.uvguix",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectGui xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_guix.xsd\">\n\n  <SchemaVersion>-6.1</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <PrjGuiSettings>\n    <LastAddFilePath></LastAddFilePath>\n  </PrjGuiSettings>\n\n  <ViewPool/>\n\n  <SECTreeCtrl>\n    <View>\n      <WinId>38003</WinId>\n      <ViewName>Registers</ViewName>\n      <TableColWidths>140 100</TableColWidths>\n    </View>\n    <View>\n      <WinId>346</WinId>\n      <ViewName>Code Coverage</ViewName>\n      <TableColWidths>1010 160</TableColWidths>\n    </View>\n    <View>\n      <WinId>204</WinId>\n      <ViewName>Performance Analyzer</ViewName>\n      <TableColWidths>1170 175 175 100</TableColWidths>\n    </View>\n  </SECTreeCtrl>\n\n  <TreeListPane>\n    <View>\n      <WinId>35141</WinId>\n      <ViewName>Event Statistics</ViewName>\n      <UserString></UserString>\n      <TableColWidths>200 50 700</TableColWidths>\n    </View>\n    <View>\n      <WinId>1506</WinId>\n      <ViewName>Symbols</ViewName>\n      <UserString></UserString>\n      <TableColWidths>80 80 80</TableColWidths>\n    </View>\n    <View>\n      <WinId>1936</WinId>\n      <ViewName>Watch 1</ViewName>\n      <UserString></UserString>\n      <TableColWidths>200 133 133</TableColWidths>\n    </View>\n    <View>\n      <WinId>1937</WinId>\n      <ViewName>Watch 2</ViewName>\n      <UserString></UserString>\n      <TableColWidths>200 133 133</TableColWidths>\n    </View>\n    <View>\n      <WinId>1935</WinId>\n      <ViewName>Call Stack + Locals</ViewName>\n      <UserString></UserString>\n      <TableColWidths>200 133 133</TableColWidths>\n    </View>\n    <View>\n      <WinId>2506</WinId>\n      <ViewName>Trace Data</ViewName>\n      <UserString></UserString>\n      <TableColWidths>75 135 130 95 70 230 200 150</TableColWidths>\n    </View>\n    <View>\n      <WinId>466</WinId>\n      <ViewName>Source Browser</ViewName>\n      <UserString>500</UserString>\n      <TableColWidths>166</TableColWidths>\n    </View>\n  </TreeListPane>\n\n  <CompViewPool/>\n\n  <WindowSettings>\n    <LogicAnalizer>\n      <ShowLACursor>0</ShowLACursor>\n      <ShowSignalInfo>0</ShowSignalInfo>\n      <ShowCycles>0</ShowCycles>\n      <LeftSideBarSize>50</LeftSideBarSize>\n      <TimeBaseIndex>16</TimeBaseIndex>\n    </LogicAnalizer>\n  </WindowSettings>\n\n  <WinLayoutEx>\n    <sActiveDebugView></sActiveDebugView>\n    <WindowPosition>\n      <length>44</length>\n      <flags>2</flags>\n      <showCmd>3</showCmd>\n      <MinPosition>\n        <xPos>-1</xPos>\n        <yPos>-1</yPos>\n      </MinPosition>\n      <MaxPosition>\n        <xPos>-1</xPos>\n        <yPos>-1</yPos>\n      </MaxPosition>\n      <NormalPosition>\n        <Top>-8</Top>\n        <Left>-8</Left>\n        <Right>1928</Right>\n        <Bottom>1047</Bottom>\n      </NormalPosition>\n    </WindowPosition>\n    <MDIClientArea>\n      <RegID>0</RegID>\n      <MDITabState>\n        <Len>258</Len>\n        <Data>01000000040000000100000001000000010000000100000000000000020000000000000001000000010000000000000028000000280000000100000001000000000000000100000038443A5C546573745C4578616D706C65735C54727573745A6F6E6556384D5C4E6F52544F535C434D33335F735C41627374726163742E747874000000000C41627374726163742E74787400000000C5D4F200FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000F4000000660000008007000075040000</Data>\n      </MDITabState>\n    </MDIClientArea>\n  </WinLayoutEx>\n\n</ProjectGui>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_ns/CM33_ns.uvoptx",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectOpt xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_optx.xsd\">\n\n  <SchemaVersion>1.0</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Extensions>\n    <cExt>*.c</cExt>\n    <aExt>*.s*; *.src; *.a*</aExt>\n    <oExt>*.obj</oExt>\n    <lExt>*.lib</lExt>\n    <tExt>*.txt; *.h; *.inc; *.md</tExt>\n    <pExt>*.plm</pExt>\n    <CppX>*.cpp</CppX>\n    <nMigrate>0</nMigrate>\n  </Extensions>\n\n  <DaveTm>\n    <dwLowDateTime>0</dwLowDateTime>\n    <dwHighDateTime>0</dwHighDateTime>\n  </DaveTm>\n\n  <Target>\n    <TargetName>FVP Simulation Model</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\Listings\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>1</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>0</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>15</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile>..\\Debug.ini</tIfile>\n        <pMon>BIN\\DbgFMv8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>PWSTATINFO</Key>\n          <Name>200,50,700</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>DLGTARM</Key>\n          <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>ARMDBGFLAGS</Key>\n          <Name></Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>DLGUARM</Key>\n          <Name>(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>DbgFMv8M</Key>\n          <Name>-I -S -L\"cpu0\" -O4102 -C0 -MC\".\\FVP\\MPS2_Cortex-M\\FVP_MPS2_Cortex-M33_MDK.exe\" -MF\"..\\ARMCM33_DSP_FP_TZ_config.txt\" -PF -MA</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>\n        </SetRegEntry>\n      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 <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Group>\n    <GroupName>Non-secure Code</GroupName>\n    <tvExp>1</tvExp>\n    <tvExpOptDlg>0</tvExpOptDlg>\n    <cbSel>0</cbSel>\n    <RteFlg>0</RteFlg>\n    <File>\n      <GroupNumber>1</GroupNumber>\n      <FileNumber>1</FileNumber>\n      <FileType>1</FileType>\n      <tvExp>0</tvExp>\n      <tvExpOptDlg>0</tvExpOptDlg>\n      <bDave2>0</bDave2>\n      <PathWithFileName>.\\main_ns.c</PathWithFileName>\n      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  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_ns/CM33_ns.uvprojx",
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category=\"linkerScript\" condition=\"TZ Non-secure ARMCC6\" name=\"Device\\ARM\\ARMCM33\\Source\\ARM\\ARMCM33_ac6.sct\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_ac6.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\startup_ARMCM33.c\" version=\"2.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\startup_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\system_ARMCM33.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\system_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00200000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20200000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_ns/main_ns.c",
    "content": "/*\n * Copyright (c) 2013-209 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * main_ns.c      Non-secure main function \n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n#include \"interface.h\"        // Interface API\n\nextern volatile int val1, val2;\nvolatile int val1, val2;\n\n/* Non-secure function */\nint func3 (int x); \n\nint func3 (int x)  {\n  return (x+4);\n}\n\n/* Non-secure main() */\nint main(void) {\n \n  /* Call non-secure callable function func1 */\n  val1 = func1 (1);\n \n  /* Call non-secure callable function func2\n     with callback to non-secure function func3 */\n  val2 = func2 (func3, 2);\n \n  while (1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/Abstract.txt",
    "content": "This ARM Cortex-M33 secure/non-secure example project that\nshows the setup for TrustZone for ARMv8-M applications.\nThe application uses CMSIS and can be executed on a Fixed\nVirtual Platform (FVP) simulation model.\n\nThe application demonstrates function calls between secure\nand non-secure state.\n\nSecure application:\n - Setup code and start non-secure application.\n\nNon-secure application:\n - Calls a secure function from non-secure state.\n - Calls a secure function that call back to a non-secure function.\n\nOutput:\nVariables used in this application can be viewed in the Debugger\nWatch window."
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/CM33_s.uvguix",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectGui xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_guix.xsd\">\n\n  <SchemaVersion>-6.1</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <PrjGuiSettings>\n    <LastAddFilePath></LastAddFilePath>\n  </PrjGuiSettings>\n\n  <ViewPool/>\n\n  <SECTreeCtrl>\n    <View>\n      <WinId>38003</WinId>\n      <ViewName>Registers</ViewName>\n      <TableColWidths>140 100</TableColWidths>\n    </View>\n    <View>\n      <WinId>346</WinId>\n      <ViewName>Code Coverage</ViewName>\n      <TableColWidths>1010 160</TableColWidths>\n    </View>\n    <View>\n      <WinId>204</WinId>\n      <ViewName>Performance Analyzer</ViewName>\n      <TableColWidths>1170 175 175 100</TableColWidths>\n    </View>\n  </SECTreeCtrl>\n\n  <TreeListPane>\n    <View>\n      <WinId>35141</WinId>\n      <ViewName>Event Statistics</ViewName>\n      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    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/CM33_s.uvprojx",
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  <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x200000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x200000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x200000</StartAddress>\n                <Size>0x200000</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x20200000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>2</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>1</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>0</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange>0x00000000</TextAddressRange>\n            <DataAddressRange>0x20000000</DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile>.\\RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_ac6_s.sct</ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc>--import-cmse-lib-out=\"..\\CM33_s\\Objects\\CM33_s_CMSE_Lib.o\"</Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Secure Code</GroupName>\n          <Files>\n            <File>\n              <FileName>main_s.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\main_s.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Interface</GroupName>\n          <Files>\n            <File>\n              <FileName>interface.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\interface.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Documentation</GroupName>\n          <Files>\n            <File>\n              <FileName>Abstract.txt</FileName>\n              <FileType>5</FileType>\n              <FilePath>.\\Abstract.txt</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Device</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis/>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.2.0\" condition=\"ARMv6_7_8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.5.2-dev5\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n      <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files>\n      <file attr=\"config\" category=\"linkerScript\" condition=\"TZ Secure ARMCC6\" name=\"Device\\ARM\\ARMCM33\\Source\\ARM\\ARMCM33_ac6_s.sct\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_ac6_s.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" condition=\"TZ Secure\" name=\"Device\\ARM\\ARMCM33\\Include\\Template\\partition_ARMCM33.h\" version=\"1.1.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\partition_ARMCM33.h</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\startup_ARMCM33.c\" version=\"2.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\startup_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\system_ARMCM33.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\system_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM33.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33\n * @version  V1.1.1\n * @date     12. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM33_H\n#define PARTITION_ARMCM33_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM33_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/interface.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * interface.c      Secure/non-secure callable application code\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n\n#include <arm_cmse.h>     // CMSE definitions\n#include \"interface.h\"    // Header file with secure interface API\n\n/* typedef for non-secure callback functions */\ntypedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));\n\n/* Non-secure callable (entry) function */\nint func1(int x) __attribute__((cmse_nonsecure_entry)) { \n  return x+3; \n}\n\n/* Non-secure callable (entry) function, calling a non-secure callback function */\nint func2(funcptr callback, int x)  __attribute__((cmse_nonsecure_entry))\t{\n\tfuncptr_NS callback_NS;               // non-secure callback function pointer\n\tint y;\n\t\n\t/* return function pointer with cleared LSB */\n  callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);\n\t\n\ty = callback_NS (x+1);\n\t\n\treturn (y+2);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/interface.h",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * interface.h    API definition for the non-secure state\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n/* Function pointer declaration */\ntypedef int (*funcptr)(int);\n\n/* Non-secure callable functions */\nextern int func1(int x);\nextern int func2(funcptr callback, int x);\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/CM33_s/main_s.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        15. October 2016\n * $Revision:    1.1.0\n *\n * Project:      TrustZone for ARMv8-M\n * Title:        Code template for secure main function\n *\n *---------------------------------------------------------------------------*/\n \n/* Use CMSE intrinsics */\n#include <arm_cmse.h>\n \n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n \n/* TZ_START_NS: Start address of non-secure application */\n#ifndef TZ_START_NS\n#define TZ_START_NS (0x200000U)\n#endif\n \n/* typedef for non-secure callback functions */\ntypedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));\n \n/* Secure main() */\nint main(void) {\n  funcptr_void NonSecure_ResetHandler;\n \n  /* Add user setup code for secure part here*/\n \n  /* Set non-secure main stack (MSP_NS) */\n  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));\n \n  /* Get non-secure reset handler */\n  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));\n \n  /* Start non-secure state software application */\n  NonSecure_ResetHandler();\n \n  /* Non-secure software does not return, this code is not executed */\n  while (1) {\n    __NOP();\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/Debug.ini",
    "content": "LOAD \"..\\\\CM33_ns\\\\Objects\\\\CM33_ns.axf\" incremental\nLOAD \"..\\\\CM33_s\\\\Objects\\\\CM33_s.axf\" incremental\nRESET\ng, \\\\CM33_s\\main_s\\main"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/NoRTOS.uvmpw",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectWorkspace xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_mpw.xsd\">\n\n  <SchemaVersion>1.0</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <WorkspaceName>WorkSpace</WorkspaceName>\n\n  <project>\n    <PathAndName>.\\CM33_s\\CM33_s.uvprojx</PathAndName>\n    <NodeIsActive>1</NodeIsActive>\n    <NodeIsExpanded>1</NodeIsExpanded>\n  </project>\n\n  <project>\n    <PathAndName>.\\CM33_ns\\CM33_ns.uvprojx</PathAndName>\n    <NodeIsExpanded>1</NodeIsExpanded>\n  </project>\n\n</ProjectWorkspace>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/NoRTOS/NoRTOS.uvmpw.uvgui",
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  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/ARMCM33_DSP_FP_TZ_config.txt",
    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=0                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/Abstract.txt",
    "content": ""
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/CM33_ns.uvguix",
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<SimDlgDllArguments></SimDlgDllArguments>\n          <TargetDllName>SARMV8M.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>0</Capability>\n            <DriverSelection>-1</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2V8M.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>1</AdsALst>\n            <AdsACrf>1</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>1</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            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<RoSelD>4</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>0</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>0</Ir1Chk>\n            <Ir2Chk>1</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>0</Im1Chk>\n            <Im2Chk>1</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x200000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x200000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x200000</StartAddress>\n                <Size>0x200000</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x20200000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>2</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>0</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>1</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>0</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange>0x00000000</TextAddressRange>\n            <DataAddressRange>0x20000000</DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile>.\\RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_AC6.sct</ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Non-secure Code</GroupName>\n          <Files>\n            <File>\n              <FileName>main_ns.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\main_ns.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>CMSE Library</GroupName>\n          <Files>\n            <File>\n              <FileName>CM33_s_CMSE_Lib.o</FileName>\n              <FileType>3</FileType>\n              <FilePath>..\\CM33_s\\Objects\\CM33_s_CMSE_Lib.o</FilePath>\n            </File>\n            <File>\n              <FileName>interface.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\CM33_s\\interface.h</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Device</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis>\n      <api Capiversion=\"2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" exclusive=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.0.0-Beta16\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </api>\n    </apis>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"ARMv6_7_8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n      <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5 NS\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n      <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files>\n      <file attr=\"config\" category=\"source\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.c\" version=\"5.2.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.c</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5 NS\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.h\" version=\"5.6.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.h</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5 NS\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"linkerScript\" condition=\"Startup ARMCC6 Unsecure\" name=\"Device\\ARM\\ARMCM33\\Source\\ARM\\ARMCM33_ac6.sct\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_ac6.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\startup_ARMCM33.c\" version=\"2.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\startup_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\system_ARMCM33.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\system_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/RTE/CMSIS/RTX_Config.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.2.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration\n *\n * -----------------------------------------------------------------------------\n */\n \n#include \"cmsis_compiler.h\"\n#include \"rtx_os.h\"\n \n// OS Idle Thread\n__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n\n  for (;;) {}\n}\n \n// OS Error Callback function\n__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {\n  (void)object_id;\n\n  switch (code) {\n    case osRtxErrorStackOverflow:\n      // Stack overflow detected for thread (thread_id=object_id)\n      break;\n    case osRtxErrorISRQueueOverflow:\n      // ISR Queue overflow detected when inserting object (object_id)\n      break;\n    case osRtxErrorTimerQueueOverflow:\n      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)\n      break;\n    case osRtxErrorClibSpace:\n      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM\n      break;\n    case osRtxErrorClibMutex:\n      // Standard C/C++ library mutex initialization failed\n      break;\n    case osRtxErrorSVC:\n      // Invalid SVC function called (function=object_id)\n      break;\n    default:\n      // Reserved\n      break;\n  }\n  for (;;) {}\n//return 0U;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/RTE/CMSIS/RTX_Config.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.6.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration definitions\n *\n * -----------------------------------------------------------------------------\n */\n \n#ifndef RTX_CONFIG_H_\n#define RTX_CONFIG_H_\n \n#ifdef   _RTE_\n#include \"RTE_Components.h\"\n#ifdef    RTE_RTX_CONFIG_H\n#include  RTE_RTX_CONFIG_H\n#endif\n#endif\n \n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n \n// <h>System Configuration\n// =======================\n \n//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>\n//   <i> Defines the combined global dynamic memory size.\n//   <i> Default: 32768\n#ifndef OS_DYNAMIC_MEM_SIZE\n#define OS_DYNAMIC_MEM_SIZE         4096\n#endif\n \n//   <o>Kernel Tick Frequency [Hz] <1-1000000>\n//   <i> Defines base time unit for delays and timeouts.\n//   <i> Default: 1000 (1ms tick)\n#ifndef OS_TICK_FREQ\n#define OS_TICK_FREQ                1000\n#endif\n \n//   <e>Round-Robin Thread switching\n//   <i> Enables Round-Robin Thread switching.\n#ifndef OS_ROBIN_ENABLE\n#define OS_ROBIN_ENABLE             1\n#endif\n \n//     <o>Round-Robin Timeout <1-1000>\n//     <i> Defines how many ticks a thread will execute before a thread switch.\n//     <i> Default: 5\n#ifndef OS_ROBIN_TIMEOUT\n#define OS_ROBIN_TIMEOUT            5\n#endif\n \n//   </e>\n \n//   <e>Safety features (Source variant only)\n//   <i> Enables FuSa related features.\n//   <i> Requires RTX Source variant.\n//   <i> Enables:\n//   <i>  - selected features from this group\n//   <i>  - Thread functions: osThreadProtectPrivileged\n#ifndef OS_SAFETY_FEATURES\n#define OS_SAFETY_FEATURES          0\n#endif\n \n//     <q>Safety Class\n//     <i> Threads assigned to lower classes cannot modify higher class threads.\n//     <i> Enables:\n//     <i>  - Object attributes: osSafetyClass\n//     <i>  - Kernel functions: osKernelProtect, osKernelDestroyClass\n//     <i>  - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass\n#ifndef OS_SAFETY_CLASS\n#define OS_SAFETY_CLASS             1\n#endif\n \n//     <q>MPU Protected Zone\n//     <i> Access protection via MPU (Spatial isolation).\n//     <i> Enables:\n//     <i>  - Thread attributes: osThreadZone\n//     <i>  - Thread functions: osThreadGetZone, osThreadTerminateZone\n//     <i>  - Zone Management: osZoneSetup_Callback\n#ifndef OS_EXECUTION_ZONE\n#define OS_EXECUTION_ZONE           1\n#endif\n \n//     <q>Thread Watchdog\n//     <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).\n//     <i> Enables:\n//     <i>  - Thread functions: osThreadFeedWatchdog\n//     <i>  - Handler functions: osWatchdogAlarm_Handler\n#ifndef OS_THREAD_WATCHDOG\n#define OS_THREAD_WATCHDOG          1\n#endif\n \n//     <q>Object Pointer checking\n//     <i> Check object pointer alignment and memory region.\n#ifndef OS_OBJ_PTR_CHECK\n#define OS_OBJ_PTR_CHECK            0\n#endif\n \n//     <q>SVC Function Pointer checking\n//     <i> Check SVC function pointer alignment and memory region.\n//     <i> User needs to define a linker execution region RTX_SVC_VENEERS\n//     <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)\n#ifndef OS_SVC_PTR_CHECK\n#define OS_SVC_PTR_CHECK            0\n#endif\n \n//   </e>\n \n//   <o>ISR FIFO Queue\n//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries\n//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries\n//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries\n//   <i> RTOS Functions called from ISR store requests to this buffer.\n//   <i> Default: 16 entries\n#ifndef OS_ISR_FIFO_QUEUE\n#define OS_ISR_FIFO_QUEUE           16\n#endif\n \n//   <q>Object Memory usage counters\n//   <i> Enables object memory usage counters (requires RTX source variant).\n#ifndef OS_OBJ_MEM_USAGE\n#define OS_OBJ_MEM_USAGE            0\n#endif\n \n// </h>\n \n// <h>Thread Configuration\n// =======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_THREAD_OBJ_MEM\n#define OS_THREAD_OBJ_MEM           0\n#endif\n \n//     <o>Number of user Threads <1-1000>\n//     <i> Defines maximum number of user threads that can be active at the same time.\n//     <i> Applies to user threads with system provided memory for control blocks.\n#ifndef OS_THREAD_NUM\n#define OS_THREAD_NUM               1\n#endif\n \n//     <o>Number of user Threads with default Stack size <0-1000>\n//     <i> Defines maximum number of user threads with default stack size.\n//     <i> Applies to user threads with zero stack size specified.\n#ifndef OS_THREAD_DEF_STACK_NUM\n#define OS_THREAD_DEF_STACK_NUM     0\n#endif\n \n//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>\n//     <i> Defines the combined stack size for user threads with user-provided stack size.\n//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.\n//     <i> Default: 0\n#ifndef OS_THREAD_USER_STACK_SIZE\n#define OS_THREAD_USER_STACK_SIZE   0\n#endif\n \n//   </e>\n \n//   <o>Default Thread Stack size [bytes] <96-1073741824:8>\n//   <i> Defines stack size for threads with zero stack size specified.\n//   <i> Default: 3072\n#ifndef OS_STACK_SIZE\n#define OS_STACK_SIZE               512\n#endif\n \n//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>\n//   <i> Defines stack size for Idle thread.\n//   <i> Default: 512\n#ifndef OS_IDLE_THREAD_STACK_SIZE\n#define OS_IDLE_THREAD_STACK_SIZE   512\n#endif\n \n//   <o>Idle Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_IDLE_THREAD_TZ_MOD_ID\n#define OS_IDLE_THREAD_TZ_MOD_ID    0\n#endif\n \n//   <o>Idle Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_CLASS\n#define OS_IDLE_THREAD_CLASS        0\n#endif\n \n//   <o>Idle Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_ZONE\n#define OS_IDLE_THREAD_ZONE         0\n#endif\n \n//   <q>Stack overrun checking\n//   <i> Enables stack overrun check at thread switch (requires RTX source variant).\n//   <i> Enabling this option increases slightly the execution time of a thread switch.\n#ifndef OS_STACK_CHECK\n#define OS_STACK_CHECK              1\n#endif\n \n//   <q>Stack usage watermark\n//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.\n//   <i> Enabling this option increases significantly the execution time of thread creation.\n#ifndef OS_STACK_WATERMARK\n#define OS_STACK_WATERMARK          0\n#endif\n \n//   <o>Default Processor mode for Thread execution\n//     <0=> Unprivileged mode\n//     <1=> Privileged mode\n//   <i> Default: Unprivileged mode\n#ifndef OS_PRIVILEGE_MODE\n#define OS_PRIVILEGE_MODE           0\n#endif\n \n// </h>\n \n// <h>Timer Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_TIMER_OBJ_MEM\n#define OS_TIMER_OBJ_MEM            0\n#endif\n \n//     <o>Number of Timer objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_TIMER_NUM\n#define OS_TIMER_NUM                1\n#endif\n \n//   </e>\n \n//   <o>Timer Thread Priority\n//      <8=> Low\n//     <16=> Below Normal  <24=> Normal  <32=> Above Normal\n//     <40=> High\n//     <48=> Realtime\n//   <i> Defines priority for timer thread\n//   <i> Default: High\n#ifndef OS_TIMER_THREAD_PRIO\n#define OS_TIMER_THREAD_PRIO        40\n#endif\n \n//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>\n//   <i> Defines stack size for Timer thread.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 512\n#ifndef OS_TIMER_THREAD_STACK_SIZE\n#define OS_TIMER_THREAD_STACK_SIZE  512\n#endif\n \n//   <o>Timer Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_TIMER_THREAD_TZ_MOD_ID\n#define OS_TIMER_THREAD_TZ_MOD_ID   0\n#endif\n \n//   <o>Timer Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_CLASS\n#define OS_TIMER_THREAD_CLASS       0\n#endif\n \n//   <o>Timer Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_ZONE\n#define OS_TIMER_THREAD_ZONE        0\n#endif\n \n//   <o>Timer Callback Queue entries <0-256>\n//   <i> Number of concurrent active timer callback functions.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 4\n#ifndef OS_TIMER_CB_QUEUE\n#define OS_TIMER_CB_QUEUE           4\n#endif\n \n// </h>\n \n// <h>Event Flags Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_EVFLAGS_OBJ_MEM\n#define OS_EVFLAGS_OBJ_MEM          0\n#endif\n \n//     <o>Number of Event Flags objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_EVFLAGS_NUM\n#define OS_EVFLAGS_NUM              1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Mutex Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MUTEX_OBJ_MEM\n#define OS_MUTEX_OBJ_MEM            0\n#endif\n \n//     <o>Number of Mutex objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MUTEX_NUM\n#define OS_MUTEX_NUM                1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Semaphore Configuration\n// ==========================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_SEMAPHORE_OBJ_MEM\n#define OS_SEMAPHORE_OBJ_MEM        0\n#endif\n \n//     <o>Number of Semaphore objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_SEMAPHORE_NUM\n#define OS_SEMAPHORE_NUM            1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Memory Pool Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MEMPOOL_OBJ_MEM\n#define OS_MEMPOOL_OBJ_MEM          0\n#endif\n \n//     <o>Number of Memory Pool objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MEMPOOL_NUM\n#define OS_MEMPOOL_NUM              1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MEMPOOL_DATA_SIZE\n#define OS_MEMPOOL_DATA_SIZE        0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Message Queue Configuration\n// ==============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MSGQUEUE_OBJ_MEM\n#define OS_MSGQUEUE_OBJ_MEM         0\n#endif\n \n//     <o>Number of Message Queue objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MSGQUEUE_NUM\n#define OS_MSGQUEUE_NUM             1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MSGQUEUE_DATA_SIZE\n#define OS_MSGQUEUE_DATA_SIZE       0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Event Recorder Configuration\n// ===============================\n \n//   <e>Global Initialization\n//   <i> Initialize Event Recorder during 'osKernelInitialize'.\n#ifndef OS_EVR_INIT\n#define OS_EVR_INIT                 0\n#endif\n \n//     <q>Start recording\n//     <i> Start event recording after initialization.\n#ifndef OS_EVR_START\n#define OS_EVR_START                1\n#endif\n \n//     <h>Global Event Filter Setup\n//     <i> Initial recording level applied to all components.\n//       <o.0>Error events\n//       <o.1>API function call events\n//       <o.2>Operation events\n//       <o.3>Detailed operation events\n//     </h>\n#ifndef OS_EVR_LEVEL\n#define OS_EVR_LEVEL                0x00U\n#endif\n \n//     <h>RTOS Event Filter Setup\n//     <i> Recording levels for RTX components.\n//     <i> Only applicable if events for the respective component are generated.\n \n//       <e.7>Memory Management\n//       <i> Recording level for Memory Management events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMORY_LEVEL\n#define OS_EVR_MEMORY_LEVEL         0x81U\n#endif\n \n//       <e.7>Kernel\n//       <i> Recording level for Kernel events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_KERNEL_LEVEL\n#define OS_EVR_KERNEL_LEVEL         0x81U\n#endif\n \n//       <e.7>Thread\n//       <i> Recording level for Thread events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THREAD_LEVEL\n#define OS_EVR_THREAD_LEVEL         0x85U\n#endif\n \n//       <e.7>Generic Wait\n//       <i> Recording level for Generic Wait events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_WAIT_LEVEL\n#define OS_EVR_WAIT_LEVEL           0x81U\n#endif\n \n//       <e.7>Thread Flags\n//       <i> Recording level for Thread Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THFLAGS_LEVEL\n#define OS_EVR_THFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Event Flags\n//       <i> Recording level for Event Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_EVFLAGS_LEVEL\n#define OS_EVR_EVFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Timer\n//       <i> Recording level for Timer events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_TIMER_LEVEL\n#define OS_EVR_TIMER_LEVEL          0x81U\n#endif\n \n//       <e.7>Mutex\n//       <i> Recording level for Mutex events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MUTEX_LEVEL\n#define OS_EVR_MUTEX_LEVEL          0x81U\n#endif\n \n//       <e.7>Semaphore\n//       <i> Recording level for Semaphore events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_SEMAPHORE_LEVEL\n#define OS_EVR_SEMAPHORE_LEVEL      0x81U\n#endif\n \n//       <e.7>Memory Pool\n//       <i> Recording level for Memory Pool events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMPOOL_LEVEL\n#define OS_EVR_MEMPOOL_LEVEL        0x81U\n#endif\n \n//       <e.7>Message Queue\n//       <i> Recording level for Message Queue events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MSGQUEUE_LEVEL\n#define OS_EVR_MSGQUEUE_LEVEL       0x81U\n#endif\n \n//     </h>\n \n//   </e>\n \n//   <h>RTOS Event Generation\n//   <i> Enables event generation for RTX components (requires RTX source variant).\n \n//     <q>Memory Management\n//     <i> Enables Memory Management event generation.\n#ifndef OS_EVR_MEMORY\n#define OS_EVR_MEMORY               1\n#endif\n \n//     <q>Kernel\n//     <i> Enables Kernel event generation.\n#ifndef OS_EVR_KERNEL\n#define OS_EVR_KERNEL               1\n#endif\n \n//     <q>Thread\n//     <i> Enables Thread event generation.\n#ifndef OS_EVR_THREAD\n#define OS_EVR_THREAD               1\n#endif\n \n//     <q>Generic Wait\n//     <i> Enables Generic Wait event generation.\n#ifndef OS_EVR_WAIT\n#define OS_EVR_WAIT                 1\n#endif\n \n//     <q>Thread Flags\n//     <i> Enables Thread Flags event generation.\n#ifndef OS_EVR_THFLAGS\n#define OS_EVR_THFLAGS              1\n#endif\n \n//     <q>Event Flags\n//     <i> Enables Event Flags event generation.\n#ifndef OS_EVR_EVFLAGS\n#define OS_EVR_EVFLAGS              1\n#endif\n \n//     <q>Timer\n//     <i> Enables Timer event generation.\n#ifndef OS_EVR_TIMER\n#define OS_EVR_TIMER                1\n#endif\n \n//     <q>Mutex\n//     <i> Enables Mutex event generation.\n#ifndef OS_EVR_MUTEX\n#define OS_EVR_MUTEX                1\n#endif\n \n//     <q>Semaphore\n//     <i> Enables Semaphore event generation.\n#ifndef OS_EVR_SEMAPHORE\n#define OS_EVR_SEMAPHORE            1\n#endif\n \n//     <q>Memory Pool\n//     <i> Enables Memory Pool event generation.\n#ifndef OS_EVR_MEMPOOL\n#define OS_EVR_MEMPOOL              1\n#endif\n \n//     <q>Message Queue\n//     <i> Enables Message Queue event generation.\n#ifndef OS_EVR_MSGQUEUE\n#define OS_EVR_MSGQUEUE             1\n#endif\n \n//   </h>\n \n// </h>\n \n// Number of Threads which use standard C/C++ library libspace\n// (when thread specific memory allocation is not used).\n#if (OS_THREAD_OBJ_MEM == 0)\n#ifndef OS_THREAD_LIBSPACE_NUM\n#define OS_THREAD_LIBSPACE_NUM      4\n#endif\n#else\n#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM\n#endif\n \n//------------- <<< end of configuration section >>> ---------------------------\n \n#define OS_TZ_CONTEXT               1\n \n#endif  // RTX_CONFIG_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00200000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20200000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_ns/main_ns.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * main_ns.c      Non-secure main function - RTOS demo\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n#include \"..\\CM33_s\\interface.h\"        // Interface API\n#include \"cmsis_os2.h\"                  // ARM::CMSIS:RTOS2:Keil RTX5\n\nstatic osStatus_t Status;\n\nstatic osThreadId_t ThreadA_Id;\nstatic osThreadId_t ThreadB_Id;\nstatic osThreadId_t ThreadC_Id;\n\nvoid ThreadA (void *argument);\nvoid ThreadB (void *argument);\nvoid ThreadC (void *argument);\n\n\nextern volatile int counterA;\nextern volatile int counterB;\nextern volatile int counterC;\n\nvolatile int counterA;\nvolatile int counterB;\nvolatile int counterC;\n\n\nstatic int callbackA (int val)  {\n  return (val);\n}\n\n__attribute__((noreturn))\nvoid ThreadA (void *argument)  {\n  (void)argument;\n\n  for (;;) {\n    counterA = func1 (counterA);\n    counterA = func2 (callbackA, counterA);\n    osDelay(2U);\n  }\n}\n\nstatic int callbackB (int val)  {\n  uint32_t flags;\n  \n  flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever);\n  if (flags == 1U)  {\n    return (val+1);\n  }  else {\n    return (0);\n  }\n}\n\n\n__attribute__((noreturn))\nvoid ThreadB (void *argument)  {\n  (void)argument;\n\n  for (;;) {\n    counterB = func1 (counterB);\n    counterB = func2 (callbackB, counterB);\n  }\n}\n\n__attribute__((noreturn))\nvoid ThreadC (void *argument) {\n  (void)argument;\n\n  for (;;) {\n    counterC = counterC + 1;\n    if ((counterC % 0x10) == 0)  {\n      osThreadFlagsSet (ThreadB_Id, 1);\n    }\n    osDelay(1U);\n  }\n}\n\nstatic const osThreadAttr_t ThreadAttr = {\n  .tz_module = 1U,                  // indicate calls to secure mode\n};\n\nint main (void) {\n\n  Status = osKernelInitialize();\n\n  ThreadA_Id = osThreadNew(ThreadA, NULL, &ThreadAttr);\n  ThreadB_Id = osThreadNew(ThreadB, NULL, &ThreadAttr);\n  ThreadC_Id = osThreadNew(ThreadC, NULL, NULL);\n\n  Status = osKernelStart();\n\n  for (;;);\n}\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/Abstract.txt",
    "content": "This ARM Cortex-M33 secure/non-secure example project that\nshows the setup of the CMSIS-RTOS2 RTX for TrustZone for \nARMv8-M applications. \n\nThe application uses CMSIS and can be executed on a Fixed\nVirtual Platform (FVP) simulation model. The application \ndemonstrates three RTOS threads. \n\n\nSecure application:\n - Setup code and start non-secure application.\n\nNon-secure application:\n - Calls a secure function from non-secure state.\n - Calls a secure function that call back to a non-secure function.\n\nOutput:\nVariables used in this application can be viewed in the Debugger\nWatch window."
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/CM33_s.uvguix",
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  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/CM33_s.uvprojx",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<Project xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_projx.xsd\">\n\n  <SchemaVersion>2.1</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Targets>\n    <Target>\n      <TargetName>FVP Simulation Model</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>\n      <uAC6>1</uAC6>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM33_DSP_FP_TZ</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.9.0</PackID>\n          <PackURL>https://www.keil.com/pack/</PackURL>\n          <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE(\"Cortex-M33\") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\\ARM\\ARMCM33\\Include\\ARMCM33_DSP_FP_TZ.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM33_DSP_FP_TZ$Device\\ARM\\SVD\\ARMCM33.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          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     </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName></SimDllName>\n          <SimDllArguments></SimDllArguments>\n          <SimDlgDll></SimDlgDll>\n          <SimDlgDllArguments></SimDlgDllArguments>\n          <TargetDllName>SARMV8M.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>0</Capability>\n            <DriverSelection>-1</DriverSelection>\n          </Flash1>\n          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<StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x200000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x200000</StartAddress>\n                <Size>0x200000</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x20200000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>2</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>1</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>0</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange>0x00000000</TextAddressRange>\n            <DataAddressRange>0x20000000</DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile>.\\RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_ac6_s.sct</ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Secure Code</GroupName>\n          <Files>\n            <File>\n              <FileName>Abstract.txt</FileName>\n              <FileType>5</FileType>\n              <FilePath>.\\Abstract.txt</FilePath>\n            </File>\n            <File>\n              <FileName>main_s.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\main_s.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Interface</GroupName>\n          <Files>\n            <File>\n              <FileName>interface.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\interface.c</FilePath>\n            </File>\n            <File>\n              <FileName>tz_context.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\tz_context.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Device</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis/>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.2.0\" condition=\"ARMv6_7_8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.5.2-dev5\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n      <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files>\n      <file attr=\"config\" category=\"linkerScript\" condition=\"Startup ARMCC6 Secure\" name=\"Device\\ARM\\ARMCM33\\Source\\ARM\\ARMCM33_ac6_s.sct\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_ac6_s.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" condition=\"TZ Secure\" name=\"Device\\ARM\\ARMCM33\\Include\\Template\\partition_ARMCM33.h\" version=\"1.1.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\partition_ARMCM33.h</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\startup_ARMCM33.c\" version=\"2.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\startup_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\system_ARMCM33.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\system_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM33.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33\n * @version  V1.1.1\n * @date     12. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM33_H\n#define PARTITION_ARMCM33_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM33_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/interface.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * interface.c      Secure/non-secure callable application code\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n\n#include <arm_cmse.h>     // CMSE definitions\n#include \"interface.h\"    // Header file with secure interface API\n\n/* typedef for non-secure callback functions */\ntypedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));\n\n/* Non-secure callable (entry) function */\nint func1(int x) __attribute__((cmse_nonsecure_entry)) { \n  return x+3; \n}\n\n/* Non-secure callable (entry) function, calling a non-secure callback function */\nint func2(funcptr callback, int x)  __attribute__((cmse_nonsecure_entry))\t{\n\tfuncptr_NS callback_NS;               // non-secure callback function pointer\n\tint y;\n\t\n\t/* return function pointer with cleared LSB */\n  callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);\n\t\n\ty = callback_NS (x+1);\n\t\n\treturn (y+2);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/interface.h",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * interface.h    API definition for the non-secure state\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n/* Function pointer declaration */\ntypedef int (*funcptr)(int);\n\n/* Non-secure callable functions */\nextern int func1(int x);\nextern int func2(funcptr callback, int x);\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/main_s.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        15. October 2016\n * $Revision:    1.1.0\n *\n * Project:      TrustZone for ARMv8-M\n * Title:        Code template for secure main function\n *\n *---------------------------------------------------------------------------*/\n \n/* Use CMSE intrinsics */\n#include <arm_cmse.h>\n \n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n \n/* TZ_START_NS: Start address of non-secure application */\n#ifndef TZ_START_NS\n#define TZ_START_NS (0x200000U)\n#endif\n \n/* typedef for non-secure callback functions */\ntypedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));\n \n/* Secure main() */\nint main(void) {\n  funcptr_void NonSecure_ResetHandler;\n \n  /* Add user setup code for secure part here*/\n \n  /* Set non-secure main stack (MSP_NS) */\n  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));\n \n  /* Get non-secure reset handler */\n  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));\n \n  /* Start non-secure state software application */\n  NonSecure_ResetHandler();\n \n  /* Non-secure software does not return, this code is not executed */\n  while (1) {\n    __NOP();\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/CM33_s/tz_context.c",
    "content": "/*\n * Copyright (c) 2015-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------------\n *\n * $Date:        15. October 2016\n * $Revision:    1.1.0\n *\n * Project:      TrustZone for ARMv8-M\n * Title:        Context Management for ARMv8-M TrustZone - Sample implementation\n *\n *---------------------------------------------------------------------------*/\n \n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"tz_context.h\"\n\n/// Number of process slots (threads may call secure library code)\n#ifndef TZ_PROCESS_STACK_SLOTS\n#define TZ_PROCESS_STACK_SLOTS     8U\n#endif\n\n/// Stack size of the secure library code\n#ifndef TZ_PROCESS_STACK_SIZE\n#define TZ_PROCESS_STACK_SIZE      256U\n#endif\n\ntypedef struct {\n  uint32_t sp_top;      // stack space top\n  uint32_t sp_limit;    // stack space limit\n  uint32_t sp;          // current stack pointer\n} stack_info_t;\n\nstatic stack_info_t ProcessStackInfo  [TZ_PROCESS_STACK_SLOTS];\nstatic uint64_t     ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];\nstatic uint32_t     ProcessStackFreeSlot = 0xFFFFFFFFU;\n\n\n/// Initialize secure context memory system\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_InitContextSystem_S (void) {\n  uint32_t n;\n\n  if (__get_IPSR() == 0U) {\n    return 0U;  // Thread Mode\n  }\n\n  for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {\n    ProcessStackInfo[n].sp = 0U;\n    ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];\n    ProcessStackInfo[n].sp_top   = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;\n    *((uint32_t *)ProcessStackMemory[n]) = n + 1U;\n  }\n  *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;\n\n  ProcessStackFreeSlot = 0U;\n\n  // Default process stack pointer and stack limit\n  __set_PSPLIM((uint32_t)ProcessStackMemory);\n  __set_PSP   ((uint32_t)ProcessStackMemory);\n\n  // Privileged Thread Mode using PSP\n  __set_CONTROL(0x02U);\n\n  return 1U;    // Success\n}\n\n\n/// Allocate context memory for calling secure software modules in TrustZone\n/// \\param[in]  module   identifies software modules called from non-secure mode\n/// \\return value != 0 id TrustZone memory slot identifier\n/// \\return value 0    no memory available or internal error\n__attribute__((cmse_nonsecure_entry))\nTZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {\n  uint32_t slot;\n\n  (void)module; // Ignore (fixed Stack size)\n\n  if (__get_IPSR() == 0U) {\n    return 0U;  // Thread Mode\n  }\n\n  if (ProcessStackFreeSlot == 0xFFFFFFFFU) {\n    return 0U;  // No slot available\n  }\n\n  slot = ProcessStackFreeSlot;\n  ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);\n\n  ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;\n\n  return (slot + 1U);\n}\n\n\n/// Free context memory that was previously allocated with \\ref TZ_AllocModuleContext_S\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {\n  uint32_t slot;\n\n  if (__get_IPSR() == 0U) {\n    return 0U;  // Thread Mode\n  }\n\n  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {\n    return 0U;  // Invalid ID\n  }\n\n  slot = id - 1U;\n\n  if (ProcessStackInfo[slot].sp == 0U) {\n    return 0U;  // Inactive slot\n  }\n  ProcessStackInfo[slot].sp = 0U;\n\n  *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;\n  ProcessStackFreeSlot = slot;\n\n  return 1U;    // Success\n}\n\n\n/// Load secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {\n  uint32_t slot;\n\n  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {\n    return 0U;  // Thread Mode or using Main Stack for threads\n  }\n\n  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {\n    return 0U;  // Invalid ID\n  }\n\n  slot = id - 1U;\n\n  if (ProcessStackInfo[slot].sp == 0U) {\n    return 0U;  // Inactive slot\n  }\n\n  // Setup process stack pointer and stack limit\n  __set_PSPLIM(ProcessStackInfo[slot].sp_limit);\n  __set_PSP   (ProcessStackInfo[slot].sp);\n\n  return 1U;    // Success\n}\n\n\n/// Store secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {\n  uint32_t slot;\n  uint32_t sp;\n\n  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {\n    return 0U;  // Thread Mode or using Main Stack for threads\n  }\n\n  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {\n    return 0U;  // Invalid ID\n  }\n\n  slot = id - 1U;\n\n  if (ProcessStackInfo[slot].sp == 0U) {\n    return 0U;  // Inactive slot\n  }\n\n  sp = __get_PSP();\n  if ((sp < ProcessStackInfo[slot].sp_limit) ||\n      (sp > ProcessStackInfo[slot].sp_top)) {\n    return 0U;  // SP out of range\n  }\n  ProcessStackInfo[slot].sp = sp;\n\n  // Default process stack pointer and stack limit\n  __set_PSPLIM((uint32_t)ProcessStackMemory);\n  __set_PSP   ((uint32_t)ProcessStackMemory);\n\n  return 1U;    // Success\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/Debug.ini",
    "content": "LOAD \"..\\\\CM33_ns\\\\Objects\\\\CM33_ns.axf\" incremental\nLOAD \"..\\\\CM33_s\\\\Objects\\\\CM33_s.axf\" incremental\nRESET\ng, \\\\CM33_s\\main_s\\main"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/RTOS.uvmpw",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectWorkspace xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_mpw.xsd\">\n\n  <SchemaVersion>1.0</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <WorkspaceName>WorkSpace</WorkspaceName>\n\n  <project>\n    <PathAndName>.\\CM33_s\\CM33_s.uvprojx</PathAndName>\n    <NodeIsActive>1</NodeIsActive>\n    <NodeIsExpanded>1</NodeIsExpanded>\n  </project>\n\n  <project>\n    <PathAndName>.\\CM33_ns\\CM33_ns.uvprojx</PathAndName>\n    <NodeIsExpanded>1</NodeIsExpanded>\n  </project>\n\n</ProjectWorkspace>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS/RTOS.uvmpw.uvgui",
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    "content": "# Parameters:\n# instance.parameter=value       #(type, mode) default = 'def value' : description : [min..max]\n#----------------------------------------------------------------------------------------------\ncpu0.FPU=1                                            # (bool  , init-time) default = '1'      : Set whether the model has VFP support\ncpu0.DSP=1                                            # (bool  , init-time) default = '1'      : Set whether the model has the DSP extension\ncpu0.semihosting-enable=0                             # (bool  , init-time) default = '1'      : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.\ncpu0.MPU_S=0x8                                        # (int   , init-time) default = '0x8'    : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10]\ncpu0.MPU_NS=0x8                                       # (int   , init-time) default = '0x8'    : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10]\ncpu0.ITM=0                                            # (bool  , init-time) default = '1'      : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included\ncpu0.IRQLVL=0x3                                       # (int   , init-time) default = '0x3'    : Number of bits of interrupt priority : [0x3..0x8]\ncpu0.BIGENDINIT=0                                     # (bool  , init-time) default = '0'      : Initialize processor to big endian mode\ncpu0.INITSVTOR=0x00000000                             # (int   , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.INITNSVTOR=0x0                                   # (int   , init-time) default = '0x0'    : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80]\ncpu0.SAU=0x8                                          # (int   , init-time) default = '0x4'    : Number of SAU regions (0 => no SAU) : [0x0..0x8]\ncpu0.SAU_CTRL.ENABLE=0                                # (bool  , init-time) default = '0'      : Enable SAU at reset\ncpu0.SAU_CTRL.ALLNS=0                                 # (bool  , init-time) default = '0'      : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set\nidau.NUM_IDAU_REGION=0x0                              # (int   , init-time) default = '0xA'    : \ncpu0.LOCK_SAU=0                                       # (bool  , init-time) default = '0'      : Lock down of SAU registers write\ncpu0.LOCK_S_MPU=0                                     # (bool  , init-time) default = '0'      : Lock down of Secure MPU registers write\ncpu0.LOCK_NS_MPU=0                                    # (bool  , init-time) default = '0'      : Lock down of Non-Secure MPU registers write\ncpu0.CPIF=1                                           # (bool  , init-time) default = '1'      : Specifies whether the external coprocessor interface is included\ncpu0.SECEXT=1                                         # (bool  , init-time) default = '1'      : Whether the ARMv8-M Security Extensions are included\nfvp_mps2.DISABLE_GATING=1                             # (bool  , init-time) default = '0'      : Disable Memory gating logic\n#----------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/Abstract.txt",
    "content": ""
  },
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  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_ns/CM33_ns.uvprojx",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<Project xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_projx.xsd\">\n\n  <SchemaVersion>2.1</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Targets>\n    <Target>\n      <TargetName>FVP Simulation Model</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>\n      <uAC6>1</uAC6>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM33_DSP_FP_TZ</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.9.1</PackID>\n          <PackURL>https://www.keil.com/pack/</PackURL>\n          <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE(\"Cortex-M33\") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM33_DSP_FP_TZ$Device\\ARM\\ARMCM33\\Include\\ARMCM33_DSP_FP_TZ.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM33_DSP_FP_TZ$Device\\ARM\\SVD\\ARMCM33.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\Objects\\</OutputDirectory>\n          <OutputName>CM33_ns</OutputName>\n          <CreateExecutable>1</CreateExecutable>\n          <CreateLib>0</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>1</BrowseInformation>\n          <ListingPath>.\\Listings\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>0</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName></SimDllName>\n          <SimDllArguments></SimDllArguments>\n          <SimDlgDll></SimDlgDll>\n          <SimDlgDllArguments></SimDlgDllArguments>\n          <TargetDllName>SARMV8M.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>\n            <Capability>0</Capability>\n            <DriverSelection>4097</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2V8M.DLL</Flash2>\n          <Flash3>\"\" ()</Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>1</AdsALst>\n            <AdsACrf>1</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>1</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M33\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>1</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>2</RvdsVP>\n            <RvdsMve>0</RvdsMve>\n            <RvdsCdeCp>0</RvdsCdeCp>\n            <nBranchProt>0</nBranchProt>\n            <hadIRAM2>1</hadIRAM2>\n            <hadIROM2>1</hadIROM2>\n            <StupSel>16</StupSel>\n            <useUlib>1</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>4</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>0</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>0</Ir1Chk>\n            <Ir2Chk>1</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>0</Im1Chk>\n            <Im2Chk>1</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x200000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x200000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x200000</StartAddress>\n                <Size>0x200000</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x20200000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>2</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>0</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>1</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>0</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange>0x00000000</TextAddressRange>\n            <DataAddressRange>0x20000000</DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile>.\\RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_AC6.sct</ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Non-secure Code</GroupName>\n          <Files>\n            <File>\n              <FileName>main_ns.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\main_ns.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>CMSE Library</GroupName>\n          <Files>\n            <File>\n              <FileName>CM33_s_CMSE_Lib.o</FileName>\n              <FileType>3</FileType>\n              <FilePath>..\\CM33_s\\Objects\\CM33_s_CMSE_Lib.o</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Device</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis>\n      <api Capiversion=\"2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" exclusive=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.0.0-Beta16\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </api>\n    </apis>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"ARMv6_7_8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n      <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5 NS\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n      <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\">\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files>\n      <file attr=\"config\" category=\"source\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.c\" version=\"5.2.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.c</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5 NS\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" name=\"CMSIS\\RTOS2\\RTX\\Config\\RTX_Config.h\" version=\"5.6.0\">\n        <instance index=\"0\">RTE\\CMSIS\\RTX_Config.h</instance>\n        <component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\" condition=\"RTOS2 RTX5 NS\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"linkerScript\" condition=\"Startup ARMCC6 Unsecure\" name=\"Device\\ARM\\ARMCM33\\Source\\ARM\\ARMCM33_ac6.sct\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_ac6.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\startup_ARMCM33.c\" version=\"2.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\startup_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\system_ARMCM33.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\system_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_ns/RTE/CMSIS/RTX_Config.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.2.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration\n *\n * -----------------------------------------------------------------------------\n */\n \n#include \"cmsis_compiler.h\"\n#include \"rtx_os.h\"\n \n// OS Idle Thread\n__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {\n  (void)argument;\n\n  for (;;) {}\n}\n \n// OS Error Callback function\n__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {\n  (void)object_id;\n\n  switch (code) {\n    case osRtxErrorStackOverflow:\n      // Stack overflow detected for thread (thread_id=object_id)\n      break;\n    case osRtxErrorISRQueueOverflow:\n      // ISR Queue overflow detected when inserting object (object_id)\n      break;\n    case osRtxErrorTimerQueueOverflow:\n      // User Timer Callback Queue overflow detected for timer (timer_id=object_id)\n      break;\n    case osRtxErrorClibSpace:\n      // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM\n      break;\n    case osRtxErrorClibMutex:\n      // Standard C/C++ library mutex initialization failed\n      break;\n    case osRtxErrorSVC:\n      // Invalid SVC function called (function=object_id)\n      break;\n    default:\n      // Reserved\n      break;\n  }\n  for (;;) {}\n//return 0U;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_ns/RTE/CMSIS/RTX_Config.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.6.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Configuration definitions\n *\n * -----------------------------------------------------------------------------\n */\n \n#ifndef RTX_CONFIG_H_\n#define RTX_CONFIG_H_\n \n#ifdef   _RTE_\n#include \"RTE_Components.h\"\n#ifdef    RTE_RTX_CONFIG_H\n#include  RTE_RTX_CONFIG_H\n#endif\n#endif\n \n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n \n// <h>System Configuration\n// =======================\n \n//   <o>Global Dynamic Memory size [bytes] <0-1073741824:8>\n//   <i> Defines the combined global dynamic memory size.\n//   <i> Default: 32768\n#ifndef OS_DYNAMIC_MEM_SIZE\n#define OS_DYNAMIC_MEM_SIZE         4096\n#endif\n \n//   <o>Kernel Tick Frequency [Hz] <1-1000000>\n//   <i> Defines base time unit for delays and timeouts.\n//   <i> Default: 1000 (1ms tick)\n#ifndef OS_TICK_FREQ\n#define OS_TICK_FREQ                1000\n#endif\n \n//   <e>Round-Robin Thread switching\n//   <i> Enables Round-Robin Thread switching.\n#ifndef OS_ROBIN_ENABLE\n#define OS_ROBIN_ENABLE             1\n#endif\n \n//     <o>Round-Robin Timeout <1-1000>\n//     <i> Defines how many ticks a thread will execute before a thread switch.\n//     <i> Default: 5\n#ifndef OS_ROBIN_TIMEOUT\n#define OS_ROBIN_TIMEOUT            5\n#endif\n \n//   </e>\n \n//   <e>Safety features (Source variant only)\n//   <i> Enables FuSa related features.\n//   <i> Requires RTX Source variant.\n//   <i> Enables:\n//   <i>  - selected features from this group\n//   <i>  - Thread functions: osThreadProtectPrivileged\n#ifndef OS_SAFETY_FEATURES\n#define OS_SAFETY_FEATURES          0\n#endif\n \n//     <q>Safety Class\n//     <i> Threads assigned to lower classes cannot modify higher class threads.\n//     <i> Enables:\n//     <i>  - Object attributes: osSafetyClass\n//     <i>  - Kernel functions: osKernelProtect, osKernelDestroyClass\n//     <i>  - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass\n#ifndef OS_SAFETY_CLASS\n#define OS_SAFETY_CLASS             1\n#endif\n \n//     <q>MPU Protected Zone\n//     <i> Access protection via MPU (Spatial isolation).\n//     <i> Enables:\n//     <i>  - Thread attributes: osThreadZone\n//     <i>  - Thread functions: osThreadGetZone, osThreadTerminateZone\n//     <i>  - Zone Management: osZoneSetup_Callback\n#ifndef OS_EXECUTION_ZONE\n#define OS_EXECUTION_ZONE           1\n#endif\n \n//     <q>Thread Watchdog\n//     <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).\n//     <i> Enables:\n//     <i>  - Thread functions: osThreadFeedWatchdog\n//     <i>  - Handler functions: osWatchdogAlarm_Handler\n#ifndef OS_THREAD_WATCHDOG\n#define OS_THREAD_WATCHDOG          1\n#endif\n \n//     <q>Object Pointer checking\n//     <i> Check object pointer alignment and memory region.\n#ifndef OS_OBJ_PTR_CHECK\n#define OS_OBJ_PTR_CHECK            0\n#endif\n \n//     <q>SVC Function Pointer checking\n//     <i> Check SVC function pointer alignment and memory region.\n//     <i> User needs to define a linker execution region RTX_SVC_VENEERS\n//     <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)\n#ifndef OS_SVC_PTR_CHECK\n#define OS_SVC_PTR_CHECK            0\n#endif\n \n//   </e>\n \n//   <o>ISR FIFO Queue\n//      <4=>  4 entries    <8=>   8 entries   <12=>  12 entries   <16=>  16 entries\n//     <24=> 24 entries   <32=>  32 entries   <48=>  48 entries   <64=>  64 entries\n//     <96=> 96 entries  <128=> 128 entries  <196=> 196 entries  <256=> 256 entries\n//   <i> RTOS Functions called from ISR store requests to this buffer.\n//   <i> Default: 16 entries\n#ifndef OS_ISR_FIFO_QUEUE\n#define OS_ISR_FIFO_QUEUE           16\n#endif\n \n//   <q>Object Memory usage counters\n//   <i> Enables object memory usage counters (requires RTX source variant).\n#ifndef OS_OBJ_MEM_USAGE\n#define OS_OBJ_MEM_USAGE            0\n#endif\n \n// </h>\n \n// <h>Thread Configuration\n// =======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_THREAD_OBJ_MEM\n#define OS_THREAD_OBJ_MEM           0\n#endif\n \n//     <o>Number of user Threads <1-1000>\n//     <i> Defines maximum number of user threads that can be active at the same time.\n//     <i> Applies to user threads with system provided memory for control blocks.\n#ifndef OS_THREAD_NUM\n#define OS_THREAD_NUM               1\n#endif\n \n//     <o>Number of user Threads with default Stack size <0-1000>\n//     <i> Defines maximum number of user threads with default stack size.\n//     <i> Applies to user threads with zero stack size specified.\n#ifndef OS_THREAD_DEF_STACK_NUM\n#define OS_THREAD_DEF_STACK_NUM     0\n#endif\n \n//     <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>\n//     <i> Defines the combined stack size for user threads with user-provided stack size.\n//     <i> Applies to user threads with user-provided stack size and system provided memory for stack.\n//     <i> Default: 0\n#ifndef OS_THREAD_USER_STACK_SIZE\n#define OS_THREAD_USER_STACK_SIZE   0\n#endif\n \n//   </e>\n \n//   <o>Default Thread Stack size [bytes] <96-1073741824:8>\n//   <i> Defines stack size for threads with zero stack size specified.\n//   <i> Default: 3072\n#ifndef OS_STACK_SIZE\n#define OS_STACK_SIZE               512\n#endif\n \n//   <o>Idle Thread Stack size [bytes] <72-1073741824:8>\n//   <i> Defines stack size for Idle thread.\n//   <i> Default: 512\n#ifndef OS_IDLE_THREAD_STACK_SIZE\n#define OS_IDLE_THREAD_STACK_SIZE   512\n#endif\n \n//   <o>Idle Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_IDLE_THREAD_TZ_MOD_ID\n#define OS_IDLE_THREAD_TZ_MOD_ID    0\n#endif\n \n//   <o>Idle Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_CLASS\n#define OS_IDLE_THREAD_CLASS        0\n#endif\n \n//   <o>Idle Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_IDLE_THREAD_ZONE\n#define OS_IDLE_THREAD_ZONE         0\n#endif\n \n//   <q>Stack overrun checking\n//   <i> Enables stack overrun check at thread switch (requires RTX source variant).\n//   <i> Enabling this option increases slightly the execution time of a thread switch.\n#ifndef OS_STACK_CHECK\n#define OS_STACK_CHECK              1\n#endif\n \n//   <q>Stack usage watermark\n//   <i> Initializes thread stack with watermark pattern for analyzing stack usage.\n//   <i> Enabling this option increases significantly the execution time of thread creation.\n#ifndef OS_STACK_WATERMARK\n#define OS_STACK_WATERMARK          0\n#endif\n \n//   <o>Default Processor mode for Thread execution\n//     <0=> Unprivileged mode\n//     <1=> Privileged mode\n//   <i> Default: Unprivileged mode\n#ifndef OS_PRIVILEGE_MODE\n#define OS_PRIVILEGE_MODE           0\n#endif\n \n// </h>\n \n// <h>Timer Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_TIMER_OBJ_MEM\n#define OS_TIMER_OBJ_MEM            0\n#endif\n \n//     <o>Number of Timer objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_TIMER_NUM\n#define OS_TIMER_NUM                1\n#endif\n \n//   </e>\n \n//   <o>Timer Thread Priority\n//      <8=> Low\n//     <16=> Below Normal  <24=> Normal  <32=> Above Normal\n//     <40=> High\n//     <48=> Realtime\n//   <i> Defines priority for timer thread\n//   <i> Default: High\n#ifndef OS_TIMER_THREAD_PRIO\n#define OS_TIMER_THREAD_PRIO        40\n#endif\n \n//   <o>Timer Thread Stack size [bytes] <0-1073741824:8>\n//   <i> Defines stack size for Timer thread.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 512\n#ifndef OS_TIMER_THREAD_STACK_SIZE\n#define OS_TIMER_THREAD_STACK_SIZE  512\n#endif\n \n//   <o>Timer Thread TrustZone Module Identifier\n//   <i> Defines TrustZone Thread Context Management Identifier.\n//   <i> Applies only to cores with TrustZone technology.\n//   <i> Default: 0 (not used)\n#ifndef OS_TIMER_THREAD_TZ_MOD_ID\n#define OS_TIMER_THREAD_TZ_MOD_ID   0\n#endif\n \n//   <o>Timer Thread Safety Class <0-15>\n//   <i> Defines the Safety Class number.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_CLASS\n#define OS_TIMER_THREAD_CLASS       0\n#endif\n \n//   <o>Timer Thread Zone <0-127>\n//   <i> Defines Thread Zone.\n//   <i> Default: 0\n#ifndef OS_TIMER_THREAD_ZONE\n#define OS_TIMER_THREAD_ZONE        0\n#endif\n \n//   <o>Timer Callback Queue entries <0-256>\n//   <i> Number of concurrent active timer callback functions.\n//   <i> May be set to 0 when timers are not used.\n//   <i> Default: 4\n#ifndef OS_TIMER_CB_QUEUE\n#define OS_TIMER_CB_QUEUE           4\n#endif\n \n// </h>\n \n// <h>Event Flags Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_EVFLAGS_OBJ_MEM\n#define OS_EVFLAGS_OBJ_MEM          0\n#endif\n \n//     <o>Number of Event Flags objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_EVFLAGS_NUM\n#define OS_EVFLAGS_NUM              1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Mutex Configuration\n// ======================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MUTEX_OBJ_MEM\n#define OS_MUTEX_OBJ_MEM            0\n#endif\n \n//     <o>Number of Mutex objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MUTEX_NUM\n#define OS_MUTEX_NUM                1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Semaphore Configuration\n// ==========================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_SEMAPHORE_OBJ_MEM\n#define OS_SEMAPHORE_OBJ_MEM        0\n#endif\n \n//     <o>Number of Semaphore objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_SEMAPHORE_NUM\n#define OS_SEMAPHORE_NUM            1\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Memory Pool Configuration\n// ============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MEMPOOL_OBJ_MEM\n#define OS_MEMPOOL_OBJ_MEM          0\n#endif\n \n//     <o>Number of Memory Pool objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MEMPOOL_NUM\n#define OS_MEMPOOL_NUM              1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MEMPOOL_DATA_SIZE\n#define OS_MEMPOOL_DATA_SIZE        0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Message Queue Configuration\n// ==============================\n \n//   <e>Object specific Memory allocation\n//   <i> Enables object specific memory allocation.\n#ifndef OS_MSGQUEUE_OBJ_MEM\n#define OS_MSGQUEUE_OBJ_MEM         0\n#endif\n \n//     <o>Number of Message Queue objects <1-1000>\n//     <i> Defines maximum number of objects that can be active at the same time.\n//     <i> Applies to objects with system provided memory for control blocks.\n#ifndef OS_MSGQUEUE_NUM\n#define OS_MSGQUEUE_NUM             1\n#endif\n \n//     <o>Data Storage Memory size [bytes] <0-1073741824:8>\n//     <i> Defines the combined data storage memory size.\n//     <i> Applies to objects with system provided memory for data storage.\n//     <i> Default: 0\n#ifndef OS_MSGQUEUE_DATA_SIZE\n#define OS_MSGQUEUE_DATA_SIZE       0\n#endif\n \n//   </e>\n \n// </h>\n \n// <h>Event Recorder Configuration\n// ===============================\n \n//   <e>Global Initialization\n//   <i> Initialize Event Recorder during 'osKernelInitialize'.\n#ifndef OS_EVR_INIT\n#define OS_EVR_INIT                 0\n#endif\n \n//     <q>Start recording\n//     <i> Start event recording after initialization.\n#ifndef OS_EVR_START\n#define OS_EVR_START                1\n#endif\n \n//     <h>Global Event Filter Setup\n//     <i> Initial recording level applied to all components.\n//       <o.0>Error events\n//       <o.1>API function call events\n//       <o.2>Operation events\n//       <o.3>Detailed operation events\n//     </h>\n#ifndef OS_EVR_LEVEL\n#define OS_EVR_LEVEL                0x00U\n#endif\n \n//     <h>RTOS Event Filter Setup\n//     <i> Recording levels for RTX components.\n//     <i> Only applicable if events for the respective component are generated.\n \n//       <e.7>Memory Management\n//       <i> Recording level for Memory Management events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMORY_LEVEL\n#define OS_EVR_MEMORY_LEVEL         0x81U\n#endif\n \n//       <e.7>Kernel\n//       <i> Recording level for Kernel events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_KERNEL_LEVEL\n#define OS_EVR_KERNEL_LEVEL         0x81U\n#endif\n \n//       <e.7>Thread\n//       <i> Recording level for Thread events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THREAD_LEVEL\n#define OS_EVR_THREAD_LEVEL         0x85U\n#endif\n \n//       <e.7>Generic Wait\n//       <i> Recording level for Generic Wait events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_WAIT_LEVEL\n#define OS_EVR_WAIT_LEVEL           0x81U\n#endif\n \n//       <e.7>Thread Flags\n//       <i> Recording level for Thread Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_THFLAGS_LEVEL\n#define OS_EVR_THFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Event Flags\n//       <i> Recording level for Event Flags events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_EVFLAGS_LEVEL\n#define OS_EVR_EVFLAGS_LEVEL        0x81U\n#endif\n \n//       <e.7>Timer\n//       <i> Recording level for Timer events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_TIMER_LEVEL\n#define OS_EVR_TIMER_LEVEL          0x81U\n#endif\n \n//       <e.7>Mutex\n//       <i> Recording level for Mutex events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MUTEX_LEVEL\n#define OS_EVR_MUTEX_LEVEL          0x81U\n#endif\n \n//       <e.7>Semaphore\n//       <i> Recording level for Semaphore events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_SEMAPHORE_LEVEL\n#define OS_EVR_SEMAPHORE_LEVEL      0x81U\n#endif\n \n//       <e.7>Memory Pool\n//       <i> Recording level for Memory Pool events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MEMPOOL_LEVEL\n#define OS_EVR_MEMPOOL_LEVEL        0x81U\n#endif\n \n//       <e.7>Message Queue\n//       <i> Recording level for Message Queue events.\n//         <o.0>Error events\n//         <o.1>API function call events\n//         <o.2>Operation events\n//         <o.3>Detailed operation events\n//       </e>\n#ifndef OS_EVR_MSGQUEUE_LEVEL\n#define OS_EVR_MSGQUEUE_LEVEL       0x81U\n#endif\n \n//     </h>\n \n//   </e>\n \n//   <h>RTOS Event Generation\n//   <i> Enables event generation for RTX components (requires RTX source variant).\n \n//     <q>Memory Management\n//     <i> Enables Memory Management event generation.\n#ifndef OS_EVR_MEMORY\n#define OS_EVR_MEMORY               1\n#endif\n \n//     <q>Kernel\n//     <i> Enables Kernel event generation.\n#ifndef OS_EVR_KERNEL\n#define OS_EVR_KERNEL               1\n#endif\n \n//     <q>Thread\n//     <i> Enables Thread event generation.\n#ifndef OS_EVR_THREAD\n#define OS_EVR_THREAD               1\n#endif\n \n//     <q>Generic Wait\n//     <i> Enables Generic Wait event generation.\n#ifndef OS_EVR_WAIT\n#define OS_EVR_WAIT                 1\n#endif\n \n//     <q>Thread Flags\n//     <i> Enables Thread Flags event generation.\n#ifndef OS_EVR_THFLAGS\n#define OS_EVR_THFLAGS              1\n#endif\n \n//     <q>Event Flags\n//     <i> Enables Event Flags event generation.\n#ifndef OS_EVR_EVFLAGS\n#define OS_EVR_EVFLAGS              1\n#endif\n \n//     <q>Timer\n//     <i> Enables Timer event generation.\n#ifndef OS_EVR_TIMER\n#define OS_EVR_TIMER                1\n#endif\n \n//     <q>Mutex\n//     <i> Enables Mutex event generation.\n#ifndef OS_EVR_MUTEX\n#define OS_EVR_MUTEX                1\n#endif\n \n//     <q>Semaphore\n//     <i> Enables Semaphore event generation.\n#ifndef OS_EVR_SEMAPHORE\n#define OS_EVR_SEMAPHORE            1\n#endif\n \n//     <q>Memory Pool\n//     <i> Enables Memory Pool event generation.\n#ifndef OS_EVR_MEMPOOL\n#define OS_EVR_MEMPOOL              1\n#endif\n \n//     <q>Message Queue\n//     <i> Enables Message Queue event generation.\n#ifndef OS_EVR_MSGQUEUE\n#define OS_EVR_MSGQUEUE             1\n#endif\n \n//   </h>\n \n// </h>\n \n// Number of Threads which use standard C/C++ library libspace\n// (when thread specific memory allocation is not used).\n#if (OS_THREAD_OBJ_MEM == 0)\n#ifndef OS_THREAD_LIBSPACE_NUM\n#define OS_THREAD_LIBSPACE_NUM      4\n#endif\n#else\n#define OS_THREAD_LIBSPACE_NUM      OS_THREAD_NUM\n#endif\n \n//------------- <<< end of configuration section >>> ---------------------------\n \n#define OS_TZ_CONTEXT               1\n \n#endif  // RTX_CONFIG_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00200000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20200000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_ns/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_ns/main_ns.c",
    "content": "/*\n * Copyright (c) 2013-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * main_ns.c      Non-secure main function - Security attacks demo\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n#include \"..\\CM33_s\\interface.h\"        // Interface API\n#include \"..\\CM33_s\\IncidentLog_s.h\"\n#include \"..\\CM33_s\\SysTick_s.h\"\n#include \"cmsis_os2.h\"                  // ARM::CMSIS:RTOS2:Keil RTX5\n\nstatic osStatus_t Status;\n\nstatic osThreadId_t ThreadA_Id;\nstatic osThreadId_t ThreadB_Id;\nstatic osThreadId_t ThreadC_Id;\nstatic osThreadId_t ThreadD_Id;\n\nvoid ThreadA (void *argument);\nvoid ThreadB (void *argument);\nvoid ThreadC (void *argument);\nvoid ThreadD (void *argument);\n\n\nextern volatile int counterA;\nextern volatile int counterB;\nextern volatile int counterC;\n\nvolatile int counterA;\nvolatile int counterB;\nvolatile int counterC;\n\n\nstatic int callbackA (int val)  {\n  return (val);\n}\n\n__attribute__((noreturn))\nvoid ThreadA (void *argument)  {\n  (void)argument;\n\n  for (;;) {\n    counterA = func1 (counterA);\n    counterA = func2 (callbackA, counterA);\n    osDelay(2U);\n  }\n}\n\nstatic int callbackB (int val)  {\n  uint32_t flags;\n  \n  flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever);\n  if (flags == 1U)  {\n    return (val+1);\n  } else {\n    return (0);\n  }\n}\n\n\n__attribute__((noreturn))\nvoid ThreadB (void *argument)  {\n  (void)argument;\n\n  for (;;) {\n    counterB = func1 (counterB);\n    counterB = func2 (callbackB, counterB);\n  }\n}\n\n\n__attribute__((noreturn))\nvoid ThreadC (void *argument) {\n  (void)argument;\n\n  for (;;) {\n    counterC = counterC + 1;\n    if ((counterC % 0x10) == 0)  {\n      osThreadFlagsSet (ThreadB_Id, 1);\n    }\n    osDelay(1U);\n  }\n}\n\n\n/*\n * by creating a large array, PSPLIM will be exeeded\n * PSPLIM was setup by the RTOS according the thread's stack border\n */\nvoid thread_stack_overflow (void);\nvoid thread_stack_overflow (void) {\n  volatile uint32_t foo [1024];\n  uint32_t i;\n  for (i=0; i<1024; i++)  {\n    foo[i] = i+i;\n  }\n}  \n\n\n/*\n * trying to call into secure memory directly is not allowed\n * address 0x1000 is in secure memory according SAU configuration\n */\nvoid illegal_secure_call (void);\nvoid illegal_secure_call (void)\n{\n  void (*FuncPointer) (void) = (void (*) (void)) 0x1000;\n  FuncPointer ();\n}\n\n\n/*\n * an \"example fault\" caused ba a division by zero\n * only generates the fault when SCB_CCR_DIV_0_TRP is set\n */\nvoid div_by_zero( void );\nvoid div_by_zero( void )\n{\n  volatile unsigned int a, b, c;\n  \n  SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;\n  a = 1;\n  b = 0;\n  c = a / b;\n}  \n\n\n/*\n * try to let secure domain overwrite secure memory\n * secure application should detect this with buffer range checks\n */\nvoid getdata_attack (void);\nvoid getdata_attack (void) {\n  /* provide pointer outsite of non-secure memory */\n  GetIncidentLog_s ((IncidentLog_t *) (0x20200000 - 0x10));\n}  \n\n\n/*\n * simulate a broken non-secure application by not returning\n * a secure SysTick watchdog can be used to detect this inactivety\n */\nvoid play_dead( void );\n__NO_RETURN void play_dead( void )\n{\n  osKernelLock( );\n  while( 1 )\n  {\n    __NOP( );\n  }\n}  \n\n\ntypedef struct  {\n  void ( *TestFunc )( void );\n  const char *TestName;\n} TestCase_t;\n\n\n// array of test cases with test functions\nstatic const TestCase_t TestCases[] = {\n  { illegal_secure_call,   \"illegal secure call\" },\n  { thread_stack_overflow, \"stack overflow\" },\n  { div_by_zero,           \"div by zero\" },\n  { getdata_attack,        \"getdata attack\" },\n  { play_dead,             \"play dead\" }\n};\n\n\nextern IncidentLog_t IncidentLogCopy;\nIncidentLog_t IncidentLogCopy;\n\nextern volatile uint32_t TestCase;\nvolatile uint32_t TestCase;\n\n\n/*\n * Test case execution\n */\n__NO_RETURN void ThreadD (void *argument) {\n  uint32_t WatchdogToken;\n\n  (void)argument;\n\n  TestCase = 0xFFFFFFFF;  \n  WatchdogToken = StartWatchdog_s ();                 /* start watchdog in secure mode */\n  GetIncidentLog_s (&IncidentLogCopy);                /* get incident log and draw the table */\n\n  while (1) {\n    FeedWatchdog_s (WatchdogToken);\n    osDelay (50);\n\n    if (TestCase < (sizeof (TestCases) / sizeof(TestCases[0])))  {\n      TestCases [TestCase].TestFunc ();               /* execute selected test */\n    }\n  }\n}\n\n\nstatic const osThreadAttr_t ThreadAttr = {\n  .tz_module = 1U,                  // indicate calls to secure mode\n};\n\nint main (void) {\n\n  Status = osKernelInitialize();\n\n  ThreadA_Id = osThreadNew(ThreadA, NULL, &ThreadAttr);\n  ThreadB_Id = osThreadNew(ThreadB, NULL, &ThreadAttr);\n  ThreadC_Id = osThreadNew(ThreadC, NULL, NULL);\n  ThreadD_Id = osThreadNew(ThreadD, NULL, &ThreadAttr);\n\n  Status = osKernelStart();\n\n  for (;;);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/Abstract.txt",
    "content": "This ARM Cortex-M33 Security Test example project shows how the ARMv8-M\narchitecture reacts to potential security attacks. It uses CMSIS-Core and\nCMSIS-RTOS2 (Keil RTX5).\n\nTo execute a test case, enter in the uVision Debugger command window\n>TestCase=<n>\nwhere <n> is a test case number (0..4).\n\nAfter a test case has been executed, the security attack gets recorded in\nthe IncidentLog and the application is reset. The struct IncidentLogCopy\ncan be viewed in a watch window and shows the past four recorded incidents."
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/CM33_s.uvguix",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectGui xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_guix.xsd\">\n\n  <SchemaVersion>-6.1</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <PrjGuiSettings>\n    <LastAddFilePath></LastAddFilePath>\n  </PrjGuiSettings>\n\n  <ViewPool/>\n\n  <SECTreeCtrl>\n    <View>\n      <WinId>38003</WinId>\n      <ViewName>Registers</ViewName>\n      <TableColWidths>149 149</TableColWidths>\n    </View>\n    <View>\n      <WinId>346</WinId>\n      <ViewName>Code Coverage</ViewName>\n      <TableColWidths>1010 160</TableColWidths>\n    </View>\n    <View>\n      <WinId>204</WinId>\n      <ViewName>Performance Analyzer</ViewName>\n      <TableColWidths>1170</TableColWidths>\n    </View>\n  </SECTreeCtrl>\n\n  <TreeListPane>\n    <View>\n      <WinId>35141</WinId>\n      <ViewName>Event Statistics</ViewName>\n      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     <Optim>2</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>3</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>1</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            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<IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Secure Code</GroupName>\n          <Files>\n            <File>\n              <FileName>Abstract.txt</FileName>\n              <FileType>5</FileType>\n              <FilePath>.\\Abstract.txt</FilePath>\n            </File>\n            <File>\n              <FileName>main_s.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\main_s.c</FilePath>\n            </File>\n            <File>\n              <FileName>Hardfault.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\Hardfault.c</FilePath>\n            </File>\n            <File>\n              <FileName>IncidentLog_s.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\IncidentLog_s.c</FilePath>\n            </File>\n            <File>\n              <FileName>SysTick_s.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\SysTick_s.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Interface</GroupName>\n          <Files>\n            <File>\n              <FileName>tz_context.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\tz_context.c</FilePath>\n            </File>\n            <File>\n              <FileName>interface.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\interface.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n        <Group>\n          <GroupName>::Device</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis/>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.2.0\" condition=\"ARMv6_7_8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.5.2-dev5\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n      <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.8.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files>\n      <file attr=\"config\" category=\"linkerScript\" condition=\"Startup ARMCC6 Secure\" name=\"Device\\ARM\\ARMCM33\\Source\\ARM\\ARMCM33_ac6_s.sct\" version=\"1.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\ARMCM33_ac6_s.sct</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"header\" condition=\"TZ Secure\" name=\"Device\\ARM\\ARMCM33\\Include\\Template\\partition_ARMCM33.h\" version=\"1.1.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\partition_ARMCM33.h</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\startup_ARMCM33.c\" version=\"2.1.0\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\startup_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n      <file attr=\"config\" category=\"sourceC\" name=\"Device\\ARM\\ARMCM33\\Source\\system_ARMCM33.c\" version=\"1.0.1\">\n        <instance index=\"0\">RTE\\Device\\ARMCM33_DSP_FP_TZ\\system_ARMCM33.c</instance>\n        <component Cclass=\"Device\" Cgroup=\"Startup\" Cvariant=\"C Startup\" Cvendor=\"ARM\" Cversion=\"2.1.0\" condition=\"ARMCM33 CMSIS\" isDefaultVariant=\"1\"/>\n        <package name=\"CMSIS\" schemaVersion=\"1.7.7\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.0\"/>\n        <targetInfos>\n          <targetInfo name=\"FVP Simulation Model\"/>\n        </targetInfos>\n      </file>\n    </files>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/Hardfault.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * Project:      ARMv8-M System Recovery demo\n * Title:        hardfault.c   Hardfault handler with incident log and restart\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n \n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"IncidentLog_s.h\"\n\n\n// \\brief perform a system reset to restart the application\n__NO_RETURN void PerformReset (void)    {\n  __DSB( ) ;\n  SCB->AIRCR = ( SCB->AIRCR & ~SCB_AIRCR_VECTKEY_Msk ) |\n               ( 0x05FAUL << SCB_AIRCR_VECTKEY_Pos ) | SCB_AIRCR_SYSRESETREQ_Msk ;\n\n\t// code should never reach this (however FVP Model does not reset!)  \n  while(1)   {\n    __NOP() ;\n  }\n}\n\n\nstatic volatile uint32_t stacked_r0;\nstatic volatile uint32_t stacked_r1;\nstatic volatile uint32_t stacked_r2;\nstatic volatile uint32_t stacked_r3;\nstatic volatile uint32_t stacked_r12;\nstatic volatile uint32_t stacked_lr;\nstatic volatile uint32_t stacked_pc;\nstatic volatile uint32_t stacked_psr;\n\n// \\brief Hardfault handler in C.\n// \\param[in] hardfault_args address of stack frame\nvoid hard_fault_handler_c (uint32_t *hardfault_args) {\n  IncidentReason_t Reason;\n  uint8_t Flags ;\n  \n  stacked_r0  = hardfault_args[0];\n  stacked_r1  = hardfault_args[1];\n  stacked_r2  = hardfault_args[2];\n  stacked_r3  = hardfault_args[3];\n  \n  stacked_r12 = hardfault_args[4];\n  stacked_lr  = hardfault_args[5];\n  stacked_pc  = hardfault_args[6];\n  stacked_psr = hardfault_args[7];\n\n  /* log the incident */\n  Flags = 0 ;\n  if (SAU->SFSR & SAU_SFSR_INVEP_Msk)  {\n    /* SecureFault, invalid Secure state entry point */\n    Reason = IR_INVEP ;\n    Flags |= IS_SECURE ;\n  }\n  else if (SCB->CFSR & SCB_CFSR_STKOF_Msk)  {\n    /* UsageFault, stack overflow */ \n    Reason = IR_STKOF ;\n    Flags |= IS_SECURE ;\n  }\n  else if (SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) {\n    /* UsageFault, divide by zero when CCR.DIV_0_TRP is 1 */\n    Reason = IR_DIVBY0 ;\n    Flags |= IS_SECURE ;\n  }\n  /* AIRCR.BFHFNMINS  not set, so also non-secure faults end here */\n  else if (SCB_NS->CFSR & SCB_CFSR_STKOF_Msk)  {\n    /* UsageFault, stack overflow */ \n    Reason = IR_STKOF ;\n  }\n  else if (SCB_NS->CFSR & SCB_CFSR_DIVBYZERO_Msk)  {\n    /* UsageFault, divide by zero when CCR.DIV_0_TRP is 1 */\n    Reason = IR_DIVBY0 ;\n  }\n//todo handle SCB->SFSR AUVIOL\n  else\n  {\n    Reason = IR_UNKNOW;\n  }\n  \n  LogIncident (Reason, stacked_pc, Flags) ;\n  PerformReset ();\n\n// code should never reach this (Fast Model does not reset!)  \n  while (1)  {\n    __NOP( ) ;\n  }\n}\n\n\n// \\brief evaluate SP that was active before the exception\nvoid HardFault_Handler (void) {\n  __ASM volatile (\n    \"TST LR, #0x40\\n\"\n    \"BEQ from_nonsecure\\n\"\n  \"from_secure:\\n\"\n    \"TST LR, #0x04\\n\"\n    \"ITE EQ\\n\"\n    \"MRSEQ R0, MSP\\n\"\n    \"MRSNE R0, PSP\\n\"\n    \"B hard_fault_handler_c\\n\"\n  \"from_nonsecure:\\n\"\n    \"MRS R0, CONTROL_NS\\n\"\n    \"TST R0, #2\\n\"\n    \"ITE EQ\\n\"\n    \"MRSEQ R0, MSP_NS\\n\"\n    \"MRSNE R0, PSP_NS\\n\"\n    \"B hard_fault_handler_c\\n\"\n  );\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/Hardfault.h",
    "content": "#ifndef _HARDFAULT_H\n#define _HARDFAULT_H\n\n\nvoid PerformReset( void ) ;\n\n\n#endif  /* !_HARDFAULT_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/IncidentLog_s.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * Project:      ARMv8-M System Recovery demo\n * Title:        IncidentLog_s.c   record system faults\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n#include \"IncidentLog_s.h\"\n#include \"Hardfault.h\"\n#include <stdio.h>\n#include <string.h>\n#include <arm_cmse.h>\n#include <arm_compat.h>\n\n// locate IncidentLog buffer in uninitialized section\n// and use the linker scatter file to ensure that it is not initialized\nstatic IncidentLog_t __attribute__((section( \".bss.noinit\"))) IncidentLog;\n\n\n// time in seconds is maintained by the SysTick_Handler\n// and is captured for each incident that gets logged\nextern unsigned int Seconds ;\n\n\n\nuint32_t InitIncidentLog (void) {\n  if (INCIDENT_LOG_MAGIC_NUMBER != IncidentLog.MagicNumber) {\n    /* magig number not there, so initialization required */\n    memset( &IncidentLog, 0, sizeof( IncidentLog ));\n    IncidentLog.MagicNumber = INCIDENT_LOG_MAGIC_NUMBER;\n  }\n  return (IncidentLog.Entries[IncidentLog.RecentEntry].Time);\n}\n\n\n\nvoid LogIncident (IncidentReason_t Reason, uint32_t Location, uint8_t Flags)  {\n  IncidentLog.Entries[IncidentLog.RecentEntry].Reason   = Reason;\n  IncidentLog.Entries[IncidentLog.RecentEntry].Location = Location;\n  IncidentLog.Entries[IncidentLog.RecentEntry].Time     = Seconds;\n  IncidentLog.Entries[IncidentLog.RecentEntry].Flags    = Flags;\n  IncidentLog.RecentEntry++;\n  if (IncidentLog.RecentEntry >= INCIDENT_LOG_ENTRIES_MAX) {\n    IncidentLog.RecentEntry = 0;\n  }\n}\n\n\n__attribute__((cmse_nonsecure_entry))\nvoid LogIncident_s (IncidentReason_t Reason, uint32_t Location, uint8_t Flags)  {\n  LogIncident (Reason, Location, Flags);\n}\n\n\n__attribute__((cmse_nonsecure_entry))\nvoid GetIncidentLog_s (IncidentLog_t *IncidentLog_p) {\n  struct IncidentLog_t *IncidentLog_p_ok;\n\n  /* cmse_check_pointed_object */\n  IncidentLog_p_ok = cmse_check_address_range (IncidentLog_p, sizeof(IncidentLog_t), CMSE_NONSECURE);\n  if (IncidentLog_p_ok != NULL)  {\n    /* requested copy range is completely in non-secure memory */\n    memcpy (IncidentLog_p_ok, &IncidentLog, sizeof (IncidentLog_t));\n  }\n  else\n  {  /* requested copy range is not comnpletely in non-secure memory */\n    LogIncident (IR_SECDAT, __current_pc(), IS_SECURE);\n    PerformReset ();\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/IncidentLog_s.h",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * Project:      ARMv8-M System Recovery demo\n * Title:        IncidentLog.h   record system faults\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n\n#ifndef _INCIDENTLOG_H\n#define _INCIDENTLOG_H\n\n\n#include <stdint.h>\n\n\n/*\n * possible incident reasons used in this test program\n */\ntypedef enum  {\n  IR_UNKNOW,  /* unknown reason                                        */\n  IR_DIVBY0,  /* UsageFault, divide by zero when CCR.DIV_0_TRP is 1    */\n  IR_STKOF,   /* UsageFault, stack overflow                            */ \n  IR_INVEP,   /* SecureFault, invalid Secure state entry point         */\n  IR_WDTEXP,  /* secure systick watchdog timeout                       */\n  IR_SECDAT   /* pointer pointing to secure instead non-secure memory  */\n} IncidentReason_t;\n\n\n// incident flag\n#define IS_SECURE    (1UL << 0)    /* incident happened in secure state */\n\n\ntypedef struct  {\n  IncidentReason_t       Reason;  // incident reason \n  uint8_t                 Flags;  // secure / non-secure state\n\tuint16_t             Reserved;  // reserved (not used)\n  uint32_t                 Time;  // time stamp\n  uint32_t             Location;  // PC address of incident\n} IncidentLogEntry_t;\n\n\n#define INCIDENT_LOG_ENTRIES_MAX   (4)\n#define INCIDENT_LOG_MAGIC_NUMBER  (0xABABABAB)\n\ntypedef struct {\n  unsigned int       MagicNumber;\n  unsigned int       RecentEntry;\n  IncidentLogEntry_t Entries [INCIDENT_LOG_ENTRIES_MAX];\n} IncidentLog_t;\n\n\nuint32_t InitIncidentLog (void) ;\nvoid LogIncident_s    (IncidentReason_t Reason, uint32_t Location, uint8_t Flags);\nvoid LogIncident      (IncidentReason_t Reason, uint32_t Location, uint8_t Flags);\nvoid GetIncidentLog_s (IncidentLog_t *IncidentLog_p);\nvoid PerformReset     (void);\nvoid hard_fault_handler_c (uint32_t *hardfault_args);\n#endif  /* !_INCIDENTLOG_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00200000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00020000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM33.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33\n * @version  V1.1.1\n * @date     12. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM33_H\n#define PARTITION_ARMCM33_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM33_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/SysTick_s.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * Project:      ARMv8-M System Recovery demo\n * Title:        SysTick_s.c   SysTick handler & timeout based watchdog \n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n#include \"SysTick_s.h\"\n#include \"IncidentLog_s.h\"\n#include \"Hardfault.h\"\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n\n#define TIMEOUT_VALUE (500)  /* ms */\nstatic const uint32_t ExpectedToken = 0xAB54AB23;\nuint32_t Seconds ;\nstatic uint32_t Timeout ;\n\n\n// Secure SysTick handler\nvoid SysTick_Handler (void) {\n  static unsigned int Milliseconds; \n  \n  Milliseconds++ ;\n  if (Milliseconds >= 1000) {\n    Seconds++;\n    Milliseconds = 0;\n  }\n  \n  if (Timeout != 0) { \n    Timeout-- ;\n    if (Timeout == 0) {\n      LogIncident (IR_WDTEXP, 0, IS_SECURE);\n      PerformReset ();\n    }\n  }\n}\n\n\n// Initialize Secure SysTick\n// \\param StartSeconds   setup seconds value\nvoid InitWatchdog (uint32_t StartSeconds)  {\n  Seconds = StartSeconds;\n  Timeout = 0;\n  SysTick_Config (SystemCoreClock / 1000);    /* 1 ms interval */\n}\n\n\n// Restart Watchdog\n// \\param Food    token obtained by StartWatchdog_s\n__attribute__((cmse_nonsecure_entry))\nvoid FeedWatchdog_s (uint32_t Food)  {\n  if( Food == ExpectedToken ) {\n    Timeout = TIMEOUT_VALUE;\n  }\n}\n\n\n// Start Watchdog\n// \\return Food token expected by RestartWatchdog\n__attribute__((cmse_nonsecure_entry))\nuint32_t StartWatchdog_s (void)  {\n  Timeout = TIMEOUT_VALUE;\n  return (ExpectedToken);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/SysTick_s.h",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * Project:      ARMv8-M System Recovery demo\n * Title:        SysTick_s.h   SysTick handler & timeout based watchdog \n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n#ifndef _SYSTICK_S_H\n#define _SYSTICK_S_H\n\n#include <stdint.h>\n\n// Initialize Secure SysTick\n// \\param StartSeconds   setup seconds value\nextern void InitWatchdog (uint32_t StartSeconds);\n\n// Restart Watchdog\n// \\param Food    token obtained by StartWatchdog_s\nextern void FeedWatchdog_s (uint32_t Food);\n\n// Start Watchdog\n// \\return Food token expected by RestartWatchdog\nextern uint32_t StartWatchdog_s (void);\n\n\n#endif  /* !_SYSTICK_S_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/interface.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * interface.c      Secure/non-secure callable application code\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n\n#include <arm_cmse.h>     // CMSE definitions\n#include \"interface.h\"    // Header file with secure interface API\n\n/* typedef for non-secure callback functions */\ntypedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call));\n\n/* Non-secure callable (entry) function */\nint func1(int x) __attribute__((cmse_nonsecure_entry)) { \n  return x+3; \n}\n\n/* Non-secure callable (entry) function, calling a non-secure callback function */\nint func2(funcptr callback, int x)  __attribute__((cmse_nonsecure_entry))\t{\n\tfuncptr_NS callback_NS;               // non-secure callback function pointer\n\tint y;\n\t\n\t/* return function pointer with cleared LSB */\n  callback_NS = (funcptr_NS)cmse_nsfptr_create(callback);\n\t\n\ty = callback_NS (x+1);\n\t\n\treturn (y+2);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/interface.h",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * interface.h    API definition for the non-secure state\n *\n * Version 1.0\n *    Initial Release\n *---------------------------------------------------------------------------*/\n\n/* Function pointer declaration */\ntypedef int (*funcptr)(int);\n\n/* Non-secure callable functions */\nextern int func1(int x);\nextern int func2(funcptr callback, int x);\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/main_s.c",
    "content": "/*\n * Copyright (c) 2013-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        15. October 2016\n * $Revision:    1.1.0\n *\n * Project:      TrustZone for ARMv8-M\n * Title:        Code template for secure main function\n *\n *---------------------------------------------------------------------------*/\n \n/* Use CMSE intrinsics */\n#include <arm_cmse.h>\n \n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"IncidentLog_s.h\"\n#include \"SysTick_s.h\"\n \n/* TZ_START_NS: Start address of non-secure application */\n#ifndef TZ_START_NS\n#define TZ_START_NS (0x200000U)\n#endif\n \n/* typedef for non-secure callback functions */\ntypedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));\n \n/* Secure main() */\nint main(void) {\n  funcptr_void NonSecure_ResetHandler;\n \n  /* Add user setup code for secure part here*/\n \n  /* Set non-secure main stack (MSP_NS) */\n  __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));\n \n  InitWatchdog (InitIncidentLog ());\n \n  /* Get non-secure reset handler */\n  NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));\n \n  /* Start non-secure state software application */\n  NonSecure_ResetHandler();\n \n  /* Non-secure software does not return, this code is not executed */\n  while (1) {\n    __NOP();\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/CM33_s/tz_context.c",
    "content": "/*\n * Copyright (c) 2015-2016 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------------\n *\n * $Date:        15. October 2016\n * $Revision:    1.1.0\n *\n * Project:      TrustZone for ARMv8-M\n * Title:        Context Management for ARMv8-M TrustZone - Sample implementation\n *\n *---------------------------------------------------------------------------*/\n \n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"tz_context.h\"\n\n/// Number of process slots (threads may call secure library code)\n#ifndef TZ_PROCESS_STACK_SLOTS\n#define TZ_PROCESS_STACK_SLOTS     8U\n#endif\n\n/// Stack size of the secure library code\n#ifndef TZ_PROCESS_STACK_SIZE\n#define TZ_PROCESS_STACK_SIZE      256U\n#endif\n\ntypedef struct {\n  uint32_t sp_top;      // stack space top\n  uint32_t sp_limit;    // stack space limit\n  uint32_t sp;          // current stack pointer\n} stack_info_t;\n\nstatic stack_info_t ProcessStackInfo  [TZ_PROCESS_STACK_SLOTS];\nstatic uint64_t     ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];\nstatic uint32_t     ProcessStackFreeSlot = 0xFFFFFFFFU;\n\n\n/// Initialize secure context memory system\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_InitContextSystem_S (void) {\n  uint32_t n;\n\n  if (__get_IPSR() == 0U) {\n    return 0U;  // Thread Mode\n  }\n\n  for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {\n    ProcessStackInfo[n].sp = 0U;\n    ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];\n    ProcessStackInfo[n].sp_top   = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;\n    *((uint32_t *)ProcessStackMemory[n]) = n + 1U;\n  }\n  *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;\n\n  ProcessStackFreeSlot = 0U;\n\n  // Default process stack pointer and stack limit\n  __set_PSPLIM((uint32_t)ProcessStackMemory);\n  __set_PSP   ((uint32_t)ProcessStackMemory);\n\n  // Privileged Thread Mode using PSP\n  __set_CONTROL(0x02U);\n\n  return 1U;    // Success\n}\n\n\n/// Allocate context memory for calling secure software modules in TrustZone\n/// \\param[in]  module   identifies software modules called from non-secure mode\n/// \\return value != 0 id TrustZone memory slot identifier\n/// \\return value 0    no memory available or internal error\n__attribute__((cmse_nonsecure_entry))\nTZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {\n  uint32_t slot;\n\n  (void)module; // Ignore (fixed Stack size)\n\n  if (__get_IPSR() == 0U) {\n    return 0U;  // Thread Mode\n  }\n\n  if (ProcessStackFreeSlot == 0xFFFFFFFFU) {\n    return 0U;  // No slot available\n  }\n\n  slot = ProcessStackFreeSlot;\n  ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);\n\n  ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;\n\n  return (slot + 1U);\n}\n\n\n/// Free context memory that was previously allocated with \\ref TZ_AllocModuleContext_S\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {\n  uint32_t slot;\n\n  if (__get_IPSR() == 0U) {\n    return 0U;  // Thread Mode\n  }\n\n  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {\n    return 0U;  // Invalid ID\n  }\n\n  slot = id - 1U;\n\n  if (ProcessStackInfo[slot].sp == 0U) {\n    return 0U;  // Inactive slot\n  }\n  ProcessStackInfo[slot].sp = 0U;\n\n  *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;\n  ProcessStackFreeSlot = slot;\n\n  return 1U;    // Success\n}\n\n\n/// Load secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {\n  uint32_t slot;\n\n  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {\n    return 0U;  // Thread Mode or using Main Stack for threads\n  }\n\n  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {\n    return 0U;  // Invalid ID\n  }\n\n  slot = id - 1U;\n\n  if (ProcessStackInfo[slot].sp == 0U) {\n    return 0U;  // Inactive slot\n  }\n\n  // Setup process stack pointer and stack limit\n  __set_PSPLIM(ProcessStackInfo[slot].sp_limit);\n  __set_PSP   (ProcessStackInfo[slot].sp);\n\n  return 1U;    // Success\n}\n\n\n/// Store secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\n__attribute__((cmse_nonsecure_entry))\nuint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {\n  uint32_t slot;\n  uint32_t sp;\n\n  if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {\n    return 0U;  // Thread Mode or using Main Stack for threads\n  }\n\n  if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {\n    return 0U;  // Invalid ID\n  }\n\n  slot = id - 1U;\n\n  if (ProcessStackInfo[slot].sp == 0U) {\n    return 0U;  // Inactive slot\n  }\n\n  sp = __get_PSP();\n  if ((sp < ProcessStackInfo[slot].sp_limit) ||\n      (sp > ProcessStackInfo[slot].sp_top)) {\n    return 0U;  // SP out of range\n  }\n  ProcessStackInfo[slot].sp = sp;\n\n  // Default process stack pointer and stack limit\n  __set_PSPLIM((uint32_t)ProcessStackMemory);\n  __set_PSP   ((uint32_t)ProcessStackMemory);\n\n  return 1U;    // Success\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/Debug.ini",
    "content": "LOAD \"..\\\\CM33_ns\\\\Objects\\\\CM33_ns.axf\" incremental\nLOAD \"..\\\\CM33_s\\\\Objects\\\\CM33_s.axf\" incremental\nRESET\ng, \\\\CM33_s\\main_s\\main"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/RTOS_Faults.uvmpw",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectWorkspace xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_mpw.xsd\">\n\n  <SchemaVersion>1.0</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <WorkspaceName>WorkSpace</WorkspaceName>\n\n  <project>\n    <PathAndName>.\\CM33_s\\CM33_s.uvprojx</PathAndName>\n    <NodeIsActive>1</NodeIsActive>\n    <NodeIsExpanded>1</NodeIsExpanded>\n  </project>\n\n  <project>\n    <PathAndName>.\\CM33_ns\\CM33_ns.uvprojx</PathAndName>\n    <NodeIsExpanded>1</NodeIsExpanded>\n  </project>\n\n</ProjectWorkspace>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples/TrustZoneV8M/RTOS_Faults/RTOS_Faults.uvmpw.uvgui",
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    "content": "The RTX_Blinky project is a simple RTX Kernel based example\nfor a simulated Cortex-M3 device\n\nExample functionality:\n - Clock Settings:\n   - XTAL    =  50 MHz\n   - Core    =  25 MHz\n\nThe simple RTX Kernel based example simulates the step-motor \ndriver. Four LEDs are blinking simulating the activation of \nthe four output driver stages\nThe simulation does not provide LEDs, so the state changes\nare output on the Debug printf window:\n\n- phase A\n- phase B\n- phase C\n- phase D\n\nThis example simulates Half step driver mode and\nCW rotation direction.\n\n\nThe BLINKY example program is available for one target:\n\n  Simulation:          configured for a simulated on-chip Flash\n\nThe example is compatible with other Cortex-M class devices.\nSimply open the project settings, navigate to Device tab and\nselect another Cortex-M class device.\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/Blinky/Blinky/Blinky.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\.iar\\config\\debugger\\ARMCM3.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    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     <name>FlashLoadersV3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>7</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>1</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n    <configuration>\n        <name>Release</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>8.50.1.24770</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>ARMSIM_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>7</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/Blinky/Blinky/Blinky.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\r\n<project>\r\n    <fileVersion>3</fileVersion>\r\n    <configuration>\r\n        <name>Debug</name>\r\n        <toolchain>\r\n            <name>ARM</name>\r\n        </toolchain>\r\n        <debug>1</debug>\r\n        <settings>\r\n            <name>General</name>\r\n            <archiveVersion>3</archiveVersion>\r\n            <data>\r\n                <version>35</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>BrowseInfoPath</name>\r\n                    <state>Debug\\BrowseInfo</state>\r\n                </option>\r\n                <option>\r\n                    <name>ExePath</name>\r\n                    <state>Debug\\Exe</state>\r\n                </option>\r\n                <option>\r\n                    <name>ObjPath</name>\r\n                    <state>Debug\\Obj</state>\r\n                </option>\r\n                <option>\r\n                    <name>ListPath</name>\r\n                    <state>Debug\\List</state>\r\n                </option>\r\n                <option>\r\n                    <name>GEndianMode</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>Input description</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>Output description</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GOutputBinary</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGCoreOrChip</name>\r\n                    <state>2</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibSelect</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibSelectSlave</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>RTDescription</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>OGProductVersion</name>\r\n                    <state>8.50.1.24770</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGLastSavedByProductVersion</name>\r\n                    <state>9.30.1.50052</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGChipSelectEditMenu</name>\r\n                    <state>Default\tNone</state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLowLevelInterface</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>GEndianModeBE</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGBufferedTerminalOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GenStdoutInterface</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>RTConfigPath2</name>\r\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\r\n                </option>\r\n                <option>\r\n                    <name>GBECoreSlave</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGUseCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGUseCmsisDspLib</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibThreads</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CoreVariant</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>GFPUDeviceSlave</name>\r\n                    <state>Default\tNone</state>\r\n                </option>\r\n                <option>\r\n                    <name>FPU2</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>NrRegs</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>NEON</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GFPUCoreSlave2</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGCMSISPackSelectDevice</name>\r\n                </option>\r\n                <option>\r\n                    <name>OgLibHeap</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGLibAdditionalLocale</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGPrintfVariant</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGPrintfMultibyteSupport</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGScanfVariant</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGScanfMultibyteSupport</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLocaleTags</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLocaleDisplayOnly</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>DSPExtension</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>TrustZone</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>TrustZoneModes</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGAarch64Abi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OG_32_64Device</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>BuildFilesPath</name>\r\n                    <state>Debug</state>\r\n                </option>\r\n                <option>\r\n                    <name>PointerAuthentication</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FPU64</name>\r\n                    <state>1</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>ICCARM</name>\r\n            <archiveVersion>2</archiveVersion>\r\n            <data>\r\n                <version>37</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>CCDefines</name>\r\n                    <state>$CMSIS_PACK_DEVICE_DEFINES$</state>\r\n                    <state>_RTE_</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocComments</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocLine</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCMnemonics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCMessages</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListAssFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListAssSource</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEnableRemarks</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagSuppress</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagRemark</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagWarning</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagError</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCObjPrefix</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCAllowList</name>\r\n                    <version>1</version>\r\n                    <state>00000000</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDebugInfo</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IEndianMode</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IExtraOptionsCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IExtraOptions</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCLangConformance</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCSignedPlainChar</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCRequirePrototypes</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagWarnAreErr</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCCompilerRuntimeInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OutputFile</name>\r\n                    <state>$FILE_BNAME$.o</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCLibConfigHeader</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>PreInclude</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCIncludePath2</name>\r\n                    <state>$CMSIS_PACK_DEVICE_INCLUDES$</state>\r\n                    <state>$CMSIS_PACK_INCLUDES$</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCStdIncCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCCodeSection</name>\r\n                    <state>.text</state>\r\n                </option>\r\n                <option>\r\n                    <name>IProcessorMode2</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptLevel</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptStrategy</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptLevelSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPosIndRopi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPosIndRwpi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPosIndNoDynInit</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccLang</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCDialect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccAllowVLA</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccStaticDestr</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCppInlineSemantics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccFloatSemantics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptimizationNoSizeConstraints</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCNoLiteralPool</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptStrategySlave</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCGuardCalls</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncSource</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncOutputBom</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncInput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccExceptions2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccRTTI2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OICompilerExtraOption</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCStackProtection</name>\r\n                    <state>0</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>AARM</name>\r\n            <archiveVersion>2</archiveVersion>\r\n            <data>\r\n                <version>11</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>AObjPrefix</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AEndian</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>ACaseSensitivity</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacroChars</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnWhat</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnOne</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnRange1</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnRange2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>ADebug</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AltRegisterNames</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>ADefines</name>\r\n                    <state>$CMSIS_PACK_DEVICE_DEFINES$</state>\r\n                    <state>_RTE_</state>\r\n                </option>\r\n                <option>\r\n                    <name>AList</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AListHeader</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AListing</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>Includes</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacDefs</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacExps</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacExec</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OnlyAssed</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MultiLine</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PageLengthCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PageLength</name>\r\n                    <state>80</state>\r\n                </option>\r\n                <option>\r\n                    <name>TabSpacing</name>\r\n                    <state>8</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRef</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefDefines</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefInternal</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefDual</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AOutputFile</name>\r\n                    <state>$FILE_BNAME$.o</state>\r\n                </option>\r\n                <option>\r\n                    <name>ALimitErrorsCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>ALimitErrorsEdit</name>\r\n                    <state>100</state>\r\n                </option>\r\n                <option>\r\n                    <name>AIgnoreStdInclude</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AUserIncludes</name>\r\n                    <state>$CMSIS_PACK_DEVICE_INCLUDES$</state>\r\n                    <state>$CMSIS_PACK_INCLUDES$</state>\r\n                </option>\r\n                <option>\r\n                    <name>AExtraOptionsCheckV2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AExtraOptionsV2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AsmNoLiteralPool</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PreInclude</name>\r\n                    <state></state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>OBJCOPY</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>1</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>OOCOutputFormat</name>\r\n                    <version>3</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OCOutputOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCOutputFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCCommandLineProducer</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCObjCopyEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>CUSTOM</name>\r\n            <archiveVersion>3</archiveVersion>\r\n            <data>\r\n                <extensions></extensions>\r\n                <cmdline></cmdline>\r\n                <hasPrio>0</hasPrio>\r\n                <buildSequence>inputOutputBased</buildSequence>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>BUILDACTION</name>\r\n            <archiveVersion>1</archiveVersion>\r\n            <data>\r\n                <prebuild></prebuild>\r\n                <postbuild></postbuild>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>ILINK</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>27</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>IlinkLibIOConfig</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkInputFileSlave</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOutputFile</name>\r\n                    <state>Blinky.out</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDebugInfoEnable</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkKeepSymbols</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySymbol</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySegment</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryAlign</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDefines</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkConfigDefines</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkMapFile</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogInitialization</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogModule</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogSection</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogVeneer</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFile</name>\r\n                    <state>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\.iar\\config\\linker\\ARMCM3.icf</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFileSlave</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEnableRemarks</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkSuppressDiags</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsRem</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsWarn</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsErr</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWarningsAreErrors</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkUseExtraOptions</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkExtraOptions</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLowLevelInterfaceSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkAutoLibEnable</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkAdditionalLibs</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOverrideProgramEntryLabel</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProgramEntryLabelSelect</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProgramEntryLabel</name>\r\n                    <state>__iar_program_start</state>\r\n                </option>\r\n                <option>\r\n                    <name>DoFill</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerByte</name>\r\n                    <state>0xFF</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerStart</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerEnd</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcSize</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcAlign</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcPoly</name>\r\n                    <state>0x11021</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcCompl</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcBitOrder</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcInitialValue</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>DoCrc</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkBE8Slave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkBufferedTerminalOutput</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStdoutInterfaceSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcFullSize</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIElfToolPostProcess</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogAutoLibSelect</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogRedirSymbols</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogUnusedFragments</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCrcReverseByteOrder</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCrcUseAsInput</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptInline</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptExceptionsAllow</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptExceptionsForce</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptMergeDuplSections</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptUseVfe</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptForceVfe</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackAnalysisEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackControlFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackCallGraphFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcAlgorithm</name>\r\n                    <version>1</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcUnitSize</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkThreadsSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogCallGraph</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFile_AltDefault</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncInput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncOutputBom</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkHeapSelect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLocaleSelect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTrustzoneImportLibraryOut</name>\r\n                    <state>Blinky_import_lib.o</state>\r\n                </option>\r\n                <option>\r\n                    <name>OILinkExtraOption</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryFile2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySymbol2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySegment2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryAlign2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogCrtRoutineSelection</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogFragmentInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogInlining</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogMerging</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDemangle</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWrapperFileEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWrapperFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>IARCHIVE</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>0</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>IarchiveInputs</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IarchiveOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IarchiveOutput</name>\r\n                    <state>###Unitialized###</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n    </configuration>\r\n    <configuration>\r\n        <name>Release</name>\r\n        <toolchain>\r\n            <name>ARM</name>\r\n        </toolchain>\r\n        <debug>0</debug>\r\n        <settings>\r\n            <name>General</name>\r\n            <archiveVersion>3</archiveVersion>\r\n            <data>\r\n                <version>35</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>BrowseInfoPath</name>\r\n                    <state>Release\\BrowseInfo</state>\r\n                </option>\r\n                <option>\r\n                    <name>ExePath</name>\r\n                    <state>Release\\Exe</state>\r\n                </option>\r\n                <option>\r\n                    <name>ObjPath</name>\r\n                    <state>Release\\Obj</state>\r\n                </option>\r\n                <option>\r\n                    <name>ListPath</name>\r\n                    <state>Release\\List</state>\r\n                </option>\r\n                <option>\r\n                    <name>GEndianMode</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>Input description</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>Output description</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GOutputBinary</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGCoreOrChip</name>\r\n                    <state>2</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibSelect</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibSelectSlave</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>RTDescription</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>OGProductVersion</name>\r\n                    <state>8.50.1.24770</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGLastSavedByProductVersion</name>\r\n                    <state>8.50.1.24770</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGChipSelectEditMenu</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLowLevelInterface</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GEndianModeBE</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGBufferedTerminalOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GenStdoutInterface</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>RTConfigPath2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GBECoreSlave</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGUseCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGUseCmsisDspLib</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibThreads</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CoreVariant</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>GFPUDeviceSlave</name>\r\n                    <state>-</state>\r\n                </option>\r\n                <option>\r\n                    <name>FPU2</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>NrRegs</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>NEON</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GFPUCoreSlave2</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGCMSISPackSelectDevice</name>\r\n                </option>\r\n                <option>\r\n                    <name>OgLibHeap</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGLibAdditionalLocale</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGPrintfVariant</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGPrintfMultibyteSupport</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGScanfVariant</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGScanfMultibyteSupport</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLocaleTags</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLocaleDisplayOnly</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>DSPExtension</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>TrustZone</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>TrustZoneModes</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGAarch64Abi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OG_32_64Device</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>BuildFilesPath</name>\r\n                    <state>Release</state>\r\n                </option>\r\n                <option>\r\n                    <name>PointerAuthentication</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FPU64</name>\r\n                    <state>1</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>ICCARM</name>\r\n            <archiveVersion>2</archiveVersion>\r\n            <data>\r\n                <version>37</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>CCDefines</name>\r\n                    <state>NDEBUG</state>\r\n                    <state>$CMSIS_PACK_DEVICE_DEFINES$</state>\r\n                    <state>_RTE_</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocComments</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocLine</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCMnemonics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCMessages</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListAssFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListAssSource</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEnableRemarks</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagSuppress</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagRemark</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagWarning</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagError</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCObjPrefix</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCAllowList</name>\r\n                    <version>1</version>\r\n                    <state>11111110</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDebugInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IEndianMode</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IExtraOptionsCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IExtraOptions</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCLangConformance</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCSignedPlainChar</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCRequirePrototypes</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagWarnAreErr</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCCompilerRuntimeInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OutputFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCLibConfigHeader</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>PreInclude</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCIncludePath2</name>\r\n                    <state>$CMSIS_PACK_DEVICE_INCLUDES$</state>\r\n                    <state>$CMSIS_PACK_INCLUDES$</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCStdIncCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCCodeSection</name>\r\n                    <state>.text</state>\r\n                </option>\r\n                <option>\r\n                    <name>IProcessorMode2</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptLevel</name>\r\n                    <state>3</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptStrategy</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptLevelSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPosIndRopi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPosIndRwpi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPosIndNoDynInit</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccLang</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCDialect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccAllowVLA</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccStaticDestr</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCppInlineSemantics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccFloatSemantics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptimizationNoSizeConstraints</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCNoLiteralPool</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptStrategySlave</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCGuardCalls</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncSource</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncOutputBom</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncInput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccExceptions2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccRTTI2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OICompilerExtraOption</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCStackProtection</name>\r\n                    <state>0</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>AARM</name>\r\n            <archiveVersion>2</archiveVersion>\r\n            <data>\r\n                <version>11</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>AObjPrefix</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AEndian</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>ACaseSensitivity</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacroChars</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnWhat</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnOne</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnRange1</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnRange2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>ADebug</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AltRegisterNames</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>ADefines</name>\r\n                    <state>$CMSIS_PACK_DEVICE_DEFINES$</state>\r\n                    <state>_RTE_</state>\r\n                </option>\r\n                <option>\r\n                    <name>AList</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AListHeader</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AListing</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>Includes</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacDefs</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacExps</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacExec</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OnlyAssed</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MultiLine</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PageLengthCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PageLength</name>\r\n                    <state>80</state>\r\n                </option>\r\n                <option>\r\n                    <name>TabSpacing</name>\r\n                    <state>8</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRef</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefDefines</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefInternal</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefDual</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AOutputFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>ALimitErrorsCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>ALimitErrorsEdit</name>\r\n                    <state>100</state>\r\n                </option>\r\n                <option>\r\n                    <name>AIgnoreStdInclude</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AUserIncludes</name>\r\n                    <state>$CMSIS_PACK_DEVICE_INCLUDES$</state>\r\n                    <state>$CMSIS_PACK_INCLUDES$</state>\r\n                </option>\r\n                <option>\r\n                    <name>AExtraOptionsCheckV2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AExtraOptionsV2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AsmNoLiteralPool</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PreInclude</name>\r\n                    <state></state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>OBJCOPY</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>1</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>OOCOutputFormat</name>\r\n                    <version>3</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OCOutputOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCOutputFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCCommandLineProducer</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCObjCopyEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>CUSTOM</name>\r\n            <archiveVersion>3</archiveVersion>\r\n            <data>\r\n                <extensions></extensions>\r\n                <cmdline></cmdline>\r\n                <hasPrio>0</hasPrio>\r\n                <buildSequence>inputOutputBased</buildSequence>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>BUILDACTION</name>\r\n            <archiveVersion>1</archiveVersion>\r\n            <data>\r\n                <prebuild></prebuild>\r\n                <postbuild></postbuild>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>ILINK</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>27</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>IlinkLibIOConfig</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkInputFileSlave</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOutputFile</name>\r\n                    <state>###Unitialized###</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDebugInfoEnable</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkKeepSymbols</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySymbol</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySegment</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryAlign</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDefines</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkConfigDefines</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkMapFile</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogInitialization</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogModule</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogSection</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogVeneer</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFile</name>\r\n                    <state>lnk0t.icf</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFileSlave</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEnableRemarks</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkSuppressDiags</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsRem</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsWarn</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsErr</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWarningsAreErrors</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkUseExtraOptions</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkExtraOptions</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLowLevelInterfaceSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkAutoLibEnable</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkAdditionalLibs</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOverrideProgramEntryLabel</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProgramEntryLabelSelect</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProgramEntryLabel</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>DoFill</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerByte</name>\r\n                    <state>0xFF</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerStart</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerEnd</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcSize</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcAlign</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcPoly</name>\r\n                    <state>0x11021</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcCompl</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcBitOrder</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcInitialValue</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>DoCrc</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkBE8Slave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkBufferedTerminalOutput</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStdoutInterfaceSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcFullSize</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIElfToolPostProcess</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogAutoLibSelect</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogRedirSymbols</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogUnusedFragments</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCrcReverseByteOrder</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCrcUseAsInput</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptInline</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptExceptionsAllow</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptExceptionsForce</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptMergeDuplSections</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptUseVfe</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptForceVfe</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackAnalysisEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackControlFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackCallGraphFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcAlgorithm</name>\r\n                    <version>1</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcUnitSize</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkThreadsSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogCallGraph</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFile_AltDefault</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncInput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncOutputBom</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkHeapSelect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLocaleSelect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTrustzoneImportLibraryOut</name>\r\n                    <state>###Unitialized###</state>\r\n                </option>\r\n                <option>\r\n                    <name>OILinkExtraOption</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryFile2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySymbol2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySegment2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryAlign2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogCrtRoutineSelection</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogFragmentInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogInlining</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogMerging</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDemangle</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWrapperFileEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWrapperFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>IARCHIVE</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>0</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>IarchiveInputs</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IarchiveOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IarchiveOutput</name>\r\n                    <state>###Unitialized###</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n    </configuration>\r\n    <file>\r\n        <name>$PROJ_DIR$\\..\\Blinky.c</name>\r\n    </file>\r\n    <group>\r\n        <name>CMSIS-Pack</name>\r\n        <tag>CMSISPack.Component</tag>\r\n        <file>\r\n            <name>$PROJ_DIR$\\RTE\\RTE_Components.h</name>\r\n        </file>\r\n        <group>\r\n            <name>CMSIS.RTOS2.Keil RTX5 Source</name>\r\n            <tag>CMSISPack.Component</tag>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/Source/os_systick.c</name>\r\n            </file>\r\n            <file>\r\n                <name>$PROJ_DIR$\\RTE\\CMSIS\\RTX_Config.c</name>\r\n            </file>\r\n            <file>\r\n                <name>$PROJ_DIR$\\RTE\\CMSIS\\RTX_Config.h</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_delay.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_evflags.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_evr.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_kernel.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_lib.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_memory.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_mempool.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_mutex.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_semaphore.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_system.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_thread.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_timer.c</name>\r\n            </file>\r\n        </group>\r\n        <group>\r\n            <name>Device Startup</name>\r\n            <tag>CMSISPack.Component</tag>\r\n            <file>\r\n                <name>$PROJ_DIR$\\RTE\\Device\\ARMCM3\\startup_ARMCM3.s</name>\r\n            </file>\r\n            <file>\r\n                <name>$PROJ_DIR$\\RTE\\Device\\ARMCM3\\system_ARMCM3.c</name>\r\n            </file>\r\n        </group>\r\n    </group>\r\n    <cmsisPackSettings>\r\n        <rte>&lt;?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\"?&gt;\r\r\n&lt;configuration xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\"&gt;\r\r\n  &lt;packages/&gt;\r\r\n  &lt;device Dclock=\"10000000\" Dcore=\"Cortex-M3\" DcoreVersion=\"r2p1\" Dendian=\"Little-endian\" Dfamily=\"ARM Cortex M3\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Dname=\"ARMCM3\" Dvendor=\"ARM:82\" info=\"ARM , 128 KB RAM, 256 KB ROM\" url=\"http://www.keil.com/dd2/arm/armcm3\"&gt;\r\r\n    &lt;package info=\"CMSIS (Common Microcontroller Software Interface Standard)\" name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n  &lt;/device&gt;\r\r\n  &lt;toolchain Tcompiler=\"IAR\" Toutput=\"exe\"/&gt;\r\r\n  &lt;components&gt;\r\r\n    &lt;component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.7.0\"&gt;\r\r\n      &lt;package name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n      &lt;file category=\"doc\" name=\"CMSIS/Documentation/Core/html/index.html\"/&gt;\r\r\n      &lt;file category=\"include\" name=\"CMSIS/Core/Include/\"/&gt;\r\r\n      &lt;file category=\"header\" condition=\"TrustZone\" name=\"CMSIS/Core/Include/tz_context.h\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"sourceC\" condition=\"TZ Secure\" name=\"CMSIS/Core/Template/ARMv8-M/main_s.c\" select=\"Secure mode 'main' module for ARMv8-M\" version=\"1.1.1\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"sourceC\" condition=\"TZ Secure\" name=\"CMSIS/Core/Template/ARMv8-M/tz_context.c\" select=\"RTOS Context Management (TrustZone for ARMv8-M)\" version=\"1.1.1\"/&gt;\r\r\n    &lt;/component&gt;\r\r\n    &lt;component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\"&gt;\r\r\n      &lt;package name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n      &lt;file category=\"doc\" name=\"CMSIS/Documentation/RTOS2/html/rtx5_impl.html\"/&gt;\r\r\n      &lt;file category=\"header\" name=\"CMSIS/RTOS2/RTX/Include/rtx_os.h\"/&gt;\r\r\n      &lt;file attr=\"config\" category=\"header\" name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.h\" version=\"5.6.0\"/&gt;\r\r\n      &lt;file attr=\"config\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.c\" version=\"5.2.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/main.c\" select=\"CMSIS-RTOS2 'main' function\" version=\"2.1.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Events.c\" select=\"CMSIS-RTOS2 Events\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/MemPool.c\" select=\"CMSIS-RTOS2 Memory Pool\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/MsgQueue.c\" select=\"CMSIS-RTOS2 Message Queue\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Mutex.c\" select=\"CMSIS-RTOS2 Mutex\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Semaphore.c\" select=\"CMSIS-RTOS2 Semaphore\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Thread.c\" select=\"CMSIS-RTOS2 Thread\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Timer.c\" select=\"CMSIS-RTOS2 Timer\" version=\"2.0.1\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/svc_user.c\" select=\"CMSIS-RTOS2 SVC User Table\" version=\"1.0.0\"/&gt;\r\r\n      &lt;file category=\"other\" name=\"CMSIS/RTOS2/RTX/RTX5.scvd\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_kernel.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_thread.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_delay.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_timer.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evflags.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mutex.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_semaphore.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_memory.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mempool.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_system.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evr.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_lib.c\"/&gt;\r\r\n      &lt;file category=\"source\" condition=\"IARASM ARMv7-M\" name=\"CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/Source/os_systick.c\"/&gt;\r\r\n    &lt;/component&gt;\r\r\n    &lt;component Cclass=\"Device\" Cgroup=\"Startup\" Cvendor=\"ARM\" Cversion=\"1.2.2\" deviceDependent=\"1\"&gt;\r\r\n      &lt;package name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n      &lt;file category=\"header\" deviceDependent=\"1\" name=\"Device/ARM/ARMCM3/Include/ARMCM3.h\"/&gt;\r\r\n      &lt;file attr=\"config\" category=\"sourceAsm\" condition=\"IAR\" deviceDependent=\"1\" name=\"Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s\" version=\"1.0.0\"/&gt;\r\r\n      &lt;file attr=\"config\" category=\"sourceC\" deviceDependent=\"1\" name=\"Device/ARM/ARMCM3/Source/system_ARMCM3.c\" version=\"1.0.1\"/&gt;\r\r\n    &lt;/component&gt;\r\r\n  &lt;/components&gt;\r\r\n  &lt;apis&gt;\r\r\n    &lt;api Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Cvendor=\"ARM\" Cversion=\"2.2.0\" exclusive=\"1\"&gt;\r\r\n      &lt;package name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n      &lt;file category=\"doc\" name=\"CMSIS/Documentation/RTOS2/html/index.html\"/&gt;\r\r\n      &lt;file category=\"header\" name=\"CMSIS/RTOS2/Include/cmsis_os2.h\"/&gt;\r\r\n    &lt;/api&gt;\r\r\n  &lt;/apis&gt;\r\r\n&lt;/configuration&gt;\r\r\n</rte>\r\n    </cmsisPackSettings>\r\n</project>\r\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/Blinky/Blinky/settings/Blinky.crun",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<crun>\n    <version>1</version>\n    <filter_entries>\n        <filter index=\"0\" type=\"default\">\n            <type>*</type>\n            <start_file>*</start_file>\n            <end_file>*</end_file>\n            <action_debugger>0</action_debugger>\n            <action_log>1</action_log>\n        </filter>\n    </filter_entries>\n</crun>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/Blinky/Blinky/settings/Blinky.dbgdt",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<Project>\n    <WindowStorage>\n        <ChildIdMap>\n            <TB_CMSISPACK>34048</TB_CMSISPACK>\n            <TB_DEBUG>34049</TB_DEBUG>\n            <TB_MAIN2>34050</TB_MAIN2>\n            <WIN_AUTO>34051</WIN_AUTO>\n            <WIN_BREAKPOINTS>34052</WIN_BREAKPOINTS>\n            <WIN_BUILD>34053</WIN_BUILD>\n            <WIN_CALL_GRAPH>34054</WIN_CALL_GRAPH>\n            <WIN_CALL_STACK>34055</WIN_CALL_STACK>\n            <WIN_CMSISPACK_AGENT_LOG>34056</WIN_CMSISPACK_AGENT_LOG>\n            <WIN_CODECOVERAGE>34057</WIN_CODECOVERAGE>\n            <WIN_CORES>34058</WIN_CORES>\n            <WIN_CUSTOM_SFR>34059</WIN_CUSTOM_SFR>\n            <WIN_C_STAT>34060</WIN_C_STAT>\n            <WIN_DATA_LOG>34061</WIN_DATA_LOG>\n            <WIN_DATA_STAT>34062</WIN_DATA_STAT>\n            <WIN_DEBUGGER_MACROS>34063</WIN_DEBUGGER_MACROS>\n            <WIN_DEBUG_LOG>34064</WIN_DEBUG_LOG>\n            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    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/Blinky/Blinky/settings/Blinky.dnx",
    "content": "<?xml version=\"1.0\"?>\n<settings>\n    <Stack>\n        <FillEnabled>0</FillEnabled>\n        <OverflowWarningsEnabled>1</OverflowWarningsEnabled>\n        <WarningThreshold>90</WarningThreshold>\n        <SpWarningsEnabled>1</SpWarningsEnabled>\n        <WarnLogOnly>1</WarnLogOnly>\n        <UseTrigger>1</UseTrigger>\n        <TriggerName>main</TriggerName>\n        <LimitSize>0</LimitSize>\n        <ByteLimit>50</ByteLimit>\n    </Stack>\n    <Trace1>\n        <Enabled>0</Enabled>\n        <ShowSource>1</ShowSource>\n    </Trace1>\n    <DebugChecksum>\n        <Checksum>3153441700</Checksum>\n    </DebugChecksum>\n    <Disassembly>\n        <InstrCount>0</InstrCount>\n        <MixedMode>1</MixedMode>\n    </Disassembly>\n    <CodeCoverage>\n        <Enabled>0</Enabled>\n        <ShowSource>0</ShowSource>\n        <HideCovered>0</HideCovered>\n    </CodeCoverage>\n    <Exceptions>\n        <StopOnUncaught>_ 0</StopOnUncaught>\n        <StopOnThrow>_ 0</StopOnThrow>\n    </Exceptions>\n    <CallStack>\n        <ShowArgs>0</ShowArgs>\n    </CallStack>\n    <DriverProfiling>\n        <Enabled>0</Enabled>\n        <Mode>1</Mode>\n        <Graph>0</Graph>\n        <Symbiont>0</Symbiont>\n    </DriverProfiling>\n    <CallStackLog>\n        <Enabled>0</Enabled>\n    </CallStackLog>\n    <CallStackStripe>\n        <ShowTiming>1</ShowTiming>\n    </CallStackStripe>\n    <TermIOLog>\n        <LoggingEnabled>_ 0</LoggingEnabled>\n        <LogFile>_ \"\"</LogFile>\n    </TermIOLog>\n    <LogFile>\n        <LoggingEnabled>_ 0</LoggingEnabled>\n        <LogFile>_ \"\"</LogFile>\n        <Category>_ 0</Category>\n    </LogFile>\n    <InterruptLog>\n        <LogEnabled>0</LogEnabled>\n        <GraphEnabled>0</GraphEnabled>\n        <ShowTimeLog>1</ShowTimeLog>\n        <SumEnabled>0</SumEnabled>\n        <ShowTimeSum>1</ShowTimeSum>\n        <SumSortOrder>0</SumSortOrder>\n    </InterruptLog>\n    <DataLog>\n        <LogEnabled>0</LogEnabled>\n        <GraphEnabled>0</GraphEnabled>\n        <ShowTimeLog>1</ShowTimeLog>\n        <SumEnabled>0</SumEnabled>\n        <ShowTimeSum>1</ShowTimeSum>\n    </DataLog>\n    <DisassembleMode>\n        <mode>0</mode>\n    </DisassembleMode>\n    <Breakpoints2>\n        <Count>0</Count>\n    </Breakpoints2>\n    <Interrupts>\n        <Enabled>1</Enabled>\n        <Irq0>_ 0 400000 0 10000 0 0 100 100 0 1 \"SysTick 1 0x3C\"</Irq0>\n        <Count>1</Count>\n    </Interrupts>\n    <MemConfig>\n        <Base>1</Base>\n        <Manual>0</Manual>\n        <Ddf>1</Ddf>\n        <TypeViol>0</TypeViol>\n        <Stop>1</Stop>\n    </MemConfig>\n    <Aliases>\n        <Count>0</Count>\n        <SuppressDialog>0</SuppressDialog>\n    </Aliases>\n    <Simulator>\n        <Freq>10000000</Freq>\n        <FreqHi>0</FreqHi>\n        <MultiCoreRunAll>1</MultiCoreRunAll>\n    </Simulator>\n</settings>\n"
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  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/Blinky/Blinky.c",
    "content": "/* -------------------------------------------------------------------------- \n * Copyright (c) 2013-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    Blinky.c\n *      Purpose: RTX example program\n *\n *---------------------------------------------------------------------------*/\n\n#include <stdio.h>\n\n#include \"cmsis_os2.h\"                  // ARM::CMSIS:RTOS2:Keil RTX5\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\nosThreadId_t tid_phaseA;                /* Thread id of thread: phase_a      */\nosThreadId_t tid_phaseB;                /* Thread id of thread: phase_b      */\nosThreadId_t tid_phaseC;                /* Thread id of thread: phase_c      */\nosThreadId_t tid_phaseD;                /* Thread id of thread: phase_d      */\nosThreadId_t tid_clock;                 /* Thread id of thread: clock        */\n\nstruct phases_t {\n  int_fast8_t phaseA;\n  int_fast8_t phaseB;\n  int_fast8_t phaseC;\n  int_fast8_t phaseD;\n} g_phases;\n\n\n/*----------------------------------------------------------------------------\n *      Switch LED on\n *---------------------------------------------------------------------------*/\nvoid Switch_On (unsigned char led) {\n  printf(\"LED On:  #%d\\n\\r\", led);\n}\n\n/*----------------------------------------------------------------------------\n *      Switch LED off\n *---------------------------------------------------------------------------*/\nvoid Switch_Off (unsigned char led) {\n  printf(\"LED Off: #%d\\n\\r\", led);\n}\n\n\n/*----------------------------------------------------------------------------\n *      Function 'signal_func' called from multiple threads\n *---------------------------------------------------------------------------*/\nvoid signal_func (osThreadId_t tid)  {\n  osThreadFlagsSet(tid_clock, 0x0100);      /* set signal to clock thread    */\n  osDelay(500);                             /* delay 500ms                   */\n  osThreadFlagsSet(tid_clock, 0x0100);      /* set signal to clock thread    */\n  osDelay(500);                             /* delay 500ms                   */\n  osThreadFlagsSet(tid, 0x0001);            /* set signal to thread 'thread' */\n  osDelay(500);                             /* delay 500ms                   */\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 1 'phaseA': Phase A output\n *---------------------------------------------------------------------------*/\nvoid phaseA (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny ,osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(0);\n    g_phases.phaseA = 1;\n    signal_func(tid_phaseB);                                     /* call common signal function   */\n    g_phases.phaseA = 0;\n    Switch_Off(0);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 2 'phaseB': Phase B output\n *---------------------------------------------------------------------------*/\nvoid phaseB (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(1);\n    g_phases.phaseB = 1;\n    signal_func(tid_phaseC);                /* call common signal function   */\n    g_phases.phaseB = 0;\n    Switch_Off(1);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 3 'phaseC': Phase C output\n *---------------------------------------------------------------------------*/\nvoid phaseC (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(2);\n    g_phases.phaseC = 1;\n    signal_func(tid_phaseD);                /* call common signal function   */\n    g_phases.phaseC = 0;\n    Switch_Off(2);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 4 'phaseD': Phase D output\n *---------------------------------------------------------------------------*/\nvoid phaseD (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0001, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0001 */\n    Switch_On(3);\n    g_phases.phaseD = 1;\n    signal_func(tid_phaseA);                /* call common signal function   */\n    g_phases.phaseD = 0;\n    Switch_Off(3);\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Thread 5 'clock': Signal Clock\n *---------------------------------------------------------------------------*/\nvoid clock (void *argument) {\n  for (;;) {\n    osThreadFlagsWait(0x0100, osFlagsWaitAny, osWaitForever);    /* wait for an event flag 0x0100 */\n    osDelay(80);                            /* delay  80ms                   */\n  }\n}\n\n/*----------------------------------------------------------------------------\n *      Main: Initialize and start RTX Kernel\n *---------------------------------------------------------------------------*/\nvoid app_main (void *argument) {\n\n  tid_phaseA = osThreadNew(phaseA, NULL, NULL);\n  tid_phaseB = osThreadNew(phaseB, NULL, NULL);\n  tid_phaseC = osThreadNew(phaseC, NULL, NULL);\n  tid_phaseD = osThreadNew(phaseD, NULL, NULL);\n  tid_clock  = osThreadNew(clock,  NULL, NULL);\n\n  osThreadFlagsSet(tid_phaseA, 0x0001);     /* set signal to phaseA thread   */\n\n  osDelay(osWaitForever);\n}\n\nint main (void) {\n\n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  if (osKernelGetState() == osKernelReady) {\n    osKernelStart();                    // Start thread execution\n  }\n\n  while(1);\n}\n"
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  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue/Abstract.txt",
    "content": "The MsgQueue project is a simple RTX Kernel based example\nfor a simulated Cortex-M3 device\n\nExample functionality:\n - Clock Settings:\n   - XTAL    =  12 MHz\n   - Core    =  12 MHz\n\nThe simple RTX Kernel based example shows how to use a \nmessage queue to send data from one thread to another.\nThe message receiver thread prints the message contents\nto the debug output window.\n\nThe MsgQueue example program is available for one target:\n\n  Simulation:          configured for a simulated on-chip Flash\n"
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  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue/MsgQueue/MsgQueue.ewd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>Debug</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>1</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\.iar\\config\\debugger\\ARMCM3.ddf</state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>8.50.1.24770</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>ARMSIM_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state>8.50.1.24770</state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n               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 <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>7</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioJtagSpeedType</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetConnection</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetUsbComPort</name>\n                    <state>Automatic</state>\n                </option>\n                <option>\n                    <name>CCMSPFetAllowAccessToBSL</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>1</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>1</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n    <configuration>\n        <name>Release</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>C-SPY</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>32</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCVariant</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>MemOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MemFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>RunToEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RunToName</name>\n                    <state>main</state>\n                </option>\n                <option>\n                    <name>CExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDDFArgumentProducer</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadSuppressDownload</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDownloadVerifyAll</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProductVersion</name>\n                    <state>8.50.1.24770</state>\n                </option>\n                <option>\n                    <name>OCDynDriverList</name>\n                    <state>ARMSIM_ID</state>\n                </option>\n                <option>\n                    <name>OCLastSavedByProductVersion</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>UseFlashLoader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CLowLevel</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CDevice</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>FlashLoadersV3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesSuppressCheck3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesPath3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OverrideDefFlashBoard</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesOffset1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesOffset3</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCImagesUse1</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCImagesUse3</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDeviceConfigMacroFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCDebuggerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAllMTBOptions</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCores</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreWorkspace</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveProject</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCMulticoreSlaveConfiguration</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCDownloadExtraImage</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCAttachSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MassEraseBeforeFlashing</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreNrOfCoresSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCMulticoreAMPConfigType</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCMulticoreSessionFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCTpiuBaseOption</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ARMSIM_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCSimDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSimEnablePSP</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspOverrideConfig</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCSimPspConfigFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CADI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCadiMemory</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Fast Model</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCADILogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCADILogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CMSISDAP_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>4</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>CMSISDAPHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>CMSISDAPDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CMSISDAPInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CMSISDAPProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CMSISDAPSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCMSISDAPUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>GDBSERVER_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJTagBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJTagUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IJET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCIarProbeScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetResetList</name>\n                    <version>1</version>\n                    <state>10</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDuration</name>\n                    <state>300</state>\n                </option>\n                <option>\n                    <name>IjetHWResetDelay</name>\n                    <state>200</state>\n                </option>\n                <option>\n                    <name>IjetPowerFromProbe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPowerRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTargetEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetJtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetProtocolRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSwoPin</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetSwoPrescalerList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetRestoreBreakpointsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetUpdateBreakpointsEdit</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>RDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchUndef</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchData</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchPrefetch</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchMMERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchNOCPERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchCHKERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSTATERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchBUSERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchINTERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchSFERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchHARDERR</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeCfgOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCProbeConfig</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IjetProbeConfigRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetMultiCPUNumber</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetSelectedCPUBehaviour</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ICpuName</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OCJetEmuParams</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetPreferETB</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IjetTraceSettingsList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IjetTraceSizeList</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>FlashBoardPathSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIjetUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREREL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL1S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL2NS</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8AREEL3S</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CatchV8ARREL3S</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>JLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>16</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>JLinkSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCJLinkHWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>JLinkInitialSpeed</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCDoJlinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCScanChainNonARMDevices</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkMultiTarget</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkIRLength</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkCommRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTCPIP</name>\n                    <state>aaa.bbb.ccc.ddd</state>\n                </option>\n                <option>\n                    <name>CCJLinkSpeedRadioV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCUSBDevice</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRDICatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCRDICatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkBreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkResetList</name>\n                    <version>6</version>\n                    <state>5</state>\n                </option>\n                <option>\n                    <name>CCJLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkScriptFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCTcpIpAlt</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCJLinkTcpIpSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkTraceSourceDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCJLinkDeviceName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>LMIFTDI_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>LmiftdiSpeed</name>\n                    <state>500</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiDoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiLogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCLmiFtdiInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLmiftdiUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCLmiftdiResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>NULINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>PEMICRO_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>3</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCJPEMicroShowSettings</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>STLINK_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>7</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceRadio</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSTLinkInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkResetList</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSwoClockAuto</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCSwoClockEdit</name>\n                    <state>2000</state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkCatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkUsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkJtagSpeedList</name>\n                    <version>2</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkDAPNumber</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCSTLinkDebugAccessPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkUseServerSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSTLinkProbeList</name>\n                    <version>1</version>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>THIRDPARTY_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CThirdPartyDriverDll</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CThirdPartyLogFileEditB</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>TIFET_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetInterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVccTypeDefault</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>CCMSPFetVCCDefault</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCMSPFetTargetSettlingtime</name>\n              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             <option>\n                    <name>CCMSPFetRadioEraseFlash</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>XDS100_ID</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>9</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OCDriverInfo</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TIPackageOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TIPackage</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>BoardFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoLogfile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>LogFile</name>\n                    <state>$PROJ_DIR$\\cspycomm.log</state>\n                </option>\n                <option>\n                    <name>CCXds100BreakpointRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100DoUpdateBreakpoints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UpdateBreakpoints</name>\n                    <state>_call_main</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchReset</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchUndef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSWI</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchData</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchPrefetch</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchIRQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchFIQ</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCORERESET</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchMMERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchNOCPERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchCHRERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSTATERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchBUSERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchINTERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchSFERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchHARDERR</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CatchDummy</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100CpuClockEdit</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockAuto</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SwoClockEdit</name>\n                    <state>1000</state>\n                </option>\n                <option>\n                    <name>CCXds100HWResetDelay</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ResetList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNo</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCXds100UsbSerialNoSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100JtagSpeedList</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceRadio</name>\n                    <state>2</state>\n                </option>\n                <option>\n                    <name>CCXds100InterfaceCmdLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100ProbeList</name>\n                    <version>0</version>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPortRadio</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXds100SWOPort</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVccEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCXDSTargetVoltage</name>\n                    <state>###Uninitialized###</state>\n                </option>\n                <option>\n                    <name>OCXDSDigitalStatesConfigFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OCSelectedCoreName</name>\n                    <state>1</state>\n                </option>\n            </data>\n        </settings>\n        <debuggerPlugins>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\CMX\\CmxTinyArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\embOS\\embOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\FreeRtos\\FreeRtosArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\Mbed\\MbedArmPlugin2.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\OpenRTOS\\OpenRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SafeRTOS\\SafeRTOSPlugin.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\SMX\\smxAwareIarArm9BE.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\ThreadX\\ThreadXArmPlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-286-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-II\\uCOS-II-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$TOOLKIT_DIR$\\plugins\\rtos\\uCOS-III\\uCOS-III-KA-CSpy.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\Orti\\Orti.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\TargetAccessServer\\TargetAccessServer.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n            <plugin>\n                <file>$EW_DIR$\\common\\plugins\\uCProbe\\uCProbePlugin.ENU.ewplugin</file>\n                <loadFlag>0</loadFlag>\n            </plugin>\n        </debuggerPlugins>\n    </configuration>\n</project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue/MsgQueue/MsgQueue.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\r\n<project>\r\n    <fileVersion>3</fileVersion>\r\n    <configuration>\r\n        <name>Debug</name>\r\n        <toolchain>\r\n            <name>ARM</name>\r\n        </toolchain>\r\n        <debug>1</debug>\r\n        <settings>\r\n            <name>General</name>\r\n            <archiveVersion>3</archiveVersion>\r\n            <data>\r\n                <version>35</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>BrowseInfoPath</name>\r\n                    <state>Debug\\BrowseInfo</state>\r\n                </option>\r\n                <option>\r\n                    <name>ExePath</name>\r\n                    <state>Debug\\Exe</state>\r\n                </option>\r\n                <option>\r\n                    <name>ObjPath</name>\r\n                    <state>Debug\\Obj</state>\r\n                </option>\r\n                <option>\r\n                    <name>ListPath</name>\r\n                    <state>Debug\\List</state>\r\n                </option>\r\n                <option>\r\n                    <name>GEndianMode</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>Input description</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>Output description</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GOutputBinary</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGCoreOrChip</name>\r\n                    <state>2</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibSelect</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibSelectSlave</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>RTDescription</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>OGProductVersion</name>\r\n                    <state>8.50.1.24770</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGLastSavedByProductVersion</name>\r\n                    <state>9.30.1.50052</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGChipSelectEditMenu</name>\r\n                    <state>Default\tNone</state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLowLevelInterface</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>GEndianModeBE</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGBufferedTerminalOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GenStdoutInterface</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>RTConfigPath2</name>\r\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\r\n                </option>\r\n                <option>\r\n                    <name>GBECoreSlave</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGUseCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGUseCmsisDspLib</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibThreads</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CoreVariant</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>GFPUDeviceSlave</name>\r\n                    <state>Default\tNone</state>\r\n                </option>\r\n                <option>\r\n                    <name>FPU2</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>NrRegs</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>NEON</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GFPUCoreSlave2</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGCMSISPackSelectDevice</name>\r\n                </option>\r\n                <option>\r\n                    <name>OgLibHeap</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGLibAdditionalLocale</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGPrintfVariant</name>\r\n                    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<state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>TrustZone</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>TrustZoneModes</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGAarch64Abi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OG_32_64Device</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>BuildFilesPath</name>\r\n                    <state>Debug</state>\r\n                </option>\r\n                <option>\r\n                    <name>PointerAuthentication</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FPU64</name>\r\n                    <state>1</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>ICCARM</name>\r\n            <archiveVersion>2</archiveVersion>\r\n            <data>\r\n                <version>37</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>CCDefines</name>\r\n                    <state>$CMSIS_PACK_DEVICE_DEFINES$</state>\r\n                    <state>_RTE_</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocComments</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocLine</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCMnemonics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCMessages</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListAssFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListAssSource</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEnableRemarks</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagSuppress</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagRemark</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagWarning</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagError</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCObjPrefix</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCAllowList</name>\r\n                    <version>1</version>\r\n                    <state>00000000</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDebugInfo</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IEndianMode</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IExtraOptionsCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IExtraOptions</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCLangConformance</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCSignedPlainChar</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCRequirePrototypes</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagWarnAreErr</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCCompilerRuntimeInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OutputFile</name>\r\n                    <state>$FILE_BNAME$.o</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCLibConfigHeader</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>PreInclude</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCIncludePath2</name>\r\n                    <state>$CMSIS_PACK_DEVICE_INCLUDES$</state>\r\n                    <state>$CMSIS_PACK_INCLUDES$</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCStdIncCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCCodeSection</name>\r\n                    <state>.text</state>\r\n                </option>\r\n                <option>\r\n                    <name>IProcessorMode2</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptLevel</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptStrategy</name>\r\n                    <version>0</version>\r\n                    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<name>IccAllowVLA</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccStaticDestr</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCppInlineSemantics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccFloatSemantics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptimizationNoSizeConstraints</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCNoLiteralPool</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptStrategySlave</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCGuardCalls</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncSource</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncOutputBom</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncInput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccExceptions2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccRTTI2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OICompilerExtraOption</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCStackProtection</name>\r\n                    <state>0</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>AARM</name>\r\n            <archiveVersion>2</archiveVersion>\r\n            <data>\r\n                <version>11</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>AObjPrefix</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AEndian</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>ACaseSensitivity</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacroChars</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnWhat</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnOne</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnRange1</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnRange2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>ADebug</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AltRegisterNames</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>ADefines</name>\r\n                    <state>$CMSIS_PACK_DEVICE_DEFINES$</state>\r\n                    <state>_RTE_</state>\r\n                </option>\r\n                <option>\r\n                    <name>AList</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AListHeader</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AListing</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>Includes</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacDefs</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacExps</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacExec</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OnlyAssed</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MultiLine</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PageLengthCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PageLength</name>\r\n                    <state>80</state>\r\n                </option>\r\n                <option>\r\n                    <name>TabSpacing</name>\r\n                    <state>8</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRef</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefDefines</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefInternal</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefDual</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AOutputFile</name>\r\n                    <state>$FILE_BNAME$.o</state>\r\n                </option>\r\n                <option>\r\n                    <name>ALimitErrorsCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>ALimitErrorsEdit</name>\r\n                    <state>100</state>\r\n                </option>\r\n                <option>\r\n                    <name>AIgnoreStdInclude</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AUserIncludes</name>\r\n                    <state>$CMSIS_PACK_DEVICE_INCLUDES$</state>\r\n                    <state>$CMSIS_PACK_INCLUDES$</state>\r\n                </option>\r\n                <option>\r\n                    <name>AExtraOptionsCheckV2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AExtraOptionsV2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AsmNoLiteralPool</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PreInclude</name>\r\n                    <state></state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>OBJCOPY</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>1</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>OOCOutputFormat</name>\r\n                    <version>3</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OCOutputOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCOutputFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCCommandLineProducer</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCObjCopyEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>CUSTOM</name>\r\n            <archiveVersion>3</archiveVersion>\r\n            <data>\r\n                <extensions></extensions>\r\n                <cmdline></cmdline>\r\n                <hasPrio>0</hasPrio>\r\n                <buildSequence>inputOutputBased</buildSequence>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>BUILDACTION</name>\r\n            <archiveVersion>1</archiveVersion>\r\n            <data>\r\n                <prebuild></prebuild>\r\n                <postbuild></postbuild>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>ILINK</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>27</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>IlinkLibIOConfig</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkInputFileSlave</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOutputFile</name>\r\n                    <state>MsgQueue.out</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDebugInfoEnable</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkKeepSymbols</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySymbol</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySegment</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryAlign</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDefines</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkConfigDefines</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkMapFile</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogInitialization</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogModule</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogSection</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogVeneer</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFile</name>\r\n                    <state>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\.iar\\config\\linker\\ARMCM3.icf</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFileSlave</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEnableRemarks</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkSuppressDiags</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsRem</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsWarn</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsErr</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWarningsAreErrors</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkUseExtraOptions</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkExtraOptions</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLowLevelInterfaceSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkAutoLibEnable</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkAdditionalLibs</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOverrideProgramEntryLabel</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProgramEntryLabelSelect</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProgramEntryLabel</name>\r\n                    <state>__iar_program_start</state>\r\n                </option>\r\n                <option>\r\n                    <name>DoFill</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerByte</name>\r\n                    <state>0xFF</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerStart</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerEnd</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcSize</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcAlign</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcPoly</name>\r\n                    <state>0x11021</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcCompl</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcBitOrder</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcInitialValue</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>DoCrc</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkBE8Slave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkBufferedTerminalOutput</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStdoutInterfaceSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcFullSize</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIElfToolPostProcess</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogAutoLibSelect</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogRedirSymbols</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogUnusedFragments</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCrcReverseByteOrder</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCrcUseAsInput</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptInline</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptExceptionsAllow</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptExceptionsForce</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptMergeDuplSections</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptUseVfe</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptForceVfe</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackAnalysisEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackControlFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackCallGraphFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcAlgorithm</name>\r\n                    <version>1</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcUnitSize</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkThreadsSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogCallGraph</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFile_AltDefault</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncInput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncOutputBom</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkHeapSelect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLocaleSelect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTrustzoneImportLibraryOut</name>\r\n                    <state>MsgQueue_import_lib.o</state>\r\n                </option>\r\n                <option>\r\n                    <name>OILinkExtraOption</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryFile2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySymbol2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySegment2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryAlign2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogCrtRoutineSelection</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogFragmentInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogInlining</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogMerging</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDemangle</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWrapperFileEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWrapperFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>IARCHIVE</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>0</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>1</debug>\r\n                <option>\r\n                    <name>IarchiveInputs</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IarchiveOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IarchiveOutput</name>\r\n                    <state>###Unitialized###</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n    </configuration>\r\n    <configuration>\r\n        <name>Release</name>\r\n        <toolchain>\r\n            <name>ARM</name>\r\n        </toolchain>\r\n        <debug>0</debug>\r\n        <settings>\r\n            <name>General</name>\r\n            <archiveVersion>3</archiveVersion>\r\n            <data>\r\n                <version>35</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>BrowseInfoPath</name>\r\n                    <state>Release\\BrowseInfo</state>\r\n                </option>\r\n                <option>\r\n                    <name>ExePath</name>\r\n                    <state>Release\\Exe</state>\r\n                </option>\r\n                <option>\r\n                    <name>ObjPath</name>\r\n                    <state>Release\\Obj</state>\r\n                </option>\r\n                <option>\r\n                    <name>ListPath</name>\r\n                    <state>Release\\List</state>\r\n                </option>\r\n                <option>\r\n                    <name>GEndianMode</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>Input description</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>Output description</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GOutputBinary</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGCoreOrChip</name>\r\n                    <state>2</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibSelect</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibSelectSlave</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>RTDescription</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>OGProductVersion</name>\r\n                    <state>8.50.1.24770</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGLastSavedByProductVersion</name>\r\n                    <state>8.50.1.24770</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGChipSelectEditMenu</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLowLevelInterface</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GEndianModeBE</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGBufferedTerminalOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GenStdoutInterface</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>RTConfigPath2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GBECoreSlave</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGUseCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGUseCmsisDspLib</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GRuntimeLibThreads</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CoreVariant</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>GFPUDeviceSlave</name>\r\n                    <state>-</state>\r\n                </option>\r\n                <option>\r\n                    <name>FPU2</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>NrRegs</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>NEON</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GFPUCoreSlave2</name>\r\n                    <version>32</version>\r\n                    <state>38</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGCMSISPackSelectDevice</name>\r\n                </option>\r\n                <option>\r\n                    <name>OgLibHeap</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGLibAdditionalLocale</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGPrintfVariant</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGPrintfMultibyteSupport</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGScanfVariant</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGScanfMultibyteSupport</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLocaleTags</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>GenLocaleDisplayOnly</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>DSPExtension</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>TrustZone</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>TrustZoneModes</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OGAarch64Abi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OG_32_64Device</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>BuildFilesPath</name>\r\n                    <state>Release</state>\r\n                </option>\r\n                <option>\r\n                    <name>PointerAuthentication</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FPU64</name>\r\n                    <state>1</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>ICCARM</name>\r\n            <archiveVersion>2</archiveVersion>\r\n            <data>\r\n                <version>37</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>CCDefines</name>\r\n                    <state>NDEBUG</state>\r\n                    <state>$CMSIS_PACK_DEVICE_DEFINES$</state>\r\n                    <state>_RTE_</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocComments</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPreprocLine</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCMnemonics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListCMessages</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListAssFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCListAssSource</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEnableRemarks</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagSuppress</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagRemark</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagWarning</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagError</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCObjPrefix</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCAllowList</name>\r\n                    <version>1</version>\r\n                    <state>11111110</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDebugInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IEndianMode</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IExtraOptionsCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IExtraOptions</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCLangConformance</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCSignedPlainChar</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCRequirePrototypes</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCDiagWarnAreErr</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCCompilerRuntimeInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OutputFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCLibConfigHeader</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>PreInclude</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CCIncludePath2</name>\r\n                    <state>$CMSIS_PACK_DEVICE_INCLUDES$</state>\r\n                    <state>$CMSIS_PACK_INCLUDES$</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCStdIncCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCCodeSection</name>\r\n                    <state>.text</state>\r\n                </option>\r\n                <option>\r\n                    <name>IProcessorMode2</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptLevel</name>\r\n                    <state>3</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptStrategy</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptLevelSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPosIndRopi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPosIndRwpi</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCPosIndNoDynInit</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccLang</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCDialect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccAllowVLA</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccStaticDestr</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCppInlineSemantics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccFloatSemantics</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptimizationNoSizeConstraints</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCNoLiteralPool</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCOptStrategySlave</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCGuardCalls</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncSource</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncOutputBom</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCEncInput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccExceptions2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IccRTTI2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OICompilerExtraOption</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CCStackProtection</name>\r\n                    <state>0</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>AARM</name>\r\n            <archiveVersion>2</archiveVersion>\r\n            <data>\r\n                <version>11</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>AObjPrefix</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AEndian</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>ACaseSensitivity</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacroChars</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnWhat</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnOne</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnRange1</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AWarnRange2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>ADebug</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AltRegisterNames</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>ADefines</name>\r\n                    <state>$CMSIS_PACK_DEVICE_DEFINES$</state>\r\n                    <state>_RTE_</state>\r\n                </option>\r\n                <option>\r\n                    <name>AList</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AListHeader</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AListing</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>Includes</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacDefs</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacExps</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>MacExec</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OnlyAssed</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>MultiLine</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PageLengthCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PageLength</name>\r\n                    <state>80</state>\r\n                </option>\r\n                <option>\r\n                    <name>TabSpacing</name>\r\n                    <state>8</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRef</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefDefines</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefInternal</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AXRefDual</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>AOutputFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>ALimitErrorsCheck</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>ALimitErrorsEdit</name>\r\n                    <state>100</state>\r\n                </option>\r\n                <option>\r\n                    <name>AIgnoreStdInclude</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AUserIncludes</name>\r\n                    <state>$CMSIS_PACK_DEVICE_INCLUDES$</state>\r\n                    <state>$CMSIS_PACK_INCLUDES$</state>\r\n                </option>\r\n                <option>\r\n                    <name>AExtraOptionsCheckV2</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>AExtraOptionsV2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>AsmNoLiteralPool</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>PreInclude</name>\r\n                    <state></state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>OBJCOPY</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>1</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>OOCOutputFormat</name>\r\n                    <version>3</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OCOutputOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCOutputFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCCommandLineProducer</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>OOCObjCopyEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>CUSTOM</name>\r\n            <archiveVersion>3</archiveVersion>\r\n            <data>\r\n                <extensions></extensions>\r\n                <cmdline></cmdline>\r\n                <hasPrio>0</hasPrio>\r\n                <buildSequence>inputOutputBased</buildSequence>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>BUILDACTION</name>\r\n            <archiveVersion>1</archiveVersion>\r\n            <data>\r\n                <prebuild></prebuild>\r\n                <postbuild></postbuild>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>ILINK</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>27</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>IlinkLibIOConfig</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkInputFileSlave</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOutputFile</name>\r\n                    <state>###Unitialized###</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDebugInfoEnable</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkKeepSymbols</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySymbol</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySegment</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryAlign</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDefines</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkConfigDefines</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkMapFile</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogFile</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogInitialization</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogModule</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogSection</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogVeneer</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFile</name>\r\n                    <state>lnk0t.icf</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFileSlave</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEnableRemarks</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkSuppressDiags</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsRem</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsWarn</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTreatAsErr</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWarningsAreErrors</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkUseExtraOptions</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkExtraOptions</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLowLevelInterfaceSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkAutoLibEnable</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkAdditionalLibs</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOverrideProgramEntryLabel</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProgramEntryLabelSelect</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProgramEntryLabel</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>DoFill</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerByte</name>\r\n                    <state>0xFF</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerStart</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>FillerEnd</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcSize</name>\r\n                    <version>0</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcAlign</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcPoly</name>\r\n                    <state>0x11021</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcCompl</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcBitOrder</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcInitialValue</name>\r\n                    <state>0x0</state>\r\n                </option>\r\n                <option>\r\n                    <name>DoCrc</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkBE8Slave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkBufferedTerminalOutput</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStdoutInterfaceSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcFullSize</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIElfToolPostProcess</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogAutoLibSelect</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogRedirSymbols</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogUnusedFragments</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCrcReverseByteOrder</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCrcUseAsInput</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptInline</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptExceptionsAllow</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptExceptionsForce</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkCmsis</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptMergeDuplSections</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptUseVfe</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkOptForceVfe</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackAnalysisEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackControlFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkStackCallGraphFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcAlgorithm</name>\r\n                    <version>1</version>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>CrcUnitSize</name>\r\n                    <version>0</version>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkThreadsSlave</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogCallGraph</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkIcfFile_AltDefault</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncInput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncOutput</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkEncOutputBom</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkHeapSelect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLocaleSelect</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkTrustzoneImportLibraryOut</name>\r\n                    <state>###Unitialized###</state>\r\n                </option>\r\n                <option>\r\n                    <name>OILinkExtraOption</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryFile2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySymbol2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinarySegment2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkRawBinaryAlign2</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogCrtRoutineSelection</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogFragmentInfo</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogInlining</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkLogMerging</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkDemangle</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWrapperFileEnable</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkWrapperFile</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n                <option>\r\n                    <name>IlinkFpuProcessor</name>\r\n                    <state>1</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n        <settings>\r\n            <name>IARCHIVE</name>\r\n            <archiveVersion>0</archiveVersion>\r\n            <data>\r\n                <version>0</version>\r\n                <wantNonLocal>1</wantNonLocal>\r\n                <debug>0</debug>\r\n                <option>\r\n                    <name>IarchiveInputs</name>\r\n                    <state></state>\r\n                </option>\r\n                <option>\r\n                    <name>IarchiveOverride</name>\r\n                    <state>0</state>\r\n                </option>\r\n                <option>\r\n                    <name>IarchiveOutput</name>\r\n                    <state>###Unitialized###</state>\r\n                </option>\r\n            </data>\r\n        </settings>\r\n    </configuration>\r\n    <file>\r\n        <name>$PROJ_DIR$\\..\\main.c</name>\r\n    </file>\r\n    <group>\r\n        <name>CMSIS-Pack</name>\r\n        <tag>CMSISPack.Component</tag>\r\n        <file>\r\n            <name>$PROJ_DIR$\\RTE\\RTE_Components.h</name>\r\n        </file>\r\n        <group>\r\n            <name>CMSIS.RTOS2.Keil RTX5 Source</name>\r\n            <tag>CMSISPack.Component</tag>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/Source/os_systick.c</name>\r\n            </file>\r\n            <file>\r\n                <name>$PROJ_DIR$\\RTE\\CMSIS\\RTX_Config.c</name>\r\n            </file>\r\n            <file>\r\n                <name>$PROJ_DIR$\\RTE\\CMSIS\\RTX_Config.h</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_delay.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_evflags.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_evr.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_kernel.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_lib.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_memory.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_mempool.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_mutex.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_semaphore.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_system.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_thread.c</name>\r\n            </file>\r\n            <file>\r\n                <name>${CMSIS_PACK_PATH_ARM#CMSIS#5.9.1}$\\CMSIS/RTOS2/RTX/Source/rtx_timer.c</name>\r\n            </file>\r\n        </group>\r\n        <group>\r\n            <name>Device Startup</name>\r\n            <tag>CMSISPack.Component</tag>\r\n            <file>\r\n                <name>$PROJ_DIR$\\RTE\\Device\\ARMCM3\\startup_ARMCM3.s</name>\r\n            </file>\r\n            <file>\r\n                <name>$PROJ_DIR$\\RTE\\Device\\ARMCM3\\system_ARMCM3.c</name>\r\n            </file>\r\n        </group>\r\n    </group>\r\n    <cmsisPackSettings>\r\n        <rte>&lt;?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\"?&gt;\r\r\n&lt;configuration xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\"&gt;\r\r\n  &lt;packages/&gt;\r\r\n  &lt;device Dclock=\"10000000\" Dcore=\"Cortex-M3\" DcoreVersion=\"r2p1\" Dendian=\"Little-endian\" Dfamily=\"ARM Cortex M3\" Dfpu=\"NO_FPU\" Dmpu=\"MPU\" Dname=\"ARMCM3\" Dvendor=\"ARM:82\" info=\"ARM , 128 KB RAM, 256 KB ROM\" url=\"http://www.keil.com/dd2/arm/armcm3\"&gt;\r\r\n    &lt;package info=\"CMSIS (Common Microcontroller Software Interface Standard)\" name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n  &lt;/device&gt;\r\r\n  &lt;toolchain Tcompiler=\"IAR\" Toutput=\"exe\"/&gt;\r\r\n  &lt;components&gt;\r\r\n    &lt;component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.7.0\"&gt;\r\r\n      &lt;package name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n      &lt;file category=\"doc\" name=\"CMSIS/Documentation/Core/html/index.html\"/&gt;\r\r\n      &lt;file category=\"include\" name=\"CMSIS/Core/Include/\"/&gt;\r\r\n      &lt;file category=\"header\" condition=\"TrustZone\" name=\"CMSIS/Core/Include/tz_context.h\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"sourceC\" condition=\"TZ Secure\" name=\"CMSIS/Core/Template/ARMv8-M/main_s.c\" select=\"Secure mode 'main' module for ARMv8-M\" version=\"1.1.1\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"sourceC\" condition=\"TZ Secure\" name=\"CMSIS/Core/Template/ARMv8-M/tz_context.c\" select=\"RTOS Context Management (TrustZone for ARMv8-M)\" version=\"1.1.1\"/&gt;\r\r\n    &lt;/component&gt;\r\r\n    &lt;component Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Csub=\"Keil RTX5\" Cvariant=\"Source\" Cvendor=\"ARM\" Cversion=\"5.7.0\"&gt;\r\r\n      &lt;package name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n      &lt;file category=\"doc\" name=\"CMSIS/Documentation/RTOS2/html/rtx5_impl.html\"/&gt;\r\r\n      &lt;file category=\"header\" name=\"CMSIS/RTOS2/RTX/Include/rtx_os.h\"/&gt;\r\r\n      &lt;file attr=\"config\" category=\"header\" name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.h\" version=\"5.6.0\"/&gt;\r\r\n      &lt;file attr=\"config\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Config/RTX_Config.c\" version=\"5.2.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/main.c\" select=\"CMSIS-RTOS2 'main' function\" version=\"2.1.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Events.c\" select=\"CMSIS-RTOS2 Events\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/MemPool.c\" select=\"CMSIS-RTOS2 Memory Pool\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/MsgQueue.c\" select=\"CMSIS-RTOS2 Message Queue\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Mutex.c\" select=\"CMSIS-RTOS2 Mutex\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Semaphore.c\" select=\"CMSIS-RTOS2 Semaphore\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Thread.c\" select=\"CMSIS-RTOS2 Thread\" version=\"2.0.0\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/Timer.c\" select=\"CMSIS-RTOS2 Timer\" version=\"2.0.1\"/&gt;\r\r\n      &lt;file attr=\"template\" category=\"source\" name=\"CMSIS/RTOS2/RTX/Template/svc_user.c\" select=\"CMSIS-RTOS2 SVC User Table\" version=\"1.0.0\"/&gt;\r\r\n      &lt;file category=\"other\" name=\"CMSIS/RTOS2/RTX/RTX5.scvd\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_kernel.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_thread.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_delay.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_timer.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evflags.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mutex.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_semaphore.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_memory.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_mempool.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_system.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_evr.c\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/RTX/Source/rtx_lib.c\"/&gt;\r\r\n      &lt;file category=\"source\" condition=\"IARASM ARMv7-M\" name=\"CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s\"/&gt;\r\r\n      &lt;file category=\"source\" name=\"CMSIS/RTOS2/Source/os_systick.c\"/&gt;\r\r\n    &lt;/component&gt;\r\r\n    &lt;component Cclass=\"Device\" Cgroup=\"Startup\" Cvendor=\"ARM\" Cversion=\"1.2.2\" deviceDependent=\"1\"&gt;\r\r\n      &lt;package name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n      &lt;file category=\"header\" deviceDependent=\"1\" name=\"Device/ARM/ARMCM3/Include/ARMCM3.h\"/&gt;\r\r\n      &lt;file attr=\"config\" category=\"sourceAsm\" condition=\"IAR\" deviceDependent=\"1\" name=\"Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s\" version=\"1.0.0\"/&gt;\r\r\n      &lt;file attr=\"config\" category=\"sourceC\" deviceDependent=\"1\" name=\"Device/ARM/ARMCM3/Source/system_ARMCM3.c\" version=\"1.0.1\"/&gt;\r\r\n    &lt;/component&gt;\r\r\n  &lt;/components&gt;\r\r\n  &lt;apis&gt;\r\r\n    &lt;api Capiversion=\"2.2.0\" Cclass=\"CMSIS\" Cgroup=\"RTOS2\" Cvendor=\"ARM\" Cversion=\"2.2.0\" exclusive=\"1\"&gt;\r\r\n      &lt;package name=\"CMSIS\" url=\"https://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.9.1\"/&gt;\r\r\n      &lt;file category=\"doc\" name=\"CMSIS/Documentation/RTOS2/html/index.html\"/&gt;\r\r\n      &lt;file category=\"header\" name=\"CMSIS/RTOS2/Include/cmsis_os2.h\"/&gt;\r\r\n    &lt;/api&gt;\r\r\n  &lt;/apis&gt;\r\r\n&lt;/configuration&gt;\r\r\n</rte>\r\n    </cmsisPackSettings>\r\n</project>\r\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue/MsgQueue/settings/MsgQueue.crun",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<crun>\n    <version>1</version>\n    <filter_entries>\n        <filter index=\"0\" type=\"default\">\n            <type>*</type>\n            <start_file>*</start_file>\n            <end_file>*</end_file>\n            <action_debugger>0</action_debugger>\n            <action_log>1</action_log>\n        </filter>\n    </filter_entries>\n</crun>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue/MsgQueue/settings/MsgQueue.dbgdt",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<Project>\n    <WindowStorage>\n        <ChildIdMap>\n            <TB_CMSISPACK>34048</TB_CMSISPACK>\n            <TB_DEBUG>34049</TB_DEBUG>\n            <TB_MAIN2>34050</TB_MAIN2>\n            <WIN_AUTO>34051</WIN_AUTO>\n            <WIN_BREAKPOINTS>34052</WIN_BREAKPOINTS>\n            <WIN_BUILD>34053</WIN_BUILD>\n            <WIN_CALL_GRAPH>34054</WIN_CALL_GRAPH>\n            <WIN_CALL_STACK>34055</WIN_CALL_STACK>\n            <WIN_CMSISPACK_AGENT_LOG>34056</WIN_CMSISPACK_AGENT_LOG>\n            <WIN_CODECOVERAGE>34057</WIN_CODECOVERAGE>\n            <WIN_CORES>34058</WIN_CORES>\n            <WIN_CUSTOM_SFR>34059</WIN_CUSTOM_SFR>\n            <WIN_C_STAT>34060</WIN_C_STAT>\n            <WIN_DATA_LOG>34061</WIN_DATA_LOG>\n            <WIN_DATA_STAT>34062</WIN_DATA_STAT>\n            <WIN_DEBUGGER_MACROS>34063</WIN_DEBUGGER_MACROS>\n            <WIN_DEBUG_LOG>34064</WIN_DEBUG_LOG>\n            <WIN_DISASSEMBLY>34065</WIN_DISASSEMBLY>\n            <WIN_EXCEPTION_VIEWER>34066</WIN_EXCEPTION_VIEWER>\n            <WIN_FIND_ALL_DECLARATIONS>34067</WIN_FIND_ALL_DECLARATIONS>\n            <WIN_FIND_ALL_REFERENCES>34068</WIN_FIND_ALL_REFERENCES>\n            <WIN_FIND_IN_FILES>34069</WIN_FIND_IN_FILES>\n            <WIN_FIND_IN_SLIDING_TRACE>34070</WIN_FIND_IN_SLIDING_TRACE>\n            <WIN_IMAGES>34071</WIN_IMAGES>\n            <WIN_INTERRUPT_LOG>34072</WIN_INTERRUPT_LOG>\n            <WIN_INTERRUPT_STAT>34073</WIN_INTERRUPT_STAT>\n            <WIN_LOCALS>34074</WIN_LOCALS>\n            <WIN_MACRO_EVAL>34075</WIN_MACRO_EVAL>\n            <WIN_MACRO_REGISTRATION>34076</WIN_MACRO_REGISTRATION>\n            <WIN_MEMORY_1>34077</WIN_MEMORY_1>\n            <WIN_MEMORY_2>34078</WIN_MEMORY_2>\n            <WIN_MEMORY_3>34079</WIN_MEMORY_3>\n            <WIN_MEMORY_4>34080</WIN_MEMORY_4>\n            <WIN_PHYSICAL_BREAKPOINTS>34081</WIN_PHYSICAL_BREAKPOINTS>\n            <WIN_PROFILING2>34082</WIN_PROFILING2>\n            <WIN_QUICK_WATCH>34083</WIN_QUICK_WATCH>\n            <WIN_REGISTER_1>34084</WIN_REGISTER_1>\n            <WIN_REGISTER_2>34085</WIN_REGISTER_2>\n            <WIN_REGISTER_3>34086</WIN_REGISTER_3>\n            <WIN_REGISTER_4>34087</WIN_REGISTER_4>\n            <WIN_REGISTER_GROUPS>34088</WIN_REGISTER_GROUPS>\n            <WIN_RTOS_MBOX>34089</WIN_RTOS_MBOX>\n            <WIN_RTOS_MEMORYPOOL>34090</WIN_RTOS_MEMORYPOOL>\n            <WIN_RTOS_MUTEX>34091</WIN_RTOS_MUTEX>\n            <WIN_RTOS_QUEUE>34092</WIN_RTOS_QUEUE>\n            <WIN_RTOS_SEMAPHORE>34093</WIN_RTOS_SEMAPHORE>\n            <WIN_RTOS_TASK>34094</WIN_RTOS_TASK>\n            <WIN_RTOS_TIMER>34095</WIN_RTOS_TIMER>\n            <WIN_SELECT_AMBIGUOUS_DEFINITIONS>34096</WIN_SELECT_AMBIGUOUS_DEFINITIONS>\n            <WIN_SLIDING_FUNCTION_TRACE>34097</WIN_SLIDING_FUNCTION_TRACE>\n            <WIN_SLIDING_TRACE_WINDOW>34098</WIN_SLIDING_TRACE_WINDOW>\n            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    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue/MsgQueue/settings/MsgQueue.dnx",
    "content": "<?xml version=\"1.0\"?>\n<settings>\n    <Stack>\n        <FillEnabled>0</FillEnabled>\n        <OverflowWarningsEnabled>1</OverflowWarningsEnabled>\n        <WarningThreshold>90</WarningThreshold>\n        <SpWarningsEnabled>1</SpWarningsEnabled>\n        <WarnLogOnly>1</WarnLogOnly>\n        <UseTrigger>1</UseTrigger>\n        <TriggerName>main</TriggerName>\n        <LimitSize>0</LimitSize>\n        <ByteLimit>50</ByteLimit>\n    </Stack>\n    <Trace1>\n        <Enabled>0</Enabled>\n        <ShowSource>1</ShowSource>\n    </Trace1>\n    <DebugChecksum>\n        <Checksum>2135918346</Checksum>\n    </DebugChecksum>\n    <Disassembly>\n        <InstrCount>0</InstrCount>\n        <MixedMode>1</MixedMode>\n    </Disassembly>\n    <CodeCoverage>\n        <Enabled>0</Enabled>\n        <ShowSource>0</ShowSource>\n        <HideCovered>0</HideCovered>\n    </CodeCoverage>\n    <Exceptions>\n        <StopOnUncaught>_ 0</StopOnUncaught>\n        <StopOnThrow>_ 0</StopOnThrow>\n    </Exceptions>\n    <CallStack>\n        <ShowArgs>0</ShowArgs>\n    </CallStack>\n    <DriverProfiling>\n        <Enabled>0</Enabled>\n        <Mode>1</Mode>\n        <Graph>0</Graph>\n        <Symbiont>0</Symbiont>\n    </DriverProfiling>\n    <CallStackLog>\n        <Enabled>0</Enabled>\n    </CallStackLog>\n    <CallStackStripe>\n        <ShowTiming>1</ShowTiming>\n    </CallStackStripe>\n    <TermIOLog>\n        <LoggingEnabled>_ 0</LoggingEnabled>\n        <LogFile>_ \"\"</LogFile>\n    </TermIOLog>\n    <LogFile>\n        <LoggingEnabled>_ 0</LoggingEnabled>\n        <LogFile>_ \"\"</LogFile>\n        <Category>_ 0</Category>\n    </LogFile>\n    <InterruptLog>\n        <LogEnabled>0</LogEnabled>\n        <GraphEnabled>0</GraphEnabled>\n        <ShowTimeLog>1</ShowTimeLog>\n        <SumEnabled>0</SumEnabled>\n        <ShowTimeSum>1</ShowTimeSum>\n        <SumSortOrder>0</SumSortOrder>\n    </InterruptLog>\n    <DataLog>\n        <LogEnabled>0</LogEnabled>\n        <GraphEnabled>0</GraphEnabled>\n        <ShowTimeLog>1</ShowTimeLog>\n        <SumEnabled>0</SumEnabled>\n        <ShowTimeSum>1</ShowTimeSum>\n    </DataLog>\n    <DisassembleMode>\n        <mode>0</mode>\n    </DisassembleMode>\n    <Breakpoints2>\n        <Count>0</Count>\n    </Breakpoints2>\n    <Interrupts>\n        <Enabled>1</Enabled>\n        <Irq0>_ 0 400000 0 10000 0 0 100 100 0 1 \"SysTick 1 0x3C\"</Irq0>\n        <Count>1</Count>\n    </Interrupts>\n    <MemConfig>\n        <Base>1</Base>\n        <Manual>0</Manual>\n        <Ddf>1</Ddf>\n        <TypeViol>0</TypeViol>\n        <Stop>1</Stop>\n    </MemConfig>\n    <Aliases>\n        <Count>0</Count>\n        <SuppressDialog>0</SuppressDialog>\n    </Aliases>\n    <Simulator>\n        <Freq>10000000</Freq>\n        <FreqHi>0</FreqHi>\n        <MultiCoreRunAll>1</MultiCoreRunAll>\n    </Simulator>\n</settings>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Examples_IAR/MsgQueue/main.c",
    "content": "/* -------------------------------------------------------------------------- \n * Copyright (c) 2013-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    main.c\n *      Purpose: RTX example program\n *\n *---------------------------------------------------------------------------*/\n\n#include <stdio.h>\n\n#include \"RTE_Components.h\"\n#include  CMSIS_device_header\n#include \"cmsis_os2.h\"\n\nvoid app_main (void *argument);\nvoid app_msg (void *argument);\n\ntypedef struct msg_s {\n  uint8_t cmd;\n  uint8_t len;\n  uint8_t data[8];\n} msg_t;\n\nstatic osMessageQueueId_t msgQueue;\n\nstatic const osThreadAttr_t msgAttr = {\n  .stack_size = 400U\n};\n\n/*----------------------------------------------------------------------------\n * Application main thread\n *---------------------------------------------------------------------------*/\n\nvoid app_main (void *argument) {\n  (void)argument;\n\n  osStatus_t status;\n  uint32_t cnt = 0UL;\n  msg_t msg = {\n    .cmd = 1U,\n    .len = 4U,\n    .data = { 0U }\n  };\n\n  while (1) {\n    // Produce a new message and put it to the queue\n    ++cnt;\n    *((uint32_t*)msg.data) = cnt;\n    status = osMessageQueuePut(msgQueue, &msg, 0U, osWaitForever);\n    if (status != osOK) {\n      printf(\"app_main: osMessageQueuePut failed.\\n\");\n    }\n\n    // Defer message creation\n    osDelay(osMessageQueueGetCount(msgQueue)*100U);\n  }\n}\n\n/*----------------------------------------------------------------------------\n * Application message receiver thread\n *---------------------------------------------------------------------------*/\n\nvoid app_msg (void *argument) {\n  (void)argument;\n\n  osStatus_t status;\n  uint32_t cnt;\n  msg_t msg;\n\n  while (1) {\n    // Defer message processing\n    osDelay(osMessageQueueGetSpace(msgQueue)*100U);\n\n    // Wait forever until a message could be received\n    status = osMessageQueueGet(msgQueue, &msg, NULL, osWaitForever);\n    if (status != osOK) {\n      printf(\"app_msg: osMessageQueueGet failed.\\n\");\n    } else {\n      if (msg.len == 4U) {\n        cnt = *((uint32_t*)msg.data);\n      }\n      printf(\"app_msg: received [cmd = %d, data = 0x%0X]\\n\", msg.cmd, cnt);\n    }\n  }\n}\n\n/*----------------------------------------------------------------------------\n * Main entry\n *---------------------------------------------------------------------------*/\n\nint main (void) {\n\n  // System Initialization\n  SystemCoreClockUpdate();\n\n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  osThreadNew(app_msg, NULL, &msgAttr); // Create message receiver thread\n\n  // Create message queue for up to 10 messages of type msg_t\n  msgQueue = osMessageQueueNew(10, sizeof(msg_t), NULL);\n  \n  osKernelStart();                      // Start thread execution\n  for (;;) {}\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Include/rtx_def.h",
    "content": "/*\n * Copyright (c) 2021-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX derived definitions\n *\n * -----------------------------------------------------------------------------\n */\n\n#ifndef RTX_DEF_H_\n#define RTX_DEF_H_\n\n#ifdef   _RTE_\n#include \"RTE_Components.h\"\n#endif\n#include \"RTX_Config.h\"\n\n#if (defined(OS_SAFETY_FEATURES) && (OS_SAFETY_FEATURES != 0))\n #define RTX_SAFETY_FEATURES\n #if (defined(OS_SAFETY_CLASS) && (OS_SAFETY_CLASS != 0))\n  #define RTX_SAFETY_CLASS\n #endif\n #if (defined(OS_EXECUTION_ZONE) && (OS_EXECUTION_ZONE != 0))\n  #define RTX_EXECUTION_ZONE\n #endif\n #if (defined(OS_THREAD_WATCHDOG) && (OS_THREAD_WATCHDOG != 0))\n  #define RTX_THREAD_WATCHDOG\n #endif\n #if (defined(OS_OBJ_PTR_CHECK) && (OS_OBJ_PTR_CHECK != 0))\n  #define RTX_OBJ_PTR_CHECK\n #endif\n #if (defined(OS_SVC_PTR_CHECK) && (OS_SVC_PTR_CHECK != 0))\n  #define RTX_SVC_PTR_CHECK\n #endif\n#endif\n\n#if (defined(OS_OBJ_MEM_USAGE) && (OS_OBJ_MEM_USAGE != 0))\n #define RTX_OBJ_MEM_USAGE\n#endif\n\n#if (defined(OS_STACK_CHECK) && (OS_STACK_CHECK != 0))\n #define RTX_STACK_CHECK\n#endif\n\n#if (defined(OS_TZ_CONTEXT) && (OS_TZ_CONTEXT != 0))\n #define RTX_TZ_CONTEXT\n#endif\n\n#ifndef DOMAIN_NS\n #ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS\n  #define DOMAIN_NS             1\n #else\n  #define DOMAIN_NS             0\n #endif\n#endif\n\n#endif  // RTX_DEF_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Include/rtx_evr.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Event Recorder definitions\n *\n * -----------------------------------------------------------------------------\n */\n\n#ifndef RTX_EVR_H_\n#define RTX_EVR_H_\n\n#include \"rtx_os.h\"                     // RTX OS definitions\n\n// Initial Thread configuration covered also Thread Flags and Generic Wait\n#ifndef   OS_EVR_THFLAGS\n#define   OS_EVR_THFLAGS        OS_EVR_THREAD\n#endif\n#ifndef   OS_EVR_WAIT\n#define   OS_EVR_WAIT           OS_EVR_THREAD\n#endif\n\n#ifdef   _RTE_\n#include \"RTE_Components.h\"\n#endif\n\n#ifdef    RTE_Compiler_EventRecorder\n\n//lint -emacro((835,845),EventID) [MISRA Note 13]\n\n#include \"EventRecorder.h\"\n#include \"EventRecorderConf.h\"\n\n#if ((defined(OS_EVR_INIT) && (OS_EVR_INIT != 0)) || (EVENT_TIMESTAMP_SOURCE == 2))\n#ifndef EVR_RTX_KERNEL_GET_STATE_DISABLE\n#define EVR_RTX_KERNEL_GET_STATE_DISABLE\n#endif\n#endif\n\n#if (EVENT_TIMESTAMP_SOURCE == 2)\n#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE\n#define EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE\n#endif\n#ifndef EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE\n#define EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE\n#endif\n#endif\n\n/// RTOS component number\n#define EvtRtxMemoryNo                  (0xF0U)\n#define EvtRtxKernelNo                  (0xF1U)\n#define EvtRtxThreadNo                  (0xF2U)\n#define EvtRtxThreadFlagsNo             (0xF4U)\n#define EvtRtxWaitNo                    (0xF3U)\n#define EvtRtxTimerNo                   (0xF6U)\n#define EvtRtxEventFlagsNo              (0xF5U)\n#define EvtRtxMutexNo                   (0xF7U)\n#define EvtRtxSemaphoreNo               (0xF8U)\n#define EvtRtxMemoryPoolNo              (0xF9U)\n#define EvtRtxMessageQueueNo            (0xFAU)\n\n#endif  // RTE_Compiler_EventRecorder\n\n\n/// Extended Status codes\n#define osRtxErrorKernelNotReady        (-8)\n#define osRtxErrorKernelNotRunning      (-9)\n#define osRtxErrorInvalidControlBlock   (-10)\n#define osRtxErrorInvalidDataMemory     (-11)\n#define osRtxErrorInvalidThreadStack    (-12)\n#define osRtxErrorInvalidPriority       (-13)\n#define osRtxErrorInvalidPrivilegedMode (-14)\n#define osRtxErrorThreadNotJoinable     (-15)\n#define osRtxErrorMutexNotOwned         (-16)\n#define osRtxErrorMutexNotLocked        (-17)\n#define osRtxErrorMutexLockLimit        (-18)\n#define osRtxErrorSemaphoreCountLimit   (-19)\n#define osRtxErrorTZ_InitContext_S      (-20)\n#define osRtxErrorTZ_AllocContext_S     (-21)\n#define osRtxErrorTZ_FreeContext_S      (-22)\n#define osRtxErrorTZ_LoadContext_S      (-23)\n#define osRtxErrorTZ_SaveContext_S      (-24)\n\n\n//  ==== Memory Events ====\n\n/**\n  \\brief  Event on memory initialization (Op)\n  \\param[in]  mem           pointer to memory pool.\n  \\param[in]  size          size of a memory pool in bytes.\n  \\param[in]  result        execution status: 1 - success, 0 - failure.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE))\nextern void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result);\n#else\n#define EvrRtxMemoryInit(mem, size, result)\n#endif\n\n/**\n  \\brief  Event on memory allocate (Op)\n  \\param[in]  mem           pointer to memory pool.\n  \\param[in]  size          size of a memory block in bytes.\n  \\param[in]  type          memory block type: 0 - generic, 1 - control block.\n  \\param[in]  block         pointer to allocated memory block or NULL in case of no memory is available.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE))\nextern void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block);\n#else\n#define EvrRtxMemoryAlloc(mem, size, type, block)\n#endif\n\n/**\n  \\brief  Event on memory free (Op)\n  \\param[in]  mem           pointer to memory pool.\n  \\param[in]  block         memory block to be returned to the memory pool.\n  \\param[in]  result        execution status: 1 - success, 0 - failure.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE))\nextern void EvrRtxMemoryFree (void *mem, void *block, uint32_t result);\n#else\n#define EvrRtxMemoryFree(mem, block, result)\n#endif\n\n/**\n  \\brief  Event on memory block initialization (Op)\n  \\param[in]  mp_info       memory pool info.\n  \\param[in]  block_count   maximum number of memory blocks in memory pool.\n  \\param[in]  block_size    size of a memory block in bytes.\n  \\param[in]  block_mem     pointer to memory for block storage.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE))\nextern void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem);\n#else\n#define EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem)\n#endif\n\n/**\n  \\brief  Event on memory block alloc (Op)\n  \\param[in]  mp_info       memory pool info.\n  \\param[in]  block         address of the allocated memory block or NULL in case of no memory is available.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE))\nextern void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block);\n#else\n#define EvrRtxMemoryBlockAlloc(mp_info, block)\n#endif\n\n/**\n  \\brief  Event on memory block free (Op)\n  \\param[in]  mp_info       memory pool info.\n  \\param[in]  block         address of the allocated memory block to be returned to the memory pool.\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE))\nextern void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status);\n#else\n#define EvrRtxMemoryBlockFree(mp_info, block, status)\n#endif\n\n\n//  ==== Kernel Events ====\n\n/**\n  \\brief  Event on RTOS kernel error (Error)\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE))\nextern void EvrRtxKernelError (int32_t status);\n#else\n#define EvrRtxKernelError(status)\n#endif\n\n/**\n  \\brief  Event on RTOS kernel initialize (API)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE))\nextern void EvrRtxKernelInitialize (void);\n#else\n#define EvrRtxKernelInitialize()\n#endif\n\n/**\n  \\brief  Event on successful RTOS kernel initialize (Op)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZED_DISABLE))\nextern void EvrRtxKernelInitialized (void);\n#else\n#define EvrRtxKernelInitialized()\n#endif\n\n/**\n  \\brief  Event on RTOS kernel information retrieve (API)\n  \\param[in]  version       pointer to buffer for retrieving version information.\n  \\param[in]  id_buf        pointer to buffer for retrieving kernel identification string.\n  \\param[in]  id_size       size of buffer for kernel identification string.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE))\nextern void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);\n#else\n#define EvrRtxKernelGetInfo(version, id_buf, id_size)\n#endif\n\n/**\n  \\brief  Event on successful RTOS kernel information retrieve (Op)\n  \\param[in]  version       pointer to buffer for retrieving version information.\n  \\param[in]  id_buf        pointer to buffer for retrieving kernel identification string.\n  \\param[in]  id_size       size of buffer for kernel identification string.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE))\nextern void EvrRtxKernelInfoRetrieved (const osVersion_t *version, const char *id_buf, uint32_t id_size);\n#else\n#define EvrRtxKernelInfoRetrieved(version, id_buf, id_size)\n#endif\n\n/**\n  \\brief  Event on current RTOS Kernel state retrieve (API)\n  \\param[in]  state         current RTOS Kernel state.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE))\nextern void EvrRtxKernelGetState (osKernelState_t state);\n#else\n#define EvrRtxKernelGetState(state)\n#endif\n\n/**\n  \\brief  Event on RTOS Kernel scheduler start (API)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE))\nextern void EvrRtxKernelStart (void);\n#else\n#define EvrRtxKernelStart()\n#endif\n\n/**\n  \\brief  Event on successful RTOS Kernel scheduler start (Op)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE))\nextern void EvrRtxKernelStarted (void);\n#else\n#define EvrRtxKernelStarted()\n#endif\n\n/**\n  \\brief  Event on RTOS Kernel scheduler lock (API)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE))\nextern void EvrRtxKernelLock (void);\n#else\n#define EvrRtxKernelLock()\n#endif\n\n/**\n  \\brief  Event on successful RTOS Kernel scheduler lock (Op)\n  \\param[in]  lock          previous lock state (1 - locked, 0 - not locked).\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE))\nextern void EvrRtxKernelLocked (int32_t lock);\n#else\n#define EvrRtxKernelLocked(lock)\n#endif\n\n/**\n  \\brief  Event on RTOS Kernel scheduler unlock (API)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE))\nextern void EvrRtxKernelUnlock (void);\n#else\n#define EvrRtxKernelUnlock()\n#endif\n\n/**\n  \\brief  Event on successful RTOS Kernel scheduler unlock (Op)\n  \\param[in]  lock          previous lock state (1 - locked, 0 - not locked).\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE))\nextern void EvrRtxKernelUnlocked (int32_t lock);\n#else\n#define EvrRtxKernelUnlocked(lock)\n#endif\n\n/**\n  \\brief  Event on RTOS Kernel scheduler lock state restore (API)\n  \\param[in]  lock          lock state obtained by \\ref osKernelLock or \\ref osKernelUnlock.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE))\nextern void EvrRtxKernelRestoreLock (int32_t lock);\n#else\n#define EvrRtxKernelRestoreLock(lock)\n#endif\n\n/**\n  \\brief  Event on successful RTOS Kernel scheduler lock state restore (Op)\n  \\param[in]  lock          new lock state (1 - locked, 0 - not locked).\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE))\nextern void EvrRtxKernelLockRestored (int32_t lock);\n#else\n#define EvrRtxKernelLockRestored(lock)\n#endif\n\n/**\n  \\brief  Event on RTOS Kernel scheduler suspend (API)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE))\nextern void EvrRtxKernelSuspend (void);\n#else\n#define EvrRtxKernelSuspend()\n#endif\n\n/**\n  \\brief  Event on successful RTOS Kernel scheduler suspend (Op)\n  \\param[in]  sleep_ticks   time in ticks, for how long the system can sleep or power-down.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE))\nextern void EvrRtxKernelSuspended (uint32_t sleep_ticks);\n#else\n#define EvrRtxKernelSuspended(sleep_ticks)\n#endif\n\n/**\n  \\brief  Event on RTOS Kernel scheduler resume (API)\n  \\param[in]  sleep_ticks   time in ticks, for how long the system was in sleep or power-down mode.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE))\nextern void EvrRtxKernelResume (uint32_t sleep_ticks);\n#else\n#define EvrRtxKernelResume(sleep_ticks)\n#endif\n\n/**\n  \\brief  Event on successful RTOS Kernel scheduler resume (Op)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE))\nextern void EvrRtxKernelResumed (void);\n#else\n#define EvrRtxKernelResumed()\n#endif\n\n/**\n  \\brief  Event on protect the RTOS Kernel scheduler access (API)\n  \\param[in]  safety_class  safety class.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_PROTECT_DISABLE))\nextern void EvrRtxKernelProtect (uint32_t safety_class);\n#else\n#define EvrRtxKernelProtect(safety_class)\n#endif\n\n/**\n  \\brief  Event on successful RTOS Kernel scheduler protect (API)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_PROTECTED_DISABLE))\nextern void EvrRtxKernelProtected (void);\n#else\n#define EvrRtxKernelProtected()\n#endif\n\n/**\n  \\brief  Event on RTOS kernel tick count retrieve (API)\n  \\param[in]  count         RTOS kernel current tick count.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE))\nextern void EvrRtxKernelGetTickCount (uint32_t count);\n#else\n#define EvrRtxKernelGetTickCount(count)\n#endif\n\n/**\n  \\brief  Event on RTOS kernel tick frequency retrieve (API)\n  \\param[in]  freq          frequency of the kernel tick.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE))\nextern void EvrRtxKernelGetTickFreq (uint32_t freq);\n#else\n#define EvrRtxKernelGetTickFreq(freq)\n#endif\n\n/**\n  \\brief  Event on RTOS kernel system timer count retrieve (API)\n  \\param[in]  count         RTOS kernel current system timer count as 32-bit value.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE))\nextern void EvrRtxKernelGetSysTimerCount (uint32_t count);\n#else\n#define EvrRtxKernelGetSysTimerCount(count)\n#endif\n\n/**\n  \\brief  Event on RTOS kernel system timer frequency retrieve (API)\n  \\param[in]  freq          frequency of the system timer.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE))\nextern void EvrRtxKernelGetSysTimerFreq (uint32_t freq);\n#else\n#define EvrRtxKernelGetSysTimerFreq(freq)\n#endif\n\n/**\n  \\brief  Event on RTOS kernel system error (Error)\n  \\param[in]  code          error code.\n  \\param[in]  object_id     object that caused the error.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_NOTIFY_DISABLE))\nextern void EvrRtxKernelErrorNotify (uint32_t code, void *object_id);\n#else\n#define EvrRtxKernelErrorNotify(code, object_id)\n#endif\n\n/**\n  \\brief  Event on destroy safety class objects (API)\n  \\param[in]  safety_class  safety class.\n  \\param[in]  mode          safety mode.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_DESTROY_CLASS_DISABLE))\nextern void EvrRtxKernelDestroyClass (uint32_t safety_class, uint32_t mode);\n#else\n#define EvrRtxKernelDestroyClass(safety_class, mode)\n#endif\n\n\n//  ==== Thread Events ====\n\n/**\n  \\brief  Event on thread error (Error)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId or NULL when ID is unknown.\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE))\nextern void EvrRtxThreadError (osThreadId_t thread_id, int32_t status);\n#else\n#define EvrRtxThreadError(thread_id, status)\n#endif\n\n/**\n  \\brief  Event on thread create and intialize (API)\n  \\param[in]  func          thread function.\n  \\param[in]  argument      pointer that is passed to the thread function as start argument.\n  \\param[in]  attr          thread attributes.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE))\nextern void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);\n#else\n#define EvrRtxThreadNew(func, argument, attr)\n#endif\n\n/**\n  \\brief  Event on successful thread create (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  thread_addr   thread entry address.\n  \\param[in]  name          pointer to thread object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE))\nextern void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name);\n#else\n#define EvrRtxThreadCreated(thread_id, thread_addr, name)\n#endif\n\n/**\n  \\brief  Event on thread name retrieve (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  name          pointer to thread object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE))\nextern void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name);\n#else\n#define EvrRtxThreadGetName(thread_id, name)\n#endif\n\n/**\n  \\brief  Event on thread safety class retrieve (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  safety_class  thread safety class.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_CLASS_DISABLE))\nextern void EvrRtxThreadGetClass (osThreadId_t thread_id, uint32_t safety_class);\n#else\n#define EvrRtxThreadGetClass(thread_id, safety_class)\n#endif\n\n/**\n  \\brief  Event on thread zone retrieve (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  zone          thread zone.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ZONE_DISABLE))\nextern void EvrRtxThreadGetZone (osThreadId_t thread_id, uint32_t zone);\n#else\n#define EvrRtxThreadGetZone(thread_id, zone)\n#endif\n\n/**\n  \\brief  Event on current running thread ID retrieve (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE))\nextern void EvrRtxThreadGetId (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadGetId(thread_id)\n#endif\n\n/**\n  \\brief  Event on thread state retrieve (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  state         current thread state of the specified thread.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE))\nextern void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state);\n#else\n#define EvrRtxThreadGetState(thread_id, state)\n#endif\n\n/**\n  \\brief  Event on thread stack size retrieve (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  stack_size    stack size in bytes.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE))\nextern void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size);\n#else\n#define EvrRtxThreadGetStackSize(thread_id, stack_size)\n#endif\n\n/**\n  \\brief  Event on available stack space retrieve (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  stack_space   remaining stack space in bytes.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE))\nextern void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space);\n#else\n#define EvrRtxThreadGetStackSpace(thread_id, stack_space)\n#endif\n\n/**\n  \\brief  Event on thread priority set (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  priority      new priority value for the thread function.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE))\nextern void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);\n#else\n#define EvrRtxThreadSetPriority(thread_id, priority)\n#endif\n\n/**\n  \\brief  Event on thread priority updated (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  priority      new priority value for the thread function.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIORITY_UPDATED_DISABLE))\nextern void EvrRtxThreadPriorityUpdated (osThreadId_t thread_id, osPriority_t priority);\n#else\n#define EvrRtxThreadPriorityUpdated(thread_id, priority)\n#endif\n\n/**\n  \\brief  Event on thread priority retrieve (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  priority      current priority value of the specified thread.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE))\nextern void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority);\n#else\n#define EvrRtxThreadGetPriority(thread_id, priority)\n#endif\n\n/**\n  \\brief  Event on thread yield (API)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE))\nextern void EvrRtxThreadYield (void);\n#else\n#define EvrRtxThreadYield()\n#endif\n\n/**\n  \\brief  Event on thread suspend (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE))\nextern void EvrRtxThreadSuspend (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadSuspend(thread_id)\n#endif\n\n/**\n  \\brief  Event on successful thread suspend (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE))\nextern void EvrRtxThreadSuspended (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadSuspended(thread_id)\n#endif\n\n/**\n  \\brief  Event on thread resume (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE))\nextern void EvrRtxThreadResume (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadResume(thread_id)\n#endif\n\n/**\n  \\brief  Event on successful thread resume (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE))\nextern void EvrRtxThreadResumed (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadResumed(thread_id)\n#endif\n\n/**\n  \\brief  Event on thread detach (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE))\nextern void EvrRtxThreadDetach (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadDetach(thread_id)\n#endif\n\n/**\n  \\brief  Event on successful thread detach (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE))\nextern void EvrRtxThreadDetached (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadDetached(thread_id)\n#endif\n\n/**\n  \\brief  Event on thread join (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE))\nextern void EvrRtxThreadJoin (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadJoin(thread_id)\n#endif\n\n/**\n  \\brief  Event on pending thread join (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE))\nextern void EvrRtxThreadJoinPending (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadJoinPending(thread_id)\n#endif\n\n/**\n  \\brief  Event on successful thread join (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE))\nextern void EvrRtxThreadJoined (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadJoined(thread_id)\n#endif\n\n/**\n  \\brief  Event on thread execution block (Detail)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE))\nextern void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout);\n#else\n#define EvrRtxThreadBlocked(thread_id, timeout)\n#endif\n\n/**\n  \\brief  Event on thread execution unblock (Detail)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  ret_val       extended execution status of the thread.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE))\nextern void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val);\n#else\n#define EvrRtxThreadUnblocked(thread_id, ret_val)\n#endif\n\n/**\n  \\brief  Event on running thread pre-emption (Detail)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PREEMPTED_DISABLE))\nextern void EvrRtxThreadPreempted (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadPreempted(thread_id)\n#endif\n\n/**\n  \\brief  Event on running thread switch (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCHED_DISABLE))\nextern void EvrRtxThreadSwitched (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadSwitched(thread_id)\n#endif\n\n/**\n  \\brief  Event on thread exit (API)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE))\nextern void EvrRtxThreadExit (void);\n#else\n#define EvrRtxThreadExit()\n#endif\n\n/**\n  \\brief  Event on thread terminate (API)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE))\nextern void EvrRtxThreadTerminate (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadTerminate(thread_id)\n#endif\n\n/**\n  \\brief  Event on successful thread terminate (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE))\nextern void EvrRtxThreadDestroyed (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadDestroyed(thread_id)\n#endif\n\n/**\n  \\brief  Event on thread feed watchdog (API)\n  \\param[in]  ticks         timeout in number of ticks.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FEED_WATCHDOG_DISABLE))\nextern void EvrRtxThreadFeedWatchdog (uint32_t ticks);\n#else\n#define EvrRtxThreadFeedWatchdog(ticks)\n#endif\n\n/**\n  \\brief  Event on thread feed watchdog done (Op)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FEED_WATCHDOG_DONE_DISABLE))\nextern void EvrRtxThreadFeedWatchdogDone (void);\n#else\n#define EvrRtxThreadFeedWatchdogDone()\n#endif\n\n/**\n  \\brief  Event on protect the creation of privileged threads (API)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PROTECT_PRIVILEGED_DISABLE))\nextern void EvrRtxThreadProtectPrivileged (void);\n#else\n#define EvrRtxThreadProtectPrivileged()\n#endif\n\n/**\n  \\brief  Event on successful protect the creation of privileged threads (Op)\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIVILEGED_PROTECTED_DISABLE))\nextern void EvrRtxThreadPrivilegedProtected (void);\n#else\n#define EvrRtxThreadPrivilegedProtected()\n#endif\n\n/**\n  \\brief  Event on active thread count retrieve (API)\n  \\param[in]  count         number of active threads.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE))\nextern void EvrRtxThreadGetCount (uint32_t count);\n#else\n#define EvrRtxThreadGetCount(count)\n#endif\n\n/**\n  \\brief  Event on active threads enumerate (API)\n  \\param[in]  thread_array  pointer to array for retrieving thread IDs.\n  \\param[in]  array_items   maximum number of items in array for retrieving thread IDs.\n  \\param[in]  count         number of enumerated threads.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE))\nextern void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count);\n#else\n#define EvrRtxThreadEnumerate(thread_array, array_items, count)\n#endif\n\n/**\n  \\brief  Event on thread safety class suspend (API)\n  \\param[in]  safety_class  safety class.\n  \\param[in]  mode          safety mode.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_CLASS_DISABLE))\nextern void EvrRtxThreadSuspendClass (uint32_t safety_class, uint32_t mode);\n#else\n#define EvrRtxThreadSuspendClass(safety_class, mode)\n#endif\n\n/**\n  \\brief  Event on thread safety class resume (API)\n  \\param[in]  safety_class  safety class.\n  \\param[in]  mode          safety mode.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_CLASS_DISABLE))\nextern void EvrRtxThreadResumeClass (uint32_t safety_class, uint32_t mode);\n#else\n#define EvrRtxThreadResumeClass(safety_class, mode)\n#endif\n\n/**\n  \\brief  Event on thread zone terminate (API)\n  \\param[in]  zone          thread zone.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_ZONE_DISABLE))\nextern void EvrRtxThreadTerminateZone (uint32_t zone);\n#else\n#define EvrRtxThreadTerminateZone(zone)\n#endif\n\n/**\n  \\brief  Event on thread watchdog expired (Error)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_WATCHDOG_EXPIRED_DISABLE))\nextern void EvrRtxThreadWatchdogExpired (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadWatchdogExpired(thread_id)\n#endif\n\n\n//  ==== Thread Flags Events ====\n\n/**\n  \\brief  Event on thread flags error (Error)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId or NULL when ID is unknown.\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_ERROR_DISABLE))\nextern void EvrRtxThreadFlagsError (osThreadId_t thread_id, int32_t status);\n#else\n#define EvrRtxThreadFlagsError(thread_id, status)\n#endif\n\n/**\n  \\brief  Event on thread flags set (API)\n  \\param[in]   thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]   flags         flags of the thread that shall be set.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE))\nextern void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);\n#else\n#define EvrRtxThreadFlagsSet(thread_id, flags)\n#endif\n\n/**\n  \\brief  Event on successful thread flags set (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n  \\param[in]  thread_flags  thread flags after setting.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE))\nextern void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags);\n#else\n#define EvrRtxThreadFlagsSetDone(thread_id, thread_flags)\n#endif\n\n/**\n  \\brief  Event on thread flags clear (API)\n  \\param[in]  flags         flags of the thread that shall be cleared.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE))\nextern void EvrRtxThreadFlagsClear (uint32_t flags);\n#else\n#define EvrRtxThreadFlagsClear(flags)\n#endif\n\n/**\n  \\brief  Event on successful thread flags clear (Op)\n  \\param[in]  thread_flags  thread flags before clearing.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE))\nextern void EvrRtxThreadFlagsClearDone (uint32_t thread_flags);\n#else\n#define EvrRtxThreadFlagsClearDone(thread_flags)\n#endif\n\n/**\n  \\brief  Event on thread flags retrieve (API)\n  \\param[in]  thread_flags  current thread flags.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE))\nextern void EvrRtxThreadFlagsGet (uint32_t thread_flags);\n#else\n#define EvrRtxThreadFlagsGet(thread_flags)\n#endif\n\n/**\n  \\brief  Event on wait for thread flags (API)\n  \\param[in]  flags         flags to wait for.\n  \\param[in]  options       flags options (osFlagsXxxx).\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE))\nextern void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);\n#else\n#define EvrRtxThreadFlagsWait(flags, options, timeout)\n#endif\n\n/**\n  \\brief  Event on pending wait for thread flags (Op)\n  \\param[in]  flags         flags to wait for.\n  \\param[in]  options       flags options (osFlagsXxxx).\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE))\nextern void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout);\n#else\n#define EvrRtxThreadFlagsWaitPending(flags, options, timeout)\n#endif\n\n/**\n  \\brief  Event on wait timeout for thread flags (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE))\nextern void EvrRtxThreadFlagsWaitTimeout (osThreadId_t thread_id);\n#else\n#define EvrRtxThreadFlagsWaitTimeout(thread_id)\n#endif\n\n/**\n  \\brief  Event on successful wait for thread flags (Op)\n  \\param[in]  flags         flags to wait for.\n  \\param[in]  options       flags options (osFlagsXxxx).\n  \\param[in]  thread_flags  thread flags before clearing.\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE))\nextern void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags, osThreadId_t thread_id);\n#else\n#define EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags, thread_id)\n#endif\n\n/**\n  \\brief  Event on unsuccessful wait for thread flags (Op)\n  \\param[in]  flags         flags to wait for.\n  \\param[in]  options       flags options (osFlagsXxxx).\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE))\nextern void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options);\n#else\n#define EvrRtxThreadFlagsWaitNotCompleted(flags, options)\n#endif\n\n\n//  ==== Generic Wait Events ====\n\n/**\n  \\brief  Event on delay error (Error)\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_ERROR_DISABLE))\nextern void EvrRtxDelayError (int32_t status);\n#else\n#define EvrRtxDelayError(status)\n#endif\n\n/**\n  \\brief  Event on delay for specified time (API)\n  \\param[in]  ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_DISABLE))\nextern void EvrRtxDelay (uint32_t ticks);\n#else\n#define EvrRtxDelay(ticks)\n#endif\n\n/**\n  \\brief  Event on delay until specified time (API)\n  \\param[in]  ticks         absolute time in ticks.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_DISABLE))\nextern void EvrRtxDelayUntil (uint32_t ticks);\n#else\n#define EvrRtxDelayUntil(ticks)\n#endif\n\n/**\n  \\brief  Event on delay started (Op)\n  \\param[in]  ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_STARTED_DISABLE))\nextern void EvrRtxDelayStarted (uint32_t ticks);\n#else\n#define EvrRtxDelayStarted(ticks)\n#endif\n\n/**\n  \\brief  Event on delay until specified time started (Op)\n  \\param[in]  ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_STARTED_DISABLE))\nextern void EvrRtxDelayUntilStarted (uint32_t ticks);\n#else\n#define EvrRtxDelayUntilStarted(ticks)\n#endif\n\n/**\n  \\brief  Event on delay completed (Op)\n  \\param[in]  thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_COMPLETED_DISABLE))\nextern void EvrRtxDelayCompleted (osThreadId_t thread_id);\n#else\n#define EvrRtxDelayCompleted(thread_id)\n#endif\n\n\n//  ==== Timer Events ====\n\n/**\n  \\brief  Event on timer error (Error)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew or NULL when ID is unknown.\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE))\nextern void EvrRtxTimerError (osTimerId_t timer_id, int32_t status);\n#else\n#define EvrRtxTimerError(timer_id, status)\n#endif\n\n/**\n  \\brief  Event on timer callback call (Op)\n  \\param[in]  func          start address of a timer call back function.\n  \\param[in]  argument      argument to the timer call back function.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE))\nextern void EvrRtxTimerCallback (osTimerFunc_t func, void *argument);\n#else\n#define EvrRtxTimerCallback(func, argument)\n#endif\n\n/**\n  \\brief  Event on timer create and initialize (API)\n  \\param[in]  func          start address of a timer call back function.\n  \\param[in]  type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n  \\param[in]  argument      argument to the timer call back function.\n  \\param[in]  attr          timer attributes.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE))\nextern void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);\n#else\n#define EvrRtxTimerNew(func, type, argument, attr)\n#endif\n\n/**\n  \\brief  Event on successful timer create (Op)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew.\n  \\param[in]  name          pointer to timer object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE))\nextern void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name);\n#else\n#define EvrRtxTimerCreated(timer_id, name)\n#endif\n\n/**\n  \\brief  Event on timer name retrieve (API)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew.\n  \\param[in]  name          pointer to timer object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE))\nextern void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name);\n#else\n#define EvrRtxTimerGetName(timer_id, name)\n#endif\n\n/**\n  \\brief  Event on timer start (API)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew.\n  \\param[in]  ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value of the timer.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE))\nextern void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks);\n#else\n#define EvrRtxTimerStart(timer_id, ticks)\n#endif\n\n/**\n  \\brief  Event on successful timer start (Op)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE))\nextern void EvrRtxTimerStarted (osTimerId_t timer_id);\n#else\n#define EvrRtxTimerStarted(timer_id)\n#endif\n\n/**\n  \\brief  Event on timer stop (API)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE))\nextern void EvrRtxTimerStop (osTimerId_t timer_id);\n#else\n#define EvrRtxTimerStop(timer_id)\n#endif\n\n/**\n  \\brief  Event on successful timer stop (Op)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE))\nextern void EvrRtxTimerStopped (osTimerId_t timer_id);\n#else\n#define EvrRtxTimerStopped(timer_id)\n#endif\n\n/**\n  \\brief  Event on timer running state check (API)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew.\n  \\param[in]  running       running state: 0 not running, 1 running.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE))\nextern void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running);\n#else\n#define EvrRtxTimerIsRunning(timer_id, running)\n#endif\n\n/**\n  \\brief  Event on timer delete (API)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE))\nextern void EvrRtxTimerDelete (osTimerId_t timer_id);\n#else\n#define EvrRtxTimerDelete(timer_id)\n#endif\n\n/**\n  \\brief  Event on successful timer delete (Op)\n  \\param[in]  timer_id      timer ID obtained by \\ref osTimerNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE))\nextern void EvrRtxTimerDestroyed (osTimerId_t timer_id);\n#else\n#define EvrRtxTimerDestroyed(timer_id)\n#endif\n\n\n//  ==== Event Flags Events ====\n\n/**\n  \\brief  Event on event flags error (Error)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew or NULL when ID is unknown.\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE))\nextern void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status);\n#else\n#define EvrRtxEventFlagsError(ef_id, status)\n#endif\n\n/**\n  \\brief  Event on event flags create and initialize (API)\n  \\param[in]  attr          event flags attributes.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE))\nextern void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr);\n#else\n#define EvrRtxEventFlagsNew(attr)\n#endif\n\n/**\n  \\brief  Event on successful event flags create (Op)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  name          pointer to event flags object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE))\nextern void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name);\n#else\n#define EvrRtxEventFlagsCreated(ef_id, name)\n#endif\n\n/**\n  \\brief  Event on event flags name retrieve (API)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  name          pointer to event flags object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE))\nextern void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name);\n#else\n#define EvrRtxEventFlagsGetName(ef_id, name)\n#endif\n\n/**\n  \\brief  Event on event flags set (API)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  flags         flags that shall be set.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE))\nextern void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);\n#else\n#define EvrRtxEventFlagsSet(ef_id, flags)\n#endif\n\n/**\n  \\brief  Event on successful event flags set (Op)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  event_flags   event flags after setting.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE))\nextern void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags);\n#else\n#define EvrRtxEventFlagsSetDone(ef_id, event_flags)\n#endif\n\n/**\n  \\brief  Event on event flags clear (API)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  flags         flags that shall be cleared.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE))\nextern void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);\n#else\n#define EvrRtxEventFlagsClear(ef_id, flags)\n#endif\n\n/**\n  \\brief  Event on successful event flags clear (Op)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  event_flags   event flags before clearing.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE))\nextern void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags);\n#else\n#define EvrRtxEventFlagsClearDone(ef_id, event_flags)\n#endif\n\n/**\n  \\brief  Event on event flags retrieve (API)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  event_flags   current event flags.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE))\nextern void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags);\n#else\n#define EvrRtxEventFlagsGet(ef_id, event_flags)\n#endif\n\n/**\n  \\brief  Event on wait for event flags (API)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  flags         flags to wait for.\n  \\param[in]  options       flags options (osFlagsXxxx).\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE))\nextern void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);\n#else\n#define EvrRtxEventFlagsWait(ef_id, flags, options, timeout)\n#endif\n\n/**\n  \\brief  Event on pending wait for event flags (Op)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  flags         flags to wait for.\n  \\param[in]  options       flags options (osFlagsXxxx).\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE))\nextern void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);\n#else\n#define EvrRtxEventFlagsWaitPending(ef_id, flags, options, timeout)\n#endif\n\n/**\n  \\brief  Event on wait timeout for event flags (Op)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE))\nextern void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id);\n#else\n#define EvrRtxEventFlagsWaitTimeout(ef_id)\n#endif\n\n/**\n  \\brief  Event on successful wait for event flags (Op)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  flags         flags to wait for.\n  \\param[in]  options       flags options (osFlagsXxxx).\n  \\param[in]  event_flags   event flags before clearing or 0 if specified flags have not been set.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE))\nextern void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags);\n#else\n#define EvrRtxEventFlagsWaitCompleted(ef_id, flags, options, event_flags)\n#endif\n\n/**\n  \\brief  Event on unsuccessful wait for event flags (Op)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n  \\param[in]  flags         flags to wait for.\n  \\param[in]  options       flags options (osFlagsXxxx).\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE))\nextern void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options);\n#else\n#define EvrRtxEventFlagsWaitNotCompleted(ef_id, flags, options)\n#endif\n\n/**\n  \\brief  Event on event flags delete (API)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE))\nextern void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id);\n#else\n#define EvrRtxEventFlagsDelete(ef_id)\n#endif\n\n/**\n  \\brief  Event on successful event flags delete (Op)\n  \\param[in]  ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE))\nextern void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id);\n#else\n#define EvrRtxEventFlagsDestroyed(ef_id)\n#endif\n\n\n//  ==== Mutex Events ====\n\n/**\n  \\brief  Event on mutex error (Error)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew or NULL when ID is unknown.\n  \\param[in]  status    extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE))\nextern void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status);\n#else\n#define EvrRtxMutexError(mutex_id, status)\n#endif\n\n/**\n  \\brief  Event on mutex create and initialize (API)\n  \\param[in]  attr      mutex attributes.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE))\nextern void EvrRtxMutexNew (const osMutexAttr_t *attr);\n#else\n#define EvrRtxMutexNew(attr)\n#endif\n\n/**\n  \\brief  Event on successful mutex create (Op)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n  \\param[in]  name      pointer to mutex object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE))\nextern void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name);\n#else\n#define EvrRtxMutexCreated(mutex_id, name)\n#endif\n\n/**\n  \\brief  Event on mutex name retrieve (API)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n  \\param[in]  name      pointer to mutex object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE))\nextern void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name);\n#else\n#define EvrRtxMutexGetName(mutex_id, name)\n#endif\n\n/**\n  \\brief  Event on mutex acquire (API)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n  \\param[in]  timeout   \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE))\nextern void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);\n#else\n#define EvrRtxMutexAcquire(mutex_id, timeout)\n#endif\n\n/**\n  \\brief  Event on pending mutex acquire (Op)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n  \\param[in]  timeout   \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE))\nextern void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout);\n#else\n#define EvrRtxMutexAcquirePending(mutex_id, timeout)\n#endif\n\n/**\n  \\brief  Event on mutex acquire timeout (Op)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE))\nextern void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id);\n#else\n#define EvrRtxMutexAcquireTimeout(mutex_id)\n#endif\n\n/**\n  \\brief  Event on successful mutex acquire (Op)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n  \\param[in]  lock      current number of times mutex object is locked.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE))\nextern void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock);\n#else\n#define EvrRtxMutexAcquired(mutex_id, lock)\n#endif\n\n/**\n  \\brief  Event on unsuccessful mutex acquire (Op)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE))\nextern void EvrRtxMutexNotAcquired (osMutexId_t mutex_id);\n#else\n#define EvrRtxMutexNotAcquired(mutex_id)\n#endif\n\n/**\n  \\brief  Event on mutex release (API)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE))\nextern void EvrRtxMutexRelease (osMutexId_t mutex_id);\n#else\n#define EvrRtxMutexRelease(mutex_id)\n#endif\n\n/**\n  \\brief  Event on successful mutex release (Op)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n  \\param[in]  lock      current number of times mutex object is locked.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE))\nextern void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock);\n#else\n#define EvrRtxMutexReleased(mutex_id, lock)\n#endif\n\n/**\n  \\brief  Event on mutex owner retrieve (API)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n  \\param[in]  thread_id thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE))\nextern void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id);\n#else\n#define EvrRtxMutexGetOwner(mutex_id, thread_id)\n#endif\n\n/**\n  \\brief  Event on mutex delete (API)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE))\nextern void EvrRtxMutexDelete (osMutexId_t mutex_id);\n#else\n#define EvrRtxMutexDelete(mutex_id)\n#endif\n\n/**\n  \\brief  Event on successful mutex delete (Op)\n  \\param[in]  mutex_id  mutex ID obtained by \\ref osMutexNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE))\nextern void EvrRtxMutexDestroyed (osMutexId_t mutex_id);\n#else\n#define EvrRtxMutexDestroyed(mutex_id)\n#endif\n\n\n//  ==== Semaphore Events ====\n\n/**\n  \\brief  Event on semaphore error (Error)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew or NULL when ID is unknown.\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE))\nextern void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status);\n#else\n#define EvrRtxSemaphoreError(semaphore_id, status)\n#endif\n\n/**\n  \\brief  Event on semaphore create and initialize (API)\n  \\param[in]  max_count     maximum number of available tokens.\n  \\param[in]  initial_count initial number of available tokens.\n  \\param[in]  attr          semaphore attributes.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE))\nextern void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);\n#else\n#define EvrRtxSemaphoreNew(max_count, initial_count, attr)\n#endif\n\n/**\n  \\brief  Event on successful semaphore create (Op)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n  \\param[in]  name          pointer to semaphore object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE))\nextern void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name);\n#else\n#define EvrRtxSemaphoreCreated(semaphore_id, name)\n#endif\n\n/**\n  \\brief  Event on semaphore name retrieve (API)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n  \\param[in]  name          pointer to semaphore object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE))\nextern void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name);\n#else\n#define EvrRtxSemaphoreGetName(semaphore_id, name)\n#endif\n\n/**\n  \\brief  Event on semaphore acquire (API)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE))\nextern void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);\n#else\n#define EvrRtxSemaphoreAcquire(semaphore_id, timeout)\n#endif\n\n/**\n  \\brief  Event on pending semaphore acquire (Op)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE))\nextern void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout);\n#else\n#define EvrRtxSemaphoreAcquirePending(semaphore_id, timeout)\n#endif\n\n/**\n  \\brief  Event on semaphore acquire timeout (Op)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE))\nextern void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id);\n#else\n#define EvrRtxSemaphoreAcquireTimeout(semaphore_id)\n#endif\n\n/**\n  \\brief  Event on successful semaphore acquire (Op)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n  \\param[in]  tokens        number of available tokens.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE))\nextern void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens);\n#else\n#define EvrRtxSemaphoreAcquired(semaphore_id, tokens)\n#endif\n\n/**\n  \\brief  Event on unsuccessful semaphore acquire (Op)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE))\nextern void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id);\n#else\n#define EvrRtxSemaphoreNotAcquired(semaphore_id)\n#endif\n\n/**\n  \\brief  Event on semaphore release (API)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE))\nextern void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id);\n#else\n#define EvrRtxSemaphoreRelease(semaphore_id)\n#endif\n\n/**\n  \\brief  Event on successful semaphore release (Op)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n  \\param[in]  tokens        number of available tokens.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE))\nextern void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens);\n#else\n#define EvrRtxSemaphoreReleased(semaphore_id, tokens)\n#endif\n\n/**\n  \\brief  Event on semaphore token count retrieval (API)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n  \\param[in]  count         current number of available tokens.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE))\nextern void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count);\n#else\n#define EvrRtxSemaphoreGetCount(semaphore_id, count)\n#endif\n\n/**\n  \\brief  Event on semaphore delete (API)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE))\nextern void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id);\n#else\n#define EvrRtxSemaphoreDelete(semaphore_id)\n#endif\n\n/**\n  \\brief  Event on successful semaphore delete (Op)\n  \\param[in]  semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE))\nextern void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id);\n#else\n#define EvrRtxSemaphoreDestroyed(semaphore_id)\n#endif\n\n\n//  ==== Memory Pool Events ====\n\n/**\n  \\brief  Event on memory pool error (Error)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew or NULL when ID is unknown.\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE))\nextern void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status);\n#else\n#define EvrRtxMemoryPoolError(mp_id, status)\n#endif\n\n/**\n  \\brief  Event on memory pool create and initialize (API)\n  \\param[in]  block_count   maximum number of memory blocks in memory pool.\n  \\param[in]  block_size    memory block size in bytes.\n  \\param[in]  attr          memory pool attributes; NULL: default values.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE))\nextern void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);\n#else\n#define EvrRtxMemoryPoolNew(block_count, block_size, attr)\n#endif\n\n/**\n  \\brief  Event on successful memory pool create (Op)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  name          pointer to memory pool object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE))\nextern void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name);\n#else\n#define EvrRtxMemoryPoolCreated(mp_id, name)\n#endif\n\n/**\n  \\brief  Event on memory pool name retrieve (API)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  name          pointer to memory pool object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE))\nextern void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name);\n#else\n#define EvrRtxMemoryPoolGetName(mp_id, name)\n#endif\n\n/**\n  \\brief  Event on memory pool allocation (API)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE))\nextern void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);\n#else\n#define EvrRtxMemoryPoolAlloc(mp_id, timeout)\n#endif\n\n/**\n  \\brief  Event on pending memory pool allocation (Op)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE))\nextern void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout);\n#else\n#define EvrRtxMemoryPoolAllocPending(mp_id, timeout)\n#endif\n\n/**\n  \\brief  Event on memory pool allocation timeout (Op)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE))\nextern void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id);\n#else\n#define EvrRtxMemoryPoolAllocTimeout(mp_id)\n#endif\n\n/**\n  \\brief  Event on successful memory pool allocation (Op)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  block         address of the allocated memory block.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE))\nextern void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block);\n#else\n#define EvrRtxMemoryPoolAllocated(mp_id, block)\n#endif\n\n/**\n  \\brief  Event on unsuccessful memory pool allocation (Op)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE))\nextern void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id);\n#else\n#define EvrRtxMemoryPoolAllocFailed(mp_id)\n#endif\n\n/**\n  \\brief  Event on memory pool free (API)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  block         address of the allocated memory block to be returned to the memory pool.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE))\nextern void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);\n#else\n#define EvrRtxMemoryPoolFree(mp_id, block)\n#endif\n\n/**\n  \\brief  Event on successful memory pool free (Op)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  block         address of the allocated memory block to be returned to the memory pool.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE))\nextern void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block);\n#else\n#define EvrRtxMemoryPoolDeallocated(mp_id, block)\n#endif\n\n/**\n  \\brief  Event on unsuccessful memory pool free (Op)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  block         address of the allocated memory block to be returned to the memory pool.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE))\nextern void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block);\n#else\n#define EvrRtxMemoryPoolFreeFailed(mp_id, block)\n#endif\n\n/**\n  \\brief  Event on memory pool capacity retrieve (API)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  capacity      maximum number of memory blocks.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE))\nextern void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity);\n#else\n#define EvrRtxMemoryPoolGetCapacity(mp_id, capacity)\n#endif\n\n/**\n  \\brief  Event on memory pool block size retrieve (API)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  block_size    memory block size in bytes.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE))\nextern void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size);\n#else\n#define EvrRtxMemoryPoolGetBlockSize(mp_id, block_size)\n#endif\n\n/**\n  \\brief  Event on used memory pool blocks retrieve (API)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  count         number of memory blocks used.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE))\nextern void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count);\n#else\n#define EvrRtxMemoryPoolGetCount(mp_id, count)\n#endif\n\n/**\n  \\brief  Event on available memory pool blocks retrieve (API)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n  \\param[in]  space         number of memory blocks available.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE))\nextern void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space);\n#else\n#define EvrRtxMemoryPoolGetSpace(mp_id, space)\n#endif\n\n/**\n  \\brief  Event on memory pool delete (API)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE))\nextern void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id);\n#else\n#define EvrRtxMemoryPoolDelete(mp_id)\n#endif\n\n/**\n  \\brief  Event on successful memory pool delete (Op)\n  \\param[in]  mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE))\nextern void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id);\n#else\n#define EvrRtxMemoryPoolDestroyed(mp_id)\n#endif\n\n\n//  ==== Message Queue Events ====\n\n/**\n  \\brief  Event on message queue error (Error)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew or NULL when ID is unknown.\n  \\param[in]  status        extended execution status.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE))\nextern void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status);\n#else\n#define EvrRtxMessageQueueError(mq_id, status)\n#endif\n\n/**\n  \\brief  Event on message queue create and initialization (API)\n  \\param[in]  msg_count     maximum number of messages in queue.\n  \\param[in]  msg_size      maximum message size in bytes.\n  \\param[in]  attr          message queue attributes; NULL: default values.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE))\nextern void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);\n#else\n#define EvrRtxMessageQueueNew(msg_count, msg_size, attr)\n#endif\n\n/**\n  \\brief  Event on successful message queue create (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  name          pointer to message queue object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE))\nextern void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name);\n#else\n#define EvrRtxMessageQueueCreated(mq_id, name)\n#endif\n\n/**\n  \\brief  Event on message queue name retrieve(API)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  name          pointer to message queue object name.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE))\nextern void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name);\n#else\n#define EvrRtxMessageQueueGetName(mq_id, name)\n#endif\n\n/**\n  \\brief  Event on message put (API)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_ptr       pointer to buffer with message to put into a queue.\n  \\param[in]  msg_prio      message priority.\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE))\nextern void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);\n#else\n#define EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout)\n#endif\n\n/**\n  \\brief  Event on pending message put (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_ptr       pointer to buffer with message to put into a queue.\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE))\nextern void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout);\n#else\n#define EvrRtxMessageQueuePutPending(mq_id, msg_ptr, timeout)\n#endif\n\n/**\n  \\brief  Event on message put timeout (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE))\nextern void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id);\n#else\n#define EvrRtxMessageQueuePutTimeout(mq_id)\n#endif\n\n/**\n  \\brief  Event on pending message insert (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_ptr       pointer to buffer with message to put into a queue.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE))\nextern void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr);\n#else\n#define EvrRtxMessageQueueInsertPending(mq_id, msg_ptr)\n#endif\n\n/**\n  \\brief  Event on successful message insert (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_ptr       pointer to buffer with message to put into a queue.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE))\nextern void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr);\n#else\n#define EvrRtxMessageQueueInserted(mq_id, msg_ptr)\n#endif\n\n/**\n  \\brief  Event on unsuccessful message insert (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_ptr       pointer to buffer with message to put into a queue.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE))\nextern void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr);\n#else\n#define EvrRtxMessageQueueNotInserted(mq_id, msg_ptr)\n#endif\n\n/**\n  \\brief  Event on message get (API)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_ptr       pointer to buffer for message to get from a queue.\n  \\param[in]  msg_prio      message priority.\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE))\nextern void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);\n#else\n#define EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout)\n#endif\n\n/**\n  \\brief  Event on pending message get (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_ptr       pointer to buffer for message to get from a queue.\n  \\param[in]  timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE))\nextern void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout);\n#else\n#define EvrRtxMessageQueueGetPending(mq_id, msg_ptr, timeout)\n#endif\n\n/**\n  \\brief  Event on message get timeout (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE))\nextern void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id);\n#else\n#define EvrRtxMessageQueueGetTimeout(mq_id)\n#endif\n\n/**\n  \\brief  Event on successful message get (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_ptr       pointer to buffer for message to get from a queue.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE))\nextern void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr);\n#else\n#define EvrRtxMessageQueueRetrieved(mq_id, msg_ptr)\n#endif\n\n/**\n  \\brief  Event on unsuccessful message get (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_ptr       pointer to buffer for message to get from a queue.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE))\nextern void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr);\n#else\n#define EvrRtxMessageQueueNotRetrieved(mq_id, msg_ptr)\n#endif\n\n/**\n  \\brief  Event on message queue capacity retrieve (API)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  capacity      maximum number of messages.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE))\nextern void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity);\n#else\n#define EvrRtxMessageQueueGetCapacity(mq_id, capacity)\n#endif\n\n/**\n  \\brief  Event on message queue message size retrieve (API)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  msg_size      maximum message size in bytes.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE))\nextern void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size);\n#else\n#define EvrRtxMessageQueueGetMsgSize(mq_id, msg_size)\n#endif\n\n/**\n  \\brief  Event on message queue message count retrieve (API)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  count         number of queued messages.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE))\nextern void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count);\n#else\n#define EvrRtxMessageQueueGetCount(mq_id, count)\n#endif\n\n/**\n  \\brief  Event on message queue message slots retrieve (API)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n  \\param[in]  space         number of available slots for messages.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE))\nextern void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space);\n#else\n#define EvrRtxMessageQueueGetSpace(mq_id, space)\n#endif\n\n/**\n  \\brief  Event on message queue reset (API)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE))\nextern void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id);\n#else\n#define EvrRtxMessageQueueReset(mq_id)\n#endif\n\n/**\n  \\brief  Event on successful message queue reset (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE))\nextern void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id);\n#else\n#define EvrRtxMessageQueueResetDone(mq_id)\n#endif\n\n/**\n  \\brief  Event on message queue delete (API)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE))\nextern void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id);\n#else\n#define EvrRtxMessageQueueDelete(mq_id)\n#endif\n\n/**\n  \\brief  Event on successful message queue delete (Op)\n  \\param[in]  mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n*/\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE))\nextern void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id);\n#else\n#define EvrRtxMessageQueueDestroyed(mq_id)\n#endif\n\n\n#endif  // RTX_EVR_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Include/rtx_os.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX OS definitions\n *\n * -----------------------------------------------------------------------------\n */\n \n#ifndef RTX_OS_H_\n#define RTX_OS_H_\n \n#include <stdint.h>\n#include <stddef.h>\n#include \"cmsis_os2.h\"\n#include \"rtx_def.h\"\n \n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n \n \n/// Kernel Information\n#define osRtxVersionAPI      20020000   ///< API version (2.2.0)\n#define osRtxVersionKernel   50070000   ///< Kernel version (5.7.0)\n#define osRtxKernelId     \"RTX V5.7.0\"  ///< Kernel identification string\n \n \n//  ==== Common definitions ====\n \n/// Object Identifier definitions\n#define osRtxIdInvalid          0x00U\n#define osRtxIdThread           0xF1U\n#define osRtxIdTimer            0xF2U\n#define osRtxIdEventFlags       0xF3U\n#define osRtxIdMutex            0xF5U\n#define osRtxIdSemaphore        0xF6U\n#define osRtxIdMemoryPool       0xF7U\n#define osRtxIdMessage          0xF9U\n#define osRtxIdMessageQueue     0xFAU\n \n/// Object Flags definitions\n#define osRtxFlagSystemObject   0x01U\n#define osRtxFlagSystemMemory   0x02U\n \n/// Object Attribute Class definitions\n#define osRtxAttrClass_Pos      4U\n#define osRtxAttrClass_Msk      0xF0U\n \n \n//  ==== Kernel definitions ====\n \n/// Kernel State definitions\n#define osRtxKernelInactive             ((uint8_t)osKernelInactive)\n#define osRtxKernelReady                ((uint8_t)osKernelReady)\n#define osRtxKernelRunning              ((uint8_t)osKernelRunning)\n#define osRtxKernelLocked               ((uint8_t)osKernelLocked)\n#define osRtxKernelSuspended            ((uint8_t)osKernelSuspended)\n \n/// Kernel Protect definitions\n#define osRtxKernelProtectPrivileged    0x01U\n#define osRtxKernelProtectClass_Pos     4U\n#define osRtxKernelProtectClass_Msk     0xF0U\n \n \n//  ==== Thread definitions ====\n \n/// Thread State definitions (extending osThreadState)\n#define osRtxThreadStateMask            0x0FU\n \n#define osRtxThreadInactive             ((uint8_t)osThreadInactive)\n#define osRtxThreadReady                ((uint8_t)osThreadReady)\n#define osRtxThreadRunning              ((uint8_t)osThreadRunning)\n#define osRtxThreadBlocked              ((uint8_t)osThreadBlocked)\n#define osRtxThreadTerminated           ((uint8_t)osThreadTerminated)\n \n#define osRtxThreadWaitingDelay         ((uint8_t)(osRtxThreadBlocked | 0x10U))\n#define osRtxThreadWaitingJoin          ((uint8_t)(osRtxThreadBlocked | 0x20U))\n#define osRtxThreadWaitingThreadFlags   ((uint8_t)(osRtxThreadBlocked | 0x30U))\n#define osRtxThreadWaitingEventFlags    ((uint8_t)(osRtxThreadBlocked | 0x40U))\n#define osRtxThreadWaitingMutex         ((uint8_t)(osRtxThreadBlocked | 0x50U))\n#define osRtxThreadWaitingSemaphore     ((uint8_t)(osRtxThreadBlocked | 0x60U))\n#define osRtxThreadWaitingMemoryPool    ((uint8_t)(osRtxThreadBlocked | 0x70U))\n#define osRtxThreadWaitingMessageGet    ((uint8_t)(osRtxThreadBlocked | 0x80U))\n#define osRtxThreadWaitingMessagePut    ((uint8_t)(osRtxThreadBlocked | 0x90U))\n \n/// Thread Flags definitions\n#define osRtxThreadFlagDefStack 0x10U   ///< Default Stack flag\n \n/// Stack Marker definitions\n#define osRtxStackMagicWord     0xE25A2EA5U ///< Stack Magic Word (Stack Base)\n#define osRtxStackFillPattern   0xCCCCCCCCU ///< Stack Fill Pattern \n \n/// Thread Control Block\ntypedef struct osRtxThread_s {\n  uint8_t                          id;  ///< Object Identifier\n  uint8_t                       state;  ///< Object State\n  uint8_t                       flags;  ///< Object Flags\n  uint8_t                        attr;  ///< Object Attributes\n  const char                    *name;  ///< Object Name\n  struct osRtxThread_s   *thread_next;  ///< Link pointer to next Thread in Object list\n  struct osRtxThread_s   *thread_prev;  ///< Link pointer to previous Thread in Object list\n  struct osRtxThread_s    *delay_next;  ///< Link pointer to next Thread in Delay list\n  struct osRtxThread_s    *delay_prev;  ///< Link pointer to previous Thread in Delay list\n  struct osRtxThread_s   *thread_join;  ///< Thread waiting to Join\n  uint32_t                      delay;  ///< Delay Time/Round Robin Time Tick\n  int8_t                     priority;  ///< Thread Priority\n  int8_t                priority_base;  ///< Base Priority\n  uint8_t                 stack_frame;  ///< Stack Frame (EXC_RETURN[7..0])\n  uint8_t               flags_options;  ///< Thread/Event Flags Options\n  uint32_t                 wait_flags;  ///< Waiting Thread/Event Flags\n  uint32_t               thread_flags;  ///< Thread Flags\n  struct osRtxMutex_s     *mutex_list;  ///< Link pointer to list of owned Mutexes\n  void                     *stack_mem;  ///< Stack Memory\n  uint32_t                 stack_size;  ///< Stack Size\n  uint32_t                         sp;  ///< Current Stack Pointer\n  uint32_t                thread_addr;  ///< Thread entry address\n  uint32_t                  tz_memory;  ///< TrustZone Memory Identifier\n  uint8_t                        zone;  ///< Thread Zone\n  uint8_t                 reserved[3];\n  struct osRtxThread_s     *wdog_next;  ///< Link pointer to next Thread in Watchdog list\n  uint32_t                  wdog_tick;  ///< Watchdog tick counter\n} osRtxThread_t;\n \n \n//  ==== Timer definitions ====\n \n/// Timer State definitions\n#define osRtxTimerInactive      0x00U   ///< Timer Inactive\n#define osRtxTimerStopped       0x01U   ///< Timer Stopped\n#define osRtxTimerRunning       0x02U   ///< Timer Running\n \n/// Timer attribute definitions\n#define osRtxTimerPeriodic      0x01U   ///< Timer Periodic mode\n \n/// Timer Function Information\ntypedef struct {\n  osTimerFunc_t                  func;  ///< Function Pointer\n  void                           *arg;  ///< Function Argument\n} osRtxTimerFinfo_t;\n \n/// Timer Control Block\ntypedef struct osRtxTimer_s {\n  uint8_t                          id;  ///< Object Identifier\n  uint8_t                       state;  ///< Object State\n  uint8_t                       flags;  ///< Object Flags\n  uint8_t                        attr;  ///< Object Attributes\n  const char                    *name;  ///< Object Name\n  struct osRtxTimer_s           *prev;  ///< Pointer to previous active Timer\n  struct osRtxTimer_s           *next;  ///< Pointer to next active Timer\n  uint32_t                       tick;  ///< Timer current Tick\n  uint32_t                       load;  ///< Timer Load value\n  osRtxTimerFinfo_t             finfo;  ///< Timer Function Info\n} osRtxTimer_t;\n \n \n//  ==== Event Flags definitions ====\n \n/// Event Flags Control Block\ntypedef struct {\n  uint8_t                          id;  ///< Object Identifier\n  uint8_t              reserved_state;  ///< Object State (not used)\n  uint8_t                       flags;  ///< Object Flags\n  uint8_t                        attr;  ///< Object Attributes\n  const char                    *name;  ///< Object Name\n  osRtxThread_t          *thread_list;  ///< Waiting Threads List\n  uint32_t                event_flags;  ///< Event Flags\n} osRtxEventFlags_t;\n \n \n//  ==== Mutex definitions ====\n \n/// Mutex Control Block\ntypedef struct osRtxMutex_s {\n  uint8_t                          id;  ///< Object Identifier\n  uint8_t              reserved_state;  ///< Object State (not used)\n  uint8_t                       flags;  ///< Object Flags\n  uint8_t                        attr;  ///< Object Attributes\n  const char                    *name;  ///< Object Name\n  osRtxThread_t          *thread_list;  ///< Waiting Threads List\n  osRtxThread_t         *owner_thread;  ///< Owner Thread\n  struct osRtxMutex_s     *owner_prev;  ///< Pointer to previous owned Mutex\n  struct osRtxMutex_s     *owner_next;  ///< Pointer to next owned Mutex\n  uint8_t                        lock;  ///< Lock counter\n  uint8_t                  padding[3];\n} osRtxMutex_t;\n \n \n//  ==== Semaphore definitions ====\n \n/// Semaphore Control Block\ntypedef struct {\n  uint8_t                          id;  ///< Object Identifier\n  uint8_t              reserved_state;  ///< Object State (not used)\n  uint8_t                       flags;  ///< Object Flags\n  uint8_t                        attr;  ///< Object Attributes\n  const char                    *name;  ///< Object Name\n  osRtxThread_t          *thread_list;  ///< Waiting Threads List\n  uint16_t                     tokens;  ///< Current number of tokens\n  uint16_t                 max_tokens;  ///< Maximum number of tokens\n} osRtxSemaphore_t;\n \n \n//  ==== Memory Pool definitions ====\n \n/// Memory Pool Information\ntypedef struct {\n  uint32_t                 max_blocks;  ///< Maximum number of Blocks\n  uint32_t                used_blocks;  ///< Number of used Blocks\n  uint32_t                 block_size;  ///< Block Size\n  void                    *block_base;  ///< Block Memory Base Address\n  void                     *block_lim;  ///< Block Memory Limit Address\n  void                    *block_free;  ///< First free Block Address\n} osRtxMpInfo_t;\n \n/// Memory Pool Control Block\ntypedef struct {\n  uint8_t                          id;  ///< Object Identifier\n  uint8_t              reserved_state;  ///< Object State (not used)\n  uint8_t                       flags;  ///< Object Flags\n  uint8_t                        attr;  ///< Object Attributes\n  const char                    *name;  ///< Object Name\n  osRtxThread_t          *thread_list;  ///< Waiting Threads List\n  osRtxMpInfo_t               mp_info;  ///< Memory Pool Info\n} osRtxMemoryPool_t;\n \n \n//  ==== Message Queue definitions ====\n \n/// Message Control Block\ntypedef struct osRtxMessage_s {\n  uint8_t                          id;  ///< Object Identifier\n  uint8_t              reserved_state;  ///< Object State (not used)\n  uint8_t                       flags;  ///< Object Flags\n  uint8_t                    priority;  ///< Message Priority\n  struct osRtxMessage_s         *prev;  ///< Pointer to previous Message\n  struct osRtxMessage_s         *next;  ///< Pointer to next Message\n} osRtxMessage_t;\n \n/// Message Queue Control Block\ntypedef struct {\n  uint8_t                          id;  ///< Object Identifier\n  uint8_t              reserved_state;  ///< Object State (not used)\n  uint8_t                       flags;  ///< Object Flags\n  uint8_t                        attr;  ///< Object Attributes\n  const char                    *name;  ///< Object Name\n  osRtxThread_t          *thread_list;  ///< Waiting Threads List\n  osRtxMpInfo_t               mp_info;  ///< Memory Pool Info\n  uint32_t                   msg_size;  ///< Message Size\n  uint32_t                  msg_count;  ///< Number of queued Messages\n  osRtxMessage_t           *msg_first;  ///< Pointer to first Message\n  osRtxMessage_t            *msg_last;  ///< Pointer to last Message\n} osRtxMessageQueue_t;\n \n \n//  ==== Generic Object definitions ====\n \n/// Generic Object Control Block\ntypedef struct {\n  uint8_t                          id;  ///< Object Identifier\n  uint8_t                       state;  ///< Object State\n  uint8_t                       flags;  ///< Object Flags\n  uint8_t                        attr;  ///< Object Attributes\n  const char                    *name;  ///< Object Name\n  osRtxThread_t          *thread_list;  ///< Threads List\n} osRtxObject_t;\n \n \n//  ==== OS Runtime Information definitions ====\n \n/// OS Runtime Information structure\ntypedef struct {\n  const char                   *os_id;  ///< OS Identification\n  uint32_t                    version;  ///< OS Version\n  struct {                              ///< Kernel Info\n    uint8_t                     state;  ///< State\n    volatile uint8_t          blocked;  ///< Blocked\n    uint8_t                    pendSV;  ///< Pending SV\n    uint8_t                   protect;  ///< Protect options\n    uint32_t                     tick;  ///< Tick counter\n  } kernel;\n  int32_t                   tick_irqn;  ///< Tick Timer IRQ Number\n  struct {                              ///< Thread Info\n    struct {                            ///< Thread Run Info\n      osRtxThread_t             *curr;  ///< Current running Thread\n      osRtxThread_t             *next;  ///< Next Thread to Run\n    } run;\n    osRtxObject_t               ready;  ///< Ready List Object\n    osRtxThread_t               *idle;  ///< Idle Thread\n    osRtxThread_t         *delay_list;  ///< Delay List\n    osRtxThread_t          *wait_list;  ///< Wait List (no Timeout)\n    osRtxThread_t     *terminate_list;  ///< Terminate Thread List\n    osRtxThread_t          *wdog_list;  ///< Watchdog List\n    struct {                            ///< Thread Round Robin Info\n      osRtxThread_t           *thread;  ///< Round Robin Thread\n      uint32_t                timeout;  ///< Round Robin Timeout\n    } robin;\n  } thread;\n  struct {                              ///< Timer Info\n    osRtxTimer_t                *list;  ///< Active Timer List\n    osRtxThread_t             *thread;  ///< Timer Thread\n    osRtxMessageQueue_t           *mq;  ///< Timer Message Queue\n    void                (*tick)(void);  ///< Timer Tick Function\n  } timer;\n  struct {                              ///< ISR Post Processing Queue\n    uint16_t                      max;  ///< Maximum Items\n    uint16_t                      cnt;  ///< Item Count\n    uint16_t                       in;  ///< Incoming Item Index\n    uint16_t                      out;  ///< Outgoing Item Index\n    void                       **data;  ///< Queue Data\n  } isr_queue;\n  struct {                                      ///< ISR Post Processing functions\n    void          (*thread)(osRtxThread_t*);    ///< Thread Post Processing function\n    void (*event_flags)(osRtxEventFlags_t*);    ///< Event Flags Post Processing function\n    void    (*semaphore)(osRtxSemaphore_t*);    ///< Semaphore Post Processing function\n    void (*memory_pool)(osRtxMemoryPool_t*);    ///< Memory Pool Post Processing function\n    void        (*message)(osRtxMessage_t*);    ///< Message Post Processing function\n  } post_process;\n  struct {                              ///< Memory Pools (Variable Block Size)\n    void                       *stack;  ///< Stack Memory\n    void                     *mp_data;  ///< Memory Pool Data Memory\n    void                     *mq_data;  ///< Message Queue Data Memory\n    void                      *common;  ///< Common Memory\n  } mem;\n  struct {                              ///< Memory Pools (Fixed Block Size)\n    osRtxMpInfo_t              *stack;  ///< Stack for Threads\n    osRtxMpInfo_t             *thread;  ///< Thread Control Blocks\n    osRtxMpInfo_t              *timer;  ///< Timer Control Blocks\n    osRtxMpInfo_t        *event_flags;  ///< Event Flags Control Blocks\n    osRtxMpInfo_t              *mutex;  ///< Mutex Control Blocks\n    osRtxMpInfo_t          *semaphore;  ///< Semaphore Control Blocks\n    osRtxMpInfo_t        *memory_pool;  ///< Memory Pool Control Blocks\n    osRtxMpInfo_t      *message_queue;  ///< Message Queue Control Blocks\n  } mpi;\n} osRtxInfo_t;\n \nextern osRtxInfo_t osRtxInfo;           ///< OS Runtime Information\n \n/// OS Runtime Object Memory Usage structure\ntypedef struct {\n  uint32_t cnt_alloc;                   ///< Counter for alloc\n  uint32_t cnt_free;                    ///< Counter for free\n  uint32_t max_used;                    ///< Maximum used\n} osRtxObjectMemUsage_t;\n \n/// OS Runtime Object Memory Usage variables\nextern osRtxObjectMemUsage_t osRtxThreadMemUsage;\nextern osRtxObjectMemUsage_t osRtxTimerMemUsage;\nextern osRtxObjectMemUsage_t osRtxEventFlagsMemUsage;\nextern osRtxObjectMemUsage_t osRtxMutexMemUsage;\nextern osRtxObjectMemUsage_t osRtxSemaphoreMemUsage;\nextern osRtxObjectMemUsage_t osRtxMemoryPoolMemUsage;\nextern osRtxObjectMemUsage_t osRtxMessageQueueMemUsage;\n \n \n//  ==== OS API definitions ====\n \n// Object Limits definitions\n#define osRtxThreadFlagsLimit    31U    ///< number of Thread Flags available per thread\n#define osRtxEventFlagsLimit     31U    ///< number of Event Flags available per object\n#define osRtxMutexLockLimit      255U   ///< maximum number of recursive mutex locks\n#define osRtxSemaphoreTokenLimit 65535U ///< maximum number of tokens per semaphore\n \n// Control Block sizes\n#define osRtxThreadCbSize        sizeof(osRtxThread_t)\n#define osRtxTimerCbSize         sizeof(osRtxTimer_t)\n#define osRtxEventFlagsCbSize    sizeof(osRtxEventFlags_t)\n#define osRtxMutexCbSize         sizeof(osRtxMutex_t)\n#define osRtxSemaphoreCbSize     sizeof(osRtxSemaphore_t)\n#define osRtxMemoryPoolCbSize    sizeof(osRtxMemoryPool_t)\n#define osRtxMessageQueueCbSize  sizeof(osRtxMessageQueue_t)\n \n/// Memory size in bytes for Memory Pool storage.\n/// \\param         block_count   maximum number of memory blocks in memory pool.\n/// \\param         block_size    memory block size in bytes.\n#define osRtxMemoryPoolMemSize(block_count, block_size) \\\n  (4*(block_count)*(((block_size)+3)/4))\n \n/// Memory size in bytes for Message Queue storage.\n/// \\param         msg_count     maximum number of messages in queue.\n/// \\param         msg_size      maximum message size in bytes.\n#define osRtxMessageQueueMemSize(msg_count, msg_size) \\\n  (4*(msg_count)*(3+(((msg_size)+3)/4)))\n \n \n//  ==== OS External Functions ====\n \n// OS Error Codes\n#define osRtxErrorStackUnderflow        1U  ///< \\deprecated Superseded by \\ref osRtxErrorStackOverflow.\n#define osRtxErrorStackOverflow         1U  ///< Stack overflow, i.e. stack pointer below its lower memory limit for descending stacks.\n#define osRtxErrorISRQueueOverflow      2U  ///< ISR Queue overflow detected when inserting object.\n#define osRtxErrorTimerQueueOverflow    3U  ///< User Timer Callback Queue overflow detected for timer.\n#define osRtxErrorClibSpace             4U  ///< Standard C/C++ library libspace not available: increase \\c OS_THREAD_LIBSPACE_NUM.\n#define osRtxErrorClibMutex             5U  ///< Standard C/C++ library mutex initialization failed.\n#define osRtxErrorSVC                   6U  ///< Invalid SVC function called.\n \n/// OS Error Callback function\nextern uint32_t osRtxErrorNotify (uint32_t code, void *object_id);\nextern uint32_t osRtxKernelErrorNotify (uint32_t code, void *object_id);\n \n/// OS Idle Thread\nextern void osRtxIdleThread (void *argument);\n \n/// OS Exception handlers\nextern void SVC_Handler     (void);\nextern void PendSV_Handler  (void);\nextern void SysTick_Handler (void);\n \n \n//  ==== OS External Configuration ====\n \n/// OS Configuration flags\n#define osRtxConfigPrivilegedMode   (1UL<<0)    ///< Threads in Privileged mode\n#define osRtxConfigStackCheck       (1UL<<1)    ///< Stack overrun checking\n#define osRtxConfigStackWatermark   (1UL<<2)    ///< Stack usage Watermark\n#define osRtxConfigSafetyFeatures   (1UL<<3)    ///< Safety features enabled\n#define osRtxConfigSafetyClass      (1UL<<4)    ///< Safety Class feature enabled\n#define osRtxConfigExecutionZone    (1UL<<5)    ///< Execution Zone enabled\n#define osRtxConfigThreadWatchdog   (1UL<<6)    ///< Thread Watchdog enabled\n#define osRtxConfigObjPtrCheck      (1UL<<7)    ///< Object Pointer Checking enabled\n#define osRtxConfigSVCPtrCheck      (1UL<<8)    ///< SVC Pointer Checking enabled\n \n/// OS Configuration structure\ntypedef struct {\n  uint32_t                             flags;   ///< OS Configuration Flags\n  uint32_t                         tick_freq;   ///< Kernel Tick Frequency\n  uint32_t                     robin_timeout;   ///< Round Robin Timeout Tick\n  struct {                                      ///< ISR Post Processing Queue\n    void                              **data;   ///< Queue Data\n    uint16_t                             max;   ///< Maximum Items\n    uint16_t                         padding;\n  } isr_queue;\n  struct {                                      ///< Memory Pools (Variable Block Size)\n    void                         *stack_addr;   ///< Stack Memory Address\n    uint32_t                      stack_size;   ///< Stack Memory Size\n    void                       *mp_data_addr;   ///< Memory Pool Memory Address\n    uint32_t                    mp_data_size;   ///< Memory Pool Memory Size\n    void                       *mq_data_addr;   ///< Message Queue Data Memory Address\n    uint32_t                    mq_data_size;   ///< Message Queue Data Memory Size\n    void                        *common_addr;   ///< Common Memory Address\n    uint32_t                     common_size;   ///< Common Memory Size\n  } mem;\n  struct {                                      ///< Memory Pools (Fixed Block Size)\n    osRtxMpInfo_t                     *stack;   ///< Stack for Threads\n    osRtxMpInfo_t                    *thread;   ///< Thread Control Blocks\n    osRtxMpInfo_t                     *timer;   ///< Timer Control Blocks\n    osRtxMpInfo_t               *event_flags;   ///< Event Flags Control Blocks\n    osRtxMpInfo_t                     *mutex;   ///< Mutex Control Blocks\n    osRtxMpInfo_t                 *semaphore;   ///< Semaphore Control Blocks\n    osRtxMpInfo_t               *memory_pool;   ///< Memory Pool Control Blocks\n    osRtxMpInfo_t             *message_queue;   ///< Message Queue Control Blocks\n  } mpi;\n  uint32_t                 thread_stack_size;   ///< Default Thread Stack Size\n  const\n  osThreadAttr_t           *idle_thread_attr;   ///< Idle Thread Attributes\n  const\n  osThreadAttr_t          *timer_thread_attr;   ///< Timer Thread Attributes\n  void               (*timer_thread)(void *);   ///< Timer Thread Function\n  int32_t               (*timer_setup)(void);   ///< Timer Setup Function\n  const\n  osMessageQueueAttr_t        *timer_mq_attr;   ///< Timer Message Queue Attributes\n  uint32_t                     timer_mq_mcnt;   ///< Timer Message Queue maximum Messages\n} osRtxConfig_t;\n \nextern const osRtxConfig_t osRtxConfig;         ///< OS Configuration\n \n \n#ifdef  __cplusplus\n}\n#endif\n \n#endif  // RTX_OS_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Include1/cmsis_os.h",
    "content": "/*\n * Copyright (c) 2013-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        30. October 2017\n * $Revision:    V2.1.2\n *\n * Project:      CMSIS-RTOS API\n * Title:        cmsis_os.h RTX header file\n *\n * Version 0.02\n *    Initial Proposal Phase\n * Version 0.03\n *    osKernelStart added, optional feature: main started as thread\n *    osSemaphores have standard behavior\n *    osTimerCreate does not start the timer, added osTimerStart\n *    osThreadPass is renamed to osThreadYield\n * Version 1.01\n *    Support for C++ interface\n *     - const attribute removed from the osXxxxDef_t typedefs\n *     - const attribute added to the osXxxxDef macros\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\n *    Added: osKernelInitialize\n * Version 1.02\n *    Control functions for short timeouts in microsecond resolution:\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\n *    Removed: osSignalGet \n * Version 2.0.0\n *    OS objects creation without macros (dynamic creation and resource allocation):\n *     - added: osXxxxNew functions which replace osXxxxCreate\n *     - added: osXxxxAttr_t structures\n *     - deprecated: osXxxxCreate functions, osXxxxDef_t structures\n *     - deprecated: osXxxxDef and osXxxx macros\n *    osStatus codes simplified and renamed to osStatus_t\n *    osEvent return structure deprecated\n *    Kernel:\n *     - added: osKernelInfo_t and osKernelGetInfo\n *     - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)\n *     - added: osKernelLock, osKernelUnlock\n *     - added: osKernelSuspend, osKernelResume\n *     - added: osKernelGetTickCount, osKernelGetTickFreq\n *     - renamed osKernelSysTick to osKernelGetSysTimerCount\n *     - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq\n *     - deprecated osKernelSysTickMicroSec\n *    Thread:\n *     - extended number of thread priorities\n *     - renamed osPrioriry to osPrioriry_t\n *     - replaced osThreadCreate with osThreadNew\n *     - added: osThreadGetName\n *     - added: osThreadState_t and osThreadGetState\n *     - added: osThreadGetStackSize, osThreadGetStackSpace\n *     - added: osThreadSuspend, osThreadResume\n *     - added: osThreadJoin, osThreadDetach, osThreadExit\n *     - added: osThreadGetCount, osThreadEnumerate\n *     - added: Thread Flags (moved from Signals) \n *    Signals:\n *     - renamed osSignals to osThreadFlags (moved to Thread Flags)\n *     - changed return value of Set/Clear/Wait functions\n *     - Clear function limited to current running thread\n *     - extended Wait function (options)\n *     - added: osThreadFlagsGet\n *    Event Flags:\n *     - added new independent object for handling Event Flags\n *    Delay and Wait functions:\n *     - added: osDelayUntil\n *     - deprecated: osWait\n *    Timer:\n *     - replaced osTimerCreate with osTimerNew\n *     - added: osTimerGetName, osTimerIsRunning\n *    Mutex:\n *     - extended: attributes (Recursive, Priority Inherit, Robust)\n *     - replaced osMutexCreate with osMutexNew\n *     - renamed osMutexWait to osMutexAcquire\n *     - added: osMutexGetName, osMutexGetOwner\n *    Semaphore:\n *     - extended: maximum and initial token count\n *     - replaced osSemaphoreCreate with osSemaphoreNew\n *     - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)\n *     - added: osSemaphoreGetName, osSemaphoreGetCount\n *    Memory Pool:\n *     - using osMemoryPool prefix instead of osPool\n *     - replaced osPoolCreate with osMemoryPoolNew\n *     - extended osMemoryPoolAlloc (timeout)\n *     - added: osMemoryPoolGetName\n *     - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize\n *     - added: osMemoryPoolGetCount, osMemoryPoolGetSpace\n *     - added: osMemoryPoolDelete\n *     - deprecated: osPoolCAlloc\n *    Message Queue:\n *     - extended: fixed size message instead of a single 32-bit value\n *     - using osMessageQueue prefix instead of osMessage\n *     - replaced osMessageCreate with osMessageQueueNew\n *     - updated: osMessageQueuePut, osMessageQueueGet\n *     - added: osMessageQueueGetName\n *     - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize\n *     - added: osMessageQueueGetCount, osMessageQueueGetSpace\n *     - added: osMessageQueueReset, osMessageQueueDelete\n *    Mail Queue: \n *     - deprecated (superseded by extended Message Queue functionality)\n * Version 2.1.0\n *    Support for critical and uncritical sections (nesting safe):\n *    - updated: osKernelLock, osKernelUnlock\n *    - added: osKernelRestoreLock\n *    Updated Thread and Event Flags:\n *    - changed flags parameter and return type from int32_t to uint32_t\n * Version 2.1.1\n *    Additional functions allowed to be called from Interrupt Service Routines:\n *    - osKernelGetTickCount, osKernelGetTickFreq\n *    Changed Kernel Tick type to uint32_t:\n *    - updated: osKernelGetTickCount, osDelayUntil\n * Version 2.1.2\n *    Additional functions allowed to be called from Interrupt Service Routines:\n *    - osKernelGetInfo, osKernelGetState\n *---------------------------------------------------------------------------*/\n \n#ifndef CMSIS_OS_H_\n#define CMSIS_OS_H_\n \n#define osCMSIS             0x20001U    ///< API version (main[31:16].sub[15:0])\n \n#define osCMSIS_RTX         0x50003U    ///< RTOS identification and version (main[31:16].sub[15:0])\n \n#define osKernelSystemId   \"RTX V5.3\"   ///< RTOS identification string\n \n#define osFeature_MainThread  0         ///< main thread      1=main can be thread, 0=not available\n#define osFeature_Signals     31U       ///< maximum number of Signal Flags available per thread\n#define osFeature_Semaphore   65535U    ///< maximum count for \\ref osSemaphoreCreate function\n#define osFeature_Wait        0         ///< osWait function: 1=available, 0=not available\n#define osFeature_SysTick     1         ///< osKernelSysTick functions: 1=available, 0=not available\n#define osFeature_Pool        1         ///< Memory Pools:    1=available, 0=not available\n#define osFeature_MessageQ    1         ///< Message Queues:  1=available, 0=not available\n#define osFeature_MailQ       1         ///< Mail Queues:     1=available, 0=not available\n \n#if   defined(__CC_ARM)\n#define os_InRegs __value_in_regs\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define os_InRegs __attribute__((value_in_regs))\n#else\n#define os_InRegs\n#endif\n \n#if (osCMSIS >= 0x20000U)\n#include \"cmsis_os2.h\"\n#else\n#include <stdint.h>\n#include <stddef.h>\n#endif\n#include \"rtx_os.h\"\n \n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n \n \n// ==== Enumerations, structures, defines ====\n \n/// Priority values.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osPriorityIdle          = -3,         ///< Priority: idle (lowest)\n  osPriorityLow           = -2,         ///< Priority: low\n  osPriorityBelowNormal   = -1,         ///< Priority: below normal\n  osPriorityNormal        =  0,         ///< Priority: normal (default)\n  osPriorityAboveNormal   = +1,         ///< Priority: above normal\n  osPriorityHigh          = +2,         ///< Priority: high\n  osPriorityRealtime      = +3,         ///< Priority: realtime (highest)\n  osPriorityError         = 0x84,       ///< System cannot determine priority or illegal priority.\n  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osPriority;\n#else\n#define osPriority osPriority_t\n#endif\n\n/// Entry point of a thread.\ntypedef void (*os_pthread) (void const *argument);\n \n/// Entry point of a timer call back function.\ntypedef void (*os_ptimer) (void const *argument);\n \n/// Timer type.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osTimerOnce             = 0,          ///< One-shot timer.\n  osTimerPeriodic         = 1           ///< Repeating timer.\n} os_timer_type;\n#else\n#define os_timer_type osTimerType_t\n#endif\n \n/// Timeout value.\n#define osWaitForever       0xFFFFFFFFU ///< Wait forever timeout value.\n \n/// Status code values returned by CMSIS-RTOS functions.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osOK                    =    0,       ///< Function completed; no error or event occurred.\n  osEventSignal           = 0x08,       ///< Function completed; signal event occurred.\n  osEventMessage          = 0x10,       ///< Function completed; message event occurred.\n  osEventMail             = 0x20,       ///< Function completed; mail event occurred.\n  osEventTimeout          = 0x40,       ///< Function completed; timeout occurred.\n  osErrorParameter        = 0x80,       ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.\n  osErrorResource         = 0x81,       ///< Resource not available: a specified resource was not available.\n  osErrorTimeoutResource  = 0xC1,       ///< Resource not available within given time: a specified resource was not available within the timeout period.\n  osErrorISR              = 0x82,       ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osErrorISRRecursive     = 0x83,       ///< Function called multiple times from ISR with same object.\n  osErrorPriority         = 0x84,       ///< System cannot determine priority or thread has illegal priority.\n  osErrorNoMemory         = 0x85,       ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorValue            = 0x86,       ///< Value of a parameter is out of range.\n  osErrorOS               = 0xFF,       ///< Unspecified RTOS error: run-time error but no other error message fits.\n  osStatusReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osStatus;\n#else\ntypedef int32_t                  osStatus;\n#define osEventSignal           (0x08)\n#define osEventMessage          (0x10)\n#define osEventMail             (0x20)\n#define osEventTimeout          (0x40)\n#define osErrorOS               osError\n#define osErrorTimeoutResource  osErrorTimeout\n#define osErrorISRRecursive     (-126)\n#define osErrorValue            (-127)\n#define osErrorPriority         (-128)\n#endif\n \n \n// >>> the following data type definitions may be adapted towards a specific RTOS\n \n/// Thread ID identifies the thread.\n#if (osCMSIS < 0x20000U)\ntypedef void *osThreadId;\n#else\n#define osThreadId osThreadId_t\n#endif\n \n/// Timer ID identifies the timer.\n#if (osCMSIS < 0x20000U)\ntypedef void *osTimerId;\n#else\n#define osTimerId osTimerId_t\n#endif\n \n/// Mutex ID identifies the mutex.\n#if (osCMSIS < 0x20000U)\ntypedef void *osMutexId;\n#else\n#define osMutexId osMutexId_t\n#endif\n \n/// Semaphore ID identifies the semaphore.\n#if (osCMSIS < 0x20000U)\ntypedef void *osSemaphoreId;\n#else\n#define osSemaphoreId osSemaphoreId_t\n#endif\n \n/// Pool ID identifies the memory pool.\ntypedef void *osPoolId;\n \n/// Message ID identifies the message queue.\ntypedef void *osMessageQId;\n \n/// Mail ID identifies the mail queue.\ntypedef void *osMailQId;\n \n \n/// Thread Definition structure contains startup information of a thread.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_thread_def {\n  os_pthread                 pthread;   ///< start address of thread function\n  osPriority               tpriority;   ///< initial thread priority\n  uint32_t                 instances;   ///< maximum number of instances of that thread function\n  uint32_t                 stacksize;   ///< stack size requirements in bytes; 0 is default stack size\n} osThreadDef_t;\n#else\ntypedef struct os_thread_def {\n  os_pthread                 pthread;   ///< start address of thread function\n  osThreadAttr_t                attr;   ///< thread attributes\n} osThreadDef_t;\n#endif\n \n/// Timer Definition structure contains timer parameters.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_timer_def {\n  os_ptimer                   ptimer;   ///< start address of a timer function\n} osTimerDef_t;\n#else\ntypedef struct os_timer_def {\n  os_ptimer                   ptimer;   ///< start address of a timer function\n  osTimerAttr_t                 attr;   ///< timer attributes\n} osTimerDef_t;\n#endif\n \n/// Mutex Definition structure contains setup information for a mutex.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_mutex_def {\n  uint32_t                     dummy;   ///< dummy value\n} osMutexDef_t;\n#else\n#define osMutexDef_t osMutexAttr_t\n#endif\n \n/// Semaphore Definition structure contains setup information for a semaphore.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_semaphore_def {\n  uint32_t                     dummy;   ///< dummy value\n} osSemaphoreDef_t;\n#else\n#define osSemaphoreDef_t osSemaphoreAttr_t\n#endif\n \n/// Definition structure for memory block allocation.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_pool_def {\n  uint32_t                   pool_sz;   ///< number of items (elements) in the pool\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *pool;   ///< pointer to memory for pool\n} osPoolDef_t;\n#else\ntypedef struct os_pool_def {\n  uint32_t                   pool_sz;   ///< number of items (elements) in the pool\n  uint32_t                   item_sz;   ///< size of an item\n  osMemoryPoolAttr_t            attr;   ///< memory pool attributes\n} osPoolDef_t;\n#endif\n \n/// Definition structure for message queue.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_messageQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  void                         *pool;   ///< memory array for messages\n} osMessageQDef_t;\n#else\ntypedef struct os_messageQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  osMessageQueueAttr_t          attr;   ///< message queue attributes\n} osMessageQDef_t;\n#endif\n \n/// Definition structure for mail queue.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_mailQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *pool;   ///< memory array for mail\n} osMailQDef_t;\n#else\ntypedef struct os_mailQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *mail;   ///< pointer to mail\n  osMemoryPoolAttr_t         mp_attr;   ///< memory pool attributes\n  osMessageQueueAttr_t       mq_attr;   ///< message queue attributes\n} osMailQDef_t;\n#endif\n \n \n/// Event structure contains detailed information about an event.\ntypedef struct {\n  osStatus                    status;   ///< status code: event or error information\n  union {\n    uint32_t                       v;   ///< message as 32-bit value\n    void                          *p;   ///< message or mail as void pointer\n    int32_t                  signals;   ///< signal flags\n  } value;                              ///< event value\n  union {\n    osMailQId                mail_id;   ///< mail id obtained by \\ref osMailCreate\n    osMessageQId          message_id;   ///< message id obtained by \\ref osMessageCreate\n  } def;                                ///< event definition\n} osEvent;\n \n \n//  ==== Kernel Management Functions ====\n \n/// Initialize the RTOS Kernel for creating objects.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osKernelInitialize (void);\n#endif\n \n/// Start the RTOS Kernel scheduler.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osKernelStart (void);\n#endif\n \n/// Check if the RTOS kernel is already started.\n/// \\return 0 RTOS is not started, 1 RTOS is started.\n#if (osCMSIS < 0x20000U)\nint32_t osKernelRunning(void);\n#endif\n \n#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0))  // System Timer available\n \n/// Get the RTOS kernel system timer counter.\n/// \\return RTOS kernel system timer as 32-bit value \n#if (osCMSIS < 0x20000U)\nuint32_t osKernelSysTick (void);\n#else\n#define  osKernelSysTick osKernelGetSysTimerCount\n#endif\n \n/// The RTOS kernel system timer frequency in Hz.\n/// \\note Reflects the system timer setting and is typically defined in a configuration file.\n#if (osCMSIS < 0x20000U)\n#define osKernelSysTickFrequency 100000000\n#endif\n \n/// Convert a microseconds value to a RTOS kernel system timer value.\n/// \\param         microsec     time value in microseconds.\n/// \\return time value normalized to the \\ref osKernelSysTickFrequency\n#if (osCMSIS < 0x20000U)\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)\n#else\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec *  osKernelGetSysTimerFreq()) / 1000000)\n#endif\n \n#endif  // System Timer available\n \n \n//  ==== Thread Management Functions ====\n \n/// Create a Thread Definition with function, priority, and stack requirements.\n/// \\param         name          name of the thread function.\n/// \\param         priority      initial priority of the thread function.\n/// \\param         instances     number of possible thread instances.\n/// \\param         stacksz       stack size (in bytes) requirements for the thread function.\n#if defined (osObjectsExternal)  // object is external\n#define osThreadDef(name, priority, instances, stacksz) \\\nextern const osThreadDef_t os_thread_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osThreadDef(name, priority, instances, stacksz) \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ (name), (priority), (instances), (stacksz) }\n#else\n#define osThreadDef(name, priority, instances, stacksz) \\\nstatic uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1] __attribute__((section(\".bss.os.thread.stack\"))); \\\nstatic osRtxThread_t os_thread_cb_##name __attribute__((section(\".bss.os.thread.cb\"))); \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ (name), \\\n  { NULL, osThreadDetached, \\\n    (instances == 1) ? (&os_thread_cb_##name) : NULL,\\\n    (instances == 1) ? osRtxThreadCbSize : 0U, \\\n    ((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \\\n    8*((stacksz+7)/8), \\\n    (priority), 0U, 0U } }\n#endif\n#endif\n \n/// Access a Thread definition.\n/// \\param         name          name of the thread definition object.\n#define osThread(name) \\\n&os_thread_def_##name\n \n/// Create a thread and add it to Active Threads and set it to state READY.\n/// \\param[in]     thread_def    thread definition referenced with \\ref osThread.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);\n \n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\n#if (osCMSIS < 0x20000U)\nosThreadId osThreadGetId (void);\n#endif\n \n/// Change priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);\n#endif\n \n/// Get current priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return current priority value of the specified thread.\n#if (osCMSIS < 0x20000U)\nosPriority osThreadGetPriority (osThreadId thread_id);\n#endif\n \n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadYield (void);\n#endif\n \n/// Terminate execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadTerminate (osThreadId thread_id);\n#endif\n \n \n//  ==== Signal Management ====\n \n/// Set the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that should be set.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\nint32_t osSignalSet (osThreadId thread_id, int32_t signals);\n \n/// Clear the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that shall be cleared.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.\nint32_t osSignalClear (osThreadId thread_id, int32_t signals);\n \n/// Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\n/// \\param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event flag information or error code.\nos_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);\n \n \n//  ==== Generic Wait Functions ====\n \n/// Wait for Timeout (Time Delay).\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osDelay (uint32_t millisec);\n#endif\n \n#if (defined (osFeature_Wait) && (osFeature_Wait != 0))  // Generic Wait available\n \n/// Wait for Signal, Message, Mail, or Timeout.\n/// \\param[in] millisec          \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return event that contains signal, message, or mail information or error code.\nos_InRegs osEvent osWait (uint32_t millisec);\n \n#endif  // Generic Wait available\n \n \n//  ==== Timer Management Functions ====\n \n/// Define a Timer object.\n/// \\param         name          name of the timer object.\n/// \\param         function      name of the timer call back function.\n#if defined (osObjectsExternal)  // object is external\n#define osTimerDef(name, function) \\\nextern const osTimerDef_t os_timer_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osTimerDef(name, function) \\\nconst osTimerDef_t os_timer_def_##name = { (function) }\n#else\n#define osTimerDef(name, function) \\\nstatic osRtxTimer_t os_timer_cb_##name __attribute__((section(\".bss.os.timer.cb\"))); \\\nconst osTimerDef_t os_timer_def_##name = \\\n{ (function), { NULL, 0U, (&os_timer_cb_##name), osRtxTimerCbSize } }\n#endif\n#endif\n \n/// Access a Timer definition.\n/// \\param         name          name of the timer object.\n#define osTimer(name) \\\n&os_timer_def_##name\n \n/// Create and Initialize a timer.\n/// \\param[in]     timer_def     timer object referenced with \\ref osTimer.\n/// \\param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer call back function.\n/// \\return timer ID for reference by other functions or NULL in case of error.\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);\n \n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value of the timer.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec);\n#endif\n \n/// Stop a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerStop (osTimerId timer_id);\n#endif\n \n/// Delete a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerDelete (osTimerId timer_id);\n#endif\n \n \n//  ==== Mutex Management Functions ====\n \n/// Define a Mutex.\n/// \\param         name          name of the mutex object.\n#if defined (osObjectsExternal)  // object is external\n#define osMutexDef(name) \\\nextern const osMutexDef_t os_mutex_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osMutexDef(name) \\\nconst osMutexDef_t os_mutex_def_##name = { 0 }\n#else\n#define osMutexDef(name) \\\nstatic osRtxMutex_t os_mutex_cb_##name __attribute__((section(\".bss.os.mutex.cb\"))); \\\nconst osMutexDef_t os_mutex_def_##name = \\\n{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, (&os_mutex_cb_##name), osRtxMutexCbSize }\n#endif\n#endif\n \n/// Access a Mutex definition.\n/// \\param         name          name of the mutex object.\n#define osMutex(name) \\\n&os_mutex_def_##name\n \n/// Create and Initialize a Mutex object.\n/// \\param[in]     mutex_def     mutex definition referenced with \\ref osMutex.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def);\n \n/// Wait until a Mutex becomes available.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);\n#else\n#define  osMutexWait osMutexAcquire\n#endif\n \n/// Release a Mutex that was obtained by \\ref osMutexWait.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexRelease (osMutexId mutex_id);\n#endif\n \n/// Delete a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexDelete (osMutexId mutex_id);\n#endif\n \n \n//  ==== Semaphore Management Functions ====\n \n#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))  // Semaphore available\n \n/// Define a Semaphore object.\n/// \\param         name          name of the semaphore object.\n#if defined (osObjectsExternal)  // object is external\n#define osSemaphoreDef(name) \\\nextern const osSemaphoreDef_t os_semaphore_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osSemaphoreDef(name) \\\nconst osSemaphoreDef_t os_semaphore_def_##name = { 0 }\n#else\n#define osSemaphoreDef(name) \\\nstatic osRtxSemaphore_t os_semaphore_cb_##name __attribute__((section(\".bss.os.semaphore.cb\"))); \\\nconst osSemaphoreDef_t os_semaphore_def_##name = \\\n{ NULL, 0U, (&os_semaphore_cb_##name), osRtxSemaphoreCbSize }\n#endif\n#endif\n \n/// Access a Semaphore definition.\n/// \\param         name          name of the semaphore object.\n#define osSemaphore(name) \\\n&os_semaphore_def_##name\n \n/// Create and Initialize a Semaphore object.\n/// \\param[in]     semaphore_def semaphore definition referenced with \\ref osSemaphore.\n/// \\param[in]     count         maximum and initial number of available tokens.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);\n \n/// Wait until a Semaphore token becomes available.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return number of available tokens, or -1 in case of incorrect parameters.\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);\n \n/// Release a Semaphore token.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id);\n#endif\n \n/// Delete a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id);\n#endif\n \n#endif  // Semaphore available\n \n \n//  ==== Memory Pool Management Functions ====\n \n#if (defined(osFeature_Pool) && (osFeature_Pool != 0))  // Memory Pool available\n \n/// \\brief Define a Memory Pool.\n/// \\param         name          name of the memory pool.\n/// \\param         no            maximum number of blocks (objects) in the memory pool.\n/// \\param         type          data type of a single block (object).\n#if defined (osObjectsExternal)  // object is external\n#define osPoolDef(name, no, type) \\\nextern const osPoolDef_t os_pool_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osPoolDef(name, no, type) \\\nconst osPoolDef_t os_pool_def_##name = \\\n{ (no), sizeof(type), NULL }\n#else\n#define osPoolDef(name, no, type) \\\nstatic osRtxMemoryPool_t os_mp_cb_##name __attribute__((section(\".bss.os.mempool.cb\"))); \\\nstatic uint32_t os_mp_data_##name[osRtxMemoryPoolMemSize((no),sizeof(type))/4] __attribute__((section(\".bss.os.mempool.mem\"))); \\\nconst osPoolDef_t os_pool_def_##name = \\\n{ (no), sizeof(type), \\\n  { NULL, 0U, (&os_mp_cb_##name), osRtxMemoryPoolCbSize, \\\n              (&os_mp_data_##name), sizeof(os_mp_data_##name) } }\n#endif\n#endif\n \n/// \\brief Access a Memory Pool definition.\n/// \\param         name          name of the memory pool\n#define osPool(name) \\\n&os_pool_def_##name\n \n/// Create and Initialize a Memory Pool object.\n/// \\param[in]     pool_def      memory pool definition referenced with \\ref osPool.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\nosPoolId osPoolCreate (const osPoolDef_t *pool_def);\n \n/// Allocate a memory block from a Memory Pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolAlloc (osPoolId pool_id);\n \n/// Allocate a memory block from a Memory Pool and set memory block to zero.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolCAlloc (osPoolId pool_id);\n \n/// Return an allocated memory block back to a Memory Pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\param[in]     block         address of the allocated memory block to be returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\nosStatus osPoolFree (osPoolId pool_id, void *block);\n \n#endif  // Memory Pool available\n \n \n//  ==== Message Queue Management Functions ====\n \n#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))  // Message Queue available\n  \n/// \\brief Create a Message Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of messages in the queue.\n/// \\param         type          data type of a single message element (for debugger).\n#if defined (osObjectsExternal)  // object is external\n#define osMessageQDef(name, queue_sz, type) \\\nextern const osMessageQDef_t os_messageQ_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osMessageQDef(name, queue_sz, type) \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), NULL }\n#else\n#define osMessageQDef(name, queue_sz, type) \\\nstatic osRtxMessageQueue_t os_mq_cb_##name __attribute__((section(\".bss.os.msgqueue.cb\"))); \\\nstatic uint32_t os_mq_data_##name[osRtxMessageQueueMemSize((queue_sz),sizeof(uint32_t))/4] __attribute__((section(\".bss.os.msgqueue.mem\"))); \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), \\\n  { NULL, 0U, (&os_mq_cb_##name), osRtxMessageQueueCbSize, \\\n              (&os_mq_data_##name), sizeof(os_mq_data_##name) } }\n#endif\n#endif\n \n/// \\brief Access a Message Queue Definition.\n/// \\param         name          name of the queue\n#define osMessageQ(name) \\\n&os_messageQ_def_##name\n \n/// Create and Initialize a Message Queue object.\n/// \\param[in]     queue_def     message queue definition referenced with \\ref osMessageQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);\n \n/// Put a Message to a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     info          message information.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);\n \n/// Get a Message from a Queue or timeout if Queue is empty.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\nos_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);\n \n#endif  // Message Queue available\n \n \n//  ==== Mail Queue Management Functions ====\n \n#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))  // Mail Queue available\n \n/// \\brief Create a Mail Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of mails in the queue.\n/// \\param         type          data type of a single mail element.\n#if defined (osObjectsExternal)  // object is external\n#define osMailQDef(name, queue_sz, type) \\\nextern const osMailQDef_t os_mailQ_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osMailQDef(name, queue_sz, type) \\\nconst osMailQDef_t os_mailQ_def_##name = \\\n{ (queue_sz), sizeof(type), NULL }\n#else\n#define osMailQDef(name, queue_sz, type) \\\nstatic void              *os_mail_p_##name[2]  __attribute__((section(\".bss.os\"))); \\\nstatic osRtxMemoryPool_t   os_mail_mp_cb_##name __attribute__((section(\".bss.os.mempool.cb\"))); \\\nstatic osRtxMessageQueue_t os_mail_mq_cb_##name __attribute__((section(\".bss.os.msgqueue.cb\"))); \\\nstatic uint32_t os_mail_mp_data_##name[osRtxMemoryPoolMemSize  ((queue_sz),sizeof(type) )/4] __attribute__((section(\".bss.os.mempool.mem\"))); \\\nstatic uint32_t os_mail_mq_data_##name[osRtxMessageQueueMemSize((queue_sz),sizeof(void*))/4] __attribute__((section(\".bss.os.msgqueue.mem\"))); \\\nconst osMailQDef_t os_mailQ_def_##name = \\\n{ (queue_sz), sizeof(type), (&os_mail_p_##name), \\\n  { NULL, 0U, (&os_mail_mp_cb_##name), osRtxMemoryPoolCbSize, \\\n              (&os_mail_mp_data_##name), sizeof(os_mail_mp_data_##name) }, \\\n  { NULL, 0U, (&os_mail_mq_cb_##name), osRtxMessageQueueCbSize, \\\n              (&os_mail_mq_data_##name), sizeof(os_mail_mq_data_##name) } }\n#endif\n#endif\n \n/// \\brief Access a Mail Queue Definition.\n/// \\param         name          name of the queue\n#define osMailQ(name) \\\n&os_mailQ_def_##name\n \n/// Create and Initialize a Mail Queue object.\n/// \\param[in]     queue_def     mail queue definition referenced with \\ref osMailQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return mail queue ID for reference by other functions or NULL in case of error.\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);\n \n/// Allocate a memory block for mail from a mail memory pool.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec);\n \n/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec);\n \n/// Put a Mail into a Queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to memory with mail to put into a queue.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailPut (osMailQId queue_id, const void *mail);\n \n/// Get a Mail from a Queue or timeout if Queue is empty.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\nos_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);\n \n/// Free a memory block by returning it to a mail memory pool.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to memory block that was obtained with \\ref osMailGet.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailFree (osMailQId queue_id, void *mail);\n \n#endif  // Mail Queue available\n \n \n#ifdef  __cplusplus\n}\n#endif\n \n#endif  // CMSIS_OS_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/ARM/MDK/Lint/MISRA_C_2012_Config.lnt",
    "content": "/*----------------------------------------------------------------------------\n  MISRA_C_2012.lnt\n  MISRA C 2012 rule configuration file for PC-lint\n *----------------------------------------------------------------------------*/\n\n// include MISRA C 2012 PC-lint file\nau-misra3.lnt\n\n// <<< Use Configuration Wizard in Context Menu >>>\n\n// <h> Checker for Misra C 2012 rules\n\n// <h> Directive 1\n/**** Dir 1.1 (Req) ************/\n// <n> Directive 1.1 (required): Any implementation-defined behaviour on which the output of the program depends shall be documented and understood\n//  <i> *** NOT CHECKED *** not statically checkable\n// </h>\n\n// <h> Directive 2\n/**** Dir 2.1 (Req) ************/\n// <!c> Directive 2.1 (required): All source files shall compile without any compilation errors\n    //-e950                      /* flag non-standard word or construct */\n    //-elib(950)\n// </c>\n// </h>\n\n// <h> Directive 3\n/**** Dir 3.1 (Req) ************/\n// <n> Directive 3.1 (required): All code shall be traceable to documented requirements\n//  <i> *** NOT CHECKED *** not statically checkable\n// </h>\n\n// <h> Directive 4 Code design\n/**** Dir 4.1 (Req) ************/\n// <n> Directive 4.1 (required): Run-time failures shall be minimized\n//  <i> *** NOT CHECKED *** not statically checkable\n\n/**** Dir 4.2 (Adv) ************/\n// <n> Directive 4.2 (advisory): (required): All usage of assembly language should be documented\n//  <i> *** NOT CHECKED *** not statically checkable\n\n/**** Dir 4.3 (Req) ************/\n// <!c> Directive 4.3 (required): Assembly language shall be encapsulated and isolated\n\t//-esym(586, asm)\n// </c>\n\n/**** Dir 4.4 (Adv) ************/\n// <!c> Directive 4.4 (advisory): Sections of code should not be \"commented out\"\n    //-e602                  /* comment within comment */\n    //-elib(602)\n// </c>\n\n/**** Dir 4.5 (Adv) ************/\n// <!c> Directive 4.5 (advisory): Identifiers in the same name space with overlapping visibility should be typographically unambiguous\n    //-e9046\t  \t     /* typographical ambiguity */\n    //-elib(9046)\n// </c>\n\n/**** Dir 4.6 (Adv) ************/\n// <!c> Directive 4.6 (advisory): typedefs that indicate size and signedness should be used in place of the basic numerical types\n    //-e970               /* flag modifiers used outside of typedefs */\n    //-elib(970)\n// </c>\n\n/**** Dir 4.7 (Req) ************/\n// <!c> Directive 4.7 (required): If a function returns error information, then that error information shall be tested\n    //-e534               /* ignoring return value of function */\n    //-elib(534)\n// </c>\n\n/**** Dir 4.8 (Adv) ************/\n// <!c> Directive 4.8 (advisory): If a pointer to a structure or union is never dereferenced within a translation unit, then the implementation of the object should be hidden\n    //-e9045               /* non-hidden definition of type */\n    //-elib(9045)\n// </c>\n\n/**** Dir 4.9 (Adv) ************/\n// <!c> Directive 4.9 (advisory): A function should be used in preference to a function-like macro where they are interchangeable\n    //-e9026               /* function-like macro defined */\n    //-elib(9026)\n// </c>\n\n/**** Dir 4.10 (Req) ************/\n// <!c> Directive 4.10 (required): Precautions shall be taken in order to prevent the contents of a header file being included more than once\n    //-e451             /* Header repeatedly included without guard */\n    //-elib(451)\n// </c>\n\n/**** Dir 4.11 (Req) ************/\n// <n> Directive 4.11 (required): The validity of values passed to library functions shall be checked\n//  <i> The arguments to over 100 calls to standard library functions are monitored;\n//  <i> users can specify additional constraints for other functions\n\n/**** Dir 4.12 (Req) ************/\n// <!c> Directive 4.12 (required): Dynamic memory allocation shall not be used\n    //-esym(586, calloc)\n    //-esym(586, malloc)\n    //-esym(586, realloc)\n    //-esym(586, free)\n// </c>\n\n/**** Dir 4.13 (Adv) ************/\n// <!c> Directive 4.13 (advisory): Functions which are designed to provide operations on a resource should be called in an appropriate sequence\n    //-e480\n    //-elib(480)\n    //-e481\n    //-elib(481)\n// </c>\n// </h>\n\n// <h> Rules 1.x: A standard C environment\n/**** Rule 1.1 (Req) ************/\n// <!c> Rule 1.1 (required): The program shall contain no violations of the standard C syntax and constraints, and shall not exceed the implementation's translation limits\n    //-e950                      /* flag non-standard word or construct */\n    //-elib(950)\n// </c>\n\n/**** Rule 1.2 (Adv) ************/\n// <!c> Rule 1.2 (advisory): Language extensions should not be used\n    //-e950                      /* flag non-ANSI word or construct */\n    //-elib(950)\n// </c>\n\n/**** Rule 1.3 (Req) ************/\n// <!c> Rule 1.3 (required): There shall be no occurrence of undefined or critical unspecified behaviour\n    //-e406   /* unclosed comment */\n    //-elib(406)\n    //-e27    /* illegal character */\n    //-elib(27)\n    //-e2     /* unclosed quote */\n    //-elib(2)\n    //-e31    /* symbol redefinition */\n    //-elib(31)\n    //-e40    /* undeclared identifier */\n    //-elib(40)\n    //-e401   /* symbol not previously declared static */\n    //-elib(401)\n    //-e31    /* symbol redefinition */\n    //-elib(31)\n    //-e604   /* returning address of auto variable */\n    //-elib(604)\n    //-e934   /* taking address of near auto variable */\n    //-elib(934)\n    //-e606   /* non-ANSI escape sequence */\n    //-elib(606)\n    //-e9020   /* header name with non-standard character */\n    //-elib(9020)\n    //-e86    /* structure has no data elements */\n    //-elib(86)\n    //-e64    /* type mismatch */\n    //-elib(64)\n    //-e67    /* cannot cast between types */\n    //-elib(67)\n    //-e144   /* non-existent return value */\n    //-elib(144)\n    //-e564   /* variable depends on order of evaluation */\n    //-elib(564)\n    //-e54    /* division by 0 */\n    //-elib(54)\n    //-e414   /* possible division by 0 */\n    //-elib(414)\n    //-e795   /* conceivable division by 0 */\n    //-elib(795)\n    //-e413   /* likely use of null pointer */\n    //-elib(413)\n    //-e415   /* out-of-bounds pointer */\n    //-elib(415)\n    //-e416   /* out-of-bounds pointer */\n    //-elib(416)\n    //-e428   /* negative subscript */\n    //-elib(428)\n    //-e740   /* unusual pointer cast */\n    //-elib(740)\n    //-e71    /* cannot cast */\n    //-elib(71)\n    //-e504   /* unusual shift */\n    //-elib(504)\n    //-e629   /* static class for function */\n    //-elib(629)\n    //-e158   /* assignment increases capability */\n    //-elib(158)\n    //-e158   /* assignment increases capability */\n    //-elib(158)\n    //-estring(10,\"a numeric constant\")  /* expecting a numeric constant */\n    //-e136   /* illegal macro name */\n    //-elib(136)\n    //-e558   /* too few arguments */\n    //-elib(558)\n    //-e719   /* too many arguments */\n    //-elib(719)\n    //-e557   /* unrecognized format */\n    //-elib(557)\n    //-e437   /* passing struct to ellipsis */\n    //-elib(437)\n    //-e449   /* previously deallocated pointer */\n    //-elib(449)\n    //-esym(424,free) /* inappropriate deallocation */\n    //-e419   /* data overrun */\n    //-elib(419)\n    //-e564   /* variable depends on order of evaluation */\n    //-elib(564)\n    //-e931   /* both sides of an expression have side-effects */\n    //-elib(931)\n    //-e564   /* variable depends on order of evaluation */\n    //-elib(564)\n    //-e9023   /* multiple '#/##' operators in macro definition */\n    //-elib(9023)\n// </c>\n// </h>\n\n// <h> Rules 2.x: Unused code\n/**** Rule 2.1 (Req) ************/\n// <!c> Rule 2.1 (required): A project shall not contain unreachable code\n    //-e506       /* constant value boolean */\n    //-elib(506)\n    //-e527       /* unreachable */\n    //-elib(527)\n    //-e681       /* loop not entered */\n    //-elib(681)\n    //-e827       /* loop not reachable */\n    //-elib(827)\n// </c>\n\n/**** Rule 2.2 (Req) ************/\n// <!c> Rule 2.2 (required): There shall be no dead code\n    //-e438       /* value not used */\n    //-elib(438)\n    //-e505       /* redundant argument to comma */\n    //-elib(505)\n    //-e520       /* highest operator has no side effects */\n    //-elib(520)\n    //-e521       /* highest operator has no side effects */\n    //-elib(521)\n    //-e522       /* highest operator has no side effects */\n    //-elib(522)\n// </c>\n\n/**** Rule 2.3 (Adv) ************/\n// <!c> Rule 2.3 (advisory): A project should not contain unused type declarations\n    //-e751\t   /* local typedef not referenced */\n    //-elib(751)\n    //-e756\t   /* global not referenced */\n    //-elib(756)\n// </c>\n\n/**** Rule 2.4 (Adv) ************/\n// <!c> Rule 2.4 (advisory): A project should not contain unused tag declarations\n    //-e753\t   /* local tag not referenced */\n    //-elib(753)\n    //-e9058\n    //-elibsym(9058)\n// </c>\n\n/**** Rule 2.5 (Adv) ************/\n// <!c> Rule 2.5 (advisory): A project should not contain unused macro declarations\n    //-e750\t   /* local macro not referenced */\n    //-elib(750)\n    //-e755\t   /* global macro not referenced */\n    //-elib(755)\n// </c>\n\n/**** Rule 2.6 (Adv) ************/\n// <!c> Rule 2.6 (advisory): A function should not contain unused label declarations\n    //-e563\t   /* label not referenced */\n    //-elib(563)\n// </c>\n\n/**** Rule 2.7 (Adv) ************/\n// <!c> Rule 2.7 (advisory): There should be no unused parameters in functions\n    //-e715      \t     /* not referenced */\n    //-elib(715)\n// </c>\n// </h>\n\n// <h> Rules 3.x: Comments\n/**** Rule 3.1 (Req) ************/\n// <!c> Rule 3.1 (required): The character sequences /* and // shall not be used within a comment\n    //-e602                  /* comment within comment */\n    //-elib(602)\n    //-e9059\n    //-elib(9059)\n    //-e9066\n    //-elib(9066)\n// </c>\n\n/**** Rule 3.2 (Req) ************/\n// <!c> Rule 3.2 (required): Line-splicing shall not be used in // comments\n    //-e427      \t     /* C++ comment ends in \\\\ */\n    //-elib(427)\n// </c>\n// </h>\n\n// <h> Rules 4.x: Character sets and lexical conventions\n/**** Rule 4.1 (Req) ************/\n// <!c> Rule 4.1 (required): Octal and hexadecimal escape sequences shall be terminated\n    //-e9039                              /* prohibited escape sequence */\n    //-elib(9039)\n// </c>\n\n/**** Rule 4.2 (Adv) ************/\n// <!c> Rule 4.2 (advisory): Trigraphs should not be used\n    //-e584                       /* activate trigraph detected message */\n    //-elib(584)\n    //-e739                       /* activate trigraph in string message */\n    //-elib(739)\n    //-e9060                       /* trigraph in comment */\n    //-elib(9060)\n// </c>\n// </h>\n\n// <h> Rules 5.x: Identifiers\n/**** Rule 5.1 (Req) ************/\n// <!c> Rule 5.1 (required): External identifiers shall be distinct\n    //-e621       /* Identifier clash - length set by -idlen */\n    //-elib(621)\n// </c>\n\n/**** Rule 5.2 (Req) ************/\n// <!c> Rule 5.2 (required): Identifiers declared in the same scope and name space shall be distinct\n    //-e621       /* Identifier clash - length set by -idlen */\n    //-elib(621)\n// </c>\n\n/**** Rule 5.3 (Req) ************/\n// <!c> Rule 5.3 (required): An identifier declared in an inner scope shall not hide an identifier declared in an outer scope\n    //-e578               /* enable reports of name hiding */\n    //-elib(578)\n// </c>\n\n/**** Rule 5.4 (Req) ************/\n// <!c> Rule 5.4 (required): Macro identifiers shall be distinct\n    //-e621       /* Identifier clash - length set by -idlen */\n    //-elib(621)\n// </c>\n\n/**** Rule 5.5 (Req) ************/\n// <!c> Rule 5.5 (required): Identifiers shall be distinct from macro names\n    //-e123       /* macro defined with arguments */\n    //-elib(123)\n    //-e621       /* Identifier clash - length set by -idlen */\n    //-elib(621)\n    //-e9061                       /* non-distinct identifier */\n    //-elib(9061)\n// </c>\n\n/**** Rule 5.6 (Req) ************/\n// <!c> Rule 5.6 (required): A typedef name shall be a unique identifier\n    //-e578               /* enable reports of name hiding */\n    //-elib(578)\n    //-e623               /* redefining the storage class of symbol */\n    //-elib(623)\n    //-esym(9062,typedef)  /* non-unique typedef */\n    //-elib(9062)\n// </c>\n\n/**** Rule 5.7 (Req) ************/\n// <!c> Rule 5.7 (required): A tag name shall be a unique identifier\n    //-e407               /* Inconsistent use of tag */\n    //-elib(407)\n    //-e578               /* Declaration of Symbol hides Symbol */\n    //-elib(578)\n    //-e14                /* Symbol previously defined */\n    //-elib(14)\n    //-e15                /* Symbol redeclared */\n    //-elib(15)\n    //-e631               /* Tag defined differently */\n    //-elib(631)\n    //-e9062                       /* non-unique tag */\n    //-elib(9062)\n// </c>\n\n/**** Rule 5.8 (Req) ************/\n// <!c> Rule 5.8 (required): Identifiers that define objects or functions with external linkage shall be unique\n    //-e401           /* Symbol not previously declared static */\n    //-elib(401)\n    //-e578           /* Declaration of Symbol hides Symbol */\n    //-elib(578)\n    //-e580           /* enable reports of name hiding */\n    //-elib(580)\n// </c>\n\n/**** Rule 5.9 (Adv) ************/\n// <!c> Rule 5.9 (advisory): Identifiers that define objects \\or functions with internal linkage should be unique\n    //-e578           /* enable reports of name hiding */\n    //-elib(578)\n    //-e580           /* enable reports of name hiding */\n    //-elib(580)\n// </c>\n// </h>\n\n// <h> Rules 6.x: Types\n/**** Rule 6.1 (Req) ************/\n// <!c> Rule 6.1 (required): Bit-fields shall only be declared with an appropriate type\n    //-e46                /* field type should be int */\n    //-elib(46)\n    //-e806               /* small bit field is signed rather than unsigned */\n    //-elib(806)\n// </c>\n\n/**** Rule 6.2 (Req) ************/\n// <!c> Rule 6.2 (required): Single-bit named bit fields shall not be of a signed type\n    //-e9088               /* named signed single-bit bit-field */\n    //-elib(9088)\n// </c>\n// </h>\n\n// <h> Rules 7.x: Literals and constants\n/**** Rule 7.1 (Req) ************/\n// <!c> Rule 7.1 (required): Octal constants shall not be used\n    //-e9001                              /* Octal constant used */\n    //-elib(9001)\n// </c>\n\n/**** Rule 7.2 (Req) ************/\n// <!c> Rule 7.2 (required): A \"u\" or \"U\" suffix shall be applied to all integer constants that are represented in an unsigned type\n    //-e9048                              /* unsigned literal without 'U' suffix */\n    //-elib(9048)\n// </c>\n\n/**** Rule 7.3 (Req) ************/\n// <!c> Rule 7.3 (required): The lowercase character \"l\" shall not be used in a literal suffix\n    //-e620                           /* suspicious constant */\n    //-elib(620)\n    //-e9057                          /* \"l\" after \"u\" in literal suffix */\n    //-elib(9057)\n// </c>\n\n/**** Rule 7.4 (Req) ************/\n// <!c> Rule 7.4 (required): A string literal shall not be assigned to an object unless the object's type is \"pointer to const-qualified char\"\n    //-e489                           /* attempting to modify a string literal */\n    //-elib(489)\n    //-e1776                          /* string literal not const safe */\n    //-elib(1776)\n    //-e1778                          /* assignment of string literal not const safe */\n    //-elib(1778)\n// </c>\n// </h>\n\n// <h> Rules 8.x: Declarations and definitions\n/**** Rule 8.1 (Req) ************/\n// <!c> Rule 8.1 (required): Types shall be explicitly specified\n    //-e601                           /* no explicit type */\n    //-elib(601)\n    //-e745                           /* function has no explicit type */\n    //-elib(745)\n    //-e808                           /* no explicit type */\n    //-elib(808)\n    //-e832                           /* parameter has no explicit type */\n    //-elib(832)\n    //-e939                           /* return type defaults to int */\n    //-elib(939)\n// </c>\n\n/**** Rule 8.2 (Req) ************/\n// <!c> Rule 8.2 (required): Function types shall be in prototype form with named parameters\n    //-e937                     /* old-style function declaration */\n    //-elib(937)\n    //-e745                           /* function has no explicit type */\n    //-elib(745)\n    //-e939                           /* return type defaults to int */\n    //-elib(939)\n    //-e18                          /* symbol redeclared */\n    //-elib(18)\n    //-e936                         /* old-style function definition */\n    //-elib(936)\n    //-e955                         /* param name missing from prototype */\n    //-elib(955)\n// </c>\n\n/**** Rule 8.3 (Req) ************/\n// <!c> Rule 8.3 (required): All declarations of an object or function shall use the same names and type qualifiers\n    //-e18                          /* symbol redeclared */\n    //-elib(18)\n    //-e516                         /* argument type conflict */\n    //-elib(516)\n    //-e532                         /* return mode of symbol inconsistent */\n    //-elib(532)\n    //-e9072                        /* parameter list differs */\n    //-elib(9072)\n// </c>\n\n/**** Rule 8.4 (Req) ************/\n// <!c> Rule 8.4 (required): A compatible declaration shall be visible when an object or function with external linkage is defined\n    //-e15        /* symbol redeclared */\n    //-elib(15)\n    //-e64        /* flag type mismatch */\n    //-elib(64)\n    //-e516       /* argument type mismatch */\n    //-elib(516)\n    //-e9075                        /* extern defined without prior declaration */\n    //-elib(9075)\n// </c>\n\n/**** Rule 8.5 (Req) ************/\n// <!c> Rule 8.5 (required): An external object or function shall be declared once in one and only one file\n    //-e9004        /* object/function previously declared */\n    //-elib(9004)\n// </c>\n\n/**** Rule 8.6 (Req) ************/\n// <!c> Rule 8.6 (required): An identifier with external linkage shall have exactly one external definition\n    //-e14        /* Symbol previously defined */\n    //-elib(14)\n// </c>\n\n/**** Rule 8.7 (Adv) ************/\n// <!c> Rule 8.7 (advisory): Functions and objects should not be defined with external linkage if they are referenced in only one translation unit\n    //-e765        /* could be made static */\n    //-elib(765)\n// </c>\n\n/**** Rule 8.8 (Req) ************/\n// <!c> Rule 8.8 (required): The static storage class specifier shall be used in all declarations of objects and functions that have internal linkage\n    //-e839           /* storage class assumed static */\n    //-elib(839)\n// </c>\n\n/**** Rule 8.9 (Adv) ************/\n// <!c> Rule 8.9 (advisory): An object should be defined at block scope if its identifier only appears in a single function\n    //-e9003        /* could define variable at block scope */\n    //-elib(9003)\n// </c>\n\n/**** Rule 8.10 (Req) ************/\n// <!c> Rule 8.10 (required): An inline function shall be declared with the static storage class\n    //-e695    \t     /* inline function without storage-class specifier */\n    //-elib(695)\n    //-esym(9056,extern)     /* inline function defined with extern */\n// </c>\n\n/**** Rule 8.11 (Adv) ************/\n// <!c> Rule 8.11 (advisory): When an array with external linkage is declared, its size should be explicitly specified\n    //-e9067             /* array has no dimension or initializer */\n    //-elib(9067)\n// </c>\n\n/**** Rule 8.12 (Req) ************/\n// <!c> Rule 8.12 (required): Within an enumerator list, the value of an implicitly-specified enumeration constant shall be unique\n    //-e488\t/* duplicate enumerator values */\n    //-elib(488)\n// </c>\n\n/**** Rule 8.13 (Adv) ************/\n// <!c> Rule 8.13 (advisory): A pointer should point to a const-qualified type whenever possible\n    //-e818\t/* pointer could be declared pointing to const */\n    //-elib(818)\n    //-e844\t/* pointer could be declared pointing to const */\n    //-elib(844)\n    //-e954\t/* pointer could be declared pointing to const */\n    //-elib(954)\n// </c>\n\n/**** Rule 8.14 (Req) ************/\n// <!c> Rule 8.14 (required): The restrict type qualifier shall not be used\n\t//-esym(586, restrict)\n// </c>\n// </h>\n\n// <h> Rules 9.x: Initialization\n/**** Rule 9.1 (Mand) ************/\n// <!c> Rule 9.1 (mandatory): The value of an object with automatic storage duration shall not be read before it has been set\n    //-e644                   /* Symbol may not have been initialized */\n    //-elib(644)\n    //-e771                   /* Symbol conceivably not initialized */\n    //-elib(771)\n    //-e530                   /* Symbol not initialized */\n    //-elib(530)\n// </c>\n\n/**** Rule 9.2 (Req) ************/\n// <!c> Rule 9.2 (required): The initializer for an aggregate or union shall be enclosed in braces\n    //-e9069                  /* omitted braces within an initializer */\n    //-elib(9069)\n// </c>\n\n/**** Rule 9.3 (Req) ************/\n// <!c> Rule 9.3 (required): Arrays shall not be partially initialized\n    //-e9068                  /* too few initializers */\n    //-elib(9068)\n// </c>\n\n/**** Rule 9.4 (Req) ************/\n// <!c> Rule 9.4 (required): An element of an object shall not be initialized more than once\n    //-e485                               /* duplicate initialization */\n    //-elib(485)\n// </c>\n\n/**** Rule 9.5 (Req) ************/\n// <!c> Rule 9.5 (required): Where designated initializers are used to initialize an array object the size of the array shall be specified explicitly\n    //-e9054                              /* designated initializer and dimensionless array */\n    //-elib(9054)\n// </c>\n// </h>\n\n// <h> Rules 10.x: The essential type model\n/**** Rule 10.1 (Req) ************/\n// <!c> Rule 10.1 (required): Operands shall not be of an inappropriate essential type\n    //-e48\t\t\t\t/* bad type */\n    //-elib(48)\n    //-e9027                              /* unpermitted operand */\n    //-elib(9027)\n// </c>\n\n/**** Rule 10.2 (Req) ************/\n// <!c> Rule 10.2 (required): Expressions of essentially character type shall not be used inappropriately in addition and subtraction operations\n    //-e9028                              /* unpermitted arithmetic */\n    //-elib(9028)\n// </c>\n\n/**** Rule 10.3 (Req) ************/\n// <!c> Rule 10.3 (required): The value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category\n    //-e9034                              /* expression assigned to narrower or different essential type */\n    //-elib(9034)\n// </c>\n\n/**** Rule 10.4 (Req) ************/\n// <!c>Rule 10.4 (required): Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category\n    //-e9029                              /* mismatched essential type */\n    //-elib(9029)\n// </c>\n\n/**** Rule 10.5 (Adv) ************/\n// <!c> Rule 10.5 (advisory): The value of an expression should not be cast to an inappropriate essential type\n    //-e9030                              /* impermissible cast */\n    //-elib(9030)\n// </c>\n\n/**** Rule 10.6 (Req) ************/\n// <!c> Rule 10.6 (required): The value of a composite expression shall not be assigned to an object with wider essential type\n    //-e9031                              /* composite expression assigned to wider essential type */\n    //-elib(9031)\n// </c>\n\n/**** Rule 10.7 (Req) ************/\n// <!c> Rule 10.7 (required): If a composite expression is used as one operand of an operator in which the usual arithmetic conversions are performed then the other operand shall not have wider essential type\n    //-e9032                              /* composite expression with smaller essential type than other operand*/\n    //-elib(9032)\n// </c>\n\n/**** Rule 10.8 (Req) ************/\n// <!c> Rule 10.8 (required): The value of a composite expression shall not be cast to a different essential type category or a wider essential type\n    //-e9033                              /* impermissible cast of composite expression */\n    //-elib(9033)\n// </c>\n// </h>\n\n// <h> Rules 11.x: Pointer type conversions\n/**** Rule 11.1 (Req) ************/\n// <!c> Rule 11.1 (required): Conversions shall not be performed between a pointer to a function and any other type\n    //-e9074                   /* conversion between a pointer to function and another type */\n    //-elib(9074)\n// </c>\n\n/**** Rule 11.2 (Req) ************/\n// <!c> Rule 11.2 (required): Conversions shall not be performed between a pointer to an incomplete type and any other type\n    //-e9076                   /* conversion between a pointer to incomplete type and another type */\n    //-elib(9076)\n// </c>\n\n/**** Rule 11.3 (Req) ************/\n// <!c> Rule 11.3 (required): A cast shall not be performed between a pointer to object type and a pointer to a different object type\n    //-e9087         /* cast from pointer to pointer */\n    //-elib(9087)\n// </c>\n\n/**** Rule 11.4 (Adv) ************/\n// <!c> Rule 11.4 (advisory): A conversion should not be performed between a pointer to object and an integer type\n    //-e9078                        /* cast pointer/integer */\n    //-elib(9078)\n// </c>\n\n/**** Rule 11.5 (Adv) ************/\n// <!c> Rule 11.5 (advisory): A conversion should not be performed from pointer to void into pointer to object\n    //-e9079         /* cast from pointer to pointer */\n    //-elib(9079)\n// </c>\n\n/**** Rule 11.6 (Req) ************/\n// <!c> Rule 11.6 (required): A cast shall not be performed between pointer to void and an arithmetic type\n    //-e923                        /* cast pointer/non-pointer */\n    //-elib(923)\n// </c>\n\n/**** Rule 11.7 (Req) ************/\n// <!c> Rule 11.7 (required): A cast shall not be performed between pointer to object and a non-integer arithmetic type\n    //-e68                        /* cast pointer/float */\n    //-elib(68)\n    //-e70                        /* cast pointer/float */\n    //-elib(70)\n// </c>\n\n/**** Rule 11.8 (Req) ************/\n// <!c> Rule 11.8 (required): A cast shall not remove any const or volatile qualification from the type pointed to by a pointer\n    //-e9005                              /* attempt to cast away const/volatile from pointer or reference */\n    //-elib(9005)\n// </c>\n\n/**** Rule 11.9 (Req) ************/\n// <!c> Rule 11.9 (required): The macro NULL shall be the only permitted form of integer null pointer constant\n    //-e910       /* conversion from 0 to pointer */\n    //-elib(910)\n    //-e9080      /* integer null pointer constant */\n    //-elib(9080)\n// </c>\n// </h>\n\n// <h> Rules 12.x: Expressions\n/**** Rule 12.1 (Adv) ************/\n// <!c> Rule 12.1 (advisory): The precedence of operators within expressions should be made explicit\n    //-e9050        /* dependence placed on precedence */\n    //-elib(9050)\n// </c>\n\n/**** Rule 12.2 (Req) ************/\n// <!c> Rule 12.2 (required): The right hand operand of a shift operator shall lie in the range zero to one less than the width in bits of the essential type of the left hand operand\n    //-e598           /* excessive left shift */\n    //-elib(598)\n    //-e9053          /* shift value exceeds size of LHS */\n    //-elib(9053)\n// </c>\n\n/**** Rule 12.3 (Adv) ************/\n// <!c> Rule 12.3 (advisory): The comma operator should not be used\n    //-e9008                              /* comma operator used */\n    //-elib(9008)\n// </c>\n\n/**** Rule 12.4 (Adv) ************/\n// <!c> Rule 12.4 (advisory): Evaluation of constant expressions should not lead to unsigned integer wrap-around\n    //-e648\n    //-elib(648)      /* Overflow in computing constant */\n    //-estring(648,\"unsigned addition\")\n    //-estring(648,\"unsigned multiplication\")\n    //-estring(648,\"unsigned sub.\")\n    //-estring(648,\"unsigned shift left\")\n    //-estring(648,\"unsigned shift right\")\n// </c>\n// </h>\n\n// <h> Rules 13.x: Side effects\n/**** Rule 13.1 (Req) ************/\n// <!c> Rule 13.1 (required): Initializer lists shall not contain persistent side effects\n    //-e446                              /* side effect in initializer */\n    //-elib(446)\n// </c>\n\n/**** Rule 13.2 (Req) ************/\n// <!c> Rule 13.2 (required): The value of an expression and its persistent side effects shall be the same under all permitted evaluation orders\n    //-e564\t\t\t/* variable depends on order of evaluation */\n    //-elib(564)\n    //-e864\t\t\t/* variable possibly depends on order of evaluation */\n    //-elib(864)\n    //-e931\t       \t    \t/* both sides have side effects */\n    //-elib(931)\n// </c>\n\n/**** Rule 13.3 (Adv) ************/\n// <!c> Rule 13.3 (advisory): A full expression containing an increment (++) or decrement (--) operator should have no other potential side effects other than that caused by the increment or decrement operator\n    //-e9049                              /* increment/decrement combined with other operations */\n    //-elib(9049)\n// </c>\n\n/**** Rule 13.4 (Adv) ************/\n// <!c> Rule 13.4 (advisory): The result of an assignment operator should not be used\n    //-e720                    /* Boolean test of assignment */\n    //-elib(720)\n    //-e820                    /* Boolean test of parenthesized assignment */\n    //-elib(820)\n    //-e9084                   /* assignment used inside larger expression */\n    //-elib(9084)\n// </c>\n\n/**** Rule 13.5 (Req) ************/\n// <!c> Rule 13.5 (required): The right hand operand of a logical && or || operator shall not contain persistent side effects\n    //-e9007                              /* side effects on right hand side of logical operator */\n    //-elib(9007)\n// </c>\n\n/**** Rule 13.6 (Mand) ************/\n// <!c> Rule 13.6 (mandatory): The operand of the sizeof operator shall not contain any expression which has potential side effects\n    //-e9006                              /* sizeof used with expression with side effect */\n    //-elib(9006)\n    //-e9089                              /* potential side-effect in argument to sizeof */\n    //-elib(9089)\n// </c>\n// </h>\n\n// <h> Rules 14.x: Control statement expressions\n/**** Rule 14.1 (Req) ************/\n// <!c> Rule 14.1 (required): A loop counter shall not have essentially floating type\n    //-e9009                              /* floating point variable used as loop counter */\n    //-elib(9009)\n// </c>\n\n/**** Rule 14.2 (Req) ************/\n// <!c> Rule 14.2 (required): A for loop shall be well-formed\n    //-e850           /* index variable modified in body of for loop */\n    //-elib(850)\n// </c>\n\n/**** Rule 14.3 (Req) ************/\n// <!c> Rule 14.3 (required): Controlling expressions shall not be invariant\n    //-e685\t\t\t/* relational always evaluates to true/false */\n    //-elib(685)\n    //-e774\t\t\t/* boolean always evaluates to true/false */\n    //-elib(774)\n    //-e650\t\t\t/* constant out of range for operator */\n    //-elib(650)\n// </c>\n\n/**** Rule 14.4 (Req) ************/\n// <!c> Rule 14.4 (required): The controlling expression of an if statement and the controlling expression of an iteration-statement shall have essentially Boolean type\n    //-e9036                              /* condition should have essentially Boolean type */\n    //-elib(9036)\n// </c>\n// </h>\n\n// <h> Rules 15.x: Control flow\n/**** Rule 15.1 (Adv) ************/\n// <!c> Rule 15.1 (advisory): The goto statement should not be used\n    //-e801       /* use of 'goto' is deprecated */\n    //-elib(801)\n// </c>\n\n/**** Rule 15.2 (Req) ************/\n// <!c> Rule 15.2 (required): The goto statement shall jump to a label declared later in the same function\n    //-e9064      /* goto references earlier label */\n    //-elib(9064)\n// </c>\n\n/**** Rule 15.3 (Req) ************/\n// <!c> Rule 15.3 (required): Any label referenced by a goto statement shall be declared in the same block, or in any block enclosing the goto statement\n    //-e9041                      /* goto not nested in the same block as label */\n    //-elib(9041)\n// </c>\n\n/**** Rule 15.4 (Adv) ************/\n// <!c> Rule 15.4 (advisory): There should be no more than one break or goto statement used to terminate any iteration statement\n    //-e9011                              /* more than one 'break' terminates loop */\n    //-elib(9011)\n// </c>\n\n/**** Rule 15.5 (Adv) ************/\n// <!c> Rule 15.5 (advisory): A function should have a single point of exit at the end\n    //-e904                   /* return before function end */\n    //-elib(904)\n// </c>\n\n/**** Rule 15.6 (Req) ************/\n// <!c> Rule 15.6 (required): The body of an iteration-statement or a selection-statement shall be acompound-statement\n    //-e9012                   /* sub-statement should be a compound statement */\n    //-elib(9012)\n// </c>\n\n/**** Rule 15.7 (Req) ************/\n// <!c> Rule 15.7 (required): All if ... else if constructs shall be terminated with an else statement\n    //-e9013                   /* no 'else' at end of 'if ... else if' chain */\n    //-elib(9013)\n    //-e9063                   /* no comment or action in else-branch */\n    //-elib(9063)\n// </c>\n// </h>\n\n// <h> Rules 16.x: Switch statements\n/**** Rule 16.1 (Req) ************/\n// <!c> Rule 16.1 (required): All switch statements shall be well-formed\n    //-e616                  /* control flows into case/default */\n    //-elib(616)\n    //-e744                  /* switch statement has no default */\n    //-elib(744)\n    //-e764                  /* switch does not have a case */\n    //-elib(764)\n    //-e825                  /* control flows into case/default without -fallthrough comment */\n    //-elib(825)\n    //-e9014                 /* default missing from switch */\n    //-elib(9014)\n    //-e9042                 /* departure from MISRA switch syntax */\n    //-elib(9042)\n    //-e9077                 /* missing unconditional break */\n    //-elib(9077)\n    //-e9081                 /* too few independent cases for switch */\n    //-elib(9081)\n    //-e9082                 /* switch statement should either begin or end with default label */\n    //-elib(9082)\n    //-e9085                 /* statement or comment should appear in default case */\n    //-elib(9085)\n// </c>\n\n/**** Rule 16.2 (Req) ************/\n// <!c> Rule 16.2 (required): A switch label shall only be used when the most closely-enclosing compound statement is the body of a switch statement\n    //-e44                  /* Need a switch */\n    //-elib(44)\n    //-e9055                /* enclosing statement is not a switch */\n    //-elib(9055)\n// </c>\n\n/**** Rule 16.3 (Req) ************/\n// <!c> Rule 16.3 (required): An unconditional break statement shall terminate every switch-clause\n    //-e616                 /* control flows into case/default */\n    //-elib(616)\n    //-e825                 /* control flows into case/default without -fallthrough comment */\n    //-elib(825)\n    //-e9077                /* missing unconditional break */\n    //-elib(9077)\n    //-e9090                /* missing unconditional break */\n    //-elib(9090)\n// </c>\n\n/**** Rule 16.4 (Req) ************/\n// <!c> Rule 16.4 (required): Every switch statement shall have a default label\n    //-e744            /* switch statement has no default */\n    //-elib(744)\n    //-e9014            /* switch statement has no default */\n    //-elib(9014)\n    //-e9085            /* default case has no statement nor comment */\n    //-elib(9085)\n// </c>\n\n/**** Rule 16.5 (Req) ************/\n// <!c> Rule 16.5 (required): A default label shall appear as either the first or the last switch label of a switch statement\n    //-e9082                   /* default should be first or last */\n    //-elib(9082)\n// </c>\n\n/**** Rule 16.6 (Req) ************/\n// <!c> Rule 16.6 (required): Every switch statement shall have at least two switch-clauses\n    //-e764            /* switch does not have a case */\n    //-elib(764)\n    //-e9081           /* too few cases */\n    //-elib(9081)\n// </c>\n\n/**** Rule 16.7 (Req) ************/\n// <!c> Rule 16.7 (required): A switch-expression shall not have essentially Boolean type\n    //-e483                   /* boolean value in switch expression */\n    //-elib(483)\n// </c>\n// </h>\n\n// <h> Rules 17.x: Functions\n/**** Rule 17.1 (Req) ************/\n// <!c> Rule 17.1 (required): The features of <stdarg.h> shall not be used\n    //-efile(829, stdarg.h)\n    //-esym(586, va_arg)\n    //-esym(586, va_start)\n    //-esym(586, va_end)\n    //-esym(586, va_copy)\n// </c>\n\n/**** Rule 17.2 (Req) ************/\n// <!c> Rule 17.2 (required): Functions shall not call themselves, either directly or indirectly\n    //-e9070\n// </c>\n\n/**** Rule 17.3 (Mand) ************/\n// <!c> Rule 17.3 (mandatory): A function shall not be declared implicitly\n    //-e718  \t      \t\t /* symbol undeclared, assumed to return int */\n    //-elib(718)\n// </c>\n\n/**** Rule 17.4 (Mand) ************/\n// <!c> Rule 17.4 (mandatory): All exit paths from a function with non-void return type shall have an explicit return statement with an expression\n    //-e533                /* function should return a value */\n    //-elib(533)\n// </c>\n\n/**** Rule 17.5 (Adv) ************/\n// <n> Rule 17.5 (advisory): The function argument corresponding to a parameter declared to have an array type shall have an appropriate number of elements\n//  <i> *** NOT CHECKED *** MISRA has declared this rule to be \"undecidable\"\n\n/**** Rule 17.6 (Mand) ************/\n// <!c> Rule 17.6 (mandatory): The declaration of an array parameter shall not contain the static keyword between the [ ]\n    //-e9043                   /* static between brackets of array declaration */\n    //-elib(9043)\n// </c>\n\n/**** Rule 17.7 (Req) ************/\n// <!c> Rule 17.7 (required): The value returned by a function having non-void return type shall be used\n    //-e534               /* ignoring return value of function */\n    //-elib(534)\n// </c>\n\n/**** Rule 17.8 (Adv) ************/\n// <!c> Rule 17.8 (advisory): A function parameter should not be modified\n    //-e9044               /* function parameter modified */\n    //-elib(9044)\n// </c>\n// </h>\n\n// <h> Rules 18.x: Pointers and arrays\n/**** Rule 18.1 (Req) ************/\n// <!c> Rule 18.1 (required): A pointer resulting from arithmetic on a pointer operand shall address an element of the same array as that pointer operand\n    //-e415          /* out-of-bounds pointer */\n    //-elib(415)\n    //-e416          /* out-of-bounds pointer */\n    //-elib(416)\n    //-e428          /* out-of-bounds pointer */\n    //-elib(428)\n    //-e661          /* out-of-bounds pointer */\n    //-elib(661)\n    //-e662          /* out-of-bounds pointer */\n    //-elib(662)\n    //-e676          /* out-of-bounds pointer */\n    //-elib(676)\n    //-e796          /* out-of-bounds pointer */\n    //-elib(796)\n    //-e797          /* out-of-bounds pointer */\n    //-elib(797)\n    //-e817          /* out-of-bounds pointer */\n    //-elib(817)\n// </c>\n\n/**** Rule 18.2 (Req) ************/\n// <!c> Rule 18.2 (required): Subtraction between pointers shall only be applied to pointers that address elements of the same array\n    //-e946          /* relational or subtract operator applied to pointers */\n    //-elib(946)\n    //-e947          /* relational or subtract operator applied to pointers */\n    //-elib(947)\n// </c>\n\n/**** Rule 18.3 (Req) ************/\n// <!c> Rule 18.3 (required): The relational operators >, >=, < and <= shall not be applied to objects of pointer type except where they point into the same object\n    //-e946          /* relational or subtract operator applied to pointers */\n    //-elib(946)\n    //-e947          /* relational or subtract operator applied to pointers */\n    //-elib(947)\n// </c>\n\n/**** Rule 18.4 (Adv) ************/\n// <!c> Rule 18.4 (advisory):  The +, -, += and -= operators should not be applied to an expression of pointer type\n    //-e9016                   /* pointer arithmetic other than array indexing used */\n    //-elib(9016)\n// </c>\n\n/**** Rule 18.5 (Adv) ************/\n// <!c> Rule 18.5 (advisory): Declarations should contain no more than two levels of pointer nesting\n    //-e9025                   /* more than two pointer indirection levels used */\n    //-elib(9025)\n// </c>\n\n/**** Rule 18.6 (Req) ************/\n// <!c> Rule 18.6 (required): The address of an object with automatic storage shall not be copied to another object that persists after the first object has ceased to exist\n    //-e733               /* assigning address of auto to outer scope symbol */\n    //-elib(733)\n    //-e789               /* assigning address of auto to static */\n    //-elib(789)\n    //-e604               /* returning address of auto variable */\n    //-elib(604)\n// </c>\n\n/**** Rule 18.7 (Req) ************/\n// <!c> Rule 18.7 (required): Flexible array members shall not be declared\n    //-e9038                   /* flexible array member declared */\n    //-elib(9038)\n// </c>\n\n/**** Rule 18.8 (Req) ************/\n// <!c> Rule 18.8 (required): Variable-length array types shall not be used\n    //-e9035                   /* variable length array declared */\n    //-elib(9035)\n// </c>\n// </h>\n\n// <h> Rules 19.x: Overlapping storage\n/**** Rule 19.1 (Mand) ************/\n// <n> Rule 19.1 (mandatory): An object shall not be assigned or copied to an overlapping object\n//  <i> *** NOT CHECKED *** MISRA has declared this rule to be \"undecidable\"\n\n/**** Rule 19.2 (Adv) ************/\n// <!c> Rule 19.2 (advisory): The union keyword should not be used\n    //-e9018                   /* union type/object declared */\n    //-elib(9018)\n// </c>\n// </h>\n\n// <h> Rules 20.x: Preprocessing directives\n/**** Rule 20.1 (Adv) ************/\n// <!c> Rule 20.1 (advisory): #include directives should only be preceded by preprocessor directives or comments\n    //-e9019                   /* declaration before #include */\n    //-elib(9019)\n// </c>\n\n/**** Rule 20.2 (Req) ************/\n// <!c> Rule 20.2 (required): The ',' or characters and the /* or // character sequences shall not occur in a header file name\n    //-e9020                   /* header file name with non-standard character */\n    //-elib(9020)\n// </c>\n\n/**** Rule 20.3 (Req) ************/\n// <!c> Rule 20.3 (required): The #include directive shall be followed by either a <filename> or \"filename\" sequence\n    //-e12                    /* Need LT or \" after #include */\n    //-elib(12)\n    //-e9086                    /* multiple arguments after #include */\n    //-elib(9086)\n// </c>\n\n/**** Rule 20.4 (Req) ************/\n// <!c> Rule 20.4 (required): A macro shall not be defined with the same name as a keyword\n    //-e9051                              /* macro with same name as a keyword */\n    //-elib(9051)\n// </c>\n\n/**** Rule 20.5 (Adv) ************/\n// <!c> Rule 20.5 (advisory): #undef should not be used\n    //-e9021                   /* use of '#undef' is discouraged */\n    //-elib(9021)\n// </c>\n\n/**** Rule 20.6 (Req) ************/\n// <!c> Rule 20.6 (required): Tokens that look like a preprocessing directive shall not occur within a macro argument\n    //-e436   /* preprocessor directive in invocation of macro */\n    //-elib(436)\n// </c>\n\n/**** Rule 20.7 (Req) ************/\n// <!c> Rule 20.7 (required): Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses\n    //-e665                   /* expression passed to unparenthesized macro */\n    //-elib(665)\n// </c>\n\n/**** Rule 20.8 (Req) ************/\n// <!c> Rule 20.8 (required): The controlling expression of a #if or #elif preprocessing directive shall evaluate to 0 or 1\n    //-e9037                  /* conditional of #if/#elif does not evaluate to 0 or 1 */\n    //-elib(9037)\n// </c>\n\n/**** Rule 20.9 (Req) ************/\n// <!c> Rule 20.9 (required): All identifiers used in the controlling expression of #if or #elif preprocessing directives shall be #define'd before evaluation\n    //-e553   /* Undefined preprocessor variable, assumed 0 */\n    //-elib(553)\n// </c>\n\n/**** Rule 20.10 (Adv) ************/\n// <!c> Rule 20.10 (advisory): The # and ## preprocessor operators should not be used\n    //-e9024                   /* '#/##' operators used */\n    //-elib(9024)\n// </c>\n\n/**** Rule 20.11 (Req) ************/\n// <!c> Rule 20.11 (required): A macro parameter immediately following a # operator shall not immediately be followed by a ## operator\n    //-e484                   /* stringize operator followed by macro parameter followed by pasting operator */\n    //-elib(484)\n// </c>\n\n/**** Rule 20.12 (Req) ************/\n// <!c> Rule 20.12 (required): A macro parameter used as an operand to the # or ## operators, which is itself subject to further macro replacement, shall only be used as an operand to these operators\n    //-e9015                              /* macro argument is used both with and without '#/##' and is subject to further replacement */\n    //-elib(9015)\n// </c>\n\n/**** Rule 20.13 (Req) ************/\n// <!c> Rule 20.13 (required): A line whose first token is # shall be a valid preprocessing directive\n    //-e544       /* endif or else not followed by EOL */\n    //-elib(544)\n    //-e16        /* # directive not followed by recognizable word */\n    //-elib(16)\n    ///* other parts of this rule such as a syntax check of the disabled portions of the code do not seem to be statically checkable */\n// </c>\n\n/**** Rule 20.14 (Req) ************/\n// <!c> Rule 20.14 (required): All #else, #elif and #endif preprocessor directives shall reside in the same file as the #if, #ifdef or #ifndef directive to which they are related\n    //-e405       /* #if/#ifdef/#ifndef not closed off */\n    //-elib(405)\n// </c>\n// </h>\n\n// <h> Rules 21.x: Standard libraries\n/**** Rule 21.1 (Req) ************/\n// <!c> Rule 21.1 (required): #define and #undef shall not be used on a reserved identifier or reserved macro name\n    //-e136       /* Illegal macro name */\n    //-elib(136)\n    ///* Undefining standard library macros is covered by rule 20.5.  */\n    ///* Defining/redefining reserved/standard identifiers is covered by rules 20.4 and 21.2. */\n    //-e9071      /* defined macro reserved to the compiler */\n    //-elib(9071)\n    //-e9083      /* undefined macro reserved to the compiler */\n    //-elib(9083)\n// </c>\n\n/**** Rule 21.2 (Req) ************/\n// <!c> Rule 21.2 (required): A reserved identifier or macro name shall not be declared\n    //-e683       /* complain about #define standard functions */\n    //-elib(683)\n    ///* Undefining standard library macros is covered by rule 20.5.  */\n    ///* Defining/redefining reserved/standard identifiers is covered by rule 20.4 and 21.2. */\n// </c>\n\n/**** Rule 21.3 (Req) ************/\n// <!c> Rule 21.3 (required): The memory allocation and deallocation functions of <stdlib.h> shall not be used\n    //-esym(586, calloc)\n    //-esym(586, malloc)\n    //-esym(586, realloc)\n    //-esym(586, free)\n// </c>\n\n/**** Rule 21.4 (Req) ************/\n// <!c> Rule 21.4 (required): The standard header file <setjmp.h> shall not be used\n    //-efile(829, setjmp.h)\n    //-esym(586, setjmp)\n    //-esym(586, longjmp)\n    //-esym(586, setjmp)\n    //-esym(586, longjmp)\n// </c>\n\n/**** Rule 21.5 (Req) ************/\n// <!c> Rule 21.5 (required): The standard header file <signal.h> shall not be used\n    //-efile(829, signal.h)\n    //-esym(586, signal)\n    //-esym(586, raise)\n    //-esym(586, SIGABRT)\n    //-esym(586, SIGFPE)\n    //-esym(586, SIGILL)\n    //-esym(586, SIGINT)\n    //-esym(586, SIGSEGV)\n    //-esym(586, SIGTERM)\n    //-esym(586, SIG_DFL)\n    //-esym(586, SIG_ERR)\n    //-esym(586, SIG_IGN)\n// </c>\n\n/**** Rule 21.6 (required): (Req) ************/\n// <!c> Rule 21.6 The Standard Library input/output functions shall not be used\n    //-esym(586, clearerr)\n    //-esym(586, fclose)\n    //-esym(586, feof)\n    //-esym(586, ferror)\n    //-esym(586, fflush)\n    //-esym(586, fgetc)\n    //-esym(586, fgetpos)\n    //-esym(586, fgets)\n    //-esym(586, fgetwc)\n    //-esym(586, fgetws)\n    //-esym(586, fopen)\n    //-esym(586, fprintf)\n    //-esym(586, fputc)\n    //-esym(586, fputs)\n    //-esym(586, fputwc)\n    //-esym(586, fputws)\n    //-esym(586, fread)\n    //-esym(586, fscanf)\n    //-esym(586, fseek)\n    //-esym(586, fsetpos)\n    //-esym(586, freopen)\n    //-esym(586, ftell)\n    //-esym(586, fwide)\n    //-esym(586, fwprintf)\n    //-esym(586, fwrite)\n    //-esym(586, fwscanf)\n    //-esym(586, getc)\n    //-esym(586, getchar)\n    //-esym(586, gets)\n    //-esym(586, getwc)\n    //-esym(586, getwchar)\n    //-esym(586, perror)\n    //-esym(586, printf)\n    //-esym(586, putc)\n    //-esym(586, putchar)\n    //-esym(586, puts)\n    //-esym(586, putwc)\n    //-esym(586, putwchar)\n    //-esym(586, remove)\n    //-esym(586, rename)\n    //-esym(586, rewind)\n    //-esym(586, scanf)\n    //-esym(586, setbuf)\n    //-esym(586, setvbuf)\n    //-esym(586, snprintf)\n    //-esym(586, sprintf)\n    //-esym(586, sscanf)\n    //-esym(586, swprintf)\n    //-esym(586, swscanf)\n    //-esym(586, tmpfile)\n    //-esym(586, tmpnam)\n    //-esym(586, ungetc)\n    //-esym(586, ungetwc)\n    //-esym(586, vfprintf)\n    //-esym(586, vfscanf)\n    //-esym(586, vfwprintf)\n    //-esym(586, vfwscanf)\n    //-esym(586, vprintf)\n    //-esym(586, vscanf)\n    //-esym(586, vsnprintf)\n    //-esym(586, vsprintf)\n    //-esym(586, vsscanf)\n    //-esym(586, vswprintf)\n    //-esym(586, vswscanf)\n    //-esym(586, vwprintf)\n    //-esym(586, vwscanf)\n    //-esym(586, wprintf)\n    //-esym(586, wscanf)\n    //-esym(586, clearerr)\n    //-esym(586, fclose)\n    //-esym(586, feof)\n    //-esym(586, ferror)\n    //-esym(586, fflush)\n    //-esym(586, fgetc)\n    //-esym(586, fgets)\n    //-esym(586, fgetpos)\n    //-esym(586, fgetwc)\n    //-esym(586, fgetws)\n    //-esym(586, fopen)\n    //-esym(586, fprintf)\n    //-esym(586, fputc)\n    //-esym(586, fputs)\n    //-esym(586, fputwc)\n    //-esym(586, fputws)\n    //-esym(586, fread)\n    //-esym(586, fscanf)\n    //-esym(586, fseek)\n    //-esym(586, fsetpos)\n    //-esym(586, freopen)\n    //-esym(586, ftell)\n    //-esym(586, fwide)\n    //-esym(586, fwprintf)\n    //-esym(586, fwrite)\n    //-esym(586, fwscanf)\n    //-esym(586, getc)\n    //-esym(586, getchar)\n    //-esym(586, gets)\n    //-esym(586, getwc)\n    //-esym(586, getwchar)\n    //-esym(586, perror)\n    //-esym(586, printf)\n    //-esym(586, putc)\n    //-esym(586, putchar)\n    //-esym(586, puts)\n    //-esym(586, putwc)\n    //-esym(586, putwchar)\n    //-esym(586, remove)\n    //-esym(586, rename)\n    //-esym(586, rewind)\n    //-esym(586, scanf)\n    //-esym(586, setbuf)\n    //-esym(586, setvbuf)\n    //-esym(586, snprintf)\n    //-esym(586, sprintf)\n    //-esym(586, sscanf)\n    //-esym(586, swprintf)\n    //-esym(586, swscanf)\n    //-esym(586, tmpfile)\n    //-esym(586, tmpnam)\n    //-esym(586, ungetc)\n    //-esym(586, ungetwc)\n    //-esym(586, vfprintf)\n    //-esym(586, vfscanf)\n    //-esym(586, vfwprintf)\n    //-esym(586, vfwscanf)\n    //-esym(586, vprintf)\n    //-esym(586, vscanf)\n    //-esym(586, vsnprintf)\n    //-esym(586, vsprintf)\n    //-esym(586, vsscanf)\n    //-esym(586, vswprintf)\n    //-esym(586, vswscanf)\n    //-esym(586, vwprintf)\n    //-esym(586, vwscanf)\n    //-esym(586, wprintf)\n    //-esym(586, wscanf)\n// </c>\n\n/**** Rule 21.7 (Req) ************/\n// <!c> Rule 21.7 (required): The atof, atoi, atol and atoll functions of <stdlib.h> shall not be used\n    //-esym(586, atof)\n    //-esym(586, atoi)\n    //-esym(586, atol)\n    //-esym(586, atoll)\n    //-esym(586, atof)\n    //-esym(586, atoi)\n    //-esym(586, atol)\n    //-esym(586, atoll)\n// </c>\n\n/**** Rule 21.8 (Req) ************/\n// <!c> Rule 21.8 (required): The library functions abort, exit, getenv and system of <stdlib.h> shall not be used\n    //-esym(586, abort)\n    //-esym(586, exit)\n    //-esym(586, getenv)\n    //-esym(586, system)\n    //-esym(586, abort)\n    //-esym(586, exit)\n    //-esym(586, getenv)\n    //-esym(586, system)\n// </c>\n\n/**** Rule 21.9 (Req) ************/\n// <!c> Rule 21.9 (required): The library functions bsearch and qsort of <stdlib.h> shall not be used\n    //-esym(586, bsearch)\n    //-esym(586, qsort)\n    //-esym(586, bsearch)\n    //-esym(586, qsort)\n// </c>\n\n/**** Rule 21.10 (Req) ************/\n// <!c> Rule 21.10 (required): The Standard Library time and date functions shall not be used\n    //-efile(829, time.h)\n    //-esym(586, wcsftime)\n    //-esym(586, wcsftime)\n    //-esym(586, clock)\n    //-esym(586, clock)\n    //-esym(586, difftime)\n    //-esym(586, difftime)\n    //-esym(586, mktime)\n    //-esym(586, mktime)\n    //-esym(586, time)\n    //-esym(586, time)\n    //-esym(586, asctime)\n    //-esym(586, asctime)\n    //-esym(586, ctime)\n    //-esym(586, ctime)\n    //-esym(586, gmtime)\n    //-esym(586, gmtime)\n    //-esym(586, localtime)\n    //-esym(586, localtime)\n    //-esym(586, strftime)\n    //-esym(586, strftime)\n    //-esym(586, CLOCKS_PER_SEC)\n// </c>\n\n/**** Rule 21.11 (Req) ************/\n// <!c> Rule 21.11 (required): The standard header file <tgmath.h> shall not be used\n    //-efile(829, tgmath.h)\n// </c>\n\n/**** Rule 21.12 (Adv) ************/\n// <!c> Rule 21.12 (advisory): The exception handling features of <fenv.h> should not be used\n    //-esym(586, feclearexcept)\n    //-esym(586, feclearexcept)\n    //-esym(586, fegetexceptflag)\n    //-esym(586, fegetexceptflag)\n    //-esym(586, feraiseexcept)\n    //-esym(586, feraiseexcept)\n    //-esym(586, fesetexceptflag)\n    //-esym(586, fesetexceptflag)\n    //-esym(586, fetestexcept)\n    //-esym(586, fetestexcept)\n    //-esym(586, FE_INEXACT)\n    //-esym(586, FE_DIVBYZERO)\n    //-esym(586, FE_UNDERFLOW)\n    //-esym(586, FE_OVERFLOW)\n    //-esym(586, FE_INVALID)\n    //-esym(586, FE_ALL_EXCEPT)\n// </c>\n// </h>\n\n// <h> Rules 22.x: Resources\n/**** Rule 22.1 (Req) ************/\n// <!c> Rule 22.1 (required): All resources obtained dynamically by means of Standard Library functions shall be explicitly released\n    //-e429       /* custodial pointer neither free'd nor returned */\n    //-elib(429)\n    //-e480       /* no balancing call */\n    //-elib(480)\n    //-e481       /* different balance call states */\n    //-elib(481)\n// </c>\n\n/**** Rule 22.2 (Mand) ************/\n// <!c> Rule 22.2 (mandatory): A block of memory shall only be freed if it was allocated by means of a Standard Library function\n    //-e424       /* inappropriate deallocation */\n    //-elib(424)\n    //-e449       /* pointer previously deallocated */\n    //-elib(449)\n// </c>\n\n/**** Rule 22.3 (required): (Req) ************/\n// <n> Rule 22.3 The same file shall not be open for read and write access at the same time on different streams\n//  <i> *** NOT CHECKED *** MISRA has declared this rule to be \"undecidable\"\n\n/**** Rule 22.4 (Mand) ************/\n// <n> Rule 22.4 (mandatory): There shall be no attempt to write to a stream which has been opened as read-only\n//  <i> *** NOT CHECKED *** MISRA has declared this rule to be \"undecidable\"\n\n/**** Rule 22.5 (Mand) ************/\n// <!c> Rule 22.5 (mandatory): A pointer to a FILE object shall not be dereferenced\n    //-e9047   /* FILE pointer dereferenced */\n    //-elib(9047)\n// </c>\n\n/**** Rule 22.6 (Mand) ************/\n// <!c> Rule 22.6 (mandatory): The value of a pointer to a FILE shall not be used after the associated stream has been closed\n    //-e449   /* previously deallocated pointer */\n    //-elib(449)\n// </c>\n// </h>\n\n// </h>\n\n// <<< end of configuration section >>>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/ARM/MDK/RTX_CM.uvoptx",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<ProjectOpt xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_optx.xsd\">\n\n  <SchemaVersion>1.0</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Extensions>\n    <cExt>*.c</cExt>\n    <aExt>*.s*; *.src; *.a*</aExt>\n    <oExt>*.obj; *.o</oExt>\n    <lExt>*.lib</lExt>\n    <tExt>*.txt; *.h; *.inc; *.md</tExt>\n    <pExt>*.plm</pExt>\n    <CppX>*.cpp</CppX>\n    <nMigrate>0</nMigrate>\n  </Extensions>\n\n  <DaveTm>\n    <dwLowDateTime>0</dwLowDateTime>\n    <dwHighDateTime>0</dwHighDateTime>\n  </DaveTm>\n\n  <Target>\n    <TargetName>CM0_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM0_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>1</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>0</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM0$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable>C:\\Lint\\lint-nt.exe</LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>63</LntExFlags>\n      <pMisraName>.\\Lint\\MISRA_C_2012_Config.lnt</pMisraName>\n      <pszMrule>MISRA_C_2012_Config</pszMrule>\n      <pSingCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pSingCmds>\n      <pMultCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>CM3_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM3_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>0</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM))</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable>C:\\Lint\\lint-nt.exe</LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>63</LntExFlags>\n      <pMisraName>.\\Lint\\MISRA_C_2012_Config.lnt</pMisraName>\n      <pszMrule>MISRA_C_2012_Config</pszMrule>\n      <pSingCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pSingCmds>\n      <pMultCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>CM4F_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM4F_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>1</uSim>\n        <uTrg>0</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>0</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable>C:\\Lint\\lint-nt.exe</LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>63</LntExFlags>\n      <pMisraName>.\\Lint\\MISRA_C_2012_Config.lnt</pMisraName>\n      <pszMrule>MISRA_C_2012_Config</pszMrule>\n      <pSingCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pSingCmds>\n      <pMultCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MBL_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MBL_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable>C:\\Lint\\lint-nt.exe</LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>63</LntExFlags>\n      <pMisraName>.\\Lint\\MISRA_C_2012_Config.lnt</pMisraName>\n      <pszMrule>MISRA_C_2012_Config</pszMrule>\n      <pSingCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pSingCmds>\n      <pMultCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MBL_NS_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MBL_NS_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable>C:\\Lint\\lint-nt.exe</LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>63</LntExFlags>\n      <pMisraName>.\\Lint\\MISRA_C_2012_Config.lnt</pMisraName>\n      <pszMrule>MISRA_C_2012_Config</pszMrule>\n      <pSingCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pSingCmds>\n      <pMultCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MML_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MML_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable>C:\\Lint\\lint-nt.exe</LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>63</LntExFlags>\n      <pMisraName>.\\Lint\\MISRA_C_2012_Config.lnt</pMisraName>\n      <pszMrule>MISRA_C_2012_Config</pszMrule>\n      <pSingCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pSingCmds>\n      <pMultCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MML_NS_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MML_NS_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable>C:\\Lint\\lint-nt.exe</LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>63</LntExFlags>\n      <pMisraName>.\\Lint\\MISRA_C_2012_Config.lnt</pMisraName>\n      <pszMrule>MISRA_C_2012_Config</pszMrule>\n      <pSingCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pSingCmds>\n      <pMultCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MML_SP_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MML_SP_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable>C:\\Lint\\lint-nt.exe</LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>63</LntExFlags>\n      <pMisraName>.\\Lint\\MISRA_C_2012_Config.lnt</pMisraName>\n      <pszMrule>MISRA_C_2012_Config</pszMrule>\n      <pSingCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pSingCmds>\n      <pMultCmds>-esym(526,__builtin_*)\n-esym(628,__builtin_*)\n-esym(718,__builtin_*)\n-esym(746,__builtin_*)\n-sem(__CLZ, pure)\n+doffsetof(t,m)=((size_t)&amp;((t*)0)-&gt;m)\n-emacro((413,923,9078),offsetof)\n-emacro(835,osRtxConfigPrivilegedMode)\n--uEVR_RTX_DISABLE\n</pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MML_SP_NS_LE</TargetName>\n    <ToolsetNumber>0x4</ToolsetNumber>\n    <ToolsetName>ARM-ADS</ToolsetName>\n    <TargetOption>\n      <CLKADS>12000000</CLKADS>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>79</PageWidth>\n        <PageLength>66</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MML_SP_NS_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        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</OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          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  <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv8mbl.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mbl.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  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       <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy CM3_LE\\RTX_CM3.lib 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<Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n           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<Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>7</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n           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<GroupName>Configuration</GroupName>\n          <Files>\n            <File>\n              <FileName>RTX_Config.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\..\\RTX_Config.h</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Core</GroupName>\n          <Files>\n            <File>\n              <FileName>rtx_kernel.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_kernel.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_thread.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_thread.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_delay.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_delay.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evflags.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evflags.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_memory.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mempool.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mempool.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_msgqueue.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_msgqueue.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_system.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_system.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evr.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evr.c</FilePath>\n            </File>\n            <File>\n              <FileName>os_systick.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\..\\Source\\os_systick.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Handlers</GroupName>\n          <Files>\n            <File>\n              <FileName>irq_armv6m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv6m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv7m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv7m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv8mbl.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mbl.S</FilePath>\n            </File>\n            <File>\n              <FileName>irq_armv8mml.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mml.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>ARMv8MBL_NS_LE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>\n      <uAC6>1</uAC6>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMv8MBL</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.9.0</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE(\"ARMV8MBL\") CLOCK(12000000) ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMv8MBL$Device\\ARM\\ARMv8MBL\\Include\\ARMv8MBL.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMv8MBL$Device\\ARM\\SVD\\ARMv8MBL.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\ARMv8MBL_NS_LE\\</OutputDirectory>\n          <OutputName>RTX_V8MBN</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>1</BrowseInformation>\n          <ListingPath>.\\ARMv8MBL_NS_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy ARMv8MBL_NS_LE\\RTX_V8MBN.lib ..\\.</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName></SimDllName>\n          <SimDllArguments></SimDllArguments>\n          <SimDlgDll></SimDlgDll>\n          <SimDlgDllArguments></SimDlgDllArguments>\n          <TargetDllName>SARMV8M.DLL</TargetDllName>\n          <TargetDllArguments></TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pV8MBL</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>4096</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2V8M.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>1</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"ARMV8MBL\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <RvdsMve>0</RvdsMve>\n            <RvdsCdeCp>0</RvdsCdeCp>\n            <nBranchProt>0</nBranchProt>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>0</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>0</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>7</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>3</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>EVR_RTX_DISABLE DOMAIN_NS=1</Define>\n              <Undefine></Undefine>\n              <IncludePath>..\\..\\..\\Library;..\\..\\..\\Include;..\\..\\..\\..\\Include</IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>DOMAIN_NS=1</Define>\n              <Undefine></Undefine>\n              <IncludePath>.;..\\..\\..\\Library;..\\..\\..\\Include</IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Configuration</GroupName>\n          <Files>\n            <File>\n              <FileName>RTX_Config.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\..\\RTX_Config.h</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Core</GroupName>\n          <Files>\n            <File>\n              <FileName>rtx_kernel.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_kernel.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_thread.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_thread.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_delay.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_delay.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evflags.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evflags.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_memory.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mempool.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mempool.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_msgqueue.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_msgqueue.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_system.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_system.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evr.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evr.c</FilePath>\n            </File>\n            <File>\n              <FileName>os_systick.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\..\\Source\\os_systick.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Handlers</GroupName>\n          <Files>\n            <File>\n              <FileName>irq_armv6m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv6m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv7m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv7m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv8mbl.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mbl.S</FilePath>\n            </File>\n            <File>\n              <FileName>irq_armv8mml.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mml.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>ARMv8MML_LE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>\n      <uAC6>1</uAC6>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMv8MML</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.9.0</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE(\"ARMV8MML\") CLOCK(12000000) ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMv8MML$Device\\ARM\\ARMv8MML\\Include\\ARMv8MML.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMv8MML$Device\\ARM\\SVD\\ARMv8MML.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\ARMv8MML_LE\\</OutputDirectory>\n          <OutputName>RTX_V8MM</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>1</BrowseInformation>\n          <ListingPath>.\\ARMv8MML_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy ARMv8MML_LE\\RTX_V8MM.lib ..\\.</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName></SimDllName>\n          <SimDllArguments></SimDllArguments>\n          <SimDlgDll></SimDlgDll>\n          <SimDlgDllArguments></SimDlgDllArguments>\n          <TargetDllName>SARMV8M.DLL</TargetDllName>\n          <TargetDllArguments></TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pV8MML</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>4096</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2V8M.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>1</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"ARMV8MML\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <RvdsMve>0</RvdsMve>\n            <RvdsCdeCp>0</RvdsCdeCp>\n            <nBranchProt>0</nBranchProt>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>0</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>0</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>7</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>3</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>EVR_RTX_DISABLE</Define>\n              <Undefine></Undefine>\n              <IncludePath>..\\..\\..\\Library;..\\..\\..\\Include;..\\..\\..\\..\\Include</IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath>.;..\\..\\..\\Library;..\\..\\..\\Include</IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Configuration</GroupName>\n          <Files>\n            <File>\n              <FileName>RTX_Config.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\..\\RTX_Config.h</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Core</GroupName>\n          <Files>\n            <File>\n              <FileName>rtx_kernel.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_kernel.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_thread.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_thread.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_delay.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_delay.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evflags.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evflags.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_memory.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mempool.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mempool.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_msgqueue.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_msgqueue.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_system.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_system.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evr.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evr.c</FilePath>\n            </File>\n            <File>\n              <FileName>os_systick.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\..\\Source\\os_systick.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Handlers</GroupName>\n          <Files>\n            <File>\n              <FileName>irq_armv6m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv6m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv7m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv7m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv8mbl.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mbl.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv8mml.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mml.S</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>ARMv8MML_NS_LE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>\n      <uAC6>1</uAC6>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMv8MML</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.9.0</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE(\"ARMV8MML\") CLOCK(12000000) ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMv8MML$Device\\ARM\\ARMv8MML\\Include\\ARMv8MML.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMv8MML$Device\\ARM\\SVD\\ARMv8MML.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\ARMv8MML_NS_LE\\</OutputDirectory>\n          <OutputName>RTX_V8MMN</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>1</BrowseInformation>\n          <ListingPath>.\\ARMv8MML_NS_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy ARMv8MML_NS_LE\\RTX_V8MMN.lib ..\\.</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName></SimDllName>\n          <SimDllArguments></SimDllArguments>\n          <SimDlgDll></SimDlgDll>\n          <SimDlgDllArguments></SimDlgDllArguments>\n          <TargetDllName>SARMV8M.DLL</TargetDllName>\n          <TargetDllArguments></TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pV8MML</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>4096</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2V8M.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>1</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"ARMV8MML\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <RvdsMve>0</RvdsMve>\n            <RvdsCdeCp>0</RvdsCdeCp>\n            <nBranchProt>0</nBranchProt>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>0</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>0</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>7</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>3</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>EVR_RTX_DISABLE DOMAIN_NS=1</Define>\n              <Undefine></Undefine>\n              <IncludePath>..\\..\\..\\Library;..\\..\\..\\Include;..\\..\\..\\..\\Include</IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>DOMAIN_NS=1</Define>\n              <Undefine></Undefine>\n              <IncludePath>.;..\\..\\..\\Library;..\\..\\..\\Include</IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Configuration</GroupName>\n          <Files>\n            <File>\n              <FileName>RTX_Config.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\..\\RTX_Config.h</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Core</GroupName>\n          <Files>\n            <File>\n              <FileName>rtx_kernel.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_kernel.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_thread.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_thread.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_delay.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_delay.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evflags.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evflags.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_memory.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mempool.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mempool.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_msgqueue.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_msgqueue.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_system.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_system.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evr.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evr.c</FilePath>\n            </File>\n            <File>\n              <FileName>os_systick.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\..\\Source\\os_systick.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Handlers</GroupName>\n          <Files>\n            <File>\n              <FileName>irq_armv6m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv6m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv7m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv7m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv8mbl.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mbl.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv8mml.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mml.S</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>ARMv8MML_SP_LE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>\n      <uAC6>1</uAC6>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMv8MML_SP</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.9.0</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE(\"ARMV8MML\") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMv8MML_SP$Device\\ARM\\ARMv8MML\\Include\\ARMv8MML_SP.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMv8MML_SP$Device\\ARM\\SVD\\ARMv8MML.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\ARMv8MML_SP_LE\\</OutputDirectory>\n          <OutputName>RTX_V8MMF</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>1</BrowseInformation>\n          <ListingPath>.\\ARMv8MML_SP_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy ARMv8MML_SP_LE\\RTX_V8MMF.lib ..\\.</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName></SimDllName>\n          <SimDllArguments></SimDllArguments>\n          <SimDlgDll></SimDlgDll>\n          <SimDlgDllArguments></SimDlgDllArguments>\n          <TargetDllName>SARMV8M.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pV8MML</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>4096</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2V8M.DLL</Flash2>\n          <Flash3></Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>1</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>0</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>1</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>1</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"ARMV8MML\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>2</RvdsVP>\n            <RvdsMve>0</RvdsMve>\n            <RvdsCdeCp>0</RvdsCdeCp>\n            <nBranchProt>0</nBranchProt>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>0</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n     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<StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>7</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>1</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>0</uC99>\n            <uGnu>0</uGnu>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>3</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define>EVR_RTX_DISABLE</Define>\n              <Undefine></Undefine>\n              <IncludePath>..\\..\\..\\Library;..\\..\\..\\Include;..\\..\\..\\..\\Include</IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <thumb>1</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <ClangAsOpt>1</ClangAsOpt>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath>.;..\\..\\..\\Library;..\\..\\..\\Include</IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile></ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc></Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Configuration</GroupName>\n          <Files>\n            <File>\n              <FileName>RTX_Config.h</FileName>\n              <FileType>5</FileType>\n              <FilePath>..\\..\\RTX_Config.h</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Core</GroupName>\n          <Files>\n            <File>\n              <FileName>rtx_kernel.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_kernel.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_thread.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_thread.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_delay.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_delay.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_timer.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_timer.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evflags.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evflags.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mutex.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mutex.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_semaphore.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_semaphore.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_memory.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_memory.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_mempool.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_mempool.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_msgqueue.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_msgqueue.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_system.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_system.c</FilePath>\n            </File>\n            <File>\n              <FileName>rtx_evr.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\Source\\rtx_evr.c</FilePath>\n            </File>\n            <File>\n              <FileName>os_systick.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>..\\..\\..\\..\\Source\\os_systick.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Handlers</GroupName>\n          <Files>\n            <File>\n              <FileName>irq_armv6m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv6m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv7m.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv7m.S</FilePath>\n              <FileOption>\n                <CommonProperty>\n                  <UseCPPCompiler>2</UseCPPCompiler>\n                  <RVCTCodeConst>0</RVCTCodeConst>\n                  <RVCTZI>0</RVCTZI>\n                  <RVCTOtherData>0</RVCTOtherData>\n                  <ModuleSelection>0</ModuleSelection>\n                  <IncludeInBuild>0</IncludeInBuild>\n                  <AlwaysBuild>2</AlwaysBuild>\n                  <GenerateAssemblyFile>2</GenerateAssemblyFile>\n                  <AssembleAssemblyFile>2</AssembleAssemblyFile>\n                  <PublicsOnly>2</PublicsOnly>\n                  <StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n             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<StopOnExitCode>11</StopOnExitCode>\n                  <CustomArgument></CustomArgument>\n                  <IncludeLibraryModules></IncludeLibraryModules>\n                  <ComprImg>1</ComprImg>\n                </CommonProperty>\n                <FileArmAds>\n                  <Aads>\n                    <interw>2</interw>\n                    <Ropi>2</Ropi>\n                    <Rwpi>2</Rwpi>\n                    <thumb>2</thumb>\n                    <SplitLS>2</SplitLS>\n                    <SwStkChk>2</SwStkChk>\n                    <NoWarn>2</NoWarn>\n                    <uSurpInc>2</uSurpInc>\n                    <useXO>2</useXO>\n                    <ClangAsOpt>0</ClangAsOpt>\n                    <VariousControls>\n                      <MiscControls></MiscControls>\n                      <Define></Define>\n                      <Undefine></Undefine>\n                      <IncludePath></IncludePath>\n                    </VariousControls>\n                  </Aads>\n                </FileArmAds>\n              </FileOption>\n            </File>\n            <File>\n              <FileName>irq_armv8mml.S</FileName>\n              <FileType>2</FileType>\n              <FilePath>..\\..\\..\\Source\\GCC\\irq_armv8mml.S</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>::CMSIS</GroupName>\n        </Group>\n      </Groups>\n    </Target>\n    <Target>\n      <TargetName>ARMv8MML_SP_NS_LE</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>6190000::V6.19::ARMCLANG</pCCUsed>\n      <uAC6>1</uAC6>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMv8MML_SP</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.9.0</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE(\"ARMV8MML\") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMv8MML_SP$Device\\ARM\\ARMv8MML\\Include\\ARMv8MML_SP.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMv8MML_SP$Device\\ARM\\SVD\\ARMv8MML.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\ARMv8MML_SP_NS_LE\\</OutputDirectory>\n          <OutputName>RTX_V8MMFN</OutputName>\n          <CreateExecutable>0</CreateExecutable>\n          <CreateLib>1</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>1</BrowseInformation>\n          <ListingPath>.\\ARMv8MML_SP_NS_LE\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>1</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy ARMv8MML_SP_NS_LE\\RTX_V8MMFN.lib ..\\.</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>1</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName></SimDllName>\n          <SimDllArguments></SimDllArguments>\n          <SimDlgDll></SimDlgDll>\n          <SimDlgDllArguments></SimDlgDllArguments>\n          <TargetDllName>SARMV8M.DLL</TargetDllName>\n          <TargetDllArguments> -MPU</TargetDllArguments>\n          <TargetDlgDll>TCM.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pV8MML</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n        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  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/GCC/MDK/RTX_CM.uvoptx",
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<sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>0</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM0$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>CM3_LE</TargetName>\n    <ToolsetNumber>0x3</ToolsetNumber>\n    <ToolsetName>ARM-GNU</ToolsetName>\n    <TargetOption>\n      <CLKARM>12000000</CLKARM>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>120</PageWidth>\n        <PageLength>65</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM3_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>0</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>CM4F_LE</TargetName>\n    <ToolsetNumber>0x3</ToolsetNumber>\n    <ToolsetName>ARM-GNU</ToolsetName>\n    <TargetOption>\n      <CLKARM>12000000</CLKARM>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>120</PageWidth>\n        <PageLength>65</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\CM4F_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>0</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM4_FP$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MBL_LE</TargetName>\n    <ToolsetNumber>0x3</ToolsetNumber>\n    <ToolsetName>ARM-GNU</ToolsetName>\n    <TargetOption>\n      <CLKARM>12000000</CLKARM>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>120</PageWidth>\n        <PageLength>65</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MBL_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MBL_NS_LE</TargetName>\n    <ToolsetNumber>0x3</ToolsetNumber>\n    <ToolsetName>ARM-GNU</ToolsetName>\n    <TargetOption>\n      <CLKARM>12000000</CLKARM>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>120</PageWidth>\n        <PageLength>65</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MBL_NS_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MML_LE</TargetName>\n    <ToolsetNumber>0x3</ToolsetNumber>\n    <ToolsetName>ARM-GNU</ToolsetName>\n    <TargetOption>\n      <CLKARM>12000000</CLKARM>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>120</PageWidth>\n        <PageLength>65</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MML_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MML_NS_LE</TargetName>\n    <ToolsetNumber>0x3</ToolsetNumber>\n    <ToolsetName>ARM-GNU</ToolsetName>\n    <TargetOption>\n      <CLKARM>12000000</CLKARM>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>120</PageWidth>\n        <PageLength>65</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MML_NS_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MML_SP_LE</TargetName>\n    <ToolsetNumber>0x3</ToolsetNumber>\n    <ToolsetName>ARM-GNU</ToolsetName>\n    <TargetOption>\n      <CLKARM>12000000</CLKARM>\n      <OPTTT>\n        <gFlags>1</gFlags>\n        <BeepAtEnd>1</BeepAtEnd>\n        <RunSim>0</RunSim>\n        <RunTarget>1</RunTarget>\n        <RunAbUc>0</RunAbUc>\n      </OPTTT>\n      <OPTHX>\n        <HexSelection>1</HexSelection>\n        <FlashByte>65535</FlashByte>\n        <HexRangeLowAddress>0</HexRangeLowAddress>\n        <HexRangeHighAddress>0</HexRangeHighAddress>\n        <HexOffset>0</HexOffset>\n      </OPTHX>\n      <OPTLEX>\n        <PageWidth>120</PageWidth>\n        <PageLength>65</PageLength>\n        <TabStop>8</TabStop>\n        <ListingPath>.\\ARMv8MML_SP_LE\\</ListingPath>\n      </OPTLEX>\n      <ListingPage>\n        <CreateCListing>1</CreateCListing>\n        <CreateAListing>1</CreateAListing>\n        <CreateLListing>1</CreateLListing>\n        <CreateIListing>0</CreateIListing>\n        <AsmCond>1</AsmCond>\n        <AsmSymb>1</AsmSymb>\n        <AsmXref>0</AsmXref>\n        <CCond>1</CCond>\n        <CCode>0</CCode>\n        <CListInc>0</CListInc>\n        <CSymb>0</CSymb>\n        <LinkerCodeListing>0</LinkerCodeListing>\n      </ListingPage>\n      <OPTXL>\n        <LMap>1</LMap>\n        <LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>0</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>13</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2V8M.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2V8M</Key>\n          <Name>UL2V8M(-S0 -C0 -P0  -FC1000 -FD20000000</Name>\n        </SetRegEntry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\\ARM\\Flash\\NEW_DEVICE.FLM)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Target>\n    <TargetName>ARMv8MML_SP_NS_LE</TargetName>\n    <ToolsetNumber>0x3</ToolsetNumber>\n    <ToolsetName>ARM-GNU</ToolsetName>\n    <TargetOption>\n      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<AssembleAssemblyFile>2</AssembleAssemblyFile>\n              <PublicsOnly>2</PublicsOnly>\n              <StopOnExitCode>11</StopOnExitCode>\n              <CustomArgument></CustomArgument>\n              <IncludeLibraryModules></IncludeLibraryModules>\n              <ComprImg>1</ComprImg>\n            </CommonProperty>\n            <GroupArm>\n              <Carm>\n                <arpcs>2</arpcs>\n                <stkchk>2</stkchk>\n                <reentr>2</reentr>\n                <interw>2</interw>\n                <bigend>2</bigend>\n                <Strict>0</Strict>\n                <Optim>0</Optim>\n                <wLevel>0</wLevel>\n                <uThumb>2</uThumb>\n                <VariousControls>\n                  <MiscControls></MiscControls>\n                  <Define></Define>\n                  <Undefine></Undefine>\n                  <IncludePath></IncludePath>\n                </VariousControls>\n              </Carm>\n              <Aarm>\n                <bBE>2</bBE>\n                <interw>2</interw>\n                <VariousControls>\n                  <MiscControls></MiscControls>\n                  <Define></Define>\n                  <Undefine></Undefine>\n                  <IncludePath></IncludePath>\n                </VariousControls>\n              </Aarm>\n            </GroupArm>\n          </GroupOption>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis/>\n    <components>\n      <component Cclass=\"CMSIS\" Cgroup=\"CORE\" Cvendor=\"ARM\" Cversion=\"5.0.0\" condition=\"Cortex-M ARMv8-M Device\">\n        <package name=\"CMSIS\" schemaVersion=\"1.3\" url=\"http://www.keil.com/pack/\" vendor=\"ARM\" version=\"5.0.0-Beta4\"/>\n        <targetInfos>\n          <targetInfo name=\"ARMv8MBL_LE\"/>\n          <targetInfo name=\"ARMv8MBL_NS_LE\"/>\n          <targetInfo name=\"ARMv8MML_LE\"/>\n          <targetInfo name=\"ARMv8MML_NS_LE\"/>\n          <targetInfo name=\"ARMv8MML_SP_LE\"/>\n          <targetInfo name=\"ARMv8MML_SP_NS_LE\"/>\n          <targetInfo name=\"CM0_LE\"/>\n          <targetInfo name=\"CM3_LE\"/>\n          <targetInfo name=\"CM4F_LE\"/>\n        </targetInfos>\n      </component>\n    </components>\n    <files/>\n  </RTE>\n\n  <LayerInfo>\n    <Layers>\n      <Layer>\n        <LayName>RTX_CM</LayName>\n        <LayPrjMark>1</LayPrjMark>\n      </Layer>\n    </Layers>\n  </LayerInfo>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/IAR/IDE/RTE_Components.h",
    "content": "\n/*\n * Auto generated Run-Time-Environment Component Configuration File\n *      *** Do not modify ! ***\n *\n * Project: 'RTX_CM' \n */\n\n#ifndef RTE_COMPONENTS_H\n#define RTE_COMPONENTS_H\n\n\n#endif /* RTE_COMPONENTS_H */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/IAR/IDE/RTX_CM.ewp",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<project>\n    <fileVersion>3</fileVersion>\n    <configuration>\n        <name>CM0</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>CM0\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>CM0\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>CM0\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>CM0\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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<state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>34</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    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<name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                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<name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    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<name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMCM0\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    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<name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n         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<name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n    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<option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_CM0.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>CM3</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>CM3\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>CM3\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>CM3\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>CM3\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>38</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>38</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>38</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>CM3</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMCM3.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMCM3\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_CM3.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>CM4F</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>CM4F\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>CM4F\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>CM4F\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>CM4F\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>39</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>39</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>4</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>39</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>CM4F</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMCM4_FP.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMCM4\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_CM4F.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V8MB</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V8MB\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V8MB\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V8MB\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V8MB\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>58</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>58</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>58</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V8MB</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv8MBL.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv8MBL\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V8MB.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V8MBN</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V8MBN\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V8MBN\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V8MBN\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V8MBN\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>58</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>58</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>58</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V8MBN</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv8MBL.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                    <state>DOMAIN_NS=1</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv8MBL\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V8MBN.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V8MM</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V8MM\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V8MM\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V8MM\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V8MM\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V8MM</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv8MML.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv8MML\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V8MM.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V8MMN</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V8MMN\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V8MMN\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V8MMN\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V8MMN\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V8MMN</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv8MML.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                    <state>DOMAIN_NS=1</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv8MML\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V8MMN.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V8MMF</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V8MMF\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V8MMF\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V8MMF\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V8MMF\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>6</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V8MMF</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv8MML_SP.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv8MML\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V8MMF.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V8MMFN</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V8MMFN\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V8MMFN\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V8MMFN\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V8MMFN\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>6</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>59</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V8MMFN</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv8MML_SP.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                    <state>DOMAIN_NS=1</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv8MML\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V8MMFN.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V81MM</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V81MM\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V81MM\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V81MM\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V81MM\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V81MM\\</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv81MML_DSP_DP_MVE_FP.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv81MML\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    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       <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n     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<name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V81MM.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V81MMN</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V81MMN\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V81MMN\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V81MMN\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V81MMN\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V81MMN\\</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv81MML_DSP_DP_MVE_FP.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                    <state>DOMAIN_NS=1</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv81MML\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V81MMN.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V81MMF</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V81MMF\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V81MMF\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V81MMF\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V81MMF\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>7</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V81MMF\\</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv81MML_DSP_DP_MVE_FP.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv81MML\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V81MMF.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <configuration>\n        <name>V81MMFN</name>\n        <toolchain>\n            <name>ARM</name>\n        </toolchain>\n        <debug>0</debug>\n        <settings>\n            <name>General</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <version>34</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>BrowseInfoPath</name>\n                    <state>V81MMFN\\BrowseInfo</state>\n                </option>\n                <option>\n                    <name>ExePath</name>\n                    <state>V81MMFN\\Exe</state>\n                </option>\n                <option>\n                    <name>ObjPath</name>\n                    <state>V81MMFN\\Obj</state>\n                </option>\n                <option>\n                    <name>ListPath</name>\n                    <state>V81MMFN\\List</state>\n                </option>\n                <option>\n                    <name>GEndianMode</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>Input description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>Output description</name>\n                    <state>Automatic choice of formatter, without multibyte support.</state>\n                </option>\n                <option>\n                    <name>GOutputBinary</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGCoreOrChip</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelect</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibSelectSlave</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>RTDescription</name>\n                    <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>\n                </option>\n                <option>\n                    <name>OGProductVersion</name>\n                    <state>7.80.2.11970</state>\n                </option>\n                <option>\n                    <name>OGLastSavedByProductVersion</name>\n                    <state>9.20.1.43525</state>\n                </option>\n                <option>\n                    <name>OGChipSelectEditMenu</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>GenLowLevelInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GEndianModeBE</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGBufferedTerminalOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenStdoutInterface</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>RTConfigPath2</name>\n                    <state>$TOOLKIT_DIR$\\inc\\c\\DLib_Config_Normal.h</state>\n                </option>\n                <option>\n                    <name>GBECoreSlave</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>OGUseCmsis</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGUseCmsisDspLib</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GRuntimeLibThreads</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CoreVariant</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>GFPUDeviceSlave</name>\n                    <state>Default\tNone</state>\n                </option>\n                <option>\n                    <name>FPU2</name>\n                    <version>0</version>\n                    <state>7</state>\n                </option>\n                <option>\n                    <name>NrRegs</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>NEON</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GFPUCoreSlave2</name>\n                    <version>31</version>\n                    <state>61</state>\n                </option>\n                <option>\n                    <name>OGCMSISPackSelectDevice</name>\n                </option>\n                <option>\n                    <name>OgLibHeap</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGLibAdditionalLocale</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGPrintfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfVariant</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OGScanfMultibyteSupport</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>GenLocaleTags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>GenLocaleDisplayOnly</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DSPExtension</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>TrustZone</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>TrustZoneModes</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OGAarch64Abi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OG_32_64Device</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>BuildFilesPath</name>\n                    <state>V81MMFN\\</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>ICCARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>37</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>CCDefines</name>\n                    <state>NDEBUG</state>\n                    <state>CMSIS_device_header=\"ARMv81MML_DSP_DP_MVE_FP.h\"</state>\n                    <state>EVR_RTX_DISABLE</state>\n                    <state>DOMAIN_NS=1</state>\n                </option>\n                <option>\n                    <name>CCPreprocFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocComments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPreprocLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMnemonics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListCMessages</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCListAssSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagSuppress</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagRemark</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagWarning</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCDiagError</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCAllowList</name>\n                    <version>1</version>\n                    <state>11111110</state>\n                </option>\n                <option>\n                    <name>CCDebugInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IEndianMode</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IExtraOptionsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCLangConformance</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCSignedPlainChar</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCRequirePrototypes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCDiagWarnAreErr</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCompilerRuntimeInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>CCLibConfigHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CCIncludePath2</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\Include</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\Core\\Include</state>\n                    <state>$PROJ_DIR$</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\..\\..\\..\\Device\\ARM\\ARMv81MML\\Include</state>\n                </option>\n                <option>\n                    <name>CCStdIncCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCCodeSection</name>\n                    <state>.text</state>\n                </option>\n                <option>\n                    <name>IProcessorMode2</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCOptLevel</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCOptStrategy</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptLevelSlave</name>\n                    <state>3</state>\n                </option>\n                <option>\n                    <name>CCPosIndRopi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndRwpi</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCPosIndNoDynInit</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccLang</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCDialect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccAllowVLA</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccStaticDestr</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccCppInlineSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IccFloatSemantics</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptimizationNoSizeConstraints</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCOptStrategySlave</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCGuardCalls</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncSource</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CCEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccExceptions2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IccRTTI2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OICompilerExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CCStackProtection</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>AARM</name>\n            <archiveVersion>2</archiveVersion>\n            <data>\n                <version>11</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>AObjPrefix</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AEndian</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>ACaseSensitivity</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacroChars</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnWhat</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AWarnOne</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange1</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AWarnRange2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>ADebug</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AltRegisterNames</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ADefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AList</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AListHeader</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AListing</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>Includes</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacDefs</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MacExps</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>MacExec</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OnlyAssed</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>MultiLine</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLengthCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PageLength</name>\n                    <state>80</state>\n                </option>\n                <option>\n                    <name>TabSpacing</name>\n                    <state>8</state>\n                </option>\n                <option>\n                    <name>AXRef</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDefines</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefInternal</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AXRefDual</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AFpuProcessor</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>AOutputFile</name>\n                    <state>$FILE_BNAME$.o</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsCheck</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>ALimitErrorsEdit</name>\n                    <state>100</state>\n                </option>\n                <option>\n                    <name>AIgnoreStdInclude</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AUserIncludes</name>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Library</state>\n                    <state>$PROJ_DIR$\\..\\..\\..\\Include</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsCheckV2</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>AExtraOptionsV2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>AsmNoLiteralPool</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>PreInclude</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>OBJCOPY</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>1</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>OOCOutputFormat</name>\n                    <version>3</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OCOutputOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>OOCOutputFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>OOCCommandLineProducer</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>OOCObjCopyEnable</name>\n                    <state>0</state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>CUSTOM</name>\n            <archiveVersion>3</archiveVersion>\n            <data>\n                <extensions></extensions>\n                <cmdline></cmdline>\n                <hasPrio>0</hasPrio>\n                <buildSequence>inputOutputBased</buildSequence>\n            </data>\n        </settings>\n        <settings>\n            <name>BUILDACTION</name>\n            <archiveVersion>1</archiveVersion>\n            <data>\n                <prebuild></prebuild>\n                <postbuild></postbuild>\n            </data>\n        </settings>\n        <settings>\n            <name>ILINK</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>26</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IlinkLibIOConfig</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkInputFileSlave</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOutputFile</name>\n                    <state>RTX_CM.out</state>\n                </option>\n                <option>\n                    <name>IlinkDebugInfoEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkKeepSymbols</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkConfigDefines</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkMapFile</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogFile</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInitialization</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogModule</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogSection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogVeneer</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfOverride</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile</name>\n                    <state>lnk0t.icf</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFileSlave</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEnableRemarks</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkSuppressDiags</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsRem</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsWarn</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkTreatAsErr</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkWarningsAreErrors</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkUseExtraOptions</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkExtraOptions</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLowLevelInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAutoLibEnable</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkAdditionalLibs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkOverrideProgramEntryLabel</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabelSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkProgramEntryLabel</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>DoFill</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>FillerByte</name>\n                    <state>0xFF</state>\n                </option>\n                <option>\n                    <name>FillerStart</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>FillerEnd</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>CrcSize</name>\n                    <version>0</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcAlign</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcPoly</name>\n                    <state>0x11021</state>\n                </option>\n                <option>\n                    <name>CrcCompl</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcBitOrder</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>CrcInitialValue</name>\n                    <state>0x0</state>\n                </option>\n                <option>\n                    <name>DoCrc</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkBE8Slave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkBufferedTerminalOutput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkStdoutInterfaceSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcFullSize</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIElfToolPostProcess</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogAutoLibSelect</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogRedirSymbols</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogUnusedFragments</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcReverseByteOrder</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCrcUseAsInput</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptInline</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsAllow</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptExceptionsForce</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkCmsis</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptMergeDuplSections</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkOptUseVfe</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkOptForceVfe</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackAnalysisEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkStackControlFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkStackCallGraphFile</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>CrcAlgorithm</name>\n                    <version>1</version>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>CrcUnitSize</name>\n                    <version>0</version>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkThreadsSlave</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLogCallGraph</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkIcfFile_AltDefault</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkEncInput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutput</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkEncOutputBom</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkHeapSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkLocaleSelect</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkTrustzoneImportLibraryOut</name>\n                    <state>###Unitialized###</state>\n                </option>\n                <option>\n                    <name>OILinkExtraOption</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryFile2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySymbol2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinarySegment2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkRawBinaryAlign2</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IlinkLogCrtRoutineSelection</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogFragmentInfo</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogInlining</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkLogMerging</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkDemangle</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFileEnable</name>\n                    <state>0</state>\n                </option>\n                <option>\n                    <name>IlinkWrapperFile</name>\n                    <state></state>\n                </option>\n            </data>\n        </settings>\n        <settings>\n            <name>IARCHIVE</name>\n            <archiveVersion>0</archiveVersion>\n            <data>\n                <version>0</version>\n                <wantNonLocal>1</wantNonLocal>\n                <debug>0</debug>\n                <option>\n                    <name>IarchiveInputs</name>\n                    <state></state>\n                </option>\n                <option>\n                    <name>IarchiveOverride</name>\n                    <state>1</state>\n                </option>\n                <option>\n                    <name>IarchiveOutput</name>\n                    <state>$PROJ_DIR$\\..\\RTX_V81MMFN.a</state>\n                </option>\n            </data>\n        </settings>\n    </configuration>\n    <group>\n        <name>Core</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\..\\Source\\os_systick.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_delay.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_evflags.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_evr.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_kernel.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_memory.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_mempool.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_msgqueue.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_mutex.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_semaphore.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_system.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_thread.c</name>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\rtx_timer.c</name>\n        </file>\n    </group>\n    <group>\n        <name>Handlers</name>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\IAR\\irq_armv6m.s</name>\n            <excluded>\n                <configuration>CM3</configuration>\n                <configuration>CM4F</configuration>\n                <configuration>V8MB</configuration>\n                <configuration>V8MBN</configuration>\n                <configuration>V8MM</configuration>\n                <configuration>V8MMN</configuration>\n                <configuration>V8MMF</configuration>\n                <configuration>V8MMFN</configuration>\n                <configuration>V81MM</configuration>\n                <configuration>V81MMN</configuration>\n                <configuration>V81MMF</configuration>\n                <configuration>V81MMFN</configuration>\n            </excluded>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\IAR\\irq_armv7m.s</name>\n            <excluded>\n                <configuration>CM0</configuration>\n                <configuration>V8MB</configuration>\n                <configuration>V8MBN</configuration>\n                <configuration>V8MM</configuration>\n                <configuration>V8MMN</configuration>\n                <configuration>V8MMF</configuration>\n                <configuration>V8MMFN</configuration>\n                <configuration>V81MM</configuration>\n                <configuration>V81MMN</configuration>\n                <configuration>V81MMF</configuration>\n                <configuration>V81MMFN</configuration>\n            </excluded>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\IAR\\irq_armv8mbl.s</name>\n            <excluded>\n                <configuration>CM0</configuration>\n                <configuration>CM3</configuration>\n                <configuration>CM4F</configuration>\n                <configuration>V8MM</configuration>\n                <configuration>V8MMN</configuration>\n                <configuration>V8MMF</configuration>\n                <configuration>V8MMFN</configuration>\n                <configuration>V81MM</configuration>\n                <configuration>V81MMN</configuration>\n                <configuration>V81MMF</configuration>\n                <configuration>V81MMFN</configuration>\n            </excluded>\n        </file>\n        <file>\n            <name>$PROJ_DIR$\\..\\..\\..\\Source\\IAR\\irq_armv8mml.s</name>\n            <excluded>\n                <configuration>CM0</configuration>\n                <configuration>CM3</configuration>\n                <configuration>CM4F</configuration>\n                <configuration>V8MB</configuration>\n                <configuration>V8MBN</configuration>\n            </excluded>\n        </file>\n    </group>\n</project>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/IAR/IDE/RTX_CM.eww",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<workspace>\n    <project>\n        <path>$WS_DIR$\\RTX_CM.ewp</path>\n    </project>\n    <batchBuild>\n        <batchDefinition>\n            <name>RTX_CM</name>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>CM0</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>CM3</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>CM4F</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V8MB</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V8MBN</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V8MM</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V8MMF</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V8MMFN</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V8MMN</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V81MM</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V81MMF</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V81MMFN</configuration>\n            </member>\n            <member>\n                <project>RTX_CM</project>\n                <configuration>V81MMN</configuration>\n            </member>\n        </batchDefinition>\n    </batchBuild>\n</workspace>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/RTX_Config.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * $Revision:   V5.6.0\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Library Configuration definitions\n *\n * -----------------------------------------------------------------------------\n */\n \n#ifndef RTX_CONFIG_H_\n#define RTX_CONFIG_H_\n \n//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------\n \n// <h>System Configuration\n// =======================\n \n//   <e>Safety features (Source variant only)\n//   <i> Enables FuSa related features.\n//   <i> Requires RTX Source variant.\n//   <i> Enables:\n//   <i>  - selected features from this group\n//   <i>  - Thread functions: osThreadProtectPrivileged\n#ifndef OS_SAFETY_FEATURES\n#define OS_SAFETY_FEATURES          0\n#endif\n \n//     <q>Safety Class\n//     <i> Threads assigned to lower classes cannot modify higher class threads.\n//     <i> Enables:\n//     <i>  - Object attributes: osSafetyClass\n//     <i>  - Kernel functions: osKernelProtect, osKernelDestroyClass\n//     <i>  - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass\n#ifndef OS_SAFETY_CLASS\n#define OS_SAFETY_CLASS             1\n#endif\n \n//     <q>MPU Protected Zone\n//     <i> Access protection via MPU (Spatial isolation).\n//     <i> Enables:\n//     <i>  - Thread attributes: osThreadZone\n//     <i>  - Thread functions: osThreadGetZone, osThreadTerminateZone\n//     <i>  - Zone Management: osZoneSetup_Callback\n#ifndef OS_EXECUTION_ZONE\n#define OS_EXECUTION_ZONE           1\n#endif\n \n//     <q>Thread Watchdog\n//     <i> Watchdog alerts ensure timing for critical threads (Temporal isolation).\n//     <i> Enables:\n//     <i>  - Thread functions: osThreadFeedWatchdog\n//     <i>  - Handler functions: osWatchdogAlarm_Handler\n#ifndef OS_THREAD_WATCHDOG\n#define OS_THREAD_WATCHDOG          1\n#endif\n \n//     <q>Object Pointer checking\n//     <i> Check object pointer alignment and memory region.\n#ifndef OS_OBJ_PTR_CHECK\n#define OS_OBJ_PTR_CHECK            0\n#endif\n \n//     <q>SVC Function Pointer checking\n//     <i> Check SVC function pointer alignment and memory region.\n//     <i> User needs to define a linker execution region RTX_SVC_VENEERS\n//     <i> containing input sections: rtx_*.o (.text.os.svc.veneer.*)\n#ifndef OS_SVC_PTR_CHECK\n#define OS_SVC_PTR_CHECK            0\n#endif\n \n//   </e>\n \n//   <q>Object Memory usage counters\n//   <i> Enables object memory usage counters (requires RTX source variant).\n#ifndef OS_OBJ_MEM_USAGE\n#define OS_OBJ_MEM_USAGE            0\n#endif\n \n// </h>\n \n// <h>Thread Configuration\n// =======================\n \n//   <q>Stack overrun checking\n//   <i> Enables stack overrun check at thread switch (requires RTX source variant).\n//   <i> Enabling this option increases slightly the execution time of a thread switch.\n#ifndef OS_STACK_CHECK\n#define OS_STACK_CHECK              0\n#endif\n \n// </h>\n \n// <h>Event Recorder Configuration\n// ===============================\n \n//   <h>RTOS Event Generation\n//   <i> Enables event generation for RTX components (requires RTX source variant).\n \n//     <q>Memory Management\n//     <i> Enables Memory Management event generation.\n#ifndef OS_EVR_MEMORY\n#define OS_EVR_MEMORY               1\n#endif\n \n//     <q>Kernel\n//     <i> Enables Kernel event generation.\n#ifndef OS_EVR_KERNEL\n#define OS_EVR_KERNEL               1\n#endif\n \n//     <q>Thread\n//     <i> Enables Thread event generation.\n#ifndef OS_EVR_THREAD\n#define OS_EVR_THREAD               1\n#endif\n \n//     <q>Generic Wait\n//     <i> Enables Generic Wait event generation.\n#ifndef OS_EVR_WAIT\n#define OS_EVR_WAIT                 1\n#endif\n \n//     <q>Thread Flags\n//     <i> Enables Thread Flags event generation.\n#ifndef OS_EVR_THFLAGS\n#define OS_EVR_THFLAGS              1\n#endif\n \n//     <q>Event Flags\n//     <i> Enables Event Flags event generation.\n#ifndef OS_EVR_EVFLAGS\n#define OS_EVR_EVFLAGS              1\n#endif\n \n//     <q>Timer\n//     <i> Enables Timer event generation.\n#ifndef OS_EVR_TIMER\n#define OS_EVR_TIMER                1\n#endif\n \n//     <q>Mutex\n//     <i> Enables Mutex event generation.\n#ifndef OS_EVR_MUTEX\n#define OS_EVR_MUTEX                1\n#endif\n \n//     <q>Semaphore\n//     <i> Enables Semaphore event generation.\n#ifndef OS_EVR_SEMAPHORE\n#define OS_EVR_SEMAPHORE            1\n#endif\n \n//     <q>Memory Pool\n//     <i> Enables Memory Pool event generation.\n#ifndef OS_EVR_MEMPOOL\n#define OS_EVR_MEMPOOL              1\n#endif\n \n//     <q>Message Queue\n//     <i> Enables Message Queue event generation.\n#ifndef OS_EVR_MSGQUEUE\n#define OS_EVR_MSGQUEUE             1\n#endif\n \n//   </h>\n \n// </h>\n \n//------------- <<< end of configuration section >>> ---------------------------\n \n#endif  // RTX_CONFIG_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/build.py",
    "content": "#!/usr/bin/python3\n# -*- coding: utf-8 -*-\n\nfrom enum import Enum\n\nfrom matrix_runner import main, matrix_axis, matrix_action, matrix_command\n\n\n@matrix_axis(\"device\", \"d\", \"Device(s) to be considered.\")\nclass Device(Enum):\n    CM0 = ('CM0', 'CM0_LE')\n    CM3 = ('CM3', 'CM3_LE')\n    CM4F = ('CM4F', 'CM4F_LE')\n    V8MB = ('V8MB', 'ARMv8MBL_LE')\n    V8MBN = ('V8MBN', 'ARMv8MBL_NS_LE')\n    V8MM = ('V8MM', 'ARMv8MML_LE')\n    V8MMF = ('V8MMF', 'ARMv8MML_SP_LE')\n    V8MMFN = ('V8MMFN', 'ARMv8MML_SP_NS_LE')\n    V8MMN = ('V8MMN', 'ARMv8MML_NS_LE')\n\n\n@matrix_axis(\"compiler\", \"c\", \"Compiler(s) to be considered.\")\nclass CompilerAxis(Enum):\n    AC6 = ('AC6', 'ArmCompiler6', 'armclang')\n    GCC = ('GCC',)\n\n    @property\n    def project(self):\n        return {\n            CompilerAxis.AC6: \"ARM/MDK/RTX_CM.uvprojx\",\n            CompilerAxis.GCC: \"GCC/MDK/RTX_CM.uvprojx\"\n        }[self]\n\n\n@matrix_action\ndef build(config, results):\n    \"\"\"Build the selected configurations.\"\"\"\n    yield uvision(config)\n\n\n@matrix_command()\ndef uvision(config):\n    return ['uvision.com',\n            '-r', config.compiler.project,\n            '-t', config.device[1],\n            '-j0']\n\n\nif __name__ == \"__main__\":\n    main()\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/cmsis_os1.c",
    "content": "/*\n * Copyright (c) 2013-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        10. January 2017\n * $Revision:    V1.2\n *\n * Project:      CMSIS-RTOS API V1\n * Title:        cmsis_os_v1.c V1 module file\n *---------------------------------------------------------------------------*/\n\n#include <string.h>\n#include \"cmsis_os.h\"\n\n#if (osCMSIS >= 0x20000U) && !defined(os1_Disable)\n\n\n// Thread\n#if !defined(os1_Disable_Thread)\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {\n\n  if (thread_def == NULL) {\n    return NULL;\n  }\n  return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr);\n}\n#endif\n\n\n// Signals\n\n#if !defined(os1_Disable_Signal)\n\n#define SignalMask ((1U<<osFeature_Signals)-1U)\n\nint32_t osSignalSet (osThreadId thread_id, int32_t signals) {\n  uint32_t flags;\n\n  flags = osThreadFlagsSet(thread_id, (uint32_t)signals);\n  if ((flags & 0x80000000U) != 0U) {\n    return ((int32_t)0x80000000U);\n  }\n  return ((int32_t)(flags & ~((uint32_t)signals)));\n}\n\nint32_t osSignalClear (osThreadId thread_id, int32_t signals) {\n  uint32_t flags;\n\n  if (thread_id != osThreadGetId()) {\n    return ((int32_t)0x80000000U);\n  }\n  flags = osThreadFlagsClear((uint32_t)signals);\n  if ((flags & 0x80000000U) != 0U) {\n    return ((int32_t)0x80000000U);\n  }\n  return ((int32_t)flags);\n}\n\nos_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) {\n  osEvent  event;\n  uint32_t flags;\n\n  if (signals != 0) {\n    flags = osThreadFlagsWait((uint32_t)signals, osFlagsWaitAll, millisec);\n  } else {\n    flags = osThreadFlagsWait(SignalMask,        osFlagsWaitAny, millisec);\n  }\n  if ((flags > 0U) && (flags < 0x80000000U)) {\n    event.status = osEventSignal;\n    event.value.signals = (int32_t)flags;\n  } else {\n    switch ((int32_t)flags) {\n      case osErrorResource:\n        event.status = osOK;\n        break;\n      case osErrorTimeout:\n        event.status = osEventTimeout;\n        break;\n      case osErrorParameter:\n        event.status = osErrorValue;\n        break;\n      default:\n        event.status = (osStatus)flags;\n        break;\n    }\n  }\n  return event;\n}\n\n#endif  // Signal\n\n\n// Timer\n#if !defined(os1_Disable_Timer)\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {\n\n  if (timer_def == NULL) {\n    return NULL;\n  }\n  return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr);\n}\n#endif\n\n\n// Mutex\n#if !defined(os1_Disable_Mutex)\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def) {\n\n  if (mutex_def == NULL) {\n    return NULL;\n  }\n  return osMutexNew(mutex_def);\n}\n#endif\n\n\n// Semaphore\n\n#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) && !defined(os1_Disable_Semaphore)\n\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {\n\n  if (semaphore_def == NULL) {\n    return NULL;\n  }\n  return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def);\n}\n\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {\n  osStatus_t status;\n  uint32_t   count;\n\n  status = osSemaphoreAcquire(semaphore_id, millisec);\n  switch (status) {\n    case osOK:\n      count = osSemaphoreGetCount(semaphore_id);\n      return ((int32_t)count + 1);\n    case osErrorResource:\n    case osErrorTimeout:\n      return 0;\n    default:\n      break;\n  }\n  return -1;\n}\n\n#endif  // Semaphore\n\n\n// Memory Pool\n\n#if (defined(osFeature_Pool) && (osFeature_Pool != 0))&& !defined(os1_Disable_Pool)\n\nosPoolId osPoolCreate (const osPoolDef_t *pool_def) {\n\n  if (pool_def == NULL) {\n    return NULL;\n  }\n  return osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr);\n}\n\nvoid *osPoolAlloc (osPoolId pool_id) {\n  return osMemoryPoolAlloc(pool_id, 0U);\n}\n\nvoid *osPoolCAlloc (osPoolId pool_id) {\n  void    *block;\n  uint32_t block_size;\n\n  block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id);\n  if (block_size == 0U) {\n    return NULL;\n  }\n  block = osMemoryPoolAlloc(pool_id, 0U);\n  if (block != NULL) {\n    memset(block, 0, block_size);\n  }\n  return block;\n}\n\nosStatus osPoolFree (osPoolId pool_id, void *block) {\n  return osMemoryPoolFree(pool_id, block);\n}\n\n#endif  // Memory Pool\n\n\n// Message Queue\n\n#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) && !defined(os1_Disable_MessageQ)\n\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {\n  (void)thread_id;\n\n  if (queue_def == NULL) {\n    return NULL;\n  }\n  return osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr);\n}\n\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {\n  return osMessageQueuePut(queue_id, &info, 0U, millisec);\n}\n\nos_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {\n  osStatus_t status;\n  osEvent    event;\n  uint32_t   message;\n\n  status = osMessageQueueGet(queue_id, &message, NULL, millisec);\n  switch (status) {\n    case osOK:\n      event.status = osEventMessage;\n      event.value.v = message;\n      break;\n    case osErrorResource:\n      event.status = osOK;\n      break;\n    case osErrorTimeout:\n      event.status = osEventTimeout;\n      break;\n    default:\n      event.status = status;\n      break;\n  }\n  return event;\n}\n\n#endif  // Message Queue\n\n\n// Mail Queue\n\n#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) && !defined(os1_Disable_MailQ)\n\ntypedef struct os_mail_queue_s {\n  osMemoryPoolId_t   mp_id;\n  osMessageQueueId_t mq_id;\n} os_mail_queue_t;\n\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {\n  os_mail_queue_t *ptr;\n  (void)thread_id;\n\n  if (queue_def == NULL) {\n    return NULL;\n  }\n\n  ptr = queue_def->mail;\n  if (ptr == NULL) {\n    return NULL;\n  }\n\n  ptr->mp_id = osMemoryPoolNew  (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr);\n  ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr);\n  if ((ptr->mp_id == NULL) || (ptr->mq_id == NULL)) {\n    if (ptr->mp_id != NULL) {\n      osMemoryPoolDelete(ptr->mp_id);\n    }\n    if (ptr->mq_id != NULL) {\n      osMessageQueueDelete(ptr->mq_id);\n    }\n    return NULL;\n  }\n\n  return ptr;\n}\n\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n\n  if (ptr == NULL) {\n    return NULL;\n  }\n  return osMemoryPoolAlloc(ptr->mp_id, millisec);\n}\n\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n  void            *block;\n  uint32_t         block_size;\n\n  if (ptr == NULL) {\n    return NULL;\n  }\n  block_size = osMemoryPoolGetBlockSize(ptr->mp_id);\n  if (block_size == 0U) {\n    return NULL;\n  }\n  block = osMemoryPoolAlloc(ptr->mp_id, millisec);\n  if (block != NULL) {\n    memset(block, 0, block_size);\n  }\n\n  return block;\n\n}\n\nosStatus osMailPut (osMailQId queue_id, const void *mail) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n\n  if (ptr == NULL) {\n    return osErrorParameter;\n  }\n  if (mail == NULL) {\n    return osErrorValue;\n  }\n  return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U);\n}\n\nos_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n  osStatus_t       status;\n  osEvent          event;\n  void            *mail;\n\n  if (ptr == NULL) {\n    event.status = osErrorParameter;\n    return event;\n  }\n\n  status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec);\n  switch (status) {\n    case osOK:\n      event.status = osEventMail;\n      event.value.p = mail;\n      break;\n    case osErrorResource:\n      event.status = osOK;\n      break;\n    case osErrorTimeout:\n      event.status = osEventTimeout;\n      break;\n    default:\n      event.status = status;\n      break;\n  }\n  return event;\n}\n\nosStatus osMailFree (osMailQId queue_id, void *mail) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n\n  if (ptr == NULL) {\n    return osErrorParameter;\n  }\n  if (mail == NULL) {\n    return osErrorValue;\n  }\n  return osMemoryPoolFree(ptr->mp_id, mail);\n}\n\n#endif  // Mail Queue\n\n\n#endif  // osCMSIS\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Library/fetch_libs.sh",
    "content": "#!/bin/bash\n\nVERSION=5.5.5\nif [ -z \"$JENKINS_FAMILY_ENV\" ]; then\n    ARTIFACTORY_URL=https://artifactory.eu02.arm.com:443/artifactory/mcu.promoted\nelse\n    ARTIFACTORY_URL=https://eu-west-1.artifactory.aws.arm.com:443/artifactory/mcu.promoted\nfi\n\nif [ -z \"$ARTIFACTORY_API_KEY\" ]; then\n  echo \"Please set your Artifactory in ARTIFACTORY_API_KEY\"\n  echo \"\"\n  echo \"1. Browse to $(dirname $(dirname $ARTIFACTORY_URL))/ui/admin/artifactory/user_profile\"\n  echo \"2. Copy the API Key\"\n  echo \"3. Add 'export ARTIFACTORY_API_KEY=\\\"<API Key>\\\"' to ~/.bashrc\"\n  exit 1\nfi\n\nset -o pipefail\n\nfunction usage {\n  echo \"$(basename $0) [-h|--help] [-f|--force]\"\n  echo \"\"\n  echo \"Arguments:\"\n  echo \"  -h|--help   Print this usage message and exit.\"\n  echo \"  -f|--force  Force (re)download.\"\n  echo \"\"\n  echo \"Environment:\"\n  echo \" curl\"\n  echo \" sha256sum\"\n  echo \"\"\n}\n\nPOSITIONAL=()\nwhile [[ $# -gt 0 ]]\ndo\n  key=\"$1\"\n\n  case $key in\n    '-h'|'--help')\n      usage\n      exit 1\n    ;;\n    '-f'|'--force')\n      FORCE=1      \n    ;;\n    *)    # unknown option\n      POSITIONAL+=(\"$1\") # save it in an array for later\n    ;;\n  esac\n  shift # past argument\ndone\nset -- \"${POSITIONAL[@]}\" # restore positional parameters\n\npushd $(dirname $0) > /dev/null\n\nARCHIVE_NAME=\"RTX5-${VERSION}.zip\"\nARCHIVE_URL=\"${ARTIFACTORY_URL}/CMSIS_5/Libraries/${ARCHIVE_NAME}\"\necho \"Fetching ${ARCHIVE_URL}...\"\n\nif [[ $FORCE == 1 ]]; then\n    rm ${ARCHIVE_NAME}\nfi\n\nif [[ -f ${ARCHIVE_NAME} ]]; then\n    sha256sum=$(curl -s -I -H \"X-JFrog-Art-Api:${ARTIFACTORY_API_KEY}\" \"${ARCHIVE_URL}\" | grep \"X-Checksum-Sha256\" | cut -d\" \" -f2)\n    if echo \"${sha256sum} *${ARCHIVE_NAME}\" | sha256sum -c --status; then\n        echo \"Already up-to-date\"\n    else\n        rm ${ARCHIVE_NAME}\n    fi\nfi\n\nif [[ ! -f ${ARCHIVE_NAME} ]]; then\n    curl -C - -H \"X-JFrog-Art-Api:${ARTIFACTORY_API_KEY}\" -O \"${ARCHIVE_URL}\"\nfi\n\nunzip -u ${ARCHIVE_NAME}\n\nexit 0\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/RTX5.scvd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<component_viewer schemaVersion=\"1.2.0\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"Component_Viewer.xsd\">\n  <component name=\"CMSIS:RTOS2:Keil RTX5\" shortname=\"RTX5\" version=\"5.7.0\"/>    <!-- name and version of the component -->\n\n  <typedefs>\n    <!-- Attributes structure for thread -->\n    <typedef name=\"osThreadAttr_t\" info=\"\" size=\"36\">\n      <member name=\"name\"       type=\"uint32_t\" offset=\"0\"  info=\"name of the thread (type is const char *)\"/>\n      <member name=\"attr_bits\"  type=\"uint32_t\" offset=\"4\"  info=\"attribute bits\"/>\n      <member name=\"cb_mem\"     type=\"uint32_t\" offset=\"8\"  info=\"memory for control block (type is void *)\"/>\n      <member name=\"cb_size\"    type=\"uint32_t\" offset=\"12\" info=\"size of provided memory for control block\"/>\n      <member name=\"stack_mem\"  type=\"uint32_t\" offset=\"16\" info=\"memory for stack (type is void *)\"/>\n      <member name=\"stack_size\" type=\"uint32_t\" offset=\"20\" info=\"size of stack\"/>\n      <member name=\"priority\"   type=\"uint32_t\" offset=\"24\" info=\"initial thread priority (type is osPriority_t)\"/>\n      <member name=\"tz_module\"  type=\"uint32_t\" offset=\"28\" info=\"TrustZone module identifier (type is TZ_ModuleId_t)\"/>\n      <member name=\"reserved\"   type=\"uint32_t\" offset=\"32\" info=\"reserved (must be 0)\"/>\n    </typedef>\n\n    <!-- Attributes structure for timer -->\n    <typedef name=\"osTimerAttr_t\" info=\"\" size=\"16\">\n      <member name=\"name\"      type=\"uint32_t\" offset=\"0\"  info=\"name of the timer (type is const char *)\"/>\n      <member name=\"attr_bits\" type=\"uint32_t\" offset=\"4\"  info=\"attribute bits\"/>\n      <member name=\"cb_mem\"    type=\"uint32_t\" offset=\"8\"  info=\"memory for control block (type is void *)\"/>\n      <member name=\"cb_size\"   type=\"uint32_t\" offset=\"12\" info=\"size of provided memory for control block\"/>\n    </typedef>\n\n    <!-- Attributes structure for event flags -->\n    <typedef name=\"osEventFlagsAttr_t\" info=\"\" size=\"16\">\n      <member name=\"name\"      type=\"uint32_t\" offset=\"0\"  info=\"name of the event flags (type is const char *)\"/>\n      <member name=\"attr_bits\" type=\"uint32_t\" offset=\"4\"  info=\"attribute bits\"/>\n      <member name=\"cb_mem\"    type=\"uint32_t\" offset=\"8\"  info=\"memory for control block (type is void *)\"/>\n      <member name=\"cb_size\"   type=\"uint32_t\" offset=\"12\" info=\"size of provided memory for control block\"/>\n    </typedef>\n\n    <!-- Attributes structure for mutex -->\n    <typedef name=\"osMutexAttr_t\" info=\"\" size=\"16\">\n      <member name=\"name\"      type=\"uint32_t\" offset=\"0\"  info=\"name of the mutex (type is const char *)\"/>\n      <member name=\"attr_bits\" type=\"uint32_t\" offset=\"4\"  info=\"attribute bits\"/>\n      <member name=\"cb_mem\"    type=\"uint32_t\" offset=\"8\"  info=\"memory for control block (type is void *)\"/>\n      <member name=\"cb_size\"   type=\"uint32_t\" offset=\"12\" info=\"size of provided memory for control block\"/>\n    </typedef>\n\n    <!-- Attributes structure for semaphore -->\n    <typedef name=\"osSemaphoreAttr_t\" info=\"\" size=\"16\">\n      <member name=\"name\"      type=\"uint32_t\" offset=\"0\"  info=\"name of the semaphore (type is const char *)\"/>\n      <member name=\"attr_bits\" type=\"uint32_t\" offset=\"4\"  info=\"attribute bits\"/>\n      <member name=\"cb_mem\"    type=\"uint32_t\" offset=\"8\"  info=\"memory for control block (type is void *)\"/>\n      <member name=\"cb_size\"   type=\"uint32_t\" offset=\"12\" info=\"size of provided memory for control block\"/>\n    </typedef>\n\n    <!-- Attributes structure for memory pool -->\n    <typedef name=\"osMemoryPoolAttr_t\" info=\"\" size=\"24\">\n      <member name=\"name\"      type=\"uint32_t\" offset=\"0\"  info=\"name of the semaphore (type is const char *)\"/>\n      <member name=\"attr_bits\" type=\"uint32_t\" offset=\"4\"  info=\"attribute bits\"/>\n      <member name=\"cb_mem\"    type=\"uint32_t\" offset=\"8\"  info=\"memory for control block (type is void *)\"/>\n      <member name=\"cb_size\"   type=\"uint32_t\" offset=\"12\" info=\"size of provided memory for control block\"/>\n      <member name=\"mp_mem\"    type=\"uint32_t\" offset=\"16\" info=\"memory for data storage (type is void *)\"/>\n      <member name=\"mp_size\"   type=\"uint32_t\" offset=\"20\" info=\"size of provided memory for data storage\"/>\n    </typedef>\n\n    <!-- Attributes structure for message queue -->\n    <typedef name=\"osMessageQueueAttr_t\" info=\"\" size=\"24\">\n      <member name=\"name\"      type=\"uint32_t\" offset=\"0\"  info=\"name of the semaphore (type is const char *)\"/>\n      <member name=\"attr_bits\" type=\"uint32_t\" offset=\"4\"  info=\"attribute bits\"/>\n      <member name=\"cb_mem\"    type=\"uint32_t\" offset=\"8\"  info=\"memory for control block (type is void *)\"/>\n      <member name=\"cb_size\"   type=\"uint32_t\" offset=\"12\" info=\"size of provided memory for control block\"/>\n      <member name=\"mq_mem\"    type=\"uint32_t\" offset=\"16\" info=\"memory for data storage (type is void *)\"/>\n      <member name=\"mq_size\"   type=\"uint32_t\" offset=\"20\" info=\"size of provided memory for data storage\"/>\n    </typedef>\n\n    <!-- Thread Control Block -->\n    <typedef name=\"osRtxThread_t\" info=\"\" size=\"80\">\n      <member name=\"id\"            type=\"uint8_t\"        offset=\"0\" info=\"Object Identifier\"/>\n      <member name=\"state\"         type=\"uint8_t\"        offset=\"1\" info=\"Object State\">\n        <enum name=\"osThreadInactive\"    value=\"0\"  info=\"\"/>\n        <enum name=\"osThreadReady\"       value=\"1\"  info=\"\"/>\n        <enum name=\"osThreadRunning\"     value=\"2\"  info=\"\"/>\n        <enum name=\"osThreadBlocked\"     value=\"3\"  info=\"\"/>\n        <enum name=\"osThreadTerminated\"  value=\"4\"  info=\"\"/>\n        <enum name=\"osThreadError\"       value=\"-1\" info=\"\"/>\n\n        <enum name=\"Delay\"        value=\"0x13\"  info=\"\"/>\n        <enum name=\"Join\"         value=\"0x23\"  info=\"\"/>\n        <enum name=\"Thread Flags\" value=\"0x33\"  info=\"\"/>\n        <enum name=\"Event Flags\"  value=\"0x43\"  info=\"\"/>\n        <enum name=\"Mutex\"        value=\"0x53\"  info=\"\"/>\n        <enum name=\"Semaphore\"    value=\"0x63\"  info=\"\"/>\n        <enum name=\"Memory Pool\"  value=\"0x73\"  info=\"\"/>\n        <enum name=\"Message Get\"  value=\"0x83\"  info=\"\"/>\n        <enum name=\"Message Put\"  value=\"0x93\"  info=\"\"/>\n      </member>\n      <member name=\"flags\"         type=\"uint8_t\"        offset=\"2\" info=\"Object Flags\"/>\n      <member name=\"attr\"          type=\"uint8_t\"        offset=\"3\" info=\"Object Attributes\">\n        <enum name=\"osThreadDetached\"     value=\"0x00\" info=\"Thread created in detached mode\"/>\n        <enum name=\"osThreadJoinable\"     value=\"0x01\" info=\"Thread created in joinable mode\"/>\n        <enum name=\"osThreadUnprivileged\" value=\"0x02\" info=\"Thread created in unprivileged mode\"/>\n        <enum name=\"osThreadPrivileged\"   value=\"0x04\" info=\"Thread created in privileged mode\"/>\n      </member>\n      <member name=\"name\"          type=\"uint32_t\"       offset=\"4\"  info=\"Object name (type is *uint8_t)\"/>\n      <member name=\"thread_next\"   type=\"*osRtxThread_t\" offset=\"8\"  info=\"Link pointer to next Thread in Object list\"/>\n      <member name=\"thread_prev\"   type=\"*osRtxThread_t\" offset=\"12\" info=\"Link pointer to previous Thread in Object list\"/>\n      <member name=\"delay_next\"    type=\"*osRtxThread_t\" offset=\"16\" info=\"Link pointer to next Thread in Delay list\"/>\n      <member name=\"delay_prev\"    type=\"*osRtxThread_t\" offset=\"20\" info=\"Link pointer to previous Thread in Delay list\"/>\n      <member name=\"thread_join\"   type=\"*osRtxThread_t\" offset=\"24\" info=\"Thread waiting to Join\"/>\n      <member name=\"delay\"         type=\"uint32_t\"       offset=\"28\" info=\"Delay time\"/>\n      <member name=\"priority\"      type=\"int8_t\"         offset=\"32\" info=\"Thread priority\">\n        <enum name=\"osPriorityNone\"         value=\"0\"    info=\"\"/>\n        <enum name=\"osPriorityIdle\"         value=\"1\"    info=\"\"/>\n        <enum name=\"osPriorityLow\"          value=\"8\"    info=\"\"/>\n        <enum name=\"osPriorityLow1\"         value=\"8+1\"  info=\"\"/>\n        <enum name=\"osPriorityLow2\"         value=\"8+2\"  info=\"\"/>\n        <enum name=\"osPriorityLow3\"         value=\"8+3\"  info=\"\"/>\n        <enum name=\"osPriorityLow4\"         value=\"8+4\"  info=\"\"/>\n        <enum name=\"osPriorityLow5\"         value=\"8+5\"  info=\"\"/>\n        <enum name=\"osPriorityLow6\"         value=\"8+6\"  info=\"\"/>\n        <enum name=\"osPriorityLow7\"         value=\"8+7\"  info=\"\"/>\n        <enum name=\"osPriorityBelowNormal\"  value=\"16\"   info=\"\"/>\n        <enum name=\"osPriorityBelowNormal1\" value=\"16+1\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal2\" value=\"16+2\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal3\" value=\"16+3\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal4\" value=\"16+4\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal5\" value=\"16+5\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal6\" value=\"16+6\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal7\" value=\"16+7\" info=\"\"/>\n        <enum name=\"osPriorityNormal\"       value=\"24\"   info=\"\"/>\n        <enum name=\"osPriorityNormal1\"      value=\"24+1\" info=\"\"/>\n        <enum name=\"osPriorityNormal2\"      value=\"24+2\" info=\"\"/>\n        <enum name=\"osPriorityNormal3\"      value=\"24+3\" info=\"\"/>\n        <enum name=\"osPriorityNormal4\"      value=\"24+4\" info=\"\"/>\n        <enum name=\"osPriorityNormal5\"      value=\"24+5\" info=\"\"/>\n        <enum name=\"osPriorityNormal6\"      value=\"24+6\" info=\"\"/>\n        <enum name=\"osPriorityNormal7\"      value=\"24+7\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal\"  value=\"32\"   info=\"\"/>\n        <enum name=\"osPriorityAboveNormal1\" value=\"32+1\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal2\" value=\"32+2\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal3\" value=\"32+3\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal4\" value=\"32+4\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal5\" value=\"32+5\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal6\" value=\"32+6\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal7\" value=\"32+7\" info=\"\"/>\n        <enum name=\"osPriorityHigh\"         value=\"40\"   info=\"\"/>\n        <enum name=\"osPriorityHigh1\"        value=\"40+1\" info=\"\"/>\n        <enum name=\"osPriorityHigh2\"        value=\"40+2\" info=\"\"/>\n        <enum name=\"osPriorityHigh3\"        value=\"40+3\" info=\"\"/>\n        <enum name=\"osPriorityHigh4\"        value=\"40+4\" info=\"\"/>\n        <enum name=\"osPriorityHigh5\"        value=\"40+5\" info=\"\"/>\n        <enum name=\"osPriorityHigh6\"        value=\"40+6\" info=\"\"/>\n        <enum name=\"osPriorityHigh7\"        value=\"40+7\" info=\"\"/>\n        <enum name=\"osPriorityRealtime\"     value=\"48\"   info=\"\"/>\n        <enum name=\"osPriorityRealtime1\"    value=\"48+1\" info=\"\"/>\n        <enum name=\"osPriorityRealtime2\"    value=\"48+2\" info=\"\"/>\n        <enum name=\"osPriorityRealtime3\"    value=\"48+3\" info=\"\"/>\n        <enum name=\"osPriorityRealtime4\"    value=\"48+4\" info=\"\"/>\n        <enum name=\"osPriorityRealtime5\"    value=\"48+5\" info=\"\"/>\n        <enum name=\"osPriorityRealtime6\"    value=\"48+6\" info=\"\"/>\n        <enum name=\"osPriorityRealtime7\"    value=\"48+7\" info=\"\"/>\n        <enum name=\"osPriorityISR\"          value=\"56\"   info=\"\"/>\n        <enum name=\"osPriorityError\"        value=\"-1\"   info=\"\"/>\n      </member>\n      <member name=\"priority_base\" type=\"int8_t\"         offset=\"33\" info=\"Base priority\"/>\n      <member name=\"stack_frame\"   type=\"uint8_t\"        offset=\"34\" info=\"Stack frame\"/>\n      <member name=\"flags_options\" type=\"uint8_t\"        offset=\"35\" info=\"Thread/Event flags options\">\n        <enum name=\"osFlagsWaitAny\" value=\"0x00\" info=\"Wait for any flag.\"/>\n        <enum name=\"osFlagsWaitAll\" value=\"0x01\" info=\"Wait for all flags.\"/>\n        <enum name=\"osFlagsNoClear\" value=\"0x02\" info=\"Do not clear flags which have been specified to wait for.\"/>\n      </member>\n      <member name=\"wait_flags\"    type=\"int32_t\"        offset=\"36\" info=\"Waiting Thread/Event flags\"/>\n      <member name=\"thread_flags\"  type=\"int32_t\"        offset=\"40\" info=\"Thread flags\"/>\n      <member name=\"mutex_list\"    type=\"*osRtxMutex_t\"  offset=\"44\" info=\"Link pointer to list of owned mutexes\"/>\n      <member name=\"stack_mem\"     type=\"uint32_t\"       offset=\"48\" info=\"Stack memory (type is void *)\"/>\n      <member name=\"stack_size\"    type=\"uint32_t\"       offset=\"52\" info=\"Stack size\"/>\n      <member name=\"sp\"            type=\"uint32_t\"       offset=\"56\" info=\"Current stack pointer\"/>\n      <member name=\"thread_addr\"   type=\"uint32_t\"       offset=\"60\" info=\"Thread entry address\"/>\n      <member name=\"tz_memory\"     type=\"uint32_t\"       offset=\"64\" info=\"TrustZone Memory Identifier\"/>\n      <member name=\"zone\"          type=\"uint8_t\"        offset=\"68\" info=\"Thread Zone\"/>\n      <member name=\"reserved\"      type=\"uint8_t\"        offset=\"69\" info=\"Reserved bytes\"/>\n      <member name=\"wdog_next\"     type=\"*osRtxThread_t\" offset=\"72\" info=\"Link pointer to next Thread in Watchdog list\"/>\n      <member name=\"wdog_tick\"     type=\"uint32_t\"       offset=\"76\" info=\"Watchdog tick counter\"/>\n\n      <var name=\"cb_valid\"   type=\"uint32_t\" info=\"Control block validation status (valid=1, invalid=0)\"/>\n      <var name=\"sp_valid\"   type=\"uint32_t\" info=\"Stack pointer validation status (valid=1, invalid=0)\"/>\n      <var name=\"out_type\"   type=\"uint8_t\"  info=\"Output display type ID\"/>\n\n      <var name=\"ex_delay\"   type=\"uint32_t\" info=\"Calculated execution delay\"/>\n      <var name=\"wd_tick\"    type=\"uint32_t\" info=\"Calculated absolute watchdog tick time\"/>\n      <var name=\"wd_state\"   type=\"uint32_t\" info=\"Watchdog state (0=not running, 1=running)\"/>\n\n      <var name=\"stack_val\"  type=\"uint32_t\" info=\"Stack usage: analysis result\"/>\n      <var name=\"stack_cur\"  type=\"uint32_t\" info=\"Stack usage: current (address)\"/>\n      <var name=\"stack_curp\" type=\"uint32_t\" info=\"Stack usage: current (in percent)\"/>\n      <var name=\"stack_curb\" type=\"uint32_t\" info=\"Stack usage: current (in bytes)\"/>\n      <var name=\"stack_maxb\" type=\"uint32_t\" info=\"Stack usage: maximum (in bytes)\"/>\n      <var name=\"stack_maxp\" type=\"uint32_t\" info=\"Stack usage: maximum (in percent)\"/>\n      <var name=\"stack_over\" type=\"uint8_t\"  info=\"Stack usage: overflow\"/>\n    </typedef>\n\n    <!-- Timer Control Block -->\n    <typedef name=\"osRtxTimer_t\" info=\"\" size=\"32\">\n      <member name=\"id\"          type=\"uint8_t\"       offset=\"0\" info=\"Object Identifier\"/>\n      <member name=\"state\"       type=\"uint8_t\"       offset=\"1\" info=\"Object State\">\n        <enum name=\"Inactive\" value=\"0\" info=\"Timer is not active\"/>\n        <enum name=\"Stopped\"  value=\"1\" info=\"Timer is stopped\"/>\n        <enum name=\"Running\"  value=\"2\" info=\"Timer is running\"/>\n      </member>\n      <member name=\"flags\"       type=\"uint8_t\"       offset=\"2\" info=\"Object Flags\"/>\n      <member name=\"attr\"        type=\"uint8_t\"       offset=\"3\" info=\"Object Attributes\">\n        <enum name=\"osTimerOnce\"     value=\"0\" info=\"One-shot timer\"/>\n        <enum name=\"osTimerPeriodic\" value=\"1\" info=\"Periodic timer\"/>\n      </member>\n      <member name=\"name\"        type=\"uint32_t\"      offset=\"4\"  info=\"Object name (type is *uint8_t)\"/>\n      <member name=\"prev\"        type=\"*osRtxTimer_t\" offset=\"8\"  info=\"Pointer to previous active timer\"/>\n      <member name=\"next\"        type=\"*osRtxTimer_t\" offset=\"12\" info=\"Pointer to next active timer\"/>\n      <member name=\"tick\"        type=\"uint32_t\"      offset=\"16\" info=\"Timer current tick\"/>\n      <member name=\"load\"        type=\"uint32_t\"      offset=\"20\" info=\"Timer load value\"/>\n      <!-- Inlined \"osRtxTimerFinfo_t\" structure -->\n      <member name=\"finfo_fp\"    type=\"uint32_t\"      offset=\"24\" info=\"Timer function pointer (type is void *)\"/>\n      <member name=\"finfo_arg\"   type=\"uint32_t\"      offset=\"28\" info=\"Timer function argument (type is void *)\"/>\n\n      <var name=\"cb_valid\" type=\"uint32_t\" info=\"Control Block validation status (valid=1, invalid=0)\"/>\n      <var name=\"ex_tick\"  type=\"uint32_t\" info=\"Calculated absolute tick time\"/>\n    </typedef>\n\n    <!-- Event Flags Control Block -->\n    <typedef name=\"osRtxEventFlags_t\" info=\"\" size=\"16\">\n      <member name=\"id\"          type=\"uint8_t\"        offset=\"0\"  info=\"Object Identifier\"/>\n      <member name=\"state\"       type=\"uint8_t\"        offset=\"1\"  info=\"Object State\"/>\n      <member name=\"flags\"       type=\"uint8_t\"        offset=\"2\"  info=\"Object Flags\"/>\n      <member name=\"attr\"        type=\"uint8_t\"        offset=\"3\"  info=\"Object Attributes\"/>\n      <member name=\"name\"        type=\"uint32_t\"       offset=\"4\"  info=\"Object name (type is *uint8_t)\"/>\n      <member name=\"thread_list\" type=\"*osRtxThread_t\" offset=\"8\"  info=\"Waiting threads list\"/>\n      <member name=\"event_flags\" type=\"int32_t\"        offset=\"12\" info=\"Event flags\"/>\n\n      <var name=\"cb_valid\" type=\"uint32_t\" info=\"Control Block validation status (valid=1, invalid=0)\"/>\n      <var name=\"wl_idx\"   type=\"uint32_t\" info=\"EventFlags waiting list (EWL) index\" />\n      <var name=\"wl_cnt\"   type=\"uint32_t\" info=\"Number of threads waiting for event flags\" />\n    </typedef>\n\n    <!-- Mutex Control Block -->\n    <typedef name=\"osRtxMutex_t\" info=\"\" size=\"28\">\n      <member name=\"id\"           type=\"uint8_t\"        offset=\"0\" info=\"Object Identifier\"/>\n      <member name=\"state\"        type=\"uint8_t\"        offset=\"1\" info=\"Object State\"/>\n      <member name=\"flags\"        type=\"uint8_t\"        offset=\"2\" info=\"Object Flags\"/>\n      <member name=\"attr\"         type=\"uint8_t\"        offset=\"3\" info=\"Object Attributes\">\n        <enum name=\"osMutexRecursive\"   value=\"0x01\" info=\"Recursive mutex.\"/>\n        <enum name=\"osMutexPrioInherit\" value=\"0x02\" info=\"Priority inherit protocol.\"/>\n        <enum name=\"osMutexRobust\"      value=\"0x08\" info=\"Robust mutex.\"/>\n      </member>\n      <member name=\"name\"         type=\"uint32_t\"       offset=\"4\"  info=\"Object name (type is *uint8_t)\"/>\n      <member name=\"thread_list\"  type=\"*osRtxThread_t\" offset=\"8\"  info=\"Waiting threads list\"/>\n      <member name=\"owner_thread\" type=\"*osRtxThread_t\" offset=\"12\" info=\"Owner thread\"/>\n      <member name=\"owner_prev\"   type=\"*osRtxMutex_t\"  offset=\"16\" info=\"Pointer to previous owned mutex\"/>\n      <member name=\"owner_next\"   type=\"*osRtxMutex_t\"  offset=\"20\" info=\"Pointer to next owned mutex\"/>\n      <member name=\"lock\"         type=\"uint8_t\"        offset=\"24\" info=\"Lock counter\"/>\n\n      <var name=\"cb_valid\" type=\"uint32_t\" info=\"Control Block validation status (valid=1, invalid=0)\"/>\n      <var name=\"wl_idx\"   type=\"uint32_t\" info=\"Mutex waiting list (MWL) index\" />\n      <var name=\"wl_cnt\"   type=\"uint32_t\" info=\"Number of threads waiting for current mutex\" />\n    </typedef>\n\n    <!-- Semaphore Control Block -->\n    <typedef name=\"osRtxSemaphore_t\" info=\"\" size=\"16\">\n      <member name=\"id\"          type=\"uint8_t\"        offset=\"0\"  info=\"Object Identifier\"/>\n      <member name=\"state\"       type=\"uint8_t\"        offset=\"1\"  info=\"Object State\"/>\n      <member name=\"flags\"       type=\"uint8_t\"        offset=\"2\"  info=\"Object Flags\"/>\n      <member name=\"attr\"        type=\"uint8_t\"        offset=\"3\"  info=\"Object Attributes\"/>\n      <member name=\"name\"        type=\"uint32_t\"       offset=\"4\"  info=\"Object name (type is *uint8_t)\"/>\n      <member name=\"thread_list\" type=\"*osRtxThread_t\" offset=\"8\"  info=\"Waiting threads list\"/>\n      <member name=\"tokens\"      type=\"uint16_t\"       offset=\"12\" info=\"Current number of tokens\"/>\n      <member name=\"max_tokens\"  type=\"uint16_t\"       offset=\"14\" info=\"Maximum number of tokens\"/>\n\n      <var name=\"cb_valid\" type=\"uint32_t\" info=\"Control Block validation status (valid=1, invalid=0)\"/>\n      <var name=\"wl_idx\"   type=\"uint32_t\" info=\"Semaphore waiting list (SWL) index\" />\n      <var name=\"wl_cnt\"   type=\"uint32_t\" info=\"Number of threads waiting for current semaphore\" />\n    </typedef>\n\n    <!-- Memory Pool Information -->\n    <typedef name=\"osRtxMpInfo_t\" info=\"Memory pool information\" size=\"24\">\n      <member name=\"max_blocks\"  type=\"uint32_t\" offset=\"0\" info=\"Maximum number of blocks\"/>\n      <member name=\"used_blocks\" type=\"uint32_t\" offset=\"4\" info=\"Number of used blocks\"/>\n      <member name=\"block_size\"  type=\"uint32_t\" offset=\"8\" info=\"Block size\"/>\n      <member name=\"block_base\"  type=\"uint32_t\" offset=\"12\" info=\"Block memory base address (type is void *)\"/>\n      <member name=\"block_lim\"   type=\"uint32_t\" offset=\"16\" info=\"Block memory limit address (type is void *)\"/>\n      <member name=\"block_free\"  type=\"uint32_t\" offset=\"20\" info=\"First free block address (type is void *)\"/>\n    </typedef>\n\n    <!-- Memory Pool Control Block -->\n    <typedef name=\"osRtxMemoryPool_t\" info=\"\" size=\"36\">\n      <member name=\"id\"          type=\"uint8_t\"        offset=\"0\" info=\"Object Identifier\"/>\n      <member name=\"state\"       type=\"uint8_t\"        offset=\"1\" info=\"Object State\"/>\n      <member name=\"flags\"       type=\"uint8_t\"        offset=\"2\" info=\"Object Flags\"/>\n      <member name=\"attr\"        type=\"uint8_t\"        offset=\"3\" info=\"Object Attributes\"/>\n      <member name=\"name\"        type=\"uint32_t\"       offset=\"4\" info=\"Object name (type is *uint8_t)\"/>\n      <member name=\"thread_list\" type=\"*osRtxThread_t\" offset=\"8\" info=\"Waiting threads list\"/>\n\n      <!-- Inlined \"osRtxMpInfo_t\" structure -->\n      <member name=\"max_blocks\"  type=\"uint32_t\"       offset=\"12+0\"  info=\"Maximum number of blocks\"/>\n      <member name=\"used_blocks\" type=\"uint32_t\"       offset=\"12+4\"  info=\"Number of used blocks\"/>\n      <member name=\"block_size\"  type=\"uint32_t\"       offset=\"12+8\"  info=\"Block size\"/>\n      <member name=\"block_base\"  type=\"uint32_t\"       offset=\"12+12\" info=\"Block memory base address (type is void *)\"/>\n      <member name=\"block_lim\"   type=\"uint32_t\"       offset=\"12+16\" info=\"Block memory limit address (type is void *)\"/>\n      <member name=\"block_free\"  type=\"uint32_t\"       offset=\"12+20\" info=\"First free block address (type is void *)\"/>\n\n      <var name=\"cb_valid\" type=\"uint32_t\" info=\"Control Block validation status (valid=1, invalid=0)\"/>\n      <var name=\"wl_idx\"   type=\"uint32_t\" info=\"Memory Pool waiting list (PWL) index\" />\n      <var name=\"wl_cnt\"   type=\"uint32_t\" info=\"Number of threads waiting for memory pool\" />\n    </typedef>\n\n    <!-- Message Control Block -->\n    <typedef name=\"osRtxMessage_t\" info=\"\" size=\"12\">\n      <member name=\"id\"       type=\"uint8_t\"         offset=\"0\" info=\"Object Identifier\"/>\n      <member name=\"state\"    type=\"uint8_t\"         offset=\"1\" info=\"Object State\"/>\n      <member name=\"flags\"    type=\"uint8_t\"         offset=\"2\" info=\"Object Flags\"/>\n      <member name=\"priority\" type=\"uint8_t\"         offset=\"3\" info=\"Message priority\"/>\n      <member name=\"prev\"     type=\"*osRtxMessage_t\" offset=\"4\" info=\"Pointer to previous message\"/>\n      <member name=\"next\"     type=\"*osRtxMessage_t\" offset=\"8\" info=\"Pointer to next message\"/>\n\n      <var name=\"addr\" type=\"uint32_t\" info=\"Message location address\" />\n    </typedef>\n\n    <!-- Message Queue Control Block -->\n    <typedef name=\"osRtxMessageQueue_t\" info=\"\" size=\"52\">\n      <member name=\"id\"          type=\"uint8_t\"         offset=\"0\" info=\"Object Identifier\"/>\n      <member name=\"state\"       type=\"uint8_t\"         offset=\"1\" info=\"Object State\"/>\n      <member name=\"flags\"       type=\"uint8_t\"         offset=\"2\" info=\"Object Flags\"/>\n      <member name=\"attr\"        type=\"uint8_t\"         offset=\"3\" info=\"Object Attributes\"/>\n      <member name=\"name\"        type=\"uint32_t\"        offset=\"4\" info=\"Object name (type is *uint8_t)\"/>\n      <member name=\"thread_list\" type=\"*osRtxThread_t\"  offset=\"8\" info=\"Waiting threads list\"/>\n\n      <!-- Inlined \"osRtxMpInfo_t\" structure -->\n      <member name=\"max_blocks\"  type=\"uint32_t\"        offset=\"12+0\"  info=\"Maximum number of blocks\"/>\n      <member name=\"used_blocks\" type=\"uint32_t\"        offset=\"12+4\"  info=\"Number of used blocks\"/>\n      <member name=\"block_size\"  type=\"uint32_t\"        offset=\"12+8\"  info=\"Block size\"/>\n      <member name=\"block_base\"  type=\"uint32_t\"        offset=\"12+12\" info=\"Block memory base address (type is void *)\"/>\n      <member name=\"block_lim\"   type=\"uint32_t\"        offset=\"12+16\" info=\"Block memory limit address (type is void *)\"/>\n      <member name=\"block_free\"  type=\"uint32_t\"        offset=\"12+20\" info=\"First free block address (type is void *)\"/>\n\n      <member name=\"msg_size\"    type=\"uint32_t\"        offset=\"36\" info=\"Message size\"/>\n      <member name=\"msg_count\"   type=\"uint32_t\"        offset=\"40\" info=\"Number of queued messages\"/>\n      <member name=\"msg_first\"   type=\"*osRtxMessage_t\" offset=\"44\" info=\"Pointer to first message\"/>\n      <member name=\"msg_last\"    type=\"*osRtxMessage_t\" offset=\"48\" info=\"Pointer to last message\"/>\n\n      <var name=\"cb_valid\" type=\"uint32_t\" info=\"Control Block validation status (valid=1, invalid=0)\"/>\n      <var name=\"wl_idx\"   type=\"uint32_t\" info=\"Waiting list index (QWL)\" />\n      <var name=\"wl_cnt\"   type=\"uint32_t\" info=\"Number of threads waiting\" />\n      <var name=\"ml_idx\"   type=\"uint32_t\" info=\"Queue message list index (QML)\" />\n      <var name=\"ml_cnt\"   type=\"uint32_t\" info=\"Number of enqueued messages\" />\n    </typedef>\n\n    <!-- OS Runtime Information structure -->\n    <typedef name=\"osRtxInfo_t\" info=\"OS Runtime Information\" size=\"164\">\n      <member name=\"os_id\"                      type=\"uint32_t\"             offset=\"0\" info=\"OS Identification (type is *uint8_t)\"/>\n      <member name=\"version\"                    type=\"uint32_t\"             offset=\"4\" info=\"OS Version\"/>\n      <member name=\"kernel_state\"               type=\"uint8_t\"              offset=\"8\" info=\"Kernel state\">\n        <enum name=\"osKernelInactive\"  value=\"0\"  info=\"Inactive\"/>\n        <enum name=\"osKernelReady\"     value=\"1\"  info=\"Ready\"/>\n        <enum name=\"osKernelRunning\"   value=\"2\"  info=\"Running\"/>\n        <enum name=\"osKernelLocked\"    value=\"3\"  info=\"Locked\"/>\n        <enum name=\"osKernelSuspended\" value=\"4\"  info=\"Suspended\"/>\n        <enum name=\"osKernelError\"     value=\"5\"  info=\"Error\"/>\n      </member>\n      <member name=\"kernel_blocked\"             type=\"uint8_t\"              offset=\"9\"  info=\"Kernel blocked\"/>\n      <member name=\"kernel_pendSV\"              type=\"uint8_t\"              offset=\"10\" info=\"Kernel pending SV\"/>\n      <member name=\"kernel_protect\"             type=\"uint8_t\"              offset=\"11\" info=\"Protect options\"/>\n      <member name=\"kernel_tick\"                type=\"uint32_t\"             offset=\"12\" info=\"Kernel tick counter\"/>\n      <member name=\"tick_irqn\"                  type=\"int32_t\"              offset=\"16\" info=\"Tick timer IRQ number\"/>\n      <member name=\"thread_run_curr\"            type=\"*osRtxThread_t\"       offset=\"20\" info=\"Current running thread\"/>\n      <member name=\"thread_run_next\"            type=\"*osRtxThread_t\"       offset=\"24\" info=\"Next thread to run\"/>\n\n      <!-- Inlined \"osRtxObject_t\" structure at offset: 28 -->\n      <member name=\"thread_ready_id\"            type=\"uint8_t\"              offset=\"28+0\" info=\"Object Identifier\" />\n      <member name=\"thread_ready_state\"         type=\"uint8_t\"              offset=\"28+1\" info=\"Object State\" />\n      <member name=\"thread_ready_flags\"         type=\"uint8_t\"              offset=\"28+2\" info=\"Object Flags\" />\n      <member name=\"thread_ready_attr\"          type=\"uint8_t\"              offset=\"28+3\" info=\"Object Attributes\"/>\n      <member name=\"thread_ready_name\"          type=\"uint32_t\"             offset=\"28+4\" info=\"Object Name (type is *uint8_t)\" />\n      <member name=\"thread_ready_thread_list\"   type=\"*osRtxThread_t\"       offset=\"28+8\" info=\"Threads List\" />\n\n      <member name=\"thread_idle\"                type=\"*osRtxThread_t\"       offset=\"40\"  info=\"Idle thread\"/>\n      <member name=\"thread_delay_list\"          type=\"*osRtxThread_t\"       offset=\"44\"  info=\"Delay list\"/>\n      <member name=\"thread_wait_list\"           type=\"*osRtxThread_t\"       offset=\"48\"  info=\"Wait list (no timeout)\"/>\n      <member name=\"thread_terminate_list\"      type=\"*osRtxThread_t\"       offset=\"52\"  info=\"Terminate list\"/>\n      <member name=\"thread_wdog_list\"           type=\"*osRtxThread_t\"       offset=\"56\"  info=\"Watchdog list\"/>\n\n      <member name=\"thread_robin_thread\"        type=\"*osRtxThread_t\"       offset=\"60\"  info=\"Round Robin thread\"/>\n      <member name=\"thread_timeout\"             type=\"uint32_t\"             offset=\"64\"  info=\"Round Robin timeout\"/>\n\n      <member name=\"timer_list\"                 type=\"*osRtxTimer_t\"        offset=\"68\"  info=\"Active timer list\"/>\n      <member name=\"timer_thread\"               type=\"*osRtxThread_t\"       offset=\"72\"  info=\"Timer thread\"/>\n      <member name=\"timer_mq\"                   type=\"*osRtxMessageQueue_t\" offset=\"76\"  info=\"Timer message queue\"/>\n      <member name=\"timer_tick\"                 type=\"uint32_t\"             offset=\"80\"  info=\"Timer tick function (type is func *)\"/>\n\n      <member name=\"isr_queue_max\"              type=\"uint16_t\"             offset=\"84\"  info=\"Maximum items\"/>\n      <member name=\"isr_queue_cnt\"              type=\"uint16_t\"             offset=\"86\"  info=\"Item count\"/>\n      <member name=\"isr_queue_in\"               type=\"uint16_t\"             offset=\"88\"  info=\"Incoming item index\"/>\n      <member name=\"isr_queue_out\"              type=\"uint16_t\"             offset=\"90\"  info=\"Outgoing item index\"/>\n      <member name=\"isr_queue_data\"             type=\"uint32_t\"             offset=\"92\"  info=\"Queue data (type is void **)\"/>\n\n      <member name=\"post_process_thread\"        type=\"uint32_t\"             offset=\"96\"  info=\"Thread post processing function (type is func *)\"/>\n      <member name=\"post_process_event_flags\"   type=\"uint32_t\"             offset=\"100\" info=\"Event flags post processing function (type is func *)\"/>\n      <member name=\"post_process_semaphore\"     type=\"uint32_t\"             offset=\"104\" info=\"Semaphore post processing function (type is func *)\"/>\n      <member name=\"post_process_memory_pool\"   type=\"uint32_t\"             offset=\"108\" info=\"Memory pool post processing function (type is func *)\"/>\n      <member name=\"post_process_message_queue\" type=\"uint32_t\"             offset=\"112\" info=\"Message queue post processing function (type is func *)\"/>\n\n      <member name=\"mem_stack\"                  type=\"uint32_t\"             offset=\"116\" info=\"Stack memory (type is void *)\"/>\n      <member name=\"mem_mp_data\"                type=\"uint32_t\"             offset=\"120\" info=\"Memory pool data memory (type is void *)\"/>\n      <member name=\"mem_mq_data\"                type=\"uint32_t\"             offset=\"124\" info=\"Message queue Data memory (type is void *)\"/>\n      <member name=\"mem_common\"                 type=\"uint32_t\"             offset=\"128\" info=\"Common memory address (type is void *)\"/>\n\n      <member name=\"mpi_stack\"                  type=\"*osRtxMpInfo_t\"       offset=\"132\" info=\"Stack for threads\"/>\n      <member name=\"mpi_thread\"                 type=\"*osRtxMpInfo_t\"       offset=\"136\" info=\"Thread control blocks\"/>\n      <member name=\"mpi_timer\"                  type=\"*osRtxMpInfo_t\"       offset=\"140\" info=\"Timer control blocks\"/>\n      <member name=\"mpi_event_flags\"            type=\"*osRtxMpInfo_t\"       offset=\"144\" info=\"Event flags control blocks\"/>\n      <member name=\"mpi_mutex\"                  type=\"*osRtxMpInfo_t\"       offset=\"148\" info=\"Mutex control blocks\"/>\n      <member name=\"mpi_semaphore\"              type=\"*osRtxMpInfo_t\"       offset=\"152\" info=\"Semaphore control blocks\"/>\n      <member name=\"mpi_memory_pool\"            type=\"*osRtxMpInfo_t\"       offset=\"156\" info=\"Memory pool control blocks\"/>\n      <member name=\"mpi_message_queue\"          type=\"*osRtxMpInfo_t\"       offset=\"160\" info=\"Message queue control blocks\"/>\n\n      <var name=\"robin_tick\" type=\"uint32_t\" info=\"Round Robin time tick (thread_robin_thread.delay)\"/>\n    </typedef>\n\n    <!-- OS Runtime Object Memory Usage structure -->\n    <typedef name=\"osRtxObjectMemUsage_t\" info=\"OS Runtime Object Memory Usage\" size=\"12\">\n      <member name=\"cnt_alloc\" type=\"uint32_t\" offset=\"0\" info=\"Counter for alloc\"/>\n      <member name=\"cnt_free\"  type=\"uint32_t\" offset=\"4\" info=\"Counter for free\"/>\n      <member name=\"max_used\"  type=\"uint32_t\" offset=\"8\" info=\"Maximum used\"/>\n    </typedef>\n\n    <!-- OS Configuration structure -->\n    <typedef name=\"osRtxConfig_t\" const=\"1\" info=\"OS Configuration Structure\" size=\"112\">\n      <member name=\"flags\"                 type=\"uint32_t\" offset=\"0\" info=\"OS configuration flags\"/>\n      <member name=\"tick_freq\"             type=\"uint32_t\" offset=\"4\" info=\"Kernel tick frequency\"/>\n\n      <member name=\"robin_timeout\"         type=\"uint32_t\" offset=\"8\"  info=\"Round Robin timeout tick\"/>\n      <member name=\"isr_queue_data\"        type=\"uint32_t\" offset=\"12\" info=\"ISR post processing queue (type is void **)\"/>\n      <member name=\"isr_queue_max\"         type=\"uint16_t\" offset=\"16\" info=\"Maximum data\"/>\n      <member name=\"isr_queue_padding\"     type=\"uint16_t\" offset=\"18\" info=\"Padding bytes\"/>\n\n      <member name=\"mem_stack_addr\"        type=\"uint32_t\" offset=\"20\" info=\"Stack memory address\"/>\n      <member name=\"mem_stack_size\"        type=\"uint32_t\" offset=\"24\" info=\"Stack memory size\"/>\n      <member name=\"mem_mp_data_addr\"      type=\"uint32_t\" offset=\"28\" info=\"Memory pool data memory address\"/>\n      <member name=\"mem_mp_data_size\"      type=\"uint32_t\" offset=\"32\" info=\"Memory pool data memory size\"/>\n      <member name=\"mem_mq_data_addr\"      type=\"uint32_t\" offset=\"36\" info=\"Message queue data memory address\"/>\n      <member name=\"mem_mq_data_size\"      type=\"uint32_t\" offset=\"40\" info=\"Message queue data memory size\"/>\n      <member name=\"mem_common_addr\"       type=\"uint32_t\" offset=\"44\" info=\"Common memory address\"/>\n      <member name=\"mem_common_size\"       type=\"uint32_t\" offset=\"48\" info=\"Common memory size\"/>\n\n      <member name=\"mpi_stack\"             type=\"*osRtxMpInfo_t\" offset=\"52\" info=\"Stack for threads\"/>\n      <member name=\"mpi_thread\"            type=\"*osRtxMpInfo_t\" offset=\"56\" info=\"Thread control blocks\"/>\n      <member name=\"mpi_timer\"             type=\"*osRtxMpInfo_t\" offset=\"60\" info=\"Timer control blocks\"/>\n      <member name=\"mpi_event_flags\"       type=\"*osRtxMpInfo_t\" offset=\"64\" info=\"Event flags control blocks\"/>\n      <member name=\"mpi_mutex\"             type=\"*osRtxMpInfo_t\" offset=\"68\" info=\"Mutex control blocks\"/>\n      <member name=\"mpi_semaphore\"         type=\"*osRtxMpInfo_t\" offset=\"72\" info=\"Semaphore control blocks\"/>\n      <member name=\"mpi_memory_pool\"       type=\"*osRtxMpInfo_t\" offset=\"76\" info=\"Memory pool control blocks\"/>\n      <member name=\"mpi_message_queue\"     type=\"*osRtxMpInfo_t\" offset=\"80\" info=\"Message queue control blocks\"/>\n\n      <member name=\"thread_stack_size\"     type=\"uint32_t\" offset=\"84\"  info=\"Default thread stack size\"/>\n      <member name=\"idle_thread_attr\"      type=\"uint32_t\" offset=\"88\"  info=\"Idle thread attributes (type is osThreadAttr_s *)\"/>\n      <member name=\"timer_thread_attr\"     type=\"uint32_t\" offset=\"92\"  info=\"Timer thread attributes (type is osThreadAttr_s *)\"/>\n      <member name=\"timer_thread\"          type=\"uint32_t\" offset=\"96\"  info=\"Timer Thread Function (type is void(*func)(void *)\"/>\n      <member name=\"timer_setup\"           type=\"uint32_t\" offset=\"100\" info=\"Timer Setup Function (type is int32_t(*func)(void)\"/>\n      <member name=\"timer_mq_attr\"         type=\"uint32_t\" offset=\"104\" info=\"Timer message queue attributes (type is osMessageQueueAttr_s *)\"/>\n      <member name=\"timer_mq_mcnt\"         type=\"uint32_t\" offset=\"108\" info=\"Timer message queue maximum messages\"/>\n\n      <var name=\"stack_check\"  type=\"uint8_t\" info=\"Stack checking (0:disabled, 1:enabled)\"/>\n      <var name=\"stack_wmark\"  type=\"uint8_t\" info=\"Stack watermark (0:disabled, 1:enabled)\"/>\n      <var name=\"safety_feat\"  type=\"uint8_t\" info=\"Safety features (0:disabled, 1:enabled)\"/>\n      <var name=\"safety_class\" type=\"uint8_t\" info=\"Thread safety class (0:disabled, 1:enabled)\"/>\n      <var name=\"exec_zone\"    type=\"uint8_t\" info=\"Execution zone (0:disabled, 1:enabled)\"/>\n      <var name=\"watchdog\"     type=\"uint8_t\" info=\"Thread watchdog (0:disabled, 1:enabled)\"/>\n      <var name=\"obj_check\"    type=\"uint8_t\" info=\"Object pointer checking (0:disabled, 1:enabled)\"/>\n      <var name=\"svc_check\"    type=\"uint8_t\" info=\"SVC function pointer checking (0:disabled, 1:enabled)\"/>\n    </typedef>\n\n    <!-- Memory Pool Header -->\n    <typedef name=\"mem_head_t\" info=\"Memory Pool Header Structure\" size=\"8\">\n      <member name=\"size\" type=\"uint32_t\" offset=\"0\" info=\"Memory pool size\"/>\n      <member name=\"used\" type=\"uint32_t\" offset=\"4\" info=\"Size of used memory\"/>\n\n      <var name=\"max_used\" type=\"uint32_t\" info=\"Maximum size of used memory\" />\n    </typedef>\n\n    <!-- Memory Block Header + Object Header -->\n    <typedef name=\"mem_block_t\" info=\"Memory Block Header Structure\" size=\"9\">\n      <member name=\"next\"     type=\"*mem_block_t\" offset=\"0\"  info=\"Next memory block\"/>\n      <member name=\"len\"      type=\"uint32_t\"     offset=\"4\"  info=\"Memory block size\"/>\n      <member name=\"id\"       type=\"uint8_t\"      offset=\"8\"  info=\"Object Identifier\"/>\n    </typedef>\n\n    <!-- Helper typedefs -->\n    <typedef name=\"rtx_sections_t\" info=\"RTX Control Block Sections Info Structure\" size=\"56\">\n      <member name=\"thread_cb_start\"    type=\"uint32_t\" offset=\"0\"  info=\"Thread control block section start\"/>\n      <member name=\"thread_cb_end\"      type=\"uint32_t\" offset=\"4\"  info=\"Thread control block section end\"/>\n      <member name=\"timer_cb_start\"     type=\"uint32_t\" offset=\"8\"  info=\"Timer control block section start\"/>\n      <member name=\"timer_cb_end\"       type=\"uint32_t\" offset=\"12\" info=\"Timer control block section end\"/>\n      <member name=\"evflags_cb_start\"   type=\"uint32_t\" offset=\"16\" info=\"Event flags control block section start\"/>\n      <member name=\"evflags_cb_end\"     type=\"uint32_t\" offset=\"20\" info=\"Event flags control block section end\"/>\n      <member name=\"mutex_cb_start\"     type=\"uint32_t\" offset=\"24\" info=\"Mutex control block section start\"/>\n      <member name=\"mutex_cb_end\"       type=\"uint32_t\" offset=\"28\" info=\"Mutex control block section end\"/>\n      <member name=\"semaphore_cb_start\" type=\"uint32_t\" offset=\"32\" info=\"Semaphore control block section start\"/>\n      <member name=\"semaphore_cb_end\"   type=\"uint32_t\" offset=\"36\" info=\"Semaphore control block section end\"/>\n      <member name=\"mempool_cb_start\"   type=\"uint32_t\" offset=\"40\" info=\"Memory pool control block section start\"/>\n      <member name=\"mempool_cb_end\"     type=\"uint32_t\" offset=\"44\" info=\"Memory pool control block section end\"/>\n      <member name=\"msgqueue_cb_start\"  type=\"uint32_t\" offset=\"48\" info=\"Message queue control block section start\"/>\n      <member name=\"msgqueue_cb_end\"    type=\"uint32_t\" offset=\"52\" info=\"Message queue control block section end\"/>\n    </typedef>\n\n    <typedef name=\"rtx_t\" info=\"Various RTX Definitions\" size=\"8\">\n      <member name=\"status\" type=\"int32_t\" offset=\"0\" info=\"RTX5 operations status\">\n        <enum name=\"osOK\"                            value=\"0\"   info=\"Operation completed successfully\"/>\n        <enum name=\"osError\"                         value=\"-1\"  info=\"Unspecified RTOS error: run-time error but no other error message fits.\"/>\n        <enum name=\"osErrorTimeout\"                  value=\"-2\"  info=\"Operation not completed within the timeout period.\"/>\n        <enum name=\"osErrorResource\"                 value=\"-3\"  info=\"Resource not available\"/>\n        <enum name=\"osErrorParameter\"                value=\"-4\"  info=\"Parameter error\"/>\n        <enum name=\"osErrorNoMemory\"                 value=\"-5\"  info=\"System is out of memory: it was impossible to allocate or reserve memory for the operation\"/>\n        <enum name=\"osErrorISR\"                      value=\"-6\"  info=\"Not allowed in ISR context: the function cannot be called from interrupt service routines\"/>\n        <enum name=\"osErrorSafetyClass\"              value=\"-7\"  info=\"Operation denied because of safety class violation\"/>\n        <enum name=\"osRtxErrorKernelNotReady\"        value=\"-8\"  info=\"RTOS Kernel scheduler is not ready\"/>\n        <enum name=\"osRtxErrorKernelNotRunning\"      value=\"-9\"  info=\"RTOS Kernel scheduler is not running\"/>\n        <enum name=\"osRtxErrorInvalidControlBlock\"   value=\"-10\" info=\"Object control block is not properly aligned or has an invalid size\"/>\n        <enum name=\"osRtxErrorInvalidDataMemory\"     value=\"-11\" info=\"Data memory is not is not properly aligned or has an invalid size\"/>\n        <enum name=\"osRtxErrorInvalidThreadStack\"    value=\"-12\" info=\"Thread stack is invalid\"/>\n        <enum name=\"osRtxErrorInvalidPriority\"       value=\"-13\" info=\"Thread priority is invalid\"/>\n        <enum name=\"osRtxErrorInvalidPrivilegedMode\" value=\"-14\" info=\"Privileged thread cannot be created, kernel protect is active\"/>\n        <enum name=\"osRtxErrorThreadNotJoinable\"     value=\"-15\" info=\"Thread is not joinable\"/>\n        <enum name=\"osRtxErrorMutexNotOwned\"         value=\"-16\" info=\"Mutex is not owned by the current running thread\"/>\n        <enum name=\"osRtxErrorMutexNotLocked\"        value=\"-17\" info=\"Mutex is not locked\"/>\n        <enum name=\"osRtxErrorMutexLockLimit\"        value=\"-18\" info=\"Maximum number of recursive mutex locks reached\"/>\n        <enum name=\"osRtxErrorSemaphoreCountLimit\"   value=\"-19\" info=\"Semaphore count limit reached\"/>\n        <enum name=\"osRtxErrorTZ_InitContext_S\"      value=\"-20\" info=\"\"/>\n        <enum name=\"osRtxErrorTZ_AllocContext_S\"     value=\"-21\" info=\"\"/>\n        <enum name=\"osRtxErrorTZ_FreeContext_S\"      value=\"-22\" info=\"\"/>\n        <enum name=\"osRtxErrorTZ_LoadContext_S\"      value=\"-23\" info=\"\"/>\n        <enum name=\"osRtxErrorTZ_SaveContext_S\"      value=\"-24\" info=\"\"/>\n      </member>\n    </typedef>\n\n    <typedef name=\"rtx_th_state\" info=\"RTX5 thread state\" size=\"4\">\n      <member name=\"id\" type=\"int32_t\" offset=\"0\" info=\"RTX5 thread state ID\">\n        <enum name=\"os_ThreadInactive\"           value=\"0x00\"   info=\"\"/>\n        <enum name=\"os_ThreadReady\"              value=\"0x01\"   info=\"\"/>\n        <enum name=\"os_ThreadRunning\"            value=\"0x02\"   info=\"\"/>\n        <enum name=\"os_ThreadBlocked\"            value=\"0x03\"   info=\"\"/>\n        <enum name=\"os_ThreadTerminated\"         value=\"0x04\"   info=\"\"/>\n        <enum name=\"os_ThreadWaitingDelay\"       value=\"0x13\"   info=\"\"/>\n        <enum name=\"os_ThreadWaitingJoin\"        value=\"0x23\"   info=\"\"/>\n        <enum name=\"os_ThreadWaitingThreadFlags\" value=\"0x33\"   info=\"\"/>\n        <enum name=\"os_ThreadWaitingEventFlags\"  value=\"0x43\"   info=\"\"/>\n        <enum name=\"os_ThreadWaitingMutex\"       value=\"0x53\"   info=\"\"/>\n        <enum name=\"os_ThreadWaitingSemaphore\"   value=\"0x63\"   info=\"\"/>\n        <enum name=\"os_ThreadWaitingMemoryPool\"  value=\"0x73\"   info=\"\"/>\n        <enum name=\"os_ThreadWaitingMessageGet\"  value=\"0x83\"   info=\"\"/>\n        <enum name=\"os_ThreadWaitingMessagePut\"  value=\"0x93\"   info=\"\"/>\n      </member>\n    </typedef>\n\n    <typedef name=\"rtx_th_priority\" info=\"RTX5 thread priority\" size=\"4\">\n      <member name=\"id\" type=\"int32_t\"  offset=\"0\" info=\"RTX5 thread priority ID\">\n        <enum name=\"osPriorityNone\"         value=\"0\"  info=\"\"/>\n        <enum name=\"osPriorityIdle\"         value=\"1\"  info=\"\"/>\n        <enum name=\"osPriorityLow\"          value=\"8\"  info=\"\"/>\n        <enum name=\"osPriorityLow1\"         value=\"9\"  info=\"\"/>\n        <enum name=\"osPriorityLow2\"         value=\"10\" info=\"\"/>\n        <enum name=\"osPriorityLow3\"         value=\"11\" info=\"\"/>\n        <enum name=\"osPriorityLow4\"         value=\"12\" info=\"\"/>\n        <enum name=\"osPriorityLow5\"         value=\"13\" info=\"\"/>\n        <enum name=\"osPriorityLow6\"         value=\"14\" info=\"\"/>\n        <enum name=\"osPriorityLow7\"         value=\"15\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal\"  value=\"16\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal1\" value=\"17\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal2\" value=\"18\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal3\" value=\"19\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal4\" value=\"20\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal5\" value=\"21\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal6\" value=\"22\" info=\"\"/>\n        <enum name=\"osPriorityBelowNormal7\" value=\"23\" info=\"\"/>\n        <enum name=\"osPriorityNormal\"       value=\"24\" info=\"\"/>\n        <enum name=\"osPriorityNormal1\"      value=\"25\" info=\"\"/>\n        <enum name=\"osPriorityNormal2\"      value=\"26\" info=\"\"/>\n        <enum name=\"osPriorityNormal3\"      value=\"27\" info=\"\"/>\n        <enum name=\"osPriorityNormal4\"      value=\"28\" info=\"\"/>\n        <enum name=\"osPriorityNormal5\"      value=\"29\" info=\"\"/>\n        <enum name=\"osPriorityNormal6\"      value=\"30\" info=\"\"/>\n        <enum name=\"osPriorityNormal7\"      value=\"31\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal\"  value=\"32\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal1\" value=\"33\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal2\" value=\"34\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal3\" value=\"35\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal4\" value=\"36\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal5\" value=\"37\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal6\" value=\"38\" info=\"\"/>\n        <enum name=\"osPriorityAboveNormal7\" value=\"39\" info=\"\"/>\n        <enum name=\"osPriorityHigh\"         value=\"40\" info=\"\"/>\n        <enum name=\"osPriorityHigh1\"        value=\"41\" info=\"\"/>\n        <enum name=\"osPriorityHigh2\"        value=\"42\" info=\"\"/>\n        <enum name=\"osPriorityHigh3\"        value=\"43\" info=\"\"/>\n        <enum name=\"osPriorityHigh4\"        value=\"44\" info=\"\"/>\n        <enum name=\"osPriorityHigh5\"        value=\"45\" info=\"\"/>\n        <enum name=\"osPriorityHigh6\"        value=\"46\" info=\"\"/>\n        <enum name=\"osPriorityHigh7\"        value=\"47\" info=\"\"/>\n        <enum name=\"osPriorityRealtime\"     value=\"48\" info=\"\"/>\n        <enum name=\"osPriorityRealtime1\"    value=\"49\" info=\"\"/>\n        <enum name=\"osPriorityRealtime2\"    value=\"50\" info=\"\"/>\n        <enum name=\"osPriorityRealtime3\"    value=\"51\" info=\"\"/>\n        <enum name=\"osPriorityRealtime4\"    value=\"52\" info=\"\"/>\n        <enum name=\"osPriorityRealtime5\"    value=\"53\" info=\"\"/>\n        <enum name=\"osPriorityRealtime6\"    value=\"54\" info=\"\"/>\n        <enum name=\"osPriorityRealtime7\"    value=\"55\" info=\"\"/>\n        <enum name=\"osPriorityISR\"          value=\"56\" info=\"\"/>\n        <enum name=\"osPriorityError\"        value=\"-1\" info=\"\"/>\n      </member>\n    </typedef>\n\n    <typedef name=\"rtx_kernel_state\" info=\"RTX5 kernel state\" size=\"1\">\n      <member name=\"id\" type=\"uint8_t\" offset=\"0\" info=\"Kernel state\">\n        <enum name=\"osKernelInactive\"  value=\"0\"  info=\"Inactive\"/>\n        <enum name=\"osKernelReady\"     value=\"1\"  info=\"Ready\"/>\n        <enum name=\"osKernelRunning\"   value=\"2\"  info=\"Running\"/>\n        <enum name=\"osKernelLocked\"    value=\"3\"  info=\"Locked\"/>\n        <enum name=\"osKernelSuspended\" value=\"4\"  info=\"Suspended\"/>\n        <enum name=\"osKernelError\"     value=\"5\"  info=\"Error\"/>\n      </member>\n    </typedef>\n\n    <typedef name=\"rtx_timer_type\" info=\"RTX5 timer type\" size=\"1\">\n      <member name=\"id\" type=\"uint8_t\" offset=\"0\" info=\"Timer Type\">\n        <enum name=\"osTimerOnce\"     value=\"0\" info=\"One-shot timer\"/>\n        <enum name=\"osTimerPeriodic\" value=\"1\" info=\"Periodic timer\"/>\n      </member>\n    </typedef>\n\n    <typedef name=\"rtx_error\" info=\"OS Error Code\" size=\"4\">\n      <member name=\"id\" type=\"uint32_t\" offset=\"0\" info=\"Error Code\">\n        <enum name=\"osRtxErrorStackOverflow\"      value=\"1\" info=\"Stack overflow\"/>\n        <enum name=\"osRtxErrorISRQueueOverflow\"   value=\"2\" info=\"ISR Queue overflow\"/>\n        <enum name=\"osRtxErrorTimerQueueOverflow\" value=\"3\" info=\"User Timer Callback Queue overflow\"/>\n        <enum name=\"osRtxErrorClibSpace\"          value=\"4\" info=\"Standard C/C++ library libspace not available\"/>\n        <enum name=\"osRtxErrorClibMutex\"          value=\"5\" info=\"Standard C/C++ library mutex initialization failed\"/>\n        <enum name=\"osRtxErrorSVC\"                value=\"6\" info=\"Invalid SVC function called\"/>\n      </member>\n    </typedef>\n\n  </typedefs>\n\n  <objects>\n    <object name=\"RTX RTOS Object\">\n      <var name=\"i\"      type=\"uint32_t\" value=\"0\" />\n      <var name=\"j\"      type=\"uint32_t\" value=\"0\" />\n      <var name=\"k\"      type=\"uint32_t\" value=\"0\" />\n      <var name=\"n\"      type=\"uint32_t\" value=\"0\" />\n      <var name=\"sp\"     type=\"uint32_t\" value=\"0\" />\n      <var name=\"addr\"   type=\"uint32_t\" value=\"0\" />\n      <var name=\"ipsr\"   type=\"uint32_t\" value=\"0\" />\n      <var name=\"psp\"    type=\"uint32_t\" value=\"0\" />\n      <var name=\"v8m_ns\" type=\"uint32_t\" value=\"0\" />\n\n      <var name=\"TCB_Rd\" type=\"uint32_t\" value=\"0\" />\n      <var name=\"CCB_Rd\" type=\"uint32_t\" value=\"0\" />\n      <var name=\"SCB_Rd\" type=\"uint32_t\" value=\"0\" />\n      <var name=\"MCB_Rd\" type=\"uint32_t\" value=\"0\" />\n      <var name=\"ECB_Rd\" type=\"uint32_t\" value=\"0\" />\n      <var name=\"PCB_Rd\" type=\"uint32_t\" value=\"0\" />\n      <var name=\"QCB_Rd\" type=\"uint32_t\" value=\"0\" />\n\n      <var name=\"RTX_En\" type=\"uint8_t\" value=\"0\" />\n      <var name=\"TCB_En\" type=\"uint8_t\" value=\"0\" />\n      <var name=\"CCB_En\" type=\"uint8_t\" value=\"0\" />\n      <var name=\"SCB_En\" type=\"uint8_t\" value=\"0\" />\n      <var name=\"MCB_En\" type=\"uint8_t\" value=\"0\" />\n      <var name=\"ECB_En\" type=\"uint8_t\" value=\"0\" />\n      <var name=\"PCB_En\" type=\"uint8_t\" value=\"0\" />\n      <var name=\"QCB_En\" type=\"uint8_t\" value=\"0\" />\n      <var name=\"MUC_En\" type=\"uint8_t\" value=\"0\" />\n\n      <var name=\"StaticMp_En\" type=\"uint8_t\" value=\"0\" />\n\n      <var name=\"MUC_Thread_En\"     type=\"uint8_t\" value=\"0\" />\n      <var name=\"MUC_Timer_En\"      type=\"uint8_t\" value=\"0\" />\n      <var name=\"MUC_EventFlags_En\" type=\"uint8_t\" value=\"0\" />\n      <var name=\"MUC_Mutex_En\"      type=\"uint8_t\" value=\"0\" />\n      <var name=\"MUC_Semaphore_En\"  type=\"uint8_t\" value=\"0\" />\n      <var name=\"MUC_MemPool_En\"    type=\"uint8_t\" value=\"0\" />\n      <var name=\"MUC_MsgQueue_En\"   type=\"uint8_t\" value=\"0\" />\n\n      <var name=\"V_Major\" type=\"uint32_t\" value=\"0\"/>\n      <var name=\"V_Minor\" type=\"uint32_t\" value=\"0\"/>\n      <var name=\"V_Patch\" type=\"uint32_t\" value=\"0\"/>\n\n      <!-- Check TrustZone symbol existence -->\n      <calc>\n        v8m_ns = __Symbol_exists(\"TZ_InitContextSystem_S\");\n      </calc>\n\n      <!-- Read main OS information and configuration structures -->\n      <read name=\"os_Info\"   type=\"osRtxInfo_t\"   symbol=\"osRtxInfo\"/>\n      <read name=\"os_Config\" type=\"osRtxConfig_t\" symbol=\"osRtxConfig\" const=\"1\"/>\n\n      <calc>\n        os_Config.stack_check  = (os_Config.flags >> 1) &amp; 1;\n        os_Config.stack_wmark  = (os_Config.flags >> 2) &amp; 1;\n        os_Config.safety_feat  = (os_Config.flags >> 3) &amp; 1;\n        os_Config.safety_class = (os_Config.flags >> 4) &amp; 1;\n        os_Config.exec_zone    = (os_Config.flags >> 5) &amp; 1;\n        os_Config.watchdog     = (os_Config.flags >> 6) &amp; 1;\n        os_Config.obj_check    = (os_Config.flags >> 7) &amp; 1;\n        os_Config.svc_check    = (os_Config.flags >> 8) &amp; 1;\n      </calc>\n\n      <calc cond=\"((os_Info.version / 10000000) == 5) &amp;&amp; (os_Info.kernel_state &gt; 0) &amp;&amp; (os_Info.kernel_state &lt; 5)\">\n        RTX_En = 1;\n      </calc>\n\n      <calc cond=\"RTX_En\">\n        V_Major =  os_Info.version / 10000000;\n        V_Minor = (os_Info.version / 10000) % 1000;\n        V_Patch =  os_Info.version % 10000;\n      </calc>\n\n      <calc cond=\"RTX_En &amp;&amp; (os_Config.mpi_thread || os_Config.mpi_timer || os_Config.mpi_event_flags || os_Config.mpi_mutex || os_Config.mpi_semaphore || os_Config.mpi_memory_pool || os_Config.mpi_message_queue)\">\n        StaticMp_En = 1;\n      </calc>\n\n      <!-- Read ISR FIFO queue -->\n      <read name=\"ISR_FIFO\" cond=\"RTX_En\" type=\"uint32_t\" offset=\"os_Config.isr_queue_data\" size=\"os_Config.isr_queue_max\"/>\n\n      <!-- Read control block sections info structure -->\n      <read name=\"cb_Sections\" cond=\"__Symbol_exists (&quot;os_cb_sections&quot;)\" type=\"rtx_sections_t\" symbol=\"os_cb_sections\" const=\"1\"/>/>\n\n      <!-- Determine section sizes -->\n      <calc cond=\"RTX_En &amp;&amp; __Symbol_exists (&quot;os_cb_sections&quot;)\">\n        TCB_Rd = cb_Sections.thread_cb_end    - cb_Sections.thread_cb_start;\n        CCB_Rd = cb_Sections.timer_cb_end     - cb_Sections.timer_cb_start;\n        ECB_Rd = cb_Sections.evflags_cb_end   - cb_Sections.evflags_cb_start;\n        MCB_Rd = cb_Sections.mutex_cb_end     - cb_Sections.mutex_cb_start;\n        SCB_Rd = cb_Sections.semaphore_cb_end - cb_Sections.semaphore_cb_start;\n        PCB_Rd = cb_Sections.mempool_cb_end   - cb_Sections.mempool_cb_start;\n        QCB_Rd = cb_Sections.msgqueue_cb_end  - cb_Sections.msgqueue_cb_start;\n      </calc>\n\n      <!-- Determine number of control blocks to read -->\n      <calc cond=\"TCB_Rd\"> TCB_Rd /= 80; </calc>\n      <calc cond=\"CCB_Rd\"> CCB_Rd /= 32; </calc>\n      <calc cond=\"ECB_Rd\"> ECB_Rd /= 16; </calc>\n      <calc cond=\"MCB_Rd\"> MCB_Rd /= 28; </calc>\n      <calc cond=\"SCB_Rd\"> SCB_Rd /= 16; </calc>\n      <calc cond=\"PCB_Rd\"> PCB_Rd /= 36; </calc>\n      <calc cond=\"QCB_Rd\"> QCB_Rd /= 52; </calc>\n\n      <!-- Read object control blocks using sections info -->\n      <readlist name=\"TCB\" cond=\"TCB_Rd\" type=\"osRtxThread_t\"       offset=\"cb_Sections.thread_cb_start\"    count=\"TCB_Rd\"/>\n      <readlist name=\"CCB\" cond=\"CCB_Rd\" type=\"osRtxTimer_t\"        offset=\"cb_Sections.timer_cb_start\"     count=\"CCB_Rd\"/>\n      <readlist name=\"ECB\" cond=\"ECB_Rd\" type=\"osRtxEventFlags_t\"   offset=\"cb_Sections.evflags_cb_start\"   count=\"ECB_Rd\"/>\n      <readlist name=\"MCB\" cond=\"MCB_Rd\" type=\"osRtxMutex_t\"        offset=\"cb_Sections.mutex_cb_start\"     count=\"MCB_Rd\"/>\n      <readlist name=\"PCB\" cond=\"PCB_Rd\" type=\"osRtxMemoryPool_t\"   offset=\"cb_Sections.mempool_cb_start\"   count=\"PCB_Rd\"/>\n      <readlist name=\"SCB\" cond=\"SCB_Rd\" type=\"osRtxSemaphore_t\"    offset=\"cb_Sections.semaphore_cb_start\" count=\"SCB_Rd\"/>\n      <readlist name=\"QCB\" cond=\"QCB_Rd\" type=\"osRtxMessageQueue_t\" offset=\"cb_Sections.msgqueue_cb_start\"  count=\"QCB_Rd\"/>\n\n      <!-- Read statically allocated control blocks -->\n      <readlist name=\"cfg_mp_stack\"     cond=\"os_Config.mpi_stack\"         type=\"osRtxMpInfo_t\" offset=\"os_Config.mpi_stack\"         const=\"1\" count=\"1\" init=\"1\"/>\n      <readlist name=\"cfg_mp_thread\"    cond=\"os_Config.mpi_thread\"        type=\"osRtxMpInfo_t\" offset=\"os_Config.mpi_thread\"        const=\"1\" count=\"1\" init=\"1\"/>\n      <readlist name=\"cfg_mp_timer\"     cond=\"os_Config.mpi_timer\"         type=\"osRtxMpInfo_t\" offset=\"os_Config.mpi_timer\"         const=\"1\" count=\"1\" init=\"1\"/>\n      <readlist name=\"cfg_mp_events\"    cond=\"os_Config.mpi_event_flags\"   type=\"osRtxMpInfo_t\" offset=\"os_Config.mpi_event_flags\"   const=\"1\" count=\"1\" init=\"1\"/>\n      <readlist name=\"cfg_mp_mutex\"     cond=\"os_Config.mpi_mutex\"         type=\"osRtxMpInfo_t\" offset=\"os_Config.mpi_mutex\"         const=\"1\" count=\"1\" init=\"1\"/>\n      <readlist name=\"cfg_mp_semaphore\" cond=\"os_Config.mpi_semaphore\"     type=\"osRtxMpInfo_t\" offset=\"os_Config.mpi_semaphore\"     const=\"1\" count=\"1\" init=\"1\"/>\n      <readlist name=\"cfg_mp_mpool\"     cond=\"os_Config.mpi_memory_pool\"   type=\"osRtxMpInfo_t\" offset=\"os_Config.mpi_memory_pool\"   const=\"1\" count=\"1\" init=\"1\"/>\n      <readlist name=\"cfg_mp_mqueue\"    cond=\"os_Config.mpi_message_queue\" type=\"osRtxMpInfo_t\" offset=\"os_Config.mpi_message_queue\" const=\"1\" count=\"1\" init=\"1\"/>\n\n      <!-- Read idle and timer thread control blocks -->\n      <readlist name=\"TCB\" cond=\"RTX_En &amp;&amp; (TCB_Rd == 0) &amp;&amp; os_Info.thread_idle\"  type=\"osRtxThread_t\" offset=\"os_Info.thread_idle\"  count=\"1\" />\n      <readlist name=\"TCB\" cond=\"RTX_En &amp;&amp; (TCB_Rd == 0) &amp;&amp; os_Info.timer_thread\" type=\"osRtxThread_t\" offset=\"os_Info.timer_thread\" count=\"1\" />\n\n      <!-- Read thread control blocks (MPI) -->\n      <readlist name=\"mp_thread\" cond=\"RTX_En &amp;&amp; (TCB_Rd == 0) &amp;&amp; os_Info.mpi_thread\" type=\"osRtxMpInfo_t\" offset=\"os_Info.mpi_thread\"   count=\"1\" init=\"1\"/>\n      <readlist name=\"TCB\"       cond=\"RTX_En &amp;&amp; (TCB_Rd == 0) &amp;&amp; os_Info.mpi_thread\" type=\"osRtxThread_t\" offset=\"mp_thread.block_base\" count=\"mp_thread.max_blocks\" />\n\n      <!-- Read timer control blocks (MPI) -->\n      <readlist name=\"mp_timer\" cond=\"RTX_En &amp;&amp; (CCB_Rd == 0) &amp;&amp; os_Info.mpi_timer\" type=\"osRtxMpInfo_t\" offset=\"os_Info.mpi_timer\"   count=\"1\" init=\"1\"/>\n      <readlist name=\"CCB\"      cond=\"RTX_En &amp;&amp; (CCB_Rd == 0) &amp;&amp; os_Info.mpi_timer\" type=\"osRtxTimer_t\"  offset=\"mp_timer.block_base\" count=\"mp_timer.max_blocks\" />\n\n      <!-- Read event flags control blocks (MPI) -->\n      <readlist name=\"mp_events\" cond=\"RTX_En &amp;&amp; (ECB_Rd == 0) &amp;&amp; os_Info.mpi_event_flags\" type=\"osRtxMpInfo_t\"     offset=\"os_Info.mpi_event_flags\" count=\"1\" init=\"1\"/>\n      <readlist name=\"ECB\"       cond=\"RTX_En &amp;&amp; (ECB_Rd == 0) &amp;&amp; os_Info.mpi_event_flags\" type=\"osRtxEventFlags_t\" offset=\"mp_events.block_base\"    count=\"mp_events.max_blocks\" />\n\n      <!-- Read mutex control blocks (MPI) -->\n      <readlist name=\"mp_mutex\" cond=\"RTX_En &amp;&amp; (MCB_Rd == 0) &amp;&amp; os_Info.mpi_mutex\" type=\"osRtxMpInfo_t\" offset=\"os_Info.mpi_mutex\"   count=\"1\" init=\"1\"/>\n      <readlist name=\"MCB\"      cond=\"RTX_En &amp;&amp; (MCB_Rd == 0) &amp;&amp; os_Info.mpi_mutex\" type=\"osRtxMutex_t\"  offset=\"mp_mutex.block_base\" count=\"mp_mutex.max_blocks\" />\n\n      <!-- Read semaphore control blocks (MPI) -->\n      <readlist name=\"mp_semaphore\" cond=\"RTX_En &amp;&amp; (SCB_Rd == 0) &amp;&amp; os_Info.mpi_semaphore\" type=\"osRtxMpInfo_t\"    offset=\"os_Info.mpi_semaphore\"   count=\"1\" init=\"1\"/>\n      <readlist name=\"SCB\"          cond=\"RTX_En &amp;&amp; (SCB_Rd == 0) &amp;&amp; os_Info.mpi_semaphore\" type=\"osRtxSemaphore_t\" offset=\"mp_semaphore.block_base\" count=\"mp_semaphore.max_blocks\" />\n\n      <!-- Read memory pool control blocks (MPI) -->\n      <readlist name=\"mp_mpool\" cond=\"RTX_En &amp;&amp; (PCB_Rd == 0) &amp;&amp; os_Info.mpi_memory_pool\" type=\"osRtxMpInfo_t\"     offset=\"os_Info.mpi_memory_pool\" count=\"1\" init=\"1\"/>\n      <readlist name=\"PCB\"      cond=\"RTX_En &amp;&amp; (PCB_Rd == 0) &amp;&amp; os_Info.mpi_memory_pool\" type=\"osRtxMemoryPool_t\" offset=\"mp_mpool.block_base\"     count=\"mp_mpool.max_blocks\" />\n\n      <!-- Read message queue control blocks (MPI) -->\n      <readlist name=\"mp_mqueue\" cond=\"RTX_En &amp;&amp; (QCB_Rd == 0) &amp;&amp; os_Info.mpi_message_queue\" type=\"osRtxMpInfo_t\"       offset=\"os_Info.mpi_message_queue\" count=\"1\" init=\"1\"/>\n      <readlist name=\"QCB\"       cond=\"RTX_En &amp;&amp; (QCB_Rd == 0) &amp;&amp; os_Info.mpi_message_queue\" type=\"osRtxMessageQueue_t\" offset=\"mp_mqueue.block_base\"      count=\"mp_mqueue.max_blocks\" />\n\n      <!-- Read stack memory header and block list (MEM) -->\n      <readlist name=\"mem_head_stack\" cond=\"RTX_En &amp;&amp; os_Config.mem_stack_addr\" type=\"mem_head_t\"  offset=\"os_Config.mem_stack_addr\" count=\"1\"/>\n      <readlist name=\"mem_list_stack\" cond=\"RTX_En &amp;&amp; os_Config.mem_stack_addr\" type=\"mem_block_t\" offset=\"os_Config.mem_stack_addr + 8\" next=\"next\"/>\n\n      <calc cond=\"RTX_En &amp;&amp; os_Config.mem_stack_addr\"> mem_head_stack.max_used = mem_list_stack[mem_list_stack._count-1].len; </calc>\n\n      <!-- Read memory pool data memory header and block list (MEM) -->\n      <readlist name=\"mem_head_mp_data\" cond=\"RTX_En &amp;&amp; os_Config.mem_mp_data_addr\" type=\"mem_head_t\"  offset=\"os_Config.mem_mp_data_addr\" count=\"1\"/>\n      <readlist name=\"mem_list_mp_data\" cond=\"RTX_En &amp;&amp; os_Config.mem_mp_data_addr\" type=\"mem_block_t\" offset=\"os_Config.mem_mp_data_addr + 8\" next=\"next\"/>\n\n      <calc cond=\"RTX_En &amp;&amp; os_Config.mem_mp_data_addr\"> mem_head_mp_data.max_used = mem_list_mp_data[mem_list_mp_data._count-1].len; </calc>\n\n      <!-- Read message queue data memory header and block list (MEM) -->\n      <readlist name=\"mem_head_mq_data\" cond=\"RTX_En &amp;&amp; os_Config.mem_mq_data_addr\" type=\"mem_head_t\"  offset=\"os_Config.mem_mq_data_addr\" count=\"1\"/>\n      <readlist name=\"mem_list_mq_data\" cond=\"RTX_En &amp;&amp; os_Config.mem_mq_data_addr\" type=\"mem_block_t\" offset=\"os_Config.mem_mq_data_addr + 8\" next=\"next\"/>\n\n      <calc cond=\"RTX_En &amp;&amp; os_Config.mem_mq_data_addr\"> mem_head_mq_data.max_used = mem_list_mq_data[mem_list_mq_data._count-1].len; </calc>\n\n      <!-- Read common memory header and block list (MEM) -->\n      <readlist name=\"mem_head_com\" cond=\"RTX_En &amp;&amp; os_Config.mem_common_addr\" type=\"mem_head_t\"  offset=\"os_Config.mem_common_addr\" count=\"1\"/>\n      <readlist name=\"mem_list_com\" cond=\"RTX_En &amp;&amp; os_Config.mem_common_addr\" type=\"mem_block_t\" offset=\"os_Config.mem_common_addr + 8\" next=\"next\"/>\n\n      <calc cond=\"RTX_En &amp;&amp; os_Config.mem_common_addr\"> mem_head_com.max_used = mem_list_com[mem_list_com._count-1].len; </calc>\n\n      <!-- Extract control blocks located in the common memory -->\n      <list cond=\"mem_list_com._count > 1\" name=\"i\" start=\"0\" limit=\"mem_list_com._count-1\">\n        <calc>\n          addr  = mem_list_com[i]._addr;\n          addr += 8;\n        </calc>\n\n        <!-- Read Thread Control Block -->\n        <readlist cond=\"(mem_list_com[i].len &amp; 1) &amp;&amp; (mem_list_com[i].id == 0xF1)\" name=\"TCB\" type=\"osRtxThread_t\" offset=\"addr\" count=\"1\" />\n\n        <!-- Read Timer Control Block -->\n        <readlist cond=\"(mem_list_com[i].len &amp; 1) &amp;&amp; (mem_list_com[i].id == 0xF2)\" name=\"CCB\" type=\"osRtxTimer_t\" offset=\"addr\" count=\"1\" />\n\n        <!-- Read EventFlags Control Block -->\n        <readlist cond=\"(mem_list_com[i].len &amp; 1) &amp;&amp; (mem_list_com[i].id == 0xF3)\" name=\"ECB\" type=\"osRtxEventFlags_t\" offset=\"addr\" count=\"1\" />\n\n        <!-- Read Mutex Control Block -->\n        <readlist cond=\"(mem_list_com[i].len &amp; 1) &amp;&amp; (mem_list_com[i].id == 0xF5)\" name=\"MCB\" type=\"osRtxMutex_t\" offset=\"addr\" count=\"1\" />\n\n        <!-- Read Semaphore Control Block -->\n        <readlist cond=\"(mem_list_com[i].len &amp; 1) &amp;&amp; (mem_list_com[i].id == 0xF6)\" name=\"SCB\" type=\"osRtxSemaphore_t\" offset=\"addr\" count=\"1\" />\n\n        <!-- Read MemoryPool Control Block -->\n        <readlist cond=\"(mem_list_com[i].len &amp; 1) &amp;&amp; (mem_list_com[i].id == 0xF7)\" name=\"PCB\" type=\"osRtxMemoryPool_t\" offset=\"addr\" count=\"1\" />\n\n        <!-- Read MessageQueue Control Block -->\n        <readlist cond=\"(mem_list_com[i].len &amp; 1) &amp;&amp; (mem_list_com[i].id == 0xFA)\" name=\"QCB\" type=\"osRtxMessageQueue_t\" offset=\"addr\" count=\"1\" />\n      </list>\n\n      <!-- Read thread watchdog list -->\n      <readlist name=\"WDL\" cond=\"RTX_En &amp;&amp; os_Config.watchdog &amp;&amp; os_Info.thread_wdog_list\" type=\"osRtxThread_t\" offset=\"os_Info.thread_wdog_list\" next=\"wdog_next\" init=\"1\"/>\n\n      <!-- Validate and process Thread control blocks -->\n      <list name=\"i\" start=\"0\" limit=\"TCB._count\">\n        <calc>\n          TCB[i].cb_valid = (TCB[i].id == 0xF1) &amp;&amp; (TCB[i].state != 0) &amp;&amp; (TCB[i].sp != 0);\n          TCB[i].sp_valid = 1;\n        </calc>\n\n        <!-- Set Round Robin time tick from the running thread tick value -->\n        <calc cond=\"(TCB[i].state == 2) &amp;&amp; os_Config.robin_timeout\">\n          os_Info.robin_tick = TCB[i].delay;\n        </calc>\n\n        <!-- Stack pointer for running thread -->\n        <calc cond=\"(TCB[i].state == 2) &amp;&amp; (__Running == 0)\">\n          ipsr = __GetRegVal(\"XPSR\") &amp; 0x01FF;\n          psp  = (v8m_ns == 0) ? (__GetRegVal(\"PSP\")) : (__GetRegVal(\"PSP_NS\"));\n          psp  = (psp == 0) ? (TCB[i].sp) : (psp);\n\n          sp = ((ipsr != 0) &amp;&amp; (ipsr &lt; 16)) ? (TCB[i].sp) : (psp);\n\n          TCB[i].sp_valid = ((ipsr != 0) &amp;&amp; (ipsr &lt; 16)) ? (0) : (1);\n        </calc>\n\n        <calc cond=\"(TCB[i].state == 2) &amp;&amp; (__Running == 1)\">\n          TCB[i].sp_valid = 0;\n          sp = TCB[i].sp;\n        </calc>\n\n        <!-- Stack pointer for waiting thread -->\n        <calc cond=\"TCB[i].state != 2\">\n          sp = TCB[i].sp;\n        </calc>\n\n        <!-- Save current stack pointer -->\n        <calc>\n          TCB[i].stack_cur = sp;\n        </calc>\n\n        <!-- Determine current stack usage -->\n        <calc cond=\"TCB[i].sp != 0\">\n          TCB[i].stack_curb  = TCB[i].stack_mem + TCB[i].stack_size;\n          TCB[i].stack_curb -= sp;\n          TCB[i].stack_curp  = TCB[i].stack_curb;\n          TCB[i].stack_curp *= 100;\n          TCB[i].stack_curp /= TCB[i].stack_size;\n        </calc>\n\n        <!-- Check for current sp overflow -->\n        <calc cond=\"TCB[i].sp != 0\">\n          TCB[i].stack_over = (sp &lt;= TCB[i].stack_mem) ? 1 : 0;\n        </calc>\n\n        <!-- Check also control values to determine maximum stack usage -->\n        <calc cond=\"(os_Config.stack_wmark != 0) &amp;&amp; (TCB[i].sp != 0) &amp;&amp; (TCB[i].stack_over == 0) &amp;&amp; (TCB[i].stack_size &lt; 65536)\">\n          TCB[i].stack_val  = __CalcMemUsed (TCB[i].stack_mem, sp - TCB[i].stack_mem, 0xCCCCCCCC, 0xE25A2EA5);\n          TCB[i].stack_over =  TCB[i].stack_val >> 31;\n          TCB[i].stack_maxb = (TCB[i].stack_mem + TCB[i].stack_size) - sp;\n          TCB[i].stack_maxb += TCB[i].stack_val &amp; 0xFFFFF;\n          TCB[i].stack_maxp = (TCB[i].stack_maxb * 100)/ TCB[i].stack_size;\n        </calc>\n\n        <!-- Set max usage in case of stack overflow -->\n        <calc cond=\"(TCB[i].sp != 0) &amp;&amp; (TCB[i].stack_over != 0)\">\n          TCB[i].stack_maxb = TCB[i].stack_size;\n          TCB[i].stack_maxp = 100;\n        </calc>\n\n        <!-- Adjust maximum usage in case if current sp below max -->\n        <calc cond=\"(TCB[i].sp != 0) &amp;&amp; (TCB[i].stack_curb &gt;= TCB[i].stack_maxb)\">\n          TCB[i].stack_maxb = TCB[i].stack_curb;\n          TCB[i].stack_maxp = TCB[i].stack_curp;\n        </calc>\n\n        <calc>\n          TCB[i].ex_delay = TCB[i].delay;\n        </calc>\n\n        <!-- Create Thread Delay List (TDL) -->\n        <readlist cond=\"TCB[i].delay != -1\" name=\"TDL\" type=\"osRtxThread_t\" offset=\"TCB[i].delay_prev\" next=\"delay_prev\" init=\"1\"/>\n\n        <list cond=\"TCB[i].delay != -1\" name=\"j\" start=\"0\" limit=\"TDL._count\">\n          <calc>\n            TCB[i].ex_delay += TDL[j].delay;\n          </calc>\n        </list>\n\n        <!-- Determine thread absolute watchdog tick value -->\n        <calc cond=\"os_Config.watchdog\">\n          k = 0;\n        </calc>\n\n        <list cond=\"os_Config.watchdog\" name=\"j\" start=\"0\" limit=\"WDL._count\">\n          <calc cond=\"k == 0\">\n            TCB[i].wd_tick += WDL[j].wdog_tick;\n          </calc>\n\n          <calc cond=\"TCB[i]._addr == WDL[j]._addr\">\n            k = 1;\n          </calc>\n        </list>\n\n        <!-- Watchdog is running for a thread that was found in the watchdog list -->\n        <calc cond=\"os_Config.safety_feat\">\n            TCB[i].wd_state = k;\n        </calc>\n      </list>\n\n      <!-- Validate and process Timer control blocks -->\n      <list name=\"i\" start=\"0\" limit=\"CCB._count\">\n        <calc>\n          CCB[i].cb_valid = (CCB[i].id == 0xF2) &amp;&amp; (CCB[i].state != 0);\n          CCB[i].ex_tick  = CCB[i].tick;\n        </calc>\n\n        <!-- Create Timer Execution List (TEL) -->\n        <readlist name=\"TEL\" type=\"osRtxTimer_t\" offset=\"CCB[i].prev\" next=\"prev\" init=\"1\"/>\n\n        <list name=\"j\" start=\"0\" limit=\"TEL._count\">\n          <calc>\n            CCB[i].ex_tick += TEL[j].tick;\n          </calc>\n        </list>\n      </list>\n\n      <!-- Validate and process EventFlags control blocks -->\n      <calc> k = 0; </calc>\n\n      <list name=\"i\" start=\"0\" limit=\"ECB._count\">\n        <calc>\n          ECB[i].cb_valid = (ECB[i].id == 0xF3);\n          ECB[i].wl_idx = k;\n          ECB[i].wl_cnt = 0;\n        </calc>\n\n        <!-- Create a list of threads waiting for event flags -->\n        <readlist name=\"EWL\" type=\"osRtxThread_t\" offset=\"ECB[i].thread_list\" next=\"thread_next\" cond=\"ECB[i].thread_list\"/>\n\n        <calc cond=\"ECB[i].thread_list\">\n          ECB[i].wl_cnt = (EWL._count - k);\n          k = EWL._count;\n        </calc>\n      </list>\n\n      <!-- Validate and process Mutex control blocks -->\n      <calc> k = 0; </calc>\n\n      <list cond=\"MCB._count\" name=\"i\" start=\"0\" limit=\"MCB._count\">\n        <calc>\n          MCB[i].cb_valid = (MCB[i].id == 0xF5);\n          MCB[i].wl_idx = k;\n          MCB[i].wl_cnt = 0;\n        </calc>\n\n        <!-- Create a list of threads waiting for mutex -->\n        <readlist name=\"MWL\" type=\"osRtxThread_t\" offset=\"MCB[i].thread_list\" next=\"thread_next\" cond=\"MCB[i].thread_list\"/>\n\n        <calc cond=\"MCB[i].thread_list\">\n          MCB[i].wl_cnt = (MWL._count - k);\n          k = MWL._count;\n        </calc>\n      </list>\n\n\n      <!-- Validate and process semaphore control blocks -->\n      <calc> k = 0; </calc>\n\n      <list cond=\"SCB._count\" name=\"i\" start=\"0\" limit=\"SCB._count\">\n        <calc>\n          SCB[i].cb_valid = (SCB[i].id == 0xF6);\n          SCB[i].wl_idx = k;\n          SCB[i].wl_cnt = 0;\n        </calc>\n\n        <!-- Create a list of threads waiting for semaphore -->\n        <readlist name=\"SWL\" type=\"osRtxThread_t\" offset=\"SCB[i].thread_list\" next=\"thread_next\" cond=\"SCB[i].thread_list\"/>\n\n        <calc cond=\"SCB[i].thread_list\">\n          SCB[i].wl_cnt = (SWL._count - k);\n          k = SWL._count;\n        </calc>\n      </list>\n\n      <!-- Validate and process MemoryPool control blocks -->\n      <calc> k = 0; </calc>\n\n      <list cond=\"PCB._count\" name=\"i\" start=\"0\" limit=\"PCB._count\">\n        <calc>\n          PCB[i].cb_valid = (PCB[i].id == 0xF7);\n          PCB[i].wl_idx = k;\n          PCB[i].wl_cnt = 0;\n        </calc>\n\n        <!-- Create a list of threads waiting for memory pool -->\n        <readlist name=\"PWL\" type=\"osRtxThread_t\" offset=\"PCB[i].thread_list\" next=\"thread_next\" cond=\"PCB[i].thread_list\"/>\n\n        <calc cond=\"PCB[i].thread_list\">\n          PCB[i].wl_cnt = (PWL._count - k);\n          k = PWL._count;\n        </calc>\n      </list>\n\n\n      <!-- Validate and process MessageQueue control blocks -->\n      <calc> k = 0; j = 0; </calc>\n\n      <list cond=\"QCB._count\" name=\"i\" start=\"0\" limit=\"QCB._count\">\n        <calc>\n          QCB[i].cb_valid = (QCB[i].id == 0xFA);\n          QCB[i].wl_idx = k;\n          QCB[i].wl_cnt = 0;\n        </calc>\n\n        <!-- Create a list of threads waiting for message queue -->\n        <readlist name=\"QWL\" type=\"osRtxThread_t\" offset=\"QCB[i].thread_list\" next=\"thread_next\" cond=\"QCB[i].thread_list\"/>\n\n        <calc cond=\"QCB[i].thread_list\">\n          QCB[i].wl_cnt = (QWL._count - k);\n          k = QWL._count;\n        </calc>\n\n        <!-- Create a list of enqueued messages -->\n        <readlist name=\"QML\" type=\"osRtxMessage_t\" offset=\"QCB[i].msg_first\" next=\"next\" cond=\"QCB[i].msg_first\"/>\n\n        <calc>\n          QCB[i].ml_idx = j;\n          QCB[i].ml_cnt = (QML._count - j)\n          j = QML._count;\n        </calc>\n      </list>\n\n      <!-- Determine the addresses of enqueued messages -->\n      <list cond=\"QML._count\" name=\"i\" start=\"0\" limit=\"QML._count\">\n        <calc>\n          QML[i].addr  = QML[i]._addr;\n          QML[i].addr += 12;\n        </calc>\n      </list>\n\n      <!-- Read Object Memory Usage Counters (MUC) -->\n      <calc cond=\"__Symbol_exists (&quot;osRtxThreadMemUsage&quot;)\">       MUC_Thread_En     = 1; </calc>\n      <calc cond=\"__Symbol_exists (&quot;osRtxTimerMemUsage&quot;)\">        MUC_Timer_En      = 1; </calc>\n      <calc cond=\"__Symbol_exists (&quot;osRtxEventFlagsMemUsage&quot;)\">   MUC_EventFlags_En = 1; </calc>\n      <calc cond=\"__Symbol_exists (&quot;osRtxMutexMemUsage&quot;)\">        MUC_Mutex_En      = 1; </calc>\n      <calc cond=\"__Symbol_exists (&quot;osRtxSemaphoreMemUsage&quot;)\">    MUC_Semaphore_En  = 1; </calc>\n      <calc cond=\"__Symbol_exists (&quot;osRtxMemoryPoolMemUsage&quot;)\">   MUC_MemPool_En    = 1; </calc>\n      <calc cond=\"__Symbol_exists (&quot;osRtxMessageQueueMemUsage&quot;)\"> MUC_MsgQueue_En   = 1; </calc>\n\n      <calc>\n        MUC_En = MUC_Thread_En | MUC_Timer_En | MUC_EventFlags_En | MUC_Mutex_En | MUC_Semaphore_En | MUC_MemPool_En | MUC_MsgQueue_En;\n      </calc>\n\n      <readlist name=\"MUC_Thread\"     type=\"osRtxObjectMemUsage_t\" symbol=\"osRtxThreadMemUsage\"       count=\"1\" init=\"1\" cond=\"MUC_Thread_En\"/>\n      <readlist name=\"MUC_Timer\"      type=\"osRtxObjectMemUsage_t\" symbol=\"osRtxTimerMemUsage\"        count=\"1\" init=\"1\" cond=\"MUC_Timer_En\"/>\n      <readlist name=\"MUC_EventFlags\" type=\"osRtxObjectMemUsage_t\" symbol=\"osRtxEventFlagsMemUsage\"   count=\"1\" init=\"1\" cond=\"MUC_EventFlags_En\"/>\n      <readlist name=\"MUC_Mutex\"      type=\"osRtxObjectMemUsage_t\" symbol=\"osRtxMutexMemUsage\"        count=\"1\" init=\"1\" cond=\"MUC_Mutex_En\"/>\n      <readlist name=\"MUC_Semaphore\"  type=\"osRtxObjectMemUsage_t\" symbol=\"osRtxSemaphoreMemUsage\"    count=\"1\" init=\"1\" cond=\"MUC_Semaphore_En\"/>\n      <readlist name=\"MUC_MemPool\"    type=\"osRtxObjectMemUsage_t\" symbol=\"osRtxMemoryPoolMemUsage\"   count=\"1\" init=\"1\" cond=\"MUC_MemPool_En\"/>\n      <readlist name=\"MUC_MsgQueue\"   type=\"osRtxObjectMemUsage_t\" symbol=\"osRtxMessageQueueMemUsage\" count=\"1\" init=\"1\" cond=\"MUC_MsgQueue_En\"/>\n\n\n      <!-- Determine what to display -->\n      <list cond=\"TCB._count\" name=\"i\" start=\"0\" limit=\"TCB._count\">\n        <calc>TCB_En += TCB[i].cb_valid; </calc>\n\n        <calc cond=\"TCB[i].cb_valid == 0\"> TCB[i].out_type = 0;</calc>\n        <calc cond=\"TCB[i].cb_valid &amp;&amp; (TCB[i].name == 0) &amp;&amp; (os_Config.stack_wmark == 0)\"> TCB[i].out_type = 1; </calc>\n        <calc cond=\"TCB[i].cb_valid &amp;&amp; (TCB[i].name == 0) &amp;&amp; (os_Config.stack_wmark != 0)\"> TCB[i].out_type = 2; </calc>\n        <calc cond=\"TCB[i].cb_valid &amp;&amp; (TCB[i].name != 0) &amp;&amp; (os_Config.stack_wmark == 0)\"> TCB[i].out_type = 3; </calc>\n        <calc cond=\"TCB[i].cb_valid &amp;&amp; (TCB[i].name != 0) &amp;&amp; (os_Config.stack_wmark != 0)\"> TCB[i].out_type = 4; </calc>\n\n        <calc cond=\"TCB[i].sp_valid == 0\"> TCB[i].out_type += 4; </calc>\n      </list>\n      <list cond=\"CCB._count\" name=\"i\" start=\"0\" limit=\"CCB._count\">\n        <calc>CCB_En += CCB[i].cb_valid; </calc>\n      </list>\n      <list cond=\"SCB._count\" name=\"i\" start=\"0\" limit=\"SCB._count\">\n        <calc>SCB_En += SCB[i].cb_valid; </calc>\n      </list>\n      <list cond=\"MCB._count\" name=\"i\" start=\"0\" limit=\"MCB._count\">\n        <calc>MCB_En += MCB[i].cb_valid; </calc>\n      </list>\n      <list cond=\"ECB._count\" name=\"i\" start=\"0\" limit=\"ECB._count\">\n        <calc>ECB_En += ECB[i].cb_valid; </calc>\n      </list>\n      <list cond=\"PCB._count\" name=\"i\" start=\"0\" limit=\"PCB._count\">\n        <calc>PCB_En += PCB[i].cb_valid; </calc>\n      </list>\n      <list cond=\"QCB._count\" name=\"i\" start=\"0\" limit=\"QCB._count\">\n        <calc>QCB_En += QCB[i].cb_valid; </calc>\n      </list>\n\n      <out name=\"RTX RTOS\">\n        <!-- System -->\n        <item property=\"System\" value=\"\">\n          <item property=\"Kernel ID\"    value=\"RTX V%d[V_Major].%d[V_Minor].%d[V_Patch]\" cond=\"RTX_En != 0\"/>\n          <item property=\"Kernel State\" value=\"osKernelInactive\"         cond=\"RTX_En == 0\"/>\n          <item property=\"Kernel State\" value=\"%E[os_Info.kernel_state]\" cond=\"RTX_En != 0\"/>\n          <item>\n            <print property=\"Kernel Protect\" value=\"osThreadPrivileged: %t[(os_Info.kernel_protect &amp; 1) ? &quot;Disabled&quot; : &quot;Enabled&quot;]\"                                               cond=\"(os_Config.safety_feat == 1) &amp;&amp; (os_Config.safety_class == 0) &amp;&amp; (RTX_En != 0)\" />\n            <print property=\"Kernel Protect\" value=\"osThreadPrivileged: %t[(os_Info.kernel_protect &amp; 1) ? &quot;Disabled&quot; : &quot;Enabled&quot;], osSafetyClass(%d[os_Info.kernel_protect/16])\" cond=\"(os_Config.safety_feat == 1) &amp;&amp; (os_Config.safety_class == 1) &amp;&amp; (RTX_En != 0)\" />\n          </item>\n          <item property=\"Kernel Tick Count\"      value=\"%d[os_Info.kernel_tick]\"     cond=\"RTX_En != 0\"/>\n          <item property=\"Kernel Tick Frequency\"  value=\"%d[os_Config.tick_freq]\"     cond=\"RTX_En != 0\" />\n          <item property=\"Round Robin\"            value=\"Disabled\"                    cond=\"(os_Config.robin_timeout == 0) &amp;&amp; (RTX_En != 0)\" />\n          <item property=\"Round Robin Tick Count\" value=\"%d[os_Info.robin_tick]\"      cond=\"(os_Config.robin_timeout > 0)  &amp;&amp; (RTX_En != 0)\" />\n          <item property=\"Round Robin Timeout\"    value=\"%d[os_Config.robin_timeout]\" cond=\"(os_Config.robin_timeout > 0)  &amp;&amp; (RTX_En != 0)\" />\n          <item property=\"Global Dynamic Memory\" value=\"Not used\"                                                                                                                    cond=\"(os_Config.mem_common_size == 0) &amp;&amp; (RTX_En != 0)\"/>\n          <item property=\"Global Dynamic Memory\" value=\"Base: %x[mem_head_com._addr], Size: %d[mem_head_com.size], Used: %d[mem_head_com.used], Max used: %d[mem_head_com.max_used]\" cond=\"(os_Config.mem_common_size != 0) &amp;&amp; (RTX_En != 0)\"/>\n          <item property=\"Stack Overrun Check\"   value=\"%t[os_Config.stack_check ? &quot;Enabled&quot; : &quot;Disabled&quot;]\" cond=\"RTX_En != 0\"/>\n          <item property=\"Stack Usage Watermark\" value=\"%t[os_Config.stack_wmark ? &quot;Enabled&quot; : &quot;Disabled&quot;]\" cond=\"RTX_En != 0\"/>\n          <item property=\"Default Thread Stack Size\" value=\"%d[os_Config.thread_stack_size]\" cond=\"RTX_En != 0\"/>\n\n          <item property=\"ISR FIFO Queue\" value=\"Size: %d[os_Info.isr_queue_max], Used: %d[os_Info.isr_queue_cnt]\" cond=\"RTX_En\">\n            <list name=\"i\" start=\"0\" limit=\"os_Info.isr_queue_cnt\">\n              <item property=\"data[%d[i]]\"    value=\"%x[ISR_FIFO[i]]\" />\n            </list>\n          </item>\n\n          <item property=\"Object specific Memory allocation\" value=\"\" cond=\"StaticMp_En\">\n              <item property=\"Thread objects\" value=\"Used: %d[cfg_mp_thread.used_blocks], Max: %d[cfg_mp_thread.max_blocks]\" cond=\"os_Config.mpi_thread\">\n                <item property=\"Control blocks\" value=\"Base: %x[cfg_mp_thread.block_base], Size: %d[cfg_mp_thread.block_lim - cfg_mp_thread.block_base], Used: %d[cfg_mp_thread.used_blocks * cfg_mp_thread.block_size]\"/>\n                <item property=\"Default stack\"  value=\"Base: %x[cfg_mp_stack.block_base], Size: %d[cfg_mp_stack.block_lim - cfg_mp_stack.block_base], Used: %d[cfg_mp_stack.used_blocks * cfg_mp_stack.block_size]\" cond=\"os_Config.mpi_stack\"/>\n                <item property=\"User stack\"     value=\"Base: %x[mem_head_stack._addr], Size: %d[mem_head_stack.size], Used: %d[mem_head_stack.used], Max used: %d[mem_head_stack.max_used]\" cond=\"os_Config.mem_stack_size\"/>\n              </item>\n              <item property=\"Timer objects\" value=\"Used: %d[cfg_mp_timer.used_blocks], Max: %d[cfg_mp_timer.max_blocks]\" cond=\"os_Config.mpi_timer\">\n                <item property=\"Control blocks\" value=\"Base: %x[cfg_mp_timer.block_base], Size: %d[cfg_mp_timer.block_lim - cfg_mp_timer.block_base], Used: %d[cfg_mp_timer.used_blocks * cfg_mp_timer.block_size]\"/>\n              </item>\n              <item property=\"Event Flags objects\" value=\"Used: %d[cfg_mp_events.used_blocks], Max: %d[cfg_mp_events.max_blocks]\" cond=\"os_Config.mpi_event_flags\">\n                <item property=\"Control blocks\" value=\"Base: %x[cfg_mp_events.block_base], Size: %d[cfg_mp_events.block_lim - cfg_mp_events.block_base], Used: %d[cfg_mp_events.used_blocks * cfg_mp_events.block_size]\"/>\n              </item>\n              <item property=\"Mutex objects\" value=\"Used: %d[cfg_mp_mutex.used_blocks], Max: %d[cfg_mp_mutex.max_blocks]\" cond=\"os_Config.mpi_mutex\">\n                <item property=\"Control blocks\" value=\"Base: %x[cfg_mp_mutex.block_base], Size: %d[cfg_mp_mutex.block_lim - cfg_mp_mutex.block_base], Used: %d[cfg_mp_mutex.used_blocks * cfg_mp_mutex.block_size]\"/>\n              </item>\n              <item property=\"Semaphore objects\" value=\"Used: %d[cfg_mp_semaphore.used_blocks], Max: %d[cfg_mp_semaphore.max_blocks]\" cond=\"os_Config.mpi_semaphore\">\n                <item property=\"Control blocks\" value=\"Base: %x[cfg_mp_semaphore.block_base], Size: %d[cfg_mp_semaphore.block_lim - cfg_mp_semaphore.block_base], Used: %d[cfg_mp_semaphore.used_blocks * cfg_mp_semaphore.block_size]\"/>\n              </item>\n              <item property=\"Memory Pool objects\" value=\"Used: %d[cfg_mp_mpool.used_blocks], Max: %d[cfg_mp_mpool.max_blocks]\" cond=\"os_Config.mpi_memory_pool\">\n                <item property=\"Control blocks\" value=\"Base: %x[cfg_mp_mpool.block_base], Size: %d[cfg_mp_mpool.block_lim - cfg_mp_mpool.block_base], Used: %d[cfg_mp_mpool.used_blocks * cfg_mp_mpool.block_size]\"/>\n                <item property=\"Data storage\" value=\"Base: %x[mem_head_mp_data._addr], Size: %d[mem_head_mp_data.size], Used: %d[mem_head_mp_data.used], Max used: %d[mem_head_mp_data.max_used]\" cond=\"os_Config.mem_mp_data_size\"/>\n              </item>\n              <item property=\"Message Queue objects\" value=\"Used: %d[cfg_mp_mqueue.used_blocks], Max: %d[cfg_mp_mqueue.max_blocks]\" cond=\"os_Config.mpi_message_queue\">\n                <item property=\"Control blocks\" value=\"Base: %x[cfg_mp_mqueue.block_base], Size: %d[cfg_mp_mqueue.block_lim - cfg_mp_mqueue.block_base], Used: %d[cfg_mp_mqueue.used_blocks * cfg_mp_mqueue.block_size]\"/>\n                <item property=\"Data storage\" value=\"Base: %x[mem_head_mq_data._addr], Size: %d[mem_head_mq_data.size], Used: %d[mem_head_mq_data.used], Max used: %d[mem_head_mq_data.max_used]\" cond=\"os_Config.mem_mq_data_size\"/>\n              </item>\n          </item>\n\n          <item property=\"Object Memory usage counters\" value=\"\" cond=\"(MUC_En != 0) &amp;&amp; (RTX_En != 0)\">\n            <item property=\"Thread objects\"        value=\"Alloc: %d[MUC_Thread.cnt_alloc], Free: %d[MUC_Thread.cnt_free], Max used: %d[MUC_Thread.max_used]\"             cond=\"MUC_Thread_En\"/>\n            <item property=\"Timer objects\"         value=\"Alloc: %d[MUC_Timer.cnt_alloc], Free: %d[MUC_Timer.cnt_free], Max used: %d[MUC_Timer.max_used]\"                cond=\"MUC_Timer_En\"/>\n            <item property=\"Event Flags objects\"   value=\"Alloc: %d[MUC_EventFlags.cnt_alloc], Free: %d[MUC_EventFlags.cnt_free], Max used: %d[MUC_EventFlags.max_used]\" cond=\"MUC_EventFlags_En\"/>\n            <item property=\"Mutex objects\"         value=\"Alloc: %d[MUC_Mutex.cnt_alloc], Free: %d[MUC_Mutex.cnt_free], Max used: %d[MUC_Mutex.max_used]\"                cond=\"MUC_Mutex_En\"/>\n            <item property=\"Semaphore objects\"     value=\"Alloc: %d[MUC_Semaphore.cnt_alloc], Free: %d[MUC_Semaphore.cnt_free], Max used: %d[MUC_Semaphore.max_used]\"    cond=\"MUC_Semaphore_En\"/>\n            <item property=\"Memory Pool objects\"   value=\"Alloc: %d[MUC_MemPool.cnt_alloc], Free: %d[MUC_MemPool.cnt_free], Max used: %d[MUC_MemPool.max_used]\"          cond=\"MUC_MemPool_En\"/>\n            <item property=\"Message Queue objects\" value=\"Alloc: %d[MUC_MsgQueue.cnt_alloc], Free: %d[MUC_MsgQueue.cnt_free], Max used: %d[MUC_MsgQueue.max_used]\"       cond=\"MUC_MsgQueue_En\"/>\n          </item>\n        </item>\n\n        <!-- Threads -->\n        <item cond=\"TCB_En\" property=\"Threads\" value=\"\">\n          <list name=\"i\" start=\"0\" limit=\"TCB._count\">\n            <item>\n              <print cond=\"TCB[i].out_type == 1\" property=\"id: %x[TCB[i]._addr] &quot;%S[TCB[i].thread_addr]&quot;\" value=\"%E[TCB[i].state &amp; 0x07], %E[TCB[i].priority], Stack Used: %d[TCB[i].stack_curp]%%\"                               alert=\"TCB[i].stack_over != 0\"/>\n              <print cond=\"TCB[i].out_type == 2\" property=\"id: %x[TCB[i]._addr] &quot;%S[TCB[i].thread_addr]&quot;\" value=\"%E[TCB[i].state &amp; 0x07], %E[TCB[i].priority], Stack Used: %d[TCB[i].stack_curp]%%, Max: %d[TCB[i].stack_maxp]%%\" alert=\"TCB[i].stack_over != 0\"/>\n              <print cond=\"TCB[i].out_type == 3\" property=\"id: %x[TCB[i]._addr] %N[TCB[i].name]\"                    value=\"%E[TCB[i].state &amp; 0x07], %E[TCB[i].priority], Stack Used: %d[TCB[i].stack_curp]%%\"                               alert=\"TCB[i].stack_over != 0\"/>\n              <print cond=\"TCB[i].out_type == 4\" property=\"id: %x[TCB[i]._addr] %N[TCB[i].name]\"                    value=\"%E[TCB[i].state &amp; 0x07], %E[TCB[i].priority], Stack Used: %d[TCB[i].stack_curp]%%, Max: %d[TCB[i].stack_maxp]%%\" alert=\"TCB[i].stack_over != 0\"/>\n\n              <print cond=\"TCB[i].out_type == 5\" property=\"id: %x[TCB[i]._addr] &quot;%S[TCB[i].thread_addr]&quot;\" value=\"%E[TCB[i].state &amp; 0x07], %E[TCB[i].priority], Stack Used: unknown\"                               alert=\"TCB[i].stack_over != 0\"/>\n              <print cond=\"TCB[i].out_type == 6\" property=\"id: %x[TCB[i]._addr] &quot;%S[TCB[i].thread_addr]&quot;\" value=\"%E[TCB[i].state &amp; 0x07], %E[TCB[i].priority], Stack Used: unknown, Max: %d[TCB[i].stack_maxp]%%\" alert=\"TCB[i].stack_over != 0\"/>\n              <print cond=\"TCB[i].out_type == 7\" property=\"id: %x[TCB[i]._addr] %N[TCB[i].name]\"                    value=\"%E[TCB[i].state &amp; 0x07], %E[TCB[i].priority], Stack Used: unknown\"                               alert=\"TCB[i].stack_over != 0\"/>\n              <print cond=\"TCB[i].out_type == 8\" property=\"id: %x[TCB[i]._addr] %N[TCB[i].name]\"                    value=\"%E[TCB[i].state &amp; 0x07], %E[TCB[i].priority], Stack Used: unknown, Max: %d[TCB[i].stack_maxp]%%\" alert=\"TCB[i].stack_over != 0\"/>\n\n              <item property=\"State\"        value=\"%E[TCB[i].state &amp; 0x07]\"/>\n              <item property=\"Priority\"     value=\"%E[TCB[i].priority]\"/>\n              <item>\n                <print cond=\"(os_Config.exec_zone == 0) &amp;&amp; (os_Config.safety_class == 0)\" property=\"Attributes\" value=\"%E[TCB[i].attr &amp; 0x01], %E[TCB[i].attr &amp; 0x06]\"/>\n                <print cond=\"(os_Config.exec_zone == 0) &amp;&amp; (os_Config.safety_class == 1)\" property=\"Attributes\" value=\"%E[TCB[i].attr &amp; 0x01], %E[TCB[i].attr &amp; 0x06], osSafetyClass(%d[TCB[i].attr/16])\"/>\n                <print cond=\"(os_Config.exec_zone == 1) &amp;&amp; (os_Config.safety_class == 0)\" property=\"Attributes\" value=\"%E[TCB[i].attr &amp; 0x01], %E[TCB[i].attr &amp; 0x06], osThreadZone(%d[TCB[i].zone])\"/>\n                <print cond=\"(os_Config.exec_zone == 1) &amp;&amp; (os_Config.safety_class == 1)\" property=\"Attributes\" value=\"%E[TCB[i].attr &amp; 0x01], %E[TCB[i].attr &amp; 0x06], osSafetyClass(%d[TCB[i].attr/16]), osThreadZone(%d[TCB[i].zone])\"/>\n              </item>\n\n              <item>\n                <print property=\"Waiting\" value=\"%E[TCB[i].state], Timeout: %d[TCB[i].ex_delay]\" cond=\"((TCB[i].state &amp; 0x07) == 3) &amp;&amp; (TCB[i].ex_delay != -1)\"/>\n                <print property=\"Waiting\" value=\"%E[TCB[i].state], Timeout: osWaitForever\"       cond=\"((TCB[i].state &amp; 0x07) == 3) &amp;&amp; (TCB[i].ex_delay == -1)\"/>\n                <!-- Wait Join -->\n                <item cond=\"TCB[i].state == 0x23\" property=\"id: %x[TCB[i].thread_join]\" value=\"\"/>\n\n                <!-- Wait Thread Flags -->\n                <item cond=\"TCB[i].state == 0x33\" property=\"id: %x[TCB[i].thread_prev]\" value=\"\"/>\n\n                <list cond=\"TCB[i].state == 0x43\" name=\"n\" start=\"0\" limit=\"ECB._count\">\n                  <!-- Wait Event Flags -->\n                  <item cond=\"TCB[i].thread_prev == ECB[n]._addr\" property=\"id: %x[ECB[n]._addr] %N[ECB[n].name]\" value=\"\"/>\n                </list>\n\n                <list cond=\"TCB[i].state == 0x53\" name=\"n\" start=\"0\" limit=\"MCB._count\">\n                  <!-- Wait Mutex -->\n                  <item cond=\"TCB[i].thread_prev == MCB[n]._addr\" property=\"id: %x[MCB[n]._addr] %N[MCB[n].name]\" value=\"\"/>\n                </list>\n\n                <list cond=\"TCB[i].state == 0x63\" name=\"n\" start=\"0\" limit=\"SCB._count\">\n                  <!-- Wait Semaphore -->\n                  <item cond=\"TCB[i].thread_prev == SCB[n]._addr\" property=\"id: %x[SCB[n]._addr] %N[SCB[n].name]\" value=\"\"/>\n                </list>\n\n                <list cond=\"TCB[i].state == 0x73\" name=\"n\" start=\"0\" limit=\"PCB._count\">\n                  <!-- Wait Memory Pool -->\n                  <item cond=\"TCB[i].thread_prev == PCB[n]._addr\" property=\"id: %x[PCB[n]._addr] %N[PCB[n].name]\" value=\"\"/>\n                </list>\n\n                <list cond=\"(TCB[i].state == 0x83) || (TCB[i].state == 0x84)\" name=\"n\" start=\"0\" limit=\"QCB._count\">\n                  <!-- Wait Message Queue -->\n                  <item cond=\"TCB[i].thread_prev == QCB[n]._addr\" property=\"id: %x[QCB[n]._addr] %N[QCB[n].name]\" value=\"\"/>\n                </list>\n              </item>\n\n              <item>\n                <print cond=\"(TCB[i].sp_valid == 0) &amp;&amp; (os_Config.stack_wmark == 0)\" property=\"Stack\" value=\"Used: unknown\"/>\n                <print cond=\"(TCB[i].sp_valid == 0) &amp;&amp; (os_Config.stack_wmark != 0)\" property=\"Stack\" value=\"Used: unknown, Max: %d[TCB[i].stack_maxp]%% [%d[TCB[i].stack_maxb]]\"/>\n                <print cond=\"(TCB[i].sp_valid == 1) &amp;&amp; (os_Config.stack_wmark == 0)\" property=\"Stack\" value=\"Used: %d[TCB[i].stack_curp]%% [%d[TCB[i].stack_curb]]\"/>\n                <print cond=\"(TCB[i].sp_valid == 1) &amp;&amp; (os_Config.stack_wmark != 0)\" property=\"Stack\" value=\"Used: %d[TCB[i].stack_curp]%% [%d[TCB[i].stack_curb]], Max: %d[TCB[i].stack_maxp]%% [%d[TCB[i].stack_maxb]]\"/>\n\n                <item>\n                  <print cond=\"TCB[i].sp_valid == 0\" property=\"Used\" value=\"unknown\"/>\n                  <print cond=\"TCB[i].sp_valid == 1\" property=\"Used\" value=\"%d[TCB[i].stack_curb]\"/>\n                </item>\n                <item property=\"Max\"   value=\"%d[TCB[i].stack_maxb]\" cond=\"os_Config.stack_wmark != 0\"/>\n                <item property=\"Top\"   value=\"%x[TCB[i].stack_mem + TCB[i].stack_size]\"/>\n                <item>\n                  <print cond=\"TCB[i].sp_valid == 0\" property=\"Current\" value=\"unknown\"/>\n                  <print cond=\"TCB[i].sp_valid == 1\" property=\"Current\" value=\"%x[TCB[i].stack_cur]\"/>\n                </item>\n                <item property=\"Limit\" value=\"%x[TCB[i].stack_mem]\"/>\n                <item property=\"Size\"  value=\"%d[TCB[i].stack_size]\"/>\n              </item>\n\n              <item property=\"Stack Overrun\" value=\"Overrun detected\" cond=\"TCB[i].stack_over != 0\"/>\n              <item property=\"Flags\" value=\"%x[TCB[i].thread_flags]\"/>\n              <item>\n                <print cond=\"(os_Config.watchdog != 0) &amp;&amp; (TCB[i].wd_state == 0)\" property=\"Watchdog\" value=\"Inactive\"/>\n                <print cond=\"(os_Config.watchdog != 0) &amp;&amp; (TCB[i].wd_state == 1)\" property=\"Watchdog\" value=\"Running, Timeout: %d[TCB[i].wd_tick]\"/>\n              </item>\n              <item property=\"Wait Flags\" value=\"%x[TCB[i].wait_flags], %E[TCB[i].flags_options &amp; 1]\"                 cond=\"(TCB[i].wait_flags != 0) &amp;&amp; ((TCB[i].flags_options &amp; 2) == 0)\"/>\n              <item property=\"Wait Flags\" value=\"%x[TCB[i].wait_flags], %E[TCB[i].flags_options &amp; 1], osFlagsNoClear\" cond=\"(TCB[i].wait_flags != 0) &amp;&amp; ((TCB[i].flags_options &amp; 2) != 0)\"/>\n              <item property=\"TrustZone ID\" value=\"%d[TCB[i].tz_memory]\" cond=\"TCB[i].tz_memory\"/>\n            </item>\n          </list>\n        </item>\n\n        <!-- Timers -->\n        <item cond=\"CCB_En\" property=\"Timers\" value=\"\">\n          <list name=\"i\" start=\"0\" limit=\"CCB._count\">\n            <item cond=\"CCB[i].cb_valid\" property=\"id: %x[CCB[i]._addr] %N[CCB[i].name]\" value=\"%E[CCB[i].state], Tick: %d[CCB[i].ex_tick]\">\n              <item property=\"State\"      value=\"%E[CCB[i].state]\" />\n              <item property=\"Type\"       value=\"%E[CCB[i].attr &amp; 0x01]\" />\n              <item property=\"Attributes\" value=\"osSafetyClass(%d[CCB[i].attr/16])\" cond=\"os_Config.safety_class == 1\"/>\n              <item property=\"Tick\"       value=\"%d[CCB[i].ex_tick]\" />\n              <item property=\"Load\"       value=\"%d[CCB[i].load]\" />\n              <item property=\"Callback\"   value=\"Func: %S[CCB[i].finfo_fp], Arg: %x[CCB[i].finfo_arg]\" />\n            </item>\n          </list>\n        </item>\n\n        <!-- Semaphores -->\n        <item cond=\"SCB_En\" property=\"Semaphores\" value=\"\">\n          <list name=\"i\" start=\"0\" limit=\"SCB._count\">\n            <item cond=\"SCB[i].cb_valid\" property=\"id: %x[SCB[i]._addr] %N[SCB[i].name]\" value=\"Tokens: %d[SCB[i].tokens], Max: %d[SCB[i].max_tokens]\">\n            <item property=\"Attributes\" value=\"osSafetyClass(%d[SCB[i].attr/16])\" cond=\"os_Config.safety_class == 1\"/>\n            <item property=\"Tokens\"     value=\"%d[SCB[i].tokens]\" />\n            <item property=\"Max Tokens\" value=\"%d[SCB[i].max_tokens]\" />\n\n              <!-- Waiting thread list -->\n              <item cond=\"SCB[i].wl_cnt\" property=\"Threads waiting (%d[SCB[i].wl_cnt])\" value=\"\">\n\n                <list name=\"j\" start=\"SCB[i].wl_idx\" limit=\"SCB[i].wl_idx + SCB[i].wl_cnt\">\n                  <list name=\"k\" start=\"0\" limit=\"TCB._count\">\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: %d[TCB[k].ex_delay]\" cond=\"(SWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay != -1)\"/>\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: osWaitForever\"       cond=\"(SWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay == -1)\"/>\n                  </list>\n                </list>\n\n              </item>\n            </item>\n          </list>\n        </item>\n\n        <!-- Mutexes -->\n        <item cond=\"MCB_En\" property=\"Mutexes\" value=\"\">\n          <list name=\"i\" start=\"0\" limit=\"MCB._count\">\n            <item cond=\"MCB[i].cb_valid\" property=\"id: %x[MCB[i]._addr] %N[MCB[i].name]\" value=\"Lock counter: %d[MCB[i].lock]\">\n              <item property=\"Lock counter\" value=\"%x[MCB[i].lock]\"/>\n              <item property=\"Attributes\" value=\"osSafetyClass(%d[MCB[i].attr/16])\" cond=\"os_Config.safety_class == 1\">\n                <item property=\"osMutexRecursive\"   value=\"%t[(MCB[i].attr &amp; 0x01) ?  &quot;True&quot; : &quot;False&quot;]\" />\n                <item property=\"osMutexPrioInherit\" value=\"%t[(MCB[i].attr &amp; 0x02) ?  &quot;True&quot; : &quot;False&quot;]\" />\n                <item property=\"osMutexRobust\"      value=\"%t[(MCB[i].attr &amp; 0x08) ?  &quot;True&quot; : &quot;False&quot;]\" />\n              </item>\n\n              <list cond=\"MCB[i].lock\" name=\"n\" start=\"0\" limit=\"TCB._count\">\n                <item cond=\"MCB[i].owner_thread == TCB[n]._addr\" property=\"Owner thread\" value=\"id: %x[TCB[n]._addr] %N[TCB[n].name]\"/>\n              </list>\n\n              <!-- Waiting thread list -->\n              <item cond=\"MCB[i].wl_cnt\" property=\"Threads waiting (%d[MCB[i].wl_cnt])\" value=\"\">\n\n                <list name=\"j\" start=\"MCB[i].wl_idx\" limit=\"MCB[i].wl_idx + MCB[i].wl_cnt\">\n                  <list name=\"k\" start=\"0\" limit=\"TCB._count\">\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: %d[TCB[k].ex_delay]\" cond=\"(MWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay != -1)\"/>\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: osWaitForever\"       cond=\"(MWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay == -1)\"/>\n                  </list>\n                </list>\n\n              </item>\n            </item>\n          </list>\n        </item>\n\n        <!-- Event Flags -->\n        <item cond=\"ECB_En\" property=\"Event Flags\" value=\"\">\n          <list name=\"i\" start=\"0\" limit=\"ECB._count\">\n            <item cond=\"ECB[i].cb_valid\" property=\"id: %x[ECB[i]._addr] %N[ECB[i].name]\" value=\"Flags: %x[ECB[i].event_flags]\">\n              <item property=\"Attributes\" value=\"osSafetyClass(%d[ECB[i].attr/16])\" cond=\"os_Config.safety_class == 1\"/>\n\n              <!-- Waiting thread list -->\n              <item cond=\"ECB[i].wl_cnt\" property=\"Threads waiting (%d[ECB[i].wl_cnt])\" value=\"\">\n\n                <list name=\"j\" start=\"ECB[i].wl_idx\" limit=\"ECB[i].wl_idx + ECB[i].wl_cnt\">\n                  <list name=\"k\" start=\"0\" limit=\"TCB._count\">\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: %d[TCB[k].ex_delay]\" cond=\"(EWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay != -1)\"/>\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: osWaitForever\"       cond=\"(EWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay == -1)\"/>\n                  </list>\n                </list>\n\n              </item>\n            </item>\n          </list>\n        </item>\n\n        <!-- Memory Pool -->\n        <item cond=\"PCB_En\" property=\"Memory Pools\" value=\"\">\n          <list name=\"i\" start=\"0\" limit=\"PCB._count\">\n            <item cond=\"PCB[i].cb_valid\" property=\"id: %x[PCB[i]._addr] %N[PCB[i].name]\" value=\"Used: %d[PCB[i].used_blocks], Max: %d[PCB[i].max_blocks]\">\n\n              <item property=\"Attributes\"  value=\"osSafetyClass(%d[PCB[i].attr/16])\" cond=\"os_Config.safety_class == 1\"/>\n              <item property=\"Used blocks\" value=\"%d[PCB[i].used_blocks]\"/>\n              <item property=\"Max blocks\"  value=\"%d[PCB[i].max_blocks]\"/>\n              <item property=\"Block size\"  value=\"%d[PCB[i].block_size]\"/>\n              <item property=\"Memory base\" value=\"%x[PCB[i].block_base]\"/>\n              <item property=\"Memory size\" value=\"%d[PCB[i].block_lim - PCB[i].block_base]\"/>\n\n              <!-- Waiting thread list -->\n              <item cond=\"PCB[i].wl_cnt\" property=\"Threads waiting (%d[PCB[i].wl_cnt])\" value=\"\">\n\n                <list name=\"j\" start=\"PCB[i].wl_idx\" limit=\"PCB[i].wl_idx + PCB[i].wl_cnt\">\n                  <list name=\"k\" start=\"0\" limit=\"TCB._count\">\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: %d[TCB[k].ex_delay]\" cond=\"(PWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay != -1)\"/>\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: osWaitForever\"       cond=\"(PWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay == -1)\"/>\n                  </list>\n                </list>\n\n              </item>\n            </item>\n          </list>\n        </item>\n\n        <!-- Message Queue -->\n        <item cond=\"QCB_En\" property=\"Message Queues\" value=\"\">\n          <list name=\"i\" start=\"0\" limit=\"QCB._count\">\n            <item cond=\"QCB[i].cb_valid\" property=\"id: %x[QCB[i]._addr] %N[QCB[i].name]\" value=\"Messages: %d[QCB[i].msg_count], Max: %d[QCB[i].max_blocks]\">\n\n              <item property=\"Attributes\"   value=\"osSafetyClass(%d[QCB[i].attr/16])\" cond=\"os_Config.safety_class == 1\"/>\n              <item property=\"Messages\"     value=\"%d[QCB[i].ml_cnt]\"/>\n              <item property=\"Max Messages\" value=\"%d[QCB[i].max_blocks]\"/>\n              <item property=\"Message size\" value=\"%d[QCB[i].msg_size]\"/>\n\n              <!-- Waiting thread list -->\n              <item cond=\"QCB[i].wl_cnt\" property=\"Threads waiting (%d[QCB[i].wl_cnt])\" value=\"\">\n\n                <list name=\"j\" start=\"QCB[i].wl_idx\" limit=\"QCB[i].wl_idx + QCB[i].wl_cnt\">\n                  <list name=\"k\" start=\"0\" limit=\"TCB._count\">\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: %d[TCB[k].ex_delay]\" cond=\"(QWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay != -1)\"/>\n                    <item property=\"id: %x[TCB[k]._addr] %N[TCB[k].name]\" value=\"Timeout: osWaitForever\"       cond=\"(QWL[j].stack_mem == TCB[k].stack_mem) &amp;&amp; (TCB[k].ex_delay == -1)\"/>\n                  </list>\n                </list>\n\n              </item>\n\n              <!-- Queued messages list-->\n              <item cond=\"QCB[i].ml_cnt\" property=\"Queue (%d[QCB[i].ml_cnt])\" value=\"\">\n\n                <list name=\"j\" start=\"0\" limit=\"QCB[i].ml_cnt\">\n                  <item property=\"Queue[%d[j]]\" value=\"Address: %x[QML[j + QCB[i].ml_idx].addr], Priority: %d[QML[j + QCB[i].ml_idx].priority]\" />\n                </list>\n\n              </item>\n\n            </item>\n          </list>\n        </item>\n\n      </out>\n    </object>\n  </objects>\n\n  <events>\n\n    <group name=\"RTX5 RTOS\">\n      <component name=\"Memory Events\"       brief=\"RTX Memory\"    no=\"0xF0\" prefix=\"EvrRtx\" info=\"RTX5 RTOS Memory Management Events\" />\n      <component name=\"Kernel Events\"       brief=\"RTX Kernel\"    no=\"0xF1\" prefix=\"EvrRtx\" info=\"RTX5 RTOS Kernel Events\" />\n      <component name=\"Thread Events\"       brief=\"RTX Thread\"    no=\"0xF2\" prefix=\"EvrRtx\" info=\"RTX5 RTOS Thread Events\" >\n        <state name=\"Inactive\"    plot=\"off\"                               />\n        <state name=\"Ready\"       plot=\"box\"                               />\n        <state name=\"Running\"     plot=\"box\"  bold=\"1\" unique=\"1\" ssel=\"1\" />\n        <state name=\"Blocked\"     plot=\"line\"                              />\n        <state name=\"Not-running\" plot=\"line\" bold=\"1\" dormant=\"1\"         />\n      </component>\n      <component name=\"Generic Wait Events\" brief=\"RTX Wait\"      no=\"0xF3\" prefix=\"EvrRtx\" info=\"RTX5 RTOS Generic Wait Events\" />\n      <component name=\"ThreadFlags Events\"  brief=\"RTX ThFlags\"   no=\"0xF4\" prefix=\"EvrRtx\" info=\"RTX5 RTOS ThreadFlags Events\" />\n      <component name=\"EventFlags Events\"   brief=\"RTX EvFlags\"   no=\"0xF5\" prefix=\"EvrRtx\" info=\"RTX5 RTOS EventFlags Events\" />\n      <component name=\"Timer Events\"        brief=\"RTX Timer\"     no=\"0xF6\" prefix=\"EvrRtx\" info=\"RTX5 RTOS Timer Events\" />\n      <component name=\"Mutex Events\"        brief=\"RTX Mutex\"     no=\"0xF7\" prefix=\"EvrRtx\" info=\"RTX5 RTOS Mutex Events\" >\n        <state name=\"Free\"   plot=\"line\" color=\"blue\" bold=\"1\" />\n        <state name=\"Used\"   plot=\"box\"  color=\"blue\"          />\n        <state name=\"Error\"  plot=\"box\"  color=\"red\"           />\n      </component>\n      <component name=\"Semaphore Events\"    brief=\"RTX Semaphore\" no=\"0xF8\" prefix=\"EvrRtx\" info=\"RTX5 RTOS Semaphore Events\" />\n      <component name=\"MemoryPool Events\"   brief=\"RTX MemPool\"   no=\"0xF9\" prefix=\"EvrRtx\" info=\"RTX5 RTOS MemoryPool Events\" />\n      <component name=\"MessageQueue Events\" brief=\"RTX MsgQueue\"  no=\"0xFA\" prefix=\"EvrRtx\" info=\"RTX5 RTOS MessageQueue Events\" />\n    </group>\n\n    <event id=\"0xF000 + 0x00\" level=\"Op\" property=\"MemoryInit\"       value=\"mem=%x[val1], size=%d[val2], result=%d[val3]\" info=\"\"/>\n    <event id=\"0xF000 + 0x01\" level=\"Op\" property=\"MemoryAlloc\"      value=\"mem=%x[val1], size=%d[val2], type=%d[val3], block=%x[val4]\" info=\"\"/>\n    <event id=\"0xF000 + 0x02\" level=\"Op\" property=\"MemoryFree\"       value=\"mem=%x[val1], block=%x[val2], result=%d[val3]\" info=\"\"/>\n    <event id=\"0xF000 + 0x03\" level=\"Op\" property=\"MemoryBlockInit\"  value=\"mp_info=%x[val1], block_count=%d[val2], block_size=%d[val3], block_mem=%x[val4]\" info=\"\"/>\n    <event id=\"0xF000 + 0x04\" level=\"Op\" property=\"MemoryBlockAlloc\" value=\"mp_info=%x[val1], block=%x[val2]\" info=\"\"/>\n    <event id=\"0xF000 + 0x05\" level=\"Op\" property=\"MemoryBlockFree\"  value=\"mp_info=%x[val1], block=%x[val2], status=%E[val3, rtx_t:status]\" info=\"\"/>\n\n    <event id=\"0xF100 + 0x00\" level=\"Error\"  property=\"KernelError\"                         value=\"status=%E[val1, rtx_t:status]\" info=\"Kernel error occurred.\"/>\n    <event id=\"0xF100 + 0x01\" level=\"API\"    property=\"KernelInitialize\"                    value=\"\" info=\"osKernelInitialize function was called.\"/>\n    <event id=\"0xF100 + 0x02\" level=\"Op\"     property=\"KernelInitialized\"  tracking=\"Reset\" value=\"\" info=\"Kernel was initialized.\"/>\n    <event id=\"0xF100 + 0x03\" level=\"API\"    property=\"KernelGetInfo\"                       value=\"version=%x[val1], id_buf=%x[val2], id_size=%d[val3]\" info=\"osKernelGetInfo function was called.\"/>\n    <event id=\"0xF100 + 0x04\" level=\"Op\"     property=\"KernelInfoRetrieved\"                 value=\"version_api=%d[val1/10000000].%d[(val1/10000)%1000].%d[val1%10000], version_kernel=%d[val2/10000000].%d[(val2/10000)%1000].%d[val2%10000]\" info=\"Kernel information was retrieved.\"/>\n    <event id=\"0xF100 + 0x05\" level=\"Detail\" property=\"KernelInfoRetrieved\"                 value=\"id=%t[val1]\" info=\"Kernel ID as ASCII string.\"/>\n    <event id=\"0xF100 + 0x06\" level=\"API\"    property=\"KernelGetState\"                      value=\"state=%E[val1, rtx_kernel_state:id]\" info=\"osKernelGetState function was called and state was retrieved.\"/>\n    <event id=\"0xF100 + 0x07\" level=\"API\"    property=\"KernelStart\"                         value=\"\" info=\"osKernelStart function was called.\"/>\n    <event id=\"0xF100 + 0x08\" level=\"Op\"     property=\"KernelStarted\"                       value=\"\" info=\"Kernel execution was started.\"/>\n    <event id=\"0xF100 + 0x09\" level=\"API\"    property=\"KernelLock\"                          value=\"\" info=\"osKernelLock function was called.\"/>\n    <event id=\"0xF100 + 0x0A\" level=\"Op\"     property=\"KernelLocked\"                        value=\"lock=%d[val1]\" info=\"Kernel was locked.\"/>\n    <event id=\"0xF100 + 0x0B\" level=\"API\"    property=\"KernelUnlock\"                        value=\"\" info=\"osKernelUnlock function was called.\"/>\n    <event id=\"0xF100 + 0x0C\" level=\"Op\"     property=\"KernelUnlocked\"                      value=\"lock=%d[val1]\" info=\"Kernel was unlocked.\"/>\n    <event id=\"0xF100 + 0x0D\" level=\"API\"    property=\"KernelRestoreLock\"                   value=\"lock=%d[val1]\" info=\"osKernelRestoreLock function was called.\"/>\n    <event id=\"0xF100 + 0x0E\" level=\"Op\"     property=\"KernelLockRestored\"                  value=\"lock=%d[val1]\" info=\"Kernel lock was restored.\"/>\n    <event id=\"0xF100 + 0x0F\" level=\"API\"    property=\"KernelSuspend\"                       value=\"\" info=\"osKernelSuspend function was called.\"/>\n    <event id=\"0xF100 + 0x10\" level=\"Op\"     property=\"KernelSuspended\"                     value=\"sleep_ticks=%d[val1]\" info=\"Kernel execution was suspended.\"/>\n    <event id=\"0xF100 + 0x11\" level=\"API\"    property=\"KernelResume\"                        value=\"sleep_ticks=%d[val1]\" info=\"osKernelResume function was called.\"/>\n    <event id=\"0xF100 + 0x12\" level=\"Op\"     property=\"KernelResumed\"                       value=\"\" info=\"Kernel execution was resumed.\"/>\n    <event id=\"0xF100 + 0x17\" level=\"API\"    property=\"KernelProtect\"                       value=\"safety_class=%d[val1]\" info=\"osKernelProtect function was called.\"/>\n    <event id=\"0xF100 + 0x18\" level=\"Op\"     property=\"KernelProtected\"                     value=\"\" info=\"Kernel safety class protection was activated.\"/>\n    <event id=\"0xF100 + 0x13\" level=\"API\"    property=\"KernelGetTickCount\"                  value=\"count=%d[val1]\" info=\"osKernelGetTickCount function was called.\"/>\n    <event id=\"0xF100 + 0x14\" level=\"API\"    property=\"KernelGetTickFreq\"                   value=\"freq=%d[val1]\" info=\"osKernelGetTickFreq function was called.\"/>\n    <event id=\"0xF100 + 0x15\" level=\"API\"    property=\"KernelGetSysTimerCount\"              value=\"count=%d[val1]\" info=\"osKernelGetSysTimerCount function was called.\"/>\n    <event id=\"0xF100 + 0x16\" level=\"API\"    property=\"KernelGetSysTimerFreq\"               value=\"freq=%d[val1]\" info=\"osKernelGetSysTimerFreq function was called.\"/>\n    <event id=\"0xF100 + 0x19\" level=\"Error\"  property=\"KernelErrorNotify\"                   value=\"code=%E[val1, rtx_error:id], object_id=%x[val2]\" info=\"osKernelErrorNotify function was called.\"/>\n    <event id=\"0xF100 + 0x1A\" level=\"API\"    property=\"KernelDestroyClass\"                  value=\"safety_class=%d[val1], mode=%x[val2]\" info=\"osKernelDestroyClass function was called.\"/>\n\n    <event id=\"0xF200 + 0x00\" level=\"Error\"  property=\"ThreadError\"                                                                       value=\"thread_id=%x[val1], status=%E[val2, rtx_t:status]\" info=\"Thread error occurred.\"/>\n    <event id=\"0xF200 + 0x01\" level=\"API\"    property=\"ThreadNew\"                                                                         value=\"func=%S[val1], argument=%x[val2], attr=%x[val3]\" info=\"osThreadNew function was called.\"/>\n    <event id=\"0xF200 + 0x03\" level=\"Op\"     property=\"ThreadCreated\"    tracking=\"Start\" state=\"Ready\"    handle=\"val1\" hname=\"%S[val2]\" value=\"thread_id=%x[val1]\" info=\"Thread object was created.\"/>\n    <event id=\"0xF200 + 0x2C\" level=\"Op\"     property=\"ThreadCreated\"    tracking=\"Start\" state=\"Ready\"    handle=\"val1\" hname=\"%N[val2]\" value=\"thread_id=%x[val1]\" info=\"Thread object was created.\"/>\n    <event id=\"0xF200 + 0x04\" level=\"API\"    property=\"ThreadGetName\"                                                                     value=\"thread_id=%x[val1], name=%N[val2]\" info=\"osThreadGetName function was called and object name was retrieved.\"/>\n    <event id=\"0xF200 + 0x30\" level=\"API\"    property=\"ThreadGetClass\"                                                                    value=\"thread_id=%x[val1], safety_class=%d[val2]\" info=\"osThreadGetClass function was called and thread safety class was retrieved.\"/>\n    <event id=\"0xF200 + 0x31\" level=\"API\"    property=\"ThreadGetZone\"                                                                     value=\"thread_id=%x[val1], zone=%d[val2]\" info=\"osThreadGetZone function was called and thread execution zone was retrieved.\"/>\n    <event id=\"0xF200 + 0x06\" level=\"API\"    property=\"ThreadGetId\"                                                                       value=\"thread_id=%x[val1]\" info=\"osThreadGetId function was called and current running thread id was retrieved.\"/>\n    <event id=\"0xF200 + 0x07\" level=\"API\"    property=\"ThreadGetState\"                                                                    value=\"thread_id=%x[val1], state=%E[val2, rtx_th_state:id]\" info=\"osThreadGetState function was called and thread state was retrieved.\"/>\n    <event id=\"0xF200 + 0x08\" level=\"API\"    property=\"ThreadGetStackSize\"                                                                value=\"thread_id=%x[val1], stack_size=%d[val2]\" info=\"osThreadGetStackSize function was called and thread stack size was retrieved.\"/>\n    <event id=\"0xF200 + 0x09\" level=\"API\"    property=\"ThreadGetStackSpace\"                                                               value=\"thread_id=%x[val1], stack_space=%d[val2]\" info=\"osThreadGetStackSpace function was called and thread stack space was retrieved.\"/>\n    <event id=\"0xF200 + 0x0A\" level=\"API\"    property=\"ThreadSetPriority\"                                                                 value=\"thread_id=%x[val1], priority=%E[val2, rtx_th_priority:id]\" info=\"osThreadSetPriority function was called.\"/>\n    <event id=\"0xF200 + 0x2D\" level=\"Op\"     property=\"ThreadPriorityUpdated\"                                                             value=\"thread_id=%x[val1], priority=%E[val2, rtx_th_priority:id]\" info=\"Thread priority was updated.\"/>\n    <event id=\"0xF200 + 0x0B\" level=\"API\"    property=\"ThreadGetPriority\"                                                                 value=\"thread_id=%x[val1], priority=%E[val2, rtx_th_priority:id]\" info=\"osThreadGetPriority function was called and thread priority was retrieved.\"/>\n    <event id=\"0xF200 + 0x0C\" level=\"API\"    property=\"ThreadYield\"                                                                       value=\"\" info=\"osThreadYield function was called.\"/>\n    <event id=\"0xF200 + 0x0D\" level=\"API\"    property=\"ThreadSuspend\"                                                                     value=\"thread_id=%x[val1]\" info=\"osThreadSuspend function was called.\"/>\n    <event id=\"0xF200 + 0x0E\" level=\"Op\"     property=\"ThreadSuspended\"                   state=\"Blocked\"  handle=\"val1\"                  value=\"thread_id=%x[val1]\" info=\"Thread execution was suspended.\"/>\n    <event id=\"0xF200 + 0x0F\" level=\"API\"    property=\"ThreadResume\"                                                                      value=\"thread_id=%x[val1]\" info=\"osThreadResume function was called.\"/>\n    <event id=\"0xF200 + 0x10\" level=\"Op\"     property=\"ThreadResumed\"                     state=\"Ready\"    handle=\"val1\"                  value=\"thread_id=%x[val1]\" info=\"Thread execution was resumed.\"/>\n    <event id=\"0xF200 + 0x11\" level=\"API\"    property=\"ThreadDetach\"                                                                      value=\"thread_id=%x[val1]\" info=\"osThreadDetach function was called.\"/>\n    <event id=\"0xF200 + 0x12\" level=\"Op\"     property=\"ThreadDetached\"                                                                    value=\"thread_id=%x[val1]\" info=\"Thread was detached.\"/>\n    <event id=\"0xF200 + 0x13\" level=\"API\"    property=\"ThreadJoin\"                                                                        value=\"thread_id=%x[val1]\" info=\"osThreadJoin function was called.\"/>\n    <event id=\"0xF200 + 0x14\" level=\"Op\"     property=\"ThreadJoinPending\"                                                                 value=\"thread_id=%x[val1]\" info=\"Thread join is pending.\"/>\n    <event id=\"0xF200 + 0x15\" level=\"Op\"     property=\"ThreadJoined\"                                                                      value=\"thread_id=%x[val1]\" info=\"Thread joined.\"/>\n    <event id=\"0xF200 + 0x16\" level=\"Detail\" property=\"ThreadBlocked\"                     state=\"Blocked\"  handle=\"val1\"                  value=\"thread_id=%x[val1], timeout=%d[val2]\" info=\"Current running thread execution was blocked.\"/>\n    <event id=\"0xF200 + 0x17\" level=\"Detail\" property=\"ThreadUnblocked\"                   state=\"Ready\"    handle=\"val1\"                  value=\"thread_id=%x[val1], ret_val=%E[val2, rtx_t:status]\" info=\"Thread execution was unblocked.\"/>\n    <event id=\"0xF200 + 0x18\" level=\"Detail\" property=\"ThreadPreempted\"                   state=\"Ready\"    handle=\"val1\"                  value=\"thread_id=%x[val1]\" info=\"Current running thread execution was preempted.\"/>\n    <event id=\"0xF200 + 0x19\" level=\"Op\"     property=\"ThreadSwitched\"                    state=\"Running\"  handle=\"val1\"                  value=\"thread_id=%x[val1]\" info=\"Switched execution of the current running thread.\"/>\n    <event id=\"0xF200 + 0x1A\" level=\"API\"    property=\"ThreadExit\"                                                                        value=\"\" info=\"osThreadExit function was called.\"/>\n    <event id=\"0xF200 + 0x1B\" level=\"API\"    property=\"ThreadTerminate\"                                                                   value=\"thread_id=%x[val1]\" info=\"osThreadTerminate function was called.\"/>\n    <event id=\"0xF200 + 0x1C\" level=\"Op\"     property=\"ThreadDestroyed\"  tracking=\"Stop\"  state=\"Inactive\" handle=\"val1\"                  value=\"thread_id=%x[val1]\" info=\"Thread execution was terminated.\"/>\n    <event id=\"0xF200 + 0x2E\" level=\"API\"    property=\"ThreadFeedWatchdog\"                                                                value=\"ticks=%d[val1]\" info=\"osThreadFeedWatchdog function was called.\"/>\n    <event id=\"0xF200 + 0x2F\" level=\"Op\"     property=\"ThreadFeedWatchdogDone\"                                                            value=\"\" info=\"Thread watchdog timer was feed.\"/>\n    <event id=\"0xF200 + 0x32\" level=\"API\"    property=\"ThreadProtectPrivileged\"                                                           value=\"\" info=\"osThreadProtectPrivileged function was called.\"/>\n    <event id=\"0xF200 + 0x33\" level=\"Op\"     property=\"ThreadPrivilegedProtected\"                                                         value=\"\" info=\"Creation of privileged threads was protected.\"/>\n    <event id=\"0xF200 + 0x1D\" level=\"API\"    property=\"ThreadGetCount\"                                                                    value=\"count=%d[val1]\" info=\"osThreadGetCount function was called and number of active threads was retrieved.\"/>\n    <event id=\"0xF200 + 0x1E\" level=\"API\"    property=\"ThreadEnumerate\"                                                                   value=\"thread_array=%x[val1], array_items=%d[val2], count=%d[val3]\" info=\"osThreadEnumerate function was called and active threads were enumerated.\"/>\n    <event id=\"0xF200 + 0x34\" level=\"API\"    property=\"ThreadSuspendClass\"                                                                value=\"safety_class=%d[val1], mode=%x[val2]\" info=\"osThreadSuspendClass function was called.\"/>\n    <event id=\"0xF200 + 0x35\" level=\"API\"    property=\"ThreadResumeClass\"                                                                 value=\"safety_class=%d[val1], mode=%x[val2]\" info=\"osThreadResumeClass function was called.\"/>\n    <event id=\"0xF200 + 0x36\" level=\"API\"    property=\"ThreadTerminateZone\"                                                               value=\"zone=%d[val1]\" info=\"osThreadTerminateZone function was called.\"/>\n    <event id=\"0xF200 + 0x37\" level=\"Error\"  property=\"ThreadWatchdogExpired\"                                                             value=\"thread_id=%x[val1]\" info=\"Thread watchdog timer has expired.\"/>\n\n    <event id=\"0xF400 + 0x00\" level=\"Error\"  property=\"ThreadFlagsError\"            value=\"thread_id=%x[val1], status=%E[val2, rtx_t:status]\" info=\"Thread flags error occurred.\"/>\n    <event id=\"0xF400 + 0x01\" level=\"API\"    property=\"ThreadFlagsSet\"              value=\"thread_id=%x[val1], flags=%x[val2]\" info=\"osThreadFlagsSet function was called.\"/>\n    <event id=\"0xF400 + 0x02\" level=\"Op\"     property=\"ThreadFlagsSetDone\"          value=\"thread_id=%x[val1], thread_flags=%x[val2]\" info=\"Thread flags were set.\"/>\n    <event id=\"0xF400 + 0x03\" level=\"API\"    property=\"ThreadFlagsClear\"            value=\"flags=%x[val1]\" info=\"osThreadFlagsClear function was called.\"/>\n    <event id=\"0xF400 + 0x04\" level=\"Op\"     property=\"ThreadFlagsClearDone\"        value=\"thread_flags=%x[val1]\" info=\"Thread flags were cleared.\"/>\n    <event id=\"0xF400 + 0x05\" level=\"API\"    property=\"ThreadFlagsGet\"              value=\"thread_flags=%x[val1]\" info=\"osThreadFlagsGet function was called and thread flags were retrieved.\"/>\n    <event id=\"0xF400 + 0x06\" level=\"API\"    property=\"ThreadFlagsWait\"             value=\"flags=%x[val1], options=%x[val2], timeout=%d[val3]\" info=\"osThreadFlagsWait function was called.\"/>\n    <event id=\"0xF400 + 0x07\" level=\"Op\"     property=\"ThreadFlagsWaitPending\"      value=\"flags=%x[val1], options=%x[val2], timeout=%d[val3]\" info=\"Waiting for thread flags to become signaled.\"/>\n    <event id=\"0xF400 + 0x08\" level=\"Op\"     property=\"ThreadFlagsWaitTimeout\"      value=\"thread_id=%x[val1]\" info=\"Waiting for thread flags timed out.\"/>\n    <event id=\"0xF400 + 0x09\" level=\"Op\"     property=\"ThreadFlagsWaitCompleted\"    value=\"flags=%x[val1], options=%x[val2], thread_flags=%x[val3], thread_id=%x[val4]\" info=\"Wait for thread flags completed.\"/>\n    <event id=\"0xF400 + 0x0A\" level=\"Op\"     property=\"ThreadFlagsWaitNotCompleted\" value=\"flags=%x[val1], options=%x[val2]\" info=\"Wait for thread flags not completed.\"/>\n\n    <event id=\"0xF300 + 0x00\" level=\"Error\"  property=\"DelayError\"         value=\"status=%E[val1, rtx_t:status]\" info=\"osDelay/osDelayUntil error occurred.\"/>\n    <event id=\"0xF300 + 0x01\" level=\"API\"    property=\"Delay\"              value=\"ticks=%d[val1]\" info=\"osDelay function was called.\"/>\n    <event id=\"0xF300 + 0x02\" level=\"API\"    property=\"DelayUntil\"         value=\"ticks=%d[val1]\" info=\"osDelayUntil function was called.\"/>\n    <event id=\"0xF300 + 0x03\" level=\"Op\"     property=\"DelayStarted\"       value=\"ticks=%d[val1]\" info=\"osDelay started.\"/>\n    <event id=\"0xF300 + 0x04\" level=\"Op\"     property=\"DelayUntilStarted\"  value=\"ticks=%d[val1]\" info=\"osDelayUntil started.\"/>\n    <event id=\"0xF300 + 0x05\" level=\"Op\"     property=\"DelayCompleted\"     value=\"thread_id=%x[val1]\" info=\"osDelay/osDelayUntil completed.\"/>\n\n    <event id=\"0xF600 + 0x00\" level=\"Error\"  property=\"TimerError\"     value=\"timer_id=%x[val1], status=%E[val2, rtx_t:status]\" info=\"Timer error occurred.\"/>\n    <event id=\"0xF600 + 0x01\" level=\"Op\"     property=\"TimerCallback\"  value=\"func=%S[val1], argument=%x[val2]\" info=\"Timer callback function was called.\"/>\n    <event id=\"0xF600 + 0x02\" level=\"API\"    property=\"TimerNew\"       value=\"func=%S[val1], type=%E[val2, rtx_timer_type:id], argument=%x[val3], attr=%x[val4]\" info=\"osTimerNew function was called.\"/>\n    <event id=\"0xF600 + 0x04\" level=\"Op\"     property=\"TimerCreated\"   value=\"timer_id=%x[val1]\" info=\"Timer object was created.\"/>\n    <event id=\"0xF600 + 0x05\" level=\"API\"    property=\"TimerGetName\"   value=\"timer_id=%x[val1], name=%N[val2]\" info=\"osTimerGetName function was called and object name was retrieved.\"/>\n    <event id=\"0xF600 + 0x07\" level=\"API\"    property=\"TimerStart\"     value=\"timer_id=%x[val1], ticks=%d[val2]\" info=\"osTimerStart function was called.\"/>\n    <event id=\"0xF600 + 0x08\" level=\"Op\"     property=\"TimerStarted\"   value=\"timer_id=%x[val1]\" info=\"Timer execution was started.\"/>\n    <event id=\"0xF600 + 0x09\" level=\"API\"    property=\"TimerStop\"      value=\"timer_id=%x[val1]\" info=\"osTimerStop function was called.\"/>\n    <event id=\"0xF600 + 0x0A\" level=\"Op\"     property=\"TimerStopped\"   value=\"timer_id=%x[val1]\" info=\"Timer execution was stopped.\"/>\n    <event id=\"0xF600 + 0x0B\" level=\"API\"    property=\"TimerIsRunning\" value=\"timer_id=%x[val1], running=%d[val2]\" info=\"osTimerIsRunning function was called and timer running state was retrieved.\"/>\n    <event id=\"0xF600 + 0x0C\" level=\"API\"    property=\"TimerDelete\"    value=\"timer_id=%x[val1]\" info=\"osTimerDelete function was called.\"/>\n    <event id=\"0xF600 + 0x0D\" level=\"Op\"     property=\"TimerDestroyed\" value=\"timer_id=%x[val1]\" info=\"Timer object was deleted.\"/>\n\n    <event id=\"0xF500 + 0x00\" level=\"Error\"  property=\"EventFlagsError\"            value=\"ef_id=%x[val1], status=%E[val2, rtx_t:status]\" info=\"Event flags error occurred.\"/>\n    <event id=\"0xF500 + 0x01\" level=\"API\"    property=\"EventFlagsNew\"              value=\"attr=%x[val1]\" info=\"osEventFlagsNew function was called.\"/>\n    <event id=\"0xF500 + 0x03\" level=\"Op\"     property=\"EventFlagsCreated\"          value=\"ef_id=%x[val1]\" info=\"Event flags object was created.\"/>\n    <event id=\"0xF500 + 0x04\" level=\"API\"    property=\"EventFlagsGetName\"          value=\"ef_id=%x[val1], name=%N[val2]\" info=\"osEventFlagsGetName function was called and object name was retrieved.\"/>\n    <event id=\"0xF500 + 0x06\" level=\"API\"    property=\"EventFlagsSet\"              value=\"ef_id=%x[val1], flags=%x[val2]\" info=\"osEventFlagsSet function was called.\"/>\n    <event id=\"0xF500 + 0x07\" level=\"Op\"     property=\"EventFlagsSetDone\"          value=\"ef_id=%x[val1], event_flags=%x[val2]\" info=\"Event flags were set.\"/>\n    <event id=\"0xF500 + 0x08\" level=\"API\"    property=\"EventFlagsClear\"            value=\"ef_id=%x[val1], flags=%x[val2]\" info=\"osEventFlagsClear function was called.\"/>\n    <event id=\"0xF500 + 0x09\" level=\"Op\"     property=\"EventFlagsClearDone\"        value=\"ef_id=%x[val1], event_flags=%x[val2]\" info=\"Event flags were cleared.\"/>\n    <event id=\"0xF500 + 0x0A\" level=\"API\"    property=\"EventFlagsGet\"              value=\"ef_id=%x[val1], event_flags=%x[val2]\" info=\"osEventFlagsGet function was called and current event flags were retrieved.\"/>\n    <event id=\"0xF500 + 0x0B\" level=\"API\"    property=\"EventFlagsWait\"             value=\"ef_id=%x[val1], flags=%x[val2], options=%x[val3], timeout=%d[val4]\" info=\"osEventFlagsWait function was called.\"/>\n    <event id=\"0xF500 + 0x0C\" level=\"Op\"     property=\"EventFlagsWaitPending\"      value=\"ef_id=%x[val1], flags=%x[val2], options=%x[val3], timeout=%d[val4]\" info=\"Event flags wait is pending.\"/>\n    <event id=\"0xF500 + 0x0D\" level=\"Op\"     property=\"EventFlagsWaitTimeout\"      value=\"ef_id=%x[val1]\" info=\"Event flags wait timed out.\"/>\n    <event id=\"0xF500 + 0x0E\" level=\"Op\"     property=\"EventFlagsWaitCompleted\"    value=\"ef_id=%x[val1], flags=%x[val2], options=%x[val3], event_flags=%x[val4]\" info=\"Event flags wait completed.\"/>\n    <event id=\"0xF500 + 0x0F\" level=\"Op\"     property=\"EventFlagsWaitNotCompleted\" value=\"ef_id=%x[val1], flags=%x[val2], options=%x[val3]\" info=\"Event flags wait not completed.\"/>\n    <event id=\"0xF500 + 0x10\" level=\"API\"    property=\"EventFlagsDelete\"           value=\"ef_id=%x[val1]\" info=\"osEventFlagsDelete function was called.\"/>\n    <event id=\"0xF500 + 0x11\" level=\"Op\"     property=\"EventFlagsDestroyed\"        value=\"ef_id=%x[val1]\" info=\"Event flags object was deleted.\"/>\n\n    <event id=\"0xF700 + 0x00\" level=\"Error\"  property=\"MutexError\"          state=\"Error\" handle=\"val1\" value=\"mutex_id=%x[val1], status=%E[val2, rtx_t:status]\" info=\"Mutex error occurred.\"/>\n    <event id=\"0xF700 + 0x01\" level=\"API\"    property=\"MutexNew\"            value=\"attr=%x[val1]\" info=\"osMutexNew function was called\"/>\n    <event id=\"0xF700 + 0x03\" level=\"Op\"     property=\"MutexCreated\"        tracking=\"Start\" state=\"Free\" handle=\"val1\" value=\"mutex_id=%x[val1]\" info=\"Mutex object was created\"/>\n    <event id=\"0xF700 + 0x04\" level=\"API\"    property=\"MutexGetName\"        value=\"mutex_id=%x[val1], name=%N[val2]\" info=\"osMutexGetName function was called and object name was retrieved.\"/>\n    <event id=\"0xF700 + 0x06\" level=\"API\"    property=\"MutexAcquire\"        state=\"Used\" handle=\"val1\" value=\"mutex_id=%x[val1], timeout=%d[val2]\" info=\"osMutexAcquire function was called.\"/>\n    <event id=\"0xF700 + 0x07\" level=\"Op\"     property=\"MutexAcquirePending\" value=\"mutex_id=%x[val1], timeout=%d[val2]\" info=\"Mutex object acquire is pending.\"/>\n    <event id=\"0xF700 + 0x08\" level=\"Op\"     property=\"MutexAcquireTimeout\" value=\"mutex_id=%x[val1]\" info=\"Mutex object acquire timed out.\"/>\n    <event id=\"0xF700 + 0x09\" level=\"Op\"     property=\"MutexAcquired\"       value=\"mutex_id=%x[val1], lock=%d[val2]\" info=\"Mutex object was acquired.\"/>\n    <event id=\"0xF700 + 0x0A\" level=\"Op\"     property=\"MutexNotAcquired\"    value=\"mutex_id=%x[val1]\" info=\"Mutex object was not acquired.\"/>\n    <event id=\"0xF700 + 0x0B\" level=\"API\"    property=\"MutexRelease\"        state=\"Free\" handle=\"val1\" value=\"mutex_id=%x[val1]\" info=\"osMutexRelease function was called.\"/>\n    <event id=\"0xF700 + 0x0C\" level=\"Op\"     property=\"MutexReleased\"       value=\"mutex_id=%x[val1], lock=%d[val2]\" info=\"Mutex object was released.\"/>\n    <event id=\"0xF700 + 0x0D\" level=\"API\"    property=\"MutexGetOwner\"       value=\"mutex_id=%x[val1], thread_id=%x[val2]\" info=\"osMutexGetOwner function was called and mutex owner thread was retrieved.\"/>\n    <event id=\"0xF700 + 0x0E\" level=\"API\"    property=\"MutexDelete\"         value=\"mutex_id=%x[val1]\" info=\"osMutexDelete function was called.\"/>\n    <event id=\"0xF700 + 0x0F\" level=\"Op\"     property=\"MutexDestroyed\"      tracking=\"Stop\" state=\"Free\" handle=\"val1\" value=\"mutex_id=%x[val1]\" info=\"Mutex object was deleted.\"/>\n\n    <event id=\"0xF800 + 0x00\" level=\"Error\"  property=\"SemaphoreError\"          value=\"semaphore_id=%x[val1], status=%E[val2, rtx_t:status]\" info=\"Semaphore error occurred.\"/>\n    <event id=\"0xF800 + 0x01\" level=\"API\"    property=\"SemaphoreNew\"            value=\"max_count=%d[val1], initial_count=%d[val2], attr=%x[val3]\" info=\"osSemaphoreNew function was called.\"/>\n    <event id=\"0xF800 + 0x03\" level=\"Op\"     property=\"SemaphoreCreated\"        value=\"semaphore_id=%x[val1]\" info=\"Semaphore object was created.\"/>\n    <event id=\"0xF800 + 0x04\" level=\"API\"    property=\"SemaphoreGetName\"        value=\"semaphore_id=%x[val1], name=%N[val2]\" info=\"osSemaphoreGetName function was called and object name was retrieved.\"/>\n    <event id=\"0xF800 + 0x06\" level=\"API\"    property=\"SemaphoreAcquire\"        value=\"semaphore_id=%x[val1], timeout=%d[val2]\" info=\"osSemaphoreAcquire function was called.\"/>\n    <event id=\"0xF800 + 0x07\" level=\"Op\"     property=\"SemaphoreAcquirePending\" value=\"semaphore_id=%x[val1], timeout=%d[val2]\" info=\"Semaphore object acquire is pending.\"/>\n    <event id=\"0xF800 + 0x08\" level=\"Op\"     property=\"SemaphoreAcquireTimeout\" value=\"semaphore_id=%x[val1]\" info=\"Semaphore object acquire timed out.\"/>\n    <event id=\"0xF800 + 0x09\" level=\"Op\"     property=\"SemaphoreAcquired\"       value=\"semaphore_id=%x[val1], tokens=%d[val2]\" info=\"Semaphore object was acquired.\"/>\n    <event id=\"0xF800 + 0x0A\" level=\"Op\"     property=\"SemaphoreNotAcquired\"    value=\"semaphore_id=%x[val1]\" info=\"Semaphore object was not acquired.\"/>\n    <event id=\"0xF800 + 0x0B\" level=\"API\"    property=\"SemaphoreRelease\"        value=\"semaphore_id=%x[val1]\" info=\"osSemaphoreRelease function was called.\"/>\n    <event id=\"0xF800 + 0x0C\" level=\"Op\"     property=\"SemaphoreReleased\"       value=\"semaphore_id=%x[val1], tokens=%d[val2]\" info=\"Semaphore object was released.\"/>\n    <event id=\"0xF800 + 0x0D\" level=\"API\"    property=\"SemaphoreGetCount\"       value=\"semaphore_id=%x[val1], count=%d[val2]\" info=\"osSemaphoreGetCount function was called and current number of available tokens was retrieved.\"/>\n    <event id=\"0xF800 + 0x0E\" level=\"API\"    property=\"SemaphoreDelete\"         value=\"semaphore_id=%x[val1]\" info=\"osSemaphoreDelete function was called.\"/>\n    <event id=\"0xF800 + 0x0F\" level=\"Op\"     property=\"SemaphoreDestroyed\"      value=\"semaphore_id=%x[val1]\" info=\"Semaphore object was deleted.\"/>\n\n    <event id=\"0xF900 + 0x00\" level=\"Error\"  property=\"MemoryPoolError\"        value=\"mp_id=%x[val1], status=%E[val2, rtx_t:status]\" info=\"Memory pool error occurred.\"/>\n    <event id=\"0xF900 + 0x01\" level=\"API\"    property=\"MemoryPoolNew\"          value=\"block_count=%d[val1], block_size=%d[val2], attr=%x[val3]\" info=\"osMemoryPoolNew function was called.\"/>\n    <event id=\"0xF900 + 0x03\" level=\"Op\"     property=\"MemoryPoolCreated\"      value=\"mp_id=%x[val1]\" info=\"Memory Pool object was created\"/>\n    <event id=\"0xF900 + 0x04\" level=\"API\"    property=\"MemoryPoolGetName\"      value=\"mp_id=%x[val1], name=%N[val2]\" info=\"osMemoryPoolGetName function was called and object name was retrieved.\"/>\n    <event id=\"0xF900 + 0x06\" level=\"API\"    property=\"MemoryPoolAlloc\"        value=\"mp_id=%x[val1], timeout=%d[val2]\" info=\"osMemoryPoolAlloc function was called.\"/>\n    <event id=\"0xF900 + 0x07\" level=\"Op\"     property=\"MemoryPoolAllocPending\" value=\"mp_id=%x[val1], timeout=%d[val2]\" info=\"Memory pool allocation is pending.\"/>\n    <event id=\"0xF900 + 0x08\" level=\"Op\"     property=\"MemoryPoolAllocTimeout\" value=\"mp_id=%x[val1]\" info=\"Memory pool allocation timed out.\"/>\n    <event id=\"0xF900 + 0x09\" level=\"Op\"     property=\"MemoryPoolAllocated\"    value=\"mp_id=%x[val1], block=%x[val2]\" info=\"Memory pool was allocated.\"/>\n    <event id=\"0xF900 + 0x0A\" level=\"Op\"     property=\"MemoryPoolAllocFailed\"  value=\"mp_id=%x[val1]\" info=\"Memory pool was not allocated.\"/>\n    <event id=\"0xF900 + 0x0B\" level=\"API\"    property=\"MemoryPoolFree\"         value=\"mp_id=%x[val1], block=%x[val2]\" info=\"osMemoryPoolFree function was called.\"/>\n    <event id=\"0xF900 + 0x0C\" level=\"Op\"     property=\"MemoryPoolDeallocated\"  value=\"mp_id=%x[val1], block=%x[val2]\" info=\"Memory pool was deallocated.\"/>\n    <event id=\"0xF900 + 0x0D\" level=\"Op\"     property=\"MemoryPoolFreeFailed\"   value=\"mp_id=%x[val1], block=%x[val2]\" info=\"Memory pool was not deallocated.\"/>\n    <event id=\"0xF900 + 0x0E\" level=\"API\"    property=\"MemoryPoolGetCapacity\"  value=\"mp_id=%x[val1], capacity=%d[val2]\" info=\"osMemoryPoolGetCapacity function was called and maximum number of memory blocks was retrieved.\"/>\n    <event id=\"0xF900 + 0x0F\" level=\"API\"    property=\"MemoryPoolGetBlockSize\" value=\"mp_id=%x[val1], block_size=%d[val2]\" info=\"osMemoryPoolGetBlockSize function was called and memory block size was retrieved.\"/>\n    <event id=\"0xF900 + 0x10\" level=\"API\"    property=\"MemoryPoolGetCount\"     value=\"mp_id=%x[val1], count=%d[val2]\" info=\"osMemoryPoolGetCount function was called and number of used memory blocks was retrieved.\"/>\n    <event id=\"0xF900 + 0x11\" level=\"API\"    property=\"MemoryPoolGetSpace\"     value=\"mp_id=%x[val1], space=%d[val2]\" info=\"osMemoryPoolGetSpace function was called and number of available memory blocks was retrieved.\"/>\n    <event id=\"0xF900 + 0x12\" level=\"API\"    property=\"MemoryPoolDelete\"       value=\"mp_id=%x[val1]\" info=\"osMemoryPoolDelete function was called.\"/>\n    <event id=\"0xF900 + 0x13\" level=\"Op\"     property=\"MemoryPoolDestroyed\"    value=\"mp_id=%x[val1]\" info=\"Memory pool object was deleted.\"/>\n\n    <event id=\"0xFA00 + 0x00\" level=\"Error\"  property=\"MessageQueueError\"         value=\"mq_id=%x[val1], status=%E[val2, rtx_t:status]\" info=\"Message queue error occurred.\"/>\n    <event id=\"0xFA00 + 0x01\" level=\"API\"    property=\"MessageQueueNew\"           value=\"msg_count=%d[val1], msg_size=%d[val2], attr=%x[val3]\" info=\"osMessageQueueNew function was called.\"/>\n    <event id=\"0xFA00 + 0x03\" level=\"Op\"     property=\"MessageQueueCreated\"       value=\"mq_id=%x[val1]\" info=\"Message Queue object was created\"/>\n    <event id=\"0xFA00 + 0x04\" level=\"API\"    property=\"MessageQueueGetName\"       value=\"mq_id=%x[val1], name=%N[val2]\" info=\"osMessageQueueGetName function was called and object name was retrieved.\"/>\n    <event id=\"0xFA00 + 0x06\" level=\"API\"    property=\"MessageQueuePut\"           value=\"mq_id=%x[val1], msg_ptr=%x[val2], msg_prio=%d[val3], timeout=%d[val4]\" info=\"osMessageQueuePut function was called.\"/>\n    <event id=\"0xFA00 + 0x07\" level=\"Op\"     property=\"MessageQueuePutPending\"    value=\"mq_id=%x[val1], msg_ptr=%x[val2], timeout=%d[val3]\" info=\"Message put is pending.\"/>\n    <event id=\"0xFA00 + 0x08\" level=\"Op\"     property=\"MessageQueuePutTimeout\"    value=\"mq_id=%x[val1]\" info=\"Message put timed out.\"/>\n    <event id=\"0xFA00 + 0x09\" level=\"Op\"     property=\"MessageQueueInsertPending\" value=\"mq_id=%x[val1], msg_ptr=%x[val2]\" info=\"Message insert is pending.\"/>\n    <event id=\"0xFA00 + 0x0A\" level=\"Op\"     property=\"MessageQueueInserted\"      value=\"mq_id=%x[val1], msg_ptr=%x[val2]\" info=\"Message was inserted.\"/>\n    <event id=\"0xFA00 + 0x0B\" level=\"Op\"     property=\"MessageQueueNotInserted\"   value=\"mq_id=%x[val1], msg_ptr=%x[val2]\" info=\"Message was not inserted\"/>\n    <event id=\"0xFA00 + 0x0C\" level=\"API\"    property=\"MessageQueueGet\"           value=\"mq_id=%x[val1], msg_ptr=%x[val2], msg_prio=%x[val3], timeout=%d[val4]\" info=\"osMessageQueueGet function was called.\"/>\n    <event id=\"0xFA00 + 0x0D\" level=\"Op\"     property=\"MessageQueueGetPending\"    value=\"mq_id=%x[val1], msg_ptr=%x[val2], timeout=%d[val3]\" info=\"Message get is pending.\"/>\n    <event id=\"0xFA00 + 0x0E\" level=\"Op\"     property=\"MessageQueueGetTimeout\"    value=\"mq_id=%x[val1]\" info=\"Message get timed out.\"/>\n    <event id=\"0xFA00 + 0x0F\" level=\"Op\"     property=\"MessageQueueRetrieved\"     value=\"mq_id=%x[val1], msg_ptr=%x[val2]\" info=\"Message was retrieved.\"/>\n    <event id=\"0xFA00 + 0x10\" level=\"Op\"     property=\"MessageQueueNotRetrieved\"  value=\"mq_id=%x[val1], msg_ptr=%x[val2]\" info=\"Message was not retrieved.\"/>\n    <event id=\"0xFA00 + 0x11\" level=\"API\"    property=\"MessageQueueGetCapacity\"   value=\"mq_id=%x[val1], capacity=%d[val2]\" info=\"osMessageQueueGetCapacity function was called and maximum number of messages was retrieved.\"/>\n    <event id=\"0xFA00 + 0x12\" level=\"API\"    property=\"MessageQueueGetMsgSize\"    value=\"mq_id=%x[val1], msg_size=%d[val2]\" info=\"osMessageQueueGetMsgSize function was called and maximum message size was retrieved.\"/>\n    <event id=\"0xFA00 + 0x13\" level=\"API\"    property=\"MessageQueueGetCount\"      value=\"mq_id=%x[val1], count=%d[val2]\" info=\"osMessageQueueGetCount function was called and number of queued messages was retrieved.\"/>\n    <event id=\"0xFA00 + 0x14\" level=\"API\"    property=\"MessageQueueGetSpace\"      value=\"mq_id=%x[val1], space=%d[val2]\" info=\"osMessageQueueGetSpace function was called and number of available message slots was retrieved.\"/>\n    <event id=\"0xFA00 + 0x15\" level=\"API\"    property=\"MessageQueueReset\"         value=\"mq_id=%x[val1]\" info=\"osMessageQueueReset function was called.\"/>\n    <event id=\"0xFA00 + 0x16\" level=\"Op\"     property=\"MessageQueueResetDone\"     value=\"mq_id=%x[val1]\" info=\"Message queue was reset.\"/>\n    <event id=\"0xFA00 + 0x17\" level=\"API\"    property=\"MessageQueueDelete\"        value=\"mq_id=%x[val1]\" info=\"osMessageQueueDelete function was called.\"/>\n    <event id=\"0xFA00 + 0x18\" level=\"Op\"     property=\"MessageQueueDestroyed\"     value=\"mq_id=%x[val1]\" info=\"Message queue object was deleted.\"/>\n\n  </events>\n</component_viewer>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s",
    "content": ";/*\n; * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; * -----------------------------------------------------------------------------\n; *\n; * Project:     CMSIS-RTOS RTX\n; * Title:       ARMv6-M Exception handlers\n; *\n; * -----------------------------------------------------------------------------\n; */\n\n\nI_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset\nTCB_SP_OFS      EQU      56                     ; TCB.SP offset\nTCB_ZONE_OFS    EQU      68                     ; TCB.zone offset\n\nosRtxErrorStackOverflow\\\n                EQU      1                      ; Stack overflow\nosRtxErrorSVC   EQU      6                      ; Invalid SVC function called\n\n\n                PRESERVE8\n                THUMB\n\n\n                AREA     |.constdata|, DATA, READONLY\n                EXPORT   irqRtxLib\nirqRtxLib       DCB      0                      ; Non weak library reference\n\n\n                AREA     |.text|, CODE, READONLY\n\n\nSVC_Handler     PROC\n                EXPORT   SVC_Handler\n                IMPORT   osRtxUserSVC\n                IMPORT   osRtxInfo\n            IF :DEF:RTX_STACK_CHECK\n                IMPORT   osRtxThreadStackCheck\n                IMPORT   osRtxKernelErrorNotify\n            ENDIF\n            IF :DEF:RTX_SVC_PTR_CHECK\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Base|\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Length|\n                IMPORT   osRtxKernelErrorNotify\n            ENDIF\n            IF :DEF:RTX_EXECUTION_ZONE\n                IMPORT   osZoneSetup_Callback\n            ENDIF\n\n                MOV      R0,LR\n                LSRS     R0,R0,#3               ; Determine return stack from EXC_RETURN bit 2\n                BCC      SVC_MSP                ; Branch if return stack is MSP\n                MRS      R0,PSP                 ; Get PSP\n\nSVC_Number\n                LDR      R1,[R0,#24]            ; Load saved PC from stack\n                SUBS     R1,R1,#2               ; Point to SVC instruction\n                LDRB     R1,[R1]                ; Load SVC number\n                CMP      R1,#0                  ; Check SVC number\n                BNE      SVC_User               ; Branch if not SVC 0\n\n            IF :DEF:RTX_SVC_PTR_CHECK\n\n                SUBS     R1,R7,#0x01            ; Clear T-bit of function address\n                LSLS     R2,R1,#29              ; Check if 8-byte aligned\n                BEQ      SVC_PtrBoundsCheck     ; Branch if address is aligned\n\nSVC_PtrInvalid\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                MOVS     R0,#osRtxErrorSVC      ; Parameter: code\n                MOV      R1,R7                  ; Parameter: object_id\n                BL       osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify\n                POP      {R2,R3}                ; Restore SP and EXC_RETURN\n                MOV      LR,R3                  ; Set EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\nSVC_PtrBoundsCheck\n                LDR      R2,=|Image$$RTX_SVC_VENEERS$$Base|\n                LDR      R3,=|Image$$RTX_SVC_VENEERS$$Length|\n                SUBS     R2,R1,R2               ; Subtract SVC table base address\n                CMP      R2,R3                  ; Compare with SVC table boundaries\n                BHS      SVC_PtrInvalid         ; Branch if address is out of bounds\n\n            ENDIF\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LDMIA    R0,{R0-R3}             ; Load function parameters from stack\n                BLX      R7                     ; Call service function\n                POP      {R2,R3}                ; Restore SP and EXC_RETURN\n                STR      R0,[R2]                ; Store function return value\n                MOV      LR,R3                  ; Set EXC_RETURN\n\nSVC_Context\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run\n                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next\n                CMP      R1,R2                  ; Check if thread switch is required\n                BEQ      SVC_Exit               ; Branch when threads are the same\n\n                SUBS     R3,R3,#8               ; Adjust address\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n                CMP      R1,#0\n                BEQ      SVC_ContextRestore     ; Branch if running thread is deleted\n\nSVC_ContextSave\n                MRS      R0,PSP                 ; Get PSP\n                SUBS     R0,R0,#32              ; Calculate SP: space for R4..R11\n                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP\n\n            IF :DEF:RTX_STACK_CHECK\n\n                PUSH     {R1,R2}                ; Save osRtxInfo.thread.run: curr & next\n                MOV      R0,R1                  ; Parameter: osRtxInfo.thread.run.curr\n                BL       osRtxThreadStackCheck  ; Check if thread stack is overrun\n                POP      {R1,R2}                ; Restore osRtxInfo.thread.run: curr & next\n                CMP      R0,#0\n                BNE      SVC_ContextSaveRegs    ; Branch when stack check is ok\n\n                MOVS     R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id\n                BL       osRtxKernelErrorNotify      ; Call osRtxKernelErrorNotify\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS   ; Load address of osRtxInfo.thread.run\n                LDR      R2,[R3,#4]             ; Load osRtxInfo.thread.run: next\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n                MOVS     R1,#0                  ; Simulate deleted running thread\n                B        SVC_ContextRestore     ; Branch to context restore handling\n\nSVC_ContextSaveRegs\n                LDR      R0,[R1,#TCB_SP_OFS]    ; Load SP\n\n            ENDIF\n\n                STMIA    R0!,{R4-R7}            ; Save R4..R7\n                MOV      R4,R8\n                MOV      R5,R9\n                MOV      R6,R10\n                MOV      R7,R11\n                STMIA    R0!,{R4-R7}            ; Save R8..R11\n\nSVC_ContextRestore\n                 MOVS     R4,R2                 ; Assign osRtxInfo.thread.run.next to R4\n            IF :DEF:RTX_EXECUTION_ZONE\n                 MOVS     R3,#TCB_ZONE_OFS      ; Get TCB.zone offset\n                 LDRB     R0,[R2,R3]            ; Load osRtxInfo.thread.run.next: zone\n                 CMP      R1,#0\n                 BEQ      SVC_ZoneSetup         ; Branch if running thread is deleted\n                 LDRB     R1,[R1,R3]            ; Load osRtxInfo.thread.run.curr: zone\n                 CMP      R0,R1                 ; Check if next:zone == curr:zone\n                 BEQ      SVC_ContextRestore_N  ; Branch if zone has not changed\n\nSVC_ZoneSetup\n                 BL     osZoneSetup_Callback    ;  Setup zone for next thread\n            ENDIF\n\nSVC_ContextRestore_N\n                LDR      R0,[R4,#TCB_SP_OFS]    ; Load SP\n                ADDS     R0,R0,#16              ; Adjust address\n                LDMIA    R0!,{R4-R7}            ; Restore R8..R11\n                MOV      R8,R4\n                MOV      R9,R5\n                MOV      R10,R6\n                MOV      R11,R7\n                MSR      PSP,R0                 ; Set PSP\n                SUBS     R0,R0,#32              ; Adjust address\n                LDMIA    R0!,{R4-R7}            ; Restore R4..R7\n\n                MOVS     R0,#2                  ; Binary complement of 0xFFFFFFFD\n                MVNS     R0,R0                  ; Set EXC_RETURN value\n                BX       R0                     ; Exit from handler\n\nSVC_MSP\n                MRS      R0,MSP                 ; Get MSP\n                B        SVC_Number\n\nSVC_Exit\n                BX       LR                     ; Exit from handler\n\nSVC_User\n                LDR      R2,=osRtxUserSVC       ; Load address of SVC table\n                LDR      R3,[R2]                ; Load SVC maximum number\n                CMP      R1,R3                  ; Check SVC number range\n                BHI      SVC_Exit               ; Branch if out of range\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LSLS     R1,R1,#2\n                LDR      R3,[R2,R1]             ; Load address of SVC function\n                MOV      R12,R3\n                LDMIA    R0,{R0-R3}             ; Load function parameters from stack\n                BLX      R12                    ; Call service function\n                POP      {R2,R3}                ; Restore SP and EXC_RETURN\n                STR      R0,[R2]                ; Store function return value\n\n                BX       R3                     ; Return from handler\n\n                ALIGN\n                ENDP\n\n\nPendSV_Handler  PROC\n                EXPORT   PendSV_Handler\n                IMPORT   osRtxPendSV_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler\n                POP      {R0,R1}                ; Restore EXC_RETURN\n                MOV      LR,R1                  ; Set EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n\nSysTick_Handler PROC\n                EXPORT   SysTick_Handler\n                IMPORT   osRtxTick_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxTick_Handler      ; Call osRtxTick_Handler\n                POP      {R0,R1}                ; Restore EXC_RETURN\n                MOV      LR,R1                  ; Set EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n\n            IF :DEF:RTX_SAFETY_FEATURES\n\nosFaultResume   PROC\n                EXPORT   osFaultResume\n\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n            ENDIF\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s",
    "content": ";/*\n; * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; * -----------------------------------------------------------------------------\n; *\n; * Project:     CMSIS-RTOS RTX\n; * Title:       ARMv7-A Exception handlers\n; *\n; * -----------------------------------------------------------------------------\n; */\n\nMODE_FIQ        EQU      0x11\nMODE_IRQ        EQU      0x12\nMODE_SVC        EQU      0x13\nMODE_ABT        EQU      0x17\nMODE_UND        EQU      0x1B\n\nCPSR_BIT_T      EQU      0x20\n\nK_STATE_RUNNING EQU      2                          ; osKernelState_t::osKernelRunning\nI_K_STATE_OFS   EQU      8                          ; osRtxInfo.kernel.state offset\nI_TICK_IRQN_OFS EQU      16                         ; osRtxInfo.tick_irqn offset\nI_T_RUN_OFS     EQU      20                         ; osRtxInfo.thread.run offset\nTCB_SP_FRAME    EQU      34                         ; osRtxThread_t.stack_frame offset\nTCB_SP_OFS      EQU      56                         ; osRtxThread_t.sp offset\nTCB_ZONE_OFS    EQU      68                         ; osRtxThread_t.zone offset\n\n\n                PRESERVE8\n                ARM\n\n\n                AREA     |.constdata|, DATA, READONLY\n                EXPORT   irqRtxLib\nirqRtxLib       DCB      0                          ; Non weak library reference\n\n\n                AREA     |.data|, DATA, READWRITE\n                EXPORT   SVC_Active\n                EXPORT   IRQ_PendSV\nIRQ_NestLevel   DCD      0                          ; IRQ nesting level counter\nSVC_Active      DCB      0                          ; SVC Handler Active\nIRQ_PendSV      DCB      0                          ; Pending SVC flag\n\n\n                AREA     |.text|, CODE, READONLY\n\n\nUndef_Handler\\\n                PROC\n                EXPORT  Undef_Handler\n                IMPORT  CUndefHandler\n\n                SRSFD   SP!, #MODE_UND\n                PUSH    {R0-R4, R12}                ; Save APCS corruptible registers to UND mode stack\n\n                MRS     R0, SPSR\n                TST     R0, #CPSR_BIT_T             ; Check mode\n                MOVEQ   R1, #4                      ; R1 = 4 ARM mode\n                MOVNE   R1, #2                      ; R1 = 2 Thumb mode\n                SUB     R0, LR, R1\n                LDREQ   R0, [R0]                    ; ARM mode - R0 points to offending instruction\n                BEQ     Undef_Cont\n\n                ; Thumb instruction\n                ; Determine if it is a 32-bit Thumb instruction\n                LDRH    R0, [R0]\n                MOV     R2, #0x1C\n                CMP     R2, R0, LSR #11\n                BHS     Undef_Cont                  ; 16-bit Thumb instruction\n\n                ; 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction\n                LDRH    R2, [LR]\n                ORR     R0, R2, R0, LSL #16\nUndef_Cont\n                MOV     R2, LR                      ; Set LR to third argument\n\n                AND     R12, SP, #4                 ; Ensure stack is 8-byte aligned\n                SUB     SP, SP, R12                 ; Adjust stack\n                PUSH    {R12, LR}                   ; Store stack adjustment and dummy LR\n\n                ; R0 =Offending instruction, R1 =2(Thumb) or =4(ARM)\n                BL      CUndefHandler\n\n                POP     {R12, LR}                   ; Get stack adjustment & discard dummy LR\n                ADD     SP, SP, R12                 ; Unadjust stack\n\n                LDR     LR, [SP, #24]               ; Restore stacked LR and possibly adjust for retry\n                SUB     LR, LR, R0\n                LDR     R0, [SP, #28]               ; Restore stacked SPSR\n                MSR     SPSR_CXSF, R0\n                CLREX                               ; Clear exclusive monitor\n                POP     {R0-R4, R12}                ; Restore stacked APCS registers\n                ADD     SP, SP, #8                  ; Adjust SP for already-restored banked registers\n                MOVS    PC, LR\n\n                ENDP\n\n\nPAbt_Handler\\\n                PROC\n                EXPORT  PAbt_Handler\n                IMPORT  CPAbtHandler\n\n                SUB     LR, LR, #4                  ; Pre-adjust LR\n                SRSFD   SP!, #MODE_ABT              ; Save LR and SPRS to ABT mode stack\n                PUSH    {R0-R4, R12}                ; Save APCS corruptible registers to ABT mode stack\n                MRC     p15, 0, R0, c5, c0, 1       ; IFSR\n                MRC     p15, 0, R1, c6, c0, 2       ; IFAR\n\n                MOV     R2, LR                      ; Set LR to third argument\n\n                AND     R12, SP, #4                 ; Ensure stack is 8-byte aligned\n                SUB     SP, SP, R12                 ; Adjust stack\n                PUSH    {R12, LR}                   ; Store stack adjustment and dummy LR\n\n                BL      CPAbtHandler\n\n                POP     {R12, LR}                   ; Get stack adjustment & discard dummy LR\n                ADD     SP, SP, R12                 ; Unadjust stack\n\n                CLREX                               ; Clear exclusive monitor\n                POP     {R0-R4, R12}                ; Restore stack APCS registers\n                RFEFD   SP!                         ; Return from exception\n\n                ENDP\n\n\nDAbt_Handler\\\n                PROC\n                EXPORT  DAbt_Handler\n                IMPORT  CDAbtHandler\n\n                SUB     LR, LR, #8                  ; Pre-adjust LR\n                SRSFD   SP!, #MODE_ABT              ; Save LR and SPRS to ABT mode stack\n                PUSH    {R0-R4, R12}                ; Save APCS corruptible registers to ABT mode stack\n                MRC     p15, 0, R0, c5, c0, 0       ; DFSR\n                MRC     p15, 0, R1, c6, c0, 0       ; DFAR\n\n                MOV     R2, LR                      ; Set LR to third argument\n\n                AND     R12, SP, #4                 ; Ensure stack is 8-byte aligned\n                SUB     SP, SP, R12                 ; Adjust stack\n                PUSH    {R12, LR}                   ; Store stack adjustment and dummy LR\n\n                BL      CDAbtHandler\n\n                POP     {R12, LR}                   ; Get stack adjustment & discard dummy LR\n                ADD     SP, SP, R12                 ; Unadjust stack\n\n                CLREX                               ; Clear exclusive monitor\n                POP     {R0-R4, R12}                ; Restore stacked APCS registers\n                RFEFD   SP!                         ; Return from exception\n\n                ENDP\n\n\nIRQ_Handler\\\n                PROC\n                EXPORT  IRQ_Handler\n                IMPORT  IRQ_GetActiveIRQ\n                IMPORT  IRQ_GetHandler\n                IMPORT  IRQ_EndOfInterrupt\n\n                SUB     LR, LR, #4                  ; Pre-adjust LR\n                SRSFD   SP!, #MODE_SVC              ; Save LR_irq and SPSR_irq on to the SVC stack\n                CPS     #MODE_SVC                   ; Change to SVC mode\n                PUSH    {R0-R3, R12, LR}            ; Save APCS corruptible registers\n\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]\n                ADD     R1, R1, #1                  ; Increment IRQ nesting level\n                STR     R1, [R0]\n\n                MOV     R3, SP                      ; Move SP into R3\n                AND     R3, R3, #4                  ; Get stack adjustment to ensure 8-byte alignment\n                SUB     SP, SP, R3                  ; Adjust stack\n                PUSH    {R3, R4}                    ; Store stack adjustment(R3) and user data(R4)\n\n                BLX     IRQ_GetActiveIRQ            ; Retrieve interrupt ID into R0\n                MOV     R4, R0                      ; Move interrupt ID to R4\n\n                BLX     IRQ_GetHandler              ; Retrieve interrupt handler address for current ID\n                CMP     R0, #0                      ; Check if handler address is 0\n                BEQ     IRQ_End                     ; If 0, end interrupt and return\n\n                CPSIE   i                           ; Re-enable interrupts\n                BLX     R0                          ; Call IRQ handler\n                CPSID   i                           ; Disable interrupts\n\nIRQ_End\n                MOV     R0, R4                      ; Move interrupt ID to R0\n                BLX     IRQ_EndOfInterrupt          ; Signal end of interrupt\n\n                POP     {R3, R4}                    ; Restore stack adjustment(R3) and user data(R4)\n                ADD     SP, SP, R3                  ; Unadjust stack\n\n                BL      osRtxContextSwitch          ; Continue in context switcher\n\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]\n                SUBS    R1, R1, #1                  ; Decrement IRQ nesting level\n                STR     R1, [R0]\n\n                CLREX                               ; Clear exclusive monitor for interrupted code\n                POP     {R0-R3, R12, LR}            ; Restore stacked APCS registers\n                RFEFD   SP!                         ; Return from IRQ handler\n\n                ENDP\n\n\nSVC_Handler\\\n                PROC\n                EXPORT  SVC_Handler\n                IMPORT  IRQ_Disable\n                IMPORT  IRQ_Enable\n                IMPORT  osRtxUserSVC\n                IMPORT  osRtxInfo\n\n                SRSFD   SP!, #MODE_SVC              ; Store SPSR_svc and LR_svc onto SVC stack\n                PUSH    {R12, LR}\n\n                MRS     R12, SPSR                   ; Load SPSR\n                TST     R12, #CPSR_BIT_T            ; Thumb bit set?\n                LDRHNE  R12, [LR,#-2]               ; Thumb: load halfword\n                BICNE   R12, R12, #0xFF00           ;        extract SVC number\n                LDREQ   R12, [LR,#-4]               ; ARM:   load word\n                BICEQ   R12, R12, #0xFF000000       ;        extract SVC number\n                CMP     R12, #0                     ; Compare SVC number\n                BNE     SVC_User                    ; Branch if User SVC\n\n                PUSH    {R0-R3}                     ; Push arguments to stack\n\n                LDR     R0, =SVC_Active\n                MOV     R1, #1\n                STRB    R1, [R0]                    ; Set SVC Handler Active\n\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]\n                ADD     R1, R1, #1                  ; Increment IRQ nesting level\n                STR     R1, [R0]\n\n                LDR     R0, =osRtxInfo\n                LDR     R1, [R0, #I_K_STATE_OFS]    ; Load RTX5 kernel state\n                CMP     R1, #K_STATE_RUNNING        ; Check osKernelRunning\n                BLT     SVC_FuncCall                ; Continue if kernel is not running\n                LDR     R0, [R0, #I_TICK_IRQN_OFS]  ; Load OS Tick irqn\n                BLX     IRQ_Disable                 ; Disable OS Tick interrupt\nSVC_FuncCall\n                LDM     SP, {R0-R3, R12}            ; Reload R0-R3 and R12 from stack\n\n                CPSIE   i                           ; Re-enable interrupts\n                BLX     R12                         ; Branch to SVC function\n                CPSID   i                           ; Disable interrupts\n\n                STR     R0, [SP]                    ; Store function return value\n\n                LDR     R0, =osRtxInfo\n                LDR     R1, [R0, #I_K_STATE_OFS]    ; Load RTX5 kernel state\n                CMP     R1, #K_STATE_RUNNING        ; Check osKernelRunning\n                BLT     SVC_ContextCheck            ; Continue if kernel is not running\n                LDR     R0, [R0, #I_TICK_IRQN_OFS]  ; Load OS Tick irqn\n                BLX     IRQ_Enable                  ; Enable OS Tick interrupt\n\nSVC_ContextCheck\n                BL      osRtxContextSwitch          ; Continue in context switcher\n\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]\n                SUB     R1, R1, #1                  ; Decrement IRQ nesting level\n                STR     R1, [R0]\n\n                LDR     R0, =SVC_Active\n                MOV     R1, #0\n                STRB    R1, [R0]                    ; Clear SVC Handler Active\n\n                CLREX                               ; Clear exclusive monitor\n                POP     {R0-R3, R12, LR}            ; Restore stacked APCS registers\n                RFEFD   SP!                         ; Return from exception\n\nSVC_User\n                PUSH    {R4, R5}\n                LDR     R5,=osRtxUserSVC            ; Load address of SVC table\n                LDR     R4,[R5]                     ; Load SVC maximum number\n                CMP     R12,R4                      ; Check SVC number range\n                BHI     SVC_Done                    ; Branch if out of range\n                LDR     R12,[R5,R12,LSL #2]         ; Load SVC Function Address\n                BLX     R12                         ; Call SVC Function\nSVC_Done\n                CLREX                               ; Clear exclusive monitor\n                POP     {R4, R5, R12, LR}\n                RFEFD   SP!                         ; Return from exception\n\n                ENDP\n\n\nosRtxContextSwitch\\\n                PROC\n                EXPORT  osRtxContextSwitch\n                IMPORT  osRtxPendSV_Handler\n                IMPORT  osRtxInfo\n            IF :DEF:RTX_EXECUTION_ZONE\n                IMPORT  osZoneSetup_Callback\n            ENDIF\n                IMPORT  IRQ_Disable\n                IMPORT  IRQ_Enable\n\n                PUSH    {LR}\n\n                ; Check interrupt nesting level\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]                    ; Load IRQ nest level\n                CMP     R1, #1\n                BNE     osRtxContextExit            ; Nesting interrupts, exit context switcher\n\n                LDR     R12, =osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.run\n                LDM     R12, {R0, R1}               ; Load osRtxInfo.thread.run: curr & next\n                LDR     R2, =IRQ_PendSV             ; Load address of IRQ_PendSV flag\n                LDRB    R3, [R2]                    ; Load PendSV flag\n\n                CMP     R0, R1                      ; Check if context switch is required\n                BNE     osRtxContextCheck           ; Not equal, check if context save required\n                CMP     R3, #1                      ; Compare IRQ_PendSV value\n                BNE     osRtxContextExit            ; No post processing (and no context switch requested)\n\nosRtxContextCheck\n                STR     R1, [R12]                   ; Store run.next as run.curr\n                ; R0 = curr, R1 = next, R2 = &IRQ_PendSV, R12 = &osRtxInfo.thread.run\n                PUSH    {R0-R2, R12}\n\n                CMP     R0, #0                      ; Is osRtxInfo.thread.run.curr == 0\n                BEQ     osRtxPostProcess            ; Current deleted, skip context save\n\nosRtxContextSave\n                MOV     LR, R0                      ; Move &osRtxInfo.thread.run.curr to LR\n                MOV     R0, SP                      ; Move SP_svc into R0\n                ADD     R0, R0, #20                 ; Adjust SP_svc to R0 of the basic frame\n                SUB     SP, SP, #4\n                STM     SP, {SP}^                   ; Save SP_usr to current stack\n                POP     {R1}                        ; Pop SP_usr into R1\n\n                SUB     R1, R1, #64                 ; Adjust SP_usr to R4 of the basic frame\n                STMIA   R1!, {R4-R11}               ; Save R4-R11 to user stack\n                LDMIA   R0!, {R4-R8}                ; Load stacked R0-R3,R12 into R4-R8\n                STMIA   R1!, {R4-R8}                ; Store them to user stack\n                STM     R1, {LR}^                   ; Store LR_usr directly\n                ADD     R1, R1, #4                  ; Adjust user sp to PC\n                LDMIB   R0!, {R5-R6}                ; Load stacked PC, CPSR\n                STMIA   R1!, {R5-R6}                ; Store them to user stack\n\n                SUB     R1, R1, #64                 ; Adjust SP_usr to stacked R4\n\n                ; Check if VFP state need to be saved\n                MRC     p15, 0, R2, c1, c0, 2       ; VFP/NEON access enabled? (CPACR)\n                AND     R2, R2, #0x00F00000\n                CMP     R2, #0x00F00000\n                BNE     osRtxContextSave1           ; Continue, no VFP\n\n                VMRS    R2, FPSCR\n                STMDB   R1!, {R2,R12}               ; Push FPSCR, maintain 8-byte alignment\n\n                VSTMDB  R1!, {D0-D15}               ; Save D0-D15\n              IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32\n                VSTMDB  R1!, {D16-D31}              ; Save D16-D31\n              ENDIF\n\n                LDRB    R2, [LR, #TCB_SP_FRAME]     ; Load osRtxInfo.thread.run.curr frame info\n              IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32\n                ORR     R2, R2, #4                  ; NEON state\n              ELSE\n                ORR     R2, R2, #2                  ; VFP state\n              ENDIF\n                STRB    R2, [LR, #TCB_SP_FRAME]     ; Store VFP/NEON state\n\nosRtxContextSave1\n                STR     R1, [LR, #TCB_SP_OFS]       ; Store user sp to osRtxInfo.thread.run.curr\n\nosRtxPostProcess\n                ; RTX IRQ post processing check\n                POP     {R8-R11}                    ; Pop R8 = curr, R9 = next, R10 = &IRQ_PendSV, R11 = &osRtxInfo.thread.run\n                LDRB    R0, [R10]                   ; Load PendSV flag\n                CMP     R0, #1                      ; Compare PendSV value\n                BNE     osRtxContextRestore         ; Skip post processing if not pending\n\n                MOV     R4, SP                      ; Move SP_svc into R4\n                AND     R4, R4, #4                  ; Get stack adjustment to ensure 8-byte alignment\n                SUB     SP, SP, R4                  ; Adjust stack\n\n                ; Disable OS Tick\n                LDR     R5, =osRtxInfo              ; Load address of osRtxInfo\n                LDR     R5, [R5, #I_TICK_IRQN_OFS]  ; Load OS Tick irqn\n                MOV     R0, R5                      ; Set it as function parameter\n                BLX     IRQ_Disable                 ; Disable OS Tick interrupt\n                MOV     R6, #0                      ; Set PendSV clear value\n                B       osRtxPendCheck\nosRtxPendExec\n                STRB    R6, [R10]                   ; Clear PendSV flag\n                CPSIE   i                           ; Re-enable interrupts\n                BLX     osRtxPendSV_Handler         ; Post process pending objects\n                CPSID   i                           ; Disable interrupts\nosRtxPendCheck\n                LDR     R9, [R11, #4]               ; Load osRtxInfo.thread.run.next\n                STR     R9, [R11]                   ; Store run.next as run.curr\n                LDRB    R0, [R10]                   ; Load PendSV flag\n                CMP     R0, #1                      ; Compare PendSV value\n                BEQ     osRtxPendExec               ; Branch to PendExec if PendSV is set\n\n                ; Re-enable OS Tick\n                MOV     R0, R5                      ; Restore irqn as function parameter\n                BLX     IRQ_Enable                  ; Enable OS Tick interrupt\n\n                ADD     SP, SP, R4                  ; Restore stack adjustment\n\nosRtxContextRestore\n            IF :DEF:RTX_EXECUTION_ZONE\n                LDRB    R0, [R9, #TCB_ZONE_OFS]     ; Load osRtxInfo.thread.run.next: zone\n                CMP     R8, #0\n                BEQ     osRtxZoneSetup              ; Branch if running thread is deleted\n                LDRB    R1, [R8, #TCB_ZONE_OFS]     ; Load osRtxInfo.thread.run.curr: zone\n                CMP     R0, R1                      ; Check if next:zone == curr:zone\n                BEQ     osRtxContextRestoreFrame    ; Branch if zone has not changed\nosRtxZoneSetup\n                BL      osZoneSetup_Callback        ; Setup zone for next thread\n            ENDIF\n\nosRtxContextRestoreFrame\n                LDR     LR, [R8, #TCB_SP_OFS]       ; Load next osRtxThread_t.sp\n                LDRB    R2, [R8, #TCB_SP_FRAME]     ; Load next osRtxThread_t.stack_frame\n\n                ANDS    R2, R2, #0x6                ; Check stack frame for VFP context\n                MRC     p15, 0, R2, c1, c0, 2       ; Read CPACR\n                ANDEQ   R2, R2, #0xFF0FFFFF         ; VFP/NEON state not stacked, disable VFP/NEON\n                ORRNE   R2, R2, #0x00F00000         ; VFP/NEON state is stacked, enable VFP/NEON\n                MCR     p15, 0, R2, c1, c0, 2       ; Write CPACR\n                BEQ     osRtxContextRestore1        ; No VFP\n                ISB                                 ; Sync if VFP was enabled\n              IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32\n                VLDMIA  LR!, {D16-D31}              ; Restore D16-D31\n              ENDIF\n                VLDMIA  LR!, {D0-D15}               ; Restore D0-D15\n                LDR     R2, [LR]\n                VMSR    FPSCR, R2                   ; Restore FPSCR\n                ADD     LR, LR, #8                  ; Adjust sp pointer to R4\n\nosRtxContextRestore1\n                LDMIA   LR!, {R4-R11}               ; Restore R4-R11\n                ADD     R12, LR, #32                ; Adjust sp and save it into R12\n                PUSH    {R12}                       ; Push sp onto stack\n                LDM     SP, {SP}^                   ; Restore SP_usr directly\n                ADD     SP, SP, #4                  ; Adjust SP_svc\n                LDMIA   LR!, {R0-R3, R12}           ; Load user registers R0-R3,R12\n                STMIB   SP!, {R0-R3, R12}           ; Store them to SP_svc\n                LDM     LR, {LR}^                   ; Restore LR_usr directly\n                LDMIB   LR!, {R0-R1}                ; Load user registers PC,CPSR\n                ADD     SP, SP, #4\n                STMIB   SP!, {R0-R1}                ; Store them to SP_svc\n                SUB     SP, SP, #32                 ; Adjust SP_svc to stacked LR\n\nosRtxContextExit\n                POP     {PC}                        ; Return\n\n                ENDP\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s",
    "content": ";/*\n; * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; * -----------------------------------------------------------------------------\n; *\n; * Project:     CMSIS-RTOS RTX\n; * Title:       ARMv7-M Exception handlers\n; *\n; * -----------------------------------------------------------------------------\n; */\n\n\n                IF       ({FPU}=\"FPv4-SP\") || ({FPU}=\"VFPv4_D16\") || ({FPU}=\"VFPv4_SP_D16\") || ({FPU}=\"FPv5-SP\") || ({FPU}=\"FPv5_D16\")\nFPU_USED        EQU      1\n                ELSE\nFPU_USED        EQU      0\n                ENDIF\n\nI_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset\nTCB_SP_OFS      EQU      56                     ; TCB.SP offset\nTCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset\nTCB_ZONE_OFS    EQU      68                     ; TCB.zone offset\n\nFPCCR           EQU      0xE000EF34             ; FPCCR Address\n\nosRtxErrorStackOverflow\\\n                EQU      1                      ; Stack overflow\nosRtxErrorSVC   EQU      6                      ; Invalid SVC function called\n\n\n                PRESERVE8\n                THUMB\n\n\n                AREA     |.constdata|, DATA, READONLY\n                EXPORT   irqRtxLib\nirqRtxLib       DCB      0                      ; Non weak library reference\n\n\n                AREA     |.text|, CODE, READONLY\n\n\nSVC_Handler     PROC\n                EXPORT   SVC_Handler\n                IMPORT   osRtxUserSVC\n                IMPORT   osRtxInfo\n            IF :DEF:RTX_STACK_CHECK\n                IMPORT   osRtxThreadStackCheck\n                IMPORT   osRtxKernelErrorNotify\n            ENDIF\n            IF :DEF:RTX_SVC_PTR_CHECK\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Base|\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Length|\n                IMPORT   osRtxKernelErrorNotify\n            ENDIF\n            IF :DEF:RTX_EXECUTION_ZONE\n                IMPORT   osZoneSetup_Callback\n            ENDIF\n\n                TST      LR,#0x04               ; Determine return stack from EXC_RETURN bit 2\n                ITE      EQ\n                MRSEQ    R0,MSP                 ; Get MSP if return stack is MSP\n                MRSNE    R0,PSP                 ; Get PSP if return stack is PSP\n\n                LDR      R1,[R0,#24]            ; Load saved PC from stack\n                LDRB     R1,[R1,#-2]            ; Load SVC number\n                CMP      R1,#0                  ; Check SVC number\n                BNE      SVC_User               ; Branch if not SVC 0\n\n            IF :DEF:RTX_SVC_PTR_CHECK\n\n                LDR      R12,[R0,#16]           ; Load function address from stack\n                SUB      R1,R12,#1              ; Clear T-bit of function address\n                LSLS     R2,R1,#30              ; Check if 4-byte aligned\n                BEQ      SVC_PtrBoundsCheck     ; Branch if address is aligned\n\nSVC_PtrInvalid\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                MOVS     R0,#osRtxErrorSVC      ; Parameter: code\n                MOV      R1,R12                 ; Parameter: object_id\n                BL       osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify\n                POP      {R12,LR}               ; Restore SP and EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\nSVC_PtrBoundsCheck\n                LDR      R2,=|Image$$RTX_SVC_VENEERS$$Base|\n                LDR      R3,=|Image$$RTX_SVC_VENEERS$$Length|\n                SUBS     R2,R1,R2               ; Subtract SVC table base address\n                CMP      R2,R3                  ; Compare with SVC table boundaries\n                BHS      SVC_PtrInvalid         ; Branch if address is out of bounds\n\n            ENDIF\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack\n                BLX      R12                    ; Call service function\n                POP      {R12,LR}               ; Restore SP and EXC_RETURN\n                STR      R0,[R12]               ; Store function return value\n\nSVC_Context\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run\n                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next\n                CMP      R1,R2                  ; Check if thread switch is required\n                IT       EQ\n                BXEQ     LR                     ; Exit when threads are the same\n\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n\n              IF FPU_USED != 0\n                CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted\nSVC_FP_LazyState\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                BNE      SVC_ContextRestore     ; Branch if not extended stack frame\n                LDR      R3,=FPCCR              ; FPCCR Address\n                LDR      R0,[R3]                ; Load FPCCR\n                BIC      R0,R0,#1               ; Clear LSPACT (Lazy state preservation)\n                STR      R0,[R3]                ; Store FPCCR\n                B        SVC_ContextRestore     ; Branch to context restore handling\n              ELSE\n                CBZ      R1,SVC_ContextRestore  ; Branch if running thread is deleted\n              ENDIF\n\nSVC_ContextSave\n            IF :DEF:RTX_STACK_CHECK\n                SUB      R12,R12,#32            ; Calculate SP: space for R4..R11\n              IF FPU_USED != 0\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                SUBEQ    R12,R12,#64            ;  Additional space for S16..S31\n                STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information\n              ENDIF\n                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP\n\n                PUSH     {R1,R2}                ; Save osRtxInfo.thread.run: curr & next\n                MOV      R0,R1                  ; Parameter: osRtxInfo.thread.run.curr\n                BL       osRtxThreadStackCheck  ; Check if thread stack is overrun\n                POP      {R1,R2}                ; Restore osRtxInfo.thread.run: curr & next\n                CBNZ     R0,SVC_ContextSaveRegs ; Branch when stack check is ok\n\n              IF FPU_USED != 0\n                MOV      R4,R1                  ; Assign osRtxInfo.thread.run.curr to R4\n              ENDIF\n                MOVS     R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id\n                BL       osRtxKernelErrorNotify      ; Call osRtxKernelErrorNotify\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS   ; Load address of osRtxInfo.thread.run\n                LDR      R2,[R3,#4]             ; Load osRtxInfo.thread.run: next\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n                MOVS     R1,#0                  ; Simulate deleted running thread\n              IF FPU_USED != 0\n                LDRSB    LR,[R4,#TCB_SF_OFS]    ; Load stack frame information\n                B        SVC_FP_LazyState       ; Branch to FP lazy state handling\n              ELSE\n                B        SVC_ContextRestore     ; Branch to context restore handling\n              ENDIF\n\nSVC_ContextSaveRegs\n                LDR      R12,[R1,#TCB_SP_OFS]   ; Load SP\n              IF FPU_USED != 0\n                LDRSB    LR, [R1,#TCB_SF_OFS]   ; Load stack frame information\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                VSTMIAEQ R12!,{S16-S31}         ;  Save VFP S16..S31\n              ENDIF\n                STM      R12,{R4-R11}           ; Save R4..R11\n            ELSE\n                STMDB    R12!,{R4-R11}          ; Save R4..R11\n              IF FPU_USED != 0\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                VSTMDBEQ R12!,{S16-S31}         ;  Save VFP S16.S31\n                STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information\n              ENDIF\n                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP\n            ENDIF\n\nSVC_ContextRestore\n                 MOVS     R4,R2                 ; Assign osRtxInfo.thread.run.next to R4, clear Z flag\n            IF :DEF:RTX_EXECUTION_ZONE\n                 LDRB     R0,[R2,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.next: zone\n                 CBZ      R1,SVC_ZoneSetup      ; Branch if running thread is deleted (Z flag unchanged)\n                 LDRB     R1,[R1,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.curr: zone\n                 CMP      R0,R1                 ; Check if next:zone == curr:zone\n\nSVC_ZoneSetup\n                 IT       NE                    ; If zone has changed or running thread is deleted\n                 BLNE     osZoneSetup_Callback  ;  Setup zone for next thread\n            ENDIF\n\n                LDR      R0,[R4,#TCB_SP_OFS]    ; Load SP\n              IF FPU_USED != 0\n                LDRSB    LR,[R4,#TCB_SF_OFS]    ; Load stack frame information\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31\n              ELSE\n                MVN      LR,#~0xFFFFFFFD        ; Set EXC_RETURN value\n              ENDIF\n                LDMIA    R0!,{R4-R11}           ; Restore R4..R11\n                MSR      PSP,R0                 ; Set PSP\n\nSVC_Exit\n                BX       LR                     ; Exit from handler\n\nSVC_User\n                LDR      R2,=osRtxUserSVC       ; Load address of SVC table\n                LDR      R3,[R2]                ; Load SVC maximum number\n                CMP      R1,R3                  ; Check SVC number range\n                BHI      SVC_Exit               ; Branch if out of range\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LDR      R12,[R2,R1,LSL #2]     ; Load address of SVC function\n                LDM      R0,{R0-R3}             ; Load function parameters from stack\n                BLX      R12                    ; Call service function\n                POP      {R12,LR}               ; Restore SP and EXC_RETURN\n                STR      R0,[R12]               ; Store function return value\n\n                BX       LR                     ; Return from handler\n\n                ALIGN\n                ENDP\n\n\nPendSV_Handler  PROC\n                EXPORT   PendSV_Handler\n                IMPORT   osRtxPendSV_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler\n                POP      {R0,LR}                ; Restore EXC_RETURN\n                MRS      R12,PSP                ; Save PSP to R12\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n\nSysTick_Handler PROC\n                EXPORT   SysTick_Handler\n                IMPORT   osRtxTick_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxTick_Handler      ; Call osRtxTick_Handler\n                POP      {R0,LR}                ; Restore EXC_RETURN\n                MRS      R12,PSP                ; Save PSP to R12\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n\n            IF :DEF:RTX_SAFETY_FEATURES\n\nosFaultResume   PROC\n                EXPORT   osFaultResume\n\n                MRS      R12,PSP                ; Save PSP to R12\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n            ENDIF\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       ARMv6-M Exception handlers\n *\n * -----------------------------------------------------------------------------\n */\n\n\n        .syntax  unified\n\n        #include \"rtx_def.h\"\n\n        .equ     I_T_RUN_OFS,       20  // osRtxInfo.thread.run offset\n        .equ     TCB_SP_OFS,        56  // TCB.SP offset\n        .equ     TCB_ZONE_OFS,      68  // TCB.zone offset\n\n        .equ     osRtxErrorStackOverflow, 1 // Stack overflow\n        .equ     osRtxErrorSVC,           6 // Invalid SVC function called\n\n        .section \".rodata\"\n        .global  irqRtxLib              // Non weak library reference\nirqRtxLib:\n        .byte    0\n\n\n        .thumb\n        .section \".text\"\n        .align   2\n        .eabi_attribute Tag_ABI_align_preserved, 1\n\n\n        .thumb_func\n        .type    SVC_Handler, %function\n        .global  SVC_Handler\n        .fnstart\n        .cantunwind\nSVC_Handler:\n\n        mov      r0,lr\n        lsrs     r0,r0,#3               // Determine return stack from EXC_RETURN bit 2\n        bcc      SVC_MSP                // Branch if return stack is MSP\n        mrs      r0,psp                 // Get PSP\n\nSVC_Number:\n        ldr      r1,[r0,#24]            // Load saved PC from stack\n        subs     r1,r1,#2               // Point to SVC instruction\n        ldrb     r1,[r1]                // Load SVC number\n        cmp      r1,#0                  // Check SVC number\n        bne      SVC_User               // Branch if not SVC 0\n\n    #ifdef RTX_SVC_PTR_CHECK\n\n        subs     r1,r7,#0x01            // Clear T-bit of function address\n        lsls     r2,r1,#29              // Check if 8-byte aligned\n        beq      SVC_PtrBoundsCheck     // Branch if address is aligned\n\nSVC_PtrInvalid:\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        movs     r0,#osRtxErrorSVC      // Parameter: code\n        mov      r1,r7                  // Parameter: object_id\n        bl       osRtxKernelErrorNotify // Call osRtxKernelErrorNotify\n        pop      {r2,r3}                // Restore SP and EXC_RETURN\n        mov      lr,r3                  // Set EXC_RETURN\n        b        SVC_Context            // Branch to context handling\n\nSVC_PtrBoundsCheck:\n        ldr      r2,=Image$$RTX_SVC_VENEERS$$Base\n        ldr      r3,=Image$$RTX_SVC_VENEERS$$Length\n        subs     r2,r1,r2               // Subtract SVC table base address\n        cmp      r2,r3                  // Compare with SVC table boundaries\n        bhs      SVC_PtrInvalid         // Branch if address is out of bounds\n\n    #endif // RTX_SVC_PTR_CHECK\n\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        ldmia    r0,{r0-r3}             // Load function parameters from stack\n        blx      r7                     // Call service function\n        pop      {r2,r3}                // Restore SP and EXC_RETURN\n        str      r0,[r2]                // Store function return value\n        mov      lr,r3                  // Set EXC_RETURN\n\nSVC_Context:\n        ldr      r3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.thread.run\n        ldmia    r3!,{r1,r2}            // Load osRtxInfo.thread.run: curr & next\n        cmp      r1,r2                  // Check if thread switch is required\n        beq      SVC_Exit               // Branch when threads are the same\n\n        subs     r3,r3,#8               // Adjust address\n        str      r2,[r3]                // osRtxInfo.thread.run: curr = next\n        cmp      r1,#0\n        beq      SVC_ContextRestore     // Branch if running thread is deleted\n\nSVC_ContextSave:\n        mrs      r0,psp                 // Get PSP\n        subs     r0,r0,#32              // Calculate SP: space for R4..R11\n        str      r0,[r1,#TCB_SP_OFS]    // Store SP\n\n    #ifdef RTX_STACK_CHECK\n\n        push     {r1,r2}                // Save osRtxInfo.thread.run: curr & next\n        mov      r0,r1                  // Parameter: osRtxInfo.thread.run.curr\n        bl       osRtxThreadStackCheck  // Check if thread stack is overrun\n        pop      {r1,r2}                // Restore osRtxInfo.thread.run: curr & next\n        cmp      r0,#0\n        bne      SVC_ContextSaveRegs    // Branch when stack check is ok\n\n        movs     r0,#osRtxErrorStackOverflow // Parameter: r0=code, r1=object_id\n        bl       osRtxKernelErrorNotify      // Call osRtxKernelErrorNotify\n        ldr      r3,=osRtxInfo+I_T_RUN_OFS   // Load address of osRtxInfo.thread.run\n        ldr      r2,[r3,#4]             // Load osRtxInfo.thread.run: next\n        str      r2,[r3]                // osRtxInfo.thread.run: curr = next\n        movs     r1,#0                  // Simulate deleted running thread\n        b        SVC_ContextRestore     // Branch to context restore handling\n\nSVC_ContextSaveRegs:\n        ldr      r0,[r1,#TCB_SP_OFS]    // Load SP\n\n    #endif // RTX_STACK_CHECK\n\n        stmia    r0!,{r4-r7}            // Save R4..R7\n        mov      r4,r8\n        mov      r5,r9\n        mov      r6,r10\n        mov      r7,r11\n        stmia    r0!,{r4-r7}            // Save R8..R11\n\nSVC_ContextRestore:\n        movs     r4,r2                  // Assign osRtxInfo.thread.run.next to R4\n    #ifdef RTX_EXECUTION_ZONE\n        movs     r3,#TCB_ZONE_OFS       // Get TCB.zone offset\n        ldrb     r0,[r2,r3]             // Load osRtxInfo.thread.run.next: zone\n        cmp      r1,#0\n        beq      SVC_ZoneSetup          // Branch if running thread is deleted\n        ldrb     r1,[r1,r3]             // Load osRtxInfo.thread.run.curr: zone\n        cmp      r0,r1                  // Check if next:zone == curr:zone\n        beq      SVC_ContextRestore_N   // Branch if zone has not changed\n\nSVC_ZoneSetup:\n        bl       osZoneSetup_Callback   // Setup zone for next thread\n    #endif // RTX_EXECUTION_ZONE\n\nSVC_ContextRestore_N:\n        ldr      r0,[r4,#TCB_SP_OFS]    // Load SP\n        adds     r0,r0,#16              // Adjust address\n        ldmia    r0!,{r4-r7}            // Restore R8..R11\n        mov      r8,r4\n        mov      r9,r5\n        mov      r10,r6\n        mov      r11,r7\n        msr      psp,r0                 // Set PSP\n        subs     r0,r0,#32              // Adjust address\n        ldmia    r0!,{r4-r7}            // Restore R4..R7\n\n        movs     r0,#2                  // Binary complement of 0xFFFFFFFD\n        mvns     r0,r0                  // Set EXC_RETURN value\n        bx       r0                     // Exit from handler\n\nSVC_MSP:\n        mrs      r0,msp                 // Get MSP\n        b        SVC_Number\n\nSVC_Exit:\n        bx       lr                     // Exit from handler\n\nSVC_User:\n        ldr      r2,=osRtxUserSVC       // Load address of SVC table\n        ldr      r3,[r2]                // Load SVC maximum number\n        cmp      r1,r3                  // Check SVC number range\n        bhi      SVC_Exit               // Branch if out of range\n\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        lsls     r1,r1,#2\n        ldr      r3,[r2,r1]             // Load address of SVC function\n        mov      r12,r3\n        ldmia    r0,{r0-r3}             // Load function parameters from stack\n        blx      r12                    // Call service function\n        pop      {r2,r3}                // Restore SP and EXC_RETURN\n        str      r0,[r2]                // Store function return value\n\n        bx       r3                     // Return from handler\n\n        .fnend\n        .size    SVC_Handler, .-SVC_Handler\n\n\n        .thumb_func\n        .type    PendSV_Handler, %function\n        .global  PendSV_Handler\n        .fnstart\n        .cantunwind\nPendSV_Handler:\n\n        push     {r0,lr}                // Save EXC_RETURN\n        bl       osRtxPendSV_Handler    // Call osRtxPendSV_Handler\n        pop      {r0,r1}                // Restore EXC_RETURN\n        mov      lr,r1                  // Set EXC_RETURN\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size    PendSV_Handler, .-PendSV_Handler\n\n\n        .thumb_func\n        .type    SysTick_Handler, %function\n        .global  SysTick_Handler\n        .fnstart\n        .cantunwind\nSysTick_Handler:\n\n        push     {r0,lr}                // Save EXC_RETURN\n        bl       osRtxTick_Handler      // Call osRtxTick_Handler\n        pop      {r0,r1}                // Restore EXC_RETURN\n        mov      lr,r1                  // Set EXC_RETURN\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size    SysTick_Handler, .-SysTick_Handler\n\n\n    #ifdef RTX_SAFETY_FEATURES\n\n        .thumb_func\n        .type    osFaultResume, %function\n        .global  osFaultResume\n        .fnstart\n        .cantunwind\nosFaultResume:\n\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size   osFaultResume, .-osFaultResume\n\n    #endif // RTX_SAFETY_FEATURES\n\n\n        .end\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       ARMv7-A Exception handlers\n *\n * -----------------------------------------------------------------------------\n */\n\n\n                .syntax  unified\n\n                #include \"rtx_def.h\"\n\n                .equ   MODE_FIQ,        0x11\n                .equ   MODE_IRQ,        0x12\n                .equ   MODE_SVC,        0x13\n                .equ   MODE_ABT,        0x17\n                .equ   MODE_UND,        0x1B\n\n                .equ   CPSR_BIT_T,      0x20\n\n                .equ   K_STATE_RUNNING, 2           // osKernelState_t::osKernelRunning\n                .equ   I_K_STATE_OFS,   8           // osRtxInfo.kernel.state offset\n                .equ   I_TICK_IRQN_OFS, 16          // osRtxInfo.tick_irqn offset\n                .equ   I_T_RUN_OFS,     20          // osRtxInfo.thread.run offset\n                .equ   TCB_SP_FRAME,    34          // osRtxThread_t.stack_frame offset\n                .equ   TCB_SP_OFS,      56          // osRtxThread_t.sp offset\n                .equ   TCB_ZONE_OFS,    68          // osRtxThread_t.zone offset\n\n\n                .section \".rodata\"\n                .global  irqRtxLib                  // Non weak library reference\nirqRtxLib:\n                .byte    0\n\n                .section \".data\"\n                .global  SVC_Active\n                .global  IRQ_PendSV\nIRQ_NestLevel:\n                .word    0                          // IRQ nesting level counter\nSVC_Active:\n                .byte    0                          // SVC Handler Active\nIRQ_PendSV:\n                .byte    0                          // Pending SVC flag\n\n                .arm\n                .section \".text\"\n                .align   4\n\n\n                .type    Undef_Handler, %function\n                .global  Undef_Handler\n                .fnstart\n                .cantunwind\nUndef_Handler:\n\n                srsfd   sp!, #MODE_UND\n                push    {r0-r4, r12}                // Save APCS corruptible registers to UND mode stack\n\n                mrs     r0, spsr\n                tst     r0, #CPSR_BIT_T             // Check mode\n                moveq   r1, #4                      // R1 = 4 ARM mode\n                movne   r1, #2                      // R1 = 2 Thumb mode\n                sub     r0, lr, r1\n                ldreq   r0, [r0]                    // ARM mode - R0 points to offending instruction\n                beq     Undef_Cont\n\n                // Thumb instruction\n                // Determine if it is a 32-bit Thumb instruction\n                ldrh    r0, [r0]\n                mov     r2, #0x1C\n                cmp     r2, r0, lsr #11\n                bhs     Undef_Cont                  // 16-bit Thumb instruction\n\n                // 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction\n                ldrh    r2, [lr]\n                orr     r0, r2, r0, lsl #16\nUndef_Cont:\n                mov     r2, lr                      // Set LR to third argument\n\n                and     r12, sp, #4                 // Ensure stack is 8-byte aligned\n                sub     sp, sp, r12                 // Adjust stack\n                push    {r12, lr}                   // Store stack adjustment and dummy LR\n\n                // R0 =Offending instruction, R1 =2(Thumb) or =4(ARM)\n                bl      CUndefHandler\n\n                pop     {r12, lr}                   // Get stack adjustment & discard dummy LR\n                add     sp, sp, r12                 // Unadjust stack\n\n                ldr     lr, [sp, #24]               // Restore stacked LR and possibly adjust for retry\n                sub     lr, lr, r0\n                ldr     r0, [sp, #28]               // Restore stacked SPSR\n                msr     spsr_cxsf, r0\n                clrex                               // Clear exclusive monitor\n                pop     {r0-r4, r12}                // Restore stacked APCS registers\n                add     sp, sp, #8                  // Adjust SP for already-restored banked registers\n                movs    pc, lr\n\n                .fnend\n                .size    Undef_Handler, .-Undef_Handler\n\n\n                .type    PAbt_Handler, %function\n                .global  PAbt_Handler\n                .fnstart\n                .cantunwind\nPAbt_Handler:\n\n                sub     lr, lr, #4                  // Pre-adjust LR\n                srsfd   sp!, #MODE_ABT              // Save LR and SPRS to ABT mode stack\n                push    {r0-r4, r12}                // Save APCS corruptible registers to ABT mode stack\n                mrc     p15, 0, r0, c5, c0, 1       // IFSR\n                mrc     p15, 0, r1, c6, c0, 2       // IFAR\n\n                mov     r2, lr                      // Set LR to third argument\n\n                and     r12, sp, #4                 // Ensure stack is 8-byte aligned\n                sub     sp, sp, r12                 // Adjust stack\n                push    {r12, lr}                   // Store stack adjustment and dummy LR\n\n                bl      CPAbtHandler\n\n                pop     {r12, lr}                   // Get stack adjustment & discard dummy LR\n                add     sp, sp, r12                 // Unadjust stack\n\n                clrex                               // Clear exclusive monitor\n                pop     {r0-r4, r12}                // Restore stack APCS registers\n                rfefd   sp!                         // Return from exception\n\n                .fnend\n                .size    PAbt_Handler, .-PAbt_Handler\n\n\n                .type    DAbt_Handler, %function\n                .global  DAbt_Handler\n                .fnstart\n                .cantunwind\nDAbt_Handler:\n                sub     lr, lr, #8                  // Pre-adjust LR\n                srsfd   sp!, #MODE_ABT              // Save LR and SPRS to ABT mode stack\n                push    {r0-r4, r12}                // Save APCS corruptible registers to ABT mode stack\n                mrc     p15, 0, r0, c5, c0, 0       // DFSR\n                mrc     p15, 0, r1, c6, c0, 0       // DFAR\n\n                mov     r2, lr                      // Set LR to third argument\n\n                and     r12, sp, #4                 // Ensure stack is 8-byte aligned\n                sub     sp, sp, r12                 // Adjust stack\n                push    {r12, lr}                   // Store stack adjustment and dummy LR\n\n                bl      CDAbtHandler\n\n                pop     {r12, lr}                   // Get stack adjustment & discard dummy LR\n                add     sp, sp, r12                 // Unadjust stack\n\n                clrex                               // Clear exclusive monitor\n                pop     {r0-r4, r12}                // Restore stacked APCS registers\n                rfefd   sp!                         // Return from exception\n\n                .fnend\n                .size    DAbt_Handler, .-DAbt_Handler\n\n\n                .type    IRQ_Handler, %function\n                .global  IRQ_Handler\n                .fnstart\n                .cantunwind\nIRQ_Handler:\n\n                sub     lr, lr, #4                  // Pre-adjust LR\n                srsfd   sp!, #MODE_SVC              // Save LR_irq and SPSR_irq on to the SVC stack\n                cps     #MODE_SVC                   // Change to SVC mode\n                push    {r0-r3, r12, lr}            // Save APCS corruptible registers\n\n                ldr     r0, =IRQ_NestLevel\n                ldr     r1, [r0]\n                add     r1, r1, #1                  // Increment IRQ nesting level\n                str     r1, [r0]\n\n                mov     r3, sp                      // Move SP into R3\n                and     r3, r3, #4                  // Get stack adjustment to ensure 8-byte alignment\n                sub     sp, sp, r3                  // Adjust stack\n                push    {r3, r4}                    // Store stack adjustment(R3) and user data(R4)\n\n                blx     IRQ_GetActiveIRQ            // Retrieve interrupt ID into R0\n                mov     r4, r0                      // Move interrupt ID to R4\n\n                blx     IRQ_GetHandler              // Retrieve interrupt handler address for current ID\n                cmp     r0, #0                      // Check if handler address is 0\n                beq     IRQ_End                     // If 0, end interrupt and return\n\n                cpsie   i                           // Re-enable interrupts\n                blx     r0                          // Call IRQ handler\n                cpsid   i                           // Disable interrupts\n\nIRQ_End:\n                mov     r0, r4                      // Move interrupt ID to R0\n                blx     IRQ_EndOfInterrupt          // Signal end of interrupt\n\n                pop     {r3, r4}                    // Restore stack adjustment(R3) and user data(R4)\n                add     sp, sp, r3                  // Unadjust stack\n\n                bl      osRtxContextSwitch          // Continue in context switcher\n\n                ldr     r0, =IRQ_NestLevel\n                ldr     r1, [r0]\n                subs    r1, r1, #1                  // Decrement IRQ nesting level\n                str     r1, [r0]\n\n                clrex                               // Clear exclusive monitor for interrupted code\n                pop     {r0-r3, r12, lr}            // Restore stacked APCS registers\n                rfefd   sp!                         // Return from IRQ handler\n\n                .fnend\n                .size    IRQ_Handler, .-IRQ_Handler\n\n\n                .type    SVC_Handler, %function\n                .global  SVC_Handler\n                .fnstart\n                .cantunwind\nSVC_Handler:\n\n                srsfd   sp!, #MODE_SVC              // Store SPSR_svc and LR_svc onto SVC stack\n                push    {r12, lr}\n\n                mrs     r12, spsr                   // Load SPSR\n                tst     r12, #CPSR_BIT_T            // Thumb bit set?\n                ldrhne  r12, [lr,#-2]               // Thumb: load halfword\n                bicne   r12, r12, #0xFF00           //        extract SVC number\n                ldreq   r12, [lr,#-4]               // ARM:   load word\n                biceq   r12, r12, #0xFF000000       //        extract SVC number\n                cmp     r12, #0                     // Compare SVC number\n                bne     SVC_User                    // Branch if User SVC\n\n                push    {r0-r3}                     // Push arguments to stack\n\n                ldr     r0, =SVC_Active\n                mov     r1, #1\n                strb    r1, [r0]                    // Set SVC Handler Active\n\n                ldr     r0, =IRQ_NestLevel\n                ldr     r1, [r0]\n                add     r1, r1, #1                  // Increment IRQ nesting level\n                str     r1, [r0]\n\n                ldr     r0, =osRtxInfo\n                ldr     r1, [r0, #I_K_STATE_OFS]    // Load RTX5 kernel state\n                cmp     r1, #K_STATE_RUNNING        // Check osKernelRunning\n                blt     SVC_FuncCall                // Continue if kernel is not running\n                ldr     r0, [r0, #I_TICK_IRQN_OFS]  // Load OS Tick irqn\n                blx     IRQ_Disable                 // Disable OS Tick interrupt\nSVC_FuncCall:\n                ldm     sp, {r0-r3, r12}            // Reload R0-R3 and R12 from stack\n\n                cpsie   i                           // Re-enable interrupts\n                blx     r12                         // Branch to SVC function\n                cpsid   i                           // Disable interrupts\n\n                str     r0, [sp]                    // Store function return value\n\n                ldr     r0, =osRtxInfo\n                ldr     r1, [r0, #I_K_STATE_OFS]    // Load RTX5 kernel state\n                cmp     r1, #K_STATE_RUNNING        // Check osKernelRunning\n                blt     SVC_ContextCheck            // Continue if kernel is not running\n                ldr     r0, [r0, #I_TICK_IRQN_OFS]  // Load OS Tick irqn\n                blx     IRQ_Enable                  // Enable OS Tick interrupt\n\nSVC_ContextCheck:\n                bl      osRtxContextSwitch          // Continue in context switcher\n\n                ldr     r0, =IRQ_NestLevel\n                ldr     r1, [r0]\n                sub     r1, r1, #1                  // Decrement IRQ nesting level\n                str     r1, [r0]\n\n                ldr     r0, =SVC_Active\n                mov     r1, #0\n                strb    r1, [r0]                    // Clear SVC Handler Active\n\n                clrex                               // Clear exclusive monitor\n                pop     {r0-r3, r12, lr}            // Restore stacked APCS registers\n                rfefd   sp!                         // Return from exception\n\nSVC_User:\n                push    {r4, r5}\n                ldr     r5,=osRtxUserSVC            // Load address of SVC table\n                ldr     r4,[r5]                     // Load SVC maximum number\n                cmp     r12,r4                      // Check SVC number range\n                bhi     SVC_Done                    // Branch if out of range\n\n                ldr     r12,[r5,r12,lsl #2]         // Load SVC Function Address\n                blx     r12                         // Call SVC Function\n\nSVC_Done:\n                clrex                               // Clear exclusive monitor\n                pop     {r4, r5, r12, lr}\n                rfefd   sp!                         // Return from exception\n\n                .fnend\n                .size    SVC_Handler, .-SVC_Handler\n\n\n                .type    osRtxContextSwitch, %function\n                .global  osRtxContextSwitch\n                .fnstart\n                .cantunwind\nosRtxContextSwitch:\n\n                push    {lr}\n\n                // Check interrupt nesting level\n                ldr     r0, =IRQ_NestLevel\n                ldr     r1, [r0]                    // Load IRQ nest level\n                cmp     r1, #1\n                bne     osRtxContextExit            // Nesting interrupts, exit context switcher\n\n                ldr     r12, =osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run\n                ldm     r12, {r0, r1}               // Load osRtxInfo.thread.run: curr & next\n                ldr     r2, =IRQ_PendSV             // Load address of IRQ_PendSV flag\n                ldrb    r3, [r2]                    // Load PendSV flag\n\n                cmp     r0, r1                      // Check if context switch is required\n                bne     osRtxContextCheck           // Not equal, check if context save required\n                cmp     r3, #1                      // Compare IRQ_PendSV value\n                bne     osRtxContextExit            // No post processing (and no context switch requested)\n\nosRtxContextCheck:\n                str     r1, [r12]                   // Store run.next as run.curr\n                // R0 = curr, R1 = next, R2 = &IRQ_PendSV, R12 = &osRtxInfo.thread.run\n                push    {r0-r2, r12}\n\n                cmp     r0, #0                      // Is osRtxInfo.thread.run.curr == 0\n                beq     osRtxPostProcess            // Current deleted, skip context save\n\nosRtxContextSave:\n                mov     lr, r0                      // Move &osRtxInfo.thread.run.curr to LR\n                mov     r0, sp                      // Move SP_svc into R0\n                add     r0, r0, #20                 // Adjust SP_svc to R0 of the basic frame\n                sub     sp, sp, #4\n                stm     sp, {sp}^                   // Save SP_usr to current stack\n                pop     {r1}                        // Pop SP_usr into R1\n\n                sub     r1, r1, #64                 // Adjust SP_usr to R4 of the basic frame\n                stmia   r1!, {r4-r11}               // Save R4-R11 to user stack\n                ldmia   r0!, {r4-r8}                // Load stacked R0-R3,R12 into R4-R8\n                stmia   r1!, {r4-r8}                // Store them to user stack\n                stm     r1, {lr}^                   // Store LR_usr directly\n                add     r1, r1, #4                  // Adjust user sp to PC\n                ldmib   r0!, {r5-r6}                // Load stacked PC, CPSR\n                stmia   r1!, {r5-r6}                // Store them to user stack\n\n                sub     r1, r1, #64                 // Adjust SP_usr to stacked R4\n\n                // Check if VFP state need to be saved\n                mrc     p15, 0, r2, c1, c0, 2       // VFP/NEON access enabled? (CPACR)\n                and     r2, r2, #0x00F00000\n                cmp     r2, #0x00F00000\n                bne     osRtxContextSaveSP          // Continue, no VFP\n\n                vmrs    r2, fpscr\n                stmdb   r1!, {r2,r12}               // Push FPSCR, maintain 8-byte alignment\n\n                vstmdb  r1!, {d0-d15}               // Save D0-D15\n              #if defined(__ARM_NEON) && (__ARM_NEON == 1)\n                vstmdb  r1!, {d16-d31}              // Save D16-D31\n              #endif\n\n                ldrb    r2, [lr, #TCB_SP_FRAME]     // Load osRtxInfo.thread.run.curr frame info\n              #if defined(__ARM_NEON) && (__ARM_NEON == 1)\n                orr     r2, r2, #4                  // NEON state\n              #else\n                orr     r2, r2, #2                  // VFP state\n              #endif\n                strb    r2, [lr, #TCB_SP_FRAME]     // Store VFP/NEON state\n\nosRtxContextSaveSP:\n                str     r1, [lr, #TCB_SP_OFS]       // Store user sp to osRtxInfo.thread.run.curr\n\nosRtxPostProcess:\n                // RTX IRQ post processing check\n                pop     {r8-r11}                    // Pop R8 = curr, R9 = next, R10 = &IRQ_PendSV, R11 = &osRtxInfo.thread.run\n                ldrb    r0, [r10]                   // Load PendSV flag\n                cmp     r0, #1                      // Compare PendSV value\n                bne     osRtxContextRestore         // Skip post processing if not pending\n\n                mov     r4, sp                      // Move SP_svc into R4\n                and     r4, r4, #4                  // Get stack adjustment to ensure 8-byte alignment\n                sub     sp, sp, r4                  // Adjust stack\n\n                // Disable OS Tick\n                ldr     r5, =osRtxInfo              // Load address of osRtxInfo\n                ldr     r5, [r5, #I_TICK_IRQN_OFS]  // Load OS Tick irqn\n                mov     r0, r5                      // Set it as function parameter\n                blx     IRQ_Disable                 // Disable OS Tick interrupt\n                mov     r6, #0                      // Set PendSV clear value\n                b       osRtxPendCheck\nosRtxPendExec:\n                strb    r6, [r10]                   // Clear PendSV flag\n                cpsie   i                           // Re-enable interrupts\n                blx     osRtxPendSV_Handler         // Post process pending objects\n                cpsid   i                           // Disable interrupts\nosRtxPendCheck:\n                ldr     r9, [r11, #4]               // Load osRtxInfo.thread.run.next\n                str     r9, [r11]                   // Store run.next as run.curr\n                ldrb    r0, [r10]                   // Load PendSV flag\n                cmp     r0, #1                      // Compare PendSV value\n                beq     osRtxPendExec               // Branch to PendExec if PendSV is set\n\n                // Re-enable OS Tick\n                mov     r0, r5                      // Restore irqn as function parameter\n                blx     IRQ_Enable                  // Enable OS Tick interrupt\n\n                add     sp, sp, r4                  // Restore stack adjustment\n\nosRtxContextRestore:\n            #ifdef RTX_EXECUTION_ZONE\n                ldrb    r0, [r9, #TCB_ZONE_OFS]     // Load osRtxInfo.thread.run.next: zone\n                cmp     r8, #0\n                beq     osRtxZoneSetup              // Branch if running thread is deleted\n                ldrb    r1, [r8, #TCB_ZONE_OFS]     // Load osRtxInfo.thread.run.curr: zone\n                cmp     r0, r1                      // Check if next:zone == curr:zone\n                beq     osRtxContextRestoreFrame    // Branch if zone has not changed\nosRtxZoneSetup:\n                bl      osZoneSetup_Callback        // Setup zone for next thread\n            #endif\n\nosRtxContextRestoreFrame:\n                ldr     lr, [r9, #TCB_SP_OFS]       // Load next osRtxThread_t.sp\n                ldrb    r2, [r9, #TCB_SP_FRAME]     // Load next osRtxThread_t.stack_frame\n\n                ands    r2, r2, #0x6                // Check stack frame for VFP context\n                mrc     p15, 0, r2, c1, c0, 2       // Read CPACR\n                andeq   r2, r2, #0xFF0FFFFF         // VFP/NEON state not stacked, disable VFP/NEON\n                orrne   r2, r2, #0x00F00000         // VFP/NEON state is stacked, enable VFP/NEON\n                mcr     p15, 0, r2, c1, c0, 2       // Write CPACR\n                beq     osRtxContextRestoreRegs     // No VFP\n                isb                                 // Sync if VFP was enabled\n              #if defined(__ARM_NEON) && (__ARM_NEON == 1)\n                vldmia  lr!, {d16-d31}              // Restore D16-D31\n              #endif\n                vldmia  lr!, {d0-d15}               // Restore D0-D15\n                ldr     r2, [lr]\n                vmsr    fpscr, r2                   // Restore FPSCR\n                add     lr, lr, #8                  // Adjust sp pointer to R4\n\nosRtxContextRestoreRegs:\n                ldmia   lr!, {r4-r11}               // Restore R4-R11\n                add     r12, lr, #32                // Adjust sp and save it into R12\n                push    {r12}                       // Push sp onto stack\n                ldm     sp, {sp}^                   // Restore SP_usr directly\n                add     sp, sp, #4                  // Adjust SP_svc\n                ldmia   lr!, {r0-r3, r12}           // Load user registers R0-R3,R12\n                stmib   sp!, {r0-r3, r12}           // Store them to SP_svc\n                ldm     lr, {lr}^                   // Restore LR_usr directly\n                ldmib   lr!, {r0-r1}                // Load user registers PC,CPSR\n                add     sp, sp, #4\n                stmib   sp!, {r0-r1}                // Store them to SP_svc\n                sub     sp, sp, #32                 // Adjust SP_svc to stacked LR\n\nosRtxContextExit:\n                pop     {pc}                        // Return\n\n                .fnend\n                .size    osRtxContextSwitch, .-osRtxContextSwitch\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       ARMv7-M Exception handlers\n *\n * -----------------------------------------------------------------------------\n */\n\n\n        .syntax  unified\n\n        #include \"rtx_def.h\"\n\n        #if (defined(__ARM_FP) && (__ARM_FP > 0))\n        .equ     FPU_USED, 1\n        #else\n        .equ     FPU_USED, 0\n        #endif\n\n        .equ     I_T_RUN_OFS,       20  // osRtxInfo.thread.run offset\n        .equ     TCB_SP_OFS,        56  // TCB.SP offset\n        .equ     TCB_SF_OFS,        34  // TCB.stack_frame offset\n        .equ     TCB_ZONE_OFS,      68  // TCB.zone offset\n\n        .equ     FPCCR,     0xE000EF34  // FPCCR Address\n\n        .equ     osRtxErrorStackOverflow, 1 // Stack overflow\n        .equ     osRtxErrorSVC,           6 // Invalid SVC function called\n\n        .section \".rodata\"\n        .global  irqRtxLib              // Non weak library reference\nirqRtxLib:\n        .byte    0\n\n\n        .thumb\n        .section \".text\"\n        .align   2\n        .eabi_attribute Tag_ABI_align_preserved, 1\n\n\n        .thumb_func\n        .type    SVC_Handler, %function\n        .global  SVC_Handler\n        .fnstart\n        .cantunwind\nSVC_Handler:\n\n        tst      lr,#0x04               // Determine return stack from EXC_RETURN bit 2\n        ite      eq\n        mrseq    r0,msp                 // Get MSP if return stack is MSP\n        mrsne    r0,psp                 // Get PSP if return stack is PSP\n\n        ldr      r1,[r0,#24]            // Load saved PC from stack\n        ldrb     r1,[r1,#-2]            // Load SVC number\n        cmp      r1,#0                  // Check SVC number\n        bne      SVC_User               // Branch if not SVC 0\n\n    #ifdef RTX_SVC_PTR_CHECK\n\n        ldr      r12,[r0,#16]           // Load function address from stack\n        sub      r1,r12,#1              // Clear T-bit of function address\n        lsls     r2,r1,#30              // Check if 4-byte aligned\n        beq      SVC_PtrBoundsCheck     // Branch if address is aligned\n\nSVC_PtrInvalid:\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        movs     r0,#osRtxErrorSVC      // Parameter: code\n        mov      r1,r12                 // Parameter: object_id\n        bl       osRtxKernelErrorNotify // Call osRtxKernelErrorNotify\n        pop      {r12,lr}               // Restore SP and EXC_RETURN\n        b        SVC_Context            // Branch to context handling\n\nSVC_PtrBoundsCheck:\n        ldr      r2,=Image$$RTX_SVC_VENEERS$$Base\n        ldr      r3,=Image$$RTX_SVC_VENEERS$$Length\n        subs     r2,r1,r2               // Subtract SVC table base address\n        cmp      r2,r3                  // Compare with SVC table boundaries\n        bhs      SVC_PtrInvalid         // Branch if address is out of bounds\n\n    #endif // RTX_SVC_PTR_CHECK\n\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        ldm      r0,{r0-r3,r12}         // Load function parameters and address from stack\n        blx      r12                    // Call service function\n        pop      {r12,lr}               // Restore SP and EXC_RETURN\n        str      r0,[r12]               // Store function return value\n\nSVC_Context:\n        ldr      r3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.thread.run\n        ldm      r3,{r1,r2}             // Load osRtxInfo.thread.run: curr & next\n        cmp      r1,r2                  // Check if thread switch is required\n        it       eq\n        bxeq     lr                     // Exit when threads are the same\n\n        str      r2,[r3]                // osRtxInfo.thread.run: curr = next\n\n      .if (FPU_USED != 0)\n        cbnz     r1,SVC_ContextSave     // Branch if running thread is not deleted\nSVC_FP_LazyState:\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        bne      SVC_ContextRestore     // Branch if not extended stack frame\n        ldr      r3,=FPCCR              // FPCCR Address\n        ldr      r0,[r3]                // Load FPCCR\n        bic      r0,r0,#1               // Clear LSPACT (Lazy state preservation)\n        str      r0,[r3]                // Store FPCCR\n        b        SVC_ContextRestore     // Branch to context restore handling\n      .else\n        cbz      r1,SVC_ContextRestore  // Branch if running thread is deleted\n      .endif\n\nSVC_ContextSave:\n    #ifdef RTX_STACK_CHECK\n        sub      r12,r12,#32            // Calculate SP: space for R4..R11\n      .if (FPU_USED != 0)\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        it       eq                     // If extended stack frame\n        subeq    r12,r12,#64            //  Additional space for S16..S31\n        strb     lr, [r1,#TCB_SF_OFS]   // Store stack frame information\n      .endif\n        str      r12,[r1,#TCB_SP_OFS]   // Store SP\n\n        push     {r1,r2}                // Save osRtxInfo.thread.run: curr & next\n        mov      r0,r1                  // Parameter: osRtxInfo.thread.run.curr\n        bl       osRtxThreadStackCheck  // Check if thread stack is overrun\n        pop      {r1,r2}                // Restore osRtxInfo.thread.run: curr & next\n        cbnz     r0,SVC_ContextSaveRegs // Branch when stack check is ok\n\n      .if (FPU_USED != 0)\n        mov      r4,r1                  // Assign osRtxInfo.thread.run.curr to R4\n      .endif\n        movs     r0,#osRtxErrorStackOverflow // Parameter: r0=code, r1=object_id\n        bl       osRtxKernelErrorNotify      // Call osRtxKernelErrorNotify\n        ldr      r3,=osRtxInfo+I_T_RUN_OFS   // Load address of osRtxInfo.thread.run\n        ldr      r2,[r3,#4]             // Load osRtxInfo.thread.run: next\n        str      r2,[r3]                // osRtxInfo.thread.run: curr = next\n        movs     r1,#0                  // Simulate deleted running thread\n      .if (FPU_USED != 0)\n        ldrsb    lr,[r4,#TCB_SF_OFS]    // Load stack frame information\n        b        SVC_FP_LazyState       // Branch to FP lazy state handling\n      .else\n        b        SVC_ContextRestore     // Branch to context restore handling\n      .endif\n\nSVC_ContextSaveRegs:\n        ldr      r12,[r1,#TCB_SP_OFS]   // Load SP\n      .if (FPU_USED != 0)\n        ldrsb    lr, [r1,#TCB_SF_OFS]   // Load stack frame information\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        it       eq                     // If extended stack frame\n        vstmiaeq r12!,{s16-s31}         //  Save VFP S16..S31\n      .endif\n        stm      r12,{r4-r11}           // Save R4..R11\n    #else\n        stmdb    r12!,{r4-r11}          // Save R4..R11\n      .if (FPU_USED != 0)\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        it       eq                     // If extended stack frame\n        vstmdbeq r12!,{s16-s31}         //  Save VFP S16.S31\n        strb     lr, [r1,#TCB_SF_OFS]   // Store stack frame information\n      .endif\n        str      r12,[r1,#TCB_SP_OFS]   // Store SP\n    #endif // RTX_STACK_CHECK\n\nSVC_ContextRestore:\n        movs     r4,r2                  // Assign osRtxInfo.thread.run.next to R4, clear Z flag\n    #ifdef RTX_EXECUTION_ZONE\n        ldrb     r0,[r2,#TCB_ZONE_OFS]  // Load osRtxInfo.thread.run.next: zone\n        cbz      r1,SVC_ZoneSetup       // Branch if running thread is deleted (Z flag unchanged)\n        ldrb     r1,[r1,#TCB_ZONE_OFS]  // Load osRtxInfo.thread.run.curr: zone\n        cmp      r0,r1                  // Check if next:zone == curr:zone\n\nSVC_ZoneSetup:\n        it       ne                     // If zone has changed or running thread is deleted\n        blne     osZoneSetup_Callback   //  Setup zone for next thread\n    #endif // RTX_EXECUTION_ZONE\n\n        ldr      r0,[r4,#TCB_SP_OFS]    // Load SP\n      .if (FPU_USED != 0)\n        ldrsb    lr,[r4,#TCB_SF_OFS]    // Load stack frame information\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        it       eq                     // If extended stack frame\n        vldmiaeq r0!,{s16-s31}          //  Restore VFP S16..S31\n      .else\n        mvn      lr,#~0xFFFFFFFD        // Set EXC_RETURN value\n      .endif\n        ldmia    r0!,{r4-r11}           // Restore R4..R11\n        msr      psp,r0                 // Set PSP\n\nSVC_Exit:\n        bx       lr                     // Exit from handler\n\nSVC_User:\n        ldr      r2,=osRtxUserSVC       // Load address of SVC table\n        ldr      r3,[r2]                // Load SVC maximum number\n        cmp      r1,r3                  // Check SVC number range\n        bhi      SVC_Exit               // Branch if out of range\n\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        ldr      r12,[r2,r1,lsl #2]     // Load address of SVC function\n        ldm      r0,{r0-r3}             // Load function parameters from stack\n        blx      r12                    // Call service function\n        pop      {r12,lr}               // Restore SP and EXC_RETURN\n        str      r0,[r12]               // Store function return value\n\n        bx       lr                     // Return from handler\n\n        .fnend\n        .size    SVC_Handler, .-SVC_Handler\n\n\n        .thumb_func\n        .type    PendSV_Handler, %function\n        .global  PendSV_Handler\n        .fnstart\n        .cantunwind\nPendSV_Handler:\n\n        push     {r0,lr}                // Save EXC_RETURN\n        bl       osRtxPendSV_Handler    // Call osRtxPendSV_Handler\n        pop      {r0,lr}                // Restore EXC_RETURN\n        mrs      r12,psp                // Save PSP to R12\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size    PendSV_Handler, .-PendSV_Handler\n\n\n        .thumb_func\n        .type    SysTick_Handler, %function\n        .global  SysTick_Handler\n        .fnstart\n        .cantunwind\nSysTick_Handler:\n\n        push     {r0,lr}                // Save EXC_RETURN\n        bl       osRtxTick_Handler      // Call osRtxTick_Handler\n        pop      {r0,lr}                // Restore EXC_RETURN\n        mrs      r12,psp                // Save PSP to R12\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size    SysTick_Handler, .-SysTick_Handler\n\n\n    #ifdef RTX_SAFETY_FEATURES\n\n        .thumb_func\n        .type    osFaultResume, %function\n        .global  osFaultResume\n        .fnstart\n        .cantunwind\nosFaultResume:\n\n        mrs      r12,psp                // Save PSP to R12\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size   osFaultResume, .-osFaultResume\n\n    #endif // RTX_SAFETY_FEATURES\n\n\n        .end\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S",
    "content": "/*\n * Copyright (c) 2016-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       ARMv8-M Baseline Exception handlers\n *\n * -----------------------------------------------------------------------------\n */\n\n\n        .syntax  unified\n\n        #include \"rtx_def.h\"\n\n        .equ     I_T_RUN_OFS, 20        // osRtxInfo.thread.run offset\n        .equ     TCB_SM_OFS,  48        // TCB.stack_mem offset\n        .equ     TCB_SP_OFS,  56        // TCB.SP offset\n        .equ     TCB_SF_OFS,  34        // TCB.stack_frame offset\n        .equ     TCB_TZM_OFS, 64        // TCB.tz_memory offset\n        .equ     TCB_ZONE_OFS,68        // TCB.zone offset\n\n        .equ     osRtxErrorStackOverflow, 1 // Stack overflow\n        .equ     osRtxErrorSVC,           6 // Invalid SVC function called\n\n        .section \".rodata\"\n        .global  irqRtxLib              // Non weak library reference\nirqRtxLib:\n        .byte    0\n\n\n        .thumb\n        .section \".text\"\n        .align   2\n        .eabi_attribute Tag_ABI_align_preserved, 1\n\n\n        .thumb_func\n        .type    SVC_Handler, %function\n        .global  SVC_Handler\n        .fnstart\n        .cantunwind\nSVC_Handler:\n\n        mov      r0,lr\n        lsrs     r0,r0,#3               // Determine return stack from EXC_RETURN bit 2\n        bcc      SVC_MSP                // Branch if return stack is MSP\n        mrs      r0,psp                 // Get PSP\n\nSVC_Number:\n        ldr      r1,[r0,#24]            // Load saved PC from stack\n        subs     r1,r1,#2               // Point to SVC instruction\n        ldrb     r1,[r1]                // Load SVC number\n        cmp      r1,#0                  // Check SVC number\n        bne      SVC_User               // Branch if not SVC 0\n\n    #ifdef RTX_SVC_PTR_CHECK\n\n        subs     r1,r7,#0x01            // Clear T-bit of function address\n        lsls     r2,r1,#29              // Check if 8-byte aligned\n        beq      SVC_PtrBoundsCheck     // Branch if address is aligned\n\nSVC_PtrInvalid:\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        movs     r0,#osRtxErrorSVC      // Parameter: code\n        mov      r1,r7                  // Parameter: object_id\n        bl       osRtxKernelErrorNotify // Call osRtxKernelErrorNotify\n        pop      {r2,r3}                // Restore SP and EXC_RETURN\n        mov      lr,r3                  // Set EXC_RETURN\n        b        SVC_Context            // Branch to context handling\n\nSVC_PtrBoundsCheck:\n        ldr      r2,=Image$$RTX_SVC_VENEERS$$Base\n        ldr      r3,=Image$$RTX_SVC_VENEERS$$Length\n        subs     r2,r1,r2               // Subtract SVC table base address\n        cmp      r2,r3                  // Compare with SVC table boundaries\n        bhs      SVC_PtrInvalid         // Branch if address is out of bounds\n\n    #endif // RTX_SVC_PTR_CHECK\n\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        ldmia    r0,{r0-r3}             // Load function parameters from stack\n        blx      r7                     // Call service function\n        pop      {r2,r3}                // Restore SP and EXC_RETURN\n        str      r0,[r2]                // Store function return value\n        mov      lr,r3                  // Set EXC_RETURN\n\nSVC_Context:\n        ldr      r3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.thread.run\n        ldmia    r3!,{r1,r2}            // Load osRtxInfo.thread.run: curr & next\n        cmp      r1,r2                  // Check if thread switch is required\n        beq      SVC_Exit               // Branch when threads are the same\n\n        subs     r3,r3,#8               // Adjust address\n        str      r2,[r3]                // osRtxInfo.thread.run: curr = next\n        cbz      r1,SVC_ContextRestore  // Branch if running thread is deleted\n\nSVC_ContextSave:\n    #ifdef RTX_TZ_CONTEXT\n        mov      r3,lr                  // Get EXC_RETURN\n        ldr      r0,[r1,#TCB_TZM_OFS]   // Load TrustZone memory identifier\n        cbz      r0,SVC_ContextSave_NS  // Branch if there is no secure context\n        push     {r0-r3}                // Save registers\n        bl       TZ_StoreContext_S      // Store secure context\n        pop      {r0-r3}                // Restore registers\n        mov      lr,r3                  // Set EXC_RETURN\n    #endif\n\nSVC_ContextSave_NS:\n        mrs      r0,psp                 // Get PSP\n    #if (DOMAIN_NS != 0)\n        mov      r3,lr                  // Get EXC_RETURN\n        lsls     r3,r3,#25              // Check domain of interrupted thread\n        bmi      SVC_ContextSaveSP      // Branch if secure\n    #endif\n\n    #ifdef RTX_STACK_CHECK\n        subs     r0,r0,#32              // Calculate SP: space for R4..R11\n\nSVC_ContextSaveSP:\n        str      r0,[r1,#TCB_SP_OFS]    // Store SP\n        mov      r3,lr                  // Get EXC_RETURN\n        movs     r0,#TCB_SF_OFS         // Get TCB.stack_frame offset\n        strb     r3,[r1,r0]             // Store stack frame information\n\n        push     {r1,r2}                // Save osRtxInfo.thread.run: curr & next\n        mov      r0,r1                  // Parameter: osRtxInfo.thread.run.curr\n        bl       osRtxThreadStackCheck  // Check if thread stack is overrun\n        pop      {r1,r2}                // Restore osRtxInfo.thread.run: curr & next\n        cbnz     r0,SVC_ContextSaveRegs // Branch when stack check is ok\n\n        movs     r0,#osRtxErrorStackOverflow // Parameter: r0=code, r1=object_id\n        bl       osRtxKernelErrorNotify      // Call osRtxKernelErrorNotify\n        ldr      r3,=osRtxInfo+I_T_RUN_OFS   // Load address of osRtxInfo.thread.run\n        ldr      r2,[r3,#4]             // Load osRtxInfo.thread.run: next\n        str      r2,[r3]                // osRtxInfo.thread.run: curr = next\n        movs     r1,#0                  // Simulate deleted running thread\n        b        SVC_ContextRestore     // Branch to context restore handling\n\nSVC_ContextSaveRegs:\n      #if (DOMAIN_NS != 0)\n        movs     r0,#TCB_SF_OFS         // Get TCB.stack_frame offset\n        ldrsb    r3,[r1,r0]             // Load stack frame information\n        lsls     r3,r3,#25              // Check domain of interrupted thread\n        bmi      SVC_ContextRestore     // Branch if secure\n      #endif\n        ldr      r0,[r1,#TCB_SP_OFS]    // Load SP\n        stmia    r0!,{r4-r7}            // Save R4..R7\n        mov      r4,r8\n        mov      r5,r9\n        mov      r6,r10\n        mov      r7,r11\n        stmia    r0!,{r4-r7}            // Save R8..R11\n    #else\n        subs     r0,r0,#32              // Calculate SP: space for R4..R11\n        stmia    r0!,{r4-r7}            // Save R4..R7\n        mov      r4,r8\n        mov      r5,r9\n        mov      r6,r10\n        mov      r7,r11\n        stmia    r0!,{r4-r7}            // Save R8..R11\n        subs     r0,r0,#32              // Adjust address\nSVC_ContextSaveSP:\n        str      r0,[r1,#TCB_SP_OFS]    // Store SP\n        mov      r3,lr                  // Get EXC_RETURN\n        movs     r0,#TCB_SF_OFS         // Get TCB.stack_frame offset\n        strb     r3,[r1,r0]             // Store stack frame information\n    #endif // RTX_STACK_CHECK\n\nSVC_ContextRestore:\n        movs     r4,r2                  // Assign osRtxInfo.thread.run.next to R4\n    #ifdef RTX_EXECUTION_ZONE\n        movs     r3,#TCB_ZONE_OFS       // Get TCB.zone offset\n        ldrb     r0,[r2,r3]             // Load osRtxInfo.thread.run.next: zone\n        cbz      r1,SVC_ZoneSetup       // Branch if running thread is deleted\n        ldrb     r1,[r1,r3]             // Load osRtxInfo.thread.run.curr: zone\n        cmp      r0,r1                  // Check if next:zone == curr:zone\n        beq      SVC_ContextRestore_S   // Branch if zone has not changed\n\nSVC_ZoneSetup:\n        bl       osZoneSetup_Callback   // Setup zone for next thread\n    #endif // RTX_EXECUTION_ZONE\n\nSVC_ContextRestore_S:\n    #ifdef RTX_TZ_CONTEXT\n        ldr      r0,[r4,#TCB_TZM_OFS]   // Load TrustZone memory identifier\n        cbz      r0,SVC_ContextRestore_NS // Branch if there is no secure context\n        bl       TZ_LoadContext_S       // Load secure context\n    #endif\n\nSVC_ContextRestore_NS:\n        ldr      r0,[r4,#TCB_SM_OFS]    // Load stack memory base\n        msr      psplim,r0              // Set PSPLIM\n        movs     r0,#TCB_SF_OFS         // Get TCB.stack_frame offset\n        ldrsb    r3,[r4,r0]             // Load stack frame information\n        mov      lr,r3                  // Set EXC_RETURN\n        ldr      r0,[r4,#TCB_SP_OFS]    // Load SP\n    #if (DOMAIN_NS != 0)\n        lsls     r3,r3,#25              // Check domain of interrupted thread\n        bmi      SVC_ContextRestoreSP   // Branch if secure\n    #endif\n\n        adds     r0,r0,#16              // Adjust address\n        ldmia    r0!,{r4-r7}            // Restore R8..R11\n        mov      r8,r4\n        mov      r9,r5\n        mov      r10,r6\n        mov      r11,r7\n        subs     r0,r0,#32              // Adjust address\n        ldmia    r0!,{r4-r7}            // Restore R4..R7\n        adds     r0,r0,#16              // Adjust address\n\nSVC_ContextRestoreSP:\n        msr      psp,r0                 // Set PSP\n\nSVC_Exit:\n        bx       lr                     // Exit from handler\n\nSVC_MSP:\n        mrs      r0,msp                 // Get MSP\n        b        SVC_Number\n\nSVC_User:\n        ldr      r2,=osRtxUserSVC       // Load address of SVC table\n        ldr      r3,[r2]                // Load SVC maximum number\n        cmp      r1,r3                  // Check SVC number range\n        bhi      SVC_Exit               // Branch if out of range\n\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        lsls     r1,r1,#2\n        ldr      r3,[r2,r1]             // Load address of SVC function\n        mov      r12,r3\n        ldmia    r0,{r0-r3}             // Load function parameters from stack\n        blx      r12                    // Call service function\n        pop      {r2,r3}                // Restore SP and EXC_RETURN\n        str      r0,[r2]                // Store function return value\n\n        bx       r3                     // Return from handler\n\n        .fnend\n        .size    SVC_Handler, .-SVC_Handler\n\n\n        .thumb_func\n        .type    PendSV_Handler, %function\n        .global  PendSV_Handler\n        .fnstart\n        .cantunwind\nPendSV_Handler:\n\n        push     {r0,lr}                // Save EXC_RETURN\n        bl       osRtxPendSV_Handler    // Call osRtxPendSV_Handler\n        pop      {r0,r1}                // Restore EXC_RETURN\n        mov      lr,r1                  // Set EXC_RETURN\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size    PendSV_Handler, .-PendSV_Handler\n\n\n        .thumb_func\n        .type    SysTick_Handler, %function\n        .global  SysTick_Handler\n        .fnstart\n        .cantunwind\nSysTick_Handler:\n\n        push     {r0,lr}                // Save EXC_RETURN\n        bl       osRtxTick_Handler      // Call osRtxTick_Handler\n        pop      {r0,r1}                // Restore EXC_RETURN\n        mov      lr,r1                  // Set EXC_RETURN\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size    SysTick_Handler, .-SysTick_Handler\n\n\n    #ifdef RTX_SAFETY_FEATURES\n\n        .thumb_func\n        .type    osFaultResume, %function\n        .global  osFaultResume\n        .fnstart\n        .cantunwind\nosFaultResume:\n\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size   osFaultResume, .-osFaultResume\n\n    #endif // RTX_SAFETY_FEATURES\n\n\n        .end\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S",
    "content": "/*\n * Copyright (c) 2016-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       ARMv8-M Mainline Exception handlers\n *\n * -----------------------------------------------------------------------------\n */\n\n\n        .syntax  unified\n\n        #include \"rtx_def.h\"\n\n        #if (defined(__ARM_FP) && (__ARM_FP > 0))\n        .equ     FPU_USED,    1\n        #else\n        .equ     FPU_USED,    0\n        #endif\n\n        #if (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))\n        .equ     MVE_USED,    1\n        #else\n        .equ     MVE_USED,    0\n        #endif\n\n        .equ     I_T_RUN_OFS, 20        // osRtxInfo.thread.run offset\n        .equ     TCB_SM_OFS,  48        // TCB.stack_mem offset\n        .equ     TCB_SP_OFS,  56        // TCB.SP offset\n        .equ     TCB_SF_OFS,  34        // TCB.stack_frame offset\n        .equ     TCB_TZM_OFS, 64        // TCB.tz_memory offset\n        .equ     TCB_ZONE_OFS,68        // TCB.zone offset\n\n        .equ     FPCCR,     0xE000EF34  // FPCCR Address\n\n        .equ     osRtxErrorStackOverflow, 1 // Stack overflow\n        .equ     osRtxErrorSVC,           6 // Invalid SVC function called\n\n        .section \".rodata\"\n        .global  irqRtxLib              // Non weak library reference\nirqRtxLib:\n        .byte    0\n\n\n        .thumb\n        .section \".text\"\n        .align   2\n        .eabi_attribute Tag_ABI_align_preserved, 1\n\n\n        .thumb_func\n        .type    SVC_Handler, %function\n        .global  SVC_Handler\n        .fnstart\n        .cantunwind\nSVC_Handler:\n\n        tst      lr,#0x04               // Determine return stack from EXC_RETURN bit 2\n        ite      eq\n        mrseq    r0,msp                 // Get MSP if return stack is MSP\n        mrsne    r0,psp                 // Get PSP if return stack is PSP\n\n        ldr      r1,[r0,#24]            // Load saved PC from stack\n        ldrb     r1,[r1,#-2]            // Load SVC number\n        cmp      r1,#0                  // Check SVC number\n        bne      SVC_User               // Branch if not SVC 0\n\n    #ifdef RTX_SVC_PTR_CHECK\n\n        ldr      r12,[r0,#16]           // Load function address from stack\n        sub      r1,r12,#1              // Clear T-bit of function address\n        lsls     r2,r1,#30              // Check if 4-byte aligned\n        beq      SVC_PtrBoundsCheck     // Branch if address is aligned\n\nSVC_PtrInvalid:\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        movs     r0,#osRtxErrorSVC      // Parameter: code\n        mov      r1,r12                 // Parameter: object_id\n        bl       osRtxKernelErrorNotify // Call osRtxKernelErrorNotify\n        pop      {r12,lr}               // Restore SP and EXC_RETURN\n        b        SVC_Context            // Branch to context handling\n\nSVC_PtrBoundsCheck:\n        ldr      r2,=Image$$RTX_SVC_VENEERS$$Base\n        ldr      r3,=Image$$RTX_SVC_VENEERS$$Length\n        subs     r2,r1,r2               // Subtract SVC table base address\n        cmp      r2,r3                  // Compare with SVC table boundaries\n        bhs      SVC_PtrInvalid         // Branch if address is out of bounds\n\n    #endif // RTX_SVC_PTR_CHECK\n\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        ldm      r0,{r0-r3,r12}         // Load function parameters and address from stack\n        blx      r12                    // Call service function\n        pop      {r12,lr}               // Restore SP and EXC_RETURN\n        str      r0,[r12]               // Store function return value\n\nSVC_Context:\n        ldr      r3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.thread.run\n        ldm      r3,{r1,r2}             // Load osRtxInfo.thread.run: curr & next\n        cmp      r1,r2                  // Check if thread switch is required\n        it       eq\n        bxeq     lr                     // Exit when threads are the same\n\n        str      r2,[r3]                // osRtxInfo.thread.run: curr = next\n\n      .if (FPU_USED != 0) || (MVE_USED != 0)\n        cbnz     r1,SVC_ContextSave     // Branch if running thread is not deleted\nSVC_FP_LazyState:\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        bne      SVC_ContextRestore     // Branch if not extended stack frame\n        ldr      r3,=FPCCR              // FPCCR Address\n        ldr      r0,[r3]                // Load FPCCR\n        bic      r0,r0,#1               // Clear LSPACT (Lazy state preservation)\n        str      r0,[r3]                // Store FPCCR\n        b        SVC_ContextRestore     // Branch to context restore handling\n      .else\n        cbz      r1,SVC_ContextRestore  // Branch if running thread is deleted\n      .endif\n\nSVC_ContextSave:\n    #ifdef RTX_TZ_CONTEXT\n        ldr      r0,[r1,#TCB_TZM_OFS]   // Load TrustZone memory identifier\n        cbz      r0,SVC_ContextSave_NS  // Branch if there is no secure context\n        push     {r1,r2,r12,lr}         // Save registers and EXC_RETURN\n        bl       TZ_StoreContext_S      // Store secure context\n        pop      {r1,r2,r12,lr}         // Restore registers and EXC_RETURN\n    #endif\n\nSVC_ContextSave_NS:\n    #if (DOMAIN_NS != 0)\n        tst      lr,#0x40               // Check domain of interrupted thread\n        bne      SVC_ContextSaveSP      // Branch if secure\n    #endif\n\n    #ifdef RTX_STACK_CHECK\n        sub      r12,r12,#32            // Calculate SP: space for R4..R11\n      .if (FPU_USED != 0) || (MVE_USED != 0)\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        it       eq                     // If extended stack frame\n        subeq    r12,r12,#64            //  Additional space for S16..S31\n      .endif\n\nSVC_ContextSaveSP:\n        str      r12,[r1,#TCB_SP_OFS]   // Store SP\n        strb     lr, [r1,#TCB_SF_OFS]   // Store stack frame information\n\n        push     {r1,r2}                // Save osRtxInfo.thread.run: curr & next\n        mov      r0,r1                  // Parameter: osRtxInfo.thread.run.curr\n        bl       osRtxThreadStackCheck  // Check if thread stack is overrun\n        pop      {r1,r2}                // Restore osRtxInfo.thread.run: curr & next\n        cbnz     r0,SVC_ContextSaveRegs // Branch when stack check is ok\n\n      .if (FPU_USED != 0) || (MVE_USED != 0)\n        mov      r4,r1                  // Assign osRtxInfo.thread.run.curr to R4\n      .endif\n        movs     r0,#osRtxErrorStackOverflow // Parameter: r0=code, r1=object_id\n        bl       osRtxKernelErrorNotify      // Call osRtxKernelErrorNotify\n        ldr      r3,=osRtxInfo+I_T_RUN_OFS   // Load address of osRtxInfo.thread.run\n        ldr      r2,[r3,#4]             // Load osRtxInfo.thread.run: next\n        str      r2,[r3]                // osRtxInfo.thread.run: curr = next\n        movs     r1,#0                  // Simulate deleted running thread\n      .if (FPU_USED != 0) || (MVE_USED != 0)\n        ldrsb    lr,[r4,#TCB_SF_OFS]    // Load stack frame information\n        b        SVC_FP_LazyState       // Branch to FP lazy state handling\n      .else\n        b        SVC_ContextRestore     // Branch to context restore handling\n      .endif\n\nSVC_ContextSaveRegs:\n        ldrsb    lr,[r1,#TCB_SF_OFS]    // Load stack frame information\n      #if (DOMAIN_NS != 0)\n        tst      lr,#0x40               // Check domain of interrupted thread\n        bne      SVC_ContextRestore     // Branch if secure\n      #endif\n        ldr      r12,[r1,#TCB_SP_OFS]   // Load SP\n      .if (FPU_USED != 0) || (MVE_USED != 0)\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        it       eq                     // If extended stack frame\n        vstmiaeq r12!,{s16-s31}         //  Save VFP S16..S31\n      .endif\n        stm      r12,{r4-r11}           // Save R4..R11\n    #else\n        stmdb    r12!,{r4-r11}          // Save R4..R11\n      .if (FPU_USED != 0) || (MVE_USED != 0)\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        it       eq                     // If extended stack frame\n        vstmdbeq r12!,{s16-s31}         //  Save VFP S16.S31\n      .endif\nSVC_ContextSaveSP:\n        str      r12,[r1,#TCB_SP_OFS]   // Store SP\n        strb     lr, [r1,#TCB_SF_OFS]   // Store stack frame information\n    #endif // RTX_STACK_CHECK\n\nSVC_ContextRestore:\n        movs     r4,r2                  // Assign osRtxInfo.thread.run.next to R4, clear Z flag\n    #ifdef RTX_EXECUTION_ZONE\n        ldrb     r0,[r2,#TCB_ZONE_OFS]  // Load osRtxInfo.thread.run.next: zone\n        cbz      r1,SVC_ZoneSetup       // Branch if running thread is deleted (Z flag unchanged)\n        ldrb     r1,[r1,#TCB_ZONE_OFS]  // Load osRtxInfo.thread.run.curr: zone\n        cmp      r0,r1                  // Check if next:zone == curr:zone\n\nSVC_ZoneSetup:\n        it       ne                     // If zone has changed or running thread is deleted\n        blne     osZoneSetup_Callback   //  Setup zone for next thread\n    #endif // RTX_EXECUTION_ZONE\n\n    #ifdef RTX_TZ_CONTEXT\n        ldr      r0,[r4,#TCB_TZM_OFS]   // Load TrustZone memory identifier\n        cmp      r0,#0\n        it       ne                     // If TrustZone memory allocated\n        blne     TZ_LoadContext_S       //  Load secure context\n    #endif\n\n        ldr      r0,[r4,#TCB_SP_OFS]    // Load SP\n        ldr      r1,[r4,#TCB_SM_OFS]    // Load stack memory base\n        msr      psplim,r1              // Set PSPLIM\n        ldrsb    lr,[r4,#TCB_SF_OFS]    // Load stack frame information\n    #if (DOMAIN_NS != 0)\n        tst      lr,#0x40               // Check domain of interrupted thread\n        itt      ne                     // If secure\n        msrne    psp,r0                 //  Set PSP\n        bxne     lr                     //  Exit from handler\n    #endif\n\n      .if (FPU_USED != 0) || (MVE_USED != 0)\n        tst      lr,#0x10               // Determine stack frame from EXC_RETURN bit 4\n        it       eq                     // If extended stack frame\n        vldmiaeq r0!,{s16-s31}          //  Restore VFP S16..S31\n      .endif\n        ldmia    r0!,{r4-r11}           // Restore R4..R11\n        msr      psp,r0                 // Set PSP\n\nSVC_Exit:\n        bx       lr                     // Exit from handler\n\nSVC_User:\n        ldr      r2,=osRtxUserSVC       // Load address of SVC table\n        ldr      r3,[r2]                // Load SVC maximum number\n        cmp      r1,r3                  // Check SVC number range\n        bhi      SVC_Exit               // Branch if out of range\n\n        push     {r0,lr}                // Save SP and EXC_RETURN\n        ldr      r12,[r2,r1,lsl #2]     // Load address of SVC function\n        ldm      r0,{r0-r3}             // Load function parameters from stack\n        blx      r12                    // Call service function\n        pop      {r12,lr}               // Restore SP and EXC_RETURN\n        str      r0,[r12]               // Store function return value\n\n        bx       lr                     // Return from handler\n\n        .fnend\n        .size    SVC_Handler, .-SVC_Handler\n\n\n        .thumb_func\n        .type    PendSV_Handler, %function\n        .global  PendSV_Handler\n        .fnstart\n        .cantunwind\nPendSV_Handler:\n\n        push     {r0,lr}                // Save EXC_RETURN\n        bl       osRtxPendSV_Handler    // Call osRtxPendSV_Handler\n        pop      {r0,lr}                // Restore EXC_RETURN\n        mrs      r12,psp                // Save PSP to R12\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size    PendSV_Handler, .-PendSV_Handler\n\n\n        .thumb_func\n        .type    SysTick_Handler, %function\n        .global  SysTick_Handler\n        .fnstart\n        .cantunwind\nSysTick_Handler:\n\n        push     {r0,lr}                // Save EXC_RETURN\n        bl       osRtxTick_Handler      // Call osRtxTick_Handler\n        pop      {r0,lr}                // Restore EXC_RETURN\n        mrs      r12,psp                // Save PSP to R12\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size    SysTick_Handler, .-SysTick_Handler\n\n\n    #ifdef RTX_SAFETY_FEATURES\n\n        .thumb_func\n        .type    osFaultResume, %function\n        .global  osFaultResume\n        .fnstart\n        .cantunwind\nosFaultResume:\n\n        mrs      r12,psp                // Save PSP to R12\n        b        SVC_Context            // Branch to context handling\n\n        .fnend\n        .size   osFaultResume, .-osFaultResume\n\n    #endif // RTX_SAFETY_FEATURES\n\n\n        .end\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s",
    "content": ";/*\n; * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; * -----------------------------------------------------------------------------\n; *\n; * Project:     CMSIS-RTOS RTX\n; * Title:       ARMv6-M Exception handlers\n; *\n; * -----------------------------------------------------------------------------\n; */\n\n\n                NAME     irq_armv6m.s\n\n\n                #include \"rtx_def.h\"\n\nI_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset\nTCB_SP_OFS      EQU      56                     ; TCB.SP offset\nTCB_ZONE_OFS    EQU      68                     ; TCB.zone offset\n\nosRtxErrorStackOverflow\\\n                EQU      1                      ; Stack overflow\nosRtxErrorSVC   EQU      6                      ; Invalid SVC function called\n\n\n                PRESERVE8\n                SECTION .rodata:DATA:NOROOT(2)\n\n\n                EXPORT   irqRtxLib\nirqRtxLib       DCB      0                      ; Non weak library reference\n\n\n                THUMB\n                SECTION .text:CODE:NOROOT(2)\n\n\nSVC_Handler\n                EXPORT   SVC_Handler\n                IMPORT   osRtxUserSVC\n                IMPORT   osRtxInfo\n            #ifdef RTX_STACK_CHECK\n                IMPORT   osRtxThreadStackCheck\n                IMPORT   osRtxKernelErrorNotify\n            #endif\n            #ifdef RTX_SVC_PTR_CHECK\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Base|\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Length|\n                IMPORT   osRtxKernelErrorNotify\n            #endif\n            #ifdef RTX_EXECUTION_ZONE\n                IMPORT   osZoneSetup_Callback\n            #endif\n\n                MOV      R0,LR\n                LSRS     R0,R0,#3               ; Determine return stack from EXC_RETURN bit 2\n                BCC      SVC_MSP                ; Branch if return stack is MSP\n                MRS      R0,PSP                 ; Get PSP\n\nSVC_Number\n                LDR      R1,[R0,#24]            ; Load saved PC from stack\n                SUBS     R1,R1,#2               ; Point to SVC instruction\n                LDRB     R1,[R1]                ; Load SVC number\n                CMP      R1,#0                  ; Check SVC number\n                BNE      SVC_User               ; Branch if not SVC 0\n\n            #ifdef RTX_SVC_PTR_CHECK\n\n                SUBS     R1,R7,#0x01            ; Clear T-bit of function address\n                LSLS     R2,R1,#29              ; Check if 8-byte aligned\n                BEQ      SVC_PtrBoundsCheck     ; Branch if address is aligned\n\nSVC_PtrInvalid\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                MOVS     R0,#osRtxErrorSVC      ; Parameter: code\n                MOV      R1,R7                  ; Parameter: object_id\n                BL       osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify\n                POP      {R2,R3}                ; Restore SP and EXC_RETURN\n                MOV      LR,R3                  ; Set EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\nSVC_PtrBoundsCheck\n                LDR      R2,=|Image$$RTX_SVC_VENEERS$$Base|\n                LDR      R3,=|Image$$RTX_SVC_VENEERS$$Length|\n                SUBS     R2,R1,R2               ; Subtract SVC table base address\n                CMP      R2,R3                  ; Compare with SVC table boundaries\n                BHS      SVC_PtrInvalid         ; Branch if address is out of bounds\n\n              #endif\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LDMIA    R0,{R0-R3}             ; Load function parameters from stack\n                BLX      R7                     ; Call service function\n                POP      {R2,R3}                ; Restore SP and EXC_RETURN\n                STR      R0,[R2]                ; Store function return value\n                MOV      LR,R3                  ; Set EXC_RETURN\n\nSVC_Context\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run\n                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next\n                CMP      R1,R2                  ; Check if thread switch is required\n                BEQ      SVC_Exit               ; Branch when threads are the same\n\n                SUBS     R3,R3,#8               ; Adjust address\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n                CMP      R1,#0\n                BEQ      SVC_ContextRestore     ; Branch if running thread is deleted\n\nSVC_ContextSave\n                MRS      R0,PSP                 ; Get PSP\n                SUBS     R0,R0,#32              ; Calculate SP: space for R4..R11\n                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP\n\n            #ifdef RTX_STACK_CHECK\n\n                PUSH     {R1,R2}                ; Save osRtxInfo.thread.run: curr & next\n                MOV      R0,R1                  ; Parameter: osRtxInfo.thread.run.curr\n                BL       osRtxThreadStackCheck  ; Check if thread stack is overrun\n                POP      {R1,R2}                ; Restore osRtxInfo.thread.run: curr & next\n                CMP      R0,#0\n                BNE      SVC_ContextSaveRegs    ; Branch when stack check is ok\n\n                MOVS     R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id\n                BL       osRtxKernelErrorNotify      ; Call osRtxKernelErrorNotify\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS   ; Load address of osRtxInfo.thread.run\n                LDR      R2,[R3,#4]             ; Load osRtxInfo.thread.run: next\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n                MOVS     R1,#0                  ; Simulate deleted running thread\n                B        SVC_ContextRestore     ; Branch to context restore handling\n\nSVC_ContextSaveRegs\n                LDR      R0,[R1,#TCB_SP_OFS]    ; Load SP\n\n            #endif\n\n                STMIA    R0!,{R4-R7}            ; Save R4..R7\n                MOV      R4,R8\n                MOV      R5,R9\n                MOV      R6,R10\n                MOV      R7,R11\n                STMIA    R0!,{R4-R7}            ; Save R8..R11\n\nSVC_ContextRestore\n                 MOVS     R4,R2                 ; Assign osRtxInfo.thread.run.next to R4\n            #ifdef RTX_EXECUTION_ZONE\n                 MOVS     R3,#TCB_ZONE_OFS      ; Get TCB.zone offset\n                 LDRB     R0,[R2,R3]            ; Load osRtxInfo.thread.run.next: zone\n                 CMP      R1,#0\n                 BEQ      SVC_ZoneSetup         ; Branch if running thread is deleted\n                 LDRB     R1,[R1,R3]            ; Load osRtxInfo.thread.run.curr: zone\n                 CMP      R0,R1                 ; Check if next:zone == curr:zone\n                 BEQ      SVC_ContextRestore_N  ; Branch if zone has not changed\n\nSVC_ZoneSetup\n                 BL     osZoneSetup_Callback    ;  Setup zone for next thread\n            #endif\n\nSVC_ContextRestore_N\n                LDR      R0,[R4,#TCB_SP_OFS]    ; Load SP\n                ADDS     R0,R0,#16              ; Adjust address\n                LDMIA    R0!,{R4-R7}            ; Restore R8..R11\n                MOV      R8,R4\n                MOV      R9,R5\n                MOV      R10,R6\n                MOV      R11,R7\n                MSR      PSP,R0                 ; Set PSP\n                SUBS     R0,R0,#32              ; Adjust address\n                LDMIA    R0!,{R4-R7}            ; Restore R4..R7\n\n                MOVS     R0,#2                  ; Binary complement of 0xFFFFFFFD\n                MVNS     R0,R0                  ; Set EXC_RETURN value\n                BX       R0                     ; Exit from handler\n\nSVC_MSP\n                MRS      R0,MSP                 ; Get MSP\n                B        SVC_Number\n\nSVC_Exit\n                BX       LR                     ; Exit from handler\n\nSVC_User\n                LDR      R2,=osRtxUserSVC       ; Load address of SVC table\n                LDR      R3,[R2]                ; Load SVC maximum number\n                CMP      R1,R3                  ; Check SVC number range\n                BHI      SVC_Exit               ; Branch if out of range\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LSLS     R1,R1,#2\n                LDR      R3,[R2,R1]             ; Load address of SVC function\n                MOV      R12,R3\n                LDMIA    R0,{R0-R3}             ; Load function parameters from stack\n                BLX      R12                    ; Call service function\n                POP      {R2,R3}                ; Restore SP and EXC_RETURN\n                STR      R0,[R2]                ; Store function return value\n\n                BX       R3                     ; Return from handler\n\n\nPendSV_Handler\n                EXPORT   PendSV_Handler\n                IMPORT   osRtxPendSV_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler\n                POP      {R0,R1}                ; Restore EXC_RETURN\n                MOV      LR,R1                  ; Set EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\n\nSysTick_Handler\n                EXPORT   SysTick_Handler\n                IMPORT   osRtxTick_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxTick_Handler      ; Call osRtxTick_Handler\n                POP      {R0,R1}                ; Restore EXC_RETURN\n                MOV      LR,R1                  ; Set EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\n\n            #ifdef RTX_SAFETY_FEATURES\n\nosFaultResume   PROC\n                EXPORT   osFaultResume\n\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n            #endif\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s",
    "content": ";/*\n; * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; * -----------------------------------------------------------------------------\n; *\n; * Project:     CMSIS-RTOS RTX\n; * Title:       ARMv7-A Exception handlers\n; *\n; * -----------------------------------------------------------------------------\n; */\n\n\n                NAME     irq_armv7a.s\n\n\n                #include \"rtx_def.h\"\n\nMODE_FIQ        EQU      0x11\nMODE_IRQ        EQU      0x12\nMODE_SVC        EQU      0x13\nMODE_ABT        EQU      0x17\nMODE_UND        EQU      0x1B\n\nCPSR_BIT_T      EQU      0x20\n\nK_STATE_RUNNING EQU      2                          ; osKernelState_t::osKernelRunning\nI_K_STATE_OFS   EQU      8                          ; osRtxInfo.kernel.state offset\nI_TICK_IRQN_OFS EQU      16                         ; osRtxInfo.tick_irqn offset\nI_T_RUN_OFS     EQU      20                         ; osRtxInfo.thread.run offset\nTCB_SP_FRAME    EQU      34                         ; osRtxThread_t.stack_frame offset\nTCB_SP_OFS      EQU      56                         ; osRtxThread_t.sp offset\nTCB_ZONE_OFS    EQU      68                         ; osRtxThread_t.zone offset\n\n\n                PRESERVE8\n\n\n                SECTION .rodata:DATA:NOROOT(2)\n                EXPORT   irqRtxLib\nirqRtxLib       DCB      0                          ; Non weak library reference\n\n\n                SECTION .data:DATA:NOROOT(2)\n                EXPORT   SVC_Active\n                EXPORT   IRQ_PendSV\nIRQ_NestLevel   DCD      0                          ; IRQ nesting level counter\nSVC_Active      DCB      0                          ; SVC Handler Active\nIRQ_PendSV      DCB      0                          ; Pending SVC flag\n\n\n                SECTION .text:CODE:NOROOT(2)\n\n\nUndef_Handler\n                EXPORT  Undef_Handler\n                IMPORT  CUndefHandler\n\n                SRSFD   SP!, #MODE_UND\n                PUSH    {R0-R4, R12}                ; Save APCS corruptible registers to UND mode stack\n\n                MRS     R0, SPSR\n                TST     R0, #CPSR_BIT_T             ; Check mode\n                MOVEQ   R1, #4                      ; R1 = 4 ARM mode\n                MOVNE   R1, #2                      ; R1 = 2 Thumb mode\n                SUB     R0, LR, R1\n                LDREQ   R0, [R0]                    ; ARM mode - R0 points to offending instruction\n                BEQ     Undef_Cont\n\n                ; Thumb instruction\n                ; Determine if it is a 32-bit Thumb instruction\n                LDRH    R0, [R0]\n                MOV     R2, #0x1C\n                CMP     R2, R0, LSR #11\n                BHS     Undef_Cont                  ; 16-bit Thumb instruction\n\n                ; 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction\n                LDRH    R2, [LR]\n                ORR     R0, R2, R0, LSL #16\nUndef_Cont\n                MOV     R2, LR                      ; Set LR to third argument\n\n                AND     R12, SP, #4                 ; Ensure stack is 8-byte aligned\n                SUB     SP, SP, R12                 ; Adjust stack\n                PUSH    {R12, LR}                   ; Store stack adjustment and dummy LR\n\n                ; R0 =Offending instruction, R1 =2(Thumb) or =4(ARM)\n                BL      CUndefHandler\n\n                POP     {R12, LR}                   ; Get stack adjustment & discard dummy LR\n                ADD     SP, SP, R12                 ; Unadjust stack\n\n                LDR     LR, [SP, #24]               ; Restore stacked LR and possibly adjust for retry\n                SUB     LR, LR, R0\n                LDR     R0, [SP, #28]               ; Restore stacked SPSR\n                MSR     SPSR_CXSF, R0\n                CLREX                               ; Clear exclusive monitor\n                POP     {R0-R4, R12}                ; Restore stacked APCS registers\n                ADD     SP, SP, #8                  ; Adjust SP for already-restored banked registers\n                MOVS    PC, LR\n\n\nPAbt_Handler\n                EXPORT  PAbt_Handler\n                IMPORT  CPAbtHandler\n\n                SUB     LR, LR, #4                  ; Pre-adjust LR\n                SRSFD   SP!, #MODE_ABT              ; Save LR and SPRS to ABT mode stack\n                PUSH    {R0-R4, R12}                ; Save APCS corruptible registers to ABT mode stack\n                MRC     p15, 0, R0, c5, c0, 1       ; IFSR\n                MRC     p15, 0, R1, c6, c0, 2       ; IFAR\n\n                MOV     R2, LR                      ; Set LR to third argument\n\n                AND     R12, SP, #4                 ; Ensure stack is 8-byte aligned\n                SUB     SP, SP, R12                 ; Adjust stack\n                PUSH    {R12, LR}                   ; Store stack adjustment and dummy LR\n\n                BL      CPAbtHandler\n\n                POP     {R12, LR}                   ; Get stack adjustment & discard dummy LR\n                ADD     SP, SP, R12                 ; Unadjust stack\n\n                CLREX                               ; Clear exclusive monitor\n                POP     {R0-R4, R12}                ; Restore stack APCS registers\n                RFEFD   SP!                         ; Return from exception\n\n\nDAbt_Handler\n                EXPORT  DAbt_Handler\n                IMPORT  CDAbtHandler\n\n                SUB     LR, LR, #8                  ; Pre-adjust LR\n                SRSFD   SP!, #MODE_ABT              ; Save LR and SPRS to ABT mode stack\n                PUSH    {R0-R4, R12}                ; Save APCS corruptible registers to ABT mode stack\n                MRC     p15, 0, R0, c5, c0, 0       ; DFSR\n                MRC     p15, 0, R1, c6, c0, 0       ; DFAR\n\n                MOV     R2, LR                      ; Set LR to third argument\n\n                AND     R12, SP, #4                 ; Ensure stack is 8-byte aligned\n                SUB     SP, SP, R12                 ; Adjust stack\n                PUSH    {R12, LR}                   ; Store stack adjustment and dummy LR\n\n                BL      CDAbtHandler\n\n                POP     {R12, LR}                   ; Get stack adjustment & discard dummy LR\n                ADD     SP, SP, R12                 ; Unadjust stack\n\n                CLREX                               ; Clear exclusive monitor\n                POP     {R0-R4, R12}                ; Restore stacked APCS registers\n                RFEFD   SP!                         ; Return from exception\n\n\nIRQ_Handler\n                EXPORT  IRQ_Handler\n                IMPORT  IRQ_GetActiveIRQ\n                IMPORT  IRQ_GetHandler\n                IMPORT  IRQ_EndOfInterrupt\n\n                SUB     LR, LR, #4                  ; Pre-adjust LR\n                SRSFD   SP!, #MODE_SVC              ; Save LR_irq and SPSR_irq on to the SVC stack\n                CPS     #MODE_SVC                   ; Change to SVC mode\n                PUSH    {R0-R3, R12, LR}            ; Save APCS corruptible registers\n\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]\n                ADD     R1, R1, #1                  ; Increment IRQ nesting level\n                STR     R1, [R0]\n\n                MOV     R3, SP                      ; Move SP into R3\n                AND     R3, R3, #4                  ; Get stack adjustment to ensure 8-byte alignment\n                SUB     SP, SP, R3                  ; Adjust stack\n                PUSH    {R3, R4}                    ; Store stack adjustment(R3) and user data(R4)\n\n                BLX     IRQ_GetActiveIRQ            ; Retrieve interrupt ID into R0\n                MOV     R4, R0                      ; Move interrupt ID to R4\n\n                BLX     IRQ_GetHandler              ; Retrieve interrupt handler address for current ID\n                CMP     R0, #0                      ; Check if handler address is 0\n                BEQ     IRQ_End                     ; If 0, end interrupt and return\n\n                CPSIE   i                           ; Re-enable interrupts\n                BLX     R0                          ; Call IRQ handler\n                CPSID   i                           ; Disable interrupts\n\nIRQ_End\n                MOV     R0, R4                      ; Move interrupt ID to R0\n                BLX     IRQ_EndOfInterrupt          ; Signal end of interrupt\n\n                POP     {R3, R4}                    ; Restore stack adjustment(R3) and user data(R4)\n                ADD     SP, SP, R3                  ; Unadjust stack\n\n                BL      osRtxContextSwitch          ; Continue in context switcher\n\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]\n                SUBS    R1, R1, #1                  ; Decrement IRQ nesting level\n                STR     R1, [R0]\n\n                CLREX                               ; Clear exclusive monitor for interrupted code\n                POP     {R0-R3, R12, LR}            ; Restore stacked APCS registers\n                RFEFD   SP!                         ; Return from IRQ handler\n\n\nSVC_Handler\n                EXPORT  SVC_Handler\n                IMPORT  IRQ_Disable\n                IMPORT  IRQ_Enable\n                IMPORT  osRtxUserSVC\n                IMPORT  osRtxInfo\n\n                SRSFD   SP!, #MODE_SVC              ; Store SPSR_svc and LR_svc onto SVC stack\n                PUSH    {R12, LR}\n\n                MRS     R12, SPSR                   ; Load SPSR\n                TST     R12, #CPSR_BIT_T            ; Thumb bit set?\n                LDRHNE  R12, [LR,#-2]               ; Thumb: load halfword\n                BICNE   R12, R12, #0xFF00           ;        extract SVC number\n                LDREQ   R12, [LR,#-4]               ; ARM:   load word\n                BICEQ   R12, R12, #0xFF000000       ;        extract SVC number\n                CMP     R12, #0                     ; Compare SVC number\n                BNE     SVC_User                    ; Branch if User SVC\n\n                PUSH    {R0-R3}                     ; Push arguments to stack\n\n                LDR     R0, =SVC_Active\n                MOV     R1, #1\n                STRB    R1, [R0]                    ; Set SVC Handler Active\n\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]\n                ADD     R1, R1, #1                  ; Increment IRQ nesting level\n                STR     R1, [R0]\n\n                LDR     R0, =osRtxInfo\n                LDR     R1, [R0, #I_K_STATE_OFS]    ; Load RTX5 kernel state\n                CMP     R1, #K_STATE_RUNNING        ; Check osKernelRunning\n                BLT     SVC_FuncCall                ; Continue if kernel is not running\n                LDR     R0, [R0, #I_TICK_IRQN_OFS]  ; Load OS Tick irqn\n                BLX     IRQ_Disable                 ; Disable OS Tick interrupt\nSVC_FuncCall\n                LDM     SP, {R0-R3, R12}            ; Reload R0-R3 and R12 from stack\n\n                CPSIE   i                           ; Re-enable interrupts\n                BLX     R12                         ; Branch to SVC function\n                CPSID   i                           ; Disable interrupts\n\n                STR     R0, [SP]                    ; Store function return value\n\n                LDR     R0, =osRtxInfo\n                LDR     R1, [R0, #I_K_STATE_OFS]    ; Load RTX5 kernel state\n                CMP     R1, #K_STATE_RUNNING        ; Check osKernelRunning\n                BLT     SVC_ContextCheck            ; Continue if kernel is not running\n                LDR     R0, [R0, #I_TICK_IRQN_OFS]  ; Load OS Tick irqn\n                BLX     IRQ_Enable                  ; Enable OS Tick interrupt\n\nSVC_ContextCheck\n                BL      osRtxContextSwitch          ; Continue in context switcher\n\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]\n                SUB     R1, R1, #1                  ; Decrement IRQ nesting level\n                STR     R1, [R0]\n\n                LDR     R0, =SVC_Active\n                MOV     R1, #0\n                STRB    R1, [R0]                    ; Clear SVC Handler Active\n\n                CLREX                               ; Clear exclusive monitor\n                POP     {R0-R3, R12, LR}            ; Restore stacked APCS registers\n                RFEFD   SP!                         ; Return from exception\n\nSVC_User\n                PUSH    {R4, R5}\n                LDR     R5,=osRtxUserSVC            ; Load address of SVC table\n                LDR     R4,[R5]                     ; Load SVC maximum number\n                CMP     R12,R4                      ; Check SVC number range\n                BHI     SVC_Done                    ; Branch if out of range\n                LDR     R12,[R5,R12,LSL #2]         ; Load SVC Function Address\n                BLX     R12                         ; Call SVC Function\nSVC_Done\n                CLREX                               ; Clear exclusive monitor\n                POP     {R4, R5, R12, LR}\n                RFEFD   SP!                         ; Return from exception\n\n\nosRtxContextSwitch\n                EXPORT  osRtxContextSwitch\n                IMPORT  osRtxPendSV_Handler\n                IMPORT  osRtxInfo\n            #ifdef RTX_EXECUTION_ZONE\n                IMPORT  osZoneSetup_Callback\n            #endif\n                IMPORT  IRQ_Disable\n                IMPORT  IRQ_Enable\n\n                PUSH    {LR}\n\n                ; Check interrupt nesting level\n                LDR     R0, =IRQ_NestLevel\n                LDR     R1, [R0]                    ; Load IRQ nest level\n                CMP     R1, #1\n                BNE     osRtxContextExit            ; Nesting interrupts, exit context switcher\n\n                LDR     R12, =osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.run\n                LDM     R12, {R0, R1}               ; Load osRtxInfo.thread.run: curr & next\n                LDR     R2, =IRQ_PendSV             ; Load address of IRQ_PendSV flag\n                LDRB    R3, [R2]                    ; Load PendSV flag\n\n                CMP     R0, R1                      ; Check if context switch is required\n                BNE     osRtxContextCheck           ; Not equal, check if context save required\n                CMP     R3, #1                      ; Compare IRQ_PendSV value\n                BNE     osRtxContextExit            ; No post processing (and no context switch requested)\n\nosRtxContextCheck\n                STR     R1, [R12]                   ; Store run.next as run.curr\n                ; R0 = curr, R1 = next, R2 = &IRQ_PendSV, R12 = &osRtxInfo.thread.run\n                PUSH    {R0-R2, R12}\n\n                CMP     R0, #0                      ; Is osRtxInfo.thread.run.curr == 0\n                BEQ     osRtxPostProcess            ; Current deleted, skip context save\n\nosRtxContextSave\n                MOV     LR, R0                      ; Move &osRtxInfo.thread.run.curr to LR\n                MOV     R0, SP                      ; Move SP_svc into R0\n                ADD     R0, R0, #20                 ; Adjust SP_svc to R0 of the basic frame\n                SUB     SP, SP, #4\n                STM     SP, {SP}^                   ; Save SP_usr to current stack\n                POP     {R1}                        ; Pop SP_usr into R1\n\n                SUB     R1, R1, #64                 ; Adjust SP_usr to R4 of the basic frame\n                STMIA   R1!, {R4-R11}               ; Save R4-R11 to user stack\n                LDMIA   R0!, {R4-R8}                ; Load stacked R0-R3,R12 into R4-R8\n                STMIA   R1!, {R4-R8}                ; Store them to user stack\n                STM     R1, {LR}^                   ; Store LR_usr directly\n                ADD     R1, R1, #4                  ; Adjust user sp to PC\n                LDMIB   R0!, {R5-R6}                ; Load stacked PC, CPSR\n                STMIA   R1!, {R5-R6}                ; Store them to user stack\n\n                SUB     R1, R1, #64                 ; Adjust SP_usr to stacked R4\n\n                ; Check if VFP state need to be saved\n                MRC     p15, 0, R2, c1, c0, 2       ; VFP/NEON access enabled? (CPACR)\n                AND     R2, R2, #0x00F00000\n                CMP     R2, #0x00F00000\n                BNE     osRtxContextSave1           ; Continue, no VFP\n\n                VMRS    R2, FPSCR\n                STMDB   R1!, {R2,R12}               ; Push FPSCR, maintain 8-byte alignment\n\n                VSTMDB  R1!, {D0-D15}               ; Save D0-D15\n              #ifdef  __ARM_ADVANCED_SIMD__\n                VSTMDB  R1!, {D16-D31}              ; Save D16-D31\n              #endif\n\n                LDRB    R2, [LR, #TCB_SP_FRAME]     ; Load osRtxInfo.thread.run.curr frame info\n              #ifdef  __ARM_ADVANCED_SIMD__\n                ORR     R2, R2, #4                  ; NEON state\n              #else\n                ORR     R2, R2, #2                  ; VFP state\n              #endif\n                STRB    R2, [LR, #TCB_SP_FRAME]     ; Store VFP/NEON state\n\nosRtxContextSave1\n                STR     R1, [LR, #TCB_SP_OFS]       ; Store user sp to osRtxInfo.thread.run.curr\n\nosRtxPostProcess\n                ; RTX IRQ post processing check\n                POP     {R8-R11}                    ; Pop R8 = curr, R9 = next, R10 = &IRQ_PendSV, R11 = &osRtxInfo.thread.run\n                LDRB    R0, [R10]                   ; Load PendSV flag\n                CMP     R0, #1                      ; Compare PendSV value\n                BNE     osRtxContextRestore         ; Skip post processing if not pending\n\n                MOV     R4, SP                      ; Move SP_svc into R4\n                AND     R4, R4, #4                  ; Get stack adjustment to ensure 8-byte alignment\n                SUB     SP, SP, R4                  ; Adjust stack\n\n                ; Disable OS Tick\n                LDR     R5, =osRtxInfo              ; Load address of osRtxInfo\n                LDR     R5, [R5, #I_TICK_IRQN_OFS]  ; Load OS Tick irqn\n                MOV     R0, R5                      ; Set it as function parameter\n                BLX     IRQ_Disable                 ; Disable OS Tick interrupt\n                MOV     R6, #0                      ; Set PendSV clear value\n                B       osRtxPendCheck\nosRtxPendExec\n                STRB    R6, [R10]                   ; Clear PendSV flag\n                CPSIE   i                           ; Re-enable interrupts\n                BLX     osRtxPendSV_Handler         ; Post process pending objects\n                CPSID   i                           ; Disable interrupts\nosRtxPendCheck\n                LDR     R9, [R11, #4]               ; Load osRtxInfo.thread.run.next\n                STR     R9, [R11]                   ; Store run.next as run.curr\n                LDRB    R0, [R10]                   ; Load PendSV flag\n                CMP     R0, #1                      ; Compare PendSV value\n                BEQ     osRtxPendExec               ; Branch to PendExec if PendSV is set\n\n                ; Re-enable OS Tick\n                MOV     R0, R5                      ; Restore irqn as function parameter\n                BLX     IRQ_Enable                  ; Enable OS Tick interrupt\n\n                ADD     SP, SP, R4                  ; Restore stack adjustment\n\nosRtxContextRestore\n            #ifdef RTX_EXECUTION_ZONE\n                LDRB    R0, [R9, #TCB_ZONE_OFS]     ; Load osRtxInfo.thread.run.next: zone\n                CMP     R8, #0\n                BEQ     osRtxZoneSetup              ; Branch if running thread is deleted\n                LDRB    R1, [R8, #TCB_ZONE_OFS]     ; Load osRtxInfo.thread.run.curr: zone\n                CMP     R0, R1                      ; Check if next:zone == curr:zone\n                BEQ     osRtxContextRestoreFrame    ; Branch if zone has not changed\nosRtxZoneSetup\n                BL      osZoneSetup_Callback        ; Setup zone for next thread\n            #endif\n\nosRtxContextRestoreFrame\n                LDR     LR, [R8, #TCB_SP_OFS]       ; Load next osRtxThread_t.sp\n                LDRB    R2, [R8, #TCB_SP_FRAME]     ; Load next osRtxThread_t.stack_frame\n\n                ANDS    R2, R2, #0x6                ; Check stack frame for VFP context\n                MRC     p15, 0, R2, c1, c0, 2       ; Read CPACR\n                ANDEQ   R2, R2, #0xFF0FFFFF         ; VFP/NEON state not stacked, disable VFP/NEON\n                ORRNE   R2, R2, #0x00F00000         ; VFP/NEON state is stacked, enable VFP/NEON\n                MCR     p15, 0, R2, c1, c0, 2       ; Write CPACR\n                BEQ     osRtxContextRestore1        ; No VFP\n                ISB                                 ; Sync if VFP was enabled\n              #ifdef  __ARM_ADVANCED_SIMD__\n                VLDMIA  LR!, {D16-D31}              ; Restore D16-D31\n              #endif\n                VLDMIA  LR!, {D0-D15}               ; Restore D0-D15\n                LDR     R2, [LR]\n                VMSR    FPSCR, R2                   ; Restore FPSCR\n                ADD     LR, LR, #8                  ; Adjust sp pointer to R4\n\nosRtxContextRestore1\n                LDMIA   LR!, {R4-R11}               ; Restore R4-R11\n                ADD     R12, LR, #32                ; Adjust sp and save it into R12\n                PUSH    {R12}                       ; Push sp onto stack\n                LDM     SP, {SP}^                   ; Restore SP_usr directly\n                ADD     SP, SP, #4                  ; Adjust SP_svc\n                LDMIA   LR!, {R0-R3, R12}           ; Load user registers R0-R3,R12\n                STMIB   SP!, {R0-R3, R12}           ; Store them to SP_svc\n                LDM     LR, {LR}^                   ; Restore LR_usr directly\n                LDMIB   LR!, {R0-R1}                ; Load user registers PC,CPSR\n                ADD     SP, SP, #4\n                STMIB   SP!, {R0-R1}                ; Store them to SP_svc\n                SUB     SP, SP, #32                 ; Adjust SP_svc to stacked LR\n\nosRtxContextExit\n                POP     {PC}                        ; Return\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s",
    "content": ";/*\n; * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; * -----------------------------------------------------------------------------\n; *\n; * Project:     CMSIS-RTOS RTX\n; * Title:       ARMv7-M Exception handlers\n; *\n; * -----------------------------------------------------------------------------\n; */\n\n\n                NAME     irq_armv7m.s\n\n\n                #include \"rtx_def.h\"\n\n#ifdef __ARMVFP__\nFPU_USED        EQU      1\n#else\nFPU_USED        EQU      0\n#endif\n\nI_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset\nTCB_SP_OFS      EQU      56                     ; TCB.SP offset\nTCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset\nTCB_ZONE_OFS    EQU      68                     ; TCB.zone offset\n\nFPCCR           EQU      0xE000EF34             ; FPCCR Address\n\nosRtxErrorStackOverflow\\\n                EQU      1                      ; Stack overflow\nosRtxErrorSVC   EQU      6                      ; Invalid SVC function called\n\n\n                PRESERVE8\n                SECTION .rodata:DATA:NOROOT(2)\n\n\n                EXPORT   irqRtxLib\nirqRtxLib       DCB      0                      ; Non weak library reference\n\n\n                THUMB\n                SECTION .text:CODE:NOROOT(2)\n\n\nSVC_Handler\n                EXPORT   SVC_Handler\n                IMPORT   osRtxUserSVC\n                IMPORT   osRtxInfo\n            #ifdef RTX_STACK_CHECK\n                IMPORT   osRtxThreadStackCheck\n                IMPORT   osRtxKernelErrorNotify\n            #endif\n            #ifdef RTX_SVC_PTR_CHECK\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Base|\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Length|\n                IMPORT   osRtxKernelErrorNotify\n            #endif\n            #ifdef RTX_EXECUTION_ZONE\n                IMPORT   osZoneSetup_Callback\n            #endif\n\n                TST      LR,#0x04               ; Determine return stack from EXC_RETURN bit 2\n                ITE      EQ\n                MRSEQ    R0,MSP                 ; Get MSP if return stack is MSP\n                MRSNE    R0,PSP                 ; Get PSP if return stack is PSP\n\n                LDR      R1,[R0,#24]            ; Load saved PC from stack\n                LDRB     R1,[R1,#-2]            ; Load SVC number\n                CMP      R1,#0                  ; Check SVC number\n                BNE      SVC_User               ; Branch if not SVC 0\n\n            #ifdef RTX_SVC_PTR_CHECK\n\n                LDR      R12,[R0,#16]           ; Load function address from stack\n                SUB      R1,R12,#1              ; Clear T-bit of function address\n                LSLS     R2,R1,#30              ; Check if 4-byte aligned\n                BEQ      SVC_PtrBoundsCheck     ; Branch if address is aligned\n\nSVC_PtrInvalid\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                MOVS     R0,#osRtxErrorSVC      ; Parameter: code\n                MOV      R1,R12                 ; Parameter: object_id\n                BL       osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify\n                POP      {R12,LR}               ; Restore SP and EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\nSVC_PtrBoundsCheck\n                LDR      R2,=|Image$$RTX_SVC_VENEERS$$Base|\n                LDR      R3,=|Image$$RTX_SVC_VENEERS$$Length|\n                SUBS     R2,R1,R2               ; Subtract SVC table base address\n                CMP      R2,R3                  ; Compare with SVC table boundaries\n                BHS      SVC_PtrInvalid         ; Branch if address is out of bounds\n\n              #endif\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack\n                BLX      R12                    ; Call service function\n                POP      {R12,LR}               ; Restore SP and EXC_RETURN\n                STR      R0,[R12]               ; Store function return value\n\nSVC_Context\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run\n                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next\n                CMP      R1,R2                  ; Check if thread switch is required\n                IT       EQ\n                BXEQ     LR                     ; Exit when threads are the same\n\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n\n              #if (FPU_USED != 0)\n                CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted\nSVC_FP_LazyState\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                BNE      SVC_ContextRestore     ; Branch if not extended stack frame\n                LDR      R3,=FPCCR              ; FPCCR Address\n                LDR      R0,[R3]                ; Load FPCCR\n                BIC      R0,R0,#1               ; Clear LSPACT (Lazy state preservation)\n                STR      R0,[R3]                ; Store FPCCR\n                B        SVC_ContextRestore     ; Branch to context restore handling\n              #else\n                CBZ      R1,SVC_ContextRestore  ; Branch if running thread is deleted\n              #endif\n\nSVC_ContextSave\n            #ifdef RTX_STACK_CHECK\n                SUB      R12,R12,#32            ; Calculate SP: space for R4..R11\n              #if (FPU_USED != 0)\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                SUBEQ    R12,R12,#64            ;  Additional space for S16..S31\n                STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information\n              #endif\n                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP\n\n                PUSH     {R1,R2}                ; Save osRtxInfo.thread.run: curr & next\n                MOV      R0,R1                  ; Parameter: osRtxInfo.thread.run.curr\n                BL       osRtxThreadStackCheck  ; Check if thread stack is overrun\n                POP      {R1,R2}                ; Restore osRtxInfo.thread.run: curr & next\n                CBNZ     R0,SVC_ContextSaveRegs ; Branch when stack check is ok\n\n              #if (FPU_USED != 0)\n                MOV      R4,R1                  ; Assign osRtxInfo.thread.run.curr to R4\n              #endif\n                MOVS     R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id\n                BL       osRtxKernelErrorNotify      ; Call osRtxKernelErrorNotify\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS   ; Load address of osRtxInfo.thread.run\n                LDR      R2,[R3,#4]             ; Load osRtxInfo.thread.run: next\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n                MOVS     R1,#0                  ; Simulate deleted running thread\n              #if (FPU_USED != 0)\n                LDRSB    LR,[R4,#TCB_SF_OFS]    ; Load stack frame information\n                B        SVC_FP_LazyState       ; Branch to FP lazy state handling\n              #else\n                B        SVC_ContextRestore     ; Branch to context restore handling\n              #endif\n\nSVC_ContextSaveRegs\n                LDR      R12,[R1,#TCB_SP_OFS]   ; Load SP\n              #if (FPU_USED != 0)\n                LDRSB    LR, [R1,#TCB_SF_OFS]   ; Load stack frame information\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                VSTMIAEQ R12!,{S16-S31}         ;  Save VFP S16..S31\n              #endif\n                STM      R12,{R4-R11}           ; Save R4..R11\n            #else\n                STMDB    R12!,{R4-R11}          ; Save R4..R11\n              #if (FPU_USED != 0)\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                VSTMDBEQ R12!,{S16-S31}         ;  Save VFP S16.S31\n                STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information\n              #endif\n                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP\n            #endif\n\nSVC_ContextRestore\n                 MOVS     R4,R2                 ; Assign osRtxInfo.thread.run.next to R4, clear Z flag\n            #ifdef RTX_EXECUTION_ZONE\n                 LDRB     R0,[R2,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.next: zone\n                 CBZ      R1,SVC_ZoneSetup      ; Branch if running thread is deleted (Z flag unchanged)\n                 LDRB     R1,[R1,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.curr: zone\n                 CMP      R0,R1                 ; Check if next:zone == curr:zone\n\nSVC_ZoneSetup\n                 IT       NE                    ; If zone has changed or running thread is deleted\n                 BLNE     osZoneSetup_Callback  ;  Setup zone for next thread\n            #endif\n\n                LDR      R0,[R4,#TCB_SP_OFS]    ; Load SP\n              #if (FPU_USED != 0)\n                LDRSB    LR,[R4,#TCB_SF_OFS]    ; Load stack frame information\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31\n              #else\n                MVN      LR,#~0xFFFFFFFD        ; Set EXC_RETURN value\n              #endif\n                LDMIA    R0!,{R4-R11}           ; Restore R4..R11\n                MSR      PSP,R0                 ; Set PSP\n\nSVC_Exit\n                BX       LR                     ; Exit from handler\n\nSVC_User\n                LDR      R2,=osRtxUserSVC       ; Load address of SVC table\n                LDR      R3,[R2]                ; Load SVC maximum number\n                CMP      R1,R3                  ; Check SVC number range\n                BHI      SVC_Exit               ; Branch if out of range\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LDR      R12,[R2,R1,LSL #2]     ; Load address of SVC function\n                LDM      R0,{R0-R3}             ; Load function parameters from stack\n                BLX      R12                    ; Call service function\n                POP      {R12,LR}               ; Restore SP and EXC_RETURN\n                STR      R0,[R12]               ; Store function return value\n\n                BX       LR                     ; Return from handler\n\n\nPendSV_Handler\n                EXPORT   PendSV_Handler\n                IMPORT   osRtxPendSV_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler\n                POP      {R0,LR}                ; Restore EXC_RETURN\n                MRS      R12,PSP                ; Save PSP to R12\n                B        SVC_Context            ; Branch to context handling\n\n\nSysTick_Handler\n                EXPORT   SysTick_Handler\n                IMPORT   osRtxTick_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxTick_Handler      ; Call osRtxTick_Handler\n                POP      {R0,LR}                ; Restore EXC_RETURN\n                MRS      R12,PSP                ; Save PSP to R12\n                B        SVC_Context            ; Branch to context handling\n\n\n            #ifdef RTX_SAFETY_FEATURES\n\nosFaultResume   PROC\n                EXPORT   osFaultResume\n\n                MRS      R12,PSP                ; Save PSP to R12\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n            #endif\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl.s",
    "content": ";/*\n; * Copyright (c) 2016-2023 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; * -----------------------------------------------------------------------------\n; *\n; * Project:     CMSIS-RTOS RTX\n; * Title:       ARMv8-M Baseline Exception handlers\n; *\n; * -----------------------------------------------------------------------------\n; */\n\n\n                NAME     irq_armv8mbl.s\n\n\n                #include \"rtx_def.h\"\n\nI_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset\nTCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset\nTCB_SP_OFS      EQU      56                     ; TCB.SP offset\nTCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset\nTCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset\nTCB_ZONE_OFS    EQU      68                     ; TCB.zone offset\n\nosRtxErrorStackOverflow\\\n                EQU      1                      ; Stack overflow\nosRtxErrorSVC   EQU      6                      ; Invalid SVC function called\n\n\n                PRESERVE8\n\n\n                SECTION  .rodata:DATA:NOROOT(2)\n                EXPORT   irqRtxLib\nirqRtxLib       DCB      0                      ; Non weak library reference\n\n\n                SECTION  .text:CODE:NOROOT(2)\n                THUMB\n\n\nSVC_Handler\n                EXPORT   SVC_Handler\n                IMPORT   osRtxUserSVC\n                IMPORT   osRtxInfo\n            #ifdef RTX_STACK_CHECK\n                IMPORT   osRtxThreadStackCheck\n                IMPORT   osRtxKernelErrorNotify\n            #endif\n            #ifdef RTX_SVC_PTR_CHECK\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Base|\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Length|\n                IMPORT   osRtxKernelErrorNotify\n            #endif\n            #ifdef RTX_EXECUTION_ZONE\n                IMPORT   osZoneSetup_Callback\n            #endif\n            #ifdef RTX_TZ_CONTEXT\n                IMPORT   TZ_LoadContext_S\n                IMPORT   TZ_StoreContext_S\n            #endif\n\n                MOV      R0,LR\n                LSRS     R0,R0,#3               ; Determine return stack from EXC_RETURN bit 2\n                BCC      SVC_MSP                ; Branch if return stack is MSP\n                MRS      R0,PSP                 ; Get PSP\n\nSVC_Number\n                LDR      R1,[R0,#24]            ; Load saved PC from stack\n                SUBS     R1,R1,#2               ; Point to SVC instruction\n                LDRB     R1,[R1]                ; Load SVC number\n                CMP      R1,#0                  ; Check SVC number\n                BNE      SVC_User               ; Branch if not SVC 0\n\n            #ifdef RTX_SVC_PTR_CHECK\n\n                SUBS     R1,R7,#0x01            ; Clear T-bit of function address\n                LSLS     R2,R1,#29              ; Check if 8-byte aligned\n                BEQ      SVC_PtrBoundsCheck     ; Branch if address is aligned\n\nSVC_PtrInvalid\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                MOVS     R0,#osRtxErrorSVC      ; Parameter: code\n                MOV      R1,R7                  ; Parameter: object_id\n                BL       osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify\n                POP      {R2,R3}                ; Restore SP and EXC_RETURN\n                MOV      LR,R3                  ; Set EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\nSVC_PtrBoundsCheck\n                LDR      R2,=|Image$$RTX_SVC_VENEERS$$Base|\n                LDR      R3,=|Image$$RTX_SVC_VENEERS$$Length|\n                SUBS     R2,R1,R2               ; Subtract SVC table base address\n                CMP      R2,R3                  ; Compare with SVC table boundaries\n                BHS      SVC_PtrInvalid         ; Branch if address is out of bounds\n\n              #endif\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LDMIA    R0,{R0-R3}             ; Load function parameters from stack\n                BLX      R7                     ; Call service function\n                POP      {R2,R3}                ; Restore SP and EXC_RETURN\n                STR      R0,[R2]                ; Store function return value\n                MOV      LR,R3                  ; Set EXC_RETURN\n\nSVC_Context\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run\n                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next\n                CMP      R1,R2                  ; Check if thread switch is required\n                BEQ      SVC_Exit               ; Branch when threads are the same\n\n                SUBS     R3,R3,#8               ; Adjust address\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n                CBZ      R1,SVC_ContextRestore  ; Branch if running thread is deleted\n\nSVC_ContextSave\n            #ifdef RTX_TZ_CONTEXT\n                MOV      R3,LR                  ; Get EXC_RETURN\n                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier\n                CBZ      R0,SVC_ContextSave_NS  ; Branch if there is no secure context\n                PUSH     {R0-R3}                ; Save registers\n                BL       TZ_StoreContext_S      ; Store secure context\n                POP      {R0-R3}                ; Restore registers\n                MOV      LR,R3                  ; Set EXC_RETURN\n            #endif\n\nSVC_ContextSave_NS\n                MRS      R0,PSP                 ; Get PSP\n            #if (DOMAIN_NS != 0)\n                MOV      R3,LR                  ; Get EXC_RETURN\n                LSLS     R3,R3,#25              ; Check domain of interrupted thread\n                BMI      SVC_ContextSaveSP      ; Branch if secure\n            #endif\n\n            #ifdef RTX_STACK_CHECK\n                SUBS     R0,R0,#32              ; Calculate SP: space for R4..R11\n\nSVC_ContextSaveSP\n                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP\n                MOV      R3,LR                  ; Get EXC_RETURN\n                MOVS     R0,#TCB_SF_OFS         ; Get TCB.stack_frame offset\n                STRB     R3,[R1,R0]             ; Store stack frame information\n\n                PUSH     {R1,R2}                ; Save osRtxInfo.thread.run: curr & next\n                MOV      R0,R1                  ; Parameter: osRtxInfo.thread.run.curr\n                BL       osRtxThreadStackCheck  ; Check if thread stack is overrun\n                POP      {R1,R2}                ; Restore osRtxInfo.thread.run: curr & next\n                CBNZ     R0,SVC_ContextSaveRegs ; Branch when stack check is ok\n\n                MOVS     R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id\n                BL       osRtxKernelErrorNotify      ; Call osRtxKernelErrorNotify\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS   ; Load address of osRtxInfo.thread.run\n                LDR      R2,[R3,#4]             ; Load osRtxInfo.thread.run: next\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n                MOVS     R1,#0                  ; Simulate deleted running thread\n                B        SVC_ContextRestore     ; Branch to context restore handling\n\nSVC_ContextSaveRegs\n              #if (DOMAIN_NS != 0)\n                MOVS     R0,#TCB_SF_OFS         ; Get TCB.stack_frame offset\n                LDRSB    R3,[R1,R0]             ; Load stack frame information\n                LSLS     R3,R3,#25              ; Check domain of interrupted thread\n                BMI      SVC_ContextRestore     ; Branch if secure\n              #endif\n                LDR      R0,[R1,#TCB_SP_OFS]    ; Load SP\n                STMIA    R0!,{R4-R7}            ; Save R4..R7\n                MOV      R4,R8\n                MOV      R5,R9\n                MOV      R6,R10\n                MOV      R7,R11\n                STMIA    R0!,{R4-R7}            ; Save R8..R11\n            #else\n                SUBS     R0,R0,#32              ; Calculate SP: space for R4..R11\n                STMIA    R0!,{R4-R7}            ; Save R4..R7\n                MOV      R4,R8\n                MOV      R5,R9\n                MOV      R6,R10\n                MOV      R7,R11\n                STMIA    R0!,{R4-R7}            ; Save R8..R11\n                SUBS     R0,R0,#32              ; Adjust address\nSVC_ContextSaveSP\n                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP\n                MOV      R3,LR                  ; Get EXC_RETURN\n                MOVS     R0,#TCB_SF_OFS         ; Get TCB.stack_frame offset\n                STRB     R3,[R1,R0]             ; Store stack frame information\n            #endif\n\nSVC_ContextRestore\n                 MOVS     R4,R2                 ; Assign osRtxInfo.thread.run.next to R4\n            #ifdef RTX_EXECUTION_ZONE\n                 MOVS     R3,#TCB_ZONE_OFS      ; Get TCB.zone offset\n                 LDRB     R0,[R2,R3]            ; Load osRtxInfo.thread.run.next: zone\n                 CBZ      R1,SVC_ZoneSetup      ; Branch if running thread is deleted\n                 LDRB     R1,[R1,R3]            ; Load osRtxInfo.thread.run.curr: zone\n                 CMP      R0,R1                 ; Check if next:zone == curr:zone\n                 BEQ      SVC_ContextRestore_S  ; Branch if zone has not changed\n\nSVC_ZoneSetup\n                 BL     osZoneSetup_Callback    ;  Setup zone for next thread\n            #endif\n\nSVC_ContextRestore_S\n            #ifdef RTX_TZ_CONTEXT\n                LDR      R0,[R4,#TCB_TZM_OFS]   ; Load TrustZone memory identifier\n                CBZ      R0,SVC_ContextRestore_NS ; Branch if there is no secure context\n                BL       TZ_LoadContext_S       ; Load secure context\n            #endif\n\nSVC_ContextRestore_NS\n                LDR      R0,[R4,#TCB_SM_OFS]    ; Load stack memory base\n                MSR      PSPLIM,R0              ; Set PSPLIM\n                MOVS     R0,#TCB_SF_OFS         ; Get TCB.stack_frame offset\n                LDRSB    R3,[R4,R0]             ; Load stack frame information\n                MOV      LR,R3                  ; Set EXC_RETURN\n                LDR      R0,[R4,#TCB_SP_OFS]    ; Load SP\n            #if (DOMAIN_NS != 0)\n                LSLS     R3,R3,#25              ; Check domain of interrupted thread\n                BMI      SVC_ContextRestoreSP   ; Branch if secure\n            #endif\n                ADDS     R0,R0,#16              ; Adjust address\n                LDMIA    R0!,{R4-R7}            ; Restore R8..R11\n                MOV      R8,R4\n                MOV      R9,R5\n                MOV      R10,R6\n                MOV      R11,R7\n                SUBS     R0,R0,#32              ; Adjust address\n                LDMIA    R0!,{R4-R7}            ; Restore R4..R7\n                ADDS     R0,R0,#16              ; Adjust address\n\nSVC_ContextRestoreSP\n                MSR      PSP,R0                 ; Set PSP\n\nSVC_Exit\n                BX       LR                     ; Exit from handler\n\nSVC_MSP\n                MRS      R0,MSP                 ; Get MSP\n                B        SVC_Number\n\nSVC_User\n                LDR      R2,=osRtxUserSVC       ; Load address of SVC table\n                LDR      R3,[R2]                ; Load SVC maximum number\n                CMP      R1,R3                  ; Check SVC number range\n                BHI      SVC_Exit               ; Branch if out of range\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LSLS     R1,R1,#2\n                LDR      R3,[R2,R1]             ; Load address of SVC function\n                MOV      R12,R3\n                LDMIA    R0,{R0-R3}             ; Load function parameters from stack\n                BLX      R12                    ; Call service function\n                POP      {R2,R3}                ; Restore SP and EXC_RETURN\n                STR      R0,[R2]                ; Store function return value\n\n                BX       R3                     ; Return from handler\n\n\nPendSV_Handler\n                EXPORT   PendSV_Handler\n                IMPORT   osRtxPendSV_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler\n                POP      {R0,R1}                ; Restore EXC_RETURN\n                MOV      LR,R1                  ; Set EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\n\nSysTick_Handler\n                EXPORT   SysTick_Handler\n                IMPORT   osRtxTick_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxTick_Handler      ; Call osRtxTick_Handler\n                POP      {R0,R1}                ; Restore EXC_RETURN\n                MOV      LR,R1                  ; Set EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\n\n            #ifdef RTX_SAFETY_FEATURES\n\nosFaultResume   PROC\n                EXPORT   osFaultResume\n\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n            #endif\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml.s",
    "content": ";/*\n; * Copyright (c) 2016-2023 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; *\n; * -----------------------------------------------------------------------------\n; *\n; * Project:     CMSIS-RTOS RTX\n; * Title:       ARMv8-M Mainline Exception handlers\n; *\n; * -----------------------------------------------------------------------------\n; */\n\n\n                NAME     irq_armv8mml.s\n\n\n                #include \"rtx_def.h\"\n\n#ifdef __ARMVFP__\nFPU_USED        EQU      1\n#else\nFPU_USED        EQU      0\n#endif\n\n#if (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))\nMVE_USED        EQU      1\n#else\nMVE_USED        EQU      0\n#endif\n\nI_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset\nTCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset\nTCB_SP_OFS      EQU      56                     ; TCB.SP offset\nTCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset\nTCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset\nTCB_ZONE_OFS    EQU      68                     ; TCB.zone offset\n\nFPCCR           EQU      0xE000EF34             ; FPCCR Address\n\nosRtxErrorStackOverflow\\\n                EQU      1                      ; Stack overflow\nosRtxErrorSVC   EQU      6                      ; Invalid SVC function called\n\n\n                PRESERVE8\n\n\n                SECTION  .rodata:DATA:NOROOT(2)\n                EXPORT   irqRtxLib\nirqRtxLib       DCB      0                      ; Non weak library reference\n\n\n                SECTION  .text:CODE:NOROOT(2)\n                THUMB\n\n\nSVC_Handler\n                EXPORT   SVC_Handler\n                IMPORT   osRtxUserSVC\n                IMPORT   osRtxInfo\n            #ifdef RTX_STACK_CHECK\n                IMPORT   osRtxThreadStackCheck\n                IMPORT   osRtxKernelErrorNotify\n            #endif\n            #ifdef RTX_SVC_PTR_CHECK\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Base|\n                IMPORT   |Image$$RTX_SVC_VENEERS$$Length|\n                IMPORT   osRtxKernelErrorNotify\n            #endif\n            #ifdef RTX_EXECUTION_ZONE\n                IMPORT   osZoneSetup_Callback\n            #endif\n            #ifdef RTX_TZ_CONTEXT\n                IMPORT   TZ_LoadContext_S\n                IMPORT   TZ_StoreContext_S\n            #endif\n\n                TST      LR,#0x04               ; Determine return stack from EXC_RETURN bit 2\n                ITE      EQ\n                MRSEQ    R0,MSP                 ; Get MSP if return stack is MSP\n                MRSNE    R0,PSP                 ; Get PSP if return stack is PSP\n\n                LDR      R1,[R0,#24]            ; Load saved PC from stack\n                LDRB     R1,[R1,#-2]            ; Load SVC number\n                CMP      R1,#0                  ; Check SVC number\n                BNE      SVC_User               ; Branch if not SVC 0\n\n            #ifdef RTX_SVC_PTR_CHECK\n\n                LDR      R12,[R0,#16]           ; Load function address from stack\n                SUB      R1,R12,#1              ; Clear T-bit of function address\n                LSLS     R2,R1,#30              ; Check if 4-byte aligned\n                BEQ      SVC_PtrBoundsCheck     ; Branch if address is aligned\n\nSVC_PtrInvalid\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                MOVS     R0,#osRtxErrorSVC      ; Parameter: code\n                MOV      R1,R12                 ; Parameter: object_id\n                BL       osRtxKernelErrorNotify ; Call osRtxKernelErrorNotify\n                POP      {R12,LR}               ; Restore SP and EXC_RETURN\n                B        SVC_Context            ; Branch to context handling\n\nSVC_PtrBoundsCheck\n                LDR      R2,=|Image$$RTX_SVC_VENEERS$$Base|\n                LDR      R3,=|Image$$RTX_SVC_VENEERS$$Length|\n                SUBS     R2,R1,R2               ; Subtract SVC table base address\n                CMP      R2,R3                  ; Compare with SVC table boundaries\n                BHS      SVC_PtrInvalid         ; Branch if address is out of bounds\n\n              #endif\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LDM      R0,{R0-R3,R12}         ; Load function parameters and address from stack\n                BLX      R12                    ; Call service function\n                POP      {R12,LR}               ; Restore SP and EXC_RETURN\n                STR      R0,[R12]               ; Store function return value\n\nSVC_Context\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run\n                LDM      R3,{R1,R2}             ; Load osRtxInfo.thread.run: curr & next\n                CMP      R1,R2                  ; Check if thread switch is required\n                IT       EQ\n                BXEQ     LR                     ; Exit when threads are the same\n\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n\n              #if ((FPU_USED != 0) || (MVE_USED != 0))\n                CBNZ     R1,SVC_ContextSave     ; Branch if running thread is not deleted\nSVC_FP_LazyState\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                BNE      SVC_ContextRestore     ; Branch if not extended stack frame\n                LDR      R3,=FPCCR              ; FPCCR Address\n                LDR      R0,[R3]                ; Load FPCCR\n                BIC      R0,R0,#1               ; Clear LSPACT (Lazy state preservation)\n                STR      R0,[R3]                ; Store FPCCR\n                B        SVC_ContextRestore     ; Branch to context restore handling\n              #else\n                CBZ      R1,SVC_ContextRestore  ; Branch if running thread is deleted\n              #endif\n\nSVC_ContextSave\n            #ifdef RTX_TZ_CONTEXT\n                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier\n                CBZ      R0,SVC_ContextSave_NS  ; Branch if there is no secure context\n                PUSH     {R1,R2,R12,LR}         ; Save registers and EXC_RETURN\n                BL       TZ_StoreContext_S      ; Store secure context\n                POP      {R1,R2,R12,LR}         ; Restore registers and EXC_RETURN\n            #endif\n\nSVC_ContextSave_NS\n            #if (DOMAIN_NS != 0)\n                TST      LR,#0x40               ; Check domain of interrupted thread\n                BNE      SVC_ContextSaveSP      ; Branch if secure\n            #endif\n\n            #ifdef RTX_STACK_CHECK\n                SUB      R12,R12,#32            ; Calculate SP: space for R4..R11\n              #if ((FPU_USED != 0) || (MVE_USED != 0))\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                SUBEQ    R12,R12,#64            ;  Additional space for S16..S31\n              #endif\n\nSVC_ContextSaveSP\n                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP\n                STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information\n\n                PUSH     {R1,R2}                ; Save osRtxInfo.thread.run: curr & next\n                MOV      R0,R1                  ; Parameter: osRtxInfo.thread.run.curr\n                BL       osRtxThreadStackCheck  ; Check if thread stack is overrun\n                POP      {R1,R2}                ; Restore osRtxInfo.thread.run: curr & next\n                CBNZ     R0,SVC_ContextSaveRegs ; Branch when stack check is ok\n\n              #if ((FPU_USED != 0) || (MVE_USED != 0))\n                MOV      R4,R1                  ; Assign osRtxInfo.thread.run.curr to R4\n              #endif\n                MOVS     R0,#osRtxErrorStackOverflow ; Parameter: r0=code, r1=object_id\n                BL       osRtxKernelErrorNotify      ; Call osRtxKernelErrorNotify\n                LDR      R3,=osRtxInfo+I_T_RUN_OFS   ; Load address of osRtxInfo.thread.run\n                LDR      R2,[R3,#4]             ; Load osRtxInfo.thread.run: next\n                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next\n                MOVS     R1,#0                  ; Simulate deleted running thread\n              #if ((FPU_USED != 0) || (MVE_USED != 0))\n                LDRSB    LR,[R4,#TCB_SF_OFS]    ; Load stack frame information\n                B        SVC_FP_LazyState       ; Branch to FP lazy state handling\n              #else\n                B        SVC_ContextRestore     ; Branch to context restore handling\n              #endif\n\nSVC_ContextSaveRegs\n                LDRSB    LR,[R1,#TCB_SF_OFS]    ; Load stack frame information\n              #if (DOMAIN_NS != 0)\n                TST      LR,#0x40               ; Check domain of interrupted thread\n                BNE      SVC_ContextRestore     ; Branch if secure\n              #endif\n                LDR      R12,[R1,#TCB_SP_OFS]   ; Load SP\n              #if ((FPU_USED != 0) || (MVE_USED != 0))\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                VSTMIAEQ R12!,{S16-S31}         ;  Save VFP S16..S31\n              #endif\n                STM      R12,{R4-R11}           ; Save R4..R11\n            #else\n                STMDB    R12!,{R4-R11}          ; Save R4..R11\n              #if ((FPU_USED != 0) || (MVE_USED != 0))\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                VSTMDBEQ R12!,{S16-S31}         ;  Save VFP S16.S31\n              #endif\n\nSVC_ContextSaveSP\n                STR      R12,[R1,#TCB_SP_OFS]   ; Store SP\n                STRB     LR, [R1,#TCB_SF_OFS]   ; Store stack frame information\n            #endif\n\nSVC_ContextRestore\n                 MOVS     R4,R2                 ; Assign osRtxInfo.thread.run.next to R4, clear Z flag\n            #ifdef RTX_EXECUTION_ZONE\n                 LDRB     R0,[R2,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.next: zone\n                 CBZ      R1,SVC_ZoneSetup      ; Branch if running thread is deleted (Z flag unchanged)\n                 LDRB     R1,[R1,#TCB_ZONE_OFS] ; Load osRtxInfo.thread.run.curr: zone\n                 CMP      R0,R1                 ; Check if next:zone == curr:zone\n\nSVC_ZoneSetup\n                 IT       NE                    ; If zone has changed or running thread is deleted\n                 BLNE     osZoneSetup_Callback  ;  Setup zone for next thread\n            #endif\n\n            #ifdef RTX_TZ_CONTEXT\n                LDR      R0,[R4,#TCB_TZM_OFS]   ; Load TrustZone memory identifier\n                CMP      R0,#0\n                IT       NE                     ; If TrustZone memory allocated\n                BLNE     TZ_LoadContext_S       ;  Load secure context\n            #endif\n\n                LDR      R0,[R4,#TCB_SP_OFS]    ; Load SP\n                LDR      R1,[R4,#TCB_SM_OFS]    ; Load stack memory base\n                MSR      PSPLIM,R1              ; Set PSPLIM\n                LDRSB    LR,[R4,#TCB_SF_OFS]    ; Load stack frame information\n\n            #if (DOMAIN_NS != 0)\n                TST      LR,#0x40               ; Check domain of interrupted thread\n                ITT      NE                     ; If secure\n                MSRNE    PSP,R0                 ;  Set PSP\n                BXNE     LR                     ;  Exit from handler\n            #endif\n\n              #if ((FPU_USED != 0) || (MVE_USED != 0))\n                TST      LR,#0x10               ; Determine stack frame from EXC_RETURN bit 4\n                IT       EQ                     ; If extended stack frame\n                VLDMIAEQ R0!,{S16-S31}          ;  Restore VFP S16..S31\n              #endif\n                LDMIA    R0!,{R4-R11}           ; Restore R4..R11\n                MSR      PSP,R0                 ; Set PSP\n\nSVC_Exit\n                BX       LR                     ; Exit from handler\n\nSVC_User\n                LDR      R2,=osRtxUserSVC       ; Load address of SVC table\n                LDR      R3,[R2]                ; Load SVC maximum number\n                CMP      R1,R3                  ; Check SVC number range\n                BHI      SVC_Exit               ; Branch if out of range\n\n                PUSH     {R0,LR}                ; Save SP and EXC_RETURN\n                LDR      R12,[R2,R1,LSL #2]     ; Load address of SVC function\n                LDM      R0,{R0-R3}             ; Load function parameters from stack\n                BLX      R12                    ; Call service function\n                POP      {R12,LR}               ; Restore SP and EXC_RETURN\n                STR      R0,[R12]               ; Store function return value\n\n                BX       LR                     ; Return from handler\n\n\nPendSV_Handler\n                EXPORT   PendSV_Handler\n                IMPORT   osRtxPendSV_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler\n                POP      {R0,LR}                ; Restore EXC_RETURN\n                MRS      R12,PSP                ; Save PSP to R12\n                B        SVC_Context            ; Branch to context handling\n\n\nSysTick_Handler\n                EXPORT   SysTick_Handler\n                IMPORT   osRtxTick_Handler\n\n                PUSH     {R0,LR}                ; Save EXC_RETURN\n                BL       osRtxTick_Handler      ; Call osRtxTick_Handler\n                POP      {R0,LR}                ; Restore EXC_RETURN\n                MRS      R12,PSP                ; Save PSP to R12\n                B        SVC_Context            ; Branch to context handling\n\n\n            #ifdef RTX_SAFETY_FEATURES\n\nosFaultResume   PROC\n                EXPORT   osFaultResume\n\n                MRS      R12,PSP                ; Save PSP to R12\n                B        SVC_Context            ; Branch to context handling\n\n                ALIGN\n                ENDP\n\n            #endif\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_core_c.h",
    "content": "/*\n * Copyright (c) 2013-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Cortex Core definitions\n *\n * -----------------------------------------------------------------------------\n */\n\n#ifndef RTX_CORE_C_H_\n#define RTX_CORE_C_H_\n\n//lint -emacro((923,9078),SCB) \"cast from unsigned long to pointer\" [MISRA Note 9]\n#ifndef RTE_COMPONENTS_H\n#include \"RTE_Components.h\"\n#endif\n#include CMSIS_device_header\n\n#if ((!defined(__ARM_ARCH_6M__))        && \\\n     (!defined(__ARM_ARCH_7A__))        && \\\n     (!defined(__ARM_ARCH_7M__))        && \\\n     (!defined(__ARM_ARCH_7EM__))       && \\\n     (!defined(__ARM_ARCH_8M_BASE__))   && \\\n     (!defined(__ARM_ARCH_8M_MAIN__))   && \\\n     (!defined(__ARM_ARCH_8_1M_MAIN__)))\n#error \"Unknown Arm Architecture!\"\n#endif\n\n#if   (defined(__ARM_ARCH_7A__) && (__ARM_ARCH_7A__ != 0))\n#include \"rtx_core_ca.h\"\n#else\n#include \"rtx_core_cm.h\"\n#endif\n\n#endif  // RTX_CORE_C_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_core_ca.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Cortex-A Core definitions\n *\n * -----------------------------------------------------------------------------\n */\n\n#ifndef RTX_CORE_CA_H_\n#define RTX_CORE_CA_H_\n\n#ifndef RTX_CORE_C_H_\n#ifndef RTE_COMPONENTS_H\n#include \"RTE_Components.h\"\n#endif\n#include CMSIS_device_header\n#endif\n#include \"irq_ctrl.h\"\n#include \"os_tick.h\"\n\n#include <stdbool.h>\ntypedef bool bool_t;\n\n#ifndef FALSE\n#define FALSE                   ((bool_t)0)\n#endif\n\n#ifndef TRUE\n#define TRUE                    ((bool_t)1)\n#endif\n\n#if defined(RTX_STACK_CHECK)\n#warning \"Stack overrun checking is not supported!\"\n#endif\n\n#define EXCLUSIVE_ACCESS        1\n\n#define OS_TICK_HANDLER         osRtxTick_Handler\n\n/// xPSR_Initialization Value\n/// \\param[in]  privileged      true=privileged, false=unprivileged\n/// \\param[in]  thumb           true=Thumb, false=Arm\n/// \\return                     xPSR Init Value\n__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) {\n  uint32_t psr;\n\n  if (privileged) {\n    if (thumb) {\n      psr = CPSR_M_SYS | CPSR_T_Msk;\n    } else {\n      psr = CPSR_M_SYS;\n    }\n  } else {\n    if (thumb) {\n      psr = CPSR_M_USR | CPSR_T_Msk;\n    } else {\n      psr = CPSR_M_USR;\n    }\n  }\n  \n  return psr;\n}\n\n// Stack Frame:\n//  - VFP-D32: D16-31, D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR\n//  - VFP-D16:         D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR\n//  - Basic:                                    R4-R11, R0-R3, R12, LR, PC, CPSR\n\n/// Stack Frame Initialization Value\n#define STACK_FRAME_INIT_VAL    0x00U\n\n/// Stack Offset of Register R0\n/// \\param[in]  stack_frame     Stack Frame\n/// \\return                     R0 Offset\n__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) {\n  uint32_t offset;\n\n  if        ((stack_frame & 0x04U) != 0U) {\n    offset = (32U*8U) + (2U*4U) + (8U*4U);\n  } else if ((stack_frame & 0x02U) != 0U) {\n    offset = (16U*8U) + (2U*4U) + (8U*4U);\n  } else {\n    offset =                      (8U*4U);\n  }\n  return offset;\n}\n\n\n//  ==== Emulated Cortex-M functions ====\n\n/// Get xPSR Register - emulate M profile: SP_usr - (8*4)\n/// \\return      xPSR Register value\n#if defined(__CC_ARM)\n#pragma push\n#pragma arm\nstatic __asm    uint32_t __get_PSP (void) {\n  sub   sp, sp, #4\n  stm   sp, {sp}^\n  pop   {r0}\n  sub   r0, r0, #32\n  bx    lr\n}\n#pragma pop\n#else\n#ifdef __ICCARM__\n__arm\n#else\n__attribute__((target(\"arm\")))\n#endif\n__STATIC_INLINE uint32_t __get_PSP (void) {\n  register uint32_t ret;\n\n  __ASM volatile (\n    \"sub  sp,sp,#4\\n\\t\"\n    \"stm  sp,{sp}^\\n\\t\"\n    \"pop  {%[ret]}\\n\\t\"\n    \"sub  %[ret],%[ret],#32\\n\\t\"\n    : [ret] \"=&l\" (ret)\n    :\n    : \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n\nextern uint8_t SVC_Active;      // SVC Handler Active\nextern uint8_t IRQ_PendSV;      // Pending SVC flag\n\n\n//  ==== Core functions ====\n\n/// Check if running Privileged\n/// \\return     true=privileged, false=unprivileged\n__STATIC_INLINE bool_t IsPrivileged (void) {\n  return (__get_mode() != CPSR_M_USR);\n}\n\n/// Set thread Privileged mode (not needed on Cortex-A)\n/// \\param[in]  privileged      true=privileged, false=unprivileged\n__STATIC_INLINE void SetPrivileged (bool_t privileged) {\n  (void)privileged;\n}\n\n/// Check if in Exception\n/// \\return     true=exception, false=thread\n__STATIC_INLINE bool_t IsException (void) {\n  return ((__get_mode() != CPSR_M_USR) && (__get_mode() != CPSR_M_SYS));\n}\n\n/// Check if in Fault\n/// \\return     true, false\n__STATIC_INLINE bool_t IsFault (void) {\n  return ((__get_mode() == CPSR_M_ABT) || (__get_mode() == CPSR_M_UND));\n}\n\n/// Check if in SVCall IRQ\n/// \\return     true, false\n__STATIC_INLINE bool_t IsSVCallIrq (void) {\n  return (SVC_Active != 0U);\n}\n\n/// Check if in PendSV IRQ\n/// \\return     true, false\n__STATIC_INLINE bool_t IsPendSvIrq (void) {\n  return ((__get_mode() == CPSR_M_SVC) && (SVC_Active == 0U) && (IRQ_PendSV != 0U));\n}\n\n/// Check if in Tick Timer IRQ\n/// \\return     true, false\n__STATIC_INLINE bool_t IsTickIrq (int32_t tick_irqn) {\n  return ((__get_mode() == CPSR_M_SVC) && (IRQ_GetActiveIRQ() == OS_Tick_GetIRQn()));\n}\n\n/// Check if IRQ is Masked\n/// \\return     true=masked, false=not masked\n__STATIC_INLINE bool_t IsIrqMasked (void) {\n  return  FALSE;\n}\n\n\n//  ==== Core Peripherals functions ====\n\n/// Setup SVC and PendSV System Service Calls (not needed on Cortex-A)\n__STATIC_INLINE void SVC_Setup (void) {\n}\n\n/// Get Pending SV (Service Call) Flag\n/// \\return     Pending SV Flag\n__STATIC_INLINE uint8_t GetPendSV (void) {\n  return (IRQ_PendSV);\n}\n\n/// Clear Pending SV (Service Call) Flag\n__STATIC_INLINE void ClrPendSV (void) {\n  IRQ_PendSV = 0U;\n}\n\n/// Set Pending SV (Service Call) Flag\n__STATIC_INLINE void SetPendSV (void) {\n  IRQ_PendSV = 1U;\n}\n\n\n//  ==== Service Calls definitions ====\n\n//lint -save -e9023 -e9024 -e9026 \"Function-like macros using '#/##'\" [MISRA Note 10]\n\n#if defined(RTX_SVC_PTR_CHECK)\n#warning \"SVC Function Pointer checking is not supported!\"\n#endif\n\n#if defined(__CC_ARM)\n\n#define SVC_INDIRECT(n) __svc_indirect(n)\n\n#define SVC0_0N(f,t)                                                           \\\nSVC_INDIRECT(0) t    svc##f (t(*)());                                          \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (void) {                                           \\\n  svc##f(svcRtx##f);                                                           \\\n}\n\n#define SVC0_0(f,t)                                                            \\\nSVC_INDIRECT(0) t    svc##f (t(*)());                                          \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (void) {                                           \\\n  return svc##f(svcRtx##f);                                                    \\\n}\n\n#define SVC0_1N(f,t,t1)                                                        \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1),t1);                                     \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1) {                                          \\\n  svc##f(svcRtx##f,a1);                                                        \\\n}\n\n#define SVC0_1(f,t,t1)                                                         \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1),t1);                                     \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1) {                                          \\\n  return svc##f(svcRtx##f,a1);                                                 \\\n}\n\n#define SVC0_2(f,t,t1,t2)                                                      \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1,t2),t1,t2);                               \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2) {                                   \\\n  return svc##f(svcRtx##f,a1,a2);                                              \\\n}\n\n#define SVC0_3(f,t,t1,t2,t3)                                                   \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1,t2,t3),t1,t2,t3);                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2, t3 a3) {                            \\\n  return svc##f(svcRtx##f,a1,a2,a3);                                           \\\n}\n\n#define SVC0_4(f,t,t1,t2,t3,t4)                                                \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4);                   \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                     \\\n  return svc##f(svcRtx##f,a1,a2,a3,a4);                                        \\\n}\n\n#elif defined(__ICCARM__)\n\n#define SVC_ArgF(f)                                                            \\\n  __asm(                                                                       \\\n    \"mov r12,%0\\n\"                                                             \\\n    :: \"r\"(&f): \"r12\"                                                          \\\n  );\n\n#define STRINGIFY(a) #a\n#define SVC_INDIRECT(n) _Pragma(STRINGIFY(svc_number = n)) __svc\n\n#define SVC0_0N(f,t)                                                           \\\nSVC_INDIRECT(0) t    svc##f ();                                                \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (void) {                                           \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  svc##f();                                                                    \\\n}\n\n#define SVC0_0(f,t)                                                            \\\nSVC_INDIRECT(0) t    svc##f ();                                                \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (void) {                                           \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f();                                                             \\\n}\n\n#define SVC0_1N(f,t,t1)                                                        \\\nSVC_INDIRECT(0) t    svc##f (t1 a1);                                           \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1) {                                          \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  svc##f(a1);                                                                  \\\n}\n\n#define SVC0_1(f,t,t1)                                                         \\\nSVC_INDIRECT(0) t    svc##f (t1 a1);                                           \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1) {                                          \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f(a1);                                                           \\\n}\n\n#define SVC0_2(f,t,t1,t2)                                                      \\\nSVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2);                                    \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2) {                                   \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f(a1,a2);                                                        \\\n}\n\n#define SVC0_3(f,t,t1,t2,t3)                                                   \\\nSVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2, t3 a3);                             \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2, t3 a3) {                            \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f(a1,a2,a3);                                                     \\\n}\n\n#define SVC0_4(f,t,t1,t2,t3,t4)                                                \\\nSVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2, t3 a3, t4 a4);                      \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                     \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f(a1,a2,a3,a4);                                                  \\\n}\n\n#else   // !(defined(__CC_ARM) || defined(__ICCARM__))\n\n#define SVC_RegF \"r12\"\n\n#define SVC_ArgN(n) \\\nregister uint32_t __r##n __ASM(\"r\"#n)\n\n#define SVC_ArgR(n,a) \\\nregister uint32_t __r##n __ASM(\"r\"#n) = (uint32_t)a\n\n#if    (defined(RTX_SVC_PTR_CHECK) && !defined(_lint))\n#define SVC_ArgF(f) \\\nregister uint32_t __rf   __ASM(SVC_RegF) = (uint32_t)jmpRtx##f\n#else\n#define SVC_ArgF(f) \\\nregister uint32_t __rf   __ASM(SVC_RegF) = (uint32_t)svcRtx##f\n#endif\n\n#define SVC_In0 \"r\"(__rf)\n#define SVC_In1 \"r\"(__rf),\"r\"(__r0)\n#define SVC_In2 \"r\"(__rf),\"r\"(__r0),\"r\"(__r1)\n#define SVC_In3 \"r\"(__rf),\"r\"(__r0),\"r\"(__r1),\"r\"(__r2)\n#define SVC_In4 \"r\"(__rf),\"r\"(__r0),\"r\"(__r1),\"r\"(__r2),\"r\"(__r3)\n\n#define SVC_Out0\n#define SVC_Out1 \"=r\"(__r0)\n\n#define SVC_CL0\n#define SVC_CL1 \"r0\"\n\n#define SVC_Call0(in, out, cl)                                                 \\\n  __ASM volatile (\"svc 0\" : out : in : cl)\n\n#if    (defined(RTX_SVC_PTR_CHECK) && !defined(_lint))\n#define SVC_Jump(f)                                                            \\\n  __ASM volatile (                                                             \\\n    \".align 2\\n\\t\"                                                             \\\n    \"b.w %[adr]\" : : [adr] \"X\" (f)                                             \\\n  )\n#define SVC_Veneer_Prototye(f)                                                 \\\n__STATIC_INLINE void jmpRtx##f (void);\n#define SVC_Veneer_Function(f)                                                 \\\n__attribute__((naked,section(\".text.os.svc.veneer.\"#f)))                       \\\n__STATIC_INLINE void jmpRtx##f (void) {                                        \\\n  SVC_Jump(svcRtx##f);                                                         \\\n}\n#else\n#define SVC_Veneer_Prototye(f)\n#define SVC_Veneer_Function(f)\n#endif\n\n#define SVC0_0N(f,t)                                                           \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (void) {                                            \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In0, SVC_Out0, SVC_CL1);                                       \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_0(f,t)                                                            \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (void) {                                            \\\n  SVC_ArgN(0);                                                                 \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In0, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_1N(f,t,t1)                                                        \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1) {                                           \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0);                                       \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_1(f,t,t1)                                                         \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1) {                                           \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_2(f,t,t1,t2)                                                      \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1, t2 a2) {                                    \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgR(1,a2);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_3(f,t,t1,t2,t3)                                                   \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) {                             \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgR(1,a2);                                                              \\\n  SVC_ArgR(2,a3);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_4(f,t,t1,t2,t3,t4)                                                \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                      \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgR(1,a2);                                                              \\\n  SVC_ArgR(2,a3);                                                              \\\n  SVC_ArgR(3,a4);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#endif\n\n//lint -restore [MISRA Note 10]\n\n\n//  ==== Exclusive Access Operation ====\n\n#if (EXCLUSIVE_ACCESS == 1)\n\n//lint ++flb \"Library Begin\" [MISRA Note 12]\n\n/// Atomic Access Operation: Write (8-bit)\n/// \\param[in]  mem             Memory address\n/// \\param[in]  val             Value to write\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {\n  mov    r2,r0\n1\n  ldrexb r0,[r2]\n  strexb r3,r1,[r2]\n  cmp    r3,#0\n  bne    %B1\n  bx     lr\n}\n#else\n__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint8_t  ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrexb %[ret],[%[mem]]\\n\\t\"\n    \"strexb %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp    %[res],#0\\n\\t\"\n    \"bne    1b\\n\\t\"\n  : [ret] \"=&l\" (ret),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem),\n    [val] \"l\"   (val)\n  : \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Set bits (32-bit)\n/// \\param[in]  mem             Memory address\n/// \\param[in]  bits            Bit mask\n/// \\return                     New value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  orr   r0,r0,r1\n  strex r3,r0,[r2]\n  cmp   r3,#0\n  bne   %B1\n  bx    lr\n}\n#else\n__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[val],[%[mem]]\\n\\t\"\n    \"orr   %[ret],%[val],%[bits]\\n\\t\"\n    \"strex %[res],%[ret],[%[mem]]\\n\\t\"\n    \"cmp   %[res],#0\\n\\t\"\n    \"bne   1b\\n\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [mem]  \"l\"   (mem),\n    [bits] \"l\"   (bits)\n  : \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Clear bits (32-bit)\n/// \\param[in]  mem             Memory address\n/// \\param[in]  bits            Bit mask\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {\n  push  {r4,lr}\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  bic   r4,r0,r1\n  strex r3,r4,[r2]\n  cmp   r3,#0\n  bne   %B1\n  pop   {r4,pc}\n}\n#else\n__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"bic   %[val],%[ret],%[bits]\\n\\t\"\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp   %[res],#0\\n\\t\"\n    \"bne   1b\\n\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [mem]  \"l\"   (mem),\n    [bits] \"l\"   (bits)\n  : \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them\n/// \\param[in]  mem             Memory address\n/// \\param[in]  bits            Bit mask\n/// \\return                     Active bits before clearing or 0 if not active\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {\n  push  {r4,lr}\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  and   r4,r0,r1\n  cmp   r4,r1\n  beq   %F2\n  clrex\n  movs  r0,#0\n  pop   {r4,pc}\n2\n  bic   r4,r0,r1\n  strex r3,r4,[r2]\n  cmp   r3,#0\n  bne   %B1\n  pop   {r4,pc}\n}\n#else\n__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"and   %[val],%[ret],%[bits]\\n\\t\"\n    \"cmp   %[val],%[bits]\\n\\t\"\n    \"beq   2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"movs  %[ret],#0\\n\\t\"\n    \"b     3f\\n\"\n  \"2:\\n\\t\"\n    \"bic   %[val],%[ret],%[bits]\\n\\t\"\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp   %[res],#0\\n\\t\"\n    \"bne   1b\\n\"\n  \"3:\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [mem]  \"l\"   (mem),\n    [bits] \"l\"   (bits)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them\n/// \\param[in]  mem             Memory address\n/// \\param[in]  bits            Bit mask\n/// \\return                     Active bits before clearing or 0 if not active\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {\n  push  {r4,lr}\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  tst   r0,r1\n  bne   %F2\n  clrex\n  movs  r0,#0\n  pop   {r4,pc}\n2\n  bic   r4,r0,r1\n  strex r3,r4,[r2]\n  cmp    r3,#0\n  bne   %B1\n  pop   {r4,pc}\n}\n#else\n__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"tst   %[ret],%[bits]\\n\\t\"\n    \"bne   2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"movs  %[ret],#0\\n\\t\"\n    \"b     3f\\n\"\n  \"2:\\n\\t\"\n    \"bic   %[val],%[ret],%[bits]\\n\\t\"\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp   %[res],#0\\n\\t\"\n    \"bne   1b\\n\"\n  \"3:\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [mem]  \"l\"   (mem),\n    [bits] \"l\"   (bits)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Increment (32-bit)\n/// \\param[in]  mem             Memory address\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_inc32 (uint32_t *mem) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  adds  r1,r0,#1\n  strex r3,r1,[r2]\n  cmp   r3,#0\n  bne   %B1\n  bx    lr\n}\n#else\n__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"adds  %[val],%[ret],#1\\n\\t\"\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp   %[res],#0\\n\\t\"\n    \"bne   1b\\n\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Increment (16-bit) if Less Than\n/// \\param[in]  mem             Memory address\n/// \\param[in]  max             Maximum value\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {\n  push   {r4,lr}\n  mov    r2,r0\n1\n  ldrexh r0,[r2]\n  cmp    r1,r0\n  bhi    %F2\n  clrex\n  pop    {r4,pc}\n2\n  adds   r4,r0,#1\n  strexh r3,r4,[r2]\n  cmp    r3,#0\n  bne    %B1\n  pop    {r4,pc}\n}\n#else\n__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint16_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrexh %[ret],[%[mem]]\\n\\t\"\n    \"cmp    %[max],%[ret]\\n\\t\"\n    \"bhi    2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"b      3f\\n\"\n  \"2:\\n\\t\"\n    \"adds   %[val],%[ret],#1\\n\\t\"\n    \"strexh %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp    %[res],#0\\n\\t\"\n    \"bne    1b\\n\"\n  \"3:\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem),\n    [max] \"l\"   (max)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Increment (16-bit) and clear on Limit\n/// \\param[in]  mem             Memory address\n/// \\param[in]  max             Maximum value\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {\n  push   {r4,lr}\n  mov    r2,r0\n1\n  ldrexh r0,[r2]\n  adds   r4,r0,#1\n  cmp    r1,r4\n  bhi    %F2\n  movs   r4,#0\n2\n  strexh r3,r4,[r2]\n  cmp    r3,#0\n  bne    %B1\n  pop    {r4,pc}\n}\n#else\n__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint16_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrexh %[ret],[%[mem]]\\n\\t\"\n    \"adds   %[val],%[ret],#1\\n\\t\"\n    \"cmp    %[lim],%[val]\\n\\t\"\n    \"bhi    2f\\n\\t\"\n    \"movs   %[val],#0\\n\"\n  \"2:\\n\\t\"\n    \"strexh %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp    %[res],#0\\n\\t\"\n    \"bne    1b\\n\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem),\n    [lim] \"l\"   (lim)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Decrement (32-bit)\n/// \\param[in]  mem             Memory address\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_dec32 (uint32_t *mem) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  subs  r1,r0,#1\n  strex r3,r1,[r2]\n  cmp   r3,#0\n  bne   %B1\n  bx    lr\n}\n#else\n__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"subs  %[val],%[ret],#1\\n\\t\"\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp   %[res],#0\\n\\t\"\n    \"bne   1b\\n\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Decrement (32-bit) if Not Zero\n/// \\param[in]  mem             Memory address\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_dec32_nz (uint32_t *mem) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  cmp   r0,#0\n  bne   %F2\n  clrex\n  bx    lr\n2\n  subs  r1,r0,#1\n  strex r3,r1,[r2]\n  cmp   r3,#0\n  bne   %B1\n  bx    lr\n}\n#else\n__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"cmp   %[ret],#0\\n\\t\"\n    \"bne   2f\\n\"\n    \"clrex\\n\\t\"\n    \"b     3f\\n\"\n  \"2:\\n\\t\"\n    \"subs  %[val],%[ret],#1\\n\\t\"\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp   %[res],#0\\n\\t\"\n    \"bne   1b\\n\"\n  \"3:\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Decrement (16-bit) if Not Zero\n/// \\param[in]  mem             Memory address\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint16_t atomic_dec16_nz (uint16_t *mem) {\n  mov    r2,r0\n1\n  ldrexh r0,[r2]\n  cmp    r0,#0\n  bne    %F2\n  clrex\n  bx     lr\n2\n  subs   r1,r0,#1\n  strexh r3,r1,[r2]\n  cmp    r3,#0\n  bne    %B1\n  bx      lr\n}\n#else\n__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint16_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrexh %[ret],[%[mem]]\\n\\t\"\n    \"cmp    %[ret],#0\\n\\t\"\n    \"bne    2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"b      3f\\n\"\n  \"2:\\n\\t\"\n    \"subs   %[val],%[ret],#1\\n\\t\"\n    \"strexh %[res],%[val],[%[mem]]\\n\\t\"\n    \"cmp    %[res],#0\\n\\t\"\n    \"bne    1b\\n\"\n  \"3:\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Link Get\n/// \\param[in]  root            Root address\n/// \\return                     Link\n#if defined(__CC_ARM)\nstatic __asm    void *atomic_link_get (void **root) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  cmp   r0,#0\n  bne   %F2\n  clrex\n  bx    lr\n2\n  ldr   r1,[r0]\n  strex r3,r1,[r2]\n  cmp   r3,#0\n  bne   %B1\n  bx    lr\n}\n#else\n__STATIC_INLINE void *atomic_link_get (void **root) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register void    *ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[root]]\\n\\t\"\n    \"cmp   %[ret],#0\\n\\t\"\n    \"bne   2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"b     3f\\n\"\n  \"2:\\n\\t\"\n    \"ldr   %[val],[%[ret]]\\n\\t\"\n    \"strex %[res],%[val],[%[root]]\\n\\t\"\n    \"cmp   %[res],#0\\n\\t\"\n    \"bne   1b\\n\"\n  \"3:\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [root] \"l\"   (root)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Link Put\n/// \\param[in]  root            Root address\n/// \\param[in]  lnk             Link\n#if defined(__CC_ARM)\nstatic __asm    void atomic_link_put (void **root, void *link) {\n1\n  ldr   r2,[r0]\n  str   r2,[r1]\n  dmb\n  ldrex r2,[r0]\n  ldr   r3,[r1]\n  cmp   r3,r2\n  bne   %B1\n  strex r3,r1,[r0]\n  cmp   r3,#0\n  bne   %B1\n  bx    lr\n}\n#else\n__STATIC_INLINE void atomic_link_put (void **root, void *link) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val1, val2, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldr   %[val1],[%[root]]\\n\\t\"\n    \"str   %[val1],[%[link]]\\n\\t\"\n    \"dmb\\n\\t\"\n    \"ldrex %[val1],[%[root]]\\n\\t\"\n    \"ldr   %[val2],[%[link]]\\n\\t\"\n    \"cmp   %[val2],%[val1]\\n\\t\"\n    \"bne   1b\\n\\t\"\n    \"strex %[res],%[link],[%[root]]\\n\\t\"\n    \"cmp   %[res],#0\\n\\t\"\n    \"bne   1b\\n\"\n  : [val1] \"=&l\" (val1),\n    [val2] \"=&l\" (val2),\n    [res]  \"=&l\" (res)\n  : [root] \"l\"   (root),\n    [link] \"l\"   (link)\n  : \"cc\", \"memory\"\n  );\n}\n#endif\n\n//lint --flb \"Library End\" [MISRA Note 12]\n\n#endif  // (EXCLUSIVE_ACCESS == 1)\n\n\n#endif  // RTX_CORE_CA_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_core_cm.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Cortex-M Core definitions\n *\n * -----------------------------------------------------------------------------\n */\n\n#ifndef RTX_CORE_CM_H_\n#define RTX_CORE_CM_H_\n\n#ifndef RTX_CORE_C_H_\n#ifndef RTE_COMPONENTS_H\n#include \"RTE_Components.h\"\n#endif\n#include CMSIS_device_header\n#endif\n\n#include <stdbool.h>\ntypedef bool bool_t;\n\n#ifndef FALSE\n#define FALSE                   ((bool_t)0)\n#endif\n\n#ifndef TRUE\n#define TRUE                    ((bool_t)1)\n#endif\n\n#ifndef EXCLUSIVE_ACCESS\n#if   ((defined(__ARM_ARCH_7M__)        && (__ARM_ARCH_7M__        != 0)) || \\\n       (defined(__ARM_ARCH_7EM__)       && (__ARM_ARCH_7EM__       != 0)) || \\\n       (defined(__ARM_ARCH_8M_BASE__)   && (__ARM_ARCH_8M_BASE__   != 0)) || \\\n       (defined(__ARM_ARCH_8M_MAIN__)   && (__ARM_ARCH_8M_MAIN__   != 0)) || \\\n       (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))\n#define EXCLUSIVE_ACCESS        1\n#else\n#define EXCLUSIVE_ACCESS        0\n#endif\n#endif\n\n#define OS_TICK_HANDLER         SysTick_Handler\n\n/// xPSR_Initialization Value\n/// \\param[in]  privileged      true=privileged, false=unprivileged\n/// \\param[in]  thumb           true=Thumb, false=ARM\n/// \\return                     xPSR Init Value\n__STATIC_INLINE uint32_t xPSR_InitVal (bool_t privileged, bool_t thumb) {\n  (void)privileged;\n  (void)thumb;\n  return (0x01000000U);\n}\n\n// Stack Frame:\n//  - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR\n//  - Basic:             R4-R11, R0-R3, R12, LR, PC, xPSR\n\n/// Stack Frame Initialization Value (EXC_RETURN[7..0])\n#if (DOMAIN_NS == 1)\n#define STACK_FRAME_INIT_VAL    0xBCU\n#else\n#define STACK_FRAME_INIT_VAL    0xFDU\n#endif\n\n/// Stack Offset of Register R0\n/// \\param[in]  stack_frame     Stack Frame (EXC_RETURN[7..0])\n/// \\return                     R0 Offset\n__STATIC_INLINE uint32_t StackOffsetR0 (uint8_t stack_frame) {\n#if ((__FPU_USED == 1U) || \\\n     (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0)))\n  return (((stack_frame & 0x10U) == 0U) ? ((16U+8U)*4U) : (8U*4U));\n#else\n  (void)stack_frame;\n  return (8U*4U);\n#endif\n}\n\n\n//  ==== Core functions ====\n\n//lint -sem(__get_CONTROL, pure)\n//lint -sem(__get_IPSR,    pure)\n//lint -sem(__get_PRIMASK, pure)\n//lint -sem(__get_BASEPRI, pure)\n\n/// Check if running Privileged\n/// \\return     true=privileged, false=unprivileged\n__STATIC_INLINE bool_t IsPrivileged (void) {\n  return ((__get_CONTROL() & 1U) == 0U);\n}\n\n/// Set thread Privileged mode\n/// \\param[in]  privileged      true=privileged, false=unprivileged\n__STATIC_INLINE void SetPrivileged (bool_t privileged) {\n  if (privileged) {\n    // Privileged Thread mode & PSP\n    __set_CONTROL(0x02U);\n  } else {\n    // Unprivileged Thread mode & PSP\n    __set_CONTROL(0x03U);\n  }\n}\n\n/// Check if in Exception\n/// \\return     true=exception, false=thread\n__STATIC_INLINE bool_t IsException (void) {\n  return (__get_IPSR() != 0U);\n}\n\n/// Check if in Fault\n/// \\return     true, false\n__STATIC_INLINE bool_t IsFault (void) {\n  uint32_t ipsr = __get_IPSR();\n  return (((int32_t)ipsr < ((int32_t)SVCall_IRQn + 16)) &&\n          ((int32_t)ipsr > ((int32_t)NonMaskableInt_IRQn + 16)));\n}\n\n/// Check if in SVCall IRQ\n/// \\return     true, false\n__STATIC_INLINE bool_t IsSVCallIrq (void) {\n  return ((int32_t)__get_IPSR() == ((int32_t)SVCall_IRQn + 16));\n}\n\n/// Check if in PendSV IRQ\n/// \\return     true, false\n__STATIC_INLINE bool_t IsPendSvIrq (void) {\n  return ((int32_t)__get_IPSR() == ((int32_t)PendSV_IRQn + 16));\n}\n\n/// Check if in Tick Timer IRQ\n/// \\return     true, false\n__STATIC_INLINE bool_t IsTickIrq (int32_t tick_irqn) {\n  return ((int32_t)__get_IPSR() == (tick_irqn + 16));\n}\n\n/// Check if IRQ is Masked\n/// \\return     true=masked, false=not masked\n__STATIC_INLINE bool_t IsIrqMasked (void) {\n#if   ((defined(__ARM_ARCH_7M__)        && (__ARM_ARCH_7M__        != 0)) || \\\n       (defined(__ARM_ARCH_7EM__)       && (__ARM_ARCH_7EM__       != 0)) || \\\n       (defined(__ARM_ARCH_8M_MAIN__)   && (__ARM_ARCH_8M_MAIN__   != 0)) || \\\n       (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))\n  return ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U));\n#else\n  return  (__get_PRIMASK() != 0U);\n#endif\n}\n\n\n//  ==== Core Peripherals functions ====\n\n/// Setup SVC and PendSV System Service Calls\n__STATIC_INLINE void SVC_Setup (void) {\n#if   ((defined(__ARM_ARCH_8M_MAIN__)   && (__ARM_ARCH_8M_MAIN__   != 0)) || \\\n       (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \\\n       (defined(__CORTEX_M)             && (__CORTEX_M == 7U)))\n  uint32_t p, n;\n\n  SCB->SHPR[10] = 0xFFU;\n  n = 32U - (uint32_t)__CLZ(~(SCB->SHPR[10] | 0xFFFFFF00U));\n  p = NVIC_GetPriorityGrouping();\n  if (p >= n) {\n    n = p + 1U;\n  }\n  SCB->SHPR[7] = (uint8_t)(0xFEU << n);\n#elif  (defined(__ARM_ARCH_8M_BASE__)   && (__ARM_ARCH_8M_BASE__   != 0))\n  uint32_t n;\n\n  SCB->SHPR[1] |= 0x00FF0000U;\n  n = SCB->SHPR[1];\n  SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U;\n#elif ((defined(__ARM_ARCH_7M__)        && (__ARM_ARCH_7M__        != 0)) || \\\n       (defined(__ARM_ARCH_7EM__)       && (__ARM_ARCH_7EM__       != 0)))\n  uint32_t p, n;\n\n  SCB->SHP[10] = 0xFFU;\n  n = 32U - (uint32_t)__CLZ(~(SCB->SHP[10] | 0xFFFFFF00U));\n  p = NVIC_GetPriorityGrouping();\n  if (p >= n) {\n    n = p + 1U;\n  }\n  SCB->SHP[7] = (uint8_t)(0xFEU << n);\n#elif  (defined(__ARM_ARCH_6M__)        && (__ARM_ARCH_6M__        != 0))\n  uint32_t n;\n\n  SCB->SHP[1] |= 0x00FF0000U;\n  n = SCB->SHP[1];\n  SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U;\n#endif\n}\n\n/// Get Pending SV (Service Call) Flag\n/// \\return     Pending SV Flag\n__STATIC_INLINE uint8_t GetPendSV (void) {\n  return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24));\n}\n\n/// Clear Pending SV (Service Call) Flag\n__STATIC_INLINE void ClrPendSV (void) {\n  SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk;\n}\n\n/// Set Pending SV (Service Call) Flag\n__STATIC_INLINE void SetPendSV (void) {\n  SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;\n}\n\n\n//  ==== Service Calls definitions ====\n\n//lint -save -e9023 -e9024 -e9026 \"Function-like macros using '#/##'\" [MISRA Note 10]\n\n#if defined(__CC_ARM)\n\n#if defined(RTX_SVC_PTR_CHECK)\n#warning \"SVC Function Pointer checking is not supported!\"\n#endif\n\n#if   ((defined(__ARM_ARCH_7M__)        && (__ARM_ARCH_7M__        != 0)) ||   \\\n       (defined(__ARM_ARCH_7EM__)       && (__ARM_ARCH_7EM__       != 0)) ||   \\\n       (defined(__ARM_ARCH_8M_MAIN__)   && (__ARM_ARCH_8M_MAIN__   != 0)) ||   \\\n       (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))\n#define SVC_INDIRECT(n) __svc_indirect(n)\n#elif ((defined(__ARM_ARCH_6M__)        && (__ARM_ARCH_6M__        != 0)) ||   \\\n       (defined(__ARM_ARCH_8M_BASE__)   && (__ARM_ARCH_8M_BASE__   != 0)))\n#define SVC_INDIRECT(n) __svc_indirect_r7(n)\n#endif\n\n#define SVC0_0N(f,t)                                                           \\\nSVC_INDIRECT(0) t    svc##f (t(*)());                                          \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (void) {                                           \\\n  svc##f(svcRtx##f);                                                           \\\n}\n\n#define SVC0_0(f,t)                                                            \\\nSVC_INDIRECT(0) t    svc##f (t(*)());                                          \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (void) {                                           \\\n  return svc##f(svcRtx##f);                                                    \\\n}\n\n#define SVC0_1N(f,t,t1)                                                        \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1),t1);                                     \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1) {                                          \\\n  svc##f(svcRtx##f,a1);                                                        \\\n}\n\n#define SVC0_1(f,t,t1)                                                         \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1),t1);                                     \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1) {                                          \\\n  return svc##f(svcRtx##f,a1);                                                 \\\n}\n\n#define SVC0_2(f,t,t1,t2)                                                      \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1,t2),t1,t2);                               \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2) {                                   \\\n  return svc##f(svcRtx##f,a1,a2);                                              \\\n}\n\n#define SVC0_3(f,t,t1,t2,t3)                                                   \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1,t2,t3),t1,t2,t3);                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2, t3 a3) {                            \\\n  return svc##f(svcRtx##f,a1,a2,a3);                                           \\\n}\n\n#define SVC0_4(f,t,t1,t2,t3,t4)                                                \\\nSVC_INDIRECT(0) t    svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4);                   \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                     \\\n  return svc##f(svcRtx##f,a1,a2,a3,a4);                                        \\\n}\n\n#elif defined(__ICCARM__)\n\n#if defined(RTX_SVC_PTR_CHECK)\n#warning \"SVC Function Pointer checking is not supported!\"\n#endif\n\n#if   ((defined(__ARM_ARCH_7M__)        && (__ARM_ARCH_7M__        != 0)) ||   \\\n       (defined(__ARM_ARCH_7EM__)       && (__ARM_ARCH_7EM__       != 0)) ||   \\\n       (defined(__ARM_ARCH_8M_MAIN__)   && (__ARM_ARCH_8M_MAIN__   != 0)) ||   \\\n       (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))\n#define SVC_ArgF(f)                                                            \\\n  __asm(                                                                       \\\n    \"mov r12,%0\\n\"                                                             \\\n    :: \"r\"(&f): \"r12\"                                                          \\\n  );\n#elif ((defined(__ARM_ARCH_6M__)        && (__ARM_ARCH_6M__        != 0)) ||   \\\n       (defined(__ARM_ARCH_8M_BASE__)   && (__ARM_ARCH_8M_BASE__   != 0)))\n#define SVC_ArgF(f)                                                            \\\n  __asm(                                                                       \\\n    \"mov r7,%0\\n\"                                                              \\\n    :: \"r\"(&f): \"r7\"                                                           \\\n  );\n#endif\n\n#define STRINGIFY(a) #a\n#define SVC_INDIRECT(n) _Pragma(STRINGIFY(svc_number = n)) __svc\n\n#define SVC0_0N(f,t)                                                           \\\nSVC_INDIRECT(0) t    svc##f ();                                                \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (void) {                                           \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  svc##f();                                                                    \\\n}\n\n#define SVC0_0(f,t)                                                            \\\nSVC_INDIRECT(0) t    svc##f ();                                                \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (void) {                                           \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f();                                                             \\\n}\n\n#define SVC0_1N(f,t,t1)                                                        \\\nSVC_INDIRECT(0) t    svc##f (t1 a1);                                           \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1) {                                          \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  svc##f(a1);                                                                  \\\n}\n\n#define SVC0_1(f,t,t1)                                                         \\\nSVC_INDIRECT(0) t    svc##f (t1 a1);                                           \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1) {                                          \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f(a1);                                                           \\\n}\n\n#define SVC0_2(f,t,t1,t2)                                                      \\\nSVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2);                                    \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2) {                                   \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f(a1,a2);                                                        \\\n}\n\n#define SVC0_3(f,t,t1,t2,t3)                                                   \\\nSVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2, t3 a3);                             \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2, t3 a3) {                            \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f(a1,a2,a3);                                                     \\\n}\n\n#define SVC0_4(f,t,t1,t2,t3,t4)                                                \\\nSVC_INDIRECT(0) t    svc##f (t1 a1, t2 a2, t3 a3, t4 a4);                      \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t  __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                     \\\n  SVC_ArgF(svcRtx##f);                                                         \\\n  return svc##f(a1,a2,a3,a4);                                                  \\\n}\n\n#else   // !(defined(__CC_ARM) || defined(__ICCARM__))\n\n//lint -esym(522,__svc*) \"Functions '__svc*' are impure (side-effects)\"\n\n#if   ((defined(__ARM_ARCH_7M__)        && (__ARM_ARCH_7M__        != 0)) ||   \\\n       (defined(__ARM_ARCH_7EM__)       && (__ARM_ARCH_7EM__       != 0)) ||   \\\n       (defined(__ARM_ARCH_8M_MAIN__)   && (__ARM_ARCH_8M_MAIN__   != 0)) ||   \\\n       (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))\n#define SVC_RegF \"r12\"\n#elif ((defined(__ARM_ARCH_6M__)        && (__ARM_ARCH_6M__        != 0)) ||   \\\n       (defined(__ARM_ARCH_8M_BASE__)   && (__ARM_ARCH_8M_BASE__   != 0)))\n#define SVC_RegF \"r7\"\n#endif\n\n#define SVC_ArgN(n) \\\nregister uint32_t __r##n __ASM(\"r\"#n)\n\n#define SVC_ArgR(n,a) \\\nregister uint32_t __r##n __ASM(\"r\"#n) = (uint32_t)a\n\n#if    (defined(RTX_SVC_PTR_CHECK) && !defined(_lint))\n#define SVC_ArgF(f) \\\nregister uint32_t __rf   __ASM(SVC_RegF) = (uint32_t)jmpRtx##f\n#else\n#define SVC_ArgF(f) \\\nregister uint32_t __rf   __ASM(SVC_RegF) = (uint32_t)svcRtx##f\n#endif\n\n#define SVC_In0 \"r\"(__rf)\n#define SVC_In1 \"r\"(__rf),\"r\"(__r0)\n#define SVC_In2 \"r\"(__rf),\"r\"(__r0),\"r\"(__r1)\n#define SVC_In3 \"r\"(__rf),\"r\"(__r0),\"r\"(__r1),\"r\"(__r2)\n#define SVC_In4 \"r\"(__rf),\"r\"(__r0),\"r\"(__r1),\"r\"(__r2),\"r\"(__r3)\n\n#define SVC_Out0\n#define SVC_Out1 \"=r\"(__r0)\n\n#define SVC_CL0\n#define SVC_CL1 \"r0\"\n\n#define SVC_Call0(in, out, cl)                                                 \\\n  __ASM volatile (\"svc 0\" : out : in : cl)\n\n#if    (defined(RTX_SVC_PTR_CHECK) && !defined(_lint))\n#if   ((defined(__ARM_ARCH_7M__)        && (__ARM_ARCH_7M__        != 0)) ||   \\\n       (defined(__ARM_ARCH_7EM__)       && (__ARM_ARCH_7EM__       != 0)) ||   \\\n       (defined(__ARM_ARCH_8M_MAIN__)   && (__ARM_ARCH_8M_MAIN__   != 0)) ||   \\\n       (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)))\n#define SVC_Jump(f)                                                            \\\n  __ASM volatile (                                                             \\\n    \".align 2\\n\\t\"                                                             \\\n    \"b.w %[adr]\" : : [adr] \"X\" (f)                                             \\\n  )\n#elif ((defined(__ARM_ARCH_6M__)        && (__ARM_ARCH_6M__        != 0)) ||   \\\n       (defined(__ARM_ARCH_8M_BASE__)   && (__ARM_ARCH_8M_BASE__   != 0)))\n#define SVC_Jump(f)                                                            \\\n  __ASM volatile (                                                             \\\n    \".align 3\\n\\t\"                                                             \\\n    \"ldr r7,1f\\n\\t\"                                                            \\\n    \"bx  r7\\n\"                                                                 \\\n    \"1: .word %[adr]\" : : [adr] \"X\" (f)                                        \\\n  )\n#endif\n#define SVC_Veneer_Prototye(f)                                                 \\\n__STATIC_INLINE void jmpRtx##f (void);\n#define SVC_Veneer_Function(f)                                                 \\\n__attribute__((naked,section(\".text.os.svc.veneer.\"#f)))                       \\\n__STATIC_INLINE void jmpRtx##f (void) {                                        \\\n  SVC_Jump(svcRtx##f);                                                         \\\n}\n#else\n#define SVC_Veneer_Prototye(f)\n#define SVC_Veneer_Function(f)\n#endif\n\n#define SVC0_0N(f,t)                                                           \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (void) {                                            \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In0, SVC_Out0, SVC_CL1);                                       \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_0(f,t)                                                            \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (void) {                                            \\\n  SVC_ArgN(0);                                                                 \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In0, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_1N(f,t,t1)                                                        \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1) {                                           \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0);                                       \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_1(f,t,t1)                                                         \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1) {                                           \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In1, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_2(f,t,t1,t2)                                                      \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1, t2 a2) {                                    \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgR(1,a2);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_3(f,t,t1,t2,t3)                                                   \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) {                             \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgR(1,a2);                                                              \\\n  SVC_ArgR(2,a3);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#define SVC0_4(f,t,t1,t2,t3,t4)                                                \\\nSVC_Veneer_Prototye(f)                                                         \\\n__attribute__((always_inline))                                                 \\\n__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) {                      \\\n  SVC_ArgR(0,a1);                                                              \\\n  SVC_ArgR(1,a2);                                                              \\\n  SVC_ArgR(2,a3);                                                              \\\n  SVC_ArgR(3,a4);                                                              \\\n  SVC_ArgF(f);                                                                 \\\n  SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0);                                       \\\n  return (t) __r0;                                                             \\\n}                                                                              \\\nSVC_Veneer_Function(f)\n\n#endif\n\n//lint -restore [MISRA Note 10]\n\n\n//  ==== Exclusive Access Operation ====\n\n#if (EXCLUSIVE_ACCESS == 1)\n\n//lint ++flb \"Library Begin\" [MISRA Note 12]\n\n/// Atomic Access Operation: Write (8-bit)\n/// \\param[in]  mem             Memory address\n/// \\param[in]  val             Value to write\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {\n  mov    r2,r0\n1\n  ldrexb r0,[r2]\n  strexb r3,r1,[r2]\n  cbz    r3,%F2\n  b      %B1\n2\n  bx     lr\n}\n#else\n__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint8_t  ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrexb %[ret],[%[mem]]\\n\\t\"\n    \"strexb %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz    %[res],2f\\n\\t\"\n    \"b       1b\\n\"\n  \"2:\"\n  : [ret] \"=&l\" (ret),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem),\n    [val] \"l\"   (val)\n  : \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Set bits (32-bit)\n/// \\param[in]  mem             Memory address\n/// \\param[in]  bits            Bit mask\n/// \\return                     New value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  orr   r0,r0,r1\n  strex r3,r0,[r2]\n  cbz   r3,%F2\n  b     %B1\n2\n  bx     lr\n}\n#else\n__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[val],[%[mem]]\\n\\t\"\n#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))\n    \"mov   %[ret],%[val]\\n\\t\"\n    \"orrs  %[ret],%[bits]\\n\\t\"\n#else\n    \"orr   %[ret],%[val],%[bits]\\n\\t\"\n#endif\n    \"strex %[res],%[ret],[%[mem]]\\n\\t\"\n    \"cbz   %[res],2f\\n\\t\"\n    \"b     1b\\n\"\n  \"2:\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [mem]  \"l\"   (mem),\n    [bits] \"l\"   (bits)\n#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))\n  : \"memory\", \"cc\"\n#else\n  : \"memory\"\n#endif\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Clear bits (32-bit)\n/// \\param[in]  mem             Memory address\n/// \\param[in]  bits            Bit mask\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {\n  push  {r4,lr}\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  bic   r4,r0,r1\n  strex r3,r4,[r2]\n  cbz   r3,%F2\n  b     %B1\n2\n  pop   {r4,pc}\n}\n#else\n__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))\n    \"mov   %[val],%[ret]\\n\\t\"\n    \"bics  %[val],%[bits]\\n\\t\"\n#else\n    \"bic   %[val],%[ret],%[bits]\\n\\t\"\n#endif\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz   %[res],2f\\n\\t\"\n    \"b     1b\\n\"\n  \"2:\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [mem]  \"l\"   (mem),\n    [bits] \"l\"   (bits)\n#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))\n  : \"memory\", \"cc\"\n#else\n  : \"memory\"\n#endif\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them\n/// \\param[in]  mem             Memory address\n/// \\param[in]  bits            Bit mask\n/// \\return                     Active bits before clearing or 0 if not active\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {\n  push  {r4,lr}\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  and   r4,r0,r1\n  cmp   r4,r1\n  beq   %F2\n  clrex\n  movs  r0,#0\n  pop   {r4,pc}\n2\n  bic   r4,r0,r1\n  strex r3,r4,[r2]\n  cbz   r3,%F3\n  b     %B1\n3\n  pop   {r4,pc}\n}\n#else\n__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))\n    \"mov   %[val],%[ret]\\n\\t\"\n    \"ands  %[val],%[bits]\\n\\t\"\n#else\n    \"and   %[val],%[ret],%[bits]\\n\\t\"\n#endif\n    \"cmp   %[val],%[bits]\\n\\t\"\n    \"beq   2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"movs  %[ret],#0\\n\\t\"\n    \"b     3f\\n\"\n  \"2:\\n\\t\"\n#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))\n    \"mov   %[val],%[ret]\\n\\t\"\n    \"bics  %[val],%[bits]\\n\\t\"\n#else\n    \"bic   %[val],%[ret],%[bits]\\n\\t\"\n#endif\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz   %[res],3f\\n\\t\"\n    \"b     1b\\n\"\n  \"3:\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [mem]  \"l\"   (mem),\n    [bits] \"l\"   (bits)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them\n/// \\param[in]  mem             Memory address\n/// \\param[in]  bits            Bit mask\n/// \\return                     Active bits before clearing or 0 if not active\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {\n  push  {r4,lr}\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  tst   r0,r1\n  bne   %F2\n  clrex\n  movs  r0,#0\n  pop   {r4,pc}\n2\n  bic   r4,r0,r1\n  strex r3,r4,[r2]\n  cbz   r3,%F3\n  b     %B1\n3\n  pop   {r4,pc}\n}\n#else\n__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"tst   %[ret],%[bits]\\n\\t\"\n    \"bne   2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"movs  %[ret],#0\\n\\t\"\n    \"b     3f\\n\"\n  \"2:\\n\\t\"\n#if (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))\n    \"mov   %[val],%[ret]\\n\\t\"\n    \"bics  %[val],%[bits]\\n\\t\"\n#else\n    \"bic   %[val],%[ret],%[bits]\\n\\t\"\n#endif\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz   %[res],3f\\n\\t\"\n    \"b     1b\\n\"\n  \"3:\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [mem]  \"l\"   (mem),\n    [bits] \"l\"   (bits)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Increment (32-bit)\n/// \\param[in]  mem             Memory address\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_inc32 (uint32_t *mem) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  adds  r1,r0,#1\n  strex r3,r1,[r2]\n  cbz   r3,%F2\n  b     %B1\n2\n  bx     lr\n}\n#else\n__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"adds  %[val],%[ret],#1\\n\\t\"\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz   %[res],2f\\n\\t\"\n    \"b     1b\\n\"\n  \"2:\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Increment (16-bit) if Less Than\n/// \\param[in]  mem             Memory address\n/// \\param[in]  max             Maximum value\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {\n  push   {r4,lr}\n  mov    r2,r0\n1\n  ldrexh r0,[r2]\n  cmp    r1,r0\n  bhi    %F2\n  clrex\n  pop    {r4,pc}\n2\n  adds   r4,r0,#1\n  strexh r3,r4,[r2]\n  cbz    r3,%F3\n  b      %B1\n3\n  pop    {r4,pc}\n}\n#else\n__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint16_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrexh %[ret],[%[mem]]\\n\\t\"\n    \"cmp    %[max],%[ret]\\n\\t\"\n    \"bhi    2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"b      3f\\n\"\n  \"2:\\n\\t\"\n    \"adds   %[val],%[ret],#1\\n\\t\"\n    \"strexh %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz    %[res],3f\\n\\t\"\n    \"b      1b\\n\"\n  \"3:\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem),\n    [max] \"l\"   (max)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Increment (16-bit) and clear on Limit\n/// \\param[in]  mem             Memory address\n/// \\param[in]  max             Maximum value\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {\n  push   {r4,lr}\n  mov    r2,r0\n1\n  ldrexh r0,[r2]\n  adds   r4,r0,#1\n  cmp    r1,r4\n  bhi    %F2\n  movs   r4,#0\n2\n  strexh r3,r4,[r2]\n  cbz    r3,%F3\n  b      %B1\n3\n  pop    {r4,pc}\n}\n#else\n__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint16_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrexh %[ret],[%[mem]]\\n\\t\"\n    \"adds   %[val],%[ret],#1\\n\\t\"\n    \"cmp    %[lim],%[val]\\n\\t\"\n    \"bhi    2f\\n\\t\"\n    \"movs   %[val],#0\\n\"\n  \"2:\\n\\t\"\n    \"strexh %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz    %[res],3f\\n\\t\"\n    \"b      1b\\n\"\n  \"3:\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem),\n    [lim] \"l\"   (lim)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Decrement (32-bit)\n/// \\param[in]  mem             Memory address\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_dec32 (uint32_t *mem) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  subs  r1,r0,#1\n  strex r3,r1,[r2]\n  cbz   r3,%F2\n  b     %B1\n2\n  bx     lr\n}\n#else\n__STATIC_INLINE uint32_t atomic_dec32 (uint32_t *mem) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"subs  %[val],%[ret],#1\\n\\t\"\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz   %[res],2f\\n\\t\"\n    \"b     1b\\n\"\n  \"2:\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Decrement (32-bit) if Not Zero\n/// \\param[in]  mem             Memory address\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint32_t atomic_dec32_nz (uint32_t *mem) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  cbnz  r0,%F2\n  clrex\n  bx    lr\n2\n  subs  r1,r0,#1\n  strex r3,r1,[r2]\n  cbz   r3,%F3\n  b     %B1\n3\n  bx     lr\n}\n#else\n__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint32_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[mem]]\\n\\t\"\n    \"cbnz  %[ret],2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"b     3f\\n\"\n  \"2:\\n\\t\"\n    \"subs  %[val],%[ret],#1\\n\\t\"\n    \"strex %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz   %[res],3f\\n\\t\"\n    \"b     1b\\n\"\n  \"3:\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Decrement (16-bit) if Not Zero\n/// \\param[in]  mem             Memory address\n/// \\return                     Previous value\n#if defined(__CC_ARM)\nstatic __asm    uint16_t atomic_dec16_nz (uint16_t *mem) {\n  mov    r2,r0\n1\n  ldrexh r0,[r2]\n  cbnz   r0,%F2\n  clrex\n  bx     lr\n2\n  subs   r1,r0,#1\n  strexh r3,r1,[r2]\n  cbz    r3,%F3\n  b      %B1\n3\n  bx      lr\n}\n#else\n__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register uint16_t ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrexh %[ret],[%[mem]]\\n\\t\"\n    \"cbnz   %[ret],2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"b      3f\\n\"\n  \"2:\\n\\t\"\n    \"subs   %[val],%[ret],#1\\n\\t\"\n    \"strexh %[res],%[val],[%[mem]]\\n\\t\"\n    \"cbz    %[res],3f\\n\\t\"\n    \"b      1b\\n\"\n  \"3:\"\n  : [ret] \"=&l\" (ret),\n    [val] \"=&l\" (val),\n    [res] \"=&l\" (res)\n  : [mem] \"l\"   (mem)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Link Get\n/// \\param[in]  root            Root address\n/// \\return                     Link\n#if defined(__CC_ARM)\nstatic __asm    void *atomic_link_get (void **root) {\n  mov   r2,r0\n1\n  ldrex r0,[r2]\n  cbnz  r0,%F2\n  clrex\n  bx    lr\n2\n  ldr   r1,[r0]\n  strex r3,r1,[r2]\n  cbz   r3,%F3\n  b     %B1\n3\n  bx     lr\n}\n#else\n__STATIC_INLINE void *atomic_link_get (void **root) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n  register void    *ret;\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldrex %[ret],[%[root]]\\n\\t\"\n    \"cbnz  %[ret],2f\\n\\t\"\n    \"clrex\\n\\t\"\n    \"b     3f\\n\"\n  \"2:\\n\\t\"\n    \"ldr   %[val],[%[ret]]\\n\\t\"\n    \"strex %[res],%[val],[%[root]]\\n\\t\"\n    \"cbz   %[res],3f\\n\\t\"\n    \"b     1b\\n\"\n  \"3:\"\n  : [ret]  \"=&l\" (ret),\n    [val]  \"=&l\" (val),\n    [res]  \"=&l\" (res)\n  : [root] \"l\"   (root)\n  : \"cc\", \"memory\"\n  );\n\n  return ret;\n}\n#endif\n\n/// Atomic Access Operation: Link Put\n/// \\param[in]  root            Root address\n/// \\param[in]  lnk             Link\n#if defined(__CC_ARM)\nstatic __asm    void atomic_link_put (void **root, void *link) {\n1\n  ldr   r2,[r0]\n  str   r2,[r1]\n  dmb\n  ldrex r2,[r0]\n  ldr   r3,[r1]\n  cmp   r3,r2\n  bne   %B1\n  strex r3,r1,[r0]\n  cbz   r3,%F2\n  b     %B1\n2\n  bx    lr\n}\n#else\n__STATIC_INLINE void atomic_link_put (void **root, void *link) {\n#ifdef  __ICCARM__\n#pragma diag_suppress=Pe550\n#endif\n  register uint32_t val1, val2, res;\n#ifdef  __ICCARM__\n#pragma diag_default=Pe550\n#endif\n\n  __ASM volatile (\n#ifndef __ICCARM__\n  \".syntax unified\\n\\t\"\n#endif\n  \"1:\\n\\t\"\n    \"ldr   %[val1],[%[root]]\\n\\t\"\n    \"str   %[val1],[%[link]]\\n\\t\"\n    \"dmb\\n\\t\"\n    \"ldrex %[val1],[%[root]]\\n\\t\"\n    \"ldr   %[val2],[%[link]]\\n\\t\"\n    \"cmp   %[val2],%[val1]\\n\\t\"\n    \"bne   1b\\n\\t\"\n    \"strex %[res],%[link],[%[root]]\\n\\t\"\n    \"cbz   %[res],2f\\n\\t\"\n    \"b     1b\\n\"\n  \"2:\"\n  : [val1] \"=&l\" (val1),\n    [val2] \"=&l\" (val2),\n    [res]  \"=&l\" (res)\n  : [root] \"l\"   (root),\n    [link] \"l\"   (link)\n  : \"cc\", \"memory\"\n  );\n}\n#endif\n\n//lint --flb \"Library End\" [MISRA Note 12]\n\n#endif  // (EXCLUSIVE_ACCESS == 1)\n\n\n#endif  // RTX_CORE_CM_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_delay.c",
    "content": "/*\n * Copyright (c) 2013-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Delay functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  ==== Service Calls ====\n\n/// Wait for Timeout (Time Delay).\n/// \\note API identical to osDelay\nstatic osStatus_t svcRtxDelay (uint32_t ticks) {\n  osStatus_t status;\n\n  if (ticks == 0U) {\n    EvrRtxDelayError((int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  if (osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) {\n    EvrRtxDelayStarted(ticks);\n    status = osOK;\n  } else {\n    EvrRtxDelayError((int32_t)osError);\n    status = osError;\n  }\n\n  return status;\n}\n\n/// Wait until specified time.\n/// \\note API identical to osDelayUntil\nstatic osStatus_t svcRtxDelayUntil (uint32_t ticks) {\n  osStatus_t status;\n\n  ticks -= osRtxInfo.kernel.tick;\n  if ((ticks == 0U) || (ticks > 0x7FFFFFFFU)) {\n    EvrRtxDelayError((int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  if (osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks)) {\n    EvrRtxDelayUntilStarted(ticks);\n    status = osOK;\n  } else {\n    EvrRtxDelayError((int32_t)osError);\n    status = osError;\n  }\n\n  return status;\n}\n\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_1(Delay,      osStatus_t, uint32_t)\nSVC0_1(DelayUntil, osStatus_t, uint32_t)\n//lint --flb \"Library End\"\n\n\n//  ==== Public API ====\n\n/// Wait for Timeout (Time Delay).\nosStatus_t osDelay (uint32_t ticks) {\n  osStatus_t status;\n\n  EvrRtxDelay(ticks);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxDelayError((int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcDelay(ticks);\n  }\n  return status;\n}\n\n/// Wait until specified time.\nosStatus_t osDelayUntil (uint32_t ticks) {\n  osStatus_t status;\n\n  EvrRtxDelayUntil(ticks);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxDelayError((int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcDelayUntil(ticks);\n  }\n  return status;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_evflags.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Event Flags functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  OS Runtime Object Memory Usage\n#ifdef RTX_OBJ_MEM_USAGE\nosRtxObjectMemUsage_t osRtxEventFlagsMemUsage \\\n__attribute__((section(\".data.os.evflags.obj\"))) =\n{ 0U, 0U, 0U };\n#endif\n\n\n//  ==== Helper functions ====\n\n/// Set Event Flags.\n/// \\param[in]  ef              event flags object.\n/// \\param[in]  flags           specifies the flags to set.\n/// \\return event flags after setting.\nstatic uint32_t EventFlagsSet (os_event_flags_t *ef, uint32_t flags) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask = __get_PRIMASK();\n#endif\n  uint32_t event_flags;\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  ef->event_flags |= flags;\n  event_flags = ef->event_flags;\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  event_flags = atomic_set32(&ef->event_flags, flags);\n#endif\n\n  return event_flags;\n}\n\n/// Clear Event Flags.\n/// \\param[in]  ef              event flags object.\n/// \\param[in]  flags           specifies the flags to clear.\n/// \\return event flags before clearing.\nstatic uint32_t EventFlagsClear (os_event_flags_t *ef, uint32_t flags) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask = __get_PRIMASK();\n#endif\n  uint32_t event_flags;\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  event_flags = ef->event_flags;\n  ef->event_flags &= ~flags;\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  event_flags = atomic_clr32(&ef->event_flags, flags);\n#endif\n\n  return event_flags;\n}\n\n/// Check Event Flags.\n/// \\param[in]  ef              event flags object.\n/// \\param[in]  flags           specifies the flags to check.\n/// \\param[in]  options         specifies flags options (osFlagsXxxx).\n/// \\return event flags before clearing or 0 if specified flags have not been set.\nstatic uint32_t EventFlagsCheck (os_event_flags_t *ef, uint32_t flags, uint32_t options) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask;\n#endif\n  uint32_t event_flags;\n\n  if ((options & osFlagsNoClear) == 0U) {\n#if (EXCLUSIVE_ACCESS == 0)\n    primask = __get_PRIMASK();\n    __disable_irq();\n\n    event_flags = ef->event_flags;\n    if ((((options & osFlagsWaitAll) != 0U) && ((event_flags & flags) != flags)) ||\n        (((options & osFlagsWaitAll) == 0U) && ((event_flags & flags) == 0U))) {\n      event_flags = 0U;\n    } else {\n      ef->event_flags &= ~flags;\n    }\n\n    if (primask == 0U) {\n      __enable_irq();\n    }\n#else\n    if ((options & osFlagsWaitAll) != 0U) {\n      event_flags = atomic_chk32_all(&ef->event_flags, flags);\n    } else {\n      event_flags = atomic_chk32_any(&ef->event_flags, flags);\n    }\n#endif\n  } else {\n    event_flags = ef->event_flags;\n    if ((((options & osFlagsWaitAll) != 0U) && ((event_flags & flags) != flags)) ||\n        (((options & osFlagsWaitAll) == 0U) && ((event_flags & flags) == 0U))) {\n      event_flags = 0U;\n    }\n  }\n\n  return event_flags;\n}\n\n/// Verify that Event Flags object pointer is valid.\n/// \\param[in]  ef              event flags object.\n/// \\return true - valid, false - invalid.\nstatic bool_t IsEventFlagsPtrValid (const os_event_flags_t *ef) {\n#ifdef RTX_OBJ_PTR_CHECK\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  uint32_t cb_start  = (uint32_t)&__os_evflags_cb_start__;\n  uint32_t cb_length = (uint32_t)&__os_evflags_cb_length__;\n\n  // Check the section boundaries\n  if (((uint32_t)ef - cb_start) >= cb_length) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n  // Check the object alignment\n  if ((((uint32_t)ef - cb_start) % sizeof(os_event_flags_t)) != 0U) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#else\n  // Check NULL pointer\n  if (ef == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#endif\n  return TRUE;\n}\n\n\n//  ==== Library functions ====\n\n/// Destroy an Event Flags object.\n/// \\param[in]  ef              event flags object.\nstatic void osRtxEventFlagsDestroy (os_event_flags_t *ef) {\n\n  // Mark object as invalid\n  ef->id = osRtxIdInvalid;\n\n  // Free object memory\n  if ((ef->flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n    (void)osRtxMemoryPoolFree(osRtxInfo.mpi.event_flags, ef);\n#else\n    if (osRtxInfo.mpi.event_flags != NULL) {\n      (void)osRtxMemoryPoolFree(osRtxInfo.mpi.event_flags, ef);\n    } else {\n      (void)osRtxMemoryFree(osRtxInfo.mem.common, ef);\n    }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n    osRtxEventFlagsMemUsage.cnt_free++;\n#endif\n  }\n\n  EvrRtxEventFlagsDestroyed(ef);\n}\n\n#ifdef RTX_SAFETY_CLASS\n/// Delete an Event Flags safety class.\n/// \\param[in]  safety_class    safety class.\n/// \\param[in]  mode            safety mode.\nvoid osRtxEventFlagsDeleteClass (uint32_t safety_class, uint32_t mode) {\n  os_event_flags_t *ef;\n  os_thread_t      *thread;\n  uint32_t          length;\n\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  ef     = (os_event_flags_t *)(uint32_t)&__os_evflags_cb_start__;\n  length =                     (uint32_t)&__os_evflags_cb_length__;\n  while (length >= sizeof(os_event_flags_t)) {\n    if (   (ef->id == osRtxIdEventFlags) &&\n        ((((mode & osSafetyWithSameClass)  != 0U) &&\n          ((ef->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n         (((mode & osSafetyWithLowerClass) != 0U) &&\n          ((ef->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class)))) {\n      while (ef->thread_list != NULL) {\n        thread = osRtxThreadListGet(osRtxObject(ef));\n        osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);\n      }\n      osRtxEventFlagsDestroy(ef);\n    }\n    length -= sizeof(os_event_flags_t);\n    ef++;\n  }\n}\n#endif\n\n\n//  ==== Post ISR processing ====\n\n/// Event Flags post ISR processing.\n/// \\param[in]  ef              event flags object.\nstatic void osRtxEventFlagsPostProcess (os_event_flags_t *ef) {\n  os_thread_t *thread;\n  os_thread_t *thread_next;\n  uint32_t     event_flags;\n\n  // Check if Threads are waiting for Event Flags\n  thread = ef->thread_list;\n  while (thread != NULL) {\n    thread_next = thread->thread_next;\n    event_flags = EventFlagsCheck(ef, thread->wait_flags, thread->flags_options);\n    if (event_flags != 0U) {\n      osRtxThreadListRemove(thread);\n      osRtxThreadWaitExit(thread, event_flags, FALSE);\n      EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags);\n    }\n    thread = thread_next;\n  }\n}\n\n\n//  ==== Service Calls ====\n\n/// Create and Initialize an Event Flags object.\n/// \\note API identical to osEventFlagsNew\nstatic osEventFlagsId_t svcRtxEventFlagsNew (const osEventFlagsAttr_t *attr) {\n  os_event_flags_t  *ef;\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread = osRtxThreadGetRunning();\n  uint32_t           attr_bits;\n#endif\n  uint8_t            flags;\n  const char        *name;\n\n  // Process attributes\n  if (attr != NULL) {\n    name      = attr->name;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = attr->attr_bits;\n#endif\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    ef        = attr->cb_mem;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      if ((thread != NULL) &&\n          ((thread->attr >> osRtxAttrClass_Pos) <\n          (uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {\n        EvrRtxEventFlagsError(NULL, (int32_t)osErrorSafetyClass);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n#endif\n    if (ef != NULL) {\n      if (!IsEventFlagsPtrValid(ef) || (attr->cb_size != sizeof(os_event_flags_t))) {\n        EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    } else {\n      if (attr->cb_size != 0U) {\n        EvrRtxEventFlagsError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n  } else {\n    name      = NULL;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = 0U;\n#endif\n    ef        = NULL;\n  }\n\n  // Allocate object memory if not provided\n  if (ef == NULL) {\n    if (osRtxInfo.mpi.event_flags != NULL) {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      ef = osRtxMemoryPoolAlloc(osRtxInfo.mpi.event_flags);\n#ifndef RTX_OBJ_PTR_CHECK\n    } else {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      ef = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_event_flags_t), 1U);\n#endif\n    }\n#ifdef RTX_OBJ_MEM_USAGE\n    if (ef != NULL) {\n      uint32_t used;\n      osRtxEventFlagsMemUsage.cnt_alloc++;\n      used = osRtxEventFlagsMemUsage.cnt_alloc - osRtxEventFlagsMemUsage.cnt_free;\n      if (osRtxEventFlagsMemUsage.max_used < used) {\n        osRtxEventFlagsMemUsage.max_used = used;\n      }\n    }\n#endif\n    flags = osRtxFlagSystemObject;\n  } else {\n    flags = 0U;\n  }\n\n  if (ef != NULL) {\n    // Initialize control block\n    ef->id          = osRtxIdEventFlags;\n    ef->flags       = flags;\n    ef->attr        = 0U;\n    ef->name        = name;\n    ef->thread_list = NULL;\n    ef->event_flags = 0U;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      ef->attr     |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>\n                                (osSafetyClass_Pos - osRtxAttrClass_Pos));\n    } else {\n      // Inherit safety class from the running thread\n      if (thread != NULL) {\n        ef->attr   |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);\n      }\n    }\n#endif\n\n    // Register post ISR processing function\n    osRtxInfo.post_process.event_flags = osRtxEventFlagsPostProcess;\n\n    EvrRtxEventFlagsCreated(ef, ef->name);\n  } else {\n    EvrRtxEventFlagsError(NULL, (int32_t)osErrorNoMemory);\n  }\n\n  return ef;\n}\n\n/// Get name of an Event Flags object.\n/// \\note API identical to osEventFlagsGetName\nstatic const char *svcRtxEventFlagsGetName (osEventFlagsId_t ef_id) {\n  os_event_flags_t *ef = osRtxEventFlagsId(ef_id);\n\n  // Check parameters\n  if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags)) {\n    EvrRtxEventFlagsGetName(ef, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  EvrRtxEventFlagsGetName(ef, ef->name);\n\n  return ef->name;\n}\n\n/// Set the specified Event Flags.\n/// \\note API identical to osEventFlagsSet\nstatic uint32_t svcRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {\n  os_event_flags_t *ef = osRtxEventFlagsId(ef_id);\n  os_thread_t      *thread;\n  os_thread_t      *thread_next;\n  uint32_t          event_flags;\n  uint32_t          event_flags0;\n\n  // Check parameters\n  if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) ||\n      ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorParameter);\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (ef->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorSafetyClass);\n  }\n#endif\n\n  // Set Event Flags\n  event_flags = EventFlagsSet(ef, flags);\n\n  // Check if Threads are waiting for Event Flags\n  thread = ef->thread_list;\n  while (thread != NULL) {\n    thread_next = thread->thread_next;\n    event_flags0 = EventFlagsCheck(ef, thread->wait_flags, thread->flags_options);\n    if (event_flags0 != 0U) {\n      if ((thread->flags_options & osFlagsNoClear) == 0U) {\n        event_flags = event_flags0 & ~thread->wait_flags;\n      } else {\n        event_flags = event_flags0;\n      }\n      osRtxThreadListRemove(thread);\n      osRtxThreadWaitExit(thread, event_flags0, FALSE);\n      EvrRtxEventFlagsWaitCompleted(ef, thread->wait_flags, thread->flags_options, event_flags0);\n    }\n    thread = thread_next;\n  }\n  osRtxThreadDispatch(NULL);\n\n  EvrRtxEventFlagsSetDone(ef, event_flags);\n\n  return event_flags;\n}\n\n/// Clear the specified Event Flags.\n/// \\note API identical to osEventFlagsClear\nstatic uint32_t svcRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {\n  os_event_flags_t  *ef = osRtxEventFlagsId(ef_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread;\n#endif\n  uint32_t           event_flags;\n\n  // Check parameters\n  if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) ||\n      ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorParameter);\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (ef->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorSafetyClass);\n  }\n#endif\n\n  // Clear Event Flags\n  event_flags = EventFlagsClear(ef, flags);\n\n  EvrRtxEventFlagsClearDone(ef, event_flags);\n\n  return event_flags;\n}\n\n/// Get the current Event Flags.\n/// \\note API identical to osEventFlagsGet\nstatic uint32_t svcRtxEventFlagsGet (osEventFlagsId_t ef_id) {\n  os_event_flags_t *ef = osRtxEventFlagsId(ef_id);\n\n  // Check parameters\n  if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags)) {\n    EvrRtxEventFlagsGet(ef, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxEventFlagsGet(ef, ef->event_flags);\n\n  return ef->event_flags;\n}\n\n/// Wait for one or more Event Flags to become signaled.\n/// \\note API identical to osEventFlagsWait\nstatic uint32_t svcRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {\n  os_event_flags_t *ef = osRtxEventFlagsId(ef_id);\n  os_thread_t      *thread;\n  uint32_t          event_flags;\n\n  // Check parameters\n  if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) ||\n      ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorParameter);\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (ef->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorSafetyClass);\n  }\n#endif\n\n  // Check Event Flags\n  event_flags = EventFlagsCheck(ef, flags, options);\n  if (event_flags != 0U) {\n    EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags);\n  } else {\n    // Check if timeout is specified\n    if (timeout != 0U) {\n      EvrRtxEventFlagsWaitPending(ef, flags, options, timeout);\n      // Suspend current Thread\n      if (osRtxThreadWaitEnter(osRtxThreadWaitingEventFlags, timeout)) {\n        thread = osRtxThreadGetRunning();\n        osRtxThreadListPut(osRtxObject(ef), thread);\n        // Store waiting flags and options\n        thread->wait_flags = flags;\n        thread->flags_options = (uint8_t)options;\n      } else {\n        EvrRtxEventFlagsWaitTimeout(ef);\n      }\n      event_flags = (uint32_t)osErrorTimeout;\n    } else {\n      EvrRtxEventFlagsWaitNotCompleted(ef, flags, options);\n      event_flags = (uint32_t)osErrorResource;\n    }\n  }\n\n  return event_flags;\n}\n\n/// Delete an Event Flags object.\n/// \\note API identical to osEventFlagsDelete\nstatic osStatus_t svcRtxEventFlagsDelete (osEventFlagsId_t ef_id) {\n  os_event_flags_t *ef = osRtxEventFlagsId(ef_id);\n  os_thread_t      *thread;\n\n  // Check parameters\n  if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags)) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (ef->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Unblock waiting threads\n  if (ef->thread_list != NULL) {\n    do {\n      thread = osRtxThreadListGet(osRtxObject(ef));\n      osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);\n    } while (ef->thread_list != NULL);\n    osRtxThreadDispatch(NULL);\n  }\n\n  osRtxEventFlagsDestroy(ef);\n\n  return osOK;\n}\n\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_1(EventFlagsNew,     osEventFlagsId_t, const osEventFlagsAttr_t *)\nSVC0_1(EventFlagsGetName, const char *,     osEventFlagsId_t)\nSVC0_2(EventFlagsSet,     uint32_t,         osEventFlagsId_t, uint32_t)\nSVC0_2(EventFlagsClear,   uint32_t,         osEventFlagsId_t, uint32_t)\nSVC0_1(EventFlagsGet,     uint32_t,         osEventFlagsId_t)\nSVC0_4(EventFlagsWait,    uint32_t,         osEventFlagsId_t, uint32_t, uint32_t, uint32_t)\nSVC0_1(EventFlagsDelete,  osStatus_t,       osEventFlagsId_t)\n//lint --flb \"Library End\"\n\n\n//  ==== ISR Calls ====\n\n/// Set the specified Event Flags.\n/// \\note API identical to osEventFlagsSet\n__STATIC_INLINE\nuint32_t isrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {\n  os_event_flags_t *ef = osRtxEventFlagsId(ef_id);\n  uint32_t          event_flags;\n\n  // Check parameters\n  if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) ||\n      ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorParameter);\n  }\n\n  // Set Event Flags\n  event_flags = EventFlagsSet(ef, flags);\n\n  // Register post ISR processing\n  osRtxPostProcess(osRtxObject(ef));\n\n  EvrRtxEventFlagsSetDone(ef, event_flags);\n\n  return event_flags;\n}\n\n/// Wait for one or more Event Flags to become signaled.\n/// \\note API identical to osEventFlagsWait\n__STATIC_INLINE\nuint32_t isrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {\n  os_event_flags_t *ef = osRtxEventFlagsId(ef_id);\n  uint32_t          event_flags;\n\n  // Check parameters\n  if (!IsEventFlagsPtrValid(ef) || (ef->id != osRtxIdEventFlags) || (timeout != 0U) ||\n      ((flags & ~(((uint32_t)1U << osRtxEventFlagsLimit) - 1U)) != 0U)) {\n    EvrRtxEventFlagsError(ef, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorParameter);\n  }\n\n  // Check Event Flags\n  event_flags = EventFlagsCheck(ef, flags, options);\n  if (event_flags != 0U) {\n    EvrRtxEventFlagsWaitCompleted(ef, flags, options, event_flags);\n  } else {\n    EvrRtxEventFlagsWaitNotCompleted(ef, flags, options);\n    event_flags = (uint32_t)osErrorResource;\n  }\n\n  return event_flags;\n}\n\n\n//  ==== Public API ====\n\n/// Create and Initialize an Event Flags object.\nosEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) {\n  osEventFlagsId_t ef_id;\n\n  EvrRtxEventFlagsNew(attr);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxEventFlagsError(NULL, (int32_t)osErrorISR);\n    ef_id = NULL;\n  } else {\n    ef_id = __svcEventFlagsNew(attr);\n  }\n  return ef_id;\n}\n\n/// Get name of an Event Flags object.\nconst char *osEventFlagsGetName (osEventFlagsId_t ef_id) {\n  const char *name;\n\n  if (IsException() || IsIrqMasked()) {\n    name = svcRtxEventFlagsGetName(ef_id);\n  } else {\n    name =  __svcEventFlagsGetName(ef_id);\n  }\n  return name;\n}\n\n/// Set the specified Event Flags.\nuint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {\n  uint32_t event_flags;\n\n  EvrRtxEventFlagsSet(ef_id, flags);\n  if (IsException() || IsIrqMasked()) {\n    event_flags = isrRtxEventFlagsSet(ef_id, flags);\n  } else {\n    event_flags =  __svcEventFlagsSet(ef_id, flags);\n  }\n  return event_flags;\n}\n\n/// Clear the specified Event Flags.\nuint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {\n  uint32_t event_flags;\n\n  EvrRtxEventFlagsClear(ef_id, flags);\n  if (IsException() || IsIrqMasked()) {\n    event_flags = svcRtxEventFlagsClear(ef_id, flags);\n  } else {\n    event_flags =  __svcEventFlagsClear(ef_id, flags);\n  }\n  return event_flags;\n}\n\n/// Get the current Event Flags.\nuint32_t osEventFlagsGet (osEventFlagsId_t ef_id) {\n  uint32_t event_flags;\n\n  if (IsException() || IsIrqMasked()) {\n    event_flags = svcRtxEventFlagsGet(ef_id);\n  } else {\n    event_flags =  __svcEventFlagsGet(ef_id);\n  }\n  return event_flags;\n}\n\n/// Wait for one or more Event Flags to become signaled.\nuint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {\n  uint32_t event_flags;\n\n  EvrRtxEventFlagsWait(ef_id, flags, options, timeout);\n  if (IsException() || IsIrqMasked()) {\n    event_flags = isrRtxEventFlagsWait(ef_id, flags, options, timeout);\n  } else {\n    event_flags =  __svcEventFlagsWait(ef_id, flags, options, timeout);\n  }\n  return event_flags;\n}\n\n/// Delete an Event Flags object.\nosStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) {\n  osStatus_t status;\n\n  EvrRtxEventFlagsDelete(ef_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxEventFlagsError(ef_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcEventFlagsDelete(ef_id);\n  }\n  return status;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_evr.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Event Recorder\n *\n * -----------------------------------------------------------------------------\n */\n\n#include <string.h>\n#include \"cmsis_compiler.h\"\n#include \"rtx_evr.h\"                    // RTX Event Recorder definitions\n\n#ifdef  RTE_Compiler_EventRecorder\n\n//lint -e923 -e9074 -e9078 [MISRA Note 13]\n\n/// Event IDs for \"RTX Memory Management\"\n#define EvtRtxMemoryInit                    EventID(EventLevelOp,     EvtRtxMemoryNo, 0x00U)\n#define EvtRtxMemoryAlloc                   EventID(EventLevelOp,     EvtRtxMemoryNo, 0x01U)\n#define EvtRtxMemoryFree                    EventID(EventLevelOp,     EvtRtxMemoryNo, 0x02U)\n#define EvtRtxMemoryBlockInit               EventID(EventLevelOp,     EvtRtxMemoryNo, 0x03U)\n#define EvtRtxMemoryBlockAlloc              EventID(EventLevelOp,     EvtRtxMemoryNo, 0x04U)\n#define EvtRtxMemoryBlockFree               EventID(EventLevelOp,     EvtRtxMemoryNo, 0x05U)\n\n/// Event IDs for \"RTX Kernel\"\n#define EvtRtxKernelError                   EventID(EventLevelError,  EvtRtxKernelNo, 0x00U)\n#define EvtRtxKernelInitialize              EventID(EventLevelAPI,    EvtRtxKernelNo, 0x01U)\n#define EvtRtxKernelInitialized             EventID(EventLevelOp,     EvtRtxKernelNo, 0x02U)\n#define EvtRtxKernelGetInfo                 EventID(EventLevelAPI,    EvtRtxKernelNo, 0x03U)\n#define EvtRtxKernelInfoRetrieved           EventID(EventLevelOp,     EvtRtxKernelNo, 0x04U)\n#define EvtRtxKernelInfoRetrieved_Detail    EventID(EventLevelDetail, EvtRtxKernelNo, 0x05U)\n#define EvtRtxKernelGetState                EventID(EventLevelAPI,    EvtRtxKernelNo, 0x06U)\n#define EvtRtxKernelStart                   EventID(EventLevelAPI,    EvtRtxKernelNo, 0x07U)\n#define EvtRtxKernelStarted                 EventID(EventLevelOp,     EvtRtxKernelNo, 0x08U)\n#define EvtRtxKernelLock                    EventID(EventLevelAPI,    EvtRtxKernelNo, 0x09U)\n#define EvtRtxKernelLocked                  EventID(EventLevelOp,     EvtRtxKernelNo, 0x0AU)\n#define EvtRtxKernelUnlock                  EventID(EventLevelAPI,    EvtRtxKernelNo, 0x0BU)\n#define EvtRtxKernelUnlocked                EventID(EventLevelOp,     EvtRtxKernelNo, 0x0CU)\n#define EvtRtxKernelRestoreLock             EventID(EventLevelAPI,    EvtRtxKernelNo, 0x0DU)\n#define EvtRtxKernelLockRestored            EventID(EventLevelOp,     EvtRtxKernelNo, 0x0EU)\n#define EvtRtxKernelSuspend                 EventID(EventLevelAPI,    EvtRtxKernelNo, 0x0FU)\n#define EvtRtxKernelSuspended               EventID(EventLevelOp,     EvtRtxKernelNo, 0x10U)\n#define EvtRtxKernelResume                  EventID(EventLevelAPI,    EvtRtxKernelNo, 0x11U)\n#define EvtRtxKernelResumed                 EventID(EventLevelOp,     EvtRtxKernelNo, 0x12U)\n#define EvtRtxKernelProtect                 EventID(EventLevelAPI,    EvtRtxKernelNo, 0x17U)\n#define EvtRtxKernelProtected               EventID(EventLevelOp,     EvtRtxKernelNo, 0x18U)\n#define EvtRtxKernelGetTickCount            EventID(EventLevelAPI,    EvtRtxKernelNo, 0x13U)\n#define EvtRtxKernelGetTickFreq             EventID(EventLevelAPI,    EvtRtxKernelNo, 0x14U)\n#define EvtRtxKernelGetSysTimerCount        EventID(EventLevelAPI,    EvtRtxKernelNo, 0x15U)\n#define EvtRtxKernelGetSysTimerFreq         EventID(EventLevelAPI,    EvtRtxKernelNo, 0x16U)\n#define EvtRtxKernelErrorNotify             EventID(EventLevelError,  EvtRtxKernelNo, 0x19U)\n#define EvtRtxKernelDestroyClass            EventID(EventLevelAPI,    EvtRtxKernelNo, 0x1AU)\n\n/// Event IDs for \"RTX Thread\"\n#define EvtRtxThreadError                   EventID(EventLevelError,  EvtRtxThreadNo, 0x00U)\n#define EvtRtxThreadNew                     EventID(EventLevelAPI,    EvtRtxThreadNo, 0x01U)\n#define EvtRtxThreadCreated_Addr            EventID(EventLevelOp,     EvtRtxThreadNo, 0x03U)\n#define EvtRtxThreadCreated_Name            EventID(EventLevelOp,     EvtRtxThreadNo, 0x2CU)\n#define EvtRtxThreadGetName                 EventID(EventLevelAPI,    EvtRtxThreadNo, 0x04U)\n#define EvtRtxThreadGetClass                EventID(EventLevelAPI,    EvtRtxThreadNo, 0x30U)\n#define EvtRtxThreadGetZone                 EventID(EventLevelAPI,    EvtRtxThreadNo, 0x31U)\n#define EvtRtxThreadGetId                   EventID(EventLevelAPI,    EvtRtxThreadNo, 0x06U)\n#define EvtRtxThreadGetState                EventID(EventLevelAPI,    EvtRtxThreadNo, 0x07U)\n#define EvtRtxThreadGetStackSize            EventID(EventLevelAPI,    EvtRtxThreadNo, 0x08U)\n#define EvtRtxThreadGetStackSpace           EventID(EventLevelAPI,    EvtRtxThreadNo, 0x09U)\n#define EvtRtxThreadSetPriority             EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0AU)\n#define EvtRtxThreadPriorityUpdated         EventID(EventLevelOp,     EvtRtxThreadNo, 0x2DU)\n#define EvtRtxThreadGetPriority             EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0BU)\n#define EvtRtxThreadYield                   EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0CU)\n#define EvtRtxThreadSuspend                 EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0DU)\n#define EvtRtxThreadSuspended               EventID(EventLevelOp,     EvtRtxThreadNo, 0x0EU)\n#define EvtRtxThreadResume                  EventID(EventLevelAPI,    EvtRtxThreadNo, 0x0FU)\n#define EvtRtxThreadResumed                 EventID(EventLevelOp,     EvtRtxThreadNo, 0x10U)\n#define EvtRtxThreadDetach                  EventID(EventLevelAPI,    EvtRtxThreadNo, 0x11U)\n#define EvtRtxThreadDetached                EventID(EventLevelOp,     EvtRtxThreadNo, 0x12U)\n#define EvtRtxThreadJoin                    EventID(EventLevelAPI,    EvtRtxThreadNo, 0x13U)\n#define EvtRtxThreadJoinPending             EventID(EventLevelOp,     EvtRtxThreadNo, 0x14U)\n#define EvtRtxThreadJoined                  EventID(EventLevelOp,     EvtRtxThreadNo, 0x15U)\n#define EvtRtxThreadBlocked                 EventID(EventLevelDetail, EvtRtxThreadNo, 0x16U)\n#define EvtRtxThreadUnblocked               EventID(EventLevelDetail, EvtRtxThreadNo, 0x17U)\n#define EvtRtxThreadPreempted               EventID(EventLevelDetail, EvtRtxThreadNo, 0x18U)\n#define EvtRtxThreadSwitched                EventID(EventLevelOp,     EvtRtxThreadNo, 0x19U)\n#define EvtRtxThreadExit                    EventID(EventLevelAPI,    EvtRtxThreadNo, 0x1AU)\n#define EvtRtxThreadTerminate               EventID(EventLevelAPI,    EvtRtxThreadNo, 0x1BU)\n#define EvtRtxThreadDestroyed               EventID(EventLevelOp,     EvtRtxThreadNo, 0x1CU)\n#define EvtRtxThreadFeedWatchdog            EventID(EventLevelAPI,    EvtRtxThreadNo, 0x2EU)\n#define EvtRtxThreadFeedWatchdogDone        EventID(EventLevelOp,     EvtRtxThreadNo, 0x2FU)\n#define EvtRtxThreadProtectPrivileged       EventID(EventLevelAPI,    EvtRtxThreadNo, 0x32U)\n#define EvtRtxThreadPrivilegedProtected     EventID(EventLevelOp,     EvtRtxThreadNo, 0x33U)\n#define EvtRtxThreadGetCount                EventID(EventLevelAPI,    EvtRtxThreadNo, 0x1DU)\n#define EvtRtxThreadEnumerate               EventID(EventLevelAPI,    EvtRtxThreadNo, 0x1EU)\n#define EvtRtxThreadSuspendClass            EventID(EventLevelAPI,    EvtRtxThreadNo, 0x34U)\n#define EvtRtxThreadResumeClass             EventID(EventLevelAPI,    EvtRtxThreadNo, 0x35U)\n#define EvtRtxThreadTerminateZone           EventID(EventLevelAPI,    EvtRtxThreadNo, 0x36U)\n#define EvtRtxThreadWatchdogExpired         EventID(EventLevelError,  EvtRtxThreadNo, 0x37U)\n\n/// Event IDs for \"RTX Thread Flags\"\n#define EvtRtxThreadFlagsError              EventID(EventLevelError,  EvtRtxThreadFlagsNo, 0x00U)\n#define EvtRtxThreadFlagsSet                EventID(EventLevelAPI,    EvtRtxThreadFlagsNo, 0x01U)\n#define EvtRtxThreadFlagsSetDone            EventID(EventLevelOp,     EvtRtxThreadFlagsNo, 0x02U)\n#define EvtRtxThreadFlagsClear              EventID(EventLevelAPI,    EvtRtxThreadFlagsNo, 0x03U)\n#define EvtRtxThreadFlagsClearDone          EventID(EventLevelOp,     EvtRtxThreadFlagsNo, 0x04U)\n#define EvtRtxThreadFlagsGet                EventID(EventLevelAPI,    EvtRtxThreadFlagsNo, 0x05U)\n#define EvtRtxThreadFlagsWait               EventID(EventLevelAPI,    EvtRtxThreadFlagsNo, 0x06U)\n#define EvtRtxThreadFlagsWaitPending        EventID(EventLevelOp,     EvtRtxThreadFlagsNo, 0x07U)\n#define EvtRtxThreadFlagsWaitTimeout        EventID(EventLevelOp,     EvtRtxThreadFlagsNo, 0x08U)\n#define EvtRtxThreadFlagsWaitCompleted      EventID(EventLevelOp,     EvtRtxThreadFlagsNo, 0x09U)\n#define EvtRtxThreadFlagsWaitNotCompleted   EventID(EventLevelOp,     EvtRtxThreadFlagsNo, 0x0AU)\n\n/// Event IDs for \"RTX Generic Wait\"\n#define EvtRtxDelayError                    EventID(EventLevelError,  EvtRtxWaitNo, 0x00U)\n#define EvtRtxDelay                         EventID(EventLevelAPI,    EvtRtxWaitNo, 0x01U)\n#define EvtRtxDelayUntil                    EventID(EventLevelAPI,    EvtRtxWaitNo, 0x02U)\n#define EvtRtxDelayStarted                  EventID(EventLevelOp,     EvtRtxWaitNo, 0x03U)\n#define EvtRtxDelayUntilStarted             EventID(EventLevelOp,     EvtRtxWaitNo, 0x04U)\n#define EvtRtxDelayCompleted                EventID(EventLevelOp,     EvtRtxWaitNo, 0x05U)\n\n/// Event IDs for \"RTX Timer\"\n#define EvtRtxTimerError                    EventID(EventLevelError,  EvtRtxTimerNo, 0x00U)\n#define EvtRtxTimerCallback                 EventID(EventLevelOp,     EvtRtxTimerNo, 0x01U)\n#define EvtRtxTimerNew                      EventID(EventLevelAPI,    EvtRtxTimerNo, 0x02U)\n#define EvtRtxTimerCreated                  EventID(EventLevelOp,     EvtRtxTimerNo, 0x04U)\n#define EvtRtxTimerGetName                  EventID(EventLevelAPI,    EvtRtxTimerNo, 0x05U)\n#define EvtRtxTimerStart                    EventID(EventLevelAPI,    EvtRtxTimerNo, 0x07U)\n#define EvtRtxTimerStarted                  EventID(EventLevelOp,     EvtRtxTimerNo, 0x08U)\n#define EvtRtxTimerStop                     EventID(EventLevelAPI,    EvtRtxTimerNo, 0x09U)\n#define EvtRtxTimerStopped                  EventID(EventLevelOp,     EvtRtxTimerNo, 0x0AU)\n#define EvtRtxTimerIsRunning                EventID(EventLevelAPI,    EvtRtxTimerNo, 0x0BU)\n#define EvtRtxTimerDelete                   EventID(EventLevelAPI,    EvtRtxTimerNo, 0x0CU)\n#define EvtRtxTimerDestroyed                EventID(EventLevelOp,     EvtRtxTimerNo, 0x0DU)\n\n/// Event IDs for \"RTX Event Flags\"\n#define EvtRtxEventFlagsError               EventID(EventLevelError,  EvtRtxEventFlagsNo, 0x00U)\n#define EvtRtxEventFlagsNew                 EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x01U)\n#define EvtRtxEventFlagsCreated             EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x03U)\n#define EvtRtxEventFlagsGetName             EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x04U)\n#define EvtRtxEventFlagsSet                 EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x06U)\n#define EvtRtxEventFlagsSetDone             EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x07U)\n#define EvtRtxEventFlagsClear               EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x08U)\n#define EvtRtxEventFlagsClearDone           EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x09U)\n#define EvtRtxEventFlagsGet                 EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x0AU)\n#define EvtRtxEventFlagsWait                EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x0BU)\n#define EvtRtxEventFlagsWaitPending         EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x0CU)\n#define EvtRtxEventFlagsWaitTimeout         EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x0DU)\n#define EvtRtxEventFlagsWaitCompleted       EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x0EU)\n#define EvtRtxEventFlagsWaitNotCompleted    EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x0FU)\n#define EvtRtxEventFlagsDelete              EventID(EventLevelAPI,    EvtRtxEventFlagsNo, 0x10U)\n#define EvtRtxEventFlagsDestroyed           EventID(EventLevelOp,     EvtRtxEventFlagsNo, 0x11U)\n\n/// Event IDs for \"RTX Mutex\"\n#define EvtRtxMutexError                    EventID(EventLevelError,  EvtRtxMutexNo, 0x00U)\n#define EvtRtxMutexNew                      EventID(EventLevelAPI,    EvtRtxMutexNo, 0x01U)\n#define EvtRtxMutexCreated                  EventID(EventLevelOp,     EvtRtxMutexNo, 0x03U)\n#define EvtRtxMutexGetName                  EventID(EventLevelAPI,    EvtRtxMutexNo, 0x04U)\n#define EvtRtxMutexAcquire                  EventID(EventLevelAPI,    EvtRtxMutexNo, 0x06U)\n#define EvtRtxMutexAcquirePending           EventID(EventLevelOp,     EvtRtxMutexNo, 0x07U)\n#define EvtRtxMutexAcquireTimeout           EventID(EventLevelOp,     EvtRtxMutexNo, 0x08U)\n#define EvtRtxMutexAcquired                 EventID(EventLevelOp,     EvtRtxMutexNo, 0x09U)\n#define EvtRtxMutexNotAcquired              EventID(EventLevelOp,     EvtRtxMutexNo, 0x0AU)\n#define EvtRtxMutexRelease                  EventID(EventLevelAPI,    EvtRtxMutexNo, 0x0BU)\n#define EvtRtxMutexReleased                 EventID(EventLevelOp,     EvtRtxMutexNo, 0x0CU)\n#define EvtRtxMutexGetOwner                 EventID(EventLevelAPI,    EvtRtxMutexNo, 0x0DU)\n#define EvtRtxMutexDelete                   EventID(EventLevelAPI,    EvtRtxMutexNo, 0x0EU)\n#define EvtRtxMutexDestroyed                EventID(EventLevelOp,     EvtRtxMutexNo, 0x0FU)\n\n/// Event IDs for \"RTX Semaphore\"\n#define EvtRtxSemaphoreError                EventID(EventLevelError,  EvtRtxSemaphoreNo, 0x00U)\n#define EvtRtxSemaphoreNew                  EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x01U)\n#define EvtRtxSemaphoreCreated              EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x03U)\n#define EvtRtxSemaphoreGetName              EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x04U)\n#define EvtRtxSemaphoreAcquire              EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x06U)\n#define EvtRtxSemaphoreAcquirePending       EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x07U)\n#define EvtRtxSemaphoreAcquireTimeout       EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x08U)\n#define EvtRtxSemaphoreAcquired             EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x09U)\n#define EvtRtxSemaphoreNotAcquired          EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x0AU)\n#define EvtRtxSemaphoreRelease              EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x0BU)\n#define EvtRtxSemaphoreReleased             EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x0CU)\n#define EvtRtxSemaphoreGetCount             EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x0DU)\n#define EvtRtxSemaphoreDelete               EventID(EventLevelAPI,    EvtRtxSemaphoreNo, 0x0EU)\n#define EvtRtxSemaphoreDestroyed            EventID(EventLevelOp,     EvtRtxSemaphoreNo, 0x0FU)\n\n/// Event IDs for \"RTX Memory Pool\"\n#define EvtRtxMemoryPoolError               EventID(EventLevelError,  EvtRtxMemoryPoolNo, 0x00U)\n#define EvtRtxMemoryPoolNew                 EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x01U)\n#define EvtRtxMemoryPoolCreated             EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x03U)\n#define EvtRtxMemoryPoolGetName             EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x04U)\n#define EvtRtxMemoryPoolAlloc               EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x06U)\n#define EvtRtxMemoryPoolAllocPending        EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x07U)\n#define EvtRtxMemoryPoolAllocTimeout        EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x08U)\n#define EvtRtxMemoryPoolAllocated           EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x09U)\n#define EvtRtxMemoryPoolAllocFailed         EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x0AU)\n#define EvtRtxMemoryPoolFree                EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x0BU)\n#define EvtRtxMemoryPoolDeallocated         EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x0CU)\n#define EvtRtxMemoryPoolFreeFailed          EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x0DU)\n#define EvtRtxMemoryPoolGetCapacity         EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x0EU)\n#define EvtRtxMemoryPoolGetBlockSize        EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x0FU)\n#define EvtRtxMemoryPoolGetCount            EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x10U)\n#define EvtRtxMemoryPoolGetSpace            EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x11U)\n#define EvtRtxMemoryPoolDelete              EventID(EventLevelAPI,    EvtRtxMemoryPoolNo, 0x12U)\n#define EvtRtxMemoryPoolDestroyed           EventID(EventLevelOp,     EvtRtxMemoryPoolNo, 0x13U)\n\n/// Event IDs for \"RTX Message Queue\"\n#define EvtRtxMessageQueueError             EventID(EventLevelError,  EvtRtxMessageQueueNo, 0x00U)\n#define EvtRtxMessageQueueNew               EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x01U)\n#define EvtRtxMessageQueueCreated           EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x03U)\n#define EvtRtxMessageQueueGetName           EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x04U)\n#define EvtRtxMessageQueuePut               EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x06U)\n#define EvtRtxMessageQueuePutPending        EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x07U)\n#define EvtRtxMessageQueuePutTimeout        EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x08U)\n#define EvtRtxMessageQueueInsertPending     EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x09U)\n#define EvtRtxMessageQueueInserted          EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0AU)\n#define EvtRtxMessageQueueNotInserted       EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0BU)\n#define EvtRtxMessageQueueGet               EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x0CU)\n#define EvtRtxMessageQueueGetPending        EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0DU)\n#define EvtRtxMessageQueueGetTimeout        EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0EU)\n#define EvtRtxMessageQueueRetrieved         EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x0FU)\n#define EvtRtxMessageQueueNotRetrieved      EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x10U)\n#define EvtRtxMessageQueueGetCapacity       EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x11U)\n#define EvtRtxMessageQueueGetMsgSize        EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x12U)\n#define EvtRtxMessageQueueGetCount          EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x13U)\n#define EvtRtxMessageQueueGetSpace          EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x14U)\n#define EvtRtxMessageQueueReset             EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x15U)\n#define EvtRtxMessageQueueResetDone         EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x16U)\n#define EvtRtxMessageQueueDelete            EventID(EventLevelAPI,    EvtRtxMessageQueueNo, 0x17U)\n#define EvtRtxMessageQueueDestroyed         EventID(EventLevelOp,     EvtRtxMessageQueueNo, 0x18U)\n\n#endif  // RTE_Compiler_EventRecorder\n\n//lint -esym(522, EvrRtx*) \"Functions 'EvrRtx*' can be overridden (do not lack side-effects)\"\n\n\n//  ==== Memory Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_INIT_DISABLE))\n__WEAK void EvrRtxMemoryInit (void *mem, uint32_t size, uint32_t result) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMemoryInit, (uint32_t)mem, size, result, 0U);\n#else\n  (void)mem;\n  (void)size;\n  (void)result;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_ALLOC_DISABLE))\n__WEAK void EvrRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type, void *block) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMemoryAlloc, (uint32_t)mem, size, type, (uint32_t)block);\n#else\n  (void)mem;\n  (void)size;\n  (void)type;\n  (void)block;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_FREE_DISABLE))\n__WEAK void EvrRtxMemoryFree (void *mem, void *block, uint32_t result) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMemoryFree, (uint32_t)mem, (uint32_t)block, result, 0U);\n#else\n  (void)mem;\n  (void)block;\n  (void)result;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_INIT_DISABLE))\n__WEAK void EvrRtxMemoryBlockInit (osRtxMpInfo_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMemoryBlockInit, (uint32_t)mp_info, block_count, block_size, (uint32_t)block_mem);\n#else\n  (void)mp_info;\n  (void)block_count;\n  (void)block_size;\n  (void)block_mem;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_ALLOC_DISABLE))\n__WEAK void EvrRtxMemoryBlockAlloc (osRtxMpInfo_t *mp_info, void *block) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryBlockAlloc, (uint32_t)mp_info, (uint32_t)block);\n#else\n  (void)mp_info;\n  (void)block;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMORY != 0) && !defined(EVR_RTX_MEMORY_BLOCK_FREE_DISABLE))\n__WEAK void EvrRtxMemoryBlockFree (osRtxMpInfo_t *mp_info, void *block, int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMemoryBlockFree, (uint32_t)mp_info, (uint32_t)block, (uint32_t)status, 0U);\n#else\n  (void)mp_info;\n  (void)block;\n  (void)status;\n#endif\n}\n#endif\n\n\n//  ==== Kernel Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_DISABLE))\n__WEAK void EvrRtxKernelError (int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelError, (uint32_t)status, 0U); \n#else\n  (void)status;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZE_DISABLE))\n__WEAK void EvrRtxKernelInitialize (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelInitialize, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INITIALIZED_DISABLE))\n__WEAK void EvrRtxKernelInitialized (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelInitialized, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_INFO_DISABLE))\n__WEAK void EvrRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxKernelGetInfo, (uint32_t)version, (uint32_t)id_buf, id_size, 0U);\n#else\n  (void)version;\n  (void)id_buf;\n  (void)id_size;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_INFO_RETRIEVED_DISABLE))\n__WEAK void EvrRtxKernelInfoRetrieved (const osVersion_t *version, const char *id_buf, uint32_t id_size) {\n#if defined(RTE_Compiler_EventRecorder)\n  if (version != NULL) {\n    (void)EventRecord2(EvtRtxKernelInfoRetrieved, version->api, version->kernel);\n  }\n  if (id_buf != NULL) {\n    (void)EventRecordData(EvtRtxKernelInfoRetrieved_Detail, id_buf, id_size);\n  }\n#else\n  (void)version;\n  (void)id_buf;\n  (void)id_size;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_STATE_DISABLE))\n__WEAK void EvrRtxKernelGetState (osKernelState_t state) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelGetState, (uint32_t)state, 0U);\n#else\n  (void)state;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_START_DISABLE))\n__WEAK void EvrRtxKernelStart (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelStart, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_STARTED_DISABLE))\n__WEAK void EvrRtxKernelStarted (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelStarted, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_DISABLE))\n__WEAK void EvrRtxKernelLock (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelLock, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCKED_DISABLE))\n__WEAK void EvrRtxKernelLocked (int32_t lock) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelLocked, (uint32_t)lock, 0U);\n#else\n  (void)lock;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCK_DISABLE))\n__WEAK void EvrRtxKernelUnlock (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelUnlock, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_UNLOCKED_DISABLE))\n__WEAK void EvrRtxKernelUnlocked (int32_t lock) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelUnlocked, (uint32_t)lock, 0U);\n#else\n  (void)lock;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESTORE_LOCK_DISABLE))\n__WEAK void EvrRtxKernelRestoreLock (int32_t lock) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelRestoreLock, (uint32_t)lock, 0U);\n#else\n  (void)lock;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_LOCK_RESTORED_DISABLE))\n__WEAK void EvrRtxKernelLockRestored (int32_t lock) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelLockRestored, (uint32_t)lock, 0U);\n#else\n  (void)lock;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPEND_DISABLE))\n__WEAK void EvrRtxKernelSuspend (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelSuspend, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_SUSPENDED_DISABLE))\n__WEAK void EvrRtxKernelSuspended (uint32_t sleep_ticks) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelSuspended, sleep_ticks, 0U);\n#else\n  (void)sleep_ticks;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUME_DISABLE))\n__WEAK void EvrRtxKernelResume (uint32_t sleep_ticks) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelResume, sleep_ticks, 0U);\n#else\n  (void)sleep_ticks;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_RESUMED_DISABLE))\n__WEAK void EvrRtxKernelResumed (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelResumed, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_PROTECT_DISABLE))\n__WEAK void EvrRtxKernelProtect (uint32_t safety_class) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelProtect, safety_class, 0U);\n#else\n  (void)safety_class;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_PROTECTED_DISABLE))\n__WEAK void EvrRtxKernelProtected (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelProtected, 0U, 0U);\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE))\n__WEAK void EvrRtxKernelGetTickCount (uint32_t count) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelGetTickCount, count, 0U);\n#else\n  (void)count;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_FREQ_DISABLE))\n__WEAK void EvrRtxKernelGetTickFreq (uint32_t freq) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelGetTickFreq, freq, 0U);\n#else\n  (void)freq;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_COUNT_DISABLE))\n__WEAK void EvrRtxKernelGetSysTimerCount (uint32_t count) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelGetSysTimerCount, count, 0U);\n#else\n  (void)count;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_SYS_TIMER_FREQ_DISABLE))\n__WEAK void EvrRtxKernelGetSysTimerFreq (uint32_t freq) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelGetSysTimerFreq, freq, 0U);\n#else\n  (void)freq;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_ERROR_NOTIFY_DISABLE))\n__WEAK void EvrRtxKernelErrorNotify (uint32_t code, void *object_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelErrorNotify, code, (uint32_t)object_id);\n#else\n  (void)code;\n  (void)object_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_DESTROY_CLASS_DISABLE))\n__WEAK void EvrRtxKernelDestroyClass (uint32_t safety_class, uint32_t mode) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxKernelDestroyClass, safety_class, mode);\n#else\n  (void)safety_class;\n  (void)mode;\n#endif\n}\n#endif\n\n\n//  ==== Thread Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ERROR_DISABLE))\n__WEAK void EvrRtxThreadError (osThreadId_t thread_id, int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadError, (uint32_t)thread_id, (uint32_t)status);\n#else\n  (void)thread_id;\n  (void)status;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_NEW_DISABLE))\n__WEAK void EvrRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxThreadNew, (uint32_t)func, (uint32_t)argument, (uint32_t)attr, 0U);\n#else\n  (void)func;\n  (void)argument;\n  (void)attr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_CREATED_DISABLE))\n__WEAK void EvrRtxThreadCreated (osThreadId_t thread_id, uint32_t thread_addr, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  if (name != NULL) {\n    (void)EventRecord2(EvtRtxThreadCreated_Name, (uint32_t)thread_id, (uint32_t)name);\n  } else {\n    (void)EventRecord2(EvtRtxThreadCreated_Addr, (uint32_t)thread_id, thread_addr);\n  }\n#else\n  (void)thread_id;\n  (void)thread_addr;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_NAME_DISABLE))\n__WEAK void EvrRtxThreadGetName (osThreadId_t thread_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadGetName, (uint32_t)thread_id, (uint32_t)name);\n#else\n  (void)thread_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_CLASS_DISABLE))\n__WEAK void EvrRtxThreadGetClass (osThreadId_t thread_id, uint32_t safety_class) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadGetClass, (uint32_t)thread_id, safety_class);\n#else\n  (void)thread_id;\n  (void)safety_class;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ZONE_DISABLE))\n__WEAK void EvrRtxThreadGetZone (osThreadId_t thread_id, uint32_t zone) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadGetZone, (uint32_t)thread_id, zone);\n#else\n  (void)thread_id;\n  (void)zone;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_ID_DISABLE))\n__WEAK void EvrRtxThreadGetId (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadGetId, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STATE_DISABLE))\n__WEAK void EvrRtxThreadGetState (osThreadId_t thread_id, osThreadState_t state) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadGetState, (uint32_t)thread_id, (uint32_t)state);\n#else\n  (void)thread_id;\n  (void)state;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SIZE_DISABLE))\n__WEAK void EvrRtxThreadGetStackSize (osThreadId_t thread_id, uint32_t stack_size) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadGetStackSize, (uint32_t)thread_id, stack_size);\n#else\n  (void)thread_id;\n  (void)stack_size;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_STACK_SPACE_DISABLE))\n__WEAK void EvrRtxThreadGetStackSpace (osThreadId_t thread_id, uint32_t stack_space) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadGetStackSpace, (uint32_t)thread_id, stack_space);\n#else\n  (void)thread_id;\n  (void)stack_space;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SET_PRIORITY_DISABLE))\n__WEAK void EvrRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadSetPriority, (uint32_t)thread_id, (uint32_t)priority);\n#else\n  (void)thread_id;\n  (void)priority;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIORITY_UPDATED_DISABLE))\n__WEAK void EvrRtxThreadPriorityUpdated (osThreadId_t thread_id, osPriority_t priority) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadPriorityUpdated, (uint32_t)thread_id, (uint32_t)priority);\n#else\n  (void)thread_id;\n  (void)priority;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_PRIORITY_DISABLE))\n__WEAK void EvrRtxThreadGetPriority (osThreadId_t thread_id, osPriority_t priority) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadGetPriority, (uint32_t)thread_id, (uint32_t)priority);\n#else\n  (void)thread_id;\n  (void)priority;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_YIELD_DISABLE))\n__WEAK void EvrRtxThreadYield (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadYield, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_DISABLE))\n__WEAK void EvrRtxThreadSuspend (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadSuspend, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPENDED_DISABLE))\n__WEAK void EvrRtxThreadSuspended (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadSuspended, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_DISABLE))\n__WEAK void EvrRtxThreadResume (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadResume, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUMED_DISABLE))\n__WEAK void EvrRtxThreadResumed (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadResumed, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACH_DISABLE))\n__WEAK void EvrRtxThreadDetach (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadDetach, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DETACHED_DISABLE))\n__WEAK void EvrRtxThreadDetached (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadDetached, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_DISABLE))\n__WEAK void EvrRtxThreadJoin (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadJoin, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOIN_PENDING_DISABLE))\n__WEAK void EvrRtxThreadJoinPending (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadJoinPending, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_JOINED_DISABLE))\n__WEAK void EvrRtxThreadJoined (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadJoined, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_BLOCKED_DISABLE))\n__WEAK void EvrRtxThreadBlocked (osThreadId_t thread_id, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadBlocked, (uint32_t)thread_id, timeout);\n#else\n  (void)thread_id;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_UNBLOCKED_DISABLE))\n__WEAK void EvrRtxThreadUnblocked (osThreadId_t thread_id, uint32_t ret_val) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadUnblocked, (uint32_t)thread_id, ret_val);\n#else\n  (void)thread_id;\n  (void)ret_val;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PREEMPTED_DISABLE))\n__WEAK void EvrRtxThreadPreempted (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadPreempted, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SWITCHED_DISABLE))\n__WEAK void EvrRtxThreadSwitched (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadSwitched, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_EXIT_DISABLE))\n__WEAK void EvrRtxThreadExit (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadExit, 0U, 0U);\n#else\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_DISABLE))\n__WEAK void EvrRtxThreadTerminate (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadTerminate, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DESTROYED_DISABLE))\n__WEAK void EvrRtxThreadDestroyed (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadDestroyed, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FEED_WATCHDOG_DISABLE))\n__WEAK void EvrRtxThreadFeedWatchdog (uint32_t ticks) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFeedWatchdog, ticks, 0U);\n#else\n  (void)ticks;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_FEED_WATCHDOG_DONE_DISABLE))\n__WEAK void EvrRtxThreadFeedWatchdogDone (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFeedWatchdogDone, 0U, 0U);\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PROTECT_PRIVILEGED_DISABLE))\n__WEAK void EvrRtxThreadProtectPrivileged (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadProtectPrivileged, 0U, 0U);\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_PRIVILEGED_PROTECTED_DISABLE))\n__WEAK void EvrRtxThreadPrivilegedProtected (void) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadPrivilegedProtected, 0U, 0U);\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_GET_COUNT_DISABLE))\n__WEAK void EvrRtxThreadGetCount (uint32_t count) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadGetCount, count, 0U);\n#else\n  (void)count;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_ENUMERATE_DISABLE))\n__WEAK void EvrRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items, uint32_t count) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxThreadEnumerate, (uint32_t)thread_array, array_items, count, 0U);\n#else\n  (void)thread_array;\n  (void)array_items;\n  (void)count;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_SUSPEND_CLASS_DISABLE))\n__WEAK void EvrRtxThreadSuspendClass (uint32_t safety_class, uint32_t mode) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadSuspendClass, safety_class, (uint32_t)mode);\n#else\n  (void)safety_class;\n  (void)mode;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_RESUME_CLASS_DISABLE))\n__WEAK void EvrRtxThreadResumeClass (uint32_t safety_class, uint32_t mode) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadResumeClass, safety_class, (uint32_t)mode);\n#else\n  (void)safety_class;\n  (void)mode;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_TERMINATE_ZONE_DISABLE))\n__WEAK void EvrRtxThreadTerminateZone (uint32_t zone) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadTerminateZone, zone, 0U);\n#else\n  (void)zone;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_WATCHDOG_EXPIRED_DISABLE))\n__WEAK void EvrRtxThreadWatchdogExpired (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadWatchdogExpired, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n\n//  ==== Thread Flags Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_ERROR_DISABLE))\n__WEAK void EvrRtxThreadFlagsError (osThreadId_t thread_id, int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFlagsError, (uint32_t)thread_id, (uint32_t)status);\n#else\n  (void)thread_id;\n  (void)status;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DISABLE))\n__WEAK void EvrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFlagsSet, (uint32_t)thread_id, flags);\n#else\n  (void)thread_id;\n  (void)flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_SET_DONE_DISABLE))\n__WEAK void EvrRtxThreadFlagsSetDone (osThreadId_t thread_id, uint32_t thread_flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFlagsSetDone, (uint32_t)thread_id, thread_flags);\n#else\n  (void)thread_id;\n  (void)thread_flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DISABLE))\n__WEAK void EvrRtxThreadFlagsClear (uint32_t flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFlagsClear, flags, 0U);\n#else\n  (void)flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_CLEAR_DONE_DISABLE))\n__WEAK void EvrRtxThreadFlagsClearDone (uint32_t thread_flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFlagsClearDone, thread_flags, 0U);\n#else\n  (void)thread_flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_GET_DISABLE))\n__WEAK void EvrRtxThreadFlagsGet (uint32_t thread_flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFlagsGet, thread_flags, 0U);\n#else\n  (void)thread_flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_DISABLE))\n__WEAK void EvrRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxThreadFlagsWait, flags, options, timeout, 0U);\n#else\n  (void)flags;\n  (void)options;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_PENDING_DISABLE))\n__WEAK void EvrRtxThreadFlagsWaitPending (uint32_t flags, uint32_t options, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxThreadFlagsWaitPending, flags, options, timeout, 0U);\n#else\n  (void)flags;\n  (void)options;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_TIMEOUT_DISABLE))\n__WEAK void EvrRtxThreadFlagsWaitTimeout (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFlagsWaitTimeout, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_COMPLETED_DISABLE))\n__WEAK void EvrRtxThreadFlagsWaitCompleted (uint32_t flags, uint32_t options, uint32_t thread_flags, osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxThreadFlagsWaitCompleted, flags, options, thread_flags, (uint32_t)thread_id);\n#else\n  (void)flags;\n  (void)options;\n  (void)thread_flags;\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THFLAGS != 0) && !defined(EVR_RTX_THREAD_FLAGS_WAIT_NOT_COMPLETED_DISABLE))\n__WEAK void EvrRtxThreadFlagsWaitNotCompleted (uint32_t flags, uint32_t options) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxThreadFlagsWaitNotCompleted, flags, options);\n#else\n  (void)flags;\n  (void)options;\n#endif\n}\n#endif\n\n\n//  ==== Generic Wait Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_ERROR_DISABLE))\n__WEAK void EvrRtxDelayError (int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxDelayError, (uint32_t)status, 0U);\n#else\n  (void)status;\n#endif\n}\n#endif\n\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_DISABLE))\n__WEAK void EvrRtxDelay (uint32_t ticks) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxDelay, ticks, 0U);\n#else\n  (void)ticks;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_DISABLE))\n__WEAK void EvrRtxDelayUntil (uint32_t ticks) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxDelayUntil, ticks, 0U);\n#else\n  (void)ticks;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_STARTED_DISABLE))\n__WEAK void EvrRtxDelayStarted (uint32_t ticks) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxDelayStarted, ticks, 0U);\n#else\n  (void)ticks;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_UNTIL_STARTED_DISABLE))\n__WEAK void EvrRtxDelayUntilStarted (uint32_t ticks) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxDelayUntilStarted, ticks, 0U);\n#else\n  (void)ticks;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_WAIT != 0) && !defined(EVR_RTX_DELAY_COMPLETED_DISABLE))\n__WEAK void EvrRtxDelayCompleted (osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxDelayCompleted, (uint32_t)thread_id, 0U);\n#else\n  (void)thread_id;\n#endif\n}\n#endif\n\n\n//  ==== Timer Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_ERROR_DISABLE))\n__WEAK void EvrRtxTimerError (osTimerId_t timer_id, int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerError, (uint32_t)timer_id, (uint32_t)status);\n#else\n  (void)timer_id;\n  (void)status;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CALLBACK_DISABLE))\n__WEAK void EvrRtxTimerCallback (osTimerFunc_t func, void *argument) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerCallback, (uint32_t)func, (uint32_t)argument);\n#else\n  (void)func;\n  (void)argument;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_NEW_DISABLE))\n__WEAK void EvrRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxTimerNew, (uint32_t)func, (uint32_t)type, (uint32_t)argument, (uint32_t)attr);\n#else\n  (void)func;\n  (void)type;\n  (void)argument;\n  (void)attr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_CREATED_DISABLE))\n__WEAK void EvrRtxTimerCreated (osTimerId_t timer_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerCreated, (uint32_t)timer_id, (uint32_t)name);\n#else\n  (void)timer_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_GET_NAME_DISABLE))\n__WEAK void EvrRtxTimerGetName (osTimerId_t timer_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerGetName, (uint32_t)timer_id, (uint32_t)name);\n#else\n  (void)timer_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_START_DISABLE))\n__WEAK void EvrRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerStart, (uint32_t)timer_id, ticks);\n#else\n  (void)timer_id;\n  (void)ticks;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STARTED_DISABLE))\n__WEAK void EvrRtxTimerStarted (osTimerId_t timer_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerStarted, (uint32_t)timer_id, 0U);\n#else\n  (void)timer_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOP_DISABLE))\n__WEAK void EvrRtxTimerStop (osTimerId_t timer_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerStop, (uint32_t)timer_id, 0U);\n#else\n  (void)timer_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_STOPPED_DISABLE))\n__WEAK void EvrRtxTimerStopped (osTimerId_t timer_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerStopped, (uint32_t)timer_id, 0U);\n#else\n  (void)timer_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_IS_RUNNING_DISABLE))\n__WEAK void EvrRtxTimerIsRunning (osTimerId_t timer_id, uint32_t running) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerIsRunning, (uint32_t)timer_id, running);\n#else\n  (void)timer_id;\n  (void)running;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DELETE_DISABLE))\n__WEAK void EvrRtxTimerDelete (osTimerId_t timer_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerDelete, (uint32_t)timer_id, 0U);\n#else\n  (void)timer_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_TIMER != 0) && !defined(EVR_RTX_TIMER_DESTROYED_DISABLE))\n__WEAK void EvrRtxTimerDestroyed (osTimerId_t timer_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxTimerDestroyed, (uint32_t)timer_id, 0U);\n#else\n  (void)timer_id;\n#endif\n}\n#endif\n\n\n//  ==== Event Flags Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_ERROR_DISABLE))\n__WEAK void EvrRtxEventFlagsError (osEventFlagsId_t ef_id, int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsError, (uint32_t)ef_id, (uint32_t)status);\n#else\n  (void)ef_id;\n  (void)status;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_NEW_DISABLE))\n__WEAK void EvrRtxEventFlagsNew (const osEventFlagsAttr_t *attr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsNew, (uint32_t)attr, 0U);\n#else\n  (void)attr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CREATED_DISABLE))\n__WEAK void EvrRtxEventFlagsCreated (osEventFlagsId_t ef_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsCreated, (uint32_t)ef_id, (uint32_t)name);\n#else\n  (void)ef_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_NAME_DISABLE))\n__WEAK void EvrRtxEventFlagsGetName (osEventFlagsId_t ef_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsGetName, (uint32_t)ef_id, (uint32_t)name);\n#else\n  (void)ef_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DISABLE))\n__WEAK void EvrRtxEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsSet, (uint32_t)ef_id, flags);\n#else\n  (void)ef_id;\n  (void)flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_SET_DONE_DISABLE))\n__WEAK void EvrRtxEventFlagsSetDone (osEventFlagsId_t ef_id, uint32_t event_flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsSetDone, (uint32_t)ef_id, event_flags);\n#else\n  (void)ef_id;\n  (void)event_flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DISABLE))\n__WEAK void EvrRtxEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsClear, (uint32_t)ef_id, flags);\n#else\n  (void)ef_id;\n  (void)flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_CLEAR_DONE_DISABLE))\n__WEAK void EvrRtxEventFlagsClearDone (osEventFlagsId_t ef_id, uint32_t event_flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsClearDone, (uint32_t)ef_id, event_flags);\n#else\n  (void)ef_id;\n  (void)event_flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_GET_DISABLE))\n__WEAK void EvrRtxEventFlagsGet (osEventFlagsId_t ef_id, uint32_t event_flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsGet, (uint32_t)ef_id, event_flags);\n#else\n  (void)ef_id;\n  (void)event_flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_DISABLE))\n__WEAK void EvrRtxEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxEventFlagsWait, (uint32_t)ef_id, flags, options, timeout);\n#else\n  (void)ef_id;\n  (void)flags;\n  (void)options;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_PENDING_DISABLE))\n__WEAK void EvrRtxEventFlagsWaitPending (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxEventFlagsWaitPending, (uint32_t)ef_id, flags, options, timeout);\n#else\n  (void)ef_id;\n  (void)flags;\n  (void)options;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_TIMEOUT_DISABLE))\n__WEAK void EvrRtxEventFlagsWaitTimeout (osEventFlagsId_t ef_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsWaitTimeout, (uint32_t)ef_id, 0U);\n#else\n  (void)ef_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_COMPLETED_DISABLE))\n__WEAK void EvrRtxEventFlagsWaitCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t event_flags) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxEventFlagsWaitCompleted, (uint32_t)ef_id, flags, options, event_flags);\n#else\n  (void)ef_id;\n  (void)flags;\n  (void)options;\n  (void)event_flags;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_WAIT_NOT_COMPLETED_DISABLE))\n__WEAK void EvrRtxEventFlagsWaitNotCompleted (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxEventFlagsWaitNotCompleted, (uint32_t)ef_id, flags, options, 0U);\n#else\n  (void)ef_id;\n  (void)flags;\n  (void)options;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DELETE_DISABLE))\n__WEAK void EvrRtxEventFlagsDelete (osEventFlagsId_t ef_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsDelete, (uint32_t)ef_id, 0U);\n#else\n  (void)ef_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_EVFLAGS != 0) && !defined(EVR_RTX_EVENT_FLAGS_DESTROYED_DISABLE))\n__WEAK void EvrRtxEventFlagsDestroyed (osEventFlagsId_t ef_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxEventFlagsDestroyed, (uint32_t)ef_id, 0U);\n#else\n  (void)ef_id;\n#endif\n}\n#endif\n\n\n//  ==== Mutex Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ERROR_DISABLE))\n__WEAK void EvrRtxMutexError (osMutexId_t mutex_id, int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexError, (uint32_t)mutex_id, (uint32_t)status);\n#else\n  (void)mutex_id;\n  (void)status;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NEW_DISABLE))\n__WEAK void EvrRtxMutexNew (const osMutexAttr_t *attr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexNew, (uint32_t)attr, 0U);\n#else\n  (void)attr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_CREATED_DISABLE))\n__WEAK void EvrRtxMutexCreated (osMutexId_t mutex_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexCreated, (uint32_t)mutex_id, (uint32_t)name);\n#else\n  (void)mutex_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_NAME_DISABLE))\n__WEAK void EvrRtxMutexGetName (osMutexId_t mutex_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexGetName, (uint32_t)mutex_id, (uint32_t)name);\n#else\n  (void)mutex_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_DISABLE))\n__WEAK void EvrRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexAcquire, (uint32_t)mutex_id, timeout);\n#else\n  (void)mutex_id;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_PENDING_DISABLE))\n__WEAK void EvrRtxMutexAcquirePending (osMutexId_t mutex_id, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexAcquirePending, (uint32_t)mutex_id, timeout);\n#else\n  (void)mutex_id;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRE_TIMEOUT_DISABLE))\n__WEAK void EvrRtxMutexAcquireTimeout (osMutexId_t mutex_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexAcquireTimeout, (uint32_t)mutex_id, 0U);\n#else\n  (void)mutex_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_ACQUIRED_DISABLE))\n__WEAK void EvrRtxMutexAcquired (osMutexId_t mutex_id, uint32_t lock) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexAcquired, (uint32_t)mutex_id, lock);\n#else\n  (void)mutex_id;\n  (void)lock;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_NOT_ACQUIRED_DISABLE))\n__WEAK void EvrRtxMutexNotAcquired (osMutexId_t mutex_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexNotAcquired, (uint32_t)mutex_id, 0U);\n#else\n  (void)mutex_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASE_DISABLE))\n__WEAK void EvrRtxMutexRelease (osMutexId_t mutex_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexRelease, (uint32_t)mutex_id, 0U);\n#else\n  (void)mutex_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_RELEASED_DISABLE))\n__WEAK void EvrRtxMutexReleased (osMutexId_t mutex_id, uint32_t lock) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexReleased, (uint32_t)mutex_id, lock);\n#else\n  (void)mutex_id;\n  (void)lock;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_GET_OWNER_DISABLE))\n__WEAK void EvrRtxMutexGetOwner (osMutexId_t mutex_id, osThreadId_t thread_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexGetOwner, (uint32_t)mutex_id, (uint32_t)thread_id);\n#else\n  (void)mutex_id;\n  (void)thread_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DELETE_DISABLE))\n__WEAK void EvrRtxMutexDelete (osMutexId_t mutex_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexDelete, (uint32_t)mutex_id, 0U);\n#else\n  (void)mutex_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MUTEX != 0) && !defined(EVR_RTX_MUTEX_DESTROYED_DISABLE))\n__WEAK void EvrRtxMutexDestroyed (osMutexId_t mutex_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMutexDestroyed, (uint32_t)mutex_id, 0U);\n#else\n  (void)mutex_id;\n#endif\n}\n#endif\n\n\n//  ==== Semaphore Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ERROR_DISABLE))\n__WEAK void EvrRtxSemaphoreError (osSemaphoreId_t semaphore_id, int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreError, (uint32_t)semaphore_id, (uint32_t)status);\n#else\n  (void)semaphore_id;\n  (void)status;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NEW_DISABLE))\n__WEAK void EvrRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxSemaphoreNew, max_count, initial_count, (uint32_t)attr, 0U);\n#else\n  (void)max_count;\n  (void)initial_count;\n  (void)attr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_CREATED_DISABLE))\n__WEAK void EvrRtxSemaphoreCreated (osSemaphoreId_t semaphore_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreCreated, (uint32_t)semaphore_id, (uint32_t)name);\n#else\n  (void)semaphore_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_NAME_DISABLE))\n__WEAK void EvrRtxSemaphoreGetName (osSemaphoreId_t semaphore_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreGetName, (uint32_t)semaphore_id, (uint32_t)name);\n#else\n#endif\n  (void)semaphore_id;\n  (void)name;\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_DISABLE))\n__WEAK void EvrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreAcquire, (uint32_t)semaphore_id, timeout);\n#else\n  (void)semaphore_id;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_PENDING_DISABLE))\n__WEAK void EvrRtxSemaphoreAcquirePending (osSemaphoreId_t semaphore_id, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreAcquirePending, (uint32_t)semaphore_id, (uint32_t)timeout);\n#else\n  (void)semaphore_id;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRE_TIMEOUT_DISABLE))\n__WEAK void EvrRtxSemaphoreAcquireTimeout (osSemaphoreId_t semaphore_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreAcquireTimeout, (uint32_t)semaphore_id, 0U);\n#else\n  (void)semaphore_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_ACQUIRED_DISABLE))\n__WEAK void EvrRtxSemaphoreAcquired (osSemaphoreId_t semaphore_id, uint32_t tokens) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreAcquired, (uint32_t)semaphore_id, tokens);\n#else\n  (void)semaphore_id;\n  (void)tokens;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_NOT_ACQUIRED_DISABLE))\n__WEAK void EvrRtxSemaphoreNotAcquired (osSemaphoreId_t semaphore_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreNotAcquired, (uint32_t)semaphore_id, 0U);\n#else\n  (void)semaphore_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASE_DISABLE))\n__WEAK void EvrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreRelease, (uint32_t)semaphore_id, 0U);\n#else\n  (void)semaphore_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_RELEASED_DISABLE))\n__WEAK void EvrRtxSemaphoreReleased (osSemaphoreId_t semaphore_id, uint32_t tokens) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreReleased, (uint32_t)semaphore_id, tokens);\n#else\n  (void)semaphore_id;\n  (void)tokens;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_GET_COUNT_DISABLE))\n__WEAK void EvrRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id, uint32_t count) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreGetCount, (uint32_t)semaphore_id, count);\n#else\n  (void)semaphore_id;\n  (void)count;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DELETE_DISABLE))\n__WEAK void EvrRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreDelete, (uint32_t)semaphore_id, 0U);\n#else\n  (void)semaphore_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_SEMAPHORE != 0) && !defined(EVR_RTX_SEMAPHORE_DESTROYED_DISABLE))\n__WEAK void EvrRtxSemaphoreDestroyed (osSemaphoreId_t semaphore_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxSemaphoreDestroyed, (uint32_t)semaphore_id, 0U);\n#else\n  (void)semaphore_id;\n#endif\n}\n#endif\n\n\n//  ==== Memory Pool Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ERROR_DISABLE))\n__WEAK void EvrRtxMemoryPoolError (osMemoryPoolId_t mp_id, int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolError, (uint32_t)mp_id, (uint32_t)status);\n#else\n  (void)mp_id;\n  (void)status;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_NEW_DISABLE))\n__WEAK void EvrRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMemoryPoolNew, block_count, block_size, (uint32_t)attr, 0U);\n#else\n  (void)block_count;\n  (void)block_size;\n  (void)attr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_CREATED_DISABLE))\n__WEAK void EvrRtxMemoryPoolCreated (osMemoryPoolId_t mp_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolCreated, (uint32_t)mp_id, (uint32_t)name);\n#else\n  (void)mp_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_NAME_DISABLE))\n__WEAK void EvrRtxMemoryPoolGetName (osMemoryPoolId_t mp_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolGetName, (uint32_t)mp_id, (uint32_t)name);\n#else\n  (void)mp_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_DISABLE))\n__WEAK void EvrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolAlloc, (uint32_t)mp_id, timeout);\n#else\n  (void)mp_id;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_PENDING_DISABLE))\n__WEAK void EvrRtxMemoryPoolAllocPending (osMemoryPoolId_t mp_id, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolAllocPending, (uint32_t)mp_id, timeout);\n#else\n  (void)mp_id;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_TIMEOUT_DISABLE))\n__WEAK void EvrRtxMemoryPoolAllocTimeout (osMemoryPoolId_t mp_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolAllocTimeout, (uint32_t)mp_id, 0U);\n#else\n  (void)mp_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOCATED_DISABLE))\n__WEAK void EvrRtxMemoryPoolAllocated (osMemoryPoolId_t mp_id, void *block) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolAllocated, (uint32_t)mp_id, (uint32_t)block);\n#else\n  (void)mp_id;\n  (void)block;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_ALLOC_FAILED_DISABLE))\n__WEAK void EvrRtxMemoryPoolAllocFailed (osMemoryPoolId_t mp_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolAllocFailed, (uint32_t)mp_id, 0U);\n#else\n  (void)mp_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_DISABLE))\n__WEAK void EvrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolFree, (uint32_t)mp_id, (uint32_t)block);\n#else\n  (void)mp_id;\n  (void)block;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DEALLOCATED_DISABLE))\n__WEAK void EvrRtxMemoryPoolDeallocated (osMemoryPoolId_t mp_id, void *block) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolDeallocated, (uint32_t)mp_id, (uint32_t)block);\n#else\n  (void)mp_id;\n  (void)block;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_FREE_FAILED_DISABLE))\n__WEAK void EvrRtxMemoryPoolFreeFailed (osMemoryPoolId_t mp_id, void *block) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolFreeFailed, (uint32_t)mp_id, (uint32_t)block);\n#else\n  (void)mp_id;\n  (void)block;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_CAPACITY_DISABLE))\n__WEAK void EvrRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id, uint32_t capacity) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolGetCapacity, (uint32_t)mp_id, capacity);\n#else\n  (void)mp_id;\n  (void)capacity;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_BLOCK_SZIE_DISABLE))\n__WEAK void EvrRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id, uint32_t block_size) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolGetBlockSize, (uint32_t)mp_id, block_size);\n#else\n  (void)mp_id;\n  (void)block_size;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_COUNT_DISABLE))\n__WEAK void EvrRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id, uint32_t count) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolGetCount, (uint32_t)mp_id, count);\n#else\n  (void)mp_id;\n  (void)count;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_GET_SPACE_DISABLE))\n__WEAK void EvrRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id, uint32_t space) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolGetSpace, (uint32_t)mp_id, space);\n#else\n  (void)mp_id;\n  (void)space;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DELETE_DISABLE))\n__WEAK void EvrRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolDelete, (uint32_t)mp_id, 0U);\n#else\n  (void)mp_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MEMPOOL != 0) && !defined(EVR_RTX_MEMORY_POOL_DESTROYED_DISABLE))\n__WEAK void EvrRtxMemoryPoolDestroyed (osMemoryPoolId_t mp_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMemoryPoolDestroyed, (uint32_t)mp_id, 0U);\n#else\n  (void)mp_id;\n#endif\n}\n#endif\n\n\n//  ==== Message Queue Events ====\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_ERROR_DISABLE))\n__WEAK void EvrRtxMessageQueueError (osMessageQueueId_t mq_id, int32_t status) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2 (EvtRtxMessageQueueError, (uint32_t)mq_id, (uint32_t)status);\n#else\n  (void)mq_id;\n  (void)status;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NEW_DISABLE))\n__WEAK void EvrRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMessageQueueNew, msg_count, msg_size, (uint32_t)attr, 0U);\n#else\n  (void)msg_count;\n  (void)msg_size;\n  (void)attr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_CREATED_DISABLE))\n__WEAK void EvrRtxMessageQueueCreated (osMessageQueueId_t mq_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueCreated, (uint32_t)mq_id, (uint32_t)name);\n#else\n  (void)mq_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_NAME_DISABLE))\n__WEAK void EvrRtxMessageQueueGetName (osMessageQueueId_t mq_id, const char *name) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueGetName, (uint32_t)mq_id, (uint32_t)name);\n#else\n  (void)mq_id;\n  (void)name;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_DISABLE))\n__WEAK void EvrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMessageQueuePut, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout);\n#else\n  (void)mq_id;\n  (void)msg_ptr;\n  (void)msg_prio;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_PENDING_DISABLE))\n__WEAK void EvrRtxMessageQueuePutPending (osMessageQueueId_t mq_id, const void *msg_ptr, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMessageQueuePutPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U);\n#else\n  (void)mq_id;\n  (void)msg_ptr;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_PUT_TIMEOUT_DISABLE))\n__WEAK void EvrRtxMessageQueuePutTimeout (osMessageQueueId_t mq_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueuePutTimeout, (uint32_t)mq_id, 0U);\n#else\n  (void)mq_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERT_PENDING_DISABLE))\n__WEAK void EvrRtxMessageQueueInsertPending (osMessageQueueId_t mq_id, const void *msg_ptr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueInsertPending, (uint32_t)mq_id, (uint32_t)msg_ptr);\n#else\n  (void)mq_id;\n  (void)msg_ptr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_INSERTED_DISABLE))\n__WEAK void EvrRtxMessageQueueInserted (osMessageQueueId_t mq_id, const void *msg_ptr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueInserted, (uint32_t)mq_id, (uint32_t)msg_ptr);\n#else\n  (void)mq_id;\n  (void)msg_ptr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_INSERTED_DISABLE))\n__WEAK void EvrRtxMessageQueueNotInserted (osMessageQueueId_t mq_id, const void *msg_ptr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueNotInserted, (uint32_t)mq_id, (uint32_t)msg_ptr);\n#else\n  (void)mq_id;\n  (void)msg_ptr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_DISABLE))\n__WEAK void EvrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMessageQueueGet, (uint32_t)mq_id, (uint32_t)msg_ptr, (uint32_t)msg_prio, timeout);\n#else\n  (void)mq_id;\n  (void)msg_ptr;\n  (void)msg_prio;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_PENDING_DISABLE))\n__WEAK void EvrRtxMessageQueueGetPending (osMessageQueueId_t mq_id, void *msg_ptr, uint32_t timeout) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord4(EvtRtxMessageQueueGetPending, (uint32_t)mq_id, (uint32_t)msg_ptr, timeout, 0U);\n#else\n  (void)mq_id;\n  (void)msg_ptr;\n  (void)timeout;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_TIMEOUT_DISABLE))\n__WEAK void EvrRtxMessageQueueGetTimeout (osMessageQueueId_t mq_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueGetTimeout, (uint32_t)mq_id, 0U);\n#else\n  (void)mq_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RETRIEVED_DISABLE))\n__WEAK void EvrRtxMessageQueueRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr);\n#else\n  (void)mq_id;\n  (void)msg_ptr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_NOT_RETRIEVED_DISABLE))\n__WEAK void EvrRtxMessageQueueNotRetrieved (osMessageQueueId_t mq_id, void *msg_ptr) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueNotRetrieved, (uint32_t)mq_id, (uint32_t)msg_ptr);\n#else\n  (void)mq_id;\n  (void)msg_ptr;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_CAPACITY_DISABLE))\n__WEAK void EvrRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id, uint32_t capacity) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueGetCapacity, (uint32_t)mq_id, capacity);\n#else\n  (void)mq_id;\n  (void)capacity;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_MSG_SIZE_DISABLE))\n__WEAK void EvrRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id, uint32_t msg_size) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueGetMsgSize, (uint32_t)mq_id, msg_size);\n#else\n  (void)mq_id;\n  (void)msg_size;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_COUNT_DISABLE))\n__WEAK void EvrRtxMessageQueueGetCount (osMessageQueueId_t mq_id, uint32_t count) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueGetCount, (uint32_t)mq_id, count);\n#else\n  (void)mq_id;\n  (void)count;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_GET_SPACE_DISABLE))\n__WEAK void EvrRtxMessageQueueGetSpace (osMessageQueueId_t mq_id, uint32_t space) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueGetSpace, (uint32_t)mq_id, space);\n#else\n  (void)mq_id;\n  (void)space;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DISABLE))\n__WEAK void EvrRtxMessageQueueReset (osMessageQueueId_t mq_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueReset, (uint32_t)mq_id, 0U);\n#else\n  (void)mq_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_RESET_DONE_DISABLE))\n__WEAK void EvrRtxMessageQueueResetDone (osMessageQueueId_t mq_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueResetDone, (uint32_t)mq_id, 0U);\n#else\n  (void)mq_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DELETE_DISABLE))\n__WEAK void EvrRtxMessageQueueDelete (osMessageQueueId_t mq_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueDelete, (uint32_t)mq_id, 0U);\n#else\n  (void)mq_id;\n#endif\n}\n#endif\n\n#if (!defined(EVR_RTX_DISABLE) && (OS_EVR_MSGQUEUE != 0) && !defined(EVR_RTX_MESSAGE_QUEUE_DESTROYED_DISABLE))\n__WEAK void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id) {\n#if defined(RTE_Compiler_EventRecorder)\n  (void)EventRecord2(EvtRtxMessageQueueDestroyed, (uint32_t)mq_id, 0U);\n#else\n  (void)mq_id;\n#endif\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_kernel.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Kernel functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  OS Runtime Information\nosRtxInfo_t osRtxInfo __attribute__((section(\".data.os\"))) =\n//lint -e{785} \"Initialize only OS ID, OS Version and Kernel State\"\n{ .os_id = osRtxKernelId, .version = osRtxVersionKernel, .kernel.state = osRtxKernelInactive };\n\n\n//  ==== Helper functions ====\n\n/// Block Kernel (disable: thread switching, time tick, post ISR processing).\nstatic void KernelBlock (void) {\n\n  OS_Tick_Disable();\n\n  osRtxInfo.kernel.blocked = 1U;\n  __DSB();\n\n  if (GetPendSV() != 0U) {\n    ClrPendSV();\n    osRtxInfo.kernel.pendSV = 1U;\n  }\n}\n\n/// Unblock Kernel\nstatic void KernelUnblock (void) {\n\n  osRtxInfo.kernel.blocked = 0U;\n  __DSB();\n\n  if (osRtxInfo.kernel.pendSV != 0U) {\n    osRtxInfo.kernel.pendSV = 0U;\n    SetPendSV();\n  }\n\n  OS_Tick_Enable();\n}\n\n// Get Kernel sleep time\nstatic uint32_t GetKernelSleepTime (void) {\n  const os_thread_t *thread;\n  const os_timer_t  *timer;\n  uint32_t           delay;\n\n  delay = osWaitForever;\n\n  // Check Thread Delay list\n  thread = osRtxInfo.thread.delay_list;\n  if (thread != NULL) {\n    delay = thread->delay;\n  }\n\n#ifdef RTX_THREAD_WATCHDOG\n  // Check Thread Watchdog list\n  thread = osRtxInfo.thread.wdog_list;\n  if (thread != NULL) {\n    if (thread->wdog_tick < delay) {\n      delay = thread->wdog_tick;\n    }\n  }\n#endif\n\n  // Check Active Timer list\n  timer = osRtxInfo.timer.list;\n  if (timer != NULL) {\n    if (timer->tick < delay) {\n      delay = timer->tick;\n    }\n  }\n\n  return delay;\n}\n\n\n//  ==== Service Calls ====\n\n/// Initialize the RTOS Kernel.\n/// \\note API identical to osKernelInitialize\nstatic osStatus_t svcRtxKernelInitialize (void) {\n\n  if (osRtxInfo.kernel.state == osRtxKernelReady) {\n    EvrRtxKernelInitialized();\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osOK;\n  }\n  if (osRtxInfo.kernel.state != osRtxKernelInactive) {\n    EvrRtxKernelError((int32_t)osError);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osError;\n  }\n\n#ifdef RTX_TZ_CONTEXT\n  // Initialize Secure Process Stack\n  if (TZ_InitContextSystem_S() == 0U) {\n    EvrRtxKernelError(osRtxErrorTZ_InitContext_S);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osError;\n  }\n#endif\n\n  // Initialize osRtxInfo\n  (void)memset(&osRtxInfo.kernel, 0, sizeof(osRtxInfo) - offsetof(osRtxInfo_t, kernel));\n\n  osRtxInfo.isr_queue.data = osRtxConfig.isr_queue.data;\n  osRtxInfo.isr_queue.max  = osRtxConfig.isr_queue.max;\n\n  osRtxInfo.thread.robin.timeout = osRtxConfig.robin_timeout;\n\n  // Initialize Memory Pools (Variable Block Size)\n  if (osRtxMemoryInit(osRtxConfig.mem.common_addr, osRtxConfig.mem.common_size) != 0U) {\n    osRtxInfo.mem.common = osRtxConfig.mem.common_addr;\n  }\n  if (osRtxMemoryInit(osRtxConfig.mem.stack_addr, osRtxConfig.mem.stack_size) != 0U) {\n    osRtxInfo.mem.stack = osRtxConfig.mem.stack_addr;\n  } else {\n    osRtxInfo.mem.stack = osRtxInfo.mem.common;\n  }\n  if (osRtxMemoryInit(osRtxConfig.mem.mp_data_addr, osRtxConfig.mem.mp_data_size) != 0U) {\n    osRtxInfo.mem.mp_data = osRtxConfig.mem.mp_data_addr;\n  } else {\n    osRtxInfo.mem.mp_data = osRtxInfo.mem.common;\n  }\n  if (osRtxMemoryInit(osRtxConfig.mem.mq_data_addr, osRtxConfig.mem.mq_data_size) != 0U) {\n    osRtxInfo.mem.mq_data = osRtxConfig.mem.mq_data_addr;\n  } else {\n    osRtxInfo.mem.mq_data = osRtxInfo.mem.common;\n  }\n\n  // Initialize Memory Pools (Fixed Block Size)\n  if (osRtxConfig.mpi.stack != NULL) {\n    (void)osRtxMemoryPoolInit(osRtxConfig.mpi.stack,\n                              osRtxConfig.mpi.stack->max_blocks,\n                              osRtxConfig.mpi.stack->block_size,\n                              osRtxConfig.mpi.stack->block_base);\n    osRtxInfo.mpi.stack = osRtxConfig.mpi.stack;\n  }\n  if (osRtxConfig.mpi.thread != NULL) {\n    (void)osRtxMemoryPoolInit(osRtxConfig.mpi.thread,\n                              osRtxConfig.mpi.thread->max_blocks,\n                              osRtxConfig.mpi.thread->block_size,\n                              osRtxConfig.mpi.thread->block_base);\n    osRtxInfo.mpi.thread = osRtxConfig.mpi.thread;\n  }\n  if (osRtxConfig.mpi.timer != NULL) {\n    (void)osRtxMemoryPoolInit(osRtxConfig.mpi.timer,\n                              osRtxConfig.mpi.timer->max_blocks,\n                              osRtxConfig.mpi.timer->block_size,\n                              osRtxConfig.mpi.timer->block_base);\n    osRtxInfo.mpi.timer = osRtxConfig.mpi.timer;\n  }\n  if (osRtxConfig.mpi.event_flags != NULL) {\n    (void)osRtxMemoryPoolInit(osRtxConfig.mpi.event_flags,\n                              osRtxConfig.mpi.event_flags->max_blocks,\n                              osRtxConfig.mpi.event_flags->block_size,\n                              osRtxConfig.mpi.event_flags->block_base);\n    osRtxInfo.mpi.event_flags = osRtxConfig.mpi.event_flags;\n  }\n  if (osRtxConfig.mpi.mutex != NULL) {\n    (void)osRtxMemoryPoolInit(osRtxConfig.mpi.mutex,\n                              osRtxConfig.mpi.mutex->max_blocks,\n                              osRtxConfig.mpi.mutex->block_size,\n                              osRtxConfig.mpi.mutex->block_base);\n    osRtxInfo.mpi.mutex = osRtxConfig.mpi.mutex;\n  }\n  if (osRtxConfig.mpi.semaphore != NULL) {\n    (void)osRtxMemoryPoolInit(osRtxConfig.mpi.semaphore,\n                              osRtxConfig.mpi.semaphore->max_blocks,\n                              osRtxConfig.mpi.semaphore->block_size,\n                              osRtxConfig.mpi.semaphore->block_base);\n    osRtxInfo.mpi.semaphore = osRtxConfig.mpi.semaphore;\n  }\n  if (osRtxConfig.mpi.memory_pool != NULL) {\n    (void)osRtxMemoryPoolInit(osRtxConfig.mpi.memory_pool,\n                              osRtxConfig.mpi.memory_pool->max_blocks,\n                              osRtxConfig.mpi.memory_pool->block_size,\n                              osRtxConfig.mpi.memory_pool->block_base);\n    osRtxInfo.mpi.memory_pool = osRtxConfig.mpi.memory_pool;\n  }\n  if (osRtxConfig.mpi.message_queue != NULL) {\n    (void)osRtxMemoryPoolInit(osRtxConfig.mpi.message_queue,\n                              osRtxConfig.mpi.message_queue->max_blocks,\n                              osRtxConfig.mpi.message_queue->block_size,\n                              osRtxConfig.mpi.message_queue->block_base);\n    osRtxInfo.mpi.message_queue = osRtxConfig.mpi.message_queue;\n  }\n\n  osRtxInfo.kernel.state = osRtxKernelReady;\n\n  EvrRtxKernelInitialized();\n\n  return osOK;\n}\n\n///  Get RTOS Kernel Information.\n/// \\note API identical to osKernelGetInfo\nstatic osStatus_t svcRtxKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {\n  uint32_t size;\n\n  if (version != NULL) {\n    version->api    = osRtxVersionAPI;\n    version->kernel = osRtxVersionKernel;\n  }\n\n  if ((id_buf != NULL) && (id_size != 0U)) {\n    if (id_size > sizeof(osRtxKernelId)) {\n      size = sizeof(osRtxKernelId);\n    } else {\n      size = id_size;\n    }\n    (void)memcpy(id_buf, osRtxKernelId, size);\n  }\n\n  EvrRtxKernelInfoRetrieved(version, id_buf, id_size);\n\n  return osOK;\n}\n\n/// Get the current RTOS Kernel state.\n/// \\note API identical to osKernelGetState\nstatic osKernelState_t svcRtxKernelGetState (void) {\n  osKernelState_t state = osRtxKernelState();\n  EvrRtxKernelGetState(state);\n  return state;\n}\n\n/// Start the RTOS Kernel scheduler.\n/// \\note API identical to osKernelStart\nstatic osStatus_t svcRtxKernelStart (void) {\n  os_thread_t *thread;\n\n  if (osRtxInfo.kernel.state != osRtxKernelReady) {\n    EvrRtxKernelError(osRtxErrorKernelNotReady);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osError;\n  }\n\n  // Thread startup (Idle and Timer Thread)\n  if (!osRtxThreadStartup()) {\n    EvrRtxKernelError((int32_t)osError);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osError;\n  }\n\n  // Setup SVC and PendSV System Service Calls\n  SVC_Setup();\n\n  // Setup RTOS Tick\n  if (OS_Tick_Setup(osRtxConfig.tick_freq, OS_TICK_HANDLER) != 0) {\n    EvrRtxKernelError((int32_t)osError);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osError;\n  }\n  osRtxInfo.tick_irqn = OS_Tick_GetIRQn();\n\n  // Enable RTOS Tick\n  OS_Tick_Enable();\n\n  // Switch to Ready Thread with highest Priority\n  thread = osRtxThreadListGet(&osRtxInfo.thread.ready);\n  osRtxThreadSwitch(thread);\n\n  osRtxInfo.kernel.state = osRtxKernelRunning;\n\n  EvrRtxKernelStarted();\n\n  return osOK;\n}\n\n/// Lock the RTOS Kernel scheduler.\n/// \\note API identical to osKernelLock\nstatic int32_t svcRtxKernelLock (void) {\n  int32_t lock;\n\n  switch (osRtxInfo.kernel.state) {\n    case osRtxKernelRunning:\n#ifdef RTX_SAFETY_CLASS\n      // Check the safety class\n      if ((osRtxThreadGetRunning()->attr >> osRtxAttrClass_Pos) <\n          (osRtxInfo.kernel.protect >> osRtxKernelProtectClass_Pos)) {\n        EvrRtxKernelError((int32_t)osErrorSafetyClass);\n        lock = (int32_t)osErrorSafetyClass;\n        break;\n      }\n#endif\n      osRtxInfo.kernel.state = osRtxKernelLocked;\n      EvrRtxKernelLocked(0);\n      lock = 0;\n      break;\n    case osRtxKernelLocked:\n      EvrRtxKernelLocked(1);\n      lock = 1;\n      break;\n    default:\n      EvrRtxKernelError((int32_t)osError);\n      lock = (int32_t)osError;\n      break;\n  }\n  return lock;\n}\n\n/// Unlock the RTOS Kernel scheduler.\n/// \\note API identical to osKernelUnlock\nstatic int32_t svcRtxKernelUnlock (void) {\n  int32_t lock;\n\n  switch (osRtxInfo.kernel.state) {\n    case osRtxKernelRunning:\n      EvrRtxKernelUnlocked(0);\n      lock = 0;\n      break;\n    case osRtxKernelLocked:\n      osRtxInfo.kernel.state = osRtxKernelRunning;\n      EvrRtxKernelUnlocked(1);\n      lock = 1;\n      break;\n    default:\n      EvrRtxKernelError((int32_t)osError);\n      lock = (int32_t)osError;\n      break;\n  }\n  return lock;\n}\n\n/// Restore the RTOS Kernel scheduler lock state.\n/// \\note API identical to osKernelRestoreLock\nstatic int32_t svcRtxKernelRestoreLock (int32_t lock) {\n  int32_t lock_new;\n\n  switch (osRtxInfo.kernel.state) {\n    case osRtxKernelRunning:\n    case osRtxKernelLocked:\n#ifdef RTX_SAFETY_CLASS\n      // Check the safety class\n      if ((osRtxThreadGetRunning()->attr >> osRtxAttrClass_Pos) <\n          (osRtxInfo.kernel.protect >> osRtxKernelProtectClass_Pos)) {\n        EvrRtxKernelError((int32_t)osErrorSafetyClass);\n        lock_new = (int32_t)osErrorSafetyClass;\n        break;\n      }\n#endif\n      switch (lock) {\n        case 0:\n          osRtxInfo.kernel.state = osRtxKernelRunning;\n          EvrRtxKernelLockRestored(0);\n          lock_new = 0;\n          break;\n        case 1:\n          osRtxInfo.kernel.state = osRtxKernelLocked;\n          EvrRtxKernelLockRestored(1);\n          lock_new = 1;\n          break;\n        default:\n          EvrRtxKernelError((int32_t)osError);\n          lock_new = (int32_t)osError;\n          break;\n      }\n      break;\n    default:\n      EvrRtxKernelError((int32_t)osError);\n      lock_new = (int32_t)osError;\n      break;\n  }\n  return lock_new;\n}\n\n/// Suspend the RTOS Kernel scheduler.\n/// \\note API identical to osKernelSuspend\nstatic uint32_t svcRtxKernelSuspend (void) {\n  uint32_t delay;\n\n  if (osRtxInfo.kernel.state != osRtxKernelRunning) {\n    EvrRtxKernelError(osRtxErrorKernelNotRunning);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check the safety class\n  if ((osRtxThreadGetRunning()->attr >> osRtxAttrClass_Pos) <\n      (osRtxInfo.kernel.protect >> osRtxKernelProtectClass_Pos)) {\n    EvrRtxKernelError((int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n#endif\n\n  KernelBlock();\n\n  osRtxInfo.kernel.state = osRtxKernelSuspended;\n\n  delay = GetKernelSleepTime();\n\n  EvrRtxKernelSuspended(delay);\n\n  return delay;\n}\n\n/// Resume the RTOS Kernel scheduler.\n/// \\note API identical to osKernelResume\nstatic void svcRtxKernelResume (uint32_t sleep_ticks) {\n  os_thread_t *thread;\n  os_timer_t  *timer;\n  uint32_t     delay;\n  uint32_t     ticks, kernel_tick;\n\n  if (osRtxInfo.kernel.state != osRtxKernelSuspended) {\n    EvrRtxKernelResumed();\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return;\n  }\n\n  delay = GetKernelSleepTime();\n  if (sleep_ticks >= delay) {\n    ticks = delay - 1U;\n  } else {\n    ticks = sleep_ticks;\n  }\n\n  // Update Thread Delay sleep ticks\n  thread = osRtxInfo.thread.delay_list;\n  if (thread != NULL) {\n    thread->delay -= ticks;\n  }\n\n  // Update Timer sleep ticks\n  timer = osRtxInfo.timer.list;\n  if (timer != NULL) {\n    timer->tick -= ticks;\n  }\n\n#ifdef RTX_THREAD_WATCHDOG\n  // Update Thread Watchdog sleep ticks\n  thread = osRtxInfo.thread.wdog_list;\n  if (thread != NULL) {\n    thread->wdog_tick -= ticks;\n  }\n#endif\n\n  kernel_tick = osRtxInfo.kernel.tick + sleep_ticks;\n  osRtxInfo.kernel.tick += ticks;\n\n  while (osRtxInfo.kernel.tick != kernel_tick) {\n    osRtxInfo.kernel.tick++;\n\n    // Process Thread Delays\n    osRtxThreadDelayTick();\n\n    // Process Timers\n    if (osRtxInfo.timer.tick != NULL) {\n      osRtxInfo.timer.tick();\n    }\n\n#ifdef RTX_THREAD_WATCHDOG\n    // Process Watchdog Timers\n    osRtxThreadWatchdogTick();\n#endif\n  }\n\n  osRtxInfo.kernel.state = osRtxKernelRunning;\n\n  osRtxThreadDispatch(NULL);\n\n  KernelUnblock();\n\n  EvrRtxKernelResumed();\n}\n\n#ifdef RTX_SAFETY_CLASS\n\n/// Protect the RTOS Kernel scheduler access.\n/// \\note API identical to osKernelProtect\nstatic osStatus_t svcRtxKernelProtect (uint32_t safety_class) {\n  uint32_t   thread_class;\n  osStatus_t status;\n\n  // Check parameters\n  if (safety_class > 0x0FU) {\n    EvrRtxKernelError((int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  switch (osRtxInfo.kernel.state) {\n    case osRtxKernelInactive:\n      EvrRtxKernelError(osRtxErrorKernelNotReady);\n      status = osError;\n      break;\n    case osRtxKernelReady:\n      osRtxInfo.kernel.protect &= (uint8_t)~osRtxKernelProtectClass_Msk;\n      osRtxInfo.kernel.protect |= (uint8_t)(safety_class << osRtxKernelProtectClass_Pos);\n      EvrRtxKernelProtected();\n      status = osOK;\n      break;\n    case osRtxKernelRunning:\n      // Check the safety class\n      thread_class = (uint32_t)osRtxThreadGetRunning()->attr >> osRtxAttrClass_Pos;\n      if ((safety_class > thread_class) ||\n          (thread_class < ((uint32_t)osRtxInfo.kernel.protect >> osRtxKernelProtectClass_Pos))) {\n        EvrRtxKernelError((int32_t)osErrorSafetyClass);\n        status = osErrorSafetyClass;\n        break;\n      }\n      osRtxInfo.kernel.protect &= (uint8_t)~osRtxKernelProtectClass_Msk;\n      osRtxInfo.kernel.protect |= (uint8_t)(safety_class << osRtxKernelProtectClass_Pos);\n      EvrRtxKernelProtected();\n      status = osOK;\n      break;\n    case osRtxKernelLocked:\n    case osRtxKernelSuspended:\n      EvrRtxKernelError(osRtxErrorKernelNotRunning);\n      status = osError;\n      break;\n    default:\n      // Should never come here\n      status = osError;\n      break;\n  }\n\n  return status;\n}\n\n/// Destroy objects for specified safety classes.\n/// \\note API identical to osKernelDestroyClass\nstatic osStatus_t svcRtxKernelDestroyClass (uint32_t safety_class, uint32_t mode) {\n  os_thread_t *thread;\n  os_thread_t *thread_next;\n\n  // Check parameters\n  if (safety_class > 0x0FU) {\n    EvrRtxKernelError((int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Check running thread safety class (when called from thread)\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) && IsSVCallIrq()) {\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         (((thread->attr >> osRtxAttrClass_Pos) + 1U) < (uint8_t)safety_class))) {\n      EvrRtxKernelError((int32_t)osErrorSafetyClass);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return osErrorSafetyClass;\n    }\n  }\n\n  // Delete RTOS objects for safety class\n  osRtxMutexDeleteClass(safety_class, mode);\n  osRtxSemaphoreDeleteClass(safety_class, mode);\n  osRtxMemoryPoolDeleteClass(safety_class, mode);\n  osRtxMessageQueueDeleteClass(safety_class, mode);\n  osRtxEventFlagsDeleteClass(safety_class, mode);\n  osRtxTimerDeleteClass(safety_class, mode);\n\n  // Threads in Wait List\n  thread = osRtxInfo.thread.wait_list;\n  while (thread != NULL) {\n    thread_next = thread->delay_next;\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class))) {\n      osRtxThreadListRemove(thread);\n      osRtxThreadDelayRemove(thread);\n#ifdef RTX_THREAD_WATCHDOG\n      osRtxThreadWatchdogRemove(thread);\n#endif\n      osRtxMutexOwnerRelease(thread->mutex_list);\n      osRtxThreadJoinWakeup(thread);\n      osRtxThreadDestroy(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Threads in Delay List\n  thread = osRtxInfo.thread.delay_list;\n  while (thread != NULL) {\n    thread_next = thread->delay_next;\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class))) {\n      osRtxThreadListRemove(thread);\n      osRtxThreadDelayRemove(thread);\n#ifdef RTX_THREAD_WATCHDOG\n      osRtxThreadWatchdogRemove(thread);\n#endif\n      osRtxMutexOwnerRelease(thread->mutex_list);\n      osRtxThreadJoinWakeup(thread);\n      osRtxThreadDestroy(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Threads in Ready List\n  thread = osRtxInfo.thread.ready.thread_list;\n  while (thread != NULL) {\n    thread_next = thread->thread_next;\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class))) {\n      osRtxThreadListRemove(thread);\n#ifdef RTX_THREAD_WATCHDOG\n      osRtxThreadWatchdogRemove(thread);\n#endif\n      osRtxMutexOwnerRelease(thread->mutex_list);\n      osRtxThreadJoinWakeup(thread);\n      osRtxThreadDestroy(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Running Thread\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((((mode & osSafetyWithSameClass)  != 0U) &&\n        ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n       (((mode & osSafetyWithLowerClass) != 0U) &&\n        ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class)))) {\n    if ((osRtxKernelGetState() != osRtxKernelRunning) ||\n        (osRtxInfo.thread.ready.thread_list == NULL)) {\n      osRtxThreadDispatch(NULL);\n      EvrRtxKernelError((int32_t)osErrorResource);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return osErrorResource;\n    }\n#ifdef RTX_THREAD_WATCHDOG\n    osRtxThreadWatchdogRemove(thread);\n#endif\n    osRtxMutexOwnerRelease(thread->mutex_list);\n    osRtxThreadJoinWakeup(thread);\n    // Switch to next Ready Thread\n    osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));\n    // Update Stack Pointer\n    thread->sp = __get_PSP();\n#ifdef RTX_STACK_CHECK\n    // Check Stack usage\n    if (!osRtxThreadStackCheck(thread)) {\n      osRtxThreadSetRunning(osRtxInfo.thread.run.next);\n      (void)osRtxKernelErrorNotify(osRtxErrorStackOverflow, thread);\n    }\n#endif\n    // Mark running thread as deleted\n    osRtxThreadSetRunning(NULL);\n    // Destroy Thread\n    osRtxThreadDestroy(thread);\n  } else {\n    osRtxThreadDispatch(NULL);\n  }\n\n  return osOK;\n}\n\n#endif\n\n/// Get the RTOS kernel tick count.\n/// \\note API identical to osKernelGetTickCount\nstatic uint32_t svcRtxKernelGetTickCount (void) {\n  EvrRtxKernelGetTickCount(osRtxInfo.kernel.tick);\n  return osRtxInfo.kernel.tick;\n}\n\n/// Get the RTOS kernel tick frequency.\n/// \\note API identical to osKernelGetTickFreq\nstatic uint32_t svcRtxKernelGetTickFreq (void) {\n  EvrRtxKernelGetTickFreq(osRtxConfig.tick_freq);\n  return osRtxConfig.tick_freq;\n}\n\n/// Get the RTOS kernel system timer count.\n/// \\note API identical to osKernelGetSysTimerCount\nstatic uint32_t svcRtxKernelGetSysTimerCount (void) {\n  uint32_t tick;\n  uint32_t count;\n\n  tick  = (uint32_t)osRtxInfo.kernel.tick;\n  count = OS_Tick_GetCount();\n  if (OS_Tick_GetOverflow() != 0U) {\n    count = OS_Tick_GetCount();\n    tick++;\n  }\n  count += tick * OS_Tick_GetInterval();\n  EvrRtxKernelGetSysTimerCount(count);\n  return count;\n}\n\n/// Get the RTOS kernel system timer frequency.\n/// \\note API identical to osKernelGetSysTimerFreq\nstatic uint32_t svcRtxKernelGetSysTimerFreq (void) {\n  uint32_t freq = OS_Tick_GetClock();\n  EvrRtxKernelGetSysTimerFreq(freq);\n  return freq;\n}\n\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_0 (KernelInitialize,       osStatus_t)\nSVC0_3 (KernelGetInfo,          osStatus_t, osVersion_t *, char *, uint32_t)\nSVC0_0 (KernelStart,            osStatus_t)\nSVC0_0 (KernelLock,             int32_t)\nSVC0_0 (KernelUnlock,           int32_t)\nSVC0_1 (KernelRestoreLock,      int32_t, int32_t)\nSVC0_0 (KernelSuspend,          uint32_t)\nSVC0_1N(KernelResume,           void, uint32_t)\n#ifdef RTX_SAFETY_CLASS\nSVC0_1 (KernelProtect,          osStatus_t, uint32_t)\nSVC0_2 (KernelDestroyClass,     osStatus_t, uint32_t, uint32_t)\n#endif\nSVC0_0 (KernelGetState,         osKernelState_t)\nSVC0_0 (KernelGetTickCount,     uint32_t)\nSVC0_0 (KernelGetTickFreq,      uint32_t)\nSVC0_0 (KernelGetSysTimerCount, uint32_t)\nSVC0_0 (KernelGetSysTimerFreq,  uint32_t)\n//lint --flb \"Library End\"\n\n\n//  ==== Library functions ====\n\n/// RTOS Kernel Pre-Initialization Hook\n//lint -esym(759,osRtxKernelBeforeInit) \"Prototype in header\"\n//lint -esym(765,osRtxKernelBeforeInit) \"Global scope (can be overridden)\"\n//lint -esym(522,osRtxKernelBeforeInit) \"Can be overridden (do not lack side-effects)\"\n__WEAK void osRtxKernelBeforeInit (void) {\n}\n\n/// RTOS Kernel Error Notification Handler\n/// \\note API identical to osRtxErrorNotify\nuint32_t osRtxKernelErrorNotify (uint32_t code, void *object_id) {\n  EvrRtxKernelErrorNotify(code, object_id);\n  return osRtxErrorNotify(code, object_id);\n}\n\n\n//  ==== Public API ====\n\n/// Initialize the RTOS Kernel.\nosStatus_t osKernelInitialize (void) {\n  osStatus_t status;\n\n  osRtxKernelBeforeInit();\n  EvrRtxKernelInitialize();\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxKernelError((int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcKernelInitialize();\n  }\n  return status;\n}\n\n///  Get RTOS Kernel Information.\nosStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {\n  osStatus_t status;\n\n  EvrRtxKernelGetInfo(version, id_buf, id_size);\n  if (IsException() || IsIrqMasked() || IsPrivileged()) {\n    status = svcRtxKernelGetInfo(version, id_buf, id_size);\n  } else {\n    status =  __svcKernelGetInfo(version, id_buf, id_size);\n  }\n  return status;\n}\n\n/// Get the current RTOS Kernel state.\nosKernelState_t osKernelGetState (void) {\n  osKernelState_t state;\n\n  if (IsException() || IsIrqMasked() || IsPrivileged()) {\n    state = svcRtxKernelGetState();\n  } else {\n    state =  __svcKernelGetState();\n  }\n  return state;\n}\n\n/// Start the RTOS Kernel scheduler.\nosStatus_t osKernelStart (void) {\n  osStatus_t status;\n\n  EvrRtxKernelStart();\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxKernelError((int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcKernelStart();\n  }\n  return status;\n}\n\n/// Lock the RTOS Kernel scheduler.\nint32_t osKernelLock (void) {\n  int32_t lock;\n\n  EvrRtxKernelLock();\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxKernelError((int32_t)osErrorISR);\n    lock = (int32_t)osErrorISR;\n  } else {\n    lock = __svcKernelLock();\n  }\n  return lock;\n}\n\n/// Unlock the RTOS Kernel scheduler.\nint32_t osKernelUnlock (void) {\n  int32_t lock;\n\n  EvrRtxKernelUnlock();\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxKernelError((int32_t)osErrorISR);\n    lock = (int32_t)osErrorISR;\n  } else {\n    lock = __svcKernelUnlock();\n  }\n  return lock;\n}\n\n/// Restore the RTOS Kernel scheduler lock state.\nint32_t osKernelRestoreLock (int32_t lock) {\n  int32_t lock_new;\n\n  EvrRtxKernelRestoreLock(lock);\n  if (IsException() || IsIrqMasked()) {\n    if (IsFault() || IsSVCallIrq() || IsPendSvIrq() || IsTickIrq(osRtxInfo.tick_irqn)) {\n      lock_new = svcRtxKernelRestoreLock(lock);\n    } else {\n      EvrRtxKernelError((int32_t)osErrorISR);\n      lock_new = (int32_t)osErrorISR;\n    }\n  } else {\n    lock_new   =  __svcKernelRestoreLock(lock);\n  }\n  return lock_new;\n}\n\n/// Suspend the RTOS Kernel scheduler.\nuint32_t osKernelSuspend (void) {\n  uint32_t ticks;\n\n  EvrRtxKernelSuspend();\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxKernelError((int32_t)osErrorISR);\n    ticks = 0U;\n  } else {\n    ticks = __svcKernelSuspend();\n  }\n  return ticks;\n}\n\n/// Resume the RTOS Kernel scheduler.\nvoid osKernelResume (uint32_t sleep_ticks) {\n\n  EvrRtxKernelResume(sleep_ticks);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxKernelError((int32_t)osErrorISR);\n  } else {\n    __svcKernelResume(sleep_ticks);\n  }\n}\n\n#ifdef RTX_SAFETY_CLASS\n\n/// Protect the RTOS Kernel scheduler access.\nosStatus_t osKernelProtect (uint32_t safety_class) {\n  osStatus_t status;\n\n  EvrRtxKernelProtect(safety_class);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxKernelError((int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcKernelProtect(safety_class);\n  }\n  return status;\n}\n\n/// Destroy RTOS objects for specified safety classes.\nosStatus_t osKernelDestroyClass (uint32_t safety_class, uint32_t mode) {\n  osStatus_t status;\n\n  EvrRtxKernelDestroyClass(safety_class, mode);\n  if (IsException() || IsIrqMasked()) {\n    if (IsTickIrq(osRtxInfo.tick_irqn)) {\n      status = svcRtxKernelDestroyClass(safety_class, mode);\n    } else {\n      EvrRtxKernelError((int32_t)osErrorISR);\n      status = osErrorISR;\n    }\n  } else {\n    status   =  __svcKernelDestroyClass(safety_class, mode);\n  }\n  return status;\n}\n\n#endif\n\n/// Get the RTOS kernel tick count.\nuint32_t osKernelGetTickCount (void) {\n  uint32_t count;\n\n  if (IsException() || IsIrqMasked()) {\n    count = svcRtxKernelGetTickCount();\n  } else {\n    count =  __svcKernelGetTickCount();\n  }\n  return count;\n}\n\n/// Get the RTOS kernel tick frequency.\nuint32_t osKernelGetTickFreq (void) {\n  uint32_t freq;\n\n  if (IsException() || IsIrqMasked()) {\n    freq = svcRtxKernelGetTickFreq();\n  } else {\n    freq =  __svcKernelGetTickFreq();\n  }\n  return freq;\n}\n\n/// Get the RTOS kernel system timer count.\nuint32_t osKernelGetSysTimerCount (void) {\n  uint32_t count;\n\n  if (IsException() || IsIrqMasked()) {\n    count = svcRtxKernelGetSysTimerCount();\n  } else {\n    count =  __svcKernelGetSysTimerCount();\n  }\n  return count;\n}\n\n/// Get the RTOS kernel system timer frequency.\nuint32_t osKernelGetSysTimerFreq (void) {\n  uint32_t freq;\n\n  if (IsException() || IsIrqMasked()) {\n    freq = svcRtxKernelGetSysTimerFreq();\n  } else {\n    freq =  __svcKernelGetSysTimerFreq();\n  }\n  return freq;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_lib.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Library Configuration\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_os.h\"\n\n#ifdef    CMSIS_device_header\n#include  CMSIS_device_header\n#else\n#include \"cmsis_compiler.h\"\n#endif\n\n#ifdef    RTE_Compiler_EventRecorder\n#include \"EventRecorder.h\"\n#include \"EventRecorderConf.h\"\n#endif\n#include \"rtx_evr.h\"\n\n\n// System Configuration\n// ====================\n\n// Dynamic Memory\n#if (OS_DYNAMIC_MEM_SIZE != 0)\n#if ((OS_DYNAMIC_MEM_SIZE % 8) != 0)\n#error \"Invalid Dynamic Memory size!\"\n#endif\nstatic uint64_t os_mem[OS_DYNAMIC_MEM_SIZE/8] \\\n__attribute__((section(\".bss.os\")));\n#endif\n\n// Kernel Tick Frequency\n#if (OS_TICK_FREQ < 1)\n#error \"Invalid Kernel Tick Frequency!\"\n#endif\n\n// ISR FIFO Queue\n#if (OS_ISR_FIFO_QUEUE < 4)\n#error \"Invalid ISR FIFO Queue size!\"\n#endif\nstatic void *os_isr_queue[OS_ISR_FIFO_QUEUE] \\\n__attribute__((section(\".bss.os\")));\n\n\n// Thread Configuration\n// ====================\n\n#if (((OS_STACK_SIZE % 8) != 0) || (OS_STACK_SIZE < 72))\n#error \"Invalid default Thread Stack size!\"\n#endif\n\n#if (((OS_IDLE_THREAD_STACK_SIZE % 8) != 0) || (OS_IDLE_THREAD_STACK_SIZE < 72))\n#error \"Invalid Idle Thread Stack size!\"\n#endif\n\n\n#if (OS_THREAD_OBJ_MEM != 0)\n\n#if (OS_THREAD_NUM == 0)\n#error \"Invalid number of user Threads!\"\n#endif\n\n#if ((OS_THREAD_USER_STACK_SIZE != 0) && ((OS_THREAD_USER_STACK_SIZE % 8) != 0))\n#error \"Invalid total Stack size!\"\n#endif\n\n// Thread Control Blocks\nstatic osRtxThread_t os_thread_cb[OS_THREAD_NUM] \\\n__attribute__((section(\".bss.os.thread.cb\")));\n\n// Thread Default Stack\n#if (OS_THREAD_DEF_STACK_NUM != 0)\nstatic uint64_t os_thread_def_stack[(OS_THREAD_DEF_STACK_NUM*OS_STACK_SIZE)/8] \\\n__attribute__((section(\".bss.os.thread.stack\")));\n#endif\n\n// Memory Pool for Thread Control Blocks\nstatic osRtxMpInfo_t os_mpi_thread \\\n__attribute__((section(\".data.os.thread.mpi\"))) =\n{ (uint32_t)OS_THREAD_NUM, 0U, (uint32_t)osRtxThreadCbSize, &os_thread_cb[0], NULL, NULL };\n\n// Memory Pool for Thread Default Stack\n#if (OS_THREAD_DEF_STACK_NUM != 0)\nstatic osRtxMpInfo_t os_mpi_def_stack \\\n__attribute__((section(\".data.os.thread.mpi\"))) =\n{ (uint32_t)OS_THREAD_DEF_STACK_NUM, 0U, (uint32_t)OS_STACK_SIZE, &os_thread_def_stack[0], NULL, NULL };\n#endif\n\n// Memory Pool for Thread Stack\n#if (OS_THREAD_USER_STACK_SIZE != 0)\nstatic uint64_t os_thread_stack[(16 + (8*OS_THREAD_NUM) + OS_THREAD_USER_STACK_SIZE)/8] \\\n__attribute__((section(\".bss.os.thread.stack\")));\n#endif\n\n#endif  // (OS_THREAD_OBJ_MEM != 0)\n\n\n// Idle Thread Control Block\nstatic osRtxThread_t os_idle_thread_cb \\\n__attribute__((section(\".bss.os.thread.cb\")));\n\n// Idle Thread Stack\nstatic uint64_t os_idle_thread_stack[OS_IDLE_THREAD_STACK_SIZE/8] \\\n__attribute__((section(\".bss.os.thread.idle.stack\")));\n\n// Idle Thread Attributes\nstatic const osThreadAttr_t os_idle_thread_attr = {\n  //lint -e{835} -e{845} \"Zero argument to operator\"\n#if defined(OS_IDLE_THREAD_NAME)\n  OS_IDLE_THREAD_NAME,\n#else\n  NULL,\n#endif\n#ifdef RTX_SAFETY_CLASS\n  osSafetyClass((uint32_t)OS_IDLE_THREAD_CLASS) |\n#endif\n#ifdef RTX_EXECUTION_ZONE\n  osThreadZone((uint32_t)OS_IDLE_THREAD_ZONE)   |\n#endif\n  osThreadDetached,\n  &os_idle_thread_cb,\n  (uint32_t)sizeof(os_idle_thread_cb),\n  &os_idle_thread_stack[0],\n  (uint32_t)sizeof(os_idle_thread_stack),\n  osPriorityIdle,\n#if defined(OS_IDLE_THREAD_TZ_MOD_ID)\n  (uint32_t)OS_IDLE_THREAD_TZ_MOD_ID,\n#else\n  0U,\n#endif\n  0U\n};\n\n\n// Timer Configuration\n// ===================\n\n#if (OS_TIMER_OBJ_MEM != 0)\n\n#if (OS_TIMER_NUM == 0)\n#error \"Invalid number of Timer objects!\"\n#endif\n\n// Timer Control Blocks\nstatic osRtxTimer_t os_timer_cb[OS_TIMER_NUM] \\\n__attribute__((section(\".bss.os.timer.cb\")));\n\n// Memory Pool for Timer Control Blocks\nstatic osRtxMpInfo_t os_mpi_timer \\\n__attribute__((section(\".data.os.timer.mpi\"))) =\n{ (uint32_t)OS_TIMER_NUM, 0U, (uint32_t)osRtxTimerCbSize, &os_timer_cb[0], NULL, NULL };\n\n#endif  // (OS_TIMER_OBJ_MEM != 0)\n\n\n#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0))\n\n#if (((OS_TIMER_THREAD_STACK_SIZE % 8) != 0) || (OS_TIMER_THREAD_STACK_SIZE < 96))\n#error \"Invalid Timer Thread Stack size!\"\n#endif\n\n// Timer Thread Control Block\nstatic osRtxThread_t os_timer_thread_cb \\\n__attribute__((section(\".bss.os.thread.cb\")));\n\n// Timer Thread Stack\nstatic uint64_t os_timer_thread_stack[OS_TIMER_THREAD_STACK_SIZE/8] \\\n__attribute__((section(\".bss.os.thread.timer.stack\")));\n\n// Timer Thread Attributes\nstatic const osThreadAttr_t os_timer_thread_attr = {\n  //lint -e{835} -e{845} \"Zero argument to operator\"\n#if defined(OS_TIMER_THREAD_NAME)\n  OS_TIMER_THREAD_NAME,\n#else\n  NULL,\n#endif\n#ifdef RTX_SAFETY_CLASS\n  osSafetyClass((uint32_t)OS_TIMER_THREAD_CLASS) |\n#endif\n#ifdef RTX_EXECUTION_ZONE\n  osThreadZone((uint32_t)OS_TIMER_THREAD_ZONE)   |\n#endif\n  osThreadDetached,\n  &os_timer_thread_cb,\n  (uint32_t)sizeof(os_timer_thread_cb),\n  &os_timer_thread_stack[0],\n  (uint32_t)sizeof(os_timer_thread_stack),\n  //lint -e{9030} -e{9034} \"cast from signed to enum\"\n  (osPriority_t)OS_TIMER_THREAD_PRIO,\n#if defined(OS_TIMER_THREAD_TZ_MOD_ID)\n  (uint32_t)OS_TIMER_THREAD_TZ_MOD_ID,\n#else\n  0U,\n#endif\n  0U\n};\n\n// Timer Message Queue Control Block\nstatic osRtxMessageQueue_t os_timer_mq_cb \\\n__attribute__((section(\".bss.os.msgqueue.cb\")));\n\n// Timer Message Queue Data\nstatic uint32_t os_timer_mq_data[osRtxMessageQueueMemSize(OS_TIMER_CB_QUEUE,8)/4] \\\n__attribute__((section(\".bss.os.msgqueue.mem\")));\n\n// Timer Message Queue Attributes\nstatic const osMessageQueueAttr_t os_timer_mq_attr = {\n  //lint -e{835} -e{845} \"Zero argument to operator\"\n  NULL,\n#ifdef RTX_SAFETY_CLASS\n  osSafetyClass((uint32_t)OS_TIMER_THREAD_CLASS) |\n#endif\n  0U,\n  &os_timer_mq_cb,\n  (uint32_t)sizeof(os_timer_mq_cb),\n  &os_timer_mq_data[0],\n  (uint32_t)sizeof(os_timer_mq_data)\n};\n\nextern int32_t osRtxTimerSetup  (void);\nextern void    osRtxTimerThread (void *argument);\n\n#endif  // ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0))\n\n\n// Event Flags Configuration\n// =========================\n\n#if (OS_EVFLAGS_OBJ_MEM != 0)\n\n#if (OS_EVFLAGS_NUM == 0)\n#error \"Invalid number of Event Flags objects!\"\n#endif\n\n// Event Flags Control Blocks\nstatic osRtxEventFlags_t os_ef_cb[OS_EVFLAGS_NUM] \\\n__attribute__((section(\".bss.os.evflags.cb\")));\n\n// Memory Pool for Event Flags Control Blocks\nstatic osRtxMpInfo_t os_mpi_ef \\\n__attribute__((section(\".data.os.evflags.mpi\"))) =\n{ (uint32_t)OS_EVFLAGS_NUM, 0U, (uint32_t)osRtxEventFlagsCbSize, &os_ef_cb[0], NULL, NULL };\n\n#endif  // (OS_EVFLAGS_OBJ_MEM != 0)\n\n\n// Mutex Configuration\n// ===================\n\n#if (OS_MUTEX_OBJ_MEM != 0)\n\n#if (OS_MUTEX_NUM == 0)\n#error \"Invalid number of Mutex objects!\"\n#endif\n\n// Mutex Control Blocks\nstatic osRtxMutex_t os_mutex_cb[OS_MUTEX_NUM] \\\n__attribute__((section(\".bss.os.mutex.cb\")));\n\n// Memory Pool for Mutex Control Blocks\nstatic osRtxMpInfo_t os_mpi_mutex \\\n__attribute__((section(\".data.os.mutex.mpi\"))) =\n{ (uint32_t)OS_MUTEX_NUM, 0U, (uint32_t)osRtxMutexCbSize, &os_mutex_cb[0], NULL, NULL };\n\n#endif  // (OS_MUTEX_OBJ_MEM != 0)\n\n\n// Semaphore Configuration\n// =======================\n\n#if (OS_SEMAPHORE_OBJ_MEM != 0)\n\n#if (OS_SEMAPHORE_NUM == 0)\n#error \"Invalid number of Semaphore objects!\"\n#endif\n\n// Semaphore Control Blocks\nstatic osRtxSemaphore_t os_semaphore_cb[OS_SEMAPHORE_NUM] \\\n__attribute__((section(\".bss.os.semaphore.cb\")));\n\n// Memory Pool for Semaphore Control Blocks\nstatic osRtxMpInfo_t os_mpi_semaphore \\\n__attribute__((section(\".data.os.semaphore.mpi\"))) =\n{ (uint32_t)OS_SEMAPHORE_NUM, 0U, (uint32_t)osRtxSemaphoreCbSize, &os_semaphore_cb[0], NULL, NULL };\n\n#endif  // (OS_SEMAPHORE_OBJ_MEM != 0)\n\n\n// Memory Pool Configuration\n// =========================\n\n#if (OS_MEMPOOL_OBJ_MEM != 0)\n\n#if (OS_MEMPOOL_NUM == 0)\n#error \"Invalid number of Memory Pool objects!\"\n#endif\n\n// Memory Pool Control Blocks\nstatic osRtxMemoryPool_t os_mp_cb[OS_MEMPOOL_NUM] \\\n__attribute__((section(\".bss.os.mempool.cb\")));\n\n// Memory Pool for Memory Pool Control Blocks\nstatic osRtxMpInfo_t os_mpi_mp \\\n__attribute__((section(\".data.os.mempool.mpi\"))) =\n{ (uint32_t)OS_MEMPOOL_NUM, 0U, (uint32_t)osRtxMemoryPoolCbSize, &os_mp_cb[0], NULL, NULL };\n\n// Memory Pool for Memory Pool Data Storage\n#if (OS_MEMPOOL_DATA_SIZE != 0)\n#if ((OS_MEMPOOL_DATA_SIZE % 8) != 0)\n#error \"Invalid Data Memory size for Memory Pools!\"\n#endif\nstatic uint64_t os_mp_data[(16 + (8*OS_MEMPOOL_NUM) + OS_MEMPOOL_DATA_SIZE)/8] \\\n__attribute__((section(\".bss.os.mempool.mem\")));\n#endif\n\n#endif  // (OS_MEMPOOL_OBJ_MEM != 0)\n\n\n// Message Queue Configuration\n// ===========================\n\n#if (OS_MSGQUEUE_OBJ_MEM != 0)\n\n#if (OS_MSGQUEUE_NUM == 0)\n#error \"Invalid number of Message Queue objects!\"\n#endif\n\n// Message Queue Control Blocks\nstatic osRtxMessageQueue_t os_mq_cb[OS_MSGQUEUE_NUM] \\\n__attribute__((section(\".bss.os.msgqueue.cb\")));\n\n// Memory Pool for Message Queue Control Blocks\nstatic osRtxMpInfo_t os_mpi_mq \\\n__attribute__((section(\".data.os.msgqueue.mpi\"))) =\n{ (uint32_t)OS_MSGQUEUE_NUM, 0U, (uint32_t)osRtxMessageQueueCbSize, &os_mq_cb[0], NULL, NULL };\n\n// Memory Pool for Message Queue Data Storage\n#if (OS_MSGQUEUE_DATA_SIZE != 0)\n#if ((OS_MSGQUEUE_DATA_SIZE % 8) != 0)\n#error \"Invalid Data Memory size for Message Queues!\"\n#endif\nstatic uint64_t os_mq_data[(16 + ((8+12)*OS_MSGQUEUE_NUM) + OS_MSGQUEUE_DATA_SIZE + 7)/8] \\\n__attribute__((section(\".bss.os.msgqueue.mem\")));\n#endif\n\n#endif  // (OS_MSGQUEUE_OBJ_MEM != 0)\n\n\n// Event Recorder Configuration\n// ============================\n\n#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0))\n\n#ifdef RTE_Compiler_EventRecorder\n\n// Event Recorder Initialize\n__STATIC_INLINE void evr_initialize (void) {\n\n  (void)EventRecorderInitialize(OS_EVR_LEVEL, (uint32_t)OS_EVR_START);\n\n#if ((OS_EVR_MEMORY_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_MEMORY_LEVEL & 0x0FU,    EvtRtxMemoryNo,       EvtRtxMemoryNo);\n  (void)EventRecorderDisable(~OS_EVR_MEMORY_LEVEL & 0x0FU,    EvtRtxMemoryNo,       EvtRtxMemoryNo);\n#endif\n#if ((OS_EVR_KERNEL_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_KERNEL_LEVEL & 0x0FU,    EvtRtxKernelNo,       EvtRtxKernelNo);\n  (void)EventRecorderDisable(~OS_EVR_KERNEL_LEVEL & 0x0FU,    EvtRtxKernelNo,       EvtRtxKernelNo);\n#endif\n#if ((OS_EVR_THREAD_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_THREAD_LEVEL & 0x0FU,    EvtRtxThreadNo,       EvtRtxThreadNo);\n  (void)EventRecorderDisable(~OS_EVR_THREAD_LEVEL & 0x0FU,    EvtRtxThreadNo,       EvtRtxThreadNo);\n#endif\n#if ((OS_EVR_WAIT_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_WAIT_LEVEL & 0x0FU,      EvtRtxWaitNo,         EvtRtxWaitNo);\n  (void)EventRecorderDisable(~OS_EVR_WAIT_LEVEL & 0x0FU,      EvtRtxWaitNo,         EvtRtxWaitNo);\n#endif\n#if ((OS_EVR_THFLAGS_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_THFLAGS_LEVEL & 0x0FU,   EvtRtxThreadFlagsNo,  EvtRtxThreadFlagsNo);\n  (void)EventRecorderDisable(~OS_EVR_THFLAGS_LEVEL & 0x0FU,   EvtRtxThreadFlagsNo,  EvtRtxThreadFlagsNo);\n#endif\n#if ((OS_EVR_EVFLAGS_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_EVFLAGS_LEVEL & 0x0FU,   EvtRtxEventFlagsNo,   EvtRtxEventFlagsNo);\n  (void)EventRecorderDisable(~OS_EVR_EVFLAGS_LEVEL & 0x0FU,   EvtRtxEventFlagsNo,   EvtRtxEventFlagsNo);\n#endif\n#if ((OS_EVR_TIMER_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_TIMER_LEVEL & 0x0FU,     EvtRtxTimerNo,        EvtRtxTimerNo);\n  (void)EventRecorderDisable(~OS_EVR_TIMER_LEVEL & 0x0FU,     EvtRtxTimerNo,        EvtRtxTimerNo);\n#endif\n#if ((OS_EVR_MUTEX_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_MUTEX_LEVEL & 0x0FU,     EvtRtxMutexNo,        EvtRtxMutexNo);\n  (void)EventRecorderDisable(~OS_EVR_MUTEX_LEVEL & 0x0FU,     EvtRtxMutexNo,        EvtRtxMutexNo);\n#endif\n#if ((OS_EVR_SEMAPHORE_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_SEMAPHORE_LEVEL & 0x0FU, EvtRtxSemaphoreNo,    EvtRtxSemaphoreNo);\n  (void)EventRecorderDisable(~OS_EVR_SEMAPHORE_LEVEL & 0x0FU, EvtRtxSemaphoreNo,    EvtRtxSemaphoreNo);\n#endif\n#if ((OS_EVR_MEMPOOL_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_MEMPOOL_LEVEL & 0x0FU,   EvtRtxMemoryPoolNo,   EvtRtxMemoryPoolNo);\n  (void)EventRecorderDisable(~OS_EVR_MEMPOOL_LEVEL & 0x0FU,   EvtRtxMemoryPoolNo,   EvtRtxMemoryPoolNo);\n#endif\n#if ((OS_EVR_MSGQUEUE_LEVEL & 0x80U) != 0U)\n  (void)EventRecorderEnable(  OS_EVR_MSGQUEUE_LEVEL & 0x0FU,  EvtRtxMessageQueueNo, EvtRtxMessageQueueNo);\n  (void)EventRecorderDisable(~OS_EVR_MSGQUEUE_LEVEL & 0x0FU,  EvtRtxMessageQueueNo, EvtRtxMessageQueueNo);\n#endif\n}\n\n#else\n#warning \"Event Recorder cannot be initialized (Event Recorder component is not selected)!\"\n#define evr_initialize()\n#endif\n\n#endif  // (OS_EVR_INIT != 0)\n\n\n// OS Configuration\n// ================\n\n\nconst osRtxConfig_t osRtxConfig \\\n__USED \\\n__attribute__((section(\".rodata\"))) =\n{\n  //lint -e{835} \"Zero argument to operator\"\n  0U   // Flags\n#if (OS_PRIVILEGE_MODE != 0)\n  | osRtxConfigPrivilegedMode\n#endif\n#if (OS_STACK_CHECK != 0)\n  | osRtxConfigStackCheck\n#endif\n#if (OS_STACK_WATERMARK != 0)\n  | osRtxConfigStackWatermark\n#endif\n#ifdef RTX_SAFETY_FEATURES\n  | osRtxConfigSafetyFeatures\n #ifdef RTX_SAFETY_CLASS\n  | osRtxConfigSafetyClass\n #endif\n #ifdef RTX_EXECUTION_ZONE\n  | osRtxConfigExecutionZone\n #endif\n #ifdef RTX_THREAD_WATCHDOG\n  | osRtxConfigThreadWatchdog\n #endif\n #ifdef RTX_OBJ_PTR_CHECK\n  | osRtxConfigObjPtrCheck\n #endif\n #ifdef RTX_SVC_PTR_CHECK\n  | osRtxConfigSVCPtrCheck\n #endif\n#endif\n  ,\n  (uint32_t)OS_TICK_FREQ,\n#if (OS_ROBIN_ENABLE != 0)\n  (uint32_t)OS_ROBIN_TIMEOUT,\n#else\n  0U,\n#endif\n  { &os_isr_queue[0], (uint16_t)(sizeof(os_isr_queue)/sizeof(void *)), 0U },\n  { \n    // Memory Pools (Variable Block Size)\n#if ((OS_THREAD_OBJ_MEM != 0) && (OS_THREAD_USER_STACK_SIZE != 0))\n    &os_thread_stack[0], sizeof(os_thread_stack),\n#else\n    NULL, 0U,\n#endif\n#if ((OS_MEMPOOL_OBJ_MEM != 0) && (OS_MEMPOOL_DATA_SIZE != 0))\n    &os_mp_data[0], sizeof(os_mp_data),\n#else\n    NULL, 0U,\n#endif\n#if ((OS_MSGQUEUE_OBJ_MEM != 0) && (OS_MSGQUEUE_DATA_SIZE != 0))\n    &os_mq_data[0], sizeof(os_mq_data),\n#else\n    NULL, 0U,\n#endif\n#if (OS_DYNAMIC_MEM_SIZE != 0)\n    &os_mem[0], (uint32_t)OS_DYNAMIC_MEM_SIZE,\n#else\n    NULL, 0U\n#endif\n  },\n  {\n    // Memory Pools (Fixed Block Size)\n#if (OS_THREAD_OBJ_MEM != 0)\n#if (OS_THREAD_DEF_STACK_NUM != 0)\n    &os_mpi_def_stack,\n#else\n    NULL,\n#endif\n    &os_mpi_thread,\n#else\n    NULL, \n    NULL,\n#endif\n#if (OS_TIMER_OBJ_MEM != 0)\n    &os_mpi_timer,\n#else\n    NULL,\n#endif\n#if (OS_EVFLAGS_OBJ_MEM != 0)\n    &os_mpi_ef,\n#else\n    NULL,\n#endif\n#if (OS_MUTEX_OBJ_MEM != 0)\n    &os_mpi_mutex,\n#else\n    NULL,\n#endif\n#if (OS_SEMAPHORE_OBJ_MEM != 0)\n    &os_mpi_semaphore,\n#else\n    NULL,\n#endif\n#if (OS_MEMPOOL_OBJ_MEM != 0)\n    &os_mpi_mp,\n#else\n    NULL,\n#endif\n#if (OS_MSGQUEUE_OBJ_MEM != 0)\n    &os_mpi_mq,\n#else\n    NULL,\n#endif\n  },\n  (uint32_t)OS_STACK_SIZE,\n  &os_idle_thread_attr,\n#if ((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0))\n  &os_timer_thread_attr,\n  osRtxTimerThread,\n  osRtxTimerSetup,\n  &os_timer_mq_attr,\n  (uint32_t)OS_TIMER_CB_QUEUE\n#else\n  NULL,\n  NULL,\n  NULL,\n  NULL,\n  0U\n#endif\n};\n\n\n// Non weak reference to library irq module\n//lint -esym(526,irqRtxLib)    \"Defined by Exception handlers\"\n//lint -esym(714,irqRtxLibRef) \"Non weak reference\"\n//lint -esym(765,irqRtxLibRef) \"Global scope\"\nextern const uint8_t         irqRtxLib;\nextern const uint8_t * const irqRtxLibRef;\n       const uint8_t * const irqRtxLibRef = &irqRtxLib;\n\n// Default User SVC Table\n//lint -esym(714,osRtxUserSVC) \"Referenced by Exception handlers\"\n//lint -esym(765,osRtxUserSVC) \"Global scope\"\n//lint -e{9067} \"extern array declared without size\"\nextern void * const osRtxUserSVC[];\n__WEAK void * const osRtxUserSVC[1] = { (void *)0 };\n\n#if (defined(RTX_SAFETY_CLASS) && defined(RTX_OBJ_PTR_CHECK) && \\\n    !((OS_TIMER_THREAD_STACK_SIZE != 0) && (OS_TIMER_CB_QUEUE != 0)))\nextern void osRtxTimerDeleteClass(uint32_t safety_class, uint32_t mode);\n// Default Timer Delete Class Function.\n__WEAK void osRtxTimerDeleteClass(uint32_t safety_class, uint32_t mode) {\n  (void)safety_class;\n  (void)mode;\n}\n#endif\n\n#ifdef RTX_THREAD_WATCHDOG\n// Default Watchdog Alarm Handler.\n__WEAK uint32_t osWatchdogAlarm_Handler (osThreadId_t thread_id) {\n  (void)thread_id;\n  return 0U;\n}\n#endif\n\n#ifdef RTX_EXECUTION_ZONE\n// Default Zone Setup Function.\n__WEAK void osZoneSetup_Callback (uint32_t zone) {\n  (void)zone;\n}\n#endif\n\n\n// OS Sections\n// ===========\n\n#if  defined(__CC_ARM) || \\\n    (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n// Initialized through linker\n//lint -esym(728,  __os_thread_cb_start__,    __os_thread_cb_end__)\n//lint -esym(728,  __os_timer_cb_start__,     __os_timer_cb_end__)\n//lint -esym(728,  __os_evflags_cb_start__,   __os_evflags_cb_end__)\n//lint -esym(728,  __os_mutex_cb_start__,     __os_mutex_cb_end__)\n//lint -esym(728,  __os_semaphore_cb_start__, __os_semaphore_cb_end__)\n//lint -esym(728,  __os_mempool_cb_start__,   __os_mempool_cb_end__)\n//lint -esym(728,  __os_msgqueue_cb_start__,  __os_msgqueue_cb_end__)\nstatic const uint32_t __os_thread_cb_start__    __attribute__((weakref(\".bss.os.thread.cb$$Base\")));\nstatic const uint32_t __os_thread_cb_end__      __attribute__((weakref(\".bss.os.thread.cb$$Limit\")));\nstatic const uint32_t __os_timer_cb_start__     __attribute__((weakref(\".bss.os.timer.cb$$Base\")));\nstatic const uint32_t __os_timer_cb_end__       __attribute__((weakref(\".bss.os.timer.cb$$Limit\")));\nstatic const uint32_t __os_evflags_cb_start__   __attribute__((weakref(\".bss.os.evflags.cb$$Base\")));\nstatic const uint32_t __os_evflags_cb_end__     __attribute__((weakref(\".bss.os.evflags.cb$$Limit\")));\nstatic const uint32_t __os_mutex_cb_start__     __attribute__((weakref(\".bss.os.mutex.cb$$Base\")));\nstatic const uint32_t __os_mutex_cb_end__       __attribute__((weakref(\".bss.os.mutex.cb$$Limit\")));\nstatic const uint32_t __os_semaphore_cb_start__ __attribute__((weakref(\".bss.os.semaphore.cb$$Base\")));\nstatic const uint32_t __os_semaphore_cb_end__   __attribute__((weakref(\".bss.os.semaphore.cb$$Limit\")));\nstatic const uint32_t __os_mempool_cb_start__   __attribute__((weakref(\".bss.os.mempool.cb$$Base\")));\nstatic const uint32_t __os_mempool_cb_end__     __attribute__((weakref(\".bss.os.mempool.cb$$Limit\")));\nstatic const uint32_t __os_msgqueue_cb_start__  __attribute__((weakref(\".bss.os.msgqueue.cb$$Base\")));\nstatic const uint32_t __os_msgqueue_cb_end__    __attribute__((weakref(\".bss.os.msgqueue.cb$$Limit\")));\n#else\nextern const uint32_t __os_thread_cb_start__    __attribute__((weak));\nextern const uint32_t __os_thread_cb_end__      __attribute__((weak));\nextern const uint32_t __os_timer_cb_start__     __attribute__((weak));\nextern const uint32_t __os_timer_cb_end__       __attribute__((weak));\nextern const uint32_t __os_evflags_cb_start__   __attribute__((weak));\nextern const uint32_t __os_evflags_cb_end__     __attribute__((weak));\nextern const uint32_t __os_mutex_cb_start__     __attribute__((weak));\nextern const uint32_t __os_mutex_cb_end__       __attribute__((weak));\nextern const uint32_t __os_semaphore_cb_start__ __attribute__((weak));\nextern const uint32_t __os_semaphore_cb_end__   __attribute__((weak));\nextern const uint32_t __os_mempool_cb_start__   __attribute__((weak));\nextern const uint32_t __os_mempool_cb_end__     __attribute__((weak));\nextern const uint32_t __os_msgqueue_cb_start__  __attribute__((weak));\nextern const uint32_t __os_msgqueue_cb_end__    __attribute__((weak));\n#endif\n\n//lint -e{9067} \"extern array declared without size\"\nextern const uint32_t * const os_cb_sections[];\n\n//lint -esym(714,os_cb_sections) \"Referenced by debugger\"\n//lint -esym(765,os_cb_sections) \"Global scope\"\nconst uint32_t * const os_cb_sections[] \\\n__USED \\\n__attribute__((section(\".rodata\"))) =\n{\n  &__os_thread_cb_start__,\n  &__os_thread_cb_end__,\n  &__os_timer_cb_start__,\n  &__os_timer_cb_end__,\n  &__os_evflags_cb_start__,\n  &__os_evflags_cb_end__,\n  &__os_mutex_cb_start__,\n  &__os_mutex_cb_end__,\n  &__os_semaphore_cb_start__,\n  &__os_semaphore_cb_end__,\n  &__os_mempool_cb_start__,\n  &__os_mempool_cb_end__,\n  &__os_msgqueue_cb_start__,\n  &__os_msgqueue_cb_end__\n};\n\n\n// OS Initialization\n// =================\n\n#if  defined(__CC_ARM) || \\\n    (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n\n#ifndef __MICROLIB\n//lint -esym(714,_platform_post_stackheap_init) \"Referenced by C library\"\n//lint -esym(765,_platform_post_stackheap_init) \"Global scope\"\nextern void _platform_post_stackheap_init (void);\n__WEAK void _platform_post_stackheap_init (void) {\n  (void)osKernelInitialize();\n}\n#endif\n\n#elif defined(__GNUC__)\n\nextern void software_init_hook (void);\n__WEAK void software_init_hook (void) {\n  (void)osKernelInitialize();\n}\n\n#elif defined(__ICCARM__)\n\nextern void $Super$$__iar_data_init3 (void);\nvoid $Sub$$__iar_data_init3 (void) {\n  $Super$$__iar_data_init3();\n  (void)osKernelInitialize();\n}\n\n#endif\n\n\n// OS Hooks\n// ========\n\n// RTOS Kernel Pre-Initialization Hook\n#if (defined(OS_EVR_INIT) && (OS_EVR_INIT != 0))\nvoid osRtxKernelBeforeInit (void);\nvoid osRtxKernelBeforeInit (void) {\n  if (osKernelGetState() == osKernelInactive) {\n    evr_initialize();\n  }\n}\n#endif\n\n\n// C/C++ Standard Library Floating-point Initialization\n// ====================================================\n\n#if ( !defined(RTX_NO_FP_INIT_CLIB) && \\\n     ( defined(__CC_ARM) || \\\n      (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \\\n      !defined(__MICROLIB))\n\n#if  (!defined(__ARM_ARCH_7A__) && \\\n      (defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n      (defined(__FPU_USED   ) && (__FPU_USED    == 1U)))\n\nextern void $Super$$_fp_init (void);\n\nvoid $Sub$$_fp_init (void);\nvoid $Sub$$_fp_init (void) {\n  $Super$$_fp_init();\n  FPU->FPDSCR = __get_FPSCR();\n}\n\n#endif\n\n#endif\n\n\n// C/C++ Standard Library Multithreading Interface\n// ===============================================\n\n#if ( !defined(RTX_NO_MULTITHREAD_CLIB) && \\\n     ( defined(__CC_ARM) || \\\n      (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \\\n      !defined(__MICROLIB))\n\n#define LIBSPACE_SIZE 96\n\n//lint -esym(714,__user_perthread_libspace,_mutex_*) \"Referenced by C library\"\n//lint -esym(765,__user_perthread_libspace,_mutex_*) \"Global scope\"\n//lint -esym(9003, os_libspace*) \"variables 'os_libspace*' defined at module scope\"\n\n// Memory for libspace\nstatic uint32_t os_libspace[OS_THREAD_LIBSPACE_NUM+1][LIBSPACE_SIZE/4] \\\n__attribute__((section(\".bss.os.libspace\")));\n\n// Thread IDs for libspace\nstatic osThreadId_t os_libspace_id[OS_THREAD_LIBSPACE_NUM] \\\n__attribute__((section(\".bss.os.libspace\")));\n\n// Check if Kernel has been started\nstatic uint32_t os_kernel_is_active (void) {\n  static uint8_t os_kernel_active = 0U;\n\n  if (os_kernel_active == 0U) {\n    if (osKernelGetState() > osKernelReady) {\n      os_kernel_active = 1U;\n    }\n  }\n  return (uint32_t)os_kernel_active;\n}\n\n// Provide libspace for current thread\nvoid *__user_perthread_libspace (void);\nvoid *__user_perthread_libspace (void) {\n  osThreadId_t id;\n  uint32_t     n;\n\n  if (os_kernel_is_active() != 0U) {\n    id = osThreadGetId();\n    for (n = 0U; n < (uint32_t)OS_THREAD_LIBSPACE_NUM; n++) {\n      if (os_libspace_id[n] == NULL) {\n        os_libspace_id[n] = id;\n      }\n      if (os_libspace_id[n] == id) {\n        break;\n      }\n    }\n    if (n == (uint32_t)OS_THREAD_LIBSPACE_NUM) {\n      (void)osRtxKernelErrorNotify(osRtxErrorClibSpace, id);\n    }\n  } else {\n    n = OS_THREAD_LIBSPACE_NUM;\n  }\n\n  //lint -e{9087} \"cast between pointers to different object types\"\n  return (void *)&os_libspace[n][0];\n}\n\n// Free libspace for specified thread\nstatic void user_perthread_libspace_free (osThreadId_t id) {\n  uint32_t n;\n\n  for (n = 0U; n < (uint32_t)OS_THREAD_LIBSPACE_NUM; n++) {\n    if (os_libspace_id[n] == id) {\n      os_libspace_id[n] = NULL;\n      break;\n    }\n  }\n}\n\n/// RTOS Thread Before Free Hook\nvoid osRtxThreadBeforeFree (osThreadId_t id);\nvoid osRtxThreadBeforeFree (osThreadId_t id) {\n  user_perthread_libspace_free(id);\n}\n\n// Mutex identifier\ntypedef void *mutex;\n\n//lint -save \"Function prototypes defined in C library\"\n//lint -e970 \"Use of 'int' outside of a typedef\"\n//lint -e818 \"Pointer 'm' could be declared as pointing to const\"\n\n// Initialize mutex\n__USED\nint _mutex_initialize(mutex *m);\nint _mutex_initialize(mutex *m) {\n  int result;\n\n  *m = osMutexNew(NULL);\n  if (*m != NULL) {\n    result = 1;\n  } else {\n    result = 0;\n    (void)osRtxKernelErrorNotify(osRtxErrorClibMutex, m);\n  }\n  return result;\n}\n\n// Acquire mutex\n__USED\nvoid _mutex_acquire(mutex *m);\nvoid _mutex_acquire(mutex *m) {\n  if (os_kernel_is_active() != 0U) {\n    (void)osMutexAcquire(*m, osWaitForever);\n  }\n}\n\n// Release mutex\n__USED\nvoid _mutex_release(mutex *m);\nvoid _mutex_release(mutex *m) {\n  if (os_kernel_is_active() != 0U) {\n    (void)osMutexRelease(*m);\n  }\n}\n\n// Free mutex\n__USED\nvoid _mutex_free(mutex *m);\nvoid _mutex_free(mutex *m) {\n  (void)osMutexDelete(*m);\n}\n\n//lint -restore\n\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_lib.h",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       RTX Library definitions\n *\n * -----------------------------------------------------------------------------\n */\n\n#ifndef RTX_LIB_H_\n#define RTX_LIB_H_\n\n#include <string.h>\n#include \"rtx_def.h\"                    // RTX Configuration definitions\n#include \"rtx_core_c.h\"                 // Cortex core definitions\n#ifdef RTX_TZ_CONTEXT\n#include \"tz_context.h\"                 // TrustZone Context API\n#endif\n#include \"os_tick.h\"                    // CMSIS OS Tick API\n#include \"cmsis_os2.h\"                  // CMSIS RTOS API\n#include \"rtx_os.h\"                     // RTX OS definitions\n#include \"rtx_evr.h\"                    // RTX Event Recorder definitions\n\n\n//  ==== Library defines ====\n\n#define os_thread_t         osRtxThread_t\n#define os_timer_t          osRtxTimer_t\n#define os_timer_finfo_t    osRtxTimerFinfo_t\n#define os_event_flags_t    osRtxEventFlags_t\n#define os_mutex_t          osRtxMutex_t\n#define os_semaphore_t      osRtxSemaphore_t\n#define os_mp_info_t        osRtxMpInfo_t\n#define os_memory_pool_t    osRtxMemoryPool_t\n#define os_message_t        osRtxMessage_t\n#define os_message_queue_t  osRtxMessageQueue_t\n#define os_object_t         osRtxObject_t\n\n\n//  ==== Library sections ====\n\n#if  defined(__CC_ARM) || \\\n    (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n// Referenced through linker\n//lint -esym(528,  __os_thread_cb_start__,    __os_thread_cb_length__)\n//lint -esym(528,  __os_timer_cb_start__,     __os_timer_cb_length__)\n//lint -esym(528,  __os_evflags_cb_start__,   __os_evflags_cb_length__)\n//lint -esym(528,  __os_mutex_cb_start__,     __os_mutex_cb_length__)\n//lint -esym(528,  __os_semaphore_cb_start__, __os_semaphore_cb_length__)\n//lint -esym(528,  __os_mempool_cb_start__,   __os_mempool_cb_length__)\n//lint -esym(528,  __os_msgqueue_cb_start__,  __os_msgqueue_cb_length__)\n// Accessed through linker\n//lint -esym(551,  __os_thread_cb_start__,    __os_thread_cb_length__)\n//lint -esym(551,  __os_timer_cb_start__,     __os_timer_cb_length__)\n//lint -esym(551,  __os_evflags_cb_start__,   __os_evflags_cb_length__)\n//lint -esym(551,  __os_mutex_cb_start__,     __os_mutex_cb_length__)\n//lint -esym(551,  __os_semaphore_cb_start__, __os_semaphore_cb_length__)\n//lint -esym(551,  __os_mempool_cb_start__,   __os_mempool_cb_length__)\n//lint -esym(551,  __os_msgqueue_cb_start__,  __os_msgqueue_cb_length__)\n// Initialized through linker\n//lint -esym(728,  __os_thread_cb_start__,    __os_thread_cb_length__)\n//lint -esym(728,  __os_timer_cb_start__,     __os_timer_cb_length__)\n//lint -esym(728,  __os_evflags_cb_start__,   __os_evflags_cb_length__)\n//lint -esym(728,  __os_mutex_cb_start__,     __os_mutex_cb_length__)\n//lint -esym(728,  __os_semaphore_cb_start__, __os_semaphore_cb_length__)\n//lint -esym(728,  __os_mempool_cb_start__,   __os_mempool_cb_length__)\n//lint -esym(728,  __os_msgqueue_cb_start__,  __os_msgqueue_cb_length__)\n// Global scope\n//lint -esym(9003, __os_thread_cb_start__,    __os_thread_cb_length__)\n//lint -esym(9003, __os_timer_cb_start__,     __os_timer_cb_length__)\n//lint -esym(9003, __os_evflags_cb_start__,   __os_evflags_cb_length__)\n//lint -esym(9003, __os_mutex_cb_start__,     __os_mutex_cb_length__)\n//lint -esym(9003, __os_semaphore_cb_start__, __os_semaphore_cb_length__)\n//lint -esym(9003, __os_mempool_cb_start__,   __os_mempool_cb_length__)\n//lint -esym(9003, __os_msgqueue_cb_start__,  __os_msgqueue_cb_length__)\nstatic const uint32_t __os_thread_cb_start__     __attribute__((weakref(\".bss.os.thread.cb$$Base\")));\nstatic const uint32_t __os_thread_cb_length__    __attribute__((weakref(\".bss.os.thread.cb$$Length\")));\nstatic const uint32_t __os_timer_cb_start__      __attribute__((weakref(\".bss.os.timer.cb$$Base\")));\nstatic const uint32_t __os_timer_cb_length__     __attribute__((weakref(\".bss.os.timer.cb$$Length\")));\nstatic const uint32_t __os_evflags_cb_start__    __attribute__((weakref(\".bss.os.evflags.cb$$Base\")));\nstatic const uint32_t __os_evflags_cb_length__   __attribute__((weakref(\".bss.os.evflags.cb$$Length\")));\nstatic const uint32_t __os_mutex_cb_start__      __attribute__((weakref(\".bss.os.mutex.cb$$Base\")));\nstatic const uint32_t __os_mutex_cb_length__     __attribute__((weakref(\".bss.os.mutex.cb$$Length\")));\nstatic const uint32_t __os_semaphore_cb_start__  __attribute__((weakref(\".bss.os.semaphore.cb$$Base\")));\nstatic const uint32_t __os_semaphore_cb_length__ __attribute__((weakref(\".bss.os.semaphore.cb$$Length\")));\nstatic const uint32_t __os_mempool_cb_start__    __attribute__((weakref(\".bss.os.mempool.cb$$Base\")));\nstatic const uint32_t __os_mempool_cb_length__   __attribute__((weakref(\".bss.os.mempool.cb$$Length\")));\nstatic const uint32_t __os_msgqueue_cb_start__   __attribute__((weakref(\".bss.os.msgqueue.cb$$Base\")));\nstatic const uint32_t __os_msgqueue_cb_length__  __attribute__((weakref(\".bss.os.msgqueue.cb$$Length\")));\n#else\nextern const uint32_t __os_thread_cb_start__     __attribute__((weak));\nextern const uint32_t __os_thread_cb_length__    __attribute__((weak));\nextern const uint32_t __os_timer_cb_start__      __attribute__((weak));\nextern const uint32_t __os_timer_cb_length__     __attribute__((weak));\nextern const uint32_t __os_evflags_cb_start__    __attribute__((weak));\nextern const uint32_t __os_evflags_cb_length__   __attribute__((weak));\nextern const uint32_t __os_mutex_cb_start__      __attribute__((weak));\nextern const uint32_t __os_mutex_cb_length__     __attribute__((weak));\nextern const uint32_t __os_semaphore_cb_start__  __attribute__((weak));\nextern const uint32_t __os_semaphore_cb_length__ __attribute__((weak));\nextern const uint32_t __os_mempool_cb_start__    __attribute__((weak));\nextern const uint32_t __os_mempool_cb_length__   __attribute__((weak));\nextern const uint32_t __os_msgqueue_cb_start__   __attribute__((weak));\nextern const uint32_t __os_msgqueue_cb_length__  __attribute__((weak));\n#endif\n\n\n//  ==== Inline functions ====\n\n// Thread ID\n__STATIC_INLINE os_thread_t *osRtxThreadId (osThreadId_t thread_id) {\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 2]\n  return ((os_thread_t *)thread_id);\n}\n// Timer ID\n__STATIC_INLINE os_timer_t *osRtxTimerId (osTimerId_t timer_id) {\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 2]\n  return ((os_timer_t *)timer_id);\n}\n// Event Flags ID\n__STATIC_INLINE os_event_flags_t *osRtxEventFlagsId (osEventFlagsId_t ef_id) {\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 2]\n  return ((os_event_flags_t *)ef_id);\n}\n// Mutex ID\n__STATIC_INLINE os_mutex_t *osRtxMutexId (osMutexId_t mutex_id) {\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 2]\n  return ((os_mutex_t *)mutex_id);\n}\n// Semaphore ID\n__STATIC_INLINE os_semaphore_t *osRtxSemaphoreId (osSemaphoreId_t semaphore_id) {\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 2]\n  return ((os_semaphore_t *)semaphore_id);\n}\n// Memory Pool ID\n__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolId (osMemoryPoolId_t mp_id) {\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 2]\n  return ((os_memory_pool_t *)mp_id);\n}\n// Message Queue ID\n__STATIC_INLINE os_message_queue_t *osRtxMessageQueueId (osMessageQueueId_t mq_id) {\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 2]\n  return ((os_message_queue_t *)mq_id);\n}\n\n// Generic Object\n__STATIC_INLINE os_object_t *osRtxObject (void *object) {\n  //lint -e{9079} -e{9087} \"cast from pointer to void to pointer to object type\" [MISRA Note 3]\n  return ((os_object_t *)object);\n}\n\n// Thread Object\n__STATIC_INLINE os_thread_t *osRtxThreadObject (os_object_t *object) {\n  //lint -e{740} -e{826} -e{9087} \"cast from pointer to generic object to specific object\" [MISRA Note 4]\n  return ((os_thread_t *)object);\n}\n// Timer Object\n__STATIC_INLINE os_timer_t *osRtxTimerObject (os_object_t *object) {\n  //lint -e{740} -e{826} -e{9087} \"cast from pointer to generic object to specific object\" [MISRA Note 4]\n  return ((os_timer_t *)object);\n}\n// Event Flags Object\n__STATIC_INLINE os_event_flags_t *osRtxEventFlagsObject (os_object_t *object) {\n  //lint -e{740} -e{826} -e{9087} \"cast from pointer to generic object to specific object\" [MISRA Note 4]\n  return ((os_event_flags_t *)object);\n}\n// Mutex Object\n__STATIC_INLINE os_mutex_t *osRtxMutexObject (os_object_t *object) {\n  //lint -e{740} -e{826} -e{9087} \"cast from pointer to generic object to specific object\" [MISRA Note 4]\n  return ((os_mutex_t *)object);\n}\n// Semaphore Object\n__STATIC_INLINE os_semaphore_t *osRtxSemaphoreObject (os_object_t *object) {\n  //lint -e{740} -e{826} -e{9087} \"cast from pointer to generic object to specific object\" [MISRA Note 4]\n  return ((os_semaphore_t *)object);\n}\n// Memory Pool Object\n__STATIC_INLINE os_memory_pool_t *osRtxMemoryPoolObject (os_object_t *object) {\n  //lint -e{740} -e{826} -e{9087} \"cast from pointer to generic object to specific object\" [MISRA Note 4]\n  return ((os_memory_pool_t *)object);\n}\n// Message Queue Object\n__STATIC_INLINE os_message_queue_t *osRtxMessageQueueObject (os_object_t *object) {\n  //lint -e{740} -e{826} -e{9087} \"cast from pointer to generic object to specific object\" [MISRA Note 4]\n  return ((os_message_queue_t *)object);\n}\n// Message Object\n__STATIC_INLINE os_message_t *osRtxMessageObject (os_object_t *object) {\n  //lint -e{740} -e{826} -e{9087} \"cast from pointer to generic object to specific object\" [MISRA Note 4]\n  return ((os_message_t *)object);\n}\n\n// Kernel State\n__STATIC_INLINE osKernelState_t osRtxKernelState (void) {\n  //lint -e{9030} -e{9034} \"cast to enum\"\n  return ((osKernelState_t)(osRtxInfo.kernel.state));\n}\n\n// Thread State\n__STATIC_INLINE osThreadState_t osRtxThreadState (const os_thread_t *thread) {\n  uint8_t state = thread->state & osRtxThreadStateMask;\n  //lint -e{9030} -e{9034} \"cast to enum\"\n  return ((osThreadState_t)state);\n}\n\n// Thread Priority\n__STATIC_INLINE osPriority_t osRtxThreadPriority (const os_thread_t *thread) {\n  //lint -e{9030} -e{9034} \"cast to enum\"\n  return ((osPriority_t)thread->priority);\n}\n\n// Kernel Get State\n__STATIC_INLINE uint8_t osRtxKernelGetState (void) {\n  return osRtxInfo.kernel.state;\n}\n\n// Thread Get/Set Running\n__STATIC_INLINE os_thread_t *osRtxThreadGetRunning (void) {\n  return osRtxInfo.thread.run.curr;\n}\n__STATIC_INLINE void osRtxThreadSetRunning (os_thread_t *thread) {\n  osRtxInfo.thread.run.curr = thread;\n}\n\n\n//  ==== Library functions ====\n\n// Kernel Library functions\nextern void         osRtxKernelBeforeInit  (void);\n\n// Thread Library functions\nextern void         osRtxThreadListPut     (os_object_t *object, os_thread_t *thread);\nextern os_thread_t *osRtxThreadListGet     (os_object_t *object);\nextern void         osRtxThreadListSort    (os_thread_t *thread);\nextern void         osRtxThreadListRemove  (os_thread_t *thread);\nextern void         osRtxThreadReadyPut    (os_thread_t *thread);\n//lint -esym(759,osRtxThreadDelayRemove)    \"Prototype in header\"\n//lint -esym(765,osRtxThreadDelayRemove)    \"Global scope\"\nextern void         osRtxThreadDelayRemove (os_thread_t *thread);\nextern void         osRtxThreadDelayTick   (void);\nextern uint32_t    *osRtxThreadRegPtr      (const os_thread_t *thread);\nextern void         osRtxThreadSwitch      (os_thread_t *thread);\nextern void         osRtxThreadDispatch    (os_thread_t *thread);\nextern void         osRtxThreadWaitExit    (os_thread_t *thread, uint32_t ret_val, bool_t dispatch);\nextern bool_t       osRtxThreadWaitEnter   (uint8_t state, uint32_t timeout);\n#ifdef RTX_STACK_CHECK\nextern bool_t       osRtxThreadStackCheck  (const os_thread_t *thread);\n#endif\n#ifdef RTX_THREAD_WATCHDOG\n//lint -esym(759,osRtxThreadWatchdogRemove) \"Prototype in header\"\n//lint -esym(765,osRtxThreadWatchdogRemove) \"Global scope\"\nextern void         osRtxThreadWatchdogRemove(const os_thread_t *thread);\nextern void         osRtxThreadWatchdogTick  (void);\n#endif\n//lint -esym(759,osRtxThreadJoinWakeup)     \"Prototype in header\"\n//lint -esym(765,osRtxThreadJoinWakeup)     \"Global scope\"\nextern void         osRtxThreadJoinWakeup  (const os_thread_t *thread);\n//lint -esym(759,osRtxThreadDestroy)        \"Prototype in header\"\n//lint -esym(765,osRtxThreadDestroy)        \"Global scope\"\nextern void         osRtxThreadDestroy     (os_thread_t *thread);\nextern void         osRtxThreadBeforeFree  (os_thread_t *thread);\nextern bool_t       osRtxThreadStartup     (void);\n\n// Timer Library functions\nextern int32_t osRtxTimerSetup       (void);\nextern void    osRtxTimerThread      (void *argument);\n#ifdef RTX_SAFETY_CLASS\nextern void    osRtxTimerDeleteClass (uint32_t safety_class, uint32_t mode);\n#endif\n\n// Mutex Library functions\nextern void osRtxMutexOwnerRelease (os_mutex_t *mutex_list);\nextern void osRtxMutexOwnerRestore (const os_mutex_t *mutex, const os_thread_t *thread_wakeup);\n#ifdef RTX_SAFETY_CLASS\nextern void osRtxMutexDeleteClass  (uint32_t safety_class, uint32_t mode);\n#endif\n\n// Semaphore Library functions\n#ifdef RTX_SAFETY_CLASS\nextern void osRtxSemaphoreDeleteClass (uint32_t safety_class, uint32_t mode);\n#endif\n\n// Event Flags Library functions\n#ifdef RTX_SAFETY_CLASS\nextern void osRtxEventFlagsDeleteClass(uint32_t safety_class, uint32_t mode);\n#endif\n\n// Memory Heap Library functions\nextern uint32_t osRtxMemoryInit (void *mem, uint32_t size);\nextern void    *osRtxMemoryAlloc(void *mem, uint32_t size, uint32_t type);\nextern uint32_t osRtxMemoryFree (void *mem, void *block);\n\n// Memory Pool Library functions\nextern uint32_t   osRtxMemoryPoolInit       (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem);\nextern void      *osRtxMemoryPoolAlloc      (os_mp_info_t *mp_info);\nextern osStatus_t osRtxMemoryPoolFree       (os_mp_info_t *mp_info, void *block);\n#ifdef RTX_SAFETY_CLASS\nextern void       osRtxMemoryPoolDeleteClass(uint32_t safety_class, uint32_t mode);\n#endif\n\n// Message Queue Library functions\nextern int32_t osRtxMessageQueueTimerSetup (void);\n#ifdef RTX_SAFETY_CLASS\nextern void    osRtxMessageQueueDeleteClass(uint32_t safety_class, uint32_t mode);\n#endif\n\n// System Library functions\nextern void osRtxTick_Handler   (void);\nextern void osRtxPendSV_Handler (void);\nextern void osRtxPostProcess    (os_object_t *object);\n\n\n#endif  // RTX_LIB_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_memory.c",
    "content": "/*\n * Copyright (c) 2013-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Memory functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  Memory Pool Header structure\ntypedef struct {\n  uint32_t size;                // Memory Pool size\n  uint32_t used;                // Used Memory\n} mem_head_t;\n\n//  Memory Block Header structure\ntypedef struct mem_block_s {\n  struct mem_block_s *next;     // Next Memory Block in list\n  uint32_t            info;     // Block Info or max used Memory (in last block)\n} mem_block_t;\n\n//  Memory Block Info: Length = <31:2>:'00', Type = <1:0>\n#define MB_INFO_LEN_MASK        0xFFFFFFFCU     // Length mask\n#define MB_INFO_TYPE_MASK       0x00000003U     // Type mask\n\n//  Memory Head Pointer\n__STATIC_INLINE mem_head_t *MemHeadPtr (void *mem) {\n  //lint -e{9079} -e{9087} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n  return ((mem_head_t *)mem);\n}\n\n//  Memory Block Pointer\n__STATIC_INLINE mem_block_t *MemBlockPtr (void *mem, uint32_t offset) {\n  uint32_t     addr;\n  mem_block_t *ptr;\n\n  //lint --e{923} --e{9078} \"cast between pointer and unsigned int\" [MISRA Note 8]\n  addr = (uint32_t)mem + offset;\n  ptr  = (mem_block_t *)addr;\n\n  return ptr;\n}\n\n\n//  ==== Library functions ====\n\n/// Initialize Memory Pool with variable block size.\n/// \\param[in]  mem             pointer to memory pool.\n/// \\param[in]  size            size of a memory pool in bytes.\n/// \\return 1 - success, 0 - failure.\n__WEAK uint32_t osRtxMemoryInit (void *mem, uint32_t size) {\n  mem_head_t  *head;\n  mem_block_t *ptr;\n\n  // Check parameters\n  //lint -e{923} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  if ((mem == NULL) || (((uint32_t)mem & 7U) != 0U) || ((size & 7U) != 0U) ||\n      (size < (sizeof(mem_head_t) + (2U*sizeof(mem_block_t))))) {\n    EvrRtxMemoryInit(mem, size, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  // Initialize memory pool header\n  head = MemHeadPtr(mem);\n  head->size = size;\n  head->used = sizeof(mem_head_t) + sizeof(mem_block_t);\n\n  // Initialize first and last block header\n  ptr = MemBlockPtr(mem, sizeof(mem_head_t));\n  ptr->next = MemBlockPtr(mem, size - sizeof(mem_block_t));\n  ptr->next->next = NULL;\n  ptr->next->info = sizeof(mem_head_t) + sizeof(mem_block_t);\n  ptr->info = 0U;\n\n  EvrRtxMemoryInit(mem, size, 1U);\n\n  return 1U;\n}\n\n/// Allocate a memory block from a Memory Pool.\n/// \\param[in]  mem             pointer to memory pool.\n/// \\param[in]  size            size of a memory block in bytes.\n/// \\param[in]  type            memory block type: 0 - generic, 1 - control block\n/// \\return allocated memory block or NULL in case of no memory is available.\n__WEAK void *osRtxMemoryAlloc (void *mem, uint32_t size, uint32_t type) {\n  mem_block_t *ptr;\n  mem_block_t *p, *p_new;\n  uint32_t     block_size;\n  uint32_t     hole_size;\n\n  // Check parameters\n  if ((mem == NULL) || (size == 0U) || ((type & ~MB_INFO_TYPE_MASK) != 0U)) {\n    EvrRtxMemoryAlloc(mem, size, type, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  // Add block header to size\n  block_size = size + sizeof(mem_block_t);\n  // Make sure that block is 8-byte aligned\n  block_size = (block_size + 7U) & ~((uint32_t)7U);\n\n  // Search for hole big enough\n  p = MemBlockPtr(mem, sizeof(mem_head_t));\n  for (;;) {\n    //lint -e{923} -e{9078} \"cast from pointer to unsigned int\"\n    hole_size  = (uint32_t)p->next - (uint32_t)p;\n    hole_size -= p->info & MB_INFO_LEN_MASK;\n    if (hole_size >= block_size) {\n      // Hole found\n      break;\n    }\n    p = p->next;\n    if (p->next == NULL) {\n      // Failed (end of list)\n      EvrRtxMemoryAlloc(mem, size, type, NULL);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return NULL;\n    }\n  }\n\n  // Update used memory\n  (MemHeadPtr(mem))->used += block_size;\n\n  // Update max used memory\n  p_new = MemBlockPtr(mem, (MemHeadPtr(mem))->size - sizeof(mem_block_t));\n  if (p_new->info < (MemHeadPtr(mem))->used) {\n    p_new->info = (MemHeadPtr(mem))->used;\n  }\n\n  // Allocate block\n  if (p->info == 0U) {\n    // No block allocated, set info of first element\n    p->info = block_size | type;\n    ptr = MemBlockPtr(p, sizeof(mem_block_t));\n  } else {\n    // Insert new element into the list\n    p_new = MemBlockPtr(p, p->info & MB_INFO_LEN_MASK);\n    p_new->next = p->next;\n    p_new->info = block_size | type;\n    p->next = p_new;\n    ptr = MemBlockPtr(p_new, sizeof(mem_block_t));\n  }\n\n  EvrRtxMemoryAlloc(mem, size, type, ptr);\n\n  return ptr;\n}\n\n/// Return an allocated memory block back to a Memory Pool.\n/// \\param[in]  mem             pointer to memory pool.\n/// \\param[in]  block           memory block to be returned to the memory pool.\n/// \\return 1 - success, 0 - failure.\n__WEAK uint32_t osRtxMemoryFree (void *mem, void *block) {\n  const mem_block_t *ptr;\n        mem_block_t *p, *p_prev;\n\n  // Check parameters\n  if ((mem == NULL) || (block == NULL)) {\n    EvrRtxMemoryFree(mem, block, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  // Memory block header\n  ptr = MemBlockPtr(block, 0U);\n  ptr--;\n\n  // Search for block header\n  p_prev = NULL;\n  p = MemBlockPtr(mem, sizeof(mem_head_t));\n  while (p != ptr) {\n    p_prev = p;\n    p = p->next;\n    if (p == NULL) {\n      // Not found\n      EvrRtxMemoryFree(mem, block, 0U);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return 0U;\n    }\n  }\n\n  // Update used memory\n  (MemHeadPtr(mem))->used -= p->info & MB_INFO_LEN_MASK;\n\n  // Free block\n  if (p_prev == NULL) {\n    // Release first block, only set info to 0\n    p->info = 0U;\n  } else {\n    // Discard block from chained list\n    p_prev->next = p->next;\n  }\n\n  EvrRtxMemoryFree(mem, block, 1U);\n\n  return 1U;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_mempool.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Memory Pool functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  OS Runtime Object Memory Usage\n#ifdef RTX_OBJ_MEM_USAGE\nosRtxObjectMemUsage_t osRtxMemoryPoolMemUsage \\\n__attribute__((section(\".data.os.mempool.obj\"))) =\n{ 0U, 0U, 0U };\n#endif\n\n\n//  ==== Helper functions ====\n\n/// Verify that Memory Pool object pointer is valid.\n/// \\param[in]  mp              memory pool object.\n/// \\return true - valid, false - invalid.\nstatic bool_t IsMemoryPoolPtrValid (const os_memory_pool_t *mp) {\n#ifdef RTX_OBJ_PTR_CHECK\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  uint32_t cb_start  = (uint32_t)&__os_mempool_cb_start__;\n  uint32_t cb_length = (uint32_t)&__os_mempool_cb_length__;\n\n  // Check the section boundaries\n  if (((uint32_t)mp - cb_start) >= cb_length) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n  // Check the object alignment\n  if ((((uint32_t)mp - cb_start) % sizeof(os_memory_pool_t)) != 0U) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#else\n  // Check NULL pointer\n  if (mp == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#endif\n  return TRUE;\n}\n\n\n//  ==== Library functions ====\n\n/// Initialize Memory Pool.\n/// \\param[in]  mp_info         memory pool info.\n/// \\param[in]  block_count     maximum number of memory blocks in memory pool.\n/// \\param[in]  block_size      size of a memory block in bytes.\n/// \\param[in]  block_mem       pointer to memory for block storage.\n/// \\return 1 - success, 0 - failure.\nuint32_t osRtxMemoryPoolInit (os_mp_info_t *mp_info, uint32_t block_count, uint32_t block_size, void *block_mem) {\n  //lint --e{9079} --e{9087} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n  void *mem;\n  void *block;\n\n  // Check parameters\n  if ((mp_info == NULL) || (block_count == 0U) || (block_size  == 0U) || (block_mem  == NULL)) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  // Initialize information structure\n  mp_info->max_blocks  = block_count;\n  mp_info->used_blocks = 0U;\n  mp_info->block_size  = block_size;\n  mp_info->block_base  = block_mem;\n  mp_info->block_free  = block_mem;\n  mp_info->block_lim   = &(((uint8_t *)block_mem)[block_count * block_size]);\n\n  EvrRtxMemoryBlockInit(mp_info, block_count, block_size, block_mem);\n\n  // Link all free blocks\n  mem = block_mem;\n  while (--block_count != 0U) {\n    block = &((uint8_t *)mem)[block_size];\n    *((void **)mem) = block;\n    mem = block;\n  }\n  *((void **)mem) = NULL;\n\n  return 1U;\n}\n\n/// Allocate a memory block from a Memory Pool.\n/// \\param[in]  mp_info         memory pool info.\n/// \\return address of the allocated memory block or NULL in case of no memory is available.\nvoid *osRtxMemoryPoolAlloc (os_mp_info_t *mp_info) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask = __get_PRIMASK();\n#endif\n  void *block;\n\n  if (mp_info == NULL) {\n    EvrRtxMemoryBlockAlloc(NULL, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  block = mp_info->block_free;\n  if (block != NULL) {\n    //lint --e{9079} --e{9087} \"conversion from pointer to void to pointer to other type\"\n    mp_info->block_free = *((void **)block);\n    mp_info->used_blocks++;\n  }\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  block = atomic_link_get(&mp_info->block_free);\n  if (block != NULL) {\n    (void)atomic_inc32(&mp_info->used_blocks);\n  }\n#endif\n\n  EvrRtxMemoryBlockAlloc(mp_info, block);\n\n  return block;\n}\n\n/// Return an allocated memory block back to a Memory Pool.\n/// \\param[in]  mp_info         memory pool info.\n/// \\param[in]  block           address of the allocated memory block to be returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osRtxMemoryPoolFree (os_mp_info_t *mp_info, void *block) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask = __get_PRIMASK();\n#endif\n\n  //lint -e{946} \"Relational operator applied to pointers\"\n  if ((mp_info == NULL) || (block < mp_info->block_base) || (block >= mp_info->block_lim)) {\n    EvrRtxMemoryBlockFree(mp_info, block, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  //lint --e{9079} --e{9087} \"conversion from pointer to void to pointer to other type\"\n  *((void **)block) = mp_info->block_free;\n  mp_info->block_free = block;\n  mp_info->used_blocks--;\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  atomic_link_put(&mp_info->block_free, block);\n  (void)atomic_dec32(&mp_info->used_blocks);\n#endif\n\n  EvrRtxMemoryBlockFree(mp_info, block, (int32_t)osOK);\n\n  return osOK;\n}\n\n/// Destroy a Memory Pool object.\n/// \\param[in]  mp              memory pool object.\nstatic void osRtxMemoryPoolDestroy (os_memory_pool_t *mp) {\n\n  // Mark object as invalid\n  mp->id = osRtxIdInvalid;\n\n  // Free data memory\n  if ((mp->flags & osRtxFlagSystemMemory) != 0U) {\n    (void)osRtxMemoryFree(osRtxInfo.mem.mp_data, mp->mp_info.block_base);\n  }\n\n  // Free object memory\n  if ((mp->flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n    (void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);\n#else\n    if (osRtxInfo.mpi.memory_pool != NULL) {\n      (void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);\n    } else {\n      (void)osRtxMemoryFree(osRtxInfo.mem.common, mp);\n    }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n    osRtxMemoryPoolMemUsage.cnt_free++;\n#endif\n  }\n\n  EvrRtxMemoryPoolDestroyed(mp);\n}\n\n#ifdef RTX_SAFETY_CLASS\n/// Delete a Memory Pool safety class.\n/// \\param[in]  safety_class    safety class.\n/// \\param[in]  mode            safety mode.\nvoid osRtxMemoryPoolDeleteClass  (uint32_t safety_class, uint32_t mode) {\n  os_memory_pool_t *mp;\n  os_thread_t      *thread;\n  uint32_t          length;\n\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  mp     = (os_memory_pool_t *)(uint32_t)&__os_mempool_cb_start__;\n  length =                     (uint32_t)&__os_mempool_cb_length__;\n  while (length >= sizeof(os_memory_pool_t)) {\n    if (   (mp->id == osRtxIdMemoryPool) &&\n        ((((mode & osSafetyWithSameClass)  != 0U) &&\n          ((mp->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n         (((mode & osSafetyWithLowerClass) != 0U) &&\n          ((mp->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class)))) {\n      while (mp->thread_list != NULL) {\n        thread = osRtxThreadListGet(osRtxObject(mp));\n        osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);\n      }\n      osRtxMemoryPoolDestroy(mp);\n    }\n    length -= sizeof(os_memory_pool_t);\n    mp++;\n  }\n}\n#endif\n\n\n//  ==== Post ISR processing ====\n\n/// Memory Pool post ISR processing.\n/// \\param[in]  mp              memory pool object.\nstatic void osRtxMemoryPoolPostProcess (os_memory_pool_t *mp) {\n  void        *block;\n  os_thread_t *thread;\n\n  // Check if Thread is waiting to allocate memory\n  if (mp->thread_list != NULL) {\n    // Allocate memory\n    block = osRtxMemoryPoolAlloc(&mp->mp_info);\n    if (block != NULL) {\n      // Wakeup waiting Thread with highest Priority\n      thread = osRtxThreadListGet(osRtxObject(mp));\n      //lint -e{923} \"cast from pointer to unsigned int\"\n      osRtxThreadWaitExit(thread, (uint32_t)block, FALSE);\n      EvrRtxMemoryPoolAllocated(mp, block);\n    }\n  }\n}\n\n\n//  ==== Service Calls ====\n\n/// Create and Initialize a Memory Pool object.\n/// \\note API identical to osMemoryPoolNew\nstatic osMemoryPoolId_t svcRtxMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {\n  os_memory_pool_t  *mp;\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread = osRtxThreadGetRunning();\n  uint32_t           attr_bits;\n#endif\n  void              *mp_mem;\n  uint32_t           mp_size;\n  uint32_t           b_count;\n  uint32_t           b_size;\n  uint32_t           size;\n  uint8_t            flags;\n  const char        *name;\n\n  // Check parameters\n  if ((block_count == 0U) || (block_size == 0U) ||\n      ((__CLZ(block_count) + __CLZ(block_size)) < 32U)) {\n    EvrRtxMemoryPoolError(NULL, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  b_count =  block_count;\n  b_size  = (block_size + 3U) & ~3UL;\n  size    =  b_count * b_size;\n\n  // Process attributes\n  if (attr != NULL) {\n    name      = attr->name;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = attr->attr_bits;\n#endif\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    mp        = attr->cb_mem;\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    mp_mem    = attr->mp_mem;\n    mp_size   = attr->mp_size;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      if ((thread != NULL) &&\n          ((thread->attr >> osRtxAttrClass_Pos) <\n          (uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {\n        EvrRtxMemoryPoolError(NULL, (int32_t)osErrorSafetyClass);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n#endif\n    if (mp != NULL) {\n      if (!IsMemoryPoolPtrValid(mp) || (attr->cb_size != sizeof(os_memory_pool_t))) {\n        EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    } else {\n      if (attr->cb_size != 0U) {\n        EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n    if (mp_mem != NULL) {\n      //lint -e{923} \"cast from pointer to unsigned int\" [MISRA Note 7]\n      if ((((uint32_t)mp_mem & 3U) != 0U) || (mp_size < size)) {\n        EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    } else {\n      if (mp_size != 0U) {\n        EvrRtxMemoryPoolError(NULL, osRtxErrorInvalidDataMemory);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n  } else {\n    name      = NULL;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = 0U;\n#endif\n    mp        = NULL;\n    mp_mem    = NULL;\n  }\n\n  // Allocate object memory if not provided\n  if (mp == NULL) {\n    if (osRtxInfo.mpi.memory_pool != NULL) {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      mp = osRtxMemoryPoolAlloc(osRtxInfo.mpi.memory_pool);\n#ifndef RTX_OBJ_PTR_CHECK\n    } else {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      mp = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_memory_pool_t), 1U);\n#endif\n    }\n#ifdef RTX_OBJ_MEM_USAGE\n    if (mp != NULL) {\n      uint32_t used;\n      osRtxMemoryPoolMemUsage.cnt_alloc++;\n      used = osRtxMemoryPoolMemUsage.cnt_alloc - osRtxMemoryPoolMemUsage.cnt_free;\n      if (osRtxMemoryPoolMemUsage.max_used < used) {\n        osRtxMemoryPoolMemUsage.max_used = used;\n      }\n    }\n#endif\n    flags = osRtxFlagSystemObject;\n  } else {\n    flags = 0U;\n  }\n\n  // Allocate data memory if not provided\n  if ((mp != NULL) && (mp_mem == NULL)) {\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n    mp_mem = osRtxMemoryAlloc(osRtxInfo.mem.mp_data, size, 0U);\n    if (mp_mem == NULL) {\n      if ((flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n        (void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);\n#else\n        if (osRtxInfo.mpi.memory_pool != NULL) {\n          (void)osRtxMemoryPoolFree(osRtxInfo.mpi.memory_pool, mp);\n        } else {\n          (void)osRtxMemoryFree(osRtxInfo.mem.common, mp);\n        }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n        osRtxMemoryPoolMemUsage.cnt_free++;\n#endif\n      }\n      mp = NULL;\n    } else {\n      (void)memset(mp_mem, 0, size);\n    }\n    flags |= osRtxFlagSystemMemory;\n  }\n\n  if (mp != NULL) {\n    // Initialize control block\n    mp->id          = osRtxIdMemoryPool;\n    mp->flags       = flags;\n    mp->attr        = 0U;\n    mp->name        = name;\n    mp->thread_list = NULL;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      mp->attr     |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>\n                                (osSafetyClass_Pos - osRtxAttrClass_Pos));\n    } else {\n      // Inherit safety class from the running thread\n      if (thread != NULL) {\n        mp->attr   |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);\n      }\n    }\n#endif\n    (void)osRtxMemoryPoolInit(&mp->mp_info, b_count, b_size, mp_mem);\n\n    // Register post ISR processing function\n    osRtxInfo.post_process.memory_pool = osRtxMemoryPoolPostProcess;\n\n    EvrRtxMemoryPoolCreated(mp, mp->name);\n  } else {\n    EvrRtxMemoryPoolError(NULL, (int32_t)osErrorNoMemory);\n  }\n\n  return mp;\n}\n\n/// Get name of a Memory Pool object.\n/// \\note API identical to osMemoryPoolGetName\nstatic const char *svcRtxMemoryPoolGetName (osMemoryPoolId_t mp_id) {\n  os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {\n    EvrRtxMemoryPoolGetName(mp, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  EvrRtxMemoryPoolGetName(mp, mp->name);\n\n  return mp->name;\n}\n\n/// Allocate a memory block from a Memory Pool.\n/// \\note API identical to osMemoryPoolAlloc\nstatic void *svcRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {\n  os_memory_pool_t  *mp = osRtxMemoryPoolId(mp_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread;\n#endif\n  void              *block;\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {\n    EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (mp->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxMemoryPoolError(mp, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n#endif\n\n  // Allocate memory\n  block = osRtxMemoryPoolAlloc(&mp->mp_info);\n  if (block != NULL) {\n    EvrRtxMemoryPoolAllocated(mp, block);\n  } else {\n    // No memory available\n    if (timeout != 0U) {\n      EvrRtxMemoryPoolAllocPending(mp, timeout);\n      // Suspend current Thread\n      if (osRtxThreadWaitEnter(osRtxThreadWaitingMemoryPool, timeout)) {\n        osRtxThreadListPut(osRtxObject(mp), osRtxThreadGetRunning());\n      } else {\n        EvrRtxMemoryPoolAllocTimeout(mp);\n      }\n    } else {\n      EvrRtxMemoryPoolAllocFailed(mp);\n    }\n  }\n\n  return block;\n}\n\n/// Return an allocated memory block back to a Memory Pool.\n/// \\note API identical to osMemoryPoolFree\nstatic osStatus_t svcRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {\n  os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);\n  void             *block0;\n  os_thread_t      *thread;\n  osStatus_t        status;\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {\n    EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (mp->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxMemoryPoolError(mp, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Free memory\n  status = osRtxMemoryPoolFree(&mp->mp_info, block);\n  if (status == osOK) {\n    EvrRtxMemoryPoolDeallocated(mp, block);\n    // Check if Thread is waiting to allocate memory\n    if (mp->thread_list != NULL) {\n      // Allocate memory\n      block0 = osRtxMemoryPoolAlloc(&mp->mp_info);\n      if (block0 != NULL) {\n        // Wakeup waiting Thread with highest Priority\n        thread = osRtxThreadListGet(osRtxObject(mp));\n        //lint -e{923} \"cast from pointer to unsigned int\"\n        osRtxThreadWaitExit(thread, (uint32_t)block0, TRUE);\n        EvrRtxMemoryPoolAllocated(mp, block0);\n      }\n    }\n  } else {\n    EvrRtxMemoryPoolFreeFailed(mp, block);\n  }\n\n  return status;\n}\n\n/// Get maximum number of memory blocks in a Memory Pool.\n/// \\note API identical to osMemoryPoolGetCapacity\nstatic uint32_t svcRtxMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {\n  os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {\n    EvrRtxMemoryPoolGetCapacity(mp, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxMemoryPoolGetCapacity(mp, mp->mp_info.max_blocks);\n\n  return mp->mp_info.max_blocks;\n}\n\n/// Get memory block size in a Memory Pool.\n/// \\note API identical to osMemoryPoolGetBlockSize\nstatic uint32_t svcRtxMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {\n  os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {\n    EvrRtxMemoryPoolGetBlockSize(mp, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxMemoryPoolGetBlockSize(mp, mp->mp_info.block_size);\n\n  return mp->mp_info.block_size;\n}\n\n/// Get number of memory blocks used in a Memory Pool.\n/// \\note API identical to osMemoryPoolGetCount\nstatic uint32_t svcRtxMemoryPoolGetCount (osMemoryPoolId_t mp_id) {\n  os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {\n    EvrRtxMemoryPoolGetCount(mp, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxMemoryPoolGetCount(mp, mp->mp_info.used_blocks);\n\n  return mp->mp_info.used_blocks;\n}\n\n/// Get number of memory blocks available in a Memory Pool.\n/// \\note API identical to osMemoryPoolGetSpace\nstatic uint32_t svcRtxMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {\n  os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {\n    EvrRtxMemoryPoolGetSpace(mp, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxMemoryPoolGetSpace(mp, mp->mp_info.max_blocks - mp->mp_info.used_blocks);\n\n  return (mp->mp_info.max_blocks - mp->mp_info.used_blocks);\n}\n\n/// Delete a Memory Pool object.\n/// \\note API identical to osMemoryPoolDelete\nstatic osStatus_t svcRtxMemoryPoolDelete (osMemoryPoolId_t mp_id) {\n  os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);\n  os_thread_t      *thread;\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {\n    EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (mp->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxMemoryPoolError(mp, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Unblock waiting threads\n  if (mp->thread_list != NULL) {\n    do {\n      thread = osRtxThreadListGet(osRtxObject(mp));\n      osRtxThreadWaitExit(thread, 0U, FALSE);\n    } while (mp->thread_list != NULL);\n    osRtxThreadDispatch(NULL);\n  }\n\n  osRtxMemoryPoolDestroy(mp);\n\n  return osOK;\n}\n\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_3(MemoryPoolNew,          osMemoryPoolId_t, uint32_t, uint32_t, const osMemoryPoolAttr_t *)\nSVC0_1(MemoryPoolGetName,      const char *,     osMemoryPoolId_t)\nSVC0_2(MemoryPoolAlloc,        void *,           osMemoryPoolId_t, uint32_t)\nSVC0_2(MemoryPoolFree,         osStatus_t,       osMemoryPoolId_t, void *)\nSVC0_1(MemoryPoolGetCapacity,  uint32_t,         osMemoryPoolId_t)\nSVC0_1(MemoryPoolGetBlockSize, uint32_t,         osMemoryPoolId_t)\nSVC0_1(MemoryPoolGetCount,     uint32_t,         osMemoryPoolId_t)\nSVC0_1(MemoryPoolGetSpace,     uint32_t,         osMemoryPoolId_t)\nSVC0_1(MemoryPoolDelete,       osStatus_t,       osMemoryPoolId_t)\n//lint --flb \"Library End\"\n\n\n//  ==== ISR Calls ====\n\n/// Allocate a memory block from a Memory Pool.\n/// \\note API identical to osMemoryPoolAlloc\n__STATIC_INLINE\nvoid *isrRtxMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {\n  os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);\n  void             *block;\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool) || (timeout != 0U)) {\n    EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  // Allocate memory\n  block = osRtxMemoryPoolAlloc(&mp->mp_info);\n  if (block == NULL) {\n    EvrRtxMemoryPoolAllocFailed(mp);\n  } else {\n    EvrRtxMemoryPoolAllocated(mp, block);\n  }\n\n  return block;\n}\n\n/// Return an allocated memory block back to a Memory Pool.\n/// \\note API identical to osMemoryPoolFree\n__STATIC_INLINE\nosStatus_t isrRtxMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {\n  os_memory_pool_t *mp = osRtxMemoryPoolId(mp_id);\n  osStatus_t        status;\n\n  // Check parameters\n  if (!IsMemoryPoolPtrValid(mp) || (mp->id != osRtxIdMemoryPool)) {\n    EvrRtxMemoryPoolError(mp, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Free memory\n  status = osRtxMemoryPoolFree(&mp->mp_info, block);\n  if (status == osOK) {\n    // Register post ISR processing\n    osRtxPostProcess(osRtxObject(mp));\n    EvrRtxMemoryPoolDeallocated(mp, block);\n  } else {\n    EvrRtxMemoryPoolFreeFailed(mp, block);\n  }\n\n  return status;\n}\n\n\n//  ==== Public API ====\n\n/// Create and Initialize a Memory Pool object.\nosMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {\n  osMemoryPoolId_t mp_id;\n\n  EvrRtxMemoryPoolNew(block_count, block_size, attr);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMemoryPoolError(NULL, (int32_t)osErrorISR);\n    mp_id = NULL;\n  } else {\n    mp_id = __svcMemoryPoolNew(block_count, block_size, attr);\n  }\n  return mp_id;\n}\n\n/// Get name of a Memory Pool object.\nconst char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) {\n  const char *name;\n\n  if (IsException() || IsIrqMasked()) {\n    name = svcRtxMemoryPoolGetName(mp_id);\n  } else {\n    name =  __svcMemoryPoolGetName(mp_id);\n  }\n  return name;\n}\n\n/// Allocate a memory block from a Memory Pool.\nvoid *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {\n  void *memory;\n\n  EvrRtxMemoryPoolAlloc(mp_id, timeout);\n  if (IsException() || IsIrqMasked()) {\n    memory = isrRtxMemoryPoolAlloc(mp_id, timeout);\n  } else {\n    memory =  __svcMemoryPoolAlloc(mp_id, timeout);\n  }\n  return memory;\n}\n\n/// Return an allocated memory block back to a Memory Pool.\nosStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {\n  osStatus_t status;\n\n  EvrRtxMemoryPoolFree(mp_id, block);\n  if (IsException() || IsIrqMasked()) {\n    status = isrRtxMemoryPoolFree(mp_id, block);\n  } else {\n    status =  __svcMemoryPoolFree(mp_id, block);\n  }\n  return status;\n}\n\n/// Get maximum number of memory blocks in a Memory Pool.\nuint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {\n  uint32_t capacity;\n\n  if (IsException() || IsIrqMasked()) {\n    capacity = svcRtxMemoryPoolGetCapacity(mp_id);\n  } else {\n    capacity =  __svcMemoryPoolGetCapacity(mp_id);\n  }\n  return capacity;\n}\n\n/// Get memory block size in a Memory Pool.\nuint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {\n  uint32_t block_size;\n\n  if (IsException() || IsIrqMasked()) {\n    block_size = svcRtxMemoryPoolGetBlockSize(mp_id);\n  } else {\n    block_size =  __svcMemoryPoolGetBlockSize(mp_id);\n  }\n  return block_size;\n}\n\n/// Get number of memory blocks used in a Memory Pool.\nuint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) {\n  uint32_t count;\n\n  if (IsException() || IsIrqMasked()) {\n    count = svcRtxMemoryPoolGetCount(mp_id);\n  } else {\n    count =  __svcMemoryPoolGetCount(mp_id);\n  }\n  return count;\n}\n\n/// Get number of memory blocks available in a Memory Pool.\nuint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {\n  uint32_t space;\n\n  if (IsException() || IsIrqMasked()) {\n    space = svcRtxMemoryPoolGetSpace(mp_id);\n  } else {\n    space =  __svcMemoryPoolGetSpace(mp_id);\n  }\n  return space;\n}\n\n/// Delete a Memory Pool object.\nosStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) {\n  osStatus_t status;\n\n  EvrRtxMemoryPoolDelete(mp_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMemoryPoolError(mp_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcMemoryPoolDelete(mp_id);\n  }\n  return status;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_msgqueue.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Message Queue functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  OS Runtime Object Memory Usage\n#ifdef RTX_OBJ_MEM_USAGE\nosRtxObjectMemUsage_t osRtxMessageQueueMemUsage \\\n__attribute__((section(\".data.os.msgqueue.obj\"))) =\n{ 0U, 0U, 0U };\n#endif\n\n\n//  ==== Helper functions ====\n\n/// Put a Message into Queue sorted by Priority (Highest at Head).\n/// \\param[in]  mq              message queue object.\n/// \\param[in]  msg             message object.\nstatic void MessageQueuePut (os_message_queue_t *mq, os_message_t *msg) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t      primask = __get_PRIMASK();\n#endif\n  os_message_t *prev, *next;\n\n  if (mq->msg_last != NULL) {\n    prev = mq->msg_last;\n    next = NULL;\n    while ((prev != NULL) && (prev->priority < msg->priority)) {\n      next = prev;\n      prev = prev->prev;\n    }\n    msg->prev = prev;\n    msg->next = next;\n    if (prev != NULL) {\n      prev->next = msg;\n    } else {\n      mq->msg_first = msg;\n    }\n    if (next != NULL) {\n      next->prev = msg;\n    } else {\n      mq->msg_last = msg;\n    }\n  } else {\n    msg->prev = NULL;\n    msg->next = NULL;\n    mq->msg_first= msg;\n    mq->msg_last = msg;\n  }\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  mq->msg_count++;\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  (void)atomic_inc32(&mq->msg_count);\n#endif\n}\n\n/// Get a Message from Queue with Highest Priority.\n/// \\param[in]  mq              message queue object.\n/// \\return message object or NULL.\nstatic os_message_t *MessageQueueGet (os_message_queue_t *mq) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t      primask = __get_PRIMASK();\n#endif\n  os_message_t *msg;\n  uint32_t      count;\n  uint8_t       flags;\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  count = mq->msg_count;\n  if (count != 0U) {\n    mq->msg_count--;\n  }\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  count = atomic_dec32_nz(&mq->msg_count);\n#endif\n\n  if (count != 0U) {\n    msg = mq->msg_first;\n\n    while (msg != NULL) {\n#if (EXCLUSIVE_ACCESS == 0)\n      __disable_irq();\n\n      flags = msg->flags;\n      msg->flags = 1U;\n\n      if (primask == 0U) {\n        __enable_irq();\n      }\n#else\n      flags = atomic_wr8(&msg->flags, 1U);\n#endif\n      if (flags == 0U) {\n        break;\n      }\n      msg = msg->next;\n    }\n  } else {\n    msg = NULL;\n  }\n\n  return msg;\n}\n\n/// Remove a Message from Queue\n/// \\param[in]  mq              message queue object.\n/// \\param[in]  msg             message object.\nstatic void MessageQueueRemove (os_message_queue_t *mq, const os_message_t *msg) {\n\n  if (msg->prev != NULL) {\n    msg->prev->next = msg->next;\n  } else {\n    mq->msg_first = msg->next;\n  }\n  if (msg->next != NULL) {\n    msg->next->prev = msg->prev;\n  } else {\n    mq->msg_last = msg->prev;\n  }\n}\n\n/// Verify that Message Queue object pointer is valid.\n/// \\param[in]  mq              message queue object.\n/// \\return true - valid, false - invalid.\nstatic bool_t IsMessageQueuePtrValid (const os_message_queue_t *mq) {\n#ifdef RTX_OBJ_PTR_CHECK\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  uint32_t cb_start  = (uint32_t)&__os_msgqueue_cb_start__;\n  uint32_t cb_length = (uint32_t)&__os_msgqueue_cb_length__;\n\n  // Check the section boundaries\n  if (((uint32_t)mq - cb_start) >= cb_length) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n  // Check the object alignment\n  if ((((uint32_t)mq - cb_start) % sizeof(os_message_queue_t)) != 0U) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#else\n  // Check NULL pointer\n  if (mq == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#endif\n  return TRUE;\n}\n\n\n//  ==== Library functions ====\n\n/// Destroy a Message Queue object.\n/// \\param[in]  mq              message queue object.\nstatic void osRtxMessageQueueDestroy (os_message_queue_t *mq) {\n\n  // Mark object as invalid\n  mq->id = osRtxIdInvalid;\n\n  // Free data memory\n  if ((mq->flags & osRtxFlagSystemMemory) != 0U) {\n    (void)osRtxMemoryFree(osRtxInfo.mem.mq_data, mq->mp_info.block_base);\n  }\n\n  // Free object memory\n  if ((mq->flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n    (void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);\n#else\n    if (osRtxInfo.mpi.message_queue != NULL) {\n      (void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);\n    } else {\n      (void)osRtxMemoryFree(osRtxInfo.mem.common, mq);\n    }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n    osRtxMessageQueueMemUsage.cnt_free++;\n#endif\n  }\n\n  EvrRtxMessageQueueDestroyed(mq);\n}\n\n#ifdef RTX_SAFETY_CLASS\n/// Delete a Message Queue safety class.\n/// \\param[in]  safety_class    safety class.\n/// \\param[in]  mode            safety mode.\nvoid osRtxMessageQueueDeleteClass (uint32_t safety_class, uint32_t mode) {\n  os_message_queue_t *mq;\n  os_thread_t        *thread;\n  uint32_t            length;\n\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  mq     = (os_message_queue_t *)(uint32_t)&__os_msgqueue_cb_start__;\n  length =                       (uint32_t)&__os_msgqueue_cb_length__;\n  while (length >= sizeof(os_message_queue_t)) {\n    if (   (mq->id == osRtxIdMessageQueue) &&\n        ((((mode & osSafetyWithSameClass)  != 0U) &&\n          ((mq->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n         (((mode & osSafetyWithLowerClass) != 0U) &&\n          ((mq->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class)))) {\n      while (mq->thread_list != NULL) {\n        thread = osRtxThreadListGet(osRtxObject(mq));\n        osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);\n      }\n      osRtxMessageQueueDestroy(mq);\n    }\n    length -= sizeof(os_message_queue_t);\n    mq++;\n  }\n}\n#endif\n\n\n//  ==== Post ISR processing ====\n\n/// Message Queue post ISR processing.\n/// \\param[in]  msg             message object.\nstatic void osRtxMessageQueuePostProcess (os_message_t *msg) {\n  //lint --e{954} \"Pointer variable 'reg' is not pointing to const\"\n  os_message_queue_t *mq;\n  os_message_t       *msg0;\n  os_thread_t        *thread;\n  uint32_t           *reg;\n  const void         *ptr_src;\n        void         *ptr_dst;\n\n  if (msg->flags != 0U) {\n    // Remove Message\n    //lint -e{9079} -e{9087} \"cast between pointers to different object types\"\n    mq = *((os_message_queue_t **)(void *)&msg[1]);\n    MessageQueueRemove(mq, msg);\n    // Free memory\n    msg->id = osRtxIdInvalid;\n    (void)osRtxMemoryPoolFree(&mq->mp_info, msg);\n    // Check if Thread is waiting to send a Message\n    if (mq->thread_list != NULL) {\n      // Try to allocate memory\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      msg0 = osRtxMemoryPoolAlloc(&mq->mp_info);\n      if (msg0 != NULL) {\n        // Wakeup waiting Thread with highest Priority\n        thread = osRtxThreadListGet(osRtxObject(mq));\n        osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);\n        // Copy Message (R1: const void *msg_ptr, R2: uint8_t msg_prio)\n        reg = osRtxThreadRegPtr(thread);\n        //lint -e{923} \"cast from unsigned int to pointer\"\n        ptr_src = (const void *)reg[1];\n        (void)memcpy(&msg0[1], ptr_src, mq->msg_size);\n        // Store Message into Queue\n        msg0->id       = osRtxIdMessage;\n        msg0->flags    = 0U;\n        msg0->priority = (uint8_t)reg[2];\n        MessageQueuePut(mq, msg0);\n        EvrRtxMessageQueueInserted(mq, ptr_src);\n      }\n    }\n  } else {\n    // New Message\n    //lint -e{9079} -e{9087} \"cast between pointers to different object types\"\n    mq = (void *)msg->next;\n    //lint -e{9087} \"cast between pointers to different object types\"\n    ptr_src = (const void *)msg->prev;\n    // Check if Thread is waiting to receive a Message\n    if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) {\n      EvrRtxMessageQueueInserted(mq, ptr_src);\n      // Wakeup waiting Thread with highest Priority\n      thread = osRtxThreadListGet(osRtxObject(mq));\n      osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);\n      // Copy Message (R1: void *msg_ptr, R2: uint8_t *msg_prio)\n      reg = osRtxThreadRegPtr(thread);\n      //lint -e{923} \"cast from unsigned int to pointer\"\n      ptr_dst = (void *)reg[1];\n      (void)memcpy(ptr_dst, &msg[1], mq->msg_size);\n      if (reg[2] != 0U) {\n        //lint -e{923} -e{9078} \"cast from unsigned int to pointer\"\n        *((uint8_t *)reg[2]) = msg->priority;\n      }\n      EvrRtxMessageQueueRetrieved(mq, ptr_dst);\n      // Free memory\n      msg->id = osRtxIdInvalid;\n      (void)osRtxMemoryPoolFree(&mq->mp_info, msg);\n    } else {\n      EvrRtxMessageQueueInserted(mq, ptr_src);\n      MessageQueuePut(mq, msg);\n    }\n  }\n}\n\n\n//  ==== Service Calls ====\n\n/// Create and Initialize a Message Queue object.\n/// \\note API identical to osMessageQueueNew\nstatic osMessageQueueId_t svcRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {\n  os_message_queue_t *mq;\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t  *thread = osRtxThreadGetRunning();\n  uint32_t            attr_bits;\n#endif\n  void               *mq_mem;\n  uint32_t            mq_size;\n  uint32_t            block_size;\n  uint32_t            size;\n  uint8_t             flags;\n  const char         *name;\n\n  // Check parameters\n  if ((msg_count == 0U) || (msg_size == 0U) ||\n      ((__CLZ(msg_count) + __CLZ(msg_size)) < 32U)) {\n    EvrRtxMessageQueueError(NULL, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  block_size = ((msg_size + 3U) & ~3UL) + sizeof(os_message_t);\n  size       = msg_count * block_size;\n\n  // Process attributes\n  if (attr != NULL) {\n    name      = attr->name;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = attr->attr_bits;\n#endif\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    mq        = attr->cb_mem;\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    mq_mem    = attr->mq_mem;\n    mq_size   = attr->mq_size;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      if ((thread != NULL) &&\n          ((thread->attr >> osRtxAttrClass_Pos) <\n          (uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {\n        EvrRtxMessageQueueError(NULL, (int32_t)osErrorSafetyClass);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n#endif\n    if (mq != NULL) {\n      if (!IsMessageQueuePtrValid(mq) || (attr->cb_size != sizeof(os_message_queue_t))) {\n        EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    } else {\n      if (attr->cb_size != 0U) {\n        EvrRtxMessageQueueError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n    if (mq_mem != NULL) {\n      //lint -e{923} \"cast from pointer to unsigned int\" [MISRA Note 7]\n      if ((((uint32_t)mq_mem & 3U) != 0U) || (mq_size < size)) {\n        EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    } else {\n      if (mq_size != 0U) {\n        EvrRtxMessageQueueError(NULL, osRtxErrorInvalidDataMemory);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n  } else {\n    name      = NULL;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = 0U;\n#endif\n    mq        = NULL;\n    mq_mem    = NULL;\n  }\n\n  // Allocate object memory if not provided\n  if (mq == NULL) {\n    if (osRtxInfo.mpi.message_queue != NULL) {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      mq = osRtxMemoryPoolAlloc(osRtxInfo.mpi.message_queue);\n#ifndef RTX_OBJ_PTR_CHECK\n    } else {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      mq = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_message_queue_t), 1U);\n#endif\n    }\n#ifdef RTX_OBJ_MEM_USAGE\n    if (mq != NULL) {\n      uint32_t used;\n      osRtxMessageQueueMemUsage.cnt_alloc++;\n      used = osRtxMessageQueueMemUsage.cnt_alloc - osRtxMessageQueueMemUsage.cnt_free;\n      if (osRtxMessageQueueMemUsage.max_used < used) {\n        osRtxMessageQueueMemUsage.max_used = used;\n      }\n    }\n#endif\n    flags = osRtxFlagSystemObject;\n  } else {\n    flags = 0U;\n  }\n\n  // Allocate data memory if not provided\n  if ((mq != NULL) && (mq_mem == NULL)) {\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n    mq_mem = osRtxMemoryAlloc(osRtxInfo.mem.mq_data, size, 0U);\n    if (mq_mem == NULL) {\n      if ((flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n        (void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);\n#else\n        if (osRtxInfo.mpi.message_queue != NULL) {\n          (void)osRtxMemoryPoolFree(osRtxInfo.mpi.message_queue, mq);\n        } else {\n          (void)osRtxMemoryFree(osRtxInfo.mem.common, mq);\n        }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n        osRtxMessageQueueMemUsage.cnt_free++;\n#endif\n      }\n      mq = NULL;\n    } else {\n      (void)memset(mq_mem, 0, size);\n    }\n    flags |= osRtxFlagSystemMemory;\n  }\n\n  if (mq != NULL) {\n    // Initialize control block\n    mq->id          = osRtxIdMessageQueue;\n    mq->flags       = flags;\n    mq->attr        = 0U;\n    mq->name        = name;\n    mq->thread_list = NULL;\n    mq->msg_size    = msg_size;\n    mq->msg_count   = 0U;\n    mq->msg_first   = NULL;\n    mq->msg_last    = NULL;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      mq->attr     |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>\n                                (osSafetyClass_Pos - osRtxAttrClass_Pos));\n    } else {\n      // Inherit safety class from the running thread\n      if (thread != NULL) {\n        mq->attr   |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);\n      }\n    }\n#endif\n    (void)osRtxMemoryPoolInit(&mq->mp_info, msg_count, block_size, mq_mem);\n\n    // Register post ISR processing function\n    osRtxInfo.post_process.message = osRtxMessageQueuePostProcess;\n\n    EvrRtxMessageQueueCreated(mq, mq->name);\n  } else {\n    EvrRtxMessageQueueError(NULL, (int32_t)osErrorNoMemory);\n  }\n\n  return mq;\n}\n\n/// Get name of a Message Queue object.\n/// \\note API identical to osMessageQueueGetName\nstatic const char *svcRtxMessageQueueGetName (osMessageQueueId_t mq_id) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {\n    EvrRtxMessageQueueGetName(mq, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  EvrRtxMessageQueueGetName(mq, mq->name);\n\n  return mq->name;\n}\n\n/// Put a Message into a Queue or timeout if Queue is full.\n/// \\note API identical to osMessageQueuePut\nstatic osStatus_t svcRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {\n  //lint --e{954} \"Pointer variable 'reg' is not pointing to const\"\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n  os_message_t       *msg;\n  os_thread_t        *thread;\n  uint32_t           *reg;\n  void               *ptr;\n  osStatus_t          status;\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (mq->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check if Thread is waiting to receive a Message\n  if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessageGet)) {\n    EvrRtxMessageQueueInserted(mq, msg_ptr);\n    // Wakeup waiting Thread with highest Priority\n    thread = osRtxThreadListGet(osRtxObject(mq));\n    osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE);\n    // Copy Message (R1: void *msg_ptr, R2: uint8_t *msg_prio)\n    reg = osRtxThreadRegPtr(thread);\n    //lint -e{923} \"cast from unsigned int to pointer\"\n    ptr = (void *)reg[1];\n    (void)memcpy(ptr, msg_ptr, mq->msg_size);\n    if (reg[2] != 0U) {\n      //lint -e{923} -e{9078} \"cast from unsigned int to pointer\"\n      *((uint8_t *)reg[2]) = msg_prio;\n    }\n    EvrRtxMessageQueueRetrieved(mq, ptr);\n    status = osOK;\n  } else {\n    // Try to allocate memory\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n    msg = osRtxMemoryPoolAlloc(&mq->mp_info);\n    if (msg != NULL) {\n      // Copy Message\n      (void)memcpy(&msg[1], msg_ptr, mq->msg_size);\n      // Put Message into Queue\n      msg->id       = osRtxIdMessage;\n      msg->flags    = 0U;\n      msg->priority = msg_prio;\n      MessageQueuePut(mq, msg);\n      EvrRtxMessageQueueInserted(mq, msg_ptr);\n      status = osOK;\n    } else {\n      // No memory available\n      if (timeout != 0U) {\n        EvrRtxMessageQueuePutPending(mq, msg_ptr, timeout);\n        // Suspend current Thread\n        if (osRtxThreadWaitEnter(osRtxThreadWaitingMessagePut, timeout)) {\n          osRtxThreadListPut(osRtxObject(mq), osRtxThreadGetRunning());\n        } else {\n          EvrRtxMessageQueuePutTimeout(mq);\n        }\n        status = osErrorTimeout;\n      } else {\n        EvrRtxMessageQueueNotInserted(mq, msg_ptr);\n        status = osErrorResource;\n      }\n    }\n  }\n\n  return status;\n}\n\n/// Get a Message from a Queue or timeout if Queue is empty.\n/// \\note API identical to osMessageQueueGet\nstatic osStatus_t svcRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n  os_message_t       *msg;\n  os_thread_t        *thread;\n  const uint32_t     *reg;\n  const void         *ptr;\n  osStatus_t          status;\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL)) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (mq->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Get Message from Queue\n  msg = MessageQueueGet(mq);\n  if (msg != NULL) {\n    MessageQueueRemove(mq, msg);\n    // Copy Message\n    (void)memcpy(msg_ptr, &msg[1], mq->msg_size);\n    if (msg_prio != NULL) {\n      *msg_prio = msg->priority;\n    }\n    EvrRtxMessageQueueRetrieved(mq, msg_ptr);\n    // Free memory\n    msg->id = osRtxIdInvalid;\n    (void)osRtxMemoryPoolFree(&mq->mp_info, msg);\n    // Check if Thread is waiting to send a Message\n    if (mq->thread_list != NULL) {\n      // Try to allocate memory\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      msg = osRtxMemoryPoolAlloc(&mq->mp_info);\n      if (msg != NULL) {\n        // Wakeup waiting Thread with highest Priority\n        thread = osRtxThreadListGet(osRtxObject(mq));\n        osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE);\n        // Copy Message (R1: const void *msg_ptr, R2: uint8_t msg_prio)\n        reg = osRtxThreadRegPtr(thread);\n        //lint -e{923} \"cast from unsigned int to pointer\"\n        ptr = (const void *)reg[1];\n        (void)memcpy(&msg[1], ptr, mq->msg_size);\n        // Store Message into Queue\n        msg->id       = osRtxIdMessage;\n        msg->flags    = 0U;\n        msg->priority = (uint8_t)reg[2];\n        MessageQueuePut(mq, msg);\n        EvrRtxMessageQueueInserted(mq, ptr);\n      }\n    }\n    status = osOK;\n  } else {\n    // No Message available\n    if (timeout != 0U) {\n      EvrRtxMessageQueueGetPending(mq, msg_ptr, timeout);\n      // Suspend current Thread\n      if (osRtxThreadWaitEnter(osRtxThreadWaitingMessageGet, timeout)) {\n        osRtxThreadListPut(osRtxObject(mq), osRtxThreadGetRunning());\n      } else {\n        EvrRtxMessageQueueGetTimeout(mq);\n      }\n      status = osErrorTimeout;\n    } else {\n      EvrRtxMessageQueueNotRetrieved(mq, msg_ptr);\n      status = osErrorResource;\n    }\n  }\n\n  return status;\n}\n\n/// Get maximum number of messages in a Message Queue.\n/// \\note API identical to osMessageQueueGetCapacity\nstatic uint32_t svcRtxMessageQueueGetCapacity (osMessageQueueId_t mq_id) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {\n    EvrRtxMessageQueueGetCapacity(mq, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxMessageQueueGetCapacity(mq, mq->mp_info.max_blocks);\n\n  return mq->mp_info.max_blocks;\n}\n\n/// Get maximum message size in a Memory Pool.\n/// \\note API identical to osMessageQueueGetMsgSize\nstatic uint32_t svcRtxMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {\n    EvrRtxMessageQueueGetMsgSize(mq, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxMessageQueueGetMsgSize(mq, mq->msg_size);\n\n  return mq->msg_size;\n}\n\n/// Get number of queued messages in a Message Queue.\n/// \\note API identical to osMessageQueueGetCount\nstatic uint32_t svcRtxMessageQueueGetCount (osMessageQueueId_t mq_id) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {\n    EvrRtxMessageQueueGetCount(mq, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxMessageQueueGetCount(mq, mq->msg_count);\n\n  return mq->msg_count;\n}\n\n/// Get number of available slots for messages in a Message Queue.\n/// \\note API identical to osMessageQueueGetSpace\nstatic uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_id) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {\n    EvrRtxMessageQueueGetSpace(mq, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxMessageQueueGetSpace(mq, mq->mp_info.max_blocks - mq->msg_count);\n\n  return (mq->mp_info.max_blocks - mq->msg_count);\n}\n\n/// Reset a Message Queue to initial empty state.\n/// \\note API identical to osMessageQueueReset\nstatic osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n  os_message_t       *msg;\n  os_thread_t        *thread;\n  const uint32_t     *reg;\n  const void         *ptr;\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (mq->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Remove Messages from Queue\n  for (;;) {\n    // Get Message from Queue\n    msg = MessageQueueGet(mq);\n    if (msg == NULL) {\n      break;\n    }\n    MessageQueueRemove(mq, msg);\n    EvrRtxMessageQueueRetrieved(mq, NULL);\n    // Free memory\n    msg->id = osRtxIdInvalid;\n    (void)osRtxMemoryPoolFree(&mq->mp_info, msg);\n  }\n\n  // Check if Threads are waiting to send Messages\n  if ((mq->thread_list != NULL) && (mq->thread_list->state == osRtxThreadWaitingMessagePut)) {\n    do {\n      // Try to allocate memory\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      msg = osRtxMemoryPoolAlloc(&mq->mp_info);\n      if (msg != NULL) {\n        // Wakeup waiting Thread with highest Priority\n        thread = osRtxThreadListGet(osRtxObject(mq));\n        osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);\n        // Copy Message (R1: const void *msg_ptr, R2: uint8_t msg_prio)\n        reg = osRtxThreadRegPtr(thread);\n        //lint -e{923} \"cast from unsigned int to pointer\"\n        ptr = (const void *)reg[1];\n        (void)memcpy(&msg[1], ptr, mq->msg_size);\n        // Store Message into Queue\n        msg->id       = osRtxIdMessage;\n        msg->flags    = 0U;\n        msg->priority = (uint8_t)reg[2];\n        MessageQueuePut(mq, msg);\n        EvrRtxMessageQueueInserted(mq, ptr);\n      }\n    } while ((msg != NULL) && (mq->thread_list != NULL));\n    osRtxThreadDispatch(NULL);\n  }\n\n  EvrRtxMessageQueueResetDone(mq);\n\n  return osOK;\n}\n\n/// Delete a Message Queue object.\n/// \\note API identical to osMessageQueueDelete\nstatic osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n  os_thread_t        *thread;\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue)) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (mq->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Unblock waiting threads\n  if (mq->thread_list != NULL) {\n    do {\n      thread = osRtxThreadListGet(osRtxObject(mq));\n      osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);\n    } while (mq->thread_list != NULL);\n    osRtxThreadDispatch(NULL);\n  }\n\n  osRtxMessageQueueDestroy(mq);\n\n  return osOK;\n}\n\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_3(MessageQueueNew,         osMessageQueueId_t, uint32_t, uint32_t, const osMessageQueueAttr_t *)\nSVC0_1(MessageQueueGetName,     const char *,       osMessageQueueId_t)\nSVC0_4(MessageQueuePut,         osStatus_t,         osMessageQueueId_t, const void *, uint8_t,   uint32_t)\nSVC0_4(MessageQueueGet,         osStatus_t,         osMessageQueueId_t,       void *, uint8_t *, uint32_t)\nSVC0_1(MessageQueueGetCapacity, uint32_t,           osMessageQueueId_t)\nSVC0_1(MessageQueueGetMsgSize,  uint32_t,           osMessageQueueId_t)\nSVC0_1(MessageQueueGetCount,    uint32_t,           osMessageQueueId_t)\nSVC0_1(MessageQueueGetSpace,    uint32_t,           osMessageQueueId_t)\nSVC0_1(MessageQueueReset,       osStatus_t,         osMessageQueueId_t)\nSVC0_1(MessageQueueDelete,      osStatus_t,         osMessageQueueId_t)\n//lint --flb \"Library End\"\n\n\n//  ==== ISR Calls ====\n\n/// Put a Message into a Queue or timeout if Queue is full.\n/// \\note API identical to osMessageQueuePut\n__STATIC_INLINE\nosStatus_t isrRtxMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n  os_message_t       *msg;\n  osStatus_t          status;\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Try to allocate memory\n  //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n  msg = osRtxMemoryPoolAlloc(&mq->mp_info);\n  if (msg != NULL) {\n    // Copy Message\n    (void)memcpy(&msg[1], msg_ptr, mq->msg_size);\n    msg->id       = osRtxIdMessage;\n    msg->flags    = 0U;\n    msg->priority = msg_prio;\n    // Register post ISR processing\n    //lint -e{9079} -e{9087} \"cast between pointers to different object types\"\n    *((const void **)(void *)&msg->prev) = msg_ptr;\n    //lint -e{9079} -e{9087} \"cast between pointers to different object types\"\n    *(      (void **)        &msg->next) = mq;\n    osRtxPostProcess(osRtxObject(msg));\n    EvrRtxMessageQueueInsertPending(mq, msg_ptr);\n    status = osOK;\n  } else {\n    // No memory available\n    EvrRtxMessageQueueNotInserted(mq, msg_ptr);\n    status = osErrorResource;\n  }\n\n  return status;\n}\n\n/// Get a Message from a Queue or timeout if Queue is empty.\n/// \\note API identical to osMessageQueueGet\n__STATIC_INLINE\nosStatus_t isrRtxMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {\n  os_message_queue_t *mq = osRtxMessageQueueId(mq_id);\n  os_message_t       *msg;\n  osStatus_t          status;\n\n  // Check parameters\n  if (!IsMessageQueuePtrValid(mq) || (mq->id != osRtxIdMessageQueue) || (msg_ptr == NULL) || (timeout != 0U)) {\n    EvrRtxMessageQueueError(mq, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Get Message from Queue\n  msg = MessageQueueGet(mq);\n  if (msg != NULL) {\n    // Copy Message\n    memcpy(msg_ptr, &msg[1], mq->msg_size);\n    if (msg_prio != NULL) {\n      *msg_prio = msg->priority;\n    }\n    // Register post ISR processing\n    //lint -e{9079} -e{9087} \"cast between pointers to different object types\"\n    *((os_message_queue_t **)(void *)&msg[1]) = mq;\n    osRtxPostProcess(osRtxObject(msg));\n    EvrRtxMessageQueueRetrieved(mq, msg_ptr);\n    status = osOK;\n  } else {\n    // No Message available\n    EvrRtxMessageQueueNotRetrieved(mq, msg_ptr);\n    status = osErrorResource;\n  }\n\n  return status;\n}\n\n\n//  ==== Library functions ====\n\n/// Create a Message Queue for the Timer Thread.\nint32_t osRtxMessageQueueTimerSetup (void) {\n  int32_t ret = -1;\n\n  osRtxInfo.timer.mq = osRtxMessageQueueId(\n    svcRtxMessageQueueNew(osRtxConfig.timer_mq_mcnt, sizeof(os_timer_finfo_t), osRtxConfig.timer_mq_attr)\n  );\n  if (osRtxInfo.timer.mq != NULL) {\n    ret = 0;\n  }\n\n  return ret;\n}\n\n\n//  ==== Public API ====\n\n/// Create and Initialize a Message Queue object.\nosMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {\n  osMessageQueueId_t mq_id;\n\n  EvrRtxMessageQueueNew(msg_count, msg_size, attr);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMessageQueueError(NULL, (int32_t)osErrorISR);\n    mq_id = NULL;\n  } else {\n    mq_id = __svcMessageQueueNew(msg_count, msg_size, attr);\n  }\n  return mq_id;\n}\n\n/// Get name of a Message Queue object.\nconst char *osMessageQueueGetName (osMessageQueueId_t mq_id) {\n  const char *name;\n\n  if (IsException() || IsIrqMasked()) {\n    name = svcRtxMessageQueueGetName(mq_id);\n  } else {\n    name =  __svcMessageQueueGetName(mq_id);\n  }\n  return name;\n}\n\n/// Put a Message into a Queue or timeout if Queue is full.\nosStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {\n  osStatus_t status;\n\n  EvrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);\n  if (IsException() || IsIrqMasked()) {\n    status = isrRtxMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);\n  } else {\n    status =  __svcMessageQueuePut(mq_id, msg_ptr, msg_prio, timeout);\n  }\n  return status;\n}\n\n/// Get a Message from a Queue or timeout if Queue is empty.\nosStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {\n  osStatus_t status;\n\n  EvrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);\n  if (IsException() || IsIrqMasked()) {\n    status = isrRtxMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);\n  } else {\n    status =  __svcMessageQueueGet(mq_id, msg_ptr, msg_prio, timeout);\n  }\n  return status;\n}\n\n/// Get maximum number of messages in a Message Queue.\nuint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {\n  uint32_t capacity;\n\n  if (IsException() || IsIrqMasked()) {\n    capacity = svcRtxMessageQueueGetCapacity(mq_id);\n  } else {\n    capacity =  __svcMessageQueueGetCapacity(mq_id);\n  }\n  return capacity;\n}\n\n/// Get maximum message size in a Memory Pool.\nuint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {\n  uint32_t msg_size;\n\n  if (IsException() || IsIrqMasked()) {\n    msg_size = svcRtxMessageQueueGetMsgSize(mq_id);\n  } else {\n    msg_size =  __svcMessageQueueGetMsgSize(mq_id);\n  }\n  return msg_size;\n}\n\n/// Get number of queued messages in a Message Queue.\nuint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) {\n  uint32_t count;\n\n  if (IsException() || IsIrqMasked()) {\n    count = svcRtxMessageQueueGetCount(mq_id);\n  } else {\n    count =  __svcMessageQueueGetCount(mq_id);\n  }\n  return count;\n}\n\n/// Get number of available slots for messages in a Message Queue.\nuint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {\n  uint32_t space;\n\n  if (IsException() || IsIrqMasked()) {\n    space = svcRtxMessageQueueGetSpace(mq_id);\n  } else {\n    space =  __svcMessageQueueGetSpace(mq_id);\n  }\n  return space;\n}\n\n/// Reset a Message Queue to initial empty state.\nosStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) {\n  osStatus_t status;\n\n  EvrRtxMessageQueueReset(mq_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcMessageQueueReset(mq_id);\n  }\n  return status;\n}\n\n/// Delete a Message Queue object.\nosStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) {\n  osStatus_t status;\n\n  EvrRtxMessageQueueDelete(mq_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMessageQueueError(mq_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcMessageQueueDelete(mq_id);\n  }\n  return status;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_mutex.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Mutex functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  OS Runtime Object Memory Usage\n#ifdef RTX_OBJ_MEM_USAGE\nosRtxObjectMemUsage_t osRtxMutexMemUsage \\\n__attribute__((section(\".data.os.mutex.obj\"))) =\n{ 0U, 0U, 0U };\n#endif\n\n\n//  ==== Helper functions ====\n\n/// Verify that Mutex object pointer is valid.\n/// \\param[in]  mutex           mutex object.\n/// \\return true - valid, false - invalid.\nstatic bool_t IsMutexPtrValid (const os_mutex_t *mutex) {\n#ifdef RTX_OBJ_PTR_CHECK\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  uint32_t cb_start  = (uint32_t)&__os_mutex_cb_start__;\n  uint32_t cb_length = (uint32_t)&__os_mutex_cb_length__;\n\n  // Check the section boundaries\n  if (((uint32_t)mutex - cb_start) >= cb_length) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n  // Check the object alignment\n  if ((((uint32_t)mutex - cb_start) % sizeof(os_mutex_t)) != 0U) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#else\n  // Check NULL pointer\n  if (mutex == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#endif\n  return TRUE;\n}\n\n\n//  ==== Library functions ====\n\n/// Release Mutex list when owner Thread terminates.\n/// \\param[in]  mutex_list      mutex list.\nvoid osRtxMutexOwnerRelease (os_mutex_t *mutex_list) {\n  os_mutex_t  *mutex;\n  os_mutex_t  *mutex_next;\n  os_thread_t *thread;\n\n  mutex = mutex_list;\n  while (mutex != NULL) {\n    mutex_next = mutex->owner_next;\n    // Check if Mutex is Robust\n    if ((mutex->attr & osMutexRobust) != 0U) {\n      // Clear Lock counter\n      mutex->lock = 0U;\n      EvrRtxMutexReleased(mutex, 0U);\n      // Check if Thread is waiting for a Mutex\n      if (mutex->thread_list != NULL) {\n        // Wakeup waiting Thread with highest Priority\n        thread = osRtxThreadListGet(osRtxObject(mutex));\n        osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);\n        // Thread is the new Mutex owner\n        mutex->owner_thread = thread;\n        mutex->owner_prev   = NULL;\n        mutex->owner_next   = thread->mutex_list;\n        if (thread->mutex_list != NULL) {\n          thread->mutex_list->owner_prev = mutex;\n        }\n        thread->mutex_list = mutex;\n        mutex->lock = 1U;\n        EvrRtxMutexAcquired(mutex, 1U);\n      }\n    }\n    mutex = mutex_next;\n  }\n}\n\n/// Restore Mutex owner Thread priority.\n/// \\param[in]  mutex           mutex object.\n/// \\param[in]  thread_wakeup   thread wakeup object.\nvoid osRtxMutexOwnerRestore (const os_mutex_t *mutex, const os_thread_t *thread_wakeup) {\n  const os_mutex_t  *mutex0;\n        os_thread_t *thread;\n  const os_thread_t *thread0;\n        int8_t       priority;\n\n  // Restore owner Thread priority\n  if ((mutex->attr & osMutexPrioInherit) != 0U) {\n    thread   = mutex->owner_thread;\n    priority = thread->priority_base;\n    mutex0   = thread->mutex_list;\n    // Check Mutexes owned by Thread\n    do {\n      if ((mutex0->attr & osMutexPrioInherit) != 0U) {\n        // Check Threads waiting for Mutex\n        thread0 = mutex0->thread_list;\n        if (thread0 == thread_wakeup) {\n          // Skip thread that is waken-up\n          thread0 = thread0->thread_next;\n        }\n        if ((thread0 != NULL) && (thread0->priority > priority)) {\n          // Higher priority Thread is waiting for Mutex\n          priority = thread0->priority;\n        }\n      }\n      mutex0 = mutex0->owner_next;\n    } while (mutex0 != NULL);\n    if (thread->priority != priority) {\n      thread->priority = priority;\n      osRtxThreadListSort(thread);\n    }\n  }\n}\n\n/// Unlock Mutex owner when mutex is deleted.\n/// \\param[in]  mutex           mutex object.\n/// \\return true - successful, false - not locked.\nstatic bool_t osRtxMutexOwnerUnlock (os_mutex_t *mutex) {\n  const os_mutex_t  *mutex0;\n        os_thread_t *thread;\n        int8_t       priority;\n\n  // Check if Mutex is locked\n  if (mutex->lock == 0U) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n\n  thread = mutex->owner_thread;\n\n  // Remove Mutex from Thread owner list\n  if (mutex->owner_next != NULL) {\n    mutex->owner_next->owner_prev = mutex->owner_prev;\n  }\n  if (mutex->owner_prev != NULL) {\n    mutex->owner_prev->owner_next = mutex->owner_next;\n  } else {\n    thread->mutex_list = mutex->owner_next;\n  }\n\n  // Restore owner Thread priority\n  priority = thread->priority_base;\n  mutex0   = thread->mutex_list;\n  // Check Mutexes owned by Thread\n  while (mutex0 != NULL) {\n    if ((mutex0->attr & osMutexPrioInherit) != 0U) {\n      if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) {\n        // Higher priority Thread is waiting for Mutex\n        priority = mutex0->thread_list->priority;\n      }\n    }\n    mutex0 = mutex0->owner_next;\n  }\n  if (thread->priority != priority) {\n    thread->priority = priority;\n    osRtxThreadListSort(thread);\n  }\n\n  // Unblock waiting threads\n  while (mutex->thread_list != NULL) {\n    thread = osRtxThreadListGet(osRtxObject(mutex));\n    osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);\n  }\n\n  mutex->lock = 0U;\n\n  return TRUE;\n}\n\n/// Destroy a Mutex object.\n/// \\param[in]  mutex           mutex object.\nstatic void osRtxMutexDestroy (os_mutex_t *mutex) {\n\n  // Mark object as invalid\n  mutex->id = osRtxIdInvalid;\n\n  // Free object memory\n  if ((mutex->flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n    (void)osRtxMemoryPoolFree(osRtxInfo.mpi.mutex, mutex);\n#else\n    if (osRtxInfo.mpi.mutex != NULL) {\n      (void)osRtxMemoryPoolFree(osRtxInfo.mpi.mutex, mutex);\n    } else {\n      (void)osRtxMemoryFree(osRtxInfo.mem.common, mutex);\n    }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n    osRtxMutexMemUsage.cnt_free++;\n#endif\n  }\n  EvrRtxMutexDestroyed(mutex);\n}\n\n#ifdef RTX_SAFETY_CLASS\n/// Delete a Mutex safety class.\n/// \\param[in]  safety_class    safety class.\n/// \\param[in]  mode            safety mode.\nvoid osRtxMutexDeleteClass (uint32_t safety_class, uint32_t mode) {\n  os_mutex_t *mutex;\n  uint32_t    length;\n\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  mutex  = (os_mutex_t *)(uint32_t)&__os_mutex_cb_start__;\n  length =               (uint32_t)&__os_mutex_cb_length__;\n  while (length >= sizeof(os_mutex_t)) {\n    if (   (mutex->id == osRtxIdMutex) &&\n        ((((mode & osSafetyWithSameClass)  != 0U) &&\n          ((mutex->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n         (((mode & osSafetyWithLowerClass) != 0U) &&\n          ((mutex->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class)))) {\n      (void)osRtxMutexOwnerUnlock(mutex);\n      osRtxMutexDestroy(mutex);\n    }\n    length -= sizeof(os_mutex_t);\n    mutex++;\n  }\n}\n#endif\n\n\n//  ==== Service Calls ====\n\n/// Create and Initialize a Mutex object.\n/// \\note API identical to osMutexNew\nstatic osMutexId_t svcRtxMutexNew (const osMutexAttr_t *attr) {\n  os_mutex_t        *mutex;\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread = osRtxThreadGetRunning();\n#endif\n  uint32_t           attr_bits;\n  uint8_t            flags;\n  const char        *name;\n\n  // Process attributes\n  if (attr != NULL) {\n    name      = attr->name;\n    attr_bits = attr->attr_bits;\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    mutex     = attr->cb_mem;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      if ((thread != NULL) &&\n          ((thread->attr >> osRtxAttrClass_Pos) <\n          (uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {\n        EvrRtxMutexError(NULL, (int32_t)osErrorSafetyClass);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n#endif\n    if (mutex != NULL) {\n      if (!IsMutexPtrValid(mutex) || (attr->cb_size != sizeof(os_mutex_t))) {\n        EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    } else {\n      if (attr->cb_size != 0U) {\n        EvrRtxMutexError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n  } else {\n    name      = NULL;\n    attr_bits = 0U;\n    mutex     = NULL;\n  }\n\n  // Allocate object memory if not provided\n  if (mutex == NULL) {\n    if (osRtxInfo.mpi.mutex != NULL) {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      mutex = osRtxMemoryPoolAlloc(osRtxInfo.mpi.mutex);\n#ifndef RTX_OBJ_PTR_CHECK\n    } else {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      mutex = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_mutex_t), 1U);\n#endif\n    }\n#ifdef RTX_OBJ_MEM_USAGE\n    if (mutex != NULL) {\n      uint32_t used;\n      osRtxMutexMemUsage.cnt_alloc++;\n      used = osRtxMutexMemUsage.cnt_alloc - osRtxMutexMemUsage.cnt_free;\n      if (osRtxMutexMemUsage.max_used < used) {\n        osRtxMutexMemUsage.max_used = used;\n      }\n    }\n#endif\n    flags = osRtxFlagSystemObject;\n  } else {\n    flags = 0U;\n  }\n\n  if (mutex != NULL) {\n    // Initialize control block\n    mutex->id           = osRtxIdMutex;\n    mutex->flags        = flags;\n    mutex->attr         = (uint8_t)(attr_bits & ~osRtxAttrClass_Msk);\n    mutex->name         = name;\n    mutex->thread_list  = NULL;\n    mutex->owner_thread = NULL;\n    mutex->owner_prev   = NULL;\n    mutex->owner_next   = NULL;\n    mutex->lock         = 0U;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      mutex->attr      |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>\n                                    (osSafetyClass_Pos - osRtxAttrClass_Pos));\n    } else {\n      // Inherit safety class from the running thread\n      if (thread != NULL) {\n        mutex->attr    |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);\n      }\n    }\n#endif\n    EvrRtxMutexCreated(mutex, mutex->name);\n  } else {\n    EvrRtxMutexError(NULL, (int32_t)osErrorNoMemory);\n  }\n\n  return mutex;\n}\n\n/// Get name of a Mutex object.\n/// \\note API identical to osMutexGetName\nstatic const char *svcRtxMutexGetName (osMutexId_t mutex_id) {\n  os_mutex_t *mutex = osRtxMutexId(mutex_id);\n\n  // Check parameters\n  if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {\n    EvrRtxMutexGetName(mutex, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  EvrRtxMutexGetName(mutex, mutex->name);\n\n  return mutex->name;\n}\n\n/// Acquire a Mutex or timeout if it is locked.\n/// \\note API identical to osMutexAcquire\nstatic osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {\n  os_mutex_t  *mutex = osRtxMutexId(mutex_id);\n  os_thread_t *thread;\n  osStatus_t   status;\n\n  // Check running thread\n  thread = osRtxThreadGetRunning();\n  if (thread == NULL) {\n    EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osError;\n  }\n\n  // Check parameters\n  if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {\n    EvrRtxMutexError(mutex, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  if ((thread->attr >> osRtxAttrClass_Pos) < (mutex->attr >> osRtxAttrClass_Pos)) {\n    EvrRtxMutexError(mutex, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check if Mutex is not locked\n  if (mutex->lock == 0U) {\n    // Acquire Mutex\n    mutex->owner_thread = thread;\n    mutex->owner_prev   = NULL;\n    mutex->owner_next   = thread->mutex_list;\n    if (thread->mutex_list != NULL) {\n      thread->mutex_list->owner_prev = mutex;\n    }\n    thread->mutex_list = mutex;\n    mutex->lock = 1U;\n    EvrRtxMutexAcquired(mutex, mutex->lock);\n    status = osOK;\n  } else {\n    // Check if Mutex is recursive and running Thread is the owner\n    if (((mutex->attr & osMutexRecursive) != 0U) && (mutex->owner_thread == thread)) {\n      // Try to increment lock counter\n      if (mutex->lock == osRtxMutexLockLimit) {\n        EvrRtxMutexError(mutex, osRtxErrorMutexLockLimit);\n        status = osErrorResource;\n      } else {\n        mutex->lock++;\n        EvrRtxMutexAcquired(mutex, mutex->lock);\n        status = osOK;\n      }\n    } else {\n      // Check if timeout is specified\n      if (timeout != 0U) {\n        // Check if Priority inheritance protocol is enabled\n        if ((mutex->attr & osMutexPrioInherit) != 0U) {\n          // Raise priority of owner Thread if lower than priority of running Thread\n          if (mutex->owner_thread->priority < thread->priority) {\n            mutex->owner_thread->priority = thread->priority;\n            osRtxThreadListSort(mutex->owner_thread);\n          }\n        }\n        EvrRtxMutexAcquirePending(mutex, timeout);\n        // Suspend current Thread\n        if (osRtxThreadWaitEnter(osRtxThreadWaitingMutex, timeout)) {\n          osRtxThreadListPut(osRtxObject(mutex), thread);\n        } else {\n          EvrRtxMutexAcquireTimeout(mutex);\n        }\n        status = osErrorTimeout;\n      } else {\n        EvrRtxMutexNotAcquired(mutex);\n        status = osErrorResource;\n      }\n    }\n  }\n\n  return status;\n}\n\n/// Release a Mutex that was acquired by osMutexAcquire.\n/// \\note API identical to osMutexRelease\nstatic osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) {\n        os_mutex_t  *mutex = osRtxMutexId(mutex_id);\n  const os_mutex_t  *mutex0;\n        os_thread_t *thread;\n        int8_t       priority;\n\n  // Check running thread\n  thread = osRtxThreadGetRunning();\n  if (thread == NULL) {\n    EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osError;\n  }\n\n  // Check parameters\n  if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {\n    EvrRtxMutexError(mutex, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Check if Mutex is not locked\n  if (mutex->lock == 0U) {\n    EvrRtxMutexError(mutex, osRtxErrorMutexNotLocked);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorResource;\n  }\n\n  // Check if running Thread is not the owner\n  if (mutex->owner_thread != thread) {\n    EvrRtxMutexError(mutex, osRtxErrorMutexNotOwned);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorResource;\n  }\n\n  // Decrement Lock counter\n  mutex->lock--;\n  EvrRtxMutexReleased(mutex, mutex->lock);\n\n  // Check Lock counter\n  if (mutex->lock == 0U) {\n\n    // Remove Mutex from Thread owner list\n    if (mutex->owner_next != NULL) {\n      mutex->owner_next->owner_prev = mutex->owner_prev;\n    }\n    if (mutex->owner_prev != NULL) {\n      mutex->owner_prev->owner_next = mutex->owner_next;\n    } else {\n      thread->mutex_list = mutex->owner_next;\n    }\n\n    // Restore running Thread priority\n    priority = thread->priority_base;\n    mutex0   = thread->mutex_list;\n    // Check mutexes owned by running Thread\n    while (mutex0 != NULL) {\n      if ((mutex0->attr & osMutexPrioInherit) != 0U) {\n        if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) {\n          // Higher priority Thread is waiting for Mutex\n          priority = mutex0->thread_list->priority;\n        }\n      }\n      mutex0 = mutex0->owner_next;\n    }\n    thread->priority = priority;\n\n    // Check if Thread is waiting for a Mutex\n    if (mutex->thread_list != NULL) {\n      // Wakeup waiting Thread with highest Priority\n      thread = osRtxThreadListGet(osRtxObject(mutex));\n      osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);\n      // Thread is the new Mutex owner\n      mutex->owner_thread = thread;\n      mutex->owner_prev   = NULL;\n      mutex->owner_next   = thread->mutex_list;\n      if (thread->mutex_list != NULL) {\n        thread->mutex_list->owner_prev = mutex;\n      }\n      thread->mutex_list = mutex;\n      mutex->lock = 1U;\n      EvrRtxMutexAcquired(mutex, 1U);\n    }\n\n    osRtxThreadDispatch(NULL);\n  }\n\n  return osOK;\n}\n\n/// Get Thread which owns a Mutex object.\n/// \\note API identical to osMutexGetOwner\nstatic osThreadId_t svcRtxMutexGetOwner (osMutexId_t mutex_id) {\n  os_mutex_t *mutex = osRtxMutexId(mutex_id);\n\n  // Check parameters\n  if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {\n    EvrRtxMutexGetOwner(mutex, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  // Check if Mutex is not locked\n  if (mutex->lock == 0U) {\n    EvrRtxMutexGetOwner(mutex, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  EvrRtxMutexGetOwner(mutex, mutex->owner_thread);\n\n  return mutex->owner_thread;\n}\n\n/// Delete a Mutex object.\n/// \\note API identical to osMutexDelete\nstatic osStatus_t svcRtxMutexDelete (osMutexId_t mutex_id) {\n        os_mutex_t  *mutex = osRtxMutexId(mutex_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread;\n#endif\n\n  // Check parameters\n  if (!IsMutexPtrValid(mutex) || (mutex->id != osRtxIdMutex)) {\n    EvrRtxMutexError(mutex, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (mutex->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxMutexError(mutex, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Unlock the mutex owner\n  if (osRtxMutexOwnerUnlock(mutex)) {\n    osRtxThreadDispatch(NULL);\n  }\n\n  osRtxMutexDestroy(mutex);\n\n  return osOK;\n}\n\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_1(MutexNew,      osMutexId_t,  const osMutexAttr_t *)\nSVC0_1(MutexGetName,  const char *, osMutexId_t)\nSVC0_2(MutexAcquire,  osStatus_t,   osMutexId_t, uint32_t)\nSVC0_1(MutexRelease,  osStatus_t,   osMutexId_t)\nSVC0_1(MutexGetOwner, osThreadId_t, osMutexId_t)\nSVC0_1(MutexDelete,   osStatus_t,   osMutexId_t)\n//lint --flb \"Library End\"\n\n\n//  ==== Public API ====\n\n/// Create and Initialize a Mutex object.\nosMutexId_t osMutexNew (const osMutexAttr_t *attr) {\n  osMutexId_t mutex_id;\n\n  EvrRtxMutexNew(attr);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMutexError(NULL, (int32_t)osErrorISR);\n    mutex_id = NULL;\n  } else {\n    mutex_id = __svcMutexNew(attr);\n  }\n  return mutex_id;\n}\n\n/// Get name of a Mutex object.\nconst char *osMutexGetName (osMutexId_t mutex_id) {\n  const char *name;\n\n  if (IsException() || IsIrqMasked()) {\n    name = svcRtxMutexGetName(mutex_id);\n  } else {\n    name =  __svcMutexGetName(mutex_id);\n  }\n  return name;\n}\n\n/// Acquire a Mutex or timeout if it is locked.\nosStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {\n  osStatus_t status;\n\n  EvrRtxMutexAcquire(mutex_id, timeout);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMutexError(mutex_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcMutexAcquire(mutex_id, timeout);\n  }\n  return status;\n}\n\n/// Release a Mutex that was acquired by \\ref osMutexAcquire.\nosStatus_t osMutexRelease (osMutexId_t mutex_id) {\n  osStatus_t status;\n\n  EvrRtxMutexRelease(mutex_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMutexError(mutex_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcMutexRelease(mutex_id);\n  }\n  return status;\n}\n\n/// Get Thread which owns a Mutex object.\nosThreadId_t osMutexGetOwner (osMutexId_t mutex_id) {\n  osThreadId_t thread;\n\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMutexGetOwner(mutex_id, NULL);\n    thread = NULL;\n  } else {\n    thread = __svcMutexGetOwner(mutex_id);\n  }\n  return thread;\n}\n\n/// Delete a Mutex object.\nosStatus_t osMutexDelete (osMutexId_t mutex_id) {\n  osStatus_t status;\n\n  EvrRtxMutexDelete(mutex_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxMutexError(mutex_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcMutexDelete(mutex_id);\n  }\n  return status;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_semaphore.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Semaphore functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  OS Runtime Object Memory Usage\n#ifdef RTX_OBJ_MEM_USAGE\nosRtxObjectMemUsage_t osRtxSemaphoreMemUsage \\\n__attribute__((section(\".data.os.semaphore.obj\"))) =\n{ 0U, 0U, 0U };\n#endif\n\n\n//  ==== Helper functions ====\n\n/// Decrement Semaphore tokens.\n/// \\param[in]  semaphore       semaphore object.\n/// \\return 1 - success, 0 - failure.\nstatic uint32_t SemaphoreTokenDecrement (os_semaphore_t *semaphore) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask = __get_PRIMASK();\n#endif\n  uint32_t ret;\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  if (semaphore->tokens != 0U) {\n    semaphore->tokens--;\n    ret = 1U;\n  } else {\n    ret = 0U;\n  }\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  if (atomic_dec16_nz(&semaphore->tokens) != 0U) {\n    ret = 1U;\n  } else {\n    ret = 0U;\n  }\n#endif\n\n  return ret;\n}\n\n/// Increment Semaphore tokens.\n/// \\param[in]  semaphore       semaphore object.\n/// \\return 1 - success, 0 - failure.\nstatic uint32_t SemaphoreTokenIncrement (os_semaphore_t *semaphore) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask = __get_PRIMASK();\n#endif\n  uint32_t ret;\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  if (semaphore->tokens < semaphore->max_tokens) {\n    semaphore->tokens++;\n    ret = 1U;\n  } else {\n    ret = 0U;\n  }\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  if (atomic_inc16_lt(&semaphore->tokens, semaphore->max_tokens) < semaphore->max_tokens) {\n    ret = 1U;\n  } else {\n    ret = 0U;\n  }\n#endif\n\n  return ret;\n}\n\n/// Verify that Semaphore object pointer is valid.\n/// \\param[in]  semaphore       semaphore object.\n/// \\return true - valid, false - invalid.\nstatic bool_t IsSemaphorePtrValid (const os_semaphore_t *semaphore) {\n#ifdef RTX_OBJ_PTR_CHECK\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  uint32_t cb_start  = (uint32_t)&__os_semaphore_cb_start__;\n  uint32_t cb_length = (uint32_t)&__os_semaphore_cb_length__;\n\n  // Check the section boundaries\n  if (((uint32_t)semaphore - cb_start) >= cb_length) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n  // Check the object alignment\n  if ((((uint32_t)semaphore - cb_start) % sizeof(os_semaphore_t)) != 0U) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#else\n  // Check NULL pointer\n  if (semaphore == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#endif\n  return TRUE;\n}\n\n\n//  ==== Library functions ====\n\n/// Destroy a Semaphore object.\n/// \\param[in]  semaphore       semaphore object.\nstatic void osRtxSemaphoreDestroy (os_semaphore_t *semaphore) {\n\n  // Mark object as invalid\n  semaphore->id = osRtxIdInvalid;\n\n  // Free object memory\n  if ((semaphore->flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n    (void)osRtxMemoryPoolFree(osRtxInfo.mpi.semaphore, semaphore);\n#else\n    if (osRtxInfo.mpi.semaphore != NULL) {\n      (void)osRtxMemoryPoolFree(osRtxInfo.mpi.semaphore, semaphore);\n    } else {\n      (void)osRtxMemoryFree(osRtxInfo.mem.common, semaphore);\n    }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n    osRtxSemaphoreMemUsage.cnt_free++;\n#endif\n  }\n  EvrRtxSemaphoreDestroyed(semaphore);\n}\n\n#ifdef RTX_SAFETY_CLASS\n/// Delete a Semaphore safety class.\n/// \\param[in]  safety_class    safety class.\n/// \\param[in]  mode            safety mode.\nvoid osRtxSemaphoreDeleteClass (uint32_t safety_class, uint32_t mode) {\n  os_semaphore_t *semaphore;\n  os_thread_t    *thread;\n  uint32_t        length;\n\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  semaphore = (os_semaphore_t *)(uint32_t)&__os_semaphore_cb_start__;\n  length    =                   (uint32_t)&__os_semaphore_cb_length__;\n  while (length >= sizeof(os_semaphore_t)) {\n    if (   (semaphore->id == osRtxIdSemaphore) &&\n        ((((mode & osSafetyWithSameClass)  != 0U) &&\n          ((semaphore->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n         (((mode & osSafetyWithLowerClass) != 0U) &&\n          ((semaphore->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class)))) {\n      while (semaphore->thread_list != NULL) {\n        thread = osRtxThreadListGet(osRtxObject(semaphore));\n        osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);\n      }\n      osRtxSemaphoreDestroy(semaphore);\n    }\n    length -= sizeof(os_semaphore_t);\n    semaphore++;\n  }\n}\n#endif\n\n\n//  ==== Post ISR processing ====\n\n/// Semaphore post ISR processing.\n/// \\param[in]  semaphore       semaphore object.\nstatic void osRtxSemaphorePostProcess (os_semaphore_t *semaphore) {\n  os_thread_t *thread;\n\n  // Check if Thread is waiting for a token\n  if (semaphore->thread_list != NULL) {\n    // Try to acquire token\n    if (SemaphoreTokenDecrement(semaphore) != 0U) {\n      // Wakeup waiting Thread with highest Priority\n      thread = osRtxThreadListGet(osRtxObject(semaphore));\n      osRtxThreadWaitExit(thread, (uint32_t)osOK, FALSE);\n      EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens);\n    }\n  }\n}\n\n\n//  ==== Service Calls ====\n\n/// Create and Initialize a Semaphore object.\n/// \\note API identical to osSemaphoreNew\nstatic osSemaphoreId_t svcRtxSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {\n  os_semaphore_t    *semaphore;\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread = osRtxThreadGetRunning();\n  uint32_t           attr_bits;\n#endif\n  uint8_t            flags;\n  const char        *name;\n\n  // Check parameters\n  if ((max_count == 0U) || (max_count > osRtxSemaphoreTokenLimit) || (initial_count > max_count)) {\n    EvrRtxSemaphoreError(NULL, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  // Process attributes\n  if (attr != NULL) {\n    name      = attr->name;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = attr->attr_bits;\n#endif\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    semaphore = attr->cb_mem;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      if ((thread != NULL) &&\n          ((thread->attr >> osRtxAttrClass_Pos) <\n          (uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {\n        EvrRtxSemaphoreError(NULL, (int32_t)osErrorSafetyClass);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n#endif\n    if (semaphore != NULL) {\n      if (!IsSemaphorePtrValid(semaphore) || (attr->cb_size != sizeof(os_semaphore_t))) {\n        EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    } else {\n      if (attr->cb_size != 0U) {\n        EvrRtxSemaphoreError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n  } else {\n    name      = NULL;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = 0U;\n#endif\n    semaphore = NULL;\n  }\n\n  // Allocate object memory if not provided\n  if (semaphore == NULL) {\n    if (osRtxInfo.mpi.semaphore != NULL) {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      semaphore = osRtxMemoryPoolAlloc(osRtxInfo.mpi.semaphore);\n#ifndef RTX_OBJ_PTR_CHECK\n    } else {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      semaphore = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_semaphore_t), 1U);\n#endif\n    }\n#ifdef RTX_OBJ_MEM_USAGE\n    if (semaphore != NULL) {\n      uint32_t used;\n      osRtxSemaphoreMemUsage.cnt_alloc++;\n      used = osRtxSemaphoreMemUsage.cnt_alloc - osRtxSemaphoreMemUsage.cnt_free;\n      if (osRtxSemaphoreMemUsage.max_used < used) {\n        osRtxSemaphoreMemUsage.max_used = used;\n      }\n    }\n#endif\n    flags = osRtxFlagSystemObject;\n  } else {\n    flags = 0U;\n  }\n\n  if (semaphore != NULL) {\n    // Initialize control block\n    semaphore->id          = osRtxIdSemaphore;\n    semaphore->flags       = flags;\n    semaphore->attr        = 0U;\n    semaphore->name        = name;\n    semaphore->thread_list = NULL;\n    semaphore->tokens      = (uint16_t)initial_count;\n    semaphore->max_tokens  = (uint16_t)max_count;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      semaphore->attr     |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>\n                                       (osSafetyClass_Pos - osRtxAttrClass_Pos));\n    } else {\n      // Inherit safety class from the running thread\n      if (thread != NULL) {\n        semaphore->attr   |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);\n      }\n    }\n#endif\n\n    // Register post ISR processing function\n    osRtxInfo.post_process.semaphore = osRtxSemaphorePostProcess;\n\n    EvrRtxSemaphoreCreated(semaphore, semaphore->name);\n  } else {\n    EvrRtxSemaphoreError(NULL,(int32_t)osErrorNoMemory);\n  }\n\n  return semaphore;\n}\n\n/// Get name of a Semaphore object.\n/// \\note API identical to osSemaphoreGetName\nstatic const char *svcRtxSemaphoreGetName (osSemaphoreId_t semaphore_id) {\n  os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);\n\n  // Check parameters\n  if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {\n    EvrRtxSemaphoreGetName(semaphore, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  EvrRtxSemaphoreGetName(semaphore, semaphore->name);\n\n  return semaphore->name;\n}\n\n/// Acquire a Semaphore token or timeout if no tokens are available.\n/// \\note API identical to osSemaphoreAcquire\nstatic osStatus_t svcRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {\n  os_semaphore_t    *semaphore = osRtxSemaphoreId(semaphore_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread;\n#endif\n  osStatus_t         status;\n\n  // Check parameters\n  if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {\n    EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (semaphore->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxSemaphoreError(semaphore, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Try to acquire token\n  if (SemaphoreTokenDecrement(semaphore) != 0U) {\n    EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens);\n    status = osOK;\n  } else {\n    // No token available\n    if (timeout != 0U) {\n      EvrRtxSemaphoreAcquirePending(semaphore, timeout);\n      // Suspend current Thread\n      if (osRtxThreadWaitEnter(osRtxThreadWaitingSemaphore, timeout)) {\n        osRtxThreadListPut(osRtxObject(semaphore), osRtxThreadGetRunning());\n      } else {\n        EvrRtxSemaphoreAcquireTimeout(semaphore);\n      }\n      status = osErrorTimeout;\n    } else {\n      EvrRtxSemaphoreNotAcquired(semaphore);\n      status = osErrorResource;\n    }\n  }\n\n  return status;\n}\n\n/// Release a Semaphore token that was acquired by osSemaphoreAcquire.\n/// \\note API identical to osSemaphoreRelease\nstatic osStatus_t svcRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {\n  os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);\n  os_thread_t    *thread;\n  osStatus_t      status;\n\n  // Check parameters\n  if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {\n    EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (semaphore->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxSemaphoreError(semaphore, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check if Thread is waiting for a token\n  if (semaphore->thread_list != NULL) {\n    EvrRtxSemaphoreReleased(semaphore, semaphore->tokens);\n    // Wakeup waiting Thread with highest Priority\n    thread = osRtxThreadListGet(osRtxObject(semaphore));\n    osRtxThreadWaitExit(thread, (uint32_t)osOK, TRUE);\n    EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens);\n    status = osOK;\n  } else {\n    // Try to release token\n    if (SemaphoreTokenIncrement(semaphore) != 0U) {\n      EvrRtxSemaphoreReleased(semaphore, semaphore->tokens);\n      status = osOK;\n    } else {\n      EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit);\n      status = osErrorResource;\n    }\n  }\n\n  return status;\n}\n\n/// Get current Semaphore token count.\n/// \\note API identical to osSemaphoreGetCount\nstatic uint32_t svcRtxSemaphoreGetCount (osSemaphoreId_t semaphore_id) {\n  os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);\n\n  // Check parameters\n  if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {\n    EvrRtxSemaphoreGetCount(semaphore, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxSemaphoreGetCount(semaphore, semaphore->tokens);\n\n  return semaphore->tokens;\n}\n\n/// Delete a Semaphore object.\n/// \\note API identical to osSemaphoreDelete\nstatic osStatus_t svcRtxSemaphoreDelete (osSemaphoreId_t semaphore_id) {\n  os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);\n  os_thread_t    *thread;\n\n  // Check parameters\n  if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {\n    EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (semaphore->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxSemaphoreError(semaphore, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Unblock waiting threads\n  if (semaphore->thread_list != NULL) {\n    do {\n      thread = osRtxThreadListGet(osRtxObject(semaphore));\n      osRtxThreadWaitExit(thread, (uint32_t)osErrorResource, FALSE);\n    } while (semaphore->thread_list != NULL);\n    osRtxThreadDispatch(NULL);\n  }\n\n  osRtxSemaphoreDestroy(semaphore);\n\n  return osOK;\n}\n\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_3(SemaphoreNew,      osSemaphoreId_t, uint32_t, uint32_t, const osSemaphoreAttr_t *)\nSVC0_1(SemaphoreGetName,  const char *,    osSemaphoreId_t)\nSVC0_2(SemaphoreAcquire,  osStatus_t,      osSemaphoreId_t, uint32_t)\nSVC0_1(SemaphoreRelease,  osStatus_t,      osSemaphoreId_t)\nSVC0_1(SemaphoreGetCount, uint32_t,        osSemaphoreId_t)\nSVC0_1(SemaphoreDelete,   osStatus_t,      osSemaphoreId_t)\n//lint --flb \"Library End\"\n\n\n//  ==== ISR Calls ====\n\n/// Acquire a Semaphore token or timeout if no tokens are available.\n/// \\note API identical to osSemaphoreAcquire\n__STATIC_INLINE\nosStatus_t isrRtxSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {\n  os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);\n  osStatus_t      status;\n\n  // Check parameters\n  if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore) || (timeout != 0U)) {\n    EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Try to acquire token\n  if (SemaphoreTokenDecrement(semaphore) != 0U) {\n    EvrRtxSemaphoreAcquired(semaphore, semaphore->tokens);\n    status = osOK;\n  } else {\n    // No token available\n    EvrRtxSemaphoreNotAcquired(semaphore);\n    status = osErrorResource;\n  }\n\n  return status;\n}\n\n/// Release a Semaphore token that was acquired by osSemaphoreAcquire.\n/// \\note API identical to osSemaphoreRelease\n__STATIC_INLINE\nosStatus_t isrRtxSemaphoreRelease (osSemaphoreId_t semaphore_id) {\n  os_semaphore_t *semaphore = osRtxSemaphoreId(semaphore_id);\n  osStatus_t      status;\n\n  // Check parameters\n  if (!IsSemaphorePtrValid(semaphore) || (semaphore->id != osRtxIdSemaphore)) {\n    EvrRtxSemaphoreError(semaphore, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Try to release token\n  if (SemaphoreTokenIncrement(semaphore) != 0U) {\n    // Register post ISR processing\n    osRtxPostProcess(osRtxObject(semaphore));\n    EvrRtxSemaphoreReleased(semaphore, semaphore->tokens);\n    status = osOK;\n  } else {\n    EvrRtxSemaphoreError(semaphore, osRtxErrorSemaphoreCountLimit);\n    status = osErrorResource;\n  }\n\n  return status;\n}\n\n\n//  ==== Public API ====\n\n/// Create and Initialize a Semaphore object.\nosSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {\n  osSemaphoreId_t semaphore_id;\n\n  EvrRtxSemaphoreNew(max_count, initial_count, attr);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxSemaphoreError(NULL, (int32_t)osErrorISR);\n    semaphore_id = NULL;\n  } else {\n    semaphore_id = __svcSemaphoreNew(max_count, initial_count, attr);\n  }\n  return semaphore_id;\n}\n\n/// Get name of a Semaphore object.\nconst char *osSemaphoreGetName (osSemaphoreId_t semaphore_id) {\n  const char *name;\n\n  if (IsException() || IsIrqMasked()) {\n    name = svcRtxSemaphoreGetName(semaphore_id);\n  } else {\n    name =  __svcSemaphoreGetName(semaphore_id);\n  }\n  return name;\n}\n\n/// Acquire a Semaphore token or timeout if no tokens are available.\nosStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {\n  osStatus_t status;\n\n  EvrRtxSemaphoreAcquire(semaphore_id, timeout);\n  if (IsException() || IsIrqMasked()) {\n    status = isrRtxSemaphoreAcquire(semaphore_id, timeout);\n  } else {\n    status =  __svcSemaphoreAcquire(semaphore_id, timeout);\n  }\n  return status;\n}\n\n/// Release a Semaphore token that was acquired by osSemaphoreAcquire.\nosStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {\n  osStatus_t status;\n\n  EvrRtxSemaphoreRelease(semaphore_id);\n  if (IsException() || IsIrqMasked()) {\n    status = isrRtxSemaphoreRelease(semaphore_id);\n  } else {\n    status =  __svcSemaphoreRelease(semaphore_id);\n  }\n  return status;\n}\n\n/// Get current Semaphore token count.\nuint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) {\n  uint32_t count;\n\n  if (IsException() || IsIrqMasked()) {\n    count = svcRtxSemaphoreGetCount(semaphore_id);\n  } else {\n    count =  __svcSemaphoreGetCount(semaphore_id);\n  }\n  return count;\n}\n\n/// Delete a Semaphore object.\nosStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) {\n  osStatus_t status;\n\n  EvrRtxSemaphoreDelete(semaphore_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxSemaphoreError(semaphore_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcSemaphoreDelete(semaphore_id);\n  }\n  return status;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_system.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       System functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  ==== Helper functions ====\n\n/// Put Object into ISR Queue.\n/// \\param[in]  object          object.\n/// \\return 1 - success, 0 - failure.\nstatic uint32_t isr_queue_put (os_object_t *object) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask = __get_PRIMASK();\n#else\n  uint32_t n;\n#endif\n  uint16_t max;\n  uint32_t ret;\n\n  max = osRtxInfo.isr_queue.max;\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  if (osRtxInfo.isr_queue.cnt < max) {\n    osRtxInfo.isr_queue.cnt++;\n    osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.in] = object;\n    if (++osRtxInfo.isr_queue.in == max) {\n      osRtxInfo.isr_queue.in = 0U;\n    }\n    ret = 1U;\n  } else {\n    ret = 0U;\n  }\n  \n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  if (atomic_inc16_lt(&osRtxInfo.isr_queue.cnt, max) < max) {\n    n = atomic_inc16_lim(&osRtxInfo.isr_queue.in, max);\n    osRtxInfo.isr_queue.data[n] = object;\n    ret = 1U;\n  } else {\n    ret = 0U;\n  }\n#endif\n\n  return ret;\n}\n\n/// Get Object from ISR Queue.\n/// \\return object or NULL.\nstatic os_object_t *isr_queue_get (void) {\n#if (EXCLUSIVE_ACCESS != 0)\n  uint32_t     n;\n#endif\n  uint16_t     max;\n  os_object_t *ret;\n\n  max = osRtxInfo.isr_queue.max;\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  if (osRtxInfo.isr_queue.cnt != 0U) {\n    osRtxInfo.isr_queue.cnt--;\n    ret = osRtxObject(osRtxInfo.isr_queue.data[osRtxInfo.isr_queue.out]);\n    if (++osRtxInfo.isr_queue.out == max) {\n      osRtxInfo.isr_queue.out = 0U;\n    }\n  } else {\n    ret = NULL;\n  }\n\n  __enable_irq();\n#else\n  if (atomic_dec16_nz(&osRtxInfo.isr_queue.cnt) != 0U) {\n    n = atomic_inc16_lim(&osRtxInfo.isr_queue.out, max);\n    ret = osRtxObject(osRtxInfo.isr_queue.data[n]);\n  } else {\n    ret = NULL;\n  }\n#endif\n\n  return ret;\n}\n\n\n//  ==== Library Functions ====\n\n/// Tick Handler.\n//lint -esym(714,osRtxTick_Handler) \"Referenced by Exception handlers\"\n//lint -esym(759,osRtxTick_Handler) \"Prototype in header\"\n//lint -esym(765,osRtxTick_Handler) \"Global scope\"\nvoid osRtxTick_Handler (void) {\n  os_thread_t *thread;\n\n  OS_Tick_AcknowledgeIRQ();\n  osRtxInfo.kernel.tick++;\n\n  // Process Thread Delays\n  osRtxThreadDelayTick();\n\n  osRtxThreadDispatch(NULL);\n\n  // Process Timers\n  if (osRtxInfo.timer.tick != NULL) {\n    osRtxInfo.timer.tick();\n  }\n\n#ifdef RTX_THREAD_WATCHDOG\n  // Process Watchdog Timers\n  osRtxThreadWatchdogTick();\n#endif\n\n  // Check Round Robin timeout\n  if (osRtxInfo.thread.robin.timeout != 0U) {\n    thread = osRtxInfo.thread.run.next;\n    if (thread != osRtxInfo.thread.robin.thread) {\n      osRtxInfo.thread.robin.thread = thread;\n      if (thread->delay == 0U) {\n        // Reset Round Robin\n        thread->delay = osRtxInfo.thread.robin.timeout;\n      }\n    }\n    if (thread->delay != 0U) {\n      thread->delay--;\n    }\n    if (thread->delay == 0U) {\n      // Round Robin Timeout\n      if (osRtxKernelGetState() == osRtxKernelRunning) {\n        thread = osRtxInfo.thread.ready.thread_list;\n        if ((thread != NULL) && (thread->priority == osRtxInfo.thread.robin.thread->priority)) {\n          osRtxThreadListRemove(thread);\n          osRtxThreadReadyPut(osRtxInfo.thread.robin.thread);\n          EvrRtxThreadPreempted(osRtxInfo.thread.robin.thread);\n          osRtxThreadSwitch(thread);\n          osRtxInfo.thread.robin.thread = thread;\n          thread->delay = osRtxInfo.thread.robin.timeout;\n        }\n      }\n    }\n  }\n}\n\n/// Pending Service Call Handler.\n//lint -esym(714,osRtxPendSV_Handler) \"Referenced by Exception handlers\"\n//lint -esym(759,osRtxPendSV_Handler) \"Prototype in header\"\n//lint -esym(765,osRtxPendSV_Handler) \"Global scope\"\nvoid osRtxPendSV_Handler (void) {\n  os_object_t *object;\n\n  for (;;) {\n    object = isr_queue_get();\n    if (object == NULL) {\n      break;\n    }\n    switch (object->id) {\n      case osRtxIdThread:\n        osRtxInfo.post_process.thread(osRtxThreadObject(object));\n        break;\n      case osRtxIdEventFlags:\n        osRtxInfo.post_process.event_flags(osRtxEventFlagsObject(object));\n        break;\n      case osRtxIdSemaphore:\n        osRtxInfo.post_process.semaphore(osRtxSemaphoreObject(object));\n        break;\n      case osRtxIdMemoryPool:\n        osRtxInfo.post_process.memory_pool(osRtxMemoryPoolObject(object));\n        break;\n      case osRtxIdMessage:\n        osRtxInfo.post_process.message(osRtxMessageObject(object));\n        break;\n      default:\n        // Should never come here\n        break;\n    }\n  }\n\n  osRtxThreadDispatch(NULL);\n}\n\n/// Register post ISR processing.\n/// \\param[in]  object          generic object.\nvoid osRtxPostProcess (os_object_t *object) {\n\n  if (isr_queue_put(object) != 0U) {\n    if (osRtxInfo.kernel.blocked == 0U) {\n      SetPendSV();\n    } else {\n      osRtxInfo.kernel.pendSV = 1U;\n    }\n  } else {\n    (void)osRtxKernelErrorNotify(osRtxErrorISRQueueOverflow, object);\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_thread.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Thread functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  OS Runtime Object Memory Usage\n#ifdef RTX_OBJ_MEM_USAGE\nosRtxObjectMemUsage_t osRtxThreadMemUsage \\\n__attribute__((section(\".data.os.thread.obj\"))) =\n{ 0U, 0U, 0U };\n#endif\n\n//  Runtime Class/Zone assignment table\n#if defined(RTX_EXECUTION_ZONE) && defined(RTX_SAFETY_CLASS)\nstatic uint8_t ThreadClassTable[64] __attribute__((section(\".data.os\"))) = { 0U };\n#endif\n\n// Watchdog Alarm Flag\n#if defined(RTX_THREAD_WATCHDOG) && defined(RTX_EXECUTION_ZONE)\nstatic uint8_t WatchdogAlarmFlag __attribute__((section(\".data.os\"))) = 0U;\n#endif\n\n\n//  ==== Helper functions ====\n\n/// Set Thread Flags.\n/// \\param[in]  thread          thread object.\n/// \\param[in]  flags           specifies the flags to set.\n/// \\return thread flags after setting.\nstatic uint32_t ThreadFlagsSet (os_thread_t *thread, uint32_t flags) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask = __get_PRIMASK();\n#endif\n  uint32_t thread_flags;\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  thread->thread_flags |= flags;\n  thread_flags = thread->thread_flags;\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  thread_flags = atomic_set32(&thread->thread_flags, flags);\n#endif\n\n  return thread_flags;\n}\n\n/// Clear Thread Flags.\n/// \\param[in]  thread          thread object.\n/// \\param[in]  flags           specifies the flags to clear.\n/// \\return thread flags before clearing.\nstatic uint32_t ThreadFlagsClear (os_thread_t *thread, uint32_t flags) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask = __get_PRIMASK();\n#endif\n  uint32_t thread_flags;\n\n#if (EXCLUSIVE_ACCESS == 0)\n  __disable_irq();\n\n  thread_flags = thread->thread_flags;\n  thread->thread_flags &= ~flags;\n\n  if (primask == 0U) {\n    __enable_irq();\n  }\n#else\n  thread_flags = atomic_clr32(&thread->thread_flags, flags);\n#endif\n\n  return thread_flags;\n}\n\n/// Check Thread Flags.\n/// \\param[in]  thread          thread object.\n/// \\param[in]  flags           specifies the flags to check.\n/// \\param[in]  options         specifies flags options (osFlagsXxxx).\n/// \\return thread flags before clearing or 0 if specified flags have not been set.\nstatic uint32_t ThreadFlagsCheck (os_thread_t *thread, uint32_t flags, uint32_t options) {\n#if (EXCLUSIVE_ACCESS == 0)\n  uint32_t primask;\n#endif\n  uint32_t thread_flags;\n\n  if ((options & osFlagsNoClear) == 0U) {\n#if (EXCLUSIVE_ACCESS == 0)\n    primask = __get_PRIMASK();\n    __disable_irq();\n\n    thread_flags = thread->thread_flags;\n    if ((((options & osFlagsWaitAll) != 0U) && ((thread_flags & flags) != flags)) ||\n        (((options & osFlagsWaitAll) == 0U) && ((thread_flags & flags) == 0U))) {\n      thread_flags = 0U;\n    } else {\n      thread->thread_flags &= ~flags;\n    }\n\n    if (primask == 0U) {\n      __enable_irq();\n    }\n#else\n    if ((options & osFlagsWaitAll) != 0U) {\n      thread_flags = atomic_chk32_all(&thread->thread_flags, flags);\n    } else {\n      thread_flags = atomic_chk32_any(&thread->thread_flags, flags);\n    }\n#endif\n  } else {\n    thread_flags = thread->thread_flags;\n    if ((((options & osFlagsWaitAll) != 0U) && ((thread_flags & flags) != flags)) ||\n        (((options & osFlagsWaitAll) == 0U) && ((thread_flags & flags) == 0U))) {\n      thread_flags = 0U;\n    }\n  }\n\n  return thread_flags;\n}\n\n/// Verify that Thread object pointer is valid.\n/// \\param[in]  thread          thread object.\n/// \\return true - valid, false - invalid.\nstatic bool_t IsThreadPtrValid (const os_thread_t *thread) {\n#ifdef RTX_OBJ_PTR_CHECK\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  uint32_t cb_start  = (uint32_t)&__os_thread_cb_start__;\n  uint32_t cb_length = (uint32_t)&__os_thread_cb_length__;\n\n  // Check the section boundaries\n  if (((uint32_t)thread - cb_start) >= cb_length) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n  // Check the object alignment\n  if ((((uint32_t)thread - cb_start) % sizeof(os_thread_t)) != 0U) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#else\n  // Check NULL pointer\n  if (thread == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#endif\n  return TRUE;\n}\n\n#if defined(RTX_EXECUTION_ZONE) && defined(RTX_SAFETY_CLASS)\n/// Check if Thread Zone to Safety Class mapping is valid.\n/// \\param[in]  attr_bits       thread attributes.\n/// \\param[in]  thread          running thread.\n/// \\return true - valid, false - not valid.\nstatic bool_t IsClassMappingValid (uint32_t attr_bits, const os_thread_t *thread) {\n  uint32_t safety_class;\n  uint32_t zone;\n\n  if ((attr_bits & osThreadZone_Valid) != 0U) {\n    zone = (attr_bits & osThreadZone_Msk) >> osThreadZone_Pos;\n  } else if (thread != NULL) {\n    zone = thread->zone;\n  } else {\n    zone = 0U;\n  }\n\n  if ((attr_bits & osSafetyClass_Valid) != 0U) {\n    safety_class = (attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos;\n  } else if (thread != NULL) {\n    safety_class = (uint32_t)thread->attr >> osRtxAttrClass_Pos;\n  } else {\n    safety_class = 0U;\n  }\n\n  // Check if zone is free or assigned to class\n  if ((ThreadClassTable[zone] == 0U) ||\n      (ThreadClassTable[zone] == (0x80U | safety_class))) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return TRUE;\n  }\n  // Invalid class to zone mapping\n  return FALSE;\n}\n#endif\n\n\n//  ==== Library functions ====\n\n/// Put a Thread into specified Object list sorted by Priority (Highest at Head).\n/// \\param[in]  object          generic object.\n/// \\param[in]  thread          thread object.\nvoid osRtxThreadListPut (os_object_t *object, os_thread_t *thread) {\n  os_thread_t *prev, *next;\n  int32_t      priority;\n\n  priority = thread->priority;\n\n  prev = osRtxThreadObject(object);\n  next = prev->thread_next;\n  while ((next != NULL) && (next->priority >= priority)) {\n    prev = next;\n    next = next->thread_next;\n  }\n  thread->thread_prev = prev;\n  thread->thread_next = next;\n  prev->thread_next = thread;\n  if (next != NULL) {\n    next->thread_prev = thread;\n  }\n}\n\n/// Get a Thread with Highest Priority from specified Object list and remove it.\n/// \\param[in]  object          generic object.\n/// \\return thread object.\nos_thread_t *osRtxThreadListGet (os_object_t *object) {\n  os_thread_t *thread;\n\n  thread = object->thread_list;\n  object->thread_list = thread->thread_next;\n  if (thread->thread_next != NULL) {\n    thread->thread_next->thread_prev = osRtxThreadObject(object);\n  }\n  thread->thread_prev = NULL;\n\n  return thread;\n}\n\n/// Retrieve Thread list root object.\n/// \\param[in]  thread          thread object.\n/// \\return root object.\nstatic void *osRtxThreadListRoot (os_thread_t *thread) {\n  os_thread_t *thread0;\n\n  thread0 = thread;\n  while (thread0->id == osRtxIdThread) {\n    thread0 = thread0->thread_prev;\n  }\n  return thread0;\n}\n\n/// Re-sort a Thread in linked Object list by Priority (Highest at Head).\n/// \\param[in]  thread          thread object.\nvoid osRtxThreadListSort (os_thread_t *thread) {\n  os_object_t *object;\n  os_thread_t *thread0;\n\n  // Search for object\n  thread0 = thread;\n  while ((thread0 != NULL) && (thread0->id == osRtxIdThread)) {\n    thread0 = thread0->thread_prev;\n  }\n  object = osRtxObject(thread0);\n\n  if (object != NULL) {\n    osRtxThreadListRemove(thread);\n    osRtxThreadListPut(object, thread);\n  }\n}\n\n/// Remove a Thread from linked Object list.\n/// \\param[in]  thread          thread object.\nvoid osRtxThreadListRemove (os_thread_t *thread) {\n\n  if (thread->thread_prev != NULL) {\n    thread->thread_prev->thread_next = thread->thread_next;\n    if (thread->thread_next != NULL) {\n      thread->thread_next->thread_prev = thread->thread_prev;\n    }\n    thread->thread_prev = NULL;\n  }\n}\n\n/// Unlink a Thread from specified linked list.\n/// \\param[in]  thread          thread object.\nstatic void osRtxThreadListUnlink (os_thread_t **thread_list, os_thread_t *thread) {\n\n  if (thread->thread_next != NULL) {\n    thread->thread_next->thread_prev = thread->thread_prev;\n  }\n  if (thread->thread_prev != NULL) {\n    thread->thread_prev->thread_next = thread->thread_next;\n    thread->thread_prev = NULL;\n  } else {\n    *thread_list = thread->thread_next;\n  }\n}\n\n/// Mark a Thread as Ready and put it into Ready list (sorted by Priority).\n/// \\param[in]  thread          thread object.\nvoid osRtxThreadReadyPut (os_thread_t *thread) {\n\n  thread->state = osRtxThreadReady;\n  osRtxThreadListPut(&osRtxInfo.thread.ready, thread);\n}\n\n/// Insert a Thread into the Delay list sorted by Delay (Lowest at Head).\n/// \\param[in]  thread          thread object.\n/// \\param[in]  delay           delay value.\nstatic void osRtxThreadDelayInsert (os_thread_t *thread, uint32_t delay) {\n  os_thread_t *prev, *next;\n\n  if (delay == osWaitForever) {\n    prev = NULL;\n    next = osRtxInfo.thread.wait_list;\n    while (next != NULL)  {\n      prev = next;\n      next = next->delay_next;\n    }\n    thread->delay = delay;\n    thread->delay_prev = prev;\n    thread->delay_next = NULL;\n    if (prev != NULL) {\n      prev->delay_next = thread;\n    } else {\n      osRtxInfo.thread.wait_list = thread;\n    }\n  } else {\n    prev = NULL;\n    next = osRtxInfo.thread.delay_list;\n    while ((next != NULL) && (next->delay <= delay)) {\n      delay -= next->delay;\n      prev = next;\n      next = next->delay_next;\n    }\n    thread->delay = delay;\n    thread->delay_prev = prev;\n    thread->delay_next = next;\n    if (prev != NULL) {\n      prev->delay_next = thread;\n    } else {\n      osRtxInfo.thread.delay_list = thread;\n    }\n    if (next != NULL) {\n      next->delay -= delay;\n      next->delay_prev = thread;\n    }\n  }\n}\n\n/// Remove a Thread from the Delay list.\n/// \\param[in]  thread          thread object.\nvoid osRtxThreadDelayRemove (os_thread_t *thread) {\n\n  if (thread->delay == osWaitForever) {\n    if (thread->delay_next != NULL) {\n      thread->delay_next->delay_prev = thread->delay_prev;\n    }\n    if (thread->delay_prev != NULL) {\n      thread->delay_prev->delay_next = thread->delay_next;\n      thread->delay_prev = NULL;\n    } else {\n      osRtxInfo.thread.wait_list = thread->delay_next;\n    }\n  } else {\n    if (thread->delay_next != NULL) {\n      thread->delay_next->delay += thread->delay;\n      thread->delay_next->delay_prev = thread->delay_prev;\n    }\n    if (thread->delay_prev != NULL) {\n      thread->delay_prev->delay_next = thread->delay_next;\n      thread->delay_prev = NULL;\n    } else {\n      osRtxInfo.thread.delay_list = thread->delay_next;\n    }\n  }\n  thread->delay = 0U;\n}\n\n/// Process Thread Delay Tick (executed each System Tick).\nvoid osRtxThreadDelayTick (void) {\n  os_thread_t *thread;\n  os_object_t *object;\n\n  thread = osRtxInfo.thread.delay_list;\n  if (thread == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return;\n  }\n\n  thread->delay--;\n\n  if (thread->delay == 0U) {\n    do {\n      switch (thread->state) {\n        case osRtxThreadWaitingDelay:\n          EvrRtxDelayCompleted(thread);\n          break;\n        case osRtxThreadWaitingThreadFlags:\n          EvrRtxThreadFlagsWaitTimeout(thread);\n          break;\n        case osRtxThreadWaitingEventFlags:\n          EvrRtxEventFlagsWaitTimeout((osEventFlagsId_t)osRtxThreadListRoot(thread));\n          break;\n        case osRtxThreadWaitingMutex:\n          object = osRtxObject(osRtxThreadListRoot(thread));\n          osRtxMutexOwnerRestore(osRtxMutexObject(object), thread);\n          EvrRtxMutexAcquireTimeout(osRtxMutexObject(object));\n          break;\n        case osRtxThreadWaitingSemaphore:\n          EvrRtxSemaphoreAcquireTimeout((osSemaphoreId_t)osRtxThreadListRoot(thread));\n          break;\n        case osRtxThreadWaitingMemoryPool:\n          EvrRtxMemoryPoolAllocTimeout((osMemoryPoolId_t)osRtxThreadListRoot(thread));\n          break;\n        case osRtxThreadWaitingMessageGet:\n          EvrRtxMessageQueueGetTimeout((osMessageQueueId_t)osRtxThreadListRoot(thread));\n          break;\n        case osRtxThreadWaitingMessagePut:\n          EvrRtxMessageQueuePutTimeout((osMessageQueueId_t)osRtxThreadListRoot(thread));\n          break;\n        default:\n          // Invalid\n          break;\n      }\n      EvrRtxThreadUnblocked(thread, (osRtxThreadRegPtr(thread))[0]);\n      osRtxThreadListRemove(thread);\n      osRtxThreadReadyPut(thread);\n      thread = thread->delay_next;\n    } while ((thread != NULL) && (thread->delay == 0U));\n    if (thread != NULL) {\n      thread->delay_prev = NULL;\n    }\n    osRtxInfo.thread.delay_list = thread;\n  }\n}\n\n/// Get pointer to Thread registers (R0..R3)\n/// \\param[in]  thread          thread object.\n/// \\return pointer to registers R0-R3.\nuint32_t *osRtxThreadRegPtr (const os_thread_t *thread) {\n  uint32_t addr = thread->sp + StackOffsetR0(thread->stack_frame);\n  //lint -e{923} -e{9078} \"cast from unsigned int to pointer\"\n  return ((uint32_t *)addr);\n}\n\n/// Block running Thread execution and register it as Ready to Run.\n/// \\param[in]  thread          running thread object.\nstatic void osRtxThreadBlock (os_thread_t *thread) {\n  os_thread_t *prev, *next;\n  int32_t      priority;\n\n  thread->state = osRtxThreadReady;\n\n  priority = thread->priority;\n\n  prev = osRtxThreadObject(&osRtxInfo.thread.ready);\n  next = prev->thread_next;\n\n  while ((next != NULL) && (next->priority > priority)) {\n    prev = next;\n    next = next->thread_next;\n  }\n  thread->thread_prev = prev;\n  thread->thread_next = next;\n  prev->thread_next = thread;\n  if (next != NULL) {\n    next->thread_prev = thread;\n  }\n\n  EvrRtxThreadPreempted(thread);\n}\n\n/// Switch to specified Thread.\n/// \\param[in]  thread          thread object.\nvoid osRtxThreadSwitch (os_thread_t *thread) {\n\n  thread->state = osRtxThreadRunning;\n  SetPrivileged((bool_t)((thread->attr & osThreadPrivileged) != 0U));\n  osRtxInfo.thread.run.next = thread;\n  EvrRtxThreadSwitched(thread);\n}\n\n/// Dispatch specified Thread or Ready Thread with Highest Priority.\n/// \\param[in]  thread          thread object or NULL.\nvoid osRtxThreadDispatch (os_thread_t *thread) {\n  uint8_t      kernel_state;\n  os_thread_t *thread_running;\n  os_thread_t *thread_ready;\n\n  kernel_state   = osRtxKernelGetState();\n  thread_running = osRtxThreadGetRunning();\n\n  if (thread == NULL) {\n    thread_ready = osRtxInfo.thread.ready.thread_list;\n    if ((kernel_state == osRtxKernelRunning) &&\n        (thread_ready != NULL) &&\n        (thread_ready->priority > thread_running->priority)) {\n      // Preempt running Thread\n      osRtxThreadListRemove(thread_ready);\n      osRtxThreadBlock(thread_running);\n      osRtxThreadSwitch(thread_ready);\n    }\n  } else {\n    if ((kernel_state == osRtxKernelRunning) &&\n        (thread->priority > thread_running->priority)) {\n      // Preempt running Thread\n      osRtxThreadBlock(thread_running);\n      osRtxThreadSwitch(thread);\n    } else {\n      // Put Thread into Ready list\n      osRtxThreadReadyPut(thread);\n    }\n  }\n}\n\n/// Exit Thread wait state.\n/// \\param[in]  thread          thread object.\n/// \\param[in]  ret_val         return value.\n/// \\param[in]  dispatch        dispatch flag.\nvoid osRtxThreadWaitExit (os_thread_t *thread, uint32_t ret_val, bool_t dispatch) {\n  uint32_t *reg;\n\n  EvrRtxThreadUnblocked(thread, ret_val);\n\n  reg = osRtxThreadRegPtr(thread);\n  reg[0] = ret_val;\n\n  osRtxThreadDelayRemove(thread);\n  if (dispatch) {\n    osRtxThreadDispatch(thread);\n  } else {\n    osRtxThreadReadyPut(thread);\n  }\n}\n\n/// Enter Thread wait state.\n/// \\param[in]  state           new thread state.\n/// \\param[in]  timeout         timeout.\n/// \\return true - success, false - failure.\nbool_t osRtxThreadWaitEnter (uint8_t state, uint32_t timeout) {\n  os_thread_t *thread;\n\n  // Check if Kernel is running\n  if (osRtxKernelGetState() != osRtxKernelRunning) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n\n  // Check if any thread is ready\n  if (osRtxInfo.thread.ready.thread_list == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n\n  // Get running thread\n  thread = osRtxThreadGetRunning();\n\n  EvrRtxThreadBlocked(thread, timeout);\n\n  thread->state = state;\n  osRtxThreadDelayInsert(thread, timeout);\n  thread = osRtxThreadListGet(&osRtxInfo.thread.ready);\n  osRtxThreadSwitch(thread);\n\n  return TRUE;\n}\n\n#ifdef RTX_STACK_CHECK\n/// Check current running Thread Stack.\n/// \\param[in]  thread          running thread.\n/// \\return true - success, false - failure.\n//lint -esym(714,osRtxThreadStackCheck) \"Referenced by Exception handlers\"\n//lint -esym(759,osRtxThreadStackCheck) \"Prototype in header\"\n//lint -esym(765,osRtxThreadStackCheck) \"Global scope\"\nbool_t osRtxThreadStackCheck (const os_thread_t *thread) {\n\n  //lint -e{923} \"cast from pointer to unsigned int\"\n  //lint -e{9079} -e{9087} \"cast between pointers to different object types\"\n  if ((thread->sp <= (uint32_t)thread->stack_mem) ||\n      (*((uint32_t *)thread->stack_mem) != osRtxStackMagicWord)) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n  return TRUE;\n}\n#endif\n\n#ifdef RTX_THREAD_WATCHDOG\n\n/// Insert a Thread into the Watchdog list, sorted by tick (lowest at Head).\n/// \\param[in]  thread          thread object.\n/// \\param[in]  ticks           watchdog timeout.\nstatic void osRtxThreadWatchdogInsert (os_thread_t *thread, uint32_t ticks) {\n  os_thread_t *prev, *next;\n\n  if (ticks == 0U) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return;\n  }\n  prev = NULL;\n  next = osRtxInfo.thread.wdog_list;\n  while ((next != NULL) && ((next->wdog_tick <= ticks))) {\n    ticks -= next->wdog_tick;\n    prev   = next;\n    next   = next->wdog_next;\n  }\n  thread->wdog_tick = ticks;\n  thread->wdog_next = next;\n  if (next != NULL) {\n    next->wdog_tick -= ticks;\n  }\n  if (prev != NULL) {\n    prev->wdog_next = thread;\n  } else {\n    osRtxInfo.thread.wdog_list = thread;\n  }\n}\n\n/// Remove a Thread from the Watchdog list.\n/// \\param[in]  thread          thread object.\nvoid osRtxThreadWatchdogRemove (const os_thread_t *thread) {\n  os_thread_t *prev, *next;\n\n  prev = NULL;\n  next = osRtxInfo.thread.wdog_list;\n  while ((next != NULL) && (next != thread)) {\n    prev = next;\n    next = next->wdog_next;\n  }\n  if (next == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return;\n  }\n  if (thread->wdog_next != NULL) {\n    thread->wdog_next->wdog_tick += thread->wdog_tick;\n  }\n  if (prev != NULL) {\n    prev->wdog_next = thread->wdog_next;\n  } else {\n    osRtxInfo.thread.wdog_list = thread->wdog_next;\n  }\n}\n\n/// Process Watchdog Tick (executed each System Tick).\nvoid osRtxThreadWatchdogTick (void) {\n  os_thread_t *thread_running;\n  os_thread_t *thread;\n#ifdef RTX_SAFETY_CLASS\n  os_thread_t *next;\n#endif\n  uint32_t ticks;\n\n  thread = osRtxInfo.thread.wdog_list;\n  if (thread == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return;\n  }\n  thread->wdog_tick--;\n\n  if (thread->wdog_tick == 0U) {\n    // Call watchdog handler for all expired threads\n    thread_running = osRtxThreadGetRunning();\n    do {\n      osRtxThreadSetRunning(osRtxInfo.thread.run.next);\n#ifdef RTX_SAFETY_CLASS\n      // First the highest safety thread (sorted by Safety Class)\n      next = thread->wdog_next;\n      while ((next != NULL) && (next->wdog_tick == 0U)) {\n        if ((next->attr & osRtxAttrClass_Msk) > (thread->attr & osRtxAttrClass_Msk)) {\n          thread = next;\n        }\n        next = next->wdog_next;\n      }\n#endif\n      osRtxThreadWatchdogRemove(thread);\n      EvrRtxThreadWatchdogExpired(thread);\n#ifdef RTX_EXECUTION_ZONE\n      WatchdogAlarmFlag = 1U;\n#endif\n      ticks = osWatchdogAlarm_Handler(thread);\n#ifdef RTX_EXECUTION_ZONE\n      WatchdogAlarmFlag = 0U;\n#endif\n      osRtxThreadWatchdogInsert(thread, ticks);\n      thread = osRtxInfo.thread.wdog_list;\n    } while ((thread != NULL) && (thread->wdog_tick == 0U));\n    osRtxThreadSetRunning(thread_running);\n  }\n}\n\n#endif\n\nstatic __NO_RETURN void osThreadEntry (void *argument, osThreadFunc_t func) {\n  func(argument);\n  osThreadExit();\n}\n\n\n//  ==== Post ISR processing ====\n\n/// Thread post ISR processing.\n/// \\param[in]  thread          thread object.\nstatic void osRtxThreadPostProcess (os_thread_t *thread) {\n  uint32_t thread_flags;\n\n  // Check if Thread is waiting for Thread Flags\n  if (thread->state == osRtxThreadWaitingThreadFlags) {\n    thread_flags = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options);\n    if (thread_flags != 0U) {\n      osRtxThreadWaitExit(thread, thread_flags, FALSE);\n      EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags, thread);\n    }\n  }\n}\n\n\n//  ==== Service Calls ====\n\n/// Create a thread and add it to Active Threads.\n/// \\note API identical to osThreadNew\nstatic osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {\n  os_thread_t       *thread;\n#if defined(RTX_SAFETY_CLASS) || defined(RTX_EXECUTION_ZONE)\n  const os_thread_t *thread_running = osRtxThreadGetRunning();\n#endif\n  uint32_t           attr_bits;\n  void              *stack_mem;\n  uint32_t           stack_size;\n  osPriority_t       priority;\n  uint8_t            flags;\n  const char        *name;\n  uint32_t          *ptr;\n  uint32_t           n;\n#ifdef RTX_TZ_CONTEXT\n  TZ_ModuleId_t      tz_module;\n  TZ_MemoryId_t      tz_memory;\n#endif\n\n  // Check parameters\n  if (func == NULL) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  // Process attributes\n  if (attr != NULL) {\n    name       = attr->name;\n    attr_bits  = attr->attr_bits;\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    thread     = attr->cb_mem;\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    stack_mem  = attr->stack_mem;\n    stack_size = attr->stack_size;\n    priority   = attr->priority;\n#ifdef RTX_TZ_CONTEXT\n    tz_module  = attr->tz_module;\n#endif\n    if (((attr_bits & osThreadPrivileged) != 0U) && ((attr_bits & osThreadUnprivileged) != 0U)) {\n      EvrRtxThreadError(NULL, (int32_t)osErrorParameter);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return NULL;\n    }\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      if ((thread_running != NULL) &&\n          ((thread_running->attr >> osRtxAttrClass_Pos) <\n          (uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {\n        EvrRtxThreadError(NULL, (int32_t)osErrorSafetyClass);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n#endif\n    if (thread != NULL) {\n      if (!IsThreadPtrValid(thread) || (attr->cb_size != sizeof(os_thread_t))) {\n        EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    } else {\n      if (attr->cb_size != 0U) {\n        EvrRtxThreadError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n    if (stack_mem != NULL) {\n      //lint -e{923} \"cast from pointer to unsigned int\" [MISRA Note 7]\n      if ((((uint32_t)stack_mem & 7U) != 0U) || (stack_size == 0U)) {\n        EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n    if (priority == osPriorityNone) {\n      priority = osPriorityNormal;\n    } else {\n      if ((priority < osPriorityIdle) || (priority > osPriorityISR)) {\n        EvrRtxThreadError(NULL, osRtxErrorInvalidPriority);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n  } else {\n    name       = NULL;\n    attr_bits  = 0U;\n    thread     = NULL;\n    stack_mem  = NULL;\n    stack_size = 0U;\n    priority   = osPriorityNormal;\n#ifdef RTX_TZ_CONTEXT\n    tz_module  = 0U;\n#endif\n  }\n\n  // Set default privilege if not specified\n  if ((attr_bits & (osThreadPrivileged | osThreadUnprivileged)) == 0U) {\n    if ((osRtxConfig.flags & osRtxConfigPrivilegedMode) != 0U) {\n      attr_bits |= osThreadPrivileged;\n    } else {\n      attr_bits |= osThreadUnprivileged;\n    }\n  }\n\n#ifdef RTX_SAFETY_FEATURES\n  // Check privilege protection\n  if ((attr_bits & osThreadPrivileged) != 0U) {\n    if ((osRtxInfo.kernel.protect & osRtxKernelProtectPrivileged) != 0U) {\n      EvrRtxThreadError(NULL, osRtxErrorInvalidPrivilegedMode);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return NULL;\n    }\n  }\n#endif\n\n#if defined(RTX_EXECUTION_ZONE) && defined(RTX_SAFETY_CLASS)\n  // Check class to zone mapping\n  if (!IsClassMappingValid(attr_bits, thread_running)) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n#endif\n\n  // Check stack size\n  if (stack_size != 0U) {\n    if (((stack_size & 7U) != 0U) || (stack_size < (64U + 8U)) || (stack_size > 0x7FFFFFFFU)) {\n      EvrRtxThreadError(NULL, osRtxErrorInvalidThreadStack);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return NULL;\n    }\n  }\n\n  // Allocate object memory if not provided\n  if (thread == NULL) {\n    if (osRtxInfo.mpi.thread != NULL) {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      thread = osRtxMemoryPoolAlloc(osRtxInfo.mpi.thread);\n#ifndef RTX_OBJ_PTR_CHECK\n    } else {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      thread = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_thread_t), 1U);\n#endif\n    }\n#ifdef RTX_OBJ_MEM_USAGE\n    if (thread != NULL) {\n      uint32_t used;\n      osRtxThreadMemUsage.cnt_alloc++;\n      used = osRtxThreadMemUsage.cnt_alloc - osRtxThreadMemUsage.cnt_free;\n      if (osRtxThreadMemUsage.max_used < used) {\n        osRtxThreadMemUsage.max_used = used;\n      }\n    }\n#endif\n    flags = osRtxFlagSystemObject;\n  } else {\n    flags = 0U;\n  }\n\n  // Allocate stack memory if not provided\n  if ((thread != NULL) && (stack_mem == NULL)) {\n    if (stack_size == 0U) {\n      stack_size = osRtxConfig.thread_stack_size;\n      if (osRtxInfo.mpi.stack != NULL) {\n        //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n        stack_mem = osRtxMemoryPoolAlloc(osRtxInfo.mpi.stack);\n        if (stack_mem != NULL) {\n          flags |= osRtxThreadFlagDefStack;\n        }\n      } else {\n        //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n        stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U);\n      }\n    } else {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      stack_mem = osRtxMemoryAlloc(osRtxInfo.mem.stack, stack_size, 0U);\n    }\n    if (stack_mem == NULL) {\n      if ((flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n        (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);\n#else\n        if (osRtxInfo.mpi.thread != NULL) {\n          (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);\n        } else {\n          (void)osRtxMemoryFree(osRtxInfo.mem.common, thread);\n        }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n        osRtxThreadMemUsage.cnt_free++;\n#endif\n      }\n      thread = NULL;\n    }\n    flags |= osRtxFlagSystemMemory;\n  }\n\n#ifdef RTX_TZ_CONTEXT\n  // Allocate secure process stack\n  if ((thread != NULL) && (tz_module != 0U)) {\n    tz_memory = TZ_AllocModuleContext_S(tz_module);\n    if (tz_memory == 0U) {\n      EvrRtxThreadError(NULL, osRtxErrorTZ_AllocContext_S);\n      if ((flags & osRtxFlagSystemMemory) != 0U) {\n        if ((flags & osRtxThreadFlagDefStack) != 0U) {\n          (void)osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem);\n        } else {\n          (void)osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem);\n        }\n      }\n      if ((flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n        (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);\n#else\n        if (osRtxInfo.mpi.thread != NULL) {\n          (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);\n        } else {\n          (void)osRtxMemoryFree(osRtxInfo.mem.common, thread);\n        }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n        osRtxThreadMemUsage.cnt_free++;\n#endif\n      }\n      thread = NULL;\n    }\n  } else {\n    tz_memory = 0U;\n  }\n#endif\n\n  if (thread != NULL) {\n    // Initialize control block\n    //lint --e{923}  --e{9078} \"cast between pointers and unsigned int\"\n    //lint --e{9079} --e{9087} \"cast between pointers to different object types\"\n    //lint --e{9074} \"conversion between a pointer to function and another type\"\n    thread->id            = osRtxIdThread;\n    thread->state         = osRtxThreadReady;\n    thread->flags         = flags;\n    thread->attr          = (uint8_t)(attr_bits & ~osRtxAttrClass_Msk);\n    thread->name          = name;\n    thread->thread_next   = NULL;\n    thread->thread_prev   = NULL;\n    thread->delay_next    = NULL;\n    thread->delay_prev    = NULL;\n    thread->thread_join   = NULL;\n    thread->delay         = 0U;\n    thread->priority      = (int8_t)priority;\n    thread->priority_base = (int8_t)priority;\n    thread->stack_frame   = STACK_FRAME_INIT_VAL;\n    thread->flags_options = 0U;\n    thread->wait_flags    = 0U;\n    thread->thread_flags  = 0U;\n    thread->mutex_list    = NULL;\n    thread->stack_mem     = stack_mem;\n    thread->stack_size    = stack_size;\n    thread->sp            = (uint32_t)stack_mem + stack_size - 64U;\n    thread->thread_addr   = (uint32_t)func;\n  #ifdef RTX_TZ_CONTEXT\n    thread->tz_memory     = tz_memory;\n  #endif\n  #ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      thread->attr       |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>\n                                      (osSafetyClass_Pos - osRtxAttrClass_Pos));\n    } else {\n      // Inherit safety class from the running thread\n      if (thread_running != NULL) {\n        thread->attr     |= (uint8_t)(thread_running->attr & osRtxAttrClass_Msk);\n      }\n    }\n  #endif\n  #ifdef RTX_EXECUTION_ZONE\n    if ((attr_bits & osThreadZone_Valid) != 0U) {\n      thread->zone        = (uint8_t)((attr_bits & osThreadZone_Msk) >> osThreadZone_Pos);\n    } else {\n      // Inherit zone from the running thread\n      if (thread_running != NULL) {\n        thread->zone      = thread_running->zone;\n      } else {\n        thread->zone      = 0U;\n      }\n    }\n  #endif\n  #if defined(RTX_EXECUTION_ZONE) && defined(RTX_SAFETY_CLASS)\n    // Update class to zone assignment table\n    if (ThreadClassTable[thread->zone] == 0U) {\n      ThreadClassTable[thread->zone] = (uint8_t)(0x80U | (thread->attr >> osRtxAttrClass_Pos));\n    }\n  #endif\n  #ifdef RTX_THREAD_WATCHDOG\n    thread->wdog_next     = NULL;\n    thread->wdog_tick     = 0U;\n  #endif\n\n    // Initialize stack\n    //lint --e{613} false detection: \"Possible use of null pointer\"\n    ptr = (uint32_t *)stack_mem;\n    ptr[0] = osRtxStackMagicWord;\n    if ((osRtxConfig.flags & osRtxConfigStackWatermark) != 0U) {\n      for (n = (stack_size/4U) - (16U + 1U); n != 0U; n--) {\n         ptr++;\n        *ptr = osRtxStackFillPattern;\n      }\n    }\n    ptr = (uint32_t *)thread->sp;\n    for (n = 0U; n != 14U; n++) {\n      ptr[n] = 0U;                      // R4..R11, R0..R3, R12, LR\n    }\n    ptr[14] = (uint32_t)osThreadEntry;  // PC\n    ptr[15] = xPSR_InitVal(\n                (bool_t)((attr_bits & osThreadPrivileged) != 0U),\n                (bool_t)(((uint32_t)func & 1U) != 0U)\n              );                        // xPSR\n    ptr[8]  = (uint32_t)argument;       // R0\n    ptr[9]  = (uint32_t)func;           // R1\n\n    // Register post ISR processing function\n    osRtxInfo.post_process.thread = osRtxThreadPostProcess;\n\n    EvrRtxThreadCreated(thread, thread->thread_addr, thread->name);\n  } else {\n    EvrRtxThreadError(NULL, (int32_t)osErrorNoMemory);\n  }\n\n  if (thread != NULL) {\n    osRtxThreadDispatch(thread);\n  }\n\n  return thread;\n}\n\n/// Get name of a thread.\n/// \\note API identical to osThreadGetName\nstatic const char *svcRtxThreadGetName (osThreadId_t thread_id) {\n  os_thread_t *thread = osRtxThreadId(thread_id);\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadGetName(thread, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  EvrRtxThreadGetName(thread, thread->name);\n\n  return thread->name;\n}\n\n#ifdef RTX_SAFETY_CLASS\n/// Get safety class of a thread.\n/// \\note API identical to osThreadGetClass\nstatic uint32_t svcRtxThreadGetClass (osThreadId_t thread_id) {\n  os_thread_t *thread = osRtxThreadId(thread_id);\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadGetClass(thread, osErrorId);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorId;\n  }\n\n  EvrRtxThreadGetClass(thread, (uint32_t)thread->attr >> osRtxAttrClass_Pos);\n\n  return ((uint32_t)thread->attr >> osRtxAttrClass_Pos);\n}\n#endif\n\n#ifdef RTX_EXECUTION_ZONE\n/// Get zone of a thread.\n/// \\note API identical to osThreadGetZone\nstatic uint32_t svcRtxThreadGetZone (osThreadId_t thread_id) {\n  os_thread_t *thread = osRtxThreadId(thread_id);\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadGetZone(thread, osErrorId);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorId;\n  }\n\n  EvrRtxThreadGetZone(thread, thread->zone);\n\n  return thread->zone;\n}\n#endif\n\n/// Return the thread ID of the current running thread.\n/// \\note API identical to osThreadGetId\nstatic osThreadId_t svcRtxThreadGetId (void) {\n  os_thread_t *thread;\n\n  thread = osRtxThreadGetRunning();\n  EvrRtxThreadGetId(thread);\n  return thread;\n}\n\n/// Get current thread state of a thread.\n/// \\note API identical to osThreadGetState\nstatic osThreadState_t svcRtxThreadGetState (osThreadId_t thread_id) {\n  os_thread_t    *thread = osRtxThreadId(thread_id);\n  osThreadState_t state;\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadGetState(thread, osThreadError);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osThreadError;\n  }\n\n  state = osRtxThreadState(thread);\n\n  EvrRtxThreadGetState(thread, state);\n\n  return state;\n}\n\n/// Get stack size of a thread.\n/// \\note API identical to osThreadGetStackSize\nstatic uint32_t svcRtxThreadGetStackSize (osThreadId_t thread_id) {\n  os_thread_t *thread = osRtxThreadId(thread_id);\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadGetStackSize(thread, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxThreadGetStackSize(thread, thread->stack_size);\n\n  return thread->stack_size;\n}\n\n/// Get available stack space of a thread based on stack watermark recording during execution.\n/// \\note API identical to osThreadGetStackSpace\nstatic uint32_t svcRtxThreadGetStackSpace (osThreadId_t thread_id) {\n  os_thread_t    *thread = osRtxThreadId(thread_id);\n  const uint32_t *stack;\n        uint32_t  space;\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadGetStackSpace(thread, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  // Check if stack watermark is not enabled\n  if ((osRtxConfig.flags & osRtxConfigStackWatermark) == 0U) {\n    EvrRtxThreadGetStackSpace(thread, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  //lint -e{9079} \"conversion from pointer to void to pointer to other type\"\n  stack = thread->stack_mem;\n  if (*stack++ == osRtxStackMagicWord) {\n    for (space = 4U; space < thread->stack_size; space += 4U) {\n      if (*stack++ != osRtxStackFillPattern) {\n        break;\n      }\n    }\n  } else {\n    space = 0U;\n  }\n\n  EvrRtxThreadGetStackSpace(thread, space);\n\n  return space;\n}\n\n/// Change priority of a thread.\n/// \\note API identical to osThreadSetPriority\nstatic osStatus_t svcRtxThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {\n  os_thread_t       *thread = osRtxThreadId(thread_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread_running;\n#endif\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread) ||\n      (priority < osPriorityIdle) || (priority > osPriorityISR)) {\n    EvrRtxThreadError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread_running = osRtxThreadGetRunning();\n  if ((thread_running != NULL) &&\n      ((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check object state\n  if (thread->state == osRtxThreadTerminated) {\n    EvrRtxThreadError(thread, (int32_t)osErrorResource);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorResource;\n  }\n\n  if (thread->priority   != (int8_t)priority) {\n    thread->priority      = (int8_t)priority;\n    thread->priority_base = (int8_t)priority;\n    EvrRtxThreadPriorityUpdated(thread, priority);\n    osRtxThreadListSort(thread);\n    osRtxThreadDispatch(NULL);\n  }\n\n  return osOK;\n}\n\n/// Get current priority of a thread.\n/// \\note API identical to osThreadGetPriority\nstatic osPriority_t svcRtxThreadGetPriority (osThreadId_t thread_id) {\n  os_thread_t *thread = osRtxThreadId(thread_id);\n  osPriority_t priority;\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadGetPriority(thread, osPriorityError);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osPriorityError;\n  }\n\n  // Check object state\n  if (thread->state == osRtxThreadTerminated) {\n    EvrRtxThreadGetPriority(thread, osPriorityError);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osPriorityError;\n  }\n\n  priority = osRtxThreadPriority(thread);\n\n  EvrRtxThreadGetPriority(thread, priority);\n\n  return priority;\n}\n\n/// Pass control to next thread that is in state READY.\n/// \\note API identical to osThreadYield\nstatic osStatus_t svcRtxThreadYield (void) {\n  os_thread_t *thread_running;\n  os_thread_t *thread_ready;\n\n  if (osRtxKernelGetState() == osRtxKernelRunning) {\n    thread_running = osRtxThreadGetRunning();\n    thread_ready   = osRtxInfo.thread.ready.thread_list;\n    if ((thread_ready != NULL) &&\n        (thread_ready->priority == thread_running->priority)) {\n      osRtxThreadListRemove(thread_ready);\n      osRtxThreadReadyPut(thread_running);\n      EvrRtxThreadPreempted(thread_running);\n      osRtxThreadSwitch(thread_ready);\n    }\n  }\n\n  return osOK;\n}\n\n/// Suspend execution of a thread.\n/// \\note API identical to osThreadSuspend\nstatic osStatus_t svcRtxThreadSuspend (osThreadId_t thread_id) {\n  os_thread_t       *thread = osRtxThreadId(thread_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread_running;\n#endif\n  osStatus_t         status;\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread_running = osRtxThreadGetRunning();\n  if ((thread_running != NULL) &&\n      ((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check object state\n  switch (thread->state & osRtxThreadStateMask) {\n    case osRtxThreadRunning:\n      if ((osRtxKernelGetState() != osRtxKernelRunning) ||\n          (osRtxInfo.thread.ready.thread_list == NULL)) {\n        EvrRtxThreadError(thread, (int32_t)osErrorResource);\n        status = osErrorResource;\n      } else {\n        status = osOK;\n      }\n      break;\n    case osRtxThreadReady:\n      osRtxThreadListRemove(thread);\n      status = osOK;\n      break;\n    case osRtxThreadBlocked:\n      osRtxThreadListRemove(thread);\n      osRtxThreadDelayRemove(thread);\n      status = osOK;\n      break;\n    case osRtxThreadInactive:\n    case osRtxThreadTerminated:\n    default:\n      EvrRtxThreadError(thread, (int32_t)osErrorResource);\n      status = osErrorResource;\n      break;\n  }\n\n  if (status == osOK) {\n    EvrRtxThreadSuspended(thread);\n\n    if (thread->state == osRtxThreadRunning) {\n      osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));\n    }\n\n    // Update Thread State and put it into Delay list\n    thread->state = osRtxThreadBlocked;\n    osRtxThreadDelayInsert(thread, osWaitForever);\n  }\n\n  return status;\n}\n\n/// Resume execution of a thread.\n/// \\note API identical to osThreadResume\nstatic osStatus_t svcRtxThreadResume (osThreadId_t thread_id) {\n  os_thread_t       *thread = osRtxThreadId(thread_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread_running;\n#endif\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread_running = osRtxThreadGetRunning();\n  if ((thread_running != NULL) &&\n      ((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check object state\n  if ((thread->state & osRtxThreadStateMask) != osRtxThreadBlocked) {\n    EvrRtxThreadError(thread, (int32_t)osErrorResource);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorResource;\n  }\n\n  EvrRtxThreadResumed(thread);\n\n  // Wakeup Thread\n  osRtxThreadListRemove(thread);\n  osRtxThreadDelayRemove(thread);\n  osRtxThreadDispatch(thread);\n\n  return osOK;\n}\n\n/// Wakeup a thread waiting to join.\n/// \\param[in]  thread          thread object.\nvoid osRtxThreadJoinWakeup (const os_thread_t *thread) {\n\n  if (thread->thread_join != NULL) {\n    osRtxThreadWaitExit(thread->thread_join, (uint32_t)osOK, FALSE);\n    EvrRtxThreadJoined(thread->thread_join);\n  }\n  if (thread->state == osRtxThreadWaitingJoin) {\n    thread->thread_next->thread_join = NULL;\n  }\n}\n\n/// Free Thread resources.\n/// \\param[in]  thread          thread object.\nstatic void osRtxThreadFree (os_thread_t *thread) {\n\n  osRtxThreadBeforeFree(thread);\n\n  // Mark object as inactive and invalid\n  thread->state = osRtxThreadInactive;\n  thread->id    = osRtxIdInvalid;\n\n#ifdef RTX_TZ_CONTEXT\n  // Free secure process stack\n  if (thread->tz_memory != 0U) {\n    (void)TZ_FreeModuleContext_S(thread->tz_memory);\n  }\n#endif\n\n  // Free stack memory\n  if ((thread->flags & osRtxFlagSystemMemory) != 0U) {\n    if ((thread->flags & osRtxThreadFlagDefStack) != 0U) {\n      (void)osRtxMemoryPoolFree(osRtxInfo.mpi.stack, thread->stack_mem);\n    } else {\n      (void)osRtxMemoryFree(osRtxInfo.mem.stack, thread->stack_mem);\n    }\n  }\n\n  // Free object memory\n  if ((thread->flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n    (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);\n#else\n    if (osRtxInfo.mpi.thread != NULL) {\n      (void)osRtxMemoryPoolFree(osRtxInfo.mpi.thread, thread);\n    } else {\n      (void)osRtxMemoryFree(osRtxInfo.mem.common, thread);\n    }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n    osRtxThreadMemUsage.cnt_free++;\n#endif\n  }\n}\n\n/// Destroy a Thread.\n/// \\param[in]  thread          thread object.\nvoid osRtxThreadDestroy (os_thread_t *thread) {\n\n  if ((thread->attr & osThreadJoinable) == 0U) {\n    osRtxThreadFree(thread);\n  } else {\n    // Update Thread State and put it into Terminate Thread list\n    thread->state = osRtxThreadTerminated;\n    thread->thread_prev = NULL;\n    thread->thread_next = osRtxInfo.thread.terminate_list;\n    if (osRtxInfo.thread.terminate_list != NULL) {\n      osRtxInfo.thread.terminate_list->thread_prev = thread;\n    }\n    osRtxInfo.thread.terminate_list = thread;\n  }\n  EvrRtxThreadDestroyed(thread);\n}\n\n/// Detach a thread (thread storage can be reclaimed when thread terminates).\n/// \\note API identical to osThreadDetach\nstatic osStatus_t svcRtxThreadDetach (osThreadId_t thread_id) {\n  os_thread_t       *thread = osRtxThreadId(thread_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread_running;\n#endif\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread_running = osRtxThreadGetRunning();\n  if ((thread_running != NULL) &&\n      ((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check object attributes\n  if ((thread->attr & osThreadJoinable) == 0U) {\n    EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorResource;\n  }\n\n  if (thread->state == osRtxThreadTerminated) {\n    osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread);\n    osRtxThreadFree(thread);\n  } else {\n    thread->attr &= ~osThreadJoinable;\n  }\n\n  EvrRtxThreadDetached(thread);\n\n  return osOK;\n}\n\n/// Wait for specified thread to terminate.\n/// \\note API identical to osThreadJoin\nstatic osStatus_t svcRtxThreadJoin (osThreadId_t thread_id) {\n  os_thread_t *thread = osRtxThreadId(thread_id);\n  os_thread_t *thread_running;\n  osStatus_t   status;\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread_running = osRtxThreadGetRunning();\n  if ((thread_running != NULL) &&\n      ((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check object attributes\n  if ((thread->attr & osThreadJoinable) == 0U) {\n    EvrRtxThreadError(thread, osRtxErrorThreadNotJoinable);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorResource;\n  }\n\n  // Check object state\n  if (thread->state == osRtxThreadRunning) {\n    EvrRtxThreadError(thread, (int32_t)osErrorResource);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorResource;\n  }\n\n  if (thread->state == osRtxThreadTerminated) {\n    osRtxThreadListUnlink(&osRtxInfo.thread.terminate_list, thread);\n    osRtxThreadFree(thread);\n    EvrRtxThreadJoined(thread);\n    status = osOK;\n  } else {\n    // Suspend current Thread\n    if (osRtxThreadWaitEnter(osRtxThreadWaitingJoin, osWaitForever)) {\n      thread_running = osRtxThreadGetRunning();\n      thread_running->thread_next = thread;\n      thread->thread_join = thread_running;\n      thread->attr &= ~osThreadJoinable;\n      EvrRtxThreadJoinPending(thread);\n    } else {\n      EvrRtxThreadError(thread, (int32_t)osErrorResource);\n    }\n    status = osErrorResource;\n  }\n\n  return status;\n}\n\n/// Terminate execution of current running thread.\n/// \\note API identical to osThreadExit\nstatic void svcRtxThreadExit (void) {\n  os_thread_t *thread;\n\n  // Check if switch to next Ready Thread is possible\n  if ((osRtxKernelGetState() != osRtxKernelRunning) ||\n      (osRtxInfo.thread.ready.thread_list == NULL)) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return;\n  }\n\n  // Get running thread\n  thread = osRtxThreadGetRunning();\n\n#ifdef RTX_THREAD_WATCHDOG\n  // Remove Thread from the Watchdog list\n  osRtxThreadWatchdogRemove(thread);\n#endif\n\n  // Release owned Mutexes\n  osRtxMutexOwnerRelease(thread->mutex_list);\n\n  // Wakeup Thread waiting to Join\n  osRtxThreadJoinWakeup(thread);\n\n  // Switch to next Ready Thread\n  osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));\n\n  // Update Stack Pointer\n  thread->sp = __get_PSP();\n#ifdef RTX_STACK_CHECK\n  // Check Stack usage\n  if (!osRtxThreadStackCheck(thread)) {\n    osRtxThreadSetRunning(osRtxInfo.thread.run.next);\n    (void)osRtxKernelErrorNotify(osRtxErrorStackOverflow, thread);\n  }\n#endif\n\n  // Mark running thread as deleted\n  osRtxThreadSetRunning(NULL);\n\n  // Destroy Thread\n  osRtxThreadDestroy(thread);\n}\n\n/// Terminate execution of a thread.\n/// \\note API identical to osThreadTerminate\nstatic osStatus_t svcRtxThreadTerminate (osThreadId_t thread_id) {\n  os_thread_t       *thread = osRtxThreadId(thread_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread_running;\n#endif\n  osStatus_t         status;\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread)) {\n    EvrRtxThreadError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread_running = osRtxThreadGetRunning();\n  if ((thread_running != NULL) &&\n      ((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxThreadError(thread, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check object state\n  switch (thread->state & osRtxThreadStateMask) {\n    case osRtxThreadRunning:\n      if ((osRtxKernelGetState() != osRtxKernelRunning) ||\n          (osRtxInfo.thread.ready.thread_list == NULL)) {\n        EvrRtxThreadError(thread, (int32_t)osErrorResource);\n        status = osErrorResource;\n      } else {\n        status = osOK;\n      }\n      break;\n    case osRtxThreadReady:\n      osRtxThreadListRemove(thread);\n      status = osOK;\n      break;\n    case osRtxThreadBlocked:\n      osRtxThreadListRemove(thread);\n      osRtxThreadDelayRemove(thread);\n      status = osOK;\n      break;\n    case osRtxThreadInactive:\n    case osRtxThreadTerminated:\n    default:\n      EvrRtxThreadError(thread, (int32_t)osErrorResource);\n      status = osErrorResource;\n      break;\n  }\n\n  if (status == osOK) {\n#ifdef RTX_THREAD_WATCHDOG\n    // Remove Thread from the Watchdog list\n    osRtxThreadWatchdogRemove(thread);\n#endif\n\n    // Release owned Mutexes\n    osRtxMutexOwnerRelease(thread->mutex_list);\n\n    // Wakeup Thread waiting to Join\n    osRtxThreadJoinWakeup(thread);\n\n    // Switch to next Ready Thread when terminating running Thread\n    if (thread->state == osRtxThreadRunning) {\n      osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));\n      // Update Stack Pointer\n      thread->sp = __get_PSP();\n#ifdef RTX_STACK_CHECK\n      // Check Stack usage\n      if (!osRtxThreadStackCheck(thread)) {\n        osRtxThreadSetRunning(osRtxInfo.thread.run.next);\n        (void)osRtxKernelErrorNotify(osRtxErrorStackOverflow, thread);\n      }\n#endif\n      // Mark running thread as deleted\n      osRtxThreadSetRunning(NULL);\n    } else {\n      osRtxThreadDispatch(NULL);\n    }\n\n    // Destroy Thread\n    osRtxThreadDestroy(thread);\n  }\n\n  return status;\n}\n\n#ifdef RTX_THREAD_WATCHDOG\n/// Feed watchdog of the current running thread.\n/// \\note API identical to osThreadFeedWatchdog\nstatic osStatus_t svcRtxThreadFeedWatchdog (uint32_t ticks) {\n  os_thread_t *thread;\n\n  // Check running thread\n  thread = osRtxThreadGetRunning();\n  if (thread == NULL) {\n    EvrRtxThreadError(NULL, osRtxErrorKernelNotRunning);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osError;\n  }\n\n  osRtxThreadWatchdogRemove(thread);\n  osRtxThreadWatchdogInsert(thread, ticks);\n\n  EvrRtxThreadFeedWatchdogDone();\n\n  return osOK;\n}\n#endif\n\n#ifdef RTX_SAFETY_FEATURES\n/// Protect the creation of privileged threads.\n/// \\note API identical to osThreadProtectPrivileged\nstatic osStatus_t svcRtxThreadProtectPrivileged (void) {\n\n  // Check that Kernel is initialized\n  if (osRtxKernelGetState() == osRtxKernelInactive) {\n    EvrRtxThreadError(NULL, osRtxErrorKernelNotReady);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osError;\n  }\n\n  osRtxInfo.kernel.protect |= osRtxKernelProtectPrivileged;\n\n  EvrRtxThreadPrivilegedProtected();\n\n  return osOK;\n}\n#endif\n\n#ifdef RTX_SAFETY_CLASS\n\n/// Suspend execution of threads for specified safety classes.\n/// \\note API identical to osThreadSuspendClass\nstatic osStatus_t svcRtxThreadSuspendClass (uint32_t safety_class, uint32_t mode) {\n  os_thread_t *thread;\n  os_thread_t *thread_next;\n\n  // Check parameters\n  if (safety_class > 0x0FU) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Check running thread safety class (when called from thread)\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) && IsSVCallIrq()) {\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         (((thread->attr >> osRtxAttrClass_Pos) + 1U) < (uint8_t)safety_class))) {\n      EvrRtxThreadError(NULL, (int32_t)osErrorSafetyClass);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return osErrorSafetyClass;\n    }\n  }\n\n  // Threads in Wait List\n  thread = osRtxInfo.thread.wait_list;\n  while (thread != NULL) {\n    thread_next = thread->delay_next;\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class))) {\n      osRtxThreadListRemove(thread);\n      thread->state = osRtxThreadBlocked;\n      EvrRtxThreadSuspended(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Threads in Delay List\n  thread = osRtxInfo.thread.delay_list;\n  while (thread != NULL) {\n    thread_next = thread->delay_next;\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class))) {\n      osRtxThreadListRemove(thread);\n      osRtxThreadDelayRemove(thread);\n      thread->state = osRtxThreadBlocked;\n      osRtxThreadDelayInsert(thread, osWaitForever);\n      EvrRtxThreadSuspended(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Threads in Ready List\n  thread = osRtxInfo.thread.ready.thread_list;\n  while (thread != NULL) {\n    thread_next = thread->thread_next;\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class))) {\n      osRtxThreadListRemove(thread);\n      thread->state = osRtxThreadBlocked;\n      osRtxThreadDelayInsert(thread, osWaitForever);\n      EvrRtxThreadSuspended(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Running Thread\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((((mode & osSafetyWithSameClass)  != 0U) &&\n        ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n       (((mode & osSafetyWithLowerClass) != 0U) &&\n        ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class)))) {\n    if ((osRtxKernelGetState() == osRtxKernelRunning) &&\n        (osRtxInfo.thread.ready.thread_list != NULL)) {\n      thread->state = osRtxThreadBlocked;\n      osRtxThreadDelayInsert(thread, osWaitForever);\n      EvrRtxThreadSuspended(thread);\n      osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));\n    } else {\n      EvrRtxThreadError(thread, (int32_t)osErrorResource);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return osErrorResource;\n    }\n  }\n\n  return osOK;\n}\n\n/// Resume execution of threads for specified safety classes.\n/// \\note API identical to osThreadResumeClass\nstatic osStatus_t svcRtxThreadResumeClass (uint32_t safety_class, uint32_t mode) {\n  os_thread_t *thread;\n  os_thread_t *thread_next;\n\n  // Check parameters\n  if (safety_class > 0x0FU) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Check running thread safety class (when called from thread)\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) && IsSVCallIrq()) {\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) < (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         (((thread->attr >> osRtxAttrClass_Pos) + 1U) < (uint8_t)safety_class))) {\n      EvrRtxThreadError(NULL, (int32_t)osErrorSafetyClass);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return osErrorSafetyClass;\n    }\n  }\n\n  // Threads in Wait List\n  thread = osRtxInfo.thread.wait_list;\n  while (thread != NULL) {\n    thread_next = thread->delay_next;\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class))) {\n      // Wakeup Thread\n      osRtxThreadListRemove(thread);\n      osRtxThreadDelayRemove(thread);\n      osRtxThreadReadyPut(thread);\n      EvrRtxThreadResumed(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Threads in Delay List\n  thread = osRtxInfo.thread.delay_list;\n  while (thread != NULL) {\n    thread_next = thread->delay_next;\n    if ((((mode & osSafetyWithSameClass)  != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n        (((mode & osSafetyWithLowerClass) != 0U) &&\n         ((thread->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class))) {\n      // Wakeup Thread\n      osRtxThreadListRemove(thread);\n      osRtxThreadDelayRemove(thread);\n      osRtxThreadReadyPut(thread);\n      EvrRtxThreadResumed(thread);\n    }\n    thread = thread_next;\n  }\n\n  osRtxThreadDispatch(NULL);\n\n  return osOK;\n}\n\n#endif\n\n#ifdef RTX_EXECUTION_ZONE\n/// Terminate execution of threads assigned to a specified MPU protected zone.\n/// \\note API identical to osThreadTerminateZone\nstatic osStatus_t svcRtxThreadTerminateZone (uint32_t zone) {\n  os_thread_t *thread;\n  os_thread_t *thread_next;\n\n#ifdef RTX_THREAD_WATCHDOG\n  // Check Watchdog Alarm Flag\n  if (WatchdogAlarmFlag != 0U) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorISR);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorISR;\n  }\n#endif\n\n  // Check parameters\n  if (zone > 0x3FU) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n  // Threads in Wait List\n  thread = osRtxInfo.thread.wait_list;\n  while (thread != NULL) {\n    thread_next = thread->delay_next;\n    if (thread->zone == zone) {\n      osRtxThreadListRemove(thread);\n      osRtxThreadDelayRemove(thread);\n#ifdef RTX_THREAD_WATCHDOG\n      osRtxThreadWatchdogRemove(thread);\n#endif\n      osRtxMutexOwnerRelease(thread->mutex_list);\n      osRtxThreadJoinWakeup(thread);\n      osRtxThreadDestroy(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Threads in Delay List\n  thread = osRtxInfo.thread.delay_list;\n  while (thread != NULL) {\n    thread_next = thread->delay_next;\n    if (thread->zone == zone) {\n      osRtxThreadListRemove(thread);\n      osRtxThreadDelayRemove(thread);\n#ifdef RTX_THREAD_WATCHDOG\n      osRtxThreadWatchdogRemove(thread);\n#endif\n      osRtxMutexOwnerRelease(thread->mutex_list);\n      osRtxThreadJoinWakeup(thread);\n      osRtxThreadDestroy(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Threads in Ready List\n  thread = osRtxInfo.thread.ready.thread_list;\n  while (thread != NULL) {\n    thread_next = thread->thread_next;\n    if (thread->zone == zone) {\n      osRtxThreadListRemove(thread);\n#ifdef RTX_THREAD_WATCHDOG\n      osRtxThreadWatchdogRemove(thread);\n#endif\n      osRtxMutexOwnerRelease(thread->mutex_list);\n      osRtxThreadJoinWakeup(thread);\n      osRtxThreadDestroy(thread);\n    }\n    thread = thread_next;\n  }\n\n  // Running Thread\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) && (thread->zone == zone)) {\n    if ((osRtxKernelGetState() != osRtxKernelRunning) ||\n        (osRtxInfo.thread.ready.thread_list == NULL)) {\n      osRtxThreadDispatch(NULL);\n      EvrRtxThreadError(thread, (int32_t)osErrorResource);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return osErrorResource;\n    }\n#ifdef RTX_THREAD_WATCHDOG\n    osRtxThreadWatchdogRemove(thread);\n#endif\n    osRtxMutexOwnerRelease(thread->mutex_list);\n    osRtxThreadJoinWakeup(thread);\n    // Switch to next Ready Thread\n    osRtxThreadSwitch(osRtxThreadListGet(&osRtxInfo.thread.ready));\n    // Update Stack Pointer\n    thread->sp = __get_PSP();\n#ifdef RTX_STACK_CHECK\n    // Check Stack usage\n    if (!osRtxThreadStackCheck(thread)) {\n      osRtxThreadSetRunning(osRtxInfo.thread.run.next);\n      (void)osRtxKernelErrorNotify(osRtxErrorStackOverflow, thread);\n    }\n#endif\n    // Mark running thread as deleted\n    osRtxThreadSetRunning(NULL);\n    // Destroy Thread\n    osRtxThreadDestroy(thread);\n  } else {\n    osRtxThreadDispatch(NULL);\n  }\n\n  return osOK;\n}\n#endif\n\n/// Get number of active threads.\n/// \\note API identical to osThreadGetCount\nstatic uint32_t svcRtxThreadGetCount (void) {\n  const os_thread_t *thread;\n        uint32_t     count;\n\n  // Running Thread\n  count = 1U;\n\n  // Ready List\n  for (thread = osRtxInfo.thread.ready.thread_list;\n       thread != NULL; thread = thread->thread_next) {\n    count++;\n  }\n\n  // Delay List\n  for (thread = osRtxInfo.thread.delay_list;\n       thread != NULL; thread = thread->delay_next) {\n    count++;\n  }\n\n  // Wait List\n  for (thread = osRtxInfo.thread.wait_list;\n       thread != NULL; thread = thread->delay_next) {\n    count++;\n  }\n\n  EvrRtxThreadGetCount(count);\n\n  return count;\n}\n\n/// Enumerate active threads.\n/// \\note API identical to osThreadEnumerate\nstatic uint32_t svcRtxThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {\n  os_thread_t *thread;\n  uint32_t     count;\n\n  // Check parameters\n  if ((thread_array == NULL) || (array_items == 0U)) {\n    EvrRtxThreadEnumerate(thread_array, array_items, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  // Running Thread\n  *thread_array = osRtxThreadGetRunning();\n   thread_array++;\n   count = 1U;\n\n  // Ready List\n  for (thread = osRtxInfo.thread.ready.thread_list;\n       (thread != NULL) && (count < array_items); thread = thread->thread_next) {\n    *thread_array = thread;\n     thread_array++;\n     count++;\n  }\n\n  // Delay List\n  for (thread = osRtxInfo.thread.delay_list;\n       (thread != NULL) && (count < array_items); thread = thread->delay_next) {\n    *thread_array = thread;\n     thread_array++;\n     count++;\n  }\n\n  // Wait List\n  for (thread = osRtxInfo.thread.wait_list;\n       (thread != NULL) && (count < array_items); thread = thread->delay_next) {\n    *thread_array = thread;\n     thread_array++;\n     count++;\n  }\n\n  EvrRtxThreadEnumerate(thread_array - count, array_items, count);\n\n  return count;\n}\n\n/// Set the specified Thread Flags of a thread.\n/// \\note API identical to osThreadFlagsSet\nstatic uint32_t svcRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {\n  os_thread_t       *thread = osRtxThreadId(thread_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread_running;\n#endif\n  uint32_t           thread_flags;\n  uint32_t           thread_flags0;\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread) ||\n      ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U)) {\n    EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorParameter);\n  }\n\n  // Check object state\n  if (thread->state == osRtxThreadTerminated) {\n    EvrRtxThreadFlagsError(thread, (int32_t)osErrorResource);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorResource);\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread_running = osRtxThreadGetRunning();\n  if ((thread_running != NULL) &&\n      ((thread_running->attr >> osRtxAttrClass_Pos) < (thread->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxThreadFlagsError(thread, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorSafetyClass);\n  }\n#endif\n\n  // Set Thread Flags\n  thread_flags = ThreadFlagsSet(thread, flags);\n\n  // Check if Thread is waiting for Thread Flags\n  if (thread->state == osRtxThreadWaitingThreadFlags) {\n    thread_flags0 = ThreadFlagsCheck(thread, thread->wait_flags, thread->flags_options);\n    if (thread_flags0 != 0U) {\n      if ((thread->flags_options & osFlagsNoClear) == 0U) {\n        thread_flags = thread_flags0 & ~thread->wait_flags;\n      } else {\n        thread_flags = thread_flags0;\n      }\n      osRtxThreadWaitExit(thread, thread_flags0, TRUE);\n      EvrRtxThreadFlagsWaitCompleted(thread->wait_flags, thread->flags_options, thread_flags0, thread);\n    }\n  }\n\n  EvrRtxThreadFlagsSetDone(thread, thread_flags);\n\n  return thread_flags;\n}\n\n/// Clear the specified Thread Flags of current running thread.\n/// \\note API identical to osThreadFlagsClear\nstatic uint32_t svcRtxThreadFlagsClear (uint32_t flags) {\n  os_thread_t *thread;\n  uint32_t     thread_flags;\n\n  // Check running thread\n  thread = osRtxThreadGetRunning();\n  if (thread == NULL) {\n    EvrRtxThreadFlagsError(NULL, osRtxErrorKernelNotRunning);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osError);\n  }\n\n  // Check parameters\n  if ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U) {\n    EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorParameter);\n  }\n\n  // Clear Thread Flags\n  thread_flags = ThreadFlagsClear(thread, flags);\n\n  EvrRtxThreadFlagsClearDone(thread_flags);\n\n  return thread_flags;\n}\n\n/// Get the current Thread Flags of current running thread.\n/// \\note API identical to osThreadFlagsGet\nstatic uint32_t svcRtxThreadFlagsGet (void) {\n  const os_thread_t *thread;\n\n  // Check running thread\n  thread = osRtxThreadGetRunning();\n  if (thread == NULL) {\n    EvrRtxThreadFlagsGet(0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  EvrRtxThreadFlagsGet(thread->thread_flags);\n\n  return thread->thread_flags;\n}\n\n/// Wait for one or more Thread Flags of the current running thread to become signaled.\n/// \\note API identical to osThreadFlagsWait\nstatic uint32_t svcRtxThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {\n  os_thread_t *thread;\n  uint32_t     thread_flags;\n\n  // Check running thread\n  thread = osRtxThreadGetRunning();\n  if (thread == NULL) {\n    EvrRtxThreadFlagsError(NULL, osRtxErrorKernelNotRunning);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osError);\n  }\n\n  // Check parameters\n  if ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U) {\n    EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorParameter);\n  }\n\n  // Check Thread Flags\n  thread_flags = ThreadFlagsCheck(thread, flags, options);\n  if (thread_flags != 0U) {\n    EvrRtxThreadFlagsWaitCompleted(flags, options, thread_flags, thread);\n  } else {\n    // Check if timeout is specified\n    if (timeout != 0U) {\n      // Store waiting flags and options\n      EvrRtxThreadFlagsWaitPending(flags, options, timeout);\n      thread->wait_flags = flags;\n      thread->flags_options = (uint8_t)options;\n      // Suspend current Thread\n      if (!osRtxThreadWaitEnter(osRtxThreadWaitingThreadFlags, timeout)) {\n        EvrRtxThreadFlagsWaitTimeout(thread);\n      }\n      thread_flags = (uint32_t)osErrorTimeout;\n    } else {\n      EvrRtxThreadFlagsWaitNotCompleted(flags, options);\n      thread_flags = (uint32_t)osErrorResource;\n    }\n  }\n  return thread_flags;\n}\n\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_3 (ThreadNew,           osThreadId_t,    osThreadFunc_t, void *, const osThreadAttr_t *)\nSVC0_1 (ThreadGetName,       const char *,    osThreadId_t)\n#ifdef RTX_SAFETY_CLASS\nSVC0_1 (ThreadGetClass,      uint32_t,        osThreadId_t)\n#endif\n#ifdef RTX_EXECUTION_ZONE\nSVC0_1 (ThreadGetZone,       uint32_t,        osThreadId_t)\n#endif\nSVC0_0 (ThreadGetId,         osThreadId_t)\nSVC0_1 (ThreadGetState,      osThreadState_t, osThreadId_t)\nSVC0_1 (ThreadGetStackSize,  uint32_t,        osThreadId_t)\nSVC0_1 (ThreadGetStackSpace, uint32_t,        osThreadId_t)\nSVC0_2 (ThreadSetPriority,   osStatus_t,      osThreadId_t, osPriority_t)\nSVC0_1 (ThreadGetPriority,   osPriority_t,    osThreadId_t)\nSVC0_0 (ThreadYield,         osStatus_t)\nSVC0_1 (ThreadSuspend,       osStatus_t,      osThreadId_t)\nSVC0_1 (ThreadResume,        osStatus_t,      osThreadId_t)\nSVC0_1 (ThreadDetach,        osStatus_t,      osThreadId_t)\nSVC0_1 (ThreadJoin,          osStatus_t,      osThreadId_t)\nSVC0_0N(ThreadExit,          void)\nSVC0_1 (ThreadTerminate,     osStatus_t,      osThreadId_t)\n#ifdef RTX_THREAD_WATCHDOG\nSVC0_1 (ThreadFeedWatchdog,      osStatus_t,  uint32_t)\n#endif\n#ifdef RTX_SAFETY_FEATURES\nSVC0_0 (ThreadProtectPrivileged, osStatus_t)\n#endif\n#ifdef RTX_SAFETY_CLASS\nSVC0_2 (ThreadSuspendClass,      osStatus_t,  uint32_t, uint32_t)\nSVC0_2 (ThreadResumeClass,       osStatus_t,  uint32_t, uint32_t)\n#endif\nSVC0_0 (ThreadGetCount,      uint32_t)\nSVC0_2 (ThreadEnumerate,     uint32_t,        osThreadId_t *, uint32_t)\nSVC0_2 (ThreadFlagsSet,      uint32_t,        osThreadId_t, uint32_t)\nSVC0_1 (ThreadFlagsClear,    uint32_t,        uint32_t)\nSVC0_0 (ThreadFlagsGet,      uint32_t)\nSVC0_3 (ThreadFlagsWait,     uint32_t,        uint32_t, uint32_t, uint32_t)\n//lint --flb \"Library End\"\n\n\n//  ==== ISR Calls ====\n\n/// Set the specified Thread Flags of a thread.\n/// \\note API identical to osThreadFlagsSet\n__STATIC_INLINE\nuint32_t isrRtxThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {\n  os_thread_t *thread = osRtxThreadId(thread_id);\n  uint32_t     thread_flags;\n\n  // Check parameters\n  if (!IsThreadPtrValid(thread) || (thread->id != osRtxIdThread) ||\n      ((flags & ~(((uint32_t)1U << osRtxThreadFlagsLimit) - 1U)) != 0U)) {\n    EvrRtxThreadFlagsError(thread, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorParameter);\n  }\n\n  // Check object state\n  if (thread->state == osRtxThreadTerminated) {\n    EvrRtxThreadFlagsError(thread, (int32_t)osErrorResource);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return ((uint32_t)osErrorResource);\n  }\n\n  // Set Thread Flags\n  thread_flags = ThreadFlagsSet(thread, flags);\n\n  // Register post ISR processing\n  osRtxPostProcess(osRtxObject(thread));\n\n  EvrRtxThreadFlagsSetDone(thread, thread_flags);\n\n  return thread_flags;\n}\n\n\n//  ==== Library functions ====\n\n/// RTOS Thread Before Free Hook.\n//lint -esym(759,osRtxThreadBeforeFree) \"Prototype in header\"\n//lint -esym(765,osRtxThreadBeforeFree) \"Global scope (can be overridden)\"\n__WEAK void osRtxThreadBeforeFree (os_thread_t *thread) {\n  (void)thread;\n}\n\n/// Thread startup (Idle and Timer Thread).\n/// \\return true - success, false - failure.\nbool_t osRtxThreadStartup (void) {\n  bool_t ret = FALSE;\n\n  // Create Idle Thread\n  osRtxInfo.thread.idle = osRtxThreadId(\n    svcRtxThreadNew(osRtxIdleThread, NULL, osRtxConfig.idle_thread_attr)\n  );\n\n  // Create Timer Thread\n  if (osRtxConfig.timer_setup != NULL) {\n    if (osRtxConfig.timer_setup() == 0) {\n      osRtxInfo.timer.thread = osRtxThreadId(\n        svcRtxThreadNew(osRtxConfig.timer_thread, osRtxInfo.timer.mq, osRtxConfig.timer_thread_attr)\n      );\n      if (osRtxInfo.timer.thread != NULL) {\n        ret = TRUE;\n      }\n    }\n  } else {\n    ret = TRUE;\n  }\n\n  return ret;\n}\n\n\n//  ==== Public API ====\n\n/// Create a thread and add it to Active Threads.\nosThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {\n  osThreadId_t thread_id;\n\n  EvrRtxThreadNew(func, argument, attr);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorISR);\n    thread_id = NULL;\n  } else {\n    thread_id = __svcThreadNew(func, argument, attr);\n  }\n  return thread_id;\n}\n\n/// Get name of a thread.\nconst char *osThreadGetName (osThreadId_t thread_id) {\n  const char *name;\n\n  if (IsException() || IsIrqMasked()) {\n    name = svcRtxThreadGetName(thread_id);\n  } else {\n    name =  __svcThreadGetName(thread_id);\n  }\n  return name;\n}\n\n#ifdef RTX_SAFETY_CLASS\n/// Get safety class of a thread.\nuint32_t osThreadGetClass (osThreadId_t thread_id) {\n  uint32_t safety_class;\n\n  if (IsException() || IsIrqMasked()) {\n    safety_class = svcRtxThreadGetClass(thread_id);\n  } else {\n    safety_class =  __svcThreadGetClass(thread_id);\n  }\n  return safety_class;\n}\n#endif\n\n#ifdef RTX_EXECUTION_ZONE\n/// Get zone of a thread.\nuint32_t osThreadGetZone (osThreadId_t thread_id) {\n  uint32_t zone;\n\n  if (IsException() || IsIrqMasked()) {\n    zone = svcRtxThreadGetZone(thread_id);\n  } else {\n    zone =  __svcThreadGetZone(thread_id);\n  }\n  return zone;\n}\n#endif\n\n/// Return the thread ID of the current running thread.\nosThreadId_t osThreadGetId (void) {\n  osThreadId_t thread_id;\n\n  if (IsException() || IsIrqMasked()) {\n    thread_id = svcRtxThreadGetId();\n  } else {\n    thread_id =  __svcThreadGetId();\n  }\n  return thread_id;\n}\n\n/// Get current thread state of a thread.\nosThreadState_t osThreadGetState (osThreadId_t thread_id) {\n  osThreadState_t state;\n\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadGetState(thread_id, osThreadError);\n    state = osThreadError;\n  } else {\n    state = __svcThreadGetState(thread_id);\n  }\n  return state;\n}\n\n/// Get stack size of a thread.\nuint32_t osThreadGetStackSize (osThreadId_t thread_id) {\n  uint32_t stack_size;\n\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadGetStackSize(thread_id, 0U);\n    stack_size = 0U;\n  } else {\n    stack_size = __svcThreadGetStackSize(thread_id);\n  }\n  return stack_size;\n}\n\n/// Get available stack space of a thread based on stack watermark recording during execution.\nuint32_t osThreadGetStackSpace (osThreadId_t thread_id) {\n  uint32_t stack_space;\n\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadGetStackSpace(thread_id, 0U);\n    stack_space = 0U;\n  } else {\n    stack_space = __svcThreadGetStackSpace(thread_id);\n  }\n  return stack_space;\n}\n\n/// Change priority of a thread.\nosStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {\n  osStatus_t status;\n\n  EvrRtxThreadSetPriority(thread_id, priority);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(thread_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcThreadSetPriority(thread_id, priority);\n  }\n  return status;\n}\n\n/// Get current priority of a thread.\nosPriority_t osThreadGetPriority (osThreadId_t thread_id) {\n  osPriority_t priority;\n\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadGetPriority(thread_id, osPriorityError);\n    priority = osPriorityError;\n  } else {\n    priority = __svcThreadGetPriority(thread_id);\n  }\n  return priority;\n}\n\n/// Pass control to next thread that is in state READY.\nosStatus_t osThreadYield (void) {\n  osStatus_t status;\n\n  EvrRtxThreadYield();\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcThreadYield();\n  }\n  return status;\n}\n\n/// Suspend execution of a thread.\nosStatus_t osThreadSuspend (osThreadId_t thread_id) {\n  osStatus_t status;\n\n  EvrRtxThreadSuspend(thread_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(thread_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcThreadSuspend(thread_id);\n  }\n  return status;\n}\n\n/// Resume execution of a thread.\nosStatus_t osThreadResume (osThreadId_t thread_id) {\n  osStatus_t status;\n\n  EvrRtxThreadResume(thread_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(thread_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcThreadResume(thread_id);\n  }\n  return status;\n}\n\n/// Detach a thread (thread storage can be reclaimed when thread terminates).\nosStatus_t osThreadDetach (osThreadId_t thread_id) {\n  osStatus_t status;\n\n  EvrRtxThreadDetach(thread_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(thread_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcThreadDetach(thread_id);\n  }\n  return status;\n}\n\n/// Wait for specified thread to terminate.\nosStatus_t osThreadJoin (osThreadId_t thread_id) {\n  osStatus_t status;\n\n  EvrRtxThreadJoin(thread_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(thread_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcThreadJoin(thread_id);\n  }\n  return status;\n}\n\n/// Terminate execution of current running thread.\n__NO_RETURN void osThreadExit (void) {\n  EvrRtxThreadExit();\n  __svcThreadExit();\n  EvrRtxThreadError(NULL, (int32_t)osError);\n  for (;;) {}\n}\n\n/// Terminate execution of a thread.\nosStatus_t osThreadTerminate (osThreadId_t thread_id) {\n  osStatus_t status;\n\n  EvrRtxThreadTerminate(thread_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(thread_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcThreadTerminate(thread_id);\n  }\n  return status;\n}\n\n#ifdef RTX_THREAD_WATCHDOG\n/// Feed watchdog of the current running thread.\nosStatus_t osThreadFeedWatchdog (uint32_t ticks) {\n  osStatus_t status;\n\n  EvrRtxThreadFeedWatchdog(ticks);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcThreadFeedWatchdog(ticks);\n  }\n  return status;\n}\n#endif\n\n#ifdef RTX_SAFETY_FEATURES\n/// Protect the creation of privileged threads.\nosStatus_t osThreadProtectPrivileged (void) {\n  osStatus_t status;\n\n  EvrRtxThreadProtectPrivileged();\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadError(NULL, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcThreadProtectPrivileged();\n  }\n  return status;\n}\n#endif\n\n#ifdef RTX_SAFETY_CLASS\n\n/// Suspend execution of threads for specified safety classes.\nosStatus_t osThreadSuspendClass (uint32_t safety_class, uint32_t mode) {\n  osStatus_t status;\n\n  EvrRtxThreadSuspendClass(safety_class, mode);\n  if (IsException() || IsIrqMasked()) {\n    if (IsTickIrq(osRtxInfo.tick_irqn)) {\n      status = svcRtxThreadSuspendClass(safety_class, mode);\n    } else {\n      EvrRtxThreadError(NULL, (int32_t)osErrorISR);\n      status = osErrorISR;\n    }\n  } else {\n    status   =  __svcThreadSuspendClass(safety_class, mode);\n  }\n  return status;\n}\n\n/// Resume execution of threads for specified safety classes.\nosStatus_t osThreadResumeClass (uint32_t safety_class, uint32_t mode) {\n  osStatus_t status;\n\n  EvrRtxThreadResumeClass(safety_class, mode);\n  if (IsException() || IsIrqMasked()) {\n    if (IsTickIrq(osRtxInfo.tick_irqn)) {\n      status = svcRtxThreadResumeClass(safety_class, mode);\n    } else {\n      EvrRtxThreadError(NULL, (int32_t)osErrorISR);\n      status = osErrorISR;\n    }\n  } else {\n    status   =  __svcThreadResumeClass(safety_class, mode);\n  }\n  return status;\n}\n\n#endif\n\n#ifdef RTX_EXECUTION_ZONE\n/// Terminate execution of threads assigned to a specified MPU protected zone.\nosStatus_t osThreadTerminateZone (uint32_t zone) {\n  osStatus_t status;\n\n  EvrRtxThreadTerminateZone(zone);\n  if (IsException() || IsIrqMasked()) {\n    if (IsFault() || IsSVCallIrq() || IsPendSvIrq() || IsTickIrq(osRtxInfo.tick_irqn)) {\n      status = svcRtxThreadTerminateZone(zone);\n    } else {\n      EvrRtxThreadError(NULL, (int32_t)osErrorISR);\n      status = osErrorISR;\n    }\n  } else {\n    EvrRtxThreadError(osRtxThreadGetRunning(), (int32_t)osError);\n    status   = osError;\n  }\n  return status;\n}\n#endif\n\n/// Get number of active threads.\nuint32_t osThreadGetCount (void) {\n  uint32_t count;\n\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadGetCount(0U);\n    count = 0U;\n  } else {\n    count = __svcThreadGetCount();\n  }\n  return count;\n}\n\n/// Enumerate active threads.\nuint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {\n  uint32_t count;\n\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadEnumerate(thread_array, array_items, 0U);\n    count = 0U;\n  } else {\n    count = __svcThreadEnumerate(thread_array, array_items);\n  }\n  return count;\n}\n\n/// Set the specified Thread Flags of a thread.\nuint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {\n  uint32_t thread_flags;\n\n  EvrRtxThreadFlagsSet(thread_id, flags);\n  if (IsException() || IsIrqMasked()) {\n    thread_flags = isrRtxThreadFlagsSet(thread_id, flags);\n  } else {\n    thread_flags =  __svcThreadFlagsSet(thread_id, flags);\n  }\n  return thread_flags;\n}\n\n/// Clear the specified Thread Flags of current running thread.\nuint32_t osThreadFlagsClear (uint32_t flags) {\n  uint32_t thread_flags;\n\n  EvrRtxThreadFlagsClear(flags);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadFlagsError(NULL, (int32_t)osErrorISR);\n    thread_flags = (uint32_t)osErrorISR;\n  } else {\n    thread_flags = __svcThreadFlagsClear(flags);\n  }\n  return thread_flags;\n}\n\n/// Get the current Thread Flags of current running thread.\nuint32_t osThreadFlagsGet (void) {\n  uint32_t thread_flags;\n\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadFlagsGet(0U);\n    thread_flags = 0U;\n  } else {\n    thread_flags = __svcThreadFlagsGet();\n  }\n  return thread_flags;\n}\n\n/// Wait for one or more Thread Flags of the current running thread to become signaled.\nuint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {\n  uint32_t thread_flags;\n\n  EvrRtxThreadFlagsWait(flags, options, timeout);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxThreadFlagsError(NULL, (int32_t)osErrorISR);\n    thread_flags = (uint32_t)osErrorISR;\n  } else {\n    thread_flags = __svcThreadFlagsWait(flags, options, timeout);\n  }\n  return thread_flags;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Source/rtx_timer.c",
    "content": "/*\n * Copyright (c) 2013-2023 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       Timer functions\n *\n * -----------------------------------------------------------------------------\n */\n\n#include \"rtx_lib.h\"\n\n\n//  OS Runtime Object Memory Usage\n#ifdef RTX_OBJ_MEM_USAGE\nosRtxObjectMemUsage_t osRtxTimerMemUsage \\\n__attribute__((section(\".data.os.timer.obj\"))) =\n{ 0U, 0U, 0U };\n#endif\n\n\n//  ==== Helper functions ====\n\n/// Insert Timer into the Timer List sorted by Time.\n/// \\param[in]  timer           timer object.\n/// \\param[in]  tick            timer tick.\nstatic void TimerInsert (os_timer_t *timer, uint32_t tick) {\n  os_timer_t *prev, *next;\n\n  prev = NULL;\n  next = osRtxInfo.timer.list;\n  while ((next != NULL) && (next->tick <= tick)) {\n    tick -= next->tick;\n    prev  = next;\n    next  = next->next;\n  }\n  timer->tick = tick;\n  timer->prev = prev;\n  timer->next = next;\n  if (next != NULL) {\n    next->tick -= timer->tick;\n    next->prev  = timer;\n  }\n  if (prev != NULL) {\n    prev->next = timer;\n  } else {\n    osRtxInfo.timer.list = timer;\n  }\n}\n\n/// Remove Timer from the Timer List.\n/// \\param[in]  timer           timer object.\nstatic void TimerRemove (const os_timer_t *timer) {\n\n  if (timer->next != NULL) {\n    timer->next->tick += timer->tick;\n    timer->next->prev  = timer->prev;\n  }\n  if (timer->prev != NULL) {\n    timer->prev->next  = timer->next;\n  } else {\n    osRtxInfo.timer.list = timer->next;\n  }\n}\n\n/// Unlink Timer from the Timer List Head.\n/// \\param[in]  timer           timer object.\nstatic void TimerUnlink (const os_timer_t *timer) {\n\n  if (timer->next != NULL) {\n    timer->next->prev = timer->prev;\n  }\n  osRtxInfo.timer.list = timer->next;\n}\n\n/// Verify that Timer object pointer is valid.\n/// \\param[in]  timer           timer object.\n/// \\return true - valid, false - invalid.\nstatic bool_t IsTimerPtrValid (const os_timer_t *timer) {\n#ifdef RTX_OBJ_PTR_CHECK\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  uint32_t cb_start  = (uint32_t)&__os_timer_cb_start__;\n  uint32_t cb_length = (uint32_t)&__os_timer_cb_length__;\n\n  // Check the section boundaries\n  if (((uint32_t)timer - cb_start) >= cb_length) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n  // Check the object alignment\n  if ((((uint32_t)timer - cb_start) % sizeof(os_timer_t)) != 0U) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#else\n  // Check NULL pointer\n  if (timer == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return FALSE;\n  }\n#endif\n  return TRUE;\n}\n\n\n//  ==== Library functions ====\n\n/// Timer Tick (called each SysTick).\nstatic void osRtxTimerTick (void) {\n  os_thread_t *thread_running;\n  os_timer_t  *timer;\n  osStatus_t   status;\n\n  timer = osRtxInfo.timer.list;\n  if (timer == NULL) {\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return;\n  }\n\n  thread_running = osRtxThreadGetRunning();\n\n  timer->tick--;\n  while ((timer != NULL) && (timer->tick == 0U)) {\n    TimerUnlink(timer);\n    status = osMessageQueuePut(osRtxInfo.timer.mq, &timer->finfo, 0U, 0U);\n    if (status != osOK) {\n      const os_thread_t *thread = osRtxThreadGetRunning();\n      osRtxThreadSetRunning(osRtxInfo.thread.run.next);\n      (void)osRtxKernelErrorNotify(osRtxErrorTimerQueueOverflow, timer);\n      if (osRtxThreadGetRunning() == NULL) {\n        if (thread_running == thread) {\n          thread_running = NULL;\n        }\n      }\n    }\n    if ((timer->attr & osRtxTimerPeriodic) != 0U) {\n      TimerInsert(timer, timer->load);\n    } else {\n      timer->state = osRtxTimerStopped;\n    }\n    timer = osRtxInfo.timer.list;\n  }\n\n  osRtxThreadSetRunning(thread_running);\n}\n\n/// Setup Timer Thread objects.\n//lint -esym(714,osRtxTimerSetup) \"Referenced from library configuration\"\n//lint -esym(759,osRtxTimerSetup) \"Prototype in header\"\n//lint -esym(765,osRtxTimerSetup) \"Global scope\"\nint32_t osRtxTimerSetup (void) {\n  int32_t ret = -1;\n\n  if (osRtxMessageQueueTimerSetup() == 0) {\n    osRtxInfo.timer.tick = osRtxTimerTick;\n    ret = 0;\n  }\n\n  return ret;\n}\n\n/// Timer Thread\n//lint -esym(714,osRtxTimerThread) \"Referenced from library configuration\"\n//lint -esym(759,osRtxTimerThread) \"Prototype in header\"\n//lint -esym(765,osRtxTimerThread) \"Global scope\"\n__NO_RETURN void osRtxTimerThread (void *argument) {\n  os_timer_finfo_t   finfo;\n  osStatus_t         status;\n  osMessageQueueId_t mq = (osMessageQueueId_t)argument;\n\n  for (;;) {\n    //lint -e{934} \"Taking address of near auto variable\"\n    status = osMessageQueueGet(mq, &finfo, NULL, osWaitForever);\n    if (status == osOK) {\n      EvrRtxTimerCallback(finfo.func, finfo.arg);\n      (finfo.func)(finfo.arg);\n    }\n  }\n}\n\n/// Destroy a Timer object.\n/// \\param[in]  timer           timer object.\nstatic void osRtxTimerDestroy (os_timer_t *timer) {\n\n  // Mark object as inactive and invalid\n  timer->state = osRtxTimerInactive;\n  timer->id    = osRtxIdInvalid;\n\n  // Free object memory\n  if ((timer->flags & osRtxFlagSystemObject) != 0U) {\n#ifdef RTX_OBJ_PTR_CHECK\n    (void)osRtxMemoryPoolFree(osRtxInfo.mpi.timer, timer);\n#else\n    if (osRtxInfo.mpi.timer != NULL) {\n      (void)osRtxMemoryPoolFree(osRtxInfo.mpi.timer, timer);\n    } else {\n      (void)osRtxMemoryFree(osRtxInfo.mem.common, timer);\n    }\n#endif\n#ifdef RTX_OBJ_MEM_USAGE\n    osRtxTimerMemUsage.cnt_free++;\n#endif\n  }\n\n  EvrRtxTimerDestroyed(timer);\n}\n\n#ifdef RTX_SAFETY_CLASS\n/// Delete a Timer safety class.\n/// \\param[in]  safety_class    safety class.\n/// \\param[in]  mode            safety mode.\nvoid osRtxTimerDeleteClass (uint32_t safety_class, uint32_t mode) {\n  os_timer_t *timer;\n  uint32_t    length;\n\n  //lint --e{923} --e{9078} \"cast from pointer to unsigned int\" [MISRA Note 7]\n  timer = (os_timer_t *)(uint32_t)&__os_timer_cb_start__;\n  length    =           (uint32_t)&__os_timer_cb_length__;\n  while (length >= sizeof(os_timer_t)) {\n    if (   (timer->id == osRtxIdTimer) &&\n        ((((mode & osSafetyWithSameClass)  != 0U) &&\n          ((timer->attr >> osRtxAttrClass_Pos) == (uint8_t)safety_class)) ||\n         (((mode & osSafetyWithLowerClass) != 0U) &&\n          ((timer->attr >> osRtxAttrClass_Pos) <  (uint8_t)safety_class)))) {\n      if (timer->state == osRtxTimerRunning) {\n        TimerRemove(timer);\n      }\n      osRtxTimerDestroy(timer);\n    }\n    length -= sizeof(os_timer_t);\n    timer++;\n  }\n}\n#endif\n\n\n//  ==== Service Calls ====\n\n/// Create and Initialize a timer.\n/// \\note API identical to osTimerNew\nstatic osTimerId_t svcRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {\n  os_timer_t        *timer;\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread = osRtxThreadGetRunning();\n  uint32_t           attr_bits;\n#endif\n  uint8_t            flags;\n  const char        *name;\n\n  // Check parameters\n  if ((func == NULL) || ((type != osTimerOnce) && (type != osTimerPeriodic))) {\n    EvrRtxTimerError(NULL, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  // Process attributes\n  if (attr != NULL) {\n    name      = attr->name;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = attr->attr_bits;\n#endif\n    //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 6]\n    timer      = attr->cb_mem;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      if ((thread != NULL) &&\n          ((thread->attr >> osRtxAttrClass_Pos) <\n          (uint8_t)((attr_bits & osSafetyClass_Msk) >> osSafetyClass_Pos))) {\n        EvrRtxTimerError(NULL, (int32_t)osErrorSafetyClass);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n#endif\n    if (timer != NULL) {\n      if (!IsTimerPtrValid(timer) || (attr->cb_size != sizeof(os_timer_t))) {\n        EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    } else {\n      if (attr->cb_size != 0U) {\n        EvrRtxTimerError(NULL, osRtxErrorInvalidControlBlock);\n        //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n        return NULL;\n      }\n    }\n  } else {\n    name      = NULL;\n#ifdef RTX_SAFETY_CLASS\n    attr_bits = 0U;\n#endif\n    timer     = NULL;\n  }\n\n  // Allocate object memory if not provided\n  if (timer == NULL) {\n    if (osRtxInfo.mpi.timer != NULL) {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      timer = osRtxMemoryPoolAlloc(osRtxInfo.mpi.timer);\n#ifndef RTX_OBJ_PTR_CHECK\n    } else {\n      //lint -e{9079} \"conversion from pointer to void to pointer to other type\" [MISRA Note 5]\n      timer = osRtxMemoryAlloc(osRtxInfo.mem.common, sizeof(os_timer_t), 1U);\n#endif\n    }\n#ifdef RTX_OBJ_MEM_USAGE\n    if (timer != NULL) {\n      uint32_t used;\n      osRtxTimerMemUsage.cnt_alloc++;\n      used = osRtxTimerMemUsage.cnt_alloc - osRtxTimerMemUsage.cnt_free;\n      if (osRtxTimerMemUsage.max_used < used) {\n        osRtxTimerMemUsage.max_used = used;\n      }\n    }\n#endif\n    flags = osRtxFlagSystemObject;\n  } else {\n    flags = 0U;\n  }\n\n  if (timer != NULL) {\n    // Initialize control block\n    timer->id         = osRtxIdTimer;\n    timer->state      = osRtxTimerStopped;\n    timer->flags      = flags;\n    if (type == osTimerPeriodic) {\n      timer->attr     = osRtxTimerPeriodic;\n    } else {\n      timer->attr     = 0U;\n    }\n    timer->name       = name;\n    timer->prev       = NULL;\n    timer->next       = NULL;\n    timer->tick       = 0U;\n    timer->load       = 0U;\n    timer->finfo.func = func;\n    timer->finfo.arg  = argument;\n#ifdef RTX_SAFETY_CLASS\n    if ((attr_bits & osSafetyClass_Valid) != 0U) {\n      timer->attr    |= (uint8_t)((attr_bits & osSafetyClass_Msk) >>\n                                  (osSafetyClass_Pos - osRtxAttrClass_Pos));\n    } else {\n      // Inherit safety class from the running thread\n      if (thread != NULL) {\n        timer->attr  |= (uint8_t)(thread->attr & osRtxAttrClass_Msk);\n      }\n    }\n#endif\n    EvrRtxTimerCreated(timer, timer->name);\n  } else {\n    EvrRtxTimerError(NULL, (int32_t)osErrorNoMemory);\n  }\n\n  return timer;\n}\n\n/// Get name of a timer.\n/// \\note API identical to osTimerGetName\nstatic const char *svcRtxTimerGetName (osTimerId_t timer_id) {\n  os_timer_t *timer = osRtxTimerId(timer_id);\n\n  // Check parameters\n  if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer)) {\n    EvrRtxTimerGetName(timer, NULL);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return NULL;\n  }\n\n  EvrRtxTimerGetName(timer, timer->name);\n\n  return timer->name;\n}\n\n/// Start or restart a timer.\n/// \\note API identical to osTimerStart\nstatic osStatus_t svcRtxTimerStart (osTimerId_t timer_id, uint32_t ticks) {\n  os_timer_t        *timer = osRtxTimerId(timer_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread;\n#endif\n\n  // Check parameters\n  if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer) || (ticks == 0U)) {\n    EvrRtxTimerError(timer, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (timer->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxTimerError(timer, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  if (timer->state == osRtxTimerRunning) {\n    timer->load = ticks;\n    TimerRemove(timer);\n  } else {\n    if (osRtxInfo.timer.tick == NULL) {\n      EvrRtxTimerError(timer, (int32_t)osErrorResource);\n      //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n      return osErrorResource;\n    } else {\n      timer->state = osRtxTimerRunning;\n      timer->load  = ticks;\n    }\n  }\n\n  TimerInsert(timer, ticks);\n\n  EvrRtxTimerStarted(timer);\n\n  return osOK;\n}\n\n/// Stop a timer.\n/// \\note API identical to osTimerStop\nstatic osStatus_t svcRtxTimerStop (osTimerId_t timer_id) {\n  os_timer_t        *timer = osRtxTimerId(timer_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread;\n#endif\n\n  // Check parameters\n  if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer)) {\n    EvrRtxTimerError(timer, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (timer->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxTimerError(timer, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  // Check object state\n  if (timer->state != osRtxTimerRunning) {\n    EvrRtxTimerError(timer, (int32_t)osErrorResource);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorResource;\n  }\n\n  timer->state = osRtxTimerStopped;\n\n  TimerRemove(timer);\n\n  EvrRtxTimerStopped(timer);\n\n  return osOK;\n}\n\n/// Check if a timer is running.\n/// \\note API identical to osTimerIsRunning\nstatic uint32_t svcRtxTimerIsRunning (osTimerId_t timer_id) {\n  os_timer_t *timer = osRtxTimerId(timer_id);\n  uint32_t    is_running;\n\n  // Check parameters\n  if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer)) {\n    EvrRtxTimerIsRunning(timer, 0U);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return 0U;\n  }\n\n  if (timer->state == osRtxTimerRunning) {\n    EvrRtxTimerIsRunning(timer, 1U);\n    is_running = 1U;\n  } else {\n    EvrRtxTimerIsRunning(timer, 0U);\n    is_running = 0;\n  }\n\n  return is_running;\n}\n\n/// Delete a timer.\n/// \\note API identical to osTimerDelete\nstatic osStatus_t svcRtxTimerDelete (osTimerId_t timer_id) {\n  os_timer_t        *timer = osRtxTimerId(timer_id);\n#ifdef RTX_SAFETY_CLASS\n  const os_thread_t *thread;\n#endif\n\n  // Check parameters\n  if (!IsTimerPtrValid(timer) || (timer->id != osRtxIdTimer)) {\n    EvrRtxTimerError(timer, (int32_t)osErrorParameter);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorParameter;\n  }\n\n#ifdef RTX_SAFETY_CLASS\n  // Check running thread safety class\n  thread = osRtxThreadGetRunning();\n  if ((thread != NULL) &&\n      ((thread->attr >> osRtxAttrClass_Pos) < (timer->attr >> osRtxAttrClass_Pos))) {\n    EvrRtxTimerError(timer, (int32_t)osErrorSafetyClass);\n    //lint -e{904} \"Return statement before end of function\" [MISRA Note 1]\n    return osErrorSafetyClass;\n  }\n#endif\n\n  if (timer->state == osRtxTimerRunning) {\n    TimerRemove(timer);\n  }\n\n  osRtxTimerDestroy(timer);\n\n  return osOK;\n}\n\n//  Service Calls definitions\n//lint ++flb \"Library Begin\" [MISRA Note 11]\nSVC0_4(TimerNew,       osTimerId_t,  osTimerFunc_t, osTimerType_t, void *, const osTimerAttr_t *)\nSVC0_1(TimerGetName,   const char *, osTimerId_t)\nSVC0_2(TimerStart,     osStatus_t,   osTimerId_t, uint32_t)\nSVC0_1(TimerStop,      osStatus_t,   osTimerId_t)\nSVC0_1(TimerIsRunning, uint32_t,     osTimerId_t)\nSVC0_1(TimerDelete,    osStatus_t,   osTimerId_t)\n//lint --flb \"Library End\"\n\n\n//  ==== Public API ====\n\n/// Create and Initialize a timer.\nosTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {\n  osTimerId_t timer_id;\n\n  EvrRtxTimerNew(func, type, argument, attr);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxTimerError(NULL, (int32_t)osErrorISR);\n    timer_id = NULL;\n  } else {\n    timer_id = __svcTimerNew(func, type, argument, attr);\n  }\n  return timer_id;\n}\n\n/// Get name of a timer.\nconst char *osTimerGetName (osTimerId_t timer_id) {\n  const char *name;\n\n  if (IsException() || IsIrqMasked()) {\n    name = svcRtxTimerGetName(timer_id);\n  } else {\n    name =  __svcTimerGetName(timer_id);\n  }\n  return name;\n}\n\n/// Start or restart a timer.\nosStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {\n  osStatus_t status;\n\n  EvrRtxTimerStart(timer_id, ticks);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxTimerError(timer_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcTimerStart(timer_id, ticks);\n  }\n  return status;\n}\n\n/// Stop a timer.\nosStatus_t osTimerStop (osTimerId_t timer_id) {\n  osStatus_t status;\n\n  EvrRtxTimerStop(timer_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxTimerError(timer_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcTimerStop(timer_id);\n  }\n  return status;\n}\n\n/// Check if a timer is running.\nuint32_t osTimerIsRunning (osTimerId_t timer_id) {\n  uint32_t is_running;\n\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxTimerIsRunning(timer_id, 0U);\n    is_running = 0U;\n  } else {\n    is_running = __svcTimerIsRunning(timer_id);\n  }\n  return is_running;\n}\n\n/// Delete a timer.\nosStatus_t osTimerDelete (osTimerId_t timer_id) {\n  osStatus_t status;\n\n  EvrRtxTimerDelete(timer_id);\n  if (IsException() || IsIrqMasked()) {\n    EvrRtxTimerError(timer_id, (int32_t)osErrorISR);\n    status = osErrorISR;\n  } else {\n    status = __svcTimerDelete(timer_id);\n  }\n  return status;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Template/Events.c",
    "content": "#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *  Event Flags creation & usage\n *---------------------------------------------------------------------------*/\n \n#define FLAGS_MSK1 0x00000001U\n \nosEventFlagsId_t evt_id;                        // event flasg id\n \nosThreadId_t tid_Thread_EventSender;            // thread id 1\nosThreadId_t tid_Thread_EventReceiver;          // thread id 2\n \nvoid Thread_EventSender   (void *argument);     // thread function 1\nvoid Thread_EventReceiver (void *argument);     // thread function 2\n \nint Init_Events (void) {\n \n  evt_id = osEventFlagsNew(NULL);\n  if (evt_id == NULL) {\n    ; // Event Flags object not created, handle failure\n  }\n \n  tid_Thread_EventSender = osThreadNew(Thread_EventSender, NULL, NULL);\n  if (tid_Thread_EventSender == NULL) {\n    return(-1);\n  }\n  tid_Thread_EventReceiver = osThreadNew(Thread_EventReceiver, NULL, NULL);\n  if (tid_Thread_EventReceiver == NULL) {\n    return(-1);\n  }\n\n  return(0);\n}\n \nvoid Thread_EventSender (void *argument) {\n \n  while (1) {    \n    osEventFlagsSet(evt_id, FLAGS_MSK1);\n    osThreadYield();                            // suspend thread\n  }\n}\n \nvoid Thread_EventReceiver (void *argument) {\n  uint32_t flags;\n \n  while (1) {\n    flags = osEventFlagsWait(evt_id, FLAGS_MSK1, osFlagsWaitAny, osWaitForever);\n    //handle event\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Template/MemPool.c",
    "content": "#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *      Memory Pool creation & usage\n *---------------------------------------------------------------------------*/\n \n#define MEMPOOL_OBJECTS 16                      // number of Memory Pool Objects\n \ntypedef struct {                                // object data type\n  uint8_t Buf[32];\n  uint8_t Idx;\n} MEM_BLOCK_t;\n \nosMemoryPoolId_t mpid_MemPool;                  // memory pool id\n \nosThreadId_t tid_Thread_MemPool;                // thread id\n \nvoid Thread_MemPool (void *argument);           // thread function\n \nint Init_MemPool (void) {\n \n  mpid_MemPool = osMemoryPoolNew(MEMPOOL_OBJECTS, sizeof(MEM_BLOCK_t), NULL);\n  if (mpid_MemPool == NULL) {\n    ; // MemPool object not created, handle failure\n  }\n \n  tid_Thread_MemPool = osThreadNew(Thread_MemPool, NULL, NULL);\n  if (tid_Thread_MemPool == NULL) {\n    return(-1);\n  }\n \n  return(0);\n}\n \nvoid Thread_MemPool (void *argument) {\n  MEM_BLOCK_t *pMem;\n  osStatus_t status;\n \n  while (1) {\n    ; // Insert thread code here...\n \n    pMem = (MEM_BLOCK_t *)osMemoryPoolAlloc(mpid_MemPool, 0U);  // get Mem Block\n    if (pMem != NULL) {                                         // Mem Block was available\n      pMem->Buf[0] = 0x55U;                                     // do some work...\n      pMem->Idx    = 0U;\n \n      status = osMemoryPoolFree(mpid_MemPool, pMem);            // free mem block\n      switch (status)  {\n        case osOK:\n          break;\n        case osErrorParameter:\n          break;\n        case osErrorNoMemory:\n          break;\n        default:\n          break;\n      }\n    }\n \n    osThreadYield();                                            // suspend thread\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Template/MsgQueue.c",
    "content": "#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *      Message Queue creation & usage\n *---------------------------------------------------------------------------*/\n \n#define MSGQUEUE_OBJECTS 16                     // number of Message Queue Objects\n \ntypedef struct {                                // object data type\n  uint8_t Buf[32];\n  uint8_t Idx;\n} MSGQUEUE_OBJ_t;\n \nosMessageQueueId_t mid_MsgQueue;                // message queue id\n \nosThreadId_t tid_Thread_MsgQueue1;              // thread id 1\nosThreadId_t tid_Thread_MsgQueue2;              // thread id 2\n \nvoid Thread_MsgQueue1 (void *argument);         // thread function 1\nvoid Thread_MsgQueue2 (void *argument);         // thread function 2\n \nint Init_MsgQueue (void) {\n \n  mid_MsgQueue = osMessageQueueNew(MSGQUEUE_OBJECTS, sizeof(MSGQUEUE_OBJ_t), NULL);\n  if (mid_MsgQueue == NULL) {\n    ; // Message Queue object not created, handle failure\n  }\n \n  tid_Thread_MsgQueue1 = osThreadNew(Thread_MsgQueue1, NULL, NULL);\n  if (tid_Thread_MsgQueue1 == NULL) {\n    return(-1);\n  }\n  tid_Thread_MsgQueue2 = osThreadNew(Thread_MsgQueue2, NULL, NULL);\n  if (tid_Thread_MsgQueue2 == NULL) {\n    return(-1);\n  }\n \n  return(0);\n}\n \nvoid Thread_MsgQueue1 (void *argument) {\n  MSGQUEUE_OBJ_t msg;\n \n  while (1) {\n    ; // Insert thread code here...\n    msg.Buf[0] = 0x55U;                                         // do some work...\n    msg.Idx    = 0U;\n    osMessageQueuePut(mid_MsgQueue, &msg, 0U, 0U);\n    osThreadYield();                                            // suspend thread\n  }\n}\n \nvoid Thread_MsgQueue2 (void *argument) {\n  MSGQUEUE_OBJ_t msg;\n  osStatus_t status;\n\n  while (1) {\n    ; // Insert thread code here...\n    status = osMessageQueueGet(mid_MsgQueue, &msg, NULL, 0U);   // wait for message\n    if (status == osOK) {\n      ; // process data\n    }\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Template/Mutex.c",
    "content": "#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *      Mutex creation & usage\n *---------------------------------------------------------------------------*/\n \nosMutexId_t mid_Mutex;                          // mutex id\n \nosThreadId_t tid_Thread_Mutex;                  // thread id\n \nvoid Thread_Mutex (void *argument);             // thread function\n \nint Init_Mutex (void) {\n \n  mid_Mutex = osMutexNew(NULL);\n  if (mid_Mutex == NULL) {\n    ; // Mutex object not created, handle failure\n  }\n \n  tid_Thread_Mutex = osThreadNew(Thread_Mutex, NULL, NULL);\n  if (tid_Thread_Mutex == NULL) {\n    return(-1);\n  }\n \n  return(0);\n}\n \nvoid Thread_Mutex (void *argument) {\n  osStatus_t status;\n \n  while (1) {\n    ; // Insert thread code here...\n \n    status = osMutexAcquire(mid_Mutex, 0U);\n    switch (status) {\n      case osOK:\n        ; // Use protected code here...\n        osMutexRelease(mid_Mutex);\n        break;\n      case osErrorResource:\n        break;\n      case osErrorParameter:\n        break;\n      case osErrorISR:\n        break;\n      default:\n        break;\n    }\n \n    osThreadYield();                            // suspend thread\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Template/Semaphore.c",
    "content": "#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *      Semaphore creation & usage\n *---------------------------------------------------------------------------*/\n \nosSemaphoreId_t sid_Semaphore;                  // semaphore id\n \nosThreadId_t tid_Thread_Semaphore;              // thread id\n \nvoid Thread_Semaphore (void *argument);         // thread function\n \nint Init_Semaphore (void) {\n \n  sid_Semaphore = osSemaphoreNew(2U, 2U, NULL);\n  if (sid_Semaphore == NULL) {\n    ; // Semaphore object not created, handle failure\n  }\n \n  tid_Thread_Semaphore = osThreadNew(Thread_Semaphore, NULL, NULL);\n  if (tid_Thread_Semaphore == NULL) {\n    return(-1);\n  }\n \n  return(0);\n}\n \nvoid Thread_Semaphore (void *argument) {\n  int32_t val;\n \n  while (1) {\n    ; // Insert thread code here...\n \n    val = osSemaphoreAcquire(sid_Semaphore, 10U);       // wait 10 mSec\n    switch (val) {\n      case osOK:\n        ; // Use protected code here...\n        osSemaphoreRelease(sid_Semaphore);              // return a token back to a semaphore\n        break;\n      case osErrorResource:\n        break;\n      case osErrorParameter:\n        break;\n      default:\n        break;\n    }\n \n    osThreadYield();                                    // suspend thread\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Template/Thread.c",
    "content": "#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *      Thread 1 'Thread_Name': Sample thread\n *---------------------------------------------------------------------------*/\n \nosThreadId_t tid_Thread;                        // thread id\n \nvoid Thread (void *argument);                   // thread function\n \nint Init_Thread (void) {\n \n  tid_Thread = osThreadNew(Thread, NULL, NULL);\n  if (tid_Thread == NULL) {\n    return(-1);\n  }\n \n  return(0);\n}\n \nvoid Thread (void *argument) {\n \n  while (1) {\n    ; // Insert thread code here...\n    osThreadYield();                            // suspend thread\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Template/Timer.c",
    "content": "#include \"cmsis_os2.h\"                          // CMSIS RTOS header file\n \n/*----------------------------------------------------------------------------\n *      Timer: Sample timer functions\n *---------------------------------------------------------------------------*/\n \n/*----- One-Shoot Timer Example -----*/\nosTimerId_t tim_id1;                            // timer id\nstatic uint32_t exec1;                          // argument for the timer call back function\n\n// One-Shoot Timer Function\nstatic void Timer1_Callback (void const *arg) {\n  // add user code here\n}\n \n/*----- Periodic Timer Example -----*/\nosTimerId_t tim_id2;                            // timer id\nstatic uint32_t exec2;                          // argument for the timer call back function\n \n// Periodic Timer Function\nstatic void Timer2_Callback (void const *arg) {\n  // add user code here\n}\n \n// Example: Create and Start timers\nint Init_Timers (void) {\n  osStatus_t status;                            // function return status\n \n  // Create one-shoot timer\n  exec1 = 1U;\n  tim_id1 = osTimerNew((osTimerFunc_t)&Timer1_Callback, osTimerOnce, &exec1, NULL);\n  if (tim_id1 != NULL) {  // One-shot timer created\n    // start timer with delay 100ms\n    status = osTimerStart(tim_id1, 100U); \n    if (status != osOK) {\n      return -1;\n    }\n  }\n \n  // Create periodic timer\n  exec2 = 2U;\n  tim_id2 = osTimerNew((osTimerFunc_t)&Timer2_Callback, osTimerPeriodic, &exec2, NULL);\n  if (tim_id2 != NULL) {  // Periodic timer created\n    // start timer with periodic 1000ms interval\n    status = osTimerStart(tim_id2, 1000U);            \n    if (status != osOK) {\n      return -1;\n    }\n  }\n  return NULL;\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Template/main.c",
    "content": "/*----------------------------------------------------------------------------\n * CMSIS-RTOS 'main' function template\n *---------------------------------------------------------------------------*/\n \n#include \"RTE_Components.h\"\n#include  CMSIS_device_header\n#include \"cmsis_os2.h\"\n \n/*----------------------------------------------------------------------------\n * Application main thread\n *---------------------------------------------------------------------------*/\n__NO_RETURN static void app_main (void *argument) {\n  (void)argument;\n  // ...\n  for (;;) {}\n}\n \nint main (void) {\n \n  // System Initialization\n  SystemCoreClockUpdate();\n  // ...\n \n  osKernelInitialize();                 // Initialize CMSIS-RTOS\n  osThreadNew(app_main, NULL, NULL);    // Create application main thread\n  osKernelStart();                      // Start thread execution\n  for (;;) {}\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/RTX/Template/svc_user.c",
    "content": "/*\n * Copyright (c) 2013-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * -----------------------------------------------------------------------------\n *\n * Project:     CMSIS-RTOS RTX\n * Title:       SVC User Table\n *\n * -----------------------------------------------------------------------------\n */\n\n#define USER_SVC_COUNT  0       // Number of user SVC functions\n\nextern void * const osRtxUserSVC[1+USER_SVC_COUNT];\n       void * const osRtxUserSVC[1+USER_SVC_COUNT] = {\n  (void *)USER_SVC_COUNT,\n//(void *)user_function1,\n// ...\n};\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/Source/os_systick.c",
    "content": "/**************************************************************************//**\n * @file     os_systick.c\n * @brief    CMSIS OS Tick SysTick implementation\n * @version  V1.0.4\n * @date     20. January 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2023 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"os_tick.h\"\n\n//lint -emacro((923,9078),SCB,SysTick) \"cast from unsigned long to pointer\"\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n#ifdef  SysTick\n\n#ifndef SYSTICK_IRQ_PRIORITY\n#define SYSTICK_IRQ_PRIORITY    0xFFU\n#endif\n\nstatic uint8_t PendST __attribute__((section(\".bss.os\")));\n\n// Setup OS Tick.\n__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {\n  uint32_t load;\n  (void)handler;\n\n  if (freq == 0U) {\n    //lint -e{904} \"Return statement before end of function\"\n    return (-1);\n  }\n\n  load = (SystemCoreClock / freq) - 1U;\n  if (load > 0x00FFFFFFU) {\n    //lint -e{904} \"Return statement before end of function\"\n    return (-1);\n  }\n\n  // Set SysTick Interrupt Priority\n#if   ((defined(__ARM_ARCH_8M_MAIN__)   && (__ARM_ARCH_8M_MAIN__   != 0)) || \\\n       (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \\\n       (defined(__CORTEX_M)             && (__CORTEX_M             == 7U)))\n  SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY;\n#elif  (defined(__ARM_ARCH_8M_BASE__)   && (__ARM_ARCH_8M_BASE__   != 0))\n  SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);\n#elif ((defined(__ARM_ARCH_7M__)        && (__ARM_ARCH_7M__        != 0)) || \\\n       (defined(__ARM_ARCH_7EM__)       && (__ARM_ARCH_7EM__       != 0)))\n  SCB->SHP[11]  = SYSTICK_IRQ_PRIORITY;\n#elif  (defined(__ARM_ARCH_6M__)        && (__ARM_ARCH_6M__        != 0))\n  SCB->SHP[1]  |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);\n#else\n#error \"Unknown ARM Core!\"\n#endif\n\n  SysTick->CTRL =  SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk;\n  SysTick->LOAD =  load;\n  SysTick->VAL  =  0U;\n\n  PendST = 0U;\n\n  return (0);\n}\n\n/// Enable OS Tick.\n__WEAK void OS_Tick_Enable (void) {\n\n  if (PendST != 0U) {\n    PendST = 0U;\n    SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;\n  }\n\n  SysTick->CTRL |=  SysTick_CTRL_ENABLE_Msk;\n}\n\n/// Disable OS Tick.\n__WEAK void OS_Tick_Disable (void) {\n\n  SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;\n\n  if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) {\n    SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;\n    PendST = 1U;\n  }\n}\n\n// Acknowledge OS Tick IRQ.\n__WEAK void OS_Tick_AcknowledgeIRQ (void) {\n  (void)SysTick->CTRL;\n}\n\n// Get OS Tick IRQ number.\n__WEAK int32_t  OS_Tick_GetIRQn (void) {\n  return ((int32_t)SysTick_IRQn);\n}\n\n// Get OS Tick clock.\n__WEAK uint32_t OS_Tick_GetClock (void) {\n  return (SystemCoreClock);\n}\n\n// Get OS Tick interval.\n__WEAK uint32_t OS_Tick_GetInterval (void) {\n  return (SysTick->LOAD + 1U);\n}\n\n// Get OS Tick count value.\n__WEAK uint32_t OS_Tick_GetCount (void) {\n  uint32_t val;\n  uint32_t count;\n\n  val = SysTick->VAL;\n  if (val != 0U) {\n    count = (SysTick->LOAD - val) + 1U;\n  } else {\n    count = 0U;\n  }\n\n  return (count);\n}\n\n// Get OS Tick overflow status.\n__WEAK uint32_t OS_Tick_GetOverflow (void) {\n  return ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) >> SCB_ICSR_PENDSTSET_Pos);\n}\n\n#endif  // SysTick\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/Source/os_tick_gtim.c",
    "content": "/**************************************************************************//**\n * @file     os_tick_gtim.c\n * @brief    CMSIS OS Tick implementation for Generic Timer\n * @version  V1.0.1\n * @date     24. November 2017\n ******************************************************************************/\n/*\n * Copyright (c) 2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"os_tick.h\"\n#include \"irq_ctrl.h\"\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n#ifndef GTIM_IRQ_PRIORITY\n#define GTIM_IRQ_PRIORITY           0xFFU\n#endif\n\n#ifndef GTIM_IRQ_NUM\n#define GTIM_IRQ_NUM                SecurePhyTimer_IRQn\n#endif\n\n// Timer interrupt pending flag\nstatic uint8_t GTIM_PendIRQ;\n\n// Timer tick frequency\nstatic uint32_t GTIM_Clock;\n\n// Timer load value\nstatic uint32_t GTIM_Load;\n\n// Setup OS Tick.\nint32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {\n  uint32_t prio, bits;\n\n  if (freq == 0U) {\n    return (-1);\n  }\n\n  GTIM_PendIRQ = 0U;\n\n  // Get timer clock\n#ifdef SCTR_BASE\n  GTIM_Clock = *(uint32_t*)(SCTR_BASE+0x20);\n#else\n  // FVP REFCLK CNTControl 100MHz\n  GTIM_Clock = 100000000UL;\n#endif\n\n  PL1_SetCounterFrequency(GTIM_Clock);\n\n  // Calculate load value\n  GTIM_Load = (GTIM_Clock / freq) - 1U;\n\n  // Disable Generic Timer and set load value\n  PL1_SetControl(0U);\n  PL1_SetLoadValue(GTIM_Load);\n\n  // Disable corresponding IRQ\n  IRQ_Disable(GTIM_IRQ_NUM);\n  IRQ_ClearPending(GTIM_IRQ_NUM);\n\n  // Determine number of implemented priority bits\n  IRQ_SetPriority(GTIM_IRQ_NUM, 0xFFU);\n\n  prio = IRQ_GetPriority(GTIM_IRQ_NUM);\n\n  // At least bits [7:4] must be implemented\n  if ((prio & 0xF0U) == 0U) {\n    return (-1);\n  }\n\n  for (bits = 0; bits < 4; bits++) {\n    if ((prio & 0x01) != 0) {\n      break;\n    }\n    prio >>= 1;\n  }\n  \n  // Adjust configured priority to the number of implemented priority bits\n  prio = (GTIM_IRQ_PRIORITY << bits) & 0xFFUL;\n\n  // Set Private Timer interrupt priority\n  IRQ_SetPriority(GTIM_IRQ_NUM, prio-1U);\n\n  // Set edge-triggered IRQ\n  IRQ_SetMode(GTIM_IRQ_NUM, IRQ_MODE_TRIG_EDGE);\n\n  // Register tick interrupt handler function\n  IRQ_SetHandler(GTIM_IRQ_NUM, handler);\n\n  // Enable corresponding interrupt\n  IRQ_Enable(GTIM_IRQ_NUM);\n\n  // Enable system counter and timer control\n#ifdef SCTR_BASE\n  *(uint32_t*)SCTR_BASE |= 3U;\n#endif\n\n  // Enable timer control\n  PL1_SetControl(1U);\n\n  return (0);\n}\n\n/// Enable OS Tick.\nvoid OS_Tick_Enable (void) {\n  uint32_t ctrl;\n\n  // Set pending interrupt if flag set\n  if (GTIM_PendIRQ != 0U) {\n    GTIM_PendIRQ = 0U;\n    IRQ_SetPending (GTIM_IRQ_NUM);\n  }\n\n  // Start the Private Timer\n  ctrl = PL1_GetControl();\n  // Set bit: Timer enable\n  ctrl |= 1U;\n  PL1_SetControl(ctrl);\n}\n\n/// Disable OS Tick.\nvoid OS_Tick_Disable (void) {\n  uint32_t ctrl;\n\n  // Stop the Private Timer\n  ctrl = PL1_GetControl();\n  // Clear bit: Timer enable\n  ctrl &= ~1U;\n  PL1_SetControl(ctrl);\n\n  // Remember pending interrupt flag\n  if (IRQ_GetPending(GTIM_IRQ_NUM) != 0) {\n    IRQ_ClearPending(GTIM_IRQ_NUM);\n    GTIM_PendIRQ = 1U;\n  }\n}\n\n// Acknowledge OS Tick IRQ.\nvoid OS_Tick_AcknowledgeIRQ (void) {\n  IRQ_ClearPending (GTIM_IRQ_NUM);\n  PL1_SetLoadValue(GTIM_Load);\n}\n\n// Get OS Tick IRQ number.\nint32_t  OS_Tick_GetIRQn (void) {\n  return (GTIM_IRQ_NUM);\n}\n\n// Get OS Tick clock.\nuint32_t OS_Tick_GetClock (void) {\n  return (GTIM_Clock);\n}\n\n// Get OS Tick interval.\nuint32_t OS_Tick_GetInterval (void) {\n  return (GTIM_Load + 1U);\n}\n\n// Get OS Tick count value.\nuint32_t OS_Tick_GetCount (void) {\n  return (GTIM_Load - PL1_GetCurrentValue());\n}\n\n// Get OS Tick overflow status.\nuint32_t OS_Tick_GetOverflow (void) {\n  CNTP_CTL_Type cntp_ctl;\n  cntp_ctl.w = PL1_GetControl();\n  return (cntp_ctl.b.ISTATUS);\n}\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/Source/os_tick_ptim.c",
    "content": "/**************************************************************************//**\n * @file     os_tick_ptim.c\n * @brief    CMSIS OS Tick implementation for Private Timer\n * @version  V1.0.2\n * @date     02. March 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n\n#if defined(PTIM)\n\n#include \"os_tick.h\"\n#include \"irq_ctrl.h\"\n\n#ifndef PTIM_IRQ_PRIORITY\n#define PTIM_IRQ_PRIORITY           0xFFU\n#endif\n\nstatic uint8_t PTIM_PendIRQ;        // Timer interrupt pending flag\n\n// Setup OS Tick.\nint32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {\n  uint32_t load;\n  uint32_t prio;\n  uint32_t bits;\n\n  if (freq == 0U) {\n    return (-1);\n  }\n\n  PTIM_PendIRQ = 0U;\n\n  // Private Timer runs with the system frequency\n  load = (SystemCoreClock / freq) - 1U;\n\n  // Disable Private Timer and set load value\n  PTIM_SetControl   (0U);\n  PTIM_SetLoadValue (load);\n\n  // Disable corresponding IRQ\n  IRQ_Disable     (PrivTimer_IRQn);\n  IRQ_ClearPending(PrivTimer_IRQn);\n\n  // Determine number of implemented priority bits\n  IRQ_SetPriority (PrivTimer_IRQn, 0xFFU);\n\n  prio = IRQ_GetPriority (PrivTimer_IRQn);\n\n  // At least bits [7:4] must be implemented\n  if ((prio & 0xF0U) == 0U) {\n    return (-1);\n  }\n\n  for (bits = 0; bits < 4; bits++) {\n    if ((prio & 0x01) != 0) {\n      break;\n    }\n    prio >>= 1;\n  }\n\n  // Adjust configured priority to the number of implemented priority bits\n  prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL;\n\n  // Set Private Timer interrupt priority\n  IRQ_SetPriority(PrivTimer_IRQn, prio-1U);\n\n  // Set edge-triggered IRQ\n  IRQ_SetMode(PrivTimer_IRQn, IRQ_MODE_TRIG_EDGE);\n\n  // Register tick interrupt handler function\n  IRQ_SetHandler(PrivTimer_IRQn, handler);\n\n  // Enable corresponding interrupt\n  IRQ_Enable (PrivTimer_IRQn);\n\n  // Set bits: IRQ enable and Auto reload\n  PTIM_SetControl (0x06U);\n\n  return (0);\n}\n\n/// Enable OS Tick.\nvoid OS_Tick_Enable (void) {\n  uint32_t ctrl;\n\n  // Set pending interrupt if flag set\n  if (PTIM_PendIRQ != 0U) {\n    PTIM_PendIRQ = 0U;\n    IRQ_SetPending (PrivTimer_IRQn);\n  }\n\n  // Start the Private Timer\n  ctrl  = PTIM_GetControl();\n  // Set bit: Timer enable\n  ctrl |= 1U;\n  PTIM_SetControl (ctrl);\n}\n\n/// Disable OS Tick.\nvoid OS_Tick_Disable (void) {\n  uint32_t ctrl;\n\n  // Stop the Private Timer\n  ctrl  = PTIM_GetControl();\n  // Clear bit: Timer enable\n  ctrl &= ~1U;\n  PTIM_SetControl (ctrl);\n\n  // Remember pending interrupt flag\n  if (IRQ_GetPending(PrivTimer_IRQn) != 0) {\n    IRQ_ClearPending (PrivTimer_IRQn);\n    PTIM_PendIRQ = 1U;\n  }\n}\n\n// Acknowledge OS Tick IRQ.\nvoid OS_Tick_AcknowledgeIRQ (void) {\n  PTIM_ClearEventFlag();\n}\n\n// Get OS Tick IRQ number.\nint32_t  OS_Tick_GetIRQn (void) {\n  return (PrivTimer_IRQn);\n}\n\n// Get OS Tick clock.\nuint32_t OS_Tick_GetClock (void) {\n  return (SystemCoreClock);\n}\n\n// Get OS Tick interval.\nuint32_t OS_Tick_GetInterval (void) {\n  return (PTIM_GetLoadValue() + 1U);\n}\n\n// Get OS Tick count value.\nuint32_t OS_Tick_GetCount (void) {\n  uint32_t load = PTIM_GetLoadValue();\n  return  (load - PTIM_GetCurrentValue());\n}\n\n// Get OS Tick overflow status.\nuint32_t OS_Tick_GetOverflow (void) {\n  return (PTIM->ISR & 1);\n}\n\n#endif  // PTIM\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/Template/cmsis_os.h",
    "content": "/*\n * Copyright (c) 2013-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        18. June 2018\n * $Revision:    V2.1.3\n *\n * Project:      CMSIS-RTOS API\n * Title:        cmsis_os.h template header file\n *\n * Version 0.02\n *    Initial Proposal Phase\n * Version 0.03\n *    osKernelStart added, optional feature: main started as thread\n *    osSemaphores have standard behavior\n *    osTimerCreate does not start the timer, added osTimerStart\n *    osThreadPass is renamed to osThreadYield\n * Version 1.01\n *    Support for C++ interface\n *     - const attribute removed from the osXxxxDef_t typedefs\n *     - const attribute added to the osXxxxDef macros\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\n *    Added: osKernelInitialize\n * Version 1.02\n *    Control functions for short timeouts in microsecond resolution:\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\n *    Removed: osSignalGet \n * Version 2.0.0\n *    OS objects creation without macros (dynamic creation and resource allocation):\n *     - added: osXxxxNew functions which replace osXxxxCreate\n *     - added: osXxxxAttr_t structures\n *     - deprecated: osXxxxCreate functions, osXxxxDef_t structures\n *     - deprecated: osXxxxDef and osXxxx macros\n *    osStatus codes simplified and renamed to osStatus_t\n *    osEvent return structure deprecated\n *    Kernel:\n *     - added: osKernelInfo_t and osKernelGetInfo\n *     - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)\n *     - added: osKernelLock, osKernelUnlock\n *     - added: osKernelSuspend, osKernelResume\n *     - added: osKernelGetTickCount, osKernelGetTickFreq\n *     - renamed osKernelSysTick to osKernelGetSysTimerCount\n *     - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq\n *     - deprecated osKernelSysTickMicroSec\n *    Thread:\n *     - extended number of thread priorities\n *     - renamed osPrioriry to osPrioriry_t\n *     - replaced osThreadCreate with osThreadNew\n *     - added: osThreadGetName\n *     - added: osThreadState_t and osThreadGetState\n *     - added: osThreadGetStackSize, osThreadGetStackSpace\n *     - added: osThreadSuspend, osThreadResume\n *     - added: osThreadJoin, osThreadDetach, osThreadExit\n *     - added: osThreadGetCount, osThreadEnumerate\n *     - added: Thread Flags (moved from Signals) \n *    Signals:\n *     - renamed osSignals to osThreadFlags (moved to Thread Flags)\n *     - changed return value of Set/Clear/Wait functions\n *     - Clear function limited to current running thread\n *     - extended Wait function (options)\n *     - added: osThreadFlagsGet\n *    Event Flags:\n *     - added new independent object for handling Event Flags\n *    Delay and Wait functions:\n *     - added: osDelayUntil\n *     - deprecated: osWait\n *    Timer:\n *     - replaced osTimerCreate with osTimerNew\n *     - added: osTimerGetName, osTimerIsRunning\n *    Mutex:\n *     - extended: attributes (Recursive, Priority Inherit, Robust)\n *     - replaced osMutexCreate with osMutexNew\n *     - renamed osMutexWait to osMutexAcquire\n *     - added: osMutexGetName, osMutexGetOwner\n *    Semaphore:\n *     - extended: maximum and initial token count\n *     - replaced osSemaphoreCreate with osSemaphoreNew\n *     - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)\n *     - added: osSemaphoreGetName, osSemaphoreGetCount\n *    Memory Pool:\n *     - using osMemoryPool prefix instead of osPool\n *     - replaced osPoolCreate with osMemoryPoolNew\n *     - extended osMemoryPoolAlloc (timeout)\n *     - added: osMemoryPoolGetName\n *     - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize\n *     - added: osMemoryPoolGetCount, osMemoryPoolGetSpace\n *     - added: osMemoryPoolDelete\n *     - deprecated: osPoolCAlloc\n *    Message Queue:\n *     - extended: fixed size message instead of a single 32-bit value\n *     - using osMessageQueue prefix instead of osMessage\n *     - replaced osMessageCreate with osMessageQueueNew\n *     - updated: osMessageQueuePut, osMessageQueueGet\n *     - added: osMessageQueueGetName\n *     - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize\n *     - added: osMessageQueueGetCount, osMessageQueueGetSpace\n *     - added: osMessageQueueReset, osMessageQueueDelete\n *    Mail Queue: \n *     - deprecated (superseded by extended Message Queue functionality)\n * Version 2.1.0\n *    Support for critical and uncritical sections (nesting safe):\n *    - updated: osKernelLock, osKernelUnlock\n *    - added: osKernelRestoreLock\n *    Updated Thread and Event Flags:\n *    - changed flags parameter and return type from int32_t to uint32_t\n * Version 2.1.1\n *    Additional functions allowed to be called from Interrupt Service Routines:\n *    - osKernelGetTickCount, osKernelGetTickFreq\n *    Changed Kernel Tick type to uint32_t:\n *    - updated: osKernelGetTickCount, osDelayUntil\n * Version 2.1.2\n *    Additional functions allowed to be called from Interrupt Service Routines:\n *    - osKernelGetInfo, osKernelGetState\n * Version 2.1.3\n *    Additional functions allowed to be called from Interrupt Service Routines:\n *    - osThreadGetId\n *---------------------------------------------------------------------------*/\n \n#ifndef CMSIS_OS_H_\n#define CMSIS_OS_H_\n \n/// \\b osCMSIS identifies the CMSIS-RTOS API version.\n#define osCMSIS             0x20001U    ///< API version (main[31:16].sub[15:0])\n \n/// \\note CAN BE CHANGED: \\b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.\n#define osCMSIS_KERNEL      0x10000U    ///< RTOS identification and version (main[31:16].sub[15:0])\n \n/// \\note CAN BE CHANGED: \\b osKernelSystemId identifies the underlying RTOS kernel.\n#define osKernelSystemId \"KERNEL V1.0\"  ///< RTOS identification string\n \n/// \\note CAN BE CHANGED: \\b osFeature_xxx identifies RTOS features.\n#define osFeature_MainThread  0         ///< main thread      1=main can be thread, 0=not available\n#define osFeature_Signals     16U       ///< maximum number of Signal Flags available per thread\n#define osFeature_Semaphore   65535U    ///< maximum count for \\ref osSemaphoreCreate function\n#define osFeature_Wait        0         ///< osWait function: 1=available, 0=not available\n#define osFeature_SysTick     1         ///< osKernelSysTick functions: 1=available, 0=not available\n#define osFeature_Pool        1         ///< Memory Pools:    1=available, 0=not available\n#define osFeature_MessageQ    1         ///< Message Queues:  1=available, 0=not available\n#define osFeature_MailQ       1         ///< Mail Queues:     1=available, 0=not available\n \n#if (osCMSIS >= 0x20000U)\n#include \"cmsis_os2.h\"\n#else\n#include <stdint.h>\n#include <stddef.h>\n#endif\n \n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n \n \n// ==== Enumerations, structures, defines ====\n \n/// Priority values.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osPriorityIdle          = -3,         ///< Priority: idle (lowest)\n  osPriorityLow           = -2,         ///< Priority: low\n  osPriorityBelowNormal   = -1,         ///< Priority: below normal\n  osPriorityNormal        =  0,         ///< Priority: normal (default)\n  osPriorityAboveNormal   = +1,         ///< Priority: above normal\n  osPriorityHigh          = +2,         ///< Priority: high\n  osPriorityRealtime      = +3,         ///< Priority: realtime (highest)\n  osPriorityError         = 0x84,       ///< System cannot determine priority or illegal priority.\n  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osPriority;\n#else\n#define osPriority osPriority_t\n#endif\n\n/// Entry point of a thread.\ntypedef void (*os_pthread) (void const *argument);\n \n/// Entry point of a timer call back function.\ntypedef void (*os_ptimer) (void const *argument);\n \n/// Timer type.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osTimerOnce             = 0,          ///< One-shot timer.\n  osTimerPeriodic         = 1           ///< Repeating timer.\n} os_timer_type;\n#else\n#define os_timer_type osTimerType_t\n#endif\n \n/// Timeout value.\n#define osWaitForever       0xFFFFFFFFU ///< Wait forever timeout value.\n \n/// Status code values returned by CMSIS-RTOS functions.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osOK                    =    0,       ///< Function completed; no error or event occurred.\n  osEventSignal           = 0x08,       ///< Function completed; signal event occurred.\n  osEventMessage          = 0x10,       ///< Function completed; message event occurred.\n  osEventMail             = 0x20,       ///< Function completed; mail event occurred.\n  osEventTimeout          = 0x40,       ///< Function completed; timeout occurred.\n  osErrorParameter        = 0x80,       ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.\n  osErrorResource         = 0x81,       ///< Resource not available: a specified resource was not available.\n  osErrorTimeoutResource  = 0xC1,       ///< Resource not available within given time: a specified resource was not available within the timeout period.\n  osErrorISR              = 0x82,       ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osErrorISRRecursive     = 0x83,       ///< Function called multiple times from ISR with same object.\n  osErrorPriority         = 0x84,       ///< System cannot determine priority or thread has illegal priority.\n  osErrorNoMemory         = 0x85,       ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorValue            = 0x86,       ///< Value of a parameter is out of range.\n  osErrorOS               = 0xFF,       ///< Unspecified RTOS error: run-time error but no other error message fits.\n  osStatusReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osStatus;\n#else\ntypedef int32_t                  osStatus;\n#define osEventSignal           (0x08)\n#define osEventMessage          (0x10)\n#define osEventMail             (0x20)\n#define osEventTimeout          (0x40)\n#define osErrorOS               osError\n#define osErrorTimeoutResource  osErrorTimeout\n#define osErrorISRRecursive     (-126)\n#define osErrorValue            (-127)\n#define osErrorPriority         (-128)\n#endif\n \n \n// >>> the following data type definitions may be adapted towards a specific RTOS\n \n/// Thread ID identifies the thread.\n/// \\note CAN BE CHANGED: \\b implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef void *osThreadId;\n#else\n#define osThreadId osThreadId_t\n#endif\n \n/// Timer ID identifies the timer.\n/// \\note CAN BE CHANGED: \\b implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef void *osTimerId;\n#else\n#define osTimerId osTimerId_t\n#endif\n \n/// Mutex ID identifies the mutex.\n/// \\note CAN BE CHANGED: \\b implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef void *osMutexId;\n#else\n#define osMutexId osMutexId_t\n#endif\n \n/// Semaphore ID identifies the semaphore.\n/// \\note CAN BE CHANGED: \\b implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef void *osSemaphoreId;\n#else\n#define osSemaphoreId osSemaphoreId_t\n#endif\n \n/// Pool ID identifies the memory pool.\n/// \\note CAN BE CHANGED: \\b implementation specific in every CMSIS-RTOS.\ntypedef void *osPoolId;\n \n/// Message ID identifies the message queue.\n/// \\note CAN BE CHANGED: \\b implementation specific in every CMSIS-RTOS.\ntypedef void *osMessageQId;\n \n/// Mail ID identifies the mail queue.\n/// \\note CAN BE CHANGED: \\b implementation specific in every CMSIS-RTOS.\ntypedef void *osMailQId;\n \n \n/// Thread Definition structure contains startup information of a thread.\n/// \\note CAN BE CHANGED: \\b os_thread_def is implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_thread_def {\n  os_pthread                 pthread;   ///< start address of thread function\n  osPriority               tpriority;   ///< initial thread priority\n  uint32_t                 instances;   ///< maximum number of instances of that thread function\n  uint32_t                 stacksize;   ///< stack size requirements in bytes; 0 is default stack size\n} osThreadDef_t;\n#else\ntypedef struct os_thread_def {\n  os_pthread                 pthread;   ///< start address of thread function\n  osThreadAttr_t                attr;   ///< thread attributes\n} osThreadDef_t;\n#endif\n \n/// Timer Definition structure contains timer parameters.\n/// \\note CAN BE CHANGED: \\b os_timer_def is implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_timer_def {\n  os_ptimer                   ptimer;   ///< start address of a timer function\n} osTimerDef_t;\n#else\ntypedef struct os_timer_def {\n  os_ptimer                   ptimer;   ///< start address of a timer function\n  osTimerAttr_t                 attr;   ///< timer attributes\n} osTimerDef_t;\n#endif\n \n/// Mutex Definition structure contains setup information for a mutex.\n/// \\note CAN BE CHANGED: \\b os_mutex_def is implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_mutex_def {\n  uint32_t                     dummy;   ///< dummy value\n} osMutexDef_t;\n#else\n#define osMutexDef_t osMutexAttr_t\n#endif\n \n/// Semaphore Definition structure contains setup information for a semaphore.\n/// \\note CAN BE CHANGED: \\b os_semaphore_def is implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_semaphore_def {\n  uint32_t                     dummy;   ///< dummy value\n} osSemaphoreDef_t;\n#else\n#define osSemaphoreDef_t osSemaphoreAttr_t\n#endif\n \n/// Definition structure for memory block allocation.\n/// \\note CAN BE CHANGED: \\b os_pool_def is implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_pool_def {\n  uint32_t                   pool_sz;   ///< number of items (elements) in the pool\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *pool;   ///< pointer to memory for pool\n} osPoolDef_t;\n#else\ntypedef struct os_pool_def {\n  uint32_t                   pool_sz;   ///< number of items (elements) in the pool\n  uint32_t                   item_sz;   ///< size of an item\n  osMemoryPoolAttr_t            attr;   ///< memory pool attributes\n} osPoolDef_t;\n#endif\n \n/// Definition structure for message queue.\n/// \\note CAN BE CHANGED: \\b os_messageQ_def is implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_messageQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  void                         *pool;   ///< memory array for messages\n} osMessageQDef_t;\n#else\ntypedef struct os_messageQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  osMessageQueueAttr_t          attr;   ///< message queue attributes\n} osMessageQDef_t;\n#endif\n \n/// Definition structure for mail queue.\n/// \\note CAN BE CHANGED: \\b os_mailQ_def is implementation specific in every CMSIS-RTOS.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_mailQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *pool;   ///< memory array for mail\n} osMailQDef_t;\n#else\ntypedef struct os_mailQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *mail;   ///< pointer to mail\n  osMemoryPoolAttr_t         mp_attr;   ///< memory pool attributes\n  osMessageQueueAttr_t       mq_attr;   ///< message queue attributes\n} osMailQDef_t;\n#endif\n \n \n/// Event structure contains detailed information about an event.\ntypedef struct {\n  osStatus                    status;   ///< status code: event or error information\n  union {\n    uint32_t                       v;   ///< message as 32-bit value\n    void                          *p;   ///< message or mail as void pointer\n    int32_t                  signals;   ///< signal flags\n  } value;                              ///< event value\n  union {\n    osMailQId                mail_id;   ///< mail id obtained by \\ref osMailCreate\n    osMessageQId          message_id;   ///< message id obtained by \\ref osMessageCreate\n  } def;                                ///< event definition\n} osEvent;\n \n \n//  ==== Kernel Management Functions ====\n \n/// Initialize the RTOS Kernel for creating objects.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osKernelInitialize (void);\n#endif\n \n/// Start the RTOS Kernel scheduler.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osKernelStart (void);\n#endif\n \n/// Check if the RTOS kernel is already started.\n/// \\return 0 RTOS is not started, 1 RTOS is started.\n#if (osCMSIS < 0x20000U)\nint32_t osKernelRunning(void);\n#endif\n \n#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0))  // System Timer available\n \n/// Get the RTOS kernel system timer counter.\n/// \\return RTOS kernel system timer as 32-bit value \n#if (osCMSIS < 0x20000U)\nuint32_t osKernelSysTick (void);\n#else\n#define  osKernelSysTick osKernelGetSysTimerCount\n#endif\n \n/// The RTOS kernel system timer frequency in Hz.\n/// \\note Reflects the system timer setting and is typically defined in a configuration file.\n#if (osCMSIS < 0x20000U)\n#define osKernelSysTickFrequency 100000000\n#endif\n \n/// Convert a microseconds value to a RTOS kernel system timer value.\n/// \\param         microsec     time value in microseconds.\n/// \\return time value normalized to the \\ref osKernelSysTickFrequency\n#if (osCMSIS < 0x20000U)\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)\n#else\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec *  osKernelGetSysTimerFreq()) / 1000000)\n#endif\n \n#endif  // System Timer available\n \n \n//  ==== Thread Management Functions ====\n \n/// Create a Thread Definition with function, priority, and stack requirements.\n/// \\param         name          name of the thread function.\n/// \\param         priority      initial priority of the thread function.\n/// \\param         instances     number of possible thread instances.\n/// \\param         stacksz       stack size (in bytes) requirements for the thread function.\n/// \\note CAN BE CHANGED: The parameters to \\b osThreadDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osThreadDef(name, priority, instances, stacksz) \\\nextern const osThreadDef_t os_thread_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osThreadDef(name, priority, instances, stacksz) \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ (name), (priority), (instances), (stacksz) }\n#else\n#define osThreadDef(name, priority, instances, stacksz) \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ (name), \\\n  { NULL, osThreadDetached, NULL, 0U, NULL, 8*((stacksz+7)/8), (priority), 0U, 0U } }\n#endif\n#endif\n \n/// Access a Thread definition.\n/// \\param         name          name of the thread definition object.\n/// \\note CAN BE CHANGED: The parameter to \\b osThread shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osThread(name) \\\n&os_thread_def_##name\n \n/// Create a thread and add it to Active Threads and set it to state READY.\n/// \\param[in]     thread_def    thread definition referenced with \\ref osThread.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);\n \n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\n#if (osCMSIS < 0x20000U)\nosThreadId osThreadGetId (void);\n#endif\n \n/// Change priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);\n#endif\n \n/// Get current priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return current priority value of the specified thread.\n#if (osCMSIS < 0x20000U)\nosPriority osThreadGetPriority (osThreadId thread_id);\n#endif\n \n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadYield (void);\n#endif\n \n/// Terminate execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadTerminate (osThreadId thread_id);\n#endif\n \n \n//  ==== Signal Management ====\n \n/// Set the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that should be set.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\nint32_t osSignalSet (osThreadId thread_id, int32_t signals);\n \n/// Clear the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that shall be cleared.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.\nint32_t osSignalClear (osThreadId thread_id, int32_t signals);\n \n/// Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\n/// \\param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event flag information or error code.\nosEvent osSignalWait (int32_t signals, uint32_t millisec);\n \n \n//  ==== Generic Wait Functions ====\n \n/// Wait for Timeout (Time Delay).\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osDelay (uint32_t millisec);\n#endif\n \n#if (defined (osFeature_Wait) && (osFeature_Wait != 0))  // Generic Wait available\n \n/// Wait for Signal, Message, Mail, or Timeout.\n/// \\param[in] millisec          \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return event that contains signal, message, or mail information or error code.\nosEvent osWait (uint32_t millisec);\n \n#endif  // Generic Wait available\n \n \n//  ==== Timer Management Functions ====\n \n/// Define a Timer object.\n/// \\param         name          name of the timer object.\n/// \\param         function      name of the timer call back function.\n/// \\note CAN BE CHANGED: The parameter to \\b osTimerDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osTimerDef(name, function) \\\nextern const osTimerDef_t os_timer_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osTimerDef(name, function) \\\nconst osTimerDef_t os_timer_def_##name = { (function) }\n#else\n#define osTimerDef(name, function) \\\nconst osTimerDef_t os_timer_def_##name = \\\n{ (function), { NULL, 0U, NULL, 0U } }\n#endif\n#endif\n \n/// Access a Timer definition.\n/// \\param         name          name of the timer object.\n/// \\note CAN BE CHANGED: The parameter to \\b osTimer shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osTimer(name) \\\n&os_timer_def_##name\n \n/// Create and Initialize a timer.\n/// \\param[in]     timer_def     timer object referenced with \\ref osTimer.\n/// \\param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer call back function.\n/// \\return timer ID for reference by other functions or NULL in case of error.\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);\n \n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value of the timer.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec);\n#endif\n \n/// Stop a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerStop (osTimerId timer_id);\n#endif\n \n/// Delete a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerDelete (osTimerId timer_id);\n#endif\n \n \n//  ==== Mutex Management Functions ====\n \n/// Define a Mutex.\n/// \\param         name          name of the mutex object.\n/// \\note CAN BE CHANGED: The parameter to \\b osMutexDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osMutexDef(name) \\\nextern const osMutexDef_t os_mutex_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osMutexDef(name) \\\nconst osMutexDef_t os_mutex_def_##name = { 0 }\n#else\n#define osMutexDef(name) \\\nconst osMutexDef_t os_mutex_def_##name = \\\n{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, NULL, 0U }\n#endif\n#endif\n \n/// Access a Mutex definition.\n/// \\param         name          name of the mutex object.\n/// \\note CAN BE CHANGED: The parameter to \\b osMutex shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osMutex(name) \\\n&os_mutex_def_##name\n \n/// Create and Initialize a Mutex object.\n/// \\param[in]     mutex_def     mutex definition referenced with \\ref osMutex.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def);\n \n/// Wait until a Mutex becomes available.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);\n#else\n#define  osMutexWait osMutexAcquire\n#endif\n \n/// Release a Mutex that was obtained by \\ref osMutexWait.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexRelease (osMutexId mutex_id);\n#endif\n \n/// Delete a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexDelete (osMutexId mutex_id);\n#endif\n \n \n//  ==== Semaphore Management Functions ====\n \n#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))  // Semaphore available\n \n/// Define a Semaphore object.\n/// \\param         name          name of the semaphore object.\n/// \\note CAN BE CHANGED: The parameter to \\b osSemaphoreDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osSemaphoreDef(name) \\\nextern const osSemaphoreDef_t os_semaphore_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osSemaphoreDef(name) \\\nconst osSemaphoreDef_t os_semaphore_def_##name = { 0 }\n#else\n#define osSemaphoreDef(name) \\\nconst osSemaphoreDef_t os_semaphore_def_##name = \\\n{ NULL, 0U, NULL, 0U }\n#endif\n#endif\n \n/// Access a Semaphore definition.\n/// \\param         name          name of the semaphore object.\n/// \\note CAN BE CHANGED: The parameter to \\b osSemaphore shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osSemaphore(name) \\\n&os_semaphore_def_##name\n \n/// Create and Initialize a Semaphore object.\n/// \\param[in]     semaphore_def semaphore definition referenced with \\ref osSemaphore.\n/// \\param[in]     count         maximum and initial number of available tokens.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);\n \n/// Wait until a Semaphore token becomes available.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return number of available tokens, or -1 in case of incorrect parameters.\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);\n \n/// Release a Semaphore token.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id);\n#endif\n \n/// Delete a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id);\n#endif\n \n#endif  // Semaphore available\n \n \n//  ==== Memory Pool Management Functions ====\n \n#if (defined(osFeature_Pool) && (osFeature_Pool != 0))  // Memory Pool available\n \n/// \\brief Define a Memory Pool.\n/// \\param         name          name of the memory pool.\n/// \\param         no            maximum number of blocks (objects) in the memory pool.\n/// \\param         type          data type of a single block (object).\n/// \\note CAN BE CHANGED: The parameter to \\b osPoolDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osPoolDef(name, no, type) \\\nextern const osPoolDef_t os_pool_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osPoolDef(name, no, type) \\\nconst osPoolDef_t os_pool_def_##name = \\\n{ (no), sizeof(type), NULL }\n#else\n#define osPoolDef(name, no, type) \\\nconst osPoolDef_t os_pool_def_##name = \\\n{ (no), sizeof(type), { NULL, 0U, NULL, 0U, NULL, 0U } }\n#endif\n#endif\n \n/// \\brief Access a Memory Pool definition.\n/// \\param         name          name of the memory pool\n/// \\note CAN BE CHANGED: The parameter to \\b osPool shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osPool(name) \\\n&os_pool_def_##name\n \n/// Create and Initialize a Memory Pool object.\n/// \\param[in]     pool_def      memory pool definition referenced with \\ref osPool.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\nosPoolId osPoolCreate (const osPoolDef_t *pool_def);\n \n/// Allocate a memory block from a Memory Pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolAlloc (osPoolId pool_id);\n \n/// Allocate a memory block from a Memory Pool and set memory block to zero.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolCAlloc (osPoolId pool_id);\n \n/// Return an allocated memory block back to a Memory Pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\param[in]     block         address of the allocated memory block to be returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\nosStatus osPoolFree (osPoolId pool_id, void *block);\n \n#endif  // Memory Pool available\n \n \n//  ==== Message Queue Management Functions ====\n \n#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))  // Message Queue available\n  \n/// \\brief Create a Message Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of messages in the queue.\n/// \\param         type          data type of a single message element (for debugger).\n/// \\note CAN BE CHANGED: The parameter to \\b osMessageQDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osMessageQDef(name, queue_sz, type) \\\nextern const osMessageQDef_t os_messageQ_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osMessageQDef(name, queue_sz, type) \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), NULL }\n#else\n#define osMessageQDef(name, queue_sz, type) \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), { NULL, 0U, NULL, 0U, NULL, 0U } }\n#endif\n#endif\n \n/// \\brief Access a Message Queue Definition.\n/// \\param         name          name of the queue\n/// \\note CAN BE CHANGED: The parameter to \\b osMessageQ shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osMessageQ(name) \\\n&os_messageQ_def_##name\n \n/// Create and Initialize a Message Queue object.\n/// \\param[in]     queue_def     message queue definition referenced with \\ref osMessageQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);\n \n/// Put a Message to a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     info          message information.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);\n \n/// Get a Message from a Queue or timeout if Queue is empty.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\nosEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);\n \n#endif  // Message Queue available\n \n \n//  ==== Mail Queue Management Functions ====\n \n#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))  // Mail Queue available\n \n/// \\brief Create a Mail Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of mails in the queue.\n/// \\param         type          data type of a single mail element.\n/// \\note CAN BE CHANGED: The parameter to \\b osMailQDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osMailQDef(name, queue_sz, type) \\\nextern const osMailQDef_t os_mailQ_def_##name\n#else                            // define the object\n#if (osCMSIS < 0x20000U)\n#define osMailQDef(name, queue_sz, type) \\\nconst osMailQDef_t os_mailQ_def_##name = \\\n{ (queue_sz), sizeof(type), NULL }\n#else\n#define osMailQDef(name, queue_sz, type) \\\nstatic void *os_mail_p_##name[2]; \\\nconst osMailQDef_t os_mailQ_def_##name = \\\n{ (queue_sz), sizeof(type), (&os_mail_p_##name), \\\n  { NULL, 0U, NULL, 0U, NULL, 0U }, \\\n  { NULL, 0U, NULL, 0U, NULL, 0U } }\n#endif\n#endif\n \n/// \\brief Access a Mail Queue Definition.\n/// \\param         name          name of the queue\n/// \\note CAN BE CHANGED: The parameter to \\b osMailQ shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osMailQ(name) \\\n&os_mailQ_def_##name\n \n/// Create and Initialize a Mail Queue object.\n/// \\param[in]     queue_def     mail queue definition referenced with \\ref osMailQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return mail queue ID for reference by other functions or NULL in case of error.\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);\n \n/// Allocate a memory block for mail from a mail memory pool.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec);\n \n/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec);\n \n/// Put a Mail into a Queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to memory with mail to put into a queue.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailPut (osMailQId queue_id, const void *mail);\n \n/// Get a Mail from a Queue or timeout if Queue is empty.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\nosEvent osMailGet (osMailQId queue_id, uint32_t millisec);\n \n/// Free a memory block by returning it to a mail memory pool.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to memory block that was obtained with \\ref osMailGet.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailFree (osMailQId queue_id, void *mail);\n \n#endif  // Mail Queue available\n \n \n#ifdef  __cplusplus\n}\n#endif\n \n#endif  // CMSIS_OS_H_\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/RTOS2/Template/cmsis_os1.c",
    "content": "/*\n * Copyright (c) 2013-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        10. January 2017\n * $Revision:    V1.2\n *\n * Project:      CMSIS-RTOS API V1\n * Title:        cmsis_os_v1.c V1 module file\n *---------------------------------------------------------------------------*/\n\n#include <string.h>\n#include \"cmsis_os.h\"\n\n#if (osCMSIS >= 0x20000U)\n\n\n// Thread\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {\n\n  if (thread_def == NULL) {\n    return (osThreadId)NULL;\n  }\n  return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr);\n}\n\n\n// Signals\n\n#define SignalMask ((1U<<osFeature_Signals)-1U)\n\nint32_t osSignalSet (osThreadId thread_id, int32_t signals) {\n  uint32_t flags;\n\n  flags = osThreadFlagsSet(thread_id, (uint32_t)signals);\n  if ((flags & 0x80000000U) != 0U) {\n    return ((int32_t)0x80000000U);\n  }\n  return ((int32_t)(flags & ~((uint32_t)signals)));\n}\n\nint32_t osSignalClear (osThreadId thread_id, int32_t signals) {\n  uint32_t flags;\n\n  if (thread_id != osThreadGetId()) {\n    return ((int32_t)0x80000000U);\n  }\n  flags = osThreadFlagsClear((uint32_t)signals);\n  if ((flags & 0x80000000U) != 0U) {\n    return ((int32_t)0x80000000U);\n  }\n  return ((int32_t)flags);\n}\n\nosEvent osSignalWait (int32_t signals, uint32_t millisec) {\n  osEvent  event;\n  uint32_t flags;\n\n  if (signals != 0) {\n    flags = osThreadFlagsWait((uint32_t)signals, osFlagsWaitAll, millisec);\n  } else {\n    flags = osThreadFlagsWait(SignalMask,        osFlagsWaitAny, millisec);\n  }\n  if ((flags > 0U) && (flags < 0x80000000U)) {\n    event.status = osEventSignal;\n    event.value.signals = (int32_t)flags;\n  } else {\n    switch ((int32_t)flags) {\n      case osErrorResource:\n        event.status = osOK;\n        break;\n      case osErrorTimeout:\n        event.status = osEventTimeout;\n        break;\n      case osErrorParameter:\n        event.status = osErrorValue;\n        break;\n      default:\n        event.status = (osStatus)flags;\n        break;\n    }\n  }\n  return event;\n}\n\n\n// Timer\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {\n\n  if (timer_def == NULL) {\n    return (osTimerId)NULL;\n  }\n  return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr);\n}\n\n\n// Mutex\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def) {\n\n  if (mutex_def == NULL) {\n    return (osMutexId)NULL;\n  }\n  return osMutexNew(mutex_def);\n}\n\n\n// Semaphore\n\n#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))\n\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {\n\n  if (semaphore_def == NULL) {\n    return (osSemaphoreId)NULL;\n  }\n  return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def);\n}\n\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {\n  osStatus_t status;\n  uint32_t   count;\n\n  status = osSemaphoreAcquire(semaphore_id, millisec);\n  switch (status) {\n    case osOK:\n      count = osSemaphoreGetCount(semaphore_id);\n      return ((int32_t)count + 1);\n    case osErrorResource:\n    case osErrorTimeout:\n      return 0;\n    default:\n      break;\n  }\n  return -1;\n}\n\n#endif  // Semaphore\n\n\n// Memory Pool\n\n#if (defined(osFeature_Pool) && (osFeature_Pool != 0))\n\nosPoolId osPoolCreate (const osPoolDef_t *pool_def) {\n\n  if (pool_def == NULL) {\n    return (osPoolId)NULL;\n  }\n  return ((osPoolId)(osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr)));\n}\n\nvoid *osPoolAlloc (osPoolId pool_id) {\n  return osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U);\n}\n\nvoid *osPoolCAlloc (osPoolId pool_id) {\n  void    *block;\n  uint32_t block_size;\n\n  block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id);\n  if (block_size == 0U) {\n    return NULL;\n  }\n  block = osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U);\n  if (block != NULL) {\n    memset(block, 0, block_size);\n  }\n  return block;\n}\n\nosStatus osPoolFree (osPoolId pool_id, void *block) {\n  return osMemoryPoolFree((osMemoryPoolId_t)pool_id, block);\n}\n\n#endif  // Memory Pool\n\n\n// Message Queue\n\n#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))\n\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {\n  (void)thread_id;\n\n  if (queue_def == NULL) {\n    return (osMessageQId)NULL;\n  }\n  return ((osMessageQId)(osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr)));\n}\n\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {\n  return osMessageQueuePut((osMessageQueueId_t)queue_id, &info, 0U, millisec);\n}\n\nosEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {\n  osStatus_t status;\n  osEvent    event;\n  uint32_t   message;\n\n  status = osMessageQueueGet((osMessageQueueId_t)queue_id, &message, NULL, millisec);\n  switch (status) {\n    case osOK:\n      event.status = osEventMessage;\n      event.value.v = message;\n      break;\n    case osErrorResource:\n      event.status = osOK;\n      break;\n    case osErrorTimeout:\n      event.status = osEventTimeout;\n      break;\n    default:\n      event.status = status;\n      break;\n  }\n  return event;\n}\n\n#endif  // Message Queue\n\n\n// Mail Queue\n\n#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))\n\ntypedef struct os_mail_queue_s {\n  osMemoryPoolId_t   mp_id;\n  osMessageQueueId_t mq_id;\n} os_mail_queue_t;\n\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {\n  os_mail_queue_t *ptr;\n  (void)thread_id;\n\n  if (queue_def == NULL) {\n    return (osMailQId)NULL;\n  }\n\n  ptr = queue_def->mail;\n  if (ptr == NULL) {\n    return (osMailQId)NULL;\n  }\n\n  ptr->mp_id = osMemoryPoolNew  (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr);\n  ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr);\n  if ((ptr->mp_id == (osMemoryPoolId_t)NULL) || (ptr->mq_id == (osMessageQueueId_t)NULL)) {\n    if (ptr->mp_id != (osMemoryPoolId_t)NULL) {\n      osMemoryPoolDelete(ptr->mp_id);\n    }\n    if (ptr->mq_id != (osMessageQueueId_t)NULL) {\n      osMessageQueueDelete(ptr->mq_id);\n    }\n    return (osMailQId)NULL;\n  }\n\n  return (osMailQId)ptr;\n}\n\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n\n  if (ptr == NULL) {\n    return NULL;\n  }\n  return osMemoryPoolAlloc(ptr->mp_id, millisec);\n}\n\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n  void            *block;\n  uint32_t         block_size;\n\n  if (ptr == NULL) {\n    return NULL;\n  }\n  block_size = osMemoryPoolGetBlockSize(ptr->mp_id);\n  if (block_size == 0U) {\n    return NULL;\n  }\n  block = osMemoryPoolAlloc(ptr->mp_id, millisec);\n  if (block != NULL) {\n    memset(block, 0, block_size);\n  }\n\n  return block;\n\n}\n\nosStatus osMailPut (osMailQId queue_id, const void *mail) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n\n  if (ptr == NULL) {\n    return osErrorParameter;\n  }\n  if (mail == NULL) {\n    return osErrorValue;\n  }\n  return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U);\n}\n\nosEvent osMailGet (osMailQId queue_id, uint32_t millisec) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n  osStatus_t       status;\n  osEvent          event;\n  void            *mail;\n\n  if (ptr == NULL) {\n    event.status = osErrorParameter;\n    return event;\n  }\n\n  status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec);\n  switch (status) {\n    case osOK:\n      event.status = osEventMail;\n      event.value.p = mail;\n      break;\n    case osErrorResource:\n      event.status = osOK;\n      break;\n    case osErrorTimeout:\n      event.status = osEventTimeout;\n      break;\n    default:\n      event.status = status;\n      break;\n  }\n  return event;\n}\n\nosStatus osMailFree (osMailQId queue_id, void *mail) {\n  os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id;\n\n  if (ptr == NULL) {\n    return osErrorParameter;\n  }\n  if (mail == NULL) {\n    return osErrorValue;\n  }\n  return osMemoryPoolFree(ptr->mp_id, mail);\n}\n\n#endif  // Mail Queue\n\n\n#endif  // osCMSIS\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Utilities/ARM_Example.h",
    "content": "/*\n * ARM Limited (ARM) is supplying this software for use with Cortex-M\n * processor based microcontroller, but can be equally used for other\n * suitable processor architectures. This file can be freely distributed.\n * Modifications to this file shall be clearly marked.\n * \n * THIS SOFTWARE IS PROVIDED \"AS IS\". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n *\n * @file     ARM_Example.h\n * @brief    CMSIS HeaderFile\n * @version  1.2\n * @date     20. July 2018\n * @note     Generated by SVDConv V3.3.21 on Friday, 20.07.2018 15:12:22\n *           from File 'ARM_Example.svd',\n *           last modified on Friday, 20.07.2018 13:11:38\n */\n\n\n\n/** @addtogroup ARM Ltd.\n  * @{\n  */\n\n\n/** @addtogroup ARM_Example\n  * @{\n  */\n\n\n#ifndef ARM_EXAMPLE_H\n#define ARM_EXAMPLE_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/** @addtogroup Configuration_of_CMSIS\n  * @{\n  */\n\n\n\n/* =========================================================================================================================== */\n/* ================                                Interrupt Number Definition                                ================ */\n/* =========================================================================================================================== */\n\ntypedef enum {\n/* =======================================  ARM Cortex-M3 Specific Interrupt Numbers  ======================================== */\n  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */\n  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */\n  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */\n  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation\n                                                     and No Match                                                              */\n  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory\n                                                     related Fault                                                             */\n  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */\n  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */\n  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */\n  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */\n  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */\n/* ========================================  ARM_Example Specific Interrupt Numbers  ========================================= */\n  TIMER0_IRQn               =   0,              /*!< 0  Timer 0 interrupt                                                      */\n  TIMER1_IRQn               =   4,              /*!< 4  Timer 2 interrupt                                                      */\n  TIMER2_IRQn               =   6               /*!< 6  Timer 2 interrupt                                                      */\n} IRQn_Type;\n\n\n\n/* =========================================================================================================================== */\n/* ================                           Processor and Core Peripheral Section                           ================ */\n/* =========================================================================================================================== */\n\n/* ===========================  Configuration of the ARM Cortex-M3 Processor and Core Peripherals  =========================== */\n#define __CM3_REV                 0x0100U       /*!< CM3 Core Revision                                                         */\n#define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */\n#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */\n#define __MPU_PRESENT                  1        /*!< MPU present or not                                                        */\n#define __FPU_PRESENT                  0        /*!< FPU present or not                                                        */\n\n\n/** @} */ /* End of group Configuration_of_CMSIS */\n\n#include \"core_cm3.h\"                           /*!< ARM Cortex-M3 processor and core peripherals                              */\n#include \"system_ARM_Example.h\"                 /*!< ARM_Example System                                                        */\n\n#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */\n  #define __IM   __I\n#endif\n#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */\n  #define __OM   __O\n#endif\n#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */\n  #define __IOM  __IO\n#endif\n\n\n/* ========================================  Start of section using anonymous unions  ======================================== */\n#if defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n  #pragma clang diagnostic ignored \"-Wgnu-anonymous-struct\"\n  #pragma clang diagnostic ignored \"-Wnested-anon-types\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* =========================================================================================================================== */\n/* ================                            Device Specific Peripheral Section                             ================ */\n/* =========================================================================================================================== */\n\n\n/** @addtogroup Device_Peripheral_peripherals\n  * @{\n  */\n\n\n\n/* =========================================================================================================================== */\n/* ================                                          TIMER0                                           ================ */\n/* =========================================================================================================================== */\n\n\n/**\n  * @brief 32 Timer / Counter, counting up or down from different sources (TIMER0)\n  */\n\ntypedef struct {                                /*!< (@ 0x40010000) TIMER0 Structure                                           */\n  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) Control Register                                           */\n  __IOM uint16_t  SR;                           /*!< (@ 0x00000004) Status Register                                            */\n  __IM  uint16_t  RESERVED;\n  __IM  uint32_t  RESERVED1[2];\n  __IOM uint16_t  INT;                          /*!< (@ 0x00000010) Interrupt Register                                         */\n  __IM  uint16_t  RESERVED2;\n  __IM  uint32_t  RESERVED3[3];\n  __IOM uint32_t  COUNT;                        /*!< (@ 0x00000020) The Counter Register reflects the actual Value\n                                                                    of the Timer/Counter                                       */\n  __IOM uint32_t  MATCH;                        /*!< (@ 0x00000024) The Match Register stores the compare Value for\n                                                                    the MATCH condition                                        */\n  \n  union {\n    __IM  uint32_t PRESCALE_RD;                 /*!< (@ 0x00000028) The Prescale Register stores the Value for the\n                                                                    prescaler. The cont event gets divided by\n                                                                    this value                                                 */\n    __OM  uint32_t PRESCALE_WR;                 /*!< (@ 0x00000028) The Prescale Register stores the Value for the\n                                                                    prescaler. The cont event gets divided by\n                                                                    this value                                                 */\n  };\n  __IM  uint32_t  RESERVED4[9];\n  __IOM uint32_t  RELOAD[4];                    /*!< (@ 0x00000050) The Reload Register stores the Value the COUNT\n                                                                    Register gets reloaded on a when a condition\n                                                                    was met.                                                   */\n} TIMER0_Type;                                  /*!< Size = 96 (0x60)                                                          */\n\n\n/** @} */ /* End of group Device_Peripheral_peripherals */\n\n\n/* =========================================================================================================================== */\n/* ================                          Device Specific Peripheral Address Map                           ================ */\n/* =========================================================================================================================== */\n\n\n/** @addtogroup Device_Peripheral_peripheralAddr\n  * @{\n  */\n\n#define TIMER0_BASE                 0x40010000UL\n#define TIMER1_BASE                 0x40010100UL\n#define TIMER2_BASE                 0x40010200UL\n\n/** @} */ /* End of group Device_Peripheral_peripheralAddr */\n\n\n/* =========================================================================================================================== */\n/* ================                                  Peripheral declaration                                   ================ */\n/* =========================================================================================================================== */\n\n\n/** @addtogroup Device_Peripheral_declaration\n  * @{\n  */\n\n#define TIMER0                      ((TIMER0_Type*)            TIMER0_BASE)\n#define TIMER1                      ((TIMER0_Type*)            TIMER1_BASE)\n#define TIMER2                      ((TIMER0_Type*)            TIMER2_BASE)\n\n/** @} */ /* End of group Device_Peripheral_declaration */\n\n\n/* =========================================  End of section using anonymous unions  ========================================= */\n#if defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* ARM_EXAMPLE_H */\n\n\n/** @} */ /* End of group ARM_Example */\n\n/** @} */ /* End of group ARM Ltd. */\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Utilities/ARM_Example.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012-2014 ARM Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n\t\t   for demonstration purposes only.\n\t\t   \n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used \n     to endorse or promote products derived from this software without \n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" \n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF \n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n \n<device schemaVersion=\"1.1\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARM_Example</name>                                        <!-- name of part-->\n  <series>ARMCM3</series>                                         <!-- device series the device belongs to -->\n  <version>1.2</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc. </description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM3</name>\n    <revision>r1p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n  </cpu>\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n  <peripherals>\n    <!-- Timer 0 -->\n    <peripheral>\n      <name>TIMER0</name>\n      <version>1.0</version>\n      <description>32 Timer / Counter, counting up or down from different sources</description>\n      <groupName>TIMER</groupName>\n      <baseAddress>0x40010000</baseAddress>\n      <size>32</size>\n      <access>read-write</access>\n\n      <addressBlock>\n        <offset>0</offset>\n        <size>0x100</size>\n        <usage>registers</usage>\n      </addressBlock>\n\n      <interrupt>\n        <name>TIMER0</name>\n        <description>Timer 0 interrupt</description>\n        <value>0</value>\n      </interrupt>\n\n      <registers>\n      <!-- CR: Control Register -->\n        <register>\n          <name>CR</name>\n          <description>Control Register</description>\n          <addressOffset>0x00</addressOffset>\n          <size>32</size>\n          <access>read-write</access>\n          <resetValue>0x00000000</resetValue>\n          <resetMask>0x1337F7F</resetMask>\n\n          <fields>\n            <!-- EN: Enable -->\n            <field>\n              <name>EN</name>\n              <description>Enable</description>\n              <bitRange>[0:0]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>Disable</name>\n                  <description>Timer is disabled and does not operate</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Enable</name>\n                  <description>Timer is enabled and can operate</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- RST: Reset -->\n            <field>\n              <name>RST</name>\n              <description>Reset Timer</description>\n              <bitRange>[1:1]</bitRange>\n              <access>write-only</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>No_Action</name>\n                  <description>Write as ZERO if necessary</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Reset_Timer</name>\n                  <description>Reset the Timer</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- CNT: Counting Direction -->\n            <field>\n              <name>CNT</name>\n              <description>Counting direction</description>\n              <bitRange>[3:2]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>Count_UP</name>\n                  <description>Timer Counts UO and wraps, if no STOP condition is set</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Count_DOWN</name>\n                  <description>Timer Counts DOWN and wraps, if no STOP condition is set</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Toggle</name>\n                  <description>Timer Counts up to MAX, then DOWN to ZERO, if no STOP condition is set</description>\n                  <value>2</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- MODE: Operation Mode -->\n            <field>\n              <name>MODE</name>\n              <description>Operation Mode</description>\n              <bitRange>[6:4]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>Continous</name>\n                  <description>Timer runs continously</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Single_ZERO_MAX</name>\n                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT) and stops</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Single_MATCH</name>\n                  <description>Timer counts to the Value of MATCH Register and stops</description>\n                  <value>2</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Reload_ZERO_MAX</name>\n                  <description>Timer counts to 0x00 or 0xFFFFFFFF (depending on CNT), loads the RELOAD Value and continues</description>\n                  <value>3</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Reload_MATCH</name>\n                  <description>Timer counts to the Value of MATCH Register, loads the RELOAD Value and continues</description>\n                  <value>4</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- PSC: Use Prescaler -->\n            <field>\n              <name>PSC</name>\n              <description>Use Prescaler</description>\n              <bitRange>[7:7]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>Disabled</name>\n                  <description>Prescaler is not used</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Enabled</name>\n                  <description>Prescaler is used as divider</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- CNTSRC: Timer / Counter Soruce Divider -->\n            <field>\n              <name>CNTSRC</name>\n              <description>Timer / Counter Source Divider</description>\n              <bitRange>[11:8]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>CAP_SRC</name>\n                  <description>Capture Source is used directly</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>CAP_SRC_div2</name>\n                  <description>Capture Source is divided by 2</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>CAP_SRC_div4</name>\n                  <description>Capture Source is divided by 4</description>\n                  <value>2</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>CAP_SRC_div8</name>\n                  <description>Capture Source is divided by 8</description>\n                  <value>3</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>CAP_SRC_div16</name>\n                  <description>Capture Source is divided by 16</description>\n                  <value>4</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>CAP_SRC_div32</name>\n                  <description>Capture Source is divided by 32</description>\n                  <value>5</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>CAP_SRC_div64</name>\n                  <description>Capture Source is divided by 64</description>\n                  <value>6</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>CAP_SRC_div128</name>\n                  <description>Capture Source is divided by 128</description>\n                  <value>7</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>CAP_SRC_div256</name>\n                  <description>Capture Source is divided by 256</description>\n                  <value>8</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- CAPSRC: Timer / COunter Capture Source -->\n            <field>\n              <name>CAPSRC</name>\n              <description>Timer / Counter Capture Source</description>\n              <bitRange>[15:12]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>CClk</name>\n                  <description>Core Clock</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOA_0</name>\n                  <description>GPIO A, PIN 0</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOA_1</name>\n                  <description>GPIO A, PIN 1</description>\n                  <value>2</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOA_2</name>\n                  <description>GPIO A, PIN 2</description>\n                  <value>3</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOA_3</name>\n                  <description>GPIO A, PIN 3</description>\n                  <value>4</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOA_4</name>\n                  <description>GPIO A, PIN 4</description>\n                  <value>5</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOA_5</name>\n                  <description>GPIO A, PIN 5</description>\n                  <value>6</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOA_6</name>\n                  <description>GPIO A, PIN 6</description>\n                  <value>7</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOA_7</name>\n                  <description>GPIO A, PIN 7</description>\n                  <value>8</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOB_0</name>\n                  <description>GPIO B, PIN 0</description>\n                  <value>9</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOB_1</name>\n                  <description>GPIO B, PIN 1</description>\n                  <value>10</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOB_2</name>\n                  <description>GPIO B, PIN 2</description>\n                  <value>11</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOB_3</name>\n                  <description>GPIO B, PIN 3</description>\n                  <value>12</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOC_0</name>\n                  <description>GPIO C, PIN 0</description>\n                  <value>13</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOC_5</name>\n                  <description>GPIO C, PIN 1</description>\n                  <value>14</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>GPIOC_6</name>\n                  <description>GPIO C, PIN 2</description>\n                  <value>15</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- CAPEDGE: Capture Edge -->\n            <field>\n              <name>CAPEDGE</name>\n              <description>Capture Edge, select which Edge should result in a counter increment or decrement</description>\n              <bitRange>[17:16]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>RISING</name>\n                  <description>Only rising edges result in a counter increment or decrement</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>FALLING</name>\n                  <description>Only falling edges  result in a counter increment or decrement</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>BOTH</name>\n                  <description>Rising and falling edges result in a counter increment or decrement</description>\n                  <value>2</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- TRGEXT: Triggers an other Peripheral -->\n            <field>\n              <name>TRGEXT</name>\n              <description>Triggers an other Peripheral</description>\n              <bitRange>[21:20]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>NONE</name>\n                  <description>No Trigger is emitted</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>DMA1</name>\n                  <description>DMA Controller 1 is triggered, dependant on MODE</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>DMA2</name>\n                  <description>DMA Controller 2 is triggered, dependant on MODE</description>\n                  <value>2</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>UART</name>\n                  <description>UART is triggered, dependant on MODE</description>\n                  <value>3</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- Reload: Selects Reload Register n -->\n            <field>\n              <name>RELOAD</name>\n              <description>Select RELOAD Register n to reload Timer on condition</description>\n              <bitRange>[25:24]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>RELOAD0</name>\n                  <description>Selects Reload Register number 0</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>RELOAD1</name>\n                  <description>Selects Reload Register number 1</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>RELOAD2</name>\n                  <description>Selects Reload Register number 2</description>\n                  <value>2</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>RELOAD3</name>\n                  <description>Selects Reload Register number 3</description>\n                  <value>3</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- IDR: Inc or dec Reload Register Selection -->\n            <field>\n              <name>IDR</name>\n              <description>Selects, if Reload Register number is incremented, decremented or not modified</description>\n              <bitRange>[27:26]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>KEEP</name>\n                  <description>Reload Register number does not change automatically</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>INCREMENT</name>\n                  <description>Reload Register number is incremented on each match</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>DECREMENT</name>\n                  <description>Reload Register number is decremented on each match</description>\n                  <value>2</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- START: Starts / Stops the Timer/Counter -->\n            <field>\n              <name>S</name>\n              <description>Starts and Stops the Timer / Counter</description>\n              <bitRange>[31:31]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>STOP</name>\n                  <description>Timer / Counter is stopped</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>START</name>\n                  <description>Timer / Counter is started</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n          </fields>\n        </register>\n\n        <!-- SR: Status Register -->\n        <register>\n          <name>SR</name>\n          <description>Status Register</description>\n          <addressOffset>0x04</addressOffset>\n          <size>16</size>\n          <access>read-write</access>\n          <resetValue>0x00000000</resetValue>\n          <resetMask>0xD701</resetMask>\n\n          <fields>\n            <!-- RUN: Shows if Timer is running -->\n            <field>\n              <name>RUN</name>\n              <description>Shows if Timer is running or not</description>\n              <bitRange>[0:0]</bitRange>\n              <access>read-only</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>Stopped</name>\n                  <description>Timer is not running</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Running</name>\n                  <description>Timer is running</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- MATCH: Shows if a Match was hit -->\n            <field>\n              <name>MATCH</name>\n              <description>Shows if the MATCH was hit</description>\n              <bitRange>[8:8]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>No_Match</name>\n                  <description>The MATCH condition was not hit</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Match_Hit</name>\n                  <description>The MATCH condition was hit</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- UN: Shows if an underflow occured -->\n            <field>\n              <name>UN</name>\n              <description>Shows if an underflow occured. This flag is sticky</description>\n              <bitRange>[9:9]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>No_Underflow</name>\n                  <description>No underflow occured since last clear</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Underflow</name>\n                  <description>A minimum of one underflow occured since last clear</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- OV: Shows if an overflow occured -->\n            <field>\n              <name>OV</name>\n              <description>Shows if an overflow occured. This flag is sticky</description>\n              <bitRange>[10:10]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>No_Overflow</name>\n                  <description>No overflow occured since last clear</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Overflow_occured</name>\n                  <description>A minimum of one overflow occured since last clear</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- RST: Shows if Timer is in RESET state -->\n            <field>\n              <name>RST</name>\n              <description>Shows if Timer is in RESET state</description>\n              <bitRange>[12:12]</bitRange>\n              <access>read-only</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>Ready</name>\n                  <description>Timer is not in RESET state and can operate</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>In_Reset</name>\n                  <description>Timer is in RESET state and can not operate</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- RELOAD: Shows the currently active Reload Register -->\n            <field>\n              <name>RELOAD</name>\n              <description>Shows the currently active RELOAD Register</description>\n              <bitRange>[15:14]</bitRange>\n              <access>read-only</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>RELOAD0</name>\n                  <description>Reload Register number 0 is active</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>RELOAD1</name>\n                  <description>Reload Register number 1 is active</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>RELOAD2</name>\n                  <description>Reload Register number 2 is active</description>\n                  <value>2</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>RELOAD3</name>\n                  <description>Reload Register number 3 is active</description>\n                  <value>3</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n          </fields>\n        </register>\n\n        <!-- INT: Interrupt Register -->\n        <register>\n          <name>INT</name>\n          <description>Interrupt Register</description>\n          <addressOffset>0x10</addressOffset>\n          <size>16</size>\n          <access>read-write</access>\n          <resetValue>0x00000000</resetValue>\n          <resetMask>0x0771</resetMask>\n\n          <fields>\n            <!-- EN: Interrupt Enable -->\n            <field>\n              <name>EN</name>\n              <description>Interrupt Enable</description>\n              <bitRange>[0:0]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>Disabled</name>\n                  <description>Timer does not generate Interrupts</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Enable</name>\n                  <description>Timer triggers the TIMERn Interrupt</description>\n                  <value>1</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n\n            <!-- MODE: Interrupt Mode -->\n            <field>\n              <name>MODE</name>\n              <description>Interrupt Mode, selects on which condition the Timer should generate an Interrupt</description>\n              <bitRange>[6:4]</bitRange>\n              <access>read-write</access>\n              <enumeratedValues>\n                <enumeratedValue>\n                  <name>Match</name>\n                  <description>Timer generates an Interrupt when the MATCH condition is hit</description>\n                  <value>0</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Underflow</name>\n                  <description>Timer generates an Interrupt when it underflows</description>\n                  <value>1</value>\n                </enumeratedValue>\n                <enumeratedValue>\n                  <name>Overflow</name>\n                  <description>Timer generates an Interrupt when it overflows</description>\n                  <value>2</value>\n                </enumeratedValue>\n              </enumeratedValues>\n            </field>\n          </fields>\n        </register>\n\n        <!-- COUNT: Counter Register -->\n        <register>\n          <name>COUNT</name>\n          <description>The Counter Register reflects the actual Value of the Timer/Counter</description>\n          <addressOffset>0x20</addressOffset>\n          <size>32</size>\n          <access>read-write</access>\n          <resetValue>0x00000000</resetValue>\n          <resetMask>0xFFFFFFFF</resetMask>\n        </register>\n\n        <!-- MATCH: Match Register -->\n        <register>\n          <name>MATCH</name>\n          <description>The Match Register stores the compare Value for the MATCH condition</description>\n          <addressOffset>0x24</addressOffset>\n          <size>32</size>\n          <access>read-write</access>\n          <resetValue>0x00000000</resetValue>\n          <resetMask>0xFFFFFFFF</resetMask>\n        </register>\n        \n        <!-- PRESCALE: Prescale Read Register -->\n        <register>\n          <name>PRESCALE_RD</name>\n          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>\n          <addressOffset>0x28</addressOffset>\n          <size>32</size>\n          <access>read-only</access>\n          <resetValue>0x00000000</resetValue>\n          <resetMask>0xFFFFFFFF</resetMask>\n        </register>\n        \n        <!-- PRESCALE: Prescale Write Register -->\n        <register>\n          <name>PRESCALE_WR</name>\n          <description>The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value</description>\n          <addressOffset>0x28</addressOffset>\n          <size>32</size>\n          <access>write-only</access>\n          <resetValue>0x00000000</resetValue>\n          <resetMask>0xFFFFFFFF</resetMask>\n        </register>\n\n\n        <!-- RELOAD: Array of Reload Register with 4 elements-->\n        <register>\n          <dim>4</dim>\n          <dimIncrement>4</dimIncrement>\n          <name>RELOAD[%s]</name>\n          <description>The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.</description>\n          <addressOffset>0x50</addressOffset>\n          <size>32</size>\n          <access>read-write</access>\n          <resetValue>0x00000000</resetValue>\n          <resetMask>0xFFFFFFFF</resetMask>\n        </register>\n      </registers>\n    </peripheral>\n\n    <!-- Timer 1 -->\n    <peripheral derivedFrom=\"TIMER0\">\n      <name>TIMER1</name>\n      <baseAddress>0x40010100</baseAddress>\n      <interrupt>\n        <name>TIMER1</name>\n        <description>Timer 1 interrupt</description>\n        <value>4</value>\n      </interrupt>\n    </peripheral>\n\n    <!-- Timer 2 -->\n    <peripheral derivedFrom=\"TIMER0\">\n      <name>TIMER2</name>\n      <baseAddress>0x40010200</baseAddress>\n      <interrupt>\n        <name>TIMER2</name>\n        <description>Timer 2 interrupt</description>\n        <value>6</value>\n      </interrupt>\n    </peripheral>\n  </peripherals>\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Utilities/CMSIS-SVD.xsd",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<!--\n\n  Copyright (c) 2013-2022 ARM Limited. All rights reserved.\n\n  SPDX-License-Identifier: Apache-2.0\n\n  Licensed under the Apache License, Version 2.0 (the License); you may\n  not use this file except in compliance with the License.\n  You may obtain a copy of the License at\n\n  www.apache.org/licenses/LICENSE-2.0\n\n  Unless required by applicable law or agreed to in writing, software\n  distributed under the License is distributed on an AS IS BASIS, WITHOUT\n  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  See the License for the specific language governing permissions and\n  limitations under the License.\n\n  $Date:         21. April 2022\n  $Revision:     1.3.9\n\n  Version 1.3.9:\n  - add CM85 as enumerated value for cpuNameType.\n\n  Version 1.3.8:\n  - add SMC1 as enumerated value for cpuNameType.\n\n  Version 1.3.7:\n  - add CM55 as enumerated value for cpuNameType.\n  \n  Version 1.3.6:\n  - add ARMV81MML as enumeration value for cpuNameType.\n  \n  Version 1.3.5:\n  - add CM35P as enumeration value for cpuNameType.\n\n  Version 1.3.4:\n  - add dspPresent element to cpuType as SIMD instructions became optional for new processors.\n\n  Version 1.3.3:\n  - update file header to Apache 2.0 License\n  - add dimableIdentifierType, as a copy of previous identifierType adding \"%s\",\n  - update identifierType to only allow names without %s included.\n  - remove enumerationNameType.\n  - add headerEnumName to enumerationType and to dimArrayIndexType for peripheral arrays\n    overwriting hierarchically generated names\n  - add dimName to dimElementGroup. Only valid in <cluster> context, ignored otherwise.\n\n  Version 1.3.2:\n  adding dimIndexArray to peripheral-, cluster- and register-array to describe\n  enumeration of array indices.\n\n  Version 1.3.1:\n  fixed peripheral name element type to identifierType to support %s for peripheral arrays\n  added optional protection element to addressBlockType and added p=privileged\n\n  Version 1.3:\n  added dim to peripherals to describe an array of peripherals.\n  added nesting of clusters to support hierarchical register structures.\n  added protection element as part of the registerPropertiesGroup indicating\n  special permissions are required for accessing a register.\n  CPU Section extended with description of the Secure Attribution Unit.\n\n  Version 1.2:\n  Cortex-M7 support items have been added as optional tags for the device header file generation:\n  fpuDP, icachePresent, dcachePresent, itcmPresent, dtcmPresent\n\n  Version 1.1:\n  For backward compatibility all additional tags have been made optional.\n  Extensions may be mandatory for successful device header file generation\n  Other changes are related to some restructuring of the schema.\n\n  Note that the memory section has been removed since this would limit the\n  reuse of descriptions for a series of devices.\n -->\n\n<xs:schema xmlns:xs=\"http://www.w3.org/2001/XMLSchema\" elementFormDefault=\"qualified\" attributeFormDefault=\"qualified\" version=\"1.3\">\n  <!-- stringType requires a none empty string of a least one character length -->\n  <xs:simpleType name=\"stringType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:minLength value=\"1\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <xs:simpleType name=\"descriptionStringType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[\\p{IsBasicLatin}\\p{IsLatin-1Supplement}]*\" />\n    </xs:restriction>\n  </xs:simpleType>\n\n  <!-- cpuType specifies a selection of Cortex-M and Secure-Cores. This list will get extended as new processors are released -->\n  <xs:simpleType name=\"cpuNameType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"CM0\"/>\n      <xs:enumeration value=\"CM0PLUS\"/>\n      <xs:enumeration value=\"CM0+\"/>\n      <xs:enumeration value=\"CM1\"/>\n      <xs:enumeration value=\"CM3\"/>\n      <xs:enumeration value=\"CM4\"/>\n      <xs:enumeration value=\"CM7\"/>\n      <xs:enumeration value=\"CM23\"/>\n      <xs:enumeration value=\"CM33\"/>\n      <xs:enumeration value=\"CM35P\"/>\n      <xs:enumeration value=\"CM55\"/>\n      <xs:enumeration value=\"CM85\"/>\n      <xs:enumeration value=\"SC000\"/>\n      <xs:enumeration value=\"SC300\"/>\n      <xs:enumeration value=\"ARMV8MML\"/>\n      <xs:enumeration value=\"ARMV8MBL\"/>\n      <xs:enumeration value=\"ARMV81MML\"/>\n      <xs:enumeration value=\"CA5\"/>\n      <xs:enumeration value=\"CA7\"/>\n      <xs:enumeration value=\"CA8\"/>\n      <xs:enumeration value=\"CA9\"/>\n      <xs:enumeration value=\"CA15\"/>\n      <xs:enumeration value=\"CA17\"/>\n      <xs:enumeration value=\"CA53\"/>\n      <xs:enumeration value=\"CA57\"/>\n      <xs:enumeration value=\"CA72\"/>\n      <xs:enumeration value=\"SMC1\"/>\n      <xs:enumeration value=\"other\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- revisionType specifies the CPU revision format as defined by ARM (rNpM) -->\n  <xs:simpleType name=\"revisionType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"r[0-9]*p[0-9]*\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- EndianType pre-defines the tokens for specifying the endianess of the device -->\n  <xs:simpleType name=\"endianType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"little\"/>\n      <xs:enumeration value=\"big\"/>\n      <xs:enumeration value=\"selectable\"/>\n      <xs:enumeration value=\"other\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- dataType pre-defines the tokens in line with CMSIS data type definitions -->\n  <xs:simpleType name=\"dataTypeType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"uint8_t\"/>\n      <xs:enumeration value=\"uint16_t\"/>\n      <xs:enumeration value=\"uint32_t\"/>\n      <xs:enumeration value=\"uint64_t\"/>\n      <xs:enumeration value=\"int8_t\"/>\n      <xs:enumeration value=\"int16_t\"/>\n      <xs:enumeration value=\"int32_t\"/>\n      <xs:enumeration value=\"int64_t\"/>\n      <xs:enumeration value=\"uint8_t *\"/>\n      <xs:enumeration value=\"uint16_t *\"/>\n      <xs:enumeration value=\"uint32_t *\"/>\n      <xs:enumeration value=\"uint64_t *\"/>\n      <xs:enumeration value=\"int8_t *\"/>\n      <xs:enumeration value=\"int16_t *\"/>\n      <xs:enumeration value=\"int32_t *\"/>\n      <xs:enumeration value=\"int64_t *\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <!-- dimableIdentifierType specifies the subset and sequence of characters used for specifying identifiers that may contain %s from dim. -->\n  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->\n  <xs:simpleType name=\"dimableIdentifierType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"((%s)|(%s)[_A-Za-z]{1}[_A-Za-z0-9]*)|([_A-Za-z]{1}[_A-Za-z0-9]*(\\[%s\\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- identifierType specifies the subset and sequence of characters used for specifying identifiers that must not contain %s from dim. -->\n  <!-- this is particularly important as these are used in ANSI C Structures during the device header file generation -->\n  <xs:simpleType name=\"identifierType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[_A-Za-z0-9]*\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- V1.3: Protection Access Attribute Strings -->\n  <xs:simpleType name=\"protectionStringType\">\n    <xs:restriction base=\"xs:string\">\n      <!-- s = Secure                      -->\n      <!-- n = Non-secure                  -->\n      <!-- p = Privileged                  -->\n      <xs:pattern value=\"[snp]\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- V1.3: SAU Access Type -->\n  <xs:simpleType name=\"sauAccessType\">\n    <xs:restriction base=\"xs:string\">\n      <!-- c = non-secure Callable / Secure -->\n      <!-- n = Non-secure                   -->\n      <xs:pattern value=\"[cn]\"/>\n    </xs:restriction>\n  </xs:simpleType>\n\n  <!-- dimIndexType specifies the subset and sequence of characters used for specifying the sequence of indices in register arrays -->\n  <xs:simpleType name=\"dimIndexType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[0-9]+\\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\\s*[_0-9a-zA-Z]+)+\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- scaledNonNegativeInteger specifies the format in which numbers are represented in hexadecimal or decimal format -->\n  <xs:simpleType name=\"scaledNonNegativeInteger\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- enumeratedValueDataType specifies the number formats for the values in enumeratedValues -->\n  <xs:simpleType name=\"enumeratedValueDataType\">\n    <xs:restriction base=\"xs:string\">\n      <xs:pattern value=\"[+]?(((0x|0X)[0-9a-fA-F]+)|([0-9]+)|((#|0b)[01xX]+))\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- accessType specfies the pre-defined tokens for the available accesses -->\n  <xs:simpleType name=\"accessType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"read-only\"/>\n      <xs:enumeration value=\"write-only\"/>\n      <xs:enumeration value=\"read-write\"/>\n      <xs:enumeration value=\"writeOnce\"/>\n      <xs:enumeration value=\"read-writeOnce\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- modifiedWriteValuesType specifies the pre-defined tokens for the write side effects -->\n  <xs:simpleType name=\"modifiedWriteValuesType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"oneToClear\"/>\n      <xs:enumeration value=\"oneToSet\"/>\n      <xs:enumeration value=\"oneToToggle\"/>\n      <xs:enumeration value=\"zeroToClear\"/>\n      <xs:enumeration value=\"zeroToSet\"/>\n      <xs:enumeration value=\"zeroToToggle\"/>\n      <xs:enumeration value=\"clear\"/>\n      <xs:enumeration value=\"set\"/>\n      <xs:enumeration value=\"modify\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- readAction type specifies the pre-defined tokens for read side effects -->\n  <xs:simpleType name=\"readActionType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"clear\"/>\n      <xs:enumeration value=\"set\"/>\n      <xs:enumeration value=\"modify\"/>\n      <xs:enumeration value=\"modifyExternal\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- enumUsageType specifies the pre-defined tokens for selecting what access types an enumeratedValues set is associated with -->\n  <xs:simpleType name=\"enumUsageType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:enumeration value=\"read\"/>\n      <xs:enumeration value=\"write\"/>\n      <xs:enumeration value=\"read-write\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- bitRangeType specifies the bit numbers to be restricted values from 0 - 69 -->\n  <xs:simpleType name=\"bitRangeType\">\n    <xs:restriction base=\"xs:token\">\n      <xs:pattern value=\"\\[([0-4])?[0-9]:([0-4])?[0-9]\\]\"/>\n    </xs:restriction>\n  </xs:simpleType>\n  <!-- writeContraintType specifies how to describe the restriction of the allowed values that can be written to a resource -->\n  <xs:complexType name=\"writeConstraintType\">\n    <xs:choice>\n      <xs:element name=\"writeAsRead\" type=\"xs:boolean\"/>\n      <xs:element name=\"useEnumeratedValues\" type=\"xs:boolean\"/>\n      <xs:element name=\"range\">\n        <xs:complexType>\n          <xs:sequence>\n            <xs:element name=\"minimum\" type=\"scaledNonNegativeInteger\"/>\n            <xs:element name=\"maximum\" type=\"scaledNonNegativeInteger\"/>\n          </xs:sequence>\n        </xs:complexType>\n      </xs:element>\n    </xs:choice>\n  </xs:complexType>\n  <!-- addressBlockType specifies the elements to describe an address block -->\n  <xs:complexType name=\"addressBlockType\">\n    <xs:sequence>\n      <xs:element name=\"offset\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"size\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"usage\">\n        <xs:simpleType>\n          <xs:restriction base=\"xs:token\">\n            <xs:enumeration value=\"registers\"/>\n            <xs:enumeration value=\"buffer\"/>\n            <xs:enumeration value=\"reserved\"/>\n          </xs:restriction>\n        </xs:simpleType>\n      </xs:element>\n      <!-- Version 1.3.2: optional access protection for an address block s=secure n=non-secure p=privileged -->\n      <xs:element name=\"protection\" type=\"protectionStringType\" minOccurs=\"0\"/>\n    </xs:sequence>\n  </xs:complexType>\n  <!-- interruptType specifies how to describe an interrupt associated with a peripheral -->\n  <xs:complexType name=\"interruptType\">\n    <xs:sequence>\n      <xs:element name=\"name\" type=\"stringType\"/>\n      <xs:element name=\"description\" type=\"xs:string\" minOccurs=\"0\"/>\n      <xs:element name=\"value\" type=\"xs:integer\"/>\n    </xs:sequence>\n  </xs:complexType>\n  <!-- register properties group specifies register size, access permission and reset value\n       this is used in multiple locations. Settings are inherited downstream. -->\n  <xs:group name=\"registerPropertiesGroup\">\n    <xs:sequence>\n      <xs:element name=\"size\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n      <xs:element name=\"access\" type=\"accessType\" minOccurs=\"0\"/>\n      <!-- V 1.3: extended register access protection -->\n      <xs:element name=\"protection\" type=\"protectionStringType\" minOccurs=\"0\"/>\n      <xs:element name=\"resetValue\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n      <xs:element name=\"resetMask\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n    </xs:sequence>\n  </xs:group>\n  <!-- bitRangeLsbMsbStyle specifies the bit position of a field within a register\n       by specifying the least significant and the most significant bit position -->\n  <xs:group name=\"bitRangeLsbMsbStyle\">\n    <xs:sequence>\n      <xs:element name=\"lsb\"  type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"msb\"  type=\"scaledNonNegativeInteger\"/>\n    </xs:sequence>\n  </xs:group>\n  <!-- bitRangeOffsetWidthStyle specifies the bit position of a field within a register\n       by specifying the least significant bit position and the bitWidth of the field -->\n  <xs:group name=\"bitRangeOffsetWidthStyle\">\n    <xs:sequence>\n      <xs:element name=\"bitOffset\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"bitWidth\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n    </xs:sequence>\n  </xs:group>\n\n  <!-- dimElementGroup specifies the number of array elements (dim), the address offset\n       between to consecutive array elements and an a comma seperated list of strings\n       being used for identifying each element in the array -->\n  <xs:group name=\"dimElementGroup\">\n    <xs:sequence>\n      <xs:element name=\"dim\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"dimIncrement\" type=\"scaledNonNegativeInteger\"/>\n      <xs:element name=\"dimIndex\" type=\"dimIndexType\" minOccurs=\"0\"/>\n      <xs:element name=\"dimName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <xs:element name=\"dimArrayIndex\" type=\"dimArrayIndexType\" minOccurs=\"0\"/>\n    </xs:sequence>\n  </xs:group>\n\n  <xs:complexType name=\"cpuType\">\n    <xs:sequence>\n      <!-- V1.1: ARM processor name: Cortex-Mx / SCxxx -->\n      <xs:element name=\"name\" type=\"cpuNameType\"/>\n      <!-- V1.1: ARM defined revision of the cpu -->\n      <xs:element name=\"revision\" type=\"revisionType\"/>\n      <!-- V1.1: Endian specifies the endianess of the processor/device -->\n      <xs:element name=\"endian\" type=\"endianType\"/>\n      <!-- V1.1: mpuPresent specifies whether or not a memory protection unit is physically present -->\n      <xs:element name=\"mpuPresent\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.1: fpuPresent specifies whether or not a floating point hardware unit is physically present -->\n      <xs:element name=\"fpuPresent\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.2: fpuDP specifies a double precision floating point hardware unit is physically present-->\n      <xs:element name=\"fpuDP\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.3: dspPresent specifies whether the optional SIMD instructions are supported by processor -->\n      <xs:element name=\"dspPresent\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.2: icachePresent specifies that an instruction cache is physically present-->\n      <xs:element name=\"icachePresent\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.2: dcachePresent specifies that a data cache is physically present-->\n      <xs:element name=\"dcachePresent\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.2: itcmPresent specifies that an instruction tightly coupled memory is physically present-->\n      <xs:element name=\"itcmPresent\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.2: dtcmPresent specifies that an data tightly coupled memory is physically present-->\n      <xs:element name=\"dtcmPresent\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.1: vtorPresent is used for Cortex-M0+ based devices only. It indicates whether the Vector -->\n      <!--       Table Offset Register is implemented in the device or not                              -->\n      <xs:element name=\"vtorPresent\" type=\"xs:boolean\" minOccurs=\"0\"/>\n      <!-- V1.1: nvicPrioBits specifies the number of bits used by the Nested Vectored Interrupt Controller -->\n      <!--       for defining the priority level = # priority levels                                        -->\n      <xs:element name=\"nvicPrioBits\" type=\"scaledNonNegativeInteger\"/>\n      <!-- V1.1: vendorSystickConfig is set true if a custom system timer is implemented in the device -->\n      <!--       instead of the ARM specified SysTickTimer                                             -->\n      <xs:element name=\"vendorSystickConfig\" type=\"xs:boolean\"/>\n      <!-- V1.3: reports the total number of interrupts implemented by the device (optional) -->\n      <xs:element name=\"deviceNumInterrupts\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n      <!-- V1.3: sauRegions specifies the available number of address regions -->\n      <!--       if not specified a value of zero is assumed                  -->\n      <xs:element name=\"sauNumRegions\" type=\"scaledNonNegativeInteger\" minOccurs=\"0\"/>\n      <!-- V1.3: SAU Regions Configuration (if fully or partially predefined) -->\n      <xs:element name=\"sauRegionsConfig\" minOccurs=\"0\">\n        <xs:complexType>\n          <xs:sequence>\n            <xs:element name=\"region\" minOccurs=\"0\" maxOccurs=\"unbounded\">\n              <!-- addressBlockType specifies the elements to describe an address block -->\n              <xs:complexType>\n                <xs:sequence minOccurs=\"1\"   maxOccurs=\"unbounded\">\n                  <xs:element name=\"base\"    type=\"scaledNonNegativeInteger\"/>\n                  <xs:element name=\"limit\"   type=\"scaledNonNegativeInteger\"/>\n                  <xs:element name=\"access\"  type=\"sauAccessType\"/>\n                </xs:sequence>\n                <xs:attribute name=\"enabled\" type=\"xs:boolean\" use=\"optional\" default=\"true\"/>\n                <xs:attribute name=\"name\"    type=\"xs:string\"  use=\"optional\"/>\n              </xs:complexType>\n            </xs:element>\n          </xs:sequence>\n          <xs:attribute name=\"enabled\" type=\"xs:boolean\" use=\"optional\" default=\"true\"/>\n          <xs:attribute name=\"protectionWhenDisabled\" type=\"protectionStringType\" use=\"optional\" default=\"s\"/>\n        </xs:complexType>\n      </xs:element>\n     </xs:sequence>\n  </xs:complexType>\n\n  <xs:complexType name=\"enumeratedValueType\">\n    <xs:sequence>\n      <!-- name is a ANSI C indentifier representing the value (C Enumeration) -->\n      <xs:element name=\"name\" type=\"identifierType\"/>\n      <!-- description contains the details about the semantics/behavior specified by this value -->\n      <xs:element name=\"description\" type=\"stringType\" minOccurs=\"0\"/>\n      <xs:choice>\n        <xs:element name=\"value\" type=\"enumeratedValueDataType\"/>\n        <!-- isDefault specifies the name and description for all values that are not\n             specifically described individually -->\n        <xs:element name=\"isDefault\" type=\"xs:boolean\"/>\n      </xs:choice>\n    </xs:sequence>\n  </xs:complexType>\n\n  <xs:complexType name=\"enumerationType\">\n    <xs:sequence>\n      <!-- name specfies a reference to this enumeratedValues section for reuse purposes\n           this name does not appear in the System Viewer nor the Header File. -->\n      <xs:element name=\"name\" type=\"identifierType\" minOccurs=\"0\"/>\n      <!-- overrides the hierarchical enumeration type in the device header file. User is responsible for uniqueness across description -->\n      <xs:element name=\"headerEnumName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <!-- usage specifies whether this enumeration is to be used for read or write or\n                                                       (read and write) accesses -->\n      <xs:element name=\"usage\" type=\"enumUsageType\" minOccurs=\"0\"/>\n      <!-- enumeratedValue derivedFrom=<identifierType> -->\n      <xs:element name=\"enumeratedValue\" type=\"enumeratedValueType\" minOccurs=\"1\" maxOccurs=\"unbounded\"/>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"identifierType\" use=\"optional\"/>\n  </xs:complexType>\n\n  <xs:complexType name=\"dimArrayIndexType\">\n    <xs:sequence>\n      <xs:element name=\"headerEnumName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <xs:element name=\"enumeratedValue\" type=\"enumeratedValueType\" minOccurs=\"1\" maxOccurs=\"unbounded\"/>\n    </xs:sequence>\n  </xs:complexType>\n\n  <xs:complexType name=\"fieldType\">\n    <xs:sequence>\n      <xs:group    ref=\"dimElementGroup\" minOccurs=\"0\"/>\n      <!-- name specifies a field's name. The System Viewer and the device header file will\n           use the name of the field as identifier -->\n      <xs:element name=\"name\" type=\"dimableIdentifierType\"/>\n      <!-- description contains reference manual level information about the function and\n           options of a field -->\n      <xs:element name=\"description\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- alternative specifications of the bit position of the field within the register -->\n      <xs:choice minOccurs=\"1\" maxOccurs=\"1\">\n        <!-- bit field described by lsb followed by msb tag -->\n        <xs:group ref=\"bitRangeLsbMsbStyle\"/>\n        <!-- bit field described by bit offset relative to Bit0 + bit width of field -->\n        <xs:group ref=\"bitRangeOffsetWidthStyle\"/>\n        <!-- bit field described by [<msb>:<lsb>] -->\n        <xs:element name=\"bitRange\" type=\"bitRangeType\"/>\n      </xs:choice>\n      <!-- access describes the predefined permissions for the field. -->\n      <xs:element name=\"access\" type=\"accessType\" minOccurs=\"0\"/>\n      <!-- predefined description of write side effects -->\n      <xs:element name=\"modifiedWriteValues\" type=\"modifiedWriteValuesType\" minOccurs=\"0\"/>\n      <!-- writeContstraint specifies the subrange of allowed values -->\n      <xs:element name=\"writeConstraint\" type=\"writeConstraintType\" minOccurs=\"0\"/>\n      <!-- readAction specifies the read side effects. -->\n      <xs:element name=\"readAction\" type=\"readActionType\" minOccurs=\"0\"/>\n      <!-- enumeratedValues derivedFrom=<identifierType> -->\n      <xs:element name=\"enumeratedValues\" type=\"enumerationType\" minOccurs=\"0\" maxOccurs=\"2\">\n      </xs:element>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"dimableIdentifierType\" use=\"optional\"/>\n  </xs:complexType>\n\n  <xs:complexType name=\"fieldsType\">\n    <xs:sequence>\n      <!-- field derivedFrom=<identifierType> -->\n      <xs:element name=\"field\" type=\"fieldType\" minOccurs=\"1\" maxOccurs=\"unbounded\"/>\n    </xs:sequence>\n  </xs:complexType>\n\n  <xs:complexType name=\"registerType\">\n    <xs:sequence>\n      <xs:group    ref=\"dimElementGroup\" minOccurs=\"0\"/>\n      <!-- name specifies the name of the register. The register name is used by System Viewer and\n                                     device header file generator to represent a register -->\n      <xs:element name=\"name\" type=\"dimableIdentifierType\"/>\n      <!-- display name specifies a register name without the restritions of an ANSIS C identifier.\n                                     The use of this tag is discouraged because it does not allow consistency between\n                                     the System View and the device header file. -->\n      <xs:element name=\"displayName\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- description contains a reference manual level description about the register and it's purpose -->\n      <xs:element name=\"description\" type=\"stringType\" minOccurs=\"0\"/>\n      <xs:choice>\n        <!-- alternateGroup specifies the identifier of the subgroup a register belongs to.\n                                       This is useful if a register has a different description per mode but a single name -->\n        <xs:element name=\"alternateGroup\" type=\"identifierType\" minOccurs=\"0\"/>\n        <!-- V1.1: alternateRegister specifies an alternate register description for an address that is\n                                       already fully described. In this case the register name must be unique within the peripheral -->\n        <xs:element name=\"alternateRegister\" type=\"dimableIdentifierType\" minOccurs=\"0\"/>\n      </xs:choice>\n      <!-- addressOffset describes the address of the register relative to the baseOffset of the peripheral -->\n      <xs:element name=\"addressOffset\" type=\"scaledNonNegativeInteger\"/>\n      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and\n                                     reset value. These default values are inherited to all fields contained in this register -->\n      <xs:group    ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n      <!-- V1.1: dataType specifies a CMSIS compliant native dataType for a register (i.e. signed, unsigned, pointer) -->\n      <xs:element name=\"dataType\" type=\"dataTypeType\" minOccurs=\"0\"/>\n      <!-- modifiedWriteValues specifies the write side effects -->\n      <xs:element name=\"modifiedWriteValues\" type=\"modifiedWriteValuesType\" minOccurs=\"0\"/>\n      <!-- writeConstraint specifies the subset of allowed write values -->\n      <xs:element name=\"writeConstraint\" type=\"writeConstraintType\" minOccurs=\"0\"/>\n      <!-- readAcction specifies the read side effects -->\n      <xs:element name=\"readAction\" type=\"readActionType\" minOccurs=\"0\"/>\n      <!-- fields section contains all fields that belong to this register -->\n      <xs:element name=\"fields\" type=\"fieldsType\" minOccurs=\"0\" maxOccurs=\"1\"/>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"dimableIdentifierType\" use=\"optional\"/>\n  </xs:complexType>\n\n  <!-- V1.1: A cluster is a set of registers that are composed into a C data structure in the device header file -->\n  <xs:complexType name=\"clusterType\">\n    <xs:sequence>\n      <xs:group   ref=\"dimElementGroup\" minOccurs=\"0\"/>\n      <xs:element name=\"name\" type=\"dimableIdentifierType\"/>\n      <xs:element name=\"description\" type=\"xs:string\"/>\n      <!-- V1.1: alternateCluster specifies an alternative description for a cluster address range that is\n                 already fully described. In this case the cluster name must be unique within the peripheral -->\n      <xs:element name=\"alternateCluster\" type=\"dimableIdentifierType\" minOccurs=\"0\"/>\n      <!-- V1.1: headerStructName specifies the name for the cluster structure typedef\n                 used in the device header generation instead of the cluster name -->\n      <xs:element name=\"headerStructName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <xs:element name=\"addressOffset\" type=\"scaledNonNegativeInteger\"/>\n      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and\n                 reset value. These default values are inherited to all registers contained in this peripheral -->\n      <xs:group ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n      <xs:sequence>\n        <xs:choice minOccurs=\"1\" maxOccurs=\"unbounded\">\n          <xs:element name=\"register\" type=\"registerType\" minOccurs=\"0\" maxOccurs=\"unbounded\"/>\n          <!-- 1.3: nesting of cluster is supported -->\n          <xs:element name=\"cluster\" type=\"clusterType\" minOccurs=\"0\" maxOccurs=\"unbounded\"/>\n        </xs:choice>\n      </xs:sequence>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"dimableIdentifierType\" use=\"optional\"/>\n  </xs:complexType>\n\n  <!-- the registers section can have an arbitrary list of cluster and register sections -->\n  <xs:complexType name=\"registersType\">\n    <xs:choice minOccurs=\"1\" maxOccurs=\"unbounded\">\n      <xs:element name=\"cluster\" type=\"clusterType\"/>\n      <xs:element name=\"register\" type=\"registerType\"/>\n    </xs:choice>\n  </xs:complexType>\n\n  <xs:complexType name=\"peripheralType\">\n    <xs:sequence>\n      <!-- 1.3: specify uni-dimensional array of peripheral - requires name=\"<name>[%s]\" -->\n      <xs:group    ref=\"dimElementGroup\" minOccurs=\"0\"/>\n      <!-- name specifies the name of a peripheral. This name is used for the System View and device header file -->\n      <xs:element name=\"name\" type=\"dimableIdentifierType\"/>\n      <!-- version specifies the version of the peripheral descriptions -->\n      <xs:element name=\"version\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- description provides a high level functional description of the peripheral -->\n      <xs:element name=\"description\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- V1.1: alternatePeripheral specifies an alternative description for an address range that is\n           already fully by a peripheral described. In this case the peripheral name must be unique within the device description -->\n      <xs:element name=\"alternatePeripheral\" type=\"dimableIdentifierType\" minOccurs=\"0\"/>\n      <!-- groupName assigns this peripheral to a group of peripherals. This is only used bye the System View -->\n      <xs:element name=\"groupName\" type=\"xs:Name\" minOccurs=\"0\"/>\n      <!-- prependToName specifies a prefix that is placed in front of each register name of this peripheral.\n                         The device header file will show the registers in a C-Struct of the peripheral without the prefix. -->\n      <xs:element name=\"prependToName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <!-- appendToName is a postfix that is appended to each register name of this peripheral. The device header\n                         file will sho the registers in a C-Struct of the peripheral without the postfix -->\n      <xs:element name=\"appendToName\" type=\"identifierType\" minOccurs=\"0\"/>\n      <!-- V1.1: headerStructName specifies the name for the peripheral structure typedef\n                         used in the device header generation instead of the peripheral name -->\n      <xs:element name=\"headerStructName\" type=\"dimableIdentifierType\" minOccurs=\"0\"/>\n      <!-- disableCondition contains a logical expression based on constants and register or bit-field values\n                         if the condition is evaluated to true, the peripheral display will be disabled -->\n      <xs:element name=\"disableCondition\" type=\"stringType\" minOccurs=\"0\"/>\n      <!-- baseAddress specifies the absolute base address of a peripheral. For derived peripherals it is mandatory\n                         to specify a baseAddress. -->\n      <xs:element name=\"baseAddress\" type=\"scaledNonNegativeInteger\"/>\n      <!-- registerPropertiesGroup elements specify the default values for register size, access permission and\n                         reset value. These default values are inherited to all registers contained in this peripheral -->\n      <xs:group ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n      <!-- addressBlock specifies one or more address ranges that are assigned exclusively to this peripheral.\n                         derived peripherals may have no addressBlock, however none-derived peripherals are required to specify\n                         at least one address block -->\n      <xs:element name=\"addressBlock\" type=\"addressBlockType\" minOccurs=\"0\" maxOccurs=\"unbounded\"/>\n      <!-- interrupt specifies can specify one or more interrtupts by name, description and value -->\n      <xs:element name=\"interrupt\" type=\"interruptType\" minOccurs=\"0\" maxOccurs=\"unbounded\"/>\n      <!-- registers section contains all registers owned by the peripheral. In case a peripheral gets derived it does\n                        not have its own registers section, hence this section is optional. A unique peripheral without a\n                        registers section is not allowed -->\n      <xs:element name=\"registers\" type=\"registersType\" minOccurs=\"0\" maxOccurs=\"1\">\n      </xs:element>\n    </xs:sequence>\n    <xs:attribute name=\"derivedFrom\" type=\"dimableIdentifierType\" use=\"optional\"/>\n  </xs:complexType>\n\n  <!-- ==================================================== -->\n  <!-- The top level element of a description is the device -->\n  <!-- ==================================================== -->\n  <xs:element name=\"device\" nillable=\"true\">\n    <xs:complexType>\n      <xs:sequence>\n        <!-- V1.1: Vendor Name -->\n        <xs:element name=\"vendor\" type=\"stringType\" minOccurs=\"0\"/>\n        <!-- V1.1: Vendor ID - a short name for referring to the vendor (e.g. Texas Instruments = TI) -->\n        <xs:element name=\"vendorID\" type=\"identifierType\" minOccurs=\"0\"/>\n        <!-- name specifies the device name being described -->\n        <xs:element name=\"name\" type=\"identifierType\"/>\n        <!-- V1.1: series specifies the device series or family name -->\n        <xs:element name=\"series\" type=\"stringType\" minOccurs=\"0\"/>\n        <!-- version specifies the version of the device description -->\n        <xs:element name=\"version\" type=\"stringType\"/>\n        <!-- description is a string describing the device features (e.g. memory size, peripherals, etc.) -->\n        <xs:element name=\"description\" type=\"stringType\"/>\n        <!-- V1.1: licenseText specifies the file header section to be included in any derived file -->\n        <xs:element name=\"licenseText\" type=\"stringType\" minOccurs=\"0\"/>\n        <!-- V1.1: cpu specifies the details of the processor included in the device -->\n        <xs:element name=\"cpu\" type=\"cpuType\" minOccurs=\"0\"/>\n        <!-- V1.1: the tag specifies the filename without extension of the CMSIS System Device include file.\n             This tag is used by the header file generator for customizing the include statement referencing the\n             CMSIS system file within the CMSIS device header file. By default the filename is \"system_<device.name>\"\n             In cases a device series shares a single system header file, the name of the series shall be used\n             instead of the individual device name. -->\n        <xs:element name=\"headerSystemFilename\" type=\"identifierType\" minOccurs=\"0\"/>\n        <!-- V1.1: headerDefinitionPrefix specifies the string being prepended to all names of types defined in\n             generated device header file -->\n        <xs:element name=\"headerDefinitionsPrefix\" type=\"identifierType\" minOccurs=\"0\"/>\n        <!-- addressUnitBits specifies the size of the minimal addressable unit in bits -->\n        <xs:element name=\"addressUnitBits\" type=\"scaledNonNegativeInteger\"/>\n        <!-- width specifies the number of bits for the maximum single transfer size allowed by the bus interface.\n             This sets the maximum size of a single register that can be defined for an address space -->\n        <xs:element name=\"width\" type=\"scaledNonNegativeInteger\"/>\n        <!-- registerPropertiesGroup elements specify the default values for register size, access permission and\n             reset value -->\n        <xs:group ref=\"registerPropertiesGroup\" minOccurs=\"0\"/>\n\n        <!-- peripherals is containing all peripherals -->\n        <xs:element name=\"peripherals\">\n          <xs:complexType>\n            <xs:sequence>\n              <xs:element name=\"peripheral\" type=\"peripheralType\" minOccurs=\"1\" maxOccurs=\"unbounded\"/>\n            </xs:sequence>\n          </xs:complexType>\n        </xs:element>\n\n        <!-- Vendor Extensions: this section captures custom extensions. This section will be ignored by default -->\n        <xs:element name=\"vendorExtensions\" minOccurs=\"0\" maxOccurs=\"1\">\n          <xs:complexType>\n            <xs:sequence>\n              <xs:any namespace=\"##any\" processContents=\"lax\" minOccurs=\"0\" maxOccurs=\"unbounded\">\n              </xs:any>\n            </xs:sequence>\n          </xs:complexType>\n        </xs:element>\n      </xs:sequence>\n      <xs:attribute name=\"schemaVersion\" type=\"xs:decimal\" use=\"required\"/>\n    </xs:complexType>\n  </xs:element>\n</xs:schema>\n\n<!-- END OF FILE -->"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Utilities/check_header.sh",
    "content": "#!/bin/bash\n\nfunction usage {\n  echo \"$(basename $0) <file>\"\n  echo \"\"\n  echo \"Arguments:\"\n  echo \"  -h|--help         Show this usage text.\"\n  echo \"  -v|--verbose      Print verbose output.\"\n  echo \"  -d|--debug        Print debug output.\"\n  echo \"  -b|--base <sha>   Git commit SHA of merge base.\"\n  echo \"  <file>            The file to check the header.\"\n  echo \"\"\n}\n\nfunction echo-verbose {\n  if [[ $VERBOSE != 0 ]]; then\n    echo $1\n  fi\n}\n\nfunction echo-debug {\n  if [[ $DEBUG != 0 ]]; then\n    echo $1\n  fi\n}\n\nset -o pipefail\n\nVERBOSE=0\nDEBUG=0\nBASE_REV=\"\"\nPOSITIONAL=()\nwhile [[ $# -gt 0 ]]\ndo\n  key=\"$1\"\n\n  case $key in\n    '-h'|'--help')\n      usage\n      exit 1\n    ;;\n    '-v'|'--verbose')\n      VERBOSE=1\n    ;;\n    '-d'|'--debug')\n      DEBUG=1\n    ;;\n    '-b'|'--base')\n      shift\n      if git rev-parse $1 2>/dev/null >/dev/null; then\n        BASE_REV=$(git rev-parse $1)\n      else\n        echo \"Unknown revision: $1\" >&2\n      fi\n    ;;\n    *)    # unknown option\n      POSITIONAL+=(\"$1\") # save it in an array for later\n    ;;\n  esac\n  shift # past argument\ndone\nset -- \"${POSITIONAL[@]}\" # restore positional parameters\n\nif [[ -z \"$1\" ]] || [[ ! -f $1 ]]; then\n  echo -e \"No file given!\\n\"\n  usage\n  exit 1\nfi\n\nFILE=$1\nRESULT=0\n\necho \"Checking $1\"\n\necho-debug \"grep -E '@date\\s+([0-9]{2}\\. \\w+ [0-9]{4})' ${FILE} | sed -E 's/^.*@date\\s+([0-9]{2}\\. \\w+ [0-9]{4}).*/\\1/'\"\nFILE_DATE=$(grep -E '@date\\s+([0-9]{2}\\. \\w+ [0-9]{4})' ${FILE} | sed -E 's/^.*@date\\s+([0-9]{2}\\. \\w+ [0-9]{4}).*/\\1/')\necho-verbose \"File date: $FILE_DATE\"\nif [[ ! -z $FILE_DATE ]]; then\n  echo-debug \"git log -1 --pretty=\"format:%ad\" --date=\"format:%d. %B %Y\" ${FILE}\"\n  HEAD_DATE=$(git log -1 --pretty=\"format:%ad\" --date=\"format:%d. %B %Y\" ${FILE})\n  echo-verbose \"Head date: $HEAD_DATE\"\n  if [[ $HEAD_DATE != $FILE_DATE ]]; then\n    echo-debug \"grep -En \"@date.*${FILE_DATE}\" ${FILE} | cut -f1 -d:\"\n    FILE_DATE_LINE=$(grep -En \"@date.*${FILE_DATE}\" ${FILE} | cut -f1 -d:)\n    echo \"${FILE}:${FILE_DATE_LINE}:Please update file date to '$HEAD_DATE'.\" >&2\n    RESULT=1\n  fi\nfi\n\necho-debug \"grep -E '@version\\s+V?([0-9]+\\.[0-9]+(\\.[0-9]+)?)' ${FILE} | sed -E 's/^.*@version\\s+V?([0-9]+\\.[0-9]+(\\.[0-9]+)?).*/\\1/'\"\nFILE_VERSION=$(grep -E '@version\\s+V?([0-9]+\\.[0-9]+(\\.[0-9]+)?)' ${FILE} | sed -E 's/^.*@version\\s+V?([0-9]+\\.[0-9]+(\\.[0-9]+)?).*/\\1/')\necho-verbose \"File version: $FILE_VERSION\"\nif [[ ! -z $FILE_VERSION ]]; then\n  echo-debug \"grep -En \\\"@version.*${FILE_VERSION}\\\" ${FILE} | cut -f1 -d:\"\n  FILE_VERSION_LINE=$(grep -En \"@version.*${FILE_VERSION}\" ${FILE} | cut -f1 -d:)\n  echo-verbose \"File version line: $FILE_VERSION_LINE\"\n  echo-debug \"git log -1 --pretty=\\\"format:%H\\\" -- ${FILE}\"\n  HEAD_REV=$(git log -1 --pretty=\"format:%H\" -- ${FILE})\n  echo-verbose \"Head revision : $HEAD_REV\"\n  if [[ -z \"$BASE_REV\" ]] || [[ $HEAD_REV =~ ^$BASE_REV ]]; then\n    echo-debug \"git log -1 --pretty=\\\"format:%P\\\" -- ${FILE}\"\n    BASE_REV=$(git log -1 --pretty=\"format:%P\" -- ${FILE})\n  fi\n  echo-verbose \"Base revision : $BASE_REV\"\n  echo-debug \"git blame ${BASE_REV}..${HEAD_REV} -l -L ${FILE_VERSION_LINE},${FILE_VERSION_LINE} ${FILE}\"\n  BLAME=$(git blame ${BASE_REV}..${HEAD_REV} -l -L ${FILE_VERSION_LINE},${FILE_VERSION_LINE} ${FILE})\n  echo-debug \"git rev-parse $(sed -E 's/^[\\^]?([[:alnum:]]+).*/\\1/' <<<$BLAME)\"\n  BLAME_REV=$(git rev-parse $(sed -E 's/^[\\^]?([[:alnum:]]+).*/\\1/' <<<$BLAME))\n  echo-verbose \"Blame revision: $BLAME_REV\"\n  if [[ $BASE_REV == $BLAME_REV ]]; then\n    echo \"${FILE}:${FILE_VERSION_LINE}:Please increment file version.\" >&2\n    RESULT=1\n  fi\nfi\n\nexit $RESULT\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Utilities/check_links.sh",
    "content": "#!/bin/bash\n\nlinkchecker -F csv --check-extern $1\n\nOFS=$IFS\nIFS=$'\\n'\n\nfor line in $(grep -E '^[^#]' linkchecker-out.csv | tail -n +2); do \n  link=$(echo $line | cut -d';' -f 1)\n  file=$(echo $line | cut -d';' -f 2)\n  msg=$(echo $line | cut -d';' -f 4)\n  src=$(echo $file | sed -E 's/file:\\/\\/(.*)\\/Documentation\\/(\\w+)\\/.*/\\1\\/DoxyGen\\/\\2/')\n  if [ -d $src ]; then\n    origin=$(grep -Ern \"href=['\\\"]${link}['\\\"]\" $src/src/)\n    for o in $origin; do\n      ofile=$(echo $o | cut -d':' -f 1)\n      oline=$(echo $o | cut -d':' -f 2)\n      echo \"${ofile}:${oline};${link};${msg}\" >&2\n    done\n  fi\ndone\n\nIFS=$OFS\n\nexit 0\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Utilities/fetch_devtools.sh",
    "content": "#!/bin/bash\n\nPACKCHK_VERSION=1.3.95\nSVDCONV_VERSION=3.3.42\n\nREPO_URL=https://github.com/Open-CMSIS-Pack/devtools\nDOWNLOAD_URL=${REPO_URL}/releases/download/\nDIRNAME=$(dirname $0)\n\nset -o pipefail\n\nfunction usage {\n  echo \"$(basename $0) [-h|--help] [-f|--force]\"\n  echo \"\"\n  echo \"Arguments:\"\n  echo \"  -h|--help   Print this usage message and exit.\"\n  echo \"  -f|--force  Force (re)download.\"\n  echo \"\"\n  echo \"Environment:\"\n  echo \" curl\"\n  echo \" sha256sum\"\n  echo \"\"\n}\n\nfunction fetch {\n  mkdir -p ${DIRNAME}/$2\n  pushd ${DIRNAME}/$2 >/dev/null\n  curl -O -L $1\n  unzip -o $(basename $1)\n  rm $(basename $1)\n  popd >/dev/null\n}\n\nPOSITIONAL=()\nwhile [[ $# -gt 0 ]]\ndo\n  key=\"$1\"\n\n  case $key in\n    '-h'|'--help')\n      usage\n      exit 1\n    ;;\n    '-f'|'--force')\n      FORCE=1\n    ;;\n    *)    # unknown option\n      POSITIONAL+=(\"$1\") # save it in an array for later\n    ;;\n  esac\n  shift # past argument\ndone\nset -- \"${POSITIONAL[@]}\" # restore positional parameters\n\nfetch \"${DOWNLOAD_URL}/tools%2Fpackchk%2F${PACKCHK_VERSION}/packchk-${PACKCHK_VERSION}-darwin64.zip\" Darwin64\nfetch \"${DOWNLOAD_URL}/tools%2Fpackchk%2F${PACKCHK_VERSION}/packchk-${PACKCHK_VERSION}-linux64.zip\" Linux64\nfetch \"${DOWNLOAD_URL}/tools%2Fpackchk%2F${PACKCHK_VERSION}/packchk-${PACKCHK_VERSION}-windows64.zip\" Win32\n\nfetch \"${DOWNLOAD_URL}/tools%2Fsvdconv%2F${SVDCONV_VERSION}/svdconv-${SVDCONV_VERSION}-darwin64.zip\" Darwin64\nfetch \"${DOWNLOAD_URL}/tools%2Fsvdconv%2F${SVDCONV_VERSION}/svdconv-${SVDCONV_VERSION}-linux64.zip\" Linux64\nfetch \"${DOWNLOAD_URL}/tools%2Fsvdconv%2F${SVDCONV_VERSION}/svdconv-${SVDCONV_VERSION}-windows64.zip\" Win32\n\nexit 0\n"
  },
  {
    "path": "external/CMSIS_5/CMSIS/Utilities/gen_pack.sh",
    "content": "#!/bin/bash\n# Version: 1.5\n# Date: 2022-04-06\n# This bash script generates a CMSIS Software Pack:\n#\n# Pre-requisites:\n# - bash shell (for Windows: install git for Windows)\n# - git in path (for Windows: install git for Windows)\n# - 7z in path (zip archiving utility)\n#   e.g. Ubuntu: sudo apt-get install p7zip-full p7zip-rar)\n# - xmllint in path (XML schema validation; available only for Linux)\n#\n# Preparation steps:\n# - Generate documentation, see CMSIS/DoxyGen/gen_doc.sh\n# - Populate utilities, see\n#   - CMSIS/Utilities/fetch_devtools.sh\n# - Populate pre-built libraries, see\n#   - CMSIS/RTOS/RTX/LIB/fetch_libs.sh\n#   - CMSIS/RTOS2/RTX/Library/fetch_libs.sh\n#\n\n############### EDIT BELOW ###############\n# Extend Path environment variable locally\n#\n\nset -o pipefail\n\nfunction usage {\n  echo \"$(basename $0) [-h|--help] [<pdsc>]\"\n  echo \"\"\n  echo \"Arguments:\"\n  echo \"  -h|--help        Print this usage message and exit.\"\n  echo \"  --ignore_errors  Ignore errors detected during pack generation.\"\n  echo \"  --version <VER>  Force pack version to <VER>.\"\n  echo \"  pdsc             The pack description to generate the pack for.\"\n  echo \"\"\n  echo \"Environment:\"\n  echo \" 7z\"\n  if [ $(uname -s) = \"Linux\" ]; then\n    echo \" xmllint\"\n  fi\n  echo \"\"\n}\n\nfunction pack_version()\n{\n  local version=$(grep -Pzo \"(?s)<releases>\\s+<release version=\\\"([^\\\"]+)\\\"\" \"$1\" | tr -d '\\0' | tail -n 1 | sed -r -e 's/.*version=\"([^\"]+)\"/\\1/g')\n  echo \"PDSC version: '$version'\" >&2\n  echo $version\n}\n\nfunction git_describe()\n{\n  if git rev-parse --git-dir 2>&1 >/dev/null; then\n    local gitversion=$(git describe --tags --match $1* --abbrev=9 2>/dev/null || echo \"$1-dirty-0-g$(git describe --tags --match $1* --always --abbrev=9 2>/dev/null)\")\n    local version=$(echo $gitversion | sed -r -e 's/-([0-9]+)-(g[0-9a-f]{9})/\\1+\\2/')\n    if [[ $version != $1 ]] && [[ $version == $gitversion ]]; then\n        version+=0\n    fi\n    echo \"Git version: '$version'\" >&2\n    echo $version\n  else\n    echo \"No Git repository: '$1-nogit'\" >&2\n    echo \"$1-nogit\"\n  fi\n}\n\nfunction patch_pdsc()\n{\n  if [[ \"$2\" != \"$3\" ]]; then\n    echo \"Updating latest release tag with version '$3'\"\n    sed -r -i -e \"s/<release version=\\\"$2\\\"/<release version=\\\"$3\\\"/\" $1\n  fi\n}\n\nIGNORE_ERRORS=0\nVERSION=\nPOSITIONAL=()\nwhile [[ $# -gt 0 ]]\ndo\n  key=\"$1\"\n\n  case $key in\n    '-h'|'--help')\n      usage\n      exit 1\n    ;;\n    '--ignore-errors')\n      IGNORE_ERRORS=1\n      shift # past argument\n    ;;\n    '--version')\n      shift # past argument\n      VERSION=$1\n      shift # past argument\n    ;;\n    *)    # unknown option\n      POSITIONAL+=(\"$1\") # save it in an array for later\n      shift # past argument\n    ;;\n  esac\ndone\nset -- \"${POSITIONAL[@]}\" # restore positional parameters\n\nOS=$(uname -s)\ncase $OS in\n  'Linux')\n    CMSIS_TOOLSDIR=\"./CMSIS/Utilities/Linux64\"\n    ;;\n  'WindowsNT'|MINGW*|CYGWIN*)\n    CMSIS_TOOLSDIR=\"./CMSIS/Utilities/Win32\"\n    ;;\n  'Darwin')\n    CMSIS_TOOLSDIR=\"./CMSIS/Utilities/Darwin64\"\n    ;;\n  *)\n    echo \"Error: unrecognized OS $OS\"\n    exit 1\n    ;;\nesac\n\nPATH_TO_ADD=\"$CMSIS_TOOLSDIR\"\n\n[[ \":$PATH:\" != *\":${PATH_TO_ADD}:\"* ]] && PATH=\"${PATH}:${PATH_TO_ADD}\"\necho $PATH_TO_ADD appended to PATH\necho \" \"\n\n# Pack warehouse directory - destination\nPACK_WAREHOUSE=./output\n\n# Temporary pack build directory\nPACK_BUILD=./build\n\n# Specify directory names to be added to pack base directory\nPACK_DIRS=\"\n  Device\n  CMSIS/Core/Include\n  CMSIS/Core/Template\n  CMSIS/Core_A\n  CMSIS/DAP\n  CMSIS/Driver\n  CMSIS/RTOS\n  CMSIS/RTOS2\n  CMSIS/Utilities/Win32\n  CMSIS/Utilities/Linux64\n  CMSIS/Utilities/Darwin64\n  CMSIS/Documentation\n\"\n\n# Specify file names to be added to pack base directory\nPACK_BASE_FILES=\"\n  LICENSE.txt\n  CMSIS/Utilities/ARM_Example.*\n  CMSIS/Utilities/*.xsd\n\"\n\n# Specify file names to be deleted from pack build directory\nPACK_DELETE_FILES=\"\n  CMSIS/RTOS/CMSIS_RTOS_Tutorial.pdf\n  CMSIS/RTOS/RTX/LIB/fetch_libs.sh\n  CMSIS/RTOS/RTX/LIB/*.zip\n  CMSIS/RTOS2/RTX/Library/fetch_libs.sh\n  CMSIS/RTOS2/RTX/Library/*.zip\n  CMSIS/RTOS2/RTX/Library/build.py\n\"\n\n# Specify patches to be applied\nPACK_PATCH_FILES=\"\"\n\n############ DO NOT EDIT BELOW ###########\necho Starting CMSIS-Pack Generation: `date`\n# Zip utility check\nZIP=7z\ntype -a \"${ZIP}\"\nerrorlevel=$?\nif [ $errorlevel -gt 0 ]\n  then\n  echo \"Error: No 7zip Utility found\"\n  echo \"Action: Add 7zip to your path\"\n  echo \" \"\n  exit 1\nfi\n\n# Pack checking utility check\nPACKCHK=packchk\ntype -a ${PACKCHK}\nerrorlevel=$?\nif [ $errorlevel != 0 ]; then\n  echo \"Error: No packchk Utility found\"\n  echo \"Action: Add packchk to your path\"\n  echo \"Hint: Included in CMSIS Pack:\"\n  echo \"$CMSIS_PACK_ROOT/ARM/CMSIS/<version>/CMSIS/Utilities/<os>/\"\n  echo \" \"\n  if [[ $IGNORE_ERRORS == 0 ]]; then\n    exit 1\n  fi\nfi\necho \" \"\n\n# Locate Package Description file\n# check whether there is more than one pdsc file\nNUM_PDSCS=$(ls -1 *.pdsc | wc -l)\nPACK_DESCRIPTION_FILE=$(ls *.pdsc)\nif [[ -n $1 && -f $1 ]]; then\n  PACK_DESCRIPTION_FILE=$1\nelif [ ${NUM_PDSCS} -lt 1 ]; then\n  echo \"Error: No *.pdsc file found in current directory\"\n  echo \" \"\n  exit 1\nelif [ ${NUM_PDSCS} -gt 1 ]; then\n  echo \"Error: Only one PDSC file allowed in directory structure:\"\n  echo \"Found:\"\n  echo \"$PACK_DESCRIPTION_FILE\"\n  echo \"Action: Provide PDSC file explicitly!\"\n  echo \" \"\n  usage\n  exit 1\nfi\n\nSAVEIFS=$IFS\nIFS=.\nset ${PACK_DESCRIPTION_FILE}\n# Pack Vendor\nPACK_VENDOR=$1\n# Pack Name\nPACK_NAME=$2\necho \"Generating Pack: for $PACK_VENDOR.$PACK_NAME\"\necho \" \"\nIFS=$SAVEIFS\n\n#if $PACK_BUILD directory does not exist, create it.\nif [ ! -d \"$PACK_BUILD\" ]; then\n  mkdir -p \"$PACK_BUILD\"\nfi\n\n# Copy files into build base directory: $PACK_BUILD\n# pdsc file is mandatory in base directory:\ncp -f \"./${PACK_VENDOR}.${PACK_NAME}.pdsc\" \"${PACK_BUILD}\"\n\n# Add directories\necho Adding directories to pack:\necho \"${PACK_DIRS}\"\necho \" \"\nfor d in ${PACK_DIRS}; do\n  cp -r --parents \"$d\" \"${PACK_BUILD}\"\ndone\n\n# Add files\necho Adding files to pack:\necho \"${PACK_BASE_FILES}\"\necho \" \"\nif [ ! -x ${PACK_BASE_FILES+x} ]; then\n  for f in ${PACK_BASE_FILES}; do\n    cp -f --parents \"$f\" $PACK_BUILD/\n  done\nfi\n\n# Delete files\necho Deleting files from pack:\necho \"${PACK_DELETE_FILES}\"\necho \" \"\nif [ ! -x ${PACK_DELETE_FILES+x} ]; then\n  for f in ${PACK_DELETE_FILES}; do\n    find $PACK_BUILD/$(dirname \"$f\") -name $(basename \"$f\") -delete\n  done\nfi\n\n# Apply patches\necho Applying patches to pack:\necho \"${PACK_PATCH_FILES}\"\necho \" \"\nif [ ! -x ${PACK_PATCH_FILES+x} ]; then\n  CWD=$(pwd)\n  pushd $PACK_BUILD > /dev/null\n  for f in ${PACK_PATCH_FILES}; do\n    patch -p0 -t -i \"${CWD}/${f}\"\n  done\n  popd > /dev/null\nfi\n\n# Create checksum file\necho Creating checksum file:\npushd $PACK_BUILD > /dev/null\nfind . -type f -exec sha1sum {} + > ../${PACK_VENDOR}.${PACK_NAME}.sha1\nmv ../${PACK_VENDOR}.${PACK_NAME}.sha1 .\npopd > /dev/null\n\n# Run Schema Check (for Linux only):\n# sudo apt-get install libxml2-utils\n\nif [ $(uname -s) = \"Linux\" ]; then\n  echo \"Running schema check for ${PACK_VENDOR}.${PACK_NAME}.pdsc\"\n  curl https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/main/schema/PACK.xsd -o CMSIS/Utilities/PACK.xsd\n  xmllint --noout --schema \"$(realpath -m ./CMSIS/Utilities/PACK.xsd)\" \"${PACK_BUILD}/${PACK_VENDOR}.${PACK_NAME}.pdsc\"\n  errorlevel=$?\n  if [ $errorlevel -ne 0 ]; then\n    echo \"build aborted: Schema check of $PACK_VENDOR.$PACK_NAME.pdsc against PACK.xsd failed\"\n    echo \" \"\n    if [[ $IGNORE_ERRORS == 0 ]]; then\n        exit 1\n    fi\n  fi\nelse\n  echo \"Use MDK PackInstaller to run schema validation for $PACK_VENDOR.$PACK_NAME.pdsc\"\nfi\n\n# Patch pack version\necho \"Checking PDCS version against Git...\"\npdsc_version=$(pack_version \"${PACK_BUILD}/${PACK_VENDOR}.${PACK_NAME}.pdsc\")\nif [ -z $VERSION ]; then\n  VERSION=$(git_describe ${pdsc_version})\nfi\npatch_pdsc \"${PACK_BUILD}/${PACK_VENDOR}.${PACK_NAME}.pdsc\" ${pdsc_version} ${VERSION}\n\n# Run Pack Check and generate PackName file with version\n\"${PACKCHK}\" \"${PACK_BUILD}/${PACK_VENDOR}.${PACK_NAME}.pdsc\" \\\n  -n ${PACK_BUILD}/PackName.txt \\\n  -x M353 -x M364 -x M335 -x M336\nerrorlevel=$?\nif [ $errorlevel -ne 0 ]; then\n  echo \"build aborted: pack check failed\"\n  echo \"Check preparation steps if missing files are reported!\"\n  echo \" \"\n  if [[ $IGNORE_ERRORS == 0 ]]; then\n    exit 1\n  fi\nfi\n\nPACKNAME=$(cat ${PACK_BUILD}/PackName.txt)\nrm -rf ${PACK_BUILD}/PackName.txt\n\n# Archiving\n# $ZIP a $PACKNAME\necho \"creating pack file $PACKNAME\"\n#if $PACK_WAREHOUSE directory does not exist create it\nif [ ! -d \"$PACK_WAREHOUSE\" ]; then\n  mkdir -p \"$PACK_WAREHOUSE\"\nfi\npushd \"$PACK_WAREHOUSE\" > /dev/null\nPACK_WAREHOUSE=$(pwd)\npopd  > /dev/null\npushd \"$PACK_BUILD\" > /dev/null\nPACK_BUILD=$(pwd)\n\"$ZIP\" a \"$PACK_WAREHOUSE/$PACKNAME\" -tzip\npopd  > /dev/null\nerrorlevel=$?\nif [ $errorlevel -ne 0 ]; then\n  echo \"build aborted: archiving failed\"\n  exit 1\nfi\n\necho \"build of pack succeeded\"\n# Clean up\necho \"cleaning up ...\"\n\nrm -rf \"$PACK_BUILD\"\necho \" \"\n\necho Completed CMSIS-Pack Generation: $(date)\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Config/mem_ARMCA5.h",
    "content": "/**************************************************************************//**\n * @file     mem_ARMCA5.h\n * @brief    Memory base and size definitions (used in scatter file)\n * @version  V1.1.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __MEM_ARMCA5_H\n#define __MEM_ARMCA5_H\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap size definition\n *----------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n/*--------------------- ROM Configuration ------------------------------------\n//\n// <h> ROM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>\n//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE       0x80000000\n#define __ROM_SIZE       0x00200000\n\n/*--------------------- RAM Configuration -----------------------------------\n// <h> RAM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>\n//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n//   <h> Data Sections\n//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//   </h>\n//   <h> Stack / Heap Configuration\n//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <h> Exceptional Modes\n//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     </h>\n//   </h>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE       0x80200000\n#define __RAM_SIZE       0x00200000\n\n#define __RW_DATA_SIZE   0x00100000\n#define __ZI_DATA_SIZE   0x000F0000\n\n#define __STACK_SIZE     0x00001000\n#define __HEAP_SIZE      0x00008000\n\n#define __UND_STACK_SIZE 0x00000100\n#define __ABT_STACK_SIZE 0x00000100\n#define __SVC_STACK_SIZE 0x00000100\n#define __IRQ_STACK_SIZE 0x00000100\n#define __FIQ_STACK_SIZE 0x00000100\n\n/*----------------------------------------------------------------------------*/\n\n/*--------------------- TTB Configuration ------------------------------------\n//\n// <h> TTB Configuration\n//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned\n//   <i> The TLB L2 entries are placed after the L1 in the MMU config\n//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>\n//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __TTB_BASE       0x80500000\n#define __TTB_SIZE       0x00005000\n\n#endif /* __MEM_ARMCA5_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Config/system_ARMCA5.h",
    "content": "/******************************************************************************\n * @file     system_ARMCA5.h\n * @brief    CMSIS Device System Header File for Arm Cortex-A5 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __SYSTEM_ARMCA5_H\n#define __SYSTEM_ARMCA5_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SYSTEM_ARMCA5_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Include/ARMCA5.h",
    "content": "/******************************************************************************\n * @file     ARMCA5.h\n * @brief    CMSIS Cortex-A5 Core Peripheral Access Layer Header File \n * @version  V1.1.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __ARMCA5_H__\n#define __ARMCA5_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/******  SGI Interrupts Numbers                 ****************************************/\n  SGI0_IRQn            =  0,        /*!< Software Generated Interrupt 0 */\n  SGI1_IRQn            =  1,        /*!< Software Generated Interrupt 1 */\n  SGI2_IRQn            =  2,        /*!< Software Generated Interrupt 2 */\n  SGI3_IRQn            =  3,        /*!< Software Generated Interrupt 3 */\n  SGI4_IRQn            =  4,        /*!< Software Generated Interrupt 4 */\n  SGI5_IRQn            =  5,        /*!< Software Generated Interrupt 5 */\n  SGI6_IRQn            =  6,        /*!< Software Generated Interrupt 6 */\n  SGI7_IRQn            =  7,        /*!< Software Generated Interrupt 7 */\n  SGI8_IRQn            =  8,        /*!< Software Generated Interrupt 8 */\n  SGI9_IRQn            =  9,        /*!< Software Generated Interrupt 9 */\n  SGI10_IRQn           = 10,        /*!< Software Generated Interrupt 10 */\n  SGI11_IRQn           = 11,        /*!< Software Generated Interrupt 11 */\n  SGI12_IRQn           = 12,        /*!< Software Generated Interrupt 12 */\n  SGI13_IRQn           = 13,        /*!< Software Generated Interrupt 13 */\n  SGI14_IRQn           = 14,        /*!< Software Generated Interrupt 14 */\n  SGI15_IRQn           = 15,        /*!< Software Generated Interrupt 15 */\n\n/******  Cortex-A5 Processor Exceptions Numbers ****************************************/\n  GlobalTimer_IRQn     = 27,        /*!< Global Timer Interrupt                        */\n  PrivTimer_IRQn       = 29,        /*!< Private Timer Interrupt                       */\n  PrivWatchdog_IRQn    = 30,        /*!< Private Watchdog Interrupt                    */\n\n/******  Platform Exceptions Numbers ***************************************************/\n  Watchdog_IRQn        = 32,        /*!< SP805 Interrupt        */\n  Timer0_IRQn          = 34,        /*!< SP804 Interrupt        */\n  Timer1_IRQn          = 35,        /*!< SP804 Interrupt        */\n  RTClock_IRQn         = 36,        /*!< PL031 Interrupt        */\n  UART0_IRQn           = 37,        /*!< PL011 Interrupt        */\n  UART1_IRQn           = 38,        /*!< PL011 Interrupt        */\n  UART2_IRQn           = 39,        /*!< PL011 Interrupt        */\n  UART3_IRQn           = 40,        /*!< PL011 Interrupt        */\n  MCI0_IRQn            = 41,        /*!< PL180 Interrupt (1st)  */\n  MCI1_IRQn            = 42,        /*!< PL180 Interrupt (2nd)  */\n  AACI_IRQn            = 43,        /*!< PL041 Interrupt        */\n  Keyboard_IRQn        = 44,        /*!< PL050 Interrupt        */\n  Mouse_IRQn           = 45,        /*!< PL050 Interrupt        */\n  CLCD_IRQn            = 46,        /*!< PL111 Interrupt        */\n  Ethernet_IRQn        = 47,        /*!< SMSC_91C111 Interrupt  */\n  VFS2_IRQn            = 73,        /*!< VFS2 Interrupt         */\n} IRQn_Type;\n\n/******************************************************************************/\n/*                         Peripheral memory map                              */\n/******************************************************************************/\n\n/* Peripheral and RAM base address */\n#define VE_A5_MP_FLASH_BASE0                  (0x00000000UL)                                /*!< (FLASH0     ) Base Address */\n#define VE_A5_MP_FLASH_BASE1                  (0x0C000000UL)                                /*!< (FLASH1     ) Base Address */\n#define VE_A5_MP_SRAM_BASE                    (0x14000000UL)                                /*!< (SRAM       ) Base Address */\n#define VE_A5_MP_PERIPH_BASE_CS2              (0x18000000UL)                                /*!< (Peripheral ) Base Address */\n#define VE_A5_MP_VRAM_BASE                    (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS2)     /*!< (VRAM       ) Base Address */\n#define VE_A5_MP_ETHERNET_BASE                (0x02000000UL + VE_A5_MP_PERIPH_BASE_CS2)     /*!< (ETHERNET   ) Base Address */\n#define VE_A5_MP_USB_BASE                     (0x03000000UL + VE_A5_MP_PERIPH_BASE_CS2)     /*!< (USB        ) Base Address */\n#define VE_A5_MP_PERIPH_BASE_CS3              (0x1C000000UL)                                /*!< (Peripheral ) Base Address */\n#define VE_A5_MP_DAP_BASE                     (0x00000000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (LOCAL DAP  ) Base Address */\n#define VE_A5_MP_SYSTEM_REG_BASE              (0x00010000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (SYSTEM REG ) Base Address */\n#define VE_A5_MP_SERIAL_BASE                  (0x00030000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (SERIAL     ) Base Address */\n#define VE_A5_MP_AACI_BASE                    (0x00040000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (AACI       ) Base Address */\n#define VE_A5_MP_MMCI_BASE                    (0x00050000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (MMCI       ) Base Address */\n#define VE_A5_MP_KMI0_BASE                    (0x00060000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (KMI0       ) Base Address */\n#define VE_A5_MP_UART_BASE                    (0x00090000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (UART       ) Base Address */\n#define VE_A5_MP_WDT_BASE                     (0x000F0000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (WDT        ) Base Address */\n#define VE_A5_MP_TIMER_BASE                   (0x00110000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (TIMER      ) Base Address */\n#define VE_A5_MP_DVI_BASE                     (0x00160000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (DVI        ) Base Address */\n#define VE_A5_MP_RTC_BASE                     (0x00170000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (RTC        ) Base Address */\n#define VE_A5_MP_UART4_BASE                   (0x001B0000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (UART4      ) Base Address */\n#define VE_A5_MP_CLCD_BASE                    (0x001F0000UL + VE_A5_MP_PERIPH_BASE_CS3)     /*!< (CLCD       ) Base Address */\n#define VE_A5_MP_PRIVATE_PERIPH_BASE          (0x2C000000UL)                                /*!< (Peripheral ) Base Address */\n#define VE_A5_MP_GIC_DISTRIBUTOR_BASE         (0x00001000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST   ) Base Address */\n#define VE_A5_MP_GIC_INTERFACE_BASE           (0x00000100UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */\n#define VE_A5_MP_PRIVATE_TIMER                (0x00000600UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (PTIM       ) Base Address */\n#define VE_A5_MP_PL310_BASE                   (0x000F0000UL + VE_A5_MP_PRIVATE_PERIPH_BASE) /*!< (L2C-310    ) Base Address */\n#define VE_A5_MP_SSRAM_BASE                   (0x2E000000UL)                                /*!< (System SRAM) Base Address */\n#define VE_A5_MP_DRAM_BASE                    (0x80000000UL)                                /*!< (DRAM       ) Base Address */\n#define GIC_DISTRIBUTOR_BASE                  VE_A5_MP_GIC_DISTRIBUTOR_BASE\n#define GIC_INTERFACE_BASE                    VE_A5_MP_GIC_INTERFACE_BASE\n#define TIMER_BASE                            VE_A5_MP_PRIVATE_TIMER\n\n//The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache.\n//Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort.\n#define L2C_310_BASE                          VE_A5_MP_PL310_BASE\n\n/* --------  Configuration of the Cortex-A5 Processor and Core Peripherals  ------- */\n#define __CA_REV        0x0000U    /* Core revision r0p0                            */\n#define __CORTEX_A           5U    /* Cortex-A5 Core                                */\n#define __FPU_PRESENT        1U    /* FPU present                                   */\n#define __GIC_PRESENT        1U    /* GIC present                                   */\n#define __TIM_PRESENT        1U    /* TIM present                                   */\n#define __L2C_PRESENT        0U    /* L2C present                                   */\n\n#include \"core_ca.h\"\n#include <system_ARMCA5.h>\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  // __ARMCA5_H__\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/AC5/ARMCA5.sct",
    "content": "#! armcc -E\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA5.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/AC5/startup_ARMCA5.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA5.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA5.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors       (void) __attribute__ ((section(\"RESET\")));\nvoid Reset_Handler (void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n__ASM void Vectors(void) {\n  PRESERVE8\n  \n  IMPORT Undef_Handler\n  IMPORT SVC_Handler\n  IMPORT PAbt_Handler\n  IMPORT DAbt_Handler\n  IMPORT IRQ_Handler\n  IMPORT FIQ_Handler\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__ASM void Reset_Handler(void) {\n  PRESERVE8\n\n  // Mask interrupts\n  CPSID  if                           \n\n  // Put any cores other than 0 to sleep\n  MRC    p15, 0, R0, c0, c0, 5       // Read MPIDR\n  ANDS   R0, R0, #3\ngoToSleep\n  WFINE\n  BNE    goToSleep\n\n  // Reset SCTLR Settings\n  MRC    p15, 0, R0, c1, c0, 0       // Read CP15 System Control register\n  BIC    R0, R0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache\n  BIC    R0, R0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache\n  BIC    R0, R0, #0x1                // Clear M bit  0 to disable MMU\n  BIC    R0, R0, #(0x1 << 11)        // Clear Z bit 11 to disable branch prediction\n  BIC    R0, R0, #(0x1 << 13)        // Clear V bit 13 to disable hivecs\n  MCR    p15, 0, R0, c1, c0, 0       // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC    p15, 0, r0, c1, c0, 1       // Read CP15 Auxiliary Control Register\n  ORR    r0, r0, #(1 <<  1)          // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR    p15, 0, r0, c1, c0, 1       // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exceptional mode\n  IMPORT |Image$$FIQ_STACK$$ZI$$Limit|\n  IMPORT |Image$$IRQ_STACK$$ZI$$Limit|\n  IMPORT |Image$$SVC_STACK$$ZI$$Limit|\n  IMPORT |Image$$ABT_STACK$$ZI$$Limit|\n  IMPORT |Image$$UND_STACK$$ZI$$Limit|\n  IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|\n  CPS    #0x11\n  LDR    SP, =|Image$$FIQ_STACK$$ZI$$Limit|\n  CPS    #0x12\n  LDR    SP, =|Image$$IRQ_STACK$$ZI$$Limit|\n  CPS    #0x13\n  LDR    SP, =|Image$$SVC_STACK$$ZI$$Limit|\n  CPS    #0x17\n  LDR    SP, =|Image$$ABT_STACK$$ZI$$Limit|\n  CPS    #0x1B\n  LDR    SP, =|Image$$UND_STACK$$ZI$$Limit|\n  CPS    #0x1F\n  LDR    SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|\n\n  // Call SystemInit\n  IMPORT SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __main\n  IMPORT __main\n  BL     __main\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/AC6/ARMCA5.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA5.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/AC6/startup_ARMCA5.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA5.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA5.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void) __attribute__ ((noreturn));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n  \"LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \\n\"\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n  \"BL     __main                                   \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/ARMCA5.ld",
    "content": "#include \"mem_ARMCA5.h\" \n\nMEMORY\n{\n  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE \n  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n\n        Image$$VECTORS$$Base = .;\n        * (RESET)\n        KEEP(*(.isr_vector))\n        Image$$VECTORS$$Limit = .;\n\n        *(SVC_TABLE)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        /* .ctors */\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        /* .dtors */\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        Image$$RO_DATA$$Base = .;\n        *(.rodata*)\n        Image$$RO_DATA$$Limit = .;\n\n        KEEP(*(.eh_frame*))\n    } > ROM\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > ROM\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > ROM\n    __exidx_end = .;\n\n\n    .copy.table :\n    {\n        . = ALIGN(4);\n        __copy_table_start__ = .;\n        LONG (__etext)\n        LONG (__data_start__)\n        LONG (__data_end__ - __data_start__)\n        __copy_table_end__ = .;\n    } > ROM\n\n    .zero.table :\n    {\n        . = ALIGN(4);\n        __zero_table_start__ = .;\n        LONG (__bss_start__)\n        LONG (__bss_end__ - __bss_start__)\n        __zero_table_end__ = .;\n    } > ROM\n\n    __etext = .;\n        \n    .ttb :\n    {\n        Image$$TTB$$ZI$$Base = .;\n        . += __TTB_SIZE;\n        Image$$TTB$$ZI$$Limit = .;\n    } > L_TTB\n\n    .data : AT (__etext)\n    {\n        Image$$RW_DATA$$Base = .;\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n        Image$$RW_DATA$$Limit = .;\n\n        . = ALIGN(4);\n        /* preinit data */\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        /* init data */\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        /* finit data */\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        /* All data end */\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss ALIGN(0x400):\n    {\n        Image$$ZI_DATA$$Base = .;\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$ZI_DATA$$Limit = .;\n        __end__ = .;\n        end = __end__;\n    } > RAM\n\n#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    \n    .heap (NOLOAD):\n    {\n        . = ALIGN(8);\n        Image$$HEAP$$ZI$$Base = .;\n        . += __HEAP_SIZE;\n        Image$$HEAP$$ZI$$Limit = .;\n        __HeapLimit = .;\n    } > RAM  \n#endif\n\n    .stack (NOLOAD):\n    {\n        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;\n        . = ALIGN(8);\n        \n        __StackTop = .;\n        Image$$SYS_STACK$$ZI$$Base = .;\n        . += __STACK_SIZE;\n        Image$$SYS_STACK$$ZI$$Limit = .;\n        __stack = .;\n\n        Image$$FIQ_STACK$$ZI$$Base = .;\n        . += __FIQ_STACK_SIZE;\n        Image$$FIQ_STACK$$ZI$$Limit = .;\n\n        Image$$IRQ_STACK$$ZI$$Base = .;\n        . += __IRQ_STACK_SIZE;\n        Image$$IRQ_STACK$$ZI$$Limit = .;\n\n        Image$$SVC_STACK$$ZI$$Base = .;\n        . += __SVC_STACK_SIZE;\n        Image$$SVC_STACK$$ZI$$Limit = .;\n\n        Image$$ABT_STACK$$ZI$$Base = .;\n        . += __ABT_STACK_SIZE;\n        Image$$ABT_STACK$$ZI$$Limit = .;\n\n        Image$$UND_STACK$$ZI$$Base = .;\n        . += __UND_STACK_SIZE;\n        Image$$UND_STACK$$ZI$$Limit = .;\n        \n    } > RAM\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/ARMCA5.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA5.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/GCC/startup_ARMCA5.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA5.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA5.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n  \"LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \\n\"\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n  \"BL     _start                                   \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/IAR/ARMCA5.icf",
    "content": "\n/*-Memory Regions-*/\ndefine symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;\ndefine symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;\ndefine symbol __ICFEDIT_region_IROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;\ndefine symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;\ndefine symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IRAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_TTB_start__   = 0x80500000;\ndefine symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;\n\n/*-Sizes-*/\ndefine symbol __ICFEDIT_size_cstack__        = 0x1000;\ndefine symbol __ICFEDIT_size_irqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_fiqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_svcstack__      = 0x100;\ndefine symbol __ICFEDIT_size_abtstack__      = 0x100;\ndefine symbol __ICFEDIT_size_undstack__      = 0x100;\ndefine symbol __ICFEDIT_size_heap__          = 0x8000;\ndefine symbol __ICFEDIT_size_ttb__           = 0x4000;\n\ndefine memory mem with size = 4G;\ndefine region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]\n                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];\ndefine region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]\n                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];\ndefine region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]\n                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]\n                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];\ndefine region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];\n\ndefine block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };\ndefine block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };\ndefine block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };\ndefine block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };\ndefine block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };\ndefine block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };\ndefine block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };\ndefine block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };\n\ndo not initialize  { section .noinit };\n\ninitialize by copy { readwrite };\nif (isdefinedsymbol(__USE_DLIB_PERTHREAD))\n{\n  // Required in a multi-threaded application\n  initialize by copy with packing = none { section __DLIB_PERTHREAD };\n}\n\nplace at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };\nplace in IROM_region  { readonly };\nplace in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };\nplace in TTB_region   { block TTB };"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/IAR/startup_ARMCA5.s",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.s\n * @brief    CMSIS Device System Source File for ARM Cortex-A5 Device Series\n * @version  V1.00\n * @date     01 Nov 2017\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n  MODULE  ?startup_ARMCA5\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n  PUBLIC  Reset_Handler\n  PUBWEAK Undef_Handler\n  PUBWEAK SVC_Handler\n  PUBWEAK PAbt_Handler\n  PUBWEAK DAbt_Handler\n  PUBWEAK IRQ_Handler\n  PUBWEAK FIQ_Handler\n\n  SECTION SVC_STACK:DATA:NOROOT(3)\n  SECTION IRQ_STACK:DATA:NOROOT(3)\n  SECTION FIQ_STACK:DATA:NOROOT(3)\n  SECTION ABT_STACK:DATA:NOROOT(3)\n  SECTION UND_STACK:DATA:NOROOT(3)\n  SECTION USR_STACK:DATA:NOROOT(3)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n\n  section RESET:CODE:NOROOT(2)\n  PUBLIC  Vectors\n\nVectors:  \n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n\n\n  section .text:CODE:NOROOT(4)\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n  *----------------------------------------------------------------------------*/\n  EXTERN  SystemInit\n  EXTERN  __iar_program_start\n\nReset_Handler:  \n\n  // Mask interrupts\n  CPSID   if\n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5\n  ANDS    R0, R0, #3\ngoToSleep:\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exception mode\n  CPS    #0x11\n  LDR    SP, =SFE(FIQ_STACK)\n  CPS    #0x12\n  LDR    SP, =SFE(IRQ_STACK)\n  CPS    #0x13\n  LDR    SP, =SFE(SVC_STACK)\n  CPS    #0x17\n  LDR    SP, =SFE(ABT_STACK)\n  CPS    #0x1B\n  LDR    SP, =SFE(UND_STACK)\n  CPS    #0x1F\n  LDR    SP, =SFE(USR_STACK)\n\n  // Call SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __iar_program_start\n  BL     __iar_program_start\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nUndef_Handler:\nSVC_Handler:\nPAbt_Handler:\nDAbt_Handler:\nIRQ_Handler:\nFIQ_Handler:\nDefault_Handler:\n  B .\n\n  END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/mmu_ARMCA5.c",
    "content": "/**************************************************************************//**\n * @file     mmu_ARMCA5.c\n * @brief    MMU Configuration for ARM Cortex-A5 Device Series\n * @version  V1.2.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map\n\n                                                     Memory Type\n0xffffffff |--------------------------|             ------------\n           |       FLAG SYNC          |             Device Memory\n0xfffff000 |--------------------------|             ------------\n           |         Fault            |                Fault\n0xfff00000 |--------------------------|             ------------\n           |                          |                Normal\n           |                          |\n           |      Daughterboard       |\n           |         memory           |\n           |                          |\n0x80505000 |--------------------------|             ------------\n           |TTB (L2 Sync Flags   ) 4k |                Normal\n0x80504C00 |--------------------------|             ------------\n           |TTB (L2 Peripherals-B) 16k|                Normal\n0x80504800 |--------------------------|             ------------\n           |TTB (L2 Peripherals-A) 16k|                Normal\n0x80504400 |--------------------------|             ------------\n           |TTB (L2 Priv Periphs)  4k |                Normal\n0x80504000 |--------------------------|             ------------\n           |    TTB (L1 Descriptors)  |                Normal\n0x80500000 |--------------------------|             ------------\n           |          Stack           |                Normal\n           |--------------------------|             ------------\n           |          Heap            |                Normal\n0x80400000 |--------------------------|             ------------\n           |         ZI Data          |                Normal\n0x80300000 |--------------------------|             ------------\n           |         RW Data          |                Normal\n0x80200000 |--------------------------|             ------------\n           |         RO Data          |                Normal\n           |--------------------------|             ------------\n           |         RO Code          |              USH Normal\n0x80000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |      HSB AXI buses       |\n0x40000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x2c002000 |--------------------------|             ------------\n           |     Private Address      |            Device Memory\n0x2c000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x20000000 |--------------------------|             ------------\n           |       Peripherals        |           Device Memory RW/RO\n           |                          |              & Fault\n0x00000000 |--------------------------|\n*/\n\n// L1 Cache info and restrictions about architecture of the caches (CCSIR register):\n// Write-Through support *not* available\n// Write-Back support available.\n// Read allocation support available.\n// Write allocation support available.\n\n//Note: You should use the Shareable attribute carefully.\n//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.\n//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.\n//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.\n\n//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.\n//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.\n//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.\n\n\n//Following MMU configuration is expected\n//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)\n//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)\n//Domain 0 is always the Client domain\n//Descriptors should place all memory in domain 0\n\n#include \"ARMCA5.h\"\n#include \"mem_ARMCA5.h\"\n\n// TTB base address\n#define TTB_BASE ((uint32_t*)__TTB_BASE)\n\n// L2 table pointers\n//----------------------------------------\n#define TTB_L1_SIZE                    (0x00004000)                        // The L1 translation table divides the full 4GB address space of a 32-bit core\n                                                                           // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.\n                                                                           // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.\n\n#define PRIVATE_TABLE_L2_BASE_4k       (__TTB_BASE + TTB_L1_SIZE)          // Map 4k Private Address space\n#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400)  // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF\n#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800)  // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF\n#define SYNC_FLAGS_TABLE_L2_BASE_4k    (__TTB_BASE + TTB_L1_SIZE + 0xC00)  // Map 4k Flag synchronization\n\n//--------------------- PERIPHERALS -------------------\n#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)\n#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)\n\n//--------------------- SYNC FLAGS --------------------\n#define FLAG_SYNC     0xFFFFF000\n#define F_SYNC_BASE   0xFFF00000  //1M aligned\n\nstatic uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0\nstatic uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable\nstatic uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable\nstatic uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable\n\n/* Define global descriptors */\nstatic uint32_t Page_L1_4k  = 0x0;  //generic\nstatic uint32_t Page_L1_64k = 0x0;  //generic\nstatic uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0\nstatic uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0\n\nvoid MMU_CreateTranslationTable(void)\n{\n    mmu_region_attributes_Type region;\n\n    //Create 4GB of faulting entries\n    MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);\n\n    /*\n     * Generate descriptors. Refer to core_ca.h to get information about attributes\n     *\n     */\n    //Create descriptors for Vectors, RO, RW, ZI sections\n    section_normal(Sect_Normal, region);\n    section_normal_cod(Sect_Normal_Cod, region);\n    section_normal_ro(Sect_Normal_RO, region);\n    section_normal_rw(Sect_Normal_RW, region);\n    //Create descriptors for peripherals\n    section_device_ro(Sect_Device_RO, region);\n    section_device_rw(Sect_Device_RW, region);\n    //Create descriptors for 64k pages\n    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);\n    //Create descriptors for 4k pages\n    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);\n\n\n    /*\n     *  Define MMU flat-map regions and attributes\n     *\n     */\n\n    //Define Image\n    MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections\n    MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);  // multiple of 1MB sections\n\n    //--------------------- PERIPHERALS -------------------\n    MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE0   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A5_MP_FLASH_BASE1   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A5_MP_SRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A5_MP_VRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A5_MP_ETHERNET_BASE , 16, Sect_Device_RW);\n    MMU_TTSection (TTB_BASE, VE_A5_MP_USB_BASE      , 16, Sect_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A5_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define private address space entry.\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n    // Define L2CC entry.  Uncomment if PL310 is present\n    //    MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)\n    MMU_TTPage4k (TTB_BASE, F_SYNC_BASE             , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define synchronization space entry.\n    MMU_TTPage4k (TTB_BASE, FLAG_SYNC               ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    /* Set location of level 1 page table\n    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)\n    ; 13:7  - 0x0\n    ; 6     - IRGN[0] 0x1  (Inner WB WA)\n    ; 5     - NOS     0x0  (Non-shared)\n    ; 4:3   - RGN     0x01 (Outer WB WA)\n    ; 2     - IMP     0x0  (Implementation Defined)\n    ; 1     - S       0x0  (Non-shared)\n    ; 0     - IRGN[1] 0x0  (Inner WB WA) */\n    __set_TTBR0(__TTB_BASE | 0x48);\n    __ISB();\n\n    /* Set up domain access control register\n    ; We set domain 0 to Client and all other domains to No Access.\n    ; All translation table entries specify domain 0 */\n    __set_DACR(1);\n    __ISB();\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA5/Source/system_ARMCA5.c",
    "content": "/******************************************************************************\n * @file     system_ARMCA5.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A5 Device Series\n * @version  V1.0.1\n * @date     13. February 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"irq_ctrl.h\"\n\n#define  SYSTEM_CLOCK  12000000U\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System Initialization\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* do not use global variables because this function is called before\n   reaching pre-main. RW section may be overwritten afterwards.          */\n\n  // Invalidate entire Unified TLB\n  __set_TLBIALL(0);\n\n  // Invalidate entire branch predictor array\n  __set_BPIALL(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate instruction cache and flush branch target cache\n  __set_ICIALLU(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate data cache\n  L1C_InvalidateDCacheAll();\n\n#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\n  // Enable FPU\n  __FPU_Enable();\n#endif\n\n  // Create Translation Table\n  MMU_CreateTranslationTable();\n\n  // Enable MMU\n  MMU_Enable();\n\n  // Enable Caches\n  L1C_EnableCaches();\n  L1C_EnableBTAC();\n\n#if (__L2C_PRESENT == 1) \n  // Enable GIC\n  L2C_Enable();\n#endif\n\n  // IRQ Initialize\n  IRQ_Initialize();\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Config/mem_ARMCA7.h",
    "content": "/**************************************************************************//**\n * @file     mem_ARMCA7.h\n * @brief    Memory base and size definitions (used in scatter file)\n * @version  V1.1.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __MEM_ARMCA7_H\n#define __MEM_ARMCA7_H\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap size definition\n *----------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n/*--------------------- ROM Configuration ------------------------------------\n//\n// <h> ROM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>\n//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE       0x80000000\n#define __ROM_SIZE       0x00200000\n\n/*--------------------- RAM Configuration -----------------------------------\n// <h> RAM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>\n//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n//   <h> Data Sections\n//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//   </h>\n//   <h> Stack / Heap Configuration\n//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <h> Exceptional Modes\n//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     </h>\n//   </h>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE       0x80200000\n#define __RAM_SIZE       0x00200000\n\n#define __RW_DATA_SIZE   0x00100000\n#define __ZI_DATA_SIZE   0x000F0000\n\n#define __STACK_SIZE     0x00001000\n#define __HEAP_SIZE      0x00008000\n\n#define __UND_STACK_SIZE 0x00000100\n#define __ABT_STACK_SIZE 0x00000100\n#define __SVC_STACK_SIZE 0x00000100\n#define __IRQ_STACK_SIZE 0x00000100\n#define __FIQ_STACK_SIZE 0x00000100\n\n/*----------------------------------------------------------------------------*/\n\n/*--------------------- TTB Configuration ------------------------------------\n//\n// <h> TTB Configuration\n//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned\n//   <i> The TLB L2 entries are placed after the L1 in the MMU config\n//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>\n//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __TTB_BASE       0x80500000\n#define __TTB_SIZE       0x00005000\n\n#endif /* __MEM_ARMCA7_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Config/system_ARMCA7.h",
    "content": "/******************************************************************************\n * @file     system_ARMCA7.h\n * @brief    CMSIS Device System Header File for Arm Cortex-A7 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __SYSTEM_ARMCA7_H\n#define __SYSTEM_ARMCA7_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SYSTEM_ARMCA7_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Include/ARMCA7.h",
    "content": "/******************************************************************************\n * @file     ARMCA7.h\n * @brief    CMSIS Cortex-A7 Core Peripheral Access Layer Header File \n * @version  V1.1.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __ARMCA7_H__\n#define __ARMCA7_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\n/** Device specific Interrupt IDs */\ntypedef enum IRQn\n{\n/******  SGI Interrupts Numbers                 ****************************************/\n  SGI0_IRQn            =  0,        /*!< Software Generated Interrupt 0 */\n  SGI1_IRQn            =  1,        /*!< Software Generated Interrupt 1 */\n  SGI2_IRQn            =  2,        /*!< Software Generated Interrupt 2 */\n  SGI3_IRQn            =  3,        /*!< Software Generated Interrupt 3 */\n  SGI4_IRQn            =  4,        /*!< Software Generated Interrupt 4 */\n  SGI5_IRQn            =  5,        /*!< Software Generated Interrupt 5 */\n  SGI6_IRQn            =  6,        /*!< Software Generated Interrupt 6 */\n  SGI7_IRQn            =  7,        /*!< Software Generated Interrupt 7 */\n  SGI8_IRQn            =  8,        /*!< Software Generated Interrupt 8 */\n  SGI9_IRQn            =  9,        /*!< Software Generated Interrupt 9 */\n  SGI10_IRQn           = 10,        /*!< Software Generated Interrupt 10 */\n  SGI11_IRQn           = 11,        /*!< Software Generated Interrupt 11 */\n  SGI12_IRQn           = 12,        /*!< Software Generated Interrupt 12 */\n  SGI13_IRQn           = 13,        /*!< Software Generated Interrupt 13 */\n  SGI14_IRQn           = 14,        /*!< Software Generated Interrupt 14 */\n  SGI15_IRQn           = 15,        /*!< Software Generated Interrupt 15 */\n\n/******  Cortex-A7 Processor Exceptions Numbers ****************************************/\n  SecurePhyTimer_IRQn  = 29,        /*!< Physical Timer Interrupt                      */\n\n/******  Platform Exceptions Numbers ***************************************************/\n  Watchdog_IRQn        = 32,        /*!< SP805 Interrupt        */\n  Timer0_IRQn          = 34,        /*!< SP804 Interrupt        */\n  Timer1_IRQn          = 35,        /*!< SP804 Interrupt        */\n  RTClock_IRQn         = 36,        /*!< PL031 Interrupt        */\n  UART0_IRQn           = 37,        /*!< PL011 Interrupt        */\n  UART1_IRQn           = 38,        /*!< PL011 Interrupt        */\n  UART2_IRQn           = 39,        /*!< PL011 Interrupt        */\n  UART3_IRQn           = 40,        /*!< PL011 Interrupt        */\n  MCI0_IRQn            = 41,        /*!< PL180 Interrupt (1st)  */\n  MCI1_IRQn            = 42,        /*!< PL180 Interrupt (2nd)  */\n  AACI_IRQn            = 43,        /*!< PL041 Interrupt        */\n  Keyboard_IRQn        = 44,        /*!< PL050 Interrupt        */\n  Mouse_IRQn           = 45,        /*!< PL050 Interrupt        */\n  CLCD_IRQn            = 46,        /*!< PL111 Interrupt        */\n  Ethernet_IRQn        = 47,        /*!< SMSC_91C111 Interrupt  */\n  VFS2_IRQn            = 73,        /*!< VFS2 Interrupt         */\n} IRQn_Type;\n\n/******************************************************************************/\n/*                         Peripheral memory map                              */\n/******************************************************************************/\n\n/* Peripheral and RAM base address */\n#define VE_A7_MP_FLASH_BASE0                  (0x00000000UL)                                /*!< (FLASH0     ) Base Address */\n#define VE_A7_MP_FLASH_BASE1                  (0x0C000000UL)                                /*!< (FLASH1     ) Base Address */\n#define VE_A7_MP_SRAM_BASE                    (0x14000000UL)                                /*!< (SRAM       ) Base Address */\n#define VE_A7_MP_PERIPH_BASE_CS2              (0x18000000UL)                                /*!< (Peripheral ) Base Address */\n#define VE_A7_MP_VRAM_BASE                    (0x00000000UL + VE_A7_MP_PERIPH_BASE_CS2)     /*!< (VRAM       ) Base Address */\n#define VE_A7_MP_ETHERNET_BASE                (0x02000000UL + VE_A7_MP_PERIPH_BASE_CS2)     /*!< (ETHERNET   ) Base Address */\n#define VE_A7_MP_USB_BASE                     (0x03000000UL + VE_A7_MP_PERIPH_BASE_CS2)     /*!< (USB        ) Base Address */\n#define VE_A7_MP_PERIPH_BASE_CS3              (0x1C000000UL)                                /*!< (Peripheral ) Base Address */\n#define VE_A7_MP_DAP_BASE                     (0x00000000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (LOCAL DAP  ) Base Address */\n#define VE_A7_MP_SYSTEM_REG_BASE              (0x00010000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (SYSTEM REG ) Base Address */\n#define VE_A7_MP_SERIAL_BASE                  (0x00030000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (SERIAL     ) Base Address */\n#define VE_A7_MP_AACI_BASE                    (0x00040000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (AACI       ) Base Address */\n#define VE_A7_MP_MMCI_BASE                    (0x00050000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (MMCI       ) Base Address */\n#define VE_A7_MP_KMI0_BASE                    (0x00060000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (KMI0       ) Base Address */\n#define VE_A7_MP_UART_BASE                    (0x00090000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (UART       ) Base Address */\n#define VE_A7_MP_WDT_BASE                     (0x000F0000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (WDT        ) Base Address */\n#define VE_A7_MP_TIMER_BASE                   (0x00110000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (TIMER      ) Base Address */\n#define VE_A7_MP_DVI_BASE                     (0x00160000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (DVI        ) Base Address */\n#define VE_A7_MP_RTC_BASE                     (0x00170000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (RTC        ) Base Address */\n#define VE_A7_MP_UART4_BASE                   (0x001B0000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (UART4      ) Base Address */\n#define VE_A7_MP_CLCD_BASE                    (0x001F0000UL + VE_A7_MP_PERIPH_BASE_CS3)     /*!< (CLCD       ) Base Address */\n#define VE_A7_MP_PRIVATE_PERIPH_BASE          (0x2C000000UL)                                /*!< (Peripheral ) Base Address */\n#define VE_A7_MP_GIC_DISTRIBUTOR_BASE         (0x00001000UL + VE_A7_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST   ) Base Address */\n#define VE_A7_MP_GIC_INTERFACE_BASE           (0x00002000UL + VE_A7_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */\n#define VE_A7_MP_PL310_BASE                   (0x000F0000UL + VE_A7_MP_PRIVATE_PERIPH_BASE) /*!< (L2C-310    ) Base Address */\n#define VE_A7_MP_SSRAM_BASE                   (0x2E000000UL)                                /*!< (System SRAM) Base Address */\n#define VE_A7_MP_DRAM_BASE                    (0x80000000UL)                                /*!< (DRAM       ) Base Address */\n#define GIC_DISTRIBUTOR_BASE                  VE_A7_MP_GIC_DISTRIBUTOR_BASE\n#define GIC_INTERFACE_BASE                    VE_A7_MP_GIC_INTERFACE_BASE\n\n//The VE-A7 model implements L1 cache as architecturally defined, but does not implement L2 cache.\n//Do not enable the L2 cache if you are running RTX on a VE-A7 model as it may cause a data abort.\n#define L2C_310_BASE                          VE_A7_MP_PL310_BASE\n\n/* --------  Configuration of the Cortex-A7 Processor and Core Peripherals  ------- */\n#define __CA_REV        0x0000U    /* Core revision r0p0                            */\n#define __CORTEX_A           7U    /* Cortex-A7 Core                                */\n#define __FPU_PRESENT        1U    /* FPU present                                   */\n#define __GIC_PRESENT        1U    /* GIC present                                   */\n#define __TIM_PRESENT        1U    /* TIM present                                   */\n#define __L2C_PRESENT        0U    /* L2C present                                   */\n\n#include \"core_ca.h\"\n#include <system_ARMCA7.h>\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  // __ARMCA7_H__\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/AC5/ARMCA7.sct",
    "content": "#! armcc -E\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA7.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/AC5/startup_ARMCA7.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA7.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA7.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors       (void) __attribute__ ((section(\"RESET\")));\nvoid Reset_Handler (void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n__ASM void Vectors(void) {\n  PRESERVE8\n  \n  IMPORT Undef_Handler\n  IMPORT SVC_Handler\n  IMPORT PAbt_Handler\n  IMPORT DAbt_Handler\n  IMPORT IRQ_Handler\n  IMPORT FIQ_Handler\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__ASM void Reset_Handler(void) {\n  PRESERVE8\n\n  // Mask interrupts\n  CPSID  if                           \n\n  // Put any cores other than 0 to sleep\n  MRC    p15, 0, R0, c0, c0, 5       // Read MPIDR\n  ANDS   R0, R0, #3\ngoToSleep\n  WFINE\n  BNE    goToSleep\n\n  // Reset SCTLR Settings\n  MRC    p15, 0, R0, c1, c0, 0       // Read CP15 System Control register\n  BIC    R0, R0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache\n  BIC    R0, R0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache\n  BIC    R0, R0, #0x1                // Clear M bit  0 to disable MMU\n  BIC    R0, R0, #(0x1 << 11)        // Clear Z bit 11 to disable branch prediction\n  BIC    R0, R0, #(0x1 << 13)        // Clear V bit 13 to disable hivecs\n  MCR    p15, 0, R0, c1, c0, 0       // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC    p15, 0, r0, c1, c0, 1       // Read CP15 Auxiliary Control Register\n  ORR    r0, r0, #(1 <<  1)          // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR    p15, 0, r0, c1, c0, 1       // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exceptional mode\n  IMPORT |Image$$FIQ_STACK$$ZI$$Limit|\n  IMPORT |Image$$IRQ_STACK$$ZI$$Limit|\n  IMPORT |Image$$SVC_STACK$$ZI$$Limit|\n  IMPORT |Image$$ABT_STACK$$ZI$$Limit|\n  IMPORT |Image$$UND_STACK$$ZI$$Limit|\n  IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|\n  CPS    #0x11\n  LDR    SP, =|Image$$FIQ_STACK$$ZI$$Limit|\n  CPS    #0x12\n  LDR    SP, =|Image$$IRQ_STACK$$ZI$$Limit|\n  CPS    #0x13\n  LDR    SP, =|Image$$SVC_STACK$$ZI$$Limit|\n  CPS    #0x17\n  LDR    SP, =|Image$$ABT_STACK$$ZI$$Limit|\n  CPS    #0x1B\n  LDR    SP, =|Image$$UND_STACK$$ZI$$Limit|\n  CPS    #0x1F\n  LDR    SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|\n\n  // Call SystemInit\n  IMPORT SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __main\n  IMPORT __main\n  BL     __main\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/AC6/ARMCA7.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA7.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/AC6/startup_ARMCA7.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA7.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA7.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void) __attribute__ ((noreturn));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n  \"LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \\n\"\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n  \"BL     __main                                   \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/ARMCA7.ld",
    "content": "#include \"mem_ARMCA7.h\" \n\nMEMORY\n{\n  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE \n  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n\n        Image$$VECTORS$$Base = .;\n        * (RESET)\n        KEEP(*(.isr_vector))\n        Image$$VECTORS$$Limit = .;\n\n        *(SVC_TABLE)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        /* .ctors */\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        /* .dtors */\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        Image$$RO_DATA$$Base = .;\n        *(.rodata*)\n        Image$$RO_DATA$$Limit = .;\n\n        KEEP(*(.eh_frame*))\n    } > ROM\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > ROM\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > ROM\n    __exidx_end = .;\n\n\n    .copy.table :\n    {\n        . = ALIGN(4);\n        __copy_table_start__ = .;\n        LONG (__etext)\n        LONG (__data_start__)\n        LONG (__data_end__ - __data_start__)\n        __copy_table_end__ = .;\n    } > ROM\n\n    .zero.table :\n    {\n        . = ALIGN(4);\n        __zero_table_start__ = .;\n        LONG (__bss_start__)\n        LONG (__bss_end__ - __bss_start__)\n        __zero_table_end__ = .;\n    } > ROM\n\n    __etext = .;\n        \n    .ttb :\n    {\n        Image$$TTB$$ZI$$Base = .;\n        . += __TTB_SIZE;\n        Image$$TTB$$ZI$$Limit = .;\n    } > L_TTB\n\n    .data : AT (__etext)\n    {\n        Image$$RW_DATA$$Base = .;\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n        Image$$RW_DATA$$Limit = .;\n\n        . = ALIGN(4);\n        /* preinit data */\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        /* init data */\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        /* finit data */\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        /* All data end */\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss ALIGN(0x400):\n    {\n        Image$$ZI_DATA$$Base = .;\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$ZI_DATA$$Limit = .;\n        __end__ = .;\n        end = __end__;\n    } > RAM\n\n#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    \n    .heap (NOLOAD):\n    {\n        . = ALIGN(8);\n        Image$$HEAP$$ZI$$Base = .;\n        . += __HEAP_SIZE;\n        Image$$HEAP$$ZI$$Limit = .;\n        __HeapLimit = .;\n    } > RAM  \n#endif\n\n    .stack (NOLOAD):\n    {\n        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;\n        . = ALIGN(8);\n        \n        __StackTop = .;\n        Image$$SYS_STACK$$ZI$$Base = .;\n        . += __STACK_SIZE;\n        Image$$SYS_STACK$$ZI$$Limit = .;\n        __stack = .;\n\n        Image$$FIQ_STACK$$ZI$$Base = .;\n        . += __FIQ_STACK_SIZE;\n        Image$$FIQ_STACK$$ZI$$Limit = .;\n\n        Image$$IRQ_STACK$$ZI$$Base = .;\n        . += __IRQ_STACK_SIZE;\n        Image$$IRQ_STACK$$ZI$$Limit = .;\n\n        Image$$SVC_STACK$$ZI$$Base = .;\n        . += __SVC_STACK_SIZE;\n        Image$$SVC_STACK$$ZI$$Limit = .;\n\n        Image$$ABT_STACK$$ZI$$Base = .;\n        . += __ABT_STACK_SIZE;\n        Image$$ABT_STACK$$ZI$$Limit = .;\n\n        Image$$UND_STACK$$ZI$$Base = .;\n        . += __UND_STACK_SIZE;\n        Image$$UND_STACK$$ZI$$Limit = .;\n        \n    } > RAM\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/GCC/startup_ARMCA7.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA7.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA7.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n  \"LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \\n\"\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n  \"BL     _start                                   \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/ARMCA7.icf",
    "content": "\n/*-Memory Regions-*/\ndefine symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;\ndefine symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;\ndefine symbol __ICFEDIT_region_IROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;\ndefine symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;\ndefine symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IRAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_TTB_start__   = 0x80500000;\ndefine symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;\n\n/*-Sizes-*/\ndefine symbol __ICFEDIT_size_cstack__        = 0x1000;\ndefine symbol __ICFEDIT_size_irqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_fiqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_svcstack__      = 0x100;\ndefine symbol __ICFEDIT_size_abtstack__      = 0x100;\ndefine symbol __ICFEDIT_size_undstack__      = 0x100;\ndefine symbol __ICFEDIT_size_heap__          = 0x8000;\ndefine symbol __ICFEDIT_size_ttb__           = 0x4000;\n\ndefine memory mem with size = 4G;\ndefine region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]\n                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];\ndefine region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]\n                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];\ndefine region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]\n                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]\n                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];\ndefine region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];\n\ndefine block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };\ndefine block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };\ndefine block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };\ndefine block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };\ndefine block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };\ndefine block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };\ndefine block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };\ndefine block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };\n\ndo not initialize  { section .noinit };\n\ninitialize by copy { readwrite };\nif (isdefinedsymbol(__USE_DLIB_PERTHREAD))\n{\n  // Required in a multi-threaded application\n  initialize by copy with packing = none { section __DLIB_PERTHREAD };\n}\n\nplace at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };\nplace in IROM_region  { readonly };\nplace in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };\nplace in TTB_region   { block TTB };"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/IAR/startup_ARMCA7.s",
    "content": "/******************************************************************************\n * @file     startup_ARMCA7.s\n * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series\n * @version  V1.00\n * @date     01 Nov 2017\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n  MODULE  ?startup_ARMCA7\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n  PUBLIC  Reset_Handler\n  PUBWEAK Undef_Handler\n  PUBWEAK SVC_Handler\n  PUBWEAK PAbt_Handler\n  PUBWEAK DAbt_Handler\n  PUBWEAK IRQ_Handler\n  PUBWEAK FIQ_Handler\n\n  SECTION SVC_STACK:DATA:NOROOT(3)\n  SECTION IRQ_STACK:DATA:NOROOT(3)\n  SECTION FIQ_STACK:DATA:NOROOT(3)\n  SECTION ABT_STACK:DATA:NOROOT(3)\n  SECTION UND_STACK:DATA:NOROOT(3)\n  SECTION USR_STACK:DATA:NOROOT(3)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n\n  section RESET:CODE:NOROOT(2)\n  PUBLIC  Vectors\n\nVectors:\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n\n\n  section .text:CODE:NOROOT(4)\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n  *----------------------------------------------------------------------------*/\n  EXTERN  SystemInit\n  EXTERN  __iar_program_start\n\nReset_Handler:  \n\n  // Mask interrupts\n  CPSID   if\n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5\n  ANDS    R0, R0, #3\ngoToSleep:\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exception mode\n  CPS    #0x11\n  LDR    SP, =SFE(FIQ_STACK)\n  CPS    #0x12\n  LDR    SP, =SFE(IRQ_STACK)\n  CPS    #0x13\n  LDR    SP, =SFE(SVC_STACK)\n  CPS    #0x17\n  LDR    SP, =SFE(ABT_STACK)\n  CPS    #0x1B\n  LDR    SP, =SFE(UND_STACK)\n  CPS    #0x1F\n  LDR    SP, =SFE(USR_STACK)\n\n  // Call SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __iar_program_start\n  BL     __iar_program_start\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nUndef_Handler:\nSVC_Handler:\nPAbt_Handler:\nDAbt_Handler:\nIRQ_Handler:\nFIQ_Handler:\nDefault_Handler:\n  B .\n\n  END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c",
    "content": "/**************************************************************************//**\n * @file     mmu_ARMCA7.c\n * @brief    MMU Configuration for Arm Cortex-A7 Device Series\n * @version  V1.2.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map\n\n                                                     Memory Type\n0xffffffff |--------------------------|             ------------\n           |       FLAG SYNC          |             Device Memory\n0xfffff000 |--------------------------|             ------------\n           |         Fault            |                Fault\n0xfff00000 |--------------------------|             ------------\n           |                          |                Normal\n           |                          |\n           |      Daughterboard       |\n           |         memory           |\n           |                          |\n0x80505000 |--------------------------|             ------------\n           |TTB (L2 Sync Flags   ) 4k |                Normal\n0x80504C00 |--------------------------|             ------------\n           |TTB (L2 Peripherals-B) 16k|                Normal\n0x80504800 |--------------------------|             ------------\n           |TTB (L2 Peripherals-A) 16k|                Normal\n0x80504400 |--------------------------|             ------------\n           |TTB (L2 Priv Periphs)  4k |                Normal\n0x80504000 |--------------------------|             ------------\n           |    TTB (L1 Descriptors)  |                Normal\n0x80500000 |--------------------------|             ------------\n           |          Stack           |                Normal\n           |--------------------------|             ------------\n           |          Heap            |                Normal\n0x80400000 |--------------------------|             ------------\n           |         ZI Data          |                Normal\n0x80300000 |--------------------------|             ------------\n           |         RW Data          |                Normal\n0x80200000 |--------------------------|             ------------\n           |         RO Data          |                Normal\n           |--------------------------|             ------------\n           |         RO Code          |              USH Normal\n0x80000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |      HSB AXI buses       |\n0x40000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x2c002000 |--------------------------|             ------------\n           |     Private Address      |            Device Memory\n0x2c000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x20000000 |--------------------------|             ------------\n           |       Peripherals        |           Device Memory RW/RO\n           |                          |              & Fault\n0x00000000 |--------------------------|\n*/\n\n// L1 Cache info and restrictions about architecture of the caches (CCSIR register):\n// Write-Through support *not* available\n// Write-Back support available.\n// Read allocation support available.\n// Write allocation support available.\n\n//Note: You should use the Shareable attribute carefully.\n//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.\n//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.\n//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.\n\n//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.\n//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.\n//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.\n\n\n//Following MMU configuration is expected\n//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)\n//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)\n//Domain 0 is always the Client domain\n//Descriptors should place all memory in domain 0\n\n#include \"ARMCA7.h\"\n#include \"mem_ARMCA7.h\"\n\n// TTB base address\n#define TTB_BASE ((uint32_t*)__TTB_BASE)\n\n// L2 table pointers\n//----------------------------------------\n#define TTB_L1_SIZE                    (0x00004000)                        // The L1 translation table divides the full 4GB address space of a 32-bit core\n                                                                           // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.\n                                                                           // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.\n\n#define PRIVATE_TABLE_L2_BASE_4k       (__TTB_BASE + TTB_L1_SIZE)          // Map 4k Private Address space\n#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400)  // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF\n#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800)  // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF\n#define SYNC_FLAGS_TABLE_L2_BASE_4k    (__TTB_BASE + TTB_L1_SIZE + 0xC00)  // Map 4k Flag synchronization\n\n//--------------------- PERIPHERALS -------------------\n#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)\n#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)\n\n//--------------------- SYNC FLAGS --------------------\n#define FLAG_SYNC     0xFFFFF000\n#define F_SYNC_BASE   0xFFF00000  //1M aligned\n\nstatic uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0\nstatic uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable\nstatic uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable\nstatic uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable\n\n/* Define global descriptors */\nstatic uint32_t Page_L1_4k  = 0x0;  //generic\nstatic uint32_t Page_L1_64k = 0x0;  //generic\nstatic uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0\nstatic uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0\n\nvoid MMU_CreateTranslationTable(void)\n{\n    mmu_region_attributes_Type region;\n\n    //Create 4GB of faulting entries\n    MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);\n\n    /*\n     * Generate descriptors. Refer to core_ca.h to get information about attributes\n     *\n     */\n    //Create descriptors for Vectors, RO, RW, ZI sections\n    section_normal(Sect_Normal, region);\n    section_normal_cod(Sect_Normal_Cod, region);\n    section_normal_ro(Sect_Normal_RO, region);\n    section_normal_rw(Sect_Normal_RW, region);\n    //Create descriptors for peripherals\n    section_device_ro(Sect_Device_RO, region);\n    section_device_rw(Sect_Device_RW, region);\n    //Create descriptors for 64k pages\n    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);\n    //Create descriptors for 4k pages\n    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);\n\n\n    /*\n     *  Define MMU flat-map regions and attributes\n     *\n     */\n\n    //Define Image\n    MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections\n    MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);  // multiple of 1MB sections\n\n    //--------------------- PERIPHERALS -------------------\n    MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW);\n    MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE      , 16, Sect_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define private address space entry.\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,  3,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n    // Define L2CC entry.  Uncomment if PL310 is present\n    //    MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)\n    MMU_TTPage4k (TTB_BASE, F_SYNC_BASE             , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define synchronization space entry.\n    MMU_TTPage4k (TTB_BASE, FLAG_SYNC               ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    /* Set location of level 1 page table\n    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)\n    ; 13:7  - 0x0\n    ; 6     - IRGN[0] 0x1  (Inner WB WA)\n    ; 5     - NOS     0x0  (Non-shared)\n    ; 4:3   - RGN     0x01 (Outer WB WA)\n    ; 2     - IMP     0x0  (Implementation Defined)\n    ; 1     - S       0x0  (Non-shared)\n    ; 0     - IRGN[1] 0x0  (Inner WB WA) */\n    __set_TTBR0(__TTB_BASE | 0x48);\n    __ISB();\n\n    /* Set up domain access control register\n    ; We set domain 0 to Client and all other domains to No Access.\n    ; All translation table entries specify domain 0 */\n    __set_DACR(1);\n    __ISB();\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA7/Source/system_ARMCA7.c",
    "content": "/******************************************************************************\n * @file     system_ARMCA7.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A7 Device Series\n * @version  V1.0.1\n * @date     13. February 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"irq_ctrl.h\"\n\n#define  SYSTEM_CLOCK  12000000U\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System Initialization\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* do not use global variables because this function is called before\n   reaching pre-main. RW section may be overwritten afterwards.          */\n\n  // Invalidate entire Unified TLB\n  __set_TLBIALL(0);\n\n  // Invalidate entire branch predictor array\n  __set_BPIALL(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate instruction cache and flush branch target cache\n  __set_ICIALLU(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate data cache\n  L1C_InvalidateDCacheAll();\n\n#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\n  // Enable FPU\n  __FPU_Enable();\n#endif\n\n  // Create Translation Table\n  MMU_CreateTranslationTable();\n\n  // Enable MMU\n  MMU_Enable();\n\n  // Enable Caches\n  L1C_EnableCaches();\n  L1C_EnableBTAC();\n\n#if (__L2C_PRESENT == 1) \n  // Enable GIC\n  L2C_Enable();\n#endif\n\n  // IRQ Initialize\n  IRQ_Initialize();\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Config/mem_ARMCA9.h",
    "content": "/**************************************************************************//**\n * @file     mem_ARMCA9.h\n * @brief    Memory base and size definitions (used in scatter file)\n * @version  V1.1.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __MEM_ARMCA9_H\n#define __MEM_ARMCA9_H\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap size definition\n *----------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n/*--------------------- ROM Configuration ------------------------------------\n//\n// <h> ROM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> ROM Base Address <0x0-0xFFFFFFFF:0x100000>\n//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE       0x80000000\n#define __ROM_SIZE       0x00200000\n\n/*--------------------- RAM Configuration -----------------------------------\n// <h> RAM Configuration\n//   <i> For compatibility with MMU config the sections must be multiple of 1MB\n//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:0x100000>\n//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000>\n//   <h> Data Sections\n//     <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//   </h>\n//   <h> Stack / Heap Configuration\n//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <h> Exceptional Modes\n//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     </h>\n//   </h>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE       0x80200000\n#define __RAM_SIZE       0x00200000\n\n#define __RW_DATA_SIZE   0x00100000\n#define __ZI_DATA_SIZE   0x000F0000\n\n#define __STACK_SIZE     0x00001000\n#define __HEAP_SIZE      0x00008000\n\n#define __UND_STACK_SIZE 0x00000100\n#define __ABT_STACK_SIZE 0x00000100\n#define __SVC_STACK_SIZE 0x00000100\n#define __IRQ_STACK_SIZE 0x00000100\n#define __FIQ_STACK_SIZE 0x00000100\n\n/*----------------------------------------------------------------------------*/\n\n/*--------------------- TTB Configuration ------------------------------------\n//\n// <h> TTB Configuration\n//   <i> The TLB L1 contains 4096 32-bit entries and must be 16kB aligned\n//   <i> The TLB L2 entries are placed after the L1 in the MMU config\n//   <o0> TTB Base Address <0x0-0xFFFFFFFF:0x4000>\n//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __TTB_BASE       0x80500000\n#define __TTB_SIZE       0x00005000\n\n#endif /* __MEM_ARMCA9_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Config/system_ARMCA9.h",
    "content": "/******************************************************************************\n * @file     system_ARMCA9.h\n * @brief    CMSIS Device System Header File for Arm Cortex-A9 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __SYSTEM_ARMCA9_H\n#define __SYSTEM_ARMCA9_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SYSTEM_ARMCA9_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Include/ARMCA9.h",
    "content": "/******************************************************************************\n * @file     ARMCA9.h\n * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File \n * @version  V1.1.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __ARMCA9_H__\n#define __ARMCA9_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\n/** Device specific Interrupt IDs */\ntypedef enum IRQn\n{\n/******  SGI Interrupts Numbers                 ****************************************/\n  SGI0_IRQn            =  0,        /*!< Software Generated Interrupt 0 */\n  SGI1_IRQn            =  1,        /*!< Software Generated Interrupt 1 */\n  SGI2_IRQn            =  2,        /*!< Software Generated Interrupt 2 */\n  SGI3_IRQn            =  3,        /*!< Software Generated Interrupt 3 */\n  SGI4_IRQn            =  4,        /*!< Software Generated Interrupt 4 */\n  SGI5_IRQn            =  5,        /*!< Software Generated Interrupt 5 */\n  SGI6_IRQn            =  6,        /*!< Software Generated Interrupt 6 */\n  SGI7_IRQn            =  7,        /*!< Software Generated Interrupt 7 */\n  SGI8_IRQn            =  8,        /*!< Software Generated Interrupt 8 */\n  SGI9_IRQn            =  9,        /*!< Software Generated Interrupt 9 */\n  SGI10_IRQn           = 10,        /*!< Software Generated Interrupt 10 */\n  SGI11_IRQn           = 11,        /*!< Software Generated Interrupt 11 */\n  SGI12_IRQn           = 12,        /*!< Software Generated Interrupt 12 */\n  SGI13_IRQn           = 13,        /*!< Software Generated Interrupt 13 */\n  SGI14_IRQn           = 14,        /*!< Software Generated Interrupt 14 */\n  SGI15_IRQn           = 15,        /*!< Software Generated Interrupt 15 */\n\n/******  Cortex-A9 Processor Exceptions Numbers ****************************************/\n  GlobalTimer_IRQn     = 27,        /*!< Global Timer Interrupt                        */\n  PrivTimer_IRQn       = 29,        /*!< Private Timer Interrupt                       */\n  PrivWatchdog_IRQn    = 30,        /*!< Private Watchdog Interrupt                    */\n\n/******  Platform Exceptions Numbers ***************************************************/\n  Watchdog_IRQn        = 32,        /*!< SP805 Interrupt        */\n  Timer0_IRQn          = 34,        /*!< SP804 Interrupt        */\n  Timer1_IRQn          = 35,        /*!< SP804 Interrupt        */\n  RTClock_IRQn         = 36,        /*!< PL031 Interrupt        */\n  UART0_IRQn           = 37,        /*!< PL011 Interrupt        */\n  UART1_IRQn           = 38,        /*!< PL011 Interrupt        */\n  UART2_IRQn           = 39,        /*!< PL011 Interrupt        */\n  UART3_IRQn           = 40,        /*!< PL011 Interrupt        */\n  MCI0_IRQn            = 41,        /*!< PL180 Interrupt (1st)  */\n  MCI1_IRQn            = 42,        /*!< PL180 Interrupt (2nd)  */\n  AACI_IRQn            = 43,        /*!< PL041 Interrupt        */\n  Keyboard_IRQn        = 44,        /*!< PL050 Interrupt        */\n  Mouse_IRQn           = 45,        /*!< PL050 Interrupt        */\n  CLCD_IRQn            = 46,        /*!< PL111 Interrupt        */\n  Ethernet_IRQn        = 47,        /*!< SMSC_91C111 Interrupt  */\n  VFS2_IRQn            = 73,        /*!< VFS2 Interrupt         */\n} IRQn_Type;\n\n/******************************************************************************/\n/*                         Peripheral memory map                              */\n/******************************************************************************/\n\n/* Peripheral and RAM base address */\n#define VE_A9_MP_FLASH_BASE0                  (0x00000000UL)                                /*!< (FLASH0     ) Base Address */\n#define VE_A9_MP_FLASH_BASE1                  (0x0C000000UL)                                /*!< (FLASH1     ) Base Address */\n#define VE_A9_MP_SRAM_BASE                    (0x14000000UL)                                /*!< (SRAM       ) Base Address */\n#define VE_A9_MP_PERIPH_BASE_CS2              (0x18000000UL)                                /*!< (Peripheral ) Base Address */\n#define VE_A9_MP_VRAM_BASE                    (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS2)     /*!< (VRAM       ) Base Address */\n#define VE_A9_MP_ETHERNET_BASE                (0x02000000UL + VE_A9_MP_PERIPH_BASE_CS2)     /*!< (ETHERNET   ) Base Address */\n#define VE_A9_MP_USB_BASE                     (0x03000000UL + VE_A9_MP_PERIPH_BASE_CS2)     /*!< (USB        ) Base Address */\n#define VE_A9_MP_PERIPH_BASE_CS3              (0x1C000000UL)                                /*!< (Peripheral ) Base Address */\n#define VE_A9_MP_DAP_BASE                     (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (LOCAL DAP  ) Base Address */\n#define VE_A9_MP_SYSTEM_REG_BASE              (0x00010000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (SYSTEM REG ) Base Address */\n#define VE_A9_MP_SERIAL_BASE                  (0x00030000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (SERIAL     ) Base Address */\n#define VE_A9_MP_AACI_BASE                    (0x00040000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (AACI       ) Base Address */\n#define VE_A9_MP_MMCI_BASE                    (0x00050000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (MMCI       ) Base Address */\n#define VE_A9_MP_KMI0_BASE                    (0x00060000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (KMI0       ) Base Address */\n#define VE_A9_MP_UART_BASE                    (0x00090000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (UART       ) Base Address */\n#define VE_A9_MP_WDT_BASE                     (0x000F0000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (WDT        ) Base Address */\n#define VE_A9_MP_TIMER_BASE                   (0x00110000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (TIMER      ) Base Address */\n#define VE_A9_MP_DVI_BASE                     (0x00160000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (DVI        ) Base Address */\n#define VE_A9_MP_RTC_BASE                     (0x00170000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (RTC        ) Base Address */\n#define VE_A9_MP_UART4_BASE                   (0x001B0000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (UART4      ) Base Address */\n#define VE_A9_MP_CLCD_BASE                    (0x001F0000UL + VE_A9_MP_PERIPH_BASE_CS3)     /*!< (CLCD       ) Base Address */\n#define VE_A9_MP_PL310_BASE                   (0x1E00A000UL)                                /*!< (L2C-310    ) Base Address */\n#define VE_A9_MP_PRIVATE_PERIPH_BASE          (0x2C000000UL)                                /*!< (Peripheral ) Base Address */\n#define VE_A9_MP_GIC_DISTRIBUTOR_BASE         (0x00001000UL + VE_A9_MP_PRIVATE_PERIPH_BASE) /*!< (GIC DIST   ) Base Address */\n#define VE_A9_MP_GIC_INTERFACE_BASE           (0x00000100UL + VE_A9_MP_PRIVATE_PERIPH_BASE) /*!< (GIC CPU IF ) Base Address */\n#define VE_A9_MP_PRIVATE_TIMER                (0x00000600UL + VE_A9_MP_PRIVATE_PERIPH_BASE) /*!< (PTIM       ) Base Address */\n#define VE_A9_MP_SSRAM_BASE                   (0x2E000000UL)                                /*!< (System SRAM) Base Address */\n#define VE_A9_MP_DRAM_BASE                    (0x80000000UL)                                /*!< (DRAM       ) Base Address */\n#define GIC_DISTRIBUTOR_BASE                  VE_A9_MP_GIC_DISTRIBUTOR_BASE\n#define GIC_INTERFACE_BASE                    VE_A9_MP_GIC_INTERFACE_BASE\n#define TIMER_BASE                            VE_A9_MP_PRIVATE_TIMER\n\n//The VE-A9 model implements L1 cache as architecturally defined, but does not implement L2 cache.\n//Do not enable the L2 cache if you are running RTX on a VE-A9 model as it may cause a data abort.\n#define L2C_310_BASE                          VE_A9_MP_PL310_BASE\n\n/* --------  Configuration of the Cortex-A9 Processor and Core Peripherals  ------- */\n#define __CA_REV        0x0000U    /*!< Core revision r0p0                          */\n#define __CORTEX_A           9U    /*!< Cortex-A9 Core                              */\n#define __FPU_PRESENT        1U    /* FPU present                                   */\n#define __GIC_PRESENT        1U    /* GIC present                                   */\n#define __TIM_PRESENT        1U    /* TIM present                                   */\n#define __L2C_PRESENT        0U    /* L2C present                                   */\n\n#include \"core_ca.h\"\n#include <system_ARMCA9.h>\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  // __ARMCA9_H__\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/AC5/ARMCA9.sct",
    "content": "#! armcc -E\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA9.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/AC5/startup_ARMCA9.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A9 Device Series\n * @version  V1.00\n * @date     10. January 2018\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA9.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors       (void) __attribute__ ((section(\"RESET\")));\nvoid Reset_Handler (void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n__ASM void Vectors(void) {\n  PRESERVE8\n  \n  IMPORT Undef_Handler\n  IMPORT SVC_Handler\n  IMPORT PAbt_Handler\n  IMPORT DAbt_Handler\n  IMPORT IRQ_Handler\n  IMPORT FIQ_Handler\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__ASM void Reset_Handler(void) {\n  PRESERVE8\n\n  // Mask interrupts\n  CPSID  if                           \n\n  // Put any cores other than 0 to sleep\n  MRC    p15, 0, R0, c0, c0, 5       // Read MPIDR\n  ANDS   R0, R0, #3\ngoToSleep\n  WFINE\n  BNE    goToSleep\n\n  // Reset SCTLR Settings\n  MRC    p15, 0, R0, c1, c0, 0       // Read CP15 System Control register\n  BIC    R0, R0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache\n  BIC    R0, R0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache\n  BIC    R0, R0, #0x1                // Clear M bit  0 to disable MMU\n  BIC    R0, R0, #(0x1 << 11)        // Clear Z bit 11 to disable branch prediction\n  BIC    R0, R0, #(0x1 << 13)        // Clear V bit 13 to disable hivecs\n  MCR    p15, 0, R0, c1, c0, 0       // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC    p15, 0, r0, c1, c0, 1       // Read CP15 Auxiliary Control Register\n  ORR    r0, r0, #(1 <<  1)          // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR    p15, 0, r0, c1, c0, 1       // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exceptional mode\n  IMPORT |Image$$FIQ_STACK$$ZI$$Limit|\n  IMPORT |Image$$IRQ_STACK$$ZI$$Limit|\n  IMPORT |Image$$SVC_STACK$$ZI$$Limit|\n  IMPORT |Image$$ABT_STACK$$ZI$$Limit|\n  IMPORT |Image$$UND_STACK$$ZI$$Limit|\n  IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|\n  CPS    #0x11\n  LDR    SP, =|Image$$FIQ_STACK$$ZI$$Limit|\n  CPS    #0x12\n  LDR    SP, =|Image$$IRQ_STACK$$ZI$$Limit|\n  CPS    #0x13\n  LDR    SP, =|Image$$SVC_STACK$$ZI$$Limit|\n  CPS    #0x17\n  LDR    SP, =|Image$$ABT_STACK$$ZI$$Limit|\n  CPS    #0x1B\n  LDR    SP, =|Image$$UND_STACK$$ZI$$Limit|\n  CPS    #0x1F\n  LDR    SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|\n\n  // Call SystemInit\n  IMPORT SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __main\n  IMPORT __main\n  BL     __main\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/AC6/ARMCA9.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for RTX Example on Versatile Express\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n; This platform has 2GB SDRAM starting at 0x80000000.\n\n#include \"mem_ARMCA9.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n  \n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n  \n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n  \n  ARM_LIB_HEAP  (__RAM_BASE\n                +__RW_DATA_SIZE\n                +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n    \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n  \n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n  \n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n  \n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n  \n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }\n  \n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/AC6/startup_ARMCA9.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A9 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA9.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void) __attribute__ ((noreturn));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n  \"LDR    SP, =Image$$ARM_LIB_STACK$$ZI$$Limit     \\n\"\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n  \"BL     __main                                   \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/GCC/ARMCA9.ld",
    "content": "#include \"mem_ARMCA9.h\" \n\nMEMORY\n{\n  ROM (rx)   : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  L_TTB (rw) : ORIGIN = __TTB_BASE, LENGTH = __TTB_SIZE \n  RAM (rwx)  : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n    .text :\n    {\n\n        Image$$VECTORS$$Base = .;\n        * (RESET)\n        KEEP(*(.isr_vector))\n        Image$$VECTORS$$Limit = .;\n\n        *(SVC_TABLE)\n        *(.text*)\n\n        KEEP(*(.init))\n        KEEP(*(.fini))\n\n        /* .ctors */\n        *crtbegin.o(.ctors)\n        *crtbegin?.o(.ctors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n        *(SORT(.ctors.*))\n        *(.ctors)\n\n        /* .dtors */\n        *crtbegin.o(.dtors)\n        *crtbegin?.o(.dtors)\n        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n        *(SORT(.dtors.*))\n        *(.dtors)\n\n        Image$$RO_DATA$$Base = .;\n        *(.rodata*)\n        Image$$RO_DATA$$Limit = .;\n\n        KEEP(*(.eh_frame*))\n    } > ROM\n\n    .ARM.extab : \n    {\n        *(.ARM.extab* .gnu.linkonce.armextab.*)\n    } > ROM\n\n    __exidx_start = .;\n    .ARM.exidx :\n    {\n        *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n    } > ROM\n    __exidx_end = .;\n\n\n    .copy.table :\n    {\n        . = ALIGN(4);\n        __copy_table_start__ = .;\n        LONG (__etext)\n        LONG (__data_start__)\n        LONG (__data_end__ - __data_start__)\n        __copy_table_end__ = .;\n    } > ROM\n\n    .zero.table :\n    {\n        . = ALIGN(4);\n        __zero_table_start__ = .;\n        LONG (__bss_start__)\n        LONG (__bss_end__ - __bss_start__)\n        __zero_table_end__ = .;\n    } > ROM\n\n    __etext = .;\n        \n    .ttb :\n    {\n        Image$$TTB$$ZI$$Base = .;\n        . += __TTB_SIZE;\n        Image$$TTB$$ZI$$Limit = .;\n    } > L_TTB\n\n    .data : AT (__etext)\n    {\n        Image$$RW_DATA$$Base = .;\n        __data_start__ = .;\n        *(vtable)\n        *(.data*)\n        Image$$RW_DATA$$Limit = .;\n\n        . = ALIGN(4);\n        /* preinit data */\n        PROVIDE (__preinit_array_start = .);\n        KEEP(*(.preinit_array))\n        PROVIDE (__preinit_array_end = .);\n\n        . = ALIGN(4);\n        /* init data */\n        PROVIDE (__init_array_start = .);\n        KEEP(*(SORT(.init_array.*)))\n        KEEP(*(.init_array))\n        PROVIDE (__init_array_end = .);\n\n\n        . = ALIGN(4);\n        /* finit data */\n        PROVIDE (__fini_array_start = .);\n        KEEP(*(SORT(.fini_array.*)))\n        KEEP(*(.fini_array))\n        PROVIDE (__fini_array_end = .);\n\n        . = ALIGN(4);\n        /* All data end */\n        __data_end__ = .;\n\n    } > RAM\n\n    \n    .bss ALIGN(0x400):\n    {\n        Image$$ZI_DATA$$Base = .;\n        __bss_start__ = .;\n        *(.bss*)\n        *(COMMON)\n        __bss_end__ = .;\n        Image$$ZI_DATA$$Limit = .;\n        __end__ = .;\n        end = __end__;\n    } > RAM\n\n#if defined(__HEAP_SIZE) && (__HEAP_SIZE > 0)    \n    .heap (NOLOAD):\n    {\n        . = ALIGN(8);\n        Image$$HEAP$$ZI$$Base = .;\n        . += __HEAP_SIZE;\n        Image$$HEAP$$ZI$$Limit = .;\n        __HeapLimit = .;\n    } > RAM  \n#endif\n\n    .stack (NOLOAD):\n    {\n        . = ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __FIQ_STACK_SIZE - __IRQ_STACK_SIZE - __SVC_STACK_SIZE - __ABT_STACK_SIZE - __UND_STACK_SIZE;\n        . = ALIGN(8);\n        \n        __StackTop = .;\n        Image$$SYS_STACK$$ZI$$Base = .;\n        . += __STACK_SIZE;\n        Image$$SYS_STACK$$ZI$$Limit = .;\n        __stack = .;\n\n        Image$$FIQ_STACK$$ZI$$Base = .;\n        . += __FIQ_STACK_SIZE;\n        Image$$FIQ_STACK$$ZI$$Limit = .;\n\n        Image$$IRQ_STACK$$ZI$$Base = .;\n        . += __IRQ_STACK_SIZE;\n        Image$$IRQ_STACK$$ZI$$Limit = .;\n\n        Image$$SVC_STACK$$ZI$$Base = .;\n        . += __SVC_STACK_SIZE;\n        Image$$SVC_STACK$$ZI$$Limit = .;\n\n        Image$$ABT_STACK$$ZI$$Base = .;\n        . += __ABT_STACK_SIZE;\n        Image$$ABT_STACK$$ZI$$Limit = .;\n\n        Image$$UND_STACK$$ZI$$Base = .;\n        . += __UND_STACK_SIZE;\n        Image$$UND_STACK$$ZI$$Limit = .;\n        \n    } > RAM\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/GCC/startup_ARMCA9.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A9 Device Series\n * @version  V1.0.1\n * @date     10. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <ARMCA9.h>\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors        (void) __attribute__ ((naked, section(\"RESET\")));\nvoid Reset_Handler  (void) __attribute__ ((naked));\nvoid Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\nvoid Vectors(void) {\n  __ASM volatile(\n  \"LDR    PC, =Reset_Handler                        \\n\"\n  \"LDR    PC, =Undef_Handler                        \\n\"\n  \"LDR    PC, =SVC_Handler                          \\n\"\n  \"LDR    PC, =PAbt_Handler                         \\n\"\n  \"LDR    PC, =DAbt_Handler                         \\n\"\n  \"NOP                                              \\n\"\n  \"LDR    PC, =IRQ_Handler                          \\n\"\n  \"LDR    PC, =FIQ_Handler                          \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\nvoid Reset_Handler(void) {\n  __ASM volatile(\n\n  // Mask interrupts\n  \"CPSID   if                                      \\n\"\n\n  // Put any cores other than 0 to sleep\n  \"MRC     p15, 0, R0, c0, c0, 5                   \\n\"  // Read MPIDR\n  \"ANDS    R0, R0, #3                              \\n\"\n  \"goToSleep:                                      \\n\"\n  \"WFINE                                           \\n\"\n  \"BNE     goToSleep                               \\n\"\n\n  // Reset SCTLR Settings\n  \"MRC     p15, 0, R0, c1, c0, 0                   \\n\"  // Read CP15 System Control register\n  \"BIC     R0, R0, #(0x1 << 12)                    \\n\"  // Clear I bit 12 to disable I Cache\n  \"BIC     R0, R0, #(0x1 <<  2)                    \\n\"  // Clear C bit  2 to disable D Cache\n  \"BIC     R0, R0, #0x1                            \\n\"  // Clear M bit  0 to disable MMU\n  \"BIC     R0, R0, #(0x1 << 11)                    \\n\"  // Clear Z bit 11 to disable branch prediction\n  \"BIC     R0, R0, #(0x1 << 13)                    \\n\"  // Clear V bit 13 to disable hivecs\n  \"MCR     p15, 0, R0, c1, c0, 0                   \\n\"  // Write value back to CP15 System Control register\n  \"ISB                                             \\n\"\n\n  // Configure ACTLR\n  \"MRC     p15, 0, r0, c1, c0, 1                   \\n\"  // Read CP15 Auxiliary Control Register\n  \"ORR     r0, r0, #(1 <<  1)                      \\n\"  // Enable L2 prefetch hint (UNK/WI since r4p1)\n  \"MCR     p15, 0, r0, c1, c0, 1                   \\n\"  // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  \"LDR    R0, =Vectors                             \\n\"\n  \"MCR    p15, 0, R0, c12, c0, 0                   \\n\"\n\n  // Setup Stack for each exceptional mode\n  \"CPS    #0x11                                    \\n\"\n  \"LDR    SP, =Image$$FIQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x12                                    \\n\"\n  \"LDR    SP, =Image$$IRQ_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x13                                    \\n\"\n  \"LDR    SP, =Image$$SVC_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x17                                    \\n\"\n  \"LDR    SP, =Image$$ABT_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1B                                    \\n\"\n  \"LDR    SP, =Image$$UND_STACK$$ZI$$Limit         \\n\"\n  \"CPS    #0x1F                                    \\n\"\n  \"LDR    SP, =Image$$SYS_STACK$$ZI$$Limit         \\n\"\n\n  // Call SystemInit\n  \"BL     SystemInit                               \\n\"\n\n  // Unmask interrupts\n  \"CPSIE  if                                       \\n\"\n\n  // Call __main\n  \"BL     _start                                   \\n\"\n  );\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/IAR/ARMCA9.icf",
    "content": "\n/*-Memory Regions-*/\ndefine symbol __ICFEDIT_region_IROM1_start__ = 0x80000000;\ndefine symbol __ICFEDIT_region_IROM1_end__   = 0x801FFFFF;\ndefine symbol __ICFEDIT_region_IROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_EROM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000;\ndefine symbol __ICFEDIT_region_IRAM1_end__   = 0x803FFFFF;\ndefine symbol __ICFEDIT_region_IRAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_IRAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM1_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM2_end__   = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_start__ = 0x0;\ndefine symbol __ICFEDIT_region_ERAM3_end__   = 0x0;\ndefine symbol __ICFEDIT_region_TTB_start__   = 0x80500000;\ndefine symbol __ICFEDIT_region_TTB_end__     = 0x805FFFFF;\n\n/*-Sizes-*/\ndefine symbol __ICFEDIT_size_cstack__        = 0x1000;\ndefine symbol __ICFEDIT_size_irqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_fiqstack__      = 0x100;\ndefine symbol __ICFEDIT_size_svcstack__      = 0x100;\ndefine symbol __ICFEDIT_size_abtstack__      = 0x100;\ndefine symbol __ICFEDIT_size_undstack__      = 0x100;\ndefine symbol __ICFEDIT_size_heap__          = 0x8000;\ndefine symbol __ICFEDIT_size_ttb__           = 0x4000;\n\ndefine memory mem with size = 4G;\ndefine region IROM_region   =   mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]\n                              | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];\ndefine region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]\n                              | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];\ndefine region ERAM_region   =   mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]\n                              | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]\n                              | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];\ndefine region TTB_region    =   mem:[from __ICFEDIT_region_TTB_start__   to __ICFEDIT_region_TTB_end__  ];\n\ndefine block USR_STACK     with alignment = 8, size = __ICFEDIT_size_cstack__        { };\ndefine block IRQ_STACK     with alignment = 8, size = __ICFEDIT_size_irqstack__      { };\ndefine block FIQ_STACK     with alignment = 8, size = __ICFEDIT_size_fiqstack__      { };\ndefine block SVC_STACK     with alignment = 8, size = __ICFEDIT_size_svcstack__      { };\ndefine block ABT_STACK     with alignment = 8, size = __ICFEDIT_size_abtstack__      { };\ndefine block UND_STACK     with alignment = 8, size = __ICFEDIT_size_undstack__      { };\ndefine block HEAP          with alignment = 8, size = __ICFEDIT_size_heap__          { };\ndefine block TTB           with alignment = 8, size = __ICFEDIT_size_ttb__           { section TTB };\n\ndo not initialize  { section .noinit };\n\ninitialize by copy { readwrite };\nif (isdefinedsymbol(__USE_DLIB_PERTHREAD))\n{\n  // Required in a multi-threaded application\n  initialize by copy with packing = none { section __DLIB_PERTHREAD };\n}\n\nplace at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET };\nplace in IROM_region  { readonly };\nplace in IRAM_region  { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK };\nplace in TTB_region   { block TTB };"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/IAR/startup_ARMCA9.s",
    "content": "/******************************************************************************\n * @file     startup_ARMCA9.s\n * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series\n * @version  V1.00\n * @date     01 Nov 2017\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n  MODULE  ?startup_ARMCA9\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n  PUBLIC  Reset_Handler\n  PUBWEAK Undef_Handler\n  PUBWEAK SVC_Handler\n  PUBWEAK PAbt_Handler\n  PUBWEAK DAbt_Handler\n  PUBWEAK IRQ_Handler\n  PUBWEAK FIQ_Handler\n\n  SECTION SVC_STACK:DATA:NOROOT(3)\n  SECTION IRQ_STACK:DATA:NOROOT(3)\n  SECTION FIQ_STACK:DATA:NOROOT(3)\n  SECTION ABT_STACK:DATA:NOROOT(3)\n  SECTION UND_STACK:DATA:NOROOT(3)\n  SECTION USR_STACK:DATA:NOROOT(3)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n\n  section RESET:CODE:NOROOT(2)\n  PUBLIC  Vectors\n\nVectors:\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n\n\n  section .text:CODE:NOROOT(2)\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n  *----------------------------------------------------------------------------*/\n  EXTERN  SystemInit\n  EXTERN  __iar_program_start\n\nReset_Handler:  \n\n  // Mask interrupts\n  CPSID   if\n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5\n  ANDS    R0, R0, #3\ngoToSleep:\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0 // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2) // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1       // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1) // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exception mode\n  CPS    #0x11\n  LDR    SP, =SFE(FIQ_STACK)\n  CPS    #0x12\n  LDR    SP, =SFE(IRQ_STACK)\n  CPS    #0x13\n  LDR    SP, =SFE(SVC_STACK)\n  CPS    #0x17\n  LDR    SP, =SFE(ABT_STACK)\n  CPS    #0x1B\n  LDR    SP, =SFE(UND_STACK)\n  CPS    #0x1F\n  LDR    SP, =SFE(USR_STACK)\n\n  // Call SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __iar_program_start\n  BL     __iar_program_start\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nUndef_Handler:\nSVC_Handler:\nPAbt_Handler:\nDAbt_Handler:\nIRQ_Handler:\nFIQ_Handler:\nDefault_Handler:\n  B .\n\n  END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/mmu_ARMCA9.c",
    "content": "/**************************************************************************//**\n * @file     mmu_ARMCA9.c\n * @brief    MMU Configuration for Arm Cortex-A9 Device Series\n * @version  V1.2.0\n * @date     15. May 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map\n\n                                                     Memory Type\n0xffffffff |--------------------------|             ------------\n           |       FLAG SYNC          |             Device Memory\n0xfffff000 |--------------------------|             ------------\n           |         Fault            |                Fault\n0xfff00000 |--------------------------|             ------------\n           |                          |                Normal\n           |                          |\n           |      Daughterboard       |\n           |         memory           |\n           |                          |\n0x80505000 |--------------------------|             ------------\n           |TTB (L2 Sync Flags   ) 4k |                Normal\n0x80504C00 |--------------------------|             ------------\n           |TTB (L2 Peripherals-B) 16k|                Normal\n0x80504800 |--------------------------|             ------------\n           |TTB (L2 Peripherals-A) 16k|                Normal\n0x80504400 |--------------------------|             ------------\n           |TTB (L2 Priv Periphs)  4k |                Normal\n0x80504000 |--------------------------|             ------------\n           |    TTB (L1 Descriptors)  |                Normal\n0x80500000 |--------------------------|             ------------\n           |          Stack           |                Normal\n           |--------------------------|             ------------\n           |          Heap            |                Normal\n0x80400000 |--------------------------|             ------------\n           |         ZI Data          |                Normal\n0x80300000 |--------------------------|             ------------\n           |         RW Data          |                Normal\n0x80200000 |--------------------------|             ------------\n           |         RO Data          |                Normal\n           |--------------------------|             ------------\n           |         RO Code          |              USH Normal\n0x80000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |      HSB AXI buses       |\n0x40000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x2c002000 |--------------------------|             ------------\n           |     Private Address      |            Device Memory\n0x2c000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x20000000 |--------------------------|             ------------\n           |       Peripherals        |           Device Memory RW/RO\n           |                          |              & Fault\n0x00000000 |--------------------------|\n*/\n\n// L1 Cache info and restrictions about architecture of the caches (CCSIR register):\n// Write-Through support *not* available\n// Write-Back support available.\n// Read allocation support available.\n// Write allocation support available.\n\n//Note: You should use the Shareable attribute carefully.\n//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.\n//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.\n//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.\n\n//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.\n//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.\n//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.\n\n\n//Following MMU configuration is expected\n//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)\n//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)\n//Domain 0 is always the Client domain\n//Descriptors should place all memory in domain 0\n\n#include \"ARMCA9.h\"\n#include \"mem_ARMCA9.h\"\n\n// TTB base address\n#define TTB_BASE ((uint32_t*)__TTB_BASE)\n\n// L2 table pointers\n//----------------------------------------\n#define TTB_L1_SIZE                    (0x00004000)                        // The L1 translation table divides the full 4GB address space of a 32-bit core\n                                                                           // into 4096 equally sized sections, each of which describes 1MB of virtual memory space.\n                                                                           // The L1 translation table therefore contains 4096 32-bit (word-sized) entries.\n\n#define PRIVATE_TABLE_L2_BASE_4k       (__TTB_BASE + TTB_L1_SIZE)          // Map 4k Private Address space\n#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400)  // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF\n#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800)  // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF\n#define SYNC_FLAGS_TABLE_L2_BASE_4k    (__TTB_BASE + TTB_L1_SIZE + 0xC00)  // Map 4k Flag synchronization\n\n//--------------------- PERIPHERALS -------------------\n#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)\n#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)\n\n//--------------------- SYNC FLAGS --------------------\n#define FLAG_SYNC     0xFFFFF000\n#define F_SYNC_BASE   0xFFF00000  //1M aligned\n\nstatic uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0\nstatic uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable\nstatic uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable\nstatic uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable\n\n/* Define global descriptors */\nstatic uint32_t Page_L1_4k  = 0x0;  //generic\nstatic uint32_t Page_L1_64k = 0x0;  //generic\nstatic uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0\nstatic uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0\n\nvoid MMU_CreateTranslationTable(void)\n{\n    mmu_region_attributes_Type region;\n\n    //Create 4GB of faulting entries\n    MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);\n\n    /*\n     * Generate descriptors. Refer to core_ca.h to get information about attributes\n     *\n     */\n    //Create descriptors for Vectors, RO, RW, ZI sections\n    section_normal(Sect_Normal, region);\n    section_normal_cod(Sect_Normal_Cod, region);\n    section_normal_ro(Sect_Normal_RO, region);\n    section_normal_rw(Sect_Normal_RW, region);\n    //Create descriptors for peripherals\n    section_device_ro(Sect_Device_RO, region);\n    section_device_rw(Sect_Device_RW, region);\n    //Create descriptors for 64k pages\n    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);\n    //Create descriptors for 4k pages\n    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);\n\n\n    /*\n     *  Define MMU flat-map regions and attributes\n     *\n     */\n\n    //Define Image\n    MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections\n    MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW);  // multiple of 1MB sections\n\n    //--------------------- PERIPHERALS -------------------\n    MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE0   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A9_MP_FLASH_BASE1   , 64, Sect_Device_RO); // 64MB NOR\n    MMU_TTSection (TTB_BASE, VE_A9_MP_SRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A9_MP_VRAM_BASE     , 32, Sect_Device_RW); // 32MB RAM\n    MMU_TTSection (TTB_BASE, VE_A9_MP_ETHERNET_BASE , 16, Sect_Device_RW);\n    MMU_TTSection (TTB_BASE, VE_A9_MP_USB_BASE      , 16, Sect_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C000000-0x1C00FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_DAP_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_SYSTEM_REG_BASE,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_SERIAL_BASE    ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_AACI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_MMCI_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_KMI0_BASE      ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART_BASE      ,  4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_WDT_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT      , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n    // Define peripheral range 0x1C100000-0x1C10FFFF\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_TIMER_BASE     ,  2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_DVI_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_RTC_BASE       ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_UART4_BASE     ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n    MMU_TTPage64k(TTB_BASE, VE_A9_MP_CLCD_BASE      ,  1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,256,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define private address space entry.\n    MMU_TTPage4k (TTB_BASE, __get_CBAR()            ,  2,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n    // Define L2CC entry.  Uncomment if PL310 is present\n    //    MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE     ,  1,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)\n    MMU_TTPage4k (TTB_BASE, F_SYNC_BASE             , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n    // Define synchronization space entry.\n    MMU_TTPage4k (TTB_BASE, FLAG_SYNC               ,   1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n    /* Set location of level 1 page table\n    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)\n    ; 13:7  - 0x0\n    ; 6     - IRGN[0] 0x1  (Inner WB WA)\n    ; 5     - NOS     0x0  (Non-shared)\n    ; 4:3   - RGN     0x01 (Outer WB WA)\n    ; 2     - IMP     0x0  (Implementation Defined)\n    ; 1     - S       0x0  (Non-shared)\n    ; 0     - IRGN[1] 0x0  (Inner WB WA) */\n    __set_TTBR0(__TTB_BASE | 0x48);\n    __ISB();\n\n    /* Set up domain access control register\n    ; We set domain 0 to Client and all other domains to No Access.\n    ; All translation table entries specify domain 0 */\n    __set_DACR(1);\n    __ISB();\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCA9/Source/system_ARMCA9.c",
    "content": "/******************************************************************************\n * @file     system_ARMCA9.c\n * @brief    CMSIS Device System Source File for Arm Cortex-A9 Device Series\n * @version  V1.0.1\n * @date     13. February 2019\n *\n * @note\n *\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"RTE_Components.h\"\n#include CMSIS_device_header\n#include \"irq_ctrl.h\"\n\n#define  SYSTEM_CLOCK  12000000U\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System Initialization\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* do not use global variables because this function is called before\n   reaching pre-main. RW section may be overwritten afterwards.          */\n\n  // Invalidate entire Unified TLB\n  __set_TLBIALL(0);\n\n  // Invalidate entire branch predictor array\n  __set_BPIALL(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate instruction cache and flush branch target cache\n  __set_ICIALLU(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate data cache\n  L1C_InvalidateDCacheAll();\n\n#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\n  // Enable FPU\n  __FPU_Enable();\n#endif\n\n  // Create Translation Table\n  MMU_CreateTranslationTable();\n\n  // Enable MMU\n  MMU_Enable();\n\n  // Enable Caches\n  L1C_EnableCaches();\n  L1C_EnableBTAC();\n\n#if (__L2C_PRESENT == 1) \n  // Enable GIC\n  L2C_Enable();\n#endif\n\n  // IRQ Initialize\n  IRQ_Initialize();\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Include/ARMCM0.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM0.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM0 Device\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM0_H\n#define ARMCM0_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n\n\n\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 30 are left out */\n  Interrupt31_IRQn              =   31\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM0_REV                 0x0000U   /* Core revision r0p0 */\n#define __MPU_PRESENT             0U        /* no MPU present */\n#define __VTOR_PRESENT            0U        /* no VTOR present */\n#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_cm0.h\"                       /* Processor and core peripherals */\n#include \"system_ARMCM0.h\"                  /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM0_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Include/system_ARMCM0.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM0.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM0 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM0_H\n#define SYSTEM_ARMCM0_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM0_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac5.sct",
    "content": "#! armcc -E\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Source/ARM/ARMCM0_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Source/ARM/startup_ARMCM0.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM0.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM0 Device\n; * @version  V1.0.1\n; * @date     23. July 2019\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nStack_Size      EQU      0x00000400\n\n                AREA     STACK, NOINIT, READWRITE, ALIGN=3\n__stack_limit\nStack_Mem       SPACE    Stack_Size\n__initial_sp\n\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nHeap_Size       EQU      0x00000C00\n\n                IF       Heap_Size != 0                      ; Heap is provided\n                AREA     HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE    Heap_Size\n__heap_limit\n                ENDIF\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n\n__Vectors       DCD      __initial_sp                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                SPACE    ( 22 * 4)                           ; Interrupts 10 .. 31 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; Default exception/interrupt handler\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Source/GCC/startup_ARMCM0.S",
    "content": "/**************************************************************************//**\n * @file     startup_ARMCM0.S\n * @brief    CMSIS-Core(M) Device Startup File for Cortex-M0 Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv6-m\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __StackTop                         /*     Top of Stack */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   ( 22 * 4)                          /* Interrupts 10 .. 31 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                blt      .L_loop0_0_done\n                ldr      r0, [r1, r3]\n                str      r0, [r2, r3]\n                b        .L_loop0_0\n\n.L_loop0_0_done:\n                adds     r4, #12\n                b        .L_loop0\n\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                blt      .L_loop2_0_done\n                str      r0, [r1, r2]\n                b        .L_loop2_0\n.L_loop2_0_done:\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Source/IAR/startup_ARMCM0.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM0.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM0 Device\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    ( 22)                                ; Interrupts 10 .. 31 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nSVC_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Source/startup_ARMCM0.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM0.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M0 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM0)\n  #include \"ARMCM0.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10..31 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0/Source/system_ARMCM0.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM0.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM0 Device\n * @version  V1.0.0\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM0.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Include/ARMCM0plus.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM0plus.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM0plus Device\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM0plus_H\n#define ARMCM0plus_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n\n\n\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 30 are left out */\n  Interrupt31_IRQn              =   31\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM0PLUS_REV             0x0001U   /* Core revision r0p1 */\n#define __MPU_PRESENT             0U        /* no MPU present */\n#define __VTOR_PRESENT            0U        /* no VTOR present */\n#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_cm0plus.h\"                   /* Processor and core peripherals */\n#include \"system_ARMCM0plus.h\"              /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM0plus_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM0plus_MPU.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM0plus Device (configured for CM0+ with MPU)\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM0plus_MPU_H\n#define ARMCM0plus_MPU_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n\n\n\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 30 are left out */\n  Interrupt31_IRQn              =   31\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM0PLUS_REV             0x0001U   /* Core revision r0p1 */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            0U        /* no VTOR present */\n#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_cm0plus.h\"                   /* Processor and core peripherals */\n#include \"system_ARMCM0plus.h\"              /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM0plus_MPU_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Include/system_ARMCM0plus.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM0plus.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM0 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM0plus_H\n#define SYSTEM_ARMCM0plus_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM0plus_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac5.sct",
    "content": "#! armcc -E\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/ARMCM0plus_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Source/ARM/startup_ARMCM0plus.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM0plus.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM0plus Device\n; * @version  V1.0.1\n; * @date     23. July 2019\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nStack_Size      EQU      0x00000400\n\n                AREA     STACK, NOINIT, READWRITE, ALIGN=3\n__stack_limit\nStack_Mem       SPACE    Stack_Size\n__initial_sp\n\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nHeap_Size       EQU      0x00000C00\n\n                IF       Heap_Size != 0                      ; Heap is provided\n                AREA     HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE    Heap_Size\n__heap_limit\n                ENDIF\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n\n__Vectors       DCD      __initial_sp                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                SPACE    ( 22 * 4)                           ; Interrupts 10 .. 31 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; Default exception/interrupt handler\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Source/GCC/startup_ARMCM0plus.S",
    "content": "/**************************************************************************//**\n * @file     startup_ARMCM0plus.S\n * @brief    CMSIS-Core(M) Device Startup File for Cortex-M0plus Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv6-m\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __StackTop                         /*     Top of Stack */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   ( 22 * 4)                          /* Interrupts 10 .. 31 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                blt      .L_loop0_0_done\n                ldr      r0, [r1, r3]\n                str      r0, [r2, r3]\n                b        .L_loop0_0\n\n.L_loop0_0_done:\n                adds     r4, #12\n                b        .L_loop0\n\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                blt      .L_loop2_0_done\n                str      r0, [r1, r2]\n                b        .L_loop2_0\n.L_loop2_0_done:\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Source/IAR/startup_ARMCM0plus.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM0plus.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM0plus Device\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    ( 22)                                ; Interrupts 10 .. 31 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nSVC_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Source/startup_ARMCM0plus.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM0plus.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM0P)\n  #include \"ARMCM0plus.h\"\n#elif defined (ARMCM0P_MPU)\n  #include \"ARMCM0plus_MPU.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10..31 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM0plus/Source/system_ARMCM0plus.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM0plus.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM0plus Device\n * @version  V1.0.1\n * @date     01. June 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM0plus.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Include/ARMCM1.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM1.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM1 Device\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM1_H\n#define ARMCM1_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n\n\n\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 30 are left out */\n  Interrupt31_IRQn              =   31\n} IRQn_Type;\n\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM1_REV                 0x0100U   /* Core revision r1p0 */\n#define __MPU_PRESENT             0U        /* no MPU present */\n#define __VTOR_PRESENT            0U        /* no VTOR present */\n#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_cm1.h\"                       /* Processor and core peripherals */\n#include \"system_ARMCM1.h\"                  /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM1_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Include/system_ARMCM1.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM1.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM1 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM1_H\n#define SYSTEM_ARMCM1_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM1_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac5.sct",
    "content": "#! armcc -E\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/ARMCM1_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m1 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Source/ARM/startup_ARMCM1.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM1.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM1 Device\n; * @version  V1.0.1\n; * @date     23. July 2019\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nStack_Size      EQU      0x00000400\n\n                AREA     STACK, NOINIT, READWRITE, ALIGN=3\n__stack_limit\nStack_Mem       SPACE    Stack_Size\n__initial_sp\n\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nHeap_Size       EQU      0x00000C00\n\n                IF       Heap_Size != 0                      ; Heap is provided\n                AREA     HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE    Heap_Size\n__heap_limit\n                ENDIF\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n\n__Vectors       DCD      __initial_sp                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                SPACE    ( 22 * 4)                           ; Interrupts 10 .. 31 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; Default exception/interrupt handler\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Source/GCC/startup_ARMCM1.S",
    "content": "/**************************************************************************//**\n * @file     startup_ARMCM1.S\n * @brief    CMSIS-Core(M) Device Startup File for Cortex-M1 Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv6-m\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __StackTop                         /*     Top of Stack */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   ( 22 * 4)                          /* Interrupts 10 .. 31 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                blt      .L_loop0_0_done\n                ldr      r0, [r1, r3]\n                str      r0, [r2, r3]\n                b        .L_loop0_0\n\n.L_loop0_0_done:\n                adds     r4, #12\n                b        .L_loop0\n\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                blt      .L_loop2_0_done\n                str      r0, [r1, r2]\n                b        .L_loop2_0\n.L_loop2_0_done:\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Source/IAR/startup_ARMCM1.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM1.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM1 Device\n; * @version  V1.0.0\n; * @date     20. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    ( 22)                                ; Interrupts 10 .. 31 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nSVC_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Source/startup_ARMCM1.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM1.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M1 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM1)\n  #include \"ARMCM1.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10..31 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM1/Source/system_ARMCM1.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM1.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM1 Device\n * @version  V1.0.0\n * @date     20. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM1.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Debug/ARMv8MBL.dbgconf",
    "content": "// <<< Use Configuration Wizard in Context Menu >>>\n\n// <e> Fixed Debug Authentication\n// <i> Use a fixed value for Debug Authentication. Only secure debug authentication configurable.\nDAuthFixed  = 0x1;\n\n//   <q.2> Secure Invasive Debug\n//   <q.3> Secure Non-Invasive Debug\nDAuthConfig = 0xF;\n\n// </e>\n\n// <<< end of configuration section >>>"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Include/ARMCM23.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM23.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM23 Device\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM23_H\n#define ARMCM23_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n\n\n\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 223 are left out */\n  Interrupt224_IRQn             =   224\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM23_REV                0x0100U   /* Core revision r1p0 */\n#define __SAUREGION_PRESENT       0U        /* SAU regions are not present */\n#define __MPU_PRESENT             1U        /* MPU is present */\n#define __VTOR_PRESENT            1U        /* VTOR is present */\n#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_cm23.h\"                      /* Processor and core peripherals */\n#include \"system_ARMCM23.h\"                 /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM23_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Include/ARMCM23_TZ.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM23_TZ.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM23 Device (configured for TrustZone)\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM23_TZ_H\n#define ARMCM23_TZ_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n\n\n\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 223 are left out */\n  Interrupt224_IRQn             =   224\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM23_REV                0x0100U   /* Core revision r1p0 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions are present */\n#define __MPU_PRESENT             1U        /* MPU is present */\n#define __VTOR_PRESENT            1U        /* VTOR is present */\n#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_cm23.h\"                      /* Processor and core peripherals */\n#include \"system_ARMCM23.h\"                 /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM23_TZ_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Include/Template/partition_ARMCM23.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM23.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23\n * @version  V1.0.0\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM23_H\n#define PARTITION_ARMCM23_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n\n/*\n// <e>Setup behaviour of single SysTick\n*/\n#define SCB_ICSR_INIT 0\n\n/*\n//   <o> in a single SysTick implementation, SysTick is\n//     <0=>Secure\n//     <1=>Non-Secure\n//   <i> Value for SCB->ICSR register bit STTNS\n//   <i> only for single SysTick implementation \n*/\n#define SCB_ICSR_STTNS_VAL  0\n\n/*\n// </e>\n*/\n\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk |  SCB_AIRCR_PRIS_Msk)        )                     |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)\n    SCB->ICSR  = (SCB->ICSR  & ~(SCB_ICSR_STTNS_Msk        )) |\n                   ((SCB_ICSR_STTNS_VAL         << SCB_ICSR_STTNS_Pos)         & SCB_ICSR_STTNS_Msk);\n  #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM23_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Include/system_ARMCM23.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM23.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM23 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM23_H\n#define SYSTEM_ARMCM23_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM23_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/ARMCM23_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Source/ARM/startup_ARMCM23.S",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.S\n * @brief    CMSIS-Core Device Startup File for Cortex-M23 Device\n * @version  V2.0.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.base\n\n                #define __INITIAL_SP     Image$$ARM_LIB_STACK$$ZI$$Limit\n                #define __STACK_LIMIT    Image$$ARM_LIB_STACK$$ZI$$Base\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     Image$$STACKSEAL$$ZI$$Base\n                #endif\n\n                .section RESET\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (214 * 4)                          /* Interrupts 10 .. 224 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                str      r1,[r0,#0]\n                str      r1,[r0,#4]\n                #endif\n\n                bl       SystemInit\n\n                bl       __main\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Source/GCC/startup_ARMCM23.S",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.S\n * @brief    CMSIS-Core Device Startup File for Cortex-M23 Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.base\n\n                #define __INITIAL_SP     __StackTop\n                #define __STACK_LIMIT    __StackLimit\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     __StackSeal\n                #endif\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (214 * 4)                          /* Interrupts 10 .. 224 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                str      r1,[r0,#0]\n                str      r1,[r0,#4]\n                #endif\n\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                blt      .L_loop0_0_done\n                ldr      r0, [r1, r3]\n                str      r0, [r2, r3]\n                b        .L_loop0_0\n\n.L_loop0_0_done:\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                blt      .L_loop2_0_done\n                str      r0, [r1, r2]\n                b        .L_loop2_0\n.L_loop2_0_done:\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Source/IAR/startup_ARMCM23.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM23.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM23 Device\n; * @version  V1.1.0\n; * @date     08. April 2021\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                #define __INITIAL_SP     sfe(CSTACK)\n                #define __STACK_LIMIT    sfb(CSTACK)\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                SECTION STACKSEAL:DATA:NOROOT(3)\n                #define __STACK_SEAL     sfb(STACKSEAL)\n                #endif\n\n                DATA\n\n__vector_table\n                DCD      __INITIAL_SP                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (214)                                ; Interrupts 10 .. 224 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                str      r1,[r0,#0]\n                str      r1,[r0,#4]\n                #endif\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nSVC_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Source/startup_ARMCM23.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM23.c\n * @brief    CMSIS-Core Device Startup File for a Cortex-M23 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM23/Source/system_ARMCM23.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM23.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM23 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM23)\n  #include \"ARMCM23.h\"\n#elif defined (ARMCM23_TZ)\n  #include \"ARMCM23_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM23.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Include/ARMCM3.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM3.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM3 Device\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM3_H\n#define ARMCM3_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 223 are left out */\n  Interrupt224_IRQn             =   224\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM3_REV                 0x0201U   /* Core revision r2p1 */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_cm3.h\"                       /* Processor and core peripherals */\n#include \"system_ARMCM3.h\"                  /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM3_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Include/system_ARMCM3.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM3.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM3 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM3_H\n#define SYSTEM_ARMCM3_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM3_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac5.sct",
    "content": "#! armcc -E\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/ARMCM3_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Source/ARM/startup_ARMCM3.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM3.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM3 Device\n; * @version  V1.0.1\n; * @date     23. July 2019\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nStack_Size      EQU      0x00000400\n\n                AREA     STACK, NOINIT, READWRITE, ALIGN=3\n__stack_limit\nStack_Mem       SPACE    Stack_Size\n__initial_sp\n\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nHeap_Size       EQU      0x00000C00\n\n                IF       Heap_Size != 0                      ; Heap is provided\n                AREA     HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE    Heap_Size\n__heap_limit\n                ENDIF\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n\n__Vectors       DCD      __initial_sp                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; Default exception/interrupt handler\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Source/GCC/startup_ARMCM3.S",
    "content": "/**************************************************************************//**\n * @file     startup_ARMCM3.S\n * @brief    CMSIS-Core(M) Device Startup File for Cortex-M3 Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv7-m\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __StackTop                         /*     Top of Stack */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVC Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (214 * 4)                          /* Interrupts 10 .. 224 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                ittt     ge\n                ldrge    r0, [r1, r3]\n                strge    r0, [r2, r3]\n                bge      .L_loop0_0\n\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                itt      ge\n                strge    r0, [r1, r2]\n                bge      .L_loop2_0\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Source/IAR/startup_ARMCM3.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM3.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM3 Device\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (214)                                ; Interrupts 10 .. 224 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK MemManage_Handler\n                PUBWEAK BusFault_Handler\n                PUBWEAK UsageFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK DebugMon_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nMemManage_Handler\nBusFault_Handler\nUsageFault_Handler\nSVC_Handler\nDebugMon_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Source/startup_ARMCM3.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM3.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M3 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM3)\n  #include \"ARMCM3.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM3/Source/system_ARMCM3.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM3.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM3 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMCM3.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM33.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM33 Device (configured for ARMCM33 without FPU, without DSP extension, without TrustZone)\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM33_H\n#define ARMCM33_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM33_REV                0x0000U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       0U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             0U        /* no FPU present */\n#define __DSP_PRESENT             0U        /* no DSP extension present */\n\n#include \"core_cm33.h\"                      /* Processor and core peripherals */\n#include \"system_ARMCM33.h\"                 /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM33_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM33_DSP_FP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM33 Device (configured for ARMCM33 with FPU, with DSP extension)\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM33_DSP_FP_H\n#define ARMCM33_DSP_FP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM33_REV                0x0000U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       0U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n\n#include \"core_cm33.h\"                      /* Processor and core peripherals */\n#include \"system_ARMCM33.h\"                 /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM33_DSP_FP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_DSP_FP_TZ.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM33_DSP_FP_TZ.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM33 Device (configured for ARMCM33 with FPU, with DSP extension, with TrustZone)\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM33_DSP_FP_TZ_H\n#define ARMCM33_DSP_FP_TZ_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM33_REV                0x0000U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n\n#include \"core_cm33.h\"                      /* Processor and core peripherals */\n#include \"system_ARMCM33.h\"                 /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM33_DSP_FP_TZ_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Include/ARMCM33_TZ.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM33_TZ.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM33 Device (configured for ARMCM33 without FPU, without DSP extension, with TrustZone)\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM33_TZ_H\n#define ARMCM33_TZ_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM33_REV                0x0000U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             0U        /* no FPU present */\n#define __DSP_PRESENT             0U        /* no DSP extension present */\n\n#include \"core_cm33.h\"                      /* Processor and core peripherals */\n#include \"system_ARMCM33.h\"                 /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM33_TZ_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Include/Template/partition_ARMCM33.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM33.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33\n * @version  V1.1.1\n * @date     12. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM33_H\n#define PARTITION_ARMCM33_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM33_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Include/system_ARMCM33.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM33 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM33_H\n#define SYSTEM_ARMCM33_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM33_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/ARMCM33_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Source/ARM/startup_ARMCM33.S",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.S\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.0.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.main\n\n                #define __INITIAL_SP     Image$$ARM_LIB_STACK$$ZI$$Limit\n                #define __STACK_LIMIT    Image$$ARM_LIB_STACK$$ZI$$Base\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     Image$$STACKSEAL$$ZI$$Base\n                #endif\n\n                .section RESET\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    SecureFault_Handler                /*  -9 Secure Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (470 * 4)                          /* Interrupts 10 .. 480 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                bl       SystemInit\n\n                bl       __main\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SecureFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Source/GCC/startup_ARMCM33.S",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.S\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.3.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.main\n\n                #define __INITIAL_SP     __StackTop\n                #define __STACK_LIMIT    __StackLimit\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     __StackSeal\n                #endif\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    SecureFault_Handler                /*  -9 Secure Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (470 * 4)                          /* Interrupts 10 .. 480 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                ittt     ge\n                ldrge    r0, [r1, r3]\n                strge    r0, [r2, r3]\n                bge      .L_loop0_0\n\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                itt      ge\n                strge    r0, [r1, r2]\n                bge      .L_loop2_0\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SecureFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Source/IAR/startup_ARMCM33.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM33.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM33 Device\n; * @version  V1.1.0\n; * @date     08. April 2021\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                #define __INITIAL_SP     sfe(CSTACK)\n                #define __STACK_LIMIT    sfb(CSTACK)\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                SECTION STACKSEAL:DATA:NOROOT(3)\n                #define __STACK_SEAL     sfb(STACKSEAL)\n                #endif\n\n                DATA\n\n__vector_table\n                DCD      __INITIAL_SP                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n__vector_table_0x1c\n                DCD      SecureFault_Handler                 ;  -9 Security Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (470)                                ; Interrupts 10 .. 480 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK MemManage_Handler\n                PUBWEAK BusFault_Handler\n                PUBWEAK UsageFault_Handler\n                PUBWEAK SecureFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK DebugMon_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nMemManage_Handler\nBusFault_Handler\nUsageFault_Handler\nSecureFault_Handler\nSVC_Handler\nDebugMon_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Source/startup_ARMCM33.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M33 Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVCall Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM33/Source/system_ARMCM33.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM33.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM33 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM33)\n  #include \"ARMCM33.h\"\n#elif defined (ARMCM33_TZ)\n  #include \"ARMCM33_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#elif defined (ARMCM33_DSP_FP)\n  #include \"ARMCM33_DSP_FP.h\"\n#elif defined (ARMCM33_DSP_FP_TZ)\n  #include \"ARMCM33_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM33.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM35P.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM35P Device (configured for ARMCM35P without FPU, without DSP extension, without TrustZone)\n * @version  V1.0.1\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM35P_H\n#define ARMCM35P_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM35P_REV               0x0000U   /* Core revision r0p0 */\n#define __SAUREGION_PRESENT       0U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             0U        /* no FPU present */\n#define __DSP_PRESENT             0U        /* no DSP extension present */\n\n#include \"core_cm35p.h\"                     /* Processor and core peripherals */\n#include \"system_ARMCM35P.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM35P_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM35P_DSP_FP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM35P Device (configured for ARMCM35P with FPU, with DSP extension)\n * @version  V1.0.1\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM35P_DSP_FP_H\n#define ARMCM35P_DSP_FP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM35P_REV               0x0000U   /* Core revision r0p0 */\n#define __SAUREGION_PRESENT       0U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n\n#include \"core_cm35p.h\"                     /* Processor and core peripherals */\n#include \"system_ARMCM35P.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM35P_DSP_FP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_DSP_FP_TZ.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM35P_DSP_FP_TZ.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM35P Device (configured for ARMCM35P with FPU, with DSP extension, with TrustZone)\n * @version  V1.0.1\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM35P_DSP_FP_TZ_H\n#define ARMCM35P_DSP_FP_TZ_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM35P_REV               0x0000U   /* Core revision r0p0 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n\n#include \"core_cm35p.h\"                     /* Processor and core peripherals */\n#include \"system_ARMCM35P.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM35P_DSP_FP_TZ_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Include/ARMCM35P_TZ.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM35P_TZ.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM35P Device (configured for ARMCM35P without FPU, without DSP extension, with TrustZone)\n * @version  V1.0.1\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM35P_TZ_H\n#define ARMCM35P_TZ_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM35P_REV               0x0000U   /* Core revision r0p0 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             0U        /* no FPU present */\n#define __DSP_PRESENT             0U        /* no DSP extension present */\n\n#include \"core_cm35p.h\"                     /* Processor and core peripherals */\n#include \"system_ARMCM35P.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM35P_TZ_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Include/Template/partition_ARMCM35P.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM35P.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM35P\n * @version  V1.0.0\n * @date     03. September 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM35P_H\n#define PARTITION_ARMCM35P_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM35P_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Include/system_ARMCM35P.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM35P.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM35P Device\n * @version  V1.0.2\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM35P_H\n#define SYSTEM_ARMCM35P_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM35P_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/ARMCM35P_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m35p -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Source/ARM/startup_ARMCM35P.S",
    "content": "/******************************************************************************\n * @file     startup_ARMCM33.S\n * @brief    CMSIS Core Device Startup File for Cortex-M33 Device\n * @version  V2.0.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.main\n\n                #define __INITIAL_SP     Image$$ARM_LIB_STACK$$ZI$$Limit\n                #define __STACK_LIMIT    Image$$ARM_LIB_STACK$$ZI$$Base\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     Image$$STACKSEAL$$ZI$$Base\n                #endif\n\n                .section RESET\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    SecureFault_Handler                /*  -9 Secure Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (470 * 4)                          /* Interrupts 10 .. 480 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                bl       SystemInit\n\n                bl       __main\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SecureFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Source/GCC/startup_ARMCM35P.S",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.S\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V1.3.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.main\n\n                #define __INITIAL_SP     __StackTop\n                #define __STACK_LIMIT    __StackLimit\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     __StackSeal\n                #endif\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    SecureFault_Handler                /*  -9 Secure Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (470 * 4)                          /* Interrupts 10 .. 480 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                ittt     ge\n                ldrge    r0, [r1, r3]\n                strge    r0, [r2, r3]\n                bge      .L_loop0_0\n\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                itt      ge\n                strge    r0, [r1, r2]\n                bge      .L_loop2_0\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SecureFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Source/IAR/startup_ARMCM35P.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM35P.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM35P Device\n; * @version  V2.1.0\n; * @date     08. April 2021\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                #define __INITIAL_SP     sfe(CSTACK)\n                #define __STACK_LIMIT    sfb(CSTACK)\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                SECTION STACKSEAL:DATA:NOROOT(3)\n                #define __STACK_SEAL     sfb(STACKSEAL)\n                #endif\n\n                DATA\n\n__vector_table\n                DCD      __INITIAL_SP                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n__vector_table_0x1c\n                DCD      SecureFault_Handler                 ;  -9 Security Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (470)                                ; Interrupts 10 .. 480 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK MemManage_Handler\n                PUBWEAK BusFault_Handler\n                PUBWEAK UsageFault_Handler\n                PUBWEAK SecureFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK DebugMon_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nMemManage_Handler\nBusFault_Handler\nUsageFault_Handler\nSecureFault_Handler\nSVC_Handler\nDebugMon_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Source/startup_ARMCM35P.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM35P.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M35P Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM35P/Source/system_ARMCM35P.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM35P.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM35P Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM35P)\n  #include \"ARMCM35P.h\"\n#elif defined (ARMCM35P_TZ)\n  #include \"ARMCM35P_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#elif defined (ARMCM35P_DSP_FP)\n  #include \"ARMCM35P_DSP_FP.h\"\n#elif defined (ARMCM35P_DSP_FP_TZ)\n  #include \"ARMCM35P_DSP_FP_TZ.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM35P.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Include/ARMCM4.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM4.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM4 Device (configured for CM4 without FPU)\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM4_H\n#define ARMCM4_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 223 are left out */\n  Interrupt224_IRQn             =   224\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM4_REV                 0x0001U   /* Core revision r0p1 */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             0U        /* no FPU present */\n\n#include \"core_cm4.h\"                       /* Processor and core peripherals */\n#include \"system_ARMCM4.h\"                  /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM4_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Include/ARMCM4_FP.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM4_FP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM4 Device (configured for CM4 with FPU)\n * @version  V5.3.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM4_FP_H\n#define ARMCM4_FP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 223 are left out */\n  Interrupt224_IRQn             =   224\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM4_REV                 0x0001U   /* Core revision r0p1 */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n\n#include \"core_cm4.h\"                       /* Processor and core peripherals */\n#include \"system_ARMCM4.h\"                  /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM4_FP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Include/system_ARMCM4.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM4.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM4 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM4_H\n#define SYSTEM_ARMCM4_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM4_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac5.sct",
    "content": "#! armcc -E\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/ARMCM4_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Source/ARM/startup_ARMCM4.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM4.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM4 Device\n; * @version  V1.0.1\n; * @date     23. July 2019\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nStack_Size      EQU      0x00000400\n\n                AREA     STACK, NOINIT, READWRITE, ALIGN=3\n__stack_limit\nStack_Mem       SPACE    Stack_Size\n__initial_sp\n\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nHeap_Size       EQU      0x00000C00\n\n                IF       Heap_Size != 0                      ; Heap is provided\n                AREA     HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE    Heap_Size\n__heap_limit\n                ENDIF\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n\n__Vectors       DCD      __initial_sp                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; Default exception/interrupt handler\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Source/GCC/startup_ARMCM4.S",
    "content": "/**************************************************************************//**\n * @file     startup_ARMCM4.S\n * @brief    CMSIS-Core(M) Device Startup File for Cortex-M4 Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv7e-m\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __StackTop                         /*     Top of Stack */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVC Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (214 * 4)                          /* Interrupts 10 .. 224 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                ittt     ge\n                ldrge    r0, [r1, r3]\n                strge    r0, [r2, r3]\n                bge      .L_loop0_0\n\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                itt      ge\n                strge    r0, [r1, r2]\n                bge      .L_loop2_0\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Source/IAR/startup_ARMCM4.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM4.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM4 Device\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (214)                                ; Interrupts 10 .. 224 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK MemManage_Handler\n                PUBWEAK BusFault_Handler\n                PUBWEAK UsageFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK DebugMon_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nMemManage_Handler\nBusFault_Handler\nUsageFault_Handler\nSVC_Handler\nDebugMon_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Source/startup_ARMCM4.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM4.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M4 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM4)\n  #include \"ARMCM4.h\"\n#elif defined (ARMCM4_FP)\n  #include \"ARMCM4_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM4/Source/system_ARMCM4.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM4.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM4 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM4)\n  #include \"ARMCM4.h\"\n#elif defined (ARMCM4_FP)\n  #include \"ARMCM4_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM55/Include/ARMCM55.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM55.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM55 Device Series (configured for ARMCM55 with double precision FPU,\n *                                  DSP extension, MVE, TrustZone)\n * @version  V1.0.1\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM55_H\n#define ARMCM55_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM55_REV                0x0001U   /* Core revision r0p1 */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __FPU_DP                  1U        /* double precision FPU */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __PMU_PRESENT             1U        /* PMU present */\n#define __PMU_NUM_EVENTCNT        8U        /* PMU Event Counters */\n#define __ICACHE_PRESENT          1U        /* Instruction Cache present */\n#define __DCACHE_PRESENT          1U        /* Data Cache present */\n\n#include \"core_cm55.h\"                      /* Processor and core peripherals */\n#include \"system_ARMCM55.h\"                 /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM55_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM55/Include/Template/partition_ARMCM55.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM55.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.0\n * @date     20. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM55_H\n#define PARTITION_ARMCM55_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM55_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM55/Include/system_ARMCM55.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM55.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM55 Device\n * @version  V1.0.1\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2020-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM55_H\n#define SYSTEM_ARMCM55_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM55_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM55/Source/ARM/ARMCM55_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM55/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM55/Source/startup_ARMCM55.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM55.c\n * @brief    CMSIS-Core Device Startup File for Cortex-M55 Device\n * @version  V1.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM55/Source/system_ARMCM55.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM55.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM55 Device\n * @version  V1.1.0\n * @date     28. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM55)\n  #include \"ARMCM55.h\"\n#else\n  #error device not specified!\n#endif\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM55.h\"\n  #endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            ( 5000000UL)      /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (5U * XTAL)\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Set low-power state for PDEPU                */\n  /*  0b00  | ON, PDEPU is not in low-power state */\n  /*  0b01  | ON, but the clock is off            */\n  /*  0b10  | RET(ention)                         */\n  /*  0b11  | OFF                                 */\n\n  /* Clear ELPSTATE, value is 0b11 on Cold reset */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk);\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM7.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM7 Device (configured for CM7 without FPU)\n * @version  V5.3.3\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM7_H\n#define ARMCM7_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 223 are left out */\n  Interrupt224_IRQn             =   224\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM7_REV                 0x0000U   /* Core revision r0p0 */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             0U        /* no FPU present */\n#define __FPU_DP                  0U        /* unused */\n#define __ICACHE_PRESENT          1U        /* Instruction Cache present */\n#define __DCACHE_PRESENT          1U        /* Data Cache present */\n#define __DTCM_PRESENT            1U        /* Data Tightly Coupled Memory present */\n\n#include \"core_cm7.h\"                       /* Processor and core peripherals */\n#include \"system_ARMCM7.h\"                  /* System Header */\n\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM7_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_DP.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM7_DP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM7 Device (configured for CM7 with double precision FPU)\n * @version  V5.3.3\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM7_DP_H\n#define ARMCM7_DP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 223 are left out */\n  Interrupt224_IRQn             =   224\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM7_REV                 0x0000U   /* Core revision r0p0 */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __FPU_DP                  1U        /* double precision FPU */\n#define __ICACHE_PRESENT          1U        /* Instruction Cache present */\n#define __DCACHE_PRESENT          1U        /* Data Cache present */\n#define __DTCM_PRESENT            1U        /* Data Tightly Coupled Memory present */\n\n#include \"core_cm7.h\"                       /* Processor and core peripherals */\n#include \"system_ARMCM7.h\"                  /* System Header */\n\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM7_DP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Include/ARMCM7_SP.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM7_SP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMCM7 Device (configured for CM7 with single precision FPU)\n * @version  V5.3.3\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM7_SP_H\n#define ARMCM7_SP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 223 are left out */\n  Interrupt224_IRQn             =   224\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM7_REV                 0x0000U   /* Core revision r0p0 */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __FPU_DP                  0U        /* single precision FPU */\n#define __ICACHE_PRESENT          1U        /* Instruction Cache present */\n#define __DCACHE_PRESENT          1U        /* Data Cache present */\n#define __DTCM_PRESENT            1U        /* Data Tightly Coupled Memory present */\n\n#include \"core_cm7.h\"                       /* Processor and core peripherals */\n#include \"system_ARMCM7.h\"                  /* System Header */\n\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM7_SP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Include/system_ARMCM7.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM7.h\n * @brief    CMSIS Device System Header File for\n *           ARMCM7 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM7_H\n#define SYSTEM_ARMCM7_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM7_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac5.sct",
    "content": "#! armcc -E\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/ARMCM7_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Source/ARM/startup_ARMCM7.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM7.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM7 Device\n; * @version  V1.0.1\n; * @date     23. July 2019\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nStack_Size      EQU      0x00000400\n\n                AREA     STACK, NOINIT, READWRITE, ALIGN=3\n__stack_limit\nStack_Mem       SPACE    Stack_Size\n__initial_sp\n\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nHeap_Size       EQU      0x00000C00\n\n                IF       Heap_Size != 0                      ; Heap is provided\n                AREA     HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE    Heap_Size\n__heap_limit\n                ENDIF\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n\n__Vectors       DCD      __initial_sp                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; Default exception/interrupt handler\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Source/GCC/startup_ARMCM7.S",
    "content": "/**************************************************************************//**\n * @file     startup_ARMCM7.S\n * @brief    CMSIS-Core(M) Device Startup File for Cortex-M7 Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv7e-m\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __StackTop                         /*     Top of Stack */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVC Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (214 * 4)                          /* Interrupts 10 .. 224 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                ittt     ge\n                ldrge    r0, [r1, r3]\n                strge    r0, [r2, r3]\n                bge      .L_loop0_0\n\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                itt      ge\n                strge    r0, [r1, r2]\n                bge      .L_loop2_0\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Source/IAR/startup_ARMCM7.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMCM7.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMCM7 Device\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (214)                                ; Interrupts 10 .. 224 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK MemManage_Handler\n                PUBWEAK BusFault_Handler\n                PUBWEAK UsageFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK DebugMon_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nMemManage_Handler\nBusFault_Handler\nUsageFault_Handler\nSVC_Handler\nDebugMon_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Source/startup_ARMCM7.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM7.c\n * @brief    CMSIS-Core(M) Device Startup File for a Cortex-M7 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM7/Source/system_ARMCM7.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM7.c\n * @brief    CMSIS Device System Source File for\n *           ARMCM7 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM7)\n  #include \"ARMCM7.h\"\n#elif defined (ARMCM7_SP)\n  #include \"ARMCM7_SP.h\"\n#elif defined (ARMCM7_DP)\n  #include \"ARMCM7_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM85/Include/ARMCM85.h",
    "content": "/**************************************************************************//**\n * @file     ARMCM85.h\n * @brief    CMSIS Device Header File for ARMCM85 Device\n *           (double precision FPU, DSP extension, MVE, TrustZone)\n * @version  V1.0.2\n * @date     01. May 2023\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMCM85_H\n#define ARMCM85_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9,\n  /* Interrupts 10 .. 479 are left out */\n  Interrupt480_IRQn             =   480\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __CM85_REV                0x0001U   /* Core revision r0p1 */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __FPU_DP                  1U        /* double precision FPU */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __PMU_PRESENT             1U        /* PMU present */\n#define __PMU_NUM_EVENTCNT        8U        /* PMU Event Counters */\n#define __ICACHE_PRESENT          1U        /* Instruction Cache present */\n#define __DCACHE_PRESENT          1U        /* Data Cache present */\n\n#include \"core_cm85.h\"                      /* Processor and core peripherals */\n#include \"system_ARMCM85.h\"                 /* System Header */\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMCM85_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM85/Include/Template/partition_ARMCM85.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMCM85.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.0\n * @date     07. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMCM85_H\n#define PARTITION_ARMCM85_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR0     \"NSC code\"   /* description SAU region 0 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR1     \"NS code\"   /* description SAU region 1 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR2     \"NS data\"   /* description SAU region 2 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR3     \"NS peripherals\"   /* description SAU region 3 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR4     \"SAU region 4\"   /* description SAU region 4 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR5     \"SAU region 5\"   /* description SAU region 5 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR6     \"SAU region 6\"   /* description SAU region 6 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <s>Description\n*/\n#define SAU_INIT_DSCR7     \"SAU region 7\"   /* description SAU region 7 */\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMCM85_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM85/Include/system_ARMCM85.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM85.h\n * @brief    CMSIS Device System Header File for ARMCM85 Device\n * @version  V1.0.1\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMCM85_H\n#define SYSTEM_ARMCM85_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMCM85_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0> CMSE VeneerBase Address     <0x0-0xFFFFFFFF:8>\n;     <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)\n;   <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_BASE    0xFFFFFFFF\n#define __CMSEVENEER_SIZE    0x00000400\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#else\n#define __CV_BASE          ( __CMSEVENEER_BASE )\n#endif\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM85/Source/ARM/ARMCM85_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m85 -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000400\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0> CMSE VeneerBase Address     <0x0-0xFFFFFFFF:8>\n;     <i> 0xFFFFFFFF: Place Veneers at the end of Flash (default)\n;   <o1> CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_BASE    0xFFFFFFFF\n#define __CMSEVENEER_SIZE    0x00000400\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#if defined (__CMSEVENEER_BASE) && (__CMSEVENEER_BASE == 0xFFFFFFFF)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#else\n#define __CV_BASE          ( __CMSEVENEER_BASE )\n#endif\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_NOINIT __RW_BASE UNINIT __RW_SIZE {\n    *(.bss.noinit)\n  }\n\n  RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {\n    *(+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM85/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM85/Source/startup_ARMCM85.c",
    "content": "/******************************************************************************\n * @file     startup_ARMCM85.c\n * @brief    CMSIS Device Startup File for ARMCM85 Device\n * @version  V1.0.0\n * @date     07. February 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMCM85/Source/system_ARMCM85.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMCM85.c\n * @brief    CMSIS Device System Source File for ARMCM85 Device\n * @version  V1.0.0\n * @date     30. March 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMCM85)\n  #include \"ARMCM85.h\"\n\n  #if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n    #include \"partition_ARMCM85.h\"\n  #endif\n#else\n  #error device not specified!\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n  /* Set CPDLPSTATE.RLPSTATE to 0\n     Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state.\n     Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */\n  PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk |\n                             PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk  );\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n\n  /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */\n  /* PDEPU ON, Clock OFF */\n  PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  /* Enable Loop and branch info cache */\n  SCB->CCR |= SCB_CCR_LOB_Msk;\n\n  /* Enable Branch Prediction */\n  SCB->CCR |= SCB_CCR_BP_Msk;\n\n  __DSB();\n  __ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Include/ARMSC000.h",
    "content": "/**************************************************************************//**\n * @file     ARMSC000.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMSC000 Device\n * @version  V5.3.2\n * @date     10. Jan 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMSC000_H\n#define ARMSC000_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n\n\n\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n\n  PendSV_IRQn                   =  -2,     /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 31 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __SC000_REV               0x0000U   /* Core revision r0p0 */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            0U        /* no VTOR present*/\n#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_sc000.h\"                     /* Processor and core peripherals */\n#include \"system_ARMSC000.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMSC000_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Include/system_ARMSC000.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMSC000.h\n * @brief    CMSIS Device System Header File for\n *           ARMSC000 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMSC000_H\n#define SYSTEM_ARMSC000_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMSC000_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac5.sct",
    "content": "#! armcc -E\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/ARMSC000_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=sc000 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Source/ARM/startup_ARMSC000.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMSC000.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMSC000 Device\n; * @version  V1.0.1\n; * @date     23. July 2019\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nStack_Size      EQU      0x00000400\n\n                AREA     STACK, NOINIT, READWRITE, ALIGN=3\n__stack_limit\nStack_Mem       SPACE    Stack_Size\n__initial_sp\n\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nHeap_Size       EQU      0x00000C00\n\n                IF       Heap_Size != 0                      ; Heap is provided\n                AREA     HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE    Heap_Size\n__heap_limit\n                ENDIF\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n\n__Vectors       DCD      __initial_sp                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                SPACE    ( 22 * 4)                           ; Interrupts 10 .. 31 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; Default exception/interrupt handler\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Source/GCC/startup_ARMSC000.S",
    "content": "/**************************************************************************//**\n * @file     startup_ARMSC000.S\n * @brief    CMSIS-Core(M) Device Startup File for SC000 Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv6-m\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __StackTop                         /*     Top of Stack */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVC Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   ( 22 * 4)                          /* Interrupts 10 .. 31 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                blt      .L_loop0_0_done\n                ldr      r0, [r1, r3]\n                str      r0, [r2, r3]\n                b        .L_loop0_0\n\n.L_loop0_0_done:\n                adds     r4, #12\n                b        .L_loop0\n\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                blt      .L_loop2_0_done\n                str      r0, [r1, r2]\n                b        .L_loop2_0\n.L_loop2_0_done:\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Source/IAR/startup_ARMSC000.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMSC000.s\n; * @brief    CMSIS Core Device Startup File for\n; *           for ARMSC000 Device\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    ( 22)                                ; Interrupts 10 .. 31 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nSVC_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Source/startup_ARMSC000.c",
    "content": "/******************************************************************************\n * @file     startup_ARMSC000.c\n * @brief    CMSIS-Core(M) Device Startup File for a SC000 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMSC000)\n  #include \"ARMSC000.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[48];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10..31 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC000/Source/system_ARMSC000.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMSC000.c\n * @brief    CMSIS Device System Source File for\n *           for ARMSC000 Device\n * @version  V1.0.0\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMSC000.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Include/ARMSC300.h",
    "content": "/**************************************************************************//**\n * @file     ARMSC300.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMSC300 Device\n * @version  V5.3.2\n * @date     10. Jan 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMSC300_H\n#define ARMSC300_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 224 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __SC300_REV               0x0000U   /* Core revision r0p0 */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_sc300.h\"                     /* Processor and core peripherals */\n#include \"system_ARMSC300.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMSC300_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Include/system_ARMSC300.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMSC300.h\n * @brief    CMSIS Device System Header File for\n *           ARMSC300 Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMSC300_H\n#define SYSTEM_ARMSC300_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMSC300_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac5.sct",
    "content": "#! armcc -E\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/ARMSC300_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=sc300 -xc\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Scatter File Definitions definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE       __ROM_BASE\n#define __RO_SIZE       __ROM_SIZE\n\n#define __RW_BASE       __RAM_BASE\n#define __RW_SIZE      (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE)\n\n\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Source/ARM/startup_ARMSC300.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMSC300.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMSC300 Device\n; * @version  V1.0.1\n; * @date     23. July 2019\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nStack_Size      EQU      0x00000400\n\n                AREA     STACK, NOINIT, READWRITE, ALIGN=3\n__stack_limit\nStack_Mem       SPACE    Stack_Size\n__initial_sp\n\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nHeap_Size       EQU      0x00000C00\n\n                IF       Heap_Size != 0                      ; Heap is provided\n                AREA     HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE    Heap_Size\n__heap_limit\n                ENDIF\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n\n__Vectors       DCD      __initial_sp                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                SPACE    (214 * 4)                           ; Interrupts 10 .. 224 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; Default exception/interrupt handler\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.1.0\n * @date     04. August 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned \n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Source/GCC/startup_ARMSC300.S",
    "content": "/**************************************************************************//**\n * @file     startup_ARMSC300.S\n * @brief    CMSIS-Core(M) Device Startup File for SC300 Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv7-m\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __StackTop                         /*     Top of Stack */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVC Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (214 * 4)                          /* Interrupts 10 .. 224 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                ittt     ge\n                ldrge    r0, [r1, r3]\n                strge    r0, [r2, r3]\n                bge      .L_loop0_0\n\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                itt      ge\n                strge    r0, [r1, r2]\n                bge      .L_loop2_0\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Source/IAR/startup_ARMSC300.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMSC300.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMSC300 Device\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (214)                                ; Interrupts 10 .. 224 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK MemManage_Handler\n                PUBWEAK BusFault_Handler\n                PUBWEAK UsageFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK DebugMon_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nMemManage_Handler\nBusFault_Handler\nUsageFault_Handler\nSVC_Handler\nDebugMon_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Source/startup_ARMSC300.c",
    "content": "/******************************************************************************\n * @file     startup_ARMSC300.c\n * @brief    CMSIS-Core(M) Device Startup File for a SC300 Device\n * @version  V2.0.3\n * @date     31. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMSC300)\n  #include \"ARMSC300.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMSC300/Source/system_ARMSC300.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMSC300.c\n * @brief    CMSIS Device System Source File for\n *           ARMSC300 Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMSC300.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]);\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv81MML/Include/ARMv81MML_DSP_DP_MVE_FP.h",
    "content": "/**************************************************************************//**\n * @file     ARMv81MML_DSP_DP_MVE_FP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           Armv8.1-M Mainline Device Series (configured for Armv8.1-M Mainline with double precision FPU, with DSP extension, with TrustZone)\n * @version  V1.1.0\n * @date     27. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMv81MML_DSP_DP_MVE_FP_H\n#define ARMv81MML_DSP_DP_MVE_FP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* --------------------  Armv8.1-M Mainline Processor Exceptions Numbers  --------- */\n  NonMaskableInt_IRQn           = -14,      /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,      /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,      /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,      /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,      /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,      /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,      /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,      /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,      /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,      /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 480 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n/* ---  Configuration of the Armv8.1-M Mainline Processor and Core Peripherals  --- */\n#define __ARMv81MML_REV           0x0001U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __PMU_PRESENT             1U        /* PMU present */\n#define __PMU_NUM_EVENTCNT        31U       /* Number of PMU event counters */  \n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __FPU_DP                  1U        /* double precision FPU */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n#define __ICACHE_PRESENT          1U        /* Instruction Cache present */\n#define __DCACHE_PRESENT          1U        /* Data Cache present */\n\n#include \"core_armv81mml.h\"                 /* Processor and core peripherals */\n#include \"system_ARMv81MML.h\"               /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMv81MML_DSP_DP_MVE_FP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv81MML/Include/Template/partition_ARMv81MML.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMv81MML.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8.1-M Mainline\n * @version  V1.0.1\n * @date     26. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMv81MML_H\n#define PARTITION_ARMv81MML_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMv81MML_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv81MML/Include/system_ARMv81MML.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMv81MML.h\n * @brief    CMSIS Device System Header File for\n *           Armv8.1-M Mainline Device Series\n * @version  V1.0.2\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMv81MML_H\n#define SYSTEM_ARMv81MML_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMv81MML_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -march=armv8.1-m.main -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -march=armv8.1-m.main -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv81MML/Source/ARM/ARMv81MML_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -march=armv8.1-m.main -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -march=armv8.1-m.main -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv81MML/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv81MML/Source/startup_ARMv81MML.c",
    "content": "/******************************************************************************\n * @file     startup_ARMv81MML.c\n * @brief    CMSIS-Core Device Startup File for ARMv81MML Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMv81MML_DSP_DP_MVE_FP)\n  #include \"ARMv81MML_DSP_DP_MVE_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv81MML/Source/system_ARMv81MML.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMv81MML.c\n * @brief    CMSIS Device System Source File for\n *           Armv8.1-M Mainline Device Series\n * @version  V1.2.1\n * @date     27. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMv81MML_DSP_DP_MVE_FP)\n  #include \"ARMv81MML_DSP_DP_MVE_FP.h\"\n#else\n  #error device not specified!\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n  #include \"partition_ARMv81MML.h\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            ( 5000000UL)      /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (5U * XTAL)\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n// Enable Loop and branch info cache\nSCB->CCR |= SCB_CCR_LOB_Msk;\n__ISB();\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Include/ARMv8MBL.h",
    "content": "/**************************************************************************//**\n * @file     ARMv8MBL.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMv8MBL Device\n * @version  V5.3.1\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMv8MBL_H\n#define ARMv8MBL_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n\n\n\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n\n  PendSV_IRQn                   =  -2,     /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 480 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __ARMv8MBL_REV            0x0000U   /* Core revision r0p0 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions are present */\n#define __MPU_PRESENT             0U        /* no MPU present */\n#define __VTOR_PRESENT            0U        /* no VTOR present */\n#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n\n#include \"core_armv8mbl.h\"                  /* Processor and core peripherals */\n#include \"system_ARMv8MBL.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMv8MBL_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Include/Template/partition_ARMv8MBL.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMv8MBL.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMv8MBL\n * @version  V1.0.0\n * @date     09. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMv8MBL_H\n#define PARTITION_ARMv8MBL_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n\n/*\n// <e>Setup behaviour of single SysTick\n*/\n#define SCB_ICSR_INIT 0\n\n/*\n//   <o> in a single SysTick implementation, SysTick is\n//     <0=>Secure\n//     <1=>Non-Secure\n//   <i> Value for SCB->ICSR register bit STTNS\n//   <i> only for single SysTick implementation \n*/\n#define SCB_ICSR_STTNS_VAL  0\n\n/*\n// </e>\n*/\n\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk |  SCB_AIRCR_PRIS_Msk)        )                     |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)\n    SCB->ICSR  = (SCB->ICSR  & ~(SCB_ICSR_STTNS_Msk        )) |\n                   ((SCB_ICSR_STTNS_VAL         << SCB_ICSR_STTNS_Pos)         & SCB_ICSR_STTNS_Msk);\n  #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMv8MBL_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Include/system_ARMv8MBL.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMv8MBL.h\n * @brief    CMSIS Device System Header File for\n *           ARMv8MBL Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMv8MBL_H\n#define SYSTEM_ARMv8MBL_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMv8MBL_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.base -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -march=armv8-m.base -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/ARMv8MBL_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.base -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -march=armv8-m.base -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Source/ARM/startup_ARMv8MBL.S",
    "content": "/******************************************************************************\n * @file     startup_ARMv8MBL.S\n * @brief    CMSIS-Core Device Startup File for ARMv8MBL Device\n * @version  V2.0.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.base\n\n                #define __INITIAL_SP     Image$$ARM_LIB_STACK$$ZI$$Limit\n                #define __STACK_LIMIT    Image$$ARM_LIB_STACK$$ZI$$Base\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     Image$$STACKSEAL$$ZI$$Base\n                #endif\n\n                .section RESET\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVC Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (214 * 4)                          /* Interrupts 10 .. 224 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                str      r1,[r0,#0]\n                str      r1,[r0,#4]\n                #endif\n\n                bl       SystemInit\n\n                bl       __main\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Source/GCC/startup_ARMv8MBL.S",
    "content": "/******************************************************************************\n * @file     startup_ARMv8MBL.S\n * @brief    CMSIS-Core Device Startup File for ARMv8MBL Device\n * @version  V2.2.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.base\n\n                #define __INITIAL_SP     __StackTop\n                #define __STACK_LIMIT    __StackLimit\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     __StackSeal\n                #endif\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVC Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (214 * 4)                          /* Interrupts 10 .. 224 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                str      r1,[r0,#0]\n                str      r1,[r0,#4]\n                #endif\n\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                blt      .L_loop0_0_done\n                ldr      r0, [r1, r3]\n                str      r0, [r2, r3]\n                b        .L_loop0_0\n\n.L_loop0_0_done:\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                blt      .L_loop2_0_done\n                str      r0, [r1, r2]\n                b        .L_loop2_0\n.L_loop2_0_done:\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Source/IAR/startup_ARMv8MBL.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMv8MBL.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMv8MBL Device\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (470)                                ; Interrupts 10 .. 480 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nSVC_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Source/startup_ARMv8MBL.c",
    "content": "/******************************************************************************\n * @file     startup_ARMv8MBL.c\n * @brief    CMSIS-Core Device Startup File for a ARMv8MBL Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMv8MBL)\n  #include \"ARMv8MBL.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 223 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MBL/Source/system_ARMv8MBL.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMv8MBL.c\n * @brief    CMSIS Device System Source File for\n *           ARMv8MBL Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"ARMv8MBL.h\"\n\n#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n  #include \"partition_ARMv8MBL.h\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[240];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__Vectors[0]);\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML.h",
    "content": "/**************************************************************************//**\n * @file     ARMv8MML.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMv8MML Device (configured for ARMv8MML without FPU, without DSP extension, with TrustZone)\n * @version  V5.4.0\n * @date     03. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMv8MML_H\n#define ARMv8MML_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 480 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __ARMv8MML_REV            0x0001U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             0U        /* no FPU present */\n#define __DSP_PRESENT             0U        /* no DSP extension present */\n#define __ICACHE_PRESENT          1U\n#define __DCACHE_PRESENT          1U\n\n#include \"core_armv8mml.h\"                  /* Processor and core peripherals */\n#include \"system_ARMv8MML.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMv8MML_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DP.h",
    "content": "/**************************************************************************//**\n * @file     ARMv8MML_DP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMv8MML Device (configured for ARMv8MML with double precision FPU, without DSP extension, with TrustZone)\n * @version  V5.4.0\n * @date     03. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMv8MML_DP_H\n#define ARMv8MML_DP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 480 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __ARMv8MML_REV            0x0001U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __FPU_DP                  1U        /* double precision FPU */\n#define __DSP_PRESENT             0U        /* no DSP extension present */\n#define __ICACHE_PRESENT          1U\n#define __DCACHE_PRESENT          1U\n\n#include \"core_armv8mml.h\"                  /* Processor and core peripherals */\n#include \"system_ARMv8MML.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMv8MML_DP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP.h",
    "content": "/**************************************************************************//**\n * @file     ARMv8MML_DSP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMv8MML Mainline Device (configured for ARMv8MML without FPU, with DSP extension, with TrustZone)\n * @version  V5.4.0\n * @date     03. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMv8MML_DSP_H\n#define ARMv8MML_DSP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 480 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __ARMv8MML_REV            0x0001U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             0U        /* no FPU present */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n#define __ICACHE_PRESENT          1U\n#define __DCACHE_PRESENT          1U\n\n#include \"core_armv8mml.h\"                  /* Processor and core peripherals */\n#include \"system_ARMv8MML.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMv8MML_DSP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_DP.h",
    "content": "/**************************************************************************//**\n * @file     ARMv8MML_DSP_DP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMv8MML Mainline Device (configured for Armv8-M MainlineARMv8MML\n * @version  V5.4.0\n * @date     03. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMv8MML_DSP_DP_H\n#define ARMv8MML_DSP_DP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 480 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __ARMv8MML_REV            0x0001U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __FPU_DP                  1U        /* double precision FPU */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n#define __ICACHE_PRESENT          1U\n#define __DCACHE_PRESENT          1U\n\n#include \"core_armv8mml.h\"                  /* Processor and core peripherals */\n#include \"system_ARMv8MML.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMv8MML_DSP_DP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_DSP_SP.h",
    "content": "/**************************************************************************//**\n * @file     ARMv8MML_DSP_SP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMv8MML Mainline Device (configured for ARMv8MML with single precision FPU, with DSP extension, with TrustZone)\n * @version  V5.4.0\n * @date     03. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMv8MML_DSP_SP_H\n#define ARMv8MML_DSP_SP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 480 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __ARMv8MML_REV            0x0001U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __FPU_DP                  0U        /* single precision FPU */\n#define __DSP_PRESENT             1U        /* DSP extension present */\n#define __ICACHE_PRESENT          1U\n#define __DCACHE_PRESENT          1U\n\n#include \"core_armv8mml.h\"                  /* Processor and core peripherals */\n#include \"system_ARMv8MML.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMv8MML_DSP_SP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Include/ARMv8MML_SP.h",
    "content": "/**************************************************************************//**\n * @file     ARMv8MML_SP.h\n * @brief    CMSIS Core Peripheral Access Layer Header File for\n *           ARMv8MML Device (configured for ARMv8MML with single precision FPU, without DSP extension, with TrustZone)\n * @version  V5.4.0\n * @date     03. March 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef ARMv8MML_SP_H\n#define ARMv8MML_SP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* -------------------------  Interrupt Number Definition  ------------------------ */\n\ntypedef enum IRQn\n{\n/* -------------------  Processor Exceptions Numbers  ----------------------------- */\n  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */\n  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */\n  MemoryManagement_IRQn         = -12,     /*  4 Memory Management Interrupt */\n  BusFault_IRQn                 = -11,     /*  5 Bus Fault Interrupt */\n  UsageFault_IRQn               = -10,     /*  6 Usage Fault Interrupt */\n  SecureFault_IRQn              =  -9,     /*  7 Secure Fault Interrupt */\n  SVCall_IRQn                   =  -5,     /* 11 SVC Interrupt */\n  DebugMonitor_IRQn             =  -4,     /* 12 Debug Monitor Interrupt */\n  PendSV_IRQn                   =  -2,     /* 14 PendSV Interrupt */\n  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */\n\n/* -------------------  Processor Interrupt Numbers  ------------------------------ */\n  Interrupt0_IRQn               =   0,\n  Interrupt1_IRQn               =   1,\n  Interrupt2_IRQn               =   2,\n  Interrupt3_IRQn               =   3,\n  Interrupt4_IRQn               =   4,\n  Interrupt5_IRQn               =   5,\n  Interrupt6_IRQn               =   6,\n  Interrupt7_IRQn               =   7,\n  Interrupt8_IRQn               =   8,\n  Interrupt9_IRQn               =   9\n  /* Interrupts 10 .. 480 are left out */\n} IRQn_Type;\n\n\n/* ================================================================================ */\n/* ================      Processor and Core Peripheral Section     ================ */\n/* ================================================================================ */\n\n/* -------  Start of section using anonymous unions and disabling warnings  ------- */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* --------  Configuration of Core Peripherals  ----------------------------------- */\n#define __ARMv8MML_REV            0x0001U   /* Core revision r0p1 */\n#define __SAUREGION_PRESENT       1U        /* SAU regions present */\n#define __MPU_PRESENT             1U        /* MPU present */\n#define __VTOR_PRESENT            1U        /* VTOR present */\n#define __NVIC_PRIO_BITS          3U        /* Number of Bits used for Priority Levels */\n#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */\n#define __FPU_PRESENT             1U        /* FPU present */\n#define __FPU_DP                  0U        /* single precision FPU */\n#define __DSP_PRESENT             0U        /* no DSP extension present */\n#define __ICACHE_PRESENT          1U\n#define __DCACHE_PRESENT          1U\n\n#include \"core_armv8mml.h\"                  /* Processor and core peripherals */\n#include \"system_ARMv8MML.h\"                /* System Header */\n\n\n/* --------  End of section using anonymous unions and disabling warnings  -------- */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* ARMv8MML_SP_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Include/Template/partition_ARMv8MML.h",
    "content": "/**************************************************************************//**\n * @file     partition_ARMv8MML.h\n * @brief    CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for Armv8-M Mainline\n * @version  V1.1.1\n * @date     18. March 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_ARMv8MML_H\n#define PARTITION_ARMv8MML_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point Unit\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if defined (__FPU_USED) && (__FPU_USED == 1U) && \\\n      defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_ARMv8MML_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Include/system_ARMv8MML.h",
    "content": "/**************************************************************************//**\n * @file     system_ARMv8MML.h\n * @brief    CMSIS Device System Header File for\n *           ARMv8MML Device\n * @version  V5.3.3\n * @date     11. July 2022\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_ARMv8MML_H\n#define SYSTEM_ARMv8MML_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_ARMv8MML_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.main -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -march=armv8-m.main -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/ARMv8MML_ac6_s.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -march=armv8-m.main -xc -mcmse\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -march=armv8-m.main -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Source/ARM/startup_ARMv8MML.S",
    "content": "/******************************************************************************\n * @file     startup_ARMv8MML.S\n * @brief    CMSIS-Core Device Startup File for Cortex-ARMv8MML Device\n * @version  V2.0.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.main\n\n                #define __INITIAL_SP     Image$$ARM_LIB_STACK$$ZI$$Limit\n                #define __STACK_LIMIT    Image$$ARM_LIB_STACK$$ZI$$Base\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     Image$$STACKSEAL$$ZI$$Base\n                #endif\n\n                .section RESET\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    SecureFault_Handler                /*  -9 Secure Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVC Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (470 * 4)                          /* Interrupts 10 .. 480 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                bl       SystemInit\n\n                bl       __main\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SecureFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n  \n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Source/GCC/startup_ARMv8MML.S",
    "content": "/******************************************************************************\n * @file     startup_ARMv8MML.S\n * @brief    CMSIS-Core Device Startup File for ARMv8MML evice\n * @version  V2.3.0\n * @date     26. May 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n                .arch    armv8-m.main\n\n                #define __INITIAL_SP     __StackTop\n                #define __STACK_LIMIT    __StackLimit\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     __StackSeal\n                #endif\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    SecureFault_Handler                /*  -9 Secure Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVC Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n                /* Interrupts */\n                .long    Interrupt0_Handler                 /*   0 Interrupt 0 */\n                .long    Interrupt1_Handler                 /*   1 Interrupt 1 */\n                .long    Interrupt2_Handler                 /*   2 Interrupt 2 */\n                .long    Interrupt3_Handler                 /*   3 Interrupt 3 */\n                .long    Interrupt4_Handler                 /*   4 Interrupt 4 */\n                .long    Interrupt5_Handler                 /*   5 Interrupt 5 */\n                .long    Interrupt6_Handler                 /*   6 Interrupt 6 */\n                .long    Interrupt7_Handler                 /*   7 Interrupt 7 */\n                .long    Interrupt8_Handler                 /*   8 Interrupt 8 */\n                .long    Interrupt9_Handler                 /*   9 Interrupt 9 */\n\n                .space   (470 * 4)                          /* Interrupts 10 .. 480 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsls     r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                ittt     ge\n                ldrge    r0, [r1, r3]\n                strge    r0, [r2, r3]\n                bge      .L_loop0_0\n\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsls     r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                itt      ge\n                strge    r0, [r1, r2]\n                bge      .L_loop2_0\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* Default exception/interrupt handler */\n\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SecureFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n                Set_Default_Handler  Interrupt0_Handler\n                Set_Default_Handler  Interrupt1_Handler\n                Set_Default_Handler  Interrupt2_Handler\n                Set_Default_Handler  Interrupt3_Handler\n                Set_Default_Handler  Interrupt4_Handler\n                Set_Default_Handler  Interrupt5_Handler\n                Set_Default_Handler  Interrupt6_Handler\n                Set_Default_Handler  Interrupt7_Handler\n                Set_Default_Handler  Interrupt8_Handler\n                Set_Default_Handler  Interrupt9_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Source/IAR/startup_ARMv8MML.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_ARMv8MML.s\n; * @brief    CMSIS Core Device Startup File for\n; *           ARMv8MML Device\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n__vector_table_0x1c\n                DCD      SecureFault_Handler                 ;  -9 Security Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVC Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n                ; Interrupts\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (470)                                ; Interrupts 10 .. 480 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK MemManage_Handler\n                PUBWEAK BusFault_Handler\n                PUBWEAK UsageFault_Handler\n                PUBWEAK SecureFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK DebugMon_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nMemManage_Handler\nBusFault_Handler\nUsageFault_Handler\nSecureFault_Handler\nSVC_Handler\nDebugMon_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Source/startup_ARMv8MML.c",
    "content": "/******************************************************************************\n * @file     startup_ARMv8MML.c\n * @brief    CMSIS-Core Device Startup File for ARMv8MML Device\n * @version  V2.1.0\n * @date     16. December 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMv8MML)\n  #include \"ARMv8MML.h\"\n#elif defined (ARMv8MML_DSP)\n  #include \"ARMv8MML_DSP.h\"\n#elif defined (ARMv8MML_SP)\n  #include \"ARMv8MML_SP.h\"\n#elif defined (ARMv8MML_DSP_SP)\n  #include \"ARMv8MML_DSP_SP.h\"\n#elif defined (ARMv8MML_DP)\n  #include \"ARMv8MML_DP.h\"\n#elif defined (ARMv8MML_DSP_DP)\n  #include \"ARMv8MML_DSP_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n/*----------------------------------------------------------------------------\n  External References\n *----------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n            void Default_Handler(void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\nvoid Interrupt0_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt1_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt2_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt3_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt4_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt5_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt6_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt7_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt8_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid Interrupt9_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),       /*     Initial Stack Pointer */\n  Reset_Handler,                            /*     Reset Handler */\n  NMI_Handler,                              /* -14 NMI Handler */\n  HardFault_Handler,                        /* -13 Hard Fault Handler */\n  MemManage_Handler,                        /* -12 MPU Fault Handler */\n  BusFault_Handler,                         /* -11 Bus Fault Handler */\n  UsageFault_Handler,                       /* -10 Usage Fault Handler */\n  SecureFault_Handler,                      /*  -9 Secure Fault Handler */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  0,                                        /*     Reserved */\n  SVC_Handler,                              /*  -5 SVC Handler */\n  DebugMon_Handler,                         /*  -4 Debug Monitor Handler */\n  0,                                        /*     Reserved */\n  PendSV_Handler,                           /*  -2 PendSV Handler */\n  SysTick_Handler,                          /*  -1 SysTick Handler */\n\n  /* Interrupts */\n  Interrupt0_Handler,                       /*   0 Interrupt 0 */\n  Interrupt1_Handler,                       /*   1 Interrupt 1 */\n  Interrupt2_Handler,                       /*   2 Interrupt 2 */\n  Interrupt3_Handler,                       /*   3 Interrupt 3 */\n  Interrupt4_Handler,                       /*   4 Interrupt 4 */\n  Interrupt5_Handler,                       /*   5 Interrupt 5 */\n  Interrupt6_Handler,                       /*   6 Interrupt 6 */\n  Interrupt7_Handler,                       /*   7 Interrupt 7 */\n  Interrupt8_Handler,                       /*   8 Interrupt 8 */\n  Interrupt9_Handler                        /*   9 Interrupt 9 */\n                                            /* Interrupts 10 .. 480 are left out */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                             /* CMSIS System Initialization */\n  __PROGRAM_START();                        /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Hard Fault Handler\n *----------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/ARMv8MML/Source/system_ARMv8MML.c",
    "content": "/**************************************************************************//**\n * @file     system_ARMv8MML.c\n * @brief    CMSIS Device System Source File for\n *           ARMv8MML Device\n * @version  V1.0.1\n * @date     15. November 2019\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2019 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if defined (ARMv8MML)\n  #include \"ARMv8MML.h\"\n#elif defined (ARMv8MML_DSP)\n  #include \"ARMv8MML_DSP.h\"\n#elif defined (ARMv8MML_SP)\n  #include \"ARMv8MML_SP.h\"\n#elif defined (ARMv8MML_DSP_SP)\n  #include \"ARMv8MML_DSP_SP.h\"\n#elif defined (ARMv8MML_DP)\n  #include \"ARMv8MML_DP.h\"\n#elif defined (ARMv8MML_DSP_DP)\n  #include \"ARMv8MML_DSP_DP.h\"\n#else\n  #error device not specified!\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n  #include \"partition_ARMv8MML.h\"\n#endif\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n#define  XTAL            (50000000UL)     /* Oscillator frequency */\n\n#define  SYSTEM_CLOCK    (XTAL / 2U)\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency */\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock update function\n *----------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n/*----------------------------------------------------------------------------\n  System initialization function\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t) &(__Vectors[0]);\n#endif\n\n#if defined (__FPU_USED) && (__FPU_USED == 1U)\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n#ifdef UNALIGNED_SUPPORT_DISABLE\n  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;\n#endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM0.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM0</name>                                             <!-- name of part-->\n  <series>ARM Cortex M0</series>                                  <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M0 based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM0</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>false</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>false</vtorPresent>\n    <nvicPrioBits>2</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM0P.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM0P</name>                                            <!-- name of part-->\n  <series>ARM Cortex M0+</series>                                 <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M0+ based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM0+</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>false</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>false</vtorPresent>\n    <nvicPrioBits>2</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM1.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM1</name>                                             <!-- name of part-->\n  <series>ARM Cortex M0+</series>                                 <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M0+ based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM1</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>false</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>false</vtorPresent>\n    <nvicPrioBits>2</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM23.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM23</name>                                            <!-- name of part-->\n  <series>ARMv8-M Baseline</series>                               <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M23 based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM23</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n    <sauNumRegions>4</sauNumRegions>\n    <sauRegionsConfig enabled=\"true\" protectionWhenDisabled=\"s\">\n      <region enabled=\"true\" name=\"SauRegion0\">\n        <base>0x00000000</base>\n        <limit>0x001FFFE0</limit>\n        <!-- secure / non-secure callable -->\n        <access>c</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion1\">\n        <base>0x00200000</base>\n        <limit>0x003FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion2\">\n        <base>0x20200000</base>\n        <limit>0x203FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion3\">\n        <base>0x40000000</base>\n        <limit>0x40040000</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n    </sauRegionsConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM3.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM3</name>                                             <!-- name of part-->\n  <series>ARM Cortex M3</series>                                  <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M3 based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM3</name>\n    <revision>r2p1</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM33.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM33</name>                                            <!-- name of part-->\n  <series>ARMv8-M Mainline</series>                               <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M33 based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM33</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n    <sauNumRegions>4</sauNumRegions>\n    <sauRegionsConfig enabled=\"true\" protectionWhenDisabled=\"s\">\n      <region enabled=\"true\" name=\"SauRegion0\">\n        <base>0x00000000</base>\n        <limit>0x001FFFE0</limit>\n        <!-- secure / non-secure callable -->\n        <access>c</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion1\">\n        <base>0x00200000</base>\n        <limit>0x003FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion2\">\n        <base>0x20200000</base>\n        <limit>0x203FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion3\">\n        <base>0x40000000</base>\n        <limit>0x40040000</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n    </sauRegionsConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n  </device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM35P.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM35P</name>                                           <!-- name of part-->\n  <series>ARMv8-M Mainline</series>                               <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M35P based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM35P</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n    <sauNumRegions>4</sauNumRegions>\n    <sauRegionsConfig enabled=\"true\" protectionWhenDisabled=\"s\">\n      <region enabled=\"true\" name=\"SauRegion0\">\n        <base>0x00000000</base>\n        <limit>0x001FFFE0</limit>\n        <!-- secure / non-secure callable -->\n        <access>c</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion1\">\n        <base>0x00200000</base>\n        <limit>0x003FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion2\">\n        <base>0x20200000</base>\n        <limit>0x203FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion3\">\n        <base>0x40000000</base>\n        <limit>0x40040000</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n    </sauRegionsConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n  </device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM4.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM4</name>                                             <!-- name of part-->\n  <series>ARM Cortex M4</series>                                  <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M4 based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM4</name>\n    <revision>r0p1</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM55.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2020 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM55</name>                                            <!-- name of part-->\n  <series>ARMv8.1-M Mainline</series>                             <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M55 based device</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM55</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>true</fpuPresent>\n    <fpuDP>true</fpuDP>\n    <dspPresent>true</dspPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n    <pmuPresent>true</pmuPresent>\n    <pmuNumEventCnt>12</pmuNumEventCnt>\n    <sauNumRegions>4</sauNumRegions>\n    <sauRegionsConfig enabled=\"true\" protectionWhenDisabled=\"s\">\n      <region enabled=\"true\" name=\"SauRegion0\">\n        <base>0x00000000</base>\n        <limit>0x001FFFE0</limit>\n        <!-- secure / non-secure callable -->\n        <access>c</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion1\">\n        <base>0x00200000</base>\n        <limit>0x003FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion2\">\n        <base>0x20200000</base>\n        <limit>0x203FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion3\">\n        <base>0x40000000</base>\n        <limit>0x40040000</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n    </sauRegionsConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM7.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 -2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM7</name>                                             <!-- name of part-->\n  <series>ARM Cortex M7</series>                                  <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M7 based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM7</name>\n    <revision>r1p1</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n    <icachePresent>true</icachePresent>\n    <dcachePresent>true</dcachePresent>\n    <itcmPresent>false</itcmPresent>\n    <dtcmPresent>false</dtcmPresent>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMCM85.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n<!--\n  Copyright (C) 2022 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMCM85</name>                                            <!-- name of part-->\n  <series>ARMv8.1-M Mainline</series>                             <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-M85 based device</description>\n\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>CM85</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>true</fpuPresent>\n    <fpuDP>true</fpuDP>\n    <dspPresent>true</dspPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n    <pmuPresent>true</pmuPresent>\n    <pmuNumEventCnt>12</pmuNumEventCnt>\n    <sauNumRegions>4</sauNumRegions>\n    <sauRegionsConfig enabled=\"true\" protectionWhenDisabled=\"s\">\n      <region enabled=\"true\" name=\"SauRegion0\">\n        <base>0x00000000</base>\n        <limit>0x001FFFE0</limit>\n        <!-- secure / non-secure callable -->\n        <access>c</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion1\">\n        <base>0x00200000</base>\n        <limit>0x003FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion2\">\n        <base>0x20200000</base>\n        <limit>0x203FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion3\">\n        <base>0x40000000</base>\n        <limit>0x40040000</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n    </sauRegionsConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMSC000.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMSC000</name>                                           <!-- name of part-->\n  <series>ARM Cortex SC000</series>                               <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-SC000 based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>SC000</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>false</vtorPresent>\n    <nvicPrioBits>2</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n  </device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMSC300.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMSC300</name>                                             <!-- name of part-->\n  <series>ARM Cortex SC300</series>                               <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit Cortex-SC300 based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>SC300</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n  </device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMv8MBL.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMv8MBL</name>                                           <!-- name of part-->\n  <series>ARMv8-M Baseline</series>                               <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit v8-M Baseline based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>ARMV8MBL</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n    <sauNumRegions>4</sauNumRegions>\n    <sauRegionsConfig enabled=\"true\" protectionWhenDisabled=\"s\">\n      <region enabled=\"true\" name=\"SauRegion0\">\n        <base>0x00000000</base>\n        <limit>0x001FFFE0</limit>\n        <!-- secure / non-secure callable -->\n        <access>c</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion1\">\n        <base>0x00200000</base>\n        <limit>0x003FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion2\">\n        <base>0x20200000</base>\n        <limit>0x203FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion3\">\n        <base>0x40000000</base>\n        <limit>0x40040000</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n    </sauRegionsConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n  </device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/ARM/SVD/ARMv8MML.svd",
    "content": "<?xml version=\"1.0\" encoding=\"utf-8\"?>\n\n<!-- File naming: <vendor>_<part/series name>.svd -->\n\n<!--\n  Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.\n\n  Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)\n           This is a description of a none-existent and incomplete device\n           for demonstration purposes only.\n\n  Redistribution and use in source and binary forms, with or without\n  modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n  POSSIBILITY OF SUCH DAMAGE.\n -->\n\n<device schemaVersion=\"1.3\" xmlns:xs=\"http://www.w3.org/2001/XMLSchema-instance\" xs:noNamespaceSchemaLocation=\"CMSIS-SVD.xsd\" >\n  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->\n  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->\n  <name>ARMv8MML</name>                                           <!-- name of part-->\n  <series>ARMV8M</series>                                         <!-- device series the device belongs to -->\n  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->\n  <description>ARM 32-bit v8-M Baseline based device.</description>\n  <licenseText>                                                   <!-- this license text will appear in header file. \\n force line breaks -->\n    ARM Limited (ARM) is supplying this software for use with Cortex-M\\n\n    processor based microcontroller, but can be equally used for other\\n\n    suitable  processor architectures. This file can be freely distributed.\\n\n    Modifications to this file shall be clearly marked.\\n\n    \\n\n    THIS SOFTWARE IS PROVIDED \"AS IS\".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\\n\n    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\\n\n    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\\n\n    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\\n\n    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n  </licenseText>\n\n  <cpu>                                                           <!-- details about the cpu embedded in the device -->\n    <name>ARMV8MML</name>\n    <revision>r0p0</revision>\n    <endian>little</endian>\n    <mpuPresent>true</mpuPresent>\n    <fpuPresent>false</fpuPresent>\n    <vtorPresent>true</vtorPresent>\n    <nvicPrioBits>3</nvicPrioBits>\n    <vendorSystickConfig>false</vendorSystickConfig>\n    <sauNumRegions>4</sauNumRegions>\n    <sauRegionsConfig enabled=\"true\" protectionWhenDisabled=\"s\">\n      <region enabled=\"true\" name=\"SauRegion0\">\n        <base>0x00000000</base>\n        <limit>0x001FFFE0</limit>\n        <!-- secure / non-secure callable -->\n        <access>c</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion1\">\n        <base>0x00200000</base>\n        <limit>0x003FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion2\">\n        <base>0x20200000</base>\n        <limit>0x203FFFE0</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n      <region enabled=\"true\" name=\"SauRegion3\">\n        <base>0x40000000</base>\n        <limit>0x40040000</limit>\n        <!-- non-secure -->\n        <access>n</access>\n      </region>\n    </sauRegionsConfig>\n  </cpu>\n\n  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->\n  <width>32</width>                                               <!-- bus width is 32 bits -->\n  <!-- default settings implicitly inherited by subsequent sections -->\n  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals\n                                                                       and register that do not define \"size\" themselves -->\n  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->\n  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->\n  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->\n\n</device>\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Flash/Abstract.txt",
    "content": "Creating a new Algorithm\n------------------------\n\nFlash programming algorithms are defined with functions to erase and program\nthe Flash device. Special compiler and linker settings are required. Follow\nthese steps to create and configure a new Flash programming algorithm:\n- From the toolbar, use the drop-down Select Target to define the processor\n  architecture. Cortex-M fits for all Arm Cortex-M0/M0+/M3/M4/M7 devices.\n  The configuration assumes a little-endian microcontroller. In case of a\n  big-endian microcontroller, select the correct processor core with\n  Project - Options for Target - Device.\n- Open the dialog Project - Options for Target - Output and change the content\n  of the field Name of Executable to represent the device, for example\n  MyDevice.\n- Adapt the programming algorithms in the file FlashPrg.c\n- Adapt the device parameters in the file FlashDev.c\n- Use Project - Build Target to generate the new Flash programming algorithm.\n  The output file (for example MyDevice.FLM) has to be added to the DFP.\n\nNote\n----\n- Creating a Flash programming algorithm with MDK-Lite is not supported.\n- Flash programming algorithms use Read-Only Position Independent and\n  Read-Write Position Independent program code. These options are set in the\n  dialogs Project - Options for Target - C/C++ and\n  Project - Options for Target - Asm.\n- The dialog Project - Options for Target - Linker defines the linker scatter\n  file Target.lin. The error L6305 is disabled with diag_suppress L6305.\n  \nFor more information, refer to the documentation available at\nhttp://arm-software.github.io/CMSIS_5/Pack/html/flashAlgorithm.html\n\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Flash/FlashDev.c",
    "content": "/**************************************************************************//**\n * @file     FlashDev.c\n * @brief    Flash Device Description for New Device Flash\n * @version  V1.0.0\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2010-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"FlashOS.h\"        // FlashOS Structures\n\n\nstruct FlashDevice const FlashDevice  =  {\n   FLASH_DRV_VERS,             // Driver Version, do not modify!\n   \"New Device 256kB Flash\",   // Device Name \n   ONCHIP,                     // Device Type\n   0x00000000,                 // Device Start Address\n   0x00040000,                 // Device Size in Bytes (256kB)\n   1024,                       // Programming Page Size\n   0,                          // Reserved, must be 0\n   0xFF,                       // Initial Content of Erased Memory\n   100,                        // Program Page Timeout 100 mSec\n   3000,                       // Erase Sector Timeout 3000 mSec\n\n// Specify Size and Address of Sectors\n   0x002000, 0x000000,         // Sector Size  8kB (8 Sectors)\n   0x010000, 0x010000,         // Sector Size 64kB (2 Sectors) \n   0x002000, 0x030000,         // Sector Size  8kB (8 Sectors)\n   SECTOR_END\n};\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Flash/FlashOS.h",
    "content": "/**************************************************************************//**\n * @file     FlashOS.h\n * @brief    Data structures and entries Functions\n * @version  V1.0.0\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2010-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#define VERS       1           // Interface Version 1.01\n\n#define UNKNOWN    0           // Unknown\n#define ONCHIP     1           // On-chip Flash Memory\n#define EXT8BIT    2           // External Flash Device on 8-bit  Bus\n#define EXT16BIT   3           // External Flash Device on 16-bit Bus\n#define EXT32BIT   4           // External Flash Device on 32-bit Bus\n#define EXTSPI     5           // External Flash Device on SPI\n\n#define SECTOR_NUM 512         // Max Number of Sector Items\n#define PAGE_MAX   65536       // Max Page Size for Programming\n\nstruct FlashSectors  {\n  unsigned long   szSector;    // Sector Size in Bytes\n  unsigned long AddrSector;    // Address of Sector\n};\n\n#define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF\n\nstruct FlashDevice  {\n   unsigned short     Vers;    // Version Number and Architecture\n   char       DevName[128];    // Device Name and Description\n   unsigned short  DevType;    // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ...\n   unsigned long    DevAdr;    // Default Device Start Address\n   unsigned long     szDev;    // Total Size of Device\n   unsigned long    szPage;    // Programming Page Size\n   unsigned long       Res;    // Reserved for future Extension\n   unsigned char  valEmpty;    // Content of Erased Memory\n\n   unsigned long    toProg;    // Time Out of Program Page Function\n   unsigned long   toErase;    // Time Out of Erase Sector Function\n\n   struct FlashSectors sectors[SECTOR_NUM];\n};\n\n#define FLASH_DRV_VERS (0x0100+VERS)   // Driver Version, do not modify!\n\n// Flash Programming Functions (Called by FlashOS)\nextern          int  Init        (unsigned long adr,   // Initialize Flash\n                                  unsigned long clk,\n                                  unsigned long fnc);\nextern          int  UnInit      (unsigned long fnc);  // De-initialize Flash\nextern          int  BlankCheck  (unsigned long adr,   // Blank Check\n                                  unsigned long sz,\n                                  unsigned char pat);\nextern          int  EraseChip   (void);               // Erase complete Device\nextern          int  EraseSector (unsigned long adr);  // Erase Sector Function\nextern          int  ProgramPage (unsigned long adr,   // Program Page Function\n                                  unsigned long sz,\n                                  unsigned char *buf);\nextern unsigned long Verify      (unsigned long adr,   // Verify Function\n                                  unsigned long sz,\n                                  unsigned char *buf);\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Flash/FlashPrg.c",
    "content": "/**************************************************************************//**\n * @file     FlashPrg.c\n * @brief    Flash Programming Functions adapted for New Device Flash\n * @version  V1.0.0\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2010-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#include \"FlashOS.h\"        // FlashOS Structures\n\n/* \n   Mandatory Flash Programming Functions (Called by FlashOS):\n                int Init        (unsigned long adr,   // Initialize Flash\n                                 unsigned long clk,\n                                 unsigned long fnc);\n                int UnInit      (unsigned long fnc);  // De-initialize Flash\n                int EraseSector (unsigned long adr);  // Erase Sector Function\n                int ProgramPage (unsigned long adr,   // Program Page Function\n                                 unsigned long sz,\n                                 unsigned char *buf);\n\n   Optional  Flash Programming Functions (Called by FlashOS):\n                int BlankCheck  (unsigned long adr,   // Blank Check\n                                 unsigned long sz,\n                                 unsigned char pat);\n                int EraseChip   (void);               // Erase complete Device\n      unsigned long Verify      (unsigned long adr,   // Verify Function\n                                 unsigned long sz,\n                                 unsigned char *buf);\n\n       - BlanckCheck  is necessary if Flash space is not mapped into CPU memory space\n       - Verify       is necessary if Flash space is not mapped into CPU memory space\n       - if EraseChip is not provided than EraseSector for all sectors is called\n*/\n\n\n/*\n *  Initialize Flash Programming Functions\n *    Parameter:      adr:  Device Base Address\n *                    clk:  Clock Frequency (Hz)\n *                    fnc:  Function Code (1 - Erase, 2 - Program, 3 - Verify)\n *    Return Value:   0 - OK,  1 - Failed\n */\n\nint Init (unsigned long adr, unsigned long clk, unsigned long fnc) {\n\n  /* Add your Code */\n  return (0);                                  // Finished without Errors\n}\n\n\n/*\n *  De-Initialize Flash Programming Functions\n *    Parameter:      fnc:  Function Code (1 - Erase, 2 - Program, 3 - Verify)\n *    Return Value:   0 - OK,  1 - Failed\n */\n\nint UnInit (unsigned long fnc) {\n\n  /* Add your Code */\n  return (0);                                  // Finished without Errors\n}\n\n\n/*\n *  Erase complete Flash Memory\n *    Return Value:   0 - OK,  1 - Failed\n */\n\nint EraseChip (void) {\n\n  /* Add your Code */\n  return (0);                                  // Finished without Errors\n}\n\n\n/*\n *  Erase Sector in Flash Memory\n *    Parameter:      adr:  Sector Address\n *    Return Value:   0 - OK,  1 - Failed\n */\n\nint EraseSector (unsigned long adr) {\n\n  /* Add your Code */\n  return (0);                                  // Finished without Errors\n}\n\n\n/*\n *  Program Page in Flash Memory\n *    Parameter:      adr:  Page Start Address\n *                    sz:   Page Size\n *                    buf:  Page Data\n *    Return Value:   0 - OK,  1 - Failed\n */\n\nint ProgramPage (unsigned long adr, unsigned long sz, unsigned char *buf) {\n\n  /* Add your Code */\n  return (0);                                  // Finished without Errors\n}\n"
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<LComments>1</LComments>\n        <LGenerateSymbols>1</LGenerateSymbols>\n        <LLibSym>1</LLibSym>\n        <LLines>1</LLines>\n        <LLocSym>1</LLocSym>\n        <LPubSym>1</LPubSym>\n        <LXref>0</LXref>\n        <LExpSel>0</LExpSel>\n      </OPTXL>\n      <OPTFL>\n        <tvExp>1</tvExp>\n        <tvExpOptDlg>0</tvExpOptDlg>\n        <IsCurrentTarget>1</IsCurrentTarget>\n      </OPTFL>\n      <CpuCode>7</CpuCode>\n      <DebugOpt>\n        <uSim>0</uSim>\n        <uTrg>1</uTrg>\n        <sLdApp>1</sLdApp>\n        <sGomain>1</sGomain>\n        <sRbreak>1</sRbreak>\n        <sRwatch>1</sRwatch>\n        <sRmem>1</sRmem>\n        <sRfunc>1</sRfunc>\n        <sRbox>1</sRbox>\n        <tLdApp>1</tLdApp>\n        <tGomain>1</tGomain>\n        <tRbreak>1</tRbreak>\n        <tRwatch>1</tRwatch>\n        <tRmem>1</tRmem>\n        <tRfunc>0</tRfunc>\n        <tRbox>1</tRbox>\n        <tRtrace>1</tRtrace>\n        <sRSysVw>1</sRSysVw>\n        <tRSysVw>1</tRSysVw>\n        <sRunDeb>0</sRunDeb>\n        <sLrtime>0</sLrtime>\n        <bEvRecOn>1</bEvRecOn>\n        <bSchkAxf>0</bSchkAxf>\n        <bTchkAxf>0</bTchkAxf>\n        <nTsel>0</nTsel>\n        <sDll></sDll>\n        <sDllPa></sDllPa>\n        <sDlgDll></sDlgDll>\n        <sDlgPa></sDlgPa>\n        <sIfile></sIfile>\n        <tDll></tDll>\n        <tDllPa></tDllPa>\n        <tDlgDll></tDlgDll>\n        <tDlgPa></tDlgPa>\n        <tIfile></tIfile>\n        <pMon>BIN\\UL2CM3.DLL</pMon>\n      </DebugOpt>\n      <TargetDriverDllRegistry>\n        <SetRegEntry>\n          <Number>0</Number>\n          <Key>UL2CM3</Key>\n          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>\n        </SetRegEntry>\n      </TargetDriverDllRegistry>\n      <Breakpoint/>\n      <Tracepoint>\n        <THDelay>0</THDelay>\n      </Tracepoint>\n      <DebugFlag>\n        <trace>0</trace>\n        <periodic>1</periodic>\n        <aLwin>0</aLwin>\n        <aCover>0</aCover>\n        <aSer1>0</aSer1>\n        <aSer2>0</aSer2>\n        <aPa>0</aPa>\n        <viewmode>0</viewmode>\n        <vrSel>0</vrSel>\n        <aSym>0</aSym>\n        <aTbox>0</aTbox>\n        <AscS1>0</AscS1>\n        <AscS2>0</AscS2>\n        <AscS3>0</AscS3>\n        <aSer3>0</aSer3>\n        <eProf>0</eProf>\n        <aLa>0</aLa>\n        <aPa1>0</aPa1>\n        <AscS4>0</AscS4>\n        <aSer4>0</aSer4>\n        <StkLoc>0</StkLoc>\n        <TrcWin>0</TrcWin>\n        <newCpu>0</newCpu>\n        <uProt>0</uProt>\n      </DebugFlag>\n      <LintExecutable></LintExecutable>\n      <LintConfigFile></LintConfigFile>\n      <bLintAuto>0</bLintAuto>\n      <bAutoGenD>0</bAutoGenD>\n      <LntExFlags>0</LntExFlags>\n      <pMisraName></pMisraName>\n      <pszMrule></pszMrule>\n      <pSingCmds></pSingCmds>\n      <pMultCmds></pMultCmds>\n      <pMisraNamep></pMisraNamep>\n      <pszMrulep></pszMrulep>\n      <pSingCmdsp></pSingCmdsp>\n      <pMultCmdsp></pMultCmdsp>\n    </TargetOption>\n  </Target>\n\n  <Group>\n    <GroupName>Documentation</GroupName>\n    <tvExp>1</tvExp>\n    <tvExpOptDlg>0</tvExpOptDlg>\n    <cbSel>0</cbSel>\n    <RteFlg>0</RteFlg>\n    <File>\n      <GroupNumber>1</GroupNumber>\n      <FileNumber>1</FileNumber>\n      <FileType>5</FileType>\n      <tvExp>0</tvExp>\n      <tvExpOptDlg>0</tvExpOptDlg>\n      <bDave2>0</bDave2>\n      <PathWithFileName>.\\Abstract.txt</PathWithFileName>\n      <FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>\n      <RteFlg>0</RteFlg>\n      <bShared>0</bShared>\n    </File>\n  </Group>\n\n  <Group>\n    <GroupName>Program Functions</GroupName>\n    <tvExp>1</tvExp>\n    <tvExpOptDlg>0</tvExpOptDlg>\n    <cbSel>0</cbSel>\n    <RteFlg>0</RteFlg>\n    <File>\n      <GroupNumber>2</GroupNumber>\n      <FileNumber>2</FileNumber>\n      <FileType>1</FileType>\n      <tvExp>0</tvExp>\n      <tvExpOptDlg>0</tvExpOptDlg>\n      <bDave2>0</bDave2>\n      <PathWithFileName>.\\FlashPrg.c</PathWithFileName>\n      <FilenameWithoutPath>FlashPrg.c</FilenameWithoutPath>\n      <RteFlg>0</RteFlg>\n      <bShared>0</bShared>\n    </File>\n  </Group>\n\n  <Group>\n    <GroupName>Device Description</GroupName>\n    <tvExp>1</tvExp>\n    <tvExpOptDlg>0</tvExpOptDlg>\n    <cbSel>0</cbSel>\n    <RteFlg>0</RteFlg>\n    <File>\n      <GroupNumber>3</GroupNumber>\n      <FileNumber>3</FileNumber>\n      <FileType>1</FileType>\n      <tvExp>0</tvExp>\n      <tvExpOptDlg>0</tvExpOptDlg>\n      <bDave2>0</bDave2>\n      <PathWithFileName>.\\FlashDev.c</PathWithFileName>\n      <FilenameWithoutPath>FlashDev.c</FilenameWithoutPath>\n      <RteFlg>0</RteFlg>\n      <bShared>0</bShared>\n    </File>\n  </Group>\n\n</ProjectOpt>\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Flash/NewDevice.uvprojx",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<Project xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:noNamespaceSchemaLocation=\"project_projx.xsd\">\n\n  <SchemaVersion>2.1</SchemaVersion>\n\n  <Header>### uVision Project, (C) Keil Software</Header>\n\n  <Targets>\n    <Target>\n      <TargetName>Cortex-M</TargetName>\n      <ToolsetNumber>0x4</ToolsetNumber>\n      <ToolsetName>ARM-ADS</ToolsetName>\n      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>\n      <uAC6>0</uAC6>\n      <TargetOption>\n        <TargetCommonOption>\n          <Device>ARMCM0</Device>\n          <Vendor>ARM</Vendor>\n          <PackID>ARM.CMSIS.5.2.1-dev1</PackID>\n          <PackURL>http://www.keil.com/pack/</PackURL>\n          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE(\"Cortex-M0\") CLOCK(12000000) ESEL ELITTLE</Cpu>\n          <FlashUtilSpec></FlashUtilSpec>\n          <StartupFile></StartupFile>\n          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>\n          <DeviceId>0</DeviceId>\n          <RegisterFile>$$Device:ARMCM0$Device\\ARM\\ARMCM0\\Include\\ARMCM0.h</RegisterFile>\n          <MemoryEnv></MemoryEnv>\n          <Cmp></Cmp>\n          <Asm></Asm>\n          <Linker></Linker>\n          <OHString></OHString>\n          <InfinionOptionDll></InfinionOptionDll>\n          <SLE66CMisc></SLE66CMisc>\n          <SLE66AMisc></SLE66AMisc>\n          <SLE66LinkerMisc></SLE66LinkerMisc>\n          <SFDFile>$$Device:ARMCM0$Device\\ARM\\SVD\\ARMCM0.svd</SFDFile>\n          <bCustSvd>0</bCustSvd>\n          <UseEnv>0</UseEnv>\n          <BinPath></BinPath>\n          <IncludePath></IncludePath>\n          <LibPath></LibPath>\n          <RegisterFilePath></RegisterFilePath>\n          <DBRegisterFilePath></DBRegisterFilePath>\n          <TargetStatus>\n            <Error>0</Error>\n            <ExitCodeStop>0</ExitCodeStop>\n            <ButtonStop>0</ButtonStop>\n            <NotGenerated>0</NotGenerated>\n            <InvalidFlash>1</InvalidFlash>\n          </TargetStatus>\n          <OutputDirectory>.\\Objects\\</OutputDirectory>\n          <OutputName>NewDevice</OutputName>\n          <CreateExecutable>1</CreateExecutable>\n          <CreateLib>0</CreateLib>\n          <CreateHexFile>0</CreateHexFile>\n          <DebugInformation>1</DebugInformation>\n          <BrowseInformation>1</BrowseInformation>\n          <ListingPath>.\\Listings\\</ListingPath>\n          <HexFormatSelection>1</HexFormatSelection>\n          <Merge32K>0</Merge32K>\n          <CreateBatchFile>0</CreateBatchFile>\n          <BeforeCompile>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopU1X>0</nStopU1X>\n            <nStopU2X>0</nStopU2X>\n          </BeforeCompile>\n          <BeforeMake>\n            <RunUserProg1>0</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name></UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopB1X>0</nStopB1X>\n            <nStopB2X>0</nStopB2X>\n          </BeforeMake>\n          <AfterMake>\n            <RunUserProg1>1</RunUserProg1>\n            <RunUserProg2>0</RunUserProg2>\n            <UserProg1Name>cmd.exe /C copy \"Objects\\%L\" \".\\@L.FLM\"</UserProg1Name>\n            <UserProg2Name></UserProg2Name>\n            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>\n            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>\n            <nStopA1X>0</nStopA1X>\n            <nStopA2X>0</nStopA2X>\n          </AfterMake>\n          <SelectedForBatchBuild>0</SelectedForBatchBuild>\n          <SVCSIdString></SVCSIdString>\n        </TargetCommonOption>\n        <CommonProperty>\n          <UseCPPCompiler>0</UseCPPCompiler>\n          <RVCTCodeConst>0</RVCTCodeConst>\n          <RVCTZI>0</RVCTZI>\n          <RVCTOtherData>0</RVCTOtherData>\n          <ModuleSelection>0</ModuleSelection>\n          <IncludeInBuild>1</IncludeInBuild>\n          <AlwaysBuild>0</AlwaysBuild>\n          <GenerateAssemblyFile>0</GenerateAssemblyFile>\n          <AssembleAssemblyFile>0</AssembleAssemblyFile>\n          <PublicsOnly>0</PublicsOnly>\n          <StopOnExitCode>3</StopOnExitCode>\n          <CustomArgument></CustomArgument>\n          <IncludeLibraryModules></IncludeLibraryModules>\n          <ComprImg>1</ComprImg>\n        </CommonProperty>\n        <DllOption>\n          <SimDllName>SARMCM3.DLL</SimDllName>\n          <SimDllArguments>  </SimDllArguments>\n          <SimDlgDll>DARMCM1.DLL</SimDlgDll>\n          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>\n          <TargetDllName>SARMCM3.DLL</TargetDllName>\n          <TargetDllArguments> </TargetDllArguments>\n          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>\n          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>\n        </DllOption>\n        <DebugOption>\n          <OPTHX>\n            <HexSelection>1</HexSelection>\n            <HexRangeLowAddress>0</HexRangeLowAddress>\n            <HexRangeHighAddress>0</HexRangeHighAddress>\n            <HexOffset>0</HexOffset>\n            <Oh166RecLen>16</Oh166RecLen>\n          </OPTHX>\n        </DebugOption>\n        <Utilities>\n          <Flash1>\n            <UseTargetDll>1</UseTargetDll>\n            <UseExternalTool>0</UseExternalTool>\n            <RunIndependent>0</RunIndependent>\n            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>\n            <Capability>1</Capability>\n            <DriverSelection>4096</DriverSelection>\n          </Flash1>\n          <bUseTDR>1</bUseTDR>\n          <Flash2>BIN\\UL2CM3.DLL</Flash2>\n          <Flash3>\"\" ()</Flash3>\n          <Flash4></Flash4>\n          <pFcarmOut></pFcarmOut>\n          <pFcarmGrp></pFcarmGrp>\n          <pFcArmRoot></pFcArmRoot>\n          <FcArmLst>0</FcArmLst>\n        </Utilities>\n        <TargetArmAds>\n          <ArmAdsMisc>\n            <GenerateListings>0</GenerateListings>\n            <asHll>1</asHll>\n            <asAsm>1</asAsm>\n            <asMacX>1</asMacX>\n            <asSyms>1</asSyms>\n            <asFals>1</asFals>\n            <asDbgD>1</asDbgD>\n            <asForm>1</asForm>\n            <ldLst>0</ldLst>\n            <ldmm>1</ldmm>\n            <ldXref>1</ldXref>\n            <BigEnd>0</BigEnd>\n            <AdsALst>0</AdsALst>\n            <AdsACrf>1</AdsACrf>\n            <AdsANop>0</AdsANop>\n            <AdsANot>0</AdsANot>\n            <AdsLLst>1</AdsLLst>\n            <AdsLmap>1</AdsLmap>\n            <AdsLcgr>0</AdsLcgr>\n            <AdsLsym>1</AdsLsym>\n            <AdsLszi>1</AdsLszi>\n            <AdsLtoi>1</AdsLtoi>\n            <AdsLsun>1</AdsLsun>\n            <AdsLven>1</AdsLven>\n            <AdsLsxf>0</AdsLsxf>\n            <RvctClst>0</RvctClst>\n            <GenPPlst>0</GenPPlst>\n            <AdsCpuType>\"Cortex-M0\"</AdsCpuType>\n            <RvctDeviceName></RvctDeviceName>\n            <mOS>0</mOS>\n            <uocRom>0</uocRom>\n            <uocRam>0</uocRam>\n            <hadIROM>1</hadIROM>\n            <hadIRAM>1</hadIRAM>\n            <hadXRAM>0</hadXRAM>\n            <uocXRam>0</uocXRam>\n            <RvdsVP>0</RvdsVP>\n            <hadIRAM2>0</hadIRAM2>\n            <hadIROM2>0</hadIROM2>\n            <StupSel>8</StupSel>\n            <useUlib>0</useUlib>\n            <EndSel>1</EndSel>\n            <uLtcg>0</uLtcg>\n            <nSecure>0</nSecure>\n            <RoSelD>3</RoSelD>\n            <RwSelD>3</RwSelD>\n            <CodeSel>0</CodeSel>\n            <OptFeed>0</OptFeed>\n            <NoZi1>0</NoZi1>\n            <NoZi2>0</NoZi2>\n            <NoZi3>0</NoZi3>\n            <NoZi4>0</NoZi4>\n            <NoZi5>0</NoZi5>\n            <Ro1Chk>0</Ro1Chk>\n            <Ro2Chk>0</Ro2Chk>\n            <Ro3Chk>0</Ro3Chk>\n            <Ir1Chk>1</Ir1Chk>\n            <Ir2Chk>0</Ir2Chk>\n            <Ra1Chk>0</Ra1Chk>\n            <Ra2Chk>0</Ra2Chk>\n            <Ra3Chk>0</Ra3Chk>\n            <Im1Chk>1</Im1Chk>\n            <Im2Chk>0</Im2Chk>\n            <OnChipMemories>\n              <Ocm1>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm1>\n              <Ocm2>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm2>\n              <Ocm3>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm3>\n              <Ocm4>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm4>\n              <Ocm5>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm5>\n              <Ocm6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </Ocm6>\n              <IRAM>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </IRAM>\n              <IROM>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </IROM>\n              <XRAM>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </XRAM>\n              <OCR_RVCT1>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT1>\n              <OCR_RVCT2>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT2>\n              <OCR_RVCT3>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT3>\n              <OCR_RVCT4>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x40000</Size>\n              </OCR_RVCT4>\n              <OCR_RVCT5>\n                <Type>1</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT5>\n              <OCR_RVCT6>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT6>\n              <OCR_RVCT7>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT7>\n              <OCR_RVCT8>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT8>\n              <OCR_RVCT9>\n                <Type>0</Type>\n                <StartAddress>0x20000000</StartAddress>\n                <Size>0x20000</Size>\n              </OCR_RVCT9>\n              <OCR_RVCT10>\n                <Type>0</Type>\n                <StartAddress>0x0</StartAddress>\n                <Size>0x0</Size>\n              </OCR_RVCT10>\n            </OnChipMemories>\n            <RvctStartVector></RvctStartVector>\n          </ArmAdsMisc>\n          <Cads>\n            <interw>1</interw>\n            <Optim>1</Optim>\n            <oTime>0</oTime>\n            <SplitLS>0</SplitLS>\n            <OneElfS>0</OneElfS>\n            <Strict>0</Strict>\n            <EnumInt>0</EnumInt>\n            <PlainCh>0</PlainCh>\n            <Ropi>1</Ropi>\n            <Rwpi>1</Rwpi>\n            <wLevel>2</wLevel>\n            <uThumb>0</uThumb>\n            <uSurpInc>0</uSurpInc>\n            <uC99>1</uC99>\n            <useXO>0</useXO>\n            <v6Lang>3</v6Lang>\n            <v6LangP>3</v6LangP>\n            <vShortEn>1</vShortEn>\n            <vShortWch>1</vShortWch>\n            <v6Lto>0</v6Lto>\n            <v6WtE>0</v6WtE>\n            <v6Rtti>0</v6Rtti>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Cads>\n          <Aads>\n            <interw>1</interw>\n            <Ropi>1</Ropi>\n            <Rwpi>1</Rwpi>\n            <thumb>0</thumb>\n            <SplitLS>0</SplitLS>\n            <SwStkChk>0</SwStkChk>\n            <NoWarn>0</NoWarn>\n            <uSurpInc>0</uSurpInc>\n            <useXO>0</useXO>\n            <uClangAs>0</uClangAs>\n            <VariousControls>\n              <MiscControls></MiscControls>\n              <Define></Define>\n              <Undefine></Undefine>\n              <IncludePath></IncludePath>\n            </VariousControls>\n          </Aads>\n          <LDads>\n            <umfTarg>0</umfTarg>\n            <Ropi>0</Ropi>\n            <Rwpi>0</Rwpi>\n            <noStLib>0</noStLib>\n            <RepFail>1</RepFail>\n            <useFile>0</useFile>\n            <TextAddressRange></TextAddressRange>\n            <DataAddressRange></DataAddressRange>\n            <pXoBase></pXoBase>\n            <ScatterFile>.\\Target.lin</ScatterFile>\n            <IncludeLibs></IncludeLibs>\n            <IncludeLibsPath></IncludeLibsPath>\n            <Misc>--diag_suppress L6305</Misc>\n            <LinkerInputFile></LinkerInputFile>\n            <DisabledWarnings></DisabledWarnings>\n          </LDads>\n        </TargetArmAds>\n      </TargetOption>\n      <Groups>\n        <Group>\n          <GroupName>Documentation</GroupName>\n          <Files>\n            <File>\n              <FileName>Abstract.txt</FileName>\n              <FileType>5</FileType>\n              <FilePath>.\\Abstract.txt</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Program Functions</GroupName>\n          <Files>\n            <File>\n              <FileName>FlashPrg.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\FlashPrg.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n        <Group>\n          <GroupName>Device Description</GroupName>\n          <Files>\n            <File>\n              <FileName>FlashDev.c</FileName>\n              <FileType>1</FileType>\n              <FilePath>.\\FlashDev.c</FilePath>\n            </File>\n          </Files>\n        </Group>\n      </Groups>\n    </Target>\n  </Targets>\n\n  <RTE>\n    <apis/>\n    <components/>\n    <files/>\n  </RTE>\n\n</Project>\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Flash/Target.lin",
    "content": "; Linker Control File (scatter-loading)\n;\n\nPRG 0 PI               ; Programming Functions\n{\n  PrgCode +0           ; Code\n  {\n    * (+RO)\n  }\n  PrgData +0           ; Data\n  {\n    * (+RW,+ZI)\n  }\n}\n\nDSCR +0                ; Device Description\n{\n  DevDscr +0\n  {\n    FlashDev.o\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/ReadMe.txt",
    "content": "/*****************************************************************************\n * @file     ReadMe.txt\n * @brief    Explanation how to use the Device folder and template files \n * @version  V3.0.4\n * @date     20. January 2021\n *****************************************************************************/\n\nFollowing directory structure and template files are given:\n\n  - <Vendor>\n      |\n      +-- <Device>\n            |\n            +-- Include\n            |     +-- Template                            only Armv8-M/v8.1-M TrustZone\n            |     |     +- partition_<Device>.h           Secure/Non-Secure configuration\n            |     +- <Device>.h                           header file \n            |     +- system_<Device>.h                    system include file \n            +-- Source\n                  |\n                  +- startup_<Device>.c                   C startup file file \n                  +- system_<Device>.c                    system source file \n                  |\n                  +-- ARM                                 Arm ARMCLang toolchain\n                  |    +- startup_<Device>.s              ASM startup file for ARMCC    (deprecated)\n                  |    +- startup_<Device>.S              ASM startup file for ARMCLang (deprecated)\n                  |    +- <Device>.sct                    Scatter file\n                  |\n                  +-- GCC                                 Arm GNU toolchain\n                  |    +- startup_<Device>.S              ASM startup file              (deprecated)\n                  |    +- <Device>.ld                     Linker description file\n                  |\n                  +-- IAR                                 IAR toolchain\n                       +- startup_<Device>.s              ASM startup file\n\n\nCopy the complete folder including files and replace:\n  - folder name 'Vendor' with the abbreviation for the device vendor  e.g.: NXP. \n  - folder name 'Device' with your specific device name e.g.: LPC17xx.\n  - in the filenames 'Device' with your specific device name e.g.: LPC17xx. \n\n\nThe template files contain comments starting with 'ToDo: '\nThere it is described what you need to do.\n\n\nThe template files contain following placeholder:\n\n  <Device>\n  <Device> should be replaced with your specific device name.\n   e.g.: LPC17xx\n  \n  <DeviceInterrupt>\n  <DeviceInterrupt> should be replaced with a specific device interrupt name.\n  e.g.: TIM1 for Timer#1 interrupt.\n\n  <DeviceAbbreviation>\n  <DeviceAbbreviation> should be replaced with a dedicated device family\n  abbreviation (e.g.: LPC for LPC17xx device family)\n\n  Cortex-M#\n  Cortex-M# can be replaced with the specific Cortex-M number\n  e.g.: Cortex-M3\n\n\n\nNote:\n  Template files (i.e. startup_Device.s, system_Device.c) are application\n  specific and therefore expected to be copied into the application project\n  folder prior to use!\n  "
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/Device.h",
    "content": "/*************************************************************************//**\n * @file     <Device>.h\n * @brief    CMSIS-Core(M) Device Peripheral Access Layer Header File for\n *           Device <Device>\n * @version  V1.0.0\n * @date     20. January 2021\n *****************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef <Device>_H      /* ToDo: Replace '<Device>' with your device name */\n#define <Device>_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/* ========================================================================= */\n/* ============           Interrupt Number Definition           ============ */\n/* ========================================================================= */\n\ntypedef enum IRQn\n{\n/* ================     Cortex-M Core Exception Numbers     ================ */\n\n/* ToDo: Add Cortex exception numbers according the used Cortex-Core */\n  Reset_IRQn             = -15,  /*  1 Reset Vector\n                                       invoked on Power up and warm reset */\n  NonMaskableInt_IRQn    = -14,  /*  2 Non maskable Interrupt\n                                       cannot be stopped or preempted */\n  HardFault_IRQn         = -13,  /*  3 Hard Fault\n                                       all classes of Fault */\n  MemoryManagement_IRQn  = -12,  /*  4 Memory Management\n                                       MPU mismatch, including Access Violation and No Match */\n  BusFault_IRQn          = -11,  /*  5 Bus Fault\n                                       Pre-Fetch-, Memory Access, other address/memory Fault */\n  UsageFault_IRQn        = -10,  /*  6 Usage Fault\n                                       i.e. Undef Instruction, Illegal State Transition */\n  SecureFault_IRQn       =  -9,  /*  7 Secure Fault Interrupt */\n  SVCall_IRQn            =  -5,  /* 11 System Service Call via SVC instruction */\n  DebugMonitor_IRQn      =  -4,  /* 12 Debug Monitor */\n  PendSV_IRQn            =  -2,  /* 14 Pendable request for system service */\n  SysTick_IRQn           =  -1,  /* 15 System Tick Timer */\n\n/* ================        <Device> Interrupt Numbers       ================ */\n/* ToDo: Add here your device specific interrupt numbers\n         according the interrupt handlers defined in startup_Device.s\n         eg.: Interrupt for Timer#1       TIM1_IRQHandler   ->   TIM1_IRQn */\n  <DeviceInterrupt first>_IRQn = 0,    /* first Device Interrupt*/\n  ...\n  <DeviceInterrupt last>_IRQn  = n     /* last Device Interrupt */\n} IRQn_Type;\n\n\n/* ========================================================================= */\n/* ============      Processor and Core Peripheral Section      ============ */\n/* ========================================================================= */\n\n/* ================ Start of section using anonymous unions ================ */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* ================    Configuration of Core Peripherals    ================ */\n/* ToDo: Set the defines according your Device */\n/* ToDo: Define the correct core revision\n         valid CMSIS core revision macro names are:\n           __CM0_REV, __CM0PLUS_REV, __CM1_REV, __CM3_REV, __CM4_REV, __CM7_REV\n           __CM23_REV, __CM33_REV, __CM35P_REV, __CM55_REV\n           __SC000_REV, __SC300_REV */\n#define __CM#_REV               0x0201U  /* Core Revision r2p1 */\n/* ToDo: define the correct core features for the <Device> */\n#define __Vendor_SysTickConfig  0U       /* Set to 1 if different SysTick Config is used */\n#define __NVIC_PRIO_BITS        3U       /* Number of Bits used for Priority Levels */\n#define __VTOR_PRESENT          1U       /* Set to 1 if VTOR is present */\n#define __MPU_PRESENT           1U       /* Set to 1 if MPU is present */\n#define __FPU_PRESENT           0U       /* Set to 1 if FPU is present */\n#define __FPU_DP                0U       /* Set to 1 if FPU is double precision FPU (default is single precision FPU) */\n#define __DSP_PRESENT           1U       /* Set to 1 if DSP extension are present */\n#define __SAUREGION_PRESENT     1U       /* Set to 1 if SAU regions are present */\n#define __PMU_PRESENT           1U       /* Set to 1 if PMU is present */\n#define __PMU_NUM_EVENTCNT      8U       /* Set number of PMU Event Counters */\n#define __ICACHE_PRESENT        0U       /* Set to 1 if I-Cache is present */\n#define __DCACHE_PRESENT        0U       /* Set to 1 if D-Cache is present */\n#define __DTCM_PRESENT          0U       /* Set to 1 if DTCM is present */\n\n\n/* ToDo: Include the CMSIS core header file according your device.\n         valid CMSIS core header files are:\n           core_cm0.h, core_cm0plus.h, core_cm1.h, core_cm3.h, core_cm4.h, core_cm7.h\n           core_cm23.h, core_cm33.h, core_cm35p.h, core_cm55.h\n           core_sc000.h, core_sc300.h */\n#include <core_cm#.h>                           /* Processor and core peripherals */\n/* ToDo: Include your system_<Device>.h file\n         replace '<Device>' with your device name */\n#include \"system_<Device>.h\"                    /* System Header */\n\n\n\n/* ========================================================================= */\n/* ============       Device Specific Peripheral Section        ============ */\n/* ========================================================================= */\n\n\n/* ToDo: Add here your device specific peripheral access structure typedefs\n         including bit definitions for Pos/Msk macros\n         following is an example for a timer */\n\n/* ========================================================================= */\n/* ============                       TMR                       ============ */\n/* ========================================================================= */\n\ntypedef struct\n{\n  __IOM  uint32_t  LOAD;                 /* Offset: 0x000 (R/W) Load Register */\n  __IM   uint32_t  VALUE;                /* Offset: 0x004 (R/ ) Value Register */\n  __IOM  uint32_t  CONTROL;              /* Offset: 0x008 (R/W) Control Register */\n  __OM   uint32_t  INTCLR;               /* Offset: 0x00C ( /W) Clear Interrupt Register */\n  __IM   uint32_t  RIS;                  /* Offset: 0x010 (R/ ) Raw Interrupt Status Register */\n  __IM   uint32_t  MIS;                  /* Offset: 0x014 (R/ ) Interrupt Status Register */\n  __IOM  uint32_t  BGLOAD;               /* Offset: 0x018 (R/W) Background Load Register */\n} <DeviceAbbreviation>_TMR_TypeDef;\n\n/* <DeviceAbbreviation>_TMR LOAD Register Definitions */\n#define <DeviceAbbreviation>_TMR_LOAD_Pos              0\n#define <DeviceAbbreviation>_TMR_LOAD_Msk             (0xFFFFFFFFUL /*<< <DeviceAbbreviation>_TMR_LOAD_Pos*/)\n\n/* <DeviceAbbreviation>_TMR VALUE Register Definitions */\n#define <DeviceAbbreviation>_TMR_VALUE_Pos             0\n#define <DeviceAbbreviation>_TMR_VALUE_Msk            (0xFFFFFFFFUL /*<< <DeviceAbbreviation>_TMR_VALUE_Pos*/)\n\n/* <DeviceAbbreviation>_TMR CONTROL Register Definitions */\n#define <DeviceAbbreviation>_TMR_CONTROL_SIZE_Pos      1\n#define <DeviceAbbreviation>_TMR_CONTROL_SIZE_Msk     (1UL << <DeviceAbbreviation>_TMR_CONTROL_SIZE_Pos)\n\n#define <DeviceAbbreviation>_TMR_CONTROL_ONESHOT_Pos   0\n#define <DeviceAbbreviation>_TMR_CONTROL_ONESHOT_Msk  (1UL /*<< <DeviceAbbreviation>_TMR_CONTROL_ONESHOT_Pos*/)\n\n\n\n/* ================  End of section using anonymous unions  ================ */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* ========================================================================= */\n/* ============     Device Specific Peripheral Address Map      ============ */\n/* ========================================================================= */\n\n\n/* ToDo: Add here your device peripherals base addresses\n         following is an example for timer */\n\n/* Peripheral and SRAM base address */\n#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /* (FLASH     ) Base Address */\n#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /* (SRAM      ) Base Address */\n#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /* (Peripheral) Base Address */\n\n/* Peripheral memory map */\n#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /* (Timer0    ) Base Address */\n#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /* (Timer1    ) Base Address */\n#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /* (Timer2    ) Base Address */\n\n\n/* ========================================================================= */\n/* ============             Peripheral declaration              ============ */\n/* ========================================================================= */\n\n\n/* ToDo: Add here your device peripherals pointer definitions\n         following is an example for timer */\n\n#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)\n#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)\n#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* <Device>_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/Template/partition_Device.h",
    "content": "/*************************************************************************//**\n * @file     partition_<Device>.h\n * @brief    CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for\n *           Device <Device>\n * @version  V1.0.0\n * @date     20. January 2021\n *****************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef PARTITION_<Device>_H      /* ToDo: Replace '<Device>' with your device name */\n#define PARTITION_<Device>_H\n\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------\n*/\n\n/*\n// <e>Initialize Security Attribution Unit (SAU) CTRL register\n*/\n#define SAU_INIT_CTRL          1\n\n/*\n//   <q> Enable SAU\n//   <i> Value for SAU->CTRL register bit ENABLE\n*/\n#define SAU_INIT_CTRL_ENABLE   1\n\n/*\n//   <o> When SAU is disabled\n//     <0=> All Memory is Secure\n//     <1=> All Memory is Non-Secure\n//   <i> Value for SAU->CTRL register bit ALLNS\n//   <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.\n*/\n#define SAU_INIT_CTRL_ALLNS  0\n\n/*\n// </e>\n*/\n\n/*\n// <h>Initialize Security Attribution Unit (SAU) Address Regions\n// <i>SAU configuration specifies regions to be one of:\n// <i> - Secure and Non-Secure Callable\n// <i> - Non-Secure\n// <i>Note: All memory regions not configured by SAU are Secure\n*/\n#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */\n\n/*\n//   <e>Initialize SAU Region 0\n//   <i> Setup SAU Region 0 memory attributes\n*/\n#define SAU_INIT_REGION0    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START0     0x00000000      /* start address of SAU region 0 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END0       0x001FFFFF      /* end address of SAU region 0 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC0       1\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 1\n//   <i> Setup SAU Region 1 memory attributes\n*/\n#define SAU_INIT_REGION1    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START1     0x00200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END1       0x003FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC1       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 2\n//   <i> Setup SAU Region 2 memory attributes\n*/\n#define SAU_INIT_REGION2    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START2     0x20200000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END2       0x203FFFFF\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC2       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 3\n//   <i> Setup SAU Region 3 memory attributes\n*/\n#define SAU_INIT_REGION3    1\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START3     0x40000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END3       0x40040000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC3       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 4\n//   <i> Setup SAU Region 4 memory attributes\n*/\n#define SAU_INIT_REGION4    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START4     0x00000000      /* start address of SAU region 4 */\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END4       0x00000000      /* end address of SAU region 4 */\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC4       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 5\n//   <i> Setup SAU Region 5 memory attributes\n*/\n#define SAU_INIT_REGION5    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START5     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END5       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC5       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 6\n//   <i> Setup SAU Region 6 memory attributes\n*/\n#define SAU_INIT_REGION6    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START6     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END6       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC6       0\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize SAU Region 7\n//   <i> Setup SAU Region 7 memory attributes\n*/\n#define SAU_INIT_REGION7    0\n\n/*\n//     <o>Start Address <0-0xFFFFFFE0>\n*/\n#define SAU_INIT_START7     0x00000000\n\n/*\n//     <o>End Address <0x1F-0xFFFFFFFF>\n*/\n#define SAU_INIT_END7       0x00000000\n\n/*\n//     <o>Region is\n//         <0=>Non-Secure\n//         <1=>Secure, Non-Secure Callable\n*/\n#define SAU_INIT_NSC7       0\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n/*\n// <e>Setup behaviour of Sleep and Exception Handling\n*/\n#define SCB_CSR_AIRCR_INIT  1\n\n/*\n//   <o> Deep Sleep can be enabled by\n//     <0=>Secure and Non-Secure state\n//     <1=>Secure state only\n//   <i> Value for SCB->CSR register bit DEEPSLEEPS\n*/\n#define SCB_CSR_DEEPSLEEPS_VAL  1\n\n/*\n//   <o>System reset request accessible from\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for SCB->AIRCR register bit SYSRESETREQS\n*/\n#define SCB_AIRCR_SYSRESETREQS_VAL  1\n\n/*\n//   <o>Priority of Non-Secure exceptions is\n//     <0=> Not altered\n//     <1=> Lowered to 0x80-0xFF\n//   <i> Value for SCB->AIRCR register bit PRIS\n*/\n#define SCB_AIRCR_PRIS_VAL      1\n\n/*\n//   <o>BusFault, HardFault, and NMI target\n//     <0=> Secure state\n//     <1=> Non-Secure state\n//   <i> Value for SCB->AIRCR register bit BFHFNMINS\n*/\n#define SCB_AIRCR_BFHFNMINS_VAL 0\n\n/*\n// </e>\n*/\n\n/*\n// <e>Setup behaviour of Floating Point and Vector Unit (FPU/MVE)\n*/\n#define TZ_FPU_NS_USAGE 1\n\n/*\n// <o>Floating Point and Vector Unit usage\n//     <0=> Secure state only\n//     <3=> Secure and Non-Secure state\n//   <i> Value for SCB->NSACR register bits CP10, CP11\n*/\n#define SCB_NSACR_CP10_11_VAL       3\n\n/*\n// <o>Treat floating-point registers as Secure\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit TS\n*/\n#define FPU_FPCCR_TS_VAL            0\n\n/*\n// <o>Clear on return (CLRONRET) accessibility\n//     <0=> Secure and Non-Secure state\n//     <1=> Secure state only\n//   <i> Value for FPU->FPCCR register bit CLRONRETS\n*/\n#define FPU_FPCCR_CLRONRETS_VAL     0\n\n/*\n// <o>Clear floating-point caller saved registers on exception return\n//     <0=> Disabled\n//     <1=> Enabled\n//   <i> Value for FPU->FPCCR register bit CLRONRET\n*/\n#define FPU_FPCCR_CLRONRET_VAL      1\n\n/*\n// </e>\n*/\n\n/*\n// <h>Setup Interrupt Target\n*/\n\n/*\n//   <e>Initialize ITNS 0 (Interrupts 0..31)\n*/\n#define NVIC_INIT_ITNS0    1\n\n/*\n// Interrupts 0..31\n//   <o.0>  Interrupt 0   <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 1   <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 2   <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 3   <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 4   <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 5   <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 6   <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 7   <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 8   <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 9   <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 10  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 11  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 12  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 13  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 14  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 15  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 16  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 17  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 18  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 19  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 20  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 21  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 22  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 23  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 24  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 25  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 26  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 27  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 28  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 29  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 30  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 31  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS0_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 1 (Interrupts 32..63)\n*/\n#define NVIC_INIT_ITNS1    1\n\n/*\n// Interrupts 32..63\n//   <o.0>  Interrupt 32  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 33  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 34  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 35  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 36  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 37  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 38  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 39  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 40  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 41  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 42  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 43  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 44  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 45  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 46  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 47  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 48  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 49  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 50  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 51  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 52  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 53  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 54  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 55  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 56  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 57  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 58  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 59  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 60  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 61  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 62  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 63  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS1_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 2 (Interrupts 64..95)\n*/\n#define NVIC_INIT_ITNS2    0\n\n/*\n// Interrupts 64..95\n//   <o.0>  Interrupt 64  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 65  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 66  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 67  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 68  <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 69  <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 70  <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 71  <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 72  <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 73  <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 74  <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 75  <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 76  <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 77  <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 78  <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 79  <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 80  <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 81  <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 82  <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 83  <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 84  <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 85  <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 86  <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 87  <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 88  <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 89  <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 90  <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 91  <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 92  <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 93  <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 94  <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 95  <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS2_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 3 (Interrupts 96..127)\n*/\n#define NVIC_INIT_ITNS3    0\n\n/*\n// Interrupts 96..127\n//   <o.0>  Interrupt 96  <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 97  <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 98  <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 99  <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 100 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 101 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 102 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 103 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 104 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 105 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS3_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 4 (Interrupts 128..159)\n*/\n#define NVIC_INIT_ITNS4    0\n\n/*\n// Interrupts 128..159\n//   <o.0>  Interrupt 128 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 129 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 130 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 131 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 132 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 133 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 134 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 135 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 136 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 137 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS4_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 5 (Interrupts 160..191)\n*/\n#define NVIC_INIT_ITNS5    0\n\n/*\n// Interrupts 160..191\n//   <o.0>  Interrupt 160 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 161 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 162 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 163 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 164 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 165 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 166 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 167 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 168 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 169 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS5_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 6 (Interrupts 192..223)\n*/\n#define NVIC_INIT_ITNS6    0\n\n/*\n// Interrupts 192..223\n//   <o.0>  Interrupt 192 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 193 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 194 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 195 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 196 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 197 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 198 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 199 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 200 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 201 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS6_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 7 (Interrupts 224..255)\n*/\n#define NVIC_INIT_ITNS7    0\n\n/*\n// Interrupts 224..255\n//   <o.0>  Interrupt 224 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 225 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 226 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 227 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 228 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 229 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 230 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 231 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 232 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 233 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS7_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 8 (Interrupts 256..287)\n*/\n#define NVIC_INIT_ITNS8    0\n\n/*\n// Interrupts 256..287\n//   <o.0>  Interrupt 256 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 257 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 258 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 259 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 260 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 261 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 262 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 263 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 264 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 265 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 266 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 267 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 268 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 269 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 270 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 271 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 272 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 273 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 274 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 275 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 276 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 277 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 278 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 279 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 280 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 281 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 282 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 283 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 284 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 285 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 286 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 287 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS8_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 9 (Interrupts 288..319)\n*/\n#define NVIC_INIT_ITNS9    0\n\n/*\n// Interrupts 288..319\n//   <o.0>  Interrupt 288 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 289 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 290 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 291 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 292 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 293 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 294 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 295 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 296 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 297 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 298 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 299 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 300 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 301 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 302 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 303 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 304 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 305 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 306 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 307 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 308 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 309 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 310 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 311 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 312 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 313 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 314 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 315 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 316 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 317 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 318 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 319 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS9_VAL      0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 10 (Interrupts 320..351)\n*/\n#define NVIC_INIT_ITNS10   0\n\n/*\n// Interrupts 320..351\n//   <o.0>  Interrupt 320 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 321 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 322 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 323 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 324 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 325 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 326 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 327 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 328 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 329 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 330 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 331 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 332 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 333 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 334 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 335 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 336 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 337 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 338 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 339 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 340 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 341 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 342 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 343 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 344 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 345 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 346 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 347 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 348 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 349 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 350 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 351 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS10_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 11 (Interrupts 352..383)\n*/\n#define NVIC_INIT_ITNS11   0\n\n/*\n// Interrupts 352..383\n//   <o.0>  Interrupt 352 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 353 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 354 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 355 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 356 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 357 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 358 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 359 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 360 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 361 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 362 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 363 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 364 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 365 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 366 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 367 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 368 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 369 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 370 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 371 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 372 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 373 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 374 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 375 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 376 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 377 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 378 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 379 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 380 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 381 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 382 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 383 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS11_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 12 (Interrupts 384..415)\n*/\n#define NVIC_INIT_ITNS12   0\n\n/*\n// Interrupts 384..415\n//   <o.0>  Interrupt 384 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 385 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 386 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 387 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 388 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 389 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 390 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 391 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 392 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 393 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 394 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 395 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 396 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 397 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 398 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 399 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 400 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 401 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 402 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 403 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 404 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 405 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 406 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 407 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 408 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 409 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 410 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 411 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 412 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 413 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 414 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 415 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS12_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 13 (Interrupts 416..447)\n*/\n#define NVIC_INIT_ITNS13   0\n\n/*\n// Interrupts 416..447\n//   <o.0>  Interrupt 416 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 417 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 418 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 419 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 420 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 421 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 422 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 423 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 424 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 425 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 426 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 427 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 428 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 429 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 430 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 431 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 432 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 433 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 434 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 435 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 436 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 437 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 438 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 439 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 440 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 441 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 442 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 443 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 444 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 445 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 446 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 447 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS13_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 14 (Interrupts 448..479)\n*/\n#define NVIC_INIT_ITNS14   0\n\n/*\n// Interrupts 448..479\n//   <o.0>  Interrupt 448 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 449 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 450 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 451 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 452 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 453 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 454 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 455 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 456 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 457 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 458 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 459 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 460 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 461 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 462 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 463 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 464 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 465 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 466 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 467 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 468 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 469 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 470 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 471 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 472 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 473 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 474 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 475 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 476 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 477 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 478 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 479 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS14_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n//   <e>Initialize ITNS 15 (Interrupts 480..511)\n*/\n#define NVIC_INIT_ITNS15   0\n\n/*\n// Interrupts 480..511\n//   <o.0>  Interrupt 480 <0=> Secure state <1=> Non-Secure state\n//   <o.1>  Interrupt 481 <0=> Secure state <1=> Non-Secure state\n//   <o.2>  Interrupt 482 <0=> Secure state <1=> Non-Secure state\n//   <o.3>  Interrupt 483 <0=> Secure state <1=> Non-Secure state\n//   <o.4>  Interrupt 484 <0=> Secure state <1=> Non-Secure state\n//   <o.5>  Interrupt 485 <0=> Secure state <1=> Non-Secure state\n//   <o.6>  Interrupt 486 <0=> Secure state <1=> Non-Secure state\n//   <o.7>  Interrupt 487 <0=> Secure state <1=> Non-Secure state\n//   <o.8>  Interrupt 488 <0=> Secure state <1=> Non-Secure state\n//   <o.9>  Interrupt 489 <0=> Secure state <1=> Non-Secure state\n//   <o.10> Interrupt 490 <0=> Secure state <1=> Non-Secure state\n//   <o.11> Interrupt 491 <0=> Secure state <1=> Non-Secure state\n//   <o.12> Interrupt 492 <0=> Secure state <1=> Non-Secure state\n//   <o.13> Interrupt 493 <0=> Secure state <1=> Non-Secure state\n//   <o.14> Interrupt 494 <0=> Secure state <1=> Non-Secure state\n//   <o.15> Interrupt 495 <0=> Secure state <1=> Non-Secure state\n//   <o.16> Interrupt 496 <0=> Secure state <1=> Non-Secure state\n//   <o.17> Interrupt 497 <0=> Secure state <1=> Non-Secure state\n//   <o.18> Interrupt 498 <0=> Secure state <1=> Non-Secure state\n//   <o.19> Interrupt 499 <0=> Secure state <1=> Non-Secure state\n//   <o.20> Interrupt 500 <0=> Secure state <1=> Non-Secure state\n//   <o.21> Interrupt 501 <0=> Secure state <1=> Non-Secure state\n//   <o.22> Interrupt 502 <0=> Secure state <1=> Non-Secure state\n//   <o.23> Interrupt 503 <0=> Secure state <1=> Non-Secure state\n//   <o.24> Interrupt 504 <0=> Secure state <1=> Non-Secure state\n//   <o.25> Interrupt 505 <0=> Secure state <1=> Non-Secure state\n//   <o.26> Interrupt 506 <0=> Secure state <1=> Non-Secure state\n//   <o.27> Interrupt 507 <0=> Secure state <1=> Non-Secure state\n//   <o.28> Interrupt 508 <0=> Secure state <1=> Non-Secure state\n//   <o.29> Interrupt 509 <0=> Secure state <1=> Non-Secure state\n//   <o.30> Interrupt 510 <0=> Secure state <1=> Non-Secure state\n//   <o.31> Interrupt 511 <0=> Secure state <1=> Non-Secure state\n*/\n#define NVIC_INIT_ITNS15_VAL     0x00000000\n\n/*\n//   </e>\n*/\n\n/*\n// </h>\n*/\n\n\n\n/*\n    max 128 SAU regions.\n    SAU regions are defined in partition.h\n */\n\n#define SAU_INIT_REGION(n) \\\n    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \\\n    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \\\n    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \\\n                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U\n\n/**\n  \\brief   Setup a SAU Region\n  \\details Writes the region information contained in SAU_Region to the\n           registers SAU_RNR, SAU_RBAR, and SAU_RLAR\n */\n__STATIC_INLINE void TZ_SAU_Setup (void)\n{\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n\n  #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)\n    SAU_INIT_REGION(0);\n  #endif\n\n  #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)\n    SAU_INIT_REGION(1);\n  #endif\n\n  #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)\n    SAU_INIT_REGION(2);\n  #endif\n\n  #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)\n    SAU_INIT_REGION(3);\n  #endif\n\n  #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)\n    SAU_INIT_REGION(4);\n  #endif\n\n  #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)\n    SAU_INIT_REGION(5);\n  #endif\n\n  #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)\n    SAU_INIT_REGION(6);\n  #endif\n\n  #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)\n    SAU_INIT_REGION(7);\n  #endif\n\n  /* repeat this for all possible SAU regions */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n\n  #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)\n    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |\n                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;\n  #endif\n\n  #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)\n    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk    )) |\n                   ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);\n\n    SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk   | SCB_AIRCR_SYSRESETREQS_Msk |\n                                 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk          ))                    |\n                   ((0x05FAU                    << SCB_AIRCR_VECTKEY_Pos)      & SCB_AIRCR_VECTKEY_Msk)      |\n                   ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |\n                   ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk)         |\n                   ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk);\n  #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */\n\n  #if (((defined (__FPU_USED) && (__FPU_USED == 1U))              || \\\n        (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \\\n       (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)))\n\n    SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |\n                   ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));\n\n    FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |\n                   ((FPU_FPCCR_TS_VAL        << FPU_FPCCR_TS_Pos       ) & FPU_FPCCR_TS_Msk       ) |\n                   ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |\n                   ((FPU_FPCCR_CLRONRET_VAL  << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );\n  #endif\n\n  #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)\n    NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)\n    NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)\n    NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)\n    NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)\n    NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)\n    NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)\n    NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)\n    NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U)\n    NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U)\n    NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U)\n    NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U)\n    NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U)\n    NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U)\n    NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U)\n    NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL;\n  #endif\n\n  #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U)\n    NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL;\n  #endif\n\n  /* repeat this for all possible ITNS elements */\n\n}\n\n#endif  /* PARTITION_<Device>_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Include/system_Device.h",
    "content": "/*************************************************************************//**\n * @file     system_<Device>.h\n * @brief    CMSIS-Core(M) Device Peripheral Access Layer Header File for\n *           Device <Device>\n * @version  V1.0.1\n * @date     11. July 2022\n *****************************************************************************/\n/*\n * Copyright (c) 2009-2022 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */\n#define SYSTEM_<Device>_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\n/**\n  \\brief Exception / Interrupt Handler Function Prototype\n*/\ntypedef void(*VECTOR_TABLE_Type)(void);\n\n/**\n  \\brief System Clock Frequency (Core Clock)\n*/\nextern uint32_t SystemCoreClock;\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_<Device>_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/Device_ac5.sct",
    "content": "#! armcc -E\n; command above MUST be in first line (no comment above!)\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE)                    /* starts at end of RAM */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/Device_ac6.sct",
    "content": "#! armclang -E --target=arm-arm-none-eabi -mcpu=<CPU> -xc\n; command above MUST be in first line (no comment above!)\n\n;Note: Add '-mcmse' to first line if your software model is \"Secure Mode\".\n;      #! armclang -E --target=arm-arm-none-eabi -mcpu=<CPU> -xc -mcmse\n\n\n/*\n;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n*/\n\n/*--------------------- Flash Configuration ----------------------------------\n; <h> Flash Configuration\n;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE      0x00000000\n#define __ROM_SIZE      0x00080000\n\n/*--------------------- Embedded RAM Configuration ---------------------------\n; <h> RAM Configuration\n;   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n;   <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE      0x20000000\n#define __RAM_SIZE      0x00040000\n\n/*--------------------- Stack / Heap Configuration ---------------------------\n; <h> Stack / Heap Configuration\n;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __STACK_SIZE    0x00000200\n#define __HEAP_SIZE     0x00000C00\n\n/*--------------------- CMSE Veneer Configuration ---------------------------\n; <h> CMSE Veneer Configuration\n;   <o0>  CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32>\n; </h>\n *----------------------------------------------------------------------------*/\n#define __CMSEVENEER_SIZE    0x200\n\n/*\n;------------- <<< end of configuration section >>> ---------------------------\n*/\n\n/* ----------------------------------------------------------------------------\n  Stack seal size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __STACKSEAL_SIZE   ( 8 )\n#else\n#define __STACKSEAL_SIZE   ( 0 )\n#endif\n\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap boundary definition\n *----------------------------------------------------------------------------*/\n#define __STACK_TOP    (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */\n#define __HEAP_BASE    (AlignExpr(+0, 8))                           /* starts after RW_RAM section, 8 byte aligned */\n\n\n/*----------------------------------------------------------------------------\n  Region base & size definition\n *----------------------------------------------------------------------------*/\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n#define __CV_BASE          ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE )\n#define __CV_SIZE          ( __CMSEVENEER_SIZE )\n#else\n#define __CV_SIZE          ( 0 )\n#endif\n\n#define __RO_BASE          ( __ROM_BASE )\n#define __RO_SIZE          ( __ROM_SIZE - __CV_SIZE )\n\n#define __RW_BASE          ( __RAM_BASE )\n#define __RW_SIZE          ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE )\n\n\n/*----------------------------------------------------------------------------\n  Scatter Region definition\n *----------------------------------------------------------------------------*/\nLR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region\n  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address\n   *.o (RESET, +First)\n   *(InRoot$$Sections)\n   .ANY (+RO)\n   .ANY (+XO)\n  }\n\n  RW_RAM __RW_BASE __RW_SIZE  {                     ; RW data\n   .ANY (+RW +ZI)\n  }\n\n#if __HEAP_SIZE > 0\n  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap\n  }\n#endif\n\n  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack\n  }\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack\n  }\n#endif\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nLR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE  {      ; own load/execution region for CMSE Veneers\n  ER_CMSE_VENEER __CV_BASE __CV_SIZE  {\n   *(Veneer$$CMSE)\n  }\n}\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac5.s",
    "content": ";/*************************************************************************//**\n; * @file     startup_<Device>.s\n; * @brief    CMSIS-Core(M) Device Startup File for\n; *           Device <Device> (using Arm Compiler 5 with scatter file)\n; * @version  V1.0.0\n; * @date     20. January 2021\n; ****************************************************************************/\n;/*\n; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n                IMPORT   |Image$$ARM_LIB_STACK$$ZI$$Limit|\n\n; ToDo: Add Cortex exception vectors according the used Cortex-Core\n__Vectors       DCD      |Image$$ARM_LIB_STACK$$ZI$$Limit|   ; Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n; ToDo: Add your device specific interrupt vectors\n                ; Interrupts\n                DCD      <DeviceInterrupt first>_Handler     ;   first Device Interrupt\n                         ...\n                DCD      <DeviceInterrupt last>_Handler      ;   last Device Interrupt\n\n; ToDo: calculate the empty space according the used Cortex-Core\n                SPACE    (x * 4)                           ; Interrupts x .. 224 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; ToDo: Add Cortex exception handler according the used Cortex-Core\n; Default exception/interrupt handler\n                Set_Default_Handler  NMI_Handler\n;               Set_Default_Handler  HardFault_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n; ToDo: Add your device specific interrupt handler\n                Set_Default_Handler  <DeviceInterrupt first>_Handler\n                ...\n                Set_Default_Handler  <DeviceInterrupt last>_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac5_noSct.s",
    "content": ";/*************************************************************************//**\n; * @file     startup_<Device>.s\n; * @brief    CMSIS-Core(M) Device Startup File for\n; *           Device <Device> (using Arm Compiler 5 without scatter file)\n; * @version  V1.0.0\n; * @date     20. January 2021\n; ****************************************************************************/\n;/*\n; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n\n\n;<h> Stack Configuration\n;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nStack_Size      EQU      0x00000400\n\n                AREA     STACK, NOINIT, READWRITE, ALIGN=3\n__stack_limit\nStack_Mem       SPACE    Stack_Size\n__initial_sp\n\n\n;<h> Heap Configuration\n;  <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n;</h>\n\nHeap_Size       EQU      0x00000C00\n\n                IF       Heap_Size != 0                      ; Heap is provided\n                AREA     HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem        SPACE    Heap_Size\n__heap_limit\n                ENDIF\n\n\n                PRESERVE8\n                THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n\n                AREA     RESET, DATA, READONLY\n                EXPORT   __Vectors\n                EXPORT   __Vectors_End\n                EXPORT   __Vectors_Size\n\n; ToDo: Add Cortex exception vectors according the used Cortex-Core\n__Vectors       DCD      __initial_sp                        ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n; ToDo: Add your device specific interrupt vectors\n                ; Interrupts\n                DCD      <DeviceInterrupt first>_Handler     ;   first Device Interrupt\n                         ...\n                DCD      <DeviceInterrupt last>_Handler      ;   last Device Interrupt\n\n; ToDo: calculate the empty space according the used Cortex-Core\n                SPACE    (x * 4)                           ; Interrupts x .. 224 are left out\n__Vectors_End\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                AREA     |.text|, CODE, READONLY\n\n; Reset Handler\n\nReset_Handler   PROC\n                EXPORT   Reset_Handler             [WEAK]\n                IMPORT   SystemInit\n                IMPORT   __main\n\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__main\n                BX       R0\n                ENDP\n\n\n; The default macro is not used for HardFault_Handler\n; because this results in a poor debug illusion.\nHardFault_Handler PROC\n                EXPORT   HardFault_Handler         [WEAK]\n                B        .\n                ENDP\n\n; Macro to define default exception/interrupt handlers.\n; Default handler are weak symbols with an endless loop.\n; They can be overwritten by real handlers.\n                MACRO\n                Set_Default_Handler  $Handler_Name\n$Handler_Name   PROC\n                EXPORT   $Handler_Name             [WEAK]\n                B        .\n                ENDP\n                MEND\n\n\n; ToDo: Add Cortex exception handler according the used Cortex-Core\n; Default exception/interrupt handler\n                Set_Default_Handler  NMI_Handler\n;               Set_Default_Handler  HardFault_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n; ToDo: Add your device specific interrupt handler\n                Set_Default_Handler  <DeviceInterrupt first>_Handler\n                ...\n                Set_Default_Handler  <DeviceInterrupt last>_Handler\n\n                ALIGN\n\n\n; User setup Stack & Heap\n\n                IF       :LNOT::DEF:__MICROLIB\n                IMPORT   __use_two_region_memory\n                ENDIF\n\n                EXPORT   __stack_limit\n                EXPORT   __initial_sp\n                IF       Heap_Size != 0                      ; Heap is provided\n                EXPORT   __heap_base\n                EXPORT   __heap_limit\n                ENDIF\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/ARM/startup_Device_ac6.S",
    "content": "/**************************************************************************//**\n * @file     startup_<Device>.S\n * @brief    CMSIS-Core(M) Device Startup File for\n *           Device <Device> (using Arm Compiler 6 with scatter file)\n * @version  V1.0.0\n * @date     20. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n/* ToDo: Set .arch to the architecture according the used Cortex-Core */\n                .arch    armv8-m.main\n\n                #define __INITIAL_SP     Image$$ARM_LIB_STACK$$ZI$$Limit\n                #define __STACK_LIMIT    Image$$ARM_LIB_STACK$$ZI$$Base\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     Image$$STACKSEAL$$ZI$$Base\n                #endif\n\n                .section RESET\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n/* ToDo: Add Cortex exception vectors according the used Cortex-Core */\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    SecureFault_Handler                /*  -9 Secure Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n/* ToDo: Add your device specific interrupt vectors */\n                /* Interrupts */\n                .long    <DeviceInterrupt first>_Handler   /*   first Device Interrupt */\n                         ...\n                .long    <DeviceInterrupt last>_Handler    /*   last Device Interrupt */\n\n/* ToDo: calculate the empty space according the used Cortex-Core */\n                .space   (x * 4)                          /* Interrupts x .. 480 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                bl       SystemInit\n\n                bl       __main\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* ToDo: Add Cortex exception handler according the used Cortex-Core */\n/* Default exception/interrupt handler */\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SecureFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n/* ToDo: Add your device specific interrupt handler */\n                Set_Default_Handler  <DeviceInterrupt first>_Handler\n                ...\n                Set_Default_Handler  <DeviceInterrupt last>_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/gcc_arm.ld",
    "content": "/******************************************************************************\n * @file     gcc_arm.ld\n * @brief    GNU Linker Script for Cortex-M based device\n * @version  V2.2.0\n * @date     20. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*\n *-------- <<< Use Configuration Wizard in Context Menu >>> -------------------\n */\n\n/*---------------------- Flash Configuration ----------------------------------\n  <h> Flash Configuration\n    <o0> Flash Base Address <0x0-0xFFFFFFFF:8>\n    <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__ROM_BASE = 0x00000000;\n__ROM_SIZE = 0x00040000;\n\n/*--------------------- Embedded RAM Configuration ----------------------------\n  <h> RAM Configuration\n    <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n    <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n -----------------------------------------------------------------------------*/\n__RAM_BASE = 0x20000000;\n__RAM_SIZE = 0x00020000;\n\n/*--------------------- Stack / Heap Configuration ----------------------------\n  <h> Stack / Heap Configuration\n    <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n    <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n  </h>\n  -----------------------------------------------------------------------------*/\n__STACK_SIZE = 0x00000400;\n__HEAP_SIZE  = 0x00000C00;\n\n/*\n *-------------------- <<< end of configuration section >>> -------------------\n */\n\n/* ARMv8-M stack sealing:\n   to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0\n */\n__STACKSEAL_SIZE = 0;\n\n\nMEMORY\n{\n  FLASH (rx)  : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE\n  RAM   (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE\n}\n\n/* Linker script to place sections and symbol values. Should be used together\n * with other linker script that defines memory regions FLASH and RAM.\n * It references following symbols, which must be defined in code:\n *   Reset_Handler : Entry of reset handler\n *\n * It defines following symbols, which code can use without definition:\n *   __exidx_start\n *   __exidx_end\n *   __copy_table_start__\n *   __copy_table_end__\n *   __zero_table_start__\n *   __zero_table_end__\n *   __etext\n *   __data_start__\n *   __preinit_array_start\n *   __preinit_array_end\n *   __init_array_start\n *   __init_array_end\n *   __fini_array_start\n *   __fini_array_end\n *   __data_end__\n *   __bss_start__\n *   __bss_end__\n *   __end__\n *   end\n *   __HeapLimit\n *   __StackLimit\n *   __StackTop\n *   __stack\n *   __StackSeal      (only if ARMv8-M stack sealing is used)\n */\nENTRY(Reset_Handler)\n\nSECTIONS\n{\n  .text :\n  {\n    KEEP(*(.vectors))\n    *(.text*)\n\n    KEEP(*(.init))\n    KEEP(*(.fini))\n\n    /* .ctors */\n    *crtbegin.o(.ctors)\n    *crtbegin?.o(.ctors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)\n    *(SORT(.ctors.*))\n    *(.ctors)\n\n    /* .dtors */\n    *crtbegin.o(.dtors)\n    *crtbegin?.o(.dtors)\n    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)\n    *(SORT(.dtors.*))\n    *(.dtors)\n\n    *(.rodata*)\n\n    KEEP(*(.eh_frame*))\n  } > FLASH\n\n  /*\n   * SG veneers:\n   * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address\n   * must be set, either with the command line option --section-start or in a linker script,\n   * to indicate where to place these veneers in memory.\n   */\n/*\n  .gnu.sgstubs :\n  {\n    . = ALIGN(32);\n  } > FLASH\n*/\n  .ARM.extab :\n  {\n    *(.ARM.extab* .gnu.linkonce.armextab.*)\n  } > FLASH\n\n  __exidx_start = .;\n  .ARM.exidx :\n  {\n    *(.ARM.exidx* .gnu.linkonce.armexidx.*)\n  } > FLASH\n  __exidx_end = .;\n\n  .copy.table :\n  {\n    . = ALIGN(4);\n    __copy_table_start__ = .;\n\n    LONG (__etext)\n    LONG (__data_start__)\n    LONG ((__data_end__ - __data_start__) / 4)\n\n    /* Add each additional data section here */\n/*\n    LONG (__etext2)\n    LONG (__data2_start__)\n    LONG ((__data2_end__ - __data2_start__) / 4)\n*/\n    __copy_table_end__ = .;\n  } > FLASH\n\n  .zero.table :\n  {\n    . = ALIGN(4);\n    __zero_table_start__ = .;\n    /* Add each additional bss section here */\n/*\n    LONG (__bss2_start__)\n    LONG ((__bss2_end__ - __bss2_start__) / 4)\n*/\n    __zero_table_end__ = .;\n  } > FLASH\n\n  /**\n   * Location counter can end up 2byte aligned with narrow Thumb code but\n   * __etext is assumed by startup code to be the LMA of a section in RAM\n   * which must be 4byte aligned\n   */\n  __etext = ALIGN (4);\n\n  .data : AT (__etext)\n  {\n    __data_start__ = .;\n    *(vtable)\n    *(.data)\n    *(.data.*)\n\n    . = ALIGN(4);\n    /* preinit data */\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP(*(.preinit_array))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n\n    . = ALIGN(4);\n    /* init data */\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP(*(SORT(.init_array.*)))\n    KEEP(*(.init_array))\n    PROVIDE_HIDDEN (__init_array_end = .);\n\n    . = ALIGN(4);\n    /* finit data */\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP(*(SORT(.fini_array.*)))\n    KEEP(*(.fini_array))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n\n    KEEP(*(.jcr*))\n    . = ALIGN(4);\n    /* All data end */\n    __data_end__ = .;\n\n  } > RAM\n\n  /*\n   * Secondary data section, optional\n   *\n   * Remember to add each additional data section\n   * to the .copy.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  __etext2 = ALIGN (4);\n\n  .data2 : AT (__etext2)\n  {\n    . = ALIGN(4);\n    __data2_start__ = .;\n    *(.data2)\n    *(.data2.*)\n    . = ALIGN(4);\n    __data2_end__ = .;\n\n  } > RAM2\n*/\n\n  .bss :\n  {\n    . = ALIGN(4);\n    __bss_start__ = .;\n    *(.bss)\n    *(.bss.*)\n    *(COMMON)\n    . = ALIGN(4);\n    __bss_end__ = .;\n  } > RAM AT > RAM\n\n  /*\n   * Secondary bss section, optional\n   *\n   * Remember to add each additional bss section\n   * to the .zero.table above to asure proper\n   * initialization during startup.\n   */\n/*\n  .bss2 :\n  {\n    . = ALIGN(4);\n    __bss2_start__ = .;\n    *(.bss2)\n    *(.bss2.*)\n    . = ALIGN(4);\n    __bss2_end__ = .;\n  } > RAM2 AT > RAM2\n*/\n\n  .heap (COPY) :\n  {\n    . = ALIGN(8);\n    __end__ = .;\n    PROVIDE(end = .);\n    . = . + __HEAP_SIZE;\n    . = ALIGN(8);\n    __HeapLimit = .;\n  } > RAM\n\n  .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackLimit = .;\n    . = . + __STACK_SIZE;\n    . = ALIGN(8);\n    __StackTop = .;\n  } > RAM\n  PROVIDE(__stack = __StackTop);\n\n  /* ARMv8-M stack sealing:\n     to use ARMv8-M stack sealing uncomment '.stackseal' section\n   */\n/*\n  .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) :\n  {\n    . = ALIGN(8);\n    __StackSeal = .;\n    . = . + 8;\n    . = ALIGN(8);\n  } > RAM\n*/\n\n  /* Check if data + heap + stack exceeds RAM limit */\n  ASSERT(__StackLimit >= __HeapLimit, \"region RAM overflowed with stack\")\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/GCC/startup_Device.S",
    "content": "/**************************************************************************//**\n * @file     startup_<Device>.S\n * @brief    CMSIS-Core(M) Device Startup File for\n *           Device <Device>\n * @version  V1.0.0\n * @date     20. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n                .syntax  unified\n/* ToDo: Set .arch to the architecture according the used Cortex-Core */\n                .arch    armv8-m.main\n\n                #define __INITIAL_SP     __StackTop\n                #define __STACK_LIMIT    __StackLimit\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                #define __STACK_SEAL     __StackSeal\n                #endif\n\n                .section .vectors\n                .align   2\n                .globl   __Vectors\n                .globl   __Vectors_End\n                .globl   __Vectors_Size\n/* ToDo: Add Cortex exception vectors according the used Cortex-Core */\n__Vectors:\n                .long    __INITIAL_SP                       /*     Initial Stack Pointer */\n                .long    Reset_Handler                      /*     Reset Handler */\n                .long    NMI_Handler                        /* -14 NMI Handler */\n                .long    HardFault_Handler                  /* -13 Hard Fault Handler */\n                .long    MemManage_Handler                  /* -12 MPU Fault Handler */\n                .long    BusFault_Handler                   /* -11 Bus Fault Handler */\n                .long    UsageFault_Handler                 /* -10 Usage Fault Handler */\n                .long    SecureFault_Handler                /*  -9 Secure Fault Handler */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    0                                  /*     Reserved */\n                .long    SVC_Handler                        /*  -5 SVCall Handler */\n                .long    DebugMon_Handler                   /*  -4 Debug Monitor Handler */\n                .long    0                                  /*     Reserved */\n                .long    PendSV_Handler                     /*  -2 PendSV Handler */\n                .long    SysTick_Handler                    /*  -1 SysTick Handler */\n\n/* ToDo: Add your device specific interrupt vectors */\n                /* Interrupts */\n                .long    <DeviceInterrupt first>_Handler   /*   first Device Interrupt */\n                         ...\n                .long    <DeviceInterrupt last>_Handler    /*   last Device Interrupt */\n\n/* ToDo: calculate the empty space according the used Cortex-Core */\n                .space   (x * 4)                          /* Interrupts x .. 480 are left out */\n__Vectors_End:\n                .equ     __Vectors_Size, __Vectors_End - __Vectors\n                .size    __Vectors, . - __Vectors\n\n\n                .thumb\n                .section .text\n                .align   2\n\n                .thumb_func\n                .type    Reset_Handler, %function\n                .globl   Reset_Handler\n                .fnstart\nReset_Handler:\n                ldr      r0, =__INITIAL_SP\n                msr      psp, r0\n\n                ldr      r0, =__STACK_LIMIT\n                msr      msplim, r0\n                msr      psplim, r0\n\n                #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n                ldr      r0, =__STACK_SEAL\n                ldr      r1, =0xFEF5EDA5U\n                strd     r1,r1,[r0,#0]\n                #endif\n\n                bl       SystemInit\n\n                ldr      r4, =__copy_table_start__\n                ldr      r5, =__copy_table_end__\n\n.L_loop0:\n                cmp      r4, r5\n                bge      .L_loop0_done\n                ldr      r1, [r4]                /* source address */\n                ldr      r2, [r4, #4]            /* destination address */\n                ldr      r3, [r4, #8]            /* word count */\n                lsl      r3, r3, #2              /* byte count */\n\n.L_loop0_0:\n                subs     r3, #4                  /* decrement byte count */\n                ittt     ge\n                ldrge    r0, [r1, r3]\n                strge    r0, [r2, r3]\n                bge      .L_loop0_0\n\n                adds     r4, #12\n                b        .L_loop0\n.L_loop0_done:\n\n                ldr      r3, =__zero_table_start__\n                ldr      r4, =__zero_table_end__\n\n.L_loop2:\n                cmp      r3, r4\n                bge      .L_loop2_done\n                ldr      r1, [r3]                /* destination address */\n                ldr      r2, [r3, #4]            /* word count */\n                lsl      r2, r2, #2              /* byte count */\n                movs     r0, 0\n\n.L_loop2_0:\n                subs     r2, #4                  /* decrement byte count */\n                itt      ge\n                strge    r0, [r1, r2]\n                bge      .L_loop2_0\n\n                adds     r3, #8\n                b        .L_loop2\n.L_loop2_done:\n\n                bl       _start\n\n                .fnend\n                .size    Reset_Handler, . - Reset_Handler\n\n\n/* The default macro is not used for HardFault_Handler\n * because this results in a poor debug illusion.\n */\n                .thumb_func\n                .type    HardFault_Handler, %function\n                .weak    HardFault_Handler\n                .fnstart\nHardFault_Handler:\n                b        .\n                .fnend\n                .size    HardFault_Handler, . - HardFault_Handler\n\n                .thumb_func\n                .type    Default_Handler, %function\n                .weak    Default_Handler\n                .fnstart\nDefault_Handler:\n                b        .\n                .fnend\n                .size    Default_Handler, . - Default_Handler\n\n/* Macro to define default exception/interrupt handlers.\n * Default handler are weak symbols with an endless loop.\n * They can be overwritten by real handlers.\n */\n                .macro   Set_Default_Handler  Handler_Name\n                .weak    \\Handler_Name\n                .set     \\Handler_Name, Default_Handler\n                .endm\n\n\n/* ToDo: Add Cortex exception handler according the used Cortex-Core */\n/* Default exception/interrupt handler */\n                Set_Default_Handler  NMI_Handler\n                Set_Default_Handler  MemManage_Handler\n                Set_Default_Handler  BusFault_Handler\n                Set_Default_Handler  UsageFault_Handler\n                Set_Default_Handler  SecureFault_Handler\n                Set_Default_Handler  SVC_Handler\n                Set_Default_Handler  DebugMon_Handler\n                Set_Default_Handler  PendSV_Handler\n                Set_Default_Handler  SysTick_Handler\n\n/* ToDo: Add your device specific interrupt handler */\n                Set_Default_Handler  <DeviceInterrupt first>_Handler\n                ...\n                Set_Default_Handler  <DeviceInterrupt last>_Handler\n\n                .end\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/IAR/startup_Device.s",
    "content": ";/**************************************************************************//**\n; * @file     startup_<Device>.s\n; * @brief    CMSIS Cortex-M# Core Device Startup File for\n; *           Device <Device>\n; * @version  V1.0.0\n; * @date     09. July 2018\n; ******************************************************************************/\n;/*\n; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n; *\n; * SPDX-License-Identifier: Apache-2.0\n; *\n; * Licensed under the Apache License, Version 2.0 (the License); you may\n; * not use this file except in compliance with the License.\n; * You may obtain a copy of the License at\n; *\n; * www.apache.org/licenses/LICENSE-2.0\n; *\n; * Unless required by applicable law or agreed to in writing, software\n; * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n; * See the License for the specific language governing permissions and\n; * limitations under the License.\n; */\n\n;\n; The modules in this file are included in the libraries, and may be replaced\n; by any user-defined modules that define the PUBLIC symbol _program_start or\n; a user defined start symbol.\n; To override the cstartup defined in the library, simply add your modified\n; version to the workbench project.\n;\n; The vector table is normally located at address 0.\n; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.\n; The name \"__vector_table\" has special meaning for C-SPY:\n; it is where the SP start value is found, and the NVIC vector\n; table register (VTOR) is initialized to this address if != 0.\n;\n; Cortex-M version\n;\n\n                MODULE   ?cstartup\n\n                ;; Forward declaration of sections.\n                SECTION  CSTACK:DATA:NOROOT(3)\n\n                SECTION  .intvec:CODE:NOROOT(2)\n\n                EXTERN   __iar_program_start\n                EXTERN   SystemInit\n                PUBLIC   __vector_table\n                PUBLIC   __vector_table_0x1c\n                PUBLIC   __Vectors\n                PUBLIC   __Vectors_End\n                PUBLIC   __Vectors_Size\n\n                DATA\n\n__vector_table\n                DCD      sfe(CSTACK)                         ;     Top of Stack\n                DCD      Reset_Handler                       ;     Reset Handler\n                DCD      NMI_Handler                         ; -14 NMI Handler\n                DCD      HardFault_Handler                   ; -13 Hard Fault Handler\n                DCD      MemManage_Handler                   ; -12 MPU Fault Handler\n                DCD      BusFault_Handler                    ; -11 Bus Fault Handler\n                DCD      UsageFault_Handler                  ; -10 Usage Fault Handler\n__vector_table_0x1c\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      0                                   ;     Reserved\n                DCD      SVC_Handler                         ;  -5 SVCall Handler\n                DCD      DebugMon_Handler                    ;  -4 Debug Monitor Handler\n                DCD      0                                   ;     Reserved\n                DCD      PendSV_Handler                      ;  -2 PendSV Handler\n                DCD      SysTick_Handler                     ;  -1 SysTick Handler\n\n        ; External Interrupts\n; ToDo:  Add here the vectors for the device specific external interrupts handler\n                DCD      Interrupt0_Handler                  ;   0 Interrupt 0\n                DCD      Interrupt1_Handler                  ;   1 Interrupt 1\n                DCD      Interrupt2_Handler                  ;   2 Interrupt 2\n                DCD      Interrupt3_Handler                  ;   3 Interrupt 3\n                DCD      Interrupt4_Handler                  ;   4 Interrupt 4\n                DCD      Interrupt5_Handler                  ;   5 Interrupt 5\n                DCD      Interrupt6_Handler                  ;   6 Interrupt 6\n                DCD      Interrupt7_Handler                  ;   7 Interrupt 7\n                DCD      Interrupt8_Handler                  ;   8 Interrupt 8\n                DCD      Interrupt9_Handler                  ;   9 Interrupt 9\n\n                DS32    (214)                                ; Interrupts 10 .. 224 are left out\n__Vectors_End\n\n__Vectors       EQU      __vector_table\n__Vectors_Size  EQU      __Vectors_End - __Vectors\n\n\n                THUMB\n\n; Reset Handler\n\n                PUBWEAK  Reset_Handler\n                SECTION  .text:CODE:REORDER:NOROOT(2)\nReset_Handler\n                LDR      R0, =SystemInit\n                BLX      R0\n                LDR      R0, =__iar_program_start\n                BX       R0\n\n\n                PUBWEAK NMI_Handler\n                PUBWEAK HardFault_Handler\n                PUBWEAK MemManage_Handler\n                PUBWEAK BusFault_Handler\n                PUBWEAK UsageFault_Handler\n                PUBWEAK SVC_Handler\n                PUBWEAK DebugMon_Handler\n                PUBWEAK PendSV_Handler\n                PUBWEAK SysTick_Handler\n\n                PUBWEAK Interrupt0_Handler\n                PUBWEAK Interrupt1_Handler\n                PUBWEAK Interrupt2_Handler\n                PUBWEAK Interrupt3_Handler\n                PUBWEAK Interrupt4_Handler\n                PUBWEAK Interrupt5_Handler\n                PUBWEAK Interrupt6_Handler\n                PUBWEAK Interrupt7_Handler\n                PUBWEAK Interrupt8_Handler\n                PUBWEAK Interrupt9_Handler\n                SECTION .text:CODE:REORDER:NOROOT(1)\nNMI_Handler\nHardFault_Handler\nMemManage_Handler\nBusFault_Handler\nUsageFault_Handler\nSVC_Handler\nDebugMon_Handler\nPendSV_Handler\nSysTick_Handler\n\nInterrupt0_Handler\nInterrupt1_Handler\nInterrupt2_Handler\nInterrupt3_Handler\nInterrupt4_Handler\nInterrupt5_Handler\nInterrupt6_Handler\nInterrupt7_Handler\nInterrupt8_Handler\nInterrupt9_Handler\nDefault_Handler\n                B        .\n\n\n                END\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/startup_Device.c",
    "content": "/******************************************************************************\n * @file     startup_<Device>.c\n * @brief    CMSIS-Core(M) Device Startup File for\n *           Device <Device>\n * @version  V1.0.0\n * @date     20. January 2021\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"<Device>.h\"\n\n/*---------------------------------------------------------------------------\n  External References\n *---------------------------------------------------------------------------*/\nextern uint32_t __INITIAL_SP;\nextern uint32_t __STACK_LIMIT;\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\nextern uint32_t __STACK_SEAL;\n#endif\n\nextern __NO_RETURN void __PROGRAM_START(void);\n\n/*---------------------------------------------------------------------------\n  Internal References\n *---------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler  (void);\n__NO_RETURN void Default_Handler(void);\n\n/* ToDo: Add Cortex exception handler according the used Cortex-Core */\n/*---------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *---------------------------------------------------------------------------*/\n/* Exceptions */\nvoid NMI_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid HardFault_Handler      (void) __attribute__ ((weak));\nvoid MemManage_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid BusFault_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid UsageFault_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SecureFault_Handler    (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler            (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DebugMon_Handler       (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PendSV_Handler         (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SysTick_Handler        (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/* ToDo: Add your device specific interrupt handler */\nvoid <DeviceInterrupt first>_Handler     (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n...\nvoid <DeviceInterrupt last>_Handler      (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *----------------------------------------------------------------------------*/\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wpedantic\"\n#endif\n\n/* ToDo: Add Cortex exception vectors according the used Cortex-Core */\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[<Device vector table entries>];\n       const VECTOR_TABLE_Type __VECTOR_TABLE[<Device vector table entries>] __VECTOR_TABLE_ATTRIBUTE = {\n  (VECTOR_TABLE_Type)(&__INITIAL_SP),  /*     Initial Stack Pointer */\n  Reset_Handler,                       /*     Reset Handler */\n  NMI_Handler,                         /* -14 NMI Handler */\n  HardFault_Handler,                   /* -13 Hard Fault Handler */\n  MemManage_Handler,                   /* -12 MPU Fault Handler */\n  BusFault_Handler,                    /* -11 Bus Fault Handler */\n  UsageFault_Handler,                  /* -10 Usage Fault Handler */\n  SecureFault_Handler,                 /*  -9 Secure Fault Handler */\n  0,                                   /*     Reserved */\n  0,                                   /*     Reserved */\n  0,                                   /*     Reserved */\n  SVC_Handler,                         /*  -5 SVCall Handler */\n  DebugMon_Handler,                    /*  -4 Debug Monitor Handler */\n  0,                                   /*     Reserved */\n  PendSV_Handler,                      /*  -2 PendSV Handler */\n  SysTick_Handler,                     /*  -1 SysTick Handler */\n\n/* ToDo: Add your device specific interrupt vectors */\n  /* Interrupts */\n  <DeviceInterrupt first>_Handler,     /* first Device Interrupt */\n  ...\n  <DeviceInterrupt last>_Handler       /* last Device Interrupt */\n};\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n/*---------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *---------------------------------------------------------------------------*/\n__NO_RETURN void Reset_Handler(void)\n{\n  __set_PSP((uint32_t)(&__INITIAL_SP));\n\n/* ToDo: Initialize stack limit register for Armv8-M Main Extension based processors*/\n  __set_MSPLIM((uint32_t)(&__STACK_LIMIT));\n  __set_PSPLIM((uint32_t)(&__STACK_LIMIT));\n\n/* ToDo: Add stack sealing for Armv8-M based processors */\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL));\n#endif\n\n  SystemInit();                    /* CMSIS System Initialization */\n  __PROGRAM_START();               /* Enter PreMain (C library entry point) */\n}\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wmissing-noreturn\"\n#endif\n\n/*---------------------------------------------------------------------------\n  Hard Fault Handler\n *---------------------------------------------------------------------------*/\nvoid HardFault_Handler(void)\n{\n  while(1);\n}\n\n/*---------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *---------------------------------------------------------------------------*/\nvoid Default_Handler(void)\n{\n  while(1);\n}\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#endif\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c",
    "content": "/*************************************************************************//**\n * @file     system_<Device>.c\n * @brief    CMSIS-Core(M) Device Peripheral Access Layer Source File for\n *           Device <Device>\n * @version  V1.0.0\n * @date     20. January 2021\n *****************************************************************************/\n/*\n * Copyright (c) 2009-2021 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <stdint.h>\n#include \"<Device>.h\"\n\n/* ToDo: Include partition header file if TZ is used */\n#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)\n  #include \"partition_<Device>.h\"\n#endif\n\n\n/*---------------------------------------------------------------------------\n  Define clocks\n *---------------------------------------------------------------------------*/\n/* ToDo: Add here your necessary defines for device initialization\n         following is an example for different system frequencies */\n#define XTAL            (12000000U)       /* Oscillator frequency */\n\n#define SYSTEM_CLOCK    (5 * XTAL)\n\n\n/*---------------------------------------------------------------------------\n  Exception / Interrupt Vector table\n *---------------------------------------------------------------------------*/\nextern const VECTOR_TABLE_Type __VECTOR_TABLE[496];\n\n\n/*---------------------------------------------------------------------------\n  System Core Clock Variable\n *---------------------------------------------------------------------------*/\n/* ToDo: Initialize SystemCoreClock with the system core clock frequency value\n         achieved after system intitialization.\n         This means system core clock frequency after call to SystemInit() */\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Clock Frequency (Core Clock)*/\n\n\n/*---------------------------------------------------------------------------\n  System Core Clock function\n *---------------------------------------------------------------------------*/\nvoid SystemCoreClockUpdate (void)\n{\n/* ToDo: Add code to calculate the system frequency based upon the current\n         register settings.\n         This function can be used to retrieve the system core clock frequeny\n         after user changed register sittings. */\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n\n/*---------------------------------------------------------------------------\n  System initialization function\n *---------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* ToDo: Add code to initialize the system.\n         Do not use global variables because this function is called before\n         reaching pre-main. RW section maybe overwritten afterwards. */\n\n/* ToDo: Initialize VTOR if available */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]);\n#endif\n\n/* ToDo: Enable co-processor if it is used */\n#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \\\n    (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))\n  SCB->CPACR |= ((3U << 10U*2U) |           /* enable CP10 Full Access */\n                 (3U << 11U*2U)  );         /* enable CP11 Full Access */\n#endif\n\n/* ToDo: Initialize SAU if TZ is used */\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  TZ_SAU_Setup();\n#endif\n\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/Device.h",
    "content": "/**************************************************************************//**\n * @file     <Device>.h\n * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File\n * @version  V1.01\n * @date     23. June 2020\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef <Device>_H      /* ToDo: replace '<Device>' with your device name */\n#define <Device>_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* ToDo: replace '<Vendor>' with vendor name; add your doxyGen comment   */\n/** @addtogroup <Vendor>\n  * @{\n  */\n\n\n/* ToDo: replace '<Device>' with device name; add your doxyGen comment   */\n/** @addtogroup <Device>\n  * @{\n  */\n\n\n/** @addtogroup Configuration_of_CMSIS\n  * @{\n  */\n\n\n/* =========================================================================================================================== */\n/* ================                                Interrupt Number Definition                                ================ */\n/* =========================================================================================================================== */\n\ntypedef enum IRQn\n{\n/* =======================================  ARM Cortex-A Specific Interrupt Numbers  ========================================= */\n\n  /* Software Generated Interrupts */\n  SGI0_IRQn                          =  0,      /*!< Software Generated Interrupt  0                                           */\n  SGI1_IRQn                          =  1,      /*!< Software Generated Interrupt  1                                           */\n  SGI2_IRQn                          =  2,      /*!< Software Generated Interrupt  2                                           */\n  SGI3_IRQn                          =  3,      /*!< Software Generated Interrupt  3                                           */\n  SGI4_IRQn                          =  4,      /*!< Software Generated Interrupt  4                                           */\n  SGI5_IRQn                          =  5,      /*!< Software Generated Interrupt  5                                           */\n  SGI6_IRQn                          =  6,      /*!< Software Generated Interrupt  6                                           */\n  SGI7_IRQn                          =  7,      /*!< Software Generated Interrupt  7                                           */\n  SGI8_IRQn                          =  8,      /*!< Software Generated Interrupt  8                                           */\n  SGI9_IRQn                          =  9,      /*!< Software Generated Interrupt  9                                           */\n  SGI10_IRQn                         = 10,      /*!< Software Generated Interrupt 10                                           */\n  SGI11_IRQn                         = 11,      /*!< Software Generated Interrupt 11                                           */\n  SGI12_IRQn                         = 12,      /*!< Software Generated Interrupt 12                                           */\n  SGI13_IRQn                         = 13,      /*!< Software Generated Interrupt 13                                           */\n  SGI14_IRQn                         = 14,      /*!< Software Generated Interrupt 14                                           */\n  SGI15_IRQn                         = 15,      /*!< Software Generated Interrupt 15                                           */\n  \n  /* Private Peripheral Interrupts */\n  VirtualMaintenanceInterrupt_IRQn   = 25,      /*!< Virtual Maintenance Interrupt                                             */\n  HypervisorTimer_IRQn               = 26,      /*!< Hypervisor Timer Interrupt                                                */\n  VirtualTimer_IRQn                  = 27,      /*!< Virtual Timer Interrupt                                                   */ \n  Legacy_nFIQ_IRQn                   = 28,      /*!< Legacy nFIQ Interrupt                                                     */\n  SecurePhyTimer_IRQn                = 29,      /*!< Secure Physical Timer Interrupt                                           */\n  NonSecurePhyTimer_IRQn             = 30,      /*!< Non-Secure Physical Timer Interrupt                                       */\n  Legacy_nIRQ_IRQn                   = 31,      /*!< Legacy nIRQ Interrupt                                                     */ \n\n /* Shared Peripheral Interrupts */\n /* ToDo: add here your device specific external interrupt numbers */\n  <DeviceInterrupt>_IRQn    = 0,                /*!< Device Interrupt                                                          */\n  \n} IRQn_Type;\n\n\n/* =========================================================================================================================== */\n/* ================                           Processor and Core Peripheral Section                           ================ */\n/* =========================================================================================================================== */\n\n/* ===========================  Configuration of the Arm Cortex-A Processor and Core Peripherals  ============================ */\n/* ToDo: set the defines according your Device */\n/* ToDo: define the correct core revision              \n         5U if your device is a CORTEX-A5 device\n         7U if your device is a CORTEX-A7 device\n         9U if your device is a CORTEX-A9 device */\n#define __CORTEX_A                    #U      /*!< Cortex-A# Core                              */\n#define __CA_REV                 0x0000U      /*!< Core revision r0p0                          */\n/* ToDo: define the correct core features for the <Device> */\n#define __FPU_PRESENT                 1U      /*!< Set to 1 if FPU is present                  */\n#define __GIC_PRESENT                 1U      /*!< Set to 1 if GIC is present                  */\n#define __TIM_PRESENT                 1U      /*!< Set to 1 if TIM is present                  */\n#define __L2C_PRESENT                 1U      /*!< Set to 1 if L2C is present                  */\n\n/** @} */ /* End of group Configuration_of_CMSIS */\n\n/* ToDo: include the correct core_ca#.h file\n         core_ca5.h if your device is a CORTEX-A5 device\n         core_ca7.h if your device is a CORTEX-A7 device\n         core_ca9.h if your device is a CORTEX-A9 device */\n#include <core_ca#.h>                         /*!< Arm Cortex-A# processor and core peripherals */\n/* ToDo: include your system_<Device>.h file\n         replace '<Device>' with your device name */\n#include \"system_<Device>.h\"                  /*!< <Device> System */\n\n\n/* ========================================  Start of section using anonymous unions  ======================================== */\n#if   defined (__CC_ARM)\n  #pragma push\n  #pragma anon_unions\n#elif defined (__ICCARM__)\n  #pragma language=extended\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wc11-extensions\"\n  #pragma clang diagnostic ignored \"-Wreserved-id-macro\"\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning 586\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* =========================================================================================================================== */\n/* ================                            Device Specific Peripheral Section                             ================ */\n/* =========================================================================================================================== */\n\n\n/** @addtogroup Device_Peripheral_peripherals\n  * @{\n  */\n\n/* ToDo: add here your device specific peripheral access structure typedefs\n         following is an example for a timer */\n\n/* =========================================================================================================================== */\n/* ================                                            TMR                                            ================ */\n/* =========================================================================================================================== */\n\n\n/**\n  * @brief Timer (TMR)\n  */\n\ntypedef struct\n{                                               /*!< (@ 0x40000000) TIM Structure                                              */\n  __IOM uint32_t   TimerLoad;                   /*!< (@ 0x00000004) Timer Load                                                 */\n  __IM  uint32_t   TimerValue;                  /*!< (@ 0x00000008) Timer Counter Current Value                                */\n  __IOM uint32_t   TimerControl;                /*!< (@ 0x0000000C) Timer Control                                              */\n  __OM  uint32_t   TimerIntClr;                 /*!< (@ 0x00000010) Timer Interrupt Clear                                      */\n  __IM  uint32_t   TimerRIS;                    /*!< (@ 0x00000014) Timer Raw Interrupt Status                                 */\n  __IM  uint32_t   TimerMIS;                    /*!< (@ 0x00000018) Timer Masked Interrupt Status                              */\n  __IM  uint32_t   RESERVED[1];\n  __IOM uint32_t   TimerBGLoad;                 /*!< (@ 0x00000020) Background Load Register                                   */\n} <DeviceAbbreviation>_TMR_TypeDef;\n\n/*@}*/ /* end of group <Device>_Peripherals */\n\n\n/* =========================================  End of section using anonymous unions  ========================================= */\n#if   defined (__CC_ARM)\n  #pragma pop\n#elif defined (__ICCARM__)\n  /* leave anonymous unions enabled */\n#elif (__ARMCC_VERSION >= 6010050)\n  #pragma clang diagnostic pop\n#elif defined (__GNUC__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TMS470__)\n  /* anonymous unions are enabled by default */\n#elif defined (__TASKING__)\n  #pragma warning restore\n#elif defined (__CSMC__)\n  /* anonymous unions are enabled by default */\n#else\n  #warning Not supported compiler type\n#endif\n\n\n/* =========================================================================================================================== */\n/* ================                          Device Specific Peripheral Address Map                           ================ */\n/* =========================================================================================================================== */\n\n\n/* ToDo: add here your device peripherals base addresses\n         following is an example for timer */\n/** @addtogroup Device_Peripheral_peripheralAddr\n  * @{\n  */\n\n/* Peripheral and SRAM base address */\n#define <DeviceAbbreviation>_FLASH_BASE       (0x00000000UL)                              /*!< (FLASH     ) Base Address */\n#define <DeviceAbbreviation>_SRAM_BASE        (0x20000000UL)                              /*!< (SRAM      ) Base Address */\n#define <DeviceAbbreviation>_PERIPH_BASE      (0x40000000UL)                              /*!< (Peripheral) Base Address */\n\n/* Peripheral memory map */\n#define <DeviceAbbreviation>TIM0_BASE         (<DeviceAbbreviation>_PERIPH_BASE)          /*!< (Timer0    ) Base Address */\n#define <DeviceAbbreviation>TIM1_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1    ) Base Address */\n#define <DeviceAbbreviation>TIM2_BASE         (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2    ) Base Address */\n\n/** @} */ /* End of group Device_Peripheral_peripheralAddr */\n\n\n/* =========================================================================================================================== */\n/* ================                                  Peripheral declaration                                   ================ */\n/* =========================================================================================================================== */\n\n\n/* ToDo: add here your device peripherals pointer definitions\n         following is an example for timer */\n/** @addtogroup Device_Peripheral_declaration\n  * @{\n  */\n\n#define <DeviceAbbreviation>_TIM0        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)\n#define <DeviceAbbreviation>_TIM1        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)\n#define <DeviceAbbreviation>_TIM2        ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)\n\n\n/** @} */ /* End of group <Device> */\n\n/** @} */ /* End of group <Vendor> */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* <Device>_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/mem_Device.h",
    "content": "/**************************************************************************//**\n * @file     mem_<Device>.h\n * @brief    CMSIS Cortex-A Memory base and size definitions (used in scatter file)\n * @version  V1.00\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef MEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */\n#define MEM_<Device>_H\n\n/*----------------------------------------------------------------------------\n  User Stack & Heap size definition\n *----------------------------------------------------------------------------*/\n/*\n//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------\n*/\n\n/*--------------------- ROM Configuration ------------------------------------\n//\n// <h> ROM Configuration\n//   <o0> ROM Base Address <0x0-0xFFFFFFFF:8>\n//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __ROM_BASE       0x80000000\n#define __ROM_SIZE       0x00200000\n\n/*--------------------- RAM Configuration -----------------------------------\n// <h> RAM Configuration\n//   <o0> RAM Base Address    <0x0-0xFFFFFFFF:8>\n//   <o1> RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//   <o2> RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//   <o3> ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//   <h> Stack / Heap Configuration\n//     <o4>  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <o5>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     <h> Exceptional Modes\n//       <o6> UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o7> ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o8> SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o9> IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//       <o10> FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n//     </h>\n//   </h>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __RAM_BASE       0x80200000\n#define __RAM_SIZE       0x00200000\n\n#define __RW_DATA_SIZE   0x00100000\n#define __ZI_DATA_SIZE   0x000F0000\n\n#define __STACK_SIZE     0x00001000\n#define __HEAP_SIZE      0x00008000\n\n#define __UND_STACK_SIZE 0x00000100\n#define __ABT_STACK_SIZE 0x00000100\n#define __SVC_STACK_SIZE 0x00000100\n#define __IRQ_STACK_SIZE 0x00000100\n#define __FIQ_STACK_SIZE 0x00000100\n\n/*----------------------------------------------------------------------------*/\n\n/*--------------------- TTB Configuration ------------------------------------\n//\n// <h> TTB Configuration\n//   <o0> TTB Base Address <0x0-0xFFFFFFFF:8>\n//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>\n// </h>\n *----------------------------------------------------------------------------*/\n#define __TTB_BASE       0x80500000\n#define __TTB_SIZE       0x00004000\n\n#endif /* MEM_<Device>_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Include/system_Device.h",
    "content": "/**************************************************************************//**\n * @file     system_<Device>.h\n * @brief    CMSIS Cortex-A Device Peripheral Access Layer\n * @version  V5.00\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef SYSTEM_<Device>_H   /* ToDo: replace '<Device>' with your device name */\n#define SYSTEM_<Device>_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <stdint.h>\n\nextern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */\n\n/**\n  \\brief Setup the microcontroller system.\n\n   Initialize the System and update the SystemCoreClock variable.\n */\nextern void SystemInit (void);\n\n/**\n  \\brief  Update SystemCoreClock variable.\n\n   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.\n */\nextern void SystemCoreClockUpdate (void);\n\n/**\n  \\brief  Create Translation Table.\n\n   Creates Memory Management Unit Translation Table.\n */\nextern void MMU_CreateTranslationTable(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* SYSTEM_<Device>_H */\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/Device.sct",
    "content": "#! armcc -E\n;**************************************************\n; Copyright (c) 2017 ARM Ltd.  All rights reserved.\n;**************************************************\n\n; Scatter-file for Cortex-A\n\n; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.\n\n#include \"mem_<Device>.h\"\n\nSDRAM __ROM_BASE __ROM_SIZE       ; load region size_region\n{\n  VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address\n  {\n      * (RESET, +FIRST)         ; Vector table and other startup code\n      * (InRoot$$Sections)      ; All (library) code that must be in a root region\n      * (+RO-CODE)              ; Application RO code (.text)\n      * (+RO-DATA)              ; Application RO data (.constdata)\n  }\n\n  RW_DATA __RAM_BASE __RW_DATA_SIZE\n  { * (+RW) }                   ; Application RW data (.data)\n\n  ZI_DATA (__RAM_BASE+\n           __RW_DATA_SIZE) __ZI_DATA_SIZE\n  { * (+ZI) }                   ; Application ZI data (.bss)\n \n  ARM_LIB_HEAP (__RAM_BASE\n               +__RW_DATA_SIZE\n               +__ZI_DATA_SIZE)    EMPTY __HEAP_SIZE        ; Heap region growing up\n  { }\n  \n  ARM_LIB_STACK (__RAM_BASE\n                +__RAM_SIZE       \n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE\n                -__UND_STACK_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down\n  { }              \n                \n  UND_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE\n                -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE  ; UND mode stack\n  { }\n\n  ABT_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE\n                -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE  ; ABT mode stack\n  { }\n\n  SVC_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE\n                -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE  ; SVC mode stack\n  { }  \n\n  IRQ_STACK     (__RAM_BASE\n                +__RAM_SIZE\n                -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE  ; IRQ mode stack\n  { }  \n\n  FIQ_STACK     (__RAM_BASE\n                +__RAM_SIZE)       EMPTY -__FIQ_STACK_SIZE  ; FIQ mode stack\n  { }                            \n\n  TTB            __TTB_BASE        EMPTY __TTB_SIZE         ; Level-1 Translation Table for MMU\n  { }                                        \n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/ARM/startup_Device.c",
    "content": "/******************************************************************************\n * @file     startup_<Device>.c\n * @brief    CMSIS Cortex-A Device Startup\n * @version  V1.00\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \"<Device>.h\" /* ToDo: replace '<Device>' with your device name */\n\n/*----------------------------------------------------------------------------\n  Definitions\n *----------------------------------------------------------------------------*/\n#define USR_MODE 0x10            // User mode\n#define FIQ_MODE 0x11            // Fast Interrupt Request mode\n#define IRQ_MODE 0x12            // Interrupt Request mode\n#define SVC_MODE 0x13            // Supervisor mode\n#define ABT_MODE 0x17            // Abort mode\n#define UND_MODE 0x1B            // Undefined Instruction mode\n#define SYS_MODE 0x1F            // System mode\n\n/*----------------------------------------------------------------------------\n  Internal References\n *----------------------------------------------------------------------------*/\nvoid Vectors       (void) __attribute__ ((section(\"RESET\")));\nvoid Reset_Handler (void);\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Handler\n *----------------------------------------------------------------------------*/\nvoid Undef_Handler (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid SVC_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid PAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid DAbt_Handler  (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid IRQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\nvoid FIQ_Handler   (void) __attribute__ ((weak, alias(\"Default_Handler\")));\n\n/*----------------------------------------------------------------------------\n  Exception / Interrupt Vector Table\n *----------------------------------------------------------------------------*/\n__ASM void Vectors(void) {\n  IMPORT Undef_Handler\n  IMPORT SVC_Handler\n  IMPORT PAbt_Handler\n  IMPORT DAbt_Handler\n  IMPORT IRQ_Handler\n  IMPORT FIQ_Handler\n  LDR    PC, =Reset_Handler\n  LDR    PC, =Undef_Handler\n  LDR    PC, =SVC_Handler\n  LDR    PC, =PAbt_Handler\n  LDR    PC, =DAbt_Handler\n  NOP\n  LDR    PC, =IRQ_Handler\n  LDR    PC, =FIQ_Handler\n}\n\n/*----------------------------------------------------------------------------\n  Reset Handler called on controller reset\n *----------------------------------------------------------------------------*/\n__ASM void Reset_Handler(void) {\n\n  // Mask interrupts\n  CPSID   if                           \n\n  // Put any cores other than 0 to sleep\n  MRC     p15, 0, R0, c0, c0, 5       // Read MPIDR\n  ANDS    R0, R0, #3\ngoToSleep\n  WFINE\n  BNE     goToSleep\n\n  // Reset SCTLR Settings\n  MRC     p15, 0, R0, c1, c0, 0       // Read CP15 System Control register\n  BIC     R0, R0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache\n  BIC     R0, R0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache\n  BIC     R0, R0, #0x1                // Clear M bit  0 to disable MMU\n  BIC     R0, R0, #(0x1 << 11)        // Clear Z bit 11 to disable branch prediction\n  BIC     R0, R0, #(0x1 << 13)        // Clear V bit 13 to disable hivecs\n  MCR     p15, 0, R0, c1, c0, 0       // Write value back to CP15 System Control register\n  ISB\n\n  // Configure ACTLR\n  MRC     p15, 0, r0, c1, c0, 1       // Read CP15 Auxiliary Control Register\n  ORR     r0, r0, #(1 <<  1)          // Enable L2 prefetch hint (UNK/WI since r4p1)\n  MCR     p15, 0, r0, c1, c0, 1       // Write CP15 Auxiliary Control Register\n\n  // Set Vector Base Address Register (VBAR) to point to this application's vector table\n  LDR    R0, =Vectors\n  MCR    p15, 0, R0, c12, c0, 0\n\n  // Setup Stack for each exceptional mode\n  IMPORT |Image$$FIQ_STACK$$ZI$$Limit|\n  IMPORT |Image$$IRQ_STACK$$ZI$$Limit|\n  IMPORT |Image$$SVC_STACK$$ZI$$Limit|\n  IMPORT |Image$$ABT_STACK$$ZI$$Limit|\n  IMPORT |Image$$UND_STACK$$ZI$$Limit|\n  IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|\n  CPS    #0x11\n  LDR    SP, =|Image$$FIQ_STACK$$ZI$$Limit|\n  CPS    #0x12\n  LDR    SP, =|Image$$IRQ_STACK$$ZI$$Limit|\n  CPS    #0x13\n  LDR    SP, =|Image$$SVC_STACK$$ZI$$Limit|\n  CPS    #0x17\n  LDR    SP, =|Image$$ABT_STACK$$ZI$$Limit|\n  CPS    #0x1B\n  LDR    SP, =|Image$$UND_STACK$$ZI$$Limit|\n  CPS    #0x1F\n  LDR    SP, =|Image$$ARM_LIB_STACK$$ZI$$Limit|\n\n  // Call SystemInit\n  IMPORT SystemInit\n  BL     SystemInit\n\n  // Unmask interrupts\n  CPSIE  if\n\n  // Call __main\n  IMPORT __main\n  BL     __main\n}\n\n/*----------------------------------------------------------------------------\n  Default Handler for Exceptions / Interrupts\n *----------------------------------------------------------------------------*/\nvoid Default_Handler(void) {\n  while(1);\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/mmu_Device.c",
    "content": "/**************************************************************************//**\n * @file     system_Device.c\n * @brief    MMU Configuration\n *           Device <DeviceAbbreviation>\n * @version  V1.1.0\n * @date     23. November 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Memory map description\n\n   ToDo: add in this file your device memory map description\n         following is an example of a Cortex-A9 Arm FVP device\n\n                                                     Memory Type\n0xFFFFFFFF |--------------------------|             ------------\n           |       FLAG SYNC          |             Device Memory\n0xFFFFF000 |--------------------------|             ------------\n           |         Fault            |                Fault\n0xFFF00000 |--------------------------|             ------------\n           |                          |                Normal\n           |                          |\n           |      Daughterboard       |\n           |         memory           |\n           |                          |\n0x80505000 |--------------------------|             ------------\n           |TTB (L2 Sync Flags   ) 4k |                Normal\n0x80504C00 |--------------------------|             ------------\n           |TTB (L2 Peripherals-B) 16k|                Normal\n0x80504800 |--------------------------|             ------------\n           |TTB (L2 Peripherals-A) 16k|                Normal\n0x80504400 |--------------------------|             ------------\n           |TTB (L2 Priv Periphs)  4k |                Normal\n0x80504000 |--------------------------|             ------------\n           |    TTB (L1 Descriptors)  |                Normal\n0x80500000 |--------------------------|             ------------\n           |           Heap           |                Normal\n           |--------------------------|             ------------\n           |          Stack           |                Normal\n0x80400000 |--------------------------|             ------------\n           |         ZI Data          |                Normal\n0x80300000 |--------------------------|             ------------\n           |         RW Data          |                Normal\n0x80200000 |--------------------------|             ------------\n           |         RO Data          |                Normal\n           |--------------------------|             ------------\n           |         RO Code          |              USH Normal\n0x80000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |      HSB AXI buses       |\n0x40000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x2C002000 |--------------------------|             ------------\n           |     Private Address      |            Device Memory\n0x2C000000 |--------------------------|             ------------\n           |      Daughterboard       |                Fault\n           |  test chips peripherals  |\n0x20000000 |--------------------------|             ------------\n           |       Peripherals        |           Device Memory RW/RO\n           |                          |              & Fault\n0x00000000 |--------------------------|\n*/\n\n// L1 Cache info and restrictions about architecture of the caches (CCSIR register):\n// Write-Through support *not* available\n// Write-Back support available.\n// Read allocation support available.\n// Write allocation support available.\n\n// Note: You should use the Shareable attribute carefully.\n// For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.\n// Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.\n// Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.\n   \n// Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.\n// When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.\n// When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.\n   \n// Following MMU configuration is expected\n// SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)\n// SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)\n// Domain 0 is always the Client domain\n// Descriptors should place all memory in domain 0\n\n#include \"<Device>.h\" /* ToDo: replace '<Device>' with your device name */\n\n// L2 table pointers\n//-----------------------------------------------------\n#define PRIVATE_TABLE_L2_BASE_4k       (0x80504000) //Map 4k Private Address space\n#define SYNC_FLAGS_TABLE_L2_BASE_4k    (0x80504C00) //Map 4k Flag synchronization\n#define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1 \n#define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2 \n\n//--------------------- PERIPHERALS -------------------\n#define PERIPHERAL_A_FAULT             (0x00000000 + 0x1C000000) \n#define PERIPHERAL_B_FAULT             (0x00100000 + 0x1C000000) \n\n//--------------------- SYNC FLAGS --------------------\n#define FLAG_SYNC                       0xFFFFF000\n#define F_SYNC_BASE                     0xFFF00000  //1M aligned\n\n//Import symbols from linker\nextern uint32_t Image$$VECTORS$$Base;\nextern uint32_t Image$$RW_DATA$$Base;\nextern uint32_t Image$$ZI_DATA$$Base;\nextern uint32_t Image$$TTB$$ZI$$Base;\n\nstatic uint32_t Sect_Normal;        // outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0\nstatic uint32_t Sect_Normal_Cod;    // outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Normal_RO;     // as Sect_Normal_Cod, but not executable\nstatic uint32_t Sect_Normal_RW;     // as Sect_Normal_Cod, but writeable and not executable\nstatic uint32_t Sect_Device_RO;     // device, non-shareable, non-executable, ro, domain 0, base addr 0\nstatic uint32_t Sect_Device_RW;     // as Sect_Device_RO, but writeable\n                                       \n/* Define global descriptors */        \nstatic uint32_t Page_L1_4k  = 0x0;  // generic\nstatic uint32_t Page_L1_64k = 0x0;  // generic\nstatic uint32_t Page_4k_Device_RW;  // shared device, not executable, rw, domain 0\nstatic uint32_t Page_64k_Device_RW; // shared device, not executable, rw, domain 0\n\nvoid MMU_CreateTranslationTable(void)\n{\n  mmu_region_attributes_Type region;\n\n  // Create 4GB of faulting entries\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);\n\n  /*\n   * Generate descriptors. Refer to core_ca.h to get information about attributes\n   *\n   */\n  // Create descriptors for Vectors, RO, RW, ZI sections\n  section_normal(Sect_Normal, region);\n  section_normal_cod(Sect_Normal_Cod, region);\n  section_normal_ro(Sect_Normal_RO, region);\n  section_normal_rw(Sect_Normal_RW, region);\n  // Create descriptors for peripherals\n  section_Device_ro(Sect_Device_RO, region);\n  section_Device_rw(Sect_Device_RW, region);\n  // Create descriptors for 64k pages\n  page64k_Device_rw(Page_L1_64k, Page_64k_Device_RW, region);\n  // Create descriptors for 4k pages\n  page4k_Device_rw(Page_L1_4k, Page_4k_Device_RW, region);\n\n  /*\n   *  Define MMU flat-map regions and attributes\n   *\n   */\n  // Define Image\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base     ,    1U, Sect_Normal_Cod);\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base     ,    1U, Sect_Normal_RW);\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base     ,    1U, Sect_Normal_RW);\n\n  // All DRAM executable, RW, cacheable - applications may choose to divide memory into RO executable\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base     , 2043U, Sect_Normal);\n\n  //--------------------- PERIPHERALS -------------------\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_FLASH_BASE0    ,   64U, Sect_Device_RO);\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_FLASH_BASE1    ,   64U, Sect_Device_RO);\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SRAM_BASE      ,   64U, Sect_Device_RW);\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_VRAM_BASE      ,   32U, Sect_Device_RW);\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_ETHERNET_BASE  ,   16U, Sect_Device_RW);\n  MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_USB_BASE       ,   16U, Sect_Device_RW);\n                                                                                \n  // Create (16 * 64k)=1MB faulting entries to cover peripheral range           \n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT                   ,   16U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n  // Define peripheral range                                                    \n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_DAP_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SYSTEM_REG_BASE ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SERIAL_BASE     ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_AACI_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_MMCI_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_KMI0_BASE       ,    2U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_UART_BASE       ,    4U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_WDT_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n                                                                                \n  // Create (16 * 64k)=1MB faulting entries to cover peripheral range           \n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT                   ,   16U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);\n  // Define peripheral range                                                    \n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_TIMER_BASE      ,    2U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_DVI_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_RTC_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_UART4_BASE      ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n  MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_CLCD_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);\n\n  // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory\n  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()                         ,  256U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n  // Define private address space entry\n  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR()                         ,    2U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n  // Define L2CC entry\n  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_L2C_BASE        ,    1U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n  // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)\n  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE                          ,  256U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);\n  // Define synchronization space entry.                       \n  MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC                            ,    1U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);\n\n  /* Set location of level 1 page table\n  ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)\n  ; 13:7  - 0x0\n  ; 6     - IRGN[0] 0x1  (Inner WB WA)\n  ; 5     - NOS     0x0  (Non-shared)\n  ; 4:3   - RGN     0x01 (Outer WB WA)\n  ; 2     - IMP     0x0  (Implementation Defined)\n  ; 1     - S       0x0  (Non-shared)\n  ; 0     - IRGN[1] 0x0  (Inner WB WA) */\n  __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 0x48);\n  __ISB();\n\n  /* Set up domain access control register\n  ; We set domain 0 to Client and all other domains to No Access.\n  ; All translation table entries specify domain 0 */\n  __set_DACR(1);\n  __ISB();\n}\n"
  },
  {
    "path": "external/CMSIS_5/Device/_Template_Vendor/Vendor/Device_A/Source/system_Device.c",
    "content": "/******************************************************************************\n * @file     system_<Device>.c\n * @brief    CMSIS Cortex-A Device Peripheral Access Layer \n * @version  V1.00\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include <stdint.h>\n#include \"<Device>.h\" /* ToDo: replace '<Device>' with your device name */\n#include \"irq_ctrl.h\"\n\n/*----------------------------------------------------------------------------\n  Define clocks\n *----------------------------------------------------------------------------*/\n/* ToDo: add here your necessary defines for device initialization\n         following is an example for different system frequencies */\n#define XTAL            (12000000U)       /* Oscillator frequency             */\n\n#define SYSTEM_CLOCK    (5 * XTAL)\n\n\n/*----------------------------------------------------------------------------\n  System Core Clock Variable\n *----------------------------------------------------------------------------*/\n/* ToDo: initialize SystemCoreClock with the system core clock frequency value\n         achieved after system intitialization.\n         This means system core clock frequency after call to SystemInit() */\nuint32_t SystemCoreClock = SYSTEM_CLOCK;  /* System Clock Frequency (Core Clock)*/\n\n\n\n/*----------------------------------------------------------------------------\n  Clock functions\n *----------------------------------------------------------------------------*/\n\nvoid SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */\n{\n/* ToDo: add code to calculate the system frequency based upon the current\n         register settings.\n         This function can be used to retrieve the system core clock frequeny\n         after user changed register sittings. */\n  SystemCoreClock = SYSTEM_CLOCK;\n}\n\n\n/*----------------------------------------------------------------------------\n  System Initialization\n *----------------------------------------------------------------------------*/\nvoid SystemInit (void)\n{\n/* ToDo: add code to initialize the system\n   Do not use global variables because this function is called before\n   reaching pre-main. RW section may be overwritten afterwards.          */\n  SystemCoreClock = SYSTEM_CLOCK;\n\n  // Invalidate entire Unified TLB\n  __set_TLBIALL(0);\n\n  // Invalidate entire branch predictor array\n  __set_BPIALL(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate instruction cache and flush branch target cache\n  __set_ICIALLU(0);\n  __DSB();\n  __ISB();\n\n  //  Invalidate data cache\n  L1C_InvalidateDCacheAll();\n  \n  // Create Translation Table\n  MMU_CreateTranslationTable();\n\n  // Enable MMU\n  MMU_Enable();\n\n  // Enable Caches\n  L1C_EnableCaches();\n  L1C_EnableBTAC();\n\n#if (__L2C_PRESENT == 1) \n  // Enable GIC\n  L2C_Enable();\n#endif\n\n#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\n  // Enable FPU\n  __FPU_Enable();\n#endif\n\n  // IRQ Initialize\n  IRQ_Initialize();\n}\n"
  },
  {
    "path": "external/CMSIS_5/Jenkinsfile",
    "content": "@Library(\"cmsis\")\nimport com.arm.dsg.cmsis.jenkins.ArtifactoryHelper\n\nDOCKERINFO = [\n    'staging': [\n        'registryUrl': 'mcu--docker-staging.eu-west-1.artifactory.aws.arm.com',\n        'registryCredentialsId': 'artifactory',\n        'k8sPullSecret': 'artifactory-mcu-docker-staging',\n        'namespace': 'mcu--docker-staging',\n        'image': 'cmsis/linux',\n        'label': \"${JENKINS_ENV}-${JOB_BASE_NAME}-${BUILD_NUMBER}\"\n    ],\n    'production': [\n        'registryUrl': 'mcu--docker.eu-west-1.artifactory.aws.arm.com',\n        'registryCredentialsId': 'artifactory',\n        'namespace': 'mcu--docker',\n        'k8sPullSecret': 'artifactory-mcu-docker',\n        'image': 'cmsis/linux',\n        'label': 'latest'\n    ]\n]\nHADOLINT_VERSION = '2.6.0-alpine'\n\ndockerinfo = DOCKERINFO['production']\n\nisPrecommit = (JOB_BASE_NAME == 'pre_commit')\nisPostcommit = (JOB_BASE_NAME == 'post_commit')\nisNightly = (JOB_BASE_NAME == 'nightly')\nisRelease = (JOB_BASE_NAME == 'release')\n\npatternGlobal = [\n    '^Jenkinsfile'\n]\n\npatternDocker = [\n    '^docker/.*'\n]\n\npatternCoreM = [\n    '^CMSIS/Core/Include/.*',\n    '^Device/ARM/ARMCM.*'\n]\n\npatternCoreA = [\n    '^CMSIS/Core_A/Include/.*',\n    '^Device/ARM/ARMCA.*'\n]\n\npatternCoreValidation = [\n    '^CMSIS/CoreValidation/.*'\n]\n\nCONFIGURATIONS = [\n    'pre_commit': [\n        'mdevices': ['CM0', 'CM3', 'CM4FP', 'CM7DP', 'CM23', 'CM33NS', 'CM35PS',\n            'CM55NS', 'CM85S'],\n        'adevices': ['CA7', 'CA9'],\n        'devices' : [],\n        'configs' : [\n            'AC5': ['low', 'tiny'],\n            'AC6': ['low', 'tiny'],\n            'AC6LTM': ['low', 'tiny'],\n            'GCC': ['low', 'tiny']\n        ]\n    ],\n    'post_commit': [\n        'devices' : ['CM0', 'CM0plus', 'CM3', 'CM4', 'CM4FP', 'CM7', 'CM7SP', 'CM7DP',\n            'CM23', 'CM23S', 'CM23NS', 'CM33', 'CM33S', 'CM33NS',\n            'CM35P', 'CM35PS', 'CM35PNS', 'CM55', 'CM55S', 'CM55NS',\n            'CM85S', 'CM85NS',\n            'CA5', 'CA7', 'CA9'],\n        'configs' : [\n            'AC5': ['low', 'tiny'],\n            'AC6': ['low', 'tiny'],\n            'AC6LTM': ['low', 'tiny'],\n            'GCC': ['low', 'tiny']\n        ]\n    ],\n    'nightly': [\n        'devices' : ['CM0', 'CM0plus', 'CM3', 'CM4', 'CM4FP', 'CM7', 'CM7SP', 'CM7DP',\n            'CM23', 'CM23S', 'CM23NS', 'CM33', 'CM33S', 'CM33NS',\n            'CM35P', 'CM35PS', 'CM35PNS', 'CM55', 'CM55S', 'CM55NS',\n            'CM85S', 'CM85NS',\n            'CA5', 'CA7', 'CA9'],\n        'configs' : [\n            'AC5': ['low', 'mid', 'high', 'size', 'tiny'],\n            'AC6': ['low', 'mid', 'high', 'size', 'tiny'],\n            'AC6LTM': ['low', 'mid', 'high', 'size', 'tiny'],\n            'GCC': ['low', 'mid', 'high', 'size', 'tiny']\n        ]\n    ],\n    'release': []\n]\nCONFIGURATION = CONFIGURATIONS[JOB_BASE_NAME]\n\n// ---- PIPELINE CODE ----\n\ndef getChangeset() {\n    def fileset = sh encoding: 'UTF-8', label: '', returnStdout: true, script: 'git diff --name-only HEAD~1..HEAD'\n    return fileset.split('\\n')\n}\n\ndef fileSetMatches(fileset, patternset) {\n    return patternset.any { p ->\n        fileset.any{ f -> f ==~ p }\n    }\n}\n\nFORCE_BUILD = false\nDOCKER_BUILD = isPrecommit || isPostcommit || isNightly\nCORE_VALIDATION = isPrecommit || isPostcommit || isNightly\nCOMMIT = null\nVERSION = null\n\nartifactory = new ArtifactoryHelper(this)\n\npipeline {\n    agent { label 'master' }\n    options {\n        timestamps()\n        timeout(time: 1, unit: 'HOURS')\n        ansiColor('xterm')\n        skipDefaultCheckout()\n    }\n    environment {\n        CI_ACCOUNT          = credentials('grasci')\n        ARTIFACTORY         = credentials('artifactory')\n        USER                = \"${CI_ACCOUNT_USR}\"\n        PASS                = \"${CI_ACCOUNT_PSW}\"\n        ARTIFACTORY_API_KEY = \"${ARTIFACTORY_PSW}\"\n    }\n    stages {\n        stage('Checkout') {\n            steps {\n                script {\n                    COMMIT = checkoutScmWithRetry(3)\n                    echo \"COMMIT: ${COMMIT}\"\n                    VERSION = (sh(returnStdout: true, script: 'git describe --tags --always')).trim()\n                    echo \"VERSION: '${VERSION}'\"\n                }\n\n                stash name: 'dockerfile', includes: 'docker/**'\n            }\n        }\n\n        stage('Analyse') {\n            when {\n                expression { return isPrecommit || isPostcommit }\n                beforeOptions true\n            }\n            steps {\n                script {\n                    def fileset = changeset\n                    def hasGlobal = fileSetMatches(fileset, patternGlobal)\n                    def hasDocker = fileSetMatches(fileset, patternDocker)\n                    def hasCoreM = fileSetMatches(fileset, patternCoreM)\n                    def hasCoreA = fileSetMatches(fileset, patternCoreA)\n                    def hasCoreValidation = fileSetMatches(fileset, patternCoreValidation)\n\necho \"\"\"Change analysis:\n- hasGlobal = ${hasGlobal}\n- hasDocker = ${hasDocker}\n- hasCoreM = ${hasCoreM}\n- hasCoreA = ${hasCoreA}\n- hasCoreValidation = ${hasCoreValidation}\n\"\"\"\n\n                    if (isPrecommit) {\n                        if (hasGlobal || hasDocker || hasCoreM || hasCoreValidation) {\n                            CONFIGURATION['devices'] += CONFIGURATION['mdevices']\n                        }\n                        if (hasGlobal || hasDocker || hasCoreA || hasCoreValidation) {\n                            CONFIGURATION['devices'] += CONFIGURATION['adevices']\n                        }\n                    }\n\n                    DOCKER_BUILD &= hasDocker\n                    CORE_VALIDATION &= hasGlobal || hasDocker || hasCoreM || hasCoreA || hasCoreValidation\n\necho \"\"\"Stage schedule:\n- DOCKER_BUILD = ${DOCKER_BUILD}\n- CORE_VALIDATION = ${CORE_VALIDATION}\n\"\"\"\n                }\n            }\n        }\n\n        stage('Docker Lint') {\n            when {\n                expression { return DOCKER_BUILD }\n                beforeOptions true\n            }\n            agent {\n                kubernetes {\n                    defaultContainer 'hadolint'\n                    slaveConnectTimeout 600\n                    yaml \"\"\"\\\n                        apiVersion: v1\n                        kind: Pod\n                        securityContext:\n                          runAsUser: 1000\n                          runAsGroup: 1000\n                        spec:\n                          imagePullSecrets:\n                            - name: artifactory-mcu-docker\n                          securityContext:\n                            runAsUser: 1000\n                            runAsGroup: 1000\n                          containers:\n                            - name: hadolint\n                              image: mcu--docker.eu-west-1.artifactory.aws.arm.com/hadolint/hadolint:${HADOLINT_VERSION}\n                              alwaysPullImage: true\n                              imagePullPolicy: Always\n                              command:\n                                - sleep\n                              args:\n                                - infinity\n                              resources:\n                                requests:\n                                  cpu: 900m\n                                  memory: 3Gi\n                        \"\"\".stripIndent()\n                }\n            }\n            steps {\n                unstash 'dockerfile'\n\n                sh 'hadolint --format json docker/dockerfile* | tee hadolint.log'\n\n                recordIssues tools: [hadoLint(id: 'hadolint', pattern: 'hadolint.log')],\n                             qualityGates: [[threshold: 1, type: 'DELTA', unstable: true]],\n                             referenceJobName: 'nightly', ignoreQualityGate: true\n            }\n        }\n\n        stage('Docker Build') {\n            when {\n                expression { return (isPrecommit || isPostcommit) && DOCKER_BUILD }\n                beforeOptions true\n            }\n            agent {\n                kubernetes {\n                    defaultContainer 'docker-dind'\n                    slaveConnectTimeout 600\n                    yaml \"\"\"\\\n                        apiVersion: v1\n                        kind: Pod\n                        spec:\n                          imagePullSecrets:\n                            - name: artifactory-mcu-docker\n                          containers:\n                            - name: docker-dind\n                              image: docker:dind\n                              securityContext:\n                                privileged: true\n                              volumeMounts:\n                                - name: dind-storage\n                                  mountPath: /var/lib/docker\n                          volumes:\n                            - name: dind-storage\n                              emptyDir: {}\n                        \"\"\".stripIndent()\n                }\n            }\n            steps {\n                sh('apk add bash curl git')\n                script {\n                    unstash 'dockerfile'\n\n                    dir('docker') {\n                        dockerinfo = DOCKERINFO['staging']\n                        withCredentials([sshUserPrivateKey(credentialsId: 'grasci_with_pk',\n                                keyFileVariable: 'grasciPk',\n                                passphraseVariable: '',\n                                usernameVariable: 'grasciUsername')]) {\n                            sh(\"GIT_SSH_COMMAND='ssh -i $grasciPk -o StrictHostKeyChecking=no' ./getDependencies.sh\")\n                        }\n                        docker.withRegistry(\"https://${dockerinfo['registryUrl']}\", dockerinfo['registryCredentialsId']) {\n                            def image = docker.build(\"${dockerinfo['registryUrl']}/${dockerinfo['image']}:${dockerinfo['label']}\", \"--build-arg DOCKER_REGISTRY=${dockerinfo['registryUrl']} .\")\n                            image.push()\n                        }\n                    }\n                }\n            }\n        }\n\n        stage('Pack') {\n            agent {\n                kubernetes {\n                    defaultContainer 'cmsis'\n                    slaveConnectTimeout 600\n                    yaml \"\"\"\\\n                        apiVersion: v1\n                        kind: Pod\n                        spec:\n                          imagePullSecrets:\n                            - name: ${dockerinfo['k8sPullSecret']}\n                          securityContext:\n                            runAsUser: 1000\n                            runAsGroup: 1000\n                          containers:\n                            - name: cmsis\n                              image: ${dockerinfo['registryUrl']}/${dockerinfo['image']}:${dockerinfo['label']}\n                              alwaysPullImage: true\n                              imagePullPolicy: Always\n                              command:\n                                - sleep\n                              args:\n                                - infinity\n                              resources:\n                                requests:\n                                  cpu: 900m\n                                  memory: 3Gi\n                        \"\"\".stripIndent()\n                }\n            }\n            steps {\n                checkoutScmWithRetry(3)\n                sh('./CMSIS/Utilities/fetch_devtools.sh')\n                sh('./CMSIS/RTOS/RTX/LIB/fetch_libs.sh')\n                sh('./CMSIS/RTOS2/RTX/Library/fetch_libs.sh')\n\n                tee('doxygen.log') {\n                    sh('./CMSIS/DoxyGen/gen_doc.sh')\n                }\n                sh('./CMSIS/Utilities/gen_pack.sh')\n\n                archiveArtifacts artifacts: 'output/ARM.CMSIS.*.pack', allowEmptyArchive: true\n                stash name: 'pack', includes: 'output/ARM.CMSIS.*.pack'\n\n                recordIssues tools: [doxygen(id: 'DOXYGEN', name: 'Doxygen', pattern: 'doxygen.log')],\n                             qualityGates: [[threshold: 1, type: 'DELTA', unstable: true]],\n                             referenceJobName: 'nightly', ignoreQualityGate: true\n            }\n        }\n\n        stage('CoreValidation') {\n            when {\n                expression { return CORE_VALIDATION }\n                beforeOptions true\n            }\n            matrix {\n                axes {\n                    axis {\n                      name 'DEVICE'\n                      values 'CM0', 'CM0plus', 'CM3', 'CM4', 'CM4FP', 'CM7', 'CM7SP', 'CM7DP',\n                             'CM23', 'CM23S', 'CM23NS', 'CM33', 'CM33S', 'CM33NS',\n                             'CM35P', 'CM35PS', 'CM35PNS', 'CM55', 'CM55S', 'CM55NS',\n                             'CA5', 'CA5neon', 'CA7', 'CA7neon', 'CA9', 'CA9neon'\n                    }\n                }\n                stages {\n                    stage('Test') {\n                        when {\n                            expression { return DEVICE in CONFIGURATION['devices'] }\n                            beforeOptions true\n                        }\n                        agent {\n                            kubernetes {\n                                defaultContainer 'cmsis'\n                                slaveConnectTimeout 600\n                                yaml \"\"\"\\\n                                    apiVersion: v1\n                                    kind: Pod\n                                    spec:\n                                      imagePullSecrets:\n                                        - name: ${dockerinfo['k8sPullSecret']}\n                                      securityContext:\n                                        runAsUser: 1000\n                                        runAsGroup: 1000\n                                      containers:\n                                        - name: cmsis\n                                          image: ${dockerinfo['registryUrl']}/${dockerinfo['image']}:${dockerinfo['label']}\n                                          alwaysPullImage: true\n                                          imagePullPolicy: Always\n                                          command:\n                                            - sleep\n                                          args:\n                                            - infinity\n                                          resources:\n                                            requests:\n                                              cpu: 900m\n                                              memory: 3Gi\n                                    \"\"\".stripIndent()\n                            }\n                        }\n                        steps {\n                            checkoutScmWithRetry(3)\n                            dir('CMSIS/CoreValidation/Project') {\n                                script {\n                                    CONFIGURATION['configs'].each { COMPILER, OPTS ->\n                                        tee(\"CV_${COMPILER}_${DEVICE}.log\") {\n                                            sh \"python3 build.py -d ${DEVICE} -c ${COMPILER} -o ${OPTS.join(' -o ')} build run\"\n                                        }\n                                    }\n                                }\n\n                                archiveArtifacts artifacts: 'CoreValidation_*.zip', allowEmptyArchive: true\n                                stash name: \"CV_${DEVICE}\", includes: '*.log, *.junit'\n                            }\n                        }\n                    }\n                }\n            }\n        }\n\n        stage('Results') {\n            when {\n                expression { return CORE_VALIDATION }\n                beforeOptions true\n            }\n            steps {\n                dir('results') {\n                    deleteDir()\n                    script {\n                        CONFIGURATION['devices'].each { unstash \"CV_${it}\" }\n                    }\n\n                    recordIssues tools: [armCc(id: 'AC5', name: 'Arm Compiler 5', pattern: 'CV_AC5_*.log'),\n                                         clang(id: 'AC6', name: 'Arm Compiler 6', pattern: 'CV_AC6_*.log'),\n                                         clang(id: 'AC6LTM', name: 'Arm Compiler 6 LTM', pattern: 'CV_AC6LTM_*.log'),\n                                         gcc(id: 'GCC', name: 'GNU Compiler', pattern: 'CV_GCC_*.log')],\n                                 qualityGates: [[threshold: 1, type: 'DELTA', unstable: true]],\n                                 referenceJobName: 'nightly', ignoreQualityGate: true\n                    xunit([\n                        JUnit(pattern: 'corevalidation_*.junit', failIfNotNew: false, skipNoTestFiles: true)\n                    ])\n                }\n\n            }\n        }\n\n        stage('Docker Promote') {\n            when {\n                expression { return isPostcommit && DOCKER_BUILD }\n                beforeOptions true\n            }\n            agent {\n                kubernetes {\n                    defaultContainer 'docker-dind'\n                    slaveConnectTimeout 600\n                    yaml \"\"\"\\\n                        apiVersion: v1\n                        kind: Pod\n                        spec:\n                          imagePullSecrets:\n                            - name: artifactory-mcu-docker\n                          containers:\n                            - name: docker-dind\n                              image: docker:dind\n                              securityContext:\n                                privileged: true\n                              volumeMounts:\n                                - name: dind-storage\n                                  mountPath: /var/lib/docker\n                          volumes:\n                            - name: dind-storage\n                              emptyDir: {}\n                        \"\"\".stripIndent()\n                }\n            }\n            steps {\n                script {\n                    String postCommitTag = \"${dockerinfo['registryUrl']}/${dockerinfo['image']}:${dockerinfo['label']}\"\n                    String prodCommitTag = \"${DOCKERINFO['production']['registryUrl']}/${DOCKERINFO['production']['image']}:${DOCKERINFO['production']['label']}\"\n\n                    // Pull & retag Docker Staging Container to Production\n                    docker.withRegistry(\"https://${dockerinfo['registryUrl']}\", dockerinfo['registryCredentialsId']) {\n                        def image = docker.image(\"$postCommitTag\")\n                        image.pull()\n                        sh \"docker tag $postCommitTag $prodCommitTag\"\n                    }\n                    // Push to Docker Production\n                    docker.withRegistry(\"https://${DOCKERINFO['production']['registryUrl']}\", DOCKERINFO['production']['registryCredentialsId']) {\n                        def image = docker.image(\"$prodCommitTag\")\n                        image.push()\n                    }\n                }\n            }\n        }\n\n        stage('Release Promote') {\n            when {\n                expression { return isRelease }\n                beforeOptions true\n            }\n            steps {\n                unstash name: 'pack'\n                dir('output') {\n                    script {\n                        artifactory.upload pattern: 'ARM.CMSIS.*.pack',\n                                           target: \"mcu.promoted/CMSIS_5/${VERSION}/\",\n                                           props: \"GIT_COMMIT=${COMMIT['GIT_COMMIT']}\"\n                    }\n                    withCredentials([string(credentialsId: 'grasci_github', variable: 'ghtoken')]) {\n                        sh \"\"\"\n                            curl -XPOST \\\n                                -H \"Authorization:token ${ghtoken}\" \\\n                                -H \"Content-Type:application/octet-stream\" \\\n                                --data-binary @ARM.CMSIS.${VERSION}.pack \\\n                                https://uploads.github.com/repos/ARM-software/CMSIS_5/releases/${VERSION}/assets?name=ARM.CMSIS.${VERSION}.pack\n                        \"\"\"\n                    }\n                }\n            }\n        }\n    }\n}\n"
  },
  {
    "path": "external/CMSIS_5/LICENSE.txt",
    "content": "                                 Apache License\n                           Version 2.0, January 2004\n                        http://www.apache.org/licenses/\n\n   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION\n\n   1. Definitions.\n\n      \"License\" shall mean the terms and conditions for use, reproduction,\n      and distribution as defined by Sections 1 through 9 of this document.\n\n      \"Licensor\" shall mean the copyright owner or entity authorized by\n      the copyright owner that is granting the License.\n\n      \"Legal Entity\" shall mean the union of the acting entity and all\n      other entities that control, are controlled by, or are under common\n      control with that entity. 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The text should be enclosed in the appropriate\n      comment syntax for the file format. We also recommend that a\n      file or class name and description of purpose be included on the\n      same \"printed page\" as the copyright notice for easier\n      identification within third-party archives.\n\n   Copyright {yyyy} {name of copyright owner}\n\n   Licensed under the Apache License, Version 2.0 (the \"License\");\n   you may not use this file except in compliance with the License.\n   You may obtain a copy of the License at\n\n       http://www.apache.org/licenses/LICENSE-2.0\n\n   Unless required by applicable law or agreed to in writing, software\n   distributed under the License is distributed on an \"AS IS\" BASIS,\n   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n   See the License for the specific language governing permissions and\n   limitations under the License.\n"
  },
  {
    "path": "external/CMSIS_5/README.md",
    "content": "# CMSIS Version 5\n\n[![Version](https://img.shields.io/github/v/release/arm-software/CMSIS_5)](https://github.com/ARM-software/CMSIS_5/releases/latest) [![License](https://img.shields.io/github/license/arm-software/CMSIS_5)](https://arm-software.github.io/CMSIS_5/General/html/LICENSE.txt)\n\nThe branch *master* of this GitHub repository contains ![Version](https://img.shields.io/github/v/release/arm-software/CMSIS_5?display_name=release&label=%20&sort=semver).\nThe [documentation](http://arm-software.github.io/CMSIS_5/General/html/index.html) is available under http://arm-software.github.io/CMSIS_5/General/html/index.html\n\nUse [Issues](https://github.com/ARM-software/CMSIS_5#issues-and-labels) to provide feedback and report problems for CMSIS Version 5.\n\n**Note:** The branch *develop* of this GitHub repository reflects our current state of development and is constantly updated. It gives our users and partners contiguous access to the CMSIS development. It allows you to review the work and provide feedback or create pull requests for contributions.\n\nA [pre-built documentation](https://arm-software.github.io/CMSIS_5/develop/General/html/index.html) is updated from time to time, but may be also generated using the instructions under [Generate CMSIS Pack for Release](https://github.com/ARM-software/CMSIS_5#generate-cmsis-pack-for-release).\n\n## Overview of CMSIS Components\n\nThe following is an list of all CMSIS components that are available.\n\n| CMSIS-... | Target Processors   | Description  |\n|:----------|:--------------------|:-------------|\n|[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html)  | All Cortex-M, SecurCore | Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions.|\n|[Core(A)](http://arm-software.github.io/CMSIS_5/Core_A/html/index.html)| Cortex-A5/A7/A9 | API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals.|\n|[Driver](http://arm-software.github.io/CMSIS_5/Driver/html/index.html) | All Cortex-M, SecurCore | Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces.|\n|[NN](http://arm-software.github.io/CMSIS_5/NN/html/index.html)        | All Cortex-M | Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores.|\n|[RTOS v1](http://arm-software.github.io/CMSIS_5/RTOS/html/index.html) | Cortex-M0/M0+/M3/M4/M7 | Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems.|\n|[RTOS v2](http://arm-software.github.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. |\n|[Pack](http://arm-software.github.io/CMSIS_5/Pack/html/index.html)    | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM). <br/>Is part of the [Open CMSIS Pack project](https://www.open-cmsis-pack.org). |\n|[Build](http://arm-software.github.io/CMSIS_5/Build/html/index.html)  | All Cortex-M, SecurCore, Cortex-A5/A7/A9 | A set of tools, software frameworks, and work flows that improve productivity, for example with Continuous Integration (CI) support.<br/>Is replaced with the [CMSIS-Toolbox](https://github.com/Open-CMSIS-Pack/devtools/tree/main/tools). |\n|[SVD](http://arm-software.github.io/CMSIS_5/SVD/html/index.html)      | All Cortex-M, SecurCore | Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files.|\n|[DAP](http://arm-software.github.io/CMSIS_5/DAP/html/index.html)      | All Cortex | Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. |\n|[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html)    | All Cortex-M | Defines methods to describe system resources and to partition these resources into multiple projects and execution areas. |\n\n**Note:** CMSIS-DSP moved off into its [own repository](https://github.com/ARM-software/CMSIS-DSP), see below.\n\n## Other related GitHub repositories\n\n| Repository                  | Description                                               |\n|:--------------------------- |:--------------------------------------------------------- |\n| [cmsis-pack-eclipse](https://github.com/ARM-software/cmsis-pack-eclipse)    |  CMSIS-Pack Management for Eclipse reference implementation Pack support  |\n| [CMSIS-FreeRTOS](https://github.com/arm-software/CMSIS-FreeRTOS)            | CMSIS-RTOS adoption of FreeRTOS                                                      |\n| [CMSIS-Driver](https://github.com/arm-software/CMSIS-Driver)                | Generic MCU driver implementations and templates for Ethernet MAC/PHY and Flash.  |\n| [CMSIS-Driver_Validation](https://github.com/ARM-software/CMSIS-Driver_Validation) | CMSIS-Driver Validation can be used to verify CMSIS-Driver in a user system |\n| [CMSIS-DSP](https://github.com/ARM-software/CMSIS-DSP)                      | DSP library collection with hundreds of functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Armv7E-M and later devices. |\n| [CMSIS-Zone](https://github.com/ARM-software/CMSIS-Zone)                    | CMSIS-Zone Utility along with example projects and FreeMarker templates         |\n| [NXP_LPC](https://github.com/ARM-software/NXP_LPC)                          | CMSIS Driver Implementations for the NXP LPC Microcontroller Series       |\n| [mdk-packs](https://github.com/mdk-packs)                                   | IoT cloud connectors as trail implementations for MDK (help us to make it generic)|\n| [trustedfirmware.org](https://www.trustedfirmware.org/)                     | Arm Trusted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.|\n\n\n## Directory Structure\n\n| Directory            | Content                                                   |\n|:-------------------- |:--------------------------------------------------------- |\n| CMSIS/Core           | CMSIS-Core(M) related files (for release)                 |\n| CMSIS/Core_A         | CMSIS-Core(A) related files (for release)                 |\n| CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release)  |\n| CMSIS/DAP            | CMSIS-DAP related files and examples                      |\n| CMSIS/Driver         | CMSIS-Driver API headers and template files               |\n| CMSIS/NN             | CMSIS-NN related files                                    |\n| CMSIS/RTOS           | RTOS v1 related files (for Cortex-M)                      |\n| CMSIS/RTOS2          | RTOS v2 related files (for Cortex-M & Armv8-M)            |\n| CMSIS/Pack           | CMSIS-Pack examples and tutorials                         |\n| CMSIS/DoxyGen        | Source of the documentation                               |\n| CMSIS/Utilities      | Utility programs                                          |\n\n## Generate CMSIS Pack for Release\n\nThis GitHub development repository lacks pre-built libraries of various software components (RTOS, RTOS2).\nIn order to generate a full pack one needs to have the build environment available to build these libraries.\nThis causes some sort of inconvenience. Hence the pre-built libraries may be moved out into separate pack(s)\nin the future.\n\nTo build a complete CMSIS pack for installation the following additional tools are required:\n - **doxygen.exe**    Version: 1.8.6 (Documentation Generator)\n - **mscgen.exe**     Version: 0.20  (Message Sequence Chart Converter)\n - **7z.exe (7-Zip)** Version: 16.02 (File Archiver)\n\nUsing these tools, you can generate on a Windows PC:\n - **CMSIS Documentation** using the batch file **gen_doc.sh** (located in ./CMSIS/Doxygen).\n - **CMSIS Software Pack** using the batch file **gen_pack.sh** (located in ./CMSIS/Utilities).\n   The bash script does not generate the documentation. The pre-built libraries for RTX4 and RTX5\n   are not included within this repository.\n\nThe file ./CMSIS/DoxyGen/How2Doc.txt describes the rules for creating API documentation.\n\n## License\n\nArm CMSIS is licensed under Apache 2.0.\n\n## Contributions and Pull Requests\n\nContributions are accepted under Apache 2.0. Only submit contributions where you have authored all of the code.\n\n### Issues and Labels\n\nPlease feel free to raise an [issue on GitHub](https://github.com/ARM-software/CMSIS_5/issues)\nto report misbehavior (i.e. bugs) or start discussions about enhancements. This\nis your best way to interact directly with the maintenance team and the community.\nWe encourage you to append implementation suggestions as this helps to decrease the\nworkload of the very limited maintenance team.\n\nWe will be monitoring and responding to issues as best we can.\nPlease attempt to avoid filing duplicates of open or closed items when possible.\nIn the spirit of openness we will be tagging issues with the following:\n\n- **bug** – We consider this issue to be a bug that will be investigated.\n\n- **wontfix** - We appreciate this issue but decided not to change the current behavior.\n\n- **enhancement** – Denotes something that will be implemented soon.\n\n- **future** - Denotes something not yet schedule for implementation.\n\n- **out-of-scope** - We consider this issue loosely related to CMSIS. It might by implemented outside of CMSIS. Let us know about your work.\n\n- **question** – We have further questions to this issue. Please review and provide feedback.\n\n- **documentation** - This issue is a documentation flaw that will be improved in future.\n\n- **review** - This issue is under review. Please be patient.\n\n- **DONE** - We consider this issue as resolved - please review and close it. In case of no further activity this issues will be closed after a week.\n\n- **duplicate** - This issue is already addressed elsewhere, see comment with provided references.\n\n- **Important Information** - We provide essential information regarding planned or resolved major enhancements.\n\n"
  },
  {
    "path": "external/CMSIS_5/docker/dockerfile",
    "content": "# Due to bandwidth limitation, we need to keep the base image into our\n# Artifactory Docker Registry. Because we have more than one registry,\n# we need to set during build time which Artifactory Docker Registry to use.\nARG DOCKER_REGISTRY\nFROM ${DOCKER_REGISTRY}/ubuntu:focal\n\n# jenkins user needs to be present to work on CI\n# User 1000 for Kubernetes\nRUN useradd -u 1000 -U -m -c Jenkins jenkins\n\n# install packages from official Ubuntu repo\nENV DEBIAN_FRONTEND=noninteractive\n# hadolint ignore=DL3008\nRUN apt-get update && \\\n    apt-get install --no-install-recommends -y \\\n        bc \\\n        build-essential \\\n        curl \\\n        dos2unix \\\n        git \\\n        lib32stdc++6 \\\n        mscgen \\\n        p7zip-full \\\n        python3 \\\n        python3-pip \\\n        tar \\\n        unzip \\\n        wget \\\n        libxml2-utils \\\n        zip && \\\n    apt-get autoremove -y && \\\n    apt-get autoclean -y && \\\n    rm -rf /var/lib/apt/lists/*\n\n# Create build ARGs for installer files & versions\nARG ARMCC=ArmCompiler-5.06u7-linux.sh\nARG ARMCLANG=ArmCompiler-6.16-linux-x86_64.sh\nARG ARMCLANGLTM=ArmCompiler-6.6.4-linux-x86_64.sh\nARG GCC=gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2\nARG DOXYGEN=doxygen_1.8.6-2_amd64.deb\nARG FASTMODELS=fvp-11.12-linux-x86_64.tar.gz\n\n# Including dependency folder\nARG DEPENDENCIESFOLDER=dependenciesFiles\nARG TOOLS_PATH=/opt\nARG INSTALLER_PATH=/tmp/dependenciesFiles\nRUN mkdir -p ${INSTALLER_PATH}\nCOPY dependenciesFiles/ ${INSTALLER_PATH}\n\n# install & setup armcc\nRUN ${INSTALLER_PATH}/${ARMCC} --i-agree-to-the-contained-eula --no-interactive -v -d ${TOOLS_PATH}/armcc\nENV PATH=${PATH}:${TOOLS_PATH}/armcc/bin\nENV CI_ARMCC5_TOOLCHAIN_ROOT=${TOOLS_PATH}/armclang/bin\n\n# install & setup armclang\nRUN ${INSTALLER_PATH}/${ARMCLANG} --i-agree-to-the-contained-eula --no-interactive -v -d ${TOOLS_PATH}/armclang\nENV PATH=${PATH}:${TOOLS_PATH}/armclang/bin\nENV CI_ARMCC6_TOOLCHAIN_ROOT=${TOOLS_PATH}/armclang/bin\n\n# install & setup armclang ltm\nRUN ${INSTALLER_PATH}/${ARMCLANGLTM} --i-agree-to-the-contained-eula --no-interactive -v -d ${TOOLS_PATH}/armclangltm\nENV CI_ARMCC6LTM_TOOLCHAIN_ROOT=${TOOLS_PATH}/armclangltm/bin\n\n# install & setup gcc\nRUN mkdir -p ${TOOLS_PATH}\nWORKDIR ${TOOLS_PATH}\nRUN tar -xvf ${INSTALLER_PATH}/${GCC}\nENV PATH=${PATH}:${TOOLS_PATH}/gcc-arm-none-eabi-10-2020-q4-major/bin\nENV CI_GCC_TOOLCHAIN_ROOT=${TOOLS_PATH}/gcc-arm-none-eabi-10-2020-q4-major/bin\nWORKDIR /\n\n# install fast models 11.12\nRUN mkdir -p ${TOOLS_PATH}/fvp/\nWORKDIR ${TOOLS_PATH}/fvp/\nRUN tar -xvf ${INSTALLER_PATH}/${FASTMODELS}\nENV PATH=${PATH}:${TOOLS_PATH}/fvp\nWORKDIR /\n\n# install doxygen\nRUN dpkg -i ${INSTALLER_PATH}/${DOXYGEN}\n\n# install PackChk\nRUN cp ${INSTALLER_PATH}/PackChk /usr/local/bin/PackChk\nRUN chmod +x /usr/local/bin/PackChk\n\n# install Python requirements\nCOPY requirements.txt ${INSTALLER_PATH}/\n# hadolint ignore=DL3013\nRUN python3 -m pip install -U --no-cache-dir pip && \\\n    python3 -m pip install -U --no-cache-dir -r ${INSTALLER_PATH}/requirements.txt\n\n# install buildtools\nRUN python3 -m pip install --no-cache-dir -r ${INSTALLER_PATH}/buildtools/requirements.txt\nRUN mv ${INSTALLER_PATH}/buildtools ${TOOLS_PATH}\nCOPY rtebuild /home/jenkins/.rtebuild\nCOPY rtebuild /root/.rtebuild\nENV PATH=${PATH}:${TOOLS_PATH}/buildtools\n\n# set ARMLMD_LICENSE_FILE for ARM compilers\nENV ARMLMD_LICENSE_FILE=\"7010@euhpc-lic-armlmd.euhpc.arm.com:7010@euhpc-lic03.euhpc.arm.com:7010@euhpc-lic05.euhpc.arm.com:7010@euhpc-lic07.euhpc.arm.com\"\n\n# remove dependency folder\nRUN rm -rf ${INSTALLER_PATH}\n\nCMD [\"bash\"]"
  },
  {
    "path": "external/CMSIS_5/docker/dockerfile.gnu",
    "content": "# Due to bandwidth limitation, we need to keep the base image into our\n# Artifactory Docker Registry. Because we have more than one registry,\n# we need to set during build time which Artifactory Docker Registry to use.\nARG DOCKER_REGISTRY\nFROM ${DOCKER_REGISTRY}/ubuntu:focal\n\n# install packages from official Ubuntu repo\nENV DEBIAN_FRONTEND=noninteractive\n# hadolint ignore=DL3008\nRUN apt-get update && \\\n    apt-get install --no-install-recommends -y \\\n        bc \\\n        build-essential \\\n        curl \\\n        dos2unix \\\n        git \\\n        lib32stdc++6 \\\n        mscgen \\\n        p7zip-full \\\n        python3 \\\n        python3-pip \\\n        tar \\\n        unzip \\\n        wget \\\n        libxml2-utils \\\n        zip && \\\n    apt-get autoremove -y && \\\n    apt-get autoclean -y && \\\n    rm -rf /var/lib/apt/lists/*\n\n# Create build ARGs for installer files & versions\nARG GCC=gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2\n\n# Including dependency folder\nARG DEPENDENCIESFOLDER=dependenciesFiles\nARG TOOLS_PATH=/opt\nARG INSTALLER_PATH=/tmp/dependenciesFiles\nRUN mkdir -p ${INSTALLER_PATH}\nCOPY dependenciesFiles/${GCC} ${INSTALLER_PATH}/${GCC}\nCOPY dependenciesFiles/buildtools ${TOOLS_PATH}/buildtools\n\n# install & setup gcc\nRUN mkdir -p ${TOOLS_PATH}\nWORKDIR ${TOOLS_PATH}\nRUN tar -xvf ${INSTALLER_PATH}/${GCC}\nENV PATH=${PATH}:${TOOLS_PATH}/gcc-arm-none-eabi-10-2020-q4-major/bin\nENV CI_GCC_TOOLCHAIN_ROOT=${TOOLS_PATH}/gcc-arm-none-eabi-10-2020-q4-major/bin\nWORKDIR /\n\n# install Python requirements\nCOPY requirements.txt ${INSTALLER_PATH}/\n# hadolint ignore=DL3013\nRUN python3 -m pip install -U --no-cache-dir pip && \\\n    python3 -m pip install -U --no-cache-dir -r ${INSTALLER_PATH}/requirements.txt\n\n# install buildtools\nRUN python3 -m pip install --no-cache-dir -r ${TOOLS_PATH}/buildtools/requirements.txt\nCOPY rtebuild /root/.rtebuild\nENV PATH=${PATH}:${TOOLS_PATH}/buildtools\n\n# remove dependency folder\nRUN rm -rf ${INSTALLER_PATH}\n\nCMD [\"bash\"]"
  },
  {
    "path": "external/CMSIS_5/docker/getDependencies.sh",
    "content": "#!/bin/bash\n\n# local variables\nDEPENDENCIES_FOLDER=dependenciesFiles\nARTIFACTORY_URL=https://eu-west-1.artifactory.aws.arm.com:443/artifactory\nARTIFACTORY_DEPOT=mcu.depot/ci/depot\nPACKCHK_VERSION=1.3.93\n\nif [ -z \"$ARTIFACTORY_API_KEY\" ]; then\n    echo \"Please set your Artifactory ARTIFACTORY_API_KEY\"\n    exit 1\nfi\n\nif [ -z \"$USER\" ]; then\n    echo \"Please set your short ARM user e.g. sampel01\"\n    exit 1\nfi\n\nfunction downloadFromArtifactory {\n    filename=$(basename $1)\n    echo \"Fetching ${filename} ...\"\n    if [[ -f \"${filename}\" ]]; then\n        sha256sum=$(curl -s -I -H \"X-JFrog-Art-Api:$ARTIFACTORY_API_KEY\" \"${ARTIFACTORY_URL}/${1}\" | grep \"X-Checksum-Sha256\" | cut -d\" \" -f2)\n        if echo \"${sha256sum} *${filename}\" | sha256sum -c --status; then\n            echo \" ... already up to date\"\n        else\n            rm ${filename}\n        fi\n    fi\n    if [[ ! -f \"${filename}\" ]]; then\n        curl -C - -H \"X-JFrog-Art-Api:$ARTIFACTORY_API_KEY\" -O \"${ARTIFACTORY_URL}/${1}\"\n        chmod +x ${filename}\n    fi\n}\n\nfunction downloadFromDepot {\n    downloadFromArtifactory \"${ARTIFACTORY_DEPOT}/${1}\"\n}\n\nfunction gitClone {\n    echo \"Cloning/updating ${2} ...\"\n    if [[ ! -d \"${2}\" ]]; then\n        git clone -b $3 $1 $2\n    else\n        pushd $2\n        git clean -fdx\n        git checkout -f $3\n        git pull origin $3\n        popd\n    fi\n}\n\nmkdir -p $DEPENDENCIES_FOLDER\npushd $DEPENDENCIES_FOLDER || exit\n\ndownloadFromDepot \"doxygen_1.8.6-2_amd64.deb\"\ndownloadFromDepot \"ArmCompiler-5.06u7-linux.sh\"\ndownloadFromDepot \"ArmCompiler-6.16-linux-x86_64.sh\"\ndownloadFromDepot \"ArmCompiler-6.6.4-linux-x86_64.sh\"\ndownloadFromDepot \"gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2\"\ndownloadFromDepot \"fvp-11.12-linux-x86_64.tar.gz\"\ndownloadFromArtifactory \"mcu.promoted/staging/devtools/tools/packchk/${PACKCHK_VERSION}/linux64/PackChk\"\n\ngitClone \"ssh://${USER}@eu-gerrit-1.euhpc.arm.com:29418/dsg/cmsis/buildtools\" \"buildtools\" \"master\"\n\npopd || exit\n"
  },
  {
    "path": "external/CMSIS_5/docker/requirements.txt",
    "content": "gcovr~=4.2\njunit-xml~=1.9\njira~=2.0\njunitparser~=1.4\nJinja2~=2.11\npython-matrix-runner~=1.0\n"
  },
  {
    "path": "external/CMSIS_5/docker/rtebuild/armcc.rtebuild",
    "content": "toolchain:\n  ARMCC5:\n    env:\n      PATH     : [ \"/opt/armcc/bin\" ]\n    rte:\n      Tcompiler: \"ARMCC\"\n      Toptions : \"AC5\"\n    ccompiler:\n      cmd     : \"armcc\"\n      cmdfile : \"--via \\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"-D\"\n    assembler:\n      cmd     : \"armasm\"\n      cmdfile : \"--via \\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"--pd \\\"%{str.join(' SETA ', (str.split(value, '=') + [ '1' ])[0:2])}\\\"\"\n    linker:\n      cmd     : \"armlink\"\n      cmdfile : \"--via \\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      script  : \"--scatter=\\\"\"\n"
  },
  {
    "path": "external/CMSIS_5/docker/rtebuild/armclang.rtebuild",
    "content": "toolchain:\n  ARMCC6:\n    env:\n      PATH     : [ \"/opt/armclang/bin\" ]\n    rte:\n      Tcompiler: \"ARMCC\"\n      Toptions : \"AC6\"\n    ccompiler:\n      cmd     : \"armclang\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"-D\"\n    assembler:\n      cmd     : \"armclang\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"-D\"\n    linker:\n      cmd     : \"armclang\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      script  : \"-Wl,--scatter=\\\"\"\n    librarian:\n      cmd     : \"armar\"\n      cmdfile : \"--Via \\\"\"\n      input   : \"\\\"\"\n      output  : \"--create \\\"\"\n  ARMCC6_MDK:\n    env:\n      PATH             : [ \"/opt/armclang/bin\" ]\n    rte:\n      Tcompiler: \"ARMCC\"\n      Toptions : \"AC6\"\n    ccompiler:\n      cmd     : \"armclang\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"-D\"\n    assembler:\n      cmd     : \"armasm\"\n      cmdfile : \"--Via \\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"--pd \\\"%{value.replace('=', ' SETA ') if '=' in value else value+' SETA 1'}\\\"\"\n    linker:\n      cmd     : \"armlink\"\n      cmdfile : \"--Via \\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      script  : \"--scatter=\\\"\"\n    librarian:\n      cmd     : \"armar\"\n      cmdfile : \"--Via \\\"\"\n      input   : \"\\\"\"\n      output  : \"--create \\\"\"\n"
  },
  {
    "path": "external/CMSIS_5/docker/rtebuild/armclang_ltm.rtebuild",
    "content": "toolchain:\n  ARMCC6_LTM:\n    env:\n      PATH             : [ \"/opt/armclangltm/bin\" ]\n    rte:\n      Tcompiler: \"ARMCC\"\n      Toptions : \"AC6\"\n    ccompiler:\n      cmd     : \"armclang\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"-D\"\n    assembler:\n      cmd     : \"armclang\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"-D\"\n    linker:\n      cmd     : \"armclang\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      script  : \"-Wl,--scatter=\\\"\"\n    librarian:\n      cmd     : \"armar\"\n      cmdfile : \"--Via \\\"\"\n      input   : \"\\\"\"\n      output  : \"--create \\\"\"\n  ARMCC6_LTM_MDK:\n    env:\n      PATH             : [ \"/opt/armclangltm/bin\" ]\n    rte:\n      Tcompiler: \"ARMCC\"\n      Toptions : \"AC6\"\n    ccompiler:\n      cmd     : \"armclang\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"-D\"\n    assembler:\n      cmd     : \"armasm\"\n      cmdfile : \"--Via \\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"--pd \\\"%{value.replace('=', ' SETA ') if '=' in value else value+' SETA 1'}\\\"\"\n    linker:\n      cmd     : \"armlink\"\n      cmdfile : \"--Via \\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      script  : \"--scatter=\\\"\"\n    librarian:\n      cmd     : \"armar\"\n      cmdfile : \"--Via \\\"\"\n      input   : \"\\\"\"\n      output  : \"--create \\\"\"\n"
  },
  {
    "path": "external/CMSIS_5/docker/rtebuild/gcc.rtebuild",
    "content": "toolchain:\n  GCC:\n    env:\n      PATH     : [ \"/opt/gcc-arm-none-eabi-10-2020-q4-major/bin\" ]\n    rte:\n      Tcompiler: \"GCC\"\n      Toptions : \"\"\n    ccompiler:\n      cmd     : \"arm-none-eabi-gcc\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"-D\"\n    assembler:\n      cmd     : \"arm-none-eabi-gcc\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      include : \"-I\\\"\"\n      define  : \"-D\"\n    linker:\n      cmd     : \"arm-none-eabi-gcc\"\n      cmdfile : \"@\\\"\"\n      input   : \"\\\"\"\n      output  : \"-o \\\"\"\n      script  : \"-T \\\"\"\n"
  },
  {
    "path": "external/CMSIS_5/docker/rtebuild/toolchain.rtebuild",
    "content": "packdir: ${home}/.rtebuild/PACK\nimport:\n - armcc.rtebuild\n - armclang.rtebuild\n - armclang_ltm.rtebuild\n - gcc.rtebuild\n"
  },
  {
    "path": "external/CMSIS_5/linter.py",
    "content": "# -*- coding: utf-8 -*-\n\nimport logging\nimport lxml\nimport os\nimport os.path\nimport re\nimport requests\n\nfrom AdvancedHTMLParser import AdvancedHTMLParser\nfrom glob import iglob\nfrom urllib.parse import urlparse\n\nfrom cmsis.PackLint import PackLinter, VersionParser\nfrom cmsis.Pack import Pack, Api, SemanticVersion\n\ndef create():\n  return CmsisPackLinter()\n\nclass CmsisPackVersionParser(VersionParser):\n  def __init__(self, logger = None):\n    super().__init__(logger)\n    self._packs = {}\n\n  def _file_version_(self, file):\n    v = self._regex_(file, \".*@version\\s+([vV])?([0-9]+[.][0-9]+([.][0-9]+)?).*\", 2)\n    if not v:\n      v = self._regex_(file, \".*\\$Revision:\\s+([vV])?([0-9]+[.][0-9]+([.][0-9]+)?).*\", 2)\n    return v\n  \n  def _cmtable_(self, file, skip = 0):\n    table = \"\"\n    dump = False\n    with open(file, 'r') as f:\n      for l in f:\n        if not dump and l.strip() == \"<table class=\\\"cmtable\\\" summary=\\\"Revision History\\\">\":\n          if skip > 0:\n            skip -= 1\n          else:\n            dump = True\n        if dump:\n          table += l.replace(\"<br>\", \"\\\\n\").replace(\"\\\\<\", \"&lt;\").replace(\"\\\\>\", \"&gt;\")\n          if l.strip() == \"</table>\":\n            break\n    if table:\n      table = lxml.etree.fromstring(table)\n      return table\n    return None\n    \n  def _revhistory_(self, file, skip = 0):\n    table = self._cmtable_(file, skip)\n    if table is not None:\n      m = re.match(\"[Vv]?(\\d+.\\d+(.\\d+)?)\", table[1][0].text)\n      if m:\n        return SemanticVersion(m.group(1))\n    else:\n      self._logger.info(\"Revision History table not found in \"+file)\n    return None\n\n  def readme_md(self, file):\n    \"\"\"Get the latest release version from README.md\"\"\"\n    return self._regex_(file, \".*repository contains the CMSIS Version ([0-9]+[.][0-9]+([.][0-9]+)?).*\")\n\n  def _dxy(self, file):\n    \"\"\"Get the PROJECT_NUMBER from a Doxygen configuration file.\"\"\"\n    return self._regex_(file, \"PROJECT_NUMBER\\s*=\\s*\\\"(Version\\s+)?(\\d+.\\d+(.\\d+)?)\\\"\", 2)\n    \n  def _pdsc(self, file, component = None):\n    pack = None\n    if not file in self._packs:\n      pack = Pack(file, None)\n      self._packs[file] = pack\n    else:\n      pack = self._packs[file]\n    if component:\n      history = pack.history()\n      for r in sorted(history.keys(), reverse=True):\n        m = re.search(re.escape(component)+\"(:)?\\s+[Vv]?(\\d+.\\d+(.\\d+)?)\", history[r], re.MULTILINE)\n        if m:\n          return SemanticVersion(m.group(2))\n    else:\n      return pack.version()\n\n  def _h(self, file):\n    return self._file_version_(file)\n\n  def _c(self, file):\n    return self._file_version_(file)\n\n  def _s(self, file):\n    return self._file_version_(file)\n    \n  def _xsd(self, file, rev=False, history=False):\n    if rev:\n      return self._all_(file)\n    elif history:\n      return self._regex_(file, \".*[0-9]+\\. [A-Z][a-z]+ [12][0-9]+: (v)?(\\d+.\\d+(.\\d+)?).*\", 2)\n    else:\n      xsd = lxml.etree.parse(str(file)).getroot()\n      return SemanticVersion(xsd.get(\"version\", None))\n\n  def overview_txt(self, file, skip = 0):\n    return self._revhistory_(file, skip)\n    \n  def introduction_txt(self, file, component = None):\n    table = self._cmtable_(file)\n    if table is None:\n      return None\n\n    if component:\n      m = re.search(re.escape(component)+\"\\s+[Vv]?(\\d+.\\d+(.\\d+)?)\", table[1][1].text, re.MULTILINE)\n      if m:\n        return SemanticVersion(m.group(1))\n    else:\n      return SemanticVersion(table[1][0].text)\n    \n  def dap_txt(self, file, skip = 0):\n    return self._revhistory_(file, skip)\n\n  def general_txt(self, file, skip = 0):\n    return self._revhistory_(file, skip)\n  \n  def history_txt(self, file, skip = 0):\n    return self._revhistory_(file, skip)\n\n  def _all_(self, file):\n    \"\"\"Get the version or revision tag from an arbitrary file.\"\"\"\n    version = self._regex_(file, \".*@version\\s+([vV])?([0-9]+[.][0-9]+([.][0-9]+)?).*\", 2)\n    if not version:\n      version = self._regex_(file, \".*\\$Revision:\\s+([vV])?([0-9]+[.][0-9]+([.][0-9]+)?).*\", 2)\n    return version\n    \nclass CmsisPackLinter(PackLinter):\n\n  def __init__(self, pdsc = \"ARM.CMSIS.pdsc\"):\n    super().__init__(pdsc)\n    self._versionParser = CmsisPackVersionParser(self._logger)\n    \n  def pack_version(self):\n    return self._pack.version()\n  \n  def cmsis_corem_component(self):\n    rte = { 'components' : set(), 'Dcore' : \"Cortex-M3\", 'Dvendor' : \"*\", 'Dname' : \"*\", 'Dtz' : \"*\", 'Dsecure' : \"*\", 'Tcompiler' : \"*\", 'Toptions' : \"*\" }\n    cs = self._pack.component_by_name(rte, \"CMSIS.CORE\")\n    cvs = { SemanticVersion(c.version()) for c in cs }\n    if len(cvs) > 1:\n      self.warning(\"Not all CMSIS-Core(M) components have same version information: %s\", str([ (c.name(), c.version()) for c in cs ]))\n    return cvs.pop()\n\n  def cmsis_corea_component(self):\n    rte = { 'components' : set(), 'Dcore' : \"Cortex-A9\", 'Dvendor' : \"*\", 'Dname' : \"*\", 'Dtz' : \"*\", 'Dsecure' : \"*\", 'Tcompiler' : \"*\", 'Toptions' : \"*\" }\n    cs = self._pack.component_by_name(rte, \"CMSIS.CORE\")\n    cvs = { SemanticVersion(c.version()) for c in cs }\n    if len(cvs) > 1:\n      self.warning(\"Not all CMSIS-Core(A) components have same version information: %s\", str([ (c.name(), c.version()) for c in cs ]))\n    return cvs.pop()\n\n  def cmsis_rtos2_api(self):\n    cs = self._pack.components_by_name(\"CMSIS.RTOS2\")\n    cvs = { SemanticVersion(c.version()) for c in cs }\n    if len(cvs) > 1:\n      self.warning(\"Not all CMSIS-RTOS2 APIs have same version information: %s\", str([ (c.name(), c.version()) for c in cs ]))\n    return cvs.pop()\n\n  def cmsis_rtx5_component(self):\n    cs = self._pack.components_by_name(\"CMSIS.RTOS2.Keil RTX5*\")\n    cvs = { (SemanticVersion(c.version()), SemanticVersion(c.apiversion())) for c in cs }\n    if len(cvs) == 1:\n      return cvs.pop()\n    elif len(cvs) > 1:\n      self.warning(\"Not all RTX5 components have same version information: %s\", str([ (c.name(), c.version(), c.apiversion()) for c in cs ]))\n    return None, None\n\n  def check_general(self):\n    \"\"\"CMSIS version\"\"\"\n    v = self.pack_version()\n    self.verify_version(\"README.md\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/general.dxy\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", v)\n\n  def check_build(self):\n    \"\"\"CMSIS-Build version\"\"\"\n    v = self._versionParser.get_version(\"CMSIS/DoxyGen/Build/Build.dxy\")\n    self.verify_version(\"CMSIS/DoxyGen/Build/src/General.txt\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", v, component=\"CMSIS-Build\")\n    self.verify_version(self._pack.location(), v, component=\"CMSIS-Build\")\n\n  def check_corem(self):\n    \"\"\"CMSIS-Core(M) version\"\"\"\n    v = self.cmsis_corem_component()\n    self.verify_version(\"CMSIS/DoxyGen/Core/core.dxy\", v)\n    self.verify_version(\"CMSIS/DoxyGen/Core/src/Overview.txt\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", v, component=\"CMSIS-Core (Cortex-M)\")\n    self.verify_version(self._pack.location(), v, component=\"CMSIS-Core(M)\")\n\n  def check_corea(self):\n    \"\"\"CMSIS-Core(A) version\"\"\"\n    v = self.cmsis_corea_component()\n    self.verify_version(\"CMSIS/DoxyGen/Core_A/core_A.dxy\", v)\n    self.verify_version(\"CMSIS/DoxyGen/Core_A/src/Overview.txt\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", v, component=\"CMSIS-Core (Cortex-A)\")\n    self.verify_version(self._pack.location(), v, component=\"CMSIS-Core(A)\")\n\n  def check_dap(self):\n    \"\"\"CMSIS-DAP version\"\"\"\n    v = self._versionParser.get_version(\"CMSIS/DoxyGen/DAP/dap.dxy\")\n    self.verify_version(\"CMSIS/DoxyGen/DAP/src/dap.txt\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", v, component=\"CMSIS-DAP\")\n    self.verify_version(self._pack.location(), v, component=\"CMSIS-DAP\")\n\n  def check_driver(self):\n    \"\"\"CMSIS-Driver version\"\"\"\n    v = self._versionParser.get_version(\"CMSIS/DoxyGen/Driver/Driver.dxy\")\n    self.verify_version(\"CMSIS/DoxyGen/Driver/src/General.txt\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", v, component=\"CMSIS-Driver\")\n    self.verify_version(self._pack.location(), v, component=\"CMSIS-Driver\")\n\n  def check_dsp(self):\n    \"\"\"CMSIS-DSP version\"\"\"\n    v = self._versionParser.get_version(\"CMSIS/DoxyGen/DSP/dsp.dxy\")\n    self.verify_version(\"CMSIS/DoxyGen/DSP/src/history.txt\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", v, component=\"CMSIS-DSP\")\n    self.verify_version(self._pack.location(), v, component=\"CMSIS-DSP\")\n\n  def check_nn(self):\n    \"\"\"CMSIS-NN version\"\"\"\n    v = self._versionParser.get_version(\"CMSIS/DoxyGen/NN/nn.dxy\")\n    self.verify_version(\"CMSIS/DoxyGen/NN/src/history.txt\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", v, component=\"CMSIS-NN\")\n    self.verify_version(self._pack.location(), v, component=\"CMSIS-NN\")\n\n  def check_pack(self):\n    \"\"\"CMSIS-Pack version\"\"\"\n    v = self._versionParser.get_version(\"CMSIS/Utilities/PACK.xsd\")\n    self.verify_version(\"CMSIS/Utilities/PACK.xsd:Revision\", v, rev=True)\n    self.verify_version(\"CMSIS/Utilities/PACK.xsd:History\", v, history=True)\n    self.verify_version(\"CMSIS/DoxyGen/Pack/Pack.dxy\", v)\n    self.verify_version(\"CMSIS/DoxyGen/Pack/src/General.txt\", v)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", v, component=\"CMSIS-Pack\")\n    self.verify_version(self._pack.location(), v, component=\"CMSIS-Pack\")\n\n  def check_rtos2(self):\n    \"\"\"CMSIS-RTOS2 version\"\"\"\n    api = self.cmsis_rtos2_api()\n    v, a = self.cmsis_rtx5_component()\n    self.verify_version(\"CMSIS/DoxyGen/RTOS2/rtos.dxy\", api)\n    self.verify_version(\"CMSIS/DoxyGen/RTOS2/src/history.txt\", api, skip=0)\n    self.verify_version(\"CMSIS/DoxyGen/General/src/introduction.txt\", api, component=\"CMSIS-RTOS\")\n    # self.verify_version(self._pack.location(), v, component=\"CMSIS-RTOS2\")\n    if a and not api.match(a):\n      self.warning(\"RTX5 API version (%s) does not match RTOS2 API version (%s)!\", a, api)\n    self.verify_version(\"CMSIS/DoxyGen/RTOS2/src/history.txt\", v, skip=1)\n    \n  def check_files(self):\n    \"\"\"Files referenced by pack description\"\"\"\n    # Check schema of pack description\n    self.verify_schema(self._pack.location(), \"CMSIS/Utilities/PACK.xsd\")\n        \n    # Check schema of SVD files\n    svdfiles = { d.svdfile() for d in self._pack.devices() if d.svdfile() }\n    for svd in svdfiles:\n      if os.path.exists(svd):\n        self.verify_schema(svd, \"CMSIS/Utilities/CMSIS-SVD.xsd\")\n      else:\n        self.warning(\"SVD File does not exist: %s!\", svd)\n\n    # Check component file version\n    for c in self._pack.components():\n      cv = c.version()\n      for f in c.files():\n        hv = f.version()\n        if c is Api:\n          if f.isHeader():\n            if not hv:\n              self.verify_version(f.location(), cv)\n        if hv:\n          self.verify_version(f.location(), SemanticVersion(hv))\n  \n  def check_doc(self, pattern=\"./CMSIS/Documentation/**/*.html\"):\n    \"\"\"Documentation\"\"\"\n    self.debug(\"Using pattern '%s'\", pattern)\n    for html in iglob(pattern, recursive=True):\n      parser = AdvancedHTMLParser()\n      parser.parseFile(html)\n      links = parser.getElementsByTagName(\"a\")\n      if links:\n        self.info(\"%s: Checking links ...\", html)\n      else:\n        self.debug(\"%s: No links found...\", html)\n      for l in links:\n        href = l.getAttribute(\"href\")\n        if href:\n          href = urlparse(href)\n          if href.scheme in [\"http\", \"https\", \"ftp\", \"ftps\" ]:\n            try:\n              self.info(\"%s: Checking link to %s...\", html, href.geturl())\n              r = requests.head(href.geturl(), headers={'user-agent' : \"packlint/1.0\"}, timeout=10)\n              if r.status_code >= 400:\n                self.debug(f'HEAD method failed with HTTP-{r.status_code}, falling back to GET method.')\n                r = requests.get(href.geturl(), headers={'user-agent': \"packlint/1.0\"}, timeout=10)\n              r.raise_for_status()\n            except (requests.exceptions.ConnectionError, requests.exceptions.HTTPError) as e:\n              exc_info = None\n              if self.loglevel() == logging.DEBUG:\n                exc_info = e\n              self.warning(\"%s: Broken web-link to %s!\", html, href.geturl(), exc_info=exc_info)\n            except requests.exceptions.Timeout as e:\n              exc_info = None\n              if self.loglevel() == logging.DEBUG:\n                exc_info = e\n              self.warning(\"%s: Timeout following web-link to %s.\", html, href.geturl(), exc_info=exc_info)\n          elif href.scheme == \"javascript\":\n            pass\n          elif not os.path.isabs(href.path):\n            target = os.path.normpath(os.path.join(os.path.dirname(html), href.path))\n            if not os.path.exists(target):\n              self.warning(\"%s: Broken relative-link to %s!\", html, href.path)\n          else:\n            self.warning(\"%s: Broken relative-link to %s!\", html, href.path)\n"
  },
  {
    "path": "external/printf/.gitattributes",
    "content": "# ignore test path\r\ntest/* linguist-vendored\r\n"
  },
  {
    "path": "external/printf/.travis.yml",
    "content": "# Use a C++11 distro\r\ndist: trusty\r\nsudo: required\r\n\r\n# Enable C++ support\r\nlanguage: cpp\r\n\r\n# Compiler selection\r\ncompiler: gcc\r\n\r\nenv:\r\n  global:\r\n    # coverity key\r\n    - secure: \"NKZbBnMALGIIQJy/s2kc3EST/stw+gjhtrGq0jkbsWr7Wx3FH+lmLeHNsDXRnD1VbpG02c5YsLllqz9OVu+0yxWGepvKNmCz1cNITIALEHbrax8/Af9LzPRL/QZxS/Qe11sMuySp4X16mFBUyxMd/X+I9i96Xf1vKkZABklYD1Q=\"\r\n\r\n# addons\r\naddons:\r\n  apt:\r\n    packages:\r\n      - gcc-6\r\n      - g++-6\r\n    sources:\r\n      - ubuntu-toolchain-r-test\r\n\r\n  coverity_scan:\r\n    project:\r\n      name: \"mpaland/printf\"\r\n      description: \"Tiny printf implementation\"\r\n    notification_email: marco@paland.com\r\n    build_command_prepend: \"make clean\"\r\n    build_command: \"make\"\r\n    branch_pattern: master\r\n\r\nbefore_install:\r\n  # connect coverity\r\n  - echo -n | openssl s_client -connect scan.coverity.com:443 | sed -ne '/-BEGIN CERTIFICATE-/,/-END CERTIFICATE-/p' | sudo tee -a /etc/ssl/certs/ca-\r\n\r\n# Active branches\r\nbranches:\r\n  only:\r\n   - master\r\n\r\nscript:\r\n  # Link gcc-6 and g++-6 to their standard commands\r\n  - sudo rm /usr/bin/gcc\r\n  - sudo rm /usr/bin/g++\r\n  - sudo ln -s /usr/bin/gcc-6 /usr/bin/gcc\r\n  - sudo ln -s /usr/bin/g++-6 /usr/bin/g++\r\n  # Export CC and CXX\r\n  - export CC=/usr/bin/gcc-6\r\n  - export CXX=/usr/bin/g++-6\r\n  # Check versions of gcc, g++\r\n  - gcc -v && g++ -v\r\n  # Run build commands\r\n  - make\r\n  # execute the text suite\r\n  - bin/test_suite -d yes\r\n  # coverall profiling\r\n  - tmp/cov/test_suite\r\n\r\nafter_success:\r\n  ## Report to codecov\r\n  - bash <(curl -s https://codecov.io/bash)\r\n"
  },
  {
    "path": "external/printf/LICENSE",
    "content": "The MIT License (MIT)\r\n\r\nCopyright (c) 2014 Marco Paland\r\n\r\nPermission is hereby granted, free of charge, to any person obtaining a copy\r\nof this software and associated documentation files (the \"Software\"), to deal\r\nin the Software without restriction, including without limitation the rights\r\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r\ncopies of the Software, and to permit persons to whom the Software is\r\nfurnished to do so, subject to the following conditions:\r\n\r\nThe above copyright notice and this permission notice shall be included in all\r\ncopies or substantial portions of the Software.\r\n\r\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r\nSOFTWARE.\r\n\r\n"
  },
  {
    "path": "external/printf/Makefile",
    "content": "# ------------------------------------------------------------------------------\r\n# \r\n# Generic Makefile\r\n#\r\n# Copyright Marco Paland 2007 - 2017\r\n# Distributed under the MIT License\r\n#\r\n# ------------------------------------------------------------------------------\r\n\r\n# ------------------------------------------------------------------------------\r\n# Paths\r\n# ------------------------------------------------------------------------------\r\nPATH_TOOLS_CC        = /usr/bin/\r\nPATH_TOOLS_CC_LIB    = /usr/lib/\r\nPATH_TOOLS_UTIL      = \r\n\r\nPATH_BIN       = bin\r\nPATH_TMP       = tmp\r\nPATH_NUL       = /dev/null\r\nPATH_OBJ       = $(PATH_TMP)/obj\r\nPATH_LST       = $(PATH_TMP)/lst\r\nPATH_ERR       = $(PATH_TMP)/err\r\nPATH_PRE       = $(PATH_TMP)/pre\r\nPATH_COV       = $(PATH_TMP)/cov\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# Application to build\r\n# ------------------------------------------------------------------------------\r\n\r\nAPP = test_suite\r\n\r\n\r\n# -----------------------------------------------------------------------------\r\n# Project file list\r\n# Format is:\r\n# FILES_PRJ  = file1                        \\\r\n#              foo/file2                    \\\r\n#              bar/file3\r\n# -----------------------------------------------------------------------------\r\n\r\nFILES_PRJ  = test/test_suite\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# Additional include files and compiler defines\r\n# Format is:\r\n# C_INCLUDES = -Iinclude_path1                 \\\r\n#              -Iinclude_path2                 \\\r\n#              -Iinclude_path3                 \\\r\n# ------------------------------------------------------------------------------\r\n\r\nC_INCLUDES = \r\n\r\nC_DEFINES  = \r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# The target name and location\r\n# ------------------------------------------------------------------------------\r\nTRG = $(PATH_BIN)/$(APP)\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# object files\r\n# ------------------------------------------------------------------------------\r\nFILES_TMP   = $(FILES_PRJ)\r\nFILES_O     = $(addsuffix .o, $(FILES_TMP))\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# VPATH definition\r\n#\r\n# VPATH is required for the maker to find the C-/ASM-Source files.\r\n# Extract the directory/module names from the file list with the dir\r\n# command and remove the duplicated directory names with the sort command.\r\n# FILES_PRJ is listed first to make sure that the source files in the project\r\n# directory are searched first.\r\n# ------------------------------------------------------------------------------\r\nVPATH := $(sort $(dir $(FILES_TMP)))\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# Development tools\r\n# ------------------------------------------------------------------------------\r\nAR        = $(PATH_TOOLS_CC)ar\r\nAS        = $(PATH_TOOLS_CC)g++\r\nCC        = $(PATH_TOOLS_CC)g++\r\nCL        = $(PATH_TOOLS_CC)g++\r\nNM        = $(PATH_TOOLS_CC)nm\r\nGCOV      = $(PATH_TOOLS_CC)gcov\r\nOBJDUMP   = $(PATH_TOOLS_CC)objdump\r\nOBJCOPY   = $(PATH_TOOLS_CC)objcopy\r\nREADELF   = $(PATH_TOOLS_CC)readelf\r\nSIZE      = $(PATH_TOOLS_CC)size\r\n\r\nECHO      = $(PATH_TOOLS_UTIL)echo\r\nMAKE      = $(PATH_TOOLS_UTIL)make\r\nMKDIR     = $(PATH_TOOLS_UTIL)mkdir\r\nRM        = $(PATH_TOOLS_UTIL)rm\r\nSED       = $(PATH_TOOLS_UTIL)sed\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# Compiler flags for the target architecture\r\n# ------------------------------------------------------------------------------\r\n\r\nGCCFLAGS      = $(C_INCLUDES)                     \\\r\n                $(C_DEFINES)                      \\\r\n                -std=c++11                        \\\r\n                -g                                \\\r\n                -Wall                             \\\r\n                -pedantic                         \\\r\n                -Wmain                            \\\r\n                -Wundef                           \\\r\n                -Wsign-conversion                 \\\r\n                -Wuninitialized                   \\\r\n                -Wshadow                          \\\r\n                -Wunreachable-code                \\\r\n                -Wswitch-default                  \\\r\n                -Wswitch                          \\\r\n                -Wcast-align                      \\\r\n                -Wmissing-include-dirs            \\\r\n                -Winit-self                       \\\r\n                -Wdouble-promotion                \\\r\n                -gdwarf-2                         \\\r\n                -fno-exceptions                   \\\r\n                -O2                               \\\r\n                -ffunction-sections               \\\r\n                -ffat-lto-objects                 \\\r\n                -fdata-sections                   \\\r\n                -fverbose-asm                     \\\r\n                -Wextra                           \\\r\n                -Wunused-parameter                \\\r\n                -Wfloat-equal\r\n\r\nCFLAGS        = $(GCCFLAGS)                       \\\r\n                -Wunsuffixed-float-constants      \\\r\n                -x c                              \\\r\n                -std=c99\r\n\r\nCPPFLAGS      = $(GCCFLAGS)                       \\\r\n                -x c++                            \\\r\n                -fno-rtti                         \\\r\n                -fstrict-enums                    \\\r\n                -fno-use-cxa-atexit               \\\r\n                -fno-use-cxa-get-exception-ptr    \\\r\n                -fno-nonansi-builtins             \\\r\n                -fno-threadsafe-statics           \\\r\n                -fno-enforce-eh-specs             \\\r\n                -ftemplate-depth-64               \\\r\n                -fexceptions\r\n\r\nAFLAGS        = $(GCCFLAGS)                       \\\r\n                -x assembler\r\n\r\nLFLAGS        = $(GCCFLAGS)                       \\\r\n                -x none                           \\\r\n                -Wl,--gc-sections\r\n\r\n# ------------------------------------------------------------------------------\r\n# Targets\r\n# ------------------------------------------------------------------------------\r\n\r\n# ------------------------------------------------------------------------------\r\n# Main-Dependencies (app: all)\r\n# ------------------------------------------------------------------------------\r\n.PHONY: all\r\nall: clean_prj $(TRG) $(TRG)_nm.txt\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# Main-Dependencies (app: rebuild)\r\n# ------------------------------------------------------------------------------\r\n.PHONY: rebuild\r\nrebuild: clean $(TRG) $(TRG)_nm.txt\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# clean project\r\n# ------------------------------------------------------------------------------\r\n.PHONY: clean_prj\r\nclean_prj:\r\n\t@-$(ECHO) +++ cleaning project\r\n\t@-$(RM) -rf $(PATH_BIN) 2> $(PATH_NUL)\r\n\t@-$(MKDIR) -p $(PATH_BIN)\r\n\t@-$(MKDIR) -p $(PATH_OBJ)\r\n\t@-$(MKDIR) -p $(PATH_ERR)\r\n\t@-$(MKDIR) -p $(PATH_LST)\r\n\t@-$(MKDIR) -p $(PATH_PRE)\r\n\t@-$(MKDIR) -p $(PATH_COV)\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# clean all\r\n# ------------------------------------------------------------------------------\r\n.PHONY: clean\r\nclean:\r\n\t@-$(ECHO) +++ cleaning all\r\n\t@-$(RM) -rf $(PATH_BIN) 2> $(PATH_NUL)\r\n\t@-$(RM) -rf $(PATH_TMP) 2> $(PATH_NUL)\r\n\t@-$(MKDIR) -p $(PATH_BIN)\r\n\t@-$(MKDIR) -p $(PATH_OBJ)\r\n\t@-$(MKDIR) -p $(PATH_ERR)\r\n\t@-$(MKDIR) -p $(PATH_LST)\r\n\t@-$(MKDIR) -p $(PATH_COV)\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# print the GNUmake version and the compiler version\r\n# ------------------------------------------------------------------------------\r\n.PHONY: version\r\nversion:\r\n  # Print the GNU make version and the compiler version\r\n\t@$(ECHO) GNUmake version:\r\n\t@$(MAKE) --version\r\n\t@$(ECHO) GCC version:\r\n\t@$(CL) -v\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# Rules\r\n# ------------------------------------------------------------------------------\r\n\r\n# ------------------------------------------------------------------------------\r\n# Link/locate application\r\n# ------------------------------------------------------------------------------\r\n$(TRG) : $(FILES_O)\r\n\t@-$(ECHO) +++ linkink application to generate: $(TRG)\r\n\t@-$(CL) $(LFLAGS) -L. -lc $(PATH_OBJ)/*.o -Wl,-Map,$(TRG).map -o $(TRG)\r\n  # profiling\r\n\t@-$(CL) $(LFLAGS) -L. -lc $(PATH_COV)/*.o --coverage -o $(PATH_COV)/$(APP)\r\n\r\n\r\n# ------------------------------------------------------------------------------\r\n# parse the object files to obtain symbol information, and create a size summary\r\n# ------------------------------------------------------------------------------\r\n$(TRG)_nm.txt : $(TRG)\r\n\t@-$(ECHO) +++ parsing symbols with nm to generate: $(TRG)_nm.txt\r\n\t@-$(NM) --numeric-sort --print-size $(TRG) > $(TRG)_nm.txt\r\n\t@-$(ECHO) +++ demangling symbols with c++filt to generate: $(TRG)_cppfilt.txt\r\n\t@-$(NM) --numeric-sort --print-size $(TRG) | $(CPPFILT) > $(TRG)_cppfilt.txt\r\n\t@-$(ECHO) +++ creating size summary table with size to generate: $(TRG)_size.txt\r\n\t@-$(SIZE) -A -t $(TRG) > $(TRG)_size.txt\r\n\r\n\r\n%.o : %.cpp\r\n\t@$(ECHO) +++ compile: $<\r\n  # Compile the source file\r\n  # ...and Reformat (using sed) any possible error/warning messages for the VisualStudio(R) output window\r\n  # ...and Create an assembly listing using objdump\r\n  # ...and Generate a dependency file (using the -MM flag)\r\n\t@-$(CL) $(CPPFLAGS) $< -E -o $(PATH_PRE)/$(basename $(@F)).pre\r\n\t@-$(CL) $(CPPFLAGS) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err\r\n\t@-$(SED) -e 's|.h:\\([0-9]*\\),|.h(\\1) :|' -e 's|:\\([0-9]*\\):|(\\1) :|' $(PATH_ERR)/$(basename $(@F)).err\r\n\t@-$(OBJDUMP) --disassemble --line-numbers -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst\r\n\t@-$(CL) $(CPPFLAGS) $< -MM > $(PATH_OBJ)/$(basename $(@F)).d\r\n  # profiling\r\n\t@-$(CL) $(CPPFLAGS) -O0 --coverage $< -c -o $(PATH_COV)/$(basename $(@F)).o 2> $(PATH_NUL)\r\n\r\n%.o : %.c\r\n\t@$(ECHO) +++ compile: $<\r\n  # Compile the source file\r\n  # ...and Reformat (using sed) any possible error/warning messages for the VisualStudio(R) output window\r\n  # ...and Create an assembly listing using objdump\r\n  # ...and Generate a dependency file (using the -MM flag)\r\n\t@-$(CL) $(CFLAGS) $< -E -o $(PATH_PRE)/$(basename $(@F)).pre\r\n\t@-$(CC) $(CFLAGS) $< -c -o $(PATH_OBJ)/$(basename $(@F)).o 2> $(PATH_ERR)/$(basename $(@F)).err\r\n\t@-$(SED) -e 's|.h:\\([0-9]*\\),|.h(\\1) :|' -e 's|:\\([0-9]*\\):|(\\1) :|' $(PATH_ERR)/$(basename $(@F)).err\r\n\t@-$(OBJDUMP) -S $(PATH_OBJ)/$(basename $(@F)).o > $(PATH_LST)/$(basename $(@F)).lst\r\n\t@-$(CC) $(CFLAGS) $< -MM > $(PATH_OBJ)/$(basename $(@F)).d\r\n"
  },
  {
    "path": "external/printf/README.md",
    "content": "# A printf / sprintf Implementation for Embedded Systems\r\n\r\n[![Build Status](https://travis-ci.org/mpaland/printf.svg?branch=master)](https://travis-ci.org/mpaland/printf)\r\n[![codecov](https://codecov.io/gh/mpaland/printf/branch/master/graph/badge.svg)](https://codecov.io/gh/mpaland/printf)\r\n[![Coverity Status](https://img.shields.io/coverity/scan/14180.svg)](https://scan.coverity.com/projects/mpaland-printf)\r\n[![Github Issues](https://img.shields.io/github/issues/mpaland/printf.svg)](http://github.com/mpaland/printf/issues)\r\n[![Github Releases](https://img.shields.io/github/release/mpaland/printf.svg)](https://github.com/mpaland/printf/releases)\r\n[![GitHub license](https://img.shields.io/badge/license-MIT-blue.svg)](https://raw.githubusercontent.com/mpaland/avl_array/master/LICENSE)\r\n\r\nThis is a tiny but **fully loaded** printf, sprintf and (v)snprintf implementation.\r\nPrimarily designed for usage in embedded systems, where printf is not available due to memory issues or in avoidance of linking against libc.\r\nUsing the standard libc printf may pull **a lot** of unwanted library stuff and can bloat code size about 20k or is not 100% thread safe. In this cases the following implementation can be used.\r\nAbsolutely **NO dependencies** are required, *printf.c* brings all necessary routines, even its own fast `ftoa` (floating point), `ntoa` (decimal) conversion.\r\n\r\nIf memory footprint is really a critical issue, floating point, exponential and 'long long' support and can be turned off via the `PRINTF_DISABLE_SUPPORT_FLOAT`, `PRINTF_DISABLE_SUPPORT_EXPONENTIAL` and `PRINTF_DISABLE_SUPPORT_LONG_LONG` compiler switches.\r\nWhen using printf (instead of sprintf/snprintf) you have to provide your own `_putchar()` low level function as console/serial output.\r\n\r\n\r\n## 2020 announcement\r\nThis project is not dead! I just had no time in 2019 for sufficient support, sorry.\r\nWithin the next weeks, I will have a look to all PRs and open issues.  \r\nThank you all for supporting this project.\r\n\r\n\r\n## Highlights and Design Goals\r\n\r\nThere is a boatload of so called 'tiny' printf implementations around. So why this one?\r\nI've tested many implementations, but most of them have very limited flag/specifier support, a lot of other dependencies or are just not standard compliant and failing most of the test suite.\r\nTherefore I decided to write an own, final implementation which meets the following items:\r\n\r\n - Very small implementation (around 600 code lines)\r\n - NO dependencies, no libs, just one module file\r\n - Support of all important flags, width and precision sub-specifiers (see below)\r\n - Support of decimal/floating number representation (with an own fast itoa/ftoa)\r\n - Reentrant and thread-safe, malloc free, no static vars/buffers\r\n - LINT and compiler L4 warning free, mature, coverity clean, automotive ready\r\n - Extensive test suite (> 400 test cases) passing\r\n - Simply the best *printf* around the net\r\n - MIT license\r\n\r\n\r\n## Usage\r\n\r\nAdd/link *printf.c* to your project and include *printf.h*. That's it.\r\nImplement your low level output function needed for `printf()`:\r\n```C\r\nvoid _putchar(char character)\r\n{\r\n  // send char to console etc.\r\n}\r\n```\r\n\r\nUsage is 1:1 like the according stdio.h library version:\r\n```C\r\nint printf(const char* format, ...);\r\nint sprintf(char* buffer, const char* format, ...);\r\nint snprintf(char* buffer, size_t count, const char* format, ...);\r\nint vsnprintf(char* buffer, size_t count, const char* format, va_list va);\r\n\r\n// use output function (instead of buffer) for streamlike interface\r\nint fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...);\r\n```\r\n\r\n**Due to general security reasons it is highly recommended to prefer and use `snprintf` (with the max buffer size as `count` parameter) instead of `sprintf`.**\r\n`sprintf` has no buffer limitation, so when needed - use it really with care!\r\n\r\n### Streamlike Usage\r\nBesides the regular standard `printf()` functions, this module also provides `fctprintf()`, which takes an output function as first parameter to build a streamlike output like `fprintf()`:\r\n```C\r\n// define the output function\r\nvoid my_stream_output(char character, void* arg)\r\n{\r\n  // opt. evaluate the argument and send the char somewhere\r\n}\r\n\r\n{\r\n  // in your code\r\n  void* arg = (void*)100;  // this argument is passed to the output function\r\n  fctprintf(&my_stream_output, arg, \"This is a test: %X\", 0xAA);\r\n  fctprintf(&my_stream_output, nullptr, \"Send to null dev\");\r\n}\r\n```\r\n\r\n## Format Specifiers\r\n\r\nA format specifier follows this prototype: `%[flags][width][.precision][length]type`\r\nThe following format specifiers are supported:\r\n\r\n\r\n### Supported Types\r\n\r\n| Type   | Output |\r\n|--------|--------|\r\n| d or i | Signed decimal integer |\r\n| u      | Unsigned decimal integer\t|\r\n| b      | Unsigned binary |\r\n| o      | Unsigned octal |\r\n| x      | Unsigned hexadecimal integer (lowercase) |\r\n| X      | Unsigned hexadecimal integer (uppercase) |\r\n| f or F | Decimal floating point |\r\n| e or E | Scientific-notation (exponential) floating point |\r\n| g or G | Scientific or decimal floating point |\r\n| c      | Single character |\r\n| s      | String of characters |\r\n| p      | Pointer address |\r\n| %      | A % followed by another % character will write a single % |\r\n\r\n\r\n### Supported Flags\r\n\r\n| Flags | Description |\r\n|-------|-------------|\r\n| -     | Left-justify within the given field width; Right justification is the default. |\r\n| +     | Forces to precede the result with a plus or minus sign (+ or -) even for positive numbers.<br>By default, only negative numbers are preceded with a - sign. |\r\n| (space) | If no sign is going to be written, a blank space is inserted before the value. |\r\n| #     | Used with o, b, x or X specifiers the value is preceded with 0, 0b, 0x or 0X respectively for values different than zero.<br>Used with f, F it forces the written output to contain a decimal point even if no more digits follow. By default, if no digits follow, no decimal point is written. |\r\n| 0     | Left-pads the number with zeros (0) instead of spaces when padding is specified (see width sub-specifier). |\r\n\r\n\r\n### Supported Width\r\n\r\n| Width    | Description |\r\n|----------|-------------|\r\n| (number) | Minimum number of characters to be printed. If the value to be printed is shorter than this number, the result is padded with blank spaces. The value is not truncated even if the result is larger. |\r\n| *        | The width is not specified in the format string, but as an additional integer value argument preceding the argument that has to be formatted. |\r\n\r\n\r\n### Supported Precision\r\n\r\n| Precision\t| Description |\r\n|-----------|-------------|\r\n| .number   | For integer specifiers (d, i, o, u, x, X): precision specifies the minimum number of digits to be written. If the value to be written is shorter than this number, the result is padded with leading zeros. The value is not truncated even if the result is longer. A precision of 0 means that no character is written for the value 0.<br>For f and F specifiers: this is the number of digits to be printed after the decimal point. **By default, this is 6, maximum is 9**.<br>For s: this is the maximum number of characters to be printed. By default all characters are printed until the ending null character is encountered.<br>If the period is specified without an explicit value for precision, 0 is assumed. |\r\n| .*        | The precision is not specified in the format string, but as an additional integer value argument preceding the argument that has to be formatted. |\r\n\r\n\r\n### Supported Length\r\n\r\nThe length sub-specifier modifies the length of the data type.\r\n\r\n| Length | d i  | u o x X |\r\n|--------|------|---------|\r\n| (none) | int  | unsigned int |\r\n| hh     | char | unsigned char |\r\n| h      | short int | unsigned short int |\r\n| l      | long int | unsigned long int |\r\n| ll     | long long int | unsigned long long int (if PRINTF_SUPPORT_LONG_LONG is defined) |\r\n| j      | intmax_t | uintmax_t |\r\n| z      | size_t | size_t |\r\n| t      | ptrdiff_t | ptrdiff_t (if PRINTF_SUPPORT_PTRDIFF_T is defined) |\r\n\r\n\r\n### Return Value\r\n\r\nUpon successful return, all functions return the number of characters written, _excluding_ the terminating null character used to end the string.\r\nFunctions `snprintf()` and `vsnprintf()` don't write more than `count` bytes, _including_ the terminating null byte ('\\0').\r\nAnyway, if the output was truncated due to this limit, the return value is the number of characters that _could_ have been written.\r\nNotice that a value equal or larger than `count` indicates a truncation. Only when the returned value is non-negative and less than `count`,\r\nthe string has been completely written.\r\nIf any error is encountered, `-1` is returned.\r\n\r\nIf `buffer` is set to `NULL` (`nullptr`) nothing is written and just the formatted length is returned.\r\n```C\r\nint length = sprintf(NULL, \"Hello, world\"); // length is set to 12\r\n```\r\n\r\n\r\n## Compiler Switches/Defines\r\n\r\n| Name | Default value | Description |\r\n|------|---------------|-------------|\r\n| PRINTF_INCLUDE_CONFIG_H            | undefined | Define this as compiler switch (e.g. `gcc -DPRINTF_INCLUDE_CONFIG_H`) to include a \"printf_config.h\" definition file |\r\n| PRINTF_NTOA_BUFFER_SIZE            | 32        | ntoa (integer) conversion buffer size. This must be big enough to hold one converted numeric number _including_ leading zeros, normally 32 is a sufficient value. Created on the stack |\r\n| PRINTF_FTOA_BUFFER_SIZE            | 32        | ftoa (float) conversion buffer size. This must be big enough to hold one converted float number _including_ leading zeros, normally 32 is a sufficient value. Created on the stack |\r\n| PRINTF_DEFAULT_FLOAT_PRECISION     | 6         | Define the default floating point precision |\r\n| PRINTF_MAX_FLOAT                   | 1e9       | Define the largest suitable value to be printed with %f, before using exponential representation |\r\n| PRINTF_DISABLE_SUPPORT_FLOAT       | undefined | Define this to disable floating point (%f) support |\r\n| PRINTF_DISABLE_SUPPORT_EXPONENTIAL | undefined | Define this to disable exponential floating point (%e) support |\r\n| PRINTF_DISABLE_SUPPORT_LONG_LONG   | undefined | Define this to disable long long (%ll) support |\r\n| PRINTF_DISABLE_SUPPORT_PTRDIFF_T   | undefined | Define this to disable ptrdiff_t (%t) support |\r\n\r\n\r\n## Caveats\r\nNone anymore (finally).\r\n\r\n\r\n## Test Suite\r\nFor testing just compile, build and run the test suite located in `test/test_suite.cpp`. This uses the [catch](https://github.com/catchorg/Catch2) framework for unit-tests, which is auto-adding main().\r\nRunning with the `--wait-for-keypress exit` option waits for the enter key after test end.\r\n\r\n\r\n## Projects Using printf\r\n- [turnkeyboard](https://github.com/mpaland/turnkeyboard) uses printf as log and generic tty (formatting) output.\r\n- printf is part of [embeddedartistry/libc](https://github.com/embeddedartistry/libc), a libc targeted for embedded systems usage.\r\n- The [Hatchling Platform]( https://github.com/adrian3git/HatchlingPlatform) uses printf.\r\n\r\n(Just send me a mail/issue/PR to get *your* project listed here)\r\n\r\n\r\n## Contributing\r\n\r\n0. Give this project a :star:\r\n1. Create an issue and describe your idea\r\n2. [Fork it](https://github.com/mpaland/printf/fork)\r\n3. Create your feature branch (`git checkout -b my-new-feature`)\r\n4. Commit your changes (`git commit -am 'Add some feature'`)\r\n5. Publish the branch (`git push origin my-new-feature`)\r\n6. Create a new pull request\r\n7. Profit! :heavy_check_mark:\r\n\r\n\r\n## License\r\nprintf is written under the [MIT license](http://www.opensource.org/licenses/MIT).\r\n"
  },
  {
    "path": "external/printf/codecov.yml",
    "content": "ignore:\r\n  - \"test\"  # ignore the test folder\r\n"
  },
  {
    "path": "external/printf/printf.c",
    "content": "///////////////////////////////////////////////////////////////////////////////\r\n// \\author (c) Marco Paland (info@paland.com)\r\n//             2014-2019, PALANDesign Hannover, Germany\r\n//\r\n// \\license The MIT License (MIT)\r\n//\r\n// Permission is hereby granted, free of charge, to any person obtaining a copy\r\n// of this software and associated documentation files (the \"Software\"), to deal\r\n// in the Software without restriction, including without limitation the rights\r\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r\n// copies of the Software, and to permit persons to whom the Software is\r\n// furnished to do so, subject to the following conditions:\r\n//\r\n// The above copyright notice and this permission notice shall be included in\r\n// all copies or substantial portions of the Software.\r\n//\r\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\r\n// THE SOFTWARE.\r\n//\r\n// \\brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on\r\n//        embedded systems with a very limited resources. These routines are thread\r\n//        safe and reentrant!\r\n//        Use this instead of the bloated standard/newlib printf cause these use\r\n//        malloc for printf (and may not be thread safe).\r\n//\r\n///////////////////////////////////////////////////////////////////////////////\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n#include \"printf.h\"\r\n\r\n\r\n// define this globally (e.g. gcc -DPRINTF_INCLUDE_CONFIG_H ...) to include the\r\n// printf_config.h header file\r\n// default: undefined\r\n#ifdef PRINTF_INCLUDE_CONFIG_H\r\n#include \"printf_config.h\"\r\n#endif\r\n\r\n\r\n// 'ntoa' conversion buffer size, this must be big enough to hold one converted\r\n// numeric number including padded zeros (dynamically created on stack)\r\n// default: 32 byte\r\n#ifndef PRINTF_NTOA_BUFFER_SIZE\r\n#define PRINTF_NTOA_BUFFER_SIZE    32U\r\n#endif\r\n\r\n// 'ftoa' conversion buffer size, this must be big enough to hold one converted\r\n// float number including padded zeros (dynamically created on stack)\r\n// default: 32 byte\r\n#ifndef PRINTF_FTOA_BUFFER_SIZE\r\n#define PRINTF_FTOA_BUFFER_SIZE    32U\r\n#endif\r\n\r\n// support for the floating point type (%f)\r\n// default: activated\r\n#ifndef PRINTF_DISABLE_SUPPORT_FLOAT\r\n#define PRINTF_SUPPORT_FLOAT\r\n#endif\r\n\r\n// support for exponential floating point notation (%e/%g)\r\n// default: activated\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n#define PRINTF_SUPPORT_EXPONENTIAL\r\n#endif\r\n\r\n// define the default floating point precision\r\n// default: 6 digits\r\n#ifndef PRINTF_DEFAULT_FLOAT_PRECISION\r\n#define PRINTF_DEFAULT_FLOAT_PRECISION  6U\r\n#endif\r\n\r\n// define the largest float suitable to print with %f\r\n// default: 1e9\r\n#ifndef PRINTF_MAX_FLOAT\r\n#define PRINTF_MAX_FLOAT  1e9\r\n#endif\r\n\r\n// support for the long long types (%llu or %p)\r\n// default: activated\r\n#ifndef PRINTF_DISABLE_SUPPORT_LONG_LONG\r\n#define PRINTF_SUPPORT_LONG_LONG\r\n#endif\r\n\r\n// support for the ptrdiff_t type (%t)\r\n// ptrdiff_t is normally defined in <stddef.h> as long or long long type\r\n// default: activated\r\n#ifndef PRINTF_DISABLE_SUPPORT_PTRDIFF_T\r\n#define PRINTF_SUPPORT_PTRDIFF_T\r\n#endif\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n\r\n// internal flag definitions\r\n#define FLAGS_ZEROPAD   (1U <<  0U)\r\n#define FLAGS_LEFT      (1U <<  1U)\r\n#define FLAGS_PLUS      (1U <<  2U)\r\n#define FLAGS_SPACE     (1U <<  3U)\r\n#define FLAGS_HASH      (1U <<  4U)\r\n#define FLAGS_UPPERCASE (1U <<  5U)\r\n#define FLAGS_CHAR      (1U <<  6U)\r\n#define FLAGS_SHORT     (1U <<  7U)\r\n#define FLAGS_LONG      (1U <<  8U)\r\n#define FLAGS_LONG_LONG (1U <<  9U)\r\n#define FLAGS_PRECISION (1U << 10U)\r\n#define FLAGS_ADAPT_EXP (1U << 11U)\r\n\r\n\r\n// import float.h for DBL_MAX\r\n#if defined(PRINTF_SUPPORT_FLOAT)\r\n\r\n#include <float.h>\r\n\r\n#endif\r\n\r\n\r\n// output function type\r\ntypedef void (*out_fct_type)(char character, void *buffer, size_t idx, size_t maxlen);\r\n\r\n\r\n// wrapper (used as buffer) for output function type\r\ntypedef struct {\r\n    void (*fct)(char character, void *arg);\r\n\r\n    void *arg;\r\n} out_fct_wrap_type;\r\n\r\n\r\n// internal buffer output\r\nstatic inline void _out_buffer(char character, void *buffer, size_t idx, size_t maxlen) {\r\n    if (idx < maxlen) {\r\n        ((char *) buffer)[idx] = character;\r\n    }\r\n}\r\n\r\n\r\n// internal null output\r\nstatic inline void _out_null(char character, void *buffer, size_t idx, size_t maxlen) {\r\n    (void) character;\r\n    (void) buffer;\r\n    (void) idx;\r\n    (void) maxlen;\r\n}\r\n\r\n\r\n// internal _putchar wrapper\r\nstatic inline void _out_char(char character, void *buffer, size_t idx, size_t maxlen) {\r\n    (void) buffer;\r\n    (void) idx;\r\n    (void) maxlen;\r\n    if (character) {\r\n        _putchar(character);\r\n    }\r\n}\r\n\r\n\r\n// internal output function wrapper\r\nstatic inline void _out_fct(char character, void *buffer, size_t idx, size_t maxlen) {\r\n    (void) idx;\r\n    (void) maxlen;\r\n    if (character) {\r\n        // buffer is the output fct pointer\r\n        ((out_fct_wrap_type *) buffer)->fct(character, ((out_fct_wrap_type *) buffer)->arg);\r\n    }\r\n}\r\n\r\n\r\n// internal secure strlen\r\n// \\return The length of the string (excluding the terminating 0) limited by 'maxsize'\r\nstatic inline unsigned int _strnlen_s(const char *str, size_t maxsize) {\r\n    const char *s;\r\n    for (s = str; *s && maxsize--; ++s);\r\n    return (unsigned int) (s - str);\r\n}\r\n\r\n\r\n// internal test if char is a digit (0-9)\r\n// \\return true if char is a digit\r\nstatic inline bool _is_digit(char ch) {\r\n    return (ch >= '0') && (ch <= '9');\r\n}\r\n\r\n\r\n// internal ASCII string to unsigned int conversion\r\nstatic unsigned int _atoi(const char **str) {\r\n    unsigned int i = 0U;\r\n    while (_is_digit(**str)) {\r\n        i = i * 10U + (unsigned int) (*((*str)++) - '0');\r\n    }\r\n    return i;\r\n}\r\n\r\n\r\n// output the specified string in reverse, taking care of any zero-padding\r\nstatic size_t\r\n_out_rev(out_fct_type out, char *buffer, size_t idx, size_t maxlen, const char *buf, size_t len, unsigned int width,\r\n         unsigned int flags) {\r\n    const size_t start_idx = idx;\r\n\r\n    // pad spaces up to given width\r\n    if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {\r\n        for (size_t i = len; i < width; i++) {\r\n            out(' ', buffer, idx++, maxlen);\r\n        }\r\n    }\r\n\r\n    // reverse string\r\n    while (len) {\r\n        out(buf[--len], buffer, idx++, maxlen);\r\n    }\r\n\r\n    // append pad spaces up to given width\r\n    if (flags & FLAGS_LEFT) {\r\n        while (idx - start_idx < width) {\r\n            out(' ', buffer, idx++, maxlen);\r\n        }\r\n    }\r\n\r\n    return idx;\r\n}\r\n\r\n\r\n// internal itoa format\r\nstatic size_t\r\n_ntoa_format(out_fct_type out, char *buffer, size_t idx, size_t maxlen, char *buf, size_t len, bool negative,\r\n             unsigned int base, unsigned int prec, unsigned int width, unsigned int flags) {\r\n    // pad leading zeros\r\n    if (!(flags & FLAGS_LEFT)) {\r\n        if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) {\r\n            width--;\r\n        }\r\n        while ((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) {\r\n            buf[len++] = '0';\r\n        }\r\n        while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) {\r\n            buf[len++] = '0';\r\n        }\r\n    }\r\n\r\n    // handle hash\r\n    if (flags & FLAGS_HASH) {\r\n        if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) {\r\n            len--;\r\n            if (len && (base == 16U)) {\r\n                len--;\r\n            }\r\n        }\r\n        if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {\r\n            buf[len++] = 'x';\r\n        } else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {\r\n            buf[len++] = 'X';\r\n        } else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) {\r\n            buf[len++] = 'b';\r\n        }\r\n        if (len < PRINTF_NTOA_BUFFER_SIZE) {\r\n            buf[len++] = '0';\r\n        }\r\n    }\r\n\r\n    if (len < PRINTF_NTOA_BUFFER_SIZE) {\r\n        if (negative) {\r\n            buf[len++] = '-';\r\n        } else if (flags & FLAGS_PLUS) {\r\n            buf[len++] = '+';  // ignore the space if the '+' exists\r\n        } else if (flags & FLAGS_SPACE) {\r\n            buf[len++] = ' ';\r\n        }\r\n    }\r\n\r\n    return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags);\r\n}\r\n\r\n\r\n// internal itoa for 'long' type\r\nstatic size_t _ntoa_long(out_fct_type out, char *buffer, size_t idx, size_t maxlen, unsigned long value, bool negative,\r\n                         unsigned long base, unsigned int prec, unsigned int width, unsigned int flags) {\r\n    char buf[PRINTF_NTOA_BUFFER_SIZE];\r\n    size_t len = 0U;\r\n\r\n    // no hash for 0 values\r\n    if (!value) {\r\n        flags &= ~FLAGS_HASH;\r\n    }\r\n\r\n    // write if precision != 0 and value is != 0\r\n    if (!(flags & FLAGS_PRECISION) || value) {\r\n        do {\r\n            const char digit = (char) (value % base);\r\n            buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;\r\n            value /= base;\r\n        } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));\r\n    }\r\n\r\n    return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int) base, prec, width, flags);\r\n}\r\n\r\n\r\n// internal itoa for 'long long' type\r\n#if defined(PRINTF_SUPPORT_LONG_LONG)\r\n\r\nstatic size_t\r\n_ntoa_long_long(out_fct_type out, char *buffer, size_t idx, size_t maxlen, unsigned long long value, bool negative,\r\n                unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags) {\r\n    char buf[PRINTF_NTOA_BUFFER_SIZE];\r\n    size_t len = 0U;\r\n\r\n    // no hash for 0 values\r\n    if (!value) {\r\n        flags &= ~FLAGS_HASH;\r\n    }\r\n\r\n    // write if precision != 0 and value is != 0\r\n    if (!(flags & FLAGS_PRECISION) || value) {\r\n        do {\r\n            const char digit = (char) (value % base);\r\n            buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;\r\n            value /= base;\r\n        } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));\r\n    }\r\n\r\n    return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int) base, prec, width, flags);\r\n}\r\n\r\n#endif  // PRINTF_SUPPORT_LONG_LONG\r\n\r\n\r\n#if defined(PRINTF_SUPPORT_FLOAT)\r\n\r\n#if defined(PRINTF_SUPPORT_EXPONENTIAL)\r\n\r\n// forward declaration so that _ftoa can switch to exp notation for values > PRINTF_MAX_FLOAT\r\nstatic size_t\r\n_etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width,\r\n      unsigned int flags);\r\n\r\n#endif\r\n\r\n\r\n// internal ftoa for fixed decimal floating point\r\nstatic size_t\r\n_ftoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width,\r\n      unsigned int flags) {\r\n    char buf[PRINTF_FTOA_BUFFER_SIZE];\r\n    size_t len = 0U;\r\n    double diff = 0.0;\r\n\r\n    // powers of 10\r\n    static const double pow10[] = {1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000};\r\n\r\n    // test for special values\r\n    if (value != value)\r\n        return _out_rev(out, buffer, idx, maxlen, \"nan\", 3, width, flags);\r\n    if (value < -DBL_MAX)\r\n        return _out_rev(out, buffer, idx, maxlen, \"fni-\", 4, width, flags);\r\n    if (value > DBL_MAX)\r\n        return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? \"fni+\" : \"fni\", (flags & FLAGS_PLUS) ? 4U : 3U,\r\n                        width, flags);\r\n\r\n    // test for very large values\r\n    // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad\r\n    if ((value > PRINTF_MAX_FLOAT) || (value < -PRINTF_MAX_FLOAT)) {\r\n#if defined(PRINTF_SUPPORT_EXPONENTIAL)\r\n        return _etoa(out, buffer, idx, maxlen, value, prec, width, flags);\r\n#else\r\n        return 0U;\r\n#endif\r\n    }\r\n\r\n    // test for negative\r\n    bool negative = false;\r\n    if (value < 0) {\r\n        negative = true;\r\n        value = 0 - value;\r\n    }\r\n\r\n    // set default precision, if not set explicitly\r\n    if (!(flags & FLAGS_PRECISION)) {\r\n        prec = PRINTF_DEFAULT_FLOAT_PRECISION;\r\n    }\r\n    // limit precision to 9, cause a prec >= 10 can lead to overflow errors\r\n    while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) {\r\n        buf[len++] = '0';\r\n        prec--;\r\n    }\r\n\r\n    int whole = (int) value;\r\n    double tmp = (value - whole) * pow10[prec];\r\n    unsigned long frac = (unsigned long) tmp;\r\n    diff = tmp - frac;\r\n\r\n    if (diff > 0.5) {\r\n        ++frac;\r\n        // handle rollover, e.g. case 0.99 with prec 1 is 1.0\r\n        if (frac >= pow10[prec]) {\r\n            frac = 0;\r\n            ++whole;\r\n        }\r\n    } else if (diff < 0.5) {\r\n    } else if ((frac == 0U) || (frac & 1U)) {\r\n        // if halfway, round up if odd OR if last digit is 0\r\n        ++frac;\r\n    }\r\n\r\n    if (prec == 0U) {\r\n        diff = value - (double) whole;\r\n        if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) {\r\n            // exactly 0.5 and ODD, then round up\r\n            // 1.5 -> 2, but 2.5 -> 2\r\n            ++whole;\r\n        }\r\n    } else {\r\n        unsigned int count = prec;\r\n        // now do fractional part, as an unsigned number\r\n        while (len < PRINTF_FTOA_BUFFER_SIZE) {\r\n            --count;\r\n            buf[len++] = (char) (48U + (frac % 10U));\r\n            if (!(frac /= 10U)) {\r\n                break;\r\n            }\r\n        }\r\n        // add extra 0s\r\n        while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) {\r\n            buf[len++] = '0';\r\n        }\r\n        if (len < PRINTF_FTOA_BUFFER_SIZE) {\r\n            // add decimal\r\n            buf[len++] = '.';\r\n        }\r\n    }\r\n\r\n    // do whole part, number is reversed\r\n    while (len < PRINTF_FTOA_BUFFER_SIZE) {\r\n        buf[len++] = (char) (48 + (whole % 10));\r\n        if (!(whole /= 10)) {\r\n            break;\r\n        }\r\n    }\r\n\r\n    // pad leading zeros\r\n    if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) {\r\n        if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) {\r\n            width--;\r\n        }\r\n        while ((len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) {\r\n            buf[len++] = '0';\r\n        }\r\n    }\r\n\r\n    if (len < PRINTF_FTOA_BUFFER_SIZE) {\r\n        if (negative) {\r\n            buf[len++] = '-';\r\n        } else if (flags & FLAGS_PLUS) {\r\n            buf[len++] = '+';  // ignore the space if the '+' exists\r\n        } else if (flags & FLAGS_SPACE) {\r\n            buf[len++] = ' ';\r\n        }\r\n    }\r\n\r\n    return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags);\r\n}\r\n\r\n\r\n#if defined(PRINTF_SUPPORT_EXPONENTIAL)\r\n\r\n// internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse <m.jasperse@gmail.com>\r\nstatic size_t\r\n_etoa(out_fct_type out, char *buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width,\r\n      unsigned int flags) {\r\n    // check for NaN and special values\r\n    if ((value != value) || (value > DBL_MAX) || (value < -DBL_MAX)) {\r\n        return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags);\r\n    }\r\n\r\n    // determine the sign\r\n    const bool negative = value < 0;\r\n    if (negative) {\r\n        value = -value;\r\n    }\r\n\r\n    // default precision\r\n    if (!(flags & FLAGS_PRECISION)) {\r\n        prec = PRINTF_DEFAULT_FLOAT_PRECISION;\r\n    }\r\n\r\n    // determine the decimal exponent\r\n    // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c)\r\n    union {\r\n        uint64_t U;\r\n        double F;\r\n    } conv;\r\n\r\n    conv.F = value;\r\n    int exp2 = (int) ((conv.U >> 52U) & 0x07FFU) - 1023;           // effectively log2\r\n    conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U);  // drop the exponent so conv.F is now in [1,2)\r\n    // now approximate log10 from the log2 integer part and an expansion of ln around 1.5\r\n    int expval = (int) (0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168);\r\n    // now we want to compute 10^expval but we want to be sure it won't overflow\r\n    exp2 = (int) (expval * 3.321928094887362 + 0.5);\r\n    const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453;\r\n    const double z2 = z * z;\r\n    conv.U = (uint64_t) (exp2 + 1023) << 52U;\r\n    // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex\r\n    conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14)))));\r\n    // correct for rounding errors\r\n    if (value < conv.F) {\r\n        expval--;\r\n        conv.F /= 10;\r\n    }\r\n\r\n    // the exponent format is \"%+03d\" and largest value is \"307\", so set aside 4-5 characters\r\n    unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U;\r\n\r\n    // in \"%g\" mode, \"prec\" is the number of *significant figures* not decimals\r\n    if (flags & FLAGS_ADAPT_EXP) {\r\n        // do we want to fall-back to \"%f\" mode?\r\n        if ((value >= 1e-4) && (value < 1e6)) {\r\n            if ((int) prec > expval) {\r\n                prec = (unsigned) ((int) prec - expval - 1);\r\n            } else {\r\n                prec = 0;\r\n            }\r\n            flags |= FLAGS_PRECISION;   // make sure _ftoa respects precision\r\n            // no characters in exponent\r\n            minwidth = 0U;\r\n            expval = 0;\r\n        } else {\r\n            // we use one sigfig for the whole part\r\n            if ((prec > 0) && (flags & FLAGS_PRECISION)) {\r\n                --prec;\r\n            }\r\n        }\r\n    }\r\n\r\n    // will everything fit?\r\n    unsigned int fwidth = width;\r\n    if (width > minwidth) {\r\n        // we didn't fall-back so subtract the characters required for the exponent\r\n        fwidth -= minwidth;\r\n    } else {\r\n        // not enough characters, so go back to default sizing\r\n        fwidth = 0U;\r\n    }\r\n    if ((flags & FLAGS_LEFT) && minwidth) {\r\n        // if we're padding on the right, DON'T pad the floating part\r\n        fwidth = 0U;\r\n    }\r\n\r\n    // rescale the float value\r\n    if (expval) {\r\n        value /= conv.F;\r\n    }\r\n\r\n    // output the floating part\r\n    const size_t start_idx = idx;\r\n    idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP);\r\n\r\n    // output the exponent part\r\n    if (minwidth) {\r\n        // output the exponential symbol\r\n        out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen);\r\n        // output the exponent value\r\n        idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, minwidth - 1,\r\n                         FLAGS_ZEROPAD | FLAGS_PLUS);\r\n        // might need to right-pad spaces\r\n        if (flags & FLAGS_LEFT) {\r\n            while (idx - start_idx < width) out(' ', buffer, idx++, maxlen);\r\n        }\r\n    }\r\n    return idx;\r\n}\r\n\r\n#endif  // PRINTF_SUPPORT_EXPONENTIAL\r\n#endif  // PRINTF_SUPPORT_FLOAT\r\n\r\n\r\n// internal vsnprintf\r\nstatic int _vsnprintf(out_fct_type out, char *buffer, const size_t maxlen, const char *format, va_list va) {\r\n    unsigned int flags, width, precision, n;\r\n    size_t idx = 0U;\r\n\r\n    if (!buffer) {\r\n        // use null output function\r\n        out = _out_null;\r\n    }\r\n\r\n    while (*format) {\r\n        // format specifier?  %[flags][width][.precision][length]\r\n        if (*format != '%') {\r\n            // no\r\n            out(*format, buffer, idx++, maxlen);\r\n            format++;\r\n            continue;\r\n        } else {\r\n            // yes, evaluate it\r\n            format++;\r\n        }\r\n\r\n        // evaluate flags\r\n        flags = 0U;\r\n        do {\r\n            switch (*format) {\r\n                case '0':\r\n                    flags |= FLAGS_ZEROPAD;\r\n                    format++;\r\n                    n = 1U;\r\n                    break;\r\n                case '-':\r\n                    flags |= FLAGS_LEFT;\r\n                    format++;\r\n                    n = 1U;\r\n                    break;\r\n                case '+':\r\n                    flags |= FLAGS_PLUS;\r\n                    format++;\r\n                    n = 1U;\r\n                    break;\r\n                case ' ':\r\n                    flags |= FLAGS_SPACE;\r\n                    format++;\r\n                    n = 1U;\r\n                    break;\r\n                case '#':\r\n                    flags |= FLAGS_HASH;\r\n                    format++;\r\n                    n = 1U;\r\n                    break;\r\n                default :\r\n                    n = 0U;\r\n                    break;\r\n            }\r\n        } while (n);\r\n\r\n        // evaluate width field\r\n        width = 0U;\r\n        if (_is_digit(*format)) {\r\n            width = _atoi(&format);\r\n        } else if (*format == '*') {\r\n            const int w = va_arg(va, int);\r\n            if (w < 0) {\r\n                flags |= FLAGS_LEFT;    // reverse padding\r\n                width = (unsigned int) -w;\r\n            } else {\r\n                width = (unsigned int) w;\r\n            }\r\n            format++;\r\n        }\r\n\r\n        // evaluate precision field\r\n        precision = 0U;\r\n        if (*format == '.') {\r\n            flags |= FLAGS_PRECISION;\r\n            format++;\r\n            if (_is_digit(*format)) {\r\n                precision = _atoi(&format);\r\n            } else if (*format == '*') {\r\n                const int prec = (int) va_arg(va, int);\r\n                precision = prec > 0 ? (unsigned int) prec : 0U;\r\n                format++;\r\n            }\r\n        }\r\n\r\n        // evaluate length field\r\n        switch (*format) {\r\n            case 'l' :\r\n                flags |= FLAGS_LONG;\r\n                format++;\r\n                if (*format == 'l') {\r\n                    flags |= FLAGS_LONG_LONG;\r\n                    format++;\r\n                }\r\n                break;\r\n            case 'h' :\r\n                flags |= FLAGS_SHORT;\r\n                format++;\r\n                if (*format == 'h') {\r\n                    flags |= FLAGS_CHAR;\r\n                    format++;\r\n                }\r\n                break;\r\n#if defined(PRINTF_SUPPORT_PTRDIFF_T)\r\n            case 't' :\r\n                flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);\r\n                format++;\r\n                break;\r\n#endif\r\n            case 'j' :\r\n                flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);\r\n                format++;\r\n                break;\r\n            case 'z' :\r\n                flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);\r\n                format++;\r\n                break;\r\n            default :\r\n                break;\r\n        }\r\n\r\n        // evaluate specifier\r\n        switch (*format) {\r\n            case 'd' :\r\n            case 'i' :\r\n            case 'u' :\r\n            case 'x' :\r\n            case 'X' :\r\n            case 'o' :\r\n            case 'b' : {\r\n                // set the base\r\n                unsigned int base;\r\n                if (*format == 'x' || *format == 'X') {\r\n                    base = 16U;\r\n                } else if (*format == 'o') {\r\n                    base = 8U;\r\n                } else if (*format == 'b') {\r\n                    base = 2U;\r\n                } else {\r\n                    base = 10U;\r\n                    flags &= ~FLAGS_HASH;   // no hash for dec format\r\n                }\r\n                // uppercase\r\n                if (*format == 'X') {\r\n                    flags |= FLAGS_UPPERCASE;\r\n                }\r\n\r\n                // no plus or space flag for u, x, X, o, b\r\n                if ((*format != 'i') && (*format != 'd')) {\r\n                    flags &= ~(FLAGS_PLUS | FLAGS_SPACE);\r\n                }\r\n\r\n                // ignore '0' flag when precision is given\r\n                if (flags & FLAGS_PRECISION) {\r\n                    flags &= ~FLAGS_ZEROPAD;\r\n                }\r\n\r\n                // convert the integer\r\n                if ((*format == 'i') || (*format == 'd')) {\r\n                    // signed\r\n                    if (flags & FLAGS_LONG_LONG) {\r\n#if defined(PRINTF_SUPPORT_LONG_LONG)\r\n                        const long long value = va_arg(va, long long);\r\n                        idx = _ntoa_long_long(out, buffer, idx, maxlen,\r\n                                              (unsigned long long) (value > 0 ? value : 0 - value), value < 0, base,\r\n                                              precision, width, flags);\r\n#endif\r\n                    } else if (flags & FLAGS_LONG) {\r\n                        const long value = va_arg(va, long);\r\n                        idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long) (value > 0 ? value : 0 - value),\r\n                                         value < 0, base, precision, width, flags);\r\n                    } else {\r\n                        const int value = (flags & FLAGS_CHAR) ? (char) va_arg(va, int) : (flags & FLAGS_SHORT)\r\n                                                                                          ? (short int) va_arg(va, int)\r\n                                                                                          : va_arg(va, int);\r\n                        idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int) (value > 0 ? value : 0 - value),\r\n                                         value < 0, base, precision, width, flags);\r\n                    }\r\n                } else {\r\n                    // unsigned\r\n                    if (flags & FLAGS_LONG_LONG) {\r\n#if defined(PRINTF_SUPPORT_LONG_LONG)\r\n                        idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base,\r\n                                              precision, width, flags);\r\n#endif\r\n                    } else if (flags & FLAGS_LONG) {\r\n                        idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision,\r\n                                         width, flags);\r\n                    } else {\r\n                        const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char) va_arg(va, unsigned int)\r\n                                                                        : (flags & FLAGS_SHORT)\r\n                                                                          ? (unsigned short int) va_arg(va,\r\n                                                                                                        unsigned int)\r\n                                                                          : va_arg(va, unsigned int);\r\n                        idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags);\r\n                    }\r\n                }\r\n                format++;\r\n                break;\r\n            }\r\n#if defined(PRINTF_SUPPORT_FLOAT)\r\n            case 'f' :\r\n            case 'F' :\r\n                if (*format == 'F') flags |= FLAGS_UPPERCASE;\r\n                idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);\r\n                format++;\r\n                break;\r\n#if defined(PRINTF_SUPPORT_EXPONENTIAL)\r\n            case 'e':\r\n            case 'E':\r\n            case 'g':\r\n            case 'G':\r\n                if ((*format == 'g') || (*format == 'G')) flags |= FLAGS_ADAPT_EXP;\r\n                if ((*format == 'E') || (*format == 'G')) flags |= FLAGS_UPPERCASE;\r\n                idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);\r\n                format++;\r\n                break;\r\n#endif  // PRINTF_SUPPORT_EXPONENTIAL\r\n#endif  // PRINTF_SUPPORT_FLOAT\r\n            case 'c' : {\r\n                unsigned int l = 1U;\r\n                // pre padding\r\n                if (!(flags & FLAGS_LEFT)) {\r\n                    while (l++ < width) {\r\n                        out(' ', buffer, idx++, maxlen);\r\n                    }\r\n                }\r\n                // char output\r\n                out((char) va_arg(va, int), buffer, idx++, maxlen);\r\n                // post padding\r\n                if (flags & FLAGS_LEFT) {\r\n                    while (l++ < width) {\r\n                        out(' ', buffer, idx++, maxlen);\r\n                    }\r\n                }\r\n                format++;\r\n                break;\r\n            }\r\n\r\n            case 's' : {\r\n                const char *p = va_arg(va, char*);\r\n                unsigned int l = _strnlen_s(p, precision ? precision : (size_t) -1);\r\n                // pre padding\r\n                if (flags & FLAGS_PRECISION) {\r\n                    l = (l < precision ? l : precision);\r\n                }\r\n                if (!(flags & FLAGS_LEFT)) {\r\n                    while (l++ < width) {\r\n                        out(' ', buffer, idx++, maxlen);\r\n                    }\r\n                }\r\n                // string output\r\n                while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) {\r\n                    out(*(p++), buffer, idx++, maxlen);\r\n                }\r\n                // post padding\r\n                if (flags & FLAGS_LEFT) {\r\n                    while (l++ < width) {\r\n                        out(' ', buffer, idx++, maxlen);\r\n                    }\r\n                }\r\n                format++;\r\n                break;\r\n            }\r\n\r\n            case 'p' : {\r\n                width = sizeof(void *) * 2U;\r\n                flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE;\r\n#if defined(PRINTF_SUPPORT_LONG_LONG)\r\n                const bool is_ll = sizeof(uintptr_t) == sizeof(long long);\r\n                if (is_ll) {\r\n                    idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t) va_arg(va, void*), false, 16U,\r\n                                          precision, width, flags);\r\n                } else {\r\n#endif\r\n                    idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long) ((uintptr_t) va_arg(va, void*)), false,\r\n                                     16U, precision, width, flags);\r\n#if defined(PRINTF_SUPPORT_LONG_LONG)\r\n                }\r\n#endif\r\n                format++;\r\n                break;\r\n            }\r\n\r\n            case '%' :\r\n                out('%', buffer, idx++, maxlen);\r\n                format++;\r\n                break;\r\n\r\n            default :\r\n                out(*format, buffer, idx++, maxlen);\r\n                format++;\r\n                break;\r\n        }\r\n    }\r\n\r\n    // termination\r\n    out((char) 0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen);\r\n\r\n    // return written chars without terminating \\0\r\n    return (int) idx;\r\n}\r\n\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n\r\nint printf_(const char *format, ...) {\r\n    va_list va;\r\n    va_start(va, format);\r\n    char buffer[1];\r\n    const int ret = _vsnprintf(_out_char, buffer, (size_t) -1, format, va);\r\n    va_end(va);\r\n    return ret;\r\n}\r\n\r\n\r\nint sprintf_(char *buffer, const char *format, ...) {\r\n    va_list va;\r\n    va_start(va, format);\r\n    const int ret = _vsnprintf(_out_buffer, buffer, (size_t) -1, format, va);\r\n    va_end(va);\r\n    return ret;\r\n}\r\n\r\n\r\nint snprintf_(char *buffer, size_t count, const char *format, ...) {\r\n    va_list va;\r\n    va_start(va, format);\r\n    const int ret = _vsnprintf(_out_buffer, buffer, count, format, va);\r\n    va_end(va);\r\n    return ret;\r\n}\r\n\r\n\r\nint vprintf_(const char *format, va_list va) {\r\n    char buffer[1];\r\n    return _vsnprintf(_out_char, buffer, (size_t) -1, format, va);\r\n}\r\n\r\n\r\nint vsnprintf_(char *buffer, size_t count, const char *format, va_list va) {\r\n    return _vsnprintf(_out_buffer, buffer, count, format, va);\r\n}\r\n\r\n\r\nint fctprintf(void (*out)(char character, void *arg), void *arg, const char *format, ...) {\r\n    va_list va;\r\n    va_start(va, format);\r\n    const out_fct_wrap_type out_fct_wrap = {out, arg};\r\n    const int ret = _vsnprintf(_out_fct, (char *) (uintptr_t) &out_fct_wrap, (size_t) -1, format, va);\r\n    va_end(va);\r\n    return ret;\r\n}\r\n"
  },
  {
    "path": "external/printf/printf.h",
    "content": "///////////////////////////////////////////////////////////////////////////////\r\n// \\author (c) Marco Paland (info@paland.com)\r\n//             2014-2019, PALANDesign Hannover, Germany\r\n//\r\n// \\license The MIT License (MIT)\r\n//\r\n// Permission is hereby granted, free of charge, to any person obtaining a copy\r\n// of this software and associated documentation files (the \"Software\"), to deal\r\n// in the Software without restriction, including without limitation the rights\r\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r\n// copies of the Software, and to permit persons to whom the Software is\r\n// furnished to do so, subject to the following conditions:\r\n// \r\n// The above copyright notice and this permission notice shall be included in\r\n// all copies or substantial portions of the Software.\r\n// \r\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\r\n// THE SOFTWARE.\r\n//\r\n// \\brief Tiny printf, sprintf and snprintf implementation, optimized for speed on\r\n//        embedded systems with a very limited resources.\r\n//        Use this instead of bloated standard/newlib printf.\r\n//        These routines are thread safe and reentrant.\r\n//\r\n///////////////////////////////////////////////////////////////////////////////\r\n\r\n#ifndef _PRINTF_H_\r\n#define _PRINTF_H_\r\n\r\n#include <stdarg.h>\r\n#include <stddef.h>\r\n\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\n\r\n/**\r\n * Output a character to a custom device like UART, used by the printf() function\r\n * This function is declared here only. You have to write your custom implementation somewhere\r\n * \\param character Character to output\r\n */\r\nvoid _putchar(char character);\r\n\r\n\r\n/**\r\n * Tiny printf implementation\r\n * You have to implement _putchar if you use printf()\r\n * To avoid conflicts with the regular printf() API it is overridden by macro defines\r\n * and internal underscore-appended functions like printf_() are used\r\n * \\param format A string that specifies the format of the output\r\n * \\return The number of characters that are written into the array, not counting the terminating null character\r\n */\r\n#define printf printf_\r\nint printf_(const char* format, ...);\r\n\r\n\r\n/**\r\n * Tiny sprintf implementation\r\n * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD!\r\n * \\param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output!\r\n * \\param format A string that specifies the format of the output\r\n * \\return The number of characters that are WRITTEN into the buffer, not counting the terminating null character\r\n */\r\n#define sprintf sprintf_\r\nint sprintf_(char* buffer, const char* format, ...);\r\n\r\n\r\n/**\r\n * Tiny snprintf/vsnprintf implementation\r\n * \\param buffer A pointer to the buffer where to store the formatted string\r\n * \\param count The maximum number of characters to store in the buffer, including a terminating null character\r\n * \\param format A string that specifies the format of the output\r\n * \\param va A value identifying a variable arguments list\r\n * \\return The number of characters that COULD have been written into the buffer, not counting the terminating\r\n *         null character. A value equal or larger than count indicates truncation. Only when the returned value\r\n *         is non-negative and less than count, the string has been completely written.\r\n */\r\n#define snprintf  snprintf_\r\n#define vsnprintf vsnprintf_\r\nint  snprintf_(char* buffer, size_t count, const char* format, ...);\r\nint vsnprintf_(char* buffer, size_t count, const char* format, va_list va);\r\n\r\n\r\n/**\r\n * Tiny vprintf implementation\r\n * \\param format A string that specifies the format of the output\r\n * \\param va A value identifying a variable arguments list\r\n * \\return The number of characters that are WRITTEN into the buffer, not counting the terminating null character\r\n */\r\n#define vprintf vprintf_\r\nint vprintf_(const char* format, va_list va);\r\n\r\n\r\n/**\r\n * printf with output function\r\n * You may use this as dynamic alternative to printf() with its fixed _putchar() output\r\n * \\param out An output function which takes one character and an argument pointer\r\n * \\param arg An argument pointer for user data passed to output function\r\n * \\param format A string that specifies the format of the output\r\n * \\return The number of characters that are sent to the output function, not counting the terminating null character\r\n */\r\nint fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...);\r\n\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n\r\n#endif  // _PRINTF_H_\r\n"
  },
  {
    "path": "external/printf/test/catch.hpp",
    "content": "/*\r\n *  Catch v2.7.0\r\n *  Generated: 2019-03-07 21:34:30.252164\r\n *  ----------------------------------------------------------\r\n *  This file has been merged from multiple headers. Please don't edit it directly\r\n *  Copyright (c) 2019 Two Blue Cubes Ltd. All rights reserved.\r\n *\r\n *  Distributed under the Boost Software License, Version 1.0. (See accompanying\r\n *  file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)\r\n */\r\n#ifndef TWOBLUECUBES_SINGLE_INCLUDE_CATCH_HPP_INCLUDED\r\n#define TWOBLUECUBES_SINGLE_INCLUDE_CATCH_HPP_INCLUDED\r\n// start catch.hpp\r\n\r\n\r\n#define CATCH_VERSION_MAJOR 2\r\n#define CATCH_VERSION_MINOR 7\r\n#define CATCH_VERSION_PATCH 0\r\n\r\n#ifdef __clang__\r\n#    pragma clang system_header\r\n#elif defined __GNUC__\r\n#    pragma GCC system_header\r\n#endif\r\n\r\n// start catch_suppress_warnings.h\r\n\r\n#ifdef __clang__\r\n#   ifdef __ICC // icpc defines the __clang__ macro\r\n#       pragma warning(push)\r\n#       pragma warning(disable: 161 1682)\r\n#   else // __ICC\r\n#       pragma clang diagnostic push\r\n#       pragma clang diagnostic ignored \"-Wpadded\"\r\n#       pragma clang diagnostic ignored \"-Wswitch-enum\"\r\n#       pragma clang diagnostic ignored \"-Wcovered-switch-default\"\r\n#    endif\r\n#elif defined __GNUC__\r\n     // Because REQUIREs trigger GCC's -Wparentheses, and because still\r\n     // supported version of g++ have only buggy support for _Pragmas,\r\n     // Wparentheses have to be suppressed globally.\r\n#    pragma GCC diagnostic ignored \"-Wparentheses\" // See #674 for details\r\n\r\n#    pragma GCC diagnostic push\r\n#    pragma GCC diagnostic ignored \"-Wunused-variable\"\r\n#    pragma GCC diagnostic ignored \"-Wpadded\"\r\n#endif\r\n// end catch_suppress_warnings.h\r\n#if defined(CATCH_CONFIG_MAIN) || defined(CATCH_CONFIG_RUNNER)\r\n#  define CATCH_IMPL\r\n#  define CATCH_CONFIG_ALL_PARTS\r\n#endif\r\n\r\n// In the impl file, we want to have access to all parts of the headers\r\n// Can also be used to sanely support PCHs\r\n#if defined(CATCH_CONFIG_ALL_PARTS)\r\n#  define CATCH_CONFIG_EXTERNAL_INTERFACES\r\n#  if defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#    undef CATCH_CONFIG_DISABLE_MATCHERS\r\n#  endif\r\n#  if !defined(CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER)\r\n#    define CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER\r\n#  endif\r\n#endif\r\n\r\n#if !defined(CATCH_CONFIG_IMPL_ONLY)\r\n// start catch_platform.h\r\n\r\n#ifdef __APPLE__\r\n# include <TargetConditionals.h>\r\n# if TARGET_OS_OSX == 1\r\n#  define CATCH_PLATFORM_MAC\r\n# elif TARGET_OS_IPHONE == 1\r\n#  define CATCH_PLATFORM_IPHONE\r\n# endif\r\n\r\n#elif defined(linux) || defined(__linux) || defined(__linux__)\r\n#  define CATCH_PLATFORM_LINUX\r\n\r\n#elif defined(WIN32) || defined(__WIN32__) || defined(_WIN32) || defined(_MSC_VER) || defined(__MINGW32__)\r\n#  define CATCH_PLATFORM_WINDOWS\r\n#endif\r\n\r\n// end catch_platform.h\r\n\r\n#ifdef CATCH_IMPL\r\n#  ifndef CLARA_CONFIG_MAIN\r\n#    define CLARA_CONFIG_MAIN_NOT_DEFINED\r\n#    define CLARA_CONFIG_MAIN\r\n#  endif\r\n#endif\r\n\r\n// start catch_user_interfaces.h\r\n\r\nnamespace Catch {\r\n    unsigned int rngSeed();\r\n}\r\n\r\n// end catch_user_interfaces.h\r\n// start catch_tag_alias_autoregistrar.h\r\n\r\n// start catch_common.h\r\n\r\n// start catch_compiler_capabilities.h\r\n\r\n// Detect a number of compiler features - by compiler\r\n// The following features are defined:\r\n//\r\n// CATCH_CONFIG_COUNTER : is the __COUNTER__ macro supported?\r\n// CATCH_CONFIG_WINDOWS_SEH : is Windows SEH supported?\r\n// CATCH_CONFIG_POSIX_SIGNALS : are POSIX signals supported?\r\n// CATCH_CONFIG_DISABLE_EXCEPTIONS : Are exceptions enabled?\r\n// ****************\r\n// Note to maintainers: if new toggles are added please document them\r\n// in configuration.md, too\r\n// ****************\r\n\r\n// In general each macro has a _NO_<feature name> form\r\n// (e.g. CATCH_CONFIG_NO_POSIX_SIGNALS) which disables the feature.\r\n// Many features, at point of detection, define an _INTERNAL_ macro, so they\r\n// can be combined, en-mass, with the _NO_ forms later.\r\n\r\n#ifdef __cplusplus\r\n\r\n#  if (__cplusplus >= 201402L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201402L)\r\n#    define CATCH_CPP14_OR_GREATER\r\n#  endif\r\n\r\n#  if (__cplusplus >= 201703L) || (defined(_MSVC_LANG) && _MSVC_LANG >= 201703L)\r\n#    define CATCH_CPP17_OR_GREATER\r\n#  endif\r\n\r\n#endif\r\n\r\n#if defined(CATCH_CPP17_OR_GREATER)\r\n#  define CATCH_INTERNAL_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS\r\n#endif\r\n\r\n#ifdef __clang__\r\n\r\n#       define CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n            _Pragma( \"clang diagnostic push\" ) \\\r\n            _Pragma( \"clang diagnostic ignored \\\"-Wexit-time-destructors\\\"\" ) \\\r\n            _Pragma( \"clang diagnostic ignored \\\"-Wglobal-constructors\\\"\")\r\n#       define CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \\\r\n            _Pragma( \"clang diagnostic pop\" )\r\n\r\n#       define CATCH_INTERNAL_SUPPRESS_PARENTHESES_WARNINGS \\\r\n            _Pragma( \"clang diagnostic push\" ) \\\r\n            _Pragma( \"clang diagnostic ignored \\\"-Wparentheses\\\"\" )\r\n#       define CATCH_INTERNAL_UNSUPPRESS_PARENTHESES_WARNINGS \\\r\n            _Pragma( \"clang diagnostic pop\" )\r\n\r\n#       define CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS \\\r\n            _Pragma( \"clang diagnostic push\" ) \\\r\n            _Pragma( \"clang diagnostic ignored \\\"-Wunused-variable\\\"\" )\r\n#       define CATCH_INTERNAL_UNSUPPRESS_UNUSED_WARNINGS \\\r\n            _Pragma( \"clang diagnostic pop\" )\r\n\r\n#endif // __clang__\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Assume that non-Windows platforms support posix signals by default\r\n#if !defined(CATCH_PLATFORM_WINDOWS)\r\n    #define CATCH_INTERNAL_CONFIG_POSIX_SIGNALS\r\n#endif\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// We know some environments not to support full POSIX signals\r\n#if defined(__CYGWIN__) || defined(__QNX__) || defined(__EMSCRIPTEN__) || defined(__DJGPP__)\r\n    #define CATCH_INTERNAL_CONFIG_NO_POSIX_SIGNALS\r\n#endif\r\n\r\n#ifdef __OS400__\r\n#       define CATCH_INTERNAL_CONFIG_NO_POSIX_SIGNALS\r\n#       define CATCH_CONFIG_COLOUR_NONE\r\n#endif\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Android somehow still does not support std::to_string\r\n#if defined(__ANDROID__)\r\n#    define CATCH_INTERNAL_CONFIG_NO_CPP11_TO_STRING\r\n#endif\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Not all Windows environments support SEH properly\r\n#if defined(__MINGW32__)\r\n#    define CATCH_INTERNAL_CONFIG_NO_WINDOWS_SEH\r\n#endif\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// PS4\r\n#if defined(__ORBIS__)\r\n#    define CATCH_INTERNAL_CONFIG_NO_NEW_CAPTURE\r\n#endif\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Cygwin\r\n#ifdef __CYGWIN__\r\n\r\n// Required for some versions of Cygwin to declare gettimeofday\r\n// see: http://stackoverflow.com/questions/36901803/gettimeofday-not-declared-in-this-scope-cygwin\r\n#   define _BSD_SOURCE\r\n// some versions of cygwin (most) do not support std::to_string. Use the libstd check.\r\n// https://gcc.gnu.org/onlinedocs/gcc-4.8.2/libstdc++/api/a01053_source.html line 2812-2813\r\n# if !((__cplusplus >= 201103L) && defined(_GLIBCXX_USE_C99) \\\r\n\t       && !defined(_GLIBCXX_HAVE_BROKEN_VSWPRINTF))\r\n\r\n#\tdefine CATCH_INTERNAL_CONFIG_NO_CPP11_TO_STRING\r\n\r\n# endif\r\n#endif // __CYGWIN__\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Visual C++\r\n#ifdef _MSC_VER\r\n\r\n#  if _MSC_VER >= 1900 // Visual Studio 2015 or newer\r\n#    define CATCH_INTERNAL_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS\r\n#  endif\r\n\r\n// Universal Windows platform does not support SEH\r\n// Or console colours (or console at all...)\r\n#  if defined(WINAPI_FAMILY) && (WINAPI_FAMILY == WINAPI_FAMILY_APP)\r\n#    define CATCH_CONFIG_COLOUR_NONE\r\n#  else\r\n#    define CATCH_INTERNAL_CONFIG_WINDOWS_SEH\r\n#  endif\r\n\r\n// MSVC traditional preprocessor needs some workaround for __VA_ARGS__\r\n// _MSVC_TRADITIONAL == 0 means new conformant preprocessor\r\n// _MSVC_TRADITIONAL == 1 means old traditional non-conformant preprocessor\r\n#  if !defined(_MSVC_TRADITIONAL) || (defined(_MSVC_TRADITIONAL) && _MSVC_TRADITIONAL)\r\n#    define CATCH_INTERNAL_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n#  endif\r\n\r\n#endif // _MSC_VER\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Check if we are compiled with -fno-exceptions or equivalent\r\n#if defined(__EXCEPTIONS) || defined(__cpp_exceptions) || defined(_CPPUNWIND)\r\n#  define CATCH_INTERNAL_CONFIG_EXCEPTIONS_ENABLED\r\n#endif\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// DJGPP\r\n#ifdef __DJGPP__\r\n#  define CATCH_INTERNAL_CONFIG_NO_WCHAR\r\n#endif // __DJGPP__\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Embarcadero C++Build\r\n#if defined(__BORLANDC__)\r\n    #define CATCH_INTERNAL_CONFIG_POLYFILL_ISNAN\r\n#endif\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n\r\n// Use of __COUNTER__ is suppressed during code analysis in\r\n// CLion/AppCode 2017.2.x and former, because __COUNTER__ is not properly\r\n// handled by it.\r\n// Otherwise all supported compilers support COUNTER macro,\r\n// but user still might want to turn it off\r\n#if ( !defined(__JETBRAINS_IDE__) || __JETBRAINS_IDE__ >= 20170300L )\r\n    #define CATCH_INTERNAL_CONFIG_COUNTER\r\n#endif\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Check if string_view is available and usable\r\n// The check is split apart to work around v140 (VS2015) preprocessor issue...\r\n#if defined(__has_include)\r\n#if __has_include(<string_view>) && defined(CATCH_CPP17_OR_GREATER)\r\n#    define CATCH_INTERNAL_CONFIG_CPP17_STRING_VIEW\r\n#endif\r\n#endif\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Check if optional is available and usable\r\n#if defined(__has_include)\r\n#  if __has_include(<optional>) && defined(CATCH_CPP17_OR_GREATER)\r\n#    define CATCH_INTERNAL_CONFIG_CPP17_OPTIONAL\r\n#  endif // __has_include(<optional>) && defined(CATCH_CPP17_OR_GREATER)\r\n#endif // __has_include\r\n\r\n////////////////////////////////////////////////////////////////////////////////\r\n// Check if variant is available and usable\r\n#if defined(__has_include)\r\n#  if __has_include(<variant>) && defined(CATCH_CPP17_OR_GREATER)\r\n#    if defined(__clang__) && (__clang_major__ < 8)\r\n       // work around clang bug with libstdc++ https://bugs.llvm.org/show_bug.cgi?id=31852\r\n       // fix should be in clang 8, workaround in libstdc++ 8.2\r\n#      include <ciso646>\r\n#      if defined(__GLIBCXX__) && defined(_GLIBCXX_RELEASE) && (_GLIBCXX_RELEASE < 9)\r\n#        define CATCH_CONFIG_NO_CPP17_VARIANT\r\n#      else\r\n#        define CATCH_INTERNAL_CONFIG_CPP17_VARIANT\r\n#      endif // defined(__GLIBCXX__) && defined(_GLIBCXX_RELEASE) && (_GLIBCXX_RELEASE < 9)\r\n#    else\r\n#      define CATCH_INTERNAL_CONFIG_CPP17_VARIANT\r\n#    endif // defined(__clang__) && (__clang_major__ < 8)\r\n#  endif // __has_include(<variant>) && defined(CATCH_CPP17_OR_GREATER)\r\n#endif // __has_include\r\n\r\n#if defined(CATCH_INTERNAL_CONFIG_COUNTER) && !defined(CATCH_CONFIG_NO_COUNTER) && !defined(CATCH_CONFIG_COUNTER)\r\n#   define CATCH_CONFIG_COUNTER\r\n#endif\r\n#if defined(CATCH_INTERNAL_CONFIG_WINDOWS_SEH) && !defined(CATCH_CONFIG_NO_WINDOWS_SEH) && !defined(CATCH_CONFIG_WINDOWS_SEH) && !defined(CATCH_INTERNAL_CONFIG_NO_WINDOWS_SEH)\r\n#   define CATCH_CONFIG_WINDOWS_SEH\r\n#endif\r\n// This is set by default, because we assume that unix compilers are posix-signal-compatible by default.\r\n#if defined(CATCH_INTERNAL_CONFIG_POSIX_SIGNALS) && !defined(CATCH_INTERNAL_CONFIG_NO_POSIX_SIGNALS) && !defined(CATCH_CONFIG_NO_POSIX_SIGNALS) && !defined(CATCH_CONFIG_POSIX_SIGNALS)\r\n#   define CATCH_CONFIG_POSIX_SIGNALS\r\n#endif\r\n// This is set by default, because we assume that compilers with no wchar_t support are just rare exceptions.\r\n#if !defined(CATCH_INTERNAL_CONFIG_NO_WCHAR) && !defined(CATCH_CONFIG_NO_WCHAR) && !defined(CATCH_CONFIG_WCHAR)\r\n#   define CATCH_CONFIG_WCHAR\r\n#endif\r\n\r\n#if !defined(CATCH_INTERNAL_CONFIG_NO_CPP11_TO_STRING) && !defined(CATCH_CONFIG_NO_CPP11_TO_STRING) && !defined(CATCH_CONFIG_CPP11_TO_STRING)\r\n#    define CATCH_CONFIG_CPP11_TO_STRING\r\n#endif\r\n\r\n#if defined(CATCH_INTERNAL_CONFIG_CPP17_OPTIONAL) && !defined(CATCH_CONFIG_NO_CPP17_OPTIONAL) && !defined(CATCH_CONFIG_CPP17_OPTIONAL)\r\n#  define CATCH_CONFIG_CPP17_OPTIONAL\r\n#endif\r\n\r\n#if defined(CATCH_INTERNAL_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS) && !defined(CATCH_CONFIG_NO_CPP17_UNCAUGHT_EXCEPTIONS) && !defined(CATCH_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS)\r\n#  define CATCH_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS\r\n#endif\r\n\r\n#if defined(CATCH_INTERNAL_CONFIG_CPP17_STRING_VIEW) && !defined(CATCH_CONFIG_NO_CPP17_STRING_VIEW) && !defined(CATCH_CONFIG_CPP17_STRING_VIEW)\r\n#  define CATCH_CONFIG_CPP17_STRING_VIEW\r\n#endif\r\n\r\n#if defined(CATCH_INTERNAL_CONFIG_CPP17_VARIANT) && !defined(CATCH_CONFIG_NO_CPP17_VARIANT) && !defined(CATCH_CONFIG_CPP17_VARIANT)\r\n#  define CATCH_CONFIG_CPP17_VARIANT\r\n#endif\r\n\r\n#if defined(CATCH_CONFIG_EXPERIMENTAL_REDIRECT)\r\n#  define CATCH_INTERNAL_CONFIG_NEW_CAPTURE\r\n#endif\r\n\r\n#if defined(CATCH_INTERNAL_CONFIG_NEW_CAPTURE) && !defined(CATCH_INTERNAL_CONFIG_NO_NEW_CAPTURE) && !defined(CATCH_CONFIG_NO_NEW_CAPTURE) && !defined(CATCH_CONFIG_NEW_CAPTURE)\r\n#  define CATCH_CONFIG_NEW_CAPTURE\r\n#endif\r\n\r\n#if !defined(CATCH_INTERNAL_CONFIG_EXCEPTIONS_ENABLED) && !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS)\r\n#  define CATCH_CONFIG_DISABLE_EXCEPTIONS\r\n#endif\r\n\r\n#if defined(CATCH_INTERNAL_CONFIG_POLYFILL_ISNAN) && !defined(CATCH_CONFIG_NO_POLYFILL_ISNAN) && !defined(CATCH_CONFIG_POLYFILL_ISNAN)\r\n#  define CATCH_CONFIG_POLYFILL_ISNAN\r\n#endif\r\n\r\n#if !defined(CATCH_INTERNAL_SUPPRESS_PARENTHESES_WARNINGS)\r\n#   define CATCH_INTERNAL_SUPPRESS_PARENTHESES_WARNINGS\r\n#   define CATCH_INTERNAL_UNSUPPRESS_PARENTHESES_WARNINGS\r\n#endif\r\n#if !defined(CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS)\r\n#   define CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS\r\n#   define CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS\r\n#endif\r\n#if !defined(CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS)\r\n#   define CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS\r\n#   define CATCH_INTERNAL_UNSUPPRESS_UNUSED_WARNINGS\r\n#endif\r\n\r\n#if defined(CATCH_CONFIG_DISABLE_EXCEPTIONS)\r\n#define CATCH_TRY if ((true))\r\n#define CATCH_CATCH_ALL if ((false))\r\n#define CATCH_CATCH_ANON(type) if ((false))\r\n#else\r\n#define CATCH_TRY try\r\n#define CATCH_CATCH_ALL catch (...)\r\n#define CATCH_CATCH_ANON(type) catch (type)\r\n#endif\r\n\r\n#if defined(CATCH_INTERNAL_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR) && !defined(CATCH_CONFIG_NO_TRADITIONAL_MSVC_PREPROCESSOR) && !defined(CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR)\r\n#define CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n#endif\r\n\r\n// end catch_compiler_capabilities.h\r\n#define INTERNAL_CATCH_UNIQUE_NAME_LINE2( name, line ) name##line\r\n#define INTERNAL_CATCH_UNIQUE_NAME_LINE( name, line ) INTERNAL_CATCH_UNIQUE_NAME_LINE2( name, line )\r\n#ifdef CATCH_CONFIG_COUNTER\r\n#  define INTERNAL_CATCH_UNIQUE_NAME( name ) INTERNAL_CATCH_UNIQUE_NAME_LINE( name, __COUNTER__ )\r\n#else\r\n#  define INTERNAL_CATCH_UNIQUE_NAME( name ) INTERNAL_CATCH_UNIQUE_NAME_LINE( name, __LINE__ )\r\n#endif\r\n\r\n#include <iosfwd>\r\n#include <string>\r\n#include <cstdint>\r\n\r\n// We need a dummy global operator<< so we can bring it into Catch namespace later\r\nstruct Catch_global_namespace_dummy {};\r\nstd::ostream& operator<<(std::ostream&, Catch_global_namespace_dummy);\r\n\r\nnamespace Catch {\r\n\r\n    struct CaseSensitive { enum Choice {\r\n        Yes,\r\n        No\r\n    }; };\r\n\r\n    class NonCopyable {\r\n        NonCopyable( NonCopyable const& )              = delete;\r\n        NonCopyable( NonCopyable && )                  = delete;\r\n        NonCopyable& operator = ( NonCopyable const& ) = delete;\r\n        NonCopyable& operator = ( NonCopyable && )     = delete;\r\n\r\n    protected:\r\n        NonCopyable();\r\n        virtual ~NonCopyable();\r\n    };\r\n\r\n    struct SourceLineInfo {\r\n\r\n        SourceLineInfo() = delete;\r\n        SourceLineInfo( char const* _file, std::size_t _line ) noexcept\r\n        :   file( _file ),\r\n            line( _line )\r\n        {}\r\n\r\n        SourceLineInfo( SourceLineInfo const& other )            = default;\r\n        SourceLineInfo& operator = ( SourceLineInfo const& )     = default;\r\n        SourceLineInfo( SourceLineInfo&& )              noexcept = default;\r\n        SourceLineInfo& operator = ( SourceLineInfo&& ) noexcept = default;\r\n\r\n        bool empty() const noexcept;\r\n        bool operator == ( SourceLineInfo const& other ) const noexcept;\r\n        bool operator < ( SourceLineInfo const& other ) const noexcept;\r\n\r\n        char const* file;\r\n        std::size_t line;\r\n    };\r\n\r\n    std::ostream& operator << ( std::ostream& os, SourceLineInfo const& info );\r\n\r\n    // Bring in operator<< from global namespace into Catch namespace\r\n    // This is necessary because the overload of operator<< above makes\r\n    // lookup stop at namespace Catch\r\n    using ::operator<<;\r\n\r\n    // Use this in variadic streaming macros to allow\r\n    //    >> +StreamEndStop\r\n    // as well as\r\n    //    >> stuff +StreamEndStop\r\n    struct StreamEndStop {\r\n        std::string operator+() const;\r\n    };\r\n    template<typename T>\r\n    T const& operator + ( T const& value, StreamEndStop ) {\r\n        return value;\r\n    }\r\n}\r\n\r\n#define CATCH_INTERNAL_LINEINFO \\\r\n    ::Catch::SourceLineInfo( __FILE__, static_cast<std::size_t>( __LINE__ ) )\r\n\r\n// end catch_common.h\r\nnamespace Catch {\r\n\r\n    struct RegistrarForTagAliases {\r\n        RegistrarForTagAliases( char const* alias, char const* tag, SourceLineInfo const& lineInfo );\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n#define CATCH_REGISTER_TAG_ALIAS( alias, spec ) \\\r\n    CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n    namespace{ Catch::RegistrarForTagAliases INTERNAL_CATCH_UNIQUE_NAME( AutoRegisterTagAlias )( alias, spec, CATCH_INTERNAL_LINEINFO ); } \\\r\n    CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS\r\n\r\n// end catch_tag_alias_autoregistrar.h\r\n// start catch_test_registry.h\r\n\r\n// start catch_interfaces_testcase.h\r\n\r\n#include <vector>\r\n\r\nnamespace Catch {\r\n\r\n    class TestSpec;\r\n\r\n    struct ITestInvoker {\r\n        virtual void invoke () const = 0;\r\n        virtual ~ITestInvoker();\r\n    };\r\n\r\n    class TestCase;\r\n    struct IConfig;\r\n\r\n    struct ITestCaseRegistry {\r\n        virtual ~ITestCaseRegistry();\r\n        virtual std::vector<TestCase> const& getAllTests() const = 0;\r\n        virtual std::vector<TestCase> const& getAllTestsSorted( IConfig const& config ) const = 0;\r\n    };\r\n\r\n    bool matchTest( TestCase const& testCase, TestSpec const& testSpec, IConfig const& config );\r\n    std::vector<TestCase> filterTests( std::vector<TestCase> const& testCases, TestSpec const& testSpec, IConfig const& config );\r\n    std::vector<TestCase> const& getAllTestCasesSorted( IConfig const& config );\r\n\r\n}\r\n\r\n// end catch_interfaces_testcase.h\r\n// start catch_stringref.h\r\n\r\n#include <cstddef>\r\n#include <string>\r\n#include <iosfwd>\r\n\r\nnamespace Catch {\r\n\r\n    /// A non-owning string class (similar to the forthcoming std::string_view)\r\n    /// Note that, because a StringRef may be a substring of another string,\r\n    /// it may not be null terminated. c_str() must return a null terminated\r\n    /// string, however, and so the StringRef will internally take ownership\r\n    /// (taking a copy), if necessary. In theory this ownership is not externally\r\n    /// visible - but it does mean (substring) StringRefs should not be shared between\r\n    /// threads.\r\n    class StringRef {\r\n    public:\r\n        using size_type = std::size_t;\r\n\r\n    private:\r\n        friend struct StringRefTestAccess;\r\n\r\n        char const* m_start;\r\n        size_type m_size;\r\n\r\n        char* m_data = nullptr;\r\n\r\n        void takeOwnership();\r\n\r\n        static constexpr char const* const s_empty = \"\";\r\n\r\n    public: // construction/ assignment\r\n        StringRef() noexcept\r\n        :   StringRef( s_empty, 0 )\r\n        {}\r\n\r\n        StringRef( StringRef const& other ) noexcept\r\n        :   m_start( other.m_start ),\r\n            m_size( other.m_size )\r\n        {}\r\n\r\n        StringRef( StringRef&& other ) noexcept\r\n        :   m_start( other.m_start ),\r\n            m_size( other.m_size ),\r\n            m_data( other.m_data )\r\n        {\r\n            other.m_data = nullptr;\r\n        }\r\n\r\n        StringRef( char const* rawChars ) noexcept;\r\n\r\n        StringRef( char const* rawChars, size_type size ) noexcept\r\n        :   m_start( rawChars ),\r\n            m_size( size )\r\n        {}\r\n\r\n        StringRef( std::string const& stdString ) noexcept\r\n        :   m_start( stdString.c_str() ),\r\n            m_size( stdString.size() )\r\n        {}\r\n\r\n        ~StringRef() noexcept {\r\n            delete[] m_data;\r\n        }\r\n\r\n        auto operator = ( StringRef const &other ) noexcept -> StringRef& {\r\n            delete[] m_data;\r\n            m_data = nullptr;\r\n            m_start = other.m_start;\r\n            m_size = other.m_size;\r\n            return *this;\r\n        }\r\n\r\n        operator std::string() const;\r\n\r\n        void swap( StringRef& other ) noexcept;\r\n\r\n    public: // operators\r\n        auto operator == ( StringRef const& other ) const noexcept -> bool;\r\n        auto operator != ( StringRef const& other ) const noexcept -> bool;\r\n\r\n        auto operator[] ( size_type index ) const noexcept -> char;\r\n\r\n    public: // named queries\r\n        auto empty() const noexcept -> bool {\r\n            return m_size == 0;\r\n        }\r\n        auto size() const noexcept -> size_type {\r\n            return m_size;\r\n        }\r\n\r\n        auto numberOfCharacters() const noexcept -> size_type;\r\n        auto c_str() const -> char const*;\r\n\r\n    public: // substrings and searches\r\n        auto substr( size_type start, size_type size ) const noexcept -> StringRef;\r\n\r\n        // Returns the current start pointer.\r\n        // Note that the pointer can change when if the StringRef is a substring\r\n        auto currentData() const noexcept -> char const*;\r\n\r\n    private: // ownership queries - may not be consistent between calls\r\n        auto isOwned() const noexcept -> bool;\r\n        auto isSubstring() const noexcept -> bool;\r\n    };\r\n\r\n    auto operator + ( StringRef const& lhs, StringRef const& rhs ) -> std::string;\r\n    auto operator + ( StringRef const& lhs, char const* rhs ) -> std::string;\r\n    auto operator + ( char const* lhs, StringRef const& rhs ) -> std::string;\r\n\r\n    auto operator += ( std::string& lhs, StringRef const& sr ) -> std::string&;\r\n    auto operator << ( std::ostream& os, StringRef const& sr ) -> std::ostream&;\r\n\r\n    inline auto operator \"\" _sr( char const* rawChars, std::size_t size ) noexcept -> StringRef {\r\n        return StringRef( rawChars, size );\r\n    }\r\n\r\n} // namespace Catch\r\n\r\ninline auto operator \"\" _catch_sr( char const* rawChars, std::size_t size ) noexcept -> Catch::StringRef {\r\n    return Catch::StringRef( rawChars, size );\r\n}\r\n\r\n// end catch_stringref.h\r\n// start catch_type_traits.hpp\r\n\r\n\r\n#include <type_traits>\r\n\r\nnamespace Catch{\r\n\r\n#ifdef CATCH_CPP17_OR_GREATER\r\n\ttemplate <typename...>\r\n\tinline constexpr auto is_unique = std::true_type{};\r\n\r\n\ttemplate <typename T, typename... Rest>\r\n\tinline constexpr auto is_unique<T, Rest...> = std::bool_constant<\r\n\t\t(!std::is_same_v<T, Rest> && ...) && is_unique<Rest...>\r\n\t>{};\r\n#else\r\n\r\ntemplate <typename...>\r\nstruct is_unique : std::true_type{};\r\n\r\ntemplate <typename T0, typename T1, typename... Rest>\r\nstruct is_unique<T0, T1, Rest...> : std::integral_constant\r\n<bool,\r\n     !std::is_same<T0, T1>::value\r\n     && is_unique<T0, Rest...>::value\r\n     && is_unique<T1, Rest...>::value\r\n>{};\r\n\r\n#endif\r\n}\r\n\r\n// end catch_type_traits.hpp\r\n// start catch_preprocessor.hpp\r\n\r\n\r\n#define CATCH_RECURSION_LEVEL0(...) __VA_ARGS__\r\n#define CATCH_RECURSION_LEVEL1(...) CATCH_RECURSION_LEVEL0(CATCH_RECURSION_LEVEL0(CATCH_RECURSION_LEVEL0(__VA_ARGS__)))\r\n#define CATCH_RECURSION_LEVEL2(...) CATCH_RECURSION_LEVEL1(CATCH_RECURSION_LEVEL1(CATCH_RECURSION_LEVEL1(__VA_ARGS__)))\r\n#define CATCH_RECURSION_LEVEL3(...) CATCH_RECURSION_LEVEL2(CATCH_RECURSION_LEVEL2(CATCH_RECURSION_LEVEL2(__VA_ARGS__)))\r\n#define CATCH_RECURSION_LEVEL4(...) CATCH_RECURSION_LEVEL3(CATCH_RECURSION_LEVEL3(CATCH_RECURSION_LEVEL3(__VA_ARGS__)))\r\n#define CATCH_RECURSION_LEVEL5(...) CATCH_RECURSION_LEVEL4(CATCH_RECURSION_LEVEL4(CATCH_RECURSION_LEVEL4(__VA_ARGS__)))\r\n\r\n#ifdef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n#define INTERNAL_CATCH_EXPAND_VARGS(...) __VA_ARGS__\r\n// MSVC needs more evaluations\r\n#define CATCH_RECURSION_LEVEL6(...) CATCH_RECURSION_LEVEL5(CATCH_RECURSION_LEVEL5(CATCH_RECURSION_LEVEL5(__VA_ARGS__)))\r\n#define CATCH_RECURSE(...)  CATCH_RECURSION_LEVEL6(CATCH_RECURSION_LEVEL6(__VA_ARGS__))\r\n#else\r\n#define CATCH_RECURSE(...)  CATCH_RECURSION_LEVEL5(__VA_ARGS__)\r\n#endif\r\n\r\n#define CATCH_REC_END(...)\r\n#define CATCH_REC_OUT\r\n\r\n#define CATCH_EMPTY()\r\n#define CATCH_DEFER(id) id CATCH_EMPTY()\r\n\r\n#define CATCH_REC_GET_END2() 0, CATCH_REC_END\r\n#define CATCH_REC_GET_END1(...) CATCH_REC_GET_END2\r\n#define CATCH_REC_GET_END(...) CATCH_REC_GET_END1\r\n#define CATCH_REC_NEXT0(test, next, ...) next CATCH_REC_OUT\r\n#define CATCH_REC_NEXT1(test, next) CATCH_DEFER ( CATCH_REC_NEXT0 ) ( test, next, 0)\r\n#define CATCH_REC_NEXT(test, next)  CATCH_REC_NEXT1(CATCH_REC_GET_END test, next)\r\n\r\n#define CATCH_REC_LIST0(f, x, peek, ...) , f(x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST1) ) ( f, peek, __VA_ARGS__ )\r\n#define CATCH_REC_LIST1(f, x, peek, ...) , f(x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST0) ) ( f, peek, __VA_ARGS__ )\r\n#define CATCH_REC_LIST2(f, x, peek, ...)   f(x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST1) ) ( f, peek, __VA_ARGS__ )\r\n\r\n#define CATCH_REC_LIST0_UD(f, userdata, x, peek, ...) , f(userdata, x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST1_UD) ) ( f, userdata, peek, __VA_ARGS__ )\r\n#define CATCH_REC_LIST1_UD(f, userdata, x, peek, ...) , f(userdata, x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST0_UD) ) ( f, userdata, peek, __VA_ARGS__ )\r\n#define CATCH_REC_LIST2_UD(f, userdata, x, peek, ...)   f(userdata, x) CATCH_DEFER ( CATCH_REC_NEXT(peek, CATCH_REC_LIST1_UD) ) ( f, userdata, peek, __VA_ARGS__ )\r\n\r\n// Applies the function macro `f` to each of the remaining parameters, inserts commas between the results,\r\n// and passes userdata as the first parameter to each invocation,\r\n// e.g. CATCH_REC_LIST_UD(f, x, a, b, c) evaluates to f(x, a), f(x, b), f(x, c)\r\n#define CATCH_REC_LIST_UD(f, userdata, ...) CATCH_RECURSE(CATCH_REC_LIST2_UD(f, userdata, __VA_ARGS__, ()()(), ()()(), ()()(), 0))\r\n\r\n#define CATCH_REC_LIST(f, ...) CATCH_RECURSE(CATCH_REC_LIST2(f, __VA_ARGS__, ()()(), ()()(), ()()(), 0))\r\n\r\n#define INTERNAL_CATCH_EXPAND1(param) INTERNAL_CATCH_EXPAND2(param)\r\n#define INTERNAL_CATCH_EXPAND2(...) INTERNAL_CATCH_NO## __VA_ARGS__\r\n#define INTERNAL_CATCH_DEF(...) INTERNAL_CATCH_DEF __VA_ARGS__\r\n#define INTERNAL_CATCH_NOINTERNAL_CATCH_DEF\r\n#define INTERNAL_CATCH_STRINGIZE(...) INTERNAL_CATCH_STRINGIZE2(__VA_ARGS__)\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n#define INTERNAL_CATCH_STRINGIZE2(...) #__VA_ARGS__\r\n#define INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS(param) INTERNAL_CATCH_STRINGIZE(INTERNAL_CATCH_REMOVE_PARENS(param))\r\n#else\r\n// MSVC is adding extra space and needs another indirection to expand INTERNAL_CATCH_NOINTERNAL_CATCH_DEF\r\n#define INTERNAL_CATCH_STRINGIZE2(...) INTERNAL_CATCH_STRINGIZE3(__VA_ARGS__)\r\n#define INTERNAL_CATCH_STRINGIZE3(...) #__VA_ARGS__\r\n#define INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS(param) (INTERNAL_CATCH_STRINGIZE(INTERNAL_CATCH_REMOVE_PARENS(param)) + 1)\r\n#endif\r\n\r\n#define INTERNAL_CATCH_REMOVE_PARENS(...) INTERNAL_CATCH_EXPAND1(INTERNAL_CATCH_DEF __VA_ARGS__)\r\n\r\n#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME2(Name, ...) INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME3(Name, __VA_ARGS__)\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME3(Name,...) Name \" - \" #__VA_ARGS__\r\n#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME(Name,...) INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME2(Name, INTERNAL_CATCH_REMOVE_PARENS(__VA_ARGS__))\r\n#else\r\n// MSVC is adding extra space and needs more calls to properly remove ()\r\n#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME3(Name,...) Name \" -\" #__VA_ARGS__\r\n#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME1(Name, ...) INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME2(Name, __VA_ARGS__)\r\n#define INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME(Name, ...) INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME1(Name, INTERNAL_CATCH_EXPAND_VARGS(INTERNAL_CATCH_REMOVE_PARENS(__VA_ARGS__)))\r\n#endif\r\n\r\n#define INTERNAL_CATCH_MAKE_TYPE_LIST(types) Catch::TypeList<INTERNAL_CATCH_REMOVE_PARENS(types)>\r\n\r\n#define INTERNAL_CATCH_MAKE_TYPE_LISTS_FROM_TYPES(types)\\\r\n    CATCH_REC_LIST(INTERNAL_CATCH_MAKE_TYPE_LIST,INTERNAL_CATCH_REMOVE_PARENS(types))\r\n\r\n// end catch_preprocessor.hpp\r\n// start catch_meta.hpp\r\n\r\n\r\n#include <type_traits>\r\n\r\nnamespace Catch {\r\ntemplate< typename... >\r\nstruct TypeList {};\r\n\r\ntemplate< typename... >\r\nstruct append;\r\n\r\ntemplate< template<typename...> class L1\r\n    , typename...E1\r\n    , template<typename...> class L2\r\n    , typename...E2\r\n>\r\nstruct append< L1<E1...>, L2<E2...> > {\r\n    using type = L1<E1..., E2...>;\r\n};\r\n\r\ntemplate< template<typename...> class L1\r\n    , typename...E1\r\n    , template<typename...> class L2\r\n    , typename...E2\r\n    , typename...Rest\r\n>\r\nstruct append< L1<E1...>, L2<E2...>, Rest...> {\r\n    using type = typename append< L1<E1..., E2...>, Rest... >::type;\r\n};\r\n\r\ntemplate< template<typename...> class\r\n    , typename...\r\n>\r\nstruct rewrap;\r\n\r\ntemplate< template<typename...> class Container\r\n    , template<typename...> class List\r\n    , typename...elems\r\n>\r\nstruct rewrap<Container, List<elems...>> {\r\n    using type = TypeList< Container< elems... > >;\r\n};\r\n\r\ntemplate< template<typename...> class Container\r\n    , template<typename...> class List\r\n    , class...Elems\r\n    , typename...Elements>\r\n    struct rewrap<Container, List<Elems...>, Elements...> {\r\n    using type = typename append<TypeList<Container<Elems...>>, typename rewrap<Container, Elements...>::type>::type;\r\n};\r\n\r\ntemplate< template<typename...> class...Containers >\r\nstruct combine {\r\n    template< typename...Types >\r\n    struct with_types {\r\n        template< template <typename...> class Final >\r\n        struct into {\r\n            using type = typename append<Final<>, typename rewrap<Containers, Types...>::type...>::type;\r\n        };\r\n    };\r\n};\r\n\r\ntemplate<typename T>\r\nstruct always_false : std::false_type {};\r\n\r\n} // namespace Catch\r\n\r\n// end catch_meta.hpp\r\nnamespace Catch {\r\n\r\ntemplate<typename C>\r\nclass TestInvokerAsMethod : public ITestInvoker {\r\n    void (C::*m_testAsMethod)();\r\npublic:\r\n    TestInvokerAsMethod( void (C::*testAsMethod)() ) noexcept : m_testAsMethod( testAsMethod ) {}\r\n\r\n    void invoke() const override {\r\n        C obj;\r\n        (obj.*m_testAsMethod)();\r\n    }\r\n};\r\n\r\nauto makeTestInvoker( void(*testAsFunction)() ) noexcept -> ITestInvoker*;\r\n\r\ntemplate<typename C>\r\nauto makeTestInvoker( void (C::*testAsMethod)() ) noexcept -> ITestInvoker* {\r\n    return new(std::nothrow) TestInvokerAsMethod<C>( testAsMethod );\r\n}\r\n\r\nstruct NameAndTags {\r\n    NameAndTags( StringRef const& name_ = StringRef(), StringRef const& tags_ = StringRef() ) noexcept;\r\n    StringRef name;\r\n    StringRef tags;\r\n};\r\n\r\nstruct AutoReg : NonCopyable {\r\n    AutoReg( ITestInvoker* invoker, SourceLineInfo const& lineInfo, StringRef const& classOrMethod, NameAndTags const& nameAndTags ) noexcept;\r\n    ~AutoReg();\r\n};\r\n\r\n} // end namespace Catch\r\n\r\n#if defined(CATCH_CONFIG_DISABLE)\r\n    #define INTERNAL_CATCH_TESTCASE_NO_REGISTRATION( TestName, ... ) \\\r\n        static void TestName()\r\n    #define INTERNAL_CATCH_TESTCASE_METHOD_NO_REGISTRATION( TestName, ClassName, ... ) \\\r\n        namespace{                        \\\r\n            struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName) { \\\r\n                void test();              \\\r\n            };                            \\\r\n        }                                 \\\r\n        void TestName::test()\r\n    #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION( TestName, ... )  \\\r\n        template<typename TestType>                                             \\\r\n        static void TestName()\r\n    #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION( TestName, ClassName, ... )    \\\r\n        namespace{                                                                                  \\\r\n            template<typename TestType>                                                             \\\r\n            struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName <TestType>) {     \\\r\n                void test();                                                                        \\\r\n            };                                                                                      \\\r\n        }                                                                                           \\\r\n        template<typename TestType>                                                                 \\\r\n        void TestName::test()\r\n#endif\r\n\r\n    ///////////////////////////////////////////////////////////////////////////////\r\n    #define INTERNAL_CATCH_TESTCASE2( TestName, ... ) \\\r\n        static void TestName(); \\\r\n        CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n        namespace{ Catch::AutoReg INTERNAL_CATCH_UNIQUE_NAME( autoRegistrar )( Catch::makeTestInvoker( &TestName ), CATCH_INTERNAL_LINEINFO, Catch::StringRef(), Catch::NameAndTags{ __VA_ARGS__ } ); } /* NOLINT */ \\\r\n        CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \\\r\n        static void TestName()\r\n    #define INTERNAL_CATCH_TESTCASE( ... ) \\\r\n        INTERNAL_CATCH_TESTCASE2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ), __VA_ARGS__ )\r\n\r\n    ///////////////////////////////////////////////////////////////////////////////\r\n    #define INTERNAL_CATCH_METHOD_AS_TEST_CASE( QualifiedMethod, ... ) \\\r\n        CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n        namespace{ Catch::AutoReg INTERNAL_CATCH_UNIQUE_NAME( autoRegistrar )( Catch::makeTestInvoker( &QualifiedMethod ), CATCH_INTERNAL_LINEINFO, \"&\" #QualifiedMethod, Catch::NameAndTags{ __VA_ARGS__ } ); } /* NOLINT */ \\\r\n        CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS\r\n\r\n    ///////////////////////////////////////////////////////////////////////////////\r\n    #define INTERNAL_CATCH_TEST_CASE_METHOD2( TestName, ClassName, ... )\\\r\n        CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n        namespace{ \\\r\n            struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName) { \\\r\n                void test(); \\\r\n            }; \\\r\n            Catch::AutoReg INTERNAL_CATCH_UNIQUE_NAME( autoRegistrar ) ( Catch::makeTestInvoker( &TestName::test ), CATCH_INTERNAL_LINEINFO, #ClassName, Catch::NameAndTags{ __VA_ARGS__ } ); /* NOLINT */ \\\r\n        } \\\r\n        CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \\\r\n        void TestName::test()\r\n    #define INTERNAL_CATCH_TEST_CASE_METHOD( ClassName, ... ) \\\r\n        INTERNAL_CATCH_TEST_CASE_METHOD2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ), ClassName, __VA_ARGS__ )\r\n\r\n    ///////////////////////////////////////////////////////////////////////////////\r\n    #define INTERNAL_CATCH_REGISTER_TESTCASE( Function, ... ) \\\r\n        CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n        Catch::AutoReg INTERNAL_CATCH_UNIQUE_NAME( autoRegistrar )( Catch::makeTestInvoker( Function ), CATCH_INTERNAL_LINEINFO, Catch::StringRef(), Catch::NameAndTags{ __VA_ARGS__ } ); /* NOLINT */ \\\r\n        CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS\r\n\r\n    ///////////////////////////////////////////////////////////////////////////////\r\n    #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_2(TestName, TestFunc, Name, Tags, ... )\\\r\n        CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n        template<typename TestType> \\\r\n        static void TestFunc();\\\r\n        namespace {\\\r\n            template<typename...Types> \\\r\n            struct TestName{\\\r\n                template<typename...Ts> \\\r\n                TestName(Ts...names){\\\r\n                    CATCH_INTERNAL_CHECK_UNIQUE_TYPES(CATCH_REC_LIST(INTERNAL_CATCH_REMOVE_PARENS, __VA_ARGS__)) \\\r\n                    using expander = int[];\\\r\n                    (void)expander{(Catch::AutoReg( Catch::makeTestInvoker( &TestFunc<Types> ), CATCH_INTERNAL_LINEINFO, Catch::StringRef(), Catch::NameAndTags{ names, Tags } ), 0)... };/* NOLINT */ \\\r\n                }\\\r\n            };\\\r\n            INTERNAL_CATCH_TEMPLATE_REGISTRY_INITIATE(TestName, Name, __VA_ARGS__) \\\r\n        }\\\r\n        CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \\\r\n        template<typename TestType> \\\r\n        static void TestFunc()\r\n\r\n#if defined(CATCH_CPP17_OR_GREATER)\r\n#define CATCH_INTERNAL_CHECK_UNIQUE_TYPES(...) static_assert(Catch::is_unique<__VA_ARGS__>,\"Duplicate type detected in declaration of template test case\");\r\n#else\r\n#define CATCH_INTERNAL_CHECK_UNIQUE_TYPES(...) static_assert(Catch::is_unique<__VA_ARGS__>::value,\"Duplicate type detected in declaration of template test case\");\r\n#endif\r\n\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n    #define INTERNAL_CATCH_TEMPLATE_TEST_CASE(Name, Tags, ...) \\\r\n        INTERNAL_CATCH_TEMPLATE_TEST_CASE_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), Name, Tags, __VA_ARGS__ )\r\n#else\r\n    #define INTERNAL_CATCH_TEMPLATE_TEST_CASE(Name, Tags, ...) \\\r\n        INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), Name, Tags, __VA_ARGS__ ) )\r\n#endif\r\n\r\n    #define INTERNAL_CATCH_TEMPLATE_REGISTRY_INITIATE(TestName, Name, ...)\\\r\n        static int INTERNAL_CATCH_UNIQUE_NAME( globalRegistrar ) = [](){\\\r\n            TestName<CATCH_REC_LIST(INTERNAL_CATCH_REMOVE_PARENS, __VA_ARGS__)>(CATCH_REC_LIST_UD(INTERNAL_CATCH_TEMPLATE_UNIQUE_NAME,Name, __VA_ARGS__));\\\r\n            return 0;\\\r\n        }();\r\n\r\n    #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE2(TestName, TestFuncName, Name, Tags, TmplTypes, TypesList) \\\r\n        CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS                      \\\r\n        template<typename TestType> static void TestFuncName();       \\\r\n        namespace {                                                   \\\r\n            template<typename... Types>                               \\\r\n            struct TestName {                                         \\\r\n                TestName() {                                          \\\r\n                    CATCH_INTERNAL_CHECK_UNIQUE_TYPES(Types...)       \\\r\n                    int index = 0;                                    \\\r\n                    using expander = int[];                           \\\r\n                    constexpr char const* tmpl_types[] = {CATCH_REC_LIST(INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS, INTERNAL_CATCH_REMOVE_PARENS(TmplTypes))};\\\r\n                    constexpr char const* types_list[] = {CATCH_REC_LIST(INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS, INTERNAL_CATCH_REMOVE_PARENS(TypesList))};\\\r\n                    constexpr auto num_types = sizeof(types_list) / sizeof(types_list[0]);\\\r\n                    (void)expander{(Catch::AutoReg( Catch::makeTestInvoker( &TestFuncName<Types> ), CATCH_INTERNAL_LINEINFO, Catch::StringRef(), Catch::NameAndTags{ Name \" - \" + std::string(tmpl_types[index / num_types]) + \"<\" + std::string(types_list[index % num_types]) + \">\", Tags } ), index++, 0)... };/* NOLINT */\\\r\n                }                                                     \\\r\n            };                                                        \\\r\n            static int INTERNAL_CATCH_UNIQUE_NAME( globalRegistrar ) = [](){ \\\r\n                using TestInit = Catch::combine<INTERNAL_CATCH_REMOVE_PARENS(TmplTypes)> \\\r\n                            ::with_types<INTERNAL_CATCH_MAKE_TYPE_LISTS_FROM_TYPES(TypesList)>::into<TestName>::type; \\\r\n                TestInit();                                           \\\r\n                return 0;                                             \\\r\n            }();                                                      \\\r\n        }                                                             \\\r\n        CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS                    \\\r\n        template<typename TestType>                                   \\\r\n        static void TestFuncName()\r\n\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n    #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE(Name, Tags, ...)\\\r\n        INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE2(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ),Name,Tags,__VA_ARGS__)\r\n#else\r\n    #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE(Name, Tags, ...)\\\r\n        INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), Name, Tags, __VA_ARGS__ ) )\r\n#endif\r\n\r\n    #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_2( TestNameClass, TestName, ClassName, Name, Tags, ... ) \\\r\n        CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n        namespace{ \\\r\n            template<typename TestType> \\\r\n            struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName <TestType>) { \\\r\n                void test();\\\r\n            };\\\r\n            template<typename...Types> \\\r\n            struct TestNameClass{\\\r\n                template<typename...Ts> \\\r\n                TestNameClass(Ts...names){\\\r\n                    CATCH_INTERNAL_CHECK_UNIQUE_TYPES(CATCH_REC_LIST(INTERNAL_CATCH_REMOVE_PARENS, __VA_ARGS__)) \\\r\n                    using expander = int[];\\\r\n                    (void)expander{(Catch::AutoReg( Catch::makeTestInvoker( &TestName<Types>::test ), CATCH_INTERNAL_LINEINFO, #ClassName, Catch::NameAndTags{ names, Tags } ), 0)... };/* NOLINT */ \\\r\n                }\\\r\n            };\\\r\n            INTERNAL_CATCH_TEMPLATE_REGISTRY_INITIATE(TestNameClass, Name, __VA_ARGS__)\\\r\n        }\\\r\n        CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS\\\r\n        template<typename TestType> \\\r\n        void TestName<TestType>::test()\r\n\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n    #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( ClassName, Name, Tags,... ) \\\r\n        INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____C_L_A_S_S____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) , ClassName, Name, Tags, __VA_ARGS__ )\r\n#else\r\n    #define INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( ClassName, Name, Tags,... ) \\\r\n        INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____C_L_A_S_S____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) , ClassName, Name, Tags, __VA_ARGS__ ) )\r\n#endif\r\n\r\n    #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD_2(TestNameClass, TestName, ClassName, Name, Tags, TmplTypes, TypesList)\\\r\n        CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n        template<typename TestType> \\\r\n            struct TestName : INTERNAL_CATCH_REMOVE_PARENS(ClassName <TestType>) { \\\r\n                void test();\\\r\n            };\\\r\n        namespace {\\\r\n            template<typename...Types>\\\r\n            struct TestNameClass{\\\r\n                TestNameClass(){\\\r\n                    CATCH_INTERNAL_CHECK_UNIQUE_TYPES(Types...)\\\r\n                    int index = 0;\\\r\n                    using expander = int[];\\\r\n                    constexpr char const* tmpl_types[] = {CATCH_REC_LIST(INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS, INTERNAL_CATCH_REMOVE_PARENS(TmplTypes))};\\\r\n                    constexpr char const* types_list[] = {CATCH_REC_LIST(INTERNAL_CATCH_STRINGIZE_WITHOUT_PARENS, INTERNAL_CATCH_REMOVE_PARENS(TypesList))};\\\r\n                    constexpr auto num_types = sizeof(types_list) / sizeof(types_list[0]);\\\r\n                    (void)expander{(Catch::AutoReg( Catch::makeTestInvoker( &TestName<Types>::test ), CATCH_INTERNAL_LINEINFO, #ClassName, Catch::NameAndTags{ Name \" - \" + std::string(tmpl_types[index / num_types]) + \"<\" + std::string(types_list[index % num_types]) + \">\", Tags } ), index++, 0)... };/* NOLINT */ \\\r\n                }\\\r\n            };\\\r\n            static int INTERNAL_CATCH_UNIQUE_NAME( globalRegistrar ) = [](){\\\r\n                using TestInit = Catch::combine<INTERNAL_CATCH_REMOVE_PARENS(TmplTypes)>\\\r\n                            ::with_types<INTERNAL_CATCH_MAKE_TYPE_LISTS_FROM_TYPES(TypesList)>::into<TestNameClass>::type;\\\r\n                TestInit();\\\r\n                return 0;\\\r\n            }(); \\\r\n        }\\\r\n        CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \\\r\n        template<typename TestType> \\\r\n        void TestName<TestType>::test()\r\n\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n    #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( ClassName, Name, Tags, ... )\\\r\n        INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), ClassName, Name, Tags, __VA_ARGS__ )\r\n#else\r\n    #define INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( ClassName, Name, Tags, ... )\\\r\n        INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD_2( INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____F_U_N_C____ ), ClassName, Name, Tags, __VA_ARGS__ ) )\r\n#endif\r\n\r\n// end catch_test_registry.h\r\n// start catch_capture.hpp\r\n\r\n// start catch_assertionhandler.h\r\n\r\n// start catch_assertioninfo.h\r\n\r\n// start catch_result_type.h\r\n\r\nnamespace Catch {\r\n\r\n    // ResultWas::OfType enum\r\n    struct ResultWas { enum OfType {\r\n        Unknown = -1,\r\n        Ok = 0,\r\n        Info = 1,\r\n        Warning = 2,\r\n\r\n        FailureBit = 0x10,\r\n\r\n        ExpressionFailed = FailureBit | 1,\r\n        ExplicitFailure = FailureBit | 2,\r\n\r\n        Exception = 0x100 | FailureBit,\r\n\r\n        ThrewException = Exception | 1,\r\n        DidntThrowException = Exception | 2,\r\n\r\n        FatalErrorCondition = 0x200 | FailureBit\r\n\r\n    }; };\r\n\r\n    bool isOk( ResultWas::OfType resultType );\r\n    bool isJustInfo( int flags );\r\n\r\n    // ResultDisposition::Flags enum\r\n    struct ResultDisposition { enum Flags {\r\n        Normal = 0x01,\r\n\r\n        ContinueOnFailure = 0x02,   // Failures fail test, but execution continues\r\n        FalseTest = 0x04,           // Prefix expression with !\r\n        SuppressFail = 0x08         // Failures are reported but do not fail the test\r\n    }; };\r\n\r\n    ResultDisposition::Flags operator | ( ResultDisposition::Flags lhs, ResultDisposition::Flags rhs );\r\n\r\n    bool shouldContinueOnFailure( int flags );\r\n    inline bool isFalseTest( int flags ) { return ( flags & ResultDisposition::FalseTest ) != 0; }\r\n    bool shouldSuppressFailure( int flags );\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_result_type.h\r\nnamespace Catch {\r\n\r\n    struct AssertionInfo\r\n    {\r\n        StringRef macroName;\r\n        SourceLineInfo lineInfo;\r\n        StringRef capturedExpression;\r\n        ResultDisposition::Flags resultDisposition;\r\n\r\n        // We want to delete this constructor but a compiler bug in 4.8 means\r\n        // the struct is then treated as non-aggregate\r\n        //AssertionInfo() = delete;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_assertioninfo.h\r\n// start catch_decomposer.h\r\n\r\n// start catch_tostring.h\r\n\r\n#include <vector>\r\n#include <cstddef>\r\n#include <type_traits>\r\n#include <string>\r\n// start catch_stream.h\r\n\r\n#include <iosfwd>\r\n#include <cstddef>\r\n#include <ostream>\r\n\r\nnamespace Catch {\r\n\r\n    std::ostream& cout();\r\n    std::ostream& cerr();\r\n    std::ostream& clog();\r\n\r\n    class StringRef;\r\n\r\n    struct IStream {\r\n        virtual ~IStream();\r\n        virtual std::ostream& stream() const = 0;\r\n    };\r\n\r\n    auto makeStream( StringRef const &filename ) -> IStream const*;\r\n\r\n    class ReusableStringStream {\r\n        std::size_t m_index;\r\n        std::ostream* m_oss;\r\n    public:\r\n        ReusableStringStream();\r\n        ~ReusableStringStream();\r\n\r\n        auto str() const -> std::string;\r\n\r\n        template<typename T>\r\n        auto operator << ( T const& value ) -> ReusableStringStream& {\r\n            *m_oss << value;\r\n            return *this;\r\n        }\r\n        auto get() -> std::ostream& { return *m_oss; }\r\n    };\r\n}\r\n\r\n// end catch_stream.h\r\n\r\n#ifdef CATCH_CONFIG_CPP17_STRING_VIEW\r\n#include <string_view>\r\n#endif\r\n\r\n#ifdef __OBJC__\r\n// start catch_objc_arc.hpp\r\n\r\n#import <Foundation/Foundation.h>\r\n\r\n#ifdef __has_feature\r\n#define CATCH_ARC_ENABLED __has_feature(objc_arc)\r\n#else\r\n#define CATCH_ARC_ENABLED 0\r\n#endif\r\n\r\nvoid arcSafeRelease( NSObject* obj );\r\nid performOptionalSelector( id obj, SEL sel );\r\n\r\n#if !CATCH_ARC_ENABLED\r\ninline void arcSafeRelease( NSObject* obj ) {\r\n    [obj release];\r\n}\r\ninline id performOptionalSelector( id obj, SEL sel ) {\r\n    if( [obj respondsToSelector: sel] )\r\n        return [obj performSelector: sel];\r\n    return nil;\r\n}\r\n#define CATCH_UNSAFE_UNRETAINED\r\n#define CATCH_ARC_STRONG\r\n#else\r\ninline void arcSafeRelease( NSObject* ){}\r\ninline id performOptionalSelector( id obj, SEL sel ) {\r\n#ifdef __clang__\r\n#pragma clang diagnostic push\r\n#pragma clang diagnostic ignored \"-Warc-performSelector-leaks\"\r\n#endif\r\n    if( [obj respondsToSelector: sel] )\r\n        return [obj performSelector: sel];\r\n#ifdef __clang__\r\n#pragma clang diagnostic pop\r\n#endif\r\n    return nil;\r\n}\r\n#define CATCH_UNSAFE_UNRETAINED __unsafe_unretained\r\n#define CATCH_ARC_STRONG __strong\r\n#endif\r\n\r\n// end catch_objc_arc.hpp\r\n#endif\r\n\r\n#ifdef _MSC_VER\r\n#pragma warning(push)\r\n#pragma warning(disable:4180) // We attempt to stream a function (address) by const&, which MSVC complains about but is harmless\r\n#endif\r\n\r\nnamespace Catch {\r\n    namespace Detail {\r\n\r\n        extern const std::string unprintableString;\r\n\r\n        std::string rawMemoryToString( const void *object, std::size_t size );\r\n\r\n        template<typename T>\r\n        std::string rawMemoryToString( const T& object ) {\r\n          return rawMemoryToString( &object, sizeof(object) );\r\n        }\r\n\r\n        template<typename T>\r\n        class IsStreamInsertable {\r\n            template<typename SS, typename TT>\r\n            static auto test(int)\r\n                -> decltype(std::declval<SS&>() << std::declval<TT>(), std::true_type());\r\n\r\n            template<typename, typename>\r\n            static auto test(...)->std::false_type;\r\n\r\n        public:\r\n            static const bool value = decltype(test<std::ostream, const T&>(0))::value;\r\n        };\r\n\r\n        template<typename E>\r\n        std::string convertUnknownEnumToString( E e );\r\n\r\n        template<typename T>\r\n        typename std::enable_if<\r\n            !std::is_enum<T>::value && !std::is_base_of<std::exception, T>::value,\r\n        std::string>::type convertUnstreamable( T const& ) {\r\n            return Detail::unprintableString;\r\n        }\r\n        template<typename T>\r\n        typename std::enable_if<\r\n            !std::is_enum<T>::value && std::is_base_of<std::exception, T>::value,\r\n         std::string>::type convertUnstreamable(T const& ex) {\r\n            return ex.what();\r\n        }\r\n\r\n        template<typename T>\r\n        typename std::enable_if<\r\n            std::is_enum<T>::value\r\n        , std::string>::type convertUnstreamable( T const& value ) {\r\n            return convertUnknownEnumToString( value );\r\n        }\r\n\r\n#if defined(_MANAGED)\r\n        //! Convert a CLR string to a utf8 std::string\r\n        template<typename T>\r\n        std::string clrReferenceToString( T^ ref ) {\r\n            if (ref == nullptr)\r\n                return std::string(\"null\");\r\n            auto bytes = System::Text::Encoding::UTF8->GetBytes(ref->ToString());\r\n            cli::pin_ptr<System::Byte> p = &bytes[0];\r\n            return std::string(reinterpret_cast<char const *>(p), bytes->Length);\r\n        }\r\n#endif\r\n\r\n    } // namespace Detail\r\n\r\n    // If we decide for C++14, change these to enable_if_ts\r\n    template <typename T, typename = void>\r\n    struct StringMaker {\r\n        template <typename Fake = T>\r\n        static\r\n        typename std::enable_if<::Catch::Detail::IsStreamInsertable<Fake>::value, std::string>::type\r\n            convert(const Fake& value) {\r\n                ReusableStringStream rss;\r\n                // NB: call using the function-like syntax to avoid ambiguity with\r\n                // user-defined templated operator<< under clang.\r\n                rss.operator<<(value);\r\n                return rss.str();\r\n        }\r\n\r\n        template <typename Fake = T>\r\n        static\r\n        typename std::enable_if<!::Catch::Detail::IsStreamInsertable<Fake>::value, std::string>::type\r\n            convert( const Fake& value ) {\r\n#if !defined(CATCH_CONFIG_FALLBACK_STRINGIFIER)\r\n            return Detail::convertUnstreamable(value);\r\n#else\r\n            return CATCH_CONFIG_FALLBACK_STRINGIFIER(value);\r\n#endif\r\n        }\r\n    };\r\n\r\n    namespace Detail {\r\n\r\n        // This function dispatches all stringification requests inside of Catch.\r\n        // Should be preferably called fully qualified, like ::Catch::Detail::stringify\r\n        template <typename T>\r\n        std::string stringify(const T& e) {\r\n            return ::Catch::StringMaker<typename std::remove_cv<typename std::remove_reference<T>::type>::type>::convert(e);\r\n        }\r\n\r\n        template<typename E>\r\n        std::string convertUnknownEnumToString( E e ) {\r\n            return ::Catch::Detail::stringify(static_cast<typename std::underlying_type<E>::type>(e));\r\n        }\r\n\r\n#if defined(_MANAGED)\r\n        template <typename T>\r\n        std::string stringify( T^ e ) {\r\n            return ::Catch::StringMaker<T^>::convert(e);\r\n        }\r\n#endif\r\n\r\n    } // namespace Detail\r\n\r\n    // Some predefined specializations\r\n\r\n    template<>\r\n    struct StringMaker<std::string> {\r\n        static std::string convert(const std::string& str);\r\n    };\r\n\r\n#ifdef CATCH_CONFIG_CPP17_STRING_VIEW\r\n    template<>\r\n    struct StringMaker<std::string_view> {\r\n        static std::string convert(std::string_view str);\r\n    };\r\n#endif\r\n\r\n    template<>\r\n    struct StringMaker<char const *> {\r\n        static std::string convert(char const * str);\r\n    };\r\n    template<>\r\n    struct StringMaker<char *> {\r\n        static std::string convert(char * str);\r\n    };\r\n\r\n#ifdef CATCH_CONFIG_WCHAR\r\n    template<>\r\n    struct StringMaker<std::wstring> {\r\n        static std::string convert(const std::wstring& wstr);\r\n    };\r\n\r\n# ifdef CATCH_CONFIG_CPP17_STRING_VIEW\r\n    template<>\r\n    struct StringMaker<std::wstring_view> {\r\n        static std::string convert(std::wstring_view str);\r\n    };\r\n# endif\r\n\r\n    template<>\r\n    struct StringMaker<wchar_t const *> {\r\n        static std::string convert(wchar_t const * str);\r\n    };\r\n    template<>\r\n    struct StringMaker<wchar_t *> {\r\n        static std::string convert(wchar_t * str);\r\n    };\r\n#endif\r\n\r\n    // TBD: Should we use `strnlen` to ensure that we don't go out of the buffer,\r\n    //      while keeping string semantics?\r\n    template<int SZ>\r\n    struct StringMaker<char[SZ]> {\r\n        static std::string convert(char const* str) {\r\n            return ::Catch::Detail::stringify(std::string{ str });\r\n        }\r\n    };\r\n    template<int SZ>\r\n    struct StringMaker<signed char[SZ]> {\r\n        static std::string convert(signed char const* str) {\r\n            return ::Catch::Detail::stringify(std::string{ reinterpret_cast<char const *>(str) });\r\n        }\r\n    };\r\n    template<int SZ>\r\n    struct StringMaker<unsigned char[SZ]> {\r\n        static std::string convert(unsigned char const* str) {\r\n            return ::Catch::Detail::stringify(std::string{ reinterpret_cast<char const *>(str) });\r\n        }\r\n    };\r\n\r\n    template<>\r\n    struct StringMaker<int> {\r\n        static std::string convert(int value);\r\n    };\r\n    template<>\r\n    struct StringMaker<long> {\r\n        static std::string convert(long value);\r\n    };\r\n    template<>\r\n    struct StringMaker<long long> {\r\n        static std::string convert(long long value);\r\n    };\r\n    template<>\r\n    struct StringMaker<unsigned int> {\r\n        static std::string convert(unsigned int value);\r\n    };\r\n    template<>\r\n    struct StringMaker<unsigned long> {\r\n        static std::string convert(unsigned long value);\r\n    };\r\n    template<>\r\n    struct StringMaker<unsigned long long> {\r\n        static std::string convert(unsigned long long value);\r\n    };\r\n\r\n    template<>\r\n    struct StringMaker<bool> {\r\n        static std::string convert(bool b);\r\n    };\r\n\r\n    template<>\r\n    struct StringMaker<char> {\r\n        static std::string convert(char c);\r\n    };\r\n    template<>\r\n    struct StringMaker<signed char> {\r\n        static std::string convert(signed char c);\r\n    };\r\n    template<>\r\n    struct StringMaker<unsigned char> {\r\n        static std::string convert(unsigned char c);\r\n    };\r\n\r\n    template<>\r\n    struct StringMaker<std::nullptr_t> {\r\n        static std::string convert(std::nullptr_t);\r\n    };\r\n\r\n    template<>\r\n    struct StringMaker<float> {\r\n        static std::string convert(float value);\r\n    };\r\n    template<>\r\n    struct StringMaker<double> {\r\n        static std::string convert(double value);\r\n    };\r\n\r\n    template <typename T>\r\n    struct StringMaker<T*> {\r\n        template <typename U>\r\n        static std::string convert(U* p) {\r\n            if (p) {\r\n                return ::Catch::Detail::rawMemoryToString(p);\r\n            } else {\r\n                return \"nullptr\";\r\n            }\r\n        }\r\n    };\r\n\r\n    template <typename R, typename C>\r\n    struct StringMaker<R C::*> {\r\n        static std::string convert(R C::* p) {\r\n            if (p) {\r\n                return ::Catch::Detail::rawMemoryToString(p);\r\n            } else {\r\n                return \"nullptr\";\r\n            }\r\n        }\r\n    };\r\n\r\n#if defined(_MANAGED)\r\n    template <typename T>\r\n    struct StringMaker<T^> {\r\n        static std::string convert( T^ ref ) {\r\n            return ::Catch::Detail::clrReferenceToString(ref);\r\n        }\r\n    };\r\n#endif\r\n\r\n    namespace Detail {\r\n        template<typename InputIterator>\r\n        std::string rangeToString(InputIterator first, InputIterator last) {\r\n            ReusableStringStream rss;\r\n            rss << \"{ \";\r\n            if (first != last) {\r\n                rss << ::Catch::Detail::stringify(*first);\r\n                for (++first; first != last; ++first)\r\n                    rss << \", \" << ::Catch::Detail::stringify(*first);\r\n            }\r\n            rss << \" }\";\r\n            return rss.str();\r\n        }\r\n    }\r\n\r\n#ifdef __OBJC__\r\n    template<>\r\n    struct StringMaker<NSString*> {\r\n        static std::string convert(NSString * nsstring) {\r\n            if (!nsstring)\r\n                return \"nil\";\r\n            return std::string(\"@\") + [nsstring UTF8String];\r\n        }\r\n    };\r\n    template<>\r\n    struct StringMaker<NSObject*> {\r\n        static std::string convert(NSObject* nsObject) {\r\n            return ::Catch::Detail::stringify([nsObject description]);\r\n        }\r\n\r\n    };\r\n    namespace Detail {\r\n        inline std::string stringify( NSString* nsstring ) {\r\n            return StringMaker<NSString*>::convert( nsstring );\r\n        }\r\n\r\n    } // namespace Detail\r\n#endif // __OBJC__\r\n\r\n} // namespace Catch\r\n\r\n//////////////////////////////////////////////////////\r\n// Separate std-lib types stringification, so it can be selectively enabled\r\n// This means that we do not bring in\r\n\r\n#if defined(CATCH_CONFIG_ENABLE_ALL_STRINGMAKERS)\r\n#  define CATCH_CONFIG_ENABLE_PAIR_STRINGMAKER\r\n#  define CATCH_CONFIG_ENABLE_TUPLE_STRINGMAKER\r\n#  define CATCH_CONFIG_ENABLE_VARIANT_STRINGMAKER\r\n#  define CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER\r\n#  define CATCH_CONFIG_ENABLE_OPTIONAL_STRINGMAKER\r\n#endif\r\n\r\n// Separate std::pair specialization\r\n#if defined(CATCH_CONFIG_ENABLE_PAIR_STRINGMAKER)\r\n#include <utility>\r\nnamespace Catch {\r\n    template<typename T1, typename T2>\r\n    struct StringMaker<std::pair<T1, T2> > {\r\n        static std::string convert(const std::pair<T1, T2>& pair) {\r\n            ReusableStringStream rss;\r\n            rss << \"{ \"\r\n                << ::Catch::Detail::stringify(pair.first)\r\n                << \", \"\r\n                << ::Catch::Detail::stringify(pair.second)\r\n                << \" }\";\r\n            return rss.str();\r\n        }\r\n    };\r\n}\r\n#endif // CATCH_CONFIG_ENABLE_PAIR_STRINGMAKER\r\n\r\n#if defined(CATCH_CONFIG_ENABLE_OPTIONAL_STRINGMAKER) && defined(CATCH_CONFIG_CPP17_OPTIONAL)\r\n#include <optional>\r\nnamespace Catch {\r\n    template<typename T>\r\n    struct StringMaker<std::optional<T> > {\r\n        static std::string convert(const std::optional<T>& optional) {\r\n            ReusableStringStream rss;\r\n            if (optional.has_value()) {\r\n                rss << ::Catch::Detail::stringify(*optional);\r\n            } else {\r\n                rss << \"{ }\";\r\n            }\r\n            return rss.str();\r\n        }\r\n    };\r\n}\r\n#endif // CATCH_CONFIG_ENABLE_OPTIONAL_STRINGMAKER\r\n\r\n// Separate std::tuple specialization\r\n#if defined(CATCH_CONFIG_ENABLE_TUPLE_STRINGMAKER)\r\n#include <tuple>\r\nnamespace Catch {\r\n    namespace Detail {\r\n        template<\r\n            typename Tuple,\r\n            std::size_t N = 0,\r\n            bool = (N < std::tuple_size<Tuple>::value)\r\n            >\r\n            struct TupleElementPrinter {\r\n            static void print(const Tuple& tuple, std::ostream& os) {\r\n                os << (N ? \", \" : \" \")\r\n                    << ::Catch::Detail::stringify(std::get<N>(tuple));\r\n                TupleElementPrinter<Tuple, N + 1>::print(tuple, os);\r\n            }\r\n        };\r\n\r\n        template<\r\n            typename Tuple,\r\n            std::size_t N\r\n        >\r\n            struct TupleElementPrinter<Tuple, N, false> {\r\n            static void print(const Tuple&, std::ostream&) {}\r\n        };\r\n\r\n    }\r\n\r\n    template<typename ...Types>\r\n    struct StringMaker<std::tuple<Types...>> {\r\n        static std::string convert(const std::tuple<Types...>& tuple) {\r\n            ReusableStringStream rss;\r\n            rss << '{';\r\n            Detail::TupleElementPrinter<std::tuple<Types...>>::print(tuple, rss.get());\r\n            rss << \" }\";\r\n            return rss.str();\r\n        }\r\n    };\r\n}\r\n#endif // CATCH_CONFIG_ENABLE_TUPLE_STRINGMAKER\r\n\r\n#if defined(CATCH_CONFIG_ENABLE_VARIANT_STRINGMAKER) && defined(CATCH_CONFIG_CPP17_VARIANT)\r\n#include <variant>\r\nnamespace Catch {\r\n    template<>\r\n    struct StringMaker<std::monostate> {\r\n        static std::string convert(const std::monostate&) {\r\n            return \"{ }\";\r\n        }\r\n    };\r\n\r\n    template<typename... Elements>\r\n    struct StringMaker<std::variant<Elements...>> {\r\n        static std::string convert(const std::variant<Elements...>& variant) {\r\n            if (variant.valueless_by_exception()) {\r\n                return \"{valueless variant}\";\r\n            } else {\r\n                return std::visit(\r\n                    [](const auto& value) {\r\n                        return ::Catch::Detail::stringify(value);\r\n                    },\r\n                    variant\r\n                );\r\n            }\r\n        }\r\n    };\r\n}\r\n#endif // CATCH_CONFIG_ENABLE_VARIANT_STRINGMAKER\r\n\r\nnamespace Catch {\r\n    struct not_this_one {}; // Tag type for detecting which begin/ end are being selected\r\n\r\n    // Import begin/ end from std here so they are considered alongside the fallback (...) overloads in this namespace\r\n    using std::begin;\r\n    using std::end;\r\n\r\n    not_this_one begin( ... );\r\n    not_this_one end( ... );\r\n\r\n    template <typename T>\r\n    struct is_range {\r\n        static const bool value =\r\n            !std::is_same<decltype(begin(std::declval<T>())), not_this_one>::value &&\r\n            !std::is_same<decltype(end(std::declval<T>())), not_this_one>::value;\r\n    };\r\n\r\n#if defined(_MANAGED) // Managed types are never ranges\r\n    template <typename T>\r\n    struct is_range<T^> {\r\n        static const bool value = false;\r\n    };\r\n#endif\r\n\r\n    template<typename Range>\r\n    std::string rangeToString( Range const& range ) {\r\n        return ::Catch::Detail::rangeToString( begin( range ), end( range ) );\r\n    }\r\n\r\n    // Handle vector<bool> specially\r\n    template<typename Allocator>\r\n    std::string rangeToString( std::vector<bool, Allocator> const& v ) {\r\n        ReusableStringStream rss;\r\n        rss << \"{ \";\r\n        bool first = true;\r\n        for( bool b : v ) {\r\n            if( first )\r\n                first = false;\r\n            else\r\n                rss << \", \";\r\n            rss << ::Catch::Detail::stringify( b );\r\n        }\r\n        rss << \" }\";\r\n        return rss.str();\r\n    }\r\n\r\n    template<typename R>\r\n    struct StringMaker<R, typename std::enable_if<is_range<R>::value && !::Catch::Detail::IsStreamInsertable<R>::value>::type> {\r\n        static std::string convert( R const& range ) {\r\n            return rangeToString( range );\r\n        }\r\n    };\r\n\r\n    template <typename T, int SZ>\r\n    struct StringMaker<T[SZ]> {\r\n        static std::string convert(T const(&arr)[SZ]) {\r\n            return rangeToString(arr);\r\n        }\r\n    };\r\n\r\n} // namespace Catch\r\n\r\n// Separate std::chrono::duration specialization\r\n#if defined(CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER)\r\n#include <ctime>\r\n#include <ratio>\r\n#include <chrono>\r\n\r\nnamespace Catch {\r\n\r\ntemplate <class Ratio>\r\nstruct ratio_string {\r\n    static std::string symbol();\r\n};\r\n\r\ntemplate <class Ratio>\r\nstd::string ratio_string<Ratio>::symbol() {\r\n    Catch::ReusableStringStream rss;\r\n    rss << '[' << Ratio::num << '/'\r\n        << Ratio::den << ']';\r\n    return rss.str();\r\n}\r\ntemplate <>\r\nstruct ratio_string<std::atto> {\r\n    static std::string symbol();\r\n};\r\ntemplate <>\r\nstruct ratio_string<std::femto> {\r\n    static std::string symbol();\r\n};\r\ntemplate <>\r\nstruct ratio_string<std::pico> {\r\n    static std::string symbol();\r\n};\r\ntemplate <>\r\nstruct ratio_string<std::nano> {\r\n    static std::string symbol();\r\n};\r\ntemplate <>\r\nstruct ratio_string<std::micro> {\r\n    static std::string symbol();\r\n};\r\ntemplate <>\r\nstruct ratio_string<std::milli> {\r\n    static std::string symbol();\r\n};\r\n\r\n    ////////////\r\n    // std::chrono::duration specializations\r\n    template<typename Value, typename Ratio>\r\n    struct StringMaker<std::chrono::duration<Value, Ratio>> {\r\n        static std::string convert(std::chrono::duration<Value, Ratio> const& duration) {\r\n            ReusableStringStream rss;\r\n            rss << duration.count() << ' ' << ratio_string<Ratio>::symbol() << 's';\r\n            return rss.str();\r\n        }\r\n    };\r\n    template<typename Value>\r\n    struct StringMaker<std::chrono::duration<Value, std::ratio<1>>> {\r\n        static std::string convert(std::chrono::duration<Value, std::ratio<1>> const& duration) {\r\n            ReusableStringStream rss;\r\n            rss << duration.count() << \" s\";\r\n            return rss.str();\r\n        }\r\n    };\r\n    template<typename Value>\r\n    struct StringMaker<std::chrono::duration<Value, std::ratio<60>>> {\r\n        static std::string convert(std::chrono::duration<Value, std::ratio<60>> const& duration) {\r\n            ReusableStringStream rss;\r\n            rss << duration.count() << \" m\";\r\n            return rss.str();\r\n        }\r\n    };\r\n    template<typename Value>\r\n    struct StringMaker<std::chrono::duration<Value, std::ratio<3600>>> {\r\n        static std::string convert(std::chrono::duration<Value, std::ratio<3600>> const& duration) {\r\n            ReusableStringStream rss;\r\n            rss << duration.count() << \" h\";\r\n            return rss.str();\r\n        }\r\n    };\r\n\r\n    ////////////\r\n    // std::chrono::time_point specialization\r\n    // Generic time_point cannot be specialized, only std::chrono::time_point<system_clock>\r\n    template<typename Clock, typename Duration>\r\n    struct StringMaker<std::chrono::time_point<Clock, Duration>> {\r\n        static std::string convert(std::chrono::time_point<Clock, Duration> const& time_point) {\r\n            return ::Catch::Detail::stringify(time_point.time_since_epoch()) + \" since epoch\";\r\n        }\r\n    };\r\n    // std::chrono::time_point<system_clock> specialization\r\n    template<typename Duration>\r\n    struct StringMaker<std::chrono::time_point<std::chrono::system_clock, Duration>> {\r\n        static std::string convert(std::chrono::time_point<std::chrono::system_clock, Duration> const& time_point) {\r\n            auto converted = std::chrono::system_clock::to_time_t(time_point);\r\n\r\n#ifdef _MSC_VER\r\n            std::tm timeInfo = {};\r\n            gmtime_s(&timeInfo, &converted);\r\n#else\r\n            std::tm* timeInfo = std::gmtime(&converted);\r\n#endif\r\n\r\n            auto const timeStampSize = sizeof(\"2017-01-16T17:06:45Z\");\r\n            char timeStamp[timeStampSize];\r\n            const char * const fmt = \"%Y-%m-%dT%H:%M:%SZ\";\r\n\r\n#ifdef _MSC_VER\r\n            std::strftime(timeStamp, timeStampSize, fmt, &timeInfo);\r\n#else\r\n            std::strftime(timeStamp, timeStampSize, fmt, timeInfo);\r\n#endif\r\n            return std::string(timeStamp);\r\n        }\r\n    };\r\n}\r\n#endif // CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER\r\n\r\n#ifdef _MSC_VER\r\n#pragma warning(pop)\r\n#endif\r\n\r\n// end catch_tostring.h\r\n#include <iosfwd>\r\n\r\n#ifdef _MSC_VER\r\n#pragma warning(push)\r\n#pragma warning(disable:4389) // '==' : signed/unsigned mismatch\r\n#pragma warning(disable:4018) // more \"signed/unsigned mismatch\"\r\n#pragma warning(disable:4312) // Converting int to T* using reinterpret_cast (issue on x64 platform)\r\n#pragma warning(disable:4180) // qualifier applied to function type has no meaning\r\n#pragma warning(disable:4800) // Forcing result to true or false\r\n#endif\r\n\r\nnamespace Catch {\r\n\r\n    struct ITransientExpression {\r\n        auto isBinaryExpression() const -> bool { return m_isBinaryExpression; }\r\n        auto getResult() const -> bool { return m_result; }\r\n        virtual void streamReconstructedExpression( std::ostream &os ) const = 0;\r\n\r\n        ITransientExpression( bool isBinaryExpression, bool result )\r\n        :   m_isBinaryExpression( isBinaryExpression ),\r\n            m_result( result )\r\n        {}\r\n\r\n        // We don't actually need a virtual destructor, but many static analysers\r\n        // complain if it's not here :-(\r\n        virtual ~ITransientExpression();\r\n\r\n        bool m_isBinaryExpression;\r\n        bool m_result;\r\n\r\n    };\r\n\r\n    void formatReconstructedExpression( std::ostream &os, std::string const& lhs, StringRef op, std::string const& rhs );\r\n\r\n    template<typename LhsT, typename RhsT>\r\n    class BinaryExpr  : public ITransientExpression {\r\n        LhsT m_lhs;\r\n        StringRef m_op;\r\n        RhsT m_rhs;\r\n\r\n        void streamReconstructedExpression( std::ostream &os ) const override {\r\n            formatReconstructedExpression\r\n                    ( os, Catch::Detail::stringify( m_lhs ), m_op, Catch::Detail::stringify( m_rhs ) );\r\n        }\r\n\r\n    public:\r\n        BinaryExpr( bool comparisonResult, LhsT lhs, StringRef op, RhsT rhs )\r\n        :   ITransientExpression{ true, comparisonResult },\r\n            m_lhs( lhs ),\r\n            m_op( op ),\r\n            m_rhs( rhs )\r\n        {}\r\n\r\n        template<typename T>\r\n        auto operator && ( T ) const -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<T>::value,\r\n            \"chained comparisons are not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n\r\n        template<typename T>\r\n        auto operator || ( T ) const -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<T>::value,\r\n            \"chained comparisons are not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n\r\n        template<typename T>\r\n        auto operator == ( T ) const -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<T>::value,\r\n            \"chained comparisons are not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n\r\n        template<typename T>\r\n        auto operator != ( T ) const -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<T>::value,\r\n            \"chained comparisons are not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n\r\n        template<typename T>\r\n        auto operator > ( T ) const -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<T>::value,\r\n            \"chained comparisons are not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n\r\n        template<typename T>\r\n        auto operator < ( T ) const -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<T>::value,\r\n            \"chained comparisons are not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n\r\n        template<typename T>\r\n        auto operator >= ( T ) const -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<T>::value,\r\n            \"chained comparisons are not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n\r\n        template<typename T>\r\n        auto operator <= ( T ) const -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<T>::value,\r\n            \"chained comparisons are not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n    };\r\n\r\n    template<typename LhsT>\r\n    class UnaryExpr : public ITransientExpression {\r\n        LhsT m_lhs;\r\n\r\n        void streamReconstructedExpression( std::ostream &os ) const override {\r\n            os << Catch::Detail::stringify( m_lhs );\r\n        }\r\n\r\n    public:\r\n        explicit UnaryExpr( LhsT lhs )\r\n        :   ITransientExpression{ false, static_cast<bool>(lhs) },\r\n            m_lhs( lhs )\r\n        {}\r\n    };\r\n\r\n    // Specialised comparison functions to handle equality comparisons between ints and pointers (NULL deduces as an int)\r\n    template<typename LhsT, typename RhsT>\r\n    auto compareEqual( LhsT const& lhs, RhsT const& rhs ) -> bool { return static_cast<bool>(lhs == rhs); }\r\n    template<typename T>\r\n    auto compareEqual( T* const& lhs, int rhs ) -> bool { return lhs == reinterpret_cast<void const*>( rhs ); }\r\n    template<typename T>\r\n    auto compareEqual( T* const& lhs, long rhs ) -> bool { return lhs == reinterpret_cast<void const*>( rhs ); }\r\n    template<typename T>\r\n    auto compareEqual( int lhs, T* const& rhs ) -> bool { return reinterpret_cast<void const*>( lhs ) == rhs; }\r\n    template<typename T>\r\n    auto compareEqual( long lhs, T* const& rhs ) -> bool { return reinterpret_cast<void const*>( lhs ) == rhs; }\r\n\r\n    template<typename LhsT, typename RhsT>\r\n    auto compareNotEqual( LhsT const& lhs, RhsT&& rhs ) -> bool { return static_cast<bool>(lhs != rhs); }\r\n    template<typename T>\r\n    auto compareNotEqual( T* const& lhs, int rhs ) -> bool { return lhs != reinterpret_cast<void const*>( rhs ); }\r\n    template<typename T>\r\n    auto compareNotEqual( T* const& lhs, long rhs ) -> bool { return lhs != reinterpret_cast<void const*>( rhs ); }\r\n    template<typename T>\r\n    auto compareNotEqual( int lhs, T* const& rhs ) -> bool { return reinterpret_cast<void const*>( lhs ) != rhs; }\r\n    template<typename T>\r\n    auto compareNotEqual( long lhs, T* const& rhs ) -> bool { return reinterpret_cast<void const*>( lhs ) != rhs; }\r\n\r\n    template<typename LhsT>\r\n    class ExprLhs {\r\n        LhsT m_lhs;\r\n    public:\r\n        explicit ExprLhs( LhsT lhs ) : m_lhs( lhs ) {}\r\n\r\n        template<typename RhsT>\r\n        auto operator == ( RhsT const& rhs ) -> BinaryExpr<LhsT, RhsT const&> const {\r\n            return { compareEqual( m_lhs, rhs ), m_lhs, \"==\", rhs };\r\n        }\r\n        auto operator == ( bool rhs ) -> BinaryExpr<LhsT, bool> const {\r\n            return { m_lhs == rhs, m_lhs, \"==\", rhs };\r\n        }\r\n\r\n        template<typename RhsT>\r\n        auto operator != ( RhsT const& rhs ) -> BinaryExpr<LhsT, RhsT const&> const {\r\n            return { compareNotEqual( m_lhs, rhs ), m_lhs, \"!=\", rhs };\r\n        }\r\n        auto operator != ( bool rhs ) -> BinaryExpr<LhsT, bool> const {\r\n            return { m_lhs != rhs, m_lhs, \"!=\", rhs };\r\n        }\r\n\r\n        template<typename RhsT>\r\n        auto operator > ( RhsT const& rhs ) -> BinaryExpr<LhsT, RhsT const&> const {\r\n            return { static_cast<bool>(m_lhs > rhs), m_lhs, \">\", rhs };\r\n        }\r\n        template<typename RhsT>\r\n        auto operator < ( RhsT const& rhs ) -> BinaryExpr<LhsT, RhsT const&> const {\r\n            return { static_cast<bool>(m_lhs < rhs), m_lhs, \"<\", rhs };\r\n        }\r\n        template<typename RhsT>\r\n        auto operator >= ( RhsT const& rhs ) -> BinaryExpr<LhsT, RhsT const&> const {\r\n            return { static_cast<bool>(m_lhs >= rhs), m_lhs, \">=\", rhs };\r\n        }\r\n        template<typename RhsT>\r\n        auto operator <= ( RhsT const& rhs ) -> BinaryExpr<LhsT, RhsT const&> const {\r\n            return { static_cast<bool>(m_lhs <= rhs), m_lhs, \"<=\", rhs };\r\n        }\r\n\r\n        template<typename RhsT>\r\n        auto operator && ( RhsT const& ) -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<RhsT>::value,\r\n            \"operator&& is not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n\r\n        template<typename RhsT>\r\n        auto operator || ( RhsT const& ) -> BinaryExpr<LhsT, RhsT const&> const {\r\n            static_assert(always_false<RhsT>::value,\r\n            \"operator|| is not supported inside assertions, \"\r\n            \"wrap the expression inside parentheses, or decompose it\");\r\n        }\r\n\r\n        auto makeUnaryExpr() const -> UnaryExpr<LhsT> {\r\n            return UnaryExpr<LhsT>{ m_lhs };\r\n        }\r\n    };\r\n\r\n    void handleExpression( ITransientExpression const& expr );\r\n\r\n    template<typename T>\r\n    void handleExpression( ExprLhs<T> const& expr ) {\r\n        handleExpression( expr.makeUnaryExpr() );\r\n    }\r\n\r\n    struct Decomposer {\r\n        template<typename T>\r\n        auto operator <= ( T const& lhs ) -> ExprLhs<T const&> {\r\n            return ExprLhs<T const&>{ lhs };\r\n        }\r\n\r\n        auto operator <=( bool value ) -> ExprLhs<bool> {\r\n            return ExprLhs<bool>{ value };\r\n        }\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n#ifdef _MSC_VER\r\n#pragma warning(pop)\r\n#endif\r\n\r\n// end catch_decomposer.h\r\n// start catch_interfaces_capture.h\r\n\r\n#include <string>\r\n\r\nnamespace Catch {\r\n\r\n    class AssertionResult;\r\n    struct AssertionInfo;\r\n    struct SectionInfo;\r\n    struct SectionEndInfo;\r\n    struct MessageInfo;\r\n    struct MessageBuilder;\r\n    struct Counts;\r\n    struct BenchmarkInfo;\r\n    struct BenchmarkStats;\r\n    struct AssertionReaction;\r\n    struct SourceLineInfo;\r\n\r\n    struct ITransientExpression;\r\n    struct IGeneratorTracker;\r\n\r\n    struct IResultCapture {\r\n\r\n        virtual ~IResultCapture();\r\n\r\n        virtual bool sectionStarted(    SectionInfo const& sectionInfo,\r\n                                        Counts& assertions ) = 0;\r\n        virtual void sectionEnded( SectionEndInfo const& endInfo ) = 0;\r\n        virtual void sectionEndedEarly( SectionEndInfo const& endInfo ) = 0;\r\n\r\n        virtual auto acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker& = 0;\r\n\r\n        virtual void benchmarkStarting( BenchmarkInfo const& info ) = 0;\r\n        virtual void benchmarkEnded( BenchmarkStats const& stats ) = 0;\r\n\r\n        virtual void pushScopedMessage( MessageInfo const& message ) = 0;\r\n        virtual void popScopedMessage( MessageInfo const& message ) = 0;\r\n\r\n        virtual void emplaceUnscopedMessage( MessageBuilder const& builder ) = 0;\r\n\r\n        virtual void handleFatalErrorCondition( StringRef message ) = 0;\r\n\r\n        virtual void handleExpr\r\n                (   AssertionInfo const& info,\r\n                    ITransientExpression const& expr,\r\n                    AssertionReaction& reaction ) = 0;\r\n        virtual void handleMessage\r\n                (   AssertionInfo const& info,\r\n                    ResultWas::OfType resultType,\r\n                    StringRef const& message,\r\n                    AssertionReaction& reaction ) = 0;\r\n        virtual void handleUnexpectedExceptionNotThrown\r\n                (   AssertionInfo const& info,\r\n                    AssertionReaction& reaction ) = 0;\r\n        virtual void handleUnexpectedInflightException\r\n                (   AssertionInfo const& info,\r\n                    std::string const& message,\r\n                    AssertionReaction& reaction ) = 0;\r\n        virtual void handleIncomplete\r\n                (   AssertionInfo const& info ) = 0;\r\n        virtual void handleNonExpr\r\n                (   AssertionInfo const &info,\r\n                    ResultWas::OfType resultType,\r\n                    AssertionReaction &reaction ) = 0;\r\n\r\n        virtual bool lastAssertionPassed() = 0;\r\n        virtual void assertionPassed() = 0;\r\n\r\n        // Deprecated, do not use:\r\n        virtual std::string getCurrentTestName() const = 0;\r\n        virtual const AssertionResult* getLastResult() const = 0;\r\n        virtual void exceptionEarlyReported() = 0;\r\n    };\r\n\r\n    IResultCapture& getResultCapture();\r\n}\r\n\r\n// end catch_interfaces_capture.h\r\nnamespace Catch {\r\n\r\n    struct TestFailureException{};\r\n    struct AssertionResultData;\r\n    struct IResultCapture;\r\n    class RunContext;\r\n\r\n    class LazyExpression {\r\n        friend class AssertionHandler;\r\n        friend struct AssertionStats;\r\n        friend class RunContext;\r\n\r\n        ITransientExpression const* m_transientExpression = nullptr;\r\n        bool m_isNegated;\r\n    public:\r\n        LazyExpression( bool isNegated );\r\n        LazyExpression( LazyExpression const& other );\r\n        LazyExpression& operator = ( LazyExpression const& ) = delete;\r\n\r\n        explicit operator bool() const;\r\n\r\n        friend auto operator << ( std::ostream& os, LazyExpression const& lazyExpr ) -> std::ostream&;\r\n    };\r\n\r\n    struct AssertionReaction {\r\n        bool shouldDebugBreak = false;\r\n        bool shouldThrow = false;\r\n    };\r\n\r\n    class AssertionHandler {\r\n        AssertionInfo m_assertionInfo;\r\n        AssertionReaction m_reaction;\r\n        bool m_completed = false;\r\n        IResultCapture& m_resultCapture;\r\n\r\n    public:\r\n        AssertionHandler\r\n            (   StringRef const& macroName,\r\n                SourceLineInfo const& lineInfo,\r\n                StringRef capturedExpression,\r\n                ResultDisposition::Flags resultDisposition );\r\n        ~AssertionHandler() {\r\n            if ( !m_completed ) {\r\n                m_resultCapture.handleIncomplete( m_assertionInfo );\r\n            }\r\n        }\r\n\r\n        template<typename T>\r\n        void handleExpr( ExprLhs<T> const& expr ) {\r\n            handleExpr( expr.makeUnaryExpr() );\r\n        }\r\n        void handleExpr( ITransientExpression const& expr );\r\n\r\n        void handleMessage(ResultWas::OfType resultType, StringRef const& message);\r\n\r\n        void handleExceptionThrownAsExpected();\r\n        void handleUnexpectedExceptionNotThrown();\r\n        void handleExceptionNotThrownAsExpected();\r\n        void handleThrowingCallSkipped();\r\n        void handleUnexpectedInflightException();\r\n\r\n        void complete();\r\n        void setCompleted();\r\n\r\n        // query\r\n        auto allowThrows() const -> bool;\r\n    };\r\n\r\n    void handleExceptionMatchExpr( AssertionHandler& handler, std::string const& str, StringRef const& matcherString );\r\n\r\n} // namespace Catch\r\n\r\n// end catch_assertionhandler.h\r\n// start catch_message.h\r\n\r\n#include <string>\r\n#include <vector>\r\n\r\nnamespace Catch {\r\n\r\n    struct MessageInfo {\r\n        MessageInfo(    StringRef const& _macroName,\r\n                        SourceLineInfo const& _lineInfo,\r\n                        ResultWas::OfType _type );\r\n\r\n        StringRef macroName;\r\n        std::string message;\r\n        SourceLineInfo lineInfo;\r\n        ResultWas::OfType type;\r\n        unsigned int sequence;\r\n\r\n        bool operator == ( MessageInfo const& other ) const;\r\n        bool operator < ( MessageInfo const& other ) const;\r\n    private:\r\n        static unsigned int globalCount;\r\n    };\r\n\r\n    struct MessageStream {\r\n\r\n        template<typename T>\r\n        MessageStream& operator << ( T const& value ) {\r\n            m_stream << value;\r\n            return *this;\r\n        }\r\n\r\n        ReusableStringStream m_stream;\r\n    };\r\n\r\n    struct MessageBuilder : MessageStream {\r\n        MessageBuilder( StringRef const& macroName,\r\n                        SourceLineInfo const& lineInfo,\r\n                        ResultWas::OfType type );\r\n\r\n        template<typename T>\r\n        MessageBuilder& operator << ( T const& value ) {\r\n            m_stream << value;\r\n            return *this;\r\n        }\r\n\r\n        MessageInfo m_info;\r\n    };\r\n\r\n    class ScopedMessage {\r\n    public:\r\n        explicit ScopedMessage( MessageBuilder const& builder );\r\n        ScopedMessage( ScopedMessage& duplicate ) = delete;\r\n        ScopedMessage( ScopedMessage&& old );\r\n        ~ScopedMessage();\r\n\r\n        MessageInfo m_info;\r\n        bool m_moved;\r\n    };\r\n\r\n    class Capturer {\r\n        std::vector<MessageInfo> m_messages;\r\n        IResultCapture& m_resultCapture = getResultCapture();\r\n        size_t m_captured = 0;\r\n    public:\r\n        Capturer( StringRef macroName, SourceLineInfo const& lineInfo, ResultWas::OfType resultType, StringRef names );\r\n        ~Capturer();\r\n\r\n        void captureValue( size_t index, std::string const& value );\r\n\r\n        template<typename T>\r\n        void captureValues( size_t index, T const& value ) {\r\n            captureValue( index, Catch::Detail::stringify( value ) );\r\n        }\r\n\r\n        template<typename T, typename... Ts>\r\n        void captureValues( size_t index, T const& value, Ts const&... values ) {\r\n            captureValue( index, Catch::Detail::stringify(value) );\r\n            captureValues( index+1, values... );\r\n        }\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_message.h\r\n#if !defined(CATCH_CONFIG_DISABLE)\r\n\r\n#if !defined(CATCH_CONFIG_DISABLE_STRINGIFICATION)\r\n  #define CATCH_INTERNAL_STRINGIFY(...) #__VA_ARGS__\r\n#else\r\n  #define CATCH_INTERNAL_STRINGIFY(...) \"Disabled by CATCH_CONFIG_DISABLE_STRINGIFICATION\"\r\n#endif\r\n\r\n#if defined(CATCH_CONFIG_FAST_COMPILE) || defined(CATCH_CONFIG_DISABLE_EXCEPTIONS)\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n// Another way to speed-up compilation is to omit local try-catch for REQUIRE*\r\n// macros.\r\n#define INTERNAL_CATCH_TRY\r\n#define INTERNAL_CATCH_CATCH( capturer )\r\n\r\n#else // CATCH_CONFIG_FAST_COMPILE\r\n\r\n#define INTERNAL_CATCH_TRY try\r\n#define INTERNAL_CATCH_CATCH( handler ) catch(...) { handler.handleUnexpectedInflightException(); }\r\n\r\n#endif\r\n\r\n#define INTERNAL_CATCH_REACT( handler ) handler.complete();\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_TEST( macroName, resultDisposition, ... ) \\\r\n    do { \\\r\n        Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__), resultDisposition ); \\\r\n        INTERNAL_CATCH_TRY { \\\r\n            CATCH_INTERNAL_SUPPRESS_PARENTHESES_WARNINGS \\\r\n            catchAssertionHandler.handleExpr( Catch::Decomposer() <= __VA_ARGS__ ); \\\r\n            CATCH_INTERNAL_UNSUPPRESS_PARENTHESES_WARNINGS \\\r\n        } INTERNAL_CATCH_CATCH( catchAssertionHandler ) \\\r\n        INTERNAL_CATCH_REACT( catchAssertionHandler ) \\\r\n    } while( (void)0, (false) && static_cast<bool>( !!(__VA_ARGS__) ) ) // the expression here is never evaluated at runtime but it forces the compiler to give it a look\r\n    // The double negation silences MSVC's C4800 warning, the static_cast forces short-circuit evaluation if the type has overloaded &&.\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_IF( macroName, resultDisposition, ... ) \\\r\n    INTERNAL_CATCH_TEST( macroName, resultDisposition, __VA_ARGS__ ); \\\r\n    if( Catch::getResultCapture().lastAssertionPassed() )\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_ELSE( macroName, resultDisposition, ... ) \\\r\n    INTERNAL_CATCH_TEST( macroName, resultDisposition, __VA_ARGS__ ); \\\r\n    if( !Catch::getResultCapture().lastAssertionPassed() )\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_NO_THROW( macroName, resultDisposition, ... ) \\\r\n    do { \\\r\n        Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__), resultDisposition ); \\\r\n        try { \\\r\n            static_cast<void>(__VA_ARGS__); \\\r\n            catchAssertionHandler.handleExceptionNotThrownAsExpected(); \\\r\n        } \\\r\n        catch( ... ) { \\\r\n            catchAssertionHandler.handleUnexpectedInflightException(); \\\r\n        } \\\r\n        INTERNAL_CATCH_REACT( catchAssertionHandler ) \\\r\n    } while( false )\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_THROWS( macroName, resultDisposition, ... ) \\\r\n    do { \\\r\n        Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__), resultDisposition); \\\r\n        if( catchAssertionHandler.allowThrows() ) \\\r\n            try { \\\r\n                static_cast<void>(__VA_ARGS__); \\\r\n                catchAssertionHandler.handleUnexpectedExceptionNotThrown(); \\\r\n            } \\\r\n            catch( ... ) { \\\r\n                catchAssertionHandler.handleExceptionThrownAsExpected(); \\\r\n            } \\\r\n        else \\\r\n            catchAssertionHandler.handleThrowingCallSkipped(); \\\r\n        INTERNAL_CATCH_REACT( catchAssertionHandler ) \\\r\n    } while( false )\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_THROWS_AS( macroName, exceptionType, resultDisposition, expr ) \\\r\n    do { \\\r\n        Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(expr) \", \" CATCH_INTERNAL_STRINGIFY(exceptionType), resultDisposition ); \\\r\n        if( catchAssertionHandler.allowThrows() ) \\\r\n            try { \\\r\n                static_cast<void>(expr); \\\r\n                catchAssertionHandler.handleUnexpectedExceptionNotThrown(); \\\r\n            } \\\r\n            catch( exceptionType const& ) { \\\r\n                catchAssertionHandler.handleExceptionThrownAsExpected(); \\\r\n            } \\\r\n            catch( ... ) { \\\r\n                catchAssertionHandler.handleUnexpectedInflightException(); \\\r\n            } \\\r\n        else \\\r\n            catchAssertionHandler.handleThrowingCallSkipped(); \\\r\n        INTERNAL_CATCH_REACT( catchAssertionHandler ) \\\r\n    } while( false )\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_MSG( macroName, messageType, resultDisposition, ... ) \\\r\n    do { \\\r\n        Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, Catch::StringRef(), resultDisposition ); \\\r\n        catchAssertionHandler.handleMessage( messageType, ( Catch::MessageStream() << __VA_ARGS__ + ::Catch::StreamEndStop() ).m_stream.str() ); \\\r\n        INTERNAL_CATCH_REACT( catchAssertionHandler ) \\\r\n    } while( false )\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_CAPTURE( varName, macroName, ... ) \\\r\n    auto varName = Catch::Capturer( macroName, CATCH_INTERNAL_LINEINFO, Catch::ResultWas::Info, #__VA_ARGS__ ); \\\r\n    varName.captureValues( 0, __VA_ARGS__ )\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_INFO( macroName, log ) \\\r\n    Catch::ScopedMessage INTERNAL_CATCH_UNIQUE_NAME( scopedMessage )( Catch::MessageBuilder( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, Catch::ResultWas::Info ) << log );\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_UNSCOPED_INFO( macroName, log ) \\\r\n    Catch::getResultCapture().emplaceUnscopedMessage( Catch::MessageBuilder( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, Catch::ResultWas::Info ) << log )\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n// Although this is matcher-based, it can be used with just a string\r\n#define INTERNAL_CATCH_THROWS_STR_MATCHES( macroName, resultDisposition, matcher, ... ) \\\r\n    do { \\\r\n        Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__) \", \" CATCH_INTERNAL_STRINGIFY(matcher), resultDisposition ); \\\r\n        if( catchAssertionHandler.allowThrows() ) \\\r\n            try { \\\r\n                static_cast<void>(__VA_ARGS__); \\\r\n                catchAssertionHandler.handleUnexpectedExceptionNotThrown(); \\\r\n            } \\\r\n            catch( ... ) { \\\r\n                Catch::handleExceptionMatchExpr( catchAssertionHandler, matcher, #matcher##_catch_sr ); \\\r\n            } \\\r\n        else \\\r\n            catchAssertionHandler.handleThrowingCallSkipped(); \\\r\n        INTERNAL_CATCH_REACT( catchAssertionHandler ) \\\r\n    } while( false )\r\n\r\n#endif // CATCH_CONFIG_DISABLE\r\n\r\n// end catch_capture.hpp\r\n// start catch_section.h\r\n\r\n// start catch_section_info.h\r\n\r\n// start catch_totals.h\r\n\r\n#include <cstddef>\r\n\r\nnamespace Catch {\r\n\r\n    struct Counts {\r\n        Counts operator - ( Counts const& other ) const;\r\n        Counts& operator += ( Counts const& other );\r\n\r\n        std::size_t total() const;\r\n        bool allPassed() const;\r\n        bool allOk() const;\r\n\r\n        std::size_t passed = 0;\r\n        std::size_t failed = 0;\r\n        std::size_t failedButOk = 0;\r\n    };\r\n\r\n    struct Totals {\r\n\r\n        Totals operator - ( Totals const& other ) const;\r\n        Totals& operator += ( Totals const& other );\r\n\r\n        Totals delta( Totals const& prevTotals ) const;\r\n\r\n        int error = 0;\r\n        Counts assertions;\r\n        Counts testCases;\r\n    };\r\n}\r\n\r\n// end catch_totals.h\r\n#include <string>\r\n\r\nnamespace Catch {\r\n\r\n    struct SectionInfo {\r\n        SectionInfo\r\n            (   SourceLineInfo const& _lineInfo,\r\n                std::string const& _name );\r\n\r\n        // Deprecated\r\n        SectionInfo\r\n            (   SourceLineInfo const& _lineInfo,\r\n                std::string const& _name,\r\n                std::string const& ) : SectionInfo( _lineInfo, _name ) {}\r\n\r\n        std::string name;\r\n        std::string description; // !Deprecated: this will always be empty\r\n        SourceLineInfo lineInfo;\r\n    };\r\n\r\n    struct SectionEndInfo {\r\n        SectionInfo sectionInfo;\r\n        Counts prevAssertions;\r\n        double durationInSeconds;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_section_info.h\r\n// start catch_timer.h\r\n\r\n#include <cstdint>\r\n\r\nnamespace Catch {\r\n\r\n    auto getCurrentNanosecondsSinceEpoch() -> uint64_t;\r\n    auto getEstimatedClockResolution() -> uint64_t;\r\n\r\n    class Timer {\r\n        uint64_t m_nanoseconds = 0;\r\n    public:\r\n        void start();\r\n        auto getElapsedNanoseconds() const -> uint64_t;\r\n        auto getElapsedMicroseconds() const -> uint64_t;\r\n        auto getElapsedMilliseconds() const -> unsigned int;\r\n        auto getElapsedSeconds() const -> double;\r\n    };\r\n\r\n} // namespace Catch\r\n\r\n// end catch_timer.h\r\n#include <string>\r\n\r\nnamespace Catch {\r\n\r\n    class Section : NonCopyable {\r\n    public:\r\n        Section( SectionInfo const& info );\r\n        ~Section();\r\n\r\n        // This indicates whether the section should be executed or not\r\n        explicit operator bool() const;\r\n\r\n    private:\r\n        SectionInfo m_info;\r\n\r\n        std::string m_name;\r\n        Counts m_assertions;\r\n        bool m_sectionIncluded;\r\n        Timer m_timer;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n#define INTERNAL_CATCH_SECTION( ... ) \\\r\n    CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS \\\r\n    if( Catch::Section const& INTERNAL_CATCH_UNIQUE_NAME( catch_internal_Section ) = Catch::SectionInfo( CATCH_INTERNAL_LINEINFO, __VA_ARGS__ ) ) \\\r\n    CATCH_INTERNAL_UNSUPPRESS_UNUSED_WARNINGS\r\n\r\n#define INTERNAL_CATCH_DYNAMIC_SECTION( ... ) \\\r\n    CATCH_INTERNAL_SUPPRESS_UNUSED_WARNINGS \\\r\n    if( Catch::Section const& INTERNAL_CATCH_UNIQUE_NAME( catch_internal_Section ) = Catch::SectionInfo( CATCH_INTERNAL_LINEINFO, (Catch::ReusableStringStream() << __VA_ARGS__).str() ) ) \\\r\n    CATCH_INTERNAL_UNSUPPRESS_UNUSED_WARNINGS\r\n\r\n// end catch_section.h\r\n// start catch_benchmark.h\r\n\r\n#include <cstdint>\r\n#include <string>\r\n\r\nnamespace Catch {\r\n\r\n    class BenchmarkLooper {\r\n\r\n        std::string m_name;\r\n        std::size_t m_count = 0;\r\n        std::size_t m_iterationsToRun = 1;\r\n        uint64_t m_resolution;\r\n        Timer m_timer;\r\n\r\n        static auto getResolution() -> uint64_t;\r\n    public:\r\n        // Keep most of this inline as it's on the code path that is being timed\r\n        BenchmarkLooper( StringRef name )\r\n        :   m_name( name ),\r\n            m_resolution( getResolution() )\r\n        {\r\n            reportStart();\r\n            m_timer.start();\r\n        }\r\n\r\n        explicit operator bool() {\r\n            if( m_count < m_iterationsToRun )\r\n                return true;\r\n            return needsMoreIterations();\r\n        }\r\n\r\n        void increment() {\r\n            ++m_count;\r\n        }\r\n\r\n        void reportStart();\r\n        auto needsMoreIterations() -> bool;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n#define BENCHMARK( name ) \\\r\n    for( Catch::BenchmarkLooper looper( name ); looper; looper.increment() )\r\n\r\n// end catch_benchmark.h\r\n// start catch_interfaces_exception.h\r\n\r\n// start catch_interfaces_registry_hub.h\r\n\r\n#include <string>\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    class TestCase;\r\n    struct ITestCaseRegistry;\r\n    struct IExceptionTranslatorRegistry;\r\n    struct IExceptionTranslator;\r\n    struct IReporterRegistry;\r\n    struct IReporterFactory;\r\n    struct ITagAliasRegistry;\r\n    class StartupExceptionRegistry;\r\n\r\n    using IReporterFactoryPtr = std::shared_ptr<IReporterFactory>;\r\n\r\n    struct IRegistryHub {\r\n        virtual ~IRegistryHub();\r\n\r\n        virtual IReporterRegistry const& getReporterRegistry() const = 0;\r\n        virtual ITestCaseRegistry const& getTestCaseRegistry() const = 0;\r\n        virtual ITagAliasRegistry const& getTagAliasRegistry() const = 0;\r\n\r\n        virtual IExceptionTranslatorRegistry const& getExceptionTranslatorRegistry() const = 0;\r\n\r\n        virtual StartupExceptionRegistry const& getStartupExceptionRegistry() const = 0;\r\n    };\r\n\r\n    struct IMutableRegistryHub {\r\n        virtual ~IMutableRegistryHub();\r\n        virtual void registerReporter( std::string const& name, IReporterFactoryPtr const& factory ) = 0;\r\n        virtual void registerListener( IReporterFactoryPtr const& factory ) = 0;\r\n        virtual void registerTest( TestCase const& testInfo ) = 0;\r\n        virtual void registerTranslator( const IExceptionTranslator* translator ) = 0;\r\n        virtual void registerTagAlias( std::string const& alias, std::string const& tag, SourceLineInfo const& lineInfo ) = 0;\r\n        virtual void registerStartupException() noexcept = 0;\r\n    };\r\n\r\n    IRegistryHub const& getRegistryHub();\r\n    IMutableRegistryHub& getMutableRegistryHub();\r\n    void cleanUp();\r\n    std::string translateActiveException();\r\n\r\n}\r\n\r\n// end catch_interfaces_registry_hub.h\r\n#if defined(CATCH_CONFIG_DISABLE)\r\n    #define INTERNAL_CATCH_TRANSLATE_EXCEPTION_NO_REG( translatorName, signature) \\\r\n        static std::string translatorName( signature )\r\n#endif\r\n\r\n#include <exception>\r\n#include <string>\r\n#include <vector>\r\n\r\nnamespace Catch {\r\n    using exceptionTranslateFunction = std::string(*)();\r\n\r\n    struct IExceptionTranslator;\r\n    using ExceptionTranslators = std::vector<std::unique_ptr<IExceptionTranslator const>>;\r\n\r\n    struct IExceptionTranslator {\r\n        virtual ~IExceptionTranslator();\r\n        virtual std::string translate( ExceptionTranslators::const_iterator it, ExceptionTranslators::const_iterator itEnd ) const = 0;\r\n    };\r\n\r\n    struct IExceptionTranslatorRegistry {\r\n        virtual ~IExceptionTranslatorRegistry();\r\n\r\n        virtual std::string translateActiveException() const = 0;\r\n    };\r\n\r\n    class ExceptionTranslatorRegistrar {\r\n        template<typename T>\r\n        class ExceptionTranslator : public IExceptionTranslator {\r\n        public:\r\n\r\n            ExceptionTranslator( std::string(*translateFunction)( T& ) )\r\n            : m_translateFunction( translateFunction )\r\n            {}\r\n\r\n            std::string translate( ExceptionTranslators::const_iterator it, ExceptionTranslators::const_iterator itEnd ) const override {\r\n                try {\r\n                    if( it == itEnd )\r\n                        std::rethrow_exception(std::current_exception());\r\n                    else\r\n                        return (*it)->translate( it+1, itEnd );\r\n                }\r\n                catch( T& ex ) {\r\n                    return m_translateFunction( ex );\r\n                }\r\n            }\r\n\r\n        protected:\r\n            std::string(*m_translateFunction)( T& );\r\n        };\r\n\r\n    public:\r\n        template<typename T>\r\n        ExceptionTranslatorRegistrar( std::string(*translateFunction)( T& ) ) {\r\n            getMutableRegistryHub().registerTranslator\r\n                ( new ExceptionTranslator<T>( translateFunction ) );\r\n        }\r\n    };\r\n}\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_TRANSLATE_EXCEPTION2( translatorName, signature ) \\\r\n    static std::string translatorName( signature ); \\\r\n    CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS \\\r\n    namespace{ Catch::ExceptionTranslatorRegistrar INTERNAL_CATCH_UNIQUE_NAME( catch_internal_ExceptionRegistrar )( &translatorName ); } \\\r\n    CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS \\\r\n    static std::string translatorName( signature )\r\n\r\n#define INTERNAL_CATCH_TRANSLATE_EXCEPTION( signature ) INTERNAL_CATCH_TRANSLATE_EXCEPTION2( INTERNAL_CATCH_UNIQUE_NAME( catch_internal_ExceptionTranslator ), signature )\r\n\r\n// end catch_interfaces_exception.h\r\n// start catch_approx.h\r\n\r\n#include <type_traits>\r\n\r\nnamespace Catch {\r\nnamespace Detail {\r\n\r\n    class Approx {\r\n    private:\r\n        bool equalityComparisonImpl(double other) const;\r\n        // Validates the new margin (margin >= 0)\r\n        // out-of-line to avoid including stdexcept in the header\r\n        void setMargin(double margin);\r\n        // Validates the new epsilon (0 < epsilon < 1)\r\n        // out-of-line to avoid including stdexcept in the header\r\n        void setEpsilon(double epsilon);\r\n\r\n    public:\r\n        explicit Approx ( double value );\r\n\r\n        static Approx custom();\r\n\r\n        Approx operator-() const;\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        Approx operator()( T const& value ) {\r\n            Approx approx( static_cast<double>(value) );\r\n            approx.m_epsilon = m_epsilon;\r\n            approx.m_margin = m_margin;\r\n            approx.m_scale = m_scale;\r\n            return approx;\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        explicit Approx( T const& value ): Approx(static_cast<double>(value))\r\n        {}\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        friend bool operator == ( const T& lhs, Approx const& rhs ) {\r\n            auto lhs_v = static_cast<double>(lhs);\r\n            return rhs.equalityComparisonImpl(lhs_v);\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        friend bool operator == ( Approx const& lhs, const T& rhs ) {\r\n            return operator==( rhs, lhs );\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        friend bool operator != ( T const& lhs, Approx const& rhs ) {\r\n            return !operator==( lhs, rhs );\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        friend bool operator != ( Approx const& lhs, T const& rhs ) {\r\n            return !operator==( rhs, lhs );\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        friend bool operator <= ( T const& lhs, Approx const& rhs ) {\r\n            return static_cast<double>(lhs) < rhs.m_value || lhs == rhs;\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        friend bool operator <= ( Approx const& lhs, T const& rhs ) {\r\n            return lhs.m_value < static_cast<double>(rhs) || lhs == rhs;\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        friend bool operator >= ( T const& lhs, Approx const& rhs ) {\r\n            return static_cast<double>(lhs) > rhs.m_value || lhs == rhs;\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        friend bool operator >= ( Approx const& lhs, T const& rhs ) {\r\n            return lhs.m_value > static_cast<double>(rhs) || lhs == rhs;\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        Approx& epsilon( T const& newEpsilon ) {\r\n            double epsilonAsDouble = static_cast<double>(newEpsilon);\r\n            setEpsilon(epsilonAsDouble);\r\n            return *this;\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        Approx& margin( T const& newMargin ) {\r\n            double marginAsDouble = static_cast<double>(newMargin);\r\n            setMargin(marginAsDouble);\r\n            return *this;\r\n        }\r\n\r\n        template <typename T, typename = typename std::enable_if<std::is_constructible<double, T>::value>::type>\r\n        Approx& scale( T const& newScale ) {\r\n            m_scale = static_cast<double>(newScale);\r\n            return *this;\r\n        }\r\n\r\n        std::string toString() const;\r\n\r\n    private:\r\n        double m_epsilon;\r\n        double m_margin;\r\n        double m_scale;\r\n        double m_value;\r\n    };\r\n} // end namespace Detail\r\n\r\nnamespace literals {\r\n    Detail::Approx operator \"\" _a(long double val);\r\n    Detail::Approx operator \"\" _a(unsigned long long val);\r\n} // end namespace literals\r\n\r\ntemplate<>\r\nstruct StringMaker<Catch::Detail::Approx> {\r\n    static std::string convert(Catch::Detail::Approx const& value);\r\n};\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_approx.h\r\n// start catch_string_manip.h\r\n\r\n#include <string>\r\n#include <iosfwd>\r\n\r\nnamespace Catch {\r\n\r\n    bool startsWith( std::string const& s, std::string const& prefix );\r\n    bool startsWith( std::string const& s, char prefix );\r\n    bool endsWith( std::string const& s, std::string const& suffix );\r\n    bool endsWith( std::string const& s, char suffix );\r\n    bool contains( std::string const& s, std::string const& infix );\r\n    void toLowerInPlace( std::string& s );\r\n    std::string toLower( std::string const& s );\r\n    std::string trim( std::string const& str );\r\n    bool replaceInPlace( std::string& str, std::string const& replaceThis, std::string const& withThis );\r\n\r\n    struct pluralise {\r\n        pluralise( std::size_t count, std::string const& label );\r\n\r\n        friend std::ostream& operator << ( std::ostream& os, pluralise const& pluraliser );\r\n\r\n        std::size_t m_count;\r\n        std::string m_label;\r\n    };\r\n}\r\n\r\n// end catch_string_manip.h\r\n#ifndef CATCH_CONFIG_DISABLE_MATCHERS\r\n// start catch_capture_matchers.h\r\n\r\n// start catch_matchers.h\r\n\r\n#include <string>\r\n#include <vector>\r\n\r\nnamespace Catch {\r\nnamespace Matchers {\r\n    namespace Impl {\r\n\r\n        template<typename ArgT> struct MatchAllOf;\r\n        template<typename ArgT> struct MatchAnyOf;\r\n        template<typename ArgT> struct MatchNotOf;\r\n\r\n        class MatcherUntypedBase {\r\n        public:\r\n            MatcherUntypedBase() = default;\r\n            MatcherUntypedBase ( MatcherUntypedBase const& ) = default;\r\n            MatcherUntypedBase& operator = ( MatcherUntypedBase const& ) = delete;\r\n            std::string toString() const;\r\n\r\n        protected:\r\n            virtual ~MatcherUntypedBase();\r\n            virtual std::string describe() const = 0;\r\n            mutable std::string m_cachedToString;\r\n        };\r\n\r\n#ifdef __clang__\r\n#    pragma clang diagnostic push\r\n#    pragma clang diagnostic ignored \"-Wnon-virtual-dtor\"\r\n#endif\r\n\r\n        template<typename ObjectT>\r\n        struct MatcherMethod {\r\n            virtual bool match( ObjectT const& arg ) const = 0;\r\n        };\r\n\r\n#ifdef __clang__\r\n#    pragma clang diagnostic pop\r\n#endif\r\n\r\n        template<typename T>\r\n        struct MatcherBase : MatcherUntypedBase, MatcherMethod<T> {\r\n\r\n            MatchAllOf<T> operator && ( MatcherBase const& other ) const;\r\n            MatchAnyOf<T> operator || ( MatcherBase const& other ) const;\r\n            MatchNotOf<T> operator ! () const;\r\n        };\r\n\r\n        template<typename ArgT>\r\n        struct MatchAllOf : MatcherBase<ArgT> {\r\n            bool match( ArgT const& arg ) const override {\r\n                for( auto matcher : m_matchers ) {\r\n                    if (!matcher->match(arg))\r\n                        return false;\r\n                }\r\n                return true;\r\n            }\r\n            std::string describe() const override {\r\n                std::string description;\r\n                description.reserve( 4 + m_matchers.size()*32 );\r\n                description += \"( \";\r\n                bool first = true;\r\n                for( auto matcher : m_matchers ) {\r\n                    if( first )\r\n                        first = false;\r\n                    else\r\n                        description += \" and \";\r\n                    description += matcher->toString();\r\n                }\r\n                description += \" )\";\r\n                return description;\r\n            }\r\n\r\n            MatchAllOf<ArgT>& operator && ( MatcherBase<ArgT> const& other ) {\r\n                m_matchers.push_back( &other );\r\n                return *this;\r\n            }\r\n\r\n            std::vector<MatcherBase<ArgT> const*> m_matchers;\r\n        };\r\n        template<typename ArgT>\r\n        struct MatchAnyOf : MatcherBase<ArgT> {\r\n\r\n            bool match( ArgT const& arg ) const override {\r\n                for( auto matcher : m_matchers ) {\r\n                    if (matcher->match(arg))\r\n                        return true;\r\n                }\r\n                return false;\r\n            }\r\n            std::string describe() const override {\r\n                std::string description;\r\n                description.reserve( 4 + m_matchers.size()*32 );\r\n                description += \"( \";\r\n                bool first = true;\r\n                for( auto matcher : m_matchers ) {\r\n                    if( first )\r\n                        first = false;\r\n                    else\r\n                        description += \" or \";\r\n                    description += matcher->toString();\r\n                }\r\n                description += \" )\";\r\n                return description;\r\n            }\r\n\r\n            MatchAnyOf<ArgT>& operator || ( MatcherBase<ArgT> const& other ) {\r\n                m_matchers.push_back( &other );\r\n                return *this;\r\n            }\r\n\r\n            std::vector<MatcherBase<ArgT> const*> m_matchers;\r\n        };\r\n\r\n        template<typename ArgT>\r\n        struct MatchNotOf : MatcherBase<ArgT> {\r\n\r\n            MatchNotOf( MatcherBase<ArgT> const& underlyingMatcher ) : m_underlyingMatcher( underlyingMatcher ) {}\r\n\r\n            bool match( ArgT const& arg ) const override {\r\n                return !m_underlyingMatcher.match( arg );\r\n            }\r\n\r\n            std::string describe() const override {\r\n                return \"not \" + m_underlyingMatcher.toString();\r\n            }\r\n            MatcherBase<ArgT> const& m_underlyingMatcher;\r\n        };\r\n\r\n        template<typename T>\r\n        MatchAllOf<T> MatcherBase<T>::operator && ( MatcherBase const& other ) const {\r\n            return MatchAllOf<T>() && *this && other;\r\n        }\r\n        template<typename T>\r\n        MatchAnyOf<T> MatcherBase<T>::operator || ( MatcherBase const& other ) const {\r\n            return MatchAnyOf<T>() || *this || other;\r\n        }\r\n        template<typename T>\r\n        MatchNotOf<T> MatcherBase<T>::operator ! () const {\r\n            return MatchNotOf<T>( *this );\r\n        }\r\n\r\n    } // namespace Impl\r\n\r\n} // namespace Matchers\r\n\r\nusing namespace Matchers;\r\nusing Matchers::Impl::MatcherBase;\r\n\r\n} // namespace Catch\r\n\r\n// end catch_matchers.h\r\n// start catch_matchers_floating.h\r\n\r\n#include <type_traits>\r\n#include <cmath>\r\n\r\nnamespace Catch {\r\nnamespace Matchers {\r\n\r\n    namespace Floating {\r\n\r\n        enum class FloatingPointKind : uint8_t;\r\n\r\n        struct WithinAbsMatcher : MatcherBase<double> {\r\n            WithinAbsMatcher(double target, double margin);\r\n            bool match(double const& matchee) const override;\r\n            std::string describe() const override;\r\n        private:\r\n            double m_target;\r\n            double m_margin;\r\n        };\r\n\r\n        struct WithinUlpsMatcher : MatcherBase<double> {\r\n            WithinUlpsMatcher(double target, int ulps, FloatingPointKind baseType);\r\n            bool match(double const& matchee) const override;\r\n            std::string describe() const override;\r\n        private:\r\n            double m_target;\r\n            int m_ulps;\r\n            FloatingPointKind m_type;\r\n        };\r\n\r\n    } // namespace Floating\r\n\r\n    // The following functions create the actual matcher objects.\r\n    // This allows the types to be inferred\r\n    Floating::WithinUlpsMatcher WithinULP(double target, int maxUlpDiff);\r\n    Floating::WithinUlpsMatcher WithinULP(float target, int maxUlpDiff);\r\n    Floating::WithinAbsMatcher WithinAbs(double target, double margin);\r\n\r\n} // namespace Matchers\r\n} // namespace Catch\r\n\r\n// end catch_matchers_floating.h\r\n// start catch_matchers_generic.hpp\r\n\r\n#include <functional>\r\n#include <string>\r\n\r\nnamespace Catch {\r\nnamespace Matchers {\r\nnamespace Generic {\r\n\r\nnamespace Detail {\r\n    std::string finalizeDescription(const std::string& desc);\r\n}\r\n\r\ntemplate <typename T>\r\nclass PredicateMatcher : public MatcherBase<T> {\r\n    std::function<bool(T const&)> m_predicate;\r\n    std::string m_description;\r\npublic:\r\n\r\n    PredicateMatcher(std::function<bool(T const&)> const& elem, std::string const& descr)\r\n        :m_predicate(std::move(elem)),\r\n        m_description(Detail::finalizeDescription(descr))\r\n    {}\r\n\r\n    bool match( T const& item ) const override {\r\n        return m_predicate(item);\r\n    }\r\n\r\n    std::string describe() const override {\r\n        return m_description;\r\n    }\r\n};\r\n\r\n} // namespace Generic\r\n\r\n    // The following functions create the actual matcher objects.\r\n    // The user has to explicitly specify type to the function, because\r\n    // infering std::function<bool(T const&)> is hard (but possible) and\r\n    // requires a lot of TMP.\r\n    template<typename T>\r\n    Generic::PredicateMatcher<T> Predicate(std::function<bool(T const&)> const& predicate, std::string const& description = \"\") {\r\n        return Generic::PredicateMatcher<T>(predicate, description);\r\n    }\r\n\r\n} // namespace Matchers\r\n} // namespace Catch\r\n\r\n// end catch_matchers_generic.hpp\r\n// start catch_matchers_string.h\r\n\r\n#include <string>\r\n\r\nnamespace Catch {\r\nnamespace Matchers {\r\n\r\n    namespace StdString {\r\n\r\n        struct CasedString\r\n        {\r\n            CasedString( std::string const& str, CaseSensitive::Choice caseSensitivity );\r\n            std::string adjustString( std::string const& str ) const;\r\n            std::string caseSensitivitySuffix() const;\r\n\r\n            CaseSensitive::Choice m_caseSensitivity;\r\n            std::string m_str;\r\n        };\r\n\r\n        struct StringMatcherBase : MatcherBase<std::string> {\r\n            StringMatcherBase( std::string const& operation, CasedString const& comparator );\r\n            std::string describe() const override;\r\n\r\n            CasedString m_comparator;\r\n            std::string m_operation;\r\n        };\r\n\r\n        struct EqualsMatcher : StringMatcherBase {\r\n            EqualsMatcher( CasedString const& comparator );\r\n            bool match( std::string const& source ) const override;\r\n        };\r\n        struct ContainsMatcher : StringMatcherBase {\r\n            ContainsMatcher( CasedString const& comparator );\r\n            bool match( std::string const& source ) const override;\r\n        };\r\n        struct StartsWithMatcher : StringMatcherBase {\r\n            StartsWithMatcher( CasedString const& comparator );\r\n            bool match( std::string const& source ) const override;\r\n        };\r\n        struct EndsWithMatcher : StringMatcherBase {\r\n            EndsWithMatcher( CasedString const& comparator );\r\n            bool match( std::string const& source ) const override;\r\n        };\r\n\r\n        struct RegexMatcher : MatcherBase<std::string> {\r\n            RegexMatcher( std::string regex, CaseSensitive::Choice caseSensitivity );\r\n            bool match( std::string const& matchee ) const override;\r\n            std::string describe() const override;\r\n\r\n        private:\r\n            std::string m_regex;\r\n            CaseSensitive::Choice m_caseSensitivity;\r\n        };\r\n\r\n    } // namespace StdString\r\n\r\n    // The following functions create the actual matcher objects.\r\n    // This allows the types to be inferred\r\n\r\n    StdString::EqualsMatcher Equals( std::string const& str, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes );\r\n    StdString::ContainsMatcher Contains( std::string const& str, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes );\r\n    StdString::EndsWithMatcher EndsWith( std::string const& str, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes );\r\n    StdString::StartsWithMatcher StartsWith( std::string const& str, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes );\r\n    StdString::RegexMatcher Matches( std::string const& regex, CaseSensitive::Choice caseSensitivity = CaseSensitive::Yes );\r\n\r\n} // namespace Matchers\r\n} // namespace Catch\r\n\r\n// end catch_matchers_string.h\r\n// start catch_matchers_vector.h\r\n\r\n#include <algorithm>\r\n\r\nnamespace Catch {\r\nnamespace Matchers {\r\n\r\n    namespace Vector {\r\n        namespace Detail {\r\n            template <typename InputIterator, typename T>\r\n            size_t count(InputIterator first, InputIterator last, T const& item) {\r\n                size_t cnt = 0;\r\n                for (; first != last; ++first) {\r\n                    if (*first == item) {\r\n                        ++cnt;\r\n                    }\r\n                }\r\n                return cnt;\r\n            }\r\n            template <typename InputIterator, typename T>\r\n            bool contains(InputIterator first, InputIterator last, T const& item) {\r\n                for (; first != last; ++first) {\r\n                    if (*first == item) {\r\n                        return true;\r\n                    }\r\n                }\r\n                return false;\r\n            }\r\n        }\r\n\r\n        template<typename T>\r\n        struct ContainsElementMatcher : MatcherBase<std::vector<T>> {\r\n\r\n            ContainsElementMatcher(T const &comparator) : m_comparator( comparator) {}\r\n\r\n            bool match(std::vector<T> const &v) const override {\r\n                for (auto const& el : v) {\r\n                    if (el == m_comparator) {\r\n                        return true;\r\n                    }\r\n                }\r\n                return false;\r\n            }\r\n\r\n            std::string describe() const override {\r\n                return \"Contains: \" + ::Catch::Detail::stringify( m_comparator );\r\n            }\r\n\r\n            T const& m_comparator;\r\n        };\r\n\r\n        template<typename T>\r\n        struct ContainsMatcher : MatcherBase<std::vector<T>> {\r\n\r\n            ContainsMatcher(std::vector<T> const &comparator) : m_comparator( comparator ) {}\r\n\r\n            bool match(std::vector<T> const &v) const override {\r\n                // !TBD: see note in EqualsMatcher\r\n                if (m_comparator.size() > v.size())\r\n                    return false;\r\n                for (auto const& comparator : m_comparator) {\r\n                    auto present = false;\r\n                    for (const auto& el : v) {\r\n                        if (el == comparator) {\r\n                            present = true;\r\n                            break;\r\n                        }\r\n                    }\r\n                    if (!present) {\r\n                        return false;\r\n                    }\r\n                }\r\n                return true;\r\n            }\r\n            std::string describe() const override {\r\n                return \"Contains: \" + ::Catch::Detail::stringify( m_comparator );\r\n            }\r\n\r\n            std::vector<T> const& m_comparator;\r\n        };\r\n\r\n        template<typename T>\r\n        struct EqualsMatcher : MatcherBase<std::vector<T>> {\r\n\r\n            EqualsMatcher(std::vector<T> const &comparator) : m_comparator( comparator ) {}\r\n\r\n            bool match(std::vector<T> const &v) const override {\r\n                // !TBD: This currently works if all elements can be compared using !=\r\n                // - a more general approach would be via a compare template that defaults\r\n                // to using !=. but could be specialised for, e.g. std::vector<T> etc\r\n                // - then just call that directly\r\n                if (m_comparator.size() != v.size())\r\n                    return false;\r\n                for (std::size_t i = 0; i < v.size(); ++i)\r\n                    if (m_comparator[i] != v[i])\r\n                        return false;\r\n                return true;\r\n            }\r\n            std::string describe() const override {\r\n                return \"Equals: \" + ::Catch::Detail::stringify( m_comparator );\r\n            }\r\n            std::vector<T> const& m_comparator;\r\n        };\r\n\r\n        template<typename T>\r\n        struct UnorderedEqualsMatcher : MatcherBase<std::vector<T>> {\r\n            UnorderedEqualsMatcher(std::vector<T> const& target) : m_target(target) {}\r\n            bool match(std::vector<T> const& vec) const override {\r\n                // Note: This is a reimplementation of std::is_permutation,\r\n                //       because I don't want to include <algorithm> inside the common path\r\n                if (m_target.size() != vec.size()) {\r\n                    return false;\r\n                }\r\n                auto lfirst = m_target.begin(), llast = m_target.end();\r\n                auto rfirst = vec.begin(), rlast = vec.end();\r\n                // Cut common prefix to optimize checking of permuted parts\r\n                while (lfirst != llast && *lfirst == *rfirst) {\r\n                    ++lfirst; ++rfirst;\r\n                }\r\n                if (lfirst == llast) {\r\n                    return true;\r\n                }\r\n\r\n                for (auto mid = lfirst; mid != llast; ++mid) {\r\n                    // Skip already counted items\r\n                    if (Detail::contains(lfirst, mid, *mid)) {\r\n                        continue;\r\n                    }\r\n                    size_t num_vec = Detail::count(rfirst, rlast, *mid);\r\n                    if (num_vec == 0 || Detail::count(lfirst, llast, *mid) != num_vec) {\r\n                        return false;\r\n                    }\r\n                }\r\n\r\n                return true;\r\n            }\r\n\r\n            std::string describe() const override {\r\n                return \"UnorderedEquals: \" + ::Catch::Detail::stringify(m_target);\r\n            }\r\n        private:\r\n            std::vector<T> const& m_target;\r\n        };\r\n\r\n    } // namespace Vector\r\n\r\n    // The following functions create the actual matcher objects.\r\n    // This allows the types to be inferred\r\n\r\n    template<typename T>\r\n    Vector::ContainsMatcher<T> Contains( std::vector<T> const& comparator ) {\r\n        return Vector::ContainsMatcher<T>( comparator );\r\n    }\r\n\r\n    template<typename T>\r\n    Vector::ContainsElementMatcher<T> VectorContains( T const& comparator ) {\r\n        return Vector::ContainsElementMatcher<T>( comparator );\r\n    }\r\n\r\n    template<typename T>\r\n    Vector::EqualsMatcher<T> Equals( std::vector<T> const& comparator ) {\r\n        return Vector::EqualsMatcher<T>( comparator );\r\n    }\r\n\r\n    template<typename T>\r\n    Vector::UnorderedEqualsMatcher<T> UnorderedEquals(std::vector<T> const& target) {\r\n        return Vector::UnorderedEqualsMatcher<T>(target);\r\n    }\r\n\r\n} // namespace Matchers\r\n} // namespace Catch\r\n\r\n// end catch_matchers_vector.h\r\nnamespace Catch {\r\n\r\n    template<typename ArgT, typename MatcherT>\r\n    class MatchExpr : public ITransientExpression {\r\n        ArgT const& m_arg;\r\n        MatcherT m_matcher;\r\n        StringRef m_matcherString;\r\n    public:\r\n        MatchExpr( ArgT const& arg, MatcherT const& matcher, StringRef const& matcherString )\r\n        :   ITransientExpression{ true, matcher.match( arg ) },\r\n            m_arg( arg ),\r\n            m_matcher( matcher ),\r\n            m_matcherString( matcherString )\r\n        {}\r\n\r\n        void streamReconstructedExpression( std::ostream &os ) const override {\r\n            auto matcherAsString = m_matcher.toString();\r\n            os << Catch::Detail::stringify( m_arg ) << ' ';\r\n            if( matcherAsString == Detail::unprintableString )\r\n                os << m_matcherString;\r\n            else\r\n                os << matcherAsString;\r\n        }\r\n    };\r\n\r\n    using StringMatcher = Matchers::Impl::MatcherBase<std::string>;\r\n\r\n    void handleExceptionMatchExpr( AssertionHandler& handler, StringMatcher const& matcher, StringRef const& matcherString  );\r\n\r\n    template<typename ArgT, typename MatcherT>\r\n    auto makeMatchExpr( ArgT const& arg, MatcherT const& matcher, StringRef const& matcherString  ) -> MatchExpr<ArgT, MatcherT> {\r\n        return MatchExpr<ArgT, MatcherT>( arg, matcher, matcherString );\r\n    }\r\n\r\n} // namespace Catch\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CHECK_THAT( macroName, matcher, resultDisposition, arg ) \\\r\n    do { \\\r\n        Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(arg) \", \" CATCH_INTERNAL_STRINGIFY(matcher), resultDisposition ); \\\r\n        INTERNAL_CATCH_TRY { \\\r\n            catchAssertionHandler.handleExpr( Catch::makeMatchExpr( arg, matcher, #matcher##_catch_sr ) ); \\\r\n        } INTERNAL_CATCH_CATCH( catchAssertionHandler ) \\\r\n        INTERNAL_CATCH_REACT( catchAssertionHandler ) \\\r\n    } while( false )\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define INTERNAL_CATCH_THROWS_MATCHES( macroName, exceptionType, resultDisposition, matcher, ... ) \\\r\n    do { \\\r\n        Catch::AssertionHandler catchAssertionHandler( macroName##_catch_sr, CATCH_INTERNAL_LINEINFO, CATCH_INTERNAL_STRINGIFY(__VA_ARGS__) \", \" CATCH_INTERNAL_STRINGIFY(exceptionType) \", \" CATCH_INTERNAL_STRINGIFY(matcher), resultDisposition ); \\\r\n        if( catchAssertionHandler.allowThrows() ) \\\r\n            try { \\\r\n                static_cast<void>(__VA_ARGS__ ); \\\r\n                catchAssertionHandler.handleUnexpectedExceptionNotThrown(); \\\r\n            } \\\r\n            catch( exceptionType const& ex ) { \\\r\n                catchAssertionHandler.handleExpr( Catch::makeMatchExpr( ex, matcher, #matcher##_catch_sr ) ); \\\r\n            } \\\r\n            catch( ... ) { \\\r\n                catchAssertionHandler.handleUnexpectedInflightException(); \\\r\n            } \\\r\n        else \\\r\n            catchAssertionHandler.handleThrowingCallSkipped(); \\\r\n        INTERNAL_CATCH_REACT( catchAssertionHandler ) \\\r\n    } while( false )\r\n\r\n// end catch_capture_matchers.h\r\n#endif\r\n// start catch_generators.hpp\r\n\r\n// start catch_interfaces_generatortracker.h\r\n\r\n\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    namespace Generators {\r\n        class GeneratorUntypedBase {\r\n        public:\r\n            GeneratorUntypedBase() = default;\r\n            virtual ~GeneratorUntypedBase();\r\n            // Attempts to move the generator to the next element\r\n             //\r\n             // Returns true iff the move succeeded (and a valid element\r\n             // can be retrieved).\r\n            virtual bool next() = 0;\r\n        };\r\n        using GeneratorBasePtr = std::unique_ptr<GeneratorUntypedBase>;\r\n\r\n    } // namespace Generators\r\n\r\n    struct IGeneratorTracker {\r\n        virtual ~IGeneratorTracker();\r\n        virtual auto hasGenerator() const -> bool = 0;\r\n        virtual auto getGenerator() const -> Generators::GeneratorBasePtr const& = 0;\r\n        virtual void setGenerator( Generators::GeneratorBasePtr&& generator ) = 0;\r\n    };\r\n\r\n} // namespace Catch\r\n\r\n// end catch_interfaces_generatortracker.h\r\n// start catch_enforce.h\r\n\r\n#include <stdexcept>\r\n\r\nnamespace Catch {\r\n#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS)\r\n    template <typename Ex>\r\n    [[noreturn]]\r\n    void throw_exception(Ex const& e) {\r\n        throw e;\r\n    }\r\n#else // ^^ Exceptions are enabled //  Exceptions are disabled vv\r\n    [[noreturn]]\r\n    void throw_exception(std::exception const& e);\r\n#endif\r\n} // namespace Catch;\r\n\r\n#define CATCH_PREPARE_EXCEPTION( type, msg ) \\\r\n    type( ( Catch::ReusableStringStream() << msg ).str() )\r\n#define CATCH_INTERNAL_ERROR( msg ) \\\r\n    Catch::throw_exception(CATCH_PREPARE_EXCEPTION( std::logic_error, CATCH_INTERNAL_LINEINFO << \": Internal Catch error: \" << msg))\r\n#define CATCH_ERROR( msg ) \\\r\n    Catch::throw_exception(CATCH_PREPARE_EXCEPTION( std::domain_error, msg ))\r\n#define CATCH_RUNTIME_ERROR( msg ) \\\r\n    Catch::throw_exception(CATCH_PREPARE_EXCEPTION( std::runtime_error, msg ))\r\n#define CATCH_ENFORCE( condition, msg ) \\\r\n    do{ if( !(condition) ) CATCH_ERROR( msg ); } while(false)\r\n\r\n// end catch_enforce.h\r\n#include <memory>\r\n#include <vector>\r\n#include <cassert>\r\n\r\n#include <utility>\r\n#include <exception>\r\n\r\nnamespace Catch {\r\n\r\nclass GeneratorException : public std::exception {\r\n    const char* const m_msg = \"\";\r\n\r\npublic:\r\n    GeneratorException(const char* msg):\r\n        m_msg(msg)\r\n    {}\r\n\r\n    const char* what() const noexcept override final;\r\n};\r\n\r\nnamespace Generators {\r\n\r\n    // !TBD move this into its own location?\r\n    namespace pf{\r\n        template<typename T, typename... Args>\r\n        std::unique_ptr<T> make_unique( Args&&... args ) {\r\n            return std::unique_ptr<T>(new T(std::forward<Args>(args)...));\r\n        }\r\n    }\r\n\r\n    template<typename T>\r\n    struct IGenerator : GeneratorUntypedBase {\r\n        virtual ~IGenerator() = default;\r\n\r\n        // Returns the current element of the generator\r\n        //\r\n        // \\Precondition The generator is either freshly constructed,\r\n        // or the last call to `next()` returned true\r\n        virtual T const& get() const = 0;\r\n        using type = T;\r\n    };\r\n\r\n    template<typename T>\r\n    class SingleValueGenerator final : public IGenerator<T> {\r\n        T m_value;\r\n    public:\r\n        SingleValueGenerator(T const& value) : m_value( value ) {}\r\n        SingleValueGenerator(T&& value) : m_value(std::move(value)) {}\r\n\r\n        T const& get() const override {\r\n            return m_value;\r\n        }\r\n        bool next() override {\r\n            return false;\r\n        }\r\n    };\r\n\r\n    template<typename T>\r\n    class FixedValuesGenerator final : public IGenerator<T> {\r\n        std::vector<T> m_values;\r\n        size_t m_idx = 0;\r\n    public:\r\n        FixedValuesGenerator( std::initializer_list<T> values ) : m_values( values ) {}\r\n\r\n        T const& get() const override {\r\n            return m_values[m_idx];\r\n        }\r\n        bool next() override {\r\n            ++m_idx;\r\n            return m_idx < m_values.size();\r\n        }\r\n    };\r\n\r\n    template <typename T>\r\n    class GeneratorWrapper final {\r\n        std::unique_ptr<IGenerator<T>> m_generator;\r\n    public:\r\n        GeneratorWrapper(std::unique_ptr<IGenerator<T>> generator):\r\n            m_generator(std::move(generator))\r\n        {}\r\n        T const& get() const {\r\n            return m_generator->get();\r\n        }\r\n        bool next() {\r\n            return m_generator->next();\r\n        }\r\n    };\r\n\r\n    template <typename T>\r\n    GeneratorWrapper<T> value(T&& value) {\r\n        return GeneratorWrapper<T>(pf::make_unique<SingleValueGenerator<T>>(std::forward<T>(value)));\r\n    }\r\n    template <typename T>\r\n    GeneratorWrapper<T> values(std::initializer_list<T> values) {\r\n        return GeneratorWrapper<T>(pf::make_unique<FixedValuesGenerator<T>>(values));\r\n    }\r\n\r\n    template<typename T>\r\n    class Generators : public IGenerator<T> {\r\n        std::vector<GeneratorWrapper<T>> m_generators;\r\n        size_t m_current = 0;\r\n\r\n        void populate(GeneratorWrapper<T>&& generator) {\r\n            m_generators.emplace_back(std::move(generator));\r\n        }\r\n        void populate(T&& val) {\r\n            m_generators.emplace_back(value(std::move(val)));\r\n        }\r\n        template<typename U>\r\n        void populate(U&& val) {\r\n            populate(T(std::move(val)));\r\n        }\r\n        template<typename U, typename... Gs>\r\n        void populate(U&& valueOrGenerator, Gs... moreGenerators) {\r\n            populate(std::forward<U>(valueOrGenerator));\r\n            populate(std::forward<Gs>(moreGenerators)...);\r\n        }\r\n\r\n    public:\r\n        template <typename... Gs>\r\n        Generators(Gs... moreGenerators) {\r\n            m_generators.reserve(sizeof...(Gs));\r\n            populate(std::forward<Gs>(moreGenerators)...);\r\n        }\r\n\r\n        T const& get() const override {\r\n            return m_generators[m_current].get();\r\n        }\r\n\r\n        bool next() override {\r\n            if (m_current >= m_generators.size()) {\r\n                return false;\r\n            }\r\n            const bool current_status = m_generators[m_current].next();\r\n            if (!current_status) {\r\n                ++m_current;\r\n            }\r\n            return m_current < m_generators.size();\r\n        }\r\n    };\r\n\r\n    template<typename... Ts>\r\n    GeneratorWrapper<std::tuple<Ts...>> table( std::initializer_list<std::tuple<typename std::decay<Ts>::type...>> tuples ) {\r\n        return values<std::tuple<Ts...>>( tuples );\r\n    }\r\n\r\n    // Tag type to signal that a generator sequence should convert arguments to a specific type\r\n    template <typename T>\r\n    struct as {};\r\n\r\n    template<typename T, typename... Gs>\r\n    auto makeGenerators( GeneratorWrapper<T>&& generator, Gs... moreGenerators ) -> Generators<T> {\r\n        return Generators<T>(std::move(generator), std::forward<Gs>(moreGenerators)...);\r\n    }\r\n    template<typename T>\r\n    auto makeGenerators( GeneratorWrapper<T>&& generator ) -> Generators<T> {\r\n        return Generators<T>(std::move(generator));\r\n    }\r\n    template<typename T, typename... Gs>\r\n    auto makeGenerators( T&& val, Gs... moreGenerators ) -> Generators<T> {\r\n        return makeGenerators( value( std::forward<T>( val ) ), std::forward<Gs>( moreGenerators )... );\r\n    }\r\n    template<typename T, typename U, typename... Gs>\r\n    auto makeGenerators( as<T>, U&& val, Gs... moreGenerators ) -> Generators<T> {\r\n        return makeGenerators( value( T( std::forward<U>( val ) ) ), std::forward<Gs>( moreGenerators )... );\r\n    }\r\n\r\n    auto acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker&;\r\n\r\n    template<typename L>\r\n    // Note: The type after -> is weird, because VS2015 cannot parse\r\n    //       the expression used in the typedef inside, when it is in\r\n    //       return type. Yeah.\r\n    auto generate( SourceLineInfo const& lineInfo, L const& generatorExpression ) -> decltype(std::declval<decltype(generatorExpression())>().get()) {\r\n        using UnderlyingType = typename decltype(generatorExpression())::type;\r\n\r\n        IGeneratorTracker& tracker = acquireGeneratorTracker( lineInfo );\r\n        if (!tracker.hasGenerator()) {\r\n            tracker.setGenerator(pf::make_unique<Generators<UnderlyingType>>(generatorExpression()));\r\n        }\r\n\r\n        auto const& generator = static_cast<IGenerator<UnderlyingType> const&>( *tracker.getGenerator() );\r\n        return generator.get();\r\n    }\r\n\r\n} // namespace Generators\r\n} // namespace Catch\r\n\r\n#define GENERATE( ... ) \\\r\n    Catch::Generators::generate( CATCH_INTERNAL_LINEINFO, []{ using namespace Catch::Generators; return makeGenerators( __VA_ARGS__ ); } )\r\n\r\n// end catch_generators.hpp\r\n// start catch_generators_generic.hpp\r\n\r\nnamespace Catch {\r\nnamespace Generators {\r\n\r\n    template <typename T>\r\n    class TakeGenerator : public IGenerator<T> {\r\n        GeneratorWrapper<T> m_generator;\r\n        size_t m_returned = 0;\r\n        size_t m_target;\r\n    public:\r\n        TakeGenerator(size_t target, GeneratorWrapper<T>&& generator):\r\n            m_generator(std::move(generator)),\r\n            m_target(target)\r\n        {\r\n            assert(target != 0 && \"Empty generators are not allowed\");\r\n        }\r\n        T const& get() const override {\r\n            return m_generator.get();\r\n        }\r\n        bool next() override {\r\n            ++m_returned;\r\n            if (m_returned >= m_target) {\r\n                return false;\r\n            }\r\n\r\n            const auto success = m_generator.next();\r\n            // If the underlying generator does not contain enough values\r\n            // then we cut short as well\r\n            if (!success) {\r\n                m_returned = m_target;\r\n            }\r\n            return success;\r\n        }\r\n    };\r\n\r\n    template <typename T>\r\n    GeneratorWrapper<T> take(size_t target, GeneratorWrapper<T>&& generator) {\r\n        return GeneratorWrapper<T>(pf::make_unique<TakeGenerator<T>>(target, std::move(generator)));\r\n    }\r\n\r\n    template <typename T, typename Predicate>\r\n    class FilterGenerator : public IGenerator<T> {\r\n        GeneratorWrapper<T> m_generator;\r\n        Predicate m_predicate;\r\n    public:\r\n        template <typename P = Predicate>\r\n        FilterGenerator(P&& pred, GeneratorWrapper<T>&& generator):\r\n            m_generator(std::move(generator)),\r\n            m_predicate(std::forward<P>(pred))\r\n        {\r\n            if (!m_predicate(m_generator.get())) {\r\n                // It might happen that there are no values that pass the\r\n                // filter. In that case we throw an exception.\r\n                auto has_initial_value = next();\r\n                if (!has_initial_value) {\r\n                    Catch::throw_exception(GeneratorException(\"No valid value found in filtered generator\"));\r\n                }\r\n            }\r\n        }\r\n\r\n        T const& get() const override {\r\n            return m_generator.get();\r\n        }\r\n\r\n        bool next() override {\r\n            bool success = m_generator.next();\r\n            if (!success) {\r\n                return false;\r\n            }\r\n            while (!m_predicate(m_generator.get()) && (success = m_generator.next()) == true);\r\n            return success;\r\n        }\r\n    };\r\n\r\n    template <typename T, typename Predicate>\r\n    GeneratorWrapper<T> filter(Predicate&& pred, GeneratorWrapper<T>&& generator) {\r\n        return GeneratorWrapper<T>(std::unique_ptr<IGenerator<T>>(pf::make_unique<FilterGenerator<T, Predicate>>(std::forward<Predicate>(pred), std::move(generator))));\r\n    }\r\n\r\n    template <typename T>\r\n    class RepeatGenerator : public IGenerator<T> {\r\n        GeneratorWrapper<T> m_generator;\r\n        mutable std::vector<T> m_returned;\r\n        size_t m_target_repeats;\r\n        size_t m_current_repeat = 0;\r\n        size_t m_repeat_index = 0;\r\n    public:\r\n        RepeatGenerator(size_t repeats, GeneratorWrapper<T>&& generator):\r\n            m_generator(std::move(generator)),\r\n            m_target_repeats(repeats)\r\n        {\r\n            assert(m_target_repeats > 0 && \"Repeat generator must repeat at least once\");\r\n        }\r\n\r\n        T const& get() const override {\r\n            if (m_current_repeat == 0) {\r\n                m_returned.push_back(m_generator.get());\r\n                return m_returned.back();\r\n            }\r\n            return m_returned[m_repeat_index];\r\n        }\r\n\r\n        bool next() override {\r\n            // There are 2 basic cases:\r\n            // 1) We are still reading the generator\r\n            // 2) We are reading our own cache\r\n\r\n            // In the first case, we need to poke the underlying generator.\r\n            // If it happily moves, we are left in that state, otherwise it is time to start reading from our cache\r\n            if (m_current_repeat == 0) {\r\n                const auto success = m_generator.next();\r\n                if (!success) {\r\n                    ++m_current_repeat;\r\n                }\r\n                return m_current_repeat < m_target_repeats;\r\n            }\r\n\r\n            // In the second case, we need to move indices forward and check that we haven't run up against the end\r\n            ++m_repeat_index;\r\n            if (m_repeat_index == m_returned.size()) {\r\n                m_repeat_index = 0;\r\n                ++m_current_repeat;\r\n            }\r\n            return m_current_repeat < m_target_repeats;\r\n        }\r\n    };\r\n\r\n    template <typename T>\r\n    GeneratorWrapper<T> repeat(size_t repeats, GeneratorWrapper<T>&& generator) {\r\n        return GeneratorWrapper<T>(pf::make_unique<RepeatGenerator<T>>(repeats, std::move(generator)));\r\n    }\r\n\r\n    template <typename T, typename U, typename Func>\r\n    class MapGenerator : public IGenerator<T> {\r\n        // TBD: provide static assert for mapping function, for friendly error message\r\n        GeneratorWrapper<U> m_generator;\r\n        Func m_function;\r\n        // To avoid returning dangling reference, we have to save the values\r\n        T m_cache;\r\n    public:\r\n        template <typename F2 = Func>\r\n        MapGenerator(F2&& function, GeneratorWrapper<U>&& generator) :\r\n            m_generator(std::move(generator)),\r\n            m_function(std::forward<F2>(function)),\r\n            m_cache(m_function(m_generator.get()))\r\n        {}\r\n\r\n        T const& get() const override {\r\n            return m_cache;\r\n        }\r\n        bool next() override {\r\n            const auto success = m_generator.next();\r\n            if (success) {\r\n                m_cache = m_function(m_generator.get());\r\n            }\r\n            return success;\r\n        }\r\n    };\r\n\r\n    template <typename T, typename U, typename Func>\r\n    GeneratorWrapper<T> map(Func&& function, GeneratorWrapper<U>&& generator) {\r\n        return GeneratorWrapper<T>(\r\n            pf::make_unique<MapGenerator<T, U, Func>>(std::forward<Func>(function), std::move(generator))\r\n        );\r\n    }\r\n    template <typename T, typename Func>\r\n    GeneratorWrapper<T> map(Func&& function, GeneratorWrapper<T>&& generator) {\r\n        return GeneratorWrapper<T>(\r\n            pf::make_unique<MapGenerator<T, T, Func>>(std::forward<Func>(function), std::move(generator))\r\n        );\r\n    }\r\n\r\n    template <typename T>\r\n    class ChunkGenerator final : public IGenerator<std::vector<T>> {\r\n        std::vector<T> m_chunk;\r\n        size_t m_chunk_size;\r\n        GeneratorWrapper<T> m_generator;\r\n        bool m_used_up = false;\r\n    public:\r\n        ChunkGenerator(size_t size, GeneratorWrapper<T> generator) :\r\n            m_chunk_size(size), m_generator(std::move(generator))\r\n        {\r\n            m_chunk.reserve(m_chunk_size);\r\n            m_chunk.push_back(m_generator.get());\r\n            for (size_t i = 1; i < m_chunk_size; ++i) {\r\n                if (!m_generator.next()) {\r\n                    Catch::throw_exception(GeneratorException(\"Not enough values to initialize the first chunk\"));\r\n                }\r\n                m_chunk.push_back(m_generator.get());\r\n            }\r\n        }\r\n        std::vector<T> const& get() const override {\r\n            return m_chunk;\r\n        }\r\n        bool next() override {\r\n            m_chunk.clear();\r\n            for (size_t idx = 0; idx < m_chunk_size; ++idx) {\r\n                if (!m_generator.next()) {\r\n                    return false;\r\n                }\r\n                m_chunk.push_back(m_generator.get());\r\n            }\r\n            return true;\r\n        }\r\n    };\r\n\r\n    template <typename T>\r\n    GeneratorWrapper<std::vector<T>> chunk(size_t size, GeneratorWrapper<T>&& generator) {\r\n        return GeneratorWrapper<std::vector<T>>(\r\n            pf::make_unique<ChunkGenerator<T>>(size, std::move(generator))\r\n        );\r\n    }\r\n\r\n} // namespace Generators\r\n} // namespace Catch\r\n\r\n// end catch_generators_generic.hpp\r\n// start catch_generators_specific.hpp\r\n\r\n// start catch_context.h\r\n\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    struct IResultCapture;\r\n    struct IRunner;\r\n    struct IConfig;\r\n    struct IMutableContext;\r\n\r\n    using IConfigPtr = std::shared_ptr<IConfig const>;\r\n\r\n    struct IContext\r\n    {\r\n        virtual ~IContext();\r\n\r\n        virtual IResultCapture* getResultCapture() = 0;\r\n        virtual IRunner* getRunner() = 0;\r\n        virtual IConfigPtr const& getConfig() const = 0;\r\n    };\r\n\r\n    struct IMutableContext : IContext\r\n    {\r\n        virtual ~IMutableContext();\r\n        virtual void setResultCapture( IResultCapture* resultCapture ) = 0;\r\n        virtual void setRunner( IRunner* runner ) = 0;\r\n        virtual void setConfig( IConfigPtr const& config ) = 0;\r\n\r\n    private:\r\n        static IMutableContext *currentContext;\r\n        friend IMutableContext& getCurrentMutableContext();\r\n        friend void cleanUpContext();\r\n        static void createContext();\r\n    };\r\n\r\n    inline IMutableContext& getCurrentMutableContext()\r\n    {\r\n        if( !IMutableContext::currentContext )\r\n            IMutableContext::createContext();\r\n        return *IMutableContext::currentContext;\r\n    }\r\n\r\n    inline IContext& getCurrentContext()\r\n    {\r\n        return getCurrentMutableContext();\r\n    }\r\n\r\n    void cleanUpContext();\r\n}\r\n\r\n// end catch_context.h\r\n// start catch_interfaces_config.h\r\n\r\n#include <iosfwd>\r\n#include <string>\r\n#include <vector>\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    enum class Verbosity {\r\n        Quiet = 0,\r\n        Normal,\r\n        High\r\n    };\r\n\r\n    struct WarnAbout { enum What {\r\n        Nothing = 0x00,\r\n        NoAssertions = 0x01,\r\n        NoTests = 0x02\r\n    }; };\r\n\r\n    struct ShowDurations { enum OrNot {\r\n        DefaultForReporter,\r\n        Always,\r\n        Never\r\n    }; };\r\n    struct RunTests { enum InWhatOrder {\r\n        InDeclarationOrder,\r\n        InLexicographicalOrder,\r\n        InRandomOrder\r\n    }; };\r\n    struct UseColour { enum YesOrNo {\r\n        Auto,\r\n        Yes,\r\n        No\r\n    }; };\r\n    struct WaitForKeypress { enum When {\r\n        Never,\r\n        BeforeStart = 1,\r\n        BeforeExit = 2,\r\n        BeforeStartAndExit = BeforeStart | BeforeExit\r\n    }; };\r\n\r\n    class TestSpec;\r\n\r\n    struct IConfig : NonCopyable {\r\n\r\n        virtual ~IConfig();\r\n\r\n        virtual bool allowThrows() const = 0;\r\n        virtual std::ostream& stream() const = 0;\r\n        virtual std::string name() const = 0;\r\n        virtual bool includeSuccessfulResults() const = 0;\r\n        virtual bool shouldDebugBreak() const = 0;\r\n        virtual bool warnAboutMissingAssertions() const = 0;\r\n        virtual bool warnAboutNoTests() const = 0;\r\n        virtual int abortAfter() const = 0;\r\n        virtual bool showInvisibles() const = 0;\r\n        virtual ShowDurations::OrNot showDurations() const = 0;\r\n        virtual TestSpec const& testSpec() const = 0;\r\n        virtual bool hasTestFilters() const = 0;\r\n        virtual RunTests::InWhatOrder runOrder() const = 0;\r\n        virtual unsigned int rngSeed() const = 0;\r\n        virtual int benchmarkResolutionMultiple() const = 0;\r\n        virtual UseColour::YesOrNo useColour() const = 0;\r\n        virtual std::vector<std::string> const& getSectionsToRun() const = 0;\r\n        virtual Verbosity verbosity() const = 0;\r\n    };\r\n\r\n    using IConfigPtr = std::shared_ptr<IConfig const>;\r\n}\r\n\r\n// end catch_interfaces_config.h\r\n#include <random>\r\n\r\nnamespace Catch {\r\nnamespace Generators {\r\n\r\ntemplate <typename Float>\r\nclass RandomFloatingGenerator final : public IGenerator<Float> {\r\n    // FIXME: What is the right seed?\r\n    std::minstd_rand m_rand;\r\n    std::uniform_real_distribution<Float> m_dist;\r\n    Float m_current_number;\r\npublic:\r\n\r\n    RandomFloatingGenerator(Float a, Float b):\r\n        m_rand(getCurrentContext().getConfig()->rngSeed()),\r\n        m_dist(a, b) {\r\n        static_cast<void>(next());\r\n    }\r\n\r\n    Float const& get() const override {\r\n        return m_current_number;\r\n    }\r\n    bool next() override {\r\n        m_current_number = m_dist(m_rand);\r\n        return true;\r\n    }\r\n};\r\n\r\ntemplate <typename Integer>\r\nclass RandomIntegerGenerator final : public IGenerator<Integer> {\r\n    std::minstd_rand m_rand;\r\n    std::uniform_int_distribution<Integer> m_dist;\r\n    Integer m_current_number;\r\npublic:\r\n\r\n    RandomIntegerGenerator(Integer a, Integer b):\r\n        m_rand(getCurrentContext().getConfig()->rngSeed()),\r\n        m_dist(a, b) {\r\n        static_cast<void>(next());\r\n    }\r\n\r\n    Integer const& get() const override {\r\n        return m_current_number;\r\n    }\r\n    bool next() override {\r\n        m_current_number = m_dist(m_rand);\r\n        return true;\r\n    }\r\n};\r\n\r\n// TODO: Ideally this would be also constrained against the various char types,\r\n//       but I don't expect users to run into that in practice.\r\ntemplate <typename T>\r\ntypename std::enable_if<std::is_integral<T>::value && !std::is_same<T, bool>::value,\r\nGeneratorWrapper<T>>::type\r\nrandom(T a, T b) {\r\n    return GeneratorWrapper<T>(\r\n        pf::make_unique<RandomIntegerGenerator<T>>(a, b)\r\n    );\r\n}\r\n\r\ntemplate <typename T>\r\ntypename std::enable_if<std::is_floating_point<T>::value,\r\nGeneratorWrapper<T>>::type\r\nrandom(T a, T b) {\r\n    return GeneratorWrapper<T>(\r\n        pf::make_unique<RandomFloatingGenerator<T>>(a, b)\r\n    );\r\n}\r\n\r\ntemplate <typename T>\r\nclass RangeGenerator final : public IGenerator<T> {\r\n    T m_current;\r\n    T m_end;\r\n    T m_step;\r\n    bool m_positive;\r\n\r\npublic:\r\n    RangeGenerator(T const& start, T const& end, T const& step):\r\n        m_current(start),\r\n        m_end(end),\r\n        m_step(step),\r\n        m_positive(m_step > T(0))\r\n    {\r\n        assert(m_current != m_end && \"Range start and end cannot be equal\");\r\n        assert(m_step != T(0) && \"Step size cannot be zero\");\r\n        assert(((m_positive && m_current <= m_end) || (!m_positive && m_current >= m_end)) && \"Step moves away from end\");\r\n    }\r\n\r\n    RangeGenerator(T const& start, T const& end):\r\n        RangeGenerator(start, end, (start < end) ? T(1) : T(-1))\r\n    {}\r\n\r\n    T const& get() const override {\r\n        return m_current;\r\n    }\r\n\r\n    bool next() override {\r\n        m_current += m_step;\r\n        return (m_positive) ? (m_current < m_end) : (m_current > m_end);\r\n    }\r\n};\r\n\r\ntemplate <typename T>\r\nGeneratorWrapper<T> range(T const& start, T const& end, T const& step) {\r\n    static_assert(std::is_integral<T>::value && !std::is_same<T, bool>::value, \"Type must be an integer\");\r\n    return GeneratorWrapper<T>(pf::make_unique<RangeGenerator<T>>(start, end, step));\r\n}\r\n\r\ntemplate <typename T>\r\nGeneratorWrapper<T> range(T const& start, T const& end) {\r\n    static_assert(std::is_integral<T>::value && !std::is_same<T, bool>::value, \"Type must be an integer\");\r\n    return GeneratorWrapper<T>(pf::make_unique<RangeGenerator<T>>(start, end));\r\n}\r\n\r\n} // namespace Generators\r\n} // namespace Catch\r\n\r\n// end catch_generators_specific.hpp\r\n\r\n// These files are included here so the single_include script doesn't put them\r\n// in the conditionally compiled sections\r\n// start catch_test_case_info.h\r\n\r\n#include <string>\r\n#include <vector>\r\n#include <memory>\r\n\r\n#ifdef __clang__\r\n#pragma clang diagnostic push\r\n#pragma clang diagnostic ignored \"-Wpadded\"\r\n#endif\r\n\r\nnamespace Catch {\r\n\r\n    struct ITestInvoker;\r\n\r\n    struct TestCaseInfo {\r\n        enum SpecialProperties{\r\n            None = 0,\r\n            IsHidden = 1 << 1,\r\n            ShouldFail = 1 << 2,\r\n            MayFail = 1 << 3,\r\n            Throws = 1 << 4,\r\n            NonPortable = 1 << 5,\r\n            Benchmark = 1 << 6\r\n        };\r\n\r\n        TestCaseInfo(   std::string const& _name,\r\n                        std::string const& _className,\r\n                        std::string const& _description,\r\n                        std::vector<std::string> const& _tags,\r\n                        SourceLineInfo const& _lineInfo );\r\n\r\n        friend void setTags( TestCaseInfo& testCaseInfo, std::vector<std::string> tags );\r\n\r\n        bool isHidden() const;\r\n        bool throws() const;\r\n        bool okToFail() const;\r\n        bool expectedToFail() const;\r\n\r\n        std::string tagsAsString() const;\r\n\r\n        std::string name;\r\n        std::string className;\r\n        std::string description;\r\n        std::vector<std::string> tags;\r\n        std::vector<std::string> lcaseTags;\r\n        SourceLineInfo lineInfo;\r\n        SpecialProperties properties;\r\n    };\r\n\r\n    class TestCase : public TestCaseInfo {\r\n    public:\r\n\r\n        TestCase( ITestInvoker* testCase, TestCaseInfo&& info );\r\n\r\n        TestCase withName( std::string const& _newName ) const;\r\n\r\n        void invoke() const;\r\n\r\n        TestCaseInfo const& getTestCaseInfo() const;\r\n\r\n        bool operator == ( TestCase const& other ) const;\r\n        bool operator < ( TestCase const& other ) const;\r\n\r\n    private:\r\n        std::shared_ptr<ITestInvoker> test;\r\n    };\r\n\r\n    TestCase makeTestCase(  ITestInvoker* testCase,\r\n                            std::string const& className,\r\n                            NameAndTags const& nameAndTags,\r\n                            SourceLineInfo const& lineInfo );\r\n}\r\n\r\n#ifdef __clang__\r\n#pragma clang diagnostic pop\r\n#endif\r\n\r\n// end catch_test_case_info.h\r\n// start catch_interfaces_runner.h\r\n\r\nnamespace Catch {\r\n\r\n    struct IRunner {\r\n        virtual ~IRunner();\r\n        virtual bool aborting() const = 0;\r\n    };\r\n}\r\n\r\n// end catch_interfaces_runner.h\r\n\r\n#ifdef __OBJC__\r\n// start catch_objc.hpp\r\n\r\n#import <objc/runtime.h>\r\n\r\n#include <string>\r\n\r\n// NB. Any general catch headers included here must be included\r\n// in catch.hpp first to make sure they are included by the single\r\n// header for non obj-usage\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n// This protocol is really only here for (self) documenting purposes, since\r\n// all its methods are optional.\r\n@protocol OcFixture\r\n\r\n@optional\r\n\r\n-(void) setUp;\r\n-(void) tearDown;\r\n\r\n@end\r\n\r\nnamespace Catch {\r\n\r\n    class OcMethod : public ITestInvoker {\r\n\r\n    public:\r\n        OcMethod( Class cls, SEL sel ) : m_cls( cls ), m_sel( sel ) {}\r\n\r\n        virtual void invoke() const {\r\n            id obj = [[m_cls alloc] init];\r\n\r\n            performOptionalSelector( obj, @selector(setUp)  );\r\n            performOptionalSelector( obj, m_sel );\r\n            performOptionalSelector( obj, @selector(tearDown)  );\r\n\r\n            arcSafeRelease( obj );\r\n        }\r\n    private:\r\n        virtual ~OcMethod() {}\r\n\r\n        Class m_cls;\r\n        SEL m_sel;\r\n    };\r\n\r\n    namespace Detail{\r\n\r\n        inline std::string getAnnotation(   Class cls,\r\n                                            std::string const& annotationName,\r\n                                            std::string const& testCaseName ) {\r\n            NSString* selStr = [[NSString alloc] initWithFormat:@\"Catch_%s_%s\", annotationName.c_str(), testCaseName.c_str()];\r\n            SEL sel = NSSelectorFromString( selStr );\r\n            arcSafeRelease( selStr );\r\n            id value = performOptionalSelector( cls, sel );\r\n            if( value )\r\n                return [(NSString*)value UTF8String];\r\n            return \"\";\r\n        }\r\n    }\r\n\r\n    inline std::size_t registerTestMethods() {\r\n        std::size_t noTestMethods = 0;\r\n        int noClasses = objc_getClassList( nullptr, 0 );\r\n\r\n        Class* classes = (CATCH_UNSAFE_UNRETAINED Class *)malloc( sizeof(Class) * noClasses);\r\n        objc_getClassList( classes, noClasses );\r\n\r\n        for( int c = 0; c < noClasses; c++ ) {\r\n            Class cls = classes[c];\r\n            {\r\n                u_int count;\r\n                Method* methods = class_copyMethodList( cls, &count );\r\n                for( u_int m = 0; m < count ; m++ ) {\r\n                    SEL selector = method_getName(methods[m]);\r\n                    std::string methodName = sel_getName(selector);\r\n                    if( startsWith( methodName, \"Catch_TestCase_\" ) ) {\r\n                        std::string testCaseName = methodName.substr( 15 );\r\n                        std::string name = Detail::getAnnotation( cls, \"Name\", testCaseName );\r\n                        std::string desc = Detail::getAnnotation( cls, \"Description\", testCaseName );\r\n                        const char* className = class_getName( cls );\r\n\r\n                        getMutableRegistryHub().registerTest( makeTestCase( new OcMethod( cls, selector ), className, NameAndTags( name.c_str(), desc.c_str() ), SourceLineInfo(\"\",0) ) );\r\n                        noTestMethods++;\r\n                    }\r\n                }\r\n                free(methods);\r\n            }\r\n        }\r\n        return noTestMethods;\r\n    }\r\n\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n\r\n    namespace Matchers {\r\n        namespace Impl {\r\n        namespace NSStringMatchers {\r\n\r\n            struct StringHolder : MatcherBase<NSString*>{\r\n                StringHolder( NSString* substr ) : m_substr( [substr copy] ){}\r\n                StringHolder( StringHolder const& other ) : m_substr( [other.m_substr copy] ){}\r\n                StringHolder() {\r\n                    arcSafeRelease( m_substr );\r\n                }\r\n\r\n                bool match( NSString* arg ) const override {\r\n                    return false;\r\n                }\r\n\r\n                NSString* CATCH_ARC_STRONG m_substr;\r\n            };\r\n\r\n            struct Equals : StringHolder {\r\n                Equals( NSString* substr ) : StringHolder( substr ){}\r\n\r\n                bool match( NSString* str ) const override {\r\n                    return  (str != nil || m_substr == nil ) &&\r\n                            [str isEqualToString:m_substr];\r\n                }\r\n\r\n                std::string describe() const override {\r\n                    return \"equals string: \" + Catch::Detail::stringify( m_substr );\r\n                }\r\n            };\r\n\r\n            struct Contains : StringHolder {\r\n                Contains( NSString* substr ) : StringHolder( substr ){}\r\n\r\n                bool match( NSString* str ) const {\r\n                    return  (str != nil || m_substr == nil ) &&\r\n                            [str rangeOfString:m_substr].location != NSNotFound;\r\n                }\r\n\r\n                std::string describe() const override {\r\n                    return \"contains string: \" + Catch::Detail::stringify( m_substr );\r\n                }\r\n            };\r\n\r\n            struct StartsWith : StringHolder {\r\n                StartsWith( NSString* substr ) : StringHolder( substr ){}\r\n\r\n                bool match( NSString* str ) const override {\r\n                    return  (str != nil || m_substr == nil ) &&\r\n                            [str rangeOfString:m_substr].location == 0;\r\n                }\r\n\r\n                std::string describe() const override {\r\n                    return \"starts with: \" + Catch::Detail::stringify( m_substr );\r\n                }\r\n            };\r\n            struct EndsWith : StringHolder {\r\n                EndsWith( NSString* substr ) : StringHolder( substr ){}\r\n\r\n                bool match( NSString* str ) const override {\r\n                    return  (str != nil || m_substr == nil ) &&\r\n                            [str rangeOfString:m_substr].location == [str length] - [m_substr length];\r\n                }\r\n\r\n                std::string describe() const override {\r\n                    return \"ends with: \" + Catch::Detail::stringify( m_substr );\r\n                }\r\n            };\r\n\r\n        } // namespace NSStringMatchers\r\n        } // namespace Impl\r\n\r\n        inline Impl::NSStringMatchers::Equals\r\n            Equals( NSString* substr ){ return Impl::NSStringMatchers::Equals( substr ); }\r\n\r\n        inline Impl::NSStringMatchers::Contains\r\n            Contains( NSString* substr ){ return Impl::NSStringMatchers::Contains( substr ); }\r\n\r\n        inline Impl::NSStringMatchers::StartsWith\r\n            StartsWith( NSString* substr ){ return Impl::NSStringMatchers::StartsWith( substr ); }\r\n\r\n        inline Impl::NSStringMatchers::EndsWith\r\n            EndsWith( NSString* substr ){ return Impl::NSStringMatchers::EndsWith( substr ); }\r\n\r\n    } // namespace Matchers\r\n\r\n    using namespace Matchers;\r\n\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n\r\n} // namespace Catch\r\n\r\n///////////////////////////////////////////////////////////////////////////////\r\n#define OC_MAKE_UNIQUE_NAME( root, uniqueSuffix ) root##uniqueSuffix\r\n#define OC_TEST_CASE2( name, desc, uniqueSuffix ) \\\r\n+(NSString*) OC_MAKE_UNIQUE_NAME( Catch_Name_test_, uniqueSuffix ) \\\r\n{ \\\r\nreturn @ name; \\\r\n} \\\r\n+(NSString*) OC_MAKE_UNIQUE_NAME( Catch_Description_test_, uniqueSuffix ) \\\r\n{ \\\r\nreturn @ desc; \\\r\n} \\\r\n-(void) OC_MAKE_UNIQUE_NAME( Catch_TestCase_test_, uniqueSuffix )\r\n\r\n#define OC_TEST_CASE( name, desc ) OC_TEST_CASE2( name, desc, __LINE__ )\r\n\r\n// end catch_objc.hpp\r\n#endif\r\n\r\n#ifdef CATCH_CONFIG_EXTERNAL_INTERFACES\r\n// start catch_external_interfaces.h\r\n\r\n// start catch_reporter_bases.hpp\r\n\r\n// start catch_interfaces_reporter.h\r\n\r\n// start catch_config.hpp\r\n\r\n// start catch_test_spec_parser.h\r\n\r\n#ifdef __clang__\r\n#pragma clang diagnostic push\r\n#pragma clang diagnostic ignored \"-Wpadded\"\r\n#endif\r\n\r\n// start catch_test_spec.h\r\n\r\n#ifdef __clang__\r\n#pragma clang diagnostic push\r\n#pragma clang diagnostic ignored \"-Wpadded\"\r\n#endif\r\n\r\n// start catch_wildcard_pattern.h\r\n\r\nnamespace Catch\r\n{\r\n    class WildcardPattern {\r\n        enum WildcardPosition {\r\n            NoWildcard = 0,\r\n            WildcardAtStart = 1,\r\n            WildcardAtEnd = 2,\r\n            WildcardAtBothEnds = WildcardAtStart | WildcardAtEnd\r\n        };\r\n\r\n    public:\r\n\r\n        WildcardPattern( std::string const& pattern, CaseSensitive::Choice caseSensitivity );\r\n        virtual ~WildcardPattern() = default;\r\n        virtual bool matches( std::string const& str ) const;\r\n\r\n    private:\r\n        std::string adjustCase( std::string const& str ) const;\r\n        CaseSensitive::Choice m_caseSensitivity;\r\n        WildcardPosition m_wildcard = NoWildcard;\r\n        std::string m_pattern;\r\n    };\r\n}\r\n\r\n// end catch_wildcard_pattern.h\r\n#include <string>\r\n#include <vector>\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    class TestSpec {\r\n        struct Pattern {\r\n            virtual ~Pattern();\r\n            virtual bool matches( TestCaseInfo const& testCase ) const = 0;\r\n        };\r\n        using PatternPtr = std::shared_ptr<Pattern>;\r\n\r\n        class NamePattern : public Pattern {\r\n        public:\r\n            NamePattern( std::string const& name );\r\n            virtual ~NamePattern();\r\n            virtual bool matches( TestCaseInfo const& testCase ) const override;\r\n        private:\r\n            WildcardPattern m_wildcardPattern;\r\n        };\r\n\r\n        class TagPattern : public Pattern {\r\n        public:\r\n            TagPattern( std::string const& tag );\r\n            virtual ~TagPattern();\r\n            virtual bool matches( TestCaseInfo const& testCase ) const override;\r\n        private:\r\n            std::string m_tag;\r\n        };\r\n\r\n        class ExcludedPattern : public Pattern {\r\n        public:\r\n            ExcludedPattern( PatternPtr const& underlyingPattern );\r\n            virtual ~ExcludedPattern();\r\n            virtual bool matches( TestCaseInfo const& testCase ) const override;\r\n        private:\r\n            PatternPtr m_underlyingPattern;\r\n        };\r\n\r\n        struct Filter {\r\n            std::vector<PatternPtr> m_patterns;\r\n\r\n            bool matches( TestCaseInfo const& testCase ) const;\r\n        };\r\n\r\n    public:\r\n        bool hasFilters() const;\r\n        bool matches( TestCaseInfo const& testCase ) const;\r\n\r\n    private:\r\n        std::vector<Filter> m_filters;\r\n\r\n        friend class TestSpecParser;\r\n    };\r\n}\r\n\r\n#ifdef __clang__\r\n#pragma clang diagnostic pop\r\n#endif\r\n\r\n// end catch_test_spec.h\r\n// start catch_interfaces_tag_alias_registry.h\r\n\r\n#include <string>\r\n\r\nnamespace Catch {\r\n\r\n    struct TagAlias;\r\n\r\n    struct ITagAliasRegistry {\r\n        virtual ~ITagAliasRegistry();\r\n        // Nullptr if not present\r\n        virtual TagAlias const* find( std::string const& alias ) const = 0;\r\n        virtual std::string expandAliases( std::string const& unexpandedTestSpec ) const = 0;\r\n\r\n        static ITagAliasRegistry const& get();\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_interfaces_tag_alias_registry.h\r\nnamespace Catch {\r\n\r\n    class TestSpecParser {\r\n        enum Mode{ None, Name, QuotedName, Tag, EscapedName };\r\n        Mode m_mode = None;\r\n        bool m_exclusion = false;\r\n        std::size_t m_start = std::string::npos, m_pos = 0;\r\n        std::string m_arg;\r\n        std::vector<std::size_t> m_escapeChars;\r\n        TestSpec::Filter m_currentFilter;\r\n        TestSpec m_testSpec;\r\n        ITagAliasRegistry const* m_tagAliases = nullptr;\r\n\r\n    public:\r\n        TestSpecParser( ITagAliasRegistry const& tagAliases );\r\n\r\n        TestSpecParser& parse( std::string const& arg );\r\n        TestSpec testSpec();\r\n\r\n    private:\r\n        void visitChar( char c );\r\n        void startNewMode( Mode mode, std::size_t start );\r\n        void escape();\r\n        std::string subString() const;\r\n\r\n        template<typename T>\r\n        void addPattern() {\r\n            std::string token = subString();\r\n            for( std::size_t i = 0; i < m_escapeChars.size(); ++i )\r\n                token = token.substr( 0, m_escapeChars[i]-m_start-i ) + token.substr( m_escapeChars[i]-m_start-i+1 );\r\n            m_escapeChars.clear();\r\n            if( startsWith( token, \"exclude:\" ) ) {\r\n                m_exclusion = true;\r\n                token = token.substr( 8 );\r\n            }\r\n            if( !token.empty() ) {\r\n                TestSpec::PatternPtr pattern = std::make_shared<T>( token );\r\n                if( m_exclusion )\r\n                    pattern = std::make_shared<TestSpec::ExcludedPattern>( pattern );\r\n                m_currentFilter.m_patterns.push_back( pattern );\r\n            }\r\n            m_exclusion = false;\r\n            m_mode = None;\r\n        }\r\n\r\n        void addFilter();\r\n    };\r\n    TestSpec parseTestSpec( std::string const& arg );\r\n\r\n} // namespace Catch\r\n\r\n#ifdef __clang__\r\n#pragma clang diagnostic pop\r\n#endif\r\n\r\n// end catch_test_spec_parser.h\r\n// Libstdc++ doesn't like incomplete classes for unique_ptr\r\n\r\n#include <memory>\r\n#include <vector>\r\n#include <string>\r\n\r\n#ifndef CATCH_CONFIG_CONSOLE_WIDTH\r\n#define CATCH_CONFIG_CONSOLE_WIDTH 80\r\n#endif\r\n\r\nnamespace Catch {\r\n\r\n    struct IStream;\r\n\r\n    struct ConfigData {\r\n        bool listTests = false;\r\n        bool listTags = false;\r\n        bool listReporters = false;\r\n        bool listTestNamesOnly = false;\r\n\r\n        bool showSuccessfulTests = false;\r\n        bool shouldDebugBreak = false;\r\n        bool noThrow = false;\r\n        bool showHelp = false;\r\n        bool showInvisibles = false;\r\n        bool filenamesAsTags = false;\r\n        bool libIdentify = false;\r\n\r\n        int abortAfter = -1;\r\n        unsigned int rngSeed = 0;\r\n        int benchmarkResolutionMultiple = 100;\r\n\r\n        Verbosity verbosity = Verbosity::Normal;\r\n        WarnAbout::What warnings = WarnAbout::Nothing;\r\n        ShowDurations::OrNot showDurations = ShowDurations::DefaultForReporter;\r\n        RunTests::InWhatOrder runOrder = RunTests::InDeclarationOrder;\r\n        UseColour::YesOrNo useColour = UseColour::Auto;\r\n        WaitForKeypress::When waitForKeypress = WaitForKeypress::Never;\r\n\r\n        std::string outputFilename;\r\n        std::string name;\r\n        std::string processName;\r\n#ifndef CATCH_CONFIG_DEFAULT_REPORTER\r\n#define CATCH_CONFIG_DEFAULT_REPORTER \"console\"\r\n#endif\r\n        std::string reporterName = CATCH_CONFIG_DEFAULT_REPORTER;\r\n#undef CATCH_CONFIG_DEFAULT_REPORTER\r\n\r\n        std::vector<std::string> testsOrTags;\r\n        std::vector<std::string> sectionsToRun;\r\n    };\r\n\r\n    class Config : public IConfig {\r\n    public:\r\n\r\n        Config() = default;\r\n        Config( ConfigData const& data );\r\n        virtual ~Config() = default;\r\n\r\n        std::string const& getFilename() const;\r\n\r\n        bool listTests() const;\r\n        bool listTestNamesOnly() const;\r\n        bool listTags() const;\r\n        bool listReporters() const;\r\n\r\n        std::string getProcessName() const;\r\n        std::string const& getReporterName() const;\r\n\r\n        std::vector<std::string> const& getTestsOrTags() const;\r\n        std::vector<std::string> const& getSectionsToRun() const override;\r\n\r\n        virtual TestSpec const& testSpec() const override;\r\n        bool hasTestFilters() const override;\r\n\r\n        bool showHelp() const;\r\n\r\n        // IConfig interface\r\n        bool allowThrows() const override;\r\n        std::ostream& stream() const override;\r\n        std::string name() const override;\r\n        bool includeSuccessfulResults() const override;\r\n        bool warnAboutMissingAssertions() const override;\r\n        bool warnAboutNoTests() const override;\r\n        ShowDurations::OrNot showDurations() const override;\r\n        RunTests::InWhatOrder runOrder() const override;\r\n        unsigned int rngSeed() const override;\r\n        int benchmarkResolutionMultiple() const override;\r\n        UseColour::YesOrNo useColour() const override;\r\n        bool shouldDebugBreak() const override;\r\n        int abortAfter() const override;\r\n        bool showInvisibles() const override;\r\n        Verbosity verbosity() const override;\r\n\r\n    private:\r\n\r\n        IStream const* openStream();\r\n        ConfigData m_data;\r\n\r\n        std::unique_ptr<IStream const> m_stream;\r\n        TestSpec m_testSpec;\r\n        bool m_hasTestFilters = false;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_config.hpp\r\n// start catch_assertionresult.h\r\n\r\n#include <string>\r\n\r\nnamespace Catch {\r\n\r\n    struct AssertionResultData\r\n    {\r\n        AssertionResultData() = delete;\r\n\r\n        AssertionResultData( ResultWas::OfType _resultType, LazyExpression const& _lazyExpression );\r\n\r\n        std::string message;\r\n        mutable std::string reconstructedExpression;\r\n        LazyExpression lazyExpression;\r\n        ResultWas::OfType resultType;\r\n\r\n        std::string reconstructExpression() const;\r\n    };\r\n\r\n    class AssertionResult {\r\n    public:\r\n        AssertionResult() = delete;\r\n        AssertionResult( AssertionInfo const& info, AssertionResultData const& data );\r\n\r\n        bool isOk() const;\r\n        bool succeeded() const;\r\n        ResultWas::OfType getResultType() const;\r\n        bool hasExpression() const;\r\n        bool hasMessage() const;\r\n        std::string getExpression() const;\r\n        std::string getExpressionInMacro() const;\r\n        bool hasExpandedExpression() const;\r\n        std::string getExpandedExpression() const;\r\n        std::string getMessage() const;\r\n        SourceLineInfo getSourceInfo() const;\r\n        StringRef getTestMacroName() const;\r\n\r\n    //protected:\r\n        AssertionInfo m_info;\r\n        AssertionResultData m_resultData;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_assertionresult.h\r\n// start catch_option.hpp\r\n\r\nnamespace Catch {\r\n\r\n    // An optional type\r\n    template<typename T>\r\n    class Option {\r\n    public:\r\n        Option() : nullableValue( nullptr ) {}\r\n        Option( T const& _value )\r\n        : nullableValue( new( storage ) T( _value ) )\r\n        {}\r\n        Option( Option const& _other )\r\n        : nullableValue( _other ? new( storage ) T( *_other ) : nullptr )\r\n        {}\r\n\r\n        ~Option() {\r\n            reset();\r\n        }\r\n\r\n        Option& operator= ( Option const& _other ) {\r\n            if( &_other != this ) {\r\n                reset();\r\n                if( _other )\r\n                    nullableValue = new( storage ) T( *_other );\r\n            }\r\n            return *this;\r\n        }\r\n        Option& operator = ( T const& _value ) {\r\n            reset();\r\n            nullableValue = new( storage ) T( _value );\r\n            return *this;\r\n        }\r\n\r\n        void reset() {\r\n            if( nullableValue )\r\n                nullableValue->~T();\r\n            nullableValue = nullptr;\r\n        }\r\n\r\n        T& operator*() { return *nullableValue; }\r\n        T const& operator*() const { return *nullableValue; }\r\n        T* operator->() { return nullableValue; }\r\n        const T* operator->() const { return nullableValue; }\r\n\r\n        T valueOr( T const& defaultValue ) const {\r\n            return nullableValue ? *nullableValue : defaultValue;\r\n        }\r\n\r\n        bool some() const { return nullableValue != nullptr; }\r\n        bool none() const { return nullableValue == nullptr; }\r\n\r\n        bool operator !() const { return nullableValue == nullptr; }\r\n        explicit operator bool() const {\r\n            return some();\r\n        }\r\n\r\n    private:\r\n        T *nullableValue;\r\n        alignas(alignof(T)) char storage[sizeof(T)];\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_option.hpp\r\n#include <string>\r\n#include <iosfwd>\r\n#include <map>\r\n#include <set>\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    struct ReporterConfig {\r\n        explicit ReporterConfig( IConfigPtr const& _fullConfig );\r\n\r\n        ReporterConfig( IConfigPtr const& _fullConfig, std::ostream& _stream );\r\n\r\n        std::ostream& stream() const;\r\n        IConfigPtr fullConfig() const;\r\n\r\n    private:\r\n        std::ostream* m_stream;\r\n        IConfigPtr m_fullConfig;\r\n    };\r\n\r\n    struct ReporterPreferences {\r\n        bool shouldRedirectStdOut = false;\r\n        bool shouldReportAllAssertions = false;\r\n    };\r\n\r\n    template<typename T>\r\n    struct LazyStat : Option<T> {\r\n        LazyStat& operator=( T const& _value ) {\r\n            Option<T>::operator=( _value );\r\n            used = false;\r\n            return *this;\r\n        }\r\n        void reset() {\r\n            Option<T>::reset();\r\n            used = false;\r\n        }\r\n        bool used = false;\r\n    };\r\n\r\n    struct TestRunInfo {\r\n        TestRunInfo( std::string const& _name );\r\n        std::string name;\r\n    };\r\n    struct GroupInfo {\r\n        GroupInfo(  std::string const& _name,\r\n                    std::size_t _groupIndex,\r\n                    std::size_t _groupsCount );\r\n\r\n        std::string name;\r\n        std::size_t groupIndex;\r\n        std::size_t groupsCounts;\r\n    };\r\n\r\n    struct AssertionStats {\r\n        AssertionStats( AssertionResult const& _assertionResult,\r\n                        std::vector<MessageInfo> const& _infoMessages,\r\n                        Totals const& _totals );\r\n\r\n        AssertionStats( AssertionStats const& )              = default;\r\n        AssertionStats( AssertionStats && )                  = default;\r\n        AssertionStats& operator = ( AssertionStats const& ) = delete;\r\n        AssertionStats& operator = ( AssertionStats && )     = delete;\r\n        virtual ~AssertionStats();\r\n\r\n        AssertionResult assertionResult;\r\n        std::vector<MessageInfo> infoMessages;\r\n        Totals totals;\r\n    };\r\n\r\n    struct SectionStats {\r\n        SectionStats(   SectionInfo const& _sectionInfo,\r\n                        Counts const& _assertions,\r\n                        double _durationInSeconds,\r\n                        bool _missingAssertions );\r\n        SectionStats( SectionStats const& )              = default;\r\n        SectionStats( SectionStats && )                  = default;\r\n        SectionStats& operator = ( SectionStats const& ) = default;\r\n        SectionStats& operator = ( SectionStats && )     = default;\r\n        virtual ~SectionStats();\r\n\r\n        SectionInfo sectionInfo;\r\n        Counts assertions;\r\n        double durationInSeconds;\r\n        bool missingAssertions;\r\n    };\r\n\r\n    struct TestCaseStats {\r\n        TestCaseStats(  TestCaseInfo const& _testInfo,\r\n                        Totals const& _totals,\r\n                        std::string const& _stdOut,\r\n                        std::string const& _stdErr,\r\n                        bool _aborting );\r\n\r\n        TestCaseStats( TestCaseStats const& )              = default;\r\n        TestCaseStats( TestCaseStats && )                  = default;\r\n        TestCaseStats& operator = ( TestCaseStats const& ) = default;\r\n        TestCaseStats& operator = ( TestCaseStats && )     = default;\r\n        virtual ~TestCaseStats();\r\n\r\n        TestCaseInfo testInfo;\r\n        Totals totals;\r\n        std::string stdOut;\r\n        std::string stdErr;\r\n        bool aborting;\r\n    };\r\n\r\n    struct TestGroupStats {\r\n        TestGroupStats( GroupInfo const& _groupInfo,\r\n                        Totals const& _totals,\r\n                        bool _aborting );\r\n        TestGroupStats( GroupInfo const& _groupInfo );\r\n\r\n        TestGroupStats( TestGroupStats const& )              = default;\r\n        TestGroupStats( TestGroupStats && )                  = default;\r\n        TestGroupStats& operator = ( TestGroupStats const& ) = default;\r\n        TestGroupStats& operator = ( TestGroupStats && )     = default;\r\n        virtual ~TestGroupStats();\r\n\r\n        GroupInfo groupInfo;\r\n        Totals totals;\r\n        bool aborting;\r\n    };\r\n\r\n    struct TestRunStats {\r\n        TestRunStats(   TestRunInfo const& _runInfo,\r\n                        Totals const& _totals,\r\n                        bool _aborting );\r\n\r\n        TestRunStats( TestRunStats const& )              = default;\r\n        TestRunStats( TestRunStats && )                  = default;\r\n        TestRunStats& operator = ( TestRunStats const& ) = default;\r\n        TestRunStats& operator = ( TestRunStats && )     = default;\r\n        virtual ~TestRunStats();\r\n\r\n        TestRunInfo runInfo;\r\n        Totals totals;\r\n        bool aborting;\r\n    };\r\n\r\n    struct BenchmarkInfo {\r\n        std::string name;\r\n    };\r\n    struct BenchmarkStats {\r\n        BenchmarkInfo info;\r\n        std::size_t iterations;\r\n        uint64_t elapsedTimeInNanoseconds;\r\n    };\r\n\r\n    struct IStreamingReporter {\r\n        virtual ~IStreamingReporter() = default;\r\n\r\n        // Implementing class must also provide the following static methods:\r\n        // static std::string getDescription();\r\n        // static std::set<Verbosity> getSupportedVerbosities()\r\n\r\n        virtual ReporterPreferences getPreferences() const = 0;\r\n\r\n        virtual void noMatchingTestCases( std::string const& spec ) = 0;\r\n\r\n        virtual void testRunStarting( TestRunInfo const& testRunInfo ) = 0;\r\n        virtual void testGroupStarting( GroupInfo const& groupInfo ) = 0;\r\n\r\n        virtual void testCaseStarting( TestCaseInfo const& testInfo ) = 0;\r\n        virtual void sectionStarting( SectionInfo const& sectionInfo ) = 0;\r\n\r\n        // *** experimental ***\r\n        virtual void benchmarkStarting( BenchmarkInfo const& ) {}\r\n\r\n        virtual void assertionStarting( AssertionInfo const& assertionInfo ) = 0;\r\n\r\n        // The return value indicates if the messages buffer should be cleared:\r\n        virtual bool assertionEnded( AssertionStats const& assertionStats ) = 0;\r\n\r\n        // *** experimental ***\r\n        virtual void benchmarkEnded( BenchmarkStats const& ) {}\r\n\r\n        virtual void sectionEnded( SectionStats const& sectionStats ) = 0;\r\n        virtual void testCaseEnded( TestCaseStats const& testCaseStats ) = 0;\r\n        virtual void testGroupEnded( TestGroupStats const& testGroupStats ) = 0;\r\n        virtual void testRunEnded( TestRunStats const& testRunStats ) = 0;\r\n\r\n        virtual void skipTest( TestCaseInfo const& testInfo ) = 0;\r\n\r\n        // Default empty implementation provided\r\n        virtual void fatalErrorEncountered( StringRef name );\r\n\r\n        virtual bool isMulti() const;\r\n    };\r\n    using IStreamingReporterPtr = std::unique_ptr<IStreamingReporter>;\r\n\r\n    struct IReporterFactory {\r\n        virtual ~IReporterFactory();\r\n        virtual IStreamingReporterPtr create( ReporterConfig const& config ) const = 0;\r\n        virtual std::string getDescription() const = 0;\r\n    };\r\n    using IReporterFactoryPtr = std::shared_ptr<IReporterFactory>;\r\n\r\n    struct IReporterRegistry {\r\n        using FactoryMap = std::map<std::string, IReporterFactoryPtr>;\r\n        using Listeners = std::vector<IReporterFactoryPtr>;\r\n\r\n        virtual ~IReporterRegistry();\r\n        virtual IStreamingReporterPtr create( std::string const& name, IConfigPtr const& config ) const = 0;\r\n        virtual FactoryMap const& getFactories() const = 0;\r\n        virtual Listeners const& getListeners() const = 0;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_interfaces_reporter.h\r\n#include <algorithm>\r\n#include <cstring>\r\n#include <cfloat>\r\n#include <cstdio>\r\n#include <cassert>\r\n#include <memory>\r\n#include <ostream>\r\n\r\nnamespace Catch {\r\n    void prepareExpandedExpression(AssertionResult& result);\r\n\r\n    // Returns double formatted as %.3f (format expected on output)\r\n    std::string getFormattedDuration( double duration );\r\n\r\n    template<typename DerivedT>\r\n    struct StreamingReporterBase : IStreamingReporter {\r\n\r\n        StreamingReporterBase( ReporterConfig const& _config )\r\n        :   m_config( _config.fullConfig() ),\r\n            stream( _config.stream() )\r\n        {\r\n            m_reporterPrefs.shouldRedirectStdOut = false;\r\n            if( !DerivedT::getSupportedVerbosities().count( m_config->verbosity() ) )\r\n                CATCH_ERROR( \"Verbosity level not supported by this reporter\" );\r\n        }\r\n\r\n        ReporterPreferences getPreferences() const override {\r\n            return m_reporterPrefs;\r\n        }\r\n\r\n        static std::set<Verbosity> getSupportedVerbosities() {\r\n            return { Verbosity::Normal };\r\n        }\r\n\r\n        ~StreamingReporterBase() override = default;\r\n\r\n        void noMatchingTestCases(std::string const&) override {}\r\n\r\n        void testRunStarting(TestRunInfo const& _testRunInfo) override {\r\n            currentTestRunInfo = _testRunInfo;\r\n        }\r\n        void testGroupStarting(GroupInfo const& _groupInfo) override {\r\n            currentGroupInfo = _groupInfo;\r\n        }\r\n\r\n        void testCaseStarting(TestCaseInfo const& _testInfo) override  {\r\n            currentTestCaseInfo = _testInfo;\r\n        }\r\n        void sectionStarting(SectionInfo const& _sectionInfo) override {\r\n            m_sectionStack.push_back(_sectionInfo);\r\n        }\r\n\r\n        void sectionEnded(SectionStats const& /* _sectionStats */) override {\r\n            m_sectionStack.pop_back();\r\n        }\r\n        void testCaseEnded(TestCaseStats const& /* _testCaseStats */) override {\r\n            currentTestCaseInfo.reset();\r\n        }\r\n        void testGroupEnded(TestGroupStats const& /* _testGroupStats */) override {\r\n            currentGroupInfo.reset();\r\n        }\r\n        void testRunEnded(TestRunStats const& /* _testRunStats */) override {\r\n            currentTestCaseInfo.reset();\r\n            currentGroupInfo.reset();\r\n            currentTestRunInfo.reset();\r\n        }\r\n\r\n        void skipTest(TestCaseInfo const&) override {\r\n            // Don't do anything with this by default.\r\n            // It can optionally be overridden in the derived class.\r\n        }\r\n\r\n        IConfigPtr m_config;\r\n        std::ostream& stream;\r\n\r\n        LazyStat<TestRunInfo> currentTestRunInfo;\r\n        LazyStat<GroupInfo> currentGroupInfo;\r\n        LazyStat<TestCaseInfo> currentTestCaseInfo;\r\n\r\n        std::vector<SectionInfo> m_sectionStack;\r\n        ReporterPreferences m_reporterPrefs;\r\n    };\r\n\r\n    template<typename DerivedT>\r\n    struct CumulativeReporterBase : IStreamingReporter {\r\n        template<typename T, typename ChildNodeT>\r\n        struct Node {\r\n            explicit Node( T const& _value ) : value( _value ) {}\r\n            virtual ~Node() {}\r\n\r\n            using ChildNodes = std::vector<std::shared_ptr<ChildNodeT>>;\r\n            T value;\r\n            ChildNodes children;\r\n        };\r\n        struct SectionNode {\r\n            explicit SectionNode(SectionStats const& _stats) : stats(_stats) {}\r\n            virtual ~SectionNode() = default;\r\n\r\n            bool operator == (SectionNode const& other) const {\r\n                return stats.sectionInfo.lineInfo == other.stats.sectionInfo.lineInfo;\r\n            }\r\n            bool operator == (std::shared_ptr<SectionNode> const& other) const {\r\n                return operator==(*other);\r\n            }\r\n\r\n            SectionStats stats;\r\n            using ChildSections = std::vector<std::shared_ptr<SectionNode>>;\r\n            using Assertions = std::vector<AssertionStats>;\r\n            ChildSections childSections;\r\n            Assertions assertions;\r\n            std::string stdOut;\r\n            std::string stdErr;\r\n        };\r\n\r\n        struct BySectionInfo {\r\n            BySectionInfo( SectionInfo const& other ) : m_other( other ) {}\r\n            BySectionInfo( BySectionInfo const& other ) : m_other( other.m_other ) {}\r\n            bool operator() (std::shared_ptr<SectionNode> const& node) const {\r\n                return ((node->stats.sectionInfo.name == m_other.name) &&\r\n                        (node->stats.sectionInfo.lineInfo == m_other.lineInfo));\r\n            }\r\n            void operator=(BySectionInfo const&) = delete;\r\n\r\n        private:\r\n            SectionInfo const& m_other;\r\n        };\r\n\r\n        using TestCaseNode = Node<TestCaseStats, SectionNode>;\r\n        using TestGroupNode = Node<TestGroupStats, TestCaseNode>;\r\n        using TestRunNode = Node<TestRunStats, TestGroupNode>;\r\n\r\n        CumulativeReporterBase( ReporterConfig const& _config )\r\n        :   m_config( _config.fullConfig() ),\r\n            stream( _config.stream() )\r\n        {\r\n            m_reporterPrefs.shouldRedirectStdOut = false;\r\n            if( !DerivedT::getSupportedVerbosities().count( m_config->verbosity() ) )\r\n                CATCH_ERROR( \"Verbosity level not supported by this reporter\" );\r\n        }\r\n        ~CumulativeReporterBase() override = default;\r\n\r\n        ReporterPreferences getPreferences() const override {\r\n            return m_reporterPrefs;\r\n        }\r\n\r\n        static std::set<Verbosity> getSupportedVerbosities() {\r\n            return { Verbosity::Normal };\r\n        }\r\n\r\n        void testRunStarting( TestRunInfo const& ) override {}\r\n        void testGroupStarting( GroupInfo const& ) override {}\r\n\r\n        void testCaseStarting( TestCaseInfo const& ) override {}\r\n\r\n        void sectionStarting( SectionInfo const& sectionInfo ) override {\r\n            SectionStats incompleteStats( sectionInfo, Counts(), 0, false );\r\n            std::shared_ptr<SectionNode> node;\r\n            if( m_sectionStack.empty() ) {\r\n                if( !m_rootSection )\r\n                    m_rootSection = std::make_shared<SectionNode>( incompleteStats );\r\n                node = m_rootSection;\r\n            }\r\n            else {\r\n                SectionNode& parentNode = *m_sectionStack.back();\r\n                auto it =\r\n                    std::find_if(   parentNode.childSections.begin(),\r\n                                    parentNode.childSections.end(),\r\n                                    BySectionInfo( sectionInfo ) );\r\n                if( it == parentNode.childSections.end() ) {\r\n                    node = std::make_shared<SectionNode>( incompleteStats );\r\n                    parentNode.childSections.push_back( node );\r\n                }\r\n                else\r\n                    node = *it;\r\n            }\r\n            m_sectionStack.push_back( node );\r\n            m_deepestSection = std::move(node);\r\n        }\r\n\r\n        void assertionStarting(AssertionInfo const&) override {}\r\n\r\n        bool assertionEnded(AssertionStats const& assertionStats) override {\r\n            assert(!m_sectionStack.empty());\r\n            // AssertionResult holds a pointer to a temporary DecomposedExpression,\r\n            // which getExpandedExpression() calls to build the expression string.\r\n            // Our section stack copy of the assertionResult will likely outlive the\r\n            // temporary, so it must be expanded or discarded now to avoid calling\r\n            // a destroyed object later.\r\n            prepareExpandedExpression(const_cast<AssertionResult&>( assertionStats.assertionResult ) );\r\n            SectionNode& sectionNode = *m_sectionStack.back();\r\n            sectionNode.assertions.push_back(assertionStats);\r\n            return true;\r\n        }\r\n        void sectionEnded(SectionStats const& sectionStats) override {\r\n            assert(!m_sectionStack.empty());\r\n            SectionNode& node = *m_sectionStack.back();\r\n            node.stats = sectionStats;\r\n            m_sectionStack.pop_back();\r\n        }\r\n        void testCaseEnded(TestCaseStats const& testCaseStats) override {\r\n            auto node = std::make_shared<TestCaseNode>(testCaseStats);\r\n            assert(m_sectionStack.size() == 0);\r\n            node->children.push_back(m_rootSection);\r\n            m_testCases.push_back(node);\r\n            m_rootSection.reset();\r\n\r\n            assert(m_deepestSection);\r\n            m_deepestSection->stdOut = testCaseStats.stdOut;\r\n            m_deepestSection->stdErr = testCaseStats.stdErr;\r\n        }\r\n        void testGroupEnded(TestGroupStats const& testGroupStats) override {\r\n            auto node = std::make_shared<TestGroupNode>(testGroupStats);\r\n            node->children.swap(m_testCases);\r\n            m_testGroups.push_back(node);\r\n        }\r\n        void testRunEnded(TestRunStats const& testRunStats) override {\r\n            auto node = std::make_shared<TestRunNode>(testRunStats);\r\n            node->children.swap(m_testGroups);\r\n            m_testRuns.push_back(node);\r\n            testRunEndedCumulative();\r\n        }\r\n        virtual void testRunEndedCumulative() = 0;\r\n\r\n        void skipTest(TestCaseInfo const&) override {}\r\n\r\n        IConfigPtr m_config;\r\n        std::ostream& stream;\r\n        std::vector<AssertionStats> m_assertions;\r\n        std::vector<std::vector<std::shared_ptr<SectionNode>>> m_sections;\r\n        std::vector<std::shared_ptr<TestCaseNode>> m_testCases;\r\n        std::vector<std::shared_ptr<TestGroupNode>> m_testGroups;\r\n\r\n        std::vector<std::shared_ptr<TestRunNode>> m_testRuns;\r\n\r\n        std::shared_ptr<SectionNode> m_rootSection;\r\n        std::shared_ptr<SectionNode> m_deepestSection;\r\n        std::vector<std::shared_ptr<SectionNode>> m_sectionStack;\r\n        ReporterPreferences m_reporterPrefs;\r\n    };\r\n\r\n    template<char C>\r\n    char const* getLineOfChars() {\r\n        static char line[CATCH_CONFIG_CONSOLE_WIDTH] = {0};\r\n        if( !*line ) {\r\n            std::memset( line, C, CATCH_CONFIG_CONSOLE_WIDTH-1 );\r\n            line[CATCH_CONFIG_CONSOLE_WIDTH-1] = 0;\r\n        }\r\n        return line;\r\n    }\r\n\r\n    struct TestEventListenerBase : StreamingReporterBase<TestEventListenerBase> {\r\n        TestEventListenerBase( ReporterConfig const& _config );\r\n\r\n        static std::set<Verbosity> getSupportedVerbosities();\r\n\r\n        void assertionStarting(AssertionInfo const&) override;\r\n        bool assertionEnded(AssertionStats const&) override;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_reporter_bases.hpp\r\n// start catch_console_colour.h\r\n\r\nnamespace Catch {\r\n\r\n    struct Colour {\r\n        enum Code {\r\n            None = 0,\r\n\r\n            White,\r\n            Red,\r\n            Green,\r\n            Blue,\r\n            Cyan,\r\n            Yellow,\r\n            Grey,\r\n\r\n            Bright = 0x10,\r\n\r\n            BrightRed = Bright | Red,\r\n            BrightGreen = Bright | Green,\r\n            LightGrey = Bright | Grey,\r\n            BrightWhite = Bright | White,\r\n            BrightYellow = Bright | Yellow,\r\n\r\n            // By intention\r\n            FileName = LightGrey,\r\n            Warning = BrightYellow,\r\n            ResultError = BrightRed,\r\n            ResultSuccess = BrightGreen,\r\n            ResultExpectedFailure = Warning,\r\n\r\n            Error = BrightRed,\r\n            Success = Green,\r\n\r\n            OriginalExpression = Cyan,\r\n            ReconstructedExpression = BrightYellow,\r\n\r\n            SecondaryText = LightGrey,\r\n            Headers = White\r\n        };\r\n\r\n        // Use constructed object for RAII guard\r\n        Colour( Code _colourCode );\r\n        Colour( Colour&& other ) noexcept;\r\n        Colour& operator=( Colour&& other ) noexcept;\r\n        ~Colour();\r\n\r\n        // Use static method for one-shot changes\r\n        static void use( Code _colourCode );\r\n\r\n    private:\r\n        bool m_moved = false;\r\n    };\r\n\r\n    std::ostream& operator << ( std::ostream& os, Colour const& );\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_console_colour.h\r\n// start catch_reporter_registrars.hpp\r\n\r\n\r\nnamespace Catch {\r\n\r\n    template<typename T>\r\n    class ReporterRegistrar {\r\n\r\n        class ReporterFactory : public IReporterFactory {\r\n\r\n            virtual IStreamingReporterPtr create( ReporterConfig const& config ) const override {\r\n                return std::unique_ptr<T>( new T( config ) );\r\n            }\r\n\r\n            virtual std::string getDescription() const override {\r\n                return T::getDescription();\r\n            }\r\n        };\r\n\r\n    public:\r\n\r\n        explicit ReporterRegistrar( std::string const& name ) {\r\n            getMutableRegistryHub().registerReporter( name, std::make_shared<ReporterFactory>() );\r\n        }\r\n    };\r\n\r\n    template<typename T>\r\n    class ListenerRegistrar {\r\n\r\n        class ListenerFactory : public IReporterFactory {\r\n\r\n            virtual IStreamingReporterPtr create( ReporterConfig const& config ) const override {\r\n                return std::unique_ptr<T>( new T( config ) );\r\n            }\r\n            virtual std::string getDescription() const override {\r\n                return std::string();\r\n            }\r\n        };\r\n\r\n    public:\r\n\r\n        ListenerRegistrar() {\r\n            getMutableRegistryHub().registerListener( std::make_shared<ListenerFactory>() );\r\n        }\r\n    };\r\n}\r\n\r\n#if !defined(CATCH_CONFIG_DISABLE)\r\n\r\n#define CATCH_REGISTER_REPORTER( name, reporterType ) \\\r\n    CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS          \\\r\n    namespace{ Catch::ReporterRegistrar<reporterType> catch_internal_RegistrarFor##reporterType( name ); } \\\r\n    CATCH_INTERNAL_UNSUPPRESS_GLOBALS_WARNINGS\r\n\r\n#define CATCH_REGISTER_LISTENER( listenerType ) \\\r\n     CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS   \\\r\n     namespace{ Catch::ListenerRegistrar<listenerType> catch_internal_RegistrarFor##listenerType; } \\\r\n     CATCH_INTERNAL_SUPPRESS_GLOBALS_WARNINGS\r\n#else // CATCH_CONFIG_DISABLE\r\n\r\n#define CATCH_REGISTER_REPORTER(name, reporterType)\r\n#define CATCH_REGISTER_LISTENER(listenerType)\r\n\r\n#endif // CATCH_CONFIG_DISABLE\r\n\r\n// end catch_reporter_registrars.hpp\r\n// Allow users to base their work off existing reporters\r\n// start catch_reporter_compact.h\r\n\r\nnamespace Catch {\r\n\r\n    struct CompactReporter : StreamingReporterBase<CompactReporter> {\r\n\r\n        using StreamingReporterBase::StreamingReporterBase;\r\n\r\n        ~CompactReporter() override;\r\n\r\n        static std::string getDescription();\r\n\r\n        ReporterPreferences getPreferences() const override;\r\n\r\n        void noMatchingTestCases(std::string const& spec) override;\r\n\r\n        void assertionStarting(AssertionInfo const&) override;\r\n\r\n        bool assertionEnded(AssertionStats const& _assertionStats) override;\r\n\r\n        void sectionEnded(SectionStats const& _sectionStats) override;\r\n\r\n        void testRunEnded(TestRunStats const& _testRunStats) override;\r\n\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_reporter_compact.h\r\n// start catch_reporter_console.h\r\n\r\n#if defined(_MSC_VER)\r\n#pragma warning(push)\r\n#pragma warning(disable:4061) // Not all labels are EXPLICITLY handled in switch\r\n                              // Note that 4062 (not all labels are handled\r\n                              // and default is missing) is enabled\r\n#endif\r\n\r\nnamespace Catch {\r\n    // Fwd decls\r\n    struct SummaryColumn;\r\n    class TablePrinter;\r\n\r\n    struct ConsoleReporter : StreamingReporterBase<ConsoleReporter> {\r\n        std::unique_ptr<TablePrinter> m_tablePrinter;\r\n\r\n        ConsoleReporter(ReporterConfig const& config);\r\n        ~ConsoleReporter() override;\r\n        static std::string getDescription();\r\n\r\n        void noMatchingTestCases(std::string const& spec) override;\r\n\r\n        void assertionStarting(AssertionInfo const&) override;\r\n\r\n        bool assertionEnded(AssertionStats const& _assertionStats) override;\r\n\r\n        void sectionStarting(SectionInfo const& _sectionInfo) override;\r\n        void sectionEnded(SectionStats const& _sectionStats) override;\r\n\r\n        void benchmarkStarting(BenchmarkInfo const& info) override;\r\n        void benchmarkEnded(BenchmarkStats const& stats) override;\r\n\r\n        void testCaseEnded(TestCaseStats const& _testCaseStats) override;\r\n        void testGroupEnded(TestGroupStats const& _testGroupStats) override;\r\n        void testRunEnded(TestRunStats const& _testRunStats) override;\r\n\r\n    private:\r\n\r\n        void lazyPrint();\r\n\r\n        void lazyPrintWithoutClosingBenchmarkTable();\r\n        void lazyPrintRunInfo();\r\n        void lazyPrintGroupInfo();\r\n        void printTestCaseAndSectionHeader();\r\n\r\n        void printClosedHeader(std::string const& _name);\r\n        void printOpenHeader(std::string const& _name);\r\n\r\n        // if string has a : in first line will set indent to follow it on\r\n        // subsequent lines\r\n        void printHeaderString(std::string const& _string, std::size_t indent = 0);\r\n\r\n        void printTotals(Totals const& totals);\r\n        void printSummaryRow(std::string const& label, std::vector<SummaryColumn> const& cols, std::size_t row);\r\n\r\n        void printTotalsDivider(Totals const& totals);\r\n        void printSummaryDivider();\r\n\r\n    private:\r\n        bool m_headerPrinted = false;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n#if defined(_MSC_VER)\r\n#pragma warning(pop)\r\n#endif\r\n\r\n// end catch_reporter_console.h\r\n// start catch_reporter_junit.h\r\n\r\n// start catch_xmlwriter.h\r\n\r\n#include <vector>\r\n\r\nnamespace Catch {\r\n\r\n    class XmlEncode {\r\n    public:\r\n        enum ForWhat { ForTextNodes, ForAttributes };\r\n\r\n        XmlEncode( std::string const& str, ForWhat forWhat = ForTextNodes );\r\n\r\n        void encodeTo( std::ostream& os ) const;\r\n\r\n        friend std::ostream& operator << ( std::ostream& os, XmlEncode const& xmlEncode );\r\n\r\n    private:\r\n        std::string m_str;\r\n        ForWhat m_forWhat;\r\n    };\r\n\r\n    class XmlWriter {\r\n    public:\r\n\r\n        class ScopedElement {\r\n        public:\r\n            ScopedElement( XmlWriter* writer );\r\n\r\n            ScopedElement( ScopedElement&& other ) noexcept;\r\n            ScopedElement& operator=( ScopedElement&& other ) noexcept;\r\n\r\n            ~ScopedElement();\r\n\r\n            ScopedElement& writeText( std::string const& text, bool indent = true );\r\n\r\n            template<typename T>\r\n            ScopedElement& writeAttribute( std::string const& name, T const& attribute ) {\r\n                m_writer->writeAttribute( name, attribute );\r\n                return *this;\r\n            }\r\n\r\n        private:\r\n            mutable XmlWriter* m_writer = nullptr;\r\n        };\r\n\r\n        XmlWriter( std::ostream& os = Catch::cout() );\r\n        ~XmlWriter();\r\n\r\n        XmlWriter( XmlWriter const& ) = delete;\r\n        XmlWriter& operator=( XmlWriter const& ) = delete;\r\n\r\n        XmlWriter& startElement( std::string const& name );\r\n\r\n        ScopedElement scopedElement( std::string const& name );\r\n\r\n        XmlWriter& endElement();\r\n\r\n        XmlWriter& writeAttribute( std::string const& name, std::string const& attribute );\r\n\r\n        XmlWriter& writeAttribute( std::string const& name, bool attribute );\r\n\r\n        template<typename T>\r\n        XmlWriter& writeAttribute( std::string const& name, T const& attribute ) {\r\n            ReusableStringStream rss;\r\n            rss << attribute;\r\n            return writeAttribute( name, rss.str() );\r\n        }\r\n\r\n        XmlWriter& writeText( std::string const& text, bool indent = true );\r\n\r\n        XmlWriter& writeComment( std::string const& text );\r\n\r\n        void writeStylesheetRef( std::string const& url );\r\n\r\n        XmlWriter& writeBlankLine();\r\n\r\n        void ensureTagClosed();\r\n\r\n    private:\r\n\r\n        void writeDeclaration();\r\n\r\n        void newlineIfNecessary();\r\n\r\n        bool m_tagIsOpen = false;\r\n        bool m_needsNewline = false;\r\n        std::vector<std::string> m_tags;\r\n        std::string m_indent;\r\n        std::ostream& m_os;\r\n    };\r\n\r\n}\r\n\r\n// end catch_xmlwriter.h\r\nnamespace Catch {\r\n\r\n    class JunitReporter : public CumulativeReporterBase<JunitReporter> {\r\n    public:\r\n        JunitReporter(ReporterConfig const& _config);\r\n\r\n        ~JunitReporter() override;\r\n\r\n        static std::string getDescription();\r\n\r\n        void noMatchingTestCases(std::string const& /*spec*/) override;\r\n\r\n        void testRunStarting(TestRunInfo const& runInfo) override;\r\n\r\n        void testGroupStarting(GroupInfo const& groupInfo) override;\r\n\r\n        void testCaseStarting(TestCaseInfo const& testCaseInfo) override;\r\n        bool assertionEnded(AssertionStats const& assertionStats) override;\r\n\r\n        void testCaseEnded(TestCaseStats const& testCaseStats) override;\r\n\r\n        void testGroupEnded(TestGroupStats const& testGroupStats) override;\r\n\r\n        void testRunEndedCumulative() override;\r\n\r\n        void writeGroup(TestGroupNode const& groupNode, double suiteTime);\r\n\r\n        void writeTestCase(TestCaseNode const& testCaseNode);\r\n\r\n        void writeSection(std::string const& className,\r\n                          std::string const& rootName,\r\n                          SectionNode const& sectionNode);\r\n\r\n        void writeAssertions(SectionNode const& sectionNode);\r\n        void writeAssertion(AssertionStats const& stats);\r\n\r\n        XmlWriter xml;\r\n        Timer suiteTimer;\r\n        std::string stdOutForSuite;\r\n        std::string stdErrForSuite;\r\n        unsigned int unexpectedExceptions = 0;\r\n        bool m_okToFail = false;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_reporter_junit.h\r\n// start catch_reporter_xml.h\r\n\r\nnamespace Catch {\r\n    class XmlReporter : public StreamingReporterBase<XmlReporter> {\r\n    public:\r\n        XmlReporter(ReporterConfig const& _config);\r\n\r\n        ~XmlReporter() override;\r\n\r\n        static std::string getDescription();\r\n\r\n        virtual std::string getStylesheetRef() const;\r\n\r\n        void writeSourceInfo(SourceLineInfo const& sourceInfo);\r\n\r\n    public: // StreamingReporterBase\r\n\r\n        void noMatchingTestCases(std::string const& s) override;\r\n\r\n        void testRunStarting(TestRunInfo const& testInfo) override;\r\n\r\n        void testGroupStarting(GroupInfo const& groupInfo) override;\r\n\r\n        void testCaseStarting(TestCaseInfo const& testInfo) override;\r\n\r\n        void sectionStarting(SectionInfo const& sectionInfo) override;\r\n\r\n        void assertionStarting(AssertionInfo const&) override;\r\n\r\n        bool assertionEnded(AssertionStats const& assertionStats) override;\r\n\r\n        void sectionEnded(SectionStats const& sectionStats) override;\r\n\r\n        void testCaseEnded(TestCaseStats const& testCaseStats) override;\r\n\r\n        void testGroupEnded(TestGroupStats const& testGroupStats) override;\r\n\r\n        void testRunEnded(TestRunStats const& testRunStats) override;\r\n\r\n    private:\r\n        Timer m_testCaseTimer;\r\n        XmlWriter m_xml;\r\n        int m_sectionDepth = 0;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_reporter_xml.h\r\n\r\n// end catch_external_interfaces.h\r\n#endif\r\n\r\n#endif // ! CATCH_CONFIG_IMPL_ONLY\r\n\r\n#ifdef CATCH_IMPL\r\n// start catch_impl.hpp\r\n\r\n#ifdef __clang__\r\n#pragma clang diagnostic push\r\n#pragma clang diagnostic ignored \"-Wweak-vtables\"\r\n#endif\r\n\r\n// Keep these here for external reporters\r\n// start catch_test_case_tracker.h\r\n\r\n#include <string>\r\n#include <vector>\r\n#include <memory>\r\n\r\nnamespace Catch {\r\nnamespace TestCaseTracking {\r\n\r\n    struct NameAndLocation {\r\n        std::string name;\r\n        SourceLineInfo location;\r\n\r\n        NameAndLocation( std::string const& _name, SourceLineInfo const& _location );\r\n    };\r\n\r\n    struct ITracker;\r\n\r\n    using ITrackerPtr = std::shared_ptr<ITracker>;\r\n\r\n    struct ITracker {\r\n        virtual ~ITracker();\r\n\r\n        // static queries\r\n        virtual NameAndLocation const& nameAndLocation() const = 0;\r\n\r\n        // dynamic queries\r\n        virtual bool isComplete() const = 0; // Successfully completed or failed\r\n        virtual bool isSuccessfullyCompleted() const = 0;\r\n        virtual bool isOpen() const = 0; // Started but not complete\r\n        virtual bool hasChildren() const = 0;\r\n\r\n        virtual ITracker& parent() = 0;\r\n\r\n        // actions\r\n        virtual void close() = 0; // Successfully complete\r\n        virtual void fail() = 0;\r\n        virtual void markAsNeedingAnotherRun() = 0;\r\n\r\n        virtual void addChild( ITrackerPtr const& child ) = 0;\r\n        virtual ITrackerPtr findChild( NameAndLocation const& nameAndLocation ) = 0;\r\n        virtual void openChild() = 0;\r\n\r\n        // Debug/ checking\r\n        virtual bool isSectionTracker() const = 0;\r\n        virtual bool isGeneratorTracker() const = 0;\r\n    };\r\n\r\n    class TrackerContext {\r\n\r\n        enum RunState {\r\n            NotStarted,\r\n            Executing,\r\n            CompletedCycle\r\n        };\r\n\r\n        ITrackerPtr m_rootTracker;\r\n        ITracker* m_currentTracker = nullptr;\r\n        RunState m_runState = NotStarted;\r\n\r\n    public:\r\n\r\n        static TrackerContext& instance();\r\n\r\n        ITracker& startRun();\r\n        void endRun();\r\n\r\n        void startCycle();\r\n        void completeCycle();\r\n\r\n        bool completedCycle() const;\r\n        ITracker& currentTracker();\r\n        void setCurrentTracker( ITracker* tracker );\r\n    };\r\n\r\n    class TrackerBase : public ITracker {\r\n    protected:\r\n        enum CycleState {\r\n            NotStarted,\r\n            Executing,\r\n            ExecutingChildren,\r\n            NeedsAnotherRun,\r\n            CompletedSuccessfully,\r\n            Failed\r\n        };\r\n\r\n        using Children = std::vector<ITrackerPtr>;\r\n        NameAndLocation m_nameAndLocation;\r\n        TrackerContext& m_ctx;\r\n        ITracker* m_parent;\r\n        Children m_children;\r\n        CycleState m_runState = NotStarted;\r\n\r\n    public:\r\n        TrackerBase( NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent );\r\n\r\n        NameAndLocation const& nameAndLocation() const override;\r\n        bool isComplete() const override;\r\n        bool isSuccessfullyCompleted() const override;\r\n        bool isOpen() const override;\r\n        bool hasChildren() const override;\r\n\r\n        void addChild( ITrackerPtr const& child ) override;\r\n\r\n        ITrackerPtr findChild( NameAndLocation const& nameAndLocation ) override;\r\n        ITracker& parent() override;\r\n\r\n        void openChild() override;\r\n\r\n        bool isSectionTracker() const override;\r\n        bool isGeneratorTracker() const override;\r\n\r\n        void open();\r\n\r\n        void close() override;\r\n        void fail() override;\r\n        void markAsNeedingAnotherRun() override;\r\n\r\n    private:\r\n        void moveToParent();\r\n        void moveToThis();\r\n    };\r\n\r\n    class SectionTracker : public TrackerBase {\r\n        std::vector<std::string> m_filters;\r\n    public:\r\n        SectionTracker( NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent );\r\n\r\n        bool isSectionTracker() const override;\r\n\r\n        bool isComplete() const override;\r\n\r\n        static SectionTracker& acquire( TrackerContext& ctx, NameAndLocation const& nameAndLocation );\r\n\r\n        void tryOpen();\r\n\r\n        void addInitialFilters( std::vector<std::string> const& filters );\r\n        void addNextFilters( std::vector<std::string> const& filters );\r\n    };\r\n\r\n} // namespace TestCaseTracking\r\n\r\nusing TestCaseTracking::ITracker;\r\nusing TestCaseTracking::TrackerContext;\r\nusing TestCaseTracking::SectionTracker;\r\n\r\n} // namespace Catch\r\n\r\n// end catch_test_case_tracker.h\r\n\r\n// start catch_leak_detector.h\r\n\r\nnamespace Catch {\r\n\r\n    struct LeakDetector {\r\n        LeakDetector();\r\n        ~LeakDetector();\r\n    };\r\n\r\n}\r\n// end catch_leak_detector.h\r\n// Cpp files will be included in the single-header file here\r\n// start catch_approx.cpp\r\n\r\n#include <cmath>\r\n#include <limits>\r\n\r\nnamespace {\r\n\r\n// Performs equivalent check of std::fabs(lhs - rhs) <= margin\r\n// But without the subtraction to allow for INFINITY in comparison\r\nbool marginComparison(double lhs, double rhs, double margin) {\r\n    return (lhs + margin >= rhs) && (rhs + margin >= lhs);\r\n}\r\n\r\n}\r\n\r\nnamespace Catch {\r\nnamespace Detail {\r\n\r\n    Approx::Approx ( double value )\r\n    :   m_epsilon( std::numeric_limits<float>::epsilon()*100 ),\r\n        m_margin( 0.0 ),\r\n        m_scale( 0.0 ),\r\n        m_value( value )\r\n    {}\r\n\r\n    Approx Approx::custom() {\r\n        return Approx( 0 );\r\n    }\r\n\r\n    Approx Approx::operator-() const {\r\n        auto temp(*this);\r\n        temp.m_value = -temp.m_value;\r\n        return temp;\r\n    }\r\n\r\n    std::string Approx::toString() const {\r\n        ReusableStringStream rss;\r\n        rss << \"Approx( \" << ::Catch::Detail::stringify( m_value ) << \" )\";\r\n        return rss.str();\r\n    }\r\n\r\n    bool Approx::equalityComparisonImpl(const double other) const {\r\n        // First try with fixed margin, then compute margin based on epsilon, scale and Approx's value\r\n        // Thanks to Richard Harris for his help refining the scaled margin value\r\n        return marginComparison(m_value, other, m_margin) || marginComparison(m_value, other, m_epsilon * (m_scale + std::fabs(m_value)));\r\n    }\r\n\r\n    void Approx::setMargin(double margin) {\r\n        CATCH_ENFORCE(margin >= 0,\r\n            \"Invalid Approx::margin: \" << margin << '.'\r\n            << \" Approx::Margin has to be non-negative.\");\r\n        m_margin = margin;\r\n    }\r\n\r\n    void Approx::setEpsilon(double epsilon) {\r\n        CATCH_ENFORCE(epsilon >= 0 && epsilon <= 1.0,\r\n            \"Invalid Approx::epsilon: \" << epsilon << '.'\r\n            << \" Approx::epsilon has to be in [0, 1]\");\r\n        m_epsilon = epsilon;\r\n    }\r\n\r\n} // end namespace Detail\r\n\r\nnamespace literals {\r\n    Detail::Approx operator \"\" _a(long double val) {\r\n        return Detail::Approx(val);\r\n    }\r\n    Detail::Approx operator \"\" _a(unsigned long long val) {\r\n        return Detail::Approx(val);\r\n    }\r\n} // end namespace literals\r\n\r\nstd::string StringMaker<Catch::Detail::Approx>::convert(Catch::Detail::Approx const& value) {\r\n    return value.toString();\r\n}\r\n\r\n} // end namespace Catch\r\n// end catch_approx.cpp\r\n// start catch_assertionhandler.cpp\r\n\r\n// start catch_debugger.h\r\n\r\nnamespace Catch {\r\n    bool isDebuggerActive();\r\n}\r\n\r\n#ifdef CATCH_PLATFORM_MAC\r\n\r\n    #define CATCH_TRAP() __asm__(\"int $3\\n\" : : ) /* NOLINT */\r\n\r\n#elif defined(CATCH_PLATFORM_LINUX)\r\n    // If we can use inline assembler, do it because this allows us to break\r\n    // directly at the location of the failing check instead of breaking inside\r\n    // raise() called from it, i.e. one stack frame below.\r\n    #if defined(__GNUC__) && (defined(__i386) || defined(__x86_64))\r\n        #define CATCH_TRAP() asm volatile (\"int $3\") /* NOLINT */\r\n    #else // Fall back to the generic way.\r\n        #include <signal.h>\r\n\r\n        #define CATCH_TRAP() raise(SIGTRAP)\r\n    #endif\r\n#elif defined(_MSC_VER)\r\n    #define CATCH_TRAP() __debugbreak()\r\n#elif defined(__MINGW32__)\r\n    extern \"C\" __declspec(dllimport) void __stdcall DebugBreak();\r\n    #define CATCH_TRAP() DebugBreak()\r\n#endif\r\n\r\n#ifdef CATCH_TRAP\r\n    #define CATCH_BREAK_INTO_DEBUGGER() []{ if( Catch::isDebuggerActive() ) { CATCH_TRAP(); } }()\r\n#else\r\n    #define CATCH_BREAK_INTO_DEBUGGER() []{}()\r\n#endif\r\n\r\n// end catch_debugger.h\r\n// start catch_run_context.h\r\n\r\n// start catch_fatal_condition.h\r\n\r\n// start catch_windows_h_proxy.h\r\n\r\n\r\n#if defined(CATCH_PLATFORM_WINDOWS)\r\n\r\n#if !defined(NOMINMAX) && !defined(CATCH_CONFIG_NO_NOMINMAX)\r\n#  define CATCH_DEFINED_NOMINMAX\r\n#  define NOMINMAX\r\n#endif\r\n#if !defined(WIN32_LEAN_AND_MEAN) && !defined(CATCH_CONFIG_NO_WIN32_LEAN_AND_MEAN)\r\n#  define CATCH_DEFINED_WIN32_LEAN_AND_MEAN\r\n#  define WIN32_LEAN_AND_MEAN\r\n#endif\r\n\r\n#ifdef __AFXDLL\r\n#include <AfxWin.h>\r\n#else\r\n#include <windows.h>\r\n#endif\r\n\r\n#ifdef CATCH_DEFINED_NOMINMAX\r\n#  undef NOMINMAX\r\n#endif\r\n#ifdef CATCH_DEFINED_WIN32_LEAN_AND_MEAN\r\n#  undef WIN32_LEAN_AND_MEAN\r\n#endif\r\n\r\n#endif // defined(CATCH_PLATFORM_WINDOWS)\r\n\r\n// end catch_windows_h_proxy.h\r\n#if defined( CATCH_CONFIG_WINDOWS_SEH )\r\n\r\nnamespace Catch {\r\n\r\n    struct FatalConditionHandler {\r\n\r\n        static LONG CALLBACK handleVectoredException(PEXCEPTION_POINTERS ExceptionInfo);\r\n        FatalConditionHandler();\r\n        static void reset();\r\n        ~FatalConditionHandler();\r\n\r\n    private:\r\n        static bool isSet;\r\n        static ULONG guaranteeSize;\r\n        static PVOID exceptionHandlerHandle;\r\n    };\r\n\r\n} // namespace Catch\r\n\r\n#elif defined ( CATCH_CONFIG_POSIX_SIGNALS )\r\n\r\n#include <signal.h>\r\n\r\nnamespace Catch {\r\n\r\n    struct FatalConditionHandler {\r\n\r\n        static bool isSet;\r\n        static struct sigaction oldSigActions[];\r\n        static stack_t oldSigStack;\r\n        static char altStackMem[];\r\n\r\n        static void handleSignal( int sig );\r\n\r\n        FatalConditionHandler();\r\n        ~FatalConditionHandler();\r\n        static void reset();\r\n    };\r\n\r\n} // namespace Catch\r\n\r\n#else\r\n\r\nnamespace Catch {\r\n    struct FatalConditionHandler {\r\n        void reset();\r\n    };\r\n}\r\n\r\n#endif\r\n\r\n// end catch_fatal_condition.h\r\n#include <string>\r\n\r\nnamespace Catch {\r\n\r\n    struct IMutableContext;\r\n\r\n    ///////////////////////////////////////////////////////////////////////////\r\n\r\n    class RunContext : public IResultCapture, public IRunner {\r\n\r\n    public:\r\n        RunContext( RunContext const& ) = delete;\r\n        RunContext& operator =( RunContext const& ) = delete;\r\n\r\n        explicit RunContext( IConfigPtr const& _config, IStreamingReporterPtr&& reporter );\r\n\r\n        ~RunContext() override;\r\n\r\n        void testGroupStarting( std::string const& testSpec, std::size_t groupIndex, std::size_t groupsCount );\r\n        void testGroupEnded( std::string const& testSpec, Totals const& totals, std::size_t groupIndex, std::size_t groupsCount );\r\n\r\n        Totals runTest(TestCase const& testCase);\r\n\r\n        IConfigPtr config() const;\r\n        IStreamingReporter& reporter() const;\r\n\r\n    public: // IResultCapture\r\n\r\n        // Assertion handlers\r\n        void handleExpr\r\n                (   AssertionInfo const& info,\r\n                    ITransientExpression const& expr,\r\n                    AssertionReaction& reaction ) override;\r\n        void handleMessage\r\n                (   AssertionInfo const& info,\r\n                    ResultWas::OfType resultType,\r\n                    StringRef const& message,\r\n                    AssertionReaction& reaction ) override;\r\n        void handleUnexpectedExceptionNotThrown\r\n                (   AssertionInfo const& info,\r\n                    AssertionReaction& reaction ) override;\r\n        void handleUnexpectedInflightException\r\n                (   AssertionInfo const& info,\r\n                    std::string const& message,\r\n                    AssertionReaction& reaction ) override;\r\n        void handleIncomplete\r\n                (   AssertionInfo const& info ) override;\r\n        void handleNonExpr\r\n                (   AssertionInfo const &info,\r\n                    ResultWas::OfType resultType,\r\n                    AssertionReaction &reaction ) override;\r\n\r\n        bool sectionStarted( SectionInfo const& sectionInfo, Counts& assertions ) override;\r\n\r\n        void sectionEnded( SectionEndInfo const& endInfo ) override;\r\n        void sectionEndedEarly( SectionEndInfo const& endInfo ) override;\r\n\r\n        auto acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker& override;\r\n\r\n        void benchmarkStarting( BenchmarkInfo const& info ) override;\r\n        void benchmarkEnded( BenchmarkStats const& stats ) override;\r\n\r\n        void pushScopedMessage( MessageInfo const& message ) override;\r\n        void popScopedMessage( MessageInfo const& message ) override;\r\n\r\n        void emplaceUnscopedMessage( MessageBuilder const& builder ) override;\r\n\r\n        std::string getCurrentTestName() const override;\r\n\r\n        const AssertionResult* getLastResult() const override;\r\n\r\n        void exceptionEarlyReported() override;\r\n\r\n        void handleFatalErrorCondition( StringRef message ) override;\r\n\r\n        bool lastAssertionPassed() override;\r\n\r\n        void assertionPassed() override;\r\n\r\n    public:\r\n        // !TBD We need to do this another way!\r\n        bool aborting() const final;\r\n\r\n    private:\r\n\r\n        void runCurrentTest( std::string& redirectedCout, std::string& redirectedCerr );\r\n        void invokeActiveTestCase();\r\n\r\n        void resetAssertionInfo();\r\n        bool testForMissingAssertions( Counts& assertions );\r\n\r\n        void assertionEnded( AssertionResult const& result );\r\n        void reportExpr\r\n                (   AssertionInfo const &info,\r\n                    ResultWas::OfType resultType,\r\n                    ITransientExpression const *expr,\r\n                    bool negated );\r\n\r\n        void populateReaction( AssertionReaction& reaction );\r\n\r\n    private:\r\n\r\n        void handleUnfinishedSections();\r\n\r\n        TestRunInfo m_runInfo;\r\n        IMutableContext& m_context;\r\n        TestCase const* m_activeTestCase = nullptr;\r\n        ITracker* m_testCaseTracker = nullptr;\r\n        Option<AssertionResult> m_lastResult;\r\n\r\n        IConfigPtr m_config;\r\n        Totals m_totals;\r\n        IStreamingReporterPtr m_reporter;\r\n        std::vector<MessageInfo> m_messages;\r\n        std::vector<ScopedMessage> m_messageScopes; /* Keeps owners of so-called unscoped messages. */\r\n        AssertionInfo m_lastAssertionInfo;\r\n        std::vector<SectionEndInfo> m_unfinishedSections;\r\n        std::vector<ITracker*> m_activeSections;\r\n        TrackerContext m_trackerContext;\r\n        bool m_lastAssertionPassed = false;\r\n        bool m_shouldReportUnexpected = true;\r\n        bool m_includeSuccessfulResults;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_run_context.h\r\nnamespace Catch {\r\n\r\n    namespace {\r\n        auto operator <<( std::ostream& os, ITransientExpression const& expr ) -> std::ostream& {\r\n            expr.streamReconstructedExpression( os );\r\n            return os;\r\n        }\r\n    }\r\n\r\n    LazyExpression::LazyExpression( bool isNegated )\r\n    :   m_isNegated( isNegated )\r\n    {}\r\n\r\n    LazyExpression::LazyExpression( LazyExpression const& other ) : m_isNegated( other.m_isNegated ) {}\r\n\r\n    LazyExpression::operator bool() const {\r\n        return m_transientExpression != nullptr;\r\n    }\r\n\r\n    auto operator << ( std::ostream& os, LazyExpression const& lazyExpr ) -> std::ostream& {\r\n        if( lazyExpr.m_isNegated )\r\n            os << \"!\";\r\n\r\n        if( lazyExpr ) {\r\n            if( lazyExpr.m_isNegated && lazyExpr.m_transientExpression->isBinaryExpression() )\r\n                os << \"(\" << *lazyExpr.m_transientExpression << \")\";\r\n            else\r\n                os << *lazyExpr.m_transientExpression;\r\n        }\r\n        else {\r\n            os << \"{** error - unchecked empty expression requested **}\";\r\n        }\r\n        return os;\r\n    }\r\n\r\n    AssertionHandler::AssertionHandler\r\n        (   StringRef const& macroName,\r\n            SourceLineInfo const& lineInfo,\r\n            StringRef capturedExpression,\r\n            ResultDisposition::Flags resultDisposition )\r\n    :   m_assertionInfo{ macroName, lineInfo, capturedExpression, resultDisposition },\r\n        m_resultCapture( getResultCapture() )\r\n    {}\r\n\r\n    void AssertionHandler::handleExpr( ITransientExpression const& expr ) {\r\n        m_resultCapture.handleExpr( m_assertionInfo, expr, m_reaction );\r\n    }\r\n    void AssertionHandler::handleMessage(ResultWas::OfType resultType, StringRef const& message) {\r\n        m_resultCapture.handleMessage( m_assertionInfo, resultType, message, m_reaction );\r\n    }\r\n\r\n    auto AssertionHandler::allowThrows() const -> bool {\r\n        return getCurrentContext().getConfig()->allowThrows();\r\n    }\r\n\r\n    void AssertionHandler::complete() {\r\n        setCompleted();\r\n        if( m_reaction.shouldDebugBreak ) {\r\n\r\n            // If you find your debugger stopping you here then go one level up on the\r\n            // call-stack for the code that caused it (typically a failed assertion)\r\n\r\n            // (To go back to the test and change execution, jump over the throw, next)\r\n            CATCH_BREAK_INTO_DEBUGGER();\r\n        }\r\n        if (m_reaction.shouldThrow) {\r\n#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS)\r\n            throw Catch::TestFailureException();\r\n#else\r\n            CATCH_ERROR( \"Test failure requires aborting test!\" );\r\n#endif\r\n        }\r\n    }\r\n    void AssertionHandler::setCompleted() {\r\n        m_completed = true;\r\n    }\r\n\r\n    void AssertionHandler::handleUnexpectedInflightException() {\r\n        m_resultCapture.handleUnexpectedInflightException( m_assertionInfo, Catch::translateActiveException(), m_reaction );\r\n    }\r\n\r\n    void AssertionHandler::handleExceptionThrownAsExpected() {\r\n        m_resultCapture.handleNonExpr(m_assertionInfo, ResultWas::Ok, m_reaction);\r\n    }\r\n    void AssertionHandler::handleExceptionNotThrownAsExpected() {\r\n        m_resultCapture.handleNonExpr(m_assertionInfo, ResultWas::Ok, m_reaction);\r\n    }\r\n\r\n    void AssertionHandler::handleUnexpectedExceptionNotThrown() {\r\n        m_resultCapture.handleUnexpectedExceptionNotThrown( m_assertionInfo, m_reaction );\r\n    }\r\n\r\n    void AssertionHandler::handleThrowingCallSkipped() {\r\n        m_resultCapture.handleNonExpr(m_assertionInfo, ResultWas::Ok, m_reaction);\r\n    }\r\n\r\n    // This is the overload that takes a string and infers the Equals matcher from it\r\n    // The more general overload, that takes any string matcher, is in catch_capture_matchers.cpp\r\n    void handleExceptionMatchExpr( AssertionHandler& handler, std::string const& str, StringRef const& matcherString  ) {\r\n        handleExceptionMatchExpr( handler, Matchers::Equals( str ), matcherString );\r\n    }\r\n\r\n} // namespace Catch\r\n// end catch_assertionhandler.cpp\r\n// start catch_assertionresult.cpp\r\n\r\nnamespace Catch {\r\n    AssertionResultData::AssertionResultData(ResultWas::OfType _resultType, LazyExpression const & _lazyExpression):\r\n        lazyExpression(_lazyExpression),\r\n        resultType(_resultType) {}\r\n\r\n    std::string AssertionResultData::reconstructExpression() const {\r\n\r\n        if( reconstructedExpression.empty() ) {\r\n            if( lazyExpression ) {\r\n                ReusableStringStream rss;\r\n                rss << lazyExpression;\r\n                reconstructedExpression = rss.str();\r\n            }\r\n        }\r\n        return reconstructedExpression;\r\n    }\r\n\r\n    AssertionResult::AssertionResult( AssertionInfo const& info, AssertionResultData const& data )\r\n    :   m_info( info ),\r\n        m_resultData( data )\r\n    {}\r\n\r\n    // Result was a success\r\n    bool AssertionResult::succeeded() const {\r\n        return Catch::isOk( m_resultData.resultType );\r\n    }\r\n\r\n    // Result was a success, or failure is suppressed\r\n    bool AssertionResult::isOk() const {\r\n        return Catch::isOk( m_resultData.resultType ) || shouldSuppressFailure( m_info.resultDisposition );\r\n    }\r\n\r\n    ResultWas::OfType AssertionResult::getResultType() const {\r\n        return m_resultData.resultType;\r\n    }\r\n\r\n    bool AssertionResult::hasExpression() const {\r\n        return m_info.capturedExpression[0] != 0;\r\n    }\r\n\r\n    bool AssertionResult::hasMessage() const {\r\n        return !m_resultData.message.empty();\r\n    }\r\n\r\n    std::string AssertionResult::getExpression() const {\r\n        if( isFalseTest( m_info.resultDisposition ) )\r\n            return \"!(\" + m_info.capturedExpression + \")\";\r\n        else\r\n            return m_info.capturedExpression;\r\n    }\r\n\r\n    std::string AssertionResult::getExpressionInMacro() const {\r\n        std::string expr;\r\n        if( m_info.macroName[0] == 0 )\r\n            expr = m_info.capturedExpression;\r\n        else {\r\n            expr.reserve( m_info.macroName.size() + m_info.capturedExpression.size() + 4 );\r\n            expr += m_info.macroName;\r\n            expr += \"( \";\r\n            expr += m_info.capturedExpression;\r\n            expr += \" )\";\r\n        }\r\n        return expr;\r\n    }\r\n\r\n    bool AssertionResult::hasExpandedExpression() const {\r\n        return hasExpression() && getExpandedExpression() != getExpression();\r\n    }\r\n\r\n    std::string AssertionResult::getExpandedExpression() const {\r\n        std::string expr = m_resultData.reconstructExpression();\r\n        return expr.empty()\r\n                ? getExpression()\r\n                : expr;\r\n    }\r\n\r\n    std::string AssertionResult::getMessage() const {\r\n        return m_resultData.message;\r\n    }\r\n    SourceLineInfo AssertionResult::getSourceInfo() const {\r\n        return m_info.lineInfo;\r\n    }\r\n\r\n    StringRef AssertionResult::getTestMacroName() const {\r\n        return m_info.macroName;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_assertionresult.cpp\r\n// start catch_benchmark.cpp\r\n\r\nnamespace Catch {\r\n\r\n    auto BenchmarkLooper::getResolution() -> uint64_t {\r\n        return getEstimatedClockResolution() * getCurrentContext().getConfig()->benchmarkResolutionMultiple();\r\n    }\r\n\r\n    void BenchmarkLooper::reportStart() {\r\n        getResultCapture().benchmarkStarting( { m_name } );\r\n    }\r\n    auto BenchmarkLooper::needsMoreIterations() -> bool {\r\n        auto elapsed = m_timer.getElapsedNanoseconds();\r\n\r\n        // Exponentially increasing iterations until we're confident in our timer resolution\r\n        if( elapsed < m_resolution ) {\r\n            m_iterationsToRun *= 10;\r\n            return true;\r\n        }\r\n\r\n        getResultCapture().benchmarkEnded( { { m_name }, m_count, elapsed } );\r\n        return false;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_benchmark.cpp\r\n// start catch_capture_matchers.cpp\r\n\r\nnamespace Catch {\r\n\r\n    using StringMatcher = Matchers::Impl::MatcherBase<std::string>;\r\n\r\n    // This is the general overload that takes a any string matcher\r\n    // There is another overload, in catch_assertionhandler.h/.cpp, that only takes a string and infers\r\n    // the Equals matcher (so the header does not mention matchers)\r\n    void handleExceptionMatchExpr( AssertionHandler& handler, StringMatcher const& matcher, StringRef const& matcherString  ) {\r\n        std::string exceptionMessage = Catch::translateActiveException();\r\n        MatchExpr<std::string, StringMatcher const&> expr( exceptionMessage, matcher, matcherString );\r\n        handler.handleExpr( expr );\r\n    }\r\n\r\n} // namespace Catch\r\n// end catch_capture_matchers.cpp\r\n// start catch_commandline.cpp\r\n\r\n// start catch_commandline.h\r\n\r\n// start catch_clara.h\r\n\r\n// Use Catch's value for console width (store Clara's off to the side, if present)\r\n#ifdef CLARA_CONFIG_CONSOLE_WIDTH\r\n#define CATCH_TEMP_CLARA_CONFIG_CONSOLE_WIDTH CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH\r\n#undef CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH\r\n#endif\r\n#define CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH CATCH_CONFIG_CONSOLE_WIDTH-1\r\n\r\n#ifdef __clang__\r\n#pragma clang diagnostic push\r\n#pragma clang diagnostic ignored \"-Wweak-vtables\"\r\n#pragma clang diagnostic ignored \"-Wexit-time-destructors\"\r\n#pragma clang diagnostic ignored \"-Wshadow\"\r\n#endif\r\n\r\n// start clara.hpp\r\n// Copyright 2017 Two Blue Cubes Ltd. All rights reserved.\r\n//\r\n// Distributed under the Boost Software License, Version 1.0. (See accompanying\r\n// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)\r\n//\r\n// See https://github.com/philsquared/Clara for more details\r\n\r\n// Clara v1.1.5\r\n\r\n\r\n#ifndef CATCH_CLARA_CONFIG_CONSOLE_WIDTH\r\n#define CATCH_CLARA_CONFIG_CONSOLE_WIDTH 80\r\n#endif\r\n\r\n#ifndef CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH\r\n#define CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH CATCH_CLARA_CONFIG_CONSOLE_WIDTH\r\n#endif\r\n\r\n#ifndef CLARA_CONFIG_OPTIONAL_TYPE\r\n#ifdef __has_include\r\n#if __has_include(<optional>) && __cplusplus >= 201703L\r\n#include <optional>\r\n#define CLARA_CONFIG_OPTIONAL_TYPE std::optional\r\n#endif\r\n#endif\r\n#endif\r\n\r\n// ----------- #included from clara_textflow.hpp -----------\r\n\r\n// TextFlowCpp\r\n//\r\n// A single-header library for wrapping and laying out basic text, by Phil Nash\r\n//\r\n// Distributed under the Boost Software License, Version 1.0. (See accompanying\r\n// file LICENSE.txt or copy at http://www.boost.org/LICENSE_1_0.txt)\r\n//\r\n// This project is hosted at https://github.com/philsquared/textflowcpp\r\n\r\n\r\n#include <cassert>\r\n#include <ostream>\r\n#include <sstream>\r\n#include <vector>\r\n\r\n#ifndef CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH\r\n#define CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH 80\r\n#endif\r\n\r\nnamespace Catch {\r\nnamespace clara {\r\nnamespace TextFlow {\r\n\r\ninline auto isWhitespace(char c) -> bool {\r\n\tstatic std::string chars = \" \\t\\n\\r\";\r\n\treturn chars.find(c) != std::string::npos;\r\n}\r\ninline auto isBreakableBefore(char c) -> bool {\r\n\tstatic std::string chars = \"[({<|\";\r\n\treturn chars.find(c) != std::string::npos;\r\n}\r\ninline auto isBreakableAfter(char c) -> bool {\r\n\tstatic std::string chars = \"])}>.,:;*+-=&/\\\\\";\r\n\treturn chars.find(c) != std::string::npos;\r\n}\r\n\r\nclass Columns;\r\n\r\nclass Column {\r\n\tstd::vector<std::string> m_strings;\r\n\tsize_t m_width = CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH;\r\n\tsize_t m_indent = 0;\r\n\tsize_t m_initialIndent = std::string::npos;\r\n\r\npublic:\r\n\tclass iterator {\r\n\t\tfriend Column;\r\n\r\n\t\tColumn const& m_column;\r\n\t\tsize_t m_stringIndex = 0;\r\n\t\tsize_t m_pos = 0;\r\n\r\n\t\tsize_t m_len = 0;\r\n\t\tsize_t m_end = 0;\r\n\t\tbool m_suffix = false;\r\n\r\n\t\titerator(Column const& column, size_t stringIndex)\r\n\t\t\t: m_column(column),\r\n\t\t\tm_stringIndex(stringIndex) {}\r\n\r\n\t\tauto line() const -> std::string const& { return m_column.m_strings[m_stringIndex]; }\r\n\r\n\t\tauto isBoundary(size_t at) const -> bool {\r\n\t\t\tassert(at > 0);\r\n\t\t\tassert(at <= line().size());\r\n\r\n\t\t\treturn at == line().size() ||\r\n\t\t\t\t(isWhitespace(line()[at]) && !isWhitespace(line()[at - 1])) ||\r\n\t\t\t\tisBreakableBefore(line()[at]) ||\r\n\t\t\t\tisBreakableAfter(line()[at - 1]);\r\n\t\t}\r\n\r\n\t\tvoid calcLength() {\r\n\t\t\tassert(m_stringIndex < m_column.m_strings.size());\r\n\r\n\t\t\tm_suffix = false;\r\n\t\t\tauto width = m_column.m_width - indent();\r\n\t\t\tm_end = m_pos;\r\n\t\t\twhile (m_end < line().size() && line()[m_end] != '\\n')\r\n\t\t\t\t++m_end;\r\n\r\n\t\t\tif (m_end < m_pos + width) {\r\n\t\t\t\tm_len = m_end - m_pos;\r\n\t\t\t} else {\r\n\t\t\t\tsize_t len = width;\r\n\t\t\t\twhile (len > 0 && !isBoundary(m_pos + len))\r\n\t\t\t\t\t--len;\r\n\t\t\t\twhile (len > 0 && isWhitespace(line()[m_pos + len - 1]))\r\n\t\t\t\t\t--len;\r\n\r\n\t\t\t\tif (len > 0) {\r\n\t\t\t\t\tm_len = len;\r\n\t\t\t\t} else {\r\n\t\t\t\t\tm_suffix = true;\r\n\t\t\t\t\tm_len = width - 1;\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\tauto indent() const -> size_t {\r\n\t\t\tauto initial = m_pos == 0 && m_stringIndex == 0 ? m_column.m_initialIndent : std::string::npos;\r\n\t\t\treturn initial == std::string::npos ? m_column.m_indent : initial;\r\n\t\t}\r\n\r\n\t\tauto addIndentAndSuffix(std::string const &plain) const -> std::string {\r\n\t\t\treturn std::string(indent(), ' ') + (m_suffix ? plain + \"-\" : plain);\r\n\t\t}\r\n\r\n\tpublic:\r\n\t\tusing difference_type = std::ptrdiff_t;\r\n\t\tusing value_type = std::string;\r\n\t\tusing pointer = value_type * ;\r\n\t\tusing reference = value_type & ;\r\n\t\tusing iterator_category = std::forward_iterator_tag;\r\n\r\n\t\texplicit iterator(Column const& column) : m_column(column) {\r\n\t\t\tassert(m_column.m_width > m_column.m_indent);\r\n\t\t\tassert(m_column.m_initialIndent == std::string::npos || m_column.m_width > m_column.m_initialIndent);\r\n\t\t\tcalcLength();\r\n\t\t\tif (m_len == 0)\r\n\t\t\t\tm_stringIndex++; // Empty string\r\n\t\t}\r\n\r\n\t\tauto operator *() const -> std::string {\r\n\t\t\tassert(m_stringIndex < m_column.m_strings.size());\r\n\t\t\tassert(m_pos <= m_end);\r\n\t\t\treturn addIndentAndSuffix(line().substr(m_pos, m_len));\r\n\t\t}\r\n\r\n\t\tauto operator ++() -> iterator& {\r\n\t\t\tm_pos += m_len;\r\n\t\t\tif (m_pos < line().size() && line()[m_pos] == '\\n')\r\n\t\t\t\tm_pos += 1;\r\n\t\t\telse\r\n\t\t\t\twhile (m_pos < line().size() && isWhitespace(line()[m_pos]))\r\n\t\t\t\t\t++m_pos;\r\n\r\n\t\t\tif (m_pos == line().size()) {\r\n\t\t\t\tm_pos = 0;\r\n\t\t\t\t++m_stringIndex;\r\n\t\t\t}\r\n\t\t\tif (m_stringIndex < m_column.m_strings.size())\r\n\t\t\t\tcalcLength();\r\n\t\t\treturn *this;\r\n\t\t}\r\n\t\tauto operator ++(int) -> iterator {\r\n\t\t\titerator prev(*this);\r\n\t\t\toperator++();\r\n\t\t\treturn prev;\r\n\t\t}\r\n\r\n\t\tauto operator ==(iterator const& other) const -> bool {\r\n\t\t\treturn\r\n\t\t\t\tm_pos == other.m_pos &&\r\n\t\t\t\tm_stringIndex == other.m_stringIndex &&\r\n\t\t\t\t&m_column == &other.m_column;\r\n\t\t}\r\n\t\tauto operator !=(iterator const& other) const -> bool {\r\n\t\t\treturn !operator==(other);\r\n\t\t}\r\n\t};\r\n\tusing const_iterator = iterator;\r\n\r\n\texplicit Column(std::string const& text) { m_strings.push_back(text); }\r\n\r\n\tauto width(size_t newWidth) -> Column& {\r\n\t\tassert(newWidth > 0);\r\n\t\tm_width = newWidth;\r\n\t\treturn *this;\r\n\t}\r\n\tauto indent(size_t newIndent) -> Column& {\r\n\t\tm_indent = newIndent;\r\n\t\treturn *this;\r\n\t}\r\n\tauto initialIndent(size_t newIndent) -> Column& {\r\n\t\tm_initialIndent = newIndent;\r\n\t\treturn *this;\r\n\t}\r\n\r\n\tauto width() const -> size_t { return m_width; }\r\n\tauto begin() const -> iterator { return iterator(*this); }\r\n\tauto end() const -> iterator { return { *this, m_strings.size() }; }\r\n\r\n\tinline friend std::ostream& operator << (std::ostream& os, Column const& col) {\r\n\t\tbool first = true;\r\n\t\tfor (auto line : col) {\r\n\t\t\tif (first)\r\n\t\t\t\tfirst = false;\r\n\t\t\telse\r\n\t\t\t\tos << \"\\n\";\r\n\t\t\tos << line;\r\n\t\t}\r\n\t\treturn os;\r\n\t}\r\n\r\n\tauto operator + (Column const& other)->Columns;\r\n\r\n\tauto toString() const -> std::string {\r\n\t\tstd::ostringstream oss;\r\n\t\toss << *this;\r\n\t\treturn oss.str();\r\n\t}\r\n};\r\n\r\nclass Spacer : public Column {\r\n\r\npublic:\r\n\texplicit Spacer(size_t spaceWidth) : Column(\"\") {\r\n\t\twidth(spaceWidth);\r\n\t}\r\n};\r\n\r\nclass Columns {\r\n\tstd::vector<Column> m_columns;\r\n\r\npublic:\r\n\r\n\tclass iterator {\r\n\t\tfriend Columns;\r\n\t\tstruct EndTag {};\r\n\r\n\t\tstd::vector<Column> const& m_columns;\r\n\t\tstd::vector<Column::iterator> m_iterators;\r\n\t\tsize_t m_activeIterators;\r\n\r\n\t\titerator(Columns const& columns, EndTag)\r\n\t\t\t: m_columns(columns.m_columns),\r\n\t\t\tm_activeIterators(0) {\r\n\t\t\tm_iterators.reserve(m_columns.size());\r\n\r\n\t\t\tfor (auto const& col : m_columns)\r\n\t\t\t\tm_iterators.push_back(col.end());\r\n\t\t}\r\n\r\n\tpublic:\r\n\t\tusing difference_type = std::ptrdiff_t;\r\n\t\tusing value_type = std::string;\r\n\t\tusing pointer = value_type * ;\r\n\t\tusing reference = value_type & ;\r\n\t\tusing iterator_category = std::forward_iterator_tag;\r\n\r\n\t\texplicit iterator(Columns const& columns)\r\n\t\t\t: m_columns(columns.m_columns),\r\n\t\t\tm_activeIterators(m_columns.size()) {\r\n\t\t\tm_iterators.reserve(m_columns.size());\r\n\r\n\t\t\tfor (auto const& col : m_columns)\r\n\t\t\t\tm_iterators.push_back(col.begin());\r\n\t\t}\r\n\r\n\t\tauto operator ==(iterator const& other) const -> bool {\r\n\t\t\treturn m_iterators == other.m_iterators;\r\n\t\t}\r\n\t\tauto operator !=(iterator const& other) const -> bool {\r\n\t\t\treturn m_iterators != other.m_iterators;\r\n\t\t}\r\n\t\tauto operator *() const -> std::string {\r\n\t\t\tstd::string row, padding;\r\n\r\n\t\t\tfor (size_t i = 0; i < m_columns.size(); ++i) {\r\n\t\t\t\tauto width = m_columns[i].width();\r\n\t\t\t\tif (m_iterators[i] != m_columns[i].end()) {\r\n\t\t\t\t\tstd::string col = *m_iterators[i];\r\n\t\t\t\t\trow += padding + col;\r\n\t\t\t\t\tif (col.size() < width)\r\n\t\t\t\t\t\tpadding = std::string(width - col.size(), ' ');\r\n\t\t\t\t\telse\r\n\t\t\t\t\t\tpadding = \"\";\r\n\t\t\t\t} else {\r\n\t\t\t\t\tpadding += std::string(width, ' ');\r\n\t\t\t\t}\r\n\t\t\t}\r\n\t\t\treturn row;\r\n\t\t}\r\n\t\tauto operator ++() -> iterator& {\r\n\t\t\tfor (size_t i = 0; i < m_columns.size(); ++i) {\r\n\t\t\t\tif (m_iterators[i] != m_columns[i].end())\r\n\t\t\t\t\t++m_iterators[i];\r\n\t\t\t}\r\n\t\t\treturn *this;\r\n\t\t}\r\n\t\tauto operator ++(int) -> iterator {\r\n\t\t\titerator prev(*this);\r\n\t\t\toperator++();\r\n\t\t\treturn prev;\r\n\t\t}\r\n\t};\r\n\tusing const_iterator = iterator;\r\n\r\n\tauto begin() const -> iterator { return iterator(*this); }\r\n\tauto end() const -> iterator { return { *this, iterator::EndTag() }; }\r\n\r\n\tauto operator += (Column const& col) -> Columns& {\r\n\t\tm_columns.push_back(col);\r\n\t\treturn *this;\r\n\t}\r\n\tauto operator + (Column const& col) -> Columns {\r\n\t\tColumns combined = *this;\r\n\t\tcombined += col;\r\n\t\treturn combined;\r\n\t}\r\n\r\n\tinline friend std::ostream& operator << (std::ostream& os, Columns const& cols) {\r\n\r\n\t\tbool first = true;\r\n\t\tfor (auto line : cols) {\r\n\t\t\tif (first)\r\n\t\t\t\tfirst = false;\r\n\t\t\telse\r\n\t\t\t\tos << \"\\n\";\r\n\t\t\tos << line;\r\n\t\t}\r\n\t\treturn os;\r\n\t}\r\n\r\n\tauto toString() const -> std::string {\r\n\t\tstd::ostringstream oss;\r\n\t\toss << *this;\r\n\t\treturn oss.str();\r\n\t}\r\n};\r\n\r\ninline auto Column::operator + (Column const& other) -> Columns {\r\n\tColumns cols;\r\n\tcols += *this;\r\n\tcols += other;\r\n\treturn cols;\r\n}\r\n}\r\n\r\n}\r\n}\r\n\r\n// ----------- end of #include from clara_textflow.hpp -----------\r\n// ........... back in clara.hpp\r\n\r\n#include <cctype>\r\n#include <string>\r\n#include <memory>\r\n#include <set>\r\n#include <algorithm>\r\n\r\n#if !defined(CATCH_PLATFORM_WINDOWS) && ( defined(WIN32) || defined(__WIN32__) || defined(_WIN32) || defined(_MSC_VER) )\r\n#define CATCH_PLATFORM_WINDOWS\r\n#endif\r\n\r\nnamespace Catch { namespace clara {\r\nnamespace detail {\r\n\r\n    // Traits for extracting arg and return type of lambdas (for single argument lambdas)\r\n    template<typename L>\r\n    struct UnaryLambdaTraits : UnaryLambdaTraits<decltype( &L::operator() )> {};\r\n\r\n    template<typename ClassT, typename ReturnT, typename... Args>\r\n    struct UnaryLambdaTraits<ReturnT( ClassT::* )( Args... ) const> {\r\n        static const bool isValid = false;\r\n    };\r\n\r\n    template<typename ClassT, typename ReturnT, typename ArgT>\r\n    struct UnaryLambdaTraits<ReturnT( ClassT::* )( ArgT ) const> {\r\n        static const bool isValid = true;\r\n        using ArgType = typename std::remove_const<typename std::remove_reference<ArgT>::type>::type;\r\n        using ReturnType = ReturnT;\r\n    };\r\n\r\n    class TokenStream;\r\n\r\n    // Transport for raw args (copied from main args, or supplied via init list for testing)\r\n    class Args {\r\n        friend TokenStream;\r\n        std::string m_exeName;\r\n        std::vector<std::string> m_args;\r\n\r\n    public:\r\n        Args( int argc, char const* const* argv )\r\n            : m_exeName(argv[0]),\r\n              m_args(argv + 1, argv + argc) {}\r\n\r\n        Args( std::initializer_list<std::string> args )\r\n        :   m_exeName( *args.begin() ),\r\n            m_args( args.begin()+1, args.end() )\r\n        {}\r\n\r\n        auto exeName() const -> std::string {\r\n            return m_exeName;\r\n        }\r\n    };\r\n\r\n    // Wraps a token coming from a token stream. These may not directly correspond to strings as a single string\r\n    // may encode an option + its argument if the : or = form is used\r\n    enum class TokenType {\r\n        Option, Argument\r\n    };\r\n    struct Token {\r\n        TokenType type;\r\n        std::string token;\r\n    };\r\n\r\n    inline auto isOptPrefix( char c ) -> bool {\r\n        return c == '-'\r\n#ifdef CATCH_PLATFORM_WINDOWS\r\n            || c == '/'\r\n#endif\r\n        ;\r\n    }\r\n\r\n    // Abstracts iterators into args as a stream of tokens, with option arguments uniformly handled\r\n    class TokenStream {\r\n        using Iterator = std::vector<std::string>::const_iterator;\r\n        Iterator it;\r\n        Iterator itEnd;\r\n        std::vector<Token> m_tokenBuffer;\r\n\r\n        void loadBuffer() {\r\n            m_tokenBuffer.resize( 0 );\r\n\r\n            // Skip any empty strings\r\n            while( it != itEnd && it->empty() )\r\n                ++it;\r\n\r\n            if( it != itEnd ) {\r\n                auto const &next = *it;\r\n                if( isOptPrefix( next[0] ) ) {\r\n                    auto delimiterPos = next.find_first_of( \" :=\" );\r\n                    if( delimiterPos != std::string::npos ) {\r\n                        m_tokenBuffer.push_back( { TokenType::Option, next.substr( 0, delimiterPos ) } );\r\n                        m_tokenBuffer.push_back( { TokenType::Argument, next.substr( delimiterPos + 1 ) } );\r\n                    } else {\r\n                        if( next[1] != '-' && next.size() > 2 ) {\r\n                            std::string opt = \"- \";\r\n                            for( size_t i = 1; i < next.size(); ++i ) {\r\n                                opt[1] = next[i];\r\n                                m_tokenBuffer.push_back( { TokenType::Option, opt } );\r\n                            }\r\n                        } else {\r\n                            m_tokenBuffer.push_back( { TokenType::Option, next } );\r\n                        }\r\n                    }\r\n                } else {\r\n                    m_tokenBuffer.push_back( { TokenType::Argument, next } );\r\n                }\r\n            }\r\n        }\r\n\r\n    public:\r\n        explicit TokenStream( Args const &args ) : TokenStream( args.m_args.begin(), args.m_args.end() ) {}\r\n\r\n        TokenStream( Iterator it, Iterator itEnd ) : it( it ), itEnd( itEnd ) {\r\n            loadBuffer();\r\n        }\r\n\r\n        explicit operator bool() const {\r\n            return !m_tokenBuffer.empty() || it != itEnd;\r\n        }\r\n\r\n        auto count() const -> size_t { return m_tokenBuffer.size() + (itEnd - it); }\r\n\r\n        auto operator*() const -> Token {\r\n            assert( !m_tokenBuffer.empty() );\r\n            return m_tokenBuffer.front();\r\n        }\r\n\r\n        auto operator->() const -> Token const * {\r\n            assert( !m_tokenBuffer.empty() );\r\n            return &m_tokenBuffer.front();\r\n        }\r\n\r\n        auto operator++() -> TokenStream & {\r\n            if( m_tokenBuffer.size() >= 2 ) {\r\n                m_tokenBuffer.erase( m_tokenBuffer.begin() );\r\n            } else {\r\n                if( it != itEnd )\r\n                    ++it;\r\n                loadBuffer();\r\n            }\r\n            return *this;\r\n        }\r\n    };\r\n\r\n    class ResultBase {\r\n    public:\r\n        enum Type {\r\n            Ok, LogicError, RuntimeError\r\n        };\r\n\r\n    protected:\r\n        ResultBase( Type type ) : m_type( type ) {}\r\n        virtual ~ResultBase() = default;\r\n\r\n        virtual void enforceOk() const = 0;\r\n\r\n        Type m_type;\r\n    };\r\n\r\n    template<typename T>\r\n    class ResultValueBase : public ResultBase {\r\n    public:\r\n        auto value() const -> T const & {\r\n            enforceOk();\r\n            return m_value;\r\n        }\r\n\r\n    protected:\r\n        ResultValueBase( Type type ) : ResultBase( type ) {}\r\n\r\n        ResultValueBase( ResultValueBase const &other ) : ResultBase( other ) {\r\n            if( m_type == ResultBase::Ok )\r\n                new( &m_value ) T( other.m_value );\r\n        }\r\n\r\n        ResultValueBase( Type, T const &value ) : ResultBase( Ok ) {\r\n            new( &m_value ) T( value );\r\n        }\r\n\r\n        auto operator=( ResultValueBase const &other ) -> ResultValueBase & {\r\n            if( m_type == ResultBase::Ok )\r\n                m_value.~T();\r\n            ResultBase::operator=(other);\r\n            if( m_type == ResultBase::Ok )\r\n                new( &m_value ) T( other.m_value );\r\n            return *this;\r\n        }\r\n\r\n        ~ResultValueBase() override {\r\n            if( m_type == Ok )\r\n                m_value.~T();\r\n        }\r\n\r\n        union {\r\n            T m_value;\r\n        };\r\n    };\r\n\r\n    template<>\r\n    class ResultValueBase<void> : public ResultBase {\r\n    protected:\r\n        using ResultBase::ResultBase;\r\n    };\r\n\r\n    template<typename T = void>\r\n    class BasicResult : public ResultValueBase<T> {\r\n    public:\r\n        template<typename U>\r\n        explicit BasicResult( BasicResult<U> const &other )\r\n        :   ResultValueBase<T>( other.type() ),\r\n            m_errorMessage( other.errorMessage() )\r\n        {\r\n            assert( type() != ResultBase::Ok );\r\n        }\r\n\r\n        template<typename U>\r\n        static auto ok( U const &value ) -> BasicResult { return { ResultBase::Ok, value }; }\r\n        static auto ok() -> BasicResult { return { ResultBase::Ok }; }\r\n        static auto logicError( std::string const &message ) -> BasicResult { return { ResultBase::LogicError, message }; }\r\n        static auto runtimeError( std::string const &message ) -> BasicResult { return { ResultBase::RuntimeError, message }; }\r\n\r\n        explicit operator bool() const { return m_type == ResultBase::Ok; }\r\n        auto type() const -> ResultBase::Type { return m_type; }\r\n        auto errorMessage() const -> std::string { return m_errorMessage; }\r\n\r\n    protected:\r\n        void enforceOk() const override {\r\n\r\n            // Errors shouldn't reach this point, but if they do\r\n            // the actual error message will be in m_errorMessage\r\n            assert( m_type != ResultBase::LogicError );\r\n            assert( m_type != ResultBase::RuntimeError );\r\n            if( m_type != ResultBase::Ok )\r\n                std::abort();\r\n        }\r\n\r\n        std::string m_errorMessage; // Only populated if resultType is an error\r\n\r\n        BasicResult( ResultBase::Type type, std::string const &message )\r\n        :   ResultValueBase<T>(type),\r\n            m_errorMessage(message)\r\n        {\r\n            assert( m_type != ResultBase::Ok );\r\n        }\r\n\r\n        using ResultValueBase<T>::ResultValueBase;\r\n        using ResultBase::m_type;\r\n    };\r\n\r\n    enum class ParseResultType {\r\n        Matched, NoMatch, ShortCircuitAll, ShortCircuitSame\r\n    };\r\n\r\n    class ParseState {\r\n    public:\r\n\r\n        ParseState( ParseResultType type, TokenStream const &remainingTokens )\r\n        : m_type(type),\r\n          m_remainingTokens( remainingTokens )\r\n        {}\r\n\r\n        auto type() const -> ParseResultType { return m_type; }\r\n        auto remainingTokens() const -> TokenStream { return m_remainingTokens; }\r\n\r\n    private:\r\n        ParseResultType m_type;\r\n        TokenStream m_remainingTokens;\r\n    };\r\n\r\n    using Result = BasicResult<void>;\r\n    using ParserResult = BasicResult<ParseResultType>;\r\n    using InternalParseResult = BasicResult<ParseState>;\r\n\r\n    struct HelpColumns {\r\n        std::string left;\r\n        std::string right;\r\n    };\r\n\r\n    template<typename T>\r\n    inline auto convertInto( std::string const &source, T& target ) -> ParserResult {\r\n        std::stringstream ss;\r\n        ss << source;\r\n        ss >> target;\r\n        if( ss.fail() )\r\n            return ParserResult::runtimeError( \"Unable to convert '\" + source + \"' to destination type\" );\r\n        else\r\n            return ParserResult::ok( ParseResultType::Matched );\r\n    }\r\n    inline auto convertInto( std::string const &source, std::string& target ) -> ParserResult {\r\n        target = source;\r\n        return ParserResult::ok( ParseResultType::Matched );\r\n    }\r\n    inline auto convertInto( std::string const &source, bool &target ) -> ParserResult {\r\n        std::string srcLC = source;\r\n        std::transform( srcLC.begin(), srcLC.end(), srcLC.begin(), []( char c ) { return static_cast<char>( std::tolower(c) ); } );\r\n        if (srcLC == \"y\" || srcLC == \"1\" || srcLC == \"true\" || srcLC == \"yes\" || srcLC == \"on\")\r\n            target = true;\r\n        else if (srcLC == \"n\" || srcLC == \"0\" || srcLC == \"false\" || srcLC == \"no\" || srcLC == \"off\")\r\n            target = false;\r\n        else\r\n            return ParserResult::runtimeError( \"Expected a boolean value but did not recognise: '\" + source + \"'\" );\r\n        return ParserResult::ok( ParseResultType::Matched );\r\n    }\r\n#ifdef CLARA_CONFIG_OPTIONAL_TYPE\r\n    template<typename T>\r\n    inline auto convertInto( std::string const &source, CLARA_CONFIG_OPTIONAL_TYPE<T>& target ) -> ParserResult {\r\n        T temp;\r\n        auto result = convertInto( source, temp );\r\n        if( result )\r\n            target = std::move(temp);\r\n        return result;\r\n    }\r\n#endif // CLARA_CONFIG_OPTIONAL_TYPE\r\n\r\n    struct NonCopyable {\r\n        NonCopyable() = default;\r\n        NonCopyable( NonCopyable const & ) = delete;\r\n        NonCopyable( NonCopyable && ) = delete;\r\n        NonCopyable &operator=( NonCopyable const & ) = delete;\r\n        NonCopyable &operator=( NonCopyable && ) = delete;\r\n    };\r\n\r\n    struct BoundRef : NonCopyable {\r\n        virtual ~BoundRef() = default;\r\n        virtual auto isContainer() const -> bool { return false; }\r\n        virtual auto isFlag() const -> bool { return false; }\r\n    };\r\n    struct BoundValueRefBase : BoundRef {\r\n        virtual auto setValue( std::string const &arg ) -> ParserResult = 0;\r\n    };\r\n    struct BoundFlagRefBase : BoundRef {\r\n        virtual auto setFlag( bool flag ) -> ParserResult = 0;\r\n        virtual auto isFlag() const -> bool { return true; }\r\n    };\r\n\r\n    template<typename T>\r\n    struct BoundValueRef : BoundValueRefBase {\r\n        T &m_ref;\r\n\r\n        explicit BoundValueRef( T &ref ) : m_ref( ref ) {}\r\n\r\n        auto setValue( std::string const &arg ) -> ParserResult override {\r\n            return convertInto( arg, m_ref );\r\n        }\r\n    };\r\n\r\n    template<typename T>\r\n    struct BoundValueRef<std::vector<T>> : BoundValueRefBase {\r\n        std::vector<T> &m_ref;\r\n\r\n        explicit BoundValueRef( std::vector<T> &ref ) : m_ref( ref ) {}\r\n\r\n        auto isContainer() const -> bool override { return true; }\r\n\r\n        auto setValue( std::string const &arg ) -> ParserResult override {\r\n            T temp;\r\n            auto result = convertInto( arg, temp );\r\n            if( result )\r\n                m_ref.push_back( temp );\r\n            return result;\r\n        }\r\n    };\r\n\r\n    struct BoundFlagRef : BoundFlagRefBase {\r\n        bool &m_ref;\r\n\r\n        explicit BoundFlagRef( bool &ref ) : m_ref( ref ) {}\r\n\r\n        auto setFlag( bool flag ) -> ParserResult override {\r\n            m_ref = flag;\r\n            return ParserResult::ok( ParseResultType::Matched );\r\n        }\r\n    };\r\n\r\n    template<typename ReturnType>\r\n    struct LambdaInvoker {\r\n        static_assert( std::is_same<ReturnType, ParserResult>::value, \"Lambda must return void or clara::ParserResult\" );\r\n\r\n        template<typename L, typename ArgType>\r\n        static auto invoke( L const &lambda, ArgType const &arg ) -> ParserResult {\r\n            return lambda( arg );\r\n        }\r\n    };\r\n\r\n    template<>\r\n    struct LambdaInvoker<void> {\r\n        template<typename L, typename ArgType>\r\n        static auto invoke( L const &lambda, ArgType const &arg ) -> ParserResult {\r\n            lambda( arg );\r\n            return ParserResult::ok( ParseResultType::Matched );\r\n        }\r\n    };\r\n\r\n    template<typename ArgType, typename L>\r\n    inline auto invokeLambda( L const &lambda, std::string const &arg ) -> ParserResult {\r\n        ArgType temp{};\r\n        auto result = convertInto( arg, temp );\r\n        return !result\r\n           ? result\r\n           : LambdaInvoker<typename UnaryLambdaTraits<L>::ReturnType>::invoke( lambda, temp );\r\n    }\r\n\r\n    template<typename L>\r\n    struct BoundLambda : BoundValueRefBase {\r\n        L m_lambda;\r\n\r\n        static_assert( UnaryLambdaTraits<L>::isValid, \"Supplied lambda must take exactly one argument\" );\r\n        explicit BoundLambda( L const &lambda ) : m_lambda( lambda ) {}\r\n\r\n        auto setValue( std::string const &arg ) -> ParserResult override {\r\n            return invokeLambda<typename UnaryLambdaTraits<L>::ArgType>( m_lambda, arg );\r\n        }\r\n    };\r\n\r\n    template<typename L>\r\n    struct BoundFlagLambda : BoundFlagRefBase {\r\n        L m_lambda;\r\n\r\n        static_assert( UnaryLambdaTraits<L>::isValid, \"Supplied lambda must take exactly one argument\" );\r\n        static_assert( std::is_same<typename UnaryLambdaTraits<L>::ArgType, bool>::value, \"flags must be boolean\" );\r\n\r\n        explicit BoundFlagLambda( L const &lambda ) : m_lambda( lambda ) {}\r\n\r\n        auto setFlag( bool flag ) -> ParserResult override {\r\n            return LambdaInvoker<typename UnaryLambdaTraits<L>::ReturnType>::invoke( m_lambda, flag );\r\n        }\r\n    };\r\n\r\n    enum class Optionality { Optional, Required };\r\n\r\n    struct Parser;\r\n\r\n    class ParserBase {\r\n    public:\r\n        virtual ~ParserBase() = default;\r\n        virtual auto validate() const -> Result { return Result::ok(); }\r\n        virtual auto parse( std::string const& exeName, TokenStream const &tokens) const -> InternalParseResult  = 0;\r\n        virtual auto cardinality() const -> size_t { return 1; }\r\n\r\n        auto parse( Args const &args ) const -> InternalParseResult {\r\n            return parse( args.exeName(), TokenStream( args ) );\r\n        }\r\n    };\r\n\r\n    template<typename DerivedT>\r\n    class ComposableParserImpl : public ParserBase {\r\n    public:\r\n        template<typename T>\r\n        auto operator|( T const &other ) const -> Parser;\r\n\r\n\t\ttemplate<typename T>\r\n        auto operator+( T const &other ) const -> Parser;\r\n    };\r\n\r\n    // Common code and state for Args and Opts\r\n    template<typename DerivedT>\r\n    class ParserRefImpl : public ComposableParserImpl<DerivedT> {\r\n    protected:\r\n        Optionality m_optionality = Optionality::Optional;\r\n        std::shared_ptr<BoundRef> m_ref;\r\n        std::string m_hint;\r\n        std::string m_description;\r\n\r\n        explicit ParserRefImpl( std::shared_ptr<BoundRef> const &ref ) : m_ref( ref ) {}\r\n\r\n    public:\r\n        template<typename T>\r\n        ParserRefImpl( T &ref, std::string const &hint )\r\n        :   m_ref( std::make_shared<BoundValueRef<T>>( ref ) ),\r\n            m_hint( hint )\r\n        {}\r\n\r\n        template<typename LambdaT>\r\n        ParserRefImpl( LambdaT const &ref, std::string const &hint )\r\n        :   m_ref( std::make_shared<BoundLambda<LambdaT>>( ref ) ),\r\n            m_hint(hint)\r\n        {}\r\n\r\n        auto operator()( std::string const &description ) -> DerivedT & {\r\n            m_description = description;\r\n            return static_cast<DerivedT &>( *this );\r\n        }\r\n\r\n        auto optional() -> DerivedT & {\r\n            m_optionality = Optionality::Optional;\r\n            return static_cast<DerivedT &>( *this );\r\n        };\r\n\r\n        auto required() -> DerivedT & {\r\n            m_optionality = Optionality::Required;\r\n            return static_cast<DerivedT &>( *this );\r\n        };\r\n\r\n        auto isOptional() const -> bool {\r\n            return m_optionality == Optionality::Optional;\r\n        }\r\n\r\n        auto cardinality() const -> size_t override {\r\n            if( m_ref->isContainer() )\r\n                return 0;\r\n            else\r\n                return 1;\r\n        }\r\n\r\n        auto hint() const -> std::string { return m_hint; }\r\n    };\r\n\r\n    class ExeName : public ComposableParserImpl<ExeName> {\r\n        std::shared_ptr<std::string> m_name;\r\n        std::shared_ptr<BoundValueRefBase> m_ref;\r\n\r\n        template<typename LambdaT>\r\n        static auto makeRef(LambdaT const &lambda) -> std::shared_ptr<BoundValueRefBase> {\r\n            return std::make_shared<BoundLambda<LambdaT>>( lambda) ;\r\n        }\r\n\r\n    public:\r\n        ExeName() : m_name( std::make_shared<std::string>( \"<executable>\" ) ) {}\r\n\r\n        explicit ExeName( std::string &ref ) : ExeName() {\r\n            m_ref = std::make_shared<BoundValueRef<std::string>>( ref );\r\n        }\r\n\r\n        template<typename LambdaT>\r\n        explicit ExeName( LambdaT const& lambda ) : ExeName() {\r\n            m_ref = std::make_shared<BoundLambda<LambdaT>>( lambda );\r\n        }\r\n\r\n        // The exe name is not parsed out of the normal tokens, but is handled specially\r\n        auto parse( std::string const&, TokenStream const &tokens ) const -> InternalParseResult override {\r\n            return InternalParseResult::ok( ParseState( ParseResultType::NoMatch, tokens ) );\r\n        }\r\n\r\n        auto name() const -> std::string { return *m_name; }\r\n        auto set( std::string const& newName ) -> ParserResult {\r\n\r\n            auto lastSlash = newName.find_last_of( \"\\\\/\" );\r\n            auto filename = ( lastSlash == std::string::npos )\r\n                    ? newName\r\n                    : newName.substr( lastSlash+1 );\r\n\r\n            *m_name = filename;\r\n            if( m_ref )\r\n                return m_ref->setValue( filename );\r\n            else\r\n                return ParserResult::ok( ParseResultType::Matched );\r\n        }\r\n    };\r\n\r\n    class Arg : public ParserRefImpl<Arg> {\r\n    public:\r\n        using ParserRefImpl::ParserRefImpl;\r\n\r\n        auto parse( std::string const &, TokenStream const &tokens ) const -> InternalParseResult override {\r\n            auto validationResult = validate();\r\n            if( !validationResult )\r\n                return InternalParseResult( validationResult );\r\n\r\n            auto remainingTokens = tokens;\r\n            auto const &token = *remainingTokens;\r\n            if( token.type != TokenType::Argument )\r\n                return InternalParseResult::ok( ParseState( ParseResultType::NoMatch, remainingTokens ) );\r\n\r\n            assert( !m_ref->isFlag() );\r\n            auto valueRef = static_cast<detail::BoundValueRefBase*>( m_ref.get() );\r\n\r\n            auto result = valueRef->setValue( remainingTokens->token );\r\n            if( !result )\r\n                return InternalParseResult( result );\r\n            else\r\n                return InternalParseResult::ok( ParseState( ParseResultType::Matched, ++remainingTokens ) );\r\n        }\r\n    };\r\n\r\n    inline auto normaliseOpt( std::string const &optName ) -> std::string {\r\n#ifdef CATCH_PLATFORM_WINDOWS\r\n        if( optName[0] == '/' )\r\n            return \"-\" + optName.substr( 1 );\r\n        else\r\n#endif\r\n            return optName;\r\n    }\r\n\r\n    class Opt : public ParserRefImpl<Opt> {\r\n    protected:\r\n        std::vector<std::string> m_optNames;\r\n\r\n    public:\r\n        template<typename LambdaT>\r\n        explicit Opt( LambdaT const &ref ) : ParserRefImpl( std::make_shared<BoundFlagLambda<LambdaT>>( ref ) ) {}\r\n\r\n        explicit Opt( bool &ref ) : ParserRefImpl( std::make_shared<BoundFlagRef>( ref ) ) {}\r\n\r\n        template<typename LambdaT>\r\n        Opt( LambdaT const &ref, std::string const &hint ) : ParserRefImpl( ref, hint ) {}\r\n\r\n        template<typename T>\r\n        Opt( T &ref, std::string const &hint ) : ParserRefImpl( ref, hint ) {}\r\n\r\n        auto operator[]( std::string const &optName ) -> Opt & {\r\n            m_optNames.push_back( optName );\r\n            return *this;\r\n        }\r\n\r\n        auto getHelpColumns() const -> std::vector<HelpColumns> {\r\n            std::ostringstream oss;\r\n            bool first = true;\r\n            for( auto const &opt : m_optNames ) {\r\n                if (first)\r\n                    first = false;\r\n                else\r\n                    oss << \", \";\r\n                oss << opt;\r\n            }\r\n            if( !m_hint.empty() )\r\n                oss << \" <\" << m_hint << \">\";\r\n            return { { oss.str(), m_description } };\r\n        }\r\n\r\n        auto isMatch( std::string const &optToken ) const -> bool {\r\n            auto normalisedToken = normaliseOpt( optToken );\r\n            for( auto const &name : m_optNames ) {\r\n                if( normaliseOpt( name ) == normalisedToken )\r\n                    return true;\r\n            }\r\n            return false;\r\n        }\r\n\r\n        using ParserBase::parse;\r\n\r\n        auto parse( std::string const&, TokenStream const &tokens ) const -> InternalParseResult override {\r\n            auto validationResult = validate();\r\n            if( !validationResult )\r\n                return InternalParseResult( validationResult );\r\n\r\n            auto remainingTokens = tokens;\r\n            if( remainingTokens && remainingTokens->type == TokenType::Option ) {\r\n                auto const &token = *remainingTokens;\r\n                if( isMatch(token.token ) ) {\r\n                    if( m_ref->isFlag() ) {\r\n                        auto flagRef = static_cast<detail::BoundFlagRefBase*>( m_ref.get() );\r\n                        auto result = flagRef->setFlag( true );\r\n                        if( !result )\r\n                            return InternalParseResult( result );\r\n                        if( result.value() == ParseResultType::ShortCircuitAll )\r\n                            return InternalParseResult::ok( ParseState( result.value(), remainingTokens ) );\r\n                    } else {\r\n                        auto valueRef = static_cast<detail::BoundValueRefBase*>( m_ref.get() );\r\n                        ++remainingTokens;\r\n                        if( !remainingTokens )\r\n                            return InternalParseResult::runtimeError( \"Expected argument following \" + token.token );\r\n                        auto const &argToken = *remainingTokens;\r\n                        if( argToken.type != TokenType::Argument )\r\n                            return InternalParseResult::runtimeError( \"Expected argument following \" + token.token );\r\n                        auto result = valueRef->setValue( argToken.token );\r\n                        if( !result )\r\n                            return InternalParseResult( result );\r\n                        if( result.value() == ParseResultType::ShortCircuitAll )\r\n                            return InternalParseResult::ok( ParseState( result.value(), remainingTokens ) );\r\n                    }\r\n                    return InternalParseResult::ok( ParseState( ParseResultType::Matched, ++remainingTokens ) );\r\n                }\r\n            }\r\n            return InternalParseResult::ok( ParseState( ParseResultType::NoMatch, remainingTokens ) );\r\n        }\r\n\r\n        auto validate() const -> Result override {\r\n            if( m_optNames.empty() )\r\n                return Result::logicError( \"No options supplied to Opt\" );\r\n            for( auto const &name : m_optNames ) {\r\n                if( name.empty() )\r\n                    return Result::logicError( \"Option name cannot be empty\" );\r\n#ifdef CATCH_PLATFORM_WINDOWS\r\n                if( name[0] != '-' && name[0] != '/' )\r\n                    return Result::logicError( \"Option name must begin with '-' or '/'\" );\r\n#else\r\n                if( name[0] != '-' )\r\n                    return Result::logicError( \"Option name must begin with '-'\" );\r\n#endif\r\n            }\r\n            return ParserRefImpl::validate();\r\n        }\r\n    };\r\n\r\n    struct Help : Opt {\r\n        Help( bool &showHelpFlag )\r\n        :   Opt([&]( bool flag ) {\r\n                showHelpFlag = flag;\r\n                return ParserResult::ok( ParseResultType::ShortCircuitAll );\r\n            })\r\n        {\r\n            static_cast<Opt &>( *this )\r\n                    (\"display usage information\")\r\n                    [\"-?\"][\"-h\"][\"--help\"]\r\n                    .optional();\r\n        }\r\n    };\r\n\r\n    struct Parser : ParserBase {\r\n\r\n        mutable ExeName m_exeName;\r\n        std::vector<Opt> m_options;\r\n        std::vector<Arg> m_args;\r\n\r\n        auto operator|=( ExeName const &exeName ) -> Parser & {\r\n            m_exeName = exeName;\r\n            return *this;\r\n        }\r\n\r\n        auto operator|=( Arg const &arg ) -> Parser & {\r\n            m_args.push_back(arg);\r\n            return *this;\r\n        }\r\n\r\n        auto operator|=( Opt const &opt ) -> Parser & {\r\n            m_options.push_back(opt);\r\n            return *this;\r\n        }\r\n\r\n        auto operator|=( Parser const &other ) -> Parser & {\r\n            m_options.insert(m_options.end(), other.m_options.begin(), other.m_options.end());\r\n            m_args.insert(m_args.end(), other.m_args.begin(), other.m_args.end());\r\n            return *this;\r\n        }\r\n\r\n        template<typename T>\r\n        auto operator|( T const &other ) const -> Parser {\r\n            return Parser( *this ) |= other;\r\n        }\r\n\r\n        // Forward deprecated interface with '+' instead of '|'\r\n        template<typename T>\r\n        auto operator+=( T const &other ) -> Parser & { return operator|=( other ); }\r\n        template<typename T>\r\n        auto operator+( T const &other ) const -> Parser { return operator|( other ); }\r\n\r\n        auto getHelpColumns() const -> std::vector<HelpColumns> {\r\n            std::vector<HelpColumns> cols;\r\n            for (auto const &o : m_options) {\r\n                auto childCols = o.getHelpColumns();\r\n                cols.insert( cols.end(), childCols.begin(), childCols.end() );\r\n            }\r\n            return cols;\r\n        }\r\n\r\n        void writeToStream( std::ostream &os ) const {\r\n            if (!m_exeName.name().empty()) {\r\n                os << \"usage:\\n\" << \"  \" << m_exeName.name() << \" \";\r\n                bool required = true, first = true;\r\n                for( auto const &arg : m_args ) {\r\n                    if (first)\r\n                        first = false;\r\n                    else\r\n                        os << \" \";\r\n                    if( arg.isOptional() && required ) {\r\n                        os << \"[\";\r\n                        required = false;\r\n                    }\r\n                    os << \"<\" << arg.hint() << \">\";\r\n                    if( arg.cardinality() == 0 )\r\n                        os << \" ... \";\r\n                }\r\n                if( !required )\r\n                    os << \"]\";\r\n                if( !m_options.empty() )\r\n                    os << \" options\";\r\n                os << \"\\n\\nwhere options are:\" << std::endl;\r\n            }\r\n\r\n            auto rows = getHelpColumns();\r\n            size_t consoleWidth = CATCH_CLARA_CONFIG_CONSOLE_WIDTH;\r\n            size_t optWidth = 0;\r\n            for( auto const &cols : rows )\r\n                optWidth = (std::max)(optWidth, cols.left.size() + 2);\r\n\r\n            optWidth = (std::min)(optWidth, consoleWidth/2);\r\n\r\n            for( auto const &cols : rows ) {\r\n                auto row =\r\n                        TextFlow::Column( cols.left ).width( optWidth ).indent( 2 ) +\r\n                        TextFlow::Spacer(4) +\r\n                        TextFlow::Column( cols.right ).width( consoleWidth - 7 - optWidth );\r\n                os << row << std::endl;\r\n            }\r\n        }\r\n\r\n        friend auto operator<<( std::ostream &os, Parser const &parser ) -> std::ostream& {\r\n            parser.writeToStream( os );\r\n            return os;\r\n        }\r\n\r\n        auto validate() const -> Result override {\r\n            for( auto const &opt : m_options ) {\r\n                auto result = opt.validate();\r\n                if( !result )\r\n                    return result;\r\n            }\r\n            for( auto const &arg : m_args ) {\r\n                auto result = arg.validate();\r\n                if( !result )\r\n                    return result;\r\n            }\r\n            return Result::ok();\r\n        }\r\n\r\n        using ParserBase::parse;\r\n\r\n        auto parse( std::string const& exeName, TokenStream const &tokens ) const -> InternalParseResult override {\r\n\r\n            struct ParserInfo {\r\n                ParserBase const* parser = nullptr;\r\n                size_t count = 0;\r\n            };\r\n            const size_t totalParsers = m_options.size() + m_args.size();\r\n            assert( totalParsers < 512 );\r\n            // ParserInfo parseInfos[totalParsers]; // <-- this is what we really want to do\r\n            ParserInfo parseInfos[512];\r\n\r\n            {\r\n                size_t i = 0;\r\n                for (auto const &opt : m_options) parseInfos[i++].parser = &opt;\r\n                for (auto const &arg : m_args) parseInfos[i++].parser = &arg;\r\n            }\r\n\r\n            m_exeName.set( exeName );\r\n\r\n            auto result = InternalParseResult::ok( ParseState( ParseResultType::NoMatch, tokens ) );\r\n            while( result.value().remainingTokens() ) {\r\n                bool tokenParsed = false;\r\n\r\n                for( size_t i = 0; i < totalParsers; ++i ) {\r\n                    auto&  parseInfo = parseInfos[i];\r\n                    if( parseInfo.parser->cardinality() == 0 || parseInfo.count < parseInfo.parser->cardinality() ) {\r\n                        result = parseInfo.parser->parse(exeName, result.value().remainingTokens());\r\n                        if (!result)\r\n                            return result;\r\n                        if (result.value().type() != ParseResultType::NoMatch) {\r\n                            tokenParsed = true;\r\n                            ++parseInfo.count;\r\n                            break;\r\n                        }\r\n                    }\r\n                }\r\n\r\n                if( result.value().type() == ParseResultType::ShortCircuitAll )\r\n                    return result;\r\n                if( !tokenParsed )\r\n                    return InternalParseResult::runtimeError( \"Unrecognised token: \" + result.value().remainingTokens()->token );\r\n            }\r\n            // !TBD Check missing required options\r\n            return result;\r\n        }\r\n    };\r\n\r\n    template<typename DerivedT>\r\n    template<typename T>\r\n    auto ComposableParserImpl<DerivedT>::operator|( T const &other ) const -> Parser {\r\n        return Parser() | static_cast<DerivedT const &>( *this ) | other;\r\n    }\r\n} // namespace detail\r\n\r\n// A Combined parser\r\nusing detail::Parser;\r\n\r\n// A parser for options\r\nusing detail::Opt;\r\n\r\n// A parser for arguments\r\nusing detail::Arg;\r\n\r\n// Wrapper for argc, argv from main()\r\nusing detail::Args;\r\n\r\n// Specifies the name of the executable\r\nusing detail::ExeName;\r\n\r\n// Convenience wrapper for option parser that specifies the help option\r\nusing detail::Help;\r\n\r\n// enum of result types from a parse\r\nusing detail::ParseResultType;\r\n\r\n// Result type for parser operation\r\nusing detail::ParserResult;\r\n\r\n}} // namespace Catch::clara\r\n\r\n// end clara.hpp\r\n#ifdef __clang__\r\n#pragma clang diagnostic pop\r\n#endif\r\n\r\n// Restore Clara's value for console width, if present\r\n#ifdef CATCH_TEMP_CLARA_CONFIG_CONSOLE_WIDTH\r\n#define CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH CATCH_TEMP_CLARA_CONFIG_CONSOLE_WIDTH\r\n#undef CATCH_TEMP_CLARA_CONFIG_CONSOLE_WIDTH\r\n#endif\r\n\r\n// end catch_clara.h\r\nnamespace Catch {\r\n\r\n    clara::Parser makeCommandLineParser( ConfigData& config );\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_commandline.h\r\n#include <fstream>\r\n#include <ctime>\r\n\r\nnamespace Catch {\r\n\r\n    clara::Parser makeCommandLineParser( ConfigData& config ) {\r\n\r\n        using namespace clara;\r\n\r\n        auto const setWarning = [&]( std::string const& warning ) {\r\n                auto warningSet = [&]() {\r\n                    if( warning == \"NoAssertions\" )\r\n                        return WarnAbout::NoAssertions;\r\n\r\n                    if ( warning == \"NoTests\" )\r\n                        return WarnAbout::NoTests;\r\n\r\n                    return WarnAbout::Nothing;\r\n                }();\r\n\r\n                if (warningSet == WarnAbout::Nothing)\r\n                    return ParserResult::runtimeError( \"Unrecognised warning: '\" + warning + \"'\" );\r\n                config.warnings = static_cast<WarnAbout::What>( config.warnings | warningSet );\r\n                return ParserResult::ok( ParseResultType::Matched );\r\n            };\r\n        auto const loadTestNamesFromFile = [&]( std::string const& filename ) {\r\n                std::ifstream f( filename.c_str() );\r\n                if( !f.is_open() )\r\n                    return ParserResult::runtimeError( \"Unable to load input file: '\" + filename + \"'\" );\r\n\r\n                std::string line;\r\n                while( std::getline( f, line ) ) {\r\n                    line = trim(line);\r\n                    if( !line.empty() && !startsWith( line, '#' ) ) {\r\n                        if( !startsWith( line, '\"' ) )\r\n                            line = '\"' + line + '\"';\r\n                        config.testsOrTags.push_back( line + ',' );\r\n                    }\r\n                }\r\n                return ParserResult::ok( ParseResultType::Matched );\r\n            };\r\n        auto const setTestOrder = [&]( std::string const& order ) {\r\n                if( startsWith( \"declared\", order ) )\r\n                    config.runOrder = RunTests::InDeclarationOrder;\r\n                else if( startsWith( \"lexical\", order ) )\r\n                    config.runOrder = RunTests::InLexicographicalOrder;\r\n                else if( startsWith( \"random\", order ) )\r\n                    config.runOrder = RunTests::InRandomOrder;\r\n                else\r\n                    return clara::ParserResult::runtimeError( \"Unrecognised ordering: '\" + order + \"'\" );\r\n                return ParserResult::ok( ParseResultType::Matched );\r\n            };\r\n        auto const setRngSeed = [&]( std::string const& seed ) {\r\n                if( seed != \"time\" )\r\n                    return clara::detail::convertInto( seed, config.rngSeed );\r\n                config.rngSeed = static_cast<unsigned int>( std::time(nullptr) );\r\n                return ParserResult::ok( ParseResultType::Matched );\r\n            };\r\n        auto const setColourUsage = [&]( std::string const& useColour ) {\r\n                    auto mode = toLower( useColour );\r\n\r\n                    if( mode == \"yes\" )\r\n                        config.useColour = UseColour::Yes;\r\n                    else if( mode == \"no\" )\r\n                        config.useColour = UseColour::No;\r\n                    else if( mode == \"auto\" )\r\n                        config.useColour = UseColour::Auto;\r\n                    else\r\n                        return ParserResult::runtimeError( \"colour mode must be one of: auto, yes or no. '\" + useColour + \"' not recognised\" );\r\n                return ParserResult::ok( ParseResultType::Matched );\r\n            };\r\n        auto const setWaitForKeypress = [&]( std::string const& keypress ) {\r\n                auto keypressLc = toLower( keypress );\r\n                if( keypressLc == \"start\" )\r\n                    config.waitForKeypress = WaitForKeypress::BeforeStart;\r\n                else if( keypressLc == \"exit\" )\r\n                    config.waitForKeypress = WaitForKeypress::BeforeExit;\r\n                else if( keypressLc == \"both\" )\r\n                    config.waitForKeypress = WaitForKeypress::BeforeStartAndExit;\r\n                else\r\n                    return ParserResult::runtimeError( \"keypress argument must be one of: start, exit or both. '\" + keypress + \"' not recognised\" );\r\n            return ParserResult::ok( ParseResultType::Matched );\r\n            };\r\n        auto const setVerbosity = [&]( std::string const& verbosity ) {\r\n            auto lcVerbosity = toLower( verbosity );\r\n            if( lcVerbosity == \"quiet\" )\r\n                config.verbosity = Verbosity::Quiet;\r\n            else if( lcVerbosity == \"normal\" )\r\n                config.verbosity = Verbosity::Normal;\r\n            else if( lcVerbosity == \"high\" )\r\n                config.verbosity = Verbosity::High;\r\n            else\r\n                return ParserResult::runtimeError( \"Unrecognised verbosity, '\" + verbosity + \"'\" );\r\n            return ParserResult::ok( ParseResultType::Matched );\r\n        };\r\n        auto const setReporter = [&]( std::string const& reporter ) {\r\n            IReporterRegistry::FactoryMap const& factories = getRegistryHub().getReporterRegistry().getFactories();\r\n\r\n            auto lcReporter = toLower( reporter );\r\n            auto result = factories.find( lcReporter );\r\n\r\n            if( factories.end() != result )\r\n                config.reporterName = lcReporter;\r\n            else\r\n                return ParserResult::runtimeError( \"Unrecognized reporter, '\" + reporter + \"'. Check available with --list-reporters\" );\r\n            return ParserResult::ok( ParseResultType::Matched );\r\n        };\r\n\r\n        auto cli\r\n            = ExeName( config.processName )\r\n            | Help( config.showHelp )\r\n            | Opt( config.listTests )\r\n                [\"-l\"][\"--list-tests\"]\r\n                ( \"list all/matching test cases\" )\r\n            | Opt( config.listTags )\r\n                [\"-t\"][\"--list-tags\"]\r\n                ( \"list all/matching tags\" )\r\n            | Opt( config.showSuccessfulTests )\r\n                [\"-s\"][\"--success\"]\r\n                ( \"include successful tests in output\" )\r\n            | Opt( config.shouldDebugBreak )\r\n                [\"-b\"][\"--break\"]\r\n                ( \"break into debugger on failure\" )\r\n            | Opt( config.noThrow )\r\n                [\"-e\"][\"--nothrow\"]\r\n                ( \"skip exception tests\" )\r\n            | Opt( config.showInvisibles )\r\n                [\"-i\"][\"--invisibles\"]\r\n                ( \"show invisibles (tabs, newlines)\" )\r\n            | Opt( config.outputFilename, \"filename\" )\r\n                [\"-o\"][\"--out\"]\r\n                ( \"output filename\" )\r\n            | Opt( setReporter, \"name\" )\r\n                [\"-r\"][\"--reporter\"]\r\n                ( \"reporter to use (defaults to console)\" )\r\n            | Opt( config.name, \"name\" )\r\n                [\"-n\"][\"--name\"]\r\n                ( \"suite name\" )\r\n            | Opt( [&]( bool ){ config.abortAfter = 1; } )\r\n                [\"-a\"][\"--abort\"]\r\n                ( \"abort at first failure\" )\r\n            | Opt( [&]( int x ){ config.abortAfter = x; }, \"no. failures\" )\r\n                [\"-x\"][\"--abortx\"]\r\n                ( \"abort after x failures\" )\r\n            | Opt( setWarning, \"warning name\" )\r\n                [\"-w\"][\"--warn\"]\r\n                ( \"enable warnings\" )\r\n            | Opt( [&]( bool flag ) { config.showDurations = flag ? ShowDurations::Always : ShowDurations::Never; }, \"yes|no\" )\r\n                [\"-d\"][\"--durations\"]\r\n                ( \"show test durations\" )\r\n            | Opt( loadTestNamesFromFile, \"filename\" )\r\n                [\"-f\"][\"--input-file\"]\r\n                ( \"load test names to run from a file\" )\r\n            | Opt( config.filenamesAsTags )\r\n                [\"-#\"][\"--filenames-as-tags\"]\r\n                ( \"adds a tag for the filename\" )\r\n            | Opt( config.sectionsToRun, \"section name\" )\r\n                [\"-c\"][\"--section\"]\r\n                ( \"specify section to run\" )\r\n            | Opt( setVerbosity, \"quiet|normal|high\" )\r\n                [\"-v\"][\"--verbosity\"]\r\n                ( \"set output verbosity\" )\r\n            | Opt( config.listTestNamesOnly )\r\n                [\"--list-test-names-only\"]\r\n                ( \"list all/matching test cases names only\" )\r\n            | Opt( config.listReporters )\r\n                [\"--list-reporters\"]\r\n                ( \"list all reporters\" )\r\n            | Opt( setTestOrder, \"decl|lex|rand\" )\r\n                [\"--order\"]\r\n                ( \"test case order (defaults to decl)\" )\r\n            | Opt( setRngSeed, \"'time'|number\" )\r\n                [\"--rng-seed\"]\r\n                ( \"set a specific seed for random numbers\" )\r\n            | Opt( setColourUsage, \"yes|no\" )\r\n                [\"--use-colour\"]\r\n                ( \"should output be colourised\" )\r\n            | Opt( config.libIdentify )\r\n                [\"--libidentify\"]\r\n                ( \"report name and version according to libidentify standard\" )\r\n            | Opt( setWaitForKeypress, \"start|exit|both\" )\r\n                [\"--wait-for-keypress\"]\r\n                ( \"waits for a keypress before exiting\" )\r\n            | Opt( config.benchmarkResolutionMultiple, \"multiplier\" )\r\n                [\"--benchmark-resolution-multiple\"]\r\n                ( \"multiple of clock resolution to run benchmarks\" )\r\n\r\n            | Arg( config.testsOrTags, \"test name|pattern|tags\" )\r\n                ( \"which test or tests to use\" );\r\n\r\n        return cli;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_commandline.cpp\r\n// start catch_common.cpp\r\n\r\n#include <cstring>\r\n#include <ostream>\r\n\r\nnamespace Catch {\r\n\r\n    bool SourceLineInfo::empty() const noexcept {\r\n        return file[0] == '\\0';\r\n    }\r\n    bool SourceLineInfo::operator == ( SourceLineInfo const& other ) const noexcept {\r\n        return line == other.line && (file == other.file || std::strcmp(file, other.file) == 0);\r\n    }\r\n    bool SourceLineInfo::operator < ( SourceLineInfo const& other ) const noexcept {\r\n        // We can assume that the same file will usually have the same pointer.\r\n        // Thus, if the pointers are the same, there is no point in calling the strcmp\r\n        return line < other.line || ( line == other.line && file != other.file && (std::strcmp(file, other.file) < 0));\r\n    }\r\n\r\n    std::ostream& operator << ( std::ostream& os, SourceLineInfo const& info ) {\r\n#ifndef __GNUG__\r\n        os << info.file << '(' << info.line << ')';\r\n#else\r\n        os << info.file << ':' << info.line;\r\n#endif\r\n        return os;\r\n    }\r\n\r\n    std::string StreamEndStop::operator+() const {\r\n        return std::string();\r\n    }\r\n\r\n    NonCopyable::NonCopyable() = default;\r\n    NonCopyable::~NonCopyable() = default;\r\n\r\n}\r\n// end catch_common.cpp\r\n// start catch_config.cpp\r\n\r\nnamespace Catch {\r\n\r\n    Config::Config( ConfigData const& data )\r\n    :   m_data( data ),\r\n        m_stream( openStream() )\r\n    {\r\n        TestSpecParser parser(ITagAliasRegistry::get());\r\n        if (data.testsOrTags.empty()) {\r\n            parser.parse(\"~[.]\"); // All not hidden tests\r\n        }\r\n        else {\r\n            m_hasTestFilters = true;\r\n            for( auto const& testOrTags : data.testsOrTags )\r\n                parser.parse( testOrTags );\r\n        }\r\n        m_testSpec = parser.testSpec();\r\n    }\r\n\r\n    std::string const& Config::getFilename() const {\r\n        return m_data.outputFilename ;\r\n    }\r\n\r\n    bool Config::listTests() const          { return m_data.listTests; }\r\n    bool Config::listTestNamesOnly() const  { return m_data.listTestNamesOnly; }\r\n    bool Config::listTags() const           { return m_data.listTags; }\r\n    bool Config::listReporters() const      { return m_data.listReporters; }\r\n\r\n    std::string Config::getProcessName() const { return m_data.processName; }\r\n    std::string const& Config::getReporterName() const { return m_data.reporterName; }\r\n\r\n    std::vector<std::string> const& Config::getTestsOrTags() const { return m_data.testsOrTags; }\r\n    std::vector<std::string> const& Config::getSectionsToRun() const { return m_data.sectionsToRun; }\r\n\r\n    TestSpec const& Config::testSpec() const { return m_testSpec; }\r\n    bool Config::hasTestFilters() const { return m_hasTestFilters; }\r\n\r\n    bool Config::showHelp() const { return m_data.showHelp; }\r\n\r\n    // IConfig interface\r\n    bool Config::allowThrows() const                   { return !m_data.noThrow; }\r\n    std::ostream& Config::stream() const               { return m_stream->stream(); }\r\n    std::string Config::name() const                   { return m_data.name.empty() ? m_data.processName : m_data.name; }\r\n    bool Config::includeSuccessfulResults() const      { return m_data.showSuccessfulTests; }\r\n    bool Config::warnAboutMissingAssertions() const    { return !!(m_data.warnings & WarnAbout::NoAssertions); }\r\n    bool Config::warnAboutNoTests() const              { return !!(m_data.warnings & WarnAbout::NoTests); }\r\n    ShowDurations::OrNot Config::showDurations() const { return m_data.showDurations; }\r\n    RunTests::InWhatOrder Config::runOrder() const     { return m_data.runOrder; }\r\n    unsigned int Config::rngSeed() const               { return m_data.rngSeed; }\r\n    int Config::benchmarkResolutionMultiple() const    { return m_data.benchmarkResolutionMultiple; }\r\n    UseColour::YesOrNo Config::useColour() const       { return m_data.useColour; }\r\n    bool Config::shouldDebugBreak() const              { return m_data.shouldDebugBreak; }\r\n    int Config::abortAfter() const                     { return m_data.abortAfter; }\r\n    bool Config::showInvisibles() const                { return m_data.showInvisibles; }\r\n    Verbosity Config::verbosity() const                { return m_data.verbosity; }\r\n\r\n    IStream const* Config::openStream() {\r\n        return Catch::makeStream(m_data.outputFilename);\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_config.cpp\r\n// start catch_console_colour.cpp\r\n\r\n#if defined(__clang__)\r\n#    pragma clang diagnostic push\r\n#    pragma clang diagnostic ignored \"-Wexit-time-destructors\"\r\n#endif\r\n\r\n// start catch_errno_guard.h\r\n\r\nnamespace Catch {\r\n\r\n    class ErrnoGuard {\r\n    public:\r\n        ErrnoGuard();\r\n        ~ErrnoGuard();\r\n    private:\r\n        int m_oldErrno;\r\n    };\r\n\r\n}\r\n\r\n// end catch_errno_guard.h\r\n#include <sstream>\r\n\r\nnamespace Catch {\r\n    namespace {\r\n\r\n        struct IColourImpl {\r\n            virtual ~IColourImpl() = default;\r\n            virtual void use( Colour::Code _colourCode ) = 0;\r\n        };\r\n\r\n        struct NoColourImpl : IColourImpl {\r\n            void use( Colour::Code ) {}\r\n\r\n            static IColourImpl* instance() {\r\n                static NoColourImpl s_instance;\r\n                return &s_instance;\r\n            }\r\n        };\r\n\r\n    } // anon namespace\r\n} // namespace Catch\r\n\r\n#if !defined( CATCH_CONFIG_COLOUR_NONE ) && !defined( CATCH_CONFIG_COLOUR_WINDOWS ) && !defined( CATCH_CONFIG_COLOUR_ANSI )\r\n#   ifdef CATCH_PLATFORM_WINDOWS\r\n#       define CATCH_CONFIG_COLOUR_WINDOWS\r\n#   else\r\n#       define CATCH_CONFIG_COLOUR_ANSI\r\n#   endif\r\n#endif\r\n\r\n#if defined ( CATCH_CONFIG_COLOUR_WINDOWS ) /////////////////////////////////////////\r\n\r\nnamespace Catch {\r\nnamespace {\r\n\r\n    class Win32ColourImpl : public IColourImpl {\r\n    public:\r\n        Win32ColourImpl() : stdoutHandle( GetStdHandle(STD_OUTPUT_HANDLE) )\r\n        {\r\n            CONSOLE_SCREEN_BUFFER_INFO csbiInfo;\r\n            GetConsoleScreenBufferInfo( stdoutHandle, &csbiInfo );\r\n            originalForegroundAttributes = csbiInfo.wAttributes & ~( BACKGROUND_GREEN | BACKGROUND_RED | BACKGROUND_BLUE | BACKGROUND_INTENSITY );\r\n            originalBackgroundAttributes = csbiInfo.wAttributes & ~( FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_BLUE | FOREGROUND_INTENSITY );\r\n        }\r\n\r\n        virtual void use( Colour::Code _colourCode ) override {\r\n            switch( _colourCode ) {\r\n                case Colour::None:      return setTextAttribute( originalForegroundAttributes );\r\n                case Colour::White:     return setTextAttribute( FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_BLUE );\r\n                case Colour::Red:       return setTextAttribute( FOREGROUND_RED );\r\n                case Colour::Green:     return setTextAttribute( FOREGROUND_GREEN );\r\n                case Colour::Blue:      return setTextAttribute( FOREGROUND_BLUE );\r\n                case Colour::Cyan:      return setTextAttribute( FOREGROUND_BLUE | FOREGROUND_GREEN );\r\n                case Colour::Yellow:    return setTextAttribute( FOREGROUND_RED | FOREGROUND_GREEN );\r\n                case Colour::Grey:      return setTextAttribute( 0 );\r\n\r\n                case Colour::LightGrey:     return setTextAttribute( FOREGROUND_INTENSITY );\r\n                case Colour::BrightRed:     return setTextAttribute( FOREGROUND_INTENSITY | FOREGROUND_RED );\r\n                case Colour::BrightGreen:   return setTextAttribute( FOREGROUND_INTENSITY | FOREGROUND_GREEN );\r\n                case Colour::BrightWhite:   return setTextAttribute( FOREGROUND_INTENSITY | FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_BLUE );\r\n                case Colour::BrightYellow:  return setTextAttribute( FOREGROUND_INTENSITY | FOREGROUND_RED | FOREGROUND_GREEN );\r\n\r\n                case Colour::Bright: CATCH_INTERNAL_ERROR( \"not a colour\" );\r\n\r\n                default:\r\n                    CATCH_ERROR( \"Unknown colour requested\" );\r\n            }\r\n        }\r\n\r\n    private:\r\n        void setTextAttribute( WORD _textAttribute ) {\r\n            SetConsoleTextAttribute( stdoutHandle, _textAttribute | originalBackgroundAttributes );\r\n        }\r\n        HANDLE stdoutHandle;\r\n        WORD originalForegroundAttributes;\r\n        WORD originalBackgroundAttributes;\r\n    };\r\n\r\n    IColourImpl* platformColourInstance() {\r\n        static Win32ColourImpl s_instance;\r\n\r\n        IConfigPtr config = getCurrentContext().getConfig();\r\n        UseColour::YesOrNo colourMode = config\r\n            ? config->useColour()\r\n            : UseColour::Auto;\r\n        if( colourMode == UseColour::Auto )\r\n            colourMode = UseColour::Yes;\r\n        return colourMode == UseColour::Yes\r\n            ? &s_instance\r\n            : NoColourImpl::instance();\r\n    }\r\n\r\n} // end anon namespace\r\n} // end namespace Catch\r\n\r\n#elif defined( CATCH_CONFIG_COLOUR_ANSI ) //////////////////////////////////////\r\n\r\n#include <unistd.h>\r\n\r\nnamespace Catch {\r\nnamespace {\r\n\r\n    // use POSIX/ ANSI console terminal codes\r\n    // Thanks to Adam Strzelecki for original contribution\r\n    // (http://github.com/nanoant)\r\n    // https://github.com/philsquared/Catch/pull/131\r\n    class PosixColourImpl : public IColourImpl {\r\n    public:\r\n        virtual void use( Colour::Code _colourCode ) override {\r\n            switch( _colourCode ) {\r\n                case Colour::None:\r\n                case Colour::White:     return setColour( \"[0m\" );\r\n                case Colour::Red:       return setColour( \"[0;31m\" );\r\n                case Colour::Green:     return setColour( \"[0;32m\" );\r\n                case Colour::Blue:      return setColour( \"[0;34m\" );\r\n                case Colour::Cyan:      return setColour( \"[0;36m\" );\r\n                case Colour::Yellow:    return setColour( \"[0;33m\" );\r\n                case Colour::Grey:      return setColour( \"[1;30m\" );\r\n\r\n                case Colour::LightGrey:     return setColour( \"[0;37m\" );\r\n                case Colour::BrightRed:     return setColour( \"[1;31m\" );\r\n                case Colour::BrightGreen:   return setColour( \"[1;32m\" );\r\n                case Colour::BrightWhite:   return setColour( \"[1;37m\" );\r\n                case Colour::BrightYellow:  return setColour( \"[1;33m\" );\r\n\r\n                case Colour::Bright: CATCH_INTERNAL_ERROR( \"not a colour\" );\r\n                default: CATCH_INTERNAL_ERROR( \"Unknown colour requested\" );\r\n            }\r\n        }\r\n        static IColourImpl* instance() {\r\n            static PosixColourImpl s_instance;\r\n            return &s_instance;\r\n        }\r\n\r\n    private:\r\n        void setColour( const char* _escapeCode ) {\r\n            getCurrentContext().getConfig()->stream()\r\n                << '\\033' << _escapeCode;\r\n        }\r\n    };\r\n\r\n    bool useColourOnPlatform() {\r\n        return\r\n#ifdef CATCH_PLATFORM_MAC\r\n            !isDebuggerActive() &&\r\n#endif\r\n#if !(defined(__DJGPP__) && defined(__STRICT_ANSI__))\r\n            isatty(STDOUT_FILENO)\r\n#else\r\n            false\r\n#endif\r\n            ;\r\n    }\r\n    IColourImpl* platformColourInstance() {\r\n        ErrnoGuard guard;\r\n        IConfigPtr config = getCurrentContext().getConfig();\r\n        UseColour::YesOrNo colourMode = config\r\n            ? config->useColour()\r\n            : UseColour::Auto;\r\n        if( colourMode == UseColour::Auto )\r\n            colourMode = useColourOnPlatform()\r\n                ? UseColour::Yes\r\n                : UseColour::No;\r\n        return colourMode == UseColour::Yes\r\n            ? PosixColourImpl::instance()\r\n            : NoColourImpl::instance();\r\n    }\r\n\r\n} // end anon namespace\r\n} // end namespace Catch\r\n\r\n#else  // not Windows or ANSI ///////////////////////////////////////////////\r\n\r\nnamespace Catch {\r\n\r\n    static IColourImpl* platformColourInstance() { return NoColourImpl::instance(); }\r\n\r\n} // end namespace Catch\r\n\r\n#endif // Windows/ ANSI/ None\r\n\r\nnamespace Catch {\r\n\r\n    Colour::Colour( Code _colourCode ) { use( _colourCode ); }\r\n    Colour::Colour( Colour&& rhs ) noexcept {\r\n        m_moved = rhs.m_moved;\r\n        rhs.m_moved = true;\r\n    }\r\n    Colour& Colour::operator=( Colour&& rhs ) noexcept {\r\n        m_moved = rhs.m_moved;\r\n        rhs.m_moved  = true;\r\n        return *this;\r\n    }\r\n\r\n    Colour::~Colour(){ if( !m_moved ) use( None ); }\r\n\r\n    void Colour::use( Code _colourCode ) {\r\n        static IColourImpl* impl = platformColourInstance();\r\n        impl->use( _colourCode );\r\n    }\r\n\r\n    std::ostream& operator << ( std::ostream& os, Colour const& ) {\r\n        return os;\r\n    }\r\n\r\n} // end namespace Catch\r\n\r\n#if defined(__clang__)\r\n#    pragma clang diagnostic pop\r\n#endif\r\n\r\n// end catch_console_colour.cpp\r\n// start catch_context.cpp\r\n\r\nnamespace Catch {\r\n\r\n    class Context : public IMutableContext, NonCopyable {\r\n\r\n    public: // IContext\r\n        virtual IResultCapture* getResultCapture() override {\r\n            return m_resultCapture;\r\n        }\r\n        virtual IRunner* getRunner() override {\r\n            return m_runner;\r\n        }\r\n\r\n        virtual IConfigPtr const& getConfig() const override {\r\n            return m_config;\r\n        }\r\n\r\n        virtual ~Context() override;\r\n\r\n    public: // IMutableContext\r\n        virtual void setResultCapture( IResultCapture* resultCapture ) override {\r\n            m_resultCapture = resultCapture;\r\n        }\r\n        virtual void setRunner( IRunner* runner ) override {\r\n            m_runner = runner;\r\n        }\r\n        virtual void setConfig( IConfigPtr const& config ) override {\r\n            m_config = config;\r\n        }\r\n\r\n        friend IMutableContext& getCurrentMutableContext();\r\n\r\n    private:\r\n        IConfigPtr m_config;\r\n        IRunner* m_runner = nullptr;\r\n        IResultCapture* m_resultCapture = nullptr;\r\n    };\r\n\r\n    IMutableContext *IMutableContext::currentContext = nullptr;\r\n\r\n    void IMutableContext::createContext()\r\n    {\r\n        currentContext = new Context();\r\n    }\r\n\r\n    void cleanUpContext() {\r\n        delete IMutableContext::currentContext;\r\n        IMutableContext::currentContext = nullptr;\r\n    }\r\n    IContext::~IContext() = default;\r\n    IMutableContext::~IMutableContext() = default;\r\n    Context::~Context() = default;\r\n}\r\n// end catch_context.cpp\r\n// start catch_debug_console.cpp\r\n\r\n// start catch_debug_console.h\r\n\r\n#include <string>\r\n\r\nnamespace Catch {\r\n    void writeToDebugConsole( std::string const& text );\r\n}\r\n\r\n// end catch_debug_console.h\r\n#ifdef CATCH_PLATFORM_WINDOWS\r\n\r\n    namespace Catch {\r\n        void writeToDebugConsole( std::string const& text ) {\r\n            ::OutputDebugStringA( text.c_str() );\r\n        }\r\n    }\r\n\r\n#else\r\n\r\n    namespace Catch {\r\n        void writeToDebugConsole( std::string const& text ) {\r\n            // !TBD: Need a version for Mac/ XCode and other IDEs\r\n            Catch::cout() << text;\r\n        }\r\n    }\r\n\r\n#endif // Platform\r\n// end catch_debug_console.cpp\r\n// start catch_debugger.cpp\r\n\r\n#ifdef CATCH_PLATFORM_MAC\r\n\r\n#  include <assert.h>\r\n#  include <stdbool.h>\r\n#  include <sys/types.h>\r\n#  include <unistd.h>\r\n#  include <sys/sysctl.h>\r\n#  include <cstddef>\r\n#  include <ostream>\r\n\r\nnamespace Catch {\r\n\r\n        // The following function is taken directly from the following technical note:\r\n        // http://developer.apple.com/library/mac/#qa/qa2004/qa1361.html\r\n\r\n        // Returns true if the current process is being debugged (either\r\n        // running under the debugger or has a debugger attached post facto).\r\n        bool isDebuggerActive(){\r\n\r\n            int                 mib[4];\r\n            struct kinfo_proc   info;\r\n            std::size_t         size;\r\n\r\n            // Initialize the flags so that, if sysctl fails for some bizarre\r\n            // reason, we get a predictable result.\r\n\r\n            info.kp_proc.p_flag = 0;\r\n\r\n            // Initialize mib, which tells sysctl the info we want, in this case\r\n            // we're looking for information about a specific process ID.\r\n\r\n            mib[0] = CTL_KERN;\r\n            mib[1] = KERN_PROC;\r\n            mib[2] = KERN_PROC_PID;\r\n            mib[3] = getpid();\r\n\r\n            // Call sysctl.\r\n\r\n            size = sizeof(info);\r\n            if( sysctl(mib, sizeof(mib) / sizeof(*mib), &info, &size, nullptr, 0) != 0 ) {\r\n                Catch::cerr() << \"\\n** Call to sysctl failed - unable to determine if debugger is active **\\n\" << std::endl;\r\n                return false;\r\n            }\r\n\r\n            // We're being debugged if the P_TRACED flag is set.\r\n\r\n            return ( (info.kp_proc.p_flag & P_TRACED) != 0 );\r\n        }\r\n    } // namespace Catch\r\n\r\n#elif defined(CATCH_PLATFORM_LINUX)\r\n    #include <fstream>\r\n    #include <string>\r\n\r\n    namespace Catch{\r\n        // The standard POSIX way of detecting a debugger is to attempt to\r\n        // ptrace() the process, but this needs to be done from a child and not\r\n        // this process itself to still allow attaching to this process later\r\n        // if wanted, so is rather heavy. Under Linux we have the PID of the\r\n        // \"debugger\" (which doesn't need to be gdb, of course, it could also\r\n        // be strace, for example) in /proc/$PID/status, so just get it from\r\n        // there instead.\r\n        bool isDebuggerActive(){\r\n            // Libstdc++ has a bug, where std::ifstream sets errno to 0\r\n            // This way our users can properly assert over errno values\r\n            ErrnoGuard guard;\r\n            std::ifstream in(\"/proc/self/status\");\r\n            for( std::string line; std::getline(in, line); ) {\r\n                static const int PREFIX_LEN = 11;\r\n                if( line.compare(0, PREFIX_LEN, \"TracerPid:\\t\") == 0 ) {\r\n                    // We're traced if the PID is not 0 and no other PID starts\r\n                    // with 0 digit, so it's enough to check for just a single\r\n                    // character.\r\n                    return line.length() > PREFIX_LEN && line[PREFIX_LEN] != '0';\r\n                }\r\n            }\r\n\r\n            return false;\r\n        }\r\n    } // namespace Catch\r\n#elif defined(_MSC_VER)\r\n    extern \"C\" __declspec(dllimport) int __stdcall IsDebuggerPresent();\r\n    namespace Catch {\r\n        bool isDebuggerActive() {\r\n            return IsDebuggerPresent() != 0;\r\n        }\r\n    }\r\n#elif defined(__MINGW32__)\r\n    extern \"C\" __declspec(dllimport) int __stdcall IsDebuggerPresent();\r\n    namespace Catch {\r\n        bool isDebuggerActive() {\r\n            return IsDebuggerPresent() != 0;\r\n        }\r\n    }\r\n#else\r\n    namespace Catch {\r\n       bool isDebuggerActive() { return false; }\r\n    }\r\n#endif // Platform\r\n// end catch_debugger.cpp\r\n// start catch_decomposer.cpp\r\n\r\nnamespace Catch {\r\n\r\n    ITransientExpression::~ITransientExpression() = default;\r\n\r\n    void formatReconstructedExpression( std::ostream &os, std::string const& lhs, StringRef op, std::string const& rhs ) {\r\n        if( lhs.size() + rhs.size() < 40 &&\r\n                lhs.find('\\n') == std::string::npos &&\r\n                rhs.find('\\n') == std::string::npos )\r\n            os << lhs << \" \" << op << \" \" << rhs;\r\n        else\r\n            os << lhs << \"\\n\" << op << \"\\n\" << rhs;\r\n    }\r\n}\r\n// end catch_decomposer.cpp\r\n// start catch_enforce.cpp\r\n\r\nnamespace Catch {\r\n#if defined(CATCH_CONFIG_DISABLE_EXCEPTIONS) && !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS_CUSTOM_HANDLER)\r\n    [[noreturn]]\r\n    void throw_exception(std::exception const& e) {\r\n        Catch::cerr() << \"Catch will terminate because it needed to throw an exception.\\n\"\r\n                      << \"The message was: \" << e.what() << '\\n';\r\n        std::terminate();\r\n    }\r\n#endif\r\n} // namespace Catch;\r\n// end catch_enforce.cpp\r\n// start catch_errno_guard.cpp\r\n\r\n#include <cerrno>\r\n\r\nnamespace Catch {\r\n        ErrnoGuard::ErrnoGuard():m_oldErrno(errno){}\r\n        ErrnoGuard::~ErrnoGuard() { errno = m_oldErrno; }\r\n}\r\n// end catch_errno_guard.cpp\r\n// start catch_exception_translator_registry.cpp\r\n\r\n// start catch_exception_translator_registry.h\r\n\r\n#include <vector>\r\n#include <string>\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    class ExceptionTranslatorRegistry : public IExceptionTranslatorRegistry {\r\n    public:\r\n        ~ExceptionTranslatorRegistry();\r\n        virtual void registerTranslator( const IExceptionTranslator* translator );\r\n        virtual std::string translateActiveException() const override;\r\n        std::string tryTranslators() const;\r\n\r\n    private:\r\n        std::vector<std::unique_ptr<IExceptionTranslator const>> m_translators;\r\n    };\r\n}\r\n\r\n// end catch_exception_translator_registry.h\r\n#ifdef __OBJC__\r\n#import \"Foundation/Foundation.h\"\r\n#endif\r\n\r\nnamespace Catch {\r\n\r\n    ExceptionTranslatorRegistry::~ExceptionTranslatorRegistry() {\r\n    }\r\n\r\n    void ExceptionTranslatorRegistry::registerTranslator( const IExceptionTranslator* translator ) {\r\n        m_translators.push_back( std::unique_ptr<const IExceptionTranslator>( translator ) );\r\n    }\r\n\r\n#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS)\r\n    std::string ExceptionTranslatorRegistry::translateActiveException() const {\r\n        try {\r\n#ifdef __OBJC__\r\n            // In Objective-C try objective-c exceptions first\r\n            @try {\r\n                return tryTranslators();\r\n            }\r\n            @catch (NSException *exception) {\r\n                return Catch::Detail::stringify( [exception description] );\r\n            }\r\n#else\r\n            // Compiling a mixed mode project with MSVC means that CLR\r\n            // exceptions will be caught in (...) as well. However, these\r\n            // do not fill-in std::current_exception and thus lead to crash\r\n            // when attempting rethrow.\r\n            // /EHa switch also causes structured exceptions to be caught\r\n            // here, but they fill-in current_exception properly, so\r\n            // at worst the output should be a little weird, instead of\r\n            // causing a crash.\r\n            if (std::current_exception() == nullptr) {\r\n                return \"Non C++ exception. Possibly a CLR exception.\";\r\n            }\r\n            return tryTranslators();\r\n#endif\r\n        }\r\n        catch( TestFailureException& ) {\r\n            std::rethrow_exception(std::current_exception());\r\n        }\r\n        catch( std::exception& ex ) {\r\n            return ex.what();\r\n        }\r\n        catch( std::string& msg ) {\r\n            return msg;\r\n        }\r\n        catch( const char* msg ) {\r\n            return msg;\r\n        }\r\n        catch(...) {\r\n            return \"Unknown exception\";\r\n        }\r\n    }\r\n\r\n    std::string ExceptionTranslatorRegistry::tryTranslators() const {\r\n        if (m_translators.empty()) {\r\n            std::rethrow_exception(std::current_exception());\r\n        } else {\r\n            return m_translators[0]->translate(m_translators.begin() + 1, m_translators.end());\r\n        }\r\n    }\r\n\r\n#else // ^^ Exceptions are enabled // Exceptions are disabled vv\r\n    std::string ExceptionTranslatorRegistry::translateActiveException() const {\r\n        CATCH_INTERNAL_ERROR(\"Attempted to translate active exception under CATCH_CONFIG_DISABLE_EXCEPTIONS!\");\r\n    }\r\n\r\n    std::string ExceptionTranslatorRegistry::tryTranslators() const {\r\n        CATCH_INTERNAL_ERROR(\"Attempted to use exception translators under CATCH_CONFIG_DISABLE_EXCEPTIONS!\");\r\n    }\r\n#endif\r\n\r\n}\r\n// end catch_exception_translator_registry.cpp\r\n// start catch_fatal_condition.cpp\r\n\r\n#if defined(__GNUC__)\r\n#    pragma GCC diagnostic push\r\n#    pragma GCC diagnostic ignored \"-Wmissing-field-initializers\"\r\n#endif\r\n\r\n#if defined( CATCH_CONFIG_WINDOWS_SEH ) || defined( CATCH_CONFIG_POSIX_SIGNALS )\r\n\r\nnamespace {\r\n    // Report the error condition\r\n    void reportFatal( char const * const message ) {\r\n        Catch::getCurrentContext().getResultCapture()->handleFatalErrorCondition( message );\r\n    }\r\n}\r\n\r\n#endif // signals/SEH handling\r\n\r\n#if defined( CATCH_CONFIG_WINDOWS_SEH )\r\n\r\nnamespace Catch {\r\n    struct SignalDefs { DWORD id; const char* name; };\r\n\r\n    // There is no 1-1 mapping between signals and windows exceptions.\r\n    // Windows can easily distinguish between SO and SigSegV,\r\n    // but SigInt, SigTerm, etc are handled differently.\r\n    static SignalDefs signalDefs[] = {\r\n        { EXCEPTION_ILLEGAL_INSTRUCTION,  \"SIGILL - Illegal instruction signal\" },\r\n        { EXCEPTION_STACK_OVERFLOW, \"SIGSEGV - Stack overflow\" },\r\n        { EXCEPTION_ACCESS_VIOLATION, \"SIGSEGV - Segmentation violation signal\" },\r\n        { EXCEPTION_INT_DIVIDE_BY_ZERO, \"Divide by zero error\" },\r\n    };\r\n\r\n    LONG CALLBACK FatalConditionHandler::handleVectoredException(PEXCEPTION_POINTERS ExceptionInfo) {\r\n        for (auto const& def : signalDefs) {\r\n            if (ExceptionInfo->ExceptionRecord->ExceptionCode == def.id) {\r\n                reportFatal(def.name);\r\n            }\r\n        }\r\n        // If its not an exception we care about, pass it along.\r\n        // This stops us from eating debugger breaks etc.\r\n        return EXCEPTION_CONTINUE_SEARCH;\r\n    }\r\n\r\n    FatalConditionHandler::FatalConditionHandler() {\r\n        isSet = true;\r\n        // 32k seems enough for Catch to handle stack overflow,\r\n        // but the value was found experimentally, so there is no strong guarantee\r\n        guaranteeSize = 32 * 1024;\r\n        exceptionHandlerHandle = nullptr;\r\n        // Register as first handler in current chain\r\n        exceptionHandlerHandle = AddVectoredExceptionHandler(1, handleVectoredException);\r\n        // Pass in guarantee size to be filled\r\n        SetThreadStackGuarantee(&guaranteeSize);\r\n    }\r\n\r\n    void FatalConditionHandler::reset() {\r\n        if (isSet) {\r\n            RemoveVectoredExceptionHandler(exceptionHandlerHandle);\r\n            SetThreadStackGuarantee(&guaranteeSize);\r\n            exceptionHandlerHandle = nullptr;\r\n            isSet = false;\r\n        }\r\n    }\r\n\r\n    FatalConditionHandler::~FatalConditionHandler() {\r\n        reset();\r\n    }\r\n\r\nbool FatalConditionHandler::isSet = false;\r\nULONG FatalConditionHandler::guaranteeSize = 0;\r\nPVOID FatalConditionHandler::exceptionHandlerHandle = nullptr;\r\n\r\n} // namespace Catch\r\n\r\n#elif defined( CATCH_CONFIG_POSIX_SIGNALS )\r\n\r\nnamespace Catch {\r\n\r\n    struct SignalDefs {\r\n        int id;\r\n        const char* name;\r\n    };\r\n\r\n    // 32kb for the alternate stack seems to be sufficient. However, this value\r\n    // is experimentally determined, so that's not guaranteed.\r\n    constexpr static std::size_t sigStackSize = 32768 >= MINSIGSTKSZ ? 32768 : MINSIGSTKSZ;\r\n\r\n    static SignalDefs signalDefs[] = {\r\n        { SIGINT,  \"SIGINT - Terminal interrupt signal\" },\r\n        { SIGILL,  \"SIGILL - Illegal instruction signal\" },\r\n        { SIGFPE,  \"SIGFPE - Floating point error signal\" },\r\n        { SIGSEGV, \"SIGSEGV - Segmentation violation signal\" },\r\n        { SIGTERM, \"SIGTERM - Termination request signal\" },\r\n        { SIGABRT, \"SIGABRT - Abort (abnormal termination) signal\" }\r\n    };\r\n\r\n    void FatalConditionHandler::handleSignal( int sig ) {\r\n        char const * name = \"<unknown signal>\";\r\n        for (auto const& def : signalDefs) {\r\n            if (sig == def.id) {\r\n                name = def.name;\r\n                break;\r\n            }\r\n        }\r\n        reset();\r\n        reportFatal(name);\r\n        raise( sig );\r\n    }\r\n\r\n    FatalConditionHandler::FatalConditionHandler() {\r\n        isSet = true;\r\n        stack_t sigStack;\r\n        sigStack.ss_sp = altStackMem;\r\n        sigStack.ss_size = sigStackSize;\r\n        sigStack.ss_flags = 0;\r\n        sigaltstack(&sigStack, &oldSigStack);\r\n        struct sigaction sa = { };\r\n\r\n        sa.sa_handler = handleSignal;\r\n        sa.sa_flags = SA_ONSTACK;\r\n        for (std::size_t i = 0; i < sizeof(signalDefs)/sizeof(SignalDefs); ++i) {\r\n            sigaction(signalDefs[i].id, &sa, &oldSigActions[i]);\r\n        }\r\n    }\r\n\r\n    FatalConditionHandler::~FatalConditionHandler() {\r\n        reset();\r\n    }\r\n\r\n    void FatalConditionHandler::reset() {\r\n        if( isSet ) {\r\n            // Set signals back to previous values -- hopefully nobody overwrote them in the meantime\r\n            for( std::size_t i = 0; i < sizeof(signalDefs)/sizeof(SignalDefs); ++i ) {\r\n                sigaction(signalDefs[i].id, &oldSigActions[i], nullptr);\r\n            }\r\n            // Return the old stack\r\n            sigaltstack(&oldSigStack, nullptr);\r\n            isSet = false;\r\n        }\r\n    }\r\n\r\n    bool FatalConditionHandler::isSet = false;\r\n    struct sigaction FatalConditionHandler::oldSigActions[sizeof(signalDefs)/sizeof(SignalDefs)] = {};\r\n    stack_t FatalConditionHandler::oldSigStack = {};\r\n    char FatalConditionHandler::altStackMem[sigStackSize] = {};\r\n\r\n} // namespace Catch\r\n\r\n#else\r\n\r\nnamespace Catch {\r\n    void FatalConditionHandler::reset() {}\r\n}\r\n\r\n#endif // signals/SEH handling\r\n\r\n#if defined(__GNUC__)\r\n#    pragma GCC diagnostic pop\r\n#endif\r\n// end catch_fatal_condition.cpp\r\n// start catch_generators.cpp\r\n\r\n// start catch_random_number_generator.h\r\n\r\n#include <algorithm>\r\n#include <random>\r\n\r\nnamespace Catch {\r\n\r\n    struct IConfig;\r\n\r\n    std::mt19937& rng();\r\n    void seedRng( IConfig const& config );\r\n    unsigned int rngSeed();\r\n\r\n}\r\n\r\n// end catch_random_number_generator.h\r\n#include <limits>\r\n#include <set>\r\n\r\nnamespace Catch {\r\n\r\nIGeneratorTracker::~IGeneratorTracker() {}\r\n\r\nconst char* GeneratorException::what() const noexcept {\r\n    return m_msg;\r\n}\r\n\r\nnamespace Generators {\r\n\r\n    GeneratorUntypedBase::~GeneratorUntypedBase() {}\r\n\r\n    auto acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker& {\r\n        return getResultCapture().acquireGeneratorTracker( lineInfo );\r\n    }\r\n\r\n} // namespace Generators\r\n} // namespace Catch\r\n// end catch_generators.cpp\r\n// start catch_interfaces_capture.cpp\r\n\r\nnamespace Catch {\r\n    IResultCapture::~IResultCapture() = default;\r\n}\r\n// end catch_interfaces_capture.cpp\r\n// start catch_interfaces_config.cpp\r\n\r\nnamespace Catch {\r\n    IConfig::~IConfig() = default;\r\n}\r\n// end catch_interfaces_config.cpp\r\n// start catch_interfaces_exception.cpp\r\n\r\nnamespace Catch {\r\n    IExceptionTranslator::~IExceptionTranslator() = default;\r\n    IExceptionTranslatorRegistry::~IExceptionTranslatorRegistry() = default;\r\n}\r\n// end catch_interfaces_exception.cpp\r\n// start catch_interfaces_registry_hub.cpp\r\n\r\nnamespace Catch {\r\n    IRegistryHub::~IRegistryHub() = default;\r\n    IMutableRegistryHub::~IMutableRegistryHub() = default;\r\n}\r\n// end catch_interfaces_registry_hub.cpp\r\n// start catch_interfaces_reporter.cpp\r\n\r\n// start catch_reporter_listening.h\r\n\r\nnamespace Catch {\r\n\r\n    class ListeningReporter : public IStreamingReporter {\r\n        using Reporters = std::vector<IStreamingReporterPtr>;\r\n        Reporters m_listeners;\r\n        IStreamingReporterPtr m_reporter = nullptr;\r\n        ReporterPreferences m_preferences;\r\n\r\n    public:\r\n        ListeningReporter();\r\n\r\n        void addListener( IStreamingReporterPtr&& listener );\r\n        void addReporter( IStreamingReporterPtr&& reporter );\r\n\r\n    public: // IStreamingReporter\r\n\r\n        ReporterPreferences getPreferences() const override;\r\n\r\n        void noMatchingTestCases( std::string const& spec ) override;\r\n\r\n        static std::set<Verbosity> getSupportedVerbosities();\r\n\r\n        void benchmarkStarting( BenchmarkInfo const& benchmarkInfo ) override;\r\n        void benchmarkEnded( BenchmarkStats const& benchmarkStats ) override;\r\n\r\n        void testRunStarting( TestRunInfo const& testRunInfo ) override;\r\n        void testGroupStarting( GroupInfo const& groupInfo ) override;\r\n        void testCaseStarting( TestCaseInfo const& testInfo ) override;\r\n        void sectionStarting( SectionInfo const& sectionInfo ) override;\r\n        void assertionStarting( AssertionInfo const& assertionInfo ) override;\r\n\r\n        // The return value indicates if the messages buffer should be cleared:\r\n        bool assertionEnded( AssertionStats const& assertionStats ) override;\r\n        void sectionEnded( SectionStats const& sectionStats ) override;\r\n        void testCaseEnded( TestCaseStats const& testCaseStats ) override;\r\n        void testGroupEnded( TestGroupStats const& testGroupStats ) override;\r\n        void testRunEnded( TestRunStats const& testRunStats ) override;\r\n\r\n        void skipTest( TestCaseInfo const& testInfo ) override;\r\n        bool isMulti() const override;\r\n\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_reporter_listening.h\r\nnamespace Catch {\r\n\r\n    ReporterConfig::ReporterConfig( IConfigPtr const& _fullConfig )\r\n    :   m_stream( &_fullConfig->stream() ), m_fullConfig( _fullConfig ) {}\r\n\r\n    ReporterConfig::ReporterConfig( IConfigPtr const& _fullConfig, std::ostream& _stream )\r\n    :   m_stream( &_stream ), m_fullConfig( _fullConfig ) {}\r\n\r\n    std::ostream& ReporterConfig::stream() const { return *m_stream; }\r\n    IConfigPtr ReporterConfig::fullConfig() const { return m_fullConfig; }\r\n\r\n    TestRunInfo::TestRunInfo( std::string const& _name ) : name( _name ) {}\r\n\r\n    GroupInfo::GroupInfo(  std::string const& _name,\r\n                           std::size_t _groupIndex,\r\n                           std::size_t _groupsCount )\r\n    :   name( _name ),\r\n        groupIndex( _groupIndex ),\r\n        groupsCounts( _groupsCount )\r\n    {}\r\n\r\n     AssertionStats::AssertionStats( AssertionResult const& _assertionResult,\r\n                                     std::vector<MessageInfo> const& _infoMessages,\r\n                                     Totals const& _totals )\r\n    :   assertionResult( _assertionResult ),\r\n        infoMessages( _infoMessages ),\r\n        totals( _totals )\r\n    {\r\n        assertionResult.m_resultData.lazyExpression.m_transientExpression = _assertionResult.m_resultData.lazyExpression.m_transientExpression;\r\n\r\n        if( assertionResult.hasMessage() ) {\r\n            // Copy message into messages list.\r\n            // !TBD This should have been done earlier, somewhere\r\n            MessageBuilder builder( assertionResult.getTestMacroName(), assertionResult.getSourceInfo(), assertionResult.getResultType() );\r\n            builder << assertionResult.getMessage();\r\n            builder.m_info.message = builder.m_stream.str();\r\n\r\n            infoMessages.push_back( builder.m_info );\r\n        }\r\n    }\r\n\r\n     AssertionStats::~AssertionStats() = default;\r\n\r\n    SectionStats::SectionStats(  SectionInfo const& _sectionInfo,\r\n                                 Counts const& _assertions,\r\n                                 double _durationInSeconds,\r\n                                 bool _missingAssertions )\r\n    :   sectionInfo( _sectionInfo ),\r\n        assertions( _assertions ),\r\n        durationInSeconds( _durationInSeconds ),\r\n        missingAssertions( _missingAssertions )\r\n    {}\r\n\r\n    SectionStats::~SectionStats() = default;\r\n\r\n    TestCaseStats::TestCaseStats(  TestCaseInfo const& _testInfo,\r\n                                   Totals const& _totals,\r\n                                   std::string const& _stdOut,\r\n                                   std::string const& _stdErr,\r\n                                   bool _aborting )\r\n    : testInfo( _testInfo ),\r\n        totals( _totals ),\r\n        stdOut( _stdOut ),\r\n        stdErr( _stdErr ),\r\n        aborting( _aborting )\r\n    {}\r\n\r\n    TestCaseStats::~TestCaseStats() = default;\r\n\r\n    TestGroupStats::TestGroupStats( GroupInfo const& _groupInfo,\r\n                                    Totals const& _totals,\r\n                                    bool _aborting )\r\n    :   groupInfo( _groupInfo ),\r\n        totals( _totals ),\r\n        aborting( _aborting )\r\n    {}\r\n\r\n    TestGroupStats::TestGroupStats( GroupInfo const& _groupInfo )\r\n    :   groupInfo( _groupInfo ),\r\n        aborting( false )\r\n    {}\r\n\r\n    TestGroupStats::~TestGroupStats() = default;\r\n\r\n    TestRunStats::TestRunStats(   TestRunInfo const& _runInfo,\r\n                    Totals const& _totals,\r\n                    bool _aborting )\r\n    :   runInfo( _runInfo ),\r\n        totals( _totals ),\r\n        aborting( _aborting )\r\n    {}\r\n\r\n    TestRunStats::~TestRunStats() = default;\r\n\r\n    void IStreamingReporter::fatalErrorEncountered( StringRef ) {}\r\n    bool IStreamingReporter::isMulti() const { return false; }\r\n\r\n    IReporterFactory::~IReporterFactory() = default;\r\n    IReporterRegistry::~IReporterRegistry() = default;\r\n\r\n} // end namespace Catch\r\n// end catch_interfaces_reporter.cpp\r\n// start catch_interfaces_runner.cpp\r\n\r\nnamespace Catch {\r\n    IRunner::~IRunner() = default;\r\n}\r\n// end catch_interfaces_runner.cpp\r\n// start catch_interfaces_testcase.cpp\r\n\r\nnamespace Catch {\r\n    ITestInvoker::~ITestInvoker() = default;\r\n    ITestCaseRegistry::~ITestCaseRegistry() = default;\r\n}\r\n// end catch_interfaces_testcase.cpp\r\n// start catch_leak_detector.cpp\r\n\r\n#ifdef CATCH_CONFIG_WINDOWS_CRTDBG\r\n#include <crtdbg.h>\r\n\r\nnamespace Catch {\r\n\r\n    LeakDetector::LeakDetector() {\r\n        int flag = _CrtSetDbgFlag(_CRTDBG_REPORT_FLAG);\r\n        flag |= _CRTDBG_LEAK_CHECK_DF;\r\n        flag |= _CRTDBG_ALLOC_MEM_DF;\r\n        _CrtSetDbgFlag(flag);\r\n        _CrtSetReportMode(_CRT_WARN, _CRTDBG_MODE_FILE | _CRTDBG_MODE_DEBUG);\r\n        _CrtSetReportFile(_CRT_WARN, _CRTDBG_FILE_STDERR);\r\n        // Change this to leaking allocation's number to break there\r\n        _CrtSetBreakAlloc(-1);\r\n    }\r\n}\r\n\r\n#else\r\n\r\n    Catch::LeakDetector::LeakDetector() {}\r\n\r\n#endif\r\n\r\nCatch::LeakDetector::~LeakDetector() {\r\n    Catch::cleanUp();\r\n}\r\n// end catch_leak_detector.cpp\r\n// start catch_list.cpp\r\n\r\n// start catch_list.h\r\n\r\n#include <set>\r\n\r\nnamespace Catch {\r\n\r\n    std::size_t listTests( Config const& config );\r\n\r\n    std::size_t listTestsNamesOnly( Config const& config );\r\n\r\n    struct TagInfo {\r\n        void add( std::string const& spelling );\r\n        std::string all() const;\r\n\r\n        std::set<std::string> spellings;\r\n        std::size_t count = 0;\r\n    };\r\n\r\n    std::size_t listTags( Config const& config );\r\n\r\n    std::size_t listReporters();\r\n\r\n    Option<std::size_t> list( std::shared_ptr<Config> const& config );\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_list.h\r\n// start catch_text.h\r\n\r\nnamespace Catch {\r\n    using namespace clara::TextFlow;\r\n}\r\n\r\n// end catch_text.h\r\n#include <limits>\r\n#include <algorithm>\r\n#include <iomanip>\r\n\r\nnamespace Catch {\r\n\r\n    std::size_t listTests( Config const& config ) {\r\n        TestSpec testSpec = config.testSpec();\r\n        if( config.hasTestFilters() )\r\n            Catch::cout() << \"Matching test cases:\\n\";\r\n        else {\r\n            Catch::cout() << \"All available test cases:\\n\";\r\n        }\r\n\r\n        auto matchedTestCases = filterTests( getAllTestCasesSorted( config ), testSpec, config );\r\n        for( auto const& testCaseInfo : matchedTestCases ) {\r\n            Colour::Code colour = testCaseInfo.isHidden()\r\n                ? Colour::SecondaryText\r\n                : Colour::None;\r\n            Colour colourGuard( colour );\r\n\r\n            Catch::cout() << Column( testCaseInfo.name ).initialIndent( 2 ).indent( 4 ) << \"\\n\";\r\n            if( config.verbosity() >= Verbosity::High ) {\r\n                Catch::cout() << Column( Catch::Detail::stringify( testCaseInfo.lineInfo ) ).indent(4) << std::endl;\r\n                std::string description = testCaseInfo.description;\r\n                if( description.empty() )\r\n                    description = \"(NO DESCRIPTION)\";\r\n                Catch::cout() << Column( description ).indent(4) << std::endl;\r\n            }\r\n            if( !testCaseInfo.tags.empty() )\r\n                Catch::cout() << Column( testCaseInfo.tagsAsString() ).indent( 6 ) << \"\\n\";\r\n        }\r\n\r\n        if( !config.hasTestFilters() )\r\n            Catch::cout() << pluralise( matchedTestCases.size(), \"test case\" ) << '\\n' << std::endl;\r\n        else\r\n            Catch::cout() << pluralise( matchedTestCases.size(), \"matching test case\" ) << '\\n' << std::endl;\r\n        return matchedTestCases.size();\r\n    }\r\n\r\n    std::size_t listTestsNamesOnly( Config const& config ) {\r\n        TestSpec testSpec = config.testSpec();\r\n        std::size_t matchedTests = 0;\r\n        std::vector<TestCase> matchedTestCases = filterTests( getAllTestCasesSorted( config ), testSpec, config );\r\n        for( auto const& testCaseInfo : matchedTestCases ) {\r\n            matchedTests++;\r\n            if( startsWith( testCaseInfo.name, '#' ) )\r\n               Catch::cout() << '\"' << testCaseInfo.name << '\"';\r\n            else\r\n               Catch::cout() << testCaseInfo.name;\r\n            if ( config.verbosity() >= Verbosity::High )\r\n                Catch::cout() << \"\\t@\" << testCaseInfo.lineInfo;\r\n            Catch::cout() << std::endl;\r\n        }\r\n        return matchedTests;\r\n    }\r\n\r\n    void TagInfo::add( std::string const& spelling ) {\r\n        ++count;\r\n        spellings.insert( spelling );\r\n    }\r\n\r\n    std::string TagInfo::all() const {\r\n        std::string out;\r\n        for( auto const& spelling : spellings )\r\n            out += \"[\" + spelling + \"]\";\r\n        return out;\r\n    }\r\n\r\n    std::size_t listTags( Config const& config ) {\r\n        TestSpec testSpec = config.testSpec();\r\n        if( config.hasTestFilters() )\r\n            Catch::cout() << \"Tags for matching test cases:\\n\";\r\n        else {\r\n            Catch::cout() << \"All available tags:\\n\";\r\n        }\r\n\r\n        std::map<std::string, TagInfo> tagCounts;\r\n\r\n        std::vector<TestCase> matchedTestCases = filterTests( getAllTestCasesSorted( config ), testSpec, config );\r\n        for( auto const& testCase : matchedTestCases ) {\r\n            for( auto const& tagName : testCase.getTestCaseInfo().tags ) {\r\n                std::string lcaseTagName = toLower( tagName );\r\n                auto countIt = tagCounts.find( lcaseTagName );\r\n                if( countIt == tagCounts.end() )\r\n                    countIt = tagCounts.insert( std::make_pair( lcaseTagName, TagInfo() ) ).first;\r\n                countIt->second.add( tagName );\r\n            }\r\n        }\r\n\r\n        for( auto const& tagCount : tagCounts ) {\r\n            ReusableStringStream rss;\r\n            rss << \"  \" << std::setw(2) << tagCount.second.count << \"  \";\r\n            auto str = rss.str();\r\n            auto wrapper = Column( tagCount.second.all() )\r\n                                                    .initialIndent( 0 )\r\n                                                    .indent( str.size() )\r\n                                                    .width( CATCH_CONFIG_CONSOLE_WIDTH-10 );\r\n            Catch::cout() << str << wrapper << '\\n';\r\n        }\r\n        Catch::cout() << pluralise( tagCounts.size(), \"tag\" ) << '\\n' << std::endl;\r\n        return tagCounts.size();\r\n    }\r\n\r\n    std::size_t listReporters() {\r\n        Catch::cout() << \"Available reporters:\\n\";\r\n        IReporterRegistry::FactoryMap const& factories = getRegistryHub().getReporterRegistry().getFactories();\r\n        std::size_t maxNameLen = 0;\r\n        for( auto const& factoryKvp : factories )\r\n            maxNameLen = (std::max)( maxNameLen, factoryKvp.first.size() );\r\n\r\n        for( auto const& factoryKvp : factories ) {\r\n            Catch::cout()\r\n                    << Column( factoryKvp.first + \":\" )\r\n                            .indent(2)\r\n                            .width( 5+maxNameLen )\r\n                    +  Column( factoryKvp.second->getDescription() )\r\n                            .initialIndent(0)\r\n                            .indent(2)\r\n                            .width( CATCH_CONFIG_CONSOLE_WIDTH - maxNameLen-8 )\r\n                    << \"\\n\";\r\n        }\r\n        Catch::cout() << std::endl;\r\n        return factories.size();\r\n    }\r\n\r\n    Option<std::size_t> list( std::shared_ptr<Config> const& config ) {\r\n        Option<std::size_t> listedCount;\r\n        getCurrentMutableContext().setConfig( config );\r\n        if( config->listTests() )\r\n            listedCount = listedCount.valueOr(0) + listTests( *config );\r\n        if( config->listTestNamesOnly() )\r\n            listedCount = listedCount.valueOr(0) + listTestsNamesOnly( *config );\r\n        if( config->listTags() )\r\n            listedCount = listedCount.valueOr(0) + listTags( *config );\r\n        if( config->listReporters() )\r\n            listedCount = listedCount.valueOr(0) + listReporters();\r\n        return listedCount;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_list.cpp\r\n// start catch_matchers.cpp\r\n\r\nnamespace Catch {\r\nnamespace Matchers {\r\n    namespace Impl {\r\n\r\n        std::string MatcherUntypedBase::toString() const {\r\n            if( m_cachedToString.empty() )\r\n                m_cachedToString = describe();\r\n            return m_cachedToString;\r\n        }\r\n\r\n        MatcherUntypedBase::~MatcherUntypedBase() = default;\r\n\r\n    } // namespace Impl\r\n} // namespace Matchers\r\n\r\nusing namespace Matchers;\r\nusing Matchers::Impl::MatcherBase;\r\n\r\n} // namespace Catch\r\n// end catch_matchers.cpp\r\n// start catch_matchers_floating.cpp\r\n\r\n// start catch_polyfills.hpp\r\n\r\nnamespace Catch {\r\n    bool isnan(float f);\r\n    bool isnan(double d);\r\n}\r\n\r\n// end catch_polyfills.hpp\r\n// start catch_to_string.hpp\r\n\r\n#include <string>\r\n\r\nnamespace Catch {\r\n    template <typename T>\r\n    std::string to_string(T const& t) {\r\n#if defined(CATCH_CONFIG_CPP11_TO_STRING)\r\n        return std::to_string(t);\r\n#else\r\n        ReusableStringStream rss;\r\n        rss << t;\r\n        return rss.str();\r\n#endif\r\n    }\r\n} // end namespace Catch\r\n\r\n// end catch_to_string.hpp\r\n#include <cstdlib>\r\n#include <cstdint>\r\n#include <cstring>\r\n\r\nnamespace Catch {\r\nnamespace Matchers {\r\nnamespace Floating {\r\nenum class FloatingPointKind : uint8_t {\r\n    Float,\r\n    Double\r\n};\r\n}\r\n}\r\n}\r\n\r\nnamespace {\r\n\r\ntemplate <typename T>\r\nstruct Converter;\r\n\r\ntemplate <>\r\nstruct Converter<float> {\r\n    static_assert(sizeof(float) == sizeof(int32_t), \"Important ULP matcher assumption violated\");\r\n    Converter(float f) {\r\n        std::memcpy(&i, &f, sizeof(f));\r\n    }\r\n    int32_t i;\r\n};\r\n\r\ntemplate <>\r\nstruct Converter<double> {\r\n    static_assert(sizeof(double) == sizeof(int64_t), \"Important ULP matcher assumption violated\");\r\n    Converter(double d) {\r\n        std::memcpy(&i, &d, sizeof(d));\r\n    }\r\n    int64_t i;\r\n};\r\n\r\ntemplate <typename T>\r\nauto convert(T t) -> Converter<T> {\r\n    return Converter<T>(t);\r\n}\r\n\r\ntemplate <typename FP>\r\nbool almostEqualUlps(FP lhs, FP rhs, int maxUlpDiff) {\r\n    // Comparison with NaN should always be false.\r\n    // This way we can rule it out before getting into the ugly details\r\n    if (Catch::isnan(lhs) || Catch::isnan(rhs)) {\r\n        return false;\r\n    }\r\n\r\n    auto lc = convert(lhs);\r\n    auto rc = convert(rhs);\r\n\r\n    if ((lc.i < 0) != (rc.i < 0)) {\r\n        // Potentially we can have +0 and -0\r\n        return lhs == rhs;\r\n    }\r\n\r\n    auto ulpDiff = std::abs(lc.i - rc.i);\r\n    return ulpDiff <= maxUlpDiff;\r\n}\r\n\r\n}\r\n\r\nnamespace Catch {\r\nnamespace Matchers {\r\nnamespace Floating {\r\n    WithinAbsMatcher::WithinAbsMatcher(double target, double margin)\r\n        :m_target{ target }, m_margin{ margin } {\r\n        CATCH_ENFORCE(margin >= 0, \"Invalid margin: \" << margin << '.'\r\n            << \" Margin has to be non-negative.\");\r\n    }\r\n\r\n    // Performs equivalent check of std::fabs(lhs - rhs) <= margin\r\n    // But without the subtraction to allow for INFINITY in comparison\r\n    bool WithinAbsMatcher::match(double const& matchee) const {\r\n        return (matchee + m_margin >= m_target) && (m_target + m_margin >= matchee);\r\n    }\r\n\r\n    std::string WithinAbsMatcher::describe() const {\r\n        return \"is within \" + ::Catch::Detail::stringify(m_margin) + \" of \" + ::Catch::Detail::stringify(m_target);\r\n    }\r\n\r\n    WithinUlpsMatcher::WithinUlpsMatcher(double target, int ulps, FloatingPointKind baseType)\r\n        :m_target{ target }, m_ulps{ ulps }, m_type{ baseType } {\r\n        CATCH_ENFORCE(ulps >= 0, \"Invalid ULP setting: \" << ulps << '.'\r\n            << \" ULPs have to be non-negative.\");\r\n    }\r\n\r\n#if defined(__clang__)\r\n#pragma clang diagnostic push\r\n// Clang <3.5 reports on the default branch in the switch below\r\n#pragma clang diagnostic ignored \"-Wunreachable-code\"\r\n#endif\r\n\r\n    bool WithinUlpsMatcher::match(double const& matchee) const {\r\n        switch (m_type) {\r\n        case FloatingPointKind::Float:\r\n            return almostEqualUlps<float>(static_cast<float>(matchee), static_cast<float>(m_target), m_ulps);\r\n        case FloatingPointKind::Double:\r\n            return almostEqualUlps<double>(matchee, m_target, m_ulps);\r\n        default:\r\n            CATCH_INTERNAL_ERROR( \"Unknown FloatingPointKind value\" );\r\n        }\r\n    }\r\n\r\n#if defined(__clang__)\r\n#pragma clang diagnostic pop\r\n#endif\r\n\r\n    std::string WithinUlpsMatcher::describe() const {\r\n        return \"is within \" + Catch::to_string(m_ulps) + \" ULPs of \" + ::Catch::Detail::stringify(m_target) + ((m_type == FloatingPointKind::Float)? \"f\" : \"\");\r\n    }\r\n\r\n}// namespace Floating\r\n\r\nFloating::WithinUlpsMatcher WithinULP(double target, int maxUlpDiff) {\r\n    return Floating::WithinUlpsMatcher(target, maxUlpDiff, Floating::FloatingPointKind::Double);\r\n}\r\n\r\nFloating::WithinUlpsMatcher WithinULP(float target, int maxUlpDiff) {\r\n    return Floating::WithinUlpsMatcher(target, maxUlpDiff, Floating::FloatingPointKind::Float);\r\n}\r\n\r\nFloating::WithinAbsMatcher WithinAbs(double target, double margin) {\r\n    return Floating::WithinAbsMatcher(target, margin);\r\n}\r\n\r\n} // namespace Matchers\r\n} // namespace Catch\r\n\r\n// end catch_matchers_floating.cpp\r\n// start catch_matchers_generic.cpp\r\n\r\nstd::string Catch::Matchers::Generic::Detail::finalizeDescription(const std::string& desc) {\r\n    if (desc.empty()) {\r\n        return \"matches undescribed predicate\";\r\n    } else {\r\n        return \"matches predicate: \\\"\" + desc + '\"';\r\n    }\r\n}\r\n// end catch_matchers_generic.cpp\r\n// start catch_matchers_string.cpp\r\n\r\n#include <regex>\r\n\r\nnamespace Catch {\r\nnamespace Matchers {\r\n\r\n    namespace StdString {\r\n\r\n        CasedString::CasedString( std::string const& str, CaseSensitive::Choice caseSensitivity )\r\n        :   m_caseSensitivity( caseSensitivity ),\r\n            m_str( adjustString( str ) )\r\n        {}\r\n        std::string CasedString::adjustString( std::string const& str ) const {\r\n            return m_caseSensitivity == CaseSensitive::No\r\n                   ? toLower( str )\r\n                   : str;\r\n        }\r\n        std::string CasedString::caseSensitivitySuffix() const {\r\n            return m_caseSensitivity == CaseSensitive::No\r\n                   ? \" (case insensitive)\"\r\n                   : std::string();\r\n        }\r\n\r\n        StringMatcherBase::StringMatcherBase( std::string const& operation, CasedString const& comparator )\r\n        : m_comparator( comparator ),\r\n          m_operation( operation ) {\r\n        }\r\n\r\n        std::string StringMatcherBase::describe() const {\r\n            std::string description;\r\n            description.reserve(5 + m_operation.size() + m_comparator.m_str.size() +\r\n                                        m_comparator.caseSensitivitySuffix().size());\r\n            description += m_operation;\r\n            description += \": \\\"\";\r\n            description += m_comparator.m_str;\r\n            description += \"\\\"\";\r\n            description += m_comparator.caseSensitivitySuffix();\r\n            return description;\r\n        }\r\n\r\n        EqualsMatcher::EqualsMatcher( CasedString const& comparator ) : StringMatcherBase( \"equals\", comparator ) {}\r\n\r\n        bool EqualsMatcher::match( std::string const& source ) const {\r\n            return m_comparator.adjustString( source ) == m_comparator.m_str;\r\n        }\r\n\r\n        ContainsMatcher::ContainsMatcher( CasedString const& comparator ) : StringMatcherBase( \"contains\", comparator ) {}\r\n\r\n        bool ContainsMatcher::match( std::string const& source ) const {\r\n            return contains( m_comparator.adjustString( source ), m_comparator.m_str );\r\n        }\r\n\r\n        StartsWithMatcher::StartsWithMatcher( CasedString const& comparator ) : StringMatcherBase( \"starts with\", comparator ) {}\r\n\r\n        bool StartsWithMatcher::match( std::string const& source ) const {\r\n            return startsWith( m_comparator.adjustString( source ), m_comparator.m_str );\r\n        }\r\n\r\n        EndsWithMatcher::EndsWithMatcher( CasedString const& comparator ) : StringMatcherBase( \"ends with\", comparator ) {}\r\n\r\n        bool EndsWithMatcher::match( std::string const& source ) const {\r\n            return endsWith( m_comparator.adjustString( source ), m_comparator.m_str );\r\n        }\r\n\r\n        RegexMatcher::RegexMatcher(std::string regex, CaseSensitive::Choice caseSensitivity): m_regex(std::move(regex)), m_caseSensitivity(caseSensitivity) {}\r\n\r\n        bool RegexMatcher::match(std::string const& matchee) const {\r\n            auto flags = std::regex::ECMAScript; // ECMAScript is the default syntax option anyway\r\n            if (m_caseSensitivity == CaseSensitive::Choice::No) {\r\n                flags |= std::regex::icase;\r\n            }\r\n            auto reg = std::regex(m_regex, flags);\r\n            return std::regex_match(matchee, reg);\r\n        }\r\n\r\n        std::string RegexMatcher::describe() const {\r\n            return \"matches \" + ::Catch::Detail::stringify(m_regex) + ((m_caseSensitivity == CaseSensitive::Choice::Yes)? \" case sensitively\" : \" case insensitively\");\r\n        }\r\n\r\n    } // namespace StdString\r\n\r\n    StdString::EqualsMatcher Equals( std::string const& str, CaseSensitive::Choice caseSensitivity ) {\r\n        return StdString::EqualsMatcher( StdString::CasedString( str, caseSensitivity) );\r\n    }\r\n    StdString::ContainsMatcher Contains( std::string const& str, CaseSensitive::Choice caseSensitivity ) {\r\n        return StdString::ContainsMatcher( StdString::CasedString( str, caseSensitivity) );\r\n    }\r\n    StdString::EndsWithMatcher EndsWith( std::string const& str, CaseSensitive::Choice caseSensitivity ) {\r\n        return StdString::EndsWithMatcher( StdString::CasedString( str, caseSensitivity) );\r\n    }\r\n    StdString::StartsWithMatcher StartsWith( std::string const& str, CaseSensitive::Choice caseSensitivity ) {\r\n        return StdString::StartsWithMatcher( StdString::CasedString( str, caseSensitivity) );\r\n    }\r\n\r\n    StdString::RegexMatcher Matches(std::string const& regex, CaseSensitive::Choice caseSensitivity) {\r\n        return StdString::RegexMatcher(regex, caseSensitivity);\r\n    }\r\n\r\n} // namespace Matchers\r\n} // namespace Catch\r\n// end catch_matchers_string.cpp\r\n// start catch_message.cpp\r\n\r\n// start catch_uncaught_exceptions.h\r\n\r\nnamespace Catch {\r\n    bool uncaught_exceptions();\r\n} // end namespace Catch\r\n\r\n// end catch_uncaught_exceptions.h\r\n#include <cassert>\r\n#include <stack>\r\n\r\nnamespace Catch {\r\n\r\n    MessageInfo::MessageInfo(   StringRef const& _macroName,\r\n                                SourceLineInfo const& _lineInfo,\r\n                                ResultWas::OfType _type )\r\n    :   macroName( _macroName ),\r\n        lineInfo( _lineInfo ),\r\n        type( _type ),\r\n        sequence( ++globalCount )\r\n    {}\r\n\r\n    bool MessageInfo::operator==( MessageInfo const& other ) const {\r\n        return sequence == other.sequence;\r\n    }\r\n\r\n    bool MessageInfo::operator<( MessageInfo const& other ) const {\r\n        return sequence < other.sequence;\r\n    }\r\n\r\n    // This may need protecting if threading support is added\r\n    unsigned int MessageInfo::globalCount = 0;\r\n\r\n    ////////////////////////////////////////////////////////////////////////////\r\n\r\n    Catch::MessageBuilder::MessageBuilder( StringRef const& macroName,\r\n                                           SourceLineInfo const& lineInfo,\r\n                                           ResultWas::OfType type )\r\n        :m_info(macroName, lineInfo, type) {}\r\n\r\n    ////////////////////////////////////////////////////////////////////////////\r\n\r\n    ScopedMessage::ScopedMessage( MessageBuilder const& builder )\r\n    : m_info( builder.m_info ), m_moved()\r\n    {\r\n        m_info.message = builder.m_stream.str();\r\n        getResultCapture().pushScopedMessage( m_info );\r\n    }\r\n\r\n    ScopedMessage::ScopedMessage( ScopedMessage&& old )\r\n    : m_info( old.m_info ), m_moved()\r\n    {\r\n        old.m_moved = true;\r\n    }\r\n\r\n    ScopedMessage::~ScopedMessage() {\r\n        if ( !uncaught_exceptions() && !m_moved ){\r\n            getResultCapture().popScopedMessage(m_info);\r\n        }\r\n    }\r\n\r\n    Capturer::Capturer( StringRef macroName, SourceLineInfo const& lineInfo, ResultWas::OfType resultType, StringRef names ) {\r\n        auto trimmed = [&] (size_t start, size_t end) {\r\n            while (names[start] == ',' || isspace(names[start])) {\r\n                ++start;\r\n            }\r\n            while (names[end] == ',' || isspace(names[end])) {\r\n                --end;\r\n            }\r\n            return names.substr(start, end - start + 1);\r\n        };\r\n\r\n        size_t start = 0;\r\n        std::stack<char> openings;\r\n        for (size_t pos = 0; pos < names.size(); ++pos) {\r\n            char c = names[pos];\r\n            switch (c) {\r\n            case '[':\r\n            case '{':\r\n            case '(':\r\n            // It is basically impossible to disambiguate between\r\n            // comparison and start of template args in this context\r\n//            case '<':\r\n                openings.push(c);\r\n                break;\r\n            case ']':\r\n            case '}':\r\n            case ')':\r\n//           case '>':\r\n                openings.pop();\r\n                break;\r\n            case ',':\r\n                if (start != pos && openings.size() == 0) {\r\n                    m_messages.emplace_back(macroName, lineInfo, resultType);\r\n                    m_messages.back().message = trimmed(start, pos);\r\n                    m_messages.back().message += \" := \";\r\n                    start = pos;\r\n                }\r\n            }\r\n        }\r\n        assert(openings.size() == 0 && \"Mismatched openings\");\r\n        m_messages.emplace_back(macroName, lineInfo, resultType);\r\n        m_messages.back().message = trimmed(start, names.size() - 1);\r\n        m_messages.back().message += \" := \";\r\n    }\r\n    Capturer::~Capturer() {\r\n        if ( !uncaught_exceptions() ){\r\n            assert( m_captured == m_messages.size() );\r\n            for( size_t i = 0; i < m_captured; ++i  )\r\n                m_resultCapture.popScopedMessage( m_messages[i] );\r\n        }\r\n    }\r\n\r\n    void Capturer::captureValue( size_t index, std::string const& value ) {\r\n        assert( index < m_messages.size() );\r\n        m_messages[index].message += value;\r\n        m_resultCapture.pushScopedMessage( m_messages[index] );\r\n        m_captured++;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_message.cpp\r\n// start catch_output_redirect.cpp\r\n\r\n// start catch_output_redirect.h\r\n#ifndef TWOBLUECUBES_CATCH_OUTPUT_REDIRECT_H\r\n#define TWOBLUECUBES_CATCH_OUTPUT_REDIRECT_H\r\n\r\n#include <cstdio>\r\n#include <iosfwd>\r\n#include <string>\r\n\r\nnamespace Catch {\r\n\r\n    class RedirectedStream {\r\n        std::ostream& m_originalStream;\r\n        std::ostream& m_redirectionStream;\r\n        std::streambuf* m_prevBuf;\r\n\r\n    public:\r\n        RedirectedStream( std::ostream& originalStream, std::ostream& redirectionStream );\r\n        ~RedirectedStream();\r\n    };\r\n\r\n    class RedirectedStdOut {\r\n        ReusableStringStream m_rss;\r\n        RedirectedStream m_cout;\r\n    public:\r\n        RedirectedStdOut();\r\n        auto str() const -> std::string;\r\n    };\r\n\r\n    // StdErr has two constituent streams in C++, std::cerr and std::clog\r\n    // This means that we need to redirect 2 streams into 1 to keep proper\r\n    // order of writes\r\n    class RedirectedStdErr {\r\n        ReusableStringStream m_rss;\r\n        RedirectedStream m_cerr;\r\n        RedirectedStream m_clog;\r\n    public:\r\n        RedirectedStdErr();\r\n        auto str() const -> std::string;\r\n    };\r\n\r\n    class RedirectedStreams {\r\n    public:\r\n        RedirectedStreams(RedirectedStreams const&) = delete;\r\n        RedirectedStreams& operator=(RedirectedStreams const&) = delete;\r\n        RedirectedStreams(RedirectedStreams&&) = delete;\r\n        RedirectedStreams& operator=(RedirectedStreams&&) = delete;\r\n\r\n        RedirectedStreams(std::string& redirectedCout, std::string& redirectedCerr);\r\n        ~RedirectedStreams();\r\n    private:\r\n        std::string& m_redirectedCout;\r\n        std::string& m_redirectedCerr;\r\n        RedirectedStdOut m_redirectedStdOut;\r\n        RedirectedStdErr m_redirectedStdErr;\r\n    };\r\n\r\n#if defined(CATCH_CONFIG_NEW_CAPTURE)\r\n\r\n    // Windows's implementation of std::tmpfile is terrible (it tries\r\n    // to create a file inside system folder, thus requiring elevated\r\n    // privileges for the binary), so we have to use tmpnam(_s) and\r\n    // create the file ourselves there.\r\n    class TempFile {\r\n    public:\r\n        TempFile(TempFile const&) = delete;\r\n        TempFile& operator=(TempFile const&) = delete;\r\n        TempFile(TempFile&&) = delete;\r\n        TempFile& operator=(TempFile&&) = delete;\r\n\r\n        TempFile();\r\n        ~TempFile();\r\n\r\n        std::FILE* getFile();\r\n        std::string getContents();\r\n\r\n    private:\r\n        std::FILE* m_file = nullptr;\r\n    #if defined(_MSC_VER)\r\n        char m_buffer[L_tmpnam] = { 0 };\r\n    #endif\r\n    };\r\n\r\n    class OutputRedirect {\r\n    public:\r\n        OutputRedirect(OutputRedirect const&) = delete;\r\n        OutputRedirect& operator=(OutputRedirect const&) = delete;\r\n        OutputRedirect(OutputRedirect&&) = delete;\r\n        OutputRedirect& operator=(OutputRedirect&&) = delete;\r\n\r\n        OutputRedirect(std::string& stdout_dest, std::string& stderr_dest);\r\n        ~OutputRedirect();\r\n\r\n    private:\r\n        int m_originalStdout = -1;\r\n        int m_originalStderr = -1;\r\n        TempFile m_stdoutFile;\r\n        TempFile m_stderrFile;\r\n        std::string& m_stdoutDest;\r\n        std::string& m_stderrDest;\r\n    };\r\n\r\n#endif\r\n\r\n} // end namespace Catch\r\n\r\n#endif // TWOBLUECUBES_CATCH_OUTPUT_REDIRECT_H\r\n// end catch_output_redirect.h\r\n#include <cstdio>\r\n#include <cstring>\r\n#include <fstream>\r\n#include <sstream>\r\n#include <stdexcept>\r\n\r\n#if defined(CATCH_CONFIG_NEW_CAPTURE)\r\n    #if defined(_MSC_VER)\r\n    #include <io.h>      //_dup and _dup2\r\n    #define dup _dup\r\n    #define dup2 _dup2\r\n    #define fileno _fileno\r\n    #else\r\n    #include <unistd.h>  // dup and dup2\r\n    #endif\r\n#endif\r\n\r\nnamespace Catch {\r\n\r\n    RedirectedStream::RedirectedStream( std::ostream& originalStream, std::ostream& redirectionStream )\r\n    :   m_originalStream( originalStream ),\r\n        m_redirectionStream( redirectionStream ),\r\n        m_prevBuf( m_originalStream.rdbuf() )\r\n    {\r\n        m_originalStream.rdbuf( m_redirectionStream.rdbuf() );\r\n    }\r\n\r\n    RedirectedStream::~RedirectedStream() {\r\n        m_originalStream.rdbuf( m_prevBuf );\r\n    }\r\n\r\n    RedirectedStdOut::RedirectedStdOut() : m_cout( Catch::cout(), m_rss.get() ) {}\r\n    auto RedirectedStdOut::str() const -> std::string { return m_rss.str(); }\r\n\r\n    RedirectedStdErr::RedirectedStdErr()\r\n    :   m_cerr( Catch::cerr(), m_rss.get() ),\r\n        m_clog( Catch::clog(), m_rss.get() )\r\n    {}\r\n    auto RedirectedStdErr::str() const -> std::string { return m_rss.str(); }\r\n\r\n    RedirectedStreams::RedirectedStreams(std::string& redirectedCout, std::string& redirectedCerr)\r\n    :   m_redirectedCout(redirectedCout),\r\n        m_redirectedCerr(redirectedCerr)\r\n    {}\r\n\r\n    RedirectedStreams::~RedirectedStreams() {\r\n        m_redirectedCout += m_redirectedStdOut.str();\r\n        m_redirectedCerr += m_redirectedStdErr.str();\r\n    }\r\n\r\n#if defined(CATCH_CONFIG_NEW_CAPTURE)\r\n\r\n#if defined(_MSC_VER)\r\n    TempFile::TempFile() {\r\n        if (tmpnam_s(m_buffer)) {\r\n            CATCH_RUNTIME_ERROR(\"Could not get a temp filename\");\r\n        }\r\n        if (fopen_s(&m_file, m_buffer, \"w\")) {\r\n            char buffer[100];\r\n            if (strerror_s(buffer, errno)) {\r\n                CATCH_RUNTIME_ERROR(\"Could not translate errno to a string\");\r\n            }\r\n            CATCH_RUNTIME_ERROR(\"Coul dnot open the temp file: '\" << m_buffer << \"' because: \" << buffer);\r\n        }\r\n    }\r\n#else\r\n    TempFile::TempFile() {\r\n        m_file = std::tmpfile();\r\n        if (!m_file) {\r\n            CATCH_RUNTIME_ERROR(\"Could not create a temp file.\");\r\n        }\r\n    }\r\n\r\n#endif\r\n\r\n    TempFile::~TempFile() {\r\n         // TBD: What to do about errors here?\r\n         std::fclose(m_file);\r\n         // We manually create the file on Windows only, on Linux\r\n         // it will be autodeleted\r\n#if defined(_MSC_VER)\r\n         std::remove(m_buffer);\r\n#endif\r\n    }\r\n\r\n    FILE* TempFile::getFile() {\r\n        return m_file;\r\n    }\r\n\r\n    std::string TempFile::getContents() {\r\n        std::stringstream sstr;\r\n        char buffer[100] = {};\r\n        std::rewind(m_file);\r\n        while (std::fgets(buffer, sizeof(buffer), m_file)) {\r\n            sstr << buffer;\r\n        }\r\n        return sstr.str();\r\n    }\r\n\r\n    OutputRedirect::OutputRedirect(std::string& stdout_dest, std::string& stderr_dest) :\r\n        m_originalStdout(dup(1)),\r\n        m_originalStderr(dup(2)),\r\n        m_stdoutDest(stdout_dest),\r\n        m_stderrDest(stderr_dest) {\r\n        dup2(fileno(m_stdoutFile.getFile()), 1);\r\n        dup2(fileno(m_stderrFile.getFile()), 2);\r\n    }\r\n\r\n    OutputRedirect::~OutputRedirect() {\r\n        Catch::cout() << std::flush;\r\n        fflush(stdout);\r\n        // Since we support overriding these streams, we flush cerr\r\n        // even though std::cerr is unbuffered\r\n        Catch::cerr() << std::flush;\r\n        Catch::clog() << std::flush;\r\n        fflush(stderr);\r\n\r\n        dup2(m_originalStdout, 1);\r\n        dup2(m_originalStderr, 2);\r\n\r\n        m_stdoutDest += m_stdoutFile.getContents();\r\n        m_stderrDest += m_stderrFile.getContents();\r\n    }\r\n\r\n#endif // CATCH_CONFIG_NEW_CAPTURE\r\n\r\n} // namespace Catch\r\n\r\n#if defined(CATCH_CONFIG_NEW_CAPTURE)\r\n    #if defined(_MSC_VER)\r\n    #undef dup\r\n    #undef dup2\r\n    #undef fileno\r\n    #endif\r\n#endif\r\n// end catch_output_redirect.cpp\r\n// start catch_polyfills.cpp\r\n\r\n#include <cmath>\r\n\r\nnamespace Catch {\r\n\r\n#if !defined(CATCH_CONFIG_POLYFILL_ISNAN)\r\n    bool isnan(float f) {\r\n        return std::isnan(f);\r\n    }\r\n    bool isnan(double d) {\r\n        return std::isnan(d);\r\n    }\r\n#else\r\n    // For now we only use this for embarcadero\r\n    bool isnan(float f) {\r\n        return std::_isnan(f);\r\n    }\r\n    bool isnan(double d) {\r\n        return std::_isnan(d);\r\n    }\r\n#endif\r\n\r\n} // end namespace Catch\r\n// end catch_polyfills.cpp\r\n// start catch_random_number_generator.cpp\r\n\r\nnamespace Catch {\r\n\r\n    std::mt19937& rng() {\r\n        static std::mt19937 s_rng;\r\n        return s_rng;\r\n    }\r\n\r\n    void seedRng( IConfig const& config ) {\r\n        if( config.rngSeed() != 0 ) {\r\n            std::srand( config.rngSeed() );\r\n            rng().seed( config.rngSeed() );\r\n        }\r\n    }\r\n\r\n    unsigned int rngSeed() {\r\n        return getCurrentContext().getConfig()->rngSeed();\r\n    }\r\n}\r\n// end catch_random_number_generator.cpp\r\n// start catch_registry_hub.cpp\r\n\r\n// start catch_test_case_registry_impl.h\r\n\r\n#include <vector>\r\n#include <set>\r\n#include <algorithm>\r\n#include <ios>\r\n\r\nnamespace Catch {\r\n\r\n    class TestCase;\r\n    struct IConfig;\r\n\r\n    std::vector<TestCase> sortTests( IConfig const& config, std::vector<TestCase> const& unsortedTestCases );\r\n    bool matchTest( TestCase const& testCase, TestSpec const& testSpec, IConfig const& config );\r\n\r\n    void enforceNoDuplicateTestCases( std::vector<TestCase> const& functions );\r\n\r\n    std::vector<TestCase> filterTests( std::vector<TestCase> const& testCases, TestSpec const& testSpec, IConfig const& config );\r\n    std::vector<TestCase> const& getAllTestCasesSorted( IConfig const& config );\r\n\r\n    class TestRegistry : public ITestCaseRegistry {\r\n    public:\r\n        virtual ~TestRegistry() = default;\r\n\r\n        virtual void registerTest( TestCase const& testCase );\r\n\r\n        std::vector<TestCase> const& getAllTests() const override;\r\n        std::vector<TestCase> const& getAllTestsSorted( IConfig const& config ) const override;\r\n\r\n    private:\r\n        std::vector<TestCase> m_functions;\r\n        mutable RunTests::InWhatOrder m_currentSortOrder = RunTests::InDeclarationOrder;\r\n        mutable std::vector<TestCase> m_sortedFunctions;\r\n        std::size_t m_unnamedCount = 0;\r\n        std::ios_base::Init m_ostreamInit; // Forces cout/ cerr to be initialised\r\n    };\r\n\r\n    ///////////////////////////////////////////////////////////////////////////\r\n\r\n    class TestInvokerAsFunction : public ITestInvoker {\r\n        void(*m_testAsFunction)();\r\n    public:\r\n        TestInvokerAsFunction( void(*testAsFunction)() ) noexcept;\r\n\r\n        void invoke() const override;\r\n    };\r\n\r\n    std::string extractClassName( StringRef const& classOrQualifiedMethodName );\r\n\r\n    ///////////////////////////////////////////////////////////////////////////\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_test_case_registry_impl.h\r\n// start catch_reporter_registry.h\r\n\r\n#include <map>\r\n\r\nnamespace Catch {\r\n\r\n    class ReporterRegistry : public IReporterRegistry {\r\n\r\n    public:\r\n\r\n        ~ReporterRegistry() override;\r\n\r\n        IStreamingReporterPtr create( std::string const& name, IConfigPtr const& config ) const override;\r\n\r\n        void registerReporter( std::string const& name, IReporterFactoryPtr const& factory );\r\n        void registerListener( IReporterFactoryPtr const& factory );\r\n\r\n        FactoryMap const& getFactories() const override;\r\n        Listeners const& getListeners() const override;\r\n\r\n    private:\r\n        FactoryMap m_factories;\r\n        Listeners m_listeners;\r\n    };\r\n}\r\n\r\n// end catch_reporter_registry.h\r\n// start catch_tag_alias_registry.h\r\n\r\n// start catch_tag_alias.h\r\n\r\n#include <string>\r\n\r\nnamespace Catch {\r\n\r\n    struct TagAlias {\r\n        TagAlias(std::string const& _tag, SourceLineInfo _lineInfo);\r\n\r\n        std::string tag;\r\n        SourceLineInfo lineInfo;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_tag_alias.h\r\n#include <map>\r\n\r\nnamespace Catch {\r\n\r\n    class TagAliasRegistry : public ITagAliasRegistry {\r\n    public:\r\n        ~TagAliasRegistry() override;\r\n        TagAlias const* find( std::string const& alias ) const override;\r\n        std::string expandAliases( std::string const& unexpandedTestSpec ) const override;\r\n        void add( std::string const& alias, std::string const& tag, SourceLineInfo const& lineInfo );\r\n\r\n    private:\r\n        std::map<std::string, TagAlias> m_registry;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_tag_alias_registry.h\r\n// start catch_startup_exception_registry.h\r\n\r\n#include <vector>\r\n#include <exception>\r\n\r\nnamespace Catch {\r\n\r\n    class StartupExceptionRegistry {\r\n    public:\r\n        void add(std::exception_ptr const& exception) noexcept;\r\n        std::vector<std::exception_ptr> const& getExceptions() const noexcept;\r\n    private:\r\n        std::vector<std::exception_ptr> m_exceptions;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_startup_exception_registry.h\r\n// start catch_singletons.hpp\r\n\r\nnamespace Catch {\r\n\r\n    struct ISingleton {\r\n        virtual ~ISingleton();\r\n    };\r\n\r\n    void addSingleton( ISingleton* singleton );\r\n    void cleanupSingletons();\r\n\r\n    template<typename SingletonImplT, typename InterfaceT = SingletonImplT, typename MutableInterfaceT = InterfaceT>\r\n    class Singleton : SingletonImplT, public ISingleton {\r\n\r\n        static auto getInternal() -> Singleton* {\r\n            static Singleton* s_instance = nullptr;\r\n            if( !s_instance ) {\r\n                s_instance = new Singleton;\r\n                addSingleton( s_instance );\r\n            }\r\n            return s_instance;\r\n        }\r\n\r\n    public:\r\n        static auto get() -> InterfaceT const& {\r\n            return *getInternal();\r\n        }\r\n        static auto getMutable() -> MutableInterfaceT& {\r\n            return *getInternal();\r\n        }\r\n    };\r\n\r\n} // namespace Catch\r\n\r\n// end catch_singletons.hpp\r\nnamespace Catch {\r\n\r\n    namespace {\r\n\r\n        class RegistryHub : public IRegistryHub, public IMutableRegistryHub,\r\n                            private NonCopyable {\r\n\r\n        public: // IRegistryHub\r\n            RegistryHub() = default;\r\n            IReporterRegistry const& getReporterRegistry() const override {\r\n                return m_reporterRegistry;\r\n            }\r\n            ITestCaseRegistry const& getTestCaseRegistry() const override {\r\n                return m_testCaseRegistry;\r\n            }\r\n            IExceptionTranslatorRegistry const& getExceptionTranslatorRegistry() const override {\r\n                return m_exceptionTranslatorRegistry;\r\n            }\r\n            ITagAliasRegistry const& getTagAliasRegistry() const override {\r\n                return m_tagAliasRegistry;\r\n            }\r\n            StartupExceptionRegistry const& getStartupExceptionRegistry() const override {\r\n                return m_exceptionRegistry;\r\n            }\r\n\r\n        public: // IMutableRegistryHub\r\n            void registerReporter( std::string const& name, IReporterFactoryPtr const& factory ) override {\r\n                m_reporterRegistry.registerReporter( name, factory );\r\n            }\r\n            void registerListener( IReporterFactoryPtr const& factory ) override {\r\n                m_reporterRegistry.registerListener( factory );\r\n            }\r\n            void registerTest( TestCase const& testInfo ) override {\r\n                m_testCaseRegistry.registerTest( testInfo );\r\n            }\r\n            void registerTranslator( const IExceptionTranslator* translator ) override {\r\n                m_exceptionTranslatorRegistry.registerTranslator( translator );\r\n            }\r\n            void registerTagAlias( std::string const& alias, std::string const& tag, SourceLineInfo const& lineInfo ) override {\r\n                m_tagAliasRegistry.add( alias, tag, lineInfo );\r\n            }\r\n            void registerStartupException() noexcept override {\r\n                m_exceptionRegistry.add(std::current_exception());\r\n            }\r\n\r\n        private:\r\n            TestRegistry m_testCaseRegistry;\r\n            ReporterRegistry m_reporterRegistry;\r\n            ExceptionTranslatorRegistry m_exceptionTranslatorRegistry;\r\n            TagAliasRegistry m_tagAliasRegistry;\r\n            StartupExceptionRegistry m_exceptionRegistry;\r\n        };\r\n    }\r\n\r\n    using RegistryHubSingleton = Singleton<RegistryHub, IRegistryHub, IMutableRegistryHub>;\r\n\r\n    IRegistryHub const& getRegistryHub() {\r\n        return RegistryHubSingleton::get();\r\n    }\r\n    IMutableRegistryHub& getMutableRegistryHub() {\r\n        return RegistryHubSingleton::getMutable();\r\n    }\r\n    void cleanUp() {\r\n        cleanupSingletons();\r\n        cleanUpContext();\r\n    }\r\n    std::string translateActiveException() {\r\n        return getRegistryHub().getExceptionTranslatorRegistry().translateActiveException();\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_registry_hub.cpp\r\n// start catch_reporter_registry.cpp\r\n\r\nnamespace Catch {\r\n\r\n    ReporterRegistry::~ReporterRegistry() = default;\r\n\r\n    IStreamingReporterPtr ReporterRegistry::create( std::string const& name, IConfigPtr const& config ) const {\r\n        auto it =  m_factories.find( name );\r\n        if( it == m_factories.end() )\r\n            return nullptr;\r\n        return it->second->create( ReporterConfig( config ) );\r\n    }\r\n\r\n    void ReporterRegistry::registerReporter( std::string const& name, IReporterFactoryPtr const& factory ) {\r\n        m_factories.emplace(name, factory);\r\n    }\r\n    void ReporterRegistry::registerListener( IReporterFactoryPtr const& factory ) {\r\n        m_listeners.push_back( factory );\r\n    }\r\n\r\n    IReporterRegistry::FactoryMap const& ReporterRegistry::getFactories() const {\r\n        return m_factories;\r\n    }\r\n    IReporterRegistry::Listeners const& ReporterRegistry::getListeners() const {\r\n        return m_listeners;\r\n    }\r\n\r\n}\r\n// end catch_reporter_registry.cpp\r\n// start catch_result_type.cpp\r\n\r\nnamespace Catch {\r\n\r\n    bool isOk( ResultWas::OfType resultType ) {\r\n        return ( resultType & ResultWas::FailureBit ) == 0;\r\n    }\r\n    bool isJustInfo( int flags ) {\r\n        return flags == ResultWas::Info;\r\n    }\r\n\r\n    ResultDisposition::Flags operator | ( ResultDisposition::Flags lhs, ResultDisposition::Flags rhs ) {\r\n        return static_cast<ResultDisposition::Flags>( static_cast<int>( lhs ) | static_cast<int>( rhs ) );\r\n    }\r\n\r\n    bool shouldContinueOnFailure( int flags )    { return ( flags & ResultDisposition::ContinueOnFailure ) != 0; }\r\n    bool shouldSuppressFailure( int flags )      { return ( flags & ResultDisposition::SuppressFail ) != 0; }\r\n\r\n} // end namespace Catch\r\n// end catch_result_type.cpp\r\n// start catch_run_context.cpp\r\n\r\n#include <cassert>\r\n#include <algorithm>\r\n#include <sstream>\r\n\r\nnamespace Catch {\r\n\r\n    namespace Generators {\r\n        struct GeneratorTracker : TestCaseTracking::TrackerBase, IGeneratorTracker {\r\n            GeneratorBasePtr m_generator;\r\n\r\n            GeneratorTracker( TestCaseTracking::NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent )\r\n            :   TrackerBase( nameAndLocation, ctx, parent )\r\n            {}\r\n            ~GeneratorTracker();\r\n\r\n            static GeneratorTracker& acquire( TrackerContext& ctx, TestCaseTracking::NameAndLocation const& nameAndLocation ) {\r\n                std::shared_ptr<GeneratorTracker> tracker;\r\n\r\n                ITracker& currentTracker = ctx.currentTracker();\r\n                if( TestCaseTracking::ITrackerPtr childTracker = currentTracker.findChild( nameAndLocation ) ) {\r\n                    assert( childTracker );\r\n                    assert( childTracker->isGeneratorTracker() );\r\n                    tracker = std::static_pointer_cast<GeneratorTracker>( childTracker );\r\n                }\r\n                else {\r\n                    tracker = std::make_shared<GeneratorTracker>( nameAndLocation, ctx, &currentTracker );\r\n                    currentTracker.addChild( tracker );\r\n                }\r\n\r\n                if( !ctx.completedCycle() && !tracker->isComplete() ) {\r\n                    tracker->open();\r\n                }\r\n\r\n                return *tracker;\r\n            }\r\n\r\n            // TrackerBase interface\r\n            bool isGeneratorTracker() const override { return true; }\r\n            auto hasGenerator() const -> bool override {\r\n                return !!m_generator;\r\n            }\r\n            void close() override {\r\n                TrackerBase::close();\r\n                // Generator interface only finds out if it has another item on atual move\r\n                if (m_runState == CompletedSuccessfully && m_generator->next()) {\r\n                    m_children.clear();\r\n                    m_runState = Executing;\r\n                }\r\n            }\r\n\r\n            // IGeneratorTracker interface\r\n            auto getGenerator() const -> GeneratorBasePtr const& override {\r\n                return m_generator;\r\n            }\r\n            void setGenerator( GeneratorBasePtr&& generator ) override {\r\n                m_generator = std::move( generator );\r\n            }\r\n        };\r\n        GeneratorTracker::~GeneratorTracker() {}\r\n    }\r\n\r\n    RunContext::RunContext(IConfigPtr const& _config, IStreamingReporterPtr&& reporter)\r\n    :   m_runInfo(_config->name()),\r\n        m_context(getCurrentMutableContext()),\r\n        m_config(_config),\r\n        m_reporter(std::move(reporter)),\r\n        m_lastAssertionInfo{ StringRef(), SourceLineInfo(\"\",0), StringRef(), ResultDisposition::Normal },\r\n        m_includeSuccessfulResults( m_config->includeSuccessfulResults() || m_reporter->getPreferences().shouldReportAllAssertions )\r\n    {\r\n        m_context.setRunner(this);\r\n        m_context.setConfig(m_config);\r\n        m_context.setResultCapture(this);\r\n        m_reporter->testRunStarting(m_runInfo);\r\n    }\r\n\r\n    RunContext::~RunContext() {\r\n        m_reporter->testRunEnded(TestRunStats(m_runInfo, m_totals, aborting()));\r\n    }\r\n\r\n    void RunContext::testGroupStarting(std::string const& testSpec, std::size_t groupIndex, std::size_t groupsCount) {\r\n        m_reporter->testGroupStarting(GroupInfo(testSpec, groupIndex, groupsCount));\r\n    }\r\n\r\n    void RunContext::testGroupEnded(std::string const& testSpec, Totals const& totals, std::size_t groupIndex, std::size_t groupsCount) {\r\n        m_reporter->testGroupEnded(TestGroupStats(GroupInfo(testSpec, groupIndex, groupsCount), totals, aborting()));\r\n    }\r\n\r\n    Totals RunContext::runTest(TestCase const& testCase) {\r\n        Totals prevTotals = m_totals;\r\n\r\n        std::string redirectedCout;\r\n        std::string redirectedCerr;\r\n\r\n        auto const& testInfo = testCase.getTestCaseInfo();\r\n\r\n        m_reporter->testCaseStarting(testInfo);\r\n\r\n        m_activeTestCase = &testCase;\r\n\r\n        ITracker& rootTracker = m_trackerContext.startRun();\r\n        assert(rootTracker.isSectionTracker());\r\n        static_cast<SectionTracker&>(rootTracker).addInitialFilters(m_config->getSectionsToRun());\r\n        do {\r\n            m_trackerContext.startCycle();\r\n            m_testCaseTracker = &SectionTracker::acquire(m_trackerContext, TestCaseTracking::NameAndLocation(testInfo.name, testInfo.lineInfo));\r\n            runCurrentTest(redirectedCout, redirectedCerr);\r\n        } while (!m_testCaseTracker->isSuccessfullyCompleted() && !aborting());\r\n\r\n        Totals deltaTotals = m_totals.delta(prevTotals);\r\n        if (testInfo.expectedToFail() && deltaTotals.testCases.passed > 0) {\r\n            deltaTotals.assertions.failed++;\r\n            deltaTotals.testCases.passed--;\r\n            deltaTotals.testCases.failed++;\r\n        }\r\n        m_totals.testCases += deltaTotals.testCases;\r\n        m_reporter->testCaseEnded(TestCaseStats(testInfo,\r\n                                  deltaTotals,\r\n                                  redirectedCout,\r\n                                  redirectedCerr,\r\n                                  aborting()));\r\n\r\n        m_activeTestCase = nullptr;\r\n        m_testCaseTracker = nullptr;\r\n\r\n        return deltaTotals;\r\n    }\r\n\r\n    IConfigPtr RunContext::config() const {\r\n        return m_config;\r\n    }\r\n\r\n    IStreamingReporter& RunContext::reporter() const {\r\n        return *m_reporter;\r\n    }\r\n\r\n    void RunContext::assertionEnded(AssertionResult const & result) {\r\n        if (result.getResultType() == ResultWas::Ok) {\r\n            m_totals.assertions.passed++;\r\n            m_lastAssertionPassed = true;\r\n        } else if (!result.isOk()) {\r\n            m_lastAssertionPassed = false;\r\n            if( m_activeTestCase->getTestCaseInfo().okToFail() )\r\n                m_totals.assertions.failedButOk++;\r\n            else\r\n                m_totals.assertions.failed++;\r\n        }\r\n        else {\r\n            m_lastAssertionPassed = true;\r\n        }\r\n\r\n        // We have no use for the return value (whether messages should be cleared), because messages were made scoped\r\n        // and should be let to clear themselves out.\r\n        static_cast<void>(m_reporter->assertionEnded(AssertionStats(result, m_messages, m_totals)));\r\n\r\n        if (result.getResultType() != ResultWas::Warning)\r\n            m_messageScopes.clear();\r\n\r\n        // Reset working state\r\n        resetAssertionInfo();\r\n        m_lastResult = result;\r\n    }\r\n    void RunContext::resetAssertionInfo() {\r\n        m_lastAssertionInfo.macroName = StringRef();\r\n        m_lastAssertionInfo.capturedExpression = \"{Unknown expression after the reported line}\"_sr;\r\n    }\r\n\r\n    bool RunContext::sectionStarted(SectionInfo const & sectionInfo, Counts & assertions) {\r\n        ITracker& sectionTracker = SectionTracker::acquire(m_trackerContext, TestCaseTracking::NameAndLocation(sectionInfo.name, sectionInfo.lineInfo));\r\n        if (!sectionTracker.isOpen())\r\n            return false;\r\n        m_activeSections.push_back(&sectionTracker);\r\n\r\n        m_lastAssertionInfo.lineInfo = sectionInfo.lineInfo;\r\n\r\n        m_reporter->sectionStarting(sectionInfo);\r\n\r\n        assertions = m_totals.assertions;\r\n\r\n        return true;\r\n    }\r\n    auto RunContext::acquireGeneratorTracker( SourceLineInfo const& lineInfo ) -> IGeneratorTracker& {\r\n        using namespace Generators;\r\n        GeneratorTracker& tracker = GeneratorTracker::acquire( m_trackerContext, TestCaseTracking::NameAndLocation( \"generator\", lineInfo ) );\r\n        assert( tracker.isOpen() );\r\n        m_lastAssertionInfo.lineInfo = lineInfo;\r\n        return tracker;\r\n    }\r\n\r\n    bool RunContext::testForMissingAssertions(Counts& assertions) {\r\n        if (assertions.total() != 0)\r\n            return false;\r\n        if (!m_config->warnAboutMissingAssertions())\r\n            return false;\r\n        if (m_trackerContext.currentTracker().hasChildren())\r\n            return false;\r\n        m_totals.assertions.failed++;\r\n        assertions.failed++;\r\n        return true;\r\n    }\r\n\r\n    void RunContext::sectionEnded(SectionEndInfo const & endInfo) {\r\n        Counts assertions = m_totals.assertions - endInfo.prevAssertions;\r\n        bool missingAssertions = testForMissingAssertions(assertions);\r\n\r\n        if (!m_activeSections.empty()) {\r\n            m_activeSections.back()->close();\r\n            m_activeSections.pop_back();\r\n        }\r\n\r\n        m_reporter->sectionEnded(SectionStats(endInfo.sectionInfo, assertions, endInfo.durationInSeconds, missingAssertions));\r\n        m_messages.clear();\r\n        m_messageScopes.clear();\r\n    }\r\n\r\n    void RunContext::sectionEndedEarly(SectionEndInfo const & endInfo) {\r\n        if (m_unfinishedSections.empty())\r\n            m_activeSections.back()->fail();\r\n        else\r\n            m_activeSections.back()->close();\r\n        m_activeSections.pop_back();\r\n\r\n        m_unfinishedSections.push_back(endInfo);\r\n    }\r\n    void RunContext::benchmarkStarting( BenchmarkInfo const& info ) {\r\n        m_reporter->benchmarkStarting( info );\r\n    }\r\n    void RunContext::benchmarkEnded( BenchmarkStats const& stats ) {\r\n        m_reporter->benchmarkEnded( stats );\r\n    }\r\n\r\n    void RunContext::pushScopedMessage(MessageInfo const & message) {\r\n        m_messages.push_back(message);\r\n    }\r\n\r\n    void RunContext::popScopedMessage(MessageInfo const & message) {\r\n        m_messages.erase(std::remove(m_messages.begin(), m_messages.end(), message), m_messages.end());\r\n    }\r\n\r\n    void RunContext::emplaceUnscopedMessage( MessageBuilder const& builder ) {\r\n        m_messageScopes.emplace_back( builder );\r\n    }\r\n\r\n    std::string RunContext::getCurrentTestName() const {\r\n        return m_activeTestCase\r\n            ? m_activeTestCase->getTestCaseInfo().name\r\n            : std::string();\r\n    }\r\n\r\n    const AssertionResult * RunContext::getLastResult() const {\r\n        return &(*m_lastResult);\r\n    }\r\n\r\n    void RunContext::exceptionEarlyReported() {\r\n        m_shouldReportUnexpected = false;\r\n    }\r\n\r\n    void RunContext::handleFatalErrorCondition( StringRef message ) {\r\n        // First notify reporter that bad things happened\r\n        m_reporter->fatalErrorEncountered(message);\r\n\r\n        // Don't rebuild the result -- the stringification itself can cause more fatal errors\r\n        // Instead, fake a result data.\r\n        AssertionResultData tempResult( ResultWas::FatalErrorCondition, { false } );\r\n        tempResult.message = message;\r\n        AssertionResult result(m_lastAssertionInfo, tempResult);\r\n\r\n        assertionEnded(result);\r\n\r\n        handleUnfinishedSections();\r\n\r\n        // Recreate section for test case (as we will lose the one that was in scope)\r\n        auto const& testCaseInfo = m_activeTestCase->getTestCaseInfo();\r\n        SectionInfo testCaseSection(testCaseInfo.lineInfo, testCaseInfo.name);\r\n\r\n        Counts assertions;\r\n        assertions.failed = 1;\r\n        SectionStats testCaseSectionStats(testCaseSection, assertions, 0, false);\r\n        m_reporter->sectionEnded(testCaseSectionStats);\r\n\r\n        auto const& testInfo = m_activeTestCase->getTestCaseInfo();\r\n\r\n        Totals deltaTotals;\r\n        deltaTotals.testCases.failed = 1;\r\n        deltaTotals.assertions.failed = 1;\r\n        m_reporter->testCaseEnded(TestCaseStats(testInfo,\r\n                                  deltaTotals,\r\n                                  std::string(),\r\n                                  std::string(),\r\n                                  false));\r\n        m_totals.testCases.failed++;\r\n        testGroupEnded(std::string(), m_totals, 1, 1);\r\n        m_reporter->testRunEnded(TestRunStats(m_runInfo, m_totals, false));\r\n    }\r\n\r\n    bool RunContext::lastAssertionPassed() {\r\n         return m_lastAssertionPassed;\r\n    }\r\n\r\n    void RunContext::assertionPassed() {\r\n        m_lastAssertionPassed = true;\r\n        ++m_totals.assertions.passed;\r\n        resetAssertionInfo();\r\n        m_messageScopes.clear();\r\n    }\r\n\r\n    bool RunContext::aborting() const {\r\n        return m_totals.assertions.failed >= static_cast<std::size_t>(m_config->abortAfter());\r\n    }\r\n\r\n    void RunContext::runCurrentTest(std::string & redirectedCout, std::string & redirectedCerr) {\r\n        auto const& testCaseInfo = m_activeTestCase->getTestCaseInfo();\r\n        SectionInfo testCaseSection(testCaseInfo.lineInfo, testCaseInfo.name);\r\n        m_reporter->sectionStarting(testCaseSection);\r\n        Counts prevAssertions = m_totals.assertions;\r\n        double duration = 0;\r\n        m_shouldReportUnexpected = true;\r\n        m_lastAssertionInfo = { \"TEST_CASE\"_sr, testCaseInfo.lineInfo, StringRef(), ResultDisposition::Normal };\r\n\r\n        seedRng(*m_config);\r\n\r\n        Timer timer;\r\n        CATCH_TRY {\r\n            if (m_reporter->getPreferences().shouldRedirectStdOut) {\r\n#if !defined(CATCH_CONFIG_EXPERIMENTAL_REDIRECT)\r\n                RedirectedStreams redirectedStreams(redirectedCout, redirectedCerr);\r\n\r\n                timer.start();\r\n                invokeActiveTestCase();\r\n#else\r\n                OutputRedirect r(redirectedCout, redirectedCerr);\r\n                timer.start();\r\n                invokeActiveTestCase();\r\n#endif\r\n            } else {\r\n                timer.start();\r\n                invokeActiveTestCase();\r\n            }\r\n            duration = timer.getElapsedSeconds();\r\n        } CATCH_CATCH_ANON (TestFailureException&) {\r\n            // This just means the test was aborted due to failure\r\n        } CATCH_CATCH_ALL {\r\n            // Under CATCH_CONFIG_FAST_COMPILE, unexpected exceptions under REQUIRE assertions\r\n            // are reported without translation at the point of origin.\r\n            if( m_shouldReportUnexpected ) {\r\n                AssertionReaction dummyReaction;\r\n                handleUnexpectedInflightException( m_lastAssertionInfo, translateActiveException(), dummyReaction );\r\n            }\r\n        }\r\n        Counts assertions = m_totals.assertions - prevAssertions;\r\n        bool missingAssertions = testForMissingAssertions(assertions);\r\n\r\n        m_testCaseTracker->close();\r\n        handleUnfinishedSections();\r\n        m_messages.clear();\r\n        m_messageScopes.clear();\r\n\r\n        SectionStats testCaseSectionStats(testCaseSection, assertions, duration, missingAssertions);\r\n        m_reporter->sectionEnded(testCaseSectionStats);\r\n    }\r\n\r\n    void RunContext::invokeActiveTestCase() {\r\n        FatalConditionHandler fatalConditionHandler; // Handle signals\r\n        m_activeTestCase->invoke();\r\n        fatalConditionHandler.reset();\r\n    }\r\n\r\n    void RunContext::handleUnfinishedSections() {\r\n        // If sections ended prematurely due to an exception we stored their\r\n        // infos here so we can tear them down outside the unwind process.\r\n        for (auto it = m_unfinishedSections.rbegin(),\r\n             itEnd = m_unfinishedSections.rend();\r\n             it != itEnd;\r\n             ++it)\r\n            sectionEnded(*it);\r\n        m_unfinishedSections.clear();\r\n    }\r\n\r\n    void RunContext::handleExpr(\r\n        AssertionInfo const& info,\r\n        ITransientExpression const& expr,\r\n        AssertionReaction& reaction\r\n    ) {\r\n        m_reporter->assertionStarting( info );\r\n\r\n        bool negated = isFalseTest( info.resultDisposition );\r\n        bool result = expr.getResult() != negated;\r\n\r\n        if( result ) {\r\n            if (!m_includeSuccessfulResults) {\r\n                assertionPassed();\r\n            }\r\n            else {\r\n                reportExpr(info, ResultWas::Ok, &expr, negated);\r\n            }\r\n        }\r\n        else {\r\n            reportExpr(info, ResultWas::ExpressionFailed, &expr, negated );\r\n            populateReaction( reaction );\r\n        }\r\n    }\r\n    void RunContext::reportExpr(\r\n            AssertionInfo const &info,\r\n            ResultWas::OfType resultType,\r\n            ITransientExpression const *expr,\r\n            bool negated ) {\r\n\r\n        m_lastAssertionInfo = info;\r\n        AssertionResultData data( resultType, LazyExpression( negated ) );\r\n\r\n        AssertionResult assertionResult{ info, data };\r\n        assertionResult.m_resultData.lazyExpression.m_transientExpression = expr;\r\n\r\n        assertionEnded( assertionResult );\r\n    }\r\n\r\n    void RunContext::handleMessage(\r\n            AssertionInfo const& info,\r\n            ResultWas::OfType resultType,\r\n            StringRef const& message,\r\n            AssertionReaction& reaction\r\n    ) {\r\n        m_reporter->assertionStarting( info );\r\n\r\n        m_lastAssertionInfo = info;\r\n\r\n        AssertionResultData data( resultType, LazyExpression( false ) );\r\n        data.message = message;\r\n        AssertionResult assertionResult{ m_lastAssertionInfo, data };\r\n        assertionEnded( assertionResult );\r\n        if( !assertionResult.isOk() )\r\n            populateReaction( reaction );\r\n    }\r\n    void RunContext::handleUnexpectedExceptionNotThrown(\r\n            AssertionInfo const& info,\r\n            AssertionReaction& reaction\r\n    ) {\r\n        handleNonExpr(info, Catch::ResultWas::DidntThrowException, reaction);\r\n    }\r\n\r\n    void RunContext::handleUnexpectedInflightException(\r\n            AssertionInfo const& info,\r\n            std::string const& message,\r\n            AssertionReaction& reaction\r\n    ) {\r\n        m_lastAssertionInfo = info;\r\n\r\n        AssertionResultData data( ResultWas::ThrewException, LazyExpression( false ) );\r\n        data.message = message;\r\n        AssertionResult assertionResult{ info, data };\r\n        assertionEnded( assertionResult );\r\n        populateReaction( reaction );\r\n    }\r\n\r\n    void RunContext::populateReaction( AssertionReaction& reaction ) {\r\n        reaction.shouldDebugBreak = m_config->shouldDebugBreak();\r\n        reaction.shouldThrow = aborting() || (m_lastAssertionInfo.resultDisposition & ResultDisposition::Normal);\r\n    }\r\n\r\n    void RunContext::handleIncomplete(\r\n            AssertionInfo const& info\r\n    ) {\r\n        m_lastAssertionInfo = info;\r\n\r\n        AssertionResultData data( ResultWas::ThrewException, LazyExpression( false ) );\r\n        data.message = \"Exception translation was disabled by CATCH_CONFIG_FAST_COMPILE\";\r\n        AssertionResult assertionResult{ info, data };\r\n        assertionEnded( assertionResult );\r\n    }\r\n    void RunContext::handleNonExpr(\r\n            AssertionInfo const &info,\r\n            ResultWas::OfType resultType,\r\n            AssertionReaction &reaction\r\n    ) {\r\n        m_lastAssertionInfo = info;\r\n\r\n        AssertionResultData data( resultType, LazyExpression( false ) );\r\n        AssertionResult assertionResult{ info, data };\r\n        assertionEnded( assertionResult );\r\n\r\n        if( !assertionResult.isOk() )\r\n            populateReaction( reaction );\r\n    }\r\n\r\n    IResultCapture& getResultCapture() {\r\n        if (auto* capture = getCurrentContext().getResultCapture())\r\n            return *capture;\r\n        else\r\n            CATCH_INTERNAL_ERROR(\"No result capture instance\");\r\n    }\r\n}\r\n// end catch_run_context.cpp\r\n// start catch_section.cpp\r\n\r\nnamespace Catch {\r\n\r\n    Section::Section( SectionInfo const& info )\r\n    :   m_info( info ),\r\n        m_sectionIncluded( getResultCapture().sectionStarted( m_info, m_assertions ) )\r\n    {\r\n        m_timer.start();\r\n    }\r\n\r\n    Section::~Section() {\r\n        if( m_sectionIncluded ) {\r\n            SectionEndInfo endInfo{ m_info, m_assertions, m_timer.getElapsedSeconds() };\r\n            if( uncaught_exceptions() )\r\n                getResultCapture().sectionEndedEarly( endInfo );\r\n            else\r\n                getResultCapture().sectionEnded( endInfo );\r\n        }\r\n    }\r\n\r\n    // This indicates whether the section should be executed or not\r\n    Section::operator bool() const {\r\n        return m_sectionIncluded;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_section.cpp\r\n// start catch_section_info.cpp\r\n\r\nnamespace Catch {\r\n\r\n    SectionInfo::SectionInfo\r\n        (   SourceLineInfo const& _lineInfo,\r\n            std::string const& _name )\r\n    :   name( _name ),\r\n        lineInfo( _lineInfo )\r\n    {}\r\n\r\n} // end namespace Catch\r\n// end catch_section_info.cpp\r\n// start catch_session.cpp\r\n\r\n// start catch_session.h\r\n\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    class Session : NonCopyable {\r\n    public:\r\n\r\n        Session();\r\n        ~Session() override;\r\n\r\n        void showHelp() const;\r\n        void libIdentify();\r\n\r\n        int applyCommandLine( int argc, char const * const * argv );\r\n    #if defined(CATCH_CONFIG_WCHAR) && defined(WIN32) && defined(UNICODE)\r\n        int applyCommandLine( int argc, wchar_t const * const * argv );\r\n    #endif\r\n\r\n        void useConfigData( ConfigData const& configData );\r\n\r\n        template<typename CharT>\r\n        int run(int argc, CharT const * const argv[]) {\r\n            if (m_startupExceptions)\r\n                return 1;\r\n            int returnCode = applyCommandLine(argc, argv);\r\n            if (returnCode == 0)\r\n                returnCode = run();\r\n            return returnCode;\r\n        }\r\n\r\n        int run();\r\n\r\n        clara::Parser const& cli() const;\r\n        void cli( clara::Parser const& newParser );\r\n        ConfigData& configData();\r\n        Config& config();\r\n    private:\r\n        int runInternal();\r\n\r\n        clara::Parser m_cli;\r\n        ConfigData m_configData;\r\n        std::shared_ptr<Config> m_config;\r\n        bool m_startupExceptions = false;\r\n    };\r\n\r\n} // end namespace Catch\r\n\r\n// end catch_session.h\r\n// start catch_version.h\r\n\r\n#include <iosfwd>\r\n\r\nnamespace Catch {\r\n\r\n    // Versioning information\r\n    struct Version {\r\n        Version( Version const& ) = delete;\r\n        Version& operator=( Version const& ) = delete;\r\n        Version(    unsigned int _majorVersion,\r\n                    unsigned int _minorVersion,\r\n                    unsigned int _patchNumber,\r\n                    char const * const _branchName,\r\n                    unsigned int _buildNumber );\r\n\r\n        unsigned int const majorVersion;\r\n        unsigned int const minorVersion;\r\n        unsigned int const patchNumber;\r\n\r\n        // buildNumber is only used if branchName is not null\r\n        char const * const branchName;\r\n        unsigned int const buildNumber;\r\n\r\n        friend std::ostream& operator << ( std::ostream& os, Version const& version );\r\n    };\r\n\r\n    Version const& libraryVersion();\r\n}\r\n\r\n// end catch_version.h\r\n#include <cstdlib>\r\n#include <iomanip>\r\n\r\nnamespace Catch {\r\n\r\n    namespace {\r\n        const int MaxExitCode = 255;\r\n\r\n        IStreamingReporterPtr createReporter(std::string const& reporterName, IConfigPtr const& config) {\r\n            auto reporter = Catch::getRegistryHub().getReporterRegistry().create(reporterName, config);\r\n            CATCH_ENFORCE(reporter, \"No reporter registered with name: '\" << reporterName << \"'\");\r\n\r\n            return reporter;\r\n        }\r\n\r\n        IStreamingReporterPtr makeReporter(std::shared_ptr<Config> const& config) {\r\n            if (Catch::getRegistryHub().getReporterRegistry().getListeners().empty()) {\r\n                return createReporter(config->getReporterName(), config);\r\n            }\r\n\r\n            // On older platforms, returning std::unique_ptr<ListeningReporter>\r\n            // when the return type is std::unique_ptr<IStreamingReporter>\r\n            // doesn't compile without a std::move call. However, this causes\r\n            // a warning on newer platforms. Thus, we have to work around\r\n            // it a bit and downcast the pointer manually.\r\n            auto ret = std::unique_ptr<IStreamingReporter>(new ListeningReporter);\r\n            auto& multi = static_cast<ListeningReporter&>(*ret);\r\n            auto const& listeners = Catch::getRegistryHub().getReporterRegistry().getListeners();\r\n            for (auto const& listener : listeners) {\r\n                multi.addListener(listener->create(Catch::ReporterConfig(config)));\r\n            }\r\n            multi.addReporter(createReporter(config->getReporterName(), config));\r\n            return ret;\r\n        }\r\n\r\n        Catch::Totals runTests(std::shared_ptr<Config> const& config) {\r\n            auto reporter = makeReporter(config);\r\n\r\n            RunContext context(config, std::move(reporter));\r\n\r\n            Totals totals;\r\n\r\n            context.testGroupStarting(config->name(), 1, 1);\r\n\r\n            TestSpec testSpec = config->testSpec();\r\n\r\n            auto const& allTestCases = getAllTestCasesSorted(*config);\r\n            for (auto const& testCase : allTestCases) {\r\n                if (!context.aborting() && matchTest(testCase, testSpec, *config))\r\n                    totals += context.runTest(testCase);\r\n                else\r\n                    context.reporter().skipTest(testCase);\r\n            }\r\n\r\n            if (config->warnAboutNoTests() && totals.testCases.total() == 0) {\r\n                ReusableStringStream testConfig;\r\n\r\n                bool first = true;\r\n                for (const auto& input : config->getTestsOrTags()) {\r\n                    if (!first) { testConfig << ' '; }\r\n                    first = false;\r\n                    testConfig << input;\r\n                }\r\n\r\n                context.reporter().noMatchingTestCases(testConfig.str());\r\n                totals.error = -1;\r\n            }\r\n\r\n            context.testGroupEnded(config->name(), totals, 1, 1);\r\n            return totals;\r\n        }\r\n\r\n        void applyFilenamesAsTags(Catch::IConfig const& config) {\r\n            auto& tests = const_cast<std::vector<TestCase>&>(getAllTestCasesSorted(config));\r\n            for (auto& testCase : tests) {\r\n                auto tags = testCase.tags;\r\n\r\n                std::string filename = testCase.lineInfo.file;\r\n                auto lastSlash = filename.find_last_of(\"\\\\/\");\r\n                if (lastSlash != std::string::npos) {\r\n                    filename.erase(0, lastSlash);\r\n                    filename[0] = '#';\r\n                }\r\n\r\n                auto lastDot = filename.find_last_of('.');\r\n                if (lastDot != std::string::npos) {\r\n                    filename.erase(lastDot);\r\n                }\r\n\r\n                tags.push_back(std::move(filename));\r\n                setTags(testCase, tags);\r\n            }\r\n        }\r\n\r\n    } // anon namespace\r\n\r\n    Session::Session() {\r\n        static bool alreadyInstantiated = false;\r\n        if( alreadyInstantiated ) {\r\n            CATCH_TRY { CATCH_INTERNAL_ERROR( \"Only one instance of Catch::Session can ever be used\" ); }\r\n            CATCH_CATCH_ALL { getMutableRegistryHub().registerStartupException(); }\r\n        }\r\n\r\n        // There cannot be exceptions at startup in no-exception mode.\r\n#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS)\r\n        const auto& exceptions = getRegistryHub().getStartupExceptionRegistry().getExceptions();\r\n        if ( !exceptions.empty() ) {\r\n            m_startupExceptions = true;\r\n            Colour colourGuard( Colour::Red );\r\n            Catch::cerr() << \"Errors occurred during startup!\" << '\\n';\r\n            // iterate over all exceptions and notify user\r\n            for ( const auto& ex_ptr : exceptions ) {\r\n                try {\r\n                    std::rethrow_exception(ex_ptr);\r\n                } catch ( std::exception const& ex ) {\r\n                    Catch::cerr() << Column( ex.what() ).indent(2) << '\\n';\r\n                }\r\n            }\r\n        }\r\n#endif\r\n\r\n        alreadyInstantiated = true;\r\n        m_cli = makeCommandLineParser( m_configData );\r\n    }\r\n    Session::~Session() {\r\n        Catch::cleanUp();\r\n    }\r\n\r\n    void Session::showHelp() const {\r\n        Catch::cout()\r\n                << \"\\nCatch v\" << libraryVersion() << \"\\n\"\r\n                << m_cli << std::endl\r\n                << \"For more detailed usage please see the project docs\\n\" << std::endl;\r\n    }\r\n    void Session::libIdentify() {\r\n        Catch::cout()\r\n                << std::left << std::setw(16) << \"description: \" << \"A Catch test executable\\n\"\r\n                << std::left << std::setw(16) << \"category: \" << \"testframework\\n\"\r\n                << std::left << std::setw(16) << \"framework: \" << \"Catch Test\\n\"\r\n                << std::left << std::setw(16) << \"version: \" << libraryVersion() << std::endl;\r\n    }\r\n\r\n    int Session::applyCommandLine( int argc, char const * const * argv ) {\r\n        if( m_startupExceptions )\r\n            return 1;\r\n\r\n        auto result = m_cli.parse( clara::Args( argc, argv ) );\r\n        if( !result ) {\r\n            config();\r\n            getCurrentMutableContext().setConfig(m_config);\r\n            Catch::cerr()\r\n                << Colour( Colour::Red )\r\n                << \"\\nError(s) in input:\\n\"\r\n                << Column( result.errorMessage() ).indent( 2 )\r\n                << \"\\n\\n\";\r\n            Catch::cerr() << \"Run with -? for usage\\n\" << std::endl;\r\n            return MaxExitCode;\r\n        }\r\n\r\n        if( m_configData.showHelp )\r\n            showHelp();\r\n        if( m_configData.libIdentify )\r\n            libIdentify();\r\n        m_config.reset();\r\n        return 0;\r\n    }\r\n\r\n#if defined(CATCH_CONFIG_WCHAR) && defined(WIN32) && defined(UNICODE)\r\n    int Session::applyCommandLine( int argc, wchar_t const * const * argv ) {\r\n\r\n        char **utf8Argv = new char *[ argc ];\r\n\r\n        for ( int i = 0; i < argc; ++i ) {\r\n            int bufSize = WideCharToMultiByte( CP_UTF8, 0, argv[i], -1, NULL, 0, NULL, NULL );\r\n\r\n            utf8Argv[ i ] = new char[ bufSize ];\r\n\r\n            WideCharToMultiByte( CP_UTF8, 0, argv[i], -1, utf8Argv[i], bufSize, NULL, NULL );\r\n        }\r\n\r\n        int returnCode = applyCommandLine( argc, utf8Argv );\r\n\r\n        for ( int i = 0; i < argc; ++i )\r\n            delete [] utf8Argv[ i ];\r\n\r\n        delete [] utf8Argv;\r\n\r\n        return returnCode;\r\n    }\r\n#endif\r\n\r\n    void Session::useConfigData( ConfigData const& configData ) {\r\n        m_configData = configData;\r\n        m_config.reset();\r\n    }\r\n\r\n    int Session::run() {\r\n        if( ( m_configData.waitForKeypress & WaitForKeypress::BeforeStart ) != 0 ) {\r\n            Catch::cout() << \"...waiting for enter/ return before starting\" << std::endl;\r\n            static_cast<void>(std::getchar());\r\n        }\r\n        int exitCode = runInternal();\r\n        if( ( m_configData.waitForKeypress & WaitForKeypress::BeforeExit ) != 0 ) {\r\n            Catch::cout() << \"...waiting for enter/ return before exiting, with code: \" << exitCode << std::endl;\r\n            static_cast<void>(std::getchar());\r\n        }\r\n        return exitCode;\r\n    }\r\n\r\n    clara::Parser const& Session::cli() const {\r\n        return m_cli;\r\n    }\r\n    void Session::cli( clara::Parser const& newParser ) {\r\n        m_cli = newParser;\r\n    }\r\n    ConfigData& Session::configData() {\r\n        return m_configData;\r\n    }\r\n    Config& Session::config() {\r\n        if( !m_config )\r\n            m_config = std::make_shared<Config>( m_configData );\r\n        return *m_config;\r\n    }\r\n\r\n    int Session::runInternal() {\r\n        if( m_startupExceptions )\r\n            return 1;\r\n\r\n        if (m_configData.showHelp || m_configData.libIdentify) {\r\n            return 0;\r\n        }\r\n\r\n        CATCH_TRY {\r\n            config(); // Force config to be constructed\r\n\r\n            seedRng( *m_config );\r\n\r\n            if( m_configData.filenamesAsTags )\r\n                applyFilenamesAsTags( *m_config );\r\n\r\n            // Handle list request\r\n            if( Option<std::size_t> listed = list( m_config ) )\r\n                return static_cast<int>( *listed );\r\n\r\n            auto totals = runTests( m_config );\r\n            // Note that on unices only the lower 8 bits are usually used, clamping\r\n            // the return value to 255 prevents false negative when some multiple\r\n            // of 256 tests has failed\r\n            return (std::min) (MaxExitCode, (std::max) (totals.error, static_cast<int>(totals.assertions.failed)));\r\n        }\r\n#if !defined(CATCH_CONFIG_DISABLE_EXCEPTIONS)\r\n        catch( std::exception& ex ) {\r\n            Catch::cerr() << ex.what() << std::endl;\r\n            return MaxExitCode;\r\n        }\r\n#endif\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_session.cpp\r\n// start catch_singletons.cpp\r\n\r\n#include <vector>\r\n\r\nnamespace Catch {\r\n\r\n    namespace {\r\n        static auto getSingletons() -> std::vector<ISingleton*>*& {\r\n            static std::vector<ISingleton*>* g_singletons = nullptr;\r\n            if( !g_singletons )\r\n                g_singletons = new std::vector<ISingleton*>();\r\n            return g_singletons;\r\n        }\r\n    }\r\n\r\n    ISingleton::~ISingleton() {}\r\n\r\n    void addSingleton(ISingleton* singleton ) {\r\n        getSingletons()->push_back( singleton );\r\n    }\r\n    void cleanupSingletons() {\r\n        auto& singletons = getSingletons();\r\n        for( auto singleton : *singletons )\r\n            delete singleton;\r\n        delete singletons;\r\n        singletons = nullptr;\r\n    }\r\n\r\n} // namespace Catch\r\n// end catch_singletons.cpp\r\n// start catch_startup_exception_registry.cpp\r\n\r\nnamespace Catch {\r\nvoid StartupExceptionRegistry::add( std::exception_ptr const& exception ) noexcept {\r\n        CATCH_TRY {\r\n            m_exceptions.push_back(exception);\r\n        } CATCH_CATCH_ALL {\r\n            // If we run out of memory during start-up there's really not a lot more we can do about it\r\n            std::terminate();\r\n        }\r\n    }\r\n\r\n    std::vector<std::exception_ptr> const& StartupExceptionRegistry::getExceptions() const noexcept {\r\n        return m_exceptions;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_startup_exception_registry.cpp\r\n// start catch_stream.cpp\r\n\r\n#include <cstdio>\r\n#include <iostream>\r\n#include <fstream>\r\n#include <sstream>\r\n#include <vector>\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    Catch::IStream::~IStream() = default;\r\n\r\n    namespace detail { namespace {\r\n        template<typename WriterF, std::size_t bufferSize=256>\r\n        class StreamBufImpl : public std::streambuf {\r\n            char data[bufferSize];\r\n            WriterF m_writer;\r\n\r\n        public:\r\n            StreamBufImpl() {\r\n                setp( data, data + sizeof(data) );\r\n            }\r\n\r\n            ~StreamBufImpl() noexcept {\r\n                StreamBufImpl::sync();\r\n            }\r\n\r\n        private:\r\n            int overflow( int c ) override {\r\n                sync();\r\n\r\n                if( c != EOF ) {\r\n                    if( pbase() == epptr() )\r\n                        m_writer( std::string( 1, static_cast<char>( c ) ) );\r\n                    else\r\n                        sputc( static_cast<char>( c ) );\r\n                }\r\n                return 0;\r\n            }\r\n\r\n            int sync() override {\r\n                if( pbase() != pptr() ) {\r\n                    m_writer( std::string( pbase(), static_cast<std::string::size_type>( pptr() - pbase() ) ) );\r\n                    setp( pbase(), epptr() );\r\n                }\r\n                return 0;\r\n            }\r\n        };\r\n\r\n        ///////////////////////////////////////////////////////////////////////////\r\n\r\n        struct OutputDebugWriter {\r\n\r\n            void operator()( std::string const&str ) {\r\n                writeToDebugConsole( str );\r\n            }\r\n        };\r\n\r\n        ///////////////////////////////////////////////////////////////////////////\r\n\r\n        class FileStream : public IStream {\r\n            mutable std::ofstream m_ofs;\r\n        public:\r\n            FileStream( StringRef filename ) {\r\n                m_ofs.open( filename.c_str() );\r\n                CATCH_ENFORCE( !m_ofs.fail(), \"Unable to open file: '\" << filename << \"'\" );\r\n            }\r\n            ~FileStream() override = default;\r\n        public: // IStream\r\n            std::ostream& stream() const override {\r\n                return m_ofs;\r\n            }\r\n        };\r\n\r\n        ///////////////////////////////////////////////////////////////////////////\r\n\r\n        class CoutStream : public IStream {\r\n            mutable std::ostream m_os;\r\n        public:\r\n            // Store the streambuf from cout up-front because\r\n            // cout may get redirected when running tests\r\n            CoutStream() : m_os( Catch::cout().rdbuf() ) {}\r\n            ~CoutStream() override = default;\r\n\r\n        public: // IStream\r\n            std::ostream& stream() const override { return m_os; }\r\n        };\r\n\r\n        ///////////////////////////////////////////////////////////////////////////\r\n\r\n        class DebugOutStream : public IStream {\r\n            std::unique_ptr<StreamBufImpl<OutputDebugWriter>> m_streamBuf;\r\n            mutable std::ostream m_os;\r\n        public:\r\n            DebugOutStream()\r\n            :   m_streamBuf( new StreamBufImpl<OutputDebugWriter>() ),\r\n                m_os( m_streamBuf.get() )\r\n            {}\r\n\r\n            ~DebugOutStream() override = default;\r\n\r\n        public: // IStream\r\n            std::ostream& stream() const override { return m_os; }\r\n        };\r\n\r\n    }} // namespace anon::detail\r\n\r\n    ///////////////////////////////////////////////////////////////////////////\r\n\r\n    auto makeStream( StringRef const &filename ) -> IStream const* {\r\n        if( filename.empty() )\r\n            return new detail::CoutStream();\r\n        else if( filename[0] == '%' ) {\r\n            if( filename == \"%debug\" )\r\n                return new detail::DebugOutStream();\r\n            else\r\n                CATCH_ERROR( \"Unrecognised stream: '\" << filename << \"'\" );\r\n        }\r\n        else\r\n            return new detail::FileStream( filename );\r\n    }\r\n\r\n    // This class encapsulates the idea of a pool of ostringstreams that can be reused.\r\n    struct StringStreams {\r\n        std::vector<std::unique_ptr<std::ostringstream>> m_streams;\r\n        std::vector<std::size_t> m_unused;\r\n        std::ostringstream m_referenceStream; // Used for copy state/ flags from\r\n\r\n        auto add() -> std::size_t {\r\n            if( m_unused.empty() ) {\r\n                m_streams.push_back( std::unique_ptr<std::ostringstream>( new std::ostringstream ) );\r\n                return m_streams.size()-1;\r\n            }\r\n            else {\r\n                auto index = m_unused.back();\r\n                m_unused.pop_back();\r\n                return index;\r\n            }\r\n        }\r\n\r\n        void release( std::size_t index ) {\r\n            m_streams[index]->copyfmt( m_referenceStream ); // Restore initial flags and other state\r\n            m_unused.push_back(index);\r\n        }\r\n    };\r\n\r\n    ReusableStringStream::ReusableStringStream()\r\n    :   m_index( Singleton<StringStreams>::getMutable().add() ),\r\n        m_oss( Singleton<StringStreams>::getMutable().m_streams[m_index].get() )\r\n    {}\r\n\r\n    ReusableStringStream::~ReusableStringStream() {\r\n        static_cast<std::ostringstream*>( m_oss )->str(\"\");\r\n        m_oss->clear();\r\n        Singleton<StringStreams>::getMutable().release( m_index );\r\n    }\r\n\r\n    auto ReusableStringStream::str() const -> std::string {\r\n        return static_cast<std::ostringstream*>( m_oss )->str();\r\n    }\r\n\r\n    ///////////////////////////////////////////////////////////////////////////\r\n\r\n#ifndef CATCH_CONFIG_NOSTDOUT // If you #define this you must implement these functions\r\n    std::ostream& cout() { return std::cout; }\r\n    std::ostream& cerr() { return std::cerr; }\r\n    std::ostream& clog() { return std::clog; }\r\n#endif\r\n}\r\n// end catch_stream.cpp\r\n// start catch_string_manip.cpp\r\n\r\n#include <algorithm>\r\n#include <ostream>\r\n#include <cstring>\r\n#include <cctype>\r\n\r\nnamespace Catch {\r\n\r\n    namespace {\r\n        char toLowerCh(char c) {\r\n            return static_cast<char>( std::tolower( c ) );\r\n        }\r\n    }\r\n\r\n    bool startsWith( std::string const& s, std::string const& prefix ) {\r\n        return s.size() >= prefix.size() && std::equal(prefix.begin(), prefix.end(), s.begin());\r\n    }\r\n    bool startsWith( std::string const& s, char prefix ) {\r\n        return !s.empty() && s[0] == prefix;\r\n    }\r\n    bool endsWith( std::string const& s, std::string const& suffix ) {\r\n        return s.size() >= suffix.size() && std::equal(suffix.rbegin(), suffix.rend(), s.rbegin());\r\n    }\r\n    bool endsWith( std::string const& s, char suffix ) {\r\n        return !s.empty() && s[s.size()-1] == suffix;\r\n    }\r\n    bool contains( std::string const& s, std::string const& infix ) {\r\n        return s.find( infix ) != std::string::npos;\r\n    }\r\n    void toLowerInPlace( std::string& s ) {\r\n        std::transform( s.begin(), s.end(), s.begin(), toLowerCh );\r\n    }\r\n    std::string toLower( std::string const& s ) {\r\n        std::string lc = s;\r\n        toLowerInPlace( lc );\r\n        return lc;\r\n    }\r\n    std::string trim( std::string const& str ) {\r\n        static char const* whitespaceChars = \"\\n\\r\\t \";\r\n        std::string::size_type start = str.find_first_not_of( whitespaceChars );\r\n        std::string::size_type end = str.find_last_not_of( whitespaceChars );\r\n\r\n        return start != std::string::npos ? str.substr( start, 1+end-start ) : std::string();\r\n    }\r\n\r\n    bool replaceInPlace( std::string& str, std::string const& replaceThis, std::string const& withThis ) {\r\n        bool replaced = false;\r\n        std::size_t i = str.find( replaceThis );\r\n        while( i != std::string::npos ) {\r\n            replaced = true;\r\n            str = str.substr( 0, i ) + withThis + str.substr( i+replaceThis.size() );\r\n            if( i < str.size()-withThis.size() )\r\n                i = str.find( replaceThis, i+withThis.size() );\r\n            else\r\n                i = std::string::npos;\r\n        }\r\n        return replaced;\r\n    }\r\n\r\n    pluralise::pluralise( std::size_t count, std::string const& label )\r\n    :   m_count( count ),\r\n        m_label( label )\r\n    {}\r\n\r\n    std::ostream& operator << ( std::ostream& os, pluralise const& pluraliser ) {\r\n        os << pluraliser.m_count << ' ' << pluraliser.m_label;\r\n        if( pluraliser.m_count != 1 )\r\n            os << 's';\r\n        return os;\r\n    }\r\n\r\n}\r\n// end catch_string_manip.cpp\r\n// start catch_stringref.cpp\r\n\r\n#if defined(__clang__)\r\n#    pragma clang diagnostic push\r\n#    pragma clang diagnostic ignored \"-Wexit-time-destructors\"\r\n#endif\r\n\r\n#include <ostream>\r\n#include <cstring>\r\n#include <cstdint>\r\n\r\nnamespace {\r\n    const uint32_t byte_2_lead = 0xC0;\r\n    const uint32_t byte_3_lead = 0xE0;\r\n    const uint32_t byte_4_lead = 0xF0;\r\n}\r\n\r\nnamespace Catch {\r\n    StringRef::StringRef( char const* rawChars ) noexcept\r\n    : StringRef( rawChars, static_cast<StringRef::size_type>(std::strlen(rawChars) ) )\r\n    {}\r\n\r\n    StringRef::operator std::string() const {\r\n        return std::string( m_start, m_size );\r\n    }\r\n\r\n    void StringRef::swap( StringRef& other ) noexcept {\r\n        std::swap( m_start, other.m_start );\r\n        std::swap( m_size, other.m_size );\r\n        std::swap( m_data, other.m_data );\r\n    }\r\n\r\n    auto StringRef::c_str() const -> char const* {\r\n        if( isSubstring() )\r\n           const_cast<StringRef*>( this )->takeOwnership();\r\n        return m_start;\r\n    }\r\n    auto StringRef::currentData() const noexcept -> char const* {\r\n        return m_start;\r\n    }\r\n\r\n    auto StringRef::isOwned() const noexcept -> bool {\r\n        return m_data != nullptr;\r\n    }\r\n    auto StringRef::isSubstring() const noexcept -> bool {\r\n        return m_start[m_size] != '\\0';\r\n    }\r\n\r\n    void StringRef::takeOwnership() {\r\n        if( !isOwned() ) {\r\n            m_data = new char[m_size+1];\r\n            memcpy( m_data, m_start, m_size );\r\n            m_data[m_size] = '\\0';\r\n            m_start = m_data;\r\n        }\r\n    }\r\n    auto StringRef::substr( size_type start, size_type size ) const noexcept -> StringRef {\r\n        if( start < m_size )\r\n            return StringRef( m_start+start, size );\r\n        else\r\n            return StringRef();\r\n    }\r\n    auto StringRef::operator == ( StringRef const& other ) const noexcept -> bool {\r\n        return\r\n            size() == other.size() &&\r\n            (std::strncmp( m_start, other.m_start, size() ) == 0);\r\n    }\r\n    auto StringRef::operator != ( StringRef const& other ) const noexcept -> bool {\r\n        return !operator==( other );\r\n    }\r\n\r\n    auto StringRef::operator[](size_type index) const noexcept -> char {\r\n        return m_start[index];\r\n    }\r\n\r\n    auto StringRef::numberOfCharacters() const noexcept -> size_type {\r\n        size_type noChars = m_size;\r\n        // Make adjustments for uft encodings\r\n        for( size_type i=0; i < m_size; ++i ) {\r\n            char c = m_start[i];\r\n            if( ( c & byte_2_lead ) == byte_2_lead ) {\r\n                noChars--;\r\n                if (( c & byte_3_lead ) == byte_3_lead )\r\n                    noChars--;\r\n                if( ( c & byte_4_lead ) == byte_4_lead )\r\n                    noChars--;\r\n            }\r\n        }\r\n        return noChars;\r\n    }\r\n\r\n    auto operator + ( StringRef const& lhs, StringRef const& rhs ) -> std::string {\r\n        std::string str;\r\n        str.reserve( lhs.size() + rhs.size() );\r\n        str += lhs;\r\n        str += rhs;\r\n        return str;\r\n    }\r\n    auto operator + ( StringRef const& lhs, const char* rhs ) -> std::string {\r\n        return std::string( lhs ) + std::string( rhs );\r\n    }\r\n    auto operator + ( char const* lhs, StringRef const& rhs ) -> std::string {\r\n        return std::string( lhs ) + std::string( rhs );\r\n    }\r\n\r\n    auto operator << ( std::ostream& os, StringRef const& str ) -> std::ostream& {\r\n        return os.write(str.currentData(), str.size());\r\n    }\r\n\r\n    auto operator+=( std::string& lhs, StringRef const& rhs ) -> std::string& {\r\n        lhs.append(rhs.currentData(), rhs.size());\r\n        return lhs;\r\n    }\r\n\r\n} // namespace Catch\r\n\r\n#if defined(__clang__)\r\n#    pragma clang diagnostic pop\r\n#endif\r\n// end catch_stringref.cpp\r\n// start catch_tag_alias.cpp\r\n\r\nnamespace Catch {\r\n    TagAlias::TagAlias(std::string const & _tag, SourceLineInfo _lineInfo): tag(_tag), lineInfo(_lineInfo) {}\r\n}\r\n// end catch_tag_alias.cpp\r\n// start catch_tag_alias_autoregistrar.cpp\r\n\r\nnamespace Catch {\r\n\r\n    RegistrarForTagAliases::RegistrarForTagAliases(char const* alias, char const* tag, SourceLineInfo const& lineInfo) {\r\n        CATCH_TRY {\r\n            getMutableRegistryHub().registerTagAlias(alias, tag, lineInfo);\r\n        } CATCH_CATCH_ALL {\r\n            // Do not throw when constructing global objects, instead register the exception to be processed later\r\n            getMutableRegistryHub().registerStartupException();\r\n        }\r\n    }\r\n\r\n}\r\n// end catch_tag_alias_autoregistrar.cpp\r\n// start catch_tag_alias_registry.cpp\r\n\r\n#include <sstream>\r\n\r\nnamespace Catch {\r\n\r\n    TagAliasRegistry::~TagAliasRegistry() {}\r\n\r\n    TagAlias const* TagAliasRegistry::find( std::string const& alias ) const {\r\n        auto it = m_registry.find( alias );\r\n        if( it != m_registry.end() )\r\n            return &(it->second);\r\n        else\r\n            return nullptr;\r\n    }\r\n\r\n    std::string TagAliasRegistry::expandAliases( std::string const& unexpandedTestSpec ) const {\r\n        std::string expandedTestSpec = unexpandedTestSpec;\r\n        for( auto const& registryKvp : m_registry ) {\r\n            std::size_t pos = expandedTestSpec.find( registryKvp.first );\r\n            if( pos != std::string::npos ) {\r\n                expandedTestSpec =  expandedTestSpec.substr( 0, pos ) +\r\n                                    registryKvp.second.tag +\r\n                                    expandedTestSpec.substr( pos + registryKvp.first.size() );\r\n            }\r\n        }\r\n        return expandedTestSpec;\r\n    }\r\n\r\n    void TagAliasRegistry::add( std::string const& alias, std::string const& tag, SourceLineInfo const& lineInfo ) {\r\n        CATCH_ENFORCE( startsWith(alias, \"[@\") && endsWith(alias, ']'),\r\n                      \"error: tag alias, '\" << alias << \"' is not of the form [@alias name].\\n\" << lineInfo );\r\n\r\n        CATCH_ENFORCE( m_registry.insert(std::make_pair(alias, TagAlias(tag, lineInfo))).second,\r\n                      \"error: tag alias, '\" << alias << \"' already registered.\\n\"\r\n                      << \"\\tFirst seen at: \" << find(alias)->lineInfo << \"\\n\"\r\n                      << \"\\tRedefined at: \" << lineInfo );\r\n    }\r\n\r\n    ITagAliasRegistry::~ITagAliasRegistry() {}\r\n\r\n    ITagAliasRegistry const& ITagAliasRegistry::get() {\r\n        return getRegistryHub().getTagAliasRegistry();\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_tag_alias_registry.cpp\r\n// start catch_test_case_info.cpp\r\n\r\n#include <cctype>\r\n#include <exception>\r\n#include <algorithm>\r\n#include <sstream>\r\n\r\nnamespace Catch {\r\n\r\n    namespace {\r\n        TestCaseInfo::SpecialProperties parseSpecialTag( std::string const& tag ) {\r\n            if( startsWith( tag, '.' ) ||\r\n                tag == \"!hide\" )\r\n                return TestCaseInfo::IsHidden;\r\n            else if( tag == \"!throws\" )\r\n                return TestCaseInfo::Throws;\r\n            else if( tag == \"!shouldfail\" )\r\n                return TestCaseInfo::ShouldFail;\r\n            else if( tag == \"!mayfail\" )\r\n                return TestCaseInfo::MayFail;\r\n            else if( tag == \"!nonportable\" )\r\n                return TestCaseInfo::NonPortable;\r\n            else if( tag == \"!benchmark\" )\r\n                return static_cast<TestCaseInfo::SpecialProperties>( TestCaseInfo::Benchmark | TestCaseInfo::IsHidden );\r\n            else\r\n                return TestCaseInfo::None;\r\n        }\r\n        bool isReservedTag( std::string const& tag ) {\r\n            return parseSpecialTag( tag ) == TestCaseInfo::None && tag.size() > 0 && !std::isalnum( static_cast<unsigned char>(tag[0]) );\r\n        }\r\n        void enforceNotReservedTag( std::string const& tag, SourceLineInfo const& _lineInfo ) {\r\n            CATCH_ENFORCE( !isReservedTag(tag),\r\n                          \"Tag name: [\" << tag << \"] is not allowed.\\n\"\r\n                          << \"Tag names starting with non alpha-numeric characters are reserved\\n\"\r\n                          << _lineInfo );\r\n        }\r\n    }\r\n\r\n    TestCase makeTestCase(  ITestInvoker* _testCase,\r\n                            std::string const& _className,\r\n                            NameAndTags const& nameAndTags,\r\n                            SourceLineInfo const& _lineInfo )\r\n    {\r\n        bool isHidden = false;\r\n\r\n        // Parse out tags\r\n        std::vector<std::string> tags;\r\n        std::string desc, tag;\r\n        bool inTag = false;\r\n        std::string _descOrTags = nameAndTags.tags;\r\n        for (char c : _descOrTags) {\r\n            if( !inTag ) {\r\n                if( c == '[' )\r\n                    inTag = true;\r\n                else\r\n                    desc += c;\r\n            }\r\n            else {\r\n                if( c == ']' ) {\r\n                    TestCaseInfo::SpecialProperties prop = parseSpecialTag( tag );\r\n                    if( ( prop & TestCaseInfo::IsHidden ) != 0 )\r\n                        isHidden = true;\r\n                    else if( prop == TestCaseInfo::None )\r\n                        enforceNotReservedTag( tag, _lineInfo );\r\n\r\n                    tags.push_back( tag );\r\n                    tag.clear();\r\n                    inTag = false;\r\n                }\r\n                else\r\n                    tag += c;\r\n            }\r\n        }\r\n        if( isHidden ) {\r\n            tags.push_back( \".\" );\r\n        }\r\n\r\n        TestCaseInfo info( nameAndTags.name, _className, desc, tags, _lineInfo );\r\n        return TestCase( _testCase, std::move(info) );\r\n    }\r\n\r\n    void setTags( TestCaseInfo& testCaseInfo, std::vector<std::string> tags ) {\r\n        std::sort(begin(tags), end(tags));\r\n        tags.erase(std::unique(begin(tags), end(tags)), end(tags));\r\n        testCaseInfo.lcaseTags.clear();\r\n\r\n        for( auto const& tag : tags ) {\r\n            std::string lcaseTag = toLower( tag );\r\n            testCaseInfo.properties = static_cast<TestCaseInfo::SpecialProperties>( testCaseInfo.properties | parseSpecialTag( lcaseTag ) );\r\n            testCaseInfo.lcaseTags.push_back( lcaseTag );\r\n        }\r\n        testCaseInfo.tags = std::move(tags);\r\n    }\r\n\r\n    TestCaseInfo::TestCaseInfo( std::string const& _name,\r\n                                std::string const& _className,\r\n                                std::string const& _description,\r\n                                std::vector<std::string> const& _tags,\r\n                                SourceLineInfo const& _lineInfo )\r\n    :   name( _name ),\r\n        className( _className ),\r\n        description( _description ),\r\n        lineInfo( _lineInfo ),\r\n        properties( None )\r\n    {\r\n        setTags( *this, _tags );\r\n    }\r\n\r\n    bool TestCaseInfo::isHidden() const {\r\n        return ( properties & IsHidden ) != 0;\r\n    }\r\n    bool TestCaseInfo::throws() const {\r\n        return ( properties & Throws ) != 0;\r\n    }\r\n    bool TestCaseInfo::okToFail() const {\r\n        return ( properties & (ShouldFail | MayFail ) ) != 0;\r\n    }\r\n    bool TestCaseInfo::expectedToFail() const {\r\n        return ( properties & (ShouldFail ) ) != 0;\r\n    }\r\n\r\n    std::string TestCaseInfo::tagsAsString() const {\r\n        std::string ret;\r\n        // '[' and ']' per tag\r\n        std::size_t full_size = 2 * tags.size();\r\n        for (const auto& tag : tags) {\r\n            full_size += tag.size();\r\n        }\r\n        ret.reserve(full_size);\r\n        for (const auto& tag : tags) {\r\n            ret.push_back('[');\r\n            ret.append(tag);\r\n            ret.push_back(']');\r\n        }\r\n\r\n        return ret;\r\n    }\r\n\r\n    TestCase::TestCase( ITestInvoker* testCase, TestCaseInfo&& info ) : TestCaseInfo( std::move(info) ), test( testCase ) {}\r\n\r\n    TestCase TestCase::withName( std::string const& _newName ) const {\r\n        TestCase other( *this );\r\n        other.name = _newName;\r\n        return other;\r\n    }\r\n\r\n    void TestCase::invoke() const {\r\n        test->invoke();\r\n    }\r\n\r\n    bool TestCase::operator == ( TestCase const& other ) const {\r\n        return  test.get() == other.test.get() &&\r\n                name == other.name &&\r\n                className == other.className;\r\n    }\r\n\r\n    bool TestCase::operator < ( TestCase const& other ) const {\r\n        return name < other.name;\r\n    }\r\n\r\n    TestCaseInfo const& TestCase::getTestCaseInfo() const\r\n    {\r\n        return *this;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_test_case_info.cpp\r\n// start catch_test_case_registry_impl.cpp\r\n\r\n#include <sstream>\r\n\r\nnamespace Catch {\r\n\r\n    std::vector<TestCase> sortTests( IConfig const& config, std::vector<TestCase> const& unsortedTestCases ) {\r\n\r\n        std::vector<TestCase> sorted = unsortedTestCases;\r\n\r\n        switch( config.runOrder() ) {\r\n            case RunTests::InLexicographicalOrder:\r\n                std::sort( sorted.begin(), sorted.end() );\r\n                break;\r\n            case RunTests::InRandomOrder:\r\n                seedRng( config );\r\n                std::shuffle( sorted.begin(), sorted.end(), rng() );\r\n                break;\r\n            case RunTests::InDeclarationOrder:\r\n                // already in declaration order\r\n                break;\r\n        }\r\n        return sorted;\r\n    }\r\n    bool matchTest( TestCase const& testCase, TestSpec const& testSpec, IConfig const& config ) {\r\n        return testSpec.matches( testCase ) && ( config.allowThrows() || !testCase.throws() );\r\n    }\r\n\r\n    void enforceNoDuplicateTestCases( std::vector<TestCase> const& functions ) {\r\n        std::set<TestCase> seenFunctions;\r\n        for( auto const& function : functions ) {\r\n            auto prev = seenFunctions.insert( function );\r\n            CATCH_ENFORCE( prev.second,\r\n                    \"error: TEST_CASE( \\\"\" << function.name << \"\\\" ) already defined.\\n\"\r\n                    << \"\\tFirst seen at \" << prev.first->getTestCaseInfo().lineInfo << \"\\n\"\r\n                    << \"\\tRedefined at \" << function.getTestCaseInfo().lineInfo );\r\n        }\r\n    }\r\n\r\n    std::vector<TestCase> filterTests( std::vector<TestCase> const& testCases, TestSpec const& testSpec, IConfig const& config ) {\r\n        std::vector<TestCase> filtered;\r\n        filtered.reserve( testCases.size() );\r\n        for( auto const& testCase : testCases )\r\n            if( matchTest( testCase, testSpec, config ) )\r\n                filtered.push_back( testCase );\r\n        return filtered;\r\n    }\r\n    std::vector<TestCase> const& getAllTestCasesSorted( IConfig const& config ) {\r\n        return getRegistryHub().getTestCaseRegistry().getAllTestsSorted( config );\r\n    }\r\n\r\n    void TestRegistry::registerTest( TestCase const& testCase ) {\r\n        std::string name = testCase.getTestCaseInfo().name;\r\n        if( name.empty() ) {\r\n            ReusableStringStream rss;\r\n            rss << \"Anonymous test case \" << ++m_unnamedCount;\r\n            return registerTest( testCase.withName( rss.str() ) );\r\n        }\r\n        m_functions.push_back( testCase );\r\n    }\r\n\r\n    std::vector<TestCase> const& TestRegistry::getAllTests() const {\r\n        return m_functions;\r\n    }\r\n    std::vector<TestCase> const& TestRegistry::getAllTestsSorted( IConfig const& config ) const {\r\n        if( m_sortedFunctions.empty() )\r\n            enforceNoDuplicateTestCases( m_functions );\r\n\r\n        if(  m_currentSortOrder != config.runOrder() || m_sortedFunctions.empty() ) {\r\n            m_sortedFunctions = sortTests( config, m_functions );\r\n            m_currentSortOrder = config.runOrder();\r\n        }\r\n        return m_sortedFunctions;\r\n    }\r\n\r\n    ///////////////////////////////////////////////////////////////////////////\r\n    TestInvokerAsFunction::TestInvokerAsFunction( void(*testAsFunction)() ) noexcept : m_testAsFunction( testAsFunction ) {}\r\n\r\n    void TestInvokerAsFunction::invoke() const {\r\n        m_testAsFunction();\r\n    }\r\n\r\n    std::string extractClassName( StringRef const& classOrQualifiedMethodName ) {\r\n        std::string className = classOrQualifiedMethodName;\r\n        if( startsWith( className, '&' ) )\r\n        {\r\n            std::size_t lastColons = className.rfind( \"::\" );\r\n            std::size_t penultimateColons = className.rfind( \"::\", lastColons-1 );\r\n            if( penultimateColons == std::string::npos )\r\n                penultimateColons = 1;\r\n            className = className.substr( penultimateColons, lastColons-penultimateColons );\r\n        }\r\n        return className;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_test_case_registry_impl.cpp\r\n// start catch_test_case_tracker.cpp\r\n\r\n#include <algorithm>\r\n#include <cassert>\r\n#include <stdexcept>\r\n#include <memory>\r\n#include <sstream>\r\n\r\n#if defined(__clang__)\r\n#    pragma clang diagnostic push\r\n#    pragma clang diagnostic ignored \"-Wexit-time-destructors\"\r\n#endif\r\n\r\nnamespace Catch {\r\nnamespace TestCaseTracking {\r\n\r\n    NameAndLocation::NameAndLocation( std::string const& _name, SourceLineInfo const& _location )\r\n    :   name( _name ),\r\n        location( _location )\r\n    {}\r\n\r\n    ITracker::~ITracker() = default;\r\n\r\n    TrackerContext& TrackerContext::instance() {\r\n        static TrackerContext s_instance;\r\n        return s_instance;\r\n    }\r\n\r\n    ITracker& TrackerContext::startRun() {\r\n        m_rootTracker = std::make_shared<SectionTracker>( NameAndLocation( \"{root}\", CATCH_INTERNAL_LINEINFO ), *this, nullptr );\r\n        m_currentTracker = nullptr;\r\n        m_runState = Executing;\r\n        return *m_rootTracker;\r\n    }\r\n\r\n    void TrackerContext::endRun() {\r\n        m_rootTracker.reset();\r\n        m_currentTracker = nullptr;\r\n        m_runState = NotStarted;\r\n    }\r\n\r\n    void TrackerContext::startCycle() {\r\n        m_currentTracker = m_rootTracker.get();\r\n        m_runState = Executing;\r\n    }\r\n    void TrackerContext::completeCycle() {\r\n        m_runState = CompletedCycle;\r\n    }\r\n\r\n    bool TrackerContext::completedCycle() const {\r\n        return m_runState == CompletedCycle;\r\n    }\r\n    ITracker& TrackerContext::currentTracker() {\r\n        return *m_currentTracker;\r\n    }\r\n    void TrackerContext::setCurrentTracker( ITracker* tracker ) {\r\n        m_currentTracker = tracker;\r\n    }\r\n\r\n    TrackerBase::TrackerBase( NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent )\r\n    :   m_nameAndLocation( nameAndLocation ),\r\n        m_ctx( ctx ),\r\n        m_parent( parent )\r\n    {}\r\n\r\n    NameAndLocation const& TrackerBase::nameAndLocation() const {\r\n        return m_nameAndLocation;\r\n    }\r\n    bool TrackerBase::isComplete() const {\r\n        return m_runState == CompletedSuccessfully || m_runState == Failed;\r\n    }\r\n    bool TrackerBase::isSuccessfullyCompleted() const {\r\n        return m_runState == CompletedSuccessfully;\r\n    }\r\n    bool TrackerBase::isOpen() const {\r\n        return m_runState != NotStarted && !isComplete();\r\n    }\r\n    bool TrackerBase::hasChildren() const {\r\n        return !m_children.empty();\r\n    }\r\n\r\n    void TrackerBase::addChild( ITrackerPtr const& child ) {\r\n        m_children.push_back( child );\r\n    }\r\n\r\n    ITrackerPtr TrackerBase::findChild( NameAndLocation const& nameAndLocation ) {\r\n        auto it = std::find_if( m_children.begin(), m_children.end(),\r\n            [&nameAndLocation]( ITrackerPtr const& tracker ){\r\n                return\r\n                    tracker->nameAndLocation().location == nameAndLocation.location &&\r\n                    tracker->nameAndLocation().name == nameAndLocation.name;\r\n            } );\r\n        return( it != m_children.end() )\r\n            ? *it\r\n            : nullptr;\r\n    }\r\n    ITracker& TrackerBase::parent() {\r\n        assert( m_parent ); // Should always be non-null except for root\r\n        return *m_parent;\r\n    }\r\n\r\n    void TrackerBase::openChild() {\r\n        if( m_runState != ExecutingChildren ) {\r\n            m_runState = ExecutingChildren;\r\n            if( m_parent )\r\n                m_parent->openChild();\r\n        }\r\n    }\r\n\r\n    bool TrackerBase::isSectionTracker() const { return false; }\r\n    bool TrackerBase::isGeneratorTracker() const { return false; }\r\n\r\n    void TrackerBase::open() {\r\n        m_runState = Executing;\r\n        moveToThis();\r\n        if( m_parent )\r\n            m_parent->openChild();\r\n    }\r\n\r\n    void TrackerBase::close() {\r\n\r\n        // Close any still open children (e.g. generators)\r\n        while( &m_ctx.currentTracker() != this )\r\n            m_ctx.currentTracker().close();\r\n\r\n        switch( m_runState ) {\r\n            case NeedsAnotherRun:\r\n                break;\r\n\r\n            case Executing:\r\n                m_runState = CompletedSuccessfully;\r\n                break;\r\n            case ExecutingChildren:\r\n                if( m_children.empty() || m_children.back()->isComplete() )\r\n                    m_runState = CompletedSuccessfully;\r\n                break;\r\n\r\n            case NotStarted:\r\n            case CompletedSuccessfully:\r\n            case Failed:\r\n                CATCH_INTERNAL_ERROR( \"Illogical state: \" << m_runState );\r\n\r\n            default:\r\n                CATCH_INTERNAL_ERROR( \"Unknown state: \" << m_runState );\r\n        }\r\n        moveToParent();\r\n        m_ctx.completeCycle();\r\n    }\r\n    void TrackerBase::fail() {\r\n        m_runState = Failed;\r\n        if( m_parent )\r\n            m_parent->markAsNeedingAnotherRun();\r\n        moveToParent();\r\n        m_ctx.completeCycle();\r\n    }\r\n    void TrackerBase::markAsNeedingAnotherRun() {\r\n        m_runState = NeedsAnotherRun;\r\n    }\r\n\r\n    void TrackerBase::moveToParent() {\r\n        assert( m_parent );\r\n        m_ctx.setCurrentTracker( m_parent );\r\n    }\r\n    void TrackerBase::moveToThis() {\r\n        m_ctx.setCurrentTracker( this );\r\n    }\r\n\r\n    SectionTracker::SectionTracker( NameAndLocation const& nameAndLocation, TrackerContext& ctx, ITracker* parent )\r\n    :   TrackerBase( nameAndLocation, ctx, parent )\r\n    {\r\n        if( parent ) {\r\n            while( !parent->isSectionTracker() )\r\n                parent = &parent->parent();\r\n\r\n            SectionTracker& parentSection = static_cast<SectionTracker&>( *parent );\r\n            addNextFilters( parentSection.m_filters );\r\n        }\r\n    }\r\n\r\n    bool SectionTracker::isComplete() const {\r\n        bool complete = true;\r\n\r\n        if ((m_filters.empty() || m_filters[0] == \"\") ||\r\n             std::find(m_filters.begin(), m_filters.end(),\r\n                       m_nameAndLocation.name) != m_filters.end())\r\n            complete = TrackerBase::isComplete();\r\n        return complete;\r\n\r\n    }\r\n\r\n    bool SectionTracker::isSectionTracker() const { return true; }\r\n\r\n    SectionTracker& SectionTracker::acquire( TrackerContext& ctx, NameAndLocation const& nameAndLocation ) {\r\n        std::shared_ptr<SectionTracker> section;\r\n\r\n        ITracker& currentTracker = ctx.currentTracker();\r\n        if( ITrackerPtr childTracker = currentTracker.findChild( nameAndLocation ) ) {\r\n            assert( childTracker );\r\n            assert( childTracker->isSectionTracker() );\r\n            section = std::static_pointer_cast<SectionTracker>( childTracker );\r\n        }\r\n        else {\r\n            section = std::make_shared<SectionTracker>( nameAndLocation, ctx, &currentTracker );\r\n            currentTracker.addChild( section );\r\n        }\r\n        if( !ctx.completedCycle() )\r\n            section->tryOpen();\r\n        return *section;\r\n    }\r\n\r\n    void SectionTracker::tryOpen() {\r\n        if( !isComplete() && (m_filters.empty() || m_filters[0].empty() ||  m_filters[0] == m_nameAndLocation.name ) )\r\n            open();\r\n    }\r\n\r\n    void SectionTracker::addInitialFilters( std::vector<std::string> const& filters ) {\r\n        if( !filters.empty() ) {\r\n            m_filters.push_back(\"\"); // Root - should never be consulted\r\n            m_filters.push_back(\"\"); // Test Case - not a section filter\r\n            m_filters.insert( m_filters.end(), filters.begin(), filters.end() );\r\n        }\r\n    }\r\n    void SectionTracker::addNextFilters( std::vector<std::string> const& filters ) {\r\n        if( filters.size() > 1 )\r\n            m_filters.insert( m_filters.end(), ++filters.begin(), filters.end() );\r\n    }\r\n\r\n} // namespace TestCaseTracking\r\n\r\nusing TestCaseTracking::ITracker;\r\nusing TestCaseTracking::TrackerContext;\r\nusing TestCaseTracking::SectionTracker;\r\n\r\n} // namespace Catch\r\n\r\n#if defined(__clang__)\r\n#    pragma clang diagnostic pop\r\n#endif\r\n// end catch_test_case_tracker.cpp\r\n// start catch_test_registry.cpp\r\n\r\nnamespace Catch {\r\n\r\n    auto makeTestInvoker( void(*testAsFunction)() ) noexcept -> ITestInvoker* {\r\n        return new(std::nothrow) TestInvokerAsFunction( testAsFunction );\r\n    }\r\n\r\n    NameAndTags::NameAndTags( StringRef const& name_ , StringRef const& tags_ ) noexcept : name( name_ ), tags( tags_ ) {}\r\n\r\n    AutoReg::AutoReg( ITestInvoker* invoker, SourceLineInfo const& lineInfo, StringRef const& classOrMethod, NameAndTags const& nameAndTags ) noexcept {\r\n        CATCH_TRY {\r\n            getMutableRegistryHub()\r\n                    .registerTest(\r\n                        makeTestCase(\r\n                            invoker,\r\n                            extractClassName( classOrMethod ),\r\n                            nameAndTags,\r\n                            lineInfo));\r\n        } CATCH_CATCH_ALL {\r\n            // Do not throw when constructing global objects, instead register the exception to be processed later\r\n            getMutableRegistryHub().registerStartupException();\r\n        }\r\n    }\r\n\r\n    AutoReg::~AutoReg() = default;\r\n}\r\n// end catch_test_registry.cpp\r\n// start catch_test_spec.cpp\r\n\r\n#include <algorithm>\r\n#include <string>\r\n#include <vector>\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n\r\n    TestSpec::Pattern::~Pattern() = default;\r\n    TestSpec::NamePattern::~NamePattern() = default;\r\n    TestSpec::TagPattern::~TagPattern() = default;\r\n    TestSpec::ExcludedPattern::~ExcludedPattern() = default;\r\n\r\n    TestSpec::NamePattern::NamePattern( std::string const& name )\r\n    : m_wildcardPattern( toLower( name ), CaseSensitive::No )\r\n    {}\r\n    bool TestSpec::NamePattern::matches( TestCaseInfo const& testCase ) const {\r\n        return m_wildcardPattern.matches( toLower( testCase.name ) );\r\n    }\r\n\r\n    TestSpec::TagPattern::TagPattern( std::string const& tag ) : m_tag( toLower( tag ) ) {}\r\n    bool TestSpec::TagPattern::matches( TestCaseInfo const& testCase ) const {\r\n        return std::find(begin(testCase.lcaseTags),\r\n                         end(testCase.lcaseTags),\r\n                         m_tag) != end(testCase.lcaseTags);\r\n    }\r\n\r\n    TestSpec::ExcludedPattern::ExcludedPattern( PatternPtr const& underlyingPattern ) : m_underlyingPattern( underlyingPattern ) {}\r\n    bool TestSpec::ExcludedPattern::matches( TestCaseInfo const& testCase ) const { return !m_underlyingPattern->matches( testCase ); }\r\n\r\n    bool TestSpec::Filter::matches( TestCaseInfo const& testCase ) const {\r\n        // All patterns in a filter must match for the filter to be a match\r\n        for( auto const& pattern : m_patterns ) {\r\n            if( !pattern->matches( testCase ) )\r\n                return false;\r\n        }\r\n        return true;\r\n    }\r\n\r\n    bool TestSpec::hasFilters() const {\r\n        return !m_filters.empty();\r\n    }\r\n    bool TestSpec::matches( TestCaseInfo const& testCase ) const {\r\n        // A TestSpec matches if any filter matches\r\n        for( auto const& filter : m_filters )\r\n            if( filter.matches( testCase ) )\r\n                return true;\r\n        return false;\r\n    }\r\n}\r\n// end catch_test_spec.cpp\r\n// start catch_test_spec_parser.cpp\r\n\r\nnamespace Catch {\r\n\r\n    TestSpecParser::TestSpecParser( ITagAliasRegistry const& tagAliases ) : m_tagAliases( &tagAliases ) {}\r\n\r\n    TestSpecParser& TestSpecParser::parse( std::string const& arg ) {\r\n        m_mode = None;\r\n        m_exclusion = false;\r\n        m_start = std::string::npos;\r\n        m_arg = m_tagAliases->expandAliases( arg );\r\n        m_escapeChars.clear();\r\n        for( m_pos = 0; m_pos < m_arg.size(); ++m_pos )\r\n            visitChar( m_arg[m_pos] );\r\n        if( m_mode == Name )\r\n            addPattern<TestSpec::NamePattern>();\r\n        return *this;\r\n    }\r\n    TestSpec TestSpecParser::testSpec() {\r\n        addFilter();\r\n        return m_testSpec;\r\n    }\r\n\r\n    void TestSpecParser::visitChar( char c ) {\r\n        if( m_mode == None ) {\r\n            switch( c ) {\r\n            case ' ': return;\r\n            case '~': m_exclusion = true; return;\r\n            case '[': return startNewMode( Tag, ++m_pos );\r\n            case '\"': return startNewMode( QuotedName, ++m_pos );\r\n            case '\\\\': return escape();\r\n            default: startNewMode( Name, m_pos ); break;\r\n            }\r\n        }\r\n        if( m_mode == Name ) {\r\n            if( c == ',' ) {\r\n                addPattern<TestSpec::NamePattern>();\r\n                addFilter();\r\n            }\r\n            else if( c == '[' ) {\r\n                if( subString() == \"exclude:\" )\r\n                    m_exclusion = true;\r\n                else\r\n                    addPattern<TestSpec::NamePattern>();\r\n                startNewMode( Tag, ++m_pos );\r\n            }\r\n            else if( c == '\\\\' )\r\n                escape();\r\n        }\r\n        else if( m_mode == EscapedName )\r\n            m_mode = Name;\r\n        else if( m_mode == QuotedName && c == '\"' )\r\n            addPattern<TestSpec::NamePattern>();\r\n        else if( m_mode == Tag && c == ']' )\r\n            addPattern<TestSpec::TagPattern>();\r\n    }\r\n    void TestSpecParser::startNewMode( Mode mode, std::size_t start ) {\r\n        m_mode = mode;\r\n        m_start = start;\r\n    }\r\n    void TestSpecParser::escape() {\r\n        if( m_mode == None )\r\n            m_start = m_pos;\r\n        m_mode = EscapedName;\r\n        m_escapeChars.push_back( m_pos );\r\n    }\r\n    std::string TestSpecParser::subString() const { return m_arg.substr( m_start, m_pos - m_start ); }\r\n\r\n    void TestSpecParser::addFilter() {\r\n        if( !m_currentFilter.m_patterns.empty() ) {\r\n            m_testSpec.m_filters.push_back( m_currentFilter );\r\n            m_currentFilter = TestSpec::Filter();\r\n        }\r\n    }\r\n\r\n    TestSpec parseTestSpec( std::string const& arg ) {\r\n        return TestSpecParser( ITagAliasRegistry::get() ).parse( arg ).testSpec();\r\n    }\r\n\r\n} // namespace Catch\r\n// end catch_test_spec_parser.cpp\r\n// start catch_timer.cpp\r\n\r\n#include <chrono>\r\n\r\nstatic const uint64_t nanosecondsInSecond = 1000000000;\r\n\r\nnamespace Catch {\r\n\r\n    auto getCurrentNanosecondsSinceEpoch() -> uint64_t {\r\n        return std::chrono::duration_cast<std::chrono::nanoseconds>( std::chrono::high_resolution_clock::now().time_since_epoch() ).count();\r\n    }\r\n\r\n    namespace {\r\n        auto estimateClockResolution() -> uint64_t {\r\n            uint64_t sum = 0;\r\n            static const uint64_t iterations = 1000000;\r\n\r\n            auto startTime = getCurrentNanosecondsSinceEpoch();\r\n\r\n            for( std::size_t i = 0; i < iterations; ++i ) {\r\n\r\n                uint64_t ticks;\r\n                uint64_t baseTicks = getCurrentNanosecondsSinceEpoch();\r\n                do {\r\n                    ticks = getCurrentNanosecondsSinceEpoch();\r\n                } while( ticks == baseTicks );\r\n\r\n                auto delta = ticks - baseTicks;\r\n                sum += delta;\r\n\r\n                // If we have been calibrating for over 3 seconds -- the clock\r\n                // is terrible and we should move on.\r\n                // TBD: How to signal that the measured resolution is probably wrong?\r\n                if (ticks > startTime + 3 * nanosecondsInSecond) {\r\n                    return sum / ( i + 1u );\r\n                }\r\n            }\r\n\r\n            // We're just taking the mean, here. To do better we could take the std. dev and exclude outliers\r\n            // - and potentially do more iterations if there's a high variance.\r\n            return sum/iterations;\r\n        }\r\n    }\r\n    auto getEstimatedClockResolution() -> uint64_t {\r\n        static auto s_resolution = estimateClockResolution();\r\n        return s_resolution;\r\n    }\r\n\r\n    void Timer::start() {\r\n       m_nanoseconds = getCurrentNanosecondsSinceEpoch();\r\n    }\r\n    auto Timer::getElapsedNanoseconds() const -> uint64_t {\r\n        return getCurrentNanosecondsSinceEpoch() - m_nanoseconds;\r\n    }\r\n    auto Timer::getElapsedMicroseconds() const -> uint64_t {\r\n        return getElapsedNanoseconds()/1000;\r\n    }\r\n    auto Timer::getElapsedMilliseconds() const -> unsigned int {\r\n        return static_cast<unsigned int>(getElapsedMicroseconds()/1000);\r\n    }\r\n    auto Timer::getElapsedSeconds() const -> double {\r\n        return getElapsedMicroseconds()/1000000.0;\r\n    }\r\n\r\n} // namespace Catch\r\n// end catch_timer.cpp\r\n// start catch_tostring.cpp\r\n\r\n#if defined(__clang__)\r\n#    pragma clang diagnostic push\r\n#    pragma clang diagnostic ignored \"-Wexit-time-destructors\"\r\n#    pragma clang diagnostic ignored \"-Wglobal-constructors\"\r\n#endif\r\n\r\n// Enable specific decls locally\r\n#if !defined(CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER)\r\n#define CATCH_CONFIG_ENABLE_CHRONO_STRINGMAKER\r\n#endif\r\n\r\n#include <cmath>\r\n#include <iomanip>\r\n\r\nnamespace Catch {\r\n\r\nnamespace Detail {\r\n\r\n    const std::string unprintableString = \"{?}\";\r\n\r\n    namespace {\r\n        const int hexThreshold = 255;\r\n\r\n        struct Endianness {\r\n            enum Arch { Big, Little };\r\n\r\n            static Arch which() {\r\n                union _{\r\n                    int asInt;\r\n                    char asChar[sizeof (int)];\r\n                } u;\r\n\r\n                u.asInt = 1;\r\n                return ( u.asChar[sizeof(int)-1] == 1 ) ? Big : Little;\r\n            }\r\n        };\r\n    }\r\n\r\n    std::string rawMemoryToString( const void *object, std::size_t size ) {\r\n        // Reverse order for little endian architectures\r\n        int i = 0, end = static_cast<int>( size ), inc = 1;\r\n        if( Endianness::which() == Endianness::Little ) {\r\n            i = end-1;\r\n            end = inc = -1;\r\n        }\r\n\r\n        unsigned char const *bytes = static_cast<unsigned char const *>(object);\r\n        ReusableStringStream rss;\r\n        rss << \"0x\" << std::setfill('0') << std::hex;\r\n        for( ; i != end; i += inc )\r\n             rss << std::setw(2) << static_cast<unsigned>(bytes[i]);\r\n       return rss.str();\r\n    }\r\n}\r\n\r\ntemplate<typename T>\r\nstd::string fpToString( T value, int precision ) {\r\n    if (Catch::isnan(value)) {\r\n        return \"nan\";\r\n    }\r\n\r\n    ReusableStringStream rss;\r\n    rss << std::setprecision( precision )\r\n        << std::fixed\r\n        << value;\r\n    std::string d = rss.str();\r\n    std::size_t i = d.find_last_not_of( '0' );\r\n    if( i != std::string::npos && i != d.size()-1 ) {\r\n        if( d[i] == '.' )\r\n            i++;\r\n        d = d.substr( 0, i+1 );\r\n    }\r\n    return d;\r\n}\r\n\r\n//// ======================================================= ////\r\n//\r\n//   Out-of-line defs for full specialization of StringMaker\r\n//\r\n//// ======================================================= ////\r\n\r\nstd::string StringMaker<std::string>::convert(const std::string& str) {\r\n    if (!getCurrentContext().getConfig()->showInvisibles()) {\r\n        return '\"' + str + '\"';\r\n    }\r\n\r\n    std::string s(\"\\\"\");\r\n    for (char c : str) {\r\n        switch (c) {\r\n        case '\\n':\r\n            s.append(\"\\\\n\");\r\n            break;\r\n        case '\\t':\r\n            s.append(\"\\\\t\");\r\n            break;\r\n        default:\r\n            s.push_back(c);\r\n            break;\r\n        }\r\n    }\r\n    s.append(\"\\\"\");\r\n    return s;\r\n}\r\n\r\n#ifdef CATCH_CONFIG_CPP17_STRING_VIEW\r\nstd::string StringMaker<std::string_view>::convert(std::string_view str) {\r\n    return ::Catch::Detail::stringify(std::string{ str });\r\n}\r\n#endif\r\n\r\nstd::string StringMaker<char const*>::convert(char const* str) {\r\n    if (str) {\r\n        return ::Catch::Detail::stringify(std::string{ str });\r\n    } else {\r\n        return{ \"{null string}\" };\r\n    }\r\n}\r\nstd::string StringMaker<char*>::convert(char* str) {\r\n    if (str) {\r\n        return ::Catch::Detail::stringify(std::string{ str });\r\n    } else {\r\n        return{ \"{null string}\" };\r\n    }\r\n}\r\n\r\n#ifdef CATCH_CONFIG_WCHAR\r\nstd::string StringMaker<std::wstring>::convert(const std::wstring& wstr) {\r\n    std::string s;\r\n    s.reserve(wstr.size());\r\n    for (auto c : wstr) {\r\n        s += (c <= 0xff) ? static_cast<char>(c) : '?';\r\n    }\r\n    return ::Catch::Detail::stringify(s);\r\n}\r\n\r\n# ifdef CATCH_CONFIG_CPP17_STRING_VIEW\r\nstd::string StringMaker<std::wstring_view>::convert(std::wstring_view str) {\r\n    return StringMaker<std::wstring>::convert(std::wstring(str));\r\n}\r\n# endif\r\n\r\nstd::string StringMaker<wchar_t const*>::convert(wchar_t const * str) {\r\n    if (str) {\r\n        return ::Catch::Detail::stringify(std::wstring{ str });\r\n    } else {\r\n        return{ \"{null string}\" };\r\n    }\r\n}\r\nstd::string StringMaker<wchar_t *>::convert(wchar_t * str) {\r\n    if (str) {\r\n        return ::Catch::Detail::stringify(std::wstring{ str });\r\n    } else {\r\n        return{ \"{null string}\" };\r\n    }\r\n}\r\n#endif\r\n\r\nstd::string StringMaker<int>::convert(int value) {\r\n    return ::Catch::Detail::stringify(static_cast<long long>(value));\r\n}\r\nstd::string StringMaker<long>::convert(long value) {\r\n    return ::Catch::Detail::stringify(static_cast<long long>(value));\r\n}\r\nstd::string StringMaker<long long>::convert(long long value) {\r\n    ReusableStringStream rss;\r\n    rss << value;\r\n    if (value > Detail::hexThreshold) {\r\n        rss << \" (0x\" << std::hex << value << ')';\r\n    }\r\n    return rss.str();\r\n}\r\n\r\nstd::string StringMaker<unsigned int>::convert(unsigned int value) {\r\n    return ::Catch::Detail::stringify(static_cast<unsigned long long>(value));\r\n}\r\nstd::string StringMaker<unsigned long>::convert(unsigned long value) {\r\n    return ::Catch::Detail::stringify(static_cast<unsigned long long>(value));\r\n}\r\nstd::string StringMaker<unsigned long long>::convert(unsigned long long value) {\r\n    ReusableStringStream rss;\r\n    rss << value;\r\n    if (value > Detail::hexThreshold) {\r\n        rss << \" (0x\" << std::hex << value << ')';\r\n    }\r\n    return rss.str();\r\n}\r\n\r\nstd::string StringMaker<bool>::convert(bool b) {\r\n    return b ? \"true\" : \"false\";\r\n}\r\n\r\nstd::string StringMaker<signed char>::convert(signed char value) {\r\n    if (value == '\\r') {\r\n        return \"'\\\\r'\";\r\n    } else if (value == '\\f') {\r\n        return \"'\\\\f'\";\r\n    } else if (value == '\\n') {\r\n        return \"'\\\\n'\";\r\n    } else if (value == '\\t') {\r\n        return \"'\\\\t'\";\r\n    } else if ('\\0' <= value && value < ' ') {\r\n        return ::Catch::Detail::stringify(static_cast<unsigned int>(value));\r\n    } else {\r\n        char chstr[] = \"' '\";\r\n        chstr[1] = value;\r\n        return chstr;\r\n    }\r\n}\r\nstd::string StringMaker<char>::convert(char c) {\r\n    return ::Catch::Detail::stringify(static_cast<signed char>(c));\r\n}\r\nstd::string StringMaker<unsigned char>::convert(unsigned char c) {\r\n    return ::Catch::Detail::stringify(static_cast<char>(c));\r\n}\r\n\r\nstd::string StringMaker<std::nullptr_t>::convert(std::nullptr_t) {\r\n    return \"nullptr\";\r\n}\r\n\r\nstd::string StringMaker<float>::convert(float value) {\r\n    return fpToString(value, 5) + 'f';\r\n}\r\nstd::string StringMaker<double>::convert(double value) {\r\n    return fpToString(value, 10);\r\n}\r\n\r\nstd::string ratio_string<std::atto>::symbol() { return \"a\"; }\r\nstd::string ratio_string<std::femto>::symbol() { return \"f\"; }\r\nstd::string ratio_string<std::pico>::symbol() { return \"p\"; }\r\nstd::string ratio_string<std::nano>::symbol() { return \"n\"; }\r\nstd::string ratio_string<std::micro>::symbol() { return \"u\"; }\r\nstd::string ratio_string<std::milli>::symbol() { return \"m\"; }\r\n\r\n} // end namespace Catch\r\n\r\n#if defined(__clang__)\r\n#    pragma clang diagnostic pop\r\n#endif\r\n\r\n// end catch_tostring.cpp\r\n// start catch_totals.cpp\r\n\r\nnamespace Catch {\r\n\r\n    Counts Counts::operator - ( Counts const& other ) const {\r\n        Counts diff;\r\n        diff.passed = passed - other.passed;\r\n        diff.failed = failed - other.failed;\r\n        diff.failedButOk = failedButOk - other.failedButOk;\r\n        return diff;\r\n    }\r\n\r\n    Counts& Counts::operator += ( Counts const& other ) {\r\n        passed += other.passed;\r\n        failed += other.failed;\r\n        failedButOk += other.failedButOk;\r\n        return *this;\r\n    }\r\n\r\n    std::size_t Counts::total() const {\r\n        return passed + failed + failedButOk;\r\n    }\r\n    bool Counts::allPassed() const {\r\n        return failed == 0 && failedButOk == 0;\r\n    }\r\n    bool Counts::allOk() const {\r\n        return failed == 0;\r\n    }\r\n\r\n    Totals Totals::operator - ( Totals const& other ) const {\r\n        Totals diff;\r\n        diff.assertions = assertions - other.assertions;\r\n        diff.testCases = testCases - other.testCases;\r\n        return diff;\r\n    }\r\n\r\n    Totals& Totals::operator += ( Totals const& other ) {\r\n        assertions += other.assertions;\r\n        testCases += other.testCases;\r\n        return *this;\r\n    }\r\n\r\n    Totals Totals::delta( Totals const& prevTotals ) const {\r\n        Totals diff = *this - prevTotals;\r\n        if( diff.assertions.failed > 0 )\r\n            ++diff.testCases.failed;\r\n        else if( diff.assertions.failedButOk > 0 )\r\n            ++diff.testCases.failedButOk;\r\n        else\r\n            ++diff.testCases.passed;\r\n        return diff;\r\n    }\r\n\r\n}\r\n// end catch_totals.cpp\r\n// start catch_uncaught_exceptions.cpp\r\n\r\n#include <exception>\r\n\r\nnamespace Catch {\r\n    bool uncaught_exceptions() {\r\n#if defined(CATCH_CONFIG_CPP17_UNCAUGHT_EXCEPTIONS)\r\n        return std::uncaught_exceptions() > 0;\r\n#else\r\n        return std::uncaught_exception();\r\n#endif\r\n  }\r\n} // end namespace Catch\r\n// end catch_uncaught_exceptions.cpp\r\n// start catch_version.cpp\r\n\r\n#include <ostream>\r\n\r\nnamespace Catch {\r\n\r\n    Version::Version\r\n        (   unsigned int _majorVersion,\r\n            unsigned int _minorVersion,\r\n            unsigned int _patchNumber,\r\n            char const * const _branchName,\r\n            unsigned int _buildNumber )\r\n    :   majorVersion( _majorVersion ),\r\n        minorVersion( _minorVersion ),\r\n        patchNumber( _patchNumber ),\r\n        branchName( _branchName ),\r\n        buildNumber( _buildNumber )\r\n    {}\r\n\r\n    std::ostream& operator << ( std::ostream& os, Version const& version ) {\r\n        os  << version.majorVersion << '.'\r\n            << version.minorVersion << '.'\r\n            << version.patchNumber;\r\n        // branchName is never null -> 0th char is \\0 if it is empty\r\n        if (version.branchName[0]) {\r\n            os << '-' << version.branchName\r\n               << '.' << version.buildNumber;\r\n        }\r\n        return os;\r\n    }\r\n\r\n    Version const& libraryVersion() {\r\n        static Version version( 2, 7, 0, \"\", 0 );\r\n        return version;\r\n    }\r\n\r\n}\r\n// end catch_version.cpp\r\n// start catch_wildcard_pattern.cpp\r\n\r\n#include <sstream>\r\n\r\nnamespace Catch {\r\n\r\n    WildcardPattern::WildcardPattern( std::string const& pattern,\r\n                                      CaseSensitive::Choice caseSensitivity )\r\n    :   m_caseSensitivity( caseSensitivity ),\r\n        m_pattern( adjustCase( pattern ) )\r\n    {\r\n        if( startsWith( m_pattern, '*' ) ) {\r\n            m_pattern = m_pattern.substr( 1 );\r\n            m_wildcard = WildcardAtStart;\r\n        }\r\n        if( endsWith( m_pattern, '*' ) ) {\r\n            m_pattern = m_pattern.substr( 0, m_pattern.size()-1 );\r\n            m_wildcard = static_cast<WildcardPosition>( m_wildcard | WildcardAtEnd );\r\n        }\r\n    }\r\n\r\n    bool WildcardPattern::matches( std::string const& str ) const {\r\n        switch( m_wildcard ) {\r\n            case NoWildcard:\r\n                return m_pattern == adjustCase( str );\r\n            case WildcardAtStart:\r\n                return endsWith( adjustCase( str ), m_pattern );\r\n            case WildcardAtEnd:\r\n                return startsWith( adjustCase( str ), m_pattern );\r\n            case WildcardAtBothEnds:\r\n                return contains( adjustCase( str ), m_pattern );\r\n            default:\r\n                CATCH_INTERNAL_ERROR( \"Unknown enum\" );\r\n        }\r\n    }\r\n\r\n    std::string WildcardPattern::adjustCase( std::string const& str ) const {\r\n        return m_caseSensitivity == CaseSensitive::No ? toLower( str ) : str;\r\n    }\r\n}\r\n// end catch_wildcard_pattern.cpp\r\n// start catch_xmlwriter.cpp\r\n\r\n#include <iomanip>\r\n\r\nusing uchar = unsigned char;\r\n\r\nnamespace Catch {\r\n\r\nnamespace {\r\n\r\n    size_t trailingBytes(unsigned char c) {\r\n        if ((c & 0xE0) == 0xC0) {\r\n            return 2;\r\n        }\r\n        if ((c & 0xF0) == 0xE0) {\r\n            return 3;\r\n        }\r\n        if ((c & 0xF8) == 0xF0) {\r\n            return 4;\r\n        }\r\n        CATCH_INTERNAL_ERROR(\"Invalid multibyte utf-8 start byte encountered\");\r\n    }\r\n\r\n    uint32_t headerValue(unsigned char c) {\r\n        if ((c & 0xE0) == 0xC0) {\r\n            return c & 0x1F;\r\n        }\r\n        if ((c & 0xF0) == 0xE0) {\r\n            return c & 0x0F;\r\n        }\r\n        if ((c & 0xF8) == 0xF0) {\r\n            return c & 0x07;\r\n        }\r\n        CATCH_INTERNAL_ERROR(\"Invalid multibyte utf-8 start byte encountered\");\r\n    }\r\n\r\n    void hexEscapeChar(std::ostream& os, unsigned char c) {\r\n        std::ios_base::fmtflags f(os.flags());\r\n        os << \"\\\\x\"\r\n            << std::uppercase << std::hex << std::setfill('0') << std::setw(2)\r\n            << static_cast<int>(c);\r\n        os.flags(f);\r\n    }\r\n\r\n} // anonymous namespace\r\n\r\n    XmlEncode::XmlEncode( std::string const& str, ForWhat forWhat )\r\n    :   m_str( str ),\r\n        m_forWhat( forWhat )\r\n    {}\r\n\r\n    void XmlEncode::encodeTo( std::ostream& os ) const {\r\n        // Apostrophe escaping not necessary if we always use \" to write attributes\r\n        // (see: http://www.w3.org/TR/xml/#syntax)\r\n\r\n        for( std::size_t idx = 0; idx < m_str.size(); ++ idx ) {\r\n            uchar c = m_str[idx];\r\n            switch (c) {\r\n            case '<':   os << \"&lt;\"; break;\r\n            case '&':   os << \"&amp;\"; break;\r\n\r\n            case '>':\r\n                // See: http://www.w3.org/TR/xml/#syntax\r\n                if (idx > 2 && m_str[idx - 1] == ']' && m_str[idx - 2] == ']')\r\n                    os << \"&gt;\";\r\n                else\r\n                    os << c;\r\n                break;\r\n\r\n            case '\\\"':\r\n                if (m_forWhat == ForAttributes)\r\n                    os << \"&quot;\";\r\n                else\r\n                    os << c;\r\n                break;\r\n\r\n            default:\r\n                // Check for control characters and invalid utf-8\r\n\r\n                // Escape control characters in standard ascii\r\n                // see http://stackoverflow.com/questions/404107/why-are-control-characters-illegal-in-xml-1-0\r\n                if (c < 0x09 || (c > 0x0D && c < 0x20) || c == 0x7F) {\r\n                    hexEscapeChar(os, c);\r\n                    break;\r\n                }\r\n\r\n                // Plain ASCII: Write it to stream\r\n                if (c < 0x7F) {\r\n                    os << c;\r\n                    break;\r\n                }\r\n\r\n                // UTF-8 territory\r\n                // Check if the encoding is valid and if it is not, hex escape bytes.\r\n                // Important: We do not check the exact decoded values for validity, only the encoding format\r\n                // First check that this bytes is a valid lead byte:\r\n                // This means that it is not encoded as 1111 1XXX\r\n                // Or as 10XX XXXX\r\n                if (c <  0xC0 ||\r\n                    c >= 0xF8) {\r\n                    hexEscapeChar(os, c);\r\n                    break;\r\n                }\r\n\r\n                auto encBytes = trailingBytes(c);\r\n                // Are there enough bytes left to avoid accessing out-of-bounds memory?\r\n                if (idx + encBytes - 1 >= m_str.size()) {\r\n                    hexEscapeChar(os, c);\r\n                    break;\r\n                }\r\n                // The header is valid, check data\r\n                // The next encBytes bytes must together be a valid utf-8\r\n                // This means: bitpattern 10XX XXXX and the extracted value is sane (ish)\r\n                bool valid = true;\r\n                uint32_t value = headerValue(c);\r\n                for (std::size_t n = 1; n < encBytes; ++n) {\r\n                    uchar nc = m_str[idx + n];\r\n                    valid &= ((nc & 0xC0) == 0x80);\r\n                    value = (value << 6) | (nc & 0x3F);\r\n                }\r\n\r\n                if (\r\n                    // Wrong bit pattern of following bytes\r\n                    (!valid) ||\r\n                    // Overlong encodings\r\n                    (value < 0x80) ||\r\n                    (0x80 <= value && value < 0x800   && encBytes > 2) ||\r\n                    (0x800 < value && value < 0x10000 && encBytes > 3) ||\r\n                    // Encoded value out of range\r\n                    (value >= 0x110000)\r\n                    ) {\r\n                    hexEscapeChar(os, c);\r\n                    break;\r\n                }\r\n\r\n                // If we got here, this is in fact a valid(ish) utf-8 sequence\r\n                for (std::size_t n = 0; n < encBytes; ++n) {\r\n                    os << m_str[idx + n];\r\n                }\r\n                idx += encBytes - 1;\r\n                break;\r\n            }\r\n        }\r\n    }\r\n\r\n    std::ostream& operator << ( std::ostream& os, XmlEncode const& xmlEncode ) {\r\n        xmlEncode.encodeTo( os );\r\n        return os;\r\n    }\r\n\r\n    XmlWriter::ScopedElement::ScopedElement( XmlWriter* writer )\r\n    :   m_writer( writer )\r\n    {}\r\n\r\n    XmlWriter::ScopedElement::ScopedElement( ScopedElement&& other ) noexcept\r\n    :   m_writer( other.m_writer ){\r\n        other.m_writer = nullptr;\r\n    }\r\n    XmlWriter::ScopedElement& XmlWriter::ScopedElement::operator=( ScopedElement&& other ) noexcept {\r\n        if ( m_writer ) {\r\n            m_writer->endElement();\r\n        }\r\n        m_writer = other.m_writer;\r\n        other.m_writer = nullptr;\r\n        return *this;\r\n    }\r\n\r\n    XmlWriter::ScopedElement::~ScopedElement() {\r\n        if( m_writer )\r\n            m_writer->endElement();\r\n    }\r\n\r\n    XmlWriter::ScopedElement& XmlWriter::ScopedElement::writeText( std::string const& text, bool indent ) {\r\n        m_writer->writeText( text, indent );\r\n        return *this;\r\n    }\r\n\r\n    XmlWriter::XmlWriter( std::ostream& os ) : m_os( os )\r\n    {\r\n        writeDeclaration();\r\n    }\r\n\r\n    XmlWriter::~XmlWriter() {\r\n        while( !m_tags.empty() )\r\n            endElement();\r\n    }\r\n\r\n    XmlWriter& XmlWriter::startElement( std::string const& name ) {\r\n        ensureTagClosed();\r\n        newlineIfNecessary();\r\n        m_os << m_indent << '<' << name;\r\n        m_tags.push_back( name );\r\n        m_indent += \"  \";\r\n        m_tagIsOpen = true;\r\n        return *this;\r\n    }\r\n\r\n    XmlWriter::ScopedElement XmlWriter::scopedElement( std::string const& name ) {\r\n        ScopedElement scoped( this );\r\n        startElement( name );\r\n        return scoped;\r\n    }\r\n\r\n    XmlWriter& XmlWriter::endElement() {\r\n        newlineIfNecessary();\r\n        m_indent = m_indent.substr( 0, m_indent.size()-2 );\r\n        if( m_tagIsOpen ) {\r\n            m_os << \"/>\";\r\n            m_tagIsOpen = false;\r\n        }\r\n        else {\r\n            m_os << m_indent << \"</\" << m_tags.back() << \">\";\r\n        }\r\n        m_os << std::endl;\r\n        m_tags.pop_back();\r\n        return *this;\r\n    }\r\n\r\n    XmlWriter& XmlWriter::writeAttribute( std::string const& name, std::string const& attribute ) {\r\n        if( !name.empty() && !attribute.empty() )\r\n            m_os << ' ' << name << \"=\\\"\" << XmlEncode( attribute, XmlEncode::ForAttributes ) << '\"';\r\n        return *this;\r\n    }\r\n\r\n    XmlWriter& XmlWriter::writeAttribute( std::string const& name, bool attribute ) {\r\n        m_os << ' ' << name << \"=\\\"\" << ( attribute ? \"true\" : \"false\" ) << '\"';\r\n        return *this;\r\n    }\r\n\r\n    XmlWriter& XmlWriter::writeText( std::string const& text, bool indent ) {\r\n        if( !text.empty() ){\r\n            bool tagWasOpen = m_tagIsOpen;\r\n            ensureTagClosed();\r\n            if( tagWasOpen && indent )\r\n                m_os << m_indent;\r\n            m_os << XmlEncode( text );\r\n            m_needsNewline = true;\r\n        }\r\n        return *this;\r\n    }\r\n\r\n    XmlWriter& XmlWriter::writeComment( std::string const& text ) {\r\n        ensureTagClosed();\r\n        m_os << m_indent << \"<!--\" << text << \"-->\";\r\n        m_needsNewline = true;\r\n        return *this;\r\n    }\r\n\r\n    void XmlWriter::writeStylesheetRef( std::string const& url ) {\r\n        m_os << \"<?xml-stylesheet type=\\\"text/xsl\\\" href=\\\"\" << url << \"\\\"?>\\n\";\r\n    }\r\n\r\n    XmlWriter& XmlWriter::writeBlankLine() {\r\n        ensureTagClosed();\r\n        m_os << '\\n';\r\n        return *this;\r\n    }\r\n\r\n    void XmlWriter::ensureTagClosed() {\r\n        if( m_tagIsOpen ) {\r\n            m_os << \">\" << std::endl;\r\n            m_tagIsOpen = false;\r\n        }\r\n    }\r\n\r\n    void XmlWriter::writeDeclaration() {\r\n        m_os << \"<?xml version=\\\"1.0\\\" encoding=\\\"UTF-8\\\"?>\\n\";\r\n    }\r\n\r\n    void XmlWriter::newlineIfNecessary() {\r\n        if( m_needsNewline ) {\r\n            m_os << std::endl;\r\n            m_needsNewline = false;\r\n        }\r\n    }\r\n}\r\n// end catch_xmlwriter.cpp\r\n// start catch_reporter_bases.cpp\r\n\r\n#include <cstring>\r\n#include <cfloat>\r\n#include <cstdio>\r\n#include <cassert>\r\n#include <memory>\r\n\r\nnamespace Catch {\r\n    void prepareExpandedExpression(AssertionResult& result) {\r\n        result.getExpandedExpression();\r\n    }\r\n\r\n    // Because formatting using c++ streams is stateful, drop down to C is required\r\n    // Alternatively we could use stringstream, but its performance is... not good.\r\n    std::string getFormattedDuration( double duration ) {\r\n        // Max exponent + 1 is required to represent the whole part\r\n        // + 1 for decimal point\r\n        // + 3 for the 3 decimal places\r\n        // + 1 for null terminator\r\n        const std::size_t maxDoubleSize = DBL_MAX_10_EXP + 1 + 1 + 3 + 1;\r\n        char buffer[maxDoubleSize];\r\n\r\n        // Save previous errno, to prevent sprintf from overwriting it\r\n        ErrnoGuard guard;\r\n#ifdef _MSC_VER\r\n        sprintf_s(buffer, \"%.3f\", duration);\r\n#else\r\n        std::sprintf(buffer, \"%.3f\", duration);\r\n#endif\r\n        return std::string(buffer);\r\n    }\r\n\r\n    TestEventListenerBase::TestEventListenerBase(ReporterConfig const & _config)\r\n        :StreamingReporterBase(_config) {}\r\n\r\n    std::set<Verbosity> TestEventListenerBase::getSupportedVerbosities() {\r\n        return { Verbosity::Quiet, Verbosity::Normal, Verbosity::High };\r\n    }\r\n\r\n    void TestEventListenerBase::assertionStarting(AssertionInfo const &) {}\r\n\r\n    bool TestEventListenerBase::assertionEnded(AssertionStats const &) {\r\n        return false;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_reporter_bases.cpp\r\n// start catch_reporter_compact.cpp\r\n\r\nnamespace {\r\n\r\n#ifdef CATCH_PLATFORM_MAC\r\n    const char* failedString() { return \"FAILED\"; }\r\n    const char* passedString() { return \"PASSED\"; }\r\n#else\r\n    const char* failedString() { return \"failed\"; }\r\n    const char* passedString() { return \"passed\"; }\r\n#endif\r\n\r\n    // Colour::LightGrey\r\n    Catch::Colour::Code dimColour() { return Catch::Colour::FileName; }\r\n\r\n    std::string bothOrAll( std::size_t count ) {\r\n        return count == 1 ? std::string() :\r\n               count == 2 ? \"both \" : \"all \" ;\r\n    }\r\n\r\n} // anon namespace\r\n\r\nnamespace Catch {\r\nnamespace {\r\n// Colour, message variants:\r\n// - white: No tests ran.\r\n// -   red: Failed [both/all] N test cases, failed [both/all] M assertions.\r\n// - white: Passed [both/all] N test cases (no assertions).\r\n// -   red: Failed N tests cases, failed M assertions.\r\n// - green: Passed [both/all] N tests cases with M assertions.\r\nvoid printTotals(std::ostream& out, const Totals& totals) {\r\n    if (totals.testCases.total() == 0) {\r\n        out << \"No tests ran.\";\r\n    } else if (totals.testCases.failed == totals.testCases.total()) {\r\n        Colour colour(Colour::ResultError);\r\n        const std::string qualify_assertions_failed =\r\n            totals.assertions.failed == totals.assertions.total() ?\r\n            bothOrAll(totals.assertions.failed) : std::string();\r\n        out <<\r\n            \"Failed \" << bothOrAll(totals.testCases.failed)\r\n            << pluralise(totals.testCases.failed, \"test case\") << \", \"\r\n            \"failed \" << qualify_assertions_failed <<\r\n            pluralise(totals.assertions.failed, \"assertion\") << '.';\r\n    } else if (totals.assertions.total() == 0) {\r\n        out <<\r\n            \"Passed \" << bothOrAll(totals.testCases.total())\r\n            << pluralise(totals.testCases.total(), \"test case\")\r\n            << \" (no assertions).\";\r\n    } else if (totals.assertions.failed) {\r\n        Colour colour(Colour::ResultError);\r\n        out <<\r\n            \"Failed \" << pluralise(totals.testCases.failed, \"test case\") << \", \"\r\n            \"failed \" << pluralise(totals.assertions.failed, \"assertion\") << '.';\r\n    } else {\r\n        Colour colour(Colour::ResultSuccess);\r\n        out <<\r\n            \"Passed \" << bothOrAll(totals.testCases.passed)\r\n            << pluralise(totals.testCases.passed, \"test case\") <<\r\n            \" with \" << pluralise(totals.assertions.passed, \"assertion\") << '.';\r\n    }\r\n}\r\n\r\n// Implementation of CompactReporter formatting\r\nclass AssertionPrinter {\r\npublic:\r\n    AssertionPrinter& operator= (AssertionPrinter const&) = delete;\r\n    AssertionPrinter(AssertionPrinter const&) = delete;\r\n    AssertionPrinter(std::ostream& _stream, AssertionStats const& _stats, bool _printInfoMessages)\r\n        : stream(_stream)\r\n        , result(_stats.assertionResult)\r\n        , messages(_stats.infoMessages)\r\n        , itMessage(_stats.infoMessages.begin())\r\n        , printInfoMessages(_printInfoMessages) {}\r\n\r\n    void print() {\r\n        printSourceInfo();\r\n\r\n        itMessage = messages.begin();\r\n\r\n        switch (result.getResultType()) {\r\n        case ResultWas::Ok:\r\n            printResultType(Colour::ResultSuccess, passedString());\r\n            printOriginalExpression();\r\n            printReconstructedExpression();\r\n            if (!result.hasExpression())\r\n                printRemainingMessages(Colour::None);\r\n            else\r\n                printRemainingMessages();\r\n            break;\r\n        case ResultWas::ExpressionFailed:\r\n            if (result.isOk())\r\n                printResultType(Colour::ResultSuccess, failedString() + std::string(\" - but was ok\"));\r\n            else\r\n                printResultType(Colour::Error, failedString());\r\n            printOriginalExpression();\r\n            printReconstructedExpression();\r\n            printRemainingMessages();\r\n            break;\r\n        case ResultWas::ThrewException:\r\n            printResultType(Colour::Error, failedString());\r\n            printIssue(\"unexpected exception with message:\");\r\n            printMessage();\r\n            printExpressionWas();\r\n            printRemainingMessages();\r\n            break;\r\n        case ResultWas::FatalErrorCondition:\r\n            printResultType(Colour::Error, failedString());\r\n            printIssue(\"fatal error condition with message:\");\r\n            printMessage();\r\n            printExpressionWas();\r\n            printRemainingMessages();\r\n            break;\r\n        case ResultWas::DidntThrowException:\r\n            printResultType(Colour::Error, failedString());\r\n            printIssue(\"expected exception, got none\");\r\n            printExpressionWas();\r\n            printRemainingMessages();\r\n            break;\r\n        case ResultWas::Info:\r\n            printResultType(Colour::None, \"info\");\r\n            printMessage();\r\n            printRemainingMessages();\r\n            break;\r\n        case ResultWas::Warning:\r\n            printResultType(Colour::None, \"warning\");\r\n            printMessage();\r\n            printRemainingMessages();\r\n            break;\r\n        case ResultWas::ExplicitFailure:\r\n            printResultType(Colour::Error, failedString());\r\n            printIssue(\"explicitly\");\r\n            printRemainingMessages(Colour::None);\r\n            break;\r\n            // These cases are here to prevent compiler warnings\r\n        case ResultWas::Unknown:\r\n        case ResultWas::FailureBit:\r\n        case ResultWas::Exception:\r\n            printResultType(Colour::Error, \"** internal error **\");\r\n            break;\r\n        }\r\n    }\r\n\r\nprivate:\r\n    void printSourceInfo() const {\r\n        Colour colourGuard(Colour::FileName);\r\n        stream << result.getSourceInfo() << ':';\r\n    }\r\n\r\n    void printResultType(Colour::Code colour, std::string const& passOrFail) const {\r\n        if (!passOrFail.empty()) {\r\n            {\r\n                Colour colourGuard(colour);\r\n                stream << ' ' << passOrFail;\r\n            }\r\n            stream << ':';\r\n        }\r\n    }\r\n\r\n    void printIssue(std::string const& issue) const {\r\n        stream << ' ' << issue;\r\n    }\r\n\r\n    void printExpressionWas() {\r\n        if (result.hasExpression()) {\r\n            stream << ';';\r\n            {\r\n                Colour colour(dimColour());\r\n                stream << \" expression was:\";\r\n            }\r\n            printOriginalExpression();\r\n        }\r\n    }\r\n\r\n    void printOriginalExpression() const {\r\n        if (result.hasExpression()) {\r\n            stream << ' ' << result.getExpression();\r\n        }\r\n    }\r\n\r\n    void printReconstructedExpression() const {\r\n        if (result.hasExpandedExpression()) {\r\n            {\r\n                Colour colour(dimColour());\r\n                stream << \" for: \";\r\n            }\r\n            stream << result.getExpandedExpression();\r\n        }\r\n    }\r\n\r\n    void printMessage() {\r\n        if (itMessage != messages.end()) {\r\n            stream << \" '\" << itMessage->message << '\\'';\r\n            ++itMessage;\r\n        }\r\n    }\r\n\r\n    void printRemainingMessages(Colour::Code colour = dimColour()) {\r\n        if (itMessage == messages.end())\r\n            return;\r\n\r\n        // using messages.end() directly yields (or auto) compilation error:\r\n        std::vector<MessageInfo>::const_iterator itEnd = messages.end();\r\n        const std::size_t N = static_cast<std::size_t>(std::distance(itMessage, itEnd));\r\n\r\n        {\r\n            Colour colourGuard(colour);\r\n            stream << \" with \" << pluralise(N, \"message\") << ':';\r\n        }\r\n\r\n        for (; itMessage != itEnd; ) {\r\n            // If this assertion is a warning ignore any INFO messages\r\n            if (printInfoMessages || itMessage->type != ResultWas::Info) {\r\n                stream << \" '\" << itMessage->message << '\\'';\r\n                if (++itMessage != itEnd) {\r\n                    Colour colourGuard(dimColour());\r\n                    stream << \" and\";\r\n                }\r\n            }\r\n        }\r\n    }\r\n\r\nprivate:\r\n    std::ostream& stream;\r\n    AssertionResult const& result;\r\n    std::vector<MessageInfo> messages;\r\n    std::vector<MessageInfo>::const_iterator itMessage;\r\n    bool printInfoMessages;\r\n};\r\n\r\n} // anon namespace\r\n\r\n        std::string CompactReporter::getDescription() {\r\n            return \"Reports test results on a single line, suitable for IDEs\";\r\n        }\r\n\r\n        ReporterPreferences CompactReporter::getPreferences() const {\r\n            return m_reporterPrefs;\r\n        }\r\n\r\n        void CompactReporter::noMatchingTestCases( std::string const& spec ) {\r\n            stream << \"No test cases matched '\" << spec << '\\'' << std::endl;\r\n        }\r\n\r\n        void CompactReporter::assertionStarting( AssertionInfo const& ) {}\r\n\r\n        bool CompactReporter::assertionEnded( AssertionStats const& _assertionStats ) {\r\n            AssertionResult const& result = _assertionStats.assertionResult;\r\n\r\n            bool printInfoMessages = true;\r\n\r\n            // Drop out if result was successful and we're not printing those\r\n            if( !m_config->includeSuccessfulResults() && result.isOk() ) {\r\n                if( result.getResultType() != ResultWas::Warning )\r\n                    return false;\r\n                printInfoMessages = false;\r\n            }\r\n\r\n            AssertionPrinter printer( stream, _assertionStats, printInfoMessages );\r\n            printer.print();\r\n\r\n            stream << std::endl;\r\n            return true;\r\n        }\r\n\r\n        void CompactReporter::sectionEnded(SectionStats const& _sectionStats) {\r\n            if (m_config->showDurations() == ShowDurations::Always) {\r\n                stream << getFormattedDuration(_sectionStats.durationInSeconds) << \" s: \" << _sectionStats.sectionInfo.name << std::endl;\r\n            }\r\n        }\r\n\r\n        void CompactReporter::testRunEnded( TestRunStats const& _testRunStats ) {\r\n            printTotals( stream, _testRunStats.totals );\r\n            stream << '\\n' << std::endl;\r\n            StreamingReporterBase::testRunEnded( _testRunStats );\r\n        }\r\n\r\n        CompactReporter::~CompactReporter() {}\r\n\r\n    CATCH_REGISTER_REPORTER( \"compact\", CompactReporter )\r\n\r\n} // end namespace Catch\r\n// end catch_reporter_compact.cpp\r\n// start catch_reporter_console.cpp\r\n\r\n#include <cfloat>\r\n#include <cstdio>\r\n\r\n#if defined(_MSC_VER)\r\n#pragma warning(push)\r\n#pragma warning(disable:4061) // Not all labels are EXPLICITLY handled in switch\r\n // Note that 4062 (not all labels are handled\r\n // and default is missing) is enabled\r\n#endif\r\n\r\nnamespace Catch {\r\n\r\nnamespace {\r\n\r\n// Formatter impl for ConsoleReporter\r\nclass ConsoleAssertionPrinter {\r\npublic:\r\n    ConsoleAssertionPrinter& operator= (ConsoleAssertionPrinter const&) = delete;\r\n    ConsoleAssertionPrinter(ConsoleAssertionPrinter const&) = delete;\r\n    ConsoleAssertionPrinter(std::ostream& _stream, AssertionStats const& _stats, bool _printInfoMessages)\r\n        : stream(_stream),\r\n        stats(_stats),\r\n        result(_stats.assertionResult),\r\n        colour(Colour::None),\r\n        message(result.getMessage()),\r\n        messages(_stats.infoMessages),\r\n        printInfoMessages(_printInfoMessages) {\r\n        switch (result.getResultType()) {\r\n        case ResultWas::Ok:\r\n            colour = Colour::Success;\r\n            passOrFail = \"PASSED\";\r\n            //if( result.hasMessage() )\r\n            if (_stats.infoMessages.size() == 1)\r\n                messageLabel = \"with message\";\r\n            if (_stats.infoMessages.size() > 1)\r\n                messageLabel = \"with messages\";\r\n            break;\r\n        case ResultWas::ExpressionFailed:\r\n            if (result.isOk()) {\r\n                colour = Colour::Success;\r\n                passOrFail = \"FAILED - but was ok\";\r\n            } else {\r\n                colour = Colour::Error;\r\n                passOrFail = \"FAILED\";\r\n            }\r\n            if (_stats.infoMessages.size() == 1)\r\n                messageLabel = \"with message\";\r\n            if (_stats.infoMessages.size() > 1)\r\n                messageLabel = \"with messages\";\r\n            break;\r\n        case ResultWas::ThrewException:\r\n            colour = Colour::Error;\r\n            passOrFail = \"FAILED\";\r\n            messageLabel = \"due to unexpected exception with \";\r\n            if (_stats.infoMessages.size() == 1)\r\n                messageLabel += \"message\";\r\n            if (_stats.infoMessages.size() > 1)\r\n                messageLabel += \"messages\";\r\n            break;\r\n        case ResultWas::FatalErrorCondition:\r\n            colour = Colour::Error;\r\n            passOrFail = \"FAILED\";\r\n            messageLabel = \"due to a fatal error condition\";\r\n            break;\r\n        case ResultWas::DidntThrowException:\r\n            colour = Colour::Error;\r\n            passOrFail = \"FAILED\";\r\n            messageLabel = \"because no exception was thrown where one was expected\";\r\n            break;\r\n        case ResultWas::Info:\r\n            messageLabel = \"info\";\r\n            break;\r\n        case ResultWas::Warning:\r\n            messageLabel = \"warning\";\r\n            break;\r\n        case ResultWas::ExplicitFailure:\r\n            passOrFail = \"FAILED\";\r\n            colour = Colour::Error;\r\n            if (_stats.infoMessages.size() == 1)\r\n                messageLabel = \"explicitly with message\";\r\n            if (_stats.infoMessages.size() > 1)\r\n                messageLabel = \"explicitly with messages\";\r\n            break;\r\n            // These cases are here to prevent compiler warnings\r\n        case ResultWas::Unknown:\r\n        case ResultWas::FailureBit:\r\n        case ResultWas::Exception:\r\n            passOrFail = \"** internal error **\";\r\n            colour = Colour::Error;\r\n            break;\r\n        }\r\n    }\r\n\r\n    void print() const {\r\n        printSourceInfo();\r\n        if (stats.totals.assertions.total() > 0) {\r\n            printResultType();\r\n            printOriginalExpression();\r\n            printReconstructedExpression();\r\n        } else {\r\n            stream << '\\n';\r\n        }\r\n        printMessage();\r\n    }\r\n\r\nprivate:\r\n    void printResultType() const {\r\n        if (!passOrFail.empty()) {\r\n            Colour colourGuard(colour);\r\n            stream << passOrFail << \":\\n\";\r\n        }\r\n    }\r\n    void printOriginalExpression() const {\r\n        if (result.hasExpression()) {\r\n            Colour colourGuard(Colour::OriginalExpression);\r\n            stream << \"  \";\r\n            stream << result.getExpressionInMacro();\r\n            stream << '\\n';\r\n        }\r\n    }\r\n    void printReconstructedExpression() const {\r\n        if (result.hasExpandedExpression()) {\r\n            stream << \"with expansion:\\n\";\r\n            Colour colourGuard(Colour::ReconstructedExpression);\r\n            stream << Column(result.getExpandedExpression()).indent(2) << '\\n';\r\n        }\r\n    }\r\n    void printMessage() const {\r\n        if (!messageLabel.empty())\r\n            stream << messageLabel << ':' << '\\n';\r\n        for (auto const& msg : messages) {\r\n            // If this assertion is a warning ignore any INFO messages\r\n            if (printInfoMessages || msg.type != ResultWas::Info)\r\n                stream << Column(msg.message).indent(2) << '\\n';\r\n        }\r\n    }\r\n    void printSourceInfo() const {\r\n        Colour colourGuard(Colour::FileName);\r\n        stream << result.getSourceInfo() << \": \";\r\n    }\r\n\r\n    std::ostream& stream;\r\n    AssertionStats const& stats;\r\n    AssertionResult const& result;\r\n    Colour::Code colour;\r\n    std::string passOrFail;\r\n    std::string messageLabel;\r\n    std::string message;\r\n    std::vector<MessageInfo> messages;\r\n    bool printInfoMessages;\r\n};\r\n\r\nstd::size_t makeRatio(std::size_t number, std::size_t total) {\r\n    std::size_t ratio = total > 0 ? CATCH_CONFIG_CONSOLE_WIDTH * number / total : 0;\r\n    return (ratio == 0 && number > 0) ? 1 : ratio;\r\n}\r\n\r\nstd::size_t& findMax(std::size_t& i, std::size_t& j, std::size_t& k) {\r\n    if (i > j && i > k)\r\n        return i;\r\n    else if (j > k)\r\n        return j;\r\n    else\r\n        return k;\r\n}\r\n\r\nstruct ColumnInfo {\r\n    enum Justification { Left, Right };\r\n    std::string name;\r\n    int width;\r\n    Justification justification;\r\n};\r\nstruct ColumnBreak {};\r\nstruct RowBreak {};\r\n\r\nclass Duration {\r\n    enum class Unit {\r\n        Auto,\r\n        Nanoseconds,\r\n        Microseconds,\r\n        Milliseconds,\r\n        Seconds,\r\n        Minutes\r\n    };\r\n    static const uint64_t s_nanosecondsInAMicrosecond = 1000;\r\n    static const uint64_t s_nanosecondsInAMillisecond = 1000 * s_nanosecondsInAMicrosecond;\r\n    static const uint64_t s_nanosecondsInASecond = 1000 * s_nanosecondsInAMillisecond;\r\n    static const uint64_t s_nanosecondsInAMinute = 60 * s_nanosecondsInASecond;\r\n\r\n    uint64_t m_inNanoseconds;\r\n    Unit m_units;\r\n\r\npublic:\r\n    explicit Duration(uint64_t inNanoseconds, Unit units = Unit::Auto)\r\n        : m_inNanoseconds(inNanoseconds),\r\n        m_units(units) {\r\n        if (m_units == Unit::Auto) {\r\n            if (m_inNanoseconds < s_nanosecondsInAMicrosecond)\r\n                m_units = Unit::Nanoseconds;\r\n            else if (m_inNanoseconds < s_nanosecondsInAMillisecond)\r\n                m_units = Unit::Microseconds;\r\n            else if (m_inNanoseconds < s_nanosecondsInASecond)\r\n                m_units = Unit::Milliseconds;\r\n            else if (m_inNanoseconds < s_nanosecondsInAMinute)\r\n                m_units = Unit::Seconds;\r\n            else\r\n                m_units = Unit::Minutes;\r\n        }\r\n\r\n    }\r\n\r\n    auto value() const -> double {\r\n        switch (m_units) {\r\n        case Unit::Microseconds:\r\n            return m_inNanoseconds / static_cast<double>(s_nanosecondsInAMicrosecond);\r\n        case Unit::Milliseconds:\r\n            return m_inNanoseconds / static_cast<double>(s_nanosecondsInAMillisecond);\r\n        case Unit::Seconds:\r\n            return m_inNanoseconds / static_cast<double>(s_nanosecondsInASecond);\r\n        case Unit::Minutes:\r\n            return m_inNanoseconds / static_cast<double>(s_nanosecondsInAMinute);\r\n        default:\r\n            return static_cast<double>(m_inNanoseconds);\r\n        }\r\n    }\r\n    auto unitsAsString() const -> std::string {\r\n        switch (m_units) {\r\n        case Unit::Nanoseconds:\r\n            return \"ns\";\r\n        case Unit::Microseconds:\r\n            return \"us\";\r\n        case Unit::Milliseconds:\r\n            return \"ms\";\r\n        case Unit::Seconds:\r\n            return \"s\";\r\n        case Unit::Minutes:\r\n            return \"m\";\r\n        default:\r\n            return \"** internal error **\";\r\n        }\r\n\r\n    }\r\n    friend auto operator << (std::ostream& os, Duration const& duration) -> std::ostream& {\r\n        return os << duration.value() << \" \" << duration.unitsAsString();\r\n    }\r\n};\r\n} // end anon namespace\r\n\r\nclass TablePrinter {\r\n    std::ostream& m_os;\r\n    std::vector<ColumnInfo> m_columnInfos;\r\n    std::ostringstream m_oss;\r\n    int m_currentColumn = -1;\r\n    bool m_isOpen = false;\r\n\r\npublic:\r\n    TablePrinter( std::ostream& os, std::vector<ColumnInfo> columnInfos )\r\n    :   m_os( os ),\r\n        m_columnInfos( std::move( columnInfos ) ) {}\r\n\r\n    auto columnInfos() const -> std::vector<ColumnInfo> const& {\r\n        return m_columnInfos;\r\n    }\r\n\r\n    void open() {\r\n        if (!m_isOpen) {\r\n            m_isOpen = true;\r\n            *this << RowBreak();\r\n            for (auto const& info : m_columnInfos)\r\n                *this << info.name << ColumnBreak();\r\n            *this << RowBreak();\r\n            m_os << Catch::getLineOfChars<'-'>() << \"\\n\";\r\n        }\r\n    }\r\n    void close() {\r\n        if (m_isOpen) {\r\n            *this << RowBreak();\r\n            m_os << std::endl;\r\n            m_isOpen = false;\r\n        }\r\n    }\r\n\r\n    template<typename T>\r\n    friend TablePrinter& operator << (TablePrinter& tp, T const& value) {\r\n        tp.m_oss << value;\r\n        return tp;\r\n    }\r\n\r\n    friend TablePrinter& operator << (TablePrinter& tp, ColumnBreak) {\r\n        auto colStr = tp.m_oss.str();\r\n        // This takes account of utf8 encodings\r\n        auto strSize = Catch::StringRef(colStr).numberOfCharacters();\r\n        tp.m_oss.str(\"\");\r\n        tp.open();\r\n        if (tp.m_currentColumn == static_cast<int>(tp.m_columnInfos.size() - 1)) {\r\n            tp.m_currentColumn = -1;\r\n            tp.m_os << \"\\n\";\r\n        }\r\n        tp.m_currentColumn++;\r\n\r\n        auto colInfo = tp.m_columnInfos[tp.m_currentColumn];\r\n        auto padding = (strSize + 2 < static_cast<std::size_t>(colInfo.width))\r\n            ? std::string(colInfo.width - (strSize + 2), ' ')\r\n            : std::string();\r\n        if (colInfo.justification == ColumnInfo::Left)\r\n            tp.m_os << colStr << padding << \" \";\r\n        else\r\n            tp.m_os << padding << colStr << \" \";\r\n        return tp;\r\n    }\r\n\r\n    friend TablePrinter& operator << (TablePrinter& tp, RowBreak) {\r\n        if (tp.m_currentColumn > 0) {\r\n            tp.m_os << \"\\n\";\r\n            tp.m_currentColumn = -1;\r\n        }\r\n        return tp;\r\n    }\r\n};\r\n\r\nConsoleReporter::ConsoleReporter(ReporterConfig const& config)\r\n    : StreamingReporterBase(config),\r\n    m_tablePrinter(new TablePrinter(config.stream(),\r\n    {\r\n        { \"benchmark name\", CATCH_CONFIG_CONSOLE_WIDTH - 32, ColumnInfo::Left },\r\n        { \"iters\", 8, ColumnInfo::Right },\r\n        { \"elapsed ns\", 14, ColumnInfo::Right },\r\n        { \"average\", 14, ColumnInfo::Right }\r\n    })) {}\r\nConsoleReporter::~ConsoleReporter() = default;\r\n\r\nstd::string ConsoleReporter::getDescription() {\r\n    return \"Reports test results as plain lines of text\";\r\n}\r\n\r\nvoid ConsoleReporter::noMatchingTestCases(std::string const& spec) {\r\n    stream << \"No test cases matched '\" << spec << '\\'' << std::endl;\r\n}\r\n\r\nvoid ConsoleReporter::assertionStarting(AssertionInfo const&) {}\r\n\r\nbool ConsoleReporter::assertionEnded(AssertionStats const& _assertionStats) {\r\n    AssertionResult const& result = _assertionStats.assertionResult;\r\n\r\n    bool includeResults = m_config->includeSuccessfulResults() || !result.isOk();\r\n\r\n    // Drop out if result was successful but we're not printing them.\r\n    if (!includeResults && result.getResultType() != ResultWas::Warning)\r\n        return false;\r\n\r\n    lazyPrint();\r\n\r\n    ConsoleAssertionPrinter printer(stream, _assertionStats, includeResults);\r\n    printer.print();\r\n    stream << std::endl;\r\n    return true;\r\n}\r\n\r\nvoid ConsoleReporter::sectionStarting(SectionInfo const& _sectionInfo) {\r\n    m_headerPrinted = false;\r\n    StreamingReporterBase::sectionStarting(_sectionInfo);\r\n}\r\nvoid ConsoleReporter::sectionEnded(SectionStats const& _sectionStats) {\r\n    m_tablePrinter->close();\r\n    if (_sectionStats.missingAssertions) {\r\n        lazyPrint();\r\n        Colour colour(Colour::ResultError);\r\n        if (m_sectionStack.size() > 1)\r\n            stream << \"\\nNo assertions in section\";\r\n        else\r\n            stream << \"\\nNo assertions in test case\";\r\n        stream << \" '\" << _sectionStats.sectionInfo.name << \"'\\n\" << std::endl;\r\n    }\r\n    if (m_config->showDurations() == ShowDurations::Always) {\r\n        stream << getFormattedDuration(_sectionStats.durationInSeconds) << \" s: \" << _sectionStats.sectionInfo.name << std::endl;\r\n    }\r\n    if (m_headerPrinted) {\r\n        m_headerPrinted = false;\r\n    }\r\n    StreamingReporterBase::sectionEnded(_sectionStats);\r\n}\r\n\r\nvoid ConsoleReporter::benchmarkStarting(BenchmarkInfo const& info) {\r\n    lazyPrintWithoutClosingBenchmarkTable();\r\n\r\n    auto nameCol = Column( info.name ).width( static_cast<std::size_t>( m_tablePrinter->columnInfos()[0].width - 2 ) );\r\n\r\n    bool firstLine = true;\r\n    for (auto line : nameCol) {\r\n        if (!firstLine)\r\n            (*m_tablePrinter) << ColumnBreak() << ColumnBreak() << ColumnBreak();\r\n        else\r\n            firstLine = false;\r\n\r\n        (*m_tablePrinter) << line << ColumnBreak();\r\n    }\r\n}\r\nvoid ConsoleReporter::benchmarkEnded(BenchmarkStats const& stats) {\r\n    Duration average(stats.elapsedTimeInNanoseconds / stats.iterations);\r\n    (*m_tablePrinter)\r\n        << stats.iterations << ColumnBreak()\r\n        << stats.elapsedTimeInNanoseconds << ColumnBreak()\r\n        << average << ColumnBreak();\r\n}\r\n\r\nvoid ConsoleReporter::testCaseEnded(TestCaseStats const& _testCaseStats) {\r\n    m_tablePrinter->close();\r\n    StreamingReporterBase::testCaseEnded(_testCaseStats);\r\n    m_headerPrinted = false;\r\n}\r\nvoid ConsoleReporter::testGroupEnded(TestGroupStats const& _testGroupStats) {\r\n    if (currentGroupInfo.used) {\r\n        printSummaryDivider();\r\n        stream << \"Summary for group '\" << _testGroupStats.groupInfo.name << \"':\\n\";\r\n        printTotals(_testGroupStats.totals);\r\n        stream << '\\n' << std::endl;\r\n    }\r\n    StreamingReporterBase::testGroupEnded(_testGroupStats);\r\n}\r\nvoid ConsoleReporter::testRunEnded(TestRunStats const& _testRunStats) {\r\n    printTotalsDivider(_testRunStats.totals);\r\n    printTotals(_testRunStats.totals);\r\n    stream << std::endl;\r\n    StreamingReporterBase::testRunEnded(_testRunStats);\r\n}\r\n\r\nvoid ConsoleReporter::lazyPrint() {\r\n\r\n    m_tablePrinter->close();\r\n    lazyPrintWithoutClosingBenchmarkTable();\r\n}\r\n\r\nvoid ConsoleReporter::lazyPrintWithoutClosingBenchmarkTable() {\r\n\r\n    if (!currentTestRunInfo.used)\r\n        lazyPrintRunInfo();\r\n    if (!currentGroupInfo.used)\r\n        lazyPrintGroupInfo();\r\n\r\n    if (!m_headerPrinted) {\r\n        printTestCaseAndSectionHeader();\r\n        m_headerPrinted = true;\r\n    }\r\n}\r\nvoid ConsoleReporter::lazyPrintRunInfo() {\r\n    stream << '\\n' << getLineOfChars<'~'>() << '\\n';\r\n    Colour colour(Colour::SecondaryText);\r\n    stream << currentTestRunInfo->name\r\n        << \" is a Catch v\" << libraryVersion() << \" host application.\\n\"\r\n        << \"Run with -? for options\\n\\n\";\r\n\r\n    if (m_config->rngSeed() != 0)\r\n        stream << \"Randomness seeded to: \" << m_config->rngSeed() << \"\\n\\n\";\r\n\r\n    currentTestRunInfo.used = true;\r\n}\r\nvoid ConsoleReporter::lazyPrintGroupInfo() {\r\n    if (!currentGroupInfo->name.empty() && currentGroupInfo->groupsCounts > 1) {\r\n        printClosedHeader(\"Group: \" + currentGroupInfo->name);\r\n        currentGroupInfo.used = true;\r\n    }\r\n}\r\nvoid ConsoleReporter::printTestCaseAndSectionHeader() {\r\n    assert(!m_sectionStack.empty());\r\n    printOpenHeader(currentTestCaseInfo->name);\r\n\r\n    if (m_sectionStack.size() > 1) {\r\n        Colour colourGuard(Colour::Headers);\r\n\r\n        auto\r\n            it = m_sectionStack.begin() + 1, // Skip first section (test case)\r\n            itEnd = m_sectionStack.end();\r\n        for (; it != itEnd; ++it)\r\n            printHeaderString(it->name, 2);\r\n    }\r\n\r\n    SourceLineInfo lineInfo = m_sectionStack.back().lineInfo;\r\n\r\n    if (!lineInfo.empty()) {\r\n        stream << getLineOfChars<'-'>() << '\\n';\r\n        Colour colourGuard(Colour::FileName);\r\n        stream << lineInfo << '\\n';\r\n    }\r\n    stream << getLineOfChars<'.'>() << '\\n' << std::endl;\r\n}\r\n\r\nvoid ConsoleReporter::printClosedHeader(std::string const& _name) {\r\n    printOpenHeader(_name);\r\n    stream << getLineOfChars<'.'>() << '\\n';\r\n}\r\nvoid ConsoleReporter::printOpenHeader(std::string const& _name) {\r\n    stream << getLineOfChars<'-'>() << '\\n';\r\n    {\r\n        Colour colourGuard(Colour::Headers);\r\n        printHeaderString(_name);\r\n    }\r\n}\r\n\r\n// if string has a : in first line will set indent to follow it on\r\n// subsequent lines\r\nvoid ConsoleReporter::printHeaderString(std::string const& _string, std::size_t indent) {\r\n    std::size_t i = _string.find(\": \");\r\n    if (i != std::string::npos)\r\n        i += 2;\r\n    else\r\n        i = 0;\r\n    stream << Column(_string).indent(indent + i).initialIndent(indent) << '\\n';\r\n}\r\n\r\nstruct SummaryColumn {\r\n\r\n    SummaryColumn( std::string _label, Colour::Code _colour )\r\n    :   label( std::move( _label ) ),\r\n        colour( _colour ) {}\r\n    SummaryColumn addRow( std::size_t count ) {\r\n        ReusableStringStream rss;\r\n        rss << count;\r\n        std::string row = rss.str();\r\n        for (auto& oldRow : rows) {\r\n            while (oldRow.size() < row.size())\r\n                oldRow = ' ' + oldRow;\r\n            while (oldRow.size() > row.size())\r\n                row = ' ' + row;\r\n        }\r\n        rows.push_back(row);\r\n        return *this;\r\n    }\r\n\r\n    std::string label;\r\n    Colour::Code colour;\r\n    std::vector<std::string> rows;\r\n\r\n};\r\n\r\nvoid ConsoleReporter::printTotals( Totals const& totals ) {\r\n    if (totals.testCases.total() == 0) {\r\n        stream << Colour(Colour::Warning) << \"No tests ran\\n\";\r\n    } else if (totals.assertions.total() > 0 && totals.testCases.allPassed()) {\r\n        stream << Colour(Colour::ResultSuccess) << \"All tests passed\";\r\n        stream << \" (\"\r\n            << pluralise(totals.assertions.passed, \"assertion\") << \" in \"\r\n            << pluralise(totals.testCases.passed, \"test case\") << ')'\r\n            << '\\n';\r\n    } else {\r\n\r\n        std::vector<SummaryColumn> columns;\r\n        columns.push_back(SummaryColumn(\"\", Colour::None)\r\n                          .addRow(totals.testCases.total())\r\n                          .addRow(totals.assertions.total()));\r\n        columns.push_back(SummaryColumn(\"passed\", Colour::Success)\r\n                          .addRow(totals.testCases.passed)\r\n                          .addRow(totals.assertions.passed));\r\n        columns.push_back(SummaryColumn(\"failed\", Colour::ResultError)\r\n                          .addRow(totals.testCases.failed)\r\n                          .addRow(totals.assertions.failed));\r\n        columns.push_back(SummaryColumn(\"failed as expected\", Colour::ResultExpectedFailure)\r\n                          .addRow(totals.testCases.failedButOk)\r\n                          .addRow(totals.assertions.failedButOk));\r\n\r\n        printSummaryRow(\"test cases\", columns, 0);\r\n        printSummaryRow(\"assertions\", columns, 1);\r\n    }\r\n}\r\nvoid ConsoleReporter::printSummaryRow(std::string const& label, std::vector<SummaryColumn> const& cols, std::size_t row) {\r\n    for (auto col : cols) {\r\n        std::string value = col.rows[row];\r\n        if (col.label.empty()) {\r\n            stream << label << \": \";\r\n            if (value != \"0\")\r\n                stream << value;\r\n            else\r\n                stream << Colour(Colour::Warning) << \"- none -\";\r\n        } else if (value != \"0\") {\r\n            stream << Colour(Colour::LightGrey) << \" | \";\r\n            stream << Colour(col.colour)\r\n                << value << ' ' << col.label;\r\n        }\r\n    }\r\n    stream << '\\n';\r\n}\r\n\r\nvoid ConsoleReporter::printTotalsDivider(Totals const& totals) {\r\n    if (totals.testCases.total() > 0) {\r\n        std::size_t failedRatio = makeRatio(totals.testCases.failed, totals.testCases.total());\r\n        std::size_t failedButOkRatio = makeRatio(totals.testCases.failedButOk, totals.testCases.total());\r\n        std::size_t passedRatio = makeRatio(totals.testCases.passed, totals.testCases.total());\r\n        while (failedRatio + failedButOkRatio + passedRatio < CATCH_CONFIG_CONSOLE_WIDTH - 1)\r\n            findMax(failedRatio, failedButOkRatio, passedRatio)++;\r\n        while (failedRatio + failedButOkRatio + passedRatio > CATCH_CONFIG_CONSOLE_WIDTH - 1)\r\n            findMax(failedRatio, failedButOkRatio, passedRatio)--;\r\n\r\n        stream << Colour(Colour::Error) << std::string(failedRatio, '=');\r\n        stream << Colour(Colour::ResultExpectedFailure) << std::string(failedButOkRatio, '=');\r\n        if (totals.testCases.allPassed())\r\n            stream << Colour(Colour::ResultSuccess) << std::string(passedRatio, '=');\r\n        else\r\n            stream << Colour(Colour::Success) << std::string(passedRatio, '=');\r\n    } else {\r\n        stream << Colour(Colour::Warning) << std::string(CATCH_CONFIG_CONSOLE_WIDTH - 1, '=');\r\n    }\r\n    stream << '\\n';\r\n}\r\nvoid ConsoleReporter::printSummaryDivider() {\r\n    stream << getLineOfChars<'-'>() << '\\n';\r\n}\r\n\r\nCATCH_REGISTER_REPORTER(\"console\", ConsoleReporter)\r\n\r\n} // end namespace Catch\r\n\r\n#if defined(_MSC_VER)\r\n#pragma warning(pop)\r\n#endif\r\n// end catch_reporter_console.cpp\r\n// start catch_reporter_junit.cpp\r\n\r\n#include <cassert>\r\n#include <sstream>\r\n#include <ctime>\r\n#include <algorithm>\r\n\r\nnamespace Catch {\r\n\r\n    namespace {\r\n        std::string getCurrentTimestamp() {\r\n            // Beware, this is not reentrant because of backward compatibility issues\r\n            // Also, UTC only, again because of backward compatibility (%z is C++11)\r\n            time_t rawtime;\r\n            std::time(&rawtime);\r\n            auto const timeStampSize = sizeof(\"2017-01-16T17:06:45Z\");\r\n\r\n#ifdef _MSC_VER\r\n            std::tm timeInfo = {};\r\n            gmtime_s(&timeInfo, &rawtime);\r\n#else\r\n            std::tm* timeInfo;\r\n            timeInfo = std::gmtime(&rawtime);\r\n#endif\r\n\r\n            char timeStamp[timeStampSize];\r\n            const char * const fmt = \"%Y-%m-%dT%H:%M:%SZ\";\r\n\r\n#ifdef _MSC_VER\r\n            std::strftime(timeStamp, timeStampSize, fmt, &timeInfo);\r\n#else\r\n            std::strftime(timeStamp, timeStampSize, fmt, timeInfo);\r\n#endif\r\n            return std::string(timeStamp);\r\n        }\r\n\r\n        std::string fileNameTag(const std::vector<std::string> &tags) {\r\n            auto it = std::find_if(begin(tags),\r\n                                   end(tags),\r\n                                   [] (std::string const& tag) {return tag.front() == '#'; });\r\n            if (it != tags.end())\r\n                return it->substr(1);\r\n            return std::string();\r\n        }\r\n    } // anonymous namespace\r\n\r\n    JunitReporter::JunitReporter( ReporterConfig const& _config )\r\n        :   CumulativeReporterBase( _config ),\r\n            xml( _config.stream() )\r\n        {\r\n            m_reporterPrefs.shouldRedirectStdOut = true;\r\n            m_reporterPrefs.shouldReportAllAssertions = true;\r\n        }\r\n\r\n    JunitReporter::~JunitReporter() {}\r\n\r\n    std::string JunitReporter::getDescription() {\r\n        return \"Reports test results in an XML format that looks like Ant's junitreport target\";\r\n    }\r\n\r\n    void JunitReporter::noMatchingTestCases( std::string const& /*spec*/ ) {}\r\n\r\n    void JunitReporter::testRunStarting( TestRunInfo const& runInfo )  {\r\n        CumulativeReporterBase::testRunStarting( runInfo );\r\n        xml.startElement( \"testsuites\" );\r\n        if( m_config->rngSeed() != 0 ) {\r\n            xml.startElement( \"properties\" );\r\n            xml.scopedElement( \"property\" )\r\n                .writeAttribute( \"name\", \"random-seed\" )\r\n                .writeAttribute( \"value\", m_config->rngSeed() );\r\n            xml.endElement();\r\n        }\r\n    }\r\n\r\n    void JunitReporter::testGroupStarting( GroupInfo const& groupInfo ) {\r\n        suiteTimer.start();\r\n        stdOutForSuite.clear();\r\n        stdErrForSuite.clear();\r\n        unexpectedExceptions = 0;\r\n        CumulativeReporterBase::testGroupStarting( groupInfo );\r\n    }\r\n\r\n    void JunitReporter::testCaseStarting( TestCaseInfo const& testCaseInfo ) {\r\n        m_okToFail = testCaseInfo.okToFail();\r\n    }\r\n\r\n    bool JunitReporter::assertionEnded( AssertionStats const& assertionStats ) {\r\n        if( assertionStats.assertionResult.getResultType() == ResultWas::ThrewException && !m_okToFail )\r\n            unexpectedExceptions++;\r\n        return CumulativeReporterBase::assertionEnded( assertionStats );\r\n    }\r\n\r\n    void JunitReporter::testCaseEnded( TestCaseStats const& testCaseStats ) {\r\n        stdOutForSuite += testCaseStats.stdOut;\r\n        stdErrForSuite += testCaseStats.stdErr;\r\n        CumulativeReporterBase::testCaseEnded( testCaseStats );\r\n    }\r\n\r\n    void JunitReporter::testGroupEnded( TestGroupStats const& testGroupStats ) {\r\n        double suiteTime = suiteTimer.getElapsedSeconds();\r\n        CumulativeReporterBase::testGroupEnded( testGroupStats );\r\n        writeGroup( *m_testGroups.back(), suiteTime );\r\n    }\r\n\r\n    void JunitReporter::testRunEndedCumulative() {\r\n        xml.endElement();\r\n    }\r\n\r\n    void JunitReporter::writeGroup( TestGroupNode const& groupNode, double suiteTime ) {\r\n        XmlWriter::ScopedElement e = xml.scopedElement( \"testsuite\" );\r\n        TestGroupStats const& stats = groupNode.value;\r\n        xml.writeAttribute( \"name\", stats.groupInfo.name );\r\n        xml.writeAttribute( \"errors\", unexpectedExceptions );\r\n        xml.writeAttribute( \"failures\", stats.totals.assertions.failed-unexpectedExceptions );\r\n        xml.writeAttribute( \"tests\", stats.totals.assertions.total() );\r\n        xml.writeAttribute( \"hostname\", \"tbd\" ); // !TBD\r\n        if( m_config->showDurations() == ShowDurations::Never )\r\n            xml.writeAttribute( \"time\", \"\" );\r\n        else\r\n            xml.writeAttribute( \"time\", suiteTime );\r\n        xml.writeAttribute( \"timestamp\", getCurrentTimestamp() );\r\n\r\n        // Write test cases\r\n        for( auto const& child : groupNode.children )\r\n            writeTestCase( *child );\r\n\r\n        xml.scopedElement( \"system-out\" ).writeText( trim( stdOutForSuite ), false );\r\n        xml.scopedElement( \"system-err\" ).writeText( trim( stdErrForSuite ), false );\r\n    }\r\n\r\n    void JunitReporter::writeTestCase( TestCaseNode const& testCaseNode ) {\r\n        TestCaseStats const& stats = testCaseNode.value;\r\n\r\n        // All test cases have exactly one section - which represents the\r\n        // test case itself. That section may have 0-n nested sections\r\n        assert( testCaseNode.children.size() == 1 );\r\n        SectionNode const& rootSection = *testCaseNode.children.front();\r\n\r\n        std::string className = stats.testInfo.className;\r\n\r\n        if( className.empty() ) {\r\n            className = fileNameTag(stats.testInfo.tags);\r\n            if ( className.empty() )\r\n                className = \"global\";\r\n        }\r\n\r\n        if ( !m_config->name().empty() )\r\n            className = m_config->name() + \".\" + className;\r\n\r\n        writeSection( className, \"\", rootSection );\r\n    }\r\n\r\n    void JunitReporter::writeSection(  std::string const& className,\r\n                        std::string const& rootName,\r\n                        SectionNode const& sectionNode ) {\r\n        std::string name = trim( sectionNode.stats.sectionInfo.name );\r\n        if( !rootName.empty() )\r\n            name = rootName + '/' + name;\r\n\r\n        if( !sectionNode.assertions.empty() ||\r\n            !sectionNode.stdOut.empty() ||\r\n            !sectionNode.stdErr.empty() ) {\r\n            XmlWriter::ScopedElement e = xml.scopedElement( \"testcase\" );\r\n            if( className.empty() ) {\r\n                xml.writeAttribute( \"classname\", name );\r\n                xml.writeAttribute( \"name\", \"root\" );\r\n            }\r\n            else {\r\n                xml.writeAttribute( \"classname\", className );\r\n                xml.writeAttribute( \"name\", name );\r\n            }\r\n            xml.writeAttribute( \"time\", ::Catch::Detail::stringify( sectionNode.stats.durationInSeconds ) );\r\n\r\n            writeAssertions( sectionNode );\r\n\r\n            if( !sectionNode.stdOut.empty() )\r\n                xml.scopedElement( \"system-out\" ).writeText( trim( sectionNode.stdOut ), false );\r\n            if( !sectionNode.stdErr.empty() )\r\n                xml.scopedElement( \"system-err\" ).writeText( trim( sectionNode.stdErr ), false );\r\n        }\r\n        for( auto const& childNode : sectionNode.childSections )\r\n            if( className.empty() )\r\n                writeSection( name, \"\", *childNode );\r\n            else\r\n                writeSection( className, name, *childNode );\r\n    }\r\n\r\n    void JunitReporter::writeAssertions( SectionNode const& sectionNode ) {\r\n        for( auto const& assertion : sectionNode.assertions )\r\n            writeAssertion( assertion );\r\n    }\r\n\r\n    void JunitReporter::writeAssertion( AssertionStats const& stats ) {\r\n        AssertionResult const& result = stats.assertionResult;\r\n        if( !result.isOk() ) {\r\n            std::string elementName;\r\n            switch( result.getResultType() ) {\r\n                case ResultWas::ThrewException:\r\n                case ResultWas::FatalErrorCondition:\r\n                    elementName = \"error\";\r\n                    break;\r\n                case ResultWas::ExplicitFailure:\r\n                    elementName = \"failure\";\r\n                    break;\r\n                case ResultWas::ExpressionFailed:\r\n                    elementName = \"failure\";\r\n                    break;\r\n                case ResultWas::DidntThrowException:\r\n                    elementName = \"failure\";\r\n                    break;\r\n\r\n                // We should never see these here:\r\n                case ResultWas::Info:\r\n                case ResultWas::Warning:\r\n                case ResultWas::Ok:\r\n                case ResultWas::Unknown:\r\n                case ResultWas::FailureBit:\r\n                case ResultWas::Exception:\r\n                    elementName = \"internalError\";\r\n                    break;\r\n            }\r\n\r\n            XmlWriter::ScopedElement e = xml.scopedElement( elementName );\r\n\r\n            xml.writeAttribute( \"message\", result.getExpandedExpression() );\r\n            xml.writeAttribute( \"type\", result.getTestMacroName() );\r\n\r\n            ReusableStringStream rss;\r\n            if( !result.getMessage().empty() )\r\n                rss << result.getMessage() << '\\n';\r\n            for( auto const& msg : stats.infoMessages )\r\n                if( msg.type == ResultWas::Info )\r\n                    rss << msg.message << '\\n';\r\n\r\n            rss << \"at \" << result.getSourceInfo();\r\n            xml.writeText( rss.str(), false );\r\n        }\r\n    }\r\n\r\n    CATCH_REGISTER_REPORTER( \"junit\", JunitReporter )\r\n\r\n} // end namespace Catch\r\n// end catch_reporter_junit.cpp\r\n// start catch_reporter_listening.cpp\r\n\r\n#include <cassert>\r\n\r\nnamespace Catch {\r\n\r\n    ListeningReporter::ListeningReporter() {\r\n        // We will assume that listeners will always want all assertions\r\n        m_preferences.shouldReportAllAssertions = true;\r\n    }\r\n\r\n    void ListeningReporter::addListener( IStreamingReporterPtr&& listener ) {\r\n        m_listeners.push_back( std::move( listener ) );\r\n    }\r\n\r\n    void ListeningReporter::addReporter(IStreamingReporterPtr&& reporter) {\r\n        assert(!m_reporter && \"Listening reporter can wrap only 1 real reporter\");\r\n        m_reporter = std::move( reporter );\r\n        m_preferences.shouldRedirectStdOut = m_reporter->getPreferences().shouldRedirectStdOut;\r\n    }\r\n\r\n    ReporterPreferences ListeningReporter::getPreferences() const {\r\n        return m_preferences;\r\n    }\r\n\r\n    std::set<Verbosity> ListeningReporter::getSupportedVerbosities() {\r\n        return std::set<Verbosity>{ };\r\n    }\r\n\r\n    void ListeningReporter::noMatchingTestCases( std::string const& spec ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->noMatchingTestCases( spec );\r\n        }\r\n        m_reporter->noMatchingTestCases( spec );\r\n    }\r\n\r\n    void ListeningReporter::benchmarkStarting( BenchmarkInfo const& benchmarkInfo ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->benchmarkStarting( benchmarkInfo );\r\n        }\r\n        m_reporter->benchmarkStarting( benchmarkInfo );\r\n    }\r\n    void ListeningReporter::benchmarkEnded( BenchmarkStats const& benchmarkStats ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->benchmarkEnded( benchmarkStats );\r\n        }\r\n        m_reporter->benchmarkEnded( benchmarkStats );\r\n    }\r\n\r\n    void ListeningReporter::testRunStarting( TestRunInfo const& testRunInfo ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->testRunStarting( testRunInfo );\r\n        }\r\n        m_reporter->testRunStarting( testRunInfo );\r\n    }\r\n\r\n    void ListeningReporter::testGroupStarting( GroupInfo const& groupInfo ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->testGroupStarting( groupInfo );\r\n        }\r\n        m_reporter->testGroupStarting( groupInfo );\r\n    }\r\n\r\n    void ListeningReporter::testCaseStarting( TestCaseInfo const& testInfo ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->testCaseStarting( testInfo );\r\n        }\r\n        m_reporter->testCaseStarting( testInfo );\r\n    }\r\n\r\n    void ListeningReporter::sectionStarting( SectionInfo const& sectionInfo ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->sectionStarting( sectionInfo );\r\n        }\r\n        m_reporter->sectionStarting( sectionInfo );\r\n    }\r\n\r\n    void ListeningReporter::assertionStarting( AssertionInfo const& assertionInfo ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->assertionStarting( assertionInfo );\r\n        }\r\n        m_reporter->assertionStarting( assertionInfo );\r\n    }\r\n\r\n    // The return value indicates if the messages buffer should be cleared:\r\n    bool ListeningReporter::assertionEnded( AssertionStats const& assertionStats ) {\r\n        for( auto const& listener : m_listeners ) {\r\n            static_cast<void>( listener->assertionEnded( assertionStats ) );\r\n        }\r\n        return m_reporter->assertionEnded( assertionStats );\r\n    }\r\n\r\n    void ListeningReporter::sectionEnded( SectionStats const& sectionStats ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->sectionEnded( sectionStats );\r\n        }\r\n        m_reporter->sectionEnded( sectionStats );\r\n    }\r\n\r\n    void ListeningReporter::testCaseEnded( TestCaseStats const& testCaseStats ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->testCaseEnded( testCaseStats );\r\n        }\r\n        m_reporter->testCaseEnded( testCaseStats );\r\n    }\r\n\r\n    void ListeningReporter::testGroupEnded( TestGroupStats const& testGroupStats ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->testGroupEnded( testGroupStats );\r\n        }\r\n        m_reporter->testGroupEnded( testGroupStats );\r\n    }\r\n\r\n    void ListeningReporter::testRunEnded( TestRunStats const& testRunStats ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->testRunEnded( testRunStats );\r\n        }\r\n        m_reporter->testRunEnded( testRunStats );\r\n    }\r\n\r\n    void ListeningReporter::skipTest( TestCaseInfo const& testInfo ) {\r\n        for ( auto const& listener : m_listeners ) {\r\n            listener->skipTest( testInfo );\r\n        }\r\n        m_reporter->skipTest( testInfo );\r\n    }\r\n\r\n    bool ListeningReporter::isMulti() const {\r\n        return true;\r\n    }\r\n\r\n} // end namespace Catch\r\n// end catch_reporter_listening.cpp\r\n// start catch_reporter_xml.cpp\r\n\r\n#if defined(_MSC_VER)\r\n#pragma warning(push)\r\n#pragma warning(disable:4061) // Not all labels are EXPLICITLY handled in switch\r\n                              // Note that 4062 (not all labels are handled\r\n                              // and default is missing) is enabled\r\n#endif\r\n\r\nnamespace Catch {\r\n    XmlReporter::XmlReporter( ReporterConfig const& _config )\r\n    :   StreamingReporterBase( _config ),\r\n        m_xml(_config.stream())\r\n    {\r\n        m_reporterPrefs.shouldRedirectStdOut = true;\r\n        m_reporterPrefs.shouldReportAllAssertions = true;\r\n    }\r\n\r\n    XmlReporter::~XmlReporter() = default;\r\n\r\n    std::string XmlReporter::getDescription() {\r\n        return \"Reports test results as an XML document\";\r\n    }\r\n\r\n    std::string XmlReporter::getStylesheetRef() const {\r\n        return std::string();\r\n    }\r\n\r\n    void XmlReporter::writeSourceInfo( SourceLineInfo const& sourceInfo ) {\r\n        m_xml\r\n            .writeAttribute( \"filename\", sourceInfo.file )\r\n            .writeAttribute( \"line\", sourceInfo.line );\r\n    }\r\n\r\n    void XmlReporter::noMatchingTestCases( std::string const& s ) {\r\n        StreamingReporterBase::noMatchingTestCases( s );\r\n    }\r\n\r\n    void XmlReporter::testRunStarting( TestRunInfo const& testInfo ) {\r\n        StreamingReporterBase::testRunStarting( testInfo );\r\n        std::string stylesheetRef = getStylesheetRef();\r\n        if( !stylesheetRef.empty() )\r\n            m_xml.writeStylesheetRef( stylesheetRef );\r\n        m_xml.startElement( \"Catch\" );\r\n        if( !m_config->name().empty() )\r\n            m_xml.writeAttribute( \"name\", m_config->name() );\r\n        if( m_config->rngSeed() != 0 )\r\n            m_xml.scopedElement( \"Randomness\" )\r\n                .writeAttribute( \"seed\", m_config->rngSeed() );\r\n    }\r\n\r\n    void XmlReporter::testGroupStarting( GroupInfo const& groupInfo ) {\r\n        StreamingReporterBase::testGroupStarting( groupInfo );\r\n        m_xml.startElement( \"Group\" )\r\n            .writeAttribute( \"name\", groupInfo.name );\r\n    }\r\n\r\n    void XmlReporter::testCaseStarting( TestCaseInfo const& testInfo ) {\r\n        StreamingReporterBase::testCaseStarting(testInfo);\r\n        m_xml.startElement( \"TestCase\" )\r\n            .writeAttribute( \"name\", trim( testInfo.name ) )\r\n            .writeAttribute( \"description\", testInfo.description )\r\n            .writeAttribute( \"tags\", testInfo.tagsAsString() );\r\n\r\n        writeSourceInfo( testInfo.lineInfo );\r\n\r\n        if ( m_config->showDurations() == ShowDurations::Always )\r\n            m_testCaseTimer.start();\r\n        m_xml.ensureTagClosed();\r\n    }\r\n\r\n    void XmlReporter::sectionStarting( SectionInfo const& sectionInfo ) {\r\n        StreamingReporterBase::sectionStarting( sectionInfo );\r\n        if( m_sectionDepth++ > 0 ) {\r\n            m_xml.startElement( \"Section\" )\r\n                .writeAttribute( \"name\", trim( sectionInfo.name ) );\r\n            writeSourceInfo( sectionInfo.lineInfo );\r\n            m_xml.ensureTagClosed();\r\n        }\r\n    }\r\n\r\n    void XmlReporter::assertionStarting( AssertionInfo const& ) { }\r\n\r\n    bool XmlReporter::assertionEnded( AssertionStats const& assertionStats ) {\r\n\r\n        AssertionResult const& result = assertionStats.assertionResult;\r\n\r\n        bool includeResults = m_config->includeSuccessfulResults() || !result.isOk();\r\n\r\n        if( includeResults || result.getResultType() == ResultWas::Warning ) {\r\n            // Print any info messages in <Info> tags.\r\n            for( auto const& msg : assertionStats.infoMessages ) {\r\n                if( msg.type == ResultWas::Info && includeResults ) {\r\n                    m_xml.scopedElement( \"Info\" )\r\n                            .writeText( msg.message );\r\n                } else if ( msg.type == ResultWas::Warning ) {\r\n                    m_xml.scopedElement( \"Warning\" )\r\n                            .writeText( msg.message );\r\n                }\r\n            }\r\n        }\r\n\r\n        // Drop out if result was successful but we're not printing them.\r\n        if( !includeResults && result.getResultType() != ResultWas::Warning )\r\n            return true;\r\n\r\n        // Print the expression if there is one.\r\n        if( result.hasExpression() ) {\r\n            m_xml.startElement( \"Expression\" )\r\n                .writeAttribute( \"success\", result.succeeded() )\r\n                .writeAttribute( \"type\", result.getTestMacroName() );\r\n\r\n            writeSourceInfo( result.getSourceInfo() );\r\n\r\n            m_xml.scopedElement( \"Original\" )\r\n                .writeText( result.getExpression() );\r\n            m_xml.scopedElement( \"Expanded\" )\r\n                .writeText( result.getExpandedExpression() );\r\n        }\r\n\r\n        // And... Print a result applicable to each result type.\r\n        switch( result.getResultType() ) {\r\n            case ResultWas::ThrewException:\r\n                m_xml.startElement( \"Exception\" );\r\n                writeSourceInfo( result.getSourceInfo() );\r\n                m_xml.writeText( result.getMessage() );\r\n                m_xml.endElement();\r\n                break;\r\n            case ResultWas::FatalErrorCondition:\r\n                m_xml.startElement( \"FatalErrorCondition\" );\r\n                writeSourceInfo( result.getSourceInfo() );\r\n                m_xml.writeText( result.getMessage() );\r\n                m_xml.endElement();\r\n                break;\r\n            case ResultWas::Info:\r\n                m_xml.scopedElement( \"Info\" )\r\n                    .writeText( result.getMessage() );\r\n                break;\r\n            case ResultWas::Warning:\r\n                // Warning will already have been written\r\n                break;\r\n            case ResultWas::ExplicitFailure:\r\n                m_xml.startElement( \"Failure\" );\r\n                writeSourceInfo( result.getSourceInfo() );\r\n                m_xml.writeText( result.getMessage() );\r\n                m_xml.endElement();\r\n                break;\r\n            default:\r\n                break;\r\n        }\r\n\r\n        if( result.hasExpression() )\r\n            m_xml.endElement();\r\n\r\n        return true;\r\n    }\r\n\r\n    void XmlReporter::sectionEnded( SectionStats const& sectionStats ) {\r\n        StreamingReporterBase::sectionEnded( sectionStats );\r\n        if( --m_sectionDepth > 0 ) {\r\n            XmlWriter::ScopedElement e = m_xml.scopedElement( \"OverallResults\" );\r\n            e.writeAttribute( \"successes\", sectionStats.assertions.passed );\r\n            e.writeAttribute( \"failures\", sectionStats.assertions.failed );\r\n            e.writeAttribute( \"expectedFailures\", sectionStats.assertions.failedButOk );\r\n\r\n            if ( m_config->showDurations() == ShowDurations::Always )\r\n                e.writeAttribute( \"durationInSeconds\", sectionStats.durationInSeconds );\r\n\r\n            m_xml.endElement();\r\n        }\r\n    }\r\n\r\n    void XmlReporter::testCaseEnded( TestCaseStats const& testCaseStats ) {\r\n        StreamingReporterBase::testCaseEnded( testCaseStats );\r\n        XmlWriter::ScopedElement e = m_xml.scopedElement( \"OverallResult\" );\r\n        e.writeAttribute( \"success\", testCaseStats.totals.assertions.allOk() );\r\n\r\n        if ( m_config->showDurations() == ShowDurations::Always )\r\n            e.writeAttribute( \"durationInSeconds\", m_testCaseTimer.getElapsedSeconds() );\r\n\r\n        if( !testCaseStats.stdOut.empty() )\r\n            m_xml.scopedElement( \"StdOut\" ).writeText( trim( testCaseStats.stdOut ), false );\r\n        if( !testCaseStats.stdErr.empty() )\r\n            m_xml.scopedElement( \"StdErr\" ).writeText( trim( testCaseStats.stdErr ), false );\r\n\r\n        m_xml.endElement();\r\n    }\r\n\r\n    void XmlReporter::testGroupEnded( TestGroupStats const& testGroupStats ) {\r\n        StreamingReporterBase::testGroupEnded( testGroupStats );\r\n        // TODO: Check testGroupStats.aborting and act accordingly.\r\n        m_xml.scopedElement( \"OverallResults\" )\r\n            .writeAttribute( \"successes\", testGroupStats.totals.assertions.passed )\r\n            .writeAttribute( \"failures\", testGroupStats.totals.assertions.failed )\r\n            .writeAttribute( \"expectedFailures\", testGroupStats.totals.assertions.failedButOk );\r\n        m_xml.endElement();\r\n    }\r\n\r\n    void XmlReporter::testRunEnded( TestRunStats const& testRunStats ) {\r\n        StreamingReporterBase::testRunEnded( testRunStats );\r\n        m_xml.scopedElement( \"OverallResults\" )\r\n            .writeAttribute( \"successes\", testRunStats.totals.assertions.passed )\r\n            .writeAttribute( \"failures\", testRunStats.totals.assertions.failed )\r\n            .writeAttribute( \"expectedFailures\", testRunStats.totals.assertions.failedButOk );\r\n        m_xml.endElement();\r\n    }\r\n\r\n    CATCH_REGISTER_REPORTER( \"xml\", XmlReporter )\r\n\r\n} // end namespace Catch\r\n\r\n#if defined(_MSC_VER)\r\n#pragma warning(pop)\r\n#endif\r\n// end catch_reporter_xml.cpp\r\n\r\nnamespace Catch {\r\n    LeakDetector leakDetector;\r\n}\r\n\r\n#ifdef __clang__\r\n#pragma clang diagnostic pop\r\n#endif\r\n\r\n// end catch_impl.hpp\r\n#endif\r\n\r\n#ifdef CATCH_CONFIG_MAIN\r\n// start catch_default_main.hpp\r\n\r\n#ifndef __OBJC__\r\n\r\n#if defined(CATCH_CONFIG_WCHAR) && defined(WIN32) && defined(_UNICODE) && !defined(DO_NOT_USE_WMAIN)\r\n// Standard C/C++ Win32 Unicode wmain entry point\r\nextern \"C\" int wmain (int argc, wchar_t * argv[], wchar_t * []) {\r\n#else\r\n// Standard C/C++ main entry point\r\nint main (int argc, char * argv[]) {\r\n#endif\r\n\r\n    return Catch::Session().run( argc, argv );\r\n}\r\n\r\n#else // __OBJC__\r\n\r\n// Objective-C entry point\r\nint main (int argc, char * const argv[]) {\r\n#if !CATCH_ARC_ENABLED\r\n    NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init];\r\n#endif\r\n\r\n    Catch::registerTestMethods();\r\n    int result = Catch::Session().run( argc, (char**)argv );\r\n\r\n#if !CATCH_ARC_ENABLED\r\n    [pool drain];\r\n#endif\r\n\r\n    return result;\r\n}\r\n\r\n#endif // __OBJC__\r\n\r\n// end catch_default_main.hpp\r\n#endif\r\n\r\n#if !defined(CATCH_CONFIG_IMPL_ONLY)\r\n\r\n#ifdef CLARA_CONFIG_MAIN_NOT_DEFINED\r\n#  undef CLARA_CONFIG_MAIN\r\n#endif\r\n\r\n#if !defined(CATCH_CONFIG_DISABLE)\r\n//////\r\n// If this config identifier is defined then all CATCH macros are prefixed with CATCH_\r\n#ifdef CATCH_CONFIG_PREFIX_ALL\r\n\r\n#define CATCH_REQUIRE( ... ) INTERNAL_CATCH_TEST( \"CATCH_REQUIRE\", Catch::ResultDisposition::Normal, __VA_ARGS__ )\r\n#define CATCH_REQUIRE_FALSE( ... ) INTERNAL_CATCH_TEST( \"CATCH_REQUIRE_FALSE\", Catch::ResultDisposition::Normal | Catch::ResultDisposition::FalseTest, __VA_ARGS__ )\r\n\r\n#define CATCH_REQUIRE_THROWS( ... ) INTERNAL_CATCH_THROWS( \"CATCH_REQUIRE_THROWS\", Catch::ResultDisposition::Normal, __VA_ARGS__ )\r\n#define CATCH_REQUIRE_THROWS_AS( expr, exceptionType ) INTERNAL_CATCH_THROWS_AS( \"CATCH_REQUIRE_THROWS_AS\", exceptionType, Catch::ResultDisposition::Normal, expr )\r\n#define CATCH_REQUIRE_THROWS_WITH( expr, matcher ) INTERNAL_CATCH_THROWS_STR_MATCHES( \"CATCH_REQUIRE_THROWS_WITH\", Catch::ResultDisposition::Normal, matcher, expr )\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CATCH_REQUIRE_THROWS_MATCHES( expr, exceptionType, matcher ) INTERNAL_CATCH_THROWS_MATCHES( \"CATCH_REQUIRE_THROWS_MATCHES\", exceptionType, Catch::ResultDisposition::Normal, matcher, expr )\r\n#endif// CATCH_CONFIG_DISABLE_MATCHERS\r\n#define CATCH_REQUIRE_NOTHROW( ... ) INTERNAL_CATCH_NO_THROW( \"CATCH_REQUIRE_NOTHROW\", Catch::ResultDisposition::Normal, __VA_ARGS__ )\r\n\r\n#define CATCH_CHECK( ... ) INTERNAL_CATCH_TEST( \"CATCH_CHECK\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define CATCH_CHECK_FALSE( ... ) INTERNAL_CATCH_TEST( \"CATCH_CHECK_FALSE\", Catch::ResultDisposition::ContinueOnFailure | Catch::ResultDisposition::FalseTest, __VA_ARGS__ )\r\n#define CATCH_CHECKED_IF( ... ) INTERNAL_CATCH_IF( \"CATCH_CHECKED_IF\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define CATCH_CHECKED_ELSE( ... ) INTERNAL_CATCH_ELSE( \"CATCH_CHECKED_ELSE\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define CATCH_CHECK_NOFAIL( ... ) INTERNAL_CATCH_TEST( \"CATCH_CHECK_NOFAIL\", Catch::ResultDisposition::ContinueOnFailure | Catch::ResultDisposition::SuppressFail, __VA_ARGS__ )\r\n\r\n#define CATCH_CHECK_THROWS( ... )  INTERNAL_CATCH_THROWS( \"CATCH_CHECK_THROWS\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define CATCH_CHECK_THROWS_AS( expr, exceptionType ) INTERNAL_CATCH_THROWS_AS( \"CATCH_CHECK_THROWS_AS\", exceptionType, Catch::ResultDisposition::ContinueOnFailure, expr )\r\n#define CATCH_CHECK_THROWS_WITH( expr, matcher ) INTERNAL_CATCH_THROWS_STR_MATCHES( \"CATCH_CHECK_THROWS_WITH\", Catch::ResultDisposition::ContinueOnFailure, matcher, expr )\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CATCH_CHECK_THROWS_MATCHES( expr, exceptionType, matcher ) INTERNAL_CATCH_THROWS_MATCHES( \"CATCH_CHECK_THROWS_MATCHES\", exceptionType, Catch::ResultDisposition::ContinueOnFailure, matcher, expr )\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n#define CATCH_CHECK_NOTHROW( ... ) INTERNAL_CATCH_NO_THROW( \"CATCH_CHECK_NOTHROW\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CATCH_CHECK_THAT( arg, matcher ) INTERNAL_CHECK_THAT( \"CATCH_CHECK_THAT\", matcher, Catch::ResultDisposition::ContinueOnFailure, arg )\r\n\r\n#define CATCH_REQUIRE_THAT( arg, matcher ) INTERNAL_CHECK_THAT( \"CATCH_REQUIRE_THAT\", matcher, Catch::ResultDisposition::Normal, arg )\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n\r\n#define CATCH_INFO( msg ) INTERNAL_CATCH_INFO( \"CATCH_INFO\", msg )\r\n#define CATCH_WARN( msg ) INTERNAL_CATCH_MSG( \"CATCH_WARN\", Catch::ResultWas::Warning, Catch::ResultDisposition::ContinueOnFailure, msg )\r\n#define CATCH_CAPTURE( ... ) INTERNAL_CATCH_CAPTURE( INTERNAL_CATCH_UNIQUE_NAME(capturer), \"CATCH_CAPTURE\",__VA_ARGS__ )\r\n\r\n#define CATCH_TEST_CASE( ... ) INTERNAL_CATCH_TESTCASE( __VA_ARGS__ )\r\n#define CATCH_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#define CATCH_METHOD_AS_TEST_CASE( method, ... ) INTERNAL_CATCH_METHOD_AS_TEST_CASE( method, __VA_ARGS__ )\r\n#define CATCH_REGISTER_TEST_CASE( Function, ... ) INTERNAL_CATCH_REGISTER_TESTCASE( Function, __VA_ARGS__ )\r\n#define CATCH_SECTION( ... ) INTERNAL_CATCH_SECTION( __VA_ARGS__ )\r\n#define CATCH_DYNAMIC_SECTION( ... ) INTERNAL_CATCH_DYNAMIC_SECTION( __VA_ARGS__ )\r\n#define CATCH_FAIL( ... ) INTERNAL_CATCH_MSG( \"CATCH_FAIL\", Catch::ResultWas::ExplicitFailure, Catch::ResultDisposition::Normal, __VA_ARGS__ )\r\n#define CATCH_FAIL_CHECK( ... ) INTERNAL_CATCH_MSG( \"CATCH_FAIL_CHECK\", Catch::ResultWas::ExplicitFailure, Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define CATCH_SUCCEED( ... ) INTERNAL_CATCH_MSG( \"CATCH_SUCCEED\", Catch::ResultWas::Ok, Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n\r\n#define CATCH_ANON_TEST_CASE() INTERNAL_CATCH_TESTCASE()\r\n\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n#define CATCH_TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ )\r\n#define CATCH_TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#define CATCH_TEMPLATE_PRODUCT_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE( __VA_ARGS__ )\r\n#define CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#else\r\n#define CATCH_TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ ) )\r\n#define CATCH_TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) )\r\n#define CATCH_TEMPLATE_PRODUCT_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE( __VA_ARGS__ ) )\r\n#define CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, __VA_ARGS__ ) )\r\n#endif\r\n\r\n#if !defined(CATCH_CONFIG_RUNTIME_STATIC_REQUIRE)\r\n#define CATCH_STATIC_REQUIRE( ... )       static_assert(   __VA_ARGS__ ,      #__VA_ARGS__ );     CATCH_SUCCEED( #__VA_ARGS__ )\r\n#define CATCH_STATIC_REQUIRE_FALSE( ... ) static_assert( !(__VA_ARGS__), \"!(\" #__VA_ARGS__ \")\" ); CATCH_SUCCEED( #__VA_ARGS__ )\r\n#else\r\n#define CATCH_STATIC_REQUIRE( ... )       CATCH_REQUIRE( __VA_ARGS__ )\r\n#define CATCH_STATIC_REQUIRE_FALSE( ... ) CATCH_REQUIRE_FALSE( __VA_ARGS__ )\r\n#endif\r\n\r\n// \"BDD-style\" convenience wrappers\r\n#define CATCH_SCENARIO( ... ) CATCH_TEST_CASE( \"Scenario: \" __VA_ARGS__ )\r\n#define CATCH_SCENARIO_METHOD( className, ... ) INTERNAL_CATCH_TEST_CASE_METHOD( className, \"Scenario: \" __VA_ARGS__ )\r\n#define CATCH_GIVEN( desc )     INTERNAL_CATCH_DYNAMIC_SECTION( \"    Given: \" << desc )\r\n#define CATCH_AND_GIVEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( \"And given: \" << desc )\r\n#define CATCH_WHEN( desc )      INTERNAL_CATCH_DYNAMIC_SECTION( \"     When: \" << desc )\r\n#define CATCH_AND_WHEN( desc )  INTERNAL_CATCH_DYNAMIC_SECTION( \" And when: \" << desc )\r\n#define CATCH_THEN( desc )      INTERNAL_CATCH_DYNAMIC_SECTION( \"     Then: \" << desc )\r\n#define CATCH_AND_THEN( desc )  INTERNAL_CATCH_DYNAMIC_SECTION( \"      And: \" << desc )\r\n\r\n// If CATCH_CONFIG_PREFIX_ALL is not defined then the CATCH_ prefix is not required\r\n#else\r\n\r\n#define REQUIRE( ... ) INTERNAL_CATCH_TEST( \"REQUIRE\", Catch::ResultDisposition::Normal, __VA_ARGS__  )\r\n#define REQUIRE_FALSE( ... ) INTERNAL_CATCH_TEST( \"REQUIRE_FALSE\", Catch::ResultDisposition::Normal | Catch::ResultDisposition::FalseTest, __VA_ARGS__ )\r\n\r\n#define REQUIRE_THROWS( ... ) INTERNAL_CATCH_THROWS( \"REQUIRE_THROWS\", Catch::ResultDisposition::Normal, __VA_ARGS__ )\r\n#define REQUIRE_THROWS_AS( expr, exceptionType ) INTERNAL_CATCH_THROWS_AS( \"REQUIRE_THROWS_AS\", exceptionType, Catch::ResultDisposition::Normal, expr )\r\n#define REQUIRE_THROWS_WITH( expr, matcher ) INTERNAL_CATCH_THROWS_STR_MATCHES( \"REQUIRE_THROWS_WITH\", Catch::ResultDisposition::Normal, matcher, expr )\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define REQUIRE_THROWS_MATCHES( expr, exceptionType, matcher ) INTERNAL_CATCH_THROWS_MATCHES( \"REQUIRE_THROWS_MATCHES\", exceptionType, Catch::ResultDisposition::Normal, matcher, expr )\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n#define REQUIRE_NOTHROW( ... ) INTERNAL_CATCH_NO_THROW( \"REQUIRE_NOTHROW\", Catch::ResultDisposition::Normal, __VA_ARGS__ )\r\n\r\n#define CHECK( ... ) INTERNAL_CATCH_TEST( \"CHECK\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define CHECK_FALSE( ... ) INTERNAL_CATCH_TEST( \"CHECK_FALSE\", Catch::ResultDisposition::ContinueOnFailure | Catch::ResultDisposition::FalseTest, __VA_ARGS__ )\r\n#define CHECKED_IF( ... ) INTERNAL_CATCH_IF( \"CHECKED_IF\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define CHECKED_ELSE( ... ) INTERNAL_CATCH_ELSE( \"CHECKED_ELSE\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define CHECK_NOFAIL( ... ) INTERNAL_CATCH_TEST( \"CHECK_NOFAIL\", Catch::ResultDisposition::ContinueOnFailure | Catch::ResultDisposition::SuppressFail, __VA_ARGS__ )\r\n\r\n#define CHECK_THROWS( ... )  INTERNAL_CATCH_THROWS( \"CHECK_THROWS\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define CHECK_THROWS_AS( expr, exceptionType ) INTERNAL_CATCH_THROWS_AS( \"CHECK_THROWS_AS\", exceptionType, Catch::ResultDisposition::ContinueOnFailure, expr )\r\n#define CHECK_THROWS_WITH( expr, matcher ) INTERNAL_CATCH_THROWS_STR_MATCHES( \"CHECK_THROWS_WITH\", Catch::ResultDisposition::ContinueOnFailure, matcher, expr )\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CHECK_THROWS_MATCHES( expr, exceptionType, matcher ) INTERNAL_CATCH_THROWS_MATCHES( \"CHECK_THROWS_MATCHES\", exceptionType, Catch::ResultDisposition::ContinueOnFailure, matcher, expr )\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n#define CHECK_NOTHROW( ... ) INTERNAL_CATCH_NO_THROW( \"CHECK_NOTHROW\", Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CHECK_THAT( arg, matcher ) INTERNAL_CHECK_THAT( \"CHECK_THAT\", matcher, Catch::ResultDisposition::ContinueOnFailure, arg )\r\n\r\n#define REQUIRE_THAT( arg, matcher ) INTERNAL_CHECK_THAT( \"REQUIRE_THAT\", matcher, Catch::ResultDisposition::Normal, arg )\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n\r\n#define INFO( msg ) INTERNAL_CATCH_INFO( \"INFO\", msg )\r\n#define UNSCOPED_INFO( msg ) INTERNAL_CATCH_UNSCOPED_INFO( \"UNSCOPED_INFO\", msg )\r\n#define WARN( msg ) INTERNAL_CATCH_MSG( \"WARN\", Catch::ResultWas::Warning, Catch::ResultDisposition::ContinueOnFailure, msg )\r\n#define CAPTURE( ... ) INTERNAL_CATCH_CAPTURE( INTERNAL_CATCH_UNIQUE_NAME(capturer), \"CAPTURE\",__VA_ARGS__ )\r\n\r\n#define TEST_CASE( ... ) INTERNAL_CATCH_TESTCASE( __VA_ARGS__ )\r\n#define TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#define METHOD_AS_TEST_CASE( method, ... ) INTERNAL_CATCH_METHOD_AS_TEST_CASE( method, __VA_ARGS__ )\r\n#define REGISTER_TEST_CASE( Function, ... ) INTERNAL_CATCH_REGISTER_TESTCASE( Function, __VA_ARGS__ )\r\n#define SECTION( ... ) INTERNAL_CATCH_SECTION( __VA_ARGS__ )\r\n#define DYNAMIC_SECTION( ... ) INTERNAL_CATCH_DYNAMIC_SECTION( __VA_ARGS__ )\r\n#define FAIL( ... ) INTERNAL_CATCH_MSG( \"FAIL\", Catch::ResultWas::ExplicitFailure, Catch::ResultDisposition::Normal, __VA_ARGS__ )\r\n#define FAIL_CHECK( ... ) INTERNAL_CATCH_MSG( \"FAIL_CHECK\", Catch::ResultWas::ExplicitFailure, Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define SUCCEED( ... ) INTERNAL_CATCH_MSG( \"SUCCEED\", Catch::ResultWas::Ok, Catch::ResultDisposition::ContinueOnFailure, __VA_ARGS__ )\r\n#define ANON_TEST_CASE() INTERNAL_CATCH_TESTCASE()\r\n\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n#define TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ )\r\n#define TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#define TEMPLATE_PRODUCT_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE( __VA_ARGS__ )\r\n#define TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#else\r\n#define TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ ) )\r\n#define TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ ) )\r\n#define TEMPLATE_PRODUCT_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE( __VA_ARGS__ ) )\r\n#define TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, __VA_ARGS__ ) )\r\n#endif\r\n\r\n#if !defined(CATCH_CONFIG_RUNTIME_STATIC_REQUIRE)\r\n#define STATIC_REQUIRE( ... )       static_assert(   __VA_ARGS__,  #__VA_ARGS__ ); SUCCEED( #__VA_ARGS__ )\r\n#define STATIC_REQUIRE_FALSE( ... ) static_assert( !(__VA_ARGS__), \"!(\" #__VA_ARGS__ \")\" ); SUCCEED( \"!(\" #__VA_ARGS__ \")\" )\r\n#else\r\n#define STATIC_REQUIRE( ... )       REQUIRE( __VA_ARGS__ )\r\n#define STATIC_REQUIRE_FALSE( ... ) REQUIRE_FALSE( __VA_ARGS__ )\r\n#endif\r\n\r\n#endif\r\n\r\n#define CATCH_TRANSLATE_EXCEPTION( signature ) INTERNAL_CATCH_TRANSLATE_EXCEPTION( signature )\r\n\r\n// \"BDD-style\" convenience wrappers\r\n#define SCENARIO( ... ) TEST_CASE( \"Scenario: \" __VA_ARGS__ )\r\n#define SCENARIO_METHOD( className, ... ) INTERNAL_CATCH_TEST_CASE_METHOD( className, \"Scenario: \" __VA_ARGS__ )\r\n\r\n#define GIVEN( desc )     INTERNAL_CATCH_DYNAMIC_SECTION( \"    Given: \" << desc )\r\n#define AND_GIVEN( desc ) INTERNAL_CATCH_DYNAMIC_SECTION( \"And given: \" << desc )\r\n#define WHEN( desc )      INTERNAL_CATCH_DYNAMIC_SECTION( \"     When: \" << desc )\r\n#define AND_WHEN( desc )  INTERNAL_CATCH_DYNAMIC_SECTION( \" And when: \" << desc )\r\n#define THEN( desc )      INTERNAL_CATCH_DYNAMIC_SECTION( \"     Then: \" << desc )\r\n#define AND_THEN( desc )  INTERNAL_CATCH_DYNAMIC_SECTION( \"      And: \" << desc )\r\n\r\nusing Catch::Detail::Approx;\r\n\r\n#else // CATCH_CONFIG_DISABLE\r\n\r\n//////\r\n// If this config identifier is defined then all CATCH macros are prefixed with CATCH_\r\n#ifdef CATCH_CONFIG_PREFIX_ALL\r\n\r\n#define CATCH_REQUIRE( ... )        (void)(0)\r\n#define CATCH_REQUIRE_FALSE( ... )  (void)(0)\r\n\r\n#define CATCH_REQUIRE_THROWS( ... ) (void)(0)\r\n#define CATCH_REQUIRE_THROWS_AS( expr, exceptionType ) (void)(0)\r\n#define CATCH_REQUIRE_THROWS_WITH( expr, matcher )     (void)(0)\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CATCH_REQUIRE_THROWS_MATCHES( expr, exceptionType, matcher ) (void)(0)\r\n#endif// CATCH_CONFIG_DISABLE_MATCHERS\r\n#define CATCH_REQUIRE_NOTHROW( ... ) (void)(0)\r\n\r\n#define CATCH_CHECK( ... )         (void)(0)\r\n#define CATCH_CHECK_FALSE( ... )   (void)(0)\r\n#define CATCH_CHECKED_IF( ... )    if (__VA_ARGS__)\r\n#define CATCH_CHECKED_ELSE( ... )  if (!(__VA_ARGS__))\r\n#define CATCH_CHECK_NOFAIL( ... )  (void)(0)\r\n\r\n#define CATCH_CHECK_THROWS( ... )  (void)(0)\r\n#define CATCH_CHECK_THROWS_AS( expr, exceptionType ) (void)(0)\r\n#define CATCH_CHECK_THROWS_WITH( expr, matcher )     (void)(0)\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CATCH_CHECK_THROWS_MATCHES( expr, exceptionType, matcher ) (void)(0)\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n#define CATCH_CHECK_NOTHROW( ... ) (void)(0)\r\n\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CATCH_CHECK_THAT( arg, matcher )   (void)(0)\r\n\r\n#define CATCH_REQUIRE_THAT( arg, matcher ) (void)(0)\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n\r\n#define CATCH_INFO( msg )    (void)(0)\r\n#define CATCH_WARN( msg )    (void)(0)\r\n#define CATCH_CAPTURE( msg ) (void)(0)\r\n\r\n#define CATCH_TEST_CASE( ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ))\r\n#define CATCH_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ))\r\n#define CATCH_METHOD_AS_TEST_CASE( method, ... )\r\n#define CATCH_REGISTER_TEST_CASE( Function, ... ) (void)(0)\r\n#define CATCH_SECTION( ... )\r\n#define CATCH_DYNAMIC_SECTION( ... )\r\n#define CATCH_FAIL( ... ) (void)(0)\r\n#define CATCH_FAIL_CHECK( ... ) (void)(0)\r\n#define CATCH_SUCCEED( ... ) (void)(0)\r\n\r\n#define CATCH_ANON_TEST_CASE() INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ))\r\n\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n#define CATCH_TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) )\r\n#define CATCH_TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), className )\r\n#define CATCH_TEMPLATE_PRODUCT_TEST_CASE( ... ) CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ )\r\n#define CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#else\r\n#define CATCH_TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) ) )\r\n#define CATCH_TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), className ) )\r\n#define CATCH_TEMPLATE_PRODUCT_TEST_CASE( ... ) CATCH_TEMPLATE_TEST_CASE( __VA_ARGS__ )\r\n#define CATCH_TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) CATCH_TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#endif\r\n\r\n// \"BDD-style\" convenience wrappers\r\n#define CATCH_SCENARIO( ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ))\r\n#define CATCH_SCENARIO_METHOD( className, ... ) INTERNAL_CATCH_TESTCASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ), className )\r\n#define CATCH_GIVEN( desc )\r\n#define CATCH_AND_GIVEN( desc )\r\n#define CATCH_WHEN( desc )\r\n#define CATCH_AND_WHEN( desc )\r\n#define CATCH_THEN( desc )\r\n#define CATCH_AND_THEN( desc )\r\n\r\n#define CATCH_STATIC_REQUIRE( ... )       (void)(0)\r\n#define CATCH_STATIC_REQUIRE_FALSE( ... ) (void)(0)\r\n\r\n// If CATCH_CONFIG_PREFIX_ALL is not defined then the CATCH_ prefix is not required\r\n#else\r\n\r\n#define REQUIRE( ... )       (void)(0)\r\n#define REQUIRE_FALSE( ... ) (void)(0)\r\n\r\n#define REQUIRE_THROWS( ... ) (void)(0)\r\n#define REQUIRE_THROWS_AS( expr, exceptionType ) (void)(0)\r\n#define REQUIRE_THROWS_WITH( expr, matcher ) (void)(0)\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define REQUIRE_THROWS_MATCHES( expr, exceptionType, matcher ) (void)(0)\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n#define REQUIRE_NOTHROW( ... ) (void)(0)\r\n\r\n#define CHECK( ... ) (void)(0)\r\n#define CHECK_FALSE( ... ) (void)(0)\r\n#define CHECKED_IF( ... ) if (__VA_ARGS__)\r\n#define CHECKED_ELSE( ... ) if (!(__VA_ARGS__))\r\n#define CHECK_NOFAIL( ... ) (void)(0)\r\n\r\n#define CHECK_THROWS( ... )  (void)(0)\r\n#define CHECK_THROWS_AS( expr, exceptionType ) (void)(0)\r\n#define CHECK_THROWS_WITH( expr, matcher ) (void)(0)\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CHECK_THROWS_MATCHES( expr, exceptionType, matcher ) (void)(0)\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n#define CHECK_NOTHROW( ... ) (void)(0)\r\n\r\n#if !defined(CATCH_CONFIG_DISABLE_MATCHERS)\r\n#define CHECK_THAT( arg, matcher ) (void)(0)\r\n\r\n#define REQUIRE_THAT( arg, matcher ) (void)(0)\r\n#endif // CATCH_CONFIG_DISABLE_MATCHERS\r\n\r\n#define INFO( msg ) (void)(0)\r\n#define WARN( msg ) (void)(0)\r\n#define CAPTURE( msg ) (void)(0)\r\n\r\n#define TEST_CASE( ... )  INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ))\r\n#define TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ))\r\n#define METHOD_AS_TEST_CASE( method, ... )\r\n#define REGISTER_TEST_CASE( Function, ... ) (void)(0)\r\n#define SECTION( ... )\r\n#define DYNAMIC_SECTION( ... )\r\n#define FAIL( ... ) (void)(0)\r\n#define FAIL_CHECK( ... ) (void)(0)\r\n#define SUCCEED( ... ) (void)(0)\r\n#define ANON_TEST_CASE() INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ))\r\n\r\n#ifndef CATCH_CONFIG_TRADITIONAL_MSVC_PREPROCESSOR\r\n#define TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) )\r\n#define TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), className )\r\n#define TEMPLATE_PRODUCT_TEST_CASE( ... ) TEMPLATE_TEST_CASE( __VA_ARGS__ )\r\n#define TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#else\r\n#define TEMPLATE_TEST_CASE( ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ) ) )\r\n#define TEMPLATE_TEST_CASE_METHOD( className, ... ) INTERNAL_CATCH_EXPAND_VARGS( INTERNAL_CATCH_TEMPLATE_TEST_CASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_M_P_L_A_T_E____T_E_S_T____ ), className ) )\r\n#define TEMPLATE_PRODUCT_TEST_CASE( ... ) TEMPLATE_TEST_CASE( __VA_ARGS__ )\r\n#define TEMPLATE_PRODUCT_TEST_CASE_METHOD( className, ... ) TEMPLATE_TEST_CASE_METHOD( className, __VA_ARGS__ )\r\n#endif\r\n\r\n#define STATIC_REQUIRE( ... )       (void)(0)\r\n#define STATIC_REQUIRE_FALSE( ... ) (void)(0)\r\n\r\n#endif\r\n\r\n#define CATCH_TRANSLATE_EXCEPTION( signature ) INTERNAL_CATCH_TRANSLATE_EXCEPTION_NO_REG( INTERNAL_CATCH_UNIQUE_NAME( catch_internal_ExceptionTranslator ), signature )\r\n\r\n// \"BDD-style\" convenience wrappers\r\n#define SCENARIO( ... ) INTERNAL_CATCH_TESTCASE_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ) )\r\n#define SCENARIO_METHOD( className, ... ) INTERNAL_CATCH_TESTCASE_METHOD_NO_REGISTRATION(INTERNAL_CATCH_UNIQUE_NAME( ____C_A_T_C_H____T_E_S_T____ ), className )\r\n\r\n#define GIVEN( desc )\r\n#define AND_GIVEN( desc )\r\n#define WHEN( desc )\r\n#define AND_WHEN( desc )\r\n#define THEN( desc )\r\n#define AND_THEN( desc )\r\n\r\nusing Catch::Detail::Approx;\r\n\r\n#endif\r\n\r\n#endif // ! CATCH_CONFIG_IMPL_ONLY\r\n\r\n// start catch_reenable_warnings.h\r\n\r\n\r\n#ifdef __clang__\r\n#    ifdef __ICC // icpc defines the __clang__ macro\r\n#        pragma warning(pop)\r\n#    else\r\n#        pragma clang diagnostic pop\r\n#    endif\r\n#elif defined __GNUC__\r\n#    pragma GCC diagnostic pop\r\n#endif\r\n\r\n// end catch_reenable_warnings.h\r\n// end catch.hpp\r\n#endif // TWOBLUECUBES_SINGLE_INCLUDE_CATCH_HPP_INCLUDED\r\n\r\n"
  },
  {
    "path": "external/printf/test/test_suite.cpp",
    "content": "///////////////////////////////////////////////////////////////////////////////\r\n// \\author (c) Marco Paland (info@paland.com)\r\n//             2017-2019, PALANDesign Hannover, Germany\r\n//\r\n// \\license The MIT License (MIT)\r\n//\r\n// Permission is hereby granted, free of charge, to any person obtaining a copy\r\n// of this software and associated documentation files (the \"Software\"), to deal\r\n// in the Software without restriction, including without limitation the rights\r\n// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\r\n// copies of the Software, and to permit persons to whom the Software is\r\n// furnished to do so, subject to the following conditions:\r\n// \r\n// The above copyright notice and this permission notice shall be included in\r\n// all copies or substantial portions of the Software.\r\n// \r\n// THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r\n// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r\n// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\r\n// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\r\n// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\r\n// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\r\n// THE SOFTWARE.\r\n//\r\n// \\brief printf unit tests\r\n//\r\n///////////////////////////////////////////////////////////////////////////////\r\n\r\n// use the 'catch' test framework\r\n#define CATCH_CONFIG_MAIN\r\n#include \"catch.hpp\"\r\n\r\n#include <string.h>\r\n#include <sstream>\r\n#include <math.h>\r\n\r\nnamespace test {\r\n  // use functions in own test namespace to avoid stdio conflicts\r\n  #include \"../printf.h\"\r\n  #include \"../printf.c\"\r\n} // namespace test\r\n\r\n\r\n// dummy putchar\r\nstatic char   printf_buffer[100];\r\nstatic size_t printf_idx = 0U;\r\n\r\nvoid test::_putchar(char character)\r\n{\r\n  printf_buffer[printf_idx++] = character;\r\n}\r\n\r\nvoid _out_fct(char character, void* arg)\r\n{\r\n  (void)arg;\r\n  printf_buffer[printf_idx++] = character;\r\n}\r\n\r\n\r\nTEST_CASE(\"printf\", \"[]\" ) {\r\n  printf_idx = 0U;\r\n  memset(printf_buffer, 0xCC, 100U);\r\n  REQUIRE(test::printf(\"% d\", 4232) == 5);\r\n  REQUIRE(printf_buffer[5] == (char)0xCC);\r\n  printf_buffer[5] = 0;\r\n  REQUIRE(!strcmp(printf_buffer, \" 4232\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"fctprintf\", \"[]\" ) {\r\n  printf_idx = 0U;\r\n  memset(printf_buffer, 0xCC, 100U);\r\n  test::fctprintf(&_out_fct, nullptr, \"This is a test of %X\", 0x12EFU);\r\n  REQUIRE(!strncmp(printf_buffer, \"This is a test of 12EF\", 22U));\r\n  REQUIRE(printf_buffer[22] == (char)0xCC);\r\n}\r\n\r\n\r\nTEST_CASE(\"snprintf\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::snprintf(buffer, 100U, \"%d\", -1000);\r\n  REQUIRE(!strcmp(buffer, \"-1000\"));\r\n\r\n  test::snprintf(buffer, 3U, \"%d\", -1000);\r\n  REQUIRE(!strcmp(buffer, \"-1\"));\r\n}\r\n\r\nstatic void vprintf_builder_1(char* buffer, ...)\r\n{\r\n  va_list args;\r\n  va_start(args, buffer);\r\n  test::vprintf(\"%d\", args);\r\n  va_end(args);\r\n}\r\n\r\nstatic void vsnprintf_builder_1(char* buffer, ...)\r\n{\r\n  va_list args;\r\n  va_start(args, buffer);\r\n  test::vsnprintf(buffer, 100U, \"%d\", args);\r\n  va_end(args);\r\n}\r\n\r\nstatic void vsnprintf_builder_3(char* buffer, ...)\r\n{\r\n  va_list args;\r\n  va_start(args, buffer);\r\n  test::vsnprintf(buffer, 100U, \"%d %d %s\", args);\r\n  va_end(args);\r\n}\r\n\r\n\r\nTEST_CASE(\"vprintf\", \"[]\" ) {\r\n  char buffer[100];\r\n  printf_idx = 0U;\r\n  memset(printf_buffer, 0xCC, 100U);\r\n  vprintf_builder_1(buffer, 2345);\r\n  REQUIRE(printf_buffer[4] == (char)0xCC);\r\n  printf_buffer[4] = 0;\r\n  REQUIRE(!strcmp(printf_buffer, \"2345\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"vsnprintf\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  vsnprintf_builder_1(buffer, -1);\r\n  REQUIRE(!strcmp(buffer, \"-1\"));\r\n\r\n  vsnprintf_builder_3(buffer, 3, -1000, \"test\");\r\n  REQUIRE(!strcmp(buffer, \"3 -1000 test\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"space flag\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"% d\", 42);\r\n  REQUIRE(!strcmp(buffer, \" 42\"));\r\n\r\n  test::sprintf(buffer, \"% d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42\"));\r\n\r\n  test::sprintf(buffer, \"% 5d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"   42\"));\r\n\r\n  test::sprintf(buffer, \"% 5d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"  -42\"));\r\n\r\n  test::sprintf(buffer, \"% 15d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"             42\"));\r\n\r\n  test::sprintf(buffer, \"% 15d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"            -42\"));\r\n\r\n  test::sprintf(buffer, \"% 15d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"            -42\"));\r\n\r\n  test::sprintf(buffer, \"% 15.3f\", -42.987);\r\n  REQUIRE(!strcmp(buffer, \"        -42.987\"));\r\n\r\n  test::sprintf(buffer, \"% 15.3f\", 42.987);\r\n  REQUIRE(!strcmp(buffer, \"         42.987\"));\r\n\r\n  test::sprintf(buffer, \"% s\", \"Hello testing\");\r\n  REQUIRE(!strcmp(buffer, \"Hello testing\"));\r\n\r\n  test::sprintf(buffer, \"% d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \" 1024\"));\r\n\r\n  test::sprintf(buffer, \"% d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024\"));\r\n\r\n  test::sprintf(buffer, \"% i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \" 1024\"));\r\n\r\n  test::sprintf(buffer, \"% i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024\"));\r\n\r\n  test::sprintf(buffer, \"% u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024\"));\r\n\r\n  test::sprintf(buffer, \"% u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"4294966272\"));\r\n\r\n  test::sprintf(buffer, \"% o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"777\"));\r\n\r\n  test::sprintf(buffer, \"% o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"37777777001\"));\r\n\r\n  test::sprintf(buffer, \"% x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"% x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"% X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"% X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"EDCB5433\"));\r\n\r\n  test::sprintf(buffer, \"% c\", 'x');\r\n  REQUIRE(!strcmp(buffer, \"x\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"+ flag\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%+d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"+42\"));\r\n\r\n  test::sprintf(buffer, \"%+d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42\"));\r\n\r\n  test::sprintf(buffer, \"%+5d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"  +42\"));\r\n\r\n  test::sprintf(buffer, \"%+5d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"  -42\"));\r\n\r\n  test::sprintf(buffer, \"%+15d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"            +42\"));\r\n\r\n  test::sprintf(buffer, \"%+15d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"            -42\"));\r\n\r\n  test::sprintf(buffer, \"%+s\", \"Hello testing\");\r\n  REQUIRE(!strcmp(buffer, \"Hello testing\"));\r\n\r\n  test::sprintf(buffer, \"%+d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"+1024\"));\r\n\r\n  test::sprintf(buffer, \"%+d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024\"));\r\n\r\n  test::sprintf(buffer, \"%+i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"+1024\"));\r\n\r\n  test::sprintf(buffer, \"%+i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024\"));\r\n\r\n  test::sprintf(buffer, \"%+u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024\"));\r\n\r\n  test::sprintf(buffer, \"%+u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"4294966272\"));\r\n\r\n  test::sprintf(buffer, \"%+o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"777\"));\r\n\r\n  test::sprintf(buffer, \"%+o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"37777777001\"));\r\n\r\n  test::sprintf(buffer, \"%+x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%+x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%+X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%+X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"EDCB5433\"));\r\n\r\n  test::sprintf(buffer, \"%+c\", 'x');\r\n  REQUIRE(!strcmp(buffer, \"x\"));\r\n\r\n  test::sprintf(buffer, \"%+.0d\", 0);\r\n  REQUIRE(!strcmp(buffer, \"+\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"0 flag\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%0d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42\"));\r\n\r\n  test::sprintf(buffer, \"%0ld\", 42L);\r\n  REQUIRE(!strcmp(buffer, \"42\"));\r\n\r\n  test::sprintf(buffer, \"%0d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42\"));\r\n\r\n  test::sprintf(buffer, \"%05d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"00042\"));\r\n\r\n  test::sprintf(buffer, \"%05d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-0042\"));\r\n\r\n  test::sprintf(buffer, \"%015d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"000000000000042\"));\r\n\r\n  test::sprintf(buffer, \"%015d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-00000000000042\"));\r\n\r\n  test::sprintf(buffer, \"%015.2f\", 42.1234);\r\n  REQUIRE(!strcmp(buffer, \"000000000042.12\"));\r\n\r\n  test::sprintf(buffer, \"%015.3f\", 42.9876);\r\n  REQUIRE(!strcmp(buffer, \"00000000042.988\"));\r\n\r\n  test::sprintf(buffer, \"%015.5f\", -42.9876);\r\n  REQUIRE(!strcmp(buffer, \"-00000042.98760\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"- flag\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%-d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42\"));\r\n\r\n  test::sprintf(buffer, \"%-d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42\"));\r\n\r\n  test::sprintf(buffer, \"%-5d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42   \"));\r\n\r\n  test::sprintf(buffer, \"%-5d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42  \"));\r\n\r\n  test::sprintf(buffer, \"%-15d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42             \"));\r\n\r\n  test::sprintf(buffer, \"%-15d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42            \"));\r\n\r\n  test::sprintf(buffer, \"%-0d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42\"));\r\n\r\n  test::sprintf(buffer, \"%-0d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42\"));\r\n\r\n  test::sprintf(buffer, \"%-05d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42   \"));\r\n\r\n  test::sprintf(buffer, \"%-05d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42  \"));\r\n\r\n  test::sprintf(buffer, \"%-015d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42             \"));\r\n\r\n  test::sprintf(buffer, \"%-015d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42            \"));\r\n\r\n  test::sprintf(buffer, \"%0-d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42\"));\r\n\r\n  test::sprintf(buffer, \"%0-d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42\"));\r\n\r\n  test::sprintf(buffer, \"%0-5d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42   \"));\r\n\r\n  test::sprintf(buffer, \"%0-5d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42  \"));\r\n\r\n  test::sprintf(buffer, \"%0-15d\", 42);\r\n  REQUIRE(!strcmp(buffer, \"42             \"));\r\n\r\n  test::sprintf(buffer, \"%0-15d\", -42);\r\n  REQUIRE(!strcmp(buffer, \"-42            \"));\r\n\r\n  test::sprintf(buffer, \"%0-15.3e\", -42.);\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n  REQUIRE(!strcmp(buffer, \"-4.200e+01     \"));\r\n#else\r\n  REQUIRE(!strcmp(buffer, \"e\"));\r\n#endif\r\n\r\n  test::sprintf(buffer, \"%0-15.3g\", -42.);\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n  REQUIRE(!strcmp(buffer, \"-42.0          \"));\r\n#else\r\n  REQUIRE(!strcmp(buffer, \"g\"));\r\n#endif\r\n}\r\n\r\n\r\nTEST_CASE(\"# flag\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%#.0x\", 0);\r\n  REQUIRE(!strcmp(buffer, \"\"));\r\n  test::sprintf(buffer, \"%#.1x\", 0);\r\n  REQUIRE(!strcmp(buffer, \"0\"));\r\n  test::sprintf(buffer, \"%#.0llx\", (long long)0);\r\n  REQUIRE(!strcmp(buffer, \"\"));\r\n  test::sprintf(buffer, \"%#.8x\", 0x614e);\r\n  REQUIRE(!strcmp(buffer, \"0x0000614e\"));\r\n  test::sprintf(buffer,\"%#b\", 6);\r\n  REQUIRE(!strcmp(buffer, \"0b110\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"specifier\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"Hello testing\");\r\n  REQUIRE(!strcmp(buffer, \"Hello testing\"));\r\n\r\n  test::sprintf(buffer, \"%s\", \"Hello testing\");\r\n  REQUIRE(!strcmp(buffer, \"Hello testing\"));\r\n\r\n  test::sprintf(buffer, \"%d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024\"));\r\n\r\n  test::sprintf(buffer, \"%d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024\"));\r\n\r\n  test::sprintf(buffer, \"%i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024\"));\r\n\r\n  test::sprintf(buffer, \"%i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024\"));\r\n\r\n  test::sprintf(buffer, \"%u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024\"));\r\n\r\n  test::sprintf(buffer, \"%u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"4294966272\"));\r\n\r\n  test::sprintf(buffer, \"%o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"777\"));\r\n\r\n  test::sprintf(buffer, \"%o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"37777777001\"));\r\n\r\n  test::sprintf(buffer, \"%x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"EDCB5433\"));\r\n\r\n  test::sprintf(buffer, \"%%\");\r\n  REQUIRE(!strcmp(buffer, \"%\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"width\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%1s\", \"Hello testing\");\r\n  REQUIRE(!strcmp(buffer, \"Hello testing\"));\r\n\r\n  test::sprintf(buffer, \"%1d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024\"));\r\n\r\n  test::sprintf(buffer, \"%1d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024\"));\r\n\r\n  test::sprintf(buffer, \"%1i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024\"));\r\n\r\n  test::sprintf(buffer, \"%1i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024\"));\r\n\r\n  test::sprintf(buffer, \"%1u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024\"));\r\n\r\n  test::sprintf(buffer, \"%1u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"4294966272\"));\r\n\r\n  test::sprintf(buffer, \"%1o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"777\"));\r\n\r\n  test::sprintf(buffer, \"%1o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"37777777001\"));\r\n\r\n  test::sprintf(buffer, \"%1x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%1x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%1X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%1X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"EDCB5433\"));\r\n\r\n  test::sprintf(buffer, \"%1c\", 'x');\r\n  REQUIRE(!strcmp(buffer, \"x\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"width 20\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%20s\", \"Hello\");\r\n  REQUIRE(!strcmp(buffer, \"               Hello\"));\r\n\r\n  test::sprintf(buffer, \"%20d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%20d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"               -1024\"));\r\n\r\n  test::sprintf(buffer, \"%20i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%20i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"               -1024\"));\r\n\r\n  test::sprintf(buffer, \"%20u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%20u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"          4294966272\"));\r\n\r\n  test::sprintf(buffer, \"%20o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"                 777\"));\r\n\r\n  test::sprintf(buffer, \"%20o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"         37777777001\"));\r\n\r\n  test::sprintf(buffer, \"%20x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"            1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%20x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"            edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%20X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"            1234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%20X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"            EDCB5433\"));\r\n\r\n  test::sprintf(buffer, \"%20c\", 'x');\r\n  REQUIRE(!strcmp(buffer, \"                   x\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"width *20\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%*s\", 20, \"Hello\");\r\n  REQUIRE(!strcmp(buffer, \"               Hello\"));\r\n\r\n  test::sprintf(buffer, \"%*d\", 20, 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%*d\", 20, -1024);\r\n  REQUIRE(!strcmp(buffer, \"               -1024\"));\r\n\r\n  test::sprintf(buffer, \"%*i\", 20, 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%*i\", 20, -1024);\r\n  REQUIRE(!strcmp(buffer, \"               -1024\"));\r\n\r\n  test::sprintf(buffer, \"%*u\", 20, 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%*u\", 20, 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"          4294966272\"));\r\n\r\n  test::sprintf(buffer, \"%*o\", 20, 511);\r\n  REQUIRE(!strcmp(buffer, \"                 777\"));\r\n\r\n  test::sprintf(buffer, \"%*o\", 20, 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"         37777777001\"));\r\n\r\n  test::sprintf(buffer, \"%*x\", 20, 305441741);\r\n  REQUIRE(!strcmp(buffer, \"            1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%*x\", 20, 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"            edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%*X\", 20, 305441741);\r\n  REQUIRE(!strcmp(buffer, \"            1234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%*X\", 20, 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"            EDCB5433\"));\r\n\r\n  test::sprintf(buffer, \"%*c\", 20,'x');\r\n  REQUIRE(!strcmp(buffer, \"                   x\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"width -20\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%-20s\", \"Hello\");\r\n  REQUIRE(!strcmp(buffer, \"Hello               \"));\r\n\r\n  test::sprintf(buffer, \"%-20d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024                \"));\r\n\r\n  test::sprintf(buffer, \"%-20d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024               \"));\r\n\r\n  test::sprintf(buffer, \"%-20i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024                \"));\r\n\r\n  test::sprintf(buffer, \"%-20i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024               \"));\r\n\r\n  test::sprintf(buffer, \"%-20u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024                \"));\r\n\r\n  test::sprintf(buffer, \"%-20.4f\", 1024.1234);\r\n  REQUIRE(!strcmp(buffer, \"1024.1234           \"));\r\n\r\n  test::sprintf(buffer, \"%-20u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"4294966272          \"));\r\n\r\n  test::sprintf(buffer, \"%-20o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"777                 \"));\r\n\r\n  test::sprintf(buffer, \"%-20o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"37777777001         \"));\r\n\r\n  test::sprintf(buffer, \"%-20x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234abcd            \"));\r\n\r\n  test::sprintf(buffer, \"%-20x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"edcb5433            \"));\r\n\r\n  test::sprintf(buffer, \"%-20X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234ABCD            \"));\r\n\r\n  test::sprintf(buffer, \"%-20X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"EDCB5433            \"));\r\n\r\n  test::sprintf(buffer, \"%-20c\", 'x');\r\n  REQUIRE(!strcmp(buffer, \"x                   \"));\r\n\r\n  test::sprintf(buffer, \"|%5d| |%-2d| |%5d|\", 9, 9, 9);\r\n  REQUIRE(!strcmp(buffer, \"|    9| |9 | |    9|\"));\r\n\r\n  test::sprintf(buffer, \"|%5d| |%-2d| |%5d|\", 10, 10, 10);\r\n  REQUIRE(!strcmp(buffer, \"|   10| |10| |   10|\"));\r\n\r\n  test::sprintf(buffer, \"|%5d| |%-12d| |%5d|\", 9, 9, 9);\r\n  REQUIRE(!strcmp(buffer, \"|    9| |9           | |    9|\"));\r\n\r\n  test::sprintf(buffer, \"|%5d| |%-12d| |%5d|\", 10, 10, 10);\r\n  REQUIRE(!strcmp(buffer, \"|   10| |10          | |   10|\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"width 0-20\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%0-20s\", \"Hello\");\r\n  REQUIRE(!strcmp(buffer, \"Hello               \"));\r\n\r\n  test::sprintf(buffer, \"%0-20d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024                \"));\r\n\r\n  test::sprintf(buffer, \"%0-20d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024               \"));\r\n\r\n  test::sprintf(buffer, \"%0-20i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024                \"));\r\n\r\n  test::sprintf(buffer, \"%0-20i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-1024               \"));\r\n\r\n  test::sprintf(buffer, \"%0-20u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"1024                \"));\r\n\r\n  test::sprintf(buffer, \"%0-20u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"4294966272          \"));\r\n\r\n  test::sprintf(buffer, \"%0-20o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"777                 \"));\r\n\r\n  test::sprintf(buffer, \"%0-20o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"37777777001         \"));\r\n\r\n  test::sprintf(buffer, \"%0-20x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234abcd            \"));\r\n\r\n  test::sprintf(buffer, \"%0-20x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"edcb5433            \"));\r\n\r\n  test::sprintf(buffer, \"%0-20X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"1234ABCD            \"));\r\n\r\n  test::sprintf(buffer, \"%0-20X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"EDCB5433            \"));\r\n\r\n  test::sprintf(buffer, \"%0-20c\", 'x');\r\n  REQUIRE(!strcmp(buffer, \"x                   \"));\r\n}\r\n\r\n\r\nTEST_CASE(\"padding 20\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%020d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%020d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-0000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%020i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%020i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-0000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%020u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%020u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"00000000004294966272\"));\r\n\r\n  test::sprintf(buffer, \"%020o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000000777\"));\r\n\r\n  test::sprintf(buffer, \"%020o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"00000000037777777001\"));\r\n\r\n  test::sprintf(buffer, \"%020x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"0000000000001234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%020x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"000000000000edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%020X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"0000000000001234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%020X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"000000000000EDCB5433\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"padding .20\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%.20d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%.20d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%.20i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%.20i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%.20u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%.20u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"00000000004294966272\"));\r\n\r\n  test::sprintf(buffer, \"%.20o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000000777\"));\r\n\r\n  test::sprintf(buffer, \"%.20o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"00000000037777777001\"));\r\n\r\n  test::sprintf(buffer, \"%.20x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"0000000000001234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%.20x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"000000000000edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%.20X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"0000000000001234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%.20X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"000000000000EDCB5433\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"padding #020\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%#020d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%#020d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-0000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%#020i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%#020i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"-0000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%#020u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000001024\"));\r\n\r\n  test::sprintf(buffer, \"%#020u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"00000000004294966272\"));\r\n\r\n  test::sprintf(buffer, \"%#020o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"00000000000000000777\"));\r\n\r\n  test::sprintf(buffer, \"%#020o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"00000000037777777001\"));\r\n\r\n  test::sprintf(buffer, \"%#020x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"0x00000000001234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%#020x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"0x0000000000edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%#020X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"0X00000000001234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%#020X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"0X0000000000EDCB5433\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"padding #20\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%#20d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%#20d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"               -1024\"));\r\n\r\n  test::sprintf(buffer, \"%#20i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%#20i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"               -1024\"));\r\n\r\n  test::sprintf(buffer, \"%#20u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%#20u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"          4294966272\"));\r\n\r\n  test::sprintf(buffer, \"%#20o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"                0777\"));\r\n\r\n  test::sprintf(buffer, \"%#20o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"        037777777001\"));\r\n\r\n  test::sprintf(buffer, \"%#20x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"          0x1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%#20x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"          0xedcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%#20X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"          0X1234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%#20X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"          0XEDCB5433\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"padding 20.5\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%20.5d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"               01024\"));\r\n\r\n  test::sprintf(buffer, \"%20.5d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"              -01024\"));\r\n\r\n  test::sprintf(buffer, \"%20.5i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"               01024\"));\r\n\r\n  test::sprintf(buffer, \"%20.5i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"              -01024\"));\r\n\r\n  test::sprintf(buffer, \"%20.5u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"               01024\"));\r\n\r\n  test::sprintf(buffer, \"%20.5u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"          4294966272\"));\r\n\r\n  test::sprintf(buffer, \"%20.5o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"               00777\"));\r\n\r\n  test::sprintf(buffer, \"%20.5o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"         37777777001\"));\r\n\r\n  test::sprintf(buffer, \"%20.5x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"            1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%20.10x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"          00edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%20.5X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"            1234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%20.10X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"          00EDCB5433\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"padding neg numbers\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  // space padding\r\n  test::sprintf(buffer, \"% 1d\", -5);\r\n  REQUIRE(!strcmp(buffer, \"-5\"));\r\n\r\n  test::sprintf(buffer, \"% 2d\", -5);\r\n  REQUIRE(!strcmp(buffer, \"-5\"));\r\n\r\n  test::sprintf(buffer, \"% 3d\", -5);\r\n  REQUIRE(!strcmp(buffer, \" -5\"));\r\n\r\n  test::sprintf(buffer, \"% 4d\", -5);\r\n  REQUIRE(!strcmp(buffer, \"  -5\"));\r\n\r\n  // zero padding\r\n  test::sprintf(buffer, \"%01d\", -5);\r\n  REQUIRE(!strcmp(buffer, \"-5\"));\r\n\r\n  test::sprintf(buffer, \"%02d\", -5);\r\n  REQUIRE(!strcmp(buffer, \"-5\"));\r\n\r\n  test::sprintf(buffer, \"%03d\", -5);\r\n  REQUIRE(!strcmp(buffer, \"-05\"));\r\n\r\n  test::sprintf(buffer, \"%04d\", -5);\r\n  REQUIRE(!strcmp(buffer, \"-005\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"float padding neg numbers\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  // space padding\r\n  test::sprintf(buffer, \"% 3.1f\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-5.0\"));\r\n\r\n  test::sprintf(buffer, \"% 4.1f\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-5.0\"));\r\n\r\n  test::sprintf(buffer, \"% 5.1f\", -5.);\r\n  REQUIRE(!strcmp(buffer, \" -5.0\"));\r\n\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n  test::sprintf(buffer, \"% 6.1g\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"    -5\"));\r\n\r\n  test::sprintf(buffer, \"% 6.1e\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-5.0e+00\"));\r\n\r\n  test::sprintf(buffer, \"% 10.1e\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"  -5.0e+00\"));\r\n#endif\r\n\r\n  // zero padding\r\n  test::sprintf(buffer, \"%03.1f\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-5.0\"));\r\n\r\n  test::sprintf(buffer, \"%04.1f\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-5.0\"));\r\n\r\n  test::sprintf(buffer, \"%05.1f\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-05.0\"));\r\n\r\n  // zero padding no decimal point\r\n  test::sprintf(buffer, \"%01.0f\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-5\"));\r\n\r\n  test::sprintf(buffer, \"%02.0f\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-5\"));\r\n\r\n  test::sprintf(buffer, \"%03.0f\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-05\"));\r\n\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n  test::sprintf(buffer, \"%010.1e\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-005.0e+00\"));\r\n\r\n  test::sprintf(buffer, \"%07.0E\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-05E+00\"));\r\n\r\n  test::sprintf(buffer, \"%03.0g\", -5.);\r\n  REQUIRE(!strcmp(buffer, \"-05\"));\r\n#endif\r\n}\r\n\r\nTEST_CASE(\"length\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%.0s\", \"Hello testing\");\r\n  REQUIRE(!strcmp(buffer, \"\"));\r\n\r\n  test::sprintf(buffer, \"%20.0s\", \"Hello testing\");\r\n  REQUIRE(!strcmp(buffer, \"                    \"));\r\n\r\n  test::sprintf(buffer, \"%.s\", \"Hello testing\");\r\n  REQUIRE(!strcmp(buffer, \"\"));\r\n\r\n  test::sprintf(buffer, \"%20.s\", \"Hello testing\");\r\n  REQUIRE(!strcmp(buffer, \"                    \"));\r\n\r\n  test::sprintf(buffer, \"%20.0d\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%20.0d\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"               -1024\"));\r\n\r\n  test::sprintf(buffer, \"%20.d\", 0);\r\n  REQUIRE(!strcmp(buffer, \"                    \"));\r\n\r\n  test::sprintf(buffer, \"%20.0i\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%20.i\", -1024);\r\n  REQUIRE(!strcmp(buffer, \"               -1024\"));\r\n\r\n  test::sprintf(buffer, \"%20.i\", 0);\r\n  REQUIRE(!strcmp(buffer, \"                    \"));\r\n\r\n  test::sprintf(buffer, \"%20.u\", 1024);\r\n  REQUIRE(!strcmp(buffer, \"                1024\"));\r\n\r\n  test::sprintf(buffer, \"%20.0u\", 4294966272U);\r\n  REQUIRE(!strcmp(buffer, \"          4294966272\"));\r\n\r\n  test::sprintf(buffer, \"%20.u\", 0U);\r\n  REQUIRE(!strcmp(buffer, \"                    \"));\r\n\r\n  test::sprintf(buffer, \"%20.o\", 511);\r\n  REQUIRE(!strcmp(buffer, \"                 777\"));\r\n\r\n  test::sprintf(buffer, \"%20.0o\", 4294966785U);\r\n  REQUIRE(!strcmp(buffer, \"         37777777001\"));\r\n\r\n  test::sprintf(buffer, \"%20.o\", 0U);\r\n  REQUIRE(!strcmp(buffer, \"                    \"));\r\n\r\n  test::sprintf(buffer, \"%20.x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"            1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%50.x\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"                                          1234abcd\"));\r\n\r\n  test::sprintf(buffer, \"%50.x%10.u\", 305441741, 12345);\r\n  REQUIRE(!strcmp(buffer, \"                                          1234abcd     12345\"));\r\n\r\n  test::sprintf(buffer, \"%20.0x\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"            edcb5433\"));\r\n\r\n  test::sprintf(buffer, \"%20.x\", 0U);\r\n  REQUIRE(!strcmp(buffer, \"                    \"));\r\n\r\n  test::sprintf(buffer, \"%20.X\", 305441741);\r\n  REQUIRE(!strcmp(buffer, \"            1234ABCD\"));\r\n\r\n  test::sprintf(buffer, \"%20.0X\", 3989525555U);\r\n  REQUIRE(!strcmp(buffer, \"            EDCB5433\"));\r\n\r\n  test::sprintf(buffer, \"%20.X\", 0U);\r\n  REQUIRE(!strcmp(buffer, \"                    \"));\r\n\r\n  test::sprintf(buffer, \"%02.0u\", 0U);\r\n  REQUIRE(!strcmp(buffer, \"  \"));\r\n\r\n  test::sprintf(buffer, \"%02.0d\", 0);\r\n  REQUIRE(!strcmp(buffer, \"  \"));\r\n}\r\n\r\n\r\nTEST_CASE(\"float\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  // test special-case floats using math.h macros\r\n  test::sprintf(buffer, \"%8f\", NAN);\r\n  REQUIRE(!strcmp(buffer, \"     nan\"));\r\n\r\n  test::sprintf(buffer, \"%8f\", INFINITY);\r\n  REQUIRE(!strcmp(buffer, \"     inf\"));\r\n\r\n  test::sprintf(buffer, \"%-8f\", -INFINITY);\r\n  REQUIRE(!strcmp(buffer, \"-inf    \"));\r\n\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n  test::sprintf(buffer, \"%+8e\", INFINITY);\r\n  REQUIRE(!strcmp(buffer, \"    +inf\"));\r\n#endif\r\n\r\n  test::sprintf(buffer, \"%.4f\", 3.1415354);\r\n  REQUIRE(!strcmp(buffer, \"3.1415\"));\r\n\r\n  test::sprintf(buffer, \"%.3f\", 30343.1415354);\r\n  REQUIRE(!strcmp(buffer, \"30343.142\"));\r\n\r\n  test::sprintf(buffer, \"%.0f\", 34.1415354);\r\n  REQUIRE(!strcmp(buffer, \"34\"));\r\n\r\n  test::sprintf(buffer, \"%.0f\", 1.3);\r\n  REQUIRE(!strcmp(buffer, \"1\"));\r\n\r\n  test::sprintf(buffer, \"%.0f\", 1.55);\r\n  REQUIRE(!strcmp(buffer, \"2\"));\r\n\r\n  test::sprintf(buffer, \"%.1f\", 1.64);\r\n  REQUIRE(!strcmp(buffer, \"1.6\"));\r\n\r\n  test::sprintf(buffer, \"%.2f\", 42.8952);\r\n  REQUIRE(!strcmp(buffer, \"42.90\"));\r\n\r\n  test::sprintf(buffer, \"%.9f\", 42.8952);\r\n  REQUIRE(!strcmp(buffer, \"42.895200000\"));\r\n\r\n  test::sprintf(buffer, \"%.10f\", 42.895223);\r\n  REQUIRE(!strcmp(buffer, \"42.8952230000\"));\r\n\r\n  // this testcase checks, that the precision is truncated to 9 digits.\r\n  // a perfect working float should return the whole number\r\n  test::sprintf(buffer, \"%.12f\", 42.89522312345678);\r\n  REQUIRE(!strcmp(buffer, \"42.895223123000\"));\r\n\r\n  // this testcase checks, that the precision is truncated AND rounded to 9 digits.\r\n  // a perfect working float should return the whole number\r\n  test::sprintf(buffer, \"%.12f\", 42.89522387654321);\r\n  REQUIRE(!strcmp(buffer, \"42.895223877000\"));\r\n\r\n  test::sprintf(buffer, \"%6.2f\", 42.8952);\r\n  REQUIRE(!strcmp(buffer, \" 42.90\"));\r\n\r\n  test::sprintf(buffer, \"%+6.2f\", 42.8952);\r\n  REQUIRE(!strcmp(buffer, \"+42.90\"));\r\n\r\n  test::sprintf(buffer, \"%+5.1f\", 42.9252);\r\n  REQUIRE(!strcmp(buffer, \"+42.9\"));\r\n\r\n  test::sprintf(buffer, \"%f\", 42.5);\r\n  REQUIRE(!strcmp(buffer, \"42.500000\"));\r\n\r\n  test::sprintf(buffer, \"%.1f\", 42.5);\r\n  REQUIRE(!strcmp(buffer, \"42.5\"));\r\n\r\n  test::sprintf(buffer, \"%f\", 42167.0);\r\n  REQUIRE(!strcmp(buffer, \"42167.000000\"));\r\n\r\n  test::sprintf(buffer, \"%.9f\", -12345.987654321);\r\n  REQUIRE(!strcmp(buffer, \"-12345.987654321\"));\r\n\r\n  test::sprintf(buffer, \"%.1f\", 3.999);\r\n  REQUIRE(!strcmp(buffer, \"4.0\"));\r\n\r\n  test::sprintf(buffer, \"%.0f\", 3.5);\r\n  REQUIRE(!strcmp(buffer, \"4\"));\r\n\r\n  test::sprintf(buffer, \"%.0f\", 4.5);\r\n  REQUIRE(!strcmp(buffer, \"4\"));\r\n\r\n  test::sprintf(buffer, \"%.0f\", 3.49);\r\n  REQUIRE(!strcmp(buffer, \"3\"));\r\n\r\n  test::sprintf(buffer, \"%.1f\", 3.49);\r\n  REQUIRE(!strcmp(buffer, \"3.5\"));\r\n\r\n  test::sprintf(buffer, \"a%-5.1f\", 0.5);\r\n  REQUIRE(!strcmp(buffer, \"a0.5  \"));\r\n\r\n  test::sprintf(buffer, \"a%-5.1fend\", 0.5);\r\n  REQUIRE(!strcmp(buffer, \"a0.5  end\"));\r\n\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n  test::sprintf(buffer, \"%G\", 12345.678);\r\n  REQUIRE(!strcmp(buffer, \"12345.7\"));\r\n\r\n  test::sprintf(buffer, \"%.7G\", 12345.678);\r\n  REQUIRE(!strcmp(buffer, \"12345.68\"));\r\n\r\n  test::sprintf(buffer, \"%.5G\", 123456789.);\r\n  REQUIRE(!strcmp(buffer, \"1.2346E+08\"));\r\n\r\n  test::sprintf(buffer, \"%.6G\", 12345.);\r\n  REQUIRE(!strcmp(buffer, \"12345.0\"));\r\n\r\n  test::sprintf(buffer, \"%+12.4g\", 123456789.);\r\n  REQUIRE(!strcmp(buffer, \"  +1.235e+08\"));\r\n\r\n  test::sprintf(buffer, \"%.2G\", 0.001234);\r\n  REQUIRE(!strcmp(buffer, \"0.0012\"));\r\n\r\n  test::sprintf(buffer, \"%+10.4G\", 0.001234);\r\n  REQUIRE(!strcmp(buffer, \" +0.001234\"));\r\n\r\n  test::sprintf(buffer, \"%+012.4g\", 0.00001234);\r\n  REQUIRE(!strcmp(buffer, \"+001.234e-05\"));\r\n\r\n  test::sprintf(buffer, \"%.3g\", -1.2345e-308);\r\n  REQUIRE(!strcmp(buffer, \"-1.23e-308\"));\r\n\r\n  test::sprintf(buffer, \"%+.3E\", 1.23e+308);\r\n  REQUIRE(!strcmp(buffer, \"+1.230E+308\"));\r\n#endif\r\n\r\n  // out of range for float: should switch to exp notation if supported, else empty\r\n  test::sprintf(buffer, \"%.1f\", 1E20);\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n  REQUIRE(!strcmp(buffer, \"1.0e+20\"));\r\n#else\r\n  REQUIRE(!strcmp(buffer, \"\"));\r\n#endif\r\n\r\n  // brute force float\r\n  bool fail = false;\r\n  std::stringstream str;\r\n  str.precision(5);\r\n  for (float i = -100000; i < 100000; i += 1) {\r\n    test::sprintf(buffer, \"%.5f\", i / 10000);\r\n    str.str(\"\");\r\n    str << std::fixed << i / 10000;\r\n    fail = fail || !!strcmp(buffer, str.str().c_str());\r\n  }\r\n  REQUIRE(!fail);\r\n\r\n\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n  // brute force exp\r\n  str.setf(std::ios::scientific, std::ios::floatfield);\r\n  for (float i = -1e20; i < 1e20; i += 1e15) {\r\n    test::sprintf(buffer, \"%.5f\", i);\r\n    str.str(\"\");\r\n    str << i;\r\n    fail = fail || !!strcmp(buffer, str.str().c_str());\r\n  }\r\n  REQUIRE(!fail);\r\n#endif\r\n}\r\n\r\n\r\nTEST_CASE(\"types\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%i\", 0);\r\n  REQUIRE(!strcmp(buffer, \"0\"));\r\n\r\n  test::sprintf(buffer, \"%i\", 1234);\r\n  REQUIRE(!strcmp(buffer, \"1234\"));\r\n\r\n  test::sprintf(buffer, \"%i\", 32767);\r\n  REQUIRE(!strcmp(buffer, \"32767\"));\r\n\r\n  test::sprintf(buffer, \"%i\", -32767);\r\n  REQUIRE(!strcmp(buffer, \"-32767\"));\r\n\r\n  test::sprintf(buffer, \"%li\", 30L);\r\n  REQUIRE(!strcmp(buffer, \"30\"));\r\n\r\n  test::sprintf(buffer, \"%li\", -2147483647L);\r\n  REQUIRE(!strcmp(buffer, \"-2147483647\"));\r\n\r\n  test::sprintf(buffer, \"%li\", 2147483647L);\r\n  REQUIRE(!strcmp(buffer, \"2147483647\"));\r\n\r\n  test::sprintf(buffer, \"%lli\", 30LL);\r\n  REQUIRE(!strcmp(buffer, \"30\"));\r\n\r\n  test::sprintf(buffer, \"%lli\", -9223372036854775807LL);\r\n  REQUIRE(!strcmp(buffer, \"-9223372036854775807\"));\r\n\r\n  test::sprintf(buffer, \"%lli\", 9223372036854775807LL);\r\n  REQUIRE(!strcmp(buffer, \"9223372036854775807\"));\r\n\r\n  test::sprintf(buffer, \"%lu\", 100000L);\r\n  REQUIRE(!strcmp(buffer, \"100000\"));\r\n\r\n  test::sprintf(buffer, \"%lu\", 0xFFFFFFFFL);\r\n  REQUIRE(!strcmp(buffer, \"4294967295\"));\r\n\r\n  test::sprintf(buffer, \"%llu\", 281474976710656LLU);\r\n  REQUIRE(!strcmp(buffer, \"281474976710656\"));\r\n\r\n  test::sprintf(buffer, \"%llu\", 18446744073709551615LLU);\r\n  REQUIRE(!strcmp(buffer, \"18446744073709551615\"));\r\n\r\n  test::sprintf(buffer, \"%zu\", 2147483647UL);\r\n  REQUIRE(!strcmp(buffer, \"2147483647\"));\r\n\r\n  test::sprintf(buffer, \"%zd\", 2147483647UL);\r\n  REQUIRE(!strcmp(buffer, \"2147483647\"));\r\n\r\n  if (sizeof(size_t) == sizeof(long)) {\r\n    test::sprintf(buffer, \"%zi\", -2147483647L);\r\n    REQUIRE(!strcmp(buffer, \"-2147483647\"));\r\n  }\r\n  else {\r\n    test::sprintf(buffer, \"%zi\", -2147483647LL);\r\n    REQUIRE(!strcmp(buffer, \"-2147483647\"));\r\n  }\r\n\r\n  test::sprintf(buffer, \"%b\", 60000);\r\n  REQUIRE(!strcmp(buffer, \"1110101001100000\"));\r\n\r\n  test::sprintf(buffer, \"%lb\", 12345678L);\r\n  REQUIRE(!strcmp(buffer, \"101111000110000101001110\"));\r\n\r\n  test::sprintf(buffer, \"%o\", 60000);\r\n  REQUIRE(!strcmp(buffer, \"165140\"));\r\n\r\n  test::sprintf(buffer, \"%lo\", 12345678L);\r\n  REQUIRE(!strcmp(buffer, \"57060516\"));\r\n\r\n  test::sprintf(buffer, \"%lx\", 0x12345678L);\r\n  REQUIRE(!strcmp(buffer, \"12345678\"));\r\n\r\n  test::sprintf(buffer, \"%llx\", 0x1234567891234567LLU);\r\n  REQUIRE(!strcmp(buffer, \"1234567891234567\"));\r\n\r\n  test::sprintf(buffer, \"%lx\", 0xabcdefabL);\r\n  REQUIRE(!strcmp(buffer, \"abcdefab\"));\r\n\r\n  test::sprintf(buffer, \"%lX\", 0xabcdefabL);\r\n  REQUIRE(!strcmp(buffer, \"ABCDEFAB\"));\r\n\r\n  test::sprintf(buffer, \"%c\", 'v');\r\n  REQUIRE(!strcmp(buffer, \"v\"));\r\n\r\n  test::sprintf(buffer, \"%cv\", 'w');\r\n  REQUIRE(!strcmp(buffer, \"wv\"));\r\n\r\n  test::sprintf(buffer, \"%s\", \"A Test\");\r\n  REQUIRE(!strcmp(buffer, \"A Test\"));\r\n\r\n  test::sprintf(buffer, \"%hhu\", 0xFFFFUL);\r\n  REQUIRE(!strcmp(buffer, \"255\"));\r\n\r\n  test::sprintf(buffer, \"%hu\", 0x123456UL);\r\n  REQUIRE(!strcmp(buffer, \"13398\"));\r\n\r\n  test::sprintf(buffer, \"%s%hhi %hu\", \"Test\", 10000, 0xFFFFFFFF);\r\n  REQUIRE(!strcmp(buffer, \"Test16 65535\"));\r\n\r\n  test::sprintf(buffer, \"%tx\", &buffer[10] - &buffer[0]);\r\n  REQUIRE(!strcmp(buffer, \"a\"));\r\n\r\n// TBD\r\n  if (sizeof(intmax_t) == sizeof(long)) {\r\n    test::sprintf(buffer, \"%ji\", -2147483647L);\r\n    REQUIRE(!strcmp(buffer, \"-2147483647\"));\r\n  }\r\n  else {\r\n    test::sprintf(buffer, \"%ji\", -2147483647LL);\r\n    REQUIRE(!strcmp(buffer, \"-2147483647\"));\r\n  }\r\n}\r\n\r\n\r\nTEST_CASE(\"pointer\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%p\", (void*)0x1234U);\r\n  if (sizeof(void*) == 4U) {\r\n    REQUIRE(!strcmp(buffer, \"00001234\"));\r\n  }\r\n  else {\r\n    REQUIRE(!strcmp(buffer, \"0000000000001234\"));\r\n  }\r\n\r\n  test::sprintf(buffer, \"%p\", (void*)0x12345678U);\r\n  if (sizeof(void*) == 4U) {\r\n    REQUIRE(!strcmp(buffer, \"12345678\"));\r\n  }\r\n  else {\r\n    REQUIRE(!strcmp(buffer, \"0000000012345678\"));\r\n  }\r\n\r\n  test::sprintf(buffer, \"%p-%p\", (void*)0x12345678U, (void*)0x7EDCBA98U);\r\n  if (sizeof(void*) == 4U) {\r\n    REQUIRE(!strcmp(buffer, \"12345678-7EDCBA98\"));\r\n  }\r\n  else {\r\n    REQUIRE(!strcmp(buffer, \"0000000012345678-000000007EDCBA98\"));\r\n  }\r\n\r\n  if (sizeof(uintptr_t) == sizeof(uint64_t)) {\r\n    test::sprintf(buffer, \"%p\", (void*)(uintptr_t)0xFFFFFFFFU);\r\n    REQUIRE(!strcmp(buffer, \"00000000FFFFFFFF\"));\r\n  }\r\n  else {\r\n    test::sprintf(buffer, \"%p\", (void*)(uintptr_t)0xFFFFFFFFU);\r\n    REQUIRE(!strcmp(buffer, \"FFFFFFFF\"));\r\n  }\r\n}\r\n\r\n\r\nTEST_CASE(\"unknown flag\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%kmarco\", 42, 37);\r\n  REQUIRE(!strcmp(buffer, \"kmarco\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"string length\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%.4s\", \"This is a test\");\r\n  REQUIRE(!strcmp(buffer, \"This\"));\r\n\r\n  test::sprintf(buffer, \"%.4s\", \"test\");\r\n  REQUIRE(!strcmp(buffer, \"test\"));\r\n\r\n  test::sprintf(buffer, \"%.7s\", \"123\");\r\n  REQUIRE(!strcmp(buffer, \"123\"));\r\n\r\n  test::sprintf(buffer, \"%.7s\", \"\");\r\n  REQUIRE(!strcmp(buffer, \"\"));\r\n\r\n  test::sprintf(buffer, \"%.4s%.2s\", \"123456\", \"abcdef\");\r\n  REQUIRE(!strcmp(buffer, \"1234ab\"));\r\n\r\n  test::sprintf(buffer, \"%.4.2s\", \"123456\");\r\n  REQUIRE(!strcmp(buffer, \".2s\"));\r\n\r\n  test::sprintf(buffer, \"%.*s\", 3, \"123456\");\r\n  REQUIRE(!strcmp(buffer, \"123\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"buffer length\", \"[]\" ) {\r\n  char buffer[100];\r\n  int ret;\r\n\r\n  ret = test::snprintf(nullptr, 10, \"%s\", \"Test\");\r\n  REQUIRE(ret == 4);\r\n  ret = test::snprintf(nullptr, 0, \"%s\", \"Test\");\r\n  REQUIRE(ret == 4);\r\n\r\n  buffer[0] = (char)0xA5;\r\n  ret = test::snprintf(buffer, 0, \"%s\", \"Test\");\r\n  REQUIRE(buffer[0] == (char)0xA5);\r\n  REQUIRE(ret == 4);\r\n\r\n  buffer[0] = (char)0xCC;\r\n  test::snprintf(buffer, 1, \"%s\", \"Test\");\r\n  REQUIRE(buffer[0] == '\\0');\r\n\r\n  test::snprintf(buffer, 2, \"%s\", \"Hello\");\r\n  REQUIRE(!strcmp(buffer, \"H\"));\r\n}\r\n\r\n\r\nTEST_CASE(\"ret value\", \"[]\" ) {\r\n  char buffer[100] ;\r\n  int ret;\r\n\r\n  ret = test::snprintf(buffer, 6, \"0%s\", \"1234\");\r\n  REQUIRE(!strcmp(buffer, \"01234\"));\r\n  REQUIRE(ret == 5);\r\n\r\n  ret = test::snprintf(buffer, 6, \"0%s\", \"12345\");\r\n  REQUIRE(!strcmp(buffer, \"01234\"));\r\n  REQUIRE(ret == 6);  // '5' is truncated\r\n\r\n  ret = test::snprintf(buffer, 6, \"0%s\", \"1234567\");\r\n  REQUIRE(!strcmp(buffer, \"01234\"));\r\n  REQUIRE(ret == 8);  // '567' are truncated\r\n\r\n  ret = test::snprintf(buffer, 10, \"hello, world\");\r\n  REQUIRE(ret == 12);\r\n\r\n  ret = test::snprintf(buffer, 3, \"%d\", 10000);\r\n  REQUIRE(ret == 5);\r\n  REQUIRE(strlen(buffer) == 2U);\r\n  REQUIRE(buffer[0] == '1');\r\n  REQUIRE(buffer[1] == '0');\r\n  REQUIRE(buffer[2] == '\\0');\r\n}\r\n\r\n\r\nTEST_CASE(\"misc\", \"[]\" ) {\r\n  char buffer[100];\r\n\r\n  test::sprintf(buffer, \"%u%u%ctest%d %s\", 5, 3000, 'a', -20, \"bit\");\r\n  REQUIRE(!strcmp(buffer, \"53000atest-20 bit\"));\r\n\r\n  test::sprintf(buffer, \"%.*f\", 2, 0.33333333);\r\n  REQUIRE(!strcmp(buffer, \"0.33\"));\r\n\r\n  test::sprintf(buffer, \"%.*d\", -1, 1);\r\n  REQUIRE(!strcmp(buffer, \"1\"));\r\n\r\n  test::sprintf(buffer, \"%.3s\", \"foobar\");\r\n  REQUIRE(!strcmp(buffer, \"foo\"));\r\n\r\n  test::sprintf(buffer, \"% .0d\", 0);\r\n  REQUIRE(!strcmp(buffer, \" \"));\r\n\r\n  test::sprintf(buffer, \"%10.5d\", 4);\r\n  REQUIRE(!strcmp(buffer, \"     00004\"));\r\n\r\n  test::sprintf(buffer, \"%*sx\", -3, \"hi\");\r\n  REQUIRE(!strcmp(buffer, \"hi x\"));\r\n\r\n#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n  test::sprintf(buffer, \"%.*g\", 2, 0.33333333);\r\n  REQUIRE(!strcmp(buffer, \"0.33\"));\r\n\r\n  test::sprintf(buffer, \"%.*e\", 2, 0.33333333);\r\n  REQUIRE(!strcmp(buffer, \"3.33e-01\"));\r\n#endif\r\n}\r\n"
  },
  {
    "path": "firmware.ld",
    "content": "ENTRY(HandlerReset)\r\n\r\n_estack = 0x20004000;    /* end of 16K RAM */\r\n\r\n_Min_Heap_Size = 0;      /* required amount of heap  */\r\n_Min_Stack_Size = 0x80;  /* required amount of stack */\r\n\r\nMEMORY\r\n{\r\n\tFLASH (rx)      : ORIGIN = 0x00000000, LENGTH = 60K\r\n\tRAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 16K\r\n}\r\n\r\nSECTIONS\r\n{\r\n\t/* Program code */\r\n\t.text :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\tKEEP(*(.text.isr)) /* .text sections of code  */\r\n\t\t*(.text)           /* .text sections of code  */\r\n\t\t*(.text*)          /* .text* sections of code */\r\n\t\t*(.rodata)         /* .rodata sections        */\r\n\t\t*(.rodata*)        /* .rodata* sections       */\r\n\t\t*(.glue_7)         /* Glue arm to thumb code  */\r\n\t\t*(.glue_7t)        /* Glue thumb to arm code  */\r\n\t\t*(.eh_frame)\r\n\r\n\t\tKEEP(*(.fini))\r\n\t\t. = ALIGN(4);\r\n\t\t_etext = .;        /* global symbols at end   */\r\n\t} >FLASH\r\n\r\n\t/* Used by startup code */\r\n\r\n\t. = ALIGN(4);\r\n\r\n\tflash_data_start = .;\r\n\r\n\t.data :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\tsram_data_start = .;\r\n\t\t*(.sramtext)\r\n\t\t*(.srambss)\r\n\t\t*(.data)           /* .data sections              */\r\n\t\t*(.data*)          /* .data* sections             */\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t_edata = .;        /* Global symbol at data end   */\r\n\t} >RAM AT> FLASH\r\n\r\n\tsram_data_end = .;\r\n\r\n\t/* Uninitialized data */\r\n\t. = ALIGN(4);\r\n\t.bss :\r\n\t{\r\n\t\t_sbss = .;         /* Global symbol at bss start */\r\n\t\t__bss_start__ = _sbss;\r\n\t\t*(.bss)\r\n\t\t*(.bss*)\r\n\t\t*(COMMON)\r\n\r\n\t\t. = ALIGN(4);\r\n\t\t_ebss = .;         /* Global symbol at bss end */\r\n\t\t__bss_end__ = _ebss;\r\n\t} >RAM\r\n\r\n\t/* Check that there is enough RAM */\r\n\t._user_heap_stack :\r\n\t{\r\n\t\t. = ALIGN(4);\r\n\t\t. = . + _Min_Heap_Size;\r\n\t\t. = . + _Min_Stack_Size;\r\n\t\t. = ALIGN(4);\r\n\t} >RAM\r\n}\r\n"
  },
  {
    "path": "font.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"font.h\"\r\n\r\nbool show_move_flag = false;\r\n#if  ENABLE_CHINESE_FULL == 4 && !defined(ENABLE_ENGLISH)\r\nbool audio_keep_flag=false;\r\n#endif\r\n#if  ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n\r\nconst uint8_t gFontBigDigits[11][20] =\r\n        {\r\n\r\n                {/*0x00, 0x00,*/ 0xFC, 0xFE, 0xFE, 0x06, 0x86, 0xC6, 0xE6, 0xFE, 0xFE, 0xFC, /*0x00,*/     /*0x00, 0x00,*/ 0x3F, 0x7F, 0x7F, 0x67, 0x63, 0x61, 0x60, 0x7F, 0x7F, 0x3F, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0x00, 0x00, 0x18, 0x1C, 0xFE, 0xFE, 0xFE, 0x00, 0x00, 0x00, /*0x00,*/     /*0x00, 0x00,*/ 0x00, 0x00, 0x60, 0x60, 0x7F, 0x7F, 0x7F, 0x60, 0x60, 0x00, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0x1C, 0x1E, 0x1E, 0x06, 0x06, 0x06, 0x86, 0xFE, 0xFE, 0x7C, /*0x00,*/     /*0x00, 0x00,*/ 0x60, 0x70, 0x78, 0x7C, 0x6E, 0x67, 0x63, 0x61, 0x60, 0x60, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0x0C, 0x0E, 0x0E, 0x86, 0x86, 0x86, 0x86, 0xFE, 0xFE, 0x7C, /*0x00,*/     /*0x00, 0x00,*/ 0x30, 0x70, 0x70, 0x61, 0x61, 0x61, 0x61, 0x7F, 0x7F, 0x3E, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0x80, 0xC0, 0xE0, 0x70, 0x38, 0x1C, 0x0E, 0xFE, 0xFE, 0xFE, /*0x00,*/     /*0x00, 0x00,*/ 0x0F, 0x0F, 0x0F, 0x0C, 0x0C, 0x0C, 0x0C, 0x7F, 0x7F, 0x7F, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0xFE, 0xFE, 0xFE, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x86, /*0x00,*/     /*0x00, 0x00,*/ 0x30, 0x70, 0x70, 0x60, 0x60, 0x60, 0x60, 0x7F, 0x7F, 0x3F, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0xF8, 0xFC, 0xFE, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x80, /*0x00,*/     /*0x00, 0x00,*/ 0x3F, 0x7F, 0x7F, 0x60, 0x60, 0x60, 0x60, 0x7F, 0x7F, 0x3F, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0x0E, 0x0E, 0x0E, 0x06, 0x06, 0x86, 0xE6, 0xFE, 0x7E, 0x1E, /*0x00,*/     /*0x00, 0x00,*/ 0x00, 0x00, 0x00, 0x00, 0x7C, 0x7F, 0x7F, 0x03, 0x00, 0x00, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0x7C, 0xFE, 0xFE, 0x86, 0x86, 0x86, 0x86, 0xFE, 0xFE, 0x7C, /*0x00,*/     /*0x00, 0x00,*/ 0x3F, 0x7F, 0x7F, 0x61, 0x61, 0x61, 0x61, 0x7F, 0x7F, 0x3F, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0xFC, 0xFE, 0xFE, 0x06, 0x06, 0x06, 0x06, 0xFE, 0xFE, 0xFC, /*0x00,*/     /*0x00, 0x00,*/ 0x01, 0x63, 0x63, 0x63, 0x63, 0x63, 0x63, 0x7F, 0x3F, 0x1F, /*0x00*/},\r\n                {/*0x00, 0x00,*/ 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, /*0x00,*/     /*0x00, 0x00,*/ 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, /*0x00*/}\r\n        };\r\n\r\n\r\nconst uint8_t gFontSmall[95 - 1][6] =\r\n        {\r\n//  {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},    // ' '\r\n                {0x00, 0x00, 0x5E, 0x00, 0x00, 0x00},    // '!'0\r\n                {0x00, 0x06, 0x00, 0x06, 0x00, 0x00},    // '\"'\r\n                {0x14, 0x3E, 0x14, 0x3E, 0x14, 0x00},    // '#'\r\n                {0x26, 0x49, 0x7F, 0x49, 0x32, 0x00},    // '$'\r\n                {0x63, 0x13, 0x08, 0x04, 0x62, 0x61},    // '%'0\r\n                {0x30, 0x4B, 0x4D, 0x55, 0x22, 0x50},    // '&'\r\n                {0x00, 0x00, 0x07, 0x07, 0x00, 0x00},    // '''\r\n                {0x00, 0x1C, 0x22, 0x41, 0x00, 0x00},    // '('\r\n                {0x00, 0x41, 0x22, 0x1C, 0x00, 0x00},    // ')'\r\n                {0x00, 0x2A, 0x1C, 0x1C, 0x2A, 0x00},    // '*'\r\n                {0x08, 0x08, 0x3E, 0x08, 0x08, 0x00},    // '+'0\r\n                {0x00, 0x40, 0x60, 0x20, 0x00, 0x00},    // ','\r\n                {0x00, 0x08, 0x08, 0x08, 0x08, 0x00},    // '-'0\r\n                {0x00, 0x00, 0x60, 0x60, 0x00, 0x00},    // '.'0\r\n                {0x40, 0x20, 0x10, 0x08, 0x04, 0x02},    // '/'0\r\n                {0x3E, 0x41, 0x41, 0x41, 0x41, 0x3E},    // '0'\r\n                {0x00, 0x40, 0x42, 0x7F, 0x40, 0x40},    // '1'\r\n                {0x62, 0x51, 0x51, 0x49, 0x49, 0x46},    // '2'\r\n                {0x22, 0x41, 0x49, 0x49, 0x49, 0x36},    // '3'\r\n                {0x18, 0x14, 0x12, 0x11, 0x7F, 0x10},    // '4'\r\n                {0x27, 0x45, 0x45, 0x45, 0x45, 0x39},    // '5'\r\n                {0x3E, 0x49, 0x49, 0x49, 0x49, 0x32},    // '6'\r\n                {0x01, 0x01, 0x71, 0x09, 0x05, 0x03},    // '7'\r\n                {0x36, 0x49, 0x49, 0x49, 0x49, 0x36},    // '8'\r\n                {0x46, 0x49, 0x49, 0x49, 0x29, 0x1E},    // '9'\r\n                {0x00, 0x00, 0x6C, 0x6C, 0x00, 0x00},    // ':'\r\n                {0x00, 0x40, 0x6C, 0x2C, 0x00, 0x00},    // ';'\r\n                {0x08, 0x14, 0x22, 0x41, 0x00, 0x00},    // '<'\r\n                {0x14, 0x14, 0x14, 0x14, 0x14, 0x00},    // '='\r\n                {0x00, 0x41, 0x22, 0x14, 0x08, 0x00},    // '>'\r\n                {0x02, 0x01, 0x51, 0x09, 0x06, 0x00},    // '?'\r\n                {0x30, 0x4A, 0x4A, 0x52, 0x3C, 0x00},    // '@'\r\n                {0x7E, 0x09, 0x09, 0x09, 0x09, 0x7E},    // 'A'\r\n                {0x7F, 0x49, 0x49, 0x49, 0x49, 0x36},    // 'B'\r\n                {0x3E, 0x41, 0x41, 0x41, 0x41, 0x22},    // 'C'\r\n                {0x7F, 0x41, 0x41, 0x41, 0x41, 0x3E},    // 'D'\r\n                {0x7F, 0x49, 0x49, 0x49, 0x49, 0x41},    // 'E'\r\n                {0x7F, 0x09, 0x09, 0x09, 0x09, 0x01},    // 'F'\r\n                {0x3E, 0x41, 0x49, 0x49, 0x49, 0x3A},    // 'G'\r\n                {0x7F, 0x08, 0x08, 0x08, 0x08, 0x7F},    // 'H'\r\n                {0x41, 0x41, 0x7F, 0x41, 0x41, 0x00},    // 'I'\r\n                {0x20, 0x41, 0x41, 0x3F, 0x01, 0x01},    // 'J'\r\n                {0x7F, 0x08, 0x0C, 0x12, 0x21, 0x40},    // 'K'\r\n                {0x7F, 0x40, 0x40, 0x40, 0x40, 0x40},    // 'L'\r\n                {0x7F, 0x02, 0x04, 0x04, 0x02, 0x7F},    // 'M'\r\n                {0x7F, 0x02, 0x04, 0x08, 0x10, 0x7F},    // 'N'\r\n                {0x3E, 0x41, 0x41, 0x41, 0x41, 0x3E},    // 'O'\r\n                {0x7F, 0x09, 0x09, 0x09, 0x09, 0x06},    // 'P'\r\n                {0x3E, 0x41, 0x51, 0x61, 0x41, 0x3E},    // 'Q'\r\n                {0x7F, 0x09, 0x09, 0x19, 0x29, 0x46},    // 'R'\r\n                {0x26, 0x49, 0x49, 0x49, 0x49, 0x32},    // 'S'\r\n                {0x01, 0x01, 0x7F, 0x01, 0x01, 0x00},    // 'T'\r\n                {0x3F, 0x40, 0x40, 0x40, 0x40, 0x3F},    // 'U'\r\n                {0x07, 0x38, 0x40, 0x40, 0x38, 0x07},    // 'V'\r\n                {0x3F, 0x40, 0x30, 0x30, 0x40, 0x3F},    // 'W'\r\n                {0x63, 0x14, 0x08, 0x08, 0x14, 0x63},    // 'X'\r\n                {0x07, 0x08, 0x70, 0x08, 0x07, 0x00},    // 'Y'\r\n                {0x61, 0x51, 0x49, 0x45, 0x43, 0x41},    // 'Z'\r\n                {0x00, 0x7F, 0x41, 0x41, 0x00, 0x00},    // '['\r\n                {0x01, 0x02, 0x04, 0x08, 0x10, 0x60},    // '\"\\'\r\n                {0x00, 0x00, 0x41, 0x41, 0x7F, 0x00},    // ']'\r\n                {0x04, 0x02, 0x01, 0x02, 0x04, 0x00},    // '^'\r\n                {0x40, 0x40, 0x40, 0x40, 0x40, 0x40},    // '_'\r\n                {0x00, 0x03, 0x07, 0x06, 0x00, 0x00},    // '`'\r\n                {0x20, 0x54, 0x54, 0x54, 0x78, 0x00},    // 'a'\r\n                {0x7F, 0x44, 0x44, 0x44, 0x38, 0x00},    // 'b'\r\n                {0x38, 0x44, 0x44, 0x44, 0x28, 0x00},    // 'c'\r\n                {0x38, 0x44, 0x44, 0x44, 0x7F, 0x00},    // 'd'\r\n                {0x38, 0x54, 0x54, 0x54, 0x48, 0x00},    // 'e'\r\n                {0x7C, 0x0A, 0x0A, 0x0A, 0x02, 0x00},    // 'f'\r\n                {0x58, 0x54, 0x54, 0x54, 0x3C, 0x00},    // 'g'\r\n                {0x7F, 0x04, 0x04, 0x04, 0x78, 0x00},    // 'h'\r\n                {0x00, 0x00, 0x7A, 0x00, 0x00, 0x00},    // 'i'\r\n                {0x20, 0x40, 0x40, 0x3D, 0x00, 0x00},    // 'j'\r\n                {0x00, 0x7F, 0x10, 0x28, 0x44, 0x00},    // 'k'\r\n                {0x00, 0x00, 0x3F, 0x40, 0x00, 0x00},    // 'l'\r\n                {0x7C, 0x08, 0x10, 0x10, 0x08, 0x7C},    // 'm'\r\n                {0x7C, 0x04, 0x04, 0x04, 0x78, 0x00},    // 'n'\r\n                {0x38, 0x44, 0x44, 0x44, 0x38, 0x00},    // 'o'\r\n                {0x7C, 0x14, 0x14, 0x14, 0x08, 0x00},    // 'p'\r\n                {0x08, 0x14, 0x14, 0x14, 0x7C, 0x40},    // 'q'\r\n                {0x7C, 0x04, 0x04, 0x04, 0x08, 0x00},    // 'r'\r\n                {0x08, 0x54, 0x54, 0x54, 0x20, 0x00},    // 's'\r\n                {0x3F, 0x44, 0x44, 0x44, 0x40, 0x00},    // 't'\r\n                {0x3C, 0x40, 0x40, 0x40, 0x3C, 0x00},    // 'u'\r\n                {0x0C, 0x30, 0x40, 0x30, 0x0C, 0x00},    // 'v'\r\n                {0x3C, 0x40, 0x30, 0x40, 0x3C, 0x00},    // 'w'\r\n                {0x44, 0x28, 0x10, 0x28, 0x44, 0x00},    // 'x'\r\n                {0x0C, 0x50, 0x50, 0x50, 0x3C, 0x00},    // 'y'\r\n                {0x44, 0x64, 0x54, 0x4C, 0x44, 0x00},    // 'z'\r\n                {0x08, 0x36, 0x41, 0x00, 0x00, 0x00},    // '{'\r\n                {0x00, 0x00, 0x7F, 0x00, 0x00, 0x00},    // '|'\r\n                {0x00, 0x00, 0x41, 0x36, 0x08, 0x00},    // '}'\r\n                {0x04, 0x02, 0x04, 0x08, 0x04, 0x00}     // '->'\r\n        };\r\n\r\n\r\nconst uint8_t gFont3x5[][3] =\r\n        {\r\n                {0x00, 0x00, 0x00}, //  32 - space\r\n                {0x00, 0x17, 0x00}, //  33 - exclam\r\n                {0x03, 0x00, 0x03}, //  34 - quotedbl\r\n                {0x1f, 0x0a, 0x1f}, //  35 - numbersign\r\n                {0x0a, 0x1f, 0x05}, //  36 - dollar\r\n                {0x09, 0x04, 0x12}, //  37 - percent\r\n                {0x0f, 0x17, 0x1c}, //  38 - ampersand\r\n                {0x00, 0x03, 0x00}, //  39 - quotesingle\r\n                {0x00, 0x0e, 0x11}, //  40 - parenleft\r\n                {0x11, 0x0e, 0x00}, //  41 - parenright\r\n                {0x05, 0x02, 0x05}, //  42 - asterisk\r\n                {0x04, 0x0e, 0x04}, //  43 - plus\r\n                {0x10, 0x08, 0x00}, //  44 - comma\r\n                {0x04, 0x04, 0x04}, //  45 - hyphen\r\n                {0x00, 0x10, 0x00}, //  46 - period\r\n                {0x18, 0x04, 0x03}, //  47 - slash\r\n                {0x1e, 0x11, 0x0f}, //  48 - zero\r\n                {0x02, 0x1f, 0x00}, //  49 - one\r\n                {0x19, 0x15, 0x12}, //  50 - two\r\n                {0x11, 0x15, 0x0a}, //  51 - three\r\n                {0x07, 0x04, 0x1f}, //  52 - four\r\n                {0x17, 0x15, 0x09}, //  53 - five\r\n                {0x1e, 0x15, 0x1d}, //  54 - six\r\n                {0x19, 0x05, 0x03}, //  55 - seven\r\n                {0x1f, 0x15, 0x1f}, //  56 - eight\r\n                {0x17, 0x15, 0x0f}, //  57 - nine\r\n                {0x00, 0x0a, 0x00}, //  58 - colon\r\n                {0x10, 0x0a, 0x00}, //  59 - semicolon\r\n                {0x04, 0x0a, 0x11}, //  60 - less\r\n                {0x0a, 0x0a, 0x0a}, //  61 - equal\r\n                {0x11, 0x0a, 0x04}, //  62 - greater\r\n                {0x01, 0x15, 0x03}, //  63 - question\r\n                {0x0e, 0x15, 0x16}, //  64 - at\r\n                {0x1e, 0x05, 0x1e}, //  65 - A\r\n                {0x1f, 0x15, 0x0a}, //  66 - B\r\n                {0x0e, 0x11, 0x11}, //  67 - C\r\n                {0x1f, 0x11, 0x0e}, //  68 - D\r\n                {0x1f, 0x15, 0x15}, //  69 - E\r\n                {0x1f, 0x05, 0x05}, //  70 - F\r\n                {0x0e, 0x15, 0x1d}, //  71 - G\r\n                {0x1f, 0x04, 0x1f}, //  72 - H\r\n                {0x11, 0x1f, 0x11}, //  73 - I\r\n                {0x08, 0x10, 0x0f}, //  74 - J\r\n                {0x1f, 0x04, 0x1b}, //  75 - K\r\n                {0x1f, 0x10, 0x10}, //  76 - L\r\n                {0x1f, 0x06, 0x1f}, //  77 - M\r\n                {0x1f, 0x0e, 0x1f}, //  78 - N\r\n                {0x0e, 0x11, 0x0e}, //  79 - O\r\n                {0x1f, 0x05, 0x02}, //  80 - P\r\n                {0x0e, 0x19, 0x1e}, //  81 - Q\r\n                {0x1f, 0x0d, 0x16}, //  82 - R\r\n                {0x12, 0x15, 0x09}, //  83 - S\r\n                {0x01, 0x1f, 0x01}, //  84 - T\r\n                {0x0f, 0x10, 0x1f}, //  85 - U\r\n                {0x07, 0x18, 0x07}, //  86 - V\r\n                {0x1f, 0x0c, 0x1f}, //  87 - W\r\n                {0x1b, 0x04, 0x1b}, //  88 - X\r\n                {0x03, 0x1c, 0x03}, //  89 - Y\r\n                {0x19, 0x15, 0x13}, //  90 - Z\r\n                {0x1f, 0x11, 0x11}, //  91 - bracketleft\r\n                {0x02, 0x04, 0x08}, //  92 - backslash\r\n                {0x11, 0x11, 0x1f}, //  93 - bracketright\r\n                {0x02, 0x01, 0x02}, //  94 - asciicircum\r\n                {0x10, 0x10, 0x10}, //  95 - underscore\r\n                {0x01, 0x02, 0x00}, //  96 - grave\r\n                {0x1a, 0x16, 0x1c}, //  97 - a\r\n                {0x1f, 0x12, 0x0c}, //  98 - b\r\n                {0x0c, 0x12, 0x12}, //  99 - c\r\n                {0x0c, 0x12, 0x1f}, // 100 - d\r\n                {0x0c, 0x1a, 0x16}, // 101 - e\r\n                {0x04, 0x1e, 0x05}, // 102 - f\r\n                {0x0c, 0x2a, 0x1e}, // 103 - g\r\n                {0x1f, 0x02, 0x1c}, // 104 - h\r\n                {0x00, 0x1d, 0x00}, // 105 - i\r\n                {0x10, 0x20, 0x1d}, // 106 - j\r\n                {0x1f, 0x0c, 0x12}, // 107 - k\r\n                {0x11, 0x1f, 0x10}, // 108 - l\r\n                {0x1e, 0x0e, 0x1e}, // 109 - m\r\n                {0x1e, 0x02, 0x1c}, // 110 - n\r\n                {0x0c, 0x12, 0x0c}, // 111 - o\r\n                {0x3e, 0x12, 0x0c}, // 112 - p\r\n                {0x0c, 0x12, 0x3e}, // 113 - q\r\n                {0x1c, 0x02, 0x02}, // 114 - r\r\n                {0x14, 0x1e, 0x0a}, // 115 - s\r\n                {0x02, 0x1f, 0x12}, // 116 - t\r\n                {0x0e, 0x10, 0x1e}, // 117 - u\r\n                {0x0e, 0x18, 0x0e}, // 118 - v\r\n                {0x1e, 0x1c, 0x1e}, // 119 - w\r\n                {0x12, 0x0c, 0x12}, // 120 - x\r\n                {0x06, 0x28, 0x1e}, // 121 - y\r\n                {0x1a, 0x1e, 0x16}, // 122 - z\r\n                {0x04, 0x1b, 0x11}, // 123 - braceleft\r\n                {0x00, 0x1b, 0x00}, // 124 - bar\r\n                {0x11, 0x1b, 0x04}, // 125 - braceright\r\n                {0x02, 0x03, 0x01}, // 126 - asciitilde\r\n                {0x12, 0x17, 0x12}, // 127 - plusminus\r\n\r\n        };\r\n\r\n#endif\r\n#if  ENABLE_CHINESE_FULL == 0\r\nconst uint8_t gFontChinese_out[2261] = {\r\n        0X20, 0X20, 0X3E, 0XA0, 0X20, 0XBF, 0X24,\r\n        0X24, 0X24, 0XA4, 0X20, 0XA0, 0X89,\r\n        0X74, 0X22, 0X01, 0X00, 0X11, 0X21,\r\n        0X0F, 0X44, 0XF4, 0X4F, 0X44, 0XF4,\r\n        0X4F, 0X04, 0X84, 0X34, 0XA4, 0X89,\r\n        0XB8, 0X88, 0X10, 0XDE, 0X10, 0XFF,\r\n        0X12, 0X92, 0XF9, 0X0D, 0XEB, 0X09,\r\n        0XF9, 0X89, 0X24, 0X01, 0X49, 0X43,\r\n        0X29, 0XA0, 0X28, 0XA5, 0X69, 0X3D,\r\n        0X2B, 0XAD, 0X28, 0XA5, 0X28, 0X20,\r\n        0X22, 0X22, 0X2F, 0X22, 0X22, 0X88,\r\n        0X88, 0XFF, 0X48, 0XA4, 0XAC, 0XB5,\r\n        0XE6, 0XB4, 0XAC, 0XA4, 0X80, 0X0F,\r\n        0XA8, 0X4B, 0XB4, 0XE8, 0X0F, 0X00,\r\n        0XF8, 0X0F, 0X02, 0XF1, 0X8E, 0X80,\r\n        0X88, 0X87, 0X30, 0X01, 0X8F, 0X24,\r\n        0X21, 0X84, 0X48, 0X2A, 0X98, 0X7F,\r\n        0X28, 0X4A, 0X10, 0XEF, 0X08, 0XF8,\r\n        0X08, 0XB9, 0X55, 0X0B, 0X58, 0X52,\r\n        0XC8, 0X40, 0X40, 0X42, 0X52, 0X62,\r\n        0X42, 0X4A, 0X46, 0X42, 0XC0, 0X10,\r\n        0X11, 0X99, 0X1F, 0X11, 0X11, 0X20,\r\n        0X42, 0X82, 0XFE, 0X02, 0X02, 0X02,\r\n        0XFE, 0X82, 0X42, 0X20, 0X88, 0XF8,\r\n        0X88, 0XF8, 0X88, 0X08, 0X21, 0X6D,\r\n        0XA5, 0X25, 0X35, 0X25, 0XA5, 0X65,\r\n        0X25, 0X0D, 0X01, 0X5F, 0X55, 0X55,\r\n        0X55, 0X0F, 0X88, 0X68, 0XFF, 0X48,\r\n        0X02, 0XFA, 0XAF, 0XAA, 0XAF, 0XFA,\r\n        0X02, 0X00, 0X0F, 0XAA, 0X36, 0XA6,\r\n        0X8A, 0XF8, 0X8F, 0X04, 0XE0, 0X0F,\r\n        0X20, 0XC8, 0X00, 0XFE, 0X01, 0X80,\r\n        0X0F, 0X30, 0X49, 0X03, 0XC3, 0X0E,\r\n        0X08, 0X88, 0X78, 0XCF, 0X48, 0X48,\r\n        0X49, 0XCA, 0X08, 0X08, 0X24, 0X89,\r\n        0X54, 0X52, 0X84, 0X18, 0X21, 0X0F,\r\n        0X84, 0X94, 0XA4, 0X84, 0XAF, 0X94,\r\n        0X84, 0X04, 0X84, 0X87, 0XAC, 0X89,\r\n        0XA9, 0X8C, 0X44, 0X54, 0X55, 0XD6,\r\n        0X74, 0X5C, 0X54, 0X56, 0X55, 0X54,\r\n        0X44, 0X24, 0X99, 0X99, 0X9F, 0X99,\r\n        0X48, 0X40, 0X40, 0XC0, 0X5F, 0X62,\r\n        0X42, 0X42, 0X42, 0X42, 0X4E, 0X80,\r\n        0X34, 0X00, 0X80, 0X88, 0X07, 0XFC,\r\n        0X04, 0X04, 0XE6, 0X25, 0X24, 0X24,\r\n        0XE4, 0X04, 0X04, 0XFC, 0X0F, 0X30,\r\n        0X22, 0X32, 0X88, 0X8F, 0X80, 0XF0,\r\n        0X8F, 0X80, 0X80, 0X0F, 0XC0, 0X4F,\r\n        0X40, 0XC0, 0X8F, 0X16, 0X88, 0X07,\r\n        0X4F, 0XF4, 0X46, 0X32, 0X82, 0XB2,\r\n        0X46, 0X6B, 0X52, 0X4A, 0X62, 0X12,\r\n        0X66, 0XE0, 0X88, 0XF8, 0X88, 0XE8,\r\n        0X10, 0X22, 0X0E, 0X00, 0XFC, 0X55,\r\n        0XF5, 0X5F, 0X55, 0XFD, 0X05, 0X8C,\r\n        0X87, 0X8B, 0X99, 0X99, 0XBA, 0X78,\r\n        0X00, 0XFF, 0X04, 0X08, 0XF8, 0X09,\r\n        0X0A, 0X08, 0X08, 0X08, 0X00, 0X0F,\r\n        0XF0, 0X88, 0X88, 0X20, 0XA1, 0XF4,\r\n        0XA7, 0X24, 0X05, 0X24, 0XA5, 0XF4,\r\n        0XA7, 0X24, 0X11, 0X59, 0X91, 0X1F,\r\n        0X51, 0X19, 0X00, 0XFE, 0X02, 0X42,\r\n        0X42, 0X42, 0XFA, 0X42, 0X42, 0X42,\r\n        0X02, 0X78, 0X88, 0X88, 0X8F, 0XA9,\r\n        0X88, 0X88, 0XF8, 0X8F, 0X04, 0XC0,\r\n        0X4F, 0X50, 0X60, 0X40, 0X40, 0X00,\r\n        0XF8, 0X80, 0X07, 0X00, 0X00, 0X84,\r\n        0X44, 0XF4, 0X0C, 0X87, 0X94, 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0XA9,\r\n        0X00, 0X28, 0XE7, 0X21, 0X21, 0XEF,\r\n        0X08, 0XF2, 0X01, 0X88, 0X25, 0X85,\r\n        0X88, 0X40, 0X3F, 0XA5, 0X6F, 0X05,\r\n        0X9F, 0X78, 0X16, 0X94, 0XFE, 0X84,\r\n        0X17, 0X97, 0X0F, 0X22, 0X2F, 0X94,\r\n        0XF3, 0X92, 0X00, 0XF2, 0X14, 0X10,\r\n        0XDF, 0X10, 0X14, 0XF2, 0XF0, 0X84,\r\n        0X49, 0X12, 0X42, 0X29, 0X42, 0X04,\r\n        0XC4, 0X0F, 0X02, 0XF1, 0X8F, 0X40,\r\n        0XC0, 0X0F, 0X40, 0X02, 0X87, 0XB8,\r\n        0X98, 0XC9, 0X11, 0XF2, 0X00, 0X00,\r\n        0XFF, 0X21, 0XA9, 0XBD, 0XA9, 0X21,\r\n        0XFF, 0X70, 0X82, 0X07, 0X23, 0X8B,\r\n        0X0F, 0X01, 0X01, 0X01, 0X01, 0XFD,\r\n        0X03, 0X0D, 0X01, 0X01, 0X01, 0X81,\r\n        0X48, 0X03, 0X00, 0X43, 0X88, 0X00,\r\n        0XC0, 0X30, 0X00, 0X00, 0XFF, 0X00,\r\n        0X00, 0X10, 0X60, 0X80, 0X01, 0X80,\r\n        0XF8, 0X00, 0X00, 0X01, 0X49, 0X65,\r\n        0X5B, 0XC9, 0X45, 0X45, 0X43, 0X69,\r\n        0X43, 0X05, 0X09, 0XAA, 0XAA, 0X59,\r\n     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0X01, 0X02, 0X48, 0X03, 0X88,\r\n        0X78, 0X00, 0X00, 0X88, 0X88, 0X88,\r\n        0X89, 0XFA, 0X88, 0X88, 0X88, 0X88,\r\n        0X00, 0X88, 0X88, 0XF8, 0X88, 0X88,\r\n        0X08, 0XE8, 0XBF, 0XAA, 0XEA, 0X0F,\r\n        0X80, 0X84, 0X88, 0XF0, 0X8F, 0X40,\r\n        0X12, 0XF8, 0X00, 0X89, 0X0F, 0X12,\r\n        0X62, 0X82, 0X62, 0X1E, 0X00, 0X1E,\r\n        0X62, 0X82, 0X62, 0X1E, 0X68, 0X61,\r\n        0X80, 0X24, 0X61, 0X18, 0XDC, 0X55,\r\n        0X55, 0X5D, 0XD5, 0X15, 0X0C, 0XC0,\r\n        0X0F, 0XF0, 0XFF, 0X55, 0X57, 0XF5,\r\n        0X10, 0XF8, 0X20, 0X20, 0XAF, 0X69,\r\n        0X29, 0X29, 0X29, 0X29, 0X2F, 0X20,\r\n        0X20, 0X00, 0X11, 0X11, 0X91, 0X79,\r\n        0X00, 0X00, 0XE0, 0X2F, 0X21, 0X29,\r\n        0X29, 0X19, 0X19, 0X19, 0X09, 0X89,\r\n        0X16, 0XF0, 0X44, 0X44, 0XF4, 0X20,\r\n        0X10, 0XFC, 0X03, 0X82, 0XBA, 0XAA,\r\n        0XAB, 0XAA, 0XBA, 0X82, 0X00, 0X0F,\r\n        0X21, 0XEA, 0X22, 0X01, 0X00, 0X80,\r\n        0X0F, 0X00, 0X00, 0XF0, 0X0F, 0X01,\r\n        0X01, 0X01, 0X80, 0XF8, 0X88, 0XF8,\r\n        0X88, 0X88, 0X12, 0XD2, 0XFE, 0X51,\r\n        0X90, 0XC8, 0X07, 0XF4, 0X04, 0X54,\r\n        0X8C, 0X01, 0X0F, 0X12, 0XF8, 0X00,\r\n        0X23, 0X20, 0X20, 0X28, 0X24, 0X22,\r\n        0XEF, 0X20, 0X22, 0X24, 0X28, 0X10,\r\n        0X01, 0X00, 0X0F, 0X00, 0X10, 0X04,\r\n        0X04, 0X84, 0X64, 0X14, 0XFF, 0X14,\r\n        0X64, 0X84, 0X04, 0X04, 0X12, 0X22,\r\n        0XF2, 0X22, 0X12, 0X02, 0X01, 0XF1,\r\n        0X0F, 0X01, 0XC2, 0X0F, 0XF1, 0X8F,\r\n        0X40, 0XC8, 0X4F, 0X34, 0X02, 0X87,\r\n        0X89, 0XE8, 0X98, 0XF7, 0X94, 0X84,\r\n        0X10, 0X48, 0X44, 0X53, 0X64, 0XC8,\r\n        0X10, 0XF0, 0X24, 0X00, 0X42, 0X0B,\r\n        0X00, 0XE0, 0X2F, 0X20, 0X20, 0X2F,\r\n        0X29, 0X29, 0X2F, 0X20, 0XE0, 0X0F,\r\n        0X4F, 0X44, 0X44, 0X44, 0XF4, 0X10,\r\n        0X10, 0X28, 0X24, 0X22, 0XE1, 0X22,\r\n        0X24, 0X28, 0X10, 0X10, 0X98, 0X99,\r\n        0XF9, 0X99, 0X99, 0X08, 0XA2, 0X2A,\r\n        0X3B, 0X2A, 0XAB, 0X0A, 0XE2, 0X2F,\r\n        0X20, 0XE3, 0X0C, 0X4F, 0X44, 0X0F,\r\n        0X2F, 0X12, 0X00, 0XFE, 0X92, 0X92,\r\n        0X92, 0XFE, 0X92, 0X92, 0X92, 0XFE,\r\n        0X00, 0X78, 0X00, 0X70, 0X80, 0XF8,\r\n        0X00, 0X02, 0XC1, 0X3F, 0XE0, 0X2F,\r\n        0X22, 0XE2, 0X1F, 0X12, 0X02, 0X02,\r\n        0XF0, 0X70, 0X52, 0X38, 0XF4, 0X20,\r\n        0X20, 0X20, 0XFF, 0X28, 0X28, 0XE4,\r\n        0X24, 0X22, 0X22, 0X20, 0X00, 0XF0,\r\n        0X24, 0X10, 0X42, 0X24, 0X28, 0XA8,\r\n        0XAB, 0XAA, 0XBA, 0XAA, 0XAA, 0XAA,\r\n        0X2B, 0X28, 0XF8, 0X00, 0XAE, 0XAA,\r\n        0X0E, 0XF8, 0X48, 0X47, 0XFC, 0X44,\r\n        0X02, 0X7A, 0X4A, 0X4A, 0X4A, 0X7A,\r\n        0X02, 0X68, 0X61, 0X98, 0X8A, 0X9A,\r\n        0X08, 0X28, 0X29, 0X29, 0X29, 0XE9,\r\n        0X1F, 0X19, 0X19, 0X19, 0X09, 0X08,\r\n        0X00, 0X88, 0X0F, 0X00, 0X00, 0X10,\r\n        0X10, 0XFF, 0X08, 0X08, 0X02, 0X02,\r\n        0XFE, 0X02, 0X02, 0XFE, 0X00, 0X27,\r\n        0X49, 0X03, 0X88, 0X87, 0X88, 0XF8,\r\n        0X8F, 0X84, 0X40, 0X3F, 0XA1, 0X6F,\r\n        0X01, 0X0F, 0X00, 0XF8, 0X90, 0X35,\r\n        0X31, 0X95, 0X04, 0X04, 0XFC, 0X04,\r\n        0X04, 0X08, 0XFF, 0X08, 0X08, 0X08,\r\n        0XF8, 0X22, 0X91, 0X35, 0X00, 0X88,\r\n        0X07, 0XE0, 0X09, 0X08, 0XF8, 0X0B,\r\n        0X89, 0X78, 0X48, 0X49, 0X4A, 0X80,\r\n        0X8F, 0XF8, 0XF8, 0X88, 0X8F, 0XFE,\r\n        0X02, 0X02, 0XFE, 0X00, 0XFE, 0X12,\r\n        0X12, 0XF1, 0X11, 0X10, 0X13, 0X31,\r\n        0X78, 0X00, 0X0F, 0X20, 0XA0, 0XAE,\r\n        0XA2, 0XA2, 0XF2, 0XAE, 0XA2, 0XA2,\r\n        0XA2, 0X2E, 0X80, 0X17, 0X11, 0X11,\r\n        0X11, 0X03, 0X88, 0XFF, 0X48, 0X00,\r\n        0X4C, 0XA4, 0X95, 0X86, 0X94, 0XA4,\r\n        0X4C, 0XF8, 0X00, 0X88, 0XF8, 0X88,\r\n        0X88, 0X88, 0XF6, 0X8F, 0X02, 0XE4,\r\n        0X2F, 0X20, 0XE0, 0X0F, 0X00, 0X00,\r\n        0XF0, 0X48, 0X03, 0X70, 0XE8, 0X2C,\r\n        0X24, 0XA4, 0X24, 0X25, 0XE6, 0X24,\r\n        0X24, 0X24, 0X24, 0X2C, 0X48, 0X43,\r\n        0XF8, 0X99, 0X99, 0X88, 0X61, 0X4D,\r\n        0XF5, 0X4F, 0X45, 0X0D, 0XC1, 0X0F,\r\n        0X00, 0XF0, 0X0F, 0X07, 0X4F, 0X07,\r\n        0X81, 0XF8, 0X06, 0XEA, 0X2A, 0X3E,\r\n        0X2A, 0XAB, 0X2A, 0X3E, 0X2A, 0XEA,\r\n        0X06, 0X98, 0X44, 0X12, 0X86, 0X98,\r\n        0X6C, 0XA8, 0X64, 0XA2, 0X23, 0X3E,\r\n        0X2A, 0X2A, 0X6A, 0XAA, 0X6A, 0X02,\r\n        0X00, 0XF0, 0X22, 0X22, 0X22, 0X32,\r\n        0X92, 0X97, 0X92, 0X92, 0XD7, 0X92,\r\n        0X92, 0X97, 0X92, 0X32, 0X70, 0X00,\r\n        0XF0, 0X00, 0X74, 0X00};\r\n#endif\r\n#if  ENABLE_CHINESE_FULL > 0\r\n#if  ENABLE_CHINESE_FULL ==1\r\nconst uint8_t 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X1C,0X86,0X62,0X4A,\r\n0XFA,0X4B,0X4A,0X0A,0XE2,0X2F,0X20,0XE3,0X0C,0X4F,0X44,0X0F,0X2F,0X12,0X9C,0X88,0XFF,0X48,0X20,0X9C,\r\n0X88,0XFF,0X88,0X88,0X00,0X00,0X0F,0X88,0XF8,0X88,0X08,0X11,0X21,0X0F,0X80,0X62,0X42,0XFE,0X43,0X4E,\r\n0X02,0X82,0X34,0XA4,0X89,0X98,0XBA,0X10,0X11,0XF2,0X00,0X10,0XD2,0X52,0X7E,0X51,0XD1,0X10,0X48,0X43,\r\n0XB8,0XAA,0XBA,0X28,0X21,0XED,0X1F,0X05,0XF8,0X0F,0X01,0XF1,0X0F,0XC1,0X10,0XF0,0X00,0X4F,0X72,0XE8,\r\n0X12,0XD2,0XFE,0X91,0X40,0X38,0X00,0XFF,0X00,0X04,0XB8,0X01,0X0F,0X88,0X44,0X12,0X80,0X84,0XA4,0XAA,\r\n0XA9,0XE8,0X9F,0X98,0X99,0X8A,0X84,0X04,0XF0,0XAA,0XAA,0XFA,0X00,0X12,0XD2,0XFE,0X51,0XF8,0X88,0X88,\r\n0XFF,0X88,0X88,0XF8,0X01,0X0F,0X01,0XF0,0X00,0X21,0X21,0XED,0X1F,0X05,0X88,0X87,0XF4,0X4F,0X44,0X04,\r\n0X1C,0XF0,0X40,0X12,0X0F,0X32,0X12,0XD2,0XFE,0X91,0X20,0X1C,0X80,0X7F,0X80,0X10,0X0C,0X01,0X0F,0X68,\r\n0X01,0X61,0X28,0X21,0XED,0X1F,0X05,0X29,0X41,0X02,0XF0,0X0F,0X08,0X18,0XF0,0X00,0X11,0XF1,0X00,0X08,\r\n0XFA,0XAA,0XAA,0XAA,0XFE,0XA9,0XA9,0XA9,0XF9,0X08,0XA8,0XAA,0XFA,0XAA,0XAA,0X48,0X20,0XD0,0X57,0X5D,\r\n0X55,0X55,0X55,0X55,0XD5,0X17,0X00,0X9A,0X5B,0X55,0XB5,0X89,0X84,0X93,0X96,0X9A,0X92,0XF0,0X94,0X93,\r\n0X96,0X9A,0X82,0X00,0X80,0XF8,0X00,0X00,0X80,0X40,0X32,0X62,0XA2,0X22,0X4E,0X32,0X62,0XA2,0X22,0X10,\r\n0X11,0X11,0X1F,0X11,0X11,0X04,0X13,0X16,0XFA,0X12,0X90,0X14,0X73,0X56,0XCA,0X02,0X48,0X83,0X48,0X25,\r\n0X85,0X48,0X30,0X61,0XAD,0X29,0X09,0X49,0X39,0X69,0XAF,0X28,0X28,0X22,0X22,0X22,0X82,0X78,0X10,0XFC,\r\n0X03,0X22,0XAA,0XFA,0XAF,0XAA,0XAA,0XEA,0XA2,0XF0,0X68,0X01,0X21,0XF8,0X00,0XE0,0XAF,0X92,0X0A,0X80,\r\n0X72,0X1E,0X12,0XF2,0X8E,0X20,0X1F,0X80,0X58,0X52,0X88,0X10,0XFC,0X03,0XCA,0X52,0X7E,0X42,0X42,0X7E,\r\n0X52,0X4A,0XF0,0X78,0X00,0X00,0X00,0X00,0XC1,0X3F,0X80,0X82,0X84,0XF8,0X8F,0X96,0XA8,0X84,0X02,0X0F,\r\n0X12,0XF8,0X10,0X42,0X20,0X10,0XFC,0X03,0XFA,0XAA,0XAA,0XFE,0XAA,0XAA,0XFA,0X00,0X0F,0X58,0X52,0X88,\r\n0X08,0XC1,0X3F,0X20,0X2F,0XE1,0X2F,0XE1,0X2F,0X21,0X2F,0X00,0X0F,0X1F,0X10,0X90,0X0F,0X20,0X10,0XFC,\r\n0X03,0XFA,0X8A,0XFA,0X02,0XFA,0X8A,0XFA,0X00,0X0F,0X0F,0X0F,0X0F,0X0F,0XE0,0XAB,0X9A,0X0A,0XFA,0X0F,\r\n0XAA,0XAA,0XEA,0X03,0X80,0X98,0X4A,0X44,0X9A,0X88,0X08,0X04,0XFE,0X05,0X04,0X84,0X5F,0X22,0X52,0X8B,\r\n0XE2,0XA8,0XAA,0XFA,0XAA,0XAA,0X88,0X40,0XEC,0X17,0X84,0X84,0XFC,0X84,0X54,0X65,0X4E,0X83,0X49,0X24,\r\n0X21,0X42,0X85,0X08,0X04,0XDE,0X81,0X88,0XC8,0X8F,0X88,0X95,0XA6,0X34,0X32,0X22,0XF2,0X22,0X22,0XE2,\r\n0X0F,0XC0,0X0F,0XF0,0X0F,0X90,0XDF,0XB0,0X9E,0X90,0X7F,0X30,0XF0,0X90,0X34,0X94,0X10,0XFC,0X03,0XF8,\r\n0X10,0X94,0X8B,0X4A,0X2A,0X96,0X10,0XF0,0X30,0XA8,0X9A,0X45,0X02,0XC1,0X3F,0X00,0X20,0X4F,0X05,0XF5,\r\n0X05,0X45,0X25,0X0F,0X0F,0XF0,0X11,0X11,0XF9,0X10,0XFC,0X83,0XA0,0XAF,0XA9,0XE9,0XA9,0XAF,0XA0,0X80,\r\n0XF0,0X80,0X24,0X21,0X84,0X08,0XC1,0X3F,0X00,0XF0,0X97,0X94,0XF4,0X9F,0X94,0XF4,0X07,0X0F,0X98,0X99,\r\n0X9F,0X99,0X20,0X10,0XFC,0X03,0X40,0X5E,0X52,0XF2,0X52,0X5E,0X40,0X00,0X0F,0X24,0XF1,0X21,0X04,0XC1,\r\n0X3F,0XE0,0XAB,0XAA,0XFA,0XAB,0XAA,0XEA,0X0B,0X08,0X0F,0X30,0X22,0XAA,0X06,0X10,0XFC,0X03,0X00,0XDF,\r\n0X11,0X11,0XF1,0X91,0X91,0X9F,0XF0,0X48,0X43,0XF8,0X88,0X08,0X02,0XC1,0X3F,0X29,0XE9,0X1F,0X05,0XF1,\r\n0X2F,0X49,0X05,0XF0,0X80,0X4F,0X32,0XE4,0X10,0XFC,0X03,0X10,0X92,0XFE,0X91,0X10,0XFC,0X00,0XFF,0XF0,\r\n0X10,0XF0,0X10,0X81,0X0F,0XC1,0XBF,0X44,0XBC,0XA7,0XA4,0XA6,0XA4,0XA4,0X2F,0X04,0X0F,0X23,0X32,0XAA,\r\n0X27,0X20,0X10,0XFC,0X03,0X10,0X28,0XA4,0X23,0X24,0XA8,0X10,0X00,0X0F,0XE9,0XB8,0XBC,0X08,0X02,0XC1,\r\n0X3F,0X40,0X24,0X1A,0XC9,0X18,0X29,0X4A,0X04,0XF0,0X00,0X4F,0X44,0X0F,0X20,0X10,0XFC,0X03,0X2A,0X32,\r\n0X26,0XAA,0X61,0X29,0X05,0X00,0X0F,0X11,0XF9,0X11,0X01,0XC1,0X3F,0X40,0X40,0X45,0X55,0X65,0X45,0X45,\r\n0X45,0X00,0X0F,0XF0,0X55,0X55,0X0F,0X00,0XBE,0XAA,0XAA,0XAB,0XAA,0XAA,0XAA,0XAA,0XBE,0X00,0X88,0XAA,\r\n0XFA,0XAA,0X8A,0X08,0XE8,0XAB,0XAA,0XBA,0XA2,0XAE,0XAA,0XA2,0XEA,0X07,0X40,0X24,0X81,0X0F,0X21,0X44,\r\n0XFC,0X26,0X25,0XFC,0X00,0XFE,0X12,0XF2,0X12,0X91,0X71,0X27,0XF2,0X34,0X58,0X52,0X08,0XC0,0X47,0X45,\r\n0X65,0XDD,0X47,0X45,0X45,0XCD,0X07,0X80,0X48,0X12,0XA7,0XAB,0XCB,0X10,0XFC,0X03,0XC0,0X51,0X55,0X55,\r\n0X55,0X55,0X5F,0XC0,0XF0,0X80,0XB9,0X55,0XB5,0X28,0XA8,0XAB,0XAA,0XAA,0XEA,0X9F,0X9A,0X9A,0X9A,0X1B,\r\n0XF8,0X20,0X22,0X23,0X62,0XF8,0X20,0X10,0XFC,0X03,0X48,0X3A,0X2A,0XEA,0X2E,0X28,0X08,0X00,0X0F,0X59,\r\n0X13,0X53,0X19,0X21,0X0F,0XC0,0X4F,0X65,0X55,0X45,0X45,0XC5,0X0D,0X80,0X87,0XAB,0XAA,0XAA,0X8B,0X20,\r\n0X10,0XFC,0X03,0XF0,0X51,0X55,0XF9,0X55,0X53,0XF0,0X00,0X0F,0X1F,0X71,0X91,0X0F,0X02,0XC1,0X3F,0X80,\r\n0XC4,0XA3,0X92,0X8E,0XC2,0X82,0X01,0XF0,0X90,0X35,0X31,0X95,0X20,0X10,0XFC,0X03,0X24,0X96,0X65,0X44,\r\n0X44,0XD6,0X2C,0X00,0X0F,0X89,0X25,0X85,0X08,0XE0,0XAF,0XA0,0XAE,0XAA,0XEA,0X9B,0X9A,0X9A,0X8E,0X80,\r\n0X07,0XAF,0XAA,0XAA,0X0F,0X11,0XF2,0X00,0XFE,0X12,0XD2,0X52,0X51,0X51,0XD1,0X10,0X78,0X9A,0XB8,0XAA,\r\n0XBA,0X88,0X44,0X22,0X9F,0X00,0X45,0X45,0XF5,0X45,0X4F,0X05,0X05,0XF0,0X00,0XA1,0XF8,0X00,0X48,0X24,\r\n0XF2,0X09,0XFE,0X02,0XF2,0X92,0XF2,0X02,0XFE,0X00,0X0F,0X4F,0X44,0X44,0X8F,0X44,0X22,0X9F,0X40,0XB0,\r\n0XAF,0XA4,0XA4,0X2F,0XE0,0X0F,0XF0,0X00,0X27,0XB2,0X78,0X48,0X24,0XF2,0X09,0X00,0X25,0X26,0XFC,0X26,\r\n0X25,0X00,0X00,0X0F,0X11,0XF1,0X11,0X41,0X24,0X12,0X8F,0X00,0X11,0X22,0X00,0X20,0X21,0X2F,0X01,0XF0,\r\n0X40,0X12,0X80,0X0F,0X24,0XF2,0X09,0X08,0XAA,0XAA,0XFF,0XAA,0XAA,0XBE,0X08,0XF0,0X20,0X22,0X2F,0X22,\r\n0X82,0X44,0X22,0X9F,0X00,0XF0,0X9F,0X94,0X9C,0XF4,0X07,0X08,0XF0,0X00,0X4F,0X21,0X85,0X44,0X22,0X11,\r\n0X00,0XF9,0X09,0X0D,0XEB,0X09,0X09,0XF9,0X24,0X81,0X49,0X12,0X42,0X09,0XE4,0XBF,0X24,0XE5,0X0F,0X80,\r\n0X0F,0XF0,0X0F,0X80,0X8F,0X17,0XFA,0X70,0X74,0XF4,0X40,0XFE,0X4B,0X52,0XFE,0X00,0X38,0XC1,0X06,0XC0,\r\n0X3C,0X78,0XA1,0X0F,0X48,0X43,0X88,0X40,0XA4,0X94,0XAF,0X44,0X24,0XE0,0X27,0X28,0XE6,0X21,0X81,0X1F,\r\n0X82,0X16,0X86,0X08,0XE8,0XA4,0XAC,0XAA,0XE9,0X0A,0XCC,0X04,0XE8,0X08,0XF0,0X22,0XFA,0X30,0XF8,0X80,\r\n0X80,0X40,0XCE,0XAA,0X9A,0XAA,0XCA,0X4A,0X8E,0X80,0X20,0XA2,0X27,0X22,0X2F,0X22,0X90,0XD5,0XBA,0XD2,\r\n0X92,0X95,0X90,0X00,0XFE,0X32,0XCE,0X70,0XF0,0X40,0X07,0X2F,0X01,0X02,0X89,0X42,0X36,0X4A,0X82,0X0A,\r\n0XC1,0X0F,0XF0,0X8F,0XB8,0X58,0X56,0X10,0XF8,0X11,0XF2,0X00,0X44,0X28,0XFF,0X00,0XFF,0X28,0X44,0X00,\r\n0X78,0XA8,0X89,0X98,0XAA,0X0B,0X82,0X71,0X8C,0X00,0XE1,0X2F,0X29,0X29,0XE9,0X0F,0X40,0X03,0XA1,0X8F,\r\n0X88,0X8F,0X44,0XA2,0X91,0X8C,0X91,0XA2,0X44,0XFE,0X02,0X02,0XFE,0XF0,0X44,0XF4,0XF0,0X20,0X03,0X24,\r\n0X65,0XA5,0X2D,0X67,0X95,0X15,0X95,0X55,0X05,0X44,0X92,0XB9,0X55,0XB5,0X88,0X2A,0X32,0X26,0XAA,0X61,\r\n0X29,0X05,0XFE,0X02,0X32,0XCE,0X22,0XFA,0X11,0XF1,0X22,0X81,0X80,0X40,0X4F,0X25,0X95,0X25,0X45,0X45,\r\n0X8F,0X80,0X00,0XF0,0X59,0X31,0X55,0X1A,0X48,0X44,0X53,0X64,0XC8,0X00,0XE2,0X9E,0XF2,0X02,0X00,0X20,\r\n0XB4,0X00,0X8F,0X87,0X8E,0X40,0XA4,0X94,0X82,0X81,0X80,0X94,0XA4,0X43,0X80,0X80,0X9F,0XF9,0XF9,0X99,\r\n0X8F,0X00,0XFE,0X92,0XFE,0X80,0X42,0X22,0XFA,0X06,0X22,0XC2,0X78,0XF8,0X80,0XB8,0X88,0X08,0XE0,0X2F,\r\n0XE9,0X8F,0X80,0XF0,0X8F,0X90,0XAF,0X88,0X84,0X87,0X4F,0X43,0X72,0XE8,0X00,0XFE,0X92,0XFE,0X04,0X64,\r\n0X5C,0XF7,0X44,0X44,0X44,0X78,0XF8,0X34,0XF8,0X10,0X06,0XE0,0X2F,0X29,0XE9,0X0F,0X02,0XF2,0X4F,0X4A,\r\n0X42,0X82,0X07,0XF8,0X00,0X0F,0X21,0X00,0XFE,0X92,0X92,0XFE,0X00,0XF0,0X90,0X9F,0X92,0XF2,0X78,0X80,\r\n0X8F,0X07,0X00,0X01,0XE0,0X2F,0X29,0XE9,0X0F,0XE0,0X2F,0X21,0X21,0XE1,0X8F,0X07,0XF8,0X90,0X99,0X99,\r\n0X00,0XFE,0X92,0X92,0XFE,0X00,0XFE,0X92,0XFE,0X92,0XFE,0X78,0X80,0X0F,0X01,0X0F,0X01,0XE0,0X2F,0X29,\r\n0XE9,0X0F,0XC0,0X4F,0XF2,0X4F,0XC2,0X8F,0X07,0XF8,0X30,0XF1,0X31,0X00,0XFE,0X92,0XFE,0X20,0X9C,0X88,\r\n0XFF,0X88,0X88,0X00,0X78,0XF8,0X88,0XF8,0X88,0X08,0XE0,0X2F,0XE9,0X8F,0X70,0XC0,0X4F,0X42,0X42,0X42,\r\n0X80,0X87,0X0F,0XF0,0X11,0X11,0X00,0XFE,0X92,0XFE,0X00,0XFE,0X02,0XFE,0X02,0XFD,0X01,0X78,0XF8,0X78,\r\n0XF0,0XCA,0X03,0XE0,0X2F,0XE9,0X0F,0X81,0X44,0X32,0X49,0X84,0X00,0X89,0X87,0X8F,0X59,0X24,0X01,0X00,\r\n0XFE,0X92,0XFE,0X00,0XFE,0X22,0X22,0XFE,0X21,0X21,0X78,0XF8,0XF0,0X84,0X43,0X0E,0XE0,0X2F,0X29,0XE9,\r\n0X0F,0X81,0X7E,0X42,0X4E,0XC0,0X8F,0X07,0XF8,0X30,0X91,0X78,0X00,0XFE,0X92,0XFE,0X08,0XF4,0X97,};\r\n#elif  ENABLE_CHINESE_FULL ==2\r\nconst uint8_t gFontChinese_out2[40960]={\r\n        0X94,\r\n        0XF4,0X04,0XFC,0X78,0XF8,0X70,0X88,0X98,0X0D,0XF0,0X9F,0XF4,0X2F,0X48,0X09,0XF9,0X0F,0X49,0X29,0X88,\r\n        0X87,0X0F,0X00,0X0F,0X00,0X00,0XFE,0X92,0XFE,0X20,0XE9,0X09,0XFA,0X62,0X90,0X08,0X78,0XF8,0X12,0XF8,\r\n        0X10,0X02,0XE0,0X2F,0XE9,0X0F,0X24,0X2A,0XA9,0X68,0X29,0X0A,0X84,0X87,0X8F,0X88,0X8F,0X88,0X00,0XFE,\r\n        0X92,0XFE,0X00,0XD8,0X54,0X53,0X50,0XD8,0X30,0X78,0XF8,0XF0,0X44,0XF4,0X00,0XF0,0X41,0X2A,0X82,0X03,\r\n        0XE0,0XBF,0X28,0XEA,0X0B,0X18,0XF1,0X11,0X20,0XA2,0X78,0X0C,0XEB,0XAA,0XAA,0XFE,0XAA,0XAA,0XEE,0X0A,\r\n        0X02,0XFE,0XF0,0X22,0X27,0XFA,0X80,0X8F,0X40,0X3F,0XA9,0X6F,0X09,0X8F,0XF0,0X8F,0X80,0X0F,0X80,0X24,\r\n        0X61,0XA8,0XA9,0XCB,0X8A,0X44,0XFB,0X00,0X88,0XE8,0X88,0XFF,0X08,0XE9,0X0A,0X88,0X87,0X34,0X48,0X43,\r\n        0XAE,0X48,0XB4,0X0F,0X40,0X49,0X4A,0XF8,0X4F,0X48,0X4A,0X89,0X78,0X80,0X24,0X21,0X84,0X8A,0X44,0XFB,\r\n        0X00,0XFF,0X00,0XF2,0X12,0XFE,0X12,0XF2,0X88,0X87,0X07,0X03,0X2F,0XA3,0X48,0XB4,0X0F,0X80,0X8F,0X88,\r\n        0XF8,0X8F,0X88,0X88,0X8F,0X78,0X80,0X88,0X4F,0XE4,0X8A,0X44,0XFB,0X00,0X88,0X94,0X92,0X91,0X92,0X94,\r\n        0X88,0X88,0X07,0X64,0X45,0X64,0XAC,0X48,0XB4,0X8F,0X44,0X35,0X25,0XAF,0X65,0X05,0X0F,0X84,0X78,0X90,\r\n        0XF9,0X11,0X03,0X10,0X8A,0X44,0XFB,0X44,0X24,0XD5,0X06,0XD4,0X24,0X44,0X81,0X78,0X88,0X25,0X85,0X08,\r\n        0XE0,0X2F,0X21,0X2E,0XE1,0X0F,0X00,0XFE,0X43,0X4E,0X80,0X17,0X10,0X87,0XAB,0XCB,0XFE,0X12,0XE2,0X12,\r\n        0XFE,0X04,0XFB,0X2A,0X3A,0X42,0X7E,0X17,0X10,0X87,0XA9,0XAA,0XAF,0X48,0XB4,0X0F,0XC0,0X42,0X5A,0X62,\r\n        0X42,0X4F,0XC2,0X82,0X78,0X00,0X90,0XF8,0X00,0X8A,0X44,0XFB,0X10,0XF1,0X02,0X10,0X10,0XFF,0X12,0X14,\r\n        0X88,0X07,0X27,0X78,0X70,0X08,0XA1,0X48,0XB4,0X0F,0XF0,0X9F,0X94,0X9C,0XF4,0X07,0X18,0X88,0X07,0X4F,\r\n        0X21,0X85,0X8A,0X44,0XFB,0X42,0XFA,0XA6,0X70,0X00,0XFF,0X10,0XE0,0X88,0X87,0X0F,0X80,0X0F,0X40,0XB0,\r\n        0XAA,0XAA,0XEA,0XAA,0XAA,0XAA,0XAA,0X20,0XE0,0X0F,0XAE,0XAA,0XAA,0X0E,0XF8,0X08,0XFF,0X08,0XF8,0X02,\r\n        0XAA,0XAA,0XAB,0XAA,0XAA,0X02,0X78,0X70,0XB8,0XAA,0XBA,0X0C,0X11,0X21,0X0F,0X40,0X61,0XB5,0XA4,0XAE,\r\n        0X64,0X05,0X81,0X34,0XB4,0XAA,0XAF,0XAA,0X48,0X44,0XAB,0X92,0XAA,0XA6,0XA0,0XBF,0XA0,0XA2,0X2C,0X00,\r\n        0XAF,0XAA,0XAA,0XFA,0XE0,0X21,0X6D,0X95,0X14,0X05,0X2C,0XE5,0X24,0X24,0XED,0X81,0X49,0X24,0X21,0X42,\r\n        0X85,0X90,0X88,0X57,0X24,0X1C,0X00,0X7E,0X82,0X92,0X9E,0XC0,0X68,0X60,0X98,0X8A,0X2C,0X8C,0X40,0XB8,\r\n        0XAA,0XAA,0XAA,0XAA,0XEA,0X8A,0X8A,0X0F,0X80,0X06,0X86,0XA9,0XC8,0XC2,0X08,0XE7,0X14,0X0C,0X02,0XFE,\r\n        0X52,0X52,0X52,0XFE,0X02,0X70,0X12,0X32,0X22,0XF2,0X81,0X70,0X4E,0XC1,0X00,0X48,0XFA,0X2A,0XA9,0X2A,\r\n        0X8A,0X0B,0X4F,0X82,0X34,0X70,0XC8,0X08,0XE7,0X14,0X0C,0XF8,0X88,0X88,0XFF,0X88,0X88,0XF8,0XF0,0X24,\r\n        0X88,0XF8,0X44,0X8E,0X70,0XCE,0X00,0XC0,0X4F,0X60,0X5E,0X42,0X4E,0XC0,0X0F,0X4F,0XF0,0X10,0X11,0XF8,\r\n        0X08,0XE7,0X14,0X0C,0X10,0XA8,0XA4,0XA3,0XA4,0XA8,0X10,0XF0,0X24,0XF0,0X44,0XF4,0X80,0X70,0X4E,0XC1,\r\n        0X80,0X44,0XBC,0X2A,0XA9,0X6A,0X0C,0X04,0X4F,0X02,0X4F,0X44,0X0F,0X08,0XE7,0X14,0X0C,0X40,0X24,0XD5,\r\n        0X06,0XD4,0X24,0X44,0XF0,0X24,0X88,0X25,0X85,0X88,0X70,0XCE,0X00,0X48,0X44,0X5E,0XE1,0X46,0X48,0X44,\r\n        0X02,0X4F,0X00,0X4F,0X10,0X42,0X00,0XFF,0X00,0XD6,0X5D,0X54,0XDA,0X00,0XFF,0X00,0X00,0X78,0XF0,0XD5,\r\n        0X0F,0X87,0X8E,0X70,0X4E,0XC1,0X00,0X98,0XA8,0X8F,0X88,0XA8,0X9F,0X08,0X4F,0X02,0X78,0X00,0X0F,0X44,\r\n        0X34,0X04,0X7C,0X05,0X86,0X04,0X7C,0X04,0X14,0X64,0XF0,0X88,0XF8,0X88,0XF8,0X20,0XA1,0X2A,0XEA,0X2B,\r\n        0X3A,0X2A,0XEA,0X2B,0XAA,0X2E,0X01,0X23,0X22,0X22,0XA2,0X6A,0X12,0X0A,0X42,0X5E,0X42,0X43,0XC2,0X5E,\r\n        0X02,0X0A,0X12,0X22,0XA2,0XFA,0X22,0X22,0X42,0X4A,0X49,0XC8,0X5B,0X6C,0X48,0XC8,0X4B,0X48,0X49,0X8A,\r\n        0XA8,0X4B,0X44,0X9A,0X08,0X04,0X88,0XFF,0X40,0X48,0X64,0X6B,0X52,0X4A,0XE6,0X40,0X01,0X0F,0X10,0X82,\r\n        0XF8,0X20,0X42,0X01,0XF0,0X07,0X80,0X48,0XB4,0X22,0XA1,0X60,0X90,0X59,0X35,0X31,0X55,0X99,0X04,0X74,\r\n        0X54,0X54,0XD5,0XD6,0X54,0X54,0X54,0X74,0X04,0X44,0XF2,0X48,0X21,0XA4,0X29,0X28,0XA8,0XAB,0XAA,0XBA,\r\n        0XAA,0XAA,0XAA,0X2B,0X28,0X18,0X22,0XAA,0X2E,0X22,0X12,0X82,0X82,0XBA,0XAA,0XAA,0XAB,0XAA,0XAA,0XBA,\r\n        0X82,0X82,0X89,0X26,0X22,0X62,0X88,0X0D,0XE0,0X2F,0X28,0XAA,0XAA,0XBA,0XEA,0XAB,0XAE,0X2A,0X8A,0X07,\r\n        0X10,0X82,0XF8,0X00,0X00,0XFE,0X0A,0X8A,0XBE,0XAA,0XAB,0XAA,0XBE,0X8A,0X0A,0X78,0X80,0XA9,0X44,0X9A,\r\n        0X28,0XA1,0X20,0XE2,0X29,0X30,0X20,0XE2,0X2B,0XA0,0X20,0X11,0X59,0X13,0X11,0X1F,0X11,0X24,0X14,0X44,\r\n        0X3C,0X05,0X86,0X44,0X7C,0X04,0X14,0X24,0X99,0X55,0X13,0X53,0X95,0X19,0X21,0X0F,0X48,0X46,0XC0,0X5F,\r\n        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0XD5,0X95,0X9D,0XB5,0XD7,0X60,0X44,0X22,0XF0,0XAA,0XFA,0XA0,0X27,0XE4,0X07,0XAC,0X24,0XE3,0X04,0XFC,\r\n        0X24,0X93,0X24,0X9A,0X97,0X35,0X31,0X95,0X7A,0X42,0X7E,0XC0,0X22,0XAE,0X92,0XD6,0X92,0XAA,0X26,0XA2,\r\n        0X79,0XB8,0XFA,0XBA,0XCC,0X3D,0X8B,0X08,0XC0,0XBA,0XA6,0XAA,0XA2,0X63,0X0A,0X42,0X24,0XA8,0XA5,0X1F,\r\n        0X86,0XCC,0XAB,0X98,0XCC,0X08,0XF4,0X52,0X59,0X52,0XF4,0X08,0X48,0X12,0XF0,0X15,0X53,0X4A,0X44,0XF5,\r\n        0X4F,0X05,0X20,0X7B,0X29,0X2D,0X79,0X29,0X2B,0XF1,0X01,0X48,0X83,0X78,0X11,0X95,0X1F,0X15,0X51,0X80,\r\n        0X11,0X95,0X1F,0X95,0X11,0X92,0X78,0XAC,0X89,0X0E,0X23,0XE2,0X2F,0X02,0X40,0XFE,0X43,0X0E,0XE0,0X2F,\r\n        0XE9,0X4F,0X27,0X70,0X32,0X78,0XF8,0X90,0X12,0XF2,0X90,0XFF,0X12,0X14,0XFE,0X8B,0XA2,0XBE,0X8F,0X47,\r\n        0X43,0X2E,0XAA,0X27,0X22,0XE2,0X2F,0X72,0X10,0X5F,0X55,0X55,0X15,0X7F,0X40,0X34,0X02,0X5F,0X55,0X0F,\r\n        0X22,0XFE,0X22,0X00,0XAE,0XA8,0XA8,0XEF,0XA8,0XA8,0XAE,0X74,0X02,0X0F,0X07,0X87,0X2F,0XE2,0X2F,0X02,\r\n        0XC0,0X47,0X65,0XDF,0X45,0XCD,0X07,0X40,0X27,0X48,0X03,0XA7,0XCB,0X22,0X22,0XFE,0X22,0X80,0XBA,0XAA,\r\n        0XFE,0XA9,0XB9,0X80,0X44,0X23,0X0F,0X32,0X86,0X2F,0XE2,0X2F,0X82,0X4E,0XAA,0X9A,0XAE,0X40,0X8C,0X80,\r\n        0X4E,0X27,0X2F,0XFA,0X30,0XF8,0X22,0XFE,0X22,0X00,0X56,0X5A,0XD6,0X7A,0X52,0X59,0X55,0X74,0X42,0X9A,\r\n        0X5B,0XB5,0X28,0XE2,0X2F,0X02,0X60,0XA0,0XAE,0XBA,0XAA,0XAA,0X6E,0X40,0X27,0X80,0XAB,0XAA,0X8B,0X22,\r\n        0XFE,0X22,0XFF,0X49,0X4F,0X00,0XC9,0X49,0XCF,0X00,0X74,0XF2,0X22,0X58,0X52,0X18,0X21,0X0F,0XA2,0XFE,\r\n        0XAB,0X8A,0X42,0X73,0XCC,0X43,0X80,0XA7,0XA9,0XAB,0X89,0X8B,0X48,0XAA,0XBA,0XAF,0XEA,0X8A,0XC4,0XAB,\r\n        0X92,0X2E,0X42,0X88,0XAB,0XAA,0X2A,0XAB,0X26,0XE2,0X2F,0X02,0X40,0XAC,0X56,0XAD,0X54,0XAD,0X14,0X4D,\r\n        0X27,0XF0,0X64,0X65,0XF4,0X11,0XF2,0X08,0XEA,0XAF,0XAA,0XFA,0XAA,0XAF,0XEA,0X08,0X78,0XFA,0XAA,};\r\n#elif  ENABLE_CHINESE_FULL ==3\r\nconst uint8_t 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0XAF,0XAE,0X19,0X00,0XFF,0X05,0X55,0X9D,0X55,0X35,0X55,0X9D,0X55,0X07,0X78,\r\n0XD4,0X57,0X50,0X5F,0X45,0X48,0X6D,0XDD,0XDC,0X5A,0X55,0X5E,0X79,0X4A,0X0D,0XBC,0XFA,0XBA,0XB0,0XFA,\r\n0XBA,0X44,0X54,0XFF,0X54,0X7A,0XAA,0X3A,0XEB,0X3A,0XAA,0X7A,0X12,0X1F,0X25,0X8F,0X43,0X4B,0X44,0XF5,\r\n0X4F,0XE5,0XAF,0XEA,0XAF,0XB9,0XEA,0XAF,0X2A,0XF1,0X79,0XE4,0XAB,0XEA,0X1A,0XEA,0XAF,0XEA,0X1A,0X21,\r\n0X92,0X48,0X37,0X44,0X8C,0XA8,0XAC,0X48,0X86,0X0D,0X2C,0XFE,0XAA,0XFF,0X2A,0X0E,0XE0,0X5F,0XD1,0X7A,\r\n0XCB,0X2A,0XF2,0X22,0X78,0XE0,0XEA,0XEA,0XAA,0X7A,0XAF,0XEA,0X12,0XFA,0X57,0XFA,0X52,0X52,0XAF,0XAA,\r\n0X0F,0X1D,0X1D,0XAD,0XFB,0XAE,0X2B,0XAC,0XFB,0XAA,0X0B,0XE0,0XBF,0XEA,0X09,0XAF,0XFA,0XAA,0XA0,0X7A,\r\n0X02,0XFA,0XAE,0XBB,0XE2,0X82,0X2A,0XBB,0XEE,0XBA,0X2A,0XAA,0X7A,0XF2,0X72,0XAA,0X2A,0XA0,0XFF,0XAA,\r\n0XA6,0XAF,0XEA,0XA4,0XFA,0XAF,0XA6,0X8A,0X07,0X55,0X0F,0X5F,0X05,0X62,0XAE,0XAA,0XEA,0XAA,0XBF,0XAA,\r\n0XEA,0XAA,0XAE,0X62,0XAA,0XF6,0X2A,0X72,0XAA,0XCA,0X5A,0XDE,0X59,0X57,0XF4,0X50,0X5E,0XDA,0X5E,0XCA,\r\n0XAE,0X5A,0XEB,0XB0,0XFA,0XBA,0X9F,0XD5,0X7F,0X40,0XFF,0X55,0X5F,0X92,0XFE,0X49,0X49,0XF0,0X55,0X57,\r\n0X05,0X87,0X4E,0X78,0XD9,0X7D,0X4F,0XCA,0X4D,0XFA,0X5D,0X5D,0XCB,0X0A,0XF0,0X2A,0X23,0XB6,0XAC,0X9E,\r\n0X12,0XF2,0X5E,0X00,0XFE,0XAA,0XFF,0XAA,0XBE,0X82,0X47,0XA3,0XB4,0XFA,0X9A,0XE2,0X29,0X21,0XEF,0X09,\r\n0XA0,0XDF,0XA8,0XDD,0XAA,0XDD,0XFF,0X78,0X04,0XAF,0XA7,0XC7,0X18,0XEF,0XA9,0XA9,0XEF,0X38,0XD7,0X5D,\r\n0XF7,0X55,0XF7,0XF0,0XA2,0X0F,0X55,0XD7,0X4F,0X39,0X2F,0X89,0XC8,0XBF,0XAA,0XAA,0XEE,0X8A,0X0B,0X00,\r\n0X4F,0XB8,0X36,0XA6,0XCB,0X94,0XF3,0X92,0X00,0XBA,0XAA,0XFA,0X83,0XFA,0XAA,0XBA,0XF0,0X04,0X6A,0XAF,\r\n0X63,0X2A,0X21,0XED,0X1F,0XA5,0XAB,0XAA,0X3F,0XA8,0XAF,0XAA,0X1B,0XF0,0XA0,0XF6,0X3A,0XA6,0XF4,0X53,\r\n0XFA,0X56,0X1B,0XEE,0XAA,0XAC,0XEB,0X0E,0X1A,0X99,0X55,0XF0,0XAA,0XEA,0XA0,0XAB,0XAA,0X3F,0XA8,0XAF,\r\n0XEA,0X2F,0XE0,0X2F,0XD0,0XAF,0XF6,0X7A,0X7A,0XF0,0XCA,0X52,0X5A,0XB6,0X92,0X4A,0XBF,0X6A,0XAA,0XBE,\r\n0X2A,0X2A,0X11,0XDF,0X75,0XF5,0X98,0XD1,0X75,0X07,0X5C,0XC5,0XF4,0XC7,0X54,0X05,0XDC,0X75,0XF7,0X51,\r\n0X57,0X5D,0X57,0XF9,0X14,0XDF,0X54,0X56,0XDD,0X54,0XC0,0X44,0X52,0XC9,0X04,0X99,0XF5,0X39,0X55,0X9B,\r\n0X49,0X4A,0XF2,0X4F,0XB2,0XA2,0XFD,0XA7,0XA6,0XF5,0XAF,0XF2,0XF4,0X89,0XAD,0XA9,0X8D,0X88,0XFF,0X48,\r\n0X80,0X5F,0XF5,0X5F,0X40,0XFF,0X55,0X5F,0XF8,0X00,0XB8,0X55,0XB5,0X89,0XF8,0X8F,0X44,0XB8,0XEF,0XA9,\r\n0XCA,0XBD,0XEA,0X2F,0X88,0X0F,0X92,0XB6,0X2E,0XA5,0XBA,0XEF,0XBA,0XC2,0XBA,0XAF,0XBA,0X00,0XFD,0X0B,\r\n0XF9,0XF0,0XAA,0XAF,0X0A,0X68,0XE8,0X29,0XE1,0X4F,0XB4,0XAA,0XF9,0XAB,0XAA,0XF9,0XAB,0X7A,0X34,0XB2,\r\n0X48,0X43,0XB4,0X48,0X47,0XFC,0X44,0XBA,0XEF,0XBA,0XC2,0XBA,0XAF,0XBA,0X8F,0X57,0XF0,0XAA,0XAF,0XEA,\r\n0X5D,0X09,0X5D,0XF9,0X0D,0XF3,0X59,0X5D,0XF9,0X09,0XFB,0X7A,0X7A,0XA8,0X45,0X8B,0XDE,0X95,0XD0,0X95,\r\n0XDF,0X02,0XB6,0XEA,0XA5,0X91,0XC5,0XAF,0XA7,0X87,0X6A,0X63,0X8A,0XE8,0X2F,0XE0,0XAB,0XEE,0X3B,0XEC,\r\n0XAB,0XEA,0X2B,0X88,0X17,0XAF,0XAA,0XAF,0X8A,0XFE,0X2A,0XFF,0XAA,0X3A,0X95,0X6E,0XC4,0X5F,0XEE,0X55,\r\n0X07,0X4F,0X92,0X16,0XF2,0X52,0X6A,0X49,0X68,0X59,0X0A,0X72,0XDD,0X75,0X5F,0X75,0XFF,0XF8,0X74,0X54,\r\n0X75,0XFD,0X40,0X42,0X7A,0XCA,0X4A,0X6F,0X4A,0XCA,0X7A,0X42,0X40,0XF8,0X99,0X8F,0X9F,0XF9,0X88,0XA9,\r\n0XAA,0XAE,0XAB,0XFA,0XAA,0XAA,0XAA,0XAE,0X88,0XB9,0XFA,0XBA,0XB0,0XFA,0XBA,0XFA,0X4A,0X3E,0X4A,0X00,\r\n0XFE,0X2A,0X7E,0XAB,0X7E,0X2A,0X5F,0X55,0X78,0X2B,0X2F,0XEB,0X29,0X21,0XEF,0X05,0XA0,0XBE,0XAA,0X4E,\r\n0XF4,0X83,0X74,0X34,0X92,0X5B,0X55,0X8B,0X24,0XF2,0X89,0XDF,0X75,0XDF,0X75,0X5F,0X12,0XF2,0X12,0XF0,\r\n0XF0,0X75,0X55,0XF8,0X40,0X40,0XCA,0XA6,0XAB,0X92,0XA3,0XA2,0XCB,0X46,0X4A,0XD0,0XEA,0XDA,0XD0,0XEA,\r\n0XDA,0X11,0X22,0X4C,0XE5,0X4D,0XE5,0X4F,0X05,0XED,0XA5,0XEC,0X24,0X54,0X5F,0X84,0XA7,0X5F,0X64,0XCF,\r\n0X0A,0XA0,0XFA,0XA7,0X4A,0XAB,0XFA,0XA7,0X0A,0X0F,0X20,0XA2,0X2F,0X22,0X22,0XA2,0XFA,0XAA,0XEA,0XBF,\r\n0XAA,0XAA,0XFA,0X22,0X22,0X7A,0XFA,0XB2,0X54,0X5E,0X4C,0XF1,0X4D,0X6B,0XD9,0X4D,0X0B,0X48,0X2C,0X9B,\r\n0X48,0X00,0XAF,0X02,0XAF,0X30,0XE4,0X88,0X88,0XFF,0X48,0X62,0XAE,0XEA,0XBF,0XEA,0XAE,0X62,0X80,0X0F,\r\n0X6A,0XAF,0X63,0XEA,0X2F,0XE0,0X0F,0X20,0XE6,0XAA,0XFE,0XAB,0XEE,0X2A,0X36,0X31,0XA0,0XF6,0X3A,0XA6,\r\n0X08,0XE7,0X14,0X0C,0X62,0XAE,0XEA,0XBF,0XEA,0XAE,0X62,0XF0,0X24,0X6A,0XAF,0X63,0XAA,0XE8,0XBB,0XEE,\r\n0XAB,0X48,0X71,0XAF,0XAA,0X6A,0X0F,0X81,0X14,0X84,0X9E,0X0C,0XA5,0X78,0X48,0XFF,0XC8,0X5F,0XF5,0X5F,\r\n0X40,0XFF,0X55,0X5F,0X44,0X23,0XB8,0X55,0XB5,0X09,0XF3,0X55,0X0D,0XFF,0X55,0XF9,0X05,0X5F,0XFD,0X05,\r\n0XA3,0XAB,0X27,0X23,0XA7,0XAB,0XF8,0XAE,0XFB,0XAE,0XFA,0XAE,0XEA,0XBF,0XEA,0XAE,0X62,0X6A,0XE2,0X6A,\r\n0XAF,0X63,0X0A,};\r\n#endif\r\n#endif\r\n"
  },
  {
    "path": "font.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef FONT_H\r\n#define FONT_H\r\n#include \"stdbool.h\"\r\n#include <stdint.h>\r\n\r\nextern const uint8_t gFontChinese_out[2261];\r\n#define CHN_FONT_WIDTH 11U\r\n#define CHN_FONT_HIGH 12U\r\n#if  ENABLE_CHINESE_FULL ==4 &&!defined(ENABLE_ENGLISH)\r\nextern bool audio_keep_flag;\r\n\r\n#define MAX_EDIT_INDEX 13\r\n#else\r\n#define MAX_EDIT_INDEX 10\r\n#endif\r\nextern bool show_move_flag;\r\n\r\nextern const uint8_t gFontBigDigits[11][20/*20*/];\r\nextern const uint8_t gFont3x5[96][3];\r\nextern const uint8_t gFontSmall[95 - 1][6];\r\nextern const uint8_t font4[1814];\r\n\r\n\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "frequencies.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"frequencies.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include <assert.h>\r\n// the BK4819 has 2 bands it covers, 18MHz(Some BK4819 chips can go down to 15MHz. It's mostly up to binning) ~ 630MHz and 760MHz ~ 1300MHz\r\n\r\n#define BX4819_band1_lower 1500000\r\n#define BX4819_band2_upper 130000000\r\n\r\nconst freq_band_table_t BX4819_band1 = {BX4819_band1_lower,  63000000};\r\nconst freq_band_table_t BX4819_band2 = {76000000, BX4819_band2_upper};\r\n\r\nconst freq_band_table_t frequencyBandTable[] =\r\n        {\r\n#ifndef ENABLE_WIDE_RX\r\n                // QS original\r\n                [BAND1_50MHz ]={.lower =  5000000,  .upper =  7600000},\r\n                [BAND7_470MHz]={.lower = 47000000,  .upper = 60000000},\r\n#else\r\n                // extended range\r\n\t\t[BAND1_50MHz ]={.lower =  BX4819_band1_lower, .upper =  10800000},\r\n\t\t[BAND7_470MHz]={.lower = 47000000, .upper = BX4819_band2_upper},\r\n#endif\r\n                [BAND2_108MHz]={.lower = 10800000,  .upper = 13700000},\r\n                [BAND3_137MHz]={.lower = 13700000,  .upper = 17400000},\r\n                [BAND4_174MHz]={.lower = 17400000,  .upper = 35000000},\r\n                [BAND5_350MHz]={.lower = 35000000,  .upper = 40000000},\r\n                [BAND6_400MHz]={.lower = 40000000,  .upper = 47000000}\r\n        };\r\n\r\n#ifdef ENABLE_NOAA\r\nconst uint32_t NoaaFrequencyTable[10] =\r\n\t{\r\n\t\t16255000,\r\n\t\t16240000,\r\n\t\t16247500,\r\n\t\t16242500,\r\n\t\t16245000,\r\n\t\t16250000,\r\n\t\t16252500,\r\n\t\t16152500,\r\n\t\t16177500,\r\n\t\t16327500\r\n\t};\r\n#endif\r\n\r\n\r\n\r\n// this order of steps has to be preserved for backwards compatibility with other/stock firmwares\r\nconst uint16_t gStepFrequencyTable[] = {\r\n// standard steps\r\n        [STEP_2_5kHz]   = 250,\r\n        [STEP_5kHz]     = 500,\r\n        [STEP_6_25kHz]  = 625,\r\n        [STEP_10kHz]    = 1000,\r\n        [STEP_12_5kHz]  = 1250,\r\n        [STEP_25kHz]    = 2500,\r\n        [STEP_8_33kHz]  = 833,\r\n// custom steps\r\n        [STEP_0_01kHz]  = 1,\r\n        [STEP_0_05kHz]  = 5,\r\n        [STEP_0_1kHz]   = 10,\r\n        [STEP_0_25kHz]  = 25,\r\n        [STEP_0_5kHz]   = 50,\r\n        [STEP_1kHz]     = 100,\r\n        [STEP_1_25kHz]  = 125,\r\n        [STEP_9kHz]     = 900,\r\n        [STEP_15kHz]    = 1500,\r\n        [STEP_20kHz]    = 2000,\r\n        [STEP_30kHz]    = 3000,\r\n        [STEP_50kHz]    = 5000,\r\n        [STEP_100kHz]   = 10000,\r\n        [STEP_125kHz]   = 12500,\r\n        [STEP_200kHz]   = 20000,\r\n        [STEP_250kHz]   = 25000,\r\n        [STEP_500kHz]   = 50000\r\n};\r\n\r\nconst STEP_Setting_t StepSortedIndexes[] = {\r\n        STEP_0_01kHz, STEP_0_05kHz, STEP_0_1kHz, STEP_0_25kHz, STEP_0_5kHz, STEP_1kHz, STEP_1_25kHz, STEP_2_5kHz, STEP_5kHz, STEP_6_25kHz,\r\n        STEP_8_33kHz, STEP_9kHz, STEP_10kHz, STEP_12_5kHz, STEP_15kHz, STEP_20kHz, STEP_25kHz, STEP_30kHz, STEP_50kHz, STEP_100kHz,\r\n        STEP_125kHz, STEP_200kHz, STEP_250kHz, STEP_500kHz\r\n};\r\n\r\nSTEP_Setting_t FREQUENCY_GetStepIdxFromSortedIdx(uint8_t sortedIdx)\r\n{\r\n    return StepSortedIndexes[sortedIdx];\r\n}\r\n\r\nuint32_t FREQUENCY_GetSortedIdxFromStepIdx(uint8_t stepIdx)\r\n{\r\n    for(uint8_t i = 0; i < ARRAY_SIZE(gStepFrequencyTable); i++)\r\n        if(StepSortedIndexes[i] == stepIdx)\r\n            return i;\r\n    return 0;\r\n}\r\nstatic_assert(ARRAY_SIZE(gStepFrequencyTable) == STEP_N_ELEM);\r\nFREQUENCY_Band_t FREQUENCY_GetBand(uint32_t Frequency)\r\n{\r\n    for (int32_t band = BAND_N_ELEM - 1; band >= 0; band--)\r\n        if (Frequency >= frequencyBandTable[band].lower)\r\n            return (FREQUENCY_Band_t)band;\r\n\r\n    return BAND1_50MHz;\r\n}\r\n\r\nuint8_t FREQUENCY_CalculateOutputPower(uint8_t TxpLow, uint8_t TxpMid, uint8_t TxpHigh, int32_t LowerLimit, int32_t Middle, int32_t UpperLimit, int32_t Frequency)\r\n{\r\n    if (Frequency <= LowerLimit)\r\n        return TxpLow;\r\n\r\n    if (UpperLimit <= Frequency)\r\n        return TxpHigh;\r\n\r\n    if (Frequency <= Middle)\r\n    {\r\n        TxpMid += ((TxpMid - TxpLow) * (Frequency - LowerLimit)) / (Middle - LowerLimit);\r\n        return TxpMid;\r\n    }\r\n\r\n    TxpMid += ((TxpHigh - TxpMid) * (Frequency - Middle)) / (UpperLimit - Middle);\r\n\r\n    return TxpMid;\r\n}\r\n\r\n\r\nuint32_t FREQUENCY_RoundToStep(uint32_t freq, uint16_t step)\r\n{\r\n    if(step == 833) {\r\n        uint32_t base = freq/2500*2500;\r\n        int chno = (freq - base) / 700;    // convert entered aviation 8.33Khz channel number scheme to actual frequency.\r\n        return base + (chno * 833) + (chno == 3);\r\n    }\r\n    if(step == 1)\r\n        return freq;\r\n    if(step >= 1000)\r\n    step = step/2;\r\n    return (freq + (step + 1) / 2) / step * step;\r\n}\r\n\r\nint32_t TX_freq_check(const uint32_t Frequency)\r\n{\t// return '0' if TX frequency is allowed\r\n    // otherwise return '-1'\r\n\r\n    if (Frequency < frequencyBandTable[0].lower || Frequency > frequencyBandTable[BAND_N_ELEM - 1].upper)\r\n        return 1;  // not allowed outside this range\r\n    if (Frequency >= BX4819_band1.upper && Frequency < BX4819_band2.lower)\r\n        return -1;  // BX chip does not work in this range\r\n\r\n    switch (gSetting_F_LOCK)\r\n    {\r\n        case F_LOCK_DEF:\r\n            if (Frequency >= frequencyBandTable[BAND3_137MHz].lower && Frequency < frequencyBandTable[BAND3_137MHz].upper)\r\n                return 0;\r\n//            if (Frequency >= frequencyBandTable[BAND4_174MHz].lower && Frequency < frequencyBandTable[BAND4_174MHz].upper)\r\n//                if (gSetting_200TX)\r\n//                    return 0;\r\n//            if (Frequency >= frequencyBandTable[BAND5_350MHz].lower && Frequency < frequencyBandTable[BAND5_350MHz].upper)\r\n//                if (gSetting_350TX && gSetting_350EN)\r\n//                    return 0;\r\n            if (Frequency >= frequencyBandTable[BAND6_400MHz].lower && Frequency < frequencyBandTable[BAND6_400MHz].upper)\r\n                return 0;\r\n//            if (Frequency >= frequencyBandTable[BAND7_470MHz].lower && Frequency <= 60000000)\r\n//                if (gSetting_500TX)\r\n//                    return 0;\r\n            break;\r\n\r\n        case F_LOCK_FCC:\r\n            if (Frequency >= 14400000 && Frequency <= 14800000)\r\n                return 0;\r\n            if (Frequency >= 42000000 && Frequency <= 45000000)\r\n                return 0;\r\n            break;\r\n\r\n        case F_LOCK_CE:\r\n            if (Frequency >= 14400000 && Frequency < 14600000)\r\n                return 0;\r\n            if (Frequency >= 43000000 && Frequency < 44000000)\r\n                return 0;\r\n            break;\r\n\r\n        case F_LOCK_GB:\r\n            if (Frequency >= 14400000 && Frequency < 14800000)\r\n                return 0;\r\n            if (Frequency >= 43000000 && Frequency < 44000000)\r\n                return 0;\r\n            break;\r\n\r\n\r\n\r\n        case F_LOCK_ALL:\r\n            break;\r\n\r\n        case F_LOCK_NONE:\r\n            for (uint32_t i = 0; i < ARRAY_SIZE(frequencyBandTable); i++)\r\n                if (Frequency >= frequencyBandTable[i].lower && Frequency < frequencyBandTable[i].upper)\r\n                    return 0;\r\n            break;\r\n    }\r\n\r\n    // dis-allowed TX frequency\r\n    return -1;\r\n}\r\n\r\nint32_t RX_freq_check(const uint32_t Frequency)\r\n{\t// return '0' if RX frequency is allowed\r\n    // otherwise return '-1'\r\n\r\n    if (Frequency < frequencyBandTable[0].lower || Frequency > frequencyBandTable[BAND_N_ELEM - 1].upper)\r\n        return -1;\r\n\r\n    if (Frequency >= BX4819_band1.upper && Frequency < BX4819_band2.lower)\r\n        return -1;\r\n\r\n    return 0;   // OK frequency\r\n}"
  },
  {
    "path": "frequencies.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef FREQUENCIES_H\r\n#define FREQUENCIES_H\r\n\r\n#include <stdint.h>\r\n\r\n#define _1GHz_in_KHz 100000000\r\n\r\ntypedef struct {\r\n    const uint32_t lower;\r\n    const uint32_t upper;\r\n} freq_band_table_t;\r\n\r\nextern const freq_band_table_t BX4819_band1;\r\nextern const freq_band_table_t BX4819_band2;\r\n\r\ntypedef enum  {\r\n    BAND_NONE = -1,\r\n    BAND1_50MHz = 0,\r\n    BAND2_108MHz,\r\n    BAND3_137MHz,\r\n    BAND4_174MHz,\r\n    BAND5_350MHz,\r\n    BAND6_400MHz,\r\n    BAND7_470MHz,\r\n    BAND_N_ELEM\r\n} FREQUENCY_Band_t;\r\n\r\nextern const freq_band_table_t frequencyBandTable[];\r\ntypedef enum {\r\n// standard steps\r\n    STEP_2_5kHz,\r\n    STEP_5kHz,\r\n    STEP_6_25kHz,\r\n    STEP_10kHz,\r\n    STEP_12_5kHz,\r\n    STEP_25kHz,\r\n    STEP_8_33kHz,\r\n// custom steps\r\n    STEP_0_01kHz,\r\n    STEP_0_05kHz,\r\n    STEP_0_1kHz,\r\n    STEP_0_25kHz,\r\n    STEP_0_5kHz,\r\n    STEP_1kHz,\r\n    STEP_1_25kHz,\r\n    STEP_9kHz,\r\n    STEP_15kHz,\r\n    STEP_20kHz,\r\n    STEP_30kHz,\r\n    STEP_50kHz,\r\n    STEP_100kHz,\r\n    STEP_125kHz,\r\n    STEP_200kHz,\r\n    STEP_250kHz,\r\n    STEP_500kHz,\r\n    STEP_N_ELEM\r\n} STEP_Setting_t;\r\n\r\n\r\nextern const uint16_t gStepFrequencyTable[];\r\n#ifdef ENABLE_NOAA\r\nextern const uint32_t NoaaFrequencyTable[10];\r\n#endif\r\n\r\nFREQUENCY_Band_t FREQUENCY_GetBand(uint32_t Frequency);\r\nuint8_t          FREQUENCY_CalculateOutputPower(uint8_t TxpLow, uint8_t TxpMid, uint8_t TxpHigh, int32_t LowerLimit, int32_t Middle, int32_t UpperLimit, int32_t Frequency);\r\nuint32_t \t\t FREQUENCY_RoundToStep(uint32_t freq, uint16_t step);\r\n\r\nSTEP_Setting_t   FREQUENCY_GetStepIdxFromSortedIdx(uint8_t sortedIdx);\r\nuint32_t\t\t FREQUENCY_GetSortedIdxFromStepIdx(uint8_t step);\r\n\r\nint32_t          TX_freq_check( uint32_t Frequency);\r\nint32_t          RX_freq_check( uint32_t Frequency);\r\n\r\n#endif"
  },
  {
    "path": "function.json",
    "content": "[\n  [\n    2,\n    \"英文菜单\",\n    \"中文菜单\",\n    \"English Menu\",\n    \"Chinese Menu\",\n    \"1\",\n    \"0\",\n    9\n  ],\n  [\n    2,\n    \"英文信道名\",\n    \"中文信道名\",\n    \"English Channel Name\",\n    \"Chinese Channel Name\",\n    \"0\",\n    \"4\",\n    1\n  ],\n  [\n    2,\n    \"停用MDC信令\",\n    \"开启MDC信令\",\n    \"Disable MDC1200\",\n    \"Enable MDC1200\",\n    \"0\",\n    \"1\",\n    4\n  ],\n  [\n    2,\n    \"停用短信\",\n    \"开启短信\",\n    \"Disable SMS\",\n    \"Enable SMS\",\n    \"0\",\n    \"1\",\n    2\n  ],\n  [\n    2,\n    \"停用多普勒\",\n    \"开启多普勒\",\n    \"Disable Doppler\",\n    \"Enable Doppler\",\n    \"0\",\n    \"1\",\n    3\n  ],\n  [\n    2,\n    \"停用输入法\",\n    \"开启输入法\",\n    \"Disable Chinese input method\",\n    \"Enable Chinese input method\",\n    \"0\",\n    \"1\",\n    6\n  ],\n  [\n    2,\n    \"停用频谱仪\",\n    \"开启频谱仪\",\n    \"Disable SPECTRUM\",\n    \"Enable SPECTRUM\",\n    \"0\",\n    \"1\",\n    7\n  ],\n  [\n    3,\n    \"停用收音机\",\n    \"默认收音机\",\n    \"SI4732收音机\",\n    \"Disable Radio\",\n    \"Default Radio\",\n    \"SI4732 Radio\",\n    \"0\",\n    \"F\",\n    \"4\",\n    5\n  ],\n  [\n    2,\n    \"停用SI4732单边带\",\n    \"开启SI4732单边带\",\n    \"Disable SI4732 SSB\",\n    \"Enable SI4732 SSB\",\n    \"0\",\n    \"1\",\n    8\n  ]\n]"
  },
  {
    "path": "functions.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include <stdint.h>\r\n#include <string.h>\r\n#include \"app/mdc1200.h\"\r\n#include \"app/dtmf.h\"\r\n\r\n#if defined(ENABLE_FMRADIO)\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"audio.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"dcs.h\"\r\n#include \"driver/backlight.h\"\r\n#ifdef ENABLE_MESSENGER\r\n#include \"app/messenger.h\"\r\n#endif\r\n#ifdef ENABLE_DOPPLER\r\n#include \"app/doppler.h\"\r\n#endif\r\n#if defined(ENABLE_FMRADIO)\r\n#include \"driver/bk1080.h\"\r\n#endif\r\n\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/system.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"frequencies.h\"\r\n#include \"functions.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"settings.h\"\r\n#include \"ui/status.h\"\r\n#include \"ui/ui.h\"\r\n\r\nFUNCTION_Type_t gCurrentFunction;\r\n\r\n\r\nbool FUNCTION_IsRx()\r\n{\r\n    return gCurrentFunction == FUNCTION_MONITOR ||\r\n           gCurrentFunction == FUNCTION_INCOMING ||\r\n           gCurrentFunction == FUNCTION_RECEIVE;\r\n}\r\n\r\nvoid FUNCTION_Init(void)\r\n{\r\n    g_CxCSS_TAIL_Found = false;\r\n    g_CDCSS_Lost       = false;\r\n    g_CTCSS_Lost       = false;\r\n\r\n    g_SquelchLost      = false;\r\n\r\n    gFlagTailToneEliminationComplete   = false;\r\n    gTailToneEliminationCountdown_10ms = 0;\r\n    gFoundCTCSS                        = false;\r\n    gFoundCDCSS                        = false;\r\n    gFoundCTCSSCountdown_10ms          = 0;\r\n    gFoundCDCSSCountdown_10ms          = 0;\r\n    gEndOfRxDetectedMaybe              = false;\r\n\r\n    gCurrentCodeType = (gRxVfo->Modulation != MODULATION_FM) ? CODE_TYPE_OFF : gRxVfo->pRX->CodeType;\r\n\r\n#ifdef ENABLE_VOX\r\n    g_VOX_Lost     = false;\r\n#endif\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    DTMF_clear_RX();\r\n#endif\r\n\r\n#ifdef ENABLE_NOAA\r\n    gNOAACountdown_10ms = 0;\r\n\r\n\tif (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE)) {\r\n\t\tgCurrentCodeType = CODE_TYPE_CONTINUOUS_TONE;\r\n\t}\r\n#endif\r\n\r\n    gUpdateStatus = true;\r\n}\r\nvoid FUNCTION_Foreground(const FUNCTION_Type_t PreviousFunction) {\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (gDTMF_ReplyState != DTMF_REPLY_NONE)\r\n        RADIO_PrepareCssTX();\r\n#endif\r\n    if (PreviousFunction == FUNCTION_TRANSMIT) {\r\n        ST7565_FixInterfGlitch();\r\n        gVFO_RSSI_bar_level[0] = 0;\r\n        gVFO_RSSI_bar_level[1] = 0;\r\n    } else if (PreviousFunction != FUNCTION_RECEIVE) {\r\n        return;\r\n    }\r\n\r\n#if defined(ENABLE_FMRADIO)\r\n    if (gFmRadioMode)\r\n        gFM_RestoreCountdown_10ms = fm_restore_countdown_10ms;\r\n#endif\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (gDTMF_CallState == DTMF_CALL_STATE_CALL_OUT ||\r\n        gDTMF_CallState == DTMF_CALL_STATE_RECEIVED ||\r\n        gDTMF_CallState == DTMF_CALL_STATE_RECEIVED_STAY)\r\n    {\r\n        gDTMF_auto_reset_time_500ms = gEeprom.DTMF_auto_reset_time * 2;\r\n    }\r\n#endif\r\n    gUpdateStatus = true;\r\n}\r\n\r\nvoid FUNCTION_PowerSave() {\r\n    gPowerSave_10ms = gEeprom.BATTERY_SAVE * 10;\r\n    gPowerSaveCountdownExpired = false;\r\n\r\n    gRxIdleMode = true;\r\n\r\n    gMonitor = false;\r\n\r\n    BK4819_DisableVox();\r\n    BK4819_Sleep();\r\n\r\n    BK4819_ToggleGpioOut(BK4819_GPIO0_PIN28_RX_ENABLE, false);\r\n\r\n    gUpdateStatus = true;\r\n\r\n    if (gScreenToDisplay != DISPLAY_MENU)     // 1of11 .. don't close the menu\r\n        GUI_SelectNextDisplay(DISPLAY_MAIN);\r\n}\r\n\r\nvoid FUNCTION_Transmit() {\r\n    // if DTMF is enabled when TX'ing, it changes the TX audio filtering !! .. 1of11\r\n\r\n#if defined(ENABLE_MESSENGER) || defined(ENABLE_MDC1200)\r\n    enable_msg_rx(false);\r\n#endif\r\n\r\n\r\n    BK4819_DisableDTMF();\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    // clear the DTMF RX buffer\r\n    DTMF_clear_RX();\r\n#endif\r\n\r\n    // clear the DTMF RX live decoder buffer\r\n    gDTMF_RX_live_timeout = 0;\r\n    memset(gDTMF_RX_live, 0, sizeof(gDTMF_RX_live));\r\n\r\n#if defined(ENABLE_FMRADIO)\r\n    if (gFmRadioMode)\r\n        BK1080_Init(0, false);\r\n#endif\r\n\r\n#ifdef ENABLE_ALARM\r\n    if (gAlarmState == ALARM_STATE_SITE_ALARM)\r\n    {\r\n        GUI_DisplayScreen();\r\n\r\n        AUDIO_AudioPathOff();\r\n\r\n        SYSTEM_DelayMs(20);\r\n        BK4819_PlayTone(500, 0);\r\n        SYSTEM_DelayMs(2);\r\n\r\n        AUDIO_AudioPathOn();\r\n\r\n        gEnableSpeaker = true;\r\n\r\n        SYSTEM_DelayMs(60);\r\n        BK4819_ExitTxMute();\r\n\r\n        gAlarmToneCounter = 0;\r\n        return;\r\n    }\r\n#endif\r\n\r\n    gUpdateStatus = true;\r\n\r\n    GUI_DisplayScreen();\r\n\r\n    RADIO_SetTxParameters();\r\n\r\n    // turn the RED LED on\r\n    BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, true);\r\n\r\n    DTMF_Reply();\r\n#ifdef ENABLE_MDC1200\r\n#ifdef ENABLE_MESSENGER\r\n    if(!stop_mdc_flag){\r\n#endif\r\n    if ((gEeprom.ROGER == ROGER_MODE_MDC_HEAD || gEeprom.ROGER == ROGER_MODE_MDC_BOTH ||gEeprom.ROGER == ROGER_MODE_MDC_HEAD_ROGER)\r\n\r\n\r\n        ) {\r\n        BK4819_send_MDC1200(1, 0x80, gEeprom.MDC1200_ID, true);\r\n\r\n#ifdef ENABLE_MDC1200_SIDE_BEEP\r\n        BK4819_start_tone(880, 10, true, true);\r\n                                    SYSTEM_DelayMs(120);\r\n                                    BK4819_stop_tones(true);\r\n#endif\r\n    } else\r\n#endif\r\n    if (gCurrentVfo->DTMF_PTT_ID_TX_MODE == PTT_ID_APOLLO)\r\n        BK4819_PlaySingleTone(2525, 250, 0, gEeprom.DTMF_SIDE_TONE);\r\n#ifdef ENABLE_MESSENGER\r\n    #ifdef ENABLE_MDC1200\r\n\r\n    }\r\n    #endif\r\n\r\n#endif\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\n    if (gAlarmState != ALARM_STATE_OFF) {\r\n#ifdef ENABLE_TX1750\r\n        if (gAlarmState == ALARM_STATE_TX1750)\r\n            BK4819_TransmitTone(true, 1750);\r\n#endif\r\n\r\n#ifdef ENABLE_ALARM\r\n        if (gAlarmState == ALARM_STATE_TXALARM)\r\n            BK4819_TransmitTone(true, 500);\r\n\r\n        gAlarmToneCounter = 0;\r\n#endif\r\n\r\n        SYSTEM_DelayMs(2);\r\n        AUDIO_AudioPathOn();\r\n        gEnableSpeaker = true;\r\n\r\n        return;\r\n    }\r\n#endif\r\n\r\n    if (gCurrentVfo->SCRAMBLING_TYPE > 0 && gSetting_ScrambleEnable)\r\n        BK4819_EnableScramble(gCurrentVfo->SCRAMBLING_TYPE - 1);\r\n    else\r\n        BK4819_DisableScramble();\r\n\r\n//    if (gSetting_backlight_on_tx_rx & BACKLIGHT_ON_TR_TX) {\r\n    BACKLIGHT_TurnOn();\r\n//    }\r\n}\r\n\r\n\r\nvoid FUNCTION_Select(FUNCTION_Type_t Function) {\r\n    const FUNCTION_Type_t PreviousFunction = gCurrentFunction;\r\n    const bool bWasPowerSave = PreviousFunction == FUNCTION_POWER_SAVE;\r\n\r\n    gCurrentFunction = Function;\r\n\r\n    if (bWasPowerSave && Function != FUNCTION_POWER_SAVE) {\r\n        BK4819_Conditional_RX_TurnOn_and_GPIO6_Enable();\r\n        gRxIdleMode = false;\r\n        UI_DisplayStatus();\r\n    }\r\n\r\n    switch (Function) {\r\n        case FUNCTION_FOREGROUND:\r\n            FUNCTION_Foreground(PreviousFunction);\r\n            return;\r\n\r\n        case FUNCTION_POWER_SAVE:\r\n            FUNCTION_PowerSave();\r\n            return;\r\n\r\n        case FUNCTION_TRANSMIT:\r\n            FUNCTION_Transmit();\r\n            break;\r\n\r\n        case FUNCTION_MONITOR:\r\n            gMonitor = true;\r\n            break;\r\n\r\n        case FUNCTION_INCOMING:\r\n        case FUNCTION_RECEIVE:\r\n        case FUNCTION_BAND_SCOPE:\r\n        default:\r\n            break;\r\n    }\r\n\r\n    gBatterySaveCountdown_10ms = battery_save_count_10ms;\r\n    gSchedulePowerSave = false;\r\n\r\n#if defined(ENABLE_FMRADIO)\r\n    gFM_RestoreCountdown_10ms = 0;\r\n#endif\r\n}\r\n"
  },
  {
    "path": "functions.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef FUNCTIONS_H\r\n#define FUNCTIONS_H\r\n\r\n#include <stdint.h>\r\n#include \"stdbool.h\"\r\nenum FUNCTION_Type_t\r\n{\r\n\tFUNCTION_FOREGROUND = 0,  // ???\r\n\tFUNCTION_TRANSMIT,        // transmitting\r\n\tFUNCTION_MONITOR,         // receiving with squelch forced open\r\n\tFUNCTION_INCOMING,        // receiving a signal (squelch is open)\r\n\tFUNCTION_RECEIVE,         // RX mode, squelch closed\r\n\tFUNCTION_POWER_SAVE,      // sleeping\r\n    FUNCTION_BAND_SCOPE,      // bandscope mode (panadpter/spectrum) .. not yet implemented\r\n    FUNCTION_N_ELEM\r\n};\r\n\r\ntypedef enum FUNCTION_Type_t FUNCTION_Type_t;\r\n\r\nextern FUNCTION_Type_t       gCurrentFunction;\r\nvoid FUNCTION_Init(void);\r\nvoid FUNCTION_Select(FUNCTION_Type_t Function);\r\nbool FUNCTION_IsRx();\r\nvoid FUNCTION_Transmit();\r\n#endif\r\n\r\n"
  },
  {
    "path": "fw-pack.py",
    "content": "#!/usr/bin/env python3\r\n\r\nimport crcmod\r\nimport sys\r\n\r\nfrom itertools import cycle\r\nfrom binascii import hexlify\r\n\r\nOBFUSCATION = [\r\n        0x47, 0x22, 0xC0, 0x52, 0x5D, 0x57, 0x48, 0x94, 0xB1, 0x60, 0x60, 0xDB, 0x6F, 0xE3, 0x4C, 0x7C,\r\n        0xD8, 0x4A, 0xD6, 0x8B, 0x30, 0xEC, 0x25, 0xE0, 0x4C, 0xD9, 0x00, 0x7F, 0xBF, 0xE3, 0x54, 0x05,\r\n        0xE9, 0x3A, 0x97, 0x6B, 0xB0, 0x6E, 0x0C, 0xFB, 0xB1, 0x1A, 0xE2, 0xC9, 0xC1, 0x56, 0x47, 0xE9,\r\n        0xBA, 0xF1, 0x42, 0xB6, 0x67, 0x5F, 0x0F, 0x96, 0xF7, 0xC9, 0x3C, 0x84, 0x1B, 0x26, 0xE1, 0x4E,\r\n        0x3B, 0x6F, 0x66, 0xE6, 0xA0, 0x6A, 0xB0, 0xBF, 0xC6, 0xA5, 0x70, 0x3A, 0xBA, 0x18, 0x9E, 0x27,\r\n        0x1A, 0x53, 0x5B, 0x71, 0xB1, 0x94, 0x1E, 0x18, 0xF2, 0xD6, 0x81, 0x02, 0x22, 0xFD, 0x5A, 0x28,\r\n        0x91, 0xDB, 0xBA, 0x5D, 0x64, 0xC6, 0xFE, 0x86, 0x83, 0x9C, 0x50, 0x1C, 0x73, 0x03, 0x11, 0xD6,\r\n        0xAF, 0x30, 0xF4, 0x2C, 0x77, 0xB2, 0x7D, 0xBB, 0x3F, 0x29, 0x28, 0x57, 0x22, 0xD6, 0x92, 0x8B,\r\n    ]\r\n\r\ndef obfuscate(fw):\r\n    return bytes([a^b for a, b in zip(fw, cycle(OBFUSCATION))])\r\n\r\nplain = open(sys.argv[1], 'rb').read()\r\nif len(sys.argv[2]) > 10:\r\n    print('Version suffix is too big!')\r\n    sys.exit(1)\r\n\r\nversion = b'*OEFW-' + bytes(sys.argv[2], 'ascii')\r\nif len(version) < 16:\r\n    version += b'\\x00' * (16 - len(version))\r\n\r\npacked = obfuscate(plain[:0x2000] + version + plain[0x2000:])\r\n\r\ncrc = crcmod.predefined.Crc('xmodem')\r\ncrc.update(packed)\r\ndigest = crc.digest()\r\ndigest = bytes([digest[1], digest[0]])\r\n\r\nopen(sys.argv[3], 'wb').write(packed + digest)\r\n\r\n"
  },
  {
    "path": "gen.py",
    "content": "import os\n\nlist1 = [\n    'ENABLE_CHINESE_FULL=4',\n    'ENABLE_CHINESE_FULL=0'\n]\n\nlist2 = [\n    'ENABLE_ENGLISH=1'\n]\n\nlist3 = [\n    'ENABLE_MESSENGER=1',\n    'ENABLE_MESSENGER_DELIVERY_NOTIFICATION=1',\n    'ENABLE_MESSENGER_NOTIFICATION=1'\n]\n\nlist4 = [\n    'ENABLE_DOPPLER=1',\n]\n\nlist5 = [\n    'ENABLE_MDC1200=1',\n    'ENABLE_MDC1200_EDIT=1',\n    'ENABLE_MDC1200_CONTACT=1'\n]\n\nlist6 = [\n    'ENABLE_4732=1',\n    'ENABLE_FMRADIO=1',\n]\n\nlist7 = [\n    'ENABLE_PINYIN=1',\n]\n\nlist8 = [\n    'ENABLE_SPECTRUM=1'\n]\n\nlist9 = [\n    'ENABLE_4732SSB=1'\n]\n\nall_lists = [list1, [[], list3], [[], list4], [[], list5], [[], list6[0], list6[1]], [[], list7], [[], list8],\n             [[], list9],[[],list2]]\n\nstrx = []\nstry = []\n\nindexes = [0] * len(all_lists)\n\n\ndef find_first_non_zero_index(s):\n    \"\"\"\n    从后往前查找字符串中第一个不为 '0' 的字符的索引\n    :param s: 输入字符串\n    :return: 第一个不为 '0' 的字符的索引，如果没有返回 -1\n    \"\"\"\n    # 从后往前遍历字符串\n    for i in range(len(s) - 1, -1, -1):\n        if s[i] != '0':\n            return i - 6\n    return -1\n\n\nwhile indexes[0] < len(all_lists[0]):\n    chinese = all_lists[0][indexes[0]]\n\n    indexes[1] = 0\n    while indexes[1] < len(all_lists[1]):\n        messenger = all_lists[1][indexes[1]]\n\n        indexes[2] = 0\n        while indexes[2] < len(all_lists[2]):\n            doppler = all_lists[2][indexes[2]]\n\n            indexes[3] = 0\n            while indexes[3] < len(all_lists[3]):\n                mdc1200 = all_lists[3][indexes[3]]\n\n                indexes[4] = 0\n                while indexes[4] < len(all_lists[4]):\n                    fm = all_lists[4][indexes[4]]\n\n                    indexes[5] = 0\n                    while indexes[5] < len(all_lists[5]):\n\n                        if chinese[-1] == '0' and indexes[5] == 1:\n                            indexes[5] += 1\n                            continue\n                        pinyin = all_lists[5][indexes[5]]\n\n                        indexes[6] = 0\n                        while indexes[6] < len(all_lists[6]):\n                            spectrum = all_lists[6][indexes[6]]\n                            indexes[7] = 0\n                            while indexes[7] < len(all_lists[7]):\n                                ssb = all_lists[7][indexes[7]]\n                                if ssb and fm != list6[0]:\n                                    indexes[7] += 1\n                                    continue\n                                indexes[8] = 0\n                                while indexes[8] < len(all_lists[8]):\n                                    english = all_lists[8][indexes[8]]\n                                    strm = ''\n                                    strn = ''\n                                    strm += chinese + ' '\n                                    strn += chinese[-1]\n                                    if messenger:\n                                        strm += \" \".join(list3) + ' '\n                                        strn += '1'\n                                    else:\n                                        strn += '0'\n\n                                    if doppler:\n                                        strm += \" \".join(list4) + ' '\n                                        strn += '1'\n                                    else:\n                                        strn += '0'\n\n                                    if mdc1200:\n                                        strm += \" \".join(list5) + ' '\n                                        strn += '1'\n                                    else:\n                                        strn += '0'\n\n                                    if fm:\n                                        strm += fm + ' '\n                                        strn += fm[7]\n                                    else:\n                                        strn += '0'\n                                    if pinyin:\n                                        strm += \" \".join(list7) + ' '\n                                        strn += '1'\n                                    else:\n                                        strn += '0'\n\n                                    if spectrum:\n                                        strm += \" \".join(list8) + ' '\n                                        strn += '1'\n                                    else:\n                                        strn += '0'\n                                    if ssb:\n                                        strm += \" \".join(list9) + ' '\n                                        strn += '1'\n                                    else:\n                                        strn += '0'\n\n                                    if english:\n                                        strm += \" \".join(list2) + ' '\n                                        strn += '1'\n                                    else:\n                                        strn += '0'\n                                    cuscanhshu_value = strm\n                                    customname_value = 'LOSEHU' + strn\n                                    result = 0\n                                    result = os.system(\n                                        'make full_all CUSCANSHU=\"{}\" CUSTOMNAME=\"{}\"'.format(cuscanhshu_value.rstrip()\n                                                                                              ,\n                                                                                              customname_value))\n\n                                    # print('make full_all CUSCANSHU=' + cuscanhshu_value + ' CUSTOMNAME=' + customname_value)\n                                    # if customname_value=='LOSEHU40104111':\n                                    #     result=1\n\n                                    # 仅在文件夹1中的文件: {'LOSEHU4010F110.bin', 'LOSEHU0010F000.bin', 'LOSEHU4010F000.bin', 'LOSEHU0010F100.bin', 'LOSEHU4010F010.bin', 'LOSEHU4010F100.bin', 'LOSEHU0010F010.bin', 'LOSEHU0010F110.bin'}\n                                    if result == 0:\n                                        pass\n                                    else:\n                                        index = find_first_non_zero_index(customname_value)\n                                        if index != -1:\n                                            indexes[len(all_lists)-1] = 2\n                                            for i in range(index + 1, len(all_lists)-1):\n                                                indexes[i] = len(all_lists[i]) - 1\n                                        continue\n                                    indexes[8] += 1\n                                indexes[7] += 1\n                            indexes[6] += 1\n                        indexes[5] += 1\n                    indexes[4] += 1\n                indexes[3] += 1\n            indexes[2] += 1\n        indexes[1] += 1\n    indexes[0] += 1\n"
  },
  {
    "path": "genJson.py",
    "content": "import os\nimport json\n\nlist = []\nfor filename in os.listdir(r'.'):\n    if len(filename) >= 5 and filename[-5] != 'm' and filename[-4] == '.' and filename[-3] == 'b' and filename[-2] == 'i' and filename[-1] == 'n':\n        list.append(filename)\n\nprint(json.dumps(list))\nwith open(\"version.json\",\"w\") as file:\n    file.write(json.dumps(list))"
  },
  {
    "path": "h --force-with-lease origin main",
    "content": "\u001b[1mdiff --git a/.idea/.gitignore b/.idea/.gitignore\u001b[m\r\n\u001b[1mdeleted file mode 100644\u001b[m\r\n\u001b[1mindex 35410ca..0000000\u001b[m\r\n\u001b[1m--- a/.idea/.gitignore\u001b[m\r\n\u001b[1m+++ /dev/null\u001b[m\r\n\u001b[36m@@ -1,8 +0,0 @@\u001b[m\r\n\u001b[31m-# 默认忽略的文件\u001b[m\r\n\u001b[31m-/shelf/\u001b[m\r\n\u001b[31m-/workspace.xml\u001b[m\r\n\u001b[31m-# 基于编辑器的 HTTP 客户端请求\u001b[m\r\n\u001b[31m-/httpRequests/\u001b[m\r\n\u001b[31m-# Datasource local storage ignored files\u001b[m\r\n\u001b[31m-/dataSources/\u001b[m\r\n\u001b[31m-/dataSources.local.xml\u001b[m\r\n\u001b[1mdiff --git a/.idea/.name b/.idea/.name\u001b[m\r\n\u001b[1mdeleted file mode 100644\u001b[m\r\n\u001b[1mindex 8829405..0000000\u001b[m\r\n\u001b[1m--- a/.idea/.name\u001b[m\r\n\u001b[1m+++ /dev/null\u001b[m\r\n\u001b[36m@@ -1 +0,0 @@\u001b[m\r\n\u001b[31m-uv_k5_firmware_custom_0_17\u001b[m\r\n\\ No newline at end of file\u001b[m\r\n\u001b[1mdiff --git a/.idea/deployment.xml b/.idea/deployment.xml\u001b[m\r\n\u001b[1mdeleted file mode 100644\u001b[m\r\n\u001b[1mindex 508379c..0000000\u001b[m\r\n\u001b[1m--- a/.idea/deployment.xml\u001b[m\r\n\u001b[1m+++ /dev/null\u001b[m\r\n\u001b[36m@@ -1,14 +0,0 @@\u001b[m\r\n\u001b[31m-<?xml version=\"1.0\" encoding=\"UTF-8\"?>\u001b[m\r\n\u001b[31m-<project version=\"4\">\u001b[m\r\n\u001b[31m-  <component name=\"PublishConfigData\" remoteFilesAllowedToDisappearOnAutoupload=\"false\">\u001b[m\r\n\u001b[31m-    <serverData>\u001b[m\r\n\u001b[31m-      <paths name=\"远程主机 (4b031f9e-4161-4ac3-8eed-b4f57092613d)\">\u001b[m\r\n\u001b[31m-        <serverdata>\u001b[m\r\n\u001b[31m-          <mappings>\u001b[m\r\n\u001b[31m-            <mapping local=\"$PROJECT_DIR$\" web=\"/\" />\u001b[m\r\n\u001b[31m-          </mappings>\u001b[m\r\n\u001b[31m-        </serverdata>\u001b[m\r\n\u001b[31m-      </paths>\u001b[m\r\n\u001b[31m-    </serverData>\u001b[m\r\n\u001b[31m-  </component>\u001b[m\r\n\u001b[31m-</project>\u001b[m\r\n\\ No newline at end of file\u001b[m\r\n\u001b[1mdiff --git a/.idea/misc.xml b/.idea/misc.xml\u001b[m\r\n\u001b[1mdeleted file mode 100644\u001b[m\r\n\u001b[1mindex 79b3c94..0000000\u001b[m\r\n\u001b[1m--- a/.idea/misc.xml\u001b[m\r\n\u001b[1m+++ /dev/null\u001b[m\r\n\u001b[36m@@ -1,4 +0,0 @@\u001b[m\r\n\u001b[31m-<?xml version=\"1.0\" encoding=\"UTF-8\"?>\u001b[m\r\n\u001b[31m-<project version=\"4\">\u001b[m\r\n\u001b[31m-  <component name=\"CMakeWorkspace\" PROJECT_DIR=\"$PROJECT_DIR$\" />\u001b[m\r\n\u001b[31m-</project>\u001b[m\r\n\\ No newline at end of file\u001b[m\r\n\u001b[1mdiff --git a/.idea/modules.xml b/.idea/modules.xml\u001b[m\r\n\u001b[1mdeleted file mode 100644\u001b[m\r\n\u001b[1mindex 49c64ec..0000000\u001b[m\r\n\u001b[1m--- a/.idea/modules.xml\u001b[m\r\n\u001b[1m+++ /dev/null\u001b[m\r\n\u001b[36m@@ -1,8 +0,0 @@\u001b[m\r\n\u001b[31m-<?xml version=\"1.0\" encoding=\"UTF-8\"?>\u001b[m\r\n\u001b[31m-<project version=\"4\">\u001b[m\r\n\u001b[31m-  <component name=\"ProjectModuleManager\">\u001b[m\r\n\u001b[31m-    <modules>\u001b[m\r\n\u001b[31m-      <module fileurl=\"file://$PROJECT_DIR$/.idea/uv-k5-firmware-chinese.iml\" filepath=\"$PROJECT_DIR$/.idea/uv-k5-firmware-chinese.iml\" />\u001b[m\r\n\u001b[31m-    </modules>\u001b[m\r\n\u001b[31m-  </component>\u001b[m\r\n\u001b[31m-</project>\u001b[m\r\n\\ No newline at end of file\u001b[m\r\n\u001b[1mdiff --git a/.idea/uv-k5-firmware-chinese.iml b/.idea/uv-k5-firmware-chinese.iml\u001b[m\r\n\u001b[1mdeleted file mode 100644\u001b[m\r\n\u001b[1mindex f08604b..0000000\u001b[m\r\n\u001b[1m--- a/.idea/uv-k5-firmware-chinese.iml\u001b[m\r\n\u001b[1m+++ /dev/null\u001b[m\r\n\u001b[36m@@ -1,2 +0,0 @@\u001b[m\r\n\u001b[31m-<?xml version=\"1.0\" encoding=\"UTF-8\"?>\u001b[m\r\n\u001b[31m-<module classpath=\"CMake\" type=\"CPP_MODULE\" version=\"4\" />\u001b[m\r\n\\ No newline at end of file\u001b[m\r\n\u001b[1mdiff --git a/.idea/vcs.xml b/.idea/vcs.xml\u001b[m\r\n\u001b[1mdeleted file mode 100644\u001b[m\r\n\u001b[1mindex 35eb1dd..0000000\u001b[m\r\n\u001b[1m--- a/.idea/vcs.xml\u001b[m\r\n\u001b[1m+++ /dev/null\u001b[m\r\n\u001b[36m@@ -1,6 +0,0 @@\u001b[m\r\n\u001b[31m-<?xml version=\"1.0\" encoding=\"UTF-8\"?>\u001b[m\r\n\u001b[31m-<project version=\"4\">\u001b[m\r\n\u001b[31m-  <component name=\"VcsDirectoryMappings\">\u001b[m\r\n\u001b[31m-    <mapping directory=\"\" vcs=\"Git\" />\u001b[m\r\n\u001b[31m-  </component>\u001b[m\r\n\u001b[31m-</project>\u001b[m\r\n\\ No newline at end of file\u001b[m\r\n\u001b[1mdiff --git a/firmware.packed.cn_all.bin b/firmware.packed.cn_all.bin\u001b[m\r\n\u001b[1mnew file mode 100644\u001b[m\r\n\u001b[1mindex 0000000..5077f87\u001b[m\r\nBinary files /dev/null and b/firmware.packed.cn_all.bin differ\r\n\u001b[1mdiff --git a/firmware.packed_antikay.bin b/firmware.packed_antikay.bin\u001b[m\r\n\u001b[1mnew file mode 100644\u001b[m\r\n\u001b[1mindex 0000000..298c688\u001b[m\r\nBinary files /dev/null and b/firmware.packed_antikay.bin differ\r\n\u001b[1mdiff --git a/ui/menu.c b/ui/menu.c\u001b[m\r\n\u001b[1mindex c696266..fbcaef5 100644\u001b[m\r\n\u001b[1m--- a/ui/menu.c\u001b[m\r\n\u001b[1m+++ b/ui/menu.c\u001b[m\r\n\u001b[36m@@ -318,14 +318,10 @@\u001b[m \u001b[mconst char gSubMenu_PONMSG[][5] =//8\u001b[m\r\n                 \"\\xE9\\xA6\\xA7\"\u001b[m\r\n         };\u001b[m\r\n \u001b[m\r\n\u001b[31m-const char gSubMenu_ROGER[][9] =\u001b[m\r\n\u001b[32m+\u001b[m\u001b[32mconst char gSubMenu_ROGER[][6] =\u001b[m\r\n         {\u001b[m\r\n\u001b[31m-//                \"OFF\",\u001b[m\r\n\u001b[31m-//                \"ROGER\",\u001b[m\r\n\u001b[31m-//                \"MDC\"\u001b[m\r\n\u001b[31m-\u001b[m\r\n                 \"\\xD9\\xDF\\xB5\\xB6\\x0E\",\u001b[m\r\n\u001b[31m-                \"ROGER\\xB5\\xB6\\x0E\",\u001b[m\r\n\u001b[32m+\u001b[m\u001b[32m                \"\\xA9\\xB4\\xB5\\xB6\\x0E\",\u001b[m\r\n                 \"\\x4D\\x44\\x43\\xEF\\xF0\"\u001b[m\r\n         };\u001b[m\r\n \u001b[m\r\n\u001b[1mdiff --git a/ui/menu.h b/ui/menu.h\u001b[m\r\n\u001b[1mindex 535c3c7..7215ff0 100644\u001b[m\r\n\u001b[1m--- a/ui/menu.h\u001b[m\r\n\u001b[1m+++ b/ui/menu.h\u001b[m\r\n\u001b[36m@@ -146,7 +146,7 @@\u001b[m \u001b[mextern const char    gSubMenu_AL_MOD[2][5];\u001b[m\r\n extern const char        gSubMenu_D_RSP[4][10];//11\u001b[m\r\n extern const char*       gSubMenu_PTT_ID[5];\u001b[m\r\n extern const char        gSubMenu_PONMSG[4][5];//8\u001b[m\r\n\u001b[31m-extern const char        gSubMenu_ROGER[3][9];\u001b[m\r\n\u001b[32m+\u001b[m\u001b[32mextern const char        gSubMenu_ROGER[3][6];\u001b[m\r\n extern const char        gSubMenu_RESET[2][6];//4\u001b[m\r\n extern const char*       gSubMenu_F_LOCK[F_LOCK_LEN];\u001b[m\r\n extern const char        gSubMenu_BACKLIGHT[8][5];//7\u001b[m\r\n\u001b[1mdiff --git a/ui/scanner.c b/ui/scanner.c\u001b[m\r\n\u001b[1mindex 431cd09..d5584bb 100644\u001b[m\r\n\u001b[1m--- a/ui/scanner.c\u001b[m\r\n\u001b[1m+++ b/ui/scanner.c\u001b[m\r\n\u001b[36m@@ -34,65 +34,44 @@\u001b[m \u001b[mvoid UI_DisplayScanner(void)\u001b[m\r\n \u001b[m\r\n \tmemset(String, 0, sizeof(String));\u001b[m\r\n \tif (gScanSingleFrequency || (gScanCssState != SCAN_CSS_STATE_OFF && gScanCssState != SCAN_CSS_STATE_FAILED))\u001b[m\r\n\u001b[31m-//\u001b[m\r\n\u001b[31m-\u001b[m\r\n\u001b[31m-    sprintf(String, \"\\x03\\x04:%u.%05u\", gScanFrequency / 100000, gScanFrequency % 100000);\u001b[m\r\n\u001b[31m-    else\u001b[m\r\n\u001b[31m-\u001b[m\r\n\u001b[31m-//\t\tstrcpy(String, \"FREQ:**.*****\");\u001b[m\r\n\u001b[31m-\u001b[m\r\n\u001b[31m-        strcpy(String, \"\\x03\\x04:**.*****\");\u001b[m\r\n\u001b[32m+\u001b[m\t\t\u001b[32msprintf(String, \"FREQ:%u.%05u\", gScanFrequency / 100000, gScanFrequency % 100000);\u001b[m\r\n\u001b[32m+\u001b[m\t\u001b[32melse\u001b[m\r\n\u001b[32m+\u001b[m\t\t\u001b[32mstrcpy(String, \"FREQ:**.*****\");\u001b[m\r\n     UI_PrintStringSmall(String, 2, 0, 1);\u001b[m\r\n \u001b[m\r\n \tmemset(String, 0, sizeof(String));\u001b[m\r\n \tif (gScanCssState < SCAN_CSS_STATE_FOUND || !gScanUseCssResult)\u001b[m\r\n\u001b[31m-//\t\tstrcpy(String, \"CTC:******\");\u001b[m\r\n\u001b[31m-\u001b[m\r\n\u001b[31m-    strcpy(String, \"\\x0F\\x10\\x0D\\x0E:******\");\u001b[m\r\n\u001b[31m-\u001b[m\r\n\u001b[32m+\u001b[m\t\t\u001b[32mstrcpy(String, \"CTC:******\");\u001b[m\r\n \telse\u001b[m\r\n \tif (gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE)\u001b[m\r\n\u001b[31m-//\t\tsprintf(String, \"CTC:%u.%uHz\", CTCSS_Options[gScanCssResultCode] / 10, CTCSS_Options[gScanCssResultCode] % 10);\u001b[m\r\n\u001b[31m-        sprintf(String, \"\\x0F\\x10\\x0D\\x0E:%u.%uHz\", CTCSS_Options[gScanCssResultCode] / 10, CTCSS_Options[gScanCssResultCode] % 10);\u001b[m\r\n\u001b[32m+\u001b[m\t\t\u001b[32msprintf(String, \"CTC:%u.%uHz\", CTCSS_Options[gScanCssResultCode] / 10, CTCSS_Options[gScanCssResultCode] % 10);\u001b[m\r\n \telse\u001b[m\r\n\u001b[31m-//\t\tsprintf(String, \"DCS:D%03oN\", DCS_Options[gScanCssResultCode]);\u001b[m\r\n\u001b[31m-\u001b[m\r\n\u001b[31m-    sprintf(String, \"\\x0B\\x0C\\x0D\\x0E:D%03oN\", DCS_Options[gScanCssResultCode]);\u001b[m\r\n\u001b[32m+\u001b[m\t\t\u001b[32msprintf(String, \"DCS:D%03oN\", DCS_Options[gScanCssResultCode]);\u001b[m\r\n     UI_PrintStringSmall(String, 2, 0, 3);\u001b[m\r\n \u001b[m\r\n \tmemset(String, 0, sizeof(String));\u001b[m\r\n \tif (gScannerSaveState == SCAN_SAVE_CHANNEL)\u001b[m\r\n \t{\u001b[m\r\n\u001b[31m-//\t\tstrcpy(String, \"SAVE?\");\u001b[m\r\n\u001b[32m+\u001b[m\t\t\u001b[32mstrcpy(String, \"SAVE?\");\u001b[m\r\n \u001b[m\r\n\u001b[31m-        strcpy(String, \"\\x19\\x88?\");\u001b[m\r\n \t\tStart     = 0;\u001b[m\r\n \t\tbCentered = 1;\u001b[m\r\n \t}\u001b[m\r\n \telse\u001b[m\r\n \t{\u001b[m\r\n \t\tif (gScannerSaveState == SCAN_SAVE_CHAN_SEL) {\u001b[m\r\n\u001b[31m-//\t\t\tstrcpy(String, \"SAVE:\");\u001b[m\r\n\u001b[31m-//            \\x88\\x19\u001b[m\r\n\u001b[31m-//\t\t\tUI_GenerateChannelStringEx(String + 5, gShowChPrefix, gScanChannel);\u001b[m\r\n\u001b[31m-            strcpy(String, \"\\x19\\x88:\");\u001b[m\r\n\u001b[31m-\u001b[m\r\n\u001b[31m-\t\t\tUI_GenerateChannelStringEx(String + 3, gShowChPrefix, gScanChannel);\u001b[m\r\n\u001b[32m+\u001b[m\t\t\t\u001b[32mstrcpy(String, \"SAVE:\");\u001b[m\r\n\u001b[32m+\u001b[m\t\t\t\u001b[32mUI_GenerateChannelStringEx(String + 5, gShowChPrefix, gScanChannel);\u001b[m\r\n \t\t}\u001b[m\r\n \t\telse if (gScanCssState < SCAN_CSS_STATE_FOUND) {\u001b[m\r\n\u001b[31m-\t\t\t//strcpy(String, \"SCAN\");\u001b[m\r\n\u001b[31m-\t\t\t//memset(String + 4, '.', (gScanProgressIndicator & 7) + 1);\u001b[m\r\n\u001b[31m-            strcpy(String, \"\\x8F\\x90\");\u001b[m\r\n\u001b[31m-            memset(String + 2, '.', (gScanProgressIndicator & 7) + 1);\u001b[m\r\n\u001b[32m+\u001b[m\t\t\t\u001b[32mstrcpy(String, \"SCAN\");\u001b[m\r\n\u001b[32m+\u001b[m\t\t\t\u001b[32mmemset(String + 4, '.', (gScanProgressIndicator & 7) + 1);\u001b[m\r\n \t\t}\u001b[m\r\n \t\telse if (gScanCssState == SCAN_CSS_STATE_FOUND)\u001b[m\r\n\u001b[31m-\t\t\t//strcpy(String, \"SCAN CMP.\");\u001b[m\r\n\u001b[31m-        strcpy(String, \"\\x8F\\x90 OK.\");\u001b[m\r\n\u001b[31m-\u001b[m\r\n\u001b[32m+\u001b[m\t\t\t\u001b[32mstrcpy(String, \"SCAN CMP.\");\u001b[m\r\n\u001b[32m+\u001b[m\t\t\u001b[32melse\u001b[m\r\n\u001b[32m+\u001b[m\t\t\t\u001b[32mstrcpy(String, \"SCAN FAIL.\");\u001b[m\r\n \u001b[m\r\n\u001b[31m-        else\u001b[m\r\n\u001b[31m-//\t\t\tstrcpy(String, \"SCAN FAIL.\");\u001b[m\r\n\u001b[31m-            strcpy(String, \"\\x8F\\x90 FAIL.\");\u001b[m\r\n \t\tStart     = 2;\u001b[m\r\n \t\tbCentered = 0;\u001b[m\r\n \t}\u001b[m\r\n"
  },
  {
    "path": "hardware/dp32g030/aes.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[AES]\r\n@ = 0x400BD000, 0x800\r\n\r\nCR = 0x0000\r\n> CCFC, 7, 1\r\n= SET, 1\r\n\r\n> CHMOD, 5, 2\r\n= ECB, 0\r\n= CBC, 1\r\n= CTR, 2\r\n\r\n> EN, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nSR = 0x0004\r\n> CCF, 0, 1\r\n= NOT_COMPLETE, 0\r\n= COMPLETE, 1\r\n\r\nDINR = 0x0008\r\nDOUTR = 0x000C\r\n\r\nKEYR0 = 0x0010\r\nKEYR1 = 0x0014\r\nKEYR2 = 0x0018\r\nKEYR3 = 0x001C\r\n\r\nIVR0 = 0x0020\r\nIVR1 = 0x0024\r\nIVR2 = 0x0028\r\nIVR3 = 0x002C\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/crc.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[CRC]\r\n@ = 0x40003000, 0x800\r\n\r\nCR = 0x0000\r\n> CRC_EN, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> INPUT_REV, 1, 1\r\n= NORMAL, 0\r\n= REVERSED, 1\r\n\r\n> INPUT_INV, 2, 2\r\n= NORMAL, 0\r\n= BIT_INVERTED, 1\r\n= BYTE_INVERTED, 2\r\n= BIT_BYTE_INVERTED, 3\r\n\r\n> OUTPUT_REV, 4, 1\r\n= NORMAL, 0\r\n= REVERSED, 1\r\n\r\n> OUTPUT_INV, 5, 2\r\n= NORMAL, 0\r\n= BIT_INVERTED, 1\r\n= BYTE_INVERTED, 2\r\n= BIT_BYTE_INVERTED, 3\r\n\r\n> DATA_WIDTH, 7, 2\r\n= 32, 0\r\n= 16, 1\r\n= 8, 2\r\n\r\n> CRC_SEL, 9, 2\r\n= CRC_16_CCITT, 0\r\n= CRC_8_ATM, 1\r\n= CRC_16, 2\r\n= CRC_32_IEEE802_3, 3\r\n\r\nIV = 0x0004\r\nDATAIN = 0x0008\r\nDATAOUT = 0x000C\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/dma.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[DMA]\r\n@ = 0x40001000, 0x100\r\n\r\nCTR = 0x0000\r\n> DMAEN, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nINTEN = 0x0004\r\n> CH0_TC_INTEN, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CH1_TC_INTEN, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CH2_TC_INTEN, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CH3_TC_INTEN, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CH0_THC_INTEN, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CH1_THC_INTEN, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CH2_THC_INTEN, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CH3_THC_INTEN, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nINTST = 0x0008\r\n> CH0_TC_INTST, 0, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> CH1_TC_INTST, 1, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> CH2_TC_INTST, 2, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> CH3_TC_INTST, 3, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> CH0_THC_INTST, 8, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> CH1_THC_INTST, 9, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> CH2_THC_INTST, 10, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> CH3_THC_INTST, 11, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n[DMA_CH]\r\n$ = DMA_Channel_t\r\n\r\nCTR = 0x0000\r\n> CH_EN, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> LENGTH, 1, 12\r\n\r\n> LOOP, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> PRI, 14, 2\r\n= LOW, 0\r\n= MEDIUM, 1\r\n= HIGH, 2\r\n= HIGHEST, 3\r\n\r\n> SWREQ, 16, 1\r\n= SET, 1\r\n\r\nMOD = 0x0004\r\n> MS_ADDMOD, 0, 1\r\n= NONE, 0\r\n= INCREMENT, 1\r\n\r\n> MS_SIZE, 1, 2\r\n= 8BIT, 0\r\n= 16BIT, 1\r\n= 32BIT, 2\r\n= KEEP, 3\r\n\r\n> MS_SEL, 3, 3\r\n= SRAM, 0\r\n= HSREQ_MS0, 1\r\n= HSREQ_MS1, 2\r\n= HSREQ_MS2, 3\r\n= HSREQ_MS3, 4\r\n= HSREQ_MS4, 5\r\n= HSREQ_MS5, 6\r\n= HSREQ_MS6, 7\r\n\r\n> MD_ADDMOD, 8, 1\r\n= NONE, 0\r\n= INCREMENT, 1\r\n\r\n> MD_SIZE, 9, 2\r\n= 8BIT, 0\r\n= 16BIT, 1\r\n= 32BIT, 2\r\n= KEEP, 3\r\n\r\n> MD_SEL, 11, 3\r\n= SRAM, 0\r\n= HSREQ_MS0, 1\r\n= HSREQ_MS1, 2\r\n= HSREQ_MS2, 3\r\n= HSREQ_MS3, 4\r\n= HSREQ_MS4, 5\r\n= HSREQ_MS5, 6\r\n= HSREQ_MS6, 7\r\n\r\nMSADDR = 0x0008\r\nMDADDR = 0x000C\r\nST = 0x0010\r\n\r\n[DMA_CH0]\r\n@ = 0x40001100, 0x20, $DMA_CH\r\n\r\n[DMA_CH1]\r\n@ = 0x40001120, 0x20, $DMA_CH\r\n\r\n[DMA_CH2]\r\n@ = 0x40001140, 0x20, $DMA_CH\r\n\r\n[DMA_CH3]\r\n@ = 0x40001160, 0x20, $DMA_CH\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/flash.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[FLASH]\r\n@ = 0x4006F000, 0x800\r\n\r\nCFG = 0x0000\r\n> READ_MD, 0, 1\r\n= 1_CYCLE, 0\r\n= 2_CYCLE, 1\r\n\r\n> NVR_SEL, 1, 1\r\n= MAIN, 0\r\n= NVR, 1\r\n\r\n> MODE, 2, 3\r\n= READ_AHB, 0\r\n= PROGRAM, 1\r\n= ERASE, 2\r\n= READ_APB, 5\r\n\r\n> DEEP_PD, 31, 1\r\n= NORMAL, 0\r\n= LOW_POWER, 1\r\n\r\nADDR = 0x0004\r\nWDATA = 0x0008\r\nRDATA = 0x000C\r\n\r\nSTART = 0x0010\r\n> START, 0, 1\r\n= START, 1\r\n\r\nST = 0x0014\r\n> INIT_BUSY, 0, 1\r\n= COMPLETE, 0\r\n= BUSY, 1\r\n\r\n> BUSY, 1, 1\r\n= READY, 0\r\n= BUSY, 1\r\n\r\n> PROG_BUF_EMPTY, 2, 1\r\n= NOT_EMPTY, 0\r\n= EMPTY, 1\r\n\r\nLOCK = 0x0018\r\n> LOCK, 0, 8\r\n= LOCK, 0x55\r\n\r\nUNLOCK = 0x001C\r\n> UNLOCK, 0, 8\r\n= UNLOCK, 0xAA\r\n\r\nMASK = 0x0020\r\n> SEL, 0, 2\r\n= NONE, 0\r\n= 2KB, 1\r\n= 4KB, 2\r\n= 8KB, 3\r\n\r\n> LOCK, 2, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\nERASETIME = 0x0024\r\n> TERASE, 0, 19\r\n> TRCV, 19, 12\r\n\r\nPROGTIME = 0x0028\r\n> TPROG, 0, 11\r\n> TPGS, 11, 11\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/gpio.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[GPIO]\r\n$ = GPIO_Bank_t\r\n\r\nDATA = 0x0000\r\nDIR = 0x0004\r\n> 0, 0, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 1, 1, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 2, 2, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 3, 3, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 4, 4, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 5, 5, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 6, 6, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 7, 7, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 8, 8, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 9, 9, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 10, 10, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 11, 11, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 12, 12, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 13, 13, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 14, 14, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n> 15, 15, 1\r\n= INPUT, 0\r\n= OUTPUT, 1\r\n\r\n[GPIOA]\r\n@ = 0x40060000, 0x800, $GPIO\r\n\r\n[GPIOB]\r\n@ = 0x40060800, 0x800, $GPIO\r\n\r\n[GPIOC]\r\n@ = 0x40061000, 0x800, $GPIO\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/pmu.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[PMU]\r\n@ = 0x40000800, 0x800\r\n\r\nSRC_CFG = 0x0010\r\n> RCHF_SEL, 1, 1\r\n= 48MHZ, 0\r\n= 24MHZ, 1\r\n\r\n> RCHF_EN, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nTRIM_POW0 = 0x0020\r\nTRIM_POW1 = 0x0024\r\nTRIM_POW2 = 0x0028\r\nTRIM_POW3 = 0x002C\r\n\r\nTRIM_RCHF = 0x0030\r\nTRIM_RCLF = 0x0034\r\nTRIM_OPA = 0x0038\r\nTRIM_PLL = 0x003C\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/portcon.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[PORTCON]\r\n@ = 0x400B0000, 0x800\r\n\r\nPORTA_SEL0 = 0x0000\r\n> A0, 0, 4\r\n= GPIOA0, 0\r\n= PWMP1_PLUS0, 1\r\n= PWMP0_PLUS1, 2\r\n= TM, 3\r\n= WAKEUP0, 4\r\n\r\n> A1, 4, 4\r\n= GPIOA1, 0\r\n= XTAL_XI, 1\r\n\r\n> A2, 8, 4\r\n= GPIOA2, 0\r\n= XTAL_XO, 1\r\n\r\n> A3, 12, 4\r\n= GPIOA3, 0\r\n= CMP0_VN, 1\r\n= XTAH_XI, 2\r\n\r\n> A4, 16, 4\r\n= GPIOA4, 0\r\n= CMP0_VP, 1\r\n= XTAH_XO, 2\r\n\r\n> A5, 20, 4\r\n= GPIOA5, 0\r\n= UART1_CTS, 1\r\n= PWMP1_PLUS1, 2\r\n= TIMERP1_IN0, 3\r\n= TIMERP1_OUT_L, 4\r\n= WAKEUP1, 5\r\n= SARADC_CH1, 6\r\n\r\n> A6, 24, 4\r\n= GPIOA6, 0\r\n= UART1_RTS, 1\r\n= TIMERP1_IN1, 2\r\n= TIMERP1_OUT_H, 3\r\n= SARADC_CH1, 4\r\n= OPA0_OUT, 5\r\n\r\n> A7, 28, 4\r\n= GPIOA7, 0\r\n= UART1_TX, 1\r\n= TIMERP0_IN0, 2\r\n= TIMERP0_OUT_L, 3\r\n= SARADC_CH2, 4\r\n= OPA0_VP, 5\r\n\r\nPORTA_SEL1  = 0x0004\r\n> A8, 0, 4\r\n= GPIOA8, 0\r\n= UART1_RX, 1\r\n= TIMERP0_IN1, 2\r\n= TIMERP0_OUT_H, 3\r\n= SARADC_CH3, 4\r\n= OPA0_VN, 5\r\n\r\n> A9, 4, 4\r\n= GPIOA9, 0\r\n= SPI0_SSN, 1\r\n= TIMERP1_IN0, 2\r\n= TIMERP1_OUT_L, 3\r\n= TM, 4\r\n= SARADC_CH4, 5\r\n= CMP1_VN, 6\r\n\r\n> A10, 8, 4\r\n= GPIOA10, 0\r\n= SPI0_CLK, 1\r\n= SARADC_CH5, 2\r\n= CMP1_VP, 3\r\n\r\n> A11, 12, 4\r\n= GPIOA11, 0\r\n= SPI0_MISO, 1\r\n= PWMB0_CH0, 2\r\n= PWMP0_BRAKE0, 3\r\n= TIMERP1_IN1, 4\r\n= TIMERP1_OUT_H, 5\r\n= SARADC_CH6, 6\r\n\r\n> A12, 16, 4\r\n= GPIOA12, 0\r\n= SPI0_MOSI, 1\r\n= PWMB0_CH1, 2\r\n= PWMP0_CH0N, 3\r\n= TIMERP0_IN0, 4\r\n= TIMERP0_OUT_L, 5\r\n= SARADC_CH7, 6\r\n\r\n> A13, 20, 4\r\n= GPIOA13, 0\r\n= PWMB0_CH2, 1\r\n= PWMP0_CH1N, 2\r\n= TIMERP0_IN1, 3\r\n= TIMERP0_OUT_H, 4\r\n= SARADC_CH8, 5\r\n\r\n> A14, 24, 4\r\n= GPIOA14, 0\r\n= PWMB1_CH0, 1\r\n= PWMP0_CH2N, 2\r\n= TIMERP1_IN0, 3\r\n= TIMERP1_OUT_L, 4\r\n= SARADC_CH9, 5\r\n\r\n> A15, 28, 4\r\n= GPIOA15, 0\r\n= PWMB1_CH1, 1\r\n= PWMP0_CH0, 2\r\n= TIMERP1_IN1, 3\r\n= TIMERP1_OUT_H, 4\r\n\r\nPORTB_SEL0 = 0x0008\r\n> B0, 0, 4\r\n= GPIOB0, 0\r\n= UART2_TX, 1\r\n= IIC0_SCL, 2\r\n= PWMB1_CH2, 3\r\n= PWMP0_CH1, 4\r\n\r\n> B1, 4, 4\r\n= GPIOB1, 0\r\n= UART2_RX, 1\r\n= IIC0_SDA, 2\r\n= PWMP0_CH2, 3\r\n\r\n> B2, 8, 4\r\n= GPIOB2, 0\r\n= SPI1_SSN, 1\r\n= PWMP0_BRAKE1, 2\r\n= TIMERP1_HALL0, 3\r\n\r\n> B3, 12, 4\r\n= GPIOB3, 0\r\n= SPI1_CLK, 1\r\n= IIC1_SDA, 2\r\n= PWMP0_CH0N, 3\r\n= TIMERP1_HALL1, 4\r\n\r\n> B4, 16, 4\r\n= GPIOB4, 0\r\n= SPI1_MISO, 1\r\n= IIC1_SCL, 2\r\n= PWMP1_CH0, 3\r\n= PWMP0_CH1N, 4\r\n= TIMERP1_HALL2, 5\r\n\r\n> B5, 20, 4\r\n= GPIOB5, 0\r\n= SPI1_MOSI, 1\r\n= PWMP1_CH0N, 2\r\n= PWMP0_CH2N, 3\r\n= TIMERP0_IN0, 4\r\n= TIMERP0_OUT_L, 5\r\n\r\n> B6, 24, 4\r\n= GPIOB6, 0\r\n= PWMP0_CH0, 1\r\n= TIMERP0_IN1, 2\r\n= TIMERP0_OUT_H, 3\r\n\r\n> B7, 28, 4\r\n= GPIOB7, 0\r\n= SPI0_SSN, 1\r\n= UART0_TX, 2\r\n= IIC0_SCL, 3\r\n= PWMP1_BRAKE0, 4\r\n= PWMP0_CH1, 5\r\n\r\nPORTB_SEL1 = 0x000C\r\n> B8, 0, 4\r\n= GPIOB8, 0\r\n= SPI0_CLK, 1\r\n= UART0_RX, 2\r\n= IIC0_SDA, 3\r\n= PWMB0_CH0, 4\r\n= PWMP1_BRAKE1, 5\r\n= PWMP0_CH2, 6\r\n\r\n> B9, 4, 4\r\n= GPIOB9, 0\r\n= SPI0_MISO, 1\r\n= UART0_CTS, 2\r\n= PWMB0_CH1, 3\r\n= PWMP1_CH0, 4\r\n= TIMERP1_IN1, 5\r\n= TIMERP1_OUT_H, 6\r\n\r\n> B10, 8, 4\r\n= GPIOB10, 0\r\n= SPI0_MOSI, 1\r\n= UART0_RTS, 2\r\n= PWMB0_CH2, 3\r\n= PWMP1_CH1, 4\r\n= PWMP0_PLUS0, 5\r\n= TIMERP1_IN0, 6\r\n= TIMERP1_OUT_L, 7\r\n\r\n> B11, 12, 4\r\n= GPIOB11, 0\r\n= SWDIO, 1\r\n= PWMP1_CH2, 2\r\n= PWMP0_BRAKE2, 3\r\n\r\n> B12, 16, 4\r\n= GPIOB12, 0\r\n= UART1_TX, 1\r\n= IIC1_SCL, 2\r\n= PWMP1_CH0N, 3\r\n\r\n> B13, 20, 4\r\n= GPIOB13, 0\r\n= UART1_RX, 1\r\n= IIC1_SDA, 2\r\n= PWMP1_CH1N, 3\r\n\r\n> B14, 24, 4\r\n= GPIOB14, 0\r\n= SWCLK, 1\r\n= UART2_TX, 2\r\n= PWMP1_CH2N, 3\r\n\r\n> B15, 28, 4\r\n= GPIOB15, 0\r\n= SPI1_SSN, 1\r\n= UART2_RX, 2\r\n\r\nPORTC_SEL0 = 0x0010\r\n> C0, 0, 4\r\n= GPIOC0, 0\r\n= SPI1_CLK, 1\r\n= UART2_CTS, 2\r\n= PWMB1_CH0, 3\r\n\r\n> C1, 4, 4\r\n= GPIOC1, 0\r\n= SPI1_MISO, 1\r\n= UART2_RTS, 2\r\n= PWMB1_CH1, 3\r\n= TIMERP0_IN0, 4\r\n= TIMERP0_OUT_L, 5\r\n\r\n> C2, 8, 4\r\n= GPIOC2, 0\r\n= SPI1_MOSI, 1\r\n= PWMB1_CH2, 2\r\n= PWMP1_BRAKE2, 3\r\n= TIMERP0_IN1, 4\r\n= TIMERP0_OUT_H, 5\r\n\r\n> C3, 12, 4\r\n= GPIOC3, 0\r\n= UART0_TX, 1\r\n= IIC0_SCL, 2\r\n= PWMP1_CH1N, 3\r\n= TIMERP0_HALL0, 4\r\n= CMP2_VN, 5\r\n\r\n> C4, 16, 4\r\n= GPIOC4, 0\r\n= UART0_RX, 1\r\n= IIC0_SDA, 2\r\n= PWMP1_CH2N, 3\r\n= TIMERP0_HALL1, 4\r\n= CMP2_VP, 5\r\n\r\n> C5, 20, 4\r\n= GPIOC5, 0\r\n= TIMERP0_HALL2, 1\r\n= TM, 2\r\n= OPA1_VP, 3\r\n\r\n> C6, 24, 4\r\n= GPIOC6, 0\r\n= IIC1_SCL, 1\r\n= PWMP1_CH1, 2\r\n= TIMERP1_IN1, 3\r\n= TIMERP1_OUT_H, 4\r\n= OPA1_VN, 5\r\n\r\n> C7, 28, 4\r\n= GPIOC7, 0\r\n= IIC1_SDA, 1\r\n= PWMP1_CH2, 2\r\n= TIMERP1_IN0, 3\r\n= TIMERP1_OUT_L, 4\r\n= OPA1_OUT, 5\r\n\r\nPORTA_IE = 0x0100\r\n> A0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTB_IE = 0x0104\r\n> B0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTC_IE = 0x0108\r\n> C0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTA_PU = 0x0200\r\n> A0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTB_PU = 0x0204\r\n> B0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTC_PU = 0x0208\r\n> C0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTA_PD = 0x0300\r\n> A0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTB_PD = 0x0304\r\n> B0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTC_PD = 0x0308\r\n> C0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTA_OD = 0x0400\r\n> A0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> A15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTB_OD = 0x0404\r\n> B0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> B15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nPORTC_OD = 0x0408\r\n> C0, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C1, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C2, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C3, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C4, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C5, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C6, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C7, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C8, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C9, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C10, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C11, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C12, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C13, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C14, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> C15, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/saradc.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[SARADC]\r\n@ = 0x400BA000, 0x800\r\n\r\nCFG = 0x0000\r\n> CH_SEL, 0, 15\r\n\r\n> AVG, 16, 2\r\n= 1_SAMPLE, 0\r\n= 2_SAMPLE, 1\r\n= 4_SAMPLE, 2\r\n= 8_SAMPLE, 3\r\n\r\n> CONT, 18, 1\r\n= SINGLE, 0\r\n= CONTINUOUS, 1\r\n\r\n> SMPL_SETUP, 19, 3\r\n= 1_CYCLE, 0\r\n= 2_CYCLE, 1\r\n= 4_CYCLE, 2\r\n= 8_CYCLE, 3\r\n= 16_CYCLE, 4\r\n= 32_CYCLE, 5\r\n= 64_CYCLE, 6\r\n= 128_CYCLE, 7\r\n\r\n> MEM_MODE, 22, 1\r\n= FIFO, 0\r\n= CHANNEL, 1\r\n\r\n> SMPL_CLK, 23, 1\r\n= EXTERNAL, 0\r\n= INTERNAL, 1\r\n\r\n> SMPL_WIN, 24, 3\r\n= 1_CYCLE, 0\r\n= 3_CYCLE, 1\r\n= 5_CYCLE, 2\r\n= 7_CYCLE, 3\r\n= 9_CYCLE, 4\r\n= 11_CYCLE, 5\r\n= 13_CYCLE, 6\r\n= 15_CYCLE, 7\r\n\r\n> ADC_EN, 27, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> ADC_TRIG, 28, 1\r\n= CPU, 0\r\n= EXTERNAL, 1\r\n\r\n> DMA_EN, 29, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nSTART = 0x0004\r\n> START, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> SOFT_RESET, 2, 1\r\n= ASSERT, 0\r\n= DEASSERT, 1\r\n\r\nIE = 0x0008\r\n> CHx_EOC, 0, 16\r\n= NONE, 0x0000\r\n= ALL, 0xFFFF\r\n\r\n> FIFO_FULL, 16, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> FIFO_HFULL, 17, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nIF = 0x000C\r\n> CHx_EOC, 0, 16\r\n\r\n> FIFO_FULL, 16, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> FIFO_HFULL, 17, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\nCH0 = 0x0010\r\n\r\nEXTTRIG_SEL = 0x00B0\r\n\r\nCALIB_OFFSET = 0x00F0\r\n> OFFSET, 0, 8\r\n> VALID, 16, 1\r\n= NO, 0\r\n= YES, 1\r\n\r\nCALIB_KD = 0x00F4\r\n> KD, 0, 8\r\n> VALID, 16, 1\r\n= NO, 0\r\n= YES, 1\r\n\r\n[ADC_CHx]\r\n$ = ADC_Channel_t\r\n\r\nSTAT = 0x0000\r\n> EOC, 0, 1\r\n= NOT_COMPLETE, 0\r\n= COMPLETE, 1\r\n\r\nDATA = 0x0004\r\n> DATA, 0, 12\r\n> NUM, 12, 4\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/spi.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[SPI]\r\n$ = SPI_Port_t\r\n\r\nCR = 0x0000\r\n> TF_CLR, 16, 1\r\n> RF_CLR, 15, 1\r\n> TXDMAEN, 14, 1\r\n> RXDMAEN, 13, 1\r\n\r\n> MSR_SSN, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CPHA_DATA_HOLD_S, 8, 4\r\n> LSB, 7, 1\r\n> MSTR, 6, 1\r\n> CPOL, 5, 1\r\n> CPHA, 4, 1\r\n\r\n> SPE, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> SPR, 0, 3\r\n= FPCLK_DIV_4, 0\r\n= FPCLK_DIV_8, 1\r\n= FPCLK_DIV_16, 2\r\n= FPCLK_DIV_32, 3\r\n= FPCLK_DIV_64, 4\r\n= FPCLK_DIV_128, 5\r\n= FPCLK_DIV_256, 6\r\n= FPCLK_DIV_512, 7\r\n\r\nWDR = 0x0004\r\nRDR = 0x0008\r\n\r\nIE = 0x0010\r\n> RXFIFO_OVF, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> RXFIFO_FULL, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> RXFIFO_HFULL, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TXFIFO_EMPTY, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TXFIFO_HFULL, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nIF = 0x0014\r\nFIFOST = 0x0018\r\n> RFE, 0, 1\r\n= NOT_EMPTY, 0\r\n= EMPTY, 1\r\n\r\n> RFF, 1, 1\r\n= NOT_FULL, 0\r\n= FULL, 1\r\n\r\n> RFHF, 2, 1\r\n= NOT_HALF_FULL, 0\r\n= HALF_FULL, 1\r\n\r\n> TFE, 3, 1\r\n= NOT_EMPTY, 0\r\n= EMPTY, 1\r\n\r\n> TFF, 4, 1\r\n= NOT_FULL, 0\r\n= FULL, 1\r\n\r\n> TFHF, 5, 1\r\n= NOT_HALF_FULL,                   0\r\n= HALF_FULL,                       1\r\n\r\n> RF_LEVEL, 6, 3\r\n= 0_BYTE, 0\r\n= 1_BYTE, 1\r\n= 2_BYTE, 2\r\n= 3_BYTE, 3\r\n= 4_BYTE, 4\r\n= 5_BYTE, 5\r\n= 6_BYTE, 6\r\n= 7_BYTE, 7\r\n\r\n> TF_LEVEL, 9, 3\r\n= 0_BYTE, 0\r\n= 1_BYTE, 1\r\n= 2_BYTE, 2\r\n= 3_BYTE, 3\r\n= 4_BYTE, 4\r\n= 5_BYTE, 5\r\n= 6_BYTE, 6\r\n= 7_BYTE, 7\r\n\r\n[SPI0]\r\n@ = 0x400B8000, 0x800, $SPI\r\n\r\n[SPI1]\r\n@ = 0x400B8800, 0x800, $SPI\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/syscon.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[SYSCON]\r\n@ = 0x40000000, 0x800\r\n\r\nCLK_SEL = 0x0000\r\n> SYS, 0, 1\r\n= RCHF, 0\r\n= DIV_CLK, 1\r\n\r\n> DIV, 1, 3\r\n= 1, 0\r\n= 2, 1\r\n= 4, 2\r\n= 8, 3\r\n= 16, 4\r\n= 32, 5\r\n\r\n> SRC, 4, 3\r\n= RCHF, 0\r\n= RCLF, 1\r\n= XTAH, 2\r\n= XTAL, 3\r\n= PLL, 4\r\n\r\n> W_PLL, 7, 1\r\n= RCHF, 0\r\n= XTAH, 1\r\n\r\n# The documentation doesn't match the firmware!\r\n> R_SARADC_SMPL, 9, 2\r\n= DIV1, 0\r\n= DIV2, 1\r\n= DIV4, 2\r\n= DIV8, 3\r\n\r\n> W_SARADC_SMPL, 10, 2\r\n= DIV1, 0\r\n= DIV2, 1\r\n= DIV4, 2\r\n= DIV8, 3\r\n\r\n> R_PLL, 11, 1\r\n= RCHF, 0\r\n= XTAH, 1\r\n\r\nDIV_CLK_GATE = 0x0004\r\n> DIV_CLK_GATE, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nDEV_CLK_GATE = 0x0008\r\n> GPIOA, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> GPIOB, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> GPIOC, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> IIC0, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> IIC1, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> UART0, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> UART1, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> UART2, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> SPI0, 10, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> SPI1, 11, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TIMER_BASE0, 12, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TIMER_BASE1, 13, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TIMER_BASE2, 14, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TIMER_PLUS0, 15, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TIMER_PLUS1, 16, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> PWM_BASE0, 17, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> PWM_BASE1, 18, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> PWM_PLUS0, 20, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> PWM_PLUS1, 21, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> RTC, 22, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> IWDT, 23, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> WWDT, 24, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> SARADC, 25, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CRC, 27, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> AES, 28, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nRC_FREQ_DELTA = 0x0078\r\n> RCLF_DELTA, 0, 10\r\n> RCLF_SIG, 10, 1\r\n> RCHF_DELTA, 11, 20\r\n> RCHF_SIG, 31, 1\r\n\r\nVREF_VOLT_DELTA = 0x007C\r\n\r\nCHIP_ID0 = 0x0080\r\nCHIP_ID1 = 0x0084\r\nCHIP_ID2 = 0x0088\r\nCHIP_ID3 = 0x008C\r\n\r\n"
  },
  {
    "path": "hardware/dp32g030/uart.def",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n[UART]\r\n$ = UART_Port_t\r\n\r\nCTRL = 0x0000\r\n> UARTEN, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> RXEN, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TXEN, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> RXDMAEN, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TXDMAEN, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> NINEBIT, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> PAREN, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nBAUD = 0x0004\r\nTDR = 0x0008\r\nRDR = 0x000C\r\n\r\nIE = 0x0010\r\n> TXDONE, 2, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> PARITYE, 3, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> STOPE, 4, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> RXTO, 5, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> RXFIFO, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TXFIFO, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> RXFIFO_OVF, 8, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> ABRD_OVF, 9, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nIF = 0x0014\r\n> TXDONE, 2, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> PARITYE, 3, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> STOPE, 4, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> RXTO, 5, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> RXFIFO, 6, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> TXFIFO, 7, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> RXFIFO_OVF, 8, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> ABRD_OVF, 9, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> RXFIFO_EMPTY, 10, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> RXFIFO_FULL, 11, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> RXFIFO_HFULL, 12, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> TXFIFO_EMPTY, 13, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> TXFIFO_FULL, 14, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> TXFIFO_HFULL, 15, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> TXBUSY, 16, 1\r\n= NOT_SET, 0\r\n= SET, 1\r\n\r\n> RF_LEVEL, 17, 3\r\n= 0_8_BYTE, 0\r\n= 1_BYTE, 1\r\n= 2_BYTE, 2\r\n= 3_BYTE, 3\r\n= 4_BYTE, 4\r\n= 5_BYTE, 5\r\n= 6_BYTE, 6\r\n= 7_BYTE, 7\r\n\r\n> TF_LEVEL, 20, 3\r\n= 0_8_BYTE, 0\r\n= 1_BYTE, 1\r\n= 2_BYTE, 2\r\n= 3_BYTE, 3\r\n= 4_BYTE, 4\r\n= 5_BYTE, 5\r\n= 6_BYTE, 6\r\n= 7_BYTE, 7\r\n\r\nFIFO = 0x0018\r\n> RF_LEVEL, 0, 3\r\n= 1_BYTE, 0\r\n= 2_BYTE, 1\r\n= 3_BYTE, 2\r\n= 4_BYTE, 3\r\n= 5_BYTE, 4\r\n= 6_BYTE, 5\r\n= 7_BYTE, 6\r\n= 8_BYTE, 7\r\n\r\n> TF_LEVEL, 3, 3\r\n= 0_BYTE, 0\r\n= 1_BYTE, 1\r\n= 2_BYTE, 2\r\n= 3_BYTE, 3\r\n= 4_BYTE, 4\r\n= 5_BYTE, 5\r\n= 6_BYTE, 6\r\n= 7_BYTE, 7\r\n\r\n> RF_CLR, 6, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> TF_CLR, 7, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\nFC = 0x001C\r\n> CTSEN, 0, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> RTSEN, 1, 1\r\n= DISABLE, 0\r\n= ENABLE, 1\r\n\r\n> CTSPOL, 2, 1\r\n= LOW, 0\r\n= HIGH, 1\r\n\r\n> RTSPOL, 3, 1\r\n= LOW, 0\r\n= HIGH, 1\r\n\r\n> CTS_SIGNAL, 4, 1\r\n= LOW, 0\r\n= HIGH, 1\r\n\r\n> RTS_SIGNAL, 5, 1\r\n= LOW, 0\r\n= HIGH, 1\r\n\r\nRXTO = 0x0020\r\n\r\n[UART0]\r\n@ = 0x4006B000, 0x800, $UART\r\n\r\n[UART1]\r\n@ = 0x4006B800, 0x800, $UART\r\n\r\n[UART2]\r\n@ = 0x4006C000, 0x800, $UART\r\n\r\n"
  },
  {
    "path": "helper/battery.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"battery.h\"\r\n#include \"driver/backlight.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"functions.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/battery.h\"\r\n#include \"ui/menu.h\"\r\n#include \"ui/ui.h\"\r\n\r\nuint16_t gBatteryCalibration[6];\r\nuint16_t gBatteryCurrentVoltage;\r\nuint16_t gBatteryCurrent;\r\nuint16_t gBatteryVoltages[4];\r\nuint16_t gBatteryVoltageAverage;\r\nuint8_t gBatteryDisplayLevel;\r\nbool gChargingWithTypeC;\r\nbool gLowBatteryBlink;\r\nbool gLowBattery;\r\nbool gLowBatteryConfirmed;\r\nuint16_t gBatteryCheckCounter;\r\n\r\ntypedef enum {\r\n    BATTERY_LOW_INACTIVE,\r\n    BATTERY_LOW_ACTIVE,\r\n    BATTERY_LOW_CONFIRMED\r\n} BatteryLow_t;\r\n\r\n\r\nuint16_t lowBatteryCountdown;\r\nconst uint16_t lowBatteryPeriod = 30;\r\n\r\nvolatile uint16_t gPowerSave_10ms;\r\n\r\n\r\nconst uint16_t Voltage2PercentageTable[][7][2] = {\r\n        [BATTERY_TYPE_1600_MAH] = {\r\n                {828, 100},\r\n                {814, 97},\r\n                {760, 25},\r\n                {729, 6},\r\n                {630, 0},\r\n                {0,   0},\r\n                {0,   0},\r\n        },\r\n\r\n        [BATTERY_TYPE_2200_MAH] = {\r\n                {832, 100},\r\n                {813, 95},\r\n                {740, 60},\r\n                {707, 21},\r\n                {682, 5},\r\n                {630, 0},\r\n                {0,   0},\r\n        },\r\n};\r\n\r\nstatic_assert(ARRAY_SIZE(Voltage2PercentageTable[BATTERY_TYPE_1600_MAH]) ==\r\n              ARRAY_SIZE(Voltage2PercentageTable[BATTERY_TYPE_2200_MAH]));\r\n\r\n\r\nunsigned int BATTERY_VoltsToPercent(const unsigned int voltage_10mV) {\r\n    const uint16_t (*crv)[2] = Voltage2PercentageTable[gEeprom.BATTERY_TYPE];\r\n    const int mulipl = 1000;\r\n    for (unsigned int i = 1; i < ARRAY_SIZE(Voltage2PercentageTable[BATTERY_TYPE_2200_MAH]); i++) {\r\n        if (voltage_10mV > crv[i][0]) {\r\n            const int a = (crv[i - 1][1] - crv[i][1]) * mulipl / (crv[i - 1][0] - crv[i][0]);\r\n            const int b = crv[i][1] - a * crv[i][0] / mulipl;\r\n            const int p = a * voltage_10mV / mulipl + b;\r\n            return MIN(p, 100);\r\n        }\r\n    }\r\n\r\n    return 0;\r\n}\r\n\r\nvoid BATTERY_GetReadings(const bool bDisplayBatteryLevel) {\r\n    const uint8_t PreviousBatteryLevel = gBatteryDisplayLevel;\r\n    const uint16_t Voltage =\r\n            (gBatteryVoltages[0] + gBatteryVoltages[1] + gBatteryVoltages[2] + gBatteryVoltages[3]) / 4;\r\n\r\n    gBatteryVoltageAverage = (Voltage * 760) / gBatteryCalibration[3];\r\n\r\n    if (gBatteryVoltageAverage > 890)\r\n        gBatteryDisplayLevel = 7; // battery overvoltage\r\n    else if (gBatteryVoltageAverage < 630)\r\n        gBatteryDisplayLevel = 0; // battery critical\r\n    else {\r\n        gBatteryDisplayLevel = 1;\r\n        const uint8_t levels[] = {5, 17, 41, 65, 88};\r\n        uint8_t perc = BATTERY_VoltsToPercent(gBatteryVoltageAverage);\r\n        for (uint8_t i = 6; i >= 1; i--) {\r\n            if (perc > levels[i - 2]) {\r\n                gBatteryDisplayLevel = i;\r\n                break;\r\n            }\r\n        }\r\n    }\r\n\r\n\r\n    if ((gScreenToDisplay == DISPLAY_MENU))\r\n        gUpdateDisplay = true;\r\n\r\n    if (gBatteryCurrent < 501) {\r\n        if (gChargingWithTypeC) {\r\n            gUpdateStatus = true;\r\n            gUpdateDisplay = true;\r\n        }\r\n\r\n        gChargingWithTypeC = false;\r\n    } else {\r\n        if (!gChargingWithTypeC) {\r\n            gUpdateStatus = true;\r\n            gUpdateDisplay = true;\r\n            BACKLIGHT_TurnOn();\r\n        }\r\n\r\n        gChargingWithTypeC = true;\r\n    }\r\n\r\n    if (PreviousBatteryLevel != gBatteryDisplayLevel) {\r\n        if (gBatteryDisplayLevel > 2)\r\n            gLowBatteryConfirmed = false;\r\n        else if (gBatteryDisplayLevel < 2) {\r\n            gLowBattery = true;\r\n        } else {\r\n            gLowBattery = false;\r\n\r\n            if (bDisplayBatteryLevel)\r\n                UI_DisplayBattery(gBatteryDisplayLevel, gLowBatteryBlink);\r\n        }\r\n\r\n        if (!gLowBatteryConfirmed)\r\n            gUpdateDisplay = true;\r\n\r\n        lowBatteryCountdown = 0;\r\n    }\r\n}\r\n\r\nvoid BATTERY_TimeSlice500ms(void) {\r\n    if (!gLowBattery) {\r\n        return;\r\n    }\r\n\r\n    gLowBatteryBlink = ++lowBatteryCountdown & 1;\r\n\r\n    UI_DisplayBattery(0, gLowBatteryBlink);\r\n\r\n    if (gCurrentFunction == FUNCTION_TRANSMIT) {\r\n        return;\r\n    }\r\n\r\n    // not transmitting\r\n\r\n    if (lowBatteryCountdown < lowBatteryPeriod) {\r\n#ifdef    ENABLE_WARNING\r\n\r\n        if (lowBatteryCountdown == lowBatteryPeriod-1 && !gChargingWithTypeC && !gLowBatteryConfirmed) {\r\n\r\n            AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP);\r\n        }\r\n#endif\r\n        return;\r\n    }\r\n\r\n    lowBatteryCountdown = 0;\r\n\r\n    if (gChargingWithTypeC) {\r\n        return;\r\n    }\r\n\r\n    // not on charge\r\n    if (!gLowBatteryConfirmed) {\r\n        AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP);\r\n#ifdef ENABLE_VOICE\r\n        AUDIO_SetVoiceID(0, VOICE_ID_LOW_VOLTAGE);\r\n#endif\r\n    }\r\n\r\n    if (gBatteryDisplayLevel != 0) {\r\n#ifdef ENABLE_VOICE\r\n        AUDIO_PlaySingleVoice(false);\r\n#endif\r\n        return;\r\n    }\r\n\r\n#ifdef ENABLE_VOICE\r\n    AUDIO_PlaySingleVoice(true);\r\n#endif\r\n\r\n    gReducedService = true;\r\n\r\n    FUNCTION_Select(FUNCTION_POWER_SAVE);\r\n\r\n    ST7565_HardwareReset();\r\n\r\n    if (gEeprom.BACKLIGHT_TIME < (ARRAY_SIZE(gSubMenu_BACKLIGHT) - 1)) {\r\n        BACKLIGHT_TurnOff();\r\n    }\r\n}"
  },
  {
    "path": "helper/battery.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef BATTERY_H\r\n#define BATTERY_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\nextern uint16_t          gBatteryCalibration[6];\r\nextern uint16_t          gBatteryCurrentVoltage;\r\nextern uint16_t          gBatteryCurrent;\r\nextern uint16_t          gBatteryVoltages[4];\r\nextern uint16_t          gBatteryVoltageAverage;\r\nextern uint8_t           gBatteryDisplayLevel;\r\nextern bool              gChargingWithTypeC;\r\nextern bool              gLowBatteryBlink;\r\nextern bool              gLowBattery;\r\nextern bool              gLowBatteryConfirmed;\r\nextern uint16_t          gBatteryCheckCounter;\r\n\r\nextern volatile uint16_t gPowerSave_10ms;\r\n\r\ntypedef enum {\r\n    BATTERY_TYPE_1600_MAH,\r\n    BATTERY_TYPE_2200_MAH,\r\n    BATTERY_TYPE_UNKNOWN\r\n} BATTERY_Type_t;\r\n\r\n\r\nunsigned int BATTERY_VoltsToPercent(unsigned int voltage_10mV);\r\nvoid BATTERY_GetReadings(bool bDisplayBatteryLevel);\r\nvoid BATTERY_TimeSlice500ms(void);\r\n\r\n#endif"
  },
  {
    "path": "helper/boot.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <string.h>\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n#include \"app/aircopy.h\"\r\n#endif\r\n\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/keyboard.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/system.h\"\r\n#include \"helper/boot.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"settings.h\"\r\n#include \"ui/menu.h\"\r\n#include \"ui/ui.h\"\r\n\r\nBOOT_Mode_t BOOT_GetMode(void) {\r\n    unsigned int i;\r\n    KEY_Code_t Keys[2];\r\n\r\n    for (i = 0; i < 2; i++) {\r\n\r\n        Keys[i] = KEYBOARD_Poll();\r\n        SYSTEM_DelayMs(20);\r\n    }\r\n\r\n    if (Keys[0] == Keys[1]) {\r\n        gKeyReading0 = Keys[0];\r\n        gKeyReading1 = Keys[0];\r\n\r\n        gDebounceCounter = 2;\r\n\r\n        if (Keys[0] == KEY_SIDE1)\r\n            return BOOT_MODE_F_LOCK;\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n        if (Keys[0] == KEY_SIDE2)\r\n            return BOOT_MODE_AIRCOPY;\r\n#endif\r\n    }\r\n\r\n    return BOOT_MODE_NORMAL;\r\n}\r\n\r\nvoid BOOT_ProcessMode(/*BOOT_Mode_t Mode*/) {\r\n    return;\r\n//\r\n//\tif (Mode == BOOT_MODE_F_LOCK)\r\n//\t{\r\n//\t\tGUI_SelectNextDisplay(DISPLAY_MENU);\r\n//\t}\r\n//\t#ifdef ENABLE_AIRCOPY\r\n//\t\telse\r\n//\t\tif (Mode == BOOT_MODE_AIRCOPY)\r\n//\t\t{\r\n//\t\t\tgEeprom.DUAL_WATCH               = DUAL_WATCH_OFF;\r\n//\t\t\tgEeprom.BATTERY_SAVE             = 0;\r\n//\t\t\t#ifdef ENABLE_VOX\r\n//\t\t\t\tgEeprom.VOX_SWITCH           = false;\r\n//\t\t\t#endif\r\n//\t\t\tgEeprom.CROSS_BAND_RX_TX         = CROSS_BAND_OFF;\r\n//\t\t\tgEeprom.AUTO_KEYPAD_LOCK         = false;\r\n//\t\t\tgEeprom.KEY_1_SHORT_PRESS_ACTION = ACTION_OPT_NONE;\r\n//\t\t\tgEeprom.KEY_1_LONG_PRESS_ACTION  = ACTION_OPT_NONE;\r\n//\t\t\tgEeprom.KEY_2_SHORT_PRESS_ACTION = ACTION_OPT_NONE;\r\n//\t\t\tgEeprom.KEY_2_LONG_PRESS_ACTION  = ACTION_OPT_NONE;\r\n//\t\t\tgEeprom.KEY_M_LONG_PRESS_ACTION  = ACTION_OPT_NONE;\r\n//\r\n//\t\t\tRADIO_InitInfo(gRxVfo, FREQ_CHANNEL_LAST - 1, 41002500);\r\n//\r\n//\t\t\tgRxVfo->CHANNEL_BANDWIDTH        = BANDWIDTH_WIDE;\r\n//\t\t\tgRxVfo->OUTPUT_POWER             = OUTPUT_POWER_LOW;\r\n//\r\n//\t\t\tRADIO_ConfigureSquelchAndOutputPower(gRxVfo);\r\n//\r\n//\t\t\tgCurrentVfo = gRxVfo;\r\n//\r\n//\t\t\tRADIO_SetupRegisters(true);\r\n//\t\t\tBK4819_SetupAircopy();\r\n//\t\t\tBK4819_ResetFSK();\r\n//\r\n//\t\t\tgAircopyState = AIRCOPY_READY;\r\n//\r\n//\t\t\tGUI_SelectNextDisplay(DISPLAY_AIRCOPY);\r\n//\t\t}\r\n//\t#endif\r\n//\telse\r\n//\t{\r\n//\t\tGUI_SelectNextDisplay(DISPLAY_MAIN);\r\n//\t}\r\n}\r\n"
  },
  {
    "path": "helper/boot.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef HELPER_BOOT_H\r\n#define HELPER_BOOT_H\r\n\r\n#include <stdint.h>\r\n#include \"driver/keyboard.h\"\r\n\r\nenum BOOT_Mode_t\r\n{\r\n\tBOOT_MODE_NORMAL = 0,\r\n\tBOOT_MODE_F_LOCK,\r\n\t#ifdef ENABLE_AIRCOPY\r\n\t\tBOOT_MODE_AIRCOPY\r\n\t#endif\r\n};\r\n\r\ntypedef enum BOOT_Mode_t BOOT_Mode_t;\r\n\r\nBOOT_Mode_t BOOT_GetMode(void);\r\nvoid BOOT_ProcessMode(/*BOOT_Mode_t Mode*/);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "helper/rds.c",
    "content": "#include \"rds.h\"\n#include \"../driver/si473x.h\"\n#include <string.h>\n\nsi47x_rds_status rdsResponse = {0};\n\nenum {\n  PI_H = 4, // Also \"Block A\"\n  PI_L,\n  Block_B_H,\n  Block_B_L,\n  Block_C_H,\n  Block_C_L,\n  Block_D_H,\n  Block_D_L\n};\n\n#define MAKE_WORD(hb, lb) (((uint8_t)(hb) << 8U) | (uint8_t)lb)\n\nenum { NO_DATE_TIME = 127 };\nRDS rds = {.offset = NO_DATE_TIME};\n\nenum {\n  RDS_THRESHOLD = 3,     // Threshold for larger variables\n  RDS_BOOL_THRESHOLD = 7 // Threshold for boolean variables\n};\n\nstatic char make_printable(char ch) {\n  // Replace non-ASCII char with space\n  if (ch < 32 || 126 < ch)\n    ch = ' ';\n  return ch;\n}\n\n/* RDS and RBDS data */\nstatic ternary _abRadioText;       // Indicates new radioText[] string\nstatic ternary _abProgramTypeName; // Indicates new programTypeName[] string\n/* RDS data counters */\nstatic uint8_t _extendedCountryCode_count;\nstatic uint8_t _language_count;\n\nvoid SI47XX_ClearRDS() {\n  memset(&rds, 0, sizeof(RDS));\n  rds.offset = NO_DATE_TIME;\n}\n\nbool  SI47XX_GetRDS() {\n\n  bool new_info = false;\n  uint8_t segment;\n\n  while (1) {\n    SI47XX_ReadRDS(rdsResponse.raw);\n\n    // Check for RDS signal\n    rds.RDSSignal = rdsResponse.raw[2] & FIELD_RDS_STATUS_RESP2_SYNC;\n    // Get number of RDS groups (packets) available\n    uint8_t num_groups = rdsResponse.raw[3];\n    // Stop if nothing returned\n    if (!num_groups)\n      break;\n\n    /* Because PI is resent in every packet's Block A, we told the radio its OK\n     * to give us packets with a corrupted Block A.\n     */\n    // Check if PI received is valid\n    if ((rdsResponse.raw[12] & FIELD_RDS_STATUS_RESP12_BLOCK_A) !=\n        RDS_STATUS_RESP12_BLOCK_A_UNCORRECTABLE) {\n      // Get PI code\n      rds.programId = MAKE_WORD(rdsResponse.raw[PI_H], rdsResponse.raw[PI_L]);\n    }\n    // Get PTY code\n    rds.programType = ((rdsResponse.raw[Block_B_H] & 0b00000011) << 3U) |\n                      (rdsResponse.raw[Block_B_L] >> 5U);\n    // Get Traffic Program bit\n    rds.trafficProgram = (bool)(rdsResponse.raw[Block_B_H] & 0b00000100);\n\n    // Get group type (0-15)\n    uint8_t type = rdsResponse.raw[Block_B_H] >> 4U;\n    // Get group version (0=A, 1=B)\n    bool version = rdsResponse.raw[Block_B_H] & 0b00001000;\n\n    // Save which group type and version was received\n    if (version) {\n      rds.groupB |= 1U << type;\n    } else {\n      rds.groupA |= 1U << type;\n    }\n\n    // Groups 0A & 0B - Basic tuning and switching information\n    // Group 15B - Fast basic tuning and switching information\n    /* Note: We support both Groups 0 and 15B in case the station has poor\n     * reception and RDS packets are barely getting through.  This increases\n     * the chances of receiving this info.\n     */\n    if (type == 0 || (type == 15 && version == 1)) {\n      // Various flags\n      rds.trafficAlert = (bool)(rdsResponse.raw[Block_B_L] & 0b00010000);\n      rds.music = (bool)(rdsResponse.raw[Block_B_L] & 0b00001000);\n      bool DI = rdsResponse.raw[Block_B_L] & 0b00000100;\n\n      // Get segment number\n      segment = rdsResponse.raw[Block_B_L] & 0b00000011;\n      // Handle DI code\n      switch (segment) {\n      case 0:\n        rds.dynamicPTY = DI;\n        break;\n      case 1:\n        rds.compressedAudio = DI;\n        break;\n      case 2:\n        rds.binauralAudio = DI;\n        break;\n      case 3:\n        rds.RDSStereo = DI;\n        break;\n      }\n\n      // Groups 0A & 0B\n      if (type == 0) {\n        // Program Service\n        char *ps = &rds.programService[segment * 2];\n        *ps++ = make_printable(rdsResponse.raw[Block_D_H]);\n        *ps = make_printable(rdsResponse.raw[Block_D_L]);\n      }\n      new_info = true;\n    }\n    // Group 1A - Extended Country Code (ECC) and Language Code\n    else if (type == 1 && version == 0) {\n      // We are only interested in the Extended Country Code (ECC) and\n      // Language Code for this Group.\n\n      // Get Variant code\n      switch (rdsResponse.raw[Block_C_H] & 0b01110000) {\n      case (0 << 4): // Variant==0\n        // Extended Country Code\n        // Check if count has reached threshold\n        if (_extendedCountryCode_count < RDS_THRESHOLD) {\n          uint8_t ecc = rdsResponse.raw[Block_C_L];\n          // Check if datum changed\n          if (rds.extendedCountryCode != ecc) {\n            _extendedCountryCode_count = 0;\n            new_info = true;\n          }\n          // Save new data\n          rds.extendedCountryCode = ecc;\n          ++_extendedCountryCode_count;\n        }\n        break;\n      case (3 << 4): // Variant==3\n        // Language Code\n        // Check if count has reached threshold\n        if (_language_count < RDS_THRESHOLD) {\n          uint8_t language = rdsResponse.raw[Block_C_L];\n          // Check if datum changed\n          if (rds.language != language) {\n            _language_count = 0;\n            new_info = true;\n          }\n          // Save new data\n          rds.language = language;\n          ++_language_count;\n        }\n        break;\n      }\n    }\n    // Groups 2A & 2B - Radio Text\n    else if (type == 2) {\n      // Check A/B flag to see if Radio Text has changed\n      uint8_t new_ab = (bool)(rdsResponse.raw[Block_B_L] & 0b00010000);\n      if (new_ab != _abRadioText) {\n        // New message found - clear buffer\n        _abRadioText = new_ab;\n        for (uint8_t i = 0; i < sizeof(rds.radioText) - 1; i++)\n          rds.radioText[i] = ' ';\n        rds.radioTextLen = sizeof(rds.radioText); // Default to max length\n      }\n      // Get segment number\n      segment = rdsResponse.raw[Block_B_L] & 0x0F;\n\n      // Get Radio Text\n      char *rt;       // Next position in rds.radioText[]\n      uint8_t *block; // Next char from segment\n      uint8_t i;      // Loop counter\n      // TODO maybe: convert RDS non ASCII chars to UTF-8 for terminal interface\n      if (version == 0) { // 2A\n        rt = &rds.radioText[segment * 4];\n        block = &rdsResponse.raw[Block_C_H];\n        i = 4;\n      } else { // 2B\n        rt = &rds.radioText[segment * 2];\n        block = &rdsResponse.raw[Block_D_H];\n        i = 2;\n      }\n      // Copy chars\n      do {\n        // Get next char from segment\n        char ch = *block++;\n        // Check for end of message marker\n        if (ch == '\\r') {\n          // Save new message length\n          rds.radioTextLen = rt - rds.radioText;\n        }\n        // Put next char in rds.radioText[]\n        *rt++ = make_printable(ch);\n      } while (--i);\n      new_info = true;\n    }\n    // Group 4A - Clock-time and date\n    else if (type == 4 && version == 0) {\n      // Only use if received perfectly.\n      /* Note: Error Correcting Codes (ECC) are not perfect.  It is possible\n       * for a block to be damaged enough that the ECC thinks the data is OK\n       * when it's damaged or that it can recover when it cannot.  Because\n       * date and time are useless unless accurate, we require that the date\n       * and time be received perfectly to increase the odds of accurate data.\n       */\n      if ((rdsResponse.raw[12] &\n           (FIELD_RDS_STATUS_RESP12_BLOCK_B | FIELD_RDS_STATUS_RESP12_BLOCK_C |\n            FIELD_RDS_STATUS_RESP12_BLOCK_D)) ==\n          (RDS_STATUS_RESP12_BLOCK_B_NO_ERRORS |\n           RDS_STATUS_RESP12_BLOCK_C_NO_ERRORS |\n           RDS_STATUS_RESP12_BLOCK_D_NO_ERRORS)) {\n        // Get Modified Julian Date (MJD)\n        rds.MJD = (rdsResponse.raw[Block_B_L] & 0b00000011) << 15UL |\n                  rdsResponse.raw[Block_C_H] << 7U |\n                  rdsResponse.raw[Block_C_L] >> 1U;\n\n        // Get hour and minute\n        rds.hour = (rdsResponse.raw[Block_C_L] & 0b00000001) << 4U |\n                   rdsResponse.raw[Block_D_H] >> 4U;\n        rds.minute = (rdsResponse.raw[Block_D_H] & 0x0F) << 2U |\n                     rdsResponse.raw[Block_D_L] >> 6U;\n\n        // Check if date and time sent (not 0)\n        if (rds.MJD || rds.hour || rds.minute || rdsResponse.raw[Block_D_L]) {\n          // Get offset to convert UTC to local time\n          rds.offset = rdsResponse.raw[Block_D_L] & 0x1F;\n          // Check if offset should be negative\n          if (rdsResponse.raw[Block_D_L] & 0b00100000) {\n            rds.offset = -rds.offset; // Make it negative\n          }\n          new_info = true;\n        }\n      }\n    }\n    // Group 10A - Program Type Name\n    else if (type == 10 && version == 0) {\n      // Check A/B flag to see if Program Type Name has changed\n      uint8_t new_ab = (bool)(rdsResponse.raw[Block_B_L] & 0b00010000);\n      if (new_ab != _abProgramTypeName) {\n        // New name found - clear buffer\n        _abProgramTypeName = new_ab;\n        for (uint8_t i = 0; i < sizeof(rds.programTypeName) - 1; i++)\n          rds.programTypeName[i] = ' ';\n      }\n      // Get segment number\n      segment = rdsResponse.raw[Block_B_L] & 0x01;\n\n      // Get Program Type Name\n      char *name = &rds.programTypeName[segment * 4];\n      *name++ = make_printable(rdsResponse.raw[Block_C_H]);\n      *name++ = make_printable(rdsResponse.raw[Block_C_L]);\n      *name++ = make_printable(rdsResponse.raw[Block_D_H]);\n      *name = make_printable(rdsResponse.raw[Block_D_L]);\n      new_info = true;\n    }\n  }\n  return new_info;\n}\n\n#define DAYS_PER_YEAR 365U\n// Leap year\n#define DAYS_PER_LEAP_YEAR (DAYS_PER_YEAR + 1)\n// Leap year every 4 years\n#define DAYS_PER_4YEARS (DAYS_PER_YEAR * 4 + 1)\n// Leap year every 4 years except century year (divisable by 100)\n#define DAYS_PER_100YEARS (DAYS_PER_4YEARS * (100 / 4) - 1)\n\n// Get last RDS date and time converted to local date and time.\n// Returns true if current station has sent date and time.  Otherwise, it\n// returns false and writes nothing to structure. Only provides info if mode==FM\n// and station is sending RDS data.\nbool SI47XX_GetLocalDateTime(DateTime *time) {\n  // Look for date/time info\n  if (rds.offset == NO_DATE_TIME)\n    return false; // No date or time info available\n\n  // Origin for Modified Julian Date (MJD) is November 17, 1858, Wednesday.\n  // Move origin to Jan. 2, 2000, Sunday.\n  // Note: We don't use Jan. 1 to compensate for the fact that 2000 is a leap\n  // year.\n  unsigned short days = rds.MJD - (                          // 1858-Nov-17\n                                      14 +                   // 1858-Dec-1\n                                      31 +                   // 1859-Jan-1\n                                      DAYS_PER_YEAR +        // 1860-Jan-1\n                                      10 * DAYS_PER_4YEARS + // 1900-Jan-1\n                                      DAYS_PER_100YEARS +    // 2000-Jan-1\n                                      1);                    // 2000-Jan-2\n\n  // Convert UTC date and time to local date and time.\n  // Combine date and time\n  unsigned long date_time = ((unsigned long)days) * (24 * 60) +\n                            ((unsigned short)rds.hour) * 60 + rds.minute;\n  // Adjust offset from units of half hours to minutes\n  int16_t offset = (int16_t)(rds.offset) * 30;\n  // Compute local date/time\n  date_time += offset;\n  // Break down date and time\n  time->minute = date_time % 60;\n  date_time /= 60;\n  time->hour = date_time % 24;\n  days = date_time / 24;\n\n  // Compute day of the week - Sunday = 0\n  time->wday = days % 7;\n\n  // Compute year\n  unsigned char leap_year = 0; /* 1 if leap year, else 0 */\n  // Note: This code assumes all century years (2000, 2100...) are not leap\n  // years. This will break in 2400 AD.  However, RDS' date field will overflow\n  // long before 2400 AD.\n  time->year = days / DAYS_PER_100YEARS * 100 + 2000;\n  days %= DAYS_PER_100YEARS;\n  if (!(days < DAYS_PER_YEAR)) {\n    days++; // Adjust for no leap year for century year\n    time->year += days / DAYS_PER_4YEARS * 4;\n    days %= DAYS_PER_4YEARS;\n    if (days < DAYS_PER_LEAP_YEAR) {\n      leap_year = 1;\n    } else {\n      days--; // Adjust for leap year for first of 4 years\n      time->year += days / DAYS_PER_YEAR;\n      days %= DAYS_PER_YEAR;\n    }\n  }\n\n  // Compute month and day of the month\n  if (days < 31 + 28 + leap_year) {\n    if (days < 31) {\n      /* January */\n      time->month = 1;\n      time->day = days + 1;\n    } else {\n      /* February */\n      time->month = 2;\n      time->day = days + 1 - 31;\n    }\n  } else {\n    /* March - December */\n    enum { NUM_MONTHS = 10 };\n    static const unsigned short month[NUM_MONTHS] = {\n        0,\n        31,\n        31 + 30,\n        31 + 30 + 31,\n        31 + 30 + 31 + 30,\n        31 + 30 + 31 + 30 + 31,\n        31 + 30 + 31 + 30 + 31 + 31,\n        31 + 30 + 31 + 30 + 31 + 31 + 30,\n        31 + 30 + 31 + 30 + 31 + 31 + 30 + 31,\n        31 + 30 + 31 + 30 + 31 + 31 + 30 + 31 + 30};\n    unsigned short value; // Value from table\n    unsigned char mon;    // Index to month[]\n\n    days -= 31 + 28 + leap_year;\n    // Look up month\n    for (mon = NUM_MONTHS; days < (value = (month[--mon]));)\n      ;\n    time->day = days - value + 1;\n    time->month = mon + 2 + 1;\n  }\n  return true;\n}\n\nbool SI47XX_GetLocalTime(Time *time) {\n  // Look for date/time info\n  if (rds.offset == NO_DATE_TIME)\n    return false; // No date or time info available\n\n  // Convert UTC to local time\n  /* Note: If the offset is negative, 'hour' and 'minute' could become negative.\n   * To compensate, we add 24 to hour and 60 to minute.  We then do a modulus\n   * division (%24 and %60) to correct for any overflow caused by either a\n   * positive offset or the above mentioned addition.\n   */\n  time->hour = (rds.hour + rds.offset / 2 + 24) % 24;\n  time->minute = (rds.minute + rds.offset % 2 * 30 + 60) % 60;\n  return true;\n}\n\nvoid SI47XX_GetProgramType(char buffer[17]) {\n  typedef struct {\n    char *pRds;\n    char *pRdbs;\n  } RDS_PTY;\n\n  static const RDS_PTY PTY_NAMES[] = {\n      {\"No program type\", \"No program type\"},\n      {\"News\", \"News\"},\n      {\"Current affairs\", \"Information\"},\n      {\"Information\", \"Sport\"},\n      {\"Sport\", \"Talk\"},\n      {\"Education\", \"Rock\"},\n      {\"Drama\", \"Classic Rock\"},\n      {\"Culture\", \"Adult Hits\"},\n      {\"Science\", \"Soft Rock\"},\n      {\"Variable\", \"Top 40\"},\n      {\"Pop\", \"Country Music\"},\n      {\"Rock\", \"Music Oldies\"},\n      {\"Easy listening\", \"Soft Music\"},\n      {\"Light classical\", \"Nostalgia\"},\n      {\"Serious classical\", \"Jazz\"},\n      {\"Other Music\", \"Classical\"},\n      {\"Weather\", \"Rhythm and Blues\"},\n      {\"Finance\", \"Soft Rhythm and Blues\"},\n      {\"Children's programs\", \"Language\"},\n      {\"Social Affairs\", \"Religious Music\"},\n      {\"Religion\", \"Religious Talk\"},\n      {\"Phone-in talk\", \"Personality\"},\n      {\"Travel\", \"Public\"},\n      {\"Leisure\", \"College\"},\n      {\"Jazz Music\", \"Unassigned\"},\n      {\"Country Music\", \"Unassigned\"},\n      {\"National Music\", \"Unassigned\"},\n      {\"Oldies Music\", \"Unassigned\"},\n      {\"Folk Music\", \"Unassigned\"},\n      {\"Documentary\", \"Weather\"},\n      {\"Alarm Test\", \"Emergency Test\"},\n      {\"Alarm\", \"Emergency\"},\n  };\n\n  const RDS_PTY *pty = &PTY_NAMES[rds.programType];\n  if (rds.RBDS) {\n    strncpy(buffer, pty->pRdbs, 16);\n  } else {\n    strncpy(buffer, pty->pRds, 16);\n  }\n  buffer[16] = '\\0';\n}\n"
  },
  {
    "path": "helper/rds.h",
    "content": "#ifndef RDS_H\n#define RDS_H\n\n#include <stdbool.h>\n#include <stdint.h>\n\ntypedef union {\n  struct {\n    // status (\"RESP0\")\n    uint8_t STCINT : 1;\n    uint8_t DUMMY1 : 1;\n    uint8_t RDSINT : 1;\n    uint8_t RSQINT : 1;\n    uint8_t DUMMY2 : 2;\n    uint8_t ERR : 1;\n    uint8_t CTS : 1;\n    // RESP1\n    uint8_t RDSRECV : 1; //!<  RDS Received; 1 = FIFO filled to minimum number\n                         //!<  of groups set by RDSFIFOCNT.\n    uint8_t RDSSYNCLOST : 1; //!<  RDS Sync Lost; 1 = Lost RDS synchronization.\n    uint8_t\n        RDSSYNCFOUND : 1; //!<  RDS Sync Found; 1 = Found RDS synchronization.\n    uint8_t DUMMY3 : 1;\n    uint8_t RDSNEWBLOCKA : 1; //!<  RDS New Block A; 1 = Valid Block A data has\n                              //!<  been received.\n    uint8_t RDSNEWBLOCKB : 1; //!<  RDS New Block B; 1 = Valid Block B data has\n                              //!<  been received.\n    uint8_t DUMMY4 : 2;\n    // RESP2\n    uint8_t RDSSYNC : 1; //!<  RDS Sync; 1 = RDS currently synchronized.\n    uint8_t DUMMY5 : 1;\n    uint8_t GRPLOST : 1; //!<  Group Lost; 1 = One or more RDS groups discarded\n                         //!<  due to FIFO overrun.\n    uint8_t DUMMY6 : 5;\n    // RESP3 to RESP11\n    uint8_t RDSFIFOUSED; //!<  RESP3 - RDS FIFO Used; Number of groups remaining\n                         //!<  in the RDS FIFO (0 if empty).\n    uint8_t BLOCKAH;     //!<  RESP4 - RDS Block A; HIGH byte\n    uint8_t BLOCKAL;     //!<  RESP5 - RDS Block A; LOW byte\n    uint8_t BLOCKBH;     //!<  RESP6 - RDS Block B; HIGH byte\n    uint8_t BLOCKBL;     //!<  RESP7 - RDS Block B; LOW byte\n    uint8_t BLOCKCH;     //!<  RESP8 - RDS Block C; HIGH byte\n    uint8_t BLOCKCL;     //!<  RESP9 - RDS Block C; LOW byte\n    uint8_t BLOCKDH;     //!<  RESP10 - RDS Block D; HIGH byte\n    uint8_t BLOCKDL;     //!<  RESP11 - RDS Block D; LOW byte\n    // RESP12 - Blocks A to D Corrected Errors.\n    // 0 = No errors;\n    // 1 = 1–2 bit errors detected and corrected;\n    // 2 = 3–5 bit errors detected and corrected.\n    // 3 = Uncorrectable.\n    uint8_t BLED : 2;\n    uint8_t BLEC : 2;\n    uint8_t BLEB : 2;\n    uint8_t BLEA : 2;\n  } resp;\n  uint8_t raw[13];\n} si47x_rds_status;\n\ntypedef signed char ternary;\n/* RDS and RBDS data */\ntypedef struct {\n  uint16_t\n      programId; // Program Identification (PI) code - unique code assigned to\n                 // program. In the US, except for simulcast stations, each\n                 // station has a unique PI. PI = 0 if no RDS info received.\n  /* groupA and groupB indicate if the station has broadcast one or more of each\n   * RDS group type and version. There is one bit for each group type.  Bit\n   * number 0 is for group type 0, and so on. groupA gives version A groups\n   * (packets), groupB gives version B groups. If a bit is true then one or more\n   * of that group type and version has been received. Example:  If (groupA &\n   * 1<<4) is true then at least one Group type 4, version A group (packet) has\n   * been received. Note: If the RDS signal is weak, many bad packets will be\n   * received.  Sometimes, the packets are so corrupted that the radio thinks\n   * the bad data is OK.  This can cause false information to be recorded in the\n   * groupA and groupB variables.\n   */\n  uint16_t groupA;     // One bit for each group type, version A\n  uint16_t groupB;     // One bit for each group type, version B\n  bool RDSSignal;      // True if RDS (or RBDS) signal currently detected\n  bool RBDS;           // True if station using RBDS, else using RDS\n  uint8_t programType; // Program Type (PTY) code - identifies program format -\n                       // call getProgramTypeStr()\n  uint8_t extendedCountryCode; // Extended Country Code (ECC) - constants\n                               // defined above\n  uint8_t language;            // Language Code - constants defined above\n  ternary trafficProgram;      // Traffic Program flag - True if station gives\n                               // Traffic Alerts\n  ternary trafficAlert;        // Traffic Alert flag - True if station currently\n                               // broadcasting Traffic Alert\n  ternary\n      music; // Music/speech flag - True if broadcasting music, false if speech\n  ternary dynamicPTY;      // Dynamic PTY flag - True if dynamic (changing) PTY,\n                           // false if static PTY\n  ternary compressedAudio; // Compressed audio flag - True if compressed audio,\n                           // false if not compressed\n  ternary binauralAudio; // Binaural audio flag - True if binaural audio, false\n                         // if not binaural audio\n  ternary RDSStereo; // RDS stereo/mono flag - True if RDS info says station is\n                     // stereo, false if mono\n  char programService[9];  // Station's name or slogan - usually used like Radio\n                           // Text\n  uint8_t radioTextLen;    // Length of Radio Text message\n  char radioText[65];      // Descriptive message from station\n  char programTypeName[9]; // Program Type Name (PTYN)\n  unsigned long MJD; // UTC Modified Julian Date - origin is November 17, 1858\n  uint8_t hour;      // UTC Hour\n  uint8_t minute;    // UTC Minute\n  signed char\n      offset; // Offset measured in half hours to convert UTC to local time.\n              // If offset==NO_DATE_TIME then MJD, hour, minute are invalid.\n} RDS;\n\ntypedef struct DateTime {\n  uint16_t year;\n  uint8_t month;\n  uint8_t day;\n  uint8_t wday; // Day of the week, Sunday = 0\n  uint8_t hour;\n  uint8_t minute;\n} DateTime;\n\ntypedef struct Time {\n  uint8_t hour;\n  uint8_t minute;\n} Time;\n\nbool SI47XX_GetLocalDateTime(DateTime *time);\nbool SI47XX_GetLocalTime(Time *time);\nvoid SI47XX_GetProgramType(char buffer[17]);\nvoid SI47XX_ClearRDS();\nbool SI47XX_GetRDS();\n\nextern RDS rds;\nextern si47x_rds_status rdsResponse;\n\n#endif /* end of include guard: RDS_H */\n"
  },
  {
    "path": "init.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n * Copyright 2023 Manuel Jedinger\r\n * https://github.com/manujedi\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <stdint.h>\r\n\r\nextern uint32_t __bss_start__[];\r\nextern uint32_t __bss_end__[];\r\nextern uint8_t flash_data_start[];\r\nextern uint8_t sram_data_start[];\r\nextern uint8_t sram_data_end[];\r\n\r\nvoid BSS_Init(void);\r\n\r\nvoid DATA_Init(void);\r\n\r\nvoid BSS_Init(void) {\r\n    uint32_t *pBss;\r\n    for (pBss = __bss_start__; pBss < __bss_end__; pBss++)\r\n        *pBss = 0;\r\n}\r\n\r\nvoid DATA_Init(void) {\r\n    volatile uint32_t *pDataRam = (volatile uint32_t *) sram_data_start;\r\n    volatile uint32_t *pDataFlash = (volatile uint32_t *) flash_data_start;\r\n    uint32_t Size = (uint32_t) sram_data_end - (uint32_t) sram_data_start;\r\n    unsigned int i;\r\n\r\n    for (i = 0; i < (Size / 4); i++)\r\n        *pDataRam++ = *pDataFlash++;\r\n}\r\n"
  },
  {
    "path": "main.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"app/si.h\"\r\n\r\n#include \"driver/i2c.h\"\r\n#include \"driver/system.h\"\r\n#include \"frequencies.h\"\r\n#include \"misc.h\"\r\n#include \"app/doppler.h\"\r\n#include \"driver/uart.h\"\r\n#include \"string.h\"\r\n#include <stdio.h>\r\n#include \"ui/helper.h\"\r\n#include <string.h>\r\n#include \"driver/bk4819.h\"\r\n#include \"font.h\"\r\n#include \"ui/ui.h\"\r\n#include <stdint.h>\r\n#include <string.h>\r\n#include \"font.h\"\r\n#include <stdio.h>     // NULL\r\n#include \"app/mdc1200.h\"\r\n#include \"app/uart.h\"\r\n#include \"string.h\"\r\n#include \"app/messenger.h\"\r\n\r\n#ifdef ENABLE_DOPPLER\r\n\r\n#include \"app/doppler.h\"\r\n\r\n#endif\r\n#ifdef ENABLE_AM_FIX\r\n\r\n#include \"am_fix.h\"\r\n\r\n#endif\r\n\r\n#include \"bsp/dp32g030/rtc.h\"\r\n\r\n#ifdef ENABLE_TIMER\r\n#include \"bsp/dp32g030/uart.h\"\r\n#include \"bsp/dp32g030/timer.h\"\r\n#endif\r\n#ifdef ENABLE_4732\r\n\r\n\r\n#endif\r\n\r\n#include \"audio.h\"\r\n#include \"board.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"settings.h\"\r\n#include \"version.h\"\r\n#include \"app/app.h\"\r\n#include \"app/dtmf.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"bsp/dp32g030/syscon.h\"\r\n#include \"driver/backlight.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/system.h\"\r\n#include \"driver/systick.h\"\r\n\r\n#ifdef ENABLE_UART\r\n\r\n#include \"driver/uart.h\"\r\n\r\n#endif\r\n\r\n#include \"app/spectrum.h\"\r\n\r\n#include \"helper/battery.h\"\r\n#include \"helper/boot.h\"\r\n\r\n#include \"ui/lock.h\"\r\n#include \"ui/welcome.h\"\r\n#include \"ui/menu.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/st7565.h\"\r\n\r\nvoid _putchar(__attribute__((unused)) char c) {\r\n\r\n#ifdef ENABLE_UART\r\n    UART_Send((uint8_t *) &c, 1);\r\n#endif\r\n\r\n}\r\n\r\n\r\nvoid Main(void) {\r\n    //BOOT_Mode_t  BootMode;\r\n\r\n    // Enable clock gating of blocks we need\r\n    SYSCON_DEV_CLK_GATE = 0\r\n                          | SYSCON_DEV_CLK_GATE_GPIOA_BITS_ENABLE\r\n                          | SYSCON_DEV_CLK_GATE_GPIOB_BITS_ENABLE\r\n                          | SYSCON_DEV_CLK_GATE_GPIOC_BITS_ENABLE\r\n                          | SYSCON_DEV_CLK_GATE_UART1_BITS_ENABLE\r\n                          | SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE\r\n                          | SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE\r\n                          | SYSCON_DEV_CLK_GATE_CRC_BITS_ENABLE\r\n                          | SYSCON_DEV_CLK_GATE_AES_BITS_ENABLE\r\n                          | SYSCON_DEV_CLK_GATE_PWM_PLUS0_BITS_ENABLE\r\n        //                          | (1 << 12)\r\n#ifdef ENABLE_DOPPLER\r\n\r\n        | (1 << 22)\r\n#endif\r\n            ;\r\n\r\n    SYSTICK_Init();\r\n\r\n    BOARD_Init();\r\n\r\n\r\n\r\n#ifdef ENABLE_UART\r\n    UART_Init();\r\n#endif\r\n\r\n\r\n    memset(gDTMF_String, '-', sizeof(gDTMF_String));\r\n    gDTMF_String[sizeof(gDTMF_String) - 1] = 0;\r\n\r\n    BK4819_Init();\r\n\r\n\r\n    BOARD_ADC_GetBatteryInfo(&gBatteryCurrentVoltage, &gBatteryCurrent);\r\n\r\n\r\n    SETTINGS_InitEEPROM();\r\n\r\n\r\n    SETTINGS_LoadCalibration();\r\n#ifdef ENABLE_MESSENGER\r\n    MSG_Init();\r\n#endif\r\n#ifdef ENABLE_MDC1200\r\n    MDC1200_init();\r\n#endif\r\n//    char name[10]=\"START6789\";\r\n//    EEPROM_WriteBuffer(0x02BA0,name,10);\r\n#ifdef ENABLE_DOPPLER\r\n\r\n    RTC_INIT();\r\n    INIT_DOPPLER_DATA();\r\n#endif\r\n\r\n    RADIO_ConfigureChannel(0, VFO_CONFIGURE_RELOAD);\r\n    RADIO_ConfigureChannel(1, VFO_CONFIGURE_RELOAD);\r\n\r\n\r\n    RADIO_SelectVfos();\r\n\r\n    RADIO_SetupRegisters(true);\r\n\r\n    for (uint32_t i = 0; i < ARRAY_SIZE(gBatteryVoltages); i++) {\r\n        BOARD_ADC_GetBatteryInfo(&gBatteryVoltages[i], &gBatteryCurrent);\r\n    }\r\n    BATTERY_GetReadings(false);\r\n\r\n#ifdef ENABLE_AM_FIX\r\n    AM_fix_init();\r\n#endif\r\n\r\n#if ENABLE_CHINESE_FULL == 0\r\n    gMenuListCount = 52;\r\n#else\r\n    gMenuListCount = 53;\r\n#endif\r\n    gKeyReading0 = KEY_INVALID;\r\n    gKeyReading1 = KEY_INVALID;\r\n    gDebounceCounter = 0;\r\n//#ifdef ENABLE_4732\r\n//\r\n//\r\n//    memset(gStatusLine, 0, sizeof(gStatusLine));\r\n//    UI_DisplayClear();\r\n//    ST7565_BlitStatusLine();  // blank status line\r\n//    ST7565_BlitFullScreen();\r\n//SI4732_Main();\r\n//#endif\r\n#ifdef ENABLE_TIMER\r\n\r\n\r\n    BOARD_PORTCON_Init();\r\n    BOARD_GPIO_Init();\r\n    ST7565_Init();\r\n    TIM0_INIT();\r\n    memset(gStatusLine, 0, sizeof(gStatusLine));\r\n    UI_DisplayClear();\r\n    ST7565_BlitStatusLine();  // blank status line\r\n    ST7565_BlitFullScreen();\r\n    char str[20]={0}; // 分配一个足够大的字符串数组来存储转换后的字符串\r\n    while(1)\r\n    {\r\n        char str[6];\r\n        show_uint32(TIM0_CNT,0);\r\n        show_uint32(TIMERBASE0_LOW_CNT,1);\r\n        show_uint32(TIMERBASE0_HIGH_CNT,2);\r\n        show_uint32(TIMERBASE0_IF,3);\r\n        show_uint32(TIMERBASE0_IE,4);\r\n    }\r\n#endif\r\n    UI_DisplayWelcome();\r\n\r\n#ifdef ENABLE_BOOTLOADER\r\n\r\n\r\n    if(KEYBOARD_Poll() == KEY_MENU)\r\n{\r\n            for (int i = 0; i < 10*1024; i += 4) {\r\n                uint32_t c;\r\n                EEPROM_ReadBuffer(0x41000 + i, (uint8_t *) &c, 4);\r\n                write_to_memory(0x20001000 + i, c);\r\n            }\r\n            JUMP_TO_FLASH(0x2000110a, 0x20003ff0);\r\n}\r\n#endif\r\n\r\n\r\n    boot_counter_10ms = 250;\r\n\r\n    while (boot_counter_10ms > 0 || (KEYBOARD_Poll() != KEY_INVALID)) {\r\n\r\n        if (KEYBOARD_Poll() == KEY_EXIT\r\n#if ENABLE_CHINESE_FULL == 4\r\n            || gEeprom.POWER_ON_DISPLAY_MODE == POWER_ON_DISPLAY_MODE_NONE\r\n#endif\r\n                ) {    // halt boot beeps\r\n            boot_counter_10ms = 0;\r\n            break;\r\n        }\r\n#ifdef ENABLE_BOOT_BEEPS\r\n\r\n        if ((boot_counter_10ms % 25) == 0)\r\n                    AUDIO_PlayBeep(BEEP_880HZ_40MS_OPTIONAL);\r\n#endif\r\n\r\n    }\r\n\r\n\r\n#ifdef ENABLE_PWRON_PASSWORD\r\n    if (gEeprom.POWER_ON_PASSWORD < 1000000)\r\n    {\r\n        bIsInLockScreen = true;\r\n        UI_DisplayLock();\r\n        bIsInLockScreen = false;\r\n    }\r\n#endif\r\n\r\n    //\tBOOT_ProcessMode();\r\n    GUI_SelectNextDisplay(DISPLAY_MAIN);\r\n\r\n    GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_VOICE_0);\r\n\r\n    gUpdateStatus = true;\r\n\r\n#ifdef ENABLE_VOICE\r\n    {\r\n        uint8_t Channel;\r\n\r\n        AUDIO_SetVoiceID(0, VOICE_ID_WELCOME);\r\n\r\n        Channel = gEeprom.ScreenChannel[gEeprom.TX_VFO];\r\n        if (IS_MR_CHANNEL(Channel))\r\n        {\r\n            AUDIO_SetVoiceID(1, VOICE_ID_CHANNEL_MODE);\r\n            AUDIO_SetDigitVoice(2, Channel + 1);\r\n        }\r\n        else if (IS_FREQ_CHANNEL(Channel))\r\n            AUDIO_SetVoiceID(1, VOICE_ID_FREQUENCY_MODE);\r\n\r\n        AUDIO_PlaySingleVoice(0);\r\n    }\r\n#endif\r\n\r\n#ifdef ENABLE_NOAA\r\n    RADIO_ConfigureNOAA();\r\n#endif\r\n\r\n    while (1) {\r\n\r\n        APP_Update();\r\n\r\n        if (gNextTimeslice) {\r\n            APP_TimeSlice10ms();\r\n        }\r\n\r\n        if (gNextTimeslice_500ms) {\r\n            APP_TimeSlice500ms();\r\n        }\r\n\r\n\r\n    }\r\n}\r\n"
  },
  {
    "path": "misc.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <string.h>\r\n\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n\r\nconst uint8_t fm_radio_countdown_500ms = 2000 / 500;  // 2 seconds\r\nconst uint16_t fm_play_countdown_scan_10ms = 100 / 10;   // 100ms\r\nconst uint16_t fm_play_countdown_noscan_10ms = 1200 / 10;   // 1.2 seconds\r\nconst uint16_t fm_restore_countdown_10ms = 5000 / 10;   // 5 seconds\r\n\r\nconst uint8_t vfo_state_resume_countdown_500ms = 2500 / 500;  // 2.5 seconds\r\n\r\nconst uint8_t menu_timeout_500ms = 20000 / 500;  // 20 seconds\r\nconst uint16_t menu_timeout_long_500ms = 120000 / 500;  // 2 minutes\r\n\r\nconst uint8_t DTMF_RX_live_timeout_500ms = 6000 / 500;  // 6 seconds live decoder on screen\r\n#ifdef ENABLE_DTMF_CALLING\r\nconst uint8_t     DTMF_RX_timeout_500ms            = 10000 / 500;  // 10 seconds till we wipe the DTMF receiver\r\nconst uint8_t     DTMF_decode_ring_countdown_500ms = 15000 / 500;  // 15 seconds .. time we sound the ringing for\r\nconst uint8_t     DTMF_txstop_countdown_500ms      =  3000 / 500;  // 6 seconds\r\n#endif\r\nconst uint8_t key_input_timeout_500ms = 8000 / 500;  // 8 seconds\r\n\r\nconst uint16_t key_repeat_delay_10ms = 400 / 10;   // 400ms\r\nconst uint16_t key_repeat_10ms = 80 / 10;   // 80ms .. MUST be less than 'key_repeat_delay'\r\nconst uint16_t key_debounce_10ms = 20 / 10;   // 20ms\r\n\r\nconst uint8_t scan_delay_10ms = 210 / 10;   // 210ms\r\n\r\nconst uint16_t dual_watch_count_after_tx_10ms = 3600 / 10;   // 3.6 sec after TX ends\r\nconst uint16_t dual_watch_count_after_rx_10ms = 1000 / 10;   // 1 sec after RX ends ?\r\nconst uint16_t dual_watch_count_after_1_10ms = 5000 / 10;   // 5 sec\r\nconst uint16_t dual_watch_count_after_2_10ms = 3600 / 10;   // 3.6 sec\r\nconst uint16_t dual_watch_count_noaa_10ms = 70 / 10;   // 70ms\r\n#ifdef ENABLE_VOX\r\nconst uint16_t dual_watch_count_after_vox_10ms  =   200 / 10;   // 200ms\r\n#endif\r\nconst uint16_t dual_watch_count_toggle_10ms = 100 / 10;   // 100ms between VFO toggles\r\n\r\nconst uint16_t scan_pause_delay_in_1_10ms = 5000 / 10;   // 5 seconds\r\nconst uint16_t scan_pause_delay_in_2_10ms = 500 / 10;   // 500ms\r\nconst uint16_t scan_pause_delay_in_3_10ms = 200 / 10;   // 200ms\r\nconst uint16_t scan_pause_delay_in_4_10ms = 300 / 10;   // 300ms\r\nconst uint16_t scan_pause_delay_in_5_10ms = 1000 / 10;   // 1 sec\r\nconst uint16_t scan_pause_delay_in_6_10ms = 100 / 10;   // 100ms\r\nconst uint16_t scan_pause_delay_in_7_10ms = 3600 / 10;   // 3.6 seconds\r\n\r\nconst uint16_t battery_save_count_10ms = 10000 / 10;   // 10 seconds\r\n\r\nconst uint16_t power_save1_10ms = 100 / 10;   // 100ms\r\nconst uint16_t power_save2_10ms = 200 / 10;   // 200ms\r\n\r\n#ifdef ENABLE_VOX\r\nconst uint16_t    vox_stop_count_down_10ms         =  1000 / 10;   // 1 second\r\n#endif\r\n\r\nconst uint16_t NOAA_countdown_10ms = 5000 / 10;   // 5 seconds\r\nconst uint16_t NOAA_countdown_2_10ms = 500 / 10;   // 500ms\r\nconst uint16_t NOAA_countdown_3_10ms = 200 / 10;   // 200ms\r\n\r\nconst uint32_t gDefaultAesKey[4] = {0x4AA5CC60, 0x0312CC5F, 0xFFD2DABB, 0x6BBA7F92};\r\n\r\nconst uint8_t gMicGain_dB2[5] = {3, 8, 16, 24, 31};\r\n\r\n//bool              gSetting_350TX;\r\n#ifdef ENABLE_DTMF_CALLING\r\nbool              gSetting_KILLED;\r\n#endif\r\n//bool              gSetting_200TX;\r\n//bool              gSetting_500TX;\r\n//bool              gSetting_350EN;\r\nuint8_t gSetting_F_LOCK;\r\nbool gSetting_ScrambleEnable;\r\n\r\n\r\n#ifdef ENABLE_AM_FIX\r\nbool          gSetting_AM_fix;\r\n#endif\r\n#ifdef ENABLE_AM_FIX_TEST1\r\nuint8_t       gSetting_AM_fix_test1 = 0;\r\n#endif\r\n//#ifdef ENABLE_AUDIO_BAR\r\n//#endif\r\nbool gSetting_live_DTMF_decoder;\r\n\r\nbool gMonitor = false;           // true opens the squelch\r\n\r\nuint32_t gCustomAesKey[4];\r\nbool bHasCustomAesKey;\r\nuint32_t gChallenge[4];\r\nuint8_t gTryCount;\r\n\r\nuint16_t gEEPROM_RSSI_CALIB[7][4];\r\n\r\nuint16_t gEEPROM_1F8A;\r\nuint16_t gEEPROM_1F8C;\r\n\r\nChannelAttributes_t gMR_ChannelAttributes[FREQ_CHANNEL_LAST + 1];\r\n\r\nvolatile uint16_t gBatterySaveCountdown_10ms = battery_save_count_10ms;\r\n\r\nvolatile bool gPowerSaveCountdownExpired;\r\nvolatile bool gSchedulePowerSave;\r\n\r\nvolatile bool gScheduleDualWatch = true;\r\n\r\nvolatile uint16_t gDualWatchCountdown_10ms;\r\nbool gDualWatchActive = false;\r\n\r\nvolatile uint8_t gSerialConfigCountDown_500ms;\r\n\r\nvolatile bool gNextTimeslice_500ms;\r\n\r\nvolatile uint16_t gTxTimerCountdown_500ms;\r\nvolatile bool gTxTimeoutReached;\r\n\r\nvolatile uint16_t gTailToneEliminationCountdown_10ms;\r\n\r\nvolatile uint8_t gVFOStateResumeCountdown_500ms;\r\n\r\n#ifdef ENABLE_NOAA\r\nvolatile uint16_t gNOAA_Countdown_10ms;\r\n#endif\r\n\r\nbool gEnableSpeaker;\r\nuint8_t gKeyInputCountdown = 0;\r\nuint8_t gKeyLockCountdown;\r\nuint8_t gRTTECountdown_10ms;\r\nbool bIsInLockScreen;\r\nuint8_t gUpdateStatus;\r\nuint8_t gFoundCTCSS;\r\nuint8_t gFoundCDCSS;\r\nbool gEndOfRxDetectedMaybe;\r\n\r\nint16_t gVFO_RSSI[2];\r\nuint8_t gVFO_RSSI_bar_level[2];\r\n\r\nuint8_t gReducedService;\r\nuint8_t gBatteryVoltageIndex;\r\nbool gCssBackgroundScan;\r\n\r\nvolatile bool gScheduleScanListen = true;\r\nvolatile uint16_t gScanPauseDelayIn_10ms;\r\n\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\nAlarmState_t  gAlarmState;\r\n#endif\r\nuint16_t gMenuCountdown;\r\nbool gPttWasReleased;\r\nbool gPttWasPressed;\r\nuint8_t gKeypadLocked;\r\nbool gFlagReconfigureVfos;\r\nuint8_t gVfoConfigureMode;\r\nbool gFlagResetVfos;\r\nbool gRequestSaveVFO;\r\nuint8_t gRequestSaveChannel;\r\nbool gRequestSaveSettings;\r\n#ifdef ENABLE_FMRADIO\r\nbool          gRequestSaveFM;\r\n#endif\r\nbool gFlagPrepareTX;\r\n\r\nbool gFlagAcceptSetting;\r\nbool gFlagRefreshSetting;\r\n\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\nbool              gFlagStopTX;\r\nbool              gFlagLastVfo;\r\n#endif\r\n\r\n#ifdef ENABLE_FMRADIO\r\nbool          gFlagSaveFM;\r\n#endif\r\nbool g_CDCSS_Lost;\r\nuint8_t gCDCSSCodeType;\r\nbool g_CTCSS_Lost;\r\nbool g_CxCSS_TAIL_Found;\r\n#ifdef ENABLE_VOX\r\nbool          g_VOX_Lost;\r\n    bool          gVOX_NoiseDetected;\r\n    uint16_t      gVoxResumeCountdown;\r\n    uint16_t      gVoxPauseCountdown;\r\n#endif\r\nbool g_SquelchLost;\r\nvolatile uint16_t gFlashLightBlinkCounter;\r\nuint8_t gNextMrChannel;\r\nReceptionMode_t gRxReceptionMode;\r\nunsigned int last_rx_vfo = -1;\r\nbool gRxVfoIsActive;\r\n#ifdef ENABLE_ALARM\r\nuint8_t       gAlarmToneCounter;\r\n    uint16_t      gAlarmRunningCounter;\r\n#endif\r\nbool gKeyBeingHeld;\r\nbool gPttIsPressed;\r\nuint8_t gPttDebounceCounter;\r\nuint8_t gMenuListCount;\r\nuint8_t gBackup_CROSS_BAND_RX_TX;\r\nuint8_t gScanDelay_10ms;\r\n#ifdef ENABLE_AIRCOPY\r\nuint8_t       gAircopySendCountdown;\r\n#endif\r\nuint8_t gFSKWriteIndex;\r\n\r\n#ifdef ENABLE_NOAA\r\nbool          gIsNoaaMode;\r\n    uint8_t       gNoaaChannel;\r\n#endif\r\n\r\nbool gUpdateDisplay;\r\n\r\n\r\nuint8_t gShowChPrefix;\r\n\r\nvolatile bool gNextTimeslice;\r\nvolatile uint8_t gFoundCDCSSCountdown_10ms;\r\nvolatile uint8_t gFoundCTCSSCountdown_10ms;\r\n#ifdef ENABLE_VOX\r\nvolatile uint16_t gVoxStopCountdown_10ms;\r\n#endif\r\nvolatile bool gNextTimeslice40ms;\r\n#ifdef ENABLE_NOAA\r\nvolatile uint16_t gNOAACountdown_10ms = 0;\r\n    volatile bool     gScheduleNOAA       = true;\r\n#endif\r\nvolatile bool gFlagTailToneEliminationComplete;\r\n#ifdef ENABLE_FMRADIO\r\nvolatile bool gScheduleFM;\r\n#endif\r\n\r\nvolatile uint8_t boot_counter_10ms;\r\n\r\n\r\nuint8_t gIsLocked = 0xFF;\r\n\r\ninline void FUNCTION_NOP() { ; }\r\n\r\nint32_t NUMBER_AddWithWraparound(int32_t Base, int32_t Add, int32_t LowerLimit, int32_t UpperLimit) {\r\n    Base += Add;\r\n\r\n    if (Base == 0x7fffffff || Base < LowerLimit)\r\n        return UpperLimit;\r\n\r\n    if (Base > UpperLimit)\r\n        return LowerLimit;\r\n\r\n    return Base;\r\n}\r\n\r\nunsigned long StrToUL(const char *str) {\r\n    unsigned long ul = 0;\r\n    for (uint8_t i = 0; i < strlen(str); i++) {\r\n        char c = str[i];\r\n        if (c < '0' || c > '9')\r\n            break;\r\n        ul = ul * 10 + (uint8_t) (c - '0');\r\n    }\r\n    return ul;\r\n}"
  },
  {
    "path": "misc.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef MISC_H\r\n#define MISC_H\r\n#include \"assert.h\"\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n#ifndef ARRAY_SIZE\r\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r\n#endif\r\n\r\n#ifndef MAX\r\n#define MAX(a, b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a > _b ? _a : _b; })\r\n#endif\r\n\r\n#ifndef MIN\r\n#define MIN(a, b) ({ __typeof__ (a) _a = (a); __typeof__ (b) _b = (b); _a < _b ? _a : _b; })\r\n#endif\r\n\r\n#define IS_MR_CHANNEL(x)       ((x) <= MR_CHANNEL_LAST)\r\n#define IS_FREQ_CHANNEL(x)     ((x) >= FREQ_CHANNEL_FIRST && (x) <= FREQ_CHANNEL_LAST)\r\n#define IS_VALID_CHANNEL(x)    ((x) < LAST_CHANNEL)\r\n#define IS_NOAA_CHANNEL(x)     ((x) >= NOAA_CHANNEL_FIRST && (x) <= NOAA_CHANNEL_LAST)\r\n#ifndef SWAP\r\n#define SWAP(a, b) ({ __typeof__ (a) _c = (a);  a = b; b = _c; })\r\n#endif\r\nenum {\r\n    MR_CHANNEL_FIRST   = 0,\r\n    MR_CHANNEL_LAST    = 199u,\r\n    FREQ_CHANNEL_FIRST = 200u,\r\n    FREQ_CHANNEL_LAST  = 206u,\r\n    NOAA_CHANNEL_FIRST = 207u,\r\n    NOAA_CHANNEL_LAST  = 216u,\r\n    LAST_CHANNEL\r\n};\r\n\r\nenum {\r\n    VFO_CONFIGURE_NONE = 0,\r\n    VFO_CONFIGURE,\r\n    VFO_CONFIGURE_RELOAD\r\n};\r\n\r\nenum AlarmState_t {\r\n    ALARM_STATE_OFF = 0,\r\n    ALARM_STATE_TXALARM,\r\n    ALARM_STATE_SITE_ALARM,\r\n    ALARM_STATE_TX1750\r\n};\r\ntypedef enum AlarmState_t AlarmState_t;\r\n\r\nenum ReceptionMode_t {\r\n    RX_MODE_NONE = 0,   // squelch close ?\r\n    RX_MODE_DETECTED,   // signal detected\r\n    RX_MODE_LISTENING   //\r\n};\r\ntypedef enum ReceptionMode_t ReceptionMode_t;\r\n\r\nenum BacklightOnRxTx_t {\r\n    BACKLIGHT_ON_TR_OFF,\r\n    BACKLIGHT_ON_TR_TX,\r\n    BACKLIGHT_ON_TR_RX,\r\n    BACKLIGHT_ON_TR_TXRX\r\n};\r\n\r\nextern const uint8_t         fm_radio_countdown_500ms;\r\nextern const uint16_t        fm_play_countdown_scan_10ms;\r\nextern const uint16_t        fm_play_countdown_noscan_10ms;\r\nextern const uint16_t        fm_restore_countdown_10ms;\r\n\r\nextern const uint8_t        vfo_state_resume_countdown_500ms;\r\n\r\nextern const uint8_t         menu_timeout_500ms;\r\nextern const uint16_t        menu_timeout_long_500ms;\r\n\r\nextern const uint8_t         DTMF_RX_live_timeout_500ms;\r\n#ifdef ENABLE_DTMF_CALLING\r\nextern const uint8_t         DTMF_RX_timeout_500ms;\r\nextern const uint8_t         DTMF_decode_ring_countdown_500ms;\r\nextern const uint8_t         DTMF_txstop_countdown_500ms;\r\n#endif\r\nextern const uint8_t         key_input_timeout_500ms;\r\n\r\nextern const uint16_t        key_repeat_delay_10ms;\r\nextern const uint16_t        key_repeat_10ms;\r\nextern const uint16_t        key_debounce_10ms;\r\n\r\nextern const uint8_t         scan_delay_10ms;\r\n\r\nextern const uint16_t        battery_save_count_10ms;\r\n\r\nextern const uint16_t        power_save1_10ms;\r\nextern const uint16_t        power_save2_10ms;\r\n\r\n#ifdef ENABLE_VOX\r\nextern const uint16_t    vox_stop_count_down_10ms;\r\n#endif\r\n\r\nextern const uint16_t        NOAA_countdown_10ms;\r\nextern const uint16_t        NOAA_countdown_2_10ms;\r\nextern const uint16_t        NOAA_countdown_3_10ms;\r\n\r\nextern const uint16_t        dual_watch_count_after_tx_10ms;\r\nextern const uint16_t        dual_watch_count_after_rx_10ms;\r\nextern const uint16_t        dual_watch_count_after_1_10ms;\r\nextern const uint16_t        dual_watch_count_after_2_10ms;\r\nextern const uint16_t        dual_watch_count_toggle_10ms;\r\nextern const uint16_t        dual_watch_count_noaa_10ms;\r\n#ifdef ENABLE_VOX\r\nextern const uint16_t    dual_watch_count_after_vox_10ms;\r\n#endif\r\n\r\nextern const uint16_t        scan_pause_delay_in_1_10ms;\r\nextern const uint16_t        scan_pause_delay_in_2_10ms;\r\nextern const uint16_t        scan_pause_delay_in_3_10ms;\r\nextern const uint16_t        scan_pause_delay_in_4_10ms;\r\nextern const uint16_t        scan_pause_delay_in_5_10ms;\r\nextern const uint16_t        scan_pause_delay_in_6_10ms;\r\nextern const uint16_t        scan_pause_delay_in_7_10ms;\r\n\r\n//extern const uint16_t        gMax_bat_v;\r\n//extern const uint16_t        gMin_bat_v;\r\n\r\nextern const uint8_t         gMicGain_dB2[5];\r\n\r\n//extern bool                  gSetting_350TX;\r\n#ifdef ENABLE_DTMF_CALLING\r\nextern bool                  gSetting_KILLED;\r\n#endif\r\n//extern bool                  gSetting_200TX;\r\n//extern bool                  gSetting_500TX;\r\n//extern bool                  gSetting_350EN;\r\nextern uint8_t               gSetting_F_LOCK;\r\nextern bool                  gSetting_ScrambleEnable;\r\n\r\n\r\n#ifdef ENABLE_AM_FIX\r\nextern bool              gSetting_AM_fix;\r\n#endif\r\n#ifdef ENABLE_AM_FIX_TEST1\r\nextern uint8_t           gSetting_AM_fix_test1;\r\n#endif\r\n//#ifdef ENABLE_AUDIO_BAR\r\n//#endif\r\nextern bool                  gSetting_live_DTMF_decoder;\r\n\r\nextern bool                  gMonitor;\r\n\r\nextern const uint32_t        gDefaultAesKey[4];\r\nextern uint32_t              gCustomAesKey[4];\r\nextern bool                  bHasCustomAesKey;\r\nextern uint32_t              gChallenge[4];\r\nextern uint8_t               gTryCount;\r\n\r\nextern uint16_t              gEEPROM_RSSI_CALIB[7][4];\r\n\r\nextern uint16_t              gEEPROM_1F8A;\r\nextern uint16_t              gEEPROM_1F8C;\r\n\r\ntypedef union {\r\n    struct {\r\n        uint8_t\r\n                band : 4,\r\n                compander : 2,\r\n                scanlist2 : 1,\r\n                scanlist1 : 1;\r\n    };\r\n    uint8_t __val;\r\n} ChannelAttributes_t;\r\n\r\nextern ChannelAttributes_t   gMR_ChannelAttributes[207];\r\n\r\nextern volatile uint16_t     gBatterySaveCountdown_10ms;\r\n\r\nextern volatile bool         gPowerSaveCountdownExpired;\r\nextern volatile bool         gSchedulePowerSave;\r\n\r\nextern volatile bool         gScheduleDualWatch;\r\n\r\nextern volatile uint16_t     gDualWatchCountdown_10ms;\r\nextern bool                  gDualWatchActive;\r\n\r\nextern volatile uint8_t      gSerialConfigCountDown_500ms;\r\n\r\nextern volatile bool         gNextTimeslice_500ms;\r\n\r\nextern volatile uint16_t     gTxTimerCountdown_500ms;\r\nextern volatile bool         gTxTimeoutReached;\r\n\r\nextern volatile uint16_t     gTailToneEliminationCountdown_10ms;\r\n\r\n#ifdef ENABLE_FMRADIO\r\nextern volatile uint16_t gFmPlayCountdown_10ms;\r\n#endif\r\n#ifdef ENABLE_NOAA\r\nextern volatile uint16_t gNOAA_Countdown_10ms;\r\n#endif\r\nextern bool                  gEnableSpeaker;\r\nextern uint8_t               gKeyInputCountdown;\r\nextern uint8_t               gKeyLockCountdown;\r\nextern uint8_t               gRTTECountdown_10ms;\r\nextern bool                  bIsInLockScreen;\r\nextern uint8_t               gUpdateStatus;\r\nextern uint8_t               gFoundCTCSS;\r\nextern uint8_t               gFoundCDCSS;\r\nextern bool                  gEndOfRxDetectedMaybe;\r\n\r\nextern int16_t               gVFO_RSSI[2];\r\nextern uint8_t               gVFO_RSSI_bar_level[2];\r\n\r\n// battery critical, limit functionality to minimum\r\nextern uint8_t               gReducedService;\r\nextern uint8_t               gBatteryVoltageIndex;\r\n\r\n// we are searching CTCSS/DCS inside RX ctcss/dcs menu\r\nextern bool         gCssBackgroundScan;\r\n\r\n\r\nenum\r\n{\r\n    SCAN_REV = -1,\r\n    SCAN_OFF =  0,\r\n    SCAN_FWD = +1\r\n};\r\n\r\nextern volatile bool     gScheduleScanListen;\r\nextern volatile uint16_t gScanPauseDelayIn_10ms;\r\n\r\nextern AlarmState_t          gAlarmState;\r\nextern uint16_t              gMenuCountdown;\r\nextern bool                  gPttWasReleased;\r\nextern bool                  gPttWasPressed;\r\nextern bool                  gFlagReconfigureVfos;\r\nextern uint8_t               gVfoConfigureMode;\r\nextern bool                  gFlagResetVfos;\r\nextern bool                  gRequestSaveVFO;\r\nextern uint8_t               gRequestSaveChannel;\r\nextern bool                  gRequestSaveSettings;\r\n#ifdef ENABLE_FMRADIO\r\nextern bool              gRequestSaveFM;\r\n#endif\r\nextern uint8_t               gKeypadLocked;\r\nextern bool                  gFlagPrepareTX;\r\n\r\nextern bool                  gFlagAcceptSetting;   // accept menu setting\r\nextern bool                  gFlagRefreshSetting;  // refresh menu display\r\n\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\nextern bool                  gFlagStopTX;\r\nextern bool                  gFlagLastVfo;\r\n#endif\r\n\r\n#ifdef ENABLE_FMRADIO\r\nextern bool              gFlagSaveFM;\r\n#endif\r\nextern bool                  g_CDCSS_Lost;\r\nextern uint8_t               gCDCSSCodeType;\r\nextern bool                  g_CTCSS_Lost;\r\nextern bool                  g_CxCSS_TAIL_Found;\r\n#ifdef ENABLE_VOX\r\nextern bool              g_VOX_Lost;\r\n\textern bool              gVOX_NoiseDetected;\r\n\textern uint16_t          gVoxResumeCountdown;\r\n\textern uint16_t          gVoxPauseCountdown;\r\n#endif\r\n\r\n// true means we are receiving signal\r\nextern bool                  g_SquelchLost;\r\n\r\nextern volatile uint16_t     gFlashLightBlinkCounter;\r\nextern uint8_t               gNextMrChannel;\r\nextern ReceptionMode_t       gRxReceptionMode;\r\n\r\n//TRUE when dual watch is momentarly suspended and RX_VFO is locked to either last TX or RX\r\nextern bool                  gRxVfoIsActive;\r\nextern uint8_t               gAlarmToneCounter;\r\nextern uint16_t              gAlarmRunningCounter;\r\nextern bool                  gKeyBeingHeld;\r\nextern bool                  gPttIsPressed;\r\nextern uint8_t               gPttDebounceCounter;\r\nextern uint8_t               gMenuListCount;\r\nextern uint8_t               gBackup_CROSS_BAND_RX_TX;\r\nextern uint8_t               gScanDelay_10ms;\r\n#ifdef ENABLE_AIRCOPY\r\nextern uint8_t           gAircopySendCountdown;\r\n#endif\r\nextern uint8_t               gFSKWriteIndex;\r\n#ifdef ENABLE_NOAA\r\nextern bool              gIsNoaaMode;\r\n\textern uint8_t           gNoaaChannel;\r\n#endif\r\nextern volatile bool         gNextTimeslice;\r\nextern bool                  gUpdateDisplay;\r\n#ifdef ENABLE_FMRADIO\r\nextern uint8_t           gFM_ChannelPosition;\r\n#endif\r\nextern uint8_t               gShowChPrefix;\r\nextern volatile uint8_t      gFoundCDCSSCountdown_10ms;\r\nextern volatile uint8_t      gFoundCTCSSCountdown_10ms;\r\n#ifdef ENABLE_VOX\r\nextern volatile uint16_t gVoxStopCountdown_10ms;\r\n#endif\r\nextern volatile bool         gNextTimeslice40ms;\r\n#ifdef ENABLE_NOAA\r\nextern volatile uint16_t gNOAACountdown_10ms;\r\n\textern volatile bool     gScheduleNOAA;\r\n#endif\r\nextern volatile bool         gFlagTailToneEliminationComplete;\r\nextern volatile uint8_t      gVFOStateResumeCountdown_500ms;\r\n#ifdef ENABLE_FMRADIO\r\nextern volatile bool     gScheduleFM;\r\n#endif\r\nextern uint8_t               gIsLocked;\r\nextern volatile uint8_t      boot_counter_10ms;\r\nextern unsigned int last_rx_vfo;\r\nint32_t NUMBER_AddWithWraparound(int32_t Base, int32_t Add, int32_t LowerLimit, int32_t UpperLimit);\r\nunsigned long StrToUL(const char * str);\r\nvoid FUNCTION_NOP();\r\ninline bool SerialConfigInProgress() { return gSerialConfigCountDown_500ms != 0; }\r\n\r\n\r\n#endif\r\n"
  },
  {
    "path": "openocd-win/README.md",
    "content": "# The xPack OpenOCD\n\nThe **xPack OpenOCD** (formerly GNU MCU Eclipse OpenOCD)\nis the **xPack** version of **OpenOCD**,\nan open-source project.\n\nFor more details, please read the corresponding release pages:\n\n- <https://xpack.github.io/openocd/releases/>\n- <https://openocd.org>\n\nThank you for using open source software,\n\nLiviu Ionescu\n"
  },
  {
    "path": "openocd-win/openocd/OpenULINK/ulink_firmware.hex",
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0474FB\n:100DC700FE5CFB907F97EBF07C00C3EC9523500310\n:100DD7000C80F7EFC313FF907F9774044BF07C00F0\n:100DE700C3EC952350030C80F70EBE080040C50ADC\n:100DF7008094E5372A240524C0F582E4347DF58301\n:100E0700E0FFAE3A7C00C3EC9539505AEF30E0056D\n:100E170043030180068B0274FE5AFBA8397A001837\n:100E2700B8FF011A8C017D00E9B50011EDB5020D7F\n:100E3700EE600A4303021EE53BC313F53B907F9721\n:100E4700EBF07D00C3ED952350030D80F7EFC3133F\n:100E5700FF907F9774044BF07D00C3ED95235003FB\n:100E67000D80F70C80A0EE6008853B0A8E82021287\n:100E77008122E582FF24C0F582E4347DF583E0F525\n:100E87003DEF0424C0F582E4347DF583E0F53E743C\n:100E9700022FFC24C0F582E4347DF583E0C4540FAF\n:100EA700FB53030FEC24C0F582E4347DF583E0FCAB\n:100EB700740F5CF53F74032F24C0F582E4347DF58D\n:100EC70083E0FA74042F24C0F582E4347DF583E0CF\n:100ED700F540EB600B8A0A8B82C00712124AD007D3\n:100EE700907F97E0FB5303F97A00A83D7C0018B880\n:100EF700FF011C8A017E00C3E998EE64808CF063D1\n:100F0700F08095F0505CEF2A240524C0F582E43484\n:100F17007DF583E0F5417C007900E54130E005434C\n:100F2700030180068B0074FE58FB907F97EBF0E57A\n:100F370041C313F541907F9774044BF0ECC313FC46\n:100F4700907F99E0F830E50343048009B908004031\n:100F5700C9E53C2A2400F582E4347EF583ECF00AE7\n:100F670080888A01EF2A240524C0F582E4347DF5C0\n:100F770083E0F5417C00AF3F754200C3E542953EF3\n:100F87005057E54130E00543030180068B0074FEAE\n:100F970058FBA83E7D0018B8FF011DAA427E00EA53\n:100FA700B50011EEB5050DEF600A4303021FE540DA\n:100FB700C313F540907F97EBF0E541C313F54190DC\n:100FC7007F9774044BF0ECC313FC907F99E0FE30DD\n:100FD700E503430480054280A2AD3E7E007408C34A\n:100FE7009DFDE49EFE8DF005F0EC8002C313D5F065\n:100FF700FBFCE53C292400F582E4347EF583ECF024\n:10100700EF600885400A8F8202124A22E582F54482\n:1010170024C0F582E4347DF583E0F545E5440424F6\n:10102700C0F582E4347DF583E0F54674022544FC7F\n:1010370024C0F582E4347DF583E0C4540FFB5303E9\n:101047000FEC24C0F582E4347DF583E0FC740F5C7B\n:10105700F5477403254424C0F582E4347DF583E025\n:10106700FA7404254424C0F582E4347DF583E0F561\n:1010770048EB60078A0A8B82121281907F97E0FB08\n:101087005303F97A00A8457C0018B8FF011C8A06AB\n:101097007F00C3EE98EF64808CF063F08095F0508A\n:1010A70074E5442A240524C0F582E4347DF583E001\n:1010B700F5497E007C00E54930E0054303018006E1\n:1010C7008B0074FE58FB907F97EBF07800C3E89590\n:1010D7002450030880F7E549C313F549907F9774B7\n:1010E700044BF07800C3E8952450030880F7EEC35B\n:1010F70013FE907F99E0F830E5034306800CBC08A7\n:101107000040B3E5432A2400F582E4347EF583EEFC\n:10111700F00A02108C8A04E5442A240524C0F582CB\n:10112700E4347DF583E0F5497E00AA47754A00C39C\n:10113700E54A9546506DE54930E0054303018006D1\n:101147008B0174FE59FBA9467D0019B9FF011DA843\n:101157004A7F00E8B50111EFB5050DEA600A4303C0\n:10116700021AE548C313F548907F97EBF07F00C359\n:10117700EF952450030F80F7E549C313F549907F96\n:101187009774044BF07F00C3EF952450030F80F74B\n:10119700EEC313FE907F99E0FF30E5034306800519\n:1011A7004A808CAD467F007408C39DFDE49FFF8D88\n:1011B700F005F0EE8002C313D5F0FBFEE5432C24C7\n:1011C70000F582E4347EF583EEF0EA600885480A8C\n:1011D7008A8202128122AE82AF83907F97E0FD530D\n:1011E70005FB74044DFC7A007B00C3EA9EEB9F501D\n:1011F7000E907F97EDF0ECF00ABA00EE0B80EB2231\n:10120700AE82AF83907F97E0FD5305FB74044DFCDE\n:101217007A007B00C3EA9EEB9F5027907F97EDF003\n:101227007900C3E9952550030980F7907F97ECF083\n:101237007900C3E9952550030980F70ABA00D50B51\n:1012470080D222AF82907F97E0FE5306FB7D00C3DA\n:10125700ED9F5025E50A30E00543060280068E041F\n:1012670074FD5CFE907F97EEF0E50AC313F50A90D4\n:101277007F9774044EF00D80D622AF82907F97E05F\n:10128700FE5306FB7D00C3ED9F503BE50A30E005AA\n:1012970043060280068E0474FD5CFE907F97EEF095\n:1012A7007C00C3EC952650030C80F7E50AC313F5C1\n:1012B7000A907F9774044EF07C00C3EC9526500388\n:1012C7000C80F70D80C0227F00907F99E0FE30E50B\n:1012D700027F01907F99E0FE30E603430702907F8B\n:1012E7009AE0FE30E703430704907F9BE0FE30E57A\n:1012F70003430708907F9AE0FE53067F8F05E4FFBC\n:10130700FCEE4FF582EC4DF58322E582547FF4FF26\n:10131700907F97E05FF0747F550AFF907F97E04FCB\n:10132700F022858222850A23850B24850C25850DCD\n:10133700262200227E567F021EBEFF011FEE4F703F\n:10134700F722750A05750B001213A6AE82AF837CD0\n:10135700007D00C3EC9EED9F501AC007C006C00574\n:10136700C004121339D004D005D006D0070CBC0036\n:10137700E20D80DF22AE82AF837C007D00C3EC9E4E\n:10138700ED9F501AC007C006C005C00412133BD01A\n:0F13970004D005D006D0070CBC00E20D80DF2289\n:03004300021B009D\n:101B0000020110000201630002016400020165008D\n:101B1000020166000201670002016800020169001B\n:101B200002016A0002016B0002016C0002019300D5\n:101B30000201BA000201BB000201BC000201BD00AB\n:101B40000201BE000201BF000201C0000201C1008B\n:081B50000201C2000201C30002\n:1013A6007A10E4FBFCE58225E0F582E58333F583DC\n:1013B600EB33FBEC33FCEB950AF5F0EC950B4006B2\n:0913C600FCABF0438201DADD22E8\n:0600A000E478FFF6D8FD34\n:10007E007900E94400601B7A009014617800759253\n:10008E0020E493F2A308B800020592D9F4DAF275CF\n:02009E0092FFCF\n:1000A6007800E84400600A7900759220E4F309D8E4\n:1000B600FC7800E84400600C7900902000E4F0A38E\n:0400C600D8FCD9FA8F\n:0D00710075814A1213CFE582600302006E14\n:0413CF007582002201\n:00000001FF\n"
  },
  {
    "path": "openocd-win/openocd/README.md",
    "content": "# The xPack OpenOCD\n\nThe **xPack OpenOCD** (formerly GNU MCU Eclipse OpenOCD)\nis the **xPack** version of **OpenOCD**,\nan open-source project.\n\nFor more details, please read the corresponding release pages:\n\n- <https://xpack.github.io/openocd/releases/>\n- <https://openocd.org>\n\nThank you for using open source software,\n\nLiviu Ionescu\n"
  },
  {
    "path": "openocd-win/openocd/contrib/60-openocd.rules",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Copy this file to /etc/udev/rules.d/\n# If rules fail to reload automatically, you can refresh udev rules\n# with the command \"udevadm control --reload\"\n\nACTION!=\"add|change\", GOTO=\"openocd_rules_end\"\n\nSUBSYSTEM==\"gpio\", MODE=\"0660\", GROUP=\"plugdev\", TAG+=\"uaccess\"\n\nSUBSYSTEM!=\"usb|tty|hidraw\", GOTO=\"openocd_rules_end\"\n\n# Please keep this list sorted by VID:PID\n\n# opendous and estick\nATTRS{idVendor}==\"03eb\", ATTRS{idProduct}==\"204f\", MODE=\"666\"\n\n# Original FT232/FT245 VID:PID\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"6001\", MODE=\"666\"\n\n# Original FT2232 VID:PID\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"6010\", MODE=\"666\"\n\n# Original FT4232 VID:PID\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"6011\", MODE=\"666\"\n\n# Original FT232H VID:PID\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"6014\", MODE=\"666\"\n# Original FT231XQ VID:PID\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"6015\", MODE=\"666\"\n\n# DISTORTEC JTAG-lock-pick Tiny 2\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"8220\", MODE=\"666\"\n\n# TUMPA, TUMPA Lite\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"8a98\", MODE=\"666\"\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"8a99\", MODE=\"666\"\n\n# Marvell OpenRD JTAGKey FT2232D B\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"9e90\", MODE=\"666\"\n\n# XDS100v2\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"a6d0\", MODE=\"666\"\n# XDS100v3\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"a6d1\", MODE=\"666\"\n\n# OOCDLink\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"baf8\", MODE=\"666\"\n\n# Kristech KT-Link\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"bbe2\", MODE=\"666\"\n\n# Xverve Signalyzer Tool (DT-USB-ST), Signalyzer LITE (DT-USB-SLITE)\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"bca0\", MODE=\"666\"\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"bca1\", MODE=\"666\"\n\n# TI/Luminary Stellaris Evaluation Board FTDI (several)\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"bcd9\", MODE=\"666\"\n\n# TI/Luminary Stellaris In-Circuit Debug Interface FTDI (ICDI) Board\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"bcda\", MODE=\"666\"\n\n# egnite Turtelizer 2\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"bdc8\", MODE=\"666\"\n\n# Section5 ICEbear\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"c140\", MODE=\"666\"\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"c141\", MODE=\"666\"\n\n# Amontec JTAGkey and JTAGkey-tiny\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"cff8\", MODE=\"666\"\n\n# ASIX Presto programmer\nATTRS{idVendor}==\"0403\", ATTRS{idProduct}==\"f1a0\", MODE=\"666\"\n\n# Nuvoton NuLink\nATTRS{idVendor}==\"0416\", ATTRS{idProduct}==\"511b\", MODE=\"666\"\nATTRS{idVendor}==\"0416\", ATTRS{idProduct}==\"511c\", MODE=\"666\"\nATTRS{idVendor}==\"0416\", ATTRS{idProduct}==\"511d\", MODE=\"666\"\nATTRS{idVendor}==\"0416\", ATTRS{idProduct}==\"5200\", MODE=\"666\"\nATTRS{idVendor}==\"0416\", ATTRS{idProduct}==\"5201\", MODE=\"666\"\n\n# TI ICDI\nATTRS{idVendor}==\"0451\", ATTRS{idProduct}==\"c32a\", MODE=\"666\"\n\n# STMicroelectronics ST-LINK V1\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"3744\", MODE=\"666\"\n\n# STMicroelectronics ST-LINK/V2\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"3748\", MODE=\"666\"\n\n# STMicroelectronics ST-LINK/V2.1\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"374b\", MODE=\"666\"\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"3752\", MODE=\"666\"\n\n# STMicroelectronics STLINK-V3\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"374d\", MODE=\"666\"\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"374e\", MODE=\"666\"\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"374f\", MODE=\"666\"\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"3753\", MODE=\"666\"\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"3754\", MODE=\"666\"\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"3755\", MODE=\"666\"\nATTRS{idVendor}==\"0483\", ATTRS{idProduct}==\"3757\", MODE=\"666\"\n\n# Cypress SuperSpeed Explorer Kit\nATTRS{idVendor}==\"04b4\", ATTRS{idProduct}==\"0007\", MODE=\"666\"\n\n# Cypress KitProg in KitProg mode\nATTRS{idVendor}==\"04b4\", ATTRS{idProduct}==\"f139\", MODE=\"666\"\n\n# Cypress KitProg in CMSIS-DAP mode\nATTRS{idVendor}==\"04b4\", ATTRS{idProduct}==\"f138\", MODE=\"666\"\n\n# Infineon DAP miniWiggler v3\nATTRS{idVendor}==\"058b\", ATTRS{idProduct}==\"0043\", MODE=\"666\"\n\n# Hitex LPC1768-Stick\nATTRS{idVendor}==\"0640\", ATTRS{idProduct}==\"0026\", MODE=\"666\"\n\n# Hilscher NXHX Boards\nATTRS{idVendor}==\"0640\", ATTRS{idProduct}==\"0028\", MODE=\"666\"\n\n# Hitex STR9-comStick\nATTRS{idVendor}==\"0640\", ATTRS{idProduct}==\"002c\", MODE=\"666\"\n\n# Hitex STM32-PerformanceStick\nATTRS{idVendor}==\"0640\", ATTRS{idProduct}==\"002d\", MODE=\"666\"\n\n# Hitex Cortino\nATTRS{idVendor}==\"0640\", ATTRS{idProduct}==\"0032\", MODE=\"666\"\n\n# Altera USB Blaster\nATTRS{idVendor}==\"09fb\", ATTRS{idProduct}==\"6001\", MODE=\"666\"\n# Altera USB Blaster2\nATTRS{idVendor}==\"09fb\", ATTRS{idProduct}==\"6010\", MODE=\"666\"\nATTRS{idVendor}==\"09fb\", ATTRS{idProduct}==\"6810\", MODE=\"666\"\n\n# Ashling Opella-LD\nATTRS{idVendor}==\"0B6B\", ATTRS{idProduct}==\"0040\", MODE=\"666\"\n\n# Amontec JTAGkey-HiSpeed\nATTRS{idVendor}==\"0fbb\", ATTRS{idProduct}==\"1000\", MODE=\"666\"\n\n# SEGGER J-Link\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"0101\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"0102\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"0103\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"0104\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"0105\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"0107\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"0108\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1010\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1011\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1012\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1013\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1014\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1015\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1016\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1017\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1018\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1020\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1051\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1055\", MODE=\"666\"\nATTRS{idVendor}==\"1366\", ATTRS{idProduct}==\"1061\", MODE=\"666\"\n\n# Raisonance RLink\nATTRS{idVendor}==\"138e\", ATTRS{idProduct}==\"9000\", MODE=\"666\"\n\n# Debug Board for Neo1973\nATTRS{idVendor}==\"1457\", ATTRS{idProduct}==\"5118\", MODE=\"666\"\n\n# OSBDM\nATTRS{idVendor}==\"15a2\", ATTRS{idProduct}==\"0042\", MODE=\"666\"\nATTRS{idVendor}==\"15a2\", ATTRS{idProduct}==\"0058\", MODE=\"666\"\nATTRS{idVendor}==\"15a2\", ATTRS{idProduct}==\"005e\", MODE=\"666\"\n\n# Olimex ARM-USB-OCD\nATTRS{idVendor}==\"15ba\", ATTRS{idProduct}==\"0003\", MODE=\"666\"\n\n# Olimex ARM-USB-OCD-TINY\nATTRS{idVendor}==\"15ba\", ATTRS{idProduct}==\"0004\", MODE=\"666\"\n\n# Olimex ARM-JTAG-EW\nATTRS{idVendor}==\"15ba\", ATTRS{idProduct}==\"001e\", MODE=\"666\"\n\n# Olimex ARM-USB-OCD-TINY-H\nATTRS{idVendor}==\"15ba\", ATTRS{idProduct}==\"002a\", MODE=\"666\"\n\n# Olimex ARM-USB-OCD-H\nATTRS{idVendor}==\"15ba\", ATTRS{idProduct}==\"002b\", MODE=\"666\"\n\n# ixo-usb-jtag - Emulation of a Altera Bus Blaster I on a Cypress FX2 IC\nATTRS{idVendor}==\"16c0\", ATTRS{idProduct}==\"06ad\", MODE=\"666\"\n\n# USBprog with OpenOCD firmware\nATTRS{idVendor}==\"1781\", ATTRS{idProduct}==\"0c63\", MODE=\"666\"\n\n# TI/Luminary Stellaris In-Circuit Debug Interface (ICDI) Board\nATTRS{idVendor}==\"1cbe\", ATTRS{idProduct}==\"00fd\", MODE=\"666\"\n\n# TI XDS110 Debug Probe (Launchpads and Standalone)\nATTRS{idVendor}==\"0451\", ATTRS{idProduct}==\"bef3\", MODE=\"666\"\nATTRS{idVendor}==\"0451\", ATTRS{idProduct}==\"bef4\", MODE=\"666\"\nATTRS{idVendor}==\"1cbe\", ATTRS{idProduct}==\"02a5\", MODE=\"666\"\n\n# TI Tiva-based ICDI and XDS110 probes in DFU mode\nATTRS{idVendor}==\"1cbe\", ATTRS{idProduct}==\"00ff\", MODE=\"666\"\n\n# isodebug v1\nATTRS{idVendor}==\"22b7\", ATTRS{idProduct}==\"150d\", MODE=\"666\"\n\n# PLS USB/JTAG Adapter for SPC5xxx\nATTRS{idVendor}==\"263d\", ATTRS{idProduct}==\"4001\", MODE=\"666\"\n\n# Numato Mimas A7 - Artix 7 FPGA Board\nATTRS{idVendor}==\"2a19\", ATTRS{idProduct}==\"1009\", MODE=\"666\"\n\n# Ambiq Micro EVK and Debug boards.\nATTRS{idVendor}==\"2aec\", ATTRS{idProduct}==\"6010\", MODE=\"666\"\nATTRS{idVendor}==\"2aec\", ATTRS{idProduct}==\"6011\", MODE=\"666\"\nATTRS{idVendor}==\"2aec\", ATTRS{idProduct}==\"1106\", MODE=\"666\"\n\n# Espressif USB JTAG/serial debug units\nATTRS{idVendor}==\"303a\", ATTRS{idProduct}==\"1001\", MODE=\"666\"\nATTRS{idVendor}==\"303a\", ATTRS{idProduct}==\"1002\", MODE=\"666\"\n\n# ANGIE USB-JTAG Adapter\nATTRS{idVendor}==\"584e\", ATTRS{idProduct}==\"424e\", MODE=\"666\"\nATTRS{idVendor}==\"584e\", ATTRS{idProduct}==\"4255\", MODE=\"666\"\nATTRS{idVendor}==\"584e\", ATTRS{idProduct}==\"4355\", MODE=\"666\"\nATTRS{idVendor}==\"584e\", ATTRS{idProduct}==\"4a55\", MODE=\"666\"\n\n# Marvell Sheevaplug\nATTRS{idVendor}==\"9e88\", ATTRS{idProduct}==\"9e8f\", MODE=\"666\"\n\n# Keil Software, Inc. ULink\nATTRS{idVendor}==\"c251\", ATTRS{idProduct}==\"2710\", MODE=\"666\"\nATTRS{idVendor}==\"c251\", ATTRS{idProduct}==\"2750\", MODE=\"666\"\n\n# CMSIS-DAP compatible adapters\nATTRS{product}==\"*CMSIS-DAP*\", MODE=\"666\"\n\nLABEL=\"openocd_rules_end\"\n"
  },
  {
    "path": "openocd-win/openocd/contrib/libdcc/README",
    "content": "This code is an example of using the openocd debug message system.\n\nBefore the message output is seen in the debug window, the functionality\nwill need enabling:\n\nFrom the gdb prompt:\nmonitor target_request debugmsgs enable\nmonitor trace point 1\n\nFrom the Telnet prompt:\ntarget_request debugmsgs enable\ntrace point 1\n\nTo see how many times the trace point was hit:\n(monitor) trace point 1\n\nSpen\nspen@spen-soft.co.uk\n"
  },
  {
    "path": "openocd-win/openocd/contrib/libdcc/dcc_stdio.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/***************************************************************************\n *   Copyright (C) 2008 by Dominic Rath                                    *\n *   Dominic.Rath@gmx.de                                                   *\n *   Copyright (C) 2008 by Spencer Oliver                                  *\n *   spen@spen-soft.co.uk                                                  *\n *   Copyright (C) 2008 by Frederik Kriewtz                                *\n *   frederik@kriewitz.eu                                                  *\n ***************************************************************************/\n\n#include \"dcc_stdio.h\"\n\n#define TARGET_REQ_TRACEMSG\t\t\t\t\t0x00\n#define TARGET_REQ_DEBUGMSG_ASCII\t\t\t0x01\n#define TARGET_REQ_DEBUGMSG_HEXMSG(size)\t(0x01 | ((size & 0xff) << 8))\n#define TARGET_REQ_DEBUGCHAR\t\t\t\t0x02\n\n#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_6SM__)\n\n/* we use the System Control Block DCRDR reg to simulate a arm7_9 dcc channel\n * DCRDR[7:0] is used by target for status\n * DCRDR[15:8] is used by target for write buffer\n * DCRDR[23:16] is used for by host for status\n * DCRDR[31:24] is used for by host for write buffer */\n\n#define NVIC_DBG_DATA_R\t\t(*((volatile unsigned short *)0xE000EDF8))\n\n#define\tBUSY\t1\n\nvoid dbg_write(unsigned long dcc_data)\n{\n\tint len = 4;\n\n\twhile (len--)\n\t{\n\t\t/* wait for data ready */\n\t\twhile (NVIC_DBG_DATA_R & BUSY);\n\n\t\t/* write our data and set write flag - tell host there is data*/\n\t\tNVIC_DBG_DATA_R = (unsigned short)(((dcc_data & 0xff) << 8) | BUSY);\n\t\tdcc_data >>= 8;\n\t}\n}\n\n#elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5T__)\n\nvoid dbg_write(unsigned long dcc_data)\n{\n\tunsigned long dcc_status;\n\n\tdo {\n\t\tasm volatile(\"mrc p14, 0, %0, c0, c0\" : \"=r\" (dcc_status));\n\t} while (dcc_status & 0x2);\n\n\tasm volatile(\"mcr p14, 0, %0, c1, c0\" : : \"r\" (dcc_data));\n}\n\n#else\n #error unsupported target\n#endif\n\nvoid dbg_trace_point(unsigned long number)\n{\n\tdbg_write(TARGET_REQ_TRACEMSG | (number << 8));\n}\n\nvoid dbg_write_u32(const unsigned long *val, long len)\n{\n\tdbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(4) | ((len & 0xffff) << 16));\n\n\twhile (len > 0)\n\t{\n\t\tdbg_write(*val);\n\n\t\tval++;\n\t\tlen--;\n\t}\n}\n\nvoid dbg_write_u16(const unsigned short *val, long len)\n{\n\tunsigned long dcc_data;\n\n\tdbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(2) | ((len & 0xffff) << 16));\n\n\twhile (len > 0)\n\t{\n\t\tdcc_data = val[0]\n\t\t\t| ((len > 1) ? val[1] << 16: 0x0000);\n\n\t\tdbg_write(dcc_data);\n\n\t\tval += 2;\n\t\tlen -= 2;\n\t}\n}\n\nvoid dbg_write_u8(const unsigned char *val, long len)\n{\n\tunsigned long dcc_data;\n\n\tdbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(1) | ((len & 0xffff) << 16));\n\n\twhile (len > 0)\n\t{\n\t\tdcc_data = val[0]\n\t\t\t| ((len > 1) ? val[1] << 8 : 0x00)\n\t\t\t| ((len > 2) ? val[2] << 16 : 0x00)\n\t\t\t| ((len > 3) ? val[3] << 24 : 0x00);\n\n\t\tdbg_write(dcc_data);\n\n\t\tval += 4;\n\t\tlen -= 4;\n\t}\n}\n\nvoid dbg_write_str(const char *msg)\n{\n\tlong len;\n\tunsigned long dcc_data;\n\n\tfor (len = 0; msg[len] && (len < 65536); len++);\n\n\tdbg_write(TARGET_REQ_DEBUGMSG_ASCII | ((len & 0xffff) << 16));\n\n\twhile (len > 0)\n\t{\n\t\tdcc_data = msg[0]\n\t\t\t| ((len > 1) ? msg[1] << 8 : 0x00)\n\t\t\t| ((len > 2) ? msg[2] << 16 : 0x00)\n\t\t\t| ((len > 3) ? msg[3] << 24 : 0x00);\n\t\tdbg_write(dcc_data);\n\n\t\tmsg += 4;\n\t\tlen -= 4;\n\t}\n}\n\nvoid dbg_write_char(char msg)\n{\n\tdbg_write(TARGET_REQ_DEBUGCHAR | ((msg & 0xff) << 16));\n}\n"
  },
  {
    "path": "openocd-win/openocd/contrib/libdcc/dcc_stdio.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-or-later */\n\n/***************************************************************************\n *   Copyright (C) 2008 by Dominic Rath                                    *\n *   Dominic.Rath@gmx.de                                                   *\n *   Copyright (C) 2008 by Spencer Oliver                                  *\n *   spen@spen-soft.co.uk                                                  *\n ***************************************************************************/\n\n#ifndef DCC_STDIO_H\n#define DCC_STDIO_H\n\nvoid dbg_trace_point(unsigned long number);\n\nvoid dbg_write_u32(const unsigned long *val, long len);\nvoid dbg_write_u16(const unsigned short *val, long len);\nvoid dbg_write_u8(const unsigned char *val, long len);\n\nvoid dbg_write_str(const char *msg);\nvoid dbg_write_char(char msg);\n\n#endif\t/* DCC_STDIO_H */\n"
  },
  {
    "path": "openocd-win/openocd/contrib/libdcc/example.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/***************************************************************************\n *   Copyright (C) 2008 by Spencer Oliver                                  *\n *   spen@spen-soft.co.uk                                                  *\n *   Copyright (C) 2008 by Frederik Kriewtz                                *\n *   frederik@kriewitz.eu                                                  *\n ***************************************************************************/\n\n#include \"dcc_stdio.h\"\n\n/* enable openocd debugmsg at the gdb prompt:\n * monitor target_request debugmsgs enable\n *\n * create a trace point:\n * monitor trace point 1\n *\n * to show how often the trace point was hit:\n * monitor trace point\n*/\n\nint main(void)\n{\n\tdbg_write_str(\"hello world\");\n\n\tdbg_write_char('t');\n\tdbg_write_char('e');\n\tdbg_write_char('s');\n\tdbg_write_char('t');\n\tdbg_write_char('\\n');\n\n\tunsigned long test_u32 = 0x01234567;\n\tdbg_write_u32(&test_u32, 1);\n\n\tstatic const unsigned short test_u16[] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x0123, 0x4567, 0x89AB, 0xCDEF};\n\tdbg_write_u16(test_u16, 8);\n\n\tstatic const unsigned char test_u8[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0XDD, 0xEE, 0xFF};\n\tdbg_write_u8(test_u8, 16);\n\n\twhile(1)\n\t{\n\t\tdbg_trace_point(0);\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/CHANGELOG.md",
    "content": "# Change & release log\n\nEntries in this file are in reverse chronological order.\n\n## 2023-09-04\n\n* 8186554 package-lock.json update\n* bdd0375 package.json: use github: helper\n* 43fb8ee package.json: remove pkg-config from deps\n* 99526e9 versioning.sh: bump deps\n* 6743160 versioning.sh: update for latest commit\n* f8e0808 openocd.sh: run_verbose diff\n* c8379f3 CHANGELOG update\n* 5a3f058 README updates\n* 88994ee package.json: bump deps\n* 012f130 dot.*ignore update\n* d3d94dd re-generate workflows\n\n## 2023-09-03\n\n* 70caa99 package.json: bump deps\n\n## 2023-08-28\n\n* b3de5ce READMEs update\n\n## 2023-08-25\n\n* e0e3c8e package.json: rm xpack-dev-tools-build/*\n* e4c5804 package.json: bump deps\n\n## 2023-08-21\n\n* e13385a READMEs update\n* 82b20e2 package.json: bump deps\n\n## 2023-08-19\n\n* c1aa321 READMEs update\n* f2f7239 package.json: bump deps\n\n## 2023-08-15\n\n* 8dd0d21 re-generate workflows\n* f959671 README-MAINTAINER rename xbbla\n* 60ff8ef package.json: rename xbbla\n* a20733a package.json: bump deps\n* 27277ab READMEs update\n* ddcc6a0 package.json: bump deps\n\n## 2023-08-05\n\n* 378cbda READMEs update\n\n## 2023-08-04\n\n* 3c3e82e READMEs update\n* 835a8d2 READMEs update\n* 1188627 READMEs update\n\n## 2023-08-03\n\n* 92f9c49 package.json: reorder build actions\n* 7a5f3eb READMEs update\n* 5be3464 package.json: bump deps\n\n## 2023-07-28\n\n* 0f34460 READMEs update\n* 3e3bceb READMEs update\n* f743191 package.json: bump deps\n* bbd6eb2 package.json: liquidjs --context --template\n* 65ea0a9 scripts cosmetics\n* cb1d34c re-generate workflows\n* 629a380 READMEs update\n* 9cdb678 package.json: minXpm 0.16.3 & @xpack-dev-tools/xbb-helper\n* 40dfb2a READMEs update\n* 77b1b4b package.json: bump deps\n\n## 2023-07-26\n\n* 60a3907 package.json: move scripts to actions\n* c26109e package.json: update xpack-dev-tools path\n* 193f4d5 READMEs update xpack-dev-tools path\n* ef9e796 .vscode/launch.json update\n* fc6ac8c body-jekyll update\n* 2774d4e READMEs update\n\n## 2023-07-17\n\n* 03631fd package.json: bump deps\n* 05f05aa package.json: add -develop-debug actions\n\n## 2023-07-08\n\n* 08fe285 versioning.sh: add 0.12.0-2 commit id\n* 592885b ~/Work/xpack-dev-tools/\n* 5423546 prepare v0.12.0-2\n\n## 2023-04-19\n\n* a6ed8e5 Merge pull request #26 from zqb-all/fix_typo\n* 2aab171 README: fix typo\n\n## 2023-03-31\n\n* 574ff3c README-DEVELOP.md: update\n* 3909232 README-DEVELOP.md: update\n* 63a1335 README-DEVELOP.md: update deep-clean\n* 8e35423 openocd.sh: --enable-internal-libjaylink\n\n## 2023-03-28\n\n* 068dc2d README-DEVELOPER update\n\n## 2023-03-27\n\n* d531f0b README-DEVELOPER update\n* 180d15d README-DEVELOPER update\n\n## 2023-03-25\n\n* 7f7d1db README update\n* c1891fb add README-DEVELOPER.md\n* 29c93c1 READMEs update\n* 26ecf82 READMEs update prerequisites\n\n## 2023-03-24\n\n* 85dfffc package.json: mkdir -pv cache\n* b5081e9 README update\n* c312703 .vscode/settings.json: ignoreWords\n* 07cb567 README-MAINTAINER.md update\n* e320656 README-MAINTAINER: update prerequisites\n\n## 2023-02-22\n\n* 33e43d0 READMEs update\n\n## 2023-02-14\n\n* 32fbd24 body-jekyll update\n\n* ebf9368 package.json: update Work/xpacks\n* 73b0ea7 READMEs update\n\n## 2023-02-07\n\n* 65251a2 READMEs update\n* 813a0e2 package.json: bump deps & reorder git-log\n* 68ba49c versioning.sh: update for https\n* 1ed35c9 body-jekyll update\n\n## 2023-01-30\n\n* 65cdee4 0.12.0-1.1\n* 85ad2d2 CHANGELOG: publish npm v0.12.0-1.1\n* f82dae3 package.json: update urls for 0.12.0-1.1 release\n* e79ff4c READMEs updates\n* af00549 body-jekyll update\n* 8022518 CHANGELOG update\n* b6da41e .vscode/settings.json: ignoreWords\n* v0.12.0-1 released\n* f37a409 README update\n* 3b8d65d remove unused XBB_BRANDING\n* bd6d610 openocd.sh: move docs to LIBRARIES\n* 381fa84 versioning.sh: move GIT_URL defs\n* e0f02bf add .vscode/launch.json\n* 61987a9 package.json: bump deps\n* 73ca561 README updates\n* 8bb511b openocd.sh: re-enable parallel build\n* 65aee84 openocd.sh: use only -ludev on linux\n* 2d369c1 openocd.sh: apply patches locally\n* 427c081 .vscode/settings.json: ignoreWords\n* e619b4d prepare v0.12.0-1\n\n## 2023-01-29\n\n* v0.12.0-1 prepared\n* 02486b4 re-generate workflows\n* 53c05f2 package.json: bump deps\n\n## 2023-01-28\n\n* bcce8c3 versioning.sh: use versioning functions\n* 949bed6 README-MAINTAINER remove caffeinate xpm\n\n## 2023-01-27\n\n* 3b80250 package.json: reorder scripts\n\n## 2023-01-24\n\n* b16e64a README updates\n\n## 2023-01-22\n\n* ac30acd README update\n\n## 2023-01-11\n\n* 4b20bb2 cosmetize xbb_adjust_ldflags_rpath\n\n## 2023-01-09\n\n* ceef268 package.json: bump deps\n* 777c73c package.json: loglevel info\n* 201a58c versioning.sh: add comment before *_installed_bin\n\n## 2023-01-02\n\n* ae9ffd4 package.json: add gcc to windows deps\n\n## 2023-01-01\n\n* 528e1f2 package.json: pass xpm version & loglevel\n* 099a8d5 README update\n\n## 2022-12-30\n\n* fef7655 README-MAINTAINER: xpm run install\n* 3556cba package.json: bump deps\n* f8576b0 versioning.sh: regexp\n\n## 2022-12-27\n\n* d8e72c0 README update\n* 30753c6 echo FUNCNAME[0]\n* 62b1cd0 use autotools_build\n* d588a1f move *_installed_bin to versions.sh\n* c7a592c re-generate from templates\n* 927f3a9 cosmetics: move versions to the top\n\n## 2022-12-26\n\n* 0258972 README updates\n\n## 2022-12-25\n\n* fce7aa2 README update\n* 12952ed versioning.sh: remove explicit xbb_set_executables_install_path\n* 8e83ec7 package.json: add m4 dep\n* 975d1d4 versioning.sh: add comment M4\n\n## 2022-12-24\n\n* 5452b76 README updates\n* 241998a openocd.sh: pass path to test\n* 719eb0a updates for xbb v 5.x\n* 54da172 test.sh: update\n* 3c40213 package.json: update\n* 23269b2 package.json: bump deps\n* 0e195e4 re-generate from templates\n* d93b8ef rename functions\n\n## 2022-12-12\n\n* d41e004 package.json: add caffeinate builds for macOS\n* cca6fcc versioning.sh: use XBB_REQUESTED_*\n\n## 2022-11-18\n\n* e92dd4c .vscode/settings.json: watcherExclude\n\n## 2022-10-28\n\n* 1e9b995 cleanups\n* 6b1c896 tests/run.sh: cosmetics\n* 6237479 README updates\n* 4b65463 README update\n* d713f53 openocd.sh: fix test\n* 33eebca .gitignore xpacks\n\n## 2022-10-27\n\n* 9757baa package.json: bump deps\n* 08b7b90 package.json: bump deps\n* a5e069e package.json: bump deps\n* b2ef4b3 package.json: bump deps\n* b5a9472 versioning.sh: adjust LD_LIBRARY_PATH for libusb1\n* 89e5a13 openocd.sh: set -rpath\n* f40f094 bring build_pkg_config back for macOS\n* af34c4f package.json: add ninja to deps\n* 15f9671 package.json: add cmake to deps\n* ac46aa1 run.sh: cleanups\n* 14be2a2 application.sh: remove pkg-config coreutils\n* 582c24f versioning.sh: remove build_pkg_config\n* 0f5a08d versioning.sh: build_application_versioned_components\n* cc1087a README updates\n* 1183e66 package.json: cp build.sh & test.sh\n* ba1fd0b package.json: bump deps & cleanups\n* cf2b53f .vscode/settings.json: ignoreWords\n* 14504f4 re-generate workflows & scripts\n\n## 2022-10-23\n\n* 821a513 package.json: bump deps\n* f332865 package.json: bump deps\n* c4b9381 READMEs update\n* fb51384 package.json: add devDep realpath\n* 0a13362 package.json: reorder actions\n* c9f1e2e versioning.sh: remove build_coreutils\n* 4a05989 cosmetics\n* d19ddee test.sh: update\n* 19956f9 build.sh: update\n* d328879 rename application.sh\n\n## 2022-10-19\n\n* b853e1c READMEs updates\n* 8b816e4 versioning.sh: add XBB_COREUTILS_INSTALL_REALPATH_ONLY\n* cd61164 updates for xbb v4.0\n* 88d94dc remove patches & pkgconfig (moved to helper)\n* 1a676ae re-generate workflows\n\n## 2022-10-18\n\n* d15ec21 remove submodule\n\n## 2022-10-04\n\n* 101682e README-RELEASE update for bullet lists in CHANGELOG\n\n## 2022-09-25\n\n* 30cf7d8 README-RELEASE update\n\n## 2022-09-17\n\n* d2d81ea package.json: remove -ia32\n* 049765b README update\n* 34d14ba README-BUILD update\n\n## 2022-09-03\n\n* 72e5bc5 READMEs updates\n\n## 2022-09-01\n\n* v0.11.0-5 published on npmjs.com\n* v0.11.0-5 released\n\n## 2022-03-25\n\n* v0.11.0-4 published on npmjs.com\n* v0.11.0-4 published\n\n## 2021-12-07\n\n* v0.11.0-3 published on npmjs.com\n* v0.11.0-3 released\n\n## 2021-11-21\n\n* v0.11.0-3 prepared\n* update for Apple Silicon\n\n## 2021-10-16\n\n* v0.11.0-2 published on npmjs.com\n* v0.11.0-2 released\n\n## 2021-08-27\n\n* v0.11.0-2 prepared\n* [#10] - fix copying license sub-folders\n\n## 2021-03-15\n\n* v0.11.0-1 prepared\n* update to upstream 0.11\n* [#3] - remove deprecated --enable-oocd_trace\n* v0.11.0-1 published\n* v0.11.0-1.1 published on npmjs.com\n\n## 2020-10-13\n\n* v0.10.0-15 published\n* v0.10.0-15.1 published on npmjs.com\n\n## 2020-06-27\n\n* v0.10.0-13.2 published on npmjs.com\n\n## 2020-06-26\n\n* v0.10.0-14.2 published on npmjs.com (wrong skip:3)\n* v0.10.0-14.1 published on npmjs.com (wrong .tgz extension)\n* v0.10.0-14 released\n* add binaries for Arm 32/64-bit\n* update for XBB v3.2\n* based on openocd.git 8833c889da07eae750bcbc11215cc84323de9b74 from June 23rd, 2020\n\n## 2020-03-26\n\n* update for XBB v3.1\n* based on openocd.git d9ffe75e257aa4005dd34603860e45c57b1765b6\n\n## 2019-07-27\n\n* bump v0.10.0-14\n* add support for Arm binaries\n* based on openocd.git e1e63ef30cea39aceda40daf194377c89c570101\n\n## 2019-07-20\n\n* v0.10.0-13.1 published on npmjs.com\n\n## 2019-07-17\n\n* v0.10.0-13 released\n\n## 2019-07-08\n\n* update to 263deb380 from 7 Jul 2019\n\n___\n\n# Historical GNU MCU Eclipse change log\n\n## 2019-04-23\n\n* v0.10.0-12-20190423 released\n\n## 2019-04-09\n\n* prepare - v0.10.0-12\n* update to latest master from Apr 7th, 2019\n* update LIBUSB1_VERSION=\"1.0.22\"\n* update LIBFTDI_VERSION=\"1.4\"\n\n## 2019-01-18\n\n* v0.10.0-11-20190118 released\n* update to latest master from Jan 16, 2019\n* RISC-V specific patches were removed, only upstreamed functionality retained.\n\n## 2018-10-20\n\n* v0.10.0-10-20181020 released\n* rerun, to fix the macOS file dates\n* update the -bit to singular\n\n## 2018-10-16\n\n* v0.10.0-9-20181016 released\n* update to latest master\n* update to latest RISC-V\n* revert some of the RISC-V patches in the common files\n\n## 2018-06-19\n\n* update to latest RISC-V commits, including semihosting\n\n## 2018-06-12\n\n* use separate README-*.md files\n* update to latest commits, which include new semihosting (OpenOCD June 6th, RISC-V June 12th)\n\n## 2018-05-12\n\n* v0.10.0-8-20180512 released\n* use new build scripts based on XBB\n* update to latest commits (OpenOCD April 27th, RISC-V May 8th)\n\n## 2018-01-23\n\n* v0.10.0-7-20180123 released\n* move semihosting code to separate files\n* use them in RISC-V and ARM\n* add 'arm semihosting_resexit enable' to allow exit() to return\n\n## 2018-01-12\n\n* v0.10.0-6-20180112 released\n* update to master from Dec 20\n* update to riscv from Dec 29\n* remove the patch to hide the CSRs, the new version displays only a limited number of them.\n* remove the `remote_bitbang.c` patch, since it compiles ok on mingw-w64\n* the SiFive board scripts were upstreamed to the RISC-V fork\n\n## 2017-11-10\n\n* v0.10.0-5-20171110-dev released\n* update to master from Oct 2\n* update to riscv from Nov 4\n* target.c & riscv/riscv-0[13].c: hide the 4096 CSRs from `monitor reg`\n* update the SiFive board script files\n* revert the risc-v changes in `remote_bitbang.c`, since they break the build on mingw-w64\n\n## 2017-10-04\n\n* v0.10.0-4-20171004-*-dev released\n* update to master from Aug 10\n* update to riscv fom Oct 2\n* gdb_server.c: workaround to gdb errors; disable passing errors back to gdb since this risc-v change breaks other targets.\n\n## 2017-08-25\n\n* v0.10.0-3-20170826-*-dev released\n* merge RISC-V tag v20170818\n* server.c: fix clang warning in getsockname()\n\n## 2017-07-03\n\n* update build script to use Debian 9 Docker containers\n\n## 2017-06-22\n\n* v0.10.0-2-20170622-1535-dev released\n* merge RISC-V tag v20170621\n\n## 2017-06-15\n\n* move the build specific gnu-mcu-eclipse folder to a separate openocd-build project\n\n## 2017-06-12\n\n* add --enable-riscv and #if BUILD_RISCV\n* add --enable-branding\n\n## 2017-06-07\n\n* v0.10.0-1-20170607-2132-dev released\n* add sifive-* configuration files to the board folder\n* 60-openocd.rules: simplify access rights\n* merge RISC-V commit '11008ba' into gnu-mcu-eclipse-dev\n\n## 2017-06-06\n\n* rename gnu-mcu-eclipse & content\n\n## 2017-06-04\n\n* merge original branch 'master' from 2017-06-02 into gnuarmeclipse-dev.\n* merge RISC-V commit '51ab5a0' from 2017-05-26 into gnuarmeclipse-dev\n\n## 2017-01-24\n\n* v0.10.0-20170124* released (stable)\n* merge original 0.10.0, override local relative path processing\n\n## 2016-10-28\n\n* v0.10.0-20161028*-dev released\n\n## 2016-10-20\n\n* nsi file: add InstallDir; silent install should honour /D\n\n## 2016-01-10\n\n* v0.10.0-20160110*-dev released\n\n## 2015-10-28\n\n* v0.10.0-20151028*-dev released\n\n## 2015-05-19\n\n* v0.9.0-20150519*-dev released\n* remove @raggedright from openocd.texi\n\n## 2015-05-11\n\n* the three separate build scripts were deprecated, and a single script,\nusing Docker, was added to the main gnuarmeclipse-se.git/scripts.\n\n* the greeting shows 32-bits or 64-bits (plural for bits). (wrong!)\n\n## 2015-03-24\n\n* v0.9.0-20150324*-dev released\n* v0.8.0-20150324* released\n\n## 2015-03-22\n\n* the NSIS script was fixed to prevent removing the keys when\nuninstalling an older version.\n\n## 2015-03-20\n\n* v0.9.0-20150320*-dev released\n* v0.8.0-20150320* released\n\n## 2015-03-18\n\n* the build scripts were extended to generate both the stable and the\ndevelopment version.\n\n* multiple versions of the package can be installed in separate folders,\nnamed using the version.\n\n* for Windows, more accurate keys were stored, so remember separate locations\nfor 32/64-bit versions.\n\n## 2015-01-31\n\n* v0.8.0-20150131* released\n\n## 2015-01-30\n\n* gnuarmeclipse\n\nAll GNU ARM Eclipse OpenOCD build related files were grouped under this folder.\n\n* README.md\n\nMarkdown files were added in all new folders, to improve the look when browsed\nin the SourceForge Git web browser.\n\n## 2015-01-19\n\n* v0.8.0-20150119* released\n\n## 2015-01-12\n\n* src/openocd.c\n\nAdd branding 'GNU ARM Eclipse' to the greeting message, to\nmore easily identify this custom version.\n\n* helper/options.c\n\nUpdate the logic used to locate the 'scripts' folder, by\nusing the argv[0], as on Windows. The logic is a bit more\ncomplicated, to accommodate 3 cases (no path, relative path\nand absolute path).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/autoconf-2.71/AUTHORS",
    "content": "Authors of GNU Autoconf.\n\nAutoconf was originally written by David MacKenzie, with help from\nFrançois Pinard, Karl Berry, Richard Pixley, Ian Lance Taylor, Roland\nMcGrath, Noah Friedman, david d zuhn, and many others.\n\nBen Elliston next took over the maintenance, facing a huge Autoconf\nbacklog that had been piling up since the departure of David.  Other\nmaintainers have included Akim Demaille, Jim Meyering, Alexandre\nOliva, and Tom Tromey, with plenty of contributions from Lars J. Aas,\nMo DeJong, Steven G. Johnson, Matthew D. Langston, Pavel Roskin.\n\nToday, the primary maintainers are Paul Eggert and Eric Blake, with\nhelp from Ralf Wildenhues, Stepan Kasal, and Benoit Sigoure.  Many\nother people have contributed, as listed in the THANKS file.\n\nThe following contributors have warranted legal paper exchanges with\nthe Free Software Foundation for their contributions to GNU Autoconf.\nThis list results from searching for AUTOCONF in the file\n/gd/gnuorg/copyright.list on the fencepost.gnu.org machine.\n\nDavid J. MacKenzie          djm@gnu.org                         1991-07-09\nJames L. Avera              ?                                   1993-10-04\nRoland McGrath              roland@gnu.org                      1994-06-24\nNoah Friedman               friedman@gnu.org                    1994-07-15\nFrancois Pinard             pinard@iro.umontreal.ca             1997-02-02\nThomas E. Dickey            dickey@clark.net                    1998-01-11\nMatthew D. Langston         langston@slac.stanford.edu          1998-09-29\nMark Elbrecht               snowball3@usa.net                   1999-01-11\nAkim Demaille               akim@gnu.org                        1999-02-02\nPavel Roskin                pavel_roskin@geocities.com          1999-02-24\nAlexandre Oliva             oliva@dcc.unicamp.br                1999-03-26\nThomas Tanner               tanner@ffii.org                     1999-06-23\nGary V. Vaughan             gary@gnu.org                        2000-01-10\nJoseph Samuel Myers         jsm28@cam.ac.uk                     2000-03-13\nLars J. Aas                 larsa@sim.no                        2000-07-07\nMorten Eriksen              mortene@sim.no                      2000-07-07\nMartin Wilck                martin@tropos.de                    2000-07-12\nPaul Eggert                 eggert@twinsun.com                  2000-10-13\nAlexandre Duret-Lutz        duret_g@epita.fr                    2001-02-12\nTim Van Holder              tim.van.holder@pandora.be           2001-02-13\nChristian Marquardt         marq@gfz-potsdam.de                 2001-02-19\nDerek R. Price              dprice@collab.net                   2001-03-12\nMarkus Kuhn                 Markus.Kuhn@cl.cam.ac.uk            2001-07-07\nErik Lindahl                erik@theophys.kth.se                2001-08-22\nHans-Peter Nilsson          hp@bitrange.com                     2001-10-24\nPaul Wagland                paul@wagland.net                    2001-10-30\nPaolo Bonzini               bonzini@gnu.org                     2001-11-08\nNishio Futoshi              fut_nis@d3.dion.ne.jp               2002-01-23\nFederico G. Schwindt        fgsch@openbsd.org                   2002-05-21\nMark D. Roth                roth@feep.net                       2002-05-28\nGreg McGary                 greg@mcgary.org                     2002-06-05\nCharles Stephen Wilson      cwilson@ece.gatech.edu              2002-07-25\nRobert Bernstein            rocky@panix.com                     2002-08-20\nAssar Westerlund            assar@kth.se                        2002-09-13\nScott Bambrough             sbambrough@storm.ca                 2002-09-24\nRichard Dawe                rich@phekda.freeserve.co.uk         2003-01-23\nAndreas Buening             andreas.buening@nexgo.de            2003-02-18\nRaja R. Harinath            harinath@acm.org                    2003-02-25\nIlya Zakharevich            ilya@Math.Berkeley.EDU              2003-03-11\nKaveh Ghazi                 ghazi@caip.rutgers.edu              2003-03-15\nFelix Lee                   felix.1@canids.net                  2003-03-31\nNathanael Nerode            neroden@twcny.rr.com                2003-04-04\nGavin Puche                 user42@zip.com.au                   2003-04-10\nSteven Glenn Johnson        stevenj@alum.mit.edu                2003-07-26\nBernardo Innocenti          bernie@codewiz.org                  2003-07-31\nAlbert Marsden Chin-A-Young china@thewrittenword.com            2003-08-02\nRalf Corsepius              corsepiu@faw.uni-ulm.de             2003-09-03\nScott Remnant               scott@netsplit.com                  2003-10-04\nDaniel Jacobowitz           dan@debian.org                      2003-10-17\nKevin Fleming               kpfleming@backtobasicsmgmt.com      2003-11-17\nJohn David Anglin           dave.anglin@nrc-cnrc.gc.ca          2004-01-21\nEric Sunshine               sunshine@sunshineco.com             2004-01-25\nRalf Wildenhues             Ralf.Wildenhues@gmx.de              2004-02-12\nNoah Jeffrey Misch          noah@cs.caltech.edu                 2004-07-05\nThorsten Glaser             tg@66h.42h.de                       2004-10-11\nPeter O'Gorman              peter@pogma.com                     2004-11-14\nToshio Ernie Kuratomi       toshio@tiki-lounge.com              2004-11-17\nRoger Leigh                 rleigh@whinlatter.ukfsn.org         2004-12-09\nIan Lance Taylor            ian@airs.com                        2004-12-22\nDaniel Manthey              dan_manthey@partech.com             2005-02-14\nGregorio Guidi              greg_g@gentoo.org                   2005-03-03\nBruno Haible                bruno@clisp.org                     2005-06-12\nToby Oliver Hilary White    tow21@cam.ac.uk                     2005-10-18\nEric Benjamin Blake         ebb9@byu.net                        2006-01-18\nRomain Lenglet              romain.lenglet@laposte.net          2006-02-10\nMarkus Duft                 markus.duft@salomon.at              2006-08-03\nRobert Schiele              rschiele@gmail.com                  2006-09-12\nJoel Edward Denny           jdenny@clemson.edu                  2006-09-15\nHelge Deller                deller@gmx.de                       2007-02-01\nBenoit Sigoure              tsuna@lrde.epita.fr                 2007-04-20\nBob Proulx                  bob@proulx.com                      2007-06-25\nBruce Korb                  bkorb@gnu.org                       2008-05-06\nBenjamin Pfaff              blp@gnu.org                         2008-09-29\nPeter Breitenlohner         peb@mppmu.mpg.de                    2009-08-18\nStefano Lattarini           stefano.lattarini@gmail.com         2009-10-01\nReuben Thomas               rrt@sc3d.org                        2010-03-10\nPeter Rosin                 peda@lysator.liu.se                 2010-07-21\nJohn W. Eaton               jwe@gnu.org                         2010-11-05\nChristopher Hulbert         cchgroupmail@gmail.com              2010-11-09\nTim Rice                    tim@multitalents.net                2011-01-24\nKO Myun-Hun                 komh78@gmail.com                    2011-04-05\nChristian Roessel           christian.roessel@gmx.de            2011-08-26\nNicolai Stange              nicolai.stange@zmaw.de              2011-10-13\nZachary Weinberg            zackw@panix.com                     2013-06-11\n\n========================================================================\n\nLocal Variables:\nmode: text\ncoding: utf-8\nEnd:\n\nCopyright (C) 1996, 2000-2001, 2005, 2007-2017, 2020-2021 Free Software\nFoundation, Inc.\n\nThis program is free software: you can redistribute it and/or modify\nit under the terms of the GNU General Public License as published by\nthe Free Software Foundation, either version 3 of the License, or\n(at your option) any later version.\n\nThis program is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\nGNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License\nalong with this program.  If not, see <https://www.gnu.org/licenses/>.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/autoconf-2.71/COPYING",
    "content": "                    GNU GENERAL PUBLIC LICENSE\n                       Version 2, June 1991\n\n Copyright (C) 1989, 1991 Free Software Foundation, Inc. <https://fsf.org/>\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  By contrast, the GNU General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users.  This\nGeneral Public License applies to most of the Free Software\nFoundation's software and to any other program whose authors commit to\nusing it.  (Some other Free Software Foundation software is covered by\nthe GNU Lesser General Public License instead.)  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthis service if you wish), that you receive source code or can get it\nif you want it, that you can change the software or use pieces of it\nin new free programs; and that you know you can do these things.\n\n  To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have.  You must make sure that they, too, receive or can get the\nsource code.  And you must show them these terms so they know their\nrights.\n\n  We protect your rights with two steps: (1) copyright the software, and\n(2) offer you this license which gives you legal permission to copy,\ndistribute and/or modify the software.\n\n  Also, for each author's protection and ours, we want to make certain\nthat everyone understands that there is no warranty for this free\nsoftware.  If the software is modified by someone else and passed on, we\nwant its recipients to know that what they have is not the original, so\nthat any problems introduced by others will not reflect on the original\nauthors' reputations.\n\n  Finally, any free program is threatened constantly by software\npatents.  We wish to avoid the danger that redistributors of a free\nprogram will individually obtain patent licenses, in effect making the\nprogram proprietary.  To prevent this, we have made it clear that any\npatent must be licensed for everyone's free use or not licensed at all.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n                    GNU GENERAL PUBLIC LICENSE\n   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n  0. This License applies to any program or other work which contains\na notice placed by the copyright holder saying it may be distributed\nunder the terms of this General Public License.  The \"Program\", below,\nrefers to any such program or work, and a \"work based on the Program\"\nmeans either the Program or any derivative work under copyright law:\nthat is to say, a work containing the Program or a portion of it,\neither verbatim or with modifications and/or translated into another\nlanguage.  (Hereinafter, translation is included without limitation in\nthe term \"modification\".)  Each licensee is addressed as \"you\".\n\nActivities other than copying, distribution and modification are not\ncovered by this License; they are outside its scope.  The act of\nrunning the Program is not restricted, and the output from the Program\nis covered only if its contents constitute a work based on the\nProgram (independent of having been made by running the Program).\nWhether that is true depends on what the Program does.\n\n  1. You may copy and distribute verbatim copies of the Program's\nsource code as you receive it, in any medium, provided that you\nconspicuously and appropriately publish on each copy an appropriate\ncopyright notice and disclaimer of warranty; keep intact all the\nnotices that refer to this License and to the absence of any warranty;\nand give any other recipients of the Program a copy of this License\nalong with the Program.\n\nYou may charge a fee for the physical act of transferring a copy, and\nyou may at your option offer warranty protection in exchange for a fee.\n\n  2. You may modify your copy or copies of the Program or any portion\nof it, thus forming a work based on the Program, and copy and\ndistribute such modifications or work under the terms of Section 1\nabove, provided that you also meet all of these conditions:\n\n    a) You must cause the modified files to carry prominent notices\n    stating that you changed the files and the date of any change.\n\n    b) You must cause any work that you distribute or publish, that in\n    whole or in part contains or is derived from the Program or any\n    part thereof, to be licensed as a whole at no charge to all third\n    parties under the terms of this License.\n\n    c) If the modified program normally reads commands interactively\n    when run, you must cause it, when started running for such\n    interactive use in the most ordinary way, to print or display an\n    announcement including an appropriate copyright notice and a\n    notice that there is no warranty (or else, saying that you provide\n    a warranty) and that users may redistribute the program under\n    these conditions, and telling the user how to view a copy of this\n    License.  (Exception: if the Program itself is interactive but\n    does not normally print such an announcement, your work based on\n    the Program is not required to print an announcement.)\n\nThese requirements apply to the modified work as a whole.  If\nidentifiable sections of that work are not derived from the Program,\nand can be reasonably considered independent and separate works in\nthemselves, then this License, and its terms, do not apply to those\nsections when you distribute them as separate works.  But when you\ndistribute the same sections as part of a whole which is a work based\non the Program, the distribution of the whole must be on the terms of\nthis License, whose permissions for other licensees extend to the\nentire whole, and thus to each and every part regardless of who wrote it.\n\nThus, it is not the intent of this section to claim rights or contest\nyour rights to work written entirely by you; rather, the intent is to\nexercise the right to control the distribution of derivative or\ncollective works based on the Program.\n\nIn addition, mere aggregation of another work not based on the Program\nwith the Program (or with a work based on the Program) on a volume of\na storage or distribution medium does not bring the other work under\nthe scope of this License.\n\n  3. You may copy and distribute the Program (or a work based on it,\nunder Section 2) in object code or executable form under the terms of\nSections 1 and 2 above provided that you also do one of the following:\n\n    a) Accompany it with the complete corresponding machine-readable\n    source code, which must be distributed under the terms of Sections\n    1 and 2 above on a medium customarily used for software interchange; or,\n\n    b) Accompany it with a written offer, valid for at least three\n    years, to give any third party, for a charge no more than your\n    cost of physically performing source distribution, a complete\n    machine-readable copy of the corresponding source code, to be\n    distributed under the terms of Sections 1 and 2 above on a medium\n    customarily used for software interchange; or,\n\n    c) Accompany it with the information you received as to the offer\n    to distribute corresponding source code.  (This alternative is\n    allowed only for noncommercial distribution and only if you\n    received the program in object code or executable form with such\n    an offer, in accord with Subsection b above.)\n\nThe source code for a work means the preferred form of the work for\nmaking modifications to it.  For an executable work, complete source\ncode means all the source code for all modules it contains, plus any\nassociated interface definition files, plus the scripts used to\ncontrol compilation and installation of the executable.  However, as a\nspecial exception, the source code distributed need not include\nanything that is normally distributed (in either source or binary\nform) with the major components (compiler, kernel, and so on) of the\noperating system on which the executable runs, unless that component\nitself accompanies the executable.\n\nIf distribution of executable or object code is made by offering\naccess to copy from a designated place, then offering equivalent\naccess to copy the source code from the same place counts as\ndistribution of the source code, even though third parties are not\ncompelled to copy the source along with the object code.\n\n  4. You may not copy, modify, sublicense, or distribute the Program\nexcept as expressly provided under this License.  Any attempt\notherwise to copy, modify, sublicense or distribute the Program is\nvoid, and will automatically terminate your rights under this License.\nHowever, parties who have received copies, or rights, from you under\nthis License will not have their licenses terminated so long as such\nparties remain in full compliance.\n\n  5. You are not required to accept this License, since you have not\nsigned it.  However, nothing else grants you permission to modify or\ndistribute the Program or its derivative works.  These actions are\nprohibited by law if you do not accept this License.  Therefore, by\nmodifying or distributing the Program (or any work based on the\nProgram), you indicate your acceptance of this License to do so, and\nall its terms and conditions for copying, distributing or modifying\nthe Program or works based on it.\n\n  6. Each time you redistribute the Program (or any work based on the\nProgram), the recipient automatically receives a license from the\noriginal licensor to copy, distribute or modify the Program subject to\nthese terms and conditions.  You may not impose any further\nrestrictions on the recipients' exercise of the rights granted herein.\nYou are not responsible for enforcing compliance by third parties to\nthis License.\n\n  7. If, as a consequence of a court judgment or allegation of patent\ninfringement or for any other reason (not limited to patent issues),\nconditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot\ndistribute so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you\nmay not distribute the Program at all.  For example, if a patent\nlicense would not permit royalty-free redistribution of the Program by\nall those who receive copies directly or indirectly through you, then\nthe only way you could satisfy both it and this License would be to\nrefrain entirely from distribution of the Program.\n\nIf any portion of this section is held invalid or unenforceable under\nany particular circumstance, the balance of the section is intended to\napply and the section as a whole is intended to apply in other\ncircumstances.\n\nIt is not the purpose of this section to induce you to infringe any\npatents or other property right claims or to contest validity of any\nsuch claims; this section has the sole purpose of protecting the\nintegrity of the free software distribution system, which is\nimplemented by public license practices.  Many people have made\ngenerous contributions to the wide range of software distributed\nthrough that system in reliance on consistent application of that\nsystem; it is up to the author/donor to decide if he or she is willing\nto distribute software through any other system and a licensee cannot\nimpose that choice.\n\nThis section is intended to make thoroughly clear what is believed to\nbe a consequence of the rest of this License.\n\n  8. If the distribution and/or use of the Program is restricted in\ncertain countries either by patents or by copyrighted interfaces, the\noriginal copyright holder who places the Program under this License\nmay add an explicit geographical distribution limitation excluding\nthose countries, so that distribution is permitted only in or among\ncountries not thus excluded.  In such case, this License incorporates\nthe limitation as if written in the body of this License.\n\n  9. The Free Software Foundation may publish revised and/or new versions\nof the General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\nEach version is given a distinguishing version number.  If the Program\nspecifies a version number of this License which applies to it and \"any\nlater version\", you have the option of following the terms and conditions\neither of that version or of any later version published by the Free\nSoftware Foundation.  If the Program does not specify a version number of\nthis License, you may choose any version ever published by the Free Software\nFoundation.\n\n  10. If you wish to incorporate parts of the Program into other free\nprograms whose distribution conditions are different, write to the author\nto ask for permission.  For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this.  Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n                            NO WARRANTY\n\n  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\nREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\nINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\nOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\nYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\nPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGES.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software; you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation; either version 2 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License along\n    with this program; if not, write to the Free Software Foundation, Inc.,\n    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n\nAlso add information on how to contact you by electronic and paper mail.\n\nIf the program is interactive, make it output a short notice like this\nwhen it starts in an interactive mode:\n\n    Gnomovision version 69, Copyright (C) year name of author\n    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, the commands you use may\nbe called something other than `show w' and `show c'; they could even be\nmouse-clicks or menu items--whatever suits your program.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the program, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the program\n  `Gnomovision' (which makes passes at compilers) written by James Hacker.\n\n  <signature of Ty Coon>, 1 April 1989\n  Ty Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into\nproprietary programs.  If your program is a subroutine library, you may\nconsider it more useful to permit linking proprietary applications with the\nlibrary.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/autoconf-2.71/COPYING.EXCEPTION",
    "content": "                   AUTOCONF CONFIGURE SCRIPT EXCEPTION\n                       Version 3.0, 18 August 2009\n\n Copyright (C) 2009 Free Software Foundation, Inc. <https://fsf.org/>\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\nThis Exception is an additional permission under section 7 of the GNU\nGeneral Public License, version 3 (\"GPLv3\").  It applies to a given\nfile that bears a notice placed by the copyright holder of the file\nstating that the file is governed by GPLv3 along with this Exception.\n\nThe purpose of this Exception is to allow distribution of Autoconf's\ntypical output under terms of the recipient's choice (including\nproprietary).\n\n0. Definitions\n\n\"Covered Code\" is the source or object code of a version of Autoconf\nthat is a covered work under this License.\n\n\"Normally Copied Code\" for a version of Autoconf means all parts of\nits Covered Code which that version can copy from its code (i.e., not\nfrom its input file) into its minimally verbose, non-debugging and\nnon-tracing output.\n\n\"Ineligible Code\" is Covered Code that is not Normally Copied Code.\n\n1. Grant of Additional Permission.\n\nYou have permission to propagate output of Autoconf, even if such\npropagation would otherwise violate the terms of GPLv3.  However, if\nby modifying Autoconf you cause any Ineligible Code of the version you\nreceived to become Normally Copied Code of your modified version, then\nyou void this Exception for the resulting covered work.  If you convey\nthat resulting covered work, you must remove this Exception in accordance\nwith the second paragraph of Section 7 of GPLv3.\n\n2. No Weakening of Autoconf Copyleft.\n\nThe availability of this Exception does not imply any general presumption\nthat third-party software is unaffected by the copyleft requirements of\nthe license of Autoconf.\n"
  },
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    "path": "openocd-win/openocd/distro-info/licenses/autoconf-2.71/COPYINGv3",
    "content": "                    GNU GENERAL PUBLIC LICENSE\n                       Version 3, 29 June 2007\n\n Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The GNU General Public License is a free, copyleft license for\nsoftware and other kinds of works.\n\n  The licenses for most software and other practical works are designed\nto take away your freedom to share and change the works.  By contrast,\nthe GNU General Public License is intended to guarantee your freedom to\nshare and change all versions of a program--to make sure it remains free\nsoftware for all its users.  We, the Free Software Foundation, use the\nGNU General Public License for most of our software; it applies also to\nany other work released this way by its authors.  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthem if you wish), that you receive source code or can get it if you\nwant it, that you can change the software or use pieces of it in new\nfree programs, and that you know you can do these things.\n\n  To protect your rights, we need to prevent others from denying you\nthese rights or asking you to surrender the rights.  Therefore, you have\ncertain responsibilities if you distribute copies of the software, or if\nyou modify it: responsibilities to respect the freedom of others.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must pass on to the recipients the same\nfreedoms that you received.  You must make sure that they, too, receive\nor can get the source code.  And you must show them these terms so they\nknow their rights.\n\n  Developers that use the GNU GPL protect your rights with two steps:\n(1) assert copyright on the software, and (2) offer you this License\ngiving you legal permission to copy, distribute and/or modify it.\n\n  For the developers' and authors' protection, the GPL clearly explains\nthat there is no warranty for this free software.  For both users' and\nauthors' sake, the GPL requires that modified versions be marked as\nchanged, so that their problems will not be attributed erroneously to\nauthors of previous versions.\n\n  Some devices are designed to deny users access to install or run\nmodified versions of the software inside them, although the manufacturer\ncan do so.  This is fundamentally incompatible with the aim of\nprotecting users' freedom to change the software.  The systematic\npattern of such abuse occurs in the area of products for individuals to\nuse, which is precisely where it is most unacceptable.  Therefore, we\nhave designed this version of the GPL to prohibit the practice for those\nproducts.  If such problems arise substantially in other domains, we\nstand ready to extend this provision to those domains in future versions\nof the GPL, as needed to protect the freedom of users.\n\n  Finally, every program is threatened constantly by software patents.\nStates should not allow patents to restrict development and use of\nsoftware on general-purpose computers, but in those that do, we wish to\navoid the special danger that patents applied to a free program could\nmake it effectively proprietary.  To prevent this, the GPL assures that\npatents cannot be used to render the program non-free.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n                       TERMS AND CONDITIONS\n\n  0. Definitions.\n\n  \"This License\" refers to version 3 of the GNU General Public License.\n\n  \"Copyright\" also means copyright-like laws that apply to other kinds of\nworks, such as semiconductor masks.\n\n  \"The Program\" refers to any copyrightable work licensed under this\nLicense.  Each licensee is addressed as \"you\".  \"Licensees\" and\n\"recipients\" may be individuals or organizations.\n\n  To \"modify\" a work means to copy from or adapt all or part of the work\nin a fashion requiring copyright permission, other than the making of an\nexact copy.  The resulting work is called a \"modified version\" of the\nearlier work or a work \"based on\" the earlier work.\n\n  A \"covered work\" means either the unmodified Program or a work based\non the Program.\n\n  To \"propagate\" a work means to do anything with it that, without\npermission, would make you directly or secondarily liable for\ninfringement under applicable copyright law, except executing it on a\ncomputer or modifying a private copy.  Propagation includes copying,\ndistribution (with or without modification), making available to the\npublic, and in some countries other activities as well.\n\n  To \"convey\" a work means any kind of propagation that enables other\nparties to make or receive copies.  Mere interaction with a user through\na computer network, with no transfer of a copy, is not conveying.\n\n  An interactive user interface displays \"Appropriate Legal Notices\"\nto the extent that it includes a convenient and prominently visible\nfeature that (1) displays an appropriate copyright notice, and (2)\ntells the user that there is no warranty for the work (except to the\nextent that warranties are provided), that licensees may convey the\nwork under this License, and how to view a copy of this License.  If\nthe interface presents a list of user commands or options, such as a\nmenu, a prominent item in the list meets this criterion.\n\n  1. Source Code.\n\n  The \"source code\" for a work means the preferred form of the work\nfor making modifications to it.  \"Object code\" means any non-source\nform of a work.\n\n  A \"Standard Interface\" means an interface that either is an official\nstandard defined by a recognized standards body, or, in the case of\ninterfaces specified for a particular programming language, one that\nis widely used among developers working in that language.\n\n  The \"System Libraries\" of an executable work include anything, other\nthan the work as a whole, that (a) is included in the normal form of\npackaging a Major Component, but which is not part of that Major\nComponent, and (b) serves only to enable use of the work with that\nMajor Component, or to implement a Standard Interface for which an\nimplementation is available to the public in source code form.  A\n\"Major Component\", in this context, means a major essential component\n(kernel, window system, and so on) of the specific operating system\n(if any) on which the executable work runs, or a compiler used to\nproduce the work, or an object code interpreter used to run it.\n\n  The \"Corresponding Source\" for a work in object code form means all\nthe source code needed to generate, install, and (for an executable\nwork) run the object code and to modify the work, including scripts to\ncontrol those activities.  However, it does not include the work's\nSystem Libraries, or general-purpose tools or generally available free\nprograms which are used unmodified in performing those activities but\nwhich are not part of the work.  For example, Corresponding Source\nincludes interface definition files associated with source files for\nthe work, and the source code for shared libraries and dynamically\nlinked subprograms that the work is specifically designed to require,\nsuch as by intimate data communication or control flow between those\nsubprograms and other parts of the work.\n\n  The Corresponding Source need not include anything that users\ncan regenerate automatically from other parts of the Corresponding\nSource.\n\n  The Corresponding Source for a work in source code form is that\nsame work.\n\n  2. Basic Permissions.\n\n  All rights granted under this License are granted for the term of\ncopyright on the Program, and are irrevocable provided the stated\nconditions are met.  This License explicitly affirms your unlimited\npermission to run the unmodified Program.  The output from running a\ncovered work is covered by this License only if the output, given its\ncontent, constitutes a covered work.  This License acknowledges your\nrights of fair use or other equivalent, as provided by copyright law.\n\n  You may make, run and propagate covered works that you do not\nconvey, without conditions so long as your license otherwise remains\nin force.  You may convey covered works to others for the sole purpose\nof having them make modifications exclusively for you, or provide you\nwith facilities for running those works, provided that you comply with\nthe terms of this License in conveying all material for which you do\nnot control copyright.  Those thus making or running the covered works\nfor you must do so exclusively on your behalf, under your direction\nand control, on terms that prohibit them from making any copies of\nyour copyrighted material outside their relationship with you.\n\n  Conveying under any other circumstances is permitted solely under\nthe conditions stated below.  Sublicensing is not allowed; section 10\nmakes it unnecessary.\n\n  3. Protecting Users' Legal Rights From Anti-Circumvention Law.\n\n  No covered work shall be deemed part of an effective technological\nmeasure under any applicable law fulfilling obligations under article\n11 of the WIPO copyright treaty adopted on 20 December 1996, or\nsimilar laws prohibiting or restricting circumvention of such\nmeasures.\n\n  When you convey a covered work, you waive any legal power to forbid\ncircumvention of technological measures to the extent such circumvention\nis effected by exercising rights under this License with respect to\nthe covered work, and you disclaim any intention to limit operation or\nmodification of the work as a means of enforcing, against the work's\nusers, your or third parties' legal rights to forbid circumvention of\ntechnological measures.\n\n  4. Conveying Verbatim Copies.\n\n  You may convey verbatim copies of the Program's source code as you\nreceive it, in any medium, provided that you conspicuously and\nappropriately publish on each copy an appropriate copyright notice;\nkeep intact all notices stating that this License and any\nnon-permissive terms added in accord with section 7 apply to the code;\nkeep intact all notices of the absence of any warranty; and give all\nrecipients a copy of this License along with the Program.\n\n  You may charge any price or no price for each copy that you convey,\nand you may offer support or warranty protection for a fee.\n\n  5. Conveying Modified Source Versions.\n\n  You may convey a work based on the Program, or the modifications to\nproduce it from the Program, in the form of source code under the\nterms of section 4, provided that you also meet all of these conditions:\n\n    a) The work must carry prominent notices stating that you modified\n    it, and giving a relevant date.\n\n    b) The work must carry prominent notices stating that it is\n    released under this License and any conditions added under section\n    7.  This requirement modifies the requirement in section 4 to\n    \"keep intact all notices\".\n\n    c) You must license the entire work, as a whole, under this\n    License to anyone who comes into possession of a copy.  This\n    License will therefore apply, along with any applicable section 7\n    additional terms, to the whole of the work, and all its parts,\n    regardless of how they are packaged.  This License gives no\n    permission to license the work in any other way, but it does not\n    invalidate such permission if you have separately received it.\n\n    d) If the work has interactive user interfaces, each must display\n    Appropriate Legal Notices; however, if the Program has interactive\n    interfaces that do not display Appropriate Legal Notices, your\n    work need not make them do so.\n\n  A compilation of a covered work with other separate and independent\nworks, which are not by their nature extensions of the covered work,\nand which are not combined with it such as to form a larger program,\nin or on a volume of a storage or distribution medium, is called an\n\"aggregate\" if the compilation and its resulting copyright are not\nused to limit the access or legal rights of the compilation's users\nbeyond what the individual works permit.  Inclusion of a covered work\nin an aggregate does not cause this License to apply to the other\nparts of the aggregate.\n\n  6. Conveying Non-Source Forms.\n\n  You may convey a covered work in object code form under the terms\nof sections 4 and 5, provided that you also convey the\nmachine-readable Corresponding Source under the terms of this License,\nin one of these ways:\n\n    a) Convey the object code in, or embodied in, a physical product\n    (including a physical distribution medium), accompanied by the\n    Corresponding Source fixed on a durable physical medium\n    customarily used for software interchange.\n\n    b) Convey the object code in, or embodied in, a physical product\n    (including a physical distribution medium), accompanied by a\n    written offer, valid for at least three years and valid for as\n    long as you offer spare parts or customer support for that product\n    model, to give anyone who possesses the object code either (1) a\n    copy of the Corresponding Source for all the software in the\n    product that is covered by this License, on a durable physical\n    medium customarily used for software interchange, for a price no\n    more than your reasonable cost of physically performing this\n    conveying of source, or (2) access to copy the\n    Corresponding Source from a network server at no charge.\n\n    c) Convey individual copies of the object code with a copy of the\n    written offer to provide the Corresponding Source.  This\n    alternative is allowed only occasionally and noncommercially, and\n    only if you received the object code with such an offer, in accord\n    with subsection 6b.\n\n    d) Convey the object code by offering access from a designated\n    place (gratis or for a charge), and offer equivalent access to the\n    Corresponding Source in the same way through the same place at no\n    further charge.  You need not require recipients to copy the\n    Corresponding Source along with the object code.  If the place to\n    copy the object code is a network server, the Corresponding Source\n    may be on a different server (operated by you or a third party)\n    that supports equivalent copying facilities, provided you maintain\n    clear directions next to the object code saying where to find the\n    Corresponding Source.  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But this requirement does not apply\nif neither you nor any third party retains the ability to install\nmodified object code on the User Product (for example, the work has\nbeen installed in ROM).\n\n  The requirement to provide Installation Information does not include a\nrequirement to continue to provide support service, warranty, or updates\nfor a work that has been modified or installed by the recipient, or for\nthe User Product in which it has been modified or installed.  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Patents.\n\n  A \"contributor\" is a copyright holder who authorizes use under this\nLicense of the Program or a work on which the Program is based.  The\nwork thus licensed is called the contributor's \"contributor version\".\n\n  A contributor's \"essential patent claims\" are all patent claims\nowned or controlled by the contributor, whether already acquired or\nhereafter acquired, that would be infringed by some manner, permitted\nby this License, of making, using, or selling its contributor version,\nbut do not include claims that would be infringed only as a\nconsequence of further modification of the contributor version.  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To \"grant\" such a patent license to a\nparty means to make such an agreement or commitment not to enforce a\npatent against the party.\n\n  If you convey a covered work, knowingly relying on a patent license,\nand the Corresponding Source of the work is not available for anyone\nto copy, free of charge and under the terms of this License, through a\npublicly available network server or other readily accessible means,\nthen you must either (1) cause the Corresponding Source to be so\navailable, or (2) arrange to deprive yourself of the benefit of the\npatent license for this particular work, or (3) arrange, in a manner\nconsistent with the requirements of this License, to extend the patent\nlicense to downstream recipients.  \"Knowingly relying\" means you have\nactual knowledge that, but for the patent license, your conveying the\ncovered work in a country, or your recipient's use of the covered work\nin a country, would infringe one or more identifiable patents in that\ncountry that you have reason to believe are valid.\n\n  If, pursuant to or in connection with a single transaction or\narrangement, you convey, or propagate by procuring conveyance of, a\ncovered work, and grant a patent license to some of the parties\nreceiving the covered work authorizing them to use, propagate, modify\nor convey a specific copy of the covered work, then the patent license\nyou grant is automatically extended to all recipients of the covered\nwork and works based on it.\n\n  A patent license is \"discriminatory\" if it does not include within\nthe scope of its coverage, prohibits the exercise of, or is\nconditioned on the non-exercise of one or more of the rights that are\nspecifically granted under this License.  You may not convey a covered\nwork if you are a party to an arrangement with a third party that is\nin the business of distributing software, under which you make payment\nto the third party based on the extent of your activity of conveying\nthe work, and under which the third party grants, to any of the\nparties who would receive the covered work from you, a discriminatory\npatent license (a) in connection with copies of the covered work\nconveyed by you (or copies made from those copies), or (b) primarily\nfor and in connection with specific products or compilations that\ncontain the covered work, unless you entered into that arrangement,\nor that patent license was granted, prior to 28 March 2007.\n\n  Nothing in this License shall be construed as excluding or limiting\nany implied license or other defenses to infringement that may\notherwise be available to you under applicable patent law.\n\n  12. No Surrender of Others' Freedom.\n\n  If conditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot convey a\ncovered work so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you may\nnot convey it at all.  For example, if you agree to terms that obligate you\nto collect a royalty for further conveying from those to whom you convey\nthe Program, the only way you could satisfy both those terms and this\nLicense would be to refrain entirely from conveying the Program.\n\n  13. Use with the GNU Affero General Public License.\n\n  Notwithstanding any other provision of this License, you have\npermission to link or combine any covered work with a work licensed\nunder version 3 of the GNU Affero General Public License into a single\ncombined work, and to convey the resulting work.  The terms of this\nLicense will continue to apply to the part which is the covered work,\nbut the special requirements of the GNU Affero General Public License,\nsection 13, concerning interaction through a network will apply to the\ncombination as such.\n\n  14. Revised Versions of this License.\n\n  The Free Software Foundation may publish revised and/or new versions of\nthe GNU General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\n  Each version is given a distinguishing version number.  If the\nProgram specifies that a certain numbered version of the GNU General\nPublic License \"or any later version\" applies to it, you have the\noption of following the terms and conditions either of that numbered\nversion or of any later version published by the Free Software\nFoundation.  If the Program does not specify a version number of the\nGNU General Public License, you may choose any version ever published\nby the Free Software Foundation.\n\n  If the Program specifies that a proxy can decide which future\nversions of the GNU General Public License can be used, that proxy's\npublic statement of acceptance of a version permanently authorizes you\nto choose that version for the Program.\n\n  Later license versions may give you additional or different\npermissions.  However, no additional obligations are imposed on any\nauthor or copyright holder as a result of your choosing to follow a\nlater version.\n\n  15. Disclaimer of Warranty.\n\n  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY\nAPPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT\nHOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY\nOF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,\nTHE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\nPURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM\nIS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF\nALL NECESSARY SERVICING, REPAIR OR CORRECTION.\n\n  16. Limitation of Liability.\n\n  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS\nTHE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY\nGENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE\nUSE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF\nDATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD\nPARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),\nEVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF\nSUCH DAMAGES.\n\n  17. Interpretation of Sections 15 and 16.\n\n  If the disclaimer of warranty and limitation of liability provided\nabove cannot be given local legal effect according to their terms,\nreviewing courts shall apply local law that most closely approximates\nan absolute waiver of all civil liability in connection with the\nProgram, unless a warranty or assumption of liability accompanies a\ncopy of the Program in return for a fee.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nstate the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software: you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation, either version 3 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License\n    along with this program.  If not, see <https://www.gnu.org/licenses/>.\n\nAlso add information on how to contact you by electronic and paper mail.\n\n  If the program does terminal interaction, make it output a short\nnotice like this when it starts in an interactive mode:\n\n    <program>  Copyright (C) <year>  <name of author>\n    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, your program's commands\nmight be different; for a GUI interface, you would use an \"about box\".\n\n  You should also get your employer (if you work as a programmer) or school,\nif any, to sign a \"copyright disclaimer\" for the program, if necessary.\nFor more information on this, and how to apply and follow the GNU GPL, see\n<https://www.gnu.org/licenses/>.\n\n  The GNU General Public License does not permit incorporating your program\ninto proprietary programs.  If your program is a subroutine library, you\nmay consider it more useful to permit linking proprietary applications with\nthe library.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.  But first, please read\n<https://www.gnu.org/licenses/why-not-lgpl.html>.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/autoconf-2.71/NEWS",
    "content": "GNU Autoconf NEWS - User visible changes.\n\n* Noteworthy changes in release 2.71 (2021-01-28) [stable]\n\n** Bug fixes, including:\n\n*** Compilers that support C99 but not C2011 are detected correctly.\n\n*** Compatibility improved with clang and Oracle C++.\n\n*** Compatibility restored with automake's rules for regenerating configure.\n\n*** Compatibility restored with old versions of std-gnu11.m4.\n\n  Packages that wish to maintain compatibility with Autoconf 2.69 or\n  older, should update their copy of std-gnu11.m4 from Gnulib as soon\n  as practical, as the compatibility code bulks up the configure script.\n\n  Packages that require Autoconf 2.70 can drop this file entirely.\n\n* Noteworthy changes in release 2.70 (2020-12-08) [stable]\n\n** Backward incompatibilities:\n\n*** Warnings about obsolete constructs are now on by default.\n\n  These warnings can be turned off with ‘-Wno-obsolete’.\n\n  Many of these warnings advise maintainers to run autoupdate.\n  Be aware that autoupdate cannot solve all backward compatibility\n  problems, and cannot completely solve all of the problems it does\n  address.  A configure script edited by autoupdate is likely to\n  need further manual fix-ups.\n\n*** Many macros have become pickier about argument quotation.\n\n  If you get a shell syntax error from your generated configure\n  script, or seemingly impossible misbehavior (e.g. entire blocks of\n  the configure script not getting executed), check first that all\n  macro arguments are properly quoted. The “M4 Quotation” section of\n  the manual explains how to quote macro arguments properly.\n\n  It is unfortunately not possible for autoupdate to correct\n  quotation errors.\n\n*** Many macros no longer AC_REQUIRE as many other macros as they used to.\n\n  This can expose several classes of latent bugs.  These are the ones\n  we know about:\n\n   - Make sure to explicitly invoke all of the macros that set result\n     variables used later in the configure script, or in generated\n     Makefiles.\n\n   - Autoconf macros that use AC_REQUIRE are not safe to use in shell\n     control-flow constructs that appear outside of macros defined by\n     AC_DEFUN.  Use AS_IF, AS_CASE, etc. instead.  (See the\n     “Prerequisite Macros” section of the manual for details.)\n\n     The set of macros that use AC_REQUIRE internally may change from\n     release to release.  The only macros that are guaranteed *not* to\n     use AC_REQUIRE are the macros for acting on the results of a\n     test: AC_DEFINE, AC_SUBST, AC_MSG_*, AC_CACHE_CHECK, etc.\n\n   - AC_REQUIRE cannot be applied to macros that need to be used with\n     arguments.  Instead, invoke the macro normally, with its arguments.\n\n*** More macros use config.sub and config.guess internally.\n\n  As a consequence of improved support for cross compilation (see below),\n  more macros now use the auxiliary scripts ‘config.sub’ and ‘config.guess’.\n  If you use any of the affected macros, these scripts must be available\n  when your configure script is run, even if you have no intention of\n  ever cross-compiling your program.\n\n  autoreconf will issue an error if any auxiliary scripts are needed but\n  cannot be found.  (It is not currently possible to make autoconf\n  itself issue this error.)\n\n  ‘autoreconf --install’ will add ‘config.sub’, ‘config.guess’, and\n  ‘install-sh’ to your source tree if they are needed.  If you are\n  using Automake, scripts added to your tree by ‘autoreconf --install’\n  will automatically be included in the tarball produced by ‘make dist’;\n  otherwise, you will need to arrange for them to be distributed\n  yourself.\n\n  See the “Input” section of the manual for more detail, including\n  where to get the auxiliary scripts that may be needed by autoconf macros.\n\n*** Setting CC to a C++ compiler is no longer supported.\n\n  The C and C++ languages have diverged enough that we can no longer\n  guarantee that test C programs will be processed as intended by a\n  C++ compiler.  In this release, configure will proceed anyway, but\n  many test results will be incorrect.  In a future release, we may\n  make AC_PROG_CC error out if it detects that CC is a C++ compiler.\n\n  See the “Language Choice” section of the manual for instructions on\n  how to write configure scripts for C++ programs, and for programs\n  with code in more than one language.\n\n*** Running configure tests with warnings promoted to errors is not supported.\n\n  For instance, setting ‘CC=\"gcc -Werror\"’ on the configure command\n  line, or adding -Werror to CFLAGS early in the configure script when\n  the compiler recognizes this option, is very likely to cause\n  subsequent tests to fail.\n\n  This has never been guaranteed to work; the code generated by\n  AC_CHECK_FUNC, for instance, is incorrect by a strict reading of the\n  original 1989 C standard, and has been ever since that macro was\n  introduced.  Problems are more likely with newer, pickier compilers.\n\n  To enable compiler warnings and/or warnings-as-errors mode for your\n  own code, we currently recommend a dedicated Makefile variable\n  (e.g. ‘WARN_CFLAGS’) that is set by AC_SUBST when appropriate.\n  The Gnulib ‘warnings’ and ‘manywarnings’ modules can help with this.\n  We plan to add core support for probing for useful sets of compiler\n  warnings in a future release.\n\n*** Including confdefs.h manually may cause test failures.\n\n  This has never been necessary; confdefs.h is automatically included\n  at the beginning of all test programs (by AC_LANG_SOURCE).  Because\n  of the way confdefs.h is generated and used, it is not practical to\n  give it a multiple inclusion guard.  Therefore, if you include it\n  yourself, all of its definitions will be scanned twice.\n\n  Historically this has not been a problem, because confdefs.h only\n  makes macro definitions, and the C standard allows redefinitions\n  of macros as long as they’re exactly the same, but newer, pickier\n  compilers may complain anyway (see for instance GCC bug 97998).\n\n*** Older versions of automake and aclocal (< 1.8) are no longer supported.\n\n*** AC_CONFIG_SUBDIRS no longer directly supports Cygnus configure.\n\n  If you are still using an Autoconf script to drive configuration of\n  a multi-package build tree where some subdirectories use Cygnus\n  configure, copy or link $ac_aux_dir/configure into each subdirectory\n  where it is needed.  Please also contact us; we were under the\n  impression nobody used this very old tool anymore.\n\n*** AC_CHECK_HEADER and AC_CHECK_HEADERS only do a compilation test.\n\n  This completes the transition from preprocessor-based header tests\n  begun in Autoconf 2.56.\n\n  The double test that was the default since Autoconf 2.64 is no\n  longer available.  You can still request a preprocessor-only test\n  by specifying [-] as the fourth argument to either macro, but this\n  is now deprecated.  If you really need that behavior use\n  AC_PREPROC_IFELSE.\n\n*** AC_INCLUDES_DEFAULT assumes an ISO C90 compliant C implementation.\n\n  Specifically, it assumes that the ISO C90 header <stddef.h>\n  is available, without checking for it, and it does not include\n  the pre-standard header <memory.h> at all.  If the POSIX header\n  <strings.h> exists, it will be included, without first testing\n  whether both <string.h> and <strings.h> can be included in the\n  same source file.\n\n  AC_INCLUDES_DEFAULT still checks for the existence of <stdlib.h>,\n  <string.h>, and <stdio.h>, because these headers may not exist\n  in a “freestanding environment” (a compilation mode intended for OS\n  kernels and similar, where most of the features of the C library are\n  optional).  Most programs need not use ‘#ifdef HAVE_STDLIB_H’ etc in\n  their own code.\n\n  For compatibility’s sake, the C preprocessor macro STDC_HEADERS\n  will be defined when both <stdlib.h> and <string.h> are available;\n  however, <stdarg.h> and <float.h> are no longer checked for\n  (these, like <stddef.h>, are required to exist in a freestanding\n  environment).  New code should not refer to this macro.\n\n  Future releases of Autoconf may reduce the set of headers checked\n  for by AC_INCLUDES_DEFAULT.\n\n*** AS_ECHO and AS_ECHO_N unconditionally use ‘printf’.\n\n  This is substantially simpler, more reliable, and, in most cases,\n  faster than attempting to use ‘echo’ at all.  However, if ‘printf’\n  is not a shell builtin, configure scripts will run noticeably\n  slower, and if ‘printf’ is not available at all, they will crash.\n  The only systems where this is known to be a problem are extremely\n  old, and unlikely to be able to handle modern C programs for other\n  reasons (e.g. not having a C90-compliant compiler at all).\n\n*** Configure scripts require support for $( ... ) command substitution.\n\n  This POSIX shell feature is approximately the same age as\n  user-defined functions, but there do exist shells that support\n  functions and not $( ... ), such as Solaris 10 /bin/sh.\n\n  Configure scripts will automatically locate a shell that supports\n  this feature and re-execute themselves with it, if necessary, so\n  the new requirement should be transparent to most users.\n\n  In this release, most of Autoconf’s code still uses the older `...`\n  notation for command substitution.\n\n*** AC_INIT now trims extra white space from its arguments.\n\n  For instance, AC_INIT([  GNU  Hello  ], [1.0]) will set PACKAGE_NAME\n  to “GNU Hello”.\n\n*** Macros that take whitespace-separated lists as arguments\n    now always expand macros within those arguments.\n\n  Formerly, these macros would *usually* expand those arguments, but\n  the behavior was not reliable nor was it consistent between autoconf\n  and autoheader.\n\n  Macro expansion within these arguments is deprecated; if expansion\n  changes the list, a warning in the “obsolete” category will be\n  emitted.  Note that ‘dnl’ is a macro.  Putting ‘dnl’ comments inside\n  any argument to an Autoconf macro is, in general, only supported\n  when that argument takes more Autoconf code (e.g. the ACTION-IF-TRUE\n  argument to AC_COMPILE_IFELSE).\n\n  The affected macros are AC_CHECK_FILES, AC_CHECK_FUNCS,\n  AC_CHECK_FUNCS_ONCE, AC_CHECK_HEADERS, AC_CHECK_HEADERS_ONCE,\n  AC_CONFIG_MACRO_DIRS, AC_CONFIG_SUBDIRS, and AC_REPLACE_FUNCS.\n\n*** AC_FUNC_VFORK no longer ignores a signal-handling bug in Solaris 2.4.\n\n  This bug was being ignored because Emacs wanted to use ‘vfork’ on\n  Solaris 2.4 anyway, but current versions of Emacs have dropped\n  support for Solaris 2.4.  Most programs will want to avoid ‘vfork’\n  on this OS because of this bug.\n\n*** AC_FUNC_STRERROR_R assumes strerror_r is unavailable if it’s not declared.\n\n  The fallback technique it used to probe strerror_r’s return type\n  when the function was present in the C library, but not declared by\n  <string.h>, was fragile and did not work at all when cross-compiling.\n  The systems where this fallback was necessary were all obsolete.\n\n  Programs that use AC_FUNC_STRERROR_R should make sure to test the\n  preprocessor macro HAVE_DECL_STRERROR_R before using strerror_r at all.\n\n*** AC_OPENMP can’t be used if you have files named ‘mp’ or ‘penmp’.\n\n  Autoconf will now issue an error if AC_OPENMP is used in a configure\n  script that’s in the same directory as a file named ‘mp’ or ‘penmp’.\n  Configure scripts that use AC_OPENMP will now error out upon\n  encountering files with these names in their working directory\n  (e.g. when the build directory is separate from the source directory).\n\n  If you have files with these names at the top level of your source\n  tree, we recommend either renaming them or moving them into a\n  subdirectory.  See the documentation of AC_OPENMP for further\n  explanation.\n\n** New features\n\n*** Configure scripts now support a ‘--runstatedir’ option.\n\n  This defaults to ‘${localstatedir}/run’.  It can be used, for\n  instance, to place per-process temporary runtime files (such as pid\n  files) into ‘/run’ instead of ‘/var/run’.\n\n*** autoreconf will now run gtkdocize and intltoolize when appropriate.\n\n*** autoreconf now recognizes AM_GNU_GETTEXT_REQUIRE_VERSION.\n\n  This macro can be used with gettext 0.19.6 or later to specify\n  a *minimum* version requirement for gettext, instead of the *fixed*\n  version requirement specified by AM_GNU_GETTEXT_VERSION.\n\n*** autoheader handles secondary config headers better.\n\n  It is no longer necessary to duplicate AC_DEFINE templates in the\n  main configuration header for autoheader to notice them.\n\n*** AC_PROG_CC now enables C2011 mode if the compiler supports it.\n\n  If not, it will fall back to C99 and C89, as before.  Similarly,\n  AC_PROG_CXX now enables C++2011 if available, falling back on C++98.\n\n*** New macro AC_C__GENERIC tests for C2011 _Generic support.\n\n*** AC_C_VARARRAYS has been aligned with C2011.\n\n  It now defines __STDC_NO_VLA__ if variable-length arrays are not\n  supported but the compiler does not define __STDC_NO_VLA__.\n\n  For backward compatibility with Autoconf 2.61-2.69 AC_C_VARARRAYS\n  still defines HAVE_C_VARARRAYS, but this result macro is obsolescent.\n\n*** New macro AC_CONFIG_MACRO_DIRS.\n\n  This macro can be used more than once and accepts a list of\n  directories to search for local M4 macros.  With Automake 1.13 and\n  later, use of this macro eliminates a reason to use ACLOCAL_AMFLAGS\n  in Makefile.am.\n\n  The older AC_CONFIG_MACRO_DIR, which could only be used once, is\n  still supported but considered deprecated.\n\n*** AC_USE_SYSTEM_EXTENSIONS knows about more extensions to enable.\n\n  System extensions will now be enabled on HP-UX, macOS, and MINIX.\n  Optional ISO C library components (e.g. decimal floating point) will\n  also be enabled.\n\n*** New compatibility macro AC_CHECK_INCLUDES_DEFAULT.\n\n  This macro runs the checks normally performed as a side-effect by\n  AC_INCLUDES_DEFAULT, if they haven’t already been done.  Autoupdate\n  will replace certain obsolete constructs, whose only remaining\n  useful effect is to trigger those checks, with this macro.  It is\n  unlikely to be useful otherwise.\n\n*** AC_REQUIRE_AUX_FILE has been improved.\n\n  Configure scripts now check, on startup, for the availability of all\n  the aux files that were mentioned in an AC_REQUIRE_AUX_FILE\n  invocation.  This should help prevent certain classes of packaging\n  errors.\n\n  Also, it is no longer necessary for third-party macros that use\n  AC_REQUIRE_AUX_FILE to mention AC_CONFIG_AUX_DIR_DEFAULT.  However,\n  if you are using AC_CONFIG_AUX_DIR_DEFAULT *without* also using\n  AC_REQUIRE_AUX_FILE, please start using AC_REQUIRE_AUX_FILE to\n  specify the aux files you actually need, so that the check can be\n  effective.\n\n*** AC_PROG_LEX has an option to not look for yywrap.\n\n  AC_PROG_LEX now takes one argument, which may be either ‘yywrap’ or\n  ‘noyywrap’.  If it is ‘noyywrap’, AC_PROG_LEX will only set LEXLIB\n  to ‘-lfl’ or ‘-ll’ if a scanner that defines both main and yywrap\n  itself still needs something else from that library.  On the other\n  hand, if it is ‘yywrap’, AC_PROG_LEX will fail (setting LEX to ‘:’\n  and LEXLIB to nothing) if it can’t find a library that defines yywrap.\n\n  In the absence of arguments, AC_PROG_LEX’s behavior is bug-compatible\n  with 2.69, which did neither of the above things (see the manual for\n  details).  This mode is deprecated.\n\n  We encourage all programs that use AC_PROG_LEX to use the new\n  ‘noyywrap’ mode, and to define yywrap themselves, or use %noyywrap.\n  The yywrap function in lib(f)l is trivial, and self-contained\n  scanners are easier to work with.\n\n** Obsolete features and new warnings\n\n*** Use of the long-deprecated name ‘configure.in’ for the autoconf\n    input file now elicits a warning in the “obsolete” category.\n\n*** Use of the undocumented internal shell variables $as_echo and\n    $as_echo_n now elicits a warning in the “obsolete” category.\n    The macros AS_ECHO and AS_ECHO_N should be used instead.\n\n*** autoconf will now issue warnings (in the “syntax” category)\n    if the input file is missing a call to AC_INIT and/or AC_OUTPUT.\n\n*** autoconf will now issue warnings (in the “syntax” category)\n    for a non-literal URL argument to AC_INIT, and for a TARNAME\n    argument to AC_INIT which is either non-literal or contains\n    characters that should not be used in file names (e.g. ‘*’).\n\n*** AC_PROG_CC_STDC, AC_PROG_CC_C89, AC_PROG_CC_C99 are now obsolete.\n\n  Applications should use AC_PROG_CC.\n\n*** AC_HEADER_STDC and AC_HEADER_TIME are now stubs.\n\n  They still define the C preprocessor macros STDC_HEADERS and\n  TIME_WITH_SYS_TIME, respectively, but they no longer check for the\n  ancient, non-ISO-C90 compliant systems where formerly those macros\n  would not be defined.  Autoupdate will remove them.\n\n  These macros were already labeled obsolete in the manual.\n\n*** AC_DIAGNOSE, AC_FATAL, AC_WARNING, and _AC_COMPUTE_INT are now\n    replaced with modern equivalents by autoupdate.\n\n  These macros were already labeled obsolete in the manual.\n\n*** AC_CONFIG_HEADER is now diagnosed as obsolete, and replaced with\n    AC_CONFIG_HEADERS by autoupdate.\n\n  This macro has been considered obsolete for many years and was not\n  documented at all.\n\n*** The macro AC_OBSOLETE is obsolete.\n\n  Autoupdate will replace it with m4_warn([obsolete], [explanation]).\n  If possible, macros using AC_OBSOLETE should be converted to use\n  AU_DEFUN or AU_ALIAS instead, which enables autoupdate to replace\n  them, but this has to be done by hand and is not always possible.\n\n  This macro has been considered obsolete for many years, but was not\n  officially declared as such.\n\n*** Man pages for config.guess and config.sub are no longer provided.\n\n  They were moved to the master source tree for config.guess and\n  config.sub.\n\n** Notable bug fixes\n\n*** Compatible with current Automake, Libtool, Perl, Texinfo, and shells.\n\n  All of autoconf’s tools and generated scripts, and the build process\n  and testsuite for autoconf itself, have been tested to work\n  correctly with current versions of Automake, Libtool, Perl, Texinfo,\n  bash, ksh93, zsh, and FreeBSD and NetBSD /bin/sh.\n\n  Generated configure scripts are expected to work reliably with an\n  even wider variety of shells, including BusyBox sh and various\n  proprietary Unixes’ /bin/sh, as long as they are minimally compliant\n  with the Unix95 shell specification.  Notably, support for\n  shell-script functions and the ‘printf’ builtin are required.\n\n*** Checks compatible with current language standards and compilers.\n\n  Many individual macros have been improved to accommodate changes in\n  recent versions of the C and C++ language standards, and new\n  features and quirks of commonly used compilers (both free and\n  proprietary).\n\n*** Improved support for cross compilation.\n\n  Many individual macros have been improved to produce more accurate\n  results when cross-compiling.\n\n*** Improved robustness against unusual build environments.\n\n  Many bugs have been fixed where generated configure scripts would\n  fail catastrophically under unusual conditions, such as stdout being\n  closed, or $TMPDIR not being an absolute path, or the root directory\n  being mentioned in $PATH.\n\n*** AC_CHECK_FUNCS_ONCE and AC_CHECK_HEADERS_ONCE now support multiple\n    programming languages.  They no longer perform all checks in the\n    language active upon the first use of the macro.\n\n*** AC_CHECK_DECL and AC_CHECK_DECLS will now detect missing declarations for\n    library functions that are also Clang compiler builtins.\n\n*** AC_PATH_X and AC_PATH_XTRA don’t search for X11 when cross-compiling.\n\n  Libraries and headers found by running xmkmf or searching /usr/X11,\n  /usr/X11R7, etc. are likely to belong to a native X11 installation\n  for the build machine and to be inappropriate for cross compilation.\n\n  To cross-compile programs that require X11, we recommend putting the\n  headers and libraries for the host system in your cross-compiler’s\n  default search paths.  Alternatively, use configure’s --x-includes\n  and --x-libraries command line options to tell it where they are.\n\n*** AS_IF’s if-false argument may be empty after macro expansion.\n\n  This long-standing limitation broke configure scripts that used\n  macros in this position that emitted shell code in 2.69 but no\n  longer do, so we have lifted it.\n\n*** AC_HEADER_MAJOR detects the location of the major, minor, and\n    makedev macros correctly under glibc 2.25 and later.\n\n*** AC_FC_LINE_LENGTH now documents the maximum portable length of\n    “unlimited” Fortran source code lines to be 250 columns, not 254.\n\n*** AC_INIT and AS_INIT no longer embed (part of) the path to the\n    source directory in generated files.\n\n  We believe this was the only case where generated file contents\n  could change depending on the environment outside the source tree\n  itself.  If you find any other cases please report them as bugs.\n\n*** config.log properly escapes arguments in the header comment.\n\n*** config.status --config output is now quoted in a more readable fashion.\n\n** Autotest enhancements\n\n*** Autotest provides a new macro AT_DATA_UNQUOTED, similar to AT_DATA\n    but processing variable substitutions, command substitutions and\n    backslashes in the contents argument.\n\n*** AC_CONFIG_TESTDIR will automatically pass EXEEXT to a testsuite (via\n    the atconfig file).\n\n*** AT_TESTED arguments can use variable or command substitutions, including\n    in particular $EXEEXT\n\n*** New macros AT_PREPARE_TESTS, AT_PREPARE_EACH_TEST, and AT_TEST_HELPER_FN.\n\n   These provide an official way to define testsuite-specific\n   initialization code and shell functions.\n\n* Noteworthy changes in release 2.69 (2012-04-24) [stable]\n\n** Autoconf now requires perl 5.6 or better (but generated configure\n   scripts continue to run without perl).\n\n* Noteworthy changes in release 2.68b (2012-03-01) [beta]\n  Released by Eric Blake, based on git versions 2.68.*.\n\n** Autoconf-generated configure scripts now unconditionally re-execute\n   themselves with $CONFIG_SHELL, if that's set in the environment.\n\n** The texinfo documentation no longer specifies \"front-cover\" or\n   \"back-cover\" texts, so that it may now be included in Debian's\n   \"main\" section.\n\n** Support for the Go programming language has been added.  The new macro\n   AC_LANG_GO sets variables GOC and GOFLAGS.\n\n** AS_LITERAL_IF again treats '=' as a literal.  Regression introduced in\n   2.66.\n\n** The macro AS_EXECUTABLE_P, present since 2.50, is now documented.\n\n** Macros\n\n- AC_PROG_LN_S and AS_LN_S now fall back on 'cp -pR' (not 'cp -p') if 'ln -s'\n  does not work.  This works better for symlinks to directories.\n\n- New macro AC_HEADER_CHECK_STDBOOL.\n\n- New and updated macros for Fortran support:\n\n    AC_FC_CHECK_BOUNDS to enable array bounds checking\n    AC_F77_IMPLICIT_NONE and AC_FC_IMPLICIT_NONE to disable implicit integer\n    AC_FC_MODULE_EXTENSION to compute the Fortran 90 module name extension\n    AC_FC_MODULE_FLAG for the Fortran 90 module search path flag\n    AC_FC_MODULE_OUTPUT_FLAG for the Fortran 90 module output directory flag\n    AC_FC_PP_SRCEXT for preprocessed Fortran source files extensions\n    AC_FC_PP_DEFINE for the Fortran preprocessor define flag\n\n* Noteworthy changes in release 2.68 (2010-09-22) [stable]\n  Released by Eric Blake, based on git versions 2.67.*.\n\n** AC_MSG_ERROR (and AS_ERROR) can once again be followed immediately by\n   `dnl'.  Regression introduced in 2.66.\n\n** AC_INIT again allows URLs with '?' for its BUG-REPORT argument.\n   Regression introduced in 2.66.\n\n** AC_REPLACE_FUNCS again allows a non-literal argument, such as a shell\n   variable that expands to a list of functions to check.  Regression\n   introduced in 2.66.\n\n** AT_BANNER() with empty argument will cause visual separation from previous\n   test category.\n\n** The macros AC_PREPROC_IFELSE, AC_COMPILE_IFELSE, AC_LINK_IFELSE, and\n   AC_RUN_IFELSE now warn if the first argument failed to use\n   AC_LANG_SOURCE or AC_LANG_PROGRAM to generate the conftest file\n   contents.  A new macro AC_LANG_DEFINES_PROVIDED exists if you have\n   a compelling reason why you cannot use AC_LANG_SOURCE but must\n   avoid the warning.\n\n** The macro m4_define_default is now documented.\n\n** Symlinked config.cache files are supported; configure now tries to\n   update non-symlinked cache files atomically, so that concurrent configure\n   runs do not leave behind broken cache files.  It is still unspecified\n   which subset or union of results is cached though.\n\n** Autotest testsuites should not contain long text lines any more, and be\n   portable even when very many test groups are used.\n\n** AT_CHECK semantics with respect to the Autotest variable $at_status and\n   shell execution environment of the arguments are documented now.\n\n** AC_FC_LIBRARY_LDFLAGS now tolerates output from newer gfortran.\n\n** Newly obsolete macros\n   The following macros have been marked obsolete.  New programs\n   should use the corresponding Gnulib modules.  Gnulib not only\n   detects a larger set of portability problems with these functions,\n   but also provides complete workarounds.\n\n     AC_FUNC_ERROR_AT_LINE  AC_FUNC_LSTAT_FOLLOWS_SLASHED_SYMLINK\n     AC_FUNC_MKTIME  AC_FUNC_STRTOD\n\n\n* Major changes in Autoconf 2.67 (2010-07-21) [stable]\n  Released by Eric Blake, based on git versions 2.66.*.\n\n** AC_CONFIG_SUBDIRS with more than one subdirectory at a time works again.\n   Regression introduced in 2.66.\n\n** AC_CHECK_SIZEOF of a pointer type works again.  Regression introduced in\n   2.66.\n\n** New macro AC_FC_LINE_LENGTH to accept long Fortran source code lines.\n\n** AC_PREPROC_IFELSE now keeps the preprocessed output in the conftest.i\n   file for inspection by the commands in the ACTION-IF-TRUE argument.\n\n** AC_INIT again allows parentheses and other characters that are literal\n   in single- or double-quoted strings, and in quoted and unquoted\n   here-documents, for its PACKAGE and VERSION arguments.  Regression\n   introduced in 2.66.\n\n** autoreconf passes warning flags to new enough versions of aclocal.\n\n** Running an Autotest testsuite in parallel mode no longer triggers a\n   race condition that could cause the testsuite run to end early,\n   fixing a sporadic failure in autoconf's own testsuite.  Bug present\n   since introduction of parallel tests in 2.63b.\n\n\n* Major changes in Autoconf 2.66 (2010-07-02) [stable]\n  Released by Eric Blake, based on git versions 2.65.*.\n\n** AC_FUNC_MMAP works in C++ mode again.  Regression introduced in 2.65.\n\n** Use of m4_divert without a named diversion now issues a syntax warning,\n   since it is seldom right to change diversions behind autoconf's back.\n\n** The macros AC_TYPE_INT8_T, AC_TYPE_INT16_T, AC_TYPE_INT32_T, and\n   AC_TYPE_INT64_T work again.  Regression introduced in 2.65.\n\n** AC_PROG_INSTALL correctly uses `shtool' again.  Regression introduced\n   in 2.64.\n\n** Autoconf should work on EBCDIC hosts.\n\n** AC_CHECK_DECL and AC_CHECK_DECLS accept optional function argument types\n   for overloaded C++ functions.\n\n** AS_SET_CATFILE accepts nonliterals in its variable name argument now.\n\n** Autotest testsuites accept an option --recheck to rerun tests that\n   failed or passed unexpectedly during the last non-debug testsuite run.\n\n** AC_ARG_ENABLE and AC_ARG_WITH now also accept `+' signs in `--enable-*'\n   and `--with-*' arguments, converting them to underscores for the variable\n   names.\n\n** In configure scripts, loading CONFIG_SITE no longer searches PATH,\n   and problems in loading the configuration site files are diagnosed.\n\n** Autotest testsuites may optionally provide colored test results.\n\n** The previously undocumented Autotest macros AT_ARG_OPTION and\n   AT_ARG_OPTION_ARG have seen bug fixes and are documented now.\n   AT_ARG_OPTION has been changed in that the negative of a long option\n   --OPTION is now --no-OPTION rather than --noOPTION.\n\n** The macro AS_LITERAL_IF is slightly more conservative; text\n   containing shell quotes are no longer treated as literals.\n   Furthermore, a new macro, AS_LITERAL_WORD_IF, adds an additional\n   level of checking that no whitespace occurs in literals.\n\n** The macros AS_TR_SH and AS_TR_CPP no longer expand their results.\n\n** The following macros are now documented:\n   AS_BOX\n\n** New macro AC_FC_FIXEDFORM to accept fixed-form Fortran.\n\n\n* Major changes in Autoconf 2.65 (2009-11-21) [stable]\n  Released by Eric Blake, based on git versions 2.64.*.\n\n** Autoconf is now licensed under the General Public License version 3\n   or later (GPLv3+).  As with earlier versions, the license includes\n   an exception clause so that you may release a configure script\n   generated by autoconf under the license of your own program.\n\n** New macros to support Objective C++.\n   AC_PROG_OBJCXX  AC_PROG_OBJCXXCPP\n\n** The following undocumented autoconf macros, removed in Autoconf 2.64,\n   have been reinstated:\n   AH_CHECK_HEADERS\n\n   These macros are present only for backwards compatibility purposes.\n\n** The macro AC_LANG_COMPILER no longer fails on embedded systems that\n   lack fopen in the C library, such as AVR or RTEMS (regression\n   introduced in 2.64).\n\n** The AC_FC_FREEFORM macro no longer suffers from a whitespace bug that\n   made it fail with some Fortran compilers (regression introduced in\n   2.64).\n\n** The AC_TYPE_UINT64_T and AC_TYPE_INT64_T macros have been fixed to no\n   longer mistakenly select a 32-bit type on some compilers (bug present\n   since macros were introduced in 2.59c).\n\n** The AC_FUNC_MMAP macro has been fixed to be portable to systems like\n   Cygwin (bug present since macro was introduced in 2.0).\n\n** The following documented autotest macros are new:\n   AT_CHECK_EUNIT\n\n** The following m4sugar macros now quote their expansion:\n   m4_toupper  m4_tolower\n\n** The following m4sugar macros are new:\n   m4_escape\n\n** The m4sugar macro m4_text_wrap now copes with embedded quoting without\n   requiring quadrigraphs.  For uses like AC_ARG_VAR([a], [[b c]]),\n   this gives the intuitive behavior of \"[b c]\" in the output (2.63\n   gave the output of \"[b], [c]\", and 2.64 encountered a failure).\n\n** The `$tmp' temporary directory used in config.status is documented for\n   public use now.\n\n** config.status now provides a --config option to produce the configuration.\n\n** Many cache variables used by Autoconf's macros are now documented.\n\n** Configure scripts work better on DJGPP by avoiding a bug present in\n   the DJGPP port of bash 2.04 in handling 'return' in a shell\n   function (regression introduced in 2.64).\n\n* Major changes in Autoconf 2.64 (2009-07-26) [stable]\n  Released by Eric Blake, based on git versions 2.63b.*.\n\n** Autoconf now requires GNU M4 1.4.6 or later.  Earlier versions of M4\n   have a bug in regular expression handling that interferes with some\n   of the speedups provided since Autoconf 2.63.  GNU M4 1.4.13 or\n   later is recommended.\n\n** AS_IF and AS_CASE have been taught to avoid syntax errors even when\n   given arguments that expand to just whitespace.\n\n** The following documented autoconf macros are new:\n   AC_ERLANG_SUBST_ERTS_VER\n\n** The autoheader tool now understands m4 macro arguments passed to\n   AC_DEFINE and AC_DEFINE_UNQUOTED.\n\n** Ensure AT_CHECK can support commands that include a # given with\n   proper m4 quoting.  For shell comments, this is a new feature; for\n   non-shell comments, this fixes a regression introduced in 2.63b.\n   Additionally, AT_CHECK correctly supplies shell escapes for\n   metacharacters occurring in m4 macro expansions within the expected\n   stdout and stderr parameters.\n\n** The macro AT_CHECK now understands the concept of hard failure.  If\n   a test exits with an unexpected status 99, cleanup actions for the\n   test are inhibited and the test is treated as a failure regardless\n   of AT_XFAIL_IF.  It also understands the new directives\n   ignore-nolog, stdout-nolog, and stderr-nolog.\n\n** The following documented autotest macros are new:\n   AT_CHECK_UNQUOTED  AT_FAIL_IF  AT_SKIP_IF\n\n** The following documented m4sugar macros are new:\n   m4_argn  m4_copy_force  m4_default_nblank  m4_default_nblank_quoted\n   m4_ifblank  m4_ifnblank  m4_rename_force\n\n** The autoconf testsuite now exercises all Erlang macros.\n\n* Major changes in Autoconf 2.63b (2009-03-31) [beta]\n  Released by Eric Blake, based on git versions 2.63.*.\n\n** The manual is now shipped under the terms of the GNU FDL 1.3.\n\n** AC_REQUIRE now detects the case of an outer macro which first expands\n   then later indirectly requires the same inner macro.  Previously,\n   this case led to silent out-of-order expansion (bug present since\n   2.50); it now issues a syntax warning, and duplicates the expansion\n   of the inner macro to guarantee dependencies have been met.  See\n   the manual for advice on how to refactor macros in order to avoid\n   the bug in earlier autoconf versions and avoid increased script\n   size in the current version.\n\n** AC_DEFUN_ONCE has improved semantics.  Previously, a macro declared\n   with AC_DEFUN_ONCE warned on a second invocation; and out-of-order\n   expansion was still possible.  Now, dependencies are guaranteed,\n   and subsequent invocations are a silent no-op.  This makes\n   AC_DEFUN_ONCE an ideal macro for silencing AC_REQUIRE warnings.\n\n** The following macros are now defined with AC_DEFUN_ONCE.  This means\n   a subtle change in semantics; previously, an AC_DEFUN macro could\n   expand one of these macros multiple times or surround the macro\n   inside shell conditional text to bypass the effects of these\n   macros, but now the macro will expand exactly once, and prior to\n   the start of any enclosing AC_DEFUN macro:\n   AC_CANONICAL_BUILD  AC_CANONICAL_HOST  AC_CANONICAL_TARGET\n   AC_HEADER_ASSERT  AC_PROG_INSTALL  AC_PROG_MKDIR_P\n   AC_USE_SYSTEM_EXTENSIONS\n\n** AC_LANG_ERLANG works once again (regression introduced in 2.61a).\n\n** AC_HEADER_ASSERT is fixed so that './configure --enable-assert' no\n   longer mistakenly disables assertions.\n\n** AC_INIT now takes an optional fifth parameter that can be used to\n   set AC_PACKAGE_URL, a URL for the package's home page; the URL is\n   used in `configure --help' and is also available via AC_DEFINE.\n\n** Autotest testsuites accept an option --jobs[=N] for parallel testing.\n   This feature is still in testing, and may not work on every\n   platform, help in improving it would be appreciated.\n\n** Autotest testsuites do not attempt to write startup error messages\n   to the log file before that is opened (regression introduced in 2.63).\n\n** Configure scripts now use shell functions.  This feature leads to\n   smaller configure files and faster execution.\n\n** Present But Cannot Be Compiled: Autoconf will now proceed with\n   the compiler's result if a header is present but cannot be compiled.\n   The warning is still printed, and you should really fix it by\n   providing a fourth parameter to AC_CHECK_HEADER/AC_CHECK_HEADERS.\n\n** Autoreconf added aclocal to the set of programs affected by the\n   `autoreconf -I dir' option.\n\n** The following documented m4sugar macros are new:\n   m4_chomp  m4_chomp_all  m4_cleardivert  m4_curry  m4_default_quoted\n   m4_esyscmd_s  m4_map_args  m4_map_args_pair  m4_map_args_sep\n   m4_map_args_w  m4_set_map  m4_set_map_sep  m4_stack_foreach\n   m4_stack_foreach_lifo  m4_stack_foreach_sep\n   m4_stack_foreach_sep_lifo\n\n** The following m4sugar macros are documented now, but in some cases\n   with slightly different semantics than what the previous\n   undocumented version had:\n   m4_copy  m4_dumpdefs  m4_rename  m4_version_prereq\n\n** The m4sugar macro m4_expand has been taught to handle unterminated\n   comments and shell case statements.  As a result, it is used\n   internally in more places, such as AC_DEFINE and AT_CHECK.  Most\n   uses of AC_DEFINE and AT_CHECK should not behave any differently;\n   however, it may be necessary to add double-quoting around\n   unbalanced `(' where single-quoting used to be sufficient.\n\n** The following documented m4sh macros are new:\n   AS_INIT_GENERATED  AS_LINENO_PREPARE  AS_ME_PREPARE  AS_SET_STATUS\n   AS_VAR_APPEND  AS_VAR_ARITH  AS_VAR_COPY\n\n** The following m4sh macros are documented now, but in some cases\n   with slightly different semantics than what the previous\n   undocumented version had:\n   AS_ECHO  AS_ECHO_N  AS_ESCAPE  AS_EXIT  AS_LITERAL_IF  AS_UNSET\n   AS_VAR_IF  AS_VAR_POPDEF  AS_VAR_PUSHDEF  AS_VAR_SET  AS_VAR_SET_IF\n   AS_VAR_TEST_SET  AS_VERSION_COMPARE\n\n** The m4sh macros AS_IF and AS_CASE can now be used in shell lists.\n   The responsibility for supplying a trailing newline now belongs to\n   the call site, but since most users did not add dnl, this generally\n   results in fewer empty lines in configure.\n\n\f\n* Major changes in Autoconf 2.63 (2008-09-09) [stable]\n  Released by Eric Blake, based on git versions 2.62.*.\n\n** AC_C_BIGENDIAN does not mistakenly report \"universal\" for some\n   bigendian hosts, a regression introduced with universal binary\n   support in 2.62.\n\n** AC_PATH_X now includes /lib64 and /usr/lib64 in its list of default\n   library directories.\n\n** AC_USE_SYSTEM_EXTENSIONS no longer conflicts with an external\n   AC_DEFINE([__EXTENSIONS__]).  This fixes a regression introduced in\n   2.62 when using macros such as AC_AIX that were made obsolete in\n   favor of the more portable AC_USE_SYSTEM_EXTENSIONS.\n\n** AC_CHECK_TARGET_TOOLS is usable in the non-cross-compile case.\n\n** Newly obsolete macros\n   The following macro has been marked obsolete, since current porting\n   targets can safely assume C89 semantics that signal handlers return\n   void.  We have no current plans to remove the macro.\n\n     AC_TYPE_SIGNAL\n\n** The macros m4_map and m4_map_sep now ignore any list elements\n   consisting of just empty quotes, and m4_map_sep now expands its\n   separator.  This fixes a regression in 2.62 when these macros were\n   first documented, for the sake of clients expecting the semantics\n   that these macros had prior to that time.  The new macros m4_mapall\n   and m4_mapall_sep, along with extra quoting of the separator, can\n   be used to get the semantics that m4_map_sep had in 2.62.\n\n** Clients of m4_expand, such as AS_HELP_STRING and AT_SETUP, can now\n   handle properly quoted but otherwise unbalanced parentheses (for\n   some macros, this fixes a regression in 2.62).\n\n** Two new quadrigraphs have been introduced: @{:@ for (, and @:}@ for ),\n   allowing the output of unbalanced parentheses in more contexts.\n\n** The following m4sugar macros are new:\n   m4_cleardivert  m4_joinall  m4_mapall  m4_mapall_sep  m4_reverse\n   m4_set_add  m4_set_add_all  m4_set_contains  m4_set_contents\n   m4_set_delete  m4_set_difference  m4_set_dump  m4_set_empty\n   m4_set_foreach  m4_set_intersection  m4_set_list  m4_set_listc\n   m4_set_remove  m4_set_size  m4_set_union\n\n** The following m4sugar macros now accept multiple arguments, as is the\n   case with underlying m4:\n   m4_defn  m4_popdef  m4_undefine\n\n** The following m4sugar macros now guarantee linear scaling; they\n   previously had linear scaling with m4 1.6 but quadratic scaling\n   when using m4 1.4.x.  All macros built on top of these also gain\n   the scaling improvements.\n   m4_bmatch  m4_bpatsubsts  m4_case  m4_cond  m4_do  m4_dquote_elt\n   m4_foreach  m4_join  m4_list_cmp  m4_map  m4_map_sep  m4_max\n   m4_min  m4_shiftn\n\n** AT_KEYWORDS once again performs expansion on its argument, such that\n   AT_KEYWORDS([m4_if([$1], [], [default])]) no longer complains about\n   the possibly unexpanded m4_if [regression introduced in 2.62].\n\n** Config header templates `#undef UNDEFINED /* comment */' do not lead to\n   nested comments any more; regression introduced in 2.62.\n\n\f\n* Major changes in Autoconf 2.62 (2008-04-05) [stable]\n  Released by Eric Blake, based on git versions 2.61a.*.\n\n** Many optimizations have been applied to make overall execution faster.\n\n** Autotest now makes use of shell functions.\n\n** config.status now uses awk instead of sed also for config headers.\n\n   - As a side effect, AC_DEFINE and AC_DEFINE_UNQUOTED now handle multi-line\n     values, i.e., backslash-newline combinations are handled correctly.\n     Further, for config headers, the total size of values is not limited by\n     the POSIX length limit of text lines any more, only each single line.\n\n** New config variable `top_build_prefix'.\n\n** New Autoconf macros:\n   AC_AUTOCONF_VERSION  AC_OPENMP  AC_PATH_PROGS_FEATURE_CHECK\n\n** AC_C_BIGENDIAN now supports universal binaries a la Mac OS X.\n\n** AC_C_RESTRICT now prefers to #define 'restrict' to a variant spelling\n   like '__restrict' if the variant spelling is available, as this is\n   more likely to work when mixing C and C++ code.\n\n** AC_CHECK_ALIGNOF's type argument T is now documented better: it must\n   be a string of tokens such that \"T y;\" is a valid member declaration\n   in a struct.\n\n** AC_CHECK_SIZEOF now accepts objects as well as types: the general rule\n   is that sizeof (X) works, then AC_CHECK_SIZEOF (X) should work.\n\n** AC_CHECK_TYPE and AC_CHECK_TYPES now work on any C type-name; formerly,\n   they did not work for function types.  In C++, they now work on any\n   type-id that can be the operand of sizeof; this is similar to C,\n   except it excludes anonymous struct and union types.  Formerly,\n   some (but not all) C++ types involving anonymous struct and union\n   were accepted, though this was not documented.\n\n** AC_CONFIG_LINKS now prefers to link against files in the build tree\n   if found, and it works to link against a file of the same name in\n   the source tree, even if both trees coincide.\n\n** AC_INIT no longer alters $@; regression introduced in 2.60.\n\n** AC_USE_SYSTEM_EXTENSIONS now defines _ALL_SOURCE for Interix platforms.\n\n** AS_HELP_STRING no longer underquotes its first argument; it also handles\n   the case where the first argument contains single-quoted commas.\n   For example, \"AS_HELP_STRING([-a, [--arg[=foo]]], [bar])\" produces:\n     \"  -a, --arg[=foo]         bar\"\n   Additionally, the macro now takes two additional arguments,\n   indent-column and wrap-column; these should not normally be needed,\n   but can be used to fine-tune how the output text is wrapped.\n\n** AC_PROG_INSTALL now requires an install program that can install multiple\n   files into a target directory.\n\n** The command 'autoconf -' now correctly processes a file from stdin.\n\n** 'autoreconf -m' now honors $MAKE.\n\n** For all of the directory arguments for 'configure', such as '--prefix'\n   or '--bindir', trailing slashes are stripped.  As an example, if\n   tab completion in the user's shell appends trailing slashes, the\n   command './configure --prefix=/usr/' will still result in an\n   expanded libdir value of /usr/lib, not /usr//lib.\n\n** `configure --help=recursive' now works in read-only trees and from\n   unconfigured build trees.\n\n** If precious variables differ only in whitespace, then the cache consistency\n   check warns instead of fails, and reuses the old value.\n\n** AT_BANNER is now documented.\n\n** AT_SETUP now handles macro expansions properly when calculating line\n   length.\n\n** Autotest now determines $srcdir correctly.\n\n** Testsuites built by autotest now accept a -C/--directory=DIR option\n   to adjust the working directory prior to creating files.\n\n** Autoconf now requires GNU M4 1.4.5 or later.  Earlier versions of M4 have\n   a bug in macro tracing that interferes with the interaction between\n   Autoconf and Automake.  GNU M4 1.4.11 or later is recommended.  The\n   configure search for a working M4 is improved.\n\n** For portability with the eventual M4 2.0, macros should no longer use\n   anything larger than $9 to refer to arguments.\n\n** Documentation for m4sugar is improved.\n\n   - The following macros were previously available as undocumented\n     interfaces; the macros are now documented as stable interfaces.\n\n     __oline__  m4_assert  m4_bmatch  m4_bpatsubsts  m4_car  m4_case\n     m4_cdr  m4_default  m4_divert_once  m4_divert_pop  m4_divert_push\n     m4_divert_text  m4_do  m4_errprintn  m4_fatal  m4_flatten\n     m4_ifndef  m4_ifset  m4_ifval  m4_ifvaln  m4_location\n     m4_n  m4_shiftn  m4_strip  m4_warn\n\n   - The following macros were previously available as undocumented\n     interfaces, but had bug fixes or semantic changes as part of this\n     release.  Packages that relied on the undocumented behavior\n     should be analyzed to make sure they will still work with the\n     new documented behavior.\n\n     m4_cmp  m4_list_cmp  m4_join  m4_map  m4_map_sep  m4_sign\n     m4_text_box  m4_text_wrap  m4_version_compare\n\n   - The m4_wrap macro used to have unspecified order, but now\n     guarantees FIFO order.  m4_wrap_lifo was added to guarantee LIFO\n     order.\n\n   - Packages using the undocumented m4sugar macro m4_PACKAGE_VERSION\n     should consider using the new AC_AUTOCONF_VERSION instead.\n\n   - m4sugar macros that are not documented in the manual are still\n     deemed experimental, and should not be used outside of Autoconf.\n\n** The m4sugar macros m4_append and m4_append_uniq, first documented in\n   2.60, have been fixed to treat both the string and the separator\n   arguments consistently with regards to quoting.  Prior to this fix,\n   m4_append_uniq could mistakenly duplicate entries if the expansion\n   of the separator resulted in a different string (for example, if it\n   contained quotes, a comma, or a macro name).  However, it means\n   that programs previously using\n     m4_append([name], [string], [[, ]])\n   are now using a four-character separator instead of the intended\n   comma and space.  If you need portability to earlier versions of\n   Autoconf, you can insert the following snippet after AC_INIT but\n   before any other macro expansions, to enforce the new semantics:\n     m4_pushdef([m4_append], [m4_define([$1],\n\t   m4_ifdef([$1], [m4_defn([$1])[$3]])[$2])])\n   Additionally, m4_append_uniq now takes optional parameters that can\n   be used to take action depending on whether anything was appended,\n   and warns if a non-empty separator occurs within the string being\n   appended, since that can lead to duplicates.\n\n** The following m4sugar macros are new:\n   m4_append_uniq_w  m4_apply  m4_combine  m4_cond  m4_count\n   m4_dquote_elt  m4_echo  m4_expand  m4_ignore  m4_make_list  m4_max\n   m4_min  m4_newline  m4_shift2  m4_shift3  m4_unquote  m4_wrap_lifo\n\n** Warnings are now generated by default when an installer invokes\n   'configure' with an unknown --enable-* or --with-* option.\n   These warnings can be disabled with the new AC_DISABLE_OPTION_CHECKING\n   macro, or by invoking 'configure' with --disable-option-checking.\n\n** Existing obsolete macros\n   The documentation for the following macros is adjusted to make it\n   more clear that they have previously been marked obsolete, as their\n   functionality can be accomplished by other macros.  We have no\n   current plans to remove them from Autoconf.\n\n     AC_ENABLE  AC_STRUCT_ST_BLKSIZE  AC_STRUCT_ST_RDEV  AC_WITH\n\n** Newly obsolete macros\n   The following macros have been marked obsolete, as they only\n   perform a subset of AC_USE_SYSTEM_EXTENSIONS.  We have no current\n   plans to remove them.\n\n     AC_AIX  AC_GNU_SOURCE  AC_ISC_POSIX  AC_MINIX\n\n** AC_C_LONG_DOUBLE is obsolescent.\n   The documentation now says that AC_C_LONG_DOUBLE is obsolescent: it\n   tests for problems that are so old that it is no longer of\n   practical importance on current systems.  New programs need not use\n   AC_C_LONG_DOUBLE.  We have no current plans to remove it.\n\n** AC_DIAGNOSE, AC_WARNING, and AC_FATAL are obsolescent.\n   The documentation now favors the use of M4sugar macros m4_warn and\n   m4_fatal, since the naming makes it more obvious that the\n   diagnostics are associated with M4 expansion (ie. when running\n   `autoconf'), and offers less confusion with the AC_MSG_ERROR,\n   AC_MSG_FAILURE, and AC_MSG_WARN macros which manage diagnostics\n   when running `configure'.  We have no current plans to remove these\n   macros.\n\n\f\n* Major changes in Autoconf 2.61a (2006-12-11)\n\n** AC_FUNC_FSEEKO was broken in 2.61; it didn't make fseeko and ftello visible\n   on many platforms.  This has been fixed.\n\n** AC_FUNC_SETVBUF_REVERSED is now obsolete.  It is still defined for backward\n   compatibility but it does nothing.  The macro was already\n   obsolescent, as the last systems to have the problem were those\n   based on SVR2, which became obsolete in 1987.  The macro had bugs\n   on some modern systems and could no longer be maintained reliably\n   due to lack of ancient systems to test it on.\n\n** config.status now uses awk instead of sed for most substitutions, for speed.\n\n   - As a side effect multi-line values of substituted variables no\n     longer have a small limit in total size, though for portability\n     each line should not exceed the POSIX length limit for text lines.\n\n   - It is now documented that Makefile.in should not contain\n     overlapping variable occurrences, e.g., @VAR1@VAR2@.\n     Autoconf's behavior was always iffy in such cases, and the\n     awk implementation has changed the behavior.\n\n** Many uses of 'echo' have been rewritten so that Autoconf-generated\n   scripts have fewer problems with strings or file names containing\n   embedded special characters such as backslash or leading \"-\".  This\n   was implemented by using `printf '%s\\n' \"$foo\"' instead of `echo\n   \"$foo\"' when printf works.  Due to the implementation technique\n   used, Autoconf-generated scripts now run considerably more slowly\n   on ancient implementations lacking printf.  However, this should\n   not be a problem, since Autoconf-generated scripts in practice\n   invariably find a more-modern shell these days.\n\n\f\n* Major changes in Autoconf 2.61 (2006-11-17)\n\n** New macros AC_C_FLEXIBLE_ARRAY_MEMBER, AC_C_VARARRAYS.\n\n** AC_ARG_ENABLE and AC_ARG_WITH now allow '.' in feature and package names.\n\n\f\n* Major changes in Autoconf 2.60b (2006-10-22)\n\n** BIN_SH\n  Autoconf-generated shell scripts no longer export BIN_SH, due to\n  configuration hassles with this.  Installers who need BIN_SH in\n  their environment should set it before invoking 'configure' and\n  'make'.  As far as we know, this affects only Unixware installations.\n\n** Obsolescent macros\n  The documentation now says that the following macros are obsolescent,\n  as they are superseded by Gnulib:\n\n    AC_FUNC_FNMATCH  AC_FUNC_FNMATCH_GNU  AC_FUNC_GETLOADVG  AC_REPLACE_FNMATCH\n\n  New programs should use the Gnulib counterparts of these macros.\n  We have no current plans to remove them from Autoconf.\n\n** AC_COMPUTE_INT no longer caches or reports results.\n\n** AC_CHECK_DECL now also works with aggregate objects.\n\n** AC_USE_SYSTEM_EXTENSIONS now defines _TANDEM_SOURCE for NonStop platforms.\n\n** GNU M4 1.4.7 or later is now recommended.\n\n** m4_mkstemp\n  New M4sugar macro, which is more secure than the POSIX M4 maketemp.\n\n** m4_maketemp\n  Now an alias for m4_mkstemp.\n\n* Major changes in Autoconf 2.60a (2006-08-25)\n\n** GNU M4 1.4.6 or later is now recommended.\n\n** The check for C99 now tests for varargs macros, as documented.\n  It also tests that the preprocessor supports 64-bit integers.\n\n** Autoconf now uses constructs like \"#ifdef HAVE_STDLIB_H\" rather than\n  \"#if HAVE_STDLIB_H\", so that it now works with \"gcc -Wundef -Werror\".\n\n** The functionality of the undocumented _AC_COMPUTE_INT is now provided\n  by a public and documented macro, AC_COMPUTE_INT.  The parameters to the\n  two macros are different, so autoupdate will not change the old private name\n  to the new one.  _AC_COMPUTE_INT may be removed in a future release.\n\n** AC_TYPE_LONG_LONG_INT and AC_TYPE_UNSIGNED_LONG_LONG_INT now require\n   that long long types be at least 64 bits wide, as C99 and tradition\n   requires.  Formerly, they accepted implementations of any width.\n\n\f\n* Major changes in Autoconf 2.60\n\n  Released 2006-06-23, by Ralf Wildenhues.\n\n** Autoconf no longer depends on whether m4wrap is FIFO (as Posix requires)\n  or LIFO (as in GNU M4 1.4.x).  GNU M4 2.0 is expected to conform to Posix\n  here, so m4wrap/m4_wrap users should no longer depend on LIFO behavior.\n\n** Provide a way to turn off warnings about the changed directory variables.\n\n* Major changes in Autoconf 2.59d\n\n  Released 2006-06-05, by Ralf Wildenhues.\n\n** GNU make now recommended for VPATH builds\n  INSTALL now suggests VPATH builds (e.g., \"sh ../srcdir/configure\")\n  only if you use GNU make.  In practice, other 'make' implementations\n  have too many subtle incompatibilities in their support for VPATH.\n  Many packages (including Autoconf itself) are portable to other\n  'make' implementations, but some packages are not, and recommending\n  GNU make keeps the installation instructions simpler.\n\n** Even more safety checks for the new Directory variables:\n  Warn about suspicious `${datarootdir}' found in config files output.\n\n** AC_TRY_COMMAND, AC_TRY_EVAL, ac_config_guess, ac_config_sub, ac_configure\n  These never-documented macros and variables have been marked with\n  comments saying that they may be removed in a future release,\n  because their use can lead to unintended code being executed.\n  If you need functionality that only these macros or variables\n  currently supply, please write bug-autoconf@gnu.org.\n\n** AC_SUBST, AC_DEFINE\n  Literal arguments to these are passed to m4_pattern_allow now.\n\n** AC_PROG_CC_STDC\n  Passing 'ac_cv_prog_cc_stdc=no' to 'configure' now sets ac_cv_prog_cc_c99\n  and ac_cv_prog_cc_c89 to 'no' as well, for backward compatibility with\n  obsolete K&R tests in the Automake test suite.\n\n** AC_PROG_CXX_C_O\n  New macro.\n\n** AC_PROG_MKDIR_P\n  New macro.\n\n** AS_MKDIR_P\n  Now more robust with special characters in file names, or when\n  multiple processes create the same directory at the same time.\n\n** Obsolescent macros\n  The documentation now says that the following macros are obsolescent:\n  they test for problems that are so old that they are no longer of\n  practical importance on current systems.\n\n    AC_C_BACKSLASH_A       AC_FUNC_MEMCMP            AC_HEADER_DIRENT\n    AC_C_CONST             AC_FUNC_SELECT_ARGTYPES   AC_HEADER_STAT\n    AC_C_PROTOTYPES        AC_FUNC_SETPGRP           AC_HEADER_STDC\n    AC_C_STRINGIZE         AC_FUNC_SETVBUF_REVERSED  AC_HEADER_SYS_WAIT\n    AC_C_VOLATILE          AC_FUNC_STAT              AC_HEADER_TIME\n    AC_FUNC_CLOSEDIR_VOID  AC_FUNC_STRFTIME          AC_ISC_POSIX\n    AC_FUNC_GETPGRP        AC_FUNC_UTIME_NULL        AC_PROG_GCC_TRADITIONAL\n    AC_FUNC_LSTAT          AC_FUNC_VPRINTF           AC_STRUCT_TM\n\n  New programs need not use these macros.  We have no current plans to\n  remove them.\n\n** autoreconf\n  For compatibility with future Libtool 2.0, autoreconf will invoke\n  libtoolize with the option `--ltdl' now, if LT_CONFIG_LTDL_DIR is\n  used.\n\n* Major changes in Autoconf 2.59c\n\n  Released 2006-04-12, by Ralf Wildenhues.\n\n** The configure command now redirects standard input from /dev/null,\n  to help avoid problems with subsidiary commands that might mistakenly\n  read standard input.  AS_ORIGINAL_STDIN_FD points to the original\n  standard input before this redirection, if you really want configure to\n  read from standard input.\n\n** Directory variables adjusted to recent changes in the GNU Coding Standards.\n  The following directory variables are new:\n\n    datarootdir   read-only architecture-independent data root [PREFIX/share]\n    localedir     locale-specific message catalogs [DATAROOTDIR/locale]\n    docdir        documentation root [DATAROOTDIR/doc/PACKAGE]\n    htmldir       html documentation [DOCDIR]\n    dvidir        dvi documentation [DOCDIR]\n    pdfdir        pdf documentation [DOCDIR]\n    psdir         ps documentation [DOCDIR]\n\n  The following variables have new default values:\n\n    datadir       read-only architecture-independent data [DATAROOTDIR]\n    infodir       info documentation [DATAROOTDIR/info]\n    mandir        man documentation [DATAROOTDIR/man]\n\n  This means that if you use any of `@datadir@', `@infodir@', or\n  `@mandir@' in a file, you will have to ensure `${datarootdir}' is\n  defined in this file.  As a temporary measure, if any of those are\n  found but no mention of `datarootdir', the substitutions will be\n  replaced with values that do not contain `${datarootdir}', and a\n  warning will be issued.\n\n** @top_builddir@ is now a dir name: it is always nonempty and doesn't have\n  a trailing slash.  Similar change will be made to ac_top_builddir in a\n  future release; the old style value, which matches (../)*, is (and will\n  continue to be) available as ac_top_build_prefix.\n\n** AC_C_TYPEOF\n  New macro to check for support of 'typeof' syntax a la GNU C.\n\n** AC_CHECK_DECLS_ONCE, AC_CHECK_FUNCS_ONCE, AC_CHECK_HEADERS_ONCE\n  New \"once-only\" variants of commonly-used macros, to make 'configure'\n  smaller and faster in common cases.\n\n** AC_FUNC_STRTOLD\n  New macro to check for strtold with C99 semantics.\n\n** AC_HEADER_ASSERT\n  New macro that lets builder disable assertions at 'configure'-time.\n\n** AC_PATH_X\n  Now checks for X11/Xlib.h and XrmInitialize (X proper) rather than\n  X11/Intrinsic.h and XtMalloc (Xt).\n\n** AC_PRESERVE_HELP_ORDER\n  New macro that causes `configure' to display help strings for AC_ARG_ENABLE\n  and AC_ARG_WITH arguments in one region, in the order defined.  The default\n  behavior is to group options of each classes separately.\n\n** AC_PROG_CC, AC_PROG_CXX\n  No longer automatically arrange to declare the 'exit' function of C,\n  when a C++ compiler is used.  Standard Autoconf macros no longer use\n  'exit', so this is no longer an issue for them.  If you use C++, and\n  want to call 'exit', you'll have to arrange for its declaration\n  yourself.  But we now suggest you return from 'main' instead.\n\n** AC_PROG_CC_C89, AC_PROG_CC_C99\n  New macros for ISO C99 support.  AC_PROG_CC_C89 and AC_PROG_CC_C99\n  check for ANSI C89 and ISO C99 support respectively.\n\n** AC_PROG_CC_STDC\n  Has been unobsoleted, and will check if the compiler supports ISO\n  C99, falling back to ANSI C89 if not.  ac_cv_prog_cc_stdc is\n  retained for backwards compatibility, assuming the value of\n  ac_cv_prog_cc_c99 or ac_cv_prog_cc_c89 (whichever is valid, in\n  that order).\n\n** AC_STRUCT_DIRENT_D_INO, AC_STRUCT_DIRENT_D_TYPE\n  New macros for checking commonly-used members of struct dirent.\n\n** AC_SUBST\n  The substituted value can now contain newlines.\n\n** AC_SUBST_FILE\n  The substitution now occurs only when @variable@ is on a line by itself,\n  optionally surrounded by spaces and tabs.  The whole line is replaced.\n\n** AC_TYPE_LONG_DOUBLE, AC_TYPE_LONG_DOUBLE_WIDER\n  New macros to check for long double, and whether it is wider than double.\n  The old macro AC_C_TYPE_LONG_DOUBLE has been marked as obsolete;\n  applications should switch to the new macro.\n\n** AC_TYPE_INT8_T, AC_TYPE_INT16_T, AC_TYPE_INT32_T, AC_TYPE_INT64_T,\n   AC_TYPE_INTMAX_T, AC_TYPE_INTPTR_T, AC_TYPE_LONG_LONG_INT, AC_TYPE_SSIZE_T,\n   AC_TYPE_UINT8_T, AC_TYPE_UINT16_T, AC_TYPE_UINT32_T, AC_TYPE_UINT64_T,\n   AC_TYPE_UINTMAX_T, AC_TYPE_UINTPTR_T, AC_TYPE_UNSIGNED_LONG_LONG_INT\n  New macros to check for C99 and POSIX types.\n\n** AC_USE_SYSTEM_EXTENSIONS\n  New macro to enable extensions to Posix.\n\n** AH_HEADER\n  New macro which is defined to the name of the first declared config header\n  or undefined if no config headers have been declared yet.\n\n** AS_HELP_STRING\n  The macro correctly handles quadrigraphs now.\n\n** AS_BOURNE_COMPATIBLE, AS_SHELL_SANITIZE, AS_CASE\n  These macros are new or published now.\n\n** AT_COPYRIGHT\n  New macro for copyright notices in testsuite files.\n\n** ALLOCA, LIBOBJS, LTLIBOBJS\n  Object names added to these variables are now prefixed with `${LIBOBJDIR}',\n  as in `${LIBOBJDIR}alloca.o'.  LIBOBJDIR is meant to be defined from\n  `Makefile.in' in case the object files lie in a different directory.\n  The LIBOBJDIR feature is experimental.\n\n** autoreconf\n  Supports --no-recursive now.\n\n** New macros to support Erlang/OTP.\n  New macros for configuring paths to Erlang tools and libraries:\n  AC_ERLANG_PATH_ERLC, AC_ERLANG_NEED_ERLC, AC_ERLANG_PATH_ERL,\n  AC_ERLANG_NEED_ERL, AC_ERLANG_CHECK_LIB, AC_ERLANG_SUBST_ROOT_DIR,\n  AC_ERLANG_SUBST_LIB_DIR.\n\n  New macros for configuring installation of Erlang libraries:\n  AC_ERLANG_SUBST_INSTALL_LIB_DIR, AC_ERLANG_SUBST_INSTALL_LIB_SUBDIR.\n\n** The manual now mentions Gnulib more prominently.\n\n** New macros to support Objective C.\n  AC_PROG_OBJC, AC_PROG_OBJCPP.\n\n* Major changes in Autoconf 2.59b\n\n  Released 2004-08-20, by Paul Eggert.\n\n** AC_CHECK_ALIGNOF\n  New macro that computes the default alignment of a type.\n\n** AC_CHECK_TOOL, AC_PATH_TOOL, AC_CHECK_TOOLS\n  When cross-compiling, these macros will give a warning if the tool\n  is not prefixed.  In the future, unprefixed cross tools will not\n  be detected; please consult the info documentation for information\n  about the reason of this change.\n\n** AC_CHECK_TARGET_TOOL, AC_PATH_TARGET_TOOL, AC_CHECK_TARGET_TOOLS\n  New macros that detect programs whose name is prefixed with the\n  target type, if the build type and target type are different.\n\n** AC_REQUIRE_AUX_FILE\n  New trace macro that declares expected auxiliary files.\n\n** AC_PROG_GREP\n  New macro that tests for a grep program that accepts as a long a line\n  as possible.\n\n** AC_PROG_EGREP, AC_PROG_FGREP\n  These macros now require AC_PROG_GREP, and try EGREP=\"$GREP -E\" and\n  FGREP=\"$GREP -F\" respectively if possible, or else run a path search for\n  a program that accepts as long a line as possible.\n\n** AC_PROG_SED\n  New macro that tests for a sed program that truncates as few characters\n  as possible.\n\f\n* Major changes in Autoconf 2.59\n\n  Released 2003-11-04, by Akim Demaille\n\n** ac_abs_builddir etc.\n  Absolute file names were actually relative in 2.58.\n\f\n* Major changes in Autoconf 2.58\n\n  Released 2003-11-04, by Akim Demaille\n\n** core.*\n  core.* files are no longer removed, as they may be valid user files.\n\n** autoreconf and auxiliary directory\n  Autoreconf creates the auxiliary directory if needed.  This is\n  especially useful for initial \"bootstrapping\" of fresh CVS checkouts.\n\n** AC_CONFIG_MACRO_DIR\n  Use this macro to declare the directory for local M4 macros for aclocal.\n\n** AC_LIBOBJS\n  No longer includes twice the same file in LIBOBJS if invoked\n  multiple times.\n\n** AC_CONFIG_COMMANDS\n  The directory for its first argument is automatically created.  For\n  instance, with\n\n      AC_CONFIG_COMMANDS([src/modules.hh], [...])\n\n  $top_builddir/src/ is created if needed.\n\n** Autotest and local.at\n  The optional file local.at is always included in Autotest test suites.\n\n** Warnings\n  The warnings are always issued, including with cached runs.\n  This became a significant problem since aclocal and automake can\n  run autoconf behind the scene.\n\n** autoheader warnings\n  The warnings of autoheader can be turned off, using --warning.\n  For instance, -Wno-obsolete disables the complaints about acconfig.h\n  and other deprecated constructs.\n\n** New macros\n  AC_C_RESTRICT, AC_INCLUDES_DEFAULT, AC_LANG_ASSERT, AC_LANG_WERROR,\n  AS_SET_CATFILE.\n\n** AC_DECL_SYS_SIGLIST\n  Works again.\n\n** AC_FUNC_MKTIME\n  Now checks that mktime is the inverse of localtime.\n\n** Improve DJGPP portability\n  The Autoconf tools and configure behave better under DJGPP.\n\n** Present But Cannot Be Compiled\n  New FAQ section dedicated to the mystic\n\n    configure: WARNING: pi.h: present but cannot be compiled\n    configure: WARNING: pi.h: check for missing prerequisite headers?\n    configure: WARNING: pi.h: proceeding with the preprocessor's result\n      messages.\n\n** Concurrent executions of autom4te\n  autom4te now locks its internal files, which enables concurrent\n  executions of autom4te, likely to happen if automake, autoconf,\n  autoheader etc. are run simultaneously.\n\n** Libtool\n  Use of Libtool 1.5 and higher is encouraged.  Compatibility with\n  Libtool pre-1.4 is not checked.\n\n** Autotest\n  Testsuites no longer rerun failed tests in verbose mode; instead,\n  failures are logged while the test is run.\n\n  In addition, expected failures can be marked as such.\n\f\n* Major changes in Autoconf 2.57\n\n  Released 2002-12-03 by Paul Eggert.\n\nBug fixes for problems with AIX linker, with freestanding C compilers,\nwith GNU M4 limitations, and with obsolete copies of GNU documents.\n\nThe Free Documentation License has been upgraded from 1.1 to 1.2.\n\f\n* Major changes in Autoconf 2.56\n\n  Released 2002-11-15 by Akim Demaille.\n\nOne packaging problem fixed (config/install-sh was not executable).\n\f\n* Major changes in Autoconf 2.55\n\n  Released 2002-11-14 by Akim Demaille.\n\nRelease tips:\n\n\t   Have your configure.ac checked by autoscan (\"autoscan\").\n\t     Try the warning options (\"autoreconf -fv -Wall\").\n\n** Documentation\n\n- AC_CHECK_HEADER, AC_CHECK_HEADERS\n  More information on proper use.\n\n- Writing Test Programs\n\n  This sections explains how to write good test sources to use with\n  AC_COMPILE_IFELSE etc.  It documents AC_LANG_PROGRAM and so forth.\n\n- AC_FOO_IFELSE vs. AC_TRY_FOO\n\n  Explains why Autoconf moves from AC_TRY_COMPILE etc. to\n  AC_COMPILE_IFELSE and AC_LANG_PROGRAM etc.\n\n** autoreconf\n\n- Is more robust to different Gettext installations.\n\n- Produces messages (when --verbose) to be understood by Emacs'\n  compile mode.\n\n- Supports -W/--warnings.\n\n- -m/--make\n  Once the GNU Build System reinstalled, run `./config.status\n  --recheck && ./config.status && make' if possible.\n\n** autom4te\n\n- Supports --cache, and --no-cache.\n\n- ~/.autom4te.cfg makes it possible to disable the caching mechanism\n  (autom4te.cache).  See `Customizing autom4te' in the documentation.\n\n** config.status\n  Supports --quiet.\n\n** Obsolete options\n\n  Support for the obsoleted options -m, --macrodir, -l, --localdir is\n  dropped in favor of the safer --include/--prepend-include scheme.\n\n** Macros\n\n- New macros\n  AC_COMPILER_IFELSE, AC_FUNC_MBRTOWC, AC_HEADER_STDBOOL,\n  AC_LANG_CONFTEST, AC_LANG_SOURCE, AC_LANG_PROGRAM, AC_LANG_CALL,\n  AC_LANG_FUNC_TRY_LINK, AC_MSG_FAILURE, AC_PREPROC_IFELSE.\n\n- Obsoleted\n  Obsoleted macros are kept for Autoconf backward compatibility, but\n  should be avoided in configure.ac.  Running autoupdate is advised.\n  AC_DECL_SYS_SIGLIST.\n\n- AC_DEFINE/AC_DEFINE_UNQUOTED\n\n  We have to stop using the old compatibility scheme --that tried to\n  avoid useless backslashes-- because Libtool 1.4.3 contains a\n\n  AC_DEFINE([error_t], [int],\n\t    [Define to a type to use for \\`error_t' if it is not\n\t     otherwise available.])\n\n  We have to quote the single quotes and backslashes with \\.  The old\n  compatibility scheme saw that ` was backslashed, and therefore did\n  not quote the single quote...  Failure.  Hence, Autoconf 2.54 is not\n  compatible with Libtool.  Autoconf 2.55 is, but in some cases might\n  produce more \\ than wanted.\n\n  Please, note that in the future the same problem will happen with\n  AC_MSG_*: use `autoreconf -f -Wall'.\n\n** Bug Fixes\n\n- Portability of the Autoconf package to Solaris.\n\n- Spurious warnings caused by config.status.\n  This bug is benign, but painful: on some systems (typically\n  FreeBSD), warnings such as:\n\n     config.status: creating Makefile\n     mv: Makefile: set owner/group (was: 1357/0): Operation not permitted\n\n  could be issued.  This is fixed.\n\n- Parallel Builds\n  Simultaneous executions of config.status are possible again.\n\n- Precious variables accumulation\n\n  config.status could stack several copies of the precious variables\n  assignments.\n\n\n** Plans for later versions\n\n- ./configure <host>\n\n  The compatibility hooks with the old scheme will be completely\n  removed.  Please, advice/use `--build', `--host', and `--target'\n  only.\n\n- AC_CHECK_HEADER, AC_CHECK_HEADERS\n\n  The tests will be stricter, please make sure your invocations are\n  valid.\n\n- shell functions\n\n  Shell functions will gradually be introduced, probably starting with\n  Autotest.  If you know machines which are in use that you suspect\n  *not* to support shell functions, please run the test suite of\n  Autoconf 2.55 on it, and report the results to\n  bug-autoconf@gnu.org.\n\n- AC_MSG_*\n\n  Special characters in AC_MSG_* need not be quoted.  Currently,\n  Autoconf has heuristics to decide when a string is escaped, or has\n  to be escaped.  This scheme is fragile, and will be removed; the\n  only risk is uglified messages.  Please, run `autoreconf -f -Wall'\n  to find occurrences that will be affected.\n\f\n* Major changes in Autoconf 2.54\n\n  Released 2002-09-13 by Akim Demaille.\n\n** Executables\n\n- autoreconf no longer changes the version of the gettext/po/intl\n  support files. It now adds the files the correspond to the\n  AM_GNU_GETTEXT_VERSION declared in configure.ac.\n\n  Warning: It now relies on the 'autopoint' program, which is part\n  of GNU gettext 0.11.4 and newer.\n\n  Please note that you need to have a GNU gettext version that\n  corresponds at least to the AM_GNU_GETTEXT_VERSION declared\n  in configure.ac. You can upgrade to newer GNU gettext versions,\n  though, without needing to change configure.ac.\n\n- The -I DIR or --include=DIR option now appends DIR to the include path\n  instead of prepending; this is for consistency with other GNU tools.\n  The new -B DIR or --prepend-include=DIR option has the old behavior.\n\n** Macros\n\n- AC_OUTPUT\n  Now handles all the gory details about LIBOBJS and LTLIBOBJS.\n  Please, remove lines such as\n\n\t# This is necessary so that .o files in LIBOBJS are also\n\t# built via the ANSI2KNR-filtering rules.\n\tLIBOBJS=`echo $LIBOBJS|sed 's/\\.o /\\$U.o /g;s/\\.o$/\\$U.o/'`\n\n  and read the `AC_LIBOBJ vs LIBOBJS' section.  Do not define U in\n  your Makefiles either.\n\n- AC_CONFIG_LINKS now makes copies if it can't make links.\n\n- AC_FUNC_FNMATCH now tests only for POSIX compatibility, reverting to\n  Autoconf 2.13 behavior.  The new macro AC_FUNC_FNMATCH_GNU also\n  tests for GNU extensions to fnmatch, and replaces fnmatch if needed.\n\n- AC_FUNC_SETVBUF_REVERSED no longer fails when cross-compiling.\n\n- AC_PROG_CC_STDC is integrated into AC_PROG_CC.\n\n- AC_PROG_F77 default search no longer includes cf77 and cfg77.\n\n- New macros\n\n  AC_C_BACKSLASH_A, AC_CONFIG_LIBOBJ_DIR, AC_GNU_SOURCE,\n  AC_PROG_EGREP, AC_PROG_FGREP, AC_REPLACE_FNMATCH,\n  AC_FUNC_FNMATCH_GNU, AC_FUNC_REALLOC, AC_TYPE_MBSTATE_T.\n\n- AC_FUNC_GETLOADAVG\n  looks for getloadavg.c in the CONFIG_LIBOBJ_DIR.\n\n- AC_FUNC_MALLOC\n  Now defines HAVE_MALLOC to 0 if `malloc' does not work, and asks\n  for an AC_LIBOBJ replacement.\n\n** Bug fixes\n\n- Spurious complaints from `m4_bmatch' about invalid regular\n  expressions are suppressed.\n\n- Empty top_builddirs are properly handled.\n\n- AC_CHECK_MEMBER works correctly when the member is an aggregate.\n\n- AC_PATH_PROG\n  Now colon in the optional path arguments are properly handled.\n\n** Improved portability\n\n- Both Autoconf the package, and the scripts it produces, should run\n  more reliably with Zsh.  Bear in mind it is the default Bourne shell\n  on Darwin.\n\n- Autoconf and the scripts it produces no longer assume the existence of\n  the obsolescent commands egrep and fgrep.\n\n** Documentation\n\n- Limitations of Make\n  More of them.\n\n- GNATS\n  The GNATS base moved to\n  https://bugs.gnu.org/cgi-bin/gnatsweb.pl?database=autoconf\n  (It is no longer available, though.)\n\n** Misc.\n\n- config.log\n  Now contains the list of output variables and files (AC_SUBST,\n  AC_SUBST_FILES).\n\f\n* Major changes in Autoconf 2.53\n\n  Released 2002-03-08 by Akim Demaille.\n\n** Requirements\n\n  Perl 5.005_03 or later is required: autom4te is written in Perl and is\n  needed by autoconf.  autoheader, autoreconf, ifnames, and autoscan are\n  rewritten in Perl.\n\n** Documentation\n\n- AC_INIT\n  Argument requirements, output variables, defined macros.\n- M4sugar, M4sh, Autotest\n  First sketch.\n- Double quoting macros\n  AC_TRY_CPP, AC_TRY_COMPILE, AC_TRY_LINK and AC_TRY_RUN.\n- Licensing\n  The Autoconf manual is now distributed under the terms of the GNU FDL.\n- Section `Hosts and Cross-Compilation'\n  Explains the rationale for the 2.5x changes in the cross-compilation\n  chain, and in the relationships between build, host, and target\n  types.\n  Emphasizes that `cross-compilation' == `--host is given'.\n  If you are working on compilers etc., be sure to read this section.\n- Section `AC_LIBOBJ vs. LIBOBJS'\n  Explains why assigning LIBOBJS directly is now an error.\n  Details how to update the code.\n\n** configure\n\n- $LINENO\n  Now used instead of hard coded line numbers.\n  This eases the comparison of `configure's, and diminishes the\n  pressure over control version archives.\n  Automatic replacement for shells that don't support this feature.\n- New output variables\n  @builddir@, @top_builddir@, @abs_srcdir@, @abs_top_srcdir@, @abs_builddir@,\n  @abs_top_builddir@.\n\n** Emacs\n\n  Autoconf and Autotest modes are provided.\n\n** Executables\n\n- autom4te\n  New, used by the Autoconf suite to cache and speed up most processing.\n- --force, -f\n  Supported by autom4te, autoconf and autoheader.\n- --include, -I\n  Replaces --autoconf-dir and --localdir in autoconf, autoheader,\n  autoupdate, and autoreconf.\n- autoreconf\n  No longer passes --cygnus, --foreign, --gnits, --gnu, --include-deps:\n  automake options are to be given via AUTOMAKE_OPTIONS.\n- autoreconf\n  Runs gettextize and libtoolize when appropriate.\n- autoreconf\n  --m4dir is no longer supported.\n- autoreconf\n  Now runs only in the specified directories, defaulting to `.',\n  but understands AC_CONFIG_SUBDIRS for dependent directories.\n  Before, it used to run on all the `configure.ac' found in the\n  current tree.\n  Independent packages are properly updated.\n\n** Bug fixes\n\n- The top level $prefix is propagated to the AC_CONFIG_SUBDIRS configures.\n- AC_TRY_RUN\n  Under the user pressure, $? is finally available.  Probably a mistake.\n- AC_F77_LIBRARY_LDFLAGS now supports the HP/UX f90 compiler.\n- Precious variables accumulation\n  config.status could stack several copies of the precious variables\n  assignments.\n- AC_PATH_PROG and family.\n  Works properly when given a literal path.\n- AC_FUNC_SETPGRP\n  Somewhere since 2.13, the result had been reversed.\n\n** C Macros\n\n- AC_C_BIGENDIAN supports the cross-compiling case.\n- AC_C_BIGENDIAN accepts ACTION-IF-TRUE, ACTION-IF-FALSE, and\n  ACTION-IF-UNKNOWN arguments.  All are optional, and the default\n  for ACTION-IF-TRUE is to define WORDS_BIGENDIAN like AC_C_BIGENDIAN\n  always did.\n- AC_C_LONG_DOUBLE now succeeds only if `long double' has more range or\n  precision than `double'.\n\n** Generic macros\n\n- AC_INIT\n  It now defines the preprocessor symbols PACKAGE_NAME,\n  PACKAGE_TARNAME, PACKAGE_VERSION, PACKAGE_STRING, and\n  PACKAGE_BUGREPORT.\n\n- AC_INIT\n  Admits a fourth optional parameter: the tar name.\n\n- AC_CONFIG_COMMANDS, HEADERS, FILES, LINKS.\n  Provide the user with srcdir, ac_srcdir, ac_top_srcdir, ac_builddir,\n  ac_top_builddir, ac_abs_srcdir, ac_abs_top_srcdir, ac_abs_builddir,\n  ac_abs_top_builddir.\n\n- AC_CONFIG_COMMANDS, HEADERS, FILES, LINKS and AC_OUTPUT.\n  Are much less expensive when using long lists of files.\n\n- AC_PREFIX_PROGRAM\n  Works with shell variables, and non alphanumeric names.\n\n** Library macros\n\n- AC_FUNC_STRERROR_R now sets STRERROR_R_CHAR_P, not HAVE_WORKING_STRERROR_R,\n  because POSIX 1003.1-200x draft 7 says strerror_r returns int, not char *.\n\n- AC_FUNC_STRTOD substitutes POW_LIB.\n\n- AC_FUNC_STRNLEN\n  New.\n\f\n* Major changes in Autoconf 2.52\n\n  Released 2001-07-18 by Akim Demaille.\n\n** Documentation\n- AC_ARG_VAR\n- Quadrigraphs\n  This feature was present in autoconf 2.50 but was not documented.\n  For example, `@<:@' is translated to `[' just before output.  This\n  is useful when writing strings that contain unbalanced quotes, or\n  other hard-to-quote constructs.\n- m4_pattern_forbid, m4_pattern_allow\n- Tips for upgrading from 2.13.\n- Using autoscan to maintain a configure.ac.\n\n** Default includes\n- Now include stdint.h.\n- sys/types.h and sys/stat.h are guarded.\n- strings.h is included if available, and not conflicting with string.h.\n\n** Bug fixes\n- The test suite is more robust and presents less false failures.\n- Invocation of GNU M4 now robust to POSIXLY_CORRECT.\n- configure accepts --prefix='' again.\n- AC_CHECK_LIB works properly when its first argument is not a\n  literal.\n- HAVE_INTTYPES_H is defined only if not conflicting with sys/types.h.\n- build_, host_, and target_alias are AC_SUBST as in 2.13.\n- AC_ARG_VAR properly propagates precious variables inherited from the\n  environment to ./config.status.\n- Using --program-suffix/--program-prefix is portable.\n- Failures to detect the default compiler's output extension are less\n  likely.\n- `config.status foo' works properly when `foo' depends on variables\n  set in an AC_CONFIG_THING INIT-CMD.\n- autoheader is more robust to broken input.\n- Fixed Fortran name-mangling and link tests on a number of systems,\n  e.g. NetBSD; see AC_F77_DUMMY_MAIN, below.\n\n** Generic macros\n- AC_CHECK_HEADER and AC_CHECK_HEADERS support a fourth argument to\n  specify pre-includes.  In this case, the headers are compiled with\n  cc, not merely preprocessed by cpp.  Therefore it is the _usability_\n  of a header which is checked for, not just its availability.\n- AC_ARG_VAR refuses to run configure when precious variables have\n  changed.\n- Versions of compilers are dumped in the logs.\n- AC_CHECK_TYPE recognizes use of `foo_t' as a replacement type.\n\n** Specific Macros\n- AC_PATH_XTRA only adds -ldnet to $LIBS if it's needed to link.\n- AC_FUNC_WAIT3 and AC_SYS_RESTARTABLE_SYSCALLS are obsoleted.\n- AM_FUNC_ERROR_AT_LINE, AM_FUNC_FNMATCH, AM_FUNC_MKTIME,\n  AM_FUNC_OBSTACK, and AM_FUNC_STRTOD are now activated.\n  Be sure to read `Upgrading from Version 2.13' to understand why\n  running `autoupdate' is needed.\n- AC_F77_DUMMY_MAIN, AC_F77_MAIN: new macros to detect whether\n  a main-like routine is required/possible when linking C/C++ with\n  Fortran.  Users of e.g. AC_F77_WRAPPERS should be aware of these.\n- AC_FUNC_GETPGRG behaves better when cross-compiling.\n\f\n* Major changes in Autoconf 2.51\nThere was no release of Autoconf 2.51 since some packagers had used\nthis version number without permission to ship intermediary versions\nof 2.50.  The version was skipped to avoid confusion.\n\f\n* Major changes in Autoconf 2.50\n\n  Released 2001-05-21 by Akim Demaille.\n\n** Lots of bug fixes\nThere have been far too many to enumerate them here.  Check out\nChangeLog if you really want to know more.\n\n** Improved documentation\nIn particular, portability issues are better covered.\n\n** Use of Automake\nAll the standard GNU Makefile targets are supported.  The layout has\nchanged: m4/ holds the M4 extensions Autoconf needs for its\nconfiguration, doc/ contains the documentation, and tests/ contains\nthe test suite.\n\n** Man pages are provided\nFor autoconf, autoreconf, autoupdate, autoheader, autoscan, ifnames,\nconfig.guess, config.sub.\n\n** autoconf\n- --trace\n  Provides a safe and powerful means to trace the macro uses.  This\n  provide the parsing layer for tools which need to `study'\n  configure.in.\n\n- --warnings\n  Specify what category of warnings should be enabled.\n\n- When recursing into subdirectories, try for configure.gnu before\n  configure to adapt for packages not using autoconf on case-insensitive\n  file systems.\n\n- Diagnostics\n  More errors are now caught (circular AC_REQUIRE dependencies,\n  AC_DEFINE in the action part of an AC_CACHE_CHECK, too many pops\n  etc.).  In addition, their location and call stack are given.\n\n** autoupdate\nautoupdate is much more powerful, and is able to provide the glue code\nwhich might be needed to move from an old macro to its newer\nequivalent.\n\nYou are strongly encouraged to use it to modernize both your\n`configure.in' and your .m4 extension files.\n\n** autoheader\nThe internal machinery of autoheader has completely changed.  As a\nresult, using `acconfig.h' should be considered to be obsoleted, and\nyou are encouraged to get rid of it using the AH macros.\n\n** autoreconf\nExtensive overhaul.\n\n** Fortran 77 compilers\nGlobally, the support for Fortran 77 is considerably improved.\n\nSupport for automatically determining a Fortran 77 compiler's\nname-mangling scheme.  New CPP macros F77_FUNC and F77_FUNC_ are\nprovided to wrap C/C++ identifiers, thus making it easier and more\ntransparent for C/C++ to call Fortran 77 routines, and Fortran 77 to\ncall C/C++ routines.  See the Texinfo documentation for details.\n\n** Test suite\nThe test suite no longer uses DejaGNU.  It should be easy to submit\ntest cases in this new framework.\n\n** configure\n- --help, --help=long, -hl\n  no longer dumps useless items.\n- --help=short, -hs\n  lists only specific options.\n- --help=recursive, -hr\n  displays the help of all the embedded packages.\n- Remembers environment variables when reconfiguring.\n  The previous scheme to set envvar before running configure was\n    ENV=VAL ./configure\n  what prevented configure from remembering the environment in which\n  it was run, therefore --recheck was run in an inconsistent\n  environment.  Now, one should run\n    ./configure ENV=VAR\n  and then --recheck will work properly.  Variables declared with\n  AC_ARG_VAR are also preserved.\n- cross-compilation\n  $build defaults to `config.guess`, $host to $build, and then $target\n  to $host.\n  Cross-compilation is a global status of the package, it no longer\n  depends upon the current language.\n  Cross compilation is enabled iff the user specified `--host'.\n  `configure' now fails if it can't run the executables it compiles,\n  unless cross-compilation is enabled.\n- Cache file\n  The cache file is disabled by default.  The new options\n  `--config-cache', `-C' set the cache to `config.cache'.\n\n** config.status\n- faster\n  Much faster on most architectures.\n- concurrent executions\n  It is safe to use `make -j' with config.status.\n- human interface improved\n  It is possible to invoke\n    ./config.status foobar\n  instead of the former form (still valid)\n    CONFIG_COMMANDS= CONFIG_HEADERS= CONFIG_LINKS= \\\n    CONFIG_FILES=foobar:foo.in:bar.in \\\n    ./config.status\n  The same holds for configuration headers and links.\n  You can instantiate unknown files and headers:\n    ./config.status --header foo.h:foo.h.in --file bar:baz\n- has a useful --help\n- accepts special file name \"-\" for stdin/stdout\n\n\n** Identity Macros\n- AC_COPYRIGHT\n  Specify additional copyright information.\n\n- AC_INIT\n  Now expects the identity of the package as argument.\n\n** General changes.\n- Uniform quotation\n  Most macros, if not all, now strictly follow the `one quotation\n  level' rule.  This results in a more predictable expansion.\n\n- AC_REQUIRE\n  A sly bug in the AC_REQUIRE machinery, which could produce incorrect\n  configure scripts, was fixed by Axel Thimm.\n\n** Setup Macros\n- AC_ARG_VAR\n  Document and ask for the registration of an envvar.\n\n- AC_CONFIG_SRCDIR\n  Specifies the file which `configure' should look for when trying to\n  find the source tree (used to be handled by AC_INIT).\n\n- AC_CONFIG_COMMANDS\n  To add new actions to config.status.  Should be used instead of\n  AC_OUTPUT_COMMANDS.\n\n- AC_CONFIG_LINKS\n  Replaces AC_LINK_FILES.\n\n- AC_CONFIG_HEADERS, AC_CONFIG_COMMANDS, AC_CONFIG_SUBDIRS,\n  AC_CONFIG_LINKS, and AC_CONFIG_FILES\n  They now obey sh: you should no longer use shell variables as\n  argument.  Instead of\n\n\ttest \"$package_foo_enabled\" = yes && $my_subdirs=\"$my_subdirs foo\"\n\tAC_CONFIG_SUBDIRS($my_subdirs)\n\n  write\n\n\tif test \"$package_foo_enabled\" = yes; then\n\t  AC_CONFIG_SUBDIRS(foo)\n\tfi\n\n- AC_HELP_STRING\n  To format an Autoconf macro's help string so that it looks pretty\n  when the user executes `configure --help'.\n\n\n** Generic Test Macros\n- AC_CHECK families\n  The interface of the AC_CHECK families of macros (decl, header,\n  type, member, func) is now uniform.  They support the same set of\n  default includes.\n\n- AC_CHECK_DECL, AC_CHECK_DECLS\n  To check whether a symbol is declared.\n\n- AC_CHECK_SIZEOF, AC_C_CHAR_UNSIGNED.\n  No longer need a cross-compilation default.\n\n- AC_CHECK_TYPE\n  The test it performs is much more robust than previously, and makes\n  it possible to test builtin types in addition to typedefs.\n  It is now schizophrenic:\n    - AC_CHECK_TYPE(TYPE, REPLACEMENT)\n      remains for backward compatibility, but its use is discouraged.\n    - AC_CHECK_TYPE(TYPE, IF-FOUND, IF-NOT-FOUND, INCLUDES)\n      behaves exactly like the other AC_CHECK macros.\n\n- AC_CHECK_TYPES\n  Checks whether given types are supported by the system.\n\n- AC_CHECK_MEMBER, AC_CHECK_MEMBERS\n  Check for given members in aggregates (e.g., pw_gecos in struct\n  passwd).\n\n- AC_PROG_CC_STDC\n  Checks if the compiler supports ISO C, included when needs special\n  options.\n\n- AC_PROG_CPP\n  Checking whether the preprocessor indicates missing includes by the\n  error code. stderr is checked by AC_TRY_CPP only as a fallback.\n\n- AC_LANG\n  Takes a language as argument and replaces AC_LANG_C,\n  AC_LANG_CPLUSPLUS and AC_LANG_FORTRAN77.\n\n- AC_LANG_PUSH, AC_LANG_POP\n  Are preferred to AC_LANG_SAVE, AC_LANG_RESTORE.\n\n** Specific Macros\n- AC_FUNC_CHOWN, AC_FUNC_MALLOC, AC_FUNC_STRERROR_R,\n  AC_FUNC_LSTAT_FOLLOWS_SLASHED_SYMLINK, AC_FUNC_STAT, AC_FUNC_LSTAT,\n  AC_FUNC_ERROR_AT_LINE, AC_FUNC_OBSTACK, AC_FUNC_STRTOD, AC_FUNC_FSEEKO.\n  New.\n\n- AC_FUNC_GETGROUPS\n  Sets GETGROUPS_LIBS.\n\n- AC_FUNC_GETLOADAVG\n  Defines `HAVE_STRUCT_NLIST_N_UN_N_NAME' instead of `NLIST_NAME_UNION'.\n\n- AC_PROG_LEX\n  Now integrates `AC_DECL_YYTEXT' which is obsoleted.\n\n- AC_SYS_LARGEFILE\n  Arrange for large-file support.\n\n- AC_EXEEXT, AC_OBJEXT\n  You are no longer expected to use them: their computation is\n  performed by default.\n\n** C++ compatibility\n  Every macro has been revisited in order to support at best CC=c++.\n\f\nMajor changes in Autoconf 2.14:\n  There was no release of GNU Autoconf 2.14.\n\f\nMajor changes in Autoconf 2.13:\n\n  Released 1999-05-01 by Ben Elliston.\n\n* Support for building on 32-bit Windows systems where the only available C or\n  C++ compiler is the Microsoft Visual C++ command line compiler\n  (`cl').  Additional support for building on 32-bit Windows systems which are\n  using the Cygwin or Mingw32 environments.\n* Support for alternative object file and executable file extensions.\n  On 32-bit Windows, for example, these are .obj and .exe. These are discovered\n  using AC_OBJEXT and AC_EXEEXT, which substitute @OBJEXT@ and\n  @EXEEXT@ in the output, respectively.\n* New macros: AC_CACHE_LOAD, AC_CACHE_SAVE, AC_FUNC_SELECT_ARGTYPES,\n  AC_VALIDATE_CACHED_SYSTEM_TUPLE, AC_SEARCH_LIBS, AC_TRY_LINK_FUNC,\n  AC_C_STRINGIZE, AC_CHECK_FILE(S), AC_PROG_F77 (and friends).\n* AC_DEFINE now has an optional third argument for a description to be\n  placed in the config header input file (e.g. config.h.in).\n* The C++ code fragment compiled for the C++ compiler test had to be\n  improved to include an explicit return type for main(). This was\n  causing failures on systems using recent versions of the EGCS C++\n  compiler.\n* Fixed an important bug in AC_CHECK_TYPE that would cause a configure\n  script to report that `sometype_t' was present when only `type_t'\n  was defined.\n* Merge of the FSF version of config.guess and config.sub to modernize\n  these scripts. Add support for a few new hosts in config.guess.\n  Incorporate latest versions of install-sh, mkinstalldirs and\n  texinfo.tex from the FSF.\n* autoreconf is capable of running automake if necessary (and\n  applicable).\n* Support for Fortran 77. See the Texinfo documentation for details.\n* Bug fixes and workarounds for quirky bugs in vendor utilities.\n\f\nMajor changes in Autoconf 2.12:\n\n  Released 1996-11-26 by David J. MacKenzie\n\n* AC_OUTPUT and AC_CONFIG_HEADERS can create output files by\n  concatenating multiple input files separated by colons, like so:\n  AC_CONFIG_HEADERS([config.h:conf.pre:config.h.in:conf.post])\n  AC_OUTPUT([Makefile:Makefile.in:Makefile.rules])\n  The arguments may be shell variables, to compute the lists on the fly.\n* AC_LINK_FILES and AC_CONFIG_SUBDIRS may be called multiple times.\n* New macro AC_OUTPUT_COMMANDS adds more commands to run in config.status.\n* Bug fixes.\n\f\nMajor changes in Autoconf 2.11:\n\n  Released November 18th, 1996, by David J. MacKenzie\n\n* AC_PROG_CC and AC_PROG_CXX check whether the compiler works.\n  They also default CFLAGS/CXXFLAGS to \"-g -O2\" for gcc, instead of \"-g -O\".\n* AC_REPLACE_FUNCS defines HAVE_foo if the system has the function `foo'.\n* AC_CONFIG_HEADERS expands shell variables in its argument.\n* New macros: AC_FUNC_FNMATCH, AC_FUNC_SETPGRP.\n* The \"checking...\" messages and the source code for test programs that\n  fail are saved in config.log.\n* Another workaround has been added for seds with small command length limits.\n* config.sub and config.guess recognize more system types.\n* Bug fixes.\n\f\nMajor changes in Autoconf 2.10:\n\n  Released May 7th, 1996, by Roland McGrath\n\n* Bug fixes.\n* The cache variable names used by `AC_CHECK_LIB(LIB, FUNC, ...)' has\n  changed: now $ac_cv_lib_LIB_FUNC, previously $ac_cv_lib_LIB.\n\f\nMajor changes in Autoconf 2.9:\n\n  Released March 16th, 1996, by Roland McGrath\n\n* Bug fixes.\n\f\nMajor changes in Autoconf 2.8:\n\n  Released March 8th, 1996, by Roland McGrath\n\n* Bug fixes.\n\f\nMajor changes in Autoconf 2.7:\n\n  Released November 22nd, 1995, by David J. MacKenzie\n\n* Bug fixes.\n\f\nMajor changes in Autoconf 2.6:\n\n  Released November 20th, 1995, by David J. MacKenzie\n\n* Bug fixes.\n\f\nMajor changes in Autoconf 2.5:\n\n  Released November 17th, 1995, by Roland McGrath\n\n* New configure options --bindir, --libdir, --datadir, etc., with\n  corresponding output variables.\n* New macro: AC_CACHE_CHECK, to make using the cache easier.\n* config.log contains the command being run as well as any output from it.\n* AC_CHECK_LIB can check for libraries with \".\" or \"/\" or \"+\" in their name.\n* AC_PROG_INSTALL doesn't cache a name for install-sh, for sharing caches.\n* AC_CHECK_PROG, AC_PATH_PROG, AC_CHECK_PROGS, AC_PATH_PROGS, and\n  AC_CHECK_TOOL can search a path other than $PATH.\n* AC_CHECK_SIZEOF takes an optional size to use when cross-compiling.\n\f\nMajor changes in Autoconf 2.4:\n\n  Released June 14th, 1995, by David J. MacKenzie\n\n* Fix a few bugs found by Emacs testers.\n\f\nMajor changes in Autoconf 2.3:\n\n  Released March 27th, 1995, by David J. MacKenzie\n\n* Fix the cleanup trap in several ways.\n* Handle C compilers that are picky about option placement.\n* ifnames gets the version number from the right directory.\n\f\nMajor changes in Autoconf 2.2:\n\n  Released March 8th, 1995, by David J. MacKenzie\n\n* The ifnames utility is much faster but requires a \"new awk\" interpreter.\n* AC_CHECK_LIB and AC_HAVE_LIBRARY check and add the new\n  library before existing libs, not after, in case it uses them.\n* New macros: AC_FUNC_GETPGRP, AC_CHECK_TOOL.\n* Lots of bug fixes.\n* Many additions to the TODO file :-)\n\f\nMajor changes in Autoconf 2.1:\n\n  Released November 4th, 1994, by David J. MacKenzie\n\n* Fix C++ problems.\n* More explanations in the manual.\n* Fix a spurious failure in the testsuite.\n* Clarify some warning messages.\n* autoreconf by default only rebuilds configure and config.h.in files\n  that are older than any of their particular input files; there is a\n  --force option to use after installing a new version of Autoconf.\n\f\nThanks to everybody who's submitted changes and additions to Autoconf!\nI've incorporated many of them, and am still considering others for\nfuture releases -- but I didn't want to postpone this release indefinitely.\n\nCaution: don't indiscriminately rebuild configure scripts with\nAutoconf version 2.  Some configure.in files need minor adjustments to\nwork with it; the documentation has a chapter on upgrading.  A few\nconfigure.in files, including those for GNU Emacs and the GNU C\nLibrary, need major changes because they relied on undocumented\ninternals of version 1.  Future releases of those packages will have\nupdated configure.in files.\n\nIt's best to use GNU M4 1.3 (or later) with Autoconf version 2.\nAutoconf now makes heavy use of M4 diversions, which were implemented\ninefficiently in GNU M4 releases before 1.3.\n\f\nMajor changes in Autoconf 2.0:\n\n  Released October 26th, 1994, by David J. MacKenzie\n\n** New copyright terms:\n* There are no restrictions on distribution or use of configure scripts.\n\n** Documentation:\n* Autoconf manual is reorganized to make information easier to find\n  and has several new indexes.\n* INSTALL is reorganized and clearer and is now made from Texinfo source.\n\n** New utilities:\n* autoscan to generate a preliminary configure.in for a package by\n  scanning its source code for commonly used nonportable functions,\n  programs, and header files.\n* ifnames to list the symbols used in #if and #ifdef directives in a\n  source tree.\n* autoupdate to update a configure.in to use the version 2 macro names.\n* autoreconf to recursively remake configure and configuration header\n  files in a source tree.\n\n** Changed utilities:\n* autoheader can take pieces of acconfig.h to replace config.h.{top,bot}.\n* autoconf and autoheader can look for package-local definition files\n  in an alternate directory.\n\n** New macros:\n* AC_CACHE_VAL to share results of tests between configure runs.\n* AC_DEFUN to define macros, automatically AC_PROVIDE them, and ensure\n  that macros invoked with AC_REQUIRE don't interrupt other macros.\n* AC_CONFIG_AUX_DIR, AC_CANONICAL_SYSTEM, AC_CANONICAL_HOST, AC_LINK_FILES to\n  support deciding unguessable features based on the host and target types.\n* AC_CONFIG_SUBDIRS to recursively configure a source tree.\n* AC_ARG_PROGRAM to use the options --program-prefix,\n  --program-suffix, and --program-transform-name to change the names\n  of programs being installed.\n* AC_PREFIX_DEFAULT to change the default installation prefix.\n* AC_TRY_COMPILE to compile a test program without linking it.\n* AC_CHECK_TYPE to check whether sys/types.h or stdlib.h defines a given type.\n* AC_CHECK_LIB to check for a particular function and library.\n* AC_MSG_CHECKING and AC_MSG_RESULT to print test results, on a single line,\n  whether or not the test succeeds.  They obsolete AC_CHECKING and AC_VERBOSE.\n* AC_SUBST_FILE to insert one file into another.\n* AC_FUNC_MEMCMP to check whether memcmp is 8-bit clean.\n* AC_FUNC_STRFTIME to find strftime even if it's in -lintl.\n* AC_FUNC_GETMNTENT to find getmntent even if it's in -lsun or -lseq.\n* AC_HEADER_SYS_WAIT to check whether sys/wait.h is POSIX.1 compatible.\n\n** Changed macros:\n* Many macros renamed systematically, but old names are accepted for\n  backward compatibility.\n* AC_OUTPUT adds the \"automatically generated\" comment to\n  non-Makefiles where it finds @configure_input@ in an input file, to\n  support files with various comment syntaxes.\n* AC_OUTPUT does not replace \"prefix\" and \"exec_prefix\" in generated\n  files when they are not enclosed in @ signs.\n* AC_OUTPUT allows the optional environment variable CONFIG_STATUS to\n  override the file name \"config.status\".\n* AC_OUTPUT takes an optional argument for passing variables from\n  configure to config.status.\n* AC_OUTPUT and AC_CONFIG_HEADERS allow you to override the input-file names.\n* AC_OUTPUT automatically substitutes the values of CFLAGS, CXXFLAGS,\n  CPPFLAGS, and LDFLAGS from the environment.\n* AC_PROG_CC and AC_PROG_CXX now set CFLAGS and CXXFLAGS, respectively.\n* AC_PROG_INSTALL looks for install-sh or install.sh in the directory\n  specified by AC_CONFIG_AUXDIR, or srcdir or srcdir/.. or\n  srcdir/../.. by default.\n* AC_DEFINE, AC_DEFINE_UNQUOTED, and AC_SUBST are more robust and smaller.\n* AC_DEFINE no longer prints anything, because of the new result reporting\n  mechanism (AC_MSG_CHECKING and AC_MSG_RESULT).\n* AC_VERBOSE pays attention to --quiet/--silent, not --verbose.\n* AC_ARG_ENABLE and AC_ARG_WITH support whitespace in the arguments to\n  --enable- and --with- options.\n* AC_CHECK_FUNCS and AC_CHECK_HEADERS take optional shell commands to\n  execute on success or failure.\n* Checking for C functions in C++ works.\n\n** Removed macros:\n* AC_REMOTE_TAPE and AC_RSH removed; too specific to tar and cpio, and\n  better maintained with them.\n* AC_ARG_ARRAY removed because no one was likely using it.\n* AC_HAVE_POUNDBANG replaced with AC_SYS_INTERPRETER, which doesn't\n  take arguments, for consistency with all of the other specific checks.\n\n** New files:\n* Comes with config.sub and config.guess, and uses them optionally.\n* Uses config.cache to cache test results.  An alternate cache file\n  can be selected with the --cache-file=FILE option.\n* Uses optional shell scripts $prefix/share/config.site and\n  $prefix/etc/config.site to perform site or system specific initializations.\n* configure saves compiler output to ./config.log for debugging.\n* New files autoconf.m4 and autoheader.m4 load the other Autoconf macros.\n* acsite.m4 is the new name for the system-wide aclocal.m4.\n* Has a DejaGnu test suite.\n\f\nMajor changes in Autoconf 1.11:\n\n* AC_PROG_INSTALL calls install.sh with the -c option.\n* AC_SET_MAKE cleans up after itself.\n* AC_OUTPUT sets prefix and exec_prefix if they weren't set already.\n* AC_OUTPUT prevents shells from looking in PATH for config.status.\n\nPlus a few other bug fixes.\n\f\nMajor changes in Autoconf 1.10:\n\n* autoheader uses config.h.bot if present, analogous to config.h.top.\n* AC_PROG_INSTALL looks for install.sh in srcdir or srcdir/.. and\n  never uses cp.\n* AC_PROG_CXX looks for cxx as a C++ compiler.\n\nPlus several bugs fixed.\n\f\nMajor changes in Autoconf 1.9:\n\n* AC_YYTEXT_POINTER replaces AC_DECLARE_YYTEXT.\n* AC_SIZEOF_TYPE generates the cpp symbol name automatically,\n  and autoheader generates entries for those names automatically.\n* AC_FIND_X gets the result from xmkmf correctly.\n* AC_FIND_X assumes no X if --without-x was given.\n* AC_FIND_XTRA adds libraries to the variable X_EXTRA_LIBS.\n* AC_PROG_INSTALL finds OSF/1 installbsd.\n\f\nMajor changes in Autoconf 1.8:\n\n** New macros:\n* New macros AC_LANG_C, AC_LANG_CPLUSPLUS, AC_LANG_SAVE, AC_LANG_RESTORE,\n  AC_PROG_CXX, AC_PROG_CXXCPP, AC_REQUIRE_CPP\n  for checking both C++ and C features in one configure script.\n* New macros AC_CHECKING, AC_VERBOSE, AC_WARN, AC_ERROR for printing messages.\n* New macros AC_FIND_XTRA, AC_MMAP, AC_SIZEOF_TYPE, AC_PREREQ,\n  AC_SET_MAKE, AC_ENABLE.\n\n** Changed macros:\n* AC_FIND_X looks for X in more places.\n* AC_PROG_INSTALL defaults to install.sh instead of cp, if it's in srcdir.\n  install.sh is distributed with Autoconf.\n* AC_DECLARE_YYTEXT has been removed because it can't work, pending\n  a rewrite of quoting in AC_DEFINE.\n* AC_OUTPUT adds its comments in C format when substituting in C files.\n* AC_COMPILE_CHECK protects its ECHO-TEXT argument with double quotes.\n\n** New or changed command line options:\n* configure accepts --enable-FEATURE[=ARG] and --disable-FEATURE options.\n* configure accepts --without-PACKAGE, which sets withval=no.\n* configure accepts --x-includes=DIR and --x-libraries=DIR.\n* Giving --with-PACKAGE no argument sets withval=yes instead of withval=1.\n* configure accepts --help, --version, --silent/--quiet, --no-create options.\n* configure accepts and ignores most other Cygnus configure options, and\n  warns about unknown options.\n* config.status accepts --help, --version options.\n\n** File names and other changes:\n* Relative srcdir values are not made absolute.\n* The values of @prefix@ and @exec_prefix@ and @top_srcdir@ get substituted.\n* Autoconf library files are installed in ${datadir}/autoconf, not ${datadir}.\n* autoheader optionally copies config.h.top to the beginning of config.h.in.\n* The example Makefile dependencies for configure et al. work better.\n* Namespace cleanup: all shell variables used internally by Autoconf\n  have names beginning with `ac_'.\n\nMore big improvements are in process for future releases, but have not\nyet been (variously) finished, integrated, tested, or documented enough\nto release yet.\n\f\nMajor changes in Autoconf 1.7:\n\n* New macro AC_OBSOLETE.\n* Bugs in Makefile.in fixed.\n* AC_LONG_FILE_NAMES improved.\n\f\nMajor changes in Autoconf 1.6:\n\n* New macro AC_LONG_64_BITS.\n* Multiple .h files can be created.\n* AC_FIND_X looks for X files directly if it doesn't find xmkmf.\n* AC_ALLOCA defines C_ALLOCA if using alloca.c.\n* --with-NAME can take a value, e.g., --with-targets=sun4,hp300bsd.\n* Unused --no-create option to configure removed.\n* autoheader doesn't change the timestamp of its output file if\n  the file didn't change.\n* All macros that look for libraries now use AC_HAVE_LIBRARY.\n* config.status checks three optional environment variables to\n  modify its behavior.\n* The usual bug fixes.\n\f\nMajor changes in Autoconf 1.5:\n\n* New macros AC_FIND_X, AC_OFF_T, AC_STAT_MACROS_BROKEN, AC_REVISION.\n* autoconf and autoheader scripts have GNU standards conforming\n  --version and --help options (they print their message and exit).\n* Many bug fixes.\n\f\nMajor changes in Autoconf 1.4:\n\n* New macros AC_HAVE_POUNDBANG, AC_TIME_WITH_SYS_TIME, AC_LONG_DOUBLE,\n  AC_GETGROUPS_T, AC_DEFINE_UNQUOTED.\n* autoconf and autoheader use the M4 environment variable to determine the\n  name of the M4 program to use.\n* The --macrodir option to autoconf and autoheader specifies the directory\n  in which acspecific.m4, acgeneral.m4, etc. reside if not the default.\n* autoconf and autoheader can take `-' as their file names, which means to\n  read stdin as input.\n* Resulting configure scripts can take a --verbose option which causes them\n  to print the results of their tests.\n* AC_DEFINE quotes its second argument in such a way that spaces, magic\n  shell characters, etc. will be preserved during various stages of\n  expansion done by the shell.  If you don't want this, use\n  AC_DEFINE_UNQUOTED instead.\n* Much textual processing done with external calls to tr and sed have been\n  internalized with builtin M4 `patsubst' and `translit' calls.\n* AC_OUTPUT doesn't hardwire the file names it outputs.  Instead, you can\n  set the shell variables `gen_files' and `gen_config' to the list of\n  file names to output.\n* AC_DECLARE_YYTEXT does an AC_SUBST of `LEX_OUTPUT_ROOT', which may be\n  \"lex.yy\" or \"lexyy\", depending on the system.\n* AC_PROGRAMS_CHECK takes an optional third arg.  If given, it is used as\n  the default value.\n* If AC_ALLOCA chooses alloca.c, it also defines STACK_DIRECTION.\n* AC_CONST works much more reliably on more systems.\n* Many bug fixes.\n\f\nMajor changes in Autoconf 1.3:\n\nconfigure no longer requires awk for packages that use a config.h.\nSupport handling --with-PACKAGE options.\nNew `autoheader' script to create `config.h.in' from `configure.in'.\nIgnore troublesome -lucb and -lPW when searching for alloca.\nRename --exec_prefix to --exec-prefix for GNU standards conformance.\nImprove detection of STDC library.\nAdd AC_HAVE_LIBRARY to check for non-default libraries.\nFunction checking should work with future GNU libc releases.\n\f\nMajor changes in Autoconf 1.2:\n\nThe --srcdir option is now usually unnecessary.\nAdd a file containing sample comments describing CPP macros.\nA comment in config.status tells which host it was configured on.\nSubstituted variable values can now contain commas.\nFix bugs in various feature checks.\n\f\nMajor changes in Autoconf 1.1:\n\nAdded AC_STRCOLL macro.\nMade AC_GETLOADAVG check for more things.\nAC_OUTPUT argument is now optional.\nVarious bug fixes.\n\n-----\n\nCopyright (C) 1993-1996, 1998-2017, 2020-2021 Free Software Foundation,\nInc.\n\nCopying and distribution of this file, with or without modification,\nare permitted in any medium without royalty provided the copyright\nnotice and this notice are preserved.  This file is offered as-is,\nwithout warranty of any kind.\n\nLocal Variables:\nmode: outline\nEnd:\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/autoconf-2.71/README",
    "content": "-*- text -*-\n\nAutoconf\n\nAutoconf is an extensible package of M4 macros that produce shell\nscripts to automatically configure software source code packages.\nThese scripts can adapt the packages to many kinds of UNIX-like\nsystems without manual user intervention.  Autoconf creates a\nconfiguration script for a package from a template file that lists the\noperating system features that the package can use, in the form of M4\nmacro calls.\n\nProducing configuration scripts using Autoconf requires GNU M4 and\nPerl.  You should install GNU M4 (version 1.4.6 or later is required;\n1.4.14 or later is recommended) and Perl (5.006 or later) before\nconfiguring Autoconf, so that Autoconf's configure script can find\nthem.  The configuration scripts produced by Autoconf are\nself-contained, so their users do not need to have Autoconf (or GNU\nM4, Perl, etc.).\n\nYou can get GNU M4 here:\n\nhttps://ftp.gnu.org/gnu/m4/\n\nThe file INSTALL should be distributed with packages that use\nAutoconf-generated configure scripts and Makefiles that conform to the\nGNU coding standards.  The package's README can just give an overview\nof the package, where to report bugs, and a pointer to INSTALL for\ninstructions on compilation and installation.  This removes the need\nto maintain many similar sets of installation instructions.\n\nBe sure to read BUGS and INSTALL.\n\nMail suggestions to autoconf@gnu.org, report bugs to\nbug-autoconf@gnu.org, and submit patches to autoconf-patches@gnu.org.\nAll changes can be tracked at the read-only autoconf-commit@gnu.org.\nAlways include the Autoconf version number, which you can get by\nrunning `autoconf --version'.  Archives of bug-autoconf@gnu.org can be\nfound in <https://lists.gnu.org/archive/html/bug-autoconf/>, and\nsimilarly for the other mailing lists.\n\nLicensing\n\nAutoconf is released under the General Public License version 3 (GPLv3+).\nAdditionally, Autoconf includes a licensing exception in some of its\nsource files; see the respective copyright notices for how your\nproject is impacted by including scripts generated by Autoconf, and the\nCOPYING.EXCEPTION file for the exception in terms of the Additional\nPermissions as described in section 7 of GPLv3.\n\nFor more licensing information, see\n<https://www.gnu.org/licenses/gpl-faq.html> and\n<https://www.gnu.org/licenses/exceptions.html>.\n\nFor any copyright year range specified as YYYY-ZZZZ in this package\nnote that the range specifies every single year in that closed interval.\n\n-----\n\nCopyright (C) 1992-1994, 1998, 2000-2017, 2020-2021 Free Software\nFoundation, Inc.\n\nCopying and distribution of this file, with or without modification,\nare permitted in any medium without royalty provided the copyright\nnotice and this notice are preserved.  This file is offered as-is,\nwithout warranty of any kind.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/autoconf-2.71/THANKS",
    "content": "GNU Autoconf THANKS file\n\nGNU Autoconf was originally written by David J. MacKenzie.  It would\nnot be what it is today without the invaluable help of these people,\nwho have reported problems, suggested improvements, or submitted\nactual code.  Please help us keep this list complete and free from\nerrors.  Also see the AUTHORS file for the list of people with\ncontributions significant enough to warrant copyright assignment.\n\nAaron Crane                 aaronc@pobox.com\nAaron M. Ucko               amu@alum.mit.edu\nAaron W. LaFramboise        aaronenvelope277@aaronwl.com\nAdam J. Richter             adam@yggdrasil.com\nAdrian Bunk                 bunk@stusta.de\nAharon Robbins              arnold@gnu.org\nAkim Demaille               akim@freefriends.org\nAkinori Musha               knu@iDaemons.org\nAlain Knaff                 Alain.Knaff@imag.fr\nAlbert Chin-A-Young         china@thewrittenword.com\nAlec Wolman                 wolman@cs.washington.edu\nAlex Unleashed              unledev@gmail.com\nAlexander Kurz              alexander.kurz@qsc.de\nAlexander Mai               ?\nAlexander Pletzer           pletzer@txcorp.com\nAlexandre Duret-Lutz        duret_g@epita.fr\nAlexandre Julliard          ?\nAlexandre Oliva             oliva@lsd.ic.unicamp.br\nAlfred G. de Wijn           dwijn@iluvatar.eu.org\nAlfred M. Szmidt            ams@gnu.org\nAllan Caffee                allan.caffee@gmail.com\nAllan Clark                 allanc@chickenandporn.com\nAnaïs Bouque                anais.bouque@fr.thalesgroup.com\nAnders Kaseorg              andersk@MIT.EDU\nAndreas Buening             andreas.buening@nexgo.de\nAndreas Jaeger              aj@suse.de\nAndreas Schott              schott@rzg.mpg.de\nAndreas Schwab              schwab@linux-m68k.org\nAndreas Waechter            andreasw@watson.ibm.com\nAndrej Borsenkow            borsenkow.msk@sni.de\nAndrew Belov                ?\nAndrew Church               achurch@achurch.org\nAndrey Simonenko            simon@comsys.ntu-kpi.kiev.ua\nAndris Pavenis              andris.pavenis@iki.fi\nAnthony N. Frasso           afrasso@yahoo.com\nArkadiusz Miskiewicz        arekm@maven.pl\nArt Haas                    ahaas@neosoft.com\nArto C. Nirkko              ?\nArtur Frysiak               wiget@pld.org.pl\nAssar Westerlund            assar@sics.se\nAxel Thimm                  Axel.Thimm@physik.fu-berlin.de\nBart Oldeman                bartoldeman@users.sourceforge.net\nBen Elliston                bje@redhat.com\nBen Pfaff                   pfaffben@debian.org\nBenoit Sigoure              tsunanet@gmail.com\nBill Moseley                moseley@hank.org\nBill Northcott              w.northcott@unsw.edu.au\nBill Sommerfeld             sommerfeld@apollo.hp.com\nBJ Terry                    bjterry@gmail.com\nBob Friesenhahn             bfriesen@simple.dallas.tx.us\nBob Proulx                  bob@proulx.com\nBob Rossi                   bob_rossi@cox.net\nBob Wilson                  bwilson@tensilica.com\nBrad Walker                 me@bradmwalker.com\nBraden McDaniel             braden@endoframe.com\nBram Moolenaar              bram@vim.org\nBrian Gough                 bjg@network-theory.co.uk\nBrian J. Murrell            brian@sun.com\nBruce Dugan                 bld0401@gmail.com\nBruce Korb                  bkorb@gnu.org\nBruce Lilly                 ?\nBruno Haible                haible@ilog.fr\nBjörn Lindqvist             bjourne@gmail.com\nCarl Edman                  cedman@princeton.edu\nCarlos Velasco              carlosev@newipnet.com\nChad R. Larson              chad@anasazi.com\nCharles 'Buck' Krasic       krasic@cs.ubc.ca\nChikama Masaki              masaki.chikama@gmail.com\nChris P. Ross               cross@uu.net\nChris Pickett               chris.pickett@mail.mcgill.ca\nChris Provenzano            proven@cygnus.com\nChris Torek                 torek@bsdi.com\nChristian Cornelssen        ccorn@cs.tu-berlin.de\nChristian Krackowizer       ckrackowiz@std.schuler-ag.com\nChristian Krone             krischan@sql.de\nChristian Rössel            christian.roessel@gmx.de\nChristophe Jarry            christophe.jarry@ouvaton.org\nChristopher Hulbert         cchgroupmail@gmail.com\nChristopher Lee             chrislee@ri.cmu.edu\nClinton Roy                 clinton.roy@gmail.com\nColin Watson                cjwatson@debian.org\nCorinna Vinschen            corinna-cygwin@cygwin.com\nCort Dougan                 cort@cs.nmt.edu\nD'Arcy A MacIsaac           ?\nDalibor Topic               robilad@kaffe.org\nDan Manthey                 dan_manthey@partech.com\nDaniel Carroll              dan@mesastate.edu\nDaniel Jacobowitz           drow@mvista.com\nDaniel Reed                 ?\nDaniele Arena               daniele@ripe.net\nDave Adams                  adams@hpesdwa.fc.hp.com\nDave Erickson               retrorandomaccess@hotmail.com\nDave Korn                   dave.korn.cygwin@googlemail.com\nDave Love                   fx@gnu.org\nDavid Byron                 dbyron@hheld.com\nDavid Carter                david@carter.net\nDavid Cournapeau            david@ar.media.kyoto-u.ac.jp\nDavid Fang                  fang@csl.cornell.edu\nDavid Hill                  dhill@mindcry.org\nDavid J. MacKenzie          djm@uunet.uu.net\nDavid M. Lloyd              dmlloyd@tds.net\nDavid Morgan                dmorgan@symark.com\nDavie Reiss                 dreiss@facebook.com\nDavid Relson                relson@osagesoftware.com\nDennis J. Linse             ?\nDerek R. Price              derek.price@openavenue.com\nDidier Desseaux             didess@infonie.fr\nDidier Verna                didier@xemacs.org\nDieter Jurzitza             dieter.jurzitza@t-online.de\nDietmar P. Schindler        schd@mra.man.de\nDmitry Grebeniuk            gdsfh1@gmail.com\nDoug Evans                  dje@canuck.cygnus.com\nDries Kimpe                 ?\nDustin J. Mitchell          dustin@zmanda.com\nEdouard Bechetoille         ebecheto@ens-lyon.fr\nElbert Pol                  elbert.pol@gmail.com\nEli Zaretskii               eliz@gnu.org\nElias Pipping               pipping@macports.org\nEnrique Robledo Arnuncio    enrique.robledo@wanadoo.es\nErez Zadok                  ezk@cs.columbia.edu\nEric Backus                 ericb@lsid.hp.com\nEric Blake                  ebb9@byu.net\nEric Lemings                lemings@roguewave.com\nEric Mumpower               nocturne@mit.edu\nEric Paire                  ?\nEric Sunshine               sunshine@sunshineco.com\nEzra Peisach                epeisach@zif.mit.edu\nFedor Sergeev               ?\nFelix Lee                   flee@cygnus.com\nFernando Carrijo            fcarrijo@freedesktop.org\nFranceseco Romani           fromani@gmail.com\nFrank Denis                 j@jedi.claranet.fr\nFrançois Pinard             pinard@iro.umontreal.ca\nFred Kreek                  Fred.Kreek@kadaster.nl\nFrederik Fouvry             fouvry@CoLi.Uni-SB.DE\nGareth McCaughan            gareth.mccaughan@pobox.com\nGary V. Vaughan             gvaughan@oranda.demon.co.uk\nGeir Ove Myhr               myhr@stud.fim.ntnu.no\nGerrit P. Haase             gp@familiehaase.de\nGideon Go                   gideon.go@gmail.com\nGiorgos Keramidas           gkeramidas@gmail.com\nGiuseppe Guerrini           guisguerrini@racine.ra.it\nGlenn P. Davis              davis@unidata.ucar.edu\nGodmar Back                 gback@cs.utah.edu\nGordon Matzigkeit           gord@trick.fig.org\nGraham Jenkins              c714553@vus415.telstra.com.au\nGreg A. Woods               woods@weird.com\nGreg Schafer                gschafer@zip.com.au\nGregorio Guidi              ?\nGregory Giannoni            sand@narguile.org\nGiulio Paci                 giuliopaci@interfree.it\nGuido Draheim               Guido.Draheim@gmx.de\nGuido Flohr                 gufl0000@stud.uni-sb.de\nGuido van Rossum            ?\nGuillermo Gomez             gomez@mi.uni-erlangen.de\nH. Merijn Brand             h.m.brand@hccnet.nl\nH. Peter Anvin              ?\nH.J. Lu                     hjl@gnu.org\nHallvard B Furuseth         h.b.furuseth@usit.uio.no\nHans Aberg                  haberg@math.su.se\nHans Olsson                 Hans.Olsson@dna.lth.se\nHans Ulrich Niedermann      hun@n-dimensional.de\nHarlan Stenn                stenn@whimsy.udel.edu\nHeiko Schlichting           inn-workers@fu-berlin.de\nHenk Krus                   h.krus@cyclone.nl\nHoward Chu                  hyc@highlandsun.com\nIan Lance Taylor            ian@cygnus.com\nIan Macdonald               iamacdo@telkomsa.net\nIan Redfern                 Ian.Redfern@logicacmg.com\nIlya Bobir                  ilya.bobir@gmail.com\nIlya Zakharevich            ilya@Math.Berkeley.EDU\nIneiev                      ineiev@yahoo.co.uk\nIohannes m zmoelnig         zmoelnig@iem.at\nJ C Fitzgerald              v7022@wave.co.nz\nJaap Haitsma                jaap@haitsma.org\nJames A. Lupo               lupoja@feynman.ml.wpafb.af.mil\nJan Madzik                  jmadzik@gmail.com\nJason Molenda               jsm@cygnus.com\nJeff Garzik                 jgarzik@pobox.com\nJeff Painter                ?\nJeff Squyres                jsquyres@cisco.com\nJeffrey A Law               law@cygnus.com\nJeffrey J. Barteet          ?\nJennis Pruett               ?\nJens Petersen               petersen@redhat.com\nJens Schmidt                jens.schmidt35@arcor.de\nJeremy Yallop               jeremy@yallop.org\nJerker Bäck                 jerker.back@home.se\nJim Blandy                  jimb@wookumz.gnu.ai.mit.edu\nJim Meyering                meyering@ascend.com\nJim Warhol                  jrw@jwarhol.com\nJiro Takabatake             jiro@din.or.jp\nJochen Friedrich            jochen@scram.de\nJoel E. Denny               jdenny@ces.clemson.edu\nJoel James Adamson          joel@chondestes.bio.unc.edu\nJoey Mingrone               joey@mingrone.org\nJohan Danielsson            joda@pdc.kth.se\nJohn Calcote                john.calcote@gmail.com\nJohn David Anglin           dave@hiauly1.hia.nrc.ca\nJohn Fortin                 fortinj@attglobal.net\nJohn Interrante             interran@uluru.stanford.edu\nJohn R. Cary                cary@txcorp.com\nJohn W. Eaton               jwe@bevo.che.wisc.edu\nJonathan Kamens             jik@kamens.brookline.ma.us\nJonathan Lebon              jlebon@redhat.com\nJosef Tran                  josef@timetrackertechnology.com\nJosef Vukovic               josefvukovic@googlemail.com\nJoseph S. Myers             jsm28@cam.ac.uk\nJoshua G. Hale              jgh.emc@gmail.com\nJuan Carlos Hurtado         adso.lists@gmail.com\nJules Colding               colding@42tools.com\nJulian C. Cummings          cummings@cacr.caltech.edu\nJulian Onions               j.onions@nexor.co.uk\nJulien Danjou               acid@debian.org\nJulien Élie                 julien@trigofacile.com\nJulio Garvia                ?\nJustace Clutter             ?\nJörn Rennecke               amylaar@cygnus.co.uk\nKarl Berry                  karl@cs.umb.edu\nKarl Heuer                  kwzh@gnu.org\nKarsten Hopp                karsten@redhat.com\nKate Hedstrom               ?\nKathryn Hargreaves          kathryn@deas.harvard.edu\nKaveh R. Ghazi              ghazi@caip.rutgers.edu\nKeith Bostic                bostic@abyssinian.sleepycat.com\nKeith Marshall              keith.marshall@total.com\nKelly Anderson              tgcorp@attglobal.net\nKen Pizzini                 ken@halcyon.com\nKen Raeburn                 raeburn@cygnus.com\nKevin Ryde                  user42@zip.com.au\nKlee Dienes                 kdienes@apple.com\nKoji Arai                   JCA02266@nifty.ne.jp\nKristian Kvilekval          kris@cs.ucsb.edu\nKřištof Želechovski         giecrilj@stegny.2a.pl\nKurt D. Zeilenga            kurt@openldap.org\nLarry Jones                 larry.jones@sdrc.com\nLarry Schmitt               larry@mail.haleakalawebdesigns.com\nLarry Schwimmer             rosebud@cyclone.stanford.edu\nLars Hecking                lhecking@nmrc.ucc.ie\nLars J. Aas                 larsa@sim.no\nLaurence Darbe              ldarby@tuffmail.com\nLeo Moisio                  leo.moisio@gmail.com\nLoulou Pouchet              loulou@lrde.epita.fr\nLuc Maisonobe               luc@spaceroots.org\nLudovic Courtes             ?\nLuke Dalessandro            luked@cs.rochester.edu\nMagnus Therning             therning@gforge.natlab.research.philips.com\nManu                        manubee@wanadoo.fr\nMarc Espie                  Marc.Espie@liafa.jussieu.fr\nMarcus Brinkmann            ?\nMarcus Daniels              marcus@sysc.pdx.edu\nMarcus Thiessel             marcus@xemacs.org\nMark Cave-Ayland            ?\nMark D. Baushke             ?\nMark D. Roth                ?\nMark Elbrecht               snowball3@usa.net\nMark Hessling               mark@rexx.org\nMark Kettenis               kettenis@gnu.org\nMarkku Savela               msa@msa.tte.vtt.fi\nMarkus Oberhumer            markus.oberhumer@jk.uni-linz.ac.at\nMarkus Geimer               m.geimer@fz-juelich.de\nMartin Buchholz             martin@xemacs.org\nMartin Costabel             costabel@wanadoo.fr\nMartin Frydl                martin@systinet.com\nMartin Koeppe               mkoeppe@gmx.de\nMartin Mokrejs              mmokrejs@natur.cuni.cz\nMartin Wilck                martin@tropos.de\nMartyn Johnson              Martyn.Johnson@cl.cam.ac.uk\nMatěj Týč                   matej.tyc@gmail.com\nMatt Kraai                  kraai@ftbfs.org\nMatteo Frigo                ?\nMatthew D. Langston         langston@SLAC.Stanford.EDU\nMatthew Mueller             donut@azstarnet.com\nMatthew Woehlke             mw_triad@users.sourceforge.net\nMatthias Andree             matthias.andree@gmx.de\nMichal Čihař                nijel@debian.org\nMichael Elizabeth Chastain  chastain@cygnus.com\nMichael Jenning             ?\nMichael Matz                matz@kde.org\nMichael Schoene             mrs@mlc.de\nMichael Wardle              ?\nMike Frysinger              vapier@gentoo.org\nMike Hopkirk                hops@sco.com\nMike Stump                  mrs@wrs.com\nMikulas Patocka             ?\nMiles Bader                 miles@gnu.ai.mit.edu\nMo DeJong                   mdejong@cygnus.com\nMomchil Velkov              velco@fadata.bg\nMonty Taylor                mordred@inaugust.com\nMorten Eriksen              mortene@sim.no\nMostafa                     mostafa_working_away@yahoo.com\nMotoyuki Kasahara           m-kasahr@sra.co.jp\nNathan Schulte              reklipz@gmail.com\nNathanael Nerode            neroden@gcc.gnu.org\nNelson H. F. Beebe          beebe@math.utah.edu\nNicolas Joly                njoly@pasteur.fr\nNicolás Lichtmaier          jnl@synapsis-sa.com.ar\nNick Bowler                 nbowler@draconx.ca\nNightStrike                 nightstrike@gmail.com\nNishio Futoshi              fut_nis@d3.dion.ne.jp\nNoah Elliott                elliott@hera.llnl.gov\nNoah Friedman               friedman@gnu.ai.mit.edu\nNoah Misch                  noah@cs.caltech.edu\nNoel Grandin                noel@peralex.com\nNorman Gray                 ?\nOlaf Lenz                   olenz@fias.uni-frankfurt.de\nOle Holm Nielsen            Ole.H.Nielsen@fysik.dtu.dk\nOliver Kiddle               opk@zsh.org\nOlly Betts                  olly@survex.com\nOssama Othman               ossama@debian.org\nPallav Gupta                pallavgupta@gmail.com\nPaolo Bonzini               bonzini@gnu.org\nPatrice Dumas               pertusus@free.fr\nPatrick Tullmann            tullmann@cs.utah.edu\nPatrick Welche              prlw1@newn.cam.ac.uk\nPaul Berrevoets             paul@swi.com\nPaul D. Smith               psmith@gnu.org\nPaul Eggert                 eggert@cs.ucla.edu\nPaul Gampe                  paulg@apnic.net\nPaul Jarc                   prj@po.cwru.edu\nPaul Martinolich            martinol@datasync.com\nPaul Pogonyshev             ?\nPaul Townsend               ?\nPavel Roskin                pavel_roskin@geocities.com\nPádraig Brady               P@draigbrady.com\nPer Øyvind Karlsen          peroyvind@mandriva.org\nPeter Breitenlohner         peb@mppmu.mpg.de\nPeter Eisentraut            peter_e@gmx.net\nPeter Hendrickson           pdh@wiredyne.com\nPeter Johansson             trojkan@gmail.com\nPeter O'Gorman              peter@pogma.com\nPeter Palfrader             weasel@debian.org\nPeter Simons                simons@cryp.to\nPeter Stephenson            pws@csr.com\nPhilipp Thomas              kthomas@gwdg.de\nPhilippe De Muyter          ?\nPierre                      pierre42d@9online.fr\nPierre Ynard                linkfanel@yahoo.fr\nPontus Skoeld               pont@soua.net\nRainer Orth                 ro@TechFak.Uni-Bielefeld.DE\nRaja R Harinath             harinath@cs.umn.edu\nRalf Corsepius              corsepiu@faw.uni-ulm.de\nRalf Menzel                 menzel@ls6.cs.uni-dortmund.de\nRalf S. Engelschall         rse@engelschall.com\nRalf Wildenhues             Ralf.Wildenhues@gmx.de\nRandall Cotton              recotton@earthlink.net\nReuben Thomas               rrt@sc3d.org\nRichard Dawe                rich@phekda.freeserve.co.uk\nRichard Stallman            rms@gnu.org\nRobert Lipe                 robertlipe@usa.net\nRobert S. Maier             rsm@math.arizona.edu\nRoberto Bagnara             bagnara@cs.unipr.it\nRochan                      rochan@ices.utexas.edu\nRoger Leigh                 rleigh@whinlatter.ukfsn.org\nRoland McGrath              roland@gnu.org\nRolf Ebert                  rolf.ebert.gcc@gmx.de\nRolf Vandevaart             Rolf.Vandevaart@sun.com\nRomain Lenglet              romain.lenglet@laposte.net\nRuediger Kuhlmann           info@ruediger-kuhlmann.de\nRugxulo                     rugxulo@gmail.com\nRuslan Babayev              ruslan@babayev.com\nRuss Allbery                rra@stanford.edu\nRuss Boylan                 ross@biostat.ucsf.edu\nRyuji Abe                   raeva@t3.rim.or.jp\nSam Sexton                  Sam.Sexton@reuters.com\nSam Sirlin                  sam@kalessin.jpl.nasa.gov\nSam Steingold               sds@gnu.org\nSam Varshavchik             mrsam@courier-mta.com\nSander Niemeijer            niemeijer@science-and-technology.nl\nsantilín                    listas@gestiong.org\nScott Bambrough             scottb@corelcomputer.com\nScott McCreary              scottmc2@gmail.com\nScott Stanton               stanton@scriptics.com\nSebastian Freundt           hroptatyr@gna.org\nSergey Poznyakoff           ?\nSimon Josefsson             jas@extundo.com\nSimon Leinen                simon@lia.di.epfl.ch\nSlava Sysoltsev             Viatcheslav.Sysoltsev@h-d-gmbh.de\nStefan Seefeld              stefan@codesourcery.com\nStefan `Sec' Zehl           ?\nStefano Lattarini           stefano.lattarini@gmail.com\nStepan Kasal                kasal@ucw.cz\nStéphane Chazelas           Stephane_Chazelas@yahoo.fr\nStephen Gildea              filtered@against.spam\nStephen Rasku               srasku@mail.tantalus-systems.com\nStephen P. Schaefer         sschaefer@acm.org\nSteve Chamberlain           sac@cygnus.com\nSteve Goetze                goetze@dovetail.com\nSteve Huston                shuston@riverace.com\nSteve Robbins               steve@nyongwa.montreal.qc.ca\nSteven G. Johnson           stevenj@alum.mit.edu\nSteven R. Loomis            srl@icu-project.org\nStu Grossman                grossman@cygnus.com\nSumit Pandya                sumit@elitecore.com\nSyd Polk                    spolk@cygnus.com\nT.E. Dickey                 dickey@clark.net\nTed Bullock                 tbullock@canada.com\nTheodore Ts'o               tytso@mit.edu\nThien-Thi Nguyen            ttn@gnu.org\nThomas Jahns                jahns@dkrz.de\nThomas Winder               tom@vlsivie.tuwien.ac.at\nTim Freeman                 tim@fungible.com\nTim Mooney                  mooney@dogbert.cc.ndsu.NoDak.edu\nTim Rice                    tim@multitalents.net\nTim Van Holder              tim.van.holder@pandora.be\nTobias Burnus               burnus@net-b.de\nTom Browder                 tom.browder@gmail.com\nTom Epperly                 tepperly@llnl.gov\nTom Lane                    tgl@sss.pgh.pa.us\nTom Purcell                 Tom.Purcell@wang.com\nTom Tromey                  tromey@cygnus.com\nTom Yu                      tlyu@mit.edu\nTomohiro Suzuki             ?\nTony Leneis                 tony@plaza.ds.adp.com\nToshio Kuratomi             ?\nUwe Seimet                  us@orbacus.com\nVáclav Haisman              v.haisman@sh.cvut.cz\nVance Shipley               vances@motivity.ca\nViktor Dukhovni             viktor@anaheim.esm.com\nVille Karaila               karaila@iki.fi\nVincent Lefèvre             vincent@vinc17.org\nVincent Torri               vtorri at univ-evry.fr\nVladimir Volovich           vvv@vsu.ru\nVolker Borchert             bt@teknon.de\nWayne Chapeskie             waynec@spinnaker.com\nWerner Lemberg              wl@gnu.org\nWilfredo Sanchez            wsanchez@apple.com\nWilliam Pursell             bill.pursell@gmail.com\nWiseman Jun                 junwiseman@gmail.com\nWolfgang Mueller            Wolfgang.Mueller@cui.unige.ch\nYaakov Selkowitz            yselkowitz@users.sourceforge.net\nYavor Doganov               yavor@gnu.org\nYury Puhalsky               pooh@cryptopro.ru\nZack Weinberg               zack@codesourcery.com\n?                           Seanster@Seanster.com\n\nMany people are not named here because we lost track of them.  We\nthank them!  Please, help us keep this list up to date.\n\n================\n\nLocal Variables:\nmode: text\ncoding: utf-8\nEnd:\n\nCopyright (C) 1999-2017, 2020-2021 Free Software Foundation, Inc.\n\nThis program is free software: you can redistribute it and/or modify\nit under the terms of the GNU General Public License as published by\nthe Free Software Foundation, either version 3 of the License, or\n(at your option) any later version.\n\nThis program is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\nGNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License\nalong with this program.  If not, see <https://www.gnu.org/licenses/>.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/automake-1.16.5/AUTHORS",
    "content": "Authors of GNU Automake.\n\nDavid Mackenzie\n  First version of most \".am\" files.\n  Wrote sh version of automake.in.\n\nTom Tromey\n  Touched all \".am\" files.\n  Rewrote automake.in\n\nAlexandre Oliva\n  Some of the user-side dependency tracking system.\n  Some more random hacking.\n\nAlexandre Duret-Lutz\n  Major overhaul of everything.\n  Maintenance since 2002.\n\nRalf Wildenhues\n  Random breakage.\n  Maintenance since 2006.\n\nStefano Lattarini\n  Testsuite overhaul.\n  TAP support and custom testsuite drivers.\n  Random breakage.\n  De-facto maintenance since 2012.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/automake-1.16.5/COPYING",
    "content": "\t\t    GNU GENERAL PUBLIC LICENSE\n\t\t       Version 2, June 1991\n\n Copyright (C) 1989, 1991 Free Software Foundation, Inc.,\n 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n\t\t\t    Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  By contrast, the GNU General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users.  This\nGeneral Public License applies to most of the Free Software\nFoundation's software and to any other program whose authors commit to\nusing it.  (Some other Free Software Foundation software is covered by\nthe GNU Lesser General Public License instead.)  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthis service if you wish), that you receive source code or can get it\nif you want it, that you can change the software or use pieces of it\nin new free programs; and that you know you can do these things.\n\n  To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have.  You must make sure that they, too, receive or can get the\nsource code.  And you must show them these terms so they know their\nrights.\n\n  We protect your rights with two steps: (1) copyright the software, and\n(2) offer you this license which gives you legal permission to copy,\ndistribute and/or modify the software.\n\n  Also, for each author's protection and ours, we want to make certain\nthat everyone understands that there is no warranty for this free\nsoftware.  If the software is modified by someone else and passed on, we\nwant its recipients to know that what they have is not the original, so\nthat any problems introduced by others will not reflect on the original\nauthors' reputations.\n\n  Finally, any free program is threatened constantly by software\npatents.  We wish to avoid the danger that redistributors of a free\nprogram will individually obtain patent licenses, in effect making the\nprogram proprietary.  To prevent this, we have made it clear that any\npatent must be licensed for everyone's free use or not licensed at all.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n\t\t    GNU GENERAL PUBLIC LICENSE\n   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n  0. This License applies to any program or other work which contains\na notice placed by the copyright holder saying it may be distributed\nunder the terms of this General Public License.  The \"Program\", below,\nrefers to any such program or work, and a \"work based on the Program\"\nmeans either the Program or any derivative work under copyright law:\nthat is to say, a work containing the Program or a portion of it,\neither verbatim or with modifications and/or translated into another\nlanguage.  (Hereinafter, translation is included without limitation in\nthe term \"modification\".)  Each licensee is addressed as \"you\".\n\nActivities other than copying, distribution and modification are not\ncovered by this License; they are outside its scope.  The act of\nrunning the Program is not restricted, and the output from the Program\nis covered only if its contents constitute a work based on the\nProgram (independent of having been made by running the Program).\nWhether that is true depends on what the Program does.\n\n  1. You may copy and distribute verbatim copies of the Program's\nsource code as you receive it, in any medium, provided that you\nconspicuously and appropriately publish on each copy an appropriate\ncopyright notice and disclaimer of warranty; keep intact all the\nnotices that refer to this License and to the absence of any warranty;\nand give any other recipients of the Program a copy of this License\nalong with the Program.\n\nYou may charge a fee for the physical act of transferring a copy, and\nyou may at your option offer warranty protection in exchange for a fee.\n\n  2. You may modify your copy or copies of the Program or any portion\nof it, thus forming a work based on the Program, and copy and\ndistribute such modifications or work under the terms of Section 1\nabove, provided that you also meet all of these conditions:\n\n    a) You must cause the modified files to carry prominent notices\n    stating that you changed the files and the date of any change.\n\n    b) You must cause any work that you distribute or publish, that in\n    whole or in part contains or is derived from the Program or any\n    part thereof, to be licensed as a whole at no charge to all third\n    parties under the terms of this License.\n\n    c) If the modified program normally reads commands interactively\n    when run, you must cause it, when started running for such\n    interactive use in the most ordinary way, to print or display an\n    announcement including an appropriate copyright notice and a\n    notice that there is no warranty (or else, saying that you provide\n    a warranty) and that users may redistribute the program under\n    these conditions, and telling the user how to view a copy of this\n    License.  (Exception: if the Program itself is interactive but\n    does not normally print such an announcement, your work based on\n    the Program is not required to print an announcement.)\n\nThese requirements apply to the modified work as a whole.  If\nidentifiable sections of that work are not derived from the Program,\nand can be reasonably considered independent and separate works in\nthemselves, then this License, and its terms, do not apply to those\nsections when you distribute them as separate works.  But when you\ndistribute the same sections as part of a whole which is a work based\non the Program, the distribution of the whole must be on the terms of\nthis License, whose permissions for other licensees extend to the\nentire whole, and thus to each and every part regardless of who wrote it.\n\nThus, it is not the intent of this section to claim rights or contest\nyour rights to work written entirely by you; rather, the intent is to\nexercise the right to control the distribution of derivative or\ncollective works based on the Program.\n\nIn addition, mere aggregation of another work not based on the Program\nwith the Program (or with a work based on the Program) on a volume of\na storage or distribution medium does not bring the other work under\nthe scope of this License.\n\n  3. You may copy and distribute the Program (or a work based on it,\nunder Section 2) in object code or executable form under the terms of\nSections 1 and 2 above provided that you also do one of the following:\n\n    a) Accompany it with the complete corresponding machine-readable\n    source code, which must be distributed under the terms of Sections\n    1 and 2 above on a medium customarily used for software interchange; or,\n\n    b) Accompany it with a written offer, valid for at least three\n    years, to give any third party, for a charge no more than your\n    cost of physically performing source distribution, a complete\n    machine-readable copy of the corresponding source code, to be\n    distributed under the terms of Sections 1 and 2 above on a medium\n    customarily used for software interchange; or,\n\n    c) Accompany it with the information you received as to the offer\n    to distribute corresponding source code.  (This alternative is\n    allowed only for noncommercial distribution and only if you\n    received the program in object code or executable form with such\n    an offer, in accord with Subsection b above.)\n\nThe source code for a work means the preferred form of the work for\nmaking modifications to it.  For an executable work, complete source\ncode means all the source code for all modules it contains, plus any\nassociated interface definition files, plus the scripts used to\ncontrol compilation and installation of the executable.  However, as a\nspecial exception, the source code distributed need not include\nanything that is normally distributed (in either source or binary\nform) with the major components (compiler, kernel, and so on) of the\noperating system on which the executable runs, unless that component\nitself accompanies the executable.\n\nIf distribution of executable or object code is made by offering\naccess to copy from a designated place, then offering equivalent\naccess to copy the source code from the same place counts as\ndistribution of the source code, even though third parties are not\ncompelled to copy the source along with the object code.\n\n  4. You may not copy, modify, sublicense, or distribute the Program\nexcept as expressly provided under this License.  Any attempt\notherwise to copy, modify, sublicense or distribute the Program is\nvoid, and will automatically terminate your rights under this License.\nHowever, parties who have received copies, or rights, from you under\nthis License will not have their licenses terminated so long as such\nparties remain in full compliance.\n\n  5. You are not required to accept this License, since you have not\nsigned it.  However, nothing else grants you permission to modify or\ndistribute the Program or its derivative works.  These actions are\nprohibited by law if you do not accept this License.  Therefore, by\nmodifying or distributing the Program (or any work based on the\nProgram), you indicate your acceptance of this License to do so, and\nall its terms and conditions for copying, distributing or modifying\nthe Program or works based on it.\n\n  6. Each time you redistribute the Program (or any work based on the\nProgram), the recipient automatically receives a license from the\noriginal licensor to copy, distribute or modify the Program subject to\nthese terms and conditions.  You may not impose any further\nrestrictions on the recipients' exercise of the rights granted herein.\nYou are not responsible for enforcing compliance by third parties to\nthis License.\n\n  7. If, as a consequence of a court judgment or allegation of patent\ninfringement or for any other reason (not limited to patent issues),\nconditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot\ndistribute so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you\nmay not distribute the Program at all.  For example, if a patent\nlicense would not permit royalty-free redistribution of the Program by\nall those who receive copies directly or indirectly through you, then\nthe only way you could satisfy both it and this License would be to\nrefrain entirely from distribution of the Program.\n\nIf any portion of this section is held invalid or unenforceable under\nany particular circumstance, the balance of the section is intended to\napply and the section as a whole is intended to apply in other\ncircumstances.\n\nIt is not the purpose of this section to induce you to infringe any\npatents or other property right claims or to contest validity of any\nsuch claims; this section has the sole purpose of protecting the\nintegrity of the free software distribution system, which is\nimplemented by public license practices.  Many people have made\ngenerous contributions to the wide range of software distributed\nthrough that system in reliance on consistent application of that\nsystem; it is up to the author/donor to decide if he or she is willing\nto distribute software through any other system and a licensee cannot\nimpose that choice.\n\nThis section is intended to make thoroughly clear what is believed to\nbe a consequence of the rest of this License.\n\n  8. If the distribution and/or use of the Program is restricted in\ncertain countries either by patents or by copyrighted interfaces, the\noriginal copyright holder who places the Program under this License\nmay add an explicit geographical distribution limitation excluding\nthose countries, so that distribution is permitted only in or among\ncountries not thus excluded.  In such case, this License incorporates\nthe limitation as if written in the body of this License.\n\n  9. The Free Software Foundation may publish revised and/or new versions\nof the General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\nEach version is given a distinguishing version number.  If the Program\nspecifies a version number of this License which applies to it and \"any\nlater version\", you have the option of following the terms and conditions\neither of that version or of any later version published by the Free\nSoftware Foundation.  If the Program does not specify a version number of\nthis License, you may choose any version ever published by the Free Software\nFoundation.\n\n  10. If you wish to incorporate parts of the Program into other free\nprograms whose distribution conditions are different, write to the author\nto ask for permission.  For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this.  Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n\t\t\t    NO WARRANTY\n\n  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\nREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\nINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\nOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\nYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\nPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGES.\n\n\t\t     END OF TERMS AND CONDITIONS\n\n\t    How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software; you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation; either version 2 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License along\n    with this program; if not, write to the Free Software Foundation, Inc.,\n    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n\nAlso add information on how to contact you by electronic and paper mail.\n\nIf the program is interactive, make it output a short notice like this\nwhen it starts in an interactive mode:\n\n    Gnomovision version 69, Copyright (C) year name of author\n    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, the commands you use may\nbe called something other than `show w' and `show c'; they could even be\nmouse-clicks or menu items--whatever suits your program.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the program, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the program\n  `Gnomovision' (which makes passes at compilers) written by James Hacker.\n\n  <signature of Ty Coon>, 1 April 1989\n  Ty Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into\nproprietary programs.  If your program is a subroutine library, you may\nconsider it more useful to permit linking proprietary applications with the\nlibrary.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/automake-1.16.5/NEWS",
    "content": "For planned incompatibilities in a future Automake 2.0 release,\nplease see NEWS-2.0 and start following the advice there now.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.16.5:\n\n* Bugs fixed\n\n  - PYTHON_PREFIX and PYTHON_EXEC_PREFIX are now set according to\n    Python's sys.* values only if the new configure option\n    --with-python-sys-prefix is specified. Otherwise, GNU default values\n    are used, as in the past. (The change in 1.16.3 was too incompatible.)\n\n  - consistently depend on install-libLTLIBRARIES.\n\n* Distribution\n\n  - use const for yyerror declaration in bison/yacc tests.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.16.4:\n\n* New features added\n\n  - The PYTHON_PREFIX and PYTHON_EXEC_PREFIX variables are now set from\n    Python's sys.prefix and sys.exec_prefix; use the new configure options\n    --with-python_prefix and --with-python_exec_prefix to specify explicitly.\n\n  - Common top-level files can be provided as .md; the non-md version is\n    used if both are present:\n      AUTHORS ChangeLog INSTALL NEWS README README-alpha THANKS\n\n  - CTAGS, ETAGS, SCOPE variables can be set via configure.\n\n  - Silent make output for custom link commands.\n\n  - New option \"no-dist-built-sources\" skips generating $(BUILT_SOURCES)\n    before building the tarball as part of \"make dist\", that is,\n    omits the dependency of $(distdir): $(BUILT_SOURCES).\n\n* Bugs fixed\n\n  - automake output more reproducible.\n\n  - test-driver less likely to clash with tests writing to the same file.\n\n  - DejaGnu tests always use the directory name, testsuite/, for\n    compatibility with the newer dejagnu-1.6.3 and with prior versions.\n\n* Distribution\n\n  - config.sub and config.guess updates include restoration of `...`\n    for maximum portability.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.16.3:\n\n* New features added\n\n  - In the testsuite summary, the \"for $(PACKAGE_STRING)\" suffix\n    can be overridden with the AM_TESTSUITE_SUMMARY_HEADER variable.\n\n* Bugs fixed\n\n  - Python version number 3.10 no longer considered to be 3.1.\n\n  - Broken links in manual fixed or removed, and new script\n    contrib/checklinkx (a small modification of W3C checklink) added,\n    with accompany target checklinkx to recheck urls.\n\n  - install-exec target depends on $(BUILT_SOURCES).\n\n  - valac argument matching more precise, to avoid garbage in DIST_COMMON.\n\n  - Support for Vala in VPATH builds fixed so that both freshly-generated and\n    distributed C files work, and operation is more reliable with or without\n    an installed valac.\n\n  - Dejagnu doesn't break on directories containing spaces.\n\n* Distribution\n\n  - new variable AM_DISTCHECK_DVI_TARGET, to allow overriding the\n    \"make dvi\" that is done as part of distcheck.\n\n* Miscellaneous changes\n\n  - install-sh tweaks:\n    . new option -p to preserve mtime, i.e., invoke cp -p.\n    . new option -S SUFFIX to attempt backup files using SUFFIX.\n    . no longer unconditionally uses -f when rm is overridden by RMPROG.\n    . does not chown existing directories.\n\n  - Removed function up_to_date_p in lib/Automake/FileUtils.pm.\n    We believe this function is completely unused.\n\n  - Support for in-tree Vala libraries improved.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.16.2:\n\n* New features added\n\n  - add zstd support and the automake option, dist-zstd.\n\n  - support for Python 3: py-compile now supports both Python 3\n    and Python 2; tests do not require .pyo files, and uninstall\n    deletes __pycache__ correctly (automake bug #32088).\n\n* Miscellaneous changes\n\n  - automake no longer requires a @setfilename in each .texi file\n\n* Bugs fixed\n\n  - When cleaning the compiled python files, '\\n' is not used anymore in the\n    substitution text of 'sed' transformations.  This is done to preserve\n    compatibility with the 'sed' implementation provided by macOS which\n    considers '\\n' as the 'n' character instead of a newline.\n    (automake bug#31222)\n\n  - For make tags, lisp_LISP is followed by the necessary space when\n    used with CONFIG_HEADERS.\n    (automake bug#38139)\n\n  - The automake test txinfo-vtexi4.sh no longer fails when localtime\n    and UTC cross a day boundary.\n\n  - Emacsen older than version 25, which require use of\n    byte-compile-dest-file, are supported again.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.16.1:\n\n* Bugs fixed:\n\n  - 'install-sh' now ensures that nobody can cross privilege boundaries by\n    pre-creating symlink on the directory inside \"/tmp\".\n\n  - 'automake' does not depend on the 'none' subroutine of the List::Util\n    module anymore to support older Perl version. (automake bug#30631)\n\n  - A regression in AM_PYTHON_PATH causing the rejection of non literal\n    minimum version parameter hasn't been fixed. (automake bug#30616)\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.16:\n\n* Miscellaneous changes\n\n  - When subdir-objects is in effect, Automake will now construct\n    shorter object file names when no programs and libraries name\n    clashes are encountered.  This should make the discouraged use of\n    'foo_SHORTNAME' unnecessary in many cases.\n\n* Bugs fixed:\n\n  - Automatic dependency tracking has been fixed to work also when the\n    'subdir-object' option is used and some 'foo_SOURCES' definition\n    contains unexpanded references to make variables, as in, e.g.:\n\n        a_src = sources/libs/aaa\n        b_src = sources/bbb\n        foo_SOURCES = $(a_src)/bar.c $(b_src)/baz.c\n\n    With such a setup, the created makefile fragment containing dependency\n    tracking information will be correctly placed under the directories\n    named 'sources/libs/aaa/.deps' and 'sources/bbb/.deps', rather than\n    mistakenly under directories named (literally!) '$(src_a)/.deps' and\n    '$(src_b)/.deps' (this was the first part of automake bug#13928).\n\n    Notice that in order to fix this bug we had to slightly change the\n    semantics of how config.status bootstraps the makefile fragments\n    required for the dependency tracking to work: rather than attempting\n    to parse the Makefiles via grep and sed trickeries only, we actually\n    invoke 'make' on a slightly preprocessed version of those Makefiles,\n    using a private target that is only meant to bootstrap the required\n    makefile fragments.\n\n  - The 'subdir-object' option no longer causes object files corresponding\n    to source files specified with an explicit '$(srcdir)' component to be\n    placed in the source tree rather than in the build tree.\n\n    For example, if Makefile.am contains:\n\n        AUTOMAKE_OPTIONS = subdir-objects\n        foo_SOURCES = $(srcdir)/foo.c $(srcdir)/s/bar.c $(top_srcdir)/baz.c\n\n    then \"make all\" will create 'foo.o' and 's/bar.o' in $(builddir) rather\n    than in $(srcdir), and will create 'baz.o' in $(top_builddir) rather\n    than in $(top_srcdir).\n\n    This was the second part of automake bug#13928.\n\n  - Installed 'aclocal' m4 macros can now accept installation directories\n    containing '@' characters (automake bug#20903)\n\n  - \"./configure && make dist\" no longer fails when a distributed file depends\n    on one from BUILT_SOURCES.\n\n  - When combining AC_LIBOBJ or AC_FUNC_ALLOCA with the\n    \"--disable-dependency-tracking\" configure option in an out of source\n    build, the build sub-directory defined by AC_CONFIG_LIBOBJ_DIR is now\n    properly created.  (automake bug#27781)\n\n  - The time printed by 'mdate-sh' is now using the UTC time zone to support\n    the reproducible build effort.  (automake bug#20314)\n\n  - The elisp byte-compilation rule now uses byte-compile-dest-file-function,\n    rather than byte-compile-dest-file, which was obsoleted in 2009. We expect\n    that Emacs-26 will continue to support the old function, but will complain\n    loudly, and that Emacs-27 will remove support for it altogether.\n\n* New features added\n\n  - A custom testsuite driver for the Guile Scheme SRFI-64 API has been added\n    to the \"contrib\" section.  This allows a more convenient way to test Guile\n    code without having to use low primitives such as exit status.  See\n    SRFI-64 API specification for more details:\n    <https://srfi.schemers.org/srfi-64/srfi-64.html>\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.15.1:\n\n* Bugs fixed:\n\n  - The code has been adapted to remove a warning present since Perl\n    5.22 stating that \"Unescaped left brace in regex is deprecated\".\n    This warning has become an hard error in Perl 5.26 (bug#22372).\n\n  - The generated Makefiles do not rely on the obsolescent GZIP\n    environment variable which was used for passing arguments to\n    'gzip'.  Compatibility with old versions has been\n    preserved. (bug#20132)\n\n* Miscellaneous changes:\n\n  - Support the Windows version of the Intel C Compiler (icl) in the\n    'compile' script in the same way the (compatible) Microsoft C\n    Compiler is supported.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.15:\n\n* Improvements and refactorings in the install-sh script:\n\n  - It has been modernized, and now makes the following assumptions\n    *unconditionally*:\n    (1) a working 'dirname' program is available;\n    (2) the ${var:-value} shell parameters substitution works;\n    (3) the \"set -f\" and \"set +f\" shell commands work, and, respectively,\n        disable and enable shell globbing.\n\n  - The script implements stricter error checking, and now it complains\n    and bails out if any of the following expectations is not met:\n    (1) the options -d and -t are never used together;\n    (2) the argument passed to option -t is a directory;\n    (3) if there are two or more SOURCEFILE arguments, the\n        DESTINATION argument must be a directory.\n\n* Automake-generated testsuites:\n\n  - The default test-driver used by the Automake-generated testsuites\n    now appends the result and exit status of each \"plain\" test to the\n    associated log file (automake bug#11814).\n\n  - The perl implementation of the TAP testsuite driver is no longer\n    installed in the Automake's scripts directory, and is instead just\n    distributed as a \"contrib\" addition.  There should be no reason to\n    use this implementation anyway in real packages, since the awk+shell\n    implementation of the TAP driver (which is documented in the manual)\n    is more portable and has feature parity with the perl implementation.\n\n  - The rule generating 'test-suite.log' no longer risk incurring in an\n    extra useless \"make all\" recursive invocation in some corner cases\n    (automake bug#16302).\n\n* Distribution:\n\n  - Automake bug#18286: \"make distcheck\" could sometimes fail to detect\n    files missing from the distribution tarball, especially in those cases\n    where both the generated files and their dependencies are explicitly\n    in $(srcdir).  An important example of this are *generated* makefile\n    fragments included at Automake time in Makefile.am; e.g.:\n\n        ...\n        $(srcdir)/fragment.am: $(srcdir)/data.txt $(srcdir)/preproc.sh\n            cd $(srcdir) && $(SHELL) preproc.sh <data.txt >fragment.am\n        include $(srcdir)/fragment.am\n        ...\n\n    If the use forgot to add data.txt and/or preproc.sh in the distribution\n    tarball, \"make distcheck\" would have erroneously succeeded!  This issue\n    is now fixed.\n\n  - As a consequence of the previous change, \"make distcheck\" will run\n    using '$(distdir)/_build/sub' as the build directory, rather than\n    simply '$(distdir)/_build' (as it was the case for Automake 1.14 and\n    earlier).  Consequently, the './configure' and 'make' invocations\n    issued by the distcheck recipe now have $(srcdir) equal to '../..',\n    rather than to just '..'.  Dependent and similar variables (e.g.,\n    '$(top_srcdir)') are also changed accordingly.\n\n    Thus, Makefiles that made assumptions about the exact values of the\n    build and source directories used by \"make distcheck\" will have to\n    be adjusted.  Notice that making such assumptions was a bad and\n    unsupported practice anyway, since the exact locations of those\n    directories should be considered implementation details, and we\n    reserve the right to change them at any time.\n\n* Miscellaneous bugs fixed:\n\n  - The expansion of AM_INIT_AUTOMAKE ends once again with a trailing\n    newline (bug#16841).  Regression introduced in Automake 1.14.\n\n  - We no longer risk to use '$ac_aux_dir' before it's defined (see\n    automake bug#15981). Bug introduced in Automake 1.14.\n\n  - The code used to detect whether the currently used make is GNU make\n    or not (relying on the private macro 'am__is_gnu_make') no longer\n    risks causing \"Arg list too long\" for projects using automatic\n    dependency tracking and having a ton of source files (bug#18744).\n\n  - Automake tries to offer a more deterministic output for generated\n    Makefiles, in the face of the newly-introduced randomization for\n    hash keys order in Perl 5.18.\n\n  - In older Automake versions, if a user defined one single Makefile\n    fragment (say 'foo.am') to be included via Automake includes in\n    his main Makefile.am, and defined a custom make rule to generate that\n    file from other data, Automake used to spuriously complain with some\n    message like \"... overrides Automake target '$(srcdir)/foo.am\".\n    This bug is now fixed.\n\n  - The user can now extend the special .PRECIOUS target, the same way\n    he could already do with the .MAKE .and .PHONY targets.\n\n  - Some confusing typos have been fixed in the manual and in few warning\n    messages (automake bug#16827 and bug#16997).\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.14.1:\n\n* Bugs fixed:\n\n  - The user is no longer allowed to override the --srcdir nor the --prefix\n    configure options used by \"make distcheck\" (bug#14991).\n\n  - Fixed a gross inefficiency in the recipes for installing byte-compiled\n    python files, that was causing an O(N^2) performance on the number N of\n    files, instead of the expected O(N) performance.  Note that this bug\n    was only relevant when the number of python files was high (which is\n    unusual in practice).\n\n  - Automake try to offer a more deterministic output for warning messages,\n    in the face of the newly-introduced randomization for hash keys order\n    in Perl 5.18.\n\n  - The 'test-driver' script now actually error out with a clear error\n    message on the most common invalid usages.\n\n  - Several spurious failures/hangs in the testsuite (bugs #14706, #14707,\n    #14760, #14911, #15181, #15237).\n\n* Documentation fixes:\n\n  - Fixed typos in the 'fix-timestamp.sh' example script that made it\n    nonsensical.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.14:\n\n* C compilation, and the AC_PROG_CC and AM_PROG_CC_C_O macros:\n\n  - The 'compile' script is now unconditionally required for all packages\n    that perform C compilation (if you are using the '--add-missing'\n    option, automake will fetch that script for you, so you shouldn't\n    need any explicit adjustment).  This new behaviour is needed to avoid\n    obscure errors when the 'subdir-objects' option is used, and the\n    compiler is an inferior one that doesn't grasp the combined use of\n    both the \"-c -o\" options; see discussion about automake bug#13378 for\n    more details:\n    <https://debbugs.gnu.org/cgi/bugreport.cgi?bug=13378#35>\n    <https://debbugs.gnu.org/cgi/bugreport.cgi?bug=13378#44>\n\n  - The next major Automake version (2.0) will unconditionally activate\n    the 'subdir-objects' option.  In order to smooth out the transition,\n    we now give a warning (in the category 'unsupported') whenever a\n    source file is present in a subdirectory but the 'subdir-object' is\n    not enabled.  For example, the following usage will trigger such a\n    warning:\n\n        bin_PROGRAMS = sub/foo\n        sub_foo_SOURCES = sub/main.c sub/bar.c\n\n  - Automake will automatically enhance the autoconf-provided macro\n    AC_PROG_CC to force it to check, at configure time, that the\n    C compiler supports the combined use of both the '-c' and '-o'\n    options.  The result of this check is saved in the cache variable\n    'am_cv_prog_cc_c_o', and said result can be overridden by\n    pre-defining that variable.\n\n  - The AM_PROG_CC_C_O macro can still be called, albeit that should no\n    longer be necessary. This macro is now just a thin wrapper around the\n    Automake-enhanced AC_PROG_CC.  This means, among the other things,\n    that its behaviour is changed in three ways:\n\n      1. It no longer invokes the Autoconf-provided AC_PROG_CC_C_O\n         macro behind the scenes.\n\n      2. It caches the check result in the 'am_cv_prog_cc_c_o' variable,\n         and not in a 'ac_cv_prog_cc_*_c_o' variable whose exact name is\n         dynamically computed only at configure runtime (really!) from\n         the content of the '$CC' variable.\n\n      3. It no longer automatically AC_DEFINE the C preprocessor\n         symbol 'NO_MINUS_C_MINUS_O'.\n\n* Texinfo support:\n\n  - Automake can now be instructed to place '.info' files generated from\n    Texinfo input in the builddir rather than in the srcdir; this is done\n    specifying the new automake option 'info-in-builddir'.  This feature\n    was requested by the developers of GCC, GDB, GNU binutils and the GNU\n    bfd library.  See the extensive discussion about automake bug#11034\n    for more details.\n\n  - For quite a long time, Automake has been implementing an undocumented\n    hack which ensured that '.info' files which appeared to be cleaned\n    (by being listed in the CLEANFILES or DISTCLEANFILES variables) were\n    built in the builddir rather than in the srcdir; this hack was\n    introduced to ensure better backward-compatibility with package\n    such as Texinfo, which do things like:\n\n        info_TEXINFOS = texinfo.txi info-stnd.texi info.texi\n        DISTCLEANFILES = texinfo texinfo-* info*.info*\n        # Do not create info files for distribution.\n        dist-info:\n            @:\n\n    in order not to distribute generated '.info' files.\n\n    Now that we have the 'info-in-builddir' option that explicitly causes\n    generated '.info' files to be placed in the builddir, this hack should\n    be longer necessary, so we deprecate it with runtime warnings.\n    It will be removed altogether in Automake 2.0.\n\n* Relative directory in Makefile fragments:\n\n  - The special Automake-time substitutions '%reldir%' and '%canon_reldir%'\n    (and their short versions, '%D%' and '%C%' respectively) can now be used\n    in an included Makefile fragment.  The former is substituted with the\n    relative directory of the included fragment (compared to the top-level\n    including Makefile), and the latter with the canonicalized version of\n    the same relative directory.\n\n        # in 'Makefile.am':\n        bin_PROGRAMS = # will be updated by included Makefile fragments\n        include src/Makefile.inc\n\n        # in 'src/Makefile.inc':\n        bin_PROGRAMS += %reldir%/foo\n        %canon_reldir%_foo_SOURCES = %reldir%/bar.c\n\n    This should be especially useful for packages using a non-recursive\n    build system.\n\n* Deprecated distribution formats:\n\n  - The 'shar' and 'compress' distribution formats are deprecated, and\n    scheduled for removal in Automake 2.0.  Accordingly, the use of the\n    'dist-shar' and 'dist-tarZ' will cause warnings at automake runtime\n    (in the 'obsolete' category), and the recipes of the Automake-generated\n    targets 'dist-shar' and 'dist-tarZ' will unconditionally display\n    (non-fatal) warnings at make runtime.\n\n* New configure runtime warnings about \"rm -f\" support:\n\n  - To simplify transition to Automake 2.0, the shell code expanded by\n    AM_INIT_AUTOMAKE now checks (at configure runtime) that the default\n    'rm' program in PATH doesn't complain when called without any\n    non-option argument if the '-f' option is given (so that commands like\n    \"rm -f\" and \"rm -rf\" act as a no-op, instead of raising usage errors).\n    If this is not the case, the configure script is aborted, to call the\n    attention of the user on the issue, and invite him to fix his PATH.\n    The checked 'rm' behavior is very widespread in the wild, and will be\n    required by future POSIX versions:\n\n        <http://austingroupbugs.net/view.php?id=542>\n\n    The user can still force the configure process to complete even in the\n    presence of a broken 'rm' by defining the ACCEPT_INFERIOR_RM_PROGRAM\n    environment variable to \"yes\".  And the generated Makefiles should\n    still work correctly even when such broken 'rm' is used.  But note\n    that this will no longer be the case with Automake 2.0 though, so, if\n    you encounter the warning, please report it to us ASAP (and try to fix\n    your environment as well).\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.13.4:\n\n* Bugs fixed:\n\n  - Fix a minor regression introduced in Automake 1.13.3: when two or more\n    user-defined suffix rules were present in a single Makefile.am,\n    automake would needlessly include definition of some make variables\n    related to C compilation in the generated Makefile.in (bug#14560).\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.13.3:\n\n* Documentation fixes:\n\n  - The documentation no longer mistakenly reports that the obsolete\n    'AM_MKDIR_PROG_P' macro and '$(mkdir_p)' make variable are going\n    to be removed in Automake 2.0.\n\n* Bugs fixed:\n\n  - Byte-compilation of Emacs lisp files could fail spuriously on\n    Solaris,  when /bin/ksh or /usr/xpg4/bin/sh were used as shell.\n\n  - If the same user-defined suffixes were transformed into different\n    Automake-known suffixes in different Makefile.am files in the same\n    project, automake could get confused and generate inconsistent\n    Makefiles (automake bug#14441).\n    For example, if 'Makefile.am' contained a \".ext.cc:\" suffix rule,\n    and 'sub/Makefile.am' contained a \".ext.c:\" suffix rule, automake\n    would have mistakenly placed into 'Makefile.in' rules to compile\n    \"*.c\" files into object files, and into 'sub/Makefile.in' rules to\n    compile \"*.cc\" files into object files --- rather than the other\n    way around.  This is now fixed.\n\n* Testsuite work:\n\n  - The test cases no longer have the executable bit set.  This should\n    make it clear that they are not meant to be run directly; as\n    explained in t/README, they can only be run through the custom\n    'runtest' script, or by a \"make check\" invocation.\n\n  - The testsuite has seen the introduction of a new helper function\n    'run_make', and several related changes.  These serve a two-fold\n    purpose:\n\n     1. Remove brittleness due to the use of \"make -e\" in test cases.\n\n     2. Seamlessly allow the use of parallel make (\"make -j...\") in the\n        test cases, even where redirection of make output is involved\n        (see automake bug#11413 for a description of the subtle issues\n        in this area).\n\n  - Several spurious failures have been fixed (they hit especially\n    MinGW/MSYS builds).  See automake bugs #14493, #14494, #14495,\n    #14498, #14499, #14500, #14501, #14517 and #14528.\n\n  - Some other minor miscellaneous changes and fixlets.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.13.2:\n\n* Documentation fixes:\n\n  - The long-deprecated but still supported two-arguments invocation form\n    of AM_INIT_AUTOMAKE is documented once again.  This seems the sanest\n    thing to do, given that support for such usage might need to remain\n    in place for an unspecified amount of time in order to cater to people\n    who want to define the version number for their package dynamically at\n    configure runtime (unfortunately, Autoconf does not yet support this\n    scenario, so we cannot delegate the work to it).\n\n  - The serial testsuite harness is no longer reported as \"deprecated\",\n    but as \"discouraged\".  We have no plan to remove it, nor to make its\n    use cause runtime warnings.\n\n  - The parallel testsuite is no longer reported as \"experimental\"; it\n    is well tested, and should be stable now.\n\n  - The 'shar' and 'tarZ' distribution formats and the 'dist-shar' and\n    'dist-tarZ' options are obsolescent, and their use is deprecated\n    in the documentation.\n\n  - Other minor miscellaneous fixes and improvements; in particular,\n    some improvements in cross-references.\n\n* Obsolescent features:\n\n  - Use of suffix-less info files (that can be specified through the\n    '@setfilename' macro in Texinfo input files) is discouraged, and\n    its use will raise warnings in the 'obsolete' category.  Simply\n    use the '.info' extension for all your info files, transforming\n    usages like:\n\n        @setfilename myprogram\n\n    into:\n\n        @setfilename myprogram.info\n\n  - Use of Texinfo input files with '.txi' or '.texinfo' extensions\n    is discouraged, and its use will raise warnings in the 'obsolete'\n    category.  You are advised to simply use the '.texi' extension\n    instead.\n\n* Bugs fixed:\n\n  - When the 'ustar' option is used, the generated configure script no\n    longer risks hanging during the tests for the availability of the\n    'pax' utility, even if the user running configure has a UID or GID\n    that requires more than 21 bits to be represented.\n    See automake bug#8343 and bug#13588.\n\n  - The obsolete macros AM_CONFIG_HEADER or AM_PROG_CC_STDC work once\n    again, as they did in Automake 1.12.x (albeit printing runtime\n    warnings in the 'obsolete' category).  Removing them has turned\n    out to be a very bad idea, because it complicated distro packing\n    enormously.  Making them issue fatal warnings, as we did in\n    Automake 1.13, has turned out to be a similarly very bad idea,\n    for exactly the same reason.\n\n  - aclocal will no longer error out if the first local m4 directory\n    (as specified by the '-I' option or the 'AC_CONFIG_MACRO_DIRS' or\n    'AC_CONFIG_MACRO_DIR' macros) doesn't exist; it will merely report\n    a warning in the 'unsupported' category.  This is done to support\n    some pre-existing real-world usages.  See automake bug#13514.\n\n  - aclocal will no longer consider directories for extra m4 files more\n    than once, even if they are specified multiple times.  This ensures\n    packages that specify both\n\n        AC_CONFIG_MACRO_DIR([m4])       in configure.ac\n        ACLOCAL_AMFLAGS = -I m4         in Makefile.am\n\n    will work correctly, even when the 'm4' directory contains no\n    package-specific files, but is used only to install third-party\n    m4 files (as can happen with e.g., \"libtoolize --install\").\n    See automake bug#13514.\n\n  - Analysis of make flags in Automake-generated rules has been made more\n    robust, and more future-proof.  For example, in presence of make that\n    (like '-I') take an argument, the characters in said argument will no\n    longer be spuriously considered as a set of additional make options.\n    In particular, automake-generated rules will no longer spuriously\n    believe to be running in dry mode (\"make -n\") if run with an invocation\n    like \"make -I noob\"; nor will they believe to be running in keep-going\n    mode (\"make -k\") if run with an invocation like \"make -I kool\"\n    (automake bug#12554).\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.13.1:\n\n* Bugs fixed:\n\n  - Use of the obsolete macros AM_CONFIG_HEADER or AM_PROG_CC_STDC now\n    causes a clear and helpful error message, instead of obscure ones\n    (issue introduced in Automake 1.13).\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.13:\n\n* Bugs fixed:\n\n  - ylwrap renames properly header guards in generated header files\n    (*.h), instead of leaving Y_TAB_H.\n\n  - ylwrap now also converts header guards in implementation files\n    (*.c).  Because ylwrap failed to rename properly #include in the\n    implementation files, current versions of Bison (e.g., 2.7)\n    duplicate the generated header file in the implementation file.\n    The header guard then protects the implementation file from\n    duplicate definitions from the header file.\n\n* Version requirements:\n\n  - Autoconf 2.65 or greater is now required.\n\n  - The rules to build PDF and DVI output from Texinfo input now\n    require Texinfo 4.9 or later.\n\n* Obsolete features:\n\n  - Support for the \"Cygnus-style\" trees (once enabled by the 'cygnus'\n    option) has been removed.  See discussion about automake bug#11034\n    for more background: <https://debbugs.gnu.org/11034>.\n\n  - The deprecated aclocal option '--acdir' has been removed.  You\n    should use the options '--automake-acdir' and '--system-acdir'\n    instead (which have been introduced in Automake 1.11.2).\n\n  - The following long-obsolete m4 macros have been removed:\n\n      AM_PROG_CC_STDC:    superseded by AC_PROG_CC since October 2002\n      fp_PROG_CC_STDC:    broken alias for AM_PROG_CC_STDC\n      fp_WITH_DMALLOC:    old alias for AM_WITH_DMALLOC\n      AM_CONFIG_HEADER:   superseded by AC_CONFIG_HEADERS since July 2002\n      ud_PATH_LISPDIR:    old alias for AM_PATH_LISPDIR\n      jm_MAINTAINER_MODE: old alias for AM_MAINTAINER_MODE\n      ud_GNU_GETTEXT:     old alias for AM_GNU_GETTEXT\n      gm_PROG_LIBTOOL:    old alias for AC_PROG_LIBTOOL\n      fp_C_PROTOTYPES:    old alias for AM_C_PROTOTYPES (which was part\n                          of the now-removed automatic de-ANSI-fication\n                          support of Automake)\n\n  - All the \"old alias\" macros in 'm4/obsolete.m4' have been removed.\n\n  - Use of the long-deprecated two- and three-arguments invocation forms\n    of the AM_INIT_AUTOMAKE is no longer documented.  It's still supported\n    though (albeit with a warning in the 'obsolete' category), to cater\n    for people who want to define the version number for their package\n    dynamically (e.g., from the current VCS revision).  We'll have to\n    continue this support until Autoconf itself is fixed to allow better\n    support for such dynamic version numbers.\n\n* Elisp byte-compilation:\n\n  - The byte compilation of '.el' files into '.elc' files is now done\n    with a suffix rule.  This has simplified the compilation process, and\n    more importantly made it less brittle.  The downside is that emacs is\n    now invoked once for each '.el' files, which cause some noticeable\n    slowdowns.  These should however be mitigated on multicore machines\n    (which are becoming the norm today) if concurrent  make (\"make -j\")\n    is used.\n\n  - Elisp files placed in a subdirectory are now byte-compiled to '.elc'\n    files in the same subdirectory; for example, byte-compiling of file\n    'sub/foo.el' file will result in 'sub/foo.elc' rather than in\n    'foo.elc'.  This behaviour is backward-incompatible with older\n    Automake versions, but it is more natural and more sane.  See also\n    automake bug#7441.\n\n  - The Emacs invocation performing byte-compilation of '.el' files honors\n    the $(AM_ELCFLAGS) and $(ELCFLAGS) variables; as typical, the former\n    one is  developer-reserved and the latter one user-reserved.\n\n  - The 'elisp-comp' script, once provided by Automake, has been rendered\n    obsoleted by the just-described changes, and thus removed.\n\n* Changes to Automake-generated testsuite harnesses:\n\n  - The parallel testsuite harness (previously only enabled by the\n    'parallel-tests' option) is the default one; the older serial\n    testsuite harness will still be available through the use of the\n    'serial-tests' option (introduced in Automake 1.12).\n\n  - The 'color-tests' option is now unconditionally activated by default.\n    In particular, this means that testsuite output is now colorized by\n    default if the attached terminal seems to support ANSI escapes, and\n    that the user can force output colorization by setting the variable\n    AM_COLOR_TESTS to \"always\".  The 'color-tests' is still recognized\n    for backward-compatibility, although it's a handled as a no-op now.\n\n* Silent rules support:\n\n  - Support for silent rules is now always active in Automake-generated\n    Makefiles.  So, although the verbose output is still the default,\n    the user can now always use \"./configure --enable-silent-rules\" or\n    \"make V=0\" to enable quieter output in the package he's building.\n\n  - The 'silent-rules' option has now become a no-op, preserved for\n    backward-compatibility only.  In particular, its use no longer\n    disables the warnings in the 'portability-recursive' category.\n\n* Texinfo Support:\n\n  - The rules to build PDF and DVI files from Texinfo input now require\n    Texinfo 4.9 or later.\n\n  - The rules to build PDF and DVI files from Texinfo input now use the\n    '--build-dir' option, to keep the auxiliary files used by texi2dvi\n    and texi2pdf around without cluttering the build directory, and to\n    make it possible to run the \"dvi\" and \"pdf\" recipes in parallel.\n\n* Automatic remake rules and 'missing' script:\n\n  - The 'missing' script no longer tries to update the timestamp of\n    out-of-date files that require a maintainer-specific tool to be\n    remade, in case the user lacks such a tool (or has a too-old version\n    of it).  It just gives a useful warning, and in some cases also a\n    tip about how to obtain such a tool.\n\n  - The missing script has thus become useless as a (poor) way to work\n    around the sketched-timestamps issues that can happen for projects\n    that keep generated files committed in their VCS repository.  Such\n    projects are now encouraged to write a custom \"fix-timestamps.sh\"\n    script to avoid such issues; a simple example is provided in the\n    \"CVS and generated files\" chapter of the automake manual.\n\n* Recursive targets:\n\n  - The user can now define his own recursive targets that recurse\n    in the directories specified in $(SUBDIRS).  This can be done by\n    specifying the name of such targets in invocations of the new\n    'AM_EXTRA_RECURSIVE_TARGETS' m4 macro.\n\n* Tags:\n\n  - Any failure in the recipe of the \"tags\", \"ctags\", \"cscope\" or\n    \"cscopelist\" targets in a subdirectory is now propagated to the\n    top-level make invocation.\n\n  - Tags are correctly computed also for files in _SOURCES variables that\n    only list files with non-standard suffixes (see automake bug#12372).\n\n* Improvements to aclocal and related rebuilds rules:\n\n  - Autoconf-provided macros AC_CONFIG_MACRO_DIR and AC_CONFIG_MACRO_DIRS\n    are now traced by aclocal, and can be used to declare the local m4\n    include directories.  Formerly, one had to specify it with an explicit\n    '-I' option to the 'aclocal' invocation.\n\n  - The special make variable ACLOCAL_AMFLAGS is deprecated; future\n    Automake versions will warn about its use, and later version will\n    remove support for it altogether.\n\n* The depcomp script:\n\n  - Dropped support for libtool 1.4.\n\n  - Various internal refactorings.  They should cause no visible change,\n    but the chance for regression is there anyway, so please report any\n    unexpected or suspicious behaviour.\n\n  - Support for pre-8.0 versions of the Intel C Compiler has been dropped.\n    This should cause no problem, since icc 8.0 has been released in\n    December 2003 -- almost nine years ago.\n\n  - Support for tcc (the Tiny C Compiler) has been improved, and is now\n    handled through a dedicated 'tcc' mode.\n\n* The ylwrap script:\n\n  - ylwrap generates header guards with a single '_' for series of non\n    alphabetic characters, instead of several.  This is what Bison >=\n    2.5.1 does.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBugs fixed in 1.12.6:\n\n* Python-related bugs:\n\n  - The default installation location for python modules has been improved\n    for Python 3 on Debian and Ubuntu systems, changing from:\n\n        ${prefix}/lib/python3/dist-packages\n\n    to\n\n        ${prefix}/lib/python3.x/site-packages\n\n    This change should ensure modules installed using the default ${prefix}\n    \"/usr/local\" are found by default by system python 3.x installations.\n    See automake bug#10227.\n\n  - Python byte-compilation supports the new layout mandated by PEP-3147,\n    with its __pycache__ directory (automake bug#8847).\n\n* Build system issues:\n\n  - The maintainer rebuild rules for Makefiles and aclocal.m4 in\n    Automake's own build system works correctly again (bug introduced\n    in Automake 1.12.5).\n\n* Testsuite issues:\n\n  - The Vala-related tests has been changed to adjust to the removal of\n    the 'posix' profile in the valac compiler.  See automake bug#12934\n    a.k.a. bug#12522.\n\n  - Some spurious testsuite failures related to older tools and systems\n    have been fixed.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.12.5:\n\n* Vala support:\n\n  - The AM_PROG_VALAC macro has been enhanced to takes two further\n    optional arguments; it's signature now being\n\n        AM_PROG_VALAC([MINIMUM-VERSION], [ACTION-IF-FOUND],\n                      [ACTION-IF-NOT-FOUND])\n\n  - By default, AM_PROG_VALAC no longer aborts the configure invocation\n    if the Vala compiler found is too old, but simply prints a warning\n    messages (as it did when the Vala compiler was not found).  This\n    should avoid unnecessary difficulties for end users that just want\n    to compile the unmodified, distributed Vala-generated C sources,\n    but happens to have an old Vala compiler in their PATH.  This fixes\n    automake bug#12688.\n\n  - If no proper Vala compiler is found at configure runtime, AM_PROG_VALAC\n    will set the AC_SUBST'd variable 'VALAC' to 'valac' rather than to ':'.\n    This is a better default, because with it a triggered makefile rule\n    invoking a Vala compilation will clearly fail with an informative error\n    message like \"valac: command not found\", rather than silently, with\n    the error possibly going unnoticed or triggering harder-to-diagnose\n    fallout failures in later steps.\n\n* Miscellaneous changes:\n\n  - automake and aclocal no longer honours the 'perllibdir' environment\n    variable.  That had always been intended only as an hack required in\n    the testsuite, not meant for any use beyond that.\n\nBugs fixed in 1.12.5:\n\n* Long-standing bugs:\n\n  - Automake no longer generates spurious remake rules invoking autoheader\n    to regenerate the template corresponding to header files specified after\n    the first one in AC_CONFIG_HEADERS (automake bug#12495).\n\n  - When wrapping Microsoft tools, the 'compile' script falls back to\n    finding classic 'libname.a' style libraries when 'name.lib' and\n    'name.dll.lib' aren't available.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.12.4:\n\n* Warnings and deprecations:\n\n  - Warnings in the 'obsolete' category are enabled by default both in\n    automake and aclocal.\n\n* Miscellaneous changes:\n\n  - Some testsuite weaknesses and spurious failures have been fixed.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.12.3:\n\n* Miscellaneous changes:\n\n  - The '.m4' files provided by Automake no longer define serial numbers.\n    This should cause no difference in the behaviour of aclocal though.\n\n  - Some testsuite weaknesses and spurious failures have been fixed.\n\n  - There is initial support for automatic dependency tracking with the\n    Portland Group C/C++ compilers, thanks to the new new depmode 'pgcc'.\n\nBugs fixed in 1.12.3:\n\n* Long-standing bugs:\n\n  - Instead of renaming only self-references of files (typically for\n    #lines), ylwrap now also renames references to the other generated\n    files.  This fixes support for GLR and C++ parsers from Bison (PR\n    automake/491 and automake bug#7648): 'parser.c' now properly\n    #includes 'parser.h' instead of 'y.tab.h'.\n\n  - Generated files unknown to ylwrap are now preserved.  This fixes\n    C++ support for Bison (automake bug#7648): location.hh and the\n    like are no longer discarded.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.12.2:\n\n* Warnings and deprecations:\n\n  - Automake now issues a warning (in the 'portability' category) if\n    'configure.in' is used instead of 'configure.ac' as the Autoconf\n    input file.  Such a warning will also be present in the next\n    Autoconf version (2.70).\n\n* Cleaning rules:\n\n  - Recursive cleaning rules descends into the $(SUBDIRS) in the natural\n    order (as done by the other recursive rules), rather than in the\n    inverse order.  They used to do that in order to work a round a\n    limitation in an older implementation of the automatic dependency\n    tracking support, but that limitation had been lifted years ago\n    already, when the automatic dependency tracking based on side-effects\n    of compilation had been introduced.\n\n  - Cleaning rules for compiled objects (both \"plain\" and libtool) work\n    better when subdir objects are involved, not triggering a distinct\n    'rm' invocation for each such object.  They do so by removing *any*\n    compiled object file that is in the same directory of a subdir\n    object.  See automake bug#10697.\n\n* Silent rules support:\n\n  - A new predefined $(AM_V_P) make variable is provided; it expands\n    to a shell conditional that can be used in recipes to know whether\n    make is being run in silent or verbose mode.\n\nBugs fixed in 1.12.2:\n\n* SECURITY VULNERABILITIES!\n\n  - The 'distcheck' recipe no longer grants temporary world-write\n    permissions on the extracted distdir.  Even if such rights were\n    only granted for a vanishingly small time window, the implied\n    race condition proved to be enough to allow a local attacker\n    to run arbitrary code with the privileges of the user running\n    \"make distcheck\".  This is CVE-2012-3386.\n\n* Long-standing bugs:\n\n  - The \"recheck\" targets behaves better in the face of build failures\n    related to previously failed tests.  For example, if a test is a\n    compiled program that must be rerun by \"make recheck\", and its\n    compilation fails, it will still be rerun by further \"make recheck\"\n    invocations.  See automake bug#11791.\n\n* Bugs introduced by 1.12.1:\n\n  - Automake provides once again the '$(mkdir_p)' make variable and the\n    '@mkdir_p@' substitution (both as simple aliases for '$(MKDIR_P)'),\n    for better backward-compatibility.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.12.1:\n\n* New supported languages:\n\n  - Support for Objective C++ has been added; it should work similarly to\n    the support for Objective C.\n\n* Deprecated obsolescent features:\n\n  - Use of the long-deprecated two- and three-arguments invocation forms\n    of the AM_INIT_AUTOMAKE macro now elicits a warning in the 'obsolete'\n    category.  Starting from some future major Automake release (likely\n    post-1.13), such usages will no longer be allowed.\n\n  - Support for the \"Cygnus-style\" trees (enabled by the 'cygnus' option) is\n    now deprecated (its use triggers a warning in the 'obsolete' category).\n    It will be removed in the next major Automake release (1.13).\n\n  - The long-obsolete (since 1.10) automake-provided $(mkdir_p) make\n    variable, @mkdir_p@ configure-time substitution and AM_PROG_MKDIR\n    m4 macro are deprecated, eliciting a warning in the 'obsolete'\n    category.\n\n* Miscellaneous changes:\n\n  - The Automake test cases now require a proper POSIX-conforming shell.\n    Older non-POSIX Bourne shells (like Solaris 10 /bin/sh) will no longer\n    be accepted.  In most cases, the user shouldn't have to specify such\n    POSIX shell explicitly, since it will be looked up at configure time.\n    Still, when this lookup fails, or when the user wants to override its\n    conclusion, the variable 'AM_TEST_RUNNER_SHELL' can be used (pointing\n    to the shell that will be used to run the Automake test cases).\n\nBugs fixed in 1.12.1:\n\n* Bugs introduced by 1.12:\n\n  - Several weaknesses in Automake's own build system and test suite\n    have been fixed.\n\n* Bugs introduced by 1.11.3:\n\n  - When given non-option arguments, aclocal rejects them, instead of\n    silently ignoring them.\n\n* Long-standing bugs:\n\n  - When the 'color-tests' option is in use, forcing of colored testsuite\n    output through \"AM_COLOR_TESTS=always\" works even if the terminal is\n    a non-ANSI one, i.e., if the TERM environment variable has a value of\n    \"dumb\".\n\n  - Several inefficiencies and poor performances in the implementation\n    of the parallel-tests 'check' and 'recheck' targets have been fixed.\n\n  - The post-processing of output \"#line\" directives done the ylwrap\n    script is more faithful w.r.t. files in a subdirectory; for example,\n    if the processed file is \"src/grammar.y\", ylwrap will correctly\n    produce directives like:\n        #line 7 \"src/grammar.y\"\n    rather than like\n        #line 7 \"grammar.y\"\n    as it did before.\n\n* Bugs with new Perl versions:\n\n  - Aclocal works correctly with perl 5.16.0 (automake bug#11543).\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.12:\n\n* Obsolete features removed:\n\n  - The never documented nor truly used script 'acinstall' has been\n    removed.\n\n  - Support for automatic de-ANSI-fication has been removed.\n\n  - The support for the \"obscure\" multilib feature has been removed\n    from Automake core (but remains available in the 'contrib/'\n    directory of the Automake distribution).\n\n  - Support for \".log -> .html\" conversion and the check-html and\n    recheck-html targets has been removed from Automake core (but\n    remains available in the 'contrib/' directory of the Automake\n    distribution).\n\n  - The deprecated 'lzma' compression format for distribution archives\n    has been removed, in favor of 'xz' and 'lzip'.\n\n  - The obsolete AM_WITH_REGEX macro has been removed.\n\n  - The long-deprecated options '--output-dir', '--Werror' and\n    '--Wno-error' have been removed.\n\n  - The chapter on the history of Automake has been moved out of the\n    reference manual, into a new dedicated Texinfo file.\n\n* New targets:\n\n  - New 'cscope' target to build a cscope database for the source tree.\n\n* Changes to Automake-generated testsuite harnesses:\n\n  - The new automake option 'serial-tests' has been introduced.  It can\n    be used to explicitly instruct automake to use the older serial\n    testsuite harness.  This is still the default at the moment, but it\n    might change in future versions.\n\n  - The 'recheck' target (provided by the parallel testsuite harness) now\n    depends on the 'all' target.  This allows for a better user-experience\n    in test-driven development.  See automake bug#11252.\n\n  - Test scripts that exit with status 99 to signal an \"hard error\" (e.g.,\n    and unexpected or internal error, or a failure to set up the test case\n    scenario) have their outcome reported as an 'ERROR' now.  Previous\n    versions of automake reported such an outcome as a 'FAIL' (the only\n    difference with normal failures being that hard errors were counted\n    as failures even when the test originating them was listed in\n    XFAIL_TESTS).\n\n  - The testsuite summary displayed by the parallel-test harness has a\n    completely new format, that always list the numbers of passed, failed,\n    xfailed, xpassed, skipped and errored tests, even when these numbers\n    are zero (but using smart coloring when the color-tests option is in\n    effect).\n\n  - The default testsuite driver offered by the 'parallel-tests' option is\n    now implemented (partly at least) with the help of automake-provided\n    auxiliary scripts (e.g., 'test-driver'), instead of relying entirely\n    on code in the generated Makefile.in.\n    This has two noteworthy implications.  The first one is that projects\n    using the 'parallel-tests' option should now either run automake with\n    the '--add-missing' option, or manually copy the 'test-driver' script\n    into their tree.  The second, and more important, implication is that\n    now, when the 'parallel-tests' option is in use, TESTS_ENVIRONMENT can\n    no longer be used to define a test runner, and the command specified\n    in LOG_COMPILER (and <ext>_LOG_COMPILER) must be a *real* executable\n    program or script.  For example, this is still a valid usage (albeit\n    a little contorted):\n\n      TESTS_ENVIRONMENT = \\\n        if test -n '$(STRICT_TESTS)'; then \\\n          maybe_errexit='-e'; \\\n        else \\\n          maybe_errexit=''; \\\n        fi;\n      LOG_COMPILER = $(SHELL) $$maybe_errexit\n\n    OTOH, this is no longer a valid usage:\n\n      TESTS_ENVIRONMENT = \\\n        $(SHELL) `test -n '$(STRICT_TESTS_CHECKING)' && echo ' -e'`\n\n    neither is this:\n\n      TESTS_ENVIRONMENT = \\\n        run_with_perl_or_shell () \\\n        { \\\n          if grep -q '^#!.*perl' $$1; then\n            $(PERL) $$1; \\\n          else \\\n            $(SHELL) $$1; \\\n          fi; \\\n        }\n      LOG_COMPILER = run_with_perl_or_shell\n\n  - The package authors can now use customary testsuite drivers within\n    the framework provided by the 'parallel-tests' testsuite harness.\n    Consistently with the existing syntax, this can be done by defining\n    special makefile variables 'LOG_DRIVER' and '<ext>_LOG_DRIVER'.\n\n  - A new developer-reserved variable 'AM_TESTS_FD_REDIRECT' can be used\n    to redirect/define file descriptors used by the test scripts.\n\n  - The parallel-tests harness generates now, in addition the '.log' files\n    holding the output produced by the test scripts, a new set of '.trs'\n    files, holding \"metadata\" derived by the execution of the test scripts;\n    among such metadata are the outcomes of the test cases run by a script.\n\n  - Initial and still experimental support for the TAP test protocol is\n    now provided.\n\n* Changes to Yacc and Lex support:\n\n  - C source and header files derived from non-distributed Yacc and/or\n    Lex sources are now removed by a simple \"make clean\" (while they were\n    previously removed only by \"make maintainer-clean\").\n\n  - Slightly backward-incompatible change, relevant only for use of Yacc\n    with C++: the extensions of the header files produced by the Yacc\n    rules are now modelled after the extension of the corresponding\n    sources.  For example, yacc files named \"foo.y++\" and \"bar.yy\" will\n    produce header files named \"foo.h++\" and \"bar.hh\" respectively, where\n    they would have previously produced header files named simply \"foo.h\"\n    and \"bar.h\".  This change offers better compatibility with 'bison -o'.\n\n* Miscellaneous changes:\n\n  - The AM_PROG_VALAC macro now causes configure to exit with status 77,\n    rather than 1, if the vala compiler found is too old.\n\n  - The build system of Automake itself now avoids the use of make\n    recursion as much as possible.\n\n  - Automake now prefers to quote 'like this' or \"like this\", rather\n    than `like this', in diagnostic message and generated Makefiles,\n    to accommodate the new GNU Coding Standards recommendations.\n\n  - Automake has a new option '--print-libdir' that prints the path of the\n    directory containing the Automake-provided scripts and data files.\n\n  - The 'dist' and 'dist-all' targets now can run compressors in parallel.\n\n  - The rules to create pdf, dvi and ps output from Texinfo files now\n    works better with modern 'texi2dvi' script, by explicitly passing\n    it the '--clean' option to ensure stray auxiliary files are not\n    left to clutter the build directory.\n\n  - Automake can now generate silenced rules for texinfo outputs.\n\n  - Some auxiliary files that are automatically distributed by Automake\n    (e.g., 'install-sh', or the 'depcomp' script for packages compiling\n    C sources) might now be listed in the DIST_COMMON variable in many\n    Makefile.in files, rather than in the top-level one.\n\n  - Messages of types warning or error from 'automake' and 'aclocal'\n    are now prefixed with the respective type, and presence of -Werror\n    is noted.\n\n  - Automake's early configure-time sanity check now tries to avoid\n    sleeping for a second, which slowed down cached configure runs\n    noticeably.  In that case, it will check back at the end of the\n    configure script to ensure that at least one second has passed, to\n    avoid time stamp issues with makefile rules rerunning autotools\n    programs.\n\n  - The warnings in the category 'extra-portability' are now enabled by\n    '-Wall'.  In previous versions, one has to use '-Wextra-portability'\n    to enable them.\n\nBugs fixed in 1.12:\n\n  - Various minor bugfixes for recent or long-standing bugs.\n\n* Bugs introduced by 1.11:\n\n  - The AM_COND_IF macro also works if the shell expression for the\n    conditional is no longer valid for the condition.\n\n  - The automake-provided parallel testsuite harness no longer fails\n    with BSD make used in parallel mode when there are test scripts in\n    a subdirectory, like in:\n\n      TESTS = sub/foo.test sub/bar.test\n\n* Long-standing bugs:\n\n  - Automake's own build system finally have a real \"installcheck\" target.\n\n  - Vala-related cleanup rules are now more complete, and work better in\n    a VPATH setup.\n\n  - Files listed with the AC_REQUIRE_AUX_FILE macro in configure.ac are\n    now automatically distributed also if the directory of the auxiliary\n    files coincides with the top-level directory.\n\n  - Automake now detects the presence of the '-d' flag in the various\n    '*YFLAGS' variables even when their definitions involve indirections\n    through other variables, such as in:\n      foo_opts = -d\n      AM_YFLAGS = $(foo_opts)\n\n  - Automake now complains if a '*YFLAGS' variable has any conditional\n    content, not only a conditional definition.\n\n  - Explicit enabling and/or disabling of Automake warning categories\n    through the '-W...' options now always takes precedence over the\n    implicit warning level implied by Automake strictness (foreign, gnu\n    or gnits), regardless of the order in which such strictness and\n    warning flags appear.  For example, a setting like:\n      AUTOMAKE_OPTIONS = -Wall --foreign\n    will cause the warnings in category 'portability' to be enabled, even\n    if those warnings are by default disabled in 'foreign' strictness.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBugs fixed in 1.11.5:\n\n* Bugs introduced by 1.11.3:\n\n  - Vala files with '.vapi' extension are now recognized and handled\n    correctly again.  See automake bug#11222.\n\n  - Vala support work again for projects that contain some program\n    built from '.vala' (and possibly '.c') sources and some other\n    program built from '.c' sources *only*.  See automake bug#11229.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.11.4:\n\n* Miscellaneous changes:\n\n  - The 'ar-lib' script now ignores the \"s\" (symbol index) and \"S\" (no\n    symbol index) modifiers as well as the \"s\" action, as the symbol index\n    is created unconditionally by Microsoft lib.  Also, the \"q\" (quick)\n    action is now a synonym for \"r\" (replace).  Also, the script has been\n    ignoring the \"v\" (verbose) modifier already since Automake 1.11.3.\n\n  - When the 'compile' script is used to wrap MSVC, it now accepts an\n    optional space between the -I, -L and -l options and their respective\n    arguments, for better POSIX compliance.\n\n  - There is an initial, experimental support for automatic dependency\n    tracking with tcc (the Tiny C Compiler).  Its associated depmode is\n    currently recognized as \"icc\" (but this and other details are likely\n    to change in future versions).\n\n  - Automatic dependency tracking now works also with the IBM XL C/C++\n    compilers, thanks to the new new depmode 'xlc'.\n\nBugs fixed in 1.11.4:\n\n* Bugs introduced by 1.11.2:\n\n  - A definition of 'noinst_PYTHON' before 'python_PYTHON' (or similar)\n    no longer cause spurious failures upon \"make install\".\n\n  - The user can now instruct the 'uninstall-info' rule not to update\n    the '${infodir}/dir' file by exporting the environment variable\n    'AM_UPDATE_INFO_DIR' to the value \"no\".  This is done for consistency\n    with how the 'install-info' rule operates since automake 1.11.2.\n\n* Long-standing bugs:\n\n  - It is now possible for a foo_SOURCES variable to hold Vala sources\n    together with C header files, as well as with sources and headers for\n    other supported languages (e.g., C++).  Previously, only mixing C and\n    Vala sources was supported.\n\n  - If \"aclocal --install\" is used, and the first directory specified with\n    '-I' is non-existent, aclocal will now create it before trying to copy\n    files in it.\n\n  - An empty declaration of a \"foo_PRIMARY\" no longer cause the generated\n    install rules to create an empty $(foodir) directory; for example, if\n    Makefile.am contains something like:\n\n      pkglibexec_SCRIPTS =\n      if FALSE\n      pkglibexec_SCRIPTS += bar.sh\n      endif\n\n    the $(pkglibexec) directory will not be created upon \"make install\".\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.11.3:\n\n* Miscellaneous changes:\n\n  - Automake's own build system is more silent by default, making use of\n    the 'silent-rules' option.\n\n  - The master copy of the 'gnupload' script is now maintained in gnulib,\n    not in automake.\n\n  - The 'missing' script no longer tries to wrap calls to 'tar'.\n\n  - \"make dist\" no longer wraps 'tar' invocations with the 'missing'\n    script.  Similarly, the obsolescent variable '$(AMTAR)' (which you\n    shouldn't be using BTW ;-) no longer invokes the 'missing' script\n    to wrap tar, but simply invokes the 'tar' program itself.\n    The TAR environment variable overrides.\n\n  - \"make dist\" can now create lzip-compressed tarballs.\n\n  - In the Automake info documentation, the Top node and the nodes about\n    the invocation of the automake and aclocal programs have been renamed;\n    now, calling \"info automake\" will open the Top node, while calling\n    \"info automake-invocation\" and \"info aclocal-invocation\" will access\n    the nodes about the invocation of respectively automake and aclocal.\n\n  - Automake is now distributed as a gzip-compressed and an xz-compressed\n    tarball.  Previously, bzip2 was used instead of xz.\n\n  - The last relics of Python 1.5 support have been removed from the\n    AM_PATH_PYTHON macro.\n\n  - For programs and libraries, automake now detects EXTRA_foo_DEPENDENCIES\n    and adds them to the normal list of dependencies, but without\n    overwriting the foo_DEPENDENCIES variable, which is normally computed\n    by automake.\n\nBugs fixed in 1.11.3:\n\n* Bugs introduced by 1.11.2:\n\n  - Automake now correctly recognizes the prefix/primary combination\n   'pkglibexec_SCRIPTS' as valid.\n\n  - The parallel-tests harness no longer trips on sed implementations\n    with stricter limits on the length of input lines (problem seen at\n    least on Solaris 8).\n\n* Long-standing bugs:\n\n  - The \"deleted header file problem\" for *.am files is avoided by stub\n    rules.  This allows 'make' to trigger a rerun of 'automake' also if\n    some previously needed '.am' file has been removed.\n\n  - The 'silent-rules' option now generates working makefiles even\n    for the uncommon 'make' implementations that do not support the\n    nested-variables extension to POSIX 2008.  For such 'make'\n    implementations, whether a build is silent is determined at\n    configure time, and cannot be overridden at make time with\n    \"make V=0\" or \"make V=1\".\n\n  - Vala support now works better in VPATH setups.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.11.2:\n\n* Changes to aclocal:\n\n  - The `--acdir' option is deprecated.  Now you should use the new options\n    `--automake-acdir' and `--system-acdir' instead.\n\n  - The `ACLOCAL_PATH' environment variable is now interpreted as a\n    colon-separated list of additional directories to search after the\n    automake internal acdir (by default ${prefix}/share/aclocal-APIVERSION)\n    and before the system acdir (by default ${prefix}/share/aclocal).\n\n* Miscellaneous changes:\n\n  - The Automake support for automatic de-ANSI-fication has been\n    deprecated.  It will probably be removed in the next major Automake\n    release (1.12).\n\n  - The `lzma' compression scheme and associated automake option `dist-lzma'\n    is obsoleted by `xz' and `dist-xz' due to upstream changes.\n\n  - You may adjust the compression options used in dist-xz and dist-bzip2.\n    The default is now merely -e for xz, but still -9 for bzip;  you may\n    specify a different level via the XZ_OPT and BZIP2 envvars respectively.\n    E.g., \"make dist-xz XZ_OPT=-7\" or \"make dist-bzip2 BZIP2=-5\"\n\n  - The `compile' script now converts some options for MSVC for a better\n    user experience.  Similarly, the new `ar-lib' script wraps Microsoft lib.\n\n  - The py-compile script now accepts empty arguments passed to the options\n    `--destdir' and `--basedir', and complains about unrecognized options.\n    Moreover, a non-option argument or a special `--' argument terminates\n    the list of options.\n\n  - A developer that needs to pass specific flags to configure at \"make\n    distcheck\" time can now, and indeed is advised to, do so by defining\n    the developer-reserved makefile variable AM_DISTCHECK_CONFIGURE_FLAGS,\n    instead of the old DISTCHECK_CONFIGURE_FLAGS.\n    The DISTCHECK_CONFIGURE_FLAGS variable should now be reserved for the\n    user; still, the old Makefile.am files that used to define it will\n    still continue to work as before.\n\n  - New macro AM_PROG_AR that looks for an archiver and wraps it in the new\n    'ar-lib' auxiliary script if the selected archiver is Microsoft lib.\n    This new macro is required for LIBRARIES and LTLIBRARIES when automake\n    is run with -Wextra-portability and -Werror.\n\n  - When using DejaGnu-based testsuites, the user can extend the `site.exp'\n    file generated by automake-provided rules by defining the special make\n    variable `$(EXTRA_DEJAGNU_SITE_CONFIG)'.\n\n  - The `install-info' rule can now be instructed not to create/update\n    the `${infodir}/dir' file, by exporting the new environment variable\n    `AM_UPDATE_INFO_DIR' to the value \"no\".\n\nBugs fixed in 1.11.2:\n\n* Bugs introduced by 1.11:\n\n  - The parallel-tests driver no longer produces erroneous results with\n    Tru64/OSF 5.1 sh upon unreadable log files.\n\n  - The `parallel-tests' test driver does not report spurious successes\n    when used with concurrent FreeBSD make (e.g., \"make check -j3\").\n\n  - When the parallel-tests driver is in use, automake now explicitly\n    rejects invalid entries and conditional contents in TEST_EXTENSIONS,\n    instead of issuing confusing and apparently unrelated error messages\n    (e.g., \"non-POSIX variable name\", \"bad characters in variable name\",\n    or \"redefinition of TEST_EXTENSIONS), or even, in some situations,\n    silently producing broken `Makefile.in' files.\n\n  - The `silent-rules' option now truly silences all compile rules, even\n    when dependency tracking is disabled.  Also, when `silent-rules' is\n    not used, `make' output no longer contains spurious backslash-only\n    lines, thus once again matching what Automake did before 1.11.\n\n  - The AM_COND_IF macro also works if the shell expression for the\n    conditional is no longer valid for the condition.\n\n* Long-standing bugs:\n\n  - The order of Yacc and Lex flags is fixed to be consistent with other\n    languages: $(AM_YFLAGS) comes before $(YFLAGS), and $(AM_LFLAGS) before\n    $(LFLAGS), so that the user variables override the developer variables.\n\n  - \"make distcheck\" now correctly complains also when \"make uninstall\"\n    leaves one and only one file installed in $(prefix).\n\n  - A \"make uninstall\" issued before a \"make install\", or after a mere\n    \"make install-data\" or a mere \"make install-exec\" does not spuriously\n    fail anymore.\n\n  - Automake now warns about more primary/directory invalid combinations,\n    such as \"doc_LIBRARIES\" or \"pkglib_PROGRAMS\".\n\n  - Rules generated by Automake now try harder to not change any files when\n    `make -n' is invoked.  Fixes include compilation of Emacs Lisp, Vala, or\n    Yacc source files and the rule to update config.h.\n\n  - Several scripts and the parallel-tests testsuite driver now exit with\n    the right exit status upon receiving a signal.\n\n  - A per-Makefile.am setting of -Werror does not erroneously carry over\n    to the handling of other Makefile.am files.\n\n  - The code for automatic dependency tracking works around a Solaris\n    make bug triggered by sources containing repeated slashes when the\n    `subdir-objects' option was used.\n\n  - The makedepend and hp depmodes now work better with VPATH builds.\n\n  - Java sources specified with check_JAVA are no longer compiled for\n    \"make all\", but only for \"make check\".\n\n  - An usage like \"java_JAVA = foo.java\" will now cause Automake to warn\n    and error out if `javadir' is undefined, instead of silently producing\n    a broken Makefile.in.\n\n  - aclocal and automake now honour the configure-time definitions of\n    AUTOCONF and AUTOM4TE when they spawn autoconf or autom4te processes.\n\n  - The `install-info' recipe no longer tries to guess whether the\n    `install-info' program is from Debian or from GNU, and adaptively\n    change its behaviour; this has proven to be frail and easy to\n    regress.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBugs fixed in 1.11.1:\n\n  - Lots of minor bugfixes.\n\n* Bugs introduced by 1.11:\n\n  - The `parallel-tests' test driver works around a GNU make 3.80 bug with\n    trailing white space in the test list (`TESTS = foo $(EMPTY)').\n\n* Long standing bugs:\n\n  - On Darwin 9, `pythondir' and `pyexecdir' pointed below `/Library/Python'\n    even if the `--prefix' argument pointed outside of a system directory.\n    AM_PATH_PYTHON has been fixed to ignore the value returned from python's\n    `get_python_lib' function if it points outside the configured prefix,\n    unless the `--prefix' argument was either `/usr' or below `/System'.\n\n  - The testsuite does not try to change the mode of `ltmain.sh' files from\n    a Libtool installation (symlinked to test directories) any more.\n\n  - AM_PROG_GCJ uses AC_CHECK_TOOLS to look for `gcj' now, so that prefixed\n    tools are preferred in a cross-compile setup.\n\n  - The distribution is tarred up with mode 755 now by the `dist*' targets.\n    This fixes a race condition where untrusted users could modify files\n    in the $(PACKAGE)-$(VERSION) distdir before packing if the toplevel\n    build directory was world-searchable.  This is CVE-2009-4029.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.11:\n\n* Version requirements:\n\n  - Autoconf 2.62 or greater is required.\n\n* Changes to aclocal:\n\n  - The autoconf version check implemented by aclocal in aclocal.m4\n    (and new in Automake 1.10) is degraded to a warning.  This helps\n    in the common case where the Autoconf versions used are compatible.\n\n* Changes to automake:\n\n  - The automake program can run multiple threads for creating most\n    Makefile.in files concurrently, if at least Perl 5.7.2 is available\n    with interpreter-based threads enabled.  Set the environment variable\n    AUTOMAKE_JOBS to the maximum number of threads to use, in order to\n    enable this experimental feature.\n\n* Changes to Libtool support:\n\n  - Libtool generic flags are now passed to the install and uninstall\n    modes as well.\n\n  - distcheck works with Libtool 2.x even when LT_OUTPUT is used, as\n    config.lt is removed correctly now.\n\n* Languages changes:\n\n  - subdir-object mode works now with Fortran (F77, FC, preprocessed\n    Fortran, and Ratfor).\n\n  - For files with extension .f90, .f95, .f03, or .f08, the flag\n    $(FCFLAGS_f[09]x) computed by AC_FC_SRCEXT is now used in compile rules.\n\n  - Files with extension .sx are also treated as preprocessed assembler.\n\n  - The default source file extension (.c) can be overridden with\n    AM_DEFAULT_SOURCE_EXT now.\n\n  - Python 3.0 is supported now, Python releases prior to 2.0 are no\n    longer supported.\n\n  - AM_PATH_PYTHON honors python's idea about the site directory.\n\n  - There is initial support for the Vala programming language, when using\n    Vala 0.7.0 or later.\n\n* Miscellaneous changes:\n\n  - Automake development is done in a git repository on Savannah now, see\n\n      https://git.sv.gnu.org/gitweb/?p=automake.git\n\n    A read-only CVS mirror is provided at\n\n      cvs -d :pserver:anonymous@pserver.git.sv.gnu.org:/automake.git \\\n          checkout -d automake HEAD\n\n  - \"make dist\" can now create xz-compressed tarballs,\n    as well as (deprecated?) lzma-compressed tarballs.\n\n  - `automake --add-missing' will by default install the GPLv3 file as\n    COPYING if it is missing.  It will also warn that the license file\n    should be added to source control.  Note that Automake will never\n    overwrite an existing COPYING file, even when the `--force-missing'\n    option is used.\n\n  - The manual is now distributed under the terms of the GNU FDL 1.3.\n\n  - Automake ships and installs man pages for automake and aclocal now.\n\n  - New shorthand `$(pkglibexecdir)' for `$(libexecdir)/@PACKAGE@'.\n\n  - install-sh supports -C, which does not update the installed file\n    (and its time stamps) if the contents did not change.\n\n  - The `gnupload' script has been revamped.\n\n  - The `depcomp' and `compile' scripts now work with MSVC under MSYS.\n\n  - The targets `install' and `uninstall' are more efficient now, in that\n    for example multiple files from one Automake variable such as\n    `bin_SCRIPTS' are copied in one `install' (or `libtool --mode=install')\n    invocation if they do not have to be renamed.\n\n    Both install and uninstall may sometimes enter (`cd' into) the target\n    installation directory now, when no build-local scripts are used.\n\n    Both install and uninstall do not fail anymore but do nothing if an\n    installation directory variable like `bindir' is set to the empty string.\n\n    For built-in rules, `make install' now fails reliably if installation\n    of a file failed.  Conversely, `make uninstall' even succeeds when\n    issued multiple times.\n\n    These changes may need some adjustments from users:  For example,\n    some `install' programs refuse to install multiple copies of the\n    same file in one invocation, so you may need to remove duplicate\n    entries from file lists.\n\n    Also, within one set of files, say, nobase_data_DATA, the order of\n    installation may be changed, or even unstable among different hosts,\n    due to the use of associative arrays in awk.  The increased use of\n    awk matches a similar move in Autoconf to provide for better scaling.\n\n    Further, most undocumented per-rule install command variables such as\n    binSCRIPT_INSTALL have been removed because they are not needed any\n    more.  Packages which use them should be using the appropriate one of\n    INSTALL_{DATA,PROGRAM,SCRIPT} or their install_sh_{DATA,PROGRAM,SCRIPT}\n    counterpart, depending on the type of files and the need for automatic\n    target directory creation.\n\n  - The \"deleted header file problem\" for *.m4 files is avoided by\n    stub rules.  This allows `make' to trigger a rerun of `aclocal'\n    also if some previously needed macro file has been removed.\n\n  - Rebuild rules now also work for a removed `subdir/Makefile.in' in\n    an otherwise up to date tree.\n\n  - The `color-tests' option causes colored test result output on terminals.\n\n  - The `parallel-tests' option enables a new test driver that allows for\n    parallel test execution, inter-test dependencies, lazy test execution\n    for unit-testing, re-testing only failed tests, and formatted result output\n    as RST (reStructuredText) and HTML.  Enabling this option may require some\n    changes to your test suite setup; see the manual for details.\n\n  - The `silent-rules' option enables Linux kernel-style silent build output.\n    This option requires the widely supported but non-POSIX `make' feature\n    of recursive variable expansion, so do not use it if your package needs\n    to build with `make' implementations that do not support it.\n\n    To enable less verbose build output, the developer has to use the Automake\n    option `silent-rules' in `AM_INIT_AUTOMAKE', or call the `AM_SILENT_RULES'\n    macro.  The user may then set the default verbosity by passing the\n    `--enable-silent-rules' option to `configure'.  At `make' run time, this\n    default may be overridden using `make V=0' for less verbose, and `make V=1'\n    for backward-compatible verbose output.\n\n  - New prefix `notrans_' for manpages which should not be transformed\n    by --program-transform.\n\n  - New macro AM_COND_IF for conditional evaluation and conditional\n    config files.\n\n  - For AC_CONFIG_LINKS, if source and destination are equal, do not\n    remove the file in a non-VPATH build.  Such setups work with Autoconf\n    2.62 or newer.\n\n  - AM_MAINTAINER_MODE now allows for an optional argument specifying\n    the default setting.\n\n  - AM_SUBST_NOTMAKE may prevent substitution of AC_SUBSTed variables,\n    useful especially for multi-line values.\n\n  - Automake's early configure-time sanity check now diagnoses an\n    unsafe absolute source directory name and makes configure fail.\n\n  - The Automake macros and rules cope better with whitespace in the\n    current directory name, as long as the relative path to `configure'\n    does not contain whitespace.  To this end, the values of `$(MISSING)'\n    and `$(install_sh)' may contain suitable quoting, and their expansion\n    might need `eval'uation if used outside of a makefile.  These\n    undocumented variables may be used in several documented macros such\n    as $(AUTOCONF) or $(MAKEINFO).\n\nBugs fixed in 1.11:\n\n* Long-standing bugs:\n\n  - Fix aix dependency tracking for libtool objects.\n\n  - Work around AIX sh quoting issue in AC_PROG_CC_C_O, leading to\n    unnecessary use of the `compile' script.\n\n  - For nobase_*_LTLIBRARIES with nonempty directory components, the\n    correct `-rpath' argument is used now.\n\n  - `config.status --file=Makefile depfiles' now also works with the\n    extra quoting used internally by Autoconf 2.62 and newer\n    (it used to work only without the `--file=' bit).\n\n  - The `missing' script works better with versioned tool names.\n\n  - Semantics for `missing help2man' have been revamped:\n\n    Previously, if `help2man' was not present, `missing help2man' would have\n    the following semantics: if some man page was out of date but present, then\n    a warning would be printed, but the exit status was 0.  If the man page was\n    not present at all, then `missing' would create a replacement man page\n    containing an error message, and exit with a status of 2.  This does not play\n    well with `make': the next run will see this particular man page as being up\n    to date, and will only error out on the next generated man page, if any;\n    repeat until all pages are done.  This was not desirable.\n\n    These are the new semantics: if some man page is not present, and help2man\n    is not either, then `missing' will warn and generate the replacement page\n    containing the error message, but exit successfully.  However, `make dist'\n    will ensure that no such bogus man pages are packaged into a tarball.\n\n  - Targets provided by automake behave better with `make -n', in that they\n    take care not to create files.\n\n  - `config.status Makefile... depfiles' works fine again in the presence of\n    disabled dependency tracking.\n\n  - The default no-op recursive rules for these targets also work with BSD make\n    now: html, install-html, install-dvi, install-pdf, install-pdf, install-info.\n\n  - `make distcheck' works also when both a directory and some file below it\n    have been added to a distribution variable, such as EXTRA_DIST or *_SOURCES.\n\n  - Texinfo dvi, ps, pdf, and html output files are not removed upon\n    `make mostlyclean' any more; only the LaTeX by-products are.\n\n  - Renamed objects also work with the `subdir-objects' option and\n    source file languages which Automake does not know itself.\n\n  - `automake' now correctly complains about variable assignments which are\n    preceded by a comment, extend over multiple lines with backslash-escaped\n    newlines, and end in a comment sign.  Previous versions would silently\n    and wrongly ignore such assignments completely.\n\n* Bugs introduced by 1.10:\n\n  - Fix output of dummy dependency files in presence of post-processed\n    Makefile.in's again, but also cope with long lines.\n\n  - $(EXEEXT) is automatically appended to filenames of XFAIL_TESTS\n    that have been declared as programs in the same Makefile.\n    This is for consistency with the analogous change to TESTS in 1.10.\n\n  - Fix order of standard includes to again be `-I. -I$(srcdir)',\n    followed by directories containing config headers.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.10:\n\n* Version requirements:\n\n  - Autoconf 2.60 or greater is required.\n\n  - Perl 5.6 or greater is required.\n\n* Changes to aclocal:\n\n  - aclocal now also supports -Wmumble and -Wno-mumble options.\n\n  - `dirlist' entries (for the aclocal search path) may use shell\n    wildcards such as `*', `?', or `[...]'.\n\n  - aclocal supports an --install option that will cause system-wide\n    third-party macros to be installed in the local directory\n    specified with the first -I flag.  This option also uses #serial\n    lines in M4 files to upgrade local macros.\n\n    The new aclocal options --dry-run and --diff help to review changes\n    before they are installed.\n\n  - aclocal now outputs an autoconf version check in aclocal.m4 in\n    projects using automake.\n\n    For a few years, automake and aclocal have been calling autoconf\n    (or its underlying engine autom4te) to accurately retrieve the\n    data they need from configure.ac and its siblings.  Doing so can\n    only work if all autotools use the same version of autoconf.  For\n    instance a Makefile.in generated by automake for one version of\n    autoconf may stop working if configure is regenerated with another\n    version of autoconf, and vice versa.\n\n    This new version check ensures that the whole build system has\n    been generated using the same autoconf version.\n\n* Support for new Autoconf macros:\n\n  - The new AC_REQUIRE_AUX_FILE Autoconf macro is supported.\n\n  - If `subdir-objects' is set, and AC_CONFIG_LIBOBJ_DIR is specified,\n    $(LIBOBJS), $(LTLIBOBJS), $(ALLOCA), and $(LTALLOCA) can be used\n    in different directories.  However, only one instance of such a\n    library objects directory is supported.\n\n* Change to Libtool support:\n\n  - Libtool generic flags (those that go before the --mode=MODE option)\n    can be specified using AM_LIBTOOLFLAGS and target_LIBTOOLFLAGS.\n\n* Yacc and Lex changes:\n\n  - The rebuild rules for distributed Yacc and Lex output will avoid\n    overwriting existing files if AM_MAINTAINER_MODE and maintainer-mode\n    is not enabled.\n\n  - ylwrap is now always used for lex and yacc source files,\n    regardless of whether there is more than one source per directory.\n\n* Languages changes:\n\n  - Preprocessed assembler (*.S) compilation now honors CPPFLAGS,\n    AM_CPPFLAGS and per-target _CPPFLAGS, and supports dependency\n    tracking, unlike non-preprocessed assembler (*.s).\n\n  - subdir-object mode works now with Assembler.  Automake assumes\n    that the compiler understands `-c -o'.\n\n  - Preprocessed assembler (*.S) compilation now also honors\n    $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES).\n\n  - Improved support for Objective C:\n    - Autoconf's new AC_PROG_OBJC will enable automatic dependency tracking.\n    - A new section of the manual documents the support.\n\n  - New support for Unified Parallel C:\n    - AM_PROG_UPC looks for a UPC compiler.\n    - A new section of the manual documents the support.\n\n  - Per-target flags are now correctly handled in link rules.\n\n    For instance maude_CFLAGS correctly overrides AM_CFLAGS; likewise\n    for maude_LDFLAGS and AM_LDFLAGS.  Previous versions bogusly\n    preferred AM_CFLAGS over maude_CFLAGS while linking, and they\n    used both AM_LDFLAGS and maude_LDFLAGS on the same link command.\n\n    The fix for compiler flags (i.e., using maude_CFLAGS instead of\n    AM_CFLAGS) should not hurt any package since that is how _CFLAGS\n    is expected to work (and actually works during compilation).\n\n    However using maude_LDFLAGS \"instead of\" AM_LDFLAGS rather than\n    \"in addition to\" breaks backward compatibility with older versions.\n    If your package used both variables, as in\n\n      AM_LDFLAGS = common flags\n      bin_PROGRAMS = a b c\n      a_LDFLAGS = more flags\n      ...\n\n    and assumed *_LDFLAGS would sum up, you should rewrite it as\n\n      AM_LDFLAGS = common flags\n      bin_PROGRAMS = a b c\n      a_LDFLAGS = $(AM_LDFLAGS) more flags\n      ...\n\n    This new behavior of *_LDFLAGS is more coherent with other\n    per-target variables, and the way *_LDFLAGS variables were\n    considered internally.\n\n* New installation targets:\n\n  - New targets mandated by GNU Coding Standards:\n      install-dvi\n      install-html\n      install-ps\n      install-pdf\n    By default they will only install Texinfo manuals.\n    You can customize them with *-local variants:\n      install-dvi-local\n      install-html-local\n      install-ps-local\n      install-pdf-local\n\n  - The undocumented recursive target `uninstall-info' no longer exists.\n    (`uninstall' is in charge of removing all possible documentation\n    flavors, including optional formats such as dvi, ps, or info even\n    when `no-installinfo' is used.)\n\n* Miscellaneous changes:\n\n  - Automake no longer complains if input files for AC_CONFIG_FILES\n    are specified using shell variables.\n\n  - clean, distribution, or rebuild rules are normally disabled for\n    inputs and outputs of AC_CONFIG_FILES, AC_CONFIG_HEADERS, and\n    AC_CONFIG_LINK specified using shell variables.  However, if these\n    variables are used as ${VAR}, and AC_SUBSTed, then Automake will\n    be able to output rules anyway.\n    (See the Automake documentation for AC_CONFIG_FILES.)\n\n  - $(EXEEXT) is automatically appended to filenames of TESTS\n    that have been declared as programs in the same Makefile.\n    This is mostly useful when some check_PROGRAMS are listed in TESTS.\n\n  - `-Wportability' has finally been turned on by default for `gnu' and\n    `gnits' strictness.  This means, automake will complain about %-rules\n    or $(GNU Make functions) unless you switch to `foreign' strictness or\n    use `-Wno-portability'.\n\n  - Automake now uses AC_PROG_MKDIR_P (new in Autoconf 2.60), and uses\n    $(MKDIR_P) instead of $(mkdir_p) to create directories.  The\n    $(mkdir_p) variable is still defined (to the same value as\n    $(MKDIR_P)) but should be considered obsolete.  If you are using\n    $(mkdir_p) in some of your rules, please plan to update them to\n    $(MKDIR_P) at some point.\n\n  - AM_C_PROTOTYPES and ansi2knr are now documented as being obsolete.\n    They still work in this release, but may be withdrawn in a future one.\n\n  - Inline compilation rules for gcc3-style dependency tracking are\n    more readable.\n\n  - Automake installs a \"Hello World!\" example package in $(docdir).\n    This example is used throughout the new \"Autotools Introduction\"\n    chapter of the manual.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.9:\n\n* Makefile.in bloat reduction:\n\n  - Inference rules are used to compile sources in subdirectories when\n    the `subdir-objects' option is used and no per-target flags are\n    used.  This should reduce the size of some projects a lot, because\n    Automake used to output an explicit rule for each such object in\n    the past.\n\n  - Automake no longer outputs three rules (.o, .obj, .lo) for each\n    object that must be built with explicit rules.  It just outputs\n    the rules required to build the kind of object considered: either\n    the two .o and .obj rules for usual objects, or the .lo rule for\n    libtool objects.\n\n* Change to Libtool support:\n\n  - Libtool tags are used with libtool versions that support them.\n    (I.e., with Libtool 1.5 or greater.)\n\n  - Automake is now able to handle setups where a libtool library is\n    conditionally installed in different directories, as in\n\n      if COND\n        lib_LTLIBRARIES = liba.la\n      else\n        pkglib_LTLIBRARIES = liba.la\n      endif\n      liba_la_SOURCES = ...\n\n* Changes to aclocal:\n\n  - aclocal now ensures that AC_DEFUNs and AU_DEFUNs it discovers are\n    really evaluated, before it decides to include them in aclocal.m4.\n    This solves nasty problems with conditional redefinitions of\n    Autoconf macros in /usr/share/aclocal/*.m4 files causing extraneous\n    *.m4 files to be included in any project using these macros.\n    (Calls to AC_PROG_EGREP causing libtool.m4 to be included is the\n    most famous instance of this bug.)\n\n  - Do not complain about missing conditionally AC_REQUIREd macros\n    that are not actually used.  In 1.8.x aclocal would correctly\n    determine which of these macros were really needed (and include\n    only these in the package); unfortunately it would also require\n    all of them to be present in order to run.  This created\n    situations were aclocal would not work on a tarball distributing\n    all the macros it uses.  For instance running aclocal on a project\n    containing only the subset of the Gettext macros in use by the\n    project did not work, because gettext conditionally requires other\n    macros.\n\n* Portability improvements:\n\n  - Tar format can be chosen with the new options tar-v7, tar-ustar, and\n    tar-pax.  The new option filename-length-max=99 helps diagnosing\n    filenames that are too long for tar-v7.  (PR/414)\n\n  - Variables augmented with `+=' are now automatically flattened (i.e.,\n    trailing backslashes removed) and then wrapped around 80 columns\n    (adding trailing backslashes).  In previous versions, a long series\n    of\n      VAR += value1\n      VAR += value2\n      VAR += value3\n      ...\n    would result in a single-line definition of VAR that could possibly\n    exceed the maximum line length of some make implementations.\n\n    Non-augmented variables are still output as they are defined in\n    the Makefile.am.\n\n* Miscellaneous:\n\n  - Support Fortran 90/95 with the new \"fc\" and \"ppfc\" languages.\n    Works the same as the old Fortran 77 implementation; just replace\n    F77 with FC everywhere (exception: FFLAGS becomes FCFLAGS).\n    Requires a version of autoconf which provides AC_PROG_FC (>=2.59).\n\n  - Support for conditional _LISP.\n\n  - Support for conditional -hook and -local rules (PR/428).\n\n  - Diagnose AC_CONFIG_AUX_DIR calls following AM_INIT_AUTOMAKE. (PR/49)\n\n  - Automake will not write any Makefile.ins after the first error it\n    encounters.  The previous Makefile.ins (if any) will be left in\n    place.  (Warnings will not prevent output, but remember they can\n    be turned into errors with -Werror.)\n\n  - The restriction that SUBDIRS must contain direct children is gone.\n    Do not abuse.\n\n  - The manual tells more about SUBDIRS vs. DIST_SUBDIRS.\n    It also gives an example of nested packages using AC_CONFIG_SUBDIRS.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBugs fixed in 1.8.5:\n\n* Long-standing bugs:\n\n  - Define DIST_SUBDIRS even when the `no-dist' or `cygnus' options are used\n    so that `make distclean' and `make maintainer-clean' can work.\n\n  - Define AR and ARFLAGS even when only EXTRA_LIBRARIES are defined.\n\n  - Fix many rules to please FreeBSD make, which runs commands with `sh -e'.\n\n  - Polish diagnostic when no input file is found.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBugs fixed in 1.8.4:\n\n* Long-standing bugs:\n\n  - Fix AM_PATH_PYTHON to correctly display $PYTHON when it has been\n    overridden by the user.\n\n  - Honor PATH_SEPARATOR in various places of the Automake package, for\n    the sake of OS/2.\n\n  - Adjust dependency tracking mode detection to ICC 8.0's new output.\n    (PR/416)\n\n  - Fix install-sh so it can install the `mv' binary... using `mv'.\n\n  - Fix tru64 dependency tracking for libtool objects.\n\n  - Work around Exuberant Ctags when creating a TAGS files in a directory\n    without files to scan but with subdirectories to include.\n\n* Bugs introduced by 1.8:\n\n  - Fix an \"internal error\" when @LIBOBJS@ is used in a variable that is\n    not defined in the same conditions as the _LDADD that uses it.\n\n  - Do not warn when JAVAROOT is overridden, this is legitimate.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBugs fixed in 1.8.3:\n\n* Long-standing bugs:\n\n  - Quote filenames in installation rules, in case $DESTDIR, $prefix,\n    or any of the other *dir variables contain a space.\n\n    Please note that Automake does not and cannot support spaces in\n    filenames that are involved during the build.  This change affects\n    only installation paths, so that `make install' does not bomb out\n    in packages configured with\n      ./configure --prefix '/c/Program Files'\n\n  - Fix the depfiles output so it works with GNU sed (<4.1) even when\n    POSIXLY_CORRECT is set.\n\n  - Do not AC_SUBST(LIBOBJS) in AM_WITH_REGEX.  This macro was unusable\n    since Autoconf 2.54, which defines LIBOBJS itself.\n\n  - Fix a potential (but unlikely) race condition in parallel elisp\n    builds.  (Introduced in 1.7.3.)\n\n  - Do not assume that users override _DEPENDENCIES in all conditions\n    where Automake will try to define them.\n\n  - Do not use `mkdir -p' in mkinstalldirs, unless this is GNU mkdir.\n    Solaris 8's `mkdir -p' is not thread-safe and can break parallel\n    builds.\n\n    This fix also affects the $(mkdir_p) variable defined since\n    Automake 1.8.  It will be set to `mkdir -p' only if mkdir is GNU\n    mkdir, and to `mkinstalldirs' or `install-sh -d' otherwise.\n\n  - Secure temporary directory creation in `make distcheck'. (PR/413)\n\n  - Do not generate two build rules for `parser.h' when the\n    parser appears in two different conditionals.\n\n  - Work around a Solaris 8 /bin/sh bug in the test for dependency\n    checking.  Usually ./configure will not pick this shell; so this\n    fix only helps cases where the shell is forced to /bin/sh.\n\n* Bugs introduced by 1.8:\n\n  - In some situations (hand-written `m4_include's), aclocal would\n    call the `File::Spec->rel2abs' method, which was only introduced\n    in Perl 5.6.  This new version reestablish support Perl 5.005.\n\n    It is likely that the next major Automake releases will require at\n    least Perl 5.6.  Consider upgrading your development environment\n    if you are still using the five-year-old Perl 5.005.\n\n  - Automake would sometimes fail to define rules for targets listed\n    in variables defined in multiple conditions.  For instance on\n      if C1\n\tbin_PROGRAMS = a\n      else\n\tbin_PROGRAMS = b\n      endif\n    it would define only the `a.$(OBJEXT): a.c' rule and omit the\n    `b.$(OBJEXT): b.c' rule.\n\n* New sections in manual:\n\n  - Third-Party Makefiles: how to interface third party Makefiles.\n  - Upgrading: upgrading packages to newer Automake versions.\n  - Multiple Outputs: handling tools that produce many outputs.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBug fixed in 1.8.2:\n\n* A (well known) portability bug slipped in the changes made to\n  install-sh in Automake 1.8.1.  The broken install-sh would refuse to\n  install anything on Tru64.\n\n* Fix install rules for conditionally built python files.  (This never\n  really worked.)\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBug fixed in 1.8.1:\n\n* Bugs introduced by 1.8:\n\n  - Fix Config.pm import error with old Perl versions (at least\n    5.005_03).  One symptom is that aclocal could not find its macro\n    directory.\n\n  - Automake 1.8 used `mkdir -m 0755 -p --' to ensure that directories\n    created by `make install' are always world readable, even if the\n    installer happens to have an overly restrictive umask (e.g. 077).\n    This was a mistake and has been reverted.  There are at least two\n    reasons why we must not use `-m 0755':\n      - it causes special bits like SGID to be ignored,\n      - it may be too restrictive (some setups expect 775 directories).\n\n  - Fix aclocal to honor definitions located in files which have been\n    m4_included manually.  aclocal 1.8 had been updated to check\n    m4_included files for new requirements, but forgot that these\n    m4_included files can also provide new definitions.\n\n    Note that if you have such a setup, we recommend you get rid of\n    it.  In the past, there was a reason to m4_include files manually:\n    aclocal used to duplicate entire M4 files into aclocal.m4, even\n    files that were distributed.  Some packages were therefore\n    m4_including the distributed file directly, and playing some\n    tricks to ensure aclocal would not copy that file to aclocal.m4,\n    in order to limit the amount of duplication.  Since aclocal 1.8.x\n    will precisely output m4_includes for local M4 files, we recommend\n    that you clean up your setup, removing all manual m4_includes and\n    letting aclocal output them.\n\n  - Output detailed menus in the Info version if the Automake manual,\n    so that Emacs can locate the indexes.\n\n  - configure.ac and configure were listed twice in DIST_COMMON (an\n    internal variable where Automake lists configury files to\n    distribute).  This was harmless, but unaesthetic.\n\n  - Use `chmod a-w' instead of `chmod -w' as the latter honors umask.\n    This was an issue only in the Automake package itself, not in\n    its output.\n\n  - Automake assumed that all AC_CONFIG_LINKS arguments had the form\n    DEST:SRC.  This was wrong, as some packages do\n    AC_CONFIG_LINKS($computedlinks).  This version no longer abort in\n    that situation.\n\n  - Contrary to mkinstalldirs, $(mkdir_p) was expecting exactly one\n    argument.  This caused two kinds of failures:\n      - Rules installing data in a conditionally defined directory\n        failed when that directory was undefined.  In this case no\n        argument was supplied.\n      - `make installdirs' failed, because several directories were\n        passed to $(mkdir_p).  This was an issue only on platform\n        were $(mkdir_p) is implemented with `install-sh -d'.\n    $(mkdir_p) as been changed to accept 0 or more arguments, as\n    mkinstalldirs did.\n\n* Long-standing bugs:\n\n  - Fix an unexpected diagnostic occurring when users attempt\n    to override some internal variables that Automake appends to.\n\n  - aclocal now scans configure.ac for macro definitions (PR/319).\n\n  - Fix a portability issue with OSF1/Tru64 Make.  If a directory\n    distributes files which are outside itself (this usually occurs\n    when using AC_CONFIG_AUX_DIR([../dir]) to use auxiliary files\n    from a parent package), then `make distcheck' fails due to an\n    optimization performed by OSF1/Tru64 Make in its VPATH handling.\n    (tests/subpkg2.test failure)\n\n  - Fix another portability issue with Sun and OSF1/Tru64 Make.\n    In a VPATH-build configuration, `make install' would install\n    nobase_ files to wrong locations.\n\n  - Fix a Perl `uninitialized value' diagnostic occurring when\n    automake complains that a Texinfo file does not have a\n    @setfilename statement.\n\n  - Erase config.status.lineno during `make distclean'.  This file\n    can be created by config.status.  Automake already knew about\n    configure.lineno, but forgot config.status.lineno.\n\n  - Distribute all files, even those which are built and installed\n    conditionally.  This change affects files listed in conditionally\n    defined *_HEADERS and *_PYTHON variable (unless they are nodist_*)\n    as well as those listed in conditionally defined dist_*_DATA,\n    dist_*_JAVA, dist_*_LISP, and dist_*_SCRIPTS variables.\n\n  - Fix AM_PATH_LISPDIR to avoid \\? in sed regular expressions; it\n    doesn't conform to POSIX.\n\n  - Normalize help strings for configure variables and options added\n    by Automake macros.\n\n* Anticipation:\n\n  - Check for python2.4 in AM_PATH_PYTHON.\n\n* Spurious failures in test suite:\n\n  - tests/libtool5.test, tests/ltcond.test, tests/ltcond2.test,\n    tests/ltconv.test: fix failures with CVS Libtool.\n  - tests/aclocal6.test: fix failure if autom4te.cache is disabled.\n  - tests/txinfo24.test, tests/txinfo25.test, tests/txinfo28.test:\n    fix failures with old Texinfo versions.\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nNew in 1.8:\n\n* Meta-News\n\n  - The NEWS file is more verbose.\n\n* Requirements\n\n  - Autoconf 2.58 or greater is required.\n\n* New features\n\n  - Default source file names in the absence of a _SOURCES declaration\n    are made by removing any target extension before appending `.c', so\n    to make the libtool module `foo.la' from `foo.c', you only need to\n    do this:\n\n\tlib_LTLIBRARIES = foo.la\n\tfoo_la_LDFLAGS  = -module\n\n    For backward compatibility, foo_la.c will be used instead of\n    foo.c if this file exists or is the explicit target of a rule.\n    However -Wobsolete will warn about this deprecated naming.\n\n  - AR's `cru' flags are now set in a global ARFLAGS variable instead\n    of being hard-coded in each $(AR) invocation, so they can be\n    substituted from configure.ac.  This has been requested by people\n    dealing with non-POSIX ar implementations.\n\n  - New warning option: -Woverride.  This will warn about any user\n    target or variable definitions which override Automake\n    definitions.\n\n  - Texinfo rules back up and restore info files when makeinfo fails.\n\n  - Texinfo rules now support the `html' target.\n    Running this requires Texinfo 4.0 or greater.\n\n    `html' is a new recursive target, so if your package mixes\n    hand-crafted `Makefile.in's with Automake-generated\n    `Makefile.in's, you should adjust the former to support (or\n    ignore) this target so that `make html' recurses successfully.  If\n    you had a custom `html' rule in your `Makefile.am', it's better to\n    rename it as `html-local', otherwise your rule will override\n    Automake's new rule (you can check that by running `automake\n    -Woverride') and that will stop the recursion to subdirectories.\n\n    Last but not least, this `html' rule is declared PHONY, even when\n    overridden.  Fortunately, it appears that few packages use a\n    non-PHONY `html' rule.\n\n  - Any file which is m4_included from configure.ac will appear as a\n    configure and Makefile.in dependency, and will be automatically\n    distributed.\n\n  - The rules for rebuilding Makefiles and Makefile.ins will now\n    rebuild all Makefiles and all Makefile.ins at once when one of\n    configure's dependencies has changed.  This is considerably faster\n    than previous implementations, where config.status and automake\n    were run separately in each directory (this still happens when you\n    change a Makefile.am locally, without touching configure.ac or\n    friends).  Doing this also solves a longstanding issue: these\n    rebuild rules failed to work when adding new directories to the\n    tree, forcing you to run automake manually.\n\n  - For similar reasons, the rules to rebuild configure,\n    config.status, and aclocal.m4 are now defined in all directories.\n    Note that if you were using the CONFIG_STATUS_DEPENDENCIES and\n    CONFIGURE_DEPENDENCIES (formerly undocumented) variables, you\n    should better define them in all directories.  This is easily done\n    using an AC_SUBST (make sure you prefix these dependencies with\n    $(top_srcdir) since this variable will appear at different\n    levels of the build tree).\n\n  - aclocal will now use `m4_include' instead of copying local m4\n    files into aclocal.m4.  (Local m4 files are those you ship with\n    your project, other files will be copied as usual.)\n\n    Because m4_included files are automatically distributed, it means\n    for most projects there is no point in EXTRA_DISTing the list of\n    m4 files which are used.  (You can probably get rid of\n    m4/Makefile.am if you had one.)\n\n  - aclocal will avoid touching aclocal.m4 when possible, so that\n    Autom4te's cache isn't needlessly invalidated.  This behavior can\n    be switched off with the new `--force' option.\n\n  - aclocal now uses Autoconf's --trace to detect macros which are\n    actually used and will no longer include unused macros simply\n    because they where mentioned.  This was often the case for macros\n    called conditionally.\n\n  - New options no-dist and no-dist-gzip.\n\n  - compile, depcomp, elisp-comp, install-sh, mdate-sh, mkinstalldirs,\n    py-compile, and ylwrap, now all understand --version and --help.\n\n  - Automake will now recognize AC_CONFIG_LINKS so far as removing created\n    links as part of the distclean target and including source files in\n    distributions.\n\n  - AM_PATH_PYTHON now supports ACTION-IF-FOUND and ACTION-IF-NOT-FOUND\n    argument.  The latter can be used to override the default behavior\n    (which is to abort).\n\n  - Automake will exit with $? = 63 on version mismatch.  (So does\n    Autoconf 2.58)  missing knows this, and in this case it will\n    emulate the tools as if they were absent.  Because older versions\n    of Automake and Autoconf did not use this exit code, this change\n    will only be useful in projects generated with future versions of\n    these tools.\n\n  - When using AC_CONFIG_FILES with multiple input files, Automake\n    generates the first \".in\" input file for which a \".am\" exists.\n    (Former versions would try to use only the first input file.)\n\n  - lisp_DATA is now allowed.  If you are using the empty ELCFILES\n    idiom to disable byte-compilation of lisp_LISP files, it is\n    recommended that you switch to using lisp_DATA.  Note that\n    this is not strictly equivalent: lisp_DATA will install elisp\n    files even if emacs is not installed, while *_LISP do not\n    install anything unless emacs is found.\n\n  - Makefiles will prefer `mkdir -p' over mkinstalldirs if it is\n    available.  This selection is achieved through the Makefile\n    variable $(mkdir_p) that is set by AM_INIT_AUTOMAKE to either\n    `mkdir -m 0755 -p --', `$(mkinstalldirs) -m 0755', or\n    `$(install_sh) -m 0755 -d'.\n\n* Obsolete features\n\n  - Because `mkdir -p' is available on most platforms, and we can use\n    `install-sh -d' when it is not, the use of the mkinstalldirs\n    script is being phased out.  `automake --add-missing' no longer\n    installs it, and if you remove mkinstalldirs from your package,\n    automake will define $(mkinstalldirs) as an alias for $(mkdir_p).\n\n    Gettext 0.12.1 still requires mkinstalldirs.  Fortunately\n    gettextize and autopoint will install it when needed.  Automake\n    will continue to define the $(mkinstalldirs) and to distribute\n    mkinstalldirs when this script is in the source tree.\n\n  - AM_PROG_CC_STDC is now empty.  The content of this macro was\n    merged in AC_PROG_CC.  If your code uses $am_cv_prog_cc_stdc, you\n    should adjust it to use $ac_cv_prog_cc_stdc instead.  (This\n    renaming should be safe, even if you have to support several,\n    versions of Automake, because AC_PROG_CC defines this variable\n    since Autoconf 2.54.)\n\n  - Some users where using the undocumented ACLOCAL_M4_SOURCES\n    variable to override the aclocal.m4 dependencies computed\n    (inaccurately) by older versions of Automake.  Because Automake\n    now tracks configure's m4 dependencies accurately (see m4_include\n    above), the use of ACLOCAL_M4_SOURCES should be considered\n    obsolete and will be flagged as such when running `automake\n    -Wobsolete'.\n\n* Bug fixes\n\n  - Defining programs conditionally using Automake conditionals no\n    longer leads to a combinatorial explosion.  The following\n    construct used to be troublesome when used with dozens of\n    conditions.\n\n      bin_PROGRAMS = a\n      if COND1\n        bin_PROGRAMS += a1\n      endif\n      if COND2\n        bin_PROGRAMS += a2\n      endif\n      if COND3\n        bin_PROGRAMS += a3\n      endif\n      ...\n\n    Likewise for _SOURCES, _LDADD, and _LIBADD variables.\n\n  - Due to implementation constraints, previous versions of Automake\n    proscribed multiple conditional definitions of some variables\n    like bin_PROGRAMS:\n\n      if COND1\n        bin_PROGRAMS = a1\n      endif\n      if COND2\n        bin_PROGRAMS = a2\n      endif\n\n    All _PROGRAMS, _LDADD, and _LIBADD variables were affected.\n    This restriction has been lifted, and these variables now\n    support multiple conditional definitions as do other variables.\n\n  - Cleanup the definitions of $(distdir) and $(top_distdir).\n    $(top_distdir) now points to the root of the distribution\n    directory created during `make dist', as it did in Automake 1.4,\n    not to the root of the build tree as it did in intervening\n    versions.  Furthermore these two variables are now only defined in\n    the top level Makefile, and passed to sub-directories when running\n    `make dist'.\n\n  - The --no-force option now correctly checks the Makefile.in's\n    dependencies before deciding not to update it.\n\n  - Do not assume that make files are called Makefile in cleaning rules.\n\n  - Update .info files in the source tree, not in the build tree.  This\n    is what the GNU Coding Standard recommend.  Only Automake 1.7.x\n    used to update these files in the build tree (previous versions did\n    it in the source tree too), and it caused several problems, varying\n    from mere annoyance to portability issues.\n\n  - COPYING, COPYING.LIB, and COPYING.LESSER are no longer overwritten\n    when --add-missing and --force-missing are used.  For backward\n    compatibility --add-missing will continue to install COPYING (in\n    `gnu' strictness) when none of these three files exist, but this\n    use is deprecated: you should better choose a license yourself and\n    install it once for all in your source tree (and in your code\n    management system).\n\n  - Fix ylwrap so that it does not overwrite header files that haven't\n    changed, as the inline rule already does.\n\n  - User-defined rules override automake-defined rules for the same\n    targets, even when rules do not have commands.  This is not new\n    (and was documented), however some of the automake-generated\n    rules have escaped this principle in former Automake versions.\n    Rules for the following targets are affected by this fix:\n\n       clean, clean-am, dist-all, distclean, distclean-am, dvi, dvi-am,\n       info, info-am, install-data-am, install-exec-am, install-info,\n       install-info-am, install-man, installcheck-am, maintainer-clean,\n       maintainer-clean-am, mostlyclean, mostlyclean-am, pdf, pdf-am,\n       ps, ps-am, uninstall-am, uninstall-info, uninstall-man\n\n    Practically it means that an attempt to supplement the dependencies\n    of some target, as in\n\n       clean: my-clean-rule\n\n    will now *silently override* the automake definition of the\n    rule for this target.  Running `automake -Woverride' will diagnose\n    all such overriding definitions.\n\n    It should be noted that almost all of these targets support a *-local\n    variant that is meant to supplement the automake-defined rule\n    (See node `Extending' in the manual).  The above rule should\n    be rewritten as\n\n      clean-local: my-clean-rule\n\n    These *-local targets have been documented since at least\n    Automake 1.2, so you should not fear the change if you have\n    to support multiple automake versions.\n\n* Miscellaneous\n\n  - The Automake manual is now distributed under the terms of the GNU FDL.\n\n  - Targets dist-gzip, dist-bzip2, dist-tarZ, dist-zip are always defined.\n\n  - core dumps are no longer removed by the cleaning rules.  There are\n    at least three reasons for this:\n      1. These files should not be created by any build step,\n\t so their removal do not fit any of the cleaning rules.\n\t Actually, they may be precious to the developer.\n      2. If such file is created during a build, then it's clearly a\n         bug Automake should not hide.  Not removing the file will\n         cause `make distcheck' to complain about its presence.\n      3. Operating systems have different naming conventions for\n         core dump files.  A core file on one system might be a\n\t completely legitimate data file on another system.\n\n  - RUNTESTFLAGS, CTAGSFLAGS, ETAGSFLAGS, JAVACFLAGS are no longer\n    defined by Automake.  This means that any definition in the\n    environment will be used, unless overridden in the Makefile.am or\n    on the command line.  The old behavior, where these variables were\n    defined empty in each Makefile, can be obtained by AC_SUBSTing or\n    AC_ARG_VARing each variable from configure.ac.\n\n  - CONFIGURE_DEPENDENCIES and CONFIG_STATUS_DEPENDENCIES are now\n    documented.  (The is not a new feature, these variables have\n    been there since at least Automake 1.4.)\n\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBugs fixed in 1.7.9:\n* Fix install-strip to work with nobase_ binaries.\n* Fix renaming of #line directives in ylwrap.\n* Rebuild with Autoconf 2.59.  (1.7.8 was not installable with pdksh.)\n\nBugs fixed in 1.7.8:\n* Remove spurious blank lines in cleaning rules introduced in 1.7.7.\n* Fix detection of Debian's install-info, broken since version 1.5.\n  (Debian bug #213524).\n* Honor -module if it appears in AM_LDFLAGS (i.e., relax name checking)\n  This was only done for libfoo_LDFLAGS and LDFLAGS in previous versions.\n\nBugs fixed in 1.7.7:\n* The implementation of automake's --no-force option is unreliable,\n  so this option is ignored in this version.  A real fix will appear in\n  Automake 1.8.  (Debian Bug #206299)\n* AM_PATH_PYTHON: really check the whole list of interpreters if no\n  argument is given.  (PR/399)\n* Do not warn about leading `_' in variable names, even with -Wportability.\n* Support user redefinitions of TEXINFO_TEX.\n* depcomp: support AIX Compiler version 6.\n* Fix missing rebuilds during `make dist' with BSD make.\n  (Could produce tarballs containing out-of-date files.)\n* Resurrect multilib support.\n* Noteworthy manual updates:\n  - Extending aclocal: how to write m4 macros that won't trigger warnings\n    with Automake 1.8.\n  - A Shared Library: Rewrite and split into subsections.\n\nBugs fixed in 1.7.6:\n* Fix depcomp's icc mode for ICC 7.1.\n* Diagnose calls to AC_CONFIG_FILES and friends with not enough arguments.\n* Fix maintainer-clean's removal of autom4te.cache in VPATH builds.\n* Fix AM_PATH_LISPDIR to work with POSIXLY_CORRECT=1.\n* Fix the location reported in some diagnostics related to AUTOMAKE_OPTIONS.\n* Remove Latin-1 characters from elisp-comp.\n* Update the manual's @dircategory to match the Free Software Directory.\n\nBugs fixed in 1.7.5:\n* Update install-sh's license to remove an advertising clause.\n  (Debian bug #191717)\n* Fix a bug introduced in 1.7.4, related to BUILT_SOURCE handling,\n  that caused invalid Makefile.ins to be generated.\n* Make sure AM_MAKE_INCLUDE doesn't fail when a `doit' file exists.\n* New FAQ entry: renamed objects.\n\nBugs fixed in 1.7.4:\n* Tweak the TAGS rule to support Exuberant Ctags (in addition to\n  the Emacs implementation)\n* Fix output of aclocal.m4 dependencies in subdirectories.\n* Use `mv -f' instead of `mv' in fastdep rules.\n* Upgrade mdate-sh to work on OS/2.\n* Don't byte-compile elisp files when ELCFILES is set empty.\n  (this documented feature was broken by 1.7.3)\n* Diagnose trailing backslashes on last line of Makefile.am.\n* Diagnose whitespace following trailing backslashes.\n* Multiple tests are now correctly supported in DEJATOOL. (PR/388)\n* Fix rebuilt rules for AC_CONFIG_FILES([Makefile:Makefile.in:Makefile.bot])\n  Makefiles. (PR/389)\n* `make install' will build `BUILT_SOURCES' first.\n* Minor documentation fixes.\n\nBugs fixed in 1.7.3:\n* Fix stamp files numbering (when using multiple AC_CONFIG_HEADERS).\n* Query distutils for `pythondir' and `pythonexecdir', instead of\n  using an hardcoded path.  This should allow builds on 64-bit\n  distributions that usually use lib64/ instead of lib/.\n* AM_PATH_PYTHON will also search for python2.3.\n* elisp files are now built all at once instead of one by one. Besides\n  incurring a speed-up, this is required to support interdependent elisp files.\n* Support for DJGPP:\n  - `make distcheck' will now work in `_inst/' and `_build' instead\n    of `=inst/' and `=build/'\n  - use `_dirstamp' when the file-system doesn't support `.dirstamp'\n  - install/uninstall `*.i[0-9][0-9]'-style info files\n  - more changes that affect only the Automake package (not its output)\n* Fix some incompatibilities with upcoming perl-5.10.\n* Properly quote AC_PACKAGE_TARNAME and AC_PACKAGE_VERSION when defining\n  PACKAGE and VERSION.\n* depcomp fixes:\n  - dashmstdout and dashXmstdout modes: don't use `-o /dev/null', this\n    is troublesome with gcc and Solaris compilers. (PR/385)\n  - makedepend mode: work with Libtool. (PR/385 too)\n  - support for ICC.\n* better support for unusual gettext setups, such as multiple po/ directories\n  (PR/381):\n  - Flag missing po/ and intl/ directories as warnings, not errors.\n  - Disable these warnings if po/ does not exist.\n* Noteworthy manual updates:\n  - New FAQ chapter.\n  - Document how AC_CONFIG_AUX_DIR interacts with missing files.\n    (Debian Bug #39542)\n  - Document `AM_YFLAGS = -d'.  (PR/382)\n\nBugs fixed in 1.7.2:\n* Fix installation and uninstallation of Info files built in subdirectories.\n* Do not run `./configure --with-included-gettext' during `make distcheck'\n  if AM_GNU_GETTEXT([external]) is used.\n* Correctly uninstall renamed man pages.\n* Do not strip escaped newline in variables defined in one condition\n  and augmented in another condition.\n* Fix ansi2knr rules for LIBOBJS sources.\n* Clean all known Texinfo index files, not only those which appear to\n  be used, because we cannot know which indexes are used in included files.\n  (PR/375, Debian Bug #168671)\n* Honor only the first @setfilename seen in a Texinfo file.\n* Treat \"required file X not found\" diagnostics as errors (exit status 1).\n* Don't complain that a required file is not found when it is a Makefile\n  target. (PR/357)\n* Don't use single suffix inference rules when building `.info'-less\n  Info files, for the sake of Solaris make.\n* The `check' target now depends on `$(BUILT_SOURCES)'. (PR/359)\n* Recognize multiple inference rules such as `.a.b .c.d:'. (PR/371)\n* Warn about multiple inference rules when -Wportability is used. (PR/372)\n* Fix building of deansified files from subdirectories. (PR/370)\n* Add missing `fi' in the .c->.obj rules.\n* Improve install-sh to work even when names contain spaces or certain\n  (but not all) shell metachars.\n* Fix the following spurious failures in the test suite:\n  depcomp2.test, gnits2.test, gnits3.test, python3.test, texinfo13.test\n* Noteworthy manual updates:\n  - Augment the section about BUILT_SOURCES.\n  - Mention that AM_PROG_CC_STDC is a relic that is better avoided today.\n\nBugs fixed in 1.7.1:\n* Honor `ansi2knr' for files built in subdirectories, or using per-targets\n  flags.\n* Aclocal should now recognize macro names containing parentheses, e.g.\n  AC_DEFUN([AC_LANG_PREPROC(Fortran 90)], [...]).\n* Erase *.sum and *.log files created by DejaGnu, during `make distclean'.\n  (Debian Bug#153697)\n* Install Python files even if they were built.  (PR/369)\n* Have stamp-vti dependent upon configure instead of configure.ac, as the\n  version might not be defined in the latter. (PR/358)\n* Reorder arguments passed to a couple of commands, so things works\n  when POSIXLY_CORRECT=1.\n* Fix a regex that can cause Perl to segfault on large input.\n  (Debian Bug#162583)\n* Fix distribution of packages that have some sources defined conditionally,\n  as in the `Conditional compilation using Automake conditionals' example\n  of the manual.\n* Fix spurious test suite failures on IRIX.\n* Don't report a required variable as undefined if it has been\n  defined conditionally for the \"right\" conditions.\n* Fix cleaning of the /tmp subdirectory used by `make distcheck', in case\n  `make distcheck' fails.\n* Fix distribution of included Makefile fragment, so we don't create\n  spurious directories in the distribution. (PR/366)\n* Don't complain that a target lacks `.$(EXEEXT)' when it has it.\n\nNew in 1.7:\n* Autoconf 2.54 is required.\n* `aclocal' and `automake' will no longer warn about obsolete\n  configure macros.  This is done by `autoconf -Wobsolete'.\n* AM_CONFIG_HEADER, AM_SYS_POSIX_TERMIOS and\n  AM_HEADER_TIOCGWINSZ_NEEDS_SYS_IOCTL are obsolete (although still\n  supported).  You should use AC_CONFIG_HEADERS, AC_SYS_POSIX_TERMIOS,\n  and AC_HEADER_TIOCGWINSZ instead.  `autoupdate' can upgrade\n  `configure.ac' for you.\n* Support for per-program and per-library `_CPPFLAGS'.\n* New `ctags' target (builds CTAGS files).\n* Support for -Wmumble and -Wno-mumble, where mumble is a warning category\n  (see `automake --help' or the manual for a list of them).\n* Honor the WARNINGS environment variable.\n* Omit the call to depcomp when using gcc3: call the compiler directly.\n* A new option, std-options, tests that programs support --help and --version\n  when `make installcheck' is run.  This is enabled by --gnits.\n* Texinfo rules now support the `ps' and `pdf' targets.\n* Info files are now created in the build directory, not the source directory.\n* info_TEXINFOS supports files in subdirectories (this requires Texinfo 4.1\n  or greater).\n* `make distcheck' will enforce DESTDIR support by attempting\n  a DESTDIR install.\n* `+=' can be used in conditionals, even if the augmented variable\n  was defined for another condition.\n* Makefile fragments (inserted with `include') are always distributed.\n* Use Autoconf's --trace interface to inspect configure.ac and get\n  a more accurate view of it.\n* Add support for extending aclocal's default macro search path\n  using a `dirlist' file within the aclocal directory.\n* automake --output-dir is deprecated.\n* The part of the distcheck target that checks whether uninstall actually\n  removes all installed files has been moved to a separate target,\n  distuninstallcheck, so it can be overridden easily.\n* Many bug fixes.\n\nNew in 1.6.3:\n* Support for AM_INIT_GETTEXT([external])\n* Bug fixes, including:\n  - Fix Automake's own `make install' so it works even if `ln' doesn't.\n  - nobase_ programs and scripts honor --program-transform correctly.\n  - Erase configure.lineno during `make distclean'.\n  - Erase YACC and LEX outputs during `make maintainer-clean'.\n\nNew in 1.6.2:\n* Many bug fixes, including:\n  - Requiring the current version works.\n  - Fix \"$@\" portability issues (for Zsh).\n  - Fix output of dummy dependency files in presence of post-processed\n    Makefile.in's.\n  - Don't compute dependencies in background to avoid races with libtool.\n  - Fix handling of _OBJECTS variables for targets sharing source variables.\n  - Check dependency mode for Java when AM_PROG_GCJ is used.\n\nNew in 1.6.1:\n* automake --output-dir is deprecated\n* Many bug fixes, including:\n  - Don't choke on AM_LDFLAGS definitions.\n  - Clean libtool objects from subdirectories.\n  - Allow configure variables with reserved suffix and unknown prefix\n    (e.g. AC_SUBST(mumble_LDFLAGS) when 'mumble' is not a target).\n  - Fix the definition of AUTOMAKE and ACLOCAL in configure.\n\nNew in 1.6:\n* Autoconf 2.52 is required.\n* automake no longer run libtoolize.\n  This is the job of autoreconf (from GNU Autoconf).\n* `dist' generates all the archive flavors, as did `dist-all'.\n* `dist-gzip' generates the Gzip tar file only.\n* Combining Automake Makefile conditionals no longer lead to a combinatorial\n  explosion.  Makefile.in's keep a reasonable size.\n* AM_FUNC_ERROR_AT_LINE, AM_FUNC_STRTOD, AM_FUNC_OBSTACK, AM_PTRDIFF_T\n  are no longer shipped, since Autoconf 2.52 provides them (both as AM_\n  and AC_).\n* `#line' of Lex and Yacc files are properly set.\n* EXTRA_DIST can contain generated directories.\n* Support for dot-less extensions in suffix rules.\n* The part of the distcheck target that checks whether distclean actually\n  cleans all built files has been moved to a separate target, distcleancheck,\n  so it can be overridden easily.\n* `make distcheck' will pass additional options defined in\n  $(DISTCHECK_CONFIGURE_FLAGS) to configure.\n* Fixed CDPATH portability problems, in particular for MacOS X.\n* Fixed handling of nobase_ targets.\n* Fixed support of implicit rules leading to .lo objects.\n* Fixed late inclusion of --add-missing files (e.g. depcomp) in DIST_COMMON\n* Added uninstall-hook target\n* `AC_INIT AM_INIT_AUTOMAKE(tarname,version)' is an obsolete construct.\n  You can now use `AC_INIT(pkgname,version) AM_INIT_AUTOMAKE' instead.\n  (Note that \"pkgname\" is not \"tarname\", see the manual for details.)\n  It is also possible to pass a list of global Automake options as\n  first argument to this new form of AM_INIT_AUTOMAKE.\n* Compiler-based assembler is now called `CCAS'; people expected `AS'\n  to be a real assembler.\n* AM_INIT_AUTOMAKE will set STRIP itself when it needs it.  Adding\n  AC_CHECK_TOOL([STRIP], [strip]) manually is no longer required.\n* aclocal and automake are also installed with the version number\n  appended, and some of the install directory names have changed.\n  This lets you have multiple versions installed simultaneously.\n* Support for parsers and lexers in subdirectories.\n\nNew in 1.5:\n* Support for `configure.ac'.\n* Support for `else COND', `endif COND' and negated conditions `!COND'.\n* `make dist-all' is much faster.\n* Allows '@' AC_SUBSTs in macro names.\n* Faster AM_INIT_AUTOMAKE (requires update of `missing' script)\n* User-side dependency tracking.  Developers no longer need GNU make\n* Python support\n* Uses DIST_SUBDIRS in some situations when SUBDIRS is conditional\n* Most files are correctly handled if they appear in subdirs\n  For instance, a _DATA file can appear in a subdir\n* GNU tar is no longer required for `make dist'\n* Added support for `dist_' and `nodist_' prefixes\n* Added support for `nobase_' prefix\n* Compiled Java support\n* Support for per-executable and per-library compilation flags\n* Many bug fixes\n\nNew in 1.4:\n* Added support for the Fortran 77 programming language.\n* Re-indexed the Automake Texinfo manual.\n* Added `AM_FOOFLAGS' variable for each compiler invocation;\n  e.g. AM_CFLAGS can be used in Makefile.am to set C compiler flags\n* Support for latest autoconf, including support for objext\n* Can now put `.' in SUBDIRS to control build order\n* `include' command and `+=' support for macro assignment\n* Dependency tracking no long susceptible to deleted header file problem\n* Maintainer mode now a conditional.  @MAINT@ is now an anachronism.\n* Bug fixes\n\nNew in 1.3:\n* Bug fixes\n* Better Cygwin32 support\n* Support for suffix rules with _SOURCES variables\n* New options `readme-alpha' and `check-news'; Gnits mode sets these\n* @LEXLIB@ no longer required when lex source seen\n  Lex support in `missing', and new lex macro.  Update your missing script.\n* Built-in support for assembly\n* aclocal gives error if `AM_' macro not found\n* Passed YFLAGS, not YACCFLAGS, to yacc\n* AM_PROG_CC_STDC does not have to come before AC_PROG_CPP\n* Dependencies computed as a side effect of compilation\n* Preliminary support for Java\n* DESTDIR support at \"make install\" time\n* Improved ansi2knr support; you must use the latest ansi2knr.c (included)\n\nNew in 1.2:\n* Bug fixes\n* Better DejaGnu support\n* Added no-installinfo option\n* Added Emacs Lisp support\n* Added --no-force option\n* Included `aclocal' program\n* Automake will now generate rules to regenerate aclocal.m4, if appropriate\n* Now uses `AM_' macro names everywhere\n* ansi2knr option can have directory prefix (eg `../lib/ansi2knr')\n  ansi2knr now works correctly on K&R sources\n* Better C++, yacc, lex support\n* Will compute _DEPENDENCIES variables automatically if not supplied\n* Will interpolate $(...) and ${...} when examining contents of a variable\n* .deps files now in build directory, not source directory; dependency\n  handling generally rewritten\n* DATA, MANS and BUILT_SOURCES no longer included in distribution\n* can now put config.h into a subdir\n* Added dist-all target\n* Support for install-info program (see texinfo 3.9)\n* Support for \"yacc -d\"\n* configure substitutions are automatically discovered and included\n  in generated Makefile.in\n* Special --cygnus mode\n* OMIT_DEPENDENCIES can now hold list of dependencies to be omitted\n  when making distribution.  Some dependencies are auto-ignored.\n* Changed how libraries are specified in _LIBRARIES variable\n* Full libtool support, from Gord Matzigkeit\n* No longer have to explicitly touch stamp-h when using AC_CONFIG_HEADER;\n  AM_CONFIG_HEADER handles it automatically\n* Texinfo output files no longer need .info extension\n* Added `missing' support\n* Cygwin32 support\n* Conditionals in Makefile.am, from Ian Taylor\n\nNew in 1.0:\n* Bug fixes\n* distcheck target runs install and installcheck targets\n* Added preliminary support for DejaGnu.\n\nNew in 0.33:\n* More bug fixes\n* More checking\n* More libtool fixes from Gord Matzigkeit; libtool support is still\n  preliminary however\n* Added support for jm_MAINTAINER_MODE\n* dist-zip support\n* New \"distcheck\" target\n\nNew in 0.32:\n* Many bug fixes\n* mkinstalldirs and mdate-sh now appear in directory specified by\n  AC_CONFIG_AUX_DIR.\n* Removed DIST_SUBDIRS, DIST_OTHER\n* AC_ARG_PROGRAM only required when an actual program exists\n* dist-hook target now run before distribution packaged up; idea from\n  Dieter Baron.  Other hooks exist, too.\n* Preliminary (unfinished) support for libtool\n* Added short option names.\n* Better \"dist\" support when gluing together multiple packages\n\nNew in 0.31:\n* Bug fixes\n* Documentation updates (many from François Pinard)\n* strictness `normal' now renamed to `foreign'\n* Renamed --install-missing to --add-missing\n* Now handles AC_CONFIG_AUX_DIR\n* Now handles TESTS macro\n* DIST_OTHER renamed to EXTRA_DIST\n* DIST_SUBDIRS is deprecated\n* @ALLOCA@ and @LIBOBJS@ now work in _LDADD variables\n* Better error messages in many cases\n* Program names are canonicalized\n* Added \"check\" prefix; from Gord Matzigkeit\n\nNew in 0.30:\n* Bug fixes\n* configure.in scanner knows about AC_PATH_XTRA, AC_OUTPUT \":\" syntax\n* Beginnings of a test suite\n* Automatically adds -I options for $(srcdir), \".\", and path to config.h\n* Doesn't print anything when running\n* Beginnings of MAINT_CHARSET support\n* Can specify version in AUTOMAKE_OPTIONS\n* Most errors recognizable by Emacs' M-x next-error\n* Added --verbose option\n* All \"primary\" variables now obsolete; use EXTRA_PRIMARY to supply\n  configure-generated names\n* Required macros now distributed in aclocal.m4\n* New documentation\n* --strictness=gnu is default\n\nNew in 0.29:\n* Many bug fixes\n* More sophisticated configure.in scanning; now understands ALLOCA and\n  LIBOBJS directly, handles AC_CONFIG_HEADER more precisely, etc.\n* TEXINFOS and MANS now obsolete; use info_TEXINFOS and man_MANS instead.\n* CONFIG_HEADER variable now obsolete\n* Can handle multiple Texinfo sources\n* Allow hierarchies deeper than 2.  From Gord Matzigkeit.\n* HEADERS variable no longer needed; now can put .h files directly into\n  foo_SOURCES variable.\n* Automake automatically rebuilds files listed in AC_OUTPUT.  The\n  corresponding \".in\" files are included in the distribution.\n\nNew in 0.28:\n* Added --gnu and --gnits options\n* More standards checking\n* Bug fixes\n* Cleaned up 'dist' targets\n* Added AUTOMAKE_OPTIONS variable and several options\n* Now scans configure.in to get some information (preliminary)\n\nNew in 0.27:\n* Works with Perl 4 again\n\nNew in 0.26:\n* Added --install-missing option.\n* Pretty-prints generated macros and rules\n* Comments in Makefile.am are placed more intelligently in Makefile.in\n* Generates .PHONY target\n* Rule or macro in Makefile.am now overrides contents of Automake file\n* Substantial cleanups from François Pinard\n\nNew in 0.25:\n* Bug fixes.\n* Works with Perl 4 again.\n\nNew in 0.24:\n* New uniform naming scheme.\n* --strictness option\n* Works with Perl 5\n* '.c' files corresponding to '.y' or '.l' files are automatically\n  distributed.\n* Many bug fixes and cleanups\n\nNew in 0.23:\n* Allow objects to be conditionally included in libraries via lib_LIBADD.\n\nNew in 0.22:\n* Bug fixes in 'clean' code.\n* Now generates 'installdirs' target.\n* man page installation reworked.\n* 'make dist' no longer re-creates all Makefile.in's.\n\nNew in 0.21:\n* Reimplemented in Perl\n* Added --amdir option (for debugging)\n* Texinfo support cleaned up.\n* Automatic de-ANSI-fication cleaned up.\n* Cleaned up 'clean' targets.\n\nNew in 0.20:\n* Automatic dependency tracking\n* More documentation\n* New variables DATA and PACKAGEDATA\n* SCRIPTS installed using $(INSTALL_SCRIPT)\n* No longer uses double-colon rules\n* Bug fixes\n* Changes in advance of internationalization\n\n-----\n\nCopyright (C) 1995-2021 Free Software Foundation, Inc.\n\nThis program is free software; you can redistribute it and/or modify\nit under the terms of the GNU General Public License as published by\nthe Free Software Foundation; either version 2, or (at your option)\nany later version.\n\nThis program is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\nGNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License\nalong with this program.  If not, see <https://www.gnu.org/licenses/>.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/automake-1.16.5/NEWS-2.0",
    "content": "This file (NEWS-2.0) lists several incompatibilities planned for a\nfuture Automake 2.0 release.\n\nHowever, the (few) current Automake maintainers have insufficient interest\nand energy to pursue the 2.0 release.  We have not even reviewed all\nexisting bugs.  New maintainers are needed!  For more information about\nhelping with Automake development:\nhttps://lists.gnu.org/archive/html/automake/2021-03/msg00018.html\n\nTherefore, there is no ETA for Automake 2.0, but it is not likely to be\nany time soon.  So moving these future issues to a separate file seemed\nwarranted.  For more info, see the ./PLANS/ directory.\n\n\n* WARNING: Future backward-incompatibilities!\n\n  - Makefile recipes generated by Automake 2.0 will expect to use an\n    'rm' program that doesn't complain when called without any non-option\n    argument if the '-f' option is given (so that commands like \"rm -f\"\n    and \"rm -rf\" will act as a no-op, instead of raising usage errors).\n    This behavior of 'rm' is very widespread in the wild, and it will be\n    required in the next POSIX version:\n\n      <http://austingroupbugs.net/view.php?id=542>\n\n    Accordingly, AM_INIT_AUTOMAKE now expands some shell code that checks\n    that the default 'rm' program in PATH satisfies this requirement,\n    aborting the configure process if this is not the case.  For the\n    moment, it's still possible to force the configuration process to\n    succeed even with a broken 'rm', but that will no longer be the case\n    for Automake 2.0.\n\n  - Automake 2.0 will require Autoconf 2.71 or later.  Exact\n    dependencies are unknowable at ths time.\n\n  - Automake 2.0 will drop support for the long-deprecated 'configure.in'\n    name for the Autoconf input file.  You are advised to start using the\n    recommended name 'configure.ac' instead, ASAP.\n\n  - The ACLOCAL_AMFLAGS special make variable will be fully deprecated in\n    Automake 2.0: it will raise warnings in the \"obsolete\" category (but\n    still no hard error of course, for compatibilities with the many, many\n    packages that still relies on that variable).  You are advised to\n    start relying on the new Automake support for AC_CONFIG_MACRO_DIRS\n    instead (which was introduced in Automake 1.13).\n\n  - Automake 2.0 will remove support for automatic dependency tracking\n    with the SGI C/C++ compilers on IRIX.  The SGI depmode has been\n    reported broken \"in the wild\" already, and we don't think investing\n    time in debugging and fixing is worthwhile, especially considering\n    that SGI has last updated those compilers in 2006, and retired\n    support for them in December 2013:\n    <http://www.sgi.com/services/support/irix_mips_support.html>\n\n  - Automake 2.0 will remove support for MS-DOS and Windows 95/98/ME\n    (support for them was offered by relying on the DJGPP project).\n    Note however that both Cygwin and MSYS/MinGW on modern Windows\n    versions will continue to be fully supported.\n\n  - Automake-provided scripts and makefile recipes might (finally!)\n    start assuming a POSIX shell in Automake 2.0.  There still is no\n    certainty about this though: we'd first like to wait and see\n    whether future Autoconf versions will be enhanced to guarantee\n    that such a shell is always found and provided by the checks in\n    ./configure.\n\n    In 2020, config.guess was changed by its then-maintainer to require\n    $(...); the ensuing bug reports and maintenance hassle\n    (unfortunately the changes have not been reverted) are a convincing\n    argument that we should not require a POSIX shell until Solaris 10,\n    at least, is completely gone from the world.\n\n  - Starting from Automake 2.0, third-party m4 files located in the\n    system-wide aclocal directory, as well as in any directory listed\n    in the ACLOCAL_PATH environment variable, will take precedence\n    over \"built-in\" Automake macros.  For example (assuming Automake\n    is installed in the /usr/local hierarchy), a definition of the\n    AM_PROG_VALAC macro found in '/usr/local/share/aclocal/my-vala.m4'\n    should take precedence over the same-named automake-provided macro\n    (defined in '/usr/local/share/aclocal-2.0/vala.m4').\n\n-----\n\nCopyright (C) 1995-2021 Free Software Foundation, Inc.\n\nThis program is free software; you can redistribute it and/or modify\nit under the terms of the GNU General Public License as published by\nthe Free Software Foundation; either version 2, or (at your option)\nany later version.\n\nThis program is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\nGNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License\nalong with this program.  If not, see <https://www.gnu.org/licenses/>.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/automake-1.16.5/README",
    "content": "This is Automake, a Makefile generator.  It aims to be portable and\nto conform to the GNU Coding Standards for Makefile variables and\ntargets.\n\nSee the INSTALL file for detailed information about how to configure\nand install Automake.\n\nAutomake is a Perl script.  The input files are called Makefile.am.\nThe output files are called Makefile.in; they are intended for use\nwith Autoconf.  Automake requires certain things to be done in your\nconfigure.ac.\n\nAutomake comes with extensive documentation; please refer to it for\nmore details about its purpose, features, and usage patterns.\n\nThis package also includes the \"aclocal\" program, whose purpose is\nto generate an 'aclocal.m4' based on the contents of 'configure.ac'.\nIt is useful as an extensible, maintainable mechanism for augmenting\nautoconf.  It is intended that other package authors will write m4\nmacros which can be automatically used by aclocal.  The documentation\nfor aclocal is currently found in the Automake manual.\n\nAutomake has a test suite.  Use \"make check\" to run it.  For more\ninformation, see the file t/README.\n\nAutomake's home page:\n\n\thttps://www.gnu.org/software/automake/\n\nAutomake has three mailing lists:\n\n  * automake@gnu.org\n    For general discussions of Automake and its interactions with other\n    configuration/portability tools like Autoconf or Libtool.\n\n  * bug-automake@gnu.org\n    Where to send bug reports and feature requests.\n\n  * automake-patches@gnu.org\n    Where to send patches, and discuss the automake development process\n    and the design of new features.\n\nTo see the archives of these lists, or to (un)subscribe to them,\nrefer to <https://www.gnu.org/software/automake/#mailinglists>.\n\nNew releases are announced to autotools-announce@gnu.org.  If you want to\nbe informed, subscribe to that list by following the instructions at\n<https://lists.gnu.org/mailman/listinfo/autotools-announce>.\n\nFor any copyright year range specified as YYYY-ZZZZ in this package,\nthe range specifies every single year in that closed interval.\n\n-----\n\nCopyright (C) 1994-2021 Free Software Foundation, Inc.\n\nThis program is free software; you can redistribute it and/or modify\nit under the terms of the GNU General Public License as published by\nthe Free Software Foundation; either version 2, or (at your option)\nany later version.\n\nThis program is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\nGNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License\nalong with this program.  If not, see <https://www.gnu.org/licenses/>.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/automake-1.16.5/THANKS",
    "content": "Automake was originally written by David J. MacKenzie <djm@uunet.uu.net>.\nIt would not be what it is today without the invaluable help of these\npeople:\n\nAdam J. Richter                 adam@yggdrasil.com\nAdam Mercer                     ramercer@gmail.com\nAdam Sampson                    ats@offog.org\nAdrian Bunk                     bunk@fs.tum.de\nAharon Robbins                  arnold@skeeve.com\nAkim Demaille                   akim@gnu.org\nAlan Modra                      amodra@bigpond.net.au\nAlex Hornby                     alex@anvil.co.uk\nAlex Unleashed                  unledev@gmail.com\nAlexander Mai                   st002279@hrzpub.tu-darmstadt.de\nAlexander Martens               alexander.martens@gtd.es\nAlexander V. Lukyanov           lav@yars.free.net\nAlexander Turbov                zaufi@sendmail.ru\nAlexandre Duret-Lutz            duret_g@epita.fr\nAlexey Mahotkin                 alexm@hsys.msk.ru\nAlfred M. Szmidt                ams@gnu.org\nAllison Karlitskaya             allison.karlitskaya@redhat.com\nAndrea Urbani                   matfanjol@mail.com\nAndreas Bergmeier               lcid-fire@gmx.net\nAndreas Buening                 andreas.buening@nexgo.de\nAndreas Köhler                  andi5.py@gmx.net\nAndreas Schwab                  schwab@suse.de\nAndrew Cagney                   cagney@tpgi.com.au\nAndrew Eikum                    aeikum@codeweavers.com\nAndrew Suffield                 asuffield@debian.org\nAndris Pavenis                  pavenis@lanet.lv\nAndy Wingo                      wingo@pobox.com\nAngus Leeming                   a.leeming@ic.ac.uk\nAnthony Green                   green@cygnus.com\nAntonio Diaz Diaz               ant_diaz@teleline.es\nArkadiusz Miskiewicz            misiek@pld.ORG.PL\nArt Haas                        ahaas@neosoft.com\nArto C. Nirkko                  anirkko@insel.ch\nAssar Westerlund                assar@sics.se\nAxel Belinfante                 Axel.Belinfante@cs.utwente.nl\nBas Wijnen                      shevek@fmf.nl\nBen Pfaff                       blp@cs.standford.edu\nBenoit Sigoure                  tsuna@lrde.epita.fr\nBernard Giroud                  bernard.giroud@creditlyonnais.ch\nBernard Urban                   Bernard.Urban@meteo.fr\nBernd Jendrissek                berndfoobar@users.sourceforge.net\nBert Wesarg                     bert.wesarg@googlemail.com\nBill Currie                     bcurrie@tssc.co.nz\nBill Davidson                   bill@kayhay.com\nBill Fenner                     fenner@parc.xerox.com\nBob Friesenhahn                 bfriesen@simple.dallas.tx.us\nBob Proulx                      rwp@hprwp.fc.hp.com\nBob Rossi                       bob@brasko.net\nBobby Jack                      bobbykjack@yahoo.co.uk\nBoris Kolpackov                 boris@codesynthesis.com\nBraden N. McDaniel              braden@endoframe.com\nBrandon Black                   blblack@gmail.com\nBrendan O'Dea                   bod@debian.org\nBrian Cameron                   Brian.Cameron@Sun.COM\nBrian Ford                      ford@vss.fsi.com\nBrian Gough                     bjg@network-theory.co.uk\nBrian Jones                     cbj@nortel.net\nBruce Korb                      bkorb@gnu.org\nBruno Haible                    haible@ilog.fr\nCarnë Draug                     carandraug+dev@gmail.com\nCarsten Lohrke                  carlo@gentoo.org\nCharles Wilson                  cwilson@ece.gatech.edu\nChris Hoogendyk                 hoogendyk@bio.umass.edu\nChris Pickett                   chris.pickett@mail.mcgill.ca\nChris Provenzano                proven@io.proven.org\nChristian Cornelssen            ccorn@cs.tu-berlin.de\nChristina Gratorp               christina.gratorp@gmail.com\nClaudio Fontana                 sick_soul@yahoo.it\nClifford Wolf                   clifford@clifford.at\nColin Watson                    cjwatson@ubuntu.com\nColomban Wendling               lists.ban@herbesfolles.org\nDagobert Michelsen              dam@opencsw.org\nDaiki Ueno                      ueno@unixuser.org\nDalibor Topic                   robilad@kaffe.org\ndanbp                           danpb@nospam.postmaster.co.uk\nDaniel Jacobowitz               drow@false.org\nDaniel Kahn Gillmor             dkg@fifthhorseman.net\nDaniel Richard G.               skunk@iskunk.org\nDebarshi Ray                    rishi@gnu.org\nDave Brolley                    brolley@redhat.com\nDave Goodell                    goodell@mcs.anl.gov\nDave Hart                       davehart@gmail.com\nDave Korn                       dave.korn.cygwin@googlemail.com\nDave Morrison                   dave@bnl.gov\nDavid A. Swierczek              swiercze@mr.med.ge.com\nDavid A. Wheeler                dwheeler@dwheeler.com\nDavid Byron                     dbyron@dbyron.com\nDavid Fang                      fang@csl.cornell.edu\nDavyd Madeley                   davyd@fugro-fsi.com.au\nDavid Pashley                   david@davidpashley.com\nDavid Wohlferd                  dw@limegreensocks.com\nDavid Zaroski                   cz253@cleveland.Freenet.Edu\nDean Povey                      dpovey@wedgetail.com\nDennis J. Linse                 Dennis.J.Linse@SAIC.com\nDennis Schridde                 devurandom@gmx.net\nDerek R. Price                  derek.price@openavenue.com\nDiab Jerius                     djerius@cfa.harvard.edu\nDidier Cassirame                faded@free.fr\nDiego Elio Pettenò              flameeyes@flameeyes.eu\nDieter Baron                    dillo@stieltjes.smc.univie.ac.at\nDieter Jurzitza                 DJurzitza@harmanbecker.com\nДилян Палаузов                  dilyan.palauzov@aegee.org\nDirk Mueller                    josef.moellers@suse.com\nDimitri Papadopoulos            dimitri.papadopoulos@gmail.com\nDmitry Mikhin                   dmitrym@acres.com.au\nDmitry V. Levin                 ldv@altlinux.org\nDoug Evans                      devans@cygnus.com\nDuncan Gibson                   duncan@thermal.esa.int\nDilyan Palauzov                 dilyan.palauzov@aegee.org\nEd Hartnett                     ed@unidata.ucar.edu\nEleftherios Gkioulekas          lf@amath.washington.edu\nElena A. Vengerova              helen@oktetlabs.ru\nElmar Hoffmann                  elho@elho.net\nElrond                          Elrond@Wunder-Nett.org\nEnrico Scholz                   enrico.scholz@informatik.tu-chemnitz.de\nErez Zadok                      ezk@cs.columbia.edu\nEric Bavier                     bavier@cray.com\nEric Blake                      eblake@redhat.com\nEric Dorland                    eric@debian.org\nEric Magnien                    emagnien@club-internet.fr\nEric Siegerman                  erics_97@pobox.com\nEric Sunshine                   sunshine@sunshineco.com\nErick Branderhorst              branderh@iaehv.nl\nErik Lindahl                    E.Lindahl@chem.rug.nl\nEsben Haabendal Soerensen       bart@kom.aau.dk\nEzra Peisach                    epeisach@MED-XTAL.BU.EDU\nFabian Alenius                  fabian.alenius@gmail.com\nFederico Simoncelli             fsimonce@redhat.com\nFelix Salfelder                 felix@salfelder.org\nFelix Yan                       felixonmars@archlinux.org\nFlavien Astraud                 flav42@yahoo.fr\nFlorian Briegel                 briegel@zone42.de\nFrancesco Salvestrini           salvestrini@gmail.com\nFrançois Pinard                 pinard@iro.umontreal.ca\nFred Fish                       fnf@ninemoons.com\nGanesan Rajagopal               rganesan@novell.com\nGarrett D'Amore                 garrett@qualcomm.com\nGarth Corral                    garthc@inktomi.com\nGary V Vaughan                  gvaughan@oranda.demon.co.uk\nGavin Smith                     gavinsmith0123@gmail.com\nGeoffrey Keating                geoffk@apple.com\nGlenn Amerine                   glenn@pie.mhsc.org\nGord Matzigkeit                 gord@gnu.ai.mit.edu\nGordon Sadler                   gbsadler1@lcisp.com\nGraham Reitz                    grahamreitz@me.com\nGreg A. Woods                   woods@most.weird.com\nGreg Schafer                    gschafer@zip.com.au\nGuido Draheim                   guidod@gmx.de\nGuillermo Ontañón               gontanonext@pandasoftware.es\nGustavo Carneiro                gjc@inescporto.pt\nGwenole Beauchesne              gbeauchesne@mandrakesoft.com\nH.J. Lu                         hjl@lucon.org\nH.Merijn Brand                  h.m.brand@hccnet.nl\nHans Ulrich Niedermann          hun@n-dimensional.de\nHanspeter Niederstrasser        fink@snaggledworks.com\nHarald Dunkel                   harald@CoWare.com\nHarlan Stenn                    Harlan.Stenn@pfcs.com\nHe Li                           tippa000@yahoo.com\nHenrik Frystyk Nielsen          frystyk@w3.org\nHib Eris                        hib@hiberis.nl\nHilko Bengen                    bengen@debian.org\nHolger Hans Peter Freyther      holger@freyther.de\nIan Lance Taylor                ian@cygnus.com\nIgnacy Gawedzki                 i@lri.fr\nИлья Н. Голубев                 gin@mo.msk.ru\nImacat                          imacat@mail.imacat.idv.tw\nInfirit                         infirit@gmail.com\nInoue                           inoue@ainet.or.jp\nJack Kelly                      jack@jackkelly.name\nJacob Bachmeyer                 jcb@gnu.org\nJames Amundson                  amundson@users.sourceforge.net\nJames Bostock                   james.bostock@gmail.com\nJames Henstridge                james@daa.com.au\nJames R. Van Zandt              jrv@vanzandt.mv.com\nJames Youngman                  jay@gnu.org\nJan Engelhardt                  jengelh@medozas.de\nJanos Farkas                    chexum@shadow.banki.hu\nJared Davis                     abiword@aiksaurus.com\nJason DeVinney                  jasondevinney@gmail.com\nJason Duell                     jcduell@lbl.gov\nJason Molenda                   crash@cygnus.co.jp\nJavier Jardón                   jjardon@gnome.org\nJeff Bailey                     Jbailey@phn.ca\nJeff A. Daily                   jeff.daily@pnl.gov\nJeff Garzik                     jgarzik@pobox.com\nJeff Squyres                    jsquyres@lam-mpi.org\nJens Elkner                     elkner@imsgroup.de\nJens Krüger                     jens_krueger@physik.tu-muenchen.de\nJens Petersen                   petersen@redhat.com\nJeremy Nimmer                   jwnimmer@alum.mit.edu\nJerome Lovy                     jlovy@multimania.com\nJerome Santini                  santini@chambord.univ-orleans.fr\nJesse Chisholm                  jesse@ctc.volant.org\nJim Meyering                    meyering@na-net.ornl.gov\nJoakim Tjernlund                Joakim.Tjernlund@transmode.se\nJochen Kuepper                  jochen@uni-duesseldorf.de\nJoel N. Weber II                nemo@koa.iolani.honolulu.hi.us\nJoerg-Martin Schwarz            jms@jms.prima.ruhr.de\nJohan Dahlin                    jdahlin@async.com.br\nJohan Danielsson                joda@pdc.kth.se\nJohan Kristensen                johankristensen@gmail.com\nJohannes Nicolai                johannes.nicolai@student.hpi.uni-potsdam.de\nJohn Calcote                    john.calcote@gmail.com\nJohn F Trudeau                  JohnTrudeau@firsthealth.com\nJohn Pierce                     hawkfan@pyrotechnics.com\nJohn Ratliff                    autoconf@technoplaza.net\nJohn R. Cary                    cary@txcorp.com\nJohn W. Coomes                  jcoomes@eng.Sun.COM\nJonathan L Peyton               jonathan.l.peyton@intel.com\nJonathan Nieder                 jrnieder@gmail.com\nJoseph S. Myers                 joseph@codesourcery.com\nJosh MacDonald                  jmacd@cs.berkeley.edu\nJoshua Cowan                    jcowan@jcowan.reslife.okstate.edu\nJoshua Root                     jmr@macports.org\njs pendry                       js.pendry@msdw.com\nJuergen A. Erhard               jae@laden.ilk.de\nJuergen Keil                    jk@tools.de\nJuergen Leising                 juergen.leising@gmx.de\nJulien Sopena                   julien.sopena@lip6.fr\nJürg Billeter                   j@bitron.ch\nKarl Berry                      kb@cs.umb.edu\nKarl Heuer                      kwzh@gnu.org\nKelley Cook                     kcook@gcc.gnu.org\nKent Boortz                     kent@mysql.com\nKevin Dalley                    kevin@aimnet.com\nKevin P. Fleming.               kpfleming@cox.net\nKevin Ryde                      user42@zip.com.au\nKevin Street                    street@iname.com\nKlaus Reichl                    Klaus.Reichl@alcatel.at\nKrzysztof Żelechowski           giecrilj@stegny.2a.pl\nL. Peter Deutsch                ghost@aladdin.com\nLadislav Strojil                Ladislav.Strojil@seznam.cz\nLarry Daniel                    larry@larrybrucedaniel.com\nLarry Jones                     larry.jones@sdrc.com\nLars Hecking                    lhecking@nmrc.ucc.ie\nLars J. Aas                     larsa@sim.no\nLaurent Morichetti              laurentm@cup.hp.com\nLeo Davis                       ldavis@fonix.com\nLeonardo Boiko                  leoboiko@conectiva.com.br\nLibor Bukata                    libor.bukata@oracle.com\nLoulou Pouchet                  loulou@lrde.epita.fr\nLudovic Courtès                 ludo@gnu.org\nLukas Fleischer                        lfleischer@lfos.de\nLuo Yi                          luoyi.ly@gmail.com\nMaciej Stachowiak               mstachow@mit.edu\nMaciej W. Rozycki               macro@ds2.pg.gda.pl\nManu Rouat                      emmanuel.rouat@wanadoo.fr\nMarc Herbert                    marc.herbert@intel.com\nMarcus Brinkmann                Marcus.Brinkmann@ruhr-uni-bochum.de\nMarcus G. Daniels               mgd@ute.santafe.edu\nMarius Vollmer                  mvo@zagadka.ping.de\nMarc-Antoine Perennou           Marc-Antoine@Perennou.com\nMark D. Baushke                 mdb@cvshome.org\nMark Eichin                     eichin@cygnus.com\nMark Elbrecht                   snowball3@bigfoot.com\nMark Galassi                    rosalia@nis.lanl.gov\nMark Mitchell                   mark@codesourcery.com\nMark Phillips                   msp@nortelnetworks.com\nMarkku Rossi                    mtr@ngs.fi\nMarkus Duft                     Markus.Duft@salomon.at\nMarkus F.X.J. Oberhumer         k3040e4@wildsau.idv-edu.uni-linz.ac.at\nMartin Bravenboer               martin@cs.uu.nl\nMartin Frydl                    martin@idoox.com\nMartin Waitz                    tali@admingilde.org\nMathias Doreille                doreille@smr.ch\nMathias Froehlich               M.Froehlich@science-computing.de\nMathias Hasselmann              mathias.hasselmann@gmx.de\nMatt Burgess                    matthew@linuxfromscratch.org\nMatt Leach                      mleach@cygnus.com\nMatthew D. Langston             langston@SLAC.Stanford.EDU\nMatthias Andree                 matthias.andree@gmx.de\nMatthias Clasen                 clasen@mathematik.uni-freiburg.de\nMatthias Klose                  doko@ubuntu.com\nMatthieu Baerts                 matttbe@glx-dock.org\nMax Horn                        max@quendi.de\nMaxim Sinev                     good@goods.ru\nMaynard Johnson                 maynardj@us.ibm.com\nMerijn de Jonge                 M.de.Jonge@cwi.nl\nMichael Brantley                Michael-Brantley@deshaw.com\nMichael Daniels                 mdaniels@rim.com\nMichael Hofmann                 mhofma@googlemail.com\nMichael Ploujnikov              ploujj@gmail.com\nMichael Zucchi                  notzed@gmail.com\nMichel de Ruiter                mdruiter@cs.vu.nl\nMike Castle                     dalgoda@ix.netcom.com\nMike Frysinger                  vapier@gentoo.org\nMike Nolta                      mrnolta@princeton.edu\nMiles Bader                     miles@ccs.mt.nec.co.jp\nMiloslav Trmac                  trmac@popelka.ms.mff.cuni.cz\nMiodrag Vallat                  miodrag@ifrance.com\nMirko Streckenbach              strecken@infosun.fmi.uni-passau.de\nMiro Hroncok                    miro@hroncok.cz\nMiroslaw Dobrzanski-Neumann     mne@mosaic-ag.com\nMorten Eriksen                  mortene@sim.no\nMotoyuki Kasahara               m-kasahr@sra.co.jp\nNathanael Nerode                neroden@twcny.rr.com\nNelson H. F. Beebe              beebe@math.utah.edu\nNicholas Wourms                 nwourms@netscape.net\nNick Bowler                     nbowler@elliptictech.com\nNick Brown                      brownn@brocade.com\nNick Gasson                     nick@nickg.me.uk\nNicola Fontana                  ntd@entidi.it\nNicolas Joly                    njoly@pasteur.fr\nNicolas Thiery                  nthiery@Icare.mines.edu\nNightStrike                     nightstrike@gmail.com\nNik A. Melchior                 nam1@cse.wustl.edu\nNikolai Weibull                 now@bitwi.se\nNISHIDA Keisuke                 knishida@nn.iij4u.or.jp\nNoah Friedman                   friedman@gnu.ai.mit.edu\nNorman Gray                     norman@astro.gla.ac.uk\nNyul Laszlo                     nyul@sol.cc.u-szeged.hu\nOKUJI Yoshinori                 okuji@kuicr.kyoto-u.ac.jp\nOlivier Fourdan                 fourdan@cena.fr\nOlivier Louchart-Fletcher       olivier@zipworld.com.au\nOlly Betts                      olly@muscat.co.uk\nOren Ben-Kiki                   oren@ben-kiki.org\nOwen Taylor                     otaylor@redhat.com\nPanther Martin                  mrsmiley98@lycos.com\nPatrick Welche                  prlw1@newn.cam.ac.uk\nPatrik Weiskircher              me@justp.at\nPaul Berrevoets                 paul@swi.com\nPaul D. Smith                   psmith@BayNetworks.COM\nPaul Eggert                     eggert@twinsun.com\nPaul Jarc                       prj@po.cwru.edu\nPaul Lunau                      temp@lunau.me.uk\nPaul Martinolich                martinol@datasync.com\nPaul Osmialowski                pawel.osmialowski@arm.com\nPaul Thomas                     PTHOMAS@novell.com\nPavel Raiskup                   praiskup@redhat.com\nPavel Roskin                    pavel_roskin@geocities.com\nPavel Sanda                     ps@twin.jikos.cz\nPer Bothner                     bothner@cygnus.com\nPer Cederqvist                  ceder@lysator.liu.se\nPer Oyvind Hvidsten             poeh@enter.vg\nPeter Breitenlohner             peb@mppmu.mpg.de\nPeter Eisentraut                peter_e@gmx.net\nPeter Gavin                     pgavin@debaser.kicks-ass.org\nPeter Hutterer                  peter.hutterer@who-t.net\nPeter Johansson                 trojkan@gmail.com\nPeter Mattis                    petm@scam.XCF.Berkeley.EDU\nPeter Muir                      iyhi@yahoo.com\nPeter O'Gorman                  peter@pogma.com\nPeter Rosin                     peda@lysator.liu.se\nPeter Seiderer                  seiderer123@ciselant.de\nPetr Hracek                     phracek@redhat.com\nPetter Reinholdtsen             pere@hungry.com\nPetteri Räty                    betelgeuse@gentoo.org\nPhil Edwards                    phil@jaj.com\nPhil Nelson                     phil@cs.wwu.edu\nPhilip Fong                     pwlfong@users.sourceforge.net\nPhilip S Tellis                 philip@ncst.ernet.in\nPhilipp A. Hartmann             philipp.hartmann@offis.de\nПухальский Юрий Андреевич       pooh@cryptopro.ru\nQuentin Glidic                  sardemff7+gnu@sardemff7.net\nRainer Orth                     ro@techfak.uni-bielefeld.de\nRafael Laboissiere              laboissiere@psy.mpg.de\nRainer Tammer                   tammer@tammer.net\nRaja R Harinath                 harinath@cs.umn.edu\nRalf Corsepius                  ralf.corsepius@gmail.com\nRalf Menzel                     menzel@ls6.cs.uni-dortmund.de\nRalf Wildenhues                 Ralf.Wildenhues@gmx.de\nRalph Schleicher                rs@purple.UL.BaWue.DE\nRamón García Fernández          ramon@jl1.quim.ucm.es\nReuben Thomas                   rrt@sc3d.org\nRich Wales                      richw@webcom.com\nRichard Boulton                 richard@tartarus.org\nRichard Dawe                    rich@phekda.freeserve.co.uk\nRichard W.M. Jones              rjones@redhat.com\nRob Savoye                      rob@cygnus.com\nRobert Bihlmeyer                robbe@orcus.priv.at\nRobert Boehne                   rboehne@ricardo-us.com\nRobert Collins                  robert.collins@itdomain.com.au\nRobert Menteer                  reetnem@mac.com\nRobert Swafford                 robert.swafford@l-3com.com\nRobert Wanamaker                rlw@nycap.rr.com\nRoberto Bagnara                 bagnara@cs.unipr.it\nRoman Fietze                    roman.fietze@telemotive.de\nRonald Copley                   ronald.copley@gmail.com\nRonald Landheer                 ronald@landheer.com\nRoumen Petrov                   bugtrack@roumenpetrov.info\nRuss Allbery                    rra@stanford.edu\nRusty Ballinger                 rusty@rlyeh.engr.sgi.com\nRyan Lortie                     desrt@desrt.ca\nRyan T. Sammartino              ryants@shaw.ca\nSam Hocevar                     sam@zoy.org\nSam Sirlin                      sam@kalessin.jpl.nasa.gov\nSam Steingold                   sds@gnu.org\nSamuel Tardieu                  sam@rfc1149.net\nSamy Mahmoudi                   samy.mahmoudi@gmail.com\nSander Niemeijer                niemeijer@science-and-technology.nl\nSantiago Vila                   sanvila@unex.es\nScott James Remnant             scott@netsplit.com\nSébastien Wilmet                swilmet@gnome.org\nSergey Poznyakoff               gray@gnu.org.ua\nSergey Vlasov                   vsu@mivlgu.murom.ru\nSeth Alves                      alves@hungry.com\nShannon L. Brown                slbrow@sandia.gov\nShuhei Amakawa                  sa264@cam.ac.uk\nShigio Yamaguchi                shigio@tamacom.com\nSimon Josefsson                 jas@extundo.com\nSimon Richter                   sjr@debian.org\nStefan Nordhausen               nordhaus@informatik.hu-berlin.de\nStefano Lattarini               stefano.lattarini@gmail.com\nStepan Kasal                    kasal@math.cas.cz\nSteve M. Robbins                steve@nyongwa.montreal.qc.ca\nSteve Goetze                    goetze@dovetail.com\nSteven Drake                    sbd@NetBSD.org\nSteven G. Johnson               stevenj@alum.mit.edu\nSven Verdoolaege                skimo@kotnet.org\nTamara L. Dahlgren              dahlgren1@llnl.gov\nTatu Ylonen                     ylo@ssh.fi\nTeun Burgers                    burgers@ecn.nl\nThe Crimson Binome              steve@nyongwa.montreal.qc.ca\nTheodoros V. Kalamatianos       thkala@gmail.com\nThien-Thi Nguyen                ttn@glug.org\nThomas Fitzsimmons              fitzsim@redhat.com\nThomas Gagne                    tgagne@ix.netcom.com\nThomas Jahns                    jahns@dkrz.de\nThomas Klausner                 tk@giga.or.at\nThomas Morgan                   tmorgan@pobox.com\nThomas Schwinge                 tschwinge@gnu.org\nThomas Tanner                   tanner@ffii.org\nToralf Förster                  toralf.foerster@gmx.de\nTim Goodwin                     tjg@star.le.ac.uk\nTim Landscheidt                 tim@tim-landscheidt.de\nTim Mooney                      mooney@dogbert.cc.ndsu.NoDak.edu\nTim Retout                      diocles@debian.org\nTim Rice                        tim@multitalents.net\nTim Van Holder                  tim.van.holder@pandora.be\nTobias Hansen                   thansen@debian.org\nToshio Kuratomi                 toshio@tiki-lounge.com\nTom Epperly                     tepperly@llnl.gov\nTom Rini                        tom_rini@mentor.com\nUlrich Drepper                  drepper@gnu.ai.mit.edu\nUlrich Eckhardt                 eckhardt@satorlaser.com\nVáclav Haisman                  V.Haisman@sh.cvut.cz\nVáclav Zeman                    vhaisman@gmail.com\nVadim Zeitlin                   Vadim.zeitlin@dptmaths.ens-cachan.fr\nVasyl Khalak                    basiliomail@gmail.com\nVincent Lefevre                 vincent@vinc17.org\nVladimir Serbinenko             phcoder@gmail.com\nVolker Boerchers                vboerchers@tecon.de\nWeiller Ronfini                 weillerronfini@yahoo.com.br\nWerner John                     john@oswf.de\nWerner Koch                     wk@isil.d.shuttle.de\nWerner Lemberg                  wl@gnu.org\nWilliam Pursell                 bill.pursell@gmail.com\nWilliam S Fulton                wsf@fultondesigns.co.uk\nYann Droneaud                   ydroneaud@meuh.eu.org\nYounes Younes                   younes@cs.tu-berlin.de\nZack Weinberg                   zackw@panix.com\nZbigniew Jędrzejewski-Szmek     zbyszek@in.waw.pl\nZoltan Rado                     z.rado@chello.hu\n\n;; Local Variables:\n;; mode: text\n;; coding: utf-8\n;; End:\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/AUTHORS.txt",
    "content": "\nHIDAPI Authors:\n\nAlan Ott <alan@signal11.us>:\n\tOriginal Author and Maintainer\n\tLinux, Windows, and Mac implementations\n\nLudovic Rousseau <rousseau@debian.org>:\n\tFormatting for Doxygen documentation\n\tBug fixes\n\tCorrectness fixes\n\nlibusb/hidapi Team:\n\tDevelopment/maintainance since June 4th 2019\n\nFor a comprehensive list of contributions, see the commit list at github:\n\thttps://github.com/libusb/hidapi/graphs/contributors\n\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE-bsd.txt",
    "content": "Copyright (c) 2010, Alan Ott, Signal 11 Software\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n    * Redistributions of source code must retain the above copyright notice,\n      this list of conditions and the following disclaimer.\n    * Redistributions in binary form must reproduce the above copyright\n      notice, this list of conditions and the following disclaimer in the\n      documentation and/or other materials provided with the distribution.\n    * Neither the name of Signal 11 Software nor the names of its\n      contributors may be used to endorse or promote products derived from\n      this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE-gpl3.txt",
    "content": "                    GNU GENERAL PUBLIC LICENSE\n                       Version 3, 29 June 2007\n\n Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The GNU General Public License is a free, copyleft license for\nsoftware and other kinds of works.\n\n  The licenses for most software and other practical works are designed\nto take away your freedom to share and change the works.  By contrast,\nthe GNU General Public License is intended to guarantee your freedom to\nshare and change all versions of a program--to make sure it remains free\nsoftware for all its users.  We, the Free Software Foundation, use the\nGNU General Public License for most of our software; it applies also to\nany other work released this way by its authors.  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To \"grant\" such a patent license to a\nparty means to make such an agreement or commitment not to enforce a\npatent against the party.\n\n  If you convey a covered work, knowingly relying on a patent license,\nand the Corresponding Source of the work is not available for anyone\nto copy, free of charge and under the terms of this License, through a\npublicly available network server or other readily accessible means,\nthen you must either (1) cause the Corresponding Source to be so\navailable, or (2) arrange to deprive yourself of the benefit of the\npatent license for this particular work, or (3) arrange, in a manner\nconsistent with the requirements of this License, to extend the patent\nlicense to downstream recipients.  \"Knowingly relying\" means you have\nactual knowledge that, but for the patent license, your conveying the\ncovered work in a country, or your recipient's use of the covered work\nin a country, would infringe one or more identifiable patents in that\ncountry that you have reason to believe are valid.\n\n  If, pursuant to or in connection with a single transaction or\narrangement, you convey, or propagate by procuring conveyance of, a\ncovered work, and grant a patent license to some of the parties\nreceiving the covered work authorizing them to use, propagate, modify\nor convey a specific copy of the covered work, then the patent license\nyou grant is automatically extended to all recipients of the covered\nwork and works based on it.\n\n  A patent license is \"discriminatory\" if it does not include within\nthe scope of its coverage, prohibits the exercise of, or is\nconditioned on the non-exercise of one or more of the rights that are\nspecifically granted under this License.  You may not convey a covered\nwork if you are a party to an arrangement with a third party that is\nin the business of distributing software, under which you make payment\nto the third party based on the extent of your activity of conveying\nthe work, and under which the third party grants, to any of the\nparties who would receive the covered work from you, a discriminatory\npatent license (a) in connection with copies of the covered work\nconveyed by you (or copies made from those copies), or (b) primarily\nfor and in connection with specific products or compilations that\ncontain the covered work, unless you entered into that arrangement,\nor that patent license was granted, prior to 28 March 2007.\n\n  Nothing in this License shall be construed as excluding or limiting\nany implied license or other defenses to infringement that may\notherwise be available to you under applicable patent law.\n\n  12. No Surrender of Others' Freedom.\n\n  If conditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot convey a\ncovered work so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you may\nnot convey it at all.  For example, if you agree to terms that obligate you\nto collect a royalty for further conveying from those to whom you convey\nthe Program, the only way you could satisfy both those terms and this\nLicense would be to refrain entirely from conveying the Program.\n\n  13. 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Disclaimer of Warranty.\n\n  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY\nAPPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT\nHOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY\nOF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,\nTHE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\nPURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM\nIS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF\nALL NECESSARY SERVICING, REPAIR OR CORRECTION.\n\n  16. Limitation of Liability.\n\n  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS\nTHE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY\nGENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE\nUSE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF\nDATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD\nPARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),\nEVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF\nSUCH DAMAGES.\n\n  17. Interpretation of Sections 15 and 16.\n\n  If the disclaimer of warranty and limitation of liability provided\nabove cannot be given local legal effect according to their terms,\nreviewing courts shall apply local law that most closely approximates\nan absolute waiver of all civil liability in connection with the\nProgram, unless a warranty or assumption of liability accompanies a\ncopy of the Program in return for a fee.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nstate the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software: you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation, either version 3 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License\n    along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\nAlso add information on how to contact you by electronic and paper mail.\n\n  If the program does terminal interaction, make it output a short\nnotice like this when it starts in an interactive mode:\n\n    <program>  Copyright (C) <year>  <name of author>\n    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, your program's commands\nmight be different; for a GUI interface, you would use an \"about box\".\n\n  You should also get your employer (if you work as a programmer) or school,\nif any, to sign a \"copyright disclaimer\" for the program, if necessary.\nFor more information on this, and how to apply and follow the GNU GPL, see\n<http://www.gnu.org/licenses/>.\n\n  The GNU General Public License does not permit incorporating your program\ninto proprietary programs.  If your program is a subroutine library, you\nmay consider it more useful to permit linking proprietary applications with\nthe library.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.  But first, please read\n<http://www.gnu.org/philosophy/why-not-lgpl.html>.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE-orig.txt",
    "content": " HIDAPI - Multi-Platform library for\n communication with HID devices.\n\n Copyright 2009, Alan Ott, Signal 11 Software.\n All Rights Reserved.\n \n This software may be used by anyone for any reason so\n long as the copyright notice in the source files\n remains intact.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/LICENSE.txt",
    "content": "HIDAPI can be used under one of three licenses.\n\n1. The GNU General Public License, version 3.0, in LICENSE-gpl3.txt\n2. A BSD-Style License, in LICENSE-bsd.txt.\n3. The more liberal original HIDAPI license. LICENSE-orig.txt\n\nThe license chosen is at the discretion of the user of HIDAPI. For example:\n1. An author of GPL software would likely use HIDAPI under the terms of the\nGPL.\n\n2. An author of commercial closed-source software would likely use HIDAPI\nunder the terms of the BSD-style license or the original HIDAPI license.\n\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/hidapi-hidapi-0.14.0/README.md",
    "content": "## HIDAPI library for Windows, Linux, FreeBSD and macOS\n\n| CI instance          | Status |\n|----------------------|--------|\n| `Linux/macOS/Windows (master)` | [![GitHub Builds](https://github.com/libusb/hidapi/workflows/GitHub%20Builds/badge.svg?branch=master)](https://github.com/libusb/hidapi/actions/workflows/builds.yml?query=branch%3Amaster) |\n| `Windows (master)` | [![Build status](https://ci.appveyor.com/api/projects/status/xfmr5fo8w0re8ded/branch/master?svg=true)](https://ci.appveyor.com/project/libusb/hidapi/branch/master) |\n| `BSD, last build (branch/PR)` | [![builds.sr.ht status](https://builds.sr.ht/~z3ntu/hidapi.svg)](https://builds.sr.ht/~z3ntu/hidapi) |\n| `Coverity Scan (last)` | ![Coverity Scan](https://scan.coverity.com/projects/583/badge.svg) |\n\nHIDAPI is a multi-platform library which allows an application to interface\nwith USB and Bluetooth HID-Class devices on Windows, Linux, FreeBSD, and macOS.\nHIDAPI can be either built as a shared library (`.so`, `.dll` or `.dylib`) or\ncan be embedded directly into a target application by adding a _single source_\nfile (per platform) and a single header.<br>\nSee [remarks](BUILD.md#embedding-hidapi-directly-into-your-source-tree) on embedding _directly_ into your build system.\n\nHIDAPI library was originally developed by Alan Ott ([signal11](https://github.com/signal11)).\n\nIt was moved to [libusb/hidapi](https://github.com/libusb/hidapi) on June 4th, 2019, in order to merge important bugfixes and continue development of the library.\n\n## Table of Contents\n\n* [About](#about)\n    * [Test GUI](#test-gui)\n    * [Console Test App](#console-test-app)\n* [What Does the API Look Like?](#what-does-the-api-look-like)\n* [License](#license)\n* [Installing HIDAPI](#installing-hidapi)\n* [Build from Source](#build-from-source)\n\n\n## About\n\n### HIDAPI has four back-ends:\n* Windows (using `hid.dll`)\n* Linux/hidraw (using the Kernel's hidraw driver)\n* libusb (using libusb-1.0 - Linux/BSD/other UNIX-like systems)\n* macOS (using IOHidManager)\n\nOn Linux, either the hidraw or the libusb back-end can be used. There are\ntradeoffs, and the functionality supported is slightly different. Both are\nbuilt by default. It is up to the application linking to hidapi to choose\nthe backend at link time by linking to either `libhidapi-libusb` or\n`libhidapi-hidraw`.\n\nNote that you will need to install an udev rule file with your application\nfor unprivileged users to be able to access HID devices with hidapi. Refer\nto the [69-hid.rules](udev/69-hid.rules) file in the `udev` directory\nfor an example.\n\n#### __Linux/hidraw__ (`linux/hid.c`):\n\nThis back-end uses the hidraw interface in the Linux kernel, and supports\nboth USB and Bluetooth HID devices. It requires kernel version at least 2.6.39\nto build. In addition, it will only communicate with devices which have hidraw\nnodes associated with them.\nKeyboards, mice, and some other devices which are blacklisted from having\nhidraw nodes will not work. Fortunately, for nearly all the uses of hidraw,\nthis is not a problem.\n\n#### __Linux/FreeBSD/libusb__ (`libusb/hid.c`):\n\nThis back-end uses libusb-1.0 to communicate directly to a USB device. This\nback-end will of course not work with Bluetooth devices.\n\n### Test GUI\n\nHIDAPI also comes with a Test GUI. The Test GUI is cross-platform and uses\nFox Toolkit <http://www.fox-toolkit.org>.  It will build on every platform\nwhich HIDAPI supports.  Since it relies on a 3rd party library, building it\nis optional but it is useful when debugging hardware.\n\nNOTE: Test GUI based on Fox Toolkit is not actively developed nor supported\nby HIDAPI team. It is kept as a historical artifact. It may even work sometime\nor on some platforms, but it is not going to get any new features or bugfixes.\n\nInstructions for installing Fox-Toolkit on each platform is not provided.\nMake sure to use Fox-Toolkit v1.6 if you choose to use it.\n\n### Console Test App\n\nIf you want to play around with your HID device before starting\nany development with HIDAPI and using a GUI app is not an option for you, you may try [`hidapitester`](https://github.com/todbot/hidapitester).\n\nThis app has a console interface for most of the features supported\nby HIDAPI library.\n\n## What Does the API Look Like?\n\nThe API provides the most commonly used HID functions including sending\nand receiving of input, output, and feature reports. The sample program,\nwhich communicates with a heavily hacked up version of the Microchip USB\nGeneric HID sample looks like this (with error checking removed for\nsimplicity):\n\n**Warning: Only run the code you understand, and only when it conforms to the\ndevice spec. Writing data (`hid_write`) at random to your HID devices can break them.**\n\n```c\n#include <stdio.h> // printf\n#include <wchar.h> // wchar_t\n\n#include <hidapi.h>\n\n#define MAX_STR 255\n\nint main(int argc, char* argv[])\n{\n\tint res;\n\tunsigned char buf[65];\n\twchar_t wstr[MAX_STR];\n\thid_device *handle;\n\tint i;\n\n\t// Initialize the hidapi library\n\tres = hid_init();\n\n\t// Open the device using the VID, PID,\n\t// and optionally the Serial number.\n\thandle = hid_open(0x4d8, 0x3f, NULL);\n\tif (!handle) {\n\t\tprintf(\"Unable to open device\\n\");\n\t\thid_exit();\n \t\treturn 1;\n\t}\n\n\t// Read the Manufacturer String\n\tres = hid_get_manufacturer_string(handle, wstr, MAX_STR);\n\tprintf(\"Manufacturer String: %ls\\n\", wstr);\n\n\t// Read the Product String\n\tres = hid_get_product_string(handle, wstr, MAX_STR);\n\tprintf(\"Product String: %ls\\n\", wstr);\n\n\t// Read the Serial Number String\n\tres = hid_get_serial_number_string(handle, wstr, MAX_STR);\n\tprintf(\"Serial Number String: (%d) %ls\\n\", wstr[0], wstr);\n\n\t// Read Indexed String 1\n\tres = hid_get_indexed_string(handle, 1, wstr, MAX_STR);\n\tprintf(\"Indexed String 1: %ls\\n\", wstr);\n\n\t// Toggle LED (cmd 0x80). The first byte is the report number (0x0).\n\tbuf[0] = 0x0;\n\tbuf[1] = 0x80;\n\tres = hid_write(handle, buf, 65);\n\n\t// Request state (cmd 0x81). The first byte is the report number (0x0).\n\tbuf[0] = 0x0;\n\tbuf[1] = 0x81;\n\tres = hid_write(handle, buf, 65);\n\n\t// Read requested state\n\tres = hid_read(handle, buf, 65);\n\n\t// Print out the returned buffer.\n\tfor (i = 0; i < 4; i++)\n\t\tprintf(\"buf[%d]: %d\\n\", i, buf[i]);\n\n\t// Close the device\n\thid_close(handle);\n\n\t// Finalize the hidapi library\n\tres = hid_exit();\n\n\treturn 0;\n}\n```\n\nYou can also use [hidtest/test.c](hidtest/test.c)\nas a starting point for your applications.\n\n\n## License\n\nHIDAPI may be used by one of three licenses as outlined in [LICENSE.txt](LICENSE.txt).\n\n## Installing HIDAPI\n\nIf you want to build your own application that uses HID devices with HIDAPI,\nyou need to get HIDAPI development package.\n\nDepending on what your development environment is, HIDAPI likely to be provided\nby your package manager.\n\nFor instance on Ubuntu, HIDAPI is available via APT:\n```sh\nsudo apt install libhidapi-dev\n```\n\nHIDAPI package name for other systems/package managers may differ.\nCheck the documentation/package list of your package manager.\n\n## Build from Source\n\nCheck [BUILD.md](BUILD.md) for details.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libftdi1-1.5/AUTHORS",
    "content": "Main developers:\n\n  Intra2net AG <opensource@intra2net.com>\n\nContributors in alphabetical order,\nsee Changelog for full details:\n\n  Adam Malinowski <amalinowski75@gmail.com>\n  Alain Abbas <aa@libertech.fr>\n  Alex Harford <harford@gmail.com>\n  Alexander Lehmann <lehmanna@in.tum.de>\n  Anders Larsen <al@alarsen.net>\n  Andrei Errapart <a.errapart@trenz-electronic.de>\n  Andrew John Rogers <andrew@rogerstech.co.uk>\n  Arnim Läuger <arnim.laeuger@gmx.net>\n  Aurelien Jarno <aurelien@aurel32.net>\n  Benjamin Vanheuverzwijn <bvanheu@gmail.com>\n  Chris Morgan <chmorgan@gmail.com>\n  Chris Zeh <chris.w.zeh@gmail.com>\n  Claudio Lanconelli <claudiolanconelli@gmail.com>\n  Clifford Wolf <clifford@clifford.at>\n  Dan Dedrick <dan.dedrick@gmail.com>\n  Daniel Kirkham <dk2@kirkham.id.au>\n  David Challis <dchallis@qsimaging.com>\n  Davide Michelizza <dmichelizza@gmail.com>\n  Denis Sirotkin <reg.libftdi@demitel.ru>\n  Diego Elio Pettenò <flameeyes@flameeyes.com>\n  Emil <emil@datel.co.uk>\n  Eneas U de Queiroz <cote2004-github@yahoo.com>\n  Eric Schott <els6@psu.edu>\n  Eugene Hutorny <eugene@hutorny.in.ua>\n  Evan Nemerson <evan@coeus-group.com>\n  Evgeny Sinelnikov <sin@geoft.ru>\n  Fabrice Fontaine <fontaine.fabrice@gmail.com>\n  Fahrzin Hemmati <fahhem@gmail.com>\n  Flynn Marquardt <ftdi@flynnux.de>\n  Forest Crossman <cyrozap@gmail.com>\n  Frank Dana <ferdnyc@gmail.com>\n  Holger Mößinger <h.moessinger@primes.de>\n  Ian Abbott <abbotti@mev.co.uk>\n  Jared Boone <jared@sharebrained.com>\n  Jarkko Sonninen <kasper@iki.fi>\n  Jean-Daniel Merkli <jdmerkli@computerscience.ch>\n  Jochen Sprickerhof <jochen@sprickerhof.de>\n  Joe Zbiciak <intvnut@gmail.com>\n  Jon Beniston <jon@beniston.com>\n  Jordan Rupprecht <rupprecht@google.com>\n  Juergen Beisert <juergen.beisert@weihenstephan.org>\n  Lorenz Moesenlechner <lorenz@hcilab.org>\n  Marek Vavruša <marek@vavrusa.com>\n  Marius Kintel <kintel@sim.no>\n  Mark Hämmerling <mail@markh.de>\n  Matthias Janke <janke@physi.uni-heidelberg.de>\n  Matthias Kranz <matthias@hcilab.org>\n  Matthias Richter <mail.to.mr@gmx.de>\n  Matthijs ten Berge <m.h.tenberge@alumnus.utwente.nl>\n  Max <max@koeln.ccc.de>\n  Maxwell Dreytser <admin@mdtech.us>\n  Michel Zou <xantares09@hotmail.com>\n  Mike Frysinger <vapier.adi@gmail.com>\n  Nathael Pajani <nathael.pajani@ed3l.fr>\n  Nathan Fraser <ndf@undershorts.org>\n  Oleg Seiljus <oseiljus@xverve.com>\n  Paul Fertser <fercerpav@gmail.com>\n  Pawel Jewstafjew <pawel.jewstafjew@gmail.com>\n  Peter Holik <peter@holik.at>\n  Raphael Assenat <raph@8d.com>\n  Richard Shaw <hobbes1069@gmail.com>\n  Robby McKilliam <robby.mckilliam@myriota.com>\n  Robert Cox <Robert.cox@novatechweb.com>\n  Robin Haberkorn <haberkorn@metratec.com>\n  Rodney Sinclair <rodney@sinclairrf.com>\n  Rogier Wolff <R.E.Wolff@harddisk-recovery.nl>\n  Rolf Fiedler <derRolf@gmx-topmail.de>\n  Roman Lapin <lampus.lapin@gmail.com>\n  Salvador Eduardo Tropea <salvador@inti.gob.ar>\n  Stephan Linz <linz@li-pro.net>\n  Steven Turner <steven.turner@ftdichip.com>\n  Tarek Heiland <tarek@illimitable.com>\n  Thilo Schulz <thilo@tjps.eu>\n  Thimo Eichstaedt <abc@digithi.de>\n  Thomas Fischl <fischl@fundf.net>\n  Thomas Klose <thomas.klose@hiperscan.com>\n  Tim Ansell <mithro@mithis.com>\n  Tom Saunders <trsaunders@gmail.com>\n  Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>\n  Vladimir Yakovlev <nagos@inbox.ru>\n  Wilfried Holzke <libftdi@holzke.net>\n  Xiaofan Chen <xiaofanc@gmail.com>\n  Yegor Yefremov <yegorslists@googlemail.com>\n  Yi-Shin Li <ysli@araisrobo.com>\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libftdi1-1.5/COPYING-CMAKE-SCRIPTS",
    "content": "Redistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions\nare met:\n\n1. Redistributions of source code must retain the copyright\n   notice, this list of conditions and the following disclaimer.\n2. Redistributions in binary form must reproduce the copyright\n   notice, this list of conditions and the following disclaimer in the\n   documentation and/or other materials provided with the distribution.\n3. The name of the author may not be used to endorse or promote products \n   derived from this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR\nIMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\nOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\nIN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\nINCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\nNOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\nDATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\nTHEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\nTHIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libftdi1-1.5/COPYING.GPL",
    "content": "\t\t    GNU GENERAL PUBLIC LICENSE\n\t\t       Version 2, June 1991\n\n Copyright (C) 1989, 1991 Free Software Foundation, Inc.,\n 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n\t\t\t    Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  By contrast, the GNU General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users.  This\nGeneral Public License applies to most of the Free Software\nFoundation's software and to any other program whose authors commit to\nusing it.  (Some other Free Software Foundation software is covered by\nthe GNU Lesser General Public License instead.)  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthis service if you wish), that you receive source code or can get it\nif you want it, that you can change the software or use pieces of it\nin new free programs; and that you know you can do these things.\n\n  To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have.  You must make sure that they, too, receive or can get the\nsource code.  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Each licensee is addressed as \"you\".\n\nActivities other than copying, distribution and modification are not\ncovered by this License; they are outside its scope.  The act of\nrunning the Program is not restricted, and the output from the Program\nis covered only if its contents constitute a work based on the\nProgram (independent of having been made by running the Program).\nWhether that is true depends on what the Program does.\n\n  1. You may copy and distribute verbatim copies of the Program's\nsource code as you receive it, in any medium, provided that you\nconspicuously and appropriately publish on each copy an appropriate\ncopyright notice and disclaimer of warranty; keep intact all the\nnotices that refer to this License and to the absence of any warranty;\nand give any other recipients of the Program a copy of this License\nalong with the Program.\n\nYou may charge a fee for the physical act of transferring a copy, and\nyou may at your option offer warranty protection in exchange for a fee.\n\n  2. You may modify your copy or copies of the Program or any portion\nof it, thus forming a work based on the Program, and copy and\ndistribute such modifications or work under the terms of Section 1\nabove, provided that you also meet all of these conditions:\n\n    a) You must cause the modified files to carry prominent notices\n    stating that you changed the files and the date of any change.\n\n    b) You must cause any work that you distribute or publish, that in\n    whole or in part contains or is derived from the Program or any\n    part thereof, to be licensed as a whole at no charge to all third\n    parties under the terms of this License.\n\n    c) If the modified program normally reads commands interactively\n    when run, you must cause it, when started running for such\n    interactive use in the most ordinary way, to print or display an\n    announcement including an appropriate copyright notice and a\n    notice that there is no warranty (or else, saying that you provide\n    a warranty) and that users may redistribute the program under\n    these conditions, and telling the user how to view a copy of this\n    License.  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You may copy and distribute the Program (or a work based on it,\nunder Section 2) in object code or executable form under the terms of\nSections 1 and 2 above provided that you also do one of the following:\n\n    a) Accompany it with the complete corresponding machine-readable\n    source code, which must be distributed under the terms of Sections\n    1 and 2 above on a medium customarily used for software interchange; or,\n\n    b) Accompany it with a written offer, valid for at least three\n    years, to give any third party, for a charge no more than your\n    cost of physically performing source distribution, a complete\n    machine-readable copy of the corresponding source code, to be\n    distributed under the terms of Sections 1 and 2 above on a medium\n    customarily used for software interchange; or,\n\n    c) Accompany it with the information you received as to the offer\n    to distribute corresponding source code.  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  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libftdi1-1.5/COPYING.LIB",
    "content": "                  GNU LIBRARY GENERAL PUBLIC LICENSE\n                       Version 2, June 1991\n\n Copyright (C) 1991 Free Software Foundation, Inc.\n 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n[This is the first released version of the library GPL.  It is\n numbered 2 because it goes with version 2 of the ordinary GPL.]\n\n                            Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  By contrast, the GNU General Public\nLicenses are intended to guarantee your freedom to share and change\nfree software--to make sure the software is free for all its users.\n\n  This license, the Library General Public License, applies to some\nspecially designated Free Software Foundation software, and to any\nother libraries whose authors decide to use it.  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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN\nWRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY\nAND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU\nFOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR\nCONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE\nLIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING\nRENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A\nFAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF\nSUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH\nDAMAGES.\n\n                     END OF TERMS AND CONDITIONS\n\f\n           How to Apply These Terms to Your New Libraries\n\n  If you develop a new library, and you want it to be of the greatest\npossible use to the public, we recommend making it free software that\neveryone can redistribute and change.  You can do so by permitting\nredistribution under these terms (or, alternatively, under the terms of the\nordinary General Public License).\n\n  To apply these terms, attach the following notices to the library.  It is\nsafest to attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least the\n\"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the library's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This library is free software; you can redistribute it and/or\n    modify it under the terms of the GNU Library General Public\n    License as published by the Free Software Foundation; either\n    version 2 of the License, or (at your option) any later version.\n\n    This library is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n    Library General Public License for more details.\n\n    You should have received a copy of the GNU Library General Public\n    License along with this library; if not, write to the Free Software\n    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n\nAlso add information on how to contact you by electronic and paper mail.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the library, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the\n  library `Frob' (a library for tweaking knobs) written by James Random Hacker.\n\n  <signature of Ty Coon>, 1 April 1990\n  Ty Coon, President of Vice\n\nThat's all there is to it!\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libftdi1-1.5/LICENSE",
    "content": "The C library \"libftdi1\" is distributed under the\nGNU Library General Public License version 2.\n\nA copy of the GNU Library General Public License (LGPL) is included\nin this distribution, in the file COPYING.LIB.\n\n----------------------------------------------------------------------\n\nThe C++ wrapper \"ftdipp1\" is distributed under the GNU General\nPublic License version 2 (with a special exception described below).\n\nA copy of the GNU General Public License (GPL) is included\nin this distribution, in the file COPYING.GPL.\n\nAs a special exception, if other files instantiate templates or use macros\nor inline functions from this file, or you compile this file and link it\nwith other works to produce a work based on this file, this file\ndoes not by itself cause the resulting work to be covered\nby the GNU General Public License.\n\nHowever the source code for this file must still be made available\nin accordance with section (3) of the GNU General Public License.\n\nThis exception does not invalidate any other reasons why a work based\non this file might be covered by the GNU General Public License.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README",
    "content": "--------------------------------------------------------------------\nlibftdi version 1.5\n--------------------------------------------------------------------\n\nlibftdi - A library (using libusb) to talk to FTDI's UART/FIFO chips\nincluding the popular bitbang mode.\n\nThe following chips are supported:\n* FT230X\n- FT4232H / FT2232H\n- FT232R  / FT245R\n- FT2232L / FT2232D / FT2232C\n- FT232BM / FT245BM (and the BL/BQ variants)\n- FT8U232AM / FT8U245AM\n\nlibftdi requires libusb 1.x.\n\nThe AUTHORS file contains a list of all the people\nthat made libftdi possible what it is today.\n\nChanges\n-------\n* Implement tc[io]flush methods & deprecate broken purge_buffers methods\n\n  Please check your code for ftdi_usb_purge_rx_buffer(),\n  ftdi_usb_purge_tx_buffer() and ftdi_usb_purge_buffers()\n  and migrate to the new ftdi_tc[io]flush() methods.\n\n  Old code will continue to function, but you'll get\n  a deprecation warning during compilation.\n\n* Add program to test buffer flush (purge) functionality\n* Add kernel driver auto attach/detach.\n  See new AUTO_DETACH_REATACH_SIO_MODULE option\n* Add ftdi_setflowctrl_xonxoff()\n* ftdi_eeprom / eeprom handling:\n  * Unify handling of all boolean eeprom flags\n  * Add device release number support\n  * Add channel_a_driver support for type xxR chips\n  * Add support for group0 drive levels on x232H chips\n  * Fix handling of high_current_drive parameter\n  * Fix inverted handling of VCP driver field for TYPE_R chips\n  * New --verbose option for eeprom decode operation\n* Add example code for async mode\n* Add SPDX license identifiers to the core library & ftdi_eeprom\n* Various python SWIG wrapper improvements\n* Various cmake file improvements\n* Fix small bugs in error code paths\n\nYou'll find the newest version of libftdi at:\nhttps://www.intra2net.com/en/developer/libftdi\n\n\nQuick start\n-----------\nmkdir build\ncd build\n\ncmake -DCMAKE_INSTALL_PREFIX=\"/usr\" ../\nmake\nmake install\n\nMore verbose build instructions are in \"README.build\"\n\n--------------------------------------------------------------------\nwww.intra2net.com                             2003-2020 Intra2net AG\n--------------------------------------------------------------------\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README.build",
    "content": "Here is a short tutorial on how to build libftdi git under\nUbuntu 12.10, But it is similar on other Linux distros.\n\n1) Install the build tools\nsudo apt-get install build-essential (yum install make automake gcc gcc-c++ kernel-devel)\nsudo apt-get install git-core (yum install git)\nsudo apt-get install cmake (yum install cmake)\nsudo apt-get install doxygen (for building documentations) (yum install doxygen)\n\n2) Install dependencies\nsudo apt-get install libusb-1.0-devel (yum install libusb-devel)\n(if the system comes with older version like 1.0.8 or\nearlier, it is recommended you build libusbx-1.0.14 or later).\n\nsudo apt-get install libconfuse-dev (for ftdi-eeprom) (yum install libconfuse-devel)\nsudo apt-get install swig python-dev (for python bindings) (yum install swig python-devel)\nsudo apt-get install libboost-all-dev (for C++ binding and unit test) (yum install boost-devel)\n\n3) Clone the git repository\nmkdir libftdi\ncd libftdi\ngit clone git://developer.intra2net.com/libftdi\n\nIf you are building the release tar ball, just extract the source\ntar ball.\n\n4) Build the git source and install\ncd libftdi\nmkdir build\ncd build\ncmake  -DCMAKE_INSTALL_PREFIX=\"/usr\" ../\nmake\nsudo make install\n\n5) carry out some tests\ncd examples\n\nmcuee@Ubuntu1210VM:~/Desktop/build/libftdi/libftdi/build/examples$\n./find_all_pp  -v 0x0403 -p 0x6001\nFound devices ( VID: 0x403, PID: 0x6001 )\n------------------------------------------------\nFTDI (0x8730800): ftdi, usb serial converter, ftDEH51S (Open OK)\nFTDI (0x8730918): FTDI, FT232R USB UART, A8007Ub5 (Open OK)\n\nmcuee@Ubuntu1210VM:~/Desktop/build/libftdi/libftdi/build/examples$ ./eeprom\n2 FTDI devices found: Only Readout on EEPROM done. Use\nVID/PID/desc/serial to select device\nDecoded values of device 1:\nChip type 1 ftdi_eeprom_size: 128\n0x000: 00 00 03 04 01 60 00 04  a0 16 08 00 10 01 94 0a .....`.. ........\n0x010: 9e 2a c8 12 0a 03 66 00  74 00 64 00 69 00 2a 03 .*....f. t.d.i.*.\n0x020: 75 00 73 00 62 00 20 00  73 00 65 00 72 00 69 00 u.s.b. . s.e.r.i.\n0x030: 61 00 6c 00 20 00 63 00  6f 00 6e 00 76 00 65 00 a.l. .c. o.n.v.e.\n0x040: 72 00 74 00 65 00 72 00  12 03 66 00 74 00 44 00 r.t.e.r. ..f.t.D.\n0x050: 45 00 48 00 35 00 31 00  53 00 02 03 00 00 00 00 E.H.5.1. S.......\n0x060: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00 ........ ........\n0x070: 00 00 00 00 00 00 00 00  00 00 00 00 01 00 16 02 ........ ........\nVID:     0x0403\nPID:     0x6001\nRelease: 0x0400\nBus Powered:  44 mA USB Remote Wake Up\nManufacturer: ftdi\nProduct:      usb serial converter\nSerial:       ftDEH51S\nChecksum      : 0216\nEnable Remote Wake Up\nPNP: 1\nDecoded values of device 2:\nChip type 3 ftdi_eeprom_size: 128\n0x000: 00 40 03 04 01 60 00 00  a0 2d 08 00 00 00 98 0a .@...`.. .-......\n0x010: a2 20 c2 12 23 10 05 00  0a 03 46 00 54 00 44 00 . ..#... ..F.T.D.\n0x020: 49 00 20 03 46 00 54 00  32 00 33 00 32 00 52 00 I. .F.T. 2.3.2.R.\n0x030: 20 00 55 00 53 00 42 00  20 00 55 00 41 00 52 00  .U.S.B.  .U.A.R.\n0x040: 54 00 12 03 41 00 38 00  30 00 30 00 37 00 55 00 T...A.8. 0.0.7.U.\n0x050: 62 00 35 00 c9 bf 1c 80  00 00 00 00 00 00 00 00 b.5..... ........\n0x060: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00 ........ ........\n0x070: 00 00 00 00 00 00 00 00  00 00 00 00 00 00 0f 23 ........ .......#\n0x080: 2c 04 d3 fb 00 00 c9 bf  1c 80 42 00 00 00 00 00 ,....... ..B.....\n0x090: 00 00 00 00 00 00 00 00  38 41 32 52 4a 33 47 4f ........ 8A2RJ3GO\nVID:     0x0403\nPID:     0x6001\nRelease: 0x0000\nBus Powered:  90 mA USB Remote Wake Up\nManufacturer: FTDI\nProduct:      FT232R USB UART\nSerial:       A8007Ub5\nChecksum      : 230f\nInternal EEPROM\nEnable Remote Wake Up\nPNP: 1\nChannel A has Mode UART VCP\nC0 Function: TXLED\nC1 Function: RXLED\nC2 Function: TXDEN\nC3 Function: PWREN\nC4 Function: SLEEP\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libftdi1-1.5/README.mingw",
    "content": "* How to cross compile libftdi-1.x for Windows? *\n   1 - Prepare a pkg-config wrapper according to\n       https://autotools.io/pkgconfig/cross-compiling.html ,\n       additionally export PKG_CONFIG_ALLOW_SYSTEM_CFLAGS and\n       PKG_CONFIG_ALLOW_SYSTEM_LIBS.\n   2 - Write a CMake toolchain file according to\n       http://www.vtk.org/Wiki/CmakeMingw . Change the path to your future sysroot.\n   3 - Get libusb sources (either by cloning the git repo or by downloading a\n       tarball). Unpack, autogen.sh (when building from git), and configure like this:\n       ./configure --build=`./config.guess` --host=i686-w64-mingw32 \\\n               --prefix=/usr --with-sysroot=$HOME/i686-w64-mingw32-root/\n   4 - run\n       make install DESTDIR=$HOME/i686-w64-mingw32-root/\n   5 - go to libftdi-1.x source directory and run\n       cmake -DCMAKE_TOOLCHAIN_FILE=~/Toolchain-mingw.cmake \\\n             -DCMAKE_INSTALL_PREFIX=\"/usr\" \\\n             -DPKG_CONFIG_EXECUTABLE=`which i686-w64-mingw32-pkg-config`\n   6 - run\n       make install DESTDIR=$HOME/i686-w64-mingw32-root/\n\n* How to run libftdi 1.x under Windows *\n\nOn 26-Jan-2014, libusbx and libusb project were merged with the release\nof libusb-1.0.18 and now the project is called libusb.\n\nlibusb Windows backend will need to rely on a proper driver to run.\nPlease refer to the following wiki page for proper driver installation.\nhttps://github.com/libusb/libusb/wiki/Windows#wiki-How_to_use_libusb_on_Windows\n\nAs of 26-Jan-2014, libusb Windows backend supports WinUSB,\nlibusb0.sys and libusbk.sys driver. However, libusb's support of\nlibusb0.sys and libusbk.sys is considered to be less mature than\nWinUSB. Therefore, WinUSB driver installation using Zadig\nis recommended.\n\nTake note once you replace the original FTDI driver with WinUSB driver,\nyou can no longer use the functionality the original FTDI driver provides\n(eg. Virtual Serial Port or D2XX).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libiconv-1.17/AUTHORS",
    "content": "Bruno Haible <bruno@clisp.org>\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libiconv-1.17/COPYING",
    "content": "                    GNU GENERAL PUBLIC LICENSE\n                       Version 3, 29 June 2007\n\n Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The GNU General Public License is a free, copyleft license for\nsoftware and other kinds of works.\n\n  The licenses for most software and other practical works are designed\nto take away your freedom to share and change the works.  By contrast,\nthe GNU General Public License is intended to guarantee your freedom to\nshare and change all versions of a program--to make sure it remains free\nsoftware for all its users.  We, the Free Software Foundation, use the\nGNU General Public License for most of our software; it applies also to\nany other work released this way by its authors.  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  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libiconv-1.17/COPYING.LIB",
    "content": "                  GNU LESSER GENERAL PUBLIC LICENSE\n                       Version 2.1, February 1999\n\n Copyright (C) 1991, 1999 Free Software Foundation, Inc.\n 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n[This is the first released version of the Lesser GPL.  It also counts\n as the successor of the GNU Library Public License, version 2, hence\n the version number 2.1.]\n\n                            Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  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See the GNU\n    Lesser General Public License for more details.\n\n    You should have received a copy of the GNU Lesser General Public\n    License along with this library; if not, write to the Free Software\n    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n\nAlso add information on how to contact you by electronic and paper mail.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the library, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the\n  library `Frob' (a library for tweaking knobs) written by James Random Hacker.\n\n  <signature of Ty Coon>, 1 April 1990\n  Ty Coon, President of Vice\n\nThat's all there is to it!\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libiconv-1.17/DEPENDENCIES",
    "content": "The following packages should be installed before GNU libiconv is installed\n(runtime dependencies that are also build dependencies):\n\nNone.\n\n\nThe following packages should be installed when GNU libiconv is installed\n(runtime dependencies, but not build dependencies):\n\nNone.\n\n\nThe following should be installed when GNU libiconv is built, but are not\nneeded later, once it is installed (build dependencies, but not runtime\ndependencies):\n\n* A C runtime, compiler, linker, etc.\n  + Mandatory.\n    Either the platform's native 'cc', or GCC 3.1 or newer.\n  + GCC Homepage:\n    https://gcc.gnu.org/\n  + Download:\n    https://ftp.gnu.org/gnu/gcc/\n\n* A 'make' utility.\n  + Mandatory.\n    Either the platform's native 'make' (for in-tree builds only),\n    or GNU Make 3.79.1 or newer.\n  + GNU Make Homepage:\n    https://www.gnu.org/software/make/\n  + Download:\n    https://ftp.gnu.org/gnu/make/\n\n* A shell\n  + Mandatory.\n    Either the platform's native 'sh', or Bash.\n  + Homepage:\n    https://www.gnu.org/software/bash/\n  + Download:\n    https://ftp.gnu.org/gnu/bash/\n\n* Core POSIX utilities, including:\n    [ basename cat chgrp chmod chown cp dd echo expand expr\n    false hostname install kill ln ls md5sum mkdir mkfifo\n    mknod mv printenv pwd rm rmdir sleep sort tee test touch\n    true uname\n  + Mandatory.\n    Either the platform's native utilities, or GNU coreutils.\n  + Homepage:\n    https://www.gnu.org/software/coreutils/\n  + Download:\n    https://ftp.gnu.org/gnu/coreutils/\n\n* The comparison utilities 'cmp' and 'diff'.\n  + Mandatory.\n    Either the platform's native utilities, or GNU diffutils.\n  + Homepage:\n    https://www.gnu.org/software/diffutils/\n  + Download:\n    https://ftp.gnu.org/gnu/diffutils/\n\n* Grep.\n  + Mandatory.\n    Either the platform's native grep, or GNU grep.\n  + Homepage:\n    https://www.gnu.org/software/grep/\n  + Download:\n    https://ftp.gnu.org/gnu/grep/\n\n* Awk.\n  + Mandatory.\n    Either the platform's native awk, mawk, or nawk, or GNU awk.\n  + Homepage:\n    https://www.gnu.org/software/gawk/\n  + Download:\n    https://ftp.gnu.org/gnu/gawk/\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libiconv-1.17/NEWS",
    "content": "New in 1.17:\n* The libiconv library is now licensed under the LGPL version 2.1, instead of\n  the LGPL version 2.0. The iconv program continues to be licensed under GPL\n  version 3.\n* Added converters for many single-byte EBCDIC encodings:\n  IBM-{037,273,277,278,280,282,284,285,297,423,424,425,500,838,870,871,875},\n  IBM-{880,905,924,1025,1026,1047,1097,1112,1122,1123,1130,1132,1137,1140},\n  IBM-{1141,1142,1143,1144,1145,1146,1147,1148,1149,1153,1154,1155,1156,1157},\n  IBM-{1158,1160,1164,1165,1166,4971,12712,16804}.\n  They are available through the configure option '--enable-extra-encodings'.\n\nNew in 1.16:\n* The preloadable library has been removed.\n\nNew in 1.15:\n* The UTF-8 converter now rejects surrogates and out-of-range code points.\n* Added ISO-2022-JP-MS converter.\n* Updated the CP1255 converter to map one more character.\n* The functions now support strings longer than 2 GB.\n\nNew in 1.14:\n* The 'iconv' program now produces its output as soon as it can. It no longer\n  unnecessarily waits for more input.\n* Updated the GB18030 converter to map 25 characters to code points that have\n  been to Unicode since 2000, rather than to code points in the Private Use\n  Area.\n* Updated the BIG5-HKSCS converter. The old BIG5-HKSCS converter is renamed to\n  BIG5-HKSCS:2004. A new converter BIG5-HKSCS:2008 is added. BIG5-HKSCS is now\n  an alias for BIG5-HKSCS:2008.\n* Fixed a bug in the conversion to wchar_t.\n* Fixed a small bug in the CP1258 converter.\n\nNew in 1.13:\n* The library and the iconv program now understand platform dependent aliases,\n  for better compatibility with the platform's own iconv_open function.\n  Examples: \"646\" on Solaris, \"iso88591\" on HP-UX, \"IBM-1252\" on AIX.\n* For stateful encodings, when the input ends with a shift sequence followed\n  by invalid input, the iconv function now increments the input pointer past\n  the shift sequence before returning (size_t)(-1) with errno = EILSEQ. This\n  is also like GNU libc's iconv() behaves.\n* The library exports a new function iconv_open_into() that stores the\n  conversion descriptor in pre-allocated memory, rather than allocating fresh\n  memory for it.\n* Added CP1131 converter.\n\nNew in 1.12:\n* The iconv program is now licensed under the GPL version 3, instead of the\n  GPL version 2. The libiconv library continues to be licensed under LGPL.\n* Added RK1048 converter.\n* On AIX, an existing system libiconv no longer causes setlocale() to fail.\n* Upgraded EUC-KR, JOHAB to include the Korean postal code sign.\n\nNew in 1.11:\n* The iconv program has new options --unicode-subst, --byte-subst,\n  --widechar-subst that allow to specify substitutions for characters that\n  cannot be converted.\n* The iconv program now understands long options:\n    long option    equivalent to\n    --from-code    -f\n    --to-code      -t\n    --list         -l\n    --silent       -s\n* The CP936 converter is now different from the GBK converter: it has changed\n  to include the Euro sign and private area characters. CP936 is no longer an\n  alias of GBK.\n* Updated GB18030 converter to include all private area characters.\n* Updated CP950 converter to include the Euro sign and private area characters.\n* Updated CP949 converter to include private area characters.\n* Updated the BIG5-HKSCS converter. The old BIG5-HKSCS converter is renamed to\n  BIG5-HKSCS:1999 and updated to Unicode 4. New converters BIG5-HKSCS:2001 and\n  BIG5-HKSCS:2004 are added. BIG5-HKSCS is now an alias for BIG5-HKSCS:2004.\n* Added a few irreversible mappings to the CP932 converter.\n* Tidy up the list of symbols exported from libiconv (assumes gcc >= 4.0).\n\nNew in 1.10:\n* Added ISO-8859-11 converter.\n* Updated the ISO-8859-7 converter.\n* Added ATARIST converter, available through --enable-extra-encodings.\n* Added BIG5-2003 converter (experimental), available through\n  --enable-extra-encodings.\n* Updated EUC-TW converter to include the Euro sign.\n* The preloadable library has been renamed from libiconv_plug.so to\n  preloadable_libiconv.so.\n* Portability to mingw.\n\nNew in 1.9:\n* Many more transliterations.\n* New configuration option --enable-relocatable.  See the INSTALL.generic file\n  for details.\n\nNew in 1.8:\n* The iconv program has new options -l, -c, -s.\n* The iconv program is internationalized.\n* Added C99 converter.\n* Added KOI8-T converter.\n* New configuration option --enable-extra-encodings that enables a bunch of\n  additional encodings; see the README for details.\n* Updated the ISO-8859-16 converter.\n* Upgraded BIG5-HKSCS, EUC-TW, ISO-2022-CN, ISO-2022-CN-EXT converters to\n  Unicode 3.2.\n* Upgraded EUC-KR, CP949, JOHAB converters to include the Euro sign.\n* Changed the ARMSCII-8 converter.\n* Extended the EUC-JP encoder so that YEN SIGN characters don't cause failures\n  in Shift_JIS to EUC-JP conversion.\n* The JAVA converter now handles characters outside the Unicode BMP correctly.\n* Fixed a bug in the CP1255, CP1258, TCVN decoders: The base characters of\n  combining characters could be dropped at the end of the conversion buffer.\n* Fixed a bug in the transliteration that could lead to excessive memory\n  allocations in libintl when transliteration was needed.\n* Portability to BSD/OS and SCO 3.2.5.\n\nNew in 1.7:\n* Added UTF-32, UTF-32BE, UTF-32LE converters.\n* Changed CP1255, CP1258 and TCVN converters to handle combining characters.\n* Changed EUC-JP, SHIFT_JIS, CP932, ISO-2022-JP, ISO-2022-JP-2, ISO-2022-JP-1\n  converters to use fullwidth Yen sign instead of halfwidth Yen sign, and\n  fullwidth tilde instead of halfwidth tilde.\n* Upgraded EUC-TW, ISO-2022-CN, ISO-2022-CN-EXT converters to Unicode 3.1.\n* Changed the GB18030 converter to not reject unassigned and private-use\n  Unicode characters.\n* Fixed a bug in the byte order mark treatment of the UCS-4 decoder.\n* The manual pages are now distributed also in HTML format.\n\nNew in 1.6:\n* The iconv program's -f and -t options are now optional.\n* Many more transliterations.\n* Added CP862 converter.\n* Changed the GB18030 converter.\n* Portability to DOS with DJGPP.\n\nNew in 1.5:\n* Added an iconv(1) program.\n* New locale dependent encodings \"char\", \"wchar_t\".\n* Transliteration is now off by default. Use a //TRANSLIT suffix to enable it.\n* The JOHAB encoding is documented again.\n* Changed a few mappings in the CP950 converter.\n\nNew in 1.4:\n* Added GB18030, BIG5HKSCS converters.\n* Portability to OS/2 with emx+gcc.\n\nNew in 1.3:\n* Added UCS-2BE, UCS-2LE, UCS-4BE, UCS-4LE converters.\n* Fixed the definition of EILSEQ on SunOS4.\n* Fixed a build problem on OSF/1.\n* Support for building as a shared library on Woe32.\n\nNew in 1.2:\n* Added UTF-16BE and UTF-16LE converters.\n* Changed the UTF-16 encoder.\n* Fixed the treatment of tab characters in the UTF-7 converter.\n* Fixed an internal error when output buffer was not large enough.\n\nNew in 1.1:\n* Added ISO-8859-16 converter.\n* Added CP932 converter, a variant of SHIFT_JIS.\n* Added CP949 converter, a variant of EUC-KR.\n* Improved the ISO-2022-CN-EXT converter: It now covers the ISO-IR-165 range.\n* Updated the ISO-8859-8 conversion table.\n* The JOHAB encoding is deprecated and not documented any more.\n* Fixed two build problems: 1. \"make -n check\" failed. 2. When libiconv was\n  already installed, \"make\" failed.\n\nNew in 1.0:\n* Added transliteration facilities.\n* Added a test suite.\n* Fixed the iconv(3) manual page and function: the return value was not\n  described correctly.\n* Fixed a bug in the CP1258 decoder: invalid bytes now yield EILSEQ instead of\n  U+FFFD.\n* Fixed a bug in the Georgian-PS encoder: accept U+00E6.\n* Fixed a bug in the EUC-JP encoder: reject 0x8E5C and 0x8E7E.\n* Fixed a bug in the KSC5601 and JOHAB converters: they recognized some Hangul\n  characters at some invalid code positions.\n* Fixed a bug in the EUC-TW decoder; it was severely broken.\n* Fixed a bug in the CP950 converter: it recognized a dubious BIG5 range.\n\nNew in 0.3:\n* Reduced the size of the tables needed for the JOHAB converter.\n* Portability to Woe32.\n\nNew in 0.2:\n* Added KOI8-RU, CP850, CP866, CP874, CP950, ISO-2022-CN-EXT, GBK and\n  ISO-2022-JP-1 converters.\n* Added MACINTOSH as an alias for MAC-ROMAN.\n* Added ASMO-708 as an alias for ISO-8859-6.\n* Added ELOT_928 as an alias for ISO-8859-7.\n* Improved the EUC-TW converter: Treat CNS 11643 plane 3.\n* Improved the ISO-2022-KR and EUC-KR converters: Hangul characters are\n  decomposed into Jamo when needed.\n* Improved the CP932 converter.\n* Updated the CP1133, MULELAO-1 and ARMSCII-8 mappings.\n* The EUC-JP and SHIFT_JIS converters now cover the user-defined range.\n* Fixed a possible buffer overrun in the JOHAB converter.\n* Fixed a bug in the UTF-7, ISO-2022-*, HZ decoders: a shift sequence a the\n  end of the input no longer gives an error.\n* The HZ encoder now always terminates its output in the ASCII state.\n* Use a perfect hash table for looking up the aliases.\n\nNew in 0.1:\n* Portability to Linux/glibc-2.0.x, Linux/libc5, OSF/1, FreeBSD.\n* Fixed a bug in the EUC-JP decoder. Extended the ISO-2022-JP-2 converter.\n* Made TIS-620 mapping consistent with glibc-2.1.\n\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libiconv-1.17/README",
    "content": "            GNU LIBICONV - character set conversion library\n\nThis library provides an iconv() implementation, for use on systems which\ndon't have one, or whose implementation cannot convert from/to Unicode.\n\nIt provides support for the encodings:\n\n    European languages\n        ASCII, ISO-8859-{1,2,3,4,5,7,9,10,13,14,15,16},\n        KOI8-R, KOI8-U, KOI8-RU,\n        CP{1250,1251,1252,1253,1254,1257}, CP{850,866,1131},\n        Mac{Roman,CentralEurope,Iceland,Croatian,Romania},\n        Mac{Cyrillic,Ukraine,Greek,Turkish},\n        Macintosh\n    Semitic languages\n        ISO-8859-{6,8}, CP{1255,1256}, CP862, Mac{Hebrew,Arabic}\n    Japanese\n        EUC-JP, SHIFT_JIS, CP932, ISO-2022-JP, ISO-2022-JP-2, ISO-2022-JP-1,\n        ISO-2022-JP-MS\n    Chinese\n        EUC-CN, HZ, GBK, CP936, GB18030, EUC-TW, BIG5, CP950, BIG5-HKSCS,\n        BIG5-HKSCS:2004, BIG5-HKSCS:2001, BIG5-HKSCS:1999, ISO-2022-CN,\n        ISO-2022-CN-EXT\n    Korean\n        EUC-KR, CP949, ISO-2022-KR, JOHAB\n    Armenian\n        ARMSCII-8\n    Georgian\n        Georgian-Academy, Georgian-PS\n    Tajik\n        KOI8-T\n    Kazakh\n        PT154, RK1048\n    Thai\n        ISO-8859-11, TIS-620, CP874, MacThai\n    Laotian\n        MuleLao-1, CP1133\n    Vietnamese\n        VISCII, TCVN, CP1258\n    Platform specifics\n        HP-ROMAN8, NEXTSTEP\n    Full Unicode\n        UTF-8\n        UCS-2, UCS-2BE, UCS-2LE\n        UCS-4, UCS-4BE, UCS-4LE\n        UTF-16, UTF-16BE, UTF-16LE\n        UTF-32, UTF-32BE, UTF-32LE\n        UTF-7\n        C99, JAVA\n    Full Unicode, in terms of 'uint16_t' or 'uint32_t'\n        (with machine dependent endianness and alignment)\n        UCS-2-INTERNAL, UCS-4-INTERNAL\n    Locale dependent, in terms of 'char' or 'wchar_t'\n        (with machine dependent endianness and alignment, and with OS and\n        locale dependent semantics)\n        char, wchar_t\n        The empty encoding name \"\" is equivalent to \"char\": it denotes the\n        locale dependent character encoding.\n\nWhen configured with the option --enable-extra-encodings, it also provides\nsupport for a few extra encodings:\n\n    European languages\n        CP{437,737,775,852,853,855,857,858,860,861,863,865,869,1125}\n    Semitic languages\n        CP864\n    Japanese\n        EUC-JISX0213, Shift_JISX0213, ISO-2022-JP-3\n    Chinese\n        BIG5-2003 (experimental)\n    Turkmen\n        TDS565\n    Platform specifics\n        ATARIST, RISCOS-LATIN1\n    EBCDIC compatible (not ASCII compatible, very rarely used)\n        European languages\n            IBM-{037,273,277,278,280,282,284,285,297,423,500,870,871,875,880},\n            IBM-{905,924,1025,1026,1047,1112,1122,1123,1140,1141,1142,1143},\n            IBM-{1144,1145,1146,1147,1148,1149,1153,1154,1155,1156,1157,1158},\n            IBM-{1165,1166,4971}\n        Semitic languages\n            IBM-{424,425,12712,16804}\n        Persian\n            IBM-1097\n        Thai\n            IBM-{838,1160}\n        Laotian\n            IBM-1132\n        Vietnamese\n            IBM-{1130,1164}\n        Indic languages\n            IBM-1137\n\nIt can convert from any of these encodings to any other, through Unicode\nconversion.\n\nIt has also some limited support for transliteration, i.e. when a character\ncannot be represented in the target character set, it can be approximated\nthrough one or several similarly looking characters. Transliteration is\nactivated when \"//TRANSLIT\" is appended to the target encoding name.\n\nlibiconv is for you if your application needs to support multiple character\nencodings, but that support lacks from your system.\n\n\nInstallation\n------------\n\nAs usual for GNU packages:\n\n    $ ./configure --prefix=[[PREFIX]]     where [[PREFIX]] is e.g. $HOME/local\n    $ make\n    $ make install\n\nAfter installing GNU libiconv for the first time, it is recommended to\nrecompile and reinstall GNU gettext, so that it can take advantage of\nlibiconv.\n\nOn systems other than GNU/Linux, the iconv program will be internationalized\nonly if GNU gettext has been built and installed before GNU libiconv. This\nmeans that the first time GNU libiconv is installed, we have a circular\ndependency between the GNU libiconv and GNU gettext packages, which can be\nresolved by building and installing either\n  - first libiconv, then gettext, then libiconv again,\nor (on systems supporting shared libraries, excluding AIX)\n  - first gettext, then libiconv, then gettext again.\nRecall that before building a package for the second time, you need to erase\nthe traces of the first build by running \"make distclean\".\n\nThis library installs:\n  - a library 'libiconv.so',\n  - a header file '<iconv.h>'.\n\nTo use it, simply #include <iconv.h> and use the functions.\n\nTo use it in a package that uses GNU autoconf and GNU automake:\n  - Use gnulib-tool to import the Gnulib module 'iconv'. It consists\n    of a couple of *.m4 files (iconv.m4 and its dependencies) and a\n    file 'build-aux/config.rpath'.\n  - Add to the link command line of libraries and executables that use\n    the functions the placeholder @LIBICONV@ (or, if using libtool for\n    the link, @LTLIBICONV@). In Makefile.am files, the right place for\n    these additions are the *_LDADD variables.\n\n\nCopyright\n---------\n\nThe libiconv and libcharset _libraries_ and their header files are under LGPL,\nsee file COPYING.LIB.\n\nThe iconv _program_ and the documentation are under GPL, see file COPYING.\n\n\nDownload\n--------\n\n    https://ftp.gnu.org/gnu/libiconv/libiconv-1.17.tar.gz\n\nHomepage\n--------\n\n    https://www.gnu.org/software/libiconv/\n\nBug reports\n-----------\n\nReport bugs\n  - in the bug tracker at <https://savannah.gnu.org/projects/libiconv>\n  - or by email to <bug-gnu-libiconv@gnu.org>.\n\n\nBruno Haible <bruno@clisp.org>\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libiconv-1.17/THANKS",
    "content": "          Thanks to                               for\n\nEdmund Grimley Evans  <edmundo@rano.org>      bug reports\n\nTaro Muraoka  <koron@tka.att.ne.jp>           Woe32 DLL support\n\nAkira Hatakeyama  <akira@sra.co.jp>           OS/2 support\n\nJuan Manuel Guerrero  <st001906@hrz1.hrz.tu-darmstadt.de>\n                                              DOS/DJGPP support\n\nHironori Sakamoto  <hsaka@mth.biglobe.ne.jp>  advice on EUC-JP and JISX0213\n\nKen Lunde  <lunde@adobe.com>                  detailed information about GB18030\n\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libtool-2.4.7/AUTHORS",
    "content": "* GNU Libtool was conceived, designed and implemented by:\n\n    Gordon Matzigkeit\t\tgord@gnu.org\n\n* GNU Libtool's Dynamic Loader library (libltdl) was conceived,\n  designed and implemented by:\n\n    Thomas Tanner\t\ttanner@ffii.org\n\n* GNU Libtool and libltdl have previously been maintained, enhanced,\n  ported and otherwise advanced by:\n\n    Alexandre Oliva\t\toliva@dcc.unicamp.br\n    Ossama Othman\t\tossama@debian.org\n    Robert Boehne\t\trboehne@ricardo-us.com\n    Scott James Remnant\t\tscott@netsplit.com\n    Peter O'Gorman\t\tpeter@pogma.com\n    Ralf Wildenhues\t\tRalf.Wildenhues@gmx.de\n    Gary V. Vaughan\t\tgary@vaughan.pe\n    Bob Friesenhahn\t\tbfriesen@simple.dallas.tx.us\n    Peter Rosin\t\t\tpeda@lysator.liu.se\n    Noah Misch\t\t\tnoah@cs.caltech.edu\n    Charles Wilson\t\tlibtool@cwilson.fastmail.fm\n    Brooks Moses\t\tbmoses@google.com\n\n* GNU Libtool is currently being cajoled, bullied,\n  rewritten and otherwise dragged into the future by:\n\n    Alex Ameen    alex.ameen.tx@gmail.com\n-- \n  Copyright (C) 1996, 1998-2019, 2021-2022 Free Software Foundation,\n  Inc.\n\n  This file is part of GNU Libtool.\n\nGNU Libtool is free software; you can redistribute it and/or\nmodify it under the terms of the GNU General Public License as\npublished by the Free Software Foundation; either version 2 of\nthe License, or (at your option) any later version.\n\nGNU Libtool is distributed in the hope that it will be useful,\nbut WITHOUT ANY WARRANTY; without even the implied warranty of\nMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\nGNU General Public License for more details.\n\nYou should have received a copy of the GNU General Public License\nalong with GNU Libtool; see the file COPYING.  If not, a copy\ncan be downloaded from  http://www.gnu.org/licenses/gpl.html,\nor obtained by writing to the Free Software Foundation, Inc.,\n51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libtool-2.4.7/COPYING",
    "content": "                    GNU GENERAL PUBLIC LICENSE\n                       Version 2, June 1991\n\n Copyright (C) 1989, 1991 Free Software Foundation, Inc.,\n 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  By contrast, the GNU General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users.  This\nGeneral Public License applies to most of the Free Software\nFoundation's software and to any other program whose authors commit to\nusing it.  (Some other Free Software Foundation software is covered by\nthe GNU Lesser General Public License instead.)  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthis service if you wish), that you receive source code or can get it\nif you want it, that you can change the software or use pieces of it\nin new free programs; and that you know you can do these things.\n\n  To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have.  You must make sure that they, too, receive or can get the\nsource code.  And you must show them these terms so they know their\nrights.\n\n  We protect your rights with two steps: (1) copyright the software, and\n(2) offer you this license which gives you legal permission to copy,\ndistribute and/or modify the software.\n\n  Also, for each author's protection and ours, we want to make certain\nthat everyone understands that there is no warranty for this free\nsoftware.  If the software is modified by someone else and passed on, we\nwant its recipients to know that what they have is not the original, so\nthat any problems introduced by others will not reflect on the original\nauthors' reputations.\n\n  Finally, any free program is threatened constantly by software\npatents.  We wish to avoid the danger that redistributors of a free\nprogram will individually obtain patent licenses, in effect making the\nprogram proprietary.  To prevent this, we have made it clear that any\npatent must be licensed for everyone's free use or not licensed at all.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n                    GNU GENERAL PUBLIC LICENSE\n   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n  0. This License applies to any program or other work which contains\na notice placed by the copyright holder saying it may be distributed\nunder the terms of this General Public License.  The \"Program\", below,\nrefers to any such program or work, and a \"work based on the Program\"\nmeans either the Program or any derivative work under copyright law:\nthat is to say, a work containing the Program or a portion of it,\neither verbatim or with modifications and/or translated into another\nlanguage.  (Hereinafter, translation is included without limitation in\nthe term \"modification\".)  Each licensee is addressed as \"you\".\n\nActivities other than copying, distribution and modification are not\ncovered by this License; they are outside its scope.  The act of\nrunning the Program is not restricted, and the output from the Program\nis covered only if its contents constitute a work based on the\nProgram (independent of having been made by running the Program).\nWhether that is true depends on what the Program does.\n\n  1. You may copy and distribute verbatim copies of the Program's\nsource code as you receive it, in any medium, provided that you\nconspicuously and appropriately publish on each copy an appropriate\ncopyright notice and disclaimer of warranty; keep intact all the\nnotices that refer to this License and to the absence of any warranty;\nand give any other recipients of the Program a copy of this License\nalong with the Program.\n\nYou may charge a fee for the physical act of transferring a copy, and\nyou may at your option offer warranty protection in exchange for a fee.\n\n  2. You may modify your copy or copies of the Program or any portion\nof it, thus forming a work based on the Program, and copy and\ndistribute such modifications or work under the terms of Section 1\nabove, provided that you also meet all of these conditions:\n\n    a) You must cause the modified files to carry prominent notices\n    stating that you changed the files and the date of any change.\n\n    b) You must cause any work that you distribute or publish, that in\n    whole or in part contains or is derived from the Program or any\n    part thereof, to be licensed as a whole at no charge to all third\n    parties under the terms of this License.\n\n    c) If the modified program normally reads commands interactively\n    when run, you must cause it, when started running for such\n    interactive use in the most ordinary way, to print or display an\n    announcement including an appropriate copyright notice and a\n    notice that there is no warranty (or else, saying that you provide\n    a warranty) and that users may redistribute the program under\n    these conditions, and telling the user how to view a copy of this\n    License.  (Exception: if the Program itself is interactive but\n    does not normally print such an announcement, your work based on\n    the Program is not required to print an announcement.)\n\nThese requirements apply to the modified work as a whole.  If\nidentifiable sections of that work are not derived from the Program,\nand can be reasonably considered independent and separate works in\nthemselves, then this License, and its terms, do not apply to those\nsections when you distribute them as separate works.  But when you\ndistribute the same sections as part of a whole which is a work based\non the Program, the distribution of the whole must be on the terms of\nthis License, whose permissions for other licensees extend to the\nentire whole, and thus to each and every part regardless of who wrote it.\n\nThus, it is not the intent of this section to claim rights or contest\nyour rights to work written entirely by you; rather, the intent is to\nexercise the right to control the distribution of derivative or\ncollective works based on the Program.\n\nIn addition, mere aggregation of another work not based on the Program\nwith the Program (or with a work based on the Program) on a volume of\na storage or distribution medium does not bring the other work under\nthe scope of this License.\n\n  3. You may copy and distribute the Program (or a work based on it,\nunder Section 2) in object code or executable form under the terms of\nSections 1 and 2 above provided that you also do one of the following:\n\n    a) Accompany it with the complete corresponding machine-readable\n    source code, which must be distributed under the terms of Sections\n    1 and 2 above on a medium customarily used for software interchange; or,\n\n    b) Accompany it with a written offer, valid for at least three\n    years, to give any third party, for a charge no more than your\n    cost of physically performing source distribution, a complete\n    machine-readable copy of the corresponding source code, to be\n    distributed under the terms of Sections 1 and 2 above on a medium\n    customarily used for software interchange; or,\n\n    c) Accompany it with the information you received as to the offer\n    to distribute corresponding source code.  (This alternative is\n    allowed only for noncommercial distribution and only if you\n    received the program in object code or executable form with such\n    an offer, in accord with Subsection b above.)\n\nThe source code for a work means the preferred form of the work for\nmaking modifications to it.  For an executable work, complete source\ncode means all the source code for all modules it contains, plus any\nassociated interface definition files, plus the scripts used to\ncontrol compilation and installation of the executable.  However, as a\nspecial exception, the source code distributed need not include\nanything that is normally distributed (in either source or binary\nform) with the major components (compiler, kernel, and so on) of the\noperating system on which the executable runs, unless that component\nitself accompanies the executable.\n\nIf distribution of executable or object code is made by offering\naccess to copy from a designated place, then offering equivalent\naccess to copy the source code from the same place counts as\ndistribution of the source code, even though third parties are not\ncompelled to copy the source along with the object code.\n\n  4. You may not copy, modify, sublicense, or distribute the Program\nexcept as expressly provided under this License.  Any attempt\notherwise to copy, modify, sublicense or distribute the Program is\nvoid, and will automatically terminate your rights under this License.\nHowever, parties who have received copies, or rights, from you under\nthis License will not have their licenses terminated so long as such\nparties remain in full compliance.\n\n  5. You are not required to accept this License, since you have not\nsigned it.  However, nothing else grants you permission to modify or\ndistribute the Program or its derivative works.  These actions are\nprohibited by law if you do not accept this License.  Therefore, by\nmodifying or distributing the Program (or any work based on the\nProgram), you indicate your acceptance of this License to do so, and\nall its terms and conditions for copying, distributing or modifying\nthe Program or works based on it.\n\n  6. Each time you redistribute the Program (or any work based on the\nProgram), the recipient automatically receives a license from the\noriginal licensor to copy, distribute or modify the Program subject to\nthese terms and conditions.  You may not impose any further\nrestrictions on the recipients' exercise of the rights granted herein.\nYou are not responsible for enforcing compliance by third parties to\nthis License.\n\n  7. If, as a consequence of a court judgment or allegation of patent\ninfringement or for any other reason (not limited to patent issues),\nconditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot\ndistribute so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you\nmay not distribute the Program at all.  For example, if a patent\nlicense would not permit royalty-free redistribution of the Program by\nall those who receive copies directly or indirectly through you, then\nthe only way you could satisfy both it and this License would be to\nrefrain entirely from distribution of the Program.\n\nIf any portion of this section is held invalid or unenforceable under\nany particular circumstance, the balance of the section is intended to\napply and the section as a whole is intended to apply in other\ncircumstances.\n\nIt is not the purpose of this section to induce you to infringe any\npatents or other property right claims or to contest validity of any\nsuch claims; this section has the sole purpose of protecting the\nintegrity of the free software distribution system, which is\nimplemented by public license practices.  Many people have made\ngenerous contributions to the wide range of software distributed\nthrough that system in reliance on consistent application of that\nsystem; it is up to the author/donor to decide if he or she is willing\nto distribute software through any other system and a licensee cannot\nimpose that choice.\n\nThis section is intended to make thoroughly clear what is believed to\nbe a consequence of the rest of this License.\n\n  8. If the distribution and/or use of the Program is restricted in\ncertain countries either by patents or by copyrighted interfaces, the\noriginal copyright holder who places the Program under this License\nmay add an explicit geographical distribution limitation excluding\nthose countries, so that distribution is permitted only in or among\ncountries not thus excluded.  In such case, this License incorporates\nthe limitation as if written in the body of this License.\n\n  9. The Free Software Foundation may publish revised and/or new versions\nof the General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\nEach version is given a distinguishing version number.  If the Program\nspecifies a version number of this License which applies to it and \"any\nlater version\", you have the option of following the terms and conditions\neither of that version or of any later version published by the Free\nSoftware Foundation.  If the Program does not specify a version number of\nthis License, you may choose any version ever published by the Free Software\nFoundation.\n\n  10. If you wish to incorporate parts of the Program into other free\nprograms whose distribution conditions are different, write to the author\nto ask for permission.  For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this.  Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n                            NO WARRANTY\n\n  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\nREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\nINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\nOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\nYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\nPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGES.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software; you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation; either version 2 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License along\n    with this program; if not, write to the Free Software Foundation, Inc.,\n    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n\nAlso add information on how to contact you by electronic and paper mail.\n\nIf the program is interactive, make it output a short notice like this\nwhen it starts in an interactive mode:\n\n    Gnomovision version 69, Copyright (C) year name of author\n    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, the commands you use may\nbe called something other than `show w' and `show c'; they could even be\nmouse-clicks or menu items--whatever suits your program.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the program, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the program\n  `Gnomovision' (which makes passes at compilers) written by James Hacker.\n\n  <signature of Ty Coon>, 1 April 1989\n  Ty Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into\nproprietary programs.  If your program is a subroutine library, you may\nconsider it more useful to permit linking proprietary applications with the\nlibrary.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libtool-2.4.7/NEWS",
    "content": "NEWS - list of user-visible changes between releases of GNU Libtool\n\n* Noteworthy changes in release 2.4.7 (2022-03-16) [stable]\n\n** New features:\n\n  - Libtool script now supports (configure-time and runtime) ARFLAGS\n    variable, which obsoletes AR_FLAGS.  This is due to naming conventions\n    among other *FLAGS and to be consistent with Automake's ARFLAGS.\n\n  - Gnulib testsuite is enabled and run during 'make check'.\n\n  - Support the Windows version of the Intel C Compiler (icl) in\n    libtool script.\n\n  - Pass '-fsanitize=*' flags for GCC and LLVM, and '-specs=*' for GCC\n    to linker.\n\n  - Pass '-Xassembler=*' and '-Wa,*' flag to compilers and linkers.\n\n  - The variable 'FILECMD' with default value of '/usr/bin/file' was used to\n    replace existing hard coded references to '/usr/bin/file'.\n\n  - Add MidnightBSD support.\n\n** Important incompatible changes:\n\n  - Libtool changed ARFLAGS/AR_FLAGS default from 'cru' to 'cr'.\n\n  - Do not pass '-pthread' to Solaris linker.\n\n  - 'libtool' and 'libtoolize' scripts now use '#! /usr/bin/env sh' shebang.\n    Previously '#! /bin/sh' was used, which presents challenges for\n    containerized environments.\n\n** Bug fixes:\n\n  - Fix significant slowdown of libtoolize for certain projects (regression\n    introduced in 2.4.3 release) caused by infinite m4 macro recursion.\n\n  - Mitigate the slowdown of libtool script (introduced in v2.4.3) caused by\n    increased number of calls to '$SED $sed_quote_subst' (bug#20006).\n\n  - Properly parse and export TLS symbols on AIX.\n\n  - Various bug fixes surrounding use of 'sed'.\n\n  - Darwin systems set proper \"allow undefined\" flag on OSX 11, and\n    PowerPC 10.5.\n\n  - Removed some deprecated tests related to 'Makefile.inc' files.\n\n* Noteworthy changes in release 2.4.6 (2015-02-15) [stable]\n\n** New features:\n\n  - LT_SYS_LIBRARY_PATH can be set in config.site, or at configure time\n    and persists correctly in the generated libtool script.\n\n** Bug fixes:\n\n  - Fix a race condition in ltdl dryrun test that would cause spurious\n    random failures of that test.\n\n  - LT_SYS_DLSEARCH_PATH is munged correctly.\n\n\n* Noteworthy changes in release 2.4.5 (2015-01-19) [stable]\n\n** New features:\n\n  - Libtoolize searches for the best available M4 on the user PATH at\n    runtime, rather than settling for the first one found.\n\n  - Support munging sys_lib_dlsearch_path_spec with LT_SYS_LIBRARY_PATH\n    environment variable.\n\n** Bug fixes:\n\n  - Bail out at configure time if the installed M4 is not sufficient\n    for the purposes of libtoolize.\n\n  - freebsd-elf library versioning was upgraded incorrectly in 2.4.4,\n    but now works properly again.\n\n  - Fix a 2.4.4 regression so that libltdl subprojects do not warn\n    about missing libltdl/libltdl directory as in prior releases.\n\n  - When using Sun C++ on Solaris or GNU/Linux we used to set libtool's\n    postdeps permanently, based on the contents of $CXX and $CXXFLAGS at\n    configure time, which was brittle and error-prone.  Now, we no\n    longer check for a SunCC ABI at configure time, but augment the\n    postdeps at libtool time based on the current invocation flags on\n    each call.\n\n** Changes in supported systems or compilers:\n\n  - /usr/local prefixed rpaths are now added to the link-line on\n    ia64-hp-hpux*, because the default system runtime loader path does\n    not contain them.\n\n  - Previously, when using Sun C++ on Solaris or GNU/Linux, `-Cstd -Crun`\n    flags were added to $postdeps unless CXX or CXXFLAGS contained\n    `-library=stlport4`.  Newer releases have added other compiler flags\n    that are also incompatible with `-Cstd -Crun`, so now we don't add\n    them if any of `-std=c++[0-9][0-9]`, `-library=stdcxx4` or\n    `-compat=g` were found in CXX or CXXFLAGS when the Sun C++ compiler\n    is detected.\n\n\n* Noteworthy changes in release 2.4.4 (2014-11-29) [stable]\n\n** New features:\n\n  - Libltdl maintains its own fork of argz, with macros and files in\n    the LT_ and lt__ namespaces (resp.) where they cannot clash with\n    client projects' use of gnulib argz.\n\n** Bug fixes:\n\n  - Installation of 'libtoolize' once again obeys '--program-prefix',\n    '--program-suffix' and '--program-transform-name' configure options.\n\n  - `libtoolize` doesn't remove any files that it can't reinstall,\n    including old versions of the snippet directory, and gnulib's\n    version of the argz module and supporting files.\n\n  - LT_FUNC_DLYSM_USCORE now works correctly on systems that don't\n    support self dlopen()ing.\n\n** Important incompatible changes:\n\n  - LT_LIB_DLLOAD no longer prepends -ldl or -ldld to LIBS, causing\n    duplicate occurrences in libltdl link lines.  If you need to\n    add a library for dlopen() or shl_load() in your Makefile, then\n    use $(LIBADD_DLOPEN) or $(LIBADD_SHL_LOAD) respectively.  If you\n    are using libltdl, this all happens automatically, and the only\n    difference you'll see is no more duplicated library names in the\n    verbose link line.\n\n** Changes in supported systems or compilers:\n\n  - Preliminary support for tcc on linux*.  Although it already worked\n    sometimes in previous releases, making sure to set LD correctly now\n    avoids mis-matching GNU ld with tcc:\n\n       ./configure CC=tcc LD=tcc\n\n  - Added -os2dllname option to work around 8 character base name\n    limit on OS/2.  The option has no effect on other systems.\n\n  - Support for DLL versioning, -export-symbols and -export-symbols-regex\n    on OS/2.\n\n  - Support filename-based shared library versioning on AIX. See manual\n    for details.\n\n\n* Noteworthy changes in release 2.4.3 (2014-10-27) [stable]\n\n** New features:\n\n  - Moved to gnulib release infrastructure.\n\n  - M4 is now used for scanning the M4 macros in your configure.ac that\n   'libtoolize' looks at to determine what files you want, and where you\n    would like them installed.  This means that you can compose your\n    version number or any other argument that Libtoolize needs to know at\n    M4 time using git-version-gen from gnulib, for example.\n\n  - Invoking 'libtoolize --ltdl' no longer maintains a separate autoconf\n    macro directory in the libltdl tree, but automatically adjusts the\n    installed libltdl configuration files to share whatever macro\n    directory is declared by the parent project. (Note: if you were\n    already sharing a macro directory with AC_CONFIG_MACRO_DIR(ltdl/m4)\n    or similar, that still works as does any other directory choice).\n\n  - Invoking 'libtoolize --ltdl' no longer maintains a separate auxiliary\n    scripts directory in the libltdl tree, but automatically adjusts the\n    installed libltdl configuration files to share whatever auxiliary\n    scripts directory is declared by the parent project. (Note: if you\n    were already sharing an auxiliary directory with subproject libltdl\n    using AC_CONFIG_AUX_DIR(ltdl/config) or similar, that still works as\n    does any other directory choice).\n\n  - The legacy tests have all been migrated to the Autotest harness.\n\n  - The Autotest testsuite can be run without the especially time consuming\n    tests with:\n\n        make check-local TESTSUITEFLAGS='-k \"!expensive\"'\n\n** Bug fixes:\n\n  - Fix a long-standing latent bug in autom4te include path for autotests\n    with VPATH builds.\n  - Fix a long-standing latent bug in libtoolize that could delete lines\n    from libltdl/Makefile.am in recursive mode due to underquoting in a\n    sed script.\n  - Fix a long-standing bug in libtoolize, by outputting the 'putting\n    auxiliary files in' header with 'libtoolize --ltdl --subproject'.\n  - Fix a long-standing bug in libtoolize subproject installation, by not\n    installing a set of autoconf macro files into the parent project if\n    there is no configure.ac present to use them.\n  - The libtoolize subproject mode selector is now named '--subproject'\n    and is equivalent to the implied '--subproject' mode when no other\n    mode is selected; '--standalone' never worked, and is no longer\n    accepted.\n  - Libtool and libtoolize no longer choke on paths with a comma in them.\n  - In the case where $SHELL does not have the same enhanced features\n    (e.g. the ability to parse 'var+=append') as $CONFIG_SHELL, libtool\n    will now correctly fallback to using only vanilla shell features\n    instead of failing with a parse at startup.\n  - Correctly recognize import libraries when Microsoft dumpbin is used\n    as the name lister and extend the dumpbin wrapper to find symbols\n    in import libraries using the -headers option of dumpbin. Also fix a\n    bug in the dumpbin wrapper that could lead to broken symbol listings\n    in some corner cases.\n  - Use the improved Microsoft dumpbin support to mend preloading of\n    import libraries for Microsoft Visual C/C++.\n  - No longer mangle module-definition (.def) files when feeding them to\n    the Microsoft Visual C/C++ linker via the -export-symbols argument to\n    the libtool script, thus matching how .def files are handled when\n    using GNU tools.\n  - Recognize more variants (e.g. those starting with a LIBRARY statement)\n    of module-definitions (.def) files when using them instead of a raw\n    list of symbols to export.\n  - Fix a long-standing bug when using libtoolize without automake; we\n    no longer remove install-sh with --force, since it's not a file\n    libtoolize will reinstall without --install..\n\n** Important incompatible changes:\n\n  - GNU M4 is required to run libtoolize in a directory with a\n    'configure.ac' (or 'configure.in') that needs tracing to determine\n    what modes and directories have been specified.\n\n  - The use of the idiosyncratically named 'Makefile.inc' in nonrecursive\n    libltdl builds is deprecated, although it will be supported for one\n    more year or until the next release, whichever takes longer.  Please\n    upgrade to the more standard naming of 'ltdl.mk' in keeping with other\n    GNU projects.\n\n  - libtoolize now behaves consistenty in respect of multiple directory\n    arguments to ACLOCAL_AMFLAGS and multiple invocations of AC_CONFIG-\n    _MACRO_DIRS, where the first directory is always selected.  Previous\n    releases took the first ACLOCAL_AMFLAGS argument, but the last\n    invocation of AC_CONFIG_MACRO_DIRS.\n\n  - The libtoolize program now advises use of the new Autoconf\n    AC_CONFIG_MACRO_DIRS declaration.  If you follow that advice, all\n    your developers will need at least autoconf-2.70 and automake-1.13\n    to rebootstrap your probject.  If you still need to support\n    bootstrap with older Autotools, then you should add the following\n    to your configure.ac file:\n\n        m4_ifndef([AC_CONFIG_MACRO_DIRS],\n            [m4_define([AC_CONFIG_MACRO_DIRS],\n                m4_defn([AC_CONFIG_MACRO_DIR]))])\n\n  - Overhead of probing for a non-backslash crippled echo equivalent\n    during initialization of every script has been removed in favor of\n    trusting that \"printf %s\\n\" works out of the box on all non-museum\n    host architectures.  Manually setting ECHO appropriately in the\n    build environment will be necessary on some ancient architectures.\n\n** Changes in supported systems or compilers:\n\n  - Support for bitrig (*-*-bitrig*).\n\n  - Solaris 7 and earlier requires ECHO=/usr/ucb/echo in the build\n    environment, to build and use libtool.\n\nNew in 2.4.2 2011-10-17: git version 2.4.1a, Libtool team:\n\n* New features:\n\n  - The --with-pic configure option now supports a list of comma-separated\n    package names.  This can be used to build some static libraries with PIC\n    objects while building others with non-PIC objects.\n\n  - Initial support for Go, using the gccgo compiler.\n\n  - On Mac OS X .dylib is now tried as well as .so with\n    lt_dlopenext().\n\n* Bug fixes:\n\n  - The generic approximation of the command line length limit (when getconf is\n    not available) works again.  Regression introduced in v2.2.6-39-g9c3d4d8.\n  - The bug that leaked developer tool paths into the release tarballs\n    from ./bootstrap is fixed.\n  - Improved support for the Cuda Compiler Driver (nvcc) on Darwin.\n  - For GCC LTO support, the -fuse-linker-plugin switch is now also removed\n    when computing compiler postdeps.\n\n* Important incompatible changes:\n\n  - The undocumented hardcode_libdir_flag_spec_ld tag variable has been\n    removed in favor of using hardcode_libdir_flag_spec with $wl set to empty.\n\n* Changes in supported systems or compilers:\n\n  - Fixes for gfortran on Darwin, XL Fortran on GNU/Linux.\n  - Support for FreeBSD 1.x (outdated since 1994) has been removed.\n\nNew in 2.4 2010-09-22: git version 2.2.11a, Libtool team:\n\n* New features:\n\n  - Sysroot support.  This allows you to build cross-compiled packages\n    with the same prefix that will be used on the destination machine,\n    and still find dependent libraries under the compiler's \"sysroot\".\n    Without sysroot support, paths internal to the build system may leak\n    into the product of the build.\n\n    Sysroot support is disabled unless the --with-sysroot configure\n    option is passed to configure, because .la files generated with\n    sysroot support will _not_ be usable in general with older Libtools.\n\n  - On non-cygwin Windows systems, we now lookup potential library\n    file names without regard to file name case.\n  - The old testsuite now uses the 'parallel-tests' Automake test driver\n    now for more concurrency and better test logging.  For this, tests are\n    run in verbose mode by default now.\n\n* Important incompatible changes:\n\n  - Autoconf 2.62 and Automake 1.11.1 or newer are now required for\n    bootstrapping Libtool.  For using Libtool in your own projects,\n    Autoconf 2.59 and Automake 1.9.6 should still work.\n  - The fix_srcfile_path variable has been replaced by a more thorough\n    mechanism triggered by the to_tool_file_cmd variable.\n\n* Changes in supported systems or compilers:\n\n  - Initial support for the Microsoft C/C++ Compiler, with help from\n    the compile script in unreleased Automake 1.12. Override the manifest\n    tool used to embed the manifest resource through the environment\n    variable MANIFEST_TOOL. Please note that the import library naming\n    has changed (from foo-2.lib to foo.dll.lib) from when the code lived\n    in its own git branch.\n  - Initial support for the NAG Fortran compiler on GNU/Linux.\n\n* Bug fixes:\n\n  - The 'check-interactive' and 'check-noninteractive' convenience make\n    targets now also work for the old testsuite.\n  - Warnings from Autoconf v2.67-36-g1e604ec about incomplete programs\n    passed to AC_*_IFELSE tests have been fixed.\n  - On IRIX, the test for -Wl,-exported_symbol now also works with gfortran.\n\nNew in 2.2.10 2010-06-10: git version 2.2.9a, Libtool team:\n\n* New features:\n\n  - On non-cygwin Windows systems, we no longer try to lookup the POSIX\n    format path recorded in $libdir of a pseudo-library when looking up\n    the location of the library with the native tools.\n\nNew in 2.2.8 2010-06-05: git version 2.2.7c, Libtool team:\n\n* No new features:\n\n  - Bumped version number and promoted 2.2.7b release candidate to a full\n    stable release.\n\nNew in 2.2.7b 2010-05-20: git version 2.2.7a, Libtool team:\n\n* New features:\n\n  - Libtool ships and installs man pages for libtool and libtoolize now.\n  - New libtool command line flag --help-all.\n  - New libtool command line flag --no-silent (with alternate spelling\n    --no-quiet). This flag (re)enables the default informational messages,\n    but has no effect on so-called \"verbose\" output messages.\n  - New libtool command line flag --no-verbose, which disables only\n    the extra \"verbose\" output messages and has no effect on the\n    default informational messages.\n  - New convenience make targets 'check-noninteractive' to avoid long testsuite\n    runs on Windows with popup windows in the middle, and 'check-interactive'\n    for the complement set of tests.\n  - New link mode flag -bindir to specify the location for installed PE DLLs.\n  - Wrapper scripts and wrapper executables for programs linked against\n    uninstalled shared libraries now support command-line options --lt-debug\n    and --lt-dump-script.\n\n* Important incompatible changes:\n\n  - The wrapper command line option support described above introduces the\n    following incompatibility: the wrapper will remove any command line\n    options that begin with '--lt-*' from the argument list before launching\n    (uninstalled) programs. Any '--lt-*' option on the command line not\n    recognized by the wrapper will result in an error.\n  - The type of the symbol lists variables (lt_*_LTX_preloaded_symbols) has\n    been fixed in the manual and in a couple of tests to match the actual\n    implementation.\n\n* Changes in supported systems or compilers:\n\n  - Improved support for 64bit Windows (mingw64).\n  - Improved support for cegcc (Windows CE/PocketPC).\n  - Support for GNU/kOpenSolaris (kopensolaris*-gnu).\n  - Initial support for compilers on BlueGene BG/P.\n  - Improved support for Atari FreeMiNT.\n  - With binutils 2.19.50+, shared libraries can be built on AIX.\n  - Initial support for the Cuda Compiler Driver on GNU/Linux.\n  - Support for Haiku (i586-pc-haiku).\n  - Initial support for GCC link-time optimization (LTO) flags.\n\n* Bug fixes:\n\n  - Fix 2.2.6 regression that prevented using the libltdl macros together\n    with Autoconf 2.59 ('possibly undefined macro: LT_LIBEXT').\n  - Fix 2.2.4 regression that caused arguments with special characters\n    to be mangled by the compile wrapper for uninstalled programs on MinGW.\n  - libtool command line flag --verbose now also enables explicit\n    verbose output, in addition to its previous behavior of (re)enabling\n    only the default informational output. See New Features, --no-silent.\n  - Link tests are guarded by cache variables so they can be avoided for\n    bootstrapping purposes (e.g., when link tests are not possible).\n  - Argument mangling of execute mode has been improved (i.e., lessened).\n  - Fix 2.1b regression that caused nm to not be the default name lister.\n    The regression affected mainly (arguably broken) cross compiles.\n  - Fix long standing bug that caused compiler checks for Fortran and\n    C++ compilers to run twice.\n  - Link mode works around a parallel build failure on Darwin 9.6.0 due\n    to the 'ar' 'flock'ing an archive upon extraction, by protecting the\n    extraction of convenience archives with a lock.\n  - The Libtool macro files do not contain instances of __oline__ any more,\n    easing merges for configure scripts that are added to version control.\n  - Fix ancient bug where \"-Wc,\" was turned into \"$wl\" (typically \"-Wl,\")\n    when using the compiler driver to link programs. Now \"-Wc,\" is stripped\n    just as it is when linking libraries through the compiler driver.\n  - Symbol versioning works with the GNU gold linker now.\n  - Fixes for detection of shared library dependencies on MinGW systems.\n  - Fixed Sun compiler detection on Solaris with sunCC, sunf77 etc. names.\n\n* Miscellaneous changes:\n\n  - The manual is distributed under the terms of the GNU FDL 1.3 now.\n\nNew in 2.2.6 2008-09-05: git version 2.2.5a, Libtool team:\n\n* New features:\n\n  - New lt_dloadvise_preload() call to set a hint that only preloadeded\n    modules can be opened.\n  - libtoolize no longer removes config.guess and config.sub, even when\n    --install is passed.\n\n* Changes in supported systems or compilers:\n\n  - Fixes for ifort on Darwin, and newer Intel compilers (icc 10, ifort 9)\n    on GNU/Linux.\n  - Fixes for cwrapper (cygwin/mingw) under -stdc=c99.\n  - Support cross compile of MinGW with Wine.\n  - Initial support for cegcc (Windows CE/PocketPC) cross compilation.\n  - Initial support for lf95 (Lahey Fortran 8.1) on GNU/Linux.\n\n* Bug fixes:\n\n  - Several testsuite issues have been fixed, thanks to user feedback.\n\n  - Fix 2.2 regression that caused argz symbols to be exported from\n    libltdl unrenamed on systems that do not have working argz.\n\n  - Revert \"lt_dlopen(NULL) works on AIX again.\". It was not the\n    correct fix.\n\n  - Diagnose '-L' arguments correctly.\n\n  - Libtool no longer tries to open devices as files in execute mode.\n\n  - Libtool no longer removes *.gcno profile information from GCC.\n\nNew in 2.2.4: 2008-05-04: git version 2.2.3a, Libtool team:\n\n* New features:\n\n  - New libtoolize option --no-warn, for users that want to continue to\n    use old libtool style without being nagged.\n  - Options --debug, --no-warn, --quiet and --verbose can be passed to\n    libtoolize through the environment variable LIBTOOLIZE_OPTIONS, for\n    cleaner interaction between the user and libtoolize when called by\n    autoreconf.\n\n* Bug fixes:\n\n  - The documentation for lt_dlopenadvise showed the wrong type for\n    the lt_dladvise parameter.\n  - The public declarations for lt_dlhandle and lt_dladvise are now\n    incomplete struct types rather than void*, which means that nearly\n    all casting is eliminated allowing the compiler to provide more\n    type checking.\n  - libtoolize no longer reports up-to-date files that it would have\n    copied, unless --force is passed.\n  - No longer reports that lt~obsolete.m4 needs to be added to aclocal.m4\n    when it is already there.\n  - When 'aclocal' copied the libtool macros directly into 'aclocal.m4'\n    (i.e. AC_CONFIG_MACRO_DIR is not being used), libtoolize no longer\n    reports that all macros need to be added to 'aclocal.m4', and\n    diagnoses only the macro files that are missing or not up-to-date.\n  - libtoolize now advises use of AC_CONFIG_MACRO_DIR to keep matching\n    libtool macros in-tree where appropriate.\n  - libtoolize now advises use of 'ACLOCAL_AMFLAGS = -I m4' (or\n    equivalent) where appropriate, and errors out when ACLOCAL_AMFLAGS\n    names a different directory to AC_CONFIG_MACRO_DIR.\n\nNew in 2.2.2: 2008-04-01: CVS version 2.2.1a, Libtool team:\n\n* New features:\n\n  - In compile mode, compiler output occurs in the user locale.  This\n    feature has been present in 1.5.26 but not in 2.2.\n\n* Changes in supported systems or compilers:\n\n  - Initial shared library support for AmigaOS4 on powerpc.\n\n* Bug fixes:\n\n  - Fix 2.2 regression in libltdl that causes memory corruption upon\n    repeated 'lt_dlinit(); lt_dlexit()'.\n  - Fix 2.2 regression in libltdl that skipped the dlopen loader if\n    the system also supports other loaders (e.g., Cygwin, HP-UX).\n  - Fix 2.2 regression in that 'libtool --mode=execute CMD ARGS' does not\n    transform ARGS that do not look like shell or C wrappers of libtool\n    programs.\n  - Fix 2.2 regression that kept cross-compiling to w32 from working.\n  - Several testsuite issues have been fixed, thanks to user feedback.\n\nNew in 2.2: 2008-03-01; CVS version 2.1c, Libtool team:\n\n* Bug fixes:\n\n  - argz.c, lt__dirent.c and lt__strl.c are correctly distributed with\n    parent projects using nonrecursive libltdl.\n  - libtoolize no longer tries to install libtool files when libltdl is\n    used in a non-autoconf parent package.\n  - Don't add the CXX tag to libtool when there is no C++ compiler, even\n    if AC_PROG_CXX sets a default g++ compiler where no such compiler\n    actually exists.\n  - make distcheck DISTCHECK_CONFIGURE_FLAGS=--disable-ltdl-install\n    works again.\n\nNew in 2.1b: 2008-02-01; CVS version 2.1a, Libtool team:\n\n* Important incompatible changes and obsoleted features:\n\n  - Removed deprecated APIs from libltdl: lt_dlcaller_register,\n    lt_dlhandle_next, lt_dlhandle_find, lt_dlforeach, lt_dlmutex_register,\n    lt_dlmutex_lock, lt_dlmutex_unlock, lt_dlmutex_seterror,\n    lt_dlmutex_geterror, lt_dlmalloc, lt_dlrealloc, lt_dlfree.\n  - The Libtool and libltdl macros and the testsuite now assume a C89\n    environment, consequently do not test for headers such as string.h,\n    strings.h, memory.h any more.\n  - Fix regression in libltdl symbol exports on Cygwin. Side effect:\n    LT_GLOBAL_DATA and LT_SCOPE are now explicitly defined as\n    declspec(dllexport), bypassing auto-export logic on Cygwin.\n    This tracks existing behavior on MinGW.\n  - The libtool script has been optimized a bit for more modern shells.\n    This breaks use of the stdin file descriptor in libtool, and can\n    break if a different shell is used to execute the libtool script\n    than the one it was configured for.\n  - The macros AC_ENABLE_SHARED, AC_DISABLE_SHARED, AC_ENABLE_STATIC, and\n    AC_DISABLE_STATIC have been un-deprecated after deprecation in\n    1.9b.\n  - The macro LT_WITH_LTDL has been renamed to LTDL_INIT.\n  - Fixed a branch-1-5/HEAD regression to only link uninstalled libraries\n    statically with '-static'.  In order to compensate for this, there\n    is a new link flag '-static-libtool-libs' to provide the previous\n    '-static' semantics.\n\n* New features:\n\n  - Fix installation of libltdl so that it does not need Autoconf and\n    Automake installed, in order to be usable in another package.  This\n    lifts the restrictions introduced in 1.9b.\n  - Default convenience or installable libltdl builds can optionally\n    be declared using new 'convenience' or 'installable' options to the\n    LTDL_INIT macro (as an alternative to individual LTDL_CONVENIENCE\n    or LTDL_INSTALLABLE invocations).\n  - New configure-time options to allow libltdl parent project builder\n    to choose between installed and shipped libltdl, when invoking\n    LTDL_INIT: --with-included-ltdl, --with-ltdl-include,\n    --with-ltdl-lib.\n  - New LT_CONFIG_LTDL_DIR macro to specify a different directory name\n    for a convenience libltdl.\n  - libtoolize has been completely overhauled.\n  - 'libtoolize --install' now also installs 'install-sh'.\n  - New libtoolize options: --non-recursive, --recursive, --subproject.\n    These options control the way libltdl is installed into a package by\n    libtoolize.  The new recursive and non-recursive build modes for\n    libltdl don't require a subconfigure any more.\n    The Libtool package itself builds libltdl nonrecursively.\n  - The 'nonrecursive', 'recursive' and 'subproject' libltdl build\n    modes are given as LTDL_INIT options.\n  - New make variable LTDLDEPS for use in output_DEPENDENCIES.\n  - New multi-module-loader safe libltdl handle iteration APIs:\n    lt_dlhandle_iterate, lt_dlhandle_fetch, lt_dlhandle_map.\n  - New lt_dlinterface_register to maintain separation of concerns\n    between modules loaded by different libraries.\n  - New lt_dlopenadvise takes a new lt_dladvise type argument, which\n    lets the caller request local or global symbol visibility from the\n    module loader with lt_dladvise_local and lt_dladvise_global\n    respectively.  If neither is given, or if lt_dlopen (or lt_dlopenext)\n    are called, then the system default module symbol visibility is used.\n  - The new lt_dladvise_init/lt_dladvise_destroy based APIs also allow\n    caller requests for a filename extension search with lt_dladvise_ext,\n    and for marking a module unloadable with lt_dladvise_resident.\n  - Allow shell special characters like '$' in source file names, but\n    not in object names, to enhance GCJ support.\n  - An entire new Autotest-based testsuite in addition to the old one.\n    Both testsuites have been made more useful for testing\n    cross-compilers.  The new testsuite exposes many more issues, but\n    may also be a little rocky on exotic systems.\n  - In 1.9b, a new variable inherited_linker_flags has been added to the\n    libtool library files.  This variable takes flags that should be\n    used by dependent libraries and programs, but that do not fit into\n    'dependency_libs' for both clarity and backward-compatibility.\n\n* Changes in supported systems or compilers:\n\n  - Removed bitrotted support for xlc on Mac OS X.\n  - Detection of compiler wrappers distcc/ccache and $host_alias prefix.\n  - Basic support for PIE (position-independent executables).\n  - Support for DragonFly BSD, improved support for FreeBSD.\n  - Improved support for GNU/kFreeBSD and GNU/NetBSD.\n  - Support for Interix 3 (Windows SFU) and newer versions.\n  - Support for AIX 6.1.\n  - Improved support for UnixWare.\n  - Initial support for RDOS.\n  - Initial Support for FC (modern Fortran).\n  - Support for Portland Group compiler, the Sun compiler suite on GNU/Linux,\n    and initial support for the IBM compiler suite on GNU/Linux/ppc.\n  - Support for linux-dietlibc ('diet' as well as 'diet-dyn', separately).\n  - Building libltdl with a C++ compiler has been undusted.\n  - On (AIX?,) HP-UX, and OpenBSD, hardcoding has been changed to prefer\n    rpath over absolute dependent library names.  This fixes DESTDIR\n    installs, among others, on the non-HP-UX/PA systems.\n  - Use of C++ templates together with shared libraries has been\n    improved on some systems and with some compilers, but is still\n    ongoing work.  Feedback is desirable here.\n\n* Bug fixes:\n\n  - Fix libltdl on static platforms.\n  - Search paths with GCC on multilib systems like x86_64 have been fixed.\n  - Fixed a regression that prevented use of libltdl without autotools.\n  - Fix error with -version-info on systems with version_type=none, such\n    as BeOS.\n  - Fix symbol exporting for cases where command line length limits are\n    exceeded.\n  - Improve linking with C++ libraries on Solaris with Sun compiler.\n  - Fix installation of libraries that are required by installation\n    commands such as 'ln' or 'rm'.\n  - More robust parsing of mangled '.la' files inside libltdl, fixing a\n    possible overrun and a crash due to memory exhaustion.\n  - Fix compile command line for gcj on MinGW.\n  - Some configure variables have been renamed to fix caching:\n    lt_prog_compiler_pic_works to lt_cv_prog_compiler_pic_works\n    lt_prog_compiler_static_works to lt_cv_prog_compiler_static_works.\n  - Fix 1.9b regression: lt_dlopen(NULL) works on AIX again.\n  - Loads of smaller bug fixes.\n\n\f\nNew in 1.9f: 2004-10-23; CVS version 1.9e, Libtool team:\n* Fix a regression in 1.9d, where ECHO was always set to 'echo' and the\n  backslash quoting tests were never run.\n* Fix a regression in 1.9d, where progpath was used for --no-reexec before it\n  was set.\n* Fix a regression in 1.9d, which required an installed automake to build the\n  bootstrapped tarball.\n* Fix hanging bug on MinGW.\n\f\nNew in 1.9d: 2004-10-03; CVS version 1.9c, Libtool team:\n* If non-pic objects were not compiled, and libtool is called in link mode,\n  libtool no longer silently creates an empty archive, but rather falls\n  back to pic objects.\n* When compiling C glue code with $LTCC, libtool now saves the setting of\n  $compiler_flags from the C tag, and passes those flags to $LTCC.\n* libtool no longer dies when concurrently creating directories with\n  'make -j' on multi-processor hosts.\n* Return type, and name parameter of lt_dlloader_remove are no longer\n  'const'.\n* Name parameter of lt_dlloader_find is no longer 'const'.\n* The API for the slist ADT has been updated: slist_new has been replaced\n  by slist_box; slist_unbox and slist_sort are new; the footprint of\n  slist_remove and slist_fnid have changed; SListCallback and SListCompare\n  types have been exchanged.  See libltdl/slist.c for documentation.\n* libltdl is C89 compatible again.  lt_dlsymbol type removed, and lt_dlsymlist\n  structure changed to avoid using C99 flexible arrays.\n* Support self dlopening for executables on cygwin and mingw.\n* Improved support for linux-gnu/ia64.\n* Initial support for s390x-ibm-tpf.\n* Fixed some memory leaks in libltdl.\n* Improved support for OpenBSD (use rpath instead of hardcoding absolute\n  file names).\n\f\nNew in 1.9b: 2004-08-29; CVS version 1.5a, Libtool team:\n* The /^_?LT_[A-Z_]+$/ namespace is now reserved for Libtool's own macros.\n  If you have any shell variables in this namespace they will need to be\n  renamed.  If you have any macros in this namespace please rename them to\n  prevent any possible future clash with libtool supplied macros.\n* New LT_PREREQ macro for specifying minimum libtool requirement.\n* New LT_INIT interface replaces AC_PROG_LIBTOOL, AC_ENABLE_SHARED,\n  AC_DISABLE_SHARED, AC_ENABLE_STATIC, AC_DISABLE_STATIC,\n  AC_ENABLE_FAST_INSTALL, AC_DISABLE_FAST_INSTALL, AC_LIBTOOL_DLOPEN,\n  AC_LIBTOOL_WIN32_DLL and AC_LIBTOOL_PIC_MODE.  Use autoupdate to modernise\n  your configure.ac files after installing this release.\n* New LT_LANG interface to enable libtool support for a specific language.\n* Language support is now only included if your configure.ac enables it,\n  either through a call to AC_PROG_CXX etc. or LT_LANG.\n* The libtool script will complain if it was built from mismatched ltmain.sh\n  and libtool m4 macro versions.\n* Like automake, libtoolize no longer installs config.guess and config.sub by\n  default.  Use new --install option to get the old behaviour.\n* libtoolize no longer supports the --ltdl-tar option.\n* libtool script is now created by config.status.  Instead of interrogating\n  './libtool' from configure.ac after calling AC_PROG_LIBTOOL, use the\n  variable names directly.\n* libltdl is no longer a self-contained package, and shares configury with\n  the top level directory now.\n* Shared objects (.lo) are no longer created when '-static' is passed in\n  compile mode.\n* New compile mode option '-shared' prevents creation of static objects (.o).\n* New link mode option '-shared' creates only shared libraries at link time.\n* If you configure libtool with --disable-shared (or if libtool does not\n  support shared libraries on your platform) trying to build a library using\n  '-shared' is a fatal error.\n* New link mode option '-weak' tells libtool when not to propagate dependency\n  libraries from dlpreopened modules.\n* libtoolize installs libtool.m4, (ltdl.m4 if used,) and various supporting\n  m4 definitions to AC_CONFIG_MACRO_DIR.\n* Mode inferrence removed, shorthand for choosing modes added.\n* Specifying -allow-undefined is now an error.\n* Speed up max_cmd_len check.\n* libltdl can now preopen modules from within a library, and libtool will\n  accept -dlpreopen options when linking either a shared library or a\n  convenience library.\n* New function in libltdl: lt_dlhandle_find provides access to module handles\n  by module name.\n* New function in libltdl: lt_dlpreload_open opens all preloaded modules.\n* libltdl no longer loads shared libraries with global symbol resolution,\n  this caused problems when the symbols were intended to be overriden further\n  up the stack; it is also not recommended practice.\n* New function in libltdl: lt_dlhandle_first, primes handle iterations (using\n  lt_dlhandle_next) to filter by module interface.\n* libltdl no longer tries to support multi-threaded programming with\n  lt_dlmutex_register(), which was unusable with POSIX threads anyway.\n  The symbols are deprecated but exported for backwards compatibility.\n* libltdl no longer uses lt_dlmalloc, lt_dlrealloc and lt_dlfree.  The symbols\n  are still exported for backwards compatibility.\n* The lt_dlinfo struct has a new module field that can be used by dlloaders.\n* libltdl no longer supports pre-c89 compilers.  Some of the pre89 portability\n  functions had compile time bugs in them anyway, so you guys can't have been\n  using it :-)\n* make install now deletes preexisting $prefix/share/libtool before installing\n  latest files.\n* Extracting symbols from an import library on cygwin and win32 now works.\n* Initial support for amigaos-ppc.\n* Improved support for OpenBSD.\n* Support for Intel C++ version 8.0.\n* New support for IBM's xlc and xlc++ on Mac OS X.\n* Finished support for QNX RTOS.\n* Bug fixes.\n\f\nNew in 1.5.8: 2004-08-07; CVS version 1.5.7a, Libtool team:\n* Support for Intel C++ version 8.0.\n* Improved support for OpenBSD.\n* Support for xlc on Mac OS X.\n* Better support for zsh as /bin/sh.\n* Much faster check for command line length on all BSD systems.\n* Better Mac OS X/darwin support.\n* Bug Fixes.\n\f\nNew in 1.5.6: 2004-04-11; CVS version 1.5.5a, Libtool team:\n* Installs libltdl files properly in $prefix/share/libtool/libltdl. 1.5.4\n  did not install them at all.\n* libltdl correctly guesses the extension for loadable modules again.\n\f\nNew in 1.5.4: 2004-04-03; CVS version 1.5.3a, Libtool team:\n* Bug fixes.\n\f\nNew in 1.5.2: 2004-01-25; CVS version 1.5.0a, Libtool team:\n* lt_dlrealloc is an official part of the libltdl API.\n* --tag, --silent and --debug options are preserved and reused when libtool\n  calls itself for relinking etc.\n* '-pthread' and similar options are honoured when linking shared libraries.\n* -no-suppress in compile mode shows compiler output for both PIC and non-PIC\n  object compilation.\n* New link mode option '-precious-files-regex' to prevent accidental removal\n  of files you want to keep, such as test coverage data, from the temporary\n  output directory.\n* Directories specified in /etc/ld.so.conf are no longer hardcoded on GNU/Linux.\n* Recognises the 'R' symbol type on Solaris so read-only symbols can be\n  exported.\n* Bug fixes.\n\f\nNew in 1.5.1: 2003-??-??; CVS version 1.5.0a, Libtool team:\n* lt_dlrealloc is an official part of the libltdl API.\n* Bug fixes.\n\f\nNew in 1.5: 2003-04-14; CVS version 1.4e, Libtool team:\n* First stable release of multi-language architecture.\n* libtool and libltdl support for Mac OS/X.\n* libltdl will now use cygwins dlopen API instead of always forcing\n  LoadLibrary.\n* Support auto-import patch to binutils on cygwin for much improved dll\n  support.\n* Bug fixes.\n\f\nNew in 1.4.3: 2002-10-13; CVS version 1.4.2a, Robert Boehne:\n* The libltdl subdirectory now bootstraps correctly with Automake 1.5.\n* srcdir != builddir builds with Automake 1.5 work correctly.\n* Support for mips-compaq-nonstopux.\n* New command line argument, --preserve-dup-deps prevents removal of\n  duplicate dependent libraries.\n\f\nNew in 1.4d: 2002-01-07; CVS version 1.4c, Libtool team:\n* Help strings display correctly again.\n* Better error messages when library linking fails.\n* Better error messages from libltdl when loading fails.\n* Better search path management in libltdl with 'lt_dlinsertsearchdir' call.\n* Support /lib/w32api in recent cygwin releases.\n* Support cross compilation to mingw.\n* Support for .rc files (Windows resource compiler).\n* Improved handling of mingw gcc.\n* Improved handling of $PATH with entries containing spaces.\n* Improved support for linking with gcc on aix4* and aix5*.\n* Improved support for GCC 3.0.\n* Initial support for QNX RTOS, UnixWare 7 and OpenUNIX 8.\n* Bug fixes to the OpenBSD port.\n* Bug fixes.\n\f\nNew in 1.4.2: 2001-09-11; CVS version 1.4.1a, Gary V. Vaughan:\n* libltdl now builds on solaris again\n* diagnose and warn about not-quite-working combinations of gcc and\n  ld on solaris.\n* Improved OpenBSD support.\n* Improved cygwin support.\n* Bugfixes.\n\f\nNew in 1.4.1: 2001-09-03; CVS version 1.4.0a, Libtool team:\n* Better error messages from libltdl when loading fails.\n* Don't leave here-doc files behind.\n* Improved support for OpenBSD.\n* Libtool will build with autoconf-2.50 and higher.\n* Plug memory management bugs in libltdl.\n* Prefer shl_load to dlopen for better operation on HP-UX.\n\f\nNew in 1.4b: 2001-07-09; CVS version 1.4a, Libtool team:\n* Now bootstraps with autoconf-2.50 and automake-1.4-p4.\n* Always try to build at least a static lib, even if both static and\n  shared libs were disabled.\n* Full support for C++ compiler.\n* Support for GNU gcj compiler.\n* libltdl can now load all modules in a given path according to user\n  supplied criteria with 'lt_dlforeachfile' call.\n* Improved support for AIX ia64, djgpp, HPUX, hurd, OpenBSD, sco3.2*.\n* Internal mutex handling no longer has namespace clashes on NCR MP-RAS.\n* New pdemo and tagdemo tests.\n* Bug fixes.\n\f\nNew in 1.4: 2001-04-25; CVS version 1.3e, Libtool team:\n* Support for aix5*.\n* Bugfixes.\n\f\nNew in 1.3d: 2001-04-02; CVS version 1.3c, Libtool team:\n* ltconfig is no more.  Generation of libtool happens directly from\n  the configure file.\n* Multithread safe with lt_dlmutex_register callback registration.\n* New -no-install flag to avoid the use of executable wrapper scripts.\n* New --with-pic, -prefer-pic and -prefer-non-pic flags to control\n  the generation of PIC/non-PIC code.\n* Support for hardcoding run-time paths (-R) into libraries.\n* Support -dlopen and -dlpreopen for libraries.\n* Libtool now allows you to link shared libraries against static code.\n* New functions in libltdl:\n  lt_dlgetinfo, lt_dlhandle_next and lt_dlforeach provide access to module\n  specific data in handles.\n  lt_dlcaller_register, lt_dlcaller_set_data and lt_dlcaller_get_data provide\n  management for user storage of per module data.\n  lt_dlloader_next, lt_dlloader_name, lt_dlloader_find, lt_dlloader_add and\n  lt_dlloader_remove can be used for adding new types of module loaders.\n  lt_dladderror, lt_dlseterror integrate user module loaders with lt_dlerror.\n* \"-Xcompiler\" and \"-Wc,\" does now work in compile mode, too.\n* Support recent dlltool formats.\n* Start of support code for cross-compiling to win32.\n* libltdl can now be built as a dll with win32.\n* m4 macros needed to configure libltdl split out into libltdl/ltdl.m4.\n* New port to NEWS-OS Release 6.\n* Improved support for darwin (rhapsody), mingw32, NetBSD, Compaq Tru64 V5.0\n  and Digital Unix V4.*.\n* Initial support for ia64 linux.\n* Initial support for a.out freebsd shared libs.\n* Initial support for Paul Sokolovsky's pw32 POSIX over win32 layer.\n* Many bugfixes (especially in libltdl)\n\f\nNew in 1.3b: 1999-07-02; CVS version 1.3a, Libtool team:\n* Complete inter-library dependencies support. It's now possible\n  to link libtool libraries against other libtool libraries.\n* Libtool is able to find already-installed libtool libraries,\n  even if they were moved out of their installation directory.\n* New \"-Wc,flag\" and \"-Xcompiler flag\" flags to pass flags\n  directly to the compiler\n* New \"-Wl,flag\" and \"-Xlinker flag\" flags to pass flags\n  directly to the linker\n* New \"-no-fast-install\" flag to selectively disable fast-install mode.\n* Support for installing stripped libraries using GNU strip (install -s).\n  Automake >= 1.5 will install stripped libraries with \"make install-strip\".\n* Allow linking shared libraries against static ones\n  on FreeBSD, GNU/Linux, GNU Hurd and Solaris\n* Support for linking DLLs on Win32\n* New 'clean' mode to delete uninstalled files.\n* New demos and tests\n* Various bugfixes\n\f\nNew in 1.3.5: 2000-05-27, CVS version 1.3.4a, Libtool team:\n* Support for mac OS X (rhapsody).\n* Support for *-sequent-sysv4.\n* Support for Cygwin-1.1.0.\n* Support recent dlltool formats.\n* Bugfixes.\n\f\nNew in 1.3.4: 1999-12-08, CVS version 1.3.3a, Libtool team:\n* Support for Compaq Tru64 V5.0.\n* Improved support for Digital Unix V4.*.\n* Improved support for NetBSD, FreeBSD and Unixware.\n* Many fine bugfixes.\n\f\nNew in 1.3.3: 1999-07-02, CVS version 1.3.2a, Libtool team:\n* New '-dlpreopen force' flag to ensure that\n  lt_preloaded_symbols is always defined.\n* Work around self-dlclose bug in FreeBSD 3.1.\n* Expand convenience libraries when creating reloadable objects.\n* Do not forget to import -L flags of convenience libraries.\n* Do not pass -whole-archive or equivalent to symbol extractor.\n* Create directory to expand convenience libraries only when needed.\n* Improved support for Cygwin, DJGPP and NetBSD\n* Various bugfixes\n\f\nNew in 1.3.2: 1999-05-26, CVS version 1.3.1a, Libtool team:\n* Avoid circular links of objects and libraries.\n* Look for dlerror when dlopen was found in -ldl (typo).\n* Disable shared libraries with broken GNU ld on Solaris.\n\f\nNew in 1.3.1: 1999-05-21, CVS version 1.3.0a, Libtool team:\n* Documentation improvements; recommend automake users to insert libtool.m4\n  in acinclude.m4\n* AC_LIBLTDL_CONVENIENCE and AC_LIBLTDL_INSTALLABLE now set INCLTDL.\n* New port to NEC UX/4800.\n* cygwin-b20.1 passes all tests.\n* Slightly improved BeOS support.\n* Many AIX 4.3.2 test failures have gone.\n* Pass unknown -L arguments through to the linker (for -LANG:* support).\n* Close a security hole with mode 777 directory during libltdl installation.\n* Fixed the infamous 'ifelse' bug in libtool.m4\n\f\nNew in 1.3: 1999-04-29, Libtool team:\n* This is just a summary of the changes since 1.2.\n  See the news of intermediate alpha releases below for details.\n* Support for convenience archives.\n* New maintainers.  Anonymous CVS and home page at gnu.org.\n* Portable dlopening interface with libltdl, new -module flag.\n* Correctly link installed libtool libraries into programs and other\n  libtool libraries.  Linking of uninstalled libtool libraries into\n  libraries is under development for 1.4.\n* Do not drop library dependencies on platforms that allow them.\n* Linking with uninstalled libraries no longer picks installed ones by\n  mistake.\n* Use libraries from the build tree when running uninstalled\n  executables (may require double linking).\n* Allow developers to optimize for build-tree executions.\n* Support -export-symbols-regex for controlled symbol exporting.\n* Support -R to hardcode directories in library search paths.\n* New ports, demos and tests.  Lots of improvements and bug fixes.\n\f\nNew in CVS version 1.2g, Libtool team:\n* AM_PROG_LIBTOOL is smaller and faster\n* AC_LIBTL_L_WIN32_DLL is required in configure.in for libtool to\n  attempt to build dlls on win32 hosts\n* Shared libraries on AmigaOS up to version 4 are now disabled\n  since they don't meet libtool's requirements for shared libraries\n* -L supports now relative directories\n* Libltdl has a new license: LGPL with a special exception\n* Libltdl can be used as stand-alone package\n* dlopen support for BeOS\n* Partial support for Motorola System V 4\n* Improved support for AIX, BeOS, Cygwin, DJGPP, DU, IRIX and HP/UX\n* Documentation updates\n* New tests\n* Bugfixes\n\f\nNew in 1.2f: 1999-03-15; CVS version 1.2e, Libtool team:\n* libtool will correctly link uninstalled libraries into programs\n  and prefer uninstalled libraries to installed ones\n* Library paths that are in the system default run-time search path\n  are no longer hardcoded into executables.\n* New fast installation mode, which links the final executable\n  in order to avoid relinking during installation.\n  Programs in the build-tree are relinked when executed.\n* New AC_DISABLE_FAST_INSTALL macro to set the default for\n  the fast-install mode to disabled\n* New -export-symbols-regex flag, to export symbols selectively by\n  a regular expression\n* Support -R for specifying run-time path of programs and library dependencies\n* New -avoid-version option to avoid versioning for libraries\n* libtool module names no longer need to have a \"lib\" prefix\n  (requires automake 1.4).\n* New -thread-safe flag, to build thread-safe libraries\n* Major improvements in libltdl: API documentation, installable version,\n  support for module search paths, support for lt_dlopen(0),\n  can be embedded into packages as a tar file (libltdl.tar.gz),\n  dynamic buffer allocation and buffer overflow checks,\n  new macro LTDL_SET_PRELOADED_SYMBOLS() which must be used in the\n  main program, dynamic memory allocation functions are user-defineable\n* New AC_LIBLTDL_CONVENIENCE and AC_LIBLTDL_INSTALLABLE macros, to select\n  convenience and/or installable versions of libltdl.\n* libltdl is now built and installed unless --disable-ltdl-install\n* New \"-dlopen self\" flag for dlopening the executable itself\n* New AC_LIBTOOL_DLOPEN macro to check for dlopen support,\n  required if you use -dlopen or -dlpreopen\n* If libtool could not satisfy all dependencies of a module\n  it will only build a static version of it\n* dld_preloaded_symbols was renamed to lt_preloaded_symbols\n* Support for BeOS\n* Improved support for FreeBSD, AIX, IRIX, OSF, SysV 4.3, HP/UX, DJGPP\n  BSD/OS 4.x and NetBSD\n* In order for libtool to attempt to link a shared library (dll) on win32\n  platforms, you must pass the -no-undefined flag to libtool in link mode.\n* The path to GNU ld now works on cygwin-b18 to cygwin-b20.2 at least.\n* Support for IRIX library versioning.\n* New demos and tests\n* Various bugfixes\n\f\nNew in 1.2d: 1998-12-16; CVS version 1.2c, Libtool team:\n* libtool will correctly link already-installed libraries into programs.\n* New -module flag, to create loadable modules.\n* New libltdl, a small library for portable dlopening of modules.\n  It is still undocumented, but you can already find some examples in:\n* New mdemo directory, with tests of -module and dlopening examples.\n  Be aware that libltdl is only known to work on a few platforms such as\n  GNU/Linux and Solaris2.  Some mdemo tests are known to FAIL on several\n  other platforms; please ignore these failures by now (or work to fix\n  them :-).\n* Inter-library dependencies patch finally integrated, but there's\n  still much porting to do.  See PORTING for details (some plans for the\n  future in mail/deplibs in the CVS tree).\n* New option -export-symbols to control symbol exporting when possible.\n* Fixed -export-dynamic problem with C++ programs in egcs 1.1.\n* New dlpreopen structure.\n* libtool now supports '-c -o' and subdirectories in sources and\n  target object names even in platforms whose compilers do not support\n  this.  In this case, file locking occurs to avoid problems with\n  parallel builds.\n* New 'echo' variant that should fix most problems with long command\n  lines and broken printf programs.\n* Support for DG/UX, UnixWare 7.x and FreeBSD 3.0, and improved\n  support for Microsoft Windows\n* Various bugfixes\n* We now have anonymous CVS access to GNU libtool.  CVSROOT is\n  :pserver:anoncvs@anoncvs.gnu.org:/gd/gnu/anoncvsroot.  The password\n  is empty.  The directory is libtool.  Check our home-page at\n  http://www.gnu.org/software/libtool/libtool.html for details.\n* Alexandre Oliva, Thomas Tanner and Gary V. Vaughan have taken over\n  the maintenance of libtool.\n* Arguments to ltconfig have been changed to allow creation of a\n  libtool C program, totally unusable as of this release.\n\f\nNew in 1.2b - 1998-07-01, Gordon Matzigkeit:\n* Libtool needs a new maintainer, since Gordon Matzigkeit has quit.\n  If you think you can do the job, send mail to bug-libtool@gnu.org.\n* Bug fixes.\n* Support for libtool convenience archives.\n\f\nNew in 1.2a - 1998-04-19, Gordon Matzigkeit:\n* Bug fixes.\n* ltconfig accepts an '--output' option to specify the name of the\n  generated libtool.\n* New '--debug' flag to turn on shell script tracing for libtool,\n  libtoolize, and ltconfig.\n* Added 'libtool --config' to print out all configuration variables.\n* Support for *-*-hpux11*.\n\f\nNew in 1.2 - 1998-03-20, Gordon Matzigkeit:\n* Minor bug fixes to provide a stable public release.\n* Libtool no longer cseses Solaris printf to barf due to silly\n  2110-byte static buffers.\n\f\nNew in 1.1 - 1998-03-08, Gordon Matzigkeit:\n* Bug fixes.\n* http://www.profitpress.com/libtool/ is libtool's homepage.\n* 'AM_PROG_LIBTOOL' supports turning shared or static libraries off\n  with the '--enable-shared=PKGS' and '--enable-static=PKGS' configure\n  flags.  See (libtool)AM_PROG_LIBTOOL.\n* Use the 'AM_DISABLE_SHARED' or 'AM_DISABLE_STATIC' macros if you\n  wish to modify the default behaviour of 'AM_PROG_LIBTOOL' for your\n  package.\n* New rules for 'AM_PROG_LD' to use gcc's '-print-prog-name' flag in\n  order to find ld, if possible.\n* Suppress duplicate compiler output during 'compile' mode.\n* Deleted 'dlname' mode.  Dlopen applications should only use the\n  runtime search method described in (libtool)Finding the dlname.\n* Experimental support for dynamically loaded modules, even on\n  static-only platforms, via new '-dlopen' and '-dlpreopen' link\n  flags.\n* 'compile' mode honours the '-static' flag to prevent libtool\n  from building PIC objects.\n* New 'execute' mode to support debugging uninstalled libtool\n  libraries and executables.\n* '-allow-undefined' is now the default.  You can use '-no-undefined'\n  to declare that a shared library is completely self-contained.\n* Inter-library dependencies are automatically handled when linking\n  against an uninstalled '.la' file.\n* New '-all-static' flag to prevent any dynamic linking.  The regular\n  '-static' flag now just prevents dynamic linking of libtool libraries.\n* New '-release' flag to encode release numbers into libtool\n  libraries.  This breaks binary compatibility, but is useful for\n  libraries whose interfaces change very frequently.  See\n  (libtool)Versioning.\n* The '-rpath' flag can be used to hardcode absolute directories when\n  linking executables using libtool.\n* New robust quoting code to handle any metacharacters passed in\n  arguments to libtool commands.\n* Full support for broken collect2 on AIX 3.  Shared libraries\n  can now be built with all working versions of GCC on AIX.\n* Shell script speed optimizations for old and buggy /bin/sh systems,\n  such as HP-UX 9 and SunOS 4.1.4.\n* Maybe use '_libs' as a temporary libtool directory instead of '.libs'\n  in order to cope with MS-DOS filenames.\n* Portability fixes for Windows NT.\n* Refuse to create libtool libraries that don't begin with 'lib'.\n  This allows us to correctly handle OSes that don't have the 'lib'\n  prefix by default, such as OS/2.\n* Support for *-*-amigaos*, *-*-os2*, *-*-sysv4.2uw2*, and *-*-uts4*.\n\f\nNew in 1.0 - 1997-07-08, Gordon Matzigkeit:\n* Bug fixes.\n* Better configuration test to find the system linker.  The old test\n  was failing because people frequently install GNU ld, but don't\n  necessarily configure GCC to use it.\n* Automake support for Libtool now uses the LTLIBRARIES primary.  See\n  the Automake documentation for more information.\n* Added new '--disable-static' flag to disable building static\n  libraries on platforms that have shared libs.\n* New '-allow-undefined' link flag to build shared libs that contain\n  references to unresolved symbols.\n* Removed all support for creating static-only libraries.\n* Basic support for dynamically loaded modules: new '-export-dynamic'\n  linking flag and corresponding 'dlname' mode.\n* New '--features' flag to display configured libtool attributes.\n* Added support for installing libtool objects, both in absolute and\n  relative directories.\n* Support *-*-linux-gnu* as an alias for *-*-linux*.\n* Support for *-*-openbsd* and *-*-freebsd3*.\n\f\nNew in 0.9 - 1997-02-03, Gordon Matzigkeit:\n* Bug fixes.\n* The libtool demo now uses the libm cos(3) function, to demonstrate\n  inter-library dependencies.\n* The PLATFORMS file has been moved to doc/platforms.texi.\n\f\nNew in 0.8 - 1997-01-26, Gordon Matzigkeit:\n* Bug fixes, and more documentation.\n* Basic support for other language compilers (C++, Fortran, and\n  preprocessed assembler).\n* Libtool is now more persistent when linking with the '-static'\n  flag fails.\n* New test for hardcoding system linkers, to verify that libtool\n  neither creates incorrect binaries, nor takes unnecessary\n  precautions while linking against uninstalled shared libraries.\n* For clarity, the demo subdirectory no longer uses ansi2knr, and has\n  been rewritten to avoid ANSI-only constructs.\n* Support for *-*-irix5, *-*-irix6*, and *-*-sco3.2v5*.\n\f\nNew in 0.7 - 1996-12-08, Gordon Matzigkeit:\n* Total rewrite of libtool, along with a new model for library building.\n* Completely rewritten documentation for the new paradigm.\n* Sane handling of broken system linkers, such as the ones on AIX\n  and HP-UX.\n* configure mode is now a separate program, 'ltconfig'\n* The libinfo helper script has been incorporated into the main\n  libtool program.\n* Automatic mode guessing, based on the command line.\n* Full support for Automake 1.2 (including ansi2knr features).\n* Support to create reloadable objects using link mode.\n* Support for new '-static' linking flag.\n* Support for stripping libraries during installation.\n* Library version information is now passed on the command line, not\n  through a version file.\n\f\nVersion 0.6 was never released.\n\f\nNew in 0.5:\n* Disabled install-progs until next version, when it will be correctly\n  implemented.\n* Clearer library versioning documentation.  See (libtool)Versioning.\n* Renamed gm_PROG_LIBTOOL to AM_PROG_LIBTOOL\n* Libtool now creates pseudo-objects named foo.lo and pseudo-archives named\n  libfoo.la instead of foo.o and libfoo.a.  See the documentation.\n* libtool compile doesn't interfere with user CFLAGS if they don't\n  conflict with the current objtype.  From Karl Berry.\n* Created new libinfo helper script.\n* libversion.in files are obsolete -- libtool uses libinfo to read the\n  new LIBINFO files.\n* Libtool is better at finding its config file and helper scripts.\n* Support for *-*-gnu*\n\f\nNew in 0.4:\n* Bug fixes and new regression tests\n* On unsupported configurations, 'libtool configure' demotes OBJTYPES to\n  'standard' instead of aborting\n* Added new object type, 't', for tcov(1) support\n* Support for *-*-aix3*, *-*-aix4*, *-*-hpux10*, *-*-osf3*, and *-*-solaris2*\n\f\nNew in 0.3:\n* Bug fixes and new regression tests\n* Added new uninstall-libs mode\n* Added a host argument to configure mode\n* Fixed debugging/hyper-optimizing flags conflict (from Karl Berry)\n* Support for --no-whole-archive when needed by GNU ld (from Ulrich Drepper)\n* Implementation of --enable-linktype, --enable-profile, --enable-shared,\n  --enable-static in gm_PROG_LIBTOOL macro\n* New 'libtoolize' program (modeled after GNU gettext's 'gettextize') to help\n  conversion to libtool\n* New ABOUT-LIBS document for inclusion with libtool-supported packages\n\f\nNew in 0.2:\n* Support for *-*-linux\n* Better checking for GNU ld\n* Reimplemented the config file so that it corresponds more closely to the\n  variables listed in (libtool)Porting Libtool.\n* Reimplemented the shared library version scheme.  See (libtool)Versioning.\n* Replaced '--config-file' and '--version-file' options with '--confdir'\n* Added new install-libs and install-progs modes\n\f\nNew in 0.1:\n* First release of libtool\n* Support for: *-*-freebsd*, *-*-netbsd*, *-*-sunos4*, *-*-ultrix4*\n-- \n\nCopyright (C) 1996, 1998-2019, 2021-2022 Free Software Foundation, Inc.\n\nThis file is part of GNU Libtool.\n\nCopying and distribution of this file, with or without modification,\nare permitted in any medium without royalty provided the copyright\nnotice and this notice are preserved.  This file is offered as-is,\nwithout warranty of any kind.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libtool-2.4.7/README",
    "content": "# GNU Libtool\n\n1. Introduction\n===============\n\n[GNU Libtool][libtool] is a generic library support script.\n[Libtool][] hides the complexity of using shared libraries behind a\nconsistent, portable interface.\n\nLibtool's home page is:\n\n    http://www.gnu.org/software/libtool/libtool.html\n\nSee the file [NEWS][] for a description of recent changes to Libtool.\n\nPlease note that you can build GNU Libtool from this directory using a\nvendor Make program as long as this is an official release tarball;\notherwise you will need GNU Make for sane VPATH support.  See the file\n[INSTALL][] for complete generic instructions on how to build and install\nLibtool.  Also, see the file [doc/notes.txt][notes] for some platform-\nspecific information.\n\nSee the info node (libtool)Tested Platforms. (or the file\n[doc/PLATFORMS][platforms]) for a list of platforms that Libtool already\nsupports.\n\nPlease try it on all the platforms you have access to:\n\n * If it builds and passes the test suite (`gmake check`), please send\n   a short note to the [libtool mailing list][libtool list] with a\n   subject line including the string `[PLATFORM]`, and containing the\n   details from the end of `./libtool --help` in the body.\n * Otherwise, see _Reporting Bugs_ below for how to help us fix any\n   problems you discover.\n\nTo use Libtool, add the new generic library building commands to your\n`Makefile`, `Makefile.in`, or `Makefile.am`.  See the documentation for\ndetails.\n\n[install]: http://git.savannah.gnu.org/cgit/libtool.git/tree/INSTALL\n[libtool]: http://www.gnu.org/s/libtool\n[libtool list]: mailto:libtool@gnu.org\n[news]: http://git.savannah.gnu.org/cgit/libtool.git/tree/NEWS\n[notes]: http://git.savannah.gnu.org/cgit/libtool.git/tree/doc/notes.texi\n[platforms]: http://git.savannah.gnu.org/cgit/libtool.git/tree/doc/PLATFORMS\n\n\n2. Reporting Bugs\n=================\n\nIf this distribution doesn't work for you, before you report the\nproblem, at least try upgrading to the latest released version first,\nand see whether the issue persists.  If you feel able, you can also\ncheck whether the issue has been fixed in the development sources for\nthe next release (see _Obtaining the Latest Sources_ below).\n\nOnce you've determined that your bug is still not fixed in the latest\nversion, please send a full report to the libtool [bug mailing list][],\nincluding:\n\n  1. the information from the end of the help message given by\n     `./libtool --help`, and the verbose output of any failed tests\n     (see _The Test Suites_ immediately below);\n  2. complete instructions for how to reproduce your bug, along with\n     the results you were expecting, and how they differ from what you\n     actually see;\n  3. a workaround or full fix for the bug, if you have it;\n  4. a copy of `tests/testsuite.log` if you are experiencing failures\n     in the Autotest testsuite.\n  5. new test cases for the testsuite that demonstrate the bug are\n     especially welcome, and will help to ensure that future releases\n     don't reintroduce the problem - if you're not able to write a\n     complete testsuite case, a simple standalone shell script is\n     usually good enough to help us write a test for you.\n\nIf you have any other suggestions, or if you wish to port Libtool to a\nnew platform, please send email to the [mailing list][libtool list].\n\nPlease note that if you send us an non-trivial code for inclusion in a\nfuture release, we may ask you for a copyright assignment (for brief\ndetails see the 'Copyright Assignment' section on our\n[Contributing][contribute] webpage.\n\n[bug mailing list]: mailto:bug-libtool@gnu.org\n[contribute]: http://www.gnu.org/software/libtool/contribute.html\n\n\n3. The Test Suite\n=================\n\nLibtool comes an integrated sets of tests to check that your build\nis sane.  You can run like this, assuming that `gmake` refers to GNU\nmake:\n\n    gmake check\n\nThe new, Autotest-driven testsuite is documented in:\n\n    info Autoconf 'testsuite Invocation'\n\nbut simple help may also be obtained through:\n\n    gmake check TESTSUITEFLAGS='--help'\n\nFor verbose output, add the flag '-v', for running only a subset of the\nindependent tests, merely specify them by number or by keyword, both of\nwhich are displayed with the '--list' flag.  For example, the 'libtool'\nkeyword is used for the tests that exercise only this script.  So it is\npossible to test an installed script, possibly from a different Libtool\nrelease, with:\n\n    gmake check \\\n        TESTSUITEFLAGS=\"-k libtool LIBTOOL=/path/to/libtool\"\n\nSome tests, like the one exercising `max_cmd_len` limits, make use of\nthis to invoke the testsuite recursively on a subset of tests.  For these\ntests, the variable `INNER_TESTSUITEFLAGS` may be used.  It will be\nexpanded right after the `-k libtool`, without separating whitespace, so\nthat further limiting of the recursive set of tests is possible.  For\nexample, to run only the template tests within the `max_cmd_len`, use:\n\n    gmake check TESTSUITEFLAGS=\"-v -x -k max_cmd_len \\\n                INNER_TESTSUITEFLAGS=',template -v -x'\"\n\nIf you wish to report test failures to the libtool list, you need to\nsend the file `tests/testsuite.log` to the [bug mailing list][].\n\n\n4. Obtaining the Latest Sources\n===============================\n\n* With the exception of ancient releases, all official GNU Libtool\n  releases have a detached GPG signature file.  With this you can verify\n  that the corresponding file (i.e. without the `.sig` suffix) is the\n  same file that was released by the owner of it's GPG key ID.  First,\n  be sure to download both the .sig file and the corresponding release,\n  then run a command like this:\n\n      gpg --verify libtool-x.y.z.tar.gz.sig\n\n  If that command fails because you don't have the required public key,\n  then run this command to import it:\n\n      gpg --keyserver keys.gnupg.net --recv-keys 2983D606\n\n  and then rerun the `gpg --verify` command.\n\n* Official stable releases of GNU Libtool, along with these detached\n  signature files are available from:\n\n      ftp://ftp.gnu.org/gnu/libtool\n\n  To reduce load on the main server, please use one of the mirrors\n  listed at:\n\n      http://www.gnu.org/order/ftp.html\n\n* Alpha quality pre-releases of GNU Libtool, also with detached\n  signature files are available from:\n\n      ftp://alpha.gnu.org/gnu/libtool\n\n  and some of the mirrors listed at:\n\n      http://www.gnu.org/order/ftp.html\n\n* The master libtool repository is stored in git.\n\n  If you are a member of the savannah group for GNU Libtool, a writable\n  copy of the libtool repository can be obtained by:\n\n      git clone <savannah-user>@git.sv.gnu.org:/srv/git/libtool.git\n\n  If you are behind a firewall that blocks the git protocol, you may\n  find it useful to use\n\n      git config --global url.http://git.sv.gnu.org/r/.insteadof \\\n        git://git.sv.gnu.org/\n\n  to force git to transparently rewrite all savannah git references to\n  use http.\n\n  If you are not a member of the savannah group for GNU Libtool, you can\n  still fetch a read-only copy with either:\n\n      git clone git://git.sv.gnu.org/libtool.git\n\n  or using the CVS pserver protocol:\n\n      cvs -d:pserver:anonymous@pserver.git.sv.gnu.org:/srv/git/libtool.git \\\n          co -d libtool HEAD\n\n* Before you can build from git, you need to bootstrap.  This requires:\n  - Autoconf 2.64 or later\n  - Automake 1.11.1 or later\n  - Help2man 1.29 or later\n  - Xz 4.999.8beta or later (from [tukaani.org](http://tukaani.org/xz))\n  - Texinfo 4.8 or later\n  - Any prerequisites of the above (such as m4, perl, tex)\n\n  Note that these bootstrapping dependencies are much stricter than\n  those required to use a destributed release for your own packages.\n  After installation, GNU Libtool is designed to work either standalone,\n  or optionally with:\n  - Autoconf 2.59 or later\n  - Automake 1.9.6 or later\n\n* The `bootstrap` script sets up the source directory for you to hack.\n\n\n5. Version Numbering\n====================\n\nPeople have complained that they find the version numbering scheme under\nwhich libtool is released confusing... so we've changed it!\n\nIt works like this:\n\n    <major-number>.<minor-number>\n\nReleases with a **major-number** less than 1 were not yet feature\ncomplete.  Releases with a **major-number** of 1 used the old numbering\nscheme that everyone disliked so much.  Releases with a **major-number**\nof 2 us the new scheme described here.  If libtool ever undergoes a\nmajor rewrite or substantial restructuring, the **major-number** will be\nincremented again.\n\nIf we make a patch release to fix bugs in a stable release, we use a\nthird number, so:\n\n    2.4.2\n\nIf we make an alpha quality prerelease, we use a fourth number for the\nnumber of changsets applied since the version it's based on:\n\n    2.4.2.418\n\nAnd finally, if you build an unreleased version it will have a short git\nrevision hash string in hexadecimal appended to all of that:\n\n    2.4.2.418.3-30eaa\n\n--\n  Copyright (C) 2004-2010, 2015-2019, 2021-2022 Free Software\n  Foundation, Inc.\n\n  Written by Gary V. Vaughan, 2004\n\n  This file is part of GNU Libtool.\n\nCopying and distribution of this file, with or without modification,\nare permitted in any medium without royalty provided the copyright\nnotice and this notice are preserved.  This file is offered as-is,\nwithout warranty of any kind.\n\n\nLocal Variables:\nmode: text\nfill-column: 72\nEnd:\nvim:tw=72\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libtool-2.4.7/THANKS",
    "content": "These people have contributed to GNU Libtool.  Some have reported problems,\nothers have contributed improvements to the documentation and actual code.\nThe particular contributions are described in the version control logs and\nChangeLog files.  If your name has been left out, if you'd rather not be\nlisted, or if you'd prefer a different address be used, please send a\nnote to the bug-report mailing list (as seen at end of e.g., libtool --help).\n\n##                                  \naakropotkin                         alex.ameen.tx@gmail.com\nAkim Demaille                       akim@epita.fr\nAlan Hourihane                      alanh@fairlite.co.uk\nAlan Modra                          amodra@bigpond.net.au\nAlan W. Irwin                       irwin@beluga.phys.uvic.ca\nAlbert Cheng                        acheng@ncsa.uiuc.edu\nAlbert Chin-A-Young                 china@thewrittenword.com\nAlex Ameen                          alex.ameen.tx@gmail.com\nAlexander Hass                      alexander.hass@sap.com\nAlexander Shevchenko                sav_ix@ukr.net\nAlexandre Duret-Lutz                adl@gnu.org\nAlexei Sheplyakov                   varg@theor.jinr.ru\nAlex Potapenko                      opotapeno@gmail.com\nAlfred M. Szmidt                    ams@kemisten.nu\nAllan McRae                         allan@archlinux.org\nAllan Sandfeld Jensen               snowwolf@one2one-networks.com\nAlon Bar-Lev                        alon.barlev@gmail.com\nAndreas Jaeger                      aj@suse.de\nAndreas Schiffler                   aschiffler@ferzkopp.net\nAndreas Schwab                      schwab@linux-m68k.org\nAndrew C. Feren                     aferen@CetaceanNetworks.com\nAndrew Suffield                     asuffield@debian.org\nAndrey Slepuhin                     pooh@msu.ru\nAneesh Kumar K.V                    kvaneesh@hotmail.com\nAnthony Green                       green@redhat.com\nArchie Cobbs                        archie@whistle.com\nArkadiusz Miśkiewicz                arekm@maven.pl\nArne Woerner                        woerner@mediabase-gmbh.de\nAssar Westerlund                    assar@sics.se\nBart Van Assche                     bvanassche@acm.org\nBenjamin Reed                       ranger@befunk.com\nBernhard Fischer                    spam.protected\nBernhard Rosenkraenzer              bero@redhat.de\nBernhard Voelker                    mail@bernhard-voelker.de\nBert Driehuis                       bert_driehuis@compuware.com\nBert Wesarg                         bert.wesarg@googlemail.com\nBob McElrath                        bob+libtool@mcelrath.org\nBoyd Lynn Gerber                    gerberb@zenez.com\nBrad                                brad@comstyle.com\nBrad Smith                          brad@comstyle.com\nBrent Leback                        brent.leback@st.com\nBrian Barrett                       brbarret@osl.iu.edu\nBrian W. Barrett                    bbarrett@lanl.gov\nBrice De Bruyne                     bricedb@gmail.com\nBrook Moses                         bmoses@google.com\nBrooks Moses                        bmoses@google.com\nBruce Korb                          bkorb@gnu.org\nBruno Haible                        bruno@clisp.org\nCamilo La Rota                      camilo.larota@ens-lyon.fr\nCarl D. Roth                        roth@cse.ucsc.edu\nChad Cunningham                     ccunning@math.ohio-state.edu\nChris Demetriou                     cgd@google.com\nChris Lattner                       sabre@skylab.org\nChris P. Ross                       cross@eng.us.uu.net\nChristiaan Welvaart                 cjw@daneel.dyndns.org\nChristian Biesinger                 cbiesinger@web.de\nChristian Cornelssen                ccorn@cs.tu-berlin.de\nChristian Rössel                    christian.roessel@gmx.de\nChristoph Egger                     Christoph_Egger@gmx.de\nChristopher A. Knight               chriskn@crt.com\nChristopher Hulbert                 cchgroupmail@gmail.com\nChristopher Pfisterer               cp@chrisp.de\nChristoph Pfisterer                 cp@chrisp.de\nCraig Dooley                        xlnxminusx@gmail.com\nCraig Tierney                       Craig.Tierney@noaa.gov\nCristophe Jarry                     christophe.jarry@ouvaton.org\nDalibor Topic                       robilad@kaffe.org\nDaniel Harvey                       daniel@amristar.com.au\nDaniel Kobras                       kobras@linux.de\nDaniel Reed                         djr@redhat.com\nDaniel Richard G.                   skunk@iSKUNK.ORG\nDan McMahill                        mcmahill@mtl.mit.edu\nDan McNichol                        mcnichol@austin.ibm.com\nDave Brolley                        brolley@redhat.com\nDave Korn                           dave.korn.cygwin@googlemail.com\nDave Vasilevsky                     thevas@mac.com\nDave Yost                           Dave@Yost.com\nDavid 'Digit' Turner                digit@google.com\nDavid Edelsohn                      dje.gcc@gmail.com\nDavid Heine                         dlheine@truffle.Stanford.EDU\nDavid Jones                         jones@mosaid.com\nDerek R. Price                      derek@ximbiot.com\nDirk Mueller                        dmueller@suse.de\nDJ Delorie                          dj@delorie.com\nDonald Anderson                     dda@world.std.com\nDonald D. Anderson                  dda@sleepycat.com\nDonn Washburn                       n5xwb@comcast.net\nDoug Evans                          devans@casey.cygnus.com\nEd Maste                            emaste@freebsd.org\nEdouard G. Parmelan                 Edouard.Parmelan@France.NCR.COM\nEdward M. Lee                       tailbert@yahoo.com\nElizabeth Barham                    soggytrousers@yahoo.com\nErez Zadok                          ezk@cs.columbia.edu\nEric Bavier                         bavier@cray.com\nEric Blake                          ebb9@byu.net\nEric Estievenart                    eric@via.ecp.fr\nEric Lindahl                        erik@theophys.kth.se\nErik van Pienbroek                  erik-gnu@vanpienbroek.nl\nEthan Mallove                       ethan.mallove@sun.com\nFabian Groffen                      grobian@gentoo.org\nFrank Ch. Eigler                    fche@cygnus.com\nFred Cox                            sailorfred@yahoo.com\nFred Fish                           fnf@be.com\nFredrik Estreen                     estreen@algonet.se\nFritz Elfert                        felfert@to.com\nGary Kumfert                        kumfert@llnl.gov\nGeoffrey Keating                    geoffk@apple.com\nGeorge Bosilca                      bosilca@cs.utk.edu\nGerald Pfeifer                      gerald@pfeifer.com\nGreg Eisenhauer                     eisen@cc.gatech.edu\nGuido Draheim                       guidod-2001q3@gmx.de\nHenning Nielsen Lund                hnl_dk@amigaos.dk\nHiroyuki Sato                       hiroysato@gmail.com\nH.J. Lu                             hjl@gnu.org\nHoward Chu                          hyc@highlandsun.com\nIan Lance Taylor                    ian@cygnus.com\nIngo Weinhold                       ingo_weinhold@gmx.de\nJacob Meuser                        jakemsr@jakemsr.com\nJakub Bogusz                        qboosh@pld-linux.org\nJakub Jelinek                       jakub@redhat.com\nJames E Wilson                      wilson@specifixinc.com\nJames Su                            james.su@gmail.com\nJan Engelhardt                      jengelh@inai.de\nJan Kratochvil                      project-libtool@jankratochvil.net\nJay Krell                           jay.krell@cornell.edu\nJean-Frederic Clere                 jfrederic.clere@fujitsu-siemens.com\nJeff Squyres                        jsquyres@cisco.com\nJens Petersen                       petersen@redhat.com\nJeremie LE HEN                      tataz@sitadelle.com\nJeremy C. Reed                      reed@reedmedia.net\nJeremy Huddleston Sequoia           jeremyhu@macports.org\nJim Meyering                        jim@meyering.net\nJim Pick                            jim@kaffe.org\nJim Tison                           jtison@us.ibm.com\nJiro Takabatake                     jiro@din.or.jp\nJoakim Tjernlund                    joakim.tjernlund@transmode.se\nJoel N. Weber II                    devnull@gnu.org\nJoe Orton                           joe@manyfish.co.uk\nJoerg Sonnenberger                  joerg@netbsd.org\nJohn Bowler                         jbowler@acm.org\nJohn David Anglin                   dave.anglin@nrc-cnrc.gc.ca\nJohn R. Cary                        cary@txcorp.com\nJohn Wehle                          john@feith.com\nJohn Wolfe                          jlw@sco.com\nJon Meredith                        jonm@alchemetrics.co.uk\nJoseph Beckenbach III               jrb3@best.com\nJoseph Prostko                      joe.prostko@gmail.com\nJuergen Reuter                      reuter@t00pcx17094.desy.de\nJürgen Reuter                       juergen.reuter@physik.uni-freiburg.de\nJustin Lecher                       jlec@gentoo.org\nKarl Berry                          karl@freefriends.org\nKean Johnston                       jkj@sco.com\nKeith Packard                       keithp@keithp.com\nKen Block                           block@zk3.dec.com\nKenneth Albanowski                  kjahds@kjahds.com\nKevin P. Fleming                    kpfleming@backtobasicsmgmt.com\nKevin Ryde                          user42@zip.com.au\nKhem Raj                            raj.khem@gmail.com\nKO Myung-Hun                        komh78@gmail.com\nKurt D. Zeilenga                    Kurt@OpenLDAP.Org\nKurt Roeckx                         kurt@roeckx.be\nLawrence Velázquez                  larryv@macports.org\nLeif Ekblad                         leif@rdos.net\nLennart Poettering                  lennart@poettering.net\nLionel Landwerlin                   llandwerlin@gmail.com\nLoren James Rittle                  rittle@latour.rsch.comm.mot.com\nLucas Holt                          luke@foolishgames.com\nMaciej Helminiak                    dion2@wp.pl\nMaciej W. Rozycki                   macro@ds2.pg.gda.pl\nMahesh Narayanamurthi               mahesh.mach@gmail.com\nMakoto Ishisone                     ishisone@sra.co.jp\nManfred Weichel                     Manfred.Weichel@pdb.siemens.de\nManish Singh                        yosh@gimp.org\nMarcel Loose                        loose@astron.nl\nMarc Espie                          espie@nerim.net\nMarc Glisse                         marc.glisse@inria.fr\nMarc J. Fraioli                     fraioli@dg-rtp.dg.com\nMarcus Comstedt                     marcus@mc.pp.se\nMarius Vollmer                      mvo@zagadka.de\nMark Kettenis                       kettenis@gnu.org\nMarkus Duft                         markus.duft@salomon.at\nMarkus F.X.J. Oberhumer             markus@oberhumer.com\nMartin Doucha                       doucha@integri.cz\nMasahiro Nobori                     nobori@ss.titech.ac.jp\nMats Rynge                          rynge@isi.edu\nMatthieu Herrb                      matthieu.herrb@laas.fr\nMatthijs Kooijman                   matthijs@stdin.nl\nMax Bowsher                         maxb@ukf.net\nMichael Forster                     email@michael-forster.de\nMichael Haubenwallner               michael.haubenwallner@salomon.at\nMichael Matz                        matz@ifh.de\nMichael Pruett                      michael@68k.org\nMichael Schmitz                     mschmitz@iname.com\nMichael Tiemann                     tiemann@cygnus.com\nMicheal E. Faenza                   mfaenza@mitre.org\nMike Frysinger                      vapier@gentoo.org\nMike Gorchak                        lestat@i.com.ua\nMike Miller                         mtmiller@ieee.org\nMike Stump                          mrs@apple.com\nMikhail Zabaluev                    mikhail.zabaluev@gmail.com\nMisty De Meo                        misty@brew.sh\nMocha                               netbsd_alpha@yahoo.com\nMo DeJong                           mdejong@redhat.com\nMorten Eriksen                      mortene@sim.no\nMumit Khan                          khan@xraylith.wisc.edu\nNaofumi Yasufuku                    naofumi@yasufuku.net\nNick Bowler                         nbowler@draconx.ca\nNick Hudson                         nick@nthcliff.demon.co.uk\nNick Rasmussen                      nick@jive.org\nNIIBE Yutaka                        gniibe@m17n.org\nNix                                 nix@esperi.org.uk\nNoah Misch                          noah@cs.caltech.edu\nNorihiro Tanaka                     noritnk@kcn.ne.jp\nOlaf Lenz                           olenz@fias.uni-frankfurt.de\nOlivier Blin                        olivier.blin@softathome.com\nOllie Wild                          aaw@google.com\nOlly Betts                          olly@muscat.co.uk\nOndřej Bílka                        neleai@seznam.cz\nOzkan Sezer                         sezeroz@gmail.com\nPádraig Brady                       P@draigBrady.com\nPaolo Bonzini                       bonzini@gnu.org\nPatrice Fromy                       patrice.fromy@u-psud.fr\nPatrick Welche                      prlw1@newn.cam.ac.uk\nPaul Berrevoets                     paul@swi.com\nPaul Biggar                         paul.biggar@gmail.com\nPaul Eggert                         eggert@cs.ucla.edu\nPaul Laight                         plaight@quantxautomation.co.uk\nPaul Seidler                        sepek@lavabit.com\nPaul Sokolovsky                     Paul.Sokolovsky@technologist.com\nPavel (Pasha) Shamis                shamisp@ornl.gov\nPavel Raiskup                       praiskup@redhat.com\nPavel Roskin                        pavel_roskin@geocities.com\nPaweł Daniluk                       pawel@bioexploratorium.pl\nPer Bothner                         per@bothner.com\nPeter Breitenlohner                 peb@mppmu.mpg.de\nPeter Eisentraut                    peter_e@gmx.net\nPeter Ekberg                        peda@axentia.se\nPeter Fritzsche                     peter.fritzsche@gmx.de\nPeter Jeremy                        peterjeremy@optushome.com.au\nPeter Johansson                     trojkan@gmail.com\nPeter Kjellerstedt                  peter.kjellerstedt@axis.com\nPeter Rosin                         peda@lysator.liu.se\nPhilip Allison                      philip.allison@smoothwall.net\nPierre Ossman                       ossman@ossman.lkpg.cendio.se\nRainer Emrich                       r.emrich@de.tecosim.com\nRainer Orth                         ro@CeBiTec.Uni-Bielefeld.DE\nRainer Tammer                       tammer@tammer.net\nRaja R Harinath                     harinath@cs.umn.edu\nRalf Menzel                         menzel@ls6.cs.uni-dortmund.de\nRalph Schleicher                    rs@nunatak.allgaeu.org\nReid Spencer                        reid@x10sys.com\nReuben Thomas                       rrt@sc3d.org\nRichard B. Kreckel                  kreckel@ginac.de\nRichard Dawe                        rich@phekda.freeserve.co.uk\nRichard Moseley                     dickie.moseley@virgin.net\nRichard Palo                        richard.palo@baou.fr\nRichard Purdie                      rpurdie@rpsys.net\nRichard Sandiford                   richards@transitive.com\nRichard W.M. Jones                  rjones@redhat.com\nRico Tzschichholz                   ricotz@ubuntu.com\nRobert Garron                       Robert.Garron@Access3000.net\nRobert Millan                       rmh@aybabtu.com\nRoberto Bagnara                     bagnara@cs.unipr.it\nRobert Ögren                        lists@roboros.com\nRobert Yang                         liezhi.yang@windriver.com\nRoger Cornelius                     rac@tenzing.org\nRoland Mainz                        roland.mainz@nrubsig.org\nRoumen Petrov                       bugtrack@roumenpetrov.info\nRudolf Leitgeb                      r.leitgeb@x-pin.com\nRyan Hill                           dirtyepic@gentoo.org\nRyan Schmidt                        libtool@ryandesign.com\nSam Thursfield                      ssssam@gmail.com\nSamuel Meder                        meder@mcs.anl.gov\nSamuel Thibault                     samuel.thibault@ens-lyon.org\nSascha Schumann                     sascha@schumann.cx\nScott McCreary                      scottmc2@gmail.com\nSebastian Wilhelmi                  wilhelmi@ira.uka.de\nSimon Josefsson                     jas@extundo.com\nStacey Marshall                     stacey.marshall@oracle.com\nStas Maximov                        smaximov@ieee.org\nStefan Nordhausen                   nordhaus@informatik.hu-berlin.de\nStefan Sperling                     stsp@elego.de\nStepan Kasal                        kasal@ucw.cz\nStephane Conversy                   Stephane.Conversy@lri.fr\nStephan Kulow                       coolo@kde.org\nSteve Ellcey                        sellcey@mips.com\nSteven M. Schultz                   sms@moe.2bsd.com\nSteve Price                         sprice@hiwaay.net\nSvante Signell                      srs@kth.se\nSven Verdoolaege                    skimo@liacs.nl\nSyd Polk                            spolk@redhat.com\nTerry D. Dontje                     Terry.Dontje@Sun.COM\nThorsten Glaser                     tg@66h.42h.de\nTijl Coosemans                      tijl@FreeBSD.org\nTilman Koschnick                    til@subnetz.org\nTim Mooney                          mooney@dogbert.cc.ndsu.NoDak.edu\nTimothy Wall                        twall@oculustech.com\nTim Rice                            tim@multitalents.net\nTim Van Holder                      tim.van.holder@pandora.be\nTitus von Boxberg                   titus@v9g.de\nTobias Stoeckmann                   tobias@stoeckmann.org\nTodd C. Miller                      Todd.Miller@courtesan.com\nTodd Vierling                       tv@duh.org\nTod Milam                           tmilam@traclabs.com\nTom Kacvinsky                       tjk@ams.org\nTom Tromey                          tromey@cygnus.com\nTony Wyatt                          wyattaw@optushome.com.au\nTor Lillqvist                       tml@iki.fi\nTörök Edwin                         edwintorok@gmail.com\nToshio Kuratomi                     badger@prtr-13.ucsc.edu\nUlrich Drepper                      drepper@ipd.info.uni-karlsruhe.de\nUtz-Uwe Haus                        haus@mail.math.uni-magdeburg.de\nVáclav Haisman                      vhaisman@gmail.com\nVáclav Zeman                        vhaisman@gmail.com\nVadim                               vadim@olly.ru\nVadim Zeitlin                       vz-libtool@zeitlins.org\nVincent Lefevre                     vincent@vinc17.net\nVincent Torri                       doursse@users.sf.net\nVladimir Kushnir                    kushn@mail.kar.net\nVolker Christian                    voc@soft.uni-linz.ac.at\nWarren Dodge                        warren.l.dodge@Tektronix.com\nWesley W. Terpstra                  terpstra@ito.tu-darmstadt.de\nWilfredo Sanchez                    wsanchez@apple.com\nWilliam M. Perry                    wmperry@aventail.com\nXavier Pianet                       xavier@xingo.com\nXin Li                              \nXin LI                              d@delphij.net\nYaakov Selkowitz                    yselkowitz@users.sourceforge.net\nДилян Палаузов                      dilyan.palauzov@aegee.org\nЮрий Андреевич Пухальский           pooh@cryptopro.ru\n\n;; Local Variables:\n;; coding: utf-8\n;; End:\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libusb-1.0.26/AUTHORS",
    "content": "Copyright © 2001 Johannes Erdfelt <johannes@erdfelt.com>\nCopyright © 2007-2009 Daniel Drake <dsd@gentoo.org>\nCopyright © 2010-2012 Peter Stuge <peter@stuge.se>\nCopyright © 2008-2016 Nathan Hjelm <hjelmn@users.sourceforge.net>\nCopyright © 2009-2013 Pete Batard <pete@akeo.ie>\nCopyright © 2009-2013 Ludovic Rousseau <ludovic.rousseau@gmail.com>\nCopyright © 2010-2012 Michael Plante <michael.plante@gmail.com>\nCopyright © 2011-2013 Hans de Goede <hdegoede@redhat.com>\nCopyright © 2012-2013 Martin Pieuchot <mpi@openbsd.org>\nCopyright © 2012-2013 Toby Gray <toby.gray@realvnc.com>\nCopyright © 2013-2018 Chris Dickens <christopher.a.dickens@gmail.com>\n\nOther contributors:\nAaron Luft\nAdam Korcz\nAdrian Bunk\nAdrien Destugues\nAkshay Jaggi\nAlan Ott\nAlan Stern\nAleksandr Mezin\nAlexander Pyhalov\nAlexander Schlarb\nAlexander Stein\nAlex Vatchenko\nAndrew Aldridge\nAndrew Fernandes\nAndrew Goodney\nAndy Chunyu\nAndy McFadden\nAngus Gratton\nAnil Nair\nAnkur Verma\nAnthony Clay\nAntonio Ospite\nArtem Egorkine\nAurelien Jarno\nAxel Gembe\nAymeric Vincent\nBaruch Siach\nBastien Nocera\nBei Zhang\nBence Csokas\nBenjamin Berg\nBenjamin Dobell\nBohdan Tymkiv\nBrent Rector\nBruno Harbulot\nCarl Karsten\nChristophe Zeitouny\nChris Zhu\nChunyu Xie\nColin Walters\nCraig Hutchinson\nDave Camarillo\nDavid Engraf\nDavidlohr Bueso\nDavid Moore\nDmitry Fleytman\nDmitry Kostjuchenko\nDmitry Zakablukov\nDoug Johnston\nEvan Hunter\nEvan Miller\nFabrice Fontaine\nFederico Manzan\nFelipe Balbi\nFlorian Albrechtskirchinger\nFrancesco Montorsi\nFrancisco Facioni\nFrank Li\nFrederik Carlier\nFreek Dijkstra\nGaurav Gupta\nGraeme Gill\nGreg Kroah-Hartman\nGustavo Zacarias\nHaidong Zheng\nHans Ulrich Niedermann\nHarry Mallon\nHector Martin\nHoi-Ho Chan\nIdo Yariv\nIgor Anokhin\nIhor Dutchak\nIlya Konstantinov\nJakub Klama\nJames Hanko\nJeffrey Nichols\nJie Zhang\nJim Chen\nJohann Richard\nJohn Keeping\nJohn Sheu\nJonas Malaco\nJonathon Jongsma\nJoost Muller\nJosh Gao\nJoshua Blake\nJoshua Hou\nJuan Cruz Viotti\nJulian Scheel\nJustin Bischoff\nKarsten Koenig\nKeith Ahluwalia\nKenjiro Tsuji\nKimura Masaru\nKonrad Rzepecki\nKuangye Guo\nLars Kanis\nLars Wirzenius\nLei Chen\nLéo Lam\nLiang Yunwang\nLuca Longinotti\nLuz Paz\nMac Wang\nMarco Trevisan (Treviño)\nMarcus Meissner\nMark Kuo\nMarkus Heidelberg\nMartin Ettl\nMartin Koegler\nMartin Ling\nMartin Thierer\nMathias Hjärtström\nMatthew Stapleton\nMatthias Bolte\nMichael Dickens\nMichel Zou\nMike Frysinger\nMikhail Gusarov\nMikolaj Kucharski\nMorgan Leborgne\nMoritz Fischer\nNancy Li\nNia Alarie\nNicholas Corgan\nOmri Iluz\nOrin Eman\nOzkan Sezer\nPatrick Stewart\nPaul Cercueil\nPaul Fertser\nPaul Qureshi\nPekka Nikander\nPhilémon Favrod\nPino Toscano\nRob Walker\nRomain Vimont\nRoman Kalashnikov\nRyan Hileman\nRyan Schmidt\nSaleem Rashid\nSameeh Jubran\nSean McBride\nSebastian Pipping\nSebastian von Ohr\nSergey Serb\nShawn Hoffman\nSimon Haggett\nSimon Newton\nSlash Gordon\nStefan Agner\nStefan Tauner\nSteinar H. Gunderson\nStephen Groat\nTheo Buehler\nThomas Röfer\nTim Hutt\nTim Roberts\nTobias Klauser\nToby Peterson\nTormod Volden\nTrygve Laugstøl\nUri Lublin\nUwe Bonnes\nVasily Khoruzhick\nVegard Storheil Eriksen\nVenkatesh Shukla\nVianney le Clément de Saint-Marcq\nVictor Toso\nVinicius Tinti\nVitali Lovich\nVladimir Beloborodov\nWilliam Orr\nWilliam Skellenger\nXiaofan Chen\nYegor Yefremov\nZhiqiang Liu\nZoltán Kovács\nСергей Валерьевич\nЛарионов Даниил\nРоман Донченко\njonner\norbitcowboy\nosy\nparafin\nRipleyTom\nSeneral\nsaur0n\nwinterrace\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libusb-1.0.26/COPYING",
    "content": "\t\t  GNU LESSER GENERAL PUBLIC LICENSE\n\t\t       Version 2.1, February 1999\n\n Copyright (C) 1991, 1999 Free Software Foundation, Inc.\n 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n[This is the first released version of the Lesser GPL.  It also counts\n as the successor of the GNU Library Public License, version 2, hence\n the version number 2.1.]\n\n\t\t\t    Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN\nWRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY\nAND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU\nFOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR\nCONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE\nLIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING\nRENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A\nFAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF\nSUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH\nDAMAGES.\n\n\t\t     END OF TERMS AND CONDITIONS\n\f\n           How to Apply These Terms to Your New Libraries\n\n  If you develop a new library, and you want it to be of the greatest\npossible use to the public, we recommend making it free software that\neveryone can redistribute and change.  You can do so by permitting\nredistribution under these terms (or, alternatively, under the terms of the\nordinary General Public License).\n\n  To apply these terms, attach the following notices to the library.  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See the GNU\n    Lesser General Public License for more details.\n\n    You should have received a copy of the GNU Lesser General Public\n    License along with this library; if not, write to the Free Software\n    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA\n\nAlso add information on how to contact you by electronic and paper mail.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the library, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the\n  library `Frob' (a library for tweaking knobs) written by James Random Hacker.\n\n  <signature of Ty Coon>, 1 April 1990\n  Ty Coon, President of Vice\n\nThat's all there is to it!\n\n\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libusb-1.0.26/NEWS",
    "content": "For the latest libusb news, please refer to the ChangeLog file, or visit:\nhttp://libusb.info\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/libusb-1.0.26/README",
    "content": "# libusb\n\nlibusb is a library for USB device access from Linux, macOS,\nWindows, OpenBSD/NetBSD, Haiku and Solaris userspace.\nIt is written in C (Haiku backend in C++) and licensed under the GNU\nLesser General Public License version 2.1 or, at your option, any later\nversion (see COPYING).\n\nlibusb is abstracted internally in such a way that it can hopefully\nbe ported to other operating systems. Please see the PORTING\nfile for more information.\n\nlibusb homepage:\nhttp://libusb.info/\n\nDevelopers will wish to consult the API documentation:\nhttp://api.libusb.info\n\nUse the mailing list for questions, comments, etc:\nhttp://mailing-list.libusb.info\n\n- Hans de Goede <hdegoede@redhat.com>\n- Xiaofan Chen <xiaofanc@gmail.com>\n- Ludovic Rousseau <ludovic.rousseau@gmail.com>\n- Nathan Hjelm <hjelmn@cs.unm.edu>\n- Chris Dickens <christopher.a.dickens@gmail.com>\n\n(Please use the mailing list rather than mailing developers directly)\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/AUTHORS",
    "content": "Dominic Rath <Dominic.Rath@gmx.de>\nMagnus Lundin <lundin@mlu.mine.nu>\nMichael Fischer <fischermi@t-online.de>\nSpencer Oliver <spen@spen-soft.co.uk>\nCarsten Schlote <schlote@vahanus.net>\nØyvind Harboe <oyvind.harboe@zylin.com>\nDuane Ellis <openocd@duaneellis.com>\nMichael Schwingen <michael@schwingen.org>\nRick Altherr <kc8apf@users.berlios.de>\nDavid Brownell <dbrownell@users.sourceforge.net>\nVincint Palatin <vpalatin@users.berlios.de>\nZachary T Welch <zw@superlucidity.net>\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/AUTHORS.ChangeLog",
    "content": "drath:Dominic Rath <Dominic.Rath@gmx.de>\nmlu:Magnus Lundin <lundin@mlu.mine.nu>\nmifi:Michael Fischer <fischermi@t-online.de>\nntfreak:Spencer Oliver <spen@spen-soft.co.uk>\nduane:Duane Ellis <openocd@duaneellis.com>\noharboe:Øyvind Harboe <oyvind.harboe@zylin.com>\nkc8apf:Rick Altherr <kc8apf@users.berlios.de>\nzwelch:Zachary T Welch <zw@superlucidity.net>\nvpalatin:Vincent Palatin <vpalatin@users.berlios.de>\nbodylove:Carsten Schlote <schlote@vahanus.net>\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/COPYING",
    "content": "OpenOCD is provided under:\n\n\tSPDX-License-Identifier: GPL-2.0-or-later\n\nBeing under the terms of the GNU General Public License version 2 or\nlater, according with:\n\n\tLICENSES/preferred/GPL-2.0\n\nIn addition, other licenses may also apply. Please see:\n\n\tLICENSES/license-rules.txt\n\nfor more details.\n\nAll contributions to OpenOCD are subject to this COPYING file.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS",
    "content": "This file includes highlights of the changes made in the OpenOCD\nsource archive release.\n\nJTAG Layer:\n\nBoundary Scan:\n\nTarget Layer:\n\nFlash Layer:\n\nBoard, Target, and Interface Configuration Scripts:\n\nServer Layer:\n\nRTOS:\n\nDocumentation:\n\nBuild and Release:\n\n\nThis release also contains a number of other important functional and\ncosmetic bugfixes. For more details about what has changed since the\nlast release, see the git repository history:\n\nhttp://sourceforge.net/p/openocd/code/ci/v0.x.0/log/?path=\n\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.10.0",
    "content": "This file includes highlights of the changes made in the OpenOCD\nsource archive release.\n\nJTAG Layer:\n\t* New driver for J-Link adapters based on libjaylink\n          (including support for FPGA configuration, SWO and EMUCOM)\n\t* FTDI improvements to work at 30MHz clock\n\t* BCM2835 native driver SWD and Raspberry Pi2 support\n\t* BCM2835 is set to 4ma drive, slow slew rate\n\t* ixo-usb-jtag (emulation of an Altera Bus Blaster I on\n          Cypress FX2 IC) support\n\t* JTAG pass-through mode for CMSIS-DAP (including support for\n          FPGA configuration)\n\t* OpenJTAG support for Cypress CY7C65215\n\t* connect_assert_srst support for SWD\n\t* Xilinx Virtex-II Series7 bitstream loading support\n\t* Use JEP106 data to decode IDs\n\t* Deprecated \"ft2232\" driver removed (use \"ftdi\" instead)\n\t* GPL-incompatible FTDI D2XX library support dropped (Presto,\n          OpenJTAG and USB-Blaster I are using libftdi only now)\n\t* ZY1000 support dropped (unmaintained since long)\n\t* oocd_trace support dropped\n\nBoundary Scan:\n\nTarget Layer:\n\t* ARMv7-A, Cortex-M, Cortex-A/R important fixes and\n          improvements (allowing e.g. simultaneous debugging of A8 and\n          M3 cores, JTAG WAIT support etc.)\n\t* ARM Cortex-A,R allow interrupt disable during single-step\n          (maskisr command)\n\t* Semihosting support for ARMv7-A\n\t* ARM Cortex-M7 support\n\t* Intel Quark mcu D2000 support\n\t* Freescale LS102x SAP support\n\t* ThreadX RTOS support on ARM926E-JS\n\t* Cortex-M RTOS stack alignment fixes\n\t* FreeRTOS FPU support\n\t* uC/OS-III RTOS support\n\t* bridging semihosting to GDB's File-I/O support\n\t* -defer-examine option added to target create command\n\t* verify_image_checksum command added\n\nFlash Layer:\n\t* Atmel SAM4S, SAM4N, SAM4C support\n\t* Atmel SAMV, SAMS, SAME (Cortex-M7) support\n\t* Atmel AT91SAMD handle reset run/halt in DSU, other fixes\n\t* Atmel AT91SAML21, SAML22, SAMC20/SAMC21, SAMD09 support\n\t* ST STM32F4x support\n\t* ST STM32F74x/76x/77x, STM32L4 support\n\t* ST STM32L0 categories 1, 2 and 5 support\n\t* Kinetis K02, K21, K22, K24, K26, K63, K64, K66 support\n\t* Kinetis KE, KVx, K8x families support\n\t* Kinetis FlexNVM handling\n\t* Kinetis flash protection, security, mass_erase improvements\n\t* Infineon XMC4xxx family support\n\t* Infineon XMC1000 flash driver\n\t* Energy Micro EFM32 Happy Gecko support\n\t* Energy Micro EFM32 debug interface lock support\n\t* Analog Devices ADuCM360 support\n\t* Unified Nuvoton NuMicro flash driver\n\t* NIIET K1921VK01T (Cortex-M4) support\n\t* Nordic Semiconductor nRF51 improvements\n\t* Spansion FM4 flash (including MB9BFx64/x65, S6E2DH) driver\n\t* Ambiq Micro Apollo flash driver\n\t* PIC32MX new device IDs, 17x/27x flash support\n\t* read_bank() and verify_bank() NOR flash internal API to\n          allow reading (and verifying) non-memory-mapped devices\n\t* JTAGSPI driver to access SPI NOR flashes via a trivial\n          FPGA proxy\n\t* Milandr read/verify for Info memory support\n\t* Various discrete SPI NOR flashes support\n\t* CFI 16-bit flash reversed endianness support\n\nBoard, Target, and Interface Configuration Scripts:\n\t* Digilent JTAG-HS2, JTAG-HS3 interfaces configs\n\t* FTDI UM232H module as JTAG interface config\n\t* 100ask's OpenJTAG interface config\n\t* MBFTDI interface config\n\t* XDS100v3 interface config\n\t* Freescale Vybrid VF6xx target config\n\t* EmCraft VF6 SOM and baseboard configs\n\t* Freescale SabreSD board config\n\t* Freescale VF65GS10 tower board config\n\t* Pipistrello Xilinx Spartan6 LX45 FPGA board config\n\t* miniSpartan6+ board config\n\t* Xilinx Kintex7 Development board config\n\t* Parallella-I board config\n\t* Digilent Atlys and Analog Discovery board configs\n\t* Numato Opsis board config\n\t* Xilinx Spartan 6 FPGA \"Device DNA\" reading support\n\t* Altera 10M50 FPGA (MAX10 family) target config\n\t* Altera EPM240 CPLD (MAXII family) target config\n\t* Marsohod2, Marsohod3 FPGA, Marsohod CPLD boards configs\n\t* Novena's integrated FPGA board config\n\t* XMOS XS1-XAU8A-10's ARM core config\n\t* XMOS xCORE-XA Core Module board config\n\t* Exynos5250 target config\n\t* Arndale board config\n\t* FM4 MB9BFxxx family configs\n\t* Spansion SK-FM4-U120-9B560 board config\n\t* Diolan LPC4357-DB1 board config\n\t* ST STM32F469 discovery board config\n\t* ST STM32F7-DISCO, STM327[4|5]6G-EVAL boards configs\n\t* ST STM32L4 discovery, NUCLEO L476RG, STM32F429I-DISC1 boards\n          configs\n\t* Atheros AR2313, AR2315 targets config\n\t* Netgear WP102 board config\n\t* La Fonera FON2200 board config\n\t* Linksys WAG200G board config\n\t* LPC-Link2 board config\n\t* NXP LPC4370 target config\n\t* Atmel SAMV, SAMS, SAME target configs\n\t* Atmel SAM E70 Xplained, SAM V71 Xplained Ultra boards\n          configs\n\t* Nordic nRF52 target config\n\t* Nordic nRF51-DK, nRF52-DK boards configs\n\t* Infineon XMC4700 Relax Kit, XMC4800 Relax EtherCAT Kit,\n          XMC4300 Relax EtherCAT Kit boards configs\n\t* Renesas S7G2 target config\n\t* Renesas DK-S7G2 board config\n\t* Altera EP3C10 FPGA (Cyclone III family) target config\n\t* TI MSP432P4xx target config\n\t* Cypress PSoC 5LP target config\n\t* Analog Devices ADSP-SC58x target config (Cortex-A5 core only)\n\nServer Layer:\n\t* tcl_trace command for async target trace output via Tcl RPC\n\nDocumentation:\n\nBuild and Release:\n\t* Various fixes thanks to http://coccinellery.org/\n\t* libftdi is now autodetected with pkgconfig\n\t* Releases should now support reproducible builds\n\t* Conversion to non-recursive make, requires automake >= 1.14\n\t* Udev rules modified to add uaccess tag and moved to\n          60-openocd.rules\n\t* Support searching for scripts relative to the openocd binary\n          for all major architectures\n\n\nThis release also contains a number of other important functional and\ncosmetic bugfixes. For more details about what has changed since the\nlast release, see the git repository history:\n\nhttp://sourceforge.net/p/openocd/code/ci/v0.10.0/log/?path=\n\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.11.0",
    "content": "This file includes highlights of the changes made in the OpenOCD\nsource archive release.\n\nJTAG Layer:\n\t* add debug level 4 for verbose I/O debug\n\t* bitbang, add read buffer to improve performance\n\t* Cadence SystemVerilog Direct Programming Interface (DPI) adapter driver\n\t* CMSIS-DAP v2 (USB bulk based) adapter driver\n\t* Cypress KitProg adapter driver\n\t* FTDI FT232R sync bitbang adapter driver\n\t* Linux GPIOD bitbang adapter driver through libgpiod\n\t* Mellanox rshim USB or PCIe adapter driver\n\t* Nuvoton Nu-Link and Nu-Link2 adapter drivers\n\t* NXP IMX GPIO mmap based adapter driver\n\t* ST-Link consolidate all versions in single config\n\t* ST-Link read properly old USB serial numbers\n\t* STLink/V3 support (for ST devices only !)\n\t* STM8 SWIM transport\n\t* TI XDS110 adapter driver\n\t* Xilinx XVC/PCIe adapter driver\n\nBoundary Scan:\n\nTarget Layer:\n\t* 64 bit address support\n\t* ARCv2 target support\n\t* ARM Cortex-A hypervisor mode support\n\t* ARM Cortex-M fast PC sampling support for profiling\n\t* ARM generic CTI support\n\t* ARM generic mem-ap target support\n\t* ARMv7-A MMU tools\n\t* ARMv7m traces add TCP stream server\n\t* ARMv8 AARCH64 target support and semihosting support\n\t* ARMv8 AARCH64 disassembler support through capstone library\n\t* ARMv8-M target support\n\t* EnSilica eSi-RISC target support, including instruction tracing\n          eSi-Trace support\n\t* MIPS64 target support\n\t* Motorola SREC S6 record image file support\n\t* RISC-V target support\n\t* SEGGER Real Time Transfer (RTT) initial support (for single target,\n\t  Cortex-M only)\n\t* ST STM8 target support\n\t* Various MIPS32 target improvements\n\nFlash Layer:\n\t* Atheros (ath79) SPI interface support\n\t* Atmel atmega128rfa1 support\n\t* Atmel SAM D21, D51, DA1, E51, E53, E54, G55, R30 support\n\t* Atmel SAMC2?N* support\n\t* Cypress PSoC5LP, PSoC6 support\n\t* EnSilica eSi-RISC support\n\t* Foshan Synwit Tech SWM050 support\n\t* Maxim Integrated MAX32XXX support\n\t* Nordic Semiconductor nRF51822, nRF52810, nRF52832 support\n\t* NXP Kinetis K27, K28, KE1x, KEAx, KL28, KL8x, KV5x, KWx support\n\t* Renesas RPC HF support\n\t* SH QSPI support\n\t* SiFive Freedom E support\n\t* Silicon Labs EFR-family, EZR32HG support\n\t* ST BlueNRG support\n\t* ST STM32 QUAD/OCTO-SPI interface support for Flash, FRAM and EEPROM\n\t* ST STM32F72x, STM32F4x3, STM32H7xx support\n\t* ST STM32G0xx, STM32G4xx, STM32L4x, STM32WB, STM32WL support\n\t* ST STM32L5x support (non secure mode)\n\t* TI CC13xx, CC26xx, CC32xx support\n\t* TI MSP432 support\n\t* Winner Micro w600 support\n\t* Xilinx XCF platform support\n\t* Various discrete SPI NOR flashes support\n\nBoard, Target, and Interface Configuration Scripts:\n\t* 8devices LIMA board config\n\t* Achilles Instant-Development Kit Arria 10 board config\n\t* Amazon Kindle 2 and DX board config\n\t* Analog Devices ADSP-SC58x, ADSP-SC584-EZBRD board config\n\t* Andes Technology ADP-XC7KFF676 board config\n\t* Andes Technology Corvette-F1 board config\n\t* ARM Musca A board config\n\t* Arty Spartan 7 FPGA board config\n\t* Atmel SAMD10 Xplained mini board config\n\t* Atmel SAMD11 Xplained Pro board config\n\t* Atmel SAM G55 Xplained Pro board config\n\t* AVNET UltraZED EG StarterKit board config\n\t* Blue Pill STM32F103C8 board config\n\t* DP Busblaster v4.1a board config\n\t* DPTechnics DPT-Board-v1 board config\n\t* Emcraft imx8 SOM BSB board config\n\t* Globalscale ESPRESSObin board config\n\t* Kasli board config\n\t* Kintex Ultrascale XCKU040 board config\n\t* Knovative KC-100 board config\n\t* LeMaker HiKey board config\n\t* Microchip (Atmel) SAME54 Xplained Pro board config\n\t* Microchip (Atmel) SAML11 Xplained Pro board config\n\t* Nordic module NRF52 board config\n\t* Numato Lab Mimas A7 board config\n\t* NXP Freedom FRDM-LS1012A board config\n\t* NXP IMX7SABRE board config\n\t* NXP IMX8MP-EVK board config\n\t* NXP MC-IMX8M-EVK board config\n\t* QuickLogic QuickFeather board config\n\t* Renesas R-Car E2, H2, M2 board config\n\t* Renesas R-Car Salvator-X(S) board config\n\t* Renesas RZ/A1H GR-Peach board config\n\t* Rigado BMD-300 board config\n\t* Sayma AMC board config\n\t* Sifive e31arty, e51arty, hifive1 board config\n\t* ST B-L475E-IOT01A board config\n\t* ST BlueNRG idb007v1, idb008v1, idb011v1 board config\n\t* ST STM32F412g discovery board config\n\t* ST STM32F413h discovery board config\n\t* ST STM32F469i discovery board config\n\t* ST STM32F7 Nucleo board config\n\t* ST STM32F723e discovery board config\n\t* ST STM32F746g discovery board config\n\t* ST STM32F769i discovery board config\n\t* ST STM32H735g discovery board config\n\t* ST STM32H743zi Nucleo board config\n\t* ST STM32H745i discovery board config\n\t* ST STM32H747i discovery board config\n\t* ST STM32H750b discovery board config\n\t* ST STM32H7b3i discovery board config\n\t* ST STM32H7x_dual_qspi board config\n\t* ST STM32H7x3i Eval boards config\n\t* ST STM32L073 Nucleo board config\n\t* ST STM32L476g discovery board config\n\t* ST STM32L496g discovery board config\n\t* ST STM32L4p5g discovery board config\n\t* ST STM32L4r9i discovery board config\n\t* ST STM32L5 Nucleo board config\n\t* ST STM32MP15x DK2 board config\n\t* ST STM32WB Nucleo board config\n\t* ST STM8L152R8 Nucleo board config\n\t* Synopsys DesignWare ARC EM board config\n\t* Synopsys DesignWare ARC HSDK board config\n\t* TI BeagleBone family boards config\n\t* TI CC13xx, CC26xx, CC32xx LaunchPad board config\n\t* TI MSP432 LaunchPad board config\n\t* Tocoding Poplar board config\n\t* TP-Link WDR4300 board config\n\t* Allwinner V3s target config\n\t* Andes Technology NDS V5 target config\n\t* Atmel atmega128rfa1 target config\n\t* ARM corelink SSE-200 target config\n\t* Atheros_ar9344 target config\n\t* Cypress PSoC5LP, PSoC6 target config\n\t* EnSilica eSi-RISC target config\n\t* Foshan Synwit Tech SWM050 target config\n\t* GigaDevice GD32VF103 target config\n\t* Hisilicon Hi3798 target config\n\t* Hisilicon Hi6220 target config\n\t* Infineon TLE987x target config\n\t* Marvell Armada 3700 target config\n\t* Maxim Integrated MAX32XXX target config\n\t* Mellanox BlueField target config\n\t* Microchip (Atmel) SAME5x, SAML1x target config\n\t* NXP IMX6SX, IMX6UL, IMX7, IMX7ULP, IMX8 target config\n\t* NXP Kinetis KE1xZ, KE1xF target config\n\t* NXP LPC84x, LPC8Nxx, LS1012A, NHS31xx target config\n\t* Qualcomm QCA4531 target config\n\t* QuickLogic EOS S3 target config\n\t* Renesas R-Car E2, H2, M2 target config\n\t* Renesas R-Car Gen3 target config\n\t* Renesas RZ/A1H target config\n\t* Rockchip RK3308 target config\n\t* ST BlueNRG target config\n\t* ST STM32G0, STM32G4, STM32H7, STM32L0, STM32L5 target config\n\t* ST STM32MP15x target config\n\t* ST STM32WBx, STM32WLEx target config\n\t* ST STM8L152, S003, S103, S105 target config\n\t* Synopsys DesignWare ARC EM target config\n\t* Synopsys DesignWare ARC HS Development Kit SoC target config\n\t* TI CC13xx, CC26xx, CC32xx target config\n\t* TI TNETC4401 target config\n\t* Xilinx UltraScale+ target config\n\t* Altera 5M570Z (MAXV family) CPLD config\n\t* Xilinx Ultrascale, XCF CPLD config\n\t* Intel (Altera) Arria10 FPGA config\n\t* Cadence SystemVerilog Direct Programming Interface (DPI) interface config\n\t* Cypress KitProg interface config\n\t* Digilent SMT2 NC interface config\n\t* DLN-2 example of Linux GPIOD interface config\n\t* FTDI C232HM interface config\n\t* HIE JTAG Debugger interface config\n\t* In-Circuit's ICprog interface config\n\t* isodebug isolated JTAG/SWD+UART interface config\n\t* Mellanox rshim USB or PCIe interface config\n\t* Nuvoton Nu-Link interface config\n\t* NXP IMX GPIO mmap based interface config\n\t* Steppenprobe open hardware interface config\n\t* TI XDS110 interface config\n\nServer Layer:\n\t* 64 bit address support\n\t* default bind to IPv4 localhost\n\t* gdb: allow multiple connections\n\t* gdb: architecture element support\n\t* gdb: vCont, vRun support\n\t* telnet: handle Ctrl+A, Ctrl+E and Ctrl+K\n\nRTOS:\n\t* Chromium-EC rtos support\n\t* hwthread pseudo rtos support\n\t* NuttX rtos support\n\t* RIOT rtos support\n\nDocumentation:\n\t* Improve STM32 flash driver\n\t* Various typo fix and improvements\n\nBuild and Release:\n\t* Add libutil to support jimtcl version 0.80\n\t* Clang warning fixes\n\t* GitHub workflow for Win32 snapshot binaries\n\t* Handle Tcl return values consistently\n\t* Mitigation for CVE-2018-5704: Prevent some forms of Cross\n          Protocol Scripting attacks\n\t* Support for libftdi 1.5\n\t* Travis-CI basic support\n\t* Update libjaylink to version 0.2.0\n\t* Update jimtcl to version 0.79\n\t* Use external (optional) library capstone for ARM and AARCH64 disassembly\n\n\nThis release also contains a number of other important functional and\ncosmetic bugfixes. For more details about what has changed since the\nlast release, see the git repository history:\n\nhttp://sourceforge.net/p/openocd/code/ci/v0.11.0/log/?path=\n\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.12.0",
    "content": "This file includes highlights of the changes made in the OpenOCD\nsource archive release.\n\nJTAG Layer:\n\t* add default to adapter speed when unspecified (100 kHz)\n\t* AM335X gpio (BeagleBones) adapter driver\n\t* BCM2835 support for SWD\n\t* Cadence Virtual Debug (vdebug) adapter driver\n\t* CMSIS-DAP support for SWO and SWD multidrop\n\t* Espressif USB JTAG Programmer adapter driver\n\t* Remote bitbang support for Windows host\n\t* ST-LINK add TCP server support to adapter driver\n\t* SWD multidrop support\n\nBoundary Scan:\n\nTarget Layer:\n\t* aarch64: support watchpoints\n\t* arm: support independent TPIU and SWO for trace\n\t* arm adi v5: support Large Physical Address Extension\n\t* arm adi v6: support added, for jtag and swd transport\n\t* cortex_a: support watchpoints\n\t* elf 64bit load support\n\t* Espressif: support ESP32, ESP32-S2 and ESP32-S3 cores\n\t* semihosting: support user defined operations\n\t* Xtensa: support Xtensa LX architecture via JTAG and ADIv5 DAP\n\nFlash Layer:\n\t* Atmel/Microchip SAM E51G18A, E51G19A, R35J18B, LAN9255 support\n\t* GigaDevice GD32E23x, GD32F1x0/3x0, GD32VF103 support\n\t* Nuvoton NPCX series support\n\t* onsemi RSL10 support\n\t* Raspberry Pi Pico RP2040 support\n\t* ST BlueNRG-LPS support\n\t* ST STM32 G05x, G06x, G0Bx, G0Cx, U57x, U58x, WB1x, WL5x support\n\t* ST STM32 G0, G4, L4, L4+, L5, WB, WL OTP support\n\nBoard, Target, and Interface Configuration Scripts:\n\t* Ampere Computing eMAG8180, Altra (\"Quicksilver\") and Altra Max (\"Mystique\") board config\n\t* Cadence KC705 FPGA (Xtensa Development Platform) via JTAG and ADIv5 DAP board config\n\t* Digilent Nexys Video board config\n\t* Espressif ESP32 ETHERNET-KIT and WROVER-KIT board config\n\t* Espressif ESP32 via ESP USB Bridge generic board config\n\t* Espressif ESP32-S2 Kaluga 1 board config\n\t* Espressif ESP32-S2 with ESP USB Bridge board config\n\t* Espressif ESP32-S3 example board config\n\t* Kontron SMARC-sAL28 board config\n\t* LambdaConcept ECPIX-5 board config\n\t* Microchip ATSAMA5D27-SOM1-EK1 board config\n\t* Microchip EVB-LAN9255 board config\n\t* Microchip SAME51 Curiosity Nano board config\n\t* NXP FRDM-K64F, LS1046ARDB and LS1088ARDB board config\n\t* NXP RT6XX board config\n\t* Olimex H405 board config\n\t* Radiona ULX3S board config\n\t* Raspberry Pi 3 and Raspberry Pi 4 model B board config\n\t* Raspberry Pi Pico-Debug board config\n\t* Renesas R-Car V3U Falcon board config\n\t* ST BlueNRG-LPS steval-idb012v1 board config\n\t* ST NUCLEO-8S208RB board config\n\t* ST NUCLEO-G031K8, NUCLEO-G070RB, NUCLEO-G071RB board config\n\t* ST NUCLEO-G431KB, NUCLEO-G431RB, NUCLEO-G474RE board config\n\t* ST STM32MP13x-DK board config\n\t* TI AM625 EVM, AM642 EVM and AM654 EVM board config\n\t* TI J721E EVM, J721S2 EVM and J7200 EVM board config\n\t* Ampere Computing eMAG, Altra (\"Quicksilver\") and Altra Max (\"Mystique\") target config\n\t* Cadence Xtensa generic and Xtensa VDebug target config\n\t* Broadcom BCM2711, BCM2835, BCM2836 and BCM2837 target config\n\t* Espressif ESP32, ESP32-S2 and ESP32-S3 target config\n\t* Microchip ATSAMA5D2 series target config\n\t* NanoXplore NG-Ultra SoC target config\n\t* NXP IMX8QM target config\n\t* NXP LS1028A, LS1046A and LS1088A target config\n\t* NXP RT600 (Xtensa HiFi DSP) target config\n\t* onsemi RSL10 target config\n\t* Raspberry Pi Pico RP2040 target config\n\t* Renesas R8A779A0 V3U target config\n\t* Renesas RZ/Five target config\n\t* Renesas RZ/G2 MPU family target config\n\t* Rockchip RK3399 target config\n\t* ST BlueNRG-LPS target config\n\t* ST STM32MP13x target config\n\t* TI AM625, AM654, J721E and J721S2 target config\n\t* Ashling Opella-LD interface config\n\t* Aspeed AST2600 linuxgpiod based interface config\n\t* Blinkinlabs JTAG_Hat interface config\n\t* Cadence Virtual Debug (vdebug) interface config\n\t* Espressif ESP32-S2 Kaluga 1 board's interface config\n\t* Espressif USB Bridge jtag interface config\n\t* Infineon DAP miniWiggler V3 interface config\n\t* PLS SPC5 interface config\n\t* Tigard interface config\n\t* Lattice MachXO3 family FPGA config\n\nServer Layer:\n\t* GDB: add per-target remote protocol extensions\n\t* GDB: more 'Z' packets support\n\t* IPDBG JtagHost server functionality\n\t* semihosting: I/O redirection to TCP server\n\t* telnet: support for command's autocomplete\n\nRTOS:\n\t* 'none' rtos support\n\t* Zephyr rtos support\n\nDocumentation:\n\nBuild and Release:\n\t* Add json extension to jimtcl build\n\t* Drop dependency from libusb0\n\t* Drop repository repo.or.cz for submodules\n\t* Move gerrit to https://review.openocd.org/\n\t* Require autoconf 2.69 or newer\n\t* Update jep106 to revision JEP106BF.01\n\t* Update jimtcl to version 0.81\n\t* Update libjaylink to version 0.3.1\n\t* New configure flag '--enable-jimtcl-maintainer' for jimtcl build\n\n\nThis release also contains a number of other important functional and\ncosmetic bugfixes. For more details about what has changed since the\nlast release, see the git repository history:\n\nhttp://sourceforge.net/p/openocd/code/ci/v0.12.0/log/?path=\n\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.2.0",
    "content": "The OpenOCD 0.2.0 source archive release includes numerous improvements\nthat were made since the initial 0.1.0 source archive release.  Many\ncontributors helped make this release a great success, and the community\nof developers and maintainers look forward to any response.\n\nIn addition to the list of changes below, countless bug fixing and\ncleaning was performed across the tree.  Various TCL command parameters\nmust past stricter value checks, and many more error conditions have\nbeen handled correctly.  These efforts helped to make the 0.2.0 release\nmore stable and robust, though some changes may expose latent bugs in\nyour existing configuration scripts.\n\nThis release does not maintain backward compatibility in all respects,\nso some target or configuration scripts may need to be updated.  In some\ncases, you may also see warnings; resolve those, because they indicate\ncommands that will be removed in the future.\n\nThe following areas of OpenOCD functionality changed in this release:\n\nJTAG Layer:\n- Improves modularity: core, TCL, driver commands, and interface have\n  been separated, encapsulated, and documented for developers.  Mostly.\n- Improves JTAG TAP transition tables:\n   * Makes TAP paths variable length, rather than being fixed at 7 steps.\n   * Fixes problems with some targets that did not like longer paths.\n- Improves JTAG driver/minidriver modularity and encapsulation.\n- New drivers:\n   * Adds stub minidriver for developing new embedded JTAG interfaces.\n- Improves drivers:\n   * ft2232+ftd2xx:\n      + Adds initial high-speed device support: --enable-ftd2xx-highspeed\n      + Supports more types of FTDI-based devices.\n   * jlink:\n      + Works with more versions of the firmware (v3 and newer)\n      + Supports dynamically detects device capabilities and limits\n   * vsllink:\n      + Supports very long scan chains\n   * amtjtagaccel:\n      + Fixes broken ID code detection problems.\n\nTarget Layer:\n- New devices: AVR, FA526\n- Improved support: ARM ADI, ARM11, MIPS\n- Numerous other bug fixes and improvements\n\nFlash Layer:\n- Improved drivers: mflash\n- New drivers: AT91SAM3, AVR, Davinci NAND\n\nBoard, Interface, and Target Configuration Scripts:\n- Many new and improved targets and boards are now available.\n- Better separation of \"board\" and \"target\" configuration\n- Moved all TCL files to top-level \"tcl\" directory in the source tree\n- Installation moved from '$pkglibdir/' to '$pkgdatadir/scripts/'.\n- Site-specific files should be installed under '$pkgdatadir/site/';\n  files that exist this tree will be used in preference to default\n  distribution configurations in '$pkgdatadir/scripts/'.\n\nDocumentation:\n- Updated User Guide:     http://openocd.berlios.de/doc/html/index.html\n   * Partially re-written and re-organized.\n   * Standardized presentation for all commands.\n   * Covers many drivers and commands that were previously omitted.\n   * New index for commands and drivers.\n- Added Developer Manual: http://openocd.berlios.de/doc/doxygen/index.html\n   * Now includes architecture, technical primers, style guides, and more.\n   * Available in-tree and on-line.\n\nBuild and Release:\n- Increased configuration and compilation warning coverage.\n   * Use --disable-werror to work around build errors caused by warnings.\n- Use libtool to produce helper libraries as a step toward \"libopenocd\".\n- New processes and scripting to facilitate future source releases.\n\nFor more details about what has changed since 0.1.0, see the ChangeLog\nassociated with this release.\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.3.0",
    "content": "This file should include highlights of the changes made in the\nOpenOCD openocd-0.3.0 source archive release.  See the repository\nhistory for details about what changed, including bugfixes and\nother issues not mentioned here.\n\nJTAG Layer:\n    FT2232H (high speed USB) support doesn't need separate configuration\n    New FT2232H JTAG adapters:  Amontec, Olimex, Signalyzer\n    New reset_config options for SRST gating the JTAG clock (or not)\n    TAP declaration no longer requires ircapture and mask attributes\n    Scan chain setup should be more robust, with better diagnostics\n    New TAP events:\n\t\"post-reset\" for TAP-invariant setup code (TAPs not usable yet)\n\t\"setup\" for use once TAPs are addressable (e.g. with ICEpick)\n    Overridable Tcl \"init_reset\" and \"jtag_init\" procedures\n    Simple \"autoprobe\" mechanism to help simplify server setup\n\nBoundary Scan:\n    SVF bugfixes ... parsing fixes, better STATE switch conformance\n    XSVF bugfixes ... be more correct, handle Xilinx tool output\n\nTarget Layer:\n    Warn on use of obsolete numeric target IDs\n    New commands for use with Cortex-M3 processors:\n\t\"cortex_m3 disassemble\" ... Thumb2 disassembly (UAL format)\n\t\"cortex_m3 vector_catch\" ... traps certain hardware faults\n\t\twithout tying up breakpoint resources\n    If you're willing to help debug it\n\tVERY EARLY Cortex-A8 and ARMv7A support\n\tUpdated BeagleBoard.org hardware support\n\tyou may need to explicitly \"reset\" after connect-to-Beagle\n    New commands for use with XScale processors: \"xscale vector_table\"\n    ARM\n\tbugfixes to single-stepping Thumb code\n\tETM: unavailable registers are not listed\n\tETB, ETM: report actual hardware status\n    ARM9\n\tname change:  \"arm9 vector_catch\" not \"arm9tdmi vector_catch\"\n    ARM11\n\tsingle stepping support for i.MX31\n\tbugfix for missing \"arm11\" prefix on \"arm11 memwrite ...\"\n    GDB support\n\tgdb_attach command is gone\n\nFlash Layer:\n    The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips\n    New drivers:\n\tlpc2900, for NXP LPC2900 chips (ARM968 based)\n\tmx3_nand, for imx31\n    New \"last\" flag for NOR \"flash erase_sector\" and \"flash protect\"\n    The \"nand erase N\" command now erases all of bank N\n    Speed up davinci_nand by about 3x\n\nBoard, Target, and Interface Configuration Scripts:\n    Amontec JTAGkey2 support\n    Cleanup and additions for the TI/Luminary Stellaris scripts\n    LPC1768 target (and flash) support\n\tKeil MCB1700 eval board\n    Samsung s3c2450\n\tMini2440 board\n    Numeric TAP and Target identifiers now trigger warnings\n    PXA255 partially enumerates\n\nDocumentation:\n    Capture more debugging and setup advice\n    Notes on target source code changes that may help debugging\n\nBuild and Release:\n    Repository moved from SVN at Berlios to GIT at SourceForge\n    Clean builds on (32-bit) Cygwin\n    Clean builds on 64-bit MinGW\n\nFor more details about what has changed since the last release,\nsee the git repository history.  With gitweb, you can browse that\nin various levels of detail.\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.4.0",
    "content": "This file includes highlights of the changes made in the\nOpenOCD 0.4.0 source archive release.  See the repository\nhistory for details about what changed, including bugfixes\nand other issues not mentioned here.\n\nJTAG Layer:\n\tSupport KT-Link JTAG adapter.\n\tSupport USB-JTAG, Altera USB-Blaster and compatibles.\n\nBoundary Scan:\n\nTarget Layer:\n\tGeneral\n\t\t- Removed commands which have been obsolete for at least\n\t\t  a year (from both documentation and, sometimes, code).\n\t\t- new \"reset-assert\" event, for systems without SRST\n\tARM\n\t\t- supports \"reset-assert\" event (except on Cortex-M3)\n\t\t- renamed \"armv4_5\" command prefix as \"arm\"\n\t\t- recognize TrustZone \"Secure Monitor\" mode\n\t\t- \"arm regs\" command output changed\n\t\t- register names use \"sp\" not \"r13\"\n\t\t- add top-level \"mcr\" and \"mrc\" commands, replacing\n\t\t  various core-specific operations\n\t\t- basic semihosting support (ARM7/ARM9 only, for now)\n\tARM11\n\t\t- Should act much more like other ARM cores:\n\t\t   * Preliminary ETM and ETB hookup\n\t\t   * accelerated \"flash erase_check\"\n\t\t   * accelerated GDB memory checksum\n\t\t   * support \"arm regs\" command\n\t\t   * can access all core modes and registers\n\t\t   * watchpoint support\n\t\t- Shares some core debug code with Cortex-A8\n\tCortex-A8\n\t\t- Should act much more like other ARM cores:\n\t\t   * support \"arm regs\" command\n\t\t   * can access all core modes and registers\n\t\t   * watchpoint support\n\t\t- Shares some core debug code with ARM11\n\tCortex-M3\n\t\t- Exposed DWT registers like cycle counter\n\t\t- vector_catch settings not clobbered by resets\n\t\t- no longer interferes with firmware's fault handling\n\tETM, ETB\n\t\t- \"trigger_percent\" command moved ETM --> ETB\n\t\t- \"etm trigger_debug\" command added\n\tMIPS\n\t\t- use fastdata writes\n\tFreescale DSP563xx cores (partial support)\n\nFlash Layer:\n\t'flash bank' and 'nand device' take <bank_name> as first argument.\n\tWith this, flash/NAND commands allow referencing banks by name:\n\t\t- <bank_name>: reference the bank with its defined name\n\t\t- <driver_name>[.N]: reference the driver's Nth bank\n\tNew 'nand verify' command to check bank against an image file.\n\tThe \"flash erase_address\" command now rejects partial sectors;\n\t\tpreviously it would silently erase extra data.  If you\n\t\twant to erase the rest of the first and/or last sectors\n\t\tinstead of failing, you must pass an explicit \"pad\" flag.\n\tNew at91sam9 NAND controller driver.\n\tNew s3c64xx NAND controller driver.\n\nBoard, Target, and Interface Configuration Scripts:\n\tARM9\n\t\t- ETM and ETB hookup for iMX2* targets\n\tAdd $HOME/.openocd to the search path.\n\tHandle Rev C of LM3S811 eval boards.\n\t\t- use \"luminary-lm3s811.cfg\" for older boards\n\t\t- use \"luminary.cfg\" for RevC and newer\n\nCore Jim/TCL Scripting:\n\tNew 'usage' command to provide terse command help.\n\tImproved command 'help' command output (sorted and indented).\n\tImproved command handling:\n\t\t- Most boolean settings now accept any of the following:\n\t\t  on/off, enable/disable, true/false, yes/no, 1/0\n\t\t- More error checking and reporting.\n\nDocumentation:\n\tNew built-in command development documentation and primer.\n\nBuild and Release:\n\tUse --enable-doxygen-pdf to build PDF developer documentation.\n\tConsider upgrading to libftdi 0.17 if you use that library; it\n\t\tincludes bugfixes which improve FT2232H support.\n\nFor more details about what has changed since the last release,\nsee the git repository history.  With gitweb, you can browse that\nin various levels of detail.\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.5.0",
    "content": "This file includes highlights of the changes made in the\nOpenOCD 0.5.0 source archive release.  See the repository\nhistory for details about what changed, including bugfixes\nand other issues not mentioned here.\n\nJTAG Layer:\n\tNew driver for \"Bus Pirate\"\n\tRename various commands so they're not JTAG-specific\n\t   There are migration procedures for most of these, but you should\n\t   convert your scripts to the new names, since those procedures\n\t   will not be around forever.\n\t\tjtag jinterface ... is now adapter_name\n\t   \tjtag_khz\t... is now adapter_khz\n\t\tjtag_nsrst_delay ... is now adapter_nsrst_delay\n\t\tjtag_nsrst_assert_width ... is now adapter_nsrst_assert_width\n\tSupport Voipac VPACLink JTAG Adapter.\n\nBoundary Scan:\n\nTransport framework core ... supporting future work for SWD, SPI, and other\nnon-JTAG ways to debug targets or program flash.\n\nTarget Layer:\n\tARM:\n\t\t- basic semihosting support for ARMv7M.\n\t\t- renamed \"armv7m\" command prefix as \"arm\"\n\tMIPS:\n\t\t- \"ejtag_srst\" variant removed. The same functionality is\n\t\t  obtained by using \"reset_config none\".\n\t\t- added PIC32MX software reset support, this means srst is not\n\t\t  required to be connected anymore.\n\tOTHER:\n\t\t- preliminary AVR32 AP7000 support.\n\nFlash Layer:\n\tNew \"stellaris recover\" command, implements the procedure\n\t\tto recover locked devices (restoring non-volatile\n\t\tstate to the factory defaults, including erasing\n\t\tthe flash and its protection bits, and possibly\n\t\tre-enabling hardware debugging).\n\tPIC32MX now uses algorithm for flash programming, this\n\t\thas increased the performance by approx 96%.\n\tNew 'pic32mx unlock' cmd to remove readout protection.\n\tNew STM32 Value Line Support.\n\tNew 'virtual' flash driver, used to associate other addresses\n\t\twith a flash bank. See pic32mx.cfg for usage.\n\tNew iMX27 NAND flash controller driver.\n\nBoard, Target, and Interface Configuration Scripts:\n\tSupport IAR LPC1768 kickstart board (by Olimex)\n\tSupport Voipac PXA270/PXA270M module.\n\tNew $PARPORTADDR tcl variable used to change default\n\t\tparallel port address used.\n\tRemove lm3s811.cfg; use \"stellaris.cfg\" instead\n\nCore Jim/TCL Scripting:\n\tNew \"add_script_search_dir\" command, behaviour is the same\n\t\tas the \"-s\" cmd line option.\n\nDocumentation:\n\nBuild and Release:\n\nFor more details about what has changed since the last release,\nsee the git repository history.  With gitweb, you can browse that\nin various levels of detail.\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.6.0",
    "content": "This file includes highlights of the changes made in the\nOpenOCD  source archive release.  See the\nrepository history for details about what changed, including\nbugfixes and other issues not mentioned here.\n\nJTAG Layer:\n\tNew STLINK V1/V2 JTAG/SWD adapter support.\n\tNew OSJTAG adapter support.\n\tNew Tincantools Flyswatter2 support.\n\tImproved ULINK driver.\n\tImproved RLINK driver.\n\tSupport for adapters based on FT232H chips.\n\tNew experimental driver for FTDI based adapters, using libusb-1.0 in asynchronous mode.\n\nBoundary Scan:\n\nTarget Layer:\n\tNew Cortex-M0 support.\n\tNew Cortex-M4 support.\n\tImproved Working area algorithm.\n\tNew RTOS support. Currently linux, FreeRTOS, ThreadX and eCos.\n\tConnecting under reset to Cortex-Mx and MIPS chips.\n\nFlash Layer:\n\tNew SST39WF1601 support.\n\tNew EN29LV800BB support.\n\tNew async algorithm support for selected targets, stm32, stellaris and pic32.\n\tNew Atmel SAM3S, SAM3N support.\n\tNew ST STM32L support.\n\tNew Microchip PIC32MX1xx/2xx support.\n\tNew Freescale Kinetis K40 support.\n\nBoard, Target, and Interface Configuration Scripts:\n\tSupport Dangerous Prototypes Bus Blaster.\n\tSupport ST SPEAr Family.\n\tSupport Gumstix Verdex boards.\n\tSupport TI Beaglebone.\n\nDocumentation:\n\tImproved HACKING info for submitting patches.\n\tFixed numerous broken links.\n\nBuild and Release:\n\nFor more details about what has changed since the last release,\nsee the git repository history.  With gitweb, you can browse that\nin various levels of detail.\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.7.0",
    "content": "This file includes highlights of the changes made in the\nOpenOCD  source archive release.  See the\nrepository history for details about what changed, including\nbugfixes and other issues not mentioned here.\n\nJTAG Layer:\n\tNew TI ICDI adapter support.\n\tSupport Latest OSBDM firmware.\n\tImproved MIPS EJTAG Support.\n\nBoundary Scan:\n\nTarget Layer:\n\tNew ARMv7R and Cortex-R4 support.\n\tAdded ChibiOS/RT support.\n\nFlash Layer:\n\tNew NXP LPC1850 support.\n\tNew NXP LPC4300 support.\n\tNew NXP SPIFI support.\n\tNew Energy Micro EFM32 support.\n\tNew ST STM32W support.\n\tNew ST STM32f2 write protection and lock/unlock support.\n\tAbility to override STM32 flash bank size.\n\nBoard, Target, and Interface Configuration Scripts:\n\tSupport Freescale i.MX6 series targets.\n\nDocumentation:\n\tNew MIPS debugging info.\n\nBuild and Release:\n\nFor more details about what has changed since the last release,\nsee the git repository history.  With gitweb, you can browse that\nin various levels of detail.\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.8.0",
    "content": "This file includes highlights of the changes made in the OpenOCD\nsource archive release.\n\nJTAG Layer:\n\t* New CMSIS-DAP driver\n\t* Andes AICE debug adapter support\n\t* New OpenJTAG driver\n\t* New BCM2835 (RaspberryPi) driver\n\t* JTAG VPI client driver (for OpenRISC Reference Platform SoC)\n\t* Xilinx BSCAN_* for OpenRISC support\n\t* ST-LINKv2-1 support\n\t* ST-LINKv2 SWO tracing support (UART emulation)\n\t* JLink-OB (onboard) support\n\t* Altera USB Blaster driver rewrite, initial Blaster II\n\t  support\n\t* ULINK driver ported to libusb-1.0, OpenULINK build fixes\n\t* Support up to 64 bit IR lengths\n\t* SVF playback (FPGA programming) fixes\n\t* \"ftdi\" interface driver got extensive testing and is now\n\t  recommended over the old ft2232 implementation\n\nBoundary Scan:\n\nTarget Layer:\n\t* New target: Andes nds32\n\t* New target: OpenRISC OR1K\n\t* New target: Intel Quark X10xx\n\t* MIPS EJTAG 1.5/2.0 support\n\t* MIPS speed improvements\n\t* Cortex-M, Cortex-A (MEM-AP, APB-AP) targets working with BE\n\t  hosts now\n\t* XScale vector_catch support, reset fixes\n\t* dsp563xx ad-hoc breakpoint/watchpoint support\n\t* RTOS support for embKernel\n\t* Target profiling improvements\n\t* Memory access functions testbench\n\nFlash Layer:\n\t* STM32 family sync with reference manuals, other bugfixes\n\t* STM32F401, STM32F07x support\n\t* Atmel SAM4L, SAMG5x support\n\t* at91sam3sd8{a,b}, at91sam3s8{a,b,c}, at91sam4s,\n\t  at91sam3n0{a,b,0a,0b} support, bugfixes\n\t* Atmel SAMD support\n\t* Milandr 1986ВЕ* support\n\t* Kinetis KL, K21 support\n\t* Nuvoton NuMicro MINI5{1,2,4} support\n\t* Nuvoton NUC910 series support\n\t* NXP LPC43xx, LPC2000 fixes\n\t* NXP LPC800, LPC810 support\n\t* More ATmega parts supported\n\t* Fujitsu MB9Ax family support\n\t* EFM32 Wonder Gecko family support\n\t* Nordic nRF51 support\n\nBoard, Target, and Interface Configuration Scripts:\n\t* STM32W108xx generic target config\n\t* STM32F429 discovery board config\n\t* STM32 Nucleo boards configs\n\t* DENX M53EVK board config\n\t* Altera Cyclone V SoC, SoCkit config\n\t* New TI Launchpads board configs\n\t* TI am43xx devices, AM437x GP EVM, AM438x ePOS EVM board\n\t  configs\n\t* Marvell Armada 370 family initial support\n\t* TI TMDX570LS31USB (TMS570, Cortex-R4) support scripts\n\t* Freescale FRDM-KL25Z, KL46Z board configs\n\t* Digilent Zedboard config\n\t* Asus RT-N16, Linksys WRT54GL, BT HomeHub board configs\n\t* Atmel Xplained initial support\n\t* Broadcom bcm28155_ap board config\n\t* TUMPA, TUMPA Lite interface configs\n\t* Digilent JTAG-SMT2 interface config\n\t* New RAM testing functions\n\t* Easy-to-use firmware recovery helpers targetting ordinary\n\t  users with common equipment\n\nServer Layer:\n\t* Auto-generation of GDB target description for ARMv7-M,\n\t  ARM4, nds32, OR1K, Quark\n\t* GDB File-I/O Remote Protocol extension support\n\t* Default GDB flashing events handlers to initialise and reset\n\t  the target automatically when \"load\" is used\n\nDocumentation:\n\t* Extensive README* changes\n\t* The official User's Guide was proofread\n\t* Example cross-build script\n\t* RTOS documentation improvements\n\t* Tcl RPC documentation and examples added\n\nBuild and Release:\n\t* *BSD, OS X, clang, ARM, windows build fixes\n\t* New pkg-config support changes the way libusb (and other\n\t  dependencies) are handled. Many adapter drivers are now\n\t  selected automatically during the configure stage.\n\n\nThis release also contains a number of other important functional and\ncosmetic bugfixes. For more details about what has changed since the\nlast release, see the git repository history:\n\nhttp://sourceforge.net/p/openocd/code/ci/v0.8.0/log/?path=\n\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/NEWS-0.9.0",
    "content": "This file includes highlights of the changes made in the OpenOCD\nsource archive release.\n\nJTAG Layer:\n\t* SWD support with FTDI, Versaloon, J-Link, sysfsgpio\n\t* CMSIS-DAP massive speed and stability improvements\n\t* Versaloon driver ported to libusb-1.0\n\t* STLink can reestablish communication with a target that was\n          disconnected or rebooted\n\t* STLink FAULT and WAIT SWD handling improved\n\t* New hla_serial command to distinguish between several HLA\n          adapters attached to a single machine\n\t* Serial number support for CMSIS-DAP and J-Link adapters\n\t* Support for more J-Link adapters\n\t* TAP autoprobing improvements\n\t* Big speedup for SVF playback with USB Blaster\n\nBoundary Scan:\n\nTarget Layer:\n\t* Stability improvements for targets that get disconnected or\n          rebooted during a debug session\n\t* MIPS speed and reliability improvements\n\t* MIPS 1.5/2.0 fixes\n\t* ARMv7-R improvements\n\t* Cortex-A improvements, A7, A15 MPCores support\n\t* FPU support for ARMv7-M (Cortex-M4F)\n\t* TPIU/ITM support (including SWO/SWV tracing), can be\n          captured with external tools or STLink\n\t* JTAG Serial Port (Advanced Debug System softcore) support\n\t* Profiling support for OpenRISC\n\t* ChibiOS/RT 3.0 support (with and without FPU)\n\t* FreeRTOS current versions support\n\t* Freescale MQX RTOS support\n\t* GDB target description support for MIPS\n\t* The last created target is auto-selected as the current\n\nFlash Layer:\n\t* nRF51 async loader to improve flashing performance and stability\n\t* Cypress PSoC 41xx/42xx and CCG1 families flash driver\n\t* Silabs SiM3 family flash driver\n\t* Marvell Wireless Microcontroller SPI flash driver\n\t* Kinetis mass erase (part unsecuring) implemented\n\t* lpcspifi stability fixes\n\t* STM32 family sync with reference manuals, L0 support, bugfixes\n\t* LPC2000 driver automatically determines part and flash size\n\t* NXP LPC11(x)xx, LPC13xx, LPC15xx, LPC8xx, LPC5410x, LPC407x support\n\t* Atmel SAMD, SAMR, SAML21 devices support\n\t* Atmel SAM4E16 support\n\t* ZeroGecko family support\n\t* TI Tiva C Blizzard and Snowflake families support\n\t* Nuvoton NuMicro M051 support\n\t* EZR32 support in EFM32 driver\n\nBoard, Target, and Interface Configuration Scripts:\n\t* Normal target configs can work with HLA (STLink, ICDI) adapters\n\t* STM32 discovery and Nucleo boards configs\n\t* Gumstix AeroCore board config\n\t* General Plus GP326XXXA target config\n\t* Micrel KS869x target config\n\t* ASUS RT-N66U board config\n\t* Atmel SAM4E-EK board config\n\t* Atmel AT91SAM4L proper reset handling implemented\n\t* TI OMAP/AM 3505, 3517 target configs\n\t* nRF51822-mKIT board config\n\t* RC Module К1879ХБ1Я target config\n\t* TI TMDX570LS20SUSB board config\n\t* TI TMS570 USB Kit board config\n\t* TI CC2538, CC26xx target configs\n\t* TI AM437x major config improvements, DDR support\n\t* TI AM437X IDK board config\n\t* TI SimpleLink Wi-Fi CC3200 LaunchPad configs\n\t* Silicon Labs EM357, EM358 target configs\n\t* Infineon XMC1000, XMC4000 family targets and boards configs\n\t* Atheros AR9331 target config\n\t* TP-LINK TL-MR3020 board config\n\t* Alphascale asm9260t target and eval kit configs\n\t* Olimex SAM7-LA2 (AT91SAM7A2) board config\n\t* EFM32 Gecko boards configs\n\t* Spansion FM4 target and SK-FM4-176L-S6E2CC board configs\n\t* LPC1xxx target configs were restructured\n\t* IoT-LAB debug adapter config\n\t* DP BusBlaster KT-Link compatible config\n\nServer Layer:\n\t* Polling period can be configured\n\t* \"shutdown\" command has an immediate effect\n\t* The \"program\" command doesn't lead to a shutdown by\n          default, use optional \"exit\" parameter for the old behaviour\n\t* Proper OS signal handling was implemented\n\t* Async target notifications for the Tcl RPC\n\nDocumentation:\n\nBuild and Release:\n\n\nThis release also contains a number of other important functional and\ncosmetic bugfixes. For more details about what has changed since the\nlast release, see the git repository history:\n\nhttp://sourceforge.net/p/openocd/code/ci/v0.9.0/log/?path=\n\n\nFor older NEWS, see the NEWS files associated with each release\n(i.e. NEWS-<version>).\n\nFor more information about contributing test reports, bug fixes, or new\nfeatures and device support, please read the new Developer Manual (or\nthe BUGS and PATCHES.txt files in the source archive).\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README",
    "content": "Welcome to OpenOCD!\n===================\n\nOpenOCD provides on-chip programming and debugging support with a\nlayered architecture of JTAG interface and TAP support including:\n\n- (X)SVF playback to facilitate automated boundary scan and FPGA/CPLD\n  programming;\n- debug target support (e.g. ARM, MIPS): single-stepping,\n  breakpoints/watchpoints, gprof profiling, etc;\n- flash chip drivers (e.g. CFI, NAND, internal flash);\n- embedded TCL interpreter for easy scripting.\n\nSeveral network interfaces are available for interacting with OpenOCD:\ntelnet, TCL, and GDB. The GDB server enables OpenOCD to function as a\n\"remote target\" for source-level debugging of embedded systems using\nthe GNU GDB program (and the others who talk GDB protocol, e.g. IDA\nPro).\n\nThis README file contains an overview of the following topics:\n\n- quickstart instructions,\n- how to find and build more OpenOCD documentation,\n- list of the supported hardware,\n- the installation and build process,\n- packaging tips.\n\n\n============================\nQuickstart for the impatient\n============================\n\nIf you have a popular board then just start OpenOCD with its config,\ne.g.:\n\n  openocd -f board/stm32f4discovery.cfg\n\nIf you are connecting a particular adapter with some specific target,\nyou need to source both the jtag interface and the target configs,\ne.g.:\n\n  openocd -f interface/ftdi/jtagkey2.cfg -c \"transport select jtag\" \\\n          -f target/ti_calypso.cfg\n\n  openocd -f interface/stlink.cfg -c \"transport select hla_swd\" \\\n          -f target/stm32l0.cfg\n\nAfter OpenOCD startup, connect GDB with\n\n  (gdb) target extended-remote localhost:3333\n\n\n=====================\nOpenOCD Documentation\n=====================\n\nIn addition to the in-tree documentation, the latest manuals may be\nviewed online at the following URLs:\n\n  OpenOCD User's Guide:\n    http://openocd.org/doc/html/index.html\n\n  OpenOCD Developer's Manual:\n    http://openocd.org/doc/doxygen/html/index.html\n\nThese reflect the latest development versions, so the following section\nintroduces how to build the complete documentation from the package.\n\nFor more information, refer to these documents or contact the developers\nby subscribing to the OpenOCD developer mailing list:\n\n\topenocd-devel@lists.sourceforge.net\n\nBuilding the OpenOCD Documentation\n----------------------------------\n\nBy default the OpenOCD build process prepares documentation in the\n\"Info format\" and installs it the standard way, so that \"info openocd\"\ncan access it.\n\nAdditionally, the OpenOCD User's Guide can be produced in the\nfollowing different formats:\n\n  # If PDFVIEWER is set, this creates and views the PDF User Guide.\n  make pdf && ${PDFVIEWER} doc/openocd.pdf\n\n  # If HTMLVIEWER is set, this creates and views the HTML User Guide.\n  make html && ${HTMLVIEWER} doc/openocd.html/index.html\n\nThe OpenOCD Developer Manual contains information about the internal\narchitecture and other details about the code:\n\n  # NB! make sure doxygen is installed, type doxygen --version\n  make doxygen && ${HTMLVIEWER} doxygen/index.html\n\n\n==================\nSupported hardware\n==================\n\nJTAG adapters\n-------------\n\nAM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835,\nBus Blaster, Buspirate, Cadence DPI, Cadence vdebug, Chameleon, CMSIS-DAP,\nCortino, Cypress KitProg, DENX, Digilent JTAG-SMT2, DLC 5, DLP-USB1232H,\nembedded projects, Espressif USB JTAG Programmer,\neStick, FlashLINK, FlossJTAG, Flyswatter, Flyswatter2,\nFTDI FT232R, Gateworks, Hoegl, ICDI, ICEBear, J-Link, JTAG VPI, JTAGkey,\nJTAGkey2, JTAG-lock-pick, KT-Link, Linux GPIOD, Lisa/L, LPC1768-Stick,\nMellanox rshim, MiniModule, NGX, Nuvoton Nu-Link, Nu-Link2, NXHX, NXP IMX GPIO,\nOOCDLink, Opendous, OpenJTAG, Openmoko, OpenRD, OSBDM, Presto, Redbee,\nRemote Bitbang, RLink, SheevaPlug devkit, Stellaris evkits,\nST-LINK (SWO tracing supported), STM32-PerformanceStick, STR9-comStick,\nsysfsgpio, Tigard, TI XDS110, TUMPA, Turtelizer, ULINK, USB-A9260, USB-Blaster,\nUSB-JTAG, USBprog, VPACLink, VSLLink, Wiggler, XDS100v2, Xilinx XVC/PCIe,\nXverve.\n\nDebug targets\n-------------\n\nARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M),\nFA526, Feroceon/Dragonite, XScale.\nARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64),\nESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, RISC-V, ST STM8,\nXtensa.\n\nFlash drivers\n-------------\n\nADUC702x, AT91SAM, AT91SAM9 (NAND), ATH79, ATmega128RFA1, Atmel SAM, AVR, CFI,\nDSP5680xx, EFM32, EM357, eSi-RISC, eSi-TSMC, EZR32HG, FM3, FM4, Freedom E SPI,\nGD32, i.MX31, Kinetis, LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPC3180, LPC32xx,\nLPCSPIFI, Marvell QSPI, MAX32, Milandr, MXC, NIIET, nRF51, nRF52 , NuMicro,\nNUC910, Nuvoton NPCX, onsemi RSL10, Orion/Kirkwood, PIC32mx, PSoC4/5LP/6,\nRaspberry RP2040, Renesas RPC HF and SH QSPI,\nS3C24xx, S3C6400, SiM3x, SiFive Freedom E, Stellaris, ST BlueNRG, STM32,\nSTM32 QUAD/OCTO-SPI for Flash/FRAM/EEPROM, STMSMI, STR7x, STR9x, SWM050,\nTI CC13xx, TI CC26xx, TI CC32xx, TI MSP432, Winner Micro w600, Xilinx XCF,\nXMC1xxx, XMC4xxx.\n\n\n==================\nInstalling OpenOCD\n==================\n\nA Note to OpenOCD Users\n-----------------------\n\nIf you would rather be working \"with\" OpenOCD rather than \"on\" it, your\noperating system or JTAG interface supplier may provide binaries for\nyou in a convenient-enough package.\n\nSuch packages may be more stable than git mainline, where\nbleeding-edge development takes place. These \"Packagers\" produce\nbinary releases of OpenOCD after the developers produces new \"release\"\nversions of the source code. Previous versions of OpenOCD cannot be\nused to diagnose problems with the current release, so users are\nencouraged to keep in contact with their distribution package\nmaintainers or interface vendors to ensure suitable upgrades appear\nregularly.\n\nUsers of these binary versions of OpenOCD must contact their Packager to\nask for support or newer versions of the binaries; the OpenOCD\ndevelopers do not support packages directly.\n\nA Note to OpenOCD Packagers\n---------------------------\n\nYou are a PACKAGER of OpenOCD if you:\n\n- Sell dongles and include pre-built binaries;\n- Supply tools or IDEs (a development solution integrating OpenOCD);\n- Build packages (e.g. RPM or DEB files for a GNU/Linux distribution).\n\nAs a PACKAGER, you will experience first reports of most issues.\nWhen you fix those problems for your users, your solution may help\nprevent hundreds (if not thousands) of other questions from other users.\n\nIf something does not work for you, please work to inform the OpenOCD\ndevelopers know how to improve the system or documentation to avoid\nfuture problems, and follow-up to help us ensure the issue will be fully\nresolved in our future releases.\n\nThat said, the OpenOCD developers would also like you to follow a few\nsuggestions:\n\n- Send patches, including config files, upstream, participate in the\n  discussions;\n- Enable all the options OpenOCD supports, even those unrelated to your\n  particular hardware;\n- Use \"ftdi\" interface adapter driver for the FTDI-based devices.\n\n\n================\nBuilding OpenOCD\n================\n\nThe INSTALL file contains generic instructions for running 'configure'\nand compiling the OpenOCD source code. That file is provided by\ndefault for all GNU autotools packages. If you are not familiar with\nthe GNU autotools, then you should read those instructions first.\n\nThe remainder of this document tries to provide some instructions for\nthose looking for a quick-install.\n\nOpenOCD Dependencies\n--------------------\n\nGCC or Clang is currently required to build OpenOCD. The developers\nhave begun to enforce strict code warnings (-Wall, -Werror, -Wextra,\nand more) and use C99-specific features: inline functions, named\ninitializers, mixing declarations with code, and other tricks. While\nit may be possible to use other compilers, they must be somewhat\nmodern and could require extending support to conditionally remove\nGCC-specific extensions.\n\nYou'll also need:\n\n- make\n- libtool\n- pkg-config >= 0.23 or pkgconf\n\nOpenOCD uses jimtcl library; build from git can retrieve jimtcl as git\nsubmodule.\n\nAdditionally, for building from git:\n\n- autoconf >= 2.69\n- automake >= 1.14\n- texinfo >= 5.0\n\nOptional USB-based adapter drivers need libusb-1.0.\n\nOptional USB-Blaster, ASIX Presto and OpenJTAG interface adapter\ndrivers need:\n  - libftdi: http://www.intra2net.com/en/developer/libftdi/index.php\n\nOptional CMSIS-DAP adapter driver needs HIDAPI library.\n\nOptional linuxgpiod adapter driver needs libgpiod library.\n\nOptional J-Link adapter driver needs libjaylink library.\n\nOptional ARM disassembly needs capstone library.\n\nOptional development script checkpatch needs:\n\n- perl\n- python\n- python-ply\n\nPermissions delegation\n----------------------\n\nRunning OpenOCD with root/administrative permissions is strongly\ndiscouraged for security reasons.\n\nFor USB devices on GNU/Linux you should use the contrib/60-openocd.rules\nfile. It probably belongs somewhere in /etc/udev/rules.d, but\nconsult your operating system documentation to be sure. Do not forget\nto add yourself to the \"plugdev\" group.\n\nFor parallel port adapters on GNU/Linux and FreeBSD please change your\n\"ppdev\" (parport* or ppi*) device node permissions accordingly.\n\nFor parport adapters on Windows you need to run install_giveio.bat\n(it's also possible to use \"ioperm\" with Cygwin instead) to give\nordinary users permissions for accessing the \"LPT\" registers directly.\n\nCompiling OpenOCD\n-----------------\n\nTo build OpenOCD, use the following sequence of commands:\n\n  ./bootstrap (when building from the git repository)\n  ./configure [options]\n  make\n  sudo make install\n\nThe 'configure' step generates the Makefiles required to build\nOpenOCD, usually with one or more options provided to it. The first\n'make' step will build OpenOCD and place the final executable in\n'./src/'. The final (optional) step, ``make install'', places all of\nthe files in the required location.\n\nTo see the list of all the supported options, run\n  ./configure --help\n\nCross-compiling Options\n-----------------------\n\nCross-compiling is supported the standard autotools way, you just need\nto specify the cross-compiling target triplet in the --host option,\ne.g. for cross-building for Windows 32-bit with MinGW on Debian:\n\n  ./configure --host=i686-w64-mingw32 [options]\n\nTo make pkg-config work nicely for cross-compiling, you might need an\nadditional wrapper script as described at\n\n  https://autotools.io/pkgconfig/cross-compiling.html\n\nThis is needed to tell pkg-config where to look for the target\nlibraries that OpenOCD depends on. Alternatively, you can specify\n*_CFLAGS and *_LIBS environment variables directly, see \"./configure\n--help\" for the details.\n\nFor a more or less complete script that does all this for you, see\n\n  contrib/cross-build.sh\n\nParallel Port Dongles\n---------------------\n\nIf you want to access the parallel port using the PPDEV interface you\nhave to specify both --enable-parport AND --enable-parport-ppdev, since\nthe later option is an option to the parport driver.\n\nThe same is true for the --enable-parport-giveio option, you have to\nuse both the --enable-parport AND the --enable-parport-giveio option\nif you want to use giveio instead of ioperm parallel port access\nmethod.\n\n\n==========================\nObtaining OpenOCD From GIT\n==========================\n\nYou can download the current GIT version with a GIT client of your\nchoice from the main repository:\n\n   git://git.code.sf.net/p/openocd/code\n\nYou may prefer to use a mirror:\n\n   http://repo.or.cz/r/openocd.git\n   git://repo.or.cz/openocd.git\n\nUsing the GIT command line client, you might use the following command\nto set up a local copy of the current repository (make sure there is no\ndirectory called \"openocd\" in the current directory):\n\n   git clone git://git.code.sf.net/p/openocd/code openocd\n\nThen you can update that at your convenience using\n\n   git pull\n\nThere is also a gitweb interface, which you can use either to browse\nthe repository or to download arbitrary snapshots using HTTP:\n\n   http://repo.or.cz/w/openocd.git\n\nSnapshots are compressed tarballs of the source tree, about 1.3 MBytes\neach at this writing.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README.Windows",
    "content": "Building OpenOCD for Windows\n----------------------------\n\nYou can build OpenOCD for Windows natively with either MinGW-w64/MSYS\nor Cygwin (plain MinGW might work with --disable-werror but is not\nrecommended as it doesn't provide enough C99 compatibility).\nAlternatively, one can cross-compile it using MinGW-w64 on a *nix\nhost. See README for the generic instructions.\n\nAlso, the MSYS2 project provides both ready-made binaries and an easy\nway to self-compile from their software repository out of the box.\n\nNative MinGW-w64/MSYS compilation\n-----------------------------\n\nAs MSYS doesn't come with pkg-config pre-installed, you need to add it\nmanually. The easiest way to do that is to download pkg-config-lite\nfrom:\n\n  http://sourceforge.net/projects/pkgconfiglite/\n\nThen simply unzip the archive to the root directory of your MinGW-w64\ninstallation.\n\nUSB adapters\n------------\n\nFor the adapters that use a HID-based protocol, e.g. CMSIS-DAP, you do\nnot need to perform any additional configuration.\n\nFor all the others you usually need to have WinUSB.sys (or\nlibusbK.sys) driver installed. Some vendor software (e.g. for\nST-LINKv2) does it on its own. For the other cases the easiest way to\nassign WinUSB to a device is to use the latest Zadig installer:\n\n  http://zadig.akeo.ie\n\nWhen using a composite USB device, it's often necessary to assign\nWinUSB.sys to the composite parent instead of the specific\ninterface. To do that one needs to activate an advanced option in the\nZadig installer.\n\nIf you need to use the same adapter with other applications that may\nrequire another driver, a solution for Windows Vista and above is to\nactivate the IgnoreHWSerNum registry setting for the USB device.\n\nThat setting forces Windows to associate the driver per port instead of\nper serial number, the same behaviour as when the device does not contain\na serial number. So different drivers can be installed for the adapter on\ndifferent ports and you just need to plug the adapter into the correct\nport depending on which application to use.\n\nFor more information, see:\n\n  https://learn.microsoft.com/en-us/windows-hardware/drivers/usbcon/usb-device-specific-registry-settings\n  http://www.ftdichip.com/Support/Knowledgebase/index.html?ignorehardwareserialnumber.htm\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/README.macOS",
    "content": "Building OpenOCD for macOS\n--------------------------\n\nThere are a few prerequisites you will need first:\n\n- Xcode (install from the AppStore)\n- Command Line Tools (install from Xcode -> Preferences -> Downloads)\n- Gentoo Prefix (http://www.gentoo.org/proj/en/gentoo-alt/prefix/bootstrap.xml)\n  or\n- Homebrew (http://mxcl.github.io/homebrew/)\n  or\n- MacPorts (http://www.macports.org/install.php)\n\n\nIf you're building manually you need Texinfo version 5.0 or later. The\nsimplest way to get it is to use Homebrew (brew install texinfo) and\nthen ``export PATH=/usr/local/opt/texinfo/bin:$PATH``.\n\n\nWith Gentoo Prefix you can build the release version or the latest\ndevel version (-9999) the usual way described in the Gentoo\ndocumentation. Alternatively, install the prerequisites and build\nmanually from the sources.\n\n\nWith Homebrew you can either run:\n  brew install [--HEAD] openocd (where optional --HEAD asks brew to\n                                 install the current git version)\n    or\n  brew install libtool automake libusb [hidapi] [libftdi]\n    (to install the needed dependencies and then proceed with the\n     manual building procedure)\n\n\nFor building with MacPorts you need to run:\n  sudo port install libtool automake autoconf pkgconfig \\\n    libusb [libftdi1]\n\nYou should also specify LDFLAGS and CPPFLAGS to allow configure to use\nMacPorts' libraries, so run configure like this:\n  LDFLAGS=-L/opt/local/lib CPPFLAGS=-I/opt/local/include ./configure [options]\n\n\nSee README for the generic building instructions.\n\nIf you're using a USB adapter and have a driver kext matched to it,\nyou will need to unload it prior to running OpenOCD. E.g. with Apple\ndriver (OS X 10.9 or later) for FTDI run:\n  sudo kextunload -b com.apple.driver.AppleUSBFTDI\nfor FTDI vendor driver use:\n  sudo kextunload FTDIUSBSerialDriver.kext\n\nTo learn more on the topic please refer to the official libusb FAQ:\nhttps://github.com/libusb/libusb/wiki/FAQ\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/exceptions/eCos-exception-2.0",
    "content": "SPDX-Exception-Identifier: eCos-exception-2.0\nSPDX-URL: https://spdx.org/licenses/eCos-exception-2.0.html\nSPDX-Licenses: GPL-2.0-only, GPL-2.0-or-later\nUsage-Guide:\n  This exception is used together with one of the above SPDX-Licenses.\n  To use this exception add it with the keyword WITH to one of the\n  identifiers in the SPDX-Licenses tag:\n    SPDX-License-Identifier: <SPDX-License> WITH eCos-exception-2.0\nLicense-Text:\n\nAs a special exception, if other files instantiate templates or use\nmacros or inline functions from this file, or you compile this\nfile and link it with other works to produce a work based on this\nfile, this file does not by itself cause the resulting work to be\ncovered by the GNU General Public License. However the source code for\nthis file must still be made available in accordance with section (3)\nof the GNU General Public License.\n\nThis exception does not invalidate any other reasons why a work based on\nthis file might be covered by the GNU General Public License.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/license-rules.txt",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later\n\nOpenOCD licensing rules\n=======================\n\nThe OpenOCD source code is provided under the terms of the GNU General\nPublic License version 2 or later (GPL-2.0-or-later), as provided in\nLICENSES/preferred/GPL-2.0.\n\nThe OpenOCD documentation is provided under the terms of the GNU Free\nDocumentation License version 1.2 or later without Invariant Sections\n(GFDL-1.2-no-invariants-or-later).\n\nFew stand-alone applications coexist in the same code tree of OpenOCD\nand are provided under the terms of the GNU General Public License\nversion 3 (GPL-3.0), as provided in LICENSES/stand-alone/GPL-3.0.\n\nThis documentation file provides a description of how each source file\nshould be annotated to make its license clear and unambiguous.\nIt doesn't replace the OpenOCD's license.\n\nThe license described in the COPYING file applies to the OpenOCD source\nas a whole, though individual source files can have a different license\nwhich is required to be compatible with the GPL-2.0:\n\n    GPL-1.0-or-later  : GNU General Public License v1.0 or later\n    GPL-2.0-or-later  : GNU General Public License v2.0 or later\n    LGPL-2.0          : GNU Library General Public License v2 only\n    LGPL-2.0-or-later : GNU Library General Public License v2 or later\n    LGPL-2.1          : GNU Lesser General Public License v2.1 only\n    LGPL-2.1-or-later : GNU Lesser General Public License v2.1 or later\n\nAside from that, individual files can be provided under a dual license,\ne.g. one of the compatible GPL variants and alternatively under a\npermissive license like BSD, MIT etc.\n\nThe common way of expressing the license of a source file is to add the\nmatching boilerplate text into the top comment of the file. Due to\nformatting, typos etc. these \"boilerplates\" are hard to validate for\ntools which are used in the context of license compliance.\n\nAn alternative to boilerplate text is the use of Software Package Data\nExchange (SPDX) license identifiers in each source file. SPDX license\nidentifiers are machine parsable and precise shorthands for the license\nunder which the content of the file is contributed. SPDX license\nidentifiers are managed by the SPDX Workgroup at the Linux Foundation and\nhave been agreed on by partners throughout the industry, tool vendors, and\nlegal teams. For further information see https://spdx.org/\n\nOpenOCD requires the precise SPDX identifier in all source files.\nThe valid identifiers used in OpenOCD are explained in the section\n`License identifiers` and have been retrieved from the official SPDX\nlicense list at https://spdx.org/licenses/ along with the license texts.\n\nLicense identifier syntax\n-------------------------\n\n1. Placement:\n\n   The SPDX license identifier in OpenOCD files shall be added at the\n   first possible line in a file which can contain a comment. For the\n   majority of files this is the first line, except for scripts which\n   require the '#!PATH_TO_INTERPRETER' in the first line. For those\n   scripts the SPDX identifier goes into the second line.\n\n2. Style:\n\n   The SPDX license identifier is added in form of a comment. The comment\n   style depends on the file type::\n\n      C source:  // SPDX-License-Identifier: <SPDX License Expression>\n      C header:  /* SPDX-License-Identifier: <SPDX License Expression> */\n      ASM:       /* SPDX-License-Identifier: <SPDX License Expression> */\n      makefiles: # SPDX-License-Identifier: <SPDX License Expression>\n      scripts:   # SPDX-License-Identifier: <SPDX License Expression>\n      texinfo:   @c SPDX-License-Identifier: <SPDX License Expression>\n      text:      # SPDX-License-Identifier: <SPDX License Expression>\n\n   If a specific tool cannot handle the standard comment style, then the\n   appropriate comment mechanism which the tool accepts shall be used. This\n   is the reason for having the \"/\\* \\*/\" style comment in C header\n   files. There was build breakage observed with generated .lds files where\n   'ld' failed to parse the C++ comment. This has been fixed by now, but\n   there are still older assembler tools which cannot handle C++ style\n   comments.\n\n3. Syntax:\n\n   A <SPDX License Expression> is either an SPDX short form license\n   identifier found on the SPDX License List, or the combination of two\n   SPDX short form license identifiers separated by \"WITH\" when a license\n   exception applies. When multiple licenses apply, an expression consists\n   of keywords \"AND\", \"OR\" separating sub-expressions and surrounded by\n   \"(\", \")\" .\n\n   License identifiers for licenses like [L]GPL with the 'or later' option\n   are constructed by using a \"-or-later\":\n\n      // SPDX-License-Identifier: GPL-2.0-or-later\n      // SPDX-License-Identifier: LGPL-2.1-or-later\n\n   WITH should be used when there is a modifier to a license needed.\n   Exceptions can only be used with particular License identifiers. The\n   valid License identifiers are listed in the tags of the exception text\n   file.\n\n   OR should be used if the file is dual licensed and only one license is\n   to be selected. For example, some source files are available under dual\n   licenses:\n\n      // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-1-Clause\n      // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause\n      // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause\n\n   AND should be used if the file has multiple licenses whose terms all\n   apply to use the file. For example, if code is inherited from another\n   project and permission has been given to put it in OpenOCD, but the\n   original license terms need to remain in effect::\n\n      // SPDX-License-Identifier: GPL-2.0-or-later AND MIT\n\nLicense identifiers\n-------------------\n\nThe licenses currently used, as well as the licenses for code added to\nOpenOCD, can be broken down into:\n\n1. `Preferred licenses`:\n\n   Whenever possible these licenses should be used as they are known to be\n   fully compatible and widely used. These licenses are available from the\n   directory:\n\n      LICENSES/preferred/\n\n   in the OpenOCD source tree.\n\n   The files in this directory contain the full license text and\n   `Metatags`. The file names are identical to the SPDX license\n   identifier which shall be used for the license in source files.\n\n   Examples:\n\n      LICENSES/preferred/GPL-2.0\n\n   Contains the GPL version 2 license text and the required metatags.\n\n   `Metatags`:\n\n   The following meta tags must be available in a license file:\n\n   - Valid-License-Identifier:\n\n     One or more lines which declare which License Identifiers are valid\n     inside the project to reference this particular license text. Usually\n     this is a single valid identifier, but e.g. for licenses with the 'or\n     later' options two identifiers are valid.\n\n   - SPDX-URL:\n\n     The URL of the SPDX page which contains additional information related\n     to the license.\n\n   - Usage-Guidance:\n\n     Freeform text for usage advice. The text must include correct examples\n     for the SPDX license identifiers as they should be put into source\n     files according to the `License identifier syntax` guidelines.\n\n   - License-Text:\n\n     All text after this tag is treated as the original license text\n\n   File format examples::\n\n      Valid-License-Identifier: GPL-2.0\n      Valid-License-Identifier: GPL-2.0-only\n      Valid-License-Identifier: GPL-2.0-or-later\n      SPDX-URL: https://spdx.org/licenses/GPL-2.0.html\n      Usage-Guide:\n        To use this license in source code, put one of the following SPDX\n        tag/value pairs into a comment according to the placement\n        guidelines in the licensing rules documentation.\n        For 'GNU General Public License (GPL) version 2 only' use:\n          SPDX-License-Identifier: GPL-2.0\n        or\n          SPDX-License-Identifier: GPL-2.0-only\n        For 'GNU General Public License (GPL) version 2 or any later version' use:\n          SPDX-License-Identifier: GPL-2.0-or-later\n      License-Text:\n        Full license text\n\n2. Exceptions:\n\n   Some licenses can be amended with exceptions which grant certain rights\n   which the original license does not.  These exceptions are available\n   from the directory::\n\n      LICENSES/exceptions/\n\n   in the OpenOCD source tree.  The files in this directory contain the full\n   exception text and the required `Exception Metatags`_.\n\n   Examples::\n\n      LICENSES/exceptions/eCos-exception-2.0\n\n   Exception Metatags:\n\n   The following meta tags must be available in an exception file:\n\n   - SPDX-Exception-Identifier:\n\n     One exception identifier which can be used with SPDX license\n     identifiers.\n\n   - SPDX-URL:\n\n     The URL of the SPDX page which contains additional information related\n     to the exception.\n\n   - SPDX-Licenses:\n\n     A comma separated list of SPDX license identifiers for which the\n     exception can be used.\n\n   - Usage-Guidance:\n\n     Freeform text for usage advice. The text must be followed by correct\n     examples for the SPDX license identifiers as they should be put into\n     source files according to the `License identifier syntax`_ guidelines.\n\n   - Exception-Text:\n\n     All text after this tag is treated as the original exception text\n\n   File format examples::\n\n      SPDX-Exception-Identifier: eCos-exception-2.0\n      SPDX-URL: https://spdx.org/licenses/eCos-exception-2.0.html\n      SPDX-Licenses: GPL-2.0-only, GPL-2.0-or-later\n      Usage-Guide:\n        This exception is used together with one of the above SPDX-Licenses.\n        To use this exception add it with the keyword WITH to one of the\n        identifiers in the SPDX-Licenses tag:\n          SPDX-License-Identifier: <SPDX-License> WITH eCos-exception-2.0\n      License-Text:\n        Full license text\n\n3. Stand-alone licenses:\n\n   These licenses should only be used for stand-alone applications that are\n   distributed with OpenOCD but are not included in the OpenOCD binary.\n   These licenses are available from the directory:\n\n     LICENSES/stand-alone/\n\n   in the OpenOCD source tree.\n\n   Examples:\n\n     SPDX-License-Identifier: GPL-3.0\n\nThe format and requirements of the license files in the other sub-directories\nof directory\n\n   LICENSES\n\nhave to follow the same format and requirements of the `Preferred licenses`.\n\nAll SPDX license identifiers and exceptions must have a corresponding file\nin the LICENSES subdirectories. This is required to allow tool\nverification (e.g. checkpatch.pl) and to have the licenses ready to read\nand extract right from the source, which is recommended by various FOSS\norganizations, e.g. the `FSFE REUSE initiative <https://reuse.software/>`.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-1-Clause",
    "content": "Valid-License-Identifier: BSD-1-Clause\nSPDX-URL: https://spdx.org/licenses/BSD-1-Clause.html\nUsage-Guide:\n  To use the BSD 1-clause License put the following SPDX\n  tag/value pair into a comment according to the placement guidelines in\n  the licensing rules documentation:\n    SPDX-License-Identifier: BSD-1-Clause\nLicense-Text:\n\nCopyright (c) <year> <owner> . All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice,\n   this list of conditions and the following disclaimer.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-2-Clause",
    "content": "Valid-License-Identifier: BSD-2-Clause\nSPDX-URL: https://spdx.org/licenses/BSD-2-Clause.html\nUsage-Guide:\n  To use the BSD 2-clause \"Simplified\" License put the following SPDX\n  tag/value pair into a comment according to the placement guidelines in\n  the licensing rules documentation:\n    SPDX-License-Identifier: BSD-2-Clause\nLicense-Text:\n\nCopyright (c) <year> <owner> . All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice,\n   this list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\n   notice, this list of conditions and the following disclaimer in the\n   documentation and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-2-Clause-Views",
    "content": "Valid-License-Identifier: BSD-2-Clause-Views\nSPDX-URL: https://spdx.org/licenses/BSD-2-Clause-Views.html\nUsage-Guide:\n  To use the BSD 2-clause with views sentence License put the following SPDX\n  tag/value pair into a comment according to the placement guidelines in\n  the licensing rules documentation:\n    SPDX-License-Identifier: BSD-2-Clause-Views\nLicense-Text:\n\nCopyright (c) <year> <owner> . All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice,\n   this list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\n   notice, this list of conditions and the following disclaimer in the\n   documentation and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\nThe views and conclusions contained in the software and documentation\nare those of the authors and should not be interpreted as representing\nofficial policies, either expressed or implied, of the copyright holders\nor contributors.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-3-Clause",
    "content": "Valid-License-Identifier: BSD-3-Clause\nSPDX-URL: https://spdx.org/licenses/BSD-3-Clause.html\nUsage-Guide:\n  To use the BSD 3-clause \"New\" or \"Revised\" License put the following SPDX\n  tag/value pair into a comment according to the placement guidelines in\n  the licensing rules documentation:\n    SPDX-License-Identifier: BSD-3-Clause\nLicense-Text:\n\nCopyright (c) <year> <owner> . All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice,\n   this list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\n   notice, this list of conditions and the following disclaimer in the\n   documentation and/or other materials provided with the distribution.\n\n3. Neither the name of the copyright holder nor the names of its\n   contributors may be used to endorse or promote products derived from this\n   software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/BSD-Source-Code",
    "content": "Valid-License-Identifier: BSD-Source-Code\nSPDX-URL: https://spdx.org/licenses/BSD-Source-Code.html\nUsage-Guide:\n  To use the BSD Source Code Attribution License put the following SPDX\n  tag/value pair into a comment according to the placement guidelines in\n  the licensing rules documentation:\n    SPDX-License-Identifier: BSD-Source-Code\nLicense-Text:\n\nCopyright (c) <year> <owner> . All rights reserved.\n\nRedistribution and use of this software in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice,\n   this list of conditions and the following disclaimer.\n\n * Neither the name of the copyright holder nor the names of its\n   contributors may be used to endorse or promote products derived from this\n   software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/GFDL-1.2",
    "content": "Valid-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later\nValid-License-Identifier: GFDL-1.2-no-invariants-or-later\nSPDX-URL: https://spdx.org/licenses/GFDL-1.2-no-invariants-or-later.html\nUsage-Guide:\n  The GNU Free Documentation License should only be used without\n  Invariant Sections, Front-Cover Texts or Back-Cover Texts.\n  It should not be used for new documents.\n  To use the license in source code, put the following SPDX tag/value pair\n  into a comment according to the placement guidelines in the licensing\n  rules documentation:\n    SPDX-License-Identifier: GPL-2.0-or-later OR GFDL-1.2-no-invariants-or-later\n  or\n    SPDX-License-Identifier: GFDL-1.2-no-invariants-or-later\nLicense-Text:\n\n                GNU Free Documentation License\n                  Version 1.2, November 2002\n\n\n Copyright (C) 2000,2001,2002  Free Software Foundation, Inc.\n     51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n\n0. PREAMBLE\n\nThe purpose of this License is to make a manual, textbook, or other\nfunctional and useful document \"free\" in the sense of freedom: to\nassure everyone the effective freedom to copy and redistribute it,\nwith or without modifying it, either commercially or noncommercially.\nSecondarily, this License preserves for the author and publisher a way\nto get credit for their work, while not being considered responsible\nfor modifications made by others.\n\nThis License is a kind of \"copyleft\", which means that derivative\nworks of the document must themselves be free in the same sense.  It\ncomplements the GNU General Public License, which is a copyleft\nlicense designed for free software.\n\nWe have designed this License in order to use it for manuals for free\nsoftware, because free software needs free documentation: a free\nprogram should come with manuals providing the same freedoms that the\nsoftware does.  But this License is not limited to software manuals;\nit can be used for any textual work, regardless of subject matter or\nwhether it is published as a printed book.  We recommend this License\nprincipally for works whose purpose is instruction or reference.\n\n\n1. APPLICABILITY AND DEFINITIONS\n\nThis License applies to any manual or other work, in any medium, that\ncontains a notice placed by the copyright holder saying it can be\ndistributed under the terms of this License.  Such a notice grants a\nworld-wide, royalty-free license, unlimited in duration, to use that\nwork under the conditions stated herein.  The \"Document\", below,\nrefers to any such manual or work.  Any member of the public is a\nlicensee, and is addressed as \"you\".  You accept the license if you\ncopy, modify or distribute the work in a way requiring permission\nunder copyright law.\n\nA \"Modified Version\" of the Document means any work containing the\nDocument or a portion of it, either copied verbatim, or with\nmodifications and/or translated into another language.\n\nA \"Secondary Section\" is a named appendix or a front-matter section of\nthe Document that deals exclusively with the relationship of the\npublishers or authors of the Document to the Document's overall subject\n(or to related matters) and contains nothing that could fall directly\nwithin that overall subject.  (Thus, if the Document is in part a\ntextbook of mathematics, a Secondary Section may not explain any\nmathematics.)  The relationship could be a matter of historical\nconnection with the subject or with related matters, or of legal,\ncommercial, philosophical, ethical or political position regarding\nthem.\n\nThe \"Invariant Sections\" are certain Secondary Sections whose titles\nare designated, as being those of Invariant Sections, in the notice\nthat says that the Document is released under this License.  If a\nsection does not fit the above definition of Secondary then it is not\nallowed to be designated as Invariant.  The Document may contain zero\nInvariant Sections.  If the Document does not identify any Invariant\nSections then there are none.\n\nThe \"Cover Texts\" are certain short passages of text that are listed,\nas Front-Cover Texts or Back-Cover Texts, in the notice that says that\nthe Document is released under this License.  A Front-Cover Text may\nbe at most 5 words, and a Back-Cover Text may be at most 25 words.\n\nA \"Transparent\" copy of the Document means a machine-readable copy,\nrepresented in a format whose specification is available to the\ngeneral public, that is suitable for revising the document\nstraightforwardly with generic text editors or (for images composed of\npixels) generic paint programs or (for drawings) some widely available\ndrawing editor, and that is suitable for input to text formatters or\nfor automatic translation to a variety of formats suitable for input\nto text formatters.  A copy made in an otherwise Transparent file\nformat whose markup, or absence of markup, has been arranged to thwart\nor discourage subsequent modification by readers is not Transparent.\nAn image format is not Transparent if used for any substantial amount\nof text.  A copy that is not \"Transparent\" is called \"Opaque\".\n\nExamples of suitable formats for Transparent copies include plain\nASCII without markup, Texinfo input format, LaTeX input format, SGML\nor XML using a publicly available DTD, and standard-conforming simple\nHTML, PostScript or PDF designed for human modification.  Examples of\ntransparent image formats include PNG, XCF and JPG.  Opaque formats\ninclude proprietary formats that can be read and edited only by\nproprietary word processors, SGML or XML for which the DTD and/or\nprocessing tools are not generally available, and the\nmachine-generated HTML, PostScript or PDF produced by some word\nprocessors for output purposes only.\n\nThe \"Title Page\" means, for a printed book, the title page itself,\nplus such following pages as are needed to hold, legibly, the material\nthis License requires to appear in the title page.  For works in\nformats which do not have any title page as such, \"Title Page\" means\nthe text near the most prominent appearance of the work's title,\npreceding the beginning of the body of the text.\n\nA section \"Entitled XYZ\" means a named subunit of the Document whose\ntitle either is precisely XYZ or contains XYZ in parentheses following\ntext that translates XYZ in another language.  (Here XYZ stands for a\nspecific section name mentioned below, such as \"Acknowledgements\",\n\"Dedications\", \"Endorsements\", or \"History\".)  To \"Preserve the Title\"\nof such a section when you modify the Document means that it remains a\nsection \"Entitled XYZ\" according to this definition.\n\nThe Document may include Warranty Disclaimers next to the notice which\nstates that this License applies to the Document.  These Warranty\nDisclaimers are considered to be included by reference in this\nLicense, but only as regards disclaiming warranties: any other\nimplication that these Warranty Disclaimers may have is void and has\nno effect on the meaning of this License.\n\n\n2. VERBATIM COPYING\n\nYou may copy and distribute the Document in any medium, either\ncommercially or noncommercially, provided that this License, the\ncopyright notices, and the license notice saying this License applies\nto the Document are reproduced in all copies, and that you add no other\nconditions whatsoever to those of this License.  You may not use\ntechnical measures to obstruct or control the reading or further\ncopying of the copies you make or distribute.  However, you may accept\ncompensation in exchange for copies.  If you distribute a large enough\nnumber of copies you must also follow the conditions in section 3.\n\nYou may also lend copies, under the same conditions stated above, and\nyou may publicly display copies.\n\n\n3. COPYING IN QUANTITY\n\nIf you publish printed copies (or copies in media that commonly have\nprinted covers) of the Document, numbering more than 100, and the\nDocument's license notice requires Cover Texts, you must enclose the\ncopies in covers that carry, clearly and legibly, all these Cover\nTexts: Front-Cover Texts on the front cover, and Back-Cover Texts on\nthe back cover.  Both covers must also clearly and legibly identify\nyou as the publisher of these copies.  The front cover must present\nthe full title with all words of the title equally prominent and\nvisible.  You may add other material on the covers in addition.\nCopying with changes limited to the covers, as long as they preserve\nthe title of the Document and satisfy these conditions, can be treated\nas verbatim copying in other respects.\n\nIf the required texts for either cover are too voluminous to fit\nlegibly, you should put the first ones listed (as many as fit\nreasonably) on the actual cover, and continue the rest onto adjacent\npages.\n\nIf you publish or distribute Opaque copies of the Document numbering\nmore than 100, you must either include a machine-readable Transparent\ncopy along with each Opaque copy, or state in or with each Opaque copy\na computer-network location from which the general network-using\npublic has access to download using public-standard network protocols\na complete Transparent copy of the Document, free of added material.\nIf you use the latter option, you must take reasonably prudent steps,\nwhen you begin distribution of Opaque copies in quantity, to ensure\nthat this Transparent copy will remain thus accessible at the stated\nlocation until at least one year after the last time you distribute an\nOpaque copy (directly or through your agents or retailers) of that\nedition to the public.\n\nIt is requested, but not required, that you contact the authors of the\nDocument well before redistributing any large number of copies, to give\nthem a chance to provide you with an updated version of the Document.\n\n\n4. MODIFICATIONS\n\nYou may copy and distribute a Modified Version of the Document under\nthe conditions of sections 2 and 3 above, provided that you release\nthe Modified Version under precisely this License, with the Modified\nVersion filling the role of the Document, thus licensing distribution\nand modification of the Modified Version to whoever possesses a copy\nof it.  In addition, you must do these things in the Modified Version:\n\nA. Use in the Title Page (and on the covers, if any) a title distinct\n   from that of the Document, and from those of previous versions\n   (which should, if there were any, be listed in the History section\n   of the Document).  You may use the same title as a previous version\n   if the original publisher of that version gives permission.\nB. List on the Title Page, as authors, one or more persons or entities\n   responsible for authorship of the modifications in the Modified\n   Version, together with at least five of the principal authors of the\n   Document (all of its principal authors, if it has fewer than five),\n   unless they release you from this requirement.\nC. State on the Title page the name of the publisher of the\n   Modified Version, as the publisher.\nD. Preserve all the copyright notices of the Document.\nE. Add an appropriate copyright notice for your modifications\n   adjacent to the other copyright notices.\nF. Include, immediately after the copyright notices, a license notice\n   giving the public permission to use the Modified Version under the\n   terms of this License, in the form shown in the Addendum below.\nG. Preserve in that license notice the full lists of Invariant Sections\n   and required Cover Texts given in the Document's license notice.\nH. Include an unaltered copy of this License.\nI. Preserve the section Entitled \"History\", Preserve its Title, and add\n   to it an item stating at least the title, year, new authors, and\n   publisher of the Modified Version as given on the Title Page.  If\n   there is no section Entitled \"History\" in the Document, create one\n   stating the title, year, authors, and publisher of the Document as\n   given on its Title Page, then add an item describing the Modified\n   Version as stated in the previous sentence.\nJ. Preserve the network location, if any, given in the Document for\n   public access to a Transparent copy of the Document, and likewise\n   the network locations given in the Document for previous versions\n   it was based on.  These may be placed in the \"History\" section.\n   You may omit a network location for a work that was published at\n   least four years before the Document itself, or if the original\n   publisher of the version it refers to gives permission.\nK. For any section Entitled \"Acknowledgements\" or \"Dedications\",\n   Preserve the Title of the section, and preserve in the section all\n   the substance and tone of each of the contributor acknowledgements\n   and/or dedications given therein.\nL. Preserve all the Invariant Sections of the Document,\n   unaltered in their text and in their titles.  Section numbers\n   or the equivalent are not considered part of the section titles.\nM. Delete any section Entitled \"Endorsements\".  Such a section\n   may not be included in the Modified Version.\nN. Do not retitle any existing section to be Entitled \"Endorsements\"\n   or to conflict in title with any Invariant Section.\nO. Preserve any Warranty Disclaimers.\n\nIf the Modified Version includes new front-matter sections or\nappendices that qualify as Secondary Sections and contain no material\ncopied from the Document, you may at your option designate some or all\nof these sections as invariant.  To do this, add their titles to the\nlist of Invariant Sections in the Modified Version's license notice.\nThese titles must be distinct from any other section titles.\n\nYou may add a section Entitled \"Endorsements\", provided it contains\nnothing but endorsements of your Modified Version by various\nparties--for example, statements of peer review or that the text has\nbeen approved by an organization as the authoritative definition of a\nstandard.\n\nYou may add a passage of up to five words as a Front-Cover Text, and a\npassage of up to 25 words as a Back-Cover Text, to the end of the list\nof Cover Texts in the Modified Version.  Only one passage of\nFront-Cover Text and one of Back-Cover Text may be added by (or\nthrough arrangements made by) any one entity.  If the Document already\nincludes a cover text for the same cover, previously added by you or\nby arrangement made by the same entity you are acting on behalf of,\nyou may not add another; but you may replace the old one, on explicit\npermission from the previous publisher that added the old one.\n\nThe author(s) and publisher(s) of the Document do not by this License\ngive permission to use their names for publicity for or to assert or\nimply endorsement of any Modified Version.\n\n\n5. COMBINING DOCUMENTS\n\nYou may combine the Document with other documents released under this\nLicense, under the terms defined in section 4 above for modified\nversions, provided that you include in the combination all of the\nInvariant Sections of all of the original documents, unmodified, and\nlist them all as Invariant Sections of your combined work in its\nlicense notice, and that you preserve all their Warranty Disclaimers.\n\nThe combined work need only contain one copy of this License, and\nmultiple identical Invariant Sections may be replaced with a single\ncopy.  If there are multiple Invariant Sections with the same name but\ndifferent contents, make the title of each such section unique by\nadding at the end of it, in parentheses, the name of the original\nauthor or publisher of that section if known, or else a unique number.\nMake the same adjustment to the section titles in the list of\nInvariant Sections in the license notice of the combined work.\n\nIn the combination, you must combine any sections Entitled \"History\"\nin the various original documents, forming one section Entitled\n\"History\"; likewise combine any sections Entitled \"Acknowledgements\",\nand any sections Entitled \"Dedications\".  You must delete all sections\nEntitled \"Endorsements\".\n\n\n6. COLLECTIONS OF DOCUMENTS\n\nYou may make a collection consisting of the Document and other documents\nreleased under this License, and replace the individual copies of this\nLicense in the various documents with a single copy that is included in\nthe collection, provided that you follow the rules of this License for\nverbatim copying of each of the documents in all other respects.\n\nYou may extract a single document from such a collection, and distribute\nit individually under this License, provided you insert a copy of this\nLicense into the extracted document, and follow this License in all\nother respects regarding verbatim copying of that document.\n\n\n7. AGGREGATION WITH INDEPENDENT WORKS\n\nA compilation of the Document or its derivatives with other separate\nand independent documents or works, in or on a volume of a storage or\ndistribution medium, is called an \"aggregate\" if the copyright\nresulting from the compilation is not used to limit the legal rights\nof the compilation's users beyond what the individual works permit.\nWhen the Document is included in an aggregate, this License does not\napply to the other works in the aggregate which are not themselves\nderivative works of the Document.\n\nIf the Cover Text requirement of section 3 is applicable to these\ncopies of the Document, then if the Document is less than one half of\nthe entire aggregate, the Document's Cover Texts may be placed on\ncovers that bracket the Document within the aggregate, or the\nelectronic equivalent of covers if the Document is in electronic form.\nOtherwise they must appear on printed covers that bracket the whole\naggregate.\n\n\n8. TRANSLATION\n\nTranslation is considered a kind of modification, so you may\ndistribute translations of the Document under the terms of section 4.\nReplacing Invariant Sections with translations requires special\npermission from their copyright holders, but you may include\ntranslations of some or all Invariant Sections in addition to the\noriginal versions of these Invariant Sections.  You may include a\ntranslation of this License, and all the license notices in the\nDocument, and any Warranty Disclaimers, provided that you also include\nthe original English version of this License and the original versions\nof those notices and disclaimers.  In case of a disagreement between\nthe translation and the original version of this License or a notice\nor disclaimer, the original version will prevail.\n\nIf a section in the Document is Entitled \"Acknowledgements\",\n\"Dedications\", or \"History\", the requirement (section 4) to Preserve\nits Title (section 1) will typically require changing the actual\ntitle.\n\n\n9. TERMINATION\n\nYou may not copy, modify, sublicense, or distribute the Document except\nas expressly provided for under this License.  Any other attempt to\ncopy, modify, sublicense or distribute the Document is void, and will\nautomatically terminate your rights under this License.  However,\nparties who have received copies, or rights, from you under this\nLicense will not have their licenses terminated so long as such\nparties remain in full compliance.\n\n\n10. FUTURE REVISIONS OF THIS LICENSE\n\nThe Free Software Foundation may publish new, revised versions\nof the GNU Free Documentation License from time to time.  Such new\nversions will be similar in spirit to the present version, but may\ndiffer in detail to address new problems or concerns.  See\nhttps://www.gnu.org/licenses/.\n\nEach version of the License is given a distinguishing version number.\nIf the Document specifies that a particular numbered version of this\nLicense \"or any later version\" applies to it, you have the option of\nfollowing the terms and conditions either of that specified version or\nof any later version that has been published (not as a draft) by the\nFree Software Foundation.  If the Document does not specify a version\nnumber of this License, you may choose any version ever published (not\nas a draft) by the Free Software Foundation.\n\n\nADDENDUM: How to use this License for your documents\n\nTo use this License in a document you have written, include a copy of\nthe License in the document and put the following copyright and\nlicense notices just after the title page:\n\n    Copyright (c)  YEAR  YOUR NAME.\n    Permission is granted to copy, distribute and/or modify this document\n    under the terms of the GNU Free Documentation License, Version 1.2\n    or any later version published by the Free Software Foundation;\n    with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts.\n    A copy of the license is included in the section entitled \"GNU\n    Free Documentation License\".\n\nIf you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,\nreplace the \"with...Texts.\" line with this:\n\n    with the Invariant Sections being LIST THEIR TITLES, with the\n    Front-Cover Texts being LIST, and with the Back-Cover Texts being LIST.\n\nIf you have Invariant Sections without Cover Texts, or some other\ncombination of the three, merge those two alternatives to suit the\nsituation.\n\nIf your document contains nontrivial examples of program code, we\nrecommend releasing these examples in parallel under your choice of\nfree software license, such as the GNU General Public License,\nto permit their use in free software.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/GPL-2.0",
    "content": "Valid-License-Identifier: GPL-2.0\nValid-License-Identifier: GPL-2.0-only\nValid-License-Identifier: GPL-2.0-or-later\nSPDX-URL: https://spdx.org/licenses/GPL-2.0.html\nUsage-Guide:\n  To use this license in source code, put one of the following SPDX\n  tag/value pairs into a comment according to the placement\n  guidelines in the licensing rules documentation.\n  For 'GNU General Public License (GPL) version 2 only' use:\n    SPDX-License-Identifier: GPL-2.0\n  or\n    SPDX-License-Identifier: GPL-2.0-only\n  For 'GNU General Public License (GPL) version 2 or any later version' use:\n    SPDX-License-Identifier: GPL-2.0-or-later\nLicense-Text:\n\n                    GNU GENERAL PUBLIC LICENSE\n                       Version 2, June 1991\n\n Copyright (C) 1989, 1991 Free Software Foundation, Inc.,\n 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  By contrast, the GNU General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users.  This\nGeneral Public License applies to most of the Free Software\nFoundation's software and to any other program whose authors commit to\nusing it.  (Some other Free Software Foundation software is covered by\nthe GNU Lesser General Public License instead.)  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthis service if you wish), that you receive source code or can get it\nif you want it, that you can change the software or use pieces of it\nin new free programs; and that you know you can do these things.\n\n  To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have.  You must make sure that they, too, receive or can get the\nsource code.  And you must show them these terms so they know their\nrights.\n\n  We protect your rights with two steps: (1) copyright the software, and\n(2) offer you this license which gives you legal permission to copy,\ndistribute and/or modify the software.\n\n  Also, for each author's protection and ours, we want to make certain\nthat everyone understands that there is no warranty for this free\nsoftware.  If the software is modified by someone else and passed on, we\nwant its recipients to know that what they have is not the original, so\nthat any problems introduced by others will not reflect on the original\nauthors' reputations.\n\n  Finally, any free program is threatened constantly by software\npatents.  We wish to avoid the danger that redistributors of a free\nprogram will individually obtain patent licenses, in effect making the\nprogram proprietary.  To prevent this, we have made it clear that any\npatent must be licensed for everyone's free use or not licensed at all.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n                    GNU GENERAL PUBLIC LICENSE\n   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n  0. This License applies to any program or other work which contains\na notice placed by the copyright holder saying it may be distributed\nunder the terms of this General Public License.  The \"Program\", below,\nrefers to any such program or work, and a \"work based on the Program\"\nmeans either the Program or any derivative work under copyright law:\nthat is to say, a work containing the Program or a portion of it,\neither verbatim or with modifications and/or translated into another\nlanguage.  (Hereinafter, translation is included without limitation in\nthe term \"modification\".)  Each licensee is addressed as \"you\".\n\nActivities other than copying, distribution and modification are not\ncovered by this License; they are outside its scope.  The act of\nrunning the Program is not restricted, and the output from the Program\nis covered only if its contents constitute a work based on the\nProgram (independent of having been made by running the Program).\nWhether that is true depends on what the Program does.\n\n  1. You may copy and distribute verbatim copies of the Program's\nsource code as you receive it, in any medium, provided that you\nconspicuously and appropriately publish on each copy an appropriate\ncopyright notice and disclaimer of warranty; keep intact all the\nnotices that refer to this License and to the absence of any warranty;\nand give any other recipients of the Program a copy of this License\nalong with the Program.\n\nYou may charge a fee for the physical act of transferring a copy, and\nyou may at your option offer warranty protection in exchange for a fee.\n\n  2. You may modify your copy or copies of the Program or any portion\nof it, thus forming a work based on the Program, and copy and\ndistribute such modifications or work under the terms of Section 1\nabove, provided that you also meet all of these conditions:\n\n    a) You must cause the modified files to carry prominent notices\n    stating that you changed the files and the date of any change.\n\n    b) You must cause any work that you distribute or publish, that in\n    whole or in part contains or is derived from the Program or any\n    part thereof, to be licensed as a whole at no charge to all third\n    parties under the terms of this License.\n\n    c) If the modified program normally reads commands interactively\n    when run, you must cause it, when started running for such\n    interactive use in the most ordinary way, to print or display an\n    announcement including an appropriate copyright notice and a\n    notice that there is no warranty (or else, saying that you provide\n    a warranty) and that users may redistribute the program under\n    these conditions, and telling the user how to view a copy of this\n    License.  (Exception: if the Program itself is interactive but\n    does not normally print such an announcement, your work based on\n    the Program is not required to print an announcement.)\n\nThese requirements apply to the modified work as a whole.  If\nidentifiable sections of that work are not derived from the Program,\nand can be reasonably considered independent and separate works in\nthemselves, then this License, and its terms, do not apply to those\nsections when you distribute them as separate works.  But when you\ndistribute the same sections as part of a whole which is a work based\non the Program, the distribution of the whole must be on the terms of\nthis License, whose permissions for other licensees extend to the\nentire whole, and thus to each and every part regardless of who wrote it.\n\nThus, it is not the intent of this section to claim rights or contest\nyour rights to work written entirely by you; rather, the intent is to\nexercise the right to control the distribution of derivative or\ncollective works based on the Program.\n\nIn addition, mere aggregation of another work not based on the Program\nwith the Program (or with a work based on the Program) on a volume of\na storage or distribution medium does not bring the other work under\nthe scope of this License.\n\n  3. You may copy and distribute the Program (or a work based on it,\nunder Section 2) in object code or executable form under the terms of\nSections 1 and 2 above provided that you also do one of the following:\n\n    a) Accompany it with the complete corresponding machine-readable\n    source code, which must be distributed under the terms of Sections\n    1 and 2 above on a medium customarily used for software interchange; or,\n\n    b) Accompany it with a written offer, valid for at least three\n    years, to give any third party, for a charge no more than your\n    cost of physically performing source distribution, a complete\n    machine-readable copy of the corresponding source code, to be\n    distributed under the terms of Sections 1 and 2 above on a medium\n    customarily used for software interchange; or,\n\n    c) Accompany it with the information you received as to the offer\n    to distribute corresponding source code.  (This alternative is\n    allowed only for noncommercial distribution and only if you\n    received the program in object code or executable form with such\n    an offer, in accord with Subsection b above.)\n\nThe source code for a work means the preferred form of the work for\nmaking modifications to it.  For an executable work, complete source\ncode means all the source code for all modules it contains, plus any\nassociated interface definition files, plus the scripts used to\ncontrol compilation and installation of the executable.  However, as a\nspecial exception, the source code distributed need not include\nanything that is normally distributed (in either source or binary\nform) with the major components (compiler, kernel, and so on) of the\noperating system on which the executable runs, unless that component\nitself accompanies the executable.\n\nIf distribution of executable or object code is made by offering\naccess to copy from a designated place, then offering equivalent\naccess to copy the source code from the same place counts as\ndistribution of the source code, even though third parties are not\ncompelled to copy the source along with the object code.\n\n  4. You may not copy, modify, sublicense, or distribute the Program\nexcept as expressly provided under this License.  Any attempt\notherwise to copy, modify, sublicense or distribute the Program is\nvoid, and will automatically terminate your rights under this License.\nHowever, parties who have received copies, or rights, from you under\nthis License will not have their licenses terminated so long as such\nparties remain in full compliance.\n\n  5. You are not required to accept this License, since you have not\nsigned it.  However, nothing else grants you permission to modify or\ndistribute the Program or its derivative works.  These actions are\nprohibited by law if you do not accept this License.  Therefore, by\nmodifying or distributing the Program (or any work based on the\nProgram), you indicate your acceptance of this License to do so, and\nall its terms and conditions for copying, distributing or modifying\nthe Program or works based on it.\n\n  6. Each time you redistribute the Program (or any work based on the\nProgram), the recipient automatically receives a license from the\noriginal licensor to copy, distribute or modify the Program subject to\nthese terms and conditions.  You may not impose any further\nrestrictions on the recipients' exercise of the rights granted herein.\nYou are not responsible for enforcing compliance by third parties to\nthis License.\n\n  7. If, as a consequence of a court judgment or allegation of patent\ninfringement or for any other reason (not limited to patent issues),\nconditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot\ndistribute so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you\nmay not distribute the Program at all.  For example, if a patent\nlicense would not permit royalty-free redistribution of the Program by\nall those who receive copies directly or indirectly through you, then\nthe only way you could satisfy both it and this License would be to\nrefrain entirely from distribution of the Program.\n\nIf any portion of this section is held invalid or unenforceable under\nany particular circumstance, the balance of the section is intended to\napply and the section as a whole is intended to apply in other\ncircumstances.\n\nIt is not the purpose of this section to induce you to infringe any\npatents or other property right claims or to contest validity of any\nsuch claims; this section has the sole purpose of protecting the\nintegrity of the free software distribution system, which is\nimplemented by public license practices.  Many people have made\ngenerous contributions to the wide range of software distributed\nthrough that system in reliance on consistent application of that\nsystem; it is up to the author/donor to decide if he or she is willing\nto distribute software through any other system and a licensee cannot\nimpose that choice.\n\nThis section is intended to make thoroughly clear what is believed to\nbe a consequence of the rest of this License.\n\n  8. If the distribution and/or use of the Program is restricted in\ncertain countries either by patents or by copyrighted interfaces, the\noriginal copyright holder who places the Program under this License\nmay add an explicit geographical distribution limitation excluding\nthose countries, so that distribution is permitted only in or among\ncountries not thus excluded.  In such case, this License incorporates\nthe limitation as if written in the body of this License.\n\n  9. The Free Software Foundation may publish revised and/or new versions\nof the General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\nEach version is given a distinguishing version number.  If the Program\nspecifies a version number of this License which applies to it and \"any\nlater version\", you have the option of following the terms and conditions\neither of that version or of any later version published by the Free\nSoftware Foundation.  If the Program does not specify a version number of\nthis License, you may choose any version ever published by the Free Software\nFoundation.\n\n  10. If you wish to incorporate parts of the Program into other free\nprograms whose distribution conditions are different, write to the author\nto ask for permission.  For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this.  Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n                            NO WARRANTY\n\n  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\nREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\nINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\nOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\nYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\nPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGES.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software; you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation; either version 2 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License along\n    with this program; if not, write to the Free Software Foundation, Inc.,\n    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n\nAlso add information on how to contact you by electronic and paper mail.\n\nIf the program is interactive, make it output a short notice like this\nwhen it starts in an interactive mode:\n\n    Gnomovision version 69, Copyright (C) year name of author\n    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, the commands you use may\nbe called something other than `show w' and `show c'; they could even be\nmouse-clicks or menu items--whatever suits your program.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the program, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the program\n  `Gnomovision' (which makes passes at compilers) written by James Hacker.\n\n  <signature of Ty Coon>, 1 April 1989\n  Ty Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into\nproprietary programs.  If your program is a subroutine library, you may\nconsider it more useful to permit linking proprietary applications with the\nlibrary.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/LGPL-2.1",
    "content": "Valid-License-Identifier: LGPL-2.1-only\nValid-License-Identifier: LGPL-2.1-or-later\nSPDX-URL: https://spdx.org/licenses/LGPL-2.1.html\nUsage-Guide:\n  To use this license in source code, put one of the following SPDX\n  tag/value pairs into a comment according to the placement\n  guidelines in the licensing rules documentation.\n  For 'GNU Lesser General Public License (LGPL) version 2.1 only' use:\n    SPDX-License-Identifier: LGPL-2.1-only\n  For 'GNU Lesser General Public License (LGPL) version 2.1 or any later\n  version' use:\n    SPDX-License-Identifier: LGPL-2.1-or-later\nLicense-Text:\n\nGNU LESSER GENERAL PUBLIC LICENSE\nVersion 2.1, February 1999\n\nCopyright (C) 1991, 1999 Free Software Foundation, Inc.\n51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n\nEveryone is permitted to copy and distribute verbatim copies of this\nlicense document, but changing it is not allowed.\n\n[This is the first released version of the Lesser GPL. It also counts as\nthe successor of the GNU Library Public License, version 2, hence the\nversion number 2.1.]\n\nPreamble\n\nThe licenses for most software are designed to take away your freedom to\nshare and change it. By contrast, the GNU General Public Licenses are\nintended to guarantee your freedom to share and change free software--to\nmake sure the software is free for all its users.\n\nThis license, the Lesser General Public License, applies to some specially\ndesignated software packages--typically libraries--of the Free Software\nFoundation and other authors who decide to use it. You can use it too, but\nwe suggest you first think carefully about whether this license or the\nordinary General Public License is the better strategy to use in any\nparticular case, based on the explanations below.\n\nWhen we speak of free software, we are referring to freedom of use, not\nprice. Our General Public Licenses are designed to make sure that you have\nthe freedom to distribute copies of free software (and charge for this\nservice if you wish); that you receive source code or can get it if you\nwant it; that you can change the software and use pieces of it in new free\nprograms; and that you are informed that you can do these things.\n\nTo protect your rights, we need to make restrictions that forbid\ndistributors to deny you these rights or to ask you to surrender these\nrights. These restrictions translate to certain responsibilities for you if\nyou distribute copies of the library or if you modify it.\n\nFor example, if you distribute copies of the library, whether gratis or for\na fee, you must give the recipients all the rights that we gave you. You\nmust make sure that they, too, receive or can get the source code. If you\nlink other code with the library, you must provide complete object files to\nthe recipients, so that they can relink them with the library after making\nchanges to the library and recompiling it. And you must show them these\nterms so they know their rights.\n\nWe protect your rights with a two-step method: (1) we copyright the\nlibrary, and (2) we offer you this license, which gives you legal\npermission to copy, distribute and/or modify the library.\n\nTo protect each distributor, we want to make it very clear that there is no\nwarranty for the free library. Also, if the library is modified by someone\nelse and passed on, the recipients should know that what they have is not\nthe original version, so that the original author's reputation will not be\naffected by problems that might be introduced by others.\n\nFinally, software patents pose a constant threat to the existence of any\nfree program. We wish to make sure that a company cannot effectively\nrestrict the users of a free program by obtaining a restrictive license\nfrom a patent holder. Therefore, we insist that any patent license obtained\nfor a version of the library must be consistent with the full freedom of\nuse specified in this license.\n\nMost GNU software, including some libraries, is covered by the ordinary GNU\nGeneral Public License. This license, the GNU Lesser General Public\nLicense, applies to certain designated libraries, and is quite different\nfrom the ordinary General Public License. We use this license for certain\nlibraries in order to permit linking those libraries into non-free\nprograms.\n\nWhen a program is linked with a library, whether statically or using a\nshared library, the combination of the two is legally speaking a combined\nwork, a derivative of the original library. The ordinary General Public\nLicense therefore permits such linking only if the entire combination fits\nits criteria of freedom. The Lesser General Public License permits more lax\ncriteria for linking other code with the library.\n\nWe call this license the \"Lesser\" General Public License because it does\nLess to protect the user's freedom than the ordinary General Public\nLicense. It also provides other free software developers Less of an\nadvantage over competing non-free programs. These disadvantages are the\nreason we use the ordinary General Public License for many\nlibraries. However, the Lesser license provides advantages in certain\nspecial circumstances.\n\nFor example, on rare occasions, there may be a special need to encourage\nthe widest possible use of a certain library, so that it becomes a de-facto\nstandard. To achieve this, non-free programs must be allowed to use the\nlibrary. A more frequent case is that a free library does the same job as\nwidely used non-free libraries. In this case, there is little to gain by\nlimiting the free library to free software only, so we use the Lesser\nGeneral Public License.\n\nIn other cases, permission to use a particular library in non-free programs\nenables a greater number of people to use a large body of free\nsoftware. For example, permission to use the GNU C Library in non-free\nprograms enables many more people to use the whole GNU operating system, as\nwell as its variant, the GNU/Linux operating system.\n\nAlthough the Lesser General Public License is Less protective of the users'\nfreedom, it does ensure that the user of a program that is linked with the\nLibrary has the freedom and the wherewithal to run that program using a\nmodified version of the Library.\n\nThe precise terms and conditions for copying, distribution and modification\nfollow. Pay close attention to the difference between a \"work based on the\nlibrary\" and a \"work that uses the library\". The former contains code\nderived from the library, whereas the latter must be combined with the\nlibrary in order to run.\n\nTERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n0. This License Agreement applies to any software library or other program\n   which contains a notice placed by the copyright holder or other\n   authorized party saying it may be distributed under the terms of this\n   Lesser General Public License (also called \"this License\"). Each\n   licensee is addressed as \"you\".\n\n   A \"library\" means a collection of software functions and/or data\n   prepared so as to be conveniently linked with application programs\n   (which use some of those functions and data) to form executables.\n\n   The \"Library\", below, refers to any such software library or work which\n   has been distributed under these terms. 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  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/MIT",
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  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/openocd-0.12.0/preferred/gfdl-1.2.texi.readme",
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  },
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But this requirement does not apply\nif neither you nor any third party retains the ability to install\nmodified object code on the User Product (for example, the work has\nbeen installed in ROM).\n\n  The requirement to provide Installation Information does not include a\nrequirement to continue to provide support service, warranty, or updates\nfor a work that has been modified or installed by the recipient, or for\nthe User Product in which it has been modified or installed.  Access to a\nnetwork may be denied when the modification itself materially and\nadversely affects the operation of the network or violates the rules and\nprotocols for communication across the network.\n\n  Corresponding Source conveyed, and Installation Information provided,\nin accord with this section must be in a format that is publicly\ndocumented (and with an implementation available to the public in\nsource code form), and must require no special password or key for\nunpacking, reading or copying.\n\n  7. Additional Terms.\n\n  \"Additional permissions\" are terms that supplement the terms of this\nLicense by making exceptions from one or more of its conditions.\nAdditional permissions that are applicable to the entire Program shall\nbe treated as though they were included in this License, to the extent\nthat they are valid under applicable law.  If additional permissions\napply only to part of the Program, that part may be used separately\nunder those permissions, but the entire Program remains governed by\nthis License without regard to the additional permissions.\n\n  When you convey a copy of a covered work, you may at your option\nremove any additional permissions from that copy, or from any part of\nit.  (Additional permissions may be written to require their own\nremoval in certain cases when you modify the work.)  You may place\nadditional permissions on material, added by you to a covered work,\nfor which you have or can give appropriate copyright permission.\n\n  Notwithstanding any other provision of this License, for material you\nadd to a covered work, you may (if authorized by the copyright holders of\nthat material) supplement the terms of this License with terms:\n\n    a) Disclaiming warranty or limiting liability differently from the\n    terms of sections 15 and 16 of this License; or\n\n    b) Requiring preservation of specified reasonable legal notices or\n    author attributions in that material or in the Appropriate Legal\n    Notices displayed by works containing it; or\n\n    c) Prohibiting misrepresentation of the origin of that material, or\n    requiring that modified versions of such material be marked in\n    reasonable ways as different from the original version; or\n\n    d) Limiting the use for publicity purposes of names of licensors or\n    authors of the material; or\n\n    e) Declining to grant rights under trademark law for use of some\n    trade names, trademarks, or service marks; or\n\n    f) Requiring indemnification of licensors and authors of that\n    material by anyone who conveys the material (or modified versions of\n    it) with contractual assumptions of liability to the recipient, for\n    any liability that these contractual assumptions directly impose on\n    those licensors and authors.\n\n  All other non-permissive additional terms are considered \"further\nrestrictions\" within the meaning of section 10.  If the Program as you\nreceived it, or any part of it, contains a notice stating that it is\ngoverned by this License along with a term that is a further\nrestriction, you may remove that term.  If a license document contains\na further restriction but permits relicensing or conveying under this\nLicense, you may add to a covered work material governed by the terms\nof that license document, provided that the further restriction does\nnot survive such relicensing or conveying.\n\n  If you add terms to a covered work in accord with this section, you\nmust place, in the relevant source files, a statement of the\nadditional terms that apply to those files, or a notice indicating\nwhere to find the applicable terms.\n\n  Additional terms, permissive or non-permissive, may be stated in the\nform of a separately written license, or stated as exceptions;\nthe above requirements apply either way.\n\n  8. Termination.\n\n  You may not propagate or modify a covered work except as expressly\nprovided under this License.  Any attempt otherwise to propagate or\nmodify it is void, and will automatically terminate your rights under\nthis License (including any patent licenses granted under the third\nparagraph of section 11).\n\n  However, if you cease all violation of this License, then your\nlicense from a particular copyright holder is reinstated (a)\nprovisionally, unless and until the copyright holder explicitly and\nfinally terminates your license, and (b) permanently, if the copyright\nholder fails to notify you of the violation by some reasonable means\nprior to 60 days after the cessation.\n\n  Moreover, your license from a particular copyright holder is\nreinstated permanently if the copyright holder notifies you of the\nviolation by some reasonable means, this is the first time you have\nreceived notice of violation of this License (for any work) from that\ncopyright holder, and you cure the violation prior to 30 days after\nyour receipt of the notice.\n\n  Termination of your rights under this section does not terminate the\nlicenses of parties who have received copies or rights from you under\nthis License.  If your rights have been terminated and not permanently\nreinstated, you do not qualify to receive new licenses for the same\nmaterial under section 10.\n\n  9. Acceptance Not Required for Having Copies.\n\n  You are not required to accept this License in order to receive or\nrun a copy of the Program.  Ancillary propagation of a covered work\noccurring solely as a consequence of using peer-to-peer transmission\nto receive a copy likewise does not require acceptance.  However,\nnothing other than this License grants you permission to propagate or\nmodify any covered work.  These actions infringe copyright if you do\nnot accept this License.  Therefore, by modifying or propagating a\ncovered work, you indicate your acceptance of this License to do so.\n\n  10. Automatic Licensing of Downstream Recipients.\n\n  Each time you convey a covered work, the recipient automatically\nreceives a license from the original licensors, to run, modify and\npropagate that work, subject to this License.  You are not responsible\nfor enforcing compliance by third parties with this License.\n\n  An \"entity transaction\" is a transaction transferring control of an\norganization, or substantially all assets of one, or subdividing an\norganization, or merging organizations.  If propagation of a covered\nwork results from an entity transaction, each party to that\ntransaction who receives a copy of the work also receives whatever\nlicenses to the work the party's predecessor in interest had or could\ngive under the previous paragraph, plus a right to possession of the\nCorresponding Source of the work from the predecessor in interest, if\nthe predecessor has it or can get it with reasonable efforts.\n\n  You may not impose any further restrictions on the exercise of the\nrights granted or affirmed under this License.  For example, you may\nnot impose a license fee, royalty, or other charge for exercise of\nrights granted under this License, and you may not initiate litigation\n(including a cross-claim or counterclaim in a lawsuit) alleging that\nany patent claim is infringed by making, using, selling, offering for\nsale, or importing the Program or any portion of it.\n\n  11. Patents.\n\n  A \"contributor\" is a copyright holder who authorizes use under this\nLicense of the Program or a work on which the Program is based.  The\nwork thus licensed is called the contributor's \"contributor version\".\n\n  A contributor's \"essential patent claims\" are all patent claims\nowned or controlled by the contributor, whether already acquired or\nhereafter acquired, that would be infringed by some manner, permitted\nby this License, of making, using, or selling its contributor version,\nbut do not include claims that would be infringed only as a\nconsequence of further modification of the contributor version.  For\npurposes of this definition, \"control\" includes the right to grant\npatent sublicenses in a manner consistent with the requirements of\nthis License.\n\n  Each contributor grants you a non-exclusive, worldwide, royalty-free\npatent license under the contributor's essential patent claims, to\nmake, use, sell, offer for sale, import and otherwise run, modify and\npropagate the contents of its contributor version.\n\n  In the following three paragraphs, a \"patent license\" is any express\nagreement or commitment, however denominated, not to enforce a patent\n(such as an express permission to practice a patent or covenant not to\nsue for patent infringement).  To \"grant\" such a patent license to a\nparty means to make such an agreement or commitment not to enforce a\npatent against the party.\n\n  If you convey a covered work, knowingly relying on a patent license,\nand the Corresponding Source of the work is not available for anyone\nto copy, free of charge and under the terms of this License, through a\npublicly available network server or other readily accessible means,\nthen you must either (1) cause the Corresponding Source to be so\navailable, or (2) arrange to deprive yourself of the benefit of the\npatent license for this particular work, or (3) arrange, in a manner\nconsistent with the requirements of this License, to extend the patent\nlicense to downstream recipients.  \"Knowingly relying\" means you have\nactual knowledge that, but for the patent license, your conveying the\ncovered work in a country, or your recipient's use of the covered work\nin a country, would infringe one or more identifiable patents in that\ncountry that you have reason to believe are valid.\n\n  If, pursuant to or in connection with a single transaction or\narrangement, you convey, or propagate by procuring conveyance of, a\ncovered work, and grant a patent license to some of the parties\nreceiving the covered work authorizing them to use, propagate, modify\nor convey a specific copy of the covered work, then the patent license\nyou grant is automatically extended to all recipients of the covered\nwork and works based on it.\n\n  A patent license is \"discriminatory\" if it does not include within\nthe scope of its coverage, prohibits the exercise of, or is\nconditioned on the non-exercise of one or more of the rights that are\nspecifically granted under this License.  You may not convey a covered\nwork if you are a party to an arrangement with a third party that is\nin the business of distributing software, under which you make payment\nto the third party based on the extent of your activity of conveying\nthe work, and under which the third party grants, to any of the\nparties who would receive the covered work from you, a discriminatory\npatent license (a) in connection with copies of the covered work\nconveyed by you (or copies made from those copies), or (b) primarily\nfor and in connection with specific products or compilations that\ncontain the covered work, unless you entered into that arrangement,\nor that patent license was granted, prior to 28 March 2007.\n\n  Nothing in this License shall be construed as excluding or limiting\nany implied license or other defenses to infringement that may\notherwise be available to you under applicable patent law.\n\n  12. No Surrender of Others' Freedom.\n\n  If conditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot convey a\ncovered work so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you may\nnot convey it at all.  For example, if you agree to terms that obligate you\nto collect a royalty for further conveying from those to whom you convey\nthe Program, the only way you could satisfy both those terms and this\nLicense would be to refrain entirely from conveying the Program.\n\n  13. Use with the GNU Affero General Public License.\n\n  Notwithstanding any other provision of this License, you have\npermission to link or combine any covered work with a work licensed\nunder version 3 of the GNU Affero General Public License into a single\ncombined work, and to convey the resulting work.  The terms of this\nLicense will continue to apply to the part which is the covered work,\nbut the special requirements of the GNU Affero General Public License,\nsection 13, concerning interaction through a network will apply to the\ncombination as such.\n\n  14. Revised Versions of this License.\n\n  The Free Software Foundation may publish revised and/or new versions of\nthe GNU General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\n  Each version is given a distinguishing version number.  If the\nProgram specifies that a certain numbered version of the GNU General\nPublic License \"or any later version\" applies to it, you have the\noption of following the terms and conditions either of that numbered\nversion or of any later version published by the Free Software\nFoundation.  If the Program does not specify a version number of the\nGNU General Public License, you may choose any version ever published\nby the Free Software Foundation.\n\n  If the Program specifies that a proxy can decide which future\nversions of the GNU General Public License can be used, that proxy's\npublic statement of acceptance of a version permanently authorizes you\nto choose that version for the Program.\n\n  Later license versions may give you additional or different\npermissions.  However, no additional obligations are imposed on any\nauthor or copyright holder as a result of your choosing to follow a\nlater version.\n\n  15. Disclaimer of Warranty.\n\n  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY\nAPPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT\nHOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY\nOF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,\nTHE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\nPURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM\nIS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF\nALL NECESSARY SERVICING, REPAIR OR CORRECTION.\n\n  16. Limitation of Liability.\n\n  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS\nTHE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY\nGENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE\nUSE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF\nDATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD\nPARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),\nEVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF\nSUCH DAMAGES.\n\n  17. Interpretation of Sections 15 and 16.\n\n  If the disclaimer of warranty and limitation of liability provided\nabove cannot be given local legal effect according to their terms,\nreviewing courts shall apply local law that most closely approximates\nan absolute waiver of all civil liability in connection with the\nProgram, unless a warranty or assumption of liability accompanies a\ncopy of the Program in return for a fee.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nstate the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software: you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation, either version 3 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License\n    along with this program.  If not, see <https://www.gnu.org/licenses/>.\n\nAlso add information on how to contact you by electronic and paper mail.\n\n  If the program does terminal interaction, make it output a short\nnotice like this when it starts in an interactive mode:\n\n    <program>  Copyright (C) <year>  <name of author>\n    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, your program's commands\nmight be different; for a GUI interface, you would use an \"about box\".\n\n  You should also get your employer (if you work as a programmer) or school,\nif any, to sign a \"copyright disclaimer\" for the program, if necessary.\nFor more information on this, and how to apply and follow the GNU GPL, see\n<https://www.gnu.org/licenses/>.\n\n  The GNU General Public License does not permit incorporating your program\ninto proprietary programs.  If your program is a subroutine library, you\nmay consider it more useful to permit linking proprietary applications with\nthe library.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.  But first, please read\n<https://www.gnu.org/licenses/why-not-lgpl.html>.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/AUTHORS",
    "content": "Original authors\n----------------\nJames Henstridge  <james@daa.com.au>     original pkg-config\nTim Janik  <timj@gtk.org>                the PKG_CHECK_VERSION macro\nHavoc Pennington <hp@redhat.com>         rewrite in C\nScott James Remnant <scott@netsplit.com> m4 cleanups and maintainer\n\t\t\t\t\t for a while\n\nMaintainer\n----------\nTollef Fog Heen <tfheen@err.no>\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/COPYING",
    "content": "                    GNU GENERAL PUBLIC LICENSE\n                       Version 2, June 1991\n\n Copyright (C) 1989, 1991 Free Software Foundation, Inc.,\n 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  By contrast, the GNU General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users.  This\nGeneral Public License applies to most of the Free Software\nFoundation's software and to any other program whose authors commit to\nusing it.  (Some other Free Software Foundation software is covered by\nthe GNU Lesser General Public License instead.)  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthis service if you wish), that you receive source code or can get it\nif you want it, that you can change the software or use pieces of it\nin new free programs; and that you know you can do these things.\n\n  To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have.  You must make sure that they, too, receive or can get the\nsource code.  And you must show them these terms so they know their\nrights.\n\n  We protect your rights with two steps: (1) copyright the software, and\n(2) offer you this license which gives you legal permission to copy,\ndistribute and/or modify the software.\n\n  Also, for each author's protection and ours, we want to make certain\nthat everyone understands that there is no warranty for this free\nsoftware.  If the software is modified by someone else and passed on, we\nwant its recipients to know that what they have is not the original, so\nthat any problems introduced by others will not reflect on the original\nauthors' reputations.\n\n  Finally, any free program is threatened constantly by software\npatents.  We wish to avoid the danger that redistributors of a free\nprogram will individually obtain patent licenses, in effect making the\nprogram proprietary.  To prevent this, we have made it clear that any\npatent must be licensed for everyone's free use or not licensed at all.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n                    GNU GENERAL PUBLIC LICENSE\n   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n  0. This License applies to any program or other work which contains\na notice placed by the copyright holder saying it may be distributed\nunder the terms of this General Public License.  The \"Program\", below,\nrefers to any such program or work, and a \"work based on the Program\"\nmeans either the Program or any derivative work under copyright law:\nthat is to say, a work containing the Program or a portion of it,\neither verbatim or with modifications and/or translated into another\nlanguage.  (Hereinafter, translation is included without limitation in\nthe term \"modification\".)  Each licensee is addressed as \"you\".\n\nActivities other than copying, distribution and modification are not\ncovered by this License; they are outside its scope.  The act of\nrunning the Program is not restricted, and the output from the Program\nis covered only if its contents constitute a work based on the\nProgram (independent of having been made by running the Program).\nWhether that is true depends on what the Program does.\n\n  1. You may copy and distribute verbatim copies of the Program's\nsource code as you receive it, in any medium, provided that you\nconspicuously and appropriately publish on each copy an appropriate\ncopyright notice and disclaimer of warranty; keep intact all the\nnotices that refer to this License and to the absence of any warranty;\nand give any other recipients of the Program a copy of this License\nalong with the Program.\n\nYou may charge a fee for the physical act of transferring a copy, and\nyou may at your option offer warranty protection in exchange for a fee.\n\n  2. You may modify your copy or copies of the Program or any portion\nof it, thus forming a work based on the Program, and copy and\ndistribute such modifications or work under the terms of Section 1\nabove, provided that you also meet all of these conditions:\n\n    a) You must cause the modified files to carry prominent notices\n    stating that you changed the files and the date of any change.\n\n    b) You must cause any work that you distribute or publish, that in\n    whole or in part contains or is derived from the Program or any\n    part thereof, to be licensed as a whole at no charge to all third\n    parties under the terms of this License.\n\n    c) If the modified program normally reads commands interactively\n    when run, you must cause it, when started running for such\n    interactive use in the most ordinary way, to print or display an\n    announcement including an appropriate copyright notice and a\n    notice that there is no warranty (or else, saying that you provide\n    a warranty) and that users may redistribute the program under\n    these conditions, and telling the user how to view a copy of this\n    License.  (Exception: if the Program itself is interactive but\n    does not normally print such an announcement, your work based on\n    the Program is not required to print an announcement.)\n\nThese requirements apply to the modified work as a whole.  If\nidentifiable sections of that work are not derived from the Program,\nand can be reasonably considered independent and separate works in\nthemselves, then this License, and its terms, do not apply to those\nsections when you distribute them as separate works.  But when you\ndistribute the same sections as part of a whole which is a work based\non the Program, the distribution of the whole must be on the terms of\nthis License, whose permissions for other licensees extend to the\nentire whole, and thus to each and every part regardless of who wrote it.\n\nThus, it is not the intent of this section to claim rights or contest\nyour rights to work written entirely by you; rather, the intent is to\nexercise the right to control the distribution of derivative or\ncollective works based on the Program.\n\nIn addition, mere aggregation of another work not based on the Program\nwith the Program (or with a work based on the Program) on a volume of\na storage or distribution medium does not bring the other work under\nthe scope of this License.\n\n  3. You may copy and distribute the Program (or a work based on it,\nunder Section 2) in object code or executable form under the terms of\nSections 1 and 2 above provided that you also do one of the following:\n\n    a) Accompany it with the complete corresponding machine-readable\n    source code, which must be distributed under the terms of Sections\n    1 and 2 above on a medium customarily used for software interchange; or,\n\n    b) Accompany it with a written offer, valid for at least three\n    years, to give any third party, for a charge no more than your\n    cost of physically performing source distribution, a complete\n    machine-readable copy of the corresponding source code, to be\n    distributed under the terms of Sections 1 and 2 above on a medium\n    customarily used for software interchange; or,\n\n    c) Accompany it with the information you received as to the offer\n    to distribute corresponding source code.  (This alternative is\n    allowed only for noncommercial distribution and only if you\n    received the program in object code or executable form with such\n    an offer, in accord with Subsection b above.)\n\nThe source code for a work means the preferred form of the work for\nmaking modifications to it.  For an executable work, complete source\ncode means all the source code for all modules it contains, plus any\nassociated interface definition files, plus the scripts used to\ncontrol compilation and installation of the executable.  However, as a\nspecial exception, the source code distributed need not include\nanything that is normally distributed (in either source or binary\nform) with the major components (compiler, kernel, and so on) of the\noperating system on which the executable runs, unless that component\nitself accompanies the executable.\n\nIf distribution of executable or object code is made by offering\naccess to copy from a designated place, then offering equivalent\naccess to copy the source code from the same place counts as\ndistribution of the source code, even though third parties are not\ncompelled to copy the source along with the object code.\n\n  4. You may not copy, modify, sublicense, or distribute the Program\nexcept as expressly provided under this License.  Any attempt\notherwise to copy, modify, sublicense or distribute the Program is\nvoid, and will automatically terminate your rights under this License.\nHowever, parties who have received copies, or rights, from you under\nthis License will not have their licenses terminated so long as such\nparties remain in full compliance.\n\n  5. You are not required to accept this License, since you have not\nsigned it.  However, nothing else grants you permission to modify or\ndistribute the Program or its derivative works.  These actions are\nprohibited by law if you do not accept this License.  Therefore, by\nmodifying or distributing the Program (or any work based on the\nProgram), you indicate your acceptance of this License to do so, and\nall its terms and conditions for copying, distributing or modifying\nthe Program or works based on it.\n\n  6. Each time you redistribute the Program (or any work based on the\nProgram), the recipient automatically receives a license from the\noriginal licensor to copy, distribute or modify the Program subject to\nthese terms and conditions.  You may not impose any further\nrestrictions on the recipients' exercise of the rights granted herein.\nYou are not responsible for enforcing compliance by third parties to\nthis License.\n\n  7. If, as a consequence of a court judgment or allegation of patent\ninfringement or for any other reason (not limited to patent issues),\nconditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot\ndistribute so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you\nmay not distribute the Program at all.  For example, if a patent\nlicense would not permit royalty-free redistribution of the Program by\nall those who receive copies directly or indirectly through you, then\nthe only way you could satisfy both it and this License would be to\nrefrain entirely from distribution of the Program.\n\nIf any portion of this section is held invalid or unenforceable under\nany particular circumstance, the balance of the section is intended to\napply and the section as a whole is intended to apply in other\ncircumstances.\n\nIt is not the purpose of this section to induce you to infringe any\npatents or other property right claims or to contest validity of any\nsuch claims; this section has the sole purpose of protecting the\nintegrity of the free software distribution system, which is\nimplemented by public license practices.  Many people have made\ngenerous contributions to the wide range of software distributed\nthrough that system in reliance on consistent application of that\nsystem; it is up to the author/donor to decide if he or she is willing\nto distribute software through any other system and a licensee cannot\nimpose that choice.\n\nThis section is intended to make thoroughly clear what is believed to\nbe a consequence of the rest of this License.\n\n  8. If the distribution and/or use of the Program is restricted in\ncertain countries either by patents or by copyrighted interfaces, the\noriginal copyright holder who places the Program under this License\nmay add an explicit geographical distribution limitation excluding\nthose countries, so that distribution is permitted only in or among\ncountries not thus excluded.  In such case, this License incorporates\nthe limitation as if written in the body of this License.\n\n  9. The Free Software Foundation may publish revised and/or new versions\nof the General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\nEach version is given a distinguishing version number.  If the Program\nspecifies a version number of this License which applies to it and \"any\nlater version\", you have the option of following the terms and conditions\neither of that version or of any later version published by the Free\nSoftware Foundation.  If the Program does not specify a version number of\nthis License, you may choose any version ever published by the Free Software\nFoundation.\n\n  10. If you wish to incorporate parts of the Program into other free\nprograms whose distribution conditions are different, write to the author\nto ask for permission.  For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this.  Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n                            NO WARRANTY\n\n  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\nREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\nINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\nOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\nYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\nPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGES.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software; you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation; either version 2 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License along\n    with this program; if not, write to the Free Software Foundation, Inc.,\n    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n\nAlso add information on how to contact you by electronic and paper mail.\n\nIf the program is interactive, make it output a short notice like this\nwhen it starts in an interactive mode:\n\n    Gnomovision version 69, Copyright (C) year name of author\n    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, the commands you use may\nbe called something other than `show w' and `show c'; they could even be\nmouse-clicks or menu items--whatever suits your program.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the program, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the program\n  `Gnomovision' (which makes passes at compilers) written by James Hacker.\n\n  <signature of Ty Coon>, 1 April 1989\n  Ty Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into\nproprietary programs.  If your program is a subroutine library, you may\nconsider it more useful to permit linking proprietary applications with the\nlibrary.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/NEWS",
    "content": "pkg-config 0.29.2\n=================\n\n- Improved pkg-config's recursive package list expansion performance.\n  Thanks to Matthew Hanna for the fix.\n- Handle an empty prefix setting correctly when --define-prefix is used.\n  (#97453)\n- Lazily load pc files instead of reading all available pc files during\n  initialization. Thanks to Marco Diego Aurélio Mesquita for the fix.\n  (#98215)\n- Check the CPATH environment variable when determining system include\n  paths like GCC does. Document the system search path behavior. Thanks\n  to v4hn for the fix. (#99224)\n- Make PKG_CHECK_MODULES show the module list rather than the variable\n  prefix in configure output. Thanks to Russ Albery for the fix.\n  (#98334)\n- Fix bundled glib build with GCC 6. (#98334)\n- Handle -isystem and -idirafter when PKG_CONFIG_SYSROOT_DIR is set.\n  (#97337)\n- Check the INCLUDE environment variable when determining system include\n  paths on Windows builds when --msvc-syntax is used. (#94729)\n\npkg-config 0.29.1\n=================\n\n- Fixed a regression from 0.29 with unquoting values queried with\n  --variable. In some cases, this would cause shell special characters to\n  be escaped in ways they weren't before. Instead, the unquoting only\n  occurs if the value appears to be quoted. (#93284)\n- Add support for building pkg-config with Microsoft Visual Studio.\n  Thanks to Chun-wei Fan for the fix. (#92489)\n- Allow overriding pkg-config variables with environment variables. By\n  setting an environment variable of the form\n  PKG_CONFIG_$PACKAGE_$VARIABLE, a pkg-config variable can be set\n  globally without always having to pass --define-variable. Thanks to\n  Alex Larsson for the fix. (#90917)\n- Honor -Wl,-framework in addition to -framework so that multiple\n  frameworks are handled on OSX. (#1278)\n- Fix the OSX build using --with-internal-glib. Thanks to Rudá Moura for\n  the initial fix and Adam Mercer for testing the final patch. (#92902)\n\npkg-config 0.29\n===\n\n- Fixed a regression from 0.28 in system -L flag handling. If the pc\n  file has multiple system -L flags, every other flag will be left as\n  is. Thanks to Andrew Oakley for the fix. (#78077)\n- Quoting of variables queried through --variable is removed so that the\n  output can be used verbatim in subsequent shell commands. Thanks to\n  Marek Kasik for the fix. (#67904)\n- Fixed a regression from 0.28 in -L flag handling on Windows. A .libs\n  suffix was inadvertantly being added to the library path.\n- Added a --validate option to check pc file syntax. This works just\n  like --exists, but package dependencies are disabled. (#7000)\n- Added the PKG_PREREQ autoconf macro. Whereas PKG_PROG_PKG_CONFIG is\n  used to check the version of the pkg-config tool, this is used to\n  check the version of the pkg-config autoconf macros in use.\n- Added the PKG_CHECK_MODULES_STATIC autoconf macro. This will\n  temporarily add --static to the pkg-config calls while invoking\n  PKG_CHECK_MODULES. (#19541)\n- Many fixes to the testsuite for Windows. It should now pass for a\n  MinGW, Cygwin, and cross-compiled MinGW using Wine for test execution.\n  (#66939)\n- More consistent handling of prefix redefinition. On Windows, the\n  prefix was always being redefined based on the pc file path. This\n  feature can now be enabled or disabled at runtime on all platforms\n  using the --define-prefix and --dont-define-prefix options. (#63602)\n- Continue listing packages with --list-all even if there are errors in\n  pc files. (#26615)\n- Various documentation improvements. (#62018, #62374, #66155)\n- Fixed a bug when multiple -isystem arguments are used. (#72584)\n- pkg-config is now built with largefile support to ensure that it works\n  correctly on filesystems with 64 bit inodes. Thanks to Peter Jones for\n  the fix. (#90078)\n- Bugs fixed: 7000, 19541, 26615, 62018, 62374, 63602, 66155, 66939,\n  67904, 70690, 72584, 78077, 80378, 80380, 89267, 90078, 90437, 92002.\n\npkg-config 0.28\n===\n- Fixed a pair of long-standing and intertwined bugs involving unwanted\n  removal of flags. The first is that other Libs flags like -Wl are now\n  kept in context order with -l flags. The second is that aggressive\n  removal of all duplicate arguments has been scaled back so that just\n  consecutive duplicate arguments are removed. One result of this change\n  is that some flags could be repeated in the final output, especially\n  flags from non-pkg-config packages like -lm. Since pkg-config rarely\n  has enough knowledge here about the right thing to do, we throw the\n  duplicate arguments at the compiler/linker and trust it will do the\n  right thing.\n- Fixed an old bug to allow circular Requires. This fix brings along a\n  small behavior change in that pkg-config resolves requires depth\n  first, causing some lower level flags to show up earlier in the output\n  than previously.\n- Cleaned up many corner-case bugs and ambiguous behavior in\n  pkg-config's interface. Thanks to Michał Górny for finding so many of\n  these.\n- New autoconf macro PKG_CHECK_VAR for reading variables from .pc files.\n- Default to suppressing -L/lib and/or -L/lib64 like their /usr\n  counterparts.\n- To help support multiarch scenarios out of the box, $host-pkg-config\n  is now installed unless --disable-host-tool is passed to configure.\n- Added optional gcov usage through the --with-gcov configure option. As\n  a result, many more tests were added to greatly increase the coverage\n  of the code to 86% of executed lines on a Fedora 18 machine.\n- Bugs fixed: 130, 7331, 16101, 17053, 19950, 34504, 48098, 54231,\n  54271, 54379, 54384, 54386, 54388, 54389, 54390, 54391, 54427, 54463,\n  54716, 57078, 58363, 59435.\n\npkg-config 0.27.1\n===\n\n - Various fixes for using the internal glib snapshot. It should now be\n   usable pretty much everywhere with the exception that universal\n   builds are not supported on OS X.\n - Remove usage of gettext from the internal glib to avoid gettext and\n   libintl dependencies.\n - Update internal glib snapshot to 2.32.4.\n - Fix check for POSIX shell used in tests to work better.\n - Handle spaces in autodetected prefix on Windows.\n - Bugs fixed 3550, 51883, 52031, 53493.\n\npkg-config 0.27\n===\n\n - Drop usage of popt for equivalent API in glib2.\n - Add back an internal snapshot of glib2 to break circular dependency.\n   This can be used by passing --with-internal-glib to configure. On\n   Windows it may still be required to use an installed glib.\n - Fix --exists to check for Requires and Requires.private. This ensures\n   that all necessary packages are installed prior to using --cflags,\n   --libs, etc.\n - Various fixes for MinGW which should allow it to be used unpatched on\n   that system.\n - New autoconf macros PKG_INSTALLDIR and PKG_NOARCH_INSTALLDIR to help\n   determine the .pc file install directory.\n - Fix handling of --exact/atleast/max-version vs. =/>=/<=.\n - Fix errors in man page source.\n - Ensure testing only searches in the check directory.\n - Bump glib requirement to 2.16 to avoid deprecated\n   g_win32_get_package_installation_subdirectory().\n - Autotools refresh and update. The required versions now are\n   autoconf-2.62, automake-1.11 and libtool-2.2.\n - Use g_alloca from glib instead of figuring out alloca ourselves.\n - Remove search for setresuid & setreuid only needed for internal popt.\n - Bugs fixed: 833, 2458, 5214, 5326, 5703, 6074, 8653, 9135, 9143,\n   9584, 10652, 11464, 14396, 17053, 23922, 28776, 29011, 29801, 31699,\n   31700, 32622, 34382, 37266, 39646, 41081, 43149, 44843, 45599, 45742,\n   48743\n\npkg-config 0.26\n===\n\n - Build system fixes\n - More tests\n - pkg.m4 fixups which makes autoconf 2.66 happier.\n - Drop support for legacy -config scripts.  Those should already be\n   gone and cause problems in cross-compilation environments.\n - Drop embedded glib\n - Fix up pkg.m4 to handle the case of --exists working and --cflags\n   or --libs failing.\n - Various documentation updates\n - Allow $() through without escaping it.\n - Add --with-system-include-path instead of hard-coding\n   /usr/include.\n\npkg-config 0.25\n===\n\n - 0.24 included a too strict whitespace/shell metacharacter filter\n   leading to some legal characters like = and : being escaped in the\n   output.  This has been fixed.\n - when building with newer and external libpopt, it would be confused\n   over being asked to split an empty string, leading to errors with\n   packages that included empty fields in their .pc files.\n - Make the COPYING file explicitly GPLv2.  The COPYING file in 0.24\n   was inadvertently GPLv3 rather than the correct GPLv2.\n - Minor changes to documentation\n\npkg-config 0.24\n===\n - Fix up bug in PKG_CONFIG_SYSROOT handling which mangled non-I and\n   non-L arguments\n - Put /usr/lib/pkgconfig and /usr/share/pkgconfig into the default\n   search path when no prefix is passed to configure.\n - Portability fixes for Windows and NetBSD\n - Various man page updates\n - Add logging support to log how pkg-config is being called.\n - Skip Requires.private unless we need them for Cflags\n - Add a variable, pc_path to the compiled-in pkg-config package that\n   you can query for the compiled-in PKG_CONFIG_PC_PATH.\n - Various updates to pkg.m4.\n - Update rpmvercmp with bugfixes from upstream.\n - Add introductory guide to pkg-config, thanks to Dan Nicholson for\n   the patch.\n - Add listing of variables in a package\n - Make it possible to use external popt.\n - Add --print-provides and --print-requires(-private) options\n - Add support for paths containing whitespace and shell metacharacters\n\npkg-config 0.23\n===\n - Add support for setting sysroot through PKG_CONFIG_SYSROOT_DIR in\n   the environment.\n - Update included glib to 1.2.10.\n - Other minor fixes, including a segfault.\n\npkg-config 0.22\n===\n - Make Requires.private a whole lot more useful by traversing the\n   whole tree, not just the top-level, for Cflags.\n - Add support for using the system glib.\n - Update URL to pkg-config website\n - Fix some win32 problems.\n - Other minor fixes.\n\npkg-config 0.21\n===\n - Fix some cosmetic output from pkg.m4\n - Fix build problems with !gcc due to always passing -Wall\n - Documentation fixes\n - We now always add the Cflags from packages we depend on, whether\n   they are public or private dependencies.  The discussion surrouding\n   this change can be found in http://bugs.debian.org/340904 .\n - Add internal pkg-config package which can be queried for version\n   number and other information.\n\npkg-config 0.20\n===\n - Fix test suite to work on Solaris.  Yay non-POSIX /bin/sh :-(\n - Fix segfault on --help with gcc4.  Fix segfault on bigendian arches\n   in some cases.\n - Win32 fixes\n - Add --short-errors, now used by pkg.m4 if available.  This gives a\n   better error message if some libraries can't be found.\n\npkg-config 0.19\n===\n - Fix a segfault\n - Fix default search path\n - Fix cosmetic bug in pkg.m4 where AC_MSG_RESULT wasn't called in\n   some cases.\n\npkg-config 0.18.1\n===\n - Fix up pkg.m4 to not end up with pkg_failed=untried always.\n\npkg-config 0.18\n===\n - The inter-library dependencies check was too tight and caused\n problems if one used the --no-undefined flag to libtool on Solaris\n (since it there expands to -Wl,-z,defs which disallows undefined\n symbols).  Add a new name to .pc files: Libs.private which will not\n be listed in the output of --libs unless --static is also given.\n\n Private libraries are libraries which are needed in the case of\n static linking or on platforms not supporting inter-library\n dependencies.  They are not supposed to be used for libraries which\n are exposed through the library in question.  An example of an\n exposed library is GTK+ exposing Glib.  A common example of a private\n library is libm.\n\n Generally, if include another library's headers in your own, it's a\n public dependency and not a private one.\n\n Thanks a lot to James Henstridge for both the bug and the following\n discussion.\n\npkg-config 0.17.2\n===\n - Don't go into an infinite loop allocating more and more memory when\n   the same name is specified twice on the command line and we're in\n   \"direct dependencies only\"-mode.\n\npkg-config 0.17.1\n===\n - Now actually sets CFLAGS and LIBS instead of trying to set those in\n   a subshell.  (Only affects if you've autoreconfiscated with 0.17)\n - Fix detection of inter-library dependencies.\n\npkg-config 0.17\n===\n\n - Evaluate second argument to PKG_CHECK_MODULES again\n - Portability fixes (MacOS, BeOS, Cygwin)\n - Handle inter-library dependencies and assume those are in place if\n   the platform supports them.  Disable with --enable-indirect-deps.\n - Add initial test framework\n - Build fixes (make distcheck now works)\n\npkg-config 0.16\n===\n\n - Use a search path, rather than a single default directory.\n - Fix a bunch of bugs in glib by backporting\n - More man page fixes\n - Lots of small fixes and cleanups over the place.\n - pkg-config now grabs _PKG_* and PKG_*, so don't use variables\n   starting with that in any configure scripts.\n\npkg-config 0.15\n===\n\n - add PKG_CONFIG_LIBDIR for cross-compiling (David Schleef)\n - add --libs-only-other/--cflags-only-other (Zack Rusin)\n - apply man page fixes (Pter Breitenlohner)\n - C portability fix (David Robins)\n - fix to win32 build (Tor Lillqvist)\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/README",
    "content": "pkg-config is a script to make putting together all the build\nflags when compiling/linking a lot easier.\n\nReport bugs at http://bugzilla.freedesktop.org/\n\nTo use pkg-config, do something like the following in your configure.ac\n\n    PKG_CHECK_MODULES([GNOME], [gtk > 1.2.8 gnomeui >= 1.2.0])\n\nThis puts the neccesary include flags to compile/link something against\nlibgnomeui and all its dependencies in $(GNOME_CFLAGS), and the -L/-l flags\nfor linking in $(GNOME_LIBS).\n\nUsers can define the PKG_CONFIG environment variable to point at the\nright one, or if they cross-compile and have a correctly named pkg-config\n(eg. arm-linux-pkg-config) in their PATH that will be used in preference.\n\nUsers can also define the GNOME_CFLAGS and GNOME_LIBS environment variables\nif they think they know better, pkg-config will not be called if they do\nthat.\n\nThe \"gtk > 1.2.8\" part is only neccesary if you want to specifically check\nif libgtk is version 1.2.8 or higher. Otherwise, the flags for gtk\nwill be included automatically, since libgnomeui depends on gtk.\nSo you could just say:\n\n     PKG_CHECK_MODULES([GNOME], [gnomeui])\n\nfor any version of gnomeui.\n\nFor more info, there's even a man page, try 'man pkg-config'\n\nBuilding\n========\npkg-config depends on glib.  Note that glib build-depends on pkg-config,\nbut you can just set the corresponding environment variables (ZLIB_LIBS,\nZLIB_CFLAGS are the only needed ones when this is written) to build it.\n\npkg-config also either needs an earlier version of itself to find glib\nor you need to set GLIB_CFLAGS and GLIB_LIBS to the correct values for\nwhere it's installed in your system.\n\nIf this requirement is too cumbersome, a bundled copy of a recent glib\nstable release is included. Pass --with-internal-glib to configure to\nuse this copy.\n\nIf you're cross-compiling and you need to build the bundled glib, refer\nto the glib documentation for cross-compiling glib. In short, this will\nrequire setting some autoconf cache variables in cases where glib would\nneed to run a program to determine the correct value. See the glib\ndocumentation:\n\nhttp://developer.gnome.org/glib/stable/glib-cross-compiling.html\n\nIf you need to use the bundled glib on Mac OS X, you'll most likely need\nto build for a single architecture rather than as a universal binary.\nThis is because glib (as of version 2.32) does not support building for\nmultiple architectures out of the box. The glib2 from MacPorts or\nHomebrew may be available as a universal binary and usable for\npkg-config as described above. Nothing in pkg-config itself precludes\nbeing built as a universal binary.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/pkg-config-0.29.2/README.win32",
    "content": "pkg-config on Win32\n===================\n\nThis file describes pkg-config for \"native\" Win32. (On Cygwin,\npkg-config builds fine right out of the box. Cygwin is just another\nUnix variant, as far as pkg-config is concerned.) I don't call this\n\"native\" Win32 target MinGW, as pkg-config on Windows is supposed to\nbe useable also by MSVC users.\n\nWhen pkg-config.exe is invoked, it uses the glib function\ng_win32_get_package_installation_directory_of_module() to find the\ndirectory it's being run from. It then adds the \"lib\" and \"share\"\nsubdirectories to the pkg-config search path unless PKG_CONFIG_LIBDIR is\nset in the environment. This allows pkg-config to adjust to being\nrelocated on Windows.\n\nFor each .pc file encountered, pkg-config will replace the prefix\nvariable to the base of it's currently installed directory unless the\ncommand line option --dont-define-prefix is set. It will take the .pc\ndirectory and strip off either lib\\pkgconfig or share\\pkgconfig to\ndetermine the prefix. This allows the paths encoded in .pc files at\nbuild time to be replaced with appropriate values at runtime.\n\nIn order to use the output of pkg-config with MSVC, the option\n--msvc-syntax can be used to convert UNIX style library output to\narguments that work with MSVC. This means -Lfoo will be converted to\n/libpath:foo, and -lfoo will be converted to foo.lib.\n\nBuilding pkg-config is now supported on Visual Studio/MSVC as well.  To\nbuild it, you will need to have a glib installation.  Note that MSVC\nbuilds of glib does not have a build-time dependency on pkg-config,\nunlike the normal autotools builds.  The headers and libs either need to\nbe found in your default %INCLUDE% and %LIB% respectively, or they need\nto be found in $(GLIB_PREFIX)\\include and $(GLIB_PREFIX)\\lib respectively;\nplease see Makefile.vc for adjusting $(GLIB_PREFIX) to suit your needs.\nTo build pkg-config with MSVC, run in a Visual Studio command prompt:\n\n\"nmake /f Makefile.vc CFG=release\" (release builds) -or-\n\"nmake /f Makefile.vc CFG=debug\" (debug builds)\n\nThe resulting pkg-config.exe will be found in [release|debug]\\[win32|x64];\na 'clean' target is supported to clean up the build.  MSVC 2008\nthrough 2015 is supported; older versions may work as well but is not\ntested.  Note that building with the glib bundled with this source\ndistribution is not currently supported-the glib DLL and all of its\ndependent DLLs are required at runtime.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/AUTHORS",
    "content": "Texinfo authors.\n\n  Copyright 2003-2019 Free Software Foundation, Inc.\n  \n  Copying and distribution of this file, with or without modification,\n  are permitted in any medium without royalty provided the copyright\n  notice and this notice are preserved.\n\nAdrian Aichner\t\ttexi2html.\nOlaf Bachmann\t\ttexi2html.\nKarl Berry\t\tall files.\nPer Bothner\t\tmakeinfo/xml.c, makeinfo/docbook.c updates.\nTorsten Bronger         texinfo.dtd.\nBob Chassell\t\ttexinfo.tex, original texinfo.txi.\nLionel Cons\t\toriginal texi2html.\nAkim Demaille\t\ttexi2dvi, util/* tests.\nPatrice Dumas\t\ttexi2html, texi2html.texi, texinfo.txi, tp author.\nAlper Ersoy\t\tmakeinfo: enhancements in all files, especially\n                          html-, xml-, and docbook-related.\nBrian Fox\t\tall makeinfo/* and info/* files, info-stnd.texi.\nNoah Friedman\t\toriginal texi2dvi.\nOleg Katsitadze\t\tdoc/*\nDave Love\t\toriginal makeinfo/html.[ch].\nKarl Heinz Marbaise\toriginal makeinfo language support, most files,\n\t\t\t  texi2html manual.\nPhilippe Martin\t\toriginal makeinfo xml/docbook output.\nSergey Poznyakoff\tall files.\nDerek Price\t\ttexi2html.\nArnold Robbins\t\tliterate (texi+awk) texindex.\nPaul Rubin\t\toriginal makeinfo/multi.c.\nAndreas Schwab\t\ttexinfo.tex, configure.ac, most makeinfo files.\nGavin Smith\t\tall files.\nRichard Stallman\toriginal texinfo.tex, install-info.c,\n\t\t\ttexindex.c, texinfo.txi.\nZack Weinberg\t\ttexinfo.tex: @macro implementation.\nRalf Wildenhues\t\tutil/gendocs.sh, makeinfo/tests/*,\n\t\t\tmakeinfo/html.c, makeinfo/cmds.c, makeinfo/footnote.c,\n\t\t\tdoc/texinfo.txi,\n\t\t\tMakefile.am, configure.ac.\nEli Zaretskii\t\tall files.\n\nSee http://translationproject.org/team/index.html for the\ntranslation teams for a given language LL.  Additional info for\noriginal texi2html translations:\nfr:    Patrice Dumas and Jean-Charles Malahieude\nde:    Reinhold Kainhofer\npt_BR,\npt:    Jorge Barros de Abreu\nja:    Found in Fedora. Don't know the author.\nes:    Francisco Vila\nit:    Federico Bruni\nhu:    Dénes Harmath\n\nImages in the images directory come from the Singular project:\nhttp://www.singular.uni-kl.de/\n\nMany files included in the Texinfo distribution are copied from other\nlocations, no author information is given for those.  See util/srclist*.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/COPYING",
    "content": "                    GNU GENERAL PUBLIC LICENSE\n                       Version 3, 29 June 2007\n\n Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n                            Preamble\n\n  The GNU General Public License is a free, copyleft license for\nsoftware and other kinds of works.\n\n  The licenses for most software and other practical works are designed\nto take away your freedom to share and change the works.  By contrast,\nthe GNU General Public License is intended to guarantee your freedom to\nshare and change all versions of a program--to make sure it remains free\nsoftware for all its users.  We, the Free Software Foundation, use the\nGNU General Public License for most of our software; it applies also to\nany other work released this way by its authors.  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthem if you wish), that you receive source code or can get it if you\nwant it, that you can change the software or use pieces of it in new\nfree programs, and that you know you can do these things.\n\n  To protect your rights, we need to prevent others from denying you\nthese rights or asking you to surrender the rights.  Therefore, you have\ncertain responsibilities if you distribute copies of the software, or if\nyou modify it: responsibilities to respect the freedom of others.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must pass on to the recipients the same\nfreedoms that you received.  You must make sure that they, too, receive\nor can get the source code.  And you must show them these terms so they\nknow their rights.\n\n  Developers that use the GNU GPL protect your rights with two steps:\n(1) assert copyright on the software, and (2) offer you this License\ngiving you legal permission to copy, distribute and/or modify it.\n\n  For the developers' and authors' protection, the GPL clearly explains\nthat there is no warranty for this free software.  For both users' and\nauthors' sake, the GPL requires that modified versions be marked as\nchanged, so that their problems will not be attributed erroneously to\nauthors of previous versions.\n\n  Some devices are designed to deny users access to install or run\nmodified versions of the software inside them, although the manufacturer\ncan do so.  This is fundamentally incompatible with the aim of\nprotecting users' freedom to change the software.  The systematic\npattern of such abuse occurs in the area of products for individuals to\nuse, which is precisely where it is most unacceptable.  Therefore, we\nhave designed this version of the GPL to prohibit the practice for those\nproducts.  If such problems arise substantially in other domains, we\nstand ready to extend this provision to those domains in future versions\nof the GPL, as needed to protect the freedom of users.\n\n  Finally, every program is threatened constantly by software patents.\nStates should not allow patents to restrict development and use of\nsoftware on general-purpose computers, but in those that do, we wish to\navoid the special danger that patents applied to a free program could\nmake it effectively proprietary.  To prevent this, the GPL assures that\npatents cannot be used to render the program non-free.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n                       TERMS AND CONDITIONS\n\n  0. Definitions.\n\n  \"This License\" refers to version 3 of the GNU General Public License.\n\n  \"Copyright\" also means copyright-like laws that apply to other kinds of\nworks, such as semiconductor masks.\n\n  \"The Program\" refers to any copyrightable work licensed under this\nLicense.  Each licensee is addressed as \"you\".  \"Licensees\" and\n\"recipients\" may be individuals or organizations.\n\n  To \"modify\" a work means to copy from or adapt all or part of the work\nin a fashion requiring copyright permission, other than the making of an\nexact copy.  The resulting work is called a \"modified version\" of the\nearlier work or a work \"based on\" the earlier work.\n\n  A \"covered work\" means either the unmodified Program or a work based\non the Program.\n\n  To \"propagate\" a work means to do anything with it that, without\npermission, would make you directly or secondarily liable for\ninfringement under applicable copyright law, except executing it on a\ncomputer or modifying a private copy.  Propagation includes copying,\ndistribution (with or without modification), making available to the\npublic, and in some countries other activities as well.\n\n  To \"convey\" a work means any kind of propagation that enables other\nparties to make or receive copies.  Mere interaction with a user through\na computer network, with no transfer of a copy, is not conveying.\n\n  An interactive user interface displays \"Appropriate Legal Notices\"\nto the extent that it includes a convenient and prominently visible\nfeature that (1) displays an appropriate copyright notice, and (2)\ntells the user that there is no warranty for the work (except to the\nextent that warranties are provided), that licensees may convey the\nwork under this License, and how to view a copy of this License.  If\nthe interface presents a list of user commands or options, such as a\nmenu, a prominent item in the list meets this criterion.\n\n  1. Source Code.\n\n  The \"source code\" for a work means the preferred form of the work\nfor making modifications to it.  \"Object code\" means any non-source\nform of a work.\n\n  A \"Standard Interface\" means an interface that either is an official\nstandard defined by a recognized standards body, or, in the case of\ninterfaces specified for a particular programming language, one that\nis widely used among developers working in that language.\n\n  The \"System Libraries\" of an executable work include anything, other\nthan the work as a whole, that (a) is included in the normal form of\npackaging a Major Component, but which is not part of that Major\nComponent, and (b) serves only to enable use of the work with that\nMajor Component, or to implement a Standard Interface for which an\nimplementation is available to the public in source code form.  A\n\"Major Component\", in this context, means a major essential component\n(kernel, window system, and so on) of the specific operating system\n(if any) on which the executable work runs, or a compiler used to\nproduce the work, or an object code interpreter used to run it.\n\n  The \"Corresponding Source\" for a work in object code form means all\nthe source code needed to generate, install, and (for an executable\nwork) run the object code and to modify the work, including scripts to\ncontrol those activities.  However, it does not include the work's\nSystem Libraries, or general-purpose tools or generally available free\nprograms which are used unmodified in performing those activities but\nwhich are not part of the work.  For example, Corresponding Source\nincludes interface definition files associated with source files for\nthe work, and the source code for shared libraries and dynamically\nlinked subprograms that the work is specifically designed to require,\nsuch as by intimate data communication or control flow between those\nsubprograms and other parts of the work.\n\n  The Corresponding Source need not include anything that users\ncan regenerate automatically from other parts of the Corresponding\nSource.\n\n  The Corresponding Source for a work in source code form is that\nsame work.\n\n  2. Basic Permissions.\n\n  All rights granted under this License are granted for the term of\ncopyright on the Program, and are irrevocable provided the stated\nconditions are met.  This License explicitly affirms your unlimited\npermission to run the unmodified Program.  The output from running a\ncovered work is covered by this License only if the output, given its\ncontent, constitutes a covered work.  This License acknowledges your\nrights of fair use or other equivalent, as provided by copyright law.\n\n  You may make, run and propagate covered works that you do not\nconvey, without conditions so long as your license otherwise remains\nin force.  You may convey covered works to others for the sole purpose\nof having them make modifications exclusively for you, or provide you\nwith facilities for running those works, provided that you comply with\nthe terms of this License in conveying all material for which you do\nnot control copyright.  Those thus making or running the covered works\nfor you must do so exclusively on your behalf, under your direction\nand control, on terms that prohibit them from making any copies of\nyour copyrighted material outside their relationship with you.\n\n  Conveying under any other circumstances is permitted solely under\nthe conditions stated below.  Sublicensing is not allowed; section 10\nmakes it unnecessary.\n\n  3. Protecting Users' Legal Rights From Anti-Circumvention Law.\n\n  No covered work shall be deemed part of an effective technological\nmeasure under any applicable law fulfilling obligations under article\n11 of the WIPO copyright treaty adopted on 20 December 1996, or\nsimilar laws prohibiting or restricting circumvention of such\nmeasures.\n\n  When you convey a covered work, you waive any legal power to forbid\ncircumvention of technological measures to the extent such circumvention\nis effected by exercising rights under this License with respect to\nthe covered work, and you disclaim any intention to limit operation or\nmodification of the work as a means of enforcing, against the work's\nusers, your or third parties' legal rights to forbid circumvention of\ntechnological measures.\n\n  4. Conveying Verbatim Copies.\n\n  You may convey verbatim copies of the Program's source code as you\nreceive it, in any medium, provided that you conspicuously and\nappropriately publish on each copy an appropriate copyright notice;\nkeep intact all notices stating that this License and any\nnon-permissive terms added in accord with section 7 apply to the code;\nkeep intact all notices of the absence of any warranty; and give all\nrecipients a copy of this License along with the Program.\n\n  You may charge any price or no price for each copy that you convey,\nand you may offer support or warranty protection for a fee.\n\n  5. Conveying Modified Source Versions.\n\n  You may convey a work based on the Program, or the modifications to\nproduce it from the Program, in the form of source code under the\nterms of section 4, provided that you also meet all of these conditions:\n\n    a) The work must carry prominent notices stating that you modified\n    it, and giving a relevant date.\n\n    b) The work must carry prominent notices stating that it is\n    released under this License and any conditions added under section\n    7.  This requirement modifies the requirement in section 4 to\n    \"keep intact all notices\".\n\n    c) You must license the entire work, as a whole, under this\n    License to anyone who comes into possession of a copy.  This\n    License will therefore apply, along with any applicable section 7\n    additional terms, to the whole of the work, and all its parts,\n    regardless of how they are packaged.  This License gives no\n    permission to license the work in any other way, but it does not\n    invalidate such permission if you have separately received it.\n\n    d) If the work has interactive user interfaces, each must display\n    Appropriate Legal Notices; however, if the Program has interactive\n    interfaces that do not display Appropriate Legal Notices, your\n    work need not make them do so.\n\n  A compilation of a covered work with other separate and independent\nworks, which are not by their nature extensions of the covered work,\nand which are not combined with it such as to form a larger program,\nin or on a volume of a storage or distribution medium, is called an\n\"aggregate\" if the compilation and its resulting copyright are not\nused to limit the access or legal rights of the compilation's users\nbeyond what the individual works permit.  Inclusion of a covered work\nin an aggregate does not cause this License to apply to the other\nparts of the aggregate.\n\n  6. Conveying Non-Source Forms.\n\n  You may convey a covered work in object code form under the terms\nof sections 4 and 5, provided that you also convey the\nmachine-readable Corresponding Source under the terms of this License,\nin one of these ways:\n\n    a) Convey the object code in, or embodied in, a physical product\n    (including a physical distribution medium), accompanied by the\n    Corresponding Source fixed on a durable physical medium\n    customarily used for software interchange.\n\n    b) Convey the object code in, or embodied in, a physical product\n    (including a physical distribution medium), accompanied by a\n    written offer, valid for at least three years and valid for as\n    long as you offer spare parts or customer support for that product\n    model, to give anyone who possesses the object code either (1) a\n    copy of the Corresponding Source for all the software in the\n    product that is covered by this License, on a durable physical\n    medium customarily used for software interchange, for a price no\n    more than your reasonable cost of physically performing this\n    conveying of source, or (2) access to copy the\n    Corresponding Source from a network server at no charge.\n\n    c) Convey individual copies of the object code with a copy of the\n    written offer to provide the Corresponding Source.  This\n    alternative is allowed only occasionally and noncommercially, and\n    only if you received the object code with such an offer, in accord\n    with subsection 6b.\n\n    d) Convey the object code by offering access from a designated\n    place (gratis or for a charge), and offer equivalent access to the\n    Corresponding Source in the same way through the same place at no\n    further charge.  You need not require recipients to copy the\n    Corresponding Source along with the object code.  If the place to\n    copy the object code is a network server, the Corresponding Source\n    may be on a different server (operated by you or a third party)\n    that supports equivalent copying facilities, provided you maintain\n    clear directions next to the object code saying where to find the\n    Corresponding Source.  Regardless of what server hosts the\n    Corresponding Source, you remain obligated to ensure that it is\n    available for as long as needed to satisfy these requirements.\n\n    e) Convey the object code using peer-to-peer transmission, provided\n    you inform other peers where the object code and Corresponding\n    Source of the work are being offered to the general public at no\n    charge under subsection 6d.\n\n  A separable portion of the object code, whose source code is excluded\nfrom the Corresponding Source as a System Library, need not be\nincluded in conveying the object code work.\n\n  A \"User Product\" is either (1) a \"consumer product\", which means any\ntangible personal property which is normally used for personal, family,\nor household purposes, or (2) anything designed or sold for incorporation\ninto a dwelling.  In determining whether a product is a consumer product,\ndoubtful cases shall be resolved in favor of coverage.  For a particular\nproduct received by a particular user, \"normally used\" refers to a\ntypical or common use of that class of product, regardless of the status\nof the particular user or of the way in which the particular user\nactually uses, or expects or is expected to use, the product.  A product\nis a consumer product regardless of whether the product has substantial\ncommercial, industrial or non-consumer uses, unless such uses represent\nthe only significant mode of use of the product.\n\n  \"Installation Information\" for a User Product means any methods,\nprocedures, authorization keys, or other information required to install\nand execute modified versions of a covered work in that User Product from\na modified version of its Corresponding Source.  The information must\nsuffice to ensure that the continued functioning of the modified object\ncode is in no case prevented or interfered with solely because\nmodification has been made.\n\n  If you convey an object code work under this section in, or with, or\nspecifically for use in, a User Product, and the conveying occurs as\npart of a transaction in which the right of possession and use of the\nUser Product is transferred to the recipient in perpetuity or for a\nfixed term (regardless of how the transaction is characterized), the\nCorresponding Source conveyed under this section must be accompanied\nby the Installation Information.  But this requirement does not apply\nif neither you nor any third party retains the ability to install\nmodified object code on the User Product (for example, the work has\nbeen installed in ROM).\n\n  The requirement to provide Installation Information does not include a\nrequirement to continue to provide support service, warranty, or updates\nfor a work that has been modified or installed by the recipient, or for\nthe User Product in which it has been modified or installed.  Access to a\nnetwork may be denied when the modification itself materially and\nadversely affects the operation of the network or violates the rules and\nprotocols for communication across the network.\n\n  Corresponding Source conveyed, and Installation Information provided,\nin accord with this section must be in a format that is publicly\ndocumented (and with an implementation available to the public in\nsource code form), and must require no special password or key for\nunpacking, reading or copying.\n\n  7. Additional Terms.\n\n  \"Additional permissions\" are terms that supplement the terms of this\nLicense by making exceptions from one or more of its conditions.\nAdditional permissions that are applicable to the entire Program shall\nbe treated as though they were included in this License, to the extent\nthat they are valid under applicable law.  If additional permissions\napply only to part of the Program, that part may be used separately\nunder those permissions, but the entire Program remains governed by\nthis License without regard to the additional permissions.\n\n  When you convey a copy of a covered work, you may at your option\nremove any additional permissions from that copy, or from any part of\nit.  (Additional permissions may be written to require their own\nremoval in certain cases when you modify the work.)  You may place\nadditional permissions on material, added by you to a covered work,\nfor which you have or can give appropriate copyright permission.\n\n  Notwithstanding any other provision of this License, for material you\nadd to a covered work, you may (if authorized by the copyright holders of\nthat material) supplement the terms of this License with terms:\n\n    a) Disclaiming warranty or limiting liability differently from the\n    terms of sections 15 and 16 of this License; or\n\n    b) Requiring preservation of specified reasonable legal notices or\n    author attributions in that material or in the Appropriate Legal\n    Notices displayed by works containing it; or\n\n    c) Prohibiting misrepresentation of the origin of that material, or\n    requiring that modified versions of such material be marked in\n    reasonable ways as different from the original version; or\n\n    d) Limiting the use for publicity purposes of names of licensors or\n    authors of the material; or\n\n    e) Declining to grant rights under trademark law for use of some\n    trade names, trademarks, or service marks; or\n\n    f) Requiring indemnification of licensors and authors of that\n    material by anyone who conveys the material (or modified versions of\n    it) with contractual assumptions of liability to the recipient, for\n    any liability that these contractual assumptions directly impose on\n    those licensors and authors.\n\n  All other non-permissive additional terms are considered \"further\nrestrictions\" within the meaning of section 10.  If the Program as you\nreceived it, or any part of it, contains a notice stating that it is\ngoverned by this License along with a term that is a further\nrestriction, you may remove that term.  If a license document contains\na further restriction but permits relicensing or conveying under this\nLicense, you may add to a covered work material governed by the terms\nof that license document, provided that the further restriction does\nnot survive such relicensing or conveying.\n\n  If you add terms to a covered work in accord with this section, you\nmust place, in the relevant source files, a statement of the\nadditional terms that apply to those files, or a notice indicating\nwhere to find the applicable terms.\n\n  Additional terms, permissive or non-permissive, may be stated in the\nform of a separately written license, or stated as exceptions;\nthe above requirements apply either way.\n\n  8. Termination.\n\n  You may not propagate or modify a covered work except as expressly\nprovided under this License.  Any attempt otherwise to propagate or\nmodify it is void, and will automatically terminate your rights under\nthis License (including any patent licenses granted under the third\nparagraph of section 11).\n\n  However, if you cease all violation of this License, then your\nlicense from a particular copyright holder is reinstated (a)\nprovisionally, unless and until the copyright holder explicitly and\nfinally terminates your license, and (b) permanently, if the copyright\nholder fails to notify you of the violation by some reasonable means\nprior to 60 days after the cessation.\n\n  Moreover, your license from a particular copyright holder is\nreinstated permanently if the copyright holder notifies you of the\nviolation by some reasonable means, this is the first time you have\nreceived notice of violation of this License (for any work) from that\ncopyright holder, and you cure the violation prior to 30 days after\nyour receipt of the notice.\n\n  Termination of your rights under this section does not terminate the\nlicenses of parties who have received copies or rights from you under\nthis License.  If your rights have been terminated and not permanently\nreinstated, you do not qualify to receive new licenses for the same\nmaterial under section 10.\n\n  9. Acceptance Not Required for Having Copies.\n\n  You are not required to accept this License in order to receive or\nrun a copy of the Program.  Ancillary propagation of a covered work\noccurring solely as a consequence of using peer-to-peer transmission\nto receive a copy likewise does not require acceptance.  However,\nnothing other than this License grants you permission to propagate or\nmodify any covered work.  These actions infringe copyright if you do\nnot accept this License.  Therefore, by modifying or propagating a\ncovered work, you indicate your acceptance of this License to do so.\n\n  10. Automatic Licensing of Downstream Recipients.\n\n  Each time you convey a covered work, the recipient automatically\nreceives a license from the original licensors, to run, modify and\npropagate that work, subject to this License.  You are not responsible\nfor enforcing compliance by third parties with this License.\n\n  An \"entity transaction\" is a transaction transferring control of an\norganization, or substantially all assets of one, or subdividing an\norganization, or merging organizations.  If propagation of a covered\nwork results from an entity transaction, each party to that\ntransaction who receives a copy of the work also receives whatever\nlicenses to the work the party's predecessor in interest had or could\ngive under the previous paragraph, plus a right to possession of the\nCorresponding Source of the work from the predecessor in interest, if\nthe predecessor has it or can get it with reasonable efforts.\n\n  You may not impose any further restrictions on the exercise of the\nrights granted or affirmed under this License.  For example, you may\nnot impose a license fee, royalty, or other charge for exercise of\nrights granted under this License, and you may not initiate litigation\n(including a cross-claim or counterclaim in a lawsuit) alleging that\nany patent claim is infringed by making, using, selling, offering for\nsale, or importing the Program or any portion of it.\n\n  11. Patents.\n\n  A \"contributor\" is a copyright holder who authorizes use under this\nLicense of the Program or a work on which the Program is based.  The\nwork thus licensed is called the contributor's \"contributor version\".\n\n  A contributor's \"essential patent claims\" are all patent claims\nowned or controlled by the contributor, whether already acquired or\nhereafter acquired, that would be infringed by some manner, permitted\nby this License, of making, using, or selling its contributor version,\nbut do not include claims that would be infringed only as a\nconsequence of further modification of the contributor version.  For\npurposes of this definition, \"control\" includes the right to grant\npatent sublicenses in a manner consistent with the requirements of\nthis License.\n\n  Each contributor grants you a non-exclusive, worldwide, royalty-free\npatent license under the contributor's essential patent claims, to\nmake, use, sell, offer for sale, import and otherwise run, modify and\npropagate the contents of its contributor version.\n\n  In the following three paragraphs, a \"patent license\" is any express\nagreement or commitment, however denominated, not to enforce a patent\n(such as an express permission to practice a patent or covenant not to\nsue for patent infringement).  To \"grant\" such a patent license to a\nparty means to make such an agreement or commitment not to enforce a\npatent against the party.\n\n  If you convey a covered work, knowingly relying on a patent license,\nand the Corresponding Source of the work is not available for anyone\nto copy, free of charge and under the terms of this License, through a\npublicly available network server or other readily accessible means,\nthen you must either (1) cause the Corresponding Source to be so\navailable, or (2) arrange to deprive yourself of the benefit of the\npatent license for this particular work, or (3) arrange, in a manner\nconsistent with the requirements of this License, to extend the patent\nlicense to downstream recipients.  \"Knowingly relying\" means you have\nactual knowledge that, but for the patent license, your conveying the\ncovered work in a country, or your recipient's use of the covered work\nin a country, would infringe one or more identifiable patents in that\ncountry that you have reason to believe are valid.\n\n  If, pursuant to or in connection with a single transaction or\narrangement, you convey, or propagate by procuring conveyance of, a\ncovered work, and grant a patent license to some of the parties\nreceiving the covered work authorizing them to use, propagate, modify\nor convey a specific copy of the covered work, then the patent license\nyou grant is automatically extended to all recipients of the covered\nwork and works based on it.\n\n  A patent license is \"discriminatory\" if it does not include within\nthe scope of its coverage, prohibits the exercise of, or is\nconditioned on the non-exercise of one or more of the rights that are\nspecifically granted under this License.  You may not convey a covered\nwork if you are a party to an arrangement with a third party that is\nin the business of distributing software, under which you make payment\nto the third party based on the extent of your activity of conveying\nthe work, and under which the third party grants, to any of the\nparties who would receive the covered work from you, a discriminatory\npatent license (a) in connection with copies of the covered work\nconveyed by you (or copies made from those copies), or (b) primarily\nfor and in connection with specific products or compilations that\ncontain the covered work, unless you entered into that arrangement,\nor that patent license was granted, prior to 28 March 2007.\n\n  Nothing in this License shall be construed as excluding or limiting\nany implied license or other defenses to infringement that may\notherwise be available to you under applicable patent law.\n\n  12. No Surrender of Others' Freedom.\n\n  If conditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot convey a\ncovered work so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you may\nnot convey it at all.  For example, if you agree to terms that obligate you\nto collect a royalty for further conveying from those to whom you convey\nthe Program, the only way you could satisfy both those terms and this\nLicense would be to refrain entirely from conveying the Program.\n\n  13. Use with the GNU Affero General Public License.\n\n  Notwithstanding any other provision of this License, you have\npermission to link or combine any covered work with a work licensed\nunder version 3 of the GNU Affero General Public License into a single\ncombined work, and to convey the resulting work.  The terms of this\nLicense will continue to apply to the part which is the covered work,\nbut the special requirements of the GNU Affero General Public License,\nsection 13, concerning interaction through a network will apply to the\ncombination as such.\n\n  14. Revised Versions of this License.\n\n  The Free Software Foundation may publish revised and/or new versions of\nthe GNU General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\n  Each version is given a distinguishing version number.  If the\nProgram specifies that a certain numbered version of the GNU General\nPublic License \"or any later version\" applies to it, you have the\noption of following the terms and conditions either of that numbered\nversion or of any later version published by the Free Software\nFoundation.  If the Program does not specify a version number of the\nGNU General Public License, you may choose any version ever published\nby the Free Software Foundation.\n\n  If the Program specifies that a proxy can decide which future\nversions of the GNU General Public License can be used, that proxy's\npublic statement of acceptance of a version permanently authorizes you\nto choose that version for the Program.\n\n  Later license versions may give you additional or different\npermissions.  However, no additional obligations are imposed on any\nauthor or copyright holder as a result of your choosing to follow a\nlater version.\n\n  15. Disclaimer of Warranty.\n\n  THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY\nAPPLICABLE LAW.  EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT\nHOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY\nOF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,\nTHE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\nPURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM\nIS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF\nALL NECESSARY SERVICING, REPAIR OR CORRECTION.\n\n  16. Limitation of Liability.\n\n  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS\nTHE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY\nGENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE\nUSE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF\nDATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD\nPARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),\nEVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF\nSUCH DAMAGES.\n\n  17. Interpretation of Sections 15 and 16.\n\n  If the disclaimer of warranty and limitation of liability provided\nabove cannot be given local legal effect according to their terms,\nreviewing courts shall apply local law that most closely approximates\nan absolute waiver of all civil liability in connection with the\nProgram, unless a warranty or assumption of liability accompanies a\ncopy of the Program in return for a fee.\n\n                     END OF TERMS AND CONDITIONS\n\n            How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nstate the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software: you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation, either version 3 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License\n    along with this program.  If not, see <https://www.gnu.org/licenses/>.\n\nAlso add information on how to contact you by electronic and paper mail.\n\n  If the program does terminal interaction, make it output a short\nnotice like this when it starts in an interactive mode:\n\n    <program>  Copyright (C) <year>  <name of author>\n    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, your program's commands\nmight be different; for a GUI interface, you would use an \"about box\".\n\n  You should also get your employer (if you work as a programmer) or school,\nif any, to sign a \"copyright disclaimer\" for the program, if necessary.\nFor more information on this, and how to apply and follow the GNU GPL, see\n<https://www.gnu.org/licenses/>.\n\n  The GNU General Public License does not permit incorporating your program\ninto proprietary programs.  If your program is a subroutine library, you\nmay consider it more useful to permit linking proprietary applications with\nthe library.  If this is what you want to do, use the GNU Lesser General\nPublic License instead of this License.  But first, please read\n<https://www.gnu.org/licenses/why-not-lgpl.html>.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/NEWS",
    "content": "This NEWS file records noteworthy changes, very tersely.\nSee the manual for detailed information.\n\n  Copyright 1992-2023 Free Software Foundation, Inc.\n\n  Copying and distribution of this file, with or without modification,\n  are permitted in any medium without royalty provided the copyright\n  notice and this notice are preserved.\n\n------------------------------------------------------------------------------\n\n7.0.3 (26 March 2023)\nThis is a bug-fix release with minimal changes.\n\n* texi2any\n  . fix performance regression when Perl binary extension (XS) modules\n    are not being used (e.g. with TEXINFO_XS=omit)\n\n* info\n  . further fix of recoding of UTF-8 files to ASCII to avoid text\n    disappearing from nodes\n  . avoid possible freeze at start of a file with `-v nodeline=pointers'\n\n\f\n7.0.2 (22 January 2023)\nThis is a bug-fix release with minimal changes.\n\n* texi2any\n  . do not distribute architecture-dependent files\n  . build fixed on OpenIndiana 11\n\n* info\n  . further fix of recoding of UTF-8 files to ASCII\n  . fix check for presence of man pages on Solaris\n\n* install-info\n  . fix build by avoiding function name clash on some platforms\n  . compiler warning re strncat silenced\n\n\f\n7.0.1 (30 November 2022)\nThis is a bug-fix release with minimal changes.\n\n* texi2any\n  . avoid crashes on empty @image argument and other potential crashes\n    (with \"Can't use an undefined value as an ARRAY reference\" message)\n  . avoid hang on @ref command inside section command\n\n* info\n  . fix recoding of UTF-8 files to ASCII when run in C locale\n\n* js\n  . index search fixed for new HTML output\n  . some obsolete files removed from distribution\n\n\f\n7.0 (7 November 2022)\n* texi2any\n . LaTeX added as an output format, selected with --latex\n . EPUB 3 added as an output format, selected with --epub3\n . reform throughout the code in general\n . thorough review of character encoding issues\n . new customization variables involved with character encoding:\n     INPUT_FILE_NAME_ENCODING, OUTPUT_FILE_NAME_ENCODING,\n     DOC_ENCODING_FOR_INPUT_FILE_NAME, DOC_ENCODING_FOR_OUTPUT_FILE_NAME,\n     MESSAGE_ENCODING and COMMAND_LINE_ENCODING\n . warn if full-text commands (@ref, @footnote, @anchor) appear in @w\n . new variable NO_TOP_NODE_OUTPUT\n . IGNORE_BEFORE_SETFILENAME variable removed.  former effect\n   is now always on.\n . HTML output:\n     . use manual_name_html as output directory for split HTML instead of\n       manual_name or manual_name.html\n     . default DOCTYPE declaration changed to plain HTML5 style rather than\n       HTML4 DTD reference\n     . output only the CSS rules that are needed in an output file\n     . remove CSS_LINES variable and add SHOW_BUILTIN_CSS_RULES\n       (custom CSS can still be output using EXTRA_HEAD)\n     . use <code> tag for the output of @t and @verb instead of <tt>\n     . use <abbr> for @acronym instead of <acronym>\n     . link to table of contents from short table of contents only if a\n       table of contents is actually output\n     . prefix classes from @example arguments with `user-'\n     . percent encode URL in @url/@uref, @email, @image and external\n       manual file\n     . new USE_XML_SYNTAX, HTML_ROOT_ELEMENT_ATTRIBUTES and\n       NO_CUSTOM_HTML_ATTRIBUTE variables can be used to output\n       valid XHTML\n     . systematic addition of classes attribute in HTML elements based on the\n       Texinfo @-command names.  renaming of class attributes to avoid\n       confusion with @-commands formatting and describe the role in the\n       document rather than the formatting style.\n     . COPIABLE_ANCHORS renamed to COPIABLE_LINKS\n     . do not add a title by default; SHOW_TITLE or NO_TOP_NODE_OUTPUT has\n       to be set\n     . USE_TITLEPAGE_FOR_TITLE is now true by default\n     . L2H variable removed, replaced by HTML_MATH set to `l2h'\n     . rename OVERVIEW_LINK_TO_TOC to SHORT_TOC_LINK_TO_TOC\n     . rename BEFORE_OVERVIEW to BEFORE_SHORT_TOC_LINE\n     . rename AFTER_OVERVIEW to AFTER_SHORT_TOC_LINES\n     . remove PRE_ABOUT, AFTER_ABOUT, and add PROGRAM_NAME_IN_ABOUT\n     . remove KEEP_TOP_EXTERNAL_REF\n     . new variables IGNORE_REF_TO_TOP_NODE_UP, CONVERT_TO_LATEX_IN_MATH,\n       HTMLXREF_MODE and HTMLXREF_FILE\n . DocBook output:\n     . do not output Top node or text before the first @node or sectioning\n       @-command.  NO_TOP_NODE_OUTPUT can be set to false to output Top node\n       for now.\n     . replace @definfocenlose defined @-commands by the argument as-is\n       to be more consistent with printed output\n . HTML/DocBook output:\n     . USE_NUMERIC_ENTITY changed to mean to use numeric entities instead\n       of named entities.  former effect is now always on.\n     . ENABLE_ENCODING_USE_ENTITY variable removed.  former effect is now\n       always off.\n . Info output\n     . quote problematic node names (with :, comma...) by default\n     . new customization variable ASCII_PUNCTUATION to use plain ASCII\n       characters for quotation marks and a few other symbols\n\n* texinfo.tex\n  . `@microtype on' uses microtypography in formatting for pdfTeX and LuaTeX\n  . do not ignore @part page immediately following Top node\n  . do `@set txicodevaristt' to get slanted typewriter for @var in code,\n    `@clear txicodevaristt' to use slanted, variable-width roman font for\n    @var everywhere.  flag is @set by default, but we may turn this off\n    in the future.\n  . new file doc/texinfo-zh.tex for Texinfo documents in Chinese.\n    new support file doc/txi-zh.tex for Chinese.  doc/short-sample-zh.texi is\n    a sample document.\n\n* info\n  . better support for index entries containing parentheses\n  . better support for getting bold text etc. when displaying manpages\n  . bug fixed where the first index entry in a file could be ignored\n  . M-C-f closes as well as opens footnotes window\n  . do not crash if run in Brazilian Portuguese locale\n\n* Language\n  . @deftype* commands use typewriter font in argument list\n  . new commands @latex, @iflatex, @ifnotlatex for new LaTeX output format\n  . do `@set txidefnamenospace' to omit space after a definition name\n\n* Other\n  . build fixed for glibc 2.34\n\n\f\n6.8 (3 July 2021)\n* Language\n  . new command @displaymath for formatting of mathematical notation\n  . @example takes an argument to specify the language\n  . mark these commands as deprecated, not to be used:\n    @centerchap, @definfoenclose, @refill, @inforef.\n  . new paper size @bsixpaper\n\n* texi2any\n  . should be faster as Perl XS parser is enabled by default\n  . SHOW_MENU customization variable replaced by FORMAT_MENU.\n    FORMAT_MENU set to 'menu' is the same as SHOW_MENU set to 1, and\n    FORMAT_MENU set to 'nomenu' is the same as SHOW_MENU set to 0.\n  . only check menu structure if CHECK_NORMAL_MENU_STRUCTURE variable is set\n  . changes to HTML output:\n      . MathJax support for display of math.  new variables HTML_MATH,\n        MATHJAX_SCRIPT and MATHJAX_SOURCE.\n      . new variables JS_WEBLABELS and JS_WEBLABELS_FILE to support\n        JavaScript License Web Labels\n      . by default, use sectional tables of contents instead of menus\n      . use section names in links by default (configure with\n        xrefautomaticsectiontitle customization variable)\n      . CONTENTS_OUTPUT_LOCATION sets location of table of contents\n      . document sections wrapped in <div> elements\n      . new variable USE_NODE_DIRECTIONS to use node or section structure\n        for node directions\n      . copiable anchor links for definitions with COPIABLE_ANCHORS variable\n      . experimental JavaScript browsing interface enabled with INFO_JS_DIR\n      . don't add an extra period before file extension given as an argument\n        to @image if image file is not found\n\n* info\n  . support compressed dir files\n\n* texi2dvi\n  . stop on first error in input file\n\n* texinfo.tex\n  . put logical page numbers into PDF's ('page labels')\n  . put chapter numbers in the PDF outline\n  . new Finnish translation\n\n* Distribution\n  . autoconf 2.71, automake 1.16.3, gettext 0.21\n\n\f\n6.7 (23 September 2019)\n* Language:\n  . support of index subentries and sub-subentries with @subentry\n  . new commands @seeentry and @seealso in index entries\n  . no need to wrap Top node in @ifnottex - omitted automatically when\n    processed with TeX\n  . UTF-8 is the default input encoding\n\n* texi2any\n  . for HTML output, mark index nodes in menus and tables of contents\n    with the 'rel' attribute of the 'a' tag.\n  . TOP_NODE_UP is now only used in HTML if TOP_NODE_UP_URL is set.\n    Also TOP_NODE_UP should now be formatted in the output format.\n    In HTML TOP_NODE_UP should be suitable for inclusion in HTML \n    element attributes, so for instance should not contain elements.\n  . support of noderename.cnf files has been removed\n  . INPUT_PERL_ENCODING, INPUT_ENCODING_NAME, NODE_FILE_EXTENSION,\n    NODE_FILENAMES, SHORTEXTN and TOP_NODE_FILE removed as customization\n    variables.\n  . TOP_NODE_FILE_TARGET now contains the extension.\n  . error messages translated when the XS parser module is in use\n\n* texi2dvi\n  . unconditionally run in --batch mode, i.e. without stopping if there\n    is a TeX error\n  . keep on going after a TeX error if the index files changed\n  . with --tidy (or --build-dir), avoid reading index files from previous\n    runs where --tidy was not used\n\n* info\n  . for a tree search (with M-/), '}' and '{' work as well as 'M-}' and\n    'M-{' to go through the results\n\n* Distribution:\n  . Several obsolete portability checks removed\n  . gettext 0.20.1, automake 1.16.1\n\n\f\n6.6 (16 February 2019)\n* Language:\n  . new commands @&, @ampchar{}\n  . @cropmarks command removed\n  . @ctrl is no longer recognised (it was a way to insert literal\n    control characters in Info files, but deprecated since the \n    time of Texinfo version 2)\n  . \\usebracesinindexestrue is no longer recommended for using braces in\n    index entries, and has been a no-op for some time\n\n* texi2any\n  . extension modules fixed to work with the \"thread-safe locales\" of\n    Perl 5.28 and newer\n  . some code changed to stop warnings being given by newer versions of Perl\n  . for HTML output, use `id' to define link targets instead of the `name'\n    attribute on <a>\n  . A native-code implementation of the Texinfo parser has been included\n    on an experimental basis, which makes texi2any a lot faster.  Set the\n    `TEXINFO_XS_PARSER' environment variable to 1 to use.\n  . changes to HTML output:\n     . omit colon after node name in menus by default (use\n       `MENU_ENTRY_COLON' to add it back)\n     . no special CSS for commands like @smallexample\n     . new customization variable `SECTION_NAME_IN_TITLE' to use the\n       section name as the document <title>\n     . use section names instead of node names in generated menus\n  . pass on flags set with -D to TeX\n  . useless static libraries are not installed\n  . the newline after an @insertcopying is not output\n  . warning given for @multitable prototypes not in braces\n  . @indent and @noindent are not allowed inside the arguments to\n    commands where they are not meaningful\n  . @quote-arg and @allow-recursion are not recognised (these two used\n    to be recognised by makeinfo in macro definitions but were never \n    implemented in texinfo.tex)\n  . `FIX_TEXINFO' removed as a customization variable\n  . do not recognise or warn about obsolete customization variables\n\n* info\n  . debugging output with -x is not diverted to a separate infodebug file\n\n* Development:\n  . switch from Subversion to git\n     - https://savannah.gnu.org/git/?group=texinfo\n  . automake 1.16\n\n\f\n6.5 (12 September 2017)\n* info:\n  . some bugs fixed:\n    . a bug where a segfault could happen in the regex search, for\n      example when the user entered a single \\ as the search string\n    . another bug which could make nodes inaccessible in long \"split\"\n      info files\n    . a bug where it was not possible to follow a cross-reference\n      that was split across more than one line has been fixed\n  . do not fall back to a man page if following a cross-reference in an\n    info file failed\n  . if looking for a file failed, do not convert the name of a file to\n    lower-case and look for it again\n\n* texinfo.tex\n  . some faulty definitions for Unicode characters have been changed or\n    removed\n  . fix indentation in table of contents for entries that are split\n    across multiple lines\n\n* texi2dvi\n  . a bug that broke the processing of LaTeX files that did not\n    use BibTeX has been fixed\n\n* texi2any\n  . output the encoding declaration of a HTML file earlier so it\n    will always occur within first 1024 bytes of file\n  . `INLINE_INSERTCOPYING' removed as a customization variable\n\n\f\n6.4 (23 June 2017)\n* texi2any:\n  . for HTML output, place section names before the manual in page\n    titles, instead of after them, so it is easier to distinguish pages\n    if titles are truncated\n  . starting points for ordered lists beginning with 0 or a letter of\n    the alphabet are output as attributes on the <ol> tag, as was\n    case for Texinfo 4.13 and earlier\n  . a bit faster\n  . some discrepancies in paragraph formatting between Perl extension\n    modules and interpreted Perl modules have been fixed\n  . `MACRO_BODY_IGNORES_LEADING_SPACE' customization variable removed,\n    and `indent_menu_descriptions' is no longer a possible value for\n    `TREE_TRANSFORMATIONS' (as these features did not work as\n    documented)\n\n* info:\n  . the `up-line' and `down-line' commands now are like the other\n    scrolling commands and are no longer confined to a single node\n    (depending on the value of `scroll-behaviour')\n  . supplying the --all option with --index-search displays a list\n    of matching index entries\n  . the style variables like `link-style' can now be set while info\n    is running\n  . display bug fixed where color could be turned off prematurely\n  . several other bugs fixed\n  . better portability in test suite\n  . do not fall back to showing the dir node if a manual isn't found\n  . Do not attempt any kind of conversion of CR LF line endings,\n    except on MS-DOS/Windows, when it is done unconditionally.  (This \n    replaces a more complicated approach, where this conversion would \n    take place if there was a problem finding a node in a file.)  The \n    main effect of this change is that Info files with CR LF line \n    endings, which would have been produced on MS-DOS/Windows with old \n    versions of makeinfo, are only supported on such operating systems.\n  . a few of the key bindings under --vi-keys have been changed for\n    consistency or to match the documentation\n\n* texinfo.tex\n  . a DVI file with a single empty page can be output again, which\n    restores the behavior from Texinfo 6.0 and earlier\n\n* Distribution\n  . autoconf 2.69, automake 1.15, gettext 0.19.8\n\n\n\f\n6.3 (10 September 2016)\n\n* Language:\n  . The commands `@setcontentsaftertitlepage' and\n    `@setshortcontentsaftertitlepage' have been removed.\n  . @-commands are no longer supported within `@errormsg'.\n\n* texinfo.tex:\n  . For a couple of characters (opening and closing braces), use glyphs\n    from the standard TeX math fonts instead of using EC fonts which are \n    less likely to be installed.\n  . Use of user-defined macros in the text of an index entry is more\n    reliable when the text contains Texinfo @-commands.\n  . @synindex and @syncodeindex have been fixed (broken in the last\n    release).\n  . Support added for native UTF-8 support with XeTeX and LuaTeX.\n  . Support of PDF output with XeTeX improved.\n  . You can use a new file doc/texinfo-ja.tex for Texinfo documents in\n    Japanese.  doc/short-sample-ja.tex is a sample document.  New \n    support file doc/txi-ja.tex for Japanese.\n\n* texi2any:\n  . Fix handling of compiler options when building Perl extension modules.\n\n* texi2dvi:\n  . Can now process files whose absolute paths contain space characters,\n    as long a relative path to the file is given.  Better support of \n    files with unusual characters in their names.\n  . No longer exits prematurely in some circumstances (due to the script\n    running under \"set -e\").\n  . Bug fixed which made the `--command' and `--tidy' options\n    incompatible.\n\n* info:\n  . Handling of \"invalid\" value in infokey file fixed.\n\n6.2 (withdrawn)\n\n\n\f\n6.1 (06 February 2016)\n\n* Language:\n  . You can now omit the @menu from nodes with other nodes below them in\n    the document structure.  If you use \"@validatemenus off\" near the \n    start of a Texinfo file, makeinfo will, where needed, create a menu \n    for nodes lacking one given explicitly.\n  . An @setfilename line is no longer required at the start of a\n    Texinfo file.  (Be aware, though, that some other tools may require \n    it, for example Automake.)\n  . For processing with TeX, a comma is automatically provided following\n    a cross-reference command (such as @xref) when needed to separate\n    the page number from following text, so you don't need to add one\n    yourself.  See the `Parts of a Cross Reference' node in the manual\n    for details.  Behavior when followed by punctuation, as always\n    recommended previously, is unchanged.\n\n* texi2any:\n  . Some Perl modules have been rewritten in C to increase speed.\n    If Perl extensions can be created, they are used by default; \n    otherwise the pure Perl implementations are still used.\n    Disable at build time with \"configure --disable-perl-xs\".  The \n    environment variable TEXINFO_XS controls how they are used by \n    texi2any.\n  . Quotation marks are left out for node names and index entries in\n    Info output where they would have been produced by commands such\n    as @file or @option.\n  . New customization variable INFO_SPECIAL_CHARS_QUOTE to allow use of\n    a quoting mechanism for problematic constructs in Info output, for\n    example node names containing colons or commas.\n  . Commands like @heading are affected by @lowersections and @raisesections\n    again, as was the case before Texinfo 5.0.\n\n* texinfo.tex:\n  . You may explicitly specify a sort key for an index entry by preceding\n    the text of the entry with the @sortas commmand with the sort key \n    desired as a braced argument.   Additionally, you may choose to\n    ignore all occurences of the characters \\, @, <, and - using new \n    flags you can specify with @set: `txiindexbackslashignore',\n    `txiindexatsignignore', `txiindexlessthanignore', and\n    `txiindexhyphenignore' respectively.\n  . Changes to macro handling to more closely match makeinfo.  Ends of\n    lines are preserved in an argument to a macro taking a single \n    argument.\n  . By default, suppress heading line on a page with a chapter on it, to\n    avoid having the chapter title repeated.\n  . Use a larger font for arguments in a @deffn line and similar.\n  . The default indices (cp, ky and so on) now don't get a file opened\n    for them unless they are actually used.  This reduces the number of\n    files that a run of TeX produces, and also allows for a greater\n    number of user-defined indices, because you will not bump into TeX's\n    limit of 16 open files at once so soon.\n  . For initials in indices that are non-alphanumeric characters (for\n    example, backslash, or braces), avoid use of a typewriter font.  \n    This gives a more consistent appearance.\n  . Have a stronger preference for breaking a column in an index before\n    a letter heading.\n  . Formatting improvements in tables of contents and indices.  Entries\n    can extend slightly into the margin instead of being broken across \n    two lines, and text is split more evenly across lines.  Reduce \n    chance of an orphaned index entry appearing at the top of a column.\n  . Support character encodings beyond ASCII for XeTeX and LuaTeX by\n    reading file input byte-by-byte.\n\n* texi2dvi:\n  . Support for determining the output files using the `-recorder'\n    option to TeX, to help to support more TeX engines.\n\n* info:\n  . New user variables `link-style', `active-link-style', and\n    `match-style' enable customization of how cross-references and search \n    matches are highlighted.\n  . By default only the node pointers are displayed at the top of a node.\n    Customize this with the `nodeline' variable.\n  . New command M-x tree-search to search all subnodes of a node.\n  . Now tries to find referenced manuals in the same directory as the\n    current file first, before looking in search path.  Customize this\n    with new variable `follow-strategy'.\n  . The `mouse' variable is now off by default, in order not to\n    interfere with the selection of text in a terminal emulator window.\n  . `q' closes a window instead of quitting altogether if there's more\n    than one, for example if a help window is open.\n  . Several bug fixes, including:\n      . one causing the wrong position in a node to be shown when\n        following an \"anchor\" cross-reference\n      . one causing a test failure in the t/c-u-m-x-scroll-forward.sh\n        test on some platforms\n  . Internal changes to reduce memory use and increase speed of\n    searches, relative to last release\n  . The meaning of the `key-time' variable has changed when its value\n    is 0.  This value meant to wait forever in the last release, but now\n    it means that the next byte must be available immediately.\n\n* Documentation:\n  . The `info.info' file (and `info.texi' source) is no longer\n    distributed with Texinfo.  Now this manual is only in Emacs.\n\n* Distribution:\n  . automake-1.15, gettext-0.19.6.\n\n\f\n6.0 (26 June 2015)\n* Language:\n  . new commands @sub and @sup, for textual subscripts and superscripts.\n  . new command @U to insert a Unicode character by code point.\n\n* texinfo.tex:\n  . @url/@uref output in PDF now the same as in DVI, showing the url\n    even if the second argument is given, not just as a link target.\n    TeX option \\urefurlonlylinktrue gives previous behavior, of invisible urls.\n    PDF-only \\linkcolor and \\urlcolor specify colors (default black).\n\n* texi2any:\n  . customization variable TOP_NODE_UP_URL now replaces all (dir) references;\n    recommended setting for GNU packages is /manual/.\n  . new customization variable INDEX_SPECIAL_CHARS_WARNING to complain\n    when index entries contain a colon.\n  . Docbook output no longer uses <lineannotation> for @r.\n  . -D'var val' on the command line works as intended again.\n  . --plaintext output can be split.\n  . a bit faster.\n\n* info:\n  . invoking as `info foo bar' looks for bar as an index entry in manual\n    foo, if not found as a top-level menu item.\n  . invoking info with an absolute or explicitly relative file name\n    (./foo.info, /tmp/foo.info, etc.) just visits that file.\n  . separate `infokey' program has been removed - the .infokey file is\n    now read directly by Info.\n  . new option --init-file allows overriding ~/.infokey.\n  . new variable `highlight-searches' allows highlighting results from a\n    search\n  . support for mouse scrollwheel, controlled by `mouse' variable.\n  . new variable `key_time' to control how long to wait for byte\n    sequences sent by special keys.\n  . new variable `hide-note-references' alters appearance of displayed nodes\n  . new variable `infopath-no-defaults' allows omitting the compile-time\n    Info directory from the Info search path.\n  . support input of multibyte characters for searches in a UTF-8 locale.\n  . if reading an Info file that is known to be in a different character\n    encoding to that of the user's environment, convert its contents \n    when displayed and substitute missing characters\n  . new command M-x info-version.\n  . the M-x kill-node command has been removed.\n  . test suite at build time.\n\n* texindex:\n  . completely new implementation as a literate program using Texinfo\n    and (portable) awk (called TexiWeb Jr.), thanks to Arnold Robbins.\n    (Requires gawk 4.0+ if .twjr source is modified.)\n  . the -o (--output) is not supported, unless we hear of someone using it.\n  . duplicated sort keys with different display texts result in one\n    merged index entry, using the first display text.\n  . better sorting and parsing in unusual cases; most notably, { and }\n    characters can appear as initials.\n\n* install-info:\n  . handle compressed input file names containing spaces.\n  . exit successfully if --remove is given and the dir file does not exist.\n  . new option --defsection, to be used instead of \"Miscellaneous\" when\n    a section is not present in the Info file.\n\n* texi2dvi:\n  . look for the environment variable THUMBPDF_CMD instead of THUMBPDF,\n    since thumbpdf itself has used THUMBPDF for options since 2000.\n  . remove --recode and --recode-from options, since they haven't\n    worked as intended for years, so evidently no one needs them.\n\n* Distribution:\n  . new translation ca (catalan).\n  . automake-1.15, gettext-0.19.4.\n\n\f\n5.2 (26 September 2013)\n* Language:\n  . new commands @inlinefmtifelse, @inlineifset, @inlineifclear, for\n    more brace-delimited alternatives to the conditional environments.\n\n* texi2any:\n  . warns about node names, menu items, and cross-references (but not\n    index entries) containing problematic characters; can be disabled\n    with -c INFO_SPECIAL_CHARS_WARNING=0.\n\n* info:\n  . new option -x (--debug) for debugging output; -x -1 to get everything.\n  . new option -v (--variable) assigns a value to an Info variable,\n    with the usual syntax, -v VARIABLE=VALUE.\n  . new option -a (--all) instructs Info to display all documents\n    matching the command line arguments, not just the first.  In\n    conjunction with the -w option, it shows full names of all Info\n    files matching the command line arguments; with -o, it outputs all\n    matching files.\n  . new variable search-skip-screen controls the starting position for\n    repeated search commands ({ and }).  When set to On, repeated\n    searches skip the lines displayed on the screen, i.e.,\n    forward searches (}) start at the beginning of the next page, and\n    backward searches ({) start at the end of the previous page.\n  . new command display-file-info (bound to = by default, C-g in vi mode)\n    shows full file name of the node being displayed and position in it.\n\n* texi2dvi:\n  . support for biblatex+biber.\n\n* Distribution: automake-1.14, gettext-0.18.3.1.\n\n\f\n5.1 (12 March 2013)\n* texi2any:\n  . irregular sectioning trees (see 5.0 news item) produce a warning\n    rather than an error.\n  . @set in the middle of the line no longer produces a warning.\n  \n* info:\n  . lzip (.lz) compression supported.\n  \n* install-info:\n  . lzip (.lz) compression supported.\n\n* Development: switch from CVS to Subversion.\n  https://savannah.gnu.org/svn/?group=texinfo\n\n\f\n5.0 (16 February 2013)\n* Language:\n  . Texinfo commands are supported in node names.\n  . #line directives are recognized.\n  . @-commands are now recognized in raw format blocks.  Therefore, for\n    example, lone @, { and } characters in @tex, @html and similar\n    environments must be converted to the normal @@, @{, and @} commands.\n  . new commands @inlinefmt and @inlineraw for brace-delimited conditionals.\n  . new conditionals @ifcommanddefined and @ifcommandnotdefined to test\n    if a Texinfo command is available.\n  . new command @part for a group of chapters.\n  . new environments @raggedright, @smallquotation,\n      @indentedblock, and @smallindentedblock.\n  . new commands @codequoteundirected and @codequotebacktick,\n      for a better interface than \"@set txicodequoteundirected\" and\n      \"@set txicodequotebacktick\"; now respected by @kbd.\n  . new command @xrefautomaticsectiontitle to allow using section titles\n      in cross references by default, instead of node names.\n  . new commands for Texinfo special characters:\n    @atchar{} @lbracechar{} @rbracechar{} @backslashchar{} @hashchar{}.\n  . new commands @deftypefnnewline to print return types on their own lines.\n  . new command @headitemfont for the sake of template rows.\n  . new command @urefbreakstyle to control breaking of @url/@uref in TeX.\n  . new diacritic command @ogonek.\n  . new commands for Icelandic letters eth and thorn: @DH{} @dh{} @TH{} @th{}.\n  . new command @errormsg to report an error.\n  . five-argument xrefs can refer to a whole manual, by omitting the\n      section name and either omitting the node name or using \"Top\".\n  . DEL (0x7f = 0177 = 127) is a true comment character (catcode 14 in TeX).\n\n* texi2any is the new generic converter for Texinfo that can produce all\n  supported output formats, both those from texi2dvi (PDF/DVI) and from\n  makeinfo (Info/HTML/etc.).  texi2any and makeinfo are now different\n  names for the same program; there are no differences in behavior based\n  on the program name.\n\n  The new implementation is in Perl, requiring Perl 5.7.3 (released in\n  March 2002) and its standard Encode module.\n  \n  The Perl texi2any/makeinfo both replaces and is intended to be (for\n  all practical purposes) upward-compatible with the C makeinfo.  It has\n  many new features not in the C makeinfo.  For example, cross-manual\n  references are now fully supported, and allows for extensive\n  customization of the HTML output.  See the `Generic Translator\n  texi2any' chapter in the manual (among other places) for more about\n  this reimplementation.\n  \n  The new program is, unfortunately, noticeably slower at present than\n  the C program was.  We hope all the many improvements make the new\n  version worthwhile for users nevertheless.\n\n* Intentional incompatibilities with the previous implementation of\n  makeinfo, through version 4.13:\n  \n  . The old implementation accepted a lone block of text inside @itemize,\n    @enumerate, etc., without any @item.  This is semantically\n    inconsistent, leading to problems with some backends, and thus now\n    produces a warning.\n    \n  . The old implementation accepted ``irregular'' sectioning trees.  Now,\n    when @node pointers are implicitly determined, the consistency of\n    @menu and the sectioning tree is checked.  (If node pointers are\n    explicitly specified in the document, the tree can still be irregular.)\n  \n  . The old implementation always added blank lines between function\n    definitions if they weren't already there.  Now blank lines are not\n    added.  (Both old and new implementations preserve blank lines that\n    are present.)\n    \n  . The old implementation processed macros in place, formatting the\n    replacement text with the output.  Now the replacement text is\n    textually substituted as Texinfo source.  A consequence of the old\n    behavior is that ends of lines from expansion of an @macro\n    definition did not end an @-command line-delimited argument\n    (@chapter, @center, etc.).  Now they do.  (A detailed example is in\n    the manual, node Macro Details.)\n\n* pod2texi is a new (Perl) program that uses the capabilities of\n  texi2any to translate Perl pod documentation to Texinfo.\n  \n* texinfo.tex:\n  . urls (given to @uref and @url) are broken by default at special\n    characters; behavior controllable with @urefbreakstyle.\n  . support some per-language hyphenation, when the underlying TeX\n    engine does (for instance, etex/pdfetex from TeX Live 2008 or\n    later).  Words with accented letters are still not handled properly.\n  . @title, text will be broken if needed, and @* can be used to override.\n  . new Icelandic translation: txi-is.tex.\n  . new Hungarian translation: txi-hu.tex.\n  . official updates between full package releases available at\n    http://ftpmirror.gnu.org/texinfo/texinfo.tex.\n\n* texi2dvi:\n  . new option --max-iterations.\n  . official updates between full package releases available at\n    http://ftpmirror.gnu.org/texinfo/texi2dvi.\n  \n* info:\n  . INFOPATH is determined from PATH by default, or if an element \"PATH\"\n    is specified.\n  . New command Info-virtual-index, bound to I by default, following Emacs.\n  . Info keywords not found by searches.\n  . A lower limit on the length of search patterns, default 1,\n    specified by the variable min-search-length.\n  . Use ASCII versions of images, if supplied by the document.\n  . xz compression supported.\n\n* install-info:\n  . xz compression supported.\n\n* Documentation:\n  . new appendix with a technical description of the Info file format.\n  . information on the customizations of the HTML output now possible.\n\n* Distribution:\n  . new file htmlxref.cnf is installed to support cross-manual\n    references; official updates between full package releases available\n    at http://ftpmirror.gnu.org/texinfo/htmlxref.cnf.\n  . language support for no removed/renamed to nb, per Norwegian translators.\n  . new translations: id it,\n    and document translations: eo pl.\n  . texinfo.cat file removed since it is (to our knowledge) unused.\n  . documentation license now GFDLv1.3 or later.\n  . autoconf 2.69, automake 1.13.1, gettext 0.18.2.\n\n\f\n4.13 (18 September 2008)\n\n* A reference card for Texinfo is now available, in doc/refcard.  For\n  convenience, preformatted PDF's for letter-size and A4 paper are included.\n\n* makeinfo:\n  . new option --internal-links for HTML output, to write a tsv file\n    mapping indexed/toc terms to links, for easy reference from external\n    documents.\n  . - as an input file name reads standard input. \n\n* info:\n  . support for multibyte encodings such as UTF-8.\n  . new option --show-malformed-multibytes, to display malformed multibyte\n    sequences.\n  . new environment variable INFO_MAN_COMMAND sets the name of man executable\n    (use it if you a need to override PATH settings).\n  \n* install-info:\n  . bug fix: support names with embedded periods (e.g., config.status) again.\n\n* Distribution:\n  . autoconf 2.63.\n\n\f\n4.12 (20 April 2008)\n\n* Language:\n  . new commands @clicksequence, @click, and @clickstyle for documenting\n    GUI sequences, and @arrow for the default glyph used.\n  . new commands @geq{} and @leq{} for the normal >= and <= relations.\n\n* install-info:\n  . lzma compression supported.\n  . Much work towards compatibility with Debian's independent\n    implementation.  Changes in behavior:\n    - new entries are formatted to start at column 34 by default.\n    - existing entries are replaced by default.\n    - new sections are alphabetized among existing sections.\n    - if an entry being removed is the last one in a section, the\n      section is also removed.\n  . Also many new options:\n    --section REGEX TITLE.\n    --no-indent: disable formatting of new entries.\n    --menuentry, --name: specify left-hand side of an entry.\n    --dry-run: alias for --test.\n    --regex REGEX: renamed from --section regex, adds to all sections\n      matching REGEX by default.\n    --add-once: add only to first specified or matching section.\n    --align COL: start description at column COL.\n    --calign COL: start continuation lines in description at COL.\n    --max-width COL: wrap the description at COL.\n  . New section in the Texinfo manual describing all this.\n\n* info:\n  Our goal with these changes to the default interface is to make Info\n  documents more easily and quickly readable, especially by non-experts.\n  . the PageUp and PageDown keys move through the whole document by\n    default, instead of just the current node.\n  . the h command shows the basic help, and H starts the Info tutorial.\n  . the newly-bound x command deletes the current window, e.g., within help.\n  . the scroll-step variable is set to 1 by default, for smooth scrolling.\n  . the cursor-movement-scrolls-p variable is set to 1 by default, so\n    link searches look through the whole document.\n  . regular expression searches are supported, and are the default for\n    both regular and incremental searches.\n  . the new R command toggles between regexp and literal-string searches.\n  . the new variable scroll-last-node controls scrolling at the end of\n    the last node; by default, it now simply reports there are no more\n    nodes.  To restore the old behavior, set scroll-last-node=Scroll.\n  . the precise line number specified in index entries is used if available.\n  . --usage=info shows usage for standalone Info.\n  . lzma compression supported.\n\n* Distribution:\n  . language support for no removed/renamed to nb, per Norwegian translators.\n  . new translation: es.\n  . bug fixes in make check (and elsewhere).\n  . gettext 0.17, automake 1.10.1, autoconf 2.62.\n\n\f\n4.11 (9 September 2007)\n\n* Language:\n  . @documentlanguage now supports an optional country code\n    specification after the language code, a la gettext.\n  . new command @allowcodebreaks controls breaks at _ and - within @code.\n  . new command @frenchspacing controls spacing after sentences.\n  . new command @fonttextsize allows changing body text font size to 10pt.\n  . new command @textdegree{} produces the normal degrees symbol.\n  . new command @thischapternum can be used in TeX headers/footers.\n  . new commands for quotes: @quotedblleft @quotedblright\n     @quoteleft @quoteright  @quotedblbase @quotesinglbase\n     @guillemetleft @guillemetright @guilsinglleft @guilsinglright.\n  . new option @set txicodequoteundirected produces an undirected quote\n    in code and example output, instead of the regular right quote.\n  . new option @set txicodequotebacktick produces a grave accent in\n    code and example output, instead of the regular left quote.\n* makeinfo:\n  . The @documentlanguage locale is used to translate various document strings.\n  . --enable-encoding is now the default, meaning Info and plain text\n    output use 8-bit characters given a supported @documentencoding.\n  . new option --css-ref=URL for creating a stylesheet <link> in HTML output.\n  . new option --transliterate-file-names to use a reduction-to-ASCII\n    algorithm for split HTML file names, useful for non-Latin-based languages.\n  . @enddots{} outputs three dots instead of four, for consistency with\n    texinfo.tex.\n  . the Local Variables coding: setting written by --enable-encoding now\n    comes at the very end, after the tags table, so that Emacs can find\n    it in more cases.\n  . @allow-recursion (never documented) is deprecated and produces a warning.\n  . @quote-args (never documented) is now the default behavior.\n  . centering and such take account of character widths.\n  . the --reference-limit option is now a no-op.\n  . improvements to XML and Docbook output and the DTD.\n* texinfo.tex:\n  . @thissection can now be used in custom headings, and @thischapter\n    works reliably even without @set chapternewpage.  Custom headings\n    have additional flexibility as well.\n* texi2dvi:\n  . pdftexi2dvi is a new wrapper to `texi2dvi --pdf', equal to texi2pdf,\n    for the sake of AUC-TeX which prepends `pdf' to the compilation\n    command when requested to produce PDF.\n* info:\n  . look for info files in the current directory first, by default.\n  . when calling man, use -a if no explicit section is found.\n  . avoid showing the top(1) man page for nonexistent info files.\n* install-info:\n  . new options --section-regex, --remove-exactly, --debug, --test.\n* Distribution:\n  . autoconf 2.60, automake 1.10, gettext 0.16.1.\n  . gettext support now [external].\n  . new translations: hu (Hungarian), rw (Kinyarwandan), vi (Vietnamese).\n  . most common sources imported from gnulib.\n\n4.10 (omitted)\n\n\f\n4.9 (29 June 2007)\n* GPLv3.\n* texi2dvi:\n  . new mode --build=tidy which supports compilation in a separate\n    directory, where intermediate files are preserved.\n  . new option --build-dir, to specify where the tidy build will take\n    place, either locally or globally.  This allows avoiding the clutter\n    while preserving auxiliary files.\n  . new support for AUC-TeX: texi2dvi (weakly) supports arguments a la\n    TeX such as `\\nonstopmode\\input{file.tex}'.\n  . new options --ps and --dvipdf, useful especially for pstricks documents.\n  . new option --src-specials, passed to TeX.\n* texinfo.tex:\n  . Latin1, Latin2, Latin9, and UTF-8 are supported -- only as well as\n    the Computer Modern fonts can manage, which means primarily English\n    and western European languages, to a limited extent.\n  . png and jpg images supported in pdf output.\n  . new Russian, Serbian, and Ukrainian translations for texinfo.tex:\n    txi-ru.tex, txi-sr.tex, txi-uk.tex.\n  . section names with \\ characters work properly in pdf outlines.\n  . have .toc files use @ as the escape character, instead of \\.\n\n\f\n4.8 (31 December 2004)\n* Language:\n  . new command @euro for the Euro currency symbol, and\n    @documentencoding has some support for ISO-8859-15.\n  . new command @abbr for general abbreviations.\n  . new command @slanted to typeset text in a slanted font,\n    and @sansserif to typeset in a sans serif font.\n* makeinfo:\n  . An empty first argument to cross-reference commands, such as @xref,\n    causes an error.  This change was made in 4.1, but not mentioned in NEWS.\n  . HTML output:\n    - <a name=\"...\"> constructs are added for the old-style\n      conversion of node names to HTML names, so that external references\n      to them can continue to work.\n    - \"g_t\" prefixed to targets for node names beginning with a\n      nonletter, for XHTML compatibility.\n  . Docbook output: recognize more image formats.\n* texi2dvi:\n  . new option --recode, to call recode for input character translation.\n* Distribution:\n  . new convenience script texi2pdf, equivalent to texi2dvi --pdf (from tetex).\n  . some cross-compiling support in configure && make.\n  . new configure option --disable-install-warnings, for TeX.\n    distributions which do have the files installed.\n  . automake 1.9.4.\n\n\f\n4.7 (9 April 2004)\n* Language:\n  . new commands @float, @caption, @shortcaption, @listoffloats for\n    initial implementation of floating material (figures, tables, etc).\n    Ironically, they do not yet actually float anywhere.\n  . new commands @docbook, @ifdocbook, @ifnotdocbook for conditional Docbook.\n  . new commands @ordf{} and @ordm{} for Spanish feminine/masculine ordinals.\n  . new commands @deftypecv[x] for class variables in typed OO languages.\n  . new command @registeredsymbol for the r-in-a-circle symbol.\n  . new command @headitem to make a heading row in @multitable.\n  . new command @LaTeX{} for the LaTeX logo.\n  . new command @comma{} to avoid comma-parsing problems.\n  . @url is now a synonym for @uref; new command @indicateurl has the\n    old meaning of just displaying a url as text.\n  . @quotation now accepts an optional argument for labelling the text\n      as a `Note', `Tip', etc.\n  . @defun (et al.) heading lines can now be continued with a lone @.\n  . @acronym accepts an optional argument for the meaning of the acronym.\n* makeinfo:\n  . New environment variable TEXINFO_OUTPUT_FORMAT determines the output\n    format at runtime, if no options are specified.\n  . New option --plaintext, equivalent to --no-headers with Info output.\n  . All outputs:\n    - sections are numbered by default.\n  . Info output:\n    - punctuation is inserted after @pxref and @ref, if needed to make\n      cross-references valid.\n    - line numbers included in index menus, so Info readers can go to\n      the exact line of an entry, not just a node.  Also in plaintext output.\n    - ^@^H[index^@^H] cookie included in index menus, so Info readers\n      can handle the ] etc. commands better.\n  . HTML output:\n    - new algorithm for cross-references to other manuals, for maximum\n      portability and stability.\n    - include node name in <title> with split output.\n    - @multicolumn fractions become percentages.\n    - entities used for bullets, quotes, dashes, and others.\n    - index entries are links to the exact locations.\n    - <h4> and <h5> used for @sub and @subsubsections again.\n    - accented dotless i supported.\n  . XML output: many new tags and structure to preserve more source features.\n  . Docbook output:\n    - upgraded DTD to Docbook XML 4.2, no longer using Docbook SGML.\n    - improved translation in general, for instance:\n    - line annotations and marked quotations.\n* texi2dvi:\n  . if available, use etex (pdfetex if --pdf) by default.\n  . if the input file includes thumbpdf.sty (for LaTeX), then run thumbpdf.\n  . more output if --debug.\n* texinfo.tex:\n  . @defun names are now printed in typewriter (instead of bold), and\n    within the arguments, @var text is printed in slanted typewriter.\n  . @tex code is executed inside a TeX group, so that any changes must\n    be prefixed with \\global (or the equivalent) to be effective.  (This\n    change was actually made years ago, but never made it into the NEWS.)\n* info:\n  . new option --where (aka --location, -w) to report where an Info file\n    would be found, instead of reading it.\n  . by default, output ANSI terminal escape sequences as-is; new option\n    --no-raw-escapes overrides this.\n  . use the newly-generated index line numbers.\n* Distribution:\n  . new script gendocs.sh (not installed), for use by GNU maintainers in\n    getting their manuals on the GNU web site.  Documented in\n    maintain.texi (http://www.gnu.org/prep/maintain/).\n  . Most code uses ANSI C prototypes, to some extent.\n  . New translation: nb.\n  . automake 1.8.3, autoconf 2.59, gettext 0.14.1.\n\n\f\n4.6 (10 June 2003)\n* Language:\n  . new command @/ specifies an allowable breakpoint within a line.\n  . new command @dofirstparagraphindent to control whether the first\n    paragraph following a section heading is indented.  Default is to\n    omit this indentation, unlike the output up to now.\n  . new command @indent for explicitly indenting a paragraph.\n  . makeinfo writes a new construct for @image in Info output, so that\n    graphical Info browsers (such as Emacs Info under X) can display an\n    actual image.  (Standalone Info ignores this, since it runs in a tty.)\n* makeinfo:\n  . Common:\n    - search for image files in the include file search path.\n    - warns if @value is used on an undefined variable.\n  . Info output:\n    - default --split-size now 300,000 bytes, up from 50,000.\n    - with --enable-encoding and a given @documentencoding,\n      output a Local Variables section specifying that encoding, for use\n      with Emacs.\n  . HTML output:\n    - uses <h3> at the smallest.\n    - a few css <style> definitions are included to better\n      implement @format, @display, @small..., etc.\n    - new option --css-include=FILE includes FILE in the <style>.\n    - @cartouche now outputs a <table> with a border.\n* texinfo.tex:\n  . new Polish translation txi-pl.tex.\n* texi2dvi:\n  . --command=CMD replaces --texinfo=CMD; it inserts CMD at the first\n    line of LaTeX files now, or after the @setfilename for Texinfo files.\n* info:\n  . RET now goes to the nearest xref (rather like Emacs Info),\n    instead of the next xref starting on the current line.\n* Distribution:\n  . new Romanian (ro) translation.\n  . variables now declared const where appropriate.\n  . gettext 0.12.1, automake 1.7.5.\n\n\f\n4.5 (4 February 2003)\n* info:\n  . a bug in 4.4 prevented compressed info files from being found.\n* Distribution:\n  . detect sys/ptem.h on Solaris.\n\n\f\n4.4 (31 January 2003)\n* Language:\n  . The ' (ASCII apostrophe/right quote) character is finally allowed in\n    node and anchor names.  Thus, after installing this texinfo.tex,\n    existing .aux files will cause errors!  Remove them and rerun TeX to\n    generate good ones.\n  . @value constructs are now expanded in the filename arguments to\n    @include and @verbatiminclude.\n* makeinfo:\n  . @macro names may no longer include ^ or _, for the sake of math mode.\n  . bug fix: @copying text is now reflected in tag table positions;\n    before, nodes may not have been found with a long-enough @copying.\n  . bug fix: html @verb arg is quoted properly, and does not imply\n    a paragraph break.\n* texinfo.tex:\n  . @smallexample and the like now output in a smaller font (9pt) in all\n    paper formats, not just @smallbook and @afourpaper.\n  . new translation txi-tr.tex.\n  . bug fix: <>| and other characters do not disappear when they are\n    first on a line in @verbatim.\n* install-info:\n  . bug fix: don't translate the `* Menu' info keyword.\n* info:\n  . CTRL-H is treated like DEL in incremental search.\n  . arrow keys once again work in isearch contexts under Solaris.\n* infokey:\n  . use .info key bindings before defaults.\n  . allow prefix keys to be disabled.\n* Distribution:\n  . update to GNU FDL 1.2 (http://www.gnu.org/licenses/fdl.html).\n  . getopt and other common library files updated from gnulib\n    (http://savannah.gnu.org/projects/gnulib/).\n  . autoconf 2.57, automake 1.7.2.\n\n\f\n4.3 (14 November 2002)\n* Language:\n  . new command @tie{} to do a real tie (unbreakable interword space).\n* makeinfo:\n  . html output for @defun and friends now has font changes.\n  . html output has some class attributes.\n  . xml and docbook output improved in many details.\n* texinfo.tex:\n  . new Italian translations, txi-it.tex.\n  . pdf bookmarks for unnumbered sections work.\n  . type name for @defun and friends no longer extends into margin.\n* info:\n  . automatic-footnotes now off by default, for emacs compatibility.\n  . crash when MALLOC_CHECK_=2 fixed.\n* install-info:\n  . new option --infodir synonym for --info-dir, for compatibility with\n    the Debian install-info.\n  . support for bzip2-compressed files.\n* texindex:\n  . omit initial if the entire index is under one character.\n* Distribution:\n . development sources now available under CVS, see\n   http://savannah.gnu.org/projects/texinfo/\n . Turkish message translation.\n . gettext 0.11.5, autoconf 2.54, automake 1.7.1.\n\n\f\n*** NEWS FOR ALL AUTHORS OF TEXINFO MANUALS ***\n\nAs of version 4.2, Texinfo has a command @copying to define the\ncopyright and copying permissions for a manual.  If you haven't already,\nplease switch to using it in your next release, because the historical\nmethod of doing copyright permissions using @ifinfo failed to output\ncopyright information in the HTML (or XML) formats.  The manual has\ndetailed explanations and examples.  For convenience, here's a url to\none of the relevant sections:\n  http://www.gnu.org/software/texinfo/manual/texinfo/html_node/Document-Permissions.html\n\n4.2 (1 April 2002)\n* Language:\n  . new command @copying to define copying permissions.  See above.\n  . new conditionals @ifplaintext, @ifnotplaintext for the plain text\n    (--no-headers) output format.\n  . new command @\\ to produce literal \\ inside @math, since \\ by itself\n    no longer works.\n* makeinfo:\n  . emit accesskey attributes for keyboard shortcuts to menu items.\n  . @{even,every,odd}{footing,header} are ignored by makeinfo now, so\n    they no longer need to be enclosed in @iftex.\n* texinfo.tex:\n  . bug fix for pdf-format table of contents.\n* info:\n  . bug fixes for -R (--raw-escapes).\n  . --help shows short option names.\n* Distribution:\n  . the doc.c, funs.h, and key.c files in info/ are no longer generated\n    at make time, to appease Automake's make distcheck.\n  . gettext 0.11.1, autoconf 2.53, automake 1.6 (with install-info kludge).\n\n\f\n4.1 (4 March 2002)\n* Language:\n  . new commands @verbatim and @verb for printing verbatim inserts.\n  . new command @verbatiminclude for verbatim include of files.\n  . new environment @documentdescription for defining the HTML description.\n  . new command @afivepaper for the A5 paper size.\n* makeinfo:\n  . supports xml and docbook output.\n  . supports HTML splitting by node, which is now the default.\n  . new option --split-size to control maximum size of split info files.\n  . new option --enable-encoding to enable\n* info:\n  . user-specified key bindings supported.\n  . ANSI escape sequences (as produced by groff) removed from man output\n    by default; use --raw-escapes to let them through if your terminal\n    supports them.\n  . RET terminates incremental search normally.\n* texinfo.tex:\n  . @math implies @tex, so all the usual plain TeX math is supported.\n  . smaller fonts for @smallexample, in all page sizes.\n  . improvements in the PDF support.\n* texi2dvi:\n  . new option -o to explicitly specify output filename.\n* Distribution:\n  . switch to GNU Free Documentation License (http://www.gnu.org/copyleft/).\n  . update to GNU gettext 0.11, autoconf 2.52, and automake 1.5.\n  . Danish, Swedish, and Hebrew message translations.\n\n\f\n4.0 (28 September 1999)\n* Language:\n  . New command @anchor for cross references to arbitrary points.\n  . New commands @documentlanguage sets the main document language,\n    and @documentencoding sets the document input encoding (although not\n    much is done yet with either).\n  . New command @pagesizes allows limited control of text area for typesetting.\n  . New command @acronym for abbreviations in all caps, such as `NASA'.\n  . New command @alias for simple command aliases.\n  . New command @definfoenclose for better control of info output.\n  . New commands @deftypeivar for typed instance variables of a class\n    and @deftypeop for typed operations of a class.\n  . New command @novalidate suppresses cross-reference checking and (in\n    TeX) auxiliary file creation.\n  . New commands @setcontentsaftertitlepage and\n    @setshortcontentsaftertitlepage to force printing the table of\n    contents after @end titlepage.  Also, @contents and @shortcontents\n    themselves can now appear at the beginning of the document as\n    well as the end.\n  . New markup commands: @env (for environment variables), @command (for\n    command names), @option (for command-line options).\n  . New commands @smallformat and @smalldisplay, a la @smallexample.\n  . New command @exampleindent to set indentation of example-like\n    environments a la @paragraphindent.\n  . @uref takes an optional third argument of text to show instead of\n    (rather than in addition to) the url for info and dvi output.\n  . @footnote works in an @item for a @table.\n* texinfo.tex:\n  . latest version always at ftp://ftp.gnu.org/gnu/texinfo/texinfo.tex\n    (and mirrors).\n  . implements @macro.\n  . implements @paragraphindent (except asis).\n  . @emph and @i use true italic type (cmti) instead of slanted (cmsl).\n  . implements pdf output when run with pdftex.\n  . better support for internationalization via txi-??.tex files.\n  . footnotes now set in a smaller point size.\n* makeinfo:\n  . supports HTML output with the --html option.\n  . implication of --html: @top nodes should be wrapped in @ifnottex\n    rather than @ifinfo.  @ifinfo conditionals are not expanded with --html.\n  . new option --number-sections to output chapter/section numbers.\n  . dashes and quotes are not treated specially in node names.\n  . new option --commands-in-node-names to allow @-commands in node names.\n    (Not implemented in TeX, and most likely never will be.)\n  . @emph output uses _underscores_.\n  . @image looks for .png files before .jpg.\n  . only output `Making ... file' line when verbose.\n  . allow -v as synonym for --verbose.\n  . new command line options to specify which conditionals to process\n    (but --iftex is not fully implemented).\n  . warns if @var contains any of ,[]().\n  . @quote-arg implicitly done for all one-argument macros, so commas in\n    the argument text are allowed.\n  . \\\\ required in macro body to get single \\, no other `escapes' defined.\n* info:\n  . ISO Latin 1 characters are displayed and input as-is by default.\n  . new option --vi-keys to enable vi-like and less-like key bindings.\n  . new command S does case-sensitive searching.\n  . new commands C-x n and C-x N repeat last search, respectively, in the\n    same and in reverse direction, without prompting for the string.  These\n    commands are bound to n and N under --vi-keys, like in Less.\n  . new command G menu1 menu2 ... searches for menu items from (dir),\n    as allowed on the command line.\n  . new command O (capital o, not zero) goes directly to the node that\n    describes command-line options.\n  . new command-line option --show-options causes the node which\n    describes command-line options to be the first node displayed.\n  . M-prior and M-DEL do new command info-scroll-other-window-backward.\n  . / searches like s does.\n  . If the search string includes upper-case letters, in both incremental\n    and non-incremental search, the search is case-sensitive.\n  . S searches case-sensitively even if the search string is all\n    lower-case.\n  . - makes the argument negative (so e.g. `- /' searches backward).\n  . l restores point in the window returned to.\n  . SPC/DEL do not move outside the current document.\n  . foo.info is found before foo.\n  . `info foo --index-search=bar' now searches for bar in foo's index.\n  . support for files compressed with bzip2.\n* install-info:\n  . handles gzipped dir files.\n  . sort entries into alphabetical order.\n  . install direntries only in preceding dircategory, not in all.\n  . --delete does not require the info file to exist.\n  . --delete can handle XEmacs-style dir entries.\n* texi2dvi:\n  . bug fixed: now uses only the @iftex and @tex parts of the source.\n  . process LaTeX source as well as Texinfo source.\n  . output PDF (using pdftex) with new option --pdf.\n  . handles --OPTION=ARG style of command line arguments.\n  . new option --batch for progress reports but no interaction.\n  . new option --clean to remove all auxiliary files.\n  . new option --quiet for silence (unless there are errors).\n  . new option -I for specifying directories for @include to search.\n  . handles LaTeX files (running BibTeX etc.).\n* Fixes to util/gen-dir-node and util/fix-info-dir (formerly util/update-info).\n* Distribution:\n  . Man pages included.\n  . Czech and Norwegian message translations.\n  . Various translations for texinfo.tex fixed words included.\n  . DJGPP support.\n\n\f\n3.12 (3 March 1998)\n* Elisp files removed, since they are only usefully distributed with Emacs.\n* Restore inclusion of compile-time $(infodir) to INFOPATH.\n* install-info creates a proper dir file.\n* Various portability fixes.\n\n\f\n3.11 (31 July 1997)\n* New commands:\n  - @uref to make a reference to a url; @url now only indicates such.\n  - @image to include graphics (epsf for TeX).\n  - @deftypemethod and @deftypemethodx to document methods in strongly\n    typed object-oriented languages, such as C++.\n  - @html for raw HTML.\n  - @ifnothtml @ifnotinfo @ifnottex for more precise conditionals.\n  - @kbdinputstyle to control when @kbd uses the slanted typewriter font.\n  - @email takes second optional argument.\n* texinfo.tex reads texinfo.cnf (if present) for site-wide TeX\n  configuration; for example, A4 paper sizes.\n* info:\n  - arrow keys supported.\n  - trailing : in INFOPATH appends default path.\n  - new option --index-search for online help support.\n* makeinfo:\n  - output files removed if errors unless (new option) --force.\n  - new option -P to prepend to search path.\n  - macro expansion file can be standard output.\n* install-info creates a new dir file if necessary.\n* update-info script to create a dir file from all info files.\n* Elisp: texnfo-tex.el and detexinfo.el removed from the distribution;\n  - texnfo-tex features are now part of standard TeX & Texinfo packages;\n  - makeinfo --no-headers does a better job than detexinfo.el.\n* Documentation:\n  - Updates, revisions, corrections in the manual.\n  - makeinfo.texi removed, as it was a copy of what was in texinfo.texi.\n* gettext support in sources, French and German translations included.\n* info man page removed; use the Texinfo manual.\n* Automake used, other portability fixes.\n\n3.10 (omitted)\n\n\f\n3.9 (4 October 1996)\n* makeinfo:\n  - Give a suppressible (with --no-validate) error for references\n    outside of any node.\n  - Keep track of multitable output correctly for split files; this\n    caused nodes after the first multitable to be ``undefined''.\n* install-info:\n  - Rename --infodir option to --info-dir.\n  - More robust error checking to avoid various crashes.\n* configure: Include replacements for memcpy and memmove functions in\n  the distribution, in case they are missing.\n\n\f\n3.8 (30 September 1996)\n* Define and/or document new and/or previously existing commands:\n  Accents: @\" @' @, @\" @= @^ @` @~ @H @d @dotaccent @dotless @ringaccent\n    @tieaccent @u @ubaraccent @v\n  Special characters: @AA @AE @L @O @OE @aa @ae @exclamdown @l @o @oe\n    @pounds @questiondown @ss\n  Special punctuation: @! @? @enddots\n  dir file maintenance: @dircategory @direntry; also new program, install-info\n  HTML support: @email @url @ifhtml...@end ifhtml\n  Macros: @macro @unmacro\n  Tables: @multitable @tab\n  Hyphenation: @- @hyphenation\n  Spacing: @  @<TAB> @<NEWLINE>\n  Sectioning:\n    @headings singleafter/doubleafter (change heading style after current page)\n    @centerchap\n    @setchapterstyle\n  Other:\n    @shorttitlepage (simple title pages)\n    @detailmenu...@end detailmenu (help makeinfo parse master menus)\n* Makeinfo prefers an input file named `foo.texinfo' or `foo.texi' or\n  `foo.txinfo' to just `foo' (the latter most likely being an executable).\n* Makeinfo implements @. @! @? correctly, as end-of-sentence punctuation.\n* @key marks its argument with a lozenge in TeX and <...> in Info.\n* TeX output has substantially decreased interline spacing and other\n  formatting changes.\n* Remove these obsolete and never-documented commands:\n    @infotop\n    @infoappendix @infoappendixsec @infoappendixsubsec @infoappendixsubsubsec\n    @infochapter @infosection @infosubsection @infosubsubsection\n    @infounnumbered @infounnumberedsec @infounnumberedsubsec\n      @infounnumberedsubsubsec\n    @input\n    @smallbreak @medbreak\n    @overfullrule\n    @br\n* Deprecate these obsolete commands, to be removed in the next release:\n    @ctrl\n    @infoinclude\n    @iappendix @iappendixsection @iappendixsec @iappendixsubsec\n      @iappendixsubsubsec\n    @ichapter @isection @isubsection @isubsubsection\n    @iunnumbered @iunnumberedsec @iunnumberedsubsec @iunnumberedsubsubsec\n    @setchapterstyle\n    @titlespec\n\n\f\n3.7 (24 December 1995)\n* Have --version print texinfo release number as well as the individual\n  program version.\n* Better man page cleaning.\n* Update Elisp files from current Emacs release.\n\n\f\n3.6 (21 June 1995)\n* Unmatched brace error reporting improved.\n* Missing comment terminator prevented compilation.\n\n\f\n3.5 (20 June 1995)\n* Autoconf update.\n* Support for parallel makes.\n* make install does not install Elisp files.\n\n\f\n3.4 (19 June 1995)\n* Handle @ifhtml in Elisp.\n* Update FSF address.\n\n\f\n3.3 (15 June 1995)\n* Portability changes.\n* Compile Elisp files.\n* Don't distribute .info* files.\n\n\f\n3.2 (9 June 1995)\n* Standalone Info can read Unix man pages.\n* New commands: @! @? @^ @\" @enddots.\n* makeinfo -E does macro expansion (and nothing else).\n\n\f\n3.1 (23 May 1993)\nJust bug fixes, see ChangeLog for full details.\n\n\f\n3.0: first release of Texinfo version 2, with many new commands.\n\n\n\f\nHere is the separate NEWS for old releases of Info:\n\nVersion 2.11,     Sat Apr  1 09:15:21 1995\n\nChanges since 2.7 beta:\n\nAlthough the basic code remains the same, there are numerous nits\nfixed, including some display bugs, and a memory leak.  Some changes\nthat have taken place with larger impact include the way in which the\n(dir) node is built; I have added in support for \"localdir\"\ndirectories among other things.  Info files may be stored in\ncompressed formats, and in their own subdirectories; menu items which\ndo not explicitly name the node to which they are attached have the\nmenu item name looked up as an Info file if it is not found within the\ncurrent document.  This means that the menu item:\n\n* Info::\t\tThe Info documentation reader.\n\nin (dir) refers to the info node \"(info)Top\".\n\nPlease see the ChangeLog and documentation for details on other\nchanges.\n\nVersion 2.7 beta, Wed Dec 30 02:02:38 1992\nVersion 2.6 beta, Tue Dec 22 03:58:07 1992\nVersion 2.5 beta, Tue Dec  8 14:50:35 1992\nVersion 2.4 beta, Sat Nov 28 14:34:02 1992\nVersion 2.3 beta, Fri Nov 27 01:04:13 1992\nVersion 2.2 beta, Tue Nov 24 09:36:08 1992\nVersion 2.1 beta, Tue Nov 17 23:29:36 1992\n\nChanges since 2.5 beta:\n\nNote that versions 2.6 and 2.7 Beta were only released to a select group.\n\n* \"info-\" removed from the front of M-x commands.\n\n* Automatic footnote display.  When you enter a node which contains\n  footnotes, and the variable \"automatic-footnotes\" is \"On\", Info pops\n  up a window containing the footnotes.  Likewise, when you leave that\n  node, the window containing the footnotes goes away.\n\n* Cleaner built in documentation, and documentation functions.\n\n  Use:\n    o `M-x describe-variable' to read a variable's documentation\n    o `M-x describe-key' to find out what a particular keystroke does.\n    o `M-x describe-function' to read a function's documentation.\n    o `M-x where-is' to find out what keys invoke a particular function.\n\n* Info can \"tile\" the displayed windows (via \"M-x tile-windows\").  If\n  the variable \"automatic-tiling\" is \"On\", then splitting a window or\n  deleting a window causes the remaining windows to be retiled.\n\n* You can save every keystroke you type in a \"dribble file\" by using the\n  `--dribble FILENAME' option.  You can initially read keystrokes from an\n  alternate input stream with `--restore FILENAME', or by redirecting\n  input on the command line `info < old-dribble'.\n\n* New behaviour of menu items.  If the label is the same as the\n  target node name, and the node couldn't be found in the current file,\n  treat the label as a file name.  For example, a menu entry in \"DIR\"\n  might contain:\n\n    * Emacs::\t\tCool text-editor.\n\n  Info would not find the node \"(dir)Emacs\", so just plain \"(emacs)\"\n  would be tried.\n\n* New variable \"ISO-Latin\" allows you to use European machines with\n  8-bit character sets.\n\n* Cleanups in echo area reading, and redisplay.  Cleanups in handling the\n  window which shows possible completions.\n\n* Info can now read files that have been compressed.  An array in filesys.c\n  maps extensions to programs that can decompress stdin, and write the results\n  to stdout.  Currently, \".Z\"/uncompress, \".z\"/gunzip, and \".Y\"/unyabba are\n  supported.  The modeline for a compressed file shows \"zz\" in it.\n\n* There is a new variable \"gc-compressed-files\" which, if non-zero, says\n  it is okay to reclaim the file buffer space allocated to a file which\n  was compressed, if, and only if, that file's contents do not appear in\n  any history node.\n\n* New file `nodemenu.c' implements a few functions for manipulating\n  previously visited nodes.  `C-x C-b' (list-visited-nodes) produces a\n  menu of the nodes that could be reached by info-history-node in some\n  window.  `C-x b' (select-visited-node) is similar, but reads one of\n  the node names with completion.\n\n* Keystroke `M-r' (move_to_screen_line) allows the user to place the cursor at\n  the start of a specific screen line.  Without a numeric argument, place the\n  cursor on the center line; with an arg, place the cursor on that line.\n\n* Interruptible display implemented.  Basic display speedups and hacks.\n* The message \"*** Tags Out of Date ***\" now means what it says.\n* Index searching with `,' (info-index-next) has been improved.\n* When scrolling with C-v, C-M-v, or M-v, only \"Page Only\" scrolling\n  will happen.\n\n* Continuous scrolling (along with `]' (info-global-next) and `['\n  (info-global-prev) works better.  `]' and `[' accept numeric\n  arguments, moving that many nodes in that case.\n\n* `C-x w' (info-toggle-wrap) controls how lines wider than the width\n  of the screen are displayed.  If a line is too long, a `$' is\n  displayed in the rightmost column of the window.\n\n* There are some new variables for controlling the behaviour of Info\n  interactively.  The current list of variables is as follows:\n\n  Variable Name      Default Value  Description\n  -------------      -------------  -----------\n  `automatic-footnotes' On\t    When \"On\", footnotes appear and\n\t\t\t\t    disappear automatically.\n\n  `automatic-tiling'    Off\t    When \"On\", creating of deleting a\n\t\t\t\t    window resizes other windows.\n\n  `visible-bell'        Off\t    If non-zero, try to use a visible bell.\n\n  `errors-ring-bell'    On\t    If non-zero, errors cause a ring.\n\n  `show-index-match'    On\t    If non-zero, the portion of the string\n\t\t\t\t    matched is highlighted by changing its\n\t\t\t\t    case.\n\n  `scroll-behaviour'    Continuous  One of \"Continuous\", \"Next Only\", or\n\t\t\t\t    \"Page Only\".  \"Page Only\" prevents you from\n\t\t\t\t    scrolling past the bottom or top of a node.\n\t\t\t\t    \"Next Only\" causes the Next or Prev node to\n\t\t\t\t    be selected when you scroll past the bottom\n\t\t\t\t    or top of a node.  \"Continous\" moves\n\t\t\t\t    linearly through the files hierarchical\n\t\t\t\t    structure.\n\n  `scroll-step'\t        0\t    Controls how scrolling is done for you when\n\t\t\t\t    the cursor moves out of the current window.\n\t\t\t\t    Non-zero means it is the number of lines\n\t\t\t\t    you would like the screen to shift.  A\n\t\t\t\t    value of 0 means to center the line\n\t\t\t\t    containing the cursor in the window.\n\n  `gc-compressed-files' Off\t    If non-zero means it is okay to reclaim the\n\t\t\t\t    file buffer space allocated to a file which\n\t\t\t\t    was compressed, if, and only if, that\n\t\t\t\t    file's contents do not appear in the node\n\t\t\t\t    list of any window.\n\n  `ISO-Latin'\t        Off\t    Non-zero means that you are using an ISO\n\t\t\t\t    Latin character set.  By default, standard\n\t\t\t\t    ASCII characters are assumed.\n________________________________________\nThis release of Info is version 2.5 beta.\n\nChanges since 2.4 beta:\n\n* Index (i) and (,) commands fully implemented.\n* \"configure\" script now shipped with Info.\n* New function \"set-variable\" allows users to set various variables.\n* User-settable behaviour on end or beginning of node scrolling.  This\n  supersedes the SPC and DEL changes in 2.3 beta.\n\n________________________________________\nThis release of Info is version 2.4 beta.\n\nChanges since 2.3 beta:\n\n* info-last-node now means move to the last node of this info file.\n* info-history-node means move backwards through this window's node history.\n* info-first-node moves to the first node in the Info file.  This node is\n  not necessarily \"Top\"!\n* SPC and DEL can select the Next or Prev node after printing an informative\n  message when pressed at the end/beg of a node.\n\n----------------------------------------\nThis release of Info is version 2.3 beta.\n\nChanges since 2.2 beta:\n\n* M-x command lines if NAMED_COMMANDS is #defined.  Variable in Makefile.\n* Screen height changes made quite robust.\n* Interactive function \"set-screen-height\" implements user height changes.\n* Scrolling on some terminals is faster now.\n* C-l with numeric argument is fixed.\n\n----------------------------------------\nThis release of Info is version 2.2 beta.\n\nChanges since 2.0:\n\n* C-g can now interrupt multi-file searches.\n* Incremental search is fully implemented.\n* Loading large tag tables is much faster now.\n* makedoc.c replaces shell script, speeding incremental builds.\n* Scrolling in redisplay is implemented.\n* Recursive uses of the echo area made more robust.\n* Garbage collection of unreferenced nodes.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/README",
    "content": "This is the README file for the GNU Texinfo distribution.  Texinfo is\nthe preferred documentation format for GNU software.\n\n  Copyright 1992-2022 Free Software Foundation, Inc.\n\n  Copying and distribution of this file, with or without modification,\n  are permitted in any medium without royalty provided the copyright\n  notice and this notice are preserved.\n\nHome page: https://www.gnu.org/software/texinfo/\n\nPrimary distribution point: https://ftp.gnu.org/gnu/texinfo/\n  automatic mirror redirection: https://ftpmirror.gnu.org/texinfo/\n                   mirror list: https://www.gnu.org/prep/ftp.html\n\nTexinfo is a documentation system that uses a single source to produce\nmany forms of output:\n- a PDF or DVI document (via the TeX typesetting system) with the normal\n  features of a book, including sectioning, cross references, indices, etc.\n- an Info file with analogous features\n- a plain text (ASCII) file\n- HTML output suitable for use with a web browser\n- an EPUB 3 e-book\n- a LaTeX file, which can then be used to create a PDF\n- a Docbook file\n\nSee ./INSTALL* for installation instructions.\n\nTo get started with Texinfo, you can read the Texinfo manual\nonline at https://www.gnu.org/software/texinfo/manual/texinfo.\n\nIf you don't have Internet access, you can read the manual locally:\n- first, build the distribution.\n- then, for HTML, run: make -C doc html\n  and you can start reading at doc/texinfo_html/index.html.\n- for PDF, if you have a working TeX, run: make -C doc pdf\n- for Info, you can read the manual:\n ./info/ginfo doc/info-stnd\n  and/or read the Texinfo manual:\n ./info/ginfo doc/texinfo\n\nTexinfo mailing lists and archives:\n- https://lists.gnu.org/mailman/listinfo/bug-texinfo\n  for bug reports, enhancement suggestions, technical discussion.\n- https://lists.gnu.org/mailman/listinfo/help-texinfo\n  for authoring questions and general discussion.\n\nBug reports:\nPlease include enough information for the maintainers to reproduce the\nproblem.  Generally speaking, that means:\n- the contents of all input files needed to reproduce the bug (crucial!).\n- a statement of the problem and any samples of the erroneous output.\n- the version number of Texinfo and the program(s) involved (use --version).\n- hardware and operating system information (uname -a).\n- unusual options you gave to configure, if any (try ./config.status --help).\n- anything else that you think could be helpful.\n\nPatches are welcome; if possible, please make them with diff -c or\ngit diff and include ChangeLog entries.\n\nSee README-hacking for information on the Texinfo development\nenvironment -- any interested parties are welcome.  If you're a\nprogrammer and wish to contribute, this should get you started.\n\nThis distribution includes the following files, among others:\n    README                 This file.\n    README-hacking         Texinfo developer information.\n\n    INSTALL                Texinfo-specific installation notes.\n    NEWS                   Summary of new features by release.\n\nTexinfo documentation files\n    doc/texinfo.texi       Describes the Texinfo language and many\n                           of the associated tools.  It tells how to use\n                           Texinfo to write documentation, how to use\n                           Texinfo mode in GNU Emacs, TeX, texi2any, and\n                           much else.\n\n    doc/info-stnd.texi     How to use the standalone GNU Info reader that is\n                           included in this distribution (./info).\n\nPrinting-related files:\n    doc/texinfo.tex        This implements Texinfo in TeX, to typeset a\n                           Texinfo file into a DVI or PDF file.\n\n    util/texi2dvi          This is a shell script for producing an\n                           indexed DVI file using TeX and texindex.\n    \n    util/texi2pdf          Generate PDF (wrapper for texi2dvi).\n\nSource directories: \n  djgpp/                   Support for compiling under DJGPP.\n  gnulib/                  Support files from Gnulib.\n  info/                    Standalone Info reader.\n  install-info/            Maintain the Info dir file.\n  tp/                      Texinfo Parser in Perl, includes texi2any.\n  texindex/                The `texindex' program that generates\n                           sorted indices used by TeX when\n                           typesetting a file for printing.\n\nTranslation support:\n  po/                      Strings of the programs.\n  po_document/             Strings in generated Texinfo documents.\n\nInstallation support:\n  Makefile.am              Read by Automake to create a Makefile.in.\n  Makefile.in              Read by configure to make a Makefile,\n                             created by Automake.\n  configure.ac             Read by Autoconf to create `configure'.\n  configure                Configuration script for local conditions,\n                             created by Autoconf.\n  build-aux/               Common files.\n\nThe util/ directory contains a few other scripts, e.g., examples of\nusing texi2any in various ways.  See util/README.\n\nSome files in this package have their copyright years stated as a range\n('2008-2010') rather than listed as individual years ('2008, 2009, \n2010').\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/licenses/texinfo-7.0.3/README-hacking",
    "content": "This file describes the development environment for Texinfo.\n\n  Copyright 2002-2022 Free Software Foundation, Inc.\n\n  Copying and distribution of this file, with or without modification,\n  are permitted in any medium without royalty provided the copyright\n  notice and this notice are preserved.\n\nThe development sources for GNU Texinfo are available through git\nat Savannah:\n  https://savannah.gnu.org/git/?group=texinfo\n\nThis distribution uses whatever versions of Automake, Autoconf, and\nGettext are listed in NEWS; usually the latest official releases.  If\nyou are getting the sources from the development repository (or change\nconfigure.ac), you'll need to have these tools installed to (re)build.\nYou'll also need help2man.  If you modify texindex/ti.twjr, you'll need\ngawk >= 4.0.  All of these programs are available from\nhttp://ftp.gnu.org/gnu.\n\nAfter getting the development sources, and installing the tools above,\nyou can run\n ./autogen.sh\nand then, for example,\n ./configure -C CFLAGS='-g' PERL_EXT_CFLAGS='-g'\nand then\n make\n\nThe -C tells configure to cache test results, which usually speeds\nthings up a bit.\n\nAfter the initial autogen && configure, simply running make should suffice.\n\nGettext or help2man not installed do not cause configure to fail,\nthough configure shows if they were found.  This is because a release\ndoes not require those tools.  Indeed, both prerequisites and\nresult files are shipped in a release, such that the tools are only\nneeded if the prerequisite changed.  The tools are needed when building\nfrom developpement sources, however, as result files are not under version\ncontrol.  Make will fail with an explicit missing command for help2man,\nand with a command not found error for a Gettext utility command.\n\nRunning make in one particular subdirectory is possible, for example\nmake -C info.  However there are interdependencies between the \nsubdirectories, notably on gnulib, so if you don't want to run \"make\", \nyou may have to run \"make -C gnulib/lib\" first.\n\nAdditionally, make dist may not work until make has been run at least \nonce, because of rules to create man pages under the man/ directory.\n\n\"make dist\" will fail if the use of Perl XS extension modules is \ndisabled and there is no Makefile in the XSParagraph subdirectory.\n\n\nUsing git\n---------\n\nThis section is if you have write access to the git repository.\n\nUsually commits to the git repository should include a ChangeLog\nentry.  Please follow the existing style (the GNU Coding Standards\nhas a guide).\n\nYou can automatically use the contents of the most recent ChangeLog\nentry with a git commit hook .git/hooks/prepare-commit-msg\n\n------------------------------------\n#!/bin/sh\n\n# $1 - file that contains commit log message\n# $2 - source of commit message\n\noutfile=\"$1\"\n\ncase $2 in\n  message|template|merge|squash|commit)\n    ;;\n  *)\n   # Use latest ChangeLog entry as commit message\n   sed -n -e '1,/^\\w*$/d' -e '/^[^\t]/q' -e '{s/^\t//;p}' ChangeLog  >\"$outfile\"\n;;\nesac\n------------------------------------\n\nWhen unable to push commits due to other commits being made, please\nuse \"git pull --rebase\" (the default for \"git pull\" complicates the\ngit history).  To deal with conflicts in the ChangeLog, you should\ninstall the git-merge-changelog program.\n\nYou can get better output from \"git diff\" for Texinfo files by putting\nthe following section in your .gitconfig file:\n\n[diff \"texinfo\"]\n        xfuncname = \"^(@node .*)$\"\n\nThis shows which node each change occurred in.\n\n\nGnulib\n------\n\nThis distribution uses Gnulib (http://www.gnu.org/software/gnulib)\nto share common files.  Gnulib files used in Texinfo are checked in to\nthe repository.  A Gnulib directory is setup in two locations, in\nthe main directory and in tp/Texinfo/XS/.\n\nTo update the gnulib files, get a checkout of gnulib in a separate\ndirectory, then run, say\n\n  ../gnulib/gnulib-tool --add-import\n\nin your top-level Texinfo directory and\n\n  ../../../../gnulib/gnulib-tool --add-import\n\nunder tp/Texinfo/XS.  (gnulib-tool is in the gnulib source tree.)\n\nThe currently-used gnulib modules and other gnulib information are\nrecorded in gnulib/m4/gnulib-cache.m4.\n\ngnulib-tool --add-import may also be used to add another gnulib module:\n  ../gnulib/gnulib-tool --add-import other_gnulib_module\n\nAfter running gnulib-tool --add-import or otherwise adding modules, it is\nnecessary to check what files were added or removed (e.g., run \"git\nstatus -u\") and add new files to the repository with \"git add\".\nAdd any new generated files (typically gnulib/lib/foo.h from foo.h.in) \nto the ignore list in .gitignore.\n\n\nSubdirectories in repository\n----------------------------\n\nIn addition to the subdirectories listed in README, there is the \nfollowing directory in the source control repository:\n\njs/ - Work on enhanced browsing of HTML manuals with JavaScript\ninfog/ - HTML-Info reader using WebKitGTK library\n\nFinally, the contrib/ directory contains additional files from users\nprovided for your reading and/or hacking pleasure.  They aren't part of\nTexinfo proper or maintained by the Texinfo developers.\n\n\n\n\f\nAbout running the Texinfo programs from a development source tree:\n\n- Once the distribution is built, you can run the compiled programs\n(info, install-info) out of the build tree without special settings; \nthey don't try to read any installed data files.\n\n- The texi2dvi script and texinfo.tex can be run as-is, since they \nare standalone and don't require compilation.  For the same reasons,\nthey are officially updated between full Texinfo releases, at\nhttp://ftpmirror.gnu.org/texinfo.\n\n- Regarding texi2any (aka makeinfo), you can run tp/texi2any.pl\ndirectly.  This is the original source file for the program, so it's\nconvenient to be able to make changes and then run it.\n\nTo run the output \"tp/texi2any\" instead, you can set the environment\nvariable TEXINFO_DEV_SOURCE to 1.  Otherwise, it will try to use\nTexinfo's Perl modules in the installed locations.  \"tp/texi2any\" uses\nthe Perl interpreter found by configure, so you might want to run that \ninstead of texi2any.pl if it's different to the default interpreter in \nyour environment.\n\n\n\f\nReferences for working on various parts of the system:\n\nIf you want to delve into making a new backend for the Perl makeinfo,\nthe documentation in tp/Texinfo/Convert/Converter.pm is a good starting\npoint, as it describes the existing backends and other places to look.\n\nIf you want to delve into texinfo.tex, a thorough plain TeX reference\nis available under the GFDL:\n  TeX by Topic - http://www.eijkhout.net/texbytopic/texbytopic.html\nAnother book on plain TeX, also available under the GFDL, is a GNU package:\n  TeX for the Impatient - http://www.gnu.org/software/teximpatient/\nOccasionally you may need to know about the details of the PDF format.\nA reference for this is the PDF reference, Sixth Edition, version 1.7,  \ndownloadable at http://www.adobe.com/devnet/pdf/pdf_reference_archive.html\n\nThe texindex program is implemented using the TexiWebJR literate\nprogramming system, combining Texinfo and Awk\n(https://github.com/arnoldrobbins/texiwebjr).  Running \"make ti.pdf\"\nin the texindex/ subdirectory creates the printable form of the\nprogram.  All the usual Texinfo output formats are possible.\n\n\n\f\nSteps for making a release (pretest or official):\n\n- When close to official release:\n\ncheck at latest automake/autoconf/gettext version, and mention in NEWS\n(to upgrade gettext, run\n  gettextize -f --po-dir=po --po-dir=po_document\nafter installing new version of gettext.\ncheck that this does not actually downgrade files due to files also\nbeing updated from gnulib --add-import)\n\n# Under the top level, and also under tp/Texinfo/XS, which uses\n# a separate gnulib import.\ngnulib-tool --add-import\n'git status -u' and add untracked files\n\nAfter upgrading automake/autoconf/gettext, run ./autogen.sh\nand/or \"autoreconf --verbose --force --install\" to update ancilliary\nfiles in build-aux and elsewhere.  Check changes before committing.\n\nUse util/srclist-txi for checking files to be copied from gnulib\n\nrun all tests with valgrind:\n* under info/t, put valgrind in $ginfo, then check t/*.val.log files after\n  running test suite\n* edit install-info/tests/defs.in, uncomment valgrind line and run\n  config.status to regenerate defs\n\nparsetexi memory leak checks with valgrind\n\nNYTProf profiling for Perl code\n* e.g. 'perl -d:NYTProf ../tp/texi2any.pl FILE.texi'.  See Devel::NYTProf\n  man page.\n\n\ntry groff.texinfo from groff source repo.\nCheck \"make ccheck\" and \"make vcheck\" work in \"doc/refcard\".\nprocess doc/texinfo-tex-test.texi with TeX and check that output is good.\ncheck for C compiler warnings by configuring with\n\n  ./configure CFLAGS='-Wall -Wdeclaration-after-statement' \\\n              PERL_EXT_CFLAGS='-Wall -Wdeclaration-after-statement'\n\n-Wdeclaration-after-statement is useful because a) intermixing\ndeclarations with statements is an easy thing to do accidentally,\nb) gcc doesn't warn about it by default, and c) other compilers that\ndon't support it are still widespread.\n\nNot all compiler warnings have to be fixed, though.\n\nHave a look at the output of \"git status -u\" to check for files that\n  should be tracked in git or ignored.\nmake po-check             # update po/POTFILES.in as needed\n\ncheck indices of Texinfo manuals and check for duplicates (with <1> in Info)\n\n- Official releases only:\nmake V=1 pdf and fix underfull/overfull boxes.\n\n- Final (easy) checks:\n\ncheck OpenCSW build reports at\n  https://buildfarm.opencsw.org/buildbot/waterfall?category=texinfo\nCheck that translations have been updated, e.g.:\n  rsync  -Lrtzv  translationproject.org::tp/latest/texinfo/ po\n  rsync  -Lrtzv  translationproject.org::tp/latest/texinfo_document/ \\\n                 po_document # note the trailing slashes in these commands\nmake\nmake update-po            # both po and po_document needed, build a dist first\nEnsure texinfo.tex, texi2dvi, and htmlxref.cnf are updated on ftp.gnu.org.\nEnsure TXI_XLATE in doc/Makefile.am matches actual file list.\nCheck that LINGUAS under po and po_document match actual file list.\nCheck that TEXINFO_DTD_VERSION has been updated to the next version in\n  configure.ac if the DTD has been modified since the last release.\n  See comments in configure.ac, and run (at the top level) make dtd-check.\nCheck \"dist-xz\" is in the option list in configure.ac (often removed\nfor speed when testing).\nupdate version in configure.ac, notice in ChangeLog.\ncheck up to date copyright years in files relevant to --version calls\n(tp/texi2any.pl, info/info.c, install-info/install-info.c)\nversion number in texi2dvi, texi2pdf, txirefcard.tex.\ncheck that texindex version is updated properly\n  (cd texindex ; rm texindex.awk ; make)\n(cd tp && ./maintain/change_perl_modules_version.sh auto)\n  -- this updates all the version numbers in the Perl modules\n(cd tp ; maintain/regenerate_file_lists.pl) # list all test results\n\n- Official releases only:\nversion and date in NEWS.\nversion number in txirefcard.tex.\n(cd tp && maintain/regenerate_documentlanguages-loc.pl)\n  -- regenerates tp/Texinfo/Documentlanguages.pm (requires Text::CSV)\n\none last \"git diff\" to check release commit looks good\nmake distcheck\n(export MALLOC_CHECK_=2; make distcheck)  # repeat until clean\ngit commit and push\n\nafter uploading distribution,\npretest announcement -> bug-texinfo / beebe / platform-testers to try.\nbcc coordinator@translationproject.org.\n\n\n\n- To do the actual upload:\npkg=texinfo\nver=7.0\n\nthen do one of:\ngnupload --to alpha.gnu.org:$pkg $pkg-$ver.tar.xz                #pretest\ngnupload --to ftp.gnu.org:$pkg   $pkg-$ver.tar.{gz,xz} *.diff.xz #official\n   Use --user option if not using default key\n   texinfo.tex and texi2dvi should already be up to date, but check.  Use\ngnupload --replace --to ftp.gnu.org:texinfo texi2dvi\n\n#  Official releases only: tag source tree\ngit tag texinfo-6.6\ngit push --tags\n\n#  ... set up dtd directory on web pages:\ncd $HOME/gnu/www/texinfo/dtd # or wherever webpages checkout is\nmkdir $ver && cvs add $ver\ncp $tutil/texinfo.dtd $ver\ncvs add -kb $ver $ver/texinfo.dtd\ncvs commit -m$ver $ver\n\n\n- When official release is out there ...\nupdate home page (texinfo.html) and commit as needed.\nincluding:\n  pod2html $txi/Pod-Simple-Texinfo/pod2texi.pl \\\n  | grep -Fv 'rev=\"made\"' >manual/pod2texi.html\n\ncheck for http links that should be changed to https - then delete\nthis item\n\nBuild web documentation with\n  make -C doc wwwdoc-build\n\nCopy documentation files to web checkout with, e.g.\n  make -C doc \\\n  wwwdoc-install www_target=../../TEXINFO_WEB_PAGES/texinfo/manual/\nCheck for removed files with, e.g. ls -ltu $(www_target)/*/html_node, \nfollowed by cvs rm -f.  Likewise, check for added files with\ncvs -qn update, followed by cvs add.  When done, run cvs commit.\n\n#  Official releases only: Contact root@tug.org to update texinfo at tug.org.\n# If root@tug.org doesn't reply, can try webmaster@tug.org,\n# or (last resort) board@tug.org.\n\n\n#  For official releases:\nsend announcement to info-gnu,\n  cc bug-texinfo and bcc coordinator@translationproject.org.\nnews item at savannah.\n\n#  ... post-release, or when development resumes:\nconfigure.ac, util/texi2dvi: add \"dev\" to versions for clarity,\nuntil it's time to do pretests again.\n\nafter next release:\nrename old ChangeLog and start a new one\ncheck TODO file and do pending tasks\ndiscuss on mailing list changing the git branch structure to allow quick\n  bug fix releases for severe bugs (e.g. glibc 2.34 incompatibility, info crash\n  in Brazillian Portuguese locale)\ndelete these lines from README-hacking\n\n\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/README-OUT.md",
    "content": "# The xPack OpenOCD\n\nThe **xPack OpenOCD** (formerly GNU MCU Eclipse OpenOCD)\nis the **xPack** version of **OpenOCD**,\nan open-source project.\n\nFor more details, please read the corresponding release pages:\n\n- <https://xpack.github.io/openocd/releases/>\n- <https://openocd.org>\n\nThank you for using open source software,\n\nLiviu Ionescu\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/VERSION",
    "content": "0.12.0-2\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/application.sh",
    "content": "# -----------------------------------------------------------------------------\n# This file is part of the xPack distribution.\n#   (https://xpack.github.io)\n# Copyright (c) 2019 Liviu Ionescu.\n#\n# Permission to use, copy, modify, and/or distribute this software\n# for any purpose is hereby granted, under the terms of the MIT license.\n# -----------------------------------------------------------------------------\n\n# -----------------------------------------------------------------------------\n# Application specific definitions. Included with source.\n\n# Used to display the application name.\nXBB_APPLICATION_NAME=${XBB_APPLICATION_NAME:-\"OpenOCD\"}\n\n# Used as part of file/folder paths.\nXBB_APPLICATION_LOWER_CASE_NAME=${XBB_APPLICATION_LOWER_CASE_NAME:-\"openocd\"}\n\nXBB_APPLICATION_DISTRO_NAME=${XBB_APPLICATION_DISTRO_NAME:-\"xPack\"}\nXBB_APPLICATION_DISTRO_LOWER_CASE_NAME=${XBB_APPLICATION_DISTRO_LOWER_CASE_NAME:-\"xpack\"}\nXBB_APPLICATION_DISTRO_TOP_FOLDER=${XBB_APPLICATION_DISTRO_TOP_FOLDER:-\"xPacks\"}\n\nXBB_APPLICATION_DESCRIPTION=\"${XBB_APPLICATION_DISTRO_NAME} ${XBB_APPLICATION_NAME}\"\n\ndeclare -a XBB_APPLICATION_DEPENDENCIES=( openocd )\ndeclare -a XBB_APPLICATION_COMMON_DEPENDENCIES=( libusb1 libusb-w32 libusb0 libftdi libiconv hidapi autotools texinfo )\n\n# -----------------------------------------------------------------------------\n\nXBB_GITHUB_ORG=\"${XBB_GITHUB_ORG:-\"xpack-dev-tools\"}\"\nXBB_GITHUB_REPO=\"${XBB_GITHUB_REPO:-\"${XBB_APPLICATION_LOWER_CASE_NAME}-xpack\"}\"\nXBB_GITHUB_PRE_RELEASES=\"${XBB_GITHUB_PRE_RELEASES:-\"pre-releases\"}\"\n\nXBB_NPM_PACKAGE=\"${XBB_NPM_PACKAGE:-\"@xpack-dev-tools/${XBB_APPLICATION_LOWER_CASE_NAME}@next\"}\"\n\n# -----------------------------------------------------------------------------\n\n# If you want to build OpenOCD from another repo then uncomment the\n# following defines and tweak as needed.\n\n# XBB_APPLICATION_OPENOCD_GIT_URL=\"https://github.com/openocd-org/openocd.git\"\n# XBB_APPLICATION_OPENOCD_GIT_BRANCH=\"master\"\n# XBB_APPLICATION_OPENOCD_GIT_COMMIT=\"HEAD\"\n\n# -----------------------------------------------------------------------------\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/build.sh",
    "content": "#!/usr/bin/env bash\n# -----------------------------------------------------------------------------\n# DO NOT EDIT! Generated from xpacks/@xpack-dev-tools/xbb-helper/templates/*.\n#\n# This file is part of the xPack distribution.\n#   (https://xpack.github.io)\n# Copyright (c) 2022 Liviu Ionescu.\n#\n# Permission to use, copy, modify, and/or distribute this software\n# for any purpose is hereby granted, under the terms of the MIT license.\n# -----------------------------------------------------------------------------\n\n# -----------------------------------------------------------------------------\n# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d).\n\nif [[ ! -z ${DEBUG} ]]\nthen\n  set ${DEBUG} # Activate the expand mode if DEBUG is anything but empty.\nelse\n  DEBUG=\"\"\nfi\n\nset -o errexit # Exit if command failed.\nset -o pipefail # Exit if pipe failed.\nset -o nounset # Exit if variable not set.\n\n# Remove the initial space and instead use '\\n'.\nIFS=$'\\n\\t'\n\n# -----------------------------------------------------------------------------\n# Identify the script location, to reach, for example, the helper scripts.\n\nbuild_script_path=\"$0\"\nif [[ \"${build_script_path}\" != /* ]]\nthen\n  # Make relative path absolute.\n  build_script_path=\"$(pwd)/$0\"\nfi\n\nscript_folder_path=\"$(dirname \"${build_script_path}\")\"\nscript_folder_name=\"$(basename \"${script_folder_path}\")\"\n\n# =============================================================================\n# Build the application.\n\nscripts_folder_path=\"${script_folder_path}\"\nproject_folder_path=\"$(dirname ${script_folder_path})\"\nhelper_folder_path=\"${project_folder_path}/xpacks/@xpack-dev-tools/xbb-helper\"\n\n# -----------------------------------------------------------------------------\n\nsource \"${scripts_folder_path}/application.sh\"\n\n# Common definitions.\nsource \"${helper_folder_path}/scripts/build-common.sh\"\n\nsource \"${scripts_folder_path}/versioning.sh\"\n\nif [ ${#XBB_APPLICATION_COMMON_DEPENDENCIES[@]} -ne 0 ]\nthen\n  for dependency in ${XBB_APPLICATION_COMMON_DEPENDENCIES[@]}\n  do\n    echo \"Including ${helper_folder_path}/dependencies/${dependency}.sh...\"\n    source \"${helper_folder_path}/dependencies/${dependency}.sh\"\n  done\nfi\n\nif [ ${#XBB_APPLICATION_DEPENDENCIES[@]} -ne 0 ]\nthen\n  for dependency in ${XBB_APPLICATION_DEPENDENCIES[@]}\n  do\n    echo \"Including ${scripts_folder_path}/dependencies/${dependency}.sh...\"\n    source \"${scripts_folder_path}/dependencies/${dependency}.sh\"\n  done\nfi\n\n# -----------------------------------------------------------------------------\n\nhelp_message=\"    bash $0 [--win] [--debug] [--develop] [--jobs N] [--help]\"\nbuild_common_parse_options \"${help_message}\" \"$@\"\n\nbuild_common_run\n\nexit 0\n\n# -----------------------------------------------------------------------------\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/dependencies/openocd.sh",
    "content": "# -----------------------------------------------------------------------------\n# This file is part of the xPack distribution.\n#   (https://xpack.github.io)\n# Copyright (c) 2019 Liviu Ionescu.\n#\n# Permission to use, copy, modify, and/or distribute this software\n# for any purpose is hereby granted, under the terms of the MIT license.\n# -----------------------------------------------------------------------------\n\n# -----------------------------------------------------------------------------\n\nfunction openocd_download()\n{\n  if [ ! -d \"${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}\" ]\n  then\n    (\n      cd \"${XBB_SOURCES_FOLDER_PATH}\"\n      git_clone \"${XBB_OPENOCD_GIT_URL}\" \"${XBB_OPENOCD_GIT_BRANCH}\" \\\n          \"${XBB_OPENOCD_GIT_COMMIT}\" \"${openocd_src_folder_name}\"\n      cd \"${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}\"\n      git submodule update --init --recursive --remote\n    )\n  fi\n}\n\n# -----------------------------------------------------------------------------\n\n# https://github.com/archlinux/svntogit-community/blob/packages/openocd/trunk/PKGBUILD\n\n# -----------------------------------------------------------------------------\n\nfunction openocd_build()\n{\n  echo_develop\n  echo_develop \"[${FUNCNAME[0]} $@]\"\n\n  local openocd_version=\"$1\"\n\n  local openocd_src_folder_name=\"${XBB_OPENOCD_SRC_FOLDER_NAME:-\"openocd.git\"}\"\n  local openocd_folder_name=\"openocd-${openocd_version}\"\n\n  mkdir -pv \"${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}\"\n\n  local openocd_stamp_file_path=\"${XBB_STAMPS_FOLDER_PATH}/stamp-${openocd_folder_name}-installed\"\n  if [ ! -f \"${openocd_stamp_file_path}\" ]\n  then\n    (\n      openocd_download\n\n      xbb_activate_dependencies_dev\n\n      cd \"${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}\"\n\n      (\n        if [ ! -d \"autom4te.cache\" ]\n        then\n          ./bootstrap\n        fi\n      ) 2>&1 | tee \"${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}/configure-output-$(ndate).txt\"\n\n      # Personalise the greeting message\n      run_verbose sed -i.bak -e 's|\"Open On-Chip Debugger \"|\"xPack Open On-Chip Debugger \"|' \"src/openocd.c\"\n\n      run_verbose diff \"src/openocd.c.bak\" \"src/openocd.c\" || true\n\n      # Simplify protections for the USB devices, allow access for all.\n      run_verbose sed -i.bak -e 's|MODE=\"660\".*|MODE=\"666\"|' \"contrib/60-openocd.rules\"\n\n      run_verbose diff \"contrib/60-openocd.rules.bak\" \"contrib/60-openocd.rules\" || true\n\n      mkdir -pv \"${XBB_BUILD_FOLDER_PATH}/${openocd_folder_name}\"\n      cd \"${XBB_BUILD_FOLDER_PATH}/${openocd_folder_name}\"\n\n      CPPFLAGS=\"${XBB_CPPFLAGS}\"\n      CFLAGS=\"${XBB_CFLAGS_NO_W}\"\n      CXXFLAGS=\"${XBB_CXXFLAGS_NO_W}\"\n\n      # It makes little sense to use -static-libgcc here, since\n      # several shared libraries will refer to it anyway.\n      LDFLAGS=\"${XBB_LDFLAGS_APP}\"\n\n      LIBS=\"\"\n      if [ \"${XBB_HOST_PLATFORM}\" == \"linux\" ]\n      then\n        # LIBS+=\" -lpthread -lrt -ludev\"\n        LIBS+=\" -ludev\"\n      fi\n\n      xbb_adjust_ldflags_rpath\n\n      export CPPFLAGS\n      export CFLAGS\n      export CXXFLAGS\n\n      export LDFLAGS\n      export LIBS\n\n      export JAYLINK_CFLAGS='${XBB_CFLAGS} -fvisibility=hidden'\n\n      if [ ! -f \"config.status\" ]\n      then\n\n        # May be required for repetitive builds, because this is an executable built\n        # in place and using one for a different architecture may not be a good idea.\n        rm -rfv \"${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}/jimtcl/autosetup/jimsh0\"\n\n        (\n          xbb_show_env_develop\n\n          echo\n          echo \"Running openocd configure...\"\n\n          if [ \"${XBB_IS_DEVELOP}\" == \"y\" ]\n          then\n            bash \"${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}/configure\" --help\n          fi\n\n          config_options=()\n\n          config_options+=(\"--prefix=${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}\")\n\n          config_options+=(\"--build=${XBB_BUILD_TRIPLET}\")\n          config_options+=(\"--host=${XBB_HOST_TRIPLET}\")\n          config_options+=(\"--target=${XBB_TARGET_TRIPLET}\")\n\n          config_options+=(\"--datarootdir=${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}\")\n          config_options+=(\"--localedir=${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}/share/locale\")\n\n          config_options+=(\"--mandir=${XBB_LIBRARIES_INSTALL_FOLDER_PATH}/share/doc/man\")\n          config_options+=(\"--pdfdir=${XBB_LIBRARIES_INSTALL_FOLDER_PATH}/share/doc/pdf\")\n          config_options+=(\"--infodir=${XBB_LIBRARIES_INSTALL_FOLDER_PATH}/share/doc/info\")\n          config_options+=(\"--docdir=${XBB_LIBRARIES_INSTALL_FOLDER_PATH}/share/doc/\")\n\n          config_options+=(\"--disable-wextra\")\n          config_options+=(\"--disable-werror\")\n          config_options+=(\"--disable-gccwarnings\")\n          config_options+=(\"--disable-doxygen-html\")\n          config_options+=(\"--disable-doxygen-pdf\")\n\n          config_options+=(\"--disable-debug\") # HB\n          config_options+=(\"--disable-dependency-tracking\") # HB\n          if [ \"${XBB_IS_DEVELOP}\" == \"y\" ]\n          then\n            config_options+=(\"--disable-silent-rules\") # HB\n          fi\n\n          # The internal libjaylink is now deprecated.\n          # https://github.com/openocd-org/openocd/commit/8bb926eb01022998ceefe666f8df102e59404015\n          config_options+=(\"--enable-internal-libjaylink\")\n\n          # Add explicit functionality.\n          config_options+=(\"--enable-aice\")\n          config_options+=(\"--enable-armjtagew\")\n          config_options+=(\"--enable-at91rm9200\")\n          config_options+=(\"--enable-bcm2835gpio\")\n          config_options+=(\"--enable-cmsis-dap\")\n          config_options+=(\"--enable-dummy\")\n          config_options+=(\"--enable-ep93xx\")\n          config_options+=(\"--enable-ft232r\")\n          config_options+=(\"--enable-ftdi\")\n          config_options+=(\"--enable-imx_gpio\")\n          config_options+=(\"--enable-jlink\")\n          config_options+=(\"--enable-jtag_vpi\")\n          config_options+=(\"--enable-kitprog\")\n          # Deprecated\n          # config_options+=(\"--enable-oocd_trace\")\n          config_options+=(\"--enable-opendous\")\n          config_options+=(\"--enable-openjtag\")\n          config_options+=(\"--enable-osbdm\")\n          config_options+=(\"--enable-presto\")\n          config_options+=(\"--enable-remote-bitbang\")\n          config_options+=(\"--enable-rlink\")\n          config_options+=(\"--enable-stlink\")\n          config_options+=(\"--enable-ti-icdi\")\n          config_options+=(\"--enable-ulink\")\n          config_options+=(\"--enable-usb-blaster\")\n          config_options+=(\"--enable-usb_blaster_2\")\n          config_options+=(\"--enable-usbprog\")\n          config_options+=(\"--enable-vsllink\")\n          config_options+=(\"--enable-xds110\")\n\n          # Disable drivers that apparently failed to build on all platforms.\n          config_options+=(\"--disable-zy1000-master\")\n          config_options+=(\"--disable-zy1000\")\n          config_options+=(\"--disable-ioutil\")\n          config_options+=(\"--disable-minidriver-dummy\")\n          config_options+=(\"--disable-parport-ppdev\")\n\n          if [ \"${XBB_HOST_PLATFORM}\" == \"win32\" ]\n          then\n\n            export OUTPUT_DIR=\"${XBB_BUILD_FOLDER_PATH}\"\n\n            # Without it, mingw redefines it as 0.\n            CPPFLAGS+=\" -D__USE_MINGW_ANSI_STDIO=1\"\n\n            # --enable-minidriver-dummy -> configure error\n            # --enable-zy1000 -> netinet/tcp.h: No such file or directory\n\n            # --enable-openjtag_ftdi -> --enable-openjtag\n            # --enable-presto_libftdi -> --enable-presto\n            # --enable-usb_blaster_libftdi -> --enable-usb_blaster\n\n            config_options+=(\"--enable-amtjtagaccel\")\n            config_options+=(\"--enable-gw16012\")\n            config_options+=(\"--enable-parport\")\n            config_options+=(\"--enable-parport-giveio\")\n\n            # --enable-sysfsgpio -> available only on Linux\n            config_options+=(\"--disable-sysfsgpio\")\n            # --enable-buspirate -> not supported on mingw\n            config_options+=(\"--disable-buspirate\")\n\n            # oocd_trace.h:22:10: fatal error: termios.h: No such file or directory\n            config_options+=(\"--disable-oocd_trace\")\n\n          elif [ \"${XBB_HOST_PLATFORM}\" == \"linux\" ]\n          then\n\n            # --enable-minidriver-dummy -> configure error\n\n            # --enable-openjtag_ftdi -> --enable-openjtag\n            # --enable-presto_libftdi -> --enable-presto\n            # --enable-usb_blaster_libftdi -> --enable-usb_blaster\n\n            config_options+=(\"--enable-amtjtagaccel\")\n            config_options+=(\"--enable-buspirate\")\n            config_options+=(\"--enable-gw16012\")\n            config_options+=(\"--enable-parport\")\n            config_options+=(\"--enable-parport-giveio\")\n            config_options+=(\"--enable-sysfsgpio\")\n\n            # Deprecated\n            # config_options+=(\"--enable-oocd_trace\")\n\n          elif [ \"${XBB_HOST_PLATFORM}\" == \"darwin\" ]\n          then\n\n            # --enable-minidriver-dummy -> configure error\n\n            # --enable-openjtag_ftdi -> --enable-openjtag\n            # --enable-presto_libftdi -> --enable-presto\n            # --enable-usb_blaster_libftdi -> --enable-usb_blaster\n\n            config_options+=(\"--enable-buspirate\")\n\n            # --enable-amtjtagaccel -> 'sys/io.h' file not found\n            config_options+=(\"--disable-amtjtagaccel\")\n            # --enable-gw16012 -> 'sys/io.h' file not found\n            config_options+=(\"--disable-gw16012\")\n            config_options+=(\"--disable-parport\")\n            config_options+=(\"--disable-parport-giveio\")\n            # --enable-sysfsgpio -> available only on Linux\n            config_options+=(\"--disable-sysfsgpio\")\n\n            # /Users/ilg/Work/openocd-0.10.0-14/openocd.git/src/target/oocd_trace.c: In function ‘oocd_trace_init’:\n            # /Users/ilg/Work/openocd-0.10.0-14/openocd.git/src/target/oocd_trace.c:121:54: error: ‘B2500000’ undeclared (first use in this function)\n            config_options+=(\"--disable-oocd_trace\")\n\n          else\n\n            echo \"Unsupported XBB_HOST_PLATFORM=${XBB_HOST_PLATFORM} in ${FUNCNAME[0]}()\"\n            exit 1\n\n          fi\n\n          run_verbose bash ${DEBUG} \"${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}/configure\" \\\n            \"${config_options[@]}\"\n\n          cp \"config.log\" \"${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}/config-log-$(ndate).txt\"\n        ) 2>&1 | tee \"${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}/configure-output-$(ndate).txt\"\n\n      fi\n\n      (\n        echo\n        echo \"Running openocd make...\"\n\n        # Build.\n        # run_verbose make -j ${XBB_JOBS} bindir=\"bin\" pkgdatadir=\"\"\n        run_verbose make -j ${XBB_JOBS}\n\n        if [ \"${XBB_WITH_STRIP}\" == \"y\" ]\n        then\n          run_verbose make install-strip\n        else\n          run_verbose make install\n        fi\n\n        if [ \"${XBB_HOST_PLATFORM}\" == \"win32\" ]\n        then\n          rm -f \"${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}/bin/openocdw.exe\"\n        fi\n\n      ) 2>&1 | tee \"${XBB_LOGS_FOLDER_PATH}/${openocd_folder_name}/make-output-$(ndate).txt\"\n\n      copy_license \\\n        \"${XBB_SOURCES_FOLDER_PATH}/${openocd_src_folder_name}\" \\\n        \"${openocd_folder_name}\"\n    )\n\n    mkdir -pv \"${XBB_STAMPS_FOLDER_PATH}\"\n    touch \"${openocd_stamp_file_path}\"\n\n  else\n    echo \"Component openocd already installed\"\n  fi\n\n  tests_add \"openocd_test\" \"${XBB_EXECUTABLES_INSTALL_FOLDER_PATH}/bin\"\n}\n\nfunction openocd_test()\n{\n  local test_bin_path=\"$1\"\n\n  echo\n  echo \"Checking the openocd shared libraries...\"\n  show_host_libs \"${test_bin_path}/openocd\"\n\n  echo\n  echo \"Checking if openocd starts...\"\n\n  run_host_app_verbose \"${test_bin_path}/openocd\" --version\n\n  run_host_app_verbose \"${test_bin_path}/openocd\" \\\n    -c \"adapter driver dummy\" \\\n    -c \"adapter speed 1000\" \\\n    -c \"adapter list\" \\\n    -c \"transport list\" \\\n    -c \"target types\" \\\n    -c \"echo baburiba\" \\\n    -c \"shutdown\"\n\n}\n\n# -----------------------------------------------------------------------------\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/templates/body-github-release-liquid.md",
    "content": "![Github Releases (by Release)](https://img.shields.io/github/downloads/xpack-dev-tools/openocd-xpack/v{{ XBB_RELEASE_VERSION }}/total.svg)\n\nVersion **{{ XBB_RELEASE_VERSION }}** is a maintenance release of the **xPack OpenOCD** package; it updates to the latest upstream master.\n\nOr (TODO: edit!):\n\nVersion **{{ XBB_RELEASE_VERSION }}** is a new release of the **xPack OpenOCD** package, following the upstream OpenOCD release.\n\n[Continue reading »](TODO: edit, add URL!)\n\n_At this moment the binaries are provided for tests only!_\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/templates/body-jekyll-release-post-part-1-liquid.md",
    "content": "---\ntitle:  xPack OpenOCD v{{ XBB_RELEASE_VERSION }} released\n\nTODO: select one summary\n\nsummary: \"Version **{{ XBB_RELEASE_VERSION }}** is a maintenance release; it updates to\nthe latest upstream master.\"\n\nsummary: \"Version **{{ XBB_RELEASE_VERSION }}** is a new release; it follows the upstream release.\"\n\nupstream_version: \"0.12.0\"\nupstream_commit: \"9ea7f3d\"\nupstream_release_date: \"15 Jan 2022\"\n\nversion: \"{{ XBB_RELEASE_VERSION }}\"\nnpm_subversion: \"1\"\n\ndownload_url: https://github.com/xpack-dev-tools/openocd-xpack/releases/tag/v{{ XBB_RELEASE_VERSION }}/\n\ncomments: true\n\ndate:   {{ RELEASE_DATE }}\n\ncategories:\n  - releases\n  - openocd\n\ntags:\n  - releases\n  - openocd\n\n---\n\n[The xPack OpenOCD](https://xpack.github.io/openocd/)\nis a standalone cross-platform binary distribution of\n[OpenOCD](https://openocd.org).\n\nThere are separate binaries for **Windows** (Intel 64-bit),\n**macOS** (Intel 64-bit, Apple Silicon 64-bit)\nand **GNU/Linux** (Intel 64-bit, Arm 32/64-bit).\n\n{% raw %}{% include note.html content=\"The main targets for the Arm binaries\nare the **Raspberry Pi** class devices (armv7l and aarch64;\narmv6 is not supported).\" %}{% endraw %}\n\n## Download\n\nThe binary files are available from GitHub [Releases]({% raw %}{{ page.download_url }}{% endraw %}).\n\n## Prerequisites\n\n- GNU/Linux Intel 64-bit: any system with **GLIBC 2.27** or higher\n  (like Ubuntu 18 or later, Debian 10 or later, RedHat 8 later,\n  Fedora 29 or later, etc)\n- GNU/Linux Arm 32/64-bit: any system with **GLIBC 2.27** or higher\n  (like Raspberry Pi OS, Ubuntu 18 or later, Debian 10 or later, RedHat 8 later,\n  Fedora 29 or later, etc)\n- Intel Windows 64-bit: Windows 7 with the Universal C Runtime\n  ([UCRT](https://support.microsoft.com/en-us/topic/update-for-universal-c-runtime-in-windows-c0514201-7fe6-95a3-b0a5-287930f3560c)),\n  Windows 8, Windows 10\n- Intel macOS 64-bit: 10.13 or later\n- Apple Silicon macOS 64-bit: 11.6 or later\n\n## Install\n\nThe full details of installing the **xPack OpenOCD** on various platforms\nare presented in the separate\n[Install]({% raw %}{{ site.baseurl }}{% endraw %}/dev-tools/openocd/install/) page.\n\n### Easy install\n\nThe easiest way to install OpenOCD is with\n[`xpm`]({% raw %}{{ site.baseurl }}{% endraw %}/xpm/)\nby using the **binary xPack**, available as\n[`@xpack-dev-tools/openocd`](https://www.npmjs.com/package/@xpack-dev-tools/openocd)\nfrom the [`npmjs.com`](https://www.npmjs.com) registry.\n\nWith the `xpm` tool available, installing\nthe latest version of the package and adding it as\na development dependency for a project is quite easy:\n\n```sh\ncd my-project\nxpm init # Add a package.json if not already present\n\nxpm install @xpack-dev-tools/openocd@latest --verbose\n\nls -l xpacks/.bin\n```\n\nTo install this specific version, use:\n\n```sh\nxpm install @xpack-dev-tools/openocd@{% raw %}{{ page.version }}.{{ page.npm_subversion }}{% endraw %} --verbose\n```\n\nFor xPacks aware tools, like the **Eclipse Embedded C/C++ plug-ins**,\nit is also possible to install OpenOCD globally, in the user home folder.\n\n```sh\nxpm install --global @xpack-dev-tools/openocd@latest --verbose\n```\n\nEclipse will automatically\nidentify binaries installed with\n`xpm` and provide a convenient method to manage paths.\n\n### Uninstall\n\nTo remove the links created by xpm in the current project:\n\n```sh\ncd my-project\n\nxpm uninstall @xpack-dev-tools/openocd\n```\n\nTo completely remove the package from the central xPack store:\n\n```sh\nxpm uninstall --global @xpack-dev-tools/openocd\n```\n\n## Compliance\n\nThe xPack OpenOCD generally follows the official\n[OpenOCD](https://openocd.org) releases.\n\nThe current version is based on:\n\n- OpenOCD version {% raw %}{{ page.upstream_version }}{% endraw %}, the development commit\n[{% raw %}{{ page.upstream_commit }}{% endraw %}](https://github.com/xpack-dev-tools/openocd/commit/{% raw %}{{ page.upstream_commit }}{% endraw %}/)\nfrom {% raw %}{{ page.upstream_release_date }}{% endraw %}.\n\n## Changes\n\nThere are no functional changes.\n\nCompared to the upstream, the following changes were applied:\n\n- the `src/openocd.c` file was edited to display the branding string\n- the `contrib/60-openocd.rules` file was simplified to avoid protection\n  related issues.\n\n## Bug fixes\n\n- none\n\n## Enhancements\n\n- none\n\n## Known problems\n\n- none\n\n## Shared libraries\n\nOn all platforms the packages are standalone, and expect only the standard\nruntime to be present on the host.\n\nAll dependencies that are build as shared libraries are copied locally\nin the `libexec` folder (or in the same folder as the executable for Windows).\n\n### `DT_RPATH` and `LD_LIBRARY_PATH`\n\nOn GNU/Linux the binaries are adjusted to use a relative path:\n\n```console\n$ readelf -d library.so | grep runpath\n 0x000000000000001d (RPATH)            Library rpath: [$ORIGIN]\n```\n\nIn the GNU ld.so search strategy, the `DT_RPATH` has\nthe highest priority, higher than `LD_LIBRARY_PATH`, so if this later one\nis set in the environment, it should not interfere with the xPack binaries.\n\nPlease note that previous versions, up to mid-2020, used `DT_RUNPATH`, which\nhas a priority lower than `LD_LIBRARY_PATH`, and does not tolerate setting\nit in the environment.\n\n### `@rpath` and `@loader_path`\n\nSimilarly, on macOS, the binaries are adjusted with `install_name_tool` to use a\nrelative path.\n\n## Documentation\n\nThe original documentation is available online:\n\n- <https://openocd.org/doc/pdf/openocd.pdf>\n\n## Build\n\nThe binaries for all supported platforms\n(Windows, macOS and GNU/Linux) were built using the\n[xPack Build Box (XBB)](https://xpack.github.io/xbb/), a set\nof build environments based on slightly older distributions, that should be\ncompatible with most recent systems.\n\nThe scripts used to build this distribution are in:\n\n- `distro-info/scripts`\n\nFor the prerequisites and more details on the build procedure, please see the\n[How to build](https://github.com/xpack-dev-tools/openocd-xpack/blob/xpack/README-BUILD.md) page.\n\n## CI tests\n\nBefore publishing, a set of simple tests were performed on an exhaustive\nset of platforms. The results are available from:\n\n- [GitHub Actions](https://github.com/xpack-dev-tools/openocd-xpack/actions/)\n- [Travis CI](https://app.travis-ci.com/github/xpack-dev-tools/openocd-xpack/builds/)\n\n## Tests\n\nThe binaries were testes on Windows 10 Pro 32/64-bit, Intel Ubuntu 18\nLTS 64-bit, Intel Xubuntu 18 LTS 32-bit and macOS 10.15.\n\nInstall the package with xpm.\n\nThe simple test, consists in starting the binaries\nonly to identify the STM32F4DISCOVERY board.\n\n```sh\n.../xpack-openocd-{{ XBB_RELEASE_VERSION }}/bin/openocd -f board/stm32f4discovery.cfg\n```\n\nA more complex test consist in programming and debugging a simple blinky\napplication on the STM32F4DISCOVERY board. The binaries were\nthose generated by\n[simple Eclipse projects](https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/tree/xpack/tests/eclipse)\navailable in the **xPack GNU Arm Embedded GCC** project.\n\n## Checksums\n\nThe SHA-256 hashes for the files are:\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/templates/body-jekyll-release-post-part-2-liquid.md",
    "content": "\n## Deprecation notices\n\n### 32-bit support\n\nSupport for 32-bit Intel Linux and Intel Windows was\ndropped in 2022. Support for 32-bit Arm Linux (armv7l) will be preserved\nfor a while, due to the large user base of 32-bit Raspberry Pi systems.\n\n### Linux minimum requirements\n\nSupport for RedHat 7 was dropped in 2022 and the\nminimum requirement was raised to GLIBC 2.27, available starting\nwith Ubuntu 18, Debian 10 and RedHat 8.\n\n## Download analytics\n\n- GitHub [xpack-dev-tools/openocd-xpack](https://github.com/xpack-dev-tools/openocd-xpack/)\n  - this release [![Github All Releases](https://img.shields.io/github/downloads/xpack-dev-tools/openocd-xpack/v{% raw %}{{ page.version }}{% endraw %}/total.svg)](https://github.com/xpack-dev-tools/openocd-xpack/releases/v{% raw %}{{ page.version }}{% endraw %}/)\n  - all xPack releases [![Github All Releases](https://img.shields.io/github/downloads/xpack-dev-tools/openocd-xpack/total.svg)](https://github.com/xpack-dev-tools/openocd-xpack/releases/)\n  - all GNU MCU Eclipse releases [![Github All Releases](https://img.shields.io/github/downloads/gnu-mcu-eclipse/openocd/total.svg)](https://github.com/gnu-mcu-eclipse/openocd/releases/)\n  - [individual file counters](https://somsubhra.github.io/github-release-stats/?username=xpack-dev-tools&repository=openocd-xpack) (grouped per release)\n- npmjs.com [@xpack-dev-tools/openocd](https://www.npmjs.com/package/@xpack-dev-tools/openocd)\n  - latest releases [![npm](https://img.shields.io/npm/dw/@xpack-dev-tools/openocd.svg)](https://www.npmjs.com/package/@xpack-dev-tools/openocd/)\n  - all @xpack-dev-tools releases [![npm](https://img.shields.io/npm/dt/@xpack-dev-tools/openocd.svg)](https://www.npmjs.com/package/@xpack-dev-tools/openocd/)\n  - all @gnu-mcu-eclipse releases [![npm](https://img.shields.io/npm/dt/@gnu-mcu-eclipse/openocd.svg)](https://www.npmjs.com/package/@gnu-mcu-eclipse/openocd/)\n\nCredit to [Shields IO](https://shields.io) for the badges and to\n[Somsubhra/github-release-stats](https://github.com/Somsubhra/github-release-stats)\nfor the individual file counters.\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/test.sh",
    "content": "#!/usr/bin/env bash\n# -----------------------------------------------------------------------------\n# DO NOT EDIT! Generated from xpacks/@xpack-dev-tools/xbb-helper/templates/*.\n#\n# This file is part of the xPack distribution.\n#   (https://xpack.github.io)\n# Copyright (c) 2020 Liviu Ionescu.\n#\n# Permission to use, copy, modify, and/or distribute this software\n# for any purpose is hereby granted, under the terms of the MIT license.\n# -----------------------------------------------------------------------------\n\n# -----------------------------------------------------------------------------\n# Safety settings (see https://gist.github.com/ilg-ul/383869cbb01f61a51c4d).\n\nif [[ ! -z ${DEBUG} ]]\nthen\n  set ${DEBUG} # Activate the expand mode if DEBUG is anything but empty.\nelse\n  DEBUG=\"\"\nfi\n\nset -o errexit # Exit if command failed.\nset -o pipefail # Exit if pipe failed.\nset -o nounset # Exit if variable not set.\n\n# Remove the initial space and instead use '\\n'.\nIFS=$'\\n\\t'\n\n# -----------------------------------------------------------------------------\n# Identify the script location, to reach, for example, the helper scripts.\n\nscript_path=\"$0\"\nif [[ \"${script_path}\" != /* ]]\nthen\n  # Make relative path absolute.\n  script_path=\"$(pwd)/$0\"\nfi\n\nscript_name=\"$(basename \"${script_path}\")\"\n\nscript_folder_path=\"$(dirname \"${script_path}\")\"\nscript_folder_name=\"$(basename \"${script_folder_path}\")\"\n\n# =============================================================================\n# Run the application tests.\n\nscripts_folder_path=\"${script_folder_path}\"\nproject_folder_path=\"$(dirname ${script_folder_path})\"\nhelper_folder_path=\"${project_folder_path}/xpacks/@xpack-dev-tools/xbb-helper\"\n\ntests_folder_path=\"$(dirname \"${scripts_folder_path}\")/tests\"\n\n# -----------------------------------------------------------------------------\n\nsource \"${scripts_folder_path}/application.sh\"\n\n# Common definitions.\nsource \"${helper_folder_path}/scripts/test-common.sh\"\n\n# Possibly override common definitions.\nsource \"${scripts_folder_path}/tests/run.sh\"\nif [ -f \"${scripts_folder_path}/tests/update.sh\" ]\nthen\n  source \"${scripts_folder_path}/tests/update.sh\"\nfi\n\nif [ ${#XBB_APPLICATION_COMMON_DEPENDENCIES[@]} -ne 0 ]\nthen\n  for dependency in ${XBB_APPLICATION_COMMON_DEPENDENCIES[@]}\n  do\n    echo \"Including ${helper_folder_path}/dependencies/${dependency}.sh...\"\n    source \"${helper_folder_path}/dependencies/${dependency}.sh\"\n  done\nfi\n\nif [ ${#XBB_APPLICATION_DEPENDENCIES[@]} -ne 0 ]\nthen\n  for dependency in ${XBB_APPLICATION_DEPENDENCIES[@]}\n  do\n    echo \"Including ${scripts_folder_path}/dependencies/${dependency}.sh...\"\n    source \"${scripts_folder_path}/dependencies/${dependency}.sh\"\n  done\nfi\n\n# -----------------------------------------------------------------------------\n\ntests_parse_options \"$@\"\n\ntests_perform_common\n\n# Completed successfully.\nexit 0\n\n# -----------------------------------------------------------------------------\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/tests/run.sh",
    "content": "# -----------------------------------------------------------------------------\n# This file is part of the xPack distribution.\n#   (https://xpack.github.io)\n# Copyright (c) 2020 Liviu Ionescu.\n#\n# Permission to use, copy, modify, and/or distribute this software\n# for any purpose is hereby granted, under the terms of the MIT license.\n# -----------------------------------------------------------------------------\n\n# -----------------------------------------------------------------------------\n# Included by `scrips/test.sh`.\n\nfunction tests_run_all()\n{\n  local test_bin_path=\"$1\"\n\n  openocd_test \"${test_bin_path}\"\n}\n\n# -----------------------------------------------------------------------------\n"
  },
  {
    "path": "openocd-win/openocd/distro-info/scripts/versioning.sh",
    "content": "# -----------------------------------------------------------------------------\n# This file is part of the xPacks distribution.\n#   (https://xpack.github.io)\n# Copyright (c) 2019 Liviu Ionescu.\n#\n# Permission to use, copy, modify, and/or distribute this software\n# for any purpose is hereby granted, under the terms of the MIT license.\n# -----------------------------------------------------------------------------\n\n# -----------------------------------------------------------------------------\n\nfunction application_build_versioned_components()\n{\n  XBB_OPENOCD_VERSION=\"$(xbb_strip_version_pre_release \"${XBB_RELEASE_VERSION}\")\"\n\n  # Keep them in sync with the combo archive content.\n  if [[ \"${XBB_RELEASE_VERSION}\" =~ 0[.]12[.]0-.* ]]\n  then\n    XBB_OPENOCD_GIT_URL=${XBB_APPLICATION_OPENOCD_GIT_URL:-\"https://github.com/openocd-org/openocd.git\"}\n    XBB_OPENOCD_GIT_BRANCH=${XBB_APPLICATION_OPENOCD_GIT_BRANCH:-\"master\"}\n\n    if [ \"${XBB_RELEASE_VERSION}\" == \"0.12.0-1\" ]\n    then\n      XBB_OPENOCD_GIT_COMMIT=${XBB_APPLICATION_OPENOCD_GIT_COMMIT:-\"v0.12.0\"}\n    elif [ \"${XBB_RELEASE_VERSION}\" == \"0.12.0-2\" ]\n    then\n      # Sep 2, 2023\n      XBB_OPENOCD_GIT_COMMIT=${XBB_APPLICATION_OPENOCD_GIT_COMMIT:-\"18281b0c497694d91c5608be54583172838be75c\"}\n    else\n      echo \"Unsupported ${XBB_APPLICATION_LOWER_CASE_NAME} version ${XBB_RELEASE_VERSION}\"\n      exit 1\n    fi\n\n    # -------------------------------------------------------------------------\n    # Build the native dependencies.\n\n    autotools_build\n\n    # https://ftp.gnu.org/gnu/texinfo/\n    texinfo_build \"7.0.3\"\n\n    # -------------------------------------------------------------------------\n    # Build the target dependencies.\n\n    xbb_reset_env\n    # Before set target (to possibly update CC & co variables).\n    xbb_activate_installed_bin\n\n    xbb_set_target \"requested\"\n\n    # -------------------------------------------------------------------------\n\n    # https://ftp.gnu.org/pub/gnu/libiconv/\n    libiconv_build \"1.17\"\n\n    # -------------------------------------------------------------------------\n\n    # https://sourceforge.net/projects/libusb/files/libusb-1.0/\n    libusb1_build \"1.0.26\"\n\n    # Starting with v0.12.0, libusb0 is no longer needed.\n    # if [ \"${XBB_REQUESTED_HOST_PLATFORM}\" == \"win32\" ]\n    # then\n    #   # https://sourceforge.net/projects/libusb-win32/files/libusb-win32-releases/\n    #   libusb_w32_build \"1.2.7.3\" # \"1.2.6.0\" # ! PATCH & pkgconfig\n    # else\n    #   # https://sourceforge.net/projects/libusb/files/libusb-compat-0.1/\n    #   # required by libjaylink\n    #   libusb0_build \"0.1.8\"\n    # fi\n\n    # https://www.intra2net.com/en/developer/libftdi/download.php\n    libftdi_build \"1.5\" # ! PATCH\n\n    # https://github.com/libusb/hidapi/releases\n    hidapi_build \"0.14.0\" # \"0.12.0\"\n\n    # -------------------------------------------------------------------------\n    # Build the application binaries.\n\n    xbb_set_executables_install_path \"${XBB_APPLICATION_INSTALL_FOLDER_PATH}\"\n    xbb_set_libraries_install_path \"${XBB_DEPENDENCIES_INSTALL_FOLDER_PATH}\"\n\n    openocd_build \"${XBB_OPENOCD_VERSION}\"\n\n    # -------------------------------------------------------------------------\n  elif [[ \"${XBB_RELEASE_VERSION}\" =~ 0[.]11[.]0-[5] ]]\n  then\n\n    XBB_OPENOCD_GIT_URL=${XBB_OPENOCD_GIT_URL:-\"https://github.com/xpack-dev-tools/openocd.git\"}\n\n    XBB_OPENOCD_GIT_BRANCH=${XBB_OPENOCD_GIT_BRANCH:-\"xpack\"}\n    # XBB_OPENOCD_GIT_BRANCH=${XBB_OPENOCD_GIT_BRANCH:-\"xpack-develop\"}\n    XBB_OPENOCD_GIT_COMMIT=${XBB_OPENOCD_GIT_COMMIT:-\"v${XBB_RELEASE_VERSION}-xpack\"}\n\n    # -------------------------------------------------------------------------\n    # Build the native dependencies.\n\n    autotools_build\n\n    # https://ftp.gnu.org/gnu/texinfo/\n    texinfo_build \"6.8\"\n\n    # -------------------------------------------------------------------------\n    # Build the target dependencies.\n\n    xbb_reset_env\n    # Before set target (to possibly update CC & co variables).\n    xbb_activate_installed_bin\n\n    xbb_set_target \"requested\"\n\n    # -------------------------------------------------------------------------\n\n    if [ \"${XBB_REQUESTED_HOST_PLATFORM}\" != \"darwin\" ]\n    then\n\n      # https://ftp.gnu.org/pub/gnu/libiconv/\n      libiconv_build \"1.17\" # \"1.16\"\n\n    fi\n\n    # -------------------------------------------------------------------------\n\n    # https://sourceforge.net/projects/libusb/files/libusb-1.0/\n    libusb1_build \"1.0.26\"\n\n    if [ \"${XBB_REQUESTED_HOST_PLATFORM}\" == \"win32\" ]\n    then\n      # https://sourceforge.net/projects/libusb-win32/files/libusb-win32-releases/\n      libusb_w32_build \"1.2.6.0\" # ! PATCH & pkgconfig\n    else\n      # https://sourceforge.net/projects/libusb/files/libusb-compat-0.1/\n      # required by libjaylink\n      libusb0_build \"0.1.5\"\n    fi\n\n    # https://www.intra2net.com/en/developer/libftdi/download.php\n    libftdi_build \"1.5\" # ! PATCH\n\n    # https://github.com/libusb/hidapi/releases\n    hidapi_build \"0.12.0\" # \"0.10.1\" # ! pkgconfig/hidapi-*-windows.pc\n\n    # -------------------------------------------------------------------------\n    # Build the application binaries.\n\n    xbb_set_executables_install_path \"${XBB_APPLICATION_INSTALL_FOLDER_PATH}\"\n    xbb_set_libraries_install_path \"${XBB_DEPENDENCIES_INSTALL_FOLDER_PATH}\"\n\n    openocd_build \"${XBB_OPENOCD_VERSION}\"\n\n    # -------------------------------------------------------------------------\n  else\n    echo \"Unsupported ${XBB_APPLICATION_LOWER_CASE_NAME} version ${XBB_RELEASE_VERSION}\"\n    exit 1\n  fi\n}\n\n# -----------------------------------------------------------------------------\n"
  },
  {
    "path": "openocd-win/openocd/scripts/bitsbytes.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#----------------------------------------\n# Purpose - Create some $BIT variables\n#           Create $K and $M variables\n#          and some bit field extraction variables.\n# Create helper variables ...\n#    BIT0.. BIT31\n\nfor { set x 0  } { $x < 32 } { set x [expr {$x + 1}]} {\n    set vn [format \"BIT%d\" $x]\n    global $vn\n    set $vn   [expr {1 << $x}]\n}\n\n# Create K bytes values\n#    __1K ... to __2048K\nfor { set x 1  } { $x < 2048 } { set x [expr {$x * 2}]} {\n    set vn [format \"__%dK\" $x]\n    global $vn\n    set $vn   [expr {1024 * $x}]\n}\n\n# Create M bytes values\n#    __1M ... to __2048K\nfor { set x 1  } { $x < 2048 } { set x [expr {$x * 2}]} {\n    set vn [format \"__%dM\" $x]\n    global $vn\n    set $vn [expr {1024 * 1024 * $x}]\n}\n\nproc create_mask { MSB LSB } {\n    return [expr {((1 << ($MSB - $LSB + 1))-1) << $LSB}]\n}\n\n# Cut Bits $MSB to $LSB out of this value.\n# Example: % format \"0x%08x\" [extract_bitfield 0x12345678 27 16]\n# Result:  0x02340000\n\nproc extract_bitfield { VALUE MSB LSB } {\n    return [expr {[create_mask $MSB $LSB] & $VALUE}]\n}\n\n\n# Cut bits $MSB to $LSB out of this value\n# and shift (normalize) them down to bit 0.\n#\n# Example: % format \"0x%08x\" [normalize_bitfield 0x12345678 27 16]\n# Result:  0x00000234\n#\nproc normalize_bitfield { VALUE MSB LSB } {\n    return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}]\n}\n\nproc show_normalize_bitfield { VALUE MSB LSB } {\n    set m [create_mask $MSB $LSB]\n    set mr [expr {$VALUE & $m}]\n    set sr [expr {$mr >> $LSB}]\n    echo [format \"((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d \" $VALUE $m $mr $LSB $sr $sr]\n   return $sr\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/8devices-lima.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Product page:\n# https://www.8devices.com/products/lima\n#\n# Location of JTAG pins:\n# J2 GPIO0\tJTAG TCK\n# J2 GPIO1\tJTAG TDI\n# J2 GPIO2\tJTAG TDO\n# J2 GPIO3\tJTAG TMS\n# J2 RST\tdirectly connected to RESET_L of the SoC and can be used as\n#               JTAG SRST. Note: this pin will also reset the debug engine.\n# J1 +3,3V\tCan be use as JTAG Vref\n# J1 or J2 GND\tCan be used for JTAG GND\n#\n# This board is powered from mini USB connecter which is also used\n# as USB to UART converted based on FTDI FT230XQ chip\n\nsource [find target/qualcomm_qca4531.cfg]\n\nproc board_init { } {\n\tqca4531_ddr2_550_550_init\n}\n\n$_TARGETNAME configure -event reset-init {\n\tboard_init\n}\n\nset ram_boot_address 0xa0000000\n$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000\n\nflash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/actux3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# board config file for AcTux3/XBA IXP42x board\n# Date:   2010-12-16\n# Author: Michael Schwingen <michael@schwingen.org>\n\nreset_config trst_and_srst separate\n\nadapter srst delay 100\njtag_ntrst_delay 100\n\nsource [find target/ixp42x.cfg]\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0\n\n$_TARGETNAME configure -event reset-init { init_actux3 }\n\nproc init_actux3 { } {\n    ##########################################################################\n    # setup expansion bus CS\n    ##########################################################################\n    mww 0xc4000000  0xbd113842  ;#CS0  : Flash, write enabled @0x50000000\n    mww 0xc4000004  0x94d10013  ;#CS1\n    mww 0xc4000008  0x95960003  ;#CS2\n    mww 0xc400000c  0x00000000  ;#CS3\n    mww 0xc4000010  0x80900003  ;#CS4\n    mww 0xc4000014  0x9d520003  ;#CS5\n    mww 0xc4000018  0x81860001  ;#CS6\n    mww 0xc400001c  0x80900003  ;#CS7\n\n    ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3\n\n    #mww 0xc4000020  0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000\n\n    ixp42x_set_bigendian\n\n    flash probe 0\n}\n\nproc flash_boot { {FILE \"/tftpboot/actux3/u-boot.bin\"} } {\n    echo \"writing bootloader: $FILE\"\n    flash write_image erase $FILE 0x50000000 bin\n}\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME\n\ninit\nreset init\n\n# setup to debug u-boot in flash\nproc uboot_debug {} {\n    gdb_breakpoint_override hard\n    xscale vector_catch 0xFF\n\n    xscale vector_table low  1 0xe59ff018\n    xscale vector_table low  2 0xe59ff018\n    xscale vector_table low  3 0xe59ff018\n    xscale vector_table low  4 0xe59ff018\n    xscale vector_table low  5 0xe59ff018\n    xscale vector_table low  6 0xe59ff018\n    xscale vector_table low  7 0xe59ff018\n\n    xscale vector_table high 1 0xe59ff018\n    xscale vector_table high 2 0xe59ff018\n    xscale vector_table high 3 0xe59ff018\n    xscale vector_table high 4 0xe59ff018\n    xscale vector_table high 5 0xe59ff018\n    xscale vector_table high 6 0xe59ff018\n    xscale vector_table high 7 0xe59ff018\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/adapteva_parallella1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Adapteva Parallella-I board (via Porcupine-1 adapter board)\n#\n\nreset_config srst_only\n\nsource [find target/zynq_7000.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/adsp-sc584-ezbrd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Analog Devices ADSP-SC584-EZBRD evaluation board\n#\n# Evaluation boards by Analog Devices (and designs derived from them) use a\n# non-standard 10-pin 0.05\" ARM Cortex Debug Connector.  In this bastardized\n# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST.\n#\n# As a result, a standards-compliant debug pod will force /TRST active,\n# putting the processor's debug interface into reset and preventing usage.\n#\n# A connector adapter must be employed on these boards to isolate or remap\n# /TRST so that it is only asserted when intended.\n\n# Analog expects users to use their proprietary ICE-1000 / ICE-2000 with all\n# ADSP-SC58x designs, but this is an ARM target (and subject to the\n# qualifications above) many ARM debug pods should be compatible.\n\n#source [find interface/cmsis-dap.cfg]\nsource [find interface/jlink.cfg]\n\n# Analog's silicon supports SWD and JTAG, but their proprietary ICE is limited\n# to JTAG.  (This is presumably why their connector pinout was modified.)\n# SWD is chosen here, as it is more efficient and doesn't require /TRST.\n\ntransport select swd\n\n# chosen speed is 'safe' choice, but your adapter may be capable of more\nadapter speed 400\n\nsource [find target/adsp-sc58x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/alphascale_asm9260_ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/alphascale_asm9260t.cfg]\n\nreset_config trst_and_srst\n\n$_TARGETNAME configure -event reset-init {\n\techo \"Configure clock\"\n\t# Enable SRAM clk\n\tmww 0x80040024 0x4\n\t# Enable IRQ clk\n\tmww 0x80040034 0x100\n\t# Enable DMA0,1 clk\n\tmww 0x80040024 0x600\n\t# Make sysre syspll is enabled\n\tmww 0x80040238 0x750\n\t#CPU = PLLCLK/2\n\tmww 0x8004017C 0x2\n\t#SYSAHBCLK = CPUCLK/2\n\tmww 0x80040180 0x2\n\t# Set PLL freq to 480MHz\n\tmww 0x80040100 480\n\t# normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)\n\tsleep 100\n\n\t# select PLL as main source\n\tmww 0x80040120 0x1\n\t# disable and enable main clk to update changes?\n\tmww 0x80040124 0x0\n\tmww 0x80040124 0x1\n\n\techo \"Configure memory\"\n\t#enable EMI CLK\n\tmww 0x80040024 0x40\n\n\t# configure memory controller for internal SRAM\n\tmww 0x80700000 0x1188\n\t# change default emi clk delay\n\tmww 0x8004034C 0xA0503\n\t# make sure chip_select_register2_low has correct value (why?)\n\tmww 0x8070001c 0x20000000\n\t# set type to sdram and size to 32MB\n\tmww 0x8070005c 0xa\n\t# configure internal SDRAM timing\n\tmww 0x80700004 0x024996d9\n\t# configure Static Memory timing\n\tmww 0x80700094 0x00542b4f\n\n\techo \"Configure uart4\"\n\t# enable pinctrl clk\n\tmww 0x80040024 0x2000000\n\t# mux GPIO3_0 and GPIO3_1 to UART4\n\tmww 0x80044060 0x2\n\tmww 0x80044064 0x2\n\t# configure UART4CLKDIV\n\tmww 0x800401a8 0x1\n\t# enable uart4 clk\n\tmww 0x80040024 0x8000\n\t# clear softrst and clkgate on uart4\n\tmww 0x80010008 0xC0000000\n\t# set bandrate 115200 12M\n\tmww 0x80010030 0x00062070\n\t# enable Rx&Tx\n\tmww 0x80010024 0x301\n\t# clear hw control\n\tmww 0x80010028 0xc000\n}\n\n$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000\n$_TARGETNAME arm7_9 fast_memory_access enable\n$_TARGETNAME arm7_9 dcc_downloads enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/altera_sockit.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Cyclone V SocKit board\n# http://www.altera.com/b/arrow-sockit.html\n#\n# Software support page:\n# http://www.rocketboards.org/\n\n# openocd does not currently support the on-board USB Blaster II.\n# Install the JTAG header and use a USB Blaster instead.\nadapter driver usb_blaster\n\nsource [find target/altera_fpgasoc.cfg]\n\n# If the USB Blaster II were supported, these settings would be needed\n#usb_blaster vid_pid 0x09fb 0x6810\n#usb_blaster device_desc \"USB-Blaster II\"\n\nadapter speed 100\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/am3517evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# DANGER!!!! early work in progress for this PCB/target.\n#\n# The most basic operations work well enough that it is\n# useful to have this in the repository for cooperation\n# alpha testing purposes.\n#\n# TI AM3517\n#\n# http://focus.ti.com/docs/prod/folders/print/am3517.html\n# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)\n# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x\n\nset CHIPTYPE \"am35x\"\nsource [find target/amdm37x.cfg]\n\n# The TI-14 JTAG connector does not have srst.  CPU reset is handled in\n# hardware.\nreset_config trst_only\n\n# \"amdm37x_dbginit am35x.cpu\" needs to be run after init.\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ampere_emag8180.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# OpenOCD Board Configuration for eMAG Development Platform\n#\n# Copyright (c) 2019-2021, Ampere Computing LLC\n#\n\n#\n# Configure JTAG speed\n#\n\nadapter speed 2000\n\n#\n# Configure Resets\n#\n\njtag_ntrst_delay 100\nreset_config trst_only\n\n#\n# Configure Targets\n#\n\nsource [find target/ampere_emag.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ampere_qs_mq_1s.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# OpenOCD Board Configuration for Ampere Altra (\"Quicksilver\") and\n# Ampere Altra Max (\"Mystique\") processors\n#\n# Copyright (c) 2019-2021, Ampere Computing LLC\n\n# Argument Description\n#\n# JTAGFREQ\n# Set the JTAG clock frequency\n# Syntax: -c \"set JTAGFREQ {freq_in_khz}\"\n#\n# SYSNAME\n# Set the system name\n# If not specified, defaults to \"qs\"\n# Syntax: -c \"set SYSNAME {qs}\"\n#\n# Life-Cycle State (LCS)\n# If not specified, defaults to \"Secure LCS\"\n# LCS=0, \"Secure LCS\"\n# LCS=1, \"Chip Manufacturing LCS\"\n# Syntax: -c \"set LCS {0}\"\n# Syntax: -c \"set LCS {1}\"\n#\n# CORELIST_S0\n# Specify available physical cores by number\n# Example syntax to connect to physical cores 16 and 17 for S0\n# Syntax: -c \"set CORELIST_S0 {16 17}\"\n#\n# COREMASK_S0_LO\n# Specify available physical cores 0-63 by mask\n# Example syntax to connect to physical cores 16 and 17 for S0\n# Syntax: -c \"set COREMASK_S0_LO {0x0000000000030000}\"\n#\n# COREMASK_S0_HI\n# Specify available physical cores 64 and above by mask\n# Example syntax to connect to physical cores 94 and 95 for S0\n# Syntax: -c \"set COREMASK_S0_HI {0x00000000C0000000}\"\n#\n# PHYS_IDX\n# Enable OpenOCD ARMv8 core target physical indexing\n# If not specified, defaults to OpenOCD ARMv8 core target logical indexing\n# Syntax: -c \"set PHYS_IDX {}\"\n\n#\n# Configure JTAG speed\n#\n\nif { [info exists JTAGFREQ] } {\n\tadapter speed $JTAGFREQ\n} else {\n\tadapter speed 100\n}\n\n#\n# Set the system name\n#\n\nif { [info exists SYSNAME] } {\n\tset _SYSNAME $SYSNAME\n} else {\n\tset _SYSNAME qs\n}\n\n#\n# Configure Resets\n#\n\njtag_ntrst_delay 100\nreset_config trst_only\n\n#\n# Configure Targets\n#\n\nif { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] } {\n\tset CHIPNAME ${_SYSNAME}0\n\tif { [info exists CORELIST_S0] } {\n\t\tset CORELIST $CORELIST_S0\n\t} else {\n\t\tif { [info exists COREMASK_S0_LO] } {\n\t\t\tset COREMASK_LO $COREMASK_S0_LO\n\t\t} else {\n\t\t\tset COREMASK_LO 0x0\n\t\t}\n\n\t\tif { [info exists COREMASK_S0_HI] } {\n\t\t\tset COREMASK_HI $COREMASK_S0_HI\n\t\t} else {\n\t\t\tset COREMASK_HI 0x0\n\t\t}\n\t}\n} else {\n\tset CHIPNAME ${_SYSNAME}0\n\tset COREMASK_LO 0x1\n\tset COREMASK_HI 0x0\n}\n\nsource [find target/ampere_qs_mq.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ampere_qs_mq_2s.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# OpenOCD Board Configuration for Ampere Altra (\"Quicksilver\") and\n# Ampere Altra Max (\"Mystique\") processors\n#\n# Copyright (c) 2019-2021, Ampere Computing LLC\n\n# Argument Description\n#\n# JTAGFREQ\n# Set the JTAG clock frequency\n# Syntax: -c \"set JTAGFREQ {freq_in_khz}\"\n#\n# SYSNAME\n# Set the system name\n# If not specified, defaults to \"qs\"\n# Syntax: -c \"set SYSNAME {qs}\"\n#\n# Life-Cycle State (LCS)\n# If not specified, defaults to \"Secure LCS\"\n# LCS=0, \"Secure LCS\"\n# LCS=1, \"Chip Manufacturing LCS\"\n# Syntax: -c \"set LCS {0}\"\n# Syntax: -c \"set LCS {1}\"\n#\n# CORELIST_S0, CORELIST_S1\n# Specify available physical cores by number\n# Example syntax to connect to physical cores 16 and 17 for S0 and S1\n# Syntax: -c \"set CORELIST_S0 {16 17}\"\n# Syntax: -c \"set CORELIST_S1 {16 17}\"\n#\n# COREMASK_S0_LO, COREMASK_S1_LO\n# Specify available physical cores 0-63 by mask\n# Example syntax to connect to physical cores 16 and 17 for S0 and S1\n# Syntax: -c \"set COREMASK_S0_LO {0x0000000000030000}\"\n# Syntax: -c \"set COREMASK_S1_LO {0x0000000000030000}\"\n#\n# COREMASK_S0_HI, COREMASK_S1_HI\n# Specify available physical cores 64 and above by mask\n# Example syntax to connect to physical cores 94 and 95 for S0 and S1\n# Syntax: -c \"set COREMASK_S0_HI {0x00000000C0000000}\"\n# Syntax: -c \"set COREMASK_S1_HI {0x00000000C0000000}\"\n#\n# SPLITSMP\n# Group all ARMv8 cores per socket into individual SMP sessions\n# If not specified, group ARMv8 cores from both sockets into one SMP session\n# Syntax: -c \"set SPLITSMP {}\"\n#\n# PHYS_IDX\n# Enable OpenOCD ARMv8 core target physical indexing\n# If not specified, defaults to OpenOCD ARMv8 core target logical indexing\n# Syntax: -c \"set PHYS_IDX {}\"\n\n#\n# Configure JTAG speed\n#\n\nif { [info exists JTAGFREQ] } {\n\tadapter speed $JTAGFREQ\n} else {\n\tadapter speed 100\n}\n\n#\n# Set the system name\n#\n\nif { [info exists SYSNAME] } {\n\tset _SYSNAME $SYSNAME\n} else {\n\tset _SYSNAME qs\n}\n\n#\n# Configure Board level SMP configuration if necessary\n#\n\nif { ![info exists SPLITSMP] } {\n\t# Group dual chip into a single SMP configuration\n\tset SMP_STR \"target smp\"\n\tset CORE_INDEX_OFFSET 0\n\tset DUAL_SOCKET_SMP_ENABLED \"\"\n}\n\n#\n# Configure Resets\n#\n\njtag_ntrst_delay 100\nreset_config trst_only\n\n#\n# Configure Targets\n#\n\nif { [info exists CORELIST_S0] || [info exists COREMASK_S0_LO] || [info exists COREMASK_S0_HI] || \\\n     [info exists CORELIST_S1] || [info exists COREMASK_S1_LO] || [info exists COREMASK_S1_HI] } {\n\tset CHIPNAME ${_SYSNAME}1\n\tif { [info exists CORELIST_S1] } {\n\t\tset CORELIST $CORELIST_S1\n\t} else {\n\t\tif { [info exists COREMASK_S1_LO] } {\n\t\t\tset COREMASK_LO $COREMASK_S1_LO\n\t\t} else {\n\t\t\tset COREMASK_LO 0x0\n\t\t}\n\n\t\tif { [info exists COREMASK_S1_HI] } {\n\t\t\tset COREMASK_HI $COREMASK_S1_HI\n\t\t} else {\n\t\t\tset COREMASK_HI 0x0\n\t\t}\n\t}\n\tsource [find target/ampere_qs_mq.cfg]\n\n\tif { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {\n\t\tif { [info exists MQ_ENABLE] } {\n\t\t\tset CORE_INDEX_OFFSET 128\n\t\t} else {\n\t\t\tset CORE_INDEX_OFFSET 80\n\t\t}\n\t}\n\n\tset CHIPNAME ${_SYSNAME}0\n\tif { [info exists CORELIST_S0] } {\n\t\tset CORELIST $CORELIST_S0\n\t} else {\n\t\tif { [info exists COREMASK_S0_LO] } {\n\t\t\tset COREMASK_LO $COREMASK_S0_LO\n\t\t} else {\n\t\t\tset COREMASK_LO 0x0\n\t\t}\n\n\t\tif { [info exists COREMASK_S0_HI] } {\n\t\t\tset COREMASK_HI $COREMASK_S0_HI\n\t\t} else {\n\t\t\tset COREMASK_HI 0x0\n\t\t}\n\t}\n\tsource [find target/ampere_qs_mq.cfg]\n} else {\n\tset CHIPNAME ${_SYSNAME}1\n\tset COREMASK_LO 0x0\n\tset COREMASK_HI 0x0\n\tsource [find target/ampere_qs_mq.cfg]\n\n\tif { [info exists DUAL_SOCKET_SMP_ENABLED] && [info exists PHYS_IDX]} {\n\t\tif { [info exists MQ_ENABLE] } {\n\t\t\tset CORE_INDEX_OFFSET 128\n\t\t} else {\n\t\t\tset CORE_INDEX_OFFSET 80\n\t\t}\n\t}\n\n\tset CHIPNAME ${_SYSNAME}0\n\tset COREMASK_LO 0x1\n\tset COREMASK_HI 0x0\n\tsource [find target/ampere_qs_mq.cfg]\n}\n\nif { [info exists DUAL_SOCKET_SMP_ENABLED] } {\n\t# For dual socket SMP configuration, evaluate the string\n\teval $SMP_STR\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/arm_evaluator7t.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This board is from ARM and has an samsung s3c45101x01 chip\n\nsource [find target/samsung_s3c4510.cfg]\n\n#\n# FIXME:\n#  Add (A) sdram configuration\n#  Add (B) flash cfi programming configuration\n#\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/arm_musca_a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Configuration script for ARM Musca-A development board\n#\n# For now we do not support Musca A flash programming using OpenOCD. However, a\n# work area is configured for flash programming speed up.\n#\n# GDB considers all memory as RAM unless target supplies a memory map.\n# OpenOCD will only send memory map if flash banks are configured. Otherwise,\n# configure GDB after connection by issuing following commands:\n# (gdb) mem 0x10200000 0x109FFFFF ro\n# (gdb) mem 0x00200000 0x009FFFFF ro\n# (gdb) set mem inaccessible-by-default off\n\n# ARM Musca A board supports both JTAG and SWD transports.\nsource [find target/swj-dp.tcl]\n\n# set a safe JTAG clock speed, can be overridden\nadapter speed 1000\n\nglobal _CHIPNAME\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME MUSCA_A\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x6ba00477\n}\n\n# Enable CPU1 debugging as a separate GDB target\nset _ENABLE_CPU1 1\n\n# Musca A1 has 32KB SRAM banks. Override default work-area-size to 8KB per CPU\nset WORKAREASIZE_CPU0 0x2000\nset WORKAREASIZE_CPU1 0x2000\n\n# Set SRAM bank 1 to be used for work area. Override here if needed.\nset WORKAREAADDR_CPU0 0x30008000\nset WORKAREAADDR_CPU1 0x3000A000\n\nsource [find target/arm_corelink_sse200.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/arty_s7.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Arty S7: Spartan7 25/50 FPGA Board for Makers and Hobbyists\n#\n# https://www.xilinx.com/products/boards-and-kits/1-pnziih.html\n# https://store.digilentinc.com/arty-s7-spartan-7-fpga-board-for-makers-and-hobbyists/\n\nsource [find interface/ftdi/digilent-hs1.cfg]\n\n# Xilinx Spartan7-25/50 FPGA (XC7S{25,50}-CSGA324)\nsource [find cpld/xilinx-xc7.cfg]\nsource [find cpld/jtagspi.cfg]\n\nadapter speed 25000\n\n# Usage:\n#\n# Load Bitstream into FPGA:\n#    openocd -f board/arty_s7.cfg -c \"init;\\\n#    pld load 0 bitstream.bit;\\\n#    shutdown\"\n#\n# Write Bitstream to Flash:\n#    openocd -f board/arty_s7.cfg -c \"init;\\\n#    jtagspi_init 0 bscan_spi_xc7s??.bit;\\\n#    jtagspi_program bitstream.bin 0;\\\n#    xc7_program xc7.tap;\\\n#    shutdown\"\n#\n# jtagspi flash proxies can be found at:\n# https://github.com/quartiq/bscan_spi_bitstreams\n#\n# For the Spartan 50 variant, use\n#  - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s50.bit\n# For the Spartan 25 variant, use\n#  - https://github.com/quartiq/bscan_spi_bitstreams/raw/master/bscan_spi_xc7s25.bit\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/asus-rt-n16.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# http://wikidevi.com/wiki/ASUS_RT-N16\n#\n\nset partition_list {\n    CFE\t\t{ Bootloader\t\t\t0xbc000000 0x00040000 }\n    firmware\t{ \"Kernel+rootfs\"\t\t0xbc040000 0x01fa0000 }\n    nvram\t{ \"Config space\"\t\t0xbdfe0000 0x00020000 }\n}\n\nsource [find target/bcm4718.cfg]\n\n# External 32MB NOR Flash (Macronix MX29GL256EHTI2I-90Q)\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0xbc000000 0x02000000 1 1 $_TARGETNAME x16_as_x8\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/asus-rt-n66u.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# http://wikidevi.com/wiki/Asus_RT-N66U\n#\n\necho \"ATTENTION: you need to solder a 4.7-10k pullup resistor to pin 21 of flash IC\"\necho \"to enable JTAG, see http://wl500g.info/album.php?albumid=28&attachmentid=8991 ,\"\necho \"there is an unpopulated footprint near U8.\\n\"\n\nset partition_list {\n    CFE\t\t{ Bootloader\t\t\t0xbc000000 0x00040000 }\n    firmware\t{ \"Kernel+rootfs\"\t\t0xbc040000 0x01fa0000 }\n    nvram\t{ \"Config space\"\t\t0xbdfe0000 0x00020000 }\n}\n\nsource [find target/bcm4706.cfg]\n\n# External 32MB NOR Flash (Spansion S29GL256P10TF101\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0xbc000000 0x02000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/at91cap7a-stk-sdram.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394\n#\n# use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config trst_and_srst srst_pulls_trst\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME cap7\n}\n\nif { [info exists ENDIAN] } {\n   set  _ENDIAN $ENDIAN\n} else {\n   set  _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x40700f0f\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-start {\n\t# start off real slow when we're running off internal RC oscillator\n\tadapter speed 32\n}\n\nproc peek32 {address} {\n\treturn [read_memory $address 32 1]\n}\n\n# Wait for an expression to be true with a timeout\nproc wait_state {expression} {\n\tfor {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {\n\t\tif {[uplevel 1 $expression] == 0} {\n\t\t\treturn\n\t\t}\n\t}\n\treturn -code 1 \"Timed out\"\n}\n\n# Use a global variable here to be able to tinker interactively with\n# post reset jtag frequency.\nglobal post_reset_khz\n# Danger!!!! Even 16MHz kinda works with this target, but\n# it needs to be as low as 2000kHz to be stable.\nset post_reset_khz 2000\n\n$_TARGETNAME configure -event reset-init {\n\techo \"Configuring master clock\"\n\t# disable watchdog\n\tmww 0xfffffd44 0xff008000\n\t# enable user reset\n\tmww 0xfffffd08 0xa5000001\n\t# Enable main oscillator\n\tmww 0xFFFFFc20  0x00000f01\n\twait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}\n\n\t# Set PLLA to 96MHz\n\tmww 0xFFFFFc28 0x20072801\n\twait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}\n\n\t# Select prescaler\n\tmww 0xFFFFFC30 0x00000004\n\twait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}\n\n\t# Select master clock to 48MHz\n\tmww 0xFFFFFC30 0x00000006\n\twait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}\n\n\techo \"Master clock ok.\"\n\n\t# Now that we're up and running, crank up speed!\n\tglobal post_reset_khz ;\tadapter speed $post_reset_khz\n\n\techo \"Configuring the SDRAM controller...\"\n\n\t# Configure EBI Chip select for SDRAM\n\tmww 0xFFFFEF30 0x00000102\n\n\t# Enable clock on EBI PIOs\n\tmww 0xFFFFFC10 0x00000004\n\n\t# Configure PIO for SDRAM\n\tmww 0xFFFFF470 0xFFFF0000\n\tmww 0xFFFFF474 0x00000000\n\tmww 0xFFFFF404 0xFFFF0000\n\n\t# Configure SDRAMC CR\n\tmww 0xFFFFEA08 0xA63392F9\n\n\t# NOP command\n\tmww 0xFFFFEA00 0x1\n\tmww 0x20000000 0\n\n\t# Precharge All Banks command\n\tmww 0xFFFFEA00 0x2\n\tmww 0x20000000 0\n\n\t# Set 1st CBR\n\tmww 0xFFFFEA00 0x00000004\n\tmww 0x20000010 0x00000001\n\n\t# Set 2nd CBR\n\tmww 0xFFFFEA00 0x00000004\n\tmww 0x20000020 0x00000002\n\n\t# Set 3rd CBR\n\tmww 0xFFFFEA00 0x00000004\n\tmww 0x20000030 0x00000003\n\n\t# Set 4th CBR\n\tmww 0xFFFFEA00 0x00000004\n\tmww 0x20000040 0x00000004\n\n\t# Set 5th CBR\n\tmww 0xFFFFEA00 0x00000004\n\tmww 0x20000050 0x00000005\n\n\t# Set 6th CBR\n\tmww 0xFFFFEA00 0x00000004\n\tmww 0x20000060 0x00000006\n\n\t# Set 7th CBR\n\tmww 0xFFFFEA00 0x00000004\n\tmww 0x20000070 0x00000007\n\n\t# Set 8th CBR\n\tmww 0xFFFFEA00 0x00000004\n\tmww 0x20000080 0x00000008\n\n\t# Set LMR operation\n\tmww 0xFFFFEA00 0x00000003\n\n\t# Perform LMR burst=1, lat=2\n\tmww 0x20000020 0xCAFEDEDE\n\n\t# Set Refresh Timer\n\tmww 0xFFFFEA04 0x00000203\n\n\t# Set Normal mode\n\tmww 0xFFFFEA00 0x00000000\n\tmww 0x20000000 0x00000000\n\n\t#remap internal memory at address 0x0\n\tmww 0xffffef00 0x3\n\n\techo \"SDRAM configuration ok.\"\n}\n\n$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0\n\narm7_9 dcc_downloads enable\narm7_9 fast_memory_access enable\n\n#set _FLASHNAME $_CHIPNAME.flash\n#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/at91eb40a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#Script for AT91EB40a\n\n# FIXME use some standard target config, maybe create one from this\n#\n#\tsource [find target/...cfg]\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME at91eb40a\n}\n\nif { [info exists ENDIAN] } {\n   set  _ENDIAN $ENDIAN\n} else {\n   set  _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x1f0f0f0f\n}\n\n\n#Atmel ties SRST & TRST together, at which point it makes\n#no sense to use TRST, but use TMS instead.\n#\n#The annoying thing with tying SRST & TRST together is that\n#there is no way to halt the CPU *before and during* the\n#SRST reset, which means that the CPU will run a number\n#of cycles before it can be halted(as much as milliseconds).\nreset_config srst_only srst_pulls_trst\n\n#jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n#target configuration\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# speed up memory downloads\narm7_9 fast_memory_access enable\narm7_9 dcc_downloads enable\n\n#flash driver\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x01000000 0x200000 2 2 $_TARGETNAME\n\n# required for usable performance. Used for lots of\n# other things than flash programming.\n$_TARGETNAME configure -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0\n\n$_TARGETNAME configure -event reset-init {\n\techo \"Running reset init script for AT91EB40A\"\n\t# Reset script for AT91EB40a\n\treg cpsr 0x000000D3\n\tmww 0xFFE00020 0x1\n\tmww 0xFFE00024 0x00000000\n\tmww 0xFFE00000 0x01002539\n\tmww 0xFFFFF124 0xFFFFFFFF\n\tmww 0xffff0010 0x100\n\tmww 0xffff0034 0x100\n}\n\n# This target is pretty snappy...\nadapter speed 16000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/at91rm9200-dk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# This is for the \"at91rm9200-DK\" (not the EK) eval board.\n#\n# The two are probably very simular.... I have DK...\n#\n# It has atmel at91rm9200 chip.\nsource [find target/at91rm9200.cfg]\n\nreset_config trst_and_srst\n\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }\n\n#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME\n\n\nproc at91rm9200_dk_init { } {\n    # Try to run at 1khz... Yea, that slow!\n    # Chip is really running @ 32khz\n    adapter speed 8\n\n    mww 0xfffffc64 0xffffffff\n    ##  disable all clocks but system clock\n    mww 0xfffffc04 0xfffffffe\n    ##  disable all clocks to pioa and piob\n    mww 0xfffffc14 0xffffffc3\n    ##  master clock = slow cpu = slow\n    ##  (means the CPU is running at 32khz!)\n    mww 0xfffffc30 0\n    ##  main osc enable\n    mww 0xfffffc20 0x0000ff01\n    ##  program pllA\n    mww 0xfffffc28 0x20263e04\n    ##  program pllB\n    mww 0xfffffc2c 0x10483e0e\n    ##  let pll settle... sleep 100msec\n    sleep 100\n    ##  switch to fast clock\n    mww 0xfffffc30 0x202\n    ## Sleep some - (go read)\n    sleep 100\n\n    #========================================\n    # CPU now runs at 180mhz\n    # SYS runs at 60mhz.\n    adapter speed 40000\n    #========================================\n\n\n    ##  set memc for all memories\n    mww 0xffffff60 0x02\n    ##  program smc controller\n    mww 0xffffff70 0x3284\n    ##  init sdram\n    mww 0xffffff98 0x7fffffd0\n    ##  all banks precharge\n    mww 0xffffff80 0x02\n    ##  touch sdram chip to make it work\n    mww 0x20000000 0\n    ##  sdram controller mode register\n    mww 0xffffff90 0x04\n    mww 0x20000000 0\n    mww 0x20000000 0\n    mww 0x20000000 0\n    mww 0x20000000 0\n    mww 0x20000000 0\n    mww 0x20000000 0\n    mww 0x20000000 0\n    mww 0x20000000 0\n    ##  sdram controller mode register\n    ##  Refresh, etc....\n    mww 0xffffff90 0x03\n    mww 0x20000080 0\n    mww 0xffffff94 0x1f4\n    mww 0x20000080 0\n    mww 0xffffff90 0x10\n    mww 0x20000000 0\n    mww 0xffffff00 0x01\n\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/at91rm9200-ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>\n#\n# under GPLv2 Only\n#\n# This is for the \"at91rm9200-ek\" eval board.\n#\n#\n# It has atmel at91rm9200 chip.\nsource [find target/at91rm9200.cfg]\n\nreset_config trst_and_srst\n\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { at91rm9200_ek_init }\n\n## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME\n\n# The chip may run @ 32khz, so set a really low JTAG speed\nadapter speed 8\n\nproc at91rm9200_ek_init { } {\n\t# Try to run at 1khz... Yea, that slow!\n\t# Chip is really running @ 32khz\n\tadapter speed 8\n\n\tmww 0xfffffc64 0xffffffff\n\t## disable all clocks but system clock\n\tmww 0xfffffc04 0xfffffffe\n\t## disable all clocks to pioa and piob\n\tmww 0xfffffc14 0xffffffc3\n\t## master clock = slow cpu = slow\n\t## (means the CPU is running at 32khz!)\n\tmww 0xfffffc30 0\n\t## main osc enable\n\tmww 0xfffffc20 0x0000ff01\n\t## MC_PUP\n\tmww 0xFFFFFF50 0x00000000\n\t## MC_PUER: Memory controller protection unit disable\n\tmww 0xFFFFFF54 0x00000000\n\t## EBI_CFGR\n\tmww 0xFFFFFF64 0x00000000\n\t## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS\n\tmww 0xFFFFFF70 0x00003284\n\n\t## Init Clocks\n\t## CKGR_PLLAR\n\tmww 0xFFFFFC28 0x2000BF05\n\t## PLLAR: 179,712000 MHz for PCK\n\tmww 0xFFFFFC28 0x20263E04\n\tsleep 100\n\t## PMC_MCKR\n\tmww 0xFFFFFC30 0x00000100\n\tsleep 100\n\t## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA\n\tmww 0xFFFFFC30 0x00000202\n\tsleep 100\n\n\t#========================================\n\t# CPU now runs at 180mhz\n\t# SYS runs at 60mhz.\n\tadapter speed 40000\n\t#========================================\n\n\t## Init SDRAM\n\t## PIOC_ASR: Configure PIOC as peripheral (D16/D31)\n\tmww 0xFFFFF870 0xFFFF0000\n\t## PIOC_BSR:\n\tmww 0xFFFFF874 0x00000000\n\t## PIOC_PDR:\n\tmww 0xFFFFF804 0xFFFF0000\n\t## EBI_CSA : CS1=SDRAM\n\tmww 0xFFFFFF60 0x00000002\n\t## EBI_CFGR:\n\tmww 0xFFFFFF64 0x00000000\n\t## SDRC_CR :\n\tmww 0xFFFFFF98 0x2188c155\n\t## SDRC_MR : Precharge All\n\tmww 0xFFFFFF90 0x00000002\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## SDRC_MR : Refresh\n\tmww 0xFFFFFF90 0x00000004\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## SDRC_MR : Load Mode Register\n\tmww 0xFFFFFF90 0x00000003\n\t## access SDRAM\n\tmww 0x20000080 0x00000000\n\t## SDRC_TR : Write refresh rate\n\tmww 0xFFFFFF94 0x000002E0\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n\t## SDRC_MR : Normal Mode\n\tmww 0xFFFFFF90 0x00000000\n\t## access SDRAM\n\tmww 0x20000000 0x00000000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/at91sam9261-ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Atmel AT91SAM9261-EK eval board\n################################################################################\n\nsource [find mem_helper.tcl]\nsource [find target/at91sam9261.cfg]\nuplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]\n\n# By default S1 is open and this means that NTRST is not connected.\n# The reset_config in target/at91sam9261.cfg is overridden here.\n# (or S1 must be populated with a 0 Ohm resistor)\nreset_config srst_only\n\nscan_chain\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }\n$_TARGETNAME configure -event reset-start { at91sam9_reset_start }\n\nproc at91sam9261ek_reset_init { } {\n\n\t;# for ppla at 199 Mhz\n\tset config(master_pll_div)\t15\n\tset config(master_pll_mul)\t162\n\n\t;# for ppla at 239 Mhz\n\t;# set master_pll_div\t1\n\t;# set master_pll_mul\t13\n\n\tset val\t$::AT91_WDT_WDV\t\t\t\t\t\t\t;# Counter Value\n\tset val\t[expr {$val | $::AT91_WDT_WDDIS}]\t\t;# Watchdog Disable\n\tset val\t[expr {$val | $::AT91_WDT_WDD}]\t\t\t;# Delta Value\n\tset val\t[expr {$val | $::AT91_WDT_WDDBGHLT}]\t;# Debug Halt\n\tset val\t[expr {$val | $::AT91_WDT_WDIDLEHLT}]\t;# Idle Halt\n\n\tset config(wdt_mr_val) $val\n\n\t;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash\n\tset config(matrix_ebicsa_addr)\t$::AT91_MATRIX_EBICSA\n\tset config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]\n\n\t;# SDRAMC_CR - Configuration register\n\tset val $::AT91_SDRAMC_NC_9\n\tset val [expr {$val | $::AT91_SDRAMC_NR_13}]\n\tset val [expr {$val | $::AT91_SDRAMC_NB_4}]\n\tset val [expr {$val | $::AT91_SDRAMC_CAS_3}]\n\tset val [expr {$val | $::AT91_SDRAMC_DBW_32}]\n\tset val [expr {$val | (2 <<  8)}]\t\t;# Write Recovery Delay\n\tset val [expr {$val | (7 << 12)}]\t\t;# Row Cycle Delay\n\tset val [expr {$val | (3 << 16)}]\t\t;# Row Precharge Delay\n\tset val [expr {$val | (2 << 20)}]\t\t;# Row to Column Delay\n\tset val [expr {$val | (5 << 24)}]\t\t;# Active to Precharge Delay\n\tset val [expr {$val | (8 << 28)}]\t\t;# Exit Self Refresh to Active Delay\n\n\tset config(sdram_cr_val) $val\n\n\tset config(sdram_tr_val) 0x13c\n\n\tset config(sdram_base) $::AT91_CHIPSELECT_1\n\tat91sam9_reset_init $config\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/at91sam9263-ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Atmel AT91SAM9263-EK eval board\n################################################################################\n\nsource [find mem_helper.tcl]\nsource [find target/at91sam9263.cfg]\nuplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]\n\n# By default S1 is open and this means that NTRST is not connected.\n# The reset_config in target/at91sam9263.cfg is overridden here.\n# (or S1 must be populated with a 0 Ohm resistor)\nreset_config srst_only\n\nscan_chain\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }\n$_TARGETNAME configure -event reset-start { at91sam9_reset_start }\n\nproc at91sam9263ek_reset_init { } {\n\n\tset config(master_pll_div)\t14\n\tset config(master_pll_mul)\t171\n\n\tset val\t$::AT91_WDT_WDV\t\t\t\t\t\t\t;# Counter Value\n\tset val\t[expr {$val | $::AT91_WDT_WDDIS}]\t\t;# Watchdog Disable\n\tset val\t[expr {$val | $::AT91_WDT_WDD}]\t\t\t;# Delta Value\n\tset val\t[expr {$val | $::AT91_WDT_WDDBGHLT}]\t;# Debug Halt\n\tset val\t[expr {$val | $::AT91_WDT_WDIDLEHLT}]\t;# Idle Halt\n\n\tset config(wdt_mr_val) $val\n\n\tset config(sdram_piod) 1\n\t;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash\n\tset config(matrix_ebicsa_addr)\t$::AT91_MATRIX_EBI0CSA\n\n\tset val\t$::AT91_MATRIX_EBI0_DBPUC\n\tset val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}]\n\tset val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}]\n\tset config(matrix_ebicsa_val) $val\n\n\t;# SDRAMC_CR - Configuration register\n\tset val $::AT91_SDRAMC_NC_9\n\tset val [expr {$val | $::AT91_SDRAMC_NR_13}]\n\tset val [expr {$val | $::AT91_SDRAMC_NB_4}]\n\tset val [expr {$val | $::AT91_SDRAMC_CAS_3}]\n\tset val [expr {$val | $::AT91_SDRAMC_DBW_32}]\n\tset val [expr {$val | (1 <<  8)}]\t\t;# Write Recovery Delay\n\tset val [expr {$val | (7 << 12)}]\t\t;# Row Cycle Delay\n\tset val [expr {$val | (2 << 16)}]\t\t;# Row Precharge Delay\n\tset val [expr {$val | (2 << 20)}]\t\t;# Row to Column Delay\n\tset val [expr {$val | (5 << 24)}]\t\t;# Active to Precharge Delay\n\tset val [expr {$val | (1 << 28)}]\t\t;# Exit Self Refresh to Active Delay\n\n\tset config(sdram_cr_val) $val\n\n\tset config(sdram_tr_val) 0x13c\n\n\tset config(sdram_base) $::AT91_CHIPSELECT_1\n\tat91sam9_reset_init $config\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/at91sam9g20-ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#################################################################################################\n#\t\t\t\t\t\t\t\t\t\t\t\t#\n# Author: Gary Carlson (gcarlson@carlson-minot.com)\t\t\t\t\t\t#\n# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8.\t#\n#\t\t\t\t\t\t\t\t\t\t\t\t#\n#################################################################################################\n\nsource [find target/at91sam9g20.cfg]\n\nset _FLASHTYPE nandflash_cs3\n\n# Set reset type.  Note that the AT91SAM9G20-EK board has the trst signal disconnected.  Therefore\n# the reset needs to be configured for \"srst_only\".  If for some reason, a zero-ohm jumper is\n# added to the board to connect the trst signal, then this parameter may need to be changed.\n\nreset_config srst_only\n\nadapter srst delay 200\njtag_ntrst_delay 200\n\n# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the\n# AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has\n# some powerful features, we want to have a special function that handles \"reset init\".  To do this we declare\n# an event handler where these special activities can take place.\n\nscan_chain\n$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}\n$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}\n\n# NandFlash configuration and definition\n\nnand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800\nat91sam9 cle 0 22\nat91sam9 ale 0 21\nat91sam9 rdy_busy 0 0xfffff800 13\nat91sam9 ce 0 0xfffff800 14\n\nproc read_register {register} {\n\treturn [read_memory $register 32 1]\n}\n\nproc at91sam9g20_reset_start { } {\n\n\t# Make sure that the the jtag is running slow, since there are a number of different ways the board\n\t# can be configured coming into this state that can cause communication problems with the jtag\n\t# adapter.  Also since this call can be made following a \"reset init\" where fast memory accesses\n\t# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower\n\t# jtag speed without causing GDB keep alive problem.\n\n\tarm7_9 fast_memory_access disable\n\tadapter speed 2                 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.\n\thalt                            ;# Make sure processor is halted, or error will result in following steps.\n\twait_halt 10000\n\tmww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.\n}\n\nproc at91sam9g20_reset_init { } {\n\n\t# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires\n\t# a number of steps that must be carefully performed.  The process outline below follows the\n\t# recommended procedure outlined in the AT91SAM9G20 technical manual.\n\t#\n\t# Several key and very important things to keep in mind:\n\t# The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This\n\t# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor\n\t# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.\n\n\tmww 0xfffffd44 0x00008000\t;# WDT_MR : disable watchdog.\n\n\t# Enable the main 18.432 MHz oscillator in CKGR_MOR register.\n\t# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.\n\n\tmww 0xfffffc20 0x00004001\n\twhile { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }\n\n\t# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).\n\t# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.\n\n\tmww 0xfffffc28 0x202a3f01\n\twhile { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }\n\n\t# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.\n\t# Wait for MCKRDY signal from PMC_SR to assert.\n\n\tmww 0xfffffc30 0x00000101\n\twhile { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }\n\n\t# Now change PMC_MCKR register to select PLLA.\n\t# Wait for MCKRDY signal from PMC_SR to assert.\n\n\tmww 0xfffffc30 0x00001302\n\twhile { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }\n\n\t# Processor and master clocks are now operating and stable at maximum frequency possible:\n\t#\t-> MCLK = 132.096 MHz\n\t#\t-> PCLK = 396.288 MHz\n\n\t# Switch over to adaptive clocking.\n\n\tadapter speed 0\n\n\t# Enable faster DCC downloads and memory accesses.\n\n\tarm7_9 dcc_downloads enable\n\tarm7_9 fast_memory_access enable\n\n\t# To be able to use external SDRAM, several peripheral configuration registers must\n\t# be modified.  The first change is made to PIO_ASR to select peripheral functions\n\t# for D15 through D31.  The second change is made to the PIO_PDR register to disable\n\t# this for D15 through D31.\n\n\tmww 0xfffff870 0xffff0000\n\tmww 0xfffff804 0xffff0000\n\n\t# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller\n\t# using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on\n\t# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.\n\n\tmww 0xffffef1c 0x000100a\n\n\t# The AT91SAM9G20-EK evaluation board has built-in NandFlash.  The exact physical timing characteristics\n\t# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting\n\t# a number of registers.  The first step involves setting up the general I/O pins on the processor\n\t# to be able to interface and support the external memory.\n\n\tmww 0xfffffc10 0x00000010\t;# PMC_PCER : enable PIOC clock\n\tmww 0xfffff800 0x00006000\t;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)\n\tmww 0xfffff810 0x00004000\t;# PIOC_OER : enable output on 14\n\tmww 0xfffff814 0x00002000\t;# PIOC_ODR : disable output on 13\n    \tmww 0xfffff830 0x00004000\t;# PIOC_SODR : set 14 to disable NAND\n\n\t# The exact physical timing characteristics for the memory type used on the current board\n\t# (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,\n\t# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers\n\t# is a little tedious to do here.  If you have questions about how to do this, Atmel has\n\t# a decent application note #6255B that covers this process.\n\n\tmww 0xffffec30 0x00020002\t;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE\n\tmww 0xffffec34 0x04040404\t;# SMC_PULSE3 : 4 clock cycle pulse for all signals\n\tmww 0xffffec38 0x00070006\t;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle\n\tmww 0xffffec3C 0x00020003\t;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,\n\n\tmww 0xffffe800 0x00000001\t;# ECC_CR : reset the ECC parity registers\n\tmww 0xffffe804 0x00000002\t;# ECC_MR : page size is 2112 words (word is 8 bits)\n\n\t# Identify NandFlash bank 0.\n\n\tnand probe nandflash_cs3\n\n\t# The AT91SAM9G20-EK evaluation board has built-in serial data flash also.\n\n\t# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations\n\t# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference\n\t# for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted\n\t# into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock\n\t# of 132.096 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:\n\t#\n\t#\tCAS latency = 3 cycles\n\t#\tTXSR = 10 cycles\n\t#\tTRAS = 6 cycles\n\t#\tTRCD = 3 cycles\n\t#\tTRP = 3 cycles\n\t#\tTRC = 9 cycles\n\t#\tTWR = 2 cycles\n\t#\t9 column, 13 row, 4 banks\n\t#\trefresh equal to or less then 7.8 us for commercial/industrial rated devices\n\t#\n\t#\tThus SDRAM_CR = 0xa6339279\n\n\tmww 0xffffea08 0xa6339279\n\n\t# Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into\n\t# the starting memory location for the SDRAM.\n\n\tmww 0xffffea00 0x00000001\n\tmww 0x20000000 0\n\n\t# Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero\n\t# value into the starting memory location for the SDRAM.\n\n\tmww 0xffffea00 0x00000002\n\tmww 0x20000000 0\n\n\t# Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing\n\t# zero values eight times into the starting memory location for the SDRAM.\n\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\n\t# Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the\n\t# the starting memory location for the SDRAM.\n\n\tmww 0xffffea00 0x3\n\tmww 0x20000000 0\n\n\t# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting\n\t# memory location for the SDRAM.\n\n\tmww 0xffffea00 0x0\n\tmww 0x20000000 0\n\n\t# Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).\n\n\tmww 0xffffea04 0x0000039c\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_at91sam7s-ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Atmel AT91SAM7S-EK\n# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784\n\nset CHIPNAME at91sam7s256\n\nsource [find target/at91sam7sx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_at91sam9260-ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Atmel AT91SAM9260-EK eval board\n#\n# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933\n#\n# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz\n#                     OSCSEL configured for external 32.768 kHz crystal\n#\n# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks\n#\n################################################################################\n\n# We add to the minimal configuration.\nsource [find target/at91sam9260.cfg]\n\n# By default S1 is open and this means that NTRST is not connected.\n# The reset_config in target/at91sam9260.cfg is overridden here.\n# (or S1 must be populated with a 0 Ohm resistor)\nreset_config srst_only\n\n$_TARGETNAME configure -event reset-start {\n        # At reset CPU runs at 32.768 kHz.\n        # JTAG Frequency must be 6 times slower if RCLK is not supported.\n        jtag_rclk 5\n        halt\n        # RSTC_MR : enable user reset, MMU may be enabled... use physical address\n        mww phys 0xfffffd08 0xa5000501\n}\n\n$_TARGETNAME configure -event reset-init {\n        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog\n\n\tmww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator\n        sleep 20                          ;# wait 20 ms\n        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator\n        sleep 10                          ;# wait 10 ms\n        mww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz\n        sleep 20                          ;# wait 20 ms\n        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)\n        sleep 10                          ;# wait 10 ms\n        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)\n        sleep 10                          ;# wait 10 ms\n\n\t# Increase JTAG Speed to 6 MHz if RCLK is not supported\n        jtag_rclk 6000\n\n\tarm7_9 dcc_downloads enable       ;# Enable faster DCC downloads\n\n\tmww 0xfffff870 0xffff0000         ;# PIO_ASR  : Select peripheral function for D15..D31\n        mww 0xfffff804 0xffff0000         ;# PIO_PDR  : Disable PIO function for D15..D31\n\n        mww 0xffffef1c 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory\n\n\tmww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)\n\n\tmww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode\n\tmww 0x20000000 0\n\tmww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_at91sam9rl-ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n#\n# Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6\n#\n# Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz\n#                     OSCSEL configured for external 32.768 kHz crystal\n#\n# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks\n#\n################################################################################\n\n# We add to the minimal configuration.\nsource [find target/at91sam9rl.cfg]\n\n$_TARGETNAME configure -event reset-start {\n        # At reset CPU runs at 32.768 kHz.\n        # JTAG Frequency must be 6 times slower if RCLK is not supported.\n        jtag_rclk 5\n        halt\n        # RSTC_MR : enable user reset, MMU may be enabled... use physical address\n        mww phys 0xfffffd08 0xa5000501\n}\n\n$_TARGETNAME configure -event reset-init {\n        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog\n\n\tmww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator\n        sleep 20                          ;# wait 20 ms\n        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator\n        sleep 10                          ;# wait 10 ms\n        mww 0xfffffc28 0x2031bf03         ;# CKGR_PLLR: Set PLL Register for 200 MHz\n        sleep 20                          ;# wait 20 ms\n        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)\n        sleep 10                          ;# wait 10 ms\n        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLL is selected (100 MHz)\n        sleep 10                          ;# wait 10 ms\n\n\t# Increase JTAG Speed to 6 MHz if RCLK is not supported\n        jtag_rclk 6000\n\n\tarm7_9 dcc_downloads enable       ;# Enable faster DCC downloads\n\n\tmww 0xfffff670 0xffff0000         ;# PIO_ASR  : Select peripheral function for D16..D31 (PIOB)\n        mww 0xfffff604 0xffff0000         ;# PIO_PDR  : Disable PIO function for D16..D31 (PIOB)\n\n        mww 0xffffef20 0x00010002         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory\n\n\tmww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)\n\n\tmww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode\n\tmww 0x20000000 0\n\tmww 0xffffea04 0x2b6              ;# SDRAMC_TR : Set refresh timer count to 7us\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_sam3n_ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Board configuration for Atmel's SAM3N-EK\n#\n\nreset_config srst_only\n\nset CHIPNAME at91sam3n4c\n\nadapter speed 32\n\nsource [find target/at91sam3nXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_sam3s_ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/at91sam3sXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_sam3u_ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/at91sam3u4e.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_sam3x_ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/at91sam3ax_8x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_sam4e_ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an SAM4E-EK board with a single SAM4E16 chip.\n# http://www.atmel.com/tools/sam4e-ek.aspx\n\n# chip name\nset CHIPNAME SAM4E16E\n\nsource [find target/at91sam4sXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_sam4l8_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAM4L8 Xplained Pro evaluation kit.\n# http://www.atmel.com/tools/ATSAM4L8-XPRO.aspx\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME ATSAM4LC8CA\n\nsource [find target/at91sam4lXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_sam4s_ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/at91sam4sXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_sam4s_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAM4S Xplained Pro evaluation kit.\n# http://www.atmel.com/tools/ATSAM4S-XPRO.aspx\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME ATSAM4SD32C\n\nsource [find target/at91sam4sd32x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samc20_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMC20 Xplained Pro evaluation kit.\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME at91samc20j18\n\nsource [find target/at91samdXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samc21_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMC21 Xplained Pro evaluation kit.\n# http://www.atmel.com/tools/ATSAMC21-XPRO.aspx\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME at91samc21j18\n\nsource [find target/at91samdXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samd10_xplained_mini.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMD10 Xplained mini evaluation kit.\n# http://www.atmel.com/tools/atsamd10-xmini.aspx\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME at91samd10d14\n\nsource [find target/at91samdXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samd11_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMD11 Xplained Pro evaluation kit.\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME at91samd11d14\n\nsource [find target/at91samdXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samd20_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMD20 Xplained Pro evaluation kit.\n# http://www.atmel.com/tools/ATSAMD20-XPRO.aspx\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME at91samd20j18\n\nsource [find target/at91samdXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samd21_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMD21 Xplained Pro evaluation kit.\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME at91samd21j18\n\nsource [find target/at91samdXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_same70_xplained.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAME70 Xplained evaluation kit.\n# http://www.atmel.com/tools/ATSAME70-XPLD.aspx\n#\n# Connect using the EDBG chip on the dev kit over USB\nsource [find interface/cmsis-dap.cfg]\n\nset CHIPNAME atsame70q21\n\nsource [find target/atsamv.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samg53_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMG53 Xplained Pro evaluation kit.\n# http://www.atmel.com/tools/ATSAMG53-XPRO.aspx\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME ATSAMG53N19\n\nsource [find target/at91samg5x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samg55_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMG55 Xplained Pro evaluation kit.\n# http://www.atmel.com/tools/ATSAMG55-XPRO.aspx\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME ATSAMG55J19\n\nsource [find target/at91samg5x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_saml21_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAML21 Xplained Pro evaluation kit.\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME at91saml21j18\n\nsource [find target/at91samdXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samr21_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMR21 Xplained Pro evaluation kit.\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# chip name\nset CHIPNAME at91samr21g18\n\nsource [find target/at91samdXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/atmel_samv71_xplained_ultra.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Atmel SAMV71 Xplained Ultra evaluation kit.\n# http://www.atmel.com/tools/ATSAMV71-XULT.aspx\n#\n# To connect using the EDBG chip on the dev kit over USB, you will\n# first need to source [find interface/cmsis-dap.cfg]\n# however, since this board also has a SWD+ETM connector, we don't\n# automatically source that file here.\n\nset CHIPNAME samv71\n\nsource [find target/atsamv.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/avnet_ultrazed-eg.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# AVNET UltraZED EG StarterKit\n# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2\n#\nsource [find interface/ftdi/digilent_jtag_smt2_nc.cfg]\n# jtag transport only\ntransport select jtag\n# reset lines are not wired\nreset_config none\n\n# slow default clock\nadapter speed 1000\n\nset CHIPNAME uscale\n\nsource [find target/xilinx_zynqmp.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/balloon3-cpu.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/\n# The board has separate JTAG ports for cpu and CPLD/FPGA devices\n# Chaining is done on IO interfaces if desired.\n\nsource [find target/pxa270.cfg]\n\n# The board supports separate reset lines\n# Override this in the interface config for parallel dongles\nreset_config trst_and_srst separate\n\n# flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>\n# 29LV650 64Mbit Flash\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/bcm28155_ap.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# BCM28155_AP\n\nadapter speed 20000\n\nset CHIPNAME bcm28155\nsource [find target/bcm281xx.cfg]\n\nreset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/bemicro_cycloneiii.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# BeMicro Cyclone III\n\n\nadapter driver ftdi\nftdi channel 0\nftdi layout_init 0x0008 0x008b\nftdi vid_pid 0x0403 0xa4a0\nreset_config none\ntransport select jtag\n\nadapter speed 10000\n\nsource [find fpga/altera-cycloneiii.cfg]\n\n#quartus_cpf --option=bitstream_compression=off -c output_files\\cycloneiii_blinker.sof cycloneiii_blinker.rbf\n\n#openocd -f board/bemicro_cycloneiii.cfg -c \"init\" -c \"pld load 0 cycloneiii_blinker.rbf\"\n# \"ipdbg -start -tap cycloneiii.tap -hub 0x00e -tool 0 -port 5555\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/bluefield.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Board configuration for BlueField SoC.\n#\n\nsource [find interface/rshim.cfg]\nsource [find target/bluefield.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/bt-homehubv1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# BT HomeHub v1\n#\n\nset partition_list {\n    CFE       { Bootloader              0xbe400000 0x00020000 }\n    firmware  { \"Kernel+rootfs\"         0xbe420000 0x007d0000 }\n    fisdir    { \"FIS Directory\"         0xbebf0000 0x0000f000 }\n    nvram     { \"Config space\"          0xbebff000 0x00001000 }\n}\n\nsource [find target/bcm6348.cfg]\n\nset _FLASHNAME $_CHIPNAME.norflash\nflash bank $_FLASHNAME cfi 0xbe400000 0x00800000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/calao-usb-a9260.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# CALAO Systems USB-A9260 (C01 and C02)\n\nadapter driver ftdi\nftdi device_desc \"USB-A9260\"\nftdi vid_pid 0x0403 0x6001 0x0403 0x6010\nftdi layout_init 0x0c08 0x0f1b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\n\ntransport select jtag\n\nsource [find target/at91sam9260.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/calao-usb-a9g20-c01.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# CALAO Systems USB-A9G20-C01\n# Authors: Gregory Hermant, Jean-Christophe PLAGNIOL-VILLARD, Wolfram Sang\n\nadapter driver ftdi\nftdi device_desc \"USB-A9G20\"\nftdi vid_pid 0x0403 0x6010\nftdi layout_init 0x0c08 0x0f1b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\n\ntransport select jtag\n\nsource [find target/at91sam9g20.cfg]\nsource [find mem_helper.tcl]\n\nproc at91sam9g20_reset_start { } {\n\n        # Make sure that the jtag is running slow, since there are a number of different ways the board\n        # can be configured coming into this state that can cause communication problems with the jtag\n        # adapter.  Also since this call can be made following a \"reset init\" where fast memory accesses\n        # are enabled, Need to temporarily shut this down so that the RSTC_MR register can be written at slower\n        # jtag speed without causing GDB keep alive problem.\n\n        arm7_9 fast_memory_access disable\n        adapter speed 2                   ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.\n        halt 0                            ;# Make sure processor is halted, or error will result in following steps.\n        wait_halt 10000\n        # RSTC_MR : enable user reset, MMU may be enabled... use physical address\n        mww phys 0xfffffd08 0xa5000501\n}\n\nproc at91sam9g20_reset_init { } {\n\n        # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires\n        # a number of steps that must be carefully performed.  The process outline below follows the\n        # recommended procedure outlined in the AT91SAM9G20 technical manual.\n        #\n        # Several key and very important things to keep in mind:\n        # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This\n        # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor\n        # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.\n\n        mww 0xfffffd44 0x00008000      ;# WDT_MR : disable watchdog.\n\n        # Set oscillator bypass bit (12.00 MHz external oscillator) in CKGR_MOR register.\n\n        mww 0xfffffc20 0x00000002\n\n        # Set PLLA Register for 798.000 MHz (divider: bypass, multiplier: 132).\n        # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.\n\n        mww 0xfffffc28 0x20843F02\n        while { [expr { [mrw 0xfffffc68] & 0x02 } ] != 2 } { sleep 1 }\n\n        # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.\n        # Wait for MCKRDY signal from PMC_SR to assert.\n\n        mww 0xfffffc30 0x00001300\n        while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }\n\n        # Now change PMC_MCKR register to select PLLA.\n        # Wait for MCKRDY signal from PMC_SR to assert.\n\n        mww 0xfffffc30 0x00001302\n        while { [expr { [mrw 0xfffffc68] & 0x08 } ] != 8 } { sleep 1 }\n\n        # Processor and master clocks are now operating and stable at maximum frequency possible:\n        #       -> MCLK = 133.000 MHz\n        #       -> PCLK = 400.000 MHz\n\n        # Switch to fast JTAG speed\n\n        adapter speed 9500\n\n        # Enable faster DCC downloads.\n\n        arm7_9 dcc_downloads enable\n        arm7_9 fast_memory_access enable\n\n        # To be able to use external SDRAM, several peripheral configuration registers must\n        # be modified.  The first change is made to PIO_ASR to select peripheral functions\n        # for D15 through D31.  The second change is made to the PIO_PDR register to disable\n        # this for D15 through D31.\n\n        mww 0xfffff870 0xffff0000\n        mww 0xfffff804 0xffff0000\n\n        # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller\n        # using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on\n        # the board to the 1.8V VDC power supply so set the appropriate register bit to notify the micrcontroller.\n\n        mww 0xffffef1c 0x000000a\n\n        # The USB-A9G20 Embedded computer has built-in NandFlash.  The exact physical timing characteristics\n        # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting\n        # four registers in order:  SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.\n\n        mww 0xffffec30 0x00020002\n        mww 0xffffec34 0x04040404\n        mww 0xffffec38 0x00070007\n        mww 0xffffec3c 0x00030003\n\n        # Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations\n        # are based on 2 x Micron LPSDRAM MT48H16M16LFBF-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference\n        # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted\n        # into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock\n        # of 133.000 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:\n        #\n        #       CAS latency = 3 cycles\n        #       TXSR = 10 cycles\n        #       TRAS = 6 cycles\n        #       TRCD = 3 cycles\n        #       TRP = 3 cycles\n        #       TRC = 9 cycles\n        #       TWR = 2 cycles\n        #       9 column, 13 row, 4 banks\n        #       refresh equal to or less then 7.8 us for commercial/industrial rated devices\n        #\n        #       Thus SDRAM_CR = 0xa6339279\n\n        mww 0xffffea08 0xa6339279\n\n        # Memory Device Type: SDRAM (low-power would be 0x1)\n        mww 0xffffea24 0x00000000\n\n        # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into\n        # the starting memory location for the SDRAM.\n\n        mww 0xffffea00 0x00000001\n        mww 0x20000000 0\n\n        # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero\n        # value into the starting memory location for the SDRAM.\n\n        mww 0xffffea00 0x00000002\n        mww 0x20000000 0\n\n        # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing\n        # zero values eight times into the starting memory location for the SDRAM.\n\n        mww 0xffffea00 0x4\n        mww 0x20000000 0\n        mww 0x20000000 0\n        mww 0x20000000 0\n        mww 0x20000000 0\n        mww 0x20000000 0\n        mww 0x20000000 0\n        mww 0x20000000 0\n        mww 0x20000000 0\n\n        # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the\n        # the starting memory location for the SDRAM.\n\n        mww 0xffffea00 0x3\n        mww 0x20000000 0\n\n        # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the starting\n        # memory location for the SDRAM.\n\n        mww 0xffffea00 0x0\n        mww 0x20000000 0\n\n        # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).\n\n        mww 0xffffea04 0x0000039c\n}\n\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}\n$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/certuspro_evaluation.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# https://www.latticesemi.com/products/developmentboardsandkits/certuspro-nx-versa-board\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n\nftdi channel 0\nftdi layout_init 0x0008 0x008b\nreset_config none\ntransport select jtag\nadapter speed 10000\n\nsource [find fpga/lattice_certuspro.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/colibri.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Toradex Colibri PXA270\nsource [find target/pxa270.cfg]\nreset_config trst_and_srst srst_push_pull\nadapter srst pulse_width 40\n\n# CS0 -- one bank of CFI flash, 32 MBytes\n# the bank is 32-bits wide, two 16-bit chips in parallel\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/crossbow_tech_imote2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Crossbow Technology iMote2\n\nset  CHIPNAME imote2\nsource [find target/pxa270.cfg]\n\n# longer-than-normal reset delay\nadapter srst delay 800\n\nreset_config trst_and_srst separate\n\n# works for P30 flash\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/csb337.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Cogent CSB337\n#   http://cogcomp.com/csb_csb337.htm\n\nsource [find target/at91rm9200.cfg]\n\n# boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME\n\n# ETM9 trace port connector present on this board, 16 data pins.\nif { [info exists ETM_DRIVER] } {\n\tetm config $_TARGETNAME 16 normal half $ETM_DRIVER\n\t# OpenOCD may someday support a real trace port driver...\n\t# system config file would need to configure it.\n} else {\n\tetm config $_TARGETNAME 16 normal half dummy\n\tetm_dummy config $_TARGETNAME\n}\n\nproc csb337_clk_init { } {\n\t# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock\n\tadapter speed 8\n\n\t# CKGR_MOR:  start main oscillator (3.6864 MHz)\n\tmww 0xfffffc20 0xff01\n\tsleep 10\n\n\t# CKGR_PLLAR:  start PLL A for CPU and peripherals (184.32 MHz)\n\tmww 0xfffffc28 0x20313e01\n\t# CKGR_PLLBR:  start PLL B for USB timing (96 MHz, with div2)\n\tmww 0xfffffc2c 0x12703e18\n\t# let PLLs lock\n\tsleep 10\n\n\t# PMC_MCKR:  switch to CPU clock = PLLA, master clock = CPU/4\n\tmww 0xfffffc30 0x0302\n\tsleep 20\n\n\t# CPU is in Normal Mode ... allows faster JTAG clock speed\n\tadapter speed 40000\n}\n\nproc csb337_nor_init { } {\n\t# SMC_CSR0:  adjust timings (10 wait states)\n\tmww 0xffffff70 0x1100318a\n\n\tflash probe 0\n}\n\nproc csb337_sdram_init { } {\n\t# enable PIOC clock\n\tmww 0xfffffc10 0x0010\n\t# PC31..PC16 are D31..D16, with internal pullups like D15..D0\n\tmww 0xfffff870 0xffff0000\n\tmww 0xfffff874 0x0\n\tmww 0xfffff804 0xffff0000\n\n\t# SDRC_CR: set timings\n\tmww 0xffffff98 0x2188b0d5\n\n\t# SDRC_MR: issue all banks precharge to SDRAM\n\tmww 0xffffff90 2\n\tmww 0x20000000 0\n\n\t# SDRC_MR: 8 autorefresh cycles\n\tmww 0xffffff90 4\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\tmww 0x20000000 0\n\n\t# SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)\n\tmww 0xffffff90 3\n\tmww 0x20000080 0\n\n\t# SDRC_TR: set refresh rate\n\tmww 0xffffff94 0x200\n\tmww 0x20000000 0\n\n\t# SDRC_MR: normal mode, 32 bit bus\n\tmww 0xffffff90 0\n\tmww 0x20000000 0\n}\n\n# The rm9200 chip has just been reset.  Bring it up far enough\n# that we can write flash or run code from SDRAM.\nproc csb337_reset_init { } {\n\tcsb337_clk_init\n\n\t# EBI_CSA:  CS0 = NOR, CS1 = SDRAM\n\tmww 0xffffff60 0x02\n\n\tcsb337_nor_init\n\tcsb337_sdram_init\n\n\t# Update CP15 control register ... we don't seem to be able to\n\t# read/modify/write its value through a TCL variable, so just\n\t# write it.  Fields are zero unless listed here ... and note\n\t# that OpenOCD numbers this register \"2\", not \"1\" (!).\n\t#\n\t#  - Core to use Async Clocking mode (so it uses 184 MHz most\n\t#    of the time instead of limiting to the master clock rate):\n\t#\tiA(31) = 1, nF(30) = 1\n\t#  - Icache on (it's disabled now, slowing i-fetches)\n\t#\tI(12) = 1\n\t#  - Reserved/ones\n\t#\t6:3 = 1\n\tarm920t cp15 2 0xc0001078\n}\n\n$_TARGETNAME configure -event reset-init {csb337_reset_init}\n\narm7_9 fast_memory_access enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/csb732.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The Cogent CSB732 board has a single i.MX35 chip\nsource [find target/imx35.cfg]\n\n# Determined by trial and error\nreset_config trst_and_srst combined\nadapter srst delay 200\njtag_ntrst_delay 200\n\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { csb732_init }\n\n# Bare-bones initialization of core clocks and SDRAM\nproc csb732_init { } {\n\n\t# Disable fast writing only for init\n\tmemwrite burst disable\n\n\t# All delay loops are omitted.\n\t# We assume the interpreter latency is enough.\n\n\t# Allow access to all coprocessors\n\tarm mcr 15 0 15 1 0 0x2001\n\n\t# Disable MMU, caches, write buffer\n\tarm mcr 15 0 1 0 0 0x78\n\n\t# Grant manager access to all domains\n\tarm mcr 15 0 3 0 0 0xFFFFFFFF\n\n\t# Set ARM clock to 532 MHz, AHB to 133 MHz\n\tmww 0x53F80004 0x1000\n\n\t# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz\n\tmww 0x53F8001C 0xB2C01\n\n\tset ESDMISC 0xB8001010\n\tset ESDCFG0 0xB8001004\n\tset ESDCTL0 0xB8001000\n\n\t# Enable DDR\n\tmww $ESDMISC 0x4\n\n\t# Timing\n\tmww $ESDCFG0 0x007fff3f\n\n\t# CS0\n\tmww $ESDCTL0 0x92120080\n\n\t# Precharge all dummy write\n\tmww 0x80000400 0\n\n\t# Enable CS) auto-refresh\n\tmww $ESDCTL0 0xA2120080\n\n\t# Refresh twice (dummy writes)\n\tmww 0x80000000 0\n\tmww 0x80000000 0\n\n\t# Enable CS0 load mode register\n\tmww $ESDCTL0 0xB2120080\n\n\t# Dummy writes\n\tmwb 0x80000033 0x01\n\tmwb 0x81000000 0x01\n\n\tmww $ESDCTL0 0x82226080\n\tmww 0x80000000 0\n\n\t# Re-enable fast writing\n\tmemwrite burst enable\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/da850evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#DA850 EVM board\n# http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939\n# http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit\n\nsource [find target/omapl138.cfg]\n\nreset_config trst_and_srst separate\n\n#currently any pinmux/timing must be setup by UBL before openocd can do debug\n#TODO: implement pinmux/timing on reset like in board/dm365evm.cfg\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/digi_connectcore_wi-9c.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target: DIGI ConnectCore Wi-9C\n######################################\n\nreset_config trst_and_srst\n\n# FIXME use some standard target config, maybe create one from this\n#\n#\tsource [find target/...cfg]\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME ns9360\n}\n\nif { [info exists ENDIAN] } {\n   set  _ENDIAN $ENDIAN\n} else {\n  # This config file was defaulting to big endian..\n   set  _ENDIAN big\n}\n\n\n# What's a good fallback frequency for this board if RCLK is\n# not available??\njtag_rclk 1000\n\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07926031\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nadapter srst delay 200\njtag_ntrst_delay 0\n\n\n######################\n# Target configuration\n######################\n\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-init {\n\tmww 0x90600104 0x33313333\n\tmww 0xA0700000 0x00000001  ;# Enable the memory controller.\n\tmww 0xA0700024 0x00000006  ;# Set the refresh counter 6\n\tmww 0xA0700028 0x00000001  ;#\n\tmww 0xA0700030 0x00000001  ;# Set the precharge period\n\tmww 0xA0700034 0x00000004  ;# Active to precharge command period is 16 clock cycles\n\tmww 0xA070003C 0x00000001  ;# tAPR\n\tmww 0xA0700040 0x00000005  ;# tDAL\n\tmww 0xA0700044 0x00000001  ;# tWR\n\tmww 0xA0700048 0x00000006  ;# tRC 32 clock cycles\n\tmww 0xA070004C 0x00000006  ;# tRFC 32 clock cycles\n\tmww 0xA0700054 0x00000001  ;# tRRD\n\tmww 0xA0700058 0x00000001  ;# tMRD\n\tmww 0xA0700100 0x00004280  ;# Dynamic Config 0 (cs4)\n\tmww 0xA0700120 0x00004280  ;# Dynamic Config 1 (cs5)\n\tmww 0xA0700140 0x00004280  ;# Dynamic Config 2 (cs6)\n\tmww 0xA0700160 0x00004280  ;# Dynamic Config 3 (cs7)\n\t#\n\tmww 0xA0700104 0x00000203  ;# CAS latency is 2 at 100 MHz\n\tmww 0xA0700124 0x00000203  ;# CAS latency is 2 at 100 MHz\n\tmww 0xA0700144 0x00000203  ;# CAS latency is 2 at 100 MHz\n\tmww 0xA0700164 0x00000203  ;# CAS latency is 2 at 100 MHz\n\t#\n\tmww 0xA0700020 0x00000103  ;# issue SDRAM PALL command\n\t#\n\tmww 0xA0700024 0x00000001  ;# Set the refresh counter to be as small as possible\n\t#\n\t# Add some dummy writes to give the SDRAM time to settle, it needs two\n\t# AHB clock cycles, here we poke in the debugger flag, this lets\n\t# the software know that we are in the debugger\n\tmww 0xA0900000 0x00000002\n\tmww 0xA0900000 0x00000002\n\tmww 0xA0900000 0x00000002\n\tmww 0xA0900000 0x00000002\n\tmww 0xA0900000 0x00000002\n\t#\n\tmdw 0xA0900000\n\tmdw 0xA0900000\n\tmdw 0xA0900000\n\tmdw 0xA0900000\n\tmdw 0xA0900000\n\t#\n\tmww 0xA0700024 0x00000030 ;# Set the refresh counter to 30\n\tmww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command\n\t#\n\t# Next we perform a read of RAM.\n\t# mw = move word.\n\tmdw 0x00022000\n\t# mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3\n\t#\n\tmww 0xA0700020 0x00000003   ;# issue SDRAM NORMAL command\n\tmww 0xA0700100 0x00084280   ;# Enable buffer access\n\tmww 0xA0700120 0x00084280   ;# Enable buffer access\n\tmww 0xA0700140 0x00084280   ;# Enable buffer access\n\tmww 0xA0700160 0x00084280   ;# Enable buffer access\n\n\t#Set byte lane state (static mem 1)\"\n\tmww 0xA0700220 0x00000082\n\t#Flash Start\n\tmww 0xA09001F8 0x50000000\n\t#Flash Mask Reg\n\tmww 0xA09001FC 0xFF000001\n\tmww 0xA0700028 0x00000001\n\n\t#  RAMAddr = 0x00020000\n\t#  RAMSize = 0x00004000\n\n\t# Set the processor mode\n\treg cpsr 0xd3\n}\n\n$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1\n\n#####################\n# Flash configuration\n#####################\n\n#M29DW323DB - not working\n#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/digilent_analog_discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Digilent Analog Discovery\n#\n# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,842,1018&Prod=ANALOG-DISCOVERY\n#\n# Config is based on data from\n# https://github.com/bvanheu/urjtag-ad/commit/8bd883ee01d134f94b79cbbd00df42cd03bafd71\n#\n\nadapter driver ftdi\nftdi device_desc \"Digilent USB Device\"\nftdi vid_pid 0x0403 0x6014\n\nftdi layout_init 0x8008 0x800b\n\nadapter speed 25000\n\nsource [find cpld/xilinx-xc6s.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/digilent_atlys.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# http://digilentinc.com/atlys/\n#\n# The Digilent Atlys normally requires proprietary tools to program and will\n# enumerate as:\n#   ID 1443:0007 Digilent Development board JTAG\n#\n# However, the ixo-usb-jtag project provides an alternative open firmware for\n# the on board programmer. When using this firmware the board will then\n# enumerate as:\n#   ID 16c0:06ad Van Ooijen Technische Informatica\n# (With SerialNumber == hw_nexys)\n#\n# See the interface/usb-jtag.cfg for more information.\n\nsource [find interface/usb-jtag.cfg]\nsource [find cpld/xilinx-xc6s.cfg]\nsource [find cpld/jtagspi.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/digilent_nexys_video.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Digilent Nexys Video with Xilinx Artix-7 FPGA\n# https://reference.digilentinc.com/programmable-logic/nexys-video/start\n\nadapter driver ftdi\nadapter speed 30000\n\nftdi device_desc \"Digilent USB Device\"\nftdi vid_pid 0x0403 0x6010\n\n# channel 0 is dedicated for Digilent's DPTI Interface\n# channel 1 is used for JTAG\nftdi channel 1\n\n# just TCK TDI TDO TMS, no reset\nftdi layout_init 0x0088 0x008b\nreset_config none\n\n# Enable sampling on falling edge for high JTAG speeds.\nftdi tdo_sample_edge falling\n\ntransport select jtag\n\nsource [find cpld/xilinx-xc7.cfg]\nsource [find cpld/jtagspi.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/digilent_zedboard.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Digilent Zedboard Rev.C, Rev.D with Xilinx Zynq chip\n#\n# http://zedboard.com/product/zedboard\n#\n\nsource [find interface/ftdi/digilent_jtag_smt2.cfg]\n\nreset_config srst_only srst_push_pull\n\nsource [find target/zynq_7000.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/diolan_lpc4350-db1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Diolan LPC-4350-DB1 development board\n#\n\nset CHIPNAME lpc4350\n\nsource [find target/lpc4350.cfg]\n\nflash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/diolan_lpc4357-db1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Diolan LPC-4357-DB1 development board\n#\n\nset CHIPNAME lpc4357\n\nsource [find target/lpc4357.cfg]\n\nflash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/dk-tm4c129.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho \"WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti_dk-tm4c129.cfg\"\n\nsource [find board/ti_dk-tm4c129.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/dm355evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# DM355 EVM board\n#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html\n#   http://c6000.spectrumdigital.com/evmdm355/\n\nsource [find target/ti_dm355.cfg]\n\nreset_config trst_and_srst separate\n\n# NOTE:  disable or replace this call to dm355evm_init if you're\n# debugging new UBL code from SRAM.\n$_TARGETNAME configure -event reset-init { dm355evm_init }\n\n#\n# This post-reset init is called when the MMU isn't active, all IRQs\n# are disabled, etc.  It should do most of what a UBL does, except for\n# loading code (like U-Boot) into DRAM and running it.\n#\nproc dm355evm_init {} {\n\tglobal dm355\n\n\techo \"Initialize DM355 EVM board\"\n\n\t# CLKIN\t= 24 MHz ... can't talk quickly to ARM yet\n\tjtag_rclk 1500\n\n\t########################\n\t# PLL1\t\t= 432 MHz (/8, x144)\n\t# ...SYSCLK1\t= 216 MHz (/2)  ... ARM, MJCP\n\t# ...SYSCLK2\t= 108 MHz (/4)  ... Peripherals\n\t# ...SYSCLK3\t= 27  MHz (/16) ... VPBE, DAC\n\t# ...SYSCLK4\t= 108 MHz (/4)  ... VPSS\n\t#\tpll1.{prediv,div1,div2} are fixed\n\t#\tpll1.postdiv set in MISC (for *this* speed grade)\n\n\tset addr [dict get $dm355 pllc1]\n\tset pll_divs [dict create]\n\tdict set pll_divs div3 16\n\tdict set pll_divs div4 4\n\tpll_v02_setup $addr 144 $pll_divs\n\n\t# ARM is now running at 216 MHz, so JTAG can go faster\n\tjtag_rclk 20000\n\n\t########################\n\t# PLL2\t\t= 342 MHz (/8, x114)\n\t# ....SYSCLK1\t= 342 MHz (/1)  ... DDR PHY at 171 MHz, 2x clock\n\t#\tpll2.{postdiv,div1} are fixed\n\n\tset addr [dict get $dm355 pllc2]\n\tset pll_divs [dict create]\n\tdict set pll_divs div1 1\n\tdict set pll_divs prediv 8\n\tpll_v02_setup $addr 114 $pll_divs\n\n\t########################\n\t# PINMUX\n\n\t# All Video Inputs\n\tdavinci_pinmux $dm355 0 0x00007f55\n\t# All Video Outputs\n\tdavinci_pinmux $dm355 1 0x00145555\n\t# EMIFA (NOTE: more could be set up for use as GPIOs)\n\tdavinci_pinmux $dm355 2 0x00000c08\n\t# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs\n\tdavinci_pinmux $dm355 3 0x1bff55ff\n\t# MMC/SD0 instead of MS; SPI0\n\tdavinci_pinmux $dm355 4 0x00000000\n\n\t########################\n\t# PSC setup (minimal)\n\n\t# DDR EMIF/13, AEMIF/14, UART0/19\n\tpsc_enable 13\n\tpsc_enable 14\n\tpsc_enable 19\n\tpsc_go\n\n\t########################\n\t# DDR2 EMIF\n\n\t# VTPIOCR impedance calibration\n\tset addr [dict get $dm355 sysbase]\n\tset addr [expr {$addr + 0x70}]\n\n\t# clear CLR, LOCK, PWRDN; wait a clock; set CLR\n\tmmw $addr 0 0x20c0\n\tmmw $addr 0x2000 0\n\n\t# wait for READY\n        while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }\n\n\t# set IO_READY; then LOCK and PWRSAVE; then PWRDN\n\tmmw $addr 0x4000 0\n\tmmw $addr 0x0180 0\n\tmmw $addr 0x0040 0\n\n\t# NOTE:  this DDR2 initialization sequence borrows from\n\t# both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.\n\n\t# reset (then re-enable) DDR controller\n\tpsc_reset 13\n\tpsc_go\n\tpsc_enable 13\n\tpsc_go\n\n\t# now set it up for Micron MT47H64M16HR-37E @ 171 MHz\n\n\tset addr [dict get $dm355 ddr_emif]\n\n\t# DDRPHYCR1\n\tmww [expr {$addr + 0xe4}] 0x50006404\n\n\t# PBBPR -- burst priority\n\tmww [expr {$addr + 0x20}] 0xfe\n\n\t# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*\n\tmmw [expr {$addr + 0x08}] 0x00800000 0\n\tmmw [expr {$addr + 0x08}] 0x0013c632 0x03870fff\n\n\t# SDTIMR0, SDTIMR1\n\tmww [expr {$addr + 0x10}] 0x2a923249\n\tmww [expr {$addr + 0x14}] 0x4c17c763\n\n\t# SDCR -- relock SDTIM*\n\tmmw [expr {$addr + 0x08}] 0 0x00008000\n\n\t# SDRCR -- refresh rate (171 MHz * 7.8usec)\n\tmww [expr {$addr + 0x0c}] 1336\n\n\t########################\n\t# ASYNC EMIF\n\n\tset addr [dict get $dm355 a_emif]\n\n\t# slow/pessimistic timings\n\tset nand_timings 0x40400204\n\t# fast (25% faster page reads)\n\t#set nand_timings 0x0400008c\n\n\t# AWCCR\n\tmww [expr {$addr + 0x04}] 0xff\n\t# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)\n\tmww [expr {$addr + 0x10}] $nand_timings\n\t# CS1 == dm9000 Ethernet\n\tmww [expr {$addr + 0x14}] 0x00a00505\n\t# NANDFCR -- only CS0 has NAND\n\tmww [expr {$addr + 0x60}] 0x01\n\n\t# default: both chipselects to the NAND socket are used\n\tnand probe 0\n\tnand probe 1\n\n\t########################\n\t# UART0\n\n\tset addr [dict get $dm355 uart0]\n\n\t# PWREMU_MGNT -- rx + tx in reset\n\tmww [expr {$addr + 0x30}] 0\n\n\t# DLL, DLH -- 115200 baud\n\tmwb [expr {$addr + 0x20}] 0x0d\n\tmwb [expr {$addr + 0x24}] 0x00\n\n\t# FCR - clear and disable FIFOs\n\tmwb [expr {$addr + 0x08}] 0x07\n\tmwb [expr {$addr + 0x08}] 0x00\n\n\t# IER - disable IRQs\n\tmwb [expr {$addr + 0x04}] 0x00\n\n\t# LCR - 8-N-1\n\tmwb [expr {$addr + 0x0c}] 0x03\n\n\t# MCR - no flow control or loopback\n\tmwb [expr {$addr + 0x10}] 0x00\n\n\t# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt\n\tmww [expr {$addr + 0x30}] 0xe001\n\n\n\t########################\n\n\t# turn on icache - set I bit in cp15 register c1\n\tarm mcr 15 0 0 1 0 0x00051078\n}\n\n# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.\n#\n# NOTE:  \"hwecc4\" here presumes that if you're using the standard 2GB NAND\n# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to\n# use \"hwecc4_infix\" for the UBL; or else (b) aren't updating anything that\n# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.\nset _FLASHNAME $_CHIPNAME.boot\nnand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000\nset _FLASHNAME $_CHIPNAME.flash\nnand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000\n\n# FIXME\n#  - support writing UBL with its header (new layout only with new ROMs)\n#  - support writing ABL/U-Boot with its header (new layout)\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/dm365evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# DM365 EVM board -- Beta\n#   http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html\n#   http://support.spectrumdigital.com/boards/evmdm365\n\nsource [find target/ti_dm365.cfg]\n\n# NOTE:  in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG\n# connector, so it doesn't affect generation of the reset signal.\n# Accordingly, resets require something else.  ICEpick could do it;\n# but its docs aren't generally available.\n#\n# At this writing, newer boards aren't available ... so assume no SRST.\n# Also ICEpick docs aren't available ... so we must use watchdog reset,\n# and hope the CPU isn't wedged or in a WFI loop (either of which can\n# block access to CPU and thus watchdog registers).\n\nreset_config trst_only\n$_TARGETNAME configure -event reset-assert \"davinci_wdog_reset\"\n\n# SW5.1 routes CS0: NAND vs OneNAND.\n# SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)\n# for boot-from-flash, those must agree with SW4.3:1 settings.\n\nif { [info exists CS0MODE] } {\n\t# NAND or OneNAND\n\tset CS0 $CS0MODE\n} else {\n\tset CS0 \"\"\n\techo \"WARNING:  CS0 configuration not known\"\n\tproc cs0_setup {a_emif} {}\n\tproc flashprobe {} {}\n}\n\nset a_emif [dict get $dm365 a_emif]\n\n# As shipped:  boot from NAND.\nif { $CS0 == \"NAND\" } {\n\techo \"CS0 NAND\"\n\n\t# NAND socket has two chipselects.  Default MT29F16G08FAA chip\n\t# has 1GByte on each one.\n\t# NOTE:  \"hwecc4\" here presumes that you're not updating anything\n\t# that needs infix layout (e.g. UBL, old U-Boot, etc)\n\tnand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif\n\tnand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif\n\n\tproc cs0_setup {a_emif} {\n\t\tglobal dm365\n\n\t\t# 8 bit EMIF\n\t\tdavinci_pinmux $dm365 2 0x00000016\n\n\t\t# slow/pessimistic timings\n\t\tset nand_timings 0x40400204\n\t\t# fast (25% faster page reads)\n\t\t#set nand_timings 0x0400008c\n\n\t\t# CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)\n\t\tmww [expr {$a_emif + 0x10}] $nand_timings\n\n\t\t# NANDFCR -- CS0 has NAND\n\t\tmww [expr {$a_emif + 0x60}] 0x01\n\t}\n\tproc flashprobe {} {\n\t\tnand probe 0\n\t\tnand probe 1\n\t}\n\n} elseif { $CS0 == \"OneNAND\" } {\n\techo \"CS0 OneNAND\"\n\n\t# No support for this OneNAND in OpenOCD (yet) or Linux ...\n\t# REVISIT OneNAND timings not verified to work!\n\techo \"WARNING -- OneNAND not yet tested!\"\n\n\tproc cs0_setup {a_emif} {\n\t\tglobal dm365\n\n\t\t# 16 bit EMIF\n\t\tdavinci_pinmux $dm365 2 0x00000055\n\n\t\t# CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)\n\t\tmww [expr {$a_emif + 0x10}] 0x00000001\n\n\t\t# ONENANDCTRL -- CS0 has OneNAND, enable sync reads\n\t\tmww [expr {$a_emif + 0x5c}] 0x0441\n\t}\n\tproc flashprobe {} { }\n}\n\n# NOTE:  disable or replace this call to dm365evm_init if you're\n# debugging new UBL/NANDboot code from SRAM.\n$_TARGETNAME configure -event reset-init { dm365evm_init }\n\n#\n# This post-reset init is called when the MMU isn't active, all IRQs\n# are disabled, etc.  It should do most of what a UBL does, except for\n# loading code (like U-Boot) into DRAM and running it.\n#\nproc dm365evm_init {} {\n\tglobal dm365\n\n\techo \"Initialize DM365 EVM board\"\n\n\t# CLKIN\t= 24 MHz ... can't talk quickly to ARM yet\n\tadapter speed 1500\n\n\t# FIXME -- PLL init\n\n\t########################\n\t# PINMUX setup\n\n\tdavinci_pinmux $dm365 0 0x00fd0000\n\tdavinci_pinmux $dm365 1 0x00145555\n\t# mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand\n\tdavinci_pinmux $dm365 3 0x375affff\n\tdavinci_pinmux $dm365 4 0x55556555\n\n\t########################\n\t# PSC setup (minimal)\n\n\t# DDR EMIF/13, AEMIF/14, UART0/19\n\tpsc_enable 13\n\tpsc_enable 14\n\tpsc_enable 19\n\tpsc_go\n\n\t# FIXME setup DDR2 (needs PLL)\n\n\t########################\n\t# ASYNC EMIF\n\n\tset a_emif [dict get $dm365 a_emif]\n\n\t# AWCCR\n\tmww [expr {$a_emif + 0x04}] 0xff\n\t# CS0 == NAND or OneNAND\n\tcs0_setup $a_emif\n\t# CS1 == CPLD\n\tmww [expr {$a_emif + 0x14}] 0x00a00505\n\n\t# FIXME setup UART0\n\n\tflashprobe\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/dm6446evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# DM6446 EVM board\n#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html\n#   http://c6000.spectrumdigital.com/davincievm/\n# EVM is just the board; buy that at Spectrum.\n# The \"kit\" from TI also has: video camera, LCD video monitor, more.\n\nsource [find target/ti_dm6446.cfg]\n\n# J4 controls what CS2 hooks up to, usually NOR or NAND flash.\n# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings.\n# S3.3 controls AEMIF bus width.\n\nif { [info exists J4_OPTION] } {\n\t# NOR, NAND, SRAM, ...\n\tset CS2_MODE $J4_OPTION\n} else {\n\tset CS2_MODE \"\"\n}\n\n# ARM boot:\n#  S3.1 = 0, S3.2 = 0\t==> ROM/UBL boot via NAND (J4 == NAND)\n#  S3.1 = 1, S3.2 = 0\t==> AEMIF boot (J4 == NOR or SRAM)\n#  S3.1 = 0, S3.2 = 1\t==> ROM/UBL boot via HPI\n#  S3.1 = 1, S3.2 = 1\t==> ROM/UBL boot via UART (J4 == don't care)\n# AEMIF bus width:\n#  S3.3 = 0\t\t==> 8 bit bus width\n#  S3.3 = 1\t\t==> 16 bit bus width\n# DSP boot:\n#  S3.4 = 0\t\t==> controlled by ARM\n\nif { $CS2_MODE == \"NOR\" } {\n\t# 16 Mbytes address space; 16 bit bus width\n\t# (older boards used 32MB parts, with upper 16 MB unusable)\n\tset _FLASHNAME $_CHIPNAME.flash\n\tflash bank $_FLASHNAME cfi 0x02000000 0x01000000 2 2 $_TARGETNAME\n\tproc flashprobe {} { flash probe 0 }\n} elseif { $CS2_MODE == \"NAND\" } {\n\t# 64 Mbyte small page; 8 bit bus width\n\tnand device davinci $_TARGETNAME 0x02000000 hwecc1 0x01e00000\n\tproc flashprobe {} { nand probe 0 }\n} elseif { $CS2_MODE == \"SRAM\" } {\n\t# 4 Mbyte address space; 16 bit bus width\n\t# loaded via JTAG or HPI\n\tproc flashprobe {} {}\n} else {\n\t# maybe it's HPI boot?  can't tell...\n\techo \"WARNING:  CS2/flash configuration not recognized\"\n\tproc flashprobe {} {}\n}\n\n# NOTE:  disable or replace this call to dm6446evm_init if you're\n# debugging new UBL code from SRAM (for NAND boot).\n$_TARGETNAME configure -event reset-init { dm6446evm_init }\n\n#\n# This post-reset init is called when the MMU isn't active, all IRQs\n# are disabled, etc.  It should do most of what a UBL does, except for\n# loading code (like U-Boot) into DRAM and running it.\n#\nproc dm6446evm_init {} {\n\n\techo \"Initialize DM6446 EVM board\"\n\n\t# FIXME initialize everything:\n\t#  - PLL1\n\t#  - PLL2\n\t#  - PINMUX\n\t#  - PSC\n\t#  - DDR\n\t#  - AEMIF\n\t#  - UART0\n\t#  - icache\n\n\tflashprobe\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/dp_busblaster_v3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Dangerous Prototypes - Bus Blaster\n#\n# http://dangerousprototypes.com/docs/Bus_Blaster\n#\n# To reprogram the on-board CPLD do:\n# openocd -f board/dp_busblaster_v3.cfg -c \"adapter speed 1000; init; svf <path_to_svf>; shutdown\"\n#\n\nsource [find interface/ftdi/dp_busblaster.cfg]\nftdi channel 1\n\njtag newtap xc2c32a tap -expected-id 0x06e1c093 -irlen 8\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/dp_busblaster_v4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Dangerous Prototypes - Bus Blaster\n#\n# http://dangerousprototypes.com/docs/Bus_Blaster\n#\n# The Bus Blaster has a configurable buffer between the FTDI FT2232H\n# and the JTAG header which allows it to emulate various debugger\n# types. This config works with KT-Link compatible implementation from\n# https://raw.githubusercontent.com/dergraaf/busblaster_v4/master/ktlink/ktlink.svf\n#\n# To reprogram the on-board CPLD do:\n# openocd -f board/dp_busblaster_v4.cfg -c \"adapter speed 1000; init; svf <path_to_svf>; shutdown\"\n#\n\nsource [find interface/ftdi/dp_busblaster.cfg]\nftdi channel 1\n\njtag newtap xc2c64a tap -expected-id 0x06e5c093 -irlen 8\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/dptechnics_dpt-board-v1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Product page:\n# https://www.dptechnics.com/en/products/dpt-board-v1.html\n#\n# JTAG is a 5 pin array located close to main module in following order:\n# 1. JTAG TCK\n# 2. JTAG TDO\n# 3. JTAG TDI\n# 4. JTAG TMS\n# 5. GND\tThe GND is located near letter G of word JTAG on board.\n#\n# Two RST pins are connected to:\n# 1. GND\n# 2. GPIO11\tthis pin is located near letter R of word RST.\n#\n# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example\n# with 10K resistor connected to V3.3 pin.\n#\n# This board is powered from micro USB connector. No real reset pin or button, for\n# example RESET_L is available.\n\nsource [find target/atheros_ar9331.cfg]\n\n$_TARGETNAME configure -event reset-init {\n\tar9331_25mhz_pll_init\n\tsleep 1\n\tar9331_ddr2_init\n}\n\nset ram_boot_address 0xa0000000\n$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000\n\nflash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ecp5_evaluation.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Lattice ECP5 evaluation Kit\n# https://www.latticesemi.com/view_document?document_id=52479\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n\nftdi channel 0\nftdi layout_init 0x0008 0x008b\nreset_config none\ntransport select jtag\nadapter speed 6000\n\nsource [find fpga/lattice_ecp5.cfg]\n\n#openocd -f board/ecp5_evaluation.cfg -c \"init\" -c \"pld load 0 shared_folder/ecp5_blinker_impl1.bit\"\n#ipdbg -start -tap ecp5.tap -hub 0x32 -port 5555 -tool 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/efikamx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Genesi USA EfikaMX\n#  http://www.genesi-usa.com/products/efika\n\n# Fall back to 6MHz if RTCK is not supported\njtag_rclk 6000\n$_TARGETNAME configure -event \"reset-start\" { jtag_rclk 6000 }\n\nsource [find target/imx51.cfg]\n\nreset_config trst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/efm32.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Configuration for EFM32 boards with on-board SEGGER J-Link\n#\n# Tested with Tiny, Giant and Zero Gecko Starter Kit.\n#\n\nsource [find interface/jlink.cfg]\ntransport select swd\nadapter speed 1000\n\nset CHIPNAME efm32\nsource [find target/efm32.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/eir.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Elector Internet Radio board\n# http://www.ethernut.de/en/hardware/eir/index.html\n\nsource [find target/at91sam7se512.cfg]\n\n$_TARGETNAME configure -event reset-init {\n\t# WDT_MR, disable watchdog\n\tmww 0xFFFFFD44 0x00008000\n\n\t# RSTC_MR, enable user reset\n\tmww 0xfffffd08 0xa5000001\n\n\t# CKGR_MOR\n\tmww 0xFFFFFC20 0x00000601\n\tsleep 10\n\n\t# CKGR_PLLR\n\tmww 0xFFFFFC2C 0x00481c0e\n\tsleep 10\n\n\t# PMC_MCKR\n\tmww 0xFFFFFC30 0x00000007\n\tsleep 10\n\n\t# PMC_IER\n\tmww 0xFFFFFF60 0x00480100\n\n\t#\n\t# Enable SDRAM interface.\n\t#\n\n\t# Enable SDRAM control at PIO A.\n\tmww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF\n\tmww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF\n\n\t# Enable address bus (A0, A2-A11, A13-A17) at PIO B\n\tmww 0xfffff674 0x0003effd ;# PIO_BSR_OFF\n\tmww 0xfffff604 0x0003effd ;# PIO_PDR_OFF\n\n\t# Enable 16 bit data bus at PIO C\n\tmww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF\n\tmww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF\n\n\t# Enable SDRAM chip select\n\tmww 0xffffff80 0x00000002 ;# EBI_CSA_OFF\n\n\t# Set SDRAM characteristics in configuration register.\n\t# Hard coded values for MT48LC32M16A2 with 48MHz CPU.\n\tmww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF\n\tsleep 10\n\n\t# Issue 16 bit SDRAM command: NOP\n\tmww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\n\t# Issue 16 bit SDRAM command: Precharge all\n\tmww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\n\t# Issue 8 auto-refresh cycles\n\tmww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\tmww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\tmww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\tmww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\tmww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\tmww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\tmww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\tmww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000000\n\n\t# Issue 16 bit SDRAM command: Set mode register\n\tmww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF\n\tmww 0x20000014 0xcafedede\n\n\t# Set refresh rate count ???\n\tmww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF\n\n\t# Issue 16 bit SDRAM command: Normal mode\n\tmww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF\n\tmww 0x20000000 0x00000180\n\n\t#\n\t# Enable external reset key.\n\t#\n\tmww 0xfffffd08 0xa5000001\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm3s1968.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI/Luminary Stellaris LM3S1968 Evaluation Kits\n#\n# http://www.ti.com/tool/ek-lm3s1968\n#\n\n# NOTE:  to use J-Link instead of the on-board interface,\n# you may also need to reduce adapter speed to be about 1200.\n# source [find interface/jlink.cfg]\n\n# include the FT2232 interface config for on-board JTAG interface\n# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!\n# so is using in JTAG mode, as done here.\nsource [find interface/ftdi/luminary.cfg]\n\n# include the target config\nset WORKAREASIZE 0x2000\nset CHIPNAME lm3s1968\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm3s3748.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI/Luminary Stellaris lm3s3748 Evaluation Kits\n#\n# http://www.ti.com/tool/ek-lm3s3748\n#\n\n# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!\n# so is using it in JTAG mode, as done here.\nsource [find interface/ftdi/luminary.cfg]\n\n# 20k working area\nset WORKAREASIZE 0x4000\nset CHIPNAME lm3s3748\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm3s6965.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI/Luminary Stellaris LM3S6965 Evaluation Kits\n#\n# http://www.ti.com/tool/ek-lm3s6965\n#\n\n# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!\n# so is using it in JTAG mode, as done here.\nsource [find interface/ftdi/luminary.cfg]\n\n# 20k working area\nset WORKAREASIZE 0x5000\nset CHIPNAME lm3s6965\n# include the target config\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm3s811-revb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI/Luminary Stellaris LM3S811 Evaluation Kits (rev B and earlier)\n#\n# http://www.ti.com/tool/ek-lm3s811\n#\n\n# NOTE: newer 811-EK boards (rev C and above) shouldn't use this.\n# use board/ek-lm3s811.cfg\nsource [find interface/ftdi/luminary-lm3s811.cfg]\n\n# include the target config\nset WORKAREASIZE 0x2000\nset CHIPNAME lm3s811\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm3s811.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI/Luminary Stellaris LM3S811 Evaluation Kits\n#\n# http://www.ti.com/tool/ek-lm3s811\n#\n\n# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!\n# so is using it in JTAG mode, as done here.\n# NOTE:  older '811-EK boards (before rev C) shouldn't use this.\nsource [find interface/ftdi/luminary.cfg]\n\n# include the target config\nset WORKAREASIZE 0x2000\nset CHIPNAME lm3s811\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm3s8962.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI/Luminary Stellaris LM3S8962 Evaluation Kits\n#\n# http://www.ti.com/tool/ek-lm3s8962\n#\n\n# NOTE:  using the on-board FT2232 JTAG/SWD/SWO interface is optional!\n# so is using it in JTAG mode, as done here.\nsource [find interface/ftdi/luminary.cfg]\n\n# 64k working area\nset WORKAREASIZE 0x10000\nset CHIPNAME lm3s8962\n# include the target config\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm3s9b9x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI/Luminary Stellaris LM3S9B9x Evaluation Kits\n#\n# http://www.ti.com/tool/ek-lm3s9b90\n# http://www.ti.com/tool/ek-lm3s9b92\n#\n\n# NOTE:  using the bundled FT2232 JTAG/SWD/SWO interface is optional!\n# so is using in JTAG mode, as done here.\nsource [find interface/ftdi/luminary-icdi.cfg]\n\nset WORKAREASIZE 0x4000\nset CHIPNAME lm3s9b9x\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm3s9d92.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI/Luminary Stellaris LM3S9D92 Evaluation Kits\n#\n# http://www.ti.com/tool/ek-lm3s9d92\n#\n\n# NOTE:  using the bundled FT2232 JTAG/SWD/SWO interface is optional!\n# so is using in JTAG mode, as done here.\nsource [find interface/ftdi/luminary-icdi.cfg]\n\n# 64k working area\nset WORKAREASIZE 0x10000\nset CHIPNAME lm3s9d92\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm4f120xl.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI Stellaris Launchpad ek-lm4f120xl Evaluation Kits\n#\n# http://www.ti.com/tool/ek-lm4f120xl\n#\n\n#\n# NOTE: using the bundled ICDI interface is optional!\n# This interface is not ftdi based as previous boards were\n#\nsource [find interface/ti-icdi.cfg]\n\ntransport select hla_jtag\n\nset WORKAREASIZE 0x8000\nset CHIPNAME lm4f120h5qr\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-lm4f232.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI Stellaris LM4F232 Evaluation Kits\n#\n# http://www.ti.com/tool/ek-lm4f232\n#\n\n#\n# NOTE: using the bundled ICDI interface is optional!\n# This interface is not ftdi based as previous boards were\n#\nsource [find interface/ti-icdi.cfg]\n\ntransport select hla_jtag\n\nset WORKAREASIZE 0x8000\nset CHIPNAME lm4f23x\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-tm4c123gxl.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho \"WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti_ek-tm4c123gxl.cfg\"\n\nsource [find board/ti_ek-tm4c123gxl.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ek-tm4c1294xl.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho \"WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti_ek-tm4c1294xl.cfg\"\n\nsource [find board/ti_ek-tm4c1294xl.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/embedded-artists_lpc2478-32.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Embedded Artists eval board for LPC2478\n# http://www.embeddedartists.com/\n\n# Target device: LPC2478\nset CCLK 72000\nsource [find target/lpc2478.cfg]\n\n# Helper\n#\nproc read_register {register} {\n    return [read_memory $register 32 1]\n}\n\nproc init_board {} {\n    # Delays on reset lines\n    adapter srst delay 500\n    jtag_ntrst_delay 1\n\n    # Adaptive JTAG clocking through RTCK.\n    #\n    jtag_rclk 20\n\n    global _TARGETNAME\n    global _CHIPNAME\n\n    # A working area will help speeding the flash programming\n    $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0\n\n    # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)\n    flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe\n\n    # Event handlers\n    #\n    $_TARGETNAME configure -event reset-start {\n        # Back to the slow JTAG clock\n        jtag_rclk 20\n    }\n\n    $_TARGETNAME configure -event reset-init {\n        arm core_state arm\n        arm7_9 dcc_downloads enable     ;# Speed up downloads by using DCC transfer\n        arm7_9 fast_memory_access enable\n\n        # Peripheral clocks\n        mww 0xE01FC0C4 0x04280FFE       ;# PCONP: (reset value)\n\n        # Map the user flash to the vector table area (0x00...0x3F)\n        mww 0xE01FC040 0x00000001       ;# MEMMAP: User flash\n\n        # Memory accelerator module\n        mww 0xE01FC004 0x00000003       ;# MAMTIM: 3 clock cycles\n        mww 0xE01FC000 0x00000002       ;# MAMCR: fully enabled\n\n        # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)\n        mww 0xE002C014 0x55010115       ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,\n                                         # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,\n                                         # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3\n        mww 0xE002C018 0x55555555       ;# PINSEL6: P3.0...P3.15=D0...D15\n        mww 0xE002C01C 0x55555555       ;# PINSEL7: P3.16...P3.31=D16...D31\n        mww 0xE002C020 0x55555555       ;# PINSEL8: P4.0...P4.15=A0...A15\n        mww 0xE002C024 0x50051555       ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,\n                                         # P4.25=WE, P4.30=CS0, P4.31=CS1\n        mww 0xFFE08000 0x00000001       ;# EMCControl: Enable EMC\n\n        # Start PLL, then use faster JTAG clock\n        enable_pll\n        jtag_rclk 3000\n\n        # 16-bit flash @ CS0 (SST39VF3201-70)\n        mww 0xFFE08200 0x00080081       ;# EMCStaticConfig0: 16 bit, PB=1, buffers on\n        mww 0xFFE08204 0x00000000       ;# EMCStaticWaitWen0\n        mww 0xFFE08208 0x00000000       ;# EMCStaticWaitOen0\n        mww 0xFFE0820C 0x00000005       ;# EMCStaticWaitRd0\n        mww 0xFFE08210 0x00000005       ;# EMCStaticWaitPage0\n        mww 0xFFE08214 0x00000003       ;# EMCStaticWaitWr0\n        mww 0xFFE08218 0x00000001       ;# EMCStaticWaitTurn0\n\n        # 8-bit NAND @ CS1\n        # TODO\n\n        # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)\n        mww 0xFFE08028 0x00000001       ;# EMCDynamicReadConfig\n        mww 0xFFE08030 0x00000001       ;# EMCDynamicRP\n        mww 0xFFE08034 0x00000003       ;# EMCDynamicRAS\n        mww 0xFFE08038 0x00000005       ;# EMCDynamicSREX\n        mww 0xFFE0803C 0x00000001       ;# EMCDynamicAPR\n        mww 0xFFE08040 0x00000005       ;# EMCDynamicDAL\n        mww 0xFFE08044 0x00000001       ;# EMCDynamicWR\n        mww 0xFFE08048 0x00000005       ;# EMCDynamicRC\n        mww 0xFFE0804C 0x00000005       ;# EMCDynamicRFC\n        mww 0xFFE08050 0x00000005       ;# EMCDynamicXSR\n        mww 0xFFE08054 0x00000001       ;# EMCDynamicRRD\n        mww 0xFFE08058 0x00000001       ;# EMCDynamicMRD\n        #\n        mww 0xFFE08104 0x00000202       ;# EMCDynamicRasCas0\n        mww 0xFFE08100 0x00005488       ;# EMCDynamicConfig0\n        sleep 100\n        mww 0xFFE08020 0x00000183       ;# EMCDynamicControl: Clock on continuously, NOP\n        sleep 10\n        mww 0xFFE08020 0x00000103       ;# EMCDynamicControl: PRECHARGE-ALL\n        mww 0xFFE08024 0x00000046       ;# EMCDynamicRefresh\n        sleep 100\n        mww 0xFFE08020 0x00000083       ;# EMCDynamicControl: MODE\n        mdw 0xA0011000 1                ;# Set SDRAM mode register\n        mww 0xFFE08020 0x00000000       ;# EMCDynamicControl: NORMAL\n        mww 0xFFE08100 0x00085488       ;# EMCDynamicConfig0: Enable buffers\n    }\n\n    $_TARGETNAME configure -event gdb-attach {\n        # Without this gdb-attach will first time as probe will fail\n        reset init\n    }\n}\n\n# Enable the PLL.\n# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.\n# Note: The PLL output runs at a frequency N times the desired CPU clock.\n#       It in unavoidable that the CPU clock drops down to (4 MHz/N) during\n#       the initialization!\n#       Here: N=4\n#       Note that if the PLL is already active at the time this script is\n#       called, the effective value of N is the value of CCLKCFG at that time!\n#\nproc enable_pll {} {\n    # Disconnect PLL in case it is already connected\n    if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} {\n        # Disconnect it, but leave it enabled\n        # (This MUST be done in two steps)\n        mww 0xE01FC080 0x00000001       ;# PLLCON: disconnect PLL\n        mww 0xE01FC08C 0x000000AA       ;# PLLFEED\n        mww 0xE01FC08C 0x00000055       ;# PLLFEED\n    }\n    # Disable PLL (as it might already be enabled at this time!)\n    mww 0xE01FC080 0x00000000       ;# PLLCON: disable PLL\n    mww 0xE01FC08C 0x000000AA       ;# PLLFEED\n    mww 0xE01FC08C 0x00000055       ;# PLLFEED\n\n    # Setup PLL to generate 288 MHz from internal RC oscillator\n    mww 0xE01FC10C 0x00000000       ;# CLKSRCSEL: IRC\n    mww 0xE01FC084 0x00000023       ;# PLLCFG: N=1, M=36\n    mww 0xE01FC08C 0x000000AA       ;# PLLFEED\n    mww 0xE01FC08C 0x00000055       ;# PLLFEED\n    mww 0xE01FC080 0x00000001       ;# PLLCON: enable PLL\n    mww 0xE01FC08C 0x000000AA       ;# PLLFEED\n    mww 0xE01FC08C 0x00000055       ;# PLLFEED\n    sleep 100\n    mww 0xE01FC104 0x00000003       ;# CCLKCFG: divide by 4 (72 MHz)\n    mww 0xE01FC080 0x00000003       ;# PLLCON: connect PLL\n    mww 0xE01FC08C 0x000000AA       ;# PLLFEED\n    mww 0xE01FC08C 0x00000055       ;# PLLFEED\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/emcraft_imx8m-som-bsb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# configuration file for Emcraft IMX8M-SOM-BSB\n#\n\n# only JTAG supported\ntransport select jtag\n\n# set a safe JTAG clock speed, can be overridden\nadapter speed 1000\n\n# SRST and TRST are wired up\nreset_config trst_and_srst\n\n# delay after SRST goes inactive\nadapter srst delay 70\n\n# board has an i.MX8MQ with 4 Cortex-A53 cores\nset CHIPNAME imx8mq\nset CHIPCORES 4\n\n# source SoC configuration\nsource [find target/imx8m.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/emcraft_twr-vf6-som-bsb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# EmCraft Systems TWR-VF6-SOM-BSB\n#\n# http://www.emcraft.com/products/259#twr-kit\n#\n\nsource [find board/emcraft_vf6-som.cfg]\n\nreset_config srst_only srst_nogate\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/emcraft_vf6-som.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# EmCraft Systems Vybrid VF6 SOM\n#\n# http://www.emcraft.com/products/259#som\n#\n\nset CHIPNAME vf610\nsource [find target/vybrid_vf6xx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/esp32-bridge.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Example OpenOCD configuration file for ESP32 connected via ESP USB Bridge board\n#\n# For example, OpenOCD can be started for ESP32 debugging on\n#\n#   openocd -f board/esp32-bridge.cfg\n#\n\n# Source the JTAG interface configuration file\nsource [find interface/esp_usb_bridge.cfg]\n# ESP32 chip id defined in the idf esp_chip_model_t\nespusbjtag chip_id 1\n# Source the ESP32 configuration file\nsource [find target/esp32.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/esp32-ethernet-kit-3.3v.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Example OpenOCD configuration file for ESP32-ETHERNET-KIT board.\n#\n# For example, OpenOCD can be started for ESP32 debugging on\n#\n#   openocd -f board/esp32-ethernet-kit-3.3v.cfg\n#\n\n# Source the JTAG interface configuration file\nsource [find interface/ftdi/esp32_devkitj_v1.cfg]\nset ESP32_FLASH_VOLTAGE 3.3\n# Source the ESP32 configuration file\nsource [find target/esp32.cfg]\n\n# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they\n# do not relate to OpenOCD trying to read from a memory range without physical\n# memory being present there), you can try lowering this.\n#\n# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz\n# if CPU frequency is 160MHz or 240MHz.\nadapter speed 20000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/esp32-wrover-kit-1.8v.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Example OpenOCD configuration file for ESP32-WROVER-KIT board.\n#\n# For example, OpenOCD can be started for ESP32 debugging on\n#\n#   openocd -f board/esp32-wrover-kit-1.8v.cfg\n#\n\n# Source the JTAG interface configuration file\nsource [find interface/ftdi/esp32_devkitj_v1.cfg]\nset ESP32_FLASH_VOLTAGE 1.8\n# Source the ESP32 configuration file\nsource [find target/esp32.cfg]\n\n# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they\n# do not relate to OpenOCD trying to read from a memory range without physical\n# memory being present there), you can try lowering this.\n#\n# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz\n# if CPU frequency is 160MHz or 240MHz.\nadapter speed 20000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/esp32-wrover-kit-3.3v.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Example OpenOCD configuration file for ESP32-WROVER-KIT board.\n#\n# For example, OpenOCD can be started for ESP32 debugging on\n#\n#   openocd -f board/esp32-wrover-kit-3.3v.cfg\n#\n\n# Source the JTAG interface configuration file\nsource [find interface/ftdi/esp32_devkitj_v1.cfg]\nset ESP32_FLASH_VOLTAGE 3.3\n# Source the ESP32 configuration file\nsource [find target/esp32.cfg]\n\n# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they\n# do not relate to OpenOCD trying to read from a memory range without physical\n# memory being present there), you can try lowering this.\n#\n# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz\n# if CPU frequency is 160MHz or 240MHz.\nadapter speed 20000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/esp32s2-bridge.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Example OpenOCD configuration file for ESP32-S2 connected via ESP USB Bridge board\n#\n# For example, OpenOCD can be started for ESP32-S2 debugging on\n#\n#   openocd -f board/esp32s2-bridge.cfg\n#\n\n# Source the JTAG interface configuration file\nsource [find interface/esp_usb_bridge.cfg]\n# ESP32S2 chip id defined in the idf esp_chip_model_t\nespusbjtag chip_id 2\n# Source the ESP32-S2 configuration file\nsource [find target/esp32s2.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/esp32s2-kaluga-1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Example OpenOCD configuration file for ESP32-S2 Kaluga board.\n#\n# For example, OpenOCD can be started for ESP32-S2 debugging on\n#\n#   openocd -f board/esp32s2-kaluga-1.cfg\n#\n\nsource [find interface/ftdi/esp32s2_kaluga_v1.cfg]\nsource [find target/esp32s2.cfg]\n\n# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they\n# do not relate to OpenOCD trying to read from a memory range without physical\n# memory being present there), you can try lowering this.\n# On ESP32-S2, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz\n# if CPU frequency is 160MHz or 240MHz.\nadapter speed 20000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/esp32s3-bridge.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Example OpenOCD configuration file for ESP32-S3 connected via ESP USB Bridge board\n#\n# For example, OpenOCD can be started for ESP32-S3 debugging on\n#\n#   openocd -f board/esp32s3-bridge.cfg\n#\n\n# Source the JTAG interface configuration file\nsource [find interface/esp_usb_bridge.cfg]\n# ESP32S3 chip id defined in the idf esp_chip_model_t\nespusbjtag chip_id 9\n# Source the ESP32-S3 configuration file\nsource [find target/esp32s3.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/esp32s3-builtin.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Example OpenOCD configuration file for ESP32-S3 connected via builtin USB-JTAG adapter.\n#\n# For example, OpenOCD can be started for ESP32-S3 debugging on\n#\n#   openocd -f board/esp32s3-builtin.cfg\n#\n\n# Source the JTAG interface configuration file\nsource [find interface/esp_usb_jtag.cfg]\n# Source the ESP32-S3 configuration file\nsource [find target/esp32s3.cfg]\n\nadapter speed 40000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/esp32s3-ftdi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Example OpenOCD configuration file for ESP32-S3 connected via ESP-Prog.\n#\n# For example, OpenOCD can be started for ESP32-S3 debugging on\n#\n#   openocd -f board/esp32s3-ftdi.cfg\n#\n\n# Source the JTAG interface configuration file\nsource [find interface/ftdi/esp32_devkitj_v1.cfg]\n# Source the ESP32-S3 configuration file\nsource [find target/esp32s3.cfg]\n\n# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they\n# do not relate to OpenOCD trying to read from a memory range without physical\n# memory being present there), you can try lowering this.\n#\n# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz\n# if CPU frequency is 160MHz or 240MHz.\nadapter speed 20000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ethernut3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Ethernut 3 board configuration file\n#\n# http://www.ethernut.de/en/hardware/enut3/\n\n\n# AT91R40008-66AU ARM7TDMI Microcontroller\n# 256kB internal RAM\nsource [find target/at91r40008.cfg]\n\n\n# AT49BV322A-70TU NOR Flash\n# 2M x 16 mode at address 0x10000000\n# Common flash interface supported\n#\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME\n\n\n# Micrel MIC2775-29YM5 Supervisor\n# Reset output will remain active for 280ms (maximum)\n#\nadapter srst delay 300\njtag_ntrst_delay 300\n\n\narm7_9 fast_memory_access enable\narm7_9 dcc_downloads enable\nadapter speed 16000\n\n\n# Target events\n#\n$_TARGETNAME configure -event reset-init { board_init }\n\n# Initialize board hardware\n#\nproc board_init { } {\n\tboard_remap\n\tflash probe 0\n}\n\n# Memory remap\n#\nproc board_remap {{VERBOSE 0}} {\n\t# CS0: NOR flash\n\t#      16MB @ 0x10000000\n\t#      16-bit data bus\n\t#      4 wait states\n\t#\n\tmww 0xffe00000 0x1000212d\n\n\t# CS1: Ethernet controller\n\t#      1MB @ 0x20000000\n\t#      16-bit data bus\n\t#      2 wait states\n\t#      Byte select access\n\t#\n\tmww 0xffe00004 0x20003025\n\n\t# CS2: CPLD registers\n\t#      1MB @ 0x21000000\n\t#      8-bit data bus\n\t#      2 wait states\n\t#\n\tmww 0xffe00008 0x21002026\n\n\t# CS3: Expansion bus\n\t#      1MB @ 0x22000000\n\t#      8-bit data bus\n\t#      8 wait states\n\t#\n\tmww 0xffe00010 0x22002e3e\n\n\t# Remap command\n\t#\n\tmww 0xffe00020 0x00000001\n\n\tif {$VERBOSE != 0} {\n\t\techo \"0x00000000 RAM\"\n\t\techo \"0x10000000 Flash\"\n\t\techo \"0x20000000 Ethernet\"\n\t\techo \"0x21000000 CPLD\"\n\t\techo \"0x22000000 Expansion\"\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/evb-lan9255.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Microchip LAN9255 evaluation board\n# https://www.microchip.com/en-us/development-tool/EV25Y25A\n#\n\nset CHIPNAME same53\n\nsource [find target/atsame5x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/frdm-kl25z.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an Freescale Freedom eval board with a single MKL25Z128VLK4 chip.\n# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL25Z\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# increase working area to 16KB\nset WORKAREASIZE 0x4000\n\n# chip name\nset CHIPNAME MKL25Z128VLK4\n\nreset_config srst_only\n\nsource [find target/kl25.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/frdm-kl46z.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an Freescale Freedom eval board with a single MKL46Z256VLL4 chip.\n# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL46Z\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# increase working area to 16KB\nset WORKAREASIZE 0x4000\n\n# chip name\nset CHIPNAME MKL46Z256VLL4\n\nreset_config srst_only\n\nsource [find target/kl46.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/fsl_imx6q_sabresd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Board configuration file for the Freescale IMX6Q Sabre SD EVM\n#\n# This board does not have an embedded JTAG adapter, you must source\n# a suitable adapter configuration before sourcing this file.\n\n# Sabre SD has a standard ARM-20 JTAG connector with\n# nTRST and nSRST available.\nreset_config trst_and_srst\n\n# the only possible transport is JTAG\ntransport select jtag\n\n# iMX6Q POR gates JTAG and the chip is completely incommunicado\n# over JTAG for at least 10ms after nSRST is deasserted\nadapter srst delay 11\n\n# Source generic iMX6Q target configuration\nset CHIPNAME imx6q\nsource [find target/imx6.cfg]\n\n# function to apply initial configuration after a reset. It\n# provides a basic pad configuration and also DDR memory and clocks\n# sufficient to load and execute a boot loader (e.g. barebox) from\n# DDR memory. This list is extracted from the barebox flash image\n# header.\nproc apply_dcd { } {\n\tmww 0x020e05a8 0x00000030\n\tmww 0x020e05b0 0x00000030\n\tmww 0x020e0524 0x00000030\n\tmww 0x020e051c 0x00000030\n\tmww 0x020e0518 0x00000030\n\tmww 0x020e050c 0x00000030\n\tmww 0x020e05b8 0x00000030\n\tmww 0x020e05c0 0x00000030\n\tmww 0x020e05ac 0x00020030\n\tmww 0x020e05b4 0x00020030\n\tmww 0x020e0528 0x00020030\n\tmww 0x020e0520 0x00020030\n\tmww 0x020e0514 0x00020030\n\tmww 0x020e0510 0x00020030\n\tmww 0x020e05bc 0x00020030\n\tmww 0x020e05c4 0x00020030\n\tmww 0x020e056c 0x00020030\n\tmww 0x020e0578 0x00020030\n\tmww 0x020e0588 0x00020030\n\tmww 0x020e0594 0x00020030\n\tmww 0x020e057c 0x00020030\n\tmww 0x020e0590 0x00003000\n\tmww 0x020e0598 0x00003000\n\tmww 0x020e058c 0x00000000\n\tmww 0x020e059c 0x00003030\n\tmww 0x020e05a0 0x00003030\n\tmww 0x020e0784 0x00000030\n\tmww 0x020e0788 0x00000030\n\tmww 0x020e0794 0x00000030\n\tmww 0x020e079c 0x00000030\n\tmww 0x020e07a0 0x00000030\n\tmww 0x020e07a4 0x00000030\n\tmww 0x020e07a8 0x00000030\n\tmww 0x020e0748 0x00000030\n\tmww 0x020e074c 0x00000030\n\tmww 0x020e0750 0x00020000\n\tmww 0x020e0758 0x00000000\n\tmww 0x020e0774 0x00020000\n\tmww 0x020e078c 0x00000030\n\tmww 0x020e0798 0x000c0000\n\tmww 0x021b081c 0x33333333\n\tmww 0x021b0820 0x33333333\n\tmww 0x021b0824 0x33333333\n\tmww 0x021b0828 0x33333333\n\tmww 0x021b481c 0x33333333\n\tmww 0x021b4820 0x33333333\n\tmww 0x021b4824 0x33333333\n\tmww 0x021b4828 0x33333333\n\tmww 0x021b0018 0x00081740\n\tmww 0x021b001c 0x00008000\n\tmww 0x021b000c 0x555a7975\n\tmww 0x021b0010 0xff538e64\n\tmww 0x021b0014 0x01ff00db\n\tmww 0x021b002c 0x000026d2\n\tmww 0x021b0030 0x005b0e21\n\tmww 0x021b0008 0x09444040\n\tmww 0x021b0004 0x00025576\n\tmww 0x021b0040 0x00000027\n\tmww 0x021b0000 0x831a0000\n\tmww 0x021b001c 0x04088032\n\tmww 0x021b001c 0x0408803a\n\tmww 0x021b001c 0x00008033\n\tmww 0x021b001c 0x0000803b\n\tmww 0x021b001c 0x00428031\n\tmww 0x021b001c 0x00428039\n\tmww 0x021b001c 0x09408030\n\tmww 0x021b001c 0x09408038\n\tmww 0x021b001c 0x04008040\n\tmww 0x021b001c 0x04008048\n\tmww 0x021b0800 0xa1380003\n\tmww 0x021b4800 0xa1380003\n\tmww 0x021b0020 0x00005800\n\tmww 0x021b0818 0x00022227\n\tmww 0x021b4818 0x00022227\n\tmww 0x021b083c 0x434b0350\n\tmww 0x021b0840 0x034c0359\n\tmww 0x021b483c 0x434b0350\n\tmww 0x021b4840 0x03650348\n\tmww 0x021b0848 0x4436383b\n\tmww 0x021b4848 0x39393341\n\tmww 0x021b0850 0x35373933\n\tmww 0x021b4850 0x48254A36\n\tmww 0x021b080c 0x001f001f\n\tmww 0x021b0810 0x001f001f\n\tmww 0x021b480c 0x00440044\n\tmww 0x021b4810 0x00440044\n\tmww 0x021b08b8 0x00000800\n\tmww 0x021b48b8 0x00000800\n\tmww 0x021b001c 0x00000000\n\tmww 0x021b0404 0x00011006\n\tmww 0x020c4068 0x00c03f3f\n\tmww 0x020c406c 0x0030fc03\n\tmww 0x020c4070 0x0fffc000\n\tmww 0x020c4074 0x3ff00000\n\tmww 0x020c4078 0x00fff300\n\tmww 0x020c407c 0x0f0000c3\n\tmww 0x020c4080 0x000003ff\n\tmww 0x020e0010 0xf00000cf\n\tmww 0x020e0018 0x007f007f\n\tmww 0x020e001c 0x007f007f\n}\n\n# disable watchdog\nproc disable_wdog { } {\n\tmwh 0x020bc000 0x30\n}\n\n# This function applies the initial configuration after a \"reset init\"\n# command\nproc imx6q_sabresd_init { } {\n\tdisable_wdog\n\tapply_dcd\n}\n\n# prevent cortex-a code from asserting SRST again\n$_TARGETNAME.0 configure -event reset-assert { }\n# hook the init function into the reset-init event\n$_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init }\n# set a slow default JTAG clock, can be overridden later\nadapter speed 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/gatemate_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# GateMateTM FPGA Evaluation Board\n# https://www.colognechip.com/programmable-logic/gatemate-evaluation-board/\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n\nftdi channel 0\nftdi layout_init 0x0014 0x011b\nreset_config none\ntransport select jtag\nadapter speed 6000\n\nsource [find fpga/gatemate.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/glyn_tonga2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9)\n#\n# http://toshiba-mikrocontroller.de/sites/TMPA900CPUBOARDStarter.htm\n#\n# Hardware on the S0-DIMM module:\n#   - Toshiba TMPA900CMXBG (ARM9, ARM926EJ-S, max. 200MHz)\n#   - DDR SDRAM: Hynix H5MS5162DFR-J3M (64Mbyte, x16, 1.8V, 166/83MHz at CL3/2)\n#   - NAND flash: Samsung K9F2G08U0B-PIB0 (256M x 8 Bit, 3.3V)\n#   - Ethernet: SMSC LAN9221I-ABZJ (10/100Mbit, Non-PCI, 16 bit interface)\n#\n\nsource [find target/tmpa900.cfg]\n\n########################\n# Target configuration #\n########################\n\n# Initial JTAG speed should not exceed 1/6 of the initial CPU clock\n# frequency (24MHz). Be conservative and use 1/8 of the frequency.\n# (24MHz / 8 = 3MHz)\nadapter speed 3000\n\n$_TARGETNAME configure -event reset-start {\n\t# Upon reset, set the JTAG frequency to 3MHz again, see above.\n\techo \"Setting JTAG speed to 3MHz until clocks are initialized.\"\n\tadapter speed 3000\n\n\t# Halt the CPU.\n\thalt\n\n\t# Disable faster memory access for now.\n\tarm7_9 fast_memory_access disable\n}\n\n$_TARGETNAME configure -event reset-init {\n\t# Setup clocks, and initialize SRAM and DDR SDRAM.\n\ttonga2_init\n\n\t# At this point the CPU is running at 192MHz, increase JTAG speed.\n\t# Tests showed that 15MHz works OK, higher speeds can cause problems,\n\t# though. Not sure if this is a CPU issue or JTAG adapter issue.\n\techo \"Increasing JTAG speed to 15MHz.\"\n\tadapter speed 15000\n\n\t# Enable faster memory access.\n\tarm7_9 fast_memory_access enable\n}\n\nproc tonga2_init { } {\n\t######################\n\t# PLL initialization #\n\t######################\n\n\t# Clock overview (see datasheet chapter 3.5.2, page 57):\n\t#   - fs: Low-frequency oscillator\n\t#   - fOSCH: High-frequency oscillator (24MHz on this board)\n\t#   - fPLL = fOSCH * multiplier (where multiplier can be 6 or 8)\n\t#   - fFCLK = fPLL / gear (where gear can be 1/2/4/8)\n\t#   - fHCLK is always fFCLK/2. fPCLK is also fFCLK/2.\n\t#\n\t# We select multiplier = 8 and gear = 1, so\n\t#   fFCLK = fOSCH * 8 / 1 = 192MHz.\n\n\t# SYSCR3 (System Control Register 3): Disable and configure PLL.\n\t#   - PLL operation control: off\n\t#   - PLL constant value setting 1: always 0, as per datasheet\n\t#   - PLL constant value setting 2: x8 (multiplier = 8)\n\tmww 0xf005000c 0x00000007\n\n\t# SYSCR4 (System Control Register 4): Configure PLL.\n\t#   - PLL constant value setting 3: 140MHz or more\n\t#   - PLL constant value setting 4: always 1, as per datasheet\n\t#   - PLL constant value setting 5: 140MHz or more\n\tmww 0xf0050010 0x00000065\n\n\t# SYSCR3 (System Control Register 3): Enable PLL.\n\t#   - PLL operation control: on\n\t#   - All other bits remain set as above.\n\tmww 0xf005000c 0x00000087\n\n\t# Wait for PLL to stabilize.\n\tsleep 10\n\n\t# SYSCR2 (System Control Register 2): Switch from fOSCH to fPLL.\n\t#   - Selection of the PLL output clock: fPLL\n\tmww 0xf0050008 0x00000002\n\n\t# SYSCR1 (System Control Register 1):\n\t#   - Clock gear programming: fc/1 (i.e., gear = 1, don't divide).\n\tmww 0xf0050004 0x00000000\n\n\t# CLKCR5 (Clock Control Register 5): Set bits 3 and 6. The datasheet\n\t# says the bits are reserved, but also recommends \"Write as one\".\n\tmww 0xf0050054 0x00000048\n\n\n\t##############################################################\n\t# Dynamic Memory Controller (DMC) / DDR SDRAM initialization #\n\t##############################################################\n\n\t# PMC (Power Management Controller):\n\t# PMCDRV (External Port \"Driverbility\" control register):\n\t# Bits DRV_MEM0/DRV_MEM1 (memory relation port drive power):\n\tmww 0xf0020260 0x00000003\t;# Select 1.8V +/- 0.1V\n\n\t# Setup DDR SDRAM timing parameters for our specific chip.\n\tmww 0xf4310014 0x00000004\t;# cas_latency = 2\n\tmww 0xf4310018 0x00000001\t;# t_dqss = 1\n\tmww 0xf431001c 0x00000002\t;# t_mrd = 2\n\tmww 0xf4310020 0x0000000a\t;# t_ras = 10\n\tmww 0xf4310024 0x0000000a\t;# t_rc = 10\n\tmww 0xf4310028 0x00000013\t;# t_rcd = 3, schedule_rcd = 2\n\tmww 0xf431002c 0x0000010a\t;# t_rfc = 10, schedule_rfc = 8\n\tmww 0xf4310030 0x00000013\t;# t_rp = 3, schedule_rp = 2\n\tmww 0xf4310034 0x00000002\t;# t_rrd = 2\n\tmww 0xf4310038 0x00000002\t;# t_wr = 2\n\tmww 0xf431003c 0x00000001\t;# t_wtr = 1\n\tmww 0xf4310040 0x0000000a\t;# t_xp = 10\n\tmww 0xf4310044 0x0000000c\t;# t_xsr = 12\n\tmww 0xf4310048 0x00000014\t;# t_esr = 20\n\n\t# dmc_memory_cfg_5 (DMC Memory Configuration register):\n\t# Set memory configuration:\n\t# column_bits = 10, row_bits = 13, ap-bit = 10, power_down_prd = 0,\n\t# auto_power_down = disable, stop_mem_clock = disable, memory_burst = 4\n\tmww 0xf431000c 0x00010012\n\n\t# dmc_user_config_5 (DMC user_config register):\n\t# Data bus width of DDR SDRAM: 16 bit\n\tmww 0xf4310304 0x00000058\n\n\t# dmc_refresh_prd_5 (DMC Refresh Period register):\n\t# Auto refresh: every 2656 (0xa60) DMCSCLK periods.\n\tmww 0xf4310010 0x00000a60\n\n\t# dmc_chip_0_cfg_5 (DMC chip_0_cfg registers):\n\t#   - SDRAM address structure: bank, row, column\n\t#   - address_match = 01000000 (start address [31:24])\n\t#   - address_mask  = 11111100 (start address [31:24] mask value)\n\tmww 0xf4310200 0x000140fc\n\n\t# Initialize the DDR SDRAM chip.\n\t# dmc_direct_cmd_5 (DMC Direct Command register).\n\t# See datasheet chapter 3.10.5.1, page 268.\n\tmww 0xf4310008 0x000c0000\t;# RAM init: NOP\n\tmww 0xf4310008 0x00000000\t;# RAM init: Precharge all\n\tmww 0xf4310008 0x00040000\t;# RAM init: Autorefresh\n\tmww 0xf4310008 0x00040000\t;# RAM init: Autorefresh\n\tmww 0xf4310008 0x00080032\t;# RAM init: addr_13_to_0 = 0x32\n\tmww 0xf4310008 0x000c0000\t;# RAM init: NOP\n\tmww 0xf4310008 0x000a0000\t;# RAM init: bank_addr = bank 2\n\n\t# dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg registers):\n\t# Set min./max. QoS values.\n\t#   - 0x5: Enable QoS, max. QoS = 1\n\t#   - 0xb: Enable QoS, min. QoS = 2\n\tmww 0xf4310100 0x00000005\t;# AHB0: CPU Data\n\tmww 0xf4310104 0x00000005\t;# AHB1: CPU Inst\n\tmww 0xf4310108 0x0000000b\t;# AHB2: LCDC\n\tmww 0xf431010c 0x00000005\t;# AHB3: LCDDA, USB\n\tmww 0xf4310110 0x00000005\t;# AHB4: DMA1\n\tmww 0xf4310114 0x00000005\t;# AHB5: DMA2\n\n\t# dmc_memc_cmd_5 (DMC Memory Controller Command register):\n\t# Change DMC state to ready.\n\tmww 0xf4310004 0x00000000\t;# memc_cmd = \"Go\"\n\n\t# EBI: SMC Timeout register\n\tmww 0xf00a0050 0x00000001\t;# smc_timeout = 1\n\n\n\t########################################################\n\t# Static Memory Controller (SMC) / SRAM initialization #\n\t########################################################\n\n\t# smc_set_cycles_5 (SMC Set Cycles register):\n\t# tRC = 10, tWC = 10, tCEOE = 7, tWP = 5, tPC=2, tTR=2\n\tmww 0xf4311014 0x0004afaa\n\n\t# smc_set_opmode_5 (SMC Set Opmode register):\n\t# Memory data bus width = 16 bits, async read mode, read burst\n\t# length = 1 beat, async write mode, write burst length = 1 beat,\n\t# byte enable (SMCBE0-1) timing = SMCCSn timing, memory burst boundary\n\t# split setting = burst can cross any address boundary\n\tmww 0xf4311018 0x00000001\n\n\t# smc_direct_cmd_5 (SMC Direct Command register):\n\t# cmd_type = UpdateRegs, chip_select = CS1\n\tmww 0xf4311010 0x00c00000\n\n\techo \"Clocks, SRAM, and DDR SDRAM are now initialized.\"\n}\n\n#######################\n# Flash configuration #\n#######################\n\n# TODO: Implement NAND support.\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/gowin_runber.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Gowin RUNBER FPGA Development Board\n# https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n\nftdi channel 0\nftdi layout_init 0x0008 0x008b\nreset_config none\ntransport select jtag\nadapter speed 6000\n\nsource [find fpga/gowin_gw1n.cfg]\n\n\n#openocd -f board/gowin_runber.cfg  -c \"init\" -c \"pld load 0 impl/pnr/gw1n_blinker.fs\"\n#ipdbg -start -tap gw1n.tap -hub 0x42 -port 5555 -tool 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/gti/espressobin.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# config for ESPRESSObin from\n# Globalscale Technologies Inc.\n\n# srst is isolated through missing resistor\nreset_config trst_only\n\nsource [find target/marvell/88f3720.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/gumstix-aerocore.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# JTAG for the STM32F4x chip used on the Gumstix AeroCore is available on\n# the first interface of a Quad FTDI chip.  nTRST is bit 4.\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6011\n\nftdi layout_init 0x0000 0x001b\nftdi layout_signal nTRST -data 0x0010\n\nsource [find target/stm32f4x.cfg]\nreset_config trst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hammer.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Target Configuration for the TinCanTools S3C2410 Based Hammer Module\n# http://www.tincantools.com\n\nsource [find target/samsung_s3c2410.cfg]\n\n$_TARGETNAME configure -event reset-init {\n\t# Reset Script for the TinCanTools S3C2410 Based Hammer Module\n\t# http://www.tincantools.com\n\t#\n\t# Setup primary clocks and initialize the SDRAM\n\tmww 0x53000000 0x00000000\n\tmww 0x4a000008 0xffffffff\n\tmww 0x4a00000c 0x000007ff\n\tmww 0x4c000000 0x00ffffff\n\tmww 0x4c000014 0x00000003\n\tmww 0x4c000004 0x000a1031\n\tmww 0x48000000 0x11111122\n\tmww 0x48000004 0x00000700\n\tmww 0x48000008 0x00000700\n\tmww 0x4800000c 0x00000700\n\tmww 0x48000010 0x00000700\n\tmww 0x48000014 0x00000700\n\tmww 0x48000018 0x00000700\n\tmww 0x4800001c 0x00018005\n\tmww 0x48000020 0x00018005\n\tmww 0x48000024 0x009c0459\n\tmww 0x48000028 0x000000b2\n\tmww 0x4800002c 0x00000030\n\tmww 0x48000030 0x00000030\n\tflash probe 0\n}\n\n\n#flash configuration\n#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target> [driver_options ...]\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x00000000 0x1000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hilscher_nxdb500sys.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Author: Michael Trensch (MTrensch@googlemail.com)\n################################################################################\n\nsource [find target/hilscher_netx500.cfg]\n\nreset_config trst_and_srst\nadapter srst delay 500\njtag_ntrst_delay 500\n\n$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1\n\n$_TARGETNAME configure -event reset-init {\n  halt\n\n  arm7_9 fast_memory_access enable\n  arm7_9 dcc_downloads enable\n\n  sdram_fix\n\n  puts \"Configuring SDRAM controller for paired K4S561632C (64MB) \"\n  mww 0x00100140 0\n  mww 0x00100144 0x03C13261\n  mww 0x00100140 0x030D0121\n\n  puts \"Configuring SRAM nCS0 for 150ns paired Par. Flash (x32)\"\n  mww 0x00100100 0x0201000E\n\n  flash probe 0\n}\n\n#####################\n# Flash configuration\n#####################\n\n#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>\nflash bank parflash cfi 0xC0000000 0x02000000 4 4 $_TARGETNAME\n\ninit\nreset init\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hilscher_nxeb500hmi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Author: Michael Trensch (MTrensch@googlemail.com)\n################################################################################\n\nsource [find target/hilscher_netx500.cfg]\n\nreset_config trst_and_srst\nadapter srst delay 500\njtag_ntrst_delay 500\n\n$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1\n\n$_TARGETNAME configure -event reset-init {\n  halt\n\n  arm7_9 fast_memory_access enable\n  arm7_9 dcc_downloads disable\n\n  sdram_fix\n\n  puts \"Configuring SDRAM controller for MT48LC8M32 (32MB) \"\n  mww 0x00100140 0\n  mww 0x00100144 0x03C23251\n  mww 0x00100140 0x030D0111\n\n  puts \"Configuring SRAM nCS0 for 150ns Par. Flash (x16)\"\n  mww 0x00100100 0x0101000E\n\n  flash probe 0\n}\n\n#####################\n# Flash configuration\n#####################\n\n#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>\nflash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME\n\ninit\nreset init\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hilscher_nxhx10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Author: Michael Trensch (MTrensch@googlemail.com)\n################################################################################\n\nsource [find target/hilscher_netx10.cfg]\n\n# Usually it is not needed to set srst_pulls_trst\n# but sometimes it does not work without it. If you encounter\n# problems try to line below\n# reset_config trst_and_srst srst_pulls_trst\nreset_config trst_and_srst\nadapter srst delay 500\njtag_ntrst_delay 500\n\n$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1\n\n# Par. Flash can only be accessed if DIP switch on the board is set in proper\n# position and init_sdrambus was called. Don't call these functions if the DIP\n# switch is in invalid position, as some outputs may collide. This is why this\n# function is not called automatically\nproc flash_init { } {\n  puts \"Configuring SRAM nCS0 for 90ns Par. Flash (x16)\"\n  mww 0x101C0100 0x01010008\n\n  flash probe 0\n}\n\nproc mread32 {addr} {\n  return [read_memory $addr 32 1]\n}\n\nproc init_clocks { } {\n  puts \"Enabling all clocks \"\n  set accesskey [mread32 0x101c0070]\n  mww  0x101c0070 $accesskey\n\n  mww  0x101c0028 0x00007511\n}\n\nproc init_sdrambus { } {\n  puts \"Initializing external SDRAM Bus 16 Bit \"\n  set accesskey [mread32 0x101c0070]\n  mww  0x101c0070 $accesskey\n  mww  0x101c0C40 0x00000050\n\n  puts \"Configuring SDRAM controller for K4S561632E (32MB) \"\n  mww 0x101C0140 0\n  sleep 100\n  #mww 0x101C0144 0x00a13262\n  mww 0x101C0144 0x00a13251\n  mww 0x101C0148 0x00000033\n  mww 0x101C0140 0x030d0121\n}\n\n$_TARGETNAME configure -event reset-init {\n  halt\n  wait_halt 1000\n\n  arm7_9 fast_memory_access enable\n  arm7_9 dcc_downloads enable\n\n  init_clocks\n#  init_sdrambus\n\n  puts \"\"\n  puts \"-------------------------------------------------\"\n  puts \"Call 'init_clocks' to enable all clocks\"\n  puts \"Call 'init_sdrambus' to enable external SDRAM bus\"\n  puts \"-------------------------------------------------\"\n}\n\n#####################\n# Flash configuration\n#####################\n\n#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>\n#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME\n\ninit\nreset init\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hilscher_nxhx50.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Author: Michael Trensch (MTrensch@googlemail.com)\n################################################################################\n\nsource [find target/hilscher_netx50.cfg]\n\nreset_config trst_and_srst\nadapter srst delay 500\njtag_ntrst_delay 500\n\n$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1\n\n$_TARGETNAME configure -event reset-init {\n  halt\n\n  arm7_9 fast_memory_access enable\n  arm7_9 dcc_downloads enable\n\n  sdram_fix\n\n  puts \"Configuring SDRAM controller for MT48LC2M32 (8MB) \"\n  mww 0x1C000140 0\n  mww 0x1C000144 0x00A12151\n  mww 0x1C000140 0x030D0001\n\n  puts \"Configuring SRAM nCS0 for 90ns Par. Flash (x16)\"\n  mww 0x1C000100 0x01010008\n\n  flash probe 0\n}\n\n#####################\n# Flash configuration\n#####################\n\n#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>\nflash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME\n\ninit\nreset init\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hilscher_nxhx500.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Author: Michael Trensch (MTrensch@googlemail.com)\n################################################################################\n\nsource [find target/hilscher_netx500.cfg]\n\nreset_config trst_and_srst\nadapter srst delay 500\njtag_ntrst_delay 500\n\n$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1\n\n$_TARGETNAME configure -event reset-init {\n  halt\n\n  arm7_9 fast_memory_access enable\n  arm7_9 dcc_downloads enable\n\n  sleep 100\n\n  sdram_fix\n\n  puts \"Configuring SDRAM controller for MT48LC2M32 (8MB) \"\n  mww 0x00100140 0\n  mww 0x00100144 0x03C23251\n  mww 0x00100140 0x030D0001\n\n  puts \"Configuring SRAM nCS0 for 90ns Par. Flash (x16)\"\n  mww 0x00100100 0x01010008\n\n  flash probe 0\n}\n\n#####################\n# Flash configuration\n#####################\n\n#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>\nflash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME\n\ninit\nreset init\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hilscher_nxsb100.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Author: Michael Trensch (MTrensch@googlemail.com)\n################################################################################\n\nsource [find target/hilscher_netx500.cfg]\n\nreset_config trst_and_srst\nadapter srst delay 500\njtag_ntrst_delay 500\n\n$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1\n\n$_TARGETNAME configure -event reset-init {\n  halt\n\n  arm7_9 fast_memory_access enable\n  arm7_9 dcc_downloads enable\n\n  sdram_fix\n\n  puts \"Configuring SDRAM controller for MT48LC2M32 (8MB) \"\n  mww 0x00100140 0\n  mww 0x00100144 0x03C23251\n  mww 0x00100140 0x030D0001\n\n}\n\ninit\nreset init\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hitex_lpc1768stick.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Hitex LPC1768 Stick\n#\n# http://www.hitex.com/?id=1602\n#\n\nreset_config trst_and_srst\n\nsource [find interface/ftdi/hitex_lpc1768stick.cfg]\n\nsource [find target/lpc17xx.cfg]\n\n\n# startup @ 500kHz\nadapter speed 500\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hitex_lpc2929.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Hitex eval board for LPC2929/LPC2939\n# http://www.hitex.com/\n\n# Delays on reset lines\nadapter srst delay 50\njtag_ntrst_delay 1\n\n# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).\n# Adaptive clocking through RTCK is not supported.\nadapter speed 2000\n\n# Target device: LPC29xx with ETB\n# The following variables are used by the LPC2900 script:\n#   HAS_ETB             Must be set to 1. The CPU on this board has ETB.\n#   FLASH_CLOCK         CPU frequency at the time of flash programming (in kHz)\nset HAS_ETB             1\nset FLASH_CLOCK         112000\nsource [find target/lpc2900.cfg]\n\n# A working area will help speeding the flash programming\n#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0\n$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0\n\n# Event handlers\n$_TARGETNAME configure -event reset-start {\n  # Back to the slow JTAG clock\n  adapter speed 2000\n}\n\n# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)\nset _FLASHNAME $_CHIPNAME.extflash\nflash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe\n\n\n$_TARGETNAME configure -event reset-init {\n  # Flash\n  mww 0x20200010 0x00000007     ;# FBWST: 7 wait states, not cached\n\n  # Use PLL\n  mww 0xFFFF8020 0x00000001     ;# XTAL_OSC_CONTROL: enable, 1-20 MHz\n  mww 0xFFFF8070 0x01000000     ;# SYS_CLK_CONF: Crystal\n  mww 0xFFFF8028 0x00000005     ;# PLL: (power down)\n  mww 0xFFFF8028 0x01060004     ;# PLL: M=7, 2P=2 (power up)\n                                 # --> f=112 MHz, fcco=224 MHz\n  sleep 100\n  mww 0xFFFF8070 0x02000000     ;# SYS_CLK_CONF: PLL\n\n  # Increase JTAG speed\n  adapter speed 6000\n\n  # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)\n  mww 0xE0001138 0x0000001F     ;# P1.14 = D0\n  mww 0xE000113C 0x0000001F     ;# P1.15 = D1\n  mww 0xE0001140 0x0000001F     ;# P1.16 = D2\n  mww 0xE0001144 0x0000001F     ;# P1.17 = D3\n  mww 0xE0001148 0x0000001F     ;# P1.18 = D4\n  mww 0xE000114C 0x0000001F     ;# P1.19 = D5\n  mww 0xE0001150 0x0000001F     ;# P1.20 = D6\n  mww 0xE0001154 0x0000001F     ;# P1.21 = D7\n  mww 0xE0001200 0x0000001F     ;# P2.0  = D8\n  mww 0xE0001204 0x0000001F     ;# P2.1  = D9\n  mww 0xE0001208 0x0000001F     ;# P2.2  = D10\n  mww 0xE000120C 0x0000001F     ;# P2.3  = D11\n  mww 0xE0001210 0x0000001F     ;# P2.4  = D12\n  mww 0xE0001214 0x0000001F     ;# P2.5  = D13\n  mww 0xE0001218 0x0000001F     ;# P2.6  = D14\n  mww 0xE000121C 0x0000001F     ;# P2.7  = D15\n  mww 0xE0001104 0x00000007     ;# P1.1  = A1\n  mww 0xE0001108 0x00000007     ;# P1.2  = A2\n  mww 0xE000110C 0x00000007     ;# P1.3  = A3\n  mww 0xE0001110 0x00000007     ;# P1.4  = A4\n  mww 0xE0001114 0x00000007     ;# P1.5  = A5\n  mww 0xE0001118 0x00000007     ;# P1.6  = A6\n  mww 0xE000111C 0x00000007     ;# P1.7  = A7\n  mww 0xE0001028 0x00000007     ;# P0.10 = A8\n  mww 0xE000102C 0x00000007     ;# P0.11 = A9\n  mww 0xE0001030 0x00000007     ;# P0.12 = A10\n  mww 0xE0001034 0x00000007     ;# P0.13 = A11\n  mww 0xE0001038 0x00000007     ;# P0.14 = A12\n  mww 0xE000103C 0x00000007     ;# P0.15 = A13\n  mww 0xE0001048 0x00000007     ;# P0.18 = A14\n  mww 0xE000104C 0x00000007     ;# P0.19 = A15\n  mww 0xE0001050 0x00000007     ;# P0.20 = A16\n  mww 0xE0001054 0x00000007     ;# P0.21 = A17\n  mww 0xE0001058 0x00000007     ;# P0.22 = A18\n  mww 0xE000105C 0x00000007     ;# P0.23 = A19\n  mww 0xE0001238 0x00000007     ;# P2.14 = BLS0\n  mww 0xE000123C 0x00000007     ;# P2.15 = BLS1\n  mww 0xE0001300 0x00000007     ;# P3.0  = CS6\n  mww 0xE0001304 0x00000007     ;# P3.1  = CS7\n  mww 0xE0001130 0x00000007     ;# P1.12 = OE_N\n  mww 0xE0001134 0x00000007     ;# P1.13 = WE_N\n  mww 0x600000BC 0x00000041     ;# Bank6 16-bit mode, RBLE=1\n  mww 0x600000B4 0x00000000     ;# Bank6 WSTOEN=0\n  mww 0x600000AC 0x00000005     ;# Bank6 WST1=5\n  mww 0x600000B8 0x00000001     ;# Bank6 WSTWEN=1\n  mww 0x600000B0 0x00000006     ;# Bank6 WST2=6\n  mww 0x600000A8 0x00000002     ;# Bank6 IDCY=2\n  mww 0x600000D8 0x00000041     ;# Bank7 16-bit mode, RBLE=1\n  mww 0x600000D0 0x00000000     ;# Bank7 WSTOEN=0\n  mww 0x600000C8 0x0000000A     ;# Bank7 WST1=10\n  mww 0x600000D4 0x00000001     ;# Bank7 WSTWEN=1\n  mww 0x600000CC 0x0000000C     ;# Bank7 WST2=8\n  mww 0x600000C4 0x00000002     ;# Bank7 IDCY=2\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hitex_stm32-performancestick.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Hitex stm32 performance stick\n\nreset_config trst_and_srst\n\nsource [find interface/ftdi/stm32-stick.cfg]\n\nset  CHIPNAME stm32_hitex\nsource [find target/stm32f1x.cfg]\n\n# configure str750 connected to jtag chain\n# FIXME -- source [find target/str750.cfg] after cleaning that up\njtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041\n\n# for some reason this board like to startup @ 500kHz\nadapter speed 500\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/hitex_str9-comstick.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Hitex STR9-comStick\n# http://www.hitex.com/index.php?id=383\n# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.\n\nsource [find interface/ftdi/hitex_str9-comstick.cfg]\n\n# set jtag speed\nadapter speed 3000\n\nadapter srst delay 100\njtag_ntrst_delay 100\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config trst_and_srst\n\n#\n# FIXME use the standard str912 target config; that script might need\n# updating to \"-ignore-version\" for the boundary scan TAP\n#\n#\tsource [find target/str912.cfg]\n#\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME str912\n}\n\nif { [info exists ENDIAN] } {\n   set  _ENDIAN $ENDIAN\n} else {\n   set  _ENDIAN little\n}\n\nif { [info exists FLASHTAPID] } {\n   set _FLASHTAPID $FLASHTAPID\n} else {\n   set _FLASHTAPID 0x04570041\n}\njtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x25966041\n}\njtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nif { [info exists BSTAPID] } {\n   set _BSTAPID $BSTAPID\n} else {\n   # Found on STR9-comStick, revision STR912CS-A1\n   set _BSTAPID1 0x1457f041\n   # Found on STR9-comStick, revision STR912CS-A2\n   set _BSTAPID2 0x2457f041\n}\njtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-init {\n\t# We can increase speed now that we know the target is halted.\n\t#jtag_rclk 3000\n\n\t# -- Enable 96K RAM\n\t# PFQBC enabled / DTCM & AHB wait-states disabled\n\tmww 0x5C002034 0x0191\n\n\tstr9x flash_config 0 4 2 0 0x80000\n\tflash protect 0 0 7 off\n}\n\n$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0\n\n#flash bank <driver> <base> <size> <chip_width> <bus_width>\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/iar_lpc1768.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Board from IAR KickStart Kit for LPC1768\n# See www.iar.com and also\n# http://www.olimex.com/dev/lpc-1766stk.html\n#\n\nsource [find target/lpc17xx.cfg]\n\n# The chip has just been reset.\n#\n$_TARGETNAME configure -event reset-init {\n\t# FIXME update the core clock to run at 100 MHz;\n\t# and update JTAG clocking similarly; then\n\t# make CCLK match,\n\n\tflash probe 0\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/iar_str912_sk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The IAR str912-sk evaluation kick start board has an str912\n\nsource [find target/str912.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/icnova_imx53_sodimm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#################################################################################################\n# Author: Benjamin Tietz <benjamin.tietz@in-circuit.de>                                        ;#\n# based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com>   ;#\n# Kiwigrid GmbH                                                                                ;#\n# Generated for In-Circuit i.MX53 SO-Dimm                                                      ;#\n#################################################################################################\n\n# The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip\nsource [find target/imx53.cfg]\n# Helper for common memory read/modify/write procedures\nsource [find mem_helper.tcl]\n\necho \"i.MX53 SO-Dimm board lodaded.\"\n\n# Set reset type\n#reset_config srst_only\n\nadapter speed 3000\n\n# Slow speed to be sure it will work\njtag_rclk 1000\n$_TARGETNAME configure -event \"reset-start\" { jtag_rclk 1000 }\n\n$_TARGETNAME configure -event \"reset-assert\" {\n\techo \"Resetting ....\"\n\t#cortex_a dbginit\n}\n\n$_TARGETNAME configure -event reset-init { sodimm_init }\n\nglobal AIPS1_BASE_ADDR\nset AIPS1_BASE_ADDR     0x53F00000\nglobal AIPS2_BASE_ADDR\nset AIPS2_BASE_ADDR     0x63F00000\n\nproc sodimm_init { } {\n\techo \"Reset-init...\"\n\t; # halt the CPU\n\thalt\n\n\techo \"HW version [format %x [mrw 0x48]]\"\n\n\tdap apsel 1\n\tDCD\n\n\t; # ARM errata ID #468414\n\tset tR [arm mrc 15 0 1 0 1]\n\tarm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]\t; # enable L1NEON bit\n\n\tinit_l2cc\n\tinit_aips\n\tinit_clock\n\n\tdap apsel 0\n\n\t; # Force ARM state\n\t; #reg cpsr 0x000001D3\n\tarm core_state arm\n\n\tjtag_rclk 3000\n#\tadapter speed 3000\n}\n\n\n# L2CC Cache setup/invalidation/disable\nproc init_l2cc { } {\n\t; #/* explicitly disable L2 cache */\n\t; #mrc 15, 0, r0, c1, c0, 1\n\tset tR [arm mrc 15 0 1 0 1]\n\t; #bic r0, r0, #0x2\n\t; #mcr 15, 0, r0, c1, c0, 1\n\tarm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]\n\n\t; #/* reconfigure L2 cache aux control reg */\n\t; #mov r0, #0xC0                   /* tag RAM */\n\t; #add r0, r0, #0x4                /* data RAM */\n\t; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */\n\t; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */\n\t; #orr r0, r0, #(1 << 22)          /* disable write allocate */\n\n\t; #mcr 15, 1, r0, c9, c0, 2\n\tarm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]\n}\n\n\n# AIPS setup - Only setup MPROTx registers.\n# The PACR default values are good.\nproc init_aips { } {\n\t; # Set all MPROTx to be non-bufferable, trusted for R/W,\n\t; # not forced to user-mode.\n\tglobal AIPS1_BASE_ADDR\n\tglobal AIPS2_BASE_ADDR\n\tset VAL\t\t\t0x77777777\n\n#\tdap apsel 1\n\tmww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL\n\tmww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL\n\tmww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL\n\tmww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL\n#\tdap apsel 0\n}\n\n\nproc init_clock { } {\n\tglobal AIPS1_BASE_ADDR\n\tglobal AIPS2_BASE_ADDR\n\tset CCM_BASE_ADDR\t[expr {$AIPS1_BASE_ADDR + 0x000D4000}]\n\tset CLKCTL_CCSR         0x0C\n\tset CLKCTL_CBCDR\t0x14\n\tset CLKCTL_CBCMR        0x18\n\tset PLL1_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x00080000}]\n\tset PLL2_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x00084000}]\n\tset PLL3_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x00088000}]\n\tset PLL4_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x0008C000}]\n\tset CLKCTL_CSCMR1\t0x1C\n\tset CLKCTL_CDHIPR\t0x48\n\tset PLATFORM_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x000A0000}]\n\tset CLKCTL_CSCDR1\t0x24\n\tset CLKCTL_CCDR\t\t0x04\n\n\t; # Switch ARM to step clock\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4\n\n\treturn\n\techo \"not returned\"\n\tsetup_pll $PLL1_BASE_ADDR 800\n\tsetup_pll $PLL3_BASE_ADDR 400\n\n\t; # Switch peripheral to PLL3\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]\n\twhile {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }\n\n\tsetup_pll $PLL2_BASE_ADDR 400\n\n\t; # Switch peripheral to PLL2\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]\n\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154\n\n\t; # change uart clk parent to pll2\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]\n\n\t; # make sure change is effective\n\twhile {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }\n\n\tsetup_pll $PLL3_BASE_ADDR 216\n\n\tsetup_pll $PLL4_BASE_ADDR 455\n\n\t; # Set the platform clock dividers\n\tmww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124\n\n\tmww [expr {$CCM_BASE_ADDR + 0x10}] 0\n\n\t; # Switch ARM back to PLL 1.\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0\n\n\t; # make uart div=6\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]\n\n\t; # Restore the default values in the Gate registers\n\tmww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF\n\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000\n\n\t; # for cko - for ARM div by 8\n\tmww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]\n}\n\n\nproc setup_pll { PLL_ADDR CLK } {\n\tset PLL_DP_CTL\t\t0x00\n\tset PLL_DP_CONFIG   \t0x04\n\tset PLL_DP_OP\t\t0x08\n\tset PLL_DP_HFS_OP\t0x1C\n\tset PLL_DP_MFD\t\t0x0C\n\tset PLL_DP_HFS_MFD\t0x20\n\tset PLL_DP_MFN\t\t0x10\n\tset PLL_DP_HFS_MFN\t0x24\n\n\tif {$CLK == 1000} {\n\t\tset DP_OP\t[expr {(10 << 4) + ((1 - 1) << 0)}]\n\t\tset DP_MFD\t[expr {12 - 1}]\n\t\tset DP_MFN\t5\n\t} elseif {$CLK == 850} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {48 - 1}]\n\t\tset DP_MFN\t41\n\t} elseif {$CLK == 800} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {3 - 1}]\n\t\tset DP_MFN\t1\n\t} elseif {$CLK == 700} {\n\t\tset DP_OP\t[expr {(7 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {24 - 1}]\n\t\tset DP_MFN\t7\n\t} elseif {$CLK == 600} {\n\t\tset DP_OP\t[expr {(6 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {4 - 1}]\n\t\tset DP_MFN\t1\n\t} elseif {$CLK == 665} {\n\t\tset DP_OP\t[expr {(6 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {96 - 1}]\n\t\tset DP_MFN\t89\n\t} elseif {$CLK == 532} {\n\t\tset DP_OP\t[expr {(5 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {24 - 1}]\n\t\tset DP_MFN\t13\n\t} elseif {$CLK == 455} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((2 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {48 - 1}]\n\t\tset DP_MFN\t71\n\t} elseif {$CLK == 400} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((2 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {3 - 1}]\n\t\tset DP_MFN\t1\n\t} elseif {$CLK == 216} {\n\t\tset DP_OP\t[expr {(6 << 4) + ((3 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {4 - 1}]\n\t\tset DP_MFN\t3\n\t} else {\n\t\terror \"Error (setup_dll): clock not found!\"\n\t}\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232\n\tmww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP\n\tmww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD\n\tmww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN\n\tmww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232\n\twhile {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }\n}\n\n\nproc CPU_2_BE_32 { L } {\n\treturn [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]\n}\n\n\n# Device Configuration Data\nproc DCD { } {\n#\tdap apsel 1\n#*========================================================================================== ======\n# Initialization script for 32 bit DDR3 (CS0+CS1)\n#*========================================================================================== ======\n# Remux D24/D25 to perform Flash-access\n\tmww 0x53fa818C 0x00000000 ; #EIM_RW\n\tmww 0x53fa8180 0x00000000 ; #EIM_CS0\n\tmww 0x53fa8188 0x00000000 ; #EIM_OE\n\tmww 0x53fa817C 0x00000000 ; #A16\n\tmww 0x53fa8178 0x00000000 ; #A17\n\tmww 0x53fa8174 0x00000000 ; #A18\n\tmww 0x53fa8170 0x00000000 ; #A19\n\tmww 0x53fa816C 0x00000000 ; #A20\n\tmww 0x53fa8168 0x00000000 ; #A21\n\tmww 0x53fa819C 0x00000000 ; #DA0\n\tmww 0x53fa81A0 0x00000000 ; #DA1\n\tmww 0x53fa81A4 0x00000000 ; #DA2\n\tmww 0x53fa81A8 0x00000000 ; #DA3\n\tmww 0x53fa81AC 0x00000000 ; #DA4\n\tmww 0x53fa81B0 0x00000000 ; #DA5\n\tmww 0x53fa81B4 0x00000000 ; #DA6\n\tmww 0x53fa81B8 0x00000000 ; #DA7\n\tmww 0x53fa81BC 0x00000000 ; #DA8\n\tmww 0x53fa81C0 0x00000000 ; #DA9\n\tmww 0x53fa81C4 0x00000000 ; #DA10\n\tmww 0x53fa81C8 0x00000000 ; #DA11\n\tmww 0x53fa81CC 0x00000000 ; #DA12\n\tmww 0x53fa81D0 0x00000000 ; #DA13\n\tmww 0x53fa81D4 0x00000000 ; #DA14\n\tmww 0x53fa81D8 0x00000000 ; #DA15\n\tmww 0x53fa8118 0x00000000 ; #D16\n\tmww 0x53fa811C 0x00000000 ; #D17\n\tmww 0x53fa8120 0x00000000 ; #D18\n\tmww 0x53fa8124 0x00000000 ; #D19\n\tmww 0x53fa8128 0x00000000 ; #D20\n\tmww 0x53fa812C 0x00000000 ; #D21\n\tmww 0x53fa8130 0x00000000 ; #D22\n\tmww 0x53fa8134 0x00000000 ; #D23\n\tmww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24\n\tmww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25\n\tmww 0x53fa8144 0x00000000 ; #D26\n\tmww 0x53fa8148 0x00000000 ; #D27\n\tmww 0x53fa814C 0x00000000 ; #D28\n\tmww 0x53fa8150 0x00000000 ; #D29\n\tmww 0x53fa8154 0x00000000 ; #D30\n\tmww 0x53fa8158 0x00000000 ; #D31\n\n# DDR3 IOMUX configuration\n#* Global pad control options */\n\tmww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3\n\tmww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3\n\tmww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2\n\tmww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1\n\tmww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2\n\tmww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency\n\tmww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS\n\tmww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency\n\tmww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0\n\tmww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0\n\tmww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0\n\tmww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS\n\tmww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1\n\tmww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1\n\tmww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS\n\tmww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL\n\tmww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE\n#\tmww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX\n\tmww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX\n\tmww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS\n\tmww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS\n\tmww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS\n\tmww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX\n\tmww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS\n\tmww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS\n#\tmww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode\n#\tmww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode\n#\tmww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE\n#\tmww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00\n\n#* Data bus byte lane pad drive strength control options */\n#\tmww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS\n#\tmww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3\n#\tmww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3\n#\tmww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS\n#\tmww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2\n#\tmww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2\n#\tmww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS\n#\tmww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1\n#\tmww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1\n#\tmww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS\n#\tmww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0\n#\tmww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0\n\n#* SDCLK pad drive strength control options */\n#\tmww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0\n#\tmww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1\n\n#* Control and addr bus pad drive strength control options */\n#\tmww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS\n#\tmww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS\n#\tmww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus\n#\tmww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE\n\n#\tmww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1\n#\tmww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0\n\n# Initialize DDR3 memory - Micron MT41J128M16-187Er\n#** Keep for now, same setting as CPU3 board **#\n\tmww 0x63fd901c 0x00008000\n#\tmww 0x63fd904c 0x01680172 ; #write leveling reg 0\n#\tmww 0x63fd9050 0x0021017f ; #write leveling reg 1\n\tmww 0x63fd9088 0x32383535 ; #read delay lines\n\tmww 0x63fd9090 0x40383538 ; #write delay lines\n#\tmww 0x63fd90F8 0x00000800 ; #Measure unit\n\tmww 0x63fd907c 0x0136014d ; #DQS gating 0\n\tmww 0x63fd9080 0x01510141 ; #DQS gating 1\n#* CPU3 Board settingr\n# Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0\n#\tmww 0x63fd9018 0x00091740 ; #Misc register:\n#* Quick Silver board setting\n# Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0\n\tmww 0x63fd9018 0x00011740 ; #Misc register\n\n# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit\n#\tmww 0x63fd9000 0xc3190000 ; #Main control register\n# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit\n\tmww 0x63fd9000 0x83190000 ; #Main control register\n# tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck\n\tmww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0\n# tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck\n\tmww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1\n# tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4\n\tmww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2\n\tmww 0x63fd902c 0x000026d2 ; #command delay (default)\n\tmww 0x63fd9030 0x009f0e21 ; #out of reset delays\n# Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values\n\tmww 0x63fd9008 0x12273030 ; #ODT timings\n# tCKE=3; tCKSRX=5; tCKSRE=5\n\tmww 0x63fd9004 0x0002002d\n#Power down control\n#**********************************\n#DDR device configuration:\n#**********************************\n#**********************************\n# CS0:\n#**********************************\n\tmww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)\n# Full array self refresh\n# Rtt_WR disabled (no ODT at IO CMOS operation)\n# Manual self refresh\n# CWS=5\n\tmww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.\n\tmww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)\n# out impedance = RZQ/7\n# Rtt_nom disabled (no ODT at IO CMOS operation)\n# Aditive latency off\n# write leveling disabled\n# tdqs (differential?) disabled\n\n\tmww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0\n\tmww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)\n#**********************************\n# CS1:\n#**********************************\n#\tmww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.\n#\tmww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.\n#\tmww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7\n#\tmww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.\n#\tmww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)\n#**********************************\n\n\n\tmww 0x63fd9020 0x00001800 ; # Refresh control register\n\tmww 0x63fd9040 0x04b80003 ; # ZQ HW control\n\tmww 0x63fd9058 0x00022227 ; # ODT control register\n\n\tmww 0x63fd901c 0x00000000\n\n# CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)\n#\tmww 0x53FA8314 = 0\n#\tmww 0x53FA8320 0x4\n#\tmww 0x53FD4060 0x01e900f0\n\n#\tdap apsel 0\n}\n\n# IRAM\n$_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1\n\nflash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME\n\n# vim:filetype=tcl\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/icnova_sam9g45_sodimm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#################################################################################################\n#\t\t\t\t\t\t\t\t\t\t\t\t                                                #\n# Author: Lars Poeschel (larsi@wh2.tu-dresden.de)\t\t\t\t\t\t\t\t\t\t\t\t#\n# Generated for In-Circuit ICnova SAM9G45 SODIMM\t\t\t\t\t\t\t\t\t\t\t\t#\n# http://www.ic-board.de/product_info.php?info=p214_ICnova-SAM9G45-SODIMM.html|ICnova\t\t\t#\n#\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t#\n#################################################################################################\n\n# FIXME use some standard target config, maybe create one from this\n#\n#\tsource [find target/...cfg]\n\nsource [find target/at91sam9g45.cfg]\n\n# Set reset type.\n# reset_config trst_and_srst\n\n# adapter srst delay 200\n# jtag_ntrst_delay 200\n\n\n# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the\n# AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has\n# some powerful features, we want to have a special function that handles \"reset init\".  To do this we declare\n# an event handler where these special activities can take place.\n\nscan_chain\n$_TARGETNAME configure -event reset-init {at91sam9g45_init}\n\n# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).\n# Slow-speed oscillator enabled at reset, so run jtag speed slow.\n$_TARGETNAME configure -event reset-start {at91sam9g45_start}\n\n\n# NandFlash configuration and definition\n# Future TBD\n# Flash configuration\n# flash bank cfi <base> <size> <chip width> <bus width> <target#>\nset _FLASHNAME $_CHIPNAME.flash\n# set _NANDNAME $_CHIPNAME.nand\nflash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME\n# nand device $_NANDNAME at91sam9 $_TARGETNAME 0x40000000 0xFFFFE800\n\n\nproc read_register {register} {\n\treturn [read_memory $register 32 1]\n}\n\nproc at91sam9g45_start { } {\n\n\t# Make sure that the the jtag is running slow, since there are a number of different ways the board\n\t# can be configured coming into this state that can cause communication problems with the jtag\n\t# adapter.  Also since this call can be made following a \"reset init\" where fast memory accesses\n\t# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower\n\t# jtag speed without causing GDB keep alive problem.\n\n\tarm7_9 fast_memory_access disable\n    # Slow-speed oscillator enabled at reset, so run jtag speed slow.\n\tadapter speed 4\n    # Make sure processor is halted, or error will result in following steps.\n\thalt\n\twait_halt 10000\n    # RSTC_MR : enable user reset.\n\tmww 0xfffffd08 0xa5000501\n}\n\n\nproc at91sam9g45_init { } {\n\n\t# At reset AT91SAM9G45 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires\n\t# a number of steps that must be carefully performed.  The process outline below follows the\n\t# recommended procedure outlined in the AT91SAM9G45 technical manual.\n\t#\n\t# Several key and very important things to keep in mind:\n\t# The SDRAM parts used currently on the board are -75 grade parts.  This\n\t# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor\n\t# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.\n\n\t# Make sure processor is halted, or error will result in following steps.\n\thalt\n\t# RSTC_MR : enable user reset.\n\tmww 0xfffffd08 0xa5000501\n\t# WDT_MR : disable watchdog.\n\tmww 0xfffffd44 0x00008000\n\n\t# Enable the main 15.000 MHz oscillator in CKGR_MOR register.\n\t# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.\n\n\tmww 0xfffffc20 0x00004001\n\twhile { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }\n\n\t# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).\n\t# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.\n\n\t#mww 0xfffffc28 0x202a3f01\n\tmww 0xfffffc28 0x20c73f03\n\twhile { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }\n\n\t# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.\n\t# Wait for MCKRDY signal from PMC_SR to assert.\n\n\t#mww 0xfffffc30 0x00000101\n\tmww 0xfffffc30 0x00001301\n\twhile { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }\n\n\t# Now change PMC_MCKR register to select PLLA.\n\t# Wait for MCKRDY signal from PMC_SR to assert.\n\n\tmww 0xfffffc30 0x00001302\n\twhile { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }\n\n\t# Processor and master clocks are now operating and stable at maximum frequency possible:\n\t#\t-> MCLK = 132.096 MHz\n\t#\t-> PCLK = 396.288 MHz\n\n\t# Switch over to adaptive clocking.\n\n\tadapter speed 6000\n\n\t# Enable faster DCC downloads.\n\n\tarm7_9 dcc_downloads enable\n\n\t# To be able to use external SDRAM, several peripheral configuration registers must\n\t# be modified.  The first change is made to PIO_ASR to select peripheral functions\n\t# for D15 through D31.  The second change is made to the PIO_PDR register to disable\n\t# this for D15 through D31.\n\n#\tmww 0xfffff870 0xffff0000\n#\tmww 0xfffff804 0xffff0000\n\n\t# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller\n\t# using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on\n\t# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.\n\n\t# mww 0xffffef1c 0x000100a\n\n\t# The ICnova SAM9G45 SODIMM has built-in NandFlash.  The exact physical timing characteristics\n\t# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting\n\t# four registers in order:  SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.\n\n\t# mww 0xffffec30 0x00020002\n\t# mww 0xffffec34 0x04040404\n\t# mww 0xffffec38 0x00070007\n\t# mww 0xffffec3c 0x00030003\n\n\t# Identify NandFlash bank 0.  Disabled at the moment because a memory driver is not yet complete.\n\n#\tnand probe 0\n\n    # SMC_SETUP0 : Setup SMC for NOR Flash\n\tmww 0xffffe800 0x0012000a\n    # SMC_PULSE0\n\tmww 0xffffe804 0x3b38343b\n    # SMC_CYCLE0\n\tmww 0xffffe808 0x003f003f\n    # SMC_MODE0\n\tmww 0xffffe80c 0x00001000\n    # Identify flash bank 0\n\tflash probe 0\n\n\t# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations\n\t# are based on 2 x Samsung K4T51083QG memory.\n\n\t# 0. Enable DDR2 Clock\n\tmww 0xfffffc00 0x4\n\t# 1. Program memory device type\n\t# 1.1 configure the DDR controller\n\tmww 0xffffe620 0x16\n\t# 1.2 program the DDR controller\n\tmww 0xffffe608 0x3d\n\n\t# 2. program memory device features\n\t# 2.1 assume timings for 7.5ns min clock period\n\tmww 0xffffe60c 0x21128226\n\t# 2.2 pSDDRC->HDDRSDRC2_T1PR\n\tmww 0xffffe610 0x02c8100e\n\t# 2.3 pSDDRC->HDDRSDRC2_T2PR\n\tmww 0xffffe614 0x01000702\n\t# 3. NOP\n\tmww 0xffffe600 0x1\n\tmww 0x70000000 0x1\n\t# 3.1 delay 200us\n\tsleep 1\n\t# jim tcl alternative: after ms\n\t# after 0.2\n\n\t# 4. NOP\n\tmww 0xffffe600 0x1\n\tmww 0x70000000 0x1\n\t# 4.1 delay 400ns\n\n\t# 5. set all bank precharge\n\tmww 0xffffe600 0x2\n\tmww 0x70000000 0x1\n\t# 5.1 delay 400ns\n\n\t# 6. set EMR operation (EMRS2)\n\tmww 0xffffe600 0x5\n\tmww 0x74000000 0x1\n\t# 6.1 delay 2 cycles\n\n\t# 7. set EMR operation (EMRS3)\n\tmww 0xffffe600 0x5\n\tmww 0x76000000 0x1\n\t# 7.1 delay 2 cycles\n\n\t# 8. set EMR operation (EMRS1)\n\tmww 0xffffe600 0x5\n\tmww 0x72000000 0x1\n\t# 8.1 delay 200 cycles (400Mhz -> 5 * 10^-7s)\n\tsleep 1\n\n\t# 9. Enable DLL Reset (set DLL bit)\n\tset CR  [expr {[read_register 0xffffe608] | 0x80}]\n\tmww 0xffffe608 $CR\n\n\t# 10. mode register cycle to reset the DLL\n\tmww 0xffffe600 0x5\n\tmww 0x70000000 0x1\n\t# 10.1 delay 2 cycles\n\n\t# 11. set all bank precharge\n\tmww 0xffffe600 0x2\n\tmww 0x70000000 0x1\n\t# 11.1 delay 400 ns\n\n\t# 12. two auto-refresh (CBR) cycles are provided.\n\tmww 0xffffe600 0x4\n\tmww 0x70000000 0x1\n\t# 12.1 delay 10 cycles\n\t# 12.2 2nd cycle (schreiben des Mode Register sparen wir uns)\n\tmww 0x70000000 0x1\n\t# 12.3 delay 10 cycles\n\n\t# 13. disable DLL reset (clear DLL bit)\n\tset CR  [expr {[read_register 0xffffe608] & 0xffffff7f}]\n\tmww 0xffffe608 $CR\n\n\t# 14. mode register set cycle\n\tmww 0xffffe600 0x3\n\tmww 0x70000000 0x1\n\n\t# 15. program OCD field (set OCD bits)\n\tset CR  [expr {[read_register 0xffffe608] | 0x7000}]\n\tmww 0xffffe608 $CR\n\n\t# 16. (EMRS1)\n\tmww 0xffffe600 0x5\n\tmww 0x72000000 0x1\n\t# 16.1 delay 2 cycles\n\n\t# 17. disable OCD field (clear OCD bits)\n\tset CR  [expr {[read_register 0xffffe608] & 0xffff8fff}]\n\tmww 0xffffe608 $CR\n\n\t# 18. (EMRS1)\n\tmww 0xffffe600 0x5\n\tmww 0x76000000 0x1\n\t# 18.1 delay 2 cycles\n\n\t# 19. normal mode command\n\tmww 0xffffe600 0x0\n\tmww 0x70000000 0x1\n\n\t# 20. perform write to any address\n\t#mww 0x70000000 0x1\n\n\t# 21. write refresh rate into the count field of the refresh rate register\n\tmww 0xffffe604 0x24b\n\t# 21.1 delay (500 * 6 cycles)\n\n\tarm7_9 fast_memory_access enable\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/imx27ads.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The IMX27 ADS eval board has a single IMX27 chip\n# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8\nsource [find target/imx27.cfg]\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { imx27ads_init }\n\n# The IMX27 ADS board has a NOR flash on CS0\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME\n\nproc imx27ads_init { } {\n\t# This setup puts RAM at 0xA0000000\n\n\t# reset the board correctly\n\treset run\n\treset halt\n\n\tmww 0x10000000 0x20040304\n\tmww 0x10020000 0x00000000\n\tmww 0x10000004 0xDFFBFCFB\n\tmww 0x10020004 0xFFFFFFFF\n\n\tsleep 100\n\n\t# ========================================\n\t#  Configure DDR on CSD0 -- initial reset\n\t# ========================================\n\tmww 0xD8001010 0x00000008\n\n\t# ========================================\n\t#  Configure PSRAM on CS5\n\t# ========================================\n\tmww 0xd8002050 0x0000dcf6\n\tmww 0xd8002054 0x444a4541\n\tmww 0xd8002058 0x44443302\n\n\t#  ========================================\n\t#         Configure16 bit NorFlash on CS0\n\t#  ========================================\n\tmww 0xd8002000 0x0000CC03\n\tmww 0xd8002004 0xa0330D01\n\tmww 0xd8002008 0x00220800\n\n\t# ========================================\n\t#  Configure CPLD on CS4\n\t# ========================================\n\tmww 0xd8002040 0x0000DCF6\n\tmww 0xd8002044 0x444A4541\n\tmww 0xd8002048 0x44443302\n\n\t# ========================================\n\t#  Configure DDR on CSD0 -- wait 5000 cycle\n\t# ========================================\n\tmww 0x10027828 0x55555555\n\tmww 0x10027830 0x55555555\n\tmww 0x10027834 0x55555555\n\tmww 0x10027838 0x00005005\n\tmww 0x1002783C 0x15555555\n\n\tmww 0xD8001010 0x00000004\n\n\tmww 0xD8001004 0x00795729\n\n\tmww 0xD8001000 0x92200000\n\tmww 0xA0000F00 0x0\n\n\tmww 0xD8001000 0xA2200000\n\tmww 0xA0000F00 0x0\n\tmww 0xA0000F00 0x0\n\n\tmww 0xD8001000 0xB2200000\n\tmwb 0xA0000033 0xFF\n\tmwb 0xA1000000 0xAA\n\n\tmww 0xD8001000 0x82228085\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/imx27lnst.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The Linuxstamp-mx27 is board has a single IMX27 chip\n# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD\nsource [find target/imx27.cfg]\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { imx27lnst_init }\n\nproc imx27lnst_init { } {\n\t# This setup puts RAM at 0xA0000000\n\n\t# reset the board correctly\n\tadapter speed 500\n\treset run\n\treset halt\n\n\tmww 0x10000000 0x20040304\n\tmww 0x10020000 0x00000000\n\tmww 0x10000004 0xDFFBFCFB\n\tmww 0x10020004 0xFFFFFFFF\n\n\tsleep 100\n\n\t# ========================================\n\t#  Configure DDR on CSD0 -- initial reset\n\t# ========================================\n\tmww 0xD8001010 0x00000008\n\n\tsleep 100\n\n\t# ========================================\n\t#  Configure DDR on CSD0 -- wait 5000 cycle\n\t# ========================================\n\tmww 0x10027828 0x55555555\n\tmww 0x10027830 0x55555555\n\tmww 0x10027834 0x55555555\n\tmww 0x10027838 0x00005005\n\tmww 0x1002783C 0x15555555\n\n\tmww 0xD8001010 0x00000004\n\n\tmww 0xD8001004 0x00795729\n\n\t#mww 0xD8001000 0x92200000\n\tmww 0xD8001000 0x91120000\n\tmww 0xA0000F00 0x0\n\n\t#mww 0xD8001000 0xA2200000\n\tmww 0xD8001000 0xA1120000\n\tmww 0xA0000F00 0x0\n\tmww 0xA0000F00 0x0\n\n\t#mww 0xD8001000 0xB2200000\n\tmww 0xD8001000 0xB1120000\n\tmwb 0xA0000033 0xFF\n\tmwb 0xA1000000 0xAA\n\n\t#mww 0xD8001000 0x82228085\n\tmww 0xD8001000 0x81128080\n\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/imx28evk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The IMX28EVK eval board has a IMX28 chip\n# Tested on SCH-26241 Rev D board with Olimex ARM-USB-OCD\n# Date:\t201-02-01\n# Authors: James Robinson & Fabio Estevam\n\nsource [find target/imx28.cfg]\n$_TARGETNAME configure -event gdb-attach { imx28evk_init }\n$_TARGETNAME configure -event reset-init { imx28evk_init }\n\nproc imx28evk_init { } {\n\n\thalt\n\n\t#****************************\n\t# VDDD setting\n\t#****************************\n\t# set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e\n\tmww 0x80044010 0x0003F503\n\tmww 0x80044040 0x0002041E\n\n\t#****************************\n\t# CLOCK set up\n\t#****************************\n\t# Power up PLL0 HW_CLKCTRL_PLL0CTRL0\n\tmww 0x80040000 0x00020000\n\t# Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0\n\t# EMI - first set DIV_EMI to div-by-2 before programming frac divider\n\tmww 0x800400F0 0x80000002\n\n\n\t# CPU: CPUFRAC=19 480*18/29=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz\n\tmww 0x800401B0 0x92921613\n\t# Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR\n\tmww 0x800401D8 0x00040080\n\t# HCLK = 227MHz,HW_CLKCTRL_HBUS DIV =0x2\n\tmww 0x80040060 0x00000002\n\n\t#****************************\n\t# POWER up DCDD_VDDA (DDR2)\n\t#****************************\n\t# Now set the voltage level to 1.8V HW_POWER_VDDACTRL bits TRC=0xC\n\tmww 0x80044050 0x0000270C\n\n\t#****************************\n\t# DDR2 DCDD_VDDA\n\t#****************************\n\t# First set up pin muxing and drive strength\n\t# Ungate module clock and bring out of reset HW_PINCTRL_CTRL_CLR\n\tmww 0x80018008 0xC0000000\n\n\t#****************************\n\t# EMI PAD setting\n\t#****************************\n\t# Set up drive strength for EMI pins\n\tmww 0x80019B80 0x00030000\n\t#IOMUXC_SW_PAD_CTL_GRP_CTLDS\n\n\t# Set up pin muxing for EMI, HW_PINCTRL_MUXSEL10, 11, 12, 13\n\tmww 0x800181A8 0xFFFFFFFF\n\tmww 0x800181B8 0xFFFFFFFF\n\tmww 0x800181C8 0xFFFFFFFF\n\tmww 0x800181D8 0xFFFFFFFF\n\n\t#** Ungate EMI clock in CCM\n\tmww 0x800400F0 0x00000002\n\n\t#============================================================================\n\t# DDR Controller Registers\n\t#============================================================================\n\t# Manufacturer:    Elpida\n\t# Device Part Number:    EDE1116AEBG\n\t# Clock Freq.:     200MHz\n\t# Density:         1Gb\n\t# Chip Selects:    1\n\t# Number of Banks: 8\n\t# Row address:     13\n\t# Column address:  10\n\t#============================================================================\n\tmww 0x800E0000 0x00000000\n\tmww 0x800E0040 0x00000000\n\tmww 0x800E0054 0x00000000\n\tmww 0x800E0058 0x00000000\n\tmww 0x800E005C 0x00000000\n\tmww 0x800E0060 0x00000000\n\tmww 0x800E0064 0x00000000\n\tmww 0x800E0068 0x00010101\n\tmww 0x800E006C 0x01010101\n\tmww 0x800E0070 0x000f0f01\n\tmww 0x800E0074 0x0102020A\n\tmww 0x800E007C 0x00010101\n\tmww 0x800E0080 0x00000100\n\tmww 0x800E0084 0x00000100\n\tmww 0x800E0088 0x00000000\n\tmww 0x800E008C 0x00000002\n\tmww 0x800E0090 0x01010000\n\tmww 0x800E0094 0x07080403\n\tmww 0x800E0098 0x06005003\n\tmww 0x800E009C 0x0A0000C8\n\tmww 0x800E00A0 0x02009C40\n\tmww 0x800E00A4 0x0002030C\n\tmww 0x800E00A8 0x0036B009\n\tmww 0x800E00AC 0x031A0612\n\tmww 0x800E00B0 0x02030202\n\tmww 0x800E00B4 0x00C8001C\n\tmww 0x800E00C0 0x00011900\n\tmww 0x800E00C4 0xffff0303\n\tmww 0x800E00C8 0x00012100\n\tmww 0x800E00CC 0xffff0303\n\tmww 0x800E00D0 0x00012100\n\tmww 0x800E00D4 0xffff0303\n\tmww 0x800E00D8 0x00012100\n\tmww 0x800E00DC 0xffff0303\n\tmww 0x800E00E0 0x00000003\n\tmww 0x800E00E8 0x00000000\n\tmww 0x800E0108 0x00000612\n\tmww 0x800E010C 0x01000f02\n\tmww 0x800E0114 0x00000200\n\tmww 0x800E0118 0x00020007\n\tmww 0x800E011C 0xf4004a27\n\tmww 0x800E0120 0xf4004a27\n\tmww 0x800E012C 0x07400300\n\tmww 0x800E0130 0x07400300\n\tmww 0x800E013C 0x00000005\n\tmww 0x800E0140 0x00000000\n\tmww 0x800E0144 0x00000000\n\tmww 0x800E0148 0x01000000\n\tmww 0x800E014C 0x01020408\n\tmww 0x800E0150 0x08040201\n\tmww 0x800E0154 0x000f1133\n\tmww 0x800E015C 0x00001f04\n\tmww 0x800E0160 0x00001f04\n\tmww 0x800E016C 0x00001f04\n\tmww 0x800E0170 0x00001f04\n\tmww 0x800E0288 0x00010000\n\tmww 0x800E028C 0x00030404\n\tmww 0x800E0290 0x00000003\n\tmww 0x800E02AC 0x01010000\n\tmww 0x800E02B0 0x01000000\n\tmww 0x800E02B4 0x03030000\n\tmww 0x800E02B8 0x00010303\n\tmww 0x800E02BC 0x01020202\n\tmww 0x800E02C0 0x00000000\n\tmww 0x800E02C4 0x02030303\n\tmww 0x800E02C8 0x21002103\n\tmww 0x800E02CC 0x00061200\n\tmww 0x800E02D0 0x06120612\n\tmww 0x800E02D4 0x04420442\n\t# Mode register 0 for CS1 and CS0, ok to program CS1 even if not used\n\tmww 0x800E02D8 0x00000000\n\t# Mode register 0 for CS2 and CS3, not supported in this processor\n\tmww 0x800E02DC 0x00040004\n\t# Mode register 1 for CS1 and CS0, ok to program CS1 even if not used\n\tmww 0x800E02E0 0x00000000\n\t# Mode register 1 for CS2 and CS3, not supported in this processor\n\tmww 0x800E02E4 0x00000000\n\t# Mode register 2 for CS1 and CS0, ok to program CS1 even if not used\n\tmww 0x800E02E8 0x00000000\n\t# Mode register 2 for CS2 and CS3, not supported in this processor\n\tmww 0x800E02EC 0x00000000\n\t# Mode register 3 for CS1 and CS0, ok to program CS1 even if not used\n\tmww 0x800E02F0 0x00000000\n\t# Mode register 3 for CS2 and CS3, not supported in this processor\n\tmww 0x800E02F4 0xffffffff\n\n\t#**  start controller **#\n\tmww 0x800E0040 0x00000001\n\t# bit[0]: start\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/imx31pdk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The IMX31PDK eval board has a single IMX31 chip\nsource [find target/imx31.cfg]\nsource [find target/imx.cfg]\n$_TARGETNAME configure -event reset-init { imx31pdk_init }\n\nproc self_test {} {\n\techo \"Running 100 iterations of test.\"\n\tdump_image /ram/test 0x80000000 0x40000\n\tfor {set i 0} {$i < 100} {set i [expr {$i+1}]} {\n\t\techo \"Iteration $i\"\n\t\treset init\n\t\tmww 0x80000000 0x12345678 0x10000\n\t\tload_image /ram/test 0x80000000 bin\n\t\tverify_image /ram/test 0x80000000 bin\n\t}\n}\n\n\n# Slow fallback frequency\n# measure_clk indicates ca. 3-4MHz.\njtag_rclk 1000\n\nproc imx31pdk_init { } {\n\n\timx3x_reset\n\n\t# This setup puts RAM at 0x80000000\n\n\tmww 0x53FC0000 0x040\n\tmww 0x53F80000 0x074B0B7D\n\n\t# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40\n\t#mww 0x53F80004 0xFF871D50\n\t#mww 0x53F80010 0x00271C1B\n\n\t# Start 16 bit NorFlash Initialization on CS0\n\tmww 0xb8002000 0x0000CC03\n\tmww 0xb8002004 0xa0330D01\n\tmww 0xb8002008 0x00220800\n\n\t# Configure CPLD on CS4\n\tmww 0xb8002040 0x0000DCF6\n\tmww 0xb8002044 0x444A4541\n\tmww 0xb8002048 0x44443302\n\n\t# SDCLK\n\tmww 0x43FAC26C 0\n\n\t# CAS\n\tmww 0x43FAC270 0\n\n\t# RAS\n\tmww 0x43FAC274 0\n\n\t# CS2 (CSD0)\n\tmww 0x43FAC27C 0x1000\n\n\t# DQM3\n\tmww 0x43FAC284 0\n\n\t# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)\n\tmww 0x43FAC288 0\n\tmww 0x43FAC28C 0\n\tmww 0x43FAC290 0\n\tmww 0x43FAC294 0\n\tmww 0x43FAC298 0\n\tmww 0x43FAC29C 0\n\tmww 0x43FAC2A0 0\n\tmww 0x43FAC2A4 0\n\tmww 0x43FAC2A8 0\n\tmww 0x43FAC2AC 0\n\tmww 0x43FAC2B0 0\n\tmww 0x43FAC2B4 0\n\tmww 0x43FAC2B8 0\n\tmww 0x43FAC2BC 0\n\tmww 0x43FAC2C0 0\n\tmww 0x43FAC2C4 0\n\tmww 0x43FAC2C8 0\n\tmww 0x43FAC2CC 0\n\tmww 0x43FAC2D0 0\n\tmww 0x43FAC2D4 0\n\tmww 0x43FAC2D8 0\n\tmww 0x43FAC2DC 0\n\n\t# Initialization script for 32 bit DDR on MX31 ADS\n\tmww 0xB8001010 0x00000004\n\tmww 0xB8001004 0x006ac73a\n\tmww 0xB8001000 0x92100000\n\tmww 0x80000f00 0x12344321\n\tmww 0xB8001000 0xa2100000\n\tmww 0x80000000 0x12344321\n\tmww 0x80000000 0x12344321\n\tmww 0xB8001000 0xb2100000\n\tmwb 0x80000033 0xda\n\tmwb 0x81000000 0xff\n\tmww 0xB8001000 0x82226080\n\tmww 0x80000000 0xDEADBEEF\n\tmww 0xB8001010 0x0000000c\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/imx35pdk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The IMX35PDK eval board has a single IMX35 chip\nsource [find target/imx35.cfg]\nsource [find target/imx.cfg]\n$_TARGETNAME configure -event reset-init { imx35pdk_init }\n\n# Stick to *really* low clock rate or reset will fail\n# without RTCK / RCLK\njtag_rclk 10\n\nproc imx35pdk_init { } {\n\n\timx3x_reset\n\n\tmww 0x43f00040 0x00000000\n\tmww 0x43f00044 0x00000000\n\tmww 0x43f00048 0x00000000\n\tmww 0x43f0004C 0x00000000\n\tmww 0x43f00050 0x00000000\n\tmww 0x43f00000 0x77777777\n\tmww 0x43f00004 0x77777777\n\tmww 0x53f00040 0x00000000\n\tmww 0x53f00044 0x00000000\n\tmww 0x53f00048 0x00000000\n\tmww 0x53f0004C 0x00000000\n\tmww 0x53f00050 0x00000000\n\tmww 0x53f00000 0x77777777\n\tmww 0x53f00004 0x77777777\n\n\t# clock setup\n\tmww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP\n\tmww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.\n\n\t#=================================================\n\t# WEIM config\n\t#=================================================\n\t# CS0U\n\tmww 0xB8002000 0x0000CC03\n\t# CS0L\n\tmww 0xB8002004 0xA0330D01\n\t# CS0A\n\tmww 0xB8002008 0x00220800\n\t# CS5U\n\tmww 0xB8002050 0x0000dcf6\n\t# CS5L\n\tmww 0xB8002054 0x444a4541\n\t# CS5A\n\tmww 0xB8002058 0x44443302\n\n\t# IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR\n\tmww 0x43FAC368 0x00000006\n\tmww 0x43FAC36C 0x00000006\n\tmww 0x43FAC370 0x00000006\n\tmww 0x43FAC374 0x00000006\n\tmww 0x43FAC378 0x00000006\n\tmww 0x43FAC37C 0x00000006\n\tmww 0x43FAC380 0x00000006\n\tmww 0x43FAC384 0x00000006\n\tmww 0x43FAC388 0x00000006\n\tmww 0x43FAC38C 0x00000006\n\tmww 0x43FAC390 0x00000006\n\tmww 0x43FAC394 0x00000006\n\tmww 0x43FAC398 0x00000006\n\tmww 0x43FAC39C 0x00000006\n\tmww 0x43FAC3A0 0x00000006\n\tmww 0x43FAC3A4 0x00000006\n\tmww 0x43FAC3A8 0x00000006\n\tmww 0x43FAC3AC 0x00000006\n\tmww 0x43FAC3B0 0x00000006\n\tmww 0x43FAC3B4 0x00000006\n\tmww 0x43FAC3B8 0x00000006\n\tmww 0x43FAC3BC 0x00000006\n\tmww 0x43FAC3C0 0x00000006\n\tmww 0x43FAC3C4 0x00000006\n\tmww 0x43FAC3C8 0x00000006\n\tmww 0x43FAC3CC 0x00000006\n\tmww 0x43FAC3D0 0x00000006\n\tmww 0x43FAC3D4 0x00000006\n\tmww 0x43FAC3D8 0x00000006\n\n\t# DDR data bus SD 0 through 31\n\tmww 0x43FAC3DC 0x00000082\n\tmww 0x43FAC3E0 0x00000082\n\tmww 0x43FAC3E4 0x00000082\n\tmww 0x43FAC3E8 0x00000082\n\tmww 0x43FAC3EC 0x00000082\n\tmww 0x43FAC3F0 0x00000082\n\tmww 0x43FAC3F4 0x00000082\n\tmww 0x43FAC3F8 0x00000082\n\tmww 0x43FAC3FC 0x00000082\n\tmww 0x43FAC400 0x00000082\n\tmww 0x43FAC404 0x00000082\n\tmww 0x43FAC408 0x00000082\n\tmww 0x43FAC40C 0x00000082\n\tmww 0x43FAC410 0x00000082\n\tmww 0x43FAC414 0x00000082\n\tmww 0x43FAC418 0x00000082\n\tmww 0x43FAC41c 0x00000082\n\tmww 0x43FAC420 0x00000082\n\tmww 0x43FAC424 0x00000082\n\tmww 0x43FAC428 0x00000082\n\tmww 0x43FAC42c 0x00000082\n\tmww 0x43FAC430 0x00000082\n\tmww 0x43FAC434 0x00000082\n\tmww 0x43FAC438 0x00000082\n\tmww 0x43FAC43c 0x00000082\n\tmww 0x43FAC440 0x00000082\n\tmww 0x43FAC444 0x00000082\n\tmww 0x43FAC448 0x00000082\n\tmww 0x43FAC44c 0x00000082\n\tmww 0x43FAC450 0x00000082\n\tmww 0x43FAC454 0x00000082\n\tmww 0x43FAC458 0x00000082\n\n\t# DQM setup\n\tmww 0x43FAC45c 0x00000082\n\tmww 0x43FAC460 0x00000082\n\tmww 0x43FAC464 0x00000082\n\tmww 0x43FAC468 0x00000082\n\n\tmww 0x43FAC46c 0x00000006\n\tmww 0x43FAC470 0x00000006\n\tmww 0x43FAC474 0x00000006\n\tmww 0x43FAC478 0x00000006\n\tmww 0x43FAC47c 0x00000006\n\tmww 0x43FAC480 0x00000006\t;# CSD0\n\tmww 0x43FAC484 0x00000006\t;# CSD1\n\tmww 0x43FAC488 0x00000006\n\tmww 0x43FAC48c 0x00000006\n\tmww 0x43FAC490 0x00000006\n\tmww 0x43FAC494 0x00000006\n\tmww 0x43FAC498 0x00000006\n\tmww 0x43FAC49c 0x00000006\n\tmww 0x43FAC4A0 0x00000006\n\tmww 0x43FAC4A4 0x00000006\t;# RAS\n\tmww 0x43FAC4A8 0x00000006\t;# CAS\n\tmww 0x43FAC4Ac 0x00000006\t;# SDWE\n\tmww 0x43FAC4B0 0x00000006 \t;# SDCKE0\n\tmww 0x43FAC4B4 0x00000006  ;# SDCKE1\n\tmww 0x43FAC4B8 0x00000002  ;# SDCLK\n\n\t# SDQS0 through SDQS3\n\tmww 0x43FAC4Bc 0x00000082\n\tmww 0x43FAC4C0 0x00000082\n\tmww 0x43FAC4C4 0x00000082\n\tmww 0x43FAC4C8 0x00000082\n\n\n\t# *==================================================\n\t#  Initialization script for 32 bit DDR2 on RINGO 3DS\n\t# *==================================================\n\n\t#--------------------------------------------\n\t# Init CCM\n\t#--------------------------------------------\n\tmww 0x53F80028 0x7D000028\n\n\t#--------------------------------------------\n\t# Init IOMUX for JTAG\n\t#--------------------------------------------\n\tmww 0x43FAC5EC 0x000000C3\n\tmww 0x43FAC5F0 0x000000C3\n\tmww 0x43FAC5F4 0x000000F3\n\tmww 0x43FAC5F8 0x000000F3\n\tmww 0x43FAC5FC 0x000000F3\n\tmww 0x43FAC600 0x000000F3\n\tmww 0x43FAC604 0x000000F3\n\n\n\t# ESD_MISC : enable DDR2\n\tmww 0xB8001010 0x00000304\n\n\t#--------------------------------------------\n\t# Init 32-bit DDR2 memory on CSD0\n\t# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]\n\t#--------------------------------------------\n\n\t# ESD_ESDCFG0 : set timing parameters\n\tmww 0xB8001004 0x007ffC2f\n\n\t# ESD_ESDCTL0 : select Prechare-All mode\n\tmww 0xB8001000 0x92220000\n\t# DDR2 : Prechare-All\n\tmww 0x80000400 0x12345678\n\n\t# ESD_ESDCTL0 : select Load-Mode-Register mode\n\tmww 0xB8001000 0xB2220000\n\t# DDR2 : Load reg EMR2\n\tmwb 0x84000000 0xda\n\t# DDR2 : Load reg EMR3\n\tmwb 0x86000000 0xda\n\t# DDR2 : Load reg EMR1 -- enable DLL\n\tmwb 0x82000400 0xda\n\t# DDR2 : Load reg MR -- reset DLL\n\tmwb 0x80000333 0xda\n\n\t# ESD_ESDCTL0 : select Prechare-All mode\n\tmww 0xB8001000 0x92220000\n\t# DDR2 : Prechare-All\n\tmwb 0x80000400 0x12345678\n\n\t# ESD_ESDCTL0 : select Manual-Refresh mode\n\tmww 0xB8001000 0xA2220000\n\t# DDR2 : Manual-Refresh 2 times\n\tmww 0x80000000 0x87654321\n\tmww 0x80000000 0x87654321\n\n\t# ESD_ESDCTL0 : select Load-Mode-Register mode\n\tmww 0xB8001000 0xB2220000\n\t# DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset\n\tmwb 0x80000233 0xda\n\t# DDR2 : Load reg EMR1 -- OCD default\n\tmwb 0x82000780 0xda\n\t# DDR2 : Load reg EMR1 -- OCD exit\n\tmwb 0x82000400 0xda\t;# ODT disabled\n\n\t# ESD_ESDCTL0 : select normal-operation mode\n\t# DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit\n\t# disable PWT & PRCT\n\t# disable Auto-Refresh\n\tmww 0xB8001000 0x82220080\n\n\t## ESD_ESDCTL0 : enable Auto-Refresh\n\tmww 0xB8001000 0x82228080\n\t## ESD_ESDCTL1 : enable Auto-Refresh\n\tmww 0xB8001008 0x00002000\n\n\n\t#***********************************************\n\t# Adjust the ESDCDLY5 register\n\t#***********************************************\n\t# Vary DQS_ABS_OFFSET5 for writes\n\tmww 0xB8001020 0x00F48000\t;# this is the default value\n\tmww 0xB8001024 0x00F48000\t;# this is the default value\n\tmww 0xB8001028 0x00F48000\t;# this is the default value\n\tmww 0xB800102c 0x00F48000\t;# this is the default value\n\n\n\t#Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)\n\tmww 0xB8001010 0x00000384\n\t# wait a while\n\tsleep 1000\n\t# now clear the force measurement bit\n\tmww 0xB8001010 0x00000304\n\n\t# dummy write to DDR memory to set DQS low\n\tmww 0x80000000 0x00000000\n\n\tmww 0x30000100 0x0\n\tmww 0x30000104 0x31024\n\n\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/imx53-m53evk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#######################################\n# DENX M53EVK                         #\n# http://www.denx-cs.de/?q=M53EVK     #\n# Author: Marek Vasut <marex@denx.de> #\n# Based on imx53loco.cfg              #\n#######################################\n\n# The DENX M53EVK has on-board JTAG adapter\nsource [find interface/ftdi/m53evk.cfg]\n# The DENX M53EVK board has a single i.MX53 chip\nsource [find target/imx53.cfg]\n# Helper for common memory read/modify/write procedures\nsource [find mem_helper.tcl]\n\necho \"iMX53 M53EVK board lodaded.\"\n\n# Set reset type\nreset_config trst_and_srst separate trst_open_drain srst_open_drain\n\n# Run at 6 MHz\nadapter speed 6000\n\n$_TARGETNAME configure -event \"reset-assert\" {\n\techo \"Resetting ....\"\n\t#cortex_a dbginit\n}\n\n$_TARGETNAME configure -event reset-init { m53evk_init }\n\nglobal AIPS1_BASE_ADDR\nset AIPS1_BASE_ADDR     0x53F00000\nglobal AIPS2_BASE_ADDR\nset AIPS2_BASE_ADDR     0x63F00000\n\nproc m53evk_init { } {\n\techo \"Reset-init...\"\n\t; # halt the CPU\n\thalt\n\n\techo \"HW version [format %x [mrw 0x48]]\"\n\n\tdap apsel 1\n\tDCD\n\n\t; # ARM errata ID #468414\n\tset tR [arm mrc 15 0 1 0 1]\n\tarm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]\t; # enable L1NEON bit\n\n\tinit_l2cc\n\tinit_aips\n\tinit_clock\n\n\tdap apsel 0\n\n\t; # Force ARM state\n\t; #reg cpsr 0x000001D3\n\tarm core_state arm\n}\n\n\n# L2CC Cache setup/invalidation/disable\nproc init_l2cc { } {\n\t; #/* explicitly disable L2 cache */\n\t; #mrc 15, 0, r0, c1, c0, 1\n\tset tR [arm mrc 15 0 1 0 1]\n\t; #bic r0, r0, #0x2\n\t; #mcr 15, 0, r0, c1, c0, 1\n\tarm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]\n\n\t; #/* reconfigure L2 cache aux control reg */\n\t; #mov r0, #0xC0                   /* tag RAM */\n\t; #add r0, r0, #0x4                /* data RAM */\n\t; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */\n\t; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */\n\t; #orr r0, r0, #(1 << 22)          /* disable write allocate */\n\n\t; #mcr 15, 1, r0, c9, c0, 2\n\tarm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]\n}\n\n\n# AIPS setup - Only setup MPROTx registers.\n# The PACR default values are good.\nproc init_aips { } {\n\t; # Set all MPROTx to be non-bufferable, trusted for R/W,\n\t; # not forced to user-mode.\n\tglobal AIPS1_BASE_ADDR\n\tglobal AIPS2_BASE_ADDR\n\tset VAL\t\t\t0x77777777\n\n#\tdap apsel 1\n\tmww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL\n\tmww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL\n\tmww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL\n\tmww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL\n#\tdap apsel 0\n}\n\n\nproc init_clock { } {\n\tglobal AIPS1_BASE_ADDR\n\tglobal AIPS2_BASE_ADDR\n\tset CCM_BASE_ADDR\t[expr {$AIPS1_BASE_ADDR + 0x000D4000}]\n\tset CLKCTL_CCSR         0x0C\n\tset CLKCTL_CBCDR\t0x14\n\tset CLKCTL_CBCMR        0x18\n\tset PLL1_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x00080000}]\n\tset PLL2_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x00084000}]\n\tset PLL3_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x00088000}]\n\tset PLL4_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x0008C000}]\n\tset CLKCTL_CSCMR1\t0x1C\n\tset CLKCTL_CDHIPR\t0x48\n\tset PLATFORM_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x000A0000}]\n\tset CLKCTL_CSCDR1\t0x24\n\tset CLKCTL_CCDR\t\t0x04\n\n\t; # Switch ARM to step clock\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4\n\n\treturn\n\techo \"not returned\"\n\tsetup_pll $PLL1_BASE_ADDR 800\n\tsetup_pll $PLL3_BASE_ADDR 400\n\n\t; # Switch peripheral to PLL3\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]\n\twhile {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }\n\n\tsetup_pll $PLL2_BASE_ADDR 400\n\n\t; # Switch peripheral to PLL2\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]\n\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154\n\n\t; # change uart clk parent to pll2\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]\n\n\t; # make sure change is effective\n\twhile {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }\n\n\tsetup_pll $PLL3_BASE_ADDR 216\n\n\tsetup_pll $PLL4_BASE_ADDR 455\n\n\t; # Set the platform clock dividers\n\tmww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124\n\n\tmww [expr {$CCM_BASE_ADDR + 0x10}] 0\n\n\t; # Switch ARM back to PLL 1.\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0\n\n\t; # make uart div=6\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]\n\n\t; # Restore the default values in the Gate registers\n\tmww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF\n\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000\n\n\t; # for cko - for ARM div by 8\n\tmww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]\n}\n\n\nproc setup_pll { PLL_ADDR CLK } {\n\tset PLL_DP_CTL\t\t0x00\n\tset PLL_DP_CONFIG   \t0x04\n\tset PLL_DP_OP\t\t0x08\n\tset PLL_DP_HFS_OP\t0x1C\n\tset PLL_DP_MFD\t\t0x0C\n\tset PLL_DP_HFS_MFD\t0x20\n\tset PLL_DP_MFN\t\t0x10\n\tset PLL_DP_HFS_MFN\t0x24\n\n\tif {$CLK == 1000} {\n\t\tset DP_OP\t[expr {(10 << 4) + ((1 - 1) << 0)}]\n\t\tset DP_MFD\t[expr {12 - 1}]\n\t\tset DP_MFN\t5\n\t} elseif {$CLK == 850} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {48 - 1}]\n\t\tset DP_MFN\t41\n\t} elseif {$CLK == 800} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {3 - 1}]\n\t\tset DP_MFN\t1\n\t} elseif {$CLK == 700} {\n\t\tset DP_OP\t[expr {(7 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {24 - 1}]\n\t\tset DP_MFN\t7\n\t} elseif {$CLK == 600} {\n\t\tset DP_OP\t[expr {(6 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {4 - 1}]\n\t\tset DP_MFN\t1\n\t} elseif {$CLK == 665} {\n\t\tset DP_OP\t[expr {(6 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {96 - 1}]\n\t\tset DP_MFN\t89\n\t} elseif {$CLK == 532} {\n\t\tset DP_OP\t[expr {(5 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {24 - 1}]\n\t\tset DP_MFN\t13\n\t} elseif {$CLK == 455} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((2 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {48 - 1}]\n\t\tset DP_MFN\t71\n\t} elseif {$CLK == 400} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((2 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {3 - 1}]\n\t\tset DP_MFN\t1\n\t} elseif {$CLK == 216} {\n\t\tset DP_OP\t[expr {(6 << 4) + ((3 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {4 - 1}]\n\t\tset DP_MFN\t3\n\t} else {\n\t\terror \"Error (setup_dll): clock not found!\"\n\t}\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232\n\tmww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP\n\tmww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD\n\tmww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN\n\tmww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232\n\twhile {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }\n}\n\n\nproc CPU_2_BE_32 { L } {\n\treturn [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]\n}\n\n\n# Device Configuration Data\nproc DCD { } {\n#\tdap apsel 1\n\tmww 0x53fa86f4 0x00000000\t ;# GRP_DDRMODE_CTL\n\tmww 0x53fa8714 0x00000000\t ;# GRP_DDRMODE\n\tmww 0x53fa86fc 0x00000000\t ;# GRP_DDRPKE\n\tmww 0x53fa8724 0x04000000\t ;# GRP_DDR_TYPE\n\n\tmww 0x53fa872c 0x00300000\t ;# GRP_B3DS\n\tmww 0x53fa8554 0x00300000\t ;# DRAM_DQM3\n\tmww 0x53fa8558 0x00300040\t ;# DRAM_SDQS3\n\n\tmww 0x53fa8728 0x00300000\t ;# GRP_B2DS\n\tmww 0x53fa8560 0x00300000\t ;# DRAM_DQM2\n\tmww 0x53fa8568 0x00300040\t ;# DRAM_SDQS2\n\n\tmww 0x53fa871c 0x00300000\t ;# GRP_B1DS\n\tmww 0x53fa8594 0x00300000\t ;# DRAM_DQM1\n\tmww 0x53fa8590 0x00300040\t ;# DRAM_SDQS1\n\n\tmww 0x53fa8718 0x00300000\t ;# GRP_B0DS\n\tmww 0x53fa8584 0x00300000\t ;# DRAM_DQM0\n\tmww 0x53fa857c 0x00300040\t ;# DRAM_SDQS0\n\n\tmww 0x53fa8578 0x00300000\t ;# DRAM_SDCLK_0\n\tmww 0x53fa8570 0x00300000\t ;# DRAM_SDCLK_1\n\n\tmww 0x53fa8574 0x00300000\t ;# DRAM_CAS\n\tmww 0x53fa8588 0x00300000\t ;# DRAM_RAS\n\tmww 0x53fa86f0 0x00300000\t ;# GRP_ADDDS\n\tmww 0x53fa8720 0x00300000\t ;# GRP_CTLDS\n\n\tmww 0x53fa8564 0x00300040\t ;# DRAM_SDODT1\n\tmww 0x53fa8580 0x00300040\t ;# DRAM_SDODT0\n\n\t# Initialize DDR2 memory\n\tmww 0x63fd9088 0x32383535\n\tmww 0x63fd9090 0x40383538\n\tmww 0x63fd907c 0x0136014d\n\tmww 0x63fd9080 0x01510141\n\n\tmww 0x63fd9018 0x00011740\n\tmww 0x63fd9000 0xc3190000\n\tmww 0x63fd900c 0x555952e3\n\tmww 0x63fd9010 0xb68e8b63\n\tmww 0x63fd9014 0x01ff00db\n\tmww 0x63fd902c 0x000026d2\n\tmww 0x63fd9030 0x009f0e21\n\tmww 0x63fd9008 0x12273030\n\tmww 0x63fd9004 0x0002002d\n\tmww 0x63fd901c 0x00008032\n\tmww 0x63fd901c 0x00008033\n\tmww 0x63fd901c 0x00028031\n\tmww 0x63fd901c 0x092080b0\n\tmww 0x63fd901c 0x04008040\n\tmww 0x63fd901c 0x0000803a\n\tmww 0x63fd901c 0x0000803b\n\tmww 0x63fd901c 0x00028039\n\tmww 0x63fd901c 0x09208138\n\tmww 0x63fd901c 0x04008048\n\tmww 0x63fd9020 0x00001800\n\tmww 0x63fd9040 0x04b80003\n\tmww 0x63fd9058 0x00022227\n\tmww 0x63fd901c 0x00000000\n#\tdap apsel 0\n}\n\n# vim:filetype=tcl\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/imx53loco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n##################################################################################\n# Author: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> #\n# Kiwigrid GmbH                                                                  #\n##################################################################################\n\n# The IMX53LOCO (QSB) board has a single IMX53 chip\nsource [find target/imx53.cfg]\n# Helper for common memory read/modify/write procedures\nsource [find mem_helper.tcl]\n\necho \"iMX53 Loco board lodaded.\"\n\n# Set reset type\n#reset_config srst_only\n\nadapter speed 3000\n\n# Slow speed to be sure it will work\njtag_rclk 1000\n$_TARGETNAME configure -event \"reset-start\" { jtag_rclk 1000 }\n\n#adapter srst delay 200\n#jtag_ntrst_delay 200\n\n$_TARGETNAME configure -event \"reset-assert\" {\n\techo \"Resetting ....\"\n\t#cortex_a dbginit\n}\n\n$_TARGETNAME configure -event reset-init { loco_init }\n\nglobal AIPS1_BASE_ADDR\nset AIPS1_BASE_ADDR     0x53F00000\nglobal AIPS2_BASE_ADDR\nset AIPS2_BASE_ADDR     0x63F00000\n\nproc loco_init { } {\n\techo \"Reset-init...\"\n\t; # halt the CPU\n\thalt\n\n\techo \"HW version [format %x [mrw 0x48]]\"\n\n\tdap apsel 1\n\tDCD\n\n\t; # ARM errata ID #468414\n\tset tR [arm mrc 15 0 1 0 1]\n\tarm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}]\t; # enable L1NEON bit\n\n\tinit_l2cc\n\tinit_aips\n\tinit_clock\n\n\tdap apsel 0\n\n\t; # Force ARM state\n\t; #reg cpsr 0x000001D3\n\tarm core_state arm\n\n\tjtag_rclk 3000\n#\tadapter speed 3000\n}\n\n\n# L2CC Cache setup/invalidation/disable\nproc init_l2cc { } {\n\t; #/* explicitly disable L2 cache */\n\t; #mrc 15, 0, r0, c1, c0, 1\n\tset tR [arm mrc 15 0 1 0 1]\n\t; #bic r0, r0, #0x2\n\t; #mcr 15, 0, r0, c1, c0, 1\n\tarm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]\n\n\t; #/* reconfigure L2 cache aux control reg */\n\t; #mov r0, #0xC0                   /* tag RAM */\n\t; #add r0, r0, #0x4                /* data RAM */\n\t; #orr r0, r0, #(1 << 24)          /* disable write allocate delay */\n\t; #orr r0, r0, #(1 << 23)          /* disable write allocate combine */\n\t; #orr r0, r0, #(1 << 22)          /* disable write allocate */\n\n\t; #mcr 15, 1, r0, c9, c0, 2\n\tarm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]\n}\n\n\n# AIPS setup - Only setup MPROTx registers.\n# The PACR default values are good.\nproc init_aips { } {\n\t; # Set all MPROTx to be non-bufferable, trusted for R/W,\n\t; # not forced to user-mode.\n\tglobal AIPS1_BASE_ADDR\n\tglobal AIPS2_BASE_ADDR\n\tset VAL\t\t\t0x77777777\n\n#\tdap apsel 1\n\tmww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL\n\tmww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL\n\tmww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL\n\tmww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL\n#\tdap apsel 0\n}\n\n\nproc init_clock { } {\n\tglobal AIPS1_BASE_ADDR\n\tglobal AIPS2_BASE_ADDR\n\tset CCM_BASE_ADDR\t[expr {$AIPS1_BASE_ADDR + 0x000D4000}]\n\tset CLKCTL_CCSR         0x0C\n\tset CLKCTL_CBCDR\t0x14\n\tset CLKCTL_CBCMR        0x18\n\tset PLL1_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x00080000}]\n\tset PLL2_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x00084000}]\n\tset PLL3_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x00088000}]\n\tset PLL4_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x0008C000}]\n\tset CLKCTL_CSCMR1\t0x1C\n\tset CLKCTL_CDHIPR\t0x48\n\tset PLATFORM_BASE_ADDR\t[expr {$AIPS2_BASE_ADDR + 0x000A0000}]\n\tset CLKCTL_CSCDR1\t0x24\n\tset CLKCTL_CCDR\t\t0x04\n\n\t; # Switch ARM to step clock\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4\n\n\treturn\n\techo \"not returned\"\n\tsetup_pll $PLL1_BASE_ADDR 800\n\tsetup_pll $PLL3_BASE_ADDR 400\n\n\t; # Switch peripheral to PLL3\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]\n\twhile {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }\n\n\tsetup_pll $PLL2_BASE_ADDR 400\n\n\t; # Switch peripheral to PLL2\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]\n\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154\n\n\t; # change uart clk parent to pll2\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]\n\n\t; # make sure change is effective\n\twhile {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }\n\n\tsetup_pll $PLL3_BASE_ADDR 216\n\n\tsetup_pll $PLL4_BASE_ADDR 455\n\n\t; # Set the platform clock dividers\n\tmww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124\n\n\tmww [expr {$CCM_BASE_ADDR + 0x10}] 0\n\n\t; # Switch ARM back to PLL 1.\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0\n\n\t; # make uart div=6\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]\n\n\t; # Restore the default values in the Gate registers\n\tmww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF\n\tmww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF\n\n\tmww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000\n\n\t; # for cko - for ARM div by 8\n\tmww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]\n}\n\n\nproc setup_pll { PLL_ADDR CLK } {\n\tset PLL_DP_CTL\t\t0x00\n\tset PLL_DP_CONFIG   \t0x04\n\tset PLL_DP_OP\t\t0x08\n\tset PLL_DP_HFS_OP\t0x1C\n\tset PLL_DP_MFD\t\t0x0C\n\tset PLL_DP_HFS_MFD\t0x20\n\tset PLL_DP_MFN\t\t0x10\n\tset PLL_DP_HFS_MFN\t0x24\n\n\tif {$CLK == 1000} {\n\t\tset DP_OP\t[expr {(10 << 4) + ((1 - 1) << 0)}]\n\t\tset DP_MFD\t[expr {12 - 1}]\n\t\tset DP_MFN\t5\n\t} elseif {$CLK == 850} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {48 - 1}]\n\t\tset DP_MFN\t41\n\t} elseif {$CLK == 800} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {3 - 1}]\n\t\tset DP_MFN\t1\n\t} elseif {$CLK == 700} {\n\t\tset DP_OP\t[expr {(7 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {24 - 1}]\n\t\tset DP_MFN\t7\n\t} elseif {$CLK == 600} {\n\t\tset DP_OP\t[expr {(6 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {4 - 1}]\n\t\tset DP_MFN\t1\n\t} elseif {$CLK == 665} {\n\t\tset DP_OP\t[expr {(6 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {96 - 1}]\n\t\tset DP_MFN\t89\n\t} elseif {$CLK == 532} {\n\t\tset DP_OP\t[expr {(5 << 4) + ((1 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {24 - 1}]\n\t\tset DP_MFN\t13\n\t} elseif {$CLK == 455} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((2 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {48 - 1}]\n\t\tset DP_MFN\t71\n\t} elseif {$CLK == 400} {\n\t\tset DP_OP\t[expr {(8 << 4) + ((2 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {3 - 1}]\n\t\tset DP_MFN\t1\n\t} elseif {$CLK == 216} {\n\t\tset DP_OP\t[expr {(6 << 4) + ((3 - 1)  << 0)}]\n\t\tset DP_MFD\t[expr {4 - 1}]\n\t\tset DP_MFN\t3\n\t} else {\n\t\terror \"Error (setup_dll): clock not found!\"\n\t}\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232\n\tmww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP\n\tmww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD\n\tmww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN\n\tmww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN\n\n\tmww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232\n\twhile {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }\n}\n\n\nproc CPU_2_BE_32 { L } {\n\treturn [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8)  | (($L & 0xFF000000) >> 24)}]\n}\n\n\n# Device Configuration Data\nproc DCD { } {\n#\tdap apsel 1\n\tmww 0x53FA8554 0x00300000\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3\n\tmww 0x53FA8558 0x00300040\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3\n\tmww 0x53FA8560 0x00300000\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2\n\tmww 0x53FA8564 0x00300040\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT\n\tmww 0x53FA8568 0x00300040\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2\n\tmww 0x53FA8570 0x00300000\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1\n\tmww 0x53FA8574 0x00300000\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS\n\tmww 0x53FA8578 0x00300000\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0\n\tmww 0x53FA857c 0x00300040\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0\n\tmww 0x53FA8580 0x00300040\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0\n\tmww 0x53FA8584 0x00300000\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0\n\tmww 0x53FA8588 0x00300000\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS\n\tmww 0x53FA8590 0x00300040\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1\n\tmww 0x53FA8594 0x00300000\t;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1\n\tmww 0x53FA86f0 0x00300000\t;# IOMUXC_SW_PAD_CTL_GRP_ADDDS\n\tmww 0x53FA86f4 0x00000000\t;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL\n\tmww 0x53FA86fc 0x00000000\t;# IOMUXC_SW_PAD_CTL_GRP_DDRPKE\n\tmww 0x53FA8714 0x00000000\t;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode\n\tmww 0x53FA8718 0x00300000\t;# IOMUXC_SW_PAD_CTL_GRP_B0DS\n\tmww 0x53FA871c 0x00300000\t;# IOMUXC_SW_PAD_CTL_GRP_B1DS\n\tmww 0x53FA8720 0x00300000\t;# IOMUXC_SW_PAD_CTL_GRP_CTLDS\n\tmww 0x53FA8724 0x04000000\t;# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0=\n\tmww 0x53FA8728 0x00300000\t;# IOMUXC_SW_PAD_CTL_GRP_B2DS\n\tmww 0x53FA872c 0x00300000\t;# IOMUXC_SW_PAD_CTL_GRP_B3DS\n\n\t# Initialize DDR2 memory\n\tmww 0x63FD9088 0x35343535\t;# ESDCTL_RDDLCTL\n\tmww 0x63FD9090 0x4d444c44\t;# ESDCTL_WRDLCTL\n\tmww 0x63FD907c 0x01370138\t;# ESDCTL_DGCTRL0\n\tmww 0x63FD9080 0x013b013c\t;# ESDCTL_DGCTRL1\n\tmww 0x63FD9018 0x00011740\t;# ESDCTL_ESDMISC\n\tmww 0x63FD9000 0xc3190000\t;# ESDCTL_ESDCTL\n\tmww 0x63FD900c 0x9f5152e3\t;# ESDCTL_ESDCFG0\n\tmww 0x63FD9010 0xb68e8a63\t;# ESDCTL_ESDCFG1\n\tmww 0x63FD9014 0x01ff00db\t;# ESDCTL_ESDCFG2\n\tmww 0x63FD902c 0x000026d2\t;# ESDCTL_ESDRWD\n\tmww 0x63FD9030 0x009f0e21\t;# ESDCTL_ESDOR\n\tmww 0x63FD9008 0x12273030\t;# ESDCTL_ESDOTC\n\tmww 0x63FD9004 0x0002002d\t;# ESDCTL_ESDPDC\n\tmww 0x63FD901c 0x00008032\t;# ESDCTL_ESDSCR\n\tmww 0x63FD901c 0x00008033\t;# ESDCTL_ESDSCR\n\tmww 0x63FD901c 0x00028031\t;# ESDCTL_ESDSCR\n\tmww 0x63FD901c 0x052080b0\t;# ESDCTL_ESDSCR\n\tmww 0x63FD901c 0x04008040\t;# ESDCTL_ESDSCR\n\tmww 0x63FD901c 0x0000803a\t;# ESDCTL_ESDSCR\n\tmww 0x63FD901c 0x0000803b\t;# ESDCTL_ESDSCR\n\tmww 0x63FD901c 0x00028039\t;# ESDCTL_ESDSCR\n\tmww 0x63FD901c 0x05208138\t;# ESDCTL_ESDSCR\n\tmww 0x63FD901c 0x04008048\t;# ESDCTL_ESDSCR\n\tmww 0x63FD9020 0x00005800\t;# ESDCTL_ESDREF\n\tmww 0x63FD9040 0x04b80003\t;# ESDCTL_ZQHWCTRL\n\tmww 0x63FD9058 0x00022227\t;# ESDCTL_ODTCTRL\n\tmww 0x63FD901C 0x00000000\t;# ESDCTL_ESDSCR\n#\tdap apsel 0\n}\n\n# vim:filetype=tcl\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/imx8mp-evk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# configuration file for NXP MC-IMX8MP-EVK\n#\n# Board includes FTDI-based JTAG adapter: interface/ftdi/imx8mp-evk.cfg\n#\n\ntransport select jtag\nadapter speed 1000\nreset_config srst_only\nadapter srst delay 100\n\nset CHIPNAME imx8mp\nset CHIPCORES 4\n\nsource [find target/imx8m.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/insignal_arndale.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# InSignal Arndale board\n#\n\nsource [find target/exynos5250.cfg]\n\n# Experimentally determined highest working speed\nadapter speed 200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/kasli.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nadapter driver ftdi\nftdi device_desc \"Quad RS232-HS\"\nftdi vid_pid 0x0403 0x6011\nftdi channel 0\nftdi layout_init 0x0008 0x000b\n# adapter usb location 1:8\n\nreset_config none\ntransport select jtag\nadapter speed 25000\n\nsource [find cpld/xilinx-xc7.cfg]\nsource [find cpld/jtagspi.cfg]\nsource [find fpga/xilinx-xadc.cfg]\nsource [find fpga/xilinx-dna.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/kc100.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Knovative KC-100 cable modem\n\n# TNETC4401PYP, 208-QFP U3\nsource [find target/tnetc4401.cfg]\n\n# 14-pin EJTAG on JP1. Standard pinout, 1-3-5-7-9-11 = nTRST-TDI-TDO-TMS-TCK-nSRST. Use 2 for GND.\n# Was initially disabled in hardware; had to add a solder bridge reenabling R124, R125 on back.\nreset_config trst_and_srst separate\n\n# 16Mb Intel CFI flash. Note this CPU has an internal ROM at 0x1FC0000 (phys) for cold boot.\n# All that really does is some minimal checks before jumping to external flash at 0x00000000 phys.\n# That is remapped to 0xB0000000 uncached, 0x90000000 cached.\nflash bank intel cfi 0xB0000000 0x200000 2 2 $_TARGETNAME\n\n# Perform this after a clean reboot, halt, and reset init (which should also leave it halted).\nproc kc100_dump_flash {} {\n\techo \"Probing 48 TSOP Intel CFI flash chip (2MB)...\"\n\tflash probe intel\n\techo \"Dumping 2MB flash chip to flashdump.bin.\n\tflash read_bank 0 flashdump.bin 0 0x200000\n}\n\n#TODO figure out memory init sequence to be able to dump from cached segment instead\n\n# There is also a serial console on JP2, 3-5-6 = TX-RX-GND. 9600/8/N/1.\n\n# Possibly of note, this modem's ancient ethernet port does not support Auto-MDIX.\n\n# This modem in many ways appears to be essentially a clone of the SB5120. See usbjtag.com.\n# The firmware/OS is also susceptible to many of the same procedures in \"Hacking the Cable Modem\"\n# by DerEngel (Ryan Harris), available from No Starch Press.\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/kc705.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html\n\nsource [find interface/ftdi/digilent-hs1.cfg]\nsource [find cpld/xilinx-xc7.cfg]\nsource [find cpld/jtagspi.cfg]\nsource [find fpga/xilinx-xadc.cfg]\nsource [find fpga/xilinx-dna.cfg]\nadapter speed 25000\n\n# example command to write bitstream, soft-cpu bios and runtime:\n# openocd -f board/kc705.cfg -c \"init;\\\n# jtagspi_init 0 bscan_spi_xc7k325t.bit;\\\n# jtagspi_program bitstream-kc705.bin 0;\\\n# jtagspi_program bios.bin 0xaf0000;\\\n# jtagspi_program runtime.fbi 0xb00000;\\\n# xc7_program xc7.tap;\\\n# exit\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/kcu105.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx ultrascale\n# http://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf\n\nsource [find interface/ftdi/digilent_jtag_smt2_nc.cfg]\n\nset CHIP XCKU040\nsource [find cpld/xilinx-xcu.cfg]\n\nsource [find cpld/jtagspi.cfg]\n\nadapter speed 25000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/keil_mcb1700.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Keil MCB1700 eval board\n#\n# http://www.keil.com/mcb1700/picture.asp\n#\n\nsource [find target/lpc17xx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/keil_mcb2140.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Keil MCB2140 eval board\n#\n# http://www.keil.com/mcb2140/picture.asp\n#\n\nsource [find target/lpc2148.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/kindle2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Board configuration file for Amazon Kindle Model No. D00701 and D00801\n# AKA Kindle 2nd generation and Kindle DX\n# using a Freescale MCIMX31LDVKN5D i.MX31 processor\n#\n# Pins at J9 40-Pin FFC-A:\n#  1 - GND\n# 16 - TRSTB\n# 17 - TDI\n# 18 - TMS\n# 19 - TCK\n# 20 - RTCK\n# 21 - TDO\n# 22 - DE\n# 25 - BOOT_MODE4\n# 27 - BOOT_MODE2\n\nsource [find target/imx31.cfg]\nsource [find target/imx.cfg]\n\n$_TARGETNAME configure -event reset-init { kindle2_init }\n$_TARGETNAME configure -event reset-start { adapter speed 1000 }\n\n# 8MiB NOR Flash\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0xa0000000 0x800000 2 2 $_TARGETNAME\n\n# 16kiB internal SRAM\n$_TARGETNAME configure -work-area-phys 0x1fffc000 \\\n\t-work-area-size 0x4000 -work-area-backup 0\n\n# FIXME: currently SRST is not wired to the system\nreset_config trst_only\njtag_ntrst_assert_width 10\njtag_ntrst_delay 30\n\n# this is broken but enabled by default\narm11 memwrite burst disable\n\nadapter speed 1000\nftdi tdo_sample_edge falling\n\nproc kindle2_init {} {\n\timx3x_reset\n\tkindle2_clock_setup\n\tdisable_mmu_and_cache\n\tkindle2_misc_init\n\tkindle2_sdram_init\n\tarm core_state arm\n}\n\nproc kindle2_clock_setup {} {\n\t# CCMR: clock from FPM/CKIL\n\tmww 0x53f80000  0x074b0b7b\n\t# IPU_CONF\n\tmww 0x53fc0000  0x040\n\t# 398MHz\n\tmww 0x53f80004 0xff871650\n\tmww 0x53f80010 0x00331c23\n}\n\nproc kindle2_misc_init { } {\n\t# AIPS1\n\tmww 0x43f00040 0x0\n\tmww 0x43f00044 0x0\n\tmww 0x43f00048 0x0\n\tmww 0x43f0004c 0x0\n\tmww 0x43f00050 0x0\n\tmww 0x43f00000 0x77777777\n\tmww 0x43f00004 0x77777777\n\n\t# AIPS2\n\tmww 0x53f00040 0x0\n\tmww 0x53f00044 0x0\n\tmww 0x53f00048 0x0\n\tmww 0x53f0004c 0x0\n\tmww 0x53f00050 0x0\n\tmww 0x53f00000 0x77777777\n\tmww 0x53f00004 0x77777777\n\n\t# Start 16 bit NorFlash Initialization on CS0\n\tmww 0xb8002000 0x0000cc03\n\tmww 0xb8002004 0xa0330d01\n\tmww 0xb8002008 0x00220800\n}\n\nproc disable_mmu_and_cache {} {\n\t# Mode Supervisor, disable FIQ, IRQ and imprecise data aborts\n\treg cpsr 0x1d3\n\n\t# flush entire BTAC\n\tarm mcr 15 0 7 5 6 0\n\t# invalidate instruction and data cache\n\t# MCR CP15, 0, R1, C7, C7, 0\n\tarm mcr 15 0 7 7 0\n\n\t# clean and invalidate cache\n\tarm mcr 15 0 7 15 0\n\n\t# disable MMU and caches\n\tarm mcr 15 0 1 0 0 0\n\n\tarm mcr 15 0 15 2 4 0\n\n\t# invalidate TLBs\n\tarm mcr 15 0 8 7 0 0\n\n\t# Drain the write buffer\n\tarm mcr 15 0 7 10 4 0\n\n\t# start from AIPS 2GB region\n\tarm mcr 15 0 15 2 4 0x40000015\n}\n\nproc kindle2_sdram_init {} {\n\t#--------------------------------------------\n\t# Samsung K4X1G323PC-8GC3 32Mx32 Mobile DDR SDRAM\n\t#--------------------------------------------\n\t# SDCLK\n\tmww 0x43fac26c 0\n\n\t# CAS\n\tmww 0x43fac270 0\n\n\t# RAS\n\tmww 0x43fac274 0\n\n\t# CS2 (CSD0)\n\tmww 0x43fac27c 0x1000\n\n\t# DQM3\n\tmww 0x43fac284 0\n\n\t# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2dc)\n\tmww 0x43fac288 0\n\tmww 0x43fac28c 0\n\tmww 0x43fac290 0\n\tmww 0x43fac294 0\n\tmww 0x43fac298 0\n\tmww 0x43fac29c 0\n\tmww 0x43fac2a0 0\n\tmww 0x43fac2a4 0\n\tmww 0x43fac2a8 0\n\tmww 0x43fac2ac 0\n\tmww 0x43fac2b0 0\n\tmww 0x43fac2b4 0\n\tmww 0x43fac2b8 0\n\tmww 0x43fac2bc 0\n\tmww 0x43fac2c0 0\n\tmww 0x43fac2c4 0\n\tmww 0x43fac2c8 0\n\tmww 0x43fac2cc 0\n\tmww 0x43fac2d0 0\n\tmww 0x43fac2d4 0\n\tmww 0x43fac2d8 0\n\tmww 0x43fac2dc 0\n\n\t# ?\n\tmww 0xb8002000 0x00006602\n\tmww 0xb8002004 0x00000501\n\tmww 0xb8002008 0x00000000\n\n\t# LPDDR1 Initialization script\n\tmww 0xb8001010 0x00000002\n\tmww 0xb8001010 0x00000004\n\t# ESDCFG0: set timing parameters\n\tmww 0xb8001004 0x007fff7f\n\t# ESDCTL0: select Prechare-All mode\n\tmww 0xb8001000 0x92100000\n\tmww 0x80000f00 0x12344321\n\t# ESDCTL0: Auto Refresh\n\tmww 0xb8001000 0xa2100000\n\tmww 0x80000000 0x12344321\n\tmww 0x80000000 0x12344321\n\t# ESDCTL0: Load Mode Register\n\tmww 0xb8001000 0xb2100000\n\tmwb 0x80000033 0xda\n\tmwb 0x81000000 0xff\n\t# ESDCTL0: enable Auto-Refresh\n\tmww 0xb8001000 0x82226080\n\tmww 0x80000000 0xdeadbeef\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/kontron_sl28.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Kontron SMARC-sAL28\n\ntransport select jtag\nreset_config srst_only srst_nogate\n\njtag newtap unknown0 tap -irlen 12\n\nset _CPUS 2\nsource [find target/ls1028a.cfg]\n\nsource [find tcl/cpld/altera-epm240.cfg]\n\nadapter speed 2000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/kwikstik.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale KwikStik development board\n#\n\n#\n# JLINK interface is onboard\n#\nsource [find interface/jlink.cfg]\n\nsource [find target/k40.cfg]\n\nreset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/la_fonera-fon2200.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/atheros_ar2315.cfg]\n\nreset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/lambdaconcept_ecpix-5.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# LambdaConcept ECPIX-5\n# http://docs.lambdaconcept.com/ecpix-5/\n# Currently there are following board variants:\n# ECPIX-5 45F - LFE5UM5G-45F\n# ECPIX-5 85F - LFE5UM5G-85F\n#\n# This boards have two JTAG interfaces:\n# - CN4, micro USB port connected to FT2232HQ chip:\n#        ADBUS0 TCK\n#        ADBUS1 TDI\n#        ADBUS2 TDO\n#        ADBUS3 TMS\n#        BDBUS0 UART_TXD\n#        BDBUS1 UART_RXD\n#   This interface should be used with following config:\n#        interface/ftdi/lambdaconcept_ecpix-5.cfg\n# - CN3, 6 pin connector\n# See schematics for more details:\n# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF\n#\n# No reset lines are implemented. So it is not possible to remote reset the FPGA\n# by using any of this interfaces\n\nsource [find interface/ftdi/lambdaconcept_ecpix-5.cfg]\nsource [find fpga/lattice_ecp5.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/lemaker_hikey.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# board configuration for LeMaker Hikey\n#\n\n# board does not feature anything but JTAG\ntransport select jtag\n\n# SRST-only reset configuration\nreset_config srst_only srst_push_pull\n\nsource [find target/hi6220.cfg]\n\n# make sure the default target is the boot core\ntargets ${_TARGETNAME}0\n\nproc core_up { args } {\n\tglobal _TARGETNAME\n\n\t# examine remaining cores\n\tforeach _core $args {\n\t\t${_TARGETNAME}$_core arp_examine\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/linksys-wag200g.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Linksys WAG200G Router\n#\n# The stock firmware Flash layout is organized as follow:\n#\n#   Start       End         Device\n#   0x90000000  0x90020000  /dev/mtdblock/2\n#   0x90020000  0x900d0000  /dev/mtdblock/1\n#   0x900d0000  0x903a0000  /dev/mtdblock/0\n#   0x903a0000  0x903e0000  /dev/mtdblock/5\n#   0x903e0000  0x903f0000  /dev/mtdblock/3\n#   0x903f0000  0x90400000  /dev/mtdblock/4\n\nset partition_list {\n    adam2\t{ \"Adam2 bootloader\"\t\t0x90000000 0x00020000 }\n    kernel\t{ \"Kernel\"\t\t\t0x90020000 0x000b0000 }\n    rootfs\t{ \"Root FS\"\t\t\t0x900d0000 0x002d0000 }\n    lang\t{ \"Minix language part\"\t\t0x903a0000 0x00040000 }\n    config\t{ \"Firmware config\"\t\t0x903e0000 0x00010000 }\n    adam2env\t{ \"Adam2 environment\"\t\t0x903f0000 0x00010000 }\n}\n\nsource [find target/ti-ar7.cfg]\n\n# External 4MB MXIC 29LV320MBTC Flash (Manufacturer/Device: 0x00c2 0x227e)\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/linksys-wrt54gl.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Linksys WRT54GL v1.1\n#\n\nsource [find target/bcm5352e.cfg]\n\nset partition_list {\n    CFE\t\t{ Bootloader\t\t\t0x1c000000 0x00040000 }\n    firmware\t{ \"Kernel+rootfs\"\t\t0x1c040000 0x003b0000 }\n    nvram\t{ \"Config space\"\t\t0x1c3f0000 0x00010000 }\n}\n\n# External 4MB NOR Flash (Intel TE28F320C3BD90 or similar)\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x1c000000 0x00400000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/linksys_nslu2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is for the LinkSys (CISCO) NSLU2 board\n# It is an Intel XSCALE IXP420 CPU.\n\nsource [find target/ixp42x.cfg]\n# The _TARGETNAME is set by the above.\n\n$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/lisa-l.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# the Lost Illusions Serendipitous Autopilot\n# http://paparazzi.enac.fr/wiki/Lisa\n\n# Work-area size (RAM size) = 20kB for STM32F103RB device\nset WORKAREASIZE 0x5000\n\nsource [find target/stm32f1x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/logicpd_imx27.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The LogicPD Eval IMX27 eval board has a single IMX27 chip\nsource [find target/imx27.cfg]\n\n# The Logic PD board has a NOR flash on CS0\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME\n\n#\n# FIX ME, Add support to\n#\n# (A) hard reset the board.\n# (B) Initialize the SDRAM on the board\n#\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/lpc1850_spifi_generic.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Generic LPC1850 board w/ SPIFI flash.\n# This config file is intended as an example of how to\n# use the lpcspifi flash driver, but it should be functional\n# for most LPC1850 boards utilizing SPIFI flash.\n\nset CHIPNAME lpc1850\n\nsource [find target/lpc1850.cfg]\n\n#A large working area greatly reduces flash write times\nset _WORKAREASIZE 0x4000\n\n$_CHIPNAME.m3 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE\n\n#Configure the flash bank; 0x14000000 is the base address for\n#lpc43xx/lpc18xx family micros.\nflash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m3\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/lpc4350_spifi_generic.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Generic LPC4350 board w/ SPIFI flash.\n# This config file is intended as an example of how to\n# use the lpcspifi flash driver, but it should be functional\n# for most LPC4350 boards utilizing SPIFI flash.\n\nset CHIPNAME lpc4350\n\nsource [find target/lpc4350.cfg]\n\n#Configure the flash bank; 0x14000000 is the base address for\n#lpc43xx/lpc18xx family micros.\nflash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/lubbock.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Intel \"Lubbock\" Development Board with PXA255 (dbpxa255)\n#  Obsolete; this was Intel's original PXA255 development system\n#  Board also had CPU cards for SA1100, PXA210, PXA250, and more.\n\nsource [find target/pxa255.cfg]\n\nadapter srst delay 250\njtag_ntrst_delay 250\n\n# NOTE: until after pinmux and such are set up, only CS0 is\n# available ... not 2nd bank of CFI, or FPGA, SRAM, ENET, etc.\n\n# CS0, CS1 -- two banks of CFI flash, 32 MBytes each\n# each bank is 32-bits wide, two 16-bit chips in parallel\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME\n\n# CS2 low -- FPGA registers\n# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch\n$_TARGETNAME configure -work-area-phys 0x0a0f0000\n\n$_TARGETNAME configure -event reset-assert-pre \\\n\t\"$_TARGETNAME configure -work-area-size 0\"\n\n# Make the hex led display a number, assuming CS2 is set up\n# and all digits have been enabled through the FPGA.\nproc hexled {u32} {\n\tmww 0x08000010 $u32\n}\n\n# CS3 -- Ethernet\n# CS4 -- SA1111\n# CS5 -- PCMCIA\n\n# NOTE:  system console normally uses the FF UART connector\n\nproc lubbock_init {target} {\n\n\techo \"Initialize PXA255 Lubbock board\"\n\n\t# (1) pinmux\n\n\t# GPSR0..GPSR2\n\tmww 0x40e00018 0x00008000\n\tmww 0x40e0001c 0x00FC0382\n\tmww 0x40e00020 0x0001FFFF\n\t# GPDR0..GPDR2\n\tmww 0x40e0000c 0x0060A800\n\tmww 0x40e00010 0x00FF0382\n\tmww 0x40e00014 0x0001C000\n\t# GAFR0_[LU]..GAFR2_[LU]\n\tmww 0x40e00054 0x98400000\n\tmww 0x40e00058 0x00002950\n\tmww 0x40e0005c 0x000A9558\n\tmww 0x40e00060 0x0005AAAA\n\tmww 0x40e00064 0xA0000000\n\tmww 0x40e00068 0x00000002\n\n\t# write PSSR, enable GPIOs\n\tmww 0x40f00000 0x00000020\n\n\t# write LED ctrl register ... ones disable\n\t# high byte, 8 hex leds; low byte, 8 discretes\n\tmwh 0x08000040 0xf0ff\n\n\thexled 0x0000\n\n\t# (2) Address space setup\n\n\t# MSC0/MSC1/MSC2\n\tmww 0x48000008 0x23f223f2\n\tmww 0x4800000c 0x3ff1a441\n\tmww 0x48000010 0x7ff97ff1\n\t# pcmcia/cf\n\tmww 0x48000014 0x00000000\n\tmww 0x48000028 0x00010504\n\tmww 0x4800002c 0x00010504\n\tmww 0x48000030 0x00010504\n\tmww 0x48000034 0x00010504\n\tmww 0x48000038 0x00004715\n\tmww 0x4800003c 0x00004715\n\n\thexled 0x1111\n\n\t# (3) SDRAM setup\n\t# REVISIT this looks dubious ... no refresh cycles\n\tmww 0x48000004 0x03CA4018\n\tmww 0x48000004 0x004B4018\n\tmww 0x48000004 0x000B4018\n\tmww 0x48000004 0x000BC018\n\tmww 0x48000000 0x00001AC8\n\tmww 0x48000000 0x00001AC9\n\n\tmww 0x48000040 0x00000000\n\n\t# FIXME -- setup:\n\t#  CLOCKS (and faster JTAG)\n\t#  enable icache\n\n\t# FIXME SRAM isn't working\n\t# $target configure -work-area-size 0x10000\n\n\thexled 0x2222\n\n\tflash probe 0\n\tflash probe 1\n\n\thexled 0xcafe\n}\n$_TARGETNAME configure -event reset-init \"lubbock_init $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/marsohod.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Marsohod CPLD Development and Education board\n#\n# http://marsohod.org/howtostart/plata\n#\n\n# Recommended MBFTDI programmer\nsource [find interface/ftdi/mbftdi.cfg]\nadapter speed 2000\ntransport select jtag\n\n# Altera MAXII EPM240T100C CPLD\nsource [find cpld/altera-epm240.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/marsohod2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Marsohod2 FPGA Development and Education board\n#\n# http://www.marsohod.org/prodmarsohod2\n#\n\n# Built-in MBFTDI programmer\nsource [find interface/ftdi/mbftdi.cfg]\nadapter speed 2000\ntransport select jtag\n\n# Cyclone III EP3C10E144 FPGA\nsource [find fpga/altera-ep3c10.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/marsohod3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Marsohod3 FPGA Development and Education board\n#\n# http://www.marsohod.org/plata-marsokhod3\n#\n\n# Built-in MBFTDI programmer\nsource [find interface/ftdi/mbftdi.cfg]\nadapter speed 2000\ntransport select jtag\n\n# MAX10 10M50SAE144C8GES FPGA\nsource [find fpga/altera-10m50.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/mbed-lpc11u24.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an mbed eval board with a single NXP LPC11U24 chip.\n# http://mbed.org/handbook/mbed-NXP-LPC11U24\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# NXP LPC11U24 Cortex-M0 with 32kB Flash and 8kB SRAM\nset WORKAREASIZE 0x2000\n\nsource [find target/lpc11xx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/mbed-lpc1768.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an mbed eval board with a single NXP LPC1768 chip.\n# http://mbed.org/handbook/mbed-NXP-LPC1768\n#\n\nsource [find interface/cmsis-dap.cfg]\n\nsource [find target/lpc17xx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/mcb1700.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Keil MCB1700 PCB with 1768\n#\n# Reset init script sets it to 100MHz\nset CCLK 100000\n\nsource [find target/lpc17xx.cfg]\n\nglobal MCB1700_CCLK\nset MCB1700_CCLK $CCLK\n\n$_TARGETNAME configure -event reset-start {\n\t# Start *real slow* as we do not know the\n    # state the boot rom left the clock in\n\tadapter speed 10\n}\n\n# Set up 100MHz clock to CPU\n$_TARGETNAME configure -event reset-init {\n    # PLL0CON: Disable PLL\n\tmww 0x400FC080 0x00000000\n    # PLLFEED\n\tmww 0x400FC08C 0x000000AA\n    # PLLFEED\n\tmww 0x400FC08C 0x00000055\n\n    # CCLK=PLL/4 (=100 MHz)\n\tmww 0x400FC104 0x00000003\n    # CLKSRCSEL: Clock source = internal RC oscillator\n\tmww 0x400FC10C 0x00000000\n\n    # PLL0CFG: M=50,N=1 -> PLL=400 MHz\n\tmww 0x400FC084 0x00000031\n    # PLLFEED\n\tmww 0x400FC08C 0x000000AA\n    # PLLFEED\n\tmww 0x400FC08C 0x00000055\n\n\t# PLL0CON: Enable PLL\n\tmww 0x400FC080 0x00000001\n    # PLLFEED\n\tmww 0x400FC08C 0x000000AA\n    # PLLFEED\n\tmww 0x400FC08C 0x00000055\n\n\tsleep 50\n\n    # PLL0CON: Connect PLL\n\tmww 0x400FC080 0x00000003\n    # PLLFEED\n\tmww 0x400FC08C 0x000000AA\n    # PLLFEED\n\tmww 0x400FC08C 0x00000055\n\n\t# Dividing CPU clock by 8 should be pretty conservative\n\t#\n\t#\n\tglobal MCB1700_CCLK\n\tadapter speed [expr {$MCB1700_CCLK / 8}]\n\n\t# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select\n\t# \"User Flash Mode\" where interrupt vectors are _not_ remapped,\n\t# and reside in flash instead).\n\t#\n\t# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description\n\t# Bit Symbol Value Description Reset\n\t# value\n\t# 0 MAP Memory map control. 0\n\t# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.\n\t# 1 User mode. The on-chip Flash memory is mapped to address 0.\n\t# 31:1 - Reserved. The value read from a reserved bit is not defined. NA\n\t#\n\t# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user\n\n\tmww 0x400FC040 0x01\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/microchip_explorer16.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Microchip Explorer 16 with PIC32MX360F512L PIM module.\n# http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en024858\n\n# TAPID for PIC32MX360F512L\nset CPUTAPID 0x30938053\n\n# use 32k working area\nset WORKAREASIZE 32768\n\nsource [find target/pic32mx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/microchip_sama5d27_som1_kit1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Microchip SAMA5D27-SOM1-EK1\n# https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMA5D27-SOM1-EK1\n# This board provide two jtag interfaces:\n# J11 - 10 pin interface\n# J10 - USB interface connected to the J-Link-OB.\n#       This functionality is implemented with an ATSAM3U4C microcontroller and\n#       provides JTAG functions and a bridge USB/Serial debug port (CDC).\n#\n# Jumper J7 disables the J-Link-OB-ATSAM3U4C JTAG functionality.\n# - Jumper J7 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional.\n# - Jumper J7 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG\n#   controller can be used through the 10-pin JTAG port J11.\n\nsource [find interface/jlink.cfg]\nreset_config srst_only\n\nsource [find target/at91sama5d2.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/microchip_same51_curiosity_nano.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Microchip SAME51 Curiosity Nano evaluation kit.\n#\n# https://www.microchip.com/en-us/development-tool/EV76S68A\n#\n\nsource [find interface/cmsis-dap.cfg]\n\nset CHIPNAME same51\n\nsource [find target/atsame5x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/microchip_same54_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Microchip (former Atmel) SAM E54 Xplained Pro evaluation kit.\n# http://www.microchip.com/developmenttools/productdetails.aspx?partno=atsame54-xpro\n#\n\nsource [find interface/cmsis-dap.cfg]\n\nset CHIPNAME same54\n\nsource [find target/atsame5x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/microchip_saml11_xplained_pro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Microchip (formerly Atmel) SAM L11 Xplained Pro Evaluation Kit.\n# https://www.microchip.com/DevelopmentTools/ProductDetails/dm320205\n#\n\nsource [find interface/cmsis-dap.cfg]\nadapter speed 1000\n\nset CHIPNAME saml11\nsource [find target/atsaml1x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/mini2440.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#-------------------------------------------------------------------------\n# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R\n# NOTE: Configured for NAND boot (switch S2 in NANDBOOT)\n# 64 MB NAND (Samsung K9D1208V0M)\n# B Findlay  08/09\n#\n#   ----------- Important notes to help you on your way ----------\n# README:\n#     NOR/NAND Boot Switch - I have not read the vivi source, but from\n#     what I could tell from reading the registers it appears that vivi\n#     loads itself into DRAM and then flips NFCONT (0x4E000004) bits\n#     Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND\n#     FLASH at the bottom 64MB of memory. This essentially takes the\n#     NOR Flash out of the circuit so you can't trash it.\n#\n#     I adapted the samsung_s3c2440.cfg file which is why I did not\n#     include \"source [find target/samsung_s3c2440.cfg]\".  I believe\n#     the -work-area-phys 0x200000 is incorrect, but also had to pad\n#     some additional resets.  I didn't modify it as if it is working\n#     for someone, the work-area-phys is not used by most.\n#\n#     JTAG ADAPTER SPECIFIC\n#     IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely\n#     FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.\n#     This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is\n#     necessary to FORCE setting the clock. Normally this should be configured\n#     in the openocd.cfg file, but was placed here as it can be a tough\n#     problem to figure out.  THIS MAY NOT FIX YOUR PROBLEM.. I modified\n#     the openOCD driver jlink.c and posted it here. It may eventually end\n#     up changed in openOCD, but its a hack in the driver and really should\n#     be in the jtag layer (core.c me thinks), but haven't done it yet. My\n#     hack for jlink.c may be found here.\n#\n#     http://forum.sparkfun.com/viewtopic.php?t=16763&sid=946e65abdd3bab39cc7d90dee33ff135\n#\n#     Note: Also if you have a USB JTAG, you will need the USB library installed\n#     on your system \"libusb-dev\" or the make of openocd will fail. I *think*\n#     it's apt-get install libusb-dev.  When I made my config I only included\n#     --enable-jlink and --enable-usbdevs\n#\n#     I HAVE NOT Tested this thoroughly, so there could still be problems.\n#     But it should get you way ahead of the game from where I started.\n#     If you find problems (and fixes) please post them to\n#     openocd-development@lists.berlios.de and join the developers and\n#     check in fixes to this and anything else you find.  I do not\n#     provide support, but if you ask really nice and I see anything\n#     obvious I will tell you.. mostly just dig, fix, and submit to openocd.\n#\n#     best!   brfindla@yahoo.com   Nashua, NH USA\n#\n#     Recommended resources:\n#       - first two are the best Mini2440 resources anywhere\n#       - maintained by buserror... thanks guy!\n#\n#       http://bliterness.blogspot.com/\n#       http://code.google.com/p/mini2440/\n#\n#       others....\n#\n#       http://forum.sparkfun.com/viewforum.php?f=18\n#       http://labs.kernelconcepts.de/Publications/Micro24401/\n#       http://www.friendlyarm.net/home\n#       http://www.amontec.com/jtag_pinout.shtml\n#\n#-------------------------------------------------------------------------\n#\n#\n# Your openocd.cfg file should contain:\n# source [find interface/<yourjtag>.cfg]\n# source [find board/mini2440.cfg]\n#\n#\n#\n\n# FIXME use some standard target config, maybe create one from this\n#\n#\tsource [find target/...cfg]\n\n#-------------------------------------------------------------------------\n# Target configuration for the Samsung 2440 system on chip\n# Tested on a S3C2440 Evaluation board by keesj\n# Processor : ARM920Tid(wb) rev 0 (v4l)\n# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d\n#  (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)\n#-------------------------------------------------------------------------\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME s3c2440\n}\n\nif { [info exists ENDIAN] } {\n   set  _ENDIAN $ENDIAN\n} else {\n  # this defaults to a bigendian\n   set  _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x0032409d\n}\n\n#jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME\n$_TARGETNAME configure -work-area-phys 0x40000000  -work-area-size 0x4000 -work-area-backup 1\n\n#reset configuration\nadapter srst delay 100\njtag_ntrst_delay 100\nreset_config trst_and_srst\n\n#-------------------------------------------------------------------------\n# JTAG ADAPTER SPECIFIC\n# IMPORTANT! See README at top of this file.\n#-------------------------------------------------------------------------\n\n    adapter speed 12000\n\n#-------------------------------------------------------------------------\n# GDB Setup\n#-------------------------------------------------------------------------\n\n    gdb_breakpoint_override hard\n\n#------------------------------------------------\n# ARM SPECIFIC\n#------------------------------------------------\n\n    targets\n  #  arm7_9 dcc_downloads enable\n  #  arm7_9 fast_memory_access enable\n\n\n    nand device s3c2440 0\n\n    adapter srst delay 100\n    jtag_ntrst_delay 100\n    reset_config trst_and_srst\n    init\n\n    echo \" \"\n    echo \"-------------------------------------------\"\n    echo \"--- login with - telnet localhost 4444  ---\"\n    echo \"--- then type help_2440                 ---\"\n    echo \"-------------------------------------------\"\n    echo \" \"\n\n\n\n#------------------------------------------------\n# Processor Initialialization\n# Note: Processor writes can only occur when\n# the state is in SYSTEM. When you call init_2440\n# one of the first lines will tell you what state\n# you are in. If a linux image is booting\n# when you run this, it will not work\n# a vivi boot loader will run with this just\n# fine. The reg values were obtained by a combination\n# of figuring them out fromt the manual, and looking\n# at post vivi values with the debugger. Don't\n# place too much faith in them, but seem to work.\n#------------------------------------------------\n\nproc init_2440 { } {\n\n    halt\n    s3c2440.cpu curstate\n\n    #-----------------------------------------------\n    # Set Processor Clocks - mini2440 xtal=12mHz\n    # we set main clock for 405mHZ\n    # we set the USB Clock for 48mHz\n    # OM2 OM3 pulled to ground so main clock and\n    # usb clock are off 12mHz xtal\n    #-----------------------------------------------\n\n    mww phys 0x4C000014 0x00000005 ;#  Clock Divider control Reg\n    mww phys 0x4C000000 0xFFFFFFFF ;#  LOCKTIME count register\n    mww phys 0x4C000008 0x00038022 ;#  UPPLCON  USB clock config Reg\n    mww phys 0x4C000004 0x0007F021 ;#  MPPLCON  Proc clock config Reg\n\n    #-----------------------------------------------\n    # Configure Memory controller\n    # BWSCON configures all banks, NAND, NOR, DRAM\n    # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7\n    #-----------------------------------------------\n\n    mww phys 0x48000000 0x22111112 ;#  BWSCON - Bank and Bus Width\n    mww phys 0x48000010 0x00001112 ;#  BANKCON4 - ?\n    mww phys 0x4800001c 0x00018009 ;#  BANKCON6 - DRAM\n    mww phys 0x48000020 0x00018009 ;#  BANKCON7 - DRAM\n    mww phys 0x48000024 0x008E04EB ;#  REFRESH  - DRAM\n    mww phys 0x48000028 0x000000B2 ;#  BANKSIZE - DRAM\n    mww phys 0x4800002C 0x00000030 ;#  MRSRB6 - DRAM\n    mww phys 0x48000030 0x00000030 ;#  MRSRB7 - DRAM\n\n    #-----------------------------------------------\n    # Now port configuration for enables for memory\n    # and other stuff.\n    #-----------------------------------------------\n\n    mww phys 0x56000000\t0x007FFFFF ;#  GPACON\n\n    mww phys 0x56000010\t0x00295559 ;#  GPBCON\n    mww phys 0x56000018\t0x000003FF ;#  GPBUP (PULLUP ENABLE)\n    mww phys 0x56000014\t0x000007C2 ;#  GPBDAT\n\n    mww phys 0x56000020\t0xAAAAA6AA ;#  GPCCON\n    mww phys 0x56000028\t0x0000FFFF ;#  GPCUP\n    mww phys 0x56000024\t0x00000020 ;#  GPCDAT\n\n    mww phys 0x56000030\t0xAAAAAAAA ;#  GPDCON\n    mww phys 0x56000038\t0x0000FFFF ;#  GPDUP\n\n    mww phys 0x56000040\t0xAAAAAAAA ;#  GPECON\n    mww phys 0x56000048\t0x0000FFFF ;#  GPEUP\n\n    mww phys 0x56000050\t0x00001555 ;#  GPFCON\n    mww phys 0x56000058\t0x0000007F ;#  GPFUP\n    mww phys 0x56000054\t0x00000000 ;#  GPFDAT\n\n    mww phys 0x56000060\t0x00150114 ;#  GPGCON\n    mww phys 0x56000068\t0x0000007F ;#  GPGUP\n\n    mww phys 0x56000070\t0x0015AAAA ;#  GPHCON\n    mww phys 0x56000078\t0x000003FF ;#  GPGUP\n\n}\n\n\n\nproc flash_config { } {\n\n    #-----------------------------------------\n    # Finish Flash Configuration\n    #-----------------------------------------\n\n    halt\n\n    #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)\n    nand probe 0\n    nand list\n}\n\nproc flash_uboot { } {\n\n\t# flash the u-Boot binary and reboot into it\n\tinit_2440\n\tflash_config\n\tnand erase 0 0x0 0x40000\n\tnand write 0 /tftpboot/u-boot-nand512.bin 0 oob_softecc_kw\n\tresume\n}\n\n\nproc load_uboot { } {\n        echo \" \"\n        echo \" \"\n        echo \"----------------------------------------------------------\"\n        echo \"---- Load U-Boot into RAM and execute it.              ---\"\n        echo \"---- NOTE: loads, partially runs, and hangs            ---\"\n        echo \"---- U-Boot is fine, this image runs from vivi.        ---\"\n        echo \"---- I burned u-boot into NAND so I didn't finish      ---\"\n        echo \"---- debugging it. I am leaving this here as it is     ---\"\n        echo \"---- part of the way there if you want to fix it.      ---\"\n        echo \"----                                                   ---\"\n        echo \"---- mini2440 U-boot here:                             ---\"\n        echo \"---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git  ---\"\n        echo \"---- Also this:                                        ---\"\n        echo \"---- http://code.google.com/p/mini2440/wiki/MiniBringup --\"\n        echo \"----------------------------------------------------------\"\n\n\tinit_2440\n\techo \"Loading /tftpboot/u-boot-nand512.bin\"\n\tload_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin\n\techo \"Verifying image....\"\n\tverify_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin\n\techo \"jumping to u-boot\"\n        #bp 0x33f80068 4 hw\n        reg 0 0\n        reg 1 0\n        reg 2 0\n        reg 3 0\n        reg 4 0x33f80000\n      \tresume 0x33f80000\n}\n\n       # this may help a little bit debugging the load_uboot\nproc s {} {\n        step\n        reg\n        arm disassemble 0x33F80068 0x10\n}\n\nproc help_2440 {} {\n    echo \" \"\n    echo \" \"\n    echo \"-----------------------------------------------------------\"\n    echo \"---- The following mini2440 funcs are supported        ----\"\n    echo \"----   init_2440 - initialize clocks, DRAM, IO         ----\"\n    echo \"----   flash_config - configures nand flash            ----\"\n    echo \"----   load_uboot - loads uboot into ram               ----\"\n    echo \"----   flash_uboot - flashes uboot to nand (untested)  ----\"\n    echo \"----   help_2440 - this help display                   ----\"\n    echo \"-----------------------------------------------------------\"\n    echo \" \"\n    echo \" \"\n}\n\n\n#----------------------------------------------------------------------------\n#----------------------------------- END ------------------------------------\n#----------------------------------------------------------------------------\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/mini6410.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Target configuration for the Samsung s3c6410 system on chip\n# Tested on a tiny6410\n# Processor       : ARM1176\n# Info : JTAG tap: s3c6410.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2)\n# Info : JTAG tap: s3c6410.cpu tap/device found: 0x07b76f0f (mfg: 0x787, part: 0x7b76, ver: 0x0)\n\nsource [find target/samsung_s3c6410.cfg]\n\nproc init_6410 {} {\n\thalt\n\treg cpsr 0x1D3\n\tarm mcr 15 0 15 2 4 0x70000013\n\n\t#-----------------------------------------------\n\t# Clock and Timer Setting\n\t#-----------------------------------------------\n\tmww 0x7e004000 0\t\t;# WATCHDOG \t- Disable\n\tmww 0x7E00F120 0x0003\t\t;# MEM_SYS_CFG\t- CS0:8 bit, Mem1:32bit, CS2=NAND\n\t#mww 0x7E00F120 0x1000\t\t;# MEM_SYS_CFG\t- CS0:16bit, Mem1:32bit, CS2=SROMC\n\t#mww 0x7E00F120 0x1002\t\t;# MEM_SYS_CFG\t- CS0:16bit, Mem1:32bit, CS2=OND\n\tmww 0x7E00F900 0x805e\t\t;# OTHERS\t- Change SYNCMUX[6] to “1”\n\tsleep 1000\n\tmww 0x7E00F900 0x80de\t\t;# OTHERS\t- Assert SYNCREQ&VICSYNCEN to “1”(rb1004modify)\n\tsleep 1000\t\t\t;#\t\t- Others[11:8] to 0xF\n\tmww 0x7E00F000 0xffff\t\t;# APLL_LOCK\t- APLL LockTime\n\tmww 0x7E00F004 0xffff\t\t;# MPLL_LOCK\t- MPLL LockTime\n\tmww 0x7E00F020 0x1047310\t;# CLK_DIV0 \t- ARMCLK:HCLK:PCLK = 1:4:16\n\tmww 0x7E00F00c 0x81900302\t;# APLL_CON \t- A:400, P:3, S:2 => 400MHz\n\tmww 0x7E00F010 0x81900303\t;# MPLL_CON \t- M:400, P:3, S:3 => 200MHz\n\tmww 0x7E00F01c 0x3\t\t;# CLK_SRC \t- APLL,MPLL Clock Select\n\n\t#-----------------------------------------------\n\t# DRAM initialization\n\t#-----------------------------------------------\n\tmww 0x7e001004 0x4\t\t;# P1MEMCCMD\t- Enter the config state\n\tmww 0x7e001010 0x30C\t\t;# P1REFRESH\t- Refresh Period register (7800ns), 100MHz\n#\tmww 0x7e001010 0x40e\t\t;# P1REFRESH\t- Refresh Period register (7800ns), 133MHz\n\tmww 0x7e001014 0x6\t\t;# P1CASLAT\t- CAS Latency = 3\n\tmww 0x7e001018 0x1\t\t;# P1T_DQSS\n\tmww 0x7e00101c 0x2\t\t;# P1T_MRD\n\tmww 0x7e001020 0x7\t\t;# P1T_RAS\t- 45 ns\n\tmww 0x7e001024 0xA\t\t;# P1T_RC\t- 67.5 ns\n\tmww 0x7e001028 0xC\t\t;# P1T_RCD\t- 22.5 ns\n\tmww 0x7e00102C 0x10B\t\t;# P1T_RFC\t- 80 ns\n\tmww 0x7e001030 0xC\t\t;# P1T_RP\t- 22.5 ns\n\tmww 0x7e001034 0x3\t\t;# P1T_RRD\t- 15 ns\n\tmww 0x7e001038 0x3\t\t;# P1T_WR\t- 15 ns\n\tmww 0x7e00103C 0x2\t\t;# P1T_WTR\n\tmww 0x7e001040 0x2\t\t;# P1T_XP\n\tmww 0x7e001044 0x11\t\t;# P1T_XSR\t- 120 ns\n\tmww 0x7e001048 0x11\t\t;# P1T_ESR\n\n\t#-----------------------------------------------\n\t# Memory Configuration Registers\n\t#-----------------------------------------------\n\tmww 0x7e00100C 0x00010012 \t;# P1MEMCFG\t- 1 CKE, 1Chip, 4burst, Alw, AP[10],ROW/Column bit\n\tmww 0x7e00104C 0x0B41 \t\t;# P1MEMCFG2\t- Read delay 1 Cycle, mDDR, 32bit, Sync.\n\tmww 0x7e001200 0x150F0 \t\t;# CHIP_N_CFG\t- 0x150F0 for 256M, 0x150F8 for 128M\n\n\t#-----------------------------------------------\n\t# Memory Direct Commands\n\t#-----------------------------------------------\n\tmww 0x7e001008 0xc0000\t\t;# Chip0 Direct Command :NOP5\n\tmww 0x7e001008 0x0\t\t;# Chip0 Direct Command :PreCharge al\n\tmww 0x7e001008 0x40000\t\t;# Chip0 Direct Command :AutoRefresh\n\tmww 0x7e001008 0x40000\t\t;# Chip0 Direct Command :AutoRefresh\n\tmww 0x7e001008 0xA0000\t\t;# EMRS, DS:Full, PASR:Full\n\tmww 0x7e001008 0x80032\t\t;# MRS, CAS3, BL4\n\tmww 0x7e001004 0x0\t\t;# Enable DMC1\n}\n\nproc install_6410_uboot {} {\n\t# write U-boot magic number\n\tmww 0x50000000 0x24564236\n\tmww 0x50000004 0x20764316\n\tload_image u-boot_nand-ram256.bin 0x50008000 bin\n\tload_image u-boot_nand-ram256.bin 0x57E00000 bin\n\n\t#Kick in\n\treg pc 0x57E00000\n\tresume\n}\n\nproc init_6410_flash {} {\n\thalt\n\tnand probe 0\n\tnand list\n}\n\n\nadapter speed 1000\nadapter srst delay 100\njtag_ntrst_delay 100\nreset_config trst_and_srst\n\ngdb_breakpoint_override hard\n\ntargets\nnand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu\n\ninit\necho \" \"\necho \" \"\necho \"-------------------------------------------------------------------\"\necho \"---- The following mini6410/tiny6410 functions are available:  ----\"\necho \"----   init_6410 - initialize clock, timer, DRAM               ----\"\necho \"----   init_6410_flash - initializes NAND flash support        ----\"\necho \"----   install_6410_uboot - copies u-boot image into RAM and   ----\"\necho \"----                        runs it                            ----\"\necho \"-------------------------------------------------------------------\"\necho \" \"\necho \" \"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/minispartan6.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# https://www.scarabhardware.com/minispartan6/\n\nsource [find interface/ftdi/minispartan6.cfg]\nsource [find cpld/xilinx-xc6s.cfg]\nsource [find cpld/jtagspi.cfg]\n\n# example command to read the device dna of the FPGA on the board;\n# openocd -f board/minispartan6.cfg -c \"init;xc6s_print_dna xc6s.tap;shutdown\"\n\n# example command to write bitstream\n# openocd -f board/minispartan6.cfg -c \"init;\\\n# jtagspi_init 0 bscan_spi_xc6slx??.bit;\\\n# jtagspi_program bitstream.bin 0;\\\n# xc6s_program xc6s.tap;\\\n# shutdown\"\n#\n# jtagspi flash procies can be found in the contrib/loaders/flash/fpga/\n# directory, with prebuilt versions available at\n# https://github.com/jordens/bscan_spi_bitstreams\n#\n# For the SLX25 variant, use\n#  - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx25.bit\n# For the SLX9 variant, use\n#  - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx9.bit\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nds32_corvettef1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# ADP-Corvette-F1 R1.0\n# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r1/\n# ADP-Corvette-F1 R2.0\n# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r2/\n\nadapter speed     10000\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0c08 0x0f1b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\nreset_config srst_only\n\nsource [find target/nds32v5.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nds32_xc7.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# ADP-XC7K160/410\n# http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/\n\nsource [find target/nds32v5.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/netgear-dg834v3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Netgear DG834v3 Router\n# Internal 4Kb RAM (@0x80000000)\n# Flash is located at 0x90000000 (CS0) and RAM is located at 0x94000000 (CS1)\n#\n\nset partition_list {\n    loader\t{ \"Bootloader (ADAM2)\"\t\t0x90000000 0x00020000 }\n    firmware\t{ \"Kernel+rootfs\"\t\t0x90020000 0x003d0000 }\n    config\t{ \"Bootloader config space\"\t0x903f0000 0x00010000 }\n}\n\nsource [find target/ti-ar7.cfg]\n\n# External 16MB SDRAM - disabled as we use internal sram\n#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000\n\n# External 4MB NOR Flash\nset _FLASHNAME $_CHIPNAME.norflash\nflash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/netgear-wg102.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/atheros_ar2313.cfg]\n\nreset_config trst_and_srst\n\n$_TARGETNAME configure -event reset-init {\n\tmips32 cp0 12 0 0x10400000\n\n\t# configure sdram controller\n\tmww 0xb8300004 0x0e03\n\tsleep 100\n\tmww 0xb8300004 0x0e01\n\tmww 0xb8300008 0x10\n\tsleep 500\n\tmww 0xb8300004 0x0e02\n\n\tmww 0xb8300000 0x6c0088\n\tmww 0xb8300008 0x57e\n\tmww 0xb8300004 0x0e00\n\tmww 0xb8300004 0xb00\n\n\t# configure flash\n\t#                 0x00000001 - 0x01 << FLASHCTL_IDCY_S\n\t#                 0x000000e0 - 0x07 << FLASHCTL_WST1_S\n\t# FLASHCTL_RBLE   0x00000400 - Read byte lane enable\n\t#                 0x00003800 - 0x07 << FLASHCTL_WST2_S\n\t# FLASHCTL_AC_8M  0x00060000 - Size of flash\n\t# FLASHCTL_E      0x00080000 - Flash bank enable (added)\n\t# FLASHCTL_WP     0x04000000 - write protect. If used, CFI mode wont work!!\n\t# FLASHCTL_MWx16  0x10000000 - 16bit mode. Do not use it!!\n\t# FLASHCTL_MWx8   0x00000000 - 8bit mode.\n\tmww 0xb8400000 0x000d3ce1\n}\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0xbe000000 0x00400000 1 1 $_TARGETNAME x16_as_x8\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nordic_nrf51822_mkit.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Nordic Semiconductor PCA10024 board (aka nRF51822-mKIT)\n#\n\nsource [find interface/cmsis-dap.cfg]\nsource [find target/nrf51.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nordic_nrf51_dk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Nordic Semiconductor NRF51 Development Kit (nRF6824)\n#\n\nsource [find interface/jlink.cfg]\n\ntransport select swd\n\nsource [find target/nrf51.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nordic_nrf52_dk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Nordic Semiconductor NRF52 Development Kit (nRF52832)\n#\n\nsource [find interface/jlink.cfg]\n\ntransport select swd\n\nsource [find target/nrf52.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nordic_nrf52_ftx232.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# nordic module NRF52 (nRF52832/52840) attached to an adafruit ft232h module\n# or any FT232H/FT2232H/FT4232H based board/module\n#\n\nsource [find interface/ftdi/ft232h-module-swd.cfg]\n#source [find interface/ftdi/minimodule-swd.cfg]\n\ntransport select swd\n\nsource [find target/nrf52.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/novena-internal-fpga.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Novena open hardware and F/OSS-friendly computing platform\n#\n# Design documentation:\n# http://www.kosagi.com/w/index.php?title=Novena_PVT_Design_Source\n#\n# +-------------+--------------+------+-------+---------+\n# | Pad name    | Schematic    | GPIO | sysfs | JTAG    |\n# +-------------+--------------+------+-------+---------+\n# | DISP0_DAT13 | FPGA_RESET_N | 5-07 |  135  | RESET_N |\n# | DISP0_DAT14 | FPGA_TCK     | 5-08 |  136  | TCK     |\n# | DISP0_DAT15 | FPGA_TDI     | 5-09 |  137  | TDI     |\n# | DISP0_DAT16 | FPGA_TDO     | 5-10 |  138  | TDO     |\n# | DISP0_DAT17 | FPGA_TMS     | 5-11 |  139  | TMS     |\n# +-------------+--------------+------+-------+---------+\n\nadapter driver sysfsgpio\n\ntransport select jtag\n\n# TCK TMS TDI TDO\nsysfsgpio jtag_nums 136 139 137 138\n\nsource [find cpld/xilinx-xc6s.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/npcx_evb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Nuvoton NPCX Evaluation Board\n\nsource [find interface/jlink.cfg]\ntransport select swd\n\nsource [find target/npcx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/numato_mimas_a7.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Numato Mimas A7 - Artix 7 FPGA Board\n#\n# https://numato.com/product/mimas-a7-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet\n#\n# Note: Connect external DC power supply if programming a heavy design onto FPGA.\n#       Programming while powering via USB may lead to programming failure.\n#       Therefore, prefer external power supply.\n\nadapter driver ftdi\nftdi device_desc \"Mimas Artix 7 FPGA Module\"\nftdi vid_pid 0x2a19 0x1009\n\n# channel 0 is for custom purpose by users (like uart, fifo etc)\n# channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers)\nftdi channel 1\nftdi tdo_sample_edge falling\n\n\n# FTDI Pin Layout\n#\n# +--------+-------+-------+-------+-------+-------+-------+-------+\n# | DBUS7  | DBUS6 | DBUS5 | DBUS4 | DBUS3 | DBUS2 | DBUS1 | DBUS0 |\n# +--------+-------+-------+-------+-------+-------+-------+-------+\n# | PROG_B | OE_N  |  NC   |  NC   |  TMS  |  TDO  |  TDI  |  TCK  |\n# +--------+-------+-------+-------+-------+-------+-------+-------+\n#\n# OE_N is JTAG buffer output enable signal (active-low)\n# PROG_B is not used, so left as input to FTDI.\n#\nftdi layout_init 0x0008 0x004b\nreset_config none\nadapter speed 30000\n\nsource [find cpld/xilinx-xc7.cfg]\nsource [find cpld/jtagspi.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/numato_opsis.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# http://opsis.hdmi2usb.tv\n#\n# The Numato Opsis is an FPGA based, open video platform.\n#\n# The board is supported via ixo-usb-jtag project. See the\n# interface/usb-jtag.cfg for more information.\n\nsource [find interface/usb-jtag.cfg]\nsource [find cpld/xilinx-xc6s.cfg]\nsource [find cpld/jtagspi.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nxp_frdm-k64f.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an NXP Freedom eval board with a single MK64FN1M0VLL12 chip.\n# https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F\n#\n\nsource [find interface/cmsis-dap.cfg]\n\n# Set working area to 16 KiB\nset WORKAREASIZE 0x4000\n\nset CHIPNAME k64f\nreset_config srst_only\n\nsource [find target/kx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nxp_frdm-ls1012a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP FRDM-LS1012A (Freedom)\n#\n\n#\n# NXP Kinetis K20\n#\nsource [find interface/cmsis-dap.cfg]\ntransport select jtag\n\n# Also offers a 10-pin 0.05\" CoreSight JTAG connector.\n\nsource [find target/ls1012a.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nxp_imx7sabre.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP IMX7SABRE board\n# use on-board JTAG header\ntransport select jtag\n\n# set a safe speed, can be overridden\nadapter speed 1000\n\n# reset configuration has TRST and SRST support\nreset_config trst_and_srst srst_push_pull\n# need at least 100ms delay after SRST release for JTAG\nadapter srst delay 100\n\n# source the target file\nsource [find target/imx7.cfg]\n# import mrw proc\nsource [find mem_helper.tcl]\n\n# function to disable the on-chip watchdog\nproc imx7_disable_wdog { } {\n        # echo \"disable watchdog power-down counter\"\n        mwh phys 0x30280008 0x00\n}\n\nproc imx7_uart_dbgconf { } {\n\t# disable response to debug_req signal for uart1\n\tmww phys 0x308600b4 0x0a60\n}\n\nproc check_bits_set_32 { addr mask } {\n    while { [expr {[mrw $addr] & $mask} == 0] } { }\n}\n\nproc apply_dcd { } {\n    # echo \"apply dcd\"\n\n    mww phys 0x30340004 0x4F400005\n    # Clear then set bit30 to ensure exit from DDR retention\n    mww phys 0x30360388 0x40000000\n    mww phys 0x30360384 0x40000000\n\n    mww phys 0x30391000 0x00000002\n    mww phys 0x307a0000 0x01040001\n    mww phys 0x307a01a0 0x80400003\n    mww phys 0x307a01a4 0x00100020\n    mww phys 0x307a01a8 0x80100004\n    mww phys 0x307a0064 0x00400046\n    mww phys 0x307a0490 0x00000001\n    mww phys 0x307a00d0 0x00020083\n    mww phys 0x307a00d4 0x00690000\n    mww phys 0x307a00dc 0x09300004\n    mww phys 0x307a00e0 0x04080000\n    mww phys 0x307a00e4 0x00100004\n    mww phys 0x307a00f4 0x0000033f\n    mww phys 0x307a0100 0x09081109\n    mww phys 0x307a0104 0x0007020d\n    mww phys 0x307a0108 0x03040407\n    mww phys 0x307a010c 0x00002006\n    mww phys 0x307a0110 0x04020205\n    mww phys 0x307a0114 0x03030202\n    mww phys 0x307a0120 0x00000803\n    mww phys 0x307a0180 0x00800020\n    mww phys 0x307a0184 0x02000100\n    mww phys 0x307a0190 0x02098204\n    mww phys 0x307a0194 0x00030303\n    mww phys 0x307a0200 0x00000016\n    mww phys 0x307a0204 0x00171717\n    mww phys 0x307a0214 0x04040404\n    mww phys 0x307a0218 0x0f040404\n    mww phys 0x307a0240 0x06000604\n    mww phys 0x307a0244 0x00000001\n    mww phys 0x30391000 0x00000000\n    mww phys 0x30790000 0x17420f40\n    mww phys 0x30790004 0x10210100\n    mww phys 0x30790010 0x00060807\n    mww phys 0x307900b0 0x1010007e\n    mww phys 0x3079009c 0x00000d6e\n    mww phys 0x30790020 0x08080808\n    mww phys 0x30790030 0x08080808\n    mww phys 0x30790050 0x01000010\n    mww phys 0x30790050 0x00000010\n\n    mww phys 0x307900c0 0x0e407304\n    mww phys 0x307900c0 0x0e447304\n    mww phys 0x307900c0 0x0e447306\n\n    check_bits_set_32 0x307900c4 0x1\n\n    mww phys 0x307900c0 0x0e447304\n    mww phys 0x307900c0 0x0e407304\n\n\n    mww phys 0x30384130 0x00000000\n    mww phys 0x30340020 0x00000178\n    mww phys 0x30384130 0x00000002\n    mww phys 0x30790018 0x0000000f\n\n    check_bits_set_32 0x307a0004 0x1\n}\n\n# disable internal reset-assert handling to\n# allow reset-init to work\n$_TARGETNAME.0 configure -event reset-assert \"\"\n$_TARGETNAME.1 configure -event reset-assert \"\"\n$_TARGETNAME_2 configure -event reset-assert \"\"\n\n$_TARGETNAME.0 configure -event reset-init {\n    global _CHIPNAME\n    imx7_disable_wdog\n    imx7_uart_dbgconf\n    apply_dcd\n    $_CHIPNAME.dap memaccess 0\n}\n\ntarget smp $_TARGETNAME.0 $_TARGETNAME.1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nxp_lpc-link2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP LPC-Link2\n#\n# http://www.nxp.com/board/OM13054.html\n# https://www.lpcware.com/lpclink2\n# http://embeddedartists.com/products/lpcxpresso/lpclink2.php\n#\n\nsource [find target/lpc4370.cfg]\n\n# W25Q80BVSSIG w/ 1 MB flash\nflash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nxp_mcimx8m-evk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# configuration file for NXP MC-IMX8M-EVK\n#\n\n# only JTAG supported\ntransport select jtag\n\n# set a safe JTAG clock speed, can be overridden\nadapter speed 1000\n\n# default JTAG configuration has only SRST and no TRST\nreset_config srst_only srst_push_pull\n\n# delay after SRST goes inactive\nadapter srst delay 70\n\n# board has an i.MX8MQ with 4 Cortex-A53 cores\nset CHIPNAME imx8mq\nset CHIPCORES 4\n\n# source SoC configuration\nsource [find target/imx8m.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nxp_rdb-ls1046a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# NXP LS1046ARDB (Reference Design Board)\n# This is for the \"console\" USB port on the front panel\n# You must ensure that SW4-7 is in the \"off\" position\n\n# NXP K20\n# The firmware implements the old CMSIS-DAP v1 USB HID interface\n# You must pass --enable-cmsis-dap to ./configure to enable it\nsource [find interface/cmsis-dap.cfg]\n\ntransport select jtag\nreset_config srst_only\n\nsource [find target/ls1046a.cfg]\n\n# The adapter can't handle 10MHz\nadapter speed 5000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/nxp_rdb-ls1088a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# NXP LS1088ARDB (Reference Design Board)\n# This is for the \"main\" JTAG connector J55\n\ntransport select jtag\nreset_config srst_only\n\n# To access the CPLD, populate J48 and add `-c 'set CWTAP 1'` to your command\n# line. At the time of this writing, programming is unsupported.\nif { [info exists CWTAP] } {\n\tsource [find cpld/altera-epm240.cfg]\n} else {\n\tsource [find target/ls1088a.cfg]\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/olimex_LPC2378STK.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#####################################################\n# Olimex LPC2378STK eval board\n#\n# http://olimex.com/dev/lpc-2378stk.html\n#\n# Author: Sten, debian@sansys-electronic.com\n#####################################################\n#\n\nsource [find target/lpc2378.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/olimex_lpc_h2148.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Olimex LPC-H2148 eval board\n#\n# http://www.olimex.com/dev/lpc-h2148.html\n#\n\nsource [find target/lpc2148.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/olimex_sam7_ex256.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.\n\nsource [find target/at91sam7x256.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/olimex_sam7_la2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/at91sam7a2.cfg]\n\n# delays needed to get stable reads of cpu state\njtag_ntrst_delay 10\nadapter srst delay 200\n\n# board uses pullup and connects only srst\nreset_config srst_open_drain\n\n# srst is connected to NRESET of CPU and fully resets everything...\nreset_config srst_only srst_pulls_trst\n\nadapter speed 1\n$_TARGETNAME configure -event reset-start {\n\tadapter speed 1\n}\n\n$_TARGETNAME configure -event reset-init {\n\t# init script from http://www.mikrocontroller.net/topic/107462\n\t# AT91SAM7A2\n\t# AMC (advanced memory controller)\n\n\techo \"setting up AMC\"\n\t# AMC_CS0 - FLASH 1MB (0x40000000-0x400FFFFF) + DM9000E (0x40100000)\n\tmww 0xFFE00000 0x40003EBD\n\n\t# AMC_CS1 - RAM low 2MB (0x40400000-0x405FFFFF)\n\tmww 0xFFE00004 0x404030A9\n\n\t# AMC_CS2 - RAM high 2MB (0x40800000-0x405FFFFF)\n\t#mww 0xFFE00008 0x404030A9\n\t# changed to  0x40_8_\n\tmww 0xFFE00008 0x408030A9\n\n\t# AMC_MCR\n\tmww 0xFFE00024 0x00000004\n\n\t# AMC_RCR force remap\n\tmww 0xFFE00020 0x00000001\n\n\techo \"set up AMC\"\n\tsleep 100\n\n\t# the following base addresses from the original script did not correspond to those from datasheet\n\t# changed bases from 0xFF000000 to 0xFFF00000\n\n\t# disable watchdog, to prevent unwanted resets\n\tmww 0xFFFA0068 0x00000000\n\techo \"disabled watchdog\"\n\n\tsleep 50\n\n\t# disable PLL\n\tmww 0xFFFEC004 0x18070004\n\n\t# PLL = 10 ==> Coreclock = 6Mhz*10/2 = 30 Mhz\n\tmww 0xFFFEC010 0x762D800A\n\n\t# enable PLL\n\tmww 0xFFFEC000 0x23050004\n\techo \"set up pll\"\n\n\tsleep 100\n\tadapter speed 5000\n}\n\n$_TARGETNAME arm7_9 dcc_downloads enable\n$_TARGETNAME arm7_9 fast_memory_access enable\n\n# remap:  ram at 0, flash at 0x40000000, like reset-init above does\n$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1\nflash bank onboard.flash cfi 0x40000000 0x00100000 2 2 at91sam7a2.cpu\n\n# boot: ram at 0x300000, flash at 0x0, useful if board is in funny configuration\n#$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1\n#flash bank onboard1.flash cfi 0x00000000 0x00100000 2 2 at91sam7a2.cpu\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/olimex_sam9_l9260.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Olimex SAM9-L9260 Development Board\n#\n# http://www.olimex.com/dev/sam9-L9260.html\n#\n# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz\n#                     PMC configured for external 18.432 MHz crystal\n#\n# 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks\n# 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit\n# Dataflash : 1 x Atmel AT45DB161D, 16Mbit\n#\n################################################################################\n\nsource [find target/at91sam9260.cfg]\n\n# NTRST_E jumper is enabled by default, so we don't need to override the reset\n# config.\n#reset_config srst_only\n\n$_TARGETNAME configure -event reset-start {\n\t# At reset, CPU runs at 32.768 kHz.  JTAG frequency must be 6 times slower if\n\t# RCLK is not supported.\n\tjtag_rclk 5\n\thalt\n\n\t# RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may\n\t# be enabled... use physical address.\n\tmww phys 0xfffffd08 0xa5000501\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog\n\n\t##\n\t# Clock configuration for 99.328 MHz main clock.\n\t##\n    echo \"Setting up clock\"\n\tmww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup\n\tsleep 20                  ;# wait 20 ms (need 15.6 ms for startup)\n\tmww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz)\n\tsleep 10                  ;# wait 10 ms\n\tmww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup\n\tsleep 20                  ;# wait 20 ms (need 1.9 ms for startup)\n\tmww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2\n\tsleep 10                  ;# wait 10 ms\n\tmww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)\n\n\t# Increase JTAG speed to 6 MHz if RCLK is not supported.\n\tjtag_rclk 6000\n\n\tarm7_9 dcc_downloads enable ;# Enable faster DCC downloads.\n\n\t##\n\t# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.\n\t##\n    echo \"Configuring SDRAM\"\n\tmww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31\n\tmww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31\n\n\tmww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory\n\n\tmww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips\n\n\tmww 0xffffea00 0x1        ;# SDRAMC_MR : issue NOP command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x2        ;# SDRAMC_MR : issue an 'All Banks Precharge' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4        ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x3        ;# SDRAMC_MR : issue a 'Load Mode Register' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x0        ;# SDRAMC_MR : normal mode\n\tmww 0x20000000 0\n\n\tmww 0xffffea04 0x2b6      ;# SDRAMC_TR : set refresh timer count to 7 us\n\n    ##\n    # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.\n    ##\n    echo \"Configuring NAND flash\"\n    mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock\n    mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)\n    mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14\n    mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13\n    mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND\n    mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13\n\n    mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before\n\n    mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE\n    mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals\n    mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle\n    mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,\n                               #             3 TDF cycles, no optimization\n\n    mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers\n    mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)\n\n    nand probe at91sam9260.flash\n\n    ##\n    # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit\n    ##\n    echo \"Setting up dataflash\"\n    mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),\n                               #            2(SPI0_SPCK), and 11(SPI0_NPCS1)\n    mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2\n    mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11\n    mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock\n\n    mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0\n    mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure\n    mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected\n\n    mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,\n                               #             250ns delay before SPCK, 250ns b/n tx\n\n    mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1\n    mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0\n}\n\nnand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800\nat91sam9 cle 0 22\nat91sam9 ale 0 21\nat91sam9 rdy_busy 0 0xfffff800 13\nat91sam9 ce 0 0xfffff800 14\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/olimex_stm32_h103.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Olimex STM32-H103 eval board\n# http://olimex.com/dev/stm32-h103.html\n\n# Work-area size (RAM size) = 20kB for STM32F103RB device\nset WORKAREASIZE 0x5000\n\nsource [find target/stm32f1x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/olimex_stm32_h107.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Olimex STM32-H107\n#\n# http://olimex.com/dev/stm32-h107.html\n#\n\n# Work-area size (RAM size) = 64kB for STM32F107VC device\nset WORKAREASIZE 0x10000\n\nsource [find target/stm32f1x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/olimex_stm32_h405.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Olimex STM32-H405 eval board\n# https://www.olimex.com/Products/ARM/ST/STM32-H405/\n\n# Work-area size (RAM size) = 128kB for STM32F405RG device\nset WORKAREASIZE 0x20000\n\nsource [find target/stm32f4x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/olimex_stm32_p107.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Olimex STM32-P107\n#\n# http://olimex.com/dev/stm32-p107.html\n#\n\n# Work-area size (RAM size) = 64kB for STM32F107VC device\nset WORKAREASIZE 0x10000\n\nsource [find target/stm32f1x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/omap2420_h4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# OMAP2420 SDP board (\"H4\")\n\nsource [find target/omap2420.cfg]\n\n# NOTE: this assumes you're *NOT* using a TI-14 connector.\nreset_config trst_and_srst separate\n\n# Board configs can vary a *LOT* ... parts, jumpers, etc.\n# This GP board boots from cs0 using NOR (2x32M), and also\n# has 64M NAND on cs6.\nflash bank h4.u10 cfi 0x04000000 0x02000000 2 2 $_TARGETNAME\nflash bank h4.u11 cfi 0x06000000 0x02000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/openrd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Marvell OpenRD\n\nsource [find interface/ftdi/openrd.cfg]\nsource [find target/feroceon.cfg]\n\nadapter speed 2000\n\n$_TARGETNAME configure \\\n\t-work-area-phys 0x10000000 \\\n\t-work-area-size 65536 \\\n\t-work-area-backup 0\n\narm7_9 dcc_downloads enable\n\n# this assumes the hardware default peripherals location before u-Boot moves it\nset _FLASHNAME $_CHIPNAME.flash\nnand device $_FLASHNAME orion 0 0xd8000000\n\nproc openrd_init { } {\n\n\t# We need to assert DBGRQ while holding nSRST down.\n\t# However DBGACK will be set only when nSRST is released.\n\t# Furthermore, the JTAG interface doesn't respond at all when\n\t# the CPU is in the WFI (wait for interrupts) state, so it is\n\t# possible that initial tap examination failed.  So let's\n\t# re-examine the target again here when nSRST is asserted which\n\t# should then succeed.\n\tadapter assert srst\n\tferoceon.cpu arp_examine\n\thalt 0\n\tadapter deassert srst\n\twait_halt\n\n\tarm mcr 15 0 0 1 0 0x00052078\n\n\tmww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register\n\tmww 0xD0001404 0x37543000 ;#  Dunit Control Low Register\n\tmww 0xD0001408 0x22125451 ;#  DDR SDRAM Timing (Low) Register\n\tmww 0xD000140C 0x00000A33 ;#  DDR SDRAM Timing (High) Register\n\tmww 0xD0001410 0x000000CC ;#  DDR SDRAM Address Control Register\n\tmww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register\n\tmww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register\n\tmww 0xD000141C 0x00000C52 ;#  DDR SDRAM Mode Register\n\tmww 0xD0001420 0x00000004 ;#  DDR SDRAM Extended Mode Register\n\tmww 0xD0001424 0x0000F17F ;#  Dunit Control High Register\n\tmww 0xD0001428 0x00085520 ;#  Dunit Control High Register\n\tmww 0xD000147c 0x00008552 ;#  Dunit Control High Register\n\tmww 0xD0001504 0x0FFFFFF1 ;#  CS0n Size Register\n\tmww 0xD0001508 0x10000000 ;#  CS1n Base Register\n\tmww 0xD000150C 0x0FFFFFF5 ;#  CS1n Size Register\n\tmww 0xD0001514 0x00000000 ;#  CS2n Size Register\n\tmww 0xD000151C 0x00000000 ;#  CS3n Size Register\n\tmww 0xD0001494 0x00120012 ;#  DDR2 SDRAM ODT Control (Low) Register\n\tmww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister\n\tmww 0xD000149C 0x0000E40F ;#  DDR2 Dunit ODT Control Register\n\tmww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register\n\tmww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\n\tmww 0xD0010000 0x01111111 ;#  MPP  0 to 7\n\tmww 0xD0010004 0x11113322 ;#  MPP  8 to 15\n\tmww 0xD0010008 0x00001111 ;#  MPP 16 to 23\n\n\tmww 0xD0010418 0x003E07CF ;#  NAND Read Parameters REgister\n\tmww 0xD001041C 0x000F0F0F ;#  NAND Write Parameters Register\n\tmww 0xD0010470 0x01C7D943 ;#  NAND Flash Control Register\n\n}\n\nproc openrd_reflash_uboot { } {\n\n\t# reflash the u-Boot binary and reboot into it\n\topenrd_init\n\tnand probe 0\n\tnand erase 0 0x0 0xa0000\n\tnand write 0 uboot.bin 0 oob_softecc_kw\n\tresume\n\n}\n\nproc openrd_load_uboot { } {\n\n\t# load u-Boot into RAM and execute it\n\topenrd_init\n\tload_image uboot.elf\n\tverify_image uboot.elf\n\tresume 0x00600000\n\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/or1k_generic.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# If you want to use the VJTAG TAP or the XILINX BSCAN,\n# you must set your FPGA TAP ID here\n\nset FPGATAPID 0x020b30dd\n\n# Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN)\nif { [info exists TAP_TYPE] == 0} {\n   set TAP_TYPE VJTAG\n}\n\n# Set your chip name\nset CHIPNAME or1200\n\nsource [find target/or1k.cfg]\n\n# Set the servers polling period to 1ms (needed to JSP Server)\npoll_period 1\n\n# Set the adapter speed\nadapter speed 3000\n\n# Enable the target description feature\ngdb_target_description enable\n\n# Add a new register in the cpu register list. This register will be\n# included in the generated target descriptor file.\n# format is addreg [name] [address] [feature] [reg_group]\naddreg rtest 0x1234 org.gnu.gdb.or1k.group0 system\n\n# Override default init_reset\nproc init_reset {mode} {\n\tsoft_reset_halt\n\tresume\n}\n\n# Target initialization\ninit\necho \"Halting processor\"\nhalt\n\nforeach name [target names] {\n\tset y [$name cget -endian]\n\tset z [$name cget -type]\n\tputs [format \"Chip is %s, Endian: %s, type: %s\" \\\n\t      $name $y $z]\n}\n\nset c_blue  \"\\033\\[01;34m\"\nset c_reset \"\\033\\[0m\"\n\nputs [format \"%sTarget ready...%s\" $c_blue $c_reset]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/osk5912.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# http://omap.spectrumdigital.com/osk5912/\n\nsource [find target/omap5912.cfg]\n\n# NOTE: this assumes you're using the ARM 20-pin (\"Multi-ICE\")\n# JTAG connector, and accordingly have J1 connecting pins 1 & 2.\n# The TI-14 pin needs \"trst_only\", and J1 connecting 2 & 3.\nreset_config trst_and_srst separate\n\n# NOTE:  boards with XOMAP parts wire nSRST to nPWRON_RESET.\n# That resets everything -- including JTAG and EmbeddedICE.\n# So they must use \"reset_config srst_pulls_trst\".\n\n# NOTE:  an expansion board could add a trace connector ... if\n# it does, change this appropriately.  And reset_config too,\n# assuming JTAG_DIS reroutes JTAG to that connector.\netm config $_TARGETNAME 8 demultiplexed full dummy\netm_dummy config $_TARGETNAME\n\n# standard boards populate two 16 MB chips, but manufacturing\n# options or an expansion board could change this config.\nflash bank osk.u1 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME\nflash bank osk.u2 cfi 0x01000000 0x01000000 2 2 $_TARGETNAME\n\nproc osk5912_init {} {\n\tomap5912_reset\n\n\t# detect flash\n\tflash probe 0\n\tflash probe 1\n}\n$_TARGETNAME configure -event reset-init { osk5912_init }\n\narm7_9 dcc_downloads enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/phone_se_j100i.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Sony Ericsson J100I Phone\n#\n# more information can be found on\n# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i\n#\nsource [find target/ti_calypso.cfg]\n\n# external flash\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x00000000 0x400000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/phytec_lpc3250.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/lpc3250.cfg]\n\nadapter srst delay 200\njtag_ntrst_delay 1\nadapter speed 200\nreset_config trst_and_srst separate\n\narm7_9 dcc_downloads enable\n\n$_TARGETNAME configure -event gdb-attach { reset init }\n\n$_TARGETNAME configure -event reset-start {\n             arm7_9 fast_memory_access disable\n             adapter speed 200\n}\n\n$_TARGETNAME configure -event reset-end {\n             adapter speed 6000\n             arm7_9 fast_memory_access enable\n}\n\n$_TARGETNAME configure -event reset-init { phytec_lpc3250_init }\n\n# Bare-bones initialization of core clocks and SDRAM\nproc phytec_lpc3250_init { } {\n        # Set clock dividers\n        #   ARMCLK = 266.5 MHz\n        #   HCLK   = 133.25 MHz\n        #   PERIPHCLK = 13.325 MHz\n        mww 0x400040BC 0\n        mww 0x40004050 0x140\n        mww 0x40004040 0x4D\n        mww 0x40004058 0x16250\n\n        # Init PLLs\n        mww 0x40004044 0x006\n        sleep 1 busy\n        mww 0x40004044 0x106\n        sleep 1 busy\n        mww 0x40004044 0x006\n        sleep 1 busy\n        mww 0x40004048 0x2\n\n        # Init SDRAM with 133 MHz timings\n        mww 0x40028134 0x00FFFFFF\n        mww 0x4002802C 0x00000008\n\n        mww 0x31080000 1\n        mww 0x31080008 0\n        mww 0x40004068 0x1C000\n        mww 0x31080028 0x11\n\n        mww 0x31080400 0\n        mww 0x31080440 0\n        mww 0x31080460 0\n        mww 0x31080480 0\n\n        # Delays\n        mww 0x31080030 1\n        mww 0x31080034 6\n        mww 0x31080038 10\n        mww 0x31080044 1\n        mww 0x31080048 9\n        mww 0x3108004C 12\n        mww 0x31080050 10\n        mww 0x31080054 1\n        mww 0x31080058 1\n        mww 0x3108005C 0\n\n        mww 0x31080100 0x5680\n        mww 0x31080104 0x302\n\n        # Init sequence\n        mww 0x31080020 0x193\n        sleep 1 busy\n        mww 0x31080024 1\n        mww 0x31080020 0x113\n        sleep 1 busy\n        mww 0x31080020 0x013\n        sleep 1 busy\n        mww 0x31080024 65\n        mww 0x31080020 0x093\n        mdw 0x80020000\n        mww 0x31080020 0x013\n\n        # SYS_CTRL remapping\n        mww 0x40004014 1\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/pic-p32mx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The Olimex PIC-P32MX has a PIC32MX\n\nset CPUTAPID 0x40916053\nsource [find target/pic32mx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/pico-debug.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# pico-debug is a virtual CMSIS-DAP debug adapter\n# it runs on the very same RP2040 target being debugged without additional hardware\n# https://github.com/majbthrd/pico-debug\n\nsource [find interface/cmsis-dap.cfg]\nadapter speed 4000\n\nset CHIPNAME rp2040\nsource [find target/rp2040-core0.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/pipistrello.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# http://pipistrello.saanlima.com/\n\nsource [find interface/ftdi/pipistrello.cfg]\nsource [find cpld/xilinx-xc6s.cfg]\nsource [find cpld/jtagspi.cfg]\n\n# example command to write bitstream, soft-cpu bios and runtime:\n# openocd -f board/pipistrello.cfg -c \"init;\\\n# jtagspi_init 0 bscan_spi_xc6slx45.bit;\\\n# jtagspi_program bitstream-pistrello.bin 0;\\\n# jtagspi_program bios.bin 0x170000;\\\n# jtagspi_program runtime.fbi 0x180000;\\\n# xc6s_program xc6s.tap;\\\n# exit\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/propox_mmnet1001.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n## Chip:\nset CHIPNAME at91sam9260\nset CPUTAPID 0x0792603f\nset ENDIAN little\nsource [find target/at91sam9260.cfg]\n\n$_TARGETNAME configure -event reset-init {at91sam_init}\n\n\nproc at91sam_init { } {\n\n\t# at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz\n\tjtag_rclk 4\n\n\t# Enable user reset and disable watchdog\n\tmww 0xfffffd08 0xa5000501         ;# RSTC_MR : enable user reset\n\tmww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog\n\n\t# Oscillator setup\n\tmww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator (18.432 MHz)\n\tsleep 20                          ;# wait 20 ms\n\tmww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator\n\tsleep 10                          ;# wait 10 ms\n\n\t# now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz\n\tjtag_rclk 2000\n\n\tmww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz\n\tsleep 20                          ;# wait 20 ms\n\tmww 0xfffffc2c 0x207c3f0c         ;# CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)\n\tsleep 10                          ;# wait 10 ms\n\tmww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler\n\tsleep 10                          ;# wait 10 ms\n\tmww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected\n\tsleep 10                          ;# wait 10 ms\n\n\t# now we are running at 198.656 MHz kHz => full speed jtag\n\tjtag_rclk 30000\n\n\tarm7_9 dcc_downloads enable       ;# Enable faster DCC downloads\n\n\t# Configure PIO Controller for SDRAM data-lines D16-D31\n\t# PC16-PC31 = Peripheral A: D16-D32\n\tmww 0xfffff844 0xffff0000\t;# Interrupt Disable\n\tmww 0xfffff854 0xffff0000\t;# Multi-Drive Disable\n\tmww 0xfffff860 0xffff0000\t;# Pull-Up Disable\n\tmww 0xfffff870 0xffff0000\t;# PIO_ASR : Select peripheral A function for D15..D31\n\tmww 0xfffff804 0xffff0000\t;# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)\n\tmww 0xfffffc10 0x00000010\t;# Enable PIO-C Clock in PMC (PID=4)\n\n\t# SD-Ram setup\n\tmww 0xffffef1c 0x2\t\t\t;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM\n\tmww 0xffffea08 0x85227259\t;# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))\n\tmww 0xffffea00 0x1\t\t\t;# SDRAMC_MR : issue a NOP command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x2\t\t\t;# SDRAMC_MR : issue an 'All Banks Precharge' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\t\t\t;# SDRAMC_MR : issue an 'Auto-Refresh' command (1st)\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\t\t\t;# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\t\t\t;# SDRAMC_MR : issue an 'Auto-Refresh' command (3th)\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\t\t\t;# SDRAMC_MR : issue an 'Auto-Refresh' command (4th)\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\t\t\t;# SDRAMC_MR : issue an 'Auto-Refresh' command (5th)\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\t\t\t;# SDRAMC_MR : issue an 'Auto-Refresh' command (6th)\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\t\t\t;# SDRAMC_MR : issue an 'Auto-Refresh' command (7th)\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\t\t\t;# SDRAMC_MR : issue an 'Auto-Refresh' command (8th)\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x3\t\t\t;# SDRAMC_MR : issue a 'Load Mode Register' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x0\t\t\t;# SDRAMC_MR : Normal Mode\n\tmww 0x20000000 0\n\tmww 0xFFFFEA04 0x30d\t\t;# SDRAM Refresh Time Register\n\t\t\t\t\t\t\t\t #  datasheet: 8k refresh cycles / 64 ms\n\t\t\t\t\t\t\t\t #  MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d\n\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/pxa255_sst.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# A PXA255 test board with SST 39LF400A flash\n#\n# At reset the memory map is as follows. Note that\n# the memory map changes later on as the application\n# starts...\n#\n# RAM at 0x4000000\n# Flash at 0x00000000\n#\nsource [find target/pxa255.cfg]\n\n# Target name is set by above\n$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0\n\n# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe\n\nproc pxa255_sst_init {} {\n\txscale cp15   15      0x00002001  ;#Enable CP0 and CP13 access\n\t#\n\t# setup GPIO\n\t#\n\tmww    0x40E00018  0x00008000  ;#CPSR0\n\tsleep   20\n\tmww    0x40E0001C  0x00000002  ;#GPSR1\n\tsleep   20\n\tmww    0x40E00020  0x00000008  ;#GPSR2\n\tsleep   20\n\tmww    0x40E0000C  0x00008000  ;#GPDR0\n\tsleep   20\n\tmww    0x40E00054  0x80000000  ;#GAFR0_L\n\tsleep   20\n\tmww    0x40E00058  0x00188010  ;#GAFR0_H\n\tsleep   20\n\tmww    0x40E0005C  0x60908018  ;#GAFR1_L\n\tsleep   20\n\tmww    0x40E0000C  0x0280E000  ;#GPDR0\n\tsleep   20\n\tmww    0x40E00010  0x821C88B2  ;#GPDR1\n\tsleep   20\n\tmww    0x40E00014  0x000F03DB  ;#GPDR2\n\tsleep   20\n\tmww    0x40E00000  0x000F03DB  ;#GPLR0\n\tsleep   20\n\n\n\tmww    0x40F00004  0x00000020  ;#PSSR\n\tsleep   20\n\n\t#\n\t# setup memory controller\n\t#\n\tmww    0x48000008  0x01111998  ;#MSC0\n\tsleep   20\n\tmww    0x48000010  0x00047ff0  ;#MSC2\n\tsleep   20\n\tmww    0x48000014  0x00000000  ;#MECR\n\tsleep   20\n\tmww    0x48000028  0x00010504  ;#MCMEM0\n\tsleep   20\n\tmww    0x4800002C  0x00010504  ;#MCMEM1\n\tsleep   20\n\tmww    0x48000030  0x00010504  ;#MCATT0\n\tsleep   20\n\tmww    0x48000034  0x00010504  ;#MCATT1\n\tsleep   20\n\tmww    0x48000038  0x00004715  ;#MCIO0\n\tsleep   20\n\tmww    0x4800003C  0x00004715  ;#MCIO1\n\tsleep   20\n\t#\n\tmww    0x48000004  0x03CA4018  ;#MDREF\n\tsleep   20\n\tmww    0x48000004  0x004B4018  ;#MDREF\n\tsleep   20\n\tmww    0x48000004  0x000B4018  ;#MDREF\n\tsleep   20\n\tmww    0x48000004  0x000BC018  ;#MDREF\n\tsleep   20\n\tmww    0x48000000  0x00001AC8  ;#MDCNFG\n\tsleep   20\n\n\tsleep   20\n\n\tmww    0x48000000  0x00001AC9  ;#MDCNFG\n\tsleep   20\n\tmww    0x48000040  0x00000000  ;#MDMRS\n\tsleep   20\n}\n\n$_TARGETNAME configure -event reset-init {pxa255_sst_init}\n\nreset_config trst_and_srst\n\nadapter srst delay 200\njtag_ntrst_delay 200\n\n#xscale debug_handler 0  0xFFFF0800      ;# debug handler base address\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/quark_d2000_refboard.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Intel Quark microcontroller D2000 Reference Board (web search for doc num 333582)\n\n# the board has an onboard FTDI FT232H chip\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6014\nftdi channel 0\n\nftdi layout_init 0x0000 0x030b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0100\n\nsource [find target/quark_d20xx.cfg]\n\nadapter speed 1000\n\nreset_config trst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/quark_x10xx_board.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# There are many Quark boards that can host the quark_x10xx SoC\n# Galileo is an example board\n\nsource [find target/quark_x10xx.cfg]\n\n#default frequency but this can be adjusted at runtime\nadapter speed 4000\n\nreset_config trst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/quicklogic_quickfeather.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# QuickLogic EOS S3 QuickFeather\n# https://www.quicklogic.com/products/eos-s3/quickfeather-development-kit/\n\nsource [find target/eos_s3.cfg]\n\nreset_config srst_only\n\ntransport select swd\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/radiona_ulx3s.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Radiona ULX3S\n# https://radiona.org/ulx3s/\n# Currently there are following board variants:\n# CS-ULX3S-01 - LFE5U 12F\n# CS-ULX3S-02 - LFE5U 45F\n# CS-ULX3S-03 - LFE5U 85F\n#\n# two JTAG interfaces:\n# - US1, micro USB port connected to FT231XQ\n#   This interface should be used with following config:\n#        interface/ft232r/radiona_ulx3s.cfg\n# - J4, 6 pin connector\n#\n# Both of this interfaces share the JTAG lines (TDI, TMS, TCK, TDO) between\n# Lattice ECP5 FPGA chip and ESP32 WiFi controller.\n# Note: TRST_N of the ESP32 is pulled up by default and can be pulled down over\n# J3 interface.\n# See schematics for more information:\n# https://github.com/emard/ulx3s/blob/master/doc/schematics_v308.pdf\n# https://github.com/emard/ulx3s/blob/master/doc/schematics_v314.pdf\n# https://github.com/emard/ulx3s/blob/master/doc/schematics_v315.pdf\n# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf\n\nsource [find interface/ft232r/radiona_ulx3s.cfg]\nsource [find fpga/lattice_ecp5.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/redbee.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/mc13224v.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/reflexces_achilles_i-dev_kit_arria10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Achilles Instant-Development Kit Arria 10 SoC SoM\n# https://www.reflexces.com/products-solutions/achilles-instant-development-kit-arria-10-soc-som\n#\n\nif { [info exists USE_EXTERNAL_DEBUGGER] } {\n\techo \"Using external debugger\"\n} else {\n\tsource [find interface/altera-usb-blaster2.cfg]\n\tusb_blaster device_desc \"Arria10 IDK\"\n}\n\nsource [find fpga/altera-10m50.cfg]\nsource [find target/altera_fpgasoc_arria10.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/renesas_dk-s7g2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Renesas Synergy DK-S7G2\n#\n\nsource [find interface/jlink.cfg]\ntransport select swd\n\n# XXX 19-pin SWD+TRACE connector also available\n\n# Synergy R7FS7G27H2A01CBD\nsource [find target/renesas_s7g2.cfg]\n\n# 32 MB QSPI flash (Micron N25Q256A13EF840E)\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/renesas_falcon.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Renesas R-Car V3U Falcon Board Config\n\n# The Falcon board comes with either an V3U SOC.\n\necho \"\\nFalcon:\"\nif { ![info exists SOC] } {\n\tset SOC V3U\n}\nsource [find target/renesas_rcar_gen3.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/renesas_gr_peach.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas RZ/A1H GR-Peach board\n\nreset_config srst_only\n\nsource [find target/renesas_r7s72100.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/renesas_porter.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas R-Car M2 Evaluation Board\n\nset SOC M2\nsource [find target/renesas_rcar_gen2.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/renesas_salvator-xs.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas R-Car Gen3 Salvator-X(S) Board Config\n\n# The Salvator-X(S) boards come with either an H3, M3W, or M3N SOC.\n\necho \"\\nSalvator-X(S):\"\nif { ![info exists SOC] } {\n\tset SOC H3\n}\nsource [find target/renesas_rcar_gen3.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/renesas_silk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas R-Car E2 Evaluation Board\n\nset SOC E2\nsource [find target/renesas_rcar_gen2.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/renesas_stout.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas R-Car H2 Evaluation Board\n\nset SOC H2\nsource [find target/renesas_rcar_gen2.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/rigado_bmd300_ek.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Rigado BMD-300 Evaluation Kit\n#\n# https://www.rigado.com/products/modules/bmd-300/\n#\n\nsource [find interface/jlink.cfg]\ntransport select swd\nadapter speed 1000\n\nsource [find target/nrf52.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/rpi3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is the Raspberry Pi 3 board with BCM2837 chip\n# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837/README.md\n#\n# Enable JTAG GPIO on Raspberry Pi boards\n# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md\n\nsource [find target/bcm2837.cfg]\ntransport select jtag\n\n# Raspberry Pi boards only expose Test Reset (TRST) pin, no System Reset (SRST)\nreset_config trst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/rpi4b.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is the Raspberry Pi 4 model B board with BCM2711 chip\n# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md\n#\n# Enable JTAG GPIO on Raspberry Pi boards\n# https://www.raspberrypi.org/documentation/configuration/config-txt/gpio.md\n\nsource [find target/bcm2711.cfg]\ntransport select jtag\n\n# Raspberry Pi boards only expose Test Reset (TRST) pin, no System Reset (SRST)\nreset_config trst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/rsc-w910.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Avalue RSC-W8910 sbc\n# http://www.avalue.com.tw/products/RSC-W910.cfm\n# 2MB NOR Flash\n# 64MB SDRAM\n# 128MB NAND Flash\n\n# Based on Nuvoton nuc910\nsource [find target/nuc910.cfg]\n\n#\n# reset only behaves correctly if we use srst_pulls_trst\n#\nreset_config trst_and_srst srst_pulls_trst\n\nadapter speed 1000\nadapter srst delay 100\njtag_ntrst_delay 100\n\n$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME\n\nset _NANDNAME $_CHIPNAME.nand\nnand device $_NANDNAME nuc910 $_TARGETNAME\n\n#\n# Target events\n#\n\n$_TARGETNAME configure -event reset-start {adapter speed 1000}\n\n$_TARGETNAME configure -event reset-init {\n\t# switch on PLL for 200MHz operation\n\t# running from 15MHz input clock\n\n\tmww 0xB0000200 0x00000030 ;# CLKEN\n\tmww 0xB0000204 0x00000f3c ;# CLKSEL\n\tmww 0xB0000208 0x05007000 ;# CLKDIV\n\tmww 0xB000020C 0x00004f24 ;# PLLCON0\n\tmww 0xB0000210 0x00002b63 ;# PLLCON1\n\tmww 0xB000000C 0x08817fa6 ;# MFSEL\n\tsleep 10\n\n\t# we are now running @ 200MHz\n\t# enable all openocd speed tweaks\n\n\tarm7_9 dcc_downloads enable\n\tarm7_9 fast_memory_access enable\n\tadapter speed 15000\n\n\t# map nor flash to 0x20000000\n\t# map sdram to 0x00000000\n\n\tmww 0xb0001000 0x000530c1 ;# EBICON\n\tmww 0xb0001004 0x40030084 ;# ROMCON\n\tmww 0xb0001008 0x000010ee ;# SDCONF0\n\tmww 0xb000100C 0x00000000 ;# SDCONF1\n\tmww 0xb0001010 0x0000015b ;# SDTIME0\n\tmww 0xb0001014 0x0000015b ;# SDTIME1\n\tmww 0xb0001018 0x00000000 ;# EXT0CON\n\tmww 0xb000101C 0x00000000 ;# EXT1CON\n\tmww 0xb0001020 0x00000000 ;# EXT2CON\n\tmww 0xb0001024 0x00000000 ;# EXT3CON\n\tmww 0xb000102c 0x00ff0048 ;# CKSKEW\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/sayma_amc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Sayma AMC is an FPGA board for the µTCA AMC format\n# The board is open hardware (CERN OHL) and the gateware and software\n# running on it are open source (ARTIQ, LGPLv3+).\n#\n# https://github.com/m-labs/sinara/wiki/Sayma\n#\n# It contains a Xilinx Kintex Ultrascale 040 FPGA (xcku040).\n# There is a SCANSTA112SM JTAG router on the board which is configured to\n# automatically add devices to the JTAG svcan chain when they are added.\n# Sayma AMC is usually combined with Sayma RTM (rear transition module)\n# which features an Artix 7 FPGA.\n\nadapter driver ftdi\nftdi device_desc \"Quad RS232-HS\"\nftdi vid_pid 0x0403 0x6011\nftdi channel 0\n# Use this to distinguish multiple boards by topology\n#adapter usb location 5:1\n# sampling on falling edge generally seems to work and accelerates things but\n# is not fully tested\n#ftdi tdo_sample_edge falling\n# EN_USB_JTAG on ADBUS7: out, high\n# USB_nTRST on ADBUS4: out, high, but R46 is DNP\nftdi layout_init 0x0098 0x008b\n#ftdi layout_signal EN_USB -data 0x0080\n#ftdi layout_signal nTRST -data 0x0010\nreset_config none\n\nadapter speed 5000\n\ntransport select jtag\n\n# Add the RTM Artix to the chain. Note that this changes the PLD numbering.\n# Unfortunately openocd TAPs can't be disabled after they have been added and\n# before `init`.\n#source [find cpld/xilinx-xc7.cfg]\n\nset CHIP XCKU040\nsource [find cpld/xilinx-xcu.cfg]\n\nset XILINX_USER1 0x02\nset XILINX_USER2 0x03\nset JTAGSPI_IR $XILINX_USER1\nsource [find cpld/jtagspi.cfg]\nflash bank xcu.spi1 jtagspi 0 0 0 0 xcu.proxy $XILINX_USER2\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/sheevaplug.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Marvell SheevaPlug\n\nsource [find interface/ftdi/sheevaplug.cfg]\nsource [find target/feroceon.cfg]\n\nadapter speed 2000\n\n$_TARGETNAME configure \\\n\t-work-area-phys 0x10000000 \\\n\t-work-area-size 65536 \\\n\t-work-area-backup 0\n\narm7_9 dcc_downloads enable\n\n# this assumes the hardware default peripherals location before u-Boot moves it\nset _FLASHNAME $_CHIPNAME.flash\nnand device $_FLASHNAME orion 0 0xd8000000\n\nproc sheevaplug_init { } {\n\n\t# We need to assert DBGRQ while holding nSRST down.\n\t# However DBGACK will be set only when nSRST is released.\n\t# Furthermore, the JTAG interface doesn't respond at all when\n\t# the CPU is in the WFI (wait for interrupts) state, so it is\n\t# possible that initial tap examination failed.  So let's\n\t# re-examine the target again here when nSRST is asserted which\n\t# should then succeed.\n\tadapter assert srst\n\tferoceon.cpu arp_examine\n\thalt 0\n\tadapter deassert srst\n\twait_halt\n\n\tarm mcr 15 0 0 1 0 0x00052078\n\n\tmww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register\n\tmww 0xD0001404 0x39543000 ;#  Dunit Control Low Register\n\tmww 0xD0001408 0x22125451 ;#  DDR SDRAM Timing (Low) Register\n\tmww 0xD000140C 0x00000833 ;#  DDR SDRAM Timing (High) Register\n\tmww 0xD0001410 0x000000CC ;#  DDR SDRAM Address Control Register\n\tmww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register\n\tmww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register\n\tmww 0xD000141C 0x00000C52 ;#  DDR SDRAM Mode Register\n\tmww 0xD0001420 0x00000042 ;#  DDR SDRAM Extended Mode Register\n\tmww 0xD0001424 0x0000F17F ;#  Dunit Control High Register\n\tmww 0xD0001428 0x00085520 ;#  Dunit Control High Register\n\tmww 0xD000147c 0x00008552 ;#  Dunit Control High Register\n\tmww 0xD0001504 0x0FFFFFF1 ;#  CS0n Size Register\n\tmww 0xD0001508 0x10000000 ;#  CS1n Base Register\n\tmww 0xD000150C 0x0FFFFFF5 ;#  CS1n Size Register\n\tmww 0xD0001514 0x00000000 ;#  CS2n Size Register\n\tmww 0xD000151C 0x00000000 ;#  CS3n Size Register\n\tmww 0xD0001494 0x003C0000 ;#  DDR2 SDRAM ODT Control (Low) Register\n\tmww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister\n\tmww 0xD000149C 0x0000F80F ;#  DDR2 Dunit ODT Control Register\n\tmww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register\n\tmww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\tmww 0xD0020204 0x00000000 ;#              \"\n\n\tmww 0xD0010000 0x01111111 ;#  MPP  0 to 7\n\tmww 0xD0010004 0x11113322 ;#  MPP  8 to 15\n\tmww 0xD0010008 0x00001111 ;#  MPP 16 to 23\n\n\tmww 0xD0010418 0x003E07CF ;#  NAND Read Parameters REgister\n\tmww 0xD001041C 0x000F0F0F ;#  NAND Write Parameters Register\n\tmww 0xD0010470 0x01C7D943 ;#  NAND Flash Control Register\n\n}\n\nproc sheevaplug_reflash_uboot { } {\n\n\t# reflash the u-Boot binary and reboot into it\n\tsheevaplug_init\n\tnand probe 0\n\tnand erase 0 0x0 0xa0000\n\tnand write 0 uboot.bin 0 oob_softecc_kw\n\tresume\n\n}\n\nproc sheevaplug_reflash_uboot_env { } {\n\n\t# reflash the u-Boot environment variables area\n\tsheevaplug_init\n\tnand probe 0\n\tnand erase 0 0xa0000 0x40000\n\tnand write 0 uboot-env.bin 0xa0000 oob_softecc_kw\n\tresume\n\n}\n\nproc sheevaplug_load_uboot { } {\n\n\t# load u-Boot into RAM and execute it\n\tsheevaplug_init\n\tload_image uboot.elf\n\tverify_image uboot.elf\n\tresume 0x00600000\n\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/sifive-e31arty.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Be sure you include the speed and interface before this file\n# Example:\n# -c \"adapter speed 5000\" -f \"interface/ftdi/olimex-arm-usb-tiny-h.cfg\" -f \"board/sifive-e31arty.cfg\"\n\nset _CHIPNAME riscv\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001\n\nset _TARGETNAME $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME\n$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1\n\nflash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000\ninit\nif {[ info exists pulse_srst]} {\n  ftdi set_signal nSRST 0\n  ftdi set_signal nSRST z\n}\nhalt\nflash protect 0 64 last off\necho \"Ready for Remote Connections\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/sifive-e51arty.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Be sure you include the speed and interface before this file\n# Example:\n# -c \"adapter speed 5000\" -f \"interface/ftdi/olimex-arm-usb-tiny-h.cfg\" -f \"board/sifive-e51arty.cfg\"\n\nset _CHIPNAME riscv\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001\n\nset _TARGETNAME $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME\n$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1\n\nflash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000\ninit\nif {[ info exists pulse_srst]} {\n  ftdi set_signal nSRST 0\n  ftdi set_signal nSRST z\n}\nhalt\nflash protect 0 64 last off\necho \"Ready for Remote Connections\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/sifive-hifive1-revb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nadapter speed 4000\n\nadapter driver jlink\ntransport select jtag\n\nset _CHIPNAME riscv\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME\n$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 0\n\nflash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME.0\n\ninit\n\njlink jtag 3\n\nhalt\nflash protect 0 1 last off\necho \"Ready for Remote Connections\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/sifive-hifive1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nadapter speed     10000\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0008 0x001b\nftdi layout_signal nSRST -oe 0x0020 -data 0x0020\n\n#Reset Stretcher logic on FE310 is ~1 second long\n#This doesn't apply if you use\n# ftdi set_signal, but still good to document\n#adapter srst delay 1500\n\nset _CHIPNAME riscv\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME riscv -chain-position $_TARGETNAME\n$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1\n\nflash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME\ninit\n#reset -- This type of reset is not implemented yet\nif {[ info exists pulse_srst]} {\n  ftdi set_signal nSRST 0\n  ftdi set_signal nSRST z\n  #Wait for the reset stretcher\n  #It will work without this, but\n  #will incur lots of delays for later commands.\n  sleep 1500\n}\nhalt\nflash protect 0 64 last off\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/smdk6410.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Target configuration for the Samsung s3c6410 system on chip\n# Tested on a SMDK6410\n# Processor       : ARM1176\n# Info:   JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)\n\nsource [find target/samsung_s3c6410.cfg]\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/snps_em_sk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2014-2016,2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\n#\n# Synopsys DesignWare ARC EM Starter Kit v2.x\n#\n\n# Configure JTAG cable\n# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.\nsource [find interface/ftdi/digilent-hs1.cfg]\n\n# 5MHz seems to work good with all cores that might happen in 2.x\nadapter speed 5000\n\n# ARCs support only JTAG.\ntransport select jtag\n\n# Configure FPGA. This script supports both LX45 and LX150.\nsource [find target/snps_em_sk_fpga.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/snps_em_sk_v1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2014-2016,2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\n#\n# Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1\n#\n\n# Configure JTAG cable\n# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.\nsource [find interface/ftdi/digilent-hs1.cfg]\nadapter speed 10000\n\n# ARCs support only JTAG.\ntransport select jtag\n\n# Configure FPGA. This script supports both LX45 and LX150.\nsource [find target/snps_em_sk_fpga.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/snps_em_sk_v2.1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2014-2016,2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\n#\n# Synopsys DesignWare ARC EM Starter Kit v2.1\n#\n\n# Configure JTAG cable\n# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.\nsource [find interface/ftdi/digilent-hs1.cfg]\n\n# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency\n# 20MHz. 7.5 MHz seems to work fine.\nadapter speed 7500\n\n# ARCs support only JTAG.\ntransport select jtag\n\n# Configure FPGA. This script supports both LX45 and LX150.\nsource [find target/snps_em_sk_fpga.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/snps_em_sk_v2.2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2016,2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\n#\n# Synopsys DesignWare ARC EM Starter Kit v2.2\n#\n\n# Configure JTAG cable\n# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.\nsource [find interface/ftdi/digilent-hs1.cfg]\n\n# EM11D reportedly requires 5 MHz. Other cores and board can work faster.\nadapter speed 5000\n\n# ARCs support only JTAG.\ntransport select jtag\n\n# Configure FPGA. This script supports both LX45 and LX150.\nsource [find target/snps_em_sk_fpga.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/snps_hsdk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2019, 2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\n#\n# Synopsys DesignWare ARC HSDK Software Development Platform (HS38 cores)\n#\n\nsource [find interface/ftdi/snps_sdp.cfg]\nadapter speed 10000\n\n# ARCs supports only JTAG.\ntransport select jtag\n\n# Configure SoC\nsource [find target/snps_hsdk.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/snps_hsdk_4xd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Copyright (C) 2023 Synopsys, Inc.\n# Artemiy Volkov <artemiy@synopsys.com>\n\n# Adapted from tcl/board/snps_hsdk.cfg.\n\n#\n# Synopsys DesignWare ARC HSDK Software Development Platform (HS47D cores)\n#\n\nsource [find interface/ftdi/snps_sdp.cfg]\nadapter speed 10000\n\n# ARCs supports only JTAG.\ntransport select jtag\n\n# Configure SoC\nsource [find target/snps_hsdk_4xd.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Spansion SK-FM4-176L-S6E2CC\n#\n\n#\n# FM3 MB9AF312K\n#\nsource [find interface/cmsis-dap.cfg]\n\n# There's also an unpopulated 10-pin 0.05\" pinout.\n\n#\n# FM4 S6E2CCAJ0A w/ 192 KB SRAM0\n#\nset CHIPNAME s6e2cc\nset CHIPSERIES S6E2CCAJ0A\nset WORKAREASIZE 0x30000\nsource [find target/fm4_s6e2cc.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/spansion_sk-fm4-u120-9b560.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Spansion SK-FM4-U120-9B560\n#\n\n#\n# FM3 MB9AF312K\n#\n# source [find interface/cmsis-dap.cfg]\n\n#\n# FM4 MB9BF568R w/ 64 KB SRAM0\n#\nset CHIPNAME mb9bf568\nset CHIPSERIES MB9BF568R\nset WORKAREASIZE 0x10000\nsource [find target/fm4_mb9bf.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/spear300evb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Configuration for the ST SPEAr300 Evaluation board\n# EVALSPEAr300 Rev. 1.0\n# http://www.st.com/spear\n#\n# Date:      2010-11-27\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\n# The standard board has JTAG SRST not connected.\n# This script targets such boards using quirky code to bypass the issue.\n\n\nsource [find mem_helper.tcl]\nsource [find target/spear3xx.cfg]\nsource [find chip/st/spear/spear3xx_ddr.tcl]\nsource [find chip/st/spear/spear3xx.tcl]\n\narm7_9 dcc_downloads enable\narm7_9 fast_memory_access enable\n\n\n# Serial NOR on SMI CS0. 8Mbyte.\nset _FLASHNAME1 $_CHIPNAME.snor\nflash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME\n\nif { [info exists BOARD_HAS_SRST] } {\n\t# Modified board has SRST on JTAG connector\n\treset_config trst_and_srst separate srst_gates_jtag \\\n\t\ttrst_push_pull srst_open_drain\n} else {\n\t# Standard board has no SRST on JTAG connector\n\treset_config trst_only separate srst_gates_jtag trst_push_pull\n\tsource [find chip/st/spear/quirk_no_srst.tcl]\n}\n\n$_TARGETNAME configure -event reset-init { spear300evb_init }\n\nproc spear300evb_init {} {\n\treg pc 0xffff0020;\t# loop forever\n\n\tsp3xx_clock_default\n\tsp3xx_common_init\n\tsp3xx_ddr_init \"mt47h64m16_3_333_cl5_async\"\n\tsp300_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/spear300evb_mod.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Configuration for the ST SPEAr300 Evaluation board\n# EVALSPEAr300 Rev. 1.0, modified to enable SRST on JTAG connector\n# http://www.st.com/spear\n#\n# List of board modifications to enable SRST, as reported in\n# ST Application Note (FIXME: add reference).\n# - Modifications on the top layer:\n#    1. replace reset chip U4 with a STM6315SDW13F;\n# - Modifications on the bottom layer:\n#    2. add 0 ohm resistor R10. It is located close to JTAG connector.\n#    3. add a 10K ohm pull-up resistor on the reset wire named as\n#       POWERGOOD in the schematic.\n#\n# The easier way to do modification 3, is to use a resistor in package\n# 0603 and solder it between R10 and R54:\n# - one pad soldered with the pad of R54 connected to 3.3V (this\n#   is the pad of R54 far from JTAG connector J4)\n# - the other pad soldered with the nearest pad of R10.\n#\n# Date:      2011-11-18\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\n\n# Modified boards has SRST on JTAG connector\nset BOARD_HAS_SRST 1\nsource [find board/spear300evb.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/spear310evb20.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Configuration for the ST SPEAr310 Evaluation board\n# EVALSPEAr310 Rev. 2.0\n# http://www.st.com/spear\n#\n# Date:      2010-08-17\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\n# The standard board has JTAG SRST not connected.\n# This script targets such boards using quirky code to bypass the issue.\n#\n# Check ST Application Note AN3321 on how to fix SRST on\n# the board, then use the script board/spear310evb20_mod.cfg\n\n\nsource [find mem_helper.tcl]\nsource [find target/spear3xx.cfg]\nsource [find chip/st/spear/spear3xx_ddr.tcl]\nsource [find chip/st/spear/spear3xx.tcl]\n\narm7_9 dcc_downloads enable\narm7_9 fast_memory_access enable\n\n# CFI parallel NOR on EMI CS0. 2x 16bit 8M devices = 16Mbyte.\nset _FLASHNAME0 $_CHIPNAME.pnor\nflash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME\n\n# Serial NOR on SMI CS0. 8Mbyte.\nset _FLASHNAME1 $_CHIPNAME.snor\nflash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME\n\nif { [info exists BOARD_HAS_SRST] } {\n\t# Modified board has SRST on JTAG connector\n\treset_config trst_and_srst separate srst_gates_jtag \\\n\t\ttrst_push_pull srst_open_drain\n} else {\n\t# Standard board has no SRST on JTAG connector\n\treset_config trst_only separate srst_gates_jtag trst_push_pull\n\tsource [find chip/st/spear/quirk_no_srst.tcl]\n}\n\n$_TARGETNAME configure -event reset-init { spear310evb20_init }\n\nproc spear310evb20_init {} {\n\treg pc 0xffff0020\t;# loop forever\n\n\tsp3xx_clock_default\n\tsp3xx_common_init\n\tsp3xx_ddr_init \"mt47h64m16_3_333_cl5_async\"\n\tsp310_init\n\tsp310_emi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/spear310evb20_mod.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Configuration for the ST SPEAr310 Evaluation board\n# EVALSPEAr310 Rev. 2.0, modified to enable SRST on JTAG connector\n# http://www.st.com/spear\n#\n# List of board modifications to enable SRST, as reported in\n# ST Application Note AN3321.\n# - Modifications on the top layer:\n#    1. remove R137 and C57, located near the SMII PHY U18;\n#    2. remove R172 and C75, located near the SMII PHY U19;\n#    3. remove R207 and C90, located near the SMII PHY U20;\n#    4. remove C236, located near the SMII PHY U21;\n#    5. remove U12, located near the JTAG connector;\n#    6. solder together pins 7, 8 and 9 of U12;\n#    7. solder together pins 11, 12, 13, 14, 15, 16, 17 and 18 of U12.\n# - Modifications on the bottom layer:\n#    8. replace reset chip U11 with a STM6315SDW13F;\n#    9. add 0 ohm resistor R329. It is located close to JTAG connector.\n#\n# Date:      2009-10-31\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\n\n# Modified boards has SRST on JTAG connector\nset BOARD_HAS_SRST 1\nsource [find board/spear310evb20.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/spear320cpu.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Configuration for the ST SPEAr320 CPU board\n# EVAL_SPEAr320CPU Rev. 2.0\n# http://www.st.com/spear\n#\n# Date:      2011-11-18\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\n# The standard board has JTAG SRST not connected.\n# This script targets such boards using quirky code to bypass the issue.\n\n\nsource [find mem_helper.tcl]\nsource [find target/spear3xx.cfg]\nsource [find chip/st/spear/spear3xx_ddr.tcl]\nsource [find chip/st/spear/spear3xx.tcl]\n\narm7_9 dcc_downloads enable\narm7_9 fast_memory_access enable\n\n\n# Serial NOR on SMI CS0. 8Mbyte.\nset _FLASHNAME1 $_CHIPNAME.snor\nflash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME\n\nif { [info exists BOARD_HAS_SRST] } {\n\t# Modified board has SRST on JTAG connector\n\treset_config trst_and_srst separate srst_gates_jtag \\\n\t\ttrst_push_pull srst_open_drain\n} else {\n\t# Standard board has no SRST on JTAG connector\n\treset_config trst_only separate srst_gates_jtag trst_push_pull\n\tsource [find chip/st/spear/quirk_no_srst.tcl]\n}\n\n$_TARGETNAME configure -event reset-init { spear320cpu_init }\n\nif { [info exists DDR_CHIPS] } {\n        set _DDR_CHIPS $DDR_CHIPS\n} else {\n        set _DDR_CHIPS 1\n}\n\nproc spear320cpu_init {} {\n\tglobal _DDR_CHIPS\n\treg pc 0xffff0020;\t# loop forever\n\n\tsp3xx_clock_default\n\tsp3xx_common_init\n\tsp3xx_ddr_init \"mt47h64m16_3_333_cl5_async\" $_DDR_CHIPS\n\tsp320_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/spear320cpu_mod.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Configuration for the ST SPEAr320 Evaluation board\n# EVAL_SPEAr320CPU Rev. 2.0, modified to enable SRST on JTAG connector\n# http://www.st.com/spear\n#\n# List of board modifications to enable SRST, as reported in\n# ST Application Note (FIXME: add reference).\n# - Modifications on the bottom layer:\n#    1. replace reset chip U7 with a STM6315SDW13F;\n#    2. add 0 ohm resistor R45. It is located close to JTAG connector.\n#    3. add a 10K ohm pull-up resistor on the reset wire named as\n#       POWERGOOD in the schematic.\n#\n# The easier way to do modification 3, is to use a resistor in package\n# 0603 or 0402 and solder it between R15 and R45:\n# - one pad soldered with the pad of R15 connected to 3.3V (this\n#   is the pad of R15 closer to R45)\n# - the other pad soldered with the nearest pad of R45.\n#\n# Date:      2011-11-18\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\n\n# Modified boards has SRST on JTAG connector\nset BOARD_HAS_SRST 1\nsource [find board/spear320cpu.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_b-l475e-iot01a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an B-L475E-IOT01A Discovery kit for IoT node with a single STM32L475VGT6 chip.\n# http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 96KB\nset WORKAREASIZE 0x18000\n\n# enable stmqspi\nset QUADSPI 1\n\nsource [find target/stm32l4x.cfg]\n\n# QUADSPI initialization\nproc qspi_init { } {\n\tglobal a\n\tmmw 0x4002104C 0x000001FF 0\t\t\t\t;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)\n\tmmw 0x40021050 0x00000100 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0\n\n\t# PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V\n\n\t# Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V\n\tmmw 0x48001000 0xAAA00000 0x55500000\t;# MODER\n\tmmw 0x48001008 0xFFF00000 0x00000000\t;# OSPEEDR\n\tmmw 0x48001024 0xAAAAAA00 0x55555500\t;# AFRH\n\n\tmww 0xA0001030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x01500008\t\t\t\t;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1\n\tmww 0xA0001004 0x00160100\t\t\t\t;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0\n\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# memory-mapped read mode with 3-byte addresses\n\tmww 0xA0001014 0x0D002503\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmmw 0x40022000 0x00000004 0x00000003\t;# 4 WS for 72 MHz HCLK\n\tsleep 1\n\tmmw 0x40021000 0x00000100 0x00000000\t;# HSI on\n\tmww 0x4002100C 0x01002432\t\t\t\t;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI\n\tmww 0x40021008 0x00008001\t\t\t\t;# always HSI, APB1: /1, APB2: /1\n\tmmw 0x40021000 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40021008 0x00000003 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\tqspi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_8l152r8.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is a ST NUCLEO 8L152R8 board with a single STM8L152R8T6 chip.\n# http://www.st.com/en/evaluation-tools/nucleo-8l152r8.html\n\nsource [find interface/stlink-dap.cfg]\n\ntransport select swim\n\nsource [find target/stm8l15xx8.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_8s208rb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is a ST NUCLEO 8S208RB board with a single STM8S208RBT6 chip.\n# https://www.st.com/en/evaluation-tools/nucleo-8s208rb.html\n\nsource [find interface/stlink-dap.cfg]\n\ntransport select swim\n\n# 128 KiB flash and 2 KiB EEPROM\nset FLASHEND 0x27fff\nset EEPROMEND 0x47ff\n\nsource [find target/stm8s.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_f0.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is for all ST NUCLEO with any STM32F0. Known boards at the moment:\n# STM32F030R8\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997\n# NUCLEO-F072RB\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997\n# STM32F091RC\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260944\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32f0x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_f103rb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an ST NUCLEO F103RB board with a single STM32F103RBT6 chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259875\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32f1x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_f3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an ST NUCLEO F334R8 board with a single STM32F334R8T6 chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260004\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32f3x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_f4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is for all ST NUCLEO with any STM32F4. Known boards at the moment:\n# STM32F401RET6\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260000\n# STM32F411RET6\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260320\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32f4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_f7.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STMicroelectronics STM32F7 Nucleo development board\n# Known boards: NUCLEO-F746ZG and NUCLEO-F767ZI\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32f7x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_g0.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is for all ST NUCLEO with any STM32G0. Known boards at the moment:\n# NUCLEO-G031K8\n# https://www.st.com/en/evaluation-tools/nucleo-g031k8.html\n# NUCLEO-G070RB\n# https://www.st.com/en/evaluation-tools/nucleo-g070rb.html\n# NUCLEO-G071RB\n# https://www.st.com/en/evaluation-tools/nucleo-g071rb.html\n# NUCLEO-G0B1RE\n# https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32g0x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_g4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is for all ST NUCLEO with any STM32G4. Known boards at the moment:\n# NUCLEO-G431KB\n# https://www.st.com/en/evaluation-tools/nucleo-g431kb.html\n# NUCLEO-G431RB\n# https://www.st.com/en/evaluation-tools/nucleo-g431rb.html\n# NUCLEO-G474RE\n# https://www.st.com/en/evaluation-tools/nucleo-g474re.html\n# NUCLEO-G491RE\n# https://www.st.com/en/evaluation-tools/nucleo-g491re.html\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32g4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_h743zi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip.\n# http://www.st.com/en/evaluation-tools/nucleo-h743zi.html\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32h7x_dual_bank.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_h745zi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an ST NUCLEO-H745ZI-Q board with single STM32H745ZITx chip.\n\nsource [find interface/stlink-dap.cfg]\ntransport select dapdirect_swd\n\n# STM32H745xx devices are dual core (Cortex-M7 and Cortex-M4)\nset DUAL_CORE 1\n\n# enable CTI for cross halting both cores\nset USE_CTI 1\n\nsource [find target/stm32h7x_dual_bank.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_l073rz.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an ST NUCLEO-L073RZ board with single STM32L073RZ chip.\n# http://www.st.com/en/evaluation-tools/nucleo-l073rz.html\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset WORKAREASIZE 0x2000\n\nsource [find target/stm32l0_dual_bank.cfg]\n\n# There is only system reset line and JTAG/SWD command can be issued when SRST\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_l1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an ST NUCLEO L152RE board with a single STM32L152RET6 chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32l1x_dual_bank.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_l4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Should work with all STM32L4 Nucleo Dev Boards.\n# http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32l4x.cfg]\n\n# use hardware reset\nreset_config srst_only srst_nogate\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_l5.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is for STM32L5 Nucleo Dev Boards.\n# http://www.st.com/en/evaluation-tools/stm32-mcu-nucleo.html\n\nsource [find interface/stlink-dap.cfg]\n\ntransport select dapdirect_swd\n\nsource [find target/stm32l5x.cfg]\n\n# use hardware reset\nreset_config srst_only srst_nogate\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/st_nucleo_wb55.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Configuration for STM32WB55 Nucleo board (STM32WB55RGV6)\n#\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32wbx.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/steval-idb007v1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an evaluation board with a single BlueNRG-1 chip.\n# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb008v1.html\nset CHIPNAME bluenrg-1\nsource [find target/bluenrg-x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/steval-idb008v1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an evaluation board with a single BlueNRG-2 chip.\n# http://www.st.com/content/st_com/en/products/evaluation-tools/solution-evaluation-tools/communication-and-connectivity-solution-eval-boards/steval-idb007v1.html\nset CHIPNAME bluenrg-2\nsource [find target/bluenrg-x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/steval-idb011v1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an evaluation board with a single BlueNRG-LP chip.\nset CHIPNAME bluenrg-lp\nsource [find target/bluenrg-x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/steval-idb012v1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an evaluation board with a single BlueNRG-LPS chip.\nset CHIPNAME bluenrg-lps\nsource [find interface/cmsis-dap.cfg]\nsource [find target/bluenrg-x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/steval_pcc010.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram\n# coming with the STEVAL-PCC010 board\n# http://www.st.com/internet/evalboard/product/251530.jsp\n# or any other board with only a STM32F2x in the JTAG chain\n\n# increase working area to 32KB for faster flash programming\nset WORKAREASIZE 0x8000\n\nsource [find target/stm32f2x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm320518_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6\n# (64KB) chip.\n# http://www.st.com/internet/evalboard/product/252994.jsp\n#\n\n# increase working area to 8KB\nset WORKAREASIZE 0x2000\n\n# chip name\nset CHIPNAME STM32F051R8T6\n\nsource [find target/stm32f0x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm320518_eval_stlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6\n# (64KB) chip.\n# http://www.st.com/internet/evalboard/product/252994.jsp\n#\n# This is for using the onboard STLINK/V2\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 8KB\nset WORKAREASIZE 0x2000\n\n# chip name\nset CHIPNAME STM32F051R8T6\n\nsource [find target/stm32f0x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32100b_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32 eval board with a single STM32F100VBT6 chip.\n# http://www.st.com/internet/evalboard/product/247099.jsp\n\n# The chip has only 8KB sram\nset WORKAREASIZE 0x2000\n\nsource [find target/stm32f1x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm3210b_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32 eval board with a single STM32F10x (128KB) chip.\n# http://www.st.com/internet/evalboard/product/176090.jsp\n\n# increase working area to 32KB for faster flash programming\nset WORKAREASIZE 0x8000\n\nsource [find target/stm32f1x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm3210c_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32 eval board with a single STM32F107VCT chip.\n# http://www.st.com/internet/evalboard/product/217965.jsp\n\n# increase working area to 32KB for faster flash programming\nset WORKAREASIZE 0x8000\n\nsource [find target/stm32f1x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm3210e_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32 eval board with a single STM32F103ZET6 chip.\n# http://www.st.com/internet/evalboard/product/204176.jsp\n\n# increase working area to 32KB for faster flash programming\nset WORKAREASIZE 0x8000\n\nsource [find target/stm32f1x.cfg]\n\n#\n# configure FSMC Bank 1 (NOR/PSRAM Bank 2) NOR flash\n# M29W128GL70ZA6E\n#\n\nset _FLASHNAME $_CHIPNAME.norflash\nflash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME\n\nproc stm32_enable_fsmc {} {\n\n\techo \"Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)\"\n\n\t# enable gpio (defg) clocks for fsmc\n\t# RCC_APB2ENR\n\tmww 0x40021018 0x000001E0\n\n\t# enable fsmc clock\n\t# RCC_AHBENR\n\tmww 0x40021014 0x00000114\n\n\t# configure gpio to alternate function\n\t# GPIOD_CRL\n\tmww 0x40011400 0x44BB44BB\n\t# GPIOD_CRH\n\tmww 0x40011404 0xBBBBBBBB\n\n\t# GPIOE_CRL\n\tmww 0x40011800 0xBBBBB444\n\t# GPIOE_CRH\n\tmww 0x40011804 0xBBBBBBBB\n\n\t# GPIOF_CRL\n\tmww 0x40011C00 0x44BBBBBB\n\t# GPIOF_CRH\n\tmww 0x40011C04 0xBBBB4444\n\n\t# GPIOG_CRL\n\tmww 0x40012000 0x44BBBBBB\n\t# GPIOG_CRH\n\tmww 0x40012004 0x444444B4\n\n\t# setup fsmc timings\n\t# FSMC_BCR1\n\tmww 0xA0000008 0x00001058\n\n\t# FSMC_BTR1\n\tmww 0xA000000C 0x10000502\n\n\t# FSMC_BCR1 - enable fsmc\n\tmww 0xA0000008 0x00001059\n}\n\n$_TARGETNAME configure -event reset-init {\n\tstm32_enable_fsmc\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm3220g_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6\n# (128KB) chip.\n# http://www.st.com/internet/evalboard/product/250374.jsp\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# chip name\nset CHIPNAME STM32F207IGH6\n\nsource [find target/stm32f2x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm3220g_eval_stlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6\n# (128KB) chip.\n# http://www.st.com/internet/evalboard/product/250374.jsp\n#\n# This is for using the onboard STLINK/V2\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# chip name\nset CHIPNAME STM32F207IGH6\n\nsource [find target/stm32f2x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm3241g_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6\n# (1024KB) chip.\n# http://www.st.com/internet/evalboard/product/252216.jsp\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# chip name\nset CHIPNAME STM32F417IGH6\n\nsource [find target/stm32f4x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm3241g_eval_stlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6\n# (1024KB) chip.\n# http://www.st.com/internet/evalboard/product/252216.jsp\n#\n# This is for using the onboard STLINK/V2\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# chip name\nset CHIPNAME STM32F417IGH6\n\nsource [find target/stm32f4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32429i_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6\n# (2048KB) chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# chip name\nset CHIPNAME STM32F429NIH6\n\nsource [find target/stm32f4x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32429i_eval_stlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6\n# (2048KB) chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093\n#\n# This is for using the onboard STLINK/V2\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# chip name\nset CHIPNAME STM32F429NIH6\n\nsource [find target/stm32f4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32439i_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6\n# (2048KB) chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# chip name\nset CHIPNAME STM32F439NIH6\n\nsource [find target/stm32f4x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32439i_eval_stlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6\n# (2048KB) chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094\n#\n# This is for using the onboard STLINK/V2\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# chip name\nset CHIPNAME STM32F439NIH6\n\nsource [find target/stm32f4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm327x6g_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM327[4|5]6G-EVAL: This is for the STM32F7 eval boards.\n# STM32746G-EVAL\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261639\n# STM32756G-EVAL\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261640\n\n# increase working area to 256KB\nset WORKAREASIZE 0x40000\n\nsource [find target/stm32f7x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f0discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F0 discovery board with a single STM32F051R8T6 chip.\n# http://www.st.com/internet/evalboard/product/253215.jsp\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset WORKAREASIZE 0x2000\nsource [find target/stm32f0x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f103c8_blue_pill.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM32F103C8 \"Blue Pill\"\n\n# NOTE:\n# There is a fair bit of confusion about whether the \"Blue Pill\" has 128kB or 64kB flash size.\n# The most likely cause is that there exist a -C8 and a -CB variant of the STM32F103, where\n# the C8 has 64kB, the CB has 128kB as per specification. \"Blue Pill\" boards are manufactured\n# by a lot of different vendors, some may actually use the CB variant but from a cursory look\n# it very hard to tell them apart (\"C8\" and \"CB\" look very similar). Nevertheless, people have\n# tried using the full 128kB of flash on the C8 and found it to be working. Hence this board file\n# overrides the internal size detection. Be aware though that you may be using you particular\n# board outside of its specification. If in doubt, comment the following line.\nset FLASH_SIZE 0x20000\n\nsource [find target/stm32f1x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f334discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F334 discovery board with a single STM32F334C8T6 chip.\n# As it is one of the few boards with stlink V.2-1, we source the corresponding\n# nucleo file.\n# http://www.st.com/web/en/catalog/tools/FM116/SC959/SS1532/LN1848/PF260318\n\nsource [find board/st_nucleo_f3.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f3discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F3 discovery board with a single STM32F303VCT6 chip.\n# http://www.st.com/internet/evalboard/product/254044.jsp\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32f3x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f412g-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F412G discovery board with a single STM32F412ZGT6 chip.\n# http://www.st.com/en/evaluation-tools/32f412gdiscovery.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# enable stmqspi\nset QUADSPI 1\n\nsource [find target/stm32f4x.cfg]\n\n# QUADSPI initialization\nproc qspi_init { } {\n\tglobal a\n\tmmw 0x40023830 0x000000FF 0\t\t\t\t;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)\n\tmmw 0x40023838 0x00000002 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PB02: CLK, PG06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0\n\n\t# PB02:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V, PG06:AF10:V\n\n\t# Port B: PB02:AF09:V\n\tmmw 0x40020400 0x00000020 0x00000010\t;# MODER\n\tmmw 0x40020408 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x40020420 0x00000900 0x00000600\t;# AFRL\n\n\t# Port F: PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V\n\tmmw 0x40021400 0x000AA000 0x00055000\t;# MODER\n\tmmw 0x40021408 0x000FF000 0x00000000\t;# OSPEEDR\n\tmmw 0x40021420 0x99000000 0x66000000\t;# AFRL\n\tmmw 0x40021424 0x000000AA 0x00000055\t;# AFRH\n\n\t# Port G: PG06:AF10:V\n\tmmw 0x40021800 0x00002000 0x00001000\t;# MODER\n\tmmw 0x40021808 0x00003000 0x00000000\t;# OSPEEDR\n\tmmw 0x40021820 0x0A000000 0x05000000\t;# AFRL\n\n\tmww 0xA0001030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x03500008\t\t\t\t;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1\n\tmww 0xA0001004 0x00170100\t\t\t\t;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0\n\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# 1-line spi mode\n\tmww 0xA0001014 0x000003F5\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO\n\tsleep 1\n\n\t# memory-mapped read mode with 3-byte addresses\n\tmww 0xA0001014 0x0D002503\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmww 0x40023C00 0x00000003\t\t\t\t;# 3 WS for 96 MHz HCLK\n\tsleep 1\n\tmww 0x40023804 0x24001808\t\t\t\t;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2\n\tmww 0x40023808 0x00001000\t\t\t\t;# APB1: /2, APB2: /1\n\tmmw 0x40023800 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40023808 0x00000002 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\tqspi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f413h-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F413H discovery board with a single STM32F413ZHT6 chip.\n# http://www.st.com/en/evaluation-tools/32f413hdiscovery.html\n\n#\n# Untested!!!\n#\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# enable stmqspi\nset QUADSPI 1\n\nsource [find target/stm32f4x.cfg]\n\n# QUADSPI initialization\nproc qspi_init { } {\n\tglobal a\n\tmmw 0x40023830 0x000000FF 0\t\t\t\t;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)\n\tmmw 0x40023838 0x00000002 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PG06: BK1_NCS, PB02: CLK, PD13: BK1_IO3, PE02: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0\n\n\t# PB02:AF09:V, PD13:AF09:V, PE02:AF09:V, PF09:AF10:V, PF08:AF10:V, PG06:AF10:V\n\n\t# Port B: PB02:AF09:V\n\tmmw 0x40020400 0x00000020 0x00000010\t;# MODER\n\tmmw 0x40020408 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x40020420 0x00000900 0x00000600\t;# AFRL\n\n\t# Port D: PD13:AF09:V\n\tmmw 0x40020C00 0x08000000 0x04000000\t;# MODER\n\tmmw 0x40020C08 0x0C000000 0x00000000\t;# OSPEEDR\n\tmmw 0x40020C24 0x00900000 0x00600000\t;# AFRH\n\n\t# Port E: PE02:AF09:V\n\tmmw 0x40021000 0x00000020 0x00000010\t;# MODER\n\tmmw 0x40021008 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x40021020 0x00000900 0x00000600\t;# AFRL\n\n\t# Port F: PF09:AF10:V, PF08:AF10:V\n\tmmw 0x40021400 0x000A0000 0x00050000\t;# MODER\n\tmmw 0x40021408 0x000F0000 0x00000000\t;# OSPEEDR\n\tmmw 0x40021424 0x000000AA 0x00000055\t;# AFRH\n\n\t# Port G: PG06:AF10:V\n\tmmw 0x40021800 0x00002000 0x00001000\t;# MODER\n\tmmw 0x40021808 0x00003000 0x00000000\t;# OSPEEDR\n\tmmw 0x40021820 0x0A000000 0x05000000\t;# AFRL\n\n\tmww 0xA0001030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x03500008\t\t\t\t;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1\n\tmww 0xA0001004 0x00170100\t\t\t\t;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0\n\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# 1-line spi mode\n\tmww 0xA0001014 0x000003F5\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO\n\tsleep 1\n\n\t# memory-mapped read mode with 3-byte addresses\n\tmww 0xA0001014 0x0D002503\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmww 0x40023C00 0x00000003\t\t\t\t;# 3 WS for 96 MHz HCLK\n\tsleep 1\n\tmww 0x40023804 0x24001808\t\t\t\t;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2\n\tmww 0x40023808 0x00001000\t\t\t\t;# APB1: /2, APB2: /1\n\tmmw 0x40023800 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40023808 0x00000002 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\tqspi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f429disc1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# This is an STM32F429 discovery board with a single STM32F429ZI chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090\n#\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32f4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f429discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# This is an STM32F429 discovery board with a single STM32F429ZI chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090\n#\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\nsource [find target/stm32f4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f469discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# This is an STM32F469 discovery board with a single STM32F469NI chip.\n# http://www.st.com/web/catalog/tools/FM116/CL1620/SC959/SS1532/LN1848/PF262395\n#\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\nsource [find target/stm32f4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f469i-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F469I discovery board with a single STM32F469NIH6 chip.\n# http://www.st.com/en/evaluation-tools/32f469idiscovery.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# enable stmqspi\nset QUADSPI 1\n\nsource [find target/stm32f4x.cfg]\n\n# QUADSPI initialization\nproc qspi_init { } {\n\tglobal a\n\tmmw 0x40023830 0x000007FF 0\t\t\t\t;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)\n\tmmw 0x40023838 0x00000002 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PF10: CLK, PB06: BK1_NCS, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0\n\n\t# PB06:AF10:V, PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V\n\n\t# Port B: PB06:AF10:V\n\tmmw 0x40020400 0x00002000 0x00001000\t;# MODER\n\tmmw 0x40020408 0x00003000 0x00000000\t;# OSPEEDR\n\tmmw 0x40020420 0x0A000000 0x05000000\t;# AFRL\n\n\t# Port F: PF10:AF09:V, PF09:AF10:V, PF08:AF10:V, PF07:AF09:V, PF06:AF09:V\n\tmmw 0x40021400 0x002AA000 0x00155000\t;# MODER\n\tmmw 0x40021408 0x003FF000 0x00000000\t;# OSPEEDR\n\tmmw 0x40021420 0x99000000 0x66000000\t;# AFRL\n\tmmw 0x40021424 0x000009AA 0x00000655\t;# AFRH\n\n\tmww 0xA0001030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x03500008\t\t\t\t;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1\n\tmww 0xA0001004 0x00170100\t\t\t\t;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0\n\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# 1-line spi mode\n\tmww 0xA0001014 0x000003F5\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO\n\tsleep 1\n\n\t# memory-mapped read mode with 3-byte addresses\n\tmww 0xA0001014 0x0D002503\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmww 0x40023C00 0x00000005\t\t\t\t;# 5 WS for 160 MHz HCLK\n\tsleep 1\n\tmww 0x40023804 0x24002808\t\t\t\t;# 160 MHz: HSI, PLLM=8, PLLN=160, PLLP=2\n\tmww 0x40023808 0x00009400\t\t\t\t;# APB1: /4, APB2: /2\n\tmmw 0x40023800 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40023808 0x00000002 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\tqspi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f4discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F4 discovery board with a single STM32F407VGT6 chip.\n# http://www.st.com/internet/evalboard/product/252419.jsp\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 64KB\nset WORKAREASIZE 0x10000\n\nsource [find target/stm32f4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f723e-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F723E discovery board with a single STM32F723IEK6 chip.\n# http://www.st.com/en/evaluation-tools/32f723ediscovery.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 128KB\nset WORKAREASIZE 0x20000\n\n# enable stmqspi\nset QUADSPI 1\n\nsource [find target/stm32f7x.cfg]\n\nreset_config srst_only\n\n# QUADSPI initialization\nproc qspi_init { } {\n\tglobal a\n\tmmw 0x40023830 0x000007FF 0\t\t\t\t;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)\n\tmmw 0x40023838 0x00000002 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0\n\n\t# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V\n\n\t# Port B: PB06:AF10:V, PB02:AF09:V\n\tmmw 0x40020400 0x00002020 0x00001010\t;# MODER\n\tmmw 0x40020408 0x00003030 0x00000000\t;# OSPEEDR\n\tmmw 0x40020420 0x0A000900 0x05000600\t;# AFRL\n\n\t# Port C: PC10:AF09:V, PC09:AF09:V\n\tmmw 0x40020800 0x00280000 0x00140000\t;# MODER\n\tmmw 0x40020808 0x003C0000 0x00000000\t;# OSPEEDR\n\tmmw 0x40020824 0x00000990 0x00000660\t;# AFRH\n\n\t# Port D: PD13:AF09:V\n\tmmw 0x40020C00 0x08000000 0x04000000\t;# MODER\n\tmmw 0x40020C08 0x0C000000 0x00000000\t;# OSPEEDR\n\tmmw 0x40020C24 0x00900000 0x00600000\t;# AFRH\n\n\t# Port E: PE02:AF09:V\n\tmmw 0x40021000 0x00000020 0x00000010\t;# MODER\n\tmmw 0x40021008 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x40021020 0x00000900 0x00000600\t;# AFRL\n\n\tmww 0xA0001030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x03500008\t\t\t\t;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1\n\tmww 0xA0001004 0x00190100\t\t\t\t;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0\n\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# 1-line spi mode\n\tmww 0xA0001014 0x000003F5\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO\n\tsleep 1\n\n\t# memory-mapped read mode with 4-byte addresses\n\tmww 0xA0001014 0x0D003513\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmww 0x40023C00 0x00000006\t\t\t\t;# 6 WS for 192 MHz HCLK\n\tsleep 1\n\tmww 0x40023804 0x24003008\t\t\t\t;# 192 MHz: PLLM=8, PLLN=192, PLLP=2\n\tmww 0x40023808 0x00009400\t\t\t\t;# APB1: /4, APB2: /2\n\tmmw 0x40023800 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40023808 0x00000002 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\tqspi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f746g-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F746G discovery board with a single STM32F746NGH6 chip.\n# http://www.st.com/en/evaluation-tools/32f746gdiscovery.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 256KB\nset WORKAREASIZE 0x40000\n\n# enable stmqspi\nset QUADSPI 1\n\nsource [find target/stm32f7x.cfg]\n\nreset_config srst_only\n\n# QUADSPI initialization\nproc qspi_init { } {\n\tglobal a\n\tmmw 0x40023830 0x000007FF 0\t\t\t\t;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)\n\tmmw 0x40023838 0x00000002 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PD12: BK1_IO1, PD11: BK1_IO0\n\n\t# PB06:AF10:V, PB02:AF09:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PE02:AF09:V\n\n\t# Port B: PB06:AF10:V, PB02:AF09:V\n\tmmw 0x40020400 0x00002020 0x00001010\t;# MODER\n\tmmw 0x40020408 0x00003030 0x00000000\t;# OSPEEDR\n\tmmw 0x40020420 0x0A000900 0x05000600\t;# AFRL\n\n\t# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V\n\tmmw 0x40020C00 0x0A800000 0x05400000\t;# MODER\n\tmmw 0x40020C08 0x0FC00000 0x00000000\t;# OSPEEDR\n\tmmw 0x40020C24 0x00999000 0x00666000\t;# AFRH\n\n\t# Port E: PE02:AF09:V\n\tmmw 0x40021000 0x00000020 0x00000010\t;# MODER\n\tmmw 0x40021008 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x40021020 0x00000900 0x00000600\t;# AFRL\n\n\tmww 0xA0001030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x03500008\t\t\t\t;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1\n\tmww 0xA0001004 0x00170100\t\t\t\t;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0\n\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# 1-line spi mode\n\tmww 0xA0001014 0x000003F5\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO\n\tsleep 1\n\n\t# memory-mapped read mode with 3-byte addresses\n\tmww 0xA0001014 0x0D002503\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmww 0x40023C00 0x00000006\t\t\t\t;# 6 WS for 192 MHz HCLK\n\tsleep 1\n\tmww 0x40023804 0x24003008\t\t\t\t;# 192 MHz: PLLM=8, PLLN=192, PLLP=2\n\tmww 0x40023808 0x00009400\t\t\t\t;# APB1: /4, APB2: /2\n\tmmw 0x40023800 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40023808 0x00000002 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\tqspi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f769i-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F769I discovery board with a single STM32F769NIH6 chip.\n# http://www.st.com/en/evaluation-tools/32f769idiscovery.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 256KB\nset WORKAREASIZE 0x40000\n\n# enable stmqspi\nset QUADSPI 1\n\nsource [find target/stm32f7x.cfg]\n\nreset_config srst_only\n\n# QUADSPI initialization\nproc qspi_init { } {\n\tglobal a\n\tmmw 0x40023830 0x000007FF 0\t\t\t\t;# RCC_AHB1ENR |= GPIOAEN-GPIOKEN (enable clocks)\n\tmmw 0x40023838 0x00000002 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PB02: CLK, PB06: BK1_NCS, PD13: BK1_IO3, PE02: BK1_IO2, PC10: BK1_IO1, PC09: BK1_IO0\n\n\t# PB06:AF10:V, PB02:AF09:V, PC10:AF09:V, PC09:AF09:V, PD13:AF09:V, PE02:AF09:V\n\n\t# Port B: PB06:AF10:V, PB02:AF09:V\n\tmmw 0x40020400 0x00002020 0x00001010\t;# MODER\n\tmmw 0x40020408 0x00003030 0x00000000\t;# OSPEEDR\n\tmmw 0x40020420 0x0A000900 0x05000600\t;# AFRL\n\n\t# Port C: PC10:AF09:V, PC09:AF09:V\n\tmmw 0x40020800 0x00280000 0x00140000\t;# MODER\n\tmmw 0x40020808 0x003C0000 0x00000000\t;# OSPEEDR\n\tmmw 0x40020824 0x00000990 0x00000660\t;# AFRH\n\n\t# Port D: PD13:AF09:V\n\tmmw 0x40020C00 0x08000000 0x04000000\t;# MODER\n\tmmw 0x40020C08 0x0C000000 0x00000000\t;# OSPEEDR\n\tmmw 0x40020C24 0x00900000 0x00600000\t;# AFRH\n\n\t# Port E: PE02:AF09:V\n\tmmw 0x40021000 0x00000020 0x00000010\t;# MODER\n\tmmw 0x40021008 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x40021020 0x00000900 0x00000600\t;# AFRL\n\n\tmww 0xA0001030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x03500008\t\t\t\t;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1\n\tmww 0xA0001004 0x00190100\t\t\t\t;# QUADSPI_DCR: FSIZE=0x19, CSHT=0x01, CKMODE=0\n\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# exit qpi mode\n\tmww 0xA0001014 0x000033f5\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO\n\n\t# 1-line memory-mapped read mode with 4-byte addresses\n\tmww 0xA0001014 0x0D003513\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ\n\n\t# 4-line qpi mode\n\tmww 0xA0001014 0x00003135\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=EQIO\n\n\t# 4-line memory-mapped read mode with 4-byte addresses\n\tmww 0xA0001014 0x0F283FEC\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0xA, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=4READ4B\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmww 0x40023C00 0x00000006\t\t\t\t;# 6 WS for 192 MHz HCLK\n\tsleep 1\n\tmww 0x40023804 0x24003008\t\t\t\t;# 192 MHz: PLLM=8, PLLN=192, PLLP=2\n\tmww 0x40023808 0x00009400\t\t\t\t;# APB1: /4, APB2: /2\n\tmmw 0x40023800 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40023808 0x00000002 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\tqspi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32f7discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32F7 discovery board with a single STM32F756NGH6 chip.\n# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641\n\n# This is for using the onboard STLINK/V2-1\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 256KB\nset WORKAREASIZE 0x40000\n\nsource [find target/stm32f7x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32h735g-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is a stm32h735g-dk with a single STM32H735IGK6 chip.\n# https://www.st.com/en/evaluation-tools/stm32h735g-dk.html\n#\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset CHIPNAME stm32h735igk6\n\n# enable stmqspi\nif {![info exists OCTOSPI1]} {\n\tset OCTOSPI1 1\n\tset OCTOSPI2 0\n}\n\nsource [find target/stm32h7x.cfg]\n\nreset_config srst_only\n\n# OCTOSPI initialization\n# octo: 8-line mode\nproc octospi_init { octo } {\n\tglobal a b\n\tmmw 0x58024540 0x000006FF 0\t\t\t\t;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)\n\tmmw 0x58024534 0x00284000 0\t\t\t\t;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\tmww 0x5200B404 0x03010111\t\t\t\t;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1\n\tmww 0x5200B408 0x00000000\t\t\t\t;# OCTOSPIM_P2CR: disable Port 2\n\n\t# PG06: OCSPI1_NCS, PF10: OCSPI1_CLK, PB02: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PD05: OCSPI1_IO5,\n\t# PD04: OCSPI1_IO4, PD13: OCSPI1_IO3, PE02: OCSPI1_IO2, PD12: OCSPI1_IO1, PD11: OCSPI1_IO0\n\n\t# PB02:AF10:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V\n\t# PD04:AF10:V, PE02:AF09:V, PF10:AF09:V, PG09:AF09:V, PG06:AF10:V\n\t# Port B: PB02:AF10:V\n\tmmw 0x58020400 0x00000020 0x00000010\t;# MODER\n\tmmw 0x58020408 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x5802040C 0x00000000 0x00000030\t;# PUPDR\n\tmmw 0x58020420 0x00000A00 0x00000500\t;# AFRL\n\t# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V\n\tmmw 0x58020C00 0x0A808A00 0x05404500\t;# MODER\n\tmmw 0x58020C08 0x0FC0CF00 0x00000000\t;# OSPEEDR\n\tmmw 0x58020C0C 0x00000000 0x0FC0CF00\t;# PUPDR\n\tmmw 0x58020C20 0xA0AA0000 0x50550000\t;# AFRL\n\tmmw 0x58020C24 0x00999000 0x00666000\t;# AFRH\n\t# Port E: PE02:AF09:V\n\tmmw 0x58021000 0x00000020 0x00000010\t;# MODER\n\tmmw 0x58021008 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x5802100C 0x00000000 0x00000030\t;# PUPDR\n\tmmw 0x58021020 0x00000900 0x00000600\t;# AFRL\n\t# Port F: PF10:AF09:V\n\tmmw 0x58021400 0x00200000 0x00100000\t;# MODER\n\tmmw 0x58021408 0x00300000 0x00000000\t;# OSPEEDR\n\tmmw 0x5802140C 0x00000000 0x00300000\t;# PUPDR\n\tmmw 0x58021424 0x00000900 0x00000600\t;# AFRH\n\t# Port G: PG09:AF09:V, PG06:AF10:V\n\tmmw 0x58021800 0x00082000 0x00041000\t;# MODER\n\tmmw 0x58021808 0x000C3000 0x00000000\t;# OSPEEDR\n\tmmw 0x5802180C 0x00000000 0x000C3000\t;# PUPDR\n\tmmw 0x58021820 0x0A000000 0x05000000\t;# AFRL\n\tmmw 0x58021824 0x00000090 0x00000060\t;# AFRH\n\n\t# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses\n\tmww 0x52005130 0x00001000\t\t\t\t;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0x52005000 0x3040000B\t\t\t\t;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0\n\tmww 0x52005008 0x01190100\t\t\t\t;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0\n\tmww 0x5200500C 0x00000005\t\t\t\t;# OCTOSPI_DCR2: PRESCALER=5\n\n\tmww 0x52005108 0x00000000\t\t\t\t;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0\n\tmww 0x52005100 0x01003101\t\t\t\t;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1\n\tmww 0x52005110 0x00000013\t\t\t\t;# OCTOSPI_IR: INSTR=READ4B\n\n\tflash probe $a\t\t\t\t\t\t\t;# load configuration from CR, TCR, CCR, IR register values\n\n\tif { $octo == 1 } {\n\t\tstmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00\t\t\t;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits\n\t\tstmqspi cmd $a 0 0x06\t\t\t\t\t\t\t\t;# Write Enable\n\t\tstmqspi cmd $a 1 0x05\t\t\t\t\t\t\t\t;# Read Status Register\n\t\tstmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02\t\t;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable\n\n\t\t# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses\n\t\tmww 0x52005000 0x3040000B\t\t\t\t;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1\n\t\tmww 0x52005108 0x10000006\t\t\t\t;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6\n\t\tmww 0x52005100 0x2C003C1C\t\t\t\t;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4\n\t\tmww 0x52005110 0x0000EE11\t\t\t\t;# OCTOSPI_IR: INSTR=OCTA DTR Read\n\n\t\tflash probe $a\t\t\t\t\t\t\t;# reload configuration from CR, TCR, CCR, IR register values\n\n\t\tstmqspi cmd $a 0 0x06\t\t\t\t\t\t\t\t;# Write Enable\n\t\tstmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00\t\t\t;# Read Status Register (note dummy address in 8-line mode)\n\t\tstmqspi cmd $a 0 0x04\t\t\t\t\t\t\t\t;# Write Disable\n\t\tstmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00\t\t\t;# Read Status Register (note dummy address in 8-line mode)\n\t\tstmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00\t\t\t;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits\n\t}\n}\n\n$_CHIPNAME.cpu0 configure -event reset-init {\n\tglobal OCTOSPI1\n\tglobal OCTOSPI2\n\n\tmmw 0x52002000 0x00000004 0x0000000B\t;# FLASH_ACR: 4 WS for 192 MHZ HCLK\n\n\tmmw 0x58024400 0x00000001 0x00000018\t;# RCC_CR: HSIDIV=1, HSI on\n\tmmw 0x58024410 0x10000000 0xEE000007\t;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock\n\tmww 0x58024418 0x00000040\t\t\t\t;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1\n\tmww 0x5802441C 0x00000440\t\t\t\t;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2\n\tmww 0x58024420 0x00000040\t\t\t\t;# RCC_D3CFGR: D3PPRE=2\n\tmww 0x58024428 0x00000040\t\t\t\t;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI\n\tmmw 0x5802442C 0x0001000C 0x00000002\t;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide\n\tmww 0x58024430 0x01070217\t\t\t\t;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24\n\tmmw 0x58024400 0x01000000 0\t\t\t\t;# RCC_CR: PLL1ON=1\n\tsleep 1\n\tmmw 0x58024410 0x00000003 0\t\t\t\t;# RCC_CFGR: PLL1 as system clock\n\tsleep 1\n\n\tadapter speed 24000\n\n\tif { $OCTOSPI1 } {\n\t\toctospi_init 1\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32h745i-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is a stm32h745i-disco with a single STM32H745XIH6 chip.\n# www.st.com/en/product/stm32h745i-disco.html\n#\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset CHIPNAME stm32h745xih6\n\n# enable stmqspi\nif {![info exists QUADSPI]} {\n\tset QUADSPI 1\n}\n\nsource [find target/stm32h7x_dual_bank.cfg]\n\nreset_config srst_only\n\nsource [find board/stm32h7x_dual_qspi.cfg]\n\n$_CHIPNAME.cpu0 configure -event reset-init {\n\tglobal QUADSPI\n\n\tmmw 0x52002000 0x00000004 0x0000000B\t;# FLASH_ACR: 4 WS for 192 MHZ HCLK\n\n\tmmw 0x58024400 0x00000001 0x00000018\t;# RCC_CR: HSIDIV=1, HSI on\n\tmmw 0x58024410 0x10000000 0xEE000007\t;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock\n\tmww 0x58024418 0x00000040\t\t\t\t;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1\n\tmww 0x5802441C 0x00000440\t\t\t\t;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2\n\tmww 0x58024420 0x00000040\t\t\t\t;# RCC_D3CFGR: D3PPRE=2\n\tmww 0x58024428 0x00000040\t\t\t\t;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI\n\tmmw 0x5802442C 0x0001000C 0x00000002\t;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide\n\tmww 0x58024430 0x01070217\t\t\t\t;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24\n\tmmw 0x58024400 0x01000000 0\t\t\t\t;# RCC_CR: PLL1ON=1\n\tsleep 1\n\tmmw 0x58024410 0x00000003 0\t\t\t\t;# RCC_CFGR: PLL1 as system clock\n\tsleep 1\n\n\tadapter speed 24000\n\n\tif { $QUADSPI } {\n\t\tqspi_init 1\n\t}\n}\n\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32h747i-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is a stm32h747i-disco with a single STM32H747XIH6 chip.\n# www.st.com/en/product/stm32h747i-disco.html\n#\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset CHIPNAME stm32h747xih6\n\n# enable stmqspi\nif {![info exists QUADSPI]} {\n\tset QUADSPI 1\n}\n\nsource [find target/stm32h7x_dual_bank.cfg]\n\nreset_config srst_only\n\n# QUADSPI initialization\n# qpi: 4-line mode\nproc qspi_init { qpi } {\n\tglobal a\n\tmmw 0x580244E0 0x000007FF 0\t\t\t\t;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)\n\tmmw 0x580244D4 0x00004000 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PG06: BK1_NCS, PB02: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,\n\t# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0\n\n\t# PB02:AF09:V, PD11:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H\n\t# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V\n\n\t# Port B: PB02:AF09:V\n\tmmw 0x58020400 0x00000020 0x00000010\t;# MODER\n\tmmw 0x58020408 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x58020420 0x00000900 0x00000600\t;# AFRL\n\t# Port D: PD11:AF09:V\n\tmmw 0x58020C00 0x00800000 0x00400000\t;# MODER\n\tmmw 0x58020C08 0x00C00000 0x00000000\t;# OSPEEDR\n\tmmw 0x58020C24 0x00009000 0x00006000\t;# AFRH\n\t# Port F: PF09:AF10:V, PF07:AF09:V, PF06:AF09:V\n\tmmw 0x58021400 0x0008A000 0x00045000\t;# MODER\n\tmmw 0x58021408 0x000CF000 0x00000000\t;# OSPEEDR\n\tmmw 0x58021420 0x99000000 0x66000000\t;# AFRL\n\tmmw 0x58021424 0x000000A0 0x00000050\t;# AFRH\n\t# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H\n\tmmw 0x58021800 0x20082000 0x10041000\t;# MODER\n\tmmw 0x58021808 0x200C2000 0x10001000\t;# OSPEEDR\n\tmmw 0x58021820 0x0A000000 0x05000000\t;# AFRL\n\tmmw 0x58021824 0x09000090 0x06000060\t;# AFRH\n\t# Port H: PH03:AF09:V, PH02:AF09:V\n\tmmw 0x58021C00 0x000000A0 0x00000050\t;# MODER\n\tmmw 0x58021C08 0x000000F0 0x00000000\t;# OSPEEDR\n\tmmw 0x58021C20 0x00009900 0x00006600\t;# AFRL\n\n\t# correct FSIZE is 0x1A, however, this causes trouble when\n\t# reading the last bytes at end of bank in *memory mapped* mode\n\n\t# for dual flash mode 2 * mt25ql512\n\tmww 0x52005000 0x05500058\t\t\t\t;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1\n\tmww 0x52005004 0x001A0200\t\t\t\t;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0\n\n\tmww 0x52005030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0x52005014 0x0D002503\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1\n\tmmw 0x52005000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# Exit QPI mode\n\tmmw 0x52005000 0x00000002 0\t\t\t\t;# QUADSPI_CR: ABORT=1\n\tmww 0x52005014 0x000003F5\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI\n\tsleep 1\n\n\tif { $qpi == 1 } {\n\t\t# Write Enable\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x00000106\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable\n\t\tsleep 1\n\n\t\t# Configure dummy clocks via volatile configuration register\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005010 0x00000001\t\t\t;# QUADSPI_DLR: 2 data bytes\n\t\tmww 0x52005014 0x01000181\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.\n\t\tmwh 0x52005020 0xABAB\t\t\t\t;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks\n\t\tsleep 1\n\n\t\t# Write Enable\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x00000106\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable\n\t\tsleep 1\n\n\t\t# Enable QPI mode via enhanced volatile configuration register\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005010 0x00000001\t\t\t;# QUADSPI_DLR: 2 data bytes\n\t\tmww 0x52005014 0x01000161\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.\n\t\tmwh 0x52005020 0x3F3F\t\t\t\t;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode\n\t\tsleep 1\n\n\t\t# Enter QPI mode\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x00000135\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI\n\t\tsleep 1\n\n\t\t# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x0F283FEC\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ\n\t} else {\n\t\t# memory-mapped read mode with 4-byte addresses\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x0D003513\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ\n\t}\n}\n\n$_CHIPNAME.cpu0 configure -event reset-init {\n\tglobal QUADSPI\n\n\tmmw 0x52002000 0x00000004 0x0000000B\t;# FLASH_ACR: 4 WS for 192 MHZ HCLK\n\n\tmmw 0x58024400 0x00000001 0x00000018\t;# RCC_CR: HSIDIV=1, HSI on\n\tmmw 0x58024410 0x10000000 0xEE000007\t;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock\n\tmww 0x58024418 0x00000040\t\t\t\t;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1\n\tmww 0x5802441C 0x00000440\t\t\t\t;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2\n\tmww 0x58024420 0x00000040\t\t\t\t;# RCC_D3CFGR: D3PPRE=2\n\tmww 0x58024428 0x00000040\t\t\t\t;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI\n\tmmw 0x5802442C 0x0001000C 0x00000002\t;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide\n\tmww 0x58024430 0x01070217\t\t\t\t;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24\n\tmmw 0x58024400 0x01000000 0\t\t\t\t;# RCC_CR: PLL1ON=1\n\tsleep 1\n\tmmw 0x58024410 0x00000003 0\t\t\t\t;# RCC_CFGR: PLL1 as system clock\n\tsleep 1\n\n\tadapter speed 24000\n\n\tif { $QUADSPI } {\n\t\tqspi_init 1\n\t}\n}\n\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32h750b-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is a stm32h750b-dk with a single STM32H750XBH6 chip.\n# www.st.com/en/product/stm32h750b-dk.html\n#\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset CHIPNAME stm32h750xbh6\n\n# enable stmqspi\nif {![info exists QUADSPI]} {\n\tset QUADSPI 1\n}\n\nsource [find target/stm32h7x.cfg]\n\nreset_config srst_only\n\nsource [find board/stm32h7x_dual_qspi.cfg]\n\n$_CHIPNAME.cpu0 configure -event reset-init {\n\tglobal QUADSPI\n\n\tmmw 0x52002000 0x00000004 0x0000000B\t;# FLASH_ACR: 4 WS for 192 MHZ HCLK\n\n\tmmw 0x58024400 0x00000001 0x00000018\t;# RCC_CR: HSIDIV=1, HSI on\n\tmmw 0x58024410 0x10000000 0xEE000007\t;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock\n\tmww 0x58024418 0x00000040\t\t\t\t;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1\n\tmww 0x5802441C 0x00000440\t\t\t\t;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2\n\tmww 0x58024420 0x00000040\t\t\t\t;# RCC_D3CFGR: D3PPRE=2\n\tmww 0x58024428 0x00000040\t\t\t\t;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI\n\tmmw 0x5802442C 0x0001000C 0x00000002\t;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide\n\tmww 0x58024430 0x01070217\t\t\t\t;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24\n\tmmw 0x58024400 0x01000000 0\t\t\t\t;# RCC_CR: PLL1ON=1\n\tsleep 1\n\tmmw 0x58024410 0x00000003 0\t\t\t\t;# RCC_CFGR: PLL1 as system clock\n\tsleep 1\n\n\tadapter speed 24000\n\n\tif { $QUADSPI } {\n\t\tqspi_init 1\n\t}\n}\n\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32h7b3i-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is a stm32h7b3i-dk with a single STM32H7B3LIH6Q chip.\n# https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html\n#\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset CHIPNAME stm32h7b3lih6q\n\n# enable stmqspi\nif {![info exists OCTOSPI1]} {\n\tset OCTOSPI1 1\n\tset OCTOSPI2 0\n}\n\nsource [find target/stm32h7x_dual_bank.cfg]\n\nreset_config srst_only\n\n# OCTOSPI initialization\n# octo: 8-line mode\nproc octospi_init { octo } {\n\tglobal a b\n\tmmw 0x58024540 0x000007FF 0\t\t\t\t;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)\n\tmmw 0x58024534 0x00284000 0\t\t\t\t;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\tmww 0x5200B404 0x03010111\t\t\t\t;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1\n\tmww 0x5200B408 0x00000000\t\t\t\t;# OCTOSPIM_P2CR: disable Port 2\n\n\t# PG06: OCSPI1_NCS, PB02: OCSPI1_CLK, PC05: OCSPI1_DQS, PD07: OCSPI1_IO7, PG09: OCSPI1_IO6, PH03: OCSPI1_IO5,\n\t# PC01: OCSPI1_IO4, PF06: OCSPI1_IO3, PF07: OCSPI1_IO2, PF09: OCSPI1_IO1, PD11: OCSPI1_IO0\n\n\t# PB02:AF09:V, PC05:AF10:V, PC01:AF10:V, PD11:AF09:V, PD07:AF10:V, PF09:AF10:V\n\t# PF07:AF10:V, PF06:AF10:V, PG09:AF09:V, PG06:AF10:V, PH03:AF09:V\n\t# Port B: PB02:AF09:V\n\tmmw 0x58020400 0x00000020 0x00000010\t;# MODER\n\tmmw 0x58020408 0x00000030 0x00000000\t;# OSPEEDR\n\tmmw 0x5802040C 0x00000000 0x00000030\t;# PUPDR\n\tmmw 0x58020420 0x00000900 0x00000600\t;# AFRL\n\t# Port C: PC05:AF10:V, PC01:AF10:V\n\tmmw 0x58020800 0x00000808 0x00000404\t;# MODER\n\tmmw 0x58020808 0x00000C0C 0x00000000\t;# OSPEEDR\n\tmmw 0x5802080C 0x00000000 0x00000C0C\t;# PUPDR\n\tmmw 0x58020820 0x00A000A0 0x00500050\t;# AFRL\n\t# Port D: PD11:AF09:V, PD07:AF10:V\n\tmmw 0x58020C00 0x00808000 0x00404000\t;# MODER\n\tmmw 0x58020C08 0x00C0C000 0x00000000\t;# OSPEEDR\n\tmmw 0x58020C0C 0x00000000 0x00C0C000\t;# PUPDR\n\tmmw 0x58020C20 0xA0000000 0x50000000\t;# AFRL\n\tmmw 0x58020C24 0x00009000 0x00006000\t;# AFRH\n\t# Port F: PF09:AF10:V, PF07:AF10:V, PF06:AF10:V\n\tmmw 0x58021400 0x0008A000 0x00045000\t;# MODER\n\tmmw 0x58021408 0x000CF000 0x00000000\t;# OSPEEDR\n\tmmw 0x5802140C 0x00000000 0x000CF000\t;# PUPDR\n\tmmw 0x58021420 0xAA000000 0x55000000\t;# AFRL\n\tmmw 0x58021424 0x000000A0 0x00000050\t;# AFRH\n\t# Port G: PG09:AF09:V, PG06:AF10:V\n\tmmw 0x58021800 0x00082000 0x00041000\t;# MODER\n\tmmw 0x58021808 0x000C3000 0x00000000\t;# OSPEEDR\n\tmmw 0x5802180C 0x00000000 0x000C3000\t;# PUPDR\n\tmmw 0x58021820 0x0A000000 0x05000000\t;# AFRL\n\tmmw 0x58021824 0x00000090 0x00000060\t;# AFRH\n\t# Port H: PH03:AF09:V\n\tmmw 0x58021C00 0x00000080 0x00000040\t;# MODER\n\tmmw 0x58021C08 0x000000C0 0x00000000\t;# OSPEEDR\n\tmmw 0x58021C0C 0x00000000 0x000000C0\t;# PUPDR\n\tmmw 0x58021C20 0x00009000 0x00006000\t;# AFRL\n\n\t# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses\n\tmww 0x52005130 0x00001000\t\t\t\t;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0x52005000 0x3040000B\t\t\t\t;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0\n\tmww 0x52005008 0x01190100\t\t\t\t;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0\n\tmww 0x5200500C 0x00000005\t\t\t\t;# OCTOSPI_DCR2: PRESCALER=5\n\n\tmww 0x52005108 0x00000000\t\t\t\t;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0\n\tmww 0x52005100 0x01003101\t\t\t\t;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1\n\tmww 0x52005110 0x00000013\t\t\t\t;# OCTOSPI_IR: INSTR=READ4B\n\n\tflash probe $a\t\t\t\t\t\t\t;# load configuration from CR, TCR, CCR, IR register values\n\n\tif { $octo == 1 } {\n\t\tstmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00\t\t\t;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits\n\t\tstmqspi cmd $a 0 0x06\t\t\t\t\t\t\t\t;# Write Enable\n\t\tstmqspi cmd $a 1 0x05\t\t\t\t\t\t\t\t;# Read Status Register\n\t\tstmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02\t\t;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable\n\n\t\t# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses\n\t\tmww 0x52005000 0x3040000B\t\t\t\t;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1\n\t\tmww 0x52005108 0x10000006\t\t\t\t;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6\n\t\tmww 0x52005100 0x2C003C1C\t\t\t\t;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4\n\t\tmww 0x52005110 0x0000EE11\t\t\t\t;# OCTOSPI_IR: INSTR=OCTA DTR Read\n\n\t\tflash probe $a\t\t\t\t\t\t\t;# reload configuration from CR, TCR, CCR, IR register values\n\n\t\tstmqspi cmd $a 0 0x06\t\t\t\t\t\t\t\t;# Write Enable\n\t\tstmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00\t\t\t;# Read Status Register (note dummy address in 8-line mode)\n\t\tstmqspi cmd $a 0 0x04\t\t\t\t\t\t\t\t;# Write Disable\n\t\tstmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00\t\t\t;# Read Status Register (note dummy address in 8-line mode)\n\t\tstmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00\t\t\t;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits\n\t}\n}\n\n$_CHIPNAME.cpu0 configure -event reset-init {\n\tglobal OCTOSPI1\n\tglobal OCTOSPI2\n\n\tmmw 0x52002000 0x00000004 0x0000000B\t;# FLASH_ACR: 4 WS for 192 MHZ HCLK\n\n\tmmw 0x58024400 0x00000001 0x00000018\t;# RCC_CR: HSIDIV=1, HSI on\n\tmmw 0x58024410 0x10000000 0xEE000007\t;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock\n\tmww 0x58024418 0x00000040\t\t\t\t;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1\n\tmww 0x5802441C 0x00000440\t\t\t\t;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2\n\tmww 0x58024420 0x00000040\t\t\t\t;# RCC_D3CFGR: D3PPRE=2\n\tmww 0x58024428 0x00000040\t\t\t\t;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI\n\tmmw 0x5802442C 0x0001000C 0x00000002\t;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide\n\tmww 0x58024430 0x01070217\t\t\t\t;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24\n\tmmw 0x58024400 0x01000000 0\t\t\t\t;# RCC_CR: PLL1ON=1\n\tsleep 1\n\tmmw 0x58024410 0x00000003 0\t\t\t\t;# RCC_CFGR: PLL1 as system clock\n\tsleep 1\n\n\tadapter speed 24000\n\n\tif { $OCTOSPI1 } {\n\t\toctospi_init 1\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32h7x3i_eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STM32H7[4|5]3I-EVAL: this is for the H7 eval boards.\n# This is an ST EVAL-H743XI board with single STM32H743XI chip.\n# http://www.st.com/en/evaluation-tools/stm32h743i-eval.html\n# This is an ST EVAL-H753XI board with single STM32H753XI chip.\n# http://www.st.com/en/evaluation-tools/stm32h753i-eval.html\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32h7x_dual_bank.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32h7x_dual_qspi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# stm32h754i-disco and stm32h750b-dk dual quad qspi.\n\n# QUADSPI initialization\n# qpi: 4-line mode\nproc qspi_init { qpi } {\n\tglobal a\n\tmmw 0x580244E0 0x000007FF 0\t\t\t\t;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)\n\tmmw 0x580244D4 0x00004000 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PG06: BK1_NCS, PF10: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,\n\t# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0\n\n\t# PD11:AF09:V, PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H\n\t# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V\n\n\t# Port D: PD11:AF09:V\n\tmmw 0x58020C00 0x00800000 0x00400000\t;# MODER\n\tmmw 0x58020C08 0x00C00000 0x00000000\t;# OSPEEDR\n\tmmw 0x58020C24 0x00009000 0x00006000\t;# AFRH\n\t# Port F: PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V\n\tmmw 0x58021400 0x0028A000 0x00145000\t;# MODER\n\tmmw 0x58021408 0x003CF000 0x00000000\t;# OSPEEDR\n\tmmw 0x58021420 0x99000000 0x66000000\t;# AFRL\n\tmmw 0x58021424 0x000009A0 0x00000650\t;# AFRH\n\t# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H\n\tmmw 0x58021800 0x20082000 0x10041000\t;# MODER\n\tmmw 0x58021808 0x200C2000 0x10001000\t;# OSPEEDR\n\tmmw 0x58021820 0x0A000000 0x05000000\t;# AFRL\n\tmmw 0x58021824 0x09000090 0x06000060\t;# AFRH\n\t# Port H: PH03:AF09:V, PH02:AF09:V\n\tmmw 0x58021C00 0x000000A0 0x00000050\t;# MODER\n\tmmw 0x58021C08 0x000000F0 0x00000000\t;# OSPEEDR\n\tmmw 0x58021C20 0x00009900 0x00006600\t;# AFRL\n\n\t# correct FSIZE is 0x1A, however, this causes trouble when\n\t# reading the last bytes at end of bank in *memory mapped* mode\n\n\t# for dual flash mode 2 * mt25ql512\n\tmww 0x52005000 0x05500058\t\t\t\t;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1\n\tmww 0x52005004 0x001A0200\t\t\t\t;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0\n\n\tmww 0x52005030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0x52005014 0x0D002503\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1\n\tmmw 0x52005000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# Exit QPI mode\n\tmmw 0x52005000 0x00000002 0\t\t\t\t;# QUADSPI_CR: ABORT=1\n\tmww 0x52005014 0x000003F5\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI\n\tsleep 1\n\n\tif { $qpi == 1 } {\n\t\t# Write Enable\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x00000106\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable\n\t\tsleep 1\n\n\t\t# Configure dummy clocks via volatile configuration register\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005010 0x00000001\t\t\t;# QUADSPI_DLR: 2 data bytes\n\t\tmww 0x52005014 0x01000181\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.\n\t\tmwh 0x52005020 0xABAB\t\t\t\t;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks\n\t\tsleep 1\n\n\t\t# Write Enable\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x00000106\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable\n\t\tsleep 1\n\n\t\t# Enable QPI mode via enhanced volatile configuration register\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005010 0x00000001\t\t\t;# QUADSPI_DLR: 2 data bytes\n\t\tmww 0x52005014 0x01000161\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.\n\t\tmwh 0x52005020 0x3F3F\t\t\t\t;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode\n\t\tsleep 1\n\n\t\t# Enter QPI mode\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x00000135\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI\n\t\tsleep 1\n\n\t\t# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x0F283FEC\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ\n\t} else {\n\t\t# memory-mapped read mode with 4-byte addresses\n\t\tmmw 0x52005000 0x00000002 0\t\t\t;# QUADSPI_CR: ABORT=1\n\t\tmww 0x52005014 0x0D003513\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32l0discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32L053 discovery board with a single STM32L053 chip.\n# http://www.st.com/web/en/catalog/tools/PF260319\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset WORKAREASIZE 0x2000\nsource [find target/stm32l0.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32l476g-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32L476G discovery board with a single STM32L476VGT6 chip.\n# http://www.st.com/en/evaluation-tools/32l476gdiscovery.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 96KB\nset WORKAREASIZE 0x18000\n\n# enable stmqspi\nset QUADSPI 1\n\nsource [find target/stm32l4x.cfg]\n\n# QUADSPI initialization\nproc qspi_init { } {\n\tglobal a\n\tmmw 0x4002104C 0x000001FF 0\t\t\t\t;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)\n\tmmw 0x40021050 0x00000100 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0\n\n\t# PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V\n\n\t# Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V\n\tmmw 0x48001000 0xAAA00000 0x55500000    ;# MODER\n\tmmw 0x48001008 0xFFF00000 0x00000000    ;# OSPEEDR\n\tmmw 0x48001024 0xAAAAAA00 0x55555500    ;# AFRH\n\n\tmww 0xA0001030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x01500008\t\t\t\t;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1\n\tmww 0xA0001004 0x00170100\t\t\t\t;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0\n\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# memory-mapped read mode with 3-byte addresses\n\tmww 0xA0001014 0x0D002503\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmmw 0x40022000 0x00000004 0x00000003\t;# 4 WS for 72 MHz HCLK\n\tsleep 1\n\tmmw 0x40021000 0x00000100 0x00000000\t;# HSI on\n\tmww 0x4002100C 0x01002432\t\t\t\t;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI\n\tmww 0x40021008 0x00008001\t\t\t\t;# always HSI, APB1: /1, APB2: /1\n\tmmw 0x40021000 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40021008 0x00000003 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\tqspi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32l496g-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32L496G discovery board with a single STM32L496AGI6 chip.\n# http://www.st.com/en/evaluation-tools/32l496gdiscovery.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 96KB\nset WORKAREASIZE 0x18000\n\n# enable stmqspi\nset QUADSPI 1\n\nsource [find target/stm32l4x.cfg]\n\n# QUADSPI initialization\nproc qspi_init { } {\n\tglobal a\n\tmmw 0x4002104C 0x000001FF 0\t\t\t\t;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)\n\tmmw 0x40021050 0x00000100 0\t\t\t\t;# RCC_AHB3ENR |= QSPIEN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\t# PB11: BK1_NCS, PA03: CLK, PA06: BK1_IO3, PA07: BK1_IO2, PB00: BK1_IO1, PB01: BK1_IO0\n\n\t# PA07:AF10:V, PA06:AF10:V, PA03:AF10:V, PB11:AF10:V, PB01:AF10:V, PB00:AF10:V\n\n\t# Port A: PA07:AF10:V, PA06:AF10:V, PA03:AF10:V\n\tmmw 0x48000000 0x0000A080 0x00005040    ;# MODER\n\tmmw 0x48000008 0x0000F0C0 0x00000000    ;# OSPEEDR\n\tmmw 0x48000020 0xAA00A000 0x55005000    ;# AFRL\n\n\t# Port B: PB11:AF10:V, PB01:AF10:V, PB00:AF10:V\n\tmmw 0x48000400 0x0080000A 0x00400005    ;# MODER\n\tmmw 0x48000408 0x00C0000F 0x00000000    ;# OSPEEDR\n\tmmw 0x48000420 0x000000AA 0x00000055    ;# AFRL\n\tmmw 0x48000424 0x0000A000 0x00005000    ;# AFRH\n\n\tmww 0xA0001030 0x00001000\t\t\t\t;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x01500008\t\t\t\t;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1\n\tmww 0xA0001004 0x00160100\t\t\t\t;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0\n\tmmw 0xA0001000 0x00000001 0\t\t\t\t;# QUADSPI_CR: EN=1\n\n\t# 1-line spi mode\n\tmww 0xA0001014 0x000003F5\t\t\t\t;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO\n\tsleep 1\n\n\t# memory-mapped read mode with 3-byte addresses\n\tmww 0xA0001014 0x0D002503\t\t\t\t;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmmw 0x40022000 0x00000004 0x00000003\t;# 4 WS for 72 MHz HCLK\n\tsleep 1\n\tmmw 0x40021000 0x00000100 0x00000000\t;# HSI on\n\tmww 0x4002100C 0x01002432\t\t\t\t;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI\n\tmww 0x40021008 0x00008001\t\t\t\t;# always HSI, APB1: /1, APB2: /1\n\tmmw 0x40021000 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40021008 0x00000003 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\tqspi_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32l4discovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Explicitly for the STM32L476 discovery board:\n# http://www.st.com/web/en/catalog/tools/PF261635\n# but perfectly functional for any other STM32L4 board connected via\n# an stlink-v2-1 interface.\n# This is for STM32L4 boards that are connected via stlink-v2-1.\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nsource [find target/stm32l4x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32l4p5g-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is a STM32L4P5G discovery board with a single STM32L4R9AGI6 chip.\n# http://www.st.com/en/evaluation-tools/stm32l4p5g-dk.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 96KB\nset WORKAREASIZE 0x18000\n\n# enable stmqspi\nset OCTOSPI1 1\nset OCTOSPI2 0\n\nsource [find target/stm32l4x.cfg]\n\n# OCTOSPI initialization\n# octo: 8-line mode\nproc octospi_init { octo } {\n\tglobal a b\n\tmmw 0x4002104C 0x001001FF 0\t\t\t\t;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)\n\tmmw 0x40021050 0x00000300 0\t\t\t\t;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)\n\tmmw 0x40021058 0x10000000 0\t\t\t\t;# RCC_APB1ENR1 |= PWREN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\tmmw 0x40007004 0x00000200 0\t\t\t\t;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)\n\n\tmww 0x50061C04 0x07050333\t\t\t\t;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI2\n\tmww 0x50061C08 0x03010111\t\t\t\t;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1\n\n\t# PE11: P1_NCS, PE10: P1_CLK, PG06: P1_DQS, PD07: P1_IO7, PC03: P1_IO6, PD05: P1_IO5\n\t# PD04: P1_IO4, PA06: P1_IO3, PA07: P1_IO2, PE13: P1_IO1, PE11: P1_IO0\n\n\t# PA07:AF10:V, PA06:AF10:V, PC03:AF10:V, PD07:AF10:V, PD05:AF10:V, PD04:AF10:V\n\t# PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V, PG06:AF03:V\n\n\t# Port A: PA07:AF10:V, PA06:AF10:V\n\tmmw 0x48000000 0x0000A000 0x00005000\t;# MODER\n\tmmw 0x48000008 0x0000F000 0x00000000\t;# OSPEEDR\n\tmmw 0x4800000C 0x00000000 0x0000F000\t;# PUPDR\n\tmmw 0x48000020 0xAA000000 0x55000000\t;# AFRL\n\t# Port C: PC03:AF10:V\n\tmmw 0x48000800 0x00000080 0x00000040\t;# MODER\n\tmmw 0x48000808 0x000000C0 0x00000000\t;# OSPEEDR\n\tmmw 0x4800080C 0x00000000 0x000000C0\t;# PUPDR\n\tmmw 0x48000820 0x0000A000 0x00005000\t;# AFRL\n\t# Port D: PD07:AF10:V, PD05:AF10:V, PD04:AF10:V\n\tmmw 0x48000C00 0x00008A00 0x00004500\t;# MODER\n\tmmw 0x48000C08 0x0000CF00 0x00000000\t;# OSPEEDR\n\tmmw 0x48000C0C 0x00000000 0x0000CF00\t;# PUPDR\n\tmmw 0x48000C20 0xA0AA0000 0x50550000\t;# AFRL\n\t# Port E: PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V\n\tmmw 0x48001000 0x0AA00000 0x05500000\t;# MODER\n\tmmw 0x48001008 0x0FF00000 0x00000000\t;# OSPEEDR\n\tmmw 0x4800100C 0x00000000 0x0FF00000\t;# PUPDR\n\tmmw 0x48001024 0x00AAAA00 0x00555500\t;# AFRH\n\t# Port G: PG06:AF03:V\n\tmmw 0x48001800 0x00002000 0x00001000\t;# MODER\n\tmmw 0x48001808 0x00003000 0x00000000\t;# OSPEEDR\n\tmmw 0x4800180C 0x00000000 0x00003000\t;# PUPDR\n\tmmw 0x48001820 0x03000000 0x0C000000\t;# AFRL\n\n\t# PG12: P2_NCS, PF04: P2_CLK, PF12: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PG01: P2_IO5\n\t# PG00: P2_IO4, PF03: P2_IO3, PF02: P2_IO2, PF01: P2_IO1, PF00: P2_IO0\n\n\t# PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V\n\t# PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V\n\n\t# Port F: PF12:AF05:V, PF04:AF05:V, PF03:AF05:V, PF02:AF05:V, PF01:AF05:V, PF00:AF05:V\n\tmmw 0x48001400 0x020002AA 0x01000155\t;# MODER\n\tmmw 0x48001408 0x030003FF 0x00000000\t;# OSPEEDR\n\tmmw 0x4800140C 0x00000000 0x030003FF\t;# PUPDR\n\tmmw 0x48001420 0x00055555 0x000AAAAA\t;# AFRL\n\tmmw 0x48001424 0x00050000 0x000A0000\t;# AFRH\n\t# Port G: PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PG01:AF05:V, PG00:AF05:V\n\tmmw 0x48001800 0x0228000A 0x01140005\t;# MODER\n\tmmw 0x48001808 0x033C000F 0x00000000\t;# OSPEEDR\n\tmmw 0x4800180C 0x00000000 0x033C000F\t;# PUPDR\n\tmmw 0x48001820 0x00000055 0x000000AA\t;# AFRL\n\tmmw 0x48001824 0x00050550 0x000A0AA0\t;# AFRH\n\n\t# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses\n\tmww 0xA0001130 0x00001000\t\t\t\t;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x3040000B\t\t\t\t;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0\n\tmww 0xA0001008 0x01190100\t\t\t\t;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0\n\tmww 0xA000100C 0x00000001\t\t\t\t;# OCTOSPI_DCR2: PRESCALER=1\n\n\tmww 0xA0001108 0x00000000\t\t\t\t;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0\n\tmww 0xA0001100 0x01003101\t\t\t\t;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1\n\tmww 0xA0001110 0x00000013\t\t\t\t;# OCTOSPI_IR: INSTR=READ4B\n\n\tif { $octo == 1 } {\n\t\tstmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00\t\t\t;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits\n\t\tstmqspi cmd $a 0 0x06\t\t\t\t\t\t\t\t;# Write Enable\n\t\tstmqspi cmd $a 1 0x05\t\t\t\t\t\t\t\t;# Read Status Register\n\t\tstmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02\t\t;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable\n\n\t\t# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses\n\t\tmww 0xA0001000 0x3040000B\t\t\t\t;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1\n\t\tmww 0xA0001108 0x10000006\t\t\t\t;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6\n\t\tmww 0xA0001100 0x2C003C1C\t\t\t\t;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4\n\t\tmww 0xA0001110 0x0000EE11\t\t\t\t;# OCTOSPI_IR: INSTR=OCTA DTR Read\n\n\t\tflash probe $a\t\t\t\t\t\t\t;# reload configuration from CR, TCR, CCR, IR register values\n\n\t\tstmqspi cmd $a 0 0x06\t\t\t\t\t\t\t\t;# Write Enable\n\t\tstmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00\t\t\t;# Read Status Register (note dummy address in 8-line mode)\n\t\tstmqspi cmd $a 0 0x04\t\t\t\t\t\t\t\t;# Write Disable\n\t\tstmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00\t\t\t;# Read Status Register (note dummy address in 8-line mode)\n\t\tstmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00\t\t\t;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits\n\t}\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmmw 0x40022000 0x00000003 0x0000000C\t;# 3 WS for 72 MHz HCLK\n\tsleep 1\n\tmmw 0x40021000 0x00000100 0x00000000\t;# HSI on\n\tmww 0x4002100C 0x01002432\t\t\t\t;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI\n\tmww 0x40021008 0x00008001\t\t\t\t;# always HSI, APB1: /1, APB2: /1\n\tmmw 0x40021000 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40021008 0x00000003 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 24000\n\n\toctospi_init 1\n}\n\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32l4r9i-disco.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is a STM32L4R9I discovery board with a single STM32L4R9AII6 chip.\n# http://www.st.com/en/evaluation-tools/32l4r9idiscovery.html\n\n# This is for using the onboard STLINK\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\n# increase working area to 96KB\nset WORKAREASIZE 0x18000\n\n# enable stmqspi\nset OCTOSPI1 1\nset OCTOSPI2 0\n\nsource [find target/stm32l4x.cfg]\n\n# OCTOSPI initialization\n# octo: 8-line mode\nproc octospi_init { octo } {\n\tglobal a b\n\tmmw 0x4002104C 0x001001FF 0\t\t\t\t;# RCC_AHB2ENR |= OSPIMEN, GPIOAEN-GPIOIEN (enable clocks)\n\tmmw 0x40021050 0x00000300 0\t\t\t\t;# RCC_AHB3ENR |= OSPI2EN, OSPI1EN (enable clocks)\n\tmmw 0x40021058 0x10000000 0\t\t\t\t;# RCC_APB1ENR1 |= PWREN (enable clock)\n\tsleep 1\t\t\t\t\t\t\t\t\t;# Wait for clock startup\n\n\tmmw 0x40007004 0x00000200 0\t\t\t\t;# PWR_CR2 |= IOSV (required for use of GPOIG, cf. RM0432)\n\n\tmww 0x50061C04 0x00000000\t\t\t\t;# OCTOSPIM_P1CR: disable Port 1\n\tmww 0x50061C08 0x03010111\t\t\t\t;# OCTOSPIM_P2CR: assign Port 2 to OCTOSPI1\n\n\t# PG12: P2_NCS, PI06: P2_CLK, PG15: P2_DQS, PG10: P2_IO7, PG09: P2_IO6, PH10: P2_IO5,\n\t# PH09: P2_IO4, PH08: P2_IO3, PI09: P2_IO2, PI10: P2_IO1, PI11: P2_IO0\n\n\t# PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V, PH10:AF05:V, PH09:AF05:V\n\t# PH08:AF05:V, PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V\n\n\t# Port G: PG15:AF05:V, PG12:AF05:V, PG10:AF05:V, PG09:AF05:V\n\tmmw 0x48001800 0x82280000 0x41140000\t;# MODER\n\tmmw 0x48001808 0xC33C0000 0x00000000\t;# OSPEEDR\n\tmmw 0x48001824 0x50050550 0xA00A0AA0\t;# AFRH\n\n\t# Port H: PH10:AF05:V, PH09:AF05:V, PH08:AF05:V\n\tmmw 0x48001C00 0x002A0000 0x00150000\t;# MODER\n\tmmw 0x48001C08 0x003F0000 0x00000000\t;# OSPEEDR\n\tmmw 0x48001C24 0x00000555 0x00000AAA\t;# AFRH\n\n\t# Port I: PI11:AF05:V, PI10:AF05:V, PI09:AF05:V, PI06:AF05:V\n\tmmw 0x48002000 0x00A82000 0x00541000\t;# MODER\n\tmmw 0x48002008 0x00FC3000 0x00000000\t;# OSPEEDR\n\tmmw 0x48002020 0x05000000 0x0A000000\t;# AFRL\n\tmmw 0x48002024 0x00005550 0x0000AAA0\t;# AFRH\n\n\t# OCTOSPI1: memory-mapped 1-line read mode with 4-byte addresses\n\tmww 0xA0001130 0x00001000\t\t\t\t;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full\n\tmww 0xA0001000 0x3040000B\t\t\t\t;# OCTOSPI_CR: FMODE=0x1, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0\n\tmww 0xA0001008 0x01190100\t\t\t\t;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0, DLYBYP=0\n\tmww 0xA000100C 0x00000001\t\t\t\t;# OCTOSPI_DCR2: PRESCALER=1\n\n\tmww 0xA0001108 0x00000000\t\t\t\t;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0\n\tmww 0xA0001100 0x01003101\t\t\t\t;# OCTOSPI_CCR: DMODE=0x1, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x1, ISIZE=0x0, IMODE=0x1\n\tmww 0xA0001110 0x00000013\t\t\t\t;# OCTOSPI_IR: INSTR=READ4B\n\n\tif { $octo == 1 } {\n\t\tstmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00\t\t\t;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits\n\t\tstmqspi cmd $a 0 0x06\t\t\t\t\t\t\t\t;# Write Enable\n\t\tstmqspi cmd $a 1 0x05\t\t\t\t\t\t\t\t;# Read Status Register\n\t\tstmqspi cmd $a 0 0x72 0x00 0x00 0x00 0x00 0x02\t\t;# Write Conf. Reg. 2, addr 0x00000000: DTR OPI enable\n\n\t\t# OCTOSPI1: memory-mapped 8-line read mode with 4-byte addresses\n\t\tmww 0xA0001000 0x3040000B\t\t\t\t;# OCTOSPI_CR: FMODE=0x3, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=1, EN=1\n\t\tmww 0xA0001108 0x10000006\t\t\t\t;# OCTOSPI_TCR: SSHIFT=0, DHQC=1, DCYC=0x6\n\t\tmww 0xA0001100 0x2C003C1C\t\t\t\t;# OCTOSPI_CCR: DTR, DMODE=0x4, ABMODE=0x0, ADSIZE=0x3, ADMODE=0x4, ISIZE=0x1, IMODE=0x4\n\t\tmww 0xA0001110 0x0000EE11\t\t\t\t;# OCTOSPI_IR: INSTR=OCTA DTR Read\n\n\t\tflash probe $a\t\t\t\t\t\t\t;# reload configuration from CR, TCR, CCR, IR register values\n\n\t\tstmqspi cmd $a 0 0x06\t\t\t\t\t\t\t\t;# Write Enable\n\t\tstmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00\t\t\t;# Read Status Register (note dummy address in 8-line mode)\n\t\tstmqspi cmd $a 0 0x04\t\t\t\t\t\t\t\t;# Write Disable\n\t\tstmqspi cmd $a 1 0x05 0x00 0x00 0x00 0x00\t\t\t;# Read Status Register (note dummy address in 8-line mode)\n\t\tstmqspi cmd $a 1 0x71 0x00 0x00 0x00 0x00\t\t\t;# Read Conf. Reg. 2, addr 0x00000000: DOPI, SOPI bits\n\t}\n}\n\n$_TARGETNAME configure -event reset-init {\n\tmmw 0x40022000 0x00000003 0x0000000C\t;# 3 WS for 72 MHz HCLK\n\tsleep 1\n\tmmw 0x40021000 0x00000100 0x00000000\t;# HSI on\n\tmww 0x4002100C 0x01002432\t\t\t\t;# RCC_PLLCFGR 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI\n\tmww 0x40021008 0x00008001\t\t\t\t;# always HSI, APB1: /1, APB2: /1\n\tmmw 0x40021000 0x01000000 0x00000000\t;# PLL on\n\tsleep 1\n\tmmw 0x40021008 0x00000003 0x00000000\t;# switch to PLL\n\tsleep 1\n\n\tadapter speed 4000\n\n\toctospi_init 1\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32ldiscovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32L discovery board with a single STM32L152RBT6 chip.\n# http://www.st.com/internet/evalboard/product/250990.jsp\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset WORKAREASIZE 0x4000\nsource [find target/stm32l1.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32mp13x_dk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# board MB1635x\n# http://www.st.com/en/evaluation-tools/stm32mp135f-dk.html\n\nsource [find interface/stlink-dap.cfg]\n\ntransport select dapdirect_swd\n\nsource [find target/stm32mp13x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32mp15x_dk2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# board MB1272B\n# http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html\n# http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html\n\nsource [find interface/stlink-dap.cfg]\n\ntransport select dapdirect_swd\n\nsource [find target/stm32mp15x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/stm32vldiscovery.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is an STM32VL discovery board with a single STM32F100RB chip.\n# http://www.st.com/internet/evalboard/product/250863.jsp\n\nsource [find interface/stlink.cfg]\n\ntransport select hla_swd\n\nset WORKAREASIZE 0x2000\nsource [find target/stm32f1x.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/str910-eval.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# str910-eval eval board\n#\n# Need reset scripts\nreset_config trst_and_srst\n\n# FIXME use some standard target config, maybe create one from this\n#\n#\tsource [find target/...cfg]\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME str912\n}\n\nif { [info exists ENDIAN] } {\n   set  _ENDIAN $ENDIAN\n} else {\n   set  _ENDIAN little\n}\n\nif { [info exists FLASHTAPID] } {\n   set _FLASHTAPID $FLASHTAPID\n} else {\n   set _FLASHTAPID 0x04570041\n}\njtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID\n\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x25966041\n}\njtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nif { [info exists BSTAPID] } {\n   set _BSTAPID $BSTAPID\n} else {\n   set _BSTAPID 0x1457f041\n}\njtag newtap $_CHIPNAME bs    -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME\n$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1\n\n$_TARGETNAME configure -event reset-init {\n\t# We can increase speed now that we know the target is halted.\n\t#jtag_rclk 3000\n\n\t# -- Enable 96K RAM\n\t# PFQBC enabled / DTCM & AHB wait-states disabled\n\tmww 0x5C002034 0x0191\n\n\tstr9x flash_config 0 4 2 0 0x80000\n\tflash protect 0 0 7 off\n}\n\n#flash bank str9x <base> <size> 0 0 <target#> <variant>\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/telo.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/c100.cfg]\n# basic register definition for C100\nsource [find target/c100regs.tcl]\n# board-config info\nsource [find target/c100config.tcl]\n# C100 helper functions\nsource [find target/c100helper.tcl]\n\n\n# Telo board & C100 support trst and srst\n# make the reset asserted to\n# allow RC circuit to discharge for: [ms]\nadapter srst pulse_width 100\njtag_ntrst_assert_width 100\n# don't talk to JTAG after reset for: [ms]\nadapter srst delay 100\njtag_ntrst_delay 100\nreset_config trst_and_srst separate\n\n\n\n\n# issue telnet: reset init\n# issue gdb: monitor reset init\n$_TARGETNAME configure -event reset-init {\n\tadapter speed 100\n\t# this will setup Telo board\n\tsetupTelo\n\t#turn up the JTAG speed\n\tadapter speed 3000\n\techo \"JTAG speek now 3MHz\"\n\techo \"type helpC100 to get help on C100\"\n}\n\n$_TARGETNAME configure -event reset-deassert-post {\n\t# Force target into ARM state.\n#\tsoft_reset_halt ;# not implemented on ARM11\n\techo \"Detected SRSRT asserted on C100.CPU\"\n\n}\n\n$_TARGETNAME configure -event reset-assert-post {\n  echo \"Assering reset\"\n  #sleep 10\n}\n\nproc power_restore {} { echo \"Sensed power restore. No action.\" }\nproc srst_deasserted {} { echo \"Sensed nSRST deasserted. No action.\" }\n\n\n# boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus\n# it's really 16MB but the upper 8mb is controller via gpio\n# openocd does not support 'complex reads/writes' to NOR\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME\n\n# writing data to memory does not work without this\narm11 memwrite burst disable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_am335xevm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI AM335x Evaluation Module\n#\n# For more information please see http://www.ti.com/tool/tmdxevm3358\n#\njtag_rclk 6000\n\nsource [find target/am335x.cfg]\n\nreset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_am437x_idk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Texas Instruments AM437x Industrial Development Kit\n\n# The JTAG interface is built directly on the board.\nsource [find interface/ftdi/xds100v2.cfg]\n\ntransport select jtag\nadapter speed 30000\n\nsource [find target/am437x.cfg]\n$_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 }\n\nreset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_am43xx_evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Works on both AM437x GP EVM and AM438x ePOS EVM\ntransport select jtag\nadapter speed 16000\n\nsource [find target/am437x.cfg]\n\nreset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_am625_swd_native.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments am625\n# Link: https://www.ti.com/product/AM625\n#\n# This configuration file is used as a self hosted debug configuration that\n# works on every AM625 platform based on firewall configuration permitted\n# in the system.\n#\n# In this system openOCD runs on one of the CPUs inside AM625 and provides\n# network ports that can then be used to debug the microcontrollers on the\n# SoC - either self hosted IDE OR remotely.\n\n# We are using dmem, which uses dapdirect_swd transport\nadapter driver dmem\n\nif { ![info exists SOC] } {\n\tset SOC am625\n}\n\nsource [find target/ti_k3.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_am625evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2021-2022 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments am625 EVM/SK\n# Link: https://www.ti.com/lit/zip/sprr448\n#\n\n# AM625 EVM has an xds110 onboard.\nsource [find interface/xds110.cfg]\n\ntransport select jtag\n\n# default JTAG configuration has only SRST and no TRST\nreset_config srst_only srst_push_pull\n\n# delay after SRST goes inactive\nadapter srst delay 20\n\nif { ![info exists SOC] } {\n\tset SOC am625\n}\n\nsource [find target/ti_k3.cfg]\n\nadapter speed 2500\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_am62a7evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments am62a7 EVM/SK\n# Link: https://www.ti.com/tool/SK-AM62A-LP\n#\n\n# AM62a7 EVM/SK has an xds110 onboard.\nsource [find interface/xds110.cfg]\n\ntransport select jtag\n\n# default JTAG configuration has only SRST and no TRST\nreset_config srst_only srst_push_pull\n\n# delay after SRST goes inactive\nadapter srst delay 20\n\nif { ![info exists SOC] } {\n\tset SOC am62a7\n}\n\nsource [find target/ti_k3.cfg]\n\nadapter speed 2500\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_am642evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments AM642 EVM\n#\n\n# AM642 EVM has an xds110 onboard.\nsource [find interface/xds110.cfg]\n\ntransport select jtag\n\n# default JTAG configuration has only SRST and no TRST\nreset_config srst_only srst_push_pull\n\n# delay after SRST goes inactive\nadapter srst delay 20\n\nif { ![info exists SOC] } {\n\tset SOC am642\n}\n\nsource [find target/ti_k3.cfg]\n\nadapter speed 250\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_am654evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments AM654 EVM/IDK Base Board\n#\n\n# AM654 EVM has an xds110 onboard.\nsource [find interface/xds110.cfg]\n\ntransport select jtag\n\n# default JTAG configuration has only SRST and no TRST\nreset_config srst_only srst_push_pull\n\n# delay after SRST goes inactive\nadapter srst delay 70\n\nif { ![info exists SOC] } {\n\tset SOC am654\n}\n\nsource [find target/ti_k3.cfg]\n\nadapter speed 2500\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_beagleboard.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# OMAP3 BeagleBoard\n#  http://beagleboard.org\n\n# Fall back to 6MHz if RTCK is not supported\njtag_rclk 6000\n\nsource [find target/omap3530.cfg]\n\n# TI-14 JTAG connector\nreset_config trst_only\n\n# Later run:  omap3_dbginit\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_beagleboard_xm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# BeagleBoard xM (DM37x)\n#  http://beagleboard.org\n\nset CHIPTYPE \"dm37x\"\nsource [find target/amdm37x.cfg]\n\n# The TI-14 JTAG connector does not have srst.  CPU reset is handled in\n# hardware.\nreset_config trst_only\n\n# \"amdm37x_dbginit dm37x.cpu\" needs to be run after init.\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_beaglebone-base.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# AM335x Beaglebone family base configuration\n#  http://beagleboard.org/bone\n\nsource [find target/am335x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_beaglebone.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# AM335x Beaglebone\n#  http://beagleboard.org/bone\n\n# The JTAG interface is built directly on the board.\nsource [find interface/ftdi/xds100v2.cfg]\n\nadapter speed 16000\n\nreset_config trst_and_srst\n\nsource [find board/ti_beaglebone-base.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_beaglebone_black.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# AM335x Beaglebone Black\n#  http://beagleboard.org/bone\n\nadapter speed 1000\n\nreset_config trst_and_srst\n\nsource [find board/ti_beaglebone-base.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_blaze.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\njtag_rclk 6000\n\nsource [find target/omap4430.cfg]\n\nreset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_cc13x0_launchpad.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI CC13x0 LaunchPad Evaluation Kit\n#\nsource [find interface/xds110.cfg]\ntransport select jtag\nadapter speed 5500\nsource [find target/ti_cc13x0.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_cc13x2_launchpad.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI CC13x2 LaunchPad Evaluation Kit\n#\nsource [find interface/xds110.cfg]\nadapter speed 5500\ntransport select jtag\nsource [find target/ti_cc13x2.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_cc26x0_launchpad.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI CC26x0 LaunchPad Evaluation Kit\n#\nsource [find interface/xds110.cfg]\nadapter speed 5500\ntransport select jtag\nsource [find target/ti_cc26x0.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_cc26x2_launchpad.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI CC26x2 LaunchPad Evaluation Kit\n#\nsource [find interface/xds110.cfg]\nadapter speed 5500\ntransport select jtag\nsource [find target/ti_cc26x2.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_cc3200_launchxl.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI SimpleLink Wi-Fi CC3200 LaunchPad\n#\n# http://www.ti.com/tool/cc3200-launchxl\n#\n\nsource [find interface/ftdi/ti-icdi.cfg]\n\nif { [info exists TRANSPORT] } {\n   transport select $TRANSPORT\n} else {\n   transport select jtag\n}\n\nadapter speed 2500\n\nset WORKAREASIZE 0x40000\nsource [find target/ti_cc32xx.cfg]\n\nreset_config srst_only\nadapter srst delay 1100\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_cc3220sf_launchpad.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit\n#\nsource [find interface/xds110.cfg]\nadapter speed 8500\ntransport select swd\nsource [find target/ti_cc3220sf.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_cc32xx_launchpad.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI CC32xx-LaunchXL LaunchPad Evaluation Kit\n#\nsource [find interface/xds110.cfg]\nadapter speed 8500\ntransport select swd\nsource [find target/ti_cc32xx.cfg]\n\nreset_config srst_only\nadapter srst delay 1100\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_dk-tm4c129.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI Tiva C DK-TM4C129X Connected Development Kit\n#\n# http://www.ti.com/tool/dk-tm4c129x\n#\n\nsource [find interface/ti-icdi.cfg]\n\ntransport select hla_jtag\n\nset WORKAREASIZE 0x8000\nset CHIPNAME tm4c129xnczad\n\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_ek-tm4c123gxl.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit\n#\n# http://www.ti.com/tool/ek-tm4c123gxl\n#\n\nsource [find interface/ti-icdi.cfg]\n\ntransport select hla_jtag\n\nset WORKAREASIZE 0x8000\nset CHIPNAME tm4c123gh6pm\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_ek-tm4c1294xl.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI Tiva C Series ek-tm4c1294xl Launchpad Evaluation Kit\n#\n# http://www.ti.com/tool/ek-tm4c1294xl\n#\n\nsource [find interface/ti-icdi.cfg]\n\ntransport select hla_jtag\n\nset WORKAREASIZE 0x8000\nset CHIPNAME tm4c1294ncpdt\n\nsource [find target/stellaris.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_j7200evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments J7200 EVM\n#\n\n# J7200 EVM has an xds110 onboard.\nsource [find interface/xds110.cfg]\n\ntransport select jtag\n\n# default JTAG configuration has only SRST and no TRST\nreset_config srst_only srst_push_pull\n\n# delay after SRST goes inactive\nadapter srst delay 20\n\nif { ![info exists SOC] } {\n\tset SOC j7200\n}\n\nsource [find target/ti_k3.cfg]\n\nadapter speed 2500\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_j721e_swd_native.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2022-2023 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments TDA4VM/J721E\n# Link: https://www.ti.com/product/TDA4VM\n#\n# This configuration file is used as a self hosted debug configuration that\n# works on every TDA4VM platform based on firewall configuration permitted\n# in the system.\n#\n# In this system openOCD runs on one of the CPUs inside TDA4VM and provides\n# network ports that can then be used to debug the microcontrollers on the\n# SoC - either self hosted IDE OR remotely.\n\n# We are using dmem, which uses dapdirect_swd transport\nadapter driver dmem\n\nif { ![info exists SOC] } {\n        set SOC j721e\n}\nsource [find target/ti_k3.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_j721evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments J721E EVM\n#\n\n# J721E EVM has an xds110 onboard.\nsource [find interface/xds110.cfg]\n\ntransport select jtag\n\n# default JTAG configuration has only SRST and no TRST\nreset_config srst_only srst_push_pull\n\n# delay after SRST goes inactive\nadapter srst delay 20\n\nif { ![info exists SOC] } {\n\tset SOC j721e\n}\n\nsource [find target/ti_k3.cfg]\n\nadapter speed 2500\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_j721s2evm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments J721s2 EVM\n# Link(SoM): https://www.ti.com/lit/zip/sprr439\n#\n\n# J721s2 EVM has an xds110 onboard.\nsource [find interface/xds110.cfg]\n\ntransport select jtag\n\n# default JTAG configuration has only SRST and no TRST\nreset_config srst_only srst_push_pull\n\n# delay after SRST goes inactive\nadapter srst delay 20\n\nif { ![info exists SOC] } {\n\tset SOC j721s2\n}\n\nsource [find target/ti_k3.cfg]\n\nadapter speed 2500\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_msp432_launchpad.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI MSP432 LaunchPad Evaluation Kit\n#\nsource [find interface/xds110.cfg]\nadapter speed 10000\ntransport select swd\nsource [find target/ti_msp432.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_pandaboard.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\njtag_rclk 6000\n\nsource [find target/omap4430.cfg]\n\nreset_config trst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_pandaboard_es.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\njtag_rclk 6000\n\nsource [find target/omap4460.cfg]\n\nreset_config trst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_tmdx570ls20susb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# TMS570 Microcontroller USB Kit\n# http://www.ti.com/tool/TMDX570LS20SUSB\n\n# Board uses a FT2232H to emulate an XDS100v2 JTAG debugger\n# TODO: board also supports an SCI UART on the 2232's B Bus\nsource [find interface/ftdi/xds100v2.cfg]\n\n# Processor is TMS570LS20216\nsource [find target/ti_tms570ls20xxx.cfg]\n\nreset_config trst_only\n\n# xds100v2 config says add this to the end\ninit\nftdi set_signal PWR_RST 1\njtag arp_init\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/ti_tmdx570ls31usb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nadapter speed 1500\n\nsource [find interface/ftdi/xds100v2.cfg]\nsource [find target/ti_tms570.cfg]\n\nreset_config trst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/tocoding_poplar.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# board configuration for Tocoding Poplar\n#\n\n# board does not feature anything but JTAG\ntransport select jtag\n\nadapter speed 10000\n\n# SRST-only reset configuration\nreset_config srst_only srst_push_pull\n\nsource [find target/hi3798.cfg]\n\n# make sure the default target is the boot core\ntargets ${_TARGETNAME}0\n\nproc core_up { args } {\n\tglobal _TARGETNAME\n\n\t# examine remaining cores\n\tforeach _core $args {\n\t\t${_TARGETNAME}$_core arp_examine\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/topas910.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Toshiba TOPAS910 -- TMPA910 Starterkit\n#\n######################################\n\n# We add to the minimal configuration.\nsource [find target/tmpa910.cfg]\n\n######################\n# Target configuration\n######################\n\n#$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { topas910_init }\n\nproc topas910_init { } {\n# Init PLL\n# my settings\n\tmww 0xf005000c 0x00000007\n\tmww 0xf0050010 0x00000065\n\tmww 0xf005000c 0x000000a7\n\tsleep 10\n\tmdw 0xf0050008\n\tmww 0xf0050008 0x00000002\n\tmww 0xf0050004 0x00000000\n# NEW: set CLKCR5\n\tmww 0xf0050054 0x00000040\n#\n\tsleep 10\n# Init SDRAM\n#  _PMCDRV          = 0x00000071;\n#  //\n#  // Initialize SDRAM timing parameter\n#  //\n#  _DMC_CAS_LATENCY = 0x00000006;\n#  _DMC_T_DQSS      = 0x00000000;\n#  _DMC_T_MRD       = 0x00000002;\n#  _DMC_T_RAS       = 0x00000007;\n#\n#  _DMC_T_RC        = 0x0000000A;\n#  _DMC_T_RCD       = 0x00000013;\n#\n#  _DMC_T_RFC       = 0x0000010A;\n#\n#  _DMC_T_RP        = 0x00000013;\n#  _DMC_T_RRD       = 0x00000002;\n#  _DMC_T_WR        = 0x00000002;\n#  _DMC_T_WTR       = 0x00000001;\n#  _DMC_T_XP        = 0x0000000A;\n#  _DMC_T_XSR       = 0x0000000B;\n#  _DMC_T_ESR       = 0x00000014;\n#\n#  //\n#  // Configure SDRAM type parameter\n#  _DMC_MEMORY_CFG  = 0x00008011;\n#  _DMC_USER_CONFIG = 0x00000011;\n#  // 32 bit memory interface\n#\n#\n#  _DMC_REFRESH_PRD = 0x00000A60;\n#  _DMC_CHIP_0_CFG  = 0x000140FC;\n#\n#  _DMC_DIRECT_CMD  = 0x000C0000;\n#  _DMC_DIRECT_CMD  = 0x00000000;\n#\n#  _DMC_DIRECT_CMD  = 0x00040000;\n#  _DMC_DIRECT_CMD  = 0x00040000;\n#  _DMC_DIRECT_CMD  = 0x00080031;\n#  //\n#  // Finally start SDRAM\n#  //\n#  _DMC_MEMC_CMD    = MEMC_CMD_GO;\n#  */\n\n\tmww 0xf0020260 0x00000071\n\tmww 0xf4300014 0x00000006\n\tmww 0xf4300018 0x00000000\n\tmww 0xf430001C 0x00000002\n\tmww 0xf4300020 0x00000007\n\tmww 0xf4300024 0x0000000A\n\tmww 0xf4300028 0x00000013\n\tmww 0xf430002C 0x0000010A\n\tmww 0xf4300030 0x00000013\n\tmww 0xf4300034 0x00000002\n\tmww 0xf4300038 0x00000002\n\tmww 0xf430003C 0x00000001\n\tmww 0xf4300040 0x0000000A\n\tmww 0xf4300044 0x0000000B\n\tmww 0xf4300048 0x00000014\n\tmww 0xf430000C 0x00008011\n\tmww 0xf4300304 0x00000011\n\tmww 0xf4300010 0x00000A60\n\tmww 0xf4300200 0x000140FC\n\tmww 0xf4300008 0x000C0000\n\tmww 0xf4300008 0x00000000\n\tmww 0xf4300008 0x00040000\n\tmww 0xf4300008 0x00040000\n\tmww 0xf4300008 0x00080031\n\tmww 0xf4300004 0x00000000\n\n\tsleep 10\n#\tadapter speed NNNN\n\n# remap off in case of IROM boot\n\tmww 0xf0000004 0x00000001\n\n}\n\n# comment the following out if usinf J-Link, it soes not support DCC\narm7_9 dcc_downloads enable       ;# Enable faster DCC downloads\n\n\n#####################\n# Flash configuration\n#####################\n\n#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/topasa900.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Thanks to Pieter Conradie for this script!\n# Target:    Toshiba TOPAS900 -- TMPA900 Starterkit\n######################################\n\n# We add to the minimal configuration.\nsource [find target/tmpa900.cfg]\n\n######################\n# Target configuration\n######################\n\n#$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { topasa900_init }\n\nproc topasa900_init { } {\n# Init PLL\n# my settings\n\tmww 0xf005000c 0x00000007\n\tmww 0xf0050010 0x00000065\n\tmww 0xf005000c 0x000000a7\n\tsleep 10\n\tmdw 0xf0050008\n\tmww 0xf0050008 0x00000002\n\tmww 0xf0050004 0x00000000\n# NEW: set CLKCR5\n\tmww 0xf0050054 0x00000040\n#\n# bplan settings\n#\tmww 0xf0050004 0x00000000\n#\tmww 0xf005000c 0x000000a7\n#\tsleep 10\n#\tmdw 0xf0050008\n#\tmww 0xf0050008 0x00000002\n#\tmww 0xf0050010 0x00000065\n#\tmww 0xf0050054 0x00000040\n\tsleep 10\n# Init SDRAM\n#  _PMCDRV          = 0x00000071;\n#  //\n#  // Initialize SDRAM timing parameter\n#  //\n#  _DMC_CAS_LATENCY = 0x00000006;\n#  _DMC_T_DQSS      = 0x00000000;\n#  _DMC_T_MRD       = 0x00000002;\n#  _DMC_T_RAS       = 0x00000007;\n#\n#  _DMC_T_RC        = 0x0000000A;\n#  _DMC_T_RCD       = 0x00000013;\n#\n#  _DMC_T_RFC       = 0x0000010A;\n#\n#  _DMC_T_RP        = 0x00000013;\n#  _DMC_T_RRD       = 0x00000002;\n#  _DMC_T_WR        = 0x00000002;\n#  _DMC_T_WTR       = 0x00000001;\n#  _DMC_T_XP        = 0x0000000A;\n#  _DMC_T_XSR       = 0x0000000B;\n#  _DMC_T_ESR       = 0x00000014;\n#\n#  //\n#  // Configure SDRAM type parameter\n#  _DMC_MEMORY_CFG  = 0x00008011;\n#  _DMC_USER_CONFIG = 0x00000011;   // 32 bit memory interface\n#\n#\n#  _DMC_REFRESH_PRD = 0x00000A60;\n#  _DMC_CHIP_0_CFG  = 0x000140FC;\n#\n#  _DMC_DIRECT_CMD  = 0x000C0000;\n#  _DMC_DIRECT_CMD  = 0x00000000;\n#\n#  _DMC_DIRECT_CMD  = 0x00040000;\n#  _DMC_DIRECT_CMD  = 0x00040000;\n#  _DMC_DIRECT_CMD  = 0x00080031;\n#  //\n#  // Finally start SDRAM\n#  //\n#  _DMC_MEMC_CMD    = MEMC_CMD_GO;\n#  */\n\n\tmww 0xf0020260 0x00000071\n\tmww 0xf4300014 0x00000006\n\tmww 0xf4300018 0x00000000\n\tmww 0xf430001C 0x00000002\n\tmww 0xf4300020 0x00000007\n\tmww 0xf4300024 0x0000000A\n\tmww 0xf4300028 0x00000013\n\tmww 0xf430002C 0x0000010A\n\tmww 0xf4300030 0x00000013\n\tmww 0xf4300034 0x00000002\n\tmww 0xf4300038 0x00000002\n\tmww 0xf430003C 0x00000001\n\tmww 0xf4300040 0x0000000A\n\tmww 0xf4300044 0x0000000B\n\tmww 0xf4300048 0x00000014\n\tmww 0xf430000C 0x00008011\n\tmww 0xf4300304 0x00000011\n\tmww 0xf4300010 0x00000A60\n\tmww 0xf4300200 0x000140FC\n\tmww 0xf4300008 0x000C0000\n\tmww 0xf4300008 0x00000000\n\tmww 0xf4300008 0x00040000\n\tmww 0xf4300008 0x00040000\n\tmww 0xf4300008 0x00080031\n\tmww 0xf4300004 0x00000000\n\n\tsleep 10\n#\tadapter speed NNNN\n\n# remap off in case of IROM boot\n\tmww 0xf0000004 0x00000001\n\n}\n\n# comment the following out if usinf J-Link, it soes not support DCC\narm7_9 dcc_downloads enable       ;# Enable faster DCC downloads\n\n\n#####################\n# Flash configuration\n#####################\n\n#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/tp-link_tl-mr3020.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/atheros_ar9331.cfg]\n\n$_TARGETNAME configure -event reset-init {\n\tar9331_25mhz_pll_init\n\tsleep 1\n\tar9331_ddr1_init\n}\n\nset ram_boot_address 0xa0000000\n$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000\n\nflash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/tp-link_wdr4300.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/atheros_ar9344.cfg]\n\nreset_config trst_only separate\n\nproc ar9344_40mhz_pll_init {} {\n\t# QCA_PLL_SRIF_CPU_DPLL2_REG\n\tmww 0xb81161C4 0x13210f00\n\t# QCA_PLL_SRIF_CPU_DPLL3_REG\n\tmww 0xb81161C8 0x03000000\n\t# QCA_PLL_SRIF_DDR_DPLL2_REG\n\tmww 0xb8116244 0x13210f00\n\t# QCA_PLL_SRIF_DDR_DPLL3_REG\n\tmww 0xb8116248 0x03000000\n\t# QCA_PLL_SRIF_BB_DPLL_BASE_REG\n\tmww 0xb8116188 0x03000000\n\n\t# QCA_PLL_CPU_DDR_CLK_CTRL_REG\n\tmww 0xb8050008 0x0130001C\n\tmww 0xb8050008 0x0130001C\n\tmww 0xb8050008 0x0130001C\n\n\t# QCA_PLL_CPU_PLL_CFG_REG\n\tmww 0xb8050000 0x40021380\n\t# QCA_PLL_DDR_PLL_CFG_REG\n\tmww 0xb8050004 0x40815800\n\t# QCA_PLL_CPU_DDR_CLK_CTRL_REG\n\tmww 0xb8050008 0x0130801C\n\n\t# QCA_PLL_SRIF_CPU_DPLL2_REG\n\tmww 0xb81161C4 0x10810F00\n\tmww 0xb81161C0 0x41C00000\n\t# QCA_PLL_SRIF_CPU_DPLL2_REG\n\tmww 0xb81161C4 0xD0810F00\n\t# QCA_PLL_SRIF_CPU_DPLL3_REG\n\tmww 0xb81161C8 0x03000000\n\t# QCA_PLL_SRIF_CPU_DPLL2_REG\n\tmww 0xb81161C4 0xD0800F00\n\n\t# QCA_PLL_SRIF_CPU_DPLL3_REG\n\tmww 0xb81161C8 0x03000000\n\t# QCA_PLL_SRIF_CPU_DPLL3_REG\n\tmww 0xb81161C8 0x43000000\n\t# QCA_PLL_SRIF_CPU_DPLL3_REG\n\tmww 0xb81161C8 0x030003E8\n\n\t# QCA_PLL_SRIF_DDR_DPLL2_REG\n\tmww 0xb8116244 0x10810F00\n\tmww 0xb8116240 0x41680000\n\t# QCA_PLL_SRIF_DDR_DPLL2_REG\n\tmww 0xb8116244 0xD0810F00\n\t# QCA_PLL_SRIF_DDR_DPLL3_REG\n\tmww 0xb8116248 0x03000000\n\t# QCA_PLL_SRIF_DDR_DPLL2_REG\n\tmww 0xb8116244 0xD0800F00\n\n\t# QCA_PLL_SRIF_DDR_DPLL3_REG\n\tmww 0xb8116248 0x03000000\n\t# QCA_PLL_SRIF_DDR_DPLL3_REG\n\tmww 0xb8116248 0x43000000\n\t# QCA_PLL_SRIF_DDR_DPLL3_REG\n\tmww 0xb8116248 0x03000718\n\n\t# QCA_PLL_CPU_DDR_CLK_CTRL_REG\n\tmww 0xb8050008 0x01308018\n\tmww 0xb8050008 0x01308010\n\tmww 0xb8050008 0x01308000\n\n\t# QCA_PLL_DDR_PLL_DITHER_REG\n\tmww 0xb8050044 0x78180200\n\t# QCA_PLL_CPU_PLL_DITHER_REG\n\tmww 0xb8050048 0x41C00000\n\n}\n\nproc ar9344_ddr_init {} {\n\t# QCA_DDR_CTRL_CFG_REG\n\tmww 0xb8000108 0x40\n\t# QCA_DDR_RD_DATA_THIS_CYCLE_REG\n\tmww 0xb8000018 0xFF\n\t# QCA_DDR_BURST_REG\n\tmww 0xb80000C4 0x74444444\n\t# QCA_DDR_BURST2_REG\n\tmww 0xb80000C8 0x0222\n\t# QCA_AHB_MASTER_TOUT_MAX_REG\n\tmww 0xb80000CC 0xFFFFF\n\n\t# QCA_DDR_CFG_REG\n\tmww 0xb8000000 0xC7D48CD0\n\t# QCA_DDR_CFG2_REG\n\tmww 0xb8000004 0x9DD0E6A8\n\n\t# QCA_DDR_DDR2_CFG_REG\n\tmww 0xb80000B8 0x0E59\n\t# QCA_DDR_CFG2_REG\n\tmww 0xb8000004 0x9DD0E6A8\n\n\t# QCA_DDR_CTRL_REG\n\tmww 0xb8000010 0x08\n\tmww 0xb8000010 0x08\n\tmww 0xb8000010 0x10\n\tmww 0xb8000010 0x20\n\t# QCA_DDR_EMR_REG\n\tmww 0xb800000C 0x02\n\t# QCA_DDR_CTRL_REG\n\tmww 0xb8000010 0x02\n\n\t# QCA_DDR_MR_REG\n\tmww 0xb8000008 0x0133\n\t# QCA_DDR_CTRL_REG\n\tmww 0xb8000010 0x1\n\tmww 0xb8000010 0x8\n\tmww 0xb8000010 0x8\n\tmww 0xb8000010 0x4\n\tmww 0xb8000010 0x4\n\n\t# QCA_DDR_MR_REG\n\tmww 0xb8000008 0x33\n\t# QCA_DDR_CTRL_REG\n\tmww 0xb8000010 0x1\n\n\t# QCA_DDR_EMR_REG\n\tmww 0xb800000C 0x0382\n\t# QCA_DDR_CTRL_REG\n\tmww 0xb8000010 0x2\n\t# QCA_DDR_EMR_REG\n\tmww 0xb800000C 0x0402\n\t# QCA_DDR_CTRL_REG\n\tmww 0xb8000010 0x2\n\n\t# QCA_DDR_REFRESH_REG\n\tmww 0xb8000014 0x4270\n\n\t# QCA_DDR_TAP_CTRL_0_REG\n\tmww 0xb800001C 0x0e\n\t# QCA_DDR_TAP_CTRL_1_REG\n\tmww 0xb8000020 0x0e\n\t# QCA_DDR_TAP_CTRL_2_REG\n\tmww 0xb8000024 0x0e\n\t# QCA_DDR_TAP_CTRL_3_REG\n\tmww 0xb8000028 0x0e\n}\n\n$_TARGETNAME configure -event reset-init {\n\n\t# mww 0xb806001c 0x1000000\n\tar9344_40mhz_pll_init\n\tsleep 100\n\n\t# flash remap\n\t# SPI_CONTROL_ADDR\n\tmww 0xbF000004 0x43\n\n\tar9344_ddr_init\n\tsleep 100\n}\n\nset ram_boot_address 0xa0000000\n$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000\n\nflash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/trion_t20_bga256.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Trion® T20 BGA256 Development Kit\n# https://www.efinixinc.com/docs/trion20-devkit-ug-v1.5.pdf\n#\n# works after power cycle or pushing sw1.\n# it is because we cannot control CDONE which is connected to ftdi channel 0\n# note from an006: For JTAG programming, T4, T8, T13, and T20 FPGAs use the\n# CRESET_N and SS_N pins in addition to the standard JTAG pins.\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n\nftdi channel 1\nftdi layout_init 0x0008 0x008b\nreset_config none\ntransport select jtag\nadapter speed 6000\n\nsource [find fpga/efinix_trion.cfg]\n\n#openocd -f board/trion_t20_bga256.cfg -c \"init\" -c \"pld load 0 outflow/trion_blinker.bit\"\n#ipdbg -start -tap trion.tap -hub 0x8 -port 5555 -tool 0\n\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/twr-k60f120m.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale TWRK60F120M development board\n#\n\nsource [find target/k60.cfg]\n\n$_TARGETNAME configure -event reset-init {\n\tputs \"-event reset-init occurred\"\n}\n\n#\n# Definitions for the additional 'program flash' banks\n# (instructions and/or data)\n#\nflash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME\nflash bank pflash.2 kinetis 0x00080000 0x40000 0 4 $_TARGETNAME\nflash bank pflash.3 kinetis 0x000c0000 0x40000 0 4 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/twr-k60n512.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale TWRK60N512 development board\n#\n\nsource [find target/k60.cfg]\n\n$_TARGETNAME configure -event reset-init {\n\tputs \"-event reset-init occurred\"\n}\n\n#\n# Definitions for the additional 'program flash' bank\n# (instructions and/or data)\n#\nflash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/twr-vf65gs10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Board configuration file for the Freescale VF65GS10 tower board\n#\n# Board has a 20 pin Cortex+ETM debug connector with only nSRST available\nreset_config srst_only\n\n# This configuration file only deals with the hardware JTAG.\n# There is has also an embedded Kinetis K20 with OpenSDA\n# where a CMSIS-DAP application can be installed.\n\n# Source generic VF6xx target configuration\nsource [find target/vybrid_vf6xx.cfg]\n\n# basic DDR memory init, setting up pad configuration\n# for DDR first then configuring the DDRMC for the\n# board\nproc ddr_init { } {\n\t# iomux ddr\n\tmww phys 0x40048220 0x00000180\n\tmww phys 0x40048224 0x00000180\n\tmww phys 0x40048228 0x00000180\n\tmww phys 0x4004822c 0x00000180\n\tmww phys 0x40048230 0x00000180\n\tmww phys 0x40048234 0x00000180\n\tmww phys 0x40048238 0x00000180\n\tmww phys 0x4004823c 0x00000180\n\tmww phys 0x40048240 0x00000180\n\tmww phys 0x40048244 0x00000180\n\tmww phys 0x40048248 0x00000180\n\tmww phys 0x4004824c 0x00000180\n\tmww phys 0x40048250 0x00000180\n\tmww phys 0x40048254 0x00000180\n\tmww phys 0x40048258 0x00000180\n\tmww phys 0x4004825c 0x00000180\n\tmww phys 0x40048260 0x00000180\n\tmww phys 0x40048264 0x00000180\n\tmww phys 0x40048268 0x00000180\n\tmww phys 0x4004826c 0x00000180\n\tmww phys 0x40048270 0x00000180\n\tmww phys 0x40048274 0x00000180\n\tmww phys 0x40048278 0x00000180\n\tmww phys 0x4004827c 0x00010180\n\tmww phys 0x40048280 0x00010180\n\tmww phys 0x40048284 0x00010180\n\tmww phys 0x40048288 0x00010180\n\tmww phys 0x4004828c 0x00010180\n\tmww phys 0x40048290 0x00010180\n\tmww phys 0x40048294 0x00010180\n\tmww phys 0x40048298 0x00010180\n\tmww phys 0x4004829c 0x00010180\n\tmww phys 0x400482a0 0x00010180\n\tmww phys 0x400482a4 0x00010180\n\tmww phys 0x400482a8 0x00010180\n\tmww phys 0x400482ac 0x00010180\n\tmww phys 0x400482b0 0x00010180\n\tmww phys 0x400482b4 0x00010180\n\tmww phys 0x400482b8 0x00010180\n\tmww phys 0x400482bc 0x00010180\n\tmww phys 0x400482c0 0x00010180\n\tmww phys 0x400482c4 0x00010180\n\tmww phys 0x400482c8 0x00010180\n\tmww phys 0x400482cc 0x00000180\n\tmww phys 0x400482d0 0x00000180\n\tmww phys 0x400482d4 0x00000180\n\tmww phys 0x400482d8 0x00000180\n\tmww phys 0x4004821c 0x000001a0\n\t# ddr_ctrl_init\n\tmww phys 0x400ae000 0x00000600\n\tmww phys 0x400ae008 0x00000020\n\tmww phys 0x400ae028 0x00013880\n\tmww phys 0x400ae02c 0x00030d40\n\tmww phys 0x400ae030 0x0000050c\n\tmww phys 0x400ae034 0x15040400\n\tmww phys 0x400ae038 0x1406040f\n\tmww phys 0x400ae040 0x04040000\n\tmww phys 0x400ae044 0x006db00c\n\tmww phys 0x400ae048 0x00000403\n\tmww phys 0x400ae050 0x01000000\n\tmww phys 0x400ae054 0x00060001\n\tmww phys 0x400ae058 0x000c0000\n\tmww phys 0x400ae05c 0x03000200\n\tmww phys 0x400ae060 0x00000006\n\tmww phys 0x400ae064 0x00010000\n\tmww phys 0x400ae068 0x0c30002c\n\tmww phys 0x400ae070 0x00000000\n\tmww phys 0x400ae074 0x00000003\n\tmww phys 0x400ae078 0x0000000a\n\tmww phys 0x400ae07c 0x003001d4\n\tmww phys 0x400ae084 0x00010000\n\tmww phys 0x400ae088 0x00050500\n\tmww phys 0x400ae098 0x00000000\n\tmww phys 0x400ae09c 0x04001002\n\tmww phys 0x400ae0a4 0x00000001\n\tmww phys 0x400ae0c0 0x00460420\n\tmww phys 0x400ae108 0x01000200\n\tmww phys 0x400ae10c 0x00000040\n\tmww phys 0x400ae114 0x00000200\n\tmww phys 0x400ae118 0x00000040\n\tmww phys 0x400ae120 0x00000000\n\tmww phys 0x400ae124 0x0a010300\n\tmww phys 0x400ae128 0x01014040\n\tmww phys 0x400ae12c 0x01010101\n\tmww phys 0x400ae130 0x03030100\n\tmww phys 0x400ae134 0x01000101\n\tmww phys 0x400ae138 0x0700000c\n\tmww phys 0x400ae13c 0x00000000\n\tmww phys 0x400ae148 0x10000000\n\tmww phys 0x400ae15c 0x01000000\n\tmww phys 0x400ae160 0x00040000\n\tmww phys 0x400ae164 0x00000002\n\tmww phys 0x400ae16c 0x00020000\n\tmww phys 0x400ae180 0x00002819\n\tmww phys 0x400ae184 0x01000000\n\tmww phys 0x400ae188 0x00000000\n\tmww phys 0x400ae18c 0x00000000\n\tmww phys 0x400ae198 0x00000000\n\tmww phys 0x400ae1a4 0x00000c00\n\tmww phys 0x400ae1a8 0x00000000\n\tmww phys 0x400ae1b8 0x0000000c\n\tmww phys 0x400ae1c8 0x00000000\n\tmww phys 0x400ae1cc 0x00000000\n\tmww phys 0x400ae1d4 0x00000000\n\tmww phys 0x400ae1d8 0x01010000\n\tmww phys 0x400ae1e0 0x02020000\n\tmww phys 0x400ae1e4 0x00000202\n\tmww phys 0x400ae1e8 0x01010064\n\tmww phys 0x400ae1ec 0x00010101\n\tmww phys 0x400ae1f0 0x00000064\n\tmww phys 0x400ae1f8 0x00000800\n\tmww phys 0x400ae210 0x00000506\n\tmww phys 0x400ae224 0x00020000\n\tmww phys 0x400ae228 0x01000000\n\tmww phys 0x400ae22c 0x04070303\n\tmww phys 0x400ae230 0x00000040\n\tmww phys 0x400ae23c 0x06000080\n\tmww phys 0x400ae240 0x04070303\n\tmww phys 0x400ae244 0x00000040\n\tmww phys 0x400ae248 0x00000040\n\tmww phys 0x400ae24c 0x000f0000\n\tmww phys 0x400ae250 0x000f0000\n\tmww phys 0x400ae25c 0x00000101\n\tmww phys 0x400ae268 0x682c4000\n\tmww phys 0x400ae26c 0x00000012\n\tmww phys 0x400ae278 0x00000006\n\tmww phys 0x400ae284 0x00010202\n\tmww phys 0x400ae400 0x00002613\n\tmww phys 0x400ae440 0x00002613\n\tmww phys 0x400ae404 0x00002615\n\tmww phys 0x400ae444 0x00002615\n\tmww phys 0x400ae408 0x00210000\n\tmww phys 0x400ae448 0x00210000\n\tmww phys 0x400ae488 0x00210000\n\tmww phys 0x400ae40c 0x0001012a\n\tmww phys 0x400ae44c 0x0001012a\n\tmww phys 0x400ae48c 0x0001012a\n\tmww phys 0x400ae410 0x00002400\n\tmww phys 0x400ae450 0x00002400\n\tmww phys 0x400ae490 0x00002400\n\tmww phys 0x400ae4c4 0x00000000\n\tmww phys 0x400ae4c8 0x00001100\n\tmww phys 0x400ae4d0 0x00010101\n\tmww phys 0x400ae000 0x00000601\n}\n\n# clock control init, setting up basic\n# clocks\nproc clock_init { } {\n\t# captured from u-boot\n\tmww phys 0x4006b040 0xffffffff\n\tmww phys 0x4006b044 0xffffffff\n\tmww phys 0x4006b048 0xffffffff\n\tmww phys 0x4006b04c 0xffffffff\n\tmww phys 0x4006b050 0xffffffff\n\tmww phys 0x4006b058 0xffffffff\n\tmww phys 0x4006b05c 0xffffffff\n\tmww phys 0x4006b060 0xffffffff\n\tmww phys 0x4006b064 0xffffffff\n\tmww phys 0x4006b068 0xffffffff\n\tmww phys 0x40050030 0x00002001\n\tmww phys 0x40050270 0x80002001\n\tmww phys 0x4006b000 0x00011005\n\tmww phys 0x4006b008 0x0001ff24\n\tmww phys 0x4006b00c 0x00000810\n\tmww phys 0x4006b010 0x00cc0000\n\tmww phys 0x4006b014 0x01000000\n\tmww phys 0x4006b018 0x20000000\n\tmww phys 0x4006b01c 0x0000001f\n\tmww phys 0x4006b020 0x00000000\n}\n\n# This function applies the initial configuration after a \"reset init\"\n# command\nproc board_init { } {\n\tclock_init\n\tddr_init\n}\n\n# hook the init function into the reset-init event\n${_TARGETNAME}0 configure -event reset-init { board_init }\n# set a slow default JTAG clock, can be overridden later\nadapter speed 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/twr-vf65gs10_cmsisdap.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Board configuration file for the Freescale VF65GS10 tower board\n#\n# CMSIS-DAP via USB-OTG connector\n#\nsource [find interface/cmsis-dap.cfg]\n\n# only SWD is supported by the CMSIS-DAP on this board\ntransport select swd\n\n# Source generic part of twr-vf65gs10 configuration\nsource [find board/twr-vf65gs10.cfg]\n\n# override reset configuration\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/tx25_stk5.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# -------------------------------------------------------------------------\n# KaRo TX25 CPU Module on a StarterkitV base board\n# http://www.karo-electronics.com/tx25.html\n# -------------------------------------------------------------------------\n\n\nsource [find target/imx25.cfg]\n\n\t#-------------------------------------------------------------------------\n\t# Declare Nand\n\t#-------------------------------------------------------------------------\n\n\tnand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap\n\n\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { tx25_init }\n\n\nproc tx25_init { } {\n\n\t#-------------------------------------------------------------------------\n\t# AIPS setup - Only setup MPROTx registers. The PACR default values are good.\n\t# Set all MPROTx to be non-bufferable, trusted for R/W,\n\t# not forced to user-mode.\n\t#-------------------------------------------------------------------------\n\n\tmww 0x43f00000 0x77777777\n\tmww 0x43f00004 0x77777777\n\tmww 0x53f00000 0x77777777\n\tmww 0x53f00004 0x77777777\n\n\tsleep 100\n\n\t#-------------------------------------------------------------------------\n\t# MAX (Multi-Layer AHB Crossbar Switch) setup\n\t# MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB\n\t#-------------------------------------------------------------------------\n\n\tmww 0x43f04000 0x00043210\n\tmww 0x43f04100 0x00043210\n\tmww 0x43f04200 0x00043210\n\tmww 0x43f04300 0x00043210\n\tmww 0x43f04400 0x00043210\n\n\t# SGPCR - always park on last master\n\tmww 0x43f04010 0x10\n\tmww 0x43f04110 0x10\n\tmww 0x43f04210 0x10\n\tmww 0x43f04310 0x10\n\tmww 0x43f04410 0x10\n\n\t# MGPCR - restore default values\n\tmww 0x43f04800 0x0\n\tmww 0x43f04900 0x0\n\tmww 0x43f04a00 0x0\n\tmww 0x43f04b00 0x0\n\tmww 0x43f04c00 0x0\n\n\t# Configure M3IF registers\n\t# M3IF Control Register (M3IFCTL) for MX25\n\t# MRRP[0] = LCDC           on priority list (1 << 0)  = 0x00000001\n\t# MRRP[1] = MAX1       not on priority list (0 << 1)  = 0x00000000\n\t# MRRP[2] = MAX0       not on priority list (0 << 2)  = 0x00000000\n\t# MRRP[3] = USB HOST   not on priority list (0 << 3)  = 0x00000000\n\t# MRRP[4] = SDMA       not on priority list (0 << 4)  = 0x00000000\n\t# MRRP[5] = SD/ATA/FEC not on priority list (0 << 5)  = 0x00000000\n\t# MRRP[6] = SCMFBC     not on priority list (0 << 6)  = 0x00000000\n\t# MRRP[7] = CSI        not on priority list (0 << 7)  = 0x00000000\n\t#                                                       ----------\n\t#                                                       0x00000001\n\tmww 0xb8003000 0x00000001\n\n\t#-------------------------------------------------------------------------\n\t# configure ARM CLK\n\t#-------------------------------------------------------------------------\n\n\t# Set the Clock CTL (HRM p. 355)\n\tmww 0x53F80008 0x20034000\n\n\t# Setup Clock Gating CTL 0-2 (HRM p. 357)\n\tmww 0x53F8000C 0x1fffffff\n\tmww 0x53F80010 0xffffffff\n\tmww 0x53F80014 0x000fdfff\n\n\t#-------------------------------------------------------------------------\n\t# SDRAM initialization\n\t#-------------------------------------------------------------------------\n\n\t# set to 3.3v SDRAM\n\tmww 0x43FAC454 0x00000800\n\n\t# reset (set up ESDMISC)\n\tmww 0xB8001010 0x00000002\n\n\t# Setup for SDRAM Bank 0\n\t#-------------------------------------------------------------------------\n\n\t# Write ESDCFG0\n\tmww 0xB8001004 0x00095728\n\n\t# CTL SMode = Precharge command\n\tmww 0xB8001000 0x92116480\n\tmww 0x80000400 0x00000000\n\n\t# CTL SMode = Auto Refresh command\n\tmww 0xB8001000 0xA2116480\n\tmww 0x80000000 0x0\n\tmww 0x80000000 0x0\n\tmww 0x80000000 0x0\n\tmww 0x80000000 0x0\n\tmww 0x80000000 0x0\n\tmww 0x80000000 0x0\n\tmww 0x80000000 0x0\n\tmww 0x80000000 0x0\n\n\t# CTL SMode = Load Mode Register command\n\tmww 0xB8001000 0xB2116480\n\tmwb 0x80000033 0x00\n\n\t# CTL SMode = normal\n\tmww 0xB8001000 0x82116480\n\n\t# Setup for SDRAM Bank 1\n\t#-------------------------------------------------------------------------\n\n\t# Write ESDCFG1\n\tmww 0xB800100C 0x00095728\n\n\t# CTL SMode = Precharge command\n\tmww 0xB8001008 0x92116480\n\tmww 0x90000400 0x00000000\n\n\t# CTL SMode = Auto Refresh command\n\tmww 0xB8001008 0xA2116480\n\tmww 0x90000000 0x00000000\n\tmww 0x90000000 0x00000000\n\tmww 0x90000000 0x00000000\n\tmww 0x90000000 0x00000000\n\tmww 0x90000000 0x00000000\n\tmww 0x90000000 0x00000000\n\tmww 0x90000000 0x00000000\n\tmww 0x90000000 0x00000000\n\n\t# CTL SMode = Load Mode Register command\n\tmww 0xB8001008 0xB2116480\n\tmwb 0x90000033 0x00\n\n\t# CTL SMode = normal\n\tmww 0xB8001008 0x82116480\n\n\t# GPIO configuration\n\t#-------------------------------------------------------------------------\n\n\tmww 0x43FAC02C 0x00000015\n\tmww 0x53FD0000 0x01000000\n\tmww 0x53FD0004 0x00000080\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/tx27_stk5.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# KaRo TX27 CPU Module on a StarterkitV base board\n#\n# http://www.karo-electronics.com/tx27.html\n#\nsource [find target/imx27.cfg]\n\n$_TARGETNAME configure -event gdb-attach { reset init }\n$_TARGETNAME configure -event reset-init { tx27_init }\n\nproc tx27_init { } {\n\t# This setup puts RAM at 0xA0000000\n\t# init_aipi (AIPI1.PSR0, AIPI2.PSR0, AIPI1.PSR1 and AIPI2.PSR1)\n\tmww 0x10000000 0x20040304\n\tmww 0x10020000 0x00000000\n\tmww 0x10000004 0xDFFBFCFB\n\tmww 0x10020004 0xFFFFFFFF\n\n\tsleep 100\n\n\t#init_max ( PORT0.MPR, #PORT0.AMPR, #PORT1.MPR, #PORT1.AMPR, #PORT2.MPR, #PORT2.AMPR)\n\tmww 0x1003F000 0x00302145\n\tmww 0x1003F004 0x00302145\n\tmww 0x1003F100 0x00302145\n\tmww 0x1003F104 0x00302145\n\tmww 0x1003F200 0x00302145\n\tmww 0x1003F204 0x00302145\n\n\t#init_drive_strength (#DSCR3, #DSCR5, #DSCR6, #DSCR7, #DSCR8 )\n\tmww 0x10027828 0x55555555\n\tmww 0x10027830 0x55555555\n\tmww 0x10027834 0x55555555\n\tmww 0x10027838 0x00005005\n\tmww 0x1002783C 0x15555555\n\n\t#init_sdram_speed\n\t#mww 0xD8001010 0x00000004\n\tmww 0xD8001010 0x00000024\n\n\tmww 0xD8001004 0x00395729\n\n\tmww 0xD8001000 0x92120000\n\tmww 0xA0000400 0x0\n\n\tmww 0xD8001000 0xA2120000\n\tmww 0xA0000000 0x0\n\tmww 0xA0000000 0x0\n\n\tmww 0xD8001000 0xB2120000\n\tmdb 0xA0000000\n\tmdb 0xA0000033\n\n\tmww 0xD8001000 0x82126485\n\n\t# =============================================\n\t# Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz)\n\t# =============================================\n\tmww 0xD8002000 0x23524E80\n\tmww 0xD8002004 0x10000D03\n\tmww 0xD8002008 0x00720900\n\n\tnand probe 0\n}\n\nnand device tx27.nand mxc $_TARGETNAME mx27 hwecc biswap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/unknown_at91sam9260.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Thanks to Pieter Conradie for this script!\n#\n# Unknown vendor board contains:\n#\n# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz\n#                     OSCSEL configured for internal RC oscillator (22 to 42 kHz)\n#\n# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit\n# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks\n##################################################################\n\n# We add to the minimal configuration.\nsource [find target/at91sam9260.cfg]\n\n$_TARGETNAME configure -event reset-start {\n        # At reset CPU runs at 22 to 42 kHz.\n        # JTAG Frequency must be 6 times slower.\n        jtag_rclk 3\n        halt\n\t# RSTC_MR : enable user reset, MMU may be enabled... use physical address\n        mww phys 0xfffffd08 0xa5000501\n}\n\n\n$_TARGETNAME configure -event reset-init {\n        mww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog\n\n\tmww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator\n        sleep 20                          ;# wait 20 ms\n        mww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator\n        sleep 10                          ;# wait 10 ms\n        mww 0xfffffc28 0x205dbf09         ;# CKGR_PLLAR: Set PLLA Register for 192.512MHz\n        sleep 20                          ;# wait 20 ms\n        mww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler (divide by 2)\n        sleep 10                          ;# wait 10 ms\n        mww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected (96.256 MHz)\n        sleep 10                          ;# wait 10 ms\n\n\t# Increase JTAG Speed to 6 MHz if RCLK is not supported\n        jtag_rclk 6000\n\n\tarm7_9 dcc_downloads enable       ;# Enable faster DCC downloads\n\n\tmww 0xffffec00 0x01020102         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit\n\tmww 0xffffec04 0x09070806         ;# SMC_PULSE0\n\tmww 0xffffec08 0x000d000b         ;# SMC_CYCLE0\n\tmww 0xffffec0c 0x00001003         ;# SMC_MODE0\n\n\tflash probe 0                     ;# Identify flash bank 0\n\n\tmww 0xfffff870 0xffff0000         ;# PIO_ASR  : Select peripheral function for D15..D31\n        mww 0xfffff804 0xffff0000         ;# PIO_PDR  : Disable PIO function for D15..D31\n        mww 0xfffff860 0xffff0000         ;# PIO_PUDR : Disable D15..D31 pull-ups\n\n        mww 0xffffef1c 0x00010102         ;# EBI_CSA  : Assign EBI Chip Select 1 to SDRAM\n                                           #            VDDIOMSEL set for +3V3 memory\n                                           #            Disable D0..D15 pull-ups\n\n\tmww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)\n\n\tmww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode\n\tmww 0x20000000 0\n\tmww 0xffffea04 0x2a2              ;# SDRAMC_TR : Set refresh timer count to 7us\n}\n\n\n#####################\n# Flash configuration\n#####################\n\n#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/uptech_2410.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Target Configuration for the Uptech 2410 board.\n# This configuration should also work on smdk2410, but I haven't tested it yet.\n# Author: xionglingfeng@Gmail.com\n\nsource [find target/samsung_s3c2410.cfg]\n\n$_TARGETNAME configure -event reset-init { uptech2410_init }\n$_TARGETNAME configure -event gdb-attach { reset init }\n\nproc init_pll_sdram { } {\n\t#echo \"---------- Initializing PLL and SDRAM ---------\"\n\t#watchdog timer disable\n\tmww phys 0x53000000 0x00000000\n\n\t#disable all interrupts\n\tmww phys 0x4a000008 0xffffffff\n\n\t#disable all sub-interrupts\n\tmww phys 0x4a00001c 0x000007ff\n\n\t#clear all source pending bits\n\tmww phys 0x4a000000 0xffffffff\n\n\t#clear all sub-source pending bits\n\tmww phys 0x4a000018 0x000007ff\n\n\t#clear interrupt pending bit\n\tmww phys 0x4a000010 0xffffffff\n\n\t#PLL locktime counter\n\tmww phys 0x4c000000 0x00ffffff\n\n\t#Fin=12MHz Fout=202.8MHz\n\t#mww phys 0x4c000004 0x000a1031\n\n\t#FCLK:HCLK:PCLK = 1:2:4\n\tmww phys 0x4c000014 0x00000003\n\n\n\tmww phys 0x48000000 0x11111110\n\tmww phys 0x48000004 0x00007FFC\n\tmww phys 0x48000008 0x00007FFC\n\tmww phys 0x4800000c 0x00000700\n\tmww phys 0x48000010 0x00000700\n\tmww phys 0x48000014 0x00002E50\n\tmww phys 0x48000018 0x00002E50\n\tmww phys 0x4800001c 0x00018005\n\tmww phys 0x48000020 0x00018005\n\tmww phys 0x48000024 0x008c04e9\n\tmww phys 0x48000028 0x000000b2\n\tmww phys 0x4800002c 0x00000030\n\tmww phys 0x48000030 0x00000030\n}\n\nproc uptech2410_init { } {\n\tinit_pll_sdram\n\t#echo \"---------- Probing Nand flash ----------\"\n\tnand probe 0\n\t#echo \"---------- Enable some functions ----------\"\n}\n\nset _NANDNAME $_CHIPNAME.nand\nnand device $_NANDNAME s3c2410 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/vd_a53x2_dap.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# Arm Cortex A53x2 through DAP\n\nsource [find interface/vdebug.cfg]\n\nset _CORES 2\nset _CHIPNAME a53\nset _MEMSTART 0x00000000\nset _MEMSIZE 0x1000000\n\n# vdebug select transport\ntransport select dapdirect_swd\n\n# JTAG reset config, frequency and reset delay\nadapter speed 50000\nadapter srst delay 5\n\n# BFM hierarchical path and input clk period\nvdebug bfm_path tbench.u_vd_swdp_bfm 10ns\n\n# DMA Memories to access backdoor (up to 4)\nvdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE\n\nsource [find target/swj-dp.tcl]\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf\n\nsource [find target/vd_aarch64.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/vd_a53x2_jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# Arm Cortex A53x2 through JTAG\n\nsource [find interface/vdebug.cfg]\n\nset _CORES 2\nset _CHIPNAME a53\nset _MEMSTART 0x00000000\nset _MEMSIZE 0x1000000\nset _CPUTAPID 0x5ba00477\n\n# vdebug select transport\ntransport select jtag\n\n# JTAG reset config, frequency and reset delay\nreset_config trst_and_srst\nadapter speed 50000\nadapter srst delay 5\n\n# BFM hierarchical path and input clk period\nvdebug bfm_path tbench.u_vd_jtag_bfm 10ns\n\n# DMA Memories to access backdoor (up to 4)\nvdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\njtag arp_init-reset\n\nsource [find target/vd_aarch64.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/vd_m4_dap.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# Arm Cortex m4 through DAP\n\nsource [find interface/vdebug.cfg]\n\nset _CHIPNAME m4\nset _MEMSTART 0x00000000\nset _MEMSIZE 0x10000\n\n# vdebug select transport\ntransport select dapdirect_swd\nadapter speed 25000\nadapter srst delay 5\n\n# BFM hierarchical path and input clk period\nvdebug bfm_path tbench.u_vd_swdp_bfm 20ns\n\n# DMA Memories to access backdoor (up to 4)\nvdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE\n\nsource [find target/swj-dp.tcl]\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf\n\nsource [find target/vd_cortex_m.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/vd_m4_jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# Arm Cortex m4 through JTAG\n\nsource [find interface/vdebug.cfg]\n\nset _CHIPNAME m4\nset _MEMSTART 0x00000000\nset _MEMSIZE 0x10000\nset _CPUTAPID 0x4ba00477\n\n# vdebug select transport\ntransport select jtag\n\n# JTAG reset config, frequency and reset delay\nreset_config trst_and_srst\nadapter speed 25000\nadapter srst delay 5\n\n# BFM hierarchical path and input clk period\nvdebug bfm_path tbench.u_vd_jtag_bfm 20ns\n\n# DMA Memories to access backdoor (up to 4)\nvdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\njtag arp_init-reset\n\nsource [find target/vd_cortex_m.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/vd_m7_jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# Arm Cortex m7 through JTAG\n\nsource [find interface/vdebug.cfg]\n\nset _CHIPNAME m7\nset _MEMSTART 0x00000000\nset _MEMSIZE 0x100000\nset _CPUTAPID 0x0ba02477\n\n# vdebug select JTAG transport\ntransport select jtag\n\n# JTAG reset config, frequency and reset delay\nreset_config trst_and_srst\nadapter speed 50000\nadapter srst delay 5\n\n# BFM hierarchical path and input clk period\nvdebug bfm_path tbench.u_vd_jtag_bfm 10ns\n\n# DMA Memories to access backdoor (up to 4)\nvdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\njtag arp_init-reset\n\nsource [find target/vd_cortex_m.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/vd_pulpissimo_jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# RISCV Ibex core with Pulpissimo through JTAG\n\nsource [find interface/vdebug.cfg]\n\nset _CHIPNAME ibex\nset _HARTID 0x20\nset _CPUTAPID 0x249511c3\n\n# vdebug select transport\ntransport select jtag\n\n# JTAG reset config, frequency and reset delay\nreset_config trst_and_srst\nadapter speed 12500\nadapter srst delay 10\n\n# BFM hierarchical path and input clk period\nvdebug bfm_path tbench.u_vd_jtag_bfm 40ns\n\n# DMA Memories to access backdoor (up to 4)\nvdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\\[0\\].sram_i.mem_array 0x1c000000 0x8000\nvdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\\[1\\].sram_i.mem_array 0x1c008000 0x8000\nvdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2\\[0\\].sram_i.mem_array 0x1c010000 0x80000\n\n# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $_CPUTAPID\n\njtag arp_init-reset\n\nsource [find target/vd_riscv.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/vd_swerv_jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# RISCV swerv core with Swerv through JTAG\n\nsource [find interface/vdebug.cfg]\n\nset _CHIPNAME rv32\nset _HARTID 0x00\nset _CPUTAPID 0x1000008b\nset _MEMSTART 0x00000000\nset _MEMSIZE 0x10000\n\n# vdebug select transport\ntransport select jtag\n\n# JTAG reset config, frequency and reset delay\nreset_config trst_and_srst\nadapter speed 50000\nadapter srst delay 5\n\n# BFM hierarchical path and input clk period\nvdebug bfm_path tbench.u_vd_jtag_bfm 10ns\n\n# DMA Memories to access backdoor (up to 4)\nvdebug mem_path tbench.i_ahb_ic.mem $_MEMSTART $_MEMSIZE\n\n# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID\n\njtag arp_init-reset\n\nsource [find target/vd_riscv.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/vd_xt8_jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# Xtensa xt8 through JTAG\n\nsource [find interface/vdebug.cfg]\n\nset CHIPNAME xt8\nset CPUTAPID 0x120034e5\n\n# vdebug select transport\ntransport select jtag\n\n# JTAG reset config, frequency and reset delay\nreset_config trst_and_srst\nadapter speed 50000\nadapter srst delay 5\n\n# BFM hierarchical path and input clk period\nvdebug bfm_path Testbench.u_vd_jtag_bfm 10ns\n\n# DMA Memories to access backdoor, the values come from generated xtensa-core-xt8.cfg\n#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray 0x40000000 0x100000\n#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray 0x3ff00000 0x40000\n\n# Create Xtensa target first\nsource [find target/xtensa.cfg]\n# Generate [xtensa-core-XXX.cfg] via \"xt-gdb --dump-oocd-config\"\nsource  [find target/xtensa-core-xt8.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/verdex.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config for Gumstix Verdex XM4 and XL6P (PXA270)\n\nset CHIPNAME verdex\nsource [find target/pxa270.cfg]\n\n# The board supports separate reset lines\n# Override this in the interface config for parallel dongles\nreset_config trst_and_srst separate\n\n# XM4 = 400MHz, XL6P = 600MHz...let's run at 0.1*400MHz=40MHz\nadapter speed 40000\n\n# flash bank <driver> <base> <size> <chip_width> <bus_width>\n# XL6P has 32 MB flash\nflash bank $_CHIPNAME.flash0 cfi 0x00000000 0x02000000 2 2 $_TARGETNAME\n# XM4 has 16 MB flash\n#flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/voipac.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config for Voipac PXA270/PXA270M module.\n\nset CHIPNAME voipac\nsource [find target/pxa270.cfg]\n\n# The board supports separate reset lines\n# Override this in the interface config for parallel dongles\nreset_config trst_and_srst separate\n\n# flash bank <driver> <base> <size> <chip_width> <bus_width>\nflash bank $_CHIPNAME.flash0 cfi 0x00000000 0x2000000 2 2 $_TARGETNAME\nflash bank $_CHIPNAME.flash1 cfi 0x02000000 0x2000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/voltcraft_dso-3062c.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Voltcraft DSO-3062C digital oscilloscope (uses a Samsung S3C2440)\n#\n# http://www.eevblog.com/forum/general-chat/hantek-tekway-dso-hack-get-200mhz-bw-for-free/\n# http://www.mikrocontroller.net/topic/249628\n# http://elinux.org/Das_Oszi\n# http://randomprojects.org/wiki/Voltcraft_DSO-3062C\n#\n\n# Enable this if your JTAG adapter supports multiple transports (JTAG or SWD).\n# Otherwise comment it out, as it will cause an OpenOCD error.\n### transport select jtag\n\nsource [find target/samsung_s3c2440.cfg]\n\nadapter speed 16000\n\n# Samsung K9F1208U0C NAND flash chip (64MiB, 3.3V, 8-bit)\nnand device $_CHIPNAME.nand s3c2440 $_TARGETNAME\n\n# arm7_9 fast_memory_access enable\n# arm7_9 dcc_downloads enable\n\ninit\nreset\nhalt\nscan_chain\ntargets\nnand probe 0\nnand list\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/x300t.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is for the T-Home X300T / X301T IPTV box,\n# which are based on IPTV reference designs from Kiss/Cisco KMM-3***\n#\n# It has Sigma Designs SMP8634 chip.\nsource [find target/smp8634.cfg]\n\n$_TARGETNAME configure -event reset-init { x300t_init }\n\n# 1MB CFI capable flash\n# flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0xac000000 0x100000 2 2 $_TARGETNAME\n\nproc x300t_init { } {\n\t# Setup SDRAM config and flash mapping\n\t# initialize ram\n\tmww 0xa003fffc 3\n\tmww 0xa003fffc 2\n\tmww 0xa0030000 0xE34111BA\n\tmww 0xa003fffc 0xa4444\n\tmww 0xa003fffc 0\n\n\t# remap boot vector in CPU local RAM\n\tmww 0xa006f000 0x60000\n\n\t# map flash to CPU address space REG_BASE_cpu_block+CPU_remap4\n\tmww 0x0006f010 0x48000000\n\n\t# map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS)\n\tmww 0x00061ff0 0x48000000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmc-2go.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC 2Go\n#\n\n#\n# Segger J-Link Lite XMC4200 on-board\n#\nsource [find interface/jlink.cfg]\ntransport select swd\n\nset CHIPNAME xmc1100\nset WORKAREASIZE 0x4000\nsource [find target/xmc1xxx.cfg]\n\nreset_config srst_only srst_nogate\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmc1100-boot-kit.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC1100 Boot Kit\n#\n\n#\n# Segger J-Link Lite XMC4200 on-board\n#\nsource [find interface/jlink.cfg]\ntransport select swd\n\nset CHIPNAME xmc1100\nset WORKAREASIZE 0x4000\nsource [find target/xmc1xxx.cfg]\n\nreset_config srst_only srst_nogate\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmc4200-application-kit-actuator.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC4200 Application Kit - Actuator\n#\n\n#\n# Segger J-Link Lite XMC4200 on-board\n#\nsource [find interface/jlink.cfg]\ntransport select swd\n\nset CHIPNAME xmc4200\nsource [find target/xmc4xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmc4300-relax.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC4300 Relax EtherCAT Kit\n#\n\n#\n# Segger J-Link Lite XMC4200 on-board\n#\nsource [find interface/jlink.cfg]\ntransport select swd\n\nset CHIPNAME xmc4300\nsource [find target/xmc4xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmc4500-application-kit-general.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC4500 Application Kit - General Purpose\n#\n\nset CHIPNAME xmc4500\nsource [find target/xmc4xxx.cfg]\n\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmc4500-application-kit-sdram.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC4500 Application Kit - SDRAM\n#\n\n#\n# Segger J-Link Lite XMC4200 on-board\n#\n\nset CHIPNAME xmc4500\nsource [find target/xmc4xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmc4500-relax.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC4500 Relax Kit / Relax Lite Kit\n#\n\n#\n# Segger J-Link Lite XMC4500 on-board\n#\nsource [find interface/jlink.cfg]\ntransport select swd\n\n# There's also an unpopulated 10-pin 0.05\" pinout.\n\nset CHIPNAME xmc4500\nsource [find target/xmc4xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmc4700-relax.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC4700 Relax Lite Kit / Relax Kit for 5V Shields / Relax Kit\n#\n\n#\n# Segger J-Link Lite XMC4200 on-board\n#\nsource [find interface/jlink.cfg]\ntransport select swd\n\n# There's also an unpopulated 10-pin 0.05\" pinout.\n\nset CHIPNAME xmc4700\nsource [find target/xmc4xxx.cfg]\n\n# Relax Kit only: N25Q032A qSPI flash\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmc4800-relax.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC4800 Relax EtherCAT Kit\n#\n\n#\n# Segger J-Link Lite XMC4200 on-board\n#\nsource [find interface/jlink.cfg]\ntransport select swd\n\n# There's also an unpopulated 10-pin 0.05\" pinout.\n\nset CHIPNAME xmc4800\nsource [find target/xmc4xxx.cfg]\n\n# N25Q032A qSPI flash\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xmos_xk-xac-xa8_arm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# xCORE-XA Core Module\n#\n# https://www.xmos.com/support/boards?product=17940\n#\n\n#\n# J-Link OB STM32F103\n#\nsource [find interface/jlink.cfg]\ntransport select swd\n\n#\n# XS1-XAU8A-10\n#\nsource [find target/xmos_xs1-xau8a-10_arm.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xtensa-kc705-ext-dap.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence KC705 FPGA Development Platform for Xtensa targets\n# Can be used with various external adapters that support DAP, e.g. JLink\n#\n\nadapter speed 5000\n\n# KC705 supports DAP/JTAG\ntransport select jtag\nset XTENSA_DAP enable\nset XTENSA_DAP_BASE 0x10000\n\n# Create Xtensa target first\nsource [find target/xtensa.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xtensa-kc705-ext.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence KC705 FPGA Development Platform for Xtensa targets\n# Can be used with various external adapters, e.g. Flyswatter2 or JLink\n#\n\nadapter speed 10000\n\n# KC705 supports JTAG only\ntransport select jtag\n\n# Create Xtensa target first\nsource [find target/xtensa.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xtensa-kc705-onboard.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence KC705 FPGA Development Platform for Xtensa targets\n# Can be used with on-board (FTDI) adapter or various external adapters\n#\n\nsource [find interface/ftdi/xt_kc705_ml605.cfg]\nadapter speed 10000\n\n# KC705 supports JTAG only\ntransport select jtag\n\n# Create Xtensa target first\nsource [find target/xtensa.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xtensa-palladium-vdebug.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# for Palladium emulation systems\n#\n\nsource [find interface/vdebug.cfg]\n\n# vdebug select JTAG transport\ntransport select jtag\n\n# JTAG reset config, frequency and reset delay\nreset_config trst_and_srst\nadapter speed 50000\nadapter srst delay 5\n\nsource [find target/vd_xtensa_jtag.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/board/xtensa-rt685-ext.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# NXP RT6XX Developemnt Platform with Xtensa HiFi DSP\n# Can be used with various external adapters that support DAP, e.g. JLink\n#\n\nadapter speed 10000\n\n# RT6XX supports SWD only\ntransport select swd\nset XTENSA_DAP enable\n\n# Create Xtensa target first\nsource [find target/xtensa.cfg]\n\nsource [find target/xtensa-core-nxp_rt600.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/aic.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset AIC_SMR      \t[expr {$AT91C_BASE_AIC + 0x00000000} ]\nglobal AIC_SMR\nset AIC_SVR      \t[expr {$AT91C_BASE_AIC + 0x00000080} ]\nglobal AIC_SVR\nset AIC_IVR      \t[expr {$AT91C_BASE_AIC + 0x00000100} ]\nglobal AIC_IVR\nset AIC_FVR      \t[expr {$AT91C_BASE_AIC + 0x00000104} ]\nglobal AIC_FVR\nset AIC_ISR      \t[expr {$AT91C_BASE_AIC + 0x00000108} ]\nglobal AIC_ISR\nset AIC_IPR      \t[expr {$AT91C_BASE_AIC + 0x0000010C} ]\nglobal AIC_IPR\nset AIC_IMR      \t[expr {$AT91C_BASE_AIC + 0x00000110} ]\nglobal AIC_IMR\nset AIC_CISR     \t[expr {$AT91C_BASE_AIC + 0x00000114} ]\nglobal AIC_CISR\nset AIC_IECR     \t[expr {$AT91C_BASE_AIC + 0x00000120} ]\nglobal AIC_IECR\nset AIC_IDCR     \t[expr {$AT91C_BASE_AIC + 0x00000124} ]\nglobal AIC_IDCR\nset AIC_ICCR     \t[expr {$AT91C_BASE_AIC + 0x00000128} ]\nglobal AIC_ICCR\nset AIC_ISCR     \t[expr {$AT91C_BASE_AIC + 0x0000012C} ]\nglobal AIC_ISCR\nset AIC_EOICR    \t[expr {$AT91C_BASE_AIC + 0x00000130} ]\nglobal AIC_EOICR\nset AIC_SPU      \t[expr {$AT91C_BASE_AIC + 0x00000134} ]\nglobal AIC_SPU\nset AIC_DCR      \t[expr {$AT91C_BASE_AIC + 0x00000138} ]\nglobal AIC_DCR\nset AIC_FFER     \t[expr {$AT91C_BASE_AIC + 0x00000140} ]\nglobal AIC_FFER\nset AIC_FFDR     \t[expr {$AT91C_BASE_AIC + 0x00000144} ]\nglobal AIC_FFDR\nset AIC_FFSR     \t[expr {$AT91C_BASE_AIC + 0x00000148} ]\nglobal AIC_FFSR\n\n\nproc aic_enable_disable_list { VAL ENAME DNAME } {\n    global AT91C_ID\n\n    show_mmr32_bits AT91C_ID $VAL\n\n}\n\nproc show_AIC_IPR_helper { NAME ADDR VAL } {\n    aic_enable_disable_list  $VAL \"IRQ PENDING\" \"irq not-pending\"\n}\n\nproc show_AIC_IMR_helper { NAME ADDR VAL } {\n    aic_enable_disable_list  $VAL \"IRQ ENABLED\" \"irq disabled\"\n}\n\n\nproc show_AIC { } {\n    global AIC_SMR\n    if [catch { set aaa [read_memory $AIC_SMR 32 [expr {32 * 4}]] } msg ] {\n\terror [format \"%s (%s)\" $msg AIC_SMR]\n    }\n    echo \"AIC_SMR: Mode & Type\"\n    global AT91C_ID\n    for { set x 0 } { $x < 32 } {  } {\n\techo -n \"   \"\n\techo -n [format \"%2d: %5s 0x%08x | \" $x $AT91C_ID($x) [lindex $aaa $x]]\n\tincr x\n\techo -n [format \"%2d: %5s 0x%08x | \" $x $AT91C_ID($x) [lindex $aaa $x]]\n\tincr x\n\techo -n [format \"%2d: %5s 0x%08x | \" $x $AT91C_ID($x) [lindex $aaa $x]]\n\tincr x\n\techo  [format \"%2d: %5s 0x%08x\"  $x $AT91C_ID($x) [lindex $aaa $x]]\n\tincr x\n    }\n    global AIC_SVR\n    if [catch { set aaa [read_memory $AIC_SVR 32 [expr {32 * 4}]] } msg ] {\n\terror [format \"%s (%s)\" $msg AIC_SVR]\n    }\n    echo \"AIC_SVR: Vectors\"\n    for { set x 0 } { $x < 32 } {  } {\n\techo -n \"   \"\n\techo -n [format \"%2d: %5s 0x%08x | \" $x $AT91C_ID($x) [lindex $aaa $x]]\n\tincr x\n\techo -n [format \"%2d: %5s 0x%08x | \" $x $AT91C_ID($x) [lindex $aaa $x]]\n\tincr x\n\techo -n [format \"%2d: %5s 0x%08x | \" $x $AT91C_ID($x) [lindex $aaa $x]]\n\tincr x\n\techo [format \"%2d: %5s 0x%08x\" $x $AT91C_ID($x) [lindex $aaa $x]]\n\tincr x\n    }\n\n    foreach REG {\n\tAIC_IVR   AIC_FVR  AIC_ISR\n\tAIC_IPR  AIC_IMR  AIC_CISR  AIC_IECR AIC_IDCR\n\tAIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU  AIC_DCR\n\tAIC_FFER AIC_FFDR AIC_FFSR } {\n\tif [catch { show_mmr32_reg $REG } msg ] {\n\t    error $msg\n\t    break\n\t}\n    }\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91_pio.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset PIO_PER\t0x00\t;# Enable Register\nset PIO_PDR\t0x04\t;# Disable Register\nset PIO_PSR\t0x08\t;# Status Register\nset PIO_OER\t0x10\t;# Output Enable Register\nset PIO_ODR\t0x14\t;# Output Disable Register\nset PIO_OSR\t0x18\t;# Output Status Register\nset PIO_IFER\t0x20\t;# Glitch Input Filter Enable\nset PIO_IFDR\t0x24\t;# Glitch Input Filter Disable\nset PIO_IFSR\t0x28\t;# Glitch Input Filter Status\nset PIO_SODR\t0x30\t;# Set Output Data Register\nset PIO_CODR\t0x34\t;# Clear Output Data Register\nset PIO_ODSR\t0x38\t;# Output Data Status Register\nset PIO_PDSR\t0x3c\t;# Pin Data Status Register\nset PIO_IER\t0x40\t;# Interrupt Enable Register\nset PIO_IDR\t0x44\t;# Interrupt Disable Register\nset PIO_IMR\t0x48\t;# Interrupt Mask Register\nset PIO_ISR\t0x4c\t;# Interrupt Status Register\nset PIO_MDER\t0x50\t;# Multi-driver Enable Register\nset PIO_MDDR\t0x54\t;# Multi-driver Disable Register\nset PIO_MDSR\t0x58\t;# Multi-driver Status Register\nset PIO_PUDR\t0x60\t;# Pull-up Disable Register\nset PIO_PUER\t0x64\t;# Pull-up Enable Register\nset PIO_PUSR\t0x68\t;# Pull-up Status Register\nset PIO_ASR\t0x70\t;# Peripheral A Select Register\nset PIO_BSR\t0x74\t;# Peripheral B Select Register\nset PIO_ABSR\t0x78\t;# AB Status Register\nset PIO_OWER\t0xa0\t;# Output Write Enable Register\nset PIO_OWDR\t0xa4\t;# Output Write Disable Register\nset PIO_OWSR\t0xa8\t;# Output Write Status Register\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91_pmc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset\tAT91_PMC_SCER\t\t[expr {$AT91_PMC + 0x00}]\t;# System Clock Enable Register\nset\tAT91_PMC_SCDR\t\t[expr {$AT91_PMC + 0x04}]\t;# System Clock Disable Register\n\nset\tAT91_PMC_SCSR\t\t[expr {$AT91_PMC + 0x08}]\t;# System Clock Status Register\nset\t\tAT91_PMC_PCK\t\t[expr {1 <<  0}]\t\t;# Processor Clock\nset\t\tAT91RM9200_PMC_UDP\t[expr {1 <<  1}]\t\t;# USB Devcice Port Clock [AT91RM9200 only]\nset\t\tAT91RM9200_PMC_MCKUDP\t[expr {1 <<  2}]\t\t;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]\nset\t\tAT91CAP9_PMC_DDR\t[expr {1 <<  2}]\t\t;# DDR Clock [CAP9 revC & some SAM9 only]\nset\t\tAT91RM9200_PMC_UHP\t[expr {1 <<  4}]\t\t;# USB Host Port Clock [AT91RM9200 only]\nset\t\tAT91SAM926x_PMC_UHP\t[expr {1 <<  6}]\t\t;# USB Host Port Clock [AT91SAM926x only]\nset\t\tAT91CAP9_PMC_UHP\t[expr {1 <<  6}]\t\t;# USB Host Port Clock [AT91CAP9 only]\nset\t\tAT91SAM926x_PMC_UDP\t[expr {1 <<  7}]\t\t;# USB Devcice Port Clock [AT91SAM926x only]\nset\t\tAT91_PMC_PCK0\t\t[expr {1 <<  8}]\t\t;# Programmable Clock 0\nset\t\tAT91_PMC_PCK1\t\t[expr {1 <<  9}]\t\t;# Programmable Clock 1\nset\t\tAT91_PMC_PCK2\t\t[expr {1 << 10}]\t\t;# Programmable Clock 2\nset\t\tAT91_PMC_PCK3\t\t[expr {1 << 11}]\t\t;# Programmable Clock 3\nset\t\tAT91_PMC_HCK0\t\t[expr {1 << 16}]\t\t;# AHB Clock (USB host) [AT91SAM9261 only]\nset\t\tAT91_PMC_HCK1\t\t[expr {1 << 17}]\t\t;# AHB Clock (LCD) [AT91SAM9261 only]\n\nset\tAT91_PMC_PCER\t\t[expr {$AT91_PMC + 0x10}]\t;# Peripheral Clock Enable Register\nset\tAT91_PMC_PCDR\t\t[expr {$AT91_PMC + 0x14}]\t;# Peripheral Clock Disable Register\nset\tAT91_PMC_PCSR\t\t[expr {$AT91_PMC + 0x18}]\t;# Peripheral Clock Status Register\n\nset\tAT91_CKGR_UCKR\t\t[expr {$AT91_PMC + 0x1C}]\t;# UTMI Clock Register [some SAM9, CAP9]\nset\t\tAT91_PMC_UPLLEN\t\t[expr {1   << 16}]\t\t;# UTMI PLL Enable\nset\t\tAT91_PMC_UPLLCOUNT\t[expr {0xf << 20}]\t\t;# UTMI PLL Start-up Time\nset\t\tAT91_PMC_BIASEN\t\t[expr {1   << 24}]\t\t;# UTMI BIAS Enable\nset\t\tAT91_PMC_BIASCOUNT\t[expr {0xf << 28}]\t\t;# UTMI BIAS Start-up Time\n\nset\tAT91_CKGR_MOR\t\t[expr {$AT91_PMC + 0x20}]\t;# Main Oscillator Register [not on SAM9RL]\nset\t\tAT91_PMC_MOSCEN\t\t[expr {1    << 0}]\t\t;# Main Oscillator Enable\nset\t\tAT91_PMC_OSCBYPASS\t[expr {1    << 1}]\t\t;# Oscillator Bypass [SAM9x, CAP9]\nset\t\tAT91_PMC_OSCOUNT\t[expr {0xff << 8}]\t\t;# Main Oscillator Start-up Time\n\nset\tAT91_CKGR_MCFR\t\t[expr {$AT91_PMC + 0x24}]\t;# Main Clock Frequency Register\nset\t\tAT91_PMC_MAINF\t\t[expr {0xffff <<  0}]\t\t;# Main Clock Frequency\nset\t\tAT91_PMC_MAINRDY\t[expr {1\t<< 16}]\t\t;# Main Clock Ready\n\nset\tAT91_CKGR_PLLAR\t\t[expr {$AT91_PMC + 0x28}]\t;# PLL A Register\nset\tAT91_CKGR_PLLBR\t\t[expr {$AT91_PMC + 0x2c}]\t;# PLL B Register\nset\t\tAT91_PMC_DIV\t\t[expr {0xff  <<  0}]\t\t;# Divider\nset\t\tAT91_PMC_PLLCOUNT\t[expr {0x3f  <<  8}]\t\t;# PLL Counter\nset\t\tAT91_PMC_OUT\t\t[expr {3     << 14}]\t\t;# PLL Clock Frequency Range\nset\t\tAT91_PMC_MUL\t\t[expr {0x7ff << 16}]\t\t;# PLL Multiplier\nset\t\tAT91_PMC_USBDIV\t\t[expr {3     << 28}]\t\t;# USB Divisor (PLLB only)\nset\t\t\tAT91_PMC_USBDIV_1\t\t[expr {0 << 28}]\nset\t\t\tAT91_PMC_USBDIV_2\t\t[expr {1 << 28}]\nset\t\t\tAT91_PMC_USBDIV_4\t\t[expr {2 << 28}]\nset\t\tAT91_PMC_USB96M\t\t[expr {1     << 28}]\t\t;# Divider by 2 Enable (PLLB only)\nset\t\tAT91_PMC_PLLA_WR_ERRATA\t[expr {1     << 29}]\t\t;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register\n\nset\tAT91_PMC_MCKR\t\t[expr {$AT91_PMC + 0x30}]\t;# Master Clock Register\nset\t\tAT91_PMC_CSS\t\t[expr {3 <<  0}]\t\t;# Master Clock Selection\nset\t\t\tAT91_PMC_CSS_SLOW\t\t[expr {0 << 0}]\nset\t\t\tAT91_PMC_CSS_MAIN\t\t[expr {1 << 0}]\nset\t\t\tAT91_PMC_CSS_PLLA\t\t[expr {2 << 0}]\nset\t\t\tAT91_PMC_CSS_PLLB\t\t[expr {3 << 0}]\nset\t\t\tAT91_PMC_CSS_UPLL\t\t[expr {3 << 0}]\t;# [some SAM9 only]\nset\t\tAT91_PMC_PRES\t\t[expr {7 <<  2}]\t\t;# Master Clock Prescaler\nset\t\t\tAT91_PMC_PRES_1\t\t\t[expr {0 << 2}]\nset\t\t\tAT91_PMC_PRES_2\t\t\t[expr {1 << 2}]\nset\t\t\tAT91_PMC_PRES_4\t\t\t[expr {2 << 2}]\nset\t\t\tAT91_PMC_PRES_8\t\t\t[expr {3 << 2}]\nset\t\t\tAT91_PMC_PRES_16\t\t[expr {4 << 2}]\nset\t\t\tAT91_PMC_PRES_32\t\t[expr {5 << 2}]\nset\t\t\tAT91_PMC_PRES_64\t\t[expr {6 << 2}]\nset\t\tAT91_PMC_MDIV\t\t[expr {3 <<  8}]\t\t;# Master Clock Division\nset\t\t\tAT91RM9200_PMC_MDIV_1\t\t[expr {0 << 8}]\t;# [AT91RM9200 only]\nset\t\t\tAT91RM9200_PMC_MDIV_2\t\t[expr {1 << 8}]\nset\t\t\tAT91RM9200_PMC_MDIV_3\t\t[expr {2 << 8}]\nset\t\t\tAT91RM9200_PMC_MDIV_4\t\t[expr {3 << 8}]\nset\t\t\tAT91SAM9_PMC_MDIV_1\t\t[expr {0 << 8}]\t;# [SAM9,CAP9 only]\nset\t\t\tAT91SAM9_PMC_MDIV_2\t\t[expr {1 << 8}]\nset\t\t\tAT91SAM9_PMC_MDIV_4\t\t[expr {2 << 8}]\nset\t\t\tAT91SAM9_PMC_MDIV_6\t\t[expr {3 << 8}]\t;# [some SAM9 only]\nset\t\t\tAT91SAM9_PMC_MDIV_3\t\t[expr {3 << 8}]\t;# [some SAM9 only]\nset\t\tAT91_PMC_PDIV\t\t[expr {1 << 12}]\t\t;# Processor Clock Division [some SAM9 only]\nset\t\t\tAT91_PMC_PDIV_1\t\t\t[expr {0 << 12}]\nset\t\t\tAT91_PMC_PDIV_2\t\t\t[expr {1 << 12}]\nset\t\tAT91_PMC_PLLADIV2\t[expr {1 << 12}]\t\t;# PLLA divisor by 2 [some SAM9 only]\nset\t\t\tAT91_PMC_PLLADIV2_OFF\t\t[expr {0 << 12}]\nset\t\t\tAT91_PMC_PLLADIV2_ON\t\t[expr {1 << 12}]\n\nset\tAT91_PMC_USB\t\t[expr {$AT91_PMC + 0x38}]\t;# USB Clock Register [some SAM9 only]\nset\t\tAT91_PMC_USBS\t\t[expr {0x1 <<  0}]\t\t;# USB OHCI Input clock selection\nset\t\t\tAT91_PMC_USBS_PLLA\t\t[expr {0 << 0}]\nset\t\t\tAT91_PMC_USBS_UPLL\t\t[expr {1 << 0}]\nset\t\tAT91_PMC_OHCIUSBDIV\t[expr {0xF <<  8}]\t\t;# Divider for USB OHCI Clock\n\n;# set\tAT91_PMC_PCKR(n)\t[expr {$AT91_PMC + 0x40 + ((n) * 4)}]\t;# Programmable Clock 0-N Registers\nset\t\tAT91_PMC_CSSMCK\t\t[expr {0x1 <<  8}]\t\t;# CSS or Master Clock Selection\nset\t\t\tAT91_PMC_CSSMCK_CSS\t\t[expr {0 << 8}]\nset\t\t\tAT91_PMC_CSSMCK_MCK\t\t[expr {1 << 8}]\n\nset\tAT91_PMC_IER\t\t[expr {$AT91_PMC + 0x60}]\t;# Interrupt Enable Register\nset\tAT91_PMC_IDR\t\t[expr {$AT91_PMC + 0x64}]\t;# Interrupt Disable Register\nset\tAT91_PMC_SR\t\t[expr {$AT91_PMC + 0x68}]\t;# Status Register\nset\t\tAT91_PMC_MOSCS\t\t[expr {1 <<  0}]\t\t;# MOSCS Flag\nset\t\tAT91_PMC_LOCKA\t\t[expr {1 <<  1}]\t\t;# PLLA Lock\nset\t\tAT91_PMC_LOCKB\t\t[expr {1 <<  2}]\t\t;# PLLB Lock\nset\t\tAT91_PMC_MCKRDY\t\t[expr {1 <<  3}]\t\t;# Master Clock\nset\t\tAT91_PMC_LOCKU\t\t[expr {1 <<  6}]\t\t;# UPLL Lock [some SAM9, AT91CAP9 only]\nset\t\tAT91_PMC_OSCSEL\t\t[expr {1 <<  7}]\t\t;# Slow Clock Oscillator [AT91CAP9 revC only]\nset\t\tAT91_PMC_PCK0RDY\t[expr {1 <<  8}]\t\t;# Programmable Clock 0\nset\t\tAT91_PMC_PCK1RDY\t[expr {1 <<  9}]\t\t;# Programmable Clock 1\nset\t\tAT91_PMC_PCK2RDY\t[expr {1 << 10}]\t\t;# Programmable Clock 2\nset\t\tAT91_PMC_PCK3RDY\t[expr {1 << 11}]\t\t;# Programmable Clock 3\nset\tAT91_PMC_IMR\t\t[expr {$AT91_PMC + 0x6c}]\t;# Interrupt Mask Register\n\nset AT91_PMC_PROT\t\t[expr {$AT91_PMC + 0xe4}]\t;# Protect Register [AT91CAP9 revC only]\nset\t\tAT91_PMC_PROTKEY\t0x504d4301\t;# Activation Code\n\nset AT91_PMC_VER\t\t[expr {$AT91_PMC + 0xfc}]\t;# PMC Module Version [AT91CAP9 only]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91_rstc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset AT91_RSTC_CR\t\t[expr {$AT91_RSTC + 0x00}]\t;# Reset Controller Control Register\nset\t\tAT91_RSTC_PROCRST\t[expr {1 << 0}]\t\t;# Processor Reset\nset\t\tAT91_RSTC_PERRST\t[expr {1 << 2}]\t\t;# Peripheral Reset\nset\t\tAT91_RSTC_EXTRST\t[expr {1 << 3}]\t\t;# External Reset\nset\t\tAT91_RSTC_KEY\t\t[expr {0xa5 << 24}]\t\t;# KEY Password\n\nset AT91_RSTC_SR\t\t[expr {$AT91_RSTC + 0x04}]\t;# Reset Controller Status Register\nset\t\tAT91_RSTC_URSTS\t\t[expr {1 << 0}]\t\t;# User Reset Status\nset\t\tAT91_RSTC_RSTTYP\t[expr {7 << 8}]\t\t;# Reset Type\nset\t\t\tAT91_RSTC_RSTTYP_GENERAL\t[expr {0 << 8}]\nset\t\t\tAT91_RSTC_RSTTYP_WAKEUP\t\t[expr {1 << 8}]\nset\t\t\tAT91_RSTC_RSTTYP_WATCHDOG\t[expr {2 << 8}]\nset\t\t\tAT91_RSTC_RSTTYP_SOFTWARE\t[expr {3 << 8}]\nset\t\t\tAT91_RSTC_RSTTYP_USER\t[expr {4 << 8}]\nset\t\tAT91_RSTC_NRSTL\t\t[expr {1 << 16}]\t\t;# NRST Pin Level\nset\t\tAT91_RSTC_SRCMP\t\t[expr {1 << 17}]\t\t;# Software Reset Command in Progress\n\nset AT91_RSTC_MR\t\t[expr {$AT91_RSTC + 0x08}]\t;# Reset Controller Mode Register\nset\t\tAT91_RSTC_URSTEN\t[expr {1 << 0}]\t\t;# User Reset Enable\nset\t\tAT91_RSTC_URSTIEN\t[expr {1 << 4}]\t\t;# User Reset Interrupt Enable\nset\t\tAT91_RSTC_ERSTL\t\t[expr {0xf << 8}]\t\t;# External Reset Length\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91_wdt.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset AT91_WDT_CR\t\t[expr {$AT91_WDT + 0x00}]\t;# Watchdog Control Register\nset\t\tAT91_WDT_WDRSTT\t\t[expr {1    << 0}]\t;# Restart\nset\t\tAT91_WDT_KEY\t\t[expr {0xa5 << 24}]\t;# KEY Password\n\nset AT91_WDT_MR\t\t[expr {$AT91_WDT + 0x04}]\t;# Watchdog Mode Register\nset\t\tAT91_WDT_WDV\t\t[expr {0xfff << 0}]\t;# Counter Value\nset\t\tAT91_WDT_WDFIEN\t\t[expr {1     << 12}]\t;# Fault Interrupt Enable\nset\t\tAT91_WDT_WDRSTEN\t[expr {1     << 13}]\t;# Reset Processor\nset\t\tAT91_WDT_WDRPROC\t[expr {1     << 14}]\t;# Timer Restart\nset\t\tAT91_WDT_WDDIS\t\t[expr {1     << 15}]\t;# Watchdog Disable\nset\t\tAT91_WDT_WDD\t\t[expr {0xfff << 16}]\t;# Delta Value\nset\t\tAT91_WDT_WDDBGHLT\t[expr {1     << 28}]\t;# Debug Halt\nset\t\tAT91_WDT_WDIDLEHLT\t[expr {1     << 29}]\t;# Idle Halt\n\nset AT91_WDT_SR\t\t[expr {$AT91_WDT + 0x08}]\t;# Watchdog Status Register\nset\t\tAT91_WDT_WDUNF\t\t[expr {1 << 0}]\t\t;# Watchdog Underflow\nset\t\tAT91_WDT_WDERR\t\t[expr {1 << 1}]\t\t;# Watchdog Error\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91sam7x128.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find bitsbytes.tcl]\nsource [find cpu/arm/arm7tdmi.tcl]\nsource [find memory.tcl]\nsource [find mmr_helpers.tcl]\n\nset CHIP_MAKER  atmel\nset CHIP_FAMILY at91sam7\nset CHIP_NAME   at91sam7x128\n# how many flash regions.\nset N_FLASH                1\nset FLASH(0,CHIPSELECT)    -1\nset FLASH(0,BASE)          0x00100000\nset FLASH(0,LEN)           $__128K\nset FLASH(0,HUMAN)         \"internal flash\"\nset FLASH(0,TYPE)          \"flash\"\nset FLASH(0,RWX)           $RWX_R_X\nset FLASH(0,ACCESS_WIDTH)  $ACCESS_WIDTH_ANY\n# how many ram regions.\nset N_RAM                  1\nset RAM(0,CHIPSELECT)      -1\nset RAM(0,BASE)            0x00200000\nset RAM(0,LEN)             $__32K\nset RAM(0,HUMAN)           \"internal ram\"\nset RAM(0,TYPE)            \"ram\"\nset RAM(0,RWX)             $RWX_RWX\nset RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY\n\n# I AM LAZY... I create 1 region for all MMRs.\nset N_MMREGS    1\nset MMREGS(0,CHIPSELECT)      -1\nset MMREGS(0,BASE)            0xfff00000\nset MMREGS(0,LEN)             0x000fffff\nset MMREGS(0,HUMAN)           \"mm-regs\"\nset MMREGS(0,TYPE)            \"mmr\"\nset MMREGS(0,RWX)             $RWX_RW\nset MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY\n\n# no external memory\nset N_XMEM 0\n\n\n\n\nset AT91C_BASE_SYS       0xFFFFF000\nset AT91C_BASE_AIC       0xFFFFF000\nset AT91C_BASE_PDC_DBGU  0xFFFFF300\nset AT91C_BASE_DBGU      0xFFFFF200\nset AT91C_BASE_PIOA      0xFFFFF400\nset AT91C_BASE_PIOB      0xFFFFF600\nset AT91C_BASE_CKGR      0xFFFFFC20\nset AT91C_BASE_PMC       0xFFFFFC00\nset AT91C_BASE_RSTC      0xFFFFFD00\nset AT91C_BASE_RTTC      0xFFFFFD20\nset AT91C_BASE_PITC      0xFFFFFD30\nset AT91C_BASE_WDTC      0xFFFFFD40\nset AT91C_BASE_VREG      0xFFFFFD60\nset AT91C_BASE_MC        0xFFFFFF00\nset AT91C_BASE_PDC_SPI1  0xFFFE4100\nset AT91C_BASE_SPI1      0xFFFE4000\nset AT91C_BASE_PDC_SPI0  0xFFFE0100\nset AT91C_BASE_SPI0      0xFFFE0000\nset AT91C_BASE_PDC_US1   0xFFFC4100\nset AT91C_BASE_US1       0xFFFC4000\nset AT91C_BASE_PDC_US0   0xFFFC0100\nset AT91C_BASE_US0       0xFFFC0000\nset AT91C_BASE_PDC_SSC   0xFFFD4100\nset AT91C_BASE_SSC       0xFFFD4000\nset AT91C_BASE_TWI       0xFFFB8000\nset AT91C_BASE_PWMC_CH3  0xFFFCC260\nset AT91C_BASE_PWMC_CH2  0xFFFCC240\nset AT91C_BASE_PWMC_CH1  0xFFFCC220\nset AT91C_BASE_PWMC_CH0  0xFFFCC200\nset AT91C_BASE_PWMC      0xFFFCC000\nset AT91C_BASE_UDP       0xFFFB0000\nset AT91C_BASE_TC0       0xFFFA0000\nset AT91C_BASE_TC1       0xFFFA0040\nset AT91C_BASE_TC2       0xFFFA0080\nset AT91C_BASE_TCB       0xFFFA0000\nset AT91C_BASE_CAN_MB0   0xFFFD0200\nset AT91C_BASE_CAN_MB1   0xFFFD0220\nset AT91C_BASE_CAN_MB2   0xFFFD0240\nset AT91C_BASE_CAN_MB3   0xFFFD0260\nset AT91C_BASE_CAN_MB4   0xFFFD0280\nset AT91C_BASE_CAN_MB5   0xFFFD02A0\nset AT91C_BASE_CAN_MB6   0xFFFD02C0\nset AT91C_BASE_CAN_MB7   0xFFFD02E0\nset AT91C_BASE_CAN       0xFFFD0000\nset AT91C_BASE_EMAC      0xFFFDC000\nset AT91C_BASE_PDC_ADC   0xFFFD8100\nset AT91C_BASE_ADC       0xFFFD8000\n\nset AT91C_ID(0) FIQ\nset AT91C_ID(1) SYS\nset AT91C_ID(2) PIOA\nset AT91C_ID(3) PIOB\nset AT91C_ID(4) SPI0\nset AT91C_ID(5) SPI1\nset AT91C_ID(6) US0\nset AT91C_ID(7) US1\nset AT91C_ID(8) SSC\nset AT91C_ID(9) TWI\nset AT91C_ID(10) PWMC\nset AT91C_ID(11) UDP\nset AT91C_ID(12) TC0\nset AT91C_ID(13) TC1\nset AT91C_ID(14) TC2\nset AT91C_ID(15) CAN\nset AT91C_ID(16) EMAC\nset AT91C_ID(17) ADC\nset AT91C_ID(18) \"\"\nset AT91C_ID(19) \"\"\nset AT91C_ID(20) \"\"\nset AT91C_ID(21) \"\"\nset AT91C_ID(22) \"\"\nset AT91C_ID(23) \"\"\nset AT91C_ID(24) \"\"\nset AT91C_ID(25) \"\"\nset AT91C_ID(26) \"\"\nset AT91C_ID(27) \"\"\nset AT91C_ID(28) \"\"\nset AT91C_ID(29) \"\"\nset AT91C_ID(30) IRQ0\nset AT91C_ID(31) IRQ1\n\nsource [find chip/atmel/at91/aic.tcl]\nsource [find chip/atmel/at91/usarts.tcl]\nsource [find chip/atmel/at91/pmc.tcl]\nsource [find chip/atmel/at91/rtt.tcl]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91sam7x256.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find bitsbytes.tcl]\nsource [find cpu/arm/arm7tdmi.tcl]\nsource [find memory.tcl]\nsource [find mmr_helpers.tcl]\n\nset CHIP_MAKER  atmel\nset CHIP_FAMILY at91sam7\nset CHIP_NAME   at91sam7x256\n# how many flash regions.\nset N_FLASH                1\nset FLASH(0,CHIPSELECT)    -1\nset FLASH(0,BASE)          0x00100000\nset FLASH(0,LEN)           $__256K\nset FLASH(0,HUMAN)         \"internal flash\"\nset FLASH(0,TYPE)          \"flash\"\nset FLASH(0,RWX)           $RWX_R_X\nset FLASH(0,ACCESS_WIDTH)  $ACCESS_WIDTH_ANY\n# how many ram regions.\nset N_RAM                  1\nset RAM(0,CHIPSELECT)      -1\nset RAM(0,BASE)            0x00200000\nset RAM(0,LEN)             $__64K\nset RAM(0,HUMAN)           \"internal ram\"\nset RAM(0,TYPE)            \"ram\"\nset RAM(0,RWX)             $RWX_RWX\nset RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY\n\n# I AM LAZY... I create 1 region for all MMRs.\nset N_MMREGS    1\nset MMREGS(0,CHIPSELECT)      -1\nset MMREGS(0,BASE)            0xfff00000\nset MMREGS(0,LEN)             0x000fffff\nset MMREGS(0,HUMAN)           \"mm-regs\"\nset MMREGS(0,TYPE)            \"mmr\"\nset MMREGS(0,RWX)             $RWX_RW\nset MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY\n\n# no external memory\nset N_XMEM 0\n\nset  AT91C_BASE_SYS              0xFFFFF000\nset  AT91C_BASE_AIC              0xFFFFF000\nset  AT91C_BASE_PDC_DBGU         0xFFFFF300\nset  AT91C_BASE_DBGU             0xFFFFF200\nset  AT91C_BASE_PIOA             0xFFFFF400\nset  AT91C_BASE_PIOB             0xFFFFF600\nset  AT91C_BASE_CKGR             0xFFFFFC20\nset  AT91C_BASE_PMC              0xFFFFFC00\nset  AT91C_BASE_RSTC             0xFFFFFD00\nset  AT91C_BASE_RTTC             0xFFFFFD20\nset  AT91C_BASE_PITC             0xFFFFFD30\nset  AT91C_BASE_WDTC             0xFFFFFD40\nset  AT91C_BASE_VREG             0xFFFFFD60\nset  AT91C_BASE_MC          0xFFFFFF00\nset  AT91C_BASE_PDC_SPI1      0xFFFE4100\nset  AT91C_BASE_SPI1          0xFFFE4000\nset  AT91C_BASE_PDC_SPI0      0xFFFE0100\nset  AT91C_BASE_SPI0          0xFFFE0000\nset  AT91C_BASE_PDC_US1       0xFFFC4100\nset  AT91C_BASE_US1           0xFFFC4000\nset  AT91C_BASE_PDC_US0       0xFFFC0100\nset  AT91C_BASE_US0           0xFFFC0000\nset  AT91C_BASE_PDC_SSC       0xFFFD4100\nset  AT91C_BASE_SSC           0xFFFD4000\nset  AT91C_BASE_TWI           0xFFFB8000\nset  AT91C_BASE_PWMC_CH3      0xFFFCC260\nset  AT91C_BASE_PWMC_CH2      0xFFFCC240\nset  AT91C_BASE_PWMC_CH1      0xFFFCC220\nset  AT91C_BASE_PWMC_CH0      0xFFFCC200\nset  AT91C_BASE_PWMC          0xFFFCC000\nset  AT91C_BASE_UDP           0xFFFB0000\nset  AT91C_BASE_TC0         0xFFFA0000\nset  AT91C_BASE_TC1         0xFFFA0040\nset  AT91C_BASE_TC2         0xFFFA0080\nset  AT91C_BASE_TCB             0xFFFA0000\nset  AT91C_BASE_CAN_MB0         0xFFFD0200\nset  AT91C_BASE_CAN_MB1         0xFFFD0220\nset  AT91C_BASE_CAN_MB2         0xFFFD0240\nset  AT91C_BASE_CAN_MB3         0xFFFD0260\nset  AT91C_BASE_CAN_MB4         0xFFFD0280\nset  AT91C_BASE_CAN_MB5         0xFFFD02A0\nset  AT91C_BASE_CAN_MB6         0xFFFD02C0\nset  AT91C_BASE_CAN_MB7         0xFFFD02E0\nset  AT91C_BASE_CAN             0xFFFD0000\nset  AT91C_BASE_EMAC            0xFFFDC000\nset  AT91C_BASE_PDC_ADC         0xFFFD8100\nset  AT91C_BASE_ADC             0xFFFD8000\n\nset AT91C_ID(0)   \"FIQ\"\nset AT91C_ID(1)   \"SYS\"\nset AT91C_ID(2)   \"PIOA\"\nset AT91C_ID(3)   \"PIOB\"\nset AT91C_ID(4)   \"SPI0\"\nset AT91C_ID(5)   \"SPI1\"\nset AT91C_ID(6)   \"US0\"\nset AT91C_ID(7)   \"US1\"\nset AT91C_ID(8)   \"SSC\"\nset AT91C_ID(9)   \"TWI\"\nset AT91C_ID(10)   \"PWMC\"\nset AT91C_ID(11)   \"UDP\"\nset AT91C_ID(12)   \"TC0\"\nset AT91C_ID(13)   \"TC1\"\nset AT91C_ID(14)   \"TC2\"\nset AT91C_ID(15)   \"CAN\"\nset AT91C_ID(16)   \"EMAC\"\nset AT91C_ID(17)   \"ADC\"\nset AT91C_ID(18)   \"\"\nset AT91C_ID(19)   \"\"\nset AT91C_ID(20)   \"\"\nset AT91C_ID(21)   \"\"\nset AT91C_ID(22)   \"\"\nset AT91C_ID(23)   \"\"\nset AT91C_ID(24)   \"\"\nset AT91C_ID(25)   \"\"\nset AT91C_ID(26)   \"\"\nset AT91C_ID(27)   \"\"\nset AT91C_ID(28)   \"\"\nset AT91C_ID(29)   \"\"\nset AT91C_ID(30)   \"IRQ0\"\nset AT91C_ID(31)   \"IRQ1\"\n\n\nsource [find chip/atmel/at91/aic.tcl]\nsource [find chip/atmel/at91/usarts.tcl]\nsource [find chip/atmel/at91/pmc.tcl]\nsource [find chip/atmel/at91/rtt.tcl]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91sam9261.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Peripheral identifiers/interrupts.\n#\nset AT91_ID_FIQ\t\t0\t;# Advanced Interrupt Controller (FIQ)\nset AT91_ID_SYS\t\t1\t;# System Peripherals\nset AT91SAM9261_ID_PIOA\t2\t;# Parallel IO Controller A\nset AT91SAM9261_ID_PIOB\t3\t;# Parallel IO Controller B\nset AT91SAM9261_ID_PIOC\t4\t;# Parallel IO Controller C\nset AT91SAM9261_ID_US0\t6\t;# USART 0\nset AT91SAM9261_ID_US1\t7\t;# USART 1\nset AT91SAM9261_ID_US2\t8\t;# USART 2\nset AT91SAM9261_ID_MCI\t9\t;# Multimedia Card Interface\nset AT91SAM9261_ID_UDP\t10\t;# USB Device Port\nset AT91SAM9261_ID_TWI\t11\t;# Two-Wire Interface\nset AT91SAM9261_ID_SPI0\t12\t;# Serial Peripheral Interface 0\nset AT91SAM9261_ID_SPI1\t13\t;# Serial Peripheral Interface 1\nset AT91SAM9261_ID_SSC0\t14\t;# Serial Synchronous Controller 0\nset AT91SAM9261_ID_SSC1\t15\t;# Serial Synchronous Controller 1\nset AT91SAM9261_ID_SSC2\t16\t;# Serial Synchronous Controller 2\nset AT91SAM9261_ID_TC0\t17\t;# Timer Counter 0\nset AT91SAM9261_ID_TC1\t18\t;# Timer Counter 1\nset AT91SAM9261_ID_TC2\t19\t;# Timer Counter 2\nset AT91SAM9261_ID_UHP\t20\t;# USB Host port\nset AT91SAM9261_ID_LCDC\t21\t;# LDC Controller\nset AT91SAM9261_ID_IRQ0\t29\t;# Advanced Interrupt Controller (IRQ0)\nset AT91SAM9261_ID_IRQ1\t30\t;# Advanced Interrupt Controller (IRQ1)\nset AT91SAM9261_ID_IRQ2\t31\t;# Advanced Interrupt Controller (IRQ2)\n\n\n#\n# User Peripheral physical base addresses.\n#\nset AT91SAM9261_BASE_TCB0\t\t0xfffa0000\nset AT91SAM9261_BASE_TC0\t\t0xfffa0000\nset AT91SAM9261_BASE_TC1\t\t0xfffa0040\nset AT91SAM9261_BASE_TC2\t\t0xfffa0080\nset AT91SAM9261_BASE_UDP\t\t0xfffa4000\nset AT91SAM9261_BASE_MCI\t\t0xfffa8000\nset AT91SAM9261_BASE_TWI\t\t0xfffac000\nset AT91SAM9261_BASE_US0\t\t0xfffb0000\nset AT91SAM9261_BASE_US1\t\t0xfffb4000\nset AT91SAM9261_BASE_US2\t\t0xfffb8000\nset AT91SAM9261_BASE_SSC0\t\t0xfffbc000\nset AT91SAM9261_BASE_SSC1\t\t0xfffc0000\nset AT91SAM9261_BASE_SSC2\t\t0xfffc4000\nset AT91SAM9261_BASE_SPI0\t\t0xfffc8000\nset AT91SAM9261_BASE_SPI1\t\t0xfffcc000\nset AT91_BASE_SYS\t\t\t0xffffea00\n\n\n#\n# System Peripherals (offset from AT91_BASE_SYS)\n#\nset AT91_SDRAMC\t0xffffea00\nset AT91_SMC\t0xffffec00\nset AT91_MATRIX\t0xffffee00\nset AT91_AIC\t0xfffff000\nset AT91_DBGU\t0xfffff200\nset AT91_PIOA\t0xfffff400\nset AT91_PIOB\t0xfffff600\nset AT91_PIOC\t0xfffff800\nset AT91_PMC\t0xfffffc00\nset AT91_RSTC\t0xfffffd00\nset AT91_SHDWC\t0xfffffd10\nset AT91_RTT\t0xfffffd20\nset AT91_PIT\t0xfffffd30\nset AT91_WDT\t0xfffffd40\nset AT91_GPBR\t0xfffffd50\n\nset AT91_USART0\t$AT91SAM9261_BASE_US0\nset AT91_USART1\t$AT91SAM9261_BASE_US1\nset AT91_USART2\t$AT91SAM9261_BASE_US2\n\n\n#\n# Internal Memory.\n#\nset AT91SAM9261_SRAM_BASE\t0x00300000\t;# Internal SRAM base address\nset AT91SAM9261_SRAM_SIZE\t0x00028000\t;# Internal SRAM size (160Kb)\n\nset AT91SAM9261_ROM_BASE\t0x00400000\t;# Internal ROM base address\nset AT91SAM9261_ROM_SIZE\t0x00008000\t;# Internal ROM size (32Kb)\n\nset AT91SAM9261_UHP_BASE\t0x00500000\t;# USB Host controller\nset AT91SAM9261_LCDC_BASE\t0x00600000\t;# LDC controller\n\n#\n# Cpu Name\n#\nset AT91_CPU_NAME\t\"AT91SAM9261\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91sam9261_matrix.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset AT91_MATRIX_MCFG\t[expr {$AT91_MATRIX + 0x00}]\t;# Master Configuration Register #\nset\t\tAT91_MATRIX_RCB0\t[expr {1 << 0}]\t\t;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)\nset\t\tAT91_MATRIX_RCB1\t[expr {1 << 1}]\t\t;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)\n\nset AT91_MATRIX_SCFG0\t[expr {$AT91_MATRIX + 0x04}]\t;# Slave Configuration Register 0\nset AT91_MATRIX_SCFG1\t[expr {$AT91_MATRIX + 0x08}]\t;# Slave Configuration Register 1\nset AT91_MATRIX_SCFG2\t[expr {$AT91_MATRIX + 0x0C}]\t;# Slave Configuration Register 2\nset AT91_MATRIX_SCFG3\t[expr {$AT91_MATRIX + 0x10}]\t;# Slave Configuration Register 3\nset AT91_MATRIX_SCFG4\t[expr {$AT91_MATRIX + 0x14}]\t;# Slave Configuration Register 4\nset\t\tAT91_MATRIX_SLOT_CYCLE\t\t[expr {0xff << 0}]\t;# Maximum Number of Allowed Cycles for a Burst\nset\t\tAT91_MATRIX_DEFMSTR_TYPE\t[expr {3    << 16}]\t;# Default Master Type\nset\t\t\tAT91_MATRIX_DEFMSTR_TYPE_NONE\t[expr {0 << 16}]\nset\t\t\tAT91_MATRIX_DEFMSTR_TYPE_LAST\t[expr {1 << 16}]\nset\t\t\tAT91_MATRIX_DEFMSTR_TYPE_FIXED\t[expr {2 << 16}]\nset\t\tAT91_MATRIX_FIXED_DEFMSTR\t[expr {7    << 18}]\t;# Fixed Index of Default Master\n\nset AT91_MATRIX_TCR\t\t[expr {$AT91_MATRIX + 0x24}]\t;# TCM Configuration Register\nset\t\tAT91_MATRIX_ITCM_SIZE\t\t[expr {0xf << 0}]\t;# Size of ITCM enabled memory block\nset\t\t\tAT91_MATRIX_ITCM_0\t\t[expr {0 << 0}]\nset\t\t\tAT91_MATRIX_ITCM_16\t\t[expr {5 << 0}]\nset\t\t\tAT91_MATRIX_ITCM_32\t\t[expr {6 << 0}]\nset\t\t\tAT91_MATRIX_ITCM_64\t\t[expr {7 << 0}]\nset\t\tAT91_MATRIX_DTCM_SIZE\t\t[expr {0xf << 4}]\t;# Size of DTCM enabled memory block\nset\t\t\tAT91_MATRIX_DTCM_0\t\t[expr {0 << 4}]\nset\t\t\tAT91_MATRIX_DTCM_16\t\t[expr {5 << 4}]\nset\t\t\tAT91_MATRIX_DTCM_32\t\t[expr {6 << 4}]\nset\t\t\tAT91_MATRIX_DTCM_64\t\t[expr {7 << 4}]\n\nset AT91_MATRIX_EBICSA\t[expr {$AT91_MATRIX + 0x30}]\t;# EBI Chip Select Assignment Register\nset\t\tAT91_MATRIX_CS1A\t\t[expr {1 << 1}]\t;# Chip Select 1 Assignment\nset\t\t\tAT91_MATRIX_CS1A_SMC\t\t[expr {0 << 1}]\nset\t\t\tAT91_MATRIX_CS1A_SDRAMC\t\t[expr {1 << 1}]\nset\t\tAT91_MATRIX_CS3A\t\t[expr {1 << 3}]\t;# Chip Select 3 Assignment\nset\t\t\tAT91_MATRIX_CS3A_SMC\t\t[expr {0 << 3}]\nset\t\t\tAT91_MATRIX_CS3A_SMC_SMARTMEDIA\t[expr {1 << 3}]\nset\t\tAT91_MATRIX_CS4A\t\t[expr {1 << 4}]\t;# Chip Select 4 Assignment\nset\t\t\tAT91_MATRIX_CS4A_SMC\t\t[expr {0 << 4}]\nset\t\t\tAT91_MATRIX_CS4A_SMC_CF1\t[expr {1 << 4}]\nset\t\tAT91_MATRIX_CS5A\t\t[expr {1 << 5}]\t;# Chip Select 5 Assignment\nset\t\t\tAT91_MATRIX_CS5A_SMC\t\t[expr {0 << 5}]\nset\t\t\tAT91_MATRIX_CS5A_SMC_CF2\t[expr {1 << 5}]\nset\t\tAT91_MATRIX_DBPUC\t\t[expr {1 << 8}]\t;# Data Bus Pull-up Configuration\n\nset AT91_MATRIX_USBPUCR\t[expr {$AT91_MATRIX + 0x34}]\t;# USB Pad Pull-Up Control Register\nset\t\tAT91_MATRIX_USBPUCR_PUON\t[expr {1 << 30}]\t;# USB Device PAD Pull-up Enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91sam9263.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Peripheral identifiers/interrupts.\n#\nset AT91_ID_FIQ\t\t0\t;# Advanced Interrupt Controller (FIQ)\nset AT91_ID_SYS\t\t1\t;# System Peripherals\nset AT91SAM9263_ID_PIOA\t2\t;# Parallel IO Controller A\nset AT91SAM9263_ID_PIOB\t3\t;# Parallel IO Controller B\nset AT91SAM9263_ID_PIOCDE\t4\t;# Parallel IO Controller C, D and E\nset AT91SAM9263_ID_US0\t7\t;# USART 0\nset AT91SAM9263_ID_US1\t8\t;# USART 1\nset AT91SAM9263_ID_US2\t9\t;# USART 2\nset AT91SAM9263_ID_MCI0\t10\t;# Multimedia Card Interface 0\nset AT91SAM9263_ID_MCI1\t11\t;# Multimedia Card Interface 1\nset AT91SAM9263_ID_CAN\t12\t;# CAN\nset AT91SAM9263_ID_TWI\t13\t;# Two-Wire Interface\nset AT91SAM9263_ID_SPI0\t14\t;# Serial Peripheral Interface 0\nset AT91SAM9263_ID_SPI1\t15\t;# Serial Peripheral Interface 1\nset AT91SAM9263_ID_SSC0\t16\t;# Serial Synchronous Controller 0\nset AT91SAM9263_ID_SSC1\t17\t;# Serial Synchronous Controller 1\nset AT91SAM9263_ID_AC97C\t18\t;# AC97 Controller\nset AT91SAM9263_ID_TCB\t19\t;# Timer Counter 0, 1 and 2\nset AT91SAM9263_ID_PWMC\t20\t;# Pulse Width Modulation Controller\nset AT91SAM9263_ID_EMAC\t21\t;# Ethernet\nset AT91SAM9263_ID_2DGE\t23\t;# 2D Graphic Engine\nset AT91SAM9263_ID_UDP\t24\t;# USB Device Port\nset AT91SAM9263_ID_ISI\t25\t;# Image Sensor Interface\nset AT91SAM9263_ID_LCDC\t26\t;# LCD Controller\nset AT91SAM9263_ID_DMA\t27\t;# DMA Controller\nset AT91SAM9263_ID_UHP\t29\t;# USB Host port\nset AT91SAM9263_ID_IRQ0\t30\t;# Advanced Interrupt Controller (IRQ0)\nset AT91SAM9263_ID_IRQ1\t31\t;# Advanced Interrupt Controller (IRQ1)\n\n\n#\n# User Peripheral physical base addresses.\n#\nset AT91SAM9263_BASE_UDP\t\t0xfff78000\nset AT91SAM9263_BASE_TCB0\t\t0xfff7c000\nset AT91SAM9263_BASE_TC0\t\t0xfff7c000\nset AT91SAM9263_BASE_TC1\t\t0xfff7c040\nset AT91SAM9263_BASE_TC2\t\t0xfff7c080\nset AT91SAM9263_BASE_MCI0\t\t0xfff80000\nset AT91SAM9263_BASE_MCI1\t\t0xfff84000\nset AT91SAM9263_BASE_TWI\t\t0xfff88000\nset AT91SAM9263_BASE_US0\t\t0xfff8c000\nset AT91SAM9263_BASE_US1\t\t0xfff90000\nset AT91SAM9263_BASE_US2\t\t0xfff94000\nset AT91SAM9263_BASE_SSC0\t\t0xfff98000\nset AT91SAM9263_BASE_SSC1\t\t0xfff9c000\nset AT91SAM9263_BASE_AC97C\t\t0xfffa0000\nset AT91SAM9263_BASE_SPI0\t\t0xfffa4000\nset AT91SAM9263_BASE_SPI1\t\t0xfffa8000\nset AT91SAM9263_BASE_CAN\t\t0xfffac000\nset AT91SAM9263_BASE_PWMC\t\t0xfffb8000\nset AT91SAM9263_BASE_EMAC\t\t0xfffbc000\nset AT91SAM9263_BASE_ISI\t\t0xfffc4000\nset AT91SAM9263_BASE_2DGE\t\t0xfffc8000\nset AT91_BASE_SYS\t\t\t0xffffe000\n\n#\n# System Peripherals (offset from AT91_BASE_SYS)\n#\nset AT91_ECC0\t\t0xffffe000\nset AT91_SDRAMC0\t0xffffe200\nset AT91_SMC0\t\t0xffffe400\nset AT91_ECC1\t\t0xffffe600\nset AT91_SDRAMC1\t0xffffe800\nset AT91_SMC1\t\t0xffffea00\nset AT91_MATRIX\t\t0xffffec00\nset AT91_CCFG\t\t0xffffed10\nset AT91_DBGU\t\t0xffffee00\nset AT91_AIC\t\t0xfffff000\nset AT91_PIOA\t\t0xfffff200\nset AT91_PIOB\t\t0xfffff400\nset AT91_PIOC\t\t0xfffff600\nset AT91_PIOD\t\t0xfffff800\nset AT91_PIOE\t\t0xfffffa00\nset AT91_PMC\t\t0xfffffc00\nset AT91_RSTC\t\t0xfffffd00\nset AT91_SHDWC\t\t0xfffffd10\nset AT91_RTT0\t\t0xfffffd20\nset AT91_PIT\t\t0xfffffd30\nset AT91_WDT\t\t0xfffffd40\nset AT91_RTT1\t\t0xfffffd50\nset AT91_GPBR\t\t0xfffffd60\n\nset AT91_USART0\t$AT91SAM9263_BASE_US0\nset AT91_USART1\t$AT91SAM9263_BASE_US1\nset AT91_USART2\t$AT91SAM9263_BASE_US2\n\nset AT91_SMC\t$AT91_SMC0\nset AT91_SDRAMC\t$AT91_SDRAMC0\n\n#\n# Internal Memory.\n#\nset AT91SAM9263_SRAM0_BASE\t0x00300000\t;# Internal SRAM 0 base address\nset AT91SAM9263_SRAM0_SIZE\t0x00014000\t;# Internal SRAM 0 size (80Kb)\n\nset AT91SAM9263_ROM_BASE\t0x00400000\t;# Internal ROM base address\nset AT91SAM9263_ROM_SIZE\t0x00020000\t;# Internal ROM size (128Kb)\n\nset AT91SAM9263_SRAM1_BASE\t0x00500000\t;# Internal SRAM 1 base address\nset AT91SAM9263_SRAM1_SIZE\t0x00004000\t;# Internal SRAM 1 size (16Kb)\n\nset AT91SAM9263_LCDC_BASE\t0x00700000\t;# LCD Controller\nset AT91SAM9263_DMAC_BASE\t0x00800000\t;# DMA Controller\nset AT91SAM9263_UHP_BASE\t0x00a00000\t;# USB Host controller\n\n#\n# Cpu Name\n#\nset AT91_CPU_NAME\t\"AT91SAM9263\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91sam9263_matrix.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset AT91_MATRIX_MCFG0\t[expr {$AT91_MATRIX + 0x00}]\t;# Master Configuration Register 0\nset AT91_MATRIX_MCFG1\t[expr {$AT91_MATRIX + 0x04}]\t;# Master Configuration Register 1\nset AT91_MATRIX_MCFG2\t[expr {$AT91_MATRIX + 0x08}]\t;# Master Configuration Register 2\nset AT91_MATRIX_MCFG3\t[expr {$AT91_MATRIX + 0x0C}]\t;# Master Configuration Register 3\nset AT91_MATRIX_MCFG4\t[expr {$AT91_MATRIX + 0x10}]\t;# Master Configuration Register 4\nset AT91_MATRIX_MCFG5\t[expr {$AT91_MATRIX + 0x14}]\t;# Master Configuration Register 5\nset AT91_MATRIX_MCFG6\t[expr {$AT91_MATRIX + 0x18}]\t;# Master Configuration Register 6\nset AT91_MATRIX_MCFG7\t[expr {$AT91_MATRIX + 0x1C}]\t;# Master Configuration Register 7\nset AT91_MATRIX_MCFG8\t[expr {$AT91_MATRIX + 0x20}]\t;# Master Configuration Register 8\nset\t\tAT91_MATRIX_ULBT\t[expr {7 << 0}]\t;# Undefined Length Burst Type\nset\t\t\tAT91_MATRIX_ULBT_INFINITE\t[expr {0 << 0}]\nset\t\t\tAT91_MATRIX_ULBT_SINGLE\t\t[expr {1 << 0}]\nset\t\t\tAT91_MATRIX_ULBT_FOUR\t\t[expr {2 << 0}]\nset\t\t\tAT91_MATRIX_ULBT_EIGHT\t\t[expr {3 << 0}]\nset\t\t\tAT91_MATRIX_ULBT_SIXTEEN\t[expr {4 << 0}]\n\nset AT91_MATRIX_SCFG0\t[expr {$AT91_MATRIX + 0x40}]\t;# Slave Configuration Register 0\nset AT91_MATRIX_SCFG1\t[expr {$AT91_MATRIX + 0x44}]\t;# Slave Configuration Register 1\nset AT91_MATRIX_SCFG2\t[expr {$AT91_MATRIX + 0x48}]\t;# Slave Configuration Register 2\nset AT91_MATRIX_SCFG3\t[expr {$AT91_MATRIX + 0x4C}]\t;# Slave Configuration Register 3\nset AT91_MATRIX_SCFG4\t[expr {$AT91_MATRIX + 0x50}]\t;# Slave Configuration Register 4\nset AT91_MATRIX_SCFG5\t[expr {$AT91_MATRIX + 0x54}]\t;# Slave Configuration Register 5\nset AT91_MATRIX_SCFG6\t[expr {$AT91_MATRIX + 0x58}]\t;# Slave Configuration Register 6\nset AT91_MATRIX_SCFG7\t[expr {$AT91_MATRIX + 0x5C}]\t;# Slave Configuration Register 7\nset\t\tAT91_MATRIX_SLOT_CYCLE\t\t[expr {0xff << 0}]\t;# Maximum Number of Allowed Cycles for a Burst\nset\t\tAT91_MATRIX_DEFMSTR_TYPE\t[expr {3    << 16}]\t;# Default Master Type\nset\t\t\tAT91_MATRIX_DEFMSTR_TYPE_NONE\t[expr {0 << 16}]\nset\t\t\tAT91_MATRIX_DEFMSTR_TYPE_LAST\t[expr {1 << 16}]\nset\t\t\tAT91_MATRIX_DEFMSTR_TYPE_FIXED\t[expr {2 << 16}]\nset\t\tAT91_MATRIX_FIXED_DEFMSTR\t[expr {0xf  << 18}]\t;# Fixed Index of Default Master\nset\t\tAT91_MATRIX_ARBT\t\t[expr {3    << 24}]\t;# Arbitration Type\nset\t\t\tAT91_MATRIX_ARBT_ROUND_ROBIN\t[expr {0 << 24}]\nset\t\t\tAT91_MATRIX_ARBT_FIXED_PRIORITY\t[expr {1 << 24}]\n\nset AT91_MATRIX_PRAS0\t[expr {$AT91_MATRIX + 0x80}]\t;# Priority Register A for Slave 0\nset AT91_MATRIX_PRBS0\t[expr {$AT91_MATRIX + 0x84}]\t;# Priority Register B for Slave 0\nset AT91_MATRIX_PRAS1\t[expr {$AT91_MATRIX + 0x88}]\t;# Priority Register A for Slave 1\nset AT91_MATRIX_PRBS1\t[expr {$AT91_MATRIX + 0x8C}]\t;# Priority Register B for Slave 1\nset AT91_MATRIX_PRAS2\t[expr {$AT91_MATRIX + 0x90}]\t;# Priority Register A for Slave 2\nset AT91_MATRIX_PRBS2\t[expr {$AT91_MATRIX + 0x94}]\t;# Priority Register B for Slave 2\nset AT91_MATRIX_PRAS3\t[expr {$AT91_MATRIX + 0x98}]\t;# Priority Register A for Slave 3\nset AT91_MATRIX_PRBS3\t[expr {$AT91_MATRIX + 0x9C}]\t;# Priority Register B for Slave 3\nset AT91_MATRIX_PRAS4\t[expr {$AT91_MATRIX + 0xA0}]\t;# Priority Register A for Slave 4\nset AT91_MATRIX_PRBS4\t[expr {$AT91_MATRIX + 0xA4}]\t;# Priority Register B for Slave 4\nset AT91_MATRIX_PRAS5\t[expr {$AT91_MATRIX + 0xA8}]\t;# Priority Register A for Slave 5\nset AT91_MATRIX_PRBS5\t[expr {$AT91_MATRIX + 0xAC}]\t;# Priority Register B for Slave 5\nset AT91_MATRIX_PRAS6\t[expr {$AT91_MATRIX + 0xB0}]\t;# Priority Register A for Slave 6\nset AT91_MATRIX_PRBS6\t[expr {$AT91_MATRIX + 0xB4}]\t;# Priority Register B for Slave 6\nset AT91_MATRIX_PRAS7\t[expr {$AT91_MATRIX + 0xB8}]\t;# Priority Register A for Slave 7\nset AT91_MATRIX_PRBS7\t[expr {$AT91_MATRIX + 0xBC}]\t;# Priority Register B for Slave 7\nset\t\tAT91_MATRIX_M0PR\t\t[expr {3 << 0}]\t\t;# Master 0 Priority\nset\t\tAT91_MATRIX_M1PR\t\t[expr {3 << 4}]\t\t;# Master 1 Priority\nset\t\tAT91_MATRIX_M2PR\t\t[expr {3 << 8}]\t\t;# Master 2 Priority\nset\t\tAT91_MATRIX_M3PR\t\t[expr {3 << 12}]\t;# Master 3 Priority\nset\t\tAT91_MATRIX_M4PR\t\t[expr {3 << 16}]\t;# Master 4 Priority\nset\t\tAT91_MATRIX_M5PR\t\t[expr {3 << 20}]\t;# Master 5 Priority\nset\t\tAT91_MATRIX_M6PR\t\t[expr {3 << 24}]\t;# Master 6 Priority\nset\t\tAT91_MATRIX_M7PR\t\t[expr {3 << 28}]\t;# Master 7 Priority\nset\t\tAT91_MATRIX_M8PR\t\t[expr {3 << 0}]\t\t;# Master 8 Priority (in Register B)\n\nset AT91_MATRIX_MRCR\t[expr {$AT91_MATRIX + 0x100}]\t;# Master Remap Control Register\nset\t\tAT91_MATRIX_RCB0\t\t[expr {1 << 0}]\t;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)\nset\t\tAT91_MATRIX_RCB1\t\t[expr {1 << 1}]\t;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)\nset\t\tAT91_MATRIX_RCB2\t\t[expr {1 << 2}]\nset\t\tAT91_MATRIX_RCB3\t\t[expr {1 << 3}]\nset\t\tAT91_MATRIX_RCB4\t\t[expr {1 << 4}]\nset\t\tAT91_MATRIX_RCB5\t\t[expr {1 << 5}]\nset\t\tAT91_MATRIX_RCB6\t\t[expr {1 << 6}]\nset\t\tAT91_MATRIX_RCB7\t\t[expr {1 << 7}]\nset\t\tAT91_MATRIX_RCB8\t\t[expr {1 << 8}]\n\nset AT91_MATRIX_TCMR\t[expr {$AT91_MATRIX + 0x114}]\t;# TCM Configuration Register\nset\t\tAT91_MATRIX_ITCM_SIZE\t\t[expr {0xf << 0}]\t;# Size of ITCM enabled memory block\nset\t\t\tAT91_MATRIX_ITCM_0\t\t[expr {0 << 0}]\nset\t\t\tAT91_MATRIX_ITCM_16\t\t[expr {5 << 0}]\nset\t\t\tAT91_MATRIX_ITCM_32\t\t[expr {6 << 0}]\nset\t\tAT91_MATRIX_DTCM_SIZE\t\t[expr {0xf << 4}]\t;# Size of DTCM enabled memory block\nset\t\t\tAT91_MATRIX_DTCM_0\t\t[expr {0 << 4}]\nset\t\t\tAT91_MATRIX_DTCM_16\t\t[expr {5 << 4}]\nset\t\t\tAT91_MATRIX_DTCM_32\t\t[expr {6 << 4}]\n\nset AT91_MATRIX_EBI0CSA\t[expr {$AT91_MATRIX + 0x120}]\t;# EBI0 Chip Select Assignment Register\nset\t\tAT91_MATRIX_EBI0_CS1A\t\t[expr {1 << 1}]\t;# Chip Select 1 Assignment\nset\t\t\tAT91_MATRIX_EBI0_CS1A_SMC\t\t[expr {0 << 1}]\nset\t\t\tAT91_MATRIX_EBI0_CS1A_SDRAMC\t\t[expr {1 << 1}]\nset\t\tAT91_MATRIX_EBI0_CS3A\t\t[expr {1 << 3}]\t;# Chip Select 3 Assignmen\nset\t\t\tAT91_MATRIX_EBI0_CS3A_SMC\t\t[expr {0 << 3}]\nset\t\t\tAT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA\t[expr {1 << 3}]\nset\t\tAT91_MATRIX_EBI0_CS4A\t\t[expr {1 << 4}]\t;# Chip Select 4 Assignment\nset\t\t\tAT91_MATRIX_EBI0_CS4A_SMC\t\t[expr {0 << 4}]\nset\t\t\tAT91_MATRIX_EBI0_CS4A_SMC_CF1\t\t[expr {1 << 4}]\nset\t\tAT91_MATRIX_EBI0_CS5A\t\t[expr {1 << 5}]\t;# Chip Select 5 Assignment\nset\t\t\tAT91_MATRIX_EBI0_CS5A_SMC\t\t[expr {0 << 5}]\nset\t\t\tAT91_MATRIX_EBI0_CS5A_SMC_CF2\t\t[expr {1 << 5}]\nset\t\tAT91_MATRIX_EBI0_DBPUC\t\t[expr {1 << 8}]\t;# Data Bus Pull-up Configuration\nset\t\tAT91_MATRIX_EBI0_VDDIOMSEL\t[expr {1 << 16}]\t;# Memory voltage selection\nset\t\t\tAT91_MATRIX_EBI0_VDDIOMSEL_1_8V\t\t[expr {0 << 16}]\nset\t\t\tAT91_MATRIX_EBI0_VDDIOMSEL_3_3V\t\t[expr {1 << 16}]\n\nset AT91_MATRIX_EBI1CSA\t[expr {$AT91_MATRIX + 0x124}]\t;# EBI1 Chip Select Assignment Register\nset\t\tAT91_MATRIX_EBI1_CS1A\t\t[expr {1 << 1}]\t;# Chip Select 1 Assignment\nset\t\t\tAT91_MATRIX_EBI1_CS1A_SMC\t\t[expr {0 << 1}]\nset\t\t\tAT91_MATRIX_EBI1_CS1A_SDRAMC\t\t[expr {1 << 1}]\nset\t\tAT91_MATRIX_EBI1_CS2A\t\t[expr {1 << 3}]\t;# Chip Select 3 Assignment\nset\t\t\tAT91_MATRIX_EBI1_CS2A_SMC\t\t[expr {0 << 3}]\nset\t\t\tAT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA\t[expr {1 << 3}]\nset\t\tAT91_MATRIX_EBI1_DBPUC\t\t[expr {1 << 8}]\t;# Data Bus Pull-up Configuration\nset\t\tAT91_MATRIX_EBI1_VDDIOMSEL\t[expr {1 << 16}]\t;# Memory voltage selection\nset\t\t\tAT91_MATRIX_EBI1_VDDIOMSEL_1_8V\t\t[expr {0 << 16}]\nset\t\t\tAT91_MATRIX_EBI1_VDDIOMSEL_3_3V\t\t[expr {1 << 16}]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_init.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nuplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]]\nuplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]]\n\nproc at91sam9_reset_start { } {\n\n\tarm7_9 fast_memory_access disable\n\n\tjtag_rclk 8\n\thalt\n\twait_halt 10000\n\tset rstc_mr_val $::AT91_RSTC_KEY\n\tset rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]\n\tset rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]\n\tmww $::AT91_RSTC_MR $rstc_mr_val\t;# RSTC_MR : enable user reset.\n}\n\nproc at91sam9_reset_init { config } {\n\n\tmww $::AT91_WDT_MR $config(wdt_mr_val)\t;# disable watchdog\n\n\tset ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]\n\n\tmww $::AT91_CKGR_MOR $ckgr_mor\t;# CKGR_MOR - enable main osc.\n\twhile { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 }\n\n\tset pllar_val\t$::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog\n\tset pllar_val\t[expr {$pllar_val | $::AT91_PMC_OUT}]\n\tset pllar_val\t[expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]\n\tset pllar_val\t[expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}]\n\tset pllar_val\t[expr {$pllar_val | $config(master_pll_div)}]\n\n\tmww $::AT91_CKGR_PLLAR $pllar_val\t ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz\n\twhile { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 }\n\n\t;# PCK/2 = MCK Master Clock from PLLA\n\tset mckr_val\t$::AT91_PMC_CSS_PLLA\n\tset mckr_val\t[expr {$mckr_val | $::AT91_PMC_PRES_1}]\n\tset mckr_val\t[expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]\n\tset mckr_val\t[expr {$mckr_val | $::AT91_PMC_PDIV_1}]\n\n\tmww $::AT91_PMC_MCKR $mckr_val\t;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)\n\twhile { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 }\n\n\t## switch JTAG clock to highspeed clock\n\tjtag_rclk 0\n\n\tarm7_9 dcc_downloads enable\t;# Enable faster DCC downloads\n\tarm7_9 fast_memory_access enable\n\n\tset rstc_mr_val $::AT91_RSTC_KEY\n\tset rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]\n\tmww $::AT91_RSTC_MR $rstc_mr_val\t;# user reset enable\n\n\tif { [info exists config(sdram_piod)] } {\n\t\tset pdr_addr\t[expr {$::AT91_PIOD + $::PIO_PDR}]\n\t\tset pudr_addr\t[expr {$::AT91_PIOD + $::PIO_PUDR}]\n\t\tset asr_addr\t[expr {$::AT91_PIOD + $::PIO_ASR}]\n\t\tmww $pdr_addr 0xffff0000\t\t\t\t;# define PDC[31:16] as DATA[31:16]\n\t\tmww $pudr_addr 0xffff0000\t\t\t\t;# no pull-up for D[31:16]\n\t\tmww $asr_addr 0xffff0000\n\t} else {\n\t\tset pdr_addr\t[expr {$::AT91_PIOC + $::PIO_PDR}]\n\t\tset pudr_addr\t[expr {$::AT91_PIOC + $::PIO_PUDR}]\n\t\tmww $pdr_addr 0xffff0000\t\t\t\t;# define PDC[31:16] as DATA[31:16]\n\t\tmww $pudr_addr 0xffff0000\t\t\t\t;# no pull-up for D[31:16]\n\t}\n\n\tmww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)\n\tmww $::AT91_SDRAMC_MR\t$::AT91_SDRAMC_MODE_NORMAL\t;# SDRAMC_MR Mode register\n\tmww $::AT91_SDRAMC_TR\t$config(sdram_tr_val)\t\t;# SDRAMC_TR - Refresh Timer register\n\tmww $::AT91_SDRAMC_CR\t$config(sdram_cr_val)\t\t;# SDRAMC_CR - Configuration register\n\tmww $::AT91_SDRAMC_MDR\t$::AT91_SDRAMC_MD_SDRAM\t\t;# Memory Device Register -> SDRAM\n\tmww $::AT91_SDRAMC_MR\t$::AT91_SDRAMC_MODE_PRECHARGE\t;# SDRAMC_MR\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $::AT91_SDRAMC_MR\t$::AT91_SDRAMC_MODE_REFRESH\t;# SDRC_MR\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $::AT91_SDRAMC_MR\t$::AT91_SDRAMC_MODE_LMR\t\t;# SDRC_MR\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $::AT91_SDRAMC_MR\t$::AT91_SDRAMC_MODE_NORMAL\t;# SDRC_MR\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\tmww $::AT91_SDRAMC_TR\t1200\t\t\t\t;# SDRAM_TR\n\tmww $config(sdram_base)\t0\t\t\t\t;# SDRAM_BASE\n\n\tmww $::AT91_MATRIX 0xf\t\t;# MATRIX_MCFG - REMAP all masters\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_sdramc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# SDRAM Controller (SDRAMC) registers\nset AT91_SDRAMC_MR\t\t[expr {$AT91_SDRAMC + 0x00}]\t;# SDRAM Controller Mode Register\nset\t\tAT91_SDRAMC_MODE\t[expr {0xf << 0}]\t;# Command Mode\nset\t\t\tAT91_SDRAMC_MODE_NORMAL\t\t0\nset\t\t\tAT91_SDRAMC_MODE_NOP\t\t1\nset\t\t\tAT91_SDRAMC_MODE_PRECHARGE\t2\nset\t\t\tAT91_SDRAMC_MODE_LMR\t\t3\nset\t\t\tAT91_SDRAMC_MODE_REFRESH\t4\nset\t\t\tAT91_SDRAMC_MODE_EXT_LMR\t5\nset\t\t\tAT91_SDRAMC_MODE_DEEP\t\t6\n\nset AT91_SDRAMC_TR\t\t[expr {$AT91_SDRAMC + 0x04}]\t;# SDRAM Controller Refresh Timer Register\nset\t\tAT91_SDRAMC_COUNT\t[expr {0xfff << 0}]\t\t;# Refresh Timer Counter\n\nset AT91_SDRAMC_CR\t\t[expr {$AT91_SDRAMC + 0x08}]\t;# SDRAM Controller Configuration Register\nset\t\tAT91_SDRAMC_NC\t\t[expr {3 << 0}]\t\t;# Number of Column Bits\nset\t\t\tAT91_SDRAMC_NC_8\t[expr {0 << 0}]\nset\t\t\tAT91_SDRAMC_NC_9\t[expr {1 << 0}]\nset\t\t\tAT91_SDRAMC_NC_10\t[expr {2 << 0}]\nset\t\t\tAT91_SDRAMC_NC_11\t[expr {3 << 0}]\nset\t\tAT91_SDRAMC_NR\t\t[expr {3 << 2}]\t\t;# Number of Row Bits\nset\t\t\tAT91_SDRAMC_NR_11\t[expr {0 << 2}]\nset\t\t\tAT91_SDRAMC_NR_12\t[expr {1 << 2}]\nset\t\t\tAT91_SDRAMC_NR_13\t[expr {2 << 2}]\nset\t\tAT91_SDRAMC_NB\t\t[expr {1 << 4}]\t\t;# Number of Banks\nset\t\t\tAT91_SDRAMC_NB_2\t[expr {0 << 4}]\nset\t\t\tAT91_SDRAMC_NB_4\t[expr {1 << 4}]\nset\t\tAT91_SDRAMC_CAS\t\t[expr {3 << 5}]\t\t;# CAS Latency\nset\t\t\tAT91_SDRAMC_CAS_1\t[expr {1 << 5}]\nset\t\t\tAT91_SDRAMC_CAS_2\t[expr {2 << 5}]\nset\t\t\tAT91_SDRAMC_CAS_3\t[expr {3 << 5}]\nset\t\tAT91_SDRAMC_DBW\t\t[expr {1 << 7}]\t\t;# Data Bus Width\nset\t\t\tAT91_SDRAMC_DBW_32\t[expr {0 << 7}]\nset\t\t\tAT91_SDRAMC_DBW_16\t[expr {1 << 7}]\nset\t\tAT91_SDRAMC_TWR\t\t[expr {0xf <<  8}]\t\t;# Write Recovery Delay\nset\t\tAT91_SDRAMC_TRC\t\t[expr {0xf << 12}]\t\t;# Row Cycle Delay\nset\t\tAT91_SDRAMC_TRP\t\t[expr {0xf << 16}]\t\t;# Row Precharge Delay\nset\t\tAT91_SDRAMC_TRCD\t[expr {0xf << 20}]\t\t;# Row to Column Delay\nset\t\tAT91_SDRAMC_TRAS\t[expr {0xf << 24}]\t\t;# Active to Precharge Delay\nset\t\tAT91_SDRAMC_TXSR\t[expr {0xf << 28}]\t\t;# Exit Self Refresh to Active Delay\n\nset AT91_SDRAMC_LPR\t\t[expr {$AT91_SDRAMC + 0x10}]\t;# SDRAM Controller Low Power Register\nset\t\tAT91_SDRAMC_LPCB\t\t[expr {3 << 0}]\t;# Low-power Configurations\nset\t\t\tAT91_SDRAMC_LPCB_DISABLE\t\t0\nset\t\t\tAT91_SDRAMC_LPCB_SELF_REFRESH\t\t1\nset\t\t\tAT91_SDRAMC_LPCB_POWER_DOWN\t\t2\nset\t\t\tAT91_SDRAMC_LPCB_DEEP_POWER_DOWN\t3\nset\t\tAT91_SDRAMC_PASR\t\t[expr {7 << 4}]\t;# Partial Array Self Refresh\nset\t\tAT91_SDRAMC_TCSR\t\t[expr {3 << 8}]\t;# Temperature Compensated Self Refresh\nset\t\tAT91_SDRAMC_DS\t\t\t[expr {3 << 10}]\t;# Drive Strength\nset\t\tAT91_SDRAMC_TIMEOUT\t\t[expr {3 << 12}]\t;# Time to define when Low Power Mode is enabled\nset\t\t\tAT91_SDRAMC_TIMEOUT_0_CLK_CYCLES\t[expr {0 << 12}]\nset\t\t\tAT91_SDRAMC_TIMEOUT_64_CLK_CYCLES\t[expr {1 << 12}]\nset\t\t\tAT91_SDRAMC_TIMEOUT_128_CLK_CYCLES\t[expr {2 << 12}]\n\nset AT91_SDRAMC_IER\t\t[expr {$AT91_SDRAMC + 0x14}]\t;# SDRAM Controller Interrupt Enable Register\nset AT91_SDRAMC_IDR\t\t[expr {$AT91_SDRAMC + 0x18}]\t;# SDRAM Controller Interrupt Disable Register\nset AT91_SDRAMC_IMR\t\t[expr {$AT91_SDRAMC + 0x1C}]\t;# SDRAM Controller Interrupt Mask Register\nset AT91_SDRAMC_ISR\t\t[expr {$AT91_SDRAMC + 0x20}]\t;# SDRAM Controller Interrupt Status Register\nset\t\tAT91_SDRAMC_RES\t\t[expr {1 << 0}]\t\t;# Refresh Error Status\n\nset AT91_SDRAMC_MDR\t\t[expr {$AT91_SDRAMC + 0x24}]\t;# SDRAM Memory Device Register\nset\t\tAT91_SDRAMC_MD\t\t[expr {3 << 0}]\t\t;# Memory Device Type\nset\t\t\tAT91_SDRAMC_MD_SDRAM\t\t0\nset\t\t\tAT91_SDRAMC_MD_LOW_POWER_SDRAM\t1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/at91sam9_smc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset\t\tAT91_SMC_READMODE\t[expr {1 <<  0}]\t\t;# Read Mode\nset\t\tAT91_SMC_WRITEMODE\t[expr {1 <<  1}]\t\t;# Write Mode\nset\t\tAT91_SMC_EXNWMODE\t[expr {3 <<  4}]\t\t;# NWAIT Mode\nset\t\t\tAT91_SMC_EXNWMODE_DISABLE\t[expr {0 << 4}]\nset\t\t\tAT91_SMC_EXNWMODE_FROZEN\t[expr {2 << 4}]\nset\t\t\tAT91_SMC_EXNWMODE_READY\t\t[expr {3 << 4}]\nset\t\tAT91_SMC_BAT\t\t[expr {1 <<  8}]\t\t;# Byte Access Type\nset\t\t\tAT91_SMC_BAT_SELECT\t\t[expr {0 << 8}]\nset\t\t\tAT91_SMC_BAT_WRITE\t\t[expr {1 << 8}]\nset\t\tAT91_SMC_DBW\t\t[expr {3 << 12}]\t\t;# Data Bus Width */\nset\t\t\tAT91_SMC_DBW_8\t\t\t[expr {0 << 12}]\nset\t\t\tAT91_SMC_DBW_16\t\t\t[expr {1 << 12}]\nset\t\t\tAT91_SMC_DBW_32\t\t\t[expr {2 << 12}]\nset\t\tAT91_SMC_TDFMODE\t[expr {1 << 20}]\t\t;# TDF Optimization - Enabled\nset\t\tAT91_SMC_PMEN\t\t[expr {1 << 24}]\t\t;# Page Mode Enabled\nset\t\tAT91_SMC_PS\t\t[expr {3 << 28}]\t\t;# Page Size\nset\t\t\tAT91_SMC_PS_4\t\t\t[expr {0 << 28}]\nset\t\t\tAT91_SMC_PS_8\t\t\t[expr {1 << 28}]\nset\t\t\tAT91_SMC_PS_16\t\t\t[expr {2 << 28}]\nset\t\t\tAT91_SMC_PS_32\t\t\t[expr {3 << 28}]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/hardware.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# External Memory Map\nset AT91_CHIPSELECT_0\t0x10000000\nset AT91_CHIPSELECT_1\t0x20000000\nset AT91_CHIPSELECT_2\t0x30000000\nset AT91_CHIPSELECT_3\t0x40000000\nset AT91_CHIPSELECT_4\t0x50000000\nset AT91_CHIPSELECT_5\t0x60000000\nset AT91_CHIPSELECT_6\t0x70000000\nset AT91_CHIPSELECT_7\t0x80000000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/pmc.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif [info exists AT91C_MAINOSC_FREQ] {\n    # user set this... let it be.\n} {\n    # 18.432mhz is a common thing...\n    set AT91C_MAINOSC_FREQ 18432000\n}\nglobal AT91C_MAINOSC_FREQ\n\nif [info exists AT91C_SLOWOSC_FREQ] {\n    # user set this... let it be.\n} {\n    # 32khz is the norm\n    set AT91C_SLOWOSC_FREQ 32768\n}\nglobal AT91C_SLOWOSC_FREQ\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/rtt.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}]\nset RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}]\nset RTTC_RTVR [expr {$AT91C_BASE_RTTC + 0x08}]\nset RTTC_RTSR [expr {$AT91C_BASE_RTTC + 0x0c}]\nglobal RTTC_RTMR\nglobal RTTC_RTAR\nglobal RTTC_RTVR\nglobal RTTC_RTSR\n\nproc show_RTTC_RTMR_helper { NAME ADDR VAL } {\n    set rtpres [expr {$VAL & 0x0ffff}]\n    global BIT16 BIT17\n    if { $rtpres == 0 } {\n\tset rtpres 65536;\n    }\n    global AT91C_SLOWOSC_FREQ\n    # Nasty hack, make this a float by tacking a .0 on the end\n    # otherwise, jim makes the value an integer\n    set f [expr \"$AT91C_SLOWOSC_FREQ.0 / $rtpres.0\"]\n    echo [format \"\\tPrescale value: 0x%04x (%5d) => %f Hz\" $rtpres $rtpres $f]\n    if { $VAL & $BIT16 } {\n\techo \"\\tBit16 -> Alarm IRQ Enabled\"\n    } else {\n\techo \"\\tBit16 -> Alarm IRQ Disabled\"\n    }\n    if { $VAL & $BIT17 } {\n\techo \"\\tBit17 -> RTC Inc IRQ Enabled\"\n    } else {\n\techo \"\\tBit17 -> RTC Inc IRQ Disabled\"\n    }\n    # Bit 18 is write only.\n}\n\nproc show_RTTC_RTSR_helper { NAME ADDR VAL } {\n    global BIT0 BIT1\n    if { $VAL & $BIT0 } {\n\techo \"\\tBit0 -> ALARM PENDING\"\n    } else {\n\techo \"\\tBit0 -> alarm not pending\"\n    }\n    if { $VAL & $BIT1 } {\n\techo \"\\tBit0 -> RTINC PENDING\"\n    } else {\n\techo \"\\tBit0 -> rtinc not pending\"\n    }\n}\n\nproc show_RTTC { } {\n\n    show_mmr32_reg RTTC_RTMR\n    show_mmr32_reg RTTC_RTAR\n    show_mmr32_reg RTTC_RTVR\n    show_mmr32_reg RTTC_RTSR\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/sam9_smc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Setup register\n#\n# ncs_read_setup\n# nrd_setup\n# ncs_write_setup\n# set nwe_setup\n#\n#\n# Pulse register\n#\n# ncs_read_pulse\n# nrd_pulse\n# ncs_write_pulse\n# nwe_pulse\n#\n#\n# Cycle register\n#\n# read_cycle 0\n# write_cycle 0\n#\n#\n# Mode register\n#\n# mode\n# tdf_cycles\nproc sam9_smc_config { cs smc_config } {\n\t;# Setup Register for CS n\n\tset AT91_SMC_SETUP [expr {$::AT91_SMC + 0x00 + $cs * 0x10}]\n\tset val [expr {$smc_config(nwe_setup) << 0}]\n\tset val [expr {$val | $smc_config(ncs_write_setup) << 8}]\n\tset val [expr {$val | $smc_config(nrd_setup)) << 16}]\n\tset val [expr {$val | $smc_config(ncs_read_setup) << 24}]\n\tmww $AT91_SMC_SETUP $val\n\n\t;# Pulse Register for CS n\n\tset AT91_SMC_PULSE [expr {$::AT91_SMC + 0x04 + $cs * 0x10}]\n\tset val [expr {$smc_config(nwe_pulse) << 0}]\n\tset val [expr {$val | $smc_config(ncs_write_pulse) << 8}]\n\tset val [expr {$val | $smc_config(nrd_pulse) << 16}]\n\tset val [expr {$val | $smc_config(ncs_read_pulse) << 24}]\n\tmww $AT91_SMC_PULSE $val\n\n\t;# Cycle Register for CS n\n\tset AT91_SMC_CYCLE [expr {$::AT91_SMC + 0x08 + $cs * 0x10}]\n\tset val [expr {$smc_config(write_cycle) << 0}]\n\tset val [expr {$val | $smc_config(read_cycle) << 16}]\n\tmww $AT91_SMC_CYCLE $val\n\n\t;# Mode Register for CS n\n\tset AT91_SMC_MODE [expr {$::AT91_SMC + 0x0c + $cs * 0x10}]\n\tset val [expr {$smc_config(mode) << 0}]\n\tset val [expr {$val | $smc_config(tdf_cycles) << 16}]\n\tmww $AT91_SMC_MODE $val\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/atmel/at91/usarts.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# the DBGU and USARTs are 'almost' indentical'\nset DBGU_CR         [expr {$AT91C_BASE_DBGU + 0x00000000}]\nset DBGU_MR         [expr {$AT91C_BASE_DBGU + 0x00000004}]\nset DBGU_IER        [expr {$AT91C_BASE_DBGU + 0x00000008}]\nset DBGU_IDR        [expr {$AT91C_BASE_DBGU + 0x0000000C}]\nset DBGU_IMR        [expr {$AT91C_BASE_DBGU + 0x00000010}]\nset DBGU_CSR        [expr {$AT91C_BASE_DBGU + 0x00000014}]\nset DBGU_RHR        [expr {$AT91C_BASE_DBGU + 0x00000018}]\nset DBGU_THR        [expr {$AT91C_BASE_DBGU + 0x0000001C}]\nset DBGU_BRGR       [expr {$AT91C_BASE_DBGU + 0x00000020}]\n# no RTOR\n# no TTGR\n# no FIDI\n# no NER\nset DBGU_CIDR       [expr {$AT91C_BASE_DBGU + 0x00000040}]\nset DBGU_EXID       [expr {$AT91C_BASE_DBGU + 0x00000044}]\nset DBGU_FNTR       [expr {$AT91C_BASE_DBGU + 0x00000048}]\n\n\nset USx_CR           0x00000000\nset USx_MR           0x00000004\nset USx_IER          0x00000008\nset USx_IDR          0x0000000C\nset USx_IMR          0x00000010\nset USx_CSR          0x00000014\nset USx_RHR          0x00000018\nset USx_THR          0x0000001C\nset USx_BRGR         0x00000020\nset USx_RTOR         0x00000024\nset USx_TTGR         0x00000028\nset USx_FIDI         0x00000040\nset USx_NER          0x00000044\nset USx_IF           0x0000004C\n\n# Create all the uarts that exist..\n# we blow up if there are >9\n\n\nproc show_mmr_USx_MR_helper { NAME ADDR VAL } {\n    # First - just print it\n\n    set x [show_normalize_bitfield $VAL 3 0]\n    if { $x == 0 } {\n\techo \"\\tNormal operation\"\n    } else {\n\techo [format \"\\tNon Normal operation mode: 0x%02x\" $x]\n    }\n\n    set x [show_normalize_bitfield $VAL 11 9]\n    set s \"unknown\"\n    switch -exact $x {\n\t0 { set s \"Even\" }\n\t1 { set s \"Odd\" }\n\t2 { set s \"Force=0\" }\n\t3 { set s \"Force=1\" }\n\t* {\n\t    set $x [expr {$x & 6}]\n\t    switch -exact $x {\n\t\t4 { set s \"None\" }\n\t\t6 { set s \"Multidrop Mode\" }\n\t    }\n\t}\n    }\n    echo [format \"\\tParity: %s \" $s]\n\n    set x [expr {5 + [show_normalize_bitfield $VAL 7 6]}]\n    echo [format \"\\tDatabits: %d\" $x]\n\n    set x [show_normalize_bitfield $VAL 13 12]\n    switch -exact $x {\n\t0 { echo \"\\tStop bits: 1\" }\n\t1 { echo \"\\tStop bits: 1.5\" }\n\t2 { echo \"\\tStop bits: 2\" }\n\t3 { echo \"\\tStop bits: Illegal/Reserved\" }\n    }\n}\n\n# For every possbile usart...\nforeach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } {\n    set n AT91C_BASE_[set WHO]\n    set str \"\"\n\n    # Only if it exists on the chip\n    if [ info exists $n ] {\n\t# Hence: $n - is like AT91C_BASE_USx\n\t# For every sub-register\n\tforeach REG {CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER IF}\t{\n\t    # vn = variable name\n\t    set vn [set WHO]_[set REG]\n\t    # vn = USx_IER\n\t    # vv = variable value\n\t    set vv [expr \"$$n + [set USx_[set REG]]\"]\n\t    # And VV is the address in memory of that register\n\n\n\t    # make that VN a GLOBAL so others can find it\n\t    global $vn\n\t    set $vn $vv\n\n\t    # Create a command for this specific register.\n\t    proc show_$vn { } \"show_mmr32_reg $vn\"\n\n\t    # Add this command to the Device(as a whole) command\n\t    set str \"$str\\nshow_$vn\"\n\t}\n\t# Now - create the DEVICE(as a whole) command\n\tset fn show_$WHO\n\tproc $fn { } $str\n    }\n}\n\n# The Debug Uart is special..\nset str \"\"\n\n\n# For every sub-register\nforeach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR\n    DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} {\n\n    # Create a command for this specific register.\n    proc show_$REG { } \"show_mmr32_reg $REG\"\n\n    # Add this command to the Device(as a whole) command\n    set str \"$str\\nshow_$REG\"\n}\n\n# Now - create the DEVICE(as a whole) command\nproc show_DBGU { } $str\n\nunset str\n\nproc show_DBGU_MR_helper { NAME ADDR VAL } { show_mmr_USx_MR_helper $NAME $ADDR $VAL }\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/st/spear/quirk_no_srst.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Quirks to bypass missing SRST on JTAG connector\n# EVALSPEAr310 Rev. 2.0\n# http://www.st.com/spear\n#\n# Date:      2010-08-17\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\n# For boards that have JTAG SRST not connected.\n# We use \"arm9 vector_catch reset\" to catch button reset event.\n\n\n$_TARGETNAME configure -event reset-assert sp_reset_assert\n$_TARGETNAME configure -event reset-deassert-post sp_reset_deassert_post\n\n# keeps the name of the SPEAr target\nglobal sp_target_name\nset sp_target_name $_TARGETNAME\n\n# Keeps the argument of \"reset\" command (run, init, halt).\nglobal sp_reset_mode\nset sp_reset_mode \"\"\n\n# Helper procedure. Returns 0 is target is halted.\nproc sp_is_halted {} {\n\tglobal sp_target_name\n\n\treturn [expr {[string compare [$sp_target_name curstate] \"halted\" ] == 0}]\n}\n\n# wait for reset button to be pressed, causing CPU to get halted\nproc sp_reset_deassert_post {} {\n\tglobal sp_reset_mode\n\n\tset bar(0) |\n\tset bar(1) /\n\tset bar(2) -\n\tset bar(3) \\\\\n\n\tpoll on\n\techo \"====> Press reset button on the board <====\"\n\tfor {set i 0} { [sp_is_halted] == 0 } { set i [expr {$i + 1}]} {\n\t\techo -n \"$bar([expr {$i & 3}])\\r\"\n\t\tsleep 200\n\t}\n\n\t# Remove catch reset event\n\tarm9 vector_catch none\n\n\t# CPU is halted, but we typed \"reset run\" ...\n\tif { [string compare $sp_reset_mode \"run\"] == 0 } {\n\t\tresume\n\t}\n}\n\n# Override reset-assert, since no SRST available\n# Catch reset event\nproc sp_reset_assert {} {\n\tarm9 vector_catch reset\n}\n\n# Override default init_reset{mode} to catch parameter \"mode\"\nproc init_reset {mode} {\n\tglobal sp_reset_mode\n\n\tset sp_reset_mode $mode\n\n\t# We need to detect CPU get halted, so exit from halt\n\tif { [sp_is_halted] } {\n\t\techo \"Resuming CPU to detect reset\"\n\t\tresume\n\t}\n\n\t# Execute default init_reset{mode}\n\tjtag arp_init-reset\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/st/spear/spear3xx.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Generic init scripts for all ST SPEAr3xx family\n# http://www.st.com/spear\n#\n# Date:      2010-09-23\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\n\n# Initialize internal clock\n# Default:\n# - Crystal =  24 MHz\n# - PLL1    = 332 MHz\n# - PLL2    = 332 MHz\n# - CPU_CLK = 332 MHz\n# - DDR_CLK = 332 MHz async\n# - HCLK    = 166 MHz\n# - PCLK    =  83 MHz\nproc sp3xx_clock_default {} {\n\tmww 0xfca00000 0x00000002\t;# set sysclk slow\n\tmww 0xfca00014 0x0ffffff8\t;# set pll timeout to minimum (100us ?!?)\n\n\t# DDRCORE disable to change frequency\n\tset val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}]\n\tmww 0xfca8002c $val\n\tmww 0xfca8002c $val ;# Yes, write twice!\n\n\t# programming PLL1\n\tmww 0xfca8000c 0xa600010c\t;# M=166 P=1 N=12\n\tmww 0xfca80008 0x00001c0a\t;# power down\n\tmww 0xfca80008 0x00001c0e\t;# enable\n\tmww 0xfca80008 0x00001c06\t;# strobe\n\tmww 0xfca80008 0x00001c0e\n\twhile { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 }\n\n\t# programming PLL2\n\tmww 0xfca80018 0xa600010c\t;# M=166, P=1, N=12\n\tmww 0xfca80014 0x00001c0a\t;# power down\n\tmww 0xfca80014 0x00001c0e\t;# enable\n\tmww 0xfca80014 0x00001c06\t;# strobe\n\tmww 0xfca80014 0x00001c0e\n\twhile { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 }\n\n\tmww 0xfca80028 0x00000082\t;# enable plltimeen\n\tmww 0xfca80024 0x00000511\t;# set hclkdiv=\"/2\" & pclkdiv=\"/2\"\n\n\tmww 0xfca00000 0x00000004\t;# setting SYSCTL to NORMAL mode\n\twhile { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 }\n\n\t# Select source of DDR clock\n\t#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1\n\tmmw 0xfca80020 0x30000000 0x70000000 ;# PLL2\n\n\t# DDRCORE enable after change frequency\n\tmmw 0xfca8002c 0x20000000 0x00000000\n}\n\nproc sp3xx_common_init {} {\n\tmww 0xfca8002c 0xfffffff8\t;# enable clock of all peripherals\n\tmww 0xfca80038 0x00000000\t;# remove reset of all peripherals\n\n\tmww 0xfca80034 0x0000ffff\t;# enable all RAS clocks\n\tmww 0xfca80040 0x00000000\t;# remove all RAS resets\n\n\tmww 0xfca800e4 0x78000008\t;# COMP1V8_REG\n\tmww 0xfca800ec 0x78000008\t;# COMP3V3_REG\n\n\tmww 0xfc000000 0x10000f5f\t;# init SMI and set HW mode\n\tmww 0xfc000000 0x00000f5f\n\n\t# Initialize Bus Interconnection Matrix\n\t# All ports Round-Robin and lowest priority\n\tmww 0xfca8007c 0x80000007\n\tmww 0xfca80080 0x80000007\n\tmww 0xfca80084 0x80000007\n\tmww 0xfca80088 0x80000007\n\tmww 0xfca8008c 0x80000007\n\tmww 0xfca80090 0x80000007\n\tmww 0xfca80094 0x80000007\n\tmww 0xfca80098 0x80000007\n\tmww 0xfca8009c 0x80000007\n}\n\n\n# Specific init scripts for ST SPEAr300\nproc sp300_init {} {\n\tmww 0x99000000 0x00003fff\t;# RAS function enable\n}\n\n\n# Specific init scripts for ST SPEAr310\nproc sp310_init {} {\n\tmww 0xb4000008 0x00002ff4\t;# RAS function enable\n\n\tmww 0xfca80050 0x00000001\t;# Enable clk mem port 1\n\n\tmww 0xfca8013c 0x2f7bc210\t;# plgpio_pad_drv\n\tmww 0xfca80140 0x017bdef6\n}\n\nproc sp310_emi_init {} {\n\t# set EMI pad strength\n\tmmw 0xfca80134 0x0e000000 0x00000000\n\tmmw 0xfca80138 0x0e739ce7 0x00000000\n\tmmw 0xfca8013c 0x00039ce7 0x00000000\n\n\t# set safe EMI timing as in BootROM\n\t#mww 0x4f000000 0x0000000f\t;# tAP_0_reg\n\t#mww 0x4f000004 0x00000000\t;# tSDP_0_reg\n\t#mww 0x4f000008 0x000000ff\t;# tDPw_0_reg\n\t#mww 0x4f00000c 0x00000111\t;# tDPr_0_reg\n\t#mww 0x4f000010 0x00000002\t;# tDCS_0_reg\n\n\t# set fast EMI timing as in Linux\n\tmww 0x4f000000 0x00000010\t;# tAP_0_reg\n\tmww 0x4f000004 0x00000005\t;# tSDP_0_reg\n\tmww 0x4f000008 0x0000000a\t;# tDPw_0_reg\n\tmww 0x4f00000c 0x0000000a\t;# tDPr_0_reg\n\tmww 0x4f000010 0x00000005\t;# tDCS_0_re\n\n\t# 32bit wide, 8/16/32bit access\n\tmww 0x4f000014 0x0000000e\t;# control_0_reg\n\tmww 0x4f000094 0x0000003f\t;# ack_reg\n}\n\n\n# Specific init scripts for ST SPEAr320\nproc sp320_init {} {\n\tmww 0xb300000c 0xffffac04\t;# RAS function enable\n\tmww 0xb3000010 0x00000001\t;# RAS mode select\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/st/spear/spear3xx_ddr.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Init scripts to configure DDR controller of SPEAr3xx\n# http://www.st.com/spear\n# Original values taken from XLoader source code\n#\n# Date:      2010-09-23\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\n\nproc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {\n\tif { $ddr_chips != 1 && $ddr_chips != 2 } {\n\t\terror \"Only 1 or 2 DDR chips permitted. Wrong value \"$ddr_chips\n\t}\n\n\tif { $ddr_type == \"mt47h64m16_3_333_cl5_async\" } {\n\t\tddr_spr3xx_mt47h64m16_3_333_cl5_async $ddr_chips\n\t\tset ddr_size 0x08000000\n\t## add here new DDR chip definition. Prototype:\n\t#} elseif { $ddr_type == \"?????\" } {\n\t#\t????? $ddr_chips\n\t#\tset ddr_size 0x?????\n\t} else {\n\t\terror \"sp3xx_ddr_init: unrecognized DDR type \"$ddr_type\n\t}\n\n\t# MPMC START\n\tmww 0xfc60001c 0x01000100\n\n\tif { $ddr_chips == 2 } {\n\t\techo [format \\\n\t\t\t\"Double chip DDR memory. Total memory size 0x%08x byte\" \\\n\t\t\t[expr {2 * $ddr_size}]]\n\t} else {\n\t\techo [format \\\n\t\t\t\"Single chip DDR memory. Memory size 0x%08x byte\" \\\n\t\t\t$ddr_size]\n\t}\n}\n\n\n# from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S\nproc ddr_spr3xx_mt47h64m16_3_333_cl5_async {ddr_chips} {\n\t# DDR_PAD_REG\n\tmww 0xfca800f0 0x00003aa5\n\n\t# Use \"1:2 sync\" only when DDR clock source is PLL1 and\n\t# HCLK is half of PLL1\n\tmww 0xfc600000 0x00000001\t;# MEMCTL_AHB_SET_00 # This is async\n\tmww 0xfc600004 0x00000000\t;# MEMCTL_AHB_SET_01\n#\tmww 0xfc600000 0x02020201\t;# MEMCTL_AHB_SET_00 # This is 1:2 sync\n#\tmww 0xfc600004 0x02020202\t;# MEMCTL_AHB_SET_01\n\n\tmww 0xfc600008 0x01000000\t;# MEMCTL_RFSH_SET_00\n\tmww 0xfc60000c 0x00000101\t;# MEMCTL_DLL_SET_00\n\tmww 0xfc600010 0x00000101\t;# MEMCTL_GP_00\n\tmww 0xfc600014 0x01000000\t;# MEMCTL_GP_01\n\tmww 0xfc600018 0x00010001\t;# MEMCTL_GP_02\n\tmww 0xfc60001c 0x00000100\t;# MEMCTL_GP_03\n\tmww 0xfc600020 0x00010001\t;# MEMCTL_GP_04\n\tif { $ddr_chips == 2 } {\n\t\tmww 0xfc600024 0x01020203\t;# MEMCTL_GP_05\n\t\tmww 0xfc600028 0x01000102\t;# MEMCTL_GP_06\n\t\tmww 0xfc60002c 0x02000202\t;# MEMCTL_AHB_SET_02\n\t} else {\n\t\tmww 0xfc600024 0x00000201\t;# MEMCTL_GP_05\n\t\tmww 0xfc600028 0x02000001\t;# MEMCTL_GP_06\n\t\tmww 0xfc60002c 0x02000201\t;# MEMCTL_AHB_SET_02\n\t}\n\tmww 0xfc600030 0x04040105\t;# MEMCTL_AHB_SET_03\n\tmww 0xfc600034 0x03030302\t;# MEMCTL_AHB_SET_04\n\tmww 0xfc600038 0x02040101\t;# MEMCTL_AHB_SET_05\n\tmww 0xfc60003c 0x00000002\t;# MEMCTL_AHB_SET_06\n\tmww 0xfc600044 0x03000405\t;# MEMCTL_DQS_SET_0\n\tmww 0xfc600048 0x03040002\t;# MEMCTL_TIME_SET_01\n\tmww 0xfc60004c 0x04000305\t;# MEMCTL_TIME_SET_02\n\tmww 0xfc600050 0x0505053f\t;# MEMCTL_AHB_RELPR_00\n\tmww 0xfc600054 0x05050505\t;# MEMCTL_AHB_RELPR_01\n\tmww 0xfc600058 0x04040405\t;# MEMCTL_AHB_RELPR_02\n\tmww 0xfc60005c 0x04040404\t;# MEMCTL_AHB_RELPR_03\n\tmww 0xfc600060 0x03030304\t;# MEMCTL_AHB_RELPR_04\n\tmww 0xfc600064 0x03030303\t;# MEMCTL_AHB_RELPR_05\n\tmww 0xfc600068 0x02020203\t;# MEMCTL_AHB_RELPR_06\n\tmww 0xfc60006c 0x02020202\t;# MEMCTL_AHB_RELPR_07\n\tmww 0xfc600070 0x01010102\t;# MEMCTL_AHB_RELPR_08\n\tmww 0xfc600074 0x01010101\t;# MEMCTL_AHB_RELPR_09\n\tmww 0xfc600078 0x00000001\t;# MEMCTL_AHB_RELPR_10\n\tmww 0xfc600088 0x0a0c0a00\t;# MEMCTL_DQS_SET_1\n\tmww 0xfc60008c 0x0000023f\t;# MEMCTL_GP_07\n\tmww 0xfc600090 0x00050a00\t;# MEMCTL_GP_08\n\tmww 0xfc600094 0x11000000\t;# MEMCTL_GP_09\n\tmww 0xfc600098 0x00001302\t;# MEMCTL_GP_10\n\tmww 0xfc60009c 0x00001c1c\t;# MEMCTL_DLL_SET_01\n\tmww 0xfc6000a0 0x7c000000\t;# MEMCTL_DQS_OUT_SHIFT\n\tmww 0xfc6000a4 0x005c0000\t;# MEMCTL_WR_DQS_SHIFT\n\tmww 0xfc6000a8 0x2b050e00\t;# MEMCTL_TIME_SET_03\n\tmww 0xfc6000ac 0x00640064\t;# MEMCTL_AHB_PRRLX_00\n\tmww 0xfc6000b0 0x00640064\t;# MEMCTL_AHB_PRRLX_01\n\tmww 0xfc6000b4 0x00000064\t;# MEMCTL_AHB_PRRLX_02\n\tmww 0xfc6000b8 0x00000000\t;# MEMCTL_OUTRANGE_LGTH\n\tmww 0xfc6000bc 0x00200020\t;# MEMCTL_AHB_RW_SET_00\n\tmww 0xfc6000c0 0x00200020\t;# MEMCTL_AHB_RW_SET_01\n\tmww 0xfc6000c4 0x00200020\t;# MEMCTL_AHB_RW_SET_02\n\tmww 0xfc6000c8 0x00200020\t;# MEMCTL_AHB_RW_SET_03\n\tmww 0xfc6000cc 0x00200020\t;# MEMCTL_AHB_RW_SET_04\n\tmww 0xfc6000d8 0x00000a24\t;# MEMCTL_TREF\n\tmww 0xfc6000dc 0x00000000\t;# MEMCTL_EMRS3_DATA\n\tmww 0xfc6000e0 0x5b1c00c8\t;# MEMCTL_TIME_SET_04\n\tmww 0xfc6000e4 0x00c8002e\t;# MEMCTL_TIME_SET_05\n\tmww 0xfc6000e8 0x00000000\t;# MEMCTL_VERSION\n\tmww 0xfc6000ec 0x0001046b\t;# MEMCTL_TINIT\n\tmww 0xfc6000f0 0x00000000\t;# MEMCTL_OUTRANGE_ADDR_01\n\tmww 0xfc6000f4 0x00000000\t;# MEMCTL_OUTRANGE_ADDR_02\n\tmww 0xfc600104 0x001c0000\t;# MEMCTL_DLL_DQS_DELAY_BYPASS_0\n\tmww 0xfc600108 0x0019001c\t;# MEMCTL_DLL_SET_02\n\tmww 0xfc60010c 0x00100000\t;# MEMCTL_DLL_SET_03\n\tmww 0xfc600110 0x001e007a\t;# MEMCTL_DQS_SET_2\n\tmww 0xfc600188 0x00000000\t;# MEMCTL_USER_DEF_REG_0\n\tmww 0xfc60018c 0x00000000\t;# MEMCTL_USER_DEF_REG_1\n\tmww 0xfc600190 0x01010001\t;# MEMCTL_GP_11\n\tmww 0xfc600194 0x01000000\t;# MEMCTL_GP_12\n\tmww 0xfc600198 0x00000001\t;# MEMCTL_GP_13\n\tmww 0xfc60019c 0x00400000\t;# MEMCTL_GP_14\n\tmww 0xfc6001a0 0x00000000\t;# MEMCTL_EMRS2_DATA_X\n\tmww 0xfc6001a4 0x00000000\t;# MEMCTL_LWPWR_CNT\n\tmww 0xfc6001a8 0x00000000\t;# MEMCTL_LWPWR_REG\n\tmww 0xfc6001ac 0x00860000\t;# MEMCTL_GP_15\n\tmww 0xfc6001b0 0x00000002\t;# MEMCTL_TPDEX\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/st/stm32/stm32.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find bitsbytes.tcl]\nsource [find cpu/arm/cortex_m3.tcl]\nsource [find memory.tcl]\nsource [find mmr_helpers.tcl]\n\nsource [find chip/st/stm32/stm32_regs.tcl]\nsource [find chip/st/stm32/stm32_rcc.tcl]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/st/stm32/stm32_rcc.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset RCC_CR            [expr {$RCC_BASE + 0x00}]\nset RCC_CFGR          [expr {$RCC_BASE + 0x04}]\nset RCC_CIR           [expr {$RCC_BASE + 0x08}]\nset RCC_APB2RSTR      [expr {$RCC_BASE + 0x0c}]\nset RCC_APB1RSTR      [expr {$RCC_BASE + 0x10}]\nset RCC_AHBENR        [expr {$RCC_BASE + 0x14}]\nset RCC_APB2ENR       [expr {$RCC_BASE + 0x18}]\nset RCC_APB1ENR       [expr {$RCC_BASE + 0x1c}]\nset RCC_BDCR          [expr {$RCC_BASE + 0x20}]\nset RCC_CSR           [expr {$RCC_BASE + 0x24}]\n\n\nproc show_RCC_CR { } {\n    if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {\n\terror $msg\n    }\n\n    show_mmr_bitfield  0  0 $val HSI      { OFF ON }\n    show_mmr_bitfield  1  1 $val HSIRDY   { NOTRDY RDY  }\n    show_mmr_bitfield  7  3 $val HSITRIM  { _NUMBER_ }\n    show_mmr_bitfield 15  8 $val HSICAL   { _NUMBER_ }\n    show_mmr_bitfield 16 16 $val HSEON    { OFF ON }\n    show_mmr_bitfield 17 17 $val HSERDY   { NOTRDY RDY  }\n    show_mmr_bitfield 18 18 $val HSEBYP   { NOTBYPASSED BYPASSED }\n    show_mmr_bitfield 19 19 $val CSSON    { OFF ON }\n    show_mmr_bitfield 24 24 $val PLLON    { OFF ON }\n    show_mmr_bitfield 25 25 $val PLLRDY   { NOTRDY RDY }\n}\n\nproc show_RCC_CFGR { } {\n    if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {\n\terror $msg\n    }\n\n\n    show_mmr_bitfield  1  0 $val  SW     { HSI HSE PLL ILLEGAL }\n    show_mmr_bitfield  3  2 $val  SWS    { HSI HSE PLL ILLEGAL }\n    show_mmr_bitfield  7  4 $val  HPRE   { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }\n    show_mmr_bitfield 10  8 $val  PPRE1  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }\n    show_mmr_bitfield 13 11 $val  PPRE2  { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }\n    show_mmr_bitfield 15 14 $val  ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }\n    show_mmr_bitfield 16 16 $val  PLLSRC { HSI_div_2 HSE }\n    show_mmr_bitfield 17 17 $val  PLLXTPRE { hse_div1 hse_div2 }\n    show_mmr_bitfield 21 18 $val  PLLMUL { x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }\n    show_mmr_bitfield 22 22 $val  USBPRE { div1 div1_5 }\n    show_mmr_bitfield 26 24 $val  MCO    { none none none none SysClk HSI HSE PLL_div2 }\n}\n\n\nproc show_RCC_CIR { } {\n    if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {\n\terror $msg\n    }\n\n}\n\nproc show_RCC_APB2RSTR { } {\n    if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {\n\terror $msg\n    }\n    for { set x 0 } { $x < 32 } { incr x } {\n\tset bits($x) xxx\n    }\n    set bits(15) adc3\n    set bits(14) usart1\n    set bits(13) tim8\n    set bits(12) spi1\n    set bits(11) tim1\n    set bits(10) adc2\n    set bits(9) adc1\n    set bits(8) iopg\n    set bits(7) iopf\n    set bits(6) iope\n    set bits(5) iopd\n    set bits(4) iopc\n    set bits(3) iopb\n    set bits(2) iopa\n    set bits(1) xxx\n    set bits(0) afio\n    show_mmr32_bits bits $val\n}\n\nproc show_RCC_APB1RSTR { } {\n    if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {\n\terror $msg\n    }\n    set bits(31) xxx\n    set bits(30) xxx\n    set bits(29) dac\n    set bits(28) pwr\n    set bits(27) bkp\n    set bits(26) xxx\n    set bits(25) can\n    set bits(24) xxx\n    set bits(23) usb\n    set bits(22) i2c2\n    set bits(21) i2c1\n    set bits(20) uart5\n    set bits(19) uart4\n    set bits(18) uart3\n    set bits(17) uart2\n    set bits(16) xxx\n    set bits(15) spi3\n    set bits(14) spi2\n    set bits(13) xxx\n    set bits(12) xxx\n    set bits(11) wwdg\n    set bits(10) xxx\n    set bits(9) xxx\n    set bits(8) xxx\n    set bits(7) xxx\n    set bits(6) xxx\n    set bits(5) tim7\n    set bits(4) tim6\n    set bits(3) tim5\n    set bits(2) tim4\n    set bits(1) tim3\n    set bits(0) tim2\n    show_mmr32_bits bits $val\n\n}\n\nproc show_RCC_AHBENR   { } {\n    if [ catch { set val [ show_mmr32_reg RCC_AHBENR  ] } msg ] {\n\terror $msg\n    }\n    set bits(31) xxx\n    set bits(30) xxx\n    set bits(29) xxx\n    set bits(28) xxx\n    set bits(27) xxx\n    set bits(26) xxx\n    set bits(25) xxx\n    set bits(24) xxx\n    set bits(23) xxx\n    set bits(22) xxx\n    set bits(21) xxx\n    set bits(20) xxx\n    set bits(19) xxx\n    set bits(18) xxx\n    set bits(17) xxx\n    set bits(16) xxx\n    set bits(15) xxx\n    set bits(14) xxx\n    set bits(13) xxx\n    set bits(12) xxx\n    set bits(11) xxx\n    set bits(10) sdio\n    set bits(9) xxx\n    set bits(8) fsmc\n    set bits(7) xxx\n    set bits(6) crce\n    set bits(5) xxx\n    set bits(4) flitf\n    set bits(3) xxx\n    set bits(2) sram\n    set bits(1) dma2\n    set bits(0) dma1\n    show_mmr32_bits bits $val\n}\n\nproc show_RCC_APB2ENR  { } {\n    if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {\n\terror $msg\n    }\n    set bits(31) xxx\n    set bits(30) xxx\n    set bits(29) xxx\n    set bits(28) xxx\n    set bits(27) xxx\n    set bits(26) xxx\n    set bits(25) xxx\n    set bits(24) xxx\n    set bits(23) xxx\n    set bits(22) xxx\n    set bits(21) xxx\n    set bits(20) xxx\n    set bits(19) xxx\n    set bits(18) xxx\n    set bits(17) xxx\n    set bits(16) xxx\n    set bits(15) adc3\n    set bits(14) usart1\n    set bits(13) tim8\n    set bits(12) spi1\n    set bits(11) tim1\n    set bits(10) adc2\n    set bits(9) adc1\n    set bits(8) iopg\n    set bits(7) iopf\n    set bits(6) iope\n    set bits(5) iopd\n    set bits(4) iopc\n    set bits(3) iopb\n    set bits(2) iopa\n    set bits(1) xxx\n    set bits(0) afio\n    show_mmr32_bits bits $val\n\n}\n\nproc show_RCC_APB1ENR  { } {\n    if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {\n\terror $msg\n    }\n    set bits(31) xxx\n    set bits(30) xxx\n    set bits(29) dac\n    set bits(28) pwr\n    set bits(27) bkp\n    set bits(26) xxx\n    set bits(25) can\n    set bits(24) xxx\n    set bits(23) usb\n    set bits(22) i2c2\n    set bits(21) i2c1\n    set bits(20) usart5\n    set bits(19) usart4\n    set bits(18) usart3\n    set bits(17) usart2\n    set bits(16) xxx\n    set bits(15) spi3\n    set bits(14) spi2\n    set bits(13) xxx\n    set bits(12) xxx\n    set bits(11) wwdg\n    set bits(10) xxx\n    set bits(9) xxx\n    set bits(8) xxx\n    set bits(7) xxx\n    set bits(6) xxx\n    set bits(5) tim7\n    set bits(4) tim6\n    set bits(3) tim5\n    set bits(2) tim4\n    set bits(1) tim3\n    set bits(0) tim2\n    show_mmr32_bits bits $val\n}\n\nproc show_RCC_BDCR     { } {\n    if [ catch { set val [ show_mmr32_reg RCC_BDCR    ] } msg ] {\n\terror $msg\n    }\n    for { set x 0 } { $x < 32 } { incr x } {\n\tset bits($x) xxx\n    }\n    set bits(0) lseon\n    set bits(1) lserdy\n    set bits(2) lsebyp\n    set bits(8) rtcsel0\n    set bits(9) rtcsel1\n    set bits(15) rtcen\n    set bits(16) bdrst\n    show_mmr32_bits bits $val\n}\n\nproc show_RCC_CSR      { } {\n    if [ catch { set val [ show_mmr32_reg RCC_CSR     ] } msg ] {\n\terror $msg\n    }\n    for { set x 0 } { $x < 32 } { incr x } {\n\tset bits($x) xxx\n    }\n    set bits(0) lsion\n    set bits(1) lsirdy\n    set bits(24) rmvf\n    set bits(26) pin\n    set bits(27) por\n    set bits(28) sft\n    set bits(29) iwdg\n    set bits(30) wwdg\n    set bits(31) lpwr\n    show_mmr32_bits bits $val\n}\n\nproc show_RCC { } {\n\n    show_RCC_CR\n    show_RCC_CFGR\n    show_RCC_CIR\n    show_RCC_APB2RSTR\n    show_RCC_APB1RSTR\n    show_RCC_AHBENR\n    show_RCC_APB2ENR\n    show_RCC_APB1ENR\n    show_RCC_BDCR\n    show_RCC_CSR\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/st/stm32/stm32_regs.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# /* Peripheral and SRAM base address in the alias region */\nset PERIPH_BB_BASE        0x42000000\nset SRAM_BB_BASE          0x22000000\n\n# /*Peripheral and SRAM base address in the bit-band region */\nset SRAM_BASE             0x20000000\nset PERIPH_BASE           0x40000000\n\n# /*FSMC registers base address */\nset FSMC_R_BASE           0xA0000000\n\n# /*Peripheral memory map */\nset APB1PERIPH_BASE       [set PERIPH_BASE]\nset APB2PERIPH_BASE       [expr {$PERIPH_BASE + 0x10000}]\nset AHBPERIPH_BASE        [expr {$PERIPH_BASE + 0x20000}]\n\nset TIM2_BASE             [expr {$APB1PERIPH_BASE + 0x0000}]\nset TIM3_BASE             [expr {$APB1PERIPH_BASE + 0x0400}]\nset TIM4_BASE             [expr {$APB1PERIPH_BASE + 0x0800}]\nset TIM5_BASE             [expr {$APB1PERIPH_BASE + 0x0C00}]\nset TIM6_BASE             [expr {$APB1PERIPH_BASE + 0x1000}]\nset TIM7_BASE             [expr {$APB1PERIPH_BASE + 0x1400}]\nset RTC_BASE              [expr {$APB1PERIPH_BASE + 0x2800}]\nset WWDG_BASE             [expr {$APB1PERIPH_BASE + 0x2C00}]\nset IWDG_BASE             [expr {$APB1PERIPH_BASE + 0x3000}]\nset SPI2_BASE             [expr {$APB1PERIPH_BASE + 0x3800}]\nset SPI3_BASE             [expr {$APB1PERIPH_BASE + 0x3C00}]\nset USART2_BASE           [expr {$APB1PERIPH_BASE + 0x4400}]\nset USART3_BASE           [expr {$APB1PERIPH_BASE + 0x4800}]\nset UART4_BASE            [expr {$APB1PERIPH_BASE + 0x4C00}]\nset UART5_BASE            [expr {$APB1PERIPH_BASE + 0x5000}]\nset I2C1_BASE             [expr {$APB1PERIPH_BASE + 0x5400}]\nset I2C2_BASE             [expr {$APB1PERIPH_BASE + 0x5800}]\nset CAN_BASE              [expr {$APB1PERIPH_BASE + 0x6400}]\nset BKP_BASE              [expr {$APB1PERIPH_BASE + 0x6C00}]\nset PWR_BASE              [expr {$APB1PERIPH_BASE + 0x7000}]\nset DAC_BASE              [expr {$APB1PERIPH_BASE + 0x7400}]\n\nset AFIO_BASE             [expr {$APB2PERIPH_BASE + 0x0000}]\nset EXTI_BASE             [expr {$APB2PERIPH_BASE + 0x0400}]\nset GPIOA_BASE            [expr {$APB2PERIPH_BASE + 0x0800}]\nset GPIOB_BASE            [expr {$APB2PERIPH_BASE + 0x0C00}]\nset GPIOC_BASE            [expr {$APB2PERIPH_BASE + 0x1000}]\nset GPIOD_BASE            [expr {$APB2PERIPH_BASE + 0x1400}]\nset GPIOE_BASE            [expr {$APB2PERIPH_BASE + 0x1800}]\nset GPIOF_BASE            [expr {$APB2PERIPH_BASE + 0x1C00}]\nset GPIOG_BASE            [expr {$APB2PERIPH_BASE + 0x2000}]\nset ADC1_BASE             [expr {$APB2PERIPH_BASE + 0x2400}]\nset ADC2_BASE             [expr {$APB2PERIPH_BASE + 0x2800}]\nset TIM1_BASE             [expr {$APB2PERIPH_BASE + 0x2C00}]\nset SPI1_BASE             [expr {$APB2PERIPH_BASE + 0x3000}]\nset TIM8_BASE             [expr {$APB2PERIPH_BASE + 0x3400}]\nset USART1_BASE           [expr {$APB2PERIPH_BASE + 0x3800}]\nset ADC3_BASE             [expr {$APB2PERIPH_BASE + 0x3C00}]\n\nset SDIO_BASE             [expr {$PERIPH_BASE + 0x18000}]\n\nset DMA1_BASE             [expr {$AHBPERIPH_BASE + 0x0000}]\nset DMA1_Channel1_BASE    [expr {$AHBPERIPH_BASE + 0x0008}]\nset DMA1_Channel2_BASE    [expr {$AHBPERIPH_BASE + 0x001C}]\nset DMA1_Channel3_BASE    [expr {$AHBPERIPH_BASE + 0x0030}]\nset DMA1_Channel4_BASE    [expr {$AHBPERIPH_BASE + 0x0044}]\nset DMA1_Channel5_BASE    [expr {$AHBPERIPH_BASE + 0x0058}]\nset DMA1_Channel6_BASE    [expr {$AHBPERIPH_BASE + 0x006C}]\nset DMA1_Channel7_BASE    [expr {$AHBPERIPH_BASE + 0x0080}]\nset DMA2_BASE             [expr {$AHBPERIPH_BASE + 0x0400}]\nset DMA2_Channel1_BASE    [expr {$AHBPERIPH_BASE + 0x0408}]\nset DMA2_Channel2_BASE    [expr {$AHBPERIPH_BASE + 0x041C}]\nset DMA2_Channel3_BASE    [expr {$AHBPERIPH_BASE + 0x0430}]\nset DMA2_Channel4_BASE    [expr {$AHBPERIPH_BASE + 0x0444}]\nset DMA2_Channel5_BASE    [expr {$AHBPERIPH_BASE + 0x0458}]\nset RCC_BASE              [expr {$AHBPERIPH_BASE + 0x1000}]\nset CRC_BASE              [expr {$AHBPERIPH_BASE + 0x3000}]\n\n# /*Flash registers base address */\nset FLASH_R_BASE          [expr {$AHBPERIPH_BASE + 0x2000}]\n# /*Flash Option Bytes base address */\nset OB_BASE               0x1FFFF800\n\n# /*FSMC Bankx registers base address */\nset FSMC_Bank1_R_BASE     [expr {$FSMC_R_BASE + 0x0000}]\nset FSMC_Bank1E_R_BASE    [expr {$FSMC_R_BASE + 0x0104}]\nset FSMC_Bank2_R_BASE     [expr {$FSMC_R_BASE + 0x0060}]\nset FSMC_Bank3_R_BASE     [expr {$FSMC_R_BASE + 0x0080}]\nset FSMC_Bank4_R_BASE     [expr {$FSMC_R_BASE + 0x00A0}]\n\n# /*Debug MCU registers base address */\nset DBGMCU_BASE           0xE0042000\n\n# /*System Control Space memory map */\nset SCS_BASE              0xE000E000\n\nset SysTick_BASE          [expr {$SCS_BASE + 0x0010}]\nset NVIC_BASE             [expr {$SCS_BASE + 0x0100}]\nset SCB_BASE              [expr {$SCS_BASE + 0x0D00}]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/ti/lm3s/lm3s.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find chip/ti/lm3s/lm3s_regs.tcl]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/chip/ti/lm3s/lm3s_regs.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#*****************************************************************************\n#\n# The following are defines for the System Control register addresses.\n#\n#*****************************************************************************\n\nset SYSCTL_DID0             0x400FE000  ;# Device Identification 0\nset SYSCTL_DID1             0x400FE004  ;# Device Identification 1\nset SYSCTL_DC0              0x400FE008  ;# Device Capabilities 0\nset SYSCTL_DC1              0x400FE010  ;# Device Capabilities 1\nset SYSCTL_DC2              0x400FE014  ;# Device Capabilities 2\nset SYSCTL_DC3              0x400FE018  ;# Device Capabilities 3\nset SYSCTL_DC4              0x400FE01C  ;# Device Capabilities 4\nset SYSCTL_DC5              0x400FE020  ;# Device Capabilities 5\nset SYSCTL_DC6              0x400FE024  ;# Device Capabilities 6\nset SYSCTL_DC7              0x400FE028  ;# Device Capabilities 7\nset SYSCTL_DC8              0x400FE02C  ;# Device Capabilities 8 ADC\n                                        ;# Channels\nset SYSCTL_PBORCTL          0x400FE030  ;# Brown-Out Reset Control\nset SYSCTL_LDOPCTL          0x400FE034  ;# LDO Power Control\nset SYSCTL_SRCR0            0x400FE040  ;# Software Reset Control 0\nset SYSCTL_SRCR1            0x400FE044  ;# Software Reset Control 1\nset SYSCTL_SRCR2            0x400FE048  ;# Software Reset Control 2\nset SYSCTL_RIS              0x400FE050  ;# Raw Interrupt Status\nset SYSCTL_IMC              0x400FE054  ;# Interrupt Mask Control\nset SYSCTL_MISC             0x400FE058  ;# Masked Interrupt Status and\n                                        ;# Clear\nset SYSCTL_RESC             0x400FE05C  ;# Reset Cause\nset SYSCTL_RCC              0x400FE060  ;# Run-Mode Clock Configuration\nset SYSCTL_PLLCFG           0x400FE064  ;# XTAL to PLL Translation\nset SYSCTL_GPIOHSCTL        0x400FE06C  ;# GPIO High-Speed Control\nset SYSCTL_GPIOHBCTL        0x400FE06C  ;# GPIO High-Performance Bus\n                                        ;# Control\nset SYSCTL_RCC2             0x400FE070  ;# Run-Mode Clock Configuration 2\nset SYSCTL_MOSCCTL          0x400FE07C  ;# Main Oscillator Control\nset SYSCTL_RCGC0            0x400FE100  ;# Run Mode Clock Gating Control\n                                        ;# Register 0\nset SYSCTL_RCGC1            0x400FE104  ;# Run Mode Clock Gating Control\n                                        ;# Register 1\nset SYSCTL_RCGC2            0x400FE108  ;# Run Mode Clock Gating Control\n                                        ;# Register 2\nset SYSCTL_SCGC0            0x400FE110  ;# Sleep Mode Clock Gating Control\n                                        ;# Register 0\nset SYSCTL_SCGC1            0x400FE114  ;# Sleep Mode Clock Gating Control\n                                        ;# Register 1\nset SYSCTL_SCGC2            0x400FE118  ;# Sleep Mode Clock Gating Control\n                                        ;# Register 2\nset SYSCTL_DCGC0            0x400FE120  ;# Deep Sleep Mode Clock Gating\n                                        ;# Control Register 0\nset SYSCTL_DCGC1            0x400FE124  ;# Deep-Sleep Mode Clock Gating\n                                        ;# Control Register 1\nset SYSCTL_DCGC2            0x400FE128  ;# Deep Sleep Mode Clock Gating\n                                        ;# Control Register 2\nset SYSCTL_DSLPCLKCFG       0x400FE144  ;# Deep Sleep Clock Configuration\nset SYSCTL_CLKVCLR          0x400FE150  ;# Clock Verification Clear\nset SYSCTL_PIOSCCAL         0x400FE150  ;# Precision Internal Oscillator\n                                        ;# Calibration\nset SYSCTL_PIOSCSTAT        0x400FE154  ;# Precision Internal Oscillator\n                                        ;# Statistics\nset SYSCTL_LDOARST          0x400FE160  ;# Allow Unregulated LDO to Reset\n                                        ;# the Part\nset SYSCTL_I2SMCLKCFG       0x400FE170  ;# I2S MCLK Configuration\nset SYSCTL_DC9              0x400FE190  ;# Device Capabilities 9 ADC\n                                        ;# Digital Comparators\nset SYSCTL_NVMSTAT          0x400FE1A0  ;# Non-Volatile Memory Information\n\nset SYSCTL_RCC_USESYSDIV    0x00400000  ;# Enable System Clock Divider\nset SYSCTL_RCC2_BYPASS2     0x00000800  ;# PLL Bypass 2\nset SYSCTL_RCC_MOSCDIS      0x00000001  ;# Main Oscillator Disable\n\nset SYSCTL_SRCR0            0x400FE040  ;# Software Reset Control 0\nset SYSCTL_SRCR1            0x400FE044  ;# Software Reset Control 1\nset SYSCTL_SRCR2            0x400FE048  ;# Software Reset Control 2\n\nset SYSCTL_MISC             0x400FE058  ;# Masked Interrupt Status and Clear\n\nset FLASH_FMA               0x400FD000  ;# Flash Memory Address\nset FLASH_FMD               0x400FD004  ;# Flash Memory Data\nset FLASH_FMC               0x400FD008  ;# Flash Memory Control\nset FLASH_FCRIS             0x400FD00C  ;# Flash Controller Raw Interrupt Status\nset FLASH_FCIM              0x400FD010  ;# Flash Controller Interrupt Mask\nset FLASH_FCMISC            0x400FD014  ;# Flash Controller Masked Interrupt Status and Clear\nset FLASH_FMC2              0x400FD020  ;#  Flash Memory Control 2\nset FLASH_FWBVAL            0x400FD030  ;# Flash Write Buffer Valid\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/altera-5m570z-cpld.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# file altera-5m570z-cpld.cfg replaced by altera-maxv.cfg\necho \"DEPRECATED: use altera-maxv.cfg instead of deprecated altera-5m570z-cpld.cfg\"\n\n#just to be backward compatible:\n#tap will be 5m570z.tap instead of maxv.tap:\nset CHIPNAME 5m570z\nsource [find cpld/altera-maxv.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/altera-epm240.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# file altera-epm240.cfg replaced by altera-maxii.cfg\necho \"DEPRECATED: use altera-maxii.cfg instead of deprecated altera-epm240.cfg\"\n\n#just to be backward compatible:\n#tap will be epm240.tap instead of maxii.tap:\nset CHIPNAME epm240\nsource [find cpld/altera-maxii.cfg]\n\n# 200ns seems like a good speed\n# c.f. Table 5-34: MAX II JTAG Timing Parameters\nadapter speed 5000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/altera-max10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# see MAX 10 FPGA Device Architecture\n# Table 3-1: IDCODE Information for MAX 10 Devices\n# Intel MAX 10M02 0x31810dd\n# Intel MAX 10M04 0x318a0dd\n# Intel MAX 10M08 0x31820dd\n# Intel MAX 10M16 0x31830dd\n# Intel MAX 10M25 0x31840dd\n# Intel MAX 10M40 0x318d0dd\n# Intel MAX 10M50 0x31850dd\n# Intel MAX 10M02 0x31010dd\n# Intel MAX 10M04 0x310a0dd\n# Intel MAX 10M08 0x31020dd\n# Intel MAX 10M16 0x31030dd\n# Intel MAX 10M25 0x31040dd\n# Intel MAX 10M40 0x310d0dd\n# Intel MAX 10M50 0x31050dd\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME max10\n}\n\njtag newtap $_CHIPNAME tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \\\n\t-expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \\\n\t-expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \\\n\t-expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \\\n\t-expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/altera-maxii.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Altera MAXII CPLD\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME maxii\n}\n\n# see MAX II Device Handbook\n# Table 3-3: 32-Bit MAX II Device IDCODE\n# Version     Part Number             Manuf. ID        LSB\n# 0000        0010 0000 1010 0001     000 0110 1110    1\njtag newtap $_CHIPNAME tap -irlen 10 \\\n\t-expected-id 0x020a10dd \\\n\t-expected-id 0x020a20dd \\\n\t-expected-id 0x020a30dd \\\n\t-expected-id 0x020a40dd \\\n\t-expected-id 0x020a50dd \\\n\t-expected-id 0x020a60dd\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/altera-maxv.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Altera MAXV 5M24OZ/5M570Z CPLD\n# see MAX V Device Handbook\n# Table 6-3: 32-Bit MAX V Device IDCODE\n# 5M40Z 5M80Z 5M160Z 5M240Z: 0x020A50DD\n# 5M570Z:                    0x020A60DD\n# 5M1270Z:                   0x020A30DD\n# 5M1270Z 5M2210Z:           0x020A40DD\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME maxv\n}\n\njtag newtap $_CHIPNAME tap -irlen 10 \\\n  -expected-id 0x020A50DD -expected-id 0x020A60DD \\\n  -expected-id 0x020A30DD -expected-id 0x020A40DD\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/jtagspi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset _USER1 0x02\n\nif { [info exists JTAGSPI_IR] } {\n\tset _JTAGSPI_IR $JTAGSPI_IR\n} else {\n\tset _JTAGSPI_IR $_USER1\n}\n\nif { [info exists TARGETNAME] } {\n\tset _TARGETNAME $TARGETNAME\n} else {\n\tset _TARGETNAME $_CHIPNAME.proxy\n}\n\nif { [info exists FLASHNAME] } {\n\tset _FLASHNAME $FLASHNAME\n} else {\n\tset _FLASHNAME $_CHIPNAME.spi\n}\n\ntarget create $_TARGETNAME testee -chain-position $_CHIPNAME.tap\nflash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR\n\n# initialize jtagspi flash\n# chain_id: identifier of pld (you can get a list with 'pld devices')\n# proxy_bit: file with bitstream connecting JTAG and SPI interface in the PLD.\n# release_from_pwr_down_cmd: optional, command sent to spi flash before probing.\n#                            ex: 0xAB to release from power-dowm.\n#                            Just omit it to not send a command.\n\nproc jtagspi_init {chain_id proxy_bit {release_from_pwr_down_cmd -1}} {\n\t# load proxy bitstream $proxy_bit and probe spi flash\n\tglobal _FLASHNAME\n\tpld load $chain_id $proxy_bit\n\treset halt\n\tif {$release_from_pwr_down_cmd != -1} {\n\t\tjtagspi cmd $_FLASHNAME 0 $release_from_pwr_down_cmd\n\t}\n\tflash probe $_FLASHNAME\n}\n\nproc jtagspi_program {bin addr} {\n\t# write and verify binary file $bin at offset $addr\n\tglobal _FLASHNAME\n\tflash write_image erase $bin $addr\n\tflash verify_bank $_FLASHNAME $bin $addr\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/lattice-lc4032ze.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Lattice ispMACH 4000ZE family, device LC4032ZE\n# just configure a tap\njtag newtap LC4032ZE tap -irlen 8 -expected-id  0x01806043\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc3s.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx spartan3\n# https://docs.xilinx.com/v/u/en-US/ug332\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc3s\n}\n\n# the 4 top bits (28:31) are the die stepping. ignore it.\njtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \\\n\t-expected-id 0x01414093 \\\n\t-expected-id 0x0141C093 \\\n\t-expected-id 0x01428093 \\\n\t-expected-id 0x01434093 \\\n\t-expected-id 0x01440093 \\\n\t-expected-id 0x01448093 \\\n\t-expected-id 0x01450093 \\\n\t-expected-id 0x01C10093 \\\n\t-expected-id 0x01C1A093 \\\n\t-expected-id 0x01C22093 \\\n\t-expected-id 0x01C2E093 \\\n\t-expected-id 0x01C3A093 \\\n\t-expected-id 0x0140C093 \\\n\t-expected-id 0x02210093 \\\n\t-expected-id 0x02218093 \\\n\t-expected-id 0x02220093 \\\n\t-expected-id 0x02228093 \\\n\t-expected-id 0x02230093 \\\n\t-expected-id 0x02610093 \\\n\t-expected-id 0x02618093 \\\n\t-expected-id 0x02620093 \\\n\t-expected-id 0x02628093 \\\n\t-expected-id 0x02630093 \\\n\t-expected-id 0x03840093 \\\n\t-expected-id 0x0384e093\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc4v.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx virtex 4\n# https://docs.xilinx.com/v/u/en-US/ug071\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc4v\n}\n\n# the 4 top bits (28:31) are the die stepping. ignore it.\njtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \\\n\t-expected-id 0x01658093 \\\n\t-expected-id 0x01E58093 \\\n\t-expected-id 0x0167C093 \\\n\t-expected-id 0x02068093 \\\n\t-expected-id 0x01E64093 \\\n\t-expected-id 0x016A4093 \\\n\t-expected-id 0x02088093 \\\n\t-expected-id 0x016B4093 \\\n\t-expected-id 0x020B0093 \\\n\t-expected-id 0x016D8093 \\\n\t-expected-id 0x01700093 \\\n\t-expected-id 0x01718093 \\\n\t-expected-id 0x01734093\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap\n# cfg_out cfg_in jprogb jstart jshutdown user1-4\nvirtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD\nvirtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc4vfx_40_60_100_140.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx virtex 4\n# https://docs.xilinx.com/v/u/en-US/ug071\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc4vfx\n}\n\n# the 4 top bits (28:31) are the die stepping. ignore it.\njtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \\\n\t-expected-id 0x01E8C093 \\\n\t-expected-id 0x01EB4093 \\\n\t-expected-id 0x01EE4093 \\\n\t-expected-id 0x01F14093 \\\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap\n# cfg_out cfg_in jprogb jstart jshutdown user1-4\nvirtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD\nvirtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc5v.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx virtex 5\n# https://docs.xilinx.com/v/u/en-US/ug191\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc5v\n}\n\n# the 4 top bits (28:31) are the die stepping. ignore it.\njtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \\\n\t-expected-id 0x0286E093 \\\n\t-expected-id 0x02896093 \\\n\t-expected-id 0x028AE093 \\\n\t-expected-id 0x028D6093 \\\n\t-expected-id 0x028EC093 \\\n\t-expected-id 0x0290C093 \\\n\t-expected-id 0x0295C093 \\\n\t-expected-id 0x02A56093 \\\n\t-expected-id 0x02A6E093 \\\n\t-expected-id 0x02A96093 \\\n\t-expected-id 0x02AAE093 \\\n\t-expected-id 0x02AD6093 \\\n\t-expected-id 0x02AEC093 \\\n\t-expected-id 0x02B0C093 \\\n\t-expected-id 0x02B5C093 \\\n\t-expected-id 0x02E72093 \\\n\t-expected-id 0x02E9A093 \\\n\t-expected-id 0x02ECE093 \\\n\t-expected-id 0x02F3E093 \\\n\t-expected-id 0x03276093 \\\n\t-expected-id 0x032C6093 \\\n\t-expected-id 0x04502093 \\\n\t-expected-id 0x0453E093\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap\n# cfg_out cfg_in jprogb jstart jshutdown user1-4\nvirtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD\nvirtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc5vfx_100_130_200.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx virtex 5\n# https://docs.xilinx.com/v/u/en-US/ug191\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc5vfx\n}\n\n# the 4 top bits (28:31) are the die stepping. ignore it.\njtag newtap $_CHIPNAME tap -irlen 14 -ignore-version \\\n\t-expected-id 0x032D8093 \\\n\t-expected-id 0x03300093 \\\n\t-expected-id 0x03334093\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap\n# cfg_out cfg_in jprogb jstart jshutdown user1-4\nvirtex2 set_instr_codes $_CHIPNAME.pld 0x3FC4 0x3FC5 0x3FCB 0x3FCC 0x3FCD\nvirtex2 set_user_codes $_CHIPNAME.pld 0x3FC2 0x3FC3 0x3FE2 0x3FE3\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc6s.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx spartan6\n# http://www.xilinx.com/support/documentation/user_guides/ug380.pdf\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc6s\n}\n\n# the 4 top bits (28:31) are the die stepping. ignore it.\njtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \\\n\t-expected-id 0x04000093 \\\n\t-expected-id 0x04001093 \\\n\t-expected-id 0x04002093 \\\n\t-expected-id 0x04004093 \\\n\t-expected-id 0x04024093 \\\n\t-expected-id 0x04008093 \\\n\t-expected-id 0x04028093 \\\n\t-expected-id 0x0400E093 \\\n\t-expected-id 0x0402E093 \\\n\t-expected-id 0x04011093 \\\n\t-expected-id 0x04031093 \\\n\t-expected-id 0x0401D093 \\\n\t-expected-id 0x0403D093\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap\nvirtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x1A 0x1B\n\nset XC6S_CFG_IN 0x05\nset XC6S_JSHUTDOWN 0x0d\nset XC6S_JPROGRAM 0x0b\nset XC6S_JSTART 0x0c\nset XC6S_BYPASS 0x3f\n\nproc xc6s_program {tap} {\n\techo \"DEPRECATED! use 'virtex2 program ...' not 'xc6s_program'\"\n\tglobal XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS\n\tirscan $tap $XC6S_JSHUTDOWN\n\tirscan $tap $XC6S_JPROGRAM\n\tirscan $tap $XC6S_JSTART\n\tirscan $tap $XC6S_BYPASS\n}\n\n#xtp038 and xc3sprog approach\nproc xc6s_program_iprog {tap} {\n\techo \"DEPRECATED! use 'virtex2 program ...' not 'xc6s_program_iprog'\"\n\tglobal XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN\n\tirscan $tap $XC6S_JSHUTDOWN\n\truntest 16\n\tirscan $tap $XC6S_CFG_IN\n\t# xtp038 IPROG 16bit flipped\n\tdrscan $tap 16 0xffff 16 0x9955 16 0x66aa 16 0x850c 16 0x7000 16 0x0004\n\tirscan $tap $XC6S_JSTART\n\truntest 32\n\tirscan $tap $XC6S_BYPASS\n\truntest 1\n}\n\nset XC6S_ISC_ENABLE 0x10\nset XC6S_ISC_DISABLE 0x16\nset XC6S_ISC_DNA 0x30\n\n# Get the \"Device DNA\" from the Spartan 6.\n# Most Xilinx FPGA devices contain an embedded, unique device identifier called\n# the \"Device DNA\". The identifier is nonvolatile, permanently programmed into\n# the FPGA, and is unchangeable providing a great serial / tracking number.\nproc xc6s_get_dna {tap} {\n\tglobal XC6S_ISC_ENABLE XC6S_ISC_DISABLE XC6S_ISC_DNA\n\tirscan $tap $XC6S_ISC_ENABLE\n\truntest 64\n\tirscan $tap $XC6S_ISC_DNA\n\t# Device DNA is 57 bits long, but we can only read 32bits at a time\n\t# with OpenOCD.\n\tset dna [drscan $tap 16 0 16 0 16 0 9 0]\n\truntest 64\n\tirscan $tap $XC6S_ISC_DISABLE\n\truntest 64\n\n\t# Convert the binary data into the order impact uses\n\tscan $dna \"%x %x %x %x\" v1 v2 v3 v4\n\tset bin_dna [string reverse [concat [format \"%09b\" $v4][format \"%016b\" $v3][format \"%016b\" $v2][format \"%016b\" $v1]]]\n\n\t# Return a hex version of binary\n\tscan [format \"0b%s\" $bin_dna] \"%i\" hex_dna\n\treturn $hex_dna\n}\n\n# Print out the \"Device DNA\" in the same format that impact uses.\nproc xc6s_print_dna {tap} {\n\tset hex_dna [xc6s_get_dna $tap]\n\n\tputs [format \"DNA = %57b (0x%x)\\n\" $hex_dna $hex_dna]\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc6v.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx virtex 6\n# https://www.xilinx.com/support/documentation/user_guides/ug360.pdf\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc6v\n}\n\n# the 4 top bits (28:31) are the die stepping. ignore it.\njtag newtap $_CHIPNAME tap -irlen 10 -ignore-version \\\n\t-expected-id 0x042A2093 \\\n\t-expected-id 0x042A4093 \\\n\t-expected-id 0x042A8093 \\\n\t-expected-id 0x042AC093 \\\n\t-expected-id 0x04244093 \\\n\t-expected-id 0x0424A093 \\\n\t-expected-id 0x0424C093 \\\n\t-expected-id 0x04250093 \\\n\t-expected-id 0x04252093 \\\n\t-expected-id 0x04256093 \\\n\t-expected-id 0x0423A093 \\\n\t-expected-id 0x04286093 \\\n\t-expected-id 0x04288093 \\\n\t-expected-id 0x042C4093 \\\n\t-expected-id 0x042CA093 \\\n\t-expected-id 0x042CC093 \\\n\t-expected-id 0x042D0093\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap\n# cfg_out cfg_in jprogb jstart jshutdown user1-4\nvirtex2 set_instr_codes $_CHIPNAME.pld 0x3C4 0x3C5 0x3CB 0x3CC 0x3CD\nvirtex2 set_user_codes $_CHIPNAME.pld 0x3C2 0x3C3 0x3E2 0x3E3\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc7.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx series 7 (spartan, artix, kintex, virtex)\n# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc7\n}\n\n# the 4 top bits (28:31) are the die stepping/revisions. ignore it.\njtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \\\n\t-expected-id 0x03622093 \\\n\t-expected-id 0x03620093 \\\n\t-expected-id 0x037C4093 \\\n\t-expected-id 0x0362F093 \\\n\t-expected-id 0x037C8093 \\\n\t-expected-id 0x037C7093 \\\n\t-expected-id 0x037C3093 \\\n\t-expected-id 0x0362E093 \\\n\t-expected-id 0x037C2093 \\\n\t-expected-id 0x0362D093 \\\n\t-expected-id 0x0362C093 \\\n\t-expected-id 0x03632093 \\\n\t-expected-id 0x03631093 \\\n\t-expected-id 0x03636093 \\\n\t-expected-id 0x03647093 \\\n\t-expected-id 0x0364C093 \\\n\t-expected-id 0x03651093 \\\n\t-expected-id 0x03747093 \\\n\t-expected-id 0x03656093 \\\n\t-expected-id 0x03752093 \\\n\t-expected-id 0x03751093 \\\n\t-expected-id 0x03671093 \\\n\t-expected-id 0x03667093 \\\n\t-expected-id 0x03682093 \\\n\t-expected-id 0x03687093 \\\n\t-expected-id 0x03692093 \\\n\t-expected-id 0x03691093 \\\n\t-expected-id 0x03696093\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart\nvirtex2 set_user_codes $_CHIPNAME.pld 0x02 0x03 0x22 0x23\n\nset XC7_JSHUTDOWN 0x0d\nset XC7_JPROGRAM 0x0b\nset XC7_JSTART 0x0c\nset XC7_BYPASS 0x3f\n\nproc xc7_program {tap} {\n\techo \"DEPRECATED! use 'virtex2 program ...' not 'xc7_program'\"\n\tglobal XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS\n\tirscan $tap $XC7_JSHUTDOWN\n\tirscan $tap $XC7_JPROGRAM\n\truntest 60000\n\t#JSTART prevents this from working...\n\t#irscan $tap $XC7_JSTART\n\truntest 2000\n\tirscan $tap $XC7_BYPASS\n\truntest 2000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc7v.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx series 7 (artix, kintex, virtex)\n# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf\n# https://bsdl.info/view.htm?sid=08e275a0cd3ac38988ca59b002289d77\n# https://bsdl.info/view.htm?sid=44dae65d3cf9593188ca59b002289d77\n#\n# this config file is for XC7VX1140T and XC7V2000T only.\n# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7vh870t.cfg or xilinx-xc7.cfg\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc7v\n}\n\n#0x036D5093: XC7VX1140T\n#0x036By093: XC7V2000T\n#y = xx11 = 3, 7, B or F\n\njtag newtap $_CHIPNAME tap -irlen 24 -ignore-version \\\n\t-expected-id 0x036B3093 -expected-id 0x036B7093 \\\n\t-expected-id 0x036BB093 -expected-id 0x036BF093 \\\n\t-expected-id 0x036D5093\n\n#CFG_OUT_SLR0 0x124924\n#CFG_IN_SLR0  0x164924\n#CFG_OUT_SLR1 0x904924\n#CFG_IN_SLR1  0x905924\n#CFG_OUT_SLR2 0x924124\n#CFG_IN_SLR2  0x924164\n#CFG_OUT_SLR3 0x924904\n#CFG_IN_SLR3  0x924905\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart\n# cfg_out cfg_in jprogb jstart jshutdown\nvirtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x2CB2CB 0x30C30C 0x34D34D\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc7vh580t.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx series 7 (artix, kintex, virtex)\n# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf\n# https://bsdl.info/view.htm?sid=65c6b2cfe1467b4988ca59b002289d77\n#\n# this config file is for xc7vh580t only.\n# for other virtex-7 devices use xilinx-xc7vh870t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc7vh580t\n}\n\njtag newtap $_CHIPNAME tap -irlen 22 -ignore-version -expected-id 0x036D9093\n\n#CFG_OUT_SLR0 0x0492A0\n#CFG_IN_SLR0  0x0592A0\n#CFG_OUT_SLR1 0x2412A0\n#CFG_IN_SLR1  0x2416A0\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart\n# cfg_out cfg_in jprogb jstart jshutdown\nvirtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFF 0x3FFFFF 0x0B2EA0 0x0C32A0 0x0D36A0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xc7vh870t.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# xilinx series 7 (artix, kintex, virtex)\n# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf\n# https://bsdl.info/view.htm?sid=d9ff0bb764df004588ca59b002289d77\n#\n# this config file is for xc7vh870t only.\n# for other virtex-7 devices use xilinx-xc7vh580t.cfg or xilinx-xc7v.cfg or xilinx-xc7.cfg\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xc7vh870t\n}\n\njtag newtap $_CHIPNAME tap -irlen 38 -ignore-version -expected-id 0x036DB093\n\n#CFG_OUT_SLR0 0x0492A092A0\n#CFG_IN_SLR0  0x0592A092A0\n#CFG_OUT_SLR1 0x2412A092A0\n#CFG_IN_SLR1  0x2416A092A0\n#CFG_OUT_SLR2 0x2492A012A0\n#CFG_IN_SLR2  0x2492A016A0\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart\n# cfg_out cfg_in jprogb jstart jshutdown\nvirtex2 set_instr_codes $_CHIPNAME.pld 0x3FFFFFFFFF 0x3FFFFFFFFF 0x0B2EA02EA0 0x0C32A032A0 0x0D36A036A0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xcf-p.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xcf\n}\n\n# IDs acquired from Xilinx's DS123.pdf\n# XCF08P <v>5057093\n# XCF16P <v>5058093\n# XCF32P <v>5059093\n# The 4 top bits (28:31) are the device revision. Ignore it.\njtag newtap $_CHIPNAME flash -irlen 16 -ignore-version \\\n\t-expected-id 0x05057093 \\\n\t-expected-id 0x05058093 \\\n\t-expected-id 0x05059093\n\ntarget create xcf.flash testee -chain-position $_CHIPNAME.flash\nflash bank XCF_P xcf 0 0 0 0 xcf.flash\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xcf-s.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xcf\n}\n\n# IDs acquired from Xilinx's DS123.pdf\n# XCF01S <v>5044093\n# XCF02S <v>5045093\n# XCF04S <v>5046093\n# The 4 top bits (28:31) are the device revision. Ignore it.\njtag newtap $_CHIPNAME flash -irlen 8 -ignore-version \\\n\t-expected-id 0x05044093 \\\n\t-expected-id 0x05045093 \\\n\t-expected-id 0x05046093\n\ntarget create xcf.flash testee -chain-position $_CHIPNAME.flash\nflash bank XCF_S xcf 0 0 0 0 xcf.flash\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xcr3256.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#xilinx coolrunner xcr3256\n#simple device - just configure a tap\njtag newtap xcr tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id  0x0494c093\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpld/xilinx-xcu.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Xilinx Ultrascale (Kintex, Virtex, Zynq)\n# https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xcu\n}\n\n# The various chips in the Ultrascale family have different IR length.\n# Set $CHIP before including this file to determine the device.\narray set _XCU_DATA {\n\tXCKU025         {0x03824093  6}\n\tXCKU035         {0x03823093  6}\n\tXCKU040         {0x03822093  6}\n\tXCKU060         {0x03919093  6}\n\tXCKU060_CIV     {0x0381b093  6}\n\tXCKU095         {0x03844093  6}\n\tXCKU095_CIV     {0x03845093  6}\n\tXCKU3P          {0x04A63093  6}\n\tXCKU5P          {0x04A62093  6}\n\tXCKU9P          {0x0484A093  6}\n\tXCKU11P         {0x04A4E093  6}\n\tXCKU11P_CIV     {0x04A51093  6}\n\tXCKU13P         {0x04A52093  6}\n\tXCKU15P         {0x04A56093  6}\n\tXCKU15P_CIV     {0x04A59093  6}\n\tXCVU065         {0x03939093  6}\n\tXCVU065_CIV     {0x0393b093  6}\n\tXCVU080         {0x03843093  6}\n\tXCVU080_CIV     {0x03845093  6}\n\tXCVU095         {0x03842093  6}\n\tXCVU2P          {0x04aea093  6}\n\tXCVU3P          {0x04B39093  6}\n\tXCVU3P_CIV      {0x04b3d093  6}\n\tXCAU10P         {0x04AC4033  6}\n\tXCAU10P_FFVB676 {0x04AC4093  6}\n\tXCAU15P         {0x04AC2033  6}\n\tXCAU15P_FFVB676 {0x04AC2093  6}\n\tXCAU20P         {0x04A65093  6}\n\tXCAU25P         {0x04A64093  6}\n\tXCKU5P_CIV      {0x04A64093  6}\n\tXCKU19P         {0x04ACF093  6}\n\tXCKU19P_CIV     {0x04AD3093  6}\n\tXCKU085         {0x0380F093 12}\n\tXCKU115         {0x0390D093 12}\n\tXCVU125         {0x0392D093 12}\n\tXCVU125_CIV     {0x0392f093 12}\n\tXCVU5P          {0x04B2B093 12}\n\tXCVU5P_CIV      {0x04b2f093 12}\n\tXCVU7P          {0x04B29093 12}\n\tXCVU7P_CIV      {0x04b2d093 12}\n\tXCVU160         {0x03933093 18}\n\tXCVU190         {0x03931093 18}\n\tXCVU440         {0x0396D093 18}\n\tXCVU440_CIV     {0x0396f093 18}\n\tXCVU9P          {0x04B31093 18}\n\tXCVU9P_CIV      {0x04b35093 18}\n\tXCVU11P         {0x04B49093 18}\n\tXCVU11P_CIV     {0x04b4f093 18}\n\tXCU200_FSGD2104 {0x04b37093 18}\n\tXCU250          {0x04b57093 24}\n\tXCVU13P         {0x04B51093 24}\n\tXCVU13P_CIV     {0x04b55093 24}\n\tXCVU15P         {0x04ba3093 24}\n\tXCVU19P         {0x04ba1093 24}\n\tXCVU19P_CIV     {0x04ba5093 24}\n}\n\nif { ![info exists CHIP] } {\n\terror \"set CHIP to one of \"[concat [array names _XCU_DATA]]\n}\n\nif { ![llength [array names _XCU_DATA $CHIP]] } {\n\terror \"unknown CHIP: \"$CHIP\n}\n\nset _EXPID [lindex $_XCU_DATA($CHIP) 0]\nset _IRLEN [lindex $_XCU_DATA($CHIP) 1]\n\n# the 4 top bits (28:31) are the die stepping/revisions. ignore it.\njtag newtap $_CHIPNAME tap -irlen $_IRLEN -ignore-version -expected-id $_EXPID\n\npld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap -no_jstart\n\n# set the correct instruction codes for jtag hub and\n# at least the right code for jprogb, jstart and jshutdown for SSI devices\nif { $_IRLEN == 6 } {\n\tvirtex2 set_user_codes $_CHIPNAME.pld 0x2 0x3 0x22 0x23\n} elseif {$_IRLEN == 12 } {\n\tputs \"loading bitstream through jtag will not work, but reprogram (refresh)\"\n\tvirtex2 set_instr_codes $_CHIPNAME.pld 0x905 0x904 0x2cb 0x30c 0x34d\n\tvirtex2 set_user_codes $_CHIPNAME.pld 0x0a4 0x0e4 0x8a4 0x8e4\n} elseif {$_IRLEN == 18 } {\n\tputs \"loading bitstream through jtag will not work, but reprogram (refresh)\"\n\tvirtex2 set_instr_codes $_CHIPNAME.pld 0x24905 0x24904 0x0b2cb 0x0c30c 0x0d34d\n\tvirtex2 set_user_codes $_CHIPNAME.pld 0x000a4 0x000e4 0x008a4 0x008e4\n} else {\n\tputs \"loading bitstream through jtag will not work, but reprogram (refresh)\"\n\tvirtex2 set_instr_codes $_CHIPNAME.pld 0x924905 0x924904 0x2cb2cb 0x30c30c 0x34d34d\n\tvirtex2 set_user_codes $_CHIPNAME.pld 0x0a4924 0x0e4924 0x8a4924 0x8e4924\n}\n\nset XCU_JSHUTDOWN 0x0d\nset XCU_JPROGRAM 0x0b\nset XCU_JSTART 0x0c\nset XCU_BYPASS 0x3f\n\nproc xcu_program {tap} {\n\techo \"DEPRECATED! use 'virtex2 program ...' not 'xcu_program'\"\n\tglobal XCU_JSHUTDOWN XCU_JPROGRAM XCU_JSTART XCU_BYPASS\n\tirscan $tap $XCU_JSHUTDOWN\n\tirscan $tap $XCU_JPROGRAM\n\truntest 60000\n\t#JSTART prevents this from working...\n\t#irscan $tap $XCU_JSTART\n\truntest 2000\n\tirscan $tap $XCU_BYPASS\n\truntest 2000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpu/arc/common.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2015, 2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\n# Things common to all ARCs\n\n# It is assumed that target is already halted.\nproc arc_common_reset { {target \"\"} } {\n        if { $target != \"\" } {\n                targets $target\n        }\n\n        halt\n\n        # 1. Interrupts are disabled (STATUS32.IE)\n        # 2. The status register flags are cleared.\n        # All fields, except the H bit, are set to 0 when the processor is Reset.\n\n        arc jtag set-aux-reg 0xA 0x1\n\n        # 3. The loop count, loop start, and loop end registers are cleared.\n        arc jtag set-core-reg 60 0\n        arc jtag set-aux-reg 0x2 0\n        arc jtag set-aux-reg 0x3 0\n\n        # Program execution begins at the address referenced by the four byte reset\n        # vector located at the interrupt vector base address, which is the first\n        # entry (offset 0x00) in the vector table.\n        set int_vector_base [arc jtag get-aux-reg 0x25]\n        set start_pc [read_memory $int_vector_base 32 1]\n        arc jtag set-aux-reg 0x6 $start_pc\n\n        # It is OK to do uncached writes - register cache will be invalidated by\n        # the reset_assert() function.\n}\n\n# vim:expandtab:\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpu/arc/em.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2015, 2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\nsource [find cpu/arc/v2.tcl]\n\nproc arc_em_examine_target { {target \"\"} } {\n\t# Will set current target\n\tarc_v2_examine_target $target\n}\n\nproc arc_em_init_regs { } {\n\tarc_v2_init_regs\n\n\t[target current] configure \\\n\t\t-event examine-end \"arc_em_examine_target [target current]\"\n}\n\n# Scripts in \"target\" folder should call this function instead of direct\n# invocation of arc_common_reset.\nproc arc_em_reset { {target \"\"} } {\n\tarc_v2_reset $target\n\n\t# Set DEBUG.ED bit to enable clock in actionpoint module.\n\t# This is specific to ARC EM.\n\tset debug [arc jtag get-aux-reg 5]\n\tif { !($debug & (1 << 20)) } {\n\t\tarc jtag set-aux-reg 5 [expr {$debug | (1 << 20)}]\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpu/arc/hs.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2015, 2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\nsource [find cpu/arc/v2.tcl]\n\nproc arc_hs_examine_target { target } {\n\t# Will set current target for us.\n\tarc_v2_examine_target $target\n}\n\nproc arc_hs_init_regs { } {\n\tarc_v2_init_regs\n\n\t[target current] configure \\\n\t\t-event examine-end \"arc_hs_examine_target [target current]\"\n}\n\n# Scripts in \"target\" folder should call this function instead of direct\n# invocation of arc_common_reset.\nproc arc_hs_reset { {target \"\"} } {\n\tarc_v2_reset $target\n\n\t# Invalidate L2 cache if there is one.\n\tset l2_config [$target arc jtag get-aux-reg 0x901]\n\t# Will return 0, if cache is not present and register doesn't exist.\n\tset l2_ctrl [$target arc jtag get-aux-reg 0x903]\n\tif { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } {\n\t\tputs \"L2 cache is present and not disabled\"\n\n\t\t# Wait until BUSY bit is 0.\n\t\tputs \"Invalidating L2 cache...\"\n\t\t$target arc jtag set-aux-reg 0x905 1\n\t\t# Dummy read of SLC_AUX_CACHE_CTRL bit, as described in:\n\t\t# https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854\n\t\tset l2_ctrl [$target arc jtag get-aux-reg 0x903]\n\t\tset l2_ctrl [$target arc jtag get-aux-reg 0x903]\n\t\twhile { ($l2_ctrl & 0x100) != 0 } {\n\t\t\tset l2_ctrl [$target arc jtag get-aux-reg 0x903]\n\t\t}\n\n\t\t# Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate\n\t\t# operation already flushed everything.\n\t\tif { ($l2_ctrl & 0x40) == 0 } {\n\t\t\tputs \"Flushing L2 cache...\"\n\t\t\t$target arc jtag set-aux-reg 0x904 1\n\t\t\tset l2_ctrl [$target arc jtag get-aux-reg 0x903]\n\t\t\tset l2_ctrl [$target arc jtag get-aux-reg 0x903]\n\t\t\twhile { [expr {$l2_ctrl & 0x100}] != 0 } {\n\t\t\t\tset l2_ctrl [$target arc jtag get-aux-reg 0x903]\n\t\t\t}\n\t\t}\n\n\t\tputs \"L2 cache has been flushed and invalidated.\"\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpu/arc/v2.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2015, 2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\nsource [find cpu/arc/common.tcl]\n\n# Currently 'examine_target' can only read JTAG registers and set properties -\n# but it shouldn't write any of registers - writes will be cached, but cache\n# will be invalidated before flushing after examine_target, and changes will be\n# lost.  Perhaps that would be fixed later - perhaps writes shouldn't be cached\n# after all.  But if write to register is really needed from TCL - then it\n# should be done via \"arc jtag\" for now.\nproc arc_v2_examine_target { {target \"\"} } {\n\t# Set current target, because OpenOCD event handlers don't do this for us.\n\tif { $target != \"\" } {\n\t\ttargets $target\n\t}\n\n\t# Those registers always exist. DEBUG and DEBUGI are formally optional,\n\t# however they come with JTAG interface, and so far there is no way\n\t# OpenOCD can communicate with target without JTAG interface.\n\tarc set-reg-exists identity pc status32 bta debug lp_start lp_end \\\n\t\teret erbta erstatus ecr efa\n\n\t# 32 core registers\n\tarc set-reg-exists \\\n\t\tr0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10 r11 r12 \\\n\t\tr13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 \\\n\t\tgp fp sp ilink r30 blink lp_count pcl\n\n\t# Actionpoints\n\tif { [arc get-reg-field ap_build version] == 5 } {\n\t\tset ap_build_type [arc get-reg-field ap_build type]\n\t\t# AP_BUILD.TYPE > 0b0110 is reserved in current ISA.\n\t\t# Current ISA supports up to 8 actionpoints.\n\t\tif { $ap_build_type < 8 } {\n\t\t\t# Two LSB bits of AP_BUILD.TYPE define amount of actionpoints:\n\t\t\t# 0b00 - 2 actionpoints\n\t\t\t# 0b01 - 4 actionpoints\n\t\t\t# 0b10 - 8 actionpoints\n\t\t\t# 0b11 - reserved.\n\t\t\tset ap_num [expr {0x2 << ($ap_build_type & 3)}]\n\t\t\t# Expression on top may produce 16 action points - which is a\n\t\t\t# reserved value for now.\n\t\t\tif { $ap_num < 16 } {\n\t\t\t\t# Enable actionpoint registers\n\t\t\t\tfor {set i 0} {$i < $ap_num} {incr i} {\n\t\t\t\t\tarc set-reg-exists ap_amv$i ap_amm$i ap_ac$i\n\t\t\t\t}\n\n\t\t\t\t# Set amount of actionpoints\n\t\t\t\tarc num-actionpoints $ap_num\n\t\t\t}\n\t\t}\n\t}\n\n\t# DCCM\n\tset dccm_version [arc get-reg-field dccm_build version]\n\tif { $dccm_version == 3 || $dccm_version == 4 } {\n\t\tarc set-reg-exists aux_dccm\n\t}\n\n\t# ICCM\n\tif { [arc get-reg-field iccm_build version] == 4 } {\n\t\tarc set-reg-exists aux_iccm\n\t}\n\n\t# MPU\n\tif { [arc get-reg-field mpu_build version] >= 2 &&\n\t\t [arc get-reg-field mpu_build version] <= 4 } {\n\t\tarc set-reg-exists mpu_en mpu_ecr\n\t\tset mpu_regions [arc get-reg-field mpu_build regions]\n\t\tfor {set i 0} {$i < $mpu_regions} {incr i} {\n\t\t\tarc set-reg-exists mpu_rdp$i mpu_rdb$i\n\t\t}\n\n\t\t# Secure MPU\n\t\tif { [arc get-reg-field mpu_build version] == 4 } {\n\t\t\tarc set-reg-exists mpu_index mpu_rstart mpu_rend mpu_rper\n\t\t}\n\t}\n}\n\nproc arc_v2_init_regs { } {\n\t# XML features\n\tset core_feature \"org.gnu.gdb.arc.core.v2\"\n\tset aux_min_feature \"org.gnu.gdb.arc.aux-minimal\"\n\tset aux_other_feature \"org.gnu.gdb.arc.aux-other\"\n\n\t# Describe types\n\t# Types are sorted alphabetically according to their name.\n\tarc add-reg-type-struct -name ap_build_t -bitfield version 0 7 \\\n\t\t-bitfield type 8 11\n\tarc add-reg-type-struct -name ap_control_t -bitfield at 0 3 -bitfield tt 4 5 \\\n\t\t-bitfield m 6 6 -bitfield p 7 7 -bitfield aa 8 8 -bitfield q 9 9\n\t# Cycles field added in version 4.\n\tarc add-reg-type-struct -name dccm_build_t -bitfield version 0 7 \\\n\t\t-bitfield size0 8 11 -bitfield size1 12 15 -bitfield cycles 17 19\n\n\tarc add-reg-type-struct -name debug_t \\\n\t\t-bitfield fh 1 1   -bitfield ah 2 2   -bitfield asr 3 10 \\\n\t\t-bitfield is 11 11 -bitfield ep 19 19 -bitfield ed 20 20 \\\n\t\t-bitfield eh 21 21 -bitfield ra 22 22 -bitfield zz 23 23 \\\n\t\t-bitfield sm 24 26 -bitfield ub 28 28 -bitfield bh 29 29 \\\n\t\t-bitfield sh 30 30 -bitfield ld 31 31\n\n\tarc add-reg-type-struct -name ecr_t \\\n\t\t-bitfield parameter 0 7 \\\n\t\t-bitfield cause 8 15 \\\n\t\t-bitfield vector 16 23 \\\n\t\t-bitfield U 30 30 \\\n\t\t-bitfield P 31 31\n\tarc add-reg-type-struct -name iccm_build_t -bitfield version 0 7 \\\n\t\t-bitfield iccm0_size0  8 11 -bitfield iccm1_size0 12 15 \\\n\t\t-bitfield iccm0_size1 16 19 -bitfield iccm1_size1 20 23\n\tarc add-reg-type-struct -name identity_t \\\n\t\t-bitfield arcver 0 7 -bitfield arcnum 8 15 -bitfield chipid 16 31\n\tarc add-reg-type-struct -name isa_config_t -bitfield version 0 7 \\\n\t\t-bitfield pc_size 8 11 -bitfield lpc_size 12 15 -bitfield addr_size 16 19 \\\n\t\t-bitfield b 20 20 -bitfield a 21 21 -bitfield n 22 22 -bitfield l 23 23 \\\n\t\t-bitfield c 24 27 -bitfield d 28 31\n\tarc add-reg-type-struct -name mpu_build_t -bitfield version 0 7 \\\n\t\t-bitfield regions 8 15 \\\n\t\t-bitfield s 16 16 \\\n\t\t-bitfield i 17 17\n\tarc add-reg-type-struct -name mpu_ecr_t \\\n\t\t-bitfield MR 0 7 \\\n\t\t-bitfield VT 8 9 \\\n\t\t-bitfield EC_CODE 16 31\n\tarc add-reg-type-struct -name mpu_en_t \\\n\t\t-bitfield UE  3  3 -bitfield UW   4  4 -bitfield UR 5 5 \\\n\t\t-bitfield KE  6  6 -bitfield KW   7  7 -bitfield KR 8 8 \\\n\t\t-bitfield S  15 15 -bitfield SID 16 23 \\\n\t\t-bitfield EN 30 30\n\tarc add-reg-type-struct -name mpu_index_t \\\n\t\t-bitfield I 0 3 -bitfield M 30 30 -bitfield D 31 31\n\tarc add-reg-type-struct -name mpu_rper_t \\\n\t\t-bitfield V 0 0 \\\n\t\t-bitfield UE 3 3 -bitfield UW 4 4 -bitfield UR 5 5 \\\n\t\t-bitfield KE 6 6 -bitfield KW 7 7 -bitfield KR 8 8 \\\n\t\t-bitfield S 15 15 -bitfield SID 16 23\n\tarc add-reg-type-flags -name status32_t \\\n\t\t-flag   H  0 -flag E0   1 -flag E1   2 -flag E2  3 \\\n\t\t-flag  E3  4 -flag AE   5 -flag DE   6 -flag  U  7 \\\n\t\t-flag   V  8 -flag  C   9 -flag  N  10 -flag  Z 11 \\\n\t\t-flag   L 12 -flag DZ  13 -flag SC  14 -flag ES 15 \\\n\t\t-flag RB0 16 -flag RB1 17 -flag RB2 18 \\\n\t\t-flag  AD 19 -flag US  20 -flag IE  31\n\n\t# Core registers\n\tset core_regs {\n\t\tr0       0  uint32\n\t\tr1       1  uint32\n\t\tr2       2  uint32\n\t\tr3       3  uint32\n\t\tr4       4  uint32\n\t\tr5       5  uint32\n\t\tr6       6  uint32\n\t\tr7       7  uint32\n\t\tr8       8  uint32\n\t\tr9       9  uint32\n\t\tr10      10 uint32\n\t\tr11      11 uint32\n\t\tr12      12 uint32\n\t\tr13      13 uint32\n\t\tr14      14 uint32\n\t\tr15      15 uint32\n\t\tr16      16 uint32\n\t\tr17      17 uint32\n\t\tr18      18 uint32\n\t\tr19      19 uint32\n\t\tr20      20 uint32\n\t\tr21      21 uint32\n\t\tr22      22 uint32\n\t\tr23      23 uint32\n\t\tr24      24 uint32\n\t\tr25      25 uint32\n\t\tgp       26 data_ptr\n\t\tfp       27 data_ptr\n\t\tsp       28 data_ptr\n\t\tilink    29 code_ptr\n\t\tr30      30 uint32\n\t\tblink    31 code_ptr\n\t\tr32      32 uint32\n\t\tr33      33 uint32\n\t\tr34      34 uint32\n\t\tr35      35 uint32\n\t\tr36      36 uint32\n\t\tr37      37 uint32\n\t\tr38      38 uint32\n\t\tr39      39 uint32\n\t\tr40      40 uint32\n\t\tr41      41 uint32\n\t\tr42      42 uint32\n\t\tr43      43 uint32\n\t\tr44      44 uint32\n\t\tr45      45 uint32\n\t\tr46      46 uint32\n\t\tr47      47 uint32\n\t\tr48      48 uint32\n\t\tr49      49 uint32\n\t\tr50      50 uint32\n\t\tr51      51 uint32\n\t\tr52      52 uint32\n\t\tr53      53 uint32\n\t\tr54      54 uint32\n\t\tr55      55 uint32\n\t\tr56      56 uint32\n\t\tr57      57 uint32\n\t\taccl     58 uint32\n\t\tacch     59 uint32\n\t\tlp_count 60 uint32\n\t\tlimm     61 uint32\n\t\treserved 62 uint32\n\t\tpcl      63 code_ptr\n\t}\n\tforeach {reg count type} $core_regs {\n\t\tarc add-reg -name $reg -num $count -core -type $type -g \\\n\t\t\t-feature $core_feature\n\t}\n\n\t# AUX min\n\tset aux_min {\n\t\t0x6 pc       code_ptr\n\t\t0x2 lp_start code_ptr\n\t\t0x3 lp_end   code_ptr\n\t\t0xA status32 status32_t\n\t}\n\tforeach {num name type} $aux_min {\n\t\tarc add-reg -name $name -num $num -type $type -feature $aux_min_feature -g\n\t}\n\n\t# AUX other\n\tset aux_other {\n\t\t0x004 identity\tidentity_t\n\t\t0x005 debug\t\tdebug_t\n\t\t0x018 aux_dccm\tint\n\t\t0x208 aux_iccm\tint\n\n\t\t0x220 ap_amv0\tuint32\n\t\t0x221 ap_amm0\tuint32\n\t\t0x222 ap_ac0\tap_control_t\n\t\t0x223 ap_amv1\tuint32\n\t\t0x224 ap_amm1\tuint32\n\t\t0x225 ap_ac1\tap_control_t\n\t\t0x226 ap_amv2\tuint32\n\t\t0x227 ap_amm2\tuint32\n\t\t0x228 ap_ac2\tap_control_t\n\t\t0x229 ap_amv3\tuint32\n\t\t0x22A ap_amm3\tuint32\n\t\t0x22B ap_ac3\tap_control_t\n\t\t0x22C ap_amv4\tuint32\n\t\t0x22D ap_amm4\tuint32\n\t\t0x22E ap_ac4\tap_control_t\n\t\t0x22F ap_amv5\tuint32\n\t\t0x230 ap_amm5\tuint32\n\t\t0x231 ap_ac5\tap_control_t\n\t\t0x232 ap_amv6\tuint32\n\t\t0x233 ap_amm6\tuint32\n\t\t0x234 ap_ac6\tap_control_t\n\t\t0x235 ap_amv7\tuint32\n\t\t0x236 ap_amm7\tuint32\n\t\t0x237 ap_ac7\tap_control_t\n\n\t\t0x400 eret\t\tcode_ptr\n\t\t0x401 erbta\t\tcode_ptr\n\t\t0x402 erstatus\tstatus32_t\n\t\t0x403 ecr\t\tecr_t\n\t\t0x404 efa\t\tdata_ptr\n\n\t\t0x409 mpu_en\tmpu_en_t\n\n\t\t0x412 bta\t\tcode_ptr\n\n\t\t0x420 mpu_ecr\tmpu_ecr_t\n\t\t0x422 mpu_rdb0\tint\n\t\t0x423 mpu_rdp0\tint\n\t\t0x424 mpu_rdb1\tint\n\t\t0x425 mpu_rdp1\tint\n\t\t0x426 mpu_rdb2\tint\n\t\t0x427 mpu_rdp2\tint\n\t\t0x428 mpu_rdb3\tint\n\t\t0x429 mpu_rdp3\tint\n\t\t0x42A mpu_rdb4\tint\n\t\t0x42B mpu_rdp4\tint\n\t\t0x42C mpu_rdb5\tint\n\t\t0x42D mpu_rdp5\tint\n\t\t0x42E mpu_rdb6\tint\n\t\t0x42F mpu_rdp6\tint\n\t\t0x430 mpu_rdb7\tint\n\t\t0x431 mpu_rdp7\tint\n\t\t0x432 mpu_rdb8\tint\n\t\t0x433 mpu_rdp8\tint\n\t\t0x434 mpu_rdb9\tint\n\t\t0x435 mpu_rdp9\tint\n\t\t0x436 mpu_rdb10\tint\n\t\t0x437 mpu_rdp10\tint\n\t\t0x438 mpu_rdb11\tint\n\t\t0x439 mpu_rdp11\tint\n\t\t0x43A mpu_rdb12\tint\n\t\t0x43B mpu_rdp12\tint\n\t\t0x43C mpu_rdb13\tint\n\t\t0x43D mpu_rdp13\tint\n\t\t0x43E mpu_rdb14\tint\n\t\t0x43F mpu_rdp14\tint\n\t\t0x440 mpu_rdb15\tint\n\t\t0x441 mpu_rdp15\tint\n\t\t0x448 mpu_index\tmpu_index_t\n\t\t0x449 mpu_rstart uint32\n\t\t0x44A mpu_rend\tuint32\n\t\t0x44B mpu_rper\tmpu_rper_t\n\t\t0x44C mpu_probe uint32\n\t}\n\tforeach {num name type} $aux_other {\n\t\tarc add-reg -name $name -num $num -type $type -feature $aux_other_feature\n\t}\n\n\t# AUX BCR\n\tset bcr {\n\t\t0x6D mpu_build\n\t\t0x74 dccm_build\n\t\t0x76 ap_build\n\t\t0x78 iccm_build\n\t\t0xC1 isa_config\n\t}\n\tforeach {num reg} $bcr {\n\t\tarc add-reg -name $reg -num $num -type ${reg}_t -bcr -feature $aux_other_feature\n\t}\n\n\t[target current] configure \\\n\t\t-event examine-end \"arc_v2_examine_target [target current]\"\n}\n\nproc arc_v2_reset { {target \"\"} } {\n\tarc_common_reset $target\n\n\t# Disable all actionpoints.  Cannot write via regcache yet, because it will\n\t# not be flushed and all changes to registers will get lost.  Therefore has\n\t# to write directly via JTAG layer...\n\tset num_ap [arc num-actionpoints]\n\tfor {set i 0} {$i < $num_ap} {incr i} {\n\t\tarc jtag set-aux-reg [expr {0x222 + $i * 3}] 0\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpu/arm/arm7tdmi.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset CPU_TYPE   arm\nset CPU_NAME   arm7tdmi\nset CPU_ARCH   armv4t\nset CPU_MAX_ADDRESS 0xFFFFFFFF\nset CPU_NBITS  32\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpu/arm/arm920.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset CPU_TYPE   arm\nset CPU_NAME   arm920\nset CPU_ARCH   armv4t\nset CPU_MAX_ADDRESS 0xFFFFFFFF\nset CPU_NBITS  32\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpu/arm/arm946.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset CPU_TYPE   arm\nset CPU_NAME   arm946\nset CPU_ARCH   armv5te\nset CPU_MAX_ADDRESS 0xFFFFFFFF\nset CPU_NBITS  32\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpu/arm/arm966.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset CPU_TYPE   arm\nset CPU_NAME   arm966\nset CPU_ARCH   armv5te\nset CPU_MAX_ADDRESS 0xFFFFFFFF\nset CPU_NBITS  32\n"
  },
  {
    "path": "openocd-win/openocd/scripts/cpu/arm/cortex_m3.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset CPU_TYPE   arm\nset CPU_NAME   cortex_m3\nset CPU_ARCH   armv7\nset CPU_MAX_ADDRESS 0xFFFFFFFF\nset CPU_NBITS  32\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/altera-10m50.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# file altera-10m50.cfg replaced by altera-max10.cfg\necho \"DEPRECATED: use altera-max10.cfg instead of deprecated altera-10m50.cfg\"\n\n#just to be backward compatible:\n#tap will be 10m50.tap instead of max10.tap:\nset CHIPNAME 10m50\nsource [find cpld/altera-max10.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/altera-arriaii.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Intel Arria II FPGA\n# Arria II Device Handbook\n# Table 11–2. 32-Bit IDCODE for Arria II Devices\n\n#GX:\n#EP2AGX45:  0x025120dd\n#EP2AGX65:  0x025020dd\n#EP2AGX95:  0x025130dd\n#EP2AGX125: 0x025030dd\n#EP2AGX190: 0x025140dd\n#EP2AGX260: 0x025040dd\n#EP2AGZ225: 0x024810dd\n#EP2AGZ300: 0x0240a0dd\n#EP2AGZ350: 0x024820dd\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME arriaii\n}\n\njtag newtap $_CHIPNAME tap -irlen 10 \\\n  -expected-id 0x025120dd -expected-id 0x025040dd \\\n  -expected-id 0x025020dd -expected-id 0x024810dd \\\n  -expected-id 0x025130dd -expected-id 0x0240a0dd \\\n  -expected-id 0x025030dd -expected-id 0x024820dd \\\n  -expected-id 0x025140dd\n\npld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/altera-cyclone10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Intel Cyclone 10 FPGA\n# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html\n# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf\n\n# GX085: 0x02e120dd\n# GX105: 0x02e320dd\n# GX150: 0x02e720dd\n# GX220: 0x02ef20dd\n# 10cl006: 0x020f10dd\n# 10cl010: 0x020f10dd\n# 10cl016: 0x020f20dd\n# 10cl025: 0x020f30dd\n# 10cl040: 0x020f40dd\n# 10cl055: 0x020f50dd\n# 10cl080: 0x020f60dd\n# 10cl120: 0x020f70dd\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME cyclone10\n}\n\njtag newtap $_CHIPNAME tap -irlen 10 \\\n  -expected-id 0x02e720dd -expected-id 0x02e120dd \\\n  -expected-id 0x02ef20dd -expected-id 0x02e320dd \\\n  -expected-id 0x020f10dd -expected-id 0x020f20dd \\\n  -expected-id 0x020f30dd -expected-id 0x020f40dd \\\n  -expected-id 0x020f50dd -expected-id 0x020f60dd \\\n  -expected-id 0x020f70dd\n\npld device intel $_CHIPNAME.tap cyclone10\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/altera-cycloneiii.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Intel Cyclone III FPGA\n# see Cyclone III Device Handbook\n# Table 12-2: Device IDCODE for Cyclone III Device Family\n\n#EP3C5     0x020f10dd\n#EP3C10    0x020f10dd\n#EP3C16    0x020f20dd\n#EP3C25    0x020f30dd\n#EP3C40    0x020f40dd\n#EP3C55    0x020f50dd\n#EP3C80    0x020f60dd\n#EP3C120   0x020f70dd\n#Cyclone III LS\n#EP3CLS70  0x027010dd\n#EP3CLS100 0x027000dd\n#EP3CLS150 0x027030dd\n#EP3CLS200 0x027020dd\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME cycloneiii\n}\n\njtag newtap $_CHIPNAME tap -irlen 10 \\\n  -expected-id 0x020f10dd -expected-id 0x020f20dd \\\n  -expected-id 0x020f30dd -expected-id 0x020f40dd \\\n  -expected-id 0x020f50dd -expected-id 0x020f60dd \\\n  -expected-id 0x020f70dd -expected-id 0x027010dd \\\n  -expected-id 0x027000dd -expected-id 0x027030dd \\\n  -expected-id 0x027020dd\n\npld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/altera-cycloneiv.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Intel Cyclone IV FPGA\n# see Cyclone IV Device Handbook\n# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices\n\n#EP4CE6       0x020f10dd\n#EP4CE10      0x020f10dd\n#EP4CE15      0x020f20dd\n#EP4CE22      0x020f30dd\n#EP4CE30      0x020f40dd\n#EP4CE40      0x020f40dd\n#EP4CE55      0x020f50dd\n#EP4CE75      0x020f60dd\n#EP4CE115     0x020f70dd\n#EP4CGX15     0x028010dd\n#EP4CGX22     0x028120dd\n#EP4CGX30 (3) 0x028020dd\n#EP4CGX30 (4) 0x028230dd\n#EP4CGX50     0x028130dd\n#EP4CGX75     0x028030dd\n#EP4CGX110    0x028140dd\n#EP4CGX150    0x028040dd\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME cycloneiv\n}\n\njtag newtap $_CHIPNAME tap -irlen 10 \\\n  -expected-id 0x020f10dd -expected-id 0x020f20dd \\\n  -expected-id 0x020f30dd -expected-id 0x020f40dd \\\n  -expected-id 0x020f50dd -expected-id 0x020f60dd \\\n  -expected-id 0x020f70dd -expected-id 0x028010dd \\\n  -expected-id 0x028120dd -expected-id 0x028020dd \\\n  -expected-id 0x028230dd -expected-id 0x028130dd \\\n  -expected-id 0x028030dd -expected-id 0x028140dd \\\n  -expected-id 0x028040dd\n\npld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/altera-cyclonev.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Intel Cyclone 5 FPGA\n# see Cyclone V Device Handbook\n# Table 9-1: IDCODE Information for Cyclone V Devices\n\n#5CEA2 0x02b150dd\n#5CEA4 0x02b050dd\n#5CEA5 0x02b220dd\n#5CEA7 0x02b130dd\n#5CEA9 0x02b140dd\n#5CGXC3 0x02b010dd\n#5CGXC4 0x02b120dd\n#5CGXC5 0x02b020dd\n#5CGXC7 0x02b030dd\n#5CGXC9 0x02b040dd\n#5CGTD5 0x02b020dd\n#5CGTD7 0x02b030dd\n#5CGTD9 0x02b040dd\n#5CSEA2 0x02d110dd\n#5CSEA4 0x02d010dd\n#5CSEA5 0x02d120dd\n#5CSEA6 0x02d020dd\n#5CSXC2 0x02d110dd\n#5CSXC4 0x02d010dd\n#5CSXC5 0x02d120dd\n#5CSXC6 0x02d020dd\n#5CSTD5 0x02d120dd\n#5CSTD6 0x02d020dd\n\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME cyclonev\n}\n\njtag newtap $_CHIPNAME tap -irlen 10 \\\n  -expected-id 0x02b150dd -expected-id 0x02b050dd \\\n  -expected-id 0x02b220dd -expected-id 0x02b130dd \\\n  -expected-id 0x02b140dd -expected-id 0x02b010dd \\\n  -expected-id 0x02b120dd -expected-id 0x02b020dd \\\n  -expected-id 0x02b030dd -expected-id 0x02b040dd \\\n  -expected-id 0x02d110dd -expected-id 0x02d010dd \\\n  -expected-id 0x02d120dd -expected-id 0x02d020dd\n\npld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/altera-ep3c10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# file altera-ep3c10.cfg replaced by altera-cycloneiii.cfg\necho \"DEPRECATED: use altera-cycloneiii.cfg instead of deprecated altera-ep3c10.cfg\"\n\n#just to be backward compatible:\n#tap will be ep3c10.tap instead of cycloneiii.tap:\nset CHIPNAME ep3c10\nsource [find fpga/altera-cycloneiii.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/efinix_titanium.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# efinix titanium\n# https://www.efinixinc.com/docs/an048-jtag-bst-titanium-v1.0.pdf\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME titanium\n}\n\njtag newtap $_CHIPNAME tap -irlen 5 -ignore-version \\\n\t-expected-id 0x10661A79 \\\n\t-expected-id 0x00360A79 \\\n\t-expected-id 0x10660A79 \\\n\t-expected-id 0x00681A79 \\\n\t-expected-id 0x00688A79 \\\n\t-expected-id 0x00682A79 \\\n\t-expected-id 0x0068CA79 \\\n\t-expected-id 0x00680A79 \\\n\t-expected-id 0x00684A79\n\npld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family titanium\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/efinix_trion.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# efinix trion\n# https://www.efinixinc.com/docs/an021-jtag-bst-trion-v1.0.pdf\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME trion\n}\n\njtag newtap $_CHIPNAME tap -irlen 4 -ignore-version \\\n\t-expected-id 0x00210A79 \\\n\t-expected-id 0x00240A79 \\\n\t-expected-id 0x00220A79\n\npld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family trion\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/gatemate.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# GateMateTM FPGA\n# https://www.colognechip.com/programmable-logic/gatemate/\n# https://colognechip.com/docs/ds1001-gatemate1-datasheet-latest.pdf\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME gatemate\n}\n\njtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \\\n\t-expected-id 0x20000001\n\npld create $_CHIPNAME.pld gatemate -chain-position $_CHIPNAME.tap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/gowin_gw1n.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Gowin FPGA IDCODEs\n# from JTAG Programming and Configuration Guide\n# http://cdn.gowinsemi.com.cn/TN653E.pdf\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME gw1n\n}\n\njtag newtap $_CHIPNAME tap -irlen 8 -ignore-version \\\n\t-expected-id 0x0900281B \\\n\t-expected-id 0x0900381B \\\n\t-expected-id 0x0100681B \\\n\t-expected-id 0x0300081B \\\n\t-expected-id 0x0300181B \\\n\t-expected-id 0x0120681B \\\n\t-expected-id 0x0100381B \\\n\t-expected-id 0x1100381B \\\n\t-expected-id 0x0100981B \\\n\t-expected-id 0x1100581B \\\n\t-expected-id 0x1100481B \\\n\t-expected-id 0x0100181B \\\n\t-expected-id 0x1100181B \\\n\t-expected-id 0x0100481B\n\npld create $_CHIPNAME.pld gowin -chain-position $_CHIPNAME.tap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/lattice_certus.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME certus\n}\n\n# Lattice Certus\n#\n# Certus NX LFD2NX-17     0x310f0043\n# Certus NX LFD2NX-40     0x310f1043\n\n\njtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \\\n\t-expected-id 0x310F1043 -expected-id 0x310F0043\n\npld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/lattice_certuspro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME certuspro\n}\n\n# Lattice CertusPro\n#\n# 0x010f4043 - LFCPNX-100\n# 0x     043 - LFCPNX-50\n\njtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \\\n\t-expected-id 0x010f4043\n#    -expected-id 0x01112043\n\npld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/lattice_ecp2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME ecp2\n}\n\n# Lattice ECP2 family\n# TAP IDs are extracted from BSDL files found on this page:\n# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP2M\n#\n# LFE2M20E: 0x01279043\n# LFE2M35E: 0x0127A043\n# LFE2M50E: 0x0127B043\n# LFE2M70E: 0x0127C043\n# LFE2M100E: 0x0127D043\n# LFEC2_6E: 0x01270043\n# LFEC2_12E: 0x01271043\n# LFEC2_20E: 0x01272043\n# LFEC2_35E: 0x01274043\n# LFEC2_50E: 0x01273043\n# LFEC2_70E: 0x01275043\n\njtag newtap $_CHIPNAME tap -irlen 8  \\\n\t-expected-id 0x01279043 -expected-id 0x0127A043 -expected-id 0x0127B043 \\\n\t-expected-id 0x0127C043 -expected-id 0x0127D043 -expected-id 0x01270043 \\\n\t-expected-id 0x01271043 -expected-id 0x01272043 -expected-id 0x01274043 \\\n\t-expected-id 0x01273043 -expected-id 0x01275043\n\npld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/lattice_ecp3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME ecp3\n}\n\n# Lattice ECP3 family\n# TAP IDs are extracted from BSDL files found on this page:\n# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP3\n#\n# LFE3_17:  0x01010043\n# LFE3_35:  0x01012043\n# LFE3_95:  0x01014043 and LFE3_70\n# LFE3_150: 0x01015043\n\njtag newtap $_CHIPNAME tap -irlen 8  \\\n\t-expected-id 0x01010043 -expected-id 0x01012043 \\\n\t-expected-id 0x01014043 -expected-id 0x01015043\n\npld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/lattice_ecp5.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME ecp5\n}\n\n# Lattice ECP5 family\n# TAP IDs are extracted from BSDL files found on this page:\n# https://www.latticesemi.com/Products/FPGAandCPLD/ECP5\n#\n# 0x01111043 - LAE5UM_25F/LFE5UM_25F\n# 0x01112043 - LAE5UM_45F/LFE5UM_45F\n# 0x01113043 - LAE5UM_85F/LFE5UM_85\n# 0x21111043 - LFE5U_12F\n# 0x41111043 - LFE5U_25F\n# 0x41112043 - LFE5U_45F\n# 0x41113043 - LFE5U_85F\n# 0x81111043 - LFE5UM5G-25\n# 0x81112043 - LFE5UM5G-45\n# 0x81113043 - LFE5UM5G-85\n\njtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \\\n\t-expected-id 0x01111043 -expected-id 0x01112043 -expected-id 0x01113043 \\\n\t-expected-id 0x21111043 -expected-id 0x41111043 -expected-id 0x41112043 \\\n\t-expected-id 0x41113043 -expected-id 0x81111043 -expected-id 0x81112043 \\\n\t-expected-id 0x81113043\n\npld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/lattice_machxo3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME machxo3\n}\n\n# Lattice MachXO3 family\n# TAP IDs are extracted from BSDL files found on this page:\n# https://www.latticesemi.com/Products/FPGAandCPLD/MachXO3\n#\n# 0x412b2043 - LCMXO3L_1300E_XXUWG36/XXMG121\n# 0x412b3043 - LCMXO3L_2100E_XXMG121/XXMG256/XXUWG49\n# 0x412b4043 - LCMXO3L_4300E_XXMG121/XXMG324/XXUWG81\n# 0x412b5043 - LCMXO3L_6900E_XXMG256/XXMG324\n# 0x412b6043 - LCMXO3L_9400E_XXBG256/XXMG256\n# 0x412bb043 - LCMXO3L_2100C_XXBG256\n# 0x412bc043 - LCMXO3L_4300C_XXBG256/XXBG324\n# 0x412bd043 - LCMXO3L_6900C_XXBG256/XXBG324/XXBG400\n# 0x412be043 - LCMXO3L_9400C_XXBG256/XXBG400/XXBG484\n# 0x612b2043 - LCMXO3LF_1300E_XXMG121/XXUWG36\n# 0x612b3043 - LCMXO3LF_2100E_XXMG121/XXMG256/XXUWG49\n# 0x612b4043 - LCMXO3LF_4300E_XXMG121/XXMG256/XXMG324/XXUWG81\n# 0x612b5043 - LCMXO3LF_6900E_XXMG256/XXMG324\n# 0x612b6043 - LCMXO3LF_9400E_XXBG256/XXMG256\n# 0x612bb043 - LCMXO3LF_2100C_XXBG256\n# 0x612bc043 - LCMXO3LF_4300C_XXBG256/XXBG324\n# 0x612bd043 - LCMXO3LF_6900C_XXBG256/XXBG324/XXBG400\n# 0x612be043 - LCMXO3LF_9400C_XXBG256/XXBG400/XXBG484\n# 0xc12b2043 - LCMXO3L_640E_XXMG121\n# 0xc12b4043 - LCMXO3L_2100E_XXMG324\n# 0xc12bb043 - LCMXO3L_1300C_XXBG256/XXMG256\n# 0xc12bc043 - LCMXO3L_2100C_XXBG324\n# 0xc12bd043 - LCMXO3L_4300C_XXBG400\n# 0xe12b2043 - LCMXO3LF_640E_XXMG121\n# 0xe12b3043 - LCMXO3LF_1300E_XXMG256\n# 0xe12b4043 - LCMXO3LF_2100E_XXMG324\n# 0xe12bb043 - LCMXO3LF_1300C_XXBG256\n# 0xe12bc043 - LCMXO3LF_2100C_XXBG324\n# 0xe12bd043 - LCMXO3LF_4300C_XXBG400\n\njtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \\\n\t-expected-id 0x412b2043 -expected-id 0x412b3043 -expected-id 0x412b4043 \\\n\t-expected-id 0x412b5043 -expected-id 0x412b6043 -expected-id 0x412bb043 \\\n\t-expected-id 0x412bc043 -expected-id 0x412bd043 -expected-id 0x412be043 \\\n\t-expected-id 0x612b2043 -expected-id 0x612b3043 -expected-id 0x612b4043 \\\n\t-expected-id 0x612b5043 -expected-id 0x612b6043 -expected-id 0x612bb043 \\\n\t-expected-id 0x612bc043 -expected-id 0x612bd043 -expected-id 0x612be043 \\\n\t-expected-id 0xc12b2043 -expected-id 0xc12b4043 -expected-id 0xc12bb043 \\\n\t-expected-id 0xc12bc043 -expected-id 0xc12bd043 -expected-id 0xe12b2043 \\\n\t-expected-id 0xe12b3043 -expected-id 0xe12b4043 -expected-id 0xe12bb043 \\\n\t-expected-id 0xe12bc043 -expected-id 0xe12bd043\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/xilinx-dna.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nproc xilinx_dna_addr {chip} {\n\tarray set addrs {\n\t\tSpartan6 0x30\n\t\tSeries7 0x17\n\t}\n\treturn $addrs($chip)\n}\n\n# Get the \"Device DNA\".\n# Most Xilinx FPGA devices contain an embedded, unique device identifier.\n# The identifier is nonvolatile, permanently programmed into\n# the FPGA, and is unchangeable providing a great serial / tracking number.\n# This function returns the DNA as a 64 bit integer with the 7 LSBs zeroed.\n# This is compatible with the FUSE DNA which contains all 64 bits.\nproc xilinx_get_dna {tap chip} {\n\tset XC7_ISC_ENABLE 0x10\n\tset XC7_ISC_DISABLE 0x16\n\tset XC7_ISC_DNA [xilinx_dna_addr $chip]\n\n\tirscan $tap $XC7_ISC_ENABLE\n\truntest 64\n\tirscan $tap $XC7_ISC_DNA\n\tscan [drscan $tap 32 0 32 0] \"%08x %08x\" hi lo\n\truntest 64\n\tirscan $tap $XC7_ISC_DISABLE\n\truntest 64\n\t# openocd interprets DR scans as LSB first, bit-reverse it\n\treturn [scan [string reverse [format \"%032b%032bb0\" $lo $hi]] \"%i\"]\n}\n\n# Print out the \"Device DNA\" in the same format that impact uses.\nproc xilinx_print_dna {dna} {\n\tset dna [expr {$dna >> 64 - 57}]\n\techo [format \"DNA = %057b (0x%016x)\" $dna $dna]\n}\n\nproc xc7_get_dna {tap} {\n\treturn [xilinx_get_dna $tap Series7]\n}\n\nproc xc6s_get_dna {tap} {\n\treturn [xilinx_get_dna $tap Spartan6]\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/fpga/xilinx-xadc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Xilinx XADC support for 7 Series FPGAs\n#\n# The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die\n# temperature, internal power supply rail voltages as well as external\n# voltages. The XADC is available both from fabric as well as through the\n# JTAG TAP.\n#\n# This code implements access through the JTAG TAP.\n#\n# https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf\n\n# build a 32 bit DRP command for the XADC DR\nproc xadc_cmd {cmd addr data} {\n\tarray set cmds {\n\t\tNOP 0x00\n\t\tREAD 0x01\n\t\tWRITE 0x02\n\t}\n\treturn [expr {($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)}]\n}\n\n# XADC register addresses\n# Some addresses (status registers 0-3) have special function when written to.\nproc XADC {key} {\n\tarray set addrs {\n\t\tTEMP 0x00\n\t\tLOCK 0x00\n\t\tVCCINT 0x01\n\t\tVCCAUX 0x02\n\t\tVAUXEN 0x02\n\t\tVPVN 0x03\n\t\tRESET 0x03\n\t\tVREFP 0x04\n\t\tVREFN 0x05\n\t\tVCCBRAM 0x06\n\t\tSUPAOFFS 0x08\n\t\tADCAOFFS 0x09\n\t\tADCAGAIN 0x0a\n\t\tVCCPINT 0x0d\n\t\tVCCPAUX 0x0e\n\t\tVCCODDR 0x0f\n\t\tVAUX0 0x10\n\t\tVAUX1 0x11\n\t\tVAUX2 0x12\n\t\tVAUX3 0x13\n\t\tVAUX4 0x14\n\t\tVAUX5 0x15\n\t\tVAUX6 0x16\n\t\tVAUX7 0x17\n\t\tVAUX8 0x18\n\t\tVAUX9 0x19\n\t\tVAUX10 0x1a\n\t\tVAUX11 0x1b\n\t\tVAUX12 0x1c\n\t\tVAUX13 0x1d\n\t\tVAUX14 0x1e\n\t\tVAUX15 0x1f\n\t\tSUPBOFFS 0x30\n\t\tADCBOFFS 0x31\n\t\tADCBGAIN 0x32\n\t\tFLAG 0x3f\n\t\tCFG0 0x40\n\t\tCFG1 0x41\n\t\tCFG2 0x42\n\t\tSEQ0 0x48\n\t\tSEQ1 0x49\n\t\tSEQ2 0x4a\n\t\tSEQ3 0x4b\n\t\tSEQ4 0x4c\n\t\tSEQ5 0x4d\n\t\tSEQ6 0x4e\n\t\tSEQ7 0x4f\n\t\tALARM0 0x50\n\t\tALARM1 0x51\n\t\tALARM2 0x52\n\t\tALARM3 0x53\n\t\tALARM4 0x54\n\t\tALARM5 0x55\n\t\tALARM6 0x56\n\t\tALARM7 0x57\n\t\tALARM8 0x58\n\t\tALARM9 0x59\n\t\tALARM10 0x5a\n\t\tALARM11 0x5b\n\t\tALARM12 0x5c\n\t\tALARM13 0x5d\n\t\tALARM14 0x5e\n\t\tALARM15 0x5f\n\t}\n\treturn $addrs($key)\n}\n\n# Select the XADC DR\nproc xadc_select {tap} {\n\tset XADC_IR 0x37\n\tirscan $tap $XADC_IR\n\truntest 10\n}\n\n# XADC transfer\nproc xadc_xfer {tap cmd addr data} {\n\tset ret [drscan $tap 32 [xadc_cmd $cmd $addr $data]]\n\truntest 10\n\treturn [expr \"0x$ret\"]\n}\n\n# XADC register write\nproc xadc_write {tap addr data} {\n\txadc_xfer $tap WRITE $addr $data\n}\n\n# XADC register read, non-pipelined\nproc xadc_read {tap addr} {\n\txadc_xfer $tap READ $addr 0\n\treturn [xadc_xfer $tap NOP 0 0]\n}\n\n# convert 16 bit register code from ADC measurement on\n# external voltages (VAUX) to Volt\nproc xadc_volt {code} {\n\treturn [expr {$code * 1./(1 << 16)}]\n}\n\n# convert 16 bit temperature measurement to Celsius\nproc xadc_temp {code} {\n\treturn [expr {$code * 503.975/(1 << 16) - 273.15}]\n}\n\n# convert 16 bit suppply voltage measurement to Volt\nproc xadc_sup {code} {\n\treturn [expr {$code * 3./(1 << 16)}]\n}\n\n# perform a single channel measurement using default settings\nproc xadc_single {tap ch} {\n\tset cfg0 [xadc_read $tap [XADC CFG0]]\n\tset cfg1 [xadc_read $tap [XADC CFG1]]\n\t# set channel\n\txadc_write $tap [XADC CFG0] $cfg0\n\t# single channel, disable the sequencer\n\txadc_write $tap [XADC CFG1] 0x3000\n\t# leave some time for the conversion\n\truntest 100\n\tset ret [xadc_read $tap [XADC $ch]]\n\t# restore CFG0/1\n\txadc_write $tap [XADC CFG0] $cfg0\n\txadc_write $tap [XADC CFG1] $cfg1\n\treturn $ret\n}\n\n# measure all internal voltages\nproc xadc_report {tap} {\n\txadc_select $tap\n\techo \"TEMP [format %.2f [xadc_temp [xadc_single $tap TEMP]]] C\"\n\tforeach ch [list VCCINT VCCAUX VCCBRAM VPVN VREFP VREFN \\\n\t\tVCCPINT VCCPAUX VCCODDR] {\n\t\techo \"$ch [format %.3f [xadc_sup [xadc_single $tap $ch]]] V\"\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/altera-usb-blaster.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Altera USB-Blaster\n#\n# http://www.altera.com/literature/ug/ug_usb_blstr.pdf\n#\n\nadapter driver usb_blaster\nusb_blaster lowlevel_driver ftdi\n# These are already the defaults.\n# usb_blaster vid_pid 0x09FB 0x6001\n# usb_blaster device_desc \"USB-Blaster\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/altera-usb-blaster2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Altera USB-Blaster II\n#\n\nadapter driver usb_blaster\nusb_blaster vid_pid 0x09fb 0x6010 0x09fb 0x6810\nusb_blaster lowlevel_driver ublast2\nusb_blaster firmware /path/to/quartus/blaster_6810.hex\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/angie.cfg",
    "content": "# SPDX-License-Identifier: BSD-3-Clause\n# Copyright (C) 2023 by NanoXplore, France - all rights reserved\n#\n# configuration file for ANGIE Adapter from NanoXplore.\n#\n\nadapter driver angie\nadapter speed 10000\nreset_config trst_and_srst trst_push_pull srst_open_drain\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/arm-jtag-ew.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Olimex ARM-JTAG-EW\n#\n# http://www.olimex.com/dev/arm-jtag-ew.html\n#\n\nadapter driver arm-jtag-ew\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ast2600-gpiod.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Use AST2600 GPIO through linuxgpiod\n#\n# +-----------+-------------+-------------+\n# | signal    | GPIO name   | gpio offset |\n# +-----------+-------------+-------------+\n# | TCK/SWCLK | GPIOI2      | 66          |\n# | TMS/SWDIO | GPIOI3      | 67          |\n# | TDI       | GPIOI1      | 65          |\n# | TDO       | GPIOI4      | 68          |\n# | nTRST     | GPIOI0      | 64          |\n# +-----------+-------------+-------------+\n\nadapter driver linuxgpiod\n\nadapter gpio trst 64 -chip 0\nadapter gpio tdi 65 -chip 0\nadapter gpio tck 66 -chip 0\nadapter gpio swclk 66 -chip 0\nadapter gpio tms 67 -chip 0\nadapter gpio swdio 67 -chip 0\nadapter gpio tdo 68 -chip 0\n\nreset_config trst_only separate trst_push_pull\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/at91rm9200.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Various Atmel AT91RM9200 boards\n#\n# TODO: URL?\n#\n\nadapter driver at91rm9200\nat91rm9200_device rea_ecr\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/beaglebone-jtag-native.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# BeagleBone native GPIO interface for JTAG\n#\n# This is best used with a fast buffer but it is also suitable for a direct\n# connection if the target voltage matches the host's IO voltage (typically\n# 3.3V) and the cable is short.\n#\n# DO NOT APPLY VOLTAGE TO THE GPIO PINS UNTIL SYS_RESETN IS HIGH.\n#\n# Do not forget the GND connection.\n\nadapter driver am335xgpio\n\n# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET\n# These depend on the system clock, calibrated for stock 1 GHz BeagleBoneBlack\n# am335xgpio speed SPEED_COEFF SPEED_OFFSET\nam335xgpio speed_coeffs 600000 575\n\n# BeagleBone pin P9_41\nadapter gpio tdo 20 -chip 0\n\n# BeagleBone pin P9_12\nadapter gpio tdi 28 -chip 1\n\n# BeagleBone pin P9_18\nadapter gpio tms 4 -chip 0\n\n# BeagleBone pin P9_22\nadapter gpio tck 2 -chip 0\n\n# BeagleBone pin P9_16\nadapter gpio led 19 -chip 1\n\n# BeagleBone pin P8_18\nadapter gpio srst 1 -chip 2\nreset_config srst_only srst_push_pull\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/beaglebone-swd-native.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# BeagleBone native GPIO interface for SWD\n#\n# This is best used with a fast buffer but it is also suitable for a direct\n# connection if the target voltage matches the host's IO voltage (typically\n# 3.3V) and the cable is short.\n#\n# DO NOT APPLY VOLTAGE TO THE GPIO PINS UNTIL SYS_RESETN IS HIGH.\n#\n# Do not forget the GND connection.\n\nadapter driver am335xgpio\n\n# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET\n# These depend on the system clock, calibrated for stock 1 GHz BeagleBoneBlack\n# am335xgpio speed SPEED_COEFF SPEED_OFFSET\nam335xgpio speed_coeffs 600000 575\n\n# BeagleBone pin P9_22\nadapter gpio swclk 2 -chip 0\n\n# BeagleBone pin P9_18\nadapter gpio swdio 4 -chip 0\n\n# BeagleBone pin P9_12\nadapter gpio swdio_dir 28 -chip 1\n\n# USR0 LED\nadapter gpio led 21 -chip 1\n\n# BeagleBone pin P8_18\nadapter gpio srst 1 -chip 2\nreset_config srst_only srst_push_pull\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/buspirate.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Buspirate with OpenOCD support\n#\n# http://dangerousprototypes.com/bus-pirate-manual/\n#\n\nadapter driver buspirate\n\n# you need to specify port on which BP lives\n#buspirate port /dev/ttyUSB0\n\n# communication speed setting\nbuspirate speed normal ;# or fast\n\n# voltage regulator Enabled = 1 Disabled = 0\n#buspirate vreg 0\n\n# pin mode normal or open-drain (jtag only)\n#buspirate mode normal\n\n# pullup state Enabled = 1 Disabled = 0\n#buspirate pullup 0\n\n# this depends on the cable, you are safe with this option\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/chameleon.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Amontec Chameleon POD\n#\n# http://www.amontec.com/chameleon.shtml\n#\n\nadapter driver parport\nparport cable chameleon\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/cmsis-dap.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# ARM CMSIS-DAP compliant adapter\n#\n# http://www.keil.com/support/man/docs/dapdebug/\n#\n\nadapter driver cmsis-dap\n\n# Optionally specify the serial number of CMSIS-DAP usb device.\n# adapter serial 02200201E6661E601B98E3B9\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/dln-2-gpiod.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Use DLN-2 GPIO through linuxgpiod\n#\n# +-----------+-------------+-------------+\n# | signal    | DLN-2       | gpio offset |\n# +-----------+-------------+-------------+\n# | nSRST     | J3.1  (PA0) | 0           |\n# | TDO       | J3.2  (PA1) | 1           |\n# | TCK/SWCLK | J3.3  (PA2) | 2           |\n# | TMS/SWDIO | J3.4  (PA3) | 3           |\n# | TDI       | J3.5  (PA4) | 4           |\n# | nTRST     | J3.6  (PA5) | 5           |\n# | LED       | J3.7  (PA6) | 6           |\n# | GND       | J3.12 (GND) |             |\n# +-----------+-------------+-------------+\n\nadapter driver linuxgpiod\n\nadapter gpio srst 0 -chip 0\nadapter gpio tdo 1 -chip 0\nadapter gpio tck 2 -chip 0\nadapter gpio swclk 2 -chip 0\nadapter gpio tms 3 -chip 0\nadapter gpio swdio 3 -chip 0\nadapter gpio tdi 4 -chip 0\nadapter gpio trst 5 -chip 0\nadapter gpio led 6 -chip 0\n\nreset_config trst_and_srst separate srst_push_pull\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/dummy.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Dummy interface (for testing purposes)\n#\n\nadapter driver dummy\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/esp_usb_bridge.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# ESP USB Bridge jtag adapter\n#\n\nadapter driver esp_usb_jtag\n\nespusbjtag vid_pid 0x303a 0x1002\nespusbjtag caps_descriptor 0x030A  # string descriptor index:10\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/esp_usb_jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Espressif builtin USB-JTAG adapter\n#\n\nadapter driver esp_usb_jtag\n\nespusbjtag vid_pid 0x303a 0x1001\nespusbjtag caps_descriptor 0x2000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/estick.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# eStick\n#\n# http://code.google.com/p/estick-jtag/\n#\n\nadapter driver opendous\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/flashlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# ST FlashLINK JTAG parallel cable\n#\n# http://www.st.com/internet/evalboard/product/94023.jsp\n# http://www.st.com/stonline/products/literature/um/7889.pdf\n#\n\nif { [info exists PARPORTADDR] } {\n   set _PARPORTADDR $PARPORTADDR\n} else {\n   set _PARPORTADDR 0\n}\n\nadapter driver parport\nparport port $_PARPORTADDR\nparport cable flashlink\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ft232r/radiona_ulx3s.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# This adapter is integrated in to Radiona ULX3S board:\n# \tboard/radiona_ulx3s.cfg\n# See schematics for the ft232r layout:\n# https://github.com/emard/ulx3s/blob/master/doc/schematics_v316.pdf\n\nadapter driver ft232r\nadapter speed 1000\nft232r vid_pid 0x0403 0x6015\nft232r tck_num DSR\nft232r tms_num DCD\nft232r tdi_num RI\nft232r tdo_num CTS\nft232r trst_num RTS\nft232r srst_num DTR\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ft232r.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nadapter driver ft232r\nadapter speed 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/100ask-openjtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# www.100ask.org OpenJTAG\n#\n# http://www.100ask.net/OpenJTAG.html\n#\n# Schematics are available from\n# https://blog.matthiasbock.net/wp-content/uploads/2015/04/100ask-JTAGv3.pdf\n#\n\nadapter driver ftdi\nftdi device_desc \"USB<=>JTAG&RS232\"\nftdi vid_pid 0x1457 0x5118\n\nftdi layout_init 0x0f08 0x0f1b\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/ashling-opella-ld-jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Ashling Opella-LD\n#\n# https://www.ashling.com/Opella-LD/\n#\n\nadapter driver ftdi\nftdi device_desc \"Opella-LD Debug Probe\"\nftdi vid_pid 0x0B6B 0x0040\nftdi tdo_sample_edge falling\nftdi layout_init 0x0A68 0xFF7B\nftdi channel 0\nftdi layout_signal JTAGOE -ndata 0x0010\nftdi layout_signal nTRST -data 0x0020\nftdi layout_signal nSRST -data 0x0040\nftdi layout_signal SWD_EN -data 0x0100\nftdi layout_signal SWDIO_OE -data 0x0200\nftdi layout_signal LED -ndata 0x0800\ntransport select jtag\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/ashling-opella-ld-swd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Ashling Opella-LD\n#\n# https://www.ashling.com/Opella-LD/\n#\n\nadapter driver ftdi\nftdi device_desc \"Opella-LD Debug Probe\"\nftdi vid_pid 0x0B6B 0x0040\nftdi layout_init 0x0860 0x0b7b\nftdi channel 0\nftdi layout_signal JTAGOE -data 0x0010\nftdi layout_signal nTRST -data 0x0020\nftdi layout_signal nSRST -data 0x0040\nftdi layout_signal SWD_EN -data 0x0100\nftdi layout_signal SWDIO_OE -data 0x0200\nftdi layout_signal LED -ndata 0x0800\ntransport select swd\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/axm0432.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Axiom axm0432\n#\n# http://www.axman.com\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"Symphony SoundBite\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0c08 0x0c2b\nftdi layout_signal nTRST -data 0x0800\nftdi layout_signal nSRST -data 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/c232hm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# FTDI USB Hi-Speed to MPSSE Cable\n#\n# http://www.ftdichip.com/Products/Cables/USBMPSSE.htm\n#\n# C232HM-DDHSL-0 and C232HM-EDSL-0 provide 3.3V and 5V on pin 1 (Red),\n# respectively.\n#\n# Adapter: http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_C232HM_MPSSE_CABLE.PDF\n# Chip: http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232H.pdf\n# See pinout/colors at end of this file.\n#\n# Tech notes:\n# http://www.ftdichip.com/Support/Documents/AppNotes/AN_135_MPSSE_Basics.pdf\n# http://www.ftdichip.com/Support/Documents/AppNotes/AN_129_FTDI_Hi_Speed_USB_To_JTAG_Example.pdf\n\nadapter driver ftdi\n#ftdi device_desc \"C232HM-DDHSL-0\"\n#ftdi device_desc \"C232HM-EDHSL-0\"\n\n# Common PID for FT232H\nftdi vid_pid 0x0403 0x6014\n\n# Layout\n# High data byte 0x40 configures red LED on ACBUS6 initially high (unlit, since active-low)\n# Low data byte 0x08 configures TMS on ACBUS3 initially high (asserted); TCK, TDI low\n# High direction byte 0x40 configures red LED on ACBUS6 as high (output)\n# Low direction byte 0x0b configures TDO on ACBUS2 as low (input)\nftdi layout_init 0x4008 0x400b\n\n# ---A*BUS-------CCCCCCCC|DDDDDDDD\n# --------\\______76543210|76543210\n# LED\t0x4000 = 01000000|00000000 = ACBUS6\n#GPIOL0\t0x0010 = 00000000|00010000 = ADBUS4\n#GPIOL1\t0x0020 = 00000000|00100000 = ADBUS5\n#GPIOL2\t0x0040 = 00000000|01000000 = ADBUS6\n#GPIOL3\t0x0080 = 00000000|10000000 = ADBUS7\n# -ndata treats the LED as active-low for expected behavior (toggle when transferring)\nftdi layout_signal LED -ndata 0x4000\n# Available for aliasing as desired\nftdi layout_signal GPIOL0 -data 0x0010 -oe 0x0010\nftdi layout_signal GPIOL1 -data 0x0020 -oe 0x0020\nftdi layout_signal GPIOL2 -data 0x0040 -oe 0x0040\nftdi layout_signal GPIOL3 -data 0x0080 -oe 0x0080\n\n# C232HM\t\tFT232H\tJTAG/Other\n# Num\tColor\tName\tFunc\n# 1\t\tRed\t\tVCC\t\tOptionally, can power the board if it is not using its own power supply.\n# 2\t\tOrange\tADBUS0\tTCK\n# 3\t\tYellow  ADBUS1\tTDI\n# 4\t\tGreen\tADBUS2\tTDO\n# 5\t\tBrown   ADBUS3\tTMS\n# 6\t\tGrey\tADBUS4\tGPIOL0\n# 7\t\tPurple\tADBUS5\tGPIOL1\n# 8\t\tWhite\tADBUS6\tGPIOL2\n# 9\t\tBlue\tADBUS7\tGPIOL3\n# 10\tBlack\tGND\t\tConnect to ground\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/cortino.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hitex Cortino\n#\n# http://www.hitex.com/index.php?id=cortino\n#\n\nadapter driver ftdi\nftdi device_desc \"Cortino\"\nftdi vid_pid 0x0640 0x0032\n\nftdi layout_init 0x0108 0x010b\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal nSRST -data 0x0200 -oe 0x0200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/digilent-hs1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# this supports JTAG-HS1 and JTAG-SMT1\n# (the later being the OEM on-board version)\n\nadapter driver ftdi\nftdi device_desc \"Digilent Adept USB Device\"\nftdi vid_pid 0x0403 0x6010\n# channel 1 does not have any functionality\nftdi channel 0\n# just TCK TDI TDO TMS, no reset\nftdi layout_init 0x0088 0x008b\nreset_config none\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/digilent-hs2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# this supports JTAG-HS2 (and apparently Nexys4 as well)\n\nadapter driver ftdi\nftdi device_desc \"Digilent Adept USB Device\"\nftdi vid_pid 0x0403 0x6014\n\nftdi channel 0\nftdi layout_init 0x00e8 0x60eb\n\nreset_config none\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_hs3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Digilent JTAG-HS3\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6014\nftdi device_desc \"Digilent USB Device\"\n\n# From Digilent support:\n# The SRST pin is [...] 0x20 and 0x10 is the /OE (active low output enable)\n\nftdi layout_init 0x2088 0x308b\nftdi layout_signal nSRST -data 0x2000 -noe 0x1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_smt2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Digilent JTAG-SMT2\n#\n# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,1053&Prod=JTAG-SMT2\n#\n# Config is based on data from\n# http://electronix.ru/forum/index.php?showtopic=114633&view=findpost&p=1215497 and ZedBoard schematics\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6014\n\nftdi layout_init 0x20e8 0x3feb\nftdi layout_signal nSRST -data 0x2000\nftdi layout_signal GPIO2 -data 0x2000\nftdi layout_signal GPIO1 -data 0x0200\nftdi layout_signal GPIO0 -data 0x0100\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/digilent_jtag_smt2_nc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Digilent JTAG-SMT2-NC\n#\n# http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/\n# https://reference.digilentinc.com/_media/jtag_smt2nc/jtag-smt2-nc_rm.pdf\n#\n# Based on reference sheet (above) and Xilinx KCU105 schematics\n# https://www.xilinx.com/products/boards-and-kits/kcu105.html#documentation\n#\n# Note that the digilent_jtag_smt2 layout does not work and hangs while\n# the ftdi device_desc from digilent_hs2 is wrong.\n\nadapter driver ftdi\nftdi device_desc \"Digilent USB Device\"\nftdi vid_pid 0x0403 0x6014\nftdi channel 0\nftdi layout_init 0x00e8 0x60eb\nreset_config none\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/dlp-usb1232h.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# DLP Design DLP-USB1232H USB-to-UART/FIFO interface module\n#\n# http://www.dlpdesign.com/usb/usb1232h.shtml\n#\n# Schematics for OpenOCD usage:\n# http://randomprojects.org/wiki/DLP-USB1232H_and_OpenOCD_based_JTAG_adapter\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on schematics and code\"\necho \"in ft2232.c. Please report your experience with this file to openocd-devel\"\necho \"mailing list, so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0008 0x000b\nftdi layout_signal nTRST -data 0x0010 -oe 0x0010\nftdi layout_signal nSRST -data 0x0040 -oe 0x0040\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/dp_busblaster.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Dangerous Prototypes - Bus Blaster\n#\n# The Bus Blaster has a configurable buffer between the FTDI FT2232H and the\n# JTAG header which allows it to emulate various debugger types. It comes\n# configured as a JTAGkey device.\n#\n# http://dangerousprototypes.com/docs/Bus_Blaster\n#\n\necho \"Info : If you need SWD support, flash KT-Link buffer from https://github.com/bharrisau/busblaster\nand use dp_busblaster_kt-link.cfg instead\"\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0c08 0x0f1b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/dp_busblaster_kt-link.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Dangerous Prototypes - Bus Blaster (with KT-Link buffer)\n#\n# The Bus Blaster has a configurable buffer between the FTDI FT2232H\n# and the JTAG header which allows it to emulate various debugger\n# types. This config works with KT-Link compatible implementation from\n# https://github.com/bharrisau/busblaster and is SWD-enabled.\n#\n# http://dangerousprototypes.com/docs/Bus_Blaster\n#\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x8c28 0xff3b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\nftdi layout_signal LED -ndata 0x8000\nftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000\nftdi layout_signal SWDIO_OE -ndata 0x1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/esp32_devkitj_v1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Driver for the FT2232H JTAG chip on the Espressif DevkitJ board\n# (and most other FT2232H and FT232H based boards)\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010 0x0403 0x6014\n\n# interface 1 is the uart\nftdi channel 0\n\n# TCK, TDI, TDO, TMS: ADBUS0-3\n# LEDs: ACBUS4-7\n\nftdi layout_init 0x0008 0xf00b\nftdi layout_signal LED -data 0x1000\nftdi layout_signal LED2 -data 0x2000\nftdi layout_signal LED3 -data 0x4000\nftdi layout_signal LED4 -data 0x8000\n\n# ESP32 series chips do not have a TRST input, and the SRST line is connected to the EN pin.\n# The target code doesn't handle SRST reset properly yet, so this is commented out:\n# ftdi layout_signal nSRST -oe 0x0020\n# reset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/esp32s2_kaluga_v1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Driver for the FT2232H JTAG chip on the Espressif Kaluga-1 ESP32-S2 board\n# (and most other FT2232H and FT232H based boards)\n#\n# JTAG DIP switch (labelled SW5 in the schematic) should be \"ON\" for lines\n# labelled TCK, TDO, TDI and TWS, to connect the FT2232H to the ESP32-S2.\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010 0x0403 0x6014\n\n# interface 1 is the uart\nftdi channel 0\n\n# TCK, TDI, TDO, TMS: ADBUS0-3\n# TRST/SRST: ADBUS5 (unused for now)\n# LEDs: ACBUS3-4 (inverted)\n\nftdi layout_init 0x0008 0x180b\nftdi layout_signal LED -ndata 0x0800\nftdi layout_signal LED2 -ndata 0x1000\n\n# ESP32* series chips do not have a TRST input, and the SRST line is connected\n# to the EN pin.\n# The target code doesn't handle SRST reset properly yet, so this is\n# commented out:\n# ftdi layout_signal nSRST -oe 0x0020\n# reset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/flossjtag-noeeprom.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# FlossJTAG\n#\n# http://github.com/esden/floss-jtag\n#\n# This is the pre v0.3 Floss-JTAG compatible config file. It can also be used\n# for newer versions of Floss-JTAG with empty or not populated EEPROM. If you\n# have several Floss-JTAG connected you have to use the USB ID to select a\n# specific one.\n#\n# If you have a Floss-JTAG WITH EEPROM that is programmed, use the\n# flossjtag.cfg file.\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0008 0x000b\nftdi layout_signal nTRST -data 0x0010 -oe 0x0010\nftdi layout_signal nSRST -data 0x0040 -oe 0x0040\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/flossjtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# FlossJTAG\n#\n# http://github.com/esden/floss-jtag\n#\n# This is the v0.3 and v1.0 Floss-JTAG compatible config file. It relies on the\n# existence of an EEPROM on Floss-JTAG containing a name. If you have several\n# Floss-JTAG adapters connected you can use the serial number to select a\n# specific device.\n#\n# If your Floss-JTAG does not have an EEPROM, or the EEPROM is empty, use the\n# flossjtag-noeeprom.cfg file.\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\nftdi device_desc \"FLOSS-JTAG\"\n# adapter serial \"FJ000001\"\n\nftdi layout_init 0x0008 0x180b\nftdi layout_signal nTRST -data 0x0010 -oe 0x0010\nftdi layout_signal nSRST -data 0x0040 -oe 0x0040\nftdi layout_signal LED -data 0x0800\nftdi layout_signal LED2 -data 0x1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/flyswatter.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TinCanTools Flyswatter\n#\n# http://web.archive.org/web/20150419072034/http://www.tincantools.com/JTAG/Flyswatter.html\n#\n\nadapter driver ftdi\nftdi device_desc \"Flyswatter\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0818 0x0cfb\nftdi layout_signal nTRST -data 0x0010\nftdi layout_signal nSRST -oe 0x0020\nftdi layout_signal LED -data 0x0c00\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/flyswatter2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TinCanTools Flyswatter2\n#\n# https://www.tincantools.com/product/flyswatter2/\n#\n\nadapter driver ftdi\nftdi device_desc \"Flyswatter2\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0538 0x057b\nftdi layout_signal LED -ndata 0x0400\nftdi layout_signal nTRST -data 0x0010\nftdi layout_signal nSRST -data 0x0020 -noe 0x0100\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/ft232h-module-swd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# ADAFRUIT FTDI FT232H as a SWD direct connect interface\n# Any FT232H based board may work\n#\n# http://www.ftdichip.com/Products/ICs/FT232H.htm\n#\n#\n\nadapter driver ftdi\n\nftdi vid_pid 0x0403 0x6014\n\n# data MSB..LSB       direction (1:out) MSB..LSB\n# 0000'0000'0011'0000 0000'0000'0011'1011\nftdi layout_init 0x0030 0x003b\n# 0xfff8 0xfffb\n# Those signal are only required on some platforms or may required to be\n# enabled explicitly (e.g. nrf5x chips).\nftdi layout_signal nSRST -data 0x0010 -oe 0x0010\nftdi layout_signal nTRST -data 0x0020 -oe 0x0020\n\n# swd enable\nftdi layout_signal SWD_EN -data 0\n# tri-state (configure as input) TDO/TIO when reading\nftdi layout_signal SWDIO_OE -data 0\n\ntransport select swd\n\n# re-configure TDO as tri-state\n#ftdi layout_signal TDO -data 0x0002 -oe 0x0002\n#ftdi layout_signal TDI -data 0x0004\n\n# Adafruit      FT232H    JTAG       SWD\n# Name  Pin     Name      Func       Func\n#  D0   J1-3    ADBUS0    TCK        SWDCLK\n#  D1   J1-4    ADBUS1    TDO/DI     SWDIO\n#  D2   J1-5    ADBUS2    TDI/DO     SWDIO\n#  D3   J1-6    ADBUS3    TMS        N/A\n#  D4   J1-7    ADBUS4    (GPIOL0)   /nSRST  optional module reset\n#  D5   J1-8    ADBUS5    (GPIOL1)   /nTRST  optional target reset\n#  D6   J1-9    ADBUS6    (GPIOL2)\n#  D7   J1-10   ADBUS7    (GPIOL3)\n#  C0   J2-1    ACBUS0    (GPIOH0)\n#  C1   J2-2    ACBUS1    (GPIOH1)\n#  C2   J2-3    ACBUS2    (GPIOH2)\n#  C3   J2-4    ACBUS3    (GPIOH3)\n#  C4   J2-5    ACBUS4    (GPIOH4)\n#  C5   J2-6    ACBUS5    (GPIOH5)\n#  C6   J2-7    ACBUS6    (GPIOH6)\n#  C7   J2-8    ACBUS7    (GPIOH7)\n#  C8   J2-9    ACBUS8\n#  C9   J2-10   ACBUS9\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/gw16042.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Gateworks GW16042 JTAG Dongle\n#\n# http://www.gateworks.com/\n#\n# Layout:  FTDI FT2232H\n#   ADBUS0 TCK\n#   ADBUS1 TDI\n#   ADBUS2 TDO (input)\n#   ADBUS3 TMS\n#   ADBUS4 nTRST\n#   ADBUS5 nSRST\n#   ADBUS6 OE (active high) for TRST, TDI, TMS, TCK\n#   ADBUS7 NC\n#   ACBUS0-7 NC\n#   BDBUS0 RXD\n#   BDBUS1 TXD (input)\n#\n\nadapter driver ftdi\nftdi device_desc \"USB-JTAG\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0058 0x007b\nftdi layout_signal nTRST -data 0x0010\nftdi layout_signal nSRST -oe 0x0020\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/hie-jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Hofstädtler Industrie-Electronic (HIE) JTAG Debugger\n#\n# https://www.hofstaedtler.com/jtag\n#\n\nadapter driver ftdi\nftdi channel 0\nftdi vid_pid 0x0403 0x6014\nftdi device_desc \"HIE JTAG Debugger\"\n\nftdi layout_init 0x0c08 0x4f1b\n\n# define both Reset signals\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\n\n# Toggle USB LED\nftdi layout_signal LED -ndata 0x4000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hilscher NXHX 10-ETM\n#\n# http://de.hilscher.com/products_details_hardware.html?p_id=P_4ce145a5983e6\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"NXHX 10-ETM\"\nftdi vid_pid 0x0640 0x0028\n\nftdi layout_init 0x0308 0x030b\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal nSRST -data 0x0200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hilscher NXHX 500-ETM\n#\n# http://de.hilscher.com/files_design/8/NXHX500-ETM_description_Rev01_EN.pdf\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"NXHX 500-ETM\"\nftdi vid_pid 0x0640 0x0028\n\nftdi layout_init 0x0308 0x030b\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal nSRST -data 0x0200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx500_re.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hilscher NXHX 500-RE\n#\n# http://de.hilscher.com/products_details_hardware.html?p_id=P_461ff2053bad1&bs=20\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"NXHX 500-RE\"\nftdi vid_pid 0x0640 0x0028\n\nftdi layout_init 0x0308 0x030b\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal nSRST -data 0x0200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hilscher NXHX 50-ETM\n#\n# http://de.hilscher.com/files_design/8/NXHX50-ETM_description_Rev01_EN.pdf\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"NXHX 50-ETM\"\nftdi vid_pid 0x0640 0x0028\n\nftdi layout_init 0x0308 0x030b\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal nSRST -data 0x0200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/hilscher_nxhx50_re.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hilscher NXHX 50-RE\n#\n# http://de.hilscher.com/products_details_hardware.html?p_id=P_483c0f582ad36&bs=20\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"NXHX50-RE\"\nftdi vid_pid 0x0640 0x0028\n\nftdi layout_init 0x0308 0x030b\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal nSRST -data 0x0200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/hitex_lpc1768stick.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hitex LPC1768-Stick\n#\n# http://www.hitex.com/?id=1602\n#\n\n\nadapter driver ftdi\nftdi device_desc \"LPC1768-Stick\"\nftdi vid_pid 0x0640 0x0026\n\nftdi layout_init 0x0388 0x038b\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal nSRST -data 0x0080 -noe 0x200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/hitex_str9-comstick.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hitex STR9-comStick\n#\n# http://www.hitex.com/index.php?id=383\n#\n\nadapter driver ftdi\nftdi device_desc \"STR9-comStick\"\nftdi vid_pid 0x0640 0x002c\n\nftdi layout_init 0x0108 0x010b\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal nSRST -data 0x0200 -oe 0x0200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/icebear.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Section5 ICEBear\n#\n# http://section5.ch/icebear\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"ICEbear JTAG adapter\"\nftdi vid_pid 0x0403 0xc140\n\nftdi layout_init 0x0028 0x002b\nftdi layout_signal nTRST -data 0x0010 -oe 0x0010\nftdi layout_signal nSRST -data 0x0020\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/imx8mp-evk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Configuration file for NXP MC-IMX8MP-EVK on-board internal JTAG\n#\n# Using this interface requires enabling \"remote mode\" for the board using the\n# NXP bcu tool (see https://github.com/NXPmicro/bcu)\n#\n#\tbcu set_gpio remote_en 1 -board=imx8mpevk\n#\n# The REMOTE_EN gpio is accessible through the same FTDI adapter but it's\n# behind an I2C GPIO expander.\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6011\nftdi channel 0\n\nftdi layout_init 0x00f8 0x000b\n\nftdi layout_signal RESET_B\t-data 0x0010 -oe 0x0010\n# Called SYS_nRST in schematics\nftdi layout_signal nSRST\t-data 0x0020 -oe 0x0020\nftdi layout_signal IO_nRST\t-data 0x0040 -oe 0x0040\nftdi layout_signal ONOFF_B\t-data 0x0080 -oe 0x0080\n\nftdi layout_signal GPIO1\t-data 0x0100 -oe 0x0100\nftdi layout_signal GPIO2\t-data 0x0200 -oe 0x0200\nftdi layout_signal GPIO3\t-data 0x0400 -oe 0x0400\nftdi layout_signal GPIO4\t-data 0x0800 -oe 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/incircuit-icprog.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# In-Circuit's ICprog OpenOCD JTAG Adapter\n# https://shop.in-circuit.de/product_info.php?products_id=112\n#\n# Schematics available at\n# http://wiki.in-circuit.de/images/0/06/610000158A_openocd.pdf\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0508 0x0f1b\nftdi layout_signal nSRST -noe 0x0400 -data 0x0800\nftdi layout_signal nTRST -noe 0x0100 -data 0x0200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/iotlab-usb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# This is the integrated adapter as found on the IoT-LAB boards\n# https://github.com/iot-lab/iot-lab/wiki\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0008 0x000b\nftdi layout_signal nTRST -data 0x0010 -oe 0x0010\nftdi layout_signal nSRST -data 0x0040 -oe 0x0040\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/isodebug.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# isodebug v1\n# 5 kV isolated JTAG/SWD + UART adapter by Unjo AB\n\nadapter driver ftdi\nftdi vid_pid 0x22b7 0x150d\n\nftdi layout_init 0x0ff8 0xfffb\n\nftdi layout_signal LED -ndata 0x0100\nftdi layout_signal nTRST -data 0x0200\nftdi layout_signal nSRST -noe 0x0400\nftdi layout_signal SWDIO_OE -data 0x0008\n\n# Mode signals, either of these needs to be high to drive the JTAG/SWD pins.\n# The power-on state is low for both signals but the init setting above sets\n# JTAG_EN high.\nftdi layout_signal SWD_EN -data 0x1000\nftdi layout_signal JTAG_EN -data 0x0800\n\n# In SWD mode, the JTAG_EN signal doubles as SWO_EN_N which switches the\n# second FTDI channel UART RxD to the SWO pin instead of the separate RxD\n# pin. Note that the default init state has this pin high so when OpenOCD\n# starts in SWD mode, SWO is by default disabled. To enable SWO tracing,\n# issue the command 'ftdi set_signal SWO_EN 1' where tracing is configured.\n# To switch back to using the separate UART, SWO_EN needs to be disabled\n# before exiting OpenOCD, or the adapter replugged.\nftdi layout_signal SWO_EN -nalias JTAG_EN\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# DISTORTEC JTAG-lock-pick Tiny 2\n#\n# http://www.distortec.com\n#\n\nadapter driver ftdi\nftdi device_desc \"JTAG-lock-pick Tiny 2\"\nftdi vid_pid 0x0403 0x8220\n\nftdi layout_init 0x8c28 0xff3b\nftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\nftdi layout_signal SWDIO_OE -ndata 0x1000\nftdi layout_signal LED -ndata 0x8000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/jtagkey.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Amontec JTAGkey\n#\n# http://www.amontec.com/jtagkey.shtml\n#\n\nadapter driver ftdi\nftdi device_desc \"Amontec JTAGkey\"\nftdi vid_pid 0x0403 0xcff8\n\nftdi layout_init 0x0c08 0x0f1b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/jtagkey2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Amontec JTAGkey2\n#\n# http://www.amontec.com/jtagkey2.shtml\n#\n\nadapter driver ftdi\nftdi device_desc \"Amontec JTAGkey-2\"\nftdi vid_pid 0x0403 0xcff8\n\nftdi layout_init 0x0c08 0x0f1b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/jtagkey2p.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Amontec JTAGkey2P\n#\n# http://www.amontec.com/jtagkey2p.shtml\n#\n\nadapter driver ftdi\nftdi device_desc \"Amontec JTAGkey-2P\"\nftdi vid_pid 0x0403 0xcff8\n\nftdi layout_init 0x0c08 0x0f1b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/kt-link.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Kristech KT-Link\n#\n# http://www.kristech.eu\n#\n\nadapter driver ftdi\nftdi device_desc \"KT-LINK\"\nftdi vid_pid 0x0403 0xbbe2\n\nftdi layout_init 0x8c28 0xff3b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\nftdi layout_signal LED -data 0x8000\nftdi layout_signal SWD_EN -ndata 0x0020 -oe 0x2000\nftdi layout_signal SWDIO_OE -ndata 0x1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/lambdaconcept_ecpix-5.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# This adapter is integrated in to LambdaConcept ECPIX-5 board:\n# \tinterface/ftdi/lambdaconcept_ecpix-5.cfg\n# See schematics for the ftdi layout:\n# http://docs.lambdaconcept.com/ecpix-5/_static/resources/SCH_ECPIX-5_R02.PDF\n\nadapter driver ftdi\nadapter speed 10000\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0xfff8 0xfffb\ntransport select jtag\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/lisa-l.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Lisa/L\n#\n# http://paparazzi.enac.fr/wiki/Lisa\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on schematics and code\"\necho \"in ft2232.c. Please report your experience with this file to openocd-devel\"\necho \"mailing list, so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"Lisa/L\"\nftdi vid_pid 0x0403 0x6010\nftdi channel 1\n\nftdi layout_init 0x0008 0x180b\nftdi layout_signal nTRST -data 0x0010 -oe 0x0010\nftdi layout_signal nSRST -data 0x0040 -oe 0x0040\nftdi layout_signal LED -data 0x1800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/luminary-icdi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Luminary Micro Stellaris LM3S9B9x Evaluation Kits\n# In-Circuit Debug Interface (ICDI) Board\n#\n# Essentially all Luminary debug hardware is the same, (with both\n# JTAG and SWD support compatible with ICDI boards.  This ICDI adapter\n# configuration is JTAG-only, but the same hardware handles SWD too.\n#\n# This is a discrete ftdi based debug board which supports ARM's\n# JTAG/SWD connectors in both backwards-compatible 20-pin format and\n# in the new-style compact 10-pin.  There's also an 8-pin connector\n# with serial port support.  It's included with LM3S9B9x eval boards.\n#\n# http://www.luminarymicro.com/products/ek-lm3s9b90.html\n# http://www.luminarymicro.com/products/ek-lm3s9b92.html\n#\n\nadapter driver ftdi\nftdi device_desc \"Luminary Micro ICDI Board\"\nftdi vid_pid 0x0403 0xbcda\n\nftdi layout_init 0x00a8 0x00eb\nftdi layout_signal nSRST -noe 0x0020\nftdi layout_signal SWD_EN -ndata 0x0080\nftdi layout_signal SWDIO_OE -data 0x0008\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/luminary-lm3s811.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Luminary Micro Stellaris LM3S811 Evaluation Kit\n#\n# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html\n#\n# NOTE:  this is only for boards *before* Rev C, which adds support\n# for SWO tracing with ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN signals.\n# The \"evb_lm3s811\" layout doesn't set up those signals.\n#\n# Rev C boards work more like the other Stellaris eval boards.  They\n# need to use the \"luminary_icdi\" layout to work correctly.\n#\n\nadapter driver ftdi\nftdi device_desc \"LM3S811 Evaluation Board\"\nftdi vid_pid 0x0403 0xbcd9\n\nftdi layout_init 0x0088 0x008b\nftdi layout_signal nSRST -data 0x0020 -oe 0x0020\nftdi layout_signal SWD_EN -ndata 0x0080\nftdi layout_signal SWDIO_OE -data 0x0008\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/luminary.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Luminary Micro Stellaris Evaluation Kits\n#\n# http://www.luminarymicro.com/products/evaluation_kits.html\n#\n# There are a number of evaluation kits for Stellaris Cortex-M3 chips.\n# Currently they all bundle ftdi based debug support.  When that is\n# used (instead of an external adapter), use this config file in one\n# of these two modes:\n#\n# - Eval board debug ... debug of the Stellaris chip via port A.\n#\n# - Other board debug ... same thing, but the board acts as a debug\n#   adapter for another board (using a standard ARM JTAG connector).\n#   The Stellaris chip stays in reset.\n#\n# Those support both JTAG and SWD.  SWD is an ARM-only two-wire debug\n# protocol; in 2009, OpenOCD does not support SWD.\n#\n# Port B of the ftdi chip is normally used as a serial link to the\n# Stellaris chip.  On most boards (but not older LM3S811 eval boards),\n# when SWD is used Port B may instead be used to read low-bandwidth\n# \"SWO trace\" data, including so-called \"printf style\" output from\n# firmware via the ITM module as well as profile data.\n#\n\nadapter driver ftdi\nftdi device_desc \"Stellaris Evaluation Board\"\nftdi vid_pid 0x0403 0xbcd9\n\nftdi layout_init 0x00a8 0x00eb\nftdi layout_signal nSRST -noe 0x0020\nftdi layout_signal SWD_EN -ndata 0x0080\nftdi layout_signal SWDIO_OE -data 0x0008\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/m53evk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# DENX M53EVK\n#\n# http://www.denx-cs.de/?q=M53EVK\n#\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi channel 0\nftdi layout_init 0x0008 0x000b\nftdi layout_signal nTRST -data 0x0010 -oe 0x0010\nftdi layout_signal nSRST -data 0x0020 -oe 0x0020\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/mbftdi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# MBFTDI\n#\n# http://www.marsohod.org/prodmbftdi\n#\n# Also the Marsohod2 and the Marsohod3 boards\n# include a built-in MBFTDI for FPGA programming.\n# See http://www.marsohod.org/prodmarsohod2\n# and http://www.marsohod.org/plata-marsokhod3 for details.\n#\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0008 0x000b\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/minimodule-swd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Supports SWD using the FT2232H or FT4232H minimodule.\n# Each can support 2 SWD interfaces.\n#\n# FT2232H or FT4232H minimodule channel 0 (Channel A)\n# Connector  FTDI              Target\n# Pin        Name\n# ---------  ------            ------\n# CN2-11     VIO               VDD_IO (Or connect to CN2-5 on the minimodule instead for a 3V3 interface)\n# CN2-2      GND               GND\n# CN2-7      ADBUS0 (TCK)      SWCLK\n# CN2-9      ADBUS2 (TDI/TDO)  SWDIO\n# CN2-10     ADBUS1 (TDO/TDI)  SWDIO\n# CN2-14     ADBUS4 (GPIOL0)   nRESET\n#\n# FT2232H minimodule channel 1 (Channel B)\n# FTDI       Target\n# ----       ------\n# CN2-11  -  VDD_IO\n# CN2-2   -  GND\n# CN3-26  -  SWCLK\n# CN3-25  -  SWDIO\n# CN3-24  -  SWDIO\n# CN3-21  -  nRESET\n#\n# FT4232H minimodule channel 1 (Channel B)\n# FTDI       Target\n# ----       ------\n# CN2-11  -  VDD_IO\n# CN2-2   -  GND\n# CN2-18  -  SWCLK\n# CN2-17  -  SWDIO\n# CN2-20  -  SWDIO\n# CN2-22  -  nRESET\n#\n\nadapter driver ftdi\n\n#Select your module type and channel\n\n#ftdi device_desc \"FT2232H MiniModule\"\nftdi vid_pid 0x0403 0x6010\n#ftdi channel 1\n\n#ftdi device_desc \"FT4232H MiniModule\"\n#ftdi vid_pid 0x0403 0x6011\n#ftdi channel 1\n\nftdi layout_init 0x0000 0x000b\nftdi layout_signal nSRST -data 0x0010 -oe 0x0010\nftdi layout_signal SWD_EN -data 0\nftdi layout_signal SWDIO_OE -data 0\n\ntransport select swd\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/minimodule.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# FTDI MiniModule\n#\n# http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf\n#\n\nadapter driver ftdi\nftdi device_desc \"FT2232H MiniModule\"\nftdi vid_pid 0x0403 0x6010\n\n# Every pin set as high impedance except TCK, TDI, TDO and TMS\nftdi layout_init 0x0008 0x000b\n\n# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)\n# This choice is arbitrary. Use other GPIO pin if desired.\nftdi layout_signal nSRST -data 0x0020 -oe 0x0020\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/minispartan6.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# https://www.scarabhardware.com/minispartan6/\n# https://github.com/scarabhardware/miniSpartan6-plus/raw/master/miniSpartan6%2B_Rev_B.pdf\nadapter driver ftdi\n# The miniSpartan6+ sadly doesn't have a custom device description, so we just\n# have to hope you got it right.\n#ftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n# interface 1 is the uart\nftdi channel 0\n# just TCK TDI TDO TMS, no reset\nftdi layout_init 0x0008 0x000b\nreset_config none\n# this generally works fast: the fpga can handle 30MHz, the spi flash can handle\n# 54MHz with simple read, no dummy cycles, and wait-for-write-completion\nadapter speed 30000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/miniwiggler.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Infineon DAP miniWiggler V3\n#\n# https://www.infineon.com/cms/en/product/evaluation-boards/kit_miniwiggler_3_usb/\n#\n# Layout:  FTDI FT2232\n#   ADBUS0 TCK\n#   ADBUS1 TDI\n#   ADBUS2 TDO\n#   ADBUS3 TMS\n#   ADBUS4 nOE (output enable)\n#   ADBUS5\n#   ADBUS6\n#   ADBUS7 Blue LED\n#\n#   ACBUS0 nTRST\n#   ACBUS1 nSRST\n#   ACUBS2\n#   ACBUS3\n#   ACBUS4\n#   ACBUS5\n#   ACBUS6\n#   ACBUS7\n#\n\nadapter driver ftdi\nftdi device_desc \"DAS JDS miniWiggler V3.1\"\nftdi vid_pid 0x058b 0x0043\n\nftdi channel 0\nftdi layout_init 0x0008 0x001b\nftdi layout_signal nTRST -data 0x0100 -oe 0x0100\nftdi layout_signal nSRST -data 0x0200 -oe 0x0200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/neodb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Openmoko USB JTAG/RS232 adapter\n#\n# http://wiki.openmoko.org/wiki/Debug_Board_v3\n#\n\nadapter driver ftdi\nftdi device_desc \"Debug Board for Neo1973\"\nftdi vid_pid 0x1457 0x5118\n\nftdi layout_init 0x0508 0x0f1b\nftdi layout_signal nTRST -data 0x0200 -noe 0x0100\nftdi layout_signal nSRST -data 0x0800 -noe 0x0400\nftdi layout_signal nNOR_WP -data 0x0010 -oe 0x0010\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/ngxtech.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NGX ARM USB JTAG\n#\n# http://shop.ngxtechnologies.com/product_info.php?cPath=26&products_id=30\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, but is assumed to work as this\"\necho \"interface uses the same layout as configs that were verified. Please report your\"\necho \"experience with this file to openocd-devel mailing list, so it could be marked\"\necho \"as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"NGX JTAG\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0508 0x0f1b\nftdi layout_signal nTRST -data 0x0200 -noe 0x0100\nftdi layout_signal nSRST -data 0x0800 -noe 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Olimex ARM JTAG SWD adapter\n# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/\n#\n\ntransport select swd\n\nftdi layout_signal SWD_EN -nalias nTRST\nftdi layout_signal SWDIO_OE -alias TMS\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Olimex ARM-USB-OCD-H\n#\n# http://www.olimex.com/dev/arm-usb-ocd-h.html\n#\n\nadapter driver ftdi\nftdi device_desc \"Olimex OpenOCD JTAG ARM-USB-OCD-H\"\nftdi vid_pid 0x15ba 0x002b\n\nftdi layout_init 0x0908 0x0b1b\nftdi layout_signal nSRST -oe 0x0200\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal LED -data 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Olimex ARM-USB-OCD\n#\n# http://www.olimex.com/dev/arm-usb-ocd.html\n#\n\nadapter driver ftdi\nftdi device_desc \"Olimex OpenOCD JTAG\"\nftdi vid_pid 0x15ba 0x0003\n\nftdi layout_init 0x0c08 0x0f1b\nftdi layout_signal nSRST -oe 0x0200\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal LED -data 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Olimex ARM-USB-TINY-H\n#\n# http://www.olimex.com/dev/arm-usb-tiny-h.html\n#\n\nadapter driver ftdi\nftdi device_desc \"Olimex OpenOCD JTAG ARM-USB-TINY-H\"\nftdi vid_pid 0x15ba 0x002a\n\nftdi layout_init 0x0808 0x0a1b\nftdi layout_signal nSRST -oe 0x0200\nftdi layout_signal nTRST -data 0x0100 -oe 0x0100\nftdi layout_signal LED -data 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/olimex-jtag-tiny.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Olimex ARM-USB-TINY\n#\n# http://www.olimex.com/dev/arm-usb-tiny.html\n#\n\nadapter driver ftdi\nftdi device_desc \"Olimex OpenOCD JTAG TINY\"\nftdi vid_pid 0x15ba 0x0004\n\nftdi layout_init 0x0808 0x0a1b\nftdi layout_signal nSRST -oe 0x0200\nftdi layout_signal nTRST -data 0x0100 -oe 0x0100\nftdi layout_signal LED -data 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/oocdlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Joern Kaipf's OOCDLink\n#\n# http://www.joernonline.de/contrexx2/cms/index.php?page=126\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, but is assumed to work as this\"\necho \"interface uses the same layout as configs that were verified. Please report your\"\necho \"experience with this file to openocd-devel mailing list, so it could be marked\"\necho \"as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"OOCDLink\"\nftdi vid_pid 0x0403 0xbaf8\n\nftdi layout_init 0x0508 0x0f1b\nftdi layout_signal nTRST -data 0x0200 -noe 0x0100\nftdi layout_signal nSRST -data 0x0800 -noe 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/opendous_ftdi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Opendous\n#\n# http://code.google.com/p/opendous/wiki/JTAG\n#\n# According to the website, it is similar to jtagkey, but it uses channel B\n# (and it has a different pid number).\n#\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\nftdi channel 1\n\nftdi layout_init 0x0c08 0x0f1b\nftdi layout_signal nTRST -data 0x0100 -noe 0x0400\nftdi layout_signal nSRST -data 0x0200 -noe 0x0800\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/openocd-usb-hs.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# embedded projects openocd usb adapter v3\n#\n# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14\n#\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232-HS\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0508 0x0f1b\nftdi layout_signal nTRST -data 0x0200 -noe 0x0100\nftdi layout_signal nSRST -data 0x0800 -noe 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/openocd-usb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hubert Hoegl's USB to JTAG\n#\n# http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html\n#\n\nadapter driver ftdi\nftdi device_desc \"Dual RS232\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0508 0x0f1b\nftdi layout_signal nTRST -data 0x0200 -noe 0x0100\nftdi layout_signal nSRST -data 0x0800 -noe 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/openrd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Marvell OpenRD\n#\n# http://www.marvell.com/products/embedded_processors/developer/kirkwood/openrd.jsp\n#\n\nadapter driver ftdi\nftdi device_desc \"OpenRD JTAGKey FT2232D B\"\nftdi vid_pid 0x0403 0x9e90\nftdi channel 0\n\nftdi layout_init 0x0608 0x0f1b\nftdi layout_signal nTRST -data 0x0200\nftdi layout_signal nSRST -noe 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/pipistrello.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# http://pipistrello.saanlima.com/\n# http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdf\nadapter driver ftdi\nftdi device_desc \"Pipistrello LX45\"\nftdi vid_pid 0x0403 0x6010\n# interface 1 is the uart\nftdi channel 0\n# just TCK TDI TDO TMS, no reset\nftdi layout_init 0x0008 0x000b\nreset_config none\n# this generally works fast: the fpga can handle 30MHz, the spi flash can handle\n# 54MHz with simple read, no dummy cycles, and wait-for-write-completion\nadapter speed 10000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/pls_spc5.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# PLS SPC5-UDESTK\n#\n# https://www.st.com/en/development-tools/spc5-udestk.html\n#\n# Reference the SPC56D Discovery schematics.\n#\n# Layout:  FTDI FT2232\n#   ADBUS0 TCK\n#   ADBUS1 TDI\n#   ADBUS2 TDO\n#   ADBUS3 TMS\n#   ADBUS4 TMS\n#   ADBUS5 RTCK\n#   ADBUS6\n#   ADBUS7 LED1\n#\n#   ACBUS0 nTRST\n#   ACBUS1 nSRST (external pull-down)\n#   ACUBS2\n#   ACBUS3\n#   ACBUS4\n#   ACBUS5 nSRST direction (input=L, output=H, external pull-down)\n#   ACBUS6 TMS direction (input=L, output=H, external pull-up)\n#   ACBUS7 LED2\n#\n\nadapter driver ftdi\nftdi device_desc \"PLS USB/JTAG Adapter for SPC5xxx\"\nftdi vid_pid 0x263d 0x4001\n\nftdi channel 0\nftdi layout_init 0x0008 0x000b\nftdi layout_signal nTRST -data 0x0100 -oe 0x0100\nftdi layout_signal nSRST -ndata 0x2000 -oe 0x2000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/redbee-econotag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Redwire Redbee-Econotag\n#\n# http://www.redwirellc.com/store/node/1\n#\n# The Redbee-Econotag has an onboard FT2232H with:\n#  - FT2232H channel A wired to mc13224v JTAG\n#  - FT2232H channel B wired to mc13224v UART1\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0c08 0x0c2b\nftdi layout_signal nTRST -data 0x0800\nftdi layout_signal nSRST -data 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/redbee-usb.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Redwire Redbee-USB\n#\n# http://www.redwirellc.com\n#\n# The Redbee-USB has an onboard FT2232H with:\n#  - FT2232H channel B wired to mc13224v JTAG\n#  - FT2232H channel A wired to mc13224v UART1\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\nftdi channel 1\n\nftdi layout_init 0x0c08 0x0c2b\nftdi layout_signal nTRST -data 0x0800\nftdi layout_signal nSRST -data 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/rowley-cc-arm-swd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Rowley ARM SWD Adapter\n# http://sites.fastspring.com/rowley/product/armswdadapter\n# https://drive.google.com/file/d/0Bzv7UpKpOQhnTUNNdzI5OUR4WGs/edit?usp=sharing\n#\n\ntransport select swd\n\nftdi layout_signal SWD_EN -nalias nTRST\nftdi layout_signal SWDIO_OE -alias TMS\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/sheevaplug.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Marvel SheevaPlug Development Kit\n#\n# http://www.marvell.com/products/embedded_processors/developer/kirkwood/sheevaplug.jsp\n#\n\nadapter driver ftdi\nftdi device_desc \"SheevaPlug JTAGKey FT2232D B\"\nftdi vid_pid 0x9e88 0x9e8f\nftdi channel 0\n\nftdi layout_init 0x0608 0x0f1b\nftdi layout_signal nTRST -data 0x0200 -noe 0x0100\nftdi layout_signal nSRST -data 0x0800 -noe 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/signalyzer-lite.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Xverve Signalyzer LITE (DT-USB-SLITE)\n#\n# http://www.signalyzer.com\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"Signalyzer LITE\"\nftdi vid_pid 0x0403 0xbca1\n\nftdi layout_init 0x0008 0x000b\nftdi layout_signal nTRST -data 0x0010 -oe 0x0010\nftdi layout_signal nSRST -data 0x0020 -oe 0x0020\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/signalyzer.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Xverve Signalyzer Tool (DT-USB-ST)\n#\n# http://www.signalyzer.com\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on code in ft2232.c.\"\necho \"Please report your experience with this file to openocd-devel mailing list,\"\necho \"so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"Signalyzer\"\nftdi vid_pid 0x0403 0xbca0\n\nftdi layout_init 0x0008 0x000b\nftdi layout_signal nTRST -data 0x0010 -oe 0x0010\nftdi layout_signal nSRST -data 0x0020 -oe 0x0020\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/sipeed-rv-debugger.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Interface file for BL702-based SIPEED RV Debugger\n#\n\nadapter driver ftdi\nadapter speed 6000\n\nftdi device_desc \"JTAG Debugger\"\nftdi vid_pid 0x0403 0x6010\nftdi layout_init 0x0008 0x001b\nftdi layout_signal nSRST -oe 0x0020 -data 0x0020\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/snps_sdp.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\n#\n# Synopsys SDP Mainboard has embdded FT2232 chip, which is similar to Digilent\n# HS-1, except that it uses channel B for JTAG communication, instead of\n# channel A.\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\nftdi layout_init 0x0088 0x008b\nftdi channel 1\n\n\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/steppenprobe.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Steppenprobe\n# https://github.com/diegoherranz/steppenprobe\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n\n# Initial Layout\nftdi layout_init 0x0058 0x99fb\n# Signal        Data    Direction       Notes\n# TCK           0       1 (out)\n# TDI           0       1 (out)\n# TDO           0       0 (in)\n# TMS           1       1 (out)         JTAG IEEE std recommendation\n# LED           1       1 (out)         LED off\n# SWD_EN        0       1 (out)         OpenOCD sets this high for SWD\n# SWDIO_OE      1       1 (out)         Ext. buffer tristated\n# SRST          0       1 (out)         Translates to nSRST=Z\n\n# Unused        0       1 (out)\n# GPIO_A        0       0 (in)\n# GPIO_B        0       0 (in)\n# Unused        0       1 (out)\n# Unused        0       1 (out)\n# GPIO_C        0       0 (in)\n# GPIO_D        0       0 (in)\n# Unused        0       1 (out)\n\n# Signals definition\nftdi layout_signal LED -ndata 0x0010\nftdi layout_signal SWD_EN -data 0x0020\nftdi layout_signal SWDIO_OE -ndata 0x0040\nftdi layout_signal nSRST -oe 0x0080\n\nftdi layout_signal GPIO_A -data 0x0200 -oe 0x0200 -input 0x0200\nftdi layout_signal GPIO_B -data 0x0400 -oe 0x0400 -input 0x0400\nftdi layout_signal GPIO_C -data 0x2000 -oe 0x2000 -input 0x2000\nftdi layout_signal GPIO_D -data 0x4000 -oe 0x4000 -input 0x4000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/stm32-stick.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Hitex STM32-PerformanceStick\n#\n# http://www.hitex.com/index.php?id=340\n#\n\nadapter driver ftdi\nftdi device_desc \"STM32-PerformanceStick\"\nftdi vid_pid 0x0640 0x002d\n\nftdi layout_init 0x0388 0x038b\nftdi layout_signal nTRST -data 0x0100\nftdi layout_signal nSRST -data 0x0080 -noe 0x200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/swd-resistor-hack.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Connect TDI to SWDIO via a suitable series resistor (220-470 Ohm or\n# so depending on the drive capability of the target and adapter);\n# connect TDO directly to SWDIO.\n#\n# You also need to have reliable GND connection between the target and\n# adapter. Vref of the adapter should be supplied with a voltage equal\n# to the target's (preferably connect it to Vcc). You can also\n# optionally connect nSRST. Leave everything else unconnected.\n#\n# FTDI                          Target\n# ----                          ------\n# 1  - Vref   ----------------- Vcc\n# 3  - nTRST  -\n# 4  - GND    ----------------- GND\n# 5  - TDI    ---/\\470 Ohm/\\--- SWDIO\n# 7  - TMS    -\n# 9  - TCK    ----------------- SWCLK\n# 11 - RTCK   -\n# 13 - TDO    ----------------- SWDIO\n# 15 - nSRST  - - - - - - - - - nRESET\n#\n\ntransport select swd\n\nftdi layout_signal SWD_EN -data 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/ti-icdi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# This is an FTDI-based debugging solution as found on some TI boards,\n# e.g. CC3200 LaunchPad.\n#\n# The schematics are identical to luminary-icdi (including SWD\n# support) but the USB IDs are different.\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0451 0xc32a\n\nftdi layout_init 0x00a8 0x00eb\nftdi layout_signal nSRST -noe 0x0020\nftdi layout_signal SWD_EN -ndata 0x0080\nftdi layout_signal SWDIO_OE -data 0x0008\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/tigard.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Tigard: An FTDI FT2232H-based multi-protocol tool for hardware hacking.\n# https://github.com/tigard-tools/tigard\n\nadapter driver ftdi\n\nftdi device_desc \"Tigard V1.1\"\nftdi vid_pid 0x0403 0x6010\n\nftdi channel 1\n\nftdi layout_init 0x0038 0x003b\nftdi layout_signal nTRST -data 0x0010\nftdi layout_signal nSRST -data 0x0020\n\n# This board doesn't support open-drain reset modes since its output buffer is\n# always enabled.\nreset_config srst_push_pull trst_push_pull\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/tumpa-lite.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TIAO USB Multi-Protocol Adapter (TUMPA) Lite\n#\n# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-lite-jtag-spi-i2c-serial.html\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x8a99\n\nftdi layout_init 0x0038 0x087b\nftdi layout_signal nTRST -data 0x0020 -oe 0x0020\nftdi layout_signal nSRST -data 0x0010 -oe 0x0010\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/tumpa.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TIAO USB Multi-Protocol Adapter (TUMPA)\n#\n# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-jtag-spi-i2c-serial.html\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x8a98 0x0403 0x6010\n\nftdi layout_init 0x0038 0x087b\nftdi layout_signal nTRST -data 0x0020\nftdi layout_signal nSRST -data 0x0010\n\nreset_config srst_push_pull\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/turtelizer2-revB.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# egnite Turtelizer 2 rev B (with SRST only)\n#\n# http://www.ethernut.de/en/hardware/turtelizer/index.html\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, it is based on schematics and code\"\necho \"in ft2232.c. Please report your experience with this file to openocd-devel\"\necho \"mailing list, so it could be marked as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"Turtelizer JTAG/RS232 Adapter\"\nftdi vid_pid 0x0403 0xbdc8\n\nftdi layout_init 0x0008 0x0c5b\nftdi layout_signal nSRST -oe 0x0040\nftdi layout_signal LED -data 0x0c00\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/turtelizer2-revC.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# egnite Turtelizer 2 revC (with TRST and SRST)\n#\n# http://www.ethernut.de/en/hardware/turtelizer/index.html\n#\n\nadapter driver ftdi\nftdi device_desc \"Turtelizer JTAG/RS232 Adapter\"\nftdi vid_pid 0x0403 0xbdc8\n\nftdi layout_init 0x0008 0x0c7b\nftdi layout_signal nTRST -oe 0x0020\nftdi layout_signal nSRST -oe 0x0040\nftdi layout_signal LED -ndata 0x0c00\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/um232h.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# FTDI UM232H as a JTAG interface\n#\n# http://www.ftdichip.com/Products/Modules/DevelopmentModules.htm#UM232H\n#\n# This should also work with a UM232H-B, but that has not been tested.\n# Note that UM232H and UM232H-B are 3.3V only.\n#\n\nadapter driver ftdi\n#ftdi device_desc \"UM232H\"\nftdi vid_pid 0x0403 0x6014\n\nftdi layout_init 0xfff8 0xfffb\nftdi layout_signal nTRST -data 0x0100 -oe 0x0100\nftdi layout_signal nSRST -data 0x0200 -oe 0x0200\n\n# UM232H        FT232H    JTAG\n# Name  Pin     Name      Func\n# AD0   J2-6    ADBUS0    TCK\n# AD1   J2-7    ADBUS1    TDI\n# AD2   J2-8    ADBUS2    TDO\n# AD3   J2-9    ADBUS3    TMS\n# AD4   J2-10   ADBUS4    (GPIOL0)\n# AD5   J2-11   ADBUS5    (GPIOL1)\n# AD6   J2-12   ADBUS6    (GPIOL2)\n# AD7   J2-13   ADBUS7    (GPIOL3)\n# AD0   J1-14   ACBUS0    /TRST\n# AD1   J1-13   ACBUS1    /SRST\n# AD2   J1-12   ACBUS2    (GPIOH2)\n# AD3   J1-11   ACBUS3    (GPIOH3)\n# AD4   J1-10   ACBUS4    (GPIOH4)\n# AD5   J1-9    ACBUS5    (GPIOH5)\n# AD6   J1-8    ACBUS6    (GPIOH6)\n# AD7   J1-7    ACBUS7    (GPIOH7)\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/vpaclink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Voipac VPACLink\n#\n# http://voipac.com/27M-JTG-000\n#\n\necho \"WARNING!\"\necho \"This file was not tested with real interface, but is assumed to work as this\"\necho \"interface uses the same layout as configs that were verified. Please report your\"\necho \"experience with this file to openocd-devel mailing list, so it could be marked\"\necho \"as working or fixed.\"\n\nadapter driver ftdi\nftdi device_desc \"VPACLink\"\nftdi vid_pid 0x0403 0x6010\n\nftdi layout_init 0x0508 0x0f1b\nftdi layout_signal nTRST -data 0x0200 -noe 0x0100\nftdi layout_signal nSRST -data 0x0800 -noe 0x0400\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/xds100v2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments XDS100v2\n#\n# http://processors.wiki.ti.com/index.php/XDS100#XDS100v2_Features\n#\n# Detailed documentation is available only as CPLD verilog source code\n# to the registered TI users.\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0xa6d0 0x0403 0x6010\n\nftdi layout_init 0x0038 0x597b\n\n#  8000 z - unused\n#  4000 0 > CPLD loopback          (all target side pins high-Z)\n#  2000 z < !( cable connected )   (open drain on CPLD side for $reasons)\n#  1000 0 > EMU1_oe\n#\n#   800 0 > PWR_RST = clear power-loss flag on rising edge\n#   400 z < !( power-loss flag )\n#   200 z < nSRST\n#   100 0 > nSRST_oe\n#\n#    80 z < RTCK\n#    40 0 > EMU0_oe\n#    20 1 > EMU_EN\n#    10 1 > nTRST\n#\n#     8 1 > TMS\n#     4 z < TDO\n#     2 0 > TDI\n#     1 0 > TCK\n#\n# As long as the power-loss flag is set, all target-side pins are\n# high-Z except the EMU-pins for which the opposite holds unless\n# EMU_EN is high.\n#\n# To use wait-in-reset, drive EMU0 low at power-on reset. If the\n# target normally reuses EMU0 for other purposes, clear EMU_EN to\n# keep the EMU pins high-Z until the target is power-cycled.\n#\n# The LED only turns off at USB suspend, which is also the only way to\n# set the power-loss flag manually. (Can be done in software e.g. by\n# changing the USB configuration to zero.)\n#\n\nftdi layout_signal nTRST -data 0x0010\nftdi layout_signal nSRST -oe 0x0100\nftdi layout_signal EMU_EN -data 0x0020\nftdi layout_signal EMU0 -oe 0x0040\nftdi layout_signal EMU1 -oe 0x1000\nftdi layout_signal PWR_RST -data 0x0800\nftdi layout_signal LOOPBACK -data 0x4000\n\necho \"\\nInfo : to use this adapter you MUST add ``init; ftdi set_signal PWR_RST 1; jtag arp_init'' to the end of your config file!\\n\"\n# note: rising edge on PWR_RST is also needed after power-cycling the\n# target\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/xds100v3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments XDS100 ver 3.0\n#\n# http://processors.wiki.ti.com/index.php/XDS100\n#\n\n# Version 3.0 is the same as 2.0 as far as OpenOCD is concerned\nsource [find interface/ftdi/xds100v2.cfg]\n\n# The USB ids are different.\nftdi vid_pid 0x0403 0xa6d1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ftdi/xt_kc705_ml605.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Xilinx KC705 / ML605 with Xtensa daughtercard; onboard USB/FT2232\n#\n\nadapter driver ftdi\nftdi vid_pid 0x0403 0x6010\n# Specify \"adapter serial <identifier>\" here as needed\n\nftdi layout_init 0x0010 0x007b\nftdi layout_signal nTRST -data 0x0010\nftdi layout_signal nSRST -ndata 0x0020\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/imx-native.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Config for using NXP IMX CPU\n#\n# This is best used with a fast enough buffer but also\n# is suitable for direct connection if the target voltage\n# matches to host voltage and the cable is short enough.\n#\n#\n\nadapter driver imx_gpio\n\n# For most IMX processors 0x0209c000\nimx_gpio_peripheral_base 0x0209c000\n\n# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET\n# These depend on system clock, calibrated for IMX6UL@528MHz\n# imx_gpio_speed SPEED_COEFF SPEED_OFFSET\nimx_gpio_speed_coeffs 50000 50\n\n# Each of the JTAG lines need a gpio number set: tck tms tdi tdo.\n# Example configuration:\n# imx_gpio_jtag_nums 6 7 8 9\n\n# SWD interface pins: swclk swdio\n# Example configuration:\nimx_gpio_swd_nums 1 6\n\n# imx_gpio_trst_num 10\n# reset_config trst_only\n\n# imx_gpio_srst_num 11\n# reset_config srst_only srst_push_pull\n\n# or if you have both connected,\n# reset_config trst_and_srst srst_push_pull\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/jlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# SEGGER J-Link\n#\n# http://www.segger.com/jlink.html\n#\n\nadapter driver jlink\n\n# The serial number can be used to select a specific device in case more than\n# one is connected to the host.\n#\n# Example: Select J-Link with serial number 123456789\n#\n# adapter serial 123456789\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/jtag_dpi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Provide support for the Cadence JTAG BFM\n#\n# Copyright (c) 2020, Ampere Computing LLC\n#\n\nadapter driver jtag_dpi\n\n# Set the DPI JTAG server port\nif { [info exists DPI_PORT] } {\n   set _DPI_PORT $DPI_PORT\n} else {\n   set _DPI_PORT 5555\n}\n\n# Set the DPI JTAG server address\nif { [info exists DPI_ADDRESS] } {\n   set _DPI_ADDRESS $DPI_ADDRESS\n} else {\n   set _DPI_ADDRESS \"127.0.0.1\"\n}\n\njtag_dpi set_port $_DPI_PORT\njtag_dpi set_address $_DPI_ADDRESS\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/jtag_hat_rpi2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Blinkinlabs JTAG_Hat\n#\n# https://github.com/blinkinlabs/jtag_hat\n#\n\nadapter driver bcm2835gpio\n\nbcm2835gpio peripheral_base 0x3F000000\n\n# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET\n# These depend on system clock, calibrated for stock 700MHz\n# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET\nbcm2835gpio speed_coeffs 146203 36\n\n# Each of the JTAG lines need a gpio number set: tck tms tdi tdo\n# Header pin numbers: 23 22 19 21\nadapter gpio tck -chip 0 11\nadapter gpio tms -chip 0 25\nadapter gpio tdi -chip 0 10\nadapter gpio tdo -chip 0 9\n\n# Each of the SWD lines need a gpio number set: swclk swdio\n# Header pin numbers: 23 22\nadapter gpio swclk -chip 0 11\nadapter gpio swdio -chip 0 25\n\n# Direction pin for SWDIO level shifting buffer\nadapter gpio swdio_dir -chip 0 6\n\n# If you define trst or srst, use appropriate reset_config\n# Header pin numbers: TRST - 26, SRST - 18\n\nadapter gpio trst -chip 0 7\n#reset_config trst_only\n\nadapter gpio srst -chip 0 24\n#reset_config srst_only\n\n# or if you have both connected\n#reset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/jtag_vpi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nadapter driver jtag_vpi\n\n# Set the VPI JTAG server port\nif { [info exists VPI_PORT] } {\n   set _VPI_PORT $VPI_PORT\n} else {\n   set _VPI_PORT 5555\n}\n\n# Set the VPI JTAG server address\nif { [info exists VPI_ADDRESS] } {\n   set _VPI_ADDRESS $VPI_ADDRESS\n} else {\n   set _VPI_ADDRESS \"127.0.0.1\"\n}\n\njtag_vpi set_port $_VPI_PORT\njtag_vpi set_address $_VPI_ADDRESS\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/kitprog.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Cypress Semiconductor KitProg\n#\n# Note: This is the driver for the proprietary KitPtog protocol. If the\n# KitProg is in CMSIS-DAP mode, you should either use the cmsis-dap\n# interface driver or switch the KitProg to KitProg mode.\n#\n\nadapter driver kitprog\n\n# Optionally specify the serial number of the KitProg you want to use.\n# adapter serial 1926402735485200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/nulink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Nuvoton Nu-Link in-circuit debugger/programmer\n#\n\nadapter driver hla\nhla_layout nulink\nhla_device_desc \"Nu-Link\"\nhla_vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201\n\n# Only swd is supported\ntransport select hla_swd\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/opendous.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# opendous-jtag\n#\n# http://code.google.com/p/opendous-jtag/\n#\n\nadapter driver opendous\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/openjtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# OpenJTAG\n#\n# www.openjtag.org\n#\n\nadapter driver openjtag\nopenjtag device_desc \"Open JTAG Project\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/osbdm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# P&E Micro OSBDM (aka OSJTAG) interface\n#\n# http://pemicro.com/osbdm/\n#\nadapter driver osbdm\nreset_config srst_only\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/parport.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Parallel port wiggler (many clones available) on port 0x378\n#\n# Addresses: 0x378/LPT1 or 0x278/LPT2 ...\n#\n\nif { [info exists PARPORTADDR] } {\n   set _PARPORTADDR $PARPORTADDR\n} else {\n   if {$tcl_platform(platform) eq \"windows\"} {\n      set _PARPORTADDR 0x378\n   } {\n      set _PARPORTADDR 0\n   }\n}\n\nadapter driver parport\nparport port $_PARPORTADDR\nparport cable wiggler\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/parport_dlc5.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Xilinx Parallel Cable III 'DLC 5' (and various clones)\n#\n# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html\n#\n\nif { [info exists PARPORTADDR] } {\n   set _PARPORTADDR $PARPORTADDR\n} else {\n   set _PARPORTADDR 0\n}\n\nadapter driver parport\nparport port $_PARPORTADDR\nparport cable dlc5\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/raspberrypi-gpio-connector.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Config for Raspberry Pi GPIO header\n#\n# This is best used with a fast enough buffer but also\n# is suitable for direct connection if the target voltage\n# matches RPi's 3.3V and the cable is short enough.\n#\n# Do not forget the GND connection, e.g. pin 20 of the GPIO header.\n#\n\n# GPIO 25 (pin 22) previously used for TMS/SWDIO is pulled-down by default.\n# The JTAG/SWD specification requires pull-up at the target board\n# for either signal. Connecting the signal pulled-up on the target\n# to the pull-down on the adapter is not a good idea.\n# GPIO 8 is pulled-up by default.\necho \"Warn : TMS/SWDIO moved to GPIO 8 (pin 24). Check the wiring please!\"\n\n# Each of the JTAG lines need a gpio number set: tck tms tdi tdo\n# Header pin numbers: 23 24 19 21\nadapter gpio tck -chip 0 11\nadapter gpio tms -chip 0 8\nadapter gpio tdi -chip 0 10\nadapter gpio tdo -chip 0 9\n\n# Each of the SWD lines need a gpio number set: swclk swdio\n# Header pin numbers: 23 24\nadapter gpio swclk -chip 0 11\nadapter gpio swdio -chip 0 8\n\n# If you define trst or srst, use appropriate reset_config\n# Header pin numbers: TRST - 26, SRST - 18\n\n# adapter gpio trst -chip 0 7\n# reset_config trst_only\n\n# adapter gpio srst -chip 0 24\n# reset_config srst_only srst_push_pull\n\n# or if you have both connected,\n# reset_config trst_and_srst srst_push_pull\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/raspberrypi-native.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config for Raspberry Pi used as a bitbang adapter.\n# https://www.raspberrypi.com/documentation/computers/raspberry-pi.html\n\n# Supports all models with 40-pin or 26-pin GPIO connector up to Raspberry Pi 4 B\n# also supports Raspberry Pi Zero, Zero W and Zero 2 W.\n\n# Adapter speed calibration is computed from cpufreq/scaling_max_freq.\n# Adjusts automatically if CPU is overclocked.\n\nadapter driver bcm2835gpio\n\nproc read_file { name } {\n\tif {[catch {open $name r} fd]} {\n\t\treturn \"\"\n\t}\n\tset result [read $fd]\n\tclose $fd\n\treturn $result\n}\n\nproc measure_clock {} {\n\tset result [exec vcgencmd measure_clock arm]\n\tset clock_hz [lindex [split $result \"=\"] 1]\n\texpr { $clock_hz / 1000 }\n}\n\nproc get_max_cpu_clock { default } {\n\tset clock [read_file /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq]\n\tif { $clock > 100000 } {\n\t\treturn $clock\n\t}\n\n\t# cpufreq not available. As the last resort try Broadcom's proprietary utility\n\tif {![catch measure_clock clock] && $clock > 100000} {\n\t\treturn $clock\n\t}\n\n\techo \"WARNING: Host CPU clock unknown.\"\n\techo \"WARNING: Using the highest possible value $default kHz as a safe default.\"\n\techo \"WARNING: Expect JTAG/SWD clock significantly slower than requested.\"\n\n\treturn $default\n}\n\nset compat [read_file /proc/device-tree/compatible]\nset clocks_per_timing_loop 4\n\nif {[string match *bcm2711* $compat]} {\n\tset speed_offset 52\n} elseif {[string match *bcm2837* $compat] || [string match *bcm2710* $compat]} {\n\tset speed_offset 34\n} elseif {[string match *bcm2836* $compat] || [string match *bcm2709* $compat]} {\n\tset speed_offset 36\n} elseif {[string match *bcm2835* $compat] || [string match *bcm2708* $compat]} {\n\tset clocks_per_timing_loop 6\n\tset speed_offset 32\n} else {\n\tset speed_offset 32\n\techo \"WARNING: Unknown type of the host SoC. Expect JTAG/SWD clock slower than requested.\"\n}\n\nset clock [get_max_cpu_clock 2000000]\nset speed_coeff [expr { $clock / $clocks_per_timing_loop }]\n\n# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET\n# The coefficients depend on system clock and CPU frequency scaling.\nbcm2835gpio speed_coeffs $speed_coeff $speed_offset\n\nsource [find interface/raspberrypi-gpio-connector.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/raspberrypi2-native.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho \"WARNING: interface/raspberrypi2-native.cfg is deprecated.\"\necho \"WARNING: Please use interface/raspberrypi-native.cfg for all Raspberry Pi models.\"\n\nsource [find interface/raspberrypi-native.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/rlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Raisonance RLink\n#\n# http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html\n#\n\nadapter driver rlink\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/rshim.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# BlueField SoC in-circuit debugger/programmer\n#\n\nadapter driver rshim\ntransport select dapdirect_swd\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/stlink-dap.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit\n# debugger/programmer\n#\n# This new interface driver creates a ST-Link wrapper for ARM-DAP named \"dapdirect\"\n# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support \"dapdirect\"\n#\n# SWIM transport is natively supported\n#\n\nadapter driver st-link\nst-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757\n\n# transport select dapdirect_jtag\n# transport select dapdirect_swd\n# transport select swim\n\n# Optionally specify the serial number of usb device\n# e.g.\n# adapter serial \"\\xaa\\xbc\\x6e\\x06\\x50\\x75\\xff\\x55\\x17\\x42\\x19\\x3f\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/stlink-v1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho \"WARNING: interface/stlink-v1.cfg is deprecated, please switch to interface/stlink.cfg\"\nsource [find interface/stlink.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/stlink-v2-1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho \"WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg\"\nsource [find interface/stlink.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/stlink-v2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho \"WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg\"\nsource [find interface/stlink.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/stlink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit\n# debugger/programmer\n#\n\nadapter driver hla\nhla_layout stlink\nhla_device_desc \"ST-LINK\"\nhla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757\n\n# Optionally specify the serial number of ST-LINK/V2 usb device.  ST-LINK/V2\n# devices seem to have serial numbers with unreadable characters.  ST-LINK/V2\n# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial\n# number reset issues.\n# eg.\n# adapter serial \"\\xaa\\xbc\\x6e\\x06\\x50\\x75\\xff\\x55\\x17\\x42\\x19\\x3f\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/sysfsgpio-raspberrypi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Config for using RaspberryPi's expansion header\n#\n# This is best used with a fast enough buffer but also\n# is suitable for direct connection if the target voltage\n# matches RPi's 3.3V\n#\n# Do not forget the GND connection, pin 6 of the expansion header.\n#\n\nadapter driver sysfsgpio\n\n# Each of the JTAG lines need a gpio number set: tck tms tdi tdo\n# Header pin numbers: 23 22 19 21\nsysfsgpio jtag_nums 11 25 10 9\n\n# Each of the SWD lines need a gpio number set: swclk swdio\n# Header pin numbers: 23 22\nsysfsgpio swd_nums 11 25\n\n# If you define trst or srst, use appropriate reset_config\n# Header pin numbers: TRST - 26, SRST - 18\n\n# sysfsgpio trst_num 7\n# reset_config trst_only\n\n# sysfsgpio srst_num 24\n# reset_config srst_only srst_push_pull\n\n# or if you have both connected,\n# reset_config trst_and_srst srst_push_pull\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ti-icdi.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI Stellaris In-Circuit Debug Interface (ICDI) Board\n#\n# This is the propriety ICDI interface used on newer boards such as\n# LM4F232 Evaluation Kit - http://www.ti.com/tool/ek-lm4f232\n# Stellaris Launchpad - http://www.ti.com/stellaris-launchpad\n# http://www.ti.com/tool/ek-lm4f232\n#\n\nadapter driver hla\nhla_layout ti-icdi\nhla_vid_pid 0x1cbe 0x00fd\n\n# Optionally specify the serial number of TI-ICDI devices, for when using\n# multiple devices. Serial numbers can be obtained using lsusb -v\n# Ex.\n# adapter serial \"0F003065\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/ulink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Keil ULINK running OpenULINK firmware.\n#\n# http://www.keil.com/ulink1/\n# http://article.gmane.org/gmane.comp.debugging.openocd.devel/17362\n#\n\nadapter driver ulink\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/usb-jtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# ixo-usb-jtag - Emulation of a Altera Bus Blaster I on a Cypress FX2 IC.\n#\n# The ixo-usb-jtag firmware can be loaded onto a bunch of different hardware\n# including;\n#  * Xilinx USB Platform Cable\n#  * Many Digilent boards such as the Nexys, Nexys 2 and Atlys boards\n#  * Many fpga4fun.com boards from such as the Saxo and Xylo boards\n#  * The Numato Opsis\n#\n# Original version - http://www.ixo.de/info/usb_jtag/\n#  Updated version - http://ixo-jtag.sourceforge.net/\n#   Newest version - http://github.com/mithro/ixo-usb-jtag\n#\n# Procedure for using is;\n#  * Get the ixo-usb-jtag firmware for your hardware (or build it yourself).\n#  * Load the firmware using the fxload tool.\n#  * Use openocd.\n#\n# Unless you burn the firmware into the EEPROM on your device, power cycling\n# will require you to reload the firmware using the fxload tool. This can be\n# automated by using udev rules (which can be found in the firmware\n# repository).\n#\n# Ubuntu packages built from mithro's version (with prebuilt firmware and udev\n# rules) can be found at\n# https://launchpad.net/~timvideos/+archive/ubuntu/fpga-support\n#\n# TODO: Refactor the usb_blaster driver to allow loading firmware using any low\n# level driver. Loading firmware is currently only supported on the ublast2\n# driver but ixo-usb-jtag requires the ftdi driver.\n\nadapter driver usb_blaster\nusb_blaster vid_pid 0x16C0 0x06AD\nusb_blaster device_desc \"Van Ooijen Technische Informatica\"\n# ixo-usb-jtag is only compatible with the ublast1 protocol implemented via the\n# ftdi modes, using ublast2 will cause openocd to hang.\nusb_blaster lowlevel_driver ftdi\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/usbprog.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Embedded Projects USBprog\n#\n# http://embedded-projects.net/index.php?page_id=135\n#\n\nadapter driver usbprog\n# USBprog is broken w/short TMS sequences, this is a workaround\n# until the C code can be fixed.\ntms_sequence long\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/vdebug.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n\nif { [info exists VDEBUGHOST] } {\n\tset _VDEBUGHOST $VDEBUGHOST\n} else {\n\tset _VDEBUGHOST localhost\n}\nif { [info exists VDEBUGPORT] } {\n\tset _VDEBUGPORT $VDEBUGPORT\n} else {\n\tset _VDEBUGPORT 8192\n}\n\nadapter driver vdebug\n# vdebug server:port\nvdebug server $_VDEBUGHOST:$_VDEBUGPORT\n\n# example config debug level and log\n#debug_level 3\n#log_output vd_ocd.log\n\n# example config listen on all interfaces, disable tcl/telnet server\nbindto 0.0.0.0\n#gdb_port 3333\n#telnet_port disabled\ntcl_port disabled\n\n# transaction batching: 0 - no batching, 1 - (default) wr, 2 - rw\nvdebug batching 1\n\n# Polling values\nvdebug polling 100 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/vsllink.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Versaloon Link -- VSLLink\n#\n# http://www.versaloon.com/\n#\n\nadapter driver vsllink\n"
  },
  {
    "path": "openocd-win/openocd/scripts/interface/xds110.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments XDS110\n#\n# http://processors.wiki.ti.com/index.php/XDS110\n# http://processors.wiki.ti.com/index.php/Emulation_Software_Package#XDS110_Support_Utilities\n#\n\nadapter driver xds110\n\n# Use serial number option to use a specific XDS110\n# when more than one are connected to the host.\n# adapter serial 00000000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/mem_helper.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Helper for common memory read/modify/write procedures\n\n# mrw: \"memory read word\", returns value of $reg\nproc mrw {reg} {\n\treturn [read_memory $reg 32 1]\n}\n\nadd_usage_text mrw \"address\"\nadd_help_text mrw \"Returns value of word in memory.\"\n\n# mrh: \"memory read halfword\", returns value of $reg\nproc mrh {reg} {\n\treturn [read_memory $reg 16 1]\n}\n\nadd_usage_text mrh \"address\"\nadd_help_text mrh \"Returns value of halfword in memory.\"\n\n# mrb: \"memory read byte\", returns value of $reg\nproc mrb {reg} {\n\treturn [read_memory $reg 8 1]\n}\n\nadd_usage_text mrb \"address\"\nadd_help_text mrb \"Returns value of byte in memory.\"\n\n# mmw: \"memory modify word\", updates value of $reg\n#       $reg <== ((value & ~$clearbits) | $setbits)\nproc mmw {reg setbits clearbits} {\n\tset old [mrw $reg]\n\tset new [expr {($old & ~$clearbits) | $setbits}]\n\tmww $reg $new\n}\n\nadd_usage_text mmw \"address setbits clearbits\"\nadd_help_text mmw \"Modify word in memory. new_val = (old_val & ~clearbits) | setbits;\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/memory.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# MEMORY\n#\n# All Memory regions have two components.\n#    (1) A count of regions, in the form N_NAME\n#    (2) An array within info about each region.\n#\n# The ARRAY\n#\n#       <NAME>(  RegionNumber ,  ATTRIBUTE )\n#\n# Where <NAME> is one of:\n#\n#     N_FLASH  & FLASH   (internal memory)\n#     N_RAM    & RAM     (internal memory)\n#     N_MMREGS & MMREGS  (for memory mapped registers)\n#     N_XMEM   & XMEM    (off chip memory, ie: flash on cs0, sdram on cs2)\n# or  N_UNKNOWN & UNKNOWN for things that do not exist.\n#\n# We have 1 unknown region.\nset N_UNKNOWN 1\n# All MEMORY regions must have these attributes\n#     CS          - chip select (if internal, use -1)\nset UNKNOWN(0,CHIPSELECT) -1\n#     BASE        - base address in memory\nset UNKNOWN(0,BASE)       0\n#     LEN         - length in bytes\nset UNKNOWN(0,LEN)        $CPU_MAX_ADDRESS\n#     HUMAN       - human name of the region\nset UNKNOWN(0,HUMAN) \"unknown\"\n#     TYPE        - one of:\n#                       flash, ram, mmr, unknown\n#                    For harvard arch:\n#                       iflash, dflash, iram, dram\nset UNKNOWN(0,TYPE)       \"unknown\"\n#     RWX         - access ablity\n#                       unix style chmod bits\n#                           0 - no access\n#                           1 - execute\n#                           2 - write\n#                           4 - read\n#                       hence: 7 - readwrite execute\nset RWX_NO_ACCESS     0\nset RWX_X_ONLY        $BIT0\nset RWX_W_ONLY        $BIT1\nset RWX_R_ONLY        $BIT2\nset RWX_RW            [expr {$RWX_R_ONLY + $RWX_W_ONLY}]\nset RWX_R_X           [expr {$RWX_R_ONLY + $RWX_X_ONLY}]\nset RWX_RWX           [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}]\nset UNKNOWN(0,RWX)     $RWX_NO_ACCESS\n\n#     WIDTH       - access width\n#                      8,16,32 [0 means ANY]\nset ACCESS_WIDTH_NONE 0\nset ACCESS_WIDTH_8    $BIT0\nset ACCESS_WIDTH_16   $BIT1\nset ACCESS_WIDTH_32   $BIT2\nset ACCESS_WIDTH_ANY  [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}]\nset UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE\n\nproc iswithin { ADDRESS BASE LEN } {\n    return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]\n}\n\nproc address_info { ADDRESS } {\n\n    foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {\n\tif { info exists $WHERE } {\n\t    set lmt [set N_[set WHERE]]\n\t    for { set region 0 } { $region < $lmt } { incr region } {\n\t\tif { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } {\n\t\t    return  \"$WHERE $region\";\n\t\t}\n\t    }\n\t}\n    }\n\n    # Return the 'unknown'\n    return \"UNKNOWN 0\"\n}\n\nproc memread32 {ADDR} {\n    if ![ catch { set foo [read_memory $ADDR 32 1] } msg ] {\n\treturn $foo\n    } else {\n\terror \"memread32: $msg\"\n    }\n}\n\nproc memread16 {ADDR} {\n    if ![ catch { set foo [read_memory $ADDR 16 1] } msg ] {\n\treturn $foo\n    } else {\n\terror \"memread16: $msg\"\n    }\n}\n\nproc memread8 {ADDR} {\n    if ![ catch { set foo [read_memory $ADDR 8 1] } msg ] {\n\treturn $foo\n    } else {\n\terror \"memread8: $msg\"\n    }\n}\n\nproc memwrite32 {ADDR DATA} {\n    if ![ catch { write_memory $ADDR 32 $DATA } msg ] {\n\treturn $DATA\n    } else {\n\terror \"memwrite32: $msg\"\n    }\n}\n\nproc memwrite16 {ADDR DATA} {\n    if ![ catch { write_memory $ADDR 16 $DATA } msg ] {\n\treturn $DATA\n    } else {\n\terror \"memwrite16: $msg\"\n    }\n}\n\nproc memwrite8 {ADDR DATA} {\n    if ![ catch { write_memory $ADDR 8 $DATA } msg ] {\n\treturn $DATA\n    } else {\n\terror \"memwrite8: $msg\"\n    }\n}\n\nproc memread32_phys {ADDR} {\n    if ![ catch { set foo [read_memory $ADDR 32 1 phys] } msg ] {\n\treturn $foo\n    } else {\n\terror \"memread32: $msg\"\n    }\n}\n\nproc memread16_phys {ADDR} {\n    if ![ catch { set foo [read_memory $ADDR 16 1 phys] } msg ] {\n\treturn $foo\n    } else {\n\terror \"memread16: $msg\"\n    }\n}\n\nproc memread8_phys {ADDR} {\n    if ![ catch { set foo [read_memory $ADDR 8 1 phys] } msg ] {\n\treturn $foo\n    } else {\n\terror \"memread8: $msg\"\n    }\n}\n\nproc memwrite32_phys {ADDR DATA} {\n    if ![ catch { write_memory $ADDR 32 $DATA phys } msg ] {\n\treturn $DATA\n    } else {\n\terror \"memwrite32: $msg\"\n    }\n}\n\nproc memwrite16_phys {ADDR DATA} {\n    if ![ catch { write_memory $ADDR 16 $DATA phys } msg ] {\n\treturn $DATA\n    } else {\n\terror \"memwrite16: $msg\"\n    }\n}\n\nproc memwrite8_phys {ADDR DATA} {\n    if ![ catch { write_memory $ADDR 8 $DATA phys } msg ] {\n\treturn $DATA\n    } else {\n\terror \"memwrite8: $msg\"\n    }\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/mmr_helpers.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nproc proc_exists { NAME } {\n    set n [info commands $NAME]\n    set l [string length $n]\n    return [expr {$l != 0}]\n}\n\n# Give: REGISTER name - must be a global variable.\nproc show_mmr32_reg { NAME } {\n\n    global $NAME\n    # we want $($NAME)\n    set a [set [set NAME]]\n\n    if ![catch { set v [memread32 $a] } msg ] {\n\techo [format \"%15s: (0x%08x): 0x%08x\" $NAME $a $v]\n\n\t# Was a helper defined?\n\tset fn show_${NAME}_helper\n\tif [ proc_exists $fn ] {\n\t    # Then call it\n\t    $fn $NAME $a $v\n\t}\n\treturn $v;\n    } else {\n\terror [format \"%s (%s)\" $msg $NAME ]\n    }\n}\n\n\n# Give: NAMES - an array of names accessible\n#               in the callers symbol-scope.\n#       VAL - the bits to display.\n\nproc show_mmr32_bits { NAMES VAL } {\n\n    upvar $NAMES MYNAMES\n\n    set w 5\n    foreach {IDX N} $MYNAMES {\n\tset l [string length $N]\n\tif { $l > $w } { set w $l }\n    }\n\n    for { set x 24 } { $x >= 0 } { incr x -8 } {\n\techo -n \"  \"\n\tfor { set y 7 } { $y >= 0 } { incr y -1 } {\n\t    set s $MYNAMES([expr {$x + $y}])\n\t    echo -n [format \"%2d: %-*s | \" [expr {$x + $y}] $w $s ]\n\t}\n\techo \"\"\n\n\techo -n \"  \"\n\tfor { set y 7 } { $y >= 0 } { incr y -1 } {\n\t    echo -n [format \"    %d%*s | \" [expr {!!($VAL & (1 << ($x + $y)))}] [expr {$w -1}] \"\"]\n\t}\n\techo \"\"\n    }\n}\n\n\nproc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } {\n    set width [expr {(($MSB - $LSB + 1) + 7) / 4}]\n    set nval [show_normalize_bitfield $VAL $MSB $LSB ]\n    set name0 [lindex $FIELDVALUES 0 ]\n    if [ string compare $name0 _NUMBER_ ] {\n\tset sval [lindex $FIELDVALUES $nval]\n    } else {\n\tset sval \"\"\n    }\n    echo [format \"%-15s: %d (0x%0*x) %s\" $FIELDNAME $nval $width $nval $sval ]\n}\n\n# Give: ADDR - address of the register.\n#       BIT - bit's number.\n\nproc get_mmr_bit { ADDR BIT } {\n\tset val [memread32 $ADDR]\n\tset bit_val [expr {$val & [expr {1 << $BIT}]}]\n\treturn $bit_val\n}\n\n\n# Give: ADDR - address of the register.\n#       MSB - MSB bit's number.\n#       LSB - LSB bit's number.\n\nproc get_mmr_bitfield { ADDR MSB LSB } {\n\tset rval [memread32 $ADDR]\n\treturn normalize_bitfield $rval $MSB $LSB\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/1986ве1т.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# 1986ВЕ1Т\n# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=236&cntnt01returnid=68\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME 1986ве1т\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Work-area is a space in RAM used for flash programming\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      set _CPUTAPID 0x4ba00477\n   } {\n      # SWD IDCODE\n      set _CPUTAPID 0x2ba01477\n   }\n}\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n# use AHB-Lite SRAM for work area\n$_TARGETNAME configure -work-area-phys 0x20100000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# can't handle overlapping memory regions\nif { [info exists IMEMORY] && [string equal $IMEMORY true] } {\n   flash bank ${_CHIPNAME}_info.flash mdr 0x00000000 0x01000 0 0 $_TARGETNAME 1 1 4\n} else {\n   flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 0 0 $_TARGETNAME 0 32 4\n}\n\n# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz\nadapter speed 1000\n\nadapter srst delay 100\nif {[using_jtag]} {\n   jtag_ntrst_delay 100\n}\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/adsp-sc58x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Analog Devices ADSP-SC58x (ARM Cortex-A5 plus one or two SHARC+ DSPs)\n#\n\n# Evaluation boards by Analog Devices (and designs derived from them) use a\n# non-standard 10-pin 0.05\" ARM Cortex Debug Connector.  In this bastardized\n# implementation, pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST.\n#\n# As a result, a standards-compliant debug pod will force /TRST active,\n# putting the processor's debug interface into reset and preventing usage.\n#\n# A connector adapter must be employed on these boards to isolate or remap\n# /TRST so that it is only asserted when intended.\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME ADSP-SC58x\n}\n\nif { [info exists ENDIAN] } {\n\tset _ENDIAN $ENDIAN\n} else {\n\tset _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x3BA02477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\ntarget create ap0.mem mem_ap -dap $_CHIPNAME.dap -ap-num 0\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -event examine-end {\n   global _TARGETNAME\n   sc58x_enabledebug\n}\n\nproc sc58x_enabledebug {} {\n   # Enable debugging functionality by setting bits in the TAPC_DBGCTL register\n   # it is not possible to halt the target unless these bits have been set\n   ap0.mem mww 0x31131000 0xFFFF\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/aduc702x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME aduc702x\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   # This config file was defaulting to big endian..\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x3f0f0f0f\n}\n\nadapter srst delay 200\njtag_ntrst_delay 200\n\n## JTAG scan chain\n#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n##\n## Target configuration\n##\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# allocate the entire SRAM as working area\n$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000\n\n## flash configuration\n# only target number is needed\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME\n\n## If you use the watchdog, the following code makes sure that the board\n## doesn't reboot when halted via JTAG.  Yes, on the older generation\n## AdUC702x, timer3 continues running even when the CPU is halted.\n\nproc watchdog_service {} {\n    global watchdog_hdl\n    mww 0xffff036c 0\n#    echo \"watchdog!!\"\n    set watchdog_hdl [after 500 watchdog_service]\n}\n\n$_TARGETNAME configure -event reset-halt-post {  watchdog_service }\n$_TARGETNAME configure -event resume-start { global watchdog_hdl; after cancel $watchdog_hdl }\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/aducm360.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# This file was created using as references the stm32f1x.cfg and aduc702x.cfg\n#\nsource [find target/swj-dp.tcl]\n\n# Chip name\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME aducm360\n}\n\n# Endianness\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Work-area is a space in RAM used for flash programming\n# Eventually, the whole SRAM of ADuCM360 will be used (8kB)\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x2000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x2ba01477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# SWD/JTAG speed\nadapter speed 1000\n\n##\n## Target configuration\n##\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n# allocate the working area\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME\n\nadapter srst delay 100\n\ncortex_m reset_config sysresetreq\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/allwinner_v3s.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is the config for an Allwinner V3/V3s (sun8iw8).\n#\n# Notes:\n# - Single core ARM Cortex-A7 with a maximum frequency of 1.2 GHz.\n# - Thumb-2 Technology\n# - Support NEON Advanced SIMD(Single Instruction Multiple Data)instruction\n#   for acceleration of media and signal processing functions\n# - Support Large Physical Address Extensions(LPAE)\n# - VFPv4 Floating Point Unit\n# - 32KB L1 Instruction cache and 32KB L1 Data cache\n# - 128KB L2 cache\n# - has some integrated DDR2 RAM.\n#\n# Pins related for debug and bootstrap:\n#   JTAG\n# JTAG_TMS\tPF0, SDC0_D1\n# JTAG_TDI\tPF1, SDC0_D0\n# JTAG_TDO\tPF3, SDC0_CMD\n# JTAG_TCK\tPF5, SDC0_D2\n#   UART\n# None of UART ports seems to be enabled by ROM.\n# UART0_TX\tPF2, SDC0_CLK\t\tPer default disabled\n# UART0_RX\tPF4, SDC0_D3 \t\tPer default disabled\n# UART1_TX\tPE21\t\t\tPer default disabled\n# UART1_RX\tPE22\t \t\tPer default disabled\n# UART2_TX\tPB0\t\t\tPer default disabled\n# UART2_RX\tPB1\t \t\tPer default disabled\n#\n# JTAG is enabled by default after power on on listed JTAG_* pins. So far the\n# boot sequence is:\n# Time\t\tAction\n# 0000ms\tPower ON\n# 0200ms\tJTAG enabled\n# 0220ms\tJTAG pins switched to SD mode\n#\n# The time frame of 20ms can be not enough to init and halt the CPU. In this\n# case I would recommend to set: \"adapter speed 15000\"\n# To get more or less precise timings, the board should provide reset pin,\n# or some bench power supply with remote function. In my case I used\n# EEZ H24005 with this command to power on and halt the target:\n# \"exec  echo \"*TRG\" > /dev/ttyACM0; sleep 220; reset halt\"\n# After this it is possible to enable JTAG mode again from boot loader or OS.\n# Following DAPs are available:\n# dap[0]->MEM-AP AHB\n# dap[1]->MEM-AP APB->CA7[0]\n#\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME v3s\n}\n\nif { [info exists DAP_TAPID] } {\n        set _DAP_TAPID $DAP_TAPID\n} else {\n        set _DAP_TAPID 0x5ba00477\n}\n\n# No NRST or SRST is present on the SoC. Boards may provide\n# some sort of Power cycle reset for complete board or SoC.\n# For this case we provide srst_pulls_trst so the board config\n# only needs to set srst_only.\nreset_config none srst_pulls_trst\n\njtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\n\n# Add Cortex A7 core\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/alphascale_asm9260t.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME asm9260t\n}\n\nif { [info exists ENDIAN] } {\n\tset _ENDIAN $ENDIAN\n} else {\n\tset _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x079264F3\n}\n\n# And srst_pulls_trst by chip design.\nreset_config srst_pulls_trst\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/altera_fpgasoc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Altera cyclone V SoC family, 5Cxxx\n#\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME fpgasoc\n}\n\n# CoreSight Debug Access Port\nif { [info exists DAP_TAPID] } {\n        set _DAP_TAPID $DAP_TAPID\n} else {\n        set _DAP_TAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\n\n# Subsidiary TAP: fpga\nif { [info exists FPGA_TAPID] } {\n   set _FPGA_TAPID $FPGA_TAPID\n} else {\n   set _FPGA_TAPID 0x02d020dd\n}\njtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID\n\n\n#\n# Cortex-A9 target\n#\n\n# GDB target: Cortex-A9, using DAP, configuring only one core\n# Base addresses of cores:\n# core 0  -  0x80110000\n# core 1  -  0x80112000\n\n# Slow speed to be sure it will work\nadapter speed 1000\n\nset _TARGETNAME1 $_CHIPNAME.cpu.0\nset _TARGETNAME2 $_CHIPNAME.cpu.1\n\n# A9 core 0\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \\\n        -coreid 0 -dbgbase 0x80110000\n\n$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }\n$_TARGETNAME1 configure -event reset-assert-post \"cycv_dbginit $_TARGETNAME1\"\n\n\n# A9 core 1\n#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \\\n#        -coreid 1 -dbgbase 0x80112000\n\n#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }\n#$_TARGETNAME2 configure -event reset-assert-post \"cycv_dbginit $_TARGETNAME2\"\n\nproc cycv_dbginit {target} {\n        # General Cortex-A8/A9 debug initialisation\n        cortex_a dbginit\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/altera_fpgasoc_arria10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Intel (Altera) Arria10 FPGA SoC\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME arria10\n}\n\n# ARM CoreSight Debug Access Port (dap HPS)\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x4ba00477\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID\n\n# Subsidiary TAP: fpga (tap)\n# See Intel Arria 10 Handbook\n# https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf\n# Intel Arria 10 GX 160  0x02ee20dd\n# Intel Arria 10 GX 220  0x02e220dd\n# Intel Arria 10 GX 270  0x02ee30dd\n# Intel Arria 10 GX 320  0x02e230dd\n# Intel Arria 10 GX 480  0x02e240dd\n# Intel Arria 10 GX 570  0x02ee50dd\n# Intel Arria 10 GX 660  0x02e250dd\n# Intel Arria 10 GX 900  0x02ee60dd\n# Intel Arria 10 GX 1150 0x02e660dd\n# Intel Arria 10 GT 900  0x02e260dd\n# Intel Arria 10 GT 1150 0x02e060dd\n# Intel Arria 10 SX 160  0x02e620dd\n# Intel Arria 10 SX 220  0x02e020dd\n# Intel Arria 10 SX 270  0x02e630dd\n# Intel Arria 10 SX 320  0x02e030dd\n# Intel Arria 10 SX 480  0x02e040dd\n# Intel Arria 10 SX 570  0x02e650dd\n# Intel Arria 10 SX 660  0x02e050dd\njtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \\\n\t-expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \\\n\t-expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \\\n\t-expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \\\n\t-expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \\\n\t-expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \\\n\t-expected-id 0x02e050dd\n\nset _TARGETNAME $_CHIPNAME.cpu\n\n#\n# Cortex-A9 target\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0\ntarget create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \\\n\t-defer-examine\ntarget smp $_TARGETNAME.0 $_TARGETNAME.1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/am335x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/icepick.cfg]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME am335x\n}\n\n# set the taps to be enabled by default. this can be overridden\n# by setting DEFAULT_TAPS in a separate configuration file\n# or directly on the command line.\nif { [info exists DEFAULT_TAPS] } {\n\tset _DEFAULT_TAPS \"$DEFAULT_TAPS\"\n} else {\n\tset _DEFAULT_TAPS \"$_CHIPNAME.tap\"\n}\n\n#\n# Main DAP\n#\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x4b6b902f\n}\njtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable\njtag configure $_CHIPNAME.tap -event tap-enable \"icepick_d_tapenable $_CHIPNAME.jrc 12 0\"\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap\n\n#\n# M3 DAP\n#\nif { [info exists M3_DAP_TAPID] } {\n\tset _M3_DAP_TAPID $M3_DAP_TAPID\n} else {\n\tset _M3_DAP_TAPID 0x4b6b902f\n}\njtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable\njtag configure $_CHIPNAME.m3_tap -event tap-enable \"icepick_d_tapenable $_CHIPNAME.jrc 11 0\"\ndap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap\n\n#\n# ICEpick-D (JTAG route controller)\n#\nif { [info exists JRC_TAPID] } {\n\tset _JRC_TAPID $JRC_TAPID\n} else {\n\tset _JRC_TAPID 0x0b94402f\n}\njtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version\njtag configure $_CHIPNAME.jrc -event setup {\n\tglobal _DEFAULT_TAPS\n\tenable_default_taps $_DEFAULT_TAPS\n}\n# some TCK tycles are required to activate the DEBUG power domain\njtag configure $_CHIPNAME.jrc -event post-reset \"runtest 100\"\n\n#\n# helper function that enables all taps passed as argument\n#\nproc enable_default_taps { taps } {\n\tforeach tap $taps {\n\t\tjtag tapenable $tap\n\t}\n}\n\n#\n# Cortex-M3 target\n#\nset _TARGETNAME_2 $_CHIPNAME.m3\ntarget create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap\n\n#\n# Cortex-A8 target\n#\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000\n\n# SRAM: 64K at 0x4030.0000; use the first 16K\n$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000\n\n\n# when putting the target into 'reset halt', we need to disable the watchdog as\n# it would otherwise trigger while we're in JTAG\n# FIXME: unify with target/am437x.cfg\nsource [find mem_helper.tcl]\nset  WDT1_BASE_ADDR                  0x44e35000\nset  WDT1_W_PEND_WSPR                [expr       {$WDT1_BASE_ADDR     +  0x0034}]\nset  WDT1_WSPR                       [expr       {$WDT1_BASE_ADDR     +  0x0048}]\nproc disable_watchdog { } {\n\tglobal WDT1_WSPR\n\tglobal WDT1_W_PEND_WSPR\n\tglobal _TARGETNAME\n\n\tset curstate [$_TARGETNAME curstate]\n\n\tif { [string compare $curstate halted] == 0 } {\n\t\tset WDT_DISABLE_SEQ1\t0xaaaa\n\t\tset WDT_DISABLE_SEQ2\t0x5555\n\n\t\tmww phys $WDT1_WSPR $WDT_DISABLE_SEQ1\n\n\t\t# Empty body to make sure this executes as fast as possible.\n\t\t# We don't want any delays here otherwise romcode might start\n\t\t# executing and end up changing state of certain IPs.\n\t\twhile { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }\n\n\t\tmww phys $WDT1_WSPR $WDT_DISABLE_SEQ2\n\t\twhile { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }\n\t}\n}\n$_TARGETNAME configure -event reset-end { disable_watchdog }\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/am437x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/icepick.cfg]\nsource [find mem_helper.tcl]\n\n###############################################################################\n##\t\t\t\tAM437x Registers\t\t\t     ##\n###############################################################################\nset  PRCM_BASE_ADDR                  0x44df0000\nset  REVISION_PRM                    [expr       {$PRCM_BASE_ADDR     +  0x0000}]\nset  PRM_IRQSTATUS_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0004}]\nset  PRM_IRQENABLE_MPU               [expr       {$PRCM_BASE_ADDR     +  0x0008}]\nset  PRM_IRQSTATUS_M3                [expr       {$PRCM_BASE_ADDR     +  0x000c}]\nset  PRM_IRQENABLE_M3                [expr       {$PRCM_BASE_ADDR     +  0x0010}]\nset  PM_MPU_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0300}]\nset  PM_MPU_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0304}]\nset  RM_MPU_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0314}]\nset  RM_MPU_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0324}]\nset  PM_GFX_PWRSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x0400}]\nset  PM_GFX_PWRSTST                  [expr       {$PRCM_BASE_ADDR     +  0x0404}]\nset  RM_GFX_RSTCTRL                  [expr       {$PRCM_BASE_ADDR     +  0x0410}]\nset  RM_GFX_RSTST                    [expr       {$PRCM_BASE_ADDR     +  0x0414}]\nset  RM_GFX_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0424}]\nset  RM_RTC_CONTEXT                  [expr       {$PRCM_BASE_ADDR     +  0x0524}]\nset  RM_WKUP_RSTCTRL                 [expr       {$PRCM_BASE_ADDR     +  0x2010}]\nset  RM_WKUP_RSTST                   [expr       {$PRCM_BASE_ADDR     +  0x2014}]\nset  CM_L3_AON_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x2800}]\nset  CM_WKUP_DEBUGSS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2820}]\nset  CM_L3S_TSC_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2900}]\nset  CM_WKUP_ADC_TSC_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2920}]\nset  CM_L4_WKUP_AON_CLKSTCTRL        [expr       {$PRCM_BASE_ADDR     +  0x2a00}]\nset  CM_WKUP_L4WKUP_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2a20}]\nset  CM_WKUP_WKUP_M3_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a28}]\nset  CM_WKUP_SYNCTIMER_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a30}]\nset  CM_WKUP_CLKDIV32K_CLKCTRL       [expr       {$PRCM_BASE_ADDR     +  0x2a38}]\nset  CM_WKUP_USBPHY0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a40}]\nset  CM_WKUP_USBPHY1_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2a48}]\nset  CM_WKUP_CLKSTCTRL               [expr       {$PRCM_BASE_ADDR     +  0x2b00}]\nset  CM_WKUP_TIMER0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b20}]\nset  CM_WKUP_TIMER1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x2b28}]\nset  CM_WKUP_WDT0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b30}]\nset  CM_WKUP_WDT1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b38}]\nset  CM_WKUP_I2C0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x2b40}]\nset  CM_WKUP_UART0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b48}]\nset  CM_WKUP_SMARTREFLEX0_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b50}]\nset  CM_WKUP_SMARTREFLEX1_CLKCTRL    [expr       {$PRCM_BASE_ADDR     +  0x2b58}]\nset  CM_WKUP_CONTROL_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x2b60}]\nset  CM_WKUP_GPIO0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x2b68}]\nset  CM_CLKMODE_DPLL_CORE            [expr       {$PRCM_BASE_ADDR     +  0x2d20}]\nset  CM_IDLEST_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d24}]\nset  CM_CLKSEL_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d2c}]\nset  CM_DIV_M4_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d38}]\nset  CM_DIV_M5_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d3c}]\nset  CM_DIV_M6_DPLL_CORE             [expr       {$PRCM_BASE_ADDR     +  0x2d40}]\nset  CM_SSC_DELTAMSTEP_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d48}]\nset  CM_SSC_MODFREQDIV_DPLL_CORE     [expr       {$PRCM_BASE_ADDR     +  0x2d4c}]\nset  CM_CLKMODE_DPLL_MPU             [expr       {$PRCM_BASE_ADDR     +  0x2d60}]\nset  CM_IDLEST_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d64}]\nset  CM_CLKSEL_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d6c}]\nset  CM_DIV_M2_DPLL_MPU              [expr       {$PRCM_BASE_ADDR     +  0x2d70}]\nset  CM_SSC_DELTAMSTEP_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d88}]\nset  CM_SSC_MODFREQDIV_DPLL_MPU      [expr       {$PRCM_BASE_ADDR     +  0x2d8c}]\nset  CM_CLKMODE_DPLL_DDR             [expr       {$PRCM_BASE_ADDR     +  0x2da0}]\nset  CM_IDLEST_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2da4}]\nset  CM_CLKSEL_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2dac}]\nset  CM_DIV_M2_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db0}]\nset  CM_DIV_M4_DPLL_DDR              [expr       {$PRCM_BASE_ADDR     +  0x2db8}]\nset  CM_SSC_DELTAMSTEP_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dc8}]\nset  CM_SSC_MODFREQDIV_DPLL_DDR      [expr       {$PRCM_BASE_ADDR     +  0x2dcc}]\nset  CM_CLKMODE_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2de0}]\nset  CM_IDLEST_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2de4}]\nset  CM_CLKSEL_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2dec}]\nset  CM_DIV_M2_DPLL_PER              [expr       {$PRCM_BASE_ADDR     +  0x2df0}]\nset  CM_CLKSEL2_DPLL_PER             [expr       {$PRCM_BASE_ADDR     +  0x2e04}]\nset  CM_SSC_DELTAMSTEP_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e08}]\nset  CM_SSC_MODFREQDIV_DPLL_PER      [expr       {$PRCM_BASE_ADDR     +  0x2e0c}]\nset  CM_CLKDCOLDO_DPLL_PER           [expr       {$PRCM_BASE_ADDR     +  0x2e14}]\nset  CM_CLKMODE_DPLL_DISP            [expr       {$PRCM_BASE_ADDR     +  0x2e20}]\nset  CM_IDLEST_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e24}]\nset  CM_CLKSEL_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e2c}]\nset  CM_DIV_M2_DPLL_DISP             [expr       {$PRCM_BASE_ADDR     +  0x2e30}]\nset  CM_SSC_DELTAMSTEP_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e48}]\nset  CM_SSC_MODFREQDIV_DPLL_DISP     [expr       {$PRCM_BASE_ADDR     +  0x2e4c}]\nset  CM_CLKMODE_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e60}]\nset  CM_IDLEST_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e64}]\nset  CM_CLKSEL_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e6c}]\nset  CM_DIV_M2_DPLL_EXTDEV           [expr       {$PRCM_BASE_ADDR     +  0x2e70}]\nset  CM_CLKSEL2_DPLL_EXTDEV          [expr       {$PRCM_BASE_ADDR     +  0x2e84}]\nset  CM_SSC_DELTAMSTEP_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e88}]\nset  CM_SSC_MODFREQDIV_DPLL_EXTDEV   [expr       {$PRCM_BASE_ADDR     +  0x2e8c}]\nset  CM_SHADOW_FREQ_CONFIG1          [expr       {$PRCM_BASE_ADDR     +  0x2fa0}]\nset  CM_SHADOW_FREQ_CONFIG2          [expr       {$PRCM_BASE_ADDR     +  0x2fa4}]\nset  CM_CLKOUT1_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4100}]\nset  CM_DLL_CTRL                     [expr       {$PRCM_BASE_ADDR     +  0x4104}]\nset  CM_CLKOUT2_CTRL                 [expr       {$PRCM_BASE_ADDR     +  0x4108}]\nset  CLKSEL_TIMER1MS_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4200}]\nset  CLKSEL_TIMER2_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4204}]\nset  CLKSEL_TIMER3_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4208}]\nset  CLKSEL_TIMER4_CLK               [expr       {$PRCM_BASE_ADDR     +  0x420c}]\nset  CLKSEL_TIMER5_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4210}]\nset  CLKSEL_TIMER6_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4214}]\nset  CLKSEL_TIMER7_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4218}]\nset  CLKSEL_TIMER8_CLK               [expr       {$PRCM_BASE_ADDR     +  0x421c}]\nset  CLKSEL_TIMER9_CLK               [expr       {$PRCM_BASE_ADDR     +  0x4220}]\nset  CLKSEL_TIMER10_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4224}]\nset  CLKSEL_TIMER11_CLK              [expr       {$PRCM_BASE_ADDR     +  0x4228}]\nset  CLKSEL_WDT1_CLK                 [expr       {$PRCM_BASE_ADDR     +  0x422c}]\nset  CLKSEL_SYNCTIMER_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4230}]\nset  CLKSEL_MAC_CLK                  [expr       {$PRCM_BASE_ADDR     +  0x4234}]\nset  CLKSEL_CPTS_RFT_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4238}]\nset  CLKSEL_GFX_FCLK                 [expr       {$PRCM_BASE_ADDR     +  0x423c}]\nset  CLKSEL_GPIO0_DBCLK              [expr       {$PRCM_BASE_ADDR     +  0x4240}]\nset  CLKSEL_LCDC_PIXEL_CLK           [expr       {$PRCM_BASE_ADDR     +  0x4244}]\nset  CLKSEL_ICSS_OCP_CLK             [expr       {$PRCM_BASE_ADDR     +  0x4248}]\nset  CLKSEL_DLL_AGING_CLK            [expr       {$PRCM_BASE_ADDR     +  0x4250}]\nset  CLKSEL_USBPHY32KHZ_GCLK         [expr       {$PRCM_BASE_ADDR     +  0x4260}]\nset  CM_MPU_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8300}]\nset  CM_MPU_MPU_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8320}]\nset  CM_GFX_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8400}]\nset  CM_GFX_GFX_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8420}]\nset  CM_RTC_CLKSTCTRL                [expr       {$PRCM_BASE_ADDR     +  0x8500}]\nset  CM_RTC_RTC_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8520}]\nset  CM_PER_L3_CLKSTCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8800}]\nset  CM_PER_L3_CLKCTRL               [expr       {$PRCM_BASE_ADDR     +  0x8820}]\nset  CM_PER_AES0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8828}]\nset  CM_PER_DES_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8830}]\nset  CM_PER_CRYPTODMA_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8838}]\nset  CM_PER_L3_INSTR_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8840}]\nset  CM_PER_MSTR_EXPS_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8848}]\nset  CM_PER_OCMCRAM_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8850}]\nset  CM_PER_SHA0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8858}]\nset  CM_PER_SLV_EXPS_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8860}]\nset  CM_PER_VPFE0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8868}]\nset  CM_PER_VPFE1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8870}]\nset  CM_PER_TPCC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8878}]\nset  CM_PER_TPTC0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8880}]\nset  CM_PER_TPTC1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8888}]\nset  CM_PER_TPTC2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8890}]\nset  CM_PER_DLL_AGING_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8898}]\nset  CM_PER_L4HS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a0}]\nset  CM_PER_L4FW_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x88a8}]\nset  CM_PER_L3S_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8a00}]\nset  CM_PER_GPMC_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a20}]\nset  CM_PER_IEEE5000_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8a28}]\nset  CM_PER_MCASP0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a38}]\nset  CM_PER_MCASP1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8a40}]\nset  CM_PER_MMC2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a48}]\nset  CM_PER_QSPI_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8a58}]\nset  CM_PER_USB_OTG_SS0_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a60}]\nset  CM_PER_USB_OTG_SS1_CLKCTRL      [expr       {$PRCM_BASE_ADDR     +  0x8a68}]\nset  CM_PER_ICSS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8b00}]\nset  CM_PER_ICSS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8b20}]\nset  CM_PER_L4LS_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8c00}]\nset  CM_PER_L4LS_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8c20}]\nset  CM_PER_DCAN0_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c28}]\nset  CM_PER_DCAN1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c30}]\nset  CM_PER_EPWMSS0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c38}]\nset  CM_PER_EPWMSS1_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c40}]\nset  CM_PER_EPWMSS2_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c48}]\nset  CM_PER_EPWMSS3_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c50}]\nset  CM_PER_EPWMSS4_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c58}]\nset  CM_PER_EPWMSS5_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8c60}]\nset  CM_PER_ELM_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8c68}]\nset  CM_PER_GPIO1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c78}]\nset  CM_PER_GPIO2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c80}]\nset  CM_PER_GPIO3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c88}]\nset  CM_PER_GPIO4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c90}]\nset  CM_PER_GPIO5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8c98}]\nset  CM_PER_HDQ1W_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8ca0}]\nset  CM_PER_I2C1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8ca8}]\nset  CM_PER_I2C2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cb0}]\nset  CM_PER_MAILBOX0_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8cb8}]\nset  CM_PER_MMC0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc0}]\nset  CM_PER_MMC1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8cc8}]\nset  CM_PER_PKA_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8cd0}]\nset  CM_PER_RNG_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8ce0}]\nset  CM_PER_SPARE0_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8ce8}]\nset  CM_PER_SPARE1_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8cf0}]\nset  CM_PER_SPI0_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d00}]\nset  CM_PER_SPI1_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d08}]\nset  CM_PER_SPI2_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d10}]\nset  CM_PER_SPI3_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d18}]\nset  CM_PER_SPI4_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8d20}]\nset  CM_PER_SPINLOCK_CLKCTRL         [expr       {$PRCM_BASE_ADDR     +  0x8d28}]\nset  CM_PER_TIMER2_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d30}]\nset  CM_PER_TIMER3_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d38}]\nset  CM_PER_TIMER4_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d40}]\nset  CM_PER_TIMER5_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d48}]\nset  CM_PER_TIMER6_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d50}]\nset  CM_PER_TIMER7_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d58}]\nset  CM_PER_TIMER8_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d60}]\nset  CM_PER_TIMER9_CLKCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8d68}]\nset  CM_PER_TIMER10_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d70}]\nset  CM_PER_TIMER11_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8d78}]\nset  CM_PER_UART1_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d80}]\nset  CM_PER_UART2_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d88}]\nset  CM_PER_UART3_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d90}]\nset  CM_PER_UART4_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8d98}]\nset  CM_PER_UART5_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x8da0}]\nset  CM_PER_USBPHYOCP2SCP0_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8db8}]\nset  CM_PER_USBPHYOCP2SCP1_CLKCTRL   [expr       {$PRCM_BASE_ADDR     +  0x8dc0}]\nset  CM_PER_EMIF_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x8f00}]\nset  CM_PER_EMIF_CLKCTRL             [expr       {$PRCM_BASE_ADDR     +  0x8f20}]\nset  CM_PER_DLL_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x8f28}]\nset  CM_PER_EMIF_FW_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x8f30}]\nset  CM_PER_OTFA_EMIF_CLKCTRL        [expr       {$PRCM_BASE_ADDR     +  0x8f38}]\nset  CM_PER_DSS_CLKSTCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9200}]\nset  CM_PER_DSS_CLKCTRL              [expr       {$PRCM_BASE_ADDR     +  0x9220}]\nset  CM_PER_CPSW_CLKSTCTRL           [expr       {$PRCM_BASE_ADDR     +  0x9300}]\nset  CM_PER_CPGMAC0_CLKCTRL          [expr       {$PRCM_BASE_ADDR     +  0x9320}]\nset  CM_PER_OCPWP_L3_CLKSTCTRL       [expr       {$PRCM_BASE_ADDR     +  0x9400}]\nset  CM_PER_OCPWP_CLKCTRL            [expr       {$PRCM_BASE_ADDR     +  0x9420}]\n\nset  CONTROL_BASE_ADDR               0x44e10000\nset  CONTROL_STATUS                  [expr       {$CONTROL_BASE_ADDR  +  0x0040}]\nset  DEVICE_ID                       [expr       {$CONTROL_BASE_ADDR  +  0x0600}]\nset  DEV_FEATURE                     [expr       {$CONTROL_BASE_ADDR  +  0x0604}]\nset  DEV_ATTRIBUTE                   [expr       {$CONTROL_BASE_ADDR  +  0x0610}]\nset  MAC_ID0_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0630}]\nset  MAC_ID0_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x0634}]\nset  MAC_ID1_LO                      [expr       {$CONTROL_BASE_ADDR  +  0x0638}]\nset  MAC_ID1_HI                      [expr       {$CONTROL_BASE_ADDR  +  0x063c}]\nset  USB_VID_PID                     [expr       {$CONTROL_BASE_ADDR  +  0x07f4}]\nset  CONTROL_CONF_ECAP0_IN_PWM0_OUT  [expr       {$CONTROL_BASE_ADDR  +  0x0964}]\nset  CONTROL_CONF_SPI4_CS0           [expr       {$CONTROL_BASE_ADDR  +  0x0a5c}]\nset  CONTROL_CONF_SPI2_SCLK          [expr       {$CONTROL_BASE_ADDR  +  0x0a60}]\nset  CONTROL_CONF_SPI2_D0            [expr       {$CONTROL_BASE_ADDR  +  0x0a64}]\nset  CONTROL_CONF_XDMA_EVENT_INTR0   [expr       {$CONTROL_BASE_ADDR  +  0x0a70}]\nset  CONTROL_CONF_XDMA_EVENT_INTR1   [expr       {$CONTROL_BASE_ADDR  +  0x0a74}]\nset  CONTROL_CONF_GPMC_A0            [expr       {$CONTROL_BASE_ADDR  +  0x0840}]\nset  DDR_IO_CTRL                     [expr       {$CONTROL_BASE_ADDR  +  0x0e04}]\nset  VTP_CTRL_REG                    [expr       {$CONTROL_BASE_ADDR  +  0x0e0c}]\nset  VREF_CTRL                       [expr       {$CONTROL_BASE_ADDR  +  0x0e14}]\nset  DDR_CKE_CTRL                    [expr       {$CONTROL_BASE_ADDR  +  0x131c}]\nset  DDR_ADDRCTRL_IOCTRL             [expr       {$CONTROL_BASE_ADDR  +  0x1404}]\nset  DDR_ADDRCTRL_WD0_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x1408}]\nset  DDR_ADDRCTRL_WD1_IOCTRL         [expr       {$CONTROL_BASE_ADDR  +  0x140c}]\nset  DDR_DATA0_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1440}]\nset  DDR_DATA1_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1444}]\nset  DDR_DATA2_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x1448}]\nset  DDR_DATA3_IOCTRL                [expr       {$CONTROL_BASE_ADDR  +  0x144c}]\nset  EMIF_SDRAM_CONFIG_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1460}]\nset  EMIF_SDRAM_STATUS_EXT           [expr       {$CONTROL_BASE_ADDR  +  0x1464}]\n\nset  GPIO0_BASE_ADDR                 0x44e07000\nset  GPIO0_SYSCONFIG                 [expr       {$GPIO0_BASE_ADDR    +  0x0010}]\nset  GPIO0_SYSSTATUS                 [expr       {$GPIO0_BASE_ADDR    +  0x0114}]\nset  GPIO0_CTRL                      [expr       {$GPIO0_BASE_ADDR    +  0x0130}]\nset  GPIO0_OE                        [expr       {$GPIO0_BASE_ADDR    +  0x0134}]\nset  GPIO0_CLEARDATAOUT              [expr       {$GPIO0_BASE_ADDR    +  0x0190}]\nset  GPIO0_SETDATAOUT                [expr       {$GPIO0_BASE_ADDR    +  0x0194}]\n\nset  GPIO5_BASE_ADDR                 0x48322000\nset  GPIO5_SYSCONFIG                 [expr       {$GPIO5_BASE_ADDR    +  0x0010}]\nset  GPIO5_SYSSTATUS                 [expr       {$GPIO5_BASE_ADDR    +  0x0114}]\nset  GPIO5_CTRL                      [expr       {$GPIO5_BASE_ADDR    +  0x0130}]\nset  GPIO5_OE                        [expr       {$GPIO5_BASE_ADDR    +  0x0134}]\nset  GPIO5_CLEARDATAOUT              [expr       {$GPIO5_BASE_ADDR    +  0x0190}]\nset  GPIO5_SETDATAOUT                [expr       {$GPIO5_BASE_ADDR    +  0x0194}]\n\nset  GPIO1_BASE_ADDR                 0x4804c000\nset  GPIO1_SYSCONFIG                 [expr       {$GPIO1_BASE_ADDR    +  0x0010}]\nset  GPIO1_SYSSTATUS                 [expr       {$GPIO1_BASE_ADDR    +  0x0114}]\nset  GPIO1_CTRL                      [expr       {$GPIO1_BASE_ADDR    +  0x0130}]\nset  GPIO1_OE                        [expr       {$GPIO1_BASE_ADDR    +  0x0134}]\nset  GPIO1_CLEARDATAOUT              [expr       {$GPIO1_BASE_ADDR    +  0x0190}]\nset  GPIO1_SETDATAOUT                [expr       {$GPIO1_BASE_ADDR    +  0x0194}]\n\nset  EMIF_BASE_ADDR                  0x4c000000\nset  EMIF_STATUS                     [expr       {$EMIF_BASE_ADDR     +  0x0004}]\nset  EMIF_SDRAM_CONFIG               [expr       {$EMIF_BASE_ADDR     +  0x0008}]\nset  EMIF_SDRAM_CONFIG_2             [expr       {$EMIF_BASE_ADDR     +  0x000c}]\nset  EMIF_SDRAM_REF_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0010}]\nset  EMIF_SDRAM_REF_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0014}]\nset  EMIF_SDRAM_TIM_1                [expr       {$EMIF_BASE_ADDR     +  0x0018}]\nset  EMIF_SDRAM_TIM_1_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x001c}]\nset  EMIF_SDRAM_TIM_2                [expr       {$EMIF_BASE_ADDR     +  0x0020}]\nset  EMIF_SDRAM_TIM_2_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x0024}]\nset  EMIF_SDRAM_TIM_3                [expr       {$EMIF_BASE_ADDR     +  0x0028}]\nset  EMIF_SDRAM_TIM_3_SHDW           [expr       {$EMIF_BASE_ADDR     +  0x002c}]\nset  EMIF_LPDDR2_NVM_TIM             [expr       {$EMIF_BASE_ADDR     +  0x0030}]\nset  EMIF_LPDDR2_NVM_TIM_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x0034}]\nset  EMIF_PWR_MGMT_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x0038}]\nset  EMIF_PWR_MGMT_CTRL_SHDW         [expr       {$EMIF_BASE_ADDR     +  0x003c}]\nset  EMIF_LPDDR2_MODE_REG_DATA       [expr       {$EMIF_BASE_ADDR     +  0x0040}]\nset  EMIF_LPDDR2_MODE_REG_CFG        [expr       {$EMIF_BASE_ADDR     +  0x0050}]\nset  EMIF_OCP_CONFIG                 [expr       {$EMIF_BASE_ADDR     +  0x0054}]\nset  EMIF_OCP_CFG_VAL_1              [expr       {$EMIF_BASE_ADDR     +  0x0058}]\nset  EMIF_OCP_CFG_VAL_2              [expr       {$EMIF_BASE_ADDR     +  0x005c}]\nset  EMIF_IODFT_TLGC                 [expr       {$EMIF_BASE_ADDR     +  0x0060}]\nset  EMIF_IODFT_CTRL_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0064}]\nset  EMIF_IODFT_ADDR_MISR_RSLT       [expr       {$EMIF_BASE_ADDR     +  0x0068}]\nset  EMIF_IODFT_DATA_MISR_RSLT_1     [expr       {$EMIF_BASE_ADDR     +  0x006c}]\nset  EMIF_IODFT_DATA_MISR_RSLT_2     [expr       {$EMIF_BASE_ADDR     +  0x0070}]\nset  EMIF_IODFT_DATA_MISR_RSLT_3     [expr       {$EMIF_BASE_ADDR     +  0x0074}]\nset  EMIF_PERF_CNT_1                 [expr       {$EMIF_BASE_ADDR     +  0x0080}]\nset  EMIF_PERF_CNT_2                 [expr       {$EMIF_BASE_ADDR     +  0x0084}]\nset  EMIF_PERF_CNT_CFG               [expr       {$EMIF_BASE_ADDR     +  0x0088}]\nset  EMIF_PERF_CNT_SEL               [expr       {$EMIF_BASE_ADDR     +  0x008c}]\nset  EMIF_PERF_CNT_TIM               [expr       {$EMIF_BASE_ADDR     +  0x0090}]\nset  EMIF_MISC_REG                   [expr       {$EMIF_BASE_ADDR     +  0x0094}]\nset  EMIF_DLL_CALIB_CTRL             [expr       {$EMIF_BASE_ADDR     +  0x0098}]\nset  EMIF_DLL_CALIB_CTRL_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x009c}]\nset  EMIF_IRQ_EOI                    [expr       {$EMIF_BASE_ADDR     +  0x00a0}]\nset  EMIF_IRQSTATUS_RAW_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00a4}]\nset  EMIF_IRQSTATUS_SYS              [expr       {$EMIF_BASE_ADDR     +  0x00ac}]\nset  EMIF_IRQENABLE_SET_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00b4}]\nset  EMIF_IRQENABLE_CLR_SYS          [expr       {$EMIF_BASE_ADDR     +  0x00bc}]\nset  EMIF_ZQ_CONFIG                  [expr       {$EMIF_BASE_ADDR     +  0x00c8}]\nset  EMIF_TEMP_ALERT_CONFIG          [expr       {$EMIF_BASE_ADDR     +  0x00cc}]\nset  EMIF_OCP_ERR_LOG                [expr       {$EMIF_BASE_ADDR     +  0x00d0}]\nset  EMIF_RDWR_LVL_RMP_WIN           [expr       {$EMIF_BASE_ADDR     +  0x00d4}]\nset  EMIF_RDWR_LVL_RMP_CTRL          [expr       {$EMIF_BASE_ADDR     +  0x00d8}]\nset  EMIF_RDWR_LVL_CTRL              [expr       {$EMIF_BASE_ADDR     +  0x00dc}]\nset  EMIF_DDR_PHY_CTRL_1             [expr       {$EMIF_BASE_ADDR     +  0x00e4}]\nset  EMIF_DDR_PHY_CTRL_1_SHDW        [expr       {$EMIF_BASE_ADDR     +  0x00e8}]\nset  EMIF_DDR_PHY_CTRL_2             [expr       {$EMIF_BASE_ADDR     +  0x00ec}]\nset  EMIF_PRI_COS_MAP                [expr       {$EMIF_BASE_ADDR     +  0x0100}]\nset  EMIF_CONNID_COS_1_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0104}]\nset  EMIF_CONNID_COS_2_MAP           [expr       {$EMIF_BASE_ADDR     +  0x0108}]\nset  ECC_CTRL                        [expr       {$EMIF_BASE_ADDR     +  0x0110}]\nset  ECC_ADDR_RNG_1                  [expr       {$EMIF_BASE_ADDR     +  0x0114}]\nset  ECC_ADDR_RNG_2                  [expr       {$EMIF_BASE_ADDR     +  0x0118}]\nset  EMIF_RD_WR_EXEC_THRSH           [expr       {$EMIF_BASE_ADDR     +  0x0120}]\nset  COS_CONFIG                      [expr       {$EMIF_BASE_ADDR     +  0x0124}]\n\nset  PHY_STATUS_1                    [expr       {$EMIF_BASE_ADDR     +  0x0144}]\nset  PHY_STATUS_2                    [expr       {$EMIF_BASE_ADDR     +  0x0148}]\nset  PHY_STATUS_3                    [expr       {$EMIF_BASE_ADDR     +  0x014c}]\nset  PHY_STATUS_4                    [expr       {$EMIF_BASE_ADDR     +  0x0150}]\nset  PHY_STATUS_5                    [expr       {$EMIF_BASE_ADDR     +  0x0154}]\nset  PHY_STATUS_6                    [expr       {$EMIF_BASE_ADDR     +  0x0158}]\nset  PHY_STATUS_7                    [expr       {$EMIF_BASE_ADDR     +  0x015c}]\nset  PHY_STATUS_8                    [expr       {$EMIF_BASE_ADDR     +  0x0160}]\nset  PHY_STATUS_9                    [expr       {$EMIF_BASE_ADDR     +  0x0164}]\nset  PHY_STATUS_10                   [expr       {$EMIF_BASE_ADDR     +  0x0168}]\nset  PHY_STATUS_11                   [expr       {$EMIF_BASE_ADDR     +  0x016c}]\nset  PHY_STATUS_12                   [expr       {$EMIF_BASE_ADDR     +  0x0170}]\nset  PHY_STATUS_13                   [expr       {$EMIF_BASE_ADDR     +  0x0174}]\nset  PHY_STATUS_14                   [expr       {$EMIF_BASE_ADDR     +  0x0178}]\nset  PHY_STATUS_15                   [expr       {$EMIF_BASE_ADDR     +  0x017c}]\nset  PHY_STATUS_16                   [expr       {$EMIF_BASE_ADDR     +  0x0180}]\nset  PHY_STATUS_17                   [expr       {$EMIF_BASE_ADDR     +  0x0184}]\nset  PHY_STATUS_18                   [expr       {$EMIF_BASE_ADDR     +  0x0188}]\nset  PHY_STATUS_19                   [expr       {$EMIF_BASE_ADDR     +  0x018c}]\nset  PHY_STATUS_20                   [expr       {$EMIF_BASE_ADDR     +  0x0190}]\nset  PHY_STATUS_21                   [expr       {$EMIF_BASE_ADDR     +  0x0194}]\nset  PHY_STATUS_22                   [expr       {$EMIF_BASE_ADDR     +  0x0198}]\nset  PHY_STATUS_23                   [expr       {$EMIF_BASE_ADDR     +  0x019c}]\nset  PHY_STATUS_24                   [expr       {$EMIF_BASE_ADDR     +  0x01a0}]\nset  PHY_STATUS_25                   [expr       {$EMIF_BASE_ADDR     +  0x01a4}]\nset  PHY_STATUS_26                   [expr       {$EMIF_BASE_ADDR     +  0x01a8}]\nset  PHY_STATUS_27                   [expr       {$EMIF_BASE_ADDR     +  0x01ac}]\nset  PHY_STATUS_28                   [expr       {$EMIF_BASE_ADDR     +  0x01b0}]\n\nset  EXT_PHY_CTRL_1                  [expr       {$EMIF_BASE_ADDR     +  0x0200}]\nset  EXT_PHY_CTRL_1_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0204}]\nset  EXT_PHY_CTRL_2                  [expr       {$EMIF_BASE_ADDR     +  0x0208}]\nset  EXT_PHY_CTRL_2_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x020c}]\nset  EXT_PHY_CTRL_3                  [expr       {$EMIF_BASE_ADDR     +  0x0210}]\nset  EXT_PHY_CTRL_3_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0214}]\nset  EXT_PHY_CTRL_4                  [expr       {$EMIF_BASE_ADDR     +  0x0218}]\nset  EXT_PHY_CTRL_4_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x021c}]\nset  EXT_PHY_CTRL_5                  [expr       {$EMIF_BASE_ADDR     +  0x0220}]\nset  EXT_PHY_CTRL_5_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0224}]\nset  EXT_PHY_CTRL_6                  [expr       {$EMIF_BASE_ADDR     +  0x0228}]\nset  EXT_PHY_CTRL_6_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x022c}]\nset  EXT_PHY_CTRL_7                  [expr       {$EMIF_BASE_ADDR     +  0x0230}]\nset  EXT_PHY_CTRL_7_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0234}]\nset  EXT_PHY_CTRL_8                  [expr       {$EMIF_BASE_ADDR     +  0x0238}]\nset  EXT_PHY_CTRL_8_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x023c}]\nset  EXT_PHY_CTRL_9                  [expr       {$EMIF_BASE_ADDR     +  0x0240}]\nset  EXT_PHY_CTRL_9_SHDW             [expr       {$EMIF_BASE_ADDR     +  0x0244}]\nset  EXT_PHY_CTRL_10                 [expr       {$EMIF_BASE_ADDR     +  0x0248}]\nset  EXT_PHY_CTRL_10_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x024c}]\nset  EXT_PHY_CTRL_11                 [expr       {$EMIF_BASE_ADDR     +  0x0250}]\nset  EXT_PHY_CTRL_11_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0254}]\nset  EXT_PHY_CTRL_12                 [expr       {$EMIF_BASE_ADDR     +  0x0258}]\nset  EXT_PHY_CTRL_12_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x025c}]\nset  EXT_PHY_CTRL_13                 [expr       {$EMIF_BASE_ADDR     +  0x0260}]\nset  EXT_PHY_CTRL_13_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0264}]\nset  EXT_PHY_CTRL_14                 [expr       {$EMIF_BASE_ADDR     +  0x0268}]\nset  EXT_PHY_CTRL_14_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x026c}]\nset  EXT_PHY_CTRL_15                 [expr       {$EMIF_BASE_ADDR     +  0x0270}]\nset  EXT_PHY_CTRL_15_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0274}]\nset  EXT_PHY_CTRL_16                 [expr       {$EMIF_BASE_ADDR     +  0x0278}]\nset  EXT_PHY_CTRL_16_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x027c}]\nset  EXT_PHY_CTRL_17                 [expr       {$EMIF_BASE_ADDR     +  0x0280}]\nset  EXT_PHY_CTRL_17_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0284}]\nset  EXT_PHY_CTRL_18                 [expr       {$EMIF_BASE_ADDR     +  0x0288}]\nset  EXT_PHY_CTRL_18_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x028c}]\nset  EXT_PHY_CTRL_19                 [expr       {$EMIF_BASE_ADDR     +  0x0290}]\nset  EXT_PHY_CTRL_19_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0294}]\nset  EXT_PHY_CTRL_20                 [expr       {$EMIF_BASE_ADDR     +  0x0298}]\nset  EXT_PHY_CTRL_20_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x029c}]\nset  EXT_PHY_CTRL_21                 [expr       {$EMIF_BASE_ADDR     +  0x02a0}]\nset  EXT_PHY_CTRL_21_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02a4}]\nset  EXT_PHY_CTRL_22                 [expr       {$EMIF_BASE_ADDR     +  0x02a8}]\nset  EXT_PHY_CTRL_22_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ac}]\nset  EXT_PHY_CTRL_23                 [expr       {$EMIF_BASE_ADDR     +  0x02b0}]\nset  EXT_PHY_CTRL_23_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02b4}]\nset  EXT_PHY_CTRL_24                 [expr       {$EMIF_BASE_ADDR     +  0x02b8}]\nset  EXT_PHY_CTRL_24_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02bc}]\nset  EXT_PHY_CTRL_25                 [expr       {$EMIF_BASE_ADDR     +  0x02c0}]\nset  EXT_PHY_CTRL_25_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02c4}]\nset  EXT_PHY_CTRL_26                 [expr       {$EMIF_BASE_ADDR     +  0x02c8}]\nset  EXT_PHY_CTRL_26_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02cc}]\nset  EXT_PHY_CTRL_27                 [expr       {$EMIF_BASE_ADDR     +  0x02d0}]\nset  EXT_PHY_CTRL_27_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02d4}]\nset  EXT_PHY_CTRL_28                 [expr       {$EMIF_BASE_ADDR     +  0x02d8}]\nset  EXT_PHY_CTRL_28_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02dc}]\nset  EXT_PHY_CTRL_29                 [expr       {$EMIF_BASE_ADDR     +  0x02e0}]\nset  EXT_PHY_CTRL_29_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02e4}]\nset  EXT_PHY_CTRL_30                 [expr       {$EMIF_BASE_ADDR     +  0x02e8}]\nset  EXT_PHY_CTRL_30_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02ec}]\nset  EXT_PHY_CTRL_31                 [expr       {$EMIF_BASE_ADDR     +  0x02f0}]\nset  EXT_PHY_CTRL_31_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02f4}]\nset  EXT_PHY_CTRL_32                 [expr       {$EMIF_BASE_ADDR     +  0x02f8}]\nset  EXT_PHY_CTRL_32_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x02fc}]\nset  EXT_PHY_CTRL_33                 [expr       {$EMIF_BASE_ADDR     +  0x0300}]\nset  EXT_PHY_CTRL_33_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0304}]\nset  EXT_PHY_CTRL_34                 [expr       {$EMIF_BASE_ADDR     +  0x0308}]\nset  EXT_PHY_CTRL_34_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x030c}]\nset  EXT_PHY_CTRL_35                 [expr       {$EMIF_BASE_ADDR     +  0x0310}]\nset  EXT_PHY_CTRL_35_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x0314}]\nset  EXT_PHY_CTRL_36                 [expr       {$EMIF_BASE_ADDR     +  0x0318}]\nset  EXT_PHY_CTRL_36_SHDW            [expr       {$EMIF_BASE_ADDR     +  0x031c}]\n\nset  WDT1_BASE_ADDR                  0x44e35000\nset  WDT1_W_PEND_WSPR                [expr       {$WDT1_BASE_ADDR     +  0x0034}]\nset  WDT1_WSPR                       [expr       {$WDT1_BASE_ADDR     +  0x0048}]\n\nset  RTC_BASE_ADDR                   0x44e3e000\nset  RTC_KICK0R                      [expr       {$RTC_BASE_ADDR      +  0x6c}]\nset  RTC_KICK1R                      [expr       {$RTC_BASE_ADDR      +  0x70}]\n\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME am437x\n}\n\nset JRC_MODULE\t\ticepick_d\nset DEBUGSS_MODULE\tdebugss\nset M3_MODULE\t\tm3_wakeupss\n\nset JRC_NAME\t\t$_CHIPNAME.$JRC_MODULE\nset DEBUGSS_NAME\t$_CHIPNAME.$DEBUGSS_MODULE\nset M3_NAME\t\t$_CHIPNAME.$M3_MODULE\nset _TARGETNAME\t\t$_CHIPNAME.mpuss\n\n#\n# M3 WakeupSS DAP\n#\nif { [info exists M3_DAP_TAPID] } {\n\tset _M3_DAP_TAPID $M3_DAP_TAPID\n} else {\n\tset _M3_DAP_TAPID 0x4b6b902f\n}\njtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable\njtag configure $M3_NAME -event tap-enable \"icepick_d_tapenable $JRC_NAME 11 0\"\ndap create $M3_NAME.dap -chain-position $M3_NAME\n\n#\n# DebugSS DAP\n#\nif { [info exists DAP_TAPID] } {\n   set _DAP_TAPID $DAP_TAPID\n} else {\n   set _DAP_TAPID 0x46b6902f\n}\njtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable\njtag configure $DEBUGSS_NAME -event tap-enable \"icepick_d_tapenable $JRC_NAME 12 0\"\ndap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME\n\n#\n# ICEpick-D (JTAG route controller)\n#\nif { [info exists JRC_TAPID] } {\n   set _JRC_TAPID $JRC_TAPID\n} else {\n   set _JRC_TAPID 0x0b98c02f\n}\njtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version\njtag configure $JRC_NAME -event setup \"jtag tapenable $DEBUGSS_NAME\"\n # some TCK tycles are required to activate the DEBUG power domain\njtag configure $JRC_NAME -event post-reset \"runtest 100\"\n\n#\n# Cortex-A9 target\n#\ntarget create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000\n\n\n# SRAM: 256K at 0x4030.0000\n$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000\n\n# Disables watchdog timer after reset otherwise board won't stay in\n# halted state.\nproc disable_watchdog { } {\n\tglobal WDT1_WSPR\n\tglobal WDT1_W_PEND_WSPR\n\tglobal _TARGETNAME\n\n\tset curstate [$_TARGETNAME curstate]\n\n\tif { [string compare $curstate halted] == 0 } {\n\t\tset WDT_DISABLE_SEQ1\t0xaaaa\n\t\tset WDT_DISABLE_SEQ2\t0x5555\n\n\t\tmww phys $WDT1_WSPR $WDT_DISABLE_SEQ1\n\n\t\t# Empty body to make sure this executes as fast as possible.\n\t\t# We don't want any delays here otherwise romcode might start\n\t\t# executing and end up changing state of certain IPs.\n\t\twhile { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }\n\n\t\tmww phys $WDT1_WSPR $WDT_DISABLE_SEQ2\n\t\twhile { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }\n\t}\n}\n\nproc ceil { x y } {\n\treturn [ expr {($x + $y - 1) / $y} ]\n}\n\nproc device_type { } {\n\tglobal CONTROL_STATUS\n\n\tset tmp [ mrw $CONTROL_STATUS ]\n\tset tmp [ expr {$tmp & 0x700} ]\n\tset tmp [ expr {$tmp >> 8} ]\n\n\treturn $tmp\n}\n\nproc get_input_clock_frequency { } {\n\tglobal CONTROL_STATUS\n\n\tif { [ device_type ] != 3 } {\n\t\terror \"Unknown device type\\n\"\n\t\treturn -1\n\t}\n\n\tset freq [ mrw $CONTROL_STATUS ]\n\tset freq [ expr {$freq & 0x00c00000} ]\n\tset freq [ expr {$freq >> 22} ]\n\n\tswitch $freq {\n\t\t0 {\n\t\t\tset CLKIN 19200000\n\t\t}\n\n\t\t1 {\n\t\t\tset CLKIN 24000000\n\t\t}\n\n\t\t2 {\n\t\t\tset CLKIN 25000000\n\t\t}\n\n\t\t3 {\n\t\t\tset CLKIN 26000000\n\t\t}\n\t}\n\n\treturn $CLKIN\n}\n\nproc mpu_pll_config { CLKIN N M M2 } {\n\tglobal CM_CLKMODE_DPLL_MPU\n\tglobal CM_CLKSEL_DPLL_MPU\n\tglobal CM_DIV_M2_DPLL_MPU\n\tglobal CM_IDLEST_DPLL_MPU\n\n\tset clksel [ mrw $CM_CLKSEL_DPLL_MPU ]\n\tset div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ]\n\n\tmww $CM_CLKMODE_DPLL_MPU 0x4\n\twhile { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { }\n\n\tset clksel [ expr {$clksel & (~0x7ffff)} ]\n\tset clksel [ expr {$clksel | ($M << 0x8) | $N} ]\n\tmww $CM_CLKSEL_DPLL_MPU $clksel\n\n\tset div_m2 [ expr {$div_m2 & (~0x1f)} ]\n\tset div_m2 [ expr {$div_m2 | $M2} ]\n\tmww $CM_DIV_M2_DPLL_MPU $div_m2\n\n\tmww $CM_CLKMODE_DPLL_MPU 0x7\n\twhile { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { }\n\n\techo \"MPU DPLL locked\"\n}\n\nproc core_pll_config { CLKIN N M M4 M5 M6 } {\n\tglobal CM_CLKMODE_DPLL_CORE\n\tglobal CM_CLKSEL_DPLL_CORE\n\tglobal CM_DIV_M4_DPLL_CORE\n\tglobal CM_DIV_M5_DPLL_CORE\n\tglobal CM_DIV_M6_DPLL_CORE\n\tglobal CM_IDLEST_DPLL_CORE\n\n\tset clksel [ mrw $CM_CLKSEL_DPLL_CORE ]\n\n\tmww $CM_CLKMODE_DPLL_CORE 0x4\n\twhile { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { }\n\n\tset clksel [ expr {$clksel & (~0x7ffff)} ]\n\tset clksel [ expr {$clksel | ($M << 0x8) | $N} ]\n\tmww $CM_CLKSEL_DPLL_CORE $clksel\n\tmww $CM_DIV_M4_DPLL_CORE $M4\n\tmww $CM_DIV_M5_DPLL_CORE $M5\n\tmww $CM_DIV_M6_DPLL_CORE $M6\n\n\tmww $CM_CLKMODE_DPLL_CORE 0x7\n\twhile { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { }\n\n\techo \"CORE DPLL locked\"\n}\n\nproc per_pll_config { CLKIN N M M2 } {\n\tglobal CM_CLKMODE_DPLL_PER\n\tglobal CM_CLKSEL_DPLL_PER\n\tglobal CM_DIV_M2_DPLL_PER\n\tglobal CM_IDLEST_DPLL_PER\n\n\tset x [ expr {$M * $CLKIN / 1000000} ]\n\tset y [ expr {($N + 1) * 250} ]\n\tset sd [ ceil $x $y ]\n\n\tset clksel [ mrw $CM_CLKSEL_DPLL_PER ]\n\tset div_m2 [ mrw $CM_DIV_M2_DPLL_PER ]\n\n\tmww $CM_CLKMODE_DPLL_PER 0x4\n\twhile { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { }\n\n\tset clksel [ expr {$clksel & (~0xff0fffff)} ]\n\tset clksel [ expr {$clksel | ($M << 0x8) | $N} ]\n\tset clksel [ expr {$clksel | ($sd << 24)} ]\n\tmww $CM_CLKSEL_DPLL_PER $clksel\n\n\tset div_m2 [ expr {0xffffff80 | $M2} ]\n\n\tmww $CM_CLKMODE_DPLL_PER 0x7\n\twhile { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { }\n\n\techo \"PER DPLL locked\"\n}\n\nproc ddr_pll_config { CLKIN N M M2 M4 } {\n\tglobal CM_CLKMODE_DPLL_DDR\n\tglobal CM_CLKSEL_DPLL_DDR\n\tglobal CM_DIV_M2_DPLL_DDR\n\tglobal CM_DIV_M4_DPLL_DDR\n\tglobal CM_IDLEST_DPLL_DDR\n\n\tset clksel [ mrw $CM_CLKSEL_DPLL_DDR ]\n\tset div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ]\n\n\tmww $CM_CLKMODE_DPLL_DDR 0x4\n\twhile { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { }\n\n\tset clksel [ expr {$clksel & (~0x7ffff)} ]\n\tset clksel [ expr {$clksel | ($M << 8) | $N} ]\n\tmww $CM_CLKSEL_DPLL_DDR $clksel\n\n\tset div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ]\n\tmww $CM_DIV_M2_DPLL_DDR $div_m2\n\tmww $CM_DIV_M4_DPLL_DDR $M4\n\n\tmww $CM_CLKMODE_DPLL_DDR 0x7\n\twhile { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { }\n\n\techo \"DDR DPLL Locked\"\n}\n\nproc config_opp100 { } {\n\tset CLKIN [ get_input_clock_frequency ]\n\n\tif { $CLKIN == -1 } {\n\t\treturn -1\n\t}\n\n\tswitch $CLKIN {\n\t\t24000000 {\n\t\t\tmpu_pll_config   $CLKIN  0  25   1\n\t\t\tcore_pll_config  $CLKIN  2  125  10  8  4\n\t\t\tper_pll_config   $CLKIN  9  400  5\n\t\t\tddr_pll_config   $CLKIN  2  50   1   2\n\t\t}\n\n\t\t25000000 {\n\t\t\tmpu_pll_config   $CLKIN  0  24   1\n\t\t\tcore_pll_config  $CLKIN  0  40   10  8  4\n\t\t\tper_pll_config   $CLKIN  9  384  5\n\t\t\tddr_pll_config   $CLKIN  0  16   1   2\n\t\t}\n\n\t\t26000000 {\n\t\t\tmpu_pll_config   $CLKIN  12  300  1\n\t\t\tcore_pll_config  $CLKIN  12  500  10  8  4\n\t\t\tper_pll_config   $CLKIN  12  480  5\n\t\t\tddr_pll_config   $CLKIN  12  200  1   2\n\t\t}\n\n\t\t19200000 {\n\t\t\tmpu_pll_config   $CLKIN  3   125  1\n\t\t\tcore_pll_config  $CLKIN  11  625  10  8  4\n\t\t\tper_pll_config   $CLKIN  7   400  5\n\t\t\tddr_pll_config   $CLKIN  2   125  1   2\n\t\t}\n\t}\n}\n\nproc emif_prcm_clk_enable { } {\n\tglobal CM_PER_EMIF_FW_CLKCTRL\n\tglobal CM_PER_EMIF_CLKCTRL\n\n\tmww $CM_PER_EMIF_FW_CLKCTRL 0x02\n\tmww $CM_PER_EMIF_CLKCTRL 0x02\n\n\twhile { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { }\n}\n\nproc vtp_enable { } {\n\tglobal VTP_CTRL_REG\n\n\tset vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }]\n\tmww $VTP_CTRL_REG $vtp\n\n\tset vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }]\n\tmww $VTP_CTRL_REG $vtp\n\n\tset vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }]\n\tmww $VTP_CTRL_REG $vtp\n\n}\n\nproc config_ddr_ioctrl { } {\n\tglobal DDR_ADDRCTRL_IOCTRL\n\tglobal DDR_ADDRCTRL_WD0_IOCTRL\n\tglobal DDR_ADDRCTRL_WD1_IOCTRL\n\tglobal DDR_CKE_CTRL\n\tglobal DDR_DATA0_IOCTRL\n\tglobal DDR_DATA1_IOCTRL\n\tglobal DDR_DATA2_IOCTRL\n\tglobal DDR_DATA3_IOCTRL\n\tglobal DDR_IO_CTRL\n\n\tmww $DDR_ADDRCTRL_IOCTRL\t0x84\n\tmww $DDR_ADDRCTRL_WD0_IOCTRL\t0x00\n\tmww $DDR_ADDRCTRL_WD1_IOCTRL\t0x00\n\tmww $DDR_DATA0_IOCTRL\t\t0x84\n\tmww $DDR_DATA1_IOCTRL\t\t0x84\n\tmww $DDR_DATA2_IOCTRL\t\t0x84\n\tmww $DDR_DATA3_IOCTRL\t\t0x84\n\n\tmww $DDR_IO_CTRL\t\t0x00\n\tmww $DDR_CKE_CTRL\t\t0x03\n}\n\nproc config_ddr_phy { } {\n\tglobal EMIF_DDR_PHY_CTRL_1\n\tglobal EMIF_DDR_PHY_CTRL_1_SHDW\n\n\tglobal EXT_PHY_CTRL_1\n\tglobal EXT_PHY_CTRL_1_SHDW\n\tglobal EXT_PHY_CTRL_2\n\tglobal EXT_PHY_CTRL_2_SHDW\n\tglobal EXT_PHY_CTRL_3\n\tglobal EXT_PHY_CTRL_3_SHDW\n\tglobal EXT_PHY_CTRL_4\n\tglobal EXT_PHY_CTRL_4_SHDW\n\tglobal EXT_PHY_CTRL_5\n\tglobal EXT_PHY_CTRL_5_SHDW\n\tglobal EXT_PHY_CTRL_6\n\tglobal EXT_PHY_CTRL_6_SHDW\n\tglobal EXT_PHY_CTRL_7\n\tglobal EXT_PHY_CTRL_7_SHDW\n\tglobal EXT_PHY_CTRL_8\n\tglobal EXT_PHY_CTRL_8_SHDW\n\tglobal EXT_PHY_CTRL_9\n\tglobal EXT_PHY_CTRL_9_SHDW\n\tglobal EXT_PHY_CTRL_10\n\tglobal EXT_PHY_CTRL_10_SHDW\n\tglobal EXT_PHY_CTRL_11\n\tglobal EXT_PHY_CTRL_11_SHDW\n\tglobal EXT_PHY_CTRL_12\n\tglobal EXT_PHY_CTRL_12_SHDW\n\tglobal EXT_PHY_CTRL_13\n\tglobal EXT_PHY_CTRL_13_SHDW\n\tglobal EXT_PHY_CTRL_14\n\tglobal EXT_PHY_CTRL_14_SHDW\n\tglobal EXT_PHY_CTRL_15\n\tglobal EXT_PHY_CTRL_15_SHDW\n\tglobal EXT_PHY_CTRL_16\n\tglobal EXT_PHY_CTRL_16_SHDW\n\tglobal EXT_PHY_CTRL_17\n\tglobal EXT_PHY_CTRL_17_SHDW\n\tglobal EXT_PHY_CTRL_18\n\tglobal EXT_PHY_CTRL_18_SHDW\n\tglobal EXT_PHY_CTRL_19\n\tglobal EXT_PHY_CTRL_19_SHDW\n\tglobal EXT_PHY_CTRL_20\n\tglobal EXT_PHY_CTRL_20_SHDW\n\tglobal EXT_PHY_CTRL_21\n\tglobal EXT_PHY_CTRL_21_SHDW\n\tglobal EXT_PHY_CTRL_22\n\tglobal EXT_PHY_CTRL_22_SHDW\n\tglobal EXT_PHY_CTRL_23\n\tglobal EXT_PHY_CTRL_23_SHDW\n\tglobal EXT_PHY_CTRL_24\n\tglobal EXT_PHY_CTRL_24_SHDW\n\tglobal EXT_PHY_CTRL_25\n\tglobal EXT_PHY_CTRL_25_SHDW\n\tglobal EXT_PHY_CTRL_26\n\tglobal EXT_PHY_CTRL_26_SHDW\n\tglobal EXT_PHY_CTRL_27\n\tglobal EXT_PHY_CTRL_27_SHDW\n\tglobal EXT_PHY_CTRL_28\n\tglobal EXT_PHY_CTRL_28_SHDW\n\tglobal EXT_PHY_CTRL_29\n\tglobal EXT_PHY_CTRL_29_SHDW\n\tglobal EXT_PHY_CTRL_30\n\tglobal EXT_PHY_CTRL_30_SHDW\n\tglobal EXT_PHY_CTRL_31\n\tglobal EXT_PHY_CTRL_31_SHDW\n\tglobal EXT_PHY_CTRL_32\n\tglobal EXT_PHY_CTRL_32_SHDW\n\tglobal EXT_PHY_CTRL_33\n\tglobal EXT_PHY_CTRL_33_SHDW\n\tglobal EXT_PHY_CTRL_34\n\tglobal EXT_PHY_CTRL_34_SHDW\n\tglobal EXT_PHY_CTRL_35\n\tglobal EXT_PHY_CTRL_35_SHDW\n\tglobal EXT_PHY_CTRL_36\n\tglobal EXT_PHY_CTRL_36_SHDW\n\n\tmww $EMIF_DDR_PHY_CTRL_1\t0x8009\n\tmww $EMIF_DDR_PHY_CTRL_1_SHDW\t0x8009\n\n\tset slave_ratio\t\t0x80\n\tset gatelvl_init_ratio\t0x20\n\tset wr_dqs_slave_delay\t0x60\n\tset rd_dqs_slave_delay\t0x60\n\tset dq_offset\t\t0x40\n\tset gatelvl_init_mode\t0x01\n\tset wr_data_slave_delay\t0x80\n\tset gatelvl_num_dq0 0x0f\n\tset wrlvl_num_dq0 0x0f\n\n\tmww $EXT_PHY_CTRL_1        [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]\n\tmww $EXT_PHY_CTRL_1_SHDW   [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]\n\tmww $EXT_PHY_CTRL_26       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_26_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_27       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_27_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_28       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_28_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_29       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_29_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_30       [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_30_SHDW  [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]\n\tmww $EXT_PHY_CTRL_31       0x00\n\tmww $EXT_PHY_CTRL_31_SHDW  0x00\n\tmww $EXT_PHY_CTRL_32       0x00\n\tmww $EXT_PHY_CTRL_32_SHDW  0x00\n\tmww $EXT_PHY_CTRL_33       0x00\n\tmww $EXT_PHY_CTRL_33_SHDW  0x00\n\tmww $EXT_PHY_CTRL_34       0x00\n\tmww $EXT_PHY_CTRL_34_SHDW  0x00\n\tmww $EXT_PHY_CTRL_35       0x00\n\tmww $EXT_PHY_CTRL_35_SHDW  0x00\n\tmww $EXT_PHY_CTRL_22       0x00\n\tmww $EXT_PHY_CTRL_22_SHDW  0x00\n\tmww $EXT_PHY_CTRL_23       [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]\n\tmww $EXT_PHY_CTRL_23_SHDW  [ expr {($wr_dqs_slave_delay  <<  16) | $rd_dqs_slave_delay} ]\n\tmww $EXT_PHY_CTRL_24       [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ]\n\tmww $EXT_PHY_CTRL_24_SHDW  [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ]\n\tmww $EXT_PHY_CTRL_25       [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]\n\tmww $EXT_PHY_CTRL_25_SHDW  [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]\n\tmww $EXT_PHY_CTRL_36       [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]\n\tmww $EXT_PHY_CTRL_36_SHDW  [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]\n}\n\nproc config_ddr_timing { } {\n\tglobal EMIF_SDRAM_TIM_1\n\tglobal EMIF_SDRAM_TIM_2\n\tglobal EMIF_SDRAM_TIM_3\n\tglobal EMIF_SDRAM_TIM_1_SHDW\n\tglobal EMIF_SDRAM_TIM_2_SHDW\n\tglobal EMIF_SDRAM_TIM_3_SHDW\n\tglobal EMIF_ZQ_CONFIG\n\n\tmww $EMIF_SDRAM_TIM_1\t\t0xeaaad4db\n\tmww $EMIF_SDRAM_TIM_1_SHDW\t0xeaaad4db\n\n\tmww $EMIF_SDRAM_TIM_2\t\t0x266b7fda\n\tmww $EMIF_SDRAM_TIM_2_SHDW\t0x266b7fda\n\n\tmww $EMIF_SDRAM_TIM_3\t\t0x107f8678\n\tmww $EMIF_SDRAM_TIM_3_SHDW\t0x107f8678\n\n\tmww $EMIF_ZQ_CONFIG\t\t0x50074be4\n}\n\nproc config_ddr_pm { } {\n\tglobal EMIF_PWR_MGMT_CTRL\n\tglobal EMIF_PWR_MGMT_CTRL_SHDW\n\tglobal EMIF_DLL_CALIB_CTRL\n\tglobal EMIF_DLL_CALIB_CTRL_SHDW\n\tglobal EMIF_TEMP_ALERT_CONFIG\n\n\tmww $EMIF_PWR_MGMT_CTRL\t\t0x00\n\tmww $EMIF_PWR_MGMT_CTRL_SHDW\t0x00\n\tmww $EMIF_DLL_CALIB_CTRL\t0x00050000\n\tmww $EMIF_DLL_CALIB_CTRL_SHDW\t0x00050000\n\tmww $EMIF_TEMP_ALERT_CONFIG\t0x00\n}\n\nproc config_ddr_priority { } {\n\tglobal EMIF_PRI_COS_MAP\n\tglobal EMIF_CONNID_COS_1_MAP\n\tglobal EMIF_CONNID_COS_2_MAP\n\tglobal EMIF_RD_WR_EXEC_THRSH\n\tglobal COS_CONFIG\n\n\tmww $EMIF_PRI_COS_MAP       0x00\n\tmww $EMIF_CONNID_COS_1_MAP  0x00\n\tmww $EMIF_CONNID_COS_2_MAP  0x0\n\tmww $EMIF_RD_WR_EXEC_THRSH  0x0405\n\tmww $COS_CONFIG             0x00ffffff\n}\n\nproc config_ddr3 { SDRAM_CONFIG } {\n\tglobal CM_DLL_CTRL\n\tglobal EMIF_IODFT_TLGC\n\tglobal EMIF_RDWR_LVL_CTRL\n\tglobal EMIF_RDWR_LVL_RMP_CTRL\n\tglobal EMIF_SDRAM_CONFIG\n\tglobal EMIF_SDRAM_CONFIG_EXT\n\tglobal EMIF_SDRAM_REF_CTRL\n\tglobal EMIF_SDRAM_REF_CTRL_SHDW\n\tglobal EMIF_STATUS\n\tglobal EXT_PHY_CTRL_36\n\tglobal EXT_PHY_CTRL_36_SHDW\n\n\temif_prcm_clk_enable\n\tvtp_enable\n\n\tset dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }]\n\tmww $CM_DLL_CTRL $dll\n\twhile { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }\n\n\tconfig_ddr_ioctrl\n\n\tmww $EMIF_SDRAM_CONFIG_EXT\t0xc163\n\tmww $EMIF_IODFT_TLGC\t\t0x2011\n\tmww $EMIF_IODFT_TLGC\t\t0x2411\n\tmww $EMIF_IODFT_TLGC\t\t0x2011\n\tmww $EMIF_SDRAM_REF_CTRL\t0x80003000\n\n\tconfig_ddr_phy\n\n\tmww $EMIF_IODFT_TLGC\t\t0x2011\n\tmww $EMIF_IODFT_TLGC\t\t0x2411\n\tmww $EMIF_IODFT_TLGC\t\t0x2011\n\n\tconfig_ddr_timing\n\tconfig_ddr_pm\n\tconfig_ddr_priority\n\n\tmww $EMIF_SDRAM_REF_CTRL\t0x3000\n\tmww $EMIF_SDRAM_CONFIG\t\t$SDRAM_CONFIG\n\n\tmww $EMIF_SDRAM_REF_CTRL\t0x0c30\n\tmww $EMIF_SDRAM_REF_CTRL_SHDW\t0x0c30\n\n\tsleep 10\n\n\tset tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }]\n\tmww $EXT_PHY_CTRL_36\t\t$tmp\n\tmww $EXT_PHY_CTRL_36_SHDW\t$tmp\n\n\tmww $EMIF_RDWR_LVL_RMP_CTRL\t0x80000000\n\tmww $EMIF_RDWR_LVL_CTRL\t\t0x80000000\n\n\twhile { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { }\n\n\tif { [ mrw $EMIF_STATUS ]  & 0x70 } {\n\t\terror \"DDR3 Hardware Leveling incomplete!!!\"\n\t}\n}\n\nproc init_platform { SDRAM_CONFIG } {\n\tconfig_opp100\n\tconfig_ddr3 $SDRAM_CONFIG\n}\n\n$_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 }\n$_TARGETNAME configure -event reset-end { disable_watchdog }\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/amdm37x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Copyright (C)   2010-2011   by Karl Kurbjun\n# Copyright (C)   2009-2011   by Øyvind Harboe\n# Copyright (C)   2009        by David Brownell\n# Copyright (C)   2009        by Magnus Lundin\n#\n# TI AM/DM37x Technical Reference Manual (Version R)\n#  http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf\n#\n# This script is based on the AM3517 initialization.  It should be considered\n# preliminary since it needs more complete testing and only the basic\n# operations work.\n#\n\n###############################################################################\n# User modifiable parameters\n###############################################################################\n\n# This script uses the variable CHIPTYPE to determine whether this is an AM35x\n# or DM37x target. If CHIPTYPE is not set it will error out.\nif { [info exists CHIPTYPE] } {\n\n   if { [info exists CHIPNAME] } {\n      set _CHIPNAME $CHIPNAME\n   } else {\n      set _CHIPNAME $CHIPTYPE\n   }\n\n   switch $CHIPTYPE {\n      dm37x {\n         # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan\n         set _JRC_TAPID \"-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f\"\n      }\n      am35x {\n         # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan\n         set _JRC_TAPID \"-expected-id 0x0b7ae02f -expected-id 0x0b86802f\"\n      }\n      default {\n         error \"ERROR: CHIPTYPE was set, but it was not set to a valid value.  Acceptable values are \\\"dm37x\\\" or \\\"am35x\\\".\"\n      }\n   }\n} else {\n  error \"ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \\\"am35x\\\" for the AM35x or \\\"dm37x\\\" for the DM37x series in the board configuration.\"\n}\n\n# Run the adapter at the fastest acceptable speed with the slowest possible\n# core clock.\nadapter speed 10\n\n###############################################################################\n# JTAG setup\n# The OpenOCD commands are described in the TAP Declaration section\n#  http://openocd.org/doc/html/TAP-Declaration.html\n###############################################################################\n\n# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More\n#  can be read about this module in sprugn4r in chapter 27:  \"Debug and\n#  Emulation\".  The module is used to route the JTAG chain to the various\n#  subsystems in the chip.\nsource [find target/icepick.cfg]\n\n# The TAP order should be described from the TDO connection in OpenOCD to the\n#  TDI pin.  The OpenOCD FAQ describes this in more detail:\n#  http://openocd.org/doc/html/FAQ.html\n\n# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO:\n#\n#  Device   |  TAP number\n#  ---------|------------\n#  DAP      |  3\n#  Sequencer|  2   Note: The sequencer is an ARM968\n#  DSP      |  1\n#  D2D      |  0\n#\n# Right now the only secondary tap enabled is the DAP so the rest are left\n# undescribed.\n\n######\n# Start of Chain Description\n# The Secondary TAPs all have enable functions defined for use with the ICEPick\n# Only the DAP is enabled.  The AM37xx does not have the Sequencer or DSP but\n# the TAP numbers for ICEPick do not change.\n#\n# TODO: A disable function should also be added.\n######\n\n# Secondary TAP: DAP is closest to the TDO output\n# The TAP enable event also needs to be described\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable\njtag configure $_CHIPNAME.cpu -event tap-enable \\\n   \"icepick_c_tapenable $_CHIPNAME.jrc 3\"\n\n# These taps are only present in the DM37x series.\nif { $CHIPTYPE == \"dm37x\" } {\n   # Secondary TAP: Sequencer (ARM968) it is not in the chain by default\n   # The ICEPick can be used to enable it in the chain.\n   jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable\n   jtag configure $_CHIPNAME.arm2 -event tap-enable \\\n      \"icepick_c_tapenable $_CHIPNAME.jrc 2\"\n\n   # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)\n   # The ICEPick can be used to enable it in the chain.\n   jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable\n   jtag configure $_CHIPNAME.dsp -event tap-enable \\\n      \"icepick_c_tapenable $_CHIPNAME.jrc 1\"\n}\n\n# Secondary TAP: D2D it is not in the chain by default (-disable)\n# The ICEPick can be used to enable it in the chain.\n# This IRLEN is probably incorrect - not sure where the documentation is.\njtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable\njtag configure $_CHIPNAME.d2d -event tap-enable \\\n   \"icepick_c_tapenable $_CHIPNAME.jrc 0\"\n\n# Primary TAP: ICEPick - it is closest to TDI so last in the chain\neval \"jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID\"\n\n######\n# End of Chain Description\n######\n\n######\n# Start JTAG TAP events\n######\n\n# some TCK tycles are required to activate the DEBUG power domain\njtag configure $_CHIPNAME.jrc -event post-reset \"runtest 100\"\n\n# Enable the DAP TAP\njtag configure $_CHIPNAME.jrc -event setup \"jtag tapenable $_CHIPNAME.dap\"\n\n######\n# End JTAG TAP events\n######\n\n###############################################################################\n# Target Setup:\n# This section is described in the OpenOCD documentation under CPU Configuration\n#  http://openocd.org/doc/html/CPU-Configuration.html\n###############################################################################\n\n# Create the CPU target to be used with GDB:  Cortex-A8, using DAP\nset _TARGETNAME $_CHIPNAME.cpu\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap\n\n# The DM37x has 64K of SRAM starting at address 0x4020_0000.  Allow the first\n# 16K to be used as a scratchpad for OpenOCD.\n\n$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000\n\n######\n# Start Target Reset Event Setup:\n######\n\n# Set the JTAG clock down to 10 kHz to be sure that it will work with the\n#  slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up\n#  *after* PLL and clock tree setup.\n\n$_TARGETNAME configure -event \"reset-start\" { adapter speed 10 }\n\n# Describe the reset assert process for openocd - this is asserted with the\n# ICEPick\n$_TARGETNAME configure -event \"reset-assert\" {\n\n   global _CHIPNAME\n\n   # assert warm system reset through ICEPick\n   icepick_c_wreset $_CHIPNAME.jrc\n}\n\n# After the reset is asserted we need to re-initialize debugging and speed up\n# the JTAG clock.\n\n$_TARGETNAME configure -event reset-assert-post {\n\n   global _TARGETNAME\n   amdm37x_dbginit $_TARGETNAME\n   adapter speed 1000\n}\n\n$_TARGETNAME configure -event gdb-attach {\n\n   global _TARGETNAME\n   amdm37x_dbginit $_TARGETNAME\n\n   echo \"Halting target\"\n   halt\n}\n\n######\n# End Target Reset Event Setup:\n######\n\n###############################################################################\n# Target Functions\n# Add any functions needed for the target here\n###############################################################################\n\n# Run this to enable invasive debugging.  This is run automatically in the\n# reset sequence.\nproc amdm37x_dbginit {target} {\n   # General Cortex-A8 debug initialisation\n   cortex_a dbginit\n\n   # Enable DBGEN signal.  This signal is described in the ARM v7 TRM, but\n   # access to the signal appears to be implementation specific.  TI does not\n   # describe this register much except a quick line that states DBGEM (sic) is\n   # at this address and this bit.\n   $target mww phys 0x5401d030 0x00002000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ampere_emag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# OpenOCD Target Configuration for eMAG ARMv8 Processor\n#\n# Copyright (c) 2019-2021, Ampere Computing LLC\n#\n\n#\n# Configure defaults for target\n# Can be overriden in board configuration file\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME emag\n}\n\nif { [info exists NUMCORES] } {\n\tset _NUMCORES $NUMCORES\n} else {\n\tset _NUMCORES 32\n}\n\nif { [info exists ENDIAN] } {\n\tset _ENDIAN $ENDIAN\n} else {\n\tset _ENDIAN little\n}\n\nif { [info exists CPUTAPID ] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x4BA00477\n}\n\n#\n# Configure JTAG TAP\n#\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_CPUTAPID\nset _TAPNAME $_CHIPNAME.cpu\n\nset _DAPNAME ${_TAPNAME}_dap\nset _APNUM 1\ndap create $_DAPNAME -chain-position $_TAPNAME\n$_DAPNAME apsel $_APNUM\n\n# Create the DAP AP0 MEM-AP AHB-AP target\ntarget create AHB mem_ap -endian $_ENDIAN -dap $_DAPNAME -ap-num 0\n\n# Create the DAP AP1 MEM-AP APB-AP target\ntarget create APB mem_ap -endian $_ENDIAN -dap $_DAPNAME -ap-num 1\n\n#\n# Configure target CPUs\n#\n\n# Build string used to enable smp mode\nset _SMP_STR \"target smp\"\n\nfor {set _i 0} {$_i < $_NUMCORES} {incr _i} {\n\t# Format a string to reference which CPU target to use\n\tset _TARGETNAME [format \"${_TAPNAME}_%02d\" $_i]\n\n\t# Create and configure Cross Trigger Interface (CTI) - required for halt and resume\n\tset _CTINAME $_TARGETNAME.cti\n\tcti create $_CTINAME -dap $_DAPNAME -ap-num $_APNUM -baseaddr [expr {0xFC020000 + ($_i << 20)}]\n\n\t# Create the target\n\ttarget create $_TARGETNAME aarch64 -endian $_ENDIAN -dap $_DAPNAME -ap-num $_APNUM -cti $_CTINAME -coreid $_i\n\tset _SMP_STR \"$_SMP_STR $_TARGETNAME\"\n\n\t# Clear CTI output/input enables that are not configured by OpenOCD for aarch64\n\t$_TARGETNAME configure -event examine-start [subst {\n\t\t$_CTINAME write INEN0 0x00000000\n\t\t$_CTINAME write INEN1 0x00000000\n\t\t$_CTINAME write INEN2 0x00000000\n\t\t$_CTINAME write INEN3 0x00000000\n\t\t$_CTINAME write INEN4 0x00000000\n\t\t$_CTINAME write INEN5 0x00000000\n\t\t$_CTINAME write INEN6 0x00000000\n\t\t$_CTINAME write INEN7 0x00000000\n\t\t$_CTINAME write INEN8 0x00000000\n\n\t\t$_CTINAME write OUTEN2 0x00000000\n\t\t$_CTINAME write OUTEN3 0x00000000\n\t\t$_CTINAME write OUTEN4 0x00000000\n\t\t$_CTINAME write OUTEN5 0x00000000\n\t\t$_CTINAME write OUTEN6 0x00000000\n\t\t$_CTINAME write OUTEN7 0x00000000\n\t\t$_CTINAME write OUTEN8 0x00000000\n\t}]\n\n\t# Enable OpenOCD HWTHREAD RTOS feature for GDB thread (CPU) selection support\n\t# This feature presents CPU cores (\"hardware threads\") in an SMP system as threads to GDB\n\t$_TARGETNAME configure -rtos hwthread\n}\neval $_SMP_STR\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ampere_qs_mq.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# OpenOCD Target Configuration for Ampere Altra (\"Quicksilver\") and\n# Ampere Altra Max (\"Mystique\") processors\n#\n# Copyright (c) 2019-2022, Ampere Computing LLC\n\n# Command Line Argument Description\n#\n# SPLITSMP\n# Only used for dual socket systems. Do not use for a single socket setup.\n# Option pertains to the ARMv8 target core naming in a dual socket setup.\n# If specified, name all ARMv8 cores per socket as individual SMP sessions.\n# If not specified, name ARMv8 cores from both sockets as one SMP session.\n# This option is used in conjunction with the SMP_STR board file option.\n# Syntax: -c \"set SPLITSMP {}\"\n#\n# PHYS_IDX\n# Enable OpenOCD ARMv8 core target physical indexing.\n# If not specified, defaults to OpenOCD ARMv8 core target logical indexing.\n# Syntax: -c \"set PHYS_IDX {}\"\n#\n# CHIPNAME\n# Specifies the name of the chip.\n# Will typically be either qs, qs0, qs1, mq, mq0 or mq1.\n# If not specified, defaults to qs.\n# Syntax: -c \"set CHIPNAME {qs}\"\n#\n# SYSNAME\n# Specifies the name of the system.\n# Will typically be either qs or mq.\n# If not specified, defaults to qs.\n# Syntax: -c \"set SYSNAME {qs}\"\n#\n# Life-Cycle State (LCS)\n# If not specified, defaults to \"Secure LCS\".\n# LCS=0, \"Secure LCS\"\n# LCS=1, \"Chip Manufacturing LCS\"\n# Syntax: -c \"set LCS {0}\"\n# Syntax: -c \"set LCS {1}\"\n#\n# CORELIST\n# Specify available physical cores by number.\n# Example syntax to connect to physical cores 16 and 17.\n# Syntax: -c \"set CORELIST {16 17}\"\n#\n# COREMASK_LO\n# Specify available physical cores 0-63 by mask.\n# Example syntax to connect to physical cores 16 and 17.\n# Syntax: -c \"set COREMASK_LO {0x0000000000030000}\"\n#\n# COREMASK_HI\n# Specify available physical cores 64 and above by mask.\n# Example syntax to connect to physical cores 94 and 95.\n# Syntax: -c \"set COREMASK_HI {0x00000000C0000000}\"\n#\n# ARMV8_TAPID\n# Can override the ARMV8 TAPID default value if necessary.\n# Experimental Use. Most users will not use this option.\n# Syntax: -c \"set ARMV8_TAPID {0x3BA06477}\"\n#\n# SMPMPRO_TAPID\n# Can override the SMPMPRO TAPID default value if necessary.\n# Experimental Use. Most users will not use this option.\n# Syntax: -c \"set SMPMPRO_TAPID {0x4BA00477}\"\n#\n#\n# Board File Argument Description\n# These optional arguments are defined in the board file and\n# referenced by the target file. See the corresponding board\n# files for examples of their use.\n#\n# SMP_STR\n# This option is used primarily for a dual socket system and it is not\n# recommended for a single socket setup. This option configures whether\n# the SMP ARMv8 core grouping is maintained at the board or target cfg level.\n# Specify the option if the SMP core grouping is defined at the board level.\n# Do not specify if the SMP core grouping is defined at the chip level.\n# If not specified, defaults to SMP core grouping defined per socket.\n# If specified, \"SMP_STR=target smp\", the SMP core grouping is maintained\n# at the board cfg level.\n# Used in conjunction with the SPLITSMP option to group two chips into\n# a single SMP configuration or maintain as two separate SMP sessions.\n#\n# CORE_INDEX_OFFSET\n# Specifies the starting logical core index value.\n# Used for dual-socket systems.\n# For socket #0, set to 0.\n# For socket #1, set the starting logical core based from\n# the last logical core on socket #0.\n# If not specified, defaults to 0.\n#\n\n#\n# Configure defaults for target.\n# Can be overridden in board configuration file.\n#\n\nif { [info exists SMP_STR] } {\n\t# SMP configured at the dual socket board level\n\tset _SMP_STR $SMP_STR\n} else {\n\t# SMP configured at the single socket target level\n\tset _SMP_STR \"target smp\"\n}\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME qs\n}\n\nif { [info exists SYSNAME] } {\n\tset _SYSNAME $SYSNAME\n} else {\n\tset _SYSNAME qs\n}\n\nif { [info exists CORE_INDEX_OFFSET] } {\n\tset _CORE_INDEX_OFFSET $CORE_INDEX_OFFSET\n} else {\n\tset _CORE_INDEX_OFFSET 0\n}\n\nif { [info exists ENDIAN] } {\n\tset _ENDIAN $ENDIAN\n} else {\n\tset _ENDIAN little\n}\n\nif { [info exists ARMV8_TAPID] } {\n\tset _ARMV8_TAPID $ARMV8_TAPID\n} else {\n\tif { [info exists MQ_ENABLE] } {\n\t\t# Configure for Mystique\n\t\tset _ARMV8_TAPID 0x3BA06477\n\t\tset _MAX_CORE 128\n\t} else {\n\t\t# Configure for Quicksilver\n\t\tset _ARMV8_TAPID 0x2BA06477\n\t\tset _MAX_CORE 80\n\t}\n}\n\nif { [info exists SMPMPRO_TAPID] } {\n\tset _SMPMPRO_TAPID $SMPMPRO_TAPID\n} else {\n\tset _SMPMPRO_TAPID 0x4BA00477\n}\n\nif { [info exists CORELIST] } {\n\tset _CORELIST $CORELIST\n} else {\n\tif { [info exists COREMASK_LO] } {\n\t\tset _COREMASK_LO $COREMASK_LO\n\t} else {\n\t\tset _COREMASK_LO 0x0\n\t}\n\n\tif { [info exists COREMASK_HI] } {\n\t\tset _COREMASK_HI $COREMASK_HI\n\t} else {\n\t\tset _COREMASK_HI 0x0\n\t}\n\n\tset _CORELIST {}\n\n\tset _MASK 0x1\n\tfor {set i 0} {$i < 64} {incr i} {\n\t\tif { [expr {$_COREMASK_LO & $_MASK}] != 0x0 } {\n\t\t\tset _CORELIST \"$_CORELIST $i\"\n\t\t}\n\t\tset _MASK [expr {$_MASK << 0x1}]\n\t}\n\n\tset _MASK 0x1\n\tfor {} {$i < $_MAX_CORE} {incr i} {\n\t\tif { [expr {$_COREMASK_HI & $_MASK}] != 0x0 } {\n\t\t\tset _CORELIST \"$_CORELIST $i\"\n\t\t}\n\t\tset _MASK [expr {$_MASK << 0x1}]\n\t}\n}\n\n#\n# Definition of target names\n#\nset _TARGETNAME_PMPRO pmpro\nset _TARGETNAME_SMPRO smpro\nset _TARGETNAME_ARMV8 armv8\n\n#\n# Configure JTAG TAPs - TAP chain declaration order is important\n#\n\njtag newtap $_CHIPNAME pmpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID\nset _TAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.tap\n\njtag newtap $_CHIPNAME smpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID\nset _TAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.tap\n\njtag newtap $_CHIPNAME armv8.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_ARMV8_TAPID\nset _TAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.tap\n\nset _DAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.dap\nset _DAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.dap\nset _DAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.dap\n\nset _AP_PMPRO_AHB 0\nset _AP_SMPRO_AHB 0\nset _AP_ARMV8_APB 0x00010000\nset _AP_ARMV8_AXI 0x00020000\n\n#\n# Configure JTAG DAPs\n#\n\ndap create $_DAPNAME_PMPRO -chain-position $_TAPNAME_PMPRO -adiv5\ndap create $_DAPNAME_SMPRO -chain-position $_TAPNAME_SMPRO -adiv5\ndap create $_DAPNAME_ARMV8 -chain-position $_TAPNAME_ARMV8 -adiv6\n\nif { [info exists LCS] && [expr {\"$LCS\"!=\"0\"}] } {\n\t#\n\t# Create the DAP AHB-AP MEM-AP target for the PMPRO CPU\n\t#\n\n\ttarget create $_CHIPNAME.$_TARGETNAME_PMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB\n\n\t#\n\t# Configure target PMPRO CPU\n\t#\n\n\ttarget create $_CHIPNAME.$_TARGETNAME_PMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB\n\n\t#\n\t# Create the DAP AHB-AP MEM-AP target for the SMPRO CPU\n\t#\n\n\ttarget create $_CHIPNAME.$_TARGETNAME_SMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB\n\n\t#\n\t# Configure target SMPRO CPU\n\t#\n\n\ttarget create $_CHIPNAME.$_TARGETNAME_SMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB\n}\n\n# Create the DAP APB-AP MEM-AP target for the ARMV8 cores\ntarget create $_CHIPNAME.$_TARGETNAME_ARMV8.apb mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB\n\n# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores\ntarget create $_CHIPNAME.$_TARGETNAME_ARMV8.axi mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_AXI\n\n# Set CSW register value default correctly for AXI accessible device memory:\n# Select the correct Access Port Number\n$_DAPNAME_ARMV8 apsel $_AP_ARMV8_AXI\n# First set the CSW to OpenOCD's internal default\n$_DAPNAME_ARMV8 apcsw default\n# Set Domain[1:0]=b'11  (CSW[14:13]=b'11)\n# Set Cache[3:0]=b'0000 (CSW[27:24]=b'0000)\n# Porter Cfg registers require secure access, AxPROT[1] (CSW[29]) must be b'0'.\n# Set AxPROT[2:0]=b'000 (CSW[30:28]=b'000) for an Unpriveleged, Secure, Data access.\n$_DAPNAME_ARMV8 apcsw 0x00006000 0x7F006000\n\n#\n# Configure target CPUs\n#\n\nset logical_index $_CORE_INDEX_OFFSET\n\nforeach physical_index $_CORELIST {\n\tif { [info exists PHYS_IDX] } {\n\t\tset logical_index [expr {$physical_index + $_CORE_INDEX_OFFSET}]\n\t}\n\n\t# Format a string to reference which CPU target to use\n\tif { [info exists SPLITSMP] } {\n\t\teval \"set _TARGETNAME $_CHIPNAME.${_TARGETNAME_ARMV8}_$logical_index\"\n\t} else {\n\t\teval \"set _TARGETNAME $_SYSNAME.${_TARGETNAME_ARMV8}_$logical_index\"\n\t}\n\n\t# Create and configure Cross Trigger Interface (CTI) - required for halt and resume\n\tset _CTINAME $_TARGETNAME.cti\n\tset _offset [expr {(0x00100000 * $physical_index) + (0x00200000 * ($physical_index>>1))}]\n\tcti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr {0xA0220000 + $_offset}]\n\n\t# Create the target\n\ttarget create $_TARGETNAME aarch64 -endian $_ENDIAN \\\n\t\t-dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr {0xA0210000 + $_offset}] \\\n\t\t-rtos hwthread -cti $_CTINAME -coreid $logical_index\n\n\t# Build string used to enable SMP mode for the ARMv8 CPU cores\n\tset _SMP_STR \"$_SMP_STR $_TARGETNAME\"\n\n\t# Clear CTI output/input enables that are not configured by OpenOCD for aarch64\n\t$_TARGETNAME configure -event reset-init [subst {\n\t\t$_CTINAME write INEN0 0x00000000\n\t\t$_CTINAME write INEN1 0x00000000\n\t\t$_CTINAME write INEN2 0x00000000\n\t\t$_CTINAME write INEN3 0x00000000\n\t\t$_CTINAME write INEN4 0x00000000\n\t\t$_CTINAME write INEN5 0x00000000\n\t\t$_CTINAME write INEN6 0x00000000\n\t\t$_CTINAME write INEN7 0x00000000\n\t\t$_CTINAME write INEN8 0x00000000\n\n\t\t$_CTINAME write OUTEN0 0x00000000\n\t\t$_CTINAME write OUTEN1 0x00000000\n\t\t$_CTINAME write OUTEN2 0x00000000\n\t\t$_CTINAME write OUTEN3 0x00000000\n\t\t$_CTINAME write OUTEN4 0x00000000\n\t\t$_CTINAME write OUTEN5 0x00000000\n\t\t$_CTINAME write OUTEN6 0x00000000\n\t\t$_CTINAME write OUTEN7 0x00000000\n\t\t$_CTINAME write OUTEN8 0x00000000\n\t}]\n\n\tincr logical_index\n}\n\nif { [info exists SMP_STR] } {\n\t# Return updated SMP configuration string back to board level\n\tset SMP_STR $_SMP_STR\n} else {\n\t# For single socket per SMP configuration, evaluate the string\n\teval $_SMP_STR\n}\n\nif { [info exists CORE_INDEX_OFFSET] } {\n\t# For multi-socket, return total number of cores back to board level\n\tset CORE_INDEX_OFFSET $logical_index\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ar71xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Atheros AR71xx MIPS 24Kc SoC.\n# tested on PB44 refererence board\n\nadapter srst delay 100\njtag_ntrst_delay 100\n\nreset_config trst_and_srst\n\nset CHIPNAME ar71xx\n\njtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1\n\nset _TARGETNAME $CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-halt-post {\n\t#setup PLL to lowest common denominator 300/300/150 setting\n\tmww 0xb8050000 0x000f40a3\t;# reset val + CPU:3 DDR:3 AHB:0\n\tmww 0xb8050000 0x800f40a3\t;# send to PLL\n\n\t#next command will reset for PLL changes to take effect\n\tmww 0xb8050008 3\t\t;# set reset_switch and clock_switch (resets SoC)\n}\n\n$_TARGETNAME configure -event reset-init {\n\t#complete pll initialization\n\tmww 0xb8050000 0x800f0080\t;# set sw_update bit\n\tmww 0xb8050008 0\t\t;# clear reset_switch bit\n\tmww 0xb8050000 0x800f00e8       ;# clr pwrdwn & bypass\n\tmww 0xb8050008 1\t\t;# set clock_switch bit\n\tsleep 1                         ;# wait for lock\n\n\t# Setup DDR config and flash mapping\n\tmww 0xb8000000 0xefbc8cd0       ;# DDR cfg cdl val (rst: 0x5bfc8d0)\n\tmww 0xb8000004 0x8e7156a2       ;# DDR cfg2 cdl val (rst: 0x80d106a8)\n\n\tmww 0xb8000010 8\t\t;# force precharge all banks\n\tmww 0xb8000010 1 \t\t;# force EMRS update cycle\n\tmww 0xb800000c 0                ;# clr ext. mode register\n\tmww 0xb8000010 2 \t\t;# force auto refresh all banks\n\tmww 0xb8000010 8\t\t;# force precharge all banks\n\tmww 0xb8000008 0x31             ;# set DDR mode value CAS=3\n\tmww 0xb8000010 1 \t\t;# force EMRS update cycle\n\tmww 0xb8000014 0x461b           ;# DDR refresh value\n\tmww 0xb8000018 0xffff           ;# DDR Read Data This Cycle value (16bit: 0xffff)\n\tmww 0xb800001c 0x7              ;# delay added to the DQS line (normal = 7)\n\tmww 0xb8000020 0\n\tmww 0xb8000024 0\n\tmww 0xb8000028 0\n}\n\n# setup working area somewhere in RAM\n$_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000\n\n# serial SPI capable flash\n# flash bank <driver> <base> <size> <chip_width> <bus_width>\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/arm_corelink_sse200.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs.\n#\n\nglobal TARGET\nset TARGET $_CHIPNAME\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n#\n# SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB\n# We will configure work area assuming 8-KB bank size in SRAM bank 1.\n# Also SRAM start addresses defaults to secure mode alias.\n# These values can be overridden as per board configuration\n#\n\nglobal _WORKAREASIZE_CPU0\nif { [info exists WORKAREASIZE_CPU0] } {\n\tset _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0\n} else {\n\tset _WORKAREASIZE_CPU0 0x1000\n}\n\nglobal _WORKAREAADDR_CPU0\nif { [info exists WORKAREAADDR_CPU0] } {\n\tset _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0\n} else {\n\tset _WORKAREAADDR_CPU0 0x30008000\n}\n\n#\n# Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200\n# Core 0 is the boot core and will always be configured.\n#\n\ntarget create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0\n\n${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0\n\n${TARGET}.CPU0 cortex_m reset_config sysresetreq\n\n#\n# Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200\n# Core 1 is optional and locked at boot until core 0 unlocks it.\n#\n\nif { $_ENABLE_CPU1 } {\n\tglobal _WORKAREASIZE_CPU1\n\tif { [info exists WORKAREASIZE_CPU1] } {\n\t\tset _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1\n\t} else {\n\t\tset _WORKAREASIZE_CPU1 0x1000\n\t}\n\n\tglobal _WORKAREAADDR_CPU1\n\tif { [info exists WORKAREAADDR_CPU1] } {\n\t\tset _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1\n\t} else {\n\t\tset _WORKAREAADDR_CPU1 0x30009000\n\t}\n\n\ttarget create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1\n\n\t${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0\n\n\t${TARGET}.CPU1 cortex_m reset_config vectreset\n}\n\n# Make sure the default target is the boot core\ntargets ${TARGET}.CPU0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/armada370.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# armada370 -- support for the Marvell Armada/370 CPU family\n#\n# gerg@uclinux.org, OCT-2013\n#\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME armada370\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap\n\nproc armada370_dbginit {target} {\n     cortex_a dbginit\n}\n\n$_TARGETNAME configure -event reset-assert-post \"armada370_dbginit $_TARGETNAME\"\n\ndap apsel 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at32ap7000.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Atmel AT32AP7000\n#\n# This is the only core in the now-inactive high end AVR32 product line,\n# with MMU, Java Acceleration, and \"pixel coprocessor\".  The AP7 line\n# is for \"Application Processors\" (AP) with 7-stage pipelines.\n#\n# Most current AVR32 parts are in the UC3 flash based microcontroller (UC)\n# product line with 3-stage pipelines and without those extras.\n#\n# All AVR32 parts provide the Nexus Class 3 on-chip debug interfaces\n# through their JTAG interfaces.\n\njtag newtap ap7 nexus -irlen 5 -expected-id 0x21e8203f\n\n# REVISIT declare an avr32 target ... needs OpenOCD infrastructure\n# for both Nexus (generic) and AVR32 (Atmel-specific).\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91r40008.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# AT91R40008 target configuration file\n\n# TRST is tied to SRST on the AT91X40 family.\nreset_config srst_only srst_pulls_trst\n\n\nif {[info exists CHIPNAME]} {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME at91r40008\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Setup the JTAG scan chain.\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x1f0f0f0f\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91rm9200.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Atmel AT91rm9200\n# http://atmel.com/products/at91/\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME at91rm9200\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x05b0203f\n}\n\n# Never allow the following!\nif { $_CPUTAPID == 0x15b0203f } {\n   echo \"-------------------------------------------------------\"\n   echo \"- ERROR:                                              -\"\n   echo \"- ERROR: TapID 0x15b0203f is wrong for at91rm9200     -\"\n   echo \"- ERROR: The chip/board has a JTAG select pin/jumper  -\"\n   echo \"- ERROR:                                              -\"\n   echo \"- ERROR: In one position (0x05b0203f) it selects the  -\"\n   echo \"- ERROR: ARM CPU, in the other position (0x1b0203f)   -\"\n   echo \"- ERROR: it selects boundary-scan not the ARM         -\"\n   echo \"- ERROR:                                              -\"\n   echo \"-------------------------------------------------------\"\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n# Create the GDB Target.\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# AT91RM9200 has a 16K block of sram @ 0x0020.0000\n$_TARGETNAME configure -work-area-phys 0x00200000 \\\n\t\t-work-area-size 0x4000 -work-area-backup 1\n\n# This chip has a DCC ... use it\narm7_9 dcc_downloads enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3XXX.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for ATMEL sam3, a Cortex-M3 chip\n#\n# at91sam3u4e\n# at91sam3u2e\n# at91sam3u1e\n# at91sam3u4c\n# at91sam3u2c\n# at91sam3u1c\n#\n# at91sam3s4c\n# at91sam3s4b\n# at91sam3s4a\n# at91sam3s2c\n# at91sam3s2b\n# at91sam3s2a\n# at91sam3s1c\n# at91sam3s1b\n# at91sam3s1a\n#\n# at91sam3A4C\n# at91sam3A8C\n# at91sam3X4C\n# at91sam3X4E\n# at91sam3X8C\n# at91sam3X8E\n# at91sam3X8H\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME sam3\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 64kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x4ba00477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n# 16K is plenty, the smallest chip has this much\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n$_TARGETNAME configure -event gdb-flash-erase-start {\n    halt\n}\n\n# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz\n#\n# Since we may be running of an RC oscilator, we crank down the speed a\n# bit more to be on the safe side. Perhaps superstition, but if are\n# running off a crystal, we can run closer to the limit. Note\n# that there can be a pretty wide band where things are more or less stable.\n\nadapter speed 500\n\nadapter srst delay 100\nif {[using_jtag]} {\n   jtag_ntrst_delay 100\n}\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3ax_4x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# common stuff\nsource [find target/at91sam3ax_xx.cfg]\n\n# size is automatically \"calculated\" by probing\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME\n# This is a 256K chip - it has the 2nd bank\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME at91sam3 0x0000A0000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3ax_8x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# common stuff\nsource [find target/at91sam3ax_xx.cfg]\n\n# size is automatically \"calculated\" by probing\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME\n# This is a 512K chip - it has the 2nd bank\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3ax_xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for ATMEL sam3, a Cortex-M3 chip\n#\n# at91sam3A4C\n# at91sam3A8C\n# at91sam3X4C\n# at91sam3X4E\n# at91sam3X8C\n# at91sam3X8E\n# at91sam3X8H\nsource [find target/at91sam3XXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3nXX.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Configuration for Atmel's SAM3N series\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME at91sam3n\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x4ba00477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3sXX.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for ATMEL sam3, a Cortex-M3 chip\n#\n# at91sam3s4c\n# at91sam3s4b\n# at91sam3s4a\n# at91sam3s2c\n# at91sam3s2b\n# at91sam3s2a\n# at91sam3s1c\n# at91sam3s1b\n# at91sam3s1a\n\nsource [find target/at91sam3XXX.cfg]\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam3 0x00400000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3u1c.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# common stuff\nsource [find target/at91sam3uxx.cfg]\n\n# size is automatically \"calculated\" by probing\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3u1e.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# common stuff\nsource [find target/at91sam3uxx.cfg]\n\n# size is automatically \"calculated\" by probing\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3u2c.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# common stuff\nsource [find target/at91sam3uxx.cfg]\n\n# size is automatically \"calculated\" by probing\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3u2e.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# common stuff\nsource [find target/at91sam3uxx.cfg]\n\n# size is automatically \"calculated\" by probing\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3u4c.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# common stuff\nsource [find target/at91sam3uxx.cfg]\n\n# size is automatically \"calculated\" by probing\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME\n# This is a 256K chip, it has the 2nd bank\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3u4e.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# common stuff\nsource [find target/at91sam3uxx.cfg]\n\n# size is automatically \"calculated\" by probing\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME\n# This is a 256K chip - it has the 2nd bank\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam3uxx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for ATMEL sam3, a Cortex-M3 chip\n#\n# at91sam3u4e\n# at91sam3u2e\n# at91sam3u1e\n# at91sam3u4c\n# at91sam3u2c\n# at91sam3u1c\n\nsource [find target/at91sam3XXX.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam4XXX.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# script for ATMEL sam4, a Cortex-M4 chip\n#\n\n#\n# sam4 devices can support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME sam4\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 64kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x4ba00477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n# 16K is plenty, the smallest chip has this much\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz\n#\n# Since we may be running of an RC oscilator, we crank down the speed a\n# bit more to be on the safe side. Perhaps superstition, but if are\n# running off a crystal, we can run closer to the limit. Note\n# that there can be a pretty wide band where things are more or less stable.\n\nadapter speed 500\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam4c32x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for ATMEL sam4c32, a Cortex-M4 chip\n#\n\nsource [find target/at91sam4XXX.cfg]\n\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME at91sam4 0x01100000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam4cXXX.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for ATMEL sam4c, a Cortex-M4 chip\n#\n\nsource [find target/at91sam4XXX.cfg]\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam4lXX.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for ATMEL sam4l, a Cortex-M4 chip\n#\n\nsource [find target/at91sam4XXX.cfg]\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME\n\n# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N\n# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3).\n#\n# smap_reset_deassert configures whether we want to run or halt out of reset,\n# then instruct the SMAP to let us out of reset.\n$_TARGETNAME configure -event reset-deassert-post \"at91sam4l smap_reset_deassert\"\n\n# SRST (wired to RESET_N) resets debug circuitry\n# srst_pulls_trst is not configured here to avoid an error raised in reset halt\nreset_config srst_gates_jtag\n\n# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed.\n# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.\n# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2\n# but your mileage may vary.\nadapter speed 50\n\n# System RC oscillator RCSYS starts in 3 cycles\nadapter srst delay 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam4sXX.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for ATMEL sam4, a Cortex-M4 chip\n#\n\nsource [find target/at91sam4XXX.cfg]\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam4sd32x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for ATMEL sam4sd32, a Cortex-M4 chip\n#\n\nsource [find target/at91sam4XXX.cfg]\n\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME at91sam4 0x00500000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam7a2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME at91sam7a2\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x1f0f0f0f\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\nset _TARGETNAME $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam7se512.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# ATMEL sam7se512\n# Example: the \"Elektor Internet Radio\" - EIR\n# http://www.ethernut.de/en/hardware/eir/index.html\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME sam7se512\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   # Force an error until we get a good number.\n   set _CPUTAPID 0xffffffff\n}\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config srst_only srst_pulls_trst\n\n#jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n# The target\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0\n\n#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam7sx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config srst_only srst_pulls_trst\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME at91sam7s\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x3f0f0f0f\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n$_TARGETNAME configure -event reset-init {\n        soft_reset_halt\n        # RSTC_CR : Reset peripherals\n        mww 0xfffffd00 0xa5000004\n        # disable watchdog\n\tmww 0xfffffd44 0x00008000\n\t# enable user reset\n\tmww 0xfffffd08 0xa5000001\n\t# CKGR_MOR : enable the main oscillator\n\tmww 0xfffffc20 0x00000601\n\tsleep 10\n\t# CKGR_PLLR: 96.1097 MHz\n\tmww 0xfffffc2c 0x00481c0e\n\tsleep 10\n\t# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz\n\tmww 0xfffffc30 0x00000007\n\tsleep 10\n\t# MC_FMR: flash mode (FWS=1,FMCN=73)\n\tmww 0xffffff60 0x00490100\n\tsleep 100\n}\n\n$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0\n\n#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam7x256.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config srst_only srst_pulls_trst\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME sam7x256\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x3f0f0f0f\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-init {\n\t# disable watchdog\n\tmww 0xfffffd44 0x00008000\n\t# enable user reset\n\tmww 0xfffffd08 0xa5000001\n\t# CKGR_MOR : enable the main oscillator\n\tmww 0xfffffc20 0x00000601\n\tsleep 10\n\t# CKGR_PLLR: 96.1097 MHz\n\tmww 0xfffffc2c 0x00481c0e\n\tsleep 10\n\t# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz\n\tmww 0xfffffc30 0x00000007\n\tsleep 10\n\t# MC_FMR: flash mode (FWS=1,FMCN=60)\n\tmww 0xffffff60 0x003c0100\n\tsleep 100\n}\n\n$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0\n\n#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam7x512.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config srst_only srst_pulls_trst\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME sam7x512\n}\n\nif { [info exists ENDIAN] } {\n   set  _ENDIAN $ENDIAN\n} else {\n   set  _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x3f0f0f0f\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-init {\n\t# disable watchdog\n\tmww 0xfffffd44 0x00008000\n\t# enable user reset\n\tmww 0xfffffd08 0xa5000001\n\t# CKGR_MOR : enable the main oscillator\n\tmww 0xfffffc20 0x00000601\n\tsleep 10\n\t# CKGR_PLLR: 96.1097 MHz\n\tmww 0xfffffc2c 0x00481c0e\n\tsleep 10\n\t# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz\n\tmww 0xfffffc30 0x00000007\n\tsleep 10\n\t# MC_FMR: flash mode (FWS=1,FMCN=60)\n\tmww 0xffffff60 0x003c0100\n\tsleep 100\n}\n\n$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0\n\n#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME.0 at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432\nflash bank $_FLASHNAME.1 at91sam7 0 0 0 0 $_TARGETNAME 1 0 0 0 0 0 0 18432\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam9.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Atmel AT91SAM9\n######################################\n\nif { [info exists AT91_CHIPNAME] } {\n\tset _CHIPNAME $AT91_CHIPNAME\n} else {\n\terror \"you must specify a chip name\"\n}\n\nif { [info exists ENDIAN] } {\n\tset _ENDIAN $ENDIAN\n} else {\n\tset _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x0792603f\n}\n\nreset_config trst_and_srst separate trst_push_pull srst_open_drain\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nadapter srst delay 300\njtag_ntrst_delay 200\n\nadapter speed 3\n\n######################\n# Target configuration\n######################\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam9260.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Atmel AT91SAM9260\n######################################\n\nif { [info exists CHIPNAME] } {\n\tset AT91_CHIPNAME $CHIPNAME\n} else {\n\tset AT91_CHIPNAME at91sam9260\n}\n\nsource [find target/at91sam9.cfg]\n\n\n# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The\n# AT91SAM9260 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.\n# Both areas are 4 kB long.\n\n#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x1000 -work-area-backup 1\n$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Atmel AT91SAM9260\n######################################\n\nsource [find target/at91sam9261.cfg]\n\nreset_config trst_and_srst\n\nadapter speed 4\n\nadapter srst delay 200\njtag_ntrst_delay 200\n\nscan_chain\n$_TARGETNAME configure -event reset-start {\n\t# at reset chip runs at 32khz\n\tadapter speed 8\n}\n\n$_TARGETNAME configure -event reset-init {at91sam_init}\n\n# Flash configuration\n#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME\n\n# Faster memory downloads. This is disabled automatically during\n# reset init since all reset init sequences are too short for\n# fast memory access\narm7_9 dcc_downloads enable\narm7_9 fast_memory_access enable\n\nproc at91sam_init { } {\n\tmww 0xfffffd08 0xa5000501         ;# RSTC_MR : enable user reset\n\tmww 0xfffffd44 0x00008000         ;# WDT_MR : disable watchdog\n\n\tmww 0xfffffc20 0x00004001         ;# CKGR_MOR : enable the main oscillator\n\tsleep 20                          ;# wait 20 ms\n\tmww 0xfffffc30 0x00000001         ;# PMC_MCKR : switch to main oscillator\n\tsleep 10                          ;# wait 10 ms\n\tmww 0xfffffc28 0x2060bf09         ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz\n\tsleep 20                          ;# wait 20 ms\n\tmww 0xfffffc30 0x00000101         ;# PMC_MCKR : Select prescaler\n\tsleep 10                          ;# wait 10 ms\n\tmww 0xfffffc30 0x00000102         ;# PMC_MCKR : Clock from PLLA is selected\n\tsleep 10                          ;# wait 10 ms\n\n\t# Now run at anything fast... ie: 10mhz!\n\tadapter speed 10000               ;# Increase JTAG Speed to 6 MHz\n\n\tmww 0xffffec00 0x0a0a0a0a         ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit\n\tmww 0xffffec04 0x0b0b0b0b         ;# SMC_PULSE0\n\tmww 0xffffec08 0x00160016         ;# SMC_CYCLE0\n\tmww 0xffffec0c 0x00161003         ;# SMC_MODE0\n\n\tmww 0xfffff870 0xffff0000         ;# PIO_ASR : Select peripheral function for D15..D31\n\tmww 0xfffff804 0xffff0000         ;# PIO_PDR : Disable PIO function for D15..D31\n\n\tmww 0xffffef1c 0x2                ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM\n\n\tmww 0xffffea08 0x85227259         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)\n\t#mww 0xffffea08 0x85227254         ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)\n\n\tmww 0xffffea00 0x1                ;# SDRAMC_MR : issue a NOP command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x2                ;# SDRAMC_MR : issue an 'All Banks Precharge' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4                ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x4\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x3                ;# SDRAMC_MR : issue a 'Load Mode Register' command\n\tmww 0x20000000 0\n\tmww 0xffffea00 0x0                ;# SDRAMC_MR : normal mode\n\tmww 0x20000000 0\n\tmww 0xffffea04 0x5d2              ;# SDRAMC_TR : Set refresh timer count to 15us\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam9261.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Atmel AT91SAM9261\n######################################\n\nif { [info exists CHIPNAME] } {\n\tset AT91_CHIPNAME $CHIPNAME\n} else {\n\tset AT91_CHIPNAME at91sam9261\n}\n\nsource [find target/at91sam9.cfg]\n\n# Internal sram1 memory\n$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x28000 -work-area-backup 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam9263.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Atmel AT91SAM9263\n######################################\n\nif { [info exists CHIPNAME] } {\n\tset AT91_CHIPNAME $CHIPNAME\n} else {\n\tset AT91_CHIPNAME at91sam9263\n}\n\nsource [find target/at91sam9.cfg]\n\n# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The\n# AT91SAM9263 has two SRAM areas,\n# one starting at 0x00300000 of 80KiB\n# and the other  starting at 0x00500000 of 16KiB.\n\n# Internal sram1 memory\n$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x14000 -work-area-backup 1\n#$_TARGETNAME configure -work-area-phys 0x00500000 -work-area-size 0x4000 -work-area-backup 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam9g10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Atmel AT91SAM9G10\n######################################\n\nif { [info exists CHIPNAME] } {\n\tset AT91_CHIPNAME $CHIPNAME\n} else {\n\tset AT91_CHIPNAME at91sam9g10\n}\n\nsource [find target/at91sam9.cfg]\n\n# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The\n# AT91SAM9G10 has one SRAM area at 0x00300000 of 16KiB\n\n$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam9g20.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Atmel AT91SAM9G20\n######################################\n\nif { [info exists CHIPNAME] } {\n\tset AT91_CHIPNAME $CHIPNAME\n} else {\n\tset AT91_CHIPNAME at91sam9g20\n}\n\nsource [find target/at91sam9.cfg]\n\n# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).\n\nadapter speed 5\n\n# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The\n# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.\n# Both areas are 16 kB long.\n\n#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1\n$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam9g45.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Atmel AT91SAM9G45\n######################################\n\nif { [info exists CHIPNAME] } {\n\tset AT91_CHIPNAME $CHIPNAME\n} else {\n\tset AT91_CHIPNAME at91sam9g45\n}\n\nsource [find target/at91sam9.cfg]\n\n# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The\n# AT91SAM9G45 has one SRAM area starting at 0x00300000 of 64 KiB.\n\n$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x200000 -work-area-backup 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sam9rl.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Atmel AT91SAM9RL\n######################################\n\nif { [info exists CHIPNAME] } {\n   set AT91_CHIPNAME $CHIPNAME\n} else {\n   set AT91_CHIPNAME at91sam9rl\n}\n\nsource [find target/at91sam9.cfg]\n\n# Internal sram1 memory\n$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x10000 -work-area-backup 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91sama5d2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# The JTAG connection is disabled at reset, and during the ROM Code execution.\n# It is re-enabled when the ROM code jumps in the boot file copied from an\n# external Flash memory into the internalSRAM, or when the ROM code launches\n# the SAM-BA monitor, when no boot file has been found in any external Flash\n# memory.\n# For more JTAG related information see, :\n# https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-sheet-ds60001476G.pdf\n#\n# If JTAGSEL pin:\n# - if enabled, boundary Scan mode is activated. JTAG ID Code value is 0x05B3F03F.\n# - if disabled, ICE mode is activated. Debug Port JTAG IDCODE value is 0x5BA00477\n#\nif { [info exists CHIPNAME] } {\n\tset  _CHIPNAME $CHIPNAME\n} else {\n\tset  _CHIPNAME at91sama5d2\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n\t-expected-id 0x5ba00477\n\n# Cortex-A5 target\nset _TARGETNAME $_CHIPNAME.cpu_a5\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91samdXX.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip\n#\n\n#\n# samdXX devices only support SWD transports.\n#\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME at91samd\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 2kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x800\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x4ba00477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# SAMD DSU will hold the CPU in reset if TCK is low when RESET_N\n# deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2)\n#\n# dsu_reset_deassert configures whether we want to run or halt out of reset,\n# then instruct the DSU to let us out of reset.\n$_TARGETNAME configure -event reset-deassert-post {\n        at91samd dsu_reset_deassert\n}\n\n# SRST (wired to RESET_N) resets debug circuitry\n# srst_pulls_trst is not configured here to avoid an error raised in reset halt\nreset_config srst_gates_jtag\n\n# Do not use a reset button with other SWD adapter than Atmel's EDBG.\n# DSU usually locks MCU in reset state until you issue a reset command\n# in OpenOCD.\n\n# SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset.\n# Other members of family usually use SYSCLK = 4 MHz after reset.\n# Datasheet does not specify SYSCLK to SWD clock ratio.\n# Usually used SYSCLK/6 is slow, testing shows that debugging can\n# work @ SYSCLK/2 but your mileage may vary.\n# This limit is most probably imposed by incorrectly handled SWD WAIT\n# on some SWD adapters.\n\nadapter speed 400\n\n# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works\n# without problem at maximal clock speed. Atmel recommends\n# adapter speed less than 10 * CPU clock.\n# adapter speed 5000\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/at91samg5x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for the ATMEL samg5x Cortex-M4F chip family\n#\n\nsource [find target/at91sam4XXX.cfg]\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atheros_ar2313.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME ar2313\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x00000001\n}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atheros_ar2315.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME ar2315\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x00000001\n}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atheros_ar9331.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The Atheros AR9331 is a highly integrated and cost effective\n# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless\n# local area network (WLAN) AP and router platforms.\n#\n# Notes:\n# - MIPS Processor ID (PRId): 0x00019374\n# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,\n#   operating at up to 400 MHz\n# - External 16-bit DDR1, DDR2, or SDRAM memory interface\n# - TRST is not available.\n# - EJTAG PrRst signal is not supported\n# - RESET_L pin A72 on the SoC will reset internal JTAG logic.\n#\n\n# Pins related for debug and bootstrap:\n# Name\t\tPin\t\tDescription\n#   JTAG\n# JTAG_TCK\tGPIO0, (A27)\tSoftware configurable, default JTAG\n# JTAG_TDI\tGPIO6, (B46)\tSoftware configurable, default JTAG\n# JTAG_TDO\tGPIO7, (A54)\tSoftware configurable, default JTAG\n# JTAG_TMS\tGPIO8, (A52)\tSoftware configurable, default JTAG\n#   Reset\n# RESET_L\t-, (A72)\tInput only\n# SYS_RST_L\t????????\tOutput reset request or GPIO\n#   Bootstrap\n# MEM_TYPE[1]\tGPIO28, (A74)\t0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM\n# MEM_TYPE[0]\tGPIO12, (A56)\n# FW_DOWNLOAD\tGPIO16, (A75)\tUsed if BOOT_FROM_SPI = 0. 0 - boot from USB\n#                               1 - boot from MDIO.\n# JTAG_MODE(JS)\tGPIO11, (B48)\t0 - JTAG (Default); 1 - EJTAG\n# BOOT_FROM_SPI\tGPIO1, (A77)\t0 - ROM boot; 1 - SPI boot\n# SEL_25M_40M\tGPIO0, (A78)\t0 - 25MHz; 1 - 40MHz\n#   UART\n# UART0_SOUT\tGPIO10, (A79)\n# UART0_SIN\tGPIO9, (B68)\n\n# Per default we need to use \"none\" variant to be able properly \"reset init\"\n# or \"reset halt\" the CPU.\nreset_config none srst_pulls_trst\n\n# For SRST based variant we still need proper timings.\n# For ETH part the reset should be asserted at least for 10ms\n# Since there is no other information let's take 100ms to be sure.\nadapter srst pulse_width 100\n\n# according to the SoC documentation it should take at least 5ms from\n# reset end till bootstrap end. In the practice we need 8ms to get JTAG back\n# to live.\nadapter srst delay 8\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME ar9331\n}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME\n\n# provide watchdog helper.\nproc disable_watchdog { } {\n\tmww 0xb8060008 0x0\n}\n\n$_TARGETNAME configure -event halted { disable_watchdog }\n\n# Since PrRst is not supported and SRST will reset complete chip\n# with JTAG engine, we need to reset CPU from CPU itself.\n$_TARGETNAME configure -event reset-assert-pre {\n\thalt\n}\n\n$_TARGETNAME configure -event reset-assert {\n\tcatch \"mww 0xb806001C 0x01000000\"\n}\n\n# To be able to trigger complete chip reset, in case JTAG is blocked\n# or CPU not responding, we still can use this helper.\nproc full_reset { } {\n\treset_config srst_only\n\treset\n\thalt\n\treset_config none\n}\n\nproc disable_watchdog { } {\n\t;# disable watchdog\n\tmww 0xb8060008 0x0\n}\n\n$_TARGETNAME configure -event reset-end { disable_watchdog }\n\n# Section with helpers which can be used by boards\nproc ar9331_25mhz_pll_init {} {\n\tmww 0xb8050008 0x00018004\t;# bypass PLL; AHB_POST_DIV - ratio 4\n\tmww 0xb8050004 0x00000352\t;# 34000(ns)/40ns(25MHz) = 0x352 (850)\n\tmww 0xb8050000 0x40818000\t;# Power down control for CPU PLL\n\t\t\t\t\t;# OUTDIV | REFDIV | DIV_INT\n\tmww 0xb8050010 0x001003e8\t;# CPU PLL Dither FRAC Register\n\t\t\t\t\t;# (disabled?)\n\tmww 0xb8050000 0x00818000\t;# Power on | OUTDIV | REFDIV | DIV_INT\n\tmww 0xb8050008 0x00008000\t;# remove bypass;\n\t\t\t\t\t;# AHB_POST_DIV - ratio 2\n}\n\nproc ar9331_ddr1_init {} {\n\tmww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs\n\tmww 0xb8000004 0x9dd0e6a8\t;# DDR_CONFIG2 - more DRAM confs\n\n\tmww 0xb8000010 0x8\t;# Forces a PRECHARGE ALL cycle\n\tmww 0xb8000008 0x133\t;# mode reg: 0x133 - default\n\tmww 0xb8000010 0x1\t;# Forces an MRS update cycl\n\tmww 0xb800000c 0x2\t;# Extended mode register value.\n\t\t\t\t;# default 0x2 - Reset to weak driver, DLL on\n\tmww 0xb8000010 0x2\t;# Forces an EMRS update cycle\n\tmww 0xb8000010 0x8\t;# Forces a PRECHARGE ALL cycle\n\tmww 0xb8000008 0x33\t;# mode reg: remove some bit?\n\tmww 0xb8000010 0x1\t;# Forces an MRS update cycl\n\tmww 0xb8000014 0x4186\t;# enable refres: bit(14) - set refresh rate\n\tmww 0xb800001c 0x8\t;# This register is used along with DQ Lane 0,\n\t\t\t\t;# DQ[7:0], DQS_0\n\tmww 0xb8000020 0x9\t;# This register is used along with DQ Lane 1,\n\t\t\t\t;# DQ[15:8], DQS_1.\n\tmww 0xb8000018 0xff\t;# DDR read and capture bit mask.\n\t\t\t\t;# Each bit represents a cycle of valid data.\n}\n\nproc ar9331_ddr2_init {} {\n\tmww 0xb8000000 0x7fbc8cd0\t;# DDR_CONFIG - lots of DRAM confs\n\tmww 0xb8000004 0x9dd0e6a8\t;# DDR_CONFIG2 - more DRAM confs\n\n\tmww 0xb800008c 0x00000a59\n\tmww 0xb8000010 0x00000008\t;# PRECHARGE ALL cycle\n\n\tmww 0xb8000090 0x00000000\n\tmww 0xb8000010 0x00000010\t;# EMR2S update cycle\n\n\tmww 0xb8000094 0x00000000\n\tmww 0xb8000010 0x00000020\t;# EMR3S update cycle\n\n\tmww 0xb800000c 0x00000000\n\tmww 0xb8000010 0x00000002\t;# EMRS update cycle\n\n\tmww 0xb8000008 0x00000100\n\tmww 0xb8000010 0x00000001\t;# MRS update cycle\n\n\tmww 0xb8000010 0x00000008\t;# PRECHARGE ALL cycle\n\n\tmww 0xb8000010 0x00000004\n\tmww 0xb8000010 0x00000004\t;# AUTO REFRESH cycle\n\n\tmww 0xb8000008 0x00000a33\n\tmww 0xb8000010 0x00000001\t;# MRS update cycle\n\n\tmww 0xb800000c 0x00000382\n\tmww 0xb8000010 0x00000002\t;# EMRS update cycle\n\n\tmww 0xb800000c 0x00000402\n\tmww 0xb8000010 0x00000002\t;# EMRS update cycle\n\n\tmww 0xb8000014 0x00004186\t;# DDR_REFRESH\n\tmww 0xb800001c 0x00000008\t;# DDR_TAP_CTRL0\n\tmww 0xb8000020 0x00000009\t;# DDR_TAP_CTRL1\n\n\t;# DDR read and capture bit mask.\n\t;# Each bit represents a cycle of valid data.\n\t;# 0xff: use 16-bit DDR\n\tmww 0xb8000018 0x000000ff\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atheros_ar9344.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME ar9344\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x00000001\n}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME\n\nproc test_ar9344_uart0_tx {} {\n\techo \"configuring uart0..\"\n\tmww 0xb802000c 0x87\n\tmww 0xb8020000 0x15\n\tmww 0xb8020004 0\n\tmww 0xb802000c 7\n\tmww 0xb8020004 0\n\n\techo \"send message: hallo world\"\n\tmww 0xb8020000 0x68\n\tmww 0xb8020000 0x65\n\tmww 0xb8020000 0x6c\n\tmww 0xb8020000 0x6c\n\tmww 0xb8020000 0x6f\n\tmww 0xb8020000 0x20\n\tmww 0xb8020000 0x77\n\tmww 0xb8020000 0x6f\n\tmww 0xb8020000 0x72\n\tmww 0xb8020000 0x6c\n\tmww 0xb8020000 0x64\n\tmww 0xb8020000 0x0a\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atmega128.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# for avr\n\n   set _CHIPNAME avr\n   set _ENDIAN little\n\n# jtag speed\nadapter speed 4500\n\nreset_config srst_only\nadapter srst delay 100\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x8970203F\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME\n\n#$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME\n\n#to use it, script will be like:\n#init\n#adapter speed 4500\n#reset init\n#verify_ircapture disable\n#\n#halt\n#wait halt\n#poll\n#avr mass_erase 0\n#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex\n#reset run\n#shutdown\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atmega128rfa1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset _CHIPNAME avr\nset _ENDIAN little\n\n# jtag speed\nadapter speed 4500\n\n# avr jtag docs never connect RSTN\nreset_config none\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x0a70103f\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atmega32u4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# ATmega32U4\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME avr\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x4958703f\n}\n\nadapter speed 4500\n\njtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atsame5x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Microchip (former Atmel) SAM E54, E53, E51 and D51 devices\n# with a Cortex-M4 core\n#\n\n#\n# Devices only support SWD transports.\n#\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME atsame5\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 32kB (the smallest RAM size is 128kB)\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x8000\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x4ba00477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# SAM DSU will hold the CPU in reset if TCK is low when RESET_N\n# deasserts\n#\n# dsu_reset_deassert configures whether we want to run or halt out of reset,\n# then instruct the DSU to let us out of reset.\n$_TARGETNAME configure -event reset-deassert-post {\n        atsame5 dsu_reset_deassert\n}\n\n# SRST (wired to RESET_N) resets debug circuitry\n# srst_pulls_trst is not configured here to avoid an error raised in reset halt\nreset_config srst_gates_jtag\n\n# Do not use a reset button with other SWD adapter than Atmel's EDBG.\n# DSU usually locks MCU in reset state until you issue a reset command\n# in OpenOCD.\n\n# SAM E5x/D51 runs at SYSCLK = 48 MHz from RC oscillator after reset.\n# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works\n# without problem at clock speed over 5000 khz. Atmel recommends\n# adapter speed less than 10 * CPU clock.\nadapter speed 2000\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atsaml1x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Microchip (formerly Atmel) SAM L1x target\n#\n# Note: These devices support SWD only.\n#\n\ntransport select swd\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME saml1x\n}\n\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x800\n}\n\nswd newdap $_CHIPNAME cpu -expected-id 0x0bf11477\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nif {![using_hla]} {\n    cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/atsamv.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts\n# The chips are very similar; the SAMV series just has\n# more peripherals and seems like the \"flagship\" of the\n# family. This script will work for all of them.\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME samv\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 16kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x0bd11477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nadapter speed 1800\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n\n   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal\n   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3\n   # makes the data access cacheable. This allows reading and writing data in the\n   # CPU cache from the debugger, which is far more useful than going straight to\n   # RAM when operating on typical variables, and is generally no worse when\n   # operating on special memory locations.\n   $_CHIPNAME.dap apcsw 0x08000000 0x08000000\n}\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/avr32.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset _CHIPNAME avr32\nset _ENDIAN big\n\nset _CPUTAPID 0x21e8203f\n\nadapter srst delay 100\njtag_ntrst_delay 100\n\nreset_config trst_and_srst separate\n\n# jtag scan chain\n# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID\n\nset _TARGETNAME [format \"%s.cpu\" $_CHIPNAME]\ntarget create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm2711.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The Broadcom BCM2711 used in Raspberry Pi 4\n# No documentation was found on Broadcom website\n\n# Partial information is available in raspberry pi website:\n# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/\n\nif { [info exists CHIPNAME] } {\n\tset  _CHIPNAME $CHIPNAME\n} else {\n\tset  _CHIPNAME bcm2711\n}\n\nif { [info exists CHIPCORES] } {\n\tset _cores $CHIPCORES\n} else {\n\tset _cores 4\n}\n\nif { [info exists USE_SMP] } {\n\tset _USE_SMP $USE_SMP\n} else {\n\tset _USE_SMP 0\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4\nadapter speed 4000\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# MEM-AP for direct access\ntarget create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0\n\n# these addresses are obtained from the ROM table via 'dap info 0' command\nset _DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}\nset _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}\n\nset _smp_command \"target smp\"\n\nfor { set _core 0 } { $_core < $_cores } { incr _core } {\n\tset _CTINAME $_CHIPNAME.cti$_core\n\tset _TARGETNAME $_CHIPNAME.cpu$_core\n\n\tcti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 0 -baseaddr [lindex $_CTIBASE $_core]\n\ttarget create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME\n\n\tset _smp_command \"$_smp_command $_TARGETNAME\"\n}\n\nif {$_USE_SMP} {\n\teval $_smp_command\n}\n\n# default target is cpu0\ntargets $_CHIPNAME.cpu0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm281xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# BCM281xx\n\nif { [info exists CHIPNAME] } {\n\tset  _CHIPNAME $CHIPNAME\n} else {\n\tset  _CHIPNAME bcm281xx\n}\n\n\n# Main CPU DAP\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4\n\n\n# Dual Cortex-A9\nset _TARGETNAME0 $_CHIPNAME.cpu0\nset _TARGETNAME1 $_CHIPNAME.cpu1\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000\ntarget create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000\ntarget smp $_TARGETNAME0 $_TARGETNAME1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm2835.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is the Broadcom chip used in the Raspberry Pi Model A, B, B+,\n# the Compute Module, and the Raspberry Pi Zero.\n\n# Partial information is available in raspberry pi website:\n# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2835\n\nif { [info exists CHIPNAME] } {\n\tset  _CHIPNAME $CHIPNAME\n} else {\n\tset  _CHIPNAME bcm2835\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x07b7617F\n}\n\njtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 5\nadapter speed 4000\n\ntarget create $_CHIPNAME.cpu0 arm11 -chain-position $_CHIPNAME.cpu\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm2836.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The Broadcom chip used in the Raspberry Pi 2 Model B\n\n# Partial information is available in raspberry pi website:\n# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836\n\nif { [info exists CHIPNAME] } {\n\tset  _CHIPNAME $CHIPNAME\n} else {\n\tset  _CHIPNAME bcm2836\n}\n\nif { [info exists CHIPCORES] } {\n\tset _cores $CHIPCORES\n} else {\n\tset _cores 4\n}\n\nif { [info exists USE_SMP] } {\n\tset _USE_SMP $USE_SMP\n} else {\n\tset _USE_SMP 0\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4\nadapter speed 4000\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# MEM-AP for direct access\ntarget create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0\n\n# these addresses are obtained from the ROM table via 'dap info 0' command\nset _DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000}\n\nset _smp_command \"target smp\"\n\nfor { set _core 0 } { $_core < $_cores } { incr _core } {\n\tset _TARGETNAME $_CHIPNAME.cpu$_core\n\n\ttarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -coreid $_core -dbgbase [lindex $_DBGBASE $_core]\n\t$_TARGETNAME configure -event reset-assert-post { cortex_a dbginit }\n\n\tset _smp_command \"$_smp_command $_CHIPNAME.cpu$_core\"\n}\n\nif {$_USE_SMP} {\n\teval $_smp_command\n}\n\n# default target is cpu0\ntargets $_CHIPNAME.cpu0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm2837.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This is the Broadcom chip used in the Raspberry Pi 3,\n# and in later models of the Raspberry Pi 2.\n\n# Partial information is available in raspberry pi website:\n# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837\n# https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2837b0\n\nif { [info exists CHIPNAME] } {\n\tset  _CHIPNAME $CHIPNAME\n} else {\n\tset  _CHIPNAME bcm2837\n}\n\nif { [info exists CHIPCORES] } {\n\tset _cores $CHIPCORES\n} else {\n\tset _cores 4\n}\n\nif { [info exists USE_SMP] } {\n\tset _USE_SMP $USE_SMP\n} else {\n\tset _USE_SMP 0\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4\nadapter speed 4000\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# MEM-AP for direct access\ntarget create $_CHIPNAME.ap mem_ap -dap $_CHIPNAME.dap -ap-num 0\n\n# these addresses are obtained from the ROM table via 'dap info 0' command\nset _DBGBASE {0x80010000 0x80012000 0x80014000 0x80016000}\nset _CTIBASE {0x80018000 0x80019000 0x8001a000 0x8001b000}\n\nset _smp_command \"target smp\"\n\nfor { set _core 0 } { $_core < $_cores } { incr _core } {\n\tset _CTINAME $_CHIPNAME.cti$_core\n\tset _TARGETNAME $_CHIPNAME.cpu$_core\n\n\tcti create $_CTINAME -dap $_CHIPNAME.dap -ap-num 0 -baseaddr [lindex $_CTIBASE $_core]\n\ttarget create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase [lindex $_DBGBASE $_core] -cti $_CTINAME\n\t$_TARGETNAME configure -event reset-assert-post { aarch64  dbginit }\n\n\tset _smp_command \"$_smp_command $_TARGETNAME\"\n}\n\nif {$_USE_SMP} {\n\teval $_smp_command\n}\n\n# default target is cpu0\ntargets $_CHIPNAME.cpu0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm4706.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset _CHIPNAME bcm4706\nset _CPUID 0x1008c17f\n\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm4718.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset _CHIPNAME bcm4718\nset _LVTAPID 0x1471617f\nset _CPUID 0x0008c17f\n\nsource [find target/bcm47xx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm47xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho \"Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed\"\nreset_config none\n\njtag newtap $_CHIPNAME-lv tap -irlen 32 -ircapture 0x1 -irmask 0x1f -expected-id $_LVTAPID -expected-id $_CPUID\njtag configure $_CHIPNAME-lv.tap -event setup \"jtag tapenable $_CHIPNAME.cpu\"\njtag configure $_CHIPNAME-lv.tap -event tap-disable {}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID -disable\njtag configure $_CHIPNAME.cpu -event tap-enable \"switch_lv_to_ejtag\"\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME\n\nproc switch_lv_to_ejtag {} {\n    global _CHIPNAME\n    poll 0\n    irscan $_CHIPNAME-lv.tap 0x143ff3a\n    drscan $_CHIPNAME-lv.tap 32 1\n    jtag tapdisable $_CHIPNAME-lv.tap\n    poll 1\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm5352e.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset _CHIPNAME bcm5352e\nset _CPUID 0x0535217f\n\njtag newtap $_CHIPNAME cpu -irlen 8 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bcm6348.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset _CHIPNAME bcm6348\nset _CPUID 0x0634817f\n\nadapter speed 1000\n\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bluefield.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# BlueField SoC Target\n\nset _CHIPNAME bluefield\n\n# Specify the target device\n#rshim device /dev/rshim0/rshim\n\n# Main DAP\nif { [info exists DAP_TAPID] } {\n   set _DAP_TAPID $DAP_TAPID\n} else {\n   set _DAP_TAPID 0x4ba00477\n}\n\nadapter speed 1500\n\nswd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# Initialize the target name and command variable.\nset _TARGETNAME $_CHIPNAME.cpu\nset _smp_command \"\"\n\n# CTI relative address\nset $_TARGETNAME.cti(0) 0xC4020000\nset $_TARGETNAME.cti(1) 0xC4120000\nset $_TARGETNAME.cti(2) 0xC8020000\nset $_TARGETNAME.cti(3) 0xC8120000\nset $_TARGETNAME.cti(4) 0xCC020000\nset $_TARGETNAME.cti(5) 0xCC120000\nset $_TARGETNAME.cti(6) 0xD0020000\nset $_TARGETNAME.cti(7) 0xD0120000\nset $_TARGETNAME.cti(8) 0xD4020000\nset $_TARGETNAME.cti(9) 0xD4120000\nset $_TARGETNAME.cti(10) 0xD8020000\nset $_TARGETNAME.cti(11) 0xD8120000\nset $_TARGETNAME.cti(12) 0xDC020000\nset $_TARGETNAME.cti(13) 0xDC120000\nset $_TARGETNAME.cti(14) 0xE0020000\nset $_TARGETNAME.cti(15) 0xE0120000\n\n# Create debug targets for a number of cores starting from core '_core_start'.\n# Adjust the numbers according to board configuration.\nset _core_start 0\nset _cores 16\n\n# Create each core\nfor { set _core $_core_start } { $_core < $_core_start + $_cores } { incr _core 1 } {\n    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0\n\n    set _command \"target create ${_TARGETNAME}$_core aarch64 \\\n                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core\"\n\n    if { $_core != $_core_start } {\n        set _smp_command \"$_smp_command ${_TARGETNAME}$_core\"\n    } else {\n        set _smp_command \"target smp ${_TARGETNAME}$_core\"\n    }\n\n    eval $_command\n}\n\n# Configure SMP\nif { $_cores > 1 } {\n    eval $_smp_command\n}\n\n# Make sure the default target is the boot core\ntargets ${_TARGETNAME}0\n\nproc core_up { args } {\n\tglobal _TARGETNAME\n\n\t# Examine remaining cores\n\tforeach _core $args {\n\t\t${_TARGETNAME}$_core arp_examine\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/bluenrg-x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# bluenrg-1/2 and bluenrg-lp devices support only SWD transports.\n#\n\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME bluenrg-1\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 24kB-256bytes\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x5F00\n}\n\nadapter speed 4000\n\nswj_newdap $_CHIPNAME cpu -expected-id 0x0bb11477 -expected-id 0x0bc11477\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\nset WDOG_VALUE 0\nset WDOG_VALUE_SET 0\n\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000100 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME bluenrg-x 0 0 0 0 $_TARGETNAME\n\n# In BlueNRG-X reset pin is actually a shutdown (power-off), so define reset as none\nreset_config none\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\nset JTAG_IDCODE_B2 0x0200A041\nset JTAG_IDCODE_B1 0x0\n\n$_TARGETNAME configure -event halted {\n    global WDOG_VALUE\n    global WDOG_VALUE_SET\n    set _JTAG_IDCODE [mrw 0x40000004]\n    if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {\n        # Stop watchdog during halt, if enabled. Only Bluenrg-1/2\n        set WDOG_VALUE [mrw 0x40700008]\n        if [expr {$WDOG_VALUE & (1 << 1)}] {\n            set WDOG_VALUE_SET 1\n            mww 0x40700008 [expr {$WDOG_VALUE & 0xFFFFFFFD}]\n        }\n    }\n}\n$_TARGETNAME configure -event resumed {\n    global WDOG_VALUE\n    global WDOG_VALUE_SET\n    set _JTAG_IDCODE [mrw 0x40000004]\n    if {$_JTAG_IDCODE == $JTAG_IDCODE_B2 || $_JTAG_IDCODE == $JTAG_IDCODE_B1} {\n        if {$WDOG_VALUE_SET} {\n            # Restore watchdog enable value after resume. Only Bluenrg-1/2\n            mww 0x40700008 $WDOG_VALUE\n            set WDOG_VALUE_SET 0\n           }\n   }\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/c100.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# c100 config.\n# This is ARM1136 dual core\n# this script only configures one core (that is used to run Linux)\n\n# assume no PLL lock, start slowly\nadapter speed 100\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME c100\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x27b3645b\n}\n\nif { [info exists DSPTAPID] } {\n   set _DSPTAPID $DSPTAPID\n} else {\n   set _DSPTAPID 0x27b3645b\n}\n\njtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_DSPTAPID\n\n\n# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# C100's ARAM 64k SRAM\n$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/c100config.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# board(-config) specific parameters file.\n\n# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]\nproc config {label} {\n    return [dict get [configC100] $label ]\n}\n\n# show the value for the param. with label\nproc showconfig {label} {\n    echo [format \"0x%x\" [dict get [configC100] $label ]]\n}\n\n# Telo board config\n# when there are more then one board config\n# use soft links to c100board-config.tcl\n# so that only the right board-config gets\n# included (just like include/configs/board-configs.h\n# in u-boot.\nproc configC100 {} {\n    # xtal freq. 24MHz\n    dict set configC100 CFG_REFCLKFREQ\t         24000000\n\n    # Amba Clk 165MHz\n    dict set configC100 CONFIG_SYS_HZ_CLOCK      165000000\n    dict set configC100 w_amba 1\n    dict set configC100 x_amba 1\n    # y = amba_clk * (w+1)*(x+1)*2/xtal_clk\n    dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]\n\n    # Arm Clk 450MHz, must be a multiple of 25 MHz\n    dict set configC100 CFG_ARM_CLOCK      450000000\n    dict set configC100 w_arm 0\n    dict set configC100 x_arm 1\n    # y = arm_clk * (w+1)*(x+1)*2/xtal_clk\n    dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]\n\n\n}\n\n# This should be called for reset init event handler\nproc setupTelo {} {\n\n    # setup GPIO used as control signals for C100\n    setupGPIO\n    # This will allow access to lower 8MB or NOR\n    lowGPIO5\n    # setup NOR size,timing,etc.\n    setupNOR\n    # setup internals + PLL + DDR2\n    initC100\n}\n\n\nproc setupNOR {} {\n    echo \"Setting up NOR: 16MB, 16-bit wide bus, CS0\"\n    # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()\n    set EX_CSEN_REG\t    [regs EX_CSEN_REG ]\n    set EX_CS0_SEG_REG\t    [regs EX_CS0_SEG_REG ]\n    set EX_CS0_CFG_REG\t    [regs EX_CS0_CFG_REG ]\n    set EX_CS0_TMG1_REG\t    [regs EX_CS0_TMG1_REG ]\n    set EX_CS0_TMG2_REG\t    [regs EX_CS0_TMG2_REG ]\n    set EX_CS0_TMG3_REG\t    [regs EX_CS0_TMG3_REG ]\n    set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]\n    set EX_MFSM_REG\t    [regs EX_MFSM_REG ]\n    set EX_CSFSM_REG\t    [regs EX_CSFSM_REG ]\n    set EX_WRFSM_REG\t    [regs EX_WRFSM_REG ]\n    set EX_RDFSM_REG\t    [regs EX_RDFSM_REG ]\n\n    # enable Expansion Bus Clock + CS0 (NOR)\n    mww $EX_CSEN_REG 0x3\n    # set the address space for CS0=16MB\n    mww $EX_CS0_SEG_REG 0x7ff\n    # set the CS0 bus width to 16-bit\n    mww $EX_CS0_CFG_REG 0x202\n    # set timings to NOR\n    mww $EX_CS0_TMG1_REG 0x03034006\n    mww $EX_CS0_TMG2_REG 0x04040002\n    #mww $EX_CS0_TMG3_REG\n    # set EBUS clock 165/5=33MHz\n    mww $EX_CLOCK_DIV_REG 0x5\n    # everything else is OK with default\n}\n\nproc bootNOR {} {\n    set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]\n    set BLOCK_RESET_REG\t       [regs BLOCK_RESET_REG]\n    set DDR_RST\t\t       [regs DDR_RST]\n\n    # put DDR controller in reset (so that it comes reset in u-boot)\n    mmw $BLOCK_RESET_REG 0x0 $DDR_RST\n    # setup CS0 controller for NOR\n    setupNOR\n    # make sure we are accessing the lower part of NOR\n    lowGPIO5\n    # set PC to start of NOR (at boot 0x20000000 = 0x0)\n    reg pc $EXP_CS0_BASEADDR\n    # run\n    resume\n}\nproc setupGPIO {} {\n    echo \"Setting up GPIO block for Telo\"\n    # This is current setup for Telo (see sch. for details):\n    #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup\n    #GPIO1 irq line for FXS-FXO\n    #GPIO5 addr22 for NOR flash (access to upper 8MB)\n    #GPIO17 reset for DECT module.\n    #GPIO29 CS_n for NAND\n\n    set GPIO_OUTPUT_REG\t\t    [regs GPIO_OUTPUT_REG]\n    set GPIO_OE_REG\t\t    [regs GPIO_OE_REG]\n\n    # set GPIO29=GPIO17=1, GPIO5=0\n    mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}]\n    # enable [as output] GPIO29,GPIO17,GPIO5\n    mww $GPIO_OE_REG [expr  {1<<29 | 1<<17 | 1<<5}]\n}\n\nproc highGPIO5 {} {\n    echo \"GPIO5 high\"\n    set GPIO_OUTPUT_REG\t\t    [regs GPIO_OUTPUT_REG]\n    # set GPIO5=1\n    mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0\n}\n\nproc lowGPIO5 {} {\n    echo \"GPIO5 low\"\n    set GPIO_OUTPUT_REG\t\t    [regs GPIO_OUTPUT_REG]\n    # set GPIO5=0\n    mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}]\n}\n\nproc boardID {id} {\n    # so far built:\n    # 4'b1111\n    dict set boardID 15 name \"EVT1\"\n    dict set boardID 15 ddr2size 128M\n    # dict set boardID 15 nandsize 1G\n    # dict set boardID 15 norsize 16M\n    # 4'b0000\n    dict set boardID 0 name \"EVT2\"\n    dict set boardID 0 ddr2size 128M\n    # 4'b0001\n    dict set boardID 1 name \"EVT3\"\n    dict set boardID 1 ddr2size 256M\n    # 4'b1110\n    dict set boardID 14 name \"EVT3_old\"\n    dict set boardID 14 ddr2size 128M\n    # 4'b0010\n    dict set boardID 2 name \"EVT4\"\n    dict set boardID 2 ddr2size 256M\n\n    return $boardID\n}\n\n\n# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()\n# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors\nproc ooma_board_detect {} {\n    set GPIO_BOOTSTRAP_REG\t[regs GPIO_BOOTSTRAP_REG]\n\n    # read the current value of the BOOTSTRAP pins\n    set tmp [mrw $GPIO_BOOTSTRAP_REG]\n    echo [format \"GPIO_BOOTSTRAP_REG  (0x%x): 0x%x\" $GPIO_BOOTSTRAP_REG $tmp]\n    # extract the GPBP bits\n    set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}]\n\n    # display board ID\n    echo [format \"This is %s (0x%x)\" [dict get [boardID $gpbt] $gpbt name] $gpbt]\n    # show it on serial console\n    putsUART0 [format \"This is %s (0x%x)\\n\" [dict get [boardID $gpbt] $gpbt name] $gpbt]\n    # return the ddr2 size, used to configure DDR2 on a given board.\n    return [dict get [boardID $gpbt] $gpbt ddr2size]\n}\n\nproc configureDDR2regs_256M {} {\n\n    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]\n    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]\n    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]\n    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]\n    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]\n    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]\n    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]\n    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]\n    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]\n    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]\n    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]\n    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]\n    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]\n    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]\n    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]\n    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]\n    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]\n    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]\n    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]\n    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]\n    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]\n\n    set DENALI_CTL_02_VAL 0x0100000000010100\n    set DENALI_CTL_11_VAL 0x433a32164a560a00\n\n    mw64bit $DENALI_CTL_00_DATA  0x0100000101010101\n    # 01_DATA mod [40]=1, enable BA2\n    mw64bit $DENALI_CTL_01_DATA  0x0100010100000001\n    mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL\n    mw64bit $DENALI_CTL_03_DATA  0x0102020202020201\n    mw64bit $DENALI_CTL_04_DATA  0x0000010100000001\n    mw64bit $DENALI_CTL_05_DATA  0x0203010300010101\n    mw64bit $DENALI_CTL_06_DATA  0x060a020200020202\n    mw64bit $DENALI_CTL_07_DATA  0x0000000300000206\n    mw64bit $DENALI_CTL_08_DATA  0x6400003f3f0a0209\n    mw64bit $DENALI_CTL_09_DATA  0x1a000000001a1a1a\n    mw64bit $DENALI_CTL_10_DATA  0x0120202020191a18\n    # 11_DATA mod [39-32]=16,more refresh\n    mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL\n    mw64bit $DENALI_CTL_12_DATA  0x0000000000000800\n    mw64bit $DENALI_CTL_13_DATA  0x0010002000100040\n    mw64bit $DENALI_CTL_14_DATA  0x0010004000100040\n    mw64bit $DENALI_CTL_15_DATA  0x04f8000000000000\n    mw64bit $DENALI_CTL_16_DATA  0x000000002cca0000\n    mw64bit $DENALI_CTL_17_DATA  0x0000000000000000\n    mw64bit $DENALI_CTL_18_DATA  0x0302000000000000\n    mw64bit $DENALI_CTL_19_DATA  0x00001300c8030600\n    mw64bit $DENALI_CTL_20_DATA  0x0000000081fe00c8\n\n    set wr_dqs_shift 0x40\n    # start DDRC\n    mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]\n    # wait int_status[2] (DRAM init complete)\n    echo -n \"Waiting for DDR2 controller to init...\"\n    set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]\n    while { [expr {$tmp & 0x040000}] == 0 } {\n\tsleep 1\n\tset tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]\n    }\n    echo \"done.\"\n\n    # do ddr2 training sequence\n    # TBD (for now, if you need it, run trainDDR command)\n}\n\n# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()\n# The values are computed based on Mindspeed and Nanya datasheets\nproc configureDDR2regs_128M {} {\n\n    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]\n    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]\n    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]\n    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]\n    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]\n    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]\n    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]\n    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]\n    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]\n    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]\n    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]\n    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]\n    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]\n    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]\n    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]\n    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]\n    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]\n    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]\n    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]\n    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]\n    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]\n\n\n    set DENALI_CTL_02_VAL 0x0100010000010100\n    set DENALI_CTL_11_VAL 0x433A42124A650A37\n    # set some default values\n    mw64bit $DENALI_CTL_00_DATA  0x0100000101010101\n    mw64bit $DENALI_CTL_01_DATA  0x0100000100000101\n    mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL\n    mw64bit $DENALI_CTL_03_DATA  0x0102020202020201\n    mw64bit $DENALI_CTL_04_DATA  0x0201010100000201\n    mw64bit $DENALI_CTL_05_DATA  0x0203010300010101\n    mw64bit $DENALI_CTL_06_DATA  0x050A020200020202\n    mw64bit $DENALI_CTL_07_DATA  0x000000030E0B0205\n    mw64bit $DENALI_CTL_08_DATA  0x6427003F3F0A0209\n    mw64bit $DENALI_CTL_09_DATA  0x1A00002F00001A00\n    mw64bit $DENALI_CTL_10_DATA  0x01202020201A1A1A\n    mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL\n    mw64bit $DENALI_CTL_12_DATA  0x0000080000000800\n    mw64bit $DENALI_CTL_13_DATA  0x0010002000100040\n    mw64bit $DENALI_CTL_14_DATA  0x0010004000100040\n    mw64bit $DENALI_CTL_15_DATA  0x0508000000000000\n    mw64bit $DENALI_CTL_16_DATA  0x000020472D200000\n    mw64bit $DENALI_CTL_17_DATA  0x0000000008000000\n    mw64bit $DENALI_CTL_18_DATA  0x0302000000000000\n    mw64bit $DENALI_CTL_19_DATA  0x00001400C8030604\n    mw64bit $DENALI_CTL_20_DATA  0x00000000823600C8\n\n    set wr_dqs_shift 0x40\n    # start DDRC\n    mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]\n    # wait int_status[2] (DRAM init complete)\n    echo -n \"Waiting for DDR2 controller to init...\"\n    set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]\n    while { [expr {$tmp & 0x040000}] == 0 } {\n\tsleep 1\n\tset tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]\n    }\n    # This is not necessary\n    #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL  & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ]\n    echo \"done.\"\n\n    # do ddr2 training sequence\n    # TBD (for now, if you need it, run trainDDR command)\n}\n\n\n\nproc setupUART0 {} {\n    # configure UART0 to 115200, 8N1\n    set GPIO_LOCK_REG      [regs GPIO_LOCK_REG]\n    set GPIO_IOCTRL_REG    [regs GPIO_IOCTRL_REG]\n    set GPIO_IOCTRL_VAL    [regs GPIO_IOCTRL_VAL]\n    set GPIO_IOCTRL_UART0  [regs GPIO_IOCTRL_UART0]\n    set UART0_LCR\t            [regs UART0_LCR]\n    set LCR_DLAB\t\t    [regs LCR_DLAB]\n    set UART0_DLL\t\t    [regs UART0_DLL]\n    set UART0_DLH\t\t    [regs UART0_DLH]\n    set UART0_IIR\t\t    [regs UART0_IIR]\n    set UART0_IER\t\t    [regs UART0_IER]\n    set LCR_ONE_STOP\t\t    [regs LCR_ONE_STOP]\n    set LCR_CHAR_LEN_8\t\t    [regs LCR_CHAR_LEN_8]\n    set FCR_XMITRES\t\t    [regs FCR_XMITRES]\n    set FCR_RCVRRES\t\t    [regs FCR_RCVRRES]\n    set FCR_FIFOEN\t\t    [regs FCR_FIFOEN]\n    set IER_UUE\t\t\t    [regs IER_UUE]\n\n    # unlock writing to IOCTRL register\n    mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL\n    # enable UART0\n    mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0\n    # baudrate  115200\n    # This should really be amba_clk/(16*115200) but amba_clk=165MHz\n    set tmp 89\n    # Enable Divisor Latch access\n    mmw  $UART0_LCR $LCR_DLAB 0x0\n    # set the divisor to $tmp\n    mww $UART0_DLL [expr {$tmp & 0xff}]\n    mww $UART0_DLH [expr {$tmp >> 8}]\n    # Disable Divisor Latch access\n    mmw  $UART0_LCR 0x0 $LCR_DLAB\n    # set the UART to 8N1\n    mmw  $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0\n    # reset FIFO\n    mmw  $UART0_IIR [expr {$FCR_XMITRES  | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0\n    #  enable FFUART\n    mww $UART0_IER $IER_UUE\n}\n\nproc putcUART0 {char} {\n\n    set UART0_LSR\t    [regs UART0_LSR]\n    set UART0_THR\t    [regs UART0_THR]\n    set LSR_TEMT\t    [regs LSR_TEMT]\n\n    # convert the 'char' to digit\n    set tmp [ scan $char %c ]\n    # /* wait for room in the tx FIFO on FFUART */\n    while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 }\n    mww $UART0_THR $tmp\n    if { $char == \"\\n\" } { putcUART0 \\r }\n}\n\nproc putsUART0 {str} {\n    set index 0\n    set len [string length $str]\n    while { $index < $len } {\n\tputcUART0 [string index $str $index]\n\tset index [expr {$index + 1}]\n    }\n}\n\n\nproc trainDDR2 {} {\n    set ARAM_BASEADDR\t[regs ARAM_BASEADDR]\n\n    # you must have run 'reset init' or u-boot\n    # load the training code to ARAM\n    load_image ./images/ddr2train.bin $ARAM_BASEADDR bin\n    # set PC to start of NOR (at boot 0x20000000 = 0x0)\n    reg pc $ARAM_BASEADDR\n    # run\n    resume\n}\n\nproc flashUBOOT {file} {\n    # this will update uboot on NOR partition\n    set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]\n\n    # setup CS0 controller for NOR\n    setupNOR\n    # make sure we are accessing the lower part of NOR\n    lowGPIO5\n    flash probe 0\n    echo \"Erasing sectors 0-3 for uboot\"\n    putsUART0 \"Erasing sectors 0-3 for uboot\\n\"\n    flash erase_sector 0 0 3\n    echo \"Programming u-boot\"\n    putsUART0 \"Programming u-boot...\"\n    arm11 memwrite burst enable\n    flash write_image $file $EXP_CS0_BASEADDR\n    arm11 memwrite burst disable\n    putsUART0 \"done.\\n\"\n    putsUART0 \"Rebooting, please wait!\\n\"\n    reboot\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/c100helper.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nproc helpC100 {} {\n    echo \"List of useful functions for C100 processor:\"\n    echo \"1)  reset init:        will set up your Telo board\"\n    echo \"2)  setupNOR:          will setup NOR access\"\n    echo \"3)  showNOR:           will show current NOR config registers for 16-bit, 16MB NOR\"\n    echo \"4)  setupGPIO:         will setup GPIOs for Telo board\"\n    echo \"5)  showGPIO:          will show current GPIO config registers\"\n    echo \"6)  highGPIO5:         will set GPIO5=NOR_addr22=1 to access upper 8MB\"\n    echo \"7)  lowGPIO5:          will set GPIO5=NOR_addr22=0 to access lower 8MB\"\n    echo \"8)  showAmbaClk:       will show current config registers for Amba Bus Clock\"\n    echo \"9)  setupAmbaClk:      will setup Amba Bus Clock=165MHz\"\n    echo \"10) showArmClk:        will show current config registers for Arm Bus Clock\"\n    echo \"11) setupArmClk:       will setup Amba Bus Clock=450MHz\"\n    echo \"12) ooma_board_detect: will show which version of Telo you have\"\n    echo \"13) setupDDR2:         will configure DDR2 controller, you must have PLLs configured\"\n    echo \"14) showDDR2:          will show DDR2 config registers\"\n    echo \"15) showWatchdog:      will show current register config for watchdog\"\n    echo \"16) reboot:            will trigger watchdog and reboot Telo (hw reset)\"\n    echo \"17) bootNOR:           will boot Telo from NOR\"\n    echo \"18) setupUART0:        will configure UART0 for 115200 8N1, PLLs have to be configured\"\n    echo \"19) putcUART0:         will print a character on UART0\"\n    echo \"20) putsUART0:         will print a string on UART0\"\n    echo \"21) trainDDR2:         will run DDR2 training program\"\n    echo \"22) flashUBOOT:        will program NOR sectors 0-3 with u-boot.bin\"\n}\n\nsource [find mem_helper.tcl]\n\n# read a 64-bit register (memory mapped)\nproc mr64bit {reg} {\n    return [read_memory $reg 32 2]\n}\n\n\n# write a 64-bit register (memory mapped)\nproc mw64bit {reg value} {\n    set high [expr {$value >> 32}]\n    set low  [expr {$value & 0xffffffff}]\n    #echo [format \"mw64bit(0x%x): 0x%08x%08x\" $reg $high $low]\n    mww $reg $low\n    mww [expr {$reg+4}] $high\n}\n\n\nproc showNOR {} {\n    echo \"This is the current NOR setup\"\n    set EX_CSEN_REG\t    [regs EX_CSEN_REG ]\n    set EX_CS0_SEG_REG\t    [regs EX_CS0_SEG_REG ]\n    set EX_CS0_CFG_REG\t    [regs EX_CS0_CFG_REG ]\n    set EX_CS0_TMG1_REG\t    [regs EX_CS0_TMG1_REG ]\n    set EX_CS0_TMG2_REG\t    [regs EX_CS0_TMG2_REG ]\n    set EX_CS0_TMG3_REG\t    [regs EX_CS0_TMG3_REG ]\n    set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]\n    set EX_MFSM_REG\t    [regs EX_MFSM_REG ]\n    set EX_CSFSM_REG\t    [regs EX_CSFSM_REG ]\n    set EX_WRFSM_REG\t    [regs EX_WRFSM_REG ]\n    set EX_RDFSM_REG\t    [regs EX_RDFSM_REG ]\n\n    echo [format \"EX_CSEN_REG      (0x%x): 0x%x\" $EX_CSEN_REG [mrw $EX_CSEN_REG]]\n    echo [format \"EX_CS0_SEG_REG   (0x%x): 0x%x\" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]\n    echo [format \"EX_CS0_CFG_REG   (0x%x): 0x%x\" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]\n    echo [format \"EX_CS0_TMG1_REG  (0x%x): 0x%x\" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]\n    echo [format \"EX_CS0_TMG2_REG  (0x%x): 0x%x\" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]\n    echo [format \"EX_CS0_TMG3_REG  (0x%x): 0x%x\" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]\n    echo [format \"EX_CLOCK_DIV_REG (0x%x): 0x%x\" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]\n    echo [format \"EX_MFSM_REG      (0x%x): 0x%x\" $EX_MFSM_REG [mrw $EX_MFSM_REG]]\n    echo [format \"EX_CSFSM_REG     (0x%x): 0x%x\" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]\n    echo [format \"EX_WRFSM_REG     (0x%x): 0x%x\" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]\n    echo [format \"EX_RDFSM_REG     (0x%x): 0x%x\" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]\n}\n\n\n\nproc showGPIO {} {\n    echo \"This is the current GPIO register setup\"\n    # GPIO outputs register\n    set GPIO_OUTPUT_REG\t\t    [regs GPIO_OUTPUT_REG]\n    # GPIO Output Enable register\n    set GPIO_OE_REG\t\t    [regs GPIO_OE_REG]\n    set GPIO_HI_INT_ENABLE_REG\t    [regs GPIO_HI_INT_ENABLE_REG]\n    set GPIO_LO_INT_ENABLE_REG\t    [regs GPIO_LO_INT_ENABLE_REG]\n    # GPIO input register\n    set GPIO_INPUT_REG\t\t    [regs GPIO_INPUT_REG]\n    set APB_ACCESS_WS_REG\t    [regs APB_ACCESS_WS_REG]\n    set MUX_CONF_REG\t\t    [regs MUX_CONF_REG]\n    set SYSCONF_REG\t\t    [regs SYSCONF_REG]\n    set GPIO_ARM_ID_REG\t\t    [regs GPIO_ARM_ID_REG]\n    set GPIO_BOOTSTRAP_REG\t    [regs GPIO_BOOTSTRAP_REG]\n    set GPIO_LOCK_REG\t\t    [regs GPIO_LOCK_REG]\n    set GPIO_IOCTRL_REG\t\t    [regs GPIO_IOCTRL_REG]\n    set GPIO_DEVID_REG\t\t    [regs GPIO_DEVID_REG]\n\n    echo [format \"GPIO_OUTPUT_REG       (0x%x): 0x%x\" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]\n    echo [format \"GPIO_OE_REG           (0x%x): 0x%x\" $GPIO_OE_REG [mrw $GPIO_OE_REG]]\n    echo [format \"GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x\" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]\n    echo [format \"GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x\" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]\n    echo [format \"GPIO_INPUT_REG        (0x%x): 0x%x\" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]\n    echo [format \"APB_ACCESS_WS_REG     (0x%x): 0x%x\" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]\n    echo [format \"MUX_CONF_REG          (0x%x): 0x%x\" $MUX_CONF_REG [mrw $MUX_CONF_REG]]\n    echo [format \"SYSCONF_REG           (0x%x): 0x%x\" $SYSCONF_REG [mrw $SYSCONF_REG]]\n    echo [format \"GPIO_ARM_ID_REG       (0x%x): 0x%x\" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]\n    echo [format \"GPIO_BOOTSTRAP_REG    (0x%x): 0x%x\" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]\n    echo [format \"GPIO_LOCK_REG         (0x%x): 0x%x\" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]\n    echo [format \"GPIO_IOCTRL_REG       (0x%x): 0x%x\" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]\n    echo [format \"GPIO_DEVID_REG        (0x%x): 0x%x\" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]\n}\n\n\n\n# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())\nproc showAmbaClk {} {\n    set CFG_REFCLKFREQ\t\t     [config CFG_REFCLKFREQ]\n    set CLKCORE_AHB_CLK_CNTRL\t     [regs CLKCORE_AHB_CLK_CNTRL]\n    set PLL_CLK_BYPASS\t             [regs PLL_CLK_BYPASS]\n\n    echo [format \"CLKCORE_AHB_CLK_CNTRL       (0x%x): 0x%x\" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]\n    set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1]\n    # see if the PLL is in bypass mode\n    set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]\n    echo [format \"PLL bypass bit: %d\" $bypass]\n    if {$bypass == 1} {\n\techo [format \"Amba Clk is set to REFCLK: %d (MHz)\" [expr {$CFG_REFCLKFREQ/1000000}]]\n    } else {\n\t# nope, extract x,y,w and compute the PLL output freq.\n\tset x [expr {($value & 0x0001F0000) >> 16}]\n\techo [format \"x: %d\" $x]\n\tset y [expr {($value & 0x00000007F)}]\n\techo [format \"y: %d\" $y]\n\tset w [expr {($value & 0x000000300) >> 8}]\n\techo [format \"w: %d\" $w]\n\techo [format \"Amba PLL Clk: %d (MHz)\" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]\n    }\n}\n\n\n# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())\n# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)\nproc setupAmbaClk {} {\n    set CLKCORE_PLL_STATUS           [regs CLKCORE_PLL_STATUS]\n    set CLKCORE_AHB_CLK_CNTRL\t     [regs CLKCORE_AHB_CLK_CNTRL]\n    set ARM_PLL_BY_CTRL\t    [regs ARM_PLL_BY_CTRL]\n    set ARM_AHB_BYP\t    [regs ARM_AHB_BYP]\n    set PLL_DISABLE\t    [regs PLL_DISABLE]\n    set PLL_CLK_BYPASS\t    [regs PLL_CLK_BYPASS]\n    set AHB_PLL_BY_CTRL\t    [regs AHB_PLL_BY_CTRL]\n    set DIV_BYPASS\t    [regs DIV_BYPASS]\n    set AHBCLK_PLL_LOCK\t    [regs AHBCLK_PLL_LOCK]\n    set CFG_REFCLKFREQ\t\t [config CFG_REFCLKFREQ]\n    set CONFIG_SYS_HZ_CLOCK      [config CONFIG_SYS_HZ_CLOCK]\n    set w    [config w_amba]\n    set x    [config x_amba]\n    set y    [config y_amba]\n\n    echo [format \"Setting Amba PLL to lock to %d MHz\" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]]\n    #echo [format \"setupAmbaClk: w= %d\" $w]\n    #echo [format \"setupAmbaClk: x= %d\" $x]\n    #echo [format \"setupAmbaClk: y= %d\" $y]\n    # set PLL into BYPASS mode using MUX\n    mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0\n    # do an internal PLL bypass\n    mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0\n    # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)\n    # openocd smallest resolution is 1ms so, wait 1ms\n    sleep 1\n    # disable the PLL\n    mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0\n    # wait 1ms\n    sleep 1\n    # enable the PLL\n    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE\n    sleep 1\n    # set X, W and X\n    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF\n    mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0\n    # wait for PLL to lock\n    echo \"Waiting for Amba PLL to lock\"\n    while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 }\n    # remove the internal PLL bypass\n    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL\n    # remove PLL from BYPASS mode using MUX\n    mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS\n}\n\n\n# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())\nproc showArmClk {} {\n    set CFG_REFCLKFREQ\t\t[config CFG_REFCLKFREQ]\n    set CLKCORE_ARM_CLK_CNTRL\t[regs CLKCORE_ARM_CLK_CNTRL]\n    set PLL_CLK_BYPASS\t        [regs PLL_CLK_BYPASS]\n\n    echo [format \"CLKCORE_ARM_CLK_CNTRL       (0x%x): 0x%x\" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]\n    set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1]\n    # see if the PLL is in bypass mode\n    set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]\n    echo [format \"PLL bypass bit: %d\" $bypass]\n    if {$bypass == 1} {\n\techo [format \"Amba Clk is set to REFCLK: %d (MHz)\" [expr {$CFG_REFCLKFREQ/1000000}]]\n    } else {\n\t# nope, extract x,y,w and compute the PLL output freq.\n\tset x [expr {($value & 0x0001F0000) >> 16}]\n\techo [format \"x: %d\" $x]\n\tset y [expr {($value & 0x00000007F)}]\n\techo [format \"y: %d\" $y]\n\tset w [expr {($value & 0x000000300) >> 8}]\n\techo [format \"w: %d\" $w]\n\techo [format \"Arm PLL Clk: %d (MHz)\" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]\n    }\n}\n\n# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())\n# Arm Clock is used by two ARM1136 cores\nproc setupArmClk {} {\n    set CLKCORE_PLL_STATUS        [regs CLKCORE_PLL_STATUS]\n    set CLKCORE_ARM_CLK_CNTRL\t  [regs CLKCORE_ARM_CLK_CNTRL]\n    set ARM_PLL_BY_CTRL\t          [regs ARM_PLL_BY_CTRL]\n    set ARM_AHB_BYP\t          [regs ARM_AHB_BYP]\n    set PLL_DISABLE\t          [regs PLL_DISABLE]\n    set PLL_CLK_BYPASS\t          [regs PLL_CLK_BYPASS]\n    set AHB_PLL_BY_CTRL\t          [regs AHB_PLL_BY_CTRL]\n    set DIV_BYPASS\t          [regs DIV_BYPASS]\n    set FCLK_PLL_LOCK\t          [regs FCLK_PLL_LOCK]\n    set CFG_REFCLKFREQ\t\t[config CFG_REFCLKFREQ]\n    set CFG_ARM_CLOCK\t\t[config CFG_ARM_CLOCK]\n    set w    [config w_arm]\n    set x    [config x_arm]\n    set y    [config y_arm]\n\n    echo [format \"Setting Arm PLL to lock to %d MHz\" [expr {$CFG_ARM_CLOCK/1000000}]]\n    #echo [format \"setupArmClk: w= %d\" $w]\n    #echo [format \"setupArmaClk: x= %d\" $x]\n    #echo [format \"setupArmaClk: y= %d\" $y]\n    # set PLL into BYPASS mode using MUX\n    mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0\n    # do an internal PLL bypass\n    mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0\n    # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)\n    # openocd smallest resolution is 1ms so, wait 1ms\n    sleep 1\n    # disable the PLL\n    mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0\n    # wait 1ms\n    sleep 1\n    # enable the PLL\n    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE\n    sleep 1\n    # set X, W and X\n    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF\n    mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0\n    # wait for PLL to lock\n    echo \"Waiting for Amba PLL to lock\"\n    while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 }\n    # remove the internal PLL bypass\n    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL\n    # remove PLL from BYPASS mode using MUX\n    mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS\n}\n\n\n\nproc setupPLL {} {\n    echo \"PLLs setup\"\n    setupAmbaClk\n    setupArmClk\n}\n\n# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()\nproc setupDDR2 {} {\n    echo \"Configuring DDR2\"\n\n    set MEMORY_BASE_ADDR\t    [regs  MEMORY_BASE_ADDR]\n    set MEMORY_MAX_ADDR\t            [regs  MEMORY_MAX_ADDR]\n    set MEMORY_CR \t\t    [regs  MEMORY_CR]\n    set BLOCK_RESET_REG\t\t    [regs  BLOCK_RESET_REG]\n    set DDR_RST\t\t            [regs  DDR_RST]\n\n    # put DDR controller in reset (so that it is reset and correctly configured)\n    # this is only necessary if DDR was previously confiured\n    # and not reset.\n    mmw $BLOCK_RESET_REG 0x0 $DDR_RST\n\n    set M [expr {1024 * 1024}]\n    set DDR_SZ_1024M\t[expr {1024 * $M}]\n    set DDR_SZ_256M\t[expr {256 * $M}]\n    set DDR_SZ_128M\t[expr {128 * $M}]\n    set DDR_SZ_64M\t[expr {64 * $M}]\n    # ooma_board_detect returns DDR2 memory size\n    set tmp [ooma_board_detect]\n    if {$tmp == \"128M\"} {\n\techo \"DDR2 size 128MB\"\n\tset ddr_size $DDR_SZ_128M\n    } elseif {$tmp == \"256M\"} {\n\techo \"DDR2 size 256MB\"\n\tset ddr_size $DDR_SZ_256M\n    } else {\n\techo \"Don't know how to handle this DDR2 size?\"\n    }\n\n    # Memory setup register\n    mww $MEMORY_MAX_ADDR  [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}]\n    # disable ROM remap\n    mww $MEMORY_CR 0x0\n    # Take DDR controller out of reset\n    mmw $BLOCK_RESET_REG $DDR_RST 0x0\n    # min. 20 ops delay\n    sleep 1\n\n    # This will setup Denali DDR2 controller\n    if {$tmp == \"128M\"} {\n\tconfigureDDR2regs_128M\n    } elseif {$tmp == \"256M\"} {\n\tconfigureDDR2regs_256M\n    } else {\n\techo \"Don't know how to configure DDR2 setup?\"\n    }\n}\n\n\n\nproc showDDR2 {} {\n\n    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]\n    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]\n    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]\n    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]\n    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]\n    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]\n    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]\n    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]\n    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]\n    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]\n    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]\n    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]\n    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]\n    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]\n    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]\n    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]\n    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]\n    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]\n    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]\n    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]\n    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]\n\n    set tmp [mr64bit $DENALI_CTL_00_DATA]\n    echo [format \"DENALI_CTL_00_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_01_DATA]\n    echo [format \"DENALI_CTL_01_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_02_DATA]\n    echo [format \"DENALI_CTL_02_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_03_DATA]\n    echo [format \"DENALI_CTL_03_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_04_DATA]\n    echo [format \"DENALI_CTL_04_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_05_DATA]\n    echo [format \"DENALI_CTL_05_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_06_DATA]\n    echo [format \"DENALI_CTL_06_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_07_DATA]\n    echo [format \"DENALI_CTL_07_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_08_DATA]\n    echo [format \"DENALI_CTL_08_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_09_DATA]\n    echo [format \"DENALI_CTL_09_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_10_DATA]\n    echo [format \"DENALI_CTL_10_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_11_DATA]\n    echo [format \"DENALI_CTL_11_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_12_DATA]\n    echo [format \"DENALI_CTL_12_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_13_DATA]\n    echo [format \"DENALI_CTL_13_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_14_DATA]\n    echo [format \"DENALI_CTL_14_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_15_DATA]\n    echo [format \"DENALI_CTL_15_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_16_DATA]\n    echo [format \"DENALI_CTL_16_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_17_DATA]\n    echo [format \"DENALI_CTL_17_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_18_DATA]\n    echo [format \"DENALI_CTL_18_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_19_DATA]\n    echo [format \"DENALI_CTL_19_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]\n    set tmp [mr64bit $DENALI_CTL_20_DATA]\n    echo [format \"DENALI_CTL_20_DATA   (0x%x): 0x%08x%08x\" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]\n\n}\n\nproc initC100 {} {\n    # this follows u-boot/cpu/arm1136/start.S\n    set GPIO_LOCK_REG\t\t    [regs GPIO_LOCK_REG]\n    set GPIO_IOCTRL_REG\t\t    [regs GPIO_IOCTRL_REG]\n    set GPIO_IOCTRL_VAL\t            [regs GPIO_IOCTRL_VAL]\n    set APB_ACCESS_WS_REG           [regs APB_ACCESS_WS_REG]\n    set ASA_ARAM_BASEADDR\t    [regs ASA_ARAM_BASEADDR]\n    set ASA_ARAM_TC_CR_REG\t    [regs ASA_ARAM_TC_CR_REG]\n    set ASA_EBUS_BASEADDR\t    [regs ASA_EBUS_BASEADDR]\n    set ASA_EBUS_TC_CR_REG\t    [regs ASA_EBUS_TC_CR_REG]\n    set ASA_TC_REQIDMAEN\t    [regs ASA_TC_REQIDMAEN]\n    set ASA_TC_REQTDMEN\t            [regs ASA_TC_REQTDMEN]\n    set ASA_TC_REQIPSECUSBEN        [regs ASA_TC_REQIPSECUSBEN]\n    set ASA_TC_REQARM0EN\t    [regs ASA_TC_REQARM0EN]\n    set ASA_TC_REQARM1EN\t    [regs ASA_TC_REQARM1EN]\n    set ASA_TC_REQMDMAEN\t    [regs ASA_TC_REQMDMAEN]\n    set INTC_ARM1_CONTROL_REG       [regs INTC_ARM1_CONTROL_REG]\n\n\n    # unlock writing to IOCTRL register\n    mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL\n    # enable address lines A15-A21\n    mmw $GPIO_IOCTRL_REG 0xf 0x0\n    # set ARM into supervisor mode (SVC32)\n    # disable IRQ, FIQ\n    # Do I need this in JTAG mode?\n    # it really should be done as 'and ~0x1f | 0xd3 but\n    # openocd does not support this yet\n    reg cpsr 0xd3\n    #\t/*\n    #\t * flush v4 I/D caches\n    #\t */\n    #\tmov\tr0, #0\n    #\tmcr\tp15, 0, r0, c7, c7, 0\t/* flush v3/v4 cache */\n    arm mcr 15 0 7 7 0 0x0\n    #\tmcr\tp15, 0, r0, c8, c7, 0\t/* flush v4 TLB */\n    arm mcr 15 0 8 7 0 0x0\n\n    #\t/*\n    #\t * disable MMU stuff and caches\n    #\t */\n    #\tmrc\tp15, 0, r0, c1, c0, 0\n    arm mrc 15 0 1 0 0\n    #\tbic\tr0, r0, #0x00002300\t@ clear bits 13, 9:8 (--V- --RS)\n    #\tbic\tr0, r0, #0x00000087\t@ clear bits 7, 2:0 (B--- -CAM)\n    #\torr\tr0, r0, #0x00000002\t@ set bit 2 (A) Align\n    #\torr\tr0, r0, #0x00001000\t@ set bit 12 (I) I-Cache\n    #\torr\tr0, r0, #0x00400000\t@ set bit 22 (U)\n    #\tmcr\tp15, 0, r0, c1, c0, 0\n    arm mcr 15 0 1 0 0 0x401002\n    # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c\n    # APB init\n    #    \t// Setting APB Bus Wait states to 1, set post write\n    #\t(*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;\n    mww $APB_ACCESS_WS_REG 0x40\n    # AHB init\n    #\t// enable all 6 masters for ARAM\n    mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0\n    #\t// enable all 6 masters for EBUS\n    mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0\n\n    # ARAM init\n    #\t// disable pipeline mode in ARAM\n    # I don't think this is documented anywhere?\n    mww $INTC_ARM1_CONTROL_REG 0x1\n    # configure clocks\n    setupPLL\n    # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.\n    setupUART0\n    # enable cache\n    # ? (u-boot does nothing here)\n    # DDR2 memory init\n    setupDDR2\n    putsUART0 \"C100 initialization complete.\\n\"\n    echo \"C100 initialization complete.\"\n}\n\n# show current state of watchdog timer\nproc showWatchdog {} {\n    set TIMER_WDT_HIGH_BOUND\t[regs TIMER_WDT_HIGH_BOUND]\n    set TIMER_WDT_CONTROL\t[regs TIMER_WDT_CONTROL]\n    set TIMER_WDT_CURRENT_COUNT\t[regs TIMER_WDT_CURRENT_COUNT]\n\n    echo [format \"TIMER_WDT_HIGH_BOUND    (0x%x): 0x%x\" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]\n    echo [format \"TIMER_WDT_CONTROL       (0x%x): 0x%x\" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]\n    echo [format \"TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x\" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]\n}\n\n# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)\n# this will trigger watchdog reset\n# the sw. reset does not work on C100\n# watchdog reset effectively works as hw. reset\nproc reboot {} {\n    set TIMER_WDT_HIGH_BOUND\t[regs TIMER_WDT_HIGH_BOUND]\n    set TIMER_WDT_CONTROL\t[regs TIMER_WDT_CONTROL]\n    set TIMER_WDT_CURRENT_COUNT\t[regs TIMER_WDT_CURRENT_COUNT]\n\n    # allow the counter to count to high value  before triggering\n    # this is because register writes are slow over JTAG and\n    # I don't want to miss the high_bound==curr_count condition\n    mww $TIMER_WDT_HIGH_BOUND  0xffffff\n    mww $TIMER_WDT_CURRENT_COUNT 0x0\n    echo \"JTAG speed lowered to 100kHz\"\n    adapter speed 100\n    mww $TIMER_WDT_CONTROL 0x1\n    # wait until the reset\n    echo -n \"Waiting for watchdog to trigger...\"\n    #while {[mrw $TIMER_WDT_CONTROL] == 1} {\n    #    echo [format \"TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x\" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]\n    #    sleep 1\n    #\n    #}\n    while {[c100.cpu curstate] != \"running\"} { sleep 1}\n    echo \"done.\"\n    echo [format \"Note that C100 is in %s state, type halt to stop\" [c100.cpu curstate]]\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/c100regs.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Note that I basically converted\n# u-boot/include/asm-arm/arch/comcerto_100.h\n# defines\n\n# this is a work-around for 'global' not working under Linux\n# access registers by calling this routine.\n# For example:\n# set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]\nproc regs {reg} {\n    return [dict get [regsC100] $reg ]\n}\n\nproc showreg {reg} {\n    echo [format \"0x%x\" [dict get [regsC100] $reg ]]\n}\n\nproc regsC100 {} {\n#/* memcore */\n#/* device memory base addresses */\n#// device memory sizes\n#/* ARAM SIZE=64K */\ndict set regsC100 ARAM_SIZE\t\t0x00010000\ndict set regsC100 ARAM_BASEADDR\t0x0A000000\n\n#/* Hardware Interface Units */\ndict set regsC100 APB_BASEADDR\t0x10000000\n#/* APB_SIZE=16M address range */\ndict set regsC100 APB_SIZE\t\t0x01000000\n\ndict set regsC100 EXP_CS0_BASEADDR       0x20000000\ndict set regsC100 EXP_CS1_BASEADDR       0x24000000\ndict set regsC100 EXP_CS2_BASEADDR       0x28000000\ndict set regsC100 EXP_CS3_BASEADDR       0x2C000000\ndict set regsC100 EXP_CS4_BASEADDR       0x30000000\n\ndict set regsC100 DDR_BASEADDR           0x80000000\n\ndict set regsC100 TDM_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x000000}]\ndict set regsC100 PHI_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x010000}]\ndict set regsC100 TDMA_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x020000}]\ndict set regsC100 ASA_DDR_BASEADDR\t        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x040000}]\ndict set regsC100 ASA_ARAM_BASEADDR\t        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x048000}]\ndict set regsC100 TIMER_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x050000}]\ndict set regsC100 ASD_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x060000}]\ndict set regsC100 GPIO_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x070000}]\ndict set regsC100 UART0_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x090000}]\ndict set regsC100 UART1_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x094000}]\ndict set regsC100 SPI_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x098000}]\ndict set regsC100 I2C_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x09C000}]\ndict set regsC100 INTC_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0A0000}]\ndict set regsC100 CLKCORE_BASEADDR\t        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}]\ndict set regsC100 PUI_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0B0000}]\ndict set regsC100 GEMAC_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0D0000}]\ndict set regsC100 IDMA_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x0E0000}]\ndict set regsC100 MEMCORE_BASEADDR\t        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x0F0000}]\ndict set regsC100 ASA_EBUS_BASEADDR\t        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x100000}]\ndict set regsC100 ASA_AAB_BASEADDR\t        [expr {[dict get $regsC100 APB_BASEADDR ] + 0x108000}]\ndict set regsC100 GEMAC1_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x190000}]\ndict set regsC100 EBUS_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x1A0000}]\ndict set regsC100 MDMA_BASEADDR\t\t[expr {[dict get $regsC100 APB_BASEADDR ] + 0x1E0000}]\n\n\n#////////////////////////////////////////////////////////////\n#//\tAHB block\t\t\t\t\t\t\t\t\t\t\t    //\n#////////////////////////////////////////////////////////////\ndict set regsC100 ASA_ARAM_PRI_REG\t[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00}]\ndict set regsC100 ASA_ARAM_TC_REG\t[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04}]\ndict set regsC100 ASA_ARAM_TC_CR_REG\t[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08}]\ndict set regsC100 ASA_ARAM_STAT_REG\t[expr {[dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C}]\n\ndict set regsC100 ASA_EBUS_PRI_REG\t[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00}]\ndict set regsC100 ASA_EBUS_TC_REG\t[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04}]\ndict set regsC100 ASA_EBUS_TC_CR_REG\t[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08}]\ndict set regsC100 ASA_EBUS_STAT_REG\t[expr {[dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C}]\n\ndict set regsC100 IDMA_MASTER\t\t0\ndict set regsC100 TDMA_MASTER\t\t1\ndict set regsC100 USBIPSEC_MASTER\t2\ndict set regsC100 ARM0_MASTER\t\t3\ndict set regsC100 ARM1_MASTER\t\t4\ndict set regsC100 MDMA_MASTER\t\t5\n\n#define IDMA_PRIORITY(level) (level)\n#define TDM_PRIORITY(level) (level << 4)\n#define USBIPSEC_PRIORITY(level) (level << 8)\n#define ARM0_PRIORITY(level) (level << 12)\n#define ARM1_PRIORITY(level) (level << 16)\n#define MDMA_PRIORITY(level) (level << 20)\n\ndict set regsC100 ASA_TC_REQIDMAEN\t [expr {1<<18}]\ndict set regsC100 ASA_TC_REQTDMEN\t [expr {1<<19}]\ndict set regsC100 ASA_TC_REQIPSECUSBEN [expr {1<<20}]\ndict set regsC100 ASA_TC_REQARM0EN\t [expr {1<<21}]\ndict set regsC100 ASA_TC_REQARM1EN\t [expr {1<<22}]\ndict set regsC100 ASA_TC_REQMDMAEN\t [expr {1<<23}]\n\ndict set regsC100 MEMORY_BASE_ADDR\t0x80000000\ndict set regsC100 MEMORY_MAX_ADDR\t[expr {[dict get $regsC100 ASD_BASEADDR ] + 0x10}]\ndict set regsC100 MEMORY_CR \t\t[expr {[dict get $regsC100 ASD_BASEADDR ] + 0x14}]\ndict set regsC100 ROM_REMAP_EN\t0x1\n\n#define HAL_asb_priority(level) \\\n#*(volatile unsigned *)ASA_PRI_REG = level\n\n#define HAL_aram_priority(level) \\\n#*(volatile unsigned *)ASA_ARAM_PRI_REG = level\n\n#define HAL_aram_arbitration(arbitration_mask) \\\n#*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask\n\n#define HAL_aram_defmaster(mask) \\\n#*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24)\n\n#////////////////////////////////////////////////////////////\n#// INTC block\t\t\t\t\t\t  //\n#////////////////////////////////////////////////////////////\n\ndict set regsC100 INTC_ARM1_CONTROL_REG\t[expr {[dict get $regsC100 INTC_BASEADDR ] + 0x18}]\n\n#////////////////////////////////////////////////////////////\n#// TIMER block\t\t\t\t\t\t  //\n#////////////////////////////////////////////////////////////\n\ndict set regsC100 TIMER0_CNTR_REG\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x00}]\ndict set regsC100 TIMER0_CURR_COUNT\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x04}]\ndict set regsC100 TIMER1_CNTR_REG\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x08}]\ndict set regsC100 TIMER1_CURR_COUNT\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x0C}]\n\ndict set regsC100 TIMER2_CNTR_REG\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x18}]\ndict set regsC100 TIMER2_LBOUND_REG\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x10}]\ndict set regsC100 TIMER2_HBOUND_REG\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x14}]\ndict set regsC100 TIMER2_CURR_COUNT\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x1C}]\n\ndict set regsC100 TIMER3_LOBND\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x20}]\ndict set regsC100 TIMER3_HIBND\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x24}]\ndict set regsC100 TIMER3_CTRL\t\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x28}]\ndict set regsC100 TIMER3_CURR_COUNT\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x2C}]\n\ndict set regsC100 TIMER_MASK\t\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x40}]\ndict set regsC100 TIMER_STATUS\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}]\ndict set regsC100 TIMER_ACK\t\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0x50}]\ndict set regsC100 TIMER_WDT_HIGH_BOUND [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD0}]\ndict set regsC100 TIMER_WDT_CONTROL\t[expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD4}]\ndict set regsC100 TIMER_WDT_CURRENT_COUNT [expr {[dict get $regsC100 TIMER_BASEADDR ] + 0xD8}]\n\n\n\n#////////////////////////////////////////////////////////////\n#//  EBUS block\n#////////////////////////////////////////////////////////////\n\ndict set regsC100 EX_SWRST_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x00}]\ndict set regsC100 EX_CSEN_REG\t\t        [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x04}]\ndict set regsC100 EX_CS0_SEG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x08}]\ndict set regsC100 EX_CS1_SEG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x0C}]\ndict set regsC100 EX_CS2_SEG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x10}]\ndict set regsC100 EX_CS3_SEG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x14}]\ndict set regsC100 EX_CS4_SEG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x18}]\ndict set regsC100 EX_CS0_CFG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x1C}]\ndict set regsC100 EX_CS1_CFG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x20}]\ndict set regsC100 EX_CS2_CFG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x24}]\ndict set regsC100 EX_CS3_CFG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x28}]\ndict set regsC100 EX_CS4_CFG_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x2C}]\ndict set regsC100 EX_CS0_TMG1_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x30}]\ndict set regsC100 EX_CS1_TMG1_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x34}]\ndict set regsC100 EX_CS2_TMG1_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x38}]\ndict set regsC100 EX_CS3_TMG1_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x3C}]\ndict set regsC100 EX_CS4_TMG1_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x40}]\ndict set regsC100 EX_CS0_TMG2_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x44}]\ndict set regsC100 EX_CS1_TMG2_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x48}]\ndict set regsC100 EX_CS2_TMG2_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x4C}]\ndict set regsC100 EX_CS3_TMG2_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x50}]\ndict set regsC100 EX_CS4_TMG2_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x54}]\ndict set regsC100 EX_CS0_TMG3_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x58}]\ndict set regsC100 EX_CS1_TMG3_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x5C}]\ndict set regsC100 EX_CS2_TMG3_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x60}]\ndict set regsC100 EX_CS3_TMG3_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x64}]\ndict set regsC100 EX_CS4_TMG3_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x68}]\ndict set regsC100 EX_CLOCK_DIV_REG\t        [expr {[dict get $regsC100 EBUS_BASEADDR ] + 0x6C}]\n\ndict set regsC100 EX_MFSM_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}]\ndict set regsC100 EX_MFSM_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x100}]\ndict set regsC100 EX_CSFSM_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x104}]\ndict set regsC100 EX_WRFSM_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x108}]\ndict set regsC100 EX_RDFSM_REG\t\t[expr {[dict get $regsC100 EBUS_BASEADDR] + 0x10C}]\n\n\ndict set regsC100 EX_CLK_EN\t\t0x00000001\ndict set regsC100 EX_CSBOOT_EN\t0x00000002\ndict set regsC100 EX_CS0_EN\t\t0x00000002\ndict set regsC100 EX_CS1_EN\t\t0x00000004\ndict set regsC100 EX_CS2_EN\t\t0x00000008\ndict set regsC100 EX_CS3_EN\t\t0x00000010\ndict set regsC100 EX_CS4_EN\t\t0x00000020\n\ndict set regsC100 EX_MEM_BUS_8\t0x00000000\ndict set regsC100 EX_MEM_BUS_16       0x00000002\ndict set regsC100 EX_MEM_BUS_32\t0x00000004\ndict set regsC100 EX_CS_HIGH\t\t0x00000008\ndict set regsC100 EX_WE_HIGH\t\t0x00000010\ndict set regsC100 EX_RE_HIGH\t\t0x00000020\ndict set regsC100 EX_ALE_MODE\t\t0x00000040\ndict set regsC100 EX_STRB_MODE\t0x00000080\ndict set regsC100 EX_DM_MODE\t\t0x00000100\ndict set regsC100 EX_NAND_MODE\t0x00000200\ndict set regsC100 EX_RDY_EN\t\t0x00000400\ndict set regsC100 EX_RDY_EDGE\t\t0x00000800\n\n#////////////////////////////////////////////////////////////\n#//  GPIO block\n#////////////////////////////////////////////////////////////\n\n# GPIO outputs register\ndict set regsC100 GPIO_OUTPUT_REG\t\t[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x00}]\n# GPIO Output Enable register\ndict set regsC100 GPIO_OE_REG\t\t        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x04}]\ndict set regsC100 GPIO_HI_INT_ENABLE_REG\t[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x08}]\ndict set regsC100 GPIO_LO_INT_ENABLE_REG\t[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x0C}]\n# GPIO input register\ndict set regsC100 GPIO_INPUT_REG\t\t[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x10}]\ndict set regsC100 APB_ACCESS_WS_REG\t        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x14}]\ndict set regsC100 MUX_CONF_REG\t\t[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x18}]\ndict set regsC100 SYSCONF_REG\t\t        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x1C}]\ndict set regsC100 GPIO_ARM_ID_REG\t\t[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x30}]\ndict set regsC100 GPIO_BOOTSTRAP_REG\t        [expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x40}]\ndict set regsC100 GPIO_LOCK_REG\t\t[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x38}]\ndict set regsC100 GPIO_IOCTRL_REG\t\t[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x44}]\ndict set regsC100 GPIO_DEVID_REG\t\t[expr {[dict get $regsC100 GPIO_BASEADDR ] + 0x50}]\n\ndict set regsC100 GPIO_IOCTRL_A15A16\t0x00000001\ndict set regsC100 GPIO_IOCTRL_A17A18\t0x00000002\ndict set regsC100 GPIO_IOCTRL_A19A21\t0x00000004\ndict set regsC100 GPIO_IOCTRL_TMREVT0\t0x00000008\ndict set regsC100 GPIO_IOCTRL_TMREVT1\t0x00000010\ndict set regsC100 GPIO_IOCTRL_GPBT3\t0x00000020\ndict set regsC100 GPIO_IOCTRL_I2C\t0x00000040\ndict set regsC100 GPIO_IOCTRL_UART0\t0x00000080\ndict set regsC100 GPIO_IOCTRL_UART1\t0x00000100\ndict set regsC100 GPIO_IOCTRL_SPI\t0x00000200\ndict set regsC100 GPIO_IOCTRL_HBMODE\t0x00000400\n\ndict set regsC100 GPIO_IOCTRL_VAL\t0x55555555\n\ndict set regsC100 GPIO_0\t\t\t0x01\ndict set regsC100 GPIO_1\t\t\t0x02\ndict set regsC100 GPIO_2\t\t\t0x04\ndict set regsC100 GPIO_3\t\t\t0x08\ndict set regsC100 GPIO_4\t\t\t0x10\ndict set regsC100 GPIO_5\t\t\t0x20\ndict set regsC100 GPIO_6\t\t\t0x40\ndict set regsC100 GPIO_7\t\t\t0x80\n\ndict set regsC100 GPIO_RISING_EDGE\t1\ndict set regsC100 GPIO_FALLING_EDGE\t2\ndict set regsC100 GPIO_BOTH_EDGES\t3\n\n#////////////////////////////////////////////////////////////\n#// UART\n#////////////////////////////////////////////////////////////\n\ndict set regsC100 UART0_RBR\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]\ndict set regsC100 UART0_THR\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]\ndict set regsC100 UART0_DLL\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x00}]\ndict set regsC100 UART0_IER\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}]\ndict set regsC100 UART0_DLH\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x04}]\ndict set regsC100 UART0_IIR\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}]\ndict set regsC100 UART0_FCR\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x08}]\ndict set regsC100 UART0_LCR\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x0C}]\ndict set regsC100 UART0_MCR\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x10}]\ndict set regsC100 UART0_LSR\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x14}]\ndict set regsC100 UART0_MSR\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x18}]\ndict set regsC100 UART0_SCR\t\t[expr {[dict get $regsC100 UART0_BASEADDR ] + 0x1C}]\n\ndict set regsC100 UART1_RBR\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]\ndict set regsC100 UART1_THR\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]\ndict set regsC100 UART1_DLL\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x00}]\ndict set regsC100 UART1_IER\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}]\ndict set regsC100 UART1_DLH\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x04}]\ndict set regsC100 UART1_IIR\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}]\ndict set regsC100 UART1_FCR\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x08}]\ndict set regsC100 UART1_LCR\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x0C}]\ndict set regsC100 UART1_MCR\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x10}]\ndict set regsC100 UART1_LSR\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x14}]\ndict set regsC100 UART1_MSR\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x18}]\ndict set regsC100 UART1_SCR\t\t[expr {[dict get $regsC100 UART1_BASEADDR ] + 0x1C}]\n\n# /* default */\ndict set regsC100 LCR_CHAR_LEN_5\t\t0x00\ndict set regsC100 LCR_CHAR_LEN_6\t\t0x01\ndict set regsC100 LCR_CHAR_LEN_7\t\t0x02\ndict set regsC100 LCR_CHAR_LEN_8\t\t0x03\n#/* One stop bit! - default */\ndict set regsC100 LCR_ONE_STOP\t\t0x00\n#/* Two stop bit! */\ndict set regsC100 LCR_TWO_STOP\t\t0x04\n#/* Parity Enable */\ndict set regsC100 LCR_PEN\t\t\t0x08\ndict set regsC100 LCR_PARITY_NONE\t\t0x00\n#/* Even Parity Select */\ndict set regsC100 LCR_EPS\t\t\t0x10\n#/* Enable Parity  Stuff */\ndict set regsC100 LCR_PS\t\t\t0x20\n#/* Start Break */\ndict set regsC100 LCR_SBRK\t\t        0x40\n#/* Parity Stuff Bit */\ndict set regsC100 LCR_PSB\t\t\t0x80\n#/* UART 16550 Divisor Latch Assess */\ndict set regsC100 LCR_DLAB\t\t        0x80\n\n#/* FIFO Error Status */\ndict set regsC100 LSR_FIFOE\t\t[expr {1 << 7}]\n#/* Transmitter Empty */\ndict set regsC100 LSR_TEMT\t\t[expr {1 << 6}]\n#/* Transmit Data Request */\ndict set regsC100 LSR_TDRQ\t\t[expr {1 << 5}]\n#/* Break Interrupt */\ndict set regsC100 LSR_BI\t\t\t[expr {1 << 4}]\n#/* Framing Error */\ndict set regsC100 LSR_FE\t\t\t[expr {1 << 3}]\n#/* Parity Error */\ndict set regsC100 LSR_PE\t\t\t[expr {1 << 2}]\n#/* Overrun Error */\ndict set regsC100 LSR_OE\t\t\t[expr {1 << 1}]\n#/* Data Ready */\ndict set regsC100 LSR_DR\t\t\t[expr {1 << 0}]\n\n#/* DMA Requests Enable */\ndict set regsC100 IER_DMAE\t\t        [expr {1 << 7}]\n#/* UART Unit Enable */\ndict set regsC100 IER_UUE\t\t\t[expr {1 << 6}]\n#/* NRZ coding Enable */\ndict set regsC100 IER_NRZE\t\t        [expr {1 << 5}]\n#/* Receiver Time Out Interrupt Enable */\ndict set regsC100 IER_RTIOE\t\t        [expr {1 << 4}]\n#/* Modem Interrupt Enable */\ndict set regsC100 IER_MIE\t\t\t[expr {1 << 3}]\n#/* Receiver Line Status Interrupt Enable */\ndict set regsC100 IER_RLSE\t\t        [expr {1 << 2}]\n#/* Transmit Data request Interrupt Enable */\ndict set regsC100 IER_TIE\t\t\t[expr {1 << 1}]\n#/* Receiver Data Available Interrupt Enable */\ndict set regsC100 IER_RAVIE\t\t        [expr {1 << 0}]\n\n#/* FIFO Mode Enable Status */\ndict set regsC100 IIR_FIFOES1\t\t        [expr {1 << 7}]\n#/* FIFO Mode Enable Status */\ndict set regsC100 IIR_FIFOES0\t\t        [expr {1 << 6}]\n#/* Time Out Detected */\ndict set regsC100 IIR_TOD\t\t\t[expr {1 << 3}]\n#/* Interrupt Source Encoded */\ndict set regsC100 IIR_IID2\t\t        [expr {1 << 2}]\n#/* Interrupt Source Encoded */\ndict set regsC100 IIR_IID1\t\t        [expr {1 << 1}]\n#/* Interrupt Pending (active low) */\ndict set regsC100 IIR_IP\t\t\t[expr {1 << 0}]\n\n#/* UART 16550 FIFO Control Register */\ndict set regsC100 FCR_FIFOEN\t\t0x01\ndict set regsC100 FCR_RCVRRES\t\t0x02\ndict set regsC100 FCR_XMITRES\t\t0x04\n\n#/* Interrupt Enable Register */\n#// UART 16550\n#// Enable Received Data Available Interrupt\ndict set regsC100 IER_RXTH\t\t0x01\n#// Enable Transmitter Empty Interrupt\ndict set regsC100 IER_TXTH\t\t0x02\n\n\n\n#////////////////////////////////////////////////////////////\n#// CLK  + RESET block\n#////////////////////////////////////////////////////////////\n\ndict set regsC100 CLKCORE_ARM_CLK_CNTRL\t[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x00}]\ndict set regsC100 CLKCORE_AHB_CLK_CNTRL\t[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x04}]\ndict set regsC100 CLKCORE_PLL_STATUS\t        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x08}]\ndict set regsC100 CLKCORE_CLKDIV_CNTRL\t[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C}]\ndict set regsC100 CLKCORE_TDM_CLK_CNTRL\t[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x10}]\ndict set regsC100 CLKCORE_FSYNC_CNTRL\t        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x14}]\ndict set regsC100 CLKCORE_CLK_PWR_DWN\t        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x18}]\ndict set regsC100 CLKCORE_RNG_CNTRL\t        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C}]\ndict set regsC100 CLKCORE_RNG_STATUS\t        [expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x20}]\ndict set regsC100 CLKCORE_ARM_CLK_CNTRL2\t[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x24}]\ndict set regsC100 CLKCORE_TDM_REF_DIV_RST\t[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x40}]\n\ndict set regsC100 ARM_PLL_BY_CTRL\t0x80000000\ndict set regsC100 ARM_AHB_BYP\t\t0x04000000\ndict set regsC100 PLL_DISABLE\t\t0x02000000\ndict set regsC100 PLL_CLK_BYPASS\t0x01000000\n\ndict set regsC100 AHB_PLL_BY_CTRL\t0x80000000\ndict set regsC100 DIV_BYPASS\t\t0x40000000\ndict set regsC100 SYNC_MODE\t\t0x20000000\n\ndict set regsC100 EPHY_CLKDIV_BYPASS\t0x00200000\ndict set regsC100 EPHY_CLKDIV_RATIO_SHIFT\t16\ndict set regsC100 PUI_CLKDIV_BYPASS\t0x00004000\ndict set regsC100 PUI_CLKDIV_SRCCLK\t0x00002000\ndict set regsC100 PUI_CLKDIV_RATIO_SHIFT\t8\ndict set regsC100 PCI_CLKDIV_BYPASS\t0x00000020\ndict set regsC100 PCI_CLKDIV_RATIO_SHIFT\t0\n\ndict set regsC100 ARM0_CLK_PD\t\t0x00200000\ndict set regsC100 ARM1_CLK_PD\t\t0x00100000\ndict set regsC100 EPHY_CLK_PD\t\t0x00080000\ndict set regsC100 TDM_CLK_PD\t\t0x00040000\ndict set regsC100 PUI_CLK_PD\t\t0x00020000\ndict set regsC100 PCI_CLK_PD\t\t0x00010000\ndict set regsC100 MDMA_AHBCLK_PD\t0x00000400\ndict set regsC100 I2CSPI_AHBCLK_PD\t0x00000200\ndict set regsC100 UART_AHBCLK_PD\t0x00000100\ndict set regsC100 IPSEC_AHBCLK_PD\t0x00000080\ndict set regsC100 TDM_AHBCLK_PD\t0x00000040\ndict set regsC100 USB1_AHBCLK_PD\t0x00000020\ndict set regsC100 USB0_AHBCLK_PD\t0x00000010\ndict set regsC100 GEMAC1_AHBCLK_PD\t0x00000008\ndict set regsC100 GEMAC0_AHBCLK_PD\t0x00000004\ndict set regsC100 PUI_AHBCLK_PD\t0x00000002\ndict set regsC100 HIF_AHBCLK_PD\t0x00000001\n\ndict set regsC100 ARM1_DIV_BP\t\t0x00001000\ndict set regsC100 ARM1_DIV_VAL_SHIFT\t8\ndict set regsC100 ARM0_DIV_BP\t\t0x00000010\ndict set regsC100 ARM0_DIV_VAL_SHIFT\t0\n\ndict set regsC100 AHBCLK_PLL_LOCK\t0x00000002\ndict set regsC100 FCLK_PLL_LOCK\t0x00000001\n\n\n#// reset block\ndict set regsC100 BLOCK_RESET_REG\t\t[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x100}]\ndict set regsC100 CSP_RESET_REG\t\t[expr {[dict get $regsC100 CLKCORE_BASEADDR ] + 0x104}]\n\ndict set regsC100 RNG_RST\t\t0x1000\ndict set regsC100 IPSEC_RST\t\t0x0800\ndict set regsC100 DDR_RST\t\t0x0400\ndict set regsC100 USB1_PHY_RST\t0x0200\ndict set regsC100 USB0_PHY_RST\t0x0100\ndict set regsC100 USB1_RST\t\t0x0080\ndict set regsC100 USB0_RST\t\t0x0040\ndict set regsC100 GEMAC1_RST\t\t0x0020\ndict set regsC100 GEMAC0_RST\t\t0x0010\ndict set regsC100 TDM_RST\t\t0x0008\ndict set regsC100 PUI_RST\t\t0x0004\ndict set regsC100 HIF_RST\t\t0x0002\ndict set regsC100 PCI_RST\t\t0x0001\n\n#////////////////////////////////////////////////////////////////\n#//\tDDR  CONTROLLER block\n#////////////////////////////////////////////////////////////////\n\ndict set regsC100 DDR_CONFIG_BASEADDR\t0x0D000000\ndict set regsC100 DENALI_CTL_00_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00}]\ndict set regsC100 DENALI_CTL_01_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08}]\ndict set regsC100 DENALI_CTL_02_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10}]\ndict set regsC100 DENALI_CTL_03_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18}]\ndict set regsC100 DENALI_CTL_04_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20}]\ndict set regsC100 DENALI_CTL_05_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28}]\ndict set regsC100 DENALI_CTL_06_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30}]\ndict set regsC100 DENALI_CTL_07_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38}]\ndict set regsC100 DENALI_CTL_08_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40}]\ndict set regsC100 DENALI_CTL_09_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48}]\ndict set regsC100 DENALI_CTL_10_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50}]\ndict set regsC100 DENALI_CTL_11_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58}]\ndict set regsC100 DENALI_CTL_12_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60}]\ndict set regsC100 DENALI_CTL_13_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68}]\ndict set regsC100 DENALI_CTL_14_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70}]\ndict set regsC100 DENALI_CTL_15_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78}]\ndict set regsC100 DENALI_CTL_16_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80}]\ndict set regsC100 DENALI_CTL_17_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88}]\ndict set regsC100 DENALI_CTL_18_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90}]\ndict set regsC100 DENALI_CTL_19_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98}]\ndict set regsC100 DENALI_CTL_20_DATA\t[expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0}]\n\n# 32-bit value\ndict set regsC100 DENALI_READY_CHECK         [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44}]\n# 8-bit\ndict set regsC100 DENALI_WR_DQS              [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D}]\n# 8-bit\ndict set regsC100 DENALI_DQS_OUT             [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A}]\n# 8-bit\ndict set regsC100 DENALI_DQS_DELAY0          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F}]\n# 8-bit\ndict set regsC100 DENALI_DQS_DELAY1          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50}]\n# 8-bit\ndict set regsC100 DENALI_DQS_DELAY2          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51}]\n# 8-bit\ndict set regsC100 DENALI_DQS_DELAY3          [expr {[dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52}]\n\n\n# end of proc regsC100\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/cc2538.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config for Texas Instruments low power RF SoC CC2538\n# http://www.ti.com/lit/pdf/swru319\n\nadapter speed 100\n\nsource [find target/icepick.cfg]\nsource [find target/ti-cjtag.cfg]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME cc2538\n}\n\n#\n# Main DAP\n#\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x8B96402F\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable\njtag configure $_CHIPNAME.cpu -event tap-enable \"icepick_c_tapenable $_CHIPNAME.jrc 0\"\n\n#\n# ICEpick-C (JTAG route controller)\n#\nif { [info exists JRC_TAPID] } {\n\tset _JRC_TAPID $JRC_TAPID\n} else {\n\tset _JRC_TAPID 0x8B96402F\n}\njtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version\n# A start sequence is needed to change from cJTAG (Compact JTAG) to\n# 4-pin JTAG before talking via JTAG commands\njtag configure $_CHIPNAME.jrc -event setup \"jtag tapenable $_CHIPNAME.cpu\"\njtag configure $_CHIPNAME.jrc -event post-reset \"ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc\"\n\n#\n# Cortex-M3 target\n#\nset _TARGETNAME $_CHIPNAME.cpu\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/cs351x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME cs351x\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x00526fa1\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n# Create the GDB Target.\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# There is 16K of SRAM on this chip\n# FIXME: flash programming is not working by using this work area. So comment this out for now.\n#$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1\n\n# This chip has a DCC ... use it\narm7_9 dcc_downloads enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/davinci.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Utility code for DaVinci-family chips\n#\n\n# davinci_pinmux: assigns PINMUX$reg <== $value\nproc davinci_pinmux {soc reg value} {\n\tmww [expr {[dict get $soc sysbase] + 4 * $reg}] $value\n}\n\nsource [find mem_helper.tcl]\n\n#\n# pll_setup: initialize PLL\n#  - pll_addr ... physical addr of controller\n#  - mult ... pll multiplier\n#  - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers\n#\n# For PLLs that don't have a given register (e.g. plldiv8), or where a\n# given divider is non-programmable, caller provides *NO* config mapping.\n#\n\n# PLL version 0x02: tested on dm355\n# REVISIT: On dm6446/dm357 the PLLRST polarity is different.\nproc pll_v02_setup {pll_addr mult config} {\n\tset pll_ctrl_addr [expr {$pll_addr + 0x100}]\n\tset pll_ctrl [mrw $pll_ctrl_addr]\n\n\t# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator\n\t# NOTE: this assumes we should clear that bit\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0100}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 2 - clear PLLENSRC (bit 5)\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0020}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 3 - clear PLLEN (bit 0) ... enter bypass mode\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0001}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 4 - wait at least 4 refclk cycles\n\tsleep 1\n\n\t# 5 - set PLLRST (bit 3)\n\tset pll_ctrl [expr {$pll_ctrl | 0x0008}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 6 - set PLLDIS (bit 4)\n\tset pll_ctrl [expr {$pll_ctrl | 0x0010}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 7 - clear PLLPWRDN (bit 1)\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0002}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 8 - clear PLLDIS (bit 4)\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0010}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 9 - optional: write prediv, postdiv, and pllm\n\t# NOTE: for dm355 PLL1, postdiv is controlled via MISC register\n\tmww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}]\n\tif { [dict exists $config prediv] } {\n\t\tset div [dict get $config prediv]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0114}] $div\n\t}\n\tif { [dict exists $config postdiv] } {\n\t\tset div [dict get $config postdiv]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0128}] $div\n\t}\n\n\t# 10 - optional: set plldiv1, plldiv2, ...\n\t# NOTE:  this assumes some registers have their just-reset values:\n\t#\t- PLLSTAT.GOSTAT is clear when we enter\n\t#\t- ALNCTL has everything set\n\tset go 0\n\tif { [dict exists $config div1] } {\n\t\tset div [dict get $config div1]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0118}] $div\n\t\tset go 1\n\t}\n\tif { [dict exists $config div2] } {\n\t\tset div [dict get $config div2]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x011c}] $div\n\t\tset go 1\n\t}\n\tif { [dict exists $config div3] } {\n\t\tset div [dict get $config div3]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0120}] $div\n\t\tset go 1\n\t}\n\tif { [dict exists $config div4] } {\n\t\tset div [dict get $config div4]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0160}] $div\n\t\tset go 1\n\t}\n\tif { [dict exists $config div5] } {\n\t\tset div [dict get $config div5]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0164}] $div\n\t\tset go 1\n\t}\n\tif {$go != 0} {\n\t\t# write pllcmd.GO; poll pllstat.GO\n\t\tmww [expr {$pll_addr + 0x0138}] 0x01\n\t\tset pllstat [expr {$pll_addr + 0x013c}]\n\t\twhile {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }\n\t}\n\tmww [expr {$pll_addr + 0x0138}] 0x00\n\n\t# 11 - wait at least 5 usec for reset to finish\n\t# (assume covered by overheads including JTAG messaging)\n\n\t# 12 - clear PLLRST (bit 3)\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0008}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 13 - wait at least 8000 refclk cycles for PLL to lock\n\t# if we assume 24 MHz (slowest osc), that's 1/3 msec\n\tsleep 3\n\n\t# 14 - set PLLEN (bit 0) ... leave bypass mode\n\tset pll_ctrl [expr {$pll_ctrl | 0x0001}]\n\tmww $pll_ctrl_addr $pll_ctrl\n}\n\n# PLL version 0x03: tested on dm365\nproc pll_v03_setup {pll_addr mult config} {\n\tset pll_ctrl_addr [expr {$pll_addr + 0x100}]\n\tset pll_secctrl_addr [expr {$pll_addr + 0x108}]\n\tset pll_ctrl [mrw $pll_ctrl_addr]\n\n\t# 1 - power up the PLL\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0002}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 2 - clear PLLENSRC (bit 5)\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0020}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 2 - clear PLLEN (bit 0) ... enter bypass mode\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0001}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 3 - wait at least 4 refclk cycles\n\tsleep 1\n\n\t# 4 - set PLLRST (bit 3)\n\tset pll_ctrl [expr {$pll_ctrl | 0x0008}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 5 - wait at least 5 usec\n\tsleep 1\n\n\t# 6 - clear PLLRST (bit 3)\n\tset pll_ctrl [expr {$pll_ctrl & ~0x0008}]\n\tmww $pll_ctrl_addr $pll_ctrl\n\n\t# 9 - optional: write prediv, postdiv, and pllm\n\tmww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}]\n\tif { [dict exists $config prediv] } {\n\t\tset div [dict get $config prediv]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0114}] $div\n\t}\n\tif { [dict exists $config postdiv] } {\n\t\tset div [dict get $config postdiv]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0128}] $div\n\t}\n\n\t# 10 - write start sequence to PLLSECCTL\n\tmww $pll_secctrl_addr 0x00470000\n\tmww $pll_secctrl_addr 0x00460000\n\tmww $pll_secctrl_addr 0x00400000\n\tmww $pll_secctrl_addr 0x00410000\n\n\t# 11 - optional: set plldiv1, plldiv2, ...\n\t# NOTE: this assumes some registers have their just-reset values:\n\t#\t- PLLSTAT.GOSTAT is clear when we enter\n\tset aln 0\n\tif { [dict exists $config div1] } {\n\t\tset div [dict get $config div1]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0118}] $div\n\t\tset aln [expr {$aln | 0x1}]\n\t} else {\n\t\tmww [expr {$pll_addr + 0x0118}] 0\n\t}\n\tif { [dict exists $config div2] } {\n\t\tset div [dict get $config div2]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x011c}] $div\n\t\tset aln [expr {$aln | 0x2}]\n\t} else {\n\t\tmww [expr {$pll_addr + 0x011c}] 0\n\t}\n\tif { [dict exists $config div3] } {\n\t\tset div [dict get $config div3]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0120}] $div\n\t\tset aln [expr {$aln | 0x4}]\n\t} else {\n\t\tmww [expr {$pll_addr + 0x0120}] 0\n\t}\n\tif { [dict exists $config oscdiv] } {\n\t\tset div [dict get $config oscdiv]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0124}] $div\n\t} else {\n\t\tmww [expr {$pll_addr + 0x0124}] 0\n\t}\n\tif { [dict exists $config div4] } {\n\t\tset div [dict get $config div4]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0160}] $div\n\t\tset aln [expr {$aln | 0x8}]\n\t} else {\n\t\tmww [expr {$pll_addr + 0x0160}] 0\n\t}\n\tif { [dict exists $config div5] } {\n\t\tset div [dict get $config div5]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0164}] $div\n\t\tset aln [expr {$aln | 0x10}]\n\t} else {\n\t\tmww [expr {$pll_addr + 0x0164}] 0\n\t}\n\tif { [dict exists $config div6] } {\n\t\tset div [dict get $config div6]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0168}] $div\n\t\tset aln [expr {$aln | 0x20}]\n\t} else {\n\t\tmww [expr {$pll_addr + 0x0168}] 0\n\t}\n\tif { [dict exists $config div7] } {\n\t\tset div [dict get $config div7]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x016c}] $div\n\t\tset aln [expr {$aln | 0x40}]\n\t} else {\n\t\tmww [expr {$pll_addr + 0x016c}] 0\n\t}\n\tif { [dict exists $config div8] } {\n\t\tset div [dict get $config div8]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0170}] $div\n\t\tset aln [expr {$aln | 0x80}]\n\t} else {\n\t\tmww [expr {$pll_addr + 0x0170}] 0\n\t}\n\tif { [dict exists $config div9] } {\n\t\tset div [dict get $config div9]\n\t\tset div [expr {0x8000 | ($div - 1)}]\n\t\tmww [expr {$pll_addr + 0x0174}] $div\n\t\tset aln [expr {$aln | 0x100}]\n\t} else {\n\t\tmww [expr {$pll_addr + 0x0174}] 0\n\t}\n\tif {$aln != 0} {\n\t\t# clear pllcmd.GO\n\t\tmww [expr {$pll_addr + 0x0138}] 0x00\n\t\t# write alignment flags\n\t\tmww [expr {$pll_addr + 0x0140}] $aln\n\t\t# write pllcmd.GO; poll pllstat.GO\n\t\tmww [expr {$pll_addr + 0x0138}] 0x01\n\t\tset pllstat [expr {$pll_addr + 0x013c}]\n\t\twhile {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }\n\t}\n\tmww [expr {$pll_addr + 0x0138}] 0x00\n\tset addr [dict get $config ctladdr]\n\twhile {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 }\n\n\t# 12 - set PLLEN (bit 0) ... leave bypass mode\n\tset pll_ctrl [expr {$pll_ctrl | 0x0001}]\n\tmww $pll_ctrl_addr $pll_ctrl\n}\n\n# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain\n# modules can be enabled.\n\n# prepare a non-DSP module to be enabled; finish with psc_go\nproc psc_enable {module} {\n\tset psc_addr 0x01c41000\n\t# write MDCTL\n\tmmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f\n}\n\n# prepare a non-DSP module to be reset; finish with psc_go\nproc psc_reset {module} {\n\tset psc_addr 0x01c41000\n\t# write MDCTL\n\tmmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f\n}\n\n# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc\nproc psc_go {} {\n\tset psc_addr 0x01c41000\n\tset ptstat_addr [expr {$psc_addr + 0x0128}]\n\n\t# just in case PTSTAT.go isn't clear\n\twhile { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }\n\n\t# write PTCMD.go ... ignoring any DSP power domain\n\tmww [expr {$psc_addr + 0x0120}] 1\n\n\t# wait for PTSTAT.go to clear (again ignoring DSP power domain)\n\twhile { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }\n}\n\n#\n# A reset using only SRST is a \"Warm Reset\", resetting everything in the\n# chip except ARM emulation (and everything _outside_ the chip that hooks\n# up to SRST).  But many boards don't expose SRST via their JTAG connectors\n# (it's not present on TI-14 headers).\n#\n# From the chip-only perspective, a \"Max Reset\" is a \"Warm\" reset ... except\n# without any board-wide side effects, since it's triggered using JTAG using\n# either (a) ARM watchdog timer, or (b) ICEpick.\n#\nproc davinci_wdog_reset {} {\n\tset timer2_phys 0x01c21c00\n\n\t# NOTE -- on entry\n\t#   - JTAG communication with the ARM *must* be working OK; this\n\t#     may imply using adaptive clocking or disabling WFI-in-idle\n\t#   - current target must be the DaVinci ARM\n\t#   - that ARM core must be halted\n\t#   - timer2 clock is still enabled (PSC 29 on most chips)\n\n\t#\n\t# Part I -- run regardless of being halted via JTAG\n\t#\n\t# NOTE:  for now, we assume there's no DSP that could control the\n\t# watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog\n\t# suspend signal is controlled via ARM emulation suspend.\n\t#\n\n\t# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt\n\tmww phys [expr {$timer2_phys + 0x28}] 0x00004000\n\n\t#\n\t# Part II -- in case watchdog hasn't been set up\n\t#\n\n\t# TCR: disable, force internal clock source\n\tmww phys [expr {$timer2_phys + 0x20}] 0\n\n\t# TGCR: reset, force to 64-bit wdog mode, un-reset (\"initial\" state)\n\tmww phys [expr {$timer2_phys + 0x24}] 0\n\tmww phys [expr {$timer2_phys + 0x24}] 0x110b\n\n\t# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers\n\t# so watchdog triggers ASAP\n\tmww phys [expr {$timer2_phys + 0x10}] 0\n\tmww phys [expr {$timer2_phys + 0x14}] 0\n\tmww phys [expr {$timer2_phys + 0x18}] 0\n\tmww phys [expr {$timer2_phys + 0x1c}] 0\n\n\t# WDTCR: put into pre-active state, then active\n\tmww phys [expr {$timer2_phys + 0x28}] 0xa5c64000\n\tmww phys [expr {$timer2_phys + 0x28}] 0xda7e4000\n\n\t#\n\t# Part III -- it's ready to rumble\n\t#\n\n\t# WDTCR: write invalid WDKEY to trigger reset\n\tmww phys [expr {$timer2_phys + 0x28}] 0x00004000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/dragonite.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Marvell Dragonite CPU core\n######################################\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME dragonite\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x121003d3\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME\n\nreset_config trst_and_srst\nadapter srst delay 200\njtag_ntrst_delay 200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/dsp56321.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Script for freescale DSP56321\n#\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME dsp56321\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n  # this defaults to a big endian\n   set _ENDIAN big\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x1181501d\n}\n\n#jtag speed\nadapter speed 4500\n\n#has only srst\nreset_config srst_only\n\n#jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id $_CPUTAPID\n\n#target configuration\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME dsp563xx -endian $_ENDIAN -chain-position $_TARGETNAME\n\n#working area at base of ram\n$_TARGETNAME configure -work-area-virt 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/dsp568013.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Script for freescale DSP568013\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME dsp568013\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n  # this defaults to a big endian\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x01f2401d\n}\n\n#jtag speed\nadapter speed 800\n\nreset_config srst_only\n\n#MASTER tap\njtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID\n\n#CORE tap\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004\n\n#target configuration - There is only 1 tap at a time, hence only 1 target is defined.\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# Setup the interesting tap\n# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations require certain instruction to be in the IR register during reset, and polling would change this)\njtag configure $_CHIPNAME.chp -event setup \"\n     jtag tapenable $_TARGETNAME\n     poll off\n\"\n\n#select CORE tap by modifying the TLM register.\n#to be used when MASTER tap is selected.\njtag configure $_TARGETNAME -event tap-enable \"\n     irscan $_CHIPNAME.chp 0x05;\n     drscan $_CHIPNAME.chp 4 0x02;\n     jtag tapdisable $_CHIPNAME.chp;\n\"\n\n#select MASTER tap by modifying the TLM register.\n#to be used when CORE tap is selected.\njtag configure $_CHIPNAME.chp -event tap-enable \"\n     irscan $_TARGETNAME 0x08;\n     drscan $_TARGETNAME 4 0x1;\n     jtag tapdisable $_TARGETNAME;\n\"\n\n#disables the master tap\njtag configure $_TARGETNAME -event tap-disable \"\n\"\n#TODO FIND SMARTER WAY.\n\njtag configure $_CHIPNAME.chp -event tap-disable \"\n\"\n#TODO FIND SMARTER WAY.\n\n\n#working area at base of ram\n$_TARGETNAME configure -work-area-virt 0\n\n#setup flash\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/dsp568037.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Script for freescale DSP568037\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME dsp568037\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n  # this defaults to a big endian\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x01f2801d\n}\n\n#jtag speed\nadapter speed 800\n\nreset_config srst_only\n\n#MASTER tap\njtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID\n\n#CORE tap\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004\n\n#target configuration - There is only 1 tap at a time, hence only 1 target is defined.\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# Setup the interesting tap\njtag configure $_CHIPNAME.chp -event setup \"jtag tapenable $_TARGETNAME\"\n\n#select CORE tap by modifying the TLM register.\n#to be used when MASTER tap is selected.\njtag configure $_TARGETNAME -event tap-enable \"\n     irscan $_CHIPNAME.chp 0x05;\n     drscan $_CHIPNAME.chp 4 0x02;\n     jtag tapdisable $_CHIPNAME.chp;\n\"\n\n#select MASTER tap by modifying the TLM register.\n#to be used when CORE tap is selected.\njtag configure $_CHIPNAME.chp -event tap-enable \"\n     irscan $_TARGETNAME 0x08;\n     drscan $_TARGETNAME 4 0x1;\n     jtag tapdisable $_TARGETNAME;\n\"\n\n#disables the master tap\njtag configure $_TARGETNAME -event tap-disable \"\n\"\n#TODO FIND SMARTER WAY.\n\njtag configure $_CHIPNAME.chp -event tap-disable \"\n\"\n#TODO FIND SMARTER WAY.\n\n\n#working area at base of ram\n$_TARGETNAME configure -work-area-virt 0\n\n#setup flash\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/efm32.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Silicon Labs (formerly Energy Micro) EFM32 target\n#\n# Note: All EFM32 chips have SWD support, but only newer series 1\n# chips have JTAG support.\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME efm32\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 2kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x800\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      set _CPUTAPID 0x4ba00477\n   } {\n      set _CPUTAPID 0x2ba01477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nadapter speed 1000\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME\nflash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME\nflash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/em357.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Target configuration for the Silicon Labs EM357 chips\n#\n\n#\n# em357 family supports JTAG and SWD transports\n#\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME em357\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 4kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x1000\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      set _CPUTAPID 0x3ba00477\n   } else {\n      set _CPUTAPID 0x1ba00477\n   }\n}\n\nif { [info exists BSTAPID] } {\n   set _BSTAPID $BSTAPID\n} else {\n  set _BSTAPID 0x069a962b\n}\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME em358\n}\n\nif { [info exists FLASHSIZE] } {\n    set _FLASHSIZE $FLASHSIZE\n} else {\n    set _FLASHSIZE 0x30000\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\nif { [using_jtag] } {\n    jtag newtap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME em357 0x08000000 $_FLASHSIZE 0 0 $_TARGETNAME\n\nif { ![using_hla]} {\n# according to errata, we need to use vectreset rather than sysresetreq to avoid lockup\n# There is a bug in the chip, which means that when using external debuggers the chip\n# may lock up in certain CPU clock modes. Affected modes are operating the CPU at\n# 24MHz derived from the 24MHz crystal, or 12MHz derived from the high frequency RC\n# oscillator. If an external debugger tool asserts SYSRESETREQ, the chip will lock up and\n# require a pin reset or power cycle.\n#\n# for details, refer to:\n# http://www.silabs.com/Support%20Documents/TechnicalDocs/EM35x-Errata.pdf\n    cortex_m reset_config vectreset\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/em358.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Target configuration for the Silicon Labs EM358 chips\n\n#\n# em357 family supports JTAG and SWD transports\n#\n\nif { ![info exists CHIPNAME] } {\n   set CHIPNAME em358\n}\n\nif { ![info exists BSTAPID] } {\n  set BSTAPID 0x069aa62b\n}\n\n# 512K of flash in the em358 chips\nset FLASHSIZE 0x80000\nsource [find target/em357.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/eos_s3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# QuickLogic EOS S3\n# https://www.quicklogic.com/products/soc/eos-s3-microcontroller/\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME eos_s3\n}\n\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x80000\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      set _CPUTAPID 0x4ba00477\n   } {\n      set _CPUTAPID 0x2ba01477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n# For now we use SRAM only for software upload\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nadapter speed 4000\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/epc9301.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME ep9301\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   # Force an error until we get a good number.\n   set _CPUTAPID 0xffffffff\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\nadapter srst delay 100\njtag_ntrst_delay 100\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1\n\n#flash configuration\n#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cfi 0x60000000 0x1000000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/esi32xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# EnSilica eSi-32xx SoC (eSi-RISC Family)\n# http://www.ensilica.com/risc-ip/\n#\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME esi32xx\n}\n\nif { [info exists CPUTAPID] } {\n    set _CPUTAPID $CPUTAPID\n} else {\n    set _CPUTAPID 0x11234001\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME esirisc -chain-position $_CHIPNAME.cpu\n\n# Targets with the UNIFIED_ADDRESS_SPACE option disabled should set\n# CACHEARCH to 'harvard'. By default, 'von_neumann' is assumed.\nif { [info exists CACHEARCH] } {\n    $_TARGETNAME esirisc cache_arch $CACHEARCH\n}\n\nadapter speed 2000\n\nreset_config none\n\n# The default linker scripts provided by the eSi-RISC toolchain do not\n# specify attributes on memory regions, which results in incorrect\n# application of software breakpoints by GDB.\ngdb_breakpoint_override hard\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/esp32.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n\n# Source the ESP common configuration file.\nsource [find target/esp_common.cfg]\n\n# Target specific global variables\nset _CHIPNAME \t\t\t\t\t\"esp32\"\nset _CPUTAPID \t\t\t\t\t0x120034e5\nset _ESP_ARCH \t\t\t\t\t\"xtensa\"\nset _ONLYCPU\t\t\t\t\t3\nset _FLASH_VOLTAGE \t\t\t\t3.3\nset _ESP_SMP_TARGET\t\t\t\t1\nset _ESP_SMP_BREAK \t\t\t\t1\nset _ESP_EFUSE_MAC_ADDR_REG \t0x3ff5A004\n\nif { [info exists ESP32_ONLYCPU] } {\n\tset _ONLYCPU $ESP32_ONLYCPU\n}\n\nif { [info exists ESP32_FLASH_VOLTAGE] } {\n\tset _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE\n}\n\nproc esp32_memprot_is_enabled { } {\n\treturn 0\n}\n\nproc esp32_soc_reset { } {\n\tsoft_reset_halt\n}\n\ncreate_esp_target $_ESP_ARCH\n\nsource [find target/xtensa-core-esp32.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/esp32s2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n\n# Source the ESP common configuration file.\nsource [find target/esp_common.cfg]\n\n# Target specific global variables\nset _CHIPNAME \t\t\t\t\t\"esp32s2\"\nset _CPUTAPID \t\t\t\t\t0x120034e5\nset _ESP_ARCH\t\t\t\t\t\"xtensa\"\nset _ONLYCPU\t\t\t\t\t1\nset _ESP_SMP_TARGET\t\t\t\t0\nset _ESP_SMP_BREAK \t\t\t\t1\nset _ESP_EFUSE_MAC_ADDR_REG  \t0x3f41A004\n\nproc esp32s2_memprot_is_enabled { } {\n\t# IRAM0, DPORT_PMS_PRO_IRAM0_0_REG\n\tif { [get_mmr_bit 0x3f4c1010 0] != 0 } {\n\t\treturn 1\n\t}\n\t# DRAM0, DPORT_PMS_PRO_DRAM0_0_REG\n\tif { [get_mmr_bit 0x3f4c1028 0] != 0 } {\n\t\treturn 1\n\t}\n\t# PERI1, DPORT_PMS_PRO_DPORT_0_REG\n\tif { [get_mmr_bit 0x3f4c103c 0] != 0 } {\n\t\treturn 1\n\t}\n\t# PERI2, DPORT_PMS_PRO_AHB_0_REG\n\tif { [get_mmr_bit 0x3f4c105c 0] != 0 } {\n\t\treturn 1\n\t}\n\treturn 0\n}\n\nproc esp32s2_soc_reset { } {\n\tsoft_reset_halt\n}\n\ncreate_esp_target $_ESP_ARCH\n\nsource [find target/xtensa-core-esp32s2.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/esp32s3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n\n# Source the ESP common configuration file.\nsource [find target/esp_common.cfg]\n\n# Target specific global variables\nset _CHIPNAME \t\t\t\t\t\"esp32s3\"\nset _CPUTAPID \t\t\t\t\t0x120034e5\nset _ESP_ARCH \t\t\t\t\t\"xtensa\"\nset _ONLYCPU\t\t\t\t\t3\nset _ESP_SMP_TARGET\t\t\t\t1\nset _ESP_SMP_BREAK \t\t\t\t1\nset _ESP_EFUSE_MAC_ADDR_REG  \t0x60007044\n\nif { [info exists ESP32_S3_ONLYCPU] } {\n\tset _ONLYCPU $ESP32_S3_ONLYCPU\n}\n\nproc esp32s3_memprot_is_enabled { } {\n\t# SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG\n\tif { [get_mmr_bit 0x600C10C0 0] != 0 } {\n\t\treturn 1\n\t}\n\t# SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG\n\tif { [get_mmr_bit 0x600C1124 0] != 0 } {\n\t\treturn 1\n\t}\n\t# SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG\n\tif { [get_mmr_bit 0x600C11D0 0] != 0 } {\n\t\treturn 1\n\t}\n\t# IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG\n\tif { [get_mmr_bit 0x600C10D8 0] != 0 } {\n\t\treturn 1\n\t}\n\t# DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG\n\tif { [get_mmr_bit 0x600C10FC 0] != 0 } {\n\t\treturn 1\n\t}\n\t# SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG\n\tif { [get_mmr_bit 0x600C10E4 0] != 0 } {\n\t\treturn 1\n\t}\n\t# SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG\n\tif { [get_mmr_bit 0x600C10F0 0] != 0 } {\n\t\treturn 1\n\t}\n\t# SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG\n\tif { [get_mmr_bit 0x600C1104 0] != 0 } {\n\t\treturn 1\n\t}\n\t# SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG\n\tif { [get_mmr_bit 0x600C1114 0] != 0 } {\n\t\treturn 1\n\t}\n\t# SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG\n\tif { [get_mmr_bit 0x600C119C 0] != 0 } {\n\t\treturn 1\n\t}\n\t# SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG\n\tif { [get_mmr_bit 0x600C1248 0] != 0 } {\n\t\treturn 1\n\t}\n\treturn 0\n}\n\nproc esp32s3_soc_reset { } {\n\tsoft_reset_halt\n}\n\ncreate_esp_target $_ESP_ARCH\n\nsource [find target/xtensa-core-esp32s3.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/esp_common.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n\nset CPU_MAX_ADDRESS 0xFFFFFFFF\nsource [find bitsbytes.tcl]\nsource [find memory.tcl]\nsource [find mmr_helpers.tcl]\n\n# Common ESP chips definitions\n\n# Espressif supports only NuttX in the upstream.\n# FreeRTOS support is not upstreamed yet.\nset _RTOS \"hwthread\"\nif { [info exists ESP_RTOS] } {\n\tset _RTOS \"$ESP_RTOS\"\n}\n\n# by default current dir (when OOCD has been started)\nset _SEMIHOST_BASEDIR \".\"\nif { [info exists ESP_SEMIHOST_BASEDIR] } {\n\tset _SEMIHOST_BASEDIR $ESP_SEMIHOST_BASEDIR\n}\n\nproc set_esp_common_variables { } {\n\tglobal _CHIPNAME _ONLYCPU _ESP_SMP_TARGET\n\tglobal _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1\n\tglobal _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED\n\n\t# For now we support dual core at most.\n\tif { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} {\n\t\tset _TARGETNAME_0 \t\t\t\t$_CHIPNAME\n\t\tset _CPUNAME_0\t\t\t\t\tcpu\n\t\tset _TAPNAME_0 \t\t\t\t\t$_CHIPNAME.$_CPUNAME_0\n\t} else {\n\t\tset _CPUNAME_0 \t\t\t\t\tcpu0\n\t\tset _CPUNAME_1 \t\t\t\t\tcpu1\n\t\tset _TARGETNAME_0 \t\t\t\t$_CHIPNAME.$_CPUNAME_0\n\t\tset _TARGETNAME_1 \t\t\t\t$_CHIPNAME.$_CPUNAME_1\n\t\tset _TAPNAME_0 \t\t\t\t\t$_TARGETNAME_0\n\t\tset _TAPNAME_1 \t\t\t\t\t$_TARGETNAME_1\n\t}\n\n\tset _ESP_WDT_DISABLE \t\t\t\"${_CHIPNAME}_wdt_disable\"\n\tset _ESP_SOC_RESET \t\t\t\t\"${_CHIPNAME}_soc_reset\"\n\tset _ESP_MEMPROT_IS_ENABLED \t\"${_CHIPNAME}_memprot_is_enabled\"\n}\n\nproc create_esp_jtag { } {\n\tglobal _CHIPNAME _CPUNAME_0 _CPUNAME_1 _CPUTAPID _ONLYCPU\n\tjtag newtap $_CHIPNAME $_CPUNAME_0 -irlen 5 -expected-id $_CPUTAPID\n\tif { $_ONLYCPU != 1 } {\n\t\tjtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -expected-id $_CPUTAPID\n\t} elseif [info exists _CPUNAME_1] {\n\t\tjtag newtap $_CHIPNAME $_CPUNAME_1 -irlen 5 -disable -expected-id $_CPUTAPID\n\t}\n}\n\nproc create_openocd_targets  { } {\n\tglobal _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU\n\n\ttarget create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS\n\tif { $_ONLYCPU != 1 } {\n\t\ttarget create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS\n\t\ttarget smp $_TARGETNAME_0 $_TARGETNAME_1\n\t}\n}\n\nproc create_esp_target { ARCH } {\n\tset_esp_common_variables\n\tcreate_esp_jtag\n\tcreate_openocd_targets\n\tconfigure_openocd_events\n\n\tif { $ARCH == \"xtensa\"} {\n\t\tconfigure_esp_xtensa_default_settings\n\t} else {\n\t\t# riscv targets are not upstreamed yet.\n\t\t# they can be found at the official Espressif fork.\n\t}\n}\n\n#################### Set event handlers and default settings  ####################\n\nproc configure_event_examine_end { } {\n\tglobal _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU\n\n\t$_TARGETNAME_0 configure -event examine-end {\n\t\t# Need to enable to set 'semihosting_basedir'\n\t\tarm semihosting enable\n\t\tarm semihosting_resexit enable\n\t\tif { [info exists _SEMIHOST_BASEDIR] } {\n\t\t\tif { $_SEMIHOST_BASEDIR != \"\" } {\n\t\t\t\tarm semihosting_basedir $_SEMIHOST_BASEDIR\n\t\t\t}\n\t\t}\n\t}\n\n\tif { $_ONLYCPU != 1 } {\n\t\t$_TARGETNAME_1 configure -event examine-end {\n\t\t\t# Need to enable to set 'semihosting_basedir'\n\t\t\tarm semihosting enable\n\t\t\tarm semihosting_resexit enable\n\t\t\tif { [info exists _SEMIHOST_BASEDIR] } {\n\t\t\t\tif { $_SEMIHOST_BASEDIR != \"\" } {\n\t\t\t\t\tarm semihosting_basedir $_SEMIHOST_BASEDIR\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc configure_event_reset_assert_post { } {\n\tglobal _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU\n\n\t$_TARGETNAME_0 configure -event reset-assert-post {\n\t\tglobal _ESP_SOC_RESET\n\t\t$_ESP_SOC_RESET\n\t}\n\n\tif { $_ONLYCPU != 1 } {\n\t\t$_TARGETNAME_1 configure -event reset-assert-post {\n\t\t\tglobal _ESP_SOC_RESET\n\t\t\t$_ESP_SOC_RESET\n\t\t}\n\t}\n}\n\nproc configure_event_halted { } {\n\tglobal _TARGETNAME_0\n\n\t$_TARGETNAME_0 configure -event halted {\n\t\tglobal _ESP_WDT_DISABLE\n\t    $_ESP_WDT_DISABLE\n\t    esp halted_event_handler\n\t}\n}\n\nproc configure_event_gdb_attach { } {\n\tglobal _TARGETNAME_0 _TARGETNAME_1 _ONLYCPU\n\n\t$_TARGETNAME_0 configure -event gdb-attach {\n\t\tif { $_ESP_SMP_BREAK != 0 } {\n\t\t\t$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut\n\t\t}\n\t\t# necessary to auto-probe flash bank when GDB is connected and generate proper memory map\n\t\thalt 1000\n\t\tif { [$_ESP_MEMPROT_IS_ENABLED] } {\n\t\t\t# 'reset halt' to disable memory protection and allow flasher to work correctly\n\t\t\techo \"Memory protection is enabled. Reset target to disable it...\"\n\t\t\treset halt\n\t\t}\n\t}\n\n\tif { $_ONLYCPU != 1 } {\n\t\t$_TARGETNAME_1 configure -event gdb-attach {\n\t\t\tif { $_ESP_SMP_BREAK != 0 } {\n\t\t\t\t$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut\n\t\t\t}\n\t\t\t# necessary to auto-probe flash bank when GDB is connected\n\t\t\thalt 1000\n\t\t\tif { [$_ESP_MEMPROT_IS_ENABLED] } {\n\t\t\t\t# 'reset halt' to disable memory protection and allow flasher to work correctly\n\t\t\t\techo \"Memory protection is enabled. Reset target to disable it...\"\n\t\t\t\treset halt\n\t\t\t}\n\t\t}\n\t}\n}\n\nproc configure_openocd_events { } {\n\tconfigure_event_examine_end\n\tconfigure_event_reset_assert_post\n\tconfigure_event_gdb_attach\n}\n\nproc configure_esp_xtensa_default_settings { } {\n\tglobal _TARGETNAME_0 _ESP_SMP_BREAK _FLASH_VOLTAGE _CHIPNAME\n\n\t$_TARGETNAME_0 xtensa maskisr on\n\tif { $_ESP_SMP_BREAK != 0 } {\n\t\t$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut\n\t}\n\n\tgdb_breakpoint_override hard\n\n\tif { [info exists _FLASH_VOLTAGE] } {\n\t\t$_TARGETNAME_0 $_CHIPNAME flashbootstrap $_FLASH_VOLTAGE\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/exynos5250.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Samsung Exynos 5250 - dual-core ARM Cortex-A15\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME exynos5250\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap\ntarget create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap\n\ntarget smp ${_TARGETNAME}0 ${_TARGETNAME}1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/faux.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#Script for faux target - used for testing\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME at91eb40a\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x00000000\n}\n\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n#target configuration\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n#dummy flash driver\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/feroceon.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Marvell Feroceon CPU core\n######################################\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME feroceon\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x20a023d3\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME\n\nreset_config trst_and_srst\nadapter srst delay 200\njtag_ntrst_delay 200\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/fm3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# MB9BF506\n# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME mb9bfxx6\n}\n\nif { [info exists ENDIAN] } {\n\tset _ENDIAN $ENDIAN\n} else {\n\tset _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x4ba00477\n}\n\n# delays on reset lines\nadapter srst delay 100\nif {[using_jtag]} {\n   jtag_ntrst_delay 100\n}\n\n# Fujitsu Cortex-M3 reset configuration\nreset_config trst_only\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n# MB9BF506 has 64kB of SRAM on its main system bus\n$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0\n\n# MB9BF506 has 512kB internal FLASH\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME\n\n# 4MHz / 6 = 666kHz, so use 500\nadapter speed 500\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/fm4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Spansion FM4 (ARM Cortex-M4)\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME fm4\n}\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CPUTAPID] } {\n\tset _CPU_TAPID $CPUTAPID\n} elseif { [using_jtag] } {\n\tset _CPU_TAPID 0x4ba00477\n} else {\n\tset _CPU_TAPID 0x2ba01477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap\n\nadapter speed 500\n\nif {![using_hla]} {\n\tcortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/fm4_mb9bf.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Spansion FM4 MB9BFxxx (ARM Cortex-M4)\n#\n\nsource [find target/fm4.cfg]\n\n# MB9BF566 M/N/R have 32 KB SRAM0\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x8000\n}\n\n$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \\\n                       -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/fm4_s6e2cc.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Spansion FM4 S6E2CC (ARM Cortex-M4)\n#\n\nsource [find target/fm4.cfg]\n\n# S6E2CC8 H/J/L have 96 KB SRAM0\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x18000\n}\n\n$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE}] \\\n                       -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank ${_FLASHNAME}0 fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES\nflash bank ${_FLASHNAME}1 fm4 0x00100000 0 0 0 $_TARGETNAME $CHIPSERIES\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/gd32e23x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for GigaDevice gd32e23x Cortex-M23 Series\n\n# https://www.gigadevice.com/microcontroller/gd32e230c8t6/\n\n#\n# gd32e23x devices support SWD transports only.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME gd32e23x\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 4kB (as found on some GD32E230s)\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x1000\n}\n\n# Allow overriding the Flash bank size\nif { [info exists FLASH_SIZE] } {\n    set _FLASH_SIZE $FLASH_SIZE\n} else {\n    # autodetect size\n    set _FLASH_SIZE 0\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   # this is the SW-DP tap id not the jtag tap id\n   set _CPUTAPID 0x0bf11477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME\n\n# SWD speed (may be updated to higher value in board config file)\nadapter speed 1000\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n    # if srst is not fitted use SYSRESETREQ to\n    # perform a soft reset\n    cortex_m reset_config sysresetreq\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# Debug clock enable\n\t# RCU_APB2EN |= DBGMCUEN\n\tmmw 0x40021018 0x00400000 0\n\n\t# Stop watchdog counters during halt\n\t# DBG_CTL0 |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD\n\tmmw 0x40015804 0x00000307 0\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/gd32vf103.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# GigaDevice GD32VF103 target\n#\n# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/\n#\n\nsource [find mem_helper.tcl]\n\ntransport select jtag\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME gd32vf103\n}\n\n# The smallest RAM size 6kB (GD32VF103C4/T4/R4)\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x1800\n}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME riscv -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME\n\n# DBGMCU_CR register cannot be set in examine-end event as the running RISC-V CPU\n# does not allow the debugger to access memory.\n# Stop watchdogs at least before flash programming.\n$_TARGETNAME configure -event reset-init {\n\t# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP\n\tmmw 0xE0042004 0x00000300 0\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/gp326xxxa.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Support for General Plus GP326XXXA chips\n#\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME gp326xxxa\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x4f1f0f0f\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# Use internal SRAM as a work area\n$_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0\n\n# The chip has both lines connected together\nreset_config trst_and_srst srst_pulls_trst\n# This delay is needed otherwise communication with the target would\n# be unreliable\nadapter srst delay 100\n\n# Set the adapter speed ridiculously low just in case we are\n# running off of a 32kHz clock\nadapter speed 2\n\nproc gp32xxxa_halt_and_reset_control_registers {} {\n\t# System control registers\n\tset P_SYSTEM_CTRL_NEW       0xD0000008\n\tset P_SYSTEM_CTRL           0xD000000C\n\tset P_SYSTEM_CLK_EN0        0xD0000010\n\tset P_SYSTEM_CLK_EN1        0xD0000014\n\tset P_SYSTEM_RESET_FLAG     0xD0000018\n\tset P_SYSTEM_CLK_CTRL       0xD000001C\n\tset P_SYSTEM_LVR_CTRL       0xD0000020\n\tset P_SYSTEM_WATCHDOG_CTRL  0xD0000024\n\tset P_SYSTEM_PLLEN          0xD000005C\n\n\t# Since we can't use SRST without pulling TRST\n\t# we can't assume the state of the clock configuration\n\t# or watchdog settings. So reset them before porceeding\n\n\t# Set the adapter speed ridiculously low just in case we are\n\t# running off of a 32kHz clock\n\tadapter speed 2\n\n\t# Disable any advanced features at this stage\n\tarm7_9 dcc_downloads disable\n\tarm7_9 fast_memory_access disable\n\n\t# Do a \"soft reset\"\n\tsoft_reset_halt\n\t# Reset all system control registers to their default \"after-reset\" values\n\tmwh $P_SYSTEM_WATCHDOG_CTRL  0x0000\n\tmwh $P_SYSTEM_LVR_CTRL       0x0000\n\n\tmwh $P_SYSTEM_CTRL_NEW       0x0001\n\tmwh $P_SYSTEM_CTRL           0x0001\n\t# Clear all reset flags by writing 1's\n\tmwh $P_SYSTEM_RESET_FLAG     0x001C\n\n\tmwh $P_SYSTEM_CLK_CTRL       0x8000\n\tmwh $P_SYSTEM_CLK_EN0        0xFFFF\n\tmwh $P_SYSTEM_CLK_EN1        0xFFFF\n\tmwh $P_SYSTEM_PLLEN          0x0010\n\n\t# Unfortunately there's no register that would allow us to\n\t# know if PLL is locked. So just wait for 100ms in hopes that\n\t# it would be enough.\n\tsleep 100\n\n\t# Now that we know that we are running at 48Mhz\n\t# Increase JTAG speed and enable speed optimization features\n\tadapter speed 5000\n\tarm7_9 dcc_downloads enable\n\tarm7_9 fast_memory_access enable\n}\n\n$_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers }\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/hi3798.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Hisilicon Hi3798 Target\n\nif { [info exists CHIPNAME] } {\n  set _CHIPNAME $CHIPNAME\n} else {\n  set _CHIPNAME hi3798\n}\n\n#\n# Main DAP\n#\nif { [info exists DAP_TAPID] } {\n   set _DAP_TAPID $DAP_TAPID\n} else {\n   set _DAP_TAPID 0x5ba00477\n}\n\n# declare the one JTAG tap to access the DAP\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n# declare the 4 main application cores\nset _TARGETNAME $_CHIPNAME.cpu\nset _smp_command \"\"\n\nset $_TARGETNAME.cti(0) 0x80020000\nset $_TARGETNAME.cti(1) 0x80120000\nset $_TARGETNAME.cti(2) 0x80220000\nset $_TARGETNAME.cti(3) 0x80320000\n\nset _cores 4\nfor { set _core 0 } { $_core < $_cores } { incr _core 1 } {\n\n    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0\n\n    set _command \"target create ${_TARGETNAME}$_core aarch64 \\\n                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core\"\n\n    if { $_core != 0 } {\n        # non-boot core examination may fail\n        #set _command \"$_command -defer-examine\"\n        set _smp_command \"$_smp_command ${_TARGETNAME}$_core\"\n    } else {\n        set _command \"$_command -rtos hwthread\"\n        set _smp_command \"target smp ${_TARGETNAME}$_core\"\n    }\n\n    eval $_command\n}\n\neval $_smp_command\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/hi6220.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Hisilicon Hi6220 Target\n\nif { [info exists CHIPNAME] } {\n  set _CHIPNAME $CHIPNAME\n} else {\n  set _CHIPNAME hi6220\n}\n\n#\n# Main DAP\n#\nif { [info exists DAP_TAPID] } {\n   set _DAP_TAPID $DAP_TAPID\n} else {\n   set _DAP_TAPID 0x4ba00477\n}\n\n# declare the one JTAG tap to access the DAP\njtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version\n\n# create the DAP\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap\n\n# declare the 8 main application cores\nset _TARGETNAME $_CHIPNAME.cpu\nset _smp_command \"\"\n\nset $_TARGETNAME.cti(0) 0x80198000\nset $_TARGETNAME.cti(1) 0x80199000\nset $_TARGETNAME.cti(2) 0x8019A000\nset $_TARGETNAME.cti(3) 0x8019B000\nset $_TARGETNAME.cti(4) 0x801D8000\nset $_TARGETNAME.cti(5) 0x801D9000\nset $_TARGETNAME.cti(6) 0x801DA000\nset $_TARGETNAME.cti(7) 0x801DB000\n\nset _cores 8\nfor { set _core 0 } { $_core < $_cores } { incr _core 1 } {\n\n    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0\n\n    set _command \"target create ${_TARGETNAME}$_core aarch64 \\\n                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core\"\n\n    if { $_core != 0 } {\n        # non-boot core examination may fail\n        set _command \"$_command -defer-examine\"\n        set _smp_command \"$_smp_command ${_TARGETNAME}$_core\"\n    } else {\n        set _command \"$_command -rtos hwthread\"\n        set _smp_command \"target smp ${_TARGETNAME}$_core\"\n    }\n\n    eval $_command\n}\n\neval $_smp_command\n\ncti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80003000\n\n# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin)\ntarget create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine\n\n# declare the auxiliary Cortex-A7 core\ntarget create ${_TARGETNAME}.a7 cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/hilscher_netx10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Author: Michael Trensch (MTrensch@googlemail.com)\n################################################################################\n\n#Hilscher netX 10 CPU\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME netx10\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x25966021\n}\n\n# jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n# that TAP is associated with a target\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/hilscher_netx50.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n################################################################################\n# Author: Michael Trensch (MTrensch@googlemail.com)\n################################################################################\n\n#Hilscher netX 50 CPU\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME netx50\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x25966021\n}\n\n# jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n# that TAP is associated with a target\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# On netX50 SDRAM is not accessible at offset 0xDEAD0-0xDEADF as it is busy from\n# DMA controller at init. This function will setup a dummy DMA to free this ares\n# and must be called before using SDRAM\nproc sdram_fix { } {\n\n  mww 0x1c005830 0x00000001\n\n  mww 0x1c005104 0xBFFFFFFC\n  mww 0x1c00510c 0x00480001\n  mww 0x1c005110 0x00000001\n\n  sleep 100\n\n  mww 0x1c00510c 0\n  mww 0x1c005110 0\n  mww 0x1c005830 0x00000000\n\n\tputs \"SDRAM Fix executed!\"\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/hilscher_netx500.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#Hilscher netX 500 CPU\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME netx500\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07926021\n}\n\n# jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n# that TAP is associated with a target\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n\nproc mread32 {addr} {\n  return [read_memory $addr 32 1]\n}\n\n# This function must be called on netX100/500 right after halt\n# If it is called later the needed register cannot be written anymore\nproc sdram_fix { } {\n\n  set accesskey [mread32 0x00100070]\n  mww 0x00100070 $accesskey\n  mww 0x0010002c 0x00000001\n\n  if {[expr {[mread32 0x0010002c] & 0x07}] == 0x07} {\n\t puts \"SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!\"\n  } else {\n\t puts \"SDRAM Fix succeeded!\"\n  }\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/icepick.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Copyright (C)   2011        by Karl Kurbjun\n# Copyright (C)   2009        by David Brownell\n#\n\n# Utilities for TI ICEpick-C/D used in most TI SoCs\n# Details about the ICEPick are available in the the TRM for each SoC\n# and http://processors.wiki.ti.com/index.php/ICEPICK\n\n# create \"constants\"\nproc CONST { key } {\n\n\tarray set constant {\n\t\t# define ICEPick instructions\n\t\tIR_BYPASS   0x00\n\t\tIR_ROUTER   0x02\n\t\tIR_CONNECT  0x07\n\t\tIF_BYPASS   0x3F\n\t}\n\treturn $constant($key)\n}\n\n# Instruction to connect to the icepick module\nproc icepick_c_connect {jrc} {\n\n\t# Send CONNECT instruction in IR state\n\tirscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE\n\n\t# Send write and connect key\n\tdrscan $jrc 8 0x89 -endstate DRPAUSE\n}\n\n# Instruction to disconnect to the icepick module\nproc icepick_c_disconnect {jrc} {\n\n\t# Send CONNECT instruction in IR state\n\tirscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE\n\n\t# Send write and connect key\n\tdrscan $jrc 8 0x86 -endstate DRPAUSE\n}\n\n#\n# icepick_c_router:\n#  this function is for sending router commands\n# arguments are:\n#  jrc:        TAP name for the ICEpick\n#  rw:         read/write (0 for read, 1 for write)\n#  block:      icepick or DAP\n#  register:   which register to read/write\n#  payload:    value to read/write\n# this function is for sending router commands\n#\nproc icepick_c_router {jrc rw block register payload} {\n\n\tset new_dr_value \\\n\t\t[expr { ( ($rw & 0x1) << 31)        | ( ($block & 0x7) << 28) | \\\n\t\t\t\t( ($register & 0xF) << 24)  | ( $payload & 0xFFFFFF ) } ]\n\n#\techo \"\\tNew router value:\\t0x[format %x $new_dr_value]\"\n\n\t# select router\n\tirscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE\n\n\t# ROUTER instructions are 32 bits wide\n\tset old_dr_value 0x[drscan $jrc 32 $new_dr_value -endstate DRPAUSE]\n#\techo \"\\tOld router value:\\t0x[format %x $old_dr_value]\"\n}\n\n# Configure the icepick control register\nproc icepick_c_setup {jrc} {\n\n\t# send a router write, block is 0, register is 1, value is 0x2100\n\ticepick_c_router $jrc 1 0x0 0x1 0x001000\n}\n\n# jrc\t== TAP name for the ICEpick\n# port\t== a port number, 0..15 for debug tap, 16..31 for test tap\nproc icepick_c_tapenable {jrc port} {\n\n\tif { ($port >= 0) && ($port < 16) } {\n\t\t# Debug tap\"\n\t\tset tap $port\n\t\tset block 0x2\n\t} elseif { $port < 32 } {\n\t\t# Test tap\n\t\tset tap [expr {$port - 16}]\n\t\tset block 0x1\n\t} else {\n\t\techo \"ERROR: Invalid ICEPick C port number: $port\"\n\t\treturn\n\t}\n\n\t# First CONNECT to the ICEPick\n#\techo \"Connecting to ICEPick\"\n\ticepick_c_connect $jrc\n\n#\techo \"Configuring the ICEpick\"\n\ticepick_c_setup $jrc\n\n\t# NOTE: it's important not to enter RUN/IDLE state until\n\t# done sending these instructions and data to the ICEpick.\n\t# And never to enter RESET, which will disable the TAPs.\n\n\t# first enable power and clock for TAP\n\ticepick_c_router $jrc 1 $block $tap 0x110048\n\n\t# TRM states that the register should be read back here, skipped for now\n\n\t# enable debug \"default\" mode\n\ticepick_c_router $jrc 1 $block $tap 0x112048\n\n\t# TRM states that debug enable and debug mode should be read back and\n\t# confirmed - skipped for now\n\n\t# Finally select the tap\n\ticepick_c_router $jrc 1 $block $tap 0x112148\n\n\t# Enter the bypass state\n\tirscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE\n\truntest 10\n}\n\n# jrc\t== TAP name for the ICEpick\n# coreid== core id number 0..15 (not same as port number!)\nproc icepick_d_set_core_control {jrc coreid value } {\n\ticepick_c_router $jrc 1 0x6 $coreid $value\n}\n\n# jrc\t== TAP name for the ICEpick\n# port\t== a port number, 0..15\n# Follow the sequence described in\n# http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf\nproc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {\n\n\t# First CONNECT to the ICEPick\n\ticepick_c_connect $jrc\n\ticepick_c_setup $jrc\n\n\t# Select the port\n\ticepick_c_router $jrc 1 0x2 $port 0x2108\n\n\t# Set icepick core control for $coreid\n\ticepick_d_set_core_control $jrc $coreid $value\n\n\t# Enter the bypass state\n\tirscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE\n\truntest 10\n}\n\n# This function uses the ICEPick to send a warm system reset\nproc icepick_c_wreset {jrc} {\n\n\t# send a router write, block is 0, register is 1, value is 0x2100\n\ticepick_c_router $jrc 1 0x0 0x1 0x002101\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# utility fn's for Freescale i.MX series\n\nglobal TARGETNAME\nset TARGETNAME $_TARGETNAME\n\n# rewrite commands of the form below to arm11 mcr...\n#\tData.Set c15:0x042f %long 0x40000015\nproc setc15 {regs value} {\n\tglobal TARGETNAME\n\n\techo [format \"set p15 0x%04x, 0x%08x\" $regs $value]\n\n\tarm mcr 15 [expr {($regs>>12)&0x7}] [expr {($regs>>0)&0xf}] [expr {($regs>>4)&0xf}] [expr {($regs>>8)&0x7}] $value\n}\n\n\nproc imx3x_reset {} {\n\t# this reset script comes from the Freescale PDK\n\t#\n\t# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK\n\n\techo \"Target Setup: initialize DRAM controller and peripherals\"\n\n#\tData.Set c15:0x01 %long 0x00050078\n\tsetc15 0x01 0x00050078\n\n\techo \"configuring CP15 for enabling the peripheral bus\"\n#\tData.Set c15:0x042f %long 0x40000015\n\tsetc15 0x042f 0x40000015\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx21.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\n#\n# Hmmm.... should srst_pulls_trst be used here like i.MX27???\nreset_config trst_and_srst\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME imx21\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n\n# Note above there is 1 tap\n\n# The CPU tap\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x0792611f\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n\n# Create the GDB Target.\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n\narm7_9 dcc_downloads enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx25.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# imx25 config\n#\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME imx25\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists ETBTAPID] } {\n   set _ETBTAPID $ETBTAPID\n} else {\n   set _ETBTAPID 0x1b900f0f\n}\njtag newtap $_CHIPNAME etb -irlen 4 -irmask 0x0f -expected-id $_ETBTAPID\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07926041\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\n\njtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id 0x0\n\nif { [info exists SDMATAPID] } {\n   set _SDMATAPID $SDMATAPID\n} else {\n   set _SDMATAPID 0x0882301d\n}\njtag newtap $_CHIPNAME sdma -irlen 5 -expected-id $_SDMATAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN \\\n\t\t-chain-position $_TARGETNAME\n\n# trace setup\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx27.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# page 3-34 of \"MCIMC27 Multimedia Applications Processor Reference Manual, Rev 0.3\"\n# SRST pulls TRST\n#\n# Without setting these options correctly you'll see all sorts\n# of weird errors, e.g. MOE=0xe, invalid cpsr values, reset\n# failing, etc.\nreset_config trst_and_srst srst_pulls_trst\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME imx27\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n\n# Note above there are 2 taps\n\n# trace buffer\nif { [info exists ETBTAPID] } {\n   set _ETBTAPID $ETBTAPID\n} else {\n   set _ETBTAPID 0x1b900f0f\n}\njtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID\n\n# The CPU tap\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07926121\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n# Create the GDB Target.\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n# REVISIT what operating environment sets up this virtual address mapping?\n$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \\\n\t-work-area-size 0x8000 -work-area-backup 1\n# Internal to the chip, there is 45K of SRAM\n#\n\narm7_9 dcc_downloads enable\n\n# trace setup\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx28.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# i.MX28 config file.\n# based off of the imx21.cfg file.\n\nreset_config trst_and_srst\n\n#jtag nTRST and nSRST delay\nadapter srst delay 100\njtag_ntrst_delay 100\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME imx28\n}\n\nif { [info exists ENDIAN] } {\n   set  _ENDIAN $ENDIAN\n} else {\n   set  _ENDIAN little\n}\n\n\n# Note above there is 1 tap\n\n# The CPU tap\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x079264f3\n}\njtag newtap $_CHIPNAME cpu  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n\n# Create the GDB Target.\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n\narm7_9 dcc_downloads enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx31.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# imx31 config\n#\n\nreset_config trst_and_srst srst_gates_jtag\n\nadapter srst delay 5\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME imx31\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07b3601d\n}\n\nif { [info exists SDMATAPID] } {\n   set _SDMATAPID $SDMATAPID\n} else {\n   set _SDMATAPID 0x2190101d\n}\n\nif { [info exists ETBTAPID] } {\n   set _ETBTAPID $ETBTAPID\n} else {\n   set _ETBTAPID 0x2b900f0f\n}\n\n#========================================\n\njtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID\n\n# The \"SDMA\" - <S>mart <DMA> controller debug tap\n# Based on some IO pins - this can be disabled & removed\n# See diagram: 6-14\n#   SIGNAL NAME:\n#    SJC_MOD - controls multiplexer - disables ARM1136\n#    SDMA_BYPASS - disables SDMA    -\n#\n# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID\n\n# No IDCODE for this TAP\njtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0\n\n# Per section 40.17.1, table 40-85 the IR register is 4 bits\n# But this conflicts with Diagram 6-13, \"3bits ir and drs\"\njtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME\n\n\nproc power_restore {} { echo \"Sensed power restore. No action.\" }\nproc srst_deasserted {} { echo \"Sensed nSRST deasserted. No action.\" }\n\n# trace setup ... NOTE, \"normal full\" mode fudges the real ETMv3.1 mode\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx35.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# imx35 config\n#\n\nreset_config trst_and_srst srst_gates_jtag\njtag_ntrst_delay 100\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME imx35\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07b3601d\n}\n\nif { [info exists SDMATAPID] } {\n   set _SDMATAPID $SDMATAPID\n} else {\n   set _SDMATAPID 0x0882601d\n}\n\nif { [info exists ETBTAPID] } {\n   set _ETBTAPID $ETBTAPID\n} else {\n   set _ETBTAPID 0x2b900f0f\n}\n\n#========================================\n\njtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID\n\n# No IDCODE for this TAP\njtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0\n\njtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME\n\nproc power_restore {} { echo \"Sensed power restore. No action.\" }\nproc srst_deasserted {} { echo \"Sensed nSRST deasserted. No action.\" }\n\n# trace setup ... NOTE, \"normal full\" mode fudges the real ETMv3.1 mode\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx51.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Freescale i.MX51\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME imx51\n}\n\n# CoreSight Debug Access Port\nif { [info exists DAP_TAPID] } {\n   set _DAP_TAPID $DAP_TAPID\n} else {\n   set _DAP_TAPID 0x1ba00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \\\n        -expected-id $_DAP_TAPID\n\n# SDMA / no IDCODE\njtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf\n\n# SJC\nif { [info exists SJC_TAPID] } {\n   set _SJC_TAPID SJC_TAPID\n} else {\n   set _SJC_TAPID 0x0190c01d\n}\n\njtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \\\n        -expected-id $_SJC_TAPID -ignore-version\n\n# GDB target: Cortex-A8, using DAP\nset _TARGETNAME $_CHIPNAME.cpu\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap\n\n# some TCK tycles are required to activate the DEBUG power domain\njtag configure $_CHIPNAME.sjc -event post-reset \"runtest 100\"\n\nproc imx51_dbginit {target} {\n     # General Cortex-A8 debug initialisation\n     cortex_a dbginit\n}\n\n$_TARGETNAME configure -event reset-assert-post \"imx51_dbginit $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx53.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Freescale i.MX53\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME imx53\n}\n\n# CoreSight Debug Access Port\nif { [info exists DAP_TAPID] } {\n   set _DAP_TAPID $DAP_TAPID\n} else {\n   set _DAP_TAPID 0x1ba00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \\\n        -expected-id $_DAP_TAPID\n\n# SDMA / no IDCODE\njtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf\n\n# SJC\nif { [info exists SJC_TAPID] } {\n   set _SJC_TAPID SJC_TAPID\n} else {\n   set _SJC_TAPID 0x0190d01d\n}\n\njtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \\\n        -expected-id $_SJC_TAPID -ignore-version\n\n# GDB target: Cortex-A8, using DAP\nset _TARGETNAME $_CHIPNAME.cpu\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap\n\n# some TCK tycles are required to activate the DEBUG power domain\njtag configure $_CHIPNAME.sjc -event post-reset \"runtest 100\"\n\nproc imx53_dbginit {target} {\n     # General Cortex-A8 debug initialisation\n     cortex_a dbginit\n}\n\n$_TARGETNAME configure -event reset-assert-post \"imx53_dbginit $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx6.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale i.MX6 series\n#\n# Supports 6Q 6D 6QP 6DP 6DL 6S 6SL 6SLL\n#\n# Some imx6 chips have Cortex-A7 or an Cortex-M and need special handling\n#\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME imx6\n}\n\n# CoreSight Debug Access Port\nif { [info exists DAP_TAPID] } {\n    set _DAP_TAPID $DAP_TAPID\n} else {\n    set _DAP_TAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\n\n# SDMA / no IDCODE\njtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f\n\n# System JTAG Controller\n\n# List supported SJC TAPIDs from imx reference manuals:\nset _SJC_TAPID_6Q   0x0191c01d\nset _SJC_TAPID_6D   0x0191e01d\nset _SJC_TAPID_6QP  0x3191c01d\nset _SJC_TAPID_6DP  0x3191d01d\nset _SJC_TAPID_6DL  0x0891a01d\nset _SJC_TAPID_6S   0x0891b01d\nset _SJC_TAPID_6SL  0x0891f01d\nset _SJC_TAPID_6SLL 0x088c201d\n\n# Allow external override of the first SJC TAPID\nif { [info exists SJC_TAPID] } {\n    set _SJC_TAPID $SJC_TAPID\n} else {\n    set _SJC_TAPID $_SJC_TAPID_6Q\n}\n\njtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \\\n        -ignore-version \\\n        -expected-id $_SJC_TAPID \\\n        -expected-id $_SJC_TAPID_6QP \\\n        -expected-id $_SJC_TAPID_6DP \\\n        -expected-id $_SJC_TAPID_6D \\\n        -expected-id $_SJC_TAPID_6DL \\\n        -expected-id $_SJC_TAPID_6S \\\n        -expected-id $_SJC_TAPID_6SL \\\n        -expected-id $_SJC_TAPID_6SLL\n\n# GDB target: Cortex-A9, using DAP, configuring only one core\n# Base addresses of cores:\n# core 0  -  0x82150000\n# core 1  -  0x82152000\n# core 2  -  0x82154000\n# core 3  -  0x82156000\nset _TARGETNAME $_CHIPNAME.cpu.0\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \\\n        -coreid 0 -dbgbase 0x82150000\n\n# some TCK cycles are required to activate the DEBUG power domain\njtag configure $_CHIPNAME.sjc -event post-reset \"runtest 100\"\n\nproc imx6_dbginit {target} {\n        # General Cortex-A8/A9 debug initialisation\n        cortex_a dbginit\n}\n\n# Slow speed to be sure it will work\nadapter speed 1000\n$_TARGETNAME configure -event reset-start { adapter speed 1000 }\n\n$_TARGETNAME configure -event reset-assert-post \"imx6_dbginit $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx6sx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale i.MX6SoloX\n#\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME imx6sx\n}\n\n# 2x CoreSight Debug Access Port for Cortex-M4 and Cortex-A9\nif { [info exists DAP_TAPID] } {\n    set _DAP_TAPID $DAP_TAPID\n} else {\n    set _DAP_TAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu_m4 -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\ndap create $_CHIPNAME.dap_m4 -chain-position $_CHIPNAME.cpu_m4\n\njtag newtap $_CHIPNAME cpu_a9 -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\ndap create $_CHIPNAME.dap_a9 -chain-position $_CHIPNAME.cpu_a9\n\n# SDMA / no IDCODE\njtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f\n\n# System JTAG Controller\nif { [info exists SJC_TAPID] } {\n    set _SJC_TAPID $SJC_TAPID\n} else {\n    set _SJC_TAPID 0x0891c01d\n}\njtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \\\n        -expected-id $_SJC_TAPID -ignore-version\n\n# Cortex-A9 (boot core)\ntarget create $_CHIPNAME.cpu_a9 cortex_a -dap $_CHIPNAME.dap_a9 \\\n        -coreid 0 -dbgbase 0x82150000\n\n# Cortex-M4 (default off)\ntarget create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap_m4 \\\n        -ap-num 0 -defer-examine\n\n# AHB mem-ap target\ntarget create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap_a9 -ap-num 0\n\n# Default target is Cortex-A9\ntargets $_CHIPNAME.cpu_a9\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx6ul.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale i.MX6UltraLite series: 6UL 6ULL 6ULZ\n#\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME imx6ul\n}\n\n# CoreSight Debug Access Port\nif { [info exists DAP_TAPID] } {\n    set _DAP_TAPID $DAP_TAPID\n} else {\n    set _DAP_TAPID 0x4ba00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\n\n# SDMA / no IDCODE\njtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f\n\n# System JTAG Controller\nset _SJC_TAPID_6UL  0x0891d01d\nset _SJC_TAPID_6ULL 0x0891e01d\nset _SJC_TAPID_6ULZ 0x1891e01d\n\n# Allow external override of the first SJC TAPID\nif { [info exists SJC_TAPID] } {\n    set _SJC_TAPID $SJC_TAPID\n} else {\n    set _SJC_TAPID $_SJC_TAPID_6UL\n}\n\njtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \\\n        -ignore-version \\\n        -expected-id $_SJC_TAPID \\\n        -expected-id $_SJC_TAPID_6ULL \\\n        -expected-id $_SJC_TAPID_6ULZ \\\n\n# Create DAP\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# Main AHB bus\ntarget create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0\n\n# Cortex-A7 single core\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x82130000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx7.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME imx7\n}\n\n# CoreSight Debug Access Port\nif { [info exists DAP_TAPID] } {\n        set _DAP_TAPID $DAP_TAPID\n} else {\n        set _DAP_TAPID 0x5ba00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\n\n#\n# Cortex-A7 target\n#\n# GDB target: Cortex-A7, using DAP, configuring only one core\n# Base addresses of cores:\n# core 0  -  0x80070000\n# core 1  -  0x80072000\nset _TARGETNAME $_CHIPNAME.cpu_a7\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap \\\n        -coreid 0 -dbgbase 0x80070000\n\ntarget create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap \\\n        -coreid 1 -dbgbase 0x80072000 -defer-examine\n#\n# Cortex-M4 target\n#\nset _TARGETNAME_2 $_CHIPNAME.cpu_m4\ntarget create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.dap -ap-num 4 \\\n        -defer-examine\n\n#\n# AHB mem-ap target\n#\ntarget create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0\n\ntargets $_TARGETNAME.0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx7ulp.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP i.MX7ULP: Cortex-A7 + Cortex-M4\n#\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME imx7ulp\n}\n\n# CoreSight Debug Access Port\nif { [info exists DAP_TAPID] } {\n    set _DAP_TAPID $DAP_TAPID\n} else {\n    # TAPID is from FreeScale!\n    set _DAP_TAPID 0x188e101d\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# Cortex-A7\ntarget create $_CHIPNAME.cpu_a7 cortex_a -dap $_CHIPNAME.dap \\\n        -coreid 0 -dbgbase 0x80030000\n\n# Cortex-M4\n# Boots by default so don't defer examination\ntarget create $_CHIPNAME.cpu_m4 cortex_m -dap $_CHIPNAME.dap -ap-num 3\n\n# AHB main soc bus\ntarget create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0\n\n# Default is Cortex-A7\ntargets $_CHIPNAME.cpu_a7\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx8m.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# configuration file for NXP i.MX8M family of SoCs\n#\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME imx8m\n}\n\nif { [info exists CHIPCORES] } {\n    set _cores $CHIPCORES\n} else {\n    set _cores 1\n}\n\n# CoreSight Debug Access Port\nif { [info exists DAP_TAPID] } {\n        set _DAP_TAPID $DAP_TAPID\n} else {\n        set _DAP_TAPID 0x5ba00477\n}\n\n# the DAP tap\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.a53\nset _CTINAME $_CHIPNAME.cti\n\nset DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}\nset CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}\n\nfor { set _core 0 } { $_core < $_cores } { incr _core } {\n\n    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \\\n        -baseaddr [lindex $CTIBASE $_core]\n\n    set _command \"target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \\\n        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core\"\n\n    if { $_core != 0 } {\n        # non-boot core examination may fail\n        set _command \"$_command -defer-examine\"\n        set _smp_command \"$_smp_command $_TARGETNAME.$_core\"\n    } else {\n        set _command \"$_command -rtos hwthread\"\n        set _smp_command \"target smp $_TARGETNAME.$_core\"\n    }\n\n    eval $_command\n}\n\neval $_smp_command\n\n# declare the auxiliary Cortex-M4 core on AP #4\ntarget create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \\\n               -defer-examine\n\n# AHB-AP for direct access to soc bus\ntarget create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0\n\n# default target is A53 core 0\ntargets $_TARGETNAME.0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/imx8qm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP i.MX8QuadMax\n#\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME imx8qm\n}\n\n# CoreSight Debug Access Port (DAP)\nif { [info exists DAP_TAPID] } {\n    set _DAP_TAPID $DAP_TAPID\n} else {\n    # TAPID is from FreeScale!\n    set _DAP_TAPID 0x1890101d\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \\\n        -expected-id $_DAP_TAPID\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# AXI: Main SOC bus on AP #0\ntarget create ${_CHIPNAME}.axi mem_ap -dap ${_CHIPNAME}.dap -ap-num 0\n\n# 4x Cortex-A53 on AP #6\nset _A53_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}\nset _A53_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}\n\ncti create $_CHIPNAME.a53_cti.0 -dap $_CHIPNAME.dap \\\n            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 0]\ncti create $_CHIPNAME.a53_cti.1 -dap $_CHIPNAME.dap \\\n            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 1]\ncti create $_CHIPNAME.a53_cti.2 -dap $_CHIPNAME.dap \\\n            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 2]\ncti create $_CHIPNAME.a53_cti.3 -dap $_CHIPNAME.dap \\\n            -ap-num 6 -baseaddr [lindex $_A53_CTIBASE 3]\ntarget create $_CHIPNAME.a53.0 aarch64 -dap $_CHIPNAME.dap \\\n            -cti $_CHIPNAME.a53_cti.0 -dbgbase [lindex $_A53_DBGBASE 0]\ntarget create $_CHIPNAME.a53.1 aarch64 -dap $_CHIPNAME.dap \\\n            -cti $_CHIPNAME.a53_cti.1 -dbgbase [lindex $_A53_DBGBASE 1] -defer-examine\ntarget create $_CHIPNAME.a53.2 aarch64 -dap $_CHIPNAME.dap \\\n            -cti $_CHIPNAME.a53_cti.2 -dbgbase [lindex $_A53_DBGBASE 2] -defer-examine\ntarget create $_CHIPNAME.a53.3 aarch64 -dap $_CHIPNAME.dap \\\n            -cti $_CHIPNAME.a53_cti.3 -dbgbase [lindex $_A53_DBGBASE 3] -defer-examine\n\n# 2x Cortex-A72 on AP #6\nset _A72_DBGBASE {0x80210000 0x80310000}\nset _A72_CTIBASE {0x80220000 0x80220000}\n\ncti create $_CHIPNAME.a72_cti.0 -dap $_CHIPNAME.dap \\\n            -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 0]\ncti create $_CHIPNAME.a72_cti.1 -dap $_CHIPNAME.dap \\\n            -ap-num 6 -baseaddr [lindex $_A72_CTIBASE 1]\ntarget create $_CHIPNAME.a72.0 aarch64 -dap $_CHIPNAME.dap \\\n            -cti $_CHIPNAME.a72_cti.0 -dbgbase [lindex $_A72_DBGBASE 0] -defer-examine\ntarget create $_CHIPNAME.a72.1 aarch64 -dap $_CHIPNAME.dap \\\n            -cti $_CHIPNAME.a72_cti.1 -dbgbase [lindex $_A72_DBGBASE 1] -defer-examine\n\n# All Cortex-A in SMP\ntarget smp \\\n        $_CHIPNAME.a53.0 \\\n        $_CHIPNAME.a53.1 \\\n        $_CHIPNAME.a53.2 \\\n        $_CHIPNAME.a53.3 \\\n        $_CHIPNAME.a72.0 \\\n        $_CHIPNAME.a72.1\n\n# SCU: Cortex-M4 core\n# always running imx SC firmware\ntarget create ${_CHIPNAME}.scu cortex_m -dap ${_CHIPNAME}.dap -ap-num 1\n\n# AHB from SCU perspective\ntarget create ${_CHIPNAME}.scu_ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 4\n\n# Cortex-M4 M4_0 core on AP #2 (default off)\ntarget create ${_CHIPNAME}.m4_0 cortex_m -dap ${_CHIPNAME}.dap -ap-num 2 \\\n        -defer-examine\n\n# Cortex-M4 M4_1 core on AP #3 (default off)\ntarget create ${_CHIPNAME}.m4_1 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3 \\\n        -defer-examine\n\n# Debug APB bus\ntarget create ${_CHIPNAME}.apb mem_ap -dap ${_CHIPNAME}.dap -ap-num 6\n\n# Default target is boot core a53.0\ntargets $_CHIPNAME.a53.0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/infineon/tle987x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon TLE987x family (Arm Cortex-M3 @ up to 40 MHz)\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME tle987x\n}\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CPU_SWD_TAPID] } {\n\tset _CPU_SWD_TAPID $CPU_SWD_TAPID\n} else {\n\tset _CPU_SWD_TAPID 0x2BA01477\n}\n\nif { [using_jtag] } {\n\t# JTAG not supported, only SWD\n\tset _CPU_TAPID 0\n} else {\n\tset _CPU_TAPID $_CPU_SWD_TAPID\n}\n\nswj_newdap $_CHIPNAME dap -irlen 4 -expected-id $_CPU_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\nif { ![using_hla] } {\n\tcortex_m reset_config sysresetreq\n}\n\nadapter speed 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/is5114.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for Insilica IS-5114\n# AKA: Atmel AT76C114 - an ARM946 chip\n# ATMEL sold his product line to Insilica...\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME is5114\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n  # this defaults to a little endian\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   # Force an error until we get a good number.\n   set _CPUTAPID 0xffffffff\n}\n\n# jtag speed. We need to stick to 16kHz until we've finished reset.\nadapter speed 16\n\nreset_config trst_and_srst\n\n# Do not specify a tap id here...\njtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1\n# This is the \"arm946\" chip.\njtag newtap $_CHIPNAME cpu      -irlen 4 -ircapture 0x0e -irmask 0xf\njtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1\n\n\n#arm946e-s and\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-start { adapter speed 16 }\n$_TARGETNAME configure -event reset-init {\n\t# We can increase speed now that we know the target is halted.\n\tadapter speed 3000\n}\n$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ixp42x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#xscale ixp42x CPU\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME ixp42x\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n  # this defaults to a bigendian\n   set _ENDIAN big\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x19274013\n}\nset _CPUTAPID2 0x19275013\nset _CPUTAPID3 0x19277013\nset _CPUTAPID4 0x29274013\nset _CPUTAPID5 0x29275013\nset _CPUTAPID6 0x29277013\n\njtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME\n\n\n# register constants for IXP42x SDRAM controller\nglobal IXP425_SDRAM_IR_MODE_SET_CAS2_CMD\nglobal IXP425_SDRAM_IR_MODE_SET_CAS3_CMD\nset IXP425_SDRAM_IR_MODE_SET_CAS2_CMD\t0x0000\nset IXP425_SDRAM_IR_MODE_SET_CAS3_CMD\t0x0001\n\nglobal IXP42x_SDRAM_CL3\nglobal IXP42x_SDRAM_CL2\nset IXP42x_SDRAM_CL3\t\t\t0x0008\nset IXP42x_SDRAM_CL2\t\t\t0x0000\n\nglobal IXP42x_SDRAM_8MB_2Mx32_1BANK\nglobal IXP42x_SDRAM_16MB_2Mx32_2BANK\nglobal IXP42x_SDRAM_16MB_4Mx16_1BANK\nglobal IXP42x_SDRAM_32MB_4Mx16_2BANK\nglobal IXP42x_SDRAM_32MB_8Mx16_1BANK\nglobal IXP42x_SDRAM_64MB_8Mx16_2BANK\nglobal IXP42x_SDRAM_64MB_16Mx16_1BANK\nglobal IXP42x_SDRAM_128MB_16Mx16_2BANK\nglobal IXP42x_SDRAM_128MB_32Mx16_1BANK\nglobal IXP42x_SDRAM_256MB_32Mx16_2BANK\n\nset IXP42x_SDRAM_8MB_2Mx32_1BANK\t0x0030\nset IXP42x_SDRAM_16MB_2Mx32_2BANK\t0x0031\nset IXP42x_SDRAM_16MB_4Mx16_1BANK\t0x0032\nset IXP42x_SDRAM_32MB_4Mx16_2BANK\t0x0033\nset IXP42x_SDRAM_32MB_8Mx16_1BANK\t0x0010\nset IXP42x_SDRAM_64MB_8Mx16_2BANK\t0x0011\nset IXP42x_SDRAM_64MB_16Mx16_1BANK\t0x0012\nset IXP42x_SDRAM_128MB_16Mx16_2BANK\t0x0013\nset IXP42x_SDRAM_128MB_32Mx16_1BANK\t0x0014\nset IXP42x_SDRAM_256MB_32Mx16_2BANK\t0x0015\n\n\n# helper function to init SDRAM on IXP42x.\n# SDRAM_CFG: one of IXP42X_SDRAM_xxx\n# REFRESH: refresh counter reload value (integer)\n# CASLAT: 2 or 3\nproc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {\n\n    switch $CASLAT {\n\t2 {\n\t    set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL2} ]\n\t    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD\n\t}\n\t3 {\n\t    set SDRAM_CFG [expr {$SDRAM_CFG | $::IXP42x_SDRAM_CL3} ]\n\t    set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD\n\t}\n\tdefault { error [format \"unsupported cas latency \\\"%s\\\" \" $CASLAT] }\n    }\n    echo [format \"\\tIXP42x SDRAM Config: 0x%x, Refresh %d \" $SDRAM_CFG $REFRESH]\n\n    mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3\n    mww 0xCC000004          0 ;# disable refresh\n    mww 0xCC000008          3 ;# NOP\n    sleep 100\n    mww 0xCC000004   $REFRESH ;# set refresh counter\n    mww 0xCC000008          2 ;# Precharge All Banks\n    sleep 100\n    mww 0xCC000008          4 ;# Auto Refresh\n    mww 0xCC000008          4 ;# Auto Refresh\n    mww 0xCC000008          4 ;# Auto Refresh\n    mww 0xCC000008          4 ;# Auto Refresh\n    mww 0xCC000008          4 ;# Auto Refresh\n    mww 0xCC000008          4 ;# Auto Refresh\n    mww 0xCC000008          4 ;# Auto Refresh\n    mww 0xCC000008          4 ;# Auto Refresh\n    mww 0xCC000008    $CASCMD ;# Mode Select CL2/CL3\n}\n\nproc ixp42x_set_bigendian { } {\n    reg XSCALE_CTRL 0xF8\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/k1921vk01t.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# K1921VK01T\n# http://niiet.ru/chips/nis?id=354\n\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME k1921vk01t\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x10000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      set _CPUTAPID 0x4ba00477\n   } {\n      # SWD IDCODE\n      set _CPUTAPID 0x2ba01477\n   }\n}\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nflash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME\n\nadapter speed 2000\n\nadapter srst delay 100\nif {[using_jtag]} {\n   jtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/k40.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale Kinetis K40 devices\n#\n\nset CHIPNAME k40\nsource [find target/kx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/k60.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale Kinetis K60 devices\n#\n\nset CHIPNAME k60\nsource [find target/kx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ke0x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale Kinetis KE0x and KEAx series devices\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME ke\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 1kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x400\n}\n\nif { [info exists CPUTAPID] } {\n    set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x0bc11477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME\n\nadapter speed 1000\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n\n   # It is important that \"kinetis_ke mdm check_security\" is called for\n   # 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start'\n   # causes \"kinetis_ke mdm check_security\" to fail the first time openocd\n   # calls it when it tries to connect after the CPU has been power-cycled.\n   $_CHIPNAME.cpu configure -event examine-end {\n      kinetis_ke mdm check_security\n   }\n\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ke1xf.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP (Freescale) Kinetis KE1xF devices\n#\n\nset CHIPNAME ke\n\nsource [find target/kx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ke1xz.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP (Freescale) Kinetis KE1xZ devices\n#\n\nset CHIPNAME ke\n\nsource [find target/klx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/kl25.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale Kinetis KL25 devices\n#\n\nset CHIPNAME kl25\nsource [find target/klx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/kl46.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale Kinetis KL46 devices\n#\n\nset CHIPNAME kl46\nsource [find target/klx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/klx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP (former Freescale) Kinetis KL series devices\n# Also used for Cortex-M0+ equipped members of KVx and KE1xZ series\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME klx\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 1KiB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x400\n}\n\nif { [info exists CPUTAPID] } {\n    set _CPUTAPID $CPUTAPID\n} else {\n    set _CPUTAPID 0x0bc11477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.pflash\nflash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME\nkinetis create_banks\n\n# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual\n# specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;\n# Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.\nadapter speed 1000\n\nreset_config srst_nogate\n\nif {[using_hla]} {\n   echo \"\"\n   echo \"!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!\"\n   echo \" Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions.\"\n   echo \" A high level adapter (like a ST-Link) you are currently using cannot access\"\n   echo \" the MDM-AP, so commands like 'mdm mass_erase' are not available in your\"\n   echo \" configuration. Also security locked state of the device will not be reported.\"\n   echo \"\"\n   echo \" Be very careful as you can lock the device though there is no way to unlock\"\n   echo \" it without mass erase. Don't set write protection on the first block.\"\n   echo \"!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!\"\n   echo \"\"\n} else {\n   # Detect secured MCU\n   $_TARGETNAME configure -event examine-fail {\n      kinetis mdm check_security\n   }\n\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\n# Disable watchdog not to disturb OpenOCD algorithms running on MCU\n# (e.g. armv7m_checksum_memory() in verify_image)\n# Flash driver also disables watchdog before FTFA flash programming.\n$_TARGETNAME configure -event reset-init {\n   kinetis disable_wdog\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ks869x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# ARM920T CPU\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME ks869x\n}\n\nif { [info exists ENDIAN] } {\n   set  _ENDIAN $ENDIAN\n} else {\n   set  _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set  _CPUTAPID $CPUTAPID\n} else {\n   set  _CPUTAPID 0x00922f0f\n}\n\nadapter speed 6000\n\n# jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0\n\n# speed up memory downloads\narm7_9 fast_memory_access enable\narm7_9 dcc_downloads enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/kx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP (former Freescale) Kinetis Kx series devices\n# Also used for Cortex-M4 equipped members of KVx and KE1xF series\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME kx\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 4kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x1000\n}\n\nif { [info exists CPUTAPID] } {\n    set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      set _CPUTAPID 0x4ba00477\n   } {\n      set _CPUTAPID 0x2ba01477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.pflash\nflash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME\nkinetis create_banks\n\nadapter speed 1000\n\nreset_config srst_nogate\n\nif {[using_hla]} {\n   echo \"\"\n   echo \"!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!\"\n   echo \" Kinetis MCUs have a MDM-AP dedicated mainly to MCU security related functions.\"\n   echo \" A high level adapter (like a ST-Link) you are currently using cannot access\"\n   echo \" the MDM-AP, so commands like 'mdm mass_erase' are not available in your\"\n   echo \" configuration. Also security locked state of the device will not be reported.\"\n   echo \" Expect problems connecting to a blank device without boot ROM.\"\n   echo \"\"\n   echo \" Be very careful as you can lock the device though there is no way to unlock\"\n   echo \" it without mass erase. Don't set write protection on the first block.\"\n   echo \"!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!\"\n   echo \"\"\n} else {\n   # Detect secured MCU or boot lock-up in RESET/WDOG loop\n   $_TARGETNAME configure -event examine-fail {\n      kinetis mdm check_security\n   }\n   # During RESET/WDOG loop the target is sometimes falsely examined\n   $_TARGETNAME configure -event examine-end {\n      kinetis mdm check_security\n   }\n\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\n# Disable watchdog not to disturb OpenOCD algorithms running on MCU\n# (e.g. armv7m_checksum_memory() in verify_image)\n# Flash driver also disables watchdog before FTFA flash programming.\n$_TARGETNAME configure -event reset-init {\n   kinetis disable_wdog\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc11xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC11xx Cortex-M0 with at least 1kB SRAM\nset CHIPNAME lpc11xx\nset CHIPSERIES lpc1100\nif { ![info exists WORKAREASIZE] } {\n\tset WORKAREASIZE 0x400\n}\n\nsource [find target/lpc1xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc12xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC12xx Cortex-M0 with at least 4kB SRAM\nset CHIPNAME lpc12xx\nset CHIPSERIES lpc1200\nif { ![info exists WORKAREASIZE] } {\n\tset WORKAREASIZE 0x1000\n}\n\nsource [find target/lpc1xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc13xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC13xx Cortex-M3 with at least 4kB SRAM\nset CHIPNAME lpc13xx\nset CHIPSERIES lpc1300\nif { ![info exists WORKAREASIZE] } {\n\tset WORKAREASIZE 0x1000\n}\n\nsource [find target/lpc1xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc17xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC17xx Cortex-M3 with at least 8kB SRAM\nset CHIPNAME lpc17xx\nset CHIPSERIES lpc1700\nif { ![info exists WORKAREASIZE] } {\n\tset WORKAREASIZE 0x2000\n}\n\nsource [find target/lpc1xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc1850.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/swj-dp.tcl]\n\nadapter speed 500\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME lpc1850\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n#\n# M3 JTAG mode TAP\n#\nif { [info exists M3_JTAG_TAPID] } {\n   set _M3_JTAG_TAPID $M3_JTAG_TAPID\n} else {\n   set _M3_JTAG_TAPID 0x4ba00477\n}\n\nswj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.m3\n\nset _TARGETNAME $_CHIPNAME.m3\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc1xxx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts\n#\n# !!!!!!\n#\n# This file should not be included directly, rather by the lpc11xx.cfg,\n# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the\n# appropriate values.\n#\n# !!!!!!\n\n# LPC8xx chips support only SWD transport.\n# LPC11xx chips support only SWD transport.\n# LPC12xx chips support only SWD transport.\n# LPC11Uxx chips support only SWD transports.\n# LPC13xx chips support only SWD transports.\n# LPC17xx chips support both JTAG and SWD transports.\n# LPC40xx chips support both JTAG and SWD transports.\n# Adapt based on what transport is active.\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\terror \"CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc).\"\n}\n\nif { [info exists CHIPSERIES] } {\n\t# Validate chip series is supported\n\tif { $CHIPSERIES != \"lpc800\" && $CHIPSERIES != \"lpc1100\" && $CHIPSERIES != \"lpc1200\" && $CHIPSERIES != \"lpc1300\" && $CHIPSERIES != \"lpc1700\"  && $CHIPSERIES != \"lpc4000\" } {\n\t\terror \"Unsupported LPC1xxx chip series specified.\"\n\t}\n\tset _CHIPSERIES $CHIPSERIES\n} else {\n\terror \"CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc).\"\n}\n\n# After reset, the chip is clocked by an internal RC oscillator.\n# When board-specific code (reset-init handler or device firmware)\n# configures another oscillator and/or PLL0, set CCLK to match; if\n# you don't, then flash erase and write operations may misbehave.\n# (The ROM code doing those updates cares about core clock speed...)\n# CCLK is the core clock frequency in KHz\nif { [info exists CCLK] } {\n\t# Allow user override\n\tset _CCLK $CCLK\n} else {\n\t# LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)\n\tif { $_CHIPSERIES == \"lpc800\" || $_CHIPSERIES == \"lpc1100\" || $_CHIPSERIES == \"lpc1200\" || $_CHIPSERIES == \"lpc1300\" } {\n\t\tset _CCLK 12000\n\t} elseif { $_CHIPSERIES == \"lpc1700\" || $_CHIPSERIES == \"lpc4000\" } {\n\t\tset _CCLK 4000\n\t}\n}\n\nif { [info exists CPUTAPID] } {\n\t# Allow user override\n\tset _CPUTAPID $CPUTAPID\n} else {\n\t# LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.\n\tif { $_CHIPSERIES == \"lpc800\" || $_CHIPSERIES == \"lpc1100\" || $_CHIPSERIES == \"lpc1200\" } {\n\t\tset _CPUTAPID 0x0bb11477\n\t} elseif { $_CHIPSERIES == \"lpc1300\" || $_CHIPSERIES == \"lpc1700\" || $_CHIPSERIES == \"lpc4000\" } {\n\t\tif { [using_jtag] } {\n\t\t\tset _CPUTAPID 0x4ba00477\n\t\t} {\n\t\t\tset _CPUTAPID 0x2ba01477\n\t\t}\n\t}\n}\n\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\terror \"WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE.\"\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M \"Code\" area (at 0x10000000)\n# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M \"Code\" area (at 0x10000000)\n# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M \"Code\" area (at 0x10000000)\n# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M \"Code\" area (at 0x10000000)\n# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M \"Code\" area (at 0x10000000)\n# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME \"Code\" area (at 0x10000000)\n$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE\n\n# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)\n# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)\n# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)\n# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)\n# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)\n# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)\n#\n# All are compatible with the \"lpc1700\" variant of the LPC2000 flash driver\n# (same cmd51 destination boundary alignment, and all three support 256 byte\n# transfers).\n#\n# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] [iap entry]\nset _IAP_ENTRY 0\nif { [info exists IAP_ENTRY] } {\n\tset _IAP_ENTRY $IAP_ENTRY\n}\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \\\n\tauto $_CCLK calc_checksum $_IAP_ENTRY\n\nif { $_CHIPSERIES == \"lpc800\" || $_CHIPSERIES == \"lpc1100\" || $_CHIPSERIES == \"lpc1200\" || $_CHIPSERIES == \"lpc1300\" } {\n\t# Do not remap 0x0000-0x0200 to anything but the flash (i.e. select\n\t# \"User Flash Mode\" where interrupt vectors are _not_ remapped,\n\t# and reside in flash instead).\n\t#\n\t# Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description\n\t# Bit Symbol Value Description\n\t# 1:0 MAP          System memory remap\n\t#            0x0   Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.\n\t#            0x1   User RAM Mode. Interrupt vectors are re-mapped to Static RAM.\n\t#            0x2   User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.\n\t# 31:2 -     -     Reserved.\n\t$_TARGETNAME configure -event reset-init {\n\t\tmww 0x40048000 0x02\n\t}\n} elseif { $_CHIPSERIES == \"lpc1700\" || $_CHIPSERIES == \"lpc4000\" } {\n\t# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select\n\t# \"User Flash Mode\" where interrupt vectors are _not_ remapped,\n\t# and reside in flash instead).\n\t#\n\t# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description\n\t# Bit Symbol Value Description Reset\n\t# value\n\t# 0 MAP Memory map control. 0\n\t# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.\n\t# 1 User mode. The on-chip Flash memory is mapped to address 0.\n\t# 31:1 - Reserved. The value read from a reserved bit is not defined. NA\n\t#\n\t# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user\n\t$_TARGETNAME configure -event reset-init {\n\t\tmww 0x400FC040 0x01\n\t}\n}\n\n# Run with *real slow* clock by default since the\n# boot rom could have been playing with the PLL, so\n# we have no idea what clock the target is running at.\nadapter speed 10\n\n# delays on reset lines\nadapter srst delay 200\nif {[using_jtag]} {\n jtag_ntrst_delay 200\n}\n\n# LPC8xx (Cortex-M0+ core) support SYSRESETREQ\n# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ\n# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ\n# LPC40xx (Cortex-M4F core) support SYSRESETREQ\nif {![using_hla]} {\n    # if srst is not fitted use SYSRESETREQ to\n    # perform a soft reset\n    cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2103.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC2103 ARM7TDMI-S with 32kB flash and 8kB SRAM, clocked with 12MHz crystal\n\nsource [find target/lpc2xxx.cfg]\n\n# parameters:\n# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000\n# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000\n\nproc setup_lpc2103 {core_freq_khz adapter_freq_khz} {\n\t# 32kB flash and 8kB SRAM\n\t# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2xxx lpc2103 0x4f1f0f0f 0x8000 lpc2000_v2 0x2000 $core_freq_khz $adapter_freq_khz\n}\n\nproc init_targets {} {\n\t# default to core clocked with 12MHz crystal\n\techo \"Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different.\"\n\n\t# setup_lpc2103 <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2103 12000 1500\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2124.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC2124 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal\n\nsource [find target/lpc2xxx.cfg]\n\n# parameters:\n# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000\n# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000\n\nproc setup_lpc2124 {core_freq_khz adapter_freq_khz} {\n\t# 256kB flash and 16kB SRAM\n\t# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2xxx lpc2124 0x4f1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz\n}\n\nproc init_targets {} {\n\t# default to core clocked with 12MHz crystal\n\techo \"Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different.\"\n\n\t# setup_lpc2124 <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2124 12000 1500\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2129.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC2129 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal\n\nsource [find target/lpc2xxx.cfg]\n\n# parameters:\n# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000\n# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000\n\nproc setup_lpc2129 {core_freq_khz adapter_freq_khz} {\n\t# 256kB flash and 16kB SRAM\n\t# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2xxx lpc2129 0xcf1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz\n}\n\nproc init_targets {} {\n\t# default to core clocked with 12MHz crystal\n\techo \"Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different.\"\n\n\t# setup_lpc2129 <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2129 12000 1500\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2148.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC2148 ARM7TDMI-S with 512kB flash (12kB used by bootloader) and 40kB SRAM (8kB for USB DMA), clocked with 12MHz crystal\n\nsource [find target/lpc2xxx.cfg]\n\n# parameters:\n# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000\n# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000\n\nproc setup_lpc2148 {core_freq_khz adapter_freq_khz} {\n\t# 500kB flash and 32kB SRAM\n\t# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2xxx lpc2148 \"0x3f0f0f0f 0x4f1f0f0f\" 0x7d000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz\n}\n\nproc init_targets {} {\n\t# default to core clocked with 12MHz crystal\n\techo \"Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different.\"\n\n\t# setup_lpc2148 <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2148 12000 1500\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2294.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC2294 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal\n\nsource [find target/lpc2xxx.cfg]\n\n# parameters:\n# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000\n# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000\n\nproc setup_lpc2294 {core_freq_khz adapter_freq_khz} {\n\t# 256kB flash and 16kB SRAM\n\t# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>\n\n\t# !! TAPID unknown !!\n\tsetup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz\n}\n\nproc init_targets {} {\n\t# default to core clocked with 12MHz crystal\n\techo \"Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different.\"\n\n\t# setup_lpc2294 <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2294 12000 1500\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2378.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC2378 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 56kB SRAM (16kB for ETH, 8kB for DMA), clocked with 4MHz internal oscillator\n\nsource [find target/lpc2xxx.cfg]\n\n# parameters:\n# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000\n# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000\n\nproc setup_lpc2378 {core_freq_khz adapter_freq_khz} {\n\t# 504kB flash and 32kB SRAM\n\t# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2xxx lpc2378 0x4f1f0f0f 0x7e000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz\n}\n\nproc init_targets {} {\n\t# default to core clocked with 4MHz internal oscillator\n\techo \"Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different.\"\n\n\t# setup_lpc2378 <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2378 4000 500\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2460.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC2460 ARM7TDMI-S with 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator\n\nsource [find target/lpc2xxx.cfg]\n\n# parameters:\n# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000\n# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000\n\nproc setup_lpc2460 {core_freq_khz adapter_freq_khz} {\n\t# 64kB SRAM\n\t# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2xxx lpc2460 0x4f1f0f0f 0 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz\n}\n\nproc init_targets {} {\n\t# default to core clocked with 4MHz internal oscillator\n\techo \"Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different.\"\n\n\t# setup_lpc2460 <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2460 4000 500\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2478.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC2478 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator\n\nsource [find target/lpc2xxx.cfg]\n\n# parameters:\n# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000\n# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000\n\nproc setup_lpc2478 {core_freq_khz adapter_freq_khz} {\n\t# 504kB flash and 64kB SRAM\n\t# setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2xxx lpc2478 0x4f1f0f0f 0x7e000 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz\n}\n\nproc init_targets {} {\n\t# default to core clocked with 4MHz internal oscillator\n\techo \"Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different.\"\n\n\t# setup_lpc2478 <core_freq_khz> <adapter_freq_khz>\n\tsetup_lpc2478 4000 500\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2900.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME lpc2900\n}\n\nif { [info exists CPUTAPID] } {\n    set _CPUTAPID $CPUTAPID\n} else {\n    set _CPUTAPID 0x0596802B\n}\n\nif { [info exists HAS_ETB] } {\n} else {\n    # Set default (no ETB).\n    # Show a warning, because this should have been configured explicitly.\n    set HAS_ETB 0\n    # TODO: warning?\n}\n\nif { [info exists ETBTAPID] } {\n    set _ETBTAPID $ETBTAPID\n} else {\n    set _ETBTAPID 0x1B900F0F\n}\n\n# TRST and SRST both exist, and can be controlled independently\nreset_config trst_and_srst separate\n\n# Define the _TARGETNAME\nset _TARGETNAME $_CHIPNAME.cpu\n\n# Include the ETB tap controller if asked for.\n# Has to be done manually for newer devices (not an \"old\" LPC2917/2919).\nif { $HAS_ETB == 1 } {\n    # Clear the HAS_ETB flag. Must be set again for a new tap in the chain.\n    set HAS_ETB 0\n\n    # Add the ETB tap controller and the ARM9 core debug tap\n    jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID\n    jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n    # Create the \".cpu\" target\n    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME\n\n    # Configure ETM and ETB\n    etm config $_TARGETNAME 8 normal full etb\n    etb config $_TARGETNAME $_CHIPNAME.etb\n\n} else {\n    # Add the ARM9 core debug tap\n    jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n    # Create the \".cpu\" target\n    target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME\n}\n\narm7_9 dbgrq enable\narm7_9 dcc_downloads enable\n\n# Flash bank configuration:\n# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>\n# Flash base address, total flash size, and number of sectors are all configured automatically.\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc2xxx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Common setup for the LPC2xxx parts\n\n# parameters:\n# - chip_name - name of the chip, e.g. lpc2103\n# - cputapids - TAP IDs of the core, should be quoted if more than one, e.g. 0x4f1f0f0f or \"0x3f0f0f0f 0x4f1f0f0f\"\n# - flash_size - size of on-chip flash (available for code, not including the bootloader) in bytes, e.g. 0x8000\n# - flash_variant - \"type\" of LPC2xxx device, lpc2000_v1 (LPC22xx and older LPC21xx) or lpc2000_v2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)\n# - workarea_size - size of work-area in RAM for flashing procedures, must not exceed the size of RAM available at 0x40000000, e.g. 0x2000\n# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000\n# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000\n\nproc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size core_freq_khz adapter_freq_khz} {\n\treset_config trst_and_srst\n\n\t# reset delays\n\tadapter srst delay 100\n\tjtag_ntrst_delay 100\n\n\tadapter speed $adapter_freq_khz\n\n\tforeach i $cputapids {\n\t\tappend expected_ids \"-expected-id \" $i \" \"\n\t}\n\n\teval \"jtag newtap $chip_name cpu -irlen 4 -ircapture 0x1 -irmask 0xf $expected_ids\"\n\n\tglobal _TARGETNAME\n\tset _TARGETNAME $chip_name.cpu\n\ttarget create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME\n\n\t$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size $workarea_size -work-area-backup 0\n\n\tif { $flash_size > 0 } {\n\t\t# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]\n\t\tset _FLASHNAME $chip_name.flash\n\t\tflash bank $_FLASHNAME lpc2000 0x0 $flash_size 0 0 $_TARGETNAME $flash_variant $core_freq_khz calc_checksum\n\t}\n}\n\nproc init_targets {} {\n\t# FIX!!! read out CPUTAPID here and choose right setup. In addition to the\n\t# CPUTAPID some querying of the target would be required.\n\treturn -error \"This is a generic LPC2xxx configuration file, use a specific target file.\"\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc3131.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    NXP lpc3131\n######################################\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME lpc3131\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# ARM926EJS core\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07926f0f\n}\n\n# Scan Tap\n# Wired to separate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module\n# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.\nif { [info exists SJCTAPID] } {\n   set _SJCTAPID $SJCTAPID\n} else {\n   set _SJCTAPID 0x1541E02B\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\n\n##################################################################\n# various symbol definitions, to avoid hard-wiring addresses\n##################################################################\n\nglobal lpc313x\nset lpc313x [ dict create ]\n\n# Physical addresses for controllers and memory\ndict set lpc313x sram0\t\t\t0x11028000\ndict set lpc313x sram1\t\t\t0x11040000\ndict set lpc313x uart\t\t\t0x15001000\ndict set lpc313x cgu\t\t\t0x13004000\ndict set lpc313x ioconfig\t\t0x13003000\ndict set lpc313x sysconfig\t\t0x13002800\ndict set lpc313x wdt\t\t\t0x13002400\n\n##################################################################\n# Target configuration\n##################################################################\n\nadapter srst delay 1000\njtag_ntrst_delay 0\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME invoke-event halted\n\n$_TARGETNAME configure -work-area-phys [dict get $lpc313x sram0] -work-area-size 0x30000 -work-area-backup 0\n\n$_TARGETNAME configure -event reset-init {\n\techo \"\\nRunning reset init script for LPC3131\\n\"\n\thalt\n\twait_halt\n\treg cpsr 0xa00000d3\t;#Supervisor mode\n\treg pc 0x11029000\n\tpoll\n\tsleep 500\n}\n\narm7_9 fast_memory_access enable\narm7_9 dcc_downloads enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc3250.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# lpc3250 config\n#\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME lpc3250\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x17900f0f\n}\n\nif { [info exists CPUTAPID_REV_A0] } {\n   set _CPUTAPID_REV_A0 $CPUTAPID_REV_A0\n} else {\n   set _CPUTAPID_REV_A0 0x17926f0f\n}\n\nif { [info exists SJCTAPID] } {\n   set _SJCTAPID $SJCTAPID\n} else {\n   set _SJCTAPID 0x1b900f0f\n}\n\njtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID \\\n     -expected-id $_CPUTAPID_REV_A0\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0\n\nproc power_restore {} { echo \"Sensed power restore. No action.\" }\nproc srst_deasserted {} { echo \"Sensed nSRST deasserted. No action.\" }\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc40xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC40xx Cortex-M4F with at least 16kB SRAM\nset CHIPNAME lpc40xx\nset CHIPSERIES lpc4000\nif { ![info exists WORKAREASIZE] } {\n\tset WORKAREASIZE 0x4000\n}\n\nsource [find target/lpc1xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc4350.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/swj-dp.tcl]\n\nadapter speed 500\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME lpc4350\n}\n\n#\n# M4 JTAG mode TAP\n#\nif { [info exists M4_JTAG_TAPID] } {\n\tset _M4_JTAG_TAPID $M4_JTAG_TAPID\n} else {\n\tset _M4_JTAG_TAPID 0x4ba00477\n}\n\n#\n# M4 SWD mode TAP\n#\nif { [info exists M4_SWD_TAPID] } {\n\tset _M4_SWD_TAPID $M4_SWD_TAPID\n} else {\n\tset _M4_SWD_TAPID 0x2ba01477\n}\n\nif { [using_jtag] } {\n\tset _M4_TAPID $_M4_JTAG_TAPID\n} {\n\tset _M4_TAPID $_M4_SWD_TAPID\n}\n\n#\n# M0 TAP\n#\nif { [info exists M0_JTAG_TAPID] } {\n\tset _M0_JTAG_TAPID $M0_JTAG_TAPID\n} else {\n\tset _M0_JTAG_TAPID 0x0ba01477\n}\n\nswj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t\t\t\t-expected-id $_M4_TAPID\ndap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4\ntarget create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap\n\nif { [using_jtag] } {\n\tswj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t\t\t\t-expected-id $_M0_JTAG_TAPID\n\tdap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0\n\ttarget create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap\n}\n\n# LPC4350 has 96+32 KB SRAM\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x20000\n}\n$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \\\n\t\t\t-work-area-size $_WORKAREASIZE -work-area-backup 0\n\nif {![using_hla]} {\n   # on this CPU we should use VECTRESET to perform a soft reset and\n   # manually reset the periphery\n   # SRST or SYSRESETREQ disable the debug interface for the time of\n   # the reset and will not fit our requirements for a consistent debug\n   # session\n   cortex_m reset_config vectreset\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc4357.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP LPC4357\n#\n\nif { ![info exists CHIPNAME] } {\n\tset CHIPNAME lpc4357\n}\nset WORKAREASIZE 0x8000\nsource [find target/lpc4350.cfg]\n\nflash bank $_CHIPNAME.flasha lpc2000 0x1A000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum\nflash bank $_CHIPNAME.flashb lpc2000 0x1B000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc4370.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each\n#\n\nadapter speed 500\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME lpc4370\n}\n\n#\n# M4 JTAG mode TAP\n#\nif { [info exists M4_JTAG_TAPID] } {\n\tset _M4_JTAG_TAPID $M4_JTAG_TAPID\n} else {\n\tset _M4_JTAG_TAPID 0x4ba00477\n}\n\n#\n# M4 SWD mode TAP\n#\nif { [info exists M4_SWD_TAPID] } {\n\tset _M4_SWD_TAPID $M4_SWD_TAPID\n} else {\n\tset _M4_SWD_TAPID 0x2ba01477\n}\n\nsource [find target/swj-dp.tcl]\n\nif { [using_jtag] } {\n\tset _M4_TAPID $_M4_JTAG_TAPID\n} else {\n\tset _M4_TAPID $_M4_SWD_TAPID\n}\n\n#\n# M0 TAP\n#\nif { [info exists M0_JTAG_TAPID] } {\n\tset _M0_JTAG_TAPID $M0_JTAG_TAPID\n} else {\n\tset _M0_JTAG_TAPID 0x0ba01477\n}\n\nswj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t\t\t\t-expected-id $_M4_TAPID\ndap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4\ntarget create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap\n\n# LPC4370 has 96+32 KB contiguous SRAM\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x20000\n}\n$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \\\n                        -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nif { [using_jtag] } {\n\tjtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t\t\t\t\t-expected-id $_M0_JTAG_TAPID\n\tjtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t\t\t\t\t-expected-id $_M0_JTAG_TAPID\n\n\tdap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app\n\tdap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub\n\ttarget create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap\n\ttarget create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap\n\n\t# 32+8+32 KB SRAM\n\t$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \\\n\t                           -work-area-size 0x92000 -work-area-backup 0\n\n\t# 16+2 KB M0 subsystem SRAM\n\t$_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \\\n\t                           -work-area-size 0x4800 -work-area-backup 0\n\n\t# Default to the Cortex-M4\n\ttargets $_CHIPNAME.m4\n}\n\nif { ![using_hla] } {\n\tcortex_m reset_config vectreset\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc84x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC84x Cortex-M0+ with at least 8kB SRAM\nif { ![info exists CHIPNAME] } {\n\tset CHIPNAME lpc84x\n}\nset CHIPSERIES lpc800\nif { ![info exists WORKAREASIZE] } {\n\tset WORKAREASIZE 0x1fe0\n}\n\nset IAP_ENTRY 0x0F001FF1\nsource [find target/lpc1xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc8nxx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM\n# Copyright (C) 2018 by Jean-Christian de Rivaz\n# Based on NXP proposal https://community.nxp.com/message/1011149\n# Many thanks to Dries Moors from NXP support.\n# SWD only transport\n\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset  _CHIPNAME $CHIPNAME\n} else {\n\tset  _CHIPNAME lpc8nxx\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id 0\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap\nif {![using_hla]} {\n\t# If srst is not fitted use SYSRESETREQ to  perform a soft reset\n\tcortex_m reset_config sysresetreq\n}\nadapter srst delay 100\n\n$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0\n\nflash bank $_CHIPNAME.flash lpc2000 0x0 0x7800 0 0 $_TARGETNAME lpc800 500\n\necho \"*********************************************************************************\"\necho \"*         !!!!! IMPORTANT NOTICE FOR LPC8Nxx and NHS31xx CHIPS !!!!!\"\necho \"* When this IC is in power-off or peep power down mode, the SWD HW block is also\"\necho \"* unpowered. These modes can be entered by firmware. The default firmware image\"\necho \"* (flashed in production) makes use of this. Best is to avoid these power modes\"\necho \"* during development, and only later add them when the functionality is complete.\"\necho \"* Hardware reset or NFC field are the only ways to connect in case the SWD is\"\necho \"* powered off. OpenOCD can do a hardware reset if you wire the adapter SRST\"\necho \"* signal to the chip RESETN pin and add the following in your configuration:\"\necho \"*     reset_config srst_only; flash init; catch init; reset\"\necho \"* But if the actual firmware immediately set the power down mode after reset,\"\necho \"* OpenOCD might be not fast enough to halt the CPU before the SWD lost power. In\"\necho \"* that case the only solution is to apply a NFC field to keep the SWD powered.\"\necho \"*********************************************************************************\"\n\n# Using soft-reset 'reset_config none' is strongly discouraged.\n# RESETN sets the system clock to 500 kHz. Unlike soft-reset does not.\n# Set the system clock to 500 kHz before reset to simulate the functionality of hw reset.\n#\nproc set_sysclk_500khz {} {\n\tset SYSCLKCTRL 0x40048020\n\tset SYSCLKUEN 0x40048024\n\tmww $SYSCLKUEN 0\n\tmmw $SYSCLKCTRL 0x8 0xe\n\tmww $SYSCLKUEN 1\n\techo \"Notice: sysclock set to 500kHz.\"\n}\n\n# Do not remap the ARM interrupt vectors to anything but the beginning of the flash.\n# Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description\n# Bit Symbol  Value   Description\n# 0   map         -   interrupt vector remap. 0 after boot.\n#                 0   interrupt vector reside in Flash\n#                 1   interrupt vector reside in SRAM\n# 5:1 offset      -   system memory remap offset. 00000b after boot.\n#            00000b   interrupt vectors in flash or remapped to SRAM but no offset\n#            00001b -\n#            00111b   interrupt vectors offset in flash or SRAM to 1K word segment\n#            01000b -\n#            11111b   interrupt vectors offset in flash to 1K word segment 8 to 31\n# 31:6                reserved\n#\nproc set_no_remap {} {\n\tmww 0x40048000 0x00\n\techo \"Notice: interrupt vector set to no remap.\"\n}\n\n$_TARGETNAME configure -event reset-init {\n\tset_sysclk_500khz\n\tset_no_remap\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lpc8xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP LPC8xx Cortex-M0+ with at least 1kB SRAM\nif { ![info exists CHIPNAME] } {\n\tset CHIPNAME lpc8xx\n}\nset CHIPSERIES lpc800\nif { ![info exists WORKAREASIZE] } {\n\tset WORKAREASIZE 0x400\n}\n\nsource [find target/lpc1xxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ls1012a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# NXP LS1012A\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME ls1012a\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x5ba00477\n}\n\nif { [info exists SAP_TAPID] } {\n\tset _SAP_TAPID $SAP_TAPID\n} else {\n\tset _SAP_TAPID 0x06b2001d\n}\n\njtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID\njtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap\n\ncti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80420000\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase 0x80410000 -cti $_CHIPNAME.cti\n\ntarget smp $_TARGETNAME\n\nadapter speed 2000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ls1028a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# NXP LS1028A\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME ls1028a\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x6ba00477\n}\n\nset _CPUS 2\n\nsource [find target/lsch3_common.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ls1046a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# NXP LS1046A\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME ls1046a\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x5ba00477\n}\n\nif { [info exists SAP_TAPID] } {\n\tset _SAP_TAPID $SAP_TAPID\n} else {\n\tset _SAP_TAPID 0x06b3001d\n}\n\njtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap\n\ntarget create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0\n\nset _CPU_BASE 0x80400000\nset _CPU_STRIDE 0x100000\nset _CPU_DBGOFF 0x10000\nset _CPU_CTIOFF 0x20000\n\nset _TARGETS {}\nfor {set i 0} {$i < 4} {incr i} {\n\tset _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]\n\tcti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 1 \\\n\t\t-baseaddr [expr {$_BASE + $_CPU_CTIOFF}]\n\ttarget create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \\\n\t\t-cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \\\n\t\t-coreid $i {*}[expr {$i ? {-defer-examine} : {-rtos hwthread} }]\n\tlappend _TARGETS $_CHIPNAME.cpu$i\n}\n\ntarget smp {*}$_TARGETS\n\njtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID\ntarget create $_CHIPNAME.sap ls1_sap -chain-position $_CHIPNAME.sap -endian big\n\nproc core_up { args } {\n    foreach core $args {\n        $::_CHIPNAME.cpu$core arp_examine\n    }\n}\n\ntargets $_CHIPNAME.cpu0\n\nadapter speed 10000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ls1088a.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# NXP LS1088A\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME ls1088a\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x5ba00477\n}\n\nset _CPUS 8\n\nsource [find target/lsch3_common.cfg]\n\n# Seems to work OK in testing\nadapter speed 10000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/lsch3_common.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# This contains common configuration for NXP Layerscape chassis generation 3\n\nif { ![info exists _CPUS] } {\n\terror \"_CPUS must be set to the number of cores\"\n}\n\njtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap\n\ntarget create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1\n\nset _CPU_BASE 0x81000000\nset _CPU_STRIDE 0x100000\nset _CPU_DBGOFF 0x10000\nset _CPU_CTIOFF 0x20000\n\nset _TARGETS {}\nfor {set i 0} {$i < $_CPUS} {incr i} {\n\tset _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]\n\tcti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \\\n\t\t-baseaddr [expr {$_BASE + $_CPU_CTIOFF}]\n\ttarget create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \\\n\t\t-cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \\\n\t\t{*}[expr {$i ? \"-coreid $i\" : \"-rtos hwthread\" }]\n\tlappend _TARGETS $_CHIPNAME.cpu$i\n}\n\ntarget smp {*}$_TARGETS\n\n# Service processor\ntarget create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000\n\n# Normally you will not need to call this, but if you are using the hard-coded\n# Reset Configuration Word (RCW) you will need to call this manually. The CPU's\n# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit\n# instructions. This will cause the CPU to almost immediately execute an\n# illegal instruction.\n#\n# This code is idempotent; releasing a released CPU has no effect, although it\n# will halt/resume the service processor.\nadd_help_text release_cpu \"Release a cpu which is held off\"\nproc release_cpu {cpu} {\n\tset RST_BRRL 0x1e60060\n\n\tset old [target current]\n\ttargets $::_CHIPNAME.sp\n\tset not_halted [string compare halted [$::_CHIPNAME.sp curstate]]\n\tif {$not_halted} {\n\t\thalt\n\t}\n\n\t# Release the cpu; it will start executing something bogus\n\tmem2array regs 32 $RST_BRRL 1\n\tmww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]\n\n\tif {$not_halted} {\n\t\tresume\n\t}\n\ttargets $old\n}\n\ntargets $_CHIPNAME.cpu0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/marvell/88f3710.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Marvell Armada 3710\n\nset CORES 1\n\nsource [find target/marvell/88f37x0.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/marvell/88f3720.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Marvell Armada 3720\n\nset CORES 2\n\nsource [find target/marvell/88f37x0.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/marvell/88f37x0.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Main file for Marvell Armada 3700 series targets\n#\n# !!!!!!\n#\n# This file should not be included directly. Instead, please include\n# either marvell/88f3710.cfg or marvell/88f3720.cfg, which set the needed\n# variables to the appropriate values.\n#\n# !!!!!!\n\n# Armada 3700 supports both JTAG and SWD transports.\nsource [find target/swj-dp.tcl]\n\nif { [info exists CORES] } {\n    set _cores $CORES\n} else {\n    error \"CORES not set. Please do not include marvell/88f37x0.cfg directly, but the specific chip configuration file (marvell/88f3710.cfg, marvell/88f3720.cfg, etc.).\"\n}\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME [format a37%s0 $_cores]\n}\n\nset _ctis {0x80820000 0x80920000}\n\n#\n# Main DAP\n#\nif { [info exists DAP_TAPID] } {\n    set _DAP_TAPID $DAP_TAPID\n} else {\n    set _DAP_TAPID 0x4ba00477\n}\n\n# declare the one JTAG tap to access the DAP\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# declare the main application cores\nset _TARGETNAME $_CHIPNAME.cpu\nset _smp_command \"\"\n\nfor { set _core 0 } { $_core < $_cores } { incr _core 1 } {\n\n    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [lindex $_ctis $_core] -ap-num 0\n\n    set _command \"target create ${_TARGETNAME}$_core aarch64 \\\n                         -dap $_CHIPNAME.dap -coreid $_core \\\n                         -cti cti$_core\"\n\n    if { $_core != 0 } {\n        # non-boot core examination may fail\n        set _command \"$_command -defer-examine\"\n        set _smp_command \"$_smp_command ${_TARGETNAME}$_core\"\n    } else {\n        set _command \"$_command -rtos hwthread\"\n        set _smp_command \"target smp ${_TARGETNAME}$_core\"\n    }\n\n    eval $_command\n}\n\neval $_smp_command\n\n# declare the auxiliary Cortex-M3 core on AP #3\ntarget create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine\n\ntargets ${_TARGETNAME}0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/max32620.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Maxim Integrated MAX32620 OpenOCD target configuration file\n# www.maximintegrated.com\n\n# adapter speed\nadapter speed 4000\n\n# reset pin configuration\nreset_config srst_only\n\nif {[using_jtag]} {\n    jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version\n    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version\n} else {\n    swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version\n}\n\ndap create max32620.dap -chain-position max32620.cpu\n\n# target configuration\ntarget create max32620.cpu cortex_m -dap max32620.dap\nmax32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000\n\n# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]\n#   flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>\n#   max32620 flash base address   0x00000000\n#   max32620 flash size           0x200000 (2MB)\n#   max32620 FLC base address     0x40002000\n#   max32620 sector (page) size   0x2000 (8kB)\n#   max32620 clock speed          96 (MHz)\nflash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/max32625.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Maxim Integrated MAX32625 OpenOCD target configuration file\n# www.maximintegrated.com\n\n# adapter speed\nadapter speed 4000\n\n# reset pin configuration\nreset_config srst_only\n\nif {[using_jtag]} {\n    jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version\n    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version\n} else {\n    swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version\n}\n\ndap create max32625.dap -chain-position max32625.cpu\n\n# target configuration\ntarget create max32625.cpu cortex_m -dap max32625.dap\nmax32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000\n\n# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]\n#   flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>\n#   max32625 flash base address   0x00000000\n#   max32625 flash size           0x80000 (512k)\n#   max32625 FLC base address     0x40002000\n#   max32625 sector (page) size   0x2000 (8kB)\n#   max32625 clock speed          96 (MHz)\nflash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/max3263x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Maxim Integrated MAX3263X OpenOCD target configuration file\n# www.maximintegrated.com\n\n# adapter speed\nadapter speed 4000\n\n# reset pin configuration\nreset_config srst_only\n\nif {[using_jtag]} {\n    jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version\n    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version\n} else {\n    swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version\n}\n\ndap create max3263x.dap -chain-position max3263x.cpu\n\n# target configuration\ntarget create max3263x.cpu cortex_m -dap max3263x.dap\nmax3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000\n\n# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]\n#   flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>\n#   max3263x flash base address   0x00000000\n#   max3263x flash size           0x200000 (2MB)\n#   max3263x FLC base address     0x40002000\n#   max3263x sector (page) size   0x2000 (8kB)\n#   max3263x clock speed          96 (MHz)\nflash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/mc13224v.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find bitsbytes.tcl]\nsource [find cpu/arm/arm7tdmi.tcl]\nsource [find memory.tcl]\nsource [find mmr_helpers.tcl]\n\nset CHIP_MAKER             freescale\nset CHIP_FAMILY            mc1322x\nset CHIP_NAME              mc13224\nset N_RAM                  1\nset RAM(0,BASE)            0x00400000\nset RAM(0,LEN)             0x18000\nset RAM(0,HUMAN)           \"internal SRAM\"\nset RAM(0,TYPE)            \"ram\"\nset RAM(0,RWX)             $RWX_RWX\nset RAM(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY\n\n# I AM LAZY... I create 1 region for all MMRs.\nset N_MMREGS                  1\nset MMREGS(0,CHIPSELECT)      -1\nset MMREGS(0,BASE)            0x80000000\nset MMREGS(0,LEN)             0x00030000\nset MMREGS(0,HUMAN)           \"mm-regs\"\nset MMREGS(0,TYPE)            \"mmr\"\nset MMREGS(0,RWX)             $RWX_RW\nset MMREGS(0,ACCESS_WIDTH)    $ACCESS_WIDTH_ANY\n\nset N_XMEM 0\n\nset _CHIPNAME mc13224v\nset _CPUTAPID 0x1f1f001d\n\njtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\n\nreset_config srst_only\njtag_ntrst_delay 200\n\n# rclk hasn't been working well. This maybe the mc13224v or something else.\n#adapter speed 2000\nadapter speed 2000\n\n######################\n# Target configuration\n######################\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME\n\n# Internal sram memory\n$_TARGETNAME configure -work-area-phys 0x00408000 \\\n                       -work-area-size 0x1000     \\\n                       -work-area-backup 1\n\n# flash support is pending (should be straightforward to implement)\n#flash bank mc1322x 0 0 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/mdr32f9q2i.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# MDR32F9Q2I (1986ВЕ92У)\n# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME mdr32f9q2i\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Work-area is a space in RAM used for flash programming\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x8000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      set _CPUTAPID 0x4ba00477\n   } {\n      # SWD IDCODE\n      set _CPUTAPID 0x2ba01477\n   }\n}\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# can't handle overlapping memory regions\nif { [info exists IMEMORY] && [string equal $IMEMORY true] } {\n   flash bank ${_CHIPNAME}_info.flash mdr 0x08000000 0x01000 0 0 $_TARGETNAME 1 1 4\n} else {\n   flash bank $_CHIPNAME.flash mdr 0x08000000 0x20000 0 0 $_TARGETNAME 0 32 4\n}\n\n# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz\nadapter speed 1000\n\nadapter srst delay 100\nif {[using_jtag]} {\n   jtag_ntrst_delay 100\n}\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/nds32v5.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Andes Core\n#\n# http://www.andestech.com\n#\n\nset _CHIPNAME nds\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563D\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME riscv -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ngultra.cfg",
    "content": "# SPDX-License-Identifier: BSD-3-Clause\n# Copyright (C) 2022 by NanoXplore, France - all rights reserved\n#\n# configuration file for NG-Ultra SoC from NanoXplore.\n# NG-Ultra is a quad-core Cortex-R52 SoC + an FPGA.\n#\ntransport select jtag\nadapter speed 10000\n\nif { [info exists CHIPNAME] } {\n   set  _CHIPNAME $CHIPNAME\n} else {\n   set  _CHIPNAME NGULTRA\n}\n\nif { [info exists CHIPCORES] } {\n    set _cores $CHIPCORES\n} else {\n    set _cores 4\n}\n\nset DBGBASE {0x88210000 0x88310000 0x88410000 0x88510000}\nset CTIBASE {0x88220000 0x88320000 0x88420000 0x88520000}\n\n# Coresight access to the SoC\njtag newtap $_CHIPNAME.coresight cpu      -irlen 4 -expected-id 0x6BA00477\n\n# Misc TAP devices\njtag newtap $_CHIPNAME.soc       cpu      -irlen 7 -expected-id 0xFAAA0555\njtag newtap $_CHIPNAME.pmb       unknown1 -irlen 5 -expected-id 0xBA20A005\njtag newtap $_CHIPNAME.fpga      fpga     -irlen 4 -ignore-version -ignore-bypass\n\n# Create the Coresight DAP\ndap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu\n\nfor { set _core 0 } { $_core < $_cores } { incr _core } {\n    cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \\\n        -baseaddr [lindex $CTIBASE $_core]\n# Cores are armv8-r but works with aarch64 (since armv8-r not directly supported by openocd yet).\n    if { $_core == 0} {\n        target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \\\n            -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core\n    } else {\n        target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \\\n            -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine\n    }\n}\n\n# Create direct APB and AXI interfaces\ntarget create APB mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 0\ntarget create AXI mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/nhs31xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP NHS31xx Cortex-M0+ with 8kB SRAM\n\nset CHIPNAME nhs31xx\nsource [find target/lpc8nxx.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/npcx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for Nuvoton NPCX Cortex-M4 Series\n\n# Adapt based on what transport is active.\nsource [find target/swj-dp.tcl]\n\n# Set Chipname\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME NPCX_M4\n}\n\n# SWD DAP ID of Nuvoton NPCX Cortex-M4.\nif { [info exists CPUDAPID ] } {\n   set _CPUDAPID $CPUDAPID\n} else {\n   set _CPUDAPID 0x4BA00477\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 32kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x8000\n}\n\n# Debug Adapter Target Settings\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# Initial JTAG/SWD speed\n# For safety purposes, set for the lowest cpu clock configuration\n# 4MHz / 6 = 666KHz, so use 600KHz for it\nadapter speed 600\n\n# For safety purposes, set for the lowest cpu clock configuration\n$_TARGETNAME configure -event reset-start {adapter speed 600}\n\n# use sysresetreq to perform a system reset\ncortex_m reset_config sysresetreq\n\n# flash configuration\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/nrf51.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# script for Nordic nRF51 series, a Cortex-M0 chip\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME nrf51\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 16kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x0bb11477\n}\n\nswj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nif {![using_hla]} {\n   # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal\n   cortex_m reset_config sysresetreq\n}\n\nflash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME\nflash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME\n\n#\n#  The chip should start up from internal 16Mhz RC, so setting adapter\n#  clock to 1Mhz should be OK\n#\nadapter speed 1000\n\nproc enable_all_ram {} {\n\t# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks\n\t# are reliably enabled after reset on some revisions (contrary to spec.) So after\n\t# resetting we enable all banks via the RAMON register\n\tmww 0x40000524 0xF\n}\n$_TARGETNAME configure -event reset-end {  enable_all_ram }\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/nrf52.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME nrf52\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 16kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x2ba01477\n}\n\nswj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\nadapter speed 1000\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nif { [using_hla] } {\n\techo \"\"\n\techo \"nRF52 device has a CTRL-AP dedicated to recover the device from AP lock.\"\n\techo \"A high level adapter (like a ST-Link) you are currently using cannot access\"\n\techo \"the CTRL-AP so 'nrf52_recover' command will not work.\"\n\techo \"Do not enable UICR APPROTECT.\"\n\techo \"\"\n} else {\n\tcortex_m reset_config sysresetreq\n\n\t$_TARGETNAME configure -event examine-fail nrf52_check_ap_lock\n}\n\nflash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME\nflash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME\n\n# Test if MEM-AP is locked by UICR APPROTECT\nproc nrf52_check_ap_lock {} {\n\tset dap [[target current] cget -dap]\n\tset err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}]\n\tif {$err == 0 && $APPROTECTSTATUS != 1} {\n\t\techo \"****** WARNING ******\"\n\t\techo \"nRF52 device has AP lock engaged (see UICR APPROTECT register).\"\n\t\techo \"Debug access is denied.\"\n\t\techo \"Use 'nrf52_recover' to erase and unlock the device.\"\n\t\techo \"\"\n\t\tpoll off\n\t}\n}\n\n# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)\n# http://www.ebyte.com produces modules with nRF52 locked by default,\n# use nrf52_recover to enable flashing and debug.\nproc nrf52_recover {} {\n\tset target [target current]\n\tset dap [$target cget -dap]\n\n\tset IDR [$dap apreg 1 0xfc]\n\tif {$IDR != 0x02880000} {\n\t\techo \"Error: Cannot access nRF52 CTRL-AP!\"\n\t\treturn\n\t}\n\n\tpoll off\n\n\t# Reset and trigger ERASEALL task\n\t$dap apreg 1 4 0\n\t$dap apreg 1 4 1\n\n\tfor {set i 0} {1} {incr i} {\n\t\tset ERASEALLSTATUS [$dap apreg 1 8]\n\t\tif {$ERASEALLSTATUS == 0} {\n\t\t\techo \"$target device has been successfully erased and unlocked.\"\n\t\t\tbreak\n\t\t}\n\t\tif {$i == 0} {\n\t\t\techo \"Waiting for chip erase...\"\n\t\t}\n\t\tif {$i >= 150} {\n\t\t\techo \"Error: $target recovery failed.\"\n\t\t\tbreak\n\t\t}\n\t\tsleep 100\n\t}\n\n\t# Assert reset\n\t$dap apreg 1 0 1\n\n\t# Deassert reset\n\t$dap apreg 1 0 0\n\n\t# Reset ERASEALL task\n\t$dap apreg 1 4 0\n\n\tsleep 100\n\t$target arp_examine\n\tpoll on\n}\n\nadd_help_text nrf52_recover \"Mass erase and unlock nRF52 device\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/nuc910.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Nuvoton nuc910 (previously W90P910) based soc\n#\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME nuc910\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n  # set useful default\n   set _CPUTAPID 0x07926f0f\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/numicro.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for Nuvoton MuMicro Cortex-M0 Series\n\n# Adapt based on what transport is active.\nsource [find target/swj-dp.tcl]\n\n# Set Chipname\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME NuMicro\n}\n\n# SWD DP-ID Nuvoton NuMicro Cortex-M0 has SWD Transport only.\nif { [info exists CPUDAPID] } {\n\tset _CPUDAPID $CPUDAPID\n} else {\n\tset _CPUDAPID 0x0BB11477\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 2kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x800\n}\n\n\n# Debug Adapter Target Settings\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# flash bank <name> numicro <base> <size(autodetect,set to 0)> 0 0 <target#>\n#set _FLASHNAME $_CHIPNAME.flash\n#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash_aprom\nflash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash_data\nflash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash_ldrom\nflash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash_config\nflash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME\n\n# set default SWCLK frequency\nadapter speed 1000\n\n# set default srst setting \"none\"\nreset_config none\n\n# HLA doesn't have cortex_m commands\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/numicro_m4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for Nuvoton MuMicro Cortex-M4 Series\n\nsource [find target/swj-dp.tcl]\n\n# Set Chipname\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME NuMicro\n}\n\n# SWD DP-ID Nuvoton NuMicro Cortex-M4 has SWD Transport only.\nif { [info exists CPUDAPID] } {\n\tset _CPUDAPID $CPUDAPID\n} else {\n\tset _CPUDAPID 0x2BA01477\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 16kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\n\n# Debug Adapter Target Settings\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# flash bank <name> numicro <base> <size(autodetect,set to 0)> 0 0 <target#>\n#set _FLASHNAME $_CHIPNAME.flash\n#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash_aprom\nflash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash_data\nflash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash_ldrom\nflash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash_config\nflash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME\n\n# set default SWCLK frequency\nadapter speed 1000\n\n# set default srst setting \"none\"\nreset_config none\n\n# HLA doesn't have cortex_m commands\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/omap2420.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Texas Instruments OMAP 2420\n#\thttp://www.ti.com/omap\n# as seen in Nokia N8x0 tablets\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME omap2420\n}\n\n# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK\nreset_config srst_nogate\n\n# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).\njtag newtap $_CHIPNAME iva -irlen 4 -disable\n\n# Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).\njtag newtap $_CHIPNAME dsp -irlen 38 -disable\n\n# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer\nif { [info exists ETB_TAPID] } {\n   set _ETB_TAPID $ETB_TAPID\n} else {\n   set _ETB_TAPID 0x2b900f0f\n}\njtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID\n\n# Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.\nif { [info exists CPU_TAPID] } {\n   set _CPU_TAPID $CPU_TAPID\n} else {\n   set _CPU_TAPID 0x07b3602f\n}\njtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID\n\n# Primary TAP: ICEpick-B (JTAG route controller) and boundary scan\nif { [info exists JRC_TAPID] } {\n   set _JRC_TAPID $JRC_TAPID\n} else {\n   set _JRC_TAPID 0x01ce4801\n}\njtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID\n\n# GDB target: the ARM.\nset _TARGETNAME $_CHIPNAME.arm\ntarget create $_TARGETNAME arm11 -chain-position $_TARGETNAME\n\n# scratch: framebuffer, may be initially unavailable in some chips\n$_TARGETNAME configure -work-area-phys 0x40210000\n$_TARGETNAME configure -work-area-size 0x00081000\n$_TARGETNAME configure -work-area-backup 0\n\n# trace setup ... NOTE, \"normal full\" mode fudges the real ETMv3.1 mode\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n\n# RM_RSTCTRL_WKUP.RST.GS - Trigger a global software reset, and\n# give it a chance to finish before we talk to the chip again.\nset RM_RSTCTRL_WKUP 0x48008450\n$_TARGETNAME configure -event reset-assert \\\n\t\"halt; $_TARGETNAME mww $RM_RSTCTRL_WKUP 2; sleep 200\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/omap3530.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# TI OMAP3530\n# http://focus.ti.com/docs/prod/folders/print/omap3530.html\n# Other OMAP3 chips remove DSP and/or the OpenGL support\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME omap3530\n}\n\n# ICEpick-C ... used to route Cortex, DSP, and more not shown here\nsource [find target/icepick.cfg]\n\n# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick\njtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable\n\n# Subsidiary TAP: CoreSight Debug Access Port (DAP)\nif { [info exists DAP_TAPID] } {\n   set _DAP_TAPID $DAP_TAPID\n} else {\n   set _DAP_TAPID 0x0b6d602f\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t-expected-id $_DAP_TAPID -disable\njtag configure $_CHIPNAME.cpu -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 3\"\n\n# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan\nif { [info exists JRC_TAPID] } {\n   set _JRC_TAPID $JRC_TAPID\n} else {\n   set _JRC_TAPID 0x0b7ae02f\n}\njtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \\\n\t-expected-id $_JRC_TAPID\n\n# GDB target: Cortex-A8, using DAP\nset _TARGETNAME $_CHIPNAME.cpu\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap\n\n# SRAM: 64K at 0x4020.0000; use the first 16K\n$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000\n\n###################\n\n# the reset sequence is event-driven\n# and kind of finicky...\n\n# some TCK tycles are required to activate the DEBUG power domain\njtag configure $_CHIPNAME.jrc -event post-reset \"runtest 100\"\n\n# have the DAP \"always\" be active\njtag configure $_CHIPNAME.jrc -event setup \"jtag tapenable $_CHIPNAME.dap\"\n\nproc omap3_dbginit {target} {\n     # General Cortex-A8 debug initialisation\n     cortex_a dbginit\n     # Enable DBGU signal for OMAP353x\n     $target mww phys 0x5401d030 0x00002000\n}\n\n# be absolutely certain the JTAG clock will work with the worst-case\n# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.\n# OK to speed up *after* PLL and clock tree setup.\nadapter speed 1000\n$_TARGETNAME configure -event \"reset-start\" { adapter speed 1000 }\n\n# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset\n# ourselves using PRM_RSTCTRL.  RST_GS (2) is a warm reset, like ICEpick\n# would issue.  RST_DPLL3 (4) is a cold reset.\nset PRM_RSTCTRL 0x48307250\n$_TARGETNAME configure -event reset-assert \"$_TARGETNAME mww $PRM_RSTCTRL 2\"\n\n$_TARGETNAME configure -event reset-assert-post \"omap3_dbginit $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/omap4430.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# OMAP4430\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME omap4430\n}\n\n\n# Although the OMAP4430 supposedly has an ICEpick-D, only the\n# ICEpick-C router commands seem to work.\n# See http://processors.wiki.ti.com/index.php/ICEPICK\nsource [find target/icepick.cfg]\n\n\n#\n# A9 DAP\n#\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x3BA00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t-expected-id $_DAP_TAPID -disable\njtag configure $_CHIPNAME.cpu -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 9\"\n\n\n#\n# M3 DAPs, one per core\n#\nif { [info exists M3_DAP_TAPID] } {\n\tset _M3_DAP_TAPID $M3_DAP_TAPID\n} else {\n\tset _M3_DAP_TAPID 0x4BA00477\n}\n\njtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t-expected-id $_M3_DAP_TAPID -disable\njtag configure $_CHIPNAME.m31 -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 5\"\n\njtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t-expected-id $_M3_DAP_TAPID -disable\njtag configure $_CHIPNAME.m30 -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 4\"\n\n\n#\n# ICEpick-D JRC (JTAG route controller)\n#\nif { [info exists JRC_TAPID] } {\n\tset _JRC_TAPID $JRC_TAPID\n} else {\n\tset _JRC_TAPID  0x3b95c02f\n\tset _JRC_TAPID2 0x1b85202f\n}\n\n# PandaBoard REV EA1 (PEAP platforms)\nif { [info exists JRC_TAPID2] } {\n\tset _JRC_TAPID2 $JRC_TAPID2\n} else {\n\tset _JRC_TAPID2 0x1b85202f\n}\n\n\n\njtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \\\n\t-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2\n\n# Required by ICEpick to power-up the debug domain\njtag configure $_CHIPNAME.jrc -event post-reset \"runtest 200\"\n\n\n#\n# GDB target: Cortex-A9, using DAP\n#\n# The debugger can connect to either core of the A9, but currently\n# not both simultaneously.  Change -coreid to 1 to connect to the\n# second core.\n#\nset _TARGETNAME $_CHIPNAME.cpu\n\n# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.\n# 0x80000000 is cpu0 coresight region\n#\n#\n# CORTEX_A8_PADDRDBG_CPU_SHIFT 13\n# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)\n\nset _coreid 0\nset _dbgbase [expr {0x80000000 | ($_coreid << 13)}]\necho \"Using dbgbase = [format 0x%x $_dbgbase]\"\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \\\n  -coreid 0 -dbgbase $_dbgbase\n\n# SRAM: 56KiB at 0x4030.0000\n$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000\n\n\n#\n# M3 targets, separate TAP/DAP for each core\n#\ndap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30\ndap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31\ntarget create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap\ntarget create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap\n\n\n# Once the JRC is up, enable our TAPs\njtag configure $_CHIPNAME.jrc -event setup \"\n\tjtag tapenable $_CHIPNAME.cpu\n\tjtag tapenable $_CHIPNAME.m30\n\tjtag tapenable $_CHIPNAME.m31\n\"\n\n# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset\n# ourselves using PRM_RSTCTRL.  1 is a warm reset, 2 a cold reset.\nset PRM_RSTCTRL 0x4A307B00\n$_TARGETNAME configure -event reset-assert \"$_TARGETNAME mww phys $PRM_RSTCTRL 0x1\"\n$_CHIPNAME.m30 configure -event reset-assert { }\n$_CHIPNAME.m31 configure -event reset-assert { }\n\n# Soft breakpoints don't currently work due to broken cache handling\ngdb_breakpoint_override hard\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/omap4460.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# OMAP4460\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME omap4460\n}\n\n\n# Although the OMAP4430 supposedly has an ICEpick-D, only the\n# ICEpick-C router commands seem to work.\n# See http://processors.wiki.ti.com/index.php/ICEPICK\nsource [find target/icepick.cfg]\n\n\n#\n# A9 DAP\n#\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x3BA00477\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t-expected-id $_DAP_TAPID -disable\njtag configure $_CHIPNAME.cpu -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 9\"\n\n\n#\n# M3 DAPs, one per core\n#\nif { [info exists M3_DAP_TAPID] } {\n\tset _M3_DAP_TAPID $M3_DAP_TAPID\n} else {\n\tset _M3_DAP_TAPID 0x4BA00477\n}\n\njtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t-expected-id $_M3_DAP_TAPID -disable\njtag configure $_CHIPNAME.m31 -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 5\"\n\njtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \\\n\t-expected-id $_M3_DAP_TAPID -disable\njtag configure $_CHIPNAME.m30 -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 4\"\n\n\n#\n# ICEpick-D JRC (JTAG route controller)\n#\nif { [info exists JRC_TAPID] } {\n\tset _JRC_TAPID $JRC_TAPID\n} else {\n\tset _JRC_TAPID  0x2b94e02f\n\tset _JRC_TAPID2 0x1b85202f\n}\n\n# PandaBoard REV EA1 (PEAP platforms)\nif { [info exists JRC_TAPID2] } {\n\tset _JRC_TAPID2 $JRC_TAPID2\n} else {\n\tset _JRC_TAPID2 0x1b85202f\n}\n\n\n\njtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \\\n\t-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2\n\n# Required by ICEpick to power-up the debug domain\njtag configure $_CHIPNAME.jrc -event post-reset \"runtest 200\"\n\n\n#\n# GDB target: Cortex-A9, using DAP\n#\n# The debugger can connect to either core of the A9, but currently\n# not both simultaneously.  Change -coreid to 1 to connect to the\n# second core.\n#\nset _TARGETNAME $_CHIPNAME.cpu\n\n# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.\n# 0x80000000 is cpu0 coresight region\n#\n#\n# CORTEX_A8_PADDRDBG_CPU_SHIFT 13\n# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)\n\nset _coreid 0\nset _dbgbase [expr {0x80000000 | ($_coreid << 13)}]\necho \"Using dbgbase = [format 0x%x $_dbgbase]\"\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \\\n  -coreid 0 -dbgbase $_dbgbase\n\n# SRAM: 56KiB at 0x4030.0000\n$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000\n\n\n#\n# M3 targets, separate TAP/DAP for each core\n#\ndap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30\ndap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31\ntarget create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap\ntarget create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap\n\n\n# Once the JRC is up, enable our TAPs\njtag configure $_CHIPNAME.jrc -event setup \"\n\tjtag tapenable $_CHIPNAME.cpu\n\tjtag tapenable $_CHIPNAME.m30\n\tjtag tapenable $_CHIPNAME.m31\n\"\n\n# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset\n# ourselves using PRM_RSTCTRL.  1 is a warm reset, 2 a cold reset.\nset PRM_RSTCTRL 0x4A307B00\n$_TARGETNAME configure -event reset-assert \"$_TARGETNAME mww phys $PRM_RSTCTRL 0x1\"\n$_CHIPNAME.m30 configure -event reset-assert { }\n$_CHIPNAME.m31 configure -event reset-assert { }\n\n# Soft breakpoints don't currently work due to broken cache handling\ngdb_breakpoint_override hard\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/omap5912.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# TI OMAP5912 dual core processor\n# http://focus.ti.com/docs/prod/folders/print/omap5912.html\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME omap5912\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   # NOTE: validated with XOMAP5912 part\n   set _CPUTAPID 0x0692602f\n}\n\nadapter srst delay 100\n\n# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for\n# its standalone siblings (like TMS320VC5502) of the same era\n\n#jtag scan chain\njtag newtap $_CHIPNAME dsp -irlen 38 -expected-id 0x03df1d81\njtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID\njtag newtap $_CHIPNAME unknown -irlen 8\n\nset _TARGETNAME $_CHIPNAME.arm\ntarget create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME\n\nproc omap5912_reset {} {\n\t#\n\t# halt target\n\t#\n\tpoll\n\tsleep 1\n\thalt\n\twait_halt\n\t#\n\t# disable wdt\n\t#\n\tmww 0xfffec808 0x000000f5\n\tmww 0xfffec808 0x000000a0\n\n\tmww 0xfffeb048 0x0000aaaa\n\tsleep 500\n\tmww 0xfffeb048 0x00005555\n\tsleep 500\n}\n\n# omap5912 lcd frame buffer as working area\n$_TARGETNAME configure -work-area-phys 0x20000000 \\\n\t-work-area-size 0x3e800 -work-area-backup 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/omapl138.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments DaVinci family: OMAPL138\n#\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME omapl138\n}\n\nsource [find target/icepick.cfg]\n\n# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer\nif { [info exists ETB_TAPID] } {\n   set _ETB_TAPID $ETB_TAPID\n} else {\n   set _ETB_TAPID 0x2b900f0f\n}\njtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID -disable\njtag configure $_CHIPNAME.etb -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 3\"\n\n# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.\nif { [info exists CPU_TAPID] } {\n   set _CPU_TAPID $CPU_TAPID\n} else {\n   set _CPU_TAPID 0x07926001\n}\njtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID -disable\njtag configure $_CHIPNAME.arm -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 2\"\n\n# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan\nif { [info exists JRC_TAPID] } {\n   set _JRC_TAPID $JRC_TAPID\n} else {\n   set _JRC_TAPID 0x0b7d102f\n}\njtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version\n\njtag configure $_CHIPNAME.jrc -event setup \\\n\t\"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm\"\n\n################\n# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)\n# and the ETB memory (4K) are other options, while trace is unused.\n# Little-endian; use the OpenOCD default.\nset _TARGETNAME $_CHIPNAME.arm\n\ntarget create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME\n$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000\n\n# be absolutely certain the JTAG clock will work with the worst-case\n# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns\n# on the PLL and starts using it.  OK to speed up after clock setup.\nadapter speed 1500\n$_TARGETNAME configure -event \"reset-start\" { adapter speed 1500 }\n\narm7_9 fast_memory_access enable\narm7_9 dcc_downloads enable\n\n# trace setup\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n\ngdb_breakpoint_override hard\narm7_9 dbgrq enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/or1k.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset  _ENDIAN big\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME or1k\n}\n\nif { [info exists TAP_TYPE] } {\n   set _TAP_TYPE $TAP_TYPE\n} else {\n   puts \"You need to select a tap type\"\n   shutdown\n}\n\n# Configure the target\nif { [string compare $_TAP_TYPE \"VJTAG\"] == 0 } {\n\tif { [info exists FPGATAPID] } {\n\t   set _FPGATAPID $FPGATAPID\n\t} else {\n\t   puts \"You need to set your FPGA JTAG ID\"\n\t\tshutdown\n\t}\n\n\tjtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID\n\n\tset _TARGETNAME $_CHIPNAME.cpu\n\ttarget create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME\n\n\t# Select the TAP core we are using\n\ttap_select vjtag\n\n} elseif { [string compare $_TAP_TYPE \"XILINX_BSCAN\"] == 0 } {\n\n\tif { [info exists FPGATAPID] } {\n\t   set _FPGATAPID $FPGATAPID\n\t} else {\n\t   puts \"You need to set your FPGA JTAG ID\"\n\t\tshutdown\n\t}\n\n\tjtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_FPGATAPID\n\n\tset _TARGETNAME $_CHIPNAME.cpu\n\ttarget create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME\n\n\t# Select the TAP core we are using\n\ttap_select xilinx_bscan\n} else {\n\t# OpenCores Mohor JTAG TAP ID\n\tset _CPUTAPID  0x14951185\n\n\tjtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\n\n\tset _TARGETNAME $_CHIPNAME.cpu\n\ttarget create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME\n\n\t# Select the TAP core we are using\n\ttap_select mohor\n}\n\n# Select the debug unit core we are using. This debug unit as an option.\n\nset ADBG_USE_HISPEED\t\t1\nset ENABLE_JSP_SERVER\t\t2\nset ENABLE_JSP_MULTI\t\t4\n\n# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped\n# on burst reads and writes to improve download speeds.\n# This option must match the RTL configured option.\n\ndu_select adv [expr {$ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI}]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/pic32mx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME pic32mx\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x30938053\n}\n\n# default working area is 16384\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\nadapter srst delay 100\njtag_ntrst_delay 100\n\n#jtag scan chain\n#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME\n\n#\n# At reset the pic32mx does not allow code execution from RAM\n# we have to setup the BMX registers to allow this.\n# One limitation is that we loose the first 2k of RAM.\n#\n\nglobal _PIC32MX_DATASIZE\nglobal _WORKAREASIZE\nset _PIC32MX_DATASIZE 0x800\nset _PIC32MX_PROGSIZE [expr {$_WORKAREASIZE - $_PIC32MX_DATASIZE}]\n\n$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0\n$_TARGETNAME configure -event reset-init {\n\t#\n\t# from reset the pic32 cannot execute code in ram - enable ram execution\n\t# minimum offset from start of ram is 2k\n\t#\n\tglobal _PIC32MX_DATASIZE\n\tglobal _WORKAREASIZE\n\n\t# BMXCON\tset 0 wait state option by clearing BMXWSDRM bit, bit 6\n\tmww 0xbf882000 0x001f0000\n\t# BMXDKPBA: 2k kernel data @ 0xa0000000\n\tmww 0xbf882010 $_PIC32MX_DATASIZE\n\t# BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)\n\tmww 0xbf882020 $_WORKAREASIZE\n\t# BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)\n\tmww 0xbf882030 $_WORKAREASIZE\n\n\t#\n\t# Set system clock to 8Mhz if the default clock configuration is set\n\t#\n\n\t# SYSKEY register, make sure OSCCON is locked\n\tmww 0xbf80f230 0x0\n\t# SYSKEY register, write unlock sequence\n\tmww 0xbf80f230 0xaa996655\n\tmww 0xbf80f230 0x556699aa\n\t# OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1\n\tmww 0xbf80f004 0x07000000\n\t# SYSKEY register, relock OSCCON\n\tmww 0xbf80f230 0x0\n}\n\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME\n# add virtual banks for kseg0 and kseg1\nflash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME\nflash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME\n\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME\n# add virtual banks for kseg0 and kseg1\nflash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME\nflash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/psoc4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for Cypress PSoC 4 devices\n\n#\n# PSoC 4 devices support SWD transports only.\n#\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME psoc4\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 4kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x1000\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x0bb11477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME\n\nadapter speed 1500\n\n# Reset, bloody PSoC 4 reset\n#\n# 1) XRES (nSRST) resets also SWD DP so SWD line reset and DP reinit is needed.\n# High level adapter stops working after SRST and needs OpenOCD restart.\n# If your hw does not use SRST for other circuits, use sysresetreq instead\n#\n# 2) PSoC 4 executes initialization code from system ROM after reset.\n# This code subsequently jumps to user flash reset vector address.\n# Unfortunately the system ROM code is protected from reading and debugging.\n# Protection breaks vector catch VC_CORERESET used for \"reset halt\" by cortex_m.\n#\n# Cypress uses TEST_MODE flag to loop CPU in system ROM before executing code\n# from user flash. Programming specifications states that TEST_MODE flag must be\n# set in time frame 400 usec delayed about 1 msec from reset.\n#\n# OpenOCD have no standard way how to set TEST_MODE in specified time frame.\n# As a workaround the TEST_MODE flag is set before reset instead.\n# It worked for the oldest family PSoC4100/4200 even though it is not guaranteed\n# by specification.\n#\n# Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE\n# clear TEST_MODE flag during device reset so workaround is not possible.\n# Use a KitProg adapter for these devices or \"reset halt\" will not stop\n# before executing user code.\n#\n# 3) SWD cannot be connected during system initialization after reset.\n# This might be a reason for unconnecting ST-Link v2 when deasserting reset.\n# As a workaround arp_reset deassert is not called for hla\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\nproc psoc4_get_family_id {} {\n\tset err [catch {set romtable_pid [read_memory 0xF0000FE0 32 3]}]\n\tif { $err } {\n\t\treturn 0\n\t}\n\tif { [expr {[lindex $romtable_pid 0] & 0xffffff00 }]\n\t  || [expr {[lindex $romtable_pid 1] & 0xffffff00 }]\n\t  || [expr {[lindex $romtable_pid 2] & 0xffffff00 }] } {\n\t\techo \"Unexpected data in ROMTABLE\"\n\t\treturn 0\n\t}\n\tset designer_id [expr {(( [lindex $romtable_pid 1] & 0xf0 ) >> 4) | (( [lindex $romtable_pid 2] & 0xf ) << 4 ) }]\n\tif { $designer_id != 0xb4 } {\n\t\techo [format \"ROMTABLE Designer ID 0x%02x is not Cypress\" $designer_id]\n\t\treturn 0\n\t}\n\tset family_id [expr {( [lindex $romtable_pid 0] & 0xff ) | (( [lindex $romtable_pid 1] & 0xf ) << 8 ) }]\n\treturn $family_id\n}\n\nproc ocd_process_reset_inner { MODE } {\n\tglobal PSOC4_USE_ACQUIRE PSOC4_TEST_MODE_WORKAROUND\n\tglobal _TARGETNAME\n\n\tif { 0 != [string compare $_TARGETNAME [target names]] } {\n\t\treturn -code error \"PSoC 4 reset can handle only one $_TARGETNAME target\";\n\t}\n\tset t $_TARGETNAME\n\n\t# If this target must be halted...\n\tset halt -1\n\tif { 0 == [string compare $MODE halt] } {\n\t\tset halt 1\n\t}\n\tif { 0 == [string compare $MODE init] } {\n\t\tset halt 1;\n\t}\n\tif { 0 == [string compare $MODE run ] } {\n\t\tset halt 0;\n\t}\n\tif { $halt < 0 } {\n\t\treturn -code error \"Invalid mode: $MODE, must be one of: halt, init, or run\";\n\t}\n\n\tif { ! [info exists PSOC4_USE_ACQUIRE] } {\n\t\tif { 0 == [string compare [adapter name] kitprog ] } {\n\t\t\tset PSOC4_USE_ACQUIRE 1\n\t\t} else {\n\t\t\tset PSOC4_USE_ACQUIRE 0\n\t\t}\n\t}\n\tif { $PSOC4_USE_ACQUIRE } {\n\t\tset PSOC4_TEST_MODE_WORKAROUND 0\n\t} elseif { ! [info exists PSOC4_TEST_MODE_WORKAROUND] } {\n\t\tif { [psoc4_get_family_id] == 0x93 } {\n\t\t\tset PSOC4_TEST_MODE_WORKAROUND 1\n\t\t} else {\n\t\t\tset PSOC4_TEST_MODE_WORKAROUND 0\n\t\t}\n\t}\n\n\t#$t invoke-event reset-start\n\t$t invoke-event reset-assert-pre\n\n\tif { $halt && $PSOC4_USE_ACQUIRE } {\n\t\tcatch { [adapter name] acquire_psoc }\n\t\t$t arp_examine\n\t} else {\n\t\tif { $PSOC4_TEST_MODE_WORKAROUND } {\n\t\t\tset TEST_MODE 0x40030014\n\t\t\tif { $halt == 1 } {\n\t\t\t\tcatch { mww $TEST_MODE 0x80000000 }\n\t\t\t} else {\n\t\t\t\tcatch { mww $TEST_MODE 0 }\n\t\t\t}\n\t\t}\n\n\t\t$t arp_reset assert 0\n\t}\n\n\t$t invoke-event reset-assert-post\n\t$t invoke-event reset-deassert-pre\n\tif {![using_hla]} {\t# workaround ST-Link v2 fails and forcing reconnect\n\t\t$t arp_reset deassert 0\n\t}\n\t$t invoke-event reset-deassert-post\n\n\t# Pass 1 - Now wait for any halt (requested as part of reset\n\t# assert/deassert) to happen.  Ideally it takes effect without\n\t# first executing any instructions.\n\tif { $halt } {\n\t\t# Now PSoC CPU should loop in system ROM\n\t\t$t arp_waitstate running 200\n\t\t$t arp_halt\n\n\t\t# Catch, but ignore any errors.\n\t\tcatch { $t arp_waitstate halted 1000 }\n\n\t\t# Did we succeed?\n\t\tset s [$t curstate]\n\n\t\tif { 0 != [string compare $s \"halted\" ] } {\n\t\t\treturn -code error [format \"TARGET: %s - Not halted\" $t]\n\t\t}\n\n\t\t# Check if PSoC CPU is stopped in system ROM\n\t\tset pc [reg pc]\n\t\tregsub {pc[^:]*: } $pc \"\" pc\n\t\tif { $pc < 0x10000000 || $pc > 0x1000ffff } {\n\t\t\tset hint \"\"\n\t\t\tset family_id [psoc4_get_family_id]\n\t\t\tif { $family_id == 0x93 } {\n\t\t\t\tset hint \", use 'reset_config none'\"\n\t\t\t} elseif { $family_id > 0x93 } {\n\t\t\t\tset hint \", use a KitProg adapter\"\n\t\t\t}\n\t\t\treturn -code error [format \"TARGET: %s - Not halted in system ROM%s\" $t $hint]\n\t\t}\n\n\t\t# Set registers to reset vector values\n\t\tset value [read_memory 0x0 32 2]\n\t\treg pc [expr {[lindex $value 1] & 0xfffffffe}]\n\t\treg msp [lindex $value 0]\n\n\t\tif { $PSOC4_TEST_MODE_WORKAROUND } {\n\t\t\tcatch { mww $TEST_MODE 0 }\n\t\t}\n\t}\n\n\t#Pass 2 - if needed \"init\"\n\tif { 0 == [string compare init $MODE] } {\n\t\tset err [catch \"$t arp_waitstate halted 5000\"]\n\n\t\t# Did it halt?\n\t\tif { $err == 0 } {\n\t\t\t$t invoke-event reset-init\n\t\t}\n\t}\n\n\t$t invoke-event reset-end\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/psoc5lp.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Cypress PSoC 5LP\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME psoc5lp\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPU_TAPID $CPUTAPID\n} else {\n\tset _CPU_TAPID 0x4BA00477\n}\n\nif { [using_jtag] } {\n\tset _CPU_DAP_ID $_CPU_TAPID\n} else {\n\tset _CPU_DAP_ID 0x2ba01477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x2000\n}\n\n$_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \\\n                       -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nsource [find mem_helper.tcl]\n\n$_TARGETNAME configure -event reset-init {\n\t# Configure Target Device (PSoC 5LP Device Programming Specification 5.2)\n\n\tset PANTHER_DBG_CFG 0x4008000C\n\tset PANTHER_DBG_CFG_BYPASS [expr {1 << 1}]\n\tmmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0\n\n\tset PM_ACT_CFG0 0x400043A0\n\tmww $PM_ACT_CFG0 0xBF\n\n\tset FASTCLK_IMO_CR 0x40004200\n\tset FASTCLK_IMO_CR_F_RANGE_2    [expr {2 << 0}]\n\tset FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}]\n\tmmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK\n}\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME\n\nif {![using_hla]} {\n\tcortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/psoc6.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)\n# PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share\n# the same Flash/RAM/MMIO address space.\n#\n\nsource [find target/swj-dp.tcl]\n\nadapter speed 1000\n\nglobal _CHIPNAME\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME psoc6\n}\n\nglobal TARGET\nset TARGET $_CHIPNAME.cpu\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# Is CM0 Debugging enabled ?\nglobal _ENABLE_CM0\nif { [info exists ENABLE_CM0] } {\n\tset _ENABLE_CM0 $ENABLE_CM0\n} else {\n\tset _ENABLE_CM0 1\n}\n\n# Is CM4 Debugging enabled ?\nglobal _ENABLE_CM4\nif { [info exists ENABLE_CM4] } {\n\tset _ENABLE_CM4 $ENABLE_CM4\n} else {\n\tset _ENABLE_CM4 1\n}\n\nglobal _WORKAREASIZE_CM0\nif { [info exists WORKAREASIZE_CM0] } {\n\tset _WORKAREASIZE_CM0 $WORKAREASIZE_CM0\n} else {\n\tset _WORKAREASIZE_CM0 0x4000\n}\n\nglobal _WORKAREASIZE_CM4\nif { [info exists WORKAREASIZE_CM4] } {\n\tset _WORKAREASIZE_CM4 $WORKAREASIZE_CM4\n} else {\n\tset _WORKAREASIZE_CM4 0x4000\n}\n\nglobal _WORKAREAADDR_CM0\nif { [info exists WORKAREAADDR_CM0] } {\n\tset _WORKAREAADDR_CM0 $WORKAREAADDR_CM0\n} else {\n\tset _WORKAREAADDR_CM0 0x08000000\n}\n\nglobal _WORKAREAADDR_CM4\nif { [info exists WORKAREAADDR_CM4] } {\n\tset _WORKAREAADDR_CM4 $WORKAREAADDR_CM4\n} else {\n\tset _WORKAREAADDR_CM4 0x08000000\n}\n\nproc init_reset { mode } {\n\tglobal RESET_MODE\n\tset RESET_MODE $mode\n\n\tif {[using_jtag]} {\n\t\tjtag arp_init-reset\n\t}\n}\n\n# Utility to make 'reset halt' work as reset;halt on a target\n# It does not prevent running code after reset\nproc psoc6_deassert_post { target } {\n\t# PSoC6 cleared AP registers including TAR during reset\n\t# Force examine to synchronize OpenOCD target status\n\t$target arp_examine\n\n\tglobal RESET_MODE\n\tglobal TARGET\n\n\tif { $RESET_MODE ne \"run\" } {\n\t\t$target arp_poll\n\t\t$target arp_poll\n\t\tset st [$target curstate]\n\n\t\tif { $st eq \"reset\" } {\n\t\t\t# we assume running state follows\n\t\t\t# if reset accidentally halts, waiting is useless\n\t\t\tcatch { $target arp_waitstate running 100 }\n\t\t\tset st [$target curstate]\n\t\t}\n\n\t\tif { $st eq \"running\" } {\n\t\t\techo \"$target: Ran after reset and before halt...\"\n\t\t\tif { $target eq \"${TARGET}.cm0\" } {\n\t\t\t\t# Try to cleanly reset whole system\n\t\t\t\t# and halt the CM0 at entry point\n\t\t\t\tpsoc6 reset_halt\n\t\t\t\t$target arp_waitstate halted 100\n\t\t\t} else {\n\t\t\t\t$target arp_halt\n\t\t\t}\n\t\t}\n\t}\n}\n\nif { $_ENABLE_CM0 } {\n\ttarget create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0\n\t${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0\n\n\tflash bank main_flash_cm0\t\tpsoc6 0x10000000 0 0 0 ${TARGET}.cm0\n\tflash bank work_flash_cm0\t\tpsoc6 0x14000000 0 0 0 ${TARGET}.cm0\n\tflash bank super_flash_user_cm0\tpsoc6 0x16000800 0 0 0 ${TARGET}.cm0\n\tflash bank super_flash_nar_cm0\tpsoc6 0x16001A00 0 0 0 ${TARGET}.cm0\n\tflash bank super_flash_key_cm0\tpsoc6 0x16005A00 0 0 0 ${TARGET}.cm0\n\tflash bank super_flash_toc2_cm0\tpsoc6 0x16007C00 0 0 0 ${TARGET}.cm0\n\n\t${TARGET}.cm0 cortex_m reset_config sysresetreq\n\t${TARGET}.cm0 configure -event reset-deassert-post \"psoc6_deassert_post ${TARGET}.cm0\"\n}\n\nif { $_ENABLE_CM4 } {\n\ttarget create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1\n\t${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0\n\n\tflash bank main_flash_cm4\t\tpsoc6 0x10000000 0 0 0 ${TARGET}.cm4\n\tflash bank work_flash_cm4\t\tpsoc6 0x14000000 0 0 0 ${TARGET}.cm4\n\tflash bank super_flash_user_cm4\tpsoc6 0x16000800 0 0 0 ${TARGET}.cm4\n\tflash bank super_flash_nar_cm4\tpsoc6 0x16001A00 0 0 0 ${TARGET}.cm4\n\tflash bank super_flash_key_cm4\tpsoc6 0x16005A00 0 0 0 ${TARGET}.cm4\n\tflash bank super_flash_toc2_cm4\tpsoc6 0x16007C00 0 0 0 ${TARGET}.cm4\n\n\t${TARGET}.cm4 cortex_m reset_config vectreset\n\t${TARGET}.cm4 configure -event reset-deassert-post \"psoc6_deassert_post ${TARGET}.cm4\"\n}\n\nif { $_ENABLE_CM0 } {\n\t# Use CM0+ by default on dual-core devices\n\ttargets ${TARGET}.cm0\n}\n\nif {[using_jtag]} {\n\tjtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/pxa255.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.\n# This chip is now at end-of-life.  Final orders have been taken.\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME pxa255\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x69264013\n}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME xscale -endian $_ENDIAN \\\n\t-chain-position $_CHIPNAME.cpu\n\n# PXA255 comes out of reset using 3.6864 MHz oscillator.\n# Until the PLL kicks in, keep the JTAG clock slow enough\n# that we get no errors.\nadapter speed 300\n$_TARGETNAME configure -event \"reset-start\" { adapter speed 300 }\n\n# both TRST and SRST are *required* for debug\n# DCSR is often accessed with SRST active\nreset_config trst_and_srst separate srst_nogate\n\n# reset processing that works with PXA\nproc init_reset {mode} {\n\t# assert both resets; equivalent to power-on reset\n\tadapter assert trst assert srst\n\n\t# drop TRST after at least 32 cycles\n\tsleep 1\n\tadapter deassert trst assert srst\n\n\t# minimum 32 TCK cycles to wake up the controller\n\truntest 50\n\n\t# now the TAP will be responsive; validate scanchain\n\tjtag arp_init\n\n\t# ... and take it out of reset\n\tadapter deassert trst deassert srst\n}\n\nproc jtag_init {} {\n\tinit_reset startup\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/pxa270.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#Marvell/Intel PXA270 Script\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME pxa270\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n#IDs for pxa270. Are there more?\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n  # set useful default\n   set _CPUTAPID 0x49265013\n}\n\nif { [info exists CPUTAPID2] } {\n   set _CPUTAPID2 $CPUTAPID2\n} else {\n  # set useful default\n   set _CPUTAPID2 0x79265013\n}\n\nif { [info exists CPUTAPID3] } {\n   set _CPUTAPID2 $CPUTAPID3\n} else {\n  # set useful default\n   set _CPUTAPID3 0x89265013\n}\n\n# set adapter srst delay to the delay introduced by your reset circuit\n# the rest of the needed delays are built into the openocd program\nadapter srst delay 260\n# set the jtag_ntrst_delay to the delay introduced by a reset circuit\n# the rest of the needed delays are built into the openocd program\njtag_ntrst_delay 250\n\nset _TARGETNAME $_CHIPNAME.cpu\njtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3\n\ntarget create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME\n# maps to PXA internal RAM. If you are using a PXA255\n# you must initialize SDRAM or leave this option off\n$_TARGETNAME configure -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/pxa3xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Marvell PXA3xx\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME pxa3xx\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# IDs for all currently known PXA3xx chips\nif { [info exists CPUTAPID_PXA30X_A0] } {\n   set _CPUTAPID_PXA30X_A0 $CPUTAPID_PXA30X_A0\n} else {\n   set _CPUTAPID_PXA30X_A0 0x0E648013\n}\nif { [info exists CPUTAPID_PXA30X_A1] } {\n   set _CPUTAPID_PXA30X_A1 $CPUTAPID_PXA30X_A1\n} else {\n   set _CPUTAPID_PXA30X_A1 0x1E648013\n}\nif { [info exists CPUTAPID_PXA31X_A0] } {\n   set _CPUTAPID_PXA31X_A0 $CPUTAPID_PXA31X_A0\n} else {\n   set _CPUTAPID_PXA31X_A0 0x0E649013\n}\nif { [info exists CPUTAPID_PXA31X_A1] } {\n   set _CPUTAPID_PXA31X_A1 $CPUTAPID_PXA31X_A1\n} else {\n   set _CPUTAPID_PXA31X_A1 0x1E649013\n}\nif { [info exists CPUTAPID_PXA31X_A2] } {\n   set _CPUTAPID_PXA31X_A2 $CPUTAPID_PXA31X_A2\n} else {\n   set _CPUTAPID_PXA31X_A2 0x2E649013\n}\nif { [info exists CPUTAPID_PXA31X_B0] } {\n   set _CPUTAPID_PXA31X_B0 $CPUTAPID_PXA31X_B0\n} else {\n   set _CPUTAPID_PXA31X_B0 0x3E649013\n}\nif { [info exists CPUTAPID_PXA32X_B1] } {\n   set _CPUTAPID_PXA32X_B1 $CPUTAPID_PXA32X_B1\n} else {\n   set _CPUTAPID_PXA32X_B1 0x5E642013\n}\nif { [info exists CPUTAPID_PXA32X_B2] } {\n   set _CPUTAPID_PXA32X_B2 $CPUTAPID_PXA32X_B2\n} else {\n   set _CPUTAPID_PXA32X_B2 0x6E642013\n}\nif { [info exists CPUTAPID_PXA32X_C0] } {\n   set _CPUTAPID_PXA32X_C0 $CPUTAPID_PXA32X_C0\n} else {\n   set _CPUTAPID_PXA32X_C0 0x7E642013\n}\n\n# set adapter srst delay to the delay introduced by your reset circuit\n# the rest of the needed delays are built into the openocd program\nadapter srst delay 260\n\n# set the jtag_ntrst_delay to the delay introduced by a reset circuit\n# the rest of the needed delays are built into the openocd program\njtag_ntrst_delay 250\n\nset _TARGETNAME $_CHIPNAME.cpu\njtag newtap $_CHIPNAME cpu -irlen 11 -ircapture 0x1 -irmask 0x7f \\\n\t-expected-id $_CPUTAPID_PXA30X_A0 \\\n\t-expected-id $_CPUTAPID_PXA30X_A1 \\\n\t-expected-id $_CPUTAPID_PXA31X_A0 \\\n\t-expected-id $_CPUTAPID_PXA31X_A1 \\\n\t-expected-id $_CPUTAPID_PXA31X_A2 \\\n\t-expected-id $_CPUTAPID_PXA31X_B0 \\\n\t-expected-id $_CPUTAPID_PXA32X_B1 \\\n\t-expected-id $_CPUTAPID_PXA32X_B2 \\\n\t-expected-id $_CPUTAPID_PXA32X_C0\n\ntarget create $_TARGETNAME xscale -endian $_ENDIAN \\\n\t-chain-position $_TARGETNAME\n\n# work area in internal RAM.\n$_TARGETNAME configure -work-area-phys 0x5c030000 -work-area-size 0x10000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/qn908x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# NXP QN908x Cortex-M4F with 128 KiB SRAM\n\nsource [find target/swj-dp.tcl]\n\nset CHIPNAME qn908x\nset CHIPSERIES qn9080\nif { ![info exists WORKAREASIZE] } {\n  set WORKAREASIZE 0x20000\n}\n\n# SWD IDCODE (Cortex M4).\nset CPUTAPID 0x2ba01477\n\nswj_newdap $CHIPNAME cpu -irlen 4 -expected-id $CPUTAPID\ndap create $CHIPNAME.dap -chain-position $CHIPNAME.cpu\n\nset TARGETNAME $CHIPNAME.cpu\ntarget create $TARGETNAME cortex_m -dap $CHIPNAME.dap\n\n# SRAM is mapped at 0x04000000.\n$TARGETNAME configure -work-area-phys 0x04000000 -work-area-size $WORKAREASIZE\n\n# flash bank <name> qn908x <base> <size> 0 0 <target#> [calc_checksum]\n# The base must be set as 0x01000000, and the size parameter is unused.\nset FLASHNAME $CHIPNAME.flash\nflash bank $FLASHNAME qn908x 0x01000000 0 0 0 $TARGETNAME calc_checksum\n\n# We write directly to flash memory over this adapter interface. For debugging\n# this could in theory be faster (the Core clock on reset is normally at 32MHz),\n# but for flashing 1MHz is more reliable.\nadapter speed 1000\n\n# Delay on reset line.\nadapter srst delay 200\n\ncortex_m reset_config sysresetreq\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/qualcomm_qca4531.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable\n# Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT).\n#\n# Product page:\n# https://www.qualcomm.com/products/qca4531\n#\n# Notes:\n# - MIPS Processor ID (PRId): 0x00019374\n# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,\n#   operating at up to 650 MHz\n# - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up\n#   to 300 MHz\n# - TRST is not available.\n# - EJTAG PrRst signal is not supported\n# - RESET_L pin B56 on the SoC will reset internal JTAG logic.\n#\n# Pins related for debug and bootstrap:\n# Name\t\tPin\t\tDescription\n#   JTAG\n# JTAG_TCK\tGPIO0, (A27)\tSoftware configurable, default JTAG\n# JTAG_TDI\tGPIO1, (B23)\tSoftware configurable, default JTAG\n# JTAG_TDO\tGPIO2, (A28)\tSoftware configurable, default JTAG\n# JTAG_TMS\tGPIO3, (A29)\tSoftware configurable, default JTAG\n#   Reset\n# RESET_L\t-, (B56)\tInput only\n# SYS_RST_L\tGPIO17, (A79)\tOutput reset request or GPIO\n#   Bootstrap\n# JTAG_MODE\tGPIO16, (A78)\t0 - JTAG (Default); 1 - EJTAG\n# DDR_SELECT\tGPIO10, (A57)\t0 - DDR2; 1 - DDR1\n#   UART\n# UART0_SOUT\tGPIO10, (A57)\n# UART0_SIN\tGPIO9, (B49)\n\n# Per default we need to use \"none\" variant to be able properly \"reset init\"\n# or \"reset halt\" the CPU.\nreset_config none srst_pulls_trst\n\n# For SRST based variant we still need proper timings.\n# For ETH part the reset should be asserted at least for 10ms\n# Since there is no other information let's take 100ms to be sure.\nadapter srst pulse_width 100\n\n# according to the SoC documentation it should take at least 5ms from\n# reset end till bootstrap end. In the practice we need 8ms to get JTAG back\n# to live.\nadapter srst delay 8\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $_CHIPNAME\n} else {\n\tset _CHIPNAME qca4531\n}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME\n\n# provide watchdog helper.\nproc disable_watchdog { } {\n\tmww 0xb8060008 0x0\n}\n\n$_TARGETNAME configure -event halted { disable_watchdog }\n\n# Since PrRst is not supported and SRST will reset complete chip\n# with JTAG engine, we need to reset CPU from CPU itself.\n$_TARGETNAME configure -event reset-assert-pre {\n\thalt\n}\n\n$_TARGETNAME configure -event reset-assert {\n\tcatch \"mww 0xb806001C 0x01000000\"\n}\n\n# To be able to trigger complete chip reset, in case JTAG is blocked\n# or CPU not responding, we still can use this helper.\nproc full_reset { } {\n\treset_config srst_only\n\treset\n\thalt\n\treset_config none\n}\n\n# Section with helpers which can be used by boards\nproc qca4531_ddr2_550_550_init {} {\n\t# Clear reset flags for different SoC components\n\tmww 0xb806001c 0xfeceffff\n\tmww 0xb806001c 0xeeceffff\n\tmww 0xb806001c 0xe6ceffff\n\n\t# PMU configurations\n\t# Internal Switcher\n\tmww 0xb8116c40 0x633c8176\n\t# Increase the DDR voltage\n\tmww 0xb8116c44 0x10200000\n\t# XTAL Configurations\n\tmww 0xb81162c0 0x4b962100\n\tmww 0xb81162c4 0x480\n\tmww 0xb81162c8 0x04000144\n\t# Recommended PLL configurations\n\tmww 0xb81161c4 0x54086000\n\tmww 0xb8116244 0x54086000\n\n\t# PLL init\n\tmww 0xb8050008 0x0131001c\n\tmww 0xb8050000 0x40001580\n\tmww 0xb8050004 0x40015800\n\tmww 0xb8050008 0x0131001c\n\tmww 0xb8050000 0x00001580\n\tmww 0xb8050004 0x00015800\n\tmww 0xb8050008 0x01310000\n\tmww 0xb8050044 0x781003ff\n\tmww 0xb8050048 0x003c103f\n\n\t# DDR2 init\n\tmww 0xb8000108 0x401f0042\n\tmww 0xb80000b8 0x0000166d\n\tmww 0xb8000000 0xcfaaf33b\n\tmww 0xb800015c 0x0000000f\n\tmww 0xb8000004 0xa272efa8\n\tmww 0xb8000018 0x0000ffff\n\tmww 0xb80000c4 0x74444444\n\tmww 0xb80000c8 0x00000444\n\tmww 0xb8000004 0xa210ee28\n\tmww 0xb8000004 0xa2b2e1a8\n\tmww 0xb8000010 0x8\n\tmww 0xb80000bc 0x0\n\tmww 0xb8000010 0x10\n\tmww 0xb80000c0 0x0\n\tmww 0xb8000010 0x40\n\tmww 0xb800000c 0x2\n\tmww 0xb8000010 0x2\n\tmww 0xb8000008 0xb43\n\tmww 0xb8000010 0x1\n\tmww 0xb8000010 0x8\n\tmww 0xb8000010 0x4\n\tmww 0xb8000010 0x4\n\tmww 0xb8000008 0xa43\n\tmww 0xb8000010 0x1\n\tmww 0xb800000c 0x382\n\tmww 0xb8000010 0x2\n\tmww 0xb800000c 0x402\n\tmww 0xb8000010 0x2\n\tmww 0xb8000014 0x40be\n\tmww 0xb800001C 0x20\n\tmww 0xb8000020 0x20\n\tmww 0xb80000cc 0xfffff\n\n\t# UART GPIO programming\n\tmww 0xb8040000 0xff30b\n\tmww 0xb8040044 0x908\n\tmww 0xb8040034 0x160000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/quark_d20xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x38289013\n}\n\njtag newtap quark_d20xx quark -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable\njtag newtap quark_d20xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e786013 -enable\n\nproc quark_d20xx_tapenable {} {\n\techo \"enabling quark core tap\"\n\tirscan quark_d20xx.cltap 0x11\n\tdrscan quark_d20xx.cltap 12 1\n\truntest 10\n}\n\nproc quark_d20xx_tapdisable {} {\n\techo \"disabling quark core tap\"\n\tirscan quark_d20xx.cltap 0x11\n\tdrscan quark_d20xx.cltap 12 0\n\truntest 10\n}\n\nproc quark_d20xx_setup {} {\n\tjtag tapenable quark_d20xx.quark\n}\n\njtag configure quark_d20xx.quark -event tap-enable \\\n   \"quark_d20xx_tapenable\"\n\njtag configure quark_d20xx.quark -event tap-disable \\\n   \"quark_d20xx_tapdisable\"\n\ntarget create quark_d20xx.quark quark_d20xx -endian little -chain-position quark_d20xx.quark\n\nquark_d20xx.quark configure -event reset-start {\n\t# need to halt the target to write to memory\n\tif {[quark_d20xx.quark curstate] ne \"halted\"} { halt }\n\t# set resetbreak via the core tap\n\tirscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x1\n\t# trigger a warm reset\n\tmww 0xb0800570 0x2\n\t# clear resetbreak\n\tirscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x0\n}\n\njtag configure quark_d20xx.quark -event setup \\\n   \"quark_d20xx_setup\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/quark_x10xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME quark_x10xx\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x18289013\n}\n\njtag newtap quark_x10xx cpu   -irlen 8  -irmask 0xff  -expected-id   $_CPUTAPID  -disable\njtag newtap quark_x10xx cltap -irlen 8  -irmask 0xff  -expected-id   0x0e681013  -enable\n\n#openocd puts tap at front of chain not end of chain\nproc quark_x10xx_tapenable {} {\n\techo \"enabling core tap\"\n\tirscan quark_x10xx.cltap 0x11\n\tdrscan quark_x10xx.cltap 64 1\n\truntest 10\n}\n\nproc quark_x10xx_tapdisable {} {\n\techo \"disabling core tap\"\n\tirscan quark_x10xx.cltap 0x11\n\tdrscan quark_x10xx.cltap 64 0\n\truntest 10\n}\n\nproc quark_x10xx_setup {} {\n\tjtag tapenable quark_x10xx.cpu\n}\n\njtag configure $_CHIPNAME.cpu -event tap-enable \\\n   \"quark_x10xx_tapenable\"\n\njtag configure $_CHIPNAME.cpu -event tap-disable \\\n   \"quark_x10xx_tapdisable\"\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create quark_x10xx.cpu quark_x10xx -endian $_ENDIAN -chain-position quark_x10xx.cpu\n\njtag configure $_CHIPNAME.cpu -event setup \\\n   \"quark_x10xx_setup\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/readme.txt",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nPrerequisites:\nThe users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands\ndo the same thing across all the targets.\n\nRules to follow when writing scripts:\n\n1. The configuration script should be defined such as , for example, the following sequences are working:\n\treset\n\tflash info <bank>\nand\n\treset\n\tflash erase_address <start> <len>\nand\n\treset init\n\tload\n\nIn most cases this can be accomplished by specifying the default startup mode as reset_init (target command\nin the configuration file).\n\n2. If the target is correctly configured, flash must be writable without any other helper commands. It is\nassumed that all write-protect mechanisms should be disabled.\n\n3. The configuration scripts should be defined such as the binary that was written to flash verifies\n(turn off remapping, checksums, etc...)\n\nflash write_image [file] <parameters>\nverify_image [file] <parameters>\n\n4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked\nmultiple times only the last setting is used.\n\ninterface/xxx.cfg files are always executed *before* target/xxx.cfg\nfiles, so any adapter speed in interface/xxx.cfg will be overridden by\ntarget/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively,\nset the default JTAG speed.\n\nNote that a target/xxx.cfg file can invoke another target/yyy.cfg file,\nso one can create target subtype configurations where e.g. only\namount of DRAM, oscillator speeds differ and having a single\nconfig file for the default/common settings.\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/renesas_r7s72100.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas RZ/A1H\n# https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x4ba00477\n}\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME r7s72100\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID\n\n# Configuring only one core using DAP.\n# Base addresses of cores:\n#  core 0  -  0x80030000\nset _TARGETNAME $_CHIPNAME.ca9\ndap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu\ntarget create ${_TARGETNAME} cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x80030000\n\ntargets ${_TARGETNAME}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/renesas_rcar_gen2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas R-Car Generation 2 SOCs\n# - There are a combination of Cortex-A15s and Cortex-A7s for each Gen2 SOC\n# - Each SOC can boot through any of the, up to 2, core types that it has\n#   e.g. H2 can boot through Cortex-A15 or Cortex-A7\n\n# Supported Gen2 SOCs and their cores:\n# H2:  Cortex-A15 x 4, Cortex-A7 x 4\n# M2:  Cortex-A15 x 2\n# V2H: Cortex-A15 x 2\n# M2N: Cortex-A15 x 2\n# E2:                  Cortex-A7 x 2\n\n# Usage:\n# There are 2 configuration options:\n# SOC:       Selects the supported SOC. (Default 'H2')\n# BOOT_CORE: Selects the booting core. 'CA15', or 'CA7'\n#            Defaults to 'CA15' if the SOC has one, else defaults to 'CA7'\n\nif { [info exists SOC] } {\n\tset _soc $SOC\n} else {\n\tset _soc H2\n}\n\n# Set configuration for each SOC and the default 'BOOT_CORE'\nswitch $_soc {\n\tH2 {\n\t\tset _CHIPNAME r8a7790\n\t\tset _num_ca15 4\n\t\tset _num_ca7 4\n\t\tset _boot_core CA15\n\t}\n\tM2 {\n\t\tset _CHIPNAME r8a7791\n\t\tset _num_ca15 2\n\t\tset _num_ca7 0\n\t\tset _boot_core CA15\n\t}\n\tV2H {\n\t\tset _CHIPNAME r8a7792\n\t\tset _num_ca15 2\n\t\tset _num_ca7 0\n\t\tset _boot_core CA15\n\t}\n\tM2N {\n\t\tset _CHIPNAME r8a7793\n\t\tset _num_ca15 2\n\t\tset _num_ca7 0\n\t\tset _boot_core CA15\n\t}\n\tE2 {\n\t\tset _CHIPNAME r8a7794\n\t\tset _num_ca15 0\n\t\tset _num_ca7 2\n\t\tset _boot_core CA7\n\t}\n\tdefault {\n\t\terror \"'$_soc' is invalid!\"\n\t}\n}\n\n# If configured, override the default 'CHIPNAME'\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n}\n\n# If configured, override the default 'BOOT_CORE'\nif { [info exists BOOT_CORE] } {\n\tset _boot_core $BOOT_CORE\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x4ba00477\n}\n\necho \"\\t$_soc - $_num_ca15 CA15(s), $_num_ca7 CA7(s)\"\necho \"\\tBoot Core - $_boot_core\\n\"\n\nset _DAPNAME $_CHIPNAME.dap\n\n# TAP and DAP\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID\ndap create $_DAPNAME -chain-position $_CHIPNAME.cpu\n\nset CA15_DBGBASE {0x800B0000 0x800B2000 0x800B4000 0x800B6000}\nset CA7_DBGBASE  {0x800F0000 0x800F2000 0x800F4000 0x800F6000}\n\nset _targets \"\"\nset smp_targets \"\"\n\nproc setup_ca {core_name dbgbase num boot} {\n\tglobal _CHIPNAME\n\tglobal _DAPNAME\n\tglobal smp_targets\n\tglobal _targets\n\tfor { set _core 0 } { $_core < $num } { incr _core } {\n\t\tset _TARGETNAME $_CHIPNAME.$core_name.$_core\n\t\tset _CTINAME $_TARGETNAME.cti\n\t\tset _command \"target create $_TARGETNAME cortex_a -dap $_DAPNAME \\\n\t\t\t-coreid $_core -dbgbase [lindex $dbgbase $_core]\"\n\t\tif { $_core == 0  && $boot == 1 } {\n\t\t\tset _targets \"$_TARGETNAME\"\n\t\t} else {\n\t\t\tset _command \"$_command -defer-examine\"\n\t\t}\n\t\tset smp_targets \"$smp_targets $_TARGETNAME\"\n\t\teval $_command\n\t}\n}\n\n# Organize target list based on the boot core\nif { [string equal $_boot_core CA15] } {\n\tsetup_ca a15 $CA15_DBGBASE $_num_ca15 1\n\tsetup_ca a7  $CA7_DBGBASE  $_num_ca7 0\n} elseif { [string equal $_boot_core CA7] } {\n\tsetup_ca a7  $CA7_DBGBASE  $_num_ca7 1\n\tsetup_ca a15 $CA15_DBGBASE $_num_ca15 0\n} else {\n\tsetup_ca a15 $CA15_DBGBASE $_num_ca15 0\n\tsetup_ca a7  $CA7_DBGBASE  $_num_ca7 0\n}\n\nsource [find target/renesas_rcar_reset_common.cfg]\n\neval \"target smp $smp_targets\"\ntargets $_targets\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/renesas_rcar_gen3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas R-Car Generation 3 SOCs\n# - There are a combination of Cortex-A57s, Cortex-A53s, and Cortex-R7 for each Gen3 SOC\n# - Each SOC can boot through any of the, up to 3, core types that it has\n#   e.g. H3 can boot through Cortex-A57, Cortex-A53, or Cortex-R7\n\n# Supported Gen3 SOCs and their cores:\n#  H3: Cortex-A57 x 4, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)\n# M3W: Cortex-A57 x 2, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)\n# M3N: Cortex-A57 x 2,                 Cortex-R7 x 2 (Lock-Step)\n# V3U:                 Cortex-A76 x 8, Cortex-R52 x2 (Lock-Step)\n# V3H:                 Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)\n# V3M:                 Cortex-A53 x 2, Cortex-R7 x 2 (Lock-Step)\n#  E3:                 Cortex-A53 x 1, Cortex-R7 x 2 (Lock-Step)\n#  D3:                 Cortex-A53 x 1\n\n# Usage:\n# There are 2 configuration options:\n# SOC:       Selects the supported SOC. (Default 'H3')\n# BOOT_CORE: Selects the booting core. 'CA57', 'CA53', or 'CR7'\n#            Defaults to 'CA57' if the SOC has one, else defaults to 'CA53'\n\nif { [info exists SOC] } {\n\tset _soc $SOC\n} else {\n\tset _soc H3\n}\n\nset _num_ca53 0\nset _num_ca57 0\nset _num_ca76 0\nset _num_cr52 0\nset _num_cr7 0\n\n# Set configuration for each SOC and the default 'BOOT_CORE'\nswitch $_soc {\n\tH3 {\n\t\tset _CHIPNAME r8a77950\n\t\tset _num_ca57 4\n\t\tset _num_ca53 4\n\t\tset _num_cr7 1\n\t\tset _boot_core CA57\n\t}\n\tM3W {\n\t\tset _CHIPNAME r8a77960\n\t\tset _num_ca57 2\n\t\tset _num_ca53 4\n\t\tset _num_cr7 1\n\t\tset _boot_core CA57\n\t}\n\tM3N {\n\t\tset _CHIPNAME r8a77965\n\t\tset _num_ca57 2\n\t\tset _num_ca53 4\n\t\tset _num_cr7 1\n\t\tset _boot_core CA57\n\t}\n\tV3M {\n\t\tset _CHIPNAME r8a77970\n\t\tset _num_ca57 0\n\t\tset _num_ca53 2\n\t\tset _num_cr7 1\n\t\tset _boot_core CA53\n\t}\n\tV3H {\n\t\tset _CHIPNAME r8a77980\n\t\tset _num_ca57 0\n\t\tset _num_ca53 4\n\t\tset _num_cr7 1\n\t\tset _boot_core CA53\n\t}\n\tE3 {\n\t\tset _CHIPNAME r8a77990\n\t\tset _num_ca57 0\n\t\tset _num_ca53 1\n\t\tset _num_cr7 1\n\t\tset _boot_core CA53\n\t}\n\tD3 {\n\t\tset _CHIPNAME r8a77995\n\t\tset _num_ca57 0\n\t\tset _num_ca53 1\n\t\tset _num_cr7 0\n\t\tset _boot_core CA53\n\t}\n\tV3U {\n\t\tset _CHIPNAME r8a779a0\n\t\tset _num_ca76 8\n\t\tset _num_cr52 1\n\t\tset _boot_core CA76\n\t}\n\tdefault {\n\t\terror \"'$_soc' is invalid!\"\n\t}\n}\n\n# If configured, override the default 'CHIPNAME'\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n}\n\n# If configured, override the default 'BOOT_CORE'\nif { [info exists BOOT_CORE] } {\n\tset _boot_core $BOOT_CORE\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x5ba00477\n}\n\necho \"\\t$_soc - $_num_ca76 CA76(s), $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr52 CR52(s), $_num_cr7 CR7(s)\"\necho \"\\tBoot Core - $_boot_core\\n\"\n\nset _DAPNAME $_CHIPNAME.dap\n\n# TAP and DAP\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID\ndap create $_DAPNAME -chain-position $_CHIPNAME.cpu\n\nset CA76_DBGBASE {0x81410000 0x81510000 0x81610000 0x81710000 0x81c10000 0x81d10000 0x81e10000 0x81f10000}\nset CA76_CTIBASE {0x81420000 0x81520000 0x81620000 0x81720000 0x81c20000 0x81d20000 0x81e20000 0x81f20000}\nset CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}\nset CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}\nset CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}\nset CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}\nset CR52_DBGBASE 0x80c10000\nset CR52_CTIBASE 0x80c20000\nset  CR7_DBGBASE 0x80910000\nset  CR7_CTIBASE 0x80918000\n\nset _targets \"\"\nset smp_targets \"\"\n\nproc setup_a5x {core_name dbgbase ctibase num boot} {\n\tglobal _CHIPNAME\n\tglobal _DAPNAME\n\tglobal smp_targets\n\tglobal _targets\n\tfor { set _core 0 } { $_core < $num } { incr _core } {\n\t\tset _TARGETNAME $_CHIPNAME.$core_name.$_core\n\t\tset _CTINAME $_TARGETNAME.cti\n\t\tcti create $_CTINAME -dap $_DAPNAME -ap-num 1 \\\n\t\t\t-baseaddr [lindex $ctibase $_core]\n\t\tset _command \"target create $_TARGETNAME aarch64 -dap $_DAPNAME \\\n\t\t\t-ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME\"\n\t\tif { $_core == 0  && $boot == 1 } {\n\t\t\tset _targets \"$_TARGETNAME\"\n\t\t} else {\n\t\t\tset _command \"$_command -defer-examine\"\n\t\t}\n\t\tset smp_targets \"$smp_targets $_TARGETNAME\"\n\t\teval $_command\n\t}\n}\n\nproc setup_crx {core_name dbgbase ctibase num boot} {\n\tglobal _CHIPNAME\n\tglobal _DAPNAME\n\tfor { set _core 0 } { $_core < $num } { incr _core } {\n\t\tset _TARGETNAME $_CHIPNAME.$core_name\n\t\tset _CTINAME $_TARGETNAME.cti\n\t\tcti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase\n\t\tif { $core_name == \"r52\" } {\n\t\t\tset _command \"target create $_TARGETNAME armv8r -dap $_DAPNAME \\\n\t\t\t\t-ap-num 1 -dbgbase $dbgbase -cti $_CTINAME\"\n\t\t} else {\n\t\t\tset _command \"target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \\\n\t\t\t\t-ap-num 1 -dbgbase $dbgbase\"\n\t\t}\n\t\tif { $boot == 1 } {\n\t\t\tset _targets \"$_TARGETNAME\"\n\t\t} else {\n\t\t\tset _command \"$_command -defer-examine\"\n\t\t}\n\t\teval $_command\n\t}\n}\n\n# Organize target list based on the boot core\nif { [string equal $_boot_core CA76] } {\n\tsetup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 1\n\tsetup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0\n} elseif { [string equal $_boot_core CA57] } {\n\tsetup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1\n\tsetup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0\n\tsetup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0\n} elseif { [string equal $_boot_core CA53] } {\n\tsetup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1\n\tsetup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0\n\tsetup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  0\n} elseif { [string equal $_boot_core CR52] } {\n\tsetup_crx r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1\n\tsetup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 0\n} else {\n\tsetup_crx r7  $CR7_DBGBASE  $CR7_CTIBASE  $_num_cr7  1\n\tsetup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0\n\tsetup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0\n}\n\nsource [find target/renesas_rcar_reset_common.cfg]\n\neval \"target smp $smp_targets\"\ntargets $_targets\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/renesas_rcar_reset_common.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas R-Car Gen2 Evaluation Board common settings\n\nreset_config trst_and_srst srst_nogate\n\nproc init_reset {mode} {\n    # Assert both resets: equivalent to a power-on reset\n    adapter assert trst assert srst\n\n    # Deassert TRST to begin TAP communication\n    adapter deassert trst assert srst\n\n    # TAP should now be responsive, validate the scan-chain\n    jtag arp_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/renesas_rz_five.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas RZ/Five SoC\n#\n# General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz)\n\ntransport select jtag\n\nreset_config trst_and_srst srst_gates_jtag\nadapter speed 4000\nadapter srst delay 500\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME r9A07g043u\n}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME riscv -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/renesas_rz_g2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Renesas RZ/G2 SOCs\n# - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7\n# and Cortex-M33 for each SOC\n# - Each SOC can boot through the Cortex-A5x cores\n\n# Supported RZ/G2 SOCs and their cores:\n# RZ/G2H:   Cortex-A57 x4, Cortex-A53 x4, Cortex-R7\n# RZ/G2M:   Cortex-A57 x2, Cortex-A53 x4, Cortex-R7\n# RZ/G2N:   Cortex-A57 x2,                Cortex-R7\n# RZ/G2E:                  Cortex-A53 x2, Cortex-R7\n# RZ/G2L:                  Cortex-A55 x2, Cortex-M33\n# RZ/G2LC:                 Cortex-A55 x2, Cortex-M33\n# RZ/G2UL:                 Cortex-A55 x1, Cortex-M33\n\n# Usage:\n# There are 2 configuration options:\n# SOC:       Selects the supported SOC. (Default 'G2L')\n# BOOT_CORE: Selects the booting core. 'CA57', 'CA53' or 'CA55'\n\ntransport select jtag\nreset_config trst_and_srst srst_gates_jtag\nadapter speed 4000\nadapter srst delay 500\n\nif { [info exists SOC] } {\n\tset _soc $SOC\n} else {\n\tset _soc G2L\n}\n\nset _num_ca57 0\nset _num_ca55 0\nset _num_ca53 0\nset _num_cr7 0\nset _num_cm33 0\n\n# Set configuration for each SOC and the default 'BOOT_CORE'\nswitch $_soc {\n\tG2H {\n\t\tset _CHIPNAME r8a774ex\n\t\tset _num_ca57 4\n\t\tset _num_ca53 4\n\t\tset _num_cr7 1\n\t\tset _boot_core CA57\n\t\tset _ap_num 1\n\t}\n\tG2M {\n\t\tset _CHIPNAME r8a774ax\n\t\tset _num_ca57 2\n\t\tset _num_ca53 4\n\t\tset _num_cr7 1\n\t\tset _boot_core CA57\n\t\tset _ap_num 1\n\t}\n\tG2N {\n\t\tset _CHIPNAME r8a774bx\n\t\tset _num_ca57 2\n\t\tset _num_ca53 0\n\t\tset _num_cr7 1\n\t\tset _boot_core CA57\n\t\tset _ap_num 1\n\t}\n\tG2E {\n\t\tset _CHIPNAME r8a774c0\n\t\tset _num_ca57 0\n\t\tset _num_ca53 2\n\t\tset _num_cr7 1\n\t\tset _boot_core CA53\n\t\tset _ap_num 1\n\t}\n\tG2L {\n\t\tset _CHIPNAME r9a07g044l\n\t\tset _num_ca55 2\n\t\tset _num_cm33 1\n\t\tset _boot_core CA55\n\t\tset _ap_num 0\n\t}\n\tG2LC {\n\t\tset _CHIPNAME r9a07g044c\n\t\tset _num_ca55 2\n\t\tset _num_cm33 1\n\t\tset _boot_core CA55\n\t\tset _ap_num 0\n\t}\n\tG2UL {\n\t\tset _CHIPNAME r9a07g043u\n\t\tset _num_ca55 1\n\t\tset _num_cm33 1\n\t\tset _boot_core CA55\n\t\tset _ap_num 0\n\t}\n\tdefault {\n\t\terror \"'$_soc' is invalid!\"\n\t}\n}\n\n# If configured, override the default 'CHIPNAME'\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n}\n\n# If configured, override the default 'BOOT_CORE'\nif { [info exists BOOT_CORE] } {\n\tset _boot_core $BOOT_CORE\n}\n\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x6ba00477\n}\n\necho \"\\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s), \\\n\t$_num_cm33 CM33(s)\"\necho \"\\tBoot Core - $_boot_core\\n\"\n\nset _DAPNAME $_CHIPNAME.dap\n\n\n# TAP and DAP\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID \\\n\t-ignore-version\ndap create $_DAPNAME -chain-position $_CHIPNAME.cpu\necho \"$_CHIPNAME.cpu\"\n\nset CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}\nset CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}\nset CA55_DBGBASE {0x10E10000 0x10F10000}\nset CA55_CTIBASE {0x10E20000 0x10F20000}\nset CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}\nset CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}\nset  CR7_DBGBASE 0x80910000\nset  CR7_CTIBASE 0x80918000\nset CM33_DBGBASE 0xE000E000\nset CM33_CTIBASE 0xE0042000\n\nset smp_targets \"\"\n\nproc setup_a5x {core_name dbgbase ctibase num boot} {\n\tfor { set _core 0 } { $_core < $num } { incr _core } {\n\t\tset _TARGETNAME $::_CHIPNAME.$core_name.$_core\n\t\tset _CTINAME $_TARGETNAME.cti\n\t\tcti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \\\n\t\t\t-baseaddr [lindex $ctibase $_core]\n\t\ttarget create $_TARGETNAME aarch64 -dap $::_DAPNAME \\\n\t\t\t-ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME\n\t\tif { $_core > 0 || $boot == 0 } {\n\t\t\t$_TARGETNAME configure -defer-examine\n\t\t}\n\t\tset ::smp_targets \"$::smp_targets $_TARGETNAME\"\n\t}\n}\n\nproc setup_cr7 {dbgbase ctibase} {\n\tset _TARGETNAME $::_CHIPNAME.r7\n\tset _CTINAME $_TARGETNAME.cti\n\tcti create $_CTINAME -dap $::_DAPNAME -ap-num 1 -baseaddr $ctibase\n\ttarget create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \\\n\t\t-ap-num 1 -dbgbase $dbgbase -defer-examine\n}\n\nproc setup_cm33 {dbgbase ctibase} {\n        set _TARGETNAME $::_CHIPNAME.m33\n        set _CTINAME $_TARGETNAME.cti\n        cti create $_CTINAME -dap $::_DAPNAME -ap-num 2 -baseaddr $ctibase\n        target create $_TARGETNAME cortex_m -dap $::_DAPNAME \\\n                -ap-num 2 -dbgbase $dbgbase -defer-examine\n}\n\n# Organize target list based on the boot core\nif { $_boot_core == \"CA57\" } {\n\tsetup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1\n\tsetup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0\n\tsetup_cr7 $CR7_DBGBASE $CR7_CTIBASE\n} elseif { $_boot_core == \"CA53\" } {\n\tsetup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1\n\tsetup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0\n\tsetup_cr7 $CR7_DBGBASE $CR7_CTIBASE\n} elseif { $_boot_core == \"CA55\" } {\n\tsetup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1\n\tsetup_cm33 $CM33_DBGBASE $CM33_CTIBASE\n}\necho \"SMP targets:$smp_targets\"\neval \"target smp $smp_targets\"\n\nif { $_soc == \"G2L\" || $_soc == \"G2LC\" || $_soc == \"G2UL\" } {\n\ttarget create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1\n}\n\nproc init_reset {mode} {\n    # Assert both resets: equivalent to a power-on reset\n    adapter assert trst assert srst\n\n    # Deassert TRST to begin TAP communication\n    adapter deassert trst assert srst\n\n    # TAP should now be responsive, validate the scan-chain\n    jtag arp_init\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/renesas_s7g2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Renesas Synergy S7 G2 w/ ARM Cortex-M4 @ 240 MHz\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME s7g2\n}\n\nif { [info exists CPU_JTAG_TAPID] } {\n\tset _CPU_JTAG_TAPID $CPU_JTAG_TAPID\n} else {\n\tset _CPU_JTAG_TAPID 0x5ba00477\n}\n\nif { [info exists CPU_SWD_TAPID] } {\n\tset _CPU_SWD_TAPID $CPU_SWD_TAPID\n} else {\n\tset _CPU_SWD_TAPID 0x5ba02477\n}\n\nsource [find target/swj-dp.tcl]\n\nif { [using_jtag] } {\n\tset _CPU_TAPID $_CPU_JTAG_TAPID\n} else {\n\tset _CPU_TAPID $_CPU_SWD_TAPID\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\t# 640 KB On-Chip SRAM\n\tset _WORKAREASIZE 0xa0000\n}\n\n$_TARGETNAME configure -work-area-phys 0x1ffe0000 \\\n                       -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nif { ![using_hla] } {\n\tcortex_m reset_config sysresetreq\n}\n\nadapter speed 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/rk3308.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Rockchip RK3308 Target\n# https://rockchip.fr/RK3308%20datasheet%20V1.5.pdf\n# https://dl.radxa.com/rockpis/docs/hw/datasheets/Rockchip%20RK3308TRM%20V1.1%20Part1-20180810.pdf\n\nif { [info exists CHIPNAME] } {\n  set _CHIPNAME $CHIPNAME\n} else {\n  set _CHIPNAME rk3308\n}\n\n#\n# Main DAP\n#\nif { [info exists DAP_TAPID] } {\n   set _DAP_TAPID $DAP_TAPID\n} else {\n   set _DAP_TAPID 0x2ba01477\n}\n\nadapter speed 12000\n\ntransport select swd\n\n# declare the one SWD tap to access the DAP\nswd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version\n\n# create the DAP\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0\n\n# declare the 4 main application cores\nset _TARGETNAME $_CHIPNAME.core\nset _smp_command \"\"\n\nset $_TARGETNAME.base(0) 0x81010000\nset $_TARGETNAME.base(1) 0x81012000\nset $_TARGETNAME.base(2) 0x81014000\nset $_TARGETNAME.base(3) 0x81016000\n\nset $_TARGETNAME.cti(0) 0x81018000\nset $_TARGETNAME.cti(1) 0x81019000\nset $_TARGETNAME.cti(2) 0x8101a000\nset $_TARGETNAME.cti(3) 0x8101b000\n\nset _cores 4\nfor { set _core 0 } { $_core < $_cores } { incr _core 1 } {\n\n    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0\n\n    set _command \"target create ${_TARGETNAME}$_core aarch64 \\\n                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \\\n                         -dbgbase [set $_TARGETNAME.base($_core)]\"\n\n    if { $_core != 0 } {\n        set _smp_command \"$_smp_command ${_TARGETNAME}$_core\"\n        set _command \"$_command -defer-examine\"\n    } else {\n        # uncomment to use hardware threads pseudo rtos\n        # set _command \"$_command -rtos hwthread\"\n        set _command \"$_command -work-area-size 0x40000 -work-area-phys 0xfff80000 \\\n                                -work-area-backup 0\"\n        set _smp_command \"target smp ${_TARGETNAME}$_core\"\n    }\n\n    eval $_command\n}\n\neval $_smp_command\n\ntargets ${_TARGETNAME}0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/rk3399.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Rockchip RK3399 Target\n# https://rockchip.fr/RK3399%20datasheet%20V1.8.pdf\n# https://rockchip.fr/Rockchip%20RK3399%20TRM%20V1.4%20Part1.pdf\n\nif { [info exists CHIPNAME] } {\n  set _CHIPNAME $CHIPNAME\n} else {\n  set _CHIPNAME rk3399\n}\n\n#\n# Main DAP\n#\nif { [info exists DAP_TAPID] } {\n   set _DAP_TAPID $DAP_TAPID\n} else {\n   set _DAP_TAPID 0x5ba02477\n}\n\nadapter speed 12000\n\ntransport select swd\n\n# declare the one SWD tap to access the DAP\nswd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version\n\n# create the DAP\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0\nset _TARGETNAME $_CHIPNAME.lcore\n# declare the 6 main application cores\nset _smp_command \"\"\n\nset $_TARGETNAME.base(0) 0x80030000\nset $_TARGETNAME.base(1) 0x80032000\nset $_TARGETNAME.base(2) 0x80034000\nset $_TARGETNAME.base(3) 0x80036000\nset $_TARGETNAME.cti(0) 0x80038000\nset $_TARGETNAME.cti(1) 0x80039000\nset $_TARGETNAME.cti(2) 0x8003a000\nset $_TARGETNAME.cti(3) 0x8003b000\n\n\nset _TARGETNAME $_CHIPNAME.bcore\nset $_TARGETNAME.base(4) 0x80210000\nset $_TARGETNAME.base(5) 0x80310000\nset $_TARGETNAME.cti(4) 0x80220000\nset $_TARGETNAME.cti(5) 0x80320000\n\nset _cores 6\nfor { set _core 0 } { $_core < $_cores } { incr _core 1 } {\n    if {$_core < 4} {\n        set _TARGETNAME $_CHIPNAME.lcore\n    } else {\n        set _TARGETNAME $_CHIPNAME.bcore\n    }\n\n\n    cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 1\n\n    target create ${_TARGETNAME}$_core aarch64 \\\n                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \\\n                         -dbgbase [set $_TARGETNAME.base($_core)]\n\n    if { $_core != 0 } {\n        ${_TARGETNAME}$_core configure -defer-examine\n    } else {\n        # uncomment to use hardware threads pseudo rtos\n        # ${_TARGETNAME}$_core configure -rtos hwthread\"\n        ${_TARGETNAME}$_core configure -work-area-size 0x30000 -work-area-phys 0xff8c0000 \\\n                                -work-area-backup 0\n    }\n    set _smp_command \"$_smp_command ${_TARGETNAME}$_core\"\n}\n\ntarget smp $_smp_command\n\ntargets rk3399.lcore0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/rp2040.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# RP2040 is a microcontroller with dual Cortex-M0+ core.\n# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html\n\n# The device requires multidrop SWD for debug.\ntransport select swd\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME rp2040\n}\n\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x10000\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x01002927\n}\n\n# Set to '1' to start rescue mode\nif { [info exists RESCUE] } {\n\tset _RESCUE $RESCUE\n} else {\n\tset _RESCUE 0\n}\n\n# Set to '0' or '1' for single core configuration, 'SMP' for -rtos hwthread\n# handling of both cores, anything else for isolated debugging of both cores\nif { [info exists USE_CORE] } {\n\tset _USE_CORE $USE_CORE\n} else {\n\tset _USE_CORE SMP\n}\nset _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }]\n\nswj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID\n\n# The rescue debug port uses the DP CTRL/STAT bit DBGPWRUPREQ to reset the\n# PSM (power on state machine) of the RP2040 with a flag set in the\n# VREG_AND_POR_CHIP_RESET register. Once the reset is released\n# (by clearing the DBGPWRUPREQ flag), the bootrom will run, see this flag,\n# and halt. Allowing the user to load some fresh code, rather than loading\n# the potentially broken code stored in flash\nif { $_RESCUE } {\n\tdap create $_CHIPNAME.rescue_dap -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0xf -ignore-syspwrupack\n\tinit\n\n\t# Clear DBGPWRUPREQ\n\t$_CHIPNAME.rescue_dap dpreg 0x4 0x00000000\n\n\t# Verifying CTRL/STAT is 0\n\tset _CTRLSTAT [$_CHIPNAME.rescue_dap dpreg 0x4]\n\tif {[expr {$_CTRLSTAT & 0xf0000000}]} {\n\t\techo \"Rescue failed, DP CTRL/STAT readback $_CTRLSTAT\"\n\t} else {\n\t\techo \"Now restart OpenOCD without RESCUE flag and load code to RP2040\"\n\t}\n\tshutdown\n}\n\n# core 0\nif { $_USE_CORE != 1 } {\n\tdap create $_CHIPNAME.dap0 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0\n\tset _TARGETNAME_0 $_CHIPNAME.core0\n\ttarget create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0\n\t# srst does not exist; use SYSRESETREQ to perform a soft reset\n\t$_TARGETNAME_0 cortex_m reset_config sysresetreq\n}\n\n# core 1\nif { $_USE_CORE != 0 } {\n\tdap create $_CHIPNAME.dap1 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 1\n\tset _TARGETNAME_1 $_CHIPNAME.core1\n\ttarget create $_TARGETNAME_1 cortex_m -dap $_CHIPNAME.dap1 -coreid 1\n\t$_TARGETNAME_1 cortex_m reset_config sysresetreq\n}\n\nif {[string compare $_USE_CORE SMP] == 0} {\n\t$_TARGETNAME_0 configure  -rtos hwthread\n\t$_TARGETNAME_1 configure  -rtos hwthread\n\ttarget smp $_TARGETNAME_0 $_TARGETNAME_1\n}\n\nif { $_USE_CORE == 1 } {\n\tset _FLASH_TARGET $_TARGETNAME_1\n} else {\n\tset _FLASH_TARGET $_TARGETNAME_0\n}\n# Backup the work area. The flash probe runs an algorithm on the target CPU.\n# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).\n$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET\n\nif { $_BOTH_CORES } {\n\t# Alias to ensure gdb connecting to core 1 gets the correct memory map\n\tflash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME\n\n\t# Select core 0\n\ttargets $_TARGETNAME_0\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/rsl10.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# RSL10: ARM Cortex-M3\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME rsl10\n}\n\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x8000\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x2ba01477\n}\n\nswj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# TODO: configure reset\n# reset_config srst_only srst_nogate connect_assert_srst\n\n$_TARGETNAME configure -event examine-fail rsl10_lock_warning\n\nproc rsl10_check_connection {} {\n    set target [target current]\n    set dap [$target cget -dap]\n\n\tset IDR [$dap apreg 0 0xfc]\n\tif {$IDR != 0x24770011} {\n\t\techo \"Error: Cannot access RSL10 AP, maybe connection problem!\"\n\t\treturn 1\n\t}\n    return 0\n}\n\nproc rsl10_lock_warning {} {\n    if {[rsl10_check_connection]} {return}\n\n    poll off\n    echo \"****** WARNING ******\"\n    echo \"RSL10 device probably has lock engaged.\"\n    echo \"Debug access is denied.\"\n    echo \"Use 'rsl10 unlock key1 key2 key3 key4' to erase and unlock the device.\"\n    echo \"****** ....... ******\"\n    echo \"\"\n}\n\nflash bank $_CHIPNAME.main rsl10 0x00100000 0x60000 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.nvr1 rsl10 0x00080000 0x800 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.nvr2 rsl10 0x00080800 0x800 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.nvr3 rsl10 0x00081000 0x800 0 0 $_TARGETNAME\n\n# TODO: implement flashing for nvr4\n# flash bank $_CHIPNAME.nvr4 rsl10 0x00081800 0x400 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/rtl872xd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n# Realtek RTL872xD (ARM Cortex-M33 + M23, wifi+bt dualband soc)\n\n# HLA does not support AP other than 0\nif { [using_hla] } {\n        echo \"ERROR: HLA transport cannot work with this target.\"\n        shutdown\n}\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n        set _CHIPNAME $CHIPNAME\n} else {\n        set _CHIPNAME rtl872xd\n}\n\nif { [info exists CPUTAPID] } {\n        set _CPUTAPID $CPUTAPID\n} else {\n        set _CPUTAPID 0x6ba02477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME.km0 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1\ntarget create $_TARGETNAME.km4 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 2\n\ncortex_m reset_config sysresetreq\n\nadapter speed 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/samsung_s3c2410.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Found on the 'TinCanTools' Hammer board.\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME s3c2410\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n  # This config file was defaulting to big endian..\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   # Force an error until we get a good number.\n   set _CPUTAPID 0xffffffff\n}\n\n#use combined on interfaces or targets that cannot set TRST/SRST separately\nreset_config trst_and_srst\n\n#jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0\n\n# speed up memory downloads\narm7_9 fast_memory_access enable\narm7_9 dcc_downloads enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/samsung_s3c2440.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Target configuration for the Samsung 2440 system on chip\n# Tested on a S3C2440 Evaluation board by keesj\n# Processor       : ARM920Tid(wb) rev 0 (v4l)\n# Info:   JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME s3c2440\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n  # this defaults to a bigendian\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x0032409d\n}\n\n#jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1\n\n#reset configuration\nreset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/samsung_s3c2450.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Target configuration for the Samsung 2450 system on chip\n# Processor       : ARM926ejs (wb) rev 0 (v4l)\n# Info:   JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F\n\n\n# FIX!!! what to use here?\n#\n# RCLK?\n#\n# adapter speed 0\n#\n# Really low clock during reset?\n#\n# adapter speed 1\n\nif { [info exists CHIPNAME] } {\n  set _CHIPNAME $CHIPNAME\n} else {\n  set _CHIPNAME s3c2450\n}\n\nif { [info exists ENDIAN] } {\n  set _ENDIAN $ENDIAN\n} else {\n # this defaults to a bigendian\n  set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n  set _CPUTAPID $CPUTAPID\n} else {\n  set _CPUTAPID 0x07926f0f\n}\n\n#jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# FIX!!!!! should this really use srst_pulls_trst?\n# With srst_pulls_trst \"reset halt\" will not reset into the\n# halted mode, but rather \"reset run\" and then halt the target.\n#\n# However, without \"srst_pulls_trst\", then \"reset halt\" produces weird\n# errors:\n# WARNING: unknown debug reason: 0x0\nreset_config trst_and_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/samsung_s3c4510.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME s3c4510\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n\n# This appears to be a \"Version 1\" arm7tdmi.\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x1f0f0f0f\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/samsung_s3c6410.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# -*- tcl -*-\n# Target configuration for the Samsung s3c6410 system on chip\n# Tested on a SMDK6410\n# Processor       : ARM1176\n# Info:   JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)\n# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]\n# [and I do not believe it to be accurate, hence the 0xffffffff below]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME s3c6410\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n  # this defaults to a bigendian\n   set _ENDIAN little\n}\n\n# trace buffer\nif { [info exists ETBTAPID] } {\n   set _ETBTAPID $ETBTAPID\n} else {\n   set _ETBTAPID 0x2b900f0f\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07b76f0f\n}\n\n#jtag scan chain\n\njtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETBTAPID\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME\n\nadapter srst delay 500\njtag_ntrst_delay 500\n\n#reset configuration\nreset_config trst_and_srst\n\n# trace setup ... NOTE, \"normal full\" mode fudges the real ETMv3.1 mode\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/sharp_lh79532.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nreset_config srst_only srst_pulls_trst\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME lh79532\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n  # sharp changed the number!\n   set _CPUTAPID 0x00002061\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/sim3x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Silicon Laboratories SiM3x Cortex-M3\n#\n\n# SiM3x devices support both JTAG and SWD transports.\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME SiM3x\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x4ba00477\n}\n\nif { [info exists CPURAMSIZE] } {\n  set _CPURAMSIZE $CPURAMSIZE\n} else {\n# Minimum size of RAM in the Silicon Labs product matrix (8KB)\n\tset _CPURAMSIZE 0x2000\n}\n\nif { [info exists CPUROMSIZE] } {\n  set _CPUROMSIZE $CPUROMSIZE\n} else {\n# Minimum size of FLASH in the Silicon Labs product matrix (32KB)\n\tset _CPUROMSIZE 0x8000\n}\n\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE $_CPURAMSIZE\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME\n\nadapter speed 1000\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/smp8634.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for Sigma Designs SMP8634 (eventually even SMP8635)\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME smp8634\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x08630001\n}\n\nadapter srst delay 100\njtag_ntrst_delay 100\n\nreset_config trst_and_srst separate\n\n# jtag scan chain\n# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\njtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian $_ENDIAN\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/snps_em_sk_fpga.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2014-2015,2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\n#\n# Xilinx Spartan-6 XC6SLX45  FPGA on EM Starter Kit v1.\n# Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2.\n#\n\nsource [find cpu/arc/em.tcl]\n\nset _CHIPNAME arc-em\nset _TARGETNAME $_CHIPNAME.cpu\n\n# EM SK IDENTITY is 0x200444b1\n# EM SK v2 IDENTITY is 0x200044b1\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \\\n  -expected-id 0x200044b1\n\nset _coreid 0\nset _dbgbase [expr {0x00000000 | ($_coreid << 13)}]\n\ntarget create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \\\n  -coreid 0 -dbgbase $_dbgbase -endian little\n\n# There is no SRST, so do a software reset\n$_TARGETNAME configure -event reset-assert \"arc_em_reset $_TARGETNAME\"\n\narc_em_init_regs\n\n# vim:ft=tcl\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/snps_hsdk.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) 2019,2020 Synopsys, Inc.\n#  Anton Kolesov <anton.kolesov@synopsys.com>\n#  Didin Evgeniy <didin@synopsys.com>\n\n#\n# HS Development Kit SoC.\n#\n# Contains quad-core ARC HS38.\n#\n\nsource [find cpu/arc/hs.tcl]\n\nset _coreid 0\nset _dbgbase [expr {$_coreid << 13}]\n\n# CHIPNAME will be used to choose core family (600, 700 or EM). As far as\n# OpenOCD is concerned EM and HS are identical.\nset _CHIPNAME arc-em\n\n# OpenOCD discovers JTAG TAPs in reverse order.\n\n# ARC HS38 core 4\nset _TARGETNAME $_CHIPNAME.cpu4\njtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1\n\ntarget create $_TARGETNAME arcv2 -chain-position $_TARGETNAME\n$_TARGETNAME configure -coreid $_coreid\n$_TARGETNAME configure -dbgbase $_dbgbase\n# Flush L2$.\n$_TARGETNAME configure -event reset-assert \"arc_hs_reset $_TARGETNAME\"\nset _coreid [expr {$_coreid + 1}]\nset _dbgbase [expr {$_coreid << 13}]\n\narc_hs_init_regs\n\n# Enable L2 cache support for core 4.\n$_TARGETNAME arc cache l2 auto 1\n\n# ARC HS38 core 3\nset _TARGETNAME $_CHIPNAME.cpu3\njtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1\n\ntarget create $_TARGETNAME arcv2 -chain-position $_TARGETNAME\n$_TARGETNAME configure -coreid $_coreid\n$_TARGETNAME configure -dbgbase $_dbgbase\n$_TARGETNAME configure -event reset-assert \"arc_common_reset $_TARGETNAME\"\nset _coreid [expr {$_coreid + 1}]\nset _dbgbase [expr {$_coreid << 13}]\n\narc_hs_init_regs\n\n# Enable L2 cache support for core 3.\n$_TARGETNAME arc cache l2 auto 1\n\n# ARC HS38 core 2\nset _TARGETNAME $_CHIPNAME.cpu2\njtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1\n\ntarget create $_TARGETNAME arcv2 -chain-position $_TARGETNAME\n$_TARGETNAME configure -coreid $_coreid\n$_TARGETNAME configure -dbgbase $_dbgbase\n$_TARGETNAME configure -event reset-assert \"arc_common_reset $_TARGETNAME\"\nset _coreid [expr {$_coreid + 1}]\nset _dbgbase [expr {$_coreid << 13}]\n\narc_hs_init_regs\n\n# Enable L2 cache support for core 2.\n$_TARGETNAME arc cache l2 auto 1\n\n# ARC HS38 core 1\nset _TARGETNAME $_CHIPNAME.cpu1\njtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1\n\ntarget create $_TARGETNAME arcv2 -chain-position $_TARGETNAME\n$_TARGETNAME configure -coreid $_coreid\n$_TARGETNAME configure -dbgbase $_dbgbase\n$_TARGETNAME configure -event reset-assert \"arc_common_reset $_TARGETNAME\"\nset _coreid [expr {$_coreid + 1}]\nset _dbgbase [expr {0x00000000 | ($_coreid << 13)}]\narc_hs_init_regs\n\n# Enable L2 cache support for core 1.\n$_TARGETNAME arc cache l2 auto 1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/snps_hsdk_4xd.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Copyright (C) 2023 Synopsys, Inc.\n# Artemiy Volkov <artemiy@synopsys.com>\n\n# Adapted from tcl/target/snps_hsdk.cfg.\n\n#\n# HS Development Kit SoC.\n#\n# Contains quad-core ARC HS47D.\n#\n\nsource [find cpu/arc/hs.tcl]\n\nset _coreid 0\nset _dbgbase [expr {$_coreid << 13}]\n\n# CHIPNAME will be used to choose core family (600, 700 or EM). As far as\n# OpenOCD is concerned EM and HS are identical.\nset _CHIPNAME arc-em\n\n\nproc setup_cpu {core_index expected_id} {\n\tglobal _coreid\n\tglobal _dbgbase\n\tglobal _CHIPNAME\n\n\tset _TARGETNAME $_CHIPNAME.cpu$core_index\n\tjtag newtap $_CHIPNAME cpu$core_index -irlen 4 -ircapture 0x1 -expected-id $expected_id\n\n\ttarget create $_TARGETNAME arcv2 -chain-position $_TARGETNAME\n\t$_TARGETNAME configure -coreid $_coreid\n\t$_TARGETNAME configure -dbgbase $_dbgbase\n\t$_TARGETNAME configure -event reset-assert \"arc_hs_reset $_TARGETNAME\"\n\n\tarc_hs_init_regs\n\n\t$_TARGETNAME arc cache l2 auto 1\n\n\tset _coreid [expr {$_coreid + 1}]\n\tset _dbgbase [expr {$_coreid << 13}]\n}\n\n# OpenOCD discovers JTAG TAPs in reverse order.\n\nsetup_cpu 4 0x100c54b1\nsetup_cpu 3 0x100854b1\nsetup_cpu 2 0x100454b1\nsetup_cpu 1 0x100054b1\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/spear3xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Target configuration for the ST SPEAr3xx family of system on chip\n# Supported SPEAr300, SPEAr310, SPEAr320\n# http://www.st.com/spear\n#\n# Processor: ARM926ejs\n# Info:      JTAG tap: spear3xx.cpu tap/device found: 0x07926041\n# Date:      2009-10-31\n# Author:    Antonio Borneo <borneo.antonio@gmail.com>\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME spear3xx\n}\n\nif { [info exists ENDIAN] } {\n\tset _ENDIAN $ENDIAN\n} else {\n\tset _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x07926041\n}\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x03 \\\n\t-expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN \\\n\t-chain-position $_TARGETNAME\n\n# SPEAr3xx has a 8K block of sram @ 0xd280.0000\n# REVISIT: what OS puts virtual address equal to phys?\n$_TARGETNAME configure \\\n\t-work-area-virt 0xd2800000 \\\n\t-work-area-phys 0xd2800000 \\\n\t-work-area-size 0x2000 \\\n\t-work-area-backup 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stellaris.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# TI/Luminary Stellaris LM3S chip family\n\n# Some devices have errata in returning their device class.\n# DEVICECLASS is provided as a manual override\n# Manual setting of a device class of 0xff is not allowed\n\nglobal _DEVICECLASS\n\nif { [info exists DEVICECLASS] } {\n   set _DEVICECLASS $DEVICECLASS\n} else {\n   set _DEVICECLASS 0xff\n}\n\n# Luminary chips support both JTAG and SWD transports.\n# Adapt based on what transport is active.\nsource [find target/swj-dp.tcl]\n\n# For now we ignore the SPI and UART options, which\n# are usable only for ISP style initial flash programming.\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME lm3s\n}\n\n# CPU TAP ID 0x1ba00477 for early Sandstorm parts\n# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2\n# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)\n# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)\n# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)\n# ... we'll ignore the JTAG version field, rather than list every\n# chip revision that turns up.\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x0ba00477\n}\n\n# SWD DAP, and JTAG TAP, take same params for now;\n# ... even though SWD ignores all except TAPID, and\n# JTAG shouldn't need anything more then irlen. (and TAPID).\nswj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \\\n    -expected-id $_CPUTAPID -ignore-version\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   # default to 2K working area\n   set _WORKAREASIZE 0x800\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n# 8K working area at base of ram, not backed up\n#\n# NOTE: you may need or want to reconfigure the work area;\n# some parts have just 6K, and you may want to use other\n# addresses (at end of mem not beginning) or back it up.\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE\n\n# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;\n# LM3S parts don't support RTCK\n#\n# NOTE: this may be increased by a reset-init handler, after it\n# configures and enables the PLL.  Or you might need to decrease\n# this, if you're using a slower clock.\nadapter speed 500\n\nsource [find mem_helper.tcl]\n\nproc reset_peripherals {family} {\n\n\tsource [find chip/ti/lm3s/lm3s.tcl]\n\n\techo \"Resetting Core Peripherals\"\n\n\t# Disable the PLL and the system clock divider (nop if disabled)\n\tmmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV\n\tmmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0\n\n\t# RCC and RCC2 to their reset values\n\tmww $SYSCTL_RCC [expr {0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS)}]\n\tmww $SYSCTL_RCC2 0x07806810\n\tmww $SYSCTL_RCC 0x078e3ad1\n\n\t# Reset the deep sleep clock configuration register\n\tmww $SYSCTL_DSLPCLKCFG 0x07800000\n\n\t# Reset the clock gating registers\n\tmww $SYSCTL_RCGC0 0x00000040\n\tmww $SYSCTL_RCGC1 0\n\tmww $SYSCTL_RCGC2 0\n\tmww $SYSCTL_SCGC0 0x00000040\n\tmww $SYSCTL_SCGC1 0\n\tmww $SYSCTL_SCGC2 0\n\tmww $SYSCTL_DCGC0 0x00000040\n\tmww $SYSCTL_DCGC1 0\n\tmww $SYSCTL_DCGC2 0\n\n\t# Reset the remaining SysCtl registers\n\tmww $SYSCTL_PBORCTL 0\n\tmww $SYSCTL_IMC 0\n\tmww $SYSCTL_GPIOHBCTL 0\n\tmww $SYSCTL_MOSCCTL 0\n\tmww $SYSCTL_PIOSCCAL 0\n\tmww $SYSCTL_I2SMCLKCFG 0\n\n\t# Reset the peripherals\n\tmww $SYSCTL_SRCR0 0xffffffff\n\tmww $SYSCTL_SRCR1 0xffffffff\n\tmww $SYSCTL_SRCR2 0xffffffff\n\tmww $SYSCTL_SRCR0 0\n\tmww $SYSCTL_SRCR1 0\n\tmww $SYSCTL_SRCR2 0\n\n\t# Clear any pending SysCtl interrupts\n\tmww $SYSCTL_MISC 0xffffffff\n\n\t# Wait for any pending flash operations to complete\n\twhile {[expr {[mrw $FLASH_FMC] & 0xffff}] != 0} { sleep 1 }\n\twhile {[expr {[mrw $FLASH_FMC2] & 0xffff}] != 0} { sleep 1 }\n\n\t# Reset the flash controller registers\n\tmww $FLASH_FMA 0\n\tmww $FLASH_FCIM 0\n\tmww $FLASH_FCMISC 0xffffffff\n\tmww $FLASH_FWBVAL 0\n}\n\n$_TARGETNAME configure -event reset-start {\n\tadapter speed 500\n\n\t#\n\t# When nRST is asserted on most Stellaris devices, it clears some of\n\t# the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;\n\t# and OpenOCD depends on those TRMs.  So we won't use SRST on those\n\t# chips.  (Only power-on reset should affect debug state, beyond a\n\t# few specified bits; not the chip's nRST input, wired to SRST.)\n\t#\n\t# REVISIT current errata specs don't seem to cover this issue.\n\t# Do we have more details than this email?\n\t#   https://lists.berlios.de/pipermail\n\t#\t/openocd-development/2008-August/003065.html\n\t#\n\n\tglobal _DEVICECLASS\n\n\tif {$_DEVICECLASS != 0xff} {\n\t   set device_class $_DEVICECLASS\n\t} else {\n\t   set device_class [expr {([mrw 0x400fe000] >> 16) & 0xff}]\n\t}\n\n\tif {$device_class == 0 || $device_class == 1 ||\n\t\t$device_class == 3 || $device_class == 5 || $device_class == 0xa} {\n\t\tif {![using_hla]} {\n\t\t   # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ\n\t\t   cortex_m reset_config sysresetreq\n\t\t}\n\t} else {\n\t\tif {![using_hla]} {\n\t\t   # Tempest and Firestorm default to using NVIC VECTRESET\n\t\t   # peripherals will need resetting manually, see proc reset_peripherals\n\t\t   cortex_m reset_config vectreset\n\t\t}\n\t\t# reset peripherals, based on code in\n\t\t# http://www.ti.com/lit/er/spmz573a/spmz573a.pdf\n\t\treset_peripherals $device_class\n\t}\n}\n\n# flash configuration ... autodetects sizes, autoprobed\nflash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32c0x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32c0x family\n#\n# stm32c0 devices support SWD transports only.\n#\n\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME stm32c0x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 6kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x1800\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   # SWD IDCODE (single drop, arm)\n   set _CPUTAPID 0x0bc11477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nflash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME\n\n# reasonable default\nadapter speed 2000\n\nadapter srst delay 100\nif {[using_jtag]} {\n\tjtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n\t# if srst is not fitted use SYSRESETREQ to\n\t# perform a soft reset\n\tcortex_m reset_config sysresetreq\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# Enable DBGMCU clock\n\t# RCC_APB1ENR |= DBGMCUEN\n\tmmw 0x4002103C 0x08000000 0\n\n\t# Enable debug during low power modes (uses more power)\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP\n\tmmw 0x40015804 0x00000006 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP\n\tmmw 0x40015808 0x00001800 0\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32f0x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32f0x family\n\n#\n# stm32 devices support SWD transports only.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32f0x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 4kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x1000\n}\n\n# Allow overriding the Flash bank size\nif { [info exists FLASH_SIZE] } {\n\tset _FLASH_SIZE $FLASH_SIZE\n} else {\n\t# autodetect size\n\tset _FLASH_SIZE 0\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n  # See STM Document RM0091\n  # Section 29.5.3\n   set _CPUTAPID 0x0bb11477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME\n\n# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz\nadapter speed 1000\n\nadapter srst delay 100\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\nproc stm32f0x_default_reset_start {} {\n\t# Reset clock is HSI (8 MHz)\n\tadapter speed 1000\n}\n\nproc stm32f0x_default_examine_end {} {\n\t# Enable debug during low power modes (uses more power)\n\tmmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP\n\n\t# Stop watchdog counters during halt\n\tmmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n}\n\nproc stm32f0x_default_reset_init {} {\n\t# Configure PLL to boost clock to HSI x 6 (48 MHz)\n\tmww 0x40021004 0x00100000   ;# RCC_CFGR = PLLMUL[2]\n\tmmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON\n\tmww 0x40022000 0x00000011   ;# FLASH_ACR = PRFTBE | LATENCY[0]\n\tsleep 10                    ;# Wait for PLL to lock\n\tmmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]\n\n\t# Boost JTAG frequency\n\tadapter speed 8000\n}\n\n# Default hooks\n$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }\n$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }\n$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32f1x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32f1x family\n\n#\n# stm32 devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32f1x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 4kB (as found on some STM32F100s)\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x1000\n}\n\n# Allow overriding the Flash bank size\nif { [info exists FLASH_SIZE] } {\n    set _FLASH_SIZE $FLASH_SIZE\n} else {\n    # autodetect size\n    set _FLASH_SIZE 0\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      # See STM Document RM0008 Section 26.6.3\n      set _CPUTAPID 0x3ba00477\n   } {\n      # this is the SW-DP tap id not the jtag tap id\n      set _CPUTAPID 0x1ba01477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n   jtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME\n\n# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz\nadapter speed 1000\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n    # if srst is not fitted use SYSRESETREQ to\n    # perform a soft reset\n    cortex_m reset_config sysresetreq\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |\n\t#              DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\tmmw 0xE0042004 0x00000307 0\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {\n\ttargets $_targetname\n\n\t# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync\n\t# change this value accordingly to configure trace pins\n\t# assignment\n\tmmw 0xE0042004 0x00000020 0\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32f2x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32f2x family\n\n#\n# stm32 devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32f2x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 64kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x10000\n}\n\n# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz\n#\n# Since we may be running of an RC oscilator, we crank down the speed a\n# bit more to be on the safe side. Perhaps superstition, but if are\n# running off a crystal, we can run closer to the limit. Note\n# that there can be a pretty wide band where things are more or less stable.\nadapter speed 1000\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      # See STM Document RM0033\n      # Section 32.6.3 - corresponds to Cortex-M3 r2p0\n      set _CPUTAPID 0x4ba00477\n   } {\n      set _CPUTAPID 0x2ba01477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n\tjtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\tmmw 0xE0042004 0x00000007 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0xE0042008 0x00001800 0\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {\n\ttargets $_targetname\n\n\t# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync\n\t# change this value accordingly to configure trace pins\n\t# assignment\n\tmmw 0xE0042004 0x00000020 0\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32f3x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32f3x family\n\n#\n# stm32 devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32f3x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 16kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\n# Allow overriding the Flash bank size\nif { [info exists FLASH_SIZE] } {\n   set _FLASH_SIZE $FLASH_SIZE\n} else {\n   # autodetect size\n   set _FLASH_SIZE 0\n}\n\n# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz\n#\n# Since we may be running of an RC oscilator, we crank down the speed a\n# bit more to be on the safe side. Perhaps superstition, but if are\n# running off a crystal, we can run closer to the limit. Note\n# that there can be a pretty wide band where things are more or less stable.\nadapter speed 1000\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      # See STM Document RM0316\n      # Section 29.6.3 - corresponds to Cortex-M4 r0p1\n      set _CPUTAPID 0x4ba00477\n   } {\n      set _CPUTAPID 0x2ba01477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n   jtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32f1x 0 $_FLASH_SIZE 0 0 $_TARGETNAME\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\nproc stm32f3x_default_reset_start {} {\n\t# Reset clock is HSI (8 MHz)\n\tadapter speed 1000\n}\n\nproc stm32f3x_default_examine_end {} {\n\t# Enable debug during low power modes (uses more power)\n\tmmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\n\t# Stop watchdog counters during halt\n\tmmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n}\n\nproc stm32f3x_default_reset_init {} {\n\t# Configure PLL to boost clock to HSI x 8 (64 MHz)\n\tmww 0x40021004 0x00380400   ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]\n\tmmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON\n\tmww 0x40022000 0x00000012   ;# FLASH_ACR = PRFTBE | LATENCY[1]\n\tsleep 10                    ;# Wait for PLL to lock\n\tmmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]\n\n\t# Boost JTAG frequency\n\tadapter speed 8000\n}\n\n# Default hooks\n$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }\n$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }\n$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {\n\ttargets $_targetname\n\n\t# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync\n\t# change this value accordingly to configure trace pins\n\t# assignment\n\tmmw 0xe0042004 0x00000020 0\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32f4x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32f4x family\n\n#\n# stm32f4 devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32f4x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 32kB (Available RAM in smallest device STM32F410)\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x8000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      # See STM Document RM0090\n      # Section 38.6.3 - corresponds to Cortex-M4 r0p1\n      set _CPUTAPID 0x4ba00477\n   } {\n      set _CPUTAPID 0x2ba01477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n   jtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME\n\nflash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME\n\nif { [info exists QUADSPI] && $QUADSPI } {\n   set a [llength [flash list]]\n   set _QSPINAME $_CHIPNAME.qspi\n   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000\n}\n\n# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz\n#\n# Since we may be running of an RC oscilator, we crank down the speed a\n# bit more to be on the safe side. Perhaps superstition, but if are\n# running off a crystal, we can run closer to the limit. Note\n# that there can be a pretty wide band where things are more or less stable.\nadapter speed 2000\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# Enable debug during low power modes (uses more power)\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\tmmw 0xE0042004 0x00000007 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0xE0042008 0x00001800 0\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {\n\ttargets $_chipname.cpu\n\n\tif { [$_chipname.tpiu cget -protocol] eq \"sync\" } {\n\t\tswitch [$_chipname.tpiu cget -port-width] {\n\t\t\t1 {\n\t\t\t\t# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0\n\t\t\t\tmmw 0xE0042004 0x00000060 0x000000c0\n\t\t\t\tmmw 0x40021020 0x00000000 0x0000ff00\n\t\t\t\tmmw 0x40021000 0x000000a0 0x000000f0\n\t\t\t\tmmw 0x40021008 0x000000f0 0x00000000\n\t\t\t  }\n\t\t\t2 {\n\t\t\t\t# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0\n\t\t\t\tmmw 0xE0042004 0x000000a0 0x000000c0\n\t\t\t\tmmw 0x40021020 0x00000000 0x000fff00\n\t\t\t\tmmw 0x40021000 0x000002a0 0x000003f0\n\t\t\t\tmmw 0x40021008 0x000003f0 0x00000000\n\t\t\t  }\n\t\t\t4 {\n\t\t\t\t# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0\n\t\t\t\tmmw 0xE0042004 0x000000e0 0x000000c0\n\t\t\t\tmmw 0x40021020 0x00000000 0x0fffff00\n\t\t\t\tmmw 0x40021000 0x00002aa0 0x00003ff0\n\t\t\t\tmmw 0x40021008 0x00003ff0 0x00000000\n\t\t\t  }\n\t\t}\n\t} else {\n\t\t# Set TRACE_IOEN; TRACE_MODE to async\n\t\tmmw 0xE0042004 0x00000020 0x000000c0\n\t}\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME\"\n\n$_TARGETNAME configure -event reset-init {\n\t# Configure PLL to boost clock to HSI x 4 (64 MHz)\n\tmww 0x40023804 0x08012008   ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)\n\tmww 0x40023C00 0x00000102   ;# FLASH_ACR = PRFTBE | 2(Latency)\n\tmmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON\n\tsleep 10                    ;# Wait for PLL to lock\n\tmmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2\n\tmmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL\n\n\t# Boost JTAG frequency\n\tadapter speed 8000\n}\n\n$_TARGETNAME configure -event reset-start {\n\t# Reduce speed since CPU speed will slow down to 16MHz with the reset\n\tadapter speed 2000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32f7x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32f7x family\n\n#\n# stm32f7 devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32f7x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 128kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x20000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      # See STM Document RM0385\n      # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0\n      set _CPUTAPID 0x5ba00477\n   } {\n      set _CPUTAPID 0x5ba02477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n   jtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.otp stm32f2x 0x1ff0f000 0 0 0 $_TARGETNAME\n\n# On the STM32F7, the Flash is mapped at address 0x08000000 via the AXI and\n# also address 0x00200000 via the ITCM. The former mapping is read-write in\n# hardware, while the latter is read-only. By presenting an alias, we\n# accomplish two things:\n# (1) We allow writing at 0x00200000 (because the alias acts identically to the\n#     original bank), which allows code intended to run from that address to\n#     also be linked for loading at that address, simplifying linking.\n# (2) We allow the proper memory map to be delivered to GDB, which will cause\n#     it to use hardware breakpoints at the 0x00200000 mapping (correctly\n#     identifying it as Flash), which it would otherwise not do. Configuring\n#     the Flash via ITCM alias as virtual\nflash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME\n\nif { [info exists QUADSPI] && $QUADSPI } {\n   set a [llength [flash list]]\n   set _QSPINAME $_CHIPNAME.qspi\n   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000\n}\n\n# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz\nadapter speed 2000\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\n# Use hardware reset.\n#\n# This target is compatible with connect_assert_srst, which may be set in a\n# board file.\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n\n   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal\n   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3\n   # makes the data access cacheable. This allows reading and writing data in the\n   # CPU cache from the debugger, which is far more useful than going straight to\n   # RAM when operating on typical variables, and is generally no worse when\n   # operating on special memory locations.\n   $_CHIPNAME.dap apcsw 0x08000000 0x08000000\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\tmmw 0xE0042004 0x00000007 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0xE0042008 0x00001800 0\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {\n\ttargets $_targetname\n\n\t# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync\n\t# change this value accordingly to configure trace pins\n\t# assignment\n\tmmw 0xE0042004 0x00000020 0\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME\"\n\n$_TARGETNAME configure -event reset-init {\n\t# If the HSE was previously enabled and the external clock source\n\t# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be\n\t# properly switched back to HSI. This situation persists even over a system\n\t# reset, including a pin reset via SRST. However, activating the clock\n\t# security system will detect the problem and clear HSERDY to 0, which in\n\t# turn allows the PLL to switch back to HSI properly. Since we just came\n\t# out of reset, HSEON should be 0. If HSERDY is 1, then this situation must\n\t# have happened; in that case, activate the clock security system to clear\n\t# HSERDY.\n\tif {[mrw 0x40023800] & 0x00020000} {\n\t\tmmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON\n\t\tsleep 10                    ;# Wait for CSS to fire, if it wants to\n\t\tmmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON\n\t\tmww 0x4002380C 0x00800000   ;# RCC_CIR = CSSC\n\t\tsleep 1                     ;# Wait for CSSF to clear\n\t}\n\n\t# If the clock security system fired, it will pend an NMI. A pending NMI\n\t# will cause a bad time for any subsequent executing code, such as a\n\t# programming algorithm.\n\tif {[mrw 0xE000ED04] & 0x80000000} {\n\t\t# ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be\n\t\t# cleared by any normal means (such as ICSR or NVIC). It can only be\n\t\t# cleared by entering the NMI handler or by resetting the processor.\n\t\techo \"[target current]: Clock security system generated NMI. Clearing.\"\n\n\t\t# Keep the old DEMCR value.\n\t\tset old [mrw 0xE000EDFC]\n\n\t\t# Enable vector catch on reset.\n\t\tmww 0xE000EDFC 0x01000001\n\n\t\t# Issue local reset via AIRCR.\n\t\tmww 0xE000ED0C 0x05FA0001\n\n\t\t# Restore old DEMCR value.\n\t\tmww 0xE000EDFC $old\n\t}\n\n\t# Configure PLL to boost clock to HSI x 10 (160 MHz)\n\tmww 0x40023804 0x08002808   ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)\n\tmww 0x40023C00 0x00000107   ;# FLASH_ACR = PRFTBE | 7(Latency)\n\tmmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON\n\tsleep 10                    ;# Wait for PLL to lock\n\tmww 0x40023808 0x00009400   ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)\n\tmmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL\n\n\t# Boost SWD frequency\n\t# Do not boost JTAG frequency and slow down JTAG memory access or flash write algo\n\t# suffers from DAP WAITs\n\tif {[using_jtag]} {\n\t\t[[target current] cget -dap] memaccess 16\n\t} {\n\t\tadapter speed 8000\n\t}\n}\n\n$_TARGETNAME configure -event reset-start {\n\t# Reduce speed since CPU speed will slow down to 16MHz with the reset\n\tadapter speed 2000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32g0x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32g0x family\n\n#\n# stm32g0 devices support SWD transports only.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME stm32g0x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x1000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\t# Section 37.5.5 - corresponds to Cortex-M0+\n\tset _CPUTAPID 0x0bc11477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nflash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME\n\n# reasonable default\nadapter speed 2000\n\nadapter srst delay 100\nif {[using_jtag]} {\n\tjtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n\t# if srst is not fitted use SYSRESETREQ to\n\t# perform a soft reset\n\tcortex_m reset_config sysresetreq\n}\n\nproc stm32g0x_default_reset_start {} {\n\t# Reset clock is HSI16 (16 MHz)\n\tadapter speed 2000\n}\n\nproc stm32g0x_default_examine_end {} {\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP\n\tmmw 0x40015804 0x00000006 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0x40015808 0x00001800 0\n}\n\nproc stm32g0x_default_reset_init {} {\n\t# Increase clock to 64 Mhz\n\tmmw 0x40022000 0x00000002 0x00000005\t;# FLASH_ACR: Latency = 2\n\tmww 0x4002100C 0x30000802\t\t\t\t;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2\n\tmmw 0x40021000 0x01000000 0x00000000\t;# RCC_CR |= PLLON\n\tmmw 0x40021008 0x00000002 0x00000005\t;# RCC_CFGR: SW=PLLRCLK\n\n\t# Boost JTAG frequency\n\tadapter speed 4000\n}\n\n# Default hooks\n$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }\n$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }\n$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32g4x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32g4x family\n\n#\n# stm32g4 devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME stm32g4x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# Smallest current target has 32kB ram, use 16kB by default to avoid surprises\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x4000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tif { [using_jtag] } {\n\t\t# See STM Document RM0440\n\t\t# Section 46.6.3 - corresponds to Cortex-M4 r0p1\n\t\tset _CPUTAPID 0x4ba00477\n\t} {\n\t\tset _CPUTAPID 0x2ba01477\n\t}\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n\tjtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nflash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME\n\nif { [info exists QUADSPI] && $QUADSPI } {\n\tset a [llength [flash list]]\n\tset _QSPINAME $_CHIPNAME.qspi\n\tflash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000\n}\n\n# reasonable default\nadapter speed 2000\n\nadapter srst delay 100\nif {[using_jtag]} {\n\tjtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n\t# if srst is not fitted use SYSRESETREQ to\n\t# perform a soft reset\n\tcortex_m reset_config sysresetreq\n}\n\n$_TARGETNAME configure -event reset-init {\n\t# CPU comes out of reset with HSION | HSIRDY.\n\t# Use HSI 16 MHz clock, compliant even with VOS == 2.\n\t# 1 WS compliant with VOS == 2 and 16 MHz.\n\tmmw 0x40022000 0x00000001 0x0000000E\t;# FLASH_ACR: Latency = 1\n\tmmw 0x40021000 0x00000100 0x00000000\t;# RCC_CR |= HSION\n\tmmw 0x40021008 0x00000001 0x00000002\t;# RCC_CFGR: SW=HSI16\n}\n\n$_TARGETNAME configure -event reset-start {\n\t# Reset clock is HSI (16 MHz)\n\tadapter speed 2000\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\tmmw 0xE0042004 0x00000007 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0xE0042008 0x00001800 0\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {\n\ttargets $_targetname\n\n\t# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync\n\t# change this value accordingly to configure trace pins\n\t# assignment\n\tmmw 0xE0042004 0x00000020 0\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32h7x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32h7x family\n\n#\n# stm32h7 devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32h7x\n}\n\nif { [info exists DUAL_BANK] } {\n\tset $_CHIPNAME.DUAL_BANK $DUAL_BANK\n\tunset DUAL_BANK\n} else {\n\tset $_CHIPNAME.DUAL_BANK 0\n}\n\nif { [info exists DUAL_CORE] } {\n\tset $_CHIPNAME.DUAL_CORE $DUAL_CORE\n\tunset DUAL_CORE\n} else {\n\tset $_CHIPNAME.DUAL_CORE 0\n}\n\n# Issue a warning when hla is used, and fallback to single core configuration\nif { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {\n\techo \"Warning : hla does not support multicore debugging\"\n\tset $_CHIPNAME.DUAL_CORE 0\n}\n\nif { [info exists USE_CTI] } {\n\tset $_CHIPNAME.USE_CTI $USE_CTI\n\tunset USE_CTI\n} else {\n\tset $_CHIPNAME.USE_CTI 0\n}\n\n# Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0\nif { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {\n\techo \"Warning : could not use CTI with a single core device, CTI is disabled\"\n\tset $_CHIPNAME.USE_CTI 0\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 64kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x10000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n\t  set _CPUTAPID 0x6ba00477\n   } {\n      set _CPUTAPID 0x6ba02477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n   jtag newtap $_CHIPNAME bs -irlen 5\n}\n\nif {![using_hla]} {\n\t# STM32H7 provides an APB-AP at access port 2, which allows the access to\n\t# the debug and trace features on the system APB System Debug Bus (APB-D).\n\ttarget create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2\n\tswo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000\n\ttpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000\n}\n\ntarget create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0\n\n$_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nflash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0\n\nif {[set $_CHIPNAME.DUAL_BANK]} {\n\tflash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0\n}\n\nif {[set $_CHIPNAME.DUAL_CORE]} {\n\ttarget create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3\n\n\t$_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n\tflash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1\n\n\tif {[set $_CHIPNAME.DUAL_BANK]} {\n\t\tflash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1\n\t}\n}\n\n# Make sure that cpu0 is selected\ntargets $_CHIPNAME.cpu0\n\nif { [info exists QUADSPI] && $QUADSPI } {\n   set a [llength [flash list]]\n   set _QSPINAME $_CHIPNAME.qspi\n   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000\n} else {\n   if { [info exists OCTOSPI1] && $OCTOSPI1 } {\n      set a [llength [flash list]]\n      set _OCTOSPINAME1 $_CHIPNAME.octospi1\n      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000\n   }\n   if { [info exists OCTOSPI2] && $OCTOSPI2 } {\n      set b [llength [flash list]]\n      set _OCTOSPINAME2 $_CHIPNAME.octospi2\n      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000\n   }\n}\n\n# Clock after reset is HSI at 64 MHz, no need of PLL\nadapter speed 1800\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\n# use hardware reset\n#\n# The STM32H7 does not support connect_assert_srst mode because the AXI is\n# unavailable while SRST is asserted, and that is used to access the DBGMCU\n# component at 0x5C001000 in the examine-end event handler.\n#\n# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead\n# of the default AP0, and that works with SRST asserted; however, nonzero AP\n# usage does not work with HLA, so is not done by default. That change could be\n# made in a local configuration file if connect_assert_srst mode is needed for\n# a specific application and a non-HLA adapter is in use.\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n\t$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq\n\n\tif {[set $_CHIPNAME.DUAL_CORE]} {\n\t\t$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq\n\t}\n\n   # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal\n   # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3\n   # makes the data access cacheable. This allows reading and writing data in the\n   # CPU cache from the debugger, which is far more useful than going straight to\n   # RAM when operating on typical variables, and is generally no worse when\n   # operating on special memory locations.\n   $_CHIPNAME.dap apcsw 0x08000000 0x08000000\n}\n\n$_CHIPNAME.cpu0 configure -event examine-end {\n\t# Enable D3 and D1 DBG clocks\n\t# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN\n\tstm32h7x_dbgmcu_mmw 0x004 0x00600000 0\n\n\t# Enable debug during low power modes (uses more power)\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain\n\tstm32h7x_dbgmcu_mmw 0x004 0x00000007 0\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain\n\tstm32h7x_dbgmcu_mmw 0x004 0x00000038 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB3FZ1 |= WWDG1\n\tstm32h7x_dbgmcu_mmw 0x034 0x00000040 0\n\t# DBGMCU_APB1LFZ1 |= WWDG2\n\tstm32h7x_dbgmcu_mmw 0x03C 0x00000800 0\n\t# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2\n\tstm32h7x_dbgmcu_mmw 0x054 0x000C0000 0\n\n\t# Enable clock for tracing\n\t# DBGMCU_CR |= TRACECLKEN\n\tstm32h7x_dbgmcu_mmw 0x004 0x00100000 0\n\n\t# RM0399 (id 0x450) M7+M4 with SWO Funnel\n\t# RM0433 (id 0x450) M7 with SWO Funnel\n\t# RM0455 (id 0x480) M7 without SWO Funnel\n\t# RM0468 (id 0x483) M7 without SWO Funnel\n\t# Enable CM7 and CM4 slave ports in SWO trace Funnel\n\t# Works ok also on devices single core and without SWO funnel\n\t# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF\n\t# SWTF_CTRL |= ENS0 | ENS1\n\tstm32h7x_dbgmcu_mmw 0x3000 0x00000003 0\n}\n\n$_CHIPNAME.cpu0 configure -event reset-init {\n\t# Clock after reset is HSI at 64 MHz, no need of PLL\n\tadapter speed 4000\n}\n\n# get _CHIPNAME from current target\nproc stm32h7x_get_chipname {} {\n\tset t [target current]\n\tset sep [string last \".\" $t]\n\tif {$sep == -1} {\n\t\treturn $t\n\t}\n\treturn [string range $t 0 [expr {$sep - 1}]]\n}\n\nif {[set $_CHIPNAME.DUAL_CORE]} {\n\t$_CHIPNAME.cpu1 configure -event examine-end {\n\t\tset _CHIPNAME [stm32h7x_get_chipname]\n\t\tglobal $_CHIPNAME.USE_CTI\n\n\t\t# Stop watchdog counters during halt\n\t\t# DBGMCU_APB3FZ2 |= WWDG1\n\t\tstm32h7x_dbgmcu_mmw 0x038 0x00000040 0\n\t\t# DBGMCU_APB1LFZ2 |= WWDG2\n\t\tstm32h7x_dbgmcu_mmw 0x040 0x00000800 0\n\t\t# DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2\n\t\tstm32h7x_dbgmcu_mmw 0x058 0x000C0000 0\n\n\t\tif {[set $_CHIPNAME.USE_CTI]} {\n\t\t\tstm32h7x_cti_start\n\t\t}\n\t}\n}\n\n# like mrw, but with target selection\nproc stm32h7x_mrw {used_target reg} {\n\treturn [$used_target read_memory $reg 32 1]\n}\n\n# like mmw, but with target selection\nproc stm32h7x_mmw {used_target reg setbits clearbits} {\n\tset old [stm32h7x_mrw $used_target $reg]\n\tset new [expr {($old & ~$clearbits) | $setbits}]\n\t$used_target mww $reg $new\n}\n\n# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base\n# this procedure will use the mem_ap on AP2 whenever possible\nproc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {\n\t# use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address\n\tif {![using_hla]} {\n\t\tset _CHIPNAME [stm32h7x_get_chipname]\n\t\tset used_target $_CHIPNAME.ap2\n\t\tset reg_addr [expr {0xE00E1000 + $reg_offset}]\n\t} {\n\t\tset used_target [target current]\n\t\tset reg_addr [expr {0x5C001000 + $reg_offset}]\n\t}\n\n\tstm32h7x_mmw $used_target $reg_addr $setbits $clearbits\n}\n\nif {[set $_CHIPNAME.USE_CTI]} {\n\t# create CTI instances for both cores\n\tcti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000\n\tcti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000\n\n\t$_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }\n\t$_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }\n\n\t$_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }\n\t$_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }\n\n\tproc stm32h7x_cti_start {} {\n\t\tset _CHIPNAME [stm32h7x_get_chipname]\n\n\t\t# Configure Cores' CTIs to halt each other\n\t\t# TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0\n\t\t$_CHIPNAME.cti0 write INEN0 0x1\n\t\t$_CHIPNAME.cti0 write OUTEN0 0x1\n\t\t$_CHIPNAME.cti1 write INEN0 0x1\n\t\t$_CHIPNAME.cti1 write OUTEN0 0x1\n\n\t\t# enable CTIs\n\t\t$_CHIPNAME.cti0 enable on\n\t\t$_CHIPNAME.cti1 enable on\n\t}\n\n\tproc stm32h7x_cti_stop {} {\n\t\tset _CHIPNAME [stm32h7x_get_chipname]\n\n\t\t$_CHIPNAME.cti0 enable off\n\t\t$_CHIPNAME.cti1 enable off\n\t}\n\n\tproc stm32h7x_cti_prepare_restart_all {} {\n\t\tstm32h7x_cti_prepare_restart cti0\n\t\tstm32h7x_cti_prepare_restart cti1\n\t}\n\n\tproc stm32h7x_cti_prepare_restart {cti} {\n\t\tset _CHIPNAME [stm32h7x_get_chipname]\n\n\t\t# Acknowlodge EDBGRQ at TRIGOUT0\n\t\t$_CHIPNAME.$cti write INACK 0x01\n\t\t$_CHIPNAME.$cti write INACK 0x00\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32h7x_dual_bank.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32h7x family (dual flash bank)\n\n# STM32H7xxxI 2Mo have a dual bank flash.\nset DUAL_BANK 1\n\nsource [find target/stm32h7x.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32l0.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# M0+ devices only have SW-DP, but swj-dp code works, just don't\n# set any jtag related features\n#\n\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32l0\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 2kB (max ram on smallest part)\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x800\n}\n\n# JTAG speed should be <= F_CPU/6.\n# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz\nadapter speed 300\n\nadapter srst delay 100\n\nif { [info exists CPUTAPID] } {\n    set _CPUTAPID $CPUTAPID\n} else {\n    # Arm, m0+, non-multidrop.\n    # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html\n    set _CPUTAPID 0x0bc11477\n}\n\nswj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\nproc stm32l0_enable_HSI16 {} {\n\t# Enable HSI16 as clock source\n\techo \"STM32L0: Enabling HSI16\"\n\n\t# Set HSI16ON in RCC_CR (leave MSI enabled)\n    mmw 0x40021000 0x00000101 0\n\n\t# Set HSI16 as SYSCLK (RCC_CFGR)\n\tmmw 0x4002100c 0x00000001 0\n\n\t# Wait until System clock switches to HSI16\n\twhile { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }\n\n\t# Increase speed\n\tadapter speed 2500\n}\n\n$_TARGETNAME configure -event reset-init {\n\tstm32l0_enable_HSI16\n}\n\n$_TARGETNAME configure -event reset-start {\n\tadapter speed 300\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\tmmw 0x40015804 0x00000007 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0x40015808 0x00001800 0\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32l0_dual_bank.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/stm32l0.cfg]\n\n# Add the second flash bank.\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32l1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# stm32l1 devices support both JTAG and SWD transports.\n#\n\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32l1\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 10kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x2800\n}\n\n# JTAG speed should be <= F_CPU/6.\n# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz\nadapter speed 300\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      # See STM Document RM0038\n      # Section 30.6.3 - corresponds to Cortex-M3 r2p0\n      set _CPUTAPID 0x4ba00477\n   } else {\n      # SWD IDCODE (single drop, arm)\n      set _CPUTAPID 0x2ba01477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n   jtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\nproc stm32l_enable_HSI {} {\n\t# Enable HSI as clock source\n\techo \"STM32L: Enabling HSI\"\n\n\t# Set HSION in RCC_CR\n\tmmw 0x40023800 0x00000101 0\n\n\t# Set HSI as SYSCLK\n\tmmw 0x40023808 0x00000001 0\n\n\t# Increase JTAG speed\n\tadapter speed 2000\n}\n\n$_TARGETNAME configure -event reset-init {\n\tstm32l_enable_HSI\n}\n\n$_TARGETNAME configure -event reset-start {\n\tadapter speed 300\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\tmmw 0xE0042004 0x00000007 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0xE0042008 0x00001800 0\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {\n\ttargets $_targetname\n\n\t# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync\n\t# change this value accordingly to configure trace pins\n\t# assignment\n\tmmw 0xE0042004 0x00000020 0\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32l1x_dual_bank.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/stm32l1.cfg]\n\n# The stm32l1x 384kb have a dual bank flash.\n# Let's add a definition for the second bank here.\n\n# Add the second flash bank.\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32l4x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32l4x family\n\n#\n# stm32l4 devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32l4x\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 40kB (Available RAM in smallest device STM32L412)\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0xa000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      # See STM Document RM0351\n      # Section 44.6.3 - corresponds to Cortex-M4 r0p1\n      set _CPUTAPID 0x4ba00477\n   } {\n      set _CPUTAPID 0x2ba01477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n   jtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME stm32l4x 0x08000000 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME\n\nif { [info exists QUADSPI] && $QUADSPI } {\n   set a [llength [flash list]]\n   set _QSPINAME $_CHIPNAME.qspi\n   flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000\n} else {\n   if { [info exists OCTOSPI1] && $OCTOSPI1 } {\n      set a [llength [flash list]]\n      set _OCTOSPINAME1 $_CHIPNAME.octospi1\n      flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000\n   }\n   if { [info exists OCTOSPI2] && $OCTOSPI2 } {\n      set b [llength [flash list]]\n      set _OCTOSPINAME2 $_CHIPNAME.octospi2\n      flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400\n   }\n}\n\n# Common knowledges tells JTAG speed should be <= F_CPU/6.\n# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on\n# the safe side.\n#\n# Note that there is a pretty wide band where things are\n# more or less stable, see http://openocd.zylin.com/#/c/3366/\nadapter speed 500\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# Enable debug during low power modes (uses more power)\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\tmmw 0xE0042004 0x00000007 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0xE0042008 0x00001800 0\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} {\n\ttargets $_chipname.cpu\n\n\tif { [$_chipname.tpiu cget -protocol] eq \"sync\" } {\n\t\tswitch [$_chipname.tpiu cget -port-width] {\n\t\t\t1 {\n\t\t\t\t# Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0\n\t\t\t\tmmw 0xE0042004 0x00000060 0x000000c0\n\t\t\t\tmmw 0x48001020 0x00000000 0x0000ff00\n\t\t\t\tmmw 0x48001000 0x000000a0 0x000000f0\n\t\t\t\tmmw 0x48001008 0x000000f0 0x00000000\n\t\t\t  }\n\t\t\t2 {\n\t\t\t\t# Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0\n\t\t\t\tmmw 0xE0042004 0x000000a0 0x000000c0\n\t\t\t\tmmw 0x48001020 0x00000000 0x000fff00\n\t\t\t\tmmw 0x48001000 0x000002a0 0x000003f0\n\t\t\t\tmmw 0x48001008 0x000003f0 0x00000000\n\t\t\t  }\n\t\t\t4 {\n\t\t\t\t# Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0\n\t\t\t\tmmw 0xE0042004 0x000000e0 0x000000c0\n\t\t\t\tmmw 0x48001020 0x00000000 0x0fffff00\n\t\t\t\tmmw 0x48001000 0x00002aa0 0x00003ff0\n\t\t\t\tmmw 0x48001008 0x00003ff0 0x00000000\n\t\t\t  }\n\t\t}\n\t} else {\n\t\t# Set TRACE_IOEN; TRACE_MODE to async\n\t\tmmw 0xE0042004 0x00000020 0x000000c0\n\t}\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME\"\n\n$_TARGETNAME configure -event reset-init {\n\t# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).\n\t# Use MSI 24 MHz clock, compliant even with VOS == 2.\n\t# 3 WS compliant with VOS == 2 and 24 MHz.\n\tmww 0x40022000 0x00000103   ;# FLASH_ACR = PRFTBE | 3(Latency)\n\tmww 0x40021000 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9\n\n\t# Boost JTAG frequency\n\tadapter speed 4000\n}\n\n$_TARGETNAME configure -event reset-start {\n\t# Reset clock is MSI (4 MHz)\n\tadapter speed 500\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32l5x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32l5x family\n# stm32l5x devices support both JTAG and SWD transports.\n\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME stm32l5x\n}\n\nsource [find target/stm32x5x_common.cfg]\n\nproc stm32l5x_clock_config {} {\n\tset offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]\n\t# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL\n\t# RCC_APB1ENR1 = PWREN\n\tmww [expr {0x40021058 + $offset}] 0x10000000\n\t# delay for register clock enable (read back reg)\n\tmrw [expr {0x40021058 + $offset}]\n\t# PWR_CR1 : VOS Range 0\n\tmww [expr {0x40007000 + $offset}] 0\n\t# while (PWR_SR2 & VOSF)\n\twhile {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}\n\t# FLASH_ACR : 5 WS for 110 MHz HCLK\n\tmww 0x40022000 0x00000005\n\t# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz\n\t# fVCO = 4 x 55 /1 = 220\n\t# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz\n\tmww [expr {0x4002100C + $offset}] 0x01003711\n\t# RCC_CR |= PLLON\n\tmmw [expr {0x40021000 + $offset}] 0x01000000 0\n\t# while !(RCC_CR & PLLRDY)\n\twhile {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}\n\t# RCC_CFGR |= SW_PLL\n\tmmw [expr {0x40021008 + $offset}] 0x00000003 0\n\t# while ((RCC_CFGR & SWS) != PLL)\n\twhile {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}\n}\n\n$_TARGETNAME configure -event reset-init {\n\tstm32l5x_clock_config\n\t# Boost JTAG frequency\n\tadapter speed 4000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32mp13x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STMicroelectronics STM32MP13x (Single Cortex-A7)\n# http://www.st.com/stm32mp1\n\n# HLA does not support custom CSW nor AP other than 0\nif { [using_hla] } {\n\techo \"ERROR: HLA transport cannot work with this target.\"\n\techo \"ERROR: To use STLink switch to DAP mode, as in \\\"board/stm32mp13x_dk.cfg\\\".\"\n\tshutdown\n}\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME stm32mp13x\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tif { [using_jtag] } {\n\t\tset _CPUTAPID 0x6ba00477\n\t} else {\n\t\tset _CPUTAPID 0x6ba02477\n\t}\n}\n\n# Chip Level TAP Controller, only in jtag mode\nif { [info exists CLCTAPID] } {\n\tset _CLCTAPID $CLCTAPID\n} else {\n\tset _CLCTAPID 0x06501041\n}\n\nswj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4\nif { [using_jtag] } {\n\tjtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5\n}\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack\n\n# NOTE: keep ap-num and dbgbase to speed-up examine after reset\n# NOTE: do not change the order of target create\ntarget create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1\ntarget create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0\ntarget create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000\n\n$_CHIPNAME.cpu cortex_a maskisr on\n$_CHIPNAME.cpu cortex_a dacrfixup on\n\n# interface does not work while srst is asserted\n# this is target specific, valid for every board\n# srst resets the debug unit, behavior equivalent to \"srst_pulls_trst\"\nreset_config srst_gates_jtag srst_pulls_trst\n\nadapter speed 5000\nadapter srst pulse_width 200\n# bootrom has an internal timeout of 1 second for detecting the boot flash.\n# wait at least 1 second to guarantee we are out of bootrom\nadapter srst delay 1100\n\nadd_help_text axi_secure \"Set secure mode for following AXI accesses\"\nproc axi_secure {} {\n\t$::_CHIPNAME.dap apsel 0\n\t$::_CHIPNAME.dap apcsw 0x10006000\n}\n\nadd_help_text axi_nsecure \"Set non-secure mode for following AXI accesses\"\nproc axi_nsecure {} {\n\t$::_CHIPNAME.dap apsel 0\n\t$::_CHIPNAME.dap apcsw 0x30006000\n}\n\naxi_secure\n\nproc dbgmcu_enable_debug {} {\n\t# keep clock enabled in low-power\n\t## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}\n\t# freeze watchdog 1 and 2 on core halted\n\tcatch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}\n\tcatch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}\n}\n\nproc toggle_cpu_dbg_claim0 {} {\n\t# toggle CPU0 DBG_CLAIM[0]\n\t$::_CHIPNAME.ap1 mww 0xe00d0fa0 1\n\t$::_CHIPNAME.ap1 mww 0xe00d0fa4 1\n}\n\n# FIXME: most of handlers below will be removed once reset framework get merged\n$_CHIPNAME.ap1 configure -event reset-deassert-pre {\n\tadapter deassert srst deassert trst\n\tcatch {dap init}\n\tcatch {$::_CHIPNAME.dap apid 1}\n}\n$_CHIPNAME.cpu configure -event reset-deassert-pre  {$::_CHIPNAME.cpu arp_examine}\n$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}\n$_CHIPNAME.ap1 configure -event examine-start       {dap init}\n$_CHIPNAME.ap1 configure -event examine-end         {dbgmcu_enable_debug}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32mp15x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)\n# http://www.st.com/stm32mp1\n\n# HLA does not support multi-cores nor custom CSW nor AP other than 0\nif { [using_hla] } {\n\techo \"ERROR: HLA transport cannot work with this target.\"\n\techo \"ERROR: To use STLink switch to DAP mode, as in \\\"board/stm32mp15x_dk2.cfg\\\".\"\n\tshutdown\n}\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME stm32mp15x\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tif { [using_jtag] } {\n\t\tset _CPUTAPID 0x6ba00477\n\t} else {\n\t\tset _CPUTAPID 0x6ba02477\n\t}\n}\n\n# Chip Level TAP Controller, only in jtag mode\nif { [info exists CLCTAPID] } {\n\tset _CLCTAPID $CLCTAPID\n} else {\n\tset _CLCTAPID 0x06500041\n}\n\nswj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4\nif { [using_jtag] } {\n\tjtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5\n}\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack\n\n# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1\n# so defer-examine it until the reset framework get merged\n# NOTE: keep ap-num and dbgbase to speed-up examine after reset\n# NOTE: do not change the order of target create\ntarget create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1\ntarget create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2\ntarget create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0\ntarget create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000\ntarget create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000\ntarget create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine\n\ntargets $_CHIPNAME.cpu0\n\ntarget smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1\n$_CHIPNAME.cpu0 cortex_a maskisr on\n$_CHIPNAME.cpu1 cortex_a maskisr on\n$_CHIPNAME.cpu0 cortex_a dacrfixup on\n$_CHIPNAME.cpu1 cortex_a dacrfixup on\n\ncti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000\ncti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000\ncti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000\ncti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000\n\nswo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000\n\n# interface does not work while srst is asserted\n# this is target specific, valid for every board\n# Errata \"2.3.5 Incorrect reset of glitch-free kernel clock switch\" requires\n# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the\n# debug unit, behavior equivalent to \"srst_pulls_trst\"\nreset_config srst_gates_jtag srst_pulls_trst\n\nadapter speed 5000\nadapter srst pulse_width 200\n# bootrom has an internal timeout of 1 second for detecting the boot flash.\n# wait at least 1 second to guarantee we are out of bootrom\nadapter srst delay 1100\n\nadd_help_text axi_secure \"Set secure mode for following AXI accesses\"\nproc axi_secure {} {\n\t$::_CHIPNAME.dap apsel 0\n\t$::_CHIPNAME.dap apcsw 0x10006000\n}\n\nadd_help_text axi_nsecure \"Set non-secure mode for following AXI accesses\"\nproc axi_nsecure {} {\n\t$::_CHIPNAME.dap apsel 0\n\t$::_CHIPNAME.dap apcsw 0x30006000\n}\n\naxi_secure\n\nproc dbgmcu_enable_debug {} {\n\t# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible\n\tcatch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}\n\t# freeze watchdog 1 and 2 on cores halted\n\tcatch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}\n\tcatch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}\n}\n\nproc toggle_cpu0_dbg_claim0 {} {\n\t# toggle CPU0 DBG_CLAIM[0]\n\t$::_CHIPNAME.ap1 mww 0xe00d0fa0 1\n\t$::_CHIPNAME.ap1 mww 0xe00d0fa4 1\n}\n\nproc detect_cpu1 {} {\n\tset cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]\n\tset dual_core [expr {$cpu1_prsr & 1}]\n\tif {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}\n}\n\nproc rcc_enable_traceclk {} {\n\t$::_CHIPNAME.ap2 mww 0x5000080c 0x301\n}\n\n# FIXME: most of handler below will be removed once reset framework get merged\n$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}\n$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}\n$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}\n$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}\n$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}\n$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == \"halted\"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}\n$_CHIPNAME.ap1  configure -event examine-start       {dap init}\n$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}\n$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}\n$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32u5x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32u5x family\n# stm32u5x devices support both JTAG and SWD transports.\n\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME stm32u5x\n}\n\nsource [find target/stm32x5x_common.cfg]\n\nproc stm32u5x_clock_config {} {\n\tset offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]\n\t# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL\n\n\t# Enable voltage range 1 for frequency above 100 Mhz\n\t# RCC_AHB3ENR = PWREN\n\tmww [expr {0x46020C94 + $offset}] 0x00000004\n\t# delay for register clock enable (read back reg)\n\tmrw [expr {0x46020C94 + $offset}]\n\t# PWR_VOSR : VOS Range 1\n\tmmw [expr {0x4602080C + $offset}] 0x00030000 0\n\t# while !(PWR_VOSR & VOSRDY)\n\twhile {!([mrw [expr {0x4602080C + $offset}]] & 0x00008000)} {}\n\t# FLASH_ACR : 4 WS for 160 MHz HCLK\n\tmww [expr {0x40022000 + $offset}] 0x00000004\n\t# RCC_PLL1CFGR => PLL1MBOOST=0, PLL1M=0=/1, PLL1FRACEN=0, PLL1SRC=MSI 4MHz\n\t#                 PLL1REN=1, PLL1RGE => VCOInputRange=PLLInputRange_4_8\n\tmww [expr {0x46020C28 + $offset}] 0x00040009\n\t# Enable EPOD Booster\n\tmmw [expr {0x4602080C + $offset}] 0x00040000 0\n\t# while !(PWR_VOSR & BOOSTRDY)\n\twhile {!([mrw [expr {0x4602080C + $offset}]] & 0x00004000)} {}\n\t# RCC_PLL1DIVR => PLL1P=PLL1Q=PLL1R=000001=/2, PLL1N=0x4F=80\n\t# fVCO = 4 x 80 /1 = 320\n\t# SYSCLOCK = fVCO/PLL1R = 320/2 = 160 MHz\n\tmww [expr {0x46020C34 + $offset}] 0x0101024F\n\t# RCC_CR |= PLL1ON\n\tmmw [expr {0x46020C00 + $offset}] 0x01000000 0\n\t# while !(RCC_CR & PLL1RDY)\n\twhile {!([mrw [expr {0x46020C00 + $offset}]] & 0x02000000)} {}\n\t# RCC_CFGR1 |= SW_PLL\n\tmmw [expr {0x46020C1C + $offset}] 0x00000003 0\n\t# while ((RCC_CFGR1 & SWS) != PLL)\n\twhile {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}\n}\n\n$_TARGETNAME configure -event reset-init {\n\tstm32u5x_clock_config\n\t# Boost JTAG frequency\n\tadapter speed 4000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32w108xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Target configuration for the ST STM32W108xx chips\n#\n# Processor: ARM Cortex-M3\n# Date:      2013-06-09\n# Author:    Giuseppe Barba <giuseppe.barba@gmail.com>\n\n#\n# stm32 devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] == 0 } {\n   set _CHIPNAME stm32w108\n} else {\n   set _CHIPNAME $CHIPNAME\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 8kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x2000\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      set _CPUTAPID 0x3ba00477\n   } {\n      set _CPUTAPID 0x1ba01477\n   }\n}\n\nset _ENDIAN little\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n if { [info exists BSTAPID] } {\n   set _BSTAPID $BSTAPID\n   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID\n } else {\n   set _BSTAPID_1 0x169a862b\n   set _BSTAPID_2 0x269a862b\n   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \\\n\t\t-expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2\n }\n}\n#\n# Set Target\n#\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n\n# Use the flash driver from the EM357\nset _FLASHNAME $_CHIPNAME.flash\n\n# 64k (0x10000) of flash\nflash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32wbx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32wbx family\n\n#\n# stm32wb devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm32wbx\n}\n\nset _ENDIAN little\n\n# Work-area is a space in RAM used for flash programming\n# By default use 64kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x10000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   if { [using_jtag] } {\n      set _CPUTAPID 0x6ba00477\n   } else {\n      # SWD IDCODE (single drop, arm)\n      set _CPUTAPID 0x6ba02477\n   }\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n   jtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nflash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME\n\n# Common knowledges tells JTAG speed should be <= F_CPU/6.\n# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on\n# the safe side.\n#\n# Note that there is a pretty wide band where things are\n# more or less stable, see http://openocd.zylin.com/#/c/3366/\nadapter speed 500\n\nadapter srst delay 100\nif {[using_jtag]} {\n jtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n\nif {![using_hla]} {\n   # if srst is not fitted use SYSRESETREQ to\n   # perform a soft reset\n   cortex_m reset_config sysresetreq\n}\n\n$_TARGETNAME configure -event reset-init {\n    # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.\n    # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.\n    # 2 WS compliant with VOS=Range1 and 24 MHz.\n    mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTBE | 2(Latency)\n    mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz\n    # Boost JTAG frequency\n    adapter speed 4000\n}\n\n$_TARGETNAME configure -event reset-start {\n    # Reset clock is MSI (4 MHz)\n    adapter speed 500\n}\n\n$_TARGETNAME configure -event examine-end {\n    # Enable debug during low power modes (uses more power)\n    # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n    mmw 0xE0042004 0x00000007 0\n\n    # Stop watchdog counters during halt\n    # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP\n    mmw 0xE004203C 0x00001800 0\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {\n    targets $_targetname\n\n    # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync\n    # change this value accordingly to configure trace pins\n    # assignment\n    mmw 0xE0042004 0x00000020 0\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32wlx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32wlx family\n\n#\n# stm32wl devices support both JTAG and SWD transports.\n#\nsource [find target/swj-dp.tcl]\nsource [find mem_helper.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME stm32wlx\n}\n\nif { [info exists DUAL_CORE] } {\n\tset $_CHIPNAME.DUAL_CORE $DUAL_CORE\n\tunset DUAL_CORE\n} else {\n\tset $_CHIPNAME.DUAL_CORE 0\n}\n\nif { [info exists WKUP_CM0P] } {\n\tset $_CHIPNAME.WKUP_CM0P $WKUP_CM0P\n\tunset WKUP_CM0P\n} else {\n\tset $_CHIPNAME.WKUP_CM0P 0\n}\n\n# Issue a warning when hla is used, and fallback to single core configuration\nif { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {\n\techo \"Warning : hla does not support multicore debugging\"\n\tset $_CHIPNAME.DUAL_CORE 0\n\tset $_CHIPNAME.WKUP_CM0P 0\n}\n\n# setup the Work-area start address and size\n# Work-area is a space in RAM used for flash programming\n\n# Memory map for known devices:\n# STM32WL   x5JC   x5JB   x5J8\n#   FLASH   256    128    64\n#   SRAM1   32     16     0\n#   SRAM2   32     32     20\n\n# By default use 8kB\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x2000\n}\n\n# Use SRAM2 as work area (some devices do not have SRAM1):\nset WORKAREASTART_CM4   0x20008000\nset WORKAREASTART_CM0P  [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}]\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tif { [using_jtag] } {\n\t\tset _CPUTAPID 0x6ba00477\n\t} else {\n\t\t# SWD IDCODE (single drop, arm)\n\t\tset _CPUTAPID 0x6ba02477\n\t}\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n\tjtag newtap $_CHIPNAME bs -irlen 5\n}\n\ntarget create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap\n\n$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nflash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0\nflash bank $_CHIPNAME.otp.cpu0   stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0\n\nif {![using_hla]} {\n\t# if srst is not fitted use SYSRESETREQ to\n\t# perform a soft reset\n\t$_CHIPNAME.cpu0 cortex_m reset_config sysresetreq\n}\n\n$_CHIPNAME.cpu0 configure -event reset-init {\n\t# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.\n\t# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.\n\t# 2 WS compliant with VOS=Range1 and 24 MHz.\n\tmmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTEN | 2(Latency)\n\tmmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz\n\t# Boost JTAG frequency\n\tadapter speed 4000\n}\n\n$_CHIPNAME.cpu0 configure -event reset-start {\n\t# Reset clock is MSI (4 MHz)\n\tadapter speed 500\n}\n\n$_CHIPNAME.cpu0 configure -event examine-end {\n\t# Enable debug during low power modes (uses more power)\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP\n\tmmw 0xE0042004 0x00000007 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0xE004203C 0x00001800 0\n\n\tset _CHIPNAME [stm32wlx_get_chipname]\n\tglobal $_CHIPNAME.WKUP_CM0P\n\n\tif {[set $_CHIPNAME.WKUP_CM0P]} {\n\t\tstm32wlx_wkup_cm0p\n\t}\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nif {[set $_CHIPNAME.DUAL_CORE]} {\n\ttarget create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1\n\n\t$_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n\tflash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1\n\tflash bank $_CHIPNAME.otp.cpu1   stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1\n\n\tif {![using_hla]} {\n\t\t# if srst is not fitted use SYSRESETREQ to\n\t\t# perform a soft reset\n\t\t$_CHIPNAME.cpu1 cortex_m reset_config sysresetreq\n\t}\n\n\tproc stm32wlx_wkup_cm0p {} {\n\t\tset _CHIPNAME [stm32wlx_get_chipname]\n\n\t\t# enable CPU2 boot after reset and after wakeup from Stop or Standby mode\n\t\t# PWR_CR4 |= C2BOOT\n\t\tstm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0\n\t}\n}\n\n# get _CHIPNAME from current target\nproc stm32wlx_get_chipname {} {\n\tset t [target current]\n\tset sep [string last \".\" $t]\n\tif {$sep == -1} {\n\t\treturn $t\n\t}\n\treturn [string range $t 0 [expr {$sep - 1}]]\n}\n\n# like mrw, but with target selection\nproc stm32wlx_mrw {used_target reg} {\n\treturn [$used_target read_memory $reg 32 1]\n}\n\n# like mmw, but with target selection\nproc stm32wlx_mmw {used_target reg setbits clearbits} {\n\tset old [stm32wlx_mrw $used_target $reg]\n\tset new [expr {($old & ~$clearbits) | $setbits}]\n\t$used_target mww $reg $new\n}\n\n# Make sure that cpu0 is selected\ntargets $_CHIPNAME.cpu0\n\n# Common knowledges tells JTAG speed should be <= F_CPU/6.\n# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on\n# the safe side.\n#\n# Note that there is a pretty wide band where things are\n# more or less stable, see http://openocd.zylin.com/#/c/3366/\nadapter speed 500\n\nadapter srst delay 100\nif {[using_jtag]} {\n\tjtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32x5x_common.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# common script for stm32l5x and stm32u5x families\n\n# Work-area is a space in RAM used for flash programming\n# By default use 64kB\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x10000\n}\n\n#jtag scan chain\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tif { [using_jtag] } {\n\t\t# STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers\n\t\t# STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers\n\t\t# Corresponds to Cortex®-M33 JTAG debug port ID code\n\t\tset _CPUTAPID 0x0ba04477\n\t} {\n\t\t# SWD IDCODE (single drop, arm)\n\t\tset _CPUTAPID 0x0be12477\n\t}\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nif {[using_jtag]} {\n\tjtag newtap $_CHIPNAME bs -irlen 5\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap\n\n# use non-secure RAM by default\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\n# create sec/ns flash and otp memories (sizes will be probed)\nflash bank $_CHIPNAME.flash_ns      stm32l4x 0x08000000 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME\nflash bank $_CHIPNAME.otp           stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME\n\n# Common knowledge tells JTAG speed should be <= F_CPU/6.\n# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on\n# the safe side.\n#\n# Note that there is a pretty wide band where things are\n# more or less stable, see http://review.openocd.org/3366\nadapter speed 500\n\nadapter srst delay 100\nif {[using_jtag]} {\n\tjtag_ntrst_delay 100\n}\n\nreset_config srst_nogate\n\nif {[using_hla]} {\n\techo \"Warn : The selected adapter does not support debugging this device in secure mode\"\n} else {\n\t# if srst is not fitted use SYSRESETREQ to\n\t# perform a soft reset\n\tcortex_m reset_config sysresetreq\n}\n\nproc stm32x5x_is_secure {} {\n\t# read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16)\n\tset DSCSR [mrw 0xE000EE08]\n\treturn [expr {($DSCSR & (1 << 16)) != 0}]\n}\n\nproc stm32x5x_ahb_ap_non_secure_access {} {\n\t# in HLA mode, non-secure debugging is possible without changing the AP CSW\n\tif {![using_hla]} {\n\t\t# SPROT=1=Non Secure access, Priv=1\n\t\t[[target current] cget -dap] apcsw 0x4B000000 0x4F000000\n\t}\n}\n\nproc stm32x5x_ahb_ap_secure_access {} {\n\tif {![using_hla]} {\n\t\t# SPROT=0=Secure access, Priv=1\n\t\t[[target current] cget -dap] apcsw 0x0B000000 0x4F000000\n\t}\n}\n\n$_TARGETNAME configure -event reset-start {\n\t# Reset clock is MSI (4 MHz)\n\tadapter speed 480\n}\n\n$_TARGETNAME configure -event examine-end {\n\t# DBGMCU_CR |= DBG_STANDBY | DBG_STOP\n\tmmw 0xE0044004 0x00000006 0\n\n\t# Stop watchdog counters during halt\n\t# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP\n\tmmw 0xE0044008 0x00001800 0\n}\n\n$_TARGETNAME configure -event halted {\n\tset secure [stm32x5x_is_secure]\n\n\tif {$secure} {\n\t\tset secure_str \"Secure\"\n\t\tstm32x5x_ahb_ap_secure_access\n\t} else {\n\t\tset secure_str \"Non-Secure\"\n\t\tstm32x5x_ahb_ap_non_secure_access\n\t}\n\n\t# print the secure state only when it changes\n\tset _TARGETNAME [target current]\n\tglobal $_TARGETNAME.secure\n\n\tif {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {\n\t\techo \"CPU in $secure_str state\"\n\t\t# update saved security state\n\t\tset $_TARGETNAME.secure $secure\n\t}\n}\n\n$_TARGETNAME configure -event gdb-flash-erase-start {\n\tset use_secure_workarea 0\n\t# check if FLASH_OPTR.TZEN is enabled\n\tset FLASH_OPTR [mrw 0x40022040]\n\tif {[expr {$FLASH_OPTR & 0x80000000}] == 0} {\n\t\techo \"TZEN option bit disabled\"\n\t\tstm32x5x_ahb_ap_non_secure_access\n\t} else {\n\t\tstm32x5x_ahb_ap_secure_access\n\t\techo \"TZEN option bit enabled\"\n\n\t\t# check if FLASH_OPTR.RDP is not Level 0.5\n\t\tif {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {\n\t\t\tset use_secure_workarea 1\n\t\t}\n\t}\n\n\tset _TARGETNAME [target current]\n\tset workarea_addr [$_TARGETNAME cget -work-area-phys]\n\techo \"workarea_addr $workarea_addr\"\n\n\tif {$use_secure_workarea} {\n\t\tset workarea_addr [expr {$workarea_addr | 0x10000000}]\n\t} else {\n\t\tset workarea_addr [expr {$workarea_addr & ~0x10000000}]\n\t}\n\n\t$_TARGETNAME configure -work-area-phys $workarea_addr\n}\n\ntpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000\n\nlappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu\nproc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {\n\ttargets $_targetname\n\n\t# Set TRACE_EN and TRACE_IOEN in DBGMCU_CR\n\t# Leave TRACE_MODE untouched (defaults to async).\n\t# When using sync change this value accordingly to configure trace pins\n\t# assignment\n\tmmw 0xE0044004 0x00000030 0\n}\n\n$_CHIPNAME.tpiu configure -event pre-enable \"_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm32xl.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm32xl family (dual flash bank)\nsource [find target/stm32f1x.cfg]\n\n# flash size will be probed\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8l.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm8l family\n\n#\n# stm8 devices support SWIM transports only.\n#\n\ntransport select swim\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm8l\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 1kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x400\n}\n\nif { [info exists FLASHSTART] } {\n   set _FLASHSTART $FLASHSTART\n} else {\n   set _FLASHSTART 0x8000\n}\n\nif { [info exists FLASHEND] } {\n   set _FLASHEND $FLASHEND\n} else {\n   set _FLASHEND 0xffff\n}\n\nif { [info exists EEPROMSTART] } {\n   set _EEPROMSTART $EEPROMSTART\n} else {\n   set _EEPROMSTART 0x4000\n}\n\nif { [info exists EEPROMEND] } {\n   set _EEPROMEND $EEPROMEND\n} else {\n   set _EEPROMEND 0x43ff\n}\n\nif { [info exists OPTIONSTART] } {\n   set _OPTIONSTART $OPTIONSTART\n} else {\n   set _OPTIONSTART 0x4800\n}\n\nif { [info exists OPTIONEND] } {\n   set _OPTIONEND $OPTIONEND\n} else {\n   set _OPTIONEND 0x487f\n}\n\nif { [info exists BLOCKSIZE] } {\n   set _BLOCKSIZE $BLOCKSIZE\n} else {\n   set _BLOCKSIZE 0x80\n}\n\nswim newtap $_CHIPNAME cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu\n\n$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1\n$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND\n$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE\n\n# Uncomment this line to enable interrupts while instruction step\n#$_TARGETNAME configure -enable_step_irq\n\n# Set stm8l type\n$_TARGETNAME configure -enable_stm8l\n\n# Set high speed\nadapter speed 800\n# Set low speed\n#adapter speed 363\n\nreset_config srst_only\n\n#uncomment this line to connect under reset\n#reset_config srst_nogate connect_assert_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8l151x2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config script for STM8L151x2\n# Supported Devices:\n# STM8L151C2\n# STM8L151F2\n# STM8L151G2\n# STM8L151K2\n\n# 1kB RAM\n# Start 0x0000\n# End   0x03ff\nset WORKAREASIZE 1024\n\n# 4kB Flash\nset FLASHSTART  0x8000\nset FLASHEND    0x8fff\n\n# 256B EEPROM\nset EEPROMSTART 0x1000\nset EEPROMEND   0x10ff\n\nset OPTIONSTART 0x4800\nset OPTIONEND   0x487f\n\nproc stm8_reset_rop {} {\n   mwb 0x4800 0xaa\n   mwb 0x4800 0xaa\n   reset halt\n}\n\nsource [find target/stm8l.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8l151x3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config script for STM8L151x3\n# Supported Devices:\n# STM8L151C3\n# STM8L151F3\n# STM8L151G3\n# STM8L151K3\n\n# 1kB RAM\n# Start 0x0000\n# End   0x03ff\nset WORKAREASIZE 1024\n\n# 8kB Flash\nset FLASHSTART  0x8000\nset FLASHEND    0x9fff\n\n# 256B EEPROM\nset EEPROMSTART 0x1000\nset EEPROMEND   0x10ff\n\nset OPTIONSTART 0x4800\nset OPTIONEND   0x487f\n\nproc stm8_reset_rop {} {\n   mwb 0x4800 0xaa\n   mwb 0x4800 0xaa\n   reset halt\n}\n\nsource [find target/stm8l.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8l152.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho 'DEPRECATED: choose between stm8l15xx4.cfg, stm8l15xx6.cfg and stm8l15xx8.cfg instead of stm8l152.cfg'\necho '            using stm8l152.cfg for backwards compatability'\n\nset EEPROMSTART 0x1000\nset EEPROMEND 0x13ff\n\nproc stm8_reset_rop {} {\n   mwb 0x4800 0xaa\n   mwb 0x4800 0xaa\n   reset halt\n}\n\nsource [find target/stm8l.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8l15xx4.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config script for STM8L151x4/STM8L152x4\n# Supported Devices:\n# STM8L151C4\n# STM8L151G4\n# STM8L151K4\n# STM8L152C4\n# STM8L152K4\n\n# 2kB RAM\n# Start 0x0000\n# End   0x07ff\nset WORKAREASIZE 2048\n\n# 16kB Flash\nset FLASHSTART  0x8000\nset FLASHEND    0xbfff\n\n# 1kB EEPROM\nset EEPROMSTART 0x1000\nset EEPROMEND   0x13ff\n\nset OPTIONSTART 0x4800\nset OPTIONEND   0x48ff\n\nproc stm8_reset_rop {} {\n   mwb 0x4800 0xaa\n   mwb 0x4800 0xaa\n   reset halt\n}\n\nsource [find target/stm8l.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8l15xx6.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config script for STM8L151x6/STM8L152x6\n# Supported Devices:\n# STM8L151C6\n# STM8L151G6\n# STM8L151K6\n# STM8L151R6\n# STM8L152C6\n# STM8L152K6\n# STM8L152R6\n\n# 2kB RAM\n# Start 0x0000\n# End   0x07ff\nset WORKAREASIZE 2048\n\n# 32kB Flash\nset FLASHSTART  0x8000\nset FLASHEND    0xffff\n\n# 1kB EEPROM\nset EEPROMSTART 0x1000\nset EEPROMEND   0x13ff\n\nset OPTIONSTART 0x4800\nset OPTIONEND   0x48ff\n\nproc stm8_reset_rop {} {\n   mwb 0x4800 0xaa\n   mwb 0x4800 0xaa\n   reset halt\n}\n\nsource [find target/stm8l.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8l15xx8.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Config script for STM8L151x8/STM8L152x8\n# Supported Devices:\n# STM8L151C8\n# STM8L151M8\n# STM8L151R8\n# STM8L152C8\n# STM8L152K8\n# STM8L152M8\n# STM8L152R8\n\n# 4kB RAM\n# Start 0x0000\n# End   0x0fff\nset WORKAREASIZE 4096\n\n# 64kB Flash\nset FLASHSTART  0x08000\nset FLASHEND    0x17fff\n\n# 2kB EEPROM\nset EEPROMSTART 0x1000\nset EEPROMEND   0x17ff\n\nset OPTIONSTART 0x4800\nset OPTIONEND   0x48ff\n\nproc stm8_reset_rop {} {\n   mwb 0x4800 0xaa\n   mwb 0x4800 0xaa\n   reset halt\n}\n\nsource [find target/stm8l.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8s.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for stm8s family\n\n#\n# stm8 devices support SWIM transports only.\n#\n\ntransport select swim\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME stm8s\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 1kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x400\n}\n\nif { [info exists FLASHSTART] } {\n   set _FLASHSTART $FLASHSTART\n} else {\n   set _FLASHSTART 0x8000\n}\n\nif { [info exists FLASHEND] } {\n   set _FLASHEND $FLASHEND\n} else {\n   set _FLASHEND 0xffff\n}\n\nif { [info exists EEPROMSTART] } {\n   set _EEPROMSTART $EEPROMSTART\n} else {\n   set _EEPROMSTART 0x4000\n}\n\nif { [info exists EEPROMEND] } {\n   set _EEPROMEND $EEPROMEND\n} else {\n   set _EEPROMEND 0x43ff\n}\n\nif { [info exists OPTIONSTART] } {\n   set _OPTIONSTART $OPTIONSTART\n} else {\n   set _OPTIONSTART 0x4800\n}\n\nif { [info exists OPTIONEND] } {\n   set _OPTIONEND $OPTIONEND\n} else {\n   set _OPTIONEND 0x487f\n}\n\nif { [info exists BLOCKSIZE] } {\n   set _BLOCKSIZE $BLOCKSIZE\n} else {\n   set _BLOCKSIZE 0x80\n}\n\nswim newtap $_CHIPNAME cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME stm8 -chain-position $_CHIPNAME.cpu\n\n$_TARGETNAME configure -work-area-phys 0x0 -work-area-size $_WORKAREASIZE -work-area-backup 1\n$_TARGETNAME configure -flashstart $_FLASHSTART -flashend $_FLASHEND -eepromstart $_EEPROMSTART -eepromend $_EEPROMEND\n$_TARGETNAME configure -optionstart $_OPTIONSTART -optionend $_OPTIONEND -blocksize $_BLOCKSIZE\n\n# Uncomment this line to enable interrupts while instruction step\n#$_TARGETNAME configure -enable_step_irq\n\n# Set high speed\nadapter speed 800\n# Set low speed\n#adapter speed 363\n\nreset_config srst_only\n\n# uncomment this line to connect under reset\n#reset_config srst_nogate connect_assert_srst\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8s003.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#config script for STM8S003\n\nset FLASHEND 0x9FFF\nset BLOCKSIZE 0x40\n\nproc stm8_reset_rop {} {\n   mwb 0x4800 0x00\n   reset halt\n}\n\nsource [find target/stm8s.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8s103.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#config script for STM8S103\n\nset FLASHEND 0x9FFF\nset EEPROMEND 0x427F\nset OPTIONEND 0x480A\nset BLOCKSIZE 0x40\n\nproc stm8_reset_rop {} {\n   mwb 0x4800 0x00\n   reset halt\n}\n\nsource [find target/stm8s.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/stm8s105.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#config script for STM8S105\n\nproc stm8_reset_rop {} {\n   mwb 0x4800 0x00\n   reset halt\n}\n\nsource [find target/stm8s.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/str710.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#start slow, speed up after reset\nadapter speed 10\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME str710\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x3f0f0f0f\n}\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config trst_and_srst srst_pulls_trst\n\n#jtag scan chain\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-start { adapter speed 10 }\n$_TARGETNAME configure -event reset-init {\n\tadapter speed 6000\n\n# Because the hardware cannot be interrogated for the protection state\n# of sectors, initialize all the sectors to be unprotected. The initial\n# state is reflected by the driver, too.\n\tflash protect 0 0 last off\n\tflash protect 1 0 last off\n}\n$_TARGETNAME configure -event gdb-flash-erase-start {\n\tflash protect 0 0 7 off\n\tflash protect 1 0 1 off\n}\n\n$_TARGETNAME configure -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0\n\n#flash bank str7x <base> <size> 0 0 <target#> <variant>\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 $_TARGETNAME STR71x\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/str730.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#STR730 CPU\n\nadapter speed 3000\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME str730\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x3f0f0f0f\n}\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config trst_and_srst srst_pulls_trst\n\n#jtag scan chain\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID\n\n#jtag nTRST and nSRST delay\nadapter srst delay 500\njtag_ntrst_delay 500\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian little -chain-position 0\n\n$_TARGETNAME configure -event reset-start { adapter speed 10 }\n$_TARGETNAME configure -event reset-init {\n\tadapter speed 3000\n\n# Because the hardware cannot be interrogated for the protection state\n# of sectors, initialize all the sectors to be unprotected. The initial\n# state is reflected by the driver, too.\n\tflash protect 0 0 last off\n}\n$_TARGETNAME configure -event gdb-flash-erase-start {\n\tflash protect 0 0 7 off\n}\n\n$_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x4000 -work-area-backup 0\n\n#flash bank <driver> <base> <size> <chip_width> <bus_width>\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR73x\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/str750.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#STR750 CPU\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME str750\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x4f1f0041\n}\n\n# jtag speed\nadapter speed 10\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config trst_and_srst srst_pulls_trst\n\n#jtag scan chain\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID\n\n#jtag nTRST and nSRST delay\nadapter srst delay 500\njtag_ntrst_delay 500\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian little -chain-position 0\n\n$_TARGETNAME configure -event reset-start { adapter speed 10 }\n$_TARGETNAME configure -event reset-init {\n\tadapter speed 3000\n\n\tinit_smi\n# Because the hardware cannot be interrogated for the protection state\n# of sectors, initialize all the sectors to be unprotected. The initial\n# state is reflected by the driver, too.\n\tflash protect 0 0 last off\n\tflash protect 1 0 last off\n}\n$_TARGETNAME configure -event gdb-flash-erase-start {\n\tflash protect 0 0 7 off\n\tflash protect 1 0 1 off\n}\n\n$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0\n\n#flash bank <driver> <base> <size> <chip_width> <bus_width>\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x\n\n# Serial NOR on SMI CS0.\nset _FLASHNAME $_CHIPNAME.snor\nflash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME\n\nsource [find mem_helper.tcl]\n\nproc init_smi {} {\n\tmmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs\n\tmmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit\n\tmmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/str912.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# script for str9\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME str912\n}\n\nif { [info exists ENDIAN] } {\n   set _ENDIAN $ENDIAN\n} else {\n   set _ENDIAN little\n}\n\n# jtag speed. We need to stick to 16kHz until we've finished reset.\nadapter speed 16\n\nadapter srst delay 100\njtag_ntrst_delay 100\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config trst_and_srst\n\nif { [info exists FLASHTAPID] } {\n   set _FLASHTAPID $FLASHTAPID\n} else {\n   set _FLASHTAPID 0x04570041\n}\njtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x25966041\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n\nif { [info exists BSTAPID] } {\n   set _BSTAPID $BSTAPID\n} else {\n   # possible values: 0x1457f041, 0x2457f041\n   # we ignore version in check below\n   set _BSTAPID 0x1457f041\n}\njtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID -ignore-version\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-start { adapter speed 16 }\n\n$_TARGETNAME configure -event reset-init {\n\t# We can increase speed now that we know the target is halted.\n\t#adapter speed 3000\n\n\t# -- Enable 96K RAM\n\t# PFQBC enabled / DTCM & AHB wait-states disabled\n\tmww 0x5C002034 0x0191\n\n\tstr9x flash_config 0 4 2 0 0x80000\n\tflash protect 0 0 7 off\n}\n\n$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0\n\n#flash bank str9x <base> <size> 0 0 <target#> <variant>\nset _FLASHNAME $_CHIPNAME.flash0\nflash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 $_TARGETNAME\nset _FLASHNAME $_CHIPNAME.flash1\nflash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 $_TARGETNAME\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/swj-dp.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# ARM Debug Interface V5 (ADI_V5) utility\n# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since\n# SW-DP and JTAG-DP targets don't need to switch based\n# on which transport is active.\n#\n# declare a JTAG or SWD Debug Access Point (DAP)\n# based on the transport in use with this session.\n# You can't access JTAG ops when SWD is active, etc.\n\n# params are currently what \"jtag newtap\" uses\n# because OpenOCD internals are still strongly biased\n# to JTAG ....  but for SWD, \"irlen\" etc are ignored,\n# and the internals work differently\n\n# for now, ignore non-JTAG and non-SWD transports\n# (e.g. initial flash programming via SPI or UART)\n\n# split out \"chip\" and \"tag\" so we can someday handle\n# them more uniformly irlen too...)\n\nif [catch {transport select}] {\n  echo \"Error: unable to select a session transport. Can't continue.\"\n  shutdown\n}\n\nproc swj_newdap {chip tag args} {\n if [using_jtag] {\n     eval jtag newtap $chip $tag $args\n } elseif [using_swd] {\n     eval swd newdap $chip $tag $args\n } else {\n     echo \"Error: transport '[ transport select ]' not supported by swj_newdap\"\n     shutdown\n }\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/swm050.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Synwit SWM050\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME swm050\n}\nset _CHIPSERIES swm050\n\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x400\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x0bb11477\n}\n\nswj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME swm050 0x0 0x2000 0 0 $_TARGETNAME\n\nadapter speed 1000\n\n$_TARGETNAME configure -event reset-init {\n\t# Stop the watchdog, just to be safe\n\tmww 0x40019000 0x00\n\t# Set clock divider value to 1\n\tmww 0x400F0000 0x01\n\t# Set system clock to 18Mhz\n\tmww 0x400F0008 0x00\n}\n\n# SWM050 (Cortex-M0 core) supports SYSRESETREQ\nif {![using_hla]} {\n    # if srst is not fitted use SYSRESETREQ to\n    # perform a soft reset\n    cortex_m reset_config sysresetreq\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/test_reset_syntax_error.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Test script to check that syntax error in reset\n# script is reported properly.\n\n# at91eb40a target\n\n#jtag scan chain\nset _CHIPNAME syntaxtest\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf\n\n#target configuration\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME\n\n$_TARGETNAME configure -event reset-init {\n\n\tsyntax error\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/test_syntax_error.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# This script tests a syntax error in the startup\n# config script\n\nsyntax error here\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti-ar7.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments AR7 SOC - used in many adsl modems.\n# http://www.linux-mips.org/wiki/AR7\n#\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME ti-ar7\n}\n\nif { [info exists ENDIAN] } {\n    set _ENDIAN $ENDIAN\n} else {\n    set _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n    set _CPUTAPID $CPUTAPID\n} else {\n    set _CPUTAPID 0x0000100f\n}\n\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_CHIPNAME.cpu\n\n# use onboard 4k sram as working area\n$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti-cjtag.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# A start sequence to change from cJTAG to 4-pin JTAG\n# This is needed for CC2538 and CC26xx to be able to communicate through JTAG\n# Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information.\nproc ti_cjtag_to_4pin_jtag {jrc} {\n\t# Bypass\n\truntest 20\n\tirscan $jrc 0x3f -endstate RUN/IDLE\n\t# Two zero bit scans and a one bit drshift\n\tpathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE\n\tpathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE\n\tpathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE\n\tpathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE\n\tpathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE\n\tpathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRUPDATE RUN/IDLE\n\tpathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE\n\n\t# A two bit drhift and a 9 bit drshift\n\tpathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRUPDATE RUN/IDLE\n\tpathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE\n\tpathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE\n\tpathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE\n\tpathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE\n\tpathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE\n\tpathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRPAUSE\n\tpathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE\n\tpathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE\n\n\t# Bypass\n\tirscan $jrc 0x3f -endstate RUN/IDLE\n\n\t# Set ICEPick IDCODE in data register\n\tirscan $jrc 0x04 -endstate RUN/IDLE\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_calypso.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# TI Calypso (lite) G2 C035 Digital Base Band chip\n#\n# ARM7TDMIE + DSP subchip (S28C128)\n#\n# 512K SRAM Calypso\n# 256K SRAM Calypso lite\n#\nif { [info exists CHIPNAME] } {\n\tset  _CHIPNAME $CHIPNAME\n} else {\n\tset  _CHIPNAME calypso\n}\n\nif { [info exists ENDIAN] } {\n\tset  _ENDIAN $ENDIAN\n} else {\n\tset  _ENDIAN little\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x3100e02f\n}\n\n# Work-area is a space in RAM used for flash programming\n# By default use 64kB\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x10000\n}\n\nadapter speed 1000\n\nreset_config trst_and_srst\n\njtag newtap $_CHIPNAME dsp -expected-id 0x00000000 -irlen 8\njtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n# target\n\nset _TARGETNAME $_CHIPNAME.arm\ntarget create $_TARGETNAME arm7tdmi -endian little -chain-position $_TARGETNAME\n\n# workarea\n\n$_TARGETNAME configure -work-area-phys 0x00800000 -work-area-size $_WORKAREASIZE -work-area-backup 1\n\narm7_9 dcc_downloads enable\narm7_9 fast_memory_access enable\n\n$_TARGETNAME configure -event examine-start {\n\tirscan calypso.arm 0x0b -endstate DRPAUSE\n\tdrscan calypso.arm 2 2 -endstate RUN/IDLE\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_cc13x0.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments CC13x0 - ARM Cortex-M3\n#\n# http://www.ti.com\n#\n\nset CHIPNAME cc13x0\nset JRC_TAPID 0x0B9BE02F\nset WORKAREASIZE 0x4000\n\nsource [find target/ti_cc26x0.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_cc13x2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments CC13x2 - ARM Cortex-M4\n#\n# http://www.ti.com\n#\n\nset CHIPNAME cc13x2\nset JRC_TAPID 0x0BB4102F\nset WORKAREASIZE 0x7000\n\nsource [find target/ti_cc26x0.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_cc26x0.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments CC26x0 - ARM Cortex-M3\n#\n# http://www.ti.com\n#\n\nsource [find target/icepick.cfg]\nsource [find target/ti-cjtag.cfg]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME cc26x0\n}\n\n#\n# Main DAP\n#\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tset _DAP_TAPID 0x4BA00477\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable\njtag configure $_CHIPNAME.cpu -event tap-enable \"icepick_c_tapenable $_CHIPNAME.jrc 0\"\n\n#\n# ICEpick-C (JTAG route controller)\n#\nif { [info exists JRC_TAPID] } {\n\tset _JRC_TAPID $JRC_TAPID\n} else {\n\tset _JRC_TAPID 0x0B99A02F\n}\njtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version\njtag configure $_CHIPNAME.jrc -event setup \"jtag tapenable $_CHIPNAME.cpu\"\n# A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG\njtag configure $_CHIPNAME.jrc -event post-reset \"ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc\"\n\nset _TARGETNAME $_CHIPNAME.cpu\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x4000\n}\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME\n\ncortex_m reset_config vectreset\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_cc26x2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments CC26x2 - ARM Cortex-M4\n#\n# http://www.ti.com\n#\n\nset CHIPNAME cc26x2\nset JRC_TAPID 0x0BB4102F\nset WORKAREASIZE 0x7000\n\nsource [find target/ti_cc26x0.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_cc3220sf.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments CC3220SF - ARM Cortex-M4\n#\n# http://www.ti.com/CC3220SF\n#\n\nsource [find target/swj-dp.tcl]\nsource [find target/icepick.cfg]\nsource [find target/ti_cc32xx.cfg]\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME\n\n#\n# On CC32xx family of devices, sysreqreset is disabled, and vectreset is\n# blocked by the boot loader (stops in a while(1) statement). srst reset can\n# leave the target in a state that prevents debug. The following uses the\n# soft_reset_halt command to reset and halt the target. Then the PC and stack\n# are initialized from internal flash. This allows for a more reliable reset,\n# but with two caveats: it only works for the SF variant that has internal\n# flash, and it only resets the CPU and not any peripherals.\n#\n\nproc ocd_process_reset_inner { MODE } {\n\n\tsoft_reset_halt\n\n\t# Initialize MSP, PSP, and PC from vector table at flash 0x01000800\n\tset boot [read_memory 0x01000800 32 2]\n\n\treg msp [lindex $boot 0]\n\treg psp [lindex $boot 0]\n\treg pc [lindex $boot 1]\n\n\tif { 0 == [string compare $MODE run ] } {\n\t\tresume\n\t}\n\n\tcc32xx.cpu invoke-event reset-end\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_cc32xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments CC32xx - ARM Cortex-M4\n#\n# http://www.ti.com/product/CC3200\n# http://www.ti.com/product/CC3220\n#\n\nsource [find target/swj-dp.tcl]\nsource [find target/icepick.cfg]\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME cc32xx\n}\n\n#\n# Main DAP\n#\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n} else {\n\tif {[using_jtag]} {\n\t\tset _DAP_TAPID 0x4BA00477\n\t} else {\n\t\tset _DAP_TAPID 0x2BA01477\n\t}\n}\n\nif {[using_jtag]} {\n\tjtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable\n\tjtag configure $_CHIPNAME.cpu -event tap-enable \"icepick_c_tapenable $_CHIPNAME.jrc 0\"\n} else {\n\tswj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID\n}\n\n#\n# ICEpick-C (JTAG route controller)\n#\nif { [info exists JRC_TAPID] } {\n\tset _JRC_TAPID $JRC_TAPID\n} else {\n\tset _JRC_TAPID 0x0B97C02F\n}\n\nif {[using_jtag]} {\n\tjtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version\n\tjtag configure $_CHIPNAME.jrc -event setup \"jtag tapenable $_CHIPNAME.cpu\"\n}\n\nset _TARGETNAME $_CHIPNAME.cpu\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x2000\n}\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_dm355.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments DaVinci family: TMS320DM355\n#\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME dm355\n}\n\n# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*\n# after JTAG reset until ICEpick is used to route them in.\nset EMU01 \"-disable\"\n\n# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without\n# needing any ICEpick interaction.\n#set EMU01 \"-enable\"\n\nsource [find target/icepick.cfg]\n\n#\n# Also note: when running without RTCK before the PLLs are set up, you\n# may need to slow the JTAG clock down quite a lot (under 2 MHz).\n#\n\n# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer\nif { [info exists ETB_TAPID] } {\n   set _ETB_TAPID $ETB_TAPID\n} else {\n   set _ETB_TAPID 0x2b900f0f\n}\njtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01\njtag configure $_CHIPNAME.etb -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 1\"\n\n# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.\nif { [info exists CPU_TAPID] } {\n   set _CPU_TAPID $CPU_TAPID\n} else {\n   set _CPU_TAPID 0x07926001\n}\njtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01\njtag configure $_CHIPNAME.arm -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 0\"\n\n# Primary TAP: ICEpick (JTAG route controller) and boundary scan\nif { [info exists JRC_TAPID] } {\n   set _JRC_TAPID $JRC_TAPID\n} else {\n   set _JRC_TAPID 0x0b73b02f\n}\njtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID\n\njtag configure $_CHIPNAME.jrc -event setup \\\n\t\"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm\"\n\n################\n\n# various symbol definitions, to avoid hard-wiring addresses\n# and enable some sharing of DaVinci-family utility code\nglobal dm355\nset dm355 [ dict create ]\n\n# Physical addresses for controllers and memory\n# (Some of these are valid for many DaVinci family chips)\ndict set dm355 sram0\t\t0x00010000\ndict set dm355 sram1\t\t0x00014000\ndict set dm355 sysbase\t\t0x01c40000\ndict set dm355 pllc1\t\t0x01c40800\ndict set dm355 pllc2\t\t0x01c40c00\ndict set dm355 psc\t\t0x01c41000\ndict set dm355 gpio\t\t0x01c67000\ndict set dm355 a_emif\t\t0x01e10000\ndict set dm355 a_emif_cs0\t0x02000000\ndict set dm355 a_emif_cs1\t0x04000000\ndict set dm355 ddr_emif\t\t0x20000000\ndict set dm355 ddr\t\t0x80000000\ndict set dm355 uart0\t\t0x01c20000\ndict set dm355 uart1\t\t0x01c20400\ndict set dm355 uart2\t\t0x01e06000\n\nsource [find target/davinci.cfg]\n\n################\n# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)\n# and the ETB memory (4K) are other options, while trace is unused.\nset _TARGETNAME $_CHIPNAME.arm\n\ntarget create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME\n\n# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,\n# and that the work area is used only with a kernel mmu context ...\n$_TARGETNAME configure \\\n\t-work-area-virt [expr {0xfffe0000 + 0x4000}] \\\n\t-work-area-phys [dict get $dm355 sram1] \\\n\t-work-area-size 0x4000 \\\n\t-work-area-backup 0\n\n# be absolutely certain the JTAG clock will work with the worst-case\n# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns\n# on the PLL and starts using it.  OK to speed up after clock setup.\nadapter speed 1500\n$_TARGETNAME configure -event \"reset-start\" { adapter speed 1500 }\n\narm7_9 fast_memory_access enable\narm7_9 dcc_downloads enable\n\n# trace setup\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_dm365.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments DaVinci family: TMS320DM365\n#\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME dm365\n}\n\n# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*\n# after JTAG reset until ICEpick is used to route them in.\nset EMU01 \"-disable\"\n\n# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without\n# needing any ICEpick interaction.\n#set EMU01 \"-enable\"\n\nsource [find target/icepick.cfg]\n\n# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer\nif { [info exists ETB_TAPID] } {\n   set _ETB_TAPID $ETB_TAPID\n} else {\n   set _ETB_TAPID 0x2b900f0f\n}\njtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01\njtag configure $_CHIPNAME.etb -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 1\"\n\n# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.\nif { [info exists CPU_TAPID] } {\n   set _CPU_TAPID $CPU_TAPID\n} else {\n   set _CPU_TAPID 0x0792602f\n}\njtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01\njtag configure $_CHIPNAME.arm -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 0\"\n\n# Primary TAP: ICEpick (JTAG route controller) and boundary scan\nif { [info exists JRC_TAPID] } {\n   set _JRC_TAPID $JRC_TAPID\n} else {\n   set _JRC_TAPID 0x0b83e02f\n}\njtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID\n\njtag configure $_CHIPNAME.jrc -event setup \\\n\t\"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm\"\n\n################\n\n# various symbol definitions, to avoid hard-wiring addresses\n# and enable some sharing of DaVinci-family utility code\nglobal dm365\nset dm365 [ dict create ]\n\n# Physical addresses for controllers and memory\n# (Some of these are valid for many DaVinci family chips)\ndict set dm365 sram0\t\t0x00010000\ndict set dm365 sram1\t\t0x00014000\ndict set dm365 sysbase\t\t0x01c40000\ndict set dm365 pllc1\t\t0x01c40800\ndict set dm365 pllc2\t\t0x01c40c00\ndict set dm365 psc\t\t0x01c41000\ndict set dm365 gpio\t\t0x01c67000\ndict set dm365 a_emif\t\t0x01d10000\ndict set dm365 a_emif_cs0\t0x02000000\ndict set dm365 a_emif_cs1\t0x04000000\ndict set dm365 ddr_emif\t\t0x20000000\ndict set dm365 ddr\t\t0x80000000\n\nsource [find target/davinci.cfg]\n\n################\n# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)\n# and the ETB memory (4K) are other options, while trace is unused.\nset _TARGETNAME $_CHIPNAME.arm\n\ntarget create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME\n\n# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,\n# and that the work area is used only with a kernel mmu context ...\n$_TARGETNAME configure \\\n\t-work-area-virt [expr {0xfffe0000 + 0x4000}] \\\n\t-work-area-phys [dict get $dm365 sram1] \\\n\t-work-area-size 0x4000 \\\n\t-work-area-backup 0\n\n# be absolutely certain the JTAG clock will work with the worst-case\n# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns\n# on the PLL and starts using it.  OK to speed up after clock setup.\nadapter speed 1500\n$_TARGETNAME configure -event \"reset-start\" { adapter speed 1500 }\n\narm7_9 fast_memory_access enable\narm7_9 dcc_downloads enable\n\n# trace setup\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_dm6446.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments DaVinci family: TMS320DM6446\n#\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME dm6446\n}\n\n# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*\n# after JTAG reset until ICEpick is used to route them in.\nset EMU01 \"-disable\"\n\n# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without\n# needing any ICEpick interaction.\n#set EMU01 \"-enable\"\n\nsource [find target/icepick.cfg]\n\n# Subsidiary TAP: unknown ... must enable via ICEpick\njtag newtap $_CHIPNAME unknown -irlen 8 -disable\njtag configure $_CHIPNAME.unknown -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 3\"\n\n# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick\njtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable\njtag configure $_CHIPNAME.dsp -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 2\"\n\n# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer\nif { [info exists ETB_TAPID] } {\n   set _ETB_TAPID $ETB_TAPID\n} else {\n   set _ETB_TAPID 0x2b900f0f\n}\njtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01\njtag configure $_CHIPNAME.etb -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 1\"\n\n# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.\nif { [info exists CPU_TAPID] } {\n   set _CPU_TAPID $CPU_TAPID\n} else {\n   set _CPU_TAPID 0x07926001\n}\njtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01\njtag configure $_CHIPNAME.arm -event tap-enable \\\n\t\"icepick_c_tapenable $_CHIPNAME.jrc 0\"\n\n# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan\nif { [info exists JRC_TAPID] } {\n   set _JRC_TAPID $JRC_TAPID\n} else {\n   set _JRC_TAPID 0x0b70002f\n}\njtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID\n\njtag configure $_CHIPNAME.jrc -event setup \\\n\t\"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm\"\n\n################\n# GDB target: the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)\n# and the ETB memory (4K) are other options, while trace is unused.\n# Little-endian; use the OpenOCD default.\nset _TARGETNAME $_CHIPNAME.arm\n\ntarget create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME\n$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000\n\n# be absolutely certain the JTAG clock will work with the worst-case\n# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns\n# on the PLL and starts using it.  OK to speed up after clock setup.\nadapter speed 1500\n$_TARGETNAME configure -event \"reset-start\" { adapter speed 1500 }\n\narm7_9 fast_memory_access enable\narm7_9 dcc_downloads enable\n\n# trace setup\netm config $_TARGETNAME 16 normal full etb\netb config $_TARGETNAME $_CHIPNAME.etb\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_k3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/\n#\n# Texas Instruments K3 devices:\n# * AM654x: https://www.ti.com/lit/pdf/spruid7\n#  Has 4 ARMV8 Cores and 2 R5 Cores and an M3\n# * J721E: https://www.ti.com/lit/pdf/spruil1\n#  Has 2 ARMV8 Cores and 6 R5 Cores and an M3\n# * J7200: https://www.ti.com/lit/pdf/spruiu1\n#  Has 2 ARMV8 Cores and 4 R5 Cores and an M3\n# * J721S2: https://www.ti.com/lit/pdf/spruj28\n#  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F\n# * AM642: https://www.ti.com/lit/pdf/spruim2\n#  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3\n# * AM625: https://www.ti.com/lit/pdf/spruiv7a\n#  Has 4 ARMV8 Cores and 1 R5 Core and an M4F\n# * AM62a7: https://www.ti.com/lit/pdf/spruj16a\n#  Has 4 ARMV8 Cores and 2 R5 Cores\n#\n\nsource [find target/swj-dp.tcl]\n\nif { [info exists SOC] } {\n\tset _soc $SOC\n} else {\n\tset _soc am654\n}\n\n# set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug\nif { [info exists V8_SMP_DEBUG] } {\n\tset _v8_smp_debug $V8_SMP_DEBUG\n} else {\n\tset _v8_smp_debug 0\n}\n\n# Common Definitions\n\n# System Controller is the very first processor - all current SoCs have it.\nset CM3_CTIBASE\t\t{0x3C016000}\n\n# sysctrl power-ap unlock offsets\nset _sysctrl_ap_unlock_offsets {0xf0 0x44}\n\n# All the ARMV8s are the next processors.\n#\t\t   CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1\nset ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}\nset ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}\n\n# And we add up the R5s\n#\t\t(0)MCU 0   (1)MCU 1   (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1\nset R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}\nset R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}\nset R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}\n\n# Finally an General Purpose(GP) MCU\nset CM4_CTIBASE\t\t{0x20001000}\n\n# General Purpose MCU (M4) may be present on some very few SoCs\nset _gp_mcu_cores 0\n# General Purpose MCU power-ap unlock offsets\nset _gp_mcu_ap_unlock_offsets {0xf0 0x60}\n\n# Set configuration overrides for each SOC\nswitch $_soc {\n\tam654 {\n\t\tset _CHIPNAME am654\n\t\tset _K3_DAP_TAPID 0x0bb5a02f\n\n\t\t# AM654 has 2 clusters of 2 A53 cores each.\n\t\tset _armv8_cpu_name a53\n\t\tset _armv8_cores 4\n\n\t\t# AM654 has 1 cluster of 2 R5s cores.\n\t\tset _r5_cores 2\n\t\tset R5_NAMES {mcu_r5.0 mcu_r5.1}\n\n\t\t# Sysctrl power-ap unlock offsets\n\t\tset _sysctrl_ap_unlock_offsets {0xf0 0x50}\n\t}\n\tam642 {\n\t\tset _CHIPNAME am642\n\t\tset _K3_DAP_TAPID 0x0bb3802f\n\n\t\t# AM642 has 1 clusters of 2 A53 cores each.\n\t\tset _armv8_cpu_name a53\n\t\tset _armv8_cores 2\n\t\tset ARMV8_DBGBASE {0x90010000 0x90110000}\n\t\tset ARMV8_CTIBASE {0x90020000 0x90120000}\n\n\t\t# AM642 has 2 cluster of 2 R5s cores.\n\t\tset _r5_cores 4\n\t\tset R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}\n\t\tset R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}\n\t\tset R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}\n\n\t\t# M4 processor\n\t\tset _gp_mcu_cores 1\n\t}\n\tam625 {\n\t\tset _CHIPNAME am625\n\t\tset _K3_DAP_TAPID 0x0bb7e02f\n\n\t\t# AM625 has 1 clusters of 4 A53 cores.\n\t\tset _armv8_cpu_name a53\n\t\tset _armv8_cores 4\n\t\tset ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}\n\t\tset ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}\n\n\t\t# AM625 has 1 cluster of 1 R5s core.\n\t\tset _r5_cores 1\n\t\tset R5_NAMES {main0_r5.0}\n\t\tset R5_DBGBASE {0x9d410000}\n\t\tset R5_CTIBASE {0x9d418000}\n\n\t\t# sysctrl CTI base\n\t\tset CM3_CTIBASE {0x20001000}\n\t\t# Sysctrl power-ap unlock offsets\n\t\tset _sysctrl_ap_unlock_offsets {0xf0 0x78}\n\n\t\t# M4 processor\n\t\tset _gp_mcu_cores 1\n\t\tset _gp_mcu_ap_unlock_offsets {0xf0 0x7c}\n\n\t\t# Setup DMEM access descriptions\n\t\t# DAPBUS (Debugger) description\n\t\tset _dmem_base_address 0x740002000\n\t\tset _dmem_ap_address_offset 0x100\n\t\tset _dmem_max_aps 10\n\t\t# Emulated AP description\n\t\tset _dmem_emu_base_address 0x760000000\n\t\tset _dmem_emu_base_address_map_to 0x1d500000\n\t\tset _dmem_emu_ap_list 1\n\t}\n\tam62a7 {\n\t\tset _CHIPNAME am62a7\n\t\tset _K3_DAP_TAPID 0x0bb8d02f\n\n\t\t# AM62a7 has 1 clusters of 4 A53 cores.\n\t\tset _armv8_cpu_name a53\n\t\tset _armv8_cores 4\n\t\tset ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}\n\t\tset ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}\n\n\t\t# AM62a7 has 2 cluster of 1 R5s core.\n\t\tset _r5_cores 2\n\t\tset R5_NAMES {main0_r5.0 mcu0_r5.0}\n\t\tset R5_DBGBASE {0x9d410000 0x9d810000}\n\t\tset R5_CTIBASE {0x9d418000 0x9d818000}\n\n\t\t# sysctrl CTI base\n\t\tset CM3_CTIBASE {0x20001000}\n\t\t# Sysctrl power-ap unlock offsets\n\t\tset _sysctrl_ap_unlock_offsets {0xf0 0x78}\n\t}\n\tj721e {\n\t\tset _CHIPNAME j721e\n\t\tset _K3_DAP_TAPID 0x0bb6402f\n\t\t# J721E has 1 cluster of 2 A72 cores.\n\t\tset _armv8_cpu_name a72\n\t\tset _armv8_cores 2\n\n\t\t# J721E has 3 clusters of 2 R5 cores each.\n\t\tset _r5_cores 6\n\n\t\t# Setup DMEM access descriptions\n\t\t# DAPBUS (Debugger) description\n\t\tset _dmem_base_address 0x4c40002000\n\t\tset _dmem_ap_address_offset 0x100\n\t\tset _dmem_max_aps 8\n\t\t# Emulated AP description\n\t\tset _dmem_emu_base_address 0x4c60000000\n\t\tset _dmem_emu_base_address_map_to 0x1d600000\n\t\tset _dmem_emu_ap_list 1\n\t}\n\tj7200 {\n\t\tset _CHIPNAME j7200\n\t\tset _K3_DAP_TAPID 0x0bb6d02f\n\n\t\t# J7200 has 1 cluster of 2 A72 cores.\n\t\tset _armv8_cpu_name a72\n\t\tset _armv8_cores 2\n\n\t\t# J7200 has 2 clusters of 2 R5 cores each.\n\t\tset _r5_cores 4\n\t\tset R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}\n\t\tset R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}\n\n\t\t# M3 CTI base\n\t\tset CM3_CTIBASE {0x20001000}\n\t}\n\tj721s2 {\n\t\tset _CHIPNAME j721s2\n\t\tset _K3_DAP_TAPID 0x0bb7502f\n\n\t\t# J721s2 has 1 cluster of 2 A72 cores.\n\t\tset _armv8_cpu_name a72\n\t\tset _armv8_cores 2\n\n\t\t# J721s2 has 3 clusters of 2 R5 cores each.\n\t\tset _r5_cores 6\n\n\t\t# sysctrl CTI base\n\t\tset CM3_CTIBASE {0x20001000}\n\t\t# Sysctrl power-ap unlock offsets\n\t\tset _sysctrl_ap_unlock_offsets {0xf0 0x78}\n\n\t\t# M4 processor\n\t\tset _gp_mcu_cores 1\n\t\tset _gp_mcu_ap_unlock_offsets {0xf0 0x7c}\n\t}\n\tdefault {\n\t\techo \"'$_soc' is invalid!\"\n\t}\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\n\nset _CTINAME $_CHIPNAME.cti\n\n# sysctrl is always present\ncti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]\ntarget create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine\n$_TARGETNAME.sysctrl configure -event reset-assert { }\n\nproc sysctrl_up {} {\n\t# To access sysctrl, we need to enable the JTAG access for the same.\n\t# Ensure Power-AP unlocked\n\t$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000\n\t$::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098\n\n\t$::_TARGETNAME.sysctrl arp_examine\n}\n\n$_TARGETNAME.sysctrl configure -event gdb-attach {\n\tsysctrl_up\n\t# gdb-attach default rule\n\thalt 1000\n}\n\nproc _cpu_no_smp_up {} {\n\tset _current_target [target current]\n\tset _current_type [$_current_target cget -type]\n\n\t$_current_target arp_examine\n\t$_current_target $_current_type dbginit\n}\n\nproc _armv8_smp_up {} {\n\tfor { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {\n\t\t$::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine\n\t\t$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit\n\t\t$::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on\n\t}\n\t# Set Default target as core 0\n\ttargets $::_TARGETNAME.$::_armv8_cpu_name.0\n}\n\nset _v8_smp_targets \"\"\n\nfor { set _core 0 } { $_core < $_armv8_cores } { incr _core } {\n\n\tcti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \\\n\t\t-baseaddr [lindex $ARMV8_CTIBASE $_core]\n\n\ttarget create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \\\n\t\t-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine\n\n\tset _v8_smp_targets \"$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core\"\n\n\tif { $_v8_smp_debug == 0 } {\n\t\t$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {\n\t\t\t_cpu_no_smp_up\n\t\t\t# gdb-attach default rule\n\t\t\thalt 1000\n\t\t}\n\t} else {\n\t\t$_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {\n\t\t\t_armv8_smp_up\n\t\t\t# gdb-attach default rule\n\t\t\thalt 1000\n\t\t}\n\t}\n}\n\n# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs\nset _armv8_up_cmd \"$_armv8_cpu_name\"_up\n# Available if V8_SMP_DEBUG is set to non-zero value\nset _armv8_smp_cmd \"$_armv8_cpu_name\"_smp\n\nif { $_v8_smp_debug == 0 } {\n\tproc $_armv8_up_cmd { args } {\n\t\tforeach _core $args {\n\t\t\ttargets $_core\n\t\t\t_cpu_no_smp_up\n\t\t}\n\t}\n} else {\n\tproc $_armv8_smp_cmd { args } {\n\t\t_armv8_smp_up\n\t}\n\t# Declare SMP\n\ttarget smp $:::_v8_smp_targets\n}\n\nfor { set _core 0 } { $_core < $_r5_cores } { incr _core } {\n\tset _r5_name [lindex $R5_NAMES $_core]\n\tcti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \\\n\t\t-baseaddr [lindex $R5_CTIBASE $_core]\n\n\t# inactive core examination will fail - wait till startup of additional core\n\ttarget create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \\\n\t\t-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine\n\n\t$_TARGETNAME.$_r5_name configure -event gdb-attach {\n\t\t_cpu_no_smp_up\n\t\t# gdb-attach default rule\n\t\thalt 1000\n\t}\n}\n\nproc r5_up { args } {\n\tforeach  _core $args {\n\t\ttargets $_core\n\t\t_cpu_no_smp_up\n\t}\n}\n\nif { $_gp_mcu_cores != 0 } {\n\tcti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]\n\ttarget create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine\n\t$_TARGETNAME.gp_mcu configure -event reset-assert { }\n\n\tproc gp_mcu_up {} {\n\t\t# To access GP MCU, we need to enable the JTAG access for the same.\n\t\t# Ensure Power-AP unlocked\n\t\t$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000\n\t\t$::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098\n\n\t\t$::_TARGETNAME.gp_mcu arp_examine\n\t}\n\n\t$_TARGETNAME.gp_mcu configure -event gdb-attach {\n\t\tgp_mcu_up\n\t\t# gdb-attach default rule\n\t\thalt 1000\n\t}\n}\n\n# In case of DMEM access, configure the dmem adapter with offsets from above.\nif { 0 == [string compare [adapter name] dmem ] } {\n\tif { [info exists _dmem_base_address] } {\n\t\t# DAPBUS (Debugger) description\n\t\tdmem base_address $_dmem_base_address\n\t\tdmem ap_address_offset $_dmem_ap_address_offset\n\t\tdmem max_aps $_dmem_max_aps\n\n\t\t# The following are the details of APs to be emulated for direct address access.\n\t\t# Debug Config (Debugger) description\n\t\tdmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to\n\t\tdmem emu_ap_list $_dmem_emu_ap_list\n\t\t# We are going local bus, so speed is really dummy here.\n\t\tadapter speed 2500\n\t} else {\n\t\tputs \"ERROR: ${SOC} data is missing to support dmem access!\"\n\t}\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_msp432.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Texas Instruments MSP432 - ARM Cortex-M4F @ up to 48 MHz\n#\n# http://www.ti.com/MSP432\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME msp432\n}\n\nif { [info exists CPUTAPID] } {\n\tset _DAP_TAPID $CPUTAPID\n} else {\n\tset _DAP_TAPID 0x4ba00477\n}\n\nif { [info exists DAP_SWD_ID] } {\n\tset _DAP_SWD_ID $DAP_SWD_ID\n} else {\n\tset _DAP_SWD_ID 0x2ba01477\n}\n\nsource [find target/swj-dp.tcl]\n\nif { [using_jtag] } {\n\tset _DAP_ID $_DAP_TAPID\n} else {\n\tset _DAP_ID $_DAP_SWD_ID\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\nif { [info exists WORKAREASIZE] } {\n\tset _WORKAREASIZE $WORKAREASIZE\n} else {\n\tset _WORKAREASIZE 0x4000\n}\n\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME\n\ncortex_m reset_config sysresetreq\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_rm4x.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nsource [find target/ti_tms570.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_tms570.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nadapter speed 1500\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME tms570\n}\n\nif { [info exists ENDIAN] } {\n\tset _ENDIAN $ENDIAN\n} else {\n\tset _ENDIAN big\n}\n\n# TMS570 has an ICEpick-C on which we need the router commands.\nsource [find target/icepick.cfg]\n\n# Main DAP\n# DAP_TAPID should be set before source-ing this file\nif { [info exists DAP_TAPID] } {\n\tset _DAP_TAPID $DAP_TAPID\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable -ignore-version\njtag configure $_CHIPNAME.cpu -event tap-enable \"icepick_c_tapenable $_CHIPNAME.jrc 0\"\n\n# ICEpick-C (JTAG route controller)\n# JRC_TAPID should be set before source-ing this file\nif { [info exists JRC_TAPID] } {\n\tset _JRC_TAPID $JRC_TAPID\n}\n\nset _JRC_TAPID2 0x0B7B302F\nset _JRC_TAPID3 0x0B95502F\nset _JRC_TAPID4 0x0B97102F\nset _JRC_TAPID5 0x0D8A002F\nset _JRC_TAPID6 0x0B8A002F\n\n\njtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \\\n\t-expected-id $_JRC_TAPID \\\n\t-expected-id $_JRC_TAPID2 \\\n\t-expected-id $_JRC_TAPID3 \\\n\t-expected-id $_JRC_TAPID4 \\\n\t-expected-id $_JRC_TAPID5 \\\n\t-expected-id $_JRC_TAPID6 \\\n\t-ignore-version\njtag configure $_CHIPNAME.jrc -event setup \"jtag tapenable $_CHIPNAME.cpu\"\njtag configure $_CHIPNAME.jrc -event post-reset \"runtest 100\"\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n# Cortex-R4 target\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_r4 -endian $_ENDIAN \\\n\t-dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80001000\n\n# TMS570 uses quirky BE-32 mode\n$_CHIPNAME.dap ti_be_32_quirks 1\n\n$_TARGETNAME configure -event \"reset-assert\" {\n\tglobal _CHIPNAME\n\n\t# assert warm system reset through ICEPick\n\ticepick_c_wreset $_CHIPNAME.jrc\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_tms570lc43xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nset DAP_TAPID 0x0B95A02F\nset JRC_TAPID 0x0B95A02F\n\nsource [find target/ti_tms570.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_tms570ls20xxx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# TMS570LS20216, TMS570LS20206, TMS570LS10216\n# TMS570LS10206, TMS570LS10116, TMS570LS10106\nset DAP_TAPID 0x0B7B302F\nset JRC_TAPID 0x0B7B302F\n\nsource [find target/ti_tms570.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/ti_tms570ls3137.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# TMS570LS3137\nset DAP_TAPID 0x0B8A002F\nset JRC_TAPID 0x0B8A002F\n\nsource [find target/ti_tms570.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/tmpa900.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Toshiba TMPA900\n######################################\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME tmpa900\n}\n\n# Toshiba TMPA900 series MCUs are always little endian as per datasheet.\nset _ENDIAN little\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07926031\n}\n\n#TMPA900 has following IDs:\n# CP15.0 register 0x41069265\n# CP15.1 register 0x1d152152\n# ARM core 0x07926031\n\n\n#\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config trst_and_srst\nadapter srst delay 20\njtag_ntrst_delay 20\n\n######################\n# Target configuration\n######################\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# Internal RAM-0 (16kB): 0xf8004000\n# Internal RAM-1 (8kB): 0xf8008000\n\n# Use internal RAM-0 and RAM-1 as working area (24kB total).\n$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0x6000 \\\n-work-area-backup 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/tmpa910.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n######################################\n# Target:    Toshiba TMPA910\n######################################\n\nif { [info exists CHIPNAME] } {\n   set _CHIPNAME $CHIPNAME\n} else {\n   set _CHIPNAME tmpa910\n}\n\n# Toshiba TMPA910 series MCUs are always little endian as per datasheet.\nset _ENDIAN little\n\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n   set _CPUTAPID 0x07926031\n}\n\n#TMPA910 has following IDs:\n# CP15.0 register 0x41069265\n# CP15.1 register 0x1d152152\n# ARM core 0x07926031\n\n\n#\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config trst_and_srst\nadapter srst delay 20\njtag_ntrst_delay 20\n\n######################\n# Target configuration\n######################\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME\n\n# Internal RAM-0 (16kB): 0xf8004000\n# Internal RAM-1 (16kB): 0xf8008000\n# Internal RAM-2 (16kB): 0xf800c000\n\n# Use internal RAM-0, RAM-1, and RAM-2 as working area (48kB total).\n$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0xc000 \\\n-work-area-backup 0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/tnetc4401.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Texas Instruments (TI) TNETC4401, MIPS32 DOCSIS-tailored SoC (4Kc-based)\n# Used in Knovative KC-100 and Motorola Surfboard SB5120 cable modems.\n# Datasheet: https://brezn.muc.ccc.de/~mazzoo/DOCSIS/tnetc4401.pdf\ntransport select jtag\nset _TARGETNAME tnetc4401\nset _CPUTAPID 0x0000100f\njtag newtap $_TARGETNAME tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id $_CPUTAPID\ntarget create $_TARGETNAME mips_m4k -chain-position $_TARGETNAME.tap -endian big\n\n# May need to halt manually before calling reset init\n$_TARGETNAME configure -event reset-init {\n\thalt\n\techo \"Attempting to disable watchdog...\"\n\tmwb phys 0xa8610b00 0 256\n\thalt\n\twait_halt\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/u8500.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#  Copyright (C) ST-Ericsson SA 2011\n#  Author : michel.jaouen@stericsson.com\n#  U8500 target\n\nproc mmu_off {} {\n\tset cp [arm mrc 15 0 1 0 0]\n\tset cp [expr {$cp & ~1}]\n\tarm mcr 15 0 1 0 0 $cp\n}\n\nproc mmu_on {} {\n\tset cp [arm mrc 15 0 1 0 0]\n\tset cp [expr {$cp | 1}]\n\tarm mcr 15 0 1 0 0 $cp\n}\n\nproc ocd_gdb_restart {target_id} {\n    global _TARGETNAME_1\n\tglobal _SMP\n    targets $_TARGETNAME_1\n\tif { $_SMP == 1 } {\n\tcortex_a smp off\n\t}\n\trst_run\n\thalt\n\tif { $_SMP == 1 } {\n\tcortex_a smp on\n\t}\n}\n\nproc smp_reg {} {\n\tglobal _TARGETNAME_1\n    global _TARGETNAME_2\n    targets $_TARGETNAME_1\n\techo \"$_TARGETNAME_1\"\n\tset pc1 [reg pc]\n\tset stck1 [reg sp_svc]\n\ttargets $_TARGETNAME_2\n\techo \"$_TARGETNAME_1\"\n\tset pc2 [reg pc]\n\tset stck2 [reg sp_svc]\n}\n\n\nproc u8500_tapenable {chip val} {\n\techo \"JTAG tap enable $chip\"\n}\n\n\nproc pwrsts { } {\n\tglobal _CHIPNAME\n\tirscan $_CHIPNAME.jrc 0x3a\n\tdrscan $_CHIPNAME.jrc 4 0\n\tset pwrsts [drscan $_CHIPNAME.jrc 16 0]\n\techo \"pwrsts =\"$pwrsts\n\tset a9 [expr \"0x$pwrsts & 0xc\"]\n\tset ape [expr \"0x$pwrsts & 0x3\"]\n\tif {[string equal \"0\" $ape]} {\n\t\techo \"ape off\"\n\t} else {\n\t\techo \"ape on\"\n\t}\n\techo \"$a9\"\n\tswitch $a9 {\n\t\t4 {\n\t\t\techo \"A9 in retention\"\n\t\t  }\n\t\t8 {\n\t\t\techo \"A9 100% DVFS\"\n\t\t  }\n\t\tc {\n\t\t\techo \"A9 50% DVFS\"\n\t\t}\n\t}\n}\n\nproc poll_pwrsts { } {\n\tglobal _CHIPNAME\n\tset result 1\n\tset i 0\n\tirscan $_CHIPNAME.jrc 0x3a\n\tdrscan $_CHIPNAME.jrc 4 0\n\tset pwrsts [drscan $_CHIPNAME.jrc 16 0]\n\tset pwrsts [expr \"0x$pwrsts & 0xc\"]\n\twhile {[string equal \"4\" $pwrsts] && $i<20} {\n\t\tirscan $_CHIPNAME.jrc 0x3a\n\t\tdrscan $_CHIPNAME.jrc 4 0;\n\t\tset pwrsts [drscan $_CHIPNAME.jrc 16 0]\n\t\tset pwrsts [expr \"0x$pwrsts & 0xc\"]\n\t\tif {![string equal \"4\" $pwrsts]} {\n\t\t\tset result 1\n\t\t} else {\n\t\t\tset result 0\n\t\t\tsleep 200\n\t\t\techo \"loop $i\"\n\t\t}\n\t\tincr i\n\t}\n\treturn $result\n}\n\nproc halt_ { } {\n\tif {[poll_pwrsts]==1} {\n\t\thalt\n\t} else {\n\t\techo \"halt failed : target in retention\"\n\t}\n}\n\n\nproc u8500_dapenable {chip} {\n}\n\nproc u8500_tapdisable {chip val} {\n\techo \"JTAG tap disable $chip\"\n}\n\n\nproc enable_apetap {} {\n\tglobal _CHIPNAME\n\tglobal _TARGETNAME_2\n    global _TARGETNAME_1\n\tpoll off\n\tirscan $_CHIPNAME.jrc 0x3e\n\tdrscan $_CHIPNAME.jrc 8 0xcf\n\tjtag tapenable $_CHIPNAME.dap\n\tirscan $_CHIPNAME.jrc 0x6\n\tdrscan $_CHIPNAME.jrc 32 0\n\tirscan $_CHIPNAME.jrc 0x6\n\tdrscan $_CHIPNAME.jrc 32 0\n\tset status [$_TARGETNAME_1 curstate]\n    if {[string equal \"unknown\" $status]} {\n\t$_TARGETNAME_1 arp_examine\n\tcache_config l2x 0xa0412000 8\n\t}\n\n\tset status [$_TARGETNAME_2 curstate]\n    if {[string equal \"unknown\" $status]} {\n\t$_TARGETNAME_2 arp_examine\n\t}\n\t}\n\ntcl_port 5555\ntelnet_port 4444\ngdb_port 3333\n\nif { [info exists CHIPNAME] } {\nglobal _CHIPNAME\n    set _CHIPNAME $CHIPNAME\n} else {\nglobal _CHIPNAME\n\tset _CHIPNAME u8500\n}\n\nif { [info exists ENDIAN] } {\n\tset _ENDIAN $ENDIAN\n} else {\n # this defaults to a bigendian\n\tset _ENDIAN little\n}\n\n\n\n# Subsidiary TAP: APE with scan chains for ARM Debug, EmbeddedICE-RT,\nif { [info exists CPUTAPID] } {\n   set _CPUTAPID $CPUTAPID\n} else {\n\tset _CPUTAPID 0x4ba00477\n}\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable\njtag configure $_CHIPNAME.cpu -event tap-enable \\\n\t\"u8500_dapenable $_CHIPNAME.cpu\"\njtag configure $_CHIPNAME.cpu -event tap-disable \\\n\t\"u8500_tapdisable $_CHIPNAME.cpu 0xc0\"\n\n\n#CLTAPC TAP JRC equivalent\nif { [info exists CLTAPC_ID] } {\n   set _CLTAPC_ID $CLTAPC_ID\n} else {\n   set _CLTAPC_ID 0x22286041\n}\njtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x6 -irmask 0xf -expected-id $_CLTAPC_ID -ignore-version\n\n\nif { ![info exists TARGETNAME_1] } {\nglobal _TARGETNAME_1\nset _TARGETNAME_1 $_CHIPNAME.cpu1\n} else {\nglobal _TARGETNAME_1\nset _TARGETNAME_1 $TARGETNAME_1\n}\n\nif { [info exists DAP_DBG1] } {\n\tset _DAP_DBG1 $DAP_DBG1\n} else {\n\tset _DAP_DBG1 0x801A8000\n}\nif { [info exists DAP_DBG2] } {\n\tset _DAP_DBG2 $DAP_DBG2\n} else {\n\tset _DAP_DBG2 0x801AA000\n}\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME_1 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux\n\n\nif { ![info exists TARGETNAME_2] } {\nglobal _TARGETNAME_2\nset _TARGETNAME_2 $_CHIPNAME.cpu2\n} else {\nglobal _TARGETNAME_2\nset _TARGETNAME_2 $TARGETNAME_2\n}\n\ntarget create $_TARGETNAME_2 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux\n\n\nif {![info exists SMP]} {\nglobal _SMP\nset _SMP 1\n} else {\nglobal _SMP\nset _SMP $SMP\n}\nglobal SMP\nif { $_SMP == 1} {\ntarget smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1\n}\n\n\n\n\nproc secsts1 { } {\n\tglobal _CHIPNAME\n        irscan $_CHIPNAME.jrc 0x3a\n\t\tdrscan $_CHIPNAME.jrc 4 4\n\tset secsts1 [drscan $_CHIPNAME.jrc 16 0]\n\techo \"secsts1 =\"$secsts1\n\tset secsts1 [expr \"0x$secsts1 & 0x4\"]\n\tif {![string equal \"4\" $secsts1]} {\n\techo \"APE target secured\"\n        } else {\n        echo \"APE target not secured\"\n        }\n}\n\nproc att { } {\n\tglobal _CHIPNAME\n\tjtag arp_init\n\tirscan $_CHIPNAME.jrc 0x3a\n\tdrscan $_CHIPNAME.jrc 4 4\n\tset secsts1 [drscan $_CHIPNAME.jrc 16 0]\n\techo \"secsts1 =\"$secsts1\n\tset secsts1 [expr \"0x$secsts1 & 0x4\"]\n\tif {[string equal \"4\" $secsts1]} {\n\t\tif {[poll_pwrsts]==1} {\n\t\tenable_apetap\n                } else {\n\t\techo \"target in retention\"\n\t\t}\n\t} else {\n\t\techo \"target secured\"\n\t}\n\n}\n\n\n\nproc rst_run { } {\n\tglobal _CHIPNAME\n\tglobal _TARGETNAME_2\n\tglobal _TARGETNAME_1\n\tset status [$_TARGETNAME_1 curstate]\n\tif {[string equal \"halted\" $status]} {\n\tresume\n\ttargets $_TARGETNAME_1\n\t}\n    set status [$_TARGETNAME_2 curstate]\n\tif {[string equal \"halted\" $status]} {\n\tresume\n\ttargets $_TARGETNAME_2\n\t}\n   \tpoll off\n\tjtag arp_init\n\treset\n\tsleep 20\n\tirscan $_CHIPNAME.jrc 0x3a\n\tdrscan $_CHIPNAME.jrc 4 4\n\tset secsts1 [drscan $_CHIPNAME.jrc 16 0]\n\techo \"secsts1 =\"$secsts1\n\tset secsts1 [expr \"0x$secsts1 & 0x4\"]\n\twhile {![string equal \"4\" $secsts1]} {\n\t\tirscan u8500.jrc 0x3a\n\t\tdrscan u8500.jrc 4 4\n\t\tset secsts1 [drscan $_CHIPNAME.jrc 16 0]\n\t\techo \"secsts1 =\"$secsts1\n\t\tset secsts1 [expr \"0x$secsts1 & 0x4\"]\n\t}\n\techo \"ape debugable\"\n\tenable_apetap\n\tpoll on\n\ttargets $_TARGETNAME_1\n\tdap apsel 1\n}\n\nif {![info exists MAXSPEED]} {\nglobal _MAXSPEED\nset _MAXSPEED 15000\n} else {\nglobal _MAXSPEED\nset _MAXSPEED $MAXSPEED\n}\nglobal _MAXSPEED\nadapter speed $_MAXSPEED\n\n\ngdb_breakpoint_override hard\nset mem inaccessible-by-default-off\n\njtag_ntrst_delay 100\nreset_config trst_and_srst combined\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/vd_aarch64.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# Arm v8 64b Cortex A\n\nif {![info exists _CORES]} {\n\tset _CORES 1\n}\nif {![info exists _CHIPNAME]} {\n\tset _CHIPNAME aarch64\n}\nset _TARGETNAME $_CHIPNAME.cpu\nset _CTINAME $_CHIPNAME.cti\n\nset DBGBASE {0x80810000 0x80910000}\nset CTIBASE {0x80820000 0x80920000}\n\ndap create $_CHIPNAME.dap -chain-position $_TARGETNAME\n$_CHIPNAME.dap apsel 1\n\nfor { set _core 0 } { $_core < $_CORES } { incr _core } \\\n{\n\tcti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core]\n\tset _command \"target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \\\n\t-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core\"\n\tif { $_core != 0 } {\n\t\t# non-boot core examination may fail\n\t\tset _command \"$_command -defer-examine\"\n\t\tset _smp_command \"$_smp_command $_TARGETNAME.$_core\"\n\t} else {\n\t\tset _smp_command \"target smp $_TARGETNAME.$_core\"\n\t}\n\teval $_command\n}\neval $_smp_command\n\n# default target is core 0\ntargets $_TARGETNAME.0\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/vd_cortex_m.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# ARM Cortex M\n\nif {![info exists _CHIPNAME]} {\n\tset _CHIPNAME cortex_m\n}\nset _TARGETNAME $_CHIPNAME.cpu\n\ndap create $_CHIPNAME.dap -chain-position $_TARGETNAME\n\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/vd_riscv.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Cadence virtual debug interface\n# RISCV core\n\nif {![info exists _HARTID]} {\n\tset _HARTID 0x00\n}\nif {![info exists _CHIPNAME]} {\n\tset _CHIPNAME riscv\n}\nset _TARGETNAME $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID\n\nriscv set_reset_timeout_sec 120\nriscv set_command_timeout_sec 120\nriscv set_mem_access sysbus progbuf\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/vybrid_vf6xx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Freescale Vybrid VF610\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME vf610\n}\n\nif { [info exists A5_JTAG_TAPID] } {\n\tset _A5_JTAG_TAPID $A5_JTAG_TAPID\n} else {\n\tset _A5_JTAG_TAPID 0x4BA00477\n}\n\nif { [info exists A5_SWD_TAPID] } {\n\tset _A5_SWD_TAPID $A5_SWD_TAPID\n} else {\n\tset _A5_SWD_TAPID 0x3BA02477\n}\n\nif { [using_jtag] } {\n\tset _A5_TAPID $_A5_JTAG_TAPID\n} else {\n\tset _A5_TAPID $_A5_SWD_TAPID\n}\n\nsource [find target/swj-dp.tcl]\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000\ntarget create ${_TARGETNAME}1 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine\nadapter speed 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xilinx_zynqmp.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# target configuration for\n# Xilinx ZynqMP (UltraScale+ / A53)\n#\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME uscale\n}\n\n#\n# DAP tap (Quard core A53)\n#\nif { [info exists DAP_TAPID] } {\n    set _DAP_TAPID $DAP_TAPID\n} else {\n    set _DAP_TAPID 0x5ba00477\n}\n\njtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap\n\n#\n# PS tap (UltraScale+)\n#\nif { [info exists PS_TAPID] } {\n    set _PS_TAPID $PS_TAPID\n    jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID\n} else {\n    # FPGA Programmable logic. Values take from Table 39-1 in UG1085:\n    jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -ignore-version \\\n        -expected-id 0x04711093 \\\n        -expected-id 0x04710093 \\\n        -expected-id 0x04721093 \\\n        -expected-id 0x04720093 \\\n        -expected-id 0x04739093 \\\n        -expected-id 0x04730093 \\\n        -expected-id 0x04738093 \\\n        -expected-id 0x04740093 \\\n        -expected-id 0x04750093 \\\n        -expected-id 0x04759093 \\\n        -expected-id 0x04758093\n}\n\nset jtag_configured 0\n\njtag configure $_CHIPNAME.ps -event setup {\n    global _CHIPNAME\n    global jtag_configured\n\n    if { $jtag_configured == 0 } {\n        # add the DAP tap to the chain\n        # See https://forums.xilinx.com/t5/UltraScale-Architecture/JTAG-Chain-Configuration-for-Zynq-UltraScale-MPSoC/td-p/758924\n        irscan $_CHIPNAME.ps 0x824\n        drscan $_CHIPNAME.ps 32 0x00000003\n        runtest 100\n\n        # setup event will be re-entered through jtag arp_init\n        # break the recursion\n        set jtag_configured 1\n        # re-initialized the jtag chain\n        jtag arp_init\n    }\n}\n\nset _TARGETNAME $_CHIPNAME.a53\nset _CTINAME $_CHIPNAME.cti\nset _smp_command \"\"\n\nset DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}\nset CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}\nset _cores 4\n\nfor { set _core 0 } { $_core < $_cores } { incr _core } {\n\n    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \\\n        -baseaddr [lindex $CTIBASE $_core]\n\n    set _command \"target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \\\n        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core\"\n\n    if { $_core != 0 } {\n        # non-boot core examination may fail\n        set _command \"$_command -defer-examine\"\n        set _smp_command \"$_smp_command $_TARGETNAME.$_core\"\n    } else {\n        set _command \"$_command -rtos hwthread\"\n        set _smp_command \"target smp $_TARGETNAME.$_core\"\n    }\n\n    eval $_command\n}\n\ntarget create uscale.axi mem_ap -dap uscale.dap -ap-num 0\n\neval $_smp_command\ntargets $_TARGETNAME.0\n\nproc core_up { args } {\n    global _TARGETNAME\n    foreach core $args {\n        $_TARGETNAME.$core arp_examine\n    }\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xmc1xxx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC1100/XMC1200/XMC1300 family (ARM Cortex-M0 @ 32 MHz)\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xmc1000\n}\n\n#\n# Only SWD and SPD supported\n#\nsource [find target/swj-dp.tcl]\n\nif { [info exists CPUTAPID] } {\n\tset _CPU_SWD_TAPID $CPUTAPID\n} else {\n\tset _CPU_SWD_TAPID 0x0BB11477\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap\n\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x4000\n}\n\n$_TARGETNAME configure -work-area-phys 0x20000000 \\\n                       -work-area-size $_WORKAREASIZE \\\n                       -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME\n\nadapter speed 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xmc4xxx.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Infineon XMC4100/XMC4200/XMC4400/XMC4500 family (ARM Cortex-M4 @ 80-120 MHz)\n#\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xmc4000\n}\n\nsource [find target/swj-dp.tcl]\n\n#\n# SWJ-DP\n#\nif { [info exists CPU_JTAG_TAPID] } {\n\tset _CPU_JTAG_TAPID $CPU_JTAG_TAPID\n} else {\n\tset _CPU_JTAG_TAPID 0x4BA00477\n}\n\n#\n# SW_DP\n#\nif { [info exists CPU_SWD_TAPID] } {\n\tset _CPU_SWD_TAPID $CPU_SWD_TAPID\n} else {\n\tset _CPU_SWD_TAPID 0x2BA01477\n}\n\nif { [using_jtag] } {\n\tset _CPU_TAPID $_CPU_JTAG_TAPID\n} else {\n\tset _CPU_TAPID $_CPU_SWD_TAPID\n}\n\nswj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\nset _TARGETNAME $_CHIPNAME.cpu\ntarget create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap\n\n# Work-area is a space in RAM used for flash programming\n# By default use 16 kB\nif { [info exists WORKAREASIZE] } {\n   set _WORKAREASIZE $WORKAREASIZE\n} else {\n   set _WORKAREASIZE 0x1000\n}\n\n$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME xmc4xxx 0x0C000000 0 0 0 $_TARGETNAME\n\nif { ![using_hla] } {\n\tcortex_m reset_config sysresetreq\n}\n\nadapter speed 1000\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xmos_xs1-xau8a-10_arm.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# XMOS xCORE-XA XS1-XAU8A-10: ARM Cortex-M3 @ 48 MHz\n#\n# http://www.xmos.com/products/silicon/xcore-xa/xa-series\n#\n\nif { ![info exists CHIPNAME] } {\n\tset CHIPNAME xcorexa\n}\n\nif { ![info exists WORKAREASIZE] } {\n\t# XS1-XAU8A-10-FB265: 128 KB SRAM\n\tset WORKAREASIZE 0x20000\n}\n\nsource [find target/efm32.cfg]\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xtensa-core-esp32.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# OpenOCD configuration file for Xtensa ESP32 target\n\n#  Core definition and ABI\nxtensa xtdef\tLX\nxtensa xtopt\tarnum\t\t\t\t64\nxtensa xtopt\twindowed\t\t\t1\n\n#  Exception/Interrupt Options\nxtensa xtopt\texceptions\t\t\t1\nxtensa xtopt\thipriints\t\t\t1\nxtensa xtopt\tintlevels\t\t\t6\nxtensa xtopt\texcmlevel\t\t\t3\n\n#  Cache Options\nxtensa xtmem\ticache\t\t\t\t4 0 1\nxtensa xtmem\tdcache\t\t\t\t4 0 1 0\n\n#  Memory Options\nxtensa xtmem\tirom\t\t\t\t0x400D0000\t0x330000\nxtensa xtmem\tirom\t\t\t\t0x40000000\t0x64F00\nxtensa xtmem\tiram\t\t\t\t0x40070000\t0x30000\nxtensa xtmem\tiram\t\t\t\t0x400C0000\t0x2000\nxtensa xtmem\tdrom\t\t\t\t0x3F400000\t0x800000\nxtensa xtmem\tdrom\t\t\t\t0x3FF90000\t0x10000\nxtensa xtmem\tdram\t\t\t\t0x3FFAE000\t0x52000\nxtensa xtmem\tdram\t\t\t\t0x3FF80000\t0x2000\nxtensa xtmem\tdram\t\t\t\t0x3F800000\t0x400000\nxtensa xtmem\tdram\t\t\t\t0x50000000\t0x2000\nxtensa xtmem\tdram\t\t\t\t0x3FF00000\t0x71000\nxtensa xtmem\tdram\t\t\t\t0x60000000\t0x20000000\n\n#  Memory Protection/Translation Options\n\n#  Debug Options\nxtensa xtopt\tdebuglevel\t\t\t6\nxtensa xtopt\tibreaknum\t\t\t2\nxtensa xtopt\tdbreaknum\t\t\t2\nxtensa xtopt\ttracemem\t\t\t0x4000\nxtensa xtopt\ttracememrev\t\t\t1\nxtensa xtopt\tperfcount\t\t\t2\n\n#  Core Registers\n#  xtregfmt:\tOptionally specify \"contiguous\" vs. \"sparse\" GDB register map.\n#\t\t\t\tDefault setting is \"sparse\" and is used with xt-gdb.\n#\t\t\t\tIf contiguous, optional parameter specifies number of registers\n#\t\t\t\tin \"Read General Registers\" (g-packet) requests.\n#\t\t\t\tNOTE: For contiguous format, registers listed in GDB order.\n#  xtregs:\t\tTotal number of Xtensa registers in the system\nxtensa xtregs\t173\nxtensa xtregfmt\tcontiguous\t\t\t105\nxtensa xtreg\tpc\t\t\t\t\t0x0020\nxtensa xtreg\tar0\t\t\t\t\t0x0100\nxtensa xtreg\tar1\t\t\t\t\t0x0101\nxtensa xtreg\tar2\t\t\t\t\t0x0102\nxtensa xtreg\tar3\t\t\t\t\t0x0103\nxtensa xtreg\tar4\t\t\t\t\t0x0104\nxtensa xtreg\tar5\t\t\t\t\t0x0105\nxtensa xtreg\tar6\t\t\t\t\t0x0106\nxtensa xtreg\tar7\t\t\t\t\t0x0107\nxtensa xtreg\tar8\t\t\t\t\t0x0108\nxtensa xtreg\tar9\t\t\t\t\t0x0109\nxtensa xtreg\tar10\t\t\t\t0x010a\nxtensa xtreg\tar11\t\t\t\t0x010b\nxtensa xtreg\tar12\t\t\t\t0x010c\nxtensa xtreg\tar13\t\t\t\t0x010d\nxtensa xtreg\tar14\t\t\t\t0x010e\nxtensa xtreg\tar15\t\t\t\t0x010f\nxtensa xtreg\tar16\t\t\t\t0x0110\nxtensa xtreg\tar17\t\t\t\t0x0111\nxtensa xtreg\tar18\t\t\t\t0x0112\nxtensa xtreg\tar19\t\t\t\t0x0113\nxtensa xtreg\tar20\t\t\t\t0x0114\nxtensa xtreg\tar21\t\t\t\t0x0115\nxtensa xtreg\tar22\t\t\t\t0x0116\nxtensa xtreg\tar23\t\t\t\t0x0117\nxtensa xtreg\tar24\t\t\t\t0x0118\nxtensa xtreg\tar25\t\t\t\t0x0119\nxtensa xtreg\tar26\t\t\t\t0x011a\nxtensa xtreg\tar27\t\t\t\t0x011b\nxtensa xtreg\tar28\t\t\t\t0x011c\nxtensa xtreg\tar29\t\t\t\t0x011d\nxtensa xtreg\tar30\t\t\t\t0x011e\nxtensa xtreg\tar31\t\t\t\t0x011f\nxtensa xtreg\tar32\t\t\t\t0x0120\nxtensa xtreg\tar33\t\t\t\t0x0121\nxtensa xtreg\tar34\t\t\t\t0x0122\nxtensa xtreg\tar35\t\t\t\t0x0123\nxtensa xtreg\tar36\t\t\t\t0x0124\nxtensa xtreg\tar37\t\t\t\t0x0125\nxtensa xtreg\tar38\t\t\t\t0x0126\nxtensa xtreg\tar39\t\t\t\t0x0127\nxtensa xtreg\tar40\t\t\t\t0x0128\nxtensa xtreg\tar41\t\t\t\t0x0129\nxtensa xtreg\tar42\t\t\t\t0x012a\nxtensa xtreg\tar43\t\t\t\t0x012b\nxtensa xtreg\tar44\t\t\t\t0x012c\nxtensa xtreg\tar45\t\t\t\t0x012d\nxtensa xtreg\tar46\t\t\t\t0x012e\nxtensa xtreg\tar47\t\t\t\t0x012f\nxtensa xtreg\tar48\t\t\t\t0x0130\nxtensa xtreg\tar49\t\t\t\t0x0131\nxtensa xtreg\tar50\t\t\t\t0x0132\nxtensa xtreg\tar51\t\t\t\t0x0133\nxtensa xtreg\tar52\t\t\t\t0x0134\nxtensa xtreg\tar53\t\t\t\t0x0135\nxtensa xtreg\tar54\t\t\t\t0x0136\nxtensa xtreg\tar55\t\t\t\t0x0137\nxtensa xtreg\tar56\t\t\t\t0x0138\nxtensa xtreg\tar57\t\t\t\t0x0139\nxtensa xtreg\tar58\t\t\t\t0x013a\nxtensa xtreg\tar59\t\t\t\t0x013b\nxtensa xtreg\tar60\t\t\t\t0x013c\nxtensa xtreg\tar61\t\t\t\t0x013d\nxtensa xtreg\tar62\t\t\t\t0x013e\nxtensa xtreg\tar63\t\t\t\t0x013f\nxtensa xtreg\tlbeg\t\t\t\t0x0200\nxtensa xtreg\tlend\t\t\t\t0x0201\nxtensa xtreg\tlcount\t\t\t\t0x0202\nxtensa xtreg\tsar\t\t\t\t\t0x0203\nxtensa xtreg\twindowbase\t\t\t0x0248\nxtensa xtreg\twindowstart\t\t\t0x0249\nxtensa xtreg\tconfigid0\t\t\t0x02b0\nxtensa xtreg\tconfigid1\t\t\t0x02d0\nxtensa xtreg\tps\t\t\t\t\t0x02e6\nxtensa xtreg\tthreadptr\t\t\t0x03e7\nxtensa xtreg\tbr\t\t\t\t\t0x0204\nxtensa xtreg\tscompare1\t\t\t0x020c\nxtensa xtreg\tacclo\t\t\t\t0x0210\nxtensa xtreg\tacchi\t\t\t\t0x0211\nxtensa xtreg\tm0\t\t\t\t\t0x0220\nxtensa xtreg\tm1\t\t\t\t\t0x0221\nxtensa xtreg\tm2\t\t\t\t\t0x0222\nxtensa xtreg\tm3\t\t\t\t\t0x0223\nxtensa xtreg\texpstate\t\t\t0x03e6\nxtensa xtreg\tf64r_lo\t\t\t\t0x03ea\nxtensa xtreg\tf64r_hi\t\t\t\t0x03eb\nxtensa xtreg\tf64s\t\t\t\t0x03ec\nxtensa xtreg\tf0\t\t\t\t\t0x0030\nxtensa xtreg\tf1\t\t\t\t\t0x0031\nxtensa xtreg\tf2\t\t\t\t\t0x0032\nxtensa xtreg\tf3\t\t\t\t\t0x0033\nxtensa xtreg\tf4\t\t\t\t\t0x0034\nxtensa xtreg\tf5\t\t\t\t\t0x0035\nxtensa xtreg\tf6\t\t\t\t\t0x0036\nxtensa xtreg\tf7\t\t\t\t\t0x0037\nxtensa xtreg\tf8\t\t\t\t\t0x0038\nxtensa xtreg\tf9\t\t\t\t\t0x0039\nxtensa xtreg\tf10\t\t\t\t\t0x003a\nxtensa xtreg\tf11\t\t\t\t\t0x003b\nxtensa xtreg\tf12\t\t\t\t\t0x003c\nxtensa xtreg\tf13\t\t\t\t\t0x003d\nxtensa xtreg\tf14\t\t\t\t\t0x003e\nxtensa xtreg\tf15\t\t\t\t\t0x003f\nxtensa xtreg\tfcr\t\t\t\t\t0x03e8\nxtensa xtreg\tfsr\t\t\t\t\t0x03e9\nxtensa xtreg\tmmid\t\t\t\t0x0259\nxtensa xtreg\tibreakenable\t\t0x0260\nxtensa xtreg\tmemctl\t\t\t\t0x0261\nxtensa xtreg\tatomctl\t\t\t\t0x0263\nxtensa xtreg\tddr\t\t\t\t\t0x0268\nxtensa xtreg\tibreaka0\t\t\t0x0280\nxtensa xtreg\tibreaka1\t\t\t0x0281\nxtensa xtreg\tdbreaka0\t\t\t0x0290\nxtensa xtreg\tdbreaka1\t\t\t0x0291\nxtensa xtreg\tdbreakc0\t\t\t0x02a0\nxtensa xtreg\tdbreakc1\t\t\t0x02a1\nxtensa xtreg\tepc1\t\t\t\t0x02b1\nxtensa xtreg\tepc2\t\t\t\t0x02b2\nxtensa xtreg\tepc3\t\t\t\t0x02b3\nxtensa xtreg\tepc4\t\t\t\t0x02b4\nxtensa xtreg\tepc5\t\t\t\t0x02b5\nxtensa xtreg\tepc6\t\t\t\t0x02b6\nxtensa xtreg\tepc7\t\t\t\t0x02b7\nxtensa xtreg\tdepc\t\t\t\t0x02c0\nxtensa xtreg\teps2\t\t\t\t0x02c2\nxtensa xtreg\teps3\t\t\t\t0x02c3\nxtensa xtreg\teps4\t\t\t\t0x02c4\nxtensa xtreg\teps5\t\t\t\t0x02c5\nxtensa xtreg\teps6\t\t\t\t0x02c6\nxtensa xtreg\teps7\t\t\t\t0x02c7\nxtensa xtreg\texcsave1\t\t\t0x02d1\nxtensa xtreg\texcsave2\t\t\t0x02d2\nxtensa xtreg\texcsave3\t\t\t0x02d3\nxtensa xtreg\texcsave4\t\t\t0x02d4\nxtensa xtreg\texcsave5\t\t\t0x02d5\nxtensa xtreg\texcsave6\t\t\t0x02d6\nxtensa xtreg\texcsave7\t\t\t0x02d7\nxtensa xtreg\tcpenable\t\t\t0x02e0\nxtensa xtreg\tinterrupt\t\t\t0x02e2\nxtensa xtreg\tintset\t\t\t\t0x02e2\nxtensa xtreg\tintclear\t\t\t0x02e3\nxtensa xtreg\tintenable\t\t\t0x02e4\nxtensa xtreg\tvecbase\t\t\t\t0x02e7\nxtensa xtreg\texccause\t\t\t0x02e8\nxtensa xtreg\tdebugcause\t\t\t0x02e9\nxtensa xtreg\tccount\t\t\t\t0x02ea\nxtensa xtreg\tprid\t\t\t\t0x02eb\nxtensa xtreg\ticount\t\t\t\t0x02ec\nxtensa xtreg\ticountlevel\t\t\t0x02ed\nxtensa xtreg\texcvaddr\t\t\t0x02ee\nxtensa xtreg\tccompare0\t\t\t0x02f0\nxtensa xtreg\tccompare1\t\t\t0x02f1\nxtensa xtreg\tccompare2\t\t\t0x02f2\nxtensa xtreg\tmisc0\t\t\t\t0x02f4\nxtensa xtreg\tmisc1\t\t\t\t0x02f5\nxtensa xtreg\tmisc2\t\t\t\t0x02f6\nxtensa xtreg\tmisc3\t\t\t\t0x02f7\nxtensa xtreg\ta0\t\t\t\t\t0x0000\nxtensa xtreg\ta1\t\t\t\t\t0x0001\nxtensa xtreg\ta2\t\t\t\t\t0x0002\nxtensa xtreg\ta3\t\t\t\t\t0x0003\nxtensa xtreg\ta4\t\t\t\t\t0x0004\nxtensa xtreg\ta5\t\t\t\t\t0x0005\nxtensa xtreg\ta6\t\t\t\t\t0x0006\nxtensa xtreg\ta7\t\t\t\t\t0x0007\nxtensa xtreg\ta8\t\t\t\t\t0x0008\nxtensa xtreg\ta9\t\t\t\t\t0x0009\nxtensa xtreg\ta10\t\t\t\t\t0x000a\nxtensa xtreg\ta11\t\t\t\t\t0x000b\nxtensa xtreg\ta12\t\t\t\t\t0x000c\nxtensa xtreg\ta13\t\t\t\t\t0x000d\nxtensa xtreg\ta14\t\t\t\t\t0x000e\nxtensa xtreg\ta15\t\t\t\t\t0x000f\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xtensa-core-esp32s2.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# OpenOCD configuration file for Xtensa ESP32S2 target\n\n#  Core definition and ABI\nxtensa xtdef\tLX\nxtensa xtopt\tarnum\t\t\t\t64\nxtensa xtopt\twindowed\t\t\t1\n\n#  Exception/Interrupt Options\nxtensa xtopt\texceptions\t\t\t1\nxtensa xtopt\thipriints\t\t\t1\nxtensa xtopt\tintlevels\t\t\t6\nxtensa xtopt\texcmlevel\t\t\t3\n\n#  Cache Options\nxtensa xtmem\ticache\t\t\t\t4 0 1\nxtensa xtmem\tdcache\t\t\t\t4 0 1 0\n\n#  Memory Options\nxtensa xtmem\tirom\t\t\t\t0x40080000\t0x780000\nxtensa xtmem\tirom\t\t\t\t0x40000000\t0x20000\nxtensa xtmem\tiram\t\t\t\t0x40020000\t0x50000\nxtensa xtmem\tiram\t\t\t\t0x40070000\t0x2000\nxtensa xtmem\tdrom\t\t\t\t0x3F000000\t0x400000\nxtensa xtmem\tdrom\t\t\t\t0x3F4D3FFC\t0xAAC004\nxtensa xtmem\tdrom\t\t\t\t0x3FFA0000\t0x10000\nxtensa xtmem\tdram\t\t\t\t0x3FFB0000\t0x50000\nxtensa xtmem\tdram\t\t\t\t0x3FF9E000\t0x2000\nxtensa xtmem\tdram\t\t\t\t0x50000000\t0x2000\nxtensa xtmem\tdram\t\t\t\t0x3F500000\t0xA80000\nxtensa xtmem\tdram\t\t\t\t0x3F400000\t0xD3FFC\nxtensa xtmem\tdram\t\t\t\t0x60000000\t0x20000000\n\n#  Memory Protection/Translation Options\n\n#  Debug Options\nxtensa xtopt\tdebuglevel\t\t\t6\nxtensa xtopt\tibreaknum\t\t\t2\nxtensa xtopt\tdbreaknum\t\t\t2\nxtensa xtopt\ttracemem\t\t\t0x4000\nxtensa xtopt\ttracememrev\t\t\t0\nxtensa xtopt\tperfcount\t\t\t2\n\n#  Core Registers\n#  xtregfmt:\tOptionally specify \"contiguous\" vs. \"sparse\" GDB register map.\n#\t\t\t\tDefault setting is \"sparse\" and is used with xt-gdb.\n#\t\t\t\tIf contiguous, optional parameter specifies number of registers\n#\t\t\t\tin \"Read General Registers\" (g-packet) requests.\n#\t\t\t\tNOTE: For contiguous format, registers listed in GDB order.\n#  xtregs:\t\tTotal number of Xtensa registers in the system\nxtensa xtregs\t171\nxtensa xtregfmt\tcontiguous\t\t\t73\nxtensa xtreg\tpc\t\t\t\t\t0x0020\nxtensa xtreg\tar0\t\t\t\t\t0x0100\nxtensa xtreg\tar1\t\t\t\t\t0x0101\nxtensa xtreg\tar2\t\t\t\t\t0x0102\nxtensa xtreg\tar3\t\t\t\t\t0x0103\nxtensa xtreg\tar4\t\t\t\t\t0x0104\nxtensa xtreg\tar5\t\t\t\t\t0x0105\nxtensa xtreg\tar6\t\t\t\t\t0x0106\nxtensa xtreg\tar7\t\t\t\t\t0x0107\nxtensa xtreg\tar8\t\t\t\t\t0x0108\nxtensa xtreg\tar9\t\t\t\t\t0x0109\nxtensa xtreg\tar10\t\t\t\t0x010a\nxtensa xtreg\tar11\t\t\t\t0x010b\nxtensa xtreg\tar12\t\t\t\t0x010c\nxtensa xtreg\tar13\t\t\t\t0x010d\nxtensa xtreg\tar14\t\t\t\t0x010e\nxtensa xtreg\tar15\t\t\t\t0x010f\nxtensa xtreg\tar16\t\t\t\t0x0110\nxtensa xtreg\tar17\t\t\t\t0x0111\nxtensa xtreg\tar18\t\t\t\t0x0112\nxtensa xtreg\tar19\t\t\t\t0x0113\nxtensa xtreg\tar20\t\t\t\t0x0114\nxtensa xtreg\tar21\t\t\t\t0x0115\nxtensa xtreg\tar22\t\t\t\t0x0116\nxtensa xtreg\tar23\t\t\t\t0x0117\nxtensa xtreg\tar24\t\t\t\t0x0118\nxtensa xtreg\tar25\t\t\t\t0x0119\nxtensa xtreg\tar26\t\t\t\t0x011a\nxtensa xtreg\tar27\t\t\t\t0x011b\nxtensa xtreg\tar28\t\t\t\t0x011c\nxtensa xtreg\tar29\t\t\t\t0x011d\nxtensa xtreg\tar30\t\t\t\t0x011e\nxtensa xtreg\tar31\t\t\t\t0x011f\nxtensa xtreg\tar32\t\t\t\t0x0120\nxtensa xtreg\tar33\t\t\t\t0x0121\nxtensa xtreg\tar34\t\t\t\t0x0122\nxtensa xtreg\tar35\t\t\t\t0x0123\nxtensa xtreg\tar36\t\t\t\t0x0124\nxtensa xtreg\tar37\t\t\t\t0x0125\nxtensa xtreg\tar38\t\t\t\t0x0126\nxtensa xtreg\tar39\t\t\t\t0x0127\nxtensa xtreg\tar40\t\t\t\t0x0128\nxtensa xtreg\tar41\t\t\t\t0x0129\nxtensa xtreg\tar42\t\t\t\t0x012a\nxtensa xtreg\tar43\t\t\t\t0x012b\nxtensa xtreg\tar44\t\t\t\t0x012c\nxtensa xtreg\tar45\t\t\t\t0x012d\nxtensa xtreg\tar46\t\t\t\t0x012e\nxtensa xtreg\tar47\t\t\t\t0x012f\nxtensa xtreg\tar48\t\t\t\t0x0130\nxtensa xtreg\tar49\t\t\t\t0x0131\nxtensa xtreg\tar50\t\t\t\t0x0132\nxtensa xtreg\tar51\t\t\t\t0x0133\nxtensa xtreg\tar52\t\t\t\t0x0134\nxtensa xtreg\tar53\t\t\t\t0x0135\nxtensa xtreg\tar54\t\t\t\t0x0136\nxtensa xtreg\tar55\t\t\t\t0x0137\nxtensa xtreg\tar56\t\t\t\t0x0138\nxtensa xtreg\tar57\t\t\t\t0x0139\nxtensa xtreg\tar58\t\t\t\t0x013a\nxtensa xtreg\tar59\t\t\t\t0x013b\nxtensa xtreg\tar60\t\t\t\t0x013c\nxtensa xtreg\tar61\t\t\t\t0x013d\nxtensa xtreg\tar62\t\t\t\t0x013e\nxtensa xtreg\tar63\t\t\t\t0x013f\nxtensa xtreg\tsar\t\t\t\t\t0x0203\nxtensa xtreg\twindowbase\t\t\t0x0248\nxtensa xtreg\twindowstart\t\t\t0x0249\nxtensa xtreg\tconfigid0\t\t\t0x02b0\nxtensa xtreg\tconfigid1\t\t\t0x02d0\nxtensa xtreg\tps\t\t\t\t\t0x02e6\nxtensa xtreg\tthreadptr\t\t\t0x03e7\nxtensa xtreg\tgpio_out\t\t\t0x0300\nxtensa xtreg\tmmid\t\t\t\t0x0259\nxtensa xtreg\tibreakenable\t\t0x0260\nxtensa xtreg\tddr\t\t\t\t\t0x0268\nxtensa xtreg\tibreaka0\t\t\t0x0280\nxtensa xtreg\tibreaka1\t\t\t0x0281\nxtensa xtreg\tdbreaka0\t\t\t0x0290\nxtensa xtreg\tdbreaka1\t\t\t0x0291\nxtensa xtreg\tdbreakc0\t\t\t0x02a0\nxtensa xtreg\tdbreakc1\t\t\t0x02a1\nxtensa xtreg\tepc1\t\t\t\t0x02b1\nxtensa xtreg\tepc2\t\t\t\t0x02b2\nxtensa xtreg\tepc3\t\t\t\t0x02b3\nxtensa xtreg\tepc4\t\t\t\t0x02b4\nxtensa xtreg\tepc5\t\t\t\t0x02b5\nxtensa xtreg\tepc6\t\t\t\t0x02b6\nxtensa xtreg\tepc7\t\t\t\t0x02b7\nxtensa xtreg\tdepc\t\t\t\t0x02c0\nxtensa xtreg\teps2\t\t\t\t0x02c2\nxtensa xtreg\teps3\t\t\t\t0x02c3\nxtensa xtreg\teps4\t\t\t\t0x02c4\nxtensa xtreg\teps5\t\t\t\t0x02c5\nxtensa xtreg\teps6\t\t\t\t0x02c6\nxtensa xtreg\teps7\t\t\t\t0x02c7\nxtensa xtreg\texcsave1\t\t\t0x02d1\nxtensa xtreg\texcsave2\t\t\t0x02d2\nxtensa xtreg\texcsave3\t\t\t0x02d3\nxtensa xtreg\texcsave4\t\t\t0x02d4\nxtensa xtreg\texcsave5\t\t\t0x02d5\nxtensa xtreg\texcsave6\t\t\t0x02d6\nxtensa xtreg\texcsave7\t\t\t0x02d7\nxtensa xtreg\tcpenable\t\t\t0x02e0\nxtensa xtreg\tinterrupt\t\t\t0x02e2\nxtensa xtreg\tintset\t\t\t\t0x02e2\nxtensa xtreg\tintclear\t\t\t0x02e3\nxtensa xtreg\tintenable\t\t\t0x02e4\nxtensa xtreg\tvecbase\t\t\t\t0x02e7\nxtensa xtreg\texccause\t\t\t0x02e8\nxtensa xtreg\tdebugcause\t\t\t0x02e9\nxtensa xtreg\tccount\t\t\t\t0x02ea\nxtensa xtreg\tprid\t\t\t\t0x02eb\nxtensa xtreg\ticount\t\t\t\t0x02ec\nxtensa xtreg\ticountlevel\t\t\t0x02ed\nxtensa xtreg\texcvaddr\t\t\t0x02ee\nxtensa xtreg\tccompare0\t\t\t0x02f0\nxtensa xtreg\tccompare1\t\t\t0x02f1\nxtensa xtreg\tccompare2\t\t\t0x02f2\nxtensa xtreg\tmisc0\t\t\t\t0x02f4\nxtensa xtreg\tmisc1\t\t\t\t0x02f5\nxtensa xtreg\tmisc2\t\t\t\t0x02f6\nxtensa xtreg\tmisc3\t\t\t\t0x02f7\nxtensa xtreg\tpwrctl\t\t\t\t0x2014\nxtensa xtreg\tpwrstat\t\t\t\t0x2015\nxtensa xtreg\teristat\t\t\t\t0x2016\nxtensa xtreg\tcs_itctrl\t\t\t0x2017\nxtensa xtreg\tcs_claimset\t\t\t0x2018\nxtensa xtreg\tcs_claimclr\t\t\t0x2019\nxtensa xtreg\tcs_lockaccess\t\t0x201a\nxtensa xtreg\tcs_lockstatus\t\t0x201b\nxtensa xtreg\tcs_authstatus\t\t0x201c\nxtensa xtreg\tfault_info\t\t\t0x202b\nxtensa xtreg\ttrax_id\t\t\t\t0x202c\nxtensa xtreg\ttrax_control\t\t0x202d\nxtensa xtreg\ttrax_status\t\t\t0x202e\nxtensa xtreg\ttrax_data\t\t\t0x202f\nxtensa xtreg\ttrax_address\t\t0x2030\nxtensa xtreg\ttrax_pctrigger\t\t0x2031\nxtensa xtreg\ttrax_pcmatch\t\t0x2032\nxtensa xtreg\ttrax_delay\t\t\t0x2033\nxtensa xtreg\ttrax_memstart\t\t0x2034\nxtensa xtreg\ttrax_memend\t\t\t0x2035\nxtensa xtreg\tpmg\t\t\t\t\t0x2043\nxtensa xtreg\tpmpc\t\t\t\t0x2044\nxtensa xtreg\tpm0\t\t\t\t\t0x2045\nxtensa xtreg\tpm1\t\t\t\t\t0x2046\nxtensa xtreg\tpmctrl0\t\t\t\t0x2047\nxtensa xtreg\tpmctrl1\t\t\t\t0x2048\nxtensa xtreg\tpmstat0\t\t\t\t0x2049\nxtensa xtreg\tpmstat1\t\t\t\t0x204a\nxtensa xtreg\tocdid\t\t\t\t0x204b\nxtensa xtreg\tocd_dcrclr\t\t\t0x204c\nxtensa xtreg\tocd_dcrset\t\t\t0x204d\nxtensa xtreg\tocd_dsr\t\t\t\t0x204e\nxtensa xtreg\ta0\t\t\t\t\t0x0000\nxtensa xtreg\ta1\t\t\t\t\t0x0001\nxtensa xtreg\ta2\t\t\t\t\t0x0002\nxtensa xtreg\ta3\t\t\t\t\t0x0003\nxtensa xtreg\ta4\t\t\t\t\t0x0004\nxtensa xtreg\ta5\t\t\t\t\t0x0005\nxtensa xtreg\ta6\t\t\t\t\t0x0006\nxtensa xtreg\ta7\t\t\t\t\t0x0007\nxtensa xtreg\ta8\t\t\t\t\t0x0008\nxtensa xtreg\ta9\t\t\t\t\t0x0009\nxtensa xtreg\ta10\t\t\t\t\t0x000a\nxtensa xtreg\ta11\t\t\t\t\t0x000b\nxtensa xtreg\ta12\t\t\t\t\t0x000c\nxtensa xtreg\ta13\t\t\t\t\t0x000d\nxtensa xtreg\ta14\t\t\t\t\t0x000e\nxtensa xtreg\ta15\t\t\t\t\t0x000f\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xtensa-core-esp32s3.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# OpenOCD configuration file for Xtensa ESP32S3 target\n\n#  Core definition and ABI\nxtensa xtdef\tLX\nxtensa xtopt\tarnum\t\t\t\t64\nxtensa xtopt\twindowed\t\t\t1\n\n#  Exception/Interrupt Options\nxtensa xtopt\texceptions\t\t\t1\nxtensa xtopt\thipriints\t\t\t1\nxtensa xtopt\tintlevels\t\t\t6\nxtensa xtopt\texcmlevel\t\t\t3\n\n#  Cache Options\n\n#  Memory Options\nxtensa xtmem\tirom\t\t\t\t0x42000000\t0x2000000\nxtensa xtmem\tirom\t\t\t\t0x40000000\t0x60000\nxtensa xtmem\tiram\t\t\t\t0x40370000\t0x70000\nxtensa xtmem\tiram\t\t\t\t0x600FE000\t0x2000\nxtensa xtmem\tdrom\t\t\t\t0x3C000000\t0x1000000\nxtensa xtmem\tdrom\t\t\t\t0x3FF00000\t0x20000\nxtensa xtmem\tdram\t\t\t\t0x3FC88000\t0x78000\nxtensa xtmem\tdram\t\t\t\t0x600FE000\t0x2000\nxtensa xtmem\tdram\t\t\t\t0x50000000\t0x2000\nxtensa xtmem\tdram\t\t\t\t0x60000000\t0x10000000\n\n#  Memory Protection/Translation Options\n\n#  Debug Options\nxtensa xtopt\tdebuglevel\t\t\t6\nxtensa xtopt\tibreaknum\t\t\t2\nxtensa xtopt\tdbreaknum\t\t\t2\nxtensa xtopt\ttracemem\t\t\t0x4000\nxtensa xtopt\ttracememrev\t\t\t0\nxtensa xtopt\tperfcount\t\t\t2\n\n\n#  Core Registers\n#  xtregfmt:\tOptionally specify \"contiguous\" vs. \"sparse\" GDB register map.\n#\t\t\t\tDefault setting is \"sparse\" and is used with xt-gdb.\n#\t\t\t\tIf contiguous, optional parameter specifies number of registers\n#\t\t\t\tin \"Read General Registers\" (g-packet) requests.\n#\t\t\t\tNOTE: For contiguous format, registers listed in GDB order.\n#  xtregs:\t\tTotal number of Xtensa registers in the system\nxtensa xtregs\t228\nxtensa xtregfmt\tcontiguous\t\t\t128\nxtensa xtreg\tpc\t\t\t\t\t0x0020\nxtensa xtreg\tar0\t\t\t\t\t0x0100\nxtensa xtreg\tar1\t\t\t\t\t0x0101\nxtensa xtreg\tar2\t\t\t\t\t0x0102\nxtensa xtreg\tar3\t\t\t\t\t0x0103\nxtensa xtreg\tar4\t\t\t\t\t0x0104\nxtensa xtreg\tar5\t\t\t\t\t0x0105\nxtensa xtreg\tar6\t\t\t\t\t0x0106\nxtensa xtreg\tar7\t\t\t\t\t0x0107\nxtensa xtreg\tar8\t\t\t\t\t0x0108\nxtensa xtreg\tar9\t\t\t\t\t0x0109\nxtensa xtreg\tar10\t\t\t\t0x010a\nxtensa xtreg\tar11\t\t\t\t0x010b\nxtensa xtreg\tar12\t\t\t\t0x010c\nxtensa xtreg\tar13\t\t\t\t0x010d\nxtensa xtreg\tar14\t\t\t\t0x010e\nxtensa xtreg\tar15\t\t\t\t0x010f\nxtensa xtreg\tar16\t\t\t\t0x0110\nxtensa xtreg\tar17\t\t\t\t0x0111\nxtensa xtreg\tar18\t\t\t\t0x0112\nxtensa xtreg\tar19\t\t\t\t0x0113\nxtensa xtreg\tar20\t\t\t\t0x0114\nxtensa xtreg\tar21\t\t\t\t0x0115\nxtensa xtreg\tar22\t\t\t\t0x0116\nxtensa xtreg\tar23\t\t\t\t0x0117\nxtensa xtreg\tar24\t\t\t\t0x0118\nxtensa xtreg\tar25\t\t\t\t0x0119\nxtensa xtreg\tar26\t\t\t\t0x011a\nxtensa xtreg\tar27\t\t\t\t0x011b\nxtensa xtreg\tar28\t\t\t\t0x011c\nxtensa xtreg\tar29\t\t\t\t0x011d\nxtensa xtreg\tar30\t\t\t\t0x011e\nxtensa xtreg\tar31\t\t\t\t0x011f\nxtensa xtreg\tar32\t\t\t\t0x0120\nxtensa xtreg\tar33\t\t\t\t0x0121\nxtensa xtreg\tar34\t\t\t\t0x0122\nxtensa xtreg\tar35\t\t\t\t0x0123\nxtensa xtreg\tar36\t\t\t\t0x0124\nxtensa xtreg\tar37\t\t\t\t0x0125\nxtensa xtreg\tar38\t\t\t\t0x0126\nxtensa xtreg\tar39\t\t\t\t0x0127\nxtensa xtreg\tar40\t\t\t\t0x0128\nxtensa xtreg\tar41\t\t\t\t0x0129\nxtensa xtreg\tar42\t\t\t\t0x012a\nxtensa xtreg\tar43\t\t\t\t0x012b\nxtensa xtreg\tar44\t\t\t\t0x012c\nxtensa xtreg\tar45\t\t\t\t0x012d\nxtensa xtreg\tar46\t\t\t\t0x012e\nxtensa xtreg\tar47\t\t\t\t0x012f\nxtensa xtreg\tar48\t\t\t\t0x0130\nxtensa xtreg\tar49\t\t\t\t0x0131\nxtensa xtreg\tar50\t\t\t\t0x0132\nxtensa xtreg\tar51\t\t\t\t0x0133\nxtensa xtreg\tar52\t\t\t\t0x0134\nxtensa xtreg\tar53\t\t\t\t0x0135\nxtensa xtreg\tar54\t\t\t\t0x0136\nxtensa xtreg\tar55\t\t\t\t0x0137\nxtensa xtreg\tar56\t\t\t\t0x0138\nxtensa xtreg\tar57\t\t\t\t0x0139\nxtensa xtreg\tar58\t\t\t\t0x013a\nxtensa xtreg\tar59\t\t\t\t0x013b\nxtensa xtreg\tar60\t\t\t\t0x013c\nxtensa xtreg\tar61\t\t\t\t0x013d\nxtensa xtreg\tar62\t\t\t\t0x013e\nxtensa xtreg\tar63\t\t\t\t0x013f\nxtensa xtreg\tlbeg\t\t\t\t0x0200\nxtensa xtreg\tlend\t\t\t\t0x0201\nxtensa xtreg\tlcount\t\t\t\t0x0202\nxtensa xtreg\tsar\t\t\t\t\t0x0203\nxtensa xtreg\twindowbase\t\t\t0x0248\nxtensa xtreg\twindowstart\t\t\t0x0249\nxtensa xtreg\tconfigid0\t\t\t0x02b0\nxtensa xtreg\tconfigid1\t\t\t0x02d0\nxtensa xtreg\tps\t\t\t\t\t0x02e6\nxtensa xtreg\tthreadptr\t\t\t0x03e7\nxtensa xtreg\tbr\t\t\t\t\t0x0204\nxtensa xtreg\tscompare1\t\t\t0x020c\nxtensa xtreg\tacclo\t\t\t\t0x0210\nxtensa xtreg\tacchi\t\t\t\t0x0211\nxtensa xtreg\tm0\t\t\t\t\t0x0220\nxtensa xtreg\tm1\t\t\t\t\t0x0221\nxtensa xtreg\tm2\t\t\t\t\t0x0222\nxtensa xtreg\tm3\t\t\t\t\t0x0223\nxtensa xtreg\tgpio_out\t\t\t0x030c\nxtensa xtreg\tf0\t\t\t\t\t0x0030\nxtensa xtreg\tf1\t\t\t\t\t0x0031\nxtensa xtreg\tf2\t\t\t\t\t0x0032\nxtensa xtreg\tf3\t\t\t\t\t0x0033\nxtensa xtreg\tf4\t\t\t\t\t0x0034\nxtensa xtreg\tf5\t\t\t\t\t0x0035\nxtensa xtreg\tf6\t\t\t\t\t0x0036\nxtensa xtreg\tf7\t\t\t\t\t0x0037\nxtensa xtreg\tf8\t\t\t\t\t0x0038\nxtensa xtreg\tf9\t\t\t\t\t0x0039\nxtensa xtreg\tf10\t\t\t\t\t0x003a\nxtensa xtreg\tf11\t\t\t\t\t0x003b\nxtensa xtreg\tf12\t\t\t\t\t0x003c\nxtensa xtreg\tf13\t\t\t\t\t0x003d\nxtensa xtreg\tf14\t\t\t\t\t0x003e\nxtensa xtreg\tf15\t\t\t\t\t0x003f\nxtensa xtreg\tfcr\t\t\t\t\t0x03e8\nxtensa xtreg\tfsr\t\t\t\t\t0x03e9\nxtensa xtreg\taccx_0\t\t\t\t0x0300\nxtensa xtreg\taccx_1\t\t\t\t0x0301\nxtensa xtreg\tqacc_h_0\t\t\t0x0302\nxtensa xtreg\tqacc_h_1\t\t\t0x0303\nxtensa xtreg\tqacc_h_2\t\t\t0x0304\nxtensa xtreg\tqacc_h_3\t\t\t0x0305\nxtensa xtreg\tqacc_h_4\t\t\t0x0306\nxtensa xtreg\tqacc_l_0\t\t\t0x0307\nxtensa xtreg\tqacc_l_1\t\t\t0x0308\nxtensa xtreg\tqacc_l_2\t\t\t0x0309\nxtensa xtreg\tqacc_l_3\t\t\t0x030a\nxtensa xtreg\tqacc_l_4\t\t\t0x030b\nxtensa xtreg\tsar_byte\t\t\t0x030d\nxtensa xtreg\tfft_bit_width\t\t0x030e\nxtensa xtreg\tua_state_0\t\t\t0x030f\nxtensa xtreg\tua_state_1\t\t\t0x0310\nxtensa xtreg\tua_state_2\t\t\t0x0311\nxtensa xtreg\tua_state_3\t\t\t0x0312\nxtensa xtreg\tq0\t\t\t\t\t0x1008\nxtensa xtreg\tq1\t\t\t\t\t0x1009\nxtensa xtreg\tq2\t\t\t\t\t0x100a\nxtensa xtreg\tq3\t\t\t\t\t0x100b\nxtensa xtreg\tq4\t\t\t\t\t0x100c\nxtensa xtreg\tq5\t\t\t\t\t0x100d\nxtensa xtreg\tq6\t\t\t\t\t0x100e\nxtensa xtreg\tq7\t\t\t\t\t0x100f\nxtensa xtreg\tmmid\t\t\t\t0x0259\nxtensa xtreg\tibreakenable\t\t0x0260\nxtensa xtreg\tmemctl\t\t\t\t0x0261\nxtensa xtreg\tatomctl\t\t\t\t0x0263\nxtensa xtreg\tddr\t\t\t\t\t0x0268\nxtensa xtreg\tibreaka0\t\t\t0x0280\nxtensa xtreg\tibreaka1\t\t\t0x0281\nxtensa xtreg\tdbreaka0\t\t\t0x0290\nxtensa xtreg\tdbreaka1\t\t\t0x0291\nxtensa xtreg\tdbreakc0\t\t\t0x02a0\nxtensa xtreg\tdbreakc1\t\t\t0x02a1\nxtensa xtreg\tepc1\t\t\t\t0x02b1\nxtensa xtreg\tepc2\t\t\t\t0x02b2\nxtensa xtreg\tepc3\t\t\t\t0x02b3\nxtensa xtreg\tepc4\t\t\t\t0x02b4\nxtensa xtreg\tepc5\t\t\t\t0x02b5\nxtensa xtreg\tepc6\t\t\t\t0x02b6\nxtensa xtreg\tepc7\t\t\t\t0x02b7\nxtensa xtreg\tdepc\t\t\t\t0x02c0\nxtensa xtreg\teps2\t\t\t\t0x02c2\nxtensa xtreg\teps3\t\t\t\t0x02c3\nxtensa xtreg\teps4\t\t\t\t0x02c4\nxtensa xtreg\teps5\t\t\t\t0x02c5\nxtensa xtreg\teps6\t\t\t\t0x02c6\nxtensa xtreg\teps7\t\t\t\t0x02c7\nxtensa xtreg\texcsave1\t\t\t0x02d1\nxtensa xtreg\texcsave2\t\t\t0x02d2\nxtensa xtreg\texcsave3\t\t\t0x02d3\nxtensa xtreg\texcsave4\t\t\t0x02d4\nxtensa xtreg\texcsave5\t\t\t0x02d5\nxtensa xtreg\texcsave6\t\t\t0x02d6\nxtensa xtreg\texcsave7\t\t\t0x02d7\nxtensa xtreg\tcpenable\t\t\t0x02e0\nxtensa xtreg\tinterrupt\t\t\t0x02e2\nxtensa xtreg\tintset\t\t\t\t0x02e2\nxtensa xtreg\tintclear\t\t\t0x02e3\nxtensa xtreg\tintenable\t\t\t0x02e4\nxtensa xtreg\tvecbase\t\t\t\t0x02e7\nxtensa xtreg\texccause\t\t\t0x02e8\nxtensa xtreg\tdebugcause\t\t\t0x02e9\nxtensa xtreg\tccount\t\t\t\t0x02ea\nxtensa xtreg\tprid\t\t\t\t0x02eb\nxtensa xtreg\ticount\t\t\t\t0x02ec\nxtensa xtreg\ticountlevel\t\t\t0x02ed\nxtensa xtreg\texcvaddr\t\t\t0x02ee\nxtensa xtreg\tccompare0\t\t\t0x02f0\nxtensa xtreg\tccompare1\t\t\t0x02f1\nxtensa xtreg\tccompare2\t\t\t0x02f2\nxtensa xtreg\tmisc0\t\t\t\t0x02f4\nxtensa xtreg\tmisc1\t\t\t\t0x02f5\nxtensa xtreg\tmisc2\t\t\t\t0x02f6\nxtensa xtreg\tmisc3\t\t\t\t0x02f7\nxtensa xtreg\tpwrctl\t\t\t\t0x2028\nxtensa xtreg\tpwrstat\t\t\t\t0x2029\nxtensa xtreg\teristat\t\t\t\t0x202a\nxtensa xtreg\tcs_itctrl\t\t\t0x202b\nxtensa xtreg\tcs_claimset\t\t\t0x202c\nxtensa xtreg\tcs_claimclr\t\t\t0x202d\nxtensa xtreg\tcs_lockaccess\t\t0x202e\nxtensa xtreg\tcs_lockstatus\t\t0x202f\nxtensa xtreg\tcs_authstatus\t\t0x2030\nxtensa xtreg\tfault_info\t\t\t0x203f\nxtensa xtreg\ttrax_id\t\t\t\t0x2040\nxtensa xtreg\ttrax_control\t\t0x2041\nxtensa xtreg\ttrax_status\t\t\t0x2042\nxtensa xtreg\ttrax_data\t\t\t0x2043\nxtensa xtreg\ttrax_address\t\t0x2044\nxtensa xtreg\ttrax_pctrigger\t\t0x2045\nxtensa xtreg\ttrax_pcmatch\t\t0x2046\nxtensa xtreg\ttrax_delay\t\t\t0x2047\nxtensa xtreg\ttrax_memstart\t\t0x2048\nxtensa xtreg\ttrax_memend\t\t\t0x2049\nxtensa xtreg\tpmg\t\t\t\t\t0x2057\nxtensa xtreg\tpmpc\t\t\t\t0x2058\nxtensa xtreg\tpm0\t\t\t\t\t0x2059\nxtensa xtreg\tpm1\t\t\t\t\t0x205a\nxtensa xtreg\tpmctrl0\t\t\t\t0x205b\nxtensa xtreg\tpmctrl1\t\t\t\t0x205c\nxtensa xtreg\tpmstat0\t\t\t\t0x205d\nxtensa xtreg\tpmstat1\t\t\t\t0x205e\nxtensa xtreg\tocdid\t\t\t\t0x205f\nxtensa xtreg\tocd_dcrclr\t\t\t0x2060\nxtensa xtreg\tocd_dcrset\t\t\t0x2061\nxtensa xtreg\tocd_dsr\t\t\t\t0x2062\nxtensa xtreg\ta0\t\t\t\t\t0x0000\nxtensa xtreg\ta1\t\t\t\t\t0x0001\nxtensa xtreg\ta2\t\t\t\t\t0x0002\nxtensa xtreg\ta3\t\t\t\t\t0x0003\nxtensa xtreg\ta4\t\t\t\t\t0x0004\nxtensa xtreg\ta5\t\t\t\t\t0x0005\nxtensa xtreg\ta6\t\t\t\t\t0x0006\nxtensa xtreg\ta7\t\t\t\t\t0x0007\nxtensa xtreg\ta8\t\t\t\t\t0x0008\nxtensa xtreg\ta9\t\t\t\t\t0x0009\nxtensa xtreg\ta10\t\t\t\t\t0x000a\nxtensa xtreg\ta11\t\t\t\t\t0x000b\nxtensa xtreg\ta12\t\t\t\t\t0x000c\nxtensa xtreg\ta13\t\t\t\t\t0x000d\nxtensa xtreg\ta14\t\t\t\t\t0x000e\nxtensa xtreg\ta15\t\t\t\t\t0x000f\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xtensa-core-nxp_rt600.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# OpenOCD configuration file for Xtensa HiFi DSP in NXP RT600 target\n\n\n#  Core definition and ABI\nxtensa xtdef\tLX\nxtensa xtopt\tarnum           \t32\nxtensa xtopt\twindowed        \t1\n\n\n#  Exception/Interrupt Options\nxtensa xtopt\texceptions      \t1\nxtensa xtopt\thipriints       \t1\nxtensa xtopt\tintlevels       \t4\nxtensa xtopt\texcmlevel       \t2\n\n\n#  Cache Options\nxtensa xtmem\ticache          \t256\t32768\t4\nxtensa xtmem\tdcache          \t256\t65536\t4\t1\n\n\n#  Memory Options\nxtensa xtmem\tiram            \t0x24020000\t65536\nxtensa xtmem\tdram            \t0x24000000\t65536\nxtensa xtmem\tsram            \t0x00000000\t603979776\n\n\n#  Memory Protection/Translation Options\n\n\n#  Debug Options\nxtensa xtopt\tdebuglevel      \t4\nxtensa xtopt\tibreaknum       \t2\nxtensa xtopt\tdbreaknum       \t2\n\n\n#  Core Registers\nxtensa xtregs\t208\nxtensa xtreg\tpc              \t0x0020\nxtensa xtreg\tar0             \t0x0100\nxtensa xtreg\tar1             \t0x0101\nxtensa xtreg\tar2             \t0x0102\nxtensa xtreg\tar3             \t0x0103\nxtensa xtreg\tar4             \t0x0104\nxtensa xtreg\tar5             \t0x0105\nxtensa xtreg\tar6             \t0x0106\nxtensa xtreg\tar7             \t0x0107\nxtensa xtreg\tar8             \t0x0108\nxtensa xtreg\tar9             \t0x0109\nxtensa xtreg\tar10            \t0x010a\nxtensa xtreg\tar11            \t0x010b\nxtensa xtreg\tar12            \t0x010c\nxtensa xtreg\tar13            \t0x010d\nxtensa xtreg\tar14            \t0x010e\nxtensa xtreg\tar15            \t0x010f\nxtensa xtreg\tar16            \t0x0110\nxtensa xtreg\tar17            \t0x0111\nxtensa xtreg\tar18            \t0x0112\nxtensa xtreg\tar19            \t0x0113\nxtensa xtreg\tar20            \t0x0114\nxtensa xtreg\tar21            \t0x0115\nxtensa xtreg\tar22            \t0x0116\nxtensa xtreg\tar23            \t0x0117\nxtensa xtreg\tar24            \t0x0118\nxtensa xtreg\tar25            \t0x0119\nxtensa xtreg\tar26            \t0x011a\nxtensa xtreg\tar27            \t0x011b\nxtensa xtreg\tar28            \t0x011c\nxtensa xtreg\tar29            \t0x011d\nxtensa xtreg\tar30            \t0x011e\nxtensa xtreg\tar31            \t0x011f\nxtensa xtreg\tlbeg            \t0x0200\nxtensa xtreg\tlend            \t0x0201\nxtensa xtreg\tlcount          \t0x0202\nxtensa xtreg\tsar             \t0x0203\nxtensa xtreg\tprefctl         \t0x0228\nxtensa xtreg\twindowbase      \t0x0248\nxtensa xtreg\twindowstart     \t0x0249\nxtensa xtreg\tconfigid0       \t0x02b0\nxtensa xtreg\tconfigid1       \t0x02d0\nxtensa xtreg\tps              \t0x02e6\nxtensa xtreg\tthreadptr       \t0x03e7\nxtensa xtreg\tbr              \t0x0204\nxtensa xtreg\tscompare1       \t0x020c\nxtensa xtreg\tacclo           \t0x0210\nxtensa xtreg\tacchi           \t0x0211\nxtensa xtreg\tm0              \t0x0220\nxtensa xtreg\tm1              \t0x0221\nxtensa xtreg\tm2              \t0x0222\nxtensa xtreg\tm3              \t0x0223\nxtensa xtreg\texpstate        \t0x03e6\nxtensa xtreg\tf64r_lo         \t0x03ea\nxtensa xtreg\tf64r_hi         \t0x03eb\nxtensa xtreg\tf64s            \t0x03ec\nxtensa xtreg\tae_ovf_sar      \t0x03f0\nxtensa xtreg\tae_bithead      \t0x03f1\nxtensa xtreg\tae_ts_fts_bu_bp \t0x03f2\nxtensa xtreg\tae_cw_sd_no     \t0x03f3\nxtensa xtreg\tae_cbegin0      \t0x03f6\nxtensa xtreg\tae_cend0        \t0x03f7\nxtensa xtreg\tae_cbegin1      \t0x03f8\nxtensa xtreg\tae_cend1        \t0x03f9\nxtensa xtreg\taed0            \t0x1010\nxtensa xtreg\taed1            \t0x1011\nxtensa xtreg\taed2            \t0x1012\nxtensa xtreg\taed3            \t0x1013\nxtensa xtreg\taed4            \t0x1014\nxtensa xtreg\taed5            \t0x1015\nxtensa xtreg\taed6            \t0x1016\nxtensa xtreg\taed7            \t0x1017\nxtensa xtreg\taed8            \t0x1018\nxtensa xtreg\taed9            \t0x1019\nxtensa xtreg\taed10           \t0x101a\nxtensa xtreg\taed11           \t0x101b\nxtensa xtreg\taed12           \t0x101c\nxtensa xtreg\taed13           \t0x101d\nxtensa xtreg\taed14           \t0x101e\nxtensa xtreg\taed15           \t0x101f\nxtensa xtreg\tu0              \t0x1020\nxtensa xtreg\tu1              \t0x1021\nxtensa xtreg\tu2              \t0x1022\nxtensa xtreg\tu3              \t0x1023\nxtensa xtreg\taep0            \t0x1024\nxtensa xtreg\taep1            \t0x1025\nxtensa xtreg\taep2            \t0x1026\nxtensa xtreg\taep3            \t0x1027\nxtensa xtreg\tfcr_fsr         \t0x1029\nxtensa xtreg\tmmid            \t0x0259\nxtensa xtreg\tibreakenable    \t0x0260\nxtensa xtreg\tmemctl          \t0x0261\nxtensa xtreg\tatomctl         \t0x0263\nxtensa xtreg\tddr             \t0x0268\nxtensa xtreg\tibreaka0        \t0x0280\nxtensa xtreg\tibreaka1        \t0x0281\nxtensa xtreg\tdbreaka0        \t0x0290\nxtensa xtreg\tdbreaka1        \t0x0291\nxtensa xtreg\tdbreakc0        \t0x02a0\nxtensa xtreg\tdbreakc1        \t0x02a1\nxtensa xtreg\tepc1            \t0x02b1\nxtensa xtreg\tepc2            \t0x02b2\nxtensa xtreg\tepc3            \t0x02b3\nxtensa xtreg\tepc4            \t0x02b4\nxtensa xtreg\tepc5            \t0x02b5\nxtensa xtreg\tdepc            \t0x02c0\nxtensa xtreg\teps2            \t0x02c2\nxtensa xtreg\teps3            \t0x02c3\nxtensa xtreg\teps4            \t0x02c4\nxtensa xtreg\teps5            \t0x02c5\nxtensa xtreg\texcsave1        \t0x02d1\nxtensa xtreg\texcsave2        \t0x02d2\nxtensa xtreg\texcsave3        \t0x02d3\nxtensa xtreg\texcsave4        \t0x02d4\nxtensa xtreg\texcsave5        \t0x02d5\nxtensa xtreg\tcpenable        \t0x02e0\nxtensa xtreg\tinterrupt       \t0x02e2\nxtensa xtreg\tintset          \t0x02e2\nxtensa xtreg\tintclear        \t0x02e3\nxtensa xtreg\tintenable       \t0x02e4\nxtensa xtreg\tvecbase         \t0x02e7\nxtensa xtreg\texccause        \t0x02e8\nxtensa xtreg\tdebugcause      \t0x02e9\nxtensa xtreg\tccount          \t0x02ea\nxtensa xtreg\tprid            \t0x02eb\nxtensa xtreg\ticount          \t0x02ec\nxtensa xtreg\ticountlevel     \t0x02ed\nxtensa xtreg\texcvaddr        \t0x02ee\nxtensa xtreg\tccompare0       \t0x02f0\nxtensa xtreg\tccompare1       \t0x02f1\nxtensa xtreg\tmisc0           \t0x02f4\nxtensa xtreg\tmisc1           \t0x02f5\nxtensa xtreg\tpwrctl          \t0x2024\nxtensa xtreg\tpwrstat         \t0x2025\nxtensa xtreg\teristat         \t0x2026\nxtensa xtreg\tcs_itctrl       \t0x2027\nxtensa xtreg\tcs_claimset     \t0x2028\nxtensa xtreg\tcs_claimclr     \t0x2029\nxtensa xtreg\tcs_lockaccess   \t0x202a\nxtensa xtreg\tcs_lockstatus   \t0x202b\nxtensa xtreg\tcs_authstatus   \t0x202c\nxtensa xtreg\tpmg             \t0x203b\nxtensa xtreg\tpmpc            \t0x203c\nxtensa xtreg\tpm0             \t0x203d\nxtensa xtreg\tpm1             \t0x203e\nxtensa xtreg\tpmctrl0         \t0x203f\nxtensa xtreg\tpmctrl1         \t0x2040\nxtensa xtreg\tpmstat0         \t0x2041\nxtensa xtreg\tpmstat1         \t0x2042\nxtensa xtreg\tocdid           \t0x2043\nxtensa xtreg\tocd_dcrclr      \t0x2044\nxtensa xtreg\tocd_dcrset      \t0x2045\nxtensa xtreg\tocd_dsr         \t0x2046\nxtensa xtreg\ta0              \t0x0000\nxtensa xtreg\ta1              \t0x0001\nxtensa xtreg\ta2              \t0x0002\nxtensa xtreg\ta3              \t0x0003\nxtensa xtreg\ta4              \t0x0004\nxtensa xtreg\ta5              \t0x0005\nxtensa xtreg\ta6              \t0x0006\nxtensa xtreg\ta7              \t0x0007\nxtensa xtreg\ta8              \t0x0008\nxtensa xtreg\ta9              \t0x0009\nxtensa xtreg\ta10             \t0x000a\nxtensa xtreg\ta11             \t0x000b\nxtensa xtreg\ta12             \t0x000c\nxtensa xtreg\ta13             \t0x000d\nxtensa xtreg\ta14             \t0x000e\nxtensa xtreg\ta15             \t0x000f\nxtensa xtreg\tb0              \t0x0010\nxtensa xtreg\tb1              \t0x0011\nxtensa xtreg\tb2              \t0x0012\nxtensa xtreg\tb3              \t0x0013\nxtensa xtreg\tb4              \t0x0014\nxtensa xtreg\tb5              \t0x0015\nxtensa xtreg\tb6              \t0x0016\nxtensa xtreg\tb7              \t0x0017\nxtensa xtreg\tb8              \t0x0018\nxtensa xtreg\tb9              \t0x0019\nxtensa xtreg\tb10             \t0x001a\nxtensa xtreg\tb11             \t0x001b\nxtensa xtreg\tb12             \t0x001c\nxtensa xtreg\tb13             \t0x001d\nxtensa xtreg\tb14             \t0x001e\nxtensa xtreg\tb15             \t0x001f\nxtensa xtreg\tpsintlevel      \t0x2006\nxtensa xtreg\tpsum            \t0x2007\nxtensa xtreg\tpswoe           \t0x2008\nxtensa xtreg\tpsexcm          \t0x2009\nxtensa xtreg\tpscallinc       \t0x200a\nxtensa xtreg\tpsowb           \t0x200b\nxtensa xtreg\tacc             \t0x200c\nxtensa xtreg\tdbnum           \t0x2011\nxtensa xtreg\tae_overflow     \t0x2014\nxtensa xtreg\tae_sar          \t0x2015\nxtensa xtreg\tae_cwrap        \t0x2016\nxtensa xtreg\tae_bitptr       \t0x2017\nxtensa xtreg\tae_bitsused     \t0x2018\nxtensa xtreg\tae_tablesize    \t0x2019\nxtensa xtreg\tae_first_ts     \t0x201a\nxtensa xtreg\tae_nextoffset   \t0x201b\nxtensa xtreg\tae_searchdone   \t0x201c\nxtensa xtreg\troundmode       \t0x201d\nxtensa xtreg\tinvalidflag     \t0x201e\nxtensa xtreg\tdivzeroflag     \t0x201f\nxtensa xtreg\toverflowflag    \t0x2020\nxtensa xtreg\tunderflowflag   \t0x2021\nxtensa xtreg\tinexactflag     \t0x2022\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xtensa-core-xt8.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# OpenOCD configuration file for Xtensa xt8 target\n\n#  Core definition and ABI\nxtensa xtdef\tLX\nxtensa xtopt\tarnum           \t32\nxtensa xtopt\twindowed        \t1\n\n\n#  Exception/Interrupt Options\nxtensa xtopt\texceptions      \t1\nxtensa xtopt\thipriints       \t1\nxtensa xtopt\tintlevels       \t3\nxtensa xtopt\texcmlevel       \t1\n\n\n#  Cache Options\nxtensa xtmem\ticache          \t16\t1024\t1\nxtensa xtmem\tdcache          \t16\t1024\t1\t1\n\n\n#  Memory Options\nxtensa xtmem\tiram            \t0x40000000\t1048576\nxtensa xtmem\tdram            \t0x3ff00000\t262144\nxtensa xtmem\tsrom            \t0x50000000\t131072\nxtensa xtmem\tsram            \t0x60000000\t4194304\n\n\n#  Memory Protection/Translation Options\n\n\n#  Debug Options\nxtensa xtopt\tdebuglevel      \t3\nxtensa xtopt\tibreaknum       \t2\nxtensa xtopt\tdbreaknum       \t2\n\n\n#  Core Registers\nxtensa xtregs\t127\nxtensa xtreg\ta0              \t0x0000\nxtensa xtreg\ta1              \t0x0001\nxtensa xtreg\ta2              \t0x0002\nxtensa xtreg\ta3              \t0x0003\nxtensa xtreg\ta4              \t0x0004\nxtensa xtreg\ta5              \t0x0005\nxtensa xtreg\ta6              \t0x0006\nxtensa xtreg\ta7              \t0x0007\nxtensa xtreg\ta8              \t0x0008\nxtensa xtreg\ta9              \t0x0009\nxtensa xtreg\ta10             \t0x000a\nxtensa xtreg\ta11             \t0x000b\nxtensa xtreg\ta12             \t0x000c\nxtensa xtreg\ta13             \t0x000d\nxtensa xtreg\ta14             \t0x000e\nxtensa xtreg\ta15             \t0x000f\nxtensa xtreg\tpc              \t0x0020\nxtensa xtreg\tar0             \t0x0100\nxtensa xtreg\tar1             \t0x0101\nxtensa xtreg\tar2             \t0x0102\nxtensa xtreg\tar3             \t0x0103\nxtensa xtreg\tar4             \t0x0104\nxtensa xtreg\tar5             \t0x0105\nxtensa xtreg\tar6             \t0x0106\nxtensa xtreg\tar7             \t0x0107\nxtensa xtreg\tar8             \t0x0108\nxtensa xtreg\tar9             \t0x0109\nxtensa xtreg\tar10            \t0x010a\nxtensa xtreg\tar11            \t0x010b\nxtensa xtreg\tar12            \t0x010c\nxtensa xtreg\tar13            \t0x010d\nxtensa xtreg\tar14            \t0x010e\nxtensa xtreg\tar15            \t0x010f\nxtensa xtreg\tar16            \t0x0110\nxtensa xtreg\tar17            \t0x0111\nxtensa xtreg\tar18            \t0x0112\nxtensa xtreg\tar19            \t0x0113\nxtensa xtreg\tar20            \t0x0114\nxtensa xtreg\tar21            \t0x0115\nxtensa xtreg\tar22            \t0x0116\nxtensa xtreg\tar23            \t0x0117\nxtensa xtreg\tar24            \t0x0118\nxtensa xtreg\tar25            \t0x0119\nxtensa xtreg\tar26            \t0x011a\nxtensa xtreg\tar27            \t0x011b\nxtensa xtreg\tar28            \t0x011c\nxtensa xtreg\tar29            \t0x011d\nxtensa xtreg\tar30            \t0x011e\nxtensa xtreg\tar31            \t0x011f\nxtensa xtreg\tlbeg            \t0x0200\nxtensa xtreg\tlend            \t0x0201\nxtensa xtreg\tlcount          \t0x0202\nxtensa xtreg\tsar             \t0x0203\nxtensa xtreg\twindowbase      \t0x0248\nxtensa xtreg\twindowstart     \t0x0249\nxtensa xtreg\tconfigid0       \t0x02b0\nxtensa xtreg\tconfigid1       \t0x02d0\nxtensa xtreg\tps              \t0x02e6\nxtensa xtreg\texpstate        \t0x03e6\nxtensa xtreg\tmmid            \t0x0259\nxtensa xtreg\tibreakenable    \t0x0260\nxtensa xtreg\tddr             \t0x0268\nxtensa xtreg\tibreaka0        \t0x0280\nxtensa xtreg\tibreaka1        \t0x0281\nxtensa xtreg\tdbreaka0        \t0x0290\nxtensa xtreg\tdbreaka1        \t0x0291\nxtensa xtreg\tdbreakc0        \t0x02a0\nxtensa xtreg\tdbreakc1        \t0x02a1\nxtensa xtreg\tepc1            \t0x02b1\nxtensa xtreg\tepc2            \t0x02b2\nxtensa xtreg\tepc3            \t0x02b3\nxtensa xtreg\tdepc            \t0x02c0\nxtensa xtreg\teps2            \t0x02c2\nxtensa xtreg\teps3            \t0x02c3\nxtensa xtreg\texcsave1        \t0x02d1\nxtensa xtreg\texcsave2        \t0x02d2\nxtensa xtreg\texcsave3        \t0x02d3\nxtensa xtreg\tinterrupt       \t0x02e2\nxtensa xtreg\tintset          \t0x02e2\nxtensa xtreg\tintclear        \t0x02e3\nxtensa xtreg\tintenable       \t0x02e4\nxtensa xtreg\texccause        \t0x02e8\nxtensa xtreg\tdebugcause      \t0x02e9\nxtensa xtreg\tccount          \t0x02ea\nxtensa xtreg\ticount          \t0x02ec\nxtensa xtreg\ticountlevel     \t0x02ed\nxtensa xtreg\texcvaddr        \t0x02ee\nxtensa xtreg\tccompare0       \t0x02f0\nxtensa xtreg\tccompare1       \t0x02f1\nxtensa xtreg\tpwrctl          \t0x200f\nxtensa xtreg\tpwrstat         \t0x2010\nxtensa xtreg\teristat         \t0x2011\nxtensa xtreg\tcs_itctrl       \t0x2012\nxtensa xtreg\tcs_claimset     \t0x2013\nxtensa xtreg\tcs_claimclr     \t0x2014\nxtensa xtreg\tcs_lockaccess   \t0x2015\nxtensa xtreg\tcs_lockstatus   \t0x2016\nxtensa xtreg\tcs_authstatus   \t0x2017\nxtensa xtreg\tfault_info      \t0x2026\nxtensa xtreg\ttrax_id         \t0x2027\nxtensa xtreg\ttrax_control    \t0x2028\nxtensa xtreg\ttrax_status     \t0x2029\nxtensa xtreg\ttrax_data       \t0x202a\nxtensa xtreg\ttrax_address    \t0x202b\nxtensa xtreg\ttrax_pctrigger  \t0x202c\nxtensa xtreg\ttrax_pcmatch    \t0x202d\nxtensa xtreg\ttrax_delay      \t0x202e\nxtensa xtreg\ttrax_memstart   \t0x202f\nxtensa xtreg\ttrax_memend     \t0x2030\nxtensa xtreg\tpmg             \t0x203e\nxtensa xtreg\tpmpc            \t0x203f\nxtensa xtreg\tpm0             \t0x2040\nxtensa xtreg\tpm1             \t0x2041\nxtensa xtreg\tpmctrl0         \t0x2042\nxtensa xtreg\tpmctrl1         \t0x2043\nxtensa xtreg\tpmstat0         \t0x2044\nxtensa xtreg\tpmstat1         \t0x2045\nxtensa xtreg\tocdid           \t0x2046\nxtensa xtreg\tocd_dcrclr      \t0x2047\nxtensa xtreg\tocd_dcrset      \t0x2048\nxtensa xtreg\tocd_dsr         \t0x2049\nxtensa xtreg\tpsintlevel      \t0x2003\nxtensa xtreg\tpsum            \t0x2004\nxtensa xtreg\tpswoe           \t0x2005\nxtensa xtreg\tpsexcm          \t0x2006\nxtensa xtreg\tpscallinc       \t0x2007\nxtensa xtreg\tpsowb           \t0x2008\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/xtensa.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n# Target Support for Xtensa Processors\n#\n\nset xtensa_ids { 0x120034e5 0x120134e5\n\t\t\t\t 0x209034e5 0x209134e5 0x209234e5 0x209334e5 0x209434e5 0x209534e5 0x209634e5 0x209734e5\n\t\t\t\t 0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5 0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5\n\t\t\t\t 0x20b034e5 }\nset expected_xtensa_ids {}\nforeach i $xtensa_ids {\n\tlappend expected_xtensa_ids -expected-id $i\n}\n\nif { [info exists CHIPNAME] } {\n\tset _CHIPNAME $CHIPNAME\n} else {\n\tset _CHIPNAME xtensa\n}\n\nif { [info exists CPUTAPID] } {\n\tset _CPUTAPARGLIST \"-expected-id $CPUTAPID\"\n} else {\n\tset _CPUTAPARGLIST [join $expected_xtensa_ids]\n}\n\nset _TARGETNAME $_CHIPNAME\nset _CPU0NAME cpu\nset _TAPNAME $_CHIPNAME.$_CPU0NAME\n\nif { [info exists XTENSA_DAP] } {\n\tsource [find target/swj-dp.tcl]\n\t# SWD mode ignores the -irlen parameter\n\teval swj_newdap $_CHIPNAME cpu -irlen 4 $_CPUTAPARGLIST\n\tdap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\n\tset _TARGETNAME $_CHIPNAME.cpu\n\tif { [info exists XTENSA_DAP_BASE] } {\n\t\t# Specify fixed offset for accessing XDM via APB behind a DAP interface\n\t\ttarget create $_TARGETNAME xtensa -dap $_CHIPNAME.dap -dbgbase $XTENSA_DAP_BASE\n\t} else {\n\t\ttarget create $_TARGETNAME xtensa -dap $_CHIPNAME.dap\n\t}\n} else {\n\t# JTAG direct (without DAP)\n\teval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST\n\ttarget create $_TARGETNAME xtensa -chain-position $_TAPNAME\n}\n\n$_TARGETNAME configure -event reset-assert-post { soft_reset_halt }\n\ngdb_report_register_access_error enable\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/zynq_7000.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Xilinx Zynq-7000 All Programmable SoC\n#\n# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm\n# https://www.xilinx.com/member/forms/download/sim-model-eval-license-xef.html?filename=bsdl_zynq_2.zip\n#\n# 0x03736093  XQ7Z100 XC7Z100I XC7Z100\n# 0x03731093  XQ7Z045 XC7Z045I XC7Z045\n# 0x0372c093  XQ7Z030 XC7Z030I XC7Z030 XA7Z030\n# 0x03727093  XQ7Z020 XC7Z020I XC7Z020 XA7Z020\n# 0x03732093  XC7Z035I XC7Z035\n# 0x0373b093  XC7Z015I XC7Z015\n# 0x03728093  XC7Z014S\n# 0x0373c093  XC7Z012S\n# 0x03722093  XC7Z010I XC7Z010 XA7Z010\n# 0x03723093  XC7Z007S\n\nset _CHIPNAME zynq\nset _TARGETNAME $_CHIPNAME.cpu\n\njtag newtap zynq_pl bs -irlen 6 -ignore-version -ircapture 0x1 -irmask 0x03 \\\n    -expected-id 0x03723093 \\\n    -expected-id 0x03722093 \\\n    -expected-id 0x0373c093 \\\n    -expected-id 0x03728093 \\\n    -expected-id 0x0373B093 \\\n    -expected-id 0x03732093 \\\n    -expected-id 0x03727093 \\\n    -expected-id 0x0372C093 \\\n    -expected-id 0x03731093 \\\n    -expected-id 0x03736093\n\njtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\ntarget create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \\\n    -coreid 0 -dbgbase 0x80090000\ntarget create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \\\n    -coreid 1 -dbgbase 0x80092000\ntarget smp ${_TARGETNAME}0 ${_TARGETNAME}1\n\nadapter speed 1000\n\n${_TARGETNAME}0 configure -event reset-assert-post \"cortex_a dbginit\"\n${_TARGETNAME}1 configure -event reset-assert-post \"cortex_a dbginit\"\n\npld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart\nvirtex2 set_user_codes $zynq_pl.pld 0x02 0x03 0x22 0x23\n\nset XC7_JSHUTDOWN 0x0d\nset XC7_JPROGRAM 0x0b\nset XC7_JSTART 0x0c\nset XC7_BYPASS 0x3f\n\nproc zynqpl_program {tap} {\n\techo \"DEPRECATED! use 'virtex2 program ...' not 'zynqpl_program'\"\n\tglobal XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS\n\tirscan $tap $XC7_JSHUTDOWN\n\tirscan $tap $XC7_JPROGRAM\n\truntest 60000\n\t#JSTART prevents this from working...\n\t#irscan $tap $XC7_JSTART\n\truntest 2000\n\tirscan $tap $XC7_BYPASS\n\truntest 2000\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/target/к1879xб1я.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# СБИС К1879ХБ1Я\n# http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/\n\nadapter speed 1000\n\nif { [info exists CHIPNAME] } {\n    set _CHIPNAME $CHIPNAME\n} else {\n    set _CHIPNAME к1879хб1я\n}\n\nif { [info exists ENDIAN] } {\n    set _ENDIAN $ENDIAN\n} else {\n    set _ENDIAN little\n}\n\nif { [info exists DSP_TAPID] } {\n    set _DSP_TAPID $DSP_TAPID\n} else {\n    set _DSP_TAPID 0x2b900f0f\n}\n\njtag newtap $_CHIPNAME dsp -irlen 4 -expected-id $_DSP_TAPID\n\nif { [info exists CPU_TAPID] } {\n    set _CPU_TAPID $CPU_TAPID\n} else {\n    set _CPU_TAPID 0x07b76f0f\n}\n\njtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID\n\nset _TARGETNAME $_CHIPNAME.arm\ntarget create $_TARGETNAME arm11 -chain-position $_CHIPNAME.arm\n"
  },
  {
    "path": "openocd-win/openocd/scripts/test/selftest.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nadd_help_text selftest \"run selftest using working ram <tmpfile> <address> <size>\"\n\nproc selftest {tmpfile address size} {\n\n   for {set i 0} {$i < $size } {set i [expr {$i+4}]} {\n       mww [expr {$address+$i}] $i\n   }\n\n   for {set i 0} {$i < 10 } {set i [expr {$i+1}]} {\n    echo \"Test iteration $i\"\n    dump_image $tmpfile $address $size\n\tverify_image $tmpfile $address bin\n\tload_image $tmpfile $address bin\n   }\n\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/test/syntax1.cfg",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nadapter srst delay 200\njtag_ntrst_delay 200\n\n#use combined on interfaces or targets that can't set TRST/SRST separately\nreset_config trst_and_srst srst_pulls_trst\n\n#LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough\nadapter assert trst assert srst\nadapter deassert trst deassert srst\n\n#jtag scan chain\n#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\njtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f\n\n#target configuration\n#daemon_startup reset\n\nset _TARGETNAME [format \"%s.cpu\" lpc2148]\ntarget create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-backup 0\n\n$_TARGETNAME configure -event reset-init {\nsoft_reset_halt\nmvb 0xE01FC040 0x01\n}\n\n\n\nset _FLASHNAME $_CHIPNAME.flash\nflash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765\n"
  },
  {
    "path": "openocd-win/openocd/scripts/tools/firmware-recovery.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\necho \"\\n\\nFirmware recovery helpers\"\necho \"Use -c firmware_help to get help\\n\"\n\nset known_boards {\n    \"asus-rt-n16\t\tASUS RT-N16\"\n    \"asus-rt-n66u\t\tASUS RT-N66U\"\n    \"linksys-wag200g\t\tLinksys WAG200G\"\n    \"linksys-wrt54gl\t\tLinksys WRT54GL v1.1\"\n    \"netgear-dg834v3\t\tNetgear DG834G v3\"\n    \"tp-link_tl-mr3020\t\tTP-LINK TL-MR3020\"\n    \"bt-homehubv1\t\tBT HomeHub v1\"\n}\n\nproc firmware_help { } {\n    echo \"\nYour OpenOCD command should look like this:\nopenocd -f interface/<jtag adapter>.cfg -f tools/firmware-recovery.tcl -c \\\"<commands>*; shutdown\\\"\n\nWhere:\n<jtag adapter> is one of the supported devices, e.g. ftdi/jtagkey2\n<commands> are firmware-recovery commands separated by semicolon\n\nSupported commands:\nfirmware_help\t\t\tget this help\nlist_boards\t\t\tlist known boards and exit\nboard <name>\t\t\tselect board you work with\nlist_partitions\t\t\tlist partitions of the currently selected board\ndump_part <name> <filename>\tsave partition's contents to a file\nerase_part <name>\t\terase the given partition\nflash_part <name> <filename>\terase, flash and verify the given partition\nram_boot <filename>\t\tload binary file to RAM and run it\nadapter speed <freq>\t\tset JTAG clock frequency in kHz\n\nFor example, to clear nvram and reflash CFE on an RT-N16 using TUMPA, run:\nopenocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\\\\n\t-c \\\"board asus-rt-n16; erase_part nvram; flash_part CFE cfe-n16.bin; shutdown\\\"\n\\n\\n\"\n    shutdown\n}\n\n# set default, can be overridden later\nadapter speed 1000\n\nproc get_partition { name } {\n    global partition_list\n    dict get $partition_list $name\n}\n\nproc partition_desc { name } { lindex [get_partition $name] 0 }\nproc partition_start { name } { lindex [get_partition $name] 1 }\nproc partition_size { name } { lindex [get_partition $name] 2 }\n\nproc list_boards { } {\n    global known_boards\n    echo \"List of the supported boards:\\n\"\n    echo \"Board name\\t\\tDescription\"\n    echo \"-----------------------------------\"\n    foreach i $known_boards {\n\techo $i\n    }\n    echo \"\\n\\n\"\n}\n\nproc board { name } {\n    script [find board/$name.cfg]\n}\n\nproc list_partitions { } {\n    global partition_list\n    set fstr \"%-16s%-14s%-14s%s\"\n    echo \"\\nThe currently selected board is known to have these partitions:\\n\"\n    echo [format $fstr Name Start Size Description]\n    echo \"-------------------------------------------------------\"\n    for {set i 0} {$i < [llength $partition_list]} {incr i 2} {\n\tset key [lindex $partition_list $i]\n\techo [format $fstr $key [partition_start $key] [partition_size $key] [partition_desc $key]]\n    }\n    echo \"\\n\\n\"\n}\n\n# Magic to work with any targets, including semi-functional\nproc prepare_target { } {\n    init\n    catch {halt}\n    catch {reset init}\n    catch {halt}\n}\n\nproc dump_part { name filename } {\n    prepare_target\n    dump_image $filename [partition_start $name] [partition_size $name]\n}\n\nproc erase_part { name } {\n    prepare_target\n    flash erase_address [partition_start $name] [partition_size $name]\n}\n\nproc flash_part { name filename } {\n    prepare_target\n    flash write_image erase $filename [partition_start $name] bin\n    echo \"Verifying:\"\n    verify_image $filename [partition_start $name]\n}\n\nproc ram_boot { filename } {\n    global ram_boot_address\n    prepare_target\n    load_image $filename $ram_boot_address bin\n    resume $ram_boot_address\n}\n\necho \"\"\n"
  },
  {
    "path": "openocd-win/openocd/scripts/tools/memtest.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Algorithms by Michael Barr, released into public domain\n# Ported to OpenOCD by Shane Volpe, additional fixes by Paul Fertser\n\nset CPU_MAX_ADDRESS 0xFFFFFFFF\nsource [find bitsbytes.tcl]\nsource [find memory.tcl]\n\nproc runAllMemTests { baseAddress nBytes } {\n    memTestDataBus $baseAddress\n    memTestAddressBus $baseAddress $nBytes\n    memTestDevice $baseAddress $nBytes\n}\n\n#***********************************************************************************\n# *\n# * Function:    memTestDataBus()\n# *\n# * Description: Test the data bus wiring in a memory region by\n# *              performing a walking 1's test at a fixed address\n# *              within that region.  The address (and hence the\n# *              memory region) is selected by the caller.\n# *\t\t Ported from:\n# *\t\t http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C\n# * Notes:\n# *\n# * Returns:     Empty string if the test succeeds.\n# *              A non-zero result is the first pattern that failed.\n# *\n#***********************************************************************************\nproc memTestDataBus { address } {\n    echo \"Running memTestDataBus\"\n\n    for {set i 0} {$i < 32} {incr i} {\n\t# Shift bit\n\tset pattern [expr {1 << $i}]\n\n\t# Write pattern to memory\n\tmemwrite32 $address $pattern\n\n\t# Read pattern from memory\n\tset data [memread32 $address]\n\n\tif {$data != $pattern} {\n\t    echo \"FAILED DATABUS: Address: $address, Pattern: $pattern, Returned: $data\"\n\t    return $pattern\n\t}\n    }\n}\n\n#***********************************************************************************\n# *\n# * Function:    memTestAddressBus()\n# *\n# * Description: Perform a walking 1's test on the relevant bits\n# *              of the address and check for aliasing.  This test\n# *              will find single-bit address failures such as stuck\n# *              -high, stuck-low, and shorted pins.  The base address\n# *              and size of the region are selected by the caller.\n# *\t\t Ported from:\n# *\t\t http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C\n# *\n# * Notes:       For best results, the selected base address should\n# *              have enough LSB 0's to guarantee single address bit\n# *              changes.  For example, to test a 64-Kbyte region,\n# *              select a base address on a 64-Kbyte boundary.  Also,\n# *              select the region size as a power-of-two--if at all\n# *              possible.\n# *\n# * Returns:     Empty string if the test succeeds.\n# *              A non-zero result is the first address at which an\n# *              aliasing problem was uncovered.  By examining the\n# *              contents of memory, it may be possible to gather\n# *              additional information about the problem.\n# *\n#***********************************************************************************\nproc memTestAddressBus { baseAddress nBytes } {\n    set addressMask [expr {$nBytes - 1}]\n    set pattern 0xAAAAAAAA\n    set antipattern 0x55555555\n\n    echo \"Running memTestAddressBus\"\n\n    echo \"addressMask: [convertToHex $addressMask]\"\n\n    echo \"memTestAddressBus: Writing the default pattern at each of the power-of-two offsets...\"\n    for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}] } {\n\tset addr [expr {$baseAddress + $offset}]\n\tmemwrite32 $addr $pattern\n    }\n\n    echo \"memTestAddressBus: Checking for address bits stuck high...\"\n    memwrite32 $baseAddress $antipattern\n\n    for {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} {\n\tset addr [expr {$baseAddress + $offset}]\n\tset data [memread32 $addr]\n\n\tif {$data != $pattern} {\n\t    echo \"FAILED DATA_ADDR_BUS_SHIGH: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]\"\n\t    return $pattern\n\t}\n    }\n\n    echo \"memTestAddressBus: Checking for address bits stuck low or shorted...\"\n    memwrite32 $baseAddress $pattern\n    for {set testOffset 32} {[expr {$testOffset & $addressMask}] != 0} {set testOffset [expr {$testOffset << 1}] } {\n\tset addr [expr {$baseAddress + $testOffset}]\n\tmemwrite32 $addr $antipattern\n\n\tset data [memread32 $baseAddress]\n\tif {$data != $pattern} {\n\t    echo \"FAILED DATA_ADDR_BUS_SLOW: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]\"\n\t    return $pattern\n\t}\n\n\tfor {set offset 32} {[expr {$offset & $addressMask}] != 0} {set offset [expr {$offset << 1}]} {\n\t    set addr [expr {$baseAddress + $offset}]\n\t    set data [memread32 $baseAddress]\n\n            if {(($data != $pattern) && ($offset != $testOffset))} {\n\t\techo \"FAILED DATA_ADDR_BUS_SLOW2: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset], testOffset [convertToHex $testOffset]\"\n\t\treturn $pattern\n\t    }\n        }\n\tset addr [expr {$baseAddress + $testOffset}]\n\tmemwrite32 $addr $pattern\n    }\n}\n\n#***********************************************************************************\n# *\n# * Function:    memTestDevice()\n# *\n# * Description: Test the integrity of a physical memory device by\n# *              performing an increment/decrement test over the\n# *              entire region.  In the process every storage bit\n# *              in the device is tested as zero and as one.  The\n# *              base address and the size of the region are\n# *              selected by the caller.\n# *\t\t Ported from:\n# *\t\t http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C\n# * Notes:\n# *\n# * Returns:     Empty string if the test succeeds.\n# *              A non-zero result is the first address at which an\n# *              incorrect value was read back.  By examining the\n# *              contents of memory, it may be possible to gather\n# *              additional information about the problem.\n# *\n#***********************************************************************************\nproc memTestDevice { baseAddress nBytes } {\n    echo \"Running memTestDevice\"\n\n    echo \"memTestDevice: Filling memory with a known pattern...\"\n    for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {\n\tmemwrite32 [expr {$baseAddress + $offset}] $pattern\n    }\n\n    echo \"memTestDevice: Checking each location and inverting it for the second pass...\"\n    for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {\n\tset addr [expr {$baseAddress + $offset}]\n\tset data [memread32 $addr]\n\n\tif {$data != $pattern} {\n\t    echo \"FAILED memTestDevice_pattern: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset]\"\n\t    return $pattern\n\t}\n\n\tset antiPattern [expr {~$pattern}]\n\tmemwrite32 [expr {$baseAddress + $offset}] $antiPattern\n    }\n\n    echo \"memTestDevice: Checking each location for the inverted pattern and zeroing it...\"\n    for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {\n\tset antiPattern [expr {~$pattern & ((1<<32) - 1)}]\n\tset addr [expr {$baseAddress + $offset}]\n\tset data [memread32 $addr]\n\tset dataHex [convertToHex $data]\n\tset antiPatternHex [convertToHex $antiPattern]\n\tif {$dataHex != $antiPatternHex} {\n\t    echo \"FAILED memTestDevice_antipattern: Address: [convertToHex $addr], antiPattern: $antiPatternHex, Returned: $dataHex, offset: $offset\"\n\t    return $pattern\n\t}\n    }\n}\n\nproc convertToHex { value } {\n    format 0x%08x $value\n}\n"
  },
  {
    "path": "openocd-win/openocd/scripts/tools/test_cpu_speed.tcl",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n# Description:\n#  Measure the CPU clock frequency of an ARM Cortex-M based device.\n#\n# Return:\n#  The CPU clock frequency in Hz. A negative value indicates that the loop\n#  counter was saturated.\n#\n# Note:\n#  You may need to adapt the number of cycles for your device.\n#\nadd_help_text cortex_m_test_cpu_speed \"Measure the CPU clock frequency of an ARM Cortex-M based device\"\nadd_usage_text cortex_m_test_cpu_speed {address [timeout [cycles_per_loop]]}\nproc cortex_m_test_cpu_speed { address { timeout 200 } { cycles_per_loop 4 } } {\n\tset loop_counter_start 0xffffffff\n\n\thalt\n\n\t# Backup registers and memory.\n\tset backup_regs [get_reg -force {pc r0 xpsr}]\n\tset backup_mem [read_memory $address 16 3]\n\n\t# We place the following code at the given address to measure the\n\t# CPU clock frequency:\n\t#\n\t# 3801: subs r0, #1\n\t# d1fd: bne #-2\n\t# e7fe: b #-4\n\twrite_memory $address 16 {0x3801 0xd1fd 0xe7fe}\n\n\tset_reg \"pc $address r0 $loop_counter_start\"\n\tresume\n\tsleep $timeout\n\thalt\n\n\t# Get the loop counter value from register r0.\n\tset loop_counter_end [dict values [get_reg r0]]\n\tset loop_counter_diff [expr {$loop_counter_start - $loop_counter_end}]\n\n\t# Restore registers and memory.\n\tset_reg $backup_regs\n\twrite_memory $address 16 $backup_mem\n\n\tif { [expr {$loop_counter_end == 0}] } {\n\t\treturn -1\n\t}\n\n\treturn [expr {double($loop_counter_diff) * $cycles_per_loop / $timeout * 1000}]\n}\n"
  },
  {
    "path": "printf_config.h",
    "content": "#define PRINTF_DISABLE_SUPPORT_LONG_LONG\r\n#define PRINTF_DISABLE_SUPPORT_EXPONENTIAL\r\n#define PRINTF_DISABLE_SUPPORT_PTRDIFF_T\r\n#define PRINTF_DISABLE_SUPPORT_FLOAT\r\n"
  },
  {
    "path": "radio.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include \"driver/bk4819-regs.h\"\r\n#include \"driver/bk4819.h\"\r\n#include <stdint.h>\r\n#include \"app/mdc1200.h\"\r\n#include <string.h>\r\n#include \"am_fix.h\"\r\n#include \"app/dtmf.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"audio.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"dcs.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/gpio.h\"\r\n#include \"driver/system.h\"\r\n#include \"frequencies.h\"\r\n#include \"functions.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"settings.h\"\r\n#include \"ui/menu.h\"\r\n\r\n#ifdef ENABLE_MESSENGER\r\n#include \"app/messenger.h\"\r\n#endif\r\n#ifdef ENABLE_DOPPLER\r\n#include \"app/doppler.h\"\r\n#endif\r\nVFO_Info_t *gTxVfo;\r\nVFO_Info_t *gRxVfo;\r\nVFO_Info_t *gCurrentVfo;\r\nDCS_CodeType_t gCurrentCodeType;\r\nVfoState_t VfoState[2];\r\nconst char gModulationStr[MODULATION_UKNOWN][4] = {\r\n        [MODULATION_FM]=\"FM\",\r\n        [MODULATION_AM]=\"AM\",\r\n        [MODULATION_USB]=\"USB\",\r\n\r\n#ifdef ENABLE_BYP_RAW_DEMODULATORS\r\n        [MODULATION_BYP]=\"BYP\",\r\n    [MODULATION_RAW]=\"RAW\"\r\n#endif\r\n};\r\n\r\nvoid RADIO_SendEndOfTransmission(void) {\r\n    BK4819_PlayRoger();\r\n    DTMF_SendEndOfTransmission();\r\n\r\n    // send the CTCSS/DCS tail tone - allows the receivers to mute the usual FM squelch tail/crash\r\n    if (gEeprom.TAIL_TONE_ELIMINATION)\r\n        RADIO_SendCssTail();\r\n    RADIO_SetupRegisters(false);\r\n}\r\n\r\nbool RADIO_CheckValidChannel(uint16_t channel, bool checkScanList, uint8_t scanList) {\r\n    // return true if the channel appears valid\r\n    if (!IS_MR_CHANNEL(channel))\r\n        return false;\r\n\r\n    const ChannelAttributes_t att = gMR_ChannelAttributes[channel];\r\n\r\n    if (att.band > BAND7_470MHz)\r\n        return false;\r\n\r\n    if (!checkScanList || scanList > 1)\r\n        return true;\r\n\r\n    if (scanList ? !att.scanlist2 : !att.scanlist1)\r\n        return false;\r\n\r\n    const uint8_t PriorityCh1 = gEeprom.SCANLIST_PRIORITY_CH1[scanList];\r\n    const uint8_t PriorityCh2 = gEeprom.SCANLIST_PRIORITY_CH2[scanList];\r\n\r\n    return PriorityCh1 != channel && PriorityCh2 != channel;\r\n}\r\n\r\nuint8_t RADIO_FindNextChannel(uint8_t Channel, int8_t Direction, bool bCheckScanList, uint8_t VFO) {\r\n    unsigned int i;\r\n\r\n    for (i = 0; IS_MR_CHANNEL(i); i++) {\r\n        if (Channel == 0xFF)\r\n            Channel = MR_CHANNEL_LAST;\r\n        else if (!IS_MR_CHANNEL(Channel))\r\n            Channel = MR_CHANNEL_FIRST;\r\n\r\n        if (RADIO_CheckValidChannel(Channel, bCheckScanList, VFO))\r\n            return Channel;\r\n\r\n        Channel += Direction;\r\n    }\r\n\r\n    return 0xFF;\r\n}\r\n\r\nvoid RADIO_InitInfo(VFO_Info_t *pInfo, const uint8_t ChannelSave, const uint32_t Frequency) {\r\n    memset(pInfo, 0, sizeof(*pInfo));\r\n\r\n    pInfo->Band = FREQUENCY_GetBand(Frequency);\r\n    pInfo->SCANLIST1_PARTICIPATION = false;\r\n    pInfo->SCANLIST2_PARTICIPATION = false;\r\n    pInfo->STEP_SETTING = STEP_12_5kHz;\r\n    pInfo->StepFrequency = gStepFrequencyTable[pInfo->STEP_SETTING];\r\n    pInfo->CHANNEL_SAVE = ChannelSave;\r\n    pInfo->FrequencyReverse = 0;\r\n    pInfo->OUTPUT_POWER = OUTPUT_POWER_LOW;\r\n    pInfo->freq_config_RX.Frequency = Frequency;\r\n    pInfo->freq_config_TX.Frequency = Frequency;\r\n    pInfo->pRX = &pInfo->freq_config_RX;\r\n    pInfo->pTX = &pInfo->freq_config_TX;\r\n    pInfo->Compander = 0;  // off\r\n\r\n    if (ChannelSave == (FREQ_CHANNEL_FIRST + BAND2_108MHz))\r\n        pInfo->Modulation = MODULATION_AM;\r\n    else\r\n        pInfo->Modulation = MODULATION_FM;\r\n\r\n    RADIO_ConfigureSquelchAndOutputPower(pInfo);\r\n}\r\n\r\nvoid RADIO_ConfigureChannel(const unsigned int VFO, const unsigned int configure) {\r\n    VFO_Info_t *pVfo = &gEeprom.VfoInfo[VFO];\r\n\r\n//    if (!gSetting_350EN) {\r\n//        if (gEeprom.FreqChannel[VFO] == FREQ_CHANNEL_FIRST + BAND5_350MHz)\r\n//            gEeprom.FreqChannel[VFO] = FREQ_CHANNEL_FIRST + BAND6_400MHz;\r\n//\r\n//        if (gEeprom.ScreenChannel[VFO] == FREQ_CHANNEL_FIRST + BAND5_350MHz)\r\n//            gEeprom.ScreenChannel[VFO] = FREQ_CHANNEL_FIRST + BAND6_400MHz;\r\n//    }\r\n\r\n    uint8_t channel = gEeprom.ScreenChannel[VFO];\r\n\r\n    if (IS_VALID_CHANNEL(channel)) {\r\n#ifdef ENABLE_NOAA\r\n        if (IS_NOAA_CHANNEL(channel))\r\n        {\r\n            RADIO_InitInfo(pVfo, gEeprom.ScreenChannel[VFO], NoaaFrequencyTable[channel - NOAA_CHANNEL_FIRST]);\r\n\r\n            if (gEeprom.CROSS_BAND_RX_TX == CROSS_BAND_OFF)\r\n                return;\r\n\r\n            gEeprom.CROSS_BAND_RX_TX = CROSS_BAND_OFF;\r\n\r\n            gUpdateStatus = true;\r\n            return;\r\n        }\r\n#endif\r\n\r\n        if (IS_MR_CHANNEL(channel)) {\r\n            channel = RADIO_FindNextChannel(channel, RADIO_CHANNEL_UP, false, VFO);\r\n            if (channel == 0xFF) {\r\n                channel = gEeprom.FreqChannel[VFO];\r\n                gEeprom.ScreenChannel[VFO] = gEeprom.FreqChannel[VFO];\r\n            } else {\r\n                gEeprom.ScreenChannel[VFO] = channel;\r\n                gEeprom.MrChannel[VFO] = channel;\r\n            }\r\n        }\r\n    } else\r\n        channel = FREQ_CHANNEL_LAST - 1;\r\n\r\n    ChannelAttributes_t att = gMR_ChannelAttributes[channel];\r\n    if (att.__val == 0xFF) { // invalid/unused channel\r\n        if (IS_MR_CHANNEL(channel)) {\r\n            channel = gEeprom.FreqChannel[VFO];\r\n            gEeprom.ScreenChannel[VFO] = channel;\r\n        }\r\n\r\n        uint8_t bandIdx = channel - FREQ_CHANNEL_FIRST;\r\n        RADIO_InitInfo(pVfo, channel, frequencyBandTable[bandIdx].lower);\r\n        return;\r\n    }\r\n\r\n    uint8_t band = att.band;\r\n    if (band > BAND7_470MHz) {\r\n        band = BAND6_400MHz;\r\n    }\r\n\r\n    bool bParticipation1;\r\n    bool bParticipation2;\r\n    if (IS_MR_CHANNEL(channel)) {\r\n        bParticipation1 = att.scanlist1;\r\n        bParticipation2 = att.scanlist2;\r\n    } else {\r\n        band = channel - FREQ_CHANNEL_FIRST;\r\n        bParticipation1 = true;\r\n        bParticipation2 = true;\r\n    }\r\n\r\n    pVfo->Band = band;\r\n    pVfo->SCANLIST1_PARTICIPATION = bParticipation1;\r\n    pVfo->SCANLIST2_PARTICIPATION = bParticipation2;\r\n    pVfo->CHANNEL_SAVE = channel;\r\n\r\n    uint16_t base;\r\n    if (IS_MR_CHANNEL(channel))\r\n        base = channel * 16;\r\n    else\r\n        base = 0x0C80 + ((channel - FREQ_CHANNEL_FIRST) * 32) + (VFO * 16);\r\n\r\n    if (configure == VFO_CONFIGURE_RELOAD || IS_FREQ_CHANNEL(channel)) {\r\n        uint8_t tmp;\r\n        uint8_t data[8];\r\n\r\n        // ***************\r\n\r\n        EEPROM_ReadBuffer(base + 8, data, sizeof(data));\r\n\r\n        tmp = data[3] & 0x0F;\r\n        if (tmp > TX_OFFSET_FREQUENCY_DIRECTION_SUB)\r\n            tmp = 0;\r\n        pVfo->TX_OFFSET_FREQUENCY_DIRECTION = tmp;\r\n        tmp = data[3] >> 4;\r\n        if (tmp >= MODULATION_UKNOWN)\r\n            tmp = MODULATION_FM;\r\n        pVfo->Modulation = tmp;\r\n\r\n        tmp = data[6];\r\n        if (tmp >= STEP_N_ELEM)\r\n            tmp = STEP_12_5kHz;\r\n        pVfo->STEP_SETTING = tmp;\r\n        pVfo->StepFrequency = gStepFrequencyTable[tmp];\r\n\r\n        tmp = data[7];\r\n        if (tmp > (ARRAY_SIZE(gSubMenu_SCRAMBLER) - 1))\r\n            tmp = 0;\r\n        pVfo->SCRAMBLING_TYPE = tmp;\r\n\r\n        pVfo->freq_config_RX.CodeType = (data[2] >> 0) & 0x0F;\r\n        pVfo->freq_config_TX.CodeType = (data[2] >> 4) & 0x0F;\r\n\r\n        tmp = data[0];\r\n        switch (pVfo->freq_config_RX.CodeType) {\r\n            default:\r\n            case CODE_TYPE_OFF:\r\n                pVfo->freq_config_RX.CodeType = CODE_TYPE_OFF;\r\n                tmp = 0;\r\n                break;\r\n\r\n            case CODE_TYPE_CONTINUOUS_TONE:\r\n                if (tmp > (50 - 1))\r\n                    tmp = 0;\r\n                break;\r\n\r\n            case CODE_TYPE_DIGITAL:\r\n            case CODE_TYPE_REVERSE_DIGITAL:\r\n                if (tmp > (104 - 1))\r\n                    tmp = 0;\r\n                break;\r\n        }\r\n        pVfo->freq_config_RX.Code = tmp;\r\n\r\n        tmp = data[1];\r\n        switch (pVfo->freq_config_TX.CodeType) {\r\n            default:\r\n            case CODE_TYPE_OFF:\r\n                pVfo->freq_config_TX.CodeType = CODE_TYPE_OFF;\r\n                tmp = 0;\r\n                break;\r\n\r\n            case CODE_TYPE_CONTINUOUS_TONE:\r\n                if (tmp > (50 - 1))\r\n                    tmp = 0;\r\n                break;\r\n\r\n            case CODE_TYPE_DIGITAL:\r\n            case CODE_TYPE_REVERSE_DIGITAL:\r\n                if (tmp > (104 - 1))\r\n                    tmp = 0;\r\n                break;\r\n        }\r\n        pVfo->freq_config_TX.Code = tmp;\r\n\r\n        if (data[4] == 0xFF) {\r\n            pVfo->FrequencyReverse = 0;\r\n            pVfo->CHANNEL_BANDWIDTH = BK4819_FILTER_BW_WIDE;\r\n            pVfo->OUTPUT_POWER = OUTPUT_POWER_LOW;\r\n            pVfo->BUSY_CHANNEL_LOCK = false;\r\n        } else {\r\n            const uint8_t d4 = data[4];\r\n            pVfo->FrequencyReverse = d4 >> 5 & 1u ? d4 >> 6 & 3u : d4 & 1u;\r\n            pVfo->CHANNEL_BANDWIDTH = !!((d4 >> 1) & 1u);\r\n            pVfo->OUTPUT_POWER = ((d4 >> 2) & 3u);\r\n            pVfo->BUSY_CHANNEL_LOCK = !!((d4 >> 4) & 1u);\r\n        }\r\n\r\n        if (data[5] == 0xFF) {\r\n#ifdef ENABLE_DTMF_CALLING\r\n            pVfo->DTMF_DECODING_ENABLE = false;\r\n#endif\r\n            pVfo->DTMF_PTT_ID_TX_MODE = PTT_ID_OFF;\r\n        } else {\r\n#ifdef ENABLE_DTMF_CALLING\r\n            pVfo->DTMF_DECODING_ENABLE = ((data[5] >> 0) & 1u) ? true : false;\r\n#endif\r\n            uint8_t pttId = ((data[5] >> 1) & 7u);\r\n            pVfo->DTMF_PTT_ID_TX_MODE = pttId < ARRAY_SIZE(gSubMenu_PTT_ID) ? pttId : PTT_ID_OFF;\r\n        }\r\n\r\n        // ***************\r\n\r\n        struct {\r\n            uint32_t Frequency;\r\n            uint32_t Offset;\r\n        } __attribute__((packed)) info;\r\n        EEPROM_ReadBuffer(base, &info, sizeof(info));\r\n        if (info.Frequency == 0xFFFFFFFF)\r\n            pVfo->freq_config_RX.Frequency = frequencyBandTable[band].lower;\r\n        else\r\n            pVfo->freq_config_RX.Frequency = info.Frequency;\r\n\r\n        if (info.Offset >= _1GHz_in_KHz)\r\n            info.Offset = _1GHz_in_KHz / 100;\r\n        pVfo->TX_OFFSET_FREQUENCY = info.Offset;\r\n\r\n        // ***************\r\n    }\r\n\r\n    uint32_t frequency = pVfo->freq_config_RX.Frequency;\r\n\r\n    // fix previously set incorrect band\r\n    band = FREQUENCY_GetBand(frequency);\r\n\r\n    if (frequency < frequencyBandTable[band].lower)\r\n        frequency = frequencyBandTable[band].lower;\r\n    else if (frequency > frequencyBandTable[band].upper)\r\n        frequency = frequencyBandTable[band].upper;\r\n    else if (channel >= FREQ_CHANNEL_FIRST)\r\n        frequency = FREQUENCY_RoundToStep(frequency, pVfo->StepFrequency);\r\n\r\n    pVfo->freq_config_RX.Frequency = frequency;\r\n\r\n    if (frequency >= frequencyBandTable[BAND2_108MHz].upper && frequency < frequencyBandTable[BAND2_108MHz].upper)\r\n        pVfo->TX_OFFSET_FREQUENCY_DIRECTION = TX_OFFSET_FREQUENCY_DIRECTION_OFF;\r\n    else if (!IS_MR_CHANNEL(channel))\r\n        pVfo->TX_OFFSET_FREQUENCY = FREQUENCY_RoundToStep(pVfo->TX_OFFSET_FREQUENCY, pVfo->StepFrequency);\r\n\r\n    RADIO_ApplyOffset(pVfo);\r\n\r\n    if (IS_MR_CHANNEL(channel)) {    // 16 bytes allocated to the channel name but only 10 used, the rest are 0's\r\n\r\n\r\n        SETTINGS_FetchChannelName(pVfo->Name, channel);\r\n    }\r\n\r\n    if (pVfo->FrequencyReverse == 0) {\r\n        pVfo->pRX = &pVfo->freq_config_RX;\r\n        pVfo->pTX = &pVfo->freq_config_TX;\r\n    } else if (pVfo->FrequencyReverse == 1) {\r\n        pVfo->pRX = &pVfo->freq_config_TX;\r\n        pVfo->pTX = &pVfo->freq_config_RX;\r\n    } else {\r\n        pVfo->pRX = &pVfo->freq_config_RX;\r\n        pVfo->pTX = &pVfo->freq_config_RX;\r\n    }\r\n\r\n//    if (!gSetting_350EN)\r\n//    {\r\n//        FREQ_Config_t *pConfig = pVfo->pRX;\r\n//        if (pConfig->Frequency >= 35000000 && pConfig->Frequency < 40000000)\r\n//            pConfig->Frequency = 43300000;\r\n//    }\r\n\r\n\r\n//    else{\r\n//\r\n//         FREQ_Config_t *pConfig =  gEeprom.VfoInfo[1].pRX;\r\n//         unsigned int code_type = pConfig->CodeType;\r\n//\r\n//\r\n//        pVfo->freq_config_RX.CodeType=  code_type;\r\n//        pVfo->freq_config_TX.CodeType=   code_type;\r\n//\r\n//    }\r\n\r\n    pVfo->Compander = att.compander;\r\n\r\n    RADIO_ConfigureSquelchAndOutputPower(pVfo);\r\n}\r\n\r\nvoid RADIO_ConfigureSquelchAndOutputPower(VFO_Info_t *pInfo) {\r\n\r\n\r\n    // *******************************\r\n    // squelch\r\n\r\n    FREQUENCY_Band_t Band = FREQUENCY_GetBand(pInfo->pRX->Frequency);\r\n    uint16_t Base = (Band < BAND4_174MHz) ? 0x1E60 : 0x1E00;\r\n\r\n    if (gEeprom.SQUELCH_LEVEL == 0) {    // squelch == 0 (off)\r\n        pInfo->SquelchOpenRSSIThresh = 0;     // 0 ~ 255\r\n        pInfo->SquelchOpenNoiseThresh = 127;   // 127 ~ 0\r\n        pInfo->SquelchCloseGlitchThresh = 255;   // 255 ~ 0\r\n\r\n        pInfo->SquelchCloseRSSIThresh = 0;     // 0 ~ 255\r\n        pInfo->SquelchCloseNoiseThresh = 127;   // 127 ~ 0\r\n        pInfo->SquelchOpenGlitchThresh = 255;   // 255 ~ 0\r\n    } else {    // squelch >= 1\r\n        Base += gEeprom.SQUELCH_LEVEL;                                        // my eeprom squelch-1\r\n        // VHF   UHF\r\n        EEPROM_ReadBuffer(Base + 0x00, &pInfo->SquelchOpenRSSIThresh, 1);  //  50    10\r\n        EEPROM_ReadBuffer(Base + 0x10, &pInfo->SquelchCloseRSSIThresh, 1);  //  40     5\r\n\r\n        EEPROM_ReadBuffer(Base + 0x20, &pInfo->SquelchOpenNoiseThresh, 1);  //  65    90\r\n        EEPROM_ReadBuffer(Base + 0x30, &pInfo->SquelchCloseNoiseThresh, 1);  //  70   100\r\n\r\n        EEPROM_ReadBuffer(Base + 0x40, &pInfo->SquelchCloseGlitchThresh, 1);  //  90    90\r\n        EEPROM_ReadBuffer(Base + 0x50, &pInfo->SquelchOpenGlitchThresh, 1);  // 100   100\r\n\r\n\r\n\r\n\r\n\r\n#if ENABLE_SQUELCH_MORE_SENSITIVE\r\n\r\n        uint8_t num=4;\r\n        uint8_t num_noise=4;\r\n        // make squelch more sensitive\r\n        // note that 'noise' and 'glitch' values are inverted compared to 'rssi' values\r\n        pInfo->SquelchOpenRSSIThresh = (pInfo->SquelchOpenRSSIThresh * 1) / num;\r\n        pInfo->SquelchOpenNoiseThresh = (pInfo->SquelchOpenNoiseThresh * num_noise) / 1;\r\n        pInfo->SquelchOpenGlitchThresh = (pInfo->SquelchOpenGlitchThresh * num_noise) / 1;\r\n\r\n\r\n        pInfo->SquelchCloseRSSIThresh = ( pInfo->SquelchCloseRSSIThresh * 1) / num;\r\n        pInfo->SquelchCloseNoiseThresh = (pInfo->SquelchCloseNoiseThresh * num_noise) / 1;\r\n        pInfo->SquelchCloseGlitchThresh = (pInfo->SquelchCloseGlitchThresh * num_noise) / 1;\r\n\r\n\r\n        pInfo->SquelchOpenRSSIThresh = (pInfo->SquelchOpenRSSIThresh > 255) ? 255 : pInfo->SquelchOpenRSSIThresh;\r\n        pInfo->SquelchCloseRSSIThresh = ( pInfo->SquelchCloseRSSIThresh > 255) ? 255 :  pInfo->SquelchCloseRSSIThresh;\r\n        pInfo->SquelchOpenNoiseThresh = (pInfo->SquelchOpenNoiseThresh > 127) ? 127 : pInfo->SquelchOpenNoiseThresh;\r\n        pInfo->SquelchCloseNoiseThresh = (pInfo->SquelchCloseNoiseThresh > 127) ? 127 : pInfo->SquelchCloseNoiseThresh;\r\n        pInfo->SquelchOpenGlitchThresh = (pInfo->SquelchOpenGlitchThresh > 255) ? 255 : pInfo->SquelchOpenGlitchThresh;\r\n        pInfo->SquelchCloseGlitchThresh = (pInfo->SquelchCloseGlitchThresh > 255) ? 255 : pInfo->SquelchCloseGlitchThresh;\r\n\r\n\r\n        // ensure the 'close' threshold is lower than the 'open' threshold\r\n        if ( pInfo->SquelchCloseRSSIThresh + 4 >= pInfo->SquelchOpenRSSIThresh)\r\n            if (pInfo->SquelchOpenRSSIThresh >= 4)\r\n                 pInfo->SquelchCloseRSSIThresh = pInfo->SquelchOpenRSSIThresh - 4;\r\n            else\r\n                pInfo->SquelchOpenRSSIThresh =  pInfo->SquelchCloseRSSIThresh + 4;\r\n            \r\n        if (pInfo->SquelchCloseGlitchThresh - 2 <= pInfo->SquelchOpenGlitchThresh)\r\n            if (pInfo->SquelchOpenGlitchThresh <= 253)\r\n                pInfo->SquelchCloseGlitchThresh = pInfo->SquelchOpenGlitchThresh + 2;\r\n            else\r\n                pInfo->SquelchOpenGlitchThresh = pInfo->SquelchCloseGlitchThresh - 2;\r\n\r\n        if (pInfo->SquelchCloseNoiseThresh - 2 <= pInfo->SquelchOpenNoiseThresh)\r\n            if (pInfo->SquelchOpenNoiseThresh <= 125)\r\n                pInfo->SquelchCloseNoiseThresh = pInfo->SquelchOpenNoiseThresh + 2;\r\n            else\r\n                pInfo->SquelchOpenNoiseThresh = pInfo->SquelchCloseNoiseThresh - 2;\r\n\r\n//\r\n//        pInfo->SquelchOpenRSSIThresh    = (pInfo->SquelchOpenRSSIThresh    > 255) ? 255 : pInfo->SquelchOpenRSSIThresh;\r\n//        pInfo->SquelchCloseRSSIThresh   = ( pInfo->SquelchCloseRSSIThresh   > 255) ? 255 :  pInfo->SquelchCloseRSSIThresh;\r\n//\r\n//        pInfo->SquelchOpenGlitchThresh  = (pInfo->SquelchOpenGlitchThresh  > 255) ? 255 : pInfo->SquelchOpenGlitchThresh;\r\n//        pInfo->SquelchCloseGlitchThresh = (pInfo->SquelchCloseGlitchThresh > 255) ? 255 : pInfo->SquelchCloseGlitchThresh;\r\n\r\n#else\r\n        pInfo->SquelchOpenNoiseThresh = (pInfo->SquelchOpenNoiseThresh > 127) ? 127 : pInfo->SquelchOpenNoiseThresh;\r\n        pInfo->SquelchCloseNoiseThresh = (pInfo->SquelchCloseNoiseThresh > 127) ? 127 : pInfo->SquelchCloseNoiseThresh;\r\n#endif\r\n    }\r\n    // *******************************\r\n    // output power\r\n\r\n    Band = FREQUENCY_GetBand(pInfo->pTX->Frequency);\r\n    uint8_t Txp[3];\r\n    EEPROM_ReadBuffer(0x1ED0 + (Band * 16) + (pInfo->OUTPUT_POWER * 3), Txp, 3);\r\n\r\n\r\n#ifdef ENABLE_REDUCE_LOW_MID_TX_POWER\r\n    // make low and mid even lower\r\n    if (pInfo->OUTPUT_POWER == OUTPUT_POWER_LOW) {\r\n        Txp[0] /= 5;\r\n        Txp[1] /= 5;\r\n        Txp[2] /= 5;\r\n    }\r\n    else if (pInfo->OUTPUT_POWER == OUTPUT_POWER_MID){\r\n        Txp[0] /= 3;\r\n        Txp[1] /= 3;\r\n        Txp[2] /= 3;\r\n    }\r\n#endif\r\n\r\n    pInfo->TXP_CalculatedSetting = FREQUENCY_CalculateOutputPower(\r\n            Txp[0],\r\n            Txp[1],\r\n            Txp[2],\r\n            frequencyBandTable[Band].lower,\r\n            (frequencyBandTable[Band].lower + frequencyBandTable[Band].upper) / 2,\r\n            frequencyBandTable[Band].upper,\r\n            pInfo->pTX->Frequency);\r\n\r\n    // *******************************\r\n}\r\n\r\nvoid RADIO_ApplyOffset(VFO_Info_t *pInfo) {\r\n    uint32_t Frequency = pInfo->freq_config_RX.Frequency;\r\n\r\n    switch (pInfo->TX_OFFSET_FREQUENCY_DIRECTION) {\r\n        case TX_OFFSET_FREQUENCY_DIRECTION_OFF:\r\n            break;\r\n        case TX_OFFSET_FREQUENCY_DIRECTION_ADD:\r\n            Frequency += pInfo->TX_OFFSET_FREQUENCY;\r\n            break;\r\n        case TX_OFFSET_FREQUENCY_DIRECTION_SUB:\r\n            Frequency -= pInfo->TX_OFFSET_FREQUENCY;\r\n            break;\r\n    }\r\n\r\n\r\n    pInfo->freq_config_TX.Frequency = Frequency;\r\n}\r\n\r\nstatic void RADIO_SelectCurrentVfo(void) {\r\n    // if crossband is active and DW not the gCurrentVfo is gTxVfo (gTxVfo/TX_VFO is only ever changed by the user)\r\n    // otherwise it is set to gRxVfo which is set to gTxVfo in RADIO_SelectVfos\r\n    // so in the end gCurrentVfo is equal to gTxVfo unless dual watch changes it on incomming transmition (again, this can only happen when XB off)\r\n    // note: it is called only in certain situations so could be not up-to-date\r\n    gCurrentVfo = (gEeprom.CROSS_BAND_RX_TX == CROSS_BAND_OFF || gEeprom.DUAL_WATCH != DUAL_WATCH_OFF) ? gRxVfo\r\n                                                                                                       : gTxVfo;\r\n}\r\n\r\nvoid RADIO_SelectVfos(void) {\r\n    // if crossband without DW is used then RX_VFO is the opposite to the TX_VFO\r\n    gEeprom.RX_VFO = (gEeprom.CROSS_BAND_RX_TX == CROSS_BAND_OFF || gEeprom.DUAL_WATCH != DUAL_WATCH_OFF)\r\n                     ? gEeprom.TX_VFO : !gEeprom.TX_VFO;\r\n\r\n    gTxVfo = &gEeprom.VfoInfo[gEeprom.TX_VFO];\r\n    gRxVfo = &gEeprom.VfoInfo[gEeprom.RX_VFO];\r\n\r\n    RADIO_SelectCurrentVfo();\r\n}\r\n\r\nvoid RADIO_SetupRegisters(bool switchToForeground) {\r\n    BK4819_FilterBandwidth_t Bandwidth = gRxVfo->CHANNEL_BANDWIDTH;\r\n    uint16_t InterruptMask;\r\n    uint32_t Frequency;\r\n#if ENABLE_CHINESE_FULL==4 && !defined(ENABLE_ENGLISH)\r\n    uint8_t read_tmp[2];\r\n#endif\r\n    AUDIO_AudioPathOff();\r\n\r\n    gEnableSpeaker = false;\r\n\r\n    BK4819_ToggleGpioOut(BK4819_GPIO6_PIN2_GREEN, false);\r\n\r\n    switch (Bandwidth) {\r\n        default:\r\n            Bandwidth = BK4819_FILTER_BW_WIDE;\r\n            [[fallthrough]];\r\n        case BK4819_FILTER_BW_WIDE:\r\n        case BK4819_FILTER_BW_NARROW:\r\n#ifdef ENABLE_AM_FIX\r\n            //\t\t\t\tBK4819_SetFilterBandwidth(Bandwidth, gRxVfo->Modulation == MODULATION_AM && gSetting_AM_fix);\r\n                BK4819_SetFilterBandwidth(Bandwidth, true);\r\n#else\r\n            BK4819_SetFilterBandwidth(Bandwidth, false);\r\n#endif\r\n            break;\r\n    }\r\n\r\n    BK4819_ToggleGpioOut(BK4819_GPIO5_PIN1_RED, false);\r\n\r\n    BK4819_SetupPowerAmplifier(0, 0);\r\n\r\n    BK4819_ToggleGpioOut(BK4819_GPIO1_PIN29_PA_ENABLE, false);\r\n\r\n    while (1) {\r\n        const uint16_t Status = BK4819_ReadRegister(BK4819_REG_0C);\r\n        if ((Status & 1u) == 0) // INTERRUPT REQUEST\r\n            break;\r\n\r\n        BK4819_WriteRegister(BK4819_REG_02, 0);\r\n        SYSTEM_DelayMs(1);\r\n    }\r\n    BK4819_WriteRegister(BK4819_REG_3F, 0);\r\n\r\n    // mic gain 0.5dB/step 0 to 31\r\n    BK4819_WriteRegister(BK4819_REG_7D, 0xE940 | (gEeprom.MIC_SENSITIVITY_TUNING & 0x1f));\r\n\r\n#ifdef ENABLE_NOAA\r\n    if (!IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE) || !gIsNoaaMode)\r\n            Frequency = gRxVfo->pRX->Frequency;\r\n        else\r\n            Frequency = NoaaFrequencyTable[gNoaaChannel];\r\n#else\r\n    Frequency = gRxVfo->pRX->Frequency;\r\n#endif\r\n    BK4819_SetFrequency(Frequency);\r\n\r\n    BK4819_SetupSquelch(\r\n            gRxVfo->SquelchOpenRSSIThresh, gRxVfo->SquelchCloseRSSIThresh,\r\n            gRxVfo->SquelchOpenNoiseThresh, gRxVfo->SquelchCloseNoiseThresh,\r\n            gRxVfo->SquelchCloseGlitchThresh, gRxVfo->SquelchOpenGlitchThresh);\r\n\r\n    BK4819_PickRXFilterPathBasedOnFrequency(Frequency);\r\n\r\n    // what does this in do ?\r\n    BK4819_ToggleGpioOut(BK4819_GPIO0_PIN28_RX_ENABLE, true);\r\n\r\n    // AF RX Gain and DAC\r\n    //BK4819_WriteRegister(BK4819_REG_48, 0xB3A8);  // 1011 00 111010 1000\r\n    BK4819_WriteRegister(BK4819_REG_48,\r\n                         (11u << 12) |     // ??? .. 0 ~ 15, doesn't seem to make any difference\r\n                         (0u << 10) |     // AF Rx Gain-1\r\n                         (gEeprom.VOLUME_GAIN << 4) |     // AF Rx Gain-2\r\n                         (gEeprom.DAC_GAIN << 0));     // AF DAC Gain (after Gain-1 and Gain-2)\r\n\r\n\r\n    InterruptMask = BK4819_REG_3F_SQUELCH_FOUND | BK4819_REG_3F_SQUELCH_LOST;\r\n\r\n#ifdef ENABLE_NOAA\r\n    if (!IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE))\r\n#endif\r\n    {\r\n        if (gRxVfo->Modulation == MODULATION_FM) {    // FM\r\n            uint8_t CodeType = gRxVfo->pRX->CodeType;\r\n            uint8_t Code = gRxVfo->pRX->Code;\r\n\r\n            switch (CodeType) {\r\n                default:\r\n                case CODE_TYPE_OFF:\r\n                    BK4819_SetCTCSSFrequency(670);\r\n\r\n                    //#ifndef ENABLE_CTCSS_TAIL_PHASE_SHIFT\r\n                    BK4819_SetTailDetection(550);        // QS's 55Hz tone method\r\n                    //#else\r\n                    //\tBK4819_SetTailDetection(670);       // 67Hz\r\n                    //#endif\r\n\r\n                    InterruptMask = BK4819_REG_3F_CxCSS_TAIL | BK4819_REG_3F_SQUELCH_FOUND | BK4819_REG_3F_SQUELCH_LOST;\r\n                    break;\r\n\r\n                case CODE_TYPE_CONTINUOUS_TONE:\r\n\r\n#if ENABLE_CHINESE_FULL == 0 ||defined(ENABLE_ENGLISH)\r\n                    BK4819_SetCTCSSFrequency(CTCSS_Options[Code]);\r\n#else\r\n                    EEPROM_ReadBuffer(0x02C00+(Code)*2, read_tmp, 2);\r\n                    uint16_t CTCSS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\n                                BK4819_SetCTCSSFrequency(CTCSS_Options_read);\r\n\r\n#endif\r\n                    //#ifndef ENABLE_CTCSS_TAIL_PHASE_SHIFT\r\n                    BK4819_SetTailDetection(550);        // QS's 55Hz tone method\r\n                    //#else\r\n                    //\tBK4819_SetTailDetection(CTCSS_Options[Code]);\r\n                    //#endif\r\n\r\n                    InterruptMask = 0\r\n                                    | BK4819_REG_3F_CxCSS_TAIL\r\n                                    | BK4819_REG_3F_CTCSS_FOUND\r\n                                    | BK4819_REG_3F_CTCSS_LOST\r\n                                    | BK4819_REG_3F_SQUELCH_FOUND\r\n                                    | BK4819_REG_3F_SQUELCH_LOST;\r\n\r\n                    break;\r\n\r\n                case CODE_TYPE_DIGITAL:\r\n                case CODE_TYPE_REVERSE_DIGITAL:\r\n                    BK4819_SetCDCSSCodeWord(DCS_GetGolayCodeWord(CodeType, Code));\r\n                    InterruptMask = 0\r\n                                    | BK4819_REG_3F_CxCSS_TAIL\r\n                                    | BK4819_REG_3F_CDCSS_FOUND\r\n                                    | BK4819_REG_3F_CDCSS_LOST\r\n                                    | BK4819_REG_3F_SQUELCH_FOUND\r\n                                    | BK4819_REG_3F_SQUELCH_LOST;\r\n                    break;\r\n            }\r\n\r\n            if (gRxVfo->SCRAMBLING_TYPE > 0 && gSetting_ScrambleEnable)\r\n                BK4819_EnableScramble(gRxVfo->SCRAMBLING_TYPE - 1);\r\n            else\r\n                BK4819_DisableScramble();\r\n        }\r\n    }\r\n#ifdef ENABLE_NOAA\r\n    else\r\n        {\r\n            BK4819_SetCTCSSFrequency(2625);\r\n            InterruptMask = 0\r\n                | BK4819_REG_3F_CTCSS_FOUND\r\n                | BK4819_REG_3F_CTCSS_LOST\r\n                | BK4819_REG_3F_SQUELCH_FOUND\r\n                | BK4819_REG_3F_SQUELCH_LOST;\r\n        }\r\n#endif\r\n\r\n#ifdef ENABLE_VOX\r\n    if (gEeprom.VOX_SWITCH  && gCurrentVfo->Modulation == MODULATION_FM\r\n#ifdef ENABLE_NOAA\r\n        && !IS_NOAA_CHANNEL(gCurrentVfo->CHANNEL_SAVE)\r\n#endif\r\n#ifdef ENABLE_FMRADIO\r\n        && !gFmRadioMode\r\n#endif\r\n    ){\r\n        BK4819_EnableVox(gEeprom.VOX1_THRESHOLD, gEeprom.VOX0_THRESHOLD);\r\n        InterruptMask |= BK4819_REG_3F_VOX_FOUND | BK4819_REG_3F_VOX_LOST;\r\n    }\r\n    else\r\n#endif\r\n    {\r\n        BK4819_DisableVox();\r\n    }\r\n    // RX expander\r\n    BK4819_SetCompander((gRxVfo->Modulation == MODULATION_FM && gRxVfo->Compander >= 2) ? gRxVfo->Compander : 0);\r\n\r\n    BK4819_EnableDTMF();\r\n    InterruptMask |= BK4819_REG_3F_DTMF_5TONE_FOUND;\r\n    RADIO_SetupAGC(gRxVfo->Modulation == MODULATION_AM, false);\r\n    // enable/disable BK4819 selected interrupts\r\n\r\n    //OK?\r\n#if defined(ENABLE_MESSENGER) || defined(ENABLE_MDC1200)\r\n    enable_msg_rx(true);\r\n#endif\r\n#ifdef ENABLE_MESSENGER\r\n    InterruptMask |= BK4819_REG_3F_FSK_RX_SYNC | BK4819_REG_3F_FSK_RX_FINISHED | BK4819_REG_3F_FSK_FIFO_ALMOST_FULL | BK4819_REG_3F_FSK_TX_FINISHED;\r\n\r\n#elif defined(ENABLE_MDC1200)\r\n    InterruptMask |= BK4819_REG_3F_FSK_RX_SYNC | BK4819_REG_3F_FSK_RX_FINISHED | BK4819_REG_3F_FSK_FIFO_ALMOST_FULL;\r\n#endif\r\n    BK4819_WriteRegister(BK4819_REG_3F, InterruptMask);\r\n\r\n    FUNCTION_Init();\r\n\r\n    if (switchToForeground)\r\n        FUNCTION_Select(FUNCTION_FOREGROUND);\r\n}\r\n\r\n#ifdef ENABLE_NOAA\r\nvoid RADIO_ConfigureNOAA(void)\r\n    {\r\n        uint8_t ChanAB;\r\n\r\n        gUpdateStatus = true;\r\n\r\n        if (gEeprom.NOAA_AUTO_SCAN)\r\n        {\r\n            if (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF)\r\n            {\r\n                if (!IS_NOAA_CHANNEL(gEeprom.ScreenChannel[0]))\r\n                {\r\n                    if (!IS_NOAA_CHANNEL(gEeprom.ScreenChannel[1]))\r\n                    {\r\n                        gIsNoaaMode = false;\r\n                        return;\r\n                    }\r\n                    ChanAB = 1;\r\n                }\r\n                else\r\n                    ChanAB = 0;\r\n\r\n                if (!gIsNoaaMode)\r\n                    gNoaaChannel = gEeprom.VfoInfo[ChanAB].CHANNEL_SAVE - NOAA_CHANNEL_FIRST;\r\n\r\n                gIsNoaaMode = true;\r\n                return;\r\n            }\r\n\r\n            if (IS_NOAA_CHANNEL(gRxVfo->CHANNEL_SAVE))\r\n            {\r\n                gIsNoaaMode          = true;\r\n                gNoaaChannel         = gRxVfo->CHANNEL_SAVE - NOAA_CHANNEL_FIRST;\r\n                gNOAA_Countdown_10ms = NOAA_countdown_2_10ms;\r\n                gScheduleNOAA        = false;\r\n            }\r\n            else\r\n                gIsNoaaMode = false;\r\n        }\r\n        else\r\n            gIsNoaaMode = false;\r\n    }\r\n#endif\r\n\r\nvoid RADIO_SetTxParameters(void) {\r\n#if ENABLE_CHINESE_FULL==4 && !defined(ENABLE_ENGLISH)\r\n\r\n    uint8_t read_tmp[2];\r\n#endif\r\n    BK4819_FilterBandwidth_t Bandwidth = gCurrentVfo->CHANNEL_BANDWIDTH;\r\n    AUDIO_AudioPathOff();\r\n\r\n    gEnableSpeaker = false;\r\n\r\n    BK4819_ToggleGpioOut(BK4819_GPIO0_PIN28_RX_ENABLE, false);\r\n\r\n    switch (Bandwidth) {\r\n        default:\r\n            Bandwidth = BK4819_FILTER_BW_WIDE;\r\n            [[fallthrough]];\r\n        case BK4819_FILTER_BW_WIDE:\r\n        case BK4819_FILTER_BW_NARROW:\r\n#ifdef ENABLE_AM_FIX\r\n            //\t\t\t\tBK4819_SetFilterBandwidth(Bandwidth, gCurrentVfo->Modulation == MODULATION_AM && gSetting_AM_fix);\r\n                BK4819_SetFilterBandwidth(Bandwidth, true);\r\n#else\r\n            BK4819_SetFilterBandwidth(Bandwidth, false);\r\n#endif\r\n            break;\r\n    }\r\n\r\n    BK4819_SetFrequency(gCurrentVfo->pTX->Frequency);\r\n\r\n    // TX compressor\r\n    BK4819_SetCompander((gRxVfo->Modulation == MODULATION_FM && (gRxVfo->Compander == 1 || gRxVfo->Compander >= 3))\r\n                        ? gRxVfo->Compander : 0);\r\n\r\n    BK4819_PrepareTransmit();\r\n\r\n    SYSTEM_DelayMs(10);\r\n\r\n    BK4819_PickRXFilterPathBasedOnFrequency(gCurrentVfo->pTX->Frequency);\r\n\r\n    BK4819_ToggleGpioOut(BK4819_GPIO1_PIN29_PA_ENABLE, true);\r\n\r\n    SYSTEM_DelayMs(5);\r\n\r\n    BK4819_SetupPowerAmplifier(gCurrentVfo->TXP_CalculatedSetting, gCurrentVfo->pTX->Frequency);\r\n\r\n    SYSTEM_DelayMs(10);\r\n\r\n    switch (gCurrentVfo->pTX->CodeType) {\r\n        default:\r\n        case CODE_TYPE_OFF:\r\n            BK4819_ExitSubAu();\r\n            break;\r\n\r\n        case CODE_TYPE_CONTINUOUS_TONE:\r\n#if ENABLE_CHINESE_FULL == 0||defined(ENABLE_ENGLISH)\r\n            BK4819_SetCTCSSFrequency(CTCSS_Options[gCurrentVfo->pTX->Code]);\r\n#else\r\n\r\n            EEPROM_ReadBuffer(0x02C00+(gCurrentVfo->pTX->Code)*2, read_tmp, 2);\r\n            uint16_t CTCSS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\n                BK4819_SetCTCSSFrequency(CTCSS_Options_read);\r\n\r\n#endif\r\n\r\n            break;\r\n\r\n        case CODE_TYPE_DIGITAL:\r\n        case CODE_TYPE_REVERSE_DIGITAL:\r\n            BK4819_SetCDCSSCodeWord(DCS_GetGolayCodeWord(gCurrentVfo->pTX->CodeType, gCurrentVfo->pTX->Code));\r\n            break;\r\n    }\r\n}\r\n\r\nvoid RADIO_SetModulation(ModulationMode_t modulation) {\r\n    BK4819_AF_Type_t mod;\r\n    switch (modulation) {\r\n        default:\r\n        case MODULATION_FM:\r\n            mod = BK4819_AF_FM;\r\n            break;\r\n        case MODULATION_AM:\r\n            mod = BK4819_AF_AM;\r\n            break;\r\n        case MODULATION_USB:\r\n            mod = BK4819_AF_BASEBAND2;\r\n            break;\r\n\r\n#ifdef ENABLE_BYP_RAW_DEMODULATORS\r\n            case MODULATION_BYP:\r\n            mod = BK4819_AF_UNKNOWN3;\r\n            break;\r\n        case MODULATION_RAW:\r\n            mod = BK4819_AF_BASEBAND1;\r\n            break;\r\n#endif\r\n    }\r\n\r\n    BK4819_SetAF(mod);\r\n\r\n\r\n    BK4819_SetRegValue(afDacGainRegSpec, 0xF);\r\n    BK4819_WriteRegister(BK4819_REG_3D, modulation == MODULATION_USB ? 0 : 0x2AAB);\r\n    BK4819_SetRegValue(afcDisableRegSpec, modulation != MODULATION_FM);\r\n\r\n    RADIO_SetupAGC(modulation == MODULATION_AM, false);\r\n}\r\n\r\nvoid RADIO_SetupAGC(bool listeningAM, bool disable) {\r\n    static uint8_t lastSettings;\r\n    uint8_t newSettings = (listeningAM << 1) | (disable << 1);\r\n    if (lastSettings == newSettings)\r\n        return;\r\n    lastSettings = newSettings;\r\n\r\n\r\n    if (!listeningAM) { // if not actively listening AM we don't need any AM specific regulation\r\n        BK4819_SetAGC(!disable);\r\n        BK4819_InitAGC(false);\r\n    } else {\r\n#ifdef ENABLE_AM_FIX\r\n        if(gSetting_AM_fix) { // if AM fix active lock AGC so AM-fix can do it's job\r\n            BK4819_SetAGC(0);\r\n            AM_fix_enable(!disable);\r\n        }\r\n        else\r\n#endif\r\n        {\r\n            BK4819_SetAGC(!disable);\r\n            BK4819_InitAGC(true);\r\n        }\r\n    }\r\n}\r\n\r\nvoid RADIO_SetVfoState(VfoState_t State) {\r\n    if (State == VFO_STATE_NORMAL) {\r\n        VfoState[0] = VFO_STATE_NORMAL;\r\n        VfoState[1] = VFO_STATE_NORMAL;\r\n    } else if (State == VFO_STATE_VOLTAGE_HIGH) {\r\n        VfoState[0] = VFO_STATE_VOLTAGE_HIGH;\r\n        VfoState[1] = VFO_STATE_TX_DISABLE;\r\n    } else {\r\n        // 1of11\r\n        const unsigned int vfo = (gEeprom.CROSS_BAND_RX_TX == CROSS_BAND_OFF) ? gEeprom.RX_VFO : gEeprom.TX_VFO;\r\n        VfoState[vfo] = State;\r\n    }\r\n\r\n    gVFOStateResumeCountdown_500ms = (State == VFO_STATE_NORMAL) ? 0 : vfo_state_resume_countdown_500ms;\r\n    gUpdateDisplay = true;\r\n}\r\n\r\nvoid RADIO_PrepareTX(void) {\r\n    VfoState_t State = VFO_STATE_NORMAL;  // default to OK to TX\r\n\r\n    if (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF) {    // dual-RX is enabled\r\n\r\n        gDualWatchCountdown_10ms = dual_watch_count_after_tx_10ms;\r\n        gScheduleDualWatch = false;\r\n\r\n        if (!gRxVfoIsActive) {    // use the current RX vfo\r\n            gEeprom.RX_VFO = gEeprom.TX_VFO;\r\n            gRxVfo = gTxVfo;\r\n            gRxVfoIsActive = true;\r\n        }\r\n\r\n        // let the user see that DW is not active\r\n        gDualWatchActive = false;\r\n        gUpdateStatus = true;\r\n    }\r\n\r\n    RADIO_SelectCurrentVfo();\r\n    if (TX_freq_check(gCurrentVfo->pTX->Frequency) != 0\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\n        && gAlarmState != ALARM_STATE_SITE_ALARM\r\n#endif\r\n            ) {\r\n        // TX frequency not allowed\r\n        State = VFO_STATE_TX_DISABLE;\r\n    } else if (SerialConfigInProgress()) {\r\n        // TX is disabled or config upload/download in progress\r\n        State = VFO_STATE_TX_DISABLE;\r\n    } else if (gCurrentVfo->BUSY_CHANNEL_LOCK && gCurrentFunction == FUNCTION_RECEIVE) {\r\n        // busy RX'ing a station\r\n        State = VFO_STATE_BUSY;\r\n    } else if (gBatteryDisplayLevel == 0) {\r\n        // charge your battery !git co\r\n        State = VFO_STATE_BAT_LOW;\r\n    } else if (gBatteryDisplayLevel > 6) {\r\n        // over voltage .. this is being a pain\r\n        State = VFO_STATE_VOLTAGE_HIGH;\r\n    }\r\n#ifndef ENABLE_TX_WHEN_AM\r\n    else if (gCurrentVfo->Modulation != MODULATION_FM) {\r\n        // not allowed to TX if in AM mode\r\n        State = VFO_STATE_TX_DISABLE;\r\n    }\r\n#endif\r\n\r\n    if (State != VFO_STATE_NORMAL) {\r\n        // TX not allowed\r\n        RADIO_SetVfoState(State);\r\n\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\n        gAlarmState = ALARM_STATE_OFF;\r\n#endif\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n        gDTMF_ReplyState = DTMF_REPLY_NONE;\r\n#endif\r\n#ifdef    ENABLE_WARNING\r\n\r\n        AUDIO_PlayBeep(BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL);\r\n#endif\r\n        return;\r\n    }\r\n\r\n    // TX is allowed\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (gDTMF_ReplyState == DTMF_REPLY_ANI)\r\n    {\r\n        gDTMF_IsTx = gDTMF_CallMode == DTMF_CALL_MODE_DTMF;\r\n\r\n        if (gDTMF_IsTx) {\r\n            gDTMF_CallState = DTMF_CALL_STATE_NONE;\r\n            gDTMF_TxStopCountdown_500ms = DTMF_txstop_countdown_500ms;\r\n        } else {\r\n            gDTMF_CallState = DTMF_CALL_STATE_CALL_OUT;\r\n        }\r\n    }\r\n#endif\r\n\r\n    FUNCTION_Select(FUNCTION_TRANSMIT);\r\n\r\n    gTxTimerCountdown_500ms = 0;            // no timeout\r\n\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\n    if (gAlarmState == ALARM_STATE_OFF)\r\n#endif\r\n    {\r\n        if (gEeprom.TX_TIMEOUT_TIMER == 0)\r\n            gTxTimerCountdown_500ms = 60;   // 30 sec\r\n        else if (gEeprom.TX_TIMEOUT_TIMER < (ARRAY_SIZE(gSubMenu_TOT) - 1))\r\n            gTxTimerCountdown_500ms = 120 * gEeprom.TX_TIMEOUT_TIMER;  // minutes\r\n        else\r\n            gTxTimerCountdown_500ms = 120 * 15;  // 15 minutes\r\n    }\r\n    gTxTimeoutReached = false;\r\n\r\n    gRTTECountdown_10ms = 0;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    gDTMF_ReplyState     = DTMF_REPLY_NONE;\r\n#endif\r\n}\r\n\r\nvoid RADIO_SendCssTail(void) {\r\n    switch (gCurrentVfo->pTX->CodeType) {\r\n        case CODE_TYPE_DIGITAL:\r\n        case CODE_TYPE_REVERSE_DIGITAL:\r\n            BK4819_PlayCDCSSTail();\r\n            break;\r\n        default:\r\n            BK4819_PlayCTCSSTail();\r\n            break;\r\n    }\r\n\r\n    SYSTEM_DelayMs(200);\r\n}\r\n\r\nvoid RADIO_PrepareCssTX(void) {\r\n    RADIO_PrepareTX();\r\n\r\n    SYSTEM_DelayMs(200);\r\n\r\n    if (gEeprom.TAIL_TONE_ELIMINATION)\r\n        RADIO_SendCssTail();\r\n    RADIO_SetupRegisters(true);\r\n}\r\n"
  },
  {
    "path": "radio.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef RADIO_H\r\n#define RADIO_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n#include \"dcs.h\"\r\n#include \"frequencies.h\"\r\n\r\nenum {\r\n    RADIO_CHANNEL_UP   = 0x01u,\r\n    RADIO_CHANNEL_DOWN = 0xFFu,\r\n};\r\n\r\nenum {\r\n    BANDWIDTH_WIDE = 0,\r\n    BANDWIDTH_NARROW\r\n};\r\n\r\nenum PTT_ID_t {\r\n    PTT_ID_OFF = 0,    // OFF\r\n    PTT_ID_TX_UP,      // BEGIN OF TX\r\n    PTT_ID_TX_DOWN,    // END OF TX\r\n    PTT_ID_BOTH,       // BOTH\r\n    PTT_ID_APOLLO      // Apolo quindar tones\r\n};\r\ntypedef enum PTT_ID_t PTT_ID_t;\r\n\r\nenum VfoState_t\r\n{\r\n    VFO_STATE_NORMAL = 0,\r\n    VFO_STATE_BUSY,\r\n    VFO_STATE_BAT_LOW,\r\n    VFO_STATE_TX_DISABLE,\r\n    VFO_STATE_TIMEOUT,\r\n    VFO_STATE_ALARM,\r\n    VFO_STATE_VOLTAGE_HIGH,\r\n    _VFO_STATE_LAST_ELEMENT\r\n};\r\ntypedef enum VfoState_t VfoState_t;\r\n\r\ntypedef enum {\r\n    MODULATION_FM,\r\n    MODULATION_AM,\r\n    MODULATION_USB,\r\n\r\n#ifdef ENABLE_BYP_RAW_DEMODULATORS\r\n    MODULATION_BYP,\r\n\tMODULATION_RAW,\r\n#endif\r\n\r\n    MODULATION_UKNOWN\r\n} ModulationMode_t;\r\n\r\nextern const char gModulationStr[MODULATION_UKNOWN][4];\r\n\r\ntypedef struct\r\n{\r\n    uint32_t       Frequency;\r\n    DCS_CodeType_t CodeType;\r\n    uint8_t        Code;\r\n    uint8_t        Padding[2];\r\n} FREQ_Config_t;\r\n\r\ntypedef struct VFO_Info_t\r\n{\r\n    FREQ_Config_t  freq_config_RX;\r\n    FREQ_Config_t  freq_config_TX;\r\n\r\n    // this is for a purpose of the FrequencyReverse function\r\n    // it points to freq_config_RX normally and to freq_config_TX if reverse function is active\r\n    //\r\n    FREQ_Config_t *pRX;\r\n\r\n    // this is for a purpose of the FrequencyReverse function\r\n    // it points to freq_config_TX normally and to freq_config_RX if reverse function is active\r\n    FREQ_Config_t *pTX;\r\n\r\n    uint32_t       TX_OFFSET_FREQUENCY;\r\n    uint16_t       StepFrequency;\r\n\r\n    uint8_t        CHANNEL_SAVE;\r\n\r\n    uint8_t        TX_OFFSET_FREQUENCY_DIRECTION;\r\n\r\n    uint8_t        SquelchOpenRSSIThresh;\r\n    uint8_t        SquelchOpenNoiseThresh;\r\n    uint8_t        SquelchCloseGlitchThresh;\r\n    uint8_t        SquelchCloseRSSIThresh;\r\n    uint8_t        SquelchCloseNoiseThresh;\r\n    uint8_t        SquelchOpenGlitchThresh;\r\n\r\n    STEP_Setting_t STEP_SETTING;\r\n    uint8_t        OUTPUT_POWER;\r\n    uint8_t        TXP_CalculatedSetting;\r\n    uint8_t        FrequencyReverse;\r\n\r\n    uint8_t        SCRAMBLING_TYPE;\r\n    uint8_t        CHANNEL_BANDWIDTH;\r\n\r\n    uint8_t        SCANLIST1_PARTICIPATION;\r\n    uint8_t        SCANLIST2_PARTICIPATION;\r\n\r\n    uint8_t        Band;\r\n#ifdef ENABLE_DTMF_CALLING\r\n    uint8_t        DTMF_DECODING_ENABLE;\r\n#endif\r\n    PTT_ID_t       DTMF_PTT_ID_TX_MODE;\r\n\r\n    uint8_t        BUSY_CHANNEL_LOCK;\r\n\r\n    ModulationMode_t    Modulation;\r\n\r\n    uint8_t        Compander;\r\n\r\n    char           Name[16];\r\n} VFO_Info_t;\r\n\r\n// Settings of the main VFO that is selected by the user\r\n// The pointer follows gEeprom.TX_VFO index\r\nextern VFO_Info_t    *gTxVfo;\r\n\r\n// Settings of the actual VFO that is now used for RX,\r\n// It is being alternated by dual watch, and flipped by crossband\r\n// The pointer follows gEeprom.RX_VFO\r\nextern VFO_Info_t    *gRxVfo;\r\n\r\n// Equal to gTxVfo unless dual watch changes it on incomming transmition (this can only happen when XB off and DW on)\r\nextern VFO_Info_t    *gCurrentVfo;\r\n\r\nextern DCS_CodeType_t gCurrentCodeType;\r\n\r\nextern VfoState_t     VfoState[2];\r\n\r\nbool     RADIO_CheckValidChannel(uint16_t channel, bool checkScanList, uint8_t scanList);\r\nuint8_t  RADIO_FindNextChannel(uint8_t ChNum, int8_t Direction, bool bCheckScanList, uint8_t RadioNum);\r\nvoid     RADIO_InitInfo(VFO_Info_t *pInfo, const uint8_t ChannelSave, const uint32_t Frequency);\r\nvoid     RADIO_ConfigureChannel(const unsigned int VFO, const unsigned int configure);\r\nvoid     RADIO_ConfigureSquelchAndOutputPower(VFO_Info_t *pInfo);\r\nvoid     RADIO_ApplyOffset(VFO_Info_t *pInfo);\r\nvoid     RADIO_SelectVfos(void);\r\nvoid RADIO_SetupRegisters(bool switchToForeground);\r\n#ifdef ENABLE_NOAA\r\nvoid RADIO_ConfigureNOAA(void);\r\n#endif\r\nvoid     RADIO_SetTxParameters(void);\r\nvoid     RADIO_SetModulation(ModulationMode_t modulation);\r\nvoid     RADIO_SetVfoState(VfoState_t State);\r\nvoid     RADIO_PrepareTX(void);\r\nvoid     RADIO_SendCssTail(void);\r\nvoid     RADIO_PrepareCssTX(void);\r\nvoid     RADIO_SendEndOfTransmission(void);\r\nvoid RADIO_SetupAGC(bool listeningAM, bool disable);\r\n\r\n#endif"
  },
  {
    "path": "scheduler.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"app/chFrScanner.h\"\r\n#ifdef ENABLE_FMRADIO\r\n\t#include \"app/fm.h\"\r\n#endif\r\n#include \"app/scanner.h\"\r\n#include \"audio.h\"\r\n#include \"functions.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n\r\n#include \"driver/backlight.h\"\r\n#include \"bsp/dp32g030/gpio.h\"\r\n#include \"driver/gpio.h\"\r\n\r\n#define DECREMENT(cnt) \\\r\n\tdo {               \\\r\n\t\tif (cnt > 0)   \\\r\n\t\t\tcnt--;     \\\r\n\t} while (0)\r\n\r\n#define DECREMENT_AND_TRIGGER(cnt, flag) \\\r\n\tdo {                                 \\\r\n\t\tif (cnt > 0)                     \\\r\n\t\t\tif (--cnt == 0)              \\\r\n\t\t\t\tflag = true;             \\\r\n\t} while (0)\r\n\r\nstatic volatile uint32_t gGlobalSysTickCounter;\r\n\r\nvoid SystickHandler(void);\r\n\r\n// we come here every 10ms\r\nvoid SystickHandler(void)\r\n{\r\n\tgGlobalSysTickCounter++;\r\n\t\r\n\tgNextTimeslice = true;\r\n\r\n\tif ((gGlobalSysTickCounter % 50) == 0)\r\n\t{\r\n\t\tgNextTimeslice_500ms = true;\r\n\t\t\r\n\t\tDECREMENT_AND_TRIGGER(gTxTimerCountdown_500ms, gTxTimeoutReached);\r\n\t\tDECREMENT(gSerialConfigCountDown_500ms);\r\n\t}\r\n\r\n\tif ((gGlobalSysTickCounter & 3) == 0)\r\n\t\tgNextTimeslice40ms = true;\r\n\r\n\t#ifdef ENABLE_NOAA\r\n\t\tDECREMENT(gNOAACountdown_10ms);\r\n\t#endif\r\n\r\n\tDECREMENT(gFoundCDCSSCountdown_10ms);\r\n\r\n\tDECREMENT(gFoundCTCSSCountdown_10ms);\r\n\r\n\tif (gCurrentFunction == FUNCTION_FOREGROUND)\r\n\t\tDECREMENT_AND_TRIGGER(gBatterySaveCountdown_10ms, gSchedulePowerSave);\r\n\r\n\tif (gCurrentFunction == FUNCTION_POWER_SAVE)\r\n\t\tDECREMENT_AND_TRIGGER(gPowerSave_10ms, gPowerSaveCountdownExpired);\r\n\r\n\tif (gScanStateDir == SCAN_OFF && !gCssBackgroundScan && gEeprom.DUAL_WATCH != DUAL_WATCH_OFF)\r\n\t\tif (gCurrentFunction != FUNCTION_MONITOR && gCurrentFunction != FUNCTION_TRANSMIT && gCurrentFunction != FUNCTION_RECEIVE)\r\n\t\t\tDECREMENT_AND_TRIGGER(gDualWatchCountdown_10ms, gScheduleDualWatch);\r\n\r\n\t#ifdef ENABLE_NOAA\r\n\t\tif (gScanStateDir == SCAN_OFF && !gCssBackgroundScan && gEeprom.DUAL_WATCH == DUAL_WATCH_OFF)\r\n\t\t\tif (gIsNoaaMode && gCurrentFunction != FUNCTION_MONITOR && gCurrentFunction != FUNCTION_TRANSMIT)\r\n\t\t\t\tif (gCurrentFunction != FUNCTION_RECEIVE)\r\n\t\t\t\t\tDECREMENT_AND_TRIGGER(gNOAA_Countdown_10ms, gScheduleNOAA);\r\n\t#endif\r\n\r\n\tif (gScanStateDir != SCAN_OFF)\r\n\t\tif (gCurrentFunction != FUNCTION_MONITOR && gCurrentFunction != FUNCTION_TRANSMIT)\r\n\t\t\tDECREMENT_AND_TRIGGER(gScanPauseDelayIn_10ms, gScheduleScanListen);\r\n\r\n\tDECREMENT_AND_TRIGGER(gTailToneEliminationCountdown_10ms, gFlagTailToneEliminationComplete);\r\n\r\n\t#ifdef ENABLE_VOICE\r\n\t\tDECREMENT_AND_TRIGGER(gCountdownToPlayNextVoice_10ms, gFlagPlayQueuedVoice);\r\n\t#endif\r\n\t\r\n\t#ifdef ENABLE_FMRADIO\r\n\t\tif (gFM_ScanState != FM_SCAN_OFF && gCurrentFunction != FUNCTION_MONITOR)\r\n\t\t\tif (gCurrentFunction != FUNCTION_TRANSMIT && gCurrentFunction != FUNCTION_RECEIVE)\r\n\t\t\t\tDECREMENT_AND_TRIGGER(gFmPlayCountdown_10ms, gScheduleFM);\r\n\t#endif\r\n\r\n\t#ifdef ENABLE_VOX\r\n\t\tDECREMENT(gVoxStopCountdown_10ms);\r\n\t#endif\r\n\r\n\tDECREMENT(boot_counter_10ms);\r\n}\r\n"
  },
  {
    "path": "settings.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <string.h>\r\n\r\n#include \"app/dtmf.h\"\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/menu.h\"\r\n\r\nstatic const uint32_t gDefaultFrequencyTable[] =\r\n        {\r\n                14500000,    //\r\n                14550000,    //\r\n                43300000,    //\r\n                43320000,    //\r\n                43350000     //\r\n        };\r\n\r\nEEPROM_Config_t gEeprom={0};\r\n int               key_dir;\r\n\r\nvoid SETTINGS_InitEEPROM(void)\r\n{\r\n    uint8_t Data[16] = {0};\r\n    // 0E70..0E77\r\n    EEPROM_ReadBuffer(0x0E70, Data, 8);\r\n    gEeprom.CHAN_1_CALL          = IS_MR_CHANNEL(Data[0]) ? Data[0] : MR_CHANNEL_FIRST;\r\n    gEeprom.SQUELCH_LEVEL        = (Data[1] < 10) ? Data[1] : 1;\r\n    gEeprom.TX_TIMEOUT_TIMER     = (Data[2] < 11) ? Data[2] : 1;\r\n#ifdef ENABLE_NOAA\r\n    gEeprom.NOAA_AUTO_SCAN   = (Data[3] <  2) ? Data[3] : false;\r\n#endif\r\n    gEeprom.KEY_LOCK             = (Data[4] <  2) ? Data[4] : false;\r\n#ifdef ENABLE_VOX\r\n    gEeprom.VOX_SWITCH       = (Data[5] <  2) ? Data[5] : false;\r\n\t\tgEeprom.VOX_LEVEL        = (Data[6] < 10) ? Data[6] : 1;\r\n#endif\r\n    gEeprom.MIC_SENSITIVITY      = (Data[7] <  5) ? Data[7] : 4;\r\n\r\n    // 0E78..0E7F\r\n    EEPROM_ReadBuffer(0x0E78, Data, 8);\r\n    gEeprom.BACKLIGHT_MAX \t\t  = (Data[0] & 0xF) <= 10 ? (Data[0] & 0xF) : 10;\r\n    key_dir \t\t  = (Data[0] >> 4) !=0xA ? -1 : 1;\r\n#ifdef ENABLE_BLMIN_TMP_OFF\r\n    gEeprom.BACKLIGHT_MIN_STAT\t  = BLMIN_STAT_ON;\r\n#endif\r\n    gEeprom.CHANNEL_DISPLAY_MODE  = (Data[1] < 4) ? Data[1] : MDF_FREQUENCY;    // 4 instead of 3 - extra display mode\r\n    gEeprom.CROSS_BAND_RX_TX      = (Data[2] < 3) ? Data[2] : CROSS_BAND_OFF;\r\n    gEeprom.BATTERY_SAVE          = (Data[3] < 5) ? Data[3] : 4;\r\n    gEeprom.DUAL_WATCH            = (Data[4] < 3) ? Data[4] : DUAL_WATCH_CHAN_A;\r\n    gEeprom.BACKLIGHT_TIME        = (Data[5] < ARRAY_SIZE(gSubMenu_BACKLIGHT)) ? Data[5] : 3;\r\n    gEeprom.TAIL_TONE_ELIMINATION = (Data[6] < 2) ? Data[6] : false;\r\n    gEeprom.VFO_OPEN              = (Data[7] < 2) ? Data[7] : true;\r\n\r\n    // 0E80..0E87\r\n    EEPROM_ReadBuffer(0x0E80, Data, 8);\r\n    gEeprom.ScreenChannel[0]   = IS_VALID_CHANNEL(Data[0]) ? Data[0] : (FREQ_CHANNEL_FIRST + BAND6_400MHz);\r\n    gEeprom.ScreenChannel[1]   = IS_VALID_CHANNEL(Data[3]) ? Data[3] : (FREQ_CHANNEL_FIRST + BAND6_400MHz);\r\n    gEeprom.MrChannel[0]       = IS_MR_CHANNEL(Data[1])    ? Data[1] : MR_CHANNEL_FIRST;\r\n    gEeprom.MrChannel[1]       = IS_MR_CHANNEL(Data[4])    ? Data[4] : MR_CHANNEL_FIRST;\r\n    gEeprom.FreqChannel[0]     = IS_FREQ_CHANNEL(Data[2])  ? Data[2] : (FREQ_CHANNEL_FIRST + BAND6_400MHz);\r\n    gEeprom.FreqChannel[1]     = IS_FREQ_CHANNEL(Data[5])  ? Data[5] : (FREQ_CHANNEL_FIRST + BAND6_400MHz);\r\n#ifdef ENABLE_NOAA\r\n    gEeprom.NoaaChannel[0] = IS_NOAA_CHANNEL(Data[6])  ? Data[6] : NOAA_CHANNEL_FIRST;\r\n\tgEeprom.NoaaChannel[1] = IS_NOAA_CHANNEL(Data[7])  ? Data[7] : NOAA_CHANNEL_FIRST;\r\n#endif\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    {\t// 0E88..0E8F\r\n\t\tstruct\r\n\t\t{\r\n\t\t\tuint16_t SelectedFrequency;\r\n\t\t\tuint8_t  SelectedChannel;\r\n\t\t\tuint8_t  IsMrMode;\r\n\t\t\tuint8_t  Padding[8];\r\n\t\t} __attribute__((packed)) FM;\r\n\r\n\t\tEEPROM_ReadBuffer(0x0E88, &FM, 8);\r\n\t\tgEeprom.FM_LowerLimit = 640;\r\n\t\tgEeprom.FM_UpperLimit = 1080;\r\n\t\tif (FM.SelectedFrequency < gEeprom.FM_LowerLimit || FM.SelectedFrequency > gEeprom.FM_UpperLimit)\r\n\t\t\tgEeprom.FM_SelectedFrequency = 960;\r\n\t\telse\r\n\t\t\tgEeprom.FM_SelectedFrequency = FM.SelectedFrequency;\r\n\r\n\t\tgEeprom.FM_SelectedChannel = FM.SelectedChannel;\r\n\t\tgEeprom.FM_IsMrMode        = (FM.IsMrMode < 2) ? FM.IsMrMode : false;\r\n\t}\r\n\r\n\t// 0E40..0E67\r\n\tEEPROM_ReadBuffer(0x0E40, gFM_Channels, sizeof(gFM_Channels));\r\n\tFM_ConfigureChannelState();\r\n#endif\r\n\r\n    // 0E90..0E97\r\n    EEPROM_ReadBuffer(0x0E90, Data, 8);\r\n    gEeprom.BEEP_CONTROL                 = Data[0] & 1;\r\n\r\n    gEeprom.MDC1200_ID     =((uint16_t) (Data[2] << 8))|((uint16_t)(Data[1] ));\r\n//    gEeprom.KEY_1_LONG_PRESS_ACTION      = (Data[2] < ACTION_OPT_LEN) ? Data[2] : ACTION_OPT_FLASHLIGHT;\r\n//    gEeprom.KEY_2_SHORT_PRESS_ACTION     = (Data[3] < ACTION_OPT_LEN) ? Data[3] : ACTION_OPT_SCAN;\r\n//    gEeprom.KEY_2_LONG_PRESS_ACTION      = (Data[4] < ACTION_OPT_LEN) ? Data[4] : ACTION_OPT_NONE;\r\n    gEeprom.SCAN_RESUME_MODE             = (Data[5] < 3)              ? Data[5] : SCAN_RESUME_CO;\r\n//    gEeprom.AUTO_KEYPAD_LOCK             = (Data[6] < 2)              ? Data[6] : false;\r\n#if ENABLE_CHINESE_FULL==4\r\n    gEeprom.POWER_ON_DISPLAY_MODE        = (Data[7] < 4)              ? Data[7] : POWER_ON_DISPLAY_MODE_NONE;\r\n#endif\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n    // 1FF8..1FFF\r\n    EEPROM_ReadBuffer(0x1FF8, Data, 8);\r\n    gEeprom.KEY_M_LONG_PRESS_ACTION       = (Data[0] < ACTION_OPT_LEN) ? Data[0] : ACTION_OPT_SWITCH_DEMODUL;\r\n    gEeprom.KEY_1_SHORT_PRESS_ACTION      = (Data[1] < ACTION_OPT_LEN-2) ? Data[1] : ACTION_OPT_MONITOR;\r\n    gEeprom.KEY_1_LONG_PRESS_ACTION       = (Data[2] < ACTION_OPT_LEN) ? Data[2] : ACTION_OPT_D_DCD;\r\n    gEeprom.KEY_2_SHORT_PRESS_ACTION      = (Data[3] < ACTION_OPT_LEN-2) ? Data[3] : ACTION_OPT_WIDTH;\r\n    gEeprom.KEY_2_LONG_PRESS_ACTION       = (Data[4] < ACTION_OPT_LEN) ? Data[4] : ACTION_OPT_FLASHLIGHT;\r\n#endif\r\n\r\n    // 0E98..0E9F\r\n    EEPROM_ReadBuffer(0x0E98, Data, 8);\r\n    memcpy(&gEeprom.POWER_ON_PASSWORD, Data, 4);\r\n\r\n    // 0EA0..0EA7\r\n    EEPROM_ReadBuffer(0x0EA0, Data, 8);\r\n#ifdef ENABLE_VOICE\r\n    gEeprom.VOICE_PROMPT = (Data[0] < 3) ? Data[0] : VOICE_PROMPT_ENGLISH;\r\n#endif\r\n#ifdef ENABLE_RSSI_BAR\r\n    if((Data[1] < 200 && Data[1] > 90) && (Data[2] < Data[1]-9 && Data[1] < 160 && Data[2] > 50)) {\r\n\t\t\tgEeprom.S0_LEVEL = Data[1];\r\n\t\t\tgEeprom.S9_LEVEL = Data[2];\r\n\t\t}\r\n\t\telse {\r\n\t\t\tgEeprom.S0_LEVEL = 130;\r\n\t\t\tgEeprom.S9_LEVEL = 76;\r\n\t\t}\r\n#endif\r\n\r\n\r\n    // 0EA8..0EAF\r\n    EEPROM_ReadBuffer(0x0EA8, Data, 8);\r\n#ifdef ENABLE_ALARM\r\n    gEeprom.ALARM_MODE                 = (Data[0] <  2) ? Data[0] : true;\r\n#endif\r\n    gEeprom.ROGER                          = (Data[1] <  6) ? Data[1] : ROGER_MODE_OFF;\r\n    gEeprom.REPEATER_TAIL_TONE_ELIMINATION = (Data[2] < 11) ? Data[2] : 0;\r\n    gEeprom.TX_VFO                         = (Data[3] <  2) ? Data[3] : 0;\r\n    gEeprom.BATTERY_TYPE                   = (Data[4] < BATTERY_TYPE_UNKNOWN) ? Data[4] : BATTERY_TYPE_1600_MAH;\r\n\r\n    // 0ED0..0ED7\r\n    EEPROM_ReadBuffer(0x0ED0, Data, 8);\r\n    gEeprom.DTMF_SIDE_TONE               = (Data[0] <   2) ? Data[0] : true;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    gEeprom.DTMF_SEPARATE_CODE           = DTMF_ValidateCodes((char *)(Data + 1), 1) ? Data[1] : '*';\r\n\tgEeprom.DTMF_GROUP_CALL_CODE         = DTMF_ValidateCodes((char *)(Data + 2), 1) ? Data[2] : '#';\r\n\tgEeprom.DTMF_DECODE_RESPONSE         = (Data[3] <   4) ? Data[3] : 0;\r\ngEeprom.DTMF_auto_reset_time = (Data[4] < 61 && Data[4] >= 5) ? Data[4] : 10;\r\n#endif\r\n    gEeprom.DTMF_PRELOAD_TIME            = (Data[5] < 101) ? Data[5] * 10 : 300;\r\n    gEeprom.DTMF_FIRST_CODE_PERSIST_TIME = (Data[6] < 101) ? Data[6] * 10 : 100;\r\n    gEeprom.DTMF_HASH_CODE_PERSIST_TIME  = (Data[7] < 101) ? Data[7] * 10 : 100;\r\n\r\n    // 0ED8..0EDF\r\n    EEPROM_ReadBuffer(0x0ED8, Data, 8);\r\n    gEeprom.DTMF_CODE_PERSIST_TIME  = (Data[0] < 101) ? Data[0] * 10 : 100;\r\n    gEeprom.DTMF_CODE_INTERVAL_TIME = (Data[1] < 101) ? Data[1] * 10 : 100;\r\n#ifdef ENABLE_DTMF_CALLING\r\n    gEeprom.PERMIT_REMOTE_KILL      = (Data[2] <   2) ? Data[2] : true;\r\n\r\n\t// 0EE0..0EE7\r\n\r\nEEPROM_ReadBuffer(0x0EE0, Data, sizeof(gEeprom.ANI_DTMF_ID));\r\n\tif (DTMF_ValidateCodes((char *)Data, sizeof(gEeprom.ANI_DTMF_ID))) {\r\n\t\tmemcpy(gEeprom.ANI_DTMF_ID, Data, sizeof(gEeprom.ANI_DTMF_ID));\r\n\t} else {\r\n\t\tstrcpy(gEeprom.ANI_DTMF_ID, \"123\");\r\n\t}\r\n\r\n\r\n\t// 0EE8..0EEF\r\nEEPROM_ReadBuffer(0x0EE8, Data, sizeof(gEeprom.KILL_CODE));\r\n\tif (DTMF_ValidateCodes((char *)Data, sizeof(gEeprom.KILL_CODE))) {\r\n\t\tmemcpy(gEeprom.KILL_CODE, Data, sizeof(gEeprom.KILL_CODE));\r\n\t} else {\r\n\t\tstrcpy(gEeprom.KILL_CODE, \"ABCD9\");\r\n\t}\r\n\r\n\t// 0EF0..0EF7\r\nEEPROM_ReadBuffer(0x0EF0, Data, sizeof(gEeprom.REVIVE_CODE));\r\n\tif (DTMF_ValidateCodes((char *)Data, sizeof(gEeprom.REVIVE_CODE))) {\r\n\t\tmemcpy(gEeprom.REVIVE_CODE, Data, sizeof(gEeprom.REVIVE_CODE));\r\n\t} else {\r\n\t\tstrcpy(gEeprom.REVIVE_CODE, \"9DCBA\");\r\n\t}\r\n#endif\r\n\r\n    // 0EF8..0F07\r\n    EEPROM_ReadBuffer(0x0EF8, Data, sizeof(gEeprom.DTMF_UP_CODE));\r\n    if (DTMF_ValidateCodes((char *)Data, sizeof(gEeprom.DTMF_UP_CODE))) {\r\n        memcpy(gEeprom.DTMF_UP_CODE, Data, sizeof(gEeprom.DTMF_UP_CODE));\r\n    } else {\r\n        strcpy(gEeprom.DTMF_UP_CODE, \"12345\");\r\n    }\r\n\r\n    // 0F08..0F17\r\n    EEPROM_ReadBuffer(0x0F08, Data, sizeof(gEeprom.DTMF_DOWN_CODE));\r\n    if (DTMF_ValidateCodes((char *)Data, sizeof(gEeprom.DTMF_DOWN_CODE))) {\r\n        memcpy(gEeprom.DTMF_DOWN_CODE, Data, sizeof(gEeprom.DTMF_DOWN_CODE));\r\n    } else {\r\n        strcpy(gEeprom.DTMF_DOWN_CODE, \"54321\");\r\n    }\r\n\r\n    // 0F18..0F1F\r\n    EEPROM_ReadBuffer(0x0F18, Data, 8);\r\n    gEeprom.SCAN_LIST_DEFAULT = (Data[0] < 3) ? Data[0] : 0;  // we now have 'all' channel scan option\r\n    for (unsigned int i = 0; i < 2; i++)\r\n    {\r\n        const unsigned int j = 1 + (i * 3);\r\n        gEeprom.SCAN_LIST_ENABLED[i]     = (Data[j + 0] < 2) ? Data[j] : false;\r\n        gEeprom.SCANLIST_PRIORITY_CH1[i] =  Data[j + 1];\r\n        gEeprom.SCANLIST_PRIORITY_CH2[i] =  Data[j + 2];\r\n    }\r\n\r\n    // 0F40..0F47\r\n    EEPROM_ReadBuffer(0x0F40, Data, 8);\r\n    gSetting_F_LOCK            = (Data[0] < F_LOCK_LEN) ? Data[0] : F_LOCK_DEF;\r\n//    gSetting_350TX             = (Data[1] < 2) ? Data[1] : false;  // was true\r\n#ifdef ENABLE_DTMF_CALLING\r\n    gSetting_KILLED            = (Data[2] < 2) ? Data[2] : false;\r\n#endif\r\n//    gSetting_200TX             = (Data[3] < 2) ? Data[3] : false;\r\n//    gSetting_500TX             = (Data[4] < 2) ? Data[4] : false;\r\n//    gSetting_350EN             = (Data[5] < 2) ? Data[5] : true;\r\n    gSetting_ScrambleEnable    = (Data[6] < 2) ? Data[6] : true;\r\n    //gSetting_TX_EN             = (Data[7] & (1u << 0)) ? true : false;\r\n    gSetting_live_DTMF_decoder = !!(Data[7] & (1u << 1));\r\n    //gSetting_battery_text      = (((Data[7] >> 2) & 3u) <= 2) ? (Data[7] >> 2) & 3 : 2;\r\n//#ifdef ENABLE_AUDIO_BAR\r\n    //gSetting_mic_bar       = (Data[7] & (1u << 4)) ? true : false;\r\n//#endif\r\n#ifdef ENABLE_AM_FIX\r\n    gSetting_AM_fix = !!(Data[7] & (1u << 5));\r\n#endif\r\n  //  gSetting_backlight_on_tx_rx = (Data[7] >> 6) & 3u;\r\n\r\n    if (!gEeprom.VFO_OPEN)\r\n    {\r\n        gEeprom.ScreenChannel[0] = gEeprom.MrChannel[0];\r\n        gEeprom.ScreenChannel[1] = gEeprom.MrChannel[1];\r\n    }\r\n\r\n    // 0D60..0E27\r\n    EEPROM_ReadBuffer(0x0D60, gMR_ChannelAttributes, sizeof(gMR_ChannelAttributes));\r\n    for(uint16_t i = 0; i < sizeof(gMR_ChannelAttributes); i++) {\r\n        ChannelAttributes_t *att = &gMR_ChannelAttributes[i];\r\n        if(att->__val == 0xff){\r\n            att->__val = 0;\r\n            att->band = 0xf;\r\n        }\r\n    }\r\n\r\n    // 0F30..0F3F\r\n    char B[8];\r\n    memset(B,0XFF,8);\r\n    EEPROM_WriteBuffer(0x0F30, B,8);\r\n    EEPROM_WriteBuffer(0x0F38, B,8);\r\n\r\n    EEPROM_ReadBuffer(0x0F30, gCustomAesKey, sizeof(gCustomAesKey));\r\n    bHasCustomAesKey = false;\r\n    //锁定\r\n    for (unsigned int i = 0; i < ARRAY_SIZE(gCustomAesKey); i++)\r\n    {\r\n        if (gCustomAesKey[i] != 0xFFFFFFFFu)\r\n        {\r\n            bHasCustomAesKey = true;\r\n            return;\r\n        }\r\n    }\r\n}\r\n\r\nvoid SETTINGS_LoadCalibration(void)\r\n{\r\n//\tuint8_t Mic;\r\n\r\n    EEPROM_ReadBuffer(0x1EC0, gEEPROM_RSSI_CALIB[3], 8);\r\n    memcpy(gEEPROM_RSSI_CALIB[4], gEEPROM_RSSI_CALIB[3], 8);\r\n    memcpy(gEEPROM_RSSI_CALIB[5], gEEPROM_RSSI_CALIB[3], 8);\r\n    memcpy(gEEPROM_RSSI_CALIB[6], gEEPROM_RSSI_CALIB[3], 8);\r\n\r\n    EEPROM_ReadBuffer(0x1EC8, gEEPROM_RSSI_CALIB[0], 8);\r\n    memcpy(gEEPROM_RSSI_CALIB[1], gEEPROM_RSSI_CALIB[0], 8);\r\n    memcpy(gEEPROM_RSSI_CALIB[2], gEEPROM_RSSI_CALIB[0], 8);\r\n\r\n    EEPROM_ReadBuffer(0x1F40, gBatteryCalibration, 12);\r\n    if (gBatteryCalibration[0] >= 5000)\r\n    {\r\n        gBatteryCalibration[0] = 1900;\r\n        gBatteryCalibration[1] = 2000;\r\n    }\r\n    gBatteryCalibration[5] = 2300;\r\n\r\n#ifdef ENABLE_VOX\r\n    EEPROM_ReadBuffer(0x1F50 + (gEeprom.VOX_LEVEL * 2), &gEeprom.VOX1_THRESHOLD, 2);\r\n\t\tEEPROM_ReadBuffer(0x1F68 + (gEeprom.VOX_LEVEL * 2), &gEeprom.VOX0_THRESHOLD, 2);\r\n#endif\r\n\r\n    //EEPROM_ReadBuffer(0x1F80 + gEeprom.MIC_SENSITIVITY, &Mic, 1);\r\n    //gEeprom.MIC_SENSITIVITY_TUNING = (Mic < 32) ? Mic : 15;\r\n    gEeprom.MIC_SENSITIVITY_TUNING = gMicGain_dB2[gEeprom.MIC_SENSITIVITY];\r\n\r\n    {\r\n        struct\r\n        {\r\n            int16_t  BK4819_XtalFreqLow;\r\n            uint16_t EEPROM_1F8A;\r\n            uint16_t EEPROM_1F8C;\r\n            uint8_t  VOLUME_GAIN;\r\n            uint8_t  DAC_GAIN;\r\n        } __attribute__((packed)) Misc;\r\n\r\n        // radio 1 .. 04 00 46 00 50 00 2C 0E\r\n        // radio 2 .. 05 00 46 00 50 00 2C 0E\r\n        EEPROM_ReadBuffer(0x1F88, &Misc, 8);\r\n\r\n        gEeprom.BK4819_XTAL_FREQ_LOW = (Misc.BK4819_XtalFreqLow >= -1000 && Misc.BK4819_XtalFreqLow <= 1000) ? Misc.BK4819_XtalFreqLow : 0;\r\n        gEEPROM_1F8A                 = Misc.EEPROM_1F8A & 0x01FF;\r\n        gEEPROM_1F8C                 = Misc.EEPROM_1F8C & 0x01FF;\r\n        gEeprom.VOLUME_GAIN          = (Misc.VOLUME_GAIN < 64) ? Misc.VOLUME_GAIN : 58;\r\n        gEeprom.DAC_GAIN             = (Misc.DAC_GAIN    < 16) ? Misc.DAC_GAIN    : 8;\r\n\r\n        BK4819_WriteRegister(BK4819_REG_3B, 22656 + gEeprom.BK4819_XTAL_FREQ_LOW);\r\n//\t\tBK4819_WriteRegister(BK4819_REG_3C, gEeprom.BK4819_XTAL_FREQ_HIGH);\r\n    }\r\n}\r\n\r\nuint32_t SETTINGS_FetchChannelFrequency(const int channel)\r\n{\r\n    struct\r\n    {\r\n        uint32_t frequency;\r\n        uint32_t offset;\r\n    } __attribute__((packed)) info;\r\n\r\n    EEPROM_ReadBuffer(channel * 16, &info, sizeof(info));\r\n\r\n    return info.frequency;\r\n}\r\n\r\nvoid SETTINGS_FetchChannelName(char *s, const int channel)\r\n{\r\n    if (s == NULL)\r\n        return;\r\n    s[0] = 0;\r\n//#if ENABLE_CHINESE_FULL==4\r\n//    memset(s, 0, 16);  // 's' had better be large enough !\r\n//#else\r\n//    memset(s, 0, 10);  // 's' had better be large enough !\r\n//#endif\r\n    if (channel < 0)\r\n        return;\r\n\r\n    if (!RADIO_CheckValidChannel(channel, false, 0))\r\n        return;\r\n//    EEPROM_ReadBuffer(0x0F50 + (channel * 16), s + 0, 8);\r\n\r\n#if ENABLE_CHINESE_FULL==4 && !defined(ENABLE_ENGLISH)\r\n\r\n    EEPROM_ReadBuffer(0x0F50 + (channel * 16), s, 16);\r\n    int i;\r\n    for (i = 0; i < 16; i++)\r\n        if (!((s[i] >= 32 && s[i] <= 127)||(\r\n        s[i]>=0xb0&&s[i]<=0xf7&&i!=15&&s[i+1]!=0)\r\n        ))break;                // invalid char\r\n            else if(s[i]>=0xb0&&s[i]<=0xf7&&i!=15&&s[i+1]!=0) i++;\r\n\r\n#else\r\n    EEPROM_ReadBuffer(0x0F50 + (channel * 16), s, 10);\r\n//    EEPROM_ReadBuffer(0x0F58 + (channel * 16), s + 8, 2);\r\n    int i;\r\n    for (i = 0; i < 10; i++)\r\n        if (s[i] < 32 || s[i] > 127)\r\n            break;                // invalid char\r\n#endif\r\n\r\n\r\n    s[i--] = 0;                   // null term\r\n\r\n    while (i >= 0 && s[i] == 32)  // trim trailing spaces\r\n        s[i--] = 0;               // null term\r\n        //中文信道名\r\n//    strcpy(s,\"\\x9b\\x2c\\x9b\\x2c\\x9b\\x2c\\x9b\\x2c\\x9b\\x2c\\x9b\\x2c\\x9b\\x2c\");\r\n}\r\n\r\nvoid SETTINGS_FactoryReset(bool bIsAll)\r\n{\r\n    uint16_t i;\r\n    uint8_t  Template[8];\r\n\r\n    memset(Template, 0xFF, sizeof(Template));\r\n\r\n    for (i = 0x0C80; i < 0x1E00; i += 8)\r\n    {\r\n        if (\r\n                !(i >= 0x0EE0 && i < 0x0F18) &&         // ANI ID + DTMF codes\r\n                !(i >= 0x0F30 && i < 0x0F50) &&         // AES KEY + F LOCK + Scramble Enable\r\n                !(i >= 0x1C00 && i < 0x1E00) &&         // DTMF contacts\r\n                !(i >= 0x0EB0 && i < 0x0ED0) &&         // Welcome strings\r\n                !(i >= 0x0EA0 && i < 0x0EA8) &&         // Voice Prompt\r\n                (bIsAll ||\r\n                 (\r\n                         !(i >= 0x0D60 && i < 0x0E28) &&     // MR Channel Attributes\r\n                         !(i >= 0x0F18 && i < 0x0F30) &&     // Scan List\r\n                         !(i >= 0x0F50 && i < 0x1C00) &&     // MR Channel Names\r\n                         !(i >= 0x0E40 && i < 0x0E70) &&     // FM Channels\r\n                         !(i >= 0x0E88 && i < 0x0E90)        // FM settings\r\n                 ))\r\n                )\r\n        {\r\n            EEPROM_WriteBuffer(i, Template,8);\r\n        }\r\n    }\r\n\r\n    if (bIsAll)\r\n    {\r\n        RADIO_InitInfo(gRxVfo, FREQ_CHANNEL_FIRST + BAND6_400MHz, 43350000);\r\n\r\n        // set the first few memory channels\r\n        for (i = 0; i < ARRAY_SIZE(gDefaultFrequencyTable); i++)\r\n        {\r\n            const uint32_t Frequency   = gDefaultFrequencyTable[i];\r\n            gRxVfo->freq_config_RX.Frequency = Frequency;\r\n            gRxVfo->freq_config_TX.Frequency = Frequency;\r\n            gRxVfo->Band               = FREQUENCY_GetBand(Frequency);\r\n            SETTINGS_SaveChannel(MR_CHANNEL_FIRST + i, 0, gRxVfo, 2);\r\n        }\r\n    }\r\n}\r\n\r\n#ifdef ENABLE_FMRADIO\r\nvoid SETTINGS_SaveFM(void)\r\n\t{\r\n\t\tunsigned int i;\r\n\r\n\t\tstruct\r\n\t\t{\r\n\t\t\tuint16_t Frequency;\r\n\t\t\tuint8_t  Channel;\r\n\t\t\tbool     IsChannelSelected;\r\n\t\t\tuint8_t  Padding[4];\r\n\t\t} State;\r\n\r\n\t\tmemset(&State, 0xFF, sizeof(State));\r\n\t\tState.Channel           = gEeprom.FM_SelectedChannel;\r\n\t\tState.Frequency         = gEeprom.FM_SelectedFrequency;\r\n\t\tState.IsChannelSelected = gEeprom.FM_IsMrMode;\r\n\r\n\t\tEEPROM_WriteBuffer(0x0E88, &State,8);\r\n\t\tfor (i = 0; i < 5; i++)\r\n\t\t\tEEPROM_WriteBuffer(0x0E40 + (i * 8), &gFM_Channels[i * 4],8);\r\n\t}\r\n#endif\r\n\r\nvoid SETTINGS_SaveVfoIndices(void)\r\n{\r\n    uint8_t State[8];\r\n\r\n#ifndef ENABLE_NOAA\r\n    EEPROM_ReadBuffer(0x0E80, State, sizeof(State));\r\n#endif\r\n\r\n    State[0] = gEeprom.ScreenChannel[0];\r\n    State[1] = gEeprom.MrChannel[0];\r\n    State[2] = gEeprom.FreqChannel[0];\r\n    State[3] = gEeprom.ScreenChannel[1];\r\n    State[4] = gEeprom.MrChannel[1];\r\n    State[5] = gEeprom.FreqChannel[1];\r\n#ifdef ENABLE_NOAA\r\n    State[6] = gEeprom.NoaaChannel[0];\r\n\t\tState[7] = gEeprom.NoaaChannel[1];\r\n#endif\r\n\r\n    EEPROM_WriteBuffer(0x0E80, State,8);\r\n}\r\n\r\nvoid SETTINGS_SaveSettings(void)\r\n{\r\n    uint8_t  State[8];\r\n    uint32_t Password[2];\r\n\r\n    State[0] = gEeprom.CHAN_1_CALL;\r\n    State[1] = gEeprom.SQUELCH_LEVEL;\r\n    State[2] = gEeprom.TX_TIMEOUT_TIMER;\r\n#ifdef ENABLE_NOAA\r\n    State[3] = gEeprom.NOAA_AUTO_SCAN;\r\n#else\r\n    State[3] = false;\r\n#endif\r\n    State[4] = gEeprom.KEY_LOCK;\r\n#ifdef ENABLE_VOX\r\n    State[5] = gEeprom.VOX_SWITCH;\r\n\t\tState[6] = gEeprom.VOX_LEVEL;\r\n#else\r\n    State[5] = false;\r\n    State[6] = 0;\r\n#endif\r\n    State[7] = gEeprom.MIC_SENSITIVITY;\r\n    EEPROM_WriteBuffer(0x0E70, State,8);\r\n\r\n//   \t\t  = (Data[0] >> 4) ==0xA ? -1 : 1;\r\n\r\n    State[0] = ( key_dir ==-1?0xB0:0xA0 ) + gEeprom.BACKLIGHT_MAX;\r\n    State[1] = gEeprom.CHANNEL_DISPLAY_MODE;\r\n    State[2] = gEeprom.CROSS_BAND_RX_TX;\r\n    State[3] = gEeprom.BATTERY_SAVE;\r\n    State[4] = gEeprom.DUAL_WATCH;\r\n    State[5] = gEeprom.BACKLIGHT_TIME;\r\n    State[6] = gEeprom.TAIL_TONE_ELIMINATION;\r\n    State[7] = gEeprom.VFO_OPEN;\r\n    EEPROM_WriteBuffer(0x0E78, State,8);\r\n\r\n    State[0] = gEeprom.BEEP_CONTROL;\r\n   // State[0] |= 0;//gEeprom.KEY_M_LONG_PRESS_ACTION << 1;\r\n//    State[1]=(uint8_t)(gEeprom.MDC1200_ID&(0x000000ff));\r\n//    State[2]=(uint8_t)((gEeprom.MDC1200_ID&0x0000ff00)>>8);\r\n//    State[3]=(uint8_t)((gEeprom.MDC1200_ID&0x00ff0000)>>16);\r\n//    State[4]=(uint8_t)((gEeprom.MDC1200_ID&0xff000000)>>24);\r\n    State[1]=(uint8_t)(gEeprom.MDC1200_ID&(0x00ff));\r\n    State[2]=(uint8_t)((gEeprom.MDC1200_ID&(0xff00))>>8);\r\n\r\n    // State[1] = 0;//gEeprom.KEY_1_SHORT_PRESS_ACTION;\r\n   // State[2] = 0;//gEeprom.KEY_1_LONG_PRESS_ACTION;\r\n    State[3] = 0;//gEeprom.KEY_2_SHORT_PRESS_ACTION;\r\n    State[4] = 0;//gEeprom.KEY_2_LONG_PRESS_ACTION;\r\n    State[5] = gEeprom.SCAN_RESUME_MODE;\r\n    State[6] = 0;//gEeprom.AUTO_KEYPAD_LOCK;\r\n#if ENABLE_CHINESE_FULL==4\r\n    State[7] = gEeprom.POWER_ON_DISPLAY_MODE;\r\n#endif\r\n    EEPROM_WriteBuffer(0x0E90, State,8);\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n    State[0] = gEeprom.KEY_M_LONG_PRESS_ACTION;\r\n    State[1] = gEeprom.KEY_1_SHORT_PRESS_ACTION;\r\n    State[2] = gEeprom.KEY_1_LONG_PRESS_ACTION;\r\n    State[3] = gEeprom.KEY_2_SHORT_PRESS_ACTION;\r\n    State[4] = gEeprom.KEY_2_LONG_PRESS_ACTION;\r\n    State[5] = 0;\r\n    State[6] = 0;\r\n    State[7] = 0;\r\n    EEPROM_WriteBuffer(0x1FF8, State, 5);\r\n#endif\r\n\r\n    memset(Password, 0xFF, sizeof(Password));\r\n#ifdef ENABLE_PWRON_PASSWORD\r\n    Password[0] = gEeprom.POWER_ON_PASSWORD;\r\n#endif\r\n    EEPROM_WriteBuffer(0x0E98, Password,8);\r\n\r\n    memset(State, 0xFF, sizeof(State));\r\n#ifdef ENABLE_VOICE\r\n    State[0] = gEeprom.VOICE_PROMPT;\r\n#endif\r\n#ifdef ENABLE_RSSI_BAR\r\n    State[1] = gEeprom.S0_LEVEL;\r\n\tState[2] = gEeprom.S9_LEVEL;\r\n#endif\r\n    EEPROM_WriteBuffer(0x0EA0, State,8);\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\n    State[0] = gEeprom.ALARM_MODE;\r\n#else\r\n    State[0] = false;\r\n#endif\r\n    State[1] = gEeprom.ROGER;\r\n    State[2] = gEeprom.REPEATER_TAIL_TONE_ELIMINATION;\r\n    State[3] = gEeprom.TX_VFO;\r\n    State[4] = gEeprom.BATTERY_TYPE;\r\n    EEPROM_WriteBuffer(0x0EA8, State,8);\r\n\r\n    State[0] = gEeprom.DTMF_SIDE_TONE;\r\n#ifdef ENABLE_DTMF_CALLING\r\n    State[1] = gEeprom.DTMF_SEPARATE_CODE;\r\n\tState[2] = gEeprom.DTMF_GROUP_CALL_CODE;\r\n\tState[3] = gEeprom.DTMF_DECODE_RESPONSE;\r\n\tState[4] = gEeprom.DTMF_auto_reset_time;\r\n#endif\r\n    State[5] = gEeprom.DTMF_PRELOAD_TIME / 10U;\r\n    State[6] = gEeprom.DTMF_FIRST_CODE_PERSIST_TIME / 10U;\r\n    State[7] = gEeprom.DTMF_HASH_CODE_PERSIST_TIME / 10U;\r\n    EEPROM_WriteBuffer(0x0ED0, State,8);\r\n\r\n    memset(State, 0xFF, sizeof(State));\r\n    State[0] = gEeprom.DTMF_CODE_PERSIST_TIME / 10U;\r\n    State[1] = gEeprom.DTMF_CODE_INTERVAL_TIME / 10U;\r\n#ifdef ENABLE_DTMF_CALLING\r\n    State[2] = gEeprom.PERMIT_REMOTE_KILL;\r\n#endif\r\n    EEPROM_WriteBuffer(0x0ED8, State,8);\r\n\r\n    State[0] = gEeprom.SCAN_LIST_DEFAULT;\r\n    State[1] = gEeprom.SCAN_LIST_ENABLED[0];\r\n    State[2] = gEeprom.SCANLIST_PRIORITY_CH1[0];\r\n    State[3] = gEeprom.SCANLIST_PRIORITY_CH2[0];\r\n    State[4] = gEeprom.SCAN_LIST_ENABLED[1];\r\n    State[5] = gEeprom.SCANLIST_PRIORITY_CH1[1];\r\n    State[6] = gEeprom.SCANLIST_PRIORITY_CH2[1];\r\n    State[7] = 0xFF;\r\n    EEPROM_WriteBuffer(0x0F18, State,8);\r\n\r\n    memset(State, 0xFF, sizeof(State));\r\n    State[0]  = gSetting_F_LOCK;\r\n//    State[1]  = gSetting_350TX;\r\n#ifdef ENABLE_DTMF_CALLING\r\n    State[2]  = gSetting_KILLED;\r\n#endif\r\n//    State[3]  = gSetting_200TX;\r\n//    State[4]  = gSetting_500TX;\r\n//    State[5]  = gSetting_350EN;\r\n    State[6]  = gSetting_ScrambleEnable;\r\n    //if (!gSetting_TX_EN)             State[7] &= ~(1u << 0);\r\n    if (!gSetting_live_DTMF_decoder) State[7] &= ~(1u << 1);\r\n    State[7] = (State[7] & ~(3u << 2)) | ((0 & 3u) << 2);\r\n\r\n#ifdef ENABLE_AM_FIX\r\n    if (!gSetting_AM_fix)            State[7] &= ~(1u << 5);\r\n#endif\r\n    State[7] = (State[7] & ~(3u << 6)) | ((2 & 3u) << 6);\r\n\r\n    EEPROM_WriteBuffer(0x0F40, State,8);\r\n}\r\n\r\nvoid SETTINGS_SaveChannel(uint8_t Channel, uint8_t VFO, const VFO_Info_t *pVFO, uint8_t Mode)\r\n{\r\n#ifdef ENABLE_NOAA\r\n    if (IS_NOAA_CHANNEL(Channel))\r\n\t\treturn;\r\n#endif\r\n\r\n    uint16_t OffsetVFO = Channel * 16;\r\n\r\n    if (IS_FREQ_CHANNEL(Channel)) { // it's a VFO, not a channel\r\n        OffsetVFO  = (VFO == 0) ? 0x0C80 : 0x0C90;\r\n        OffsetVFO += (Channel - FREQ_CHANNEL_FIRST) * 32;\r\n    }\r\n\r\n    if (Mode >= 2 || IS_FREQ_CHANNEL(Channel)) { // copy VFO to a channel\r\n        union {\r\n            uint8_t _8[8];\r\n            uint32_t _32[2];\r\n        } State;\r\n\r\n        State._32[0] = pVFO->freq_config_RX.Frequency;\r\n        State._32[1] = pVFO->TX_OFFSET_FREQUENCY;\r\n        EEPROM_WriteBuffer(OffsetVFO + 0, State._32,8);\r\n\r\n        State._8[0] =  pVFO->freq_config_RX.Code;\r\n        State._8[1] =  pVFO->freq_config_TX.Code;\r\n        State._8[2] = (pVFO->freq_config_TX.CodeType << 4) | pVFO->freq_config_RX.CodeType;\r\n        State._8[3] = (pVFO->Modulation << 4) | pVFO->TX_OFFSET_FREQUENCY_DIRECTION;\r\n        State._8[4] = 0\r\n                      | (pVFO->BUSY_CHANNEL_LOCK << 4)\r\n                      | (pVFO->OUTPUT_POWER      << 2)\r\n                      | (pVFO->CHANNEL_BANDWIDTH << 1)\r\n                      | (pVFO->FrequencyReverse & 1u)\r\n                      | (1u << 5)\r\n                      | (pVFO->FrequencyReverse  << 6);\r\n        State._8[5] = ((pVFO->DTMF_PTT_ID_TX_MODE & 7u) << 1)\r\n#ifdef ENABLE_DTMF_CALLING\r\n            | ((pVFO->DTMF_DECODING_ENABLE & 1u) << 0)\r\n#endif\r\n                ;\r\n        State._8[6] =  pVFO->STEP_SETTING;\r\n        State._8[7] =  pVFO->SCRAMBLING_TYPE;\r\n        EEPROM_WriteBuffer(OffsetVFO + 8, State._8,8);\r\n\r\n        SETTINGS_UpdateChannel(Channel, pVFO, true);\r\n\r\n        if (IS_MR_CHANNEL(Channel)) {\r\n#ifndef ENABLE_KEEP_MEM_NAME\r\n            // clear/reset the channel name\r\n            SETTINGS_SaveChannelName(Channel, \"\");\r\n#else\r\n            if (Mode >= 3) {\r\n\t\t\t\tSETTINGS_SaveChannelName(Channel, pVFO->Name);\r\n\t\t\t}\r\n#endif\r\n        }\r\n    }\r\n\r\n}\r\n\r\nvoid SETTINGS_SaveBatteryCalibration(const uint16_t * batteryCalibration)\r\n{\r\n    uint16_t buf[4];\r\n    EEPROM_WriteBuffer(0x1F40, batteryCalibration,8);\r\n    EEPROM_ReadBuffer( 0x1F48, buf, sizeof(buf));\r\n    buf[0] = batteryCalibration[4];\r\n    buf[1] = batteryCalibration[5];\r\n    EEPROM_WriteBuffer(0x1F48, buf,8);\r\n}\r\n\r\nvoid SETTINGS_SaveChannelName(uint8_t channel, const char * name)\r\n{\r\n    uint16_t offset = channel * 16;\r\n    uint8_t buf[16] = {0};\r\n    memcpy(buf, name, MIN(( int)strlen(name), MAX_EDIT_INDEX));\r\n    EEPROM_WriteBuffer(0x0F50 + offset, buf,8);\r\n    EEPROM_WriteBuffer(0x0F58 + offset, buf + 8,8);\r\n}\r\n\r\nvoid SETTINGS_UpdateChannel(uint8_t channel, const VFO_Info_t *pVFO, bool keep)\r\n{\r\n#ifdef ENABLE_NOAA\r\n    if (!IS_NOAA_CHANNEL(channel))\r\n#endif\r\n    {\r\n        uint8_t  state[8];\r\n        ChannelAttributes_t  att = {\r\n                .band = 0xf,\r\n                .compander = 0,\r\n                .scanlist1 = 0,\r\n                .scanlist2 = 0,\r\n        };        // default attributes\r\n\r\n        uint16_t offset = 0x0D60 + (channel & ~7u);\r\n        EEPROM_ReadBuffer(offset, state, sizeof(state));\r\n\r\n        if (keep) {\r\n            att.band = pVFO->Band;\r\n            att.scanlist1 = pVFO->SCANLIST1_PARTICIPATION;\r\n            att.scanlist2 = pVFO->SCANLIST2_PARTICIPATION;\r\n            att.compander = pVFO->Compander;\r\n            if (state[channel & 7u] == att.__val)\r\n                return; // no change in the attributes\r\n        }\r\n\r\n        state[channel & 7u] = att.__val;\r\n        EEPROM_WriteBuffer(offset, state,8);\r\n\r\n        gMR_ChannelAttributes[channel] = att;\r\n\r\n        if (IS_MR_CHANNEL(channel)) {\t// it's a memory channel\r\n            if (!keep) {\r\n                // clear/reset the channel name\r\n                SETTINGS_SaveChannelName(channel, \"\");\r\n            }\r\n        }\r\n    }\r\n}\r\nvoid SETTINGS_WriteBuildOptions(void)\r\n{\r\n    uint8_t buf[8] = {0};\r\n    buf[0]=0\r\n#ifdef ENABLE_FMRADIO\r\n        | (1 << 0)\r\n#endif\r\n#ifdef ENABLE_NOAA\r\n        | (1 << 1)\r\n#endif\r\n#ifdef ENABLE_VOICE\r\n        | (1 << 2)\r\n#endif\r\n#ifdef ENABLE_VOX\r\n        | (1 << 3)\r\n#endif\r\n#ifdef ENABLE_ALARM\r\n        | (1 << 4)\r\n#endif\r\n#ifdef ENABLE_TX1750\r\n        | (1 << 5)\r\n#endif\r\n#ifdef ENABLE_PWRON_PASSWORD\r\n        | (1 << 6)\r\n#endif\r\n#ifdef ENABLE_DTMF_CALLING\r\n        | (1 << 7)\r\n#endif\r\n            ;\r\n\r\n    buf[1] = 0\r\n#ifdef ENABLE_FLASHLIGHT\r\n        | (1 << 0)\r\n#endif\r\n#ifdef ENABLE_WIDE_RX\r\n        | (1 << 1)\r\n#endif\r\n#ifdef ENABLE_BYP_RAW_DEMODULATORS\r\n        | (1 << 2)\r\n#endif\r\n#ifdef ENABLE_BLMIN_TMP_OFF\r\n        | (1 << 3)\r\n#endif\r\n#ifdef ENABLE_AM_FIX\r\n        | (1 << 4)\r\n#endif\r\n            ;\r\n    EEPROM_WriteBuffer(0x1FF0, buf,8);\r\n}"
  },
  {
    "path": "settings.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef SETTINGS_H\r\n#define SETTINGS_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n#include \"frequencies.h\"\r\n#include <helper/battery.h>\r\n#include \"radio.h\"\r\n#include <driver/backlight.h>\r\n#if ENABLE_CHINESE_FULL==4\r\n\r\nenum POWER_OnDisplayMode_t {\r\n    POWER_ON_DISPLAY_MODE_NONE,\r\n    POWER_ON_DISPLAY_MODE_PIC,\r\n    POWER_ON_DISPLAY_MODE_MESSAGE\r\n\r\n};\r\ntypedef enum POWER_OnDisplayMode_t POWER_OnDisplayMode_t;\r\n#endif\r\nenum TxLockModes_t {\r\n    F_LOCK_DEF, //all default frequencies + configurable\r\n    F_LOCK_FCC,\r\n    F_LOCK_CE,\r\n    F_LOCK_GB,\r\n\r\n    F_LOCK_ALL,\t// disable TX on all frequencies\r\n    F_LOCK_NONE, // enable TX on all frequencies\r\n    F_LOCK_LEN\r\n};\r\n\r\nenum {\r\n    SCAN_RESUME_TO = 0,\r\n    SCAN_RESUME_CO,\r\n    SCAN_RESUME_SE\r\n};\r\n\r\nenum {\r\n    CROSS_BAND_OFF = 0,\r\n    CROSS_BAND_CHAN_A,\r\n    CROSS_BAND_CHAN_B\r\n};\r\n\r\nenum {\r\n    DUAL_WATCH_OFF = 0,\r\n    DUAL_WATCH_CHAN_A,\r\n    DUAL_WATCH_CHAN_B\r\n};\r\n\r\nenum {\r\n    TX_OFFSET_FREQUENCY_DIRECTION_OFF = 0,\r\n    TX_OFFSET_FREQUENCY_DIRECTION_ADD,\r\n    TX_OFFSET_FREQUENCY_DIRECTION_SUB\r\n};\r\n\r\nenum {\r\n    OUTPUT_POWER_LOW = 0,\r\n    OUTPUT_POWER_MID,\r\n    OUTPUT_POWER_HIGH\r\n};\r\n\r\n\r\nenum ACTION_OPT_t {\r\n    ACTION_OPT_NONE = 0,\r\n    ACTION_OPT_FLASHLIGHT,\r\n    ACTION_OPT_POWER,\r\n    ACTION_OPT_MONITOR,\r\n    ACTION_OPT_SCAN,\r\n    ACTION_OPT_VOX,\r\n    ACTION_OPT_ALARM,\r\n    ACTION_OPT_FM,\r\n    ACTION_OPT_1750,\r\n    ACTION_OPT_KEYLOCK,\r\n    ACTION_OPT_A_B,\r\n    ACTION_OPT_VFO_MR,\r\n    ACTION_OPT_SWITCH_DEMODUL,\r\n    ACTION_OPT_BLMIN_TMP_OFF, //BackLight Minimum Temporay OFF\r\n    ACTION_OPT_D_DCD,\r\n    ACTION_OPT_WIDTH,\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\n    ACTION_OPT_SEND_CURRENT,\r\n    ACTION_OPT_SEND_OTHER,\r\n#endif\r\n    ACTION_OPT_LEN\r\n};\r\n\r\n#ifdef ENABLE_VOICE\r\nenum VOICE_Prompt_t\r\n\t{\r\n\t\tVOICE_PROMPT_OFF = 0,\r\n\t\tVOICE_PROMPT_CHINESE,\r\n\t\tVOICE_PROMPT_ENGLISH\r\n\t};\r\n\ttypedef enum VOICE_Prompt_t VOICE_Prompt_t;\r\n#endif\r\n\r\nenum ALARM_Mode_t {\r\n    ALARM_MODE_SITE = 0,\r\n    ALARM_MODE_TONE\r\n};\r\ntypedef enum ALARM_Mode_t ALARM_Mode_t;\r\n\r\nenum ROGER_Mode_t {\r\n    ROGER_MODE_OFF = 0,\r\n    ROGER_MODE_ROGER,\r\n    ROGER_MODE_MDC_END,\r\n    ROGER_MODE_MDC_HEAD,\r\n    ROGER_MODE_MDC_BOTH,\r\n    ROGER_MODE_MDC_HEAD_ROGER\r\n\r\n};\r\ntypedef enum ROGER_Mode_t ROGER_Mode_t;\r\n\r\nenum CHANNEL_DisplayMode_t {\r\n    MDF_FREQUENCY = 0,\r\n    MDF_CHANNEL,\r\n    MDF_NAME,\r\n    MDF_NAME_FREQ\r\n};\r\ntypedef enum CHANNEL_DisplayMode_t CHANNEL_DisplayMode_t;\r\n\r\ntypedef struct {\r\n    uint8_t               ScreenChannel[2]; // current channels set in the radio (memory or frequency channels)\r\n    uint8_t               FreqChannel[2]; // last frequency channels used\r\n    uint8_t               MrChannel[2]; // last memory channels used\r\n#ifdef ENABLE_NOAA\r\n    uint8_t           NoaaChannel[2];\r\n#endif\r\n\r\n    // The actual VFO index (0-upper/1-lower) that is now used for RX,\r\n    // It is being alternated by dual watch, and flipped by crossband\r\n    uint8_t               RX_VFO;\r\n\r\n    // The main VFO index (0-upper/1-lower) selected by the user\r\n    //\r\n    uint8_t               TX_VFO;\r\n\r\n    uint8_t               field7_0xa;\r\n    uint8_t               field8_0xb;\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    uint16_t          FM_SelectedFrequency;\r\n\t\tuint8_t           FM_SelectedChannel;\r\n\t\tbool              FM_IsMrMode;\r\n\t\tuint16_t          FM_FrequencyPlaying;\r\n\t\tuint16_t          FM_LowerLimit;\r\n\t\tuint16_t          FM_UpperLimit;\r\n#endif\r\n\r\n    uint8_t               SQUELCH_LEVEL;\r\n    uint8_t               TX_TIMEOUT_TIMER;\r\n    bool                  KEY_LOCK;\r\n    bool                  VOX_SWITCH;\r\n    uint8_t               VOX_LEVEL;\r\n#ifdef ENABLE_VOICE\r\n    VOICE_Prompt_t    VOICE_PROMPT;\r\n#endif\r\n    bool                  BEEP_CONTROL;\r\n    uint8_t               CHANNEL_DISPLAY_MODE;\r\n    bool                  TAIL_TONE_ELIMINATION;\r\n    bool                  VFO_OPEN;\r\n    uint8_t               DUAL_WATCH;\r\n    uint8_t               CROSS_BAND_RX_TX;\r\n    uint8_t               BATTERY_SAVE;\r\n    uint8_t               BACKLIGHT_TIME;\r\n    uint8_t               SCAN_RESUME_MODE;\r\n    uint8_t               SCAN_LIST_DEFAULT;\r\n    bool                  SCAN_LIST_ENABLED[2];\r\n    uint8_t               SCANLIST_PRIORITY_CH1[2];\r\n    uint8_t               SCANLIST_PRIORITY_CH2[2];\r\n\r\n    uint8_t               field29_0x26;\r\n    uint8_t               field30_0x27;\r\n\r\n    uint8_t               field37_0x32;\r\n    uint8_t               field38_0x33;\r\n\r\n//    bool                  AUTO_KEYPAD_LOCK;\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\n    ALARM_Mode_t      ALARM_MODE;\r\n#endif\r\n#if ENABLE_CHINESE_FULL==4\r\n    POWER_OnDisplayMode_t POWER_ON_DISPLAY_MODE;\r\n#endif\r\n    ROGER_Mode_t          ROGER;\r\n    uint8_t               REPEATER_TAIL_TONE_ELIMINATION;\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n    uint8_t               KEY_1_SHORT_PRESS_ACTION;\r\n    uint8_t               KEY_1_LONG_PRESS_ACTION;\r\n    uint8_t               KEY_2_SHORT_PRESS_ACTION;\r\n    uint8_t               KEY_2_LONG_PRESS_ACTION;\r\n#endif\r\n    uint8_t               MIC_SENSITIVITY;\r\n    uint8_t               MIC_SENSITIVITY_TUNING;\r\n    uint8_t               CHAN_1_CALL;\r\n#ifdef ENABLE_DTMF_CALLING\r\n    char                  ANI_DTMF_ID[8];\r\n\tchar                  KILL_CODE[8];\r\n\tchar                  REVIVE_CODE[8];\r\n#endif\r\n    char                  DTMF_UP_CODE[16];\r\n\r\n    uint8_t               field57_0x6c;\r\n    uint8_t               field58_0x6d;\r\n\r\n    char                  DTMF_DOWN_CODE[16];\r\n\r\n    uint8_t               field60_0x7e;\r\n    uint8_t               field61_0x7f;\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n    char                  DTMF_SEPARATE_CODE;\r\n\tchar                  DTMF_GROUP_CALL_CODE;\r\n\tuint8_t               DTMF_DECODE_RESPONSE;\r\n\tuint8_t               DTMF_auto_reset_time;\r\n#endif\r\n    uint16_t              DTMF_PRELOAD_TIME;\r\n    uint16_t              DTMF_FIRST_CODE_PERSIST_TIME;\r\n    uint16_t              DTMF_HASH_CODE_PERSIST_TIME;\r\n    uint16_t              DTMF_CODE_PERSIST_TIME;\r\n    uint16_t              DTMF_CODE_INTERVAL_TIME;\r\n    bool                  DTMF_SIDE_TONE;\r\n#ifdef ENABLE_DTMF_CALLING\r\n    bool                  PERMIT_REMOTE_KILL;\r\n#endif\r\n    int16_t               BK4819_XTAL_FREQ_LOW;\r\n#ifdef ENABLE_NOAA\r\n    bool              NOAA_AUTO_SCAN;\r\n#endif\r\n    uint8_t               VOLUME_GAIN;\r\n    uint8_t               DAC_GAIN;\r\n\r\n    VFO_Info_t            VfoInfo[2];\r\n    uint32_t              POWER_ON_PASSWORD;\r\n    uint16_t              VOX1_THRESHOLD;\r\n    uint16_t              VOX0_THRESHOLD;\r\n\r\n    uint8_t               field77_0x95;\r\n    uint8_t               field78_0x96;\r\n    uint8_t               field79_0x97;\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n    uint8_t \t\t\t  KEY_M_LONG_PRESS_ACTION;\r\n#endif\r\n//    uint8_t               BACKLIGHT_MIN;\r\n#ifdef ENABLE_BLMIN_TMP_OFF\r\n    BLMIN_STAT_t\t\t  BACKLIGHT_MIN_STAT;\r\n#endif\r\n    uint8_t               BACKLIGHT_MAX;\r\n\r\n    BATTERY_Type_t\t\t  BATTERY_TYPE;\r\n#ifdef ENABLE_RSSI_BAR\r\n    uint8_t               S0_LEVEL;\r\n\tuint8_t               S9_LEVEL;\r\n#endif\r\n    uint32_t MDC1200_ID;\r\n} EEPROM_Config_t;\r\n\r\nextern EEPROM_Config_t gEeprom;\r\n\r\nvoid     SETTINGS_InitEEPROM(void);\r\nvoid     SETTINGS_LoadCalibration(void);\r\nuint32_t SETTINGS_FetchChannelFrequency(const int channel);\r\nvoid     SETTINGS_FetchChannelName(char *s, const int channel);\r\nvoid     SETTINGS_FactoryReset(bool bIsAll);\r\n#ifdef ENABLE_FMRADIO\r\nvoid SETTINGS_SaveFM(void);\r\n#endif\r\nvoid SETTINGS_SaveVfoIndices(void);\r\nvoid SETTINGS_SaveSettings(void);\r\nvoid SETTINGS_SaveChannelName(uint8_t channel, const char * name);\r\nvoid SETTINGS_SaveChannel(uint8_t Channel, uint8_t VFO, const VFO_Info_t *pVFO, uint8_t Mode);\r\nvoid SETTINGS_SaveBatteryCalibration(const uint16_t * batteryCalibration);\r\nvoid SETTINGS_UpdateChannel(uint8_t channel, const VFO_Info_t *pVFO, bool keep);\r\nvoid SETTINGS_WriteBuildOptions(void);\r\nextern int               key_dir;\r\n\r\n#endif"
  },
  {
    "path": "sram-overlay.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include \"ARMCM0.h\"\r\n#include \"bsp/dp32g030/pmu.h\"\r\n#include \"bsp/dp32g030/saradc.h\"\r\n#include \"bsp/dp32g030/syscon.h\"\r\n#include \"sram-overlay.h\"\r\n#include \"driver/eeprom.h\"\r\nstatic volatile uint32_t *pFlash = 0;\r\nuint32_t                  overlay_FLASH_MainClock;\r\nuint32_t                  overlay_FLASH_ClockMultiplier;\r\nuint32_t                  overlay_0x20000478;         // Nothing is using this???\r\n\r\nvoid overlay_FLASH_RebootToBootloader(void)\r\n{\r\n\toverlay_FLASH_MaskUnlock();\r\n\toverlay_FLASH_SetMaskSel(FLASH_MASK_SELECTION_NONE);\r\n\toverlay_FLASH_MaskLock();\r\n\toverlay_SystemReset();\r\n}\r\n\r\nbool overlay_FLASH_IsBusy(void)\r\n{\r\n\treturn (FLASH_ST & FLASH_ST_BUSY_MASK) != FLASH_ST_BUSY_BITS_READY;\r\n}\r\n\r\nbool overlay_FLASH_IsInitComplete(void)\r\n{\r\n\treturn (FLASH_ST & FLASH_ST_INIT_BUSY_MASK) == FLASH_ST_INIT_BUSY_BITS_COMPLETE;\r\n}\r\n\r\nbool overlay_FLASH_IsNotEmpty(void)\r\n{\r\n    return (FLASH_ST & 4) != 4;\r\n}\r\n\r\nvoid overlay_FLASH_Start(void)\r\n{\r\n\toverlay_FLASH_Unlock();\r\n\tFLASH_START |= FLASH_START_START_BITS_START;\r\n}\r\n\r\nvoid overlay_FLASH_Init(FLASH_READ_MODE ReadMode)\r\n{\r\n\toverlay_FLASH_WakeFromDeepSleep();\r\n\toverlay_FLASH_SetMode(FLASH_MODE_READ_AHB);\r\n\toverlay_FLASH_SetReadMode(ReadMode);\r\n\toverlay_FLASH_SetEraseTime();\r\n\toverlay_FLASH_SetProgramTime();\r\n\toverlay_FLASH_Lock();\r\n}\r\n\r\nvoid overlay_FLASH_MaskLock(void)\r\n{\r\n\tFLASH_MASK = (FLASH_MASK & ~FLASH_MASK_LOCK_MASK) | FLASH_MASK_LOCK_BITS_SET;\r\n}\r\n\r\nvoid overlay_FLASH_SetMaskSel(FLASH_MASK_SELECTION Mask)\r\n{\r\n\tFLASH_MASK = (FLASH_MASK & ~FLASH_MASK_SEL_MASK) | ((Mask << FLASH_MASK_SEL_SHIFT) & FLASH_MASK_SEL_MASK);\r\n}\r\n\r\nvoid overlay_FLASH_MaskUnlock(void)\r\n{\r\n\tFLASH_MASK = (FLASH_MASK & ~FLASH_MASK_LOCK_MASK) | FLASH_MASK_LOCK_BITS_NOT_SET;\r\n}\r\n\r\nvoid overlay_FLASH_Lock(void)\r\n{\r\n\tFLASH_LOCK = FLASH_LOCK_LOCK_BITS_LOCK;\r\n}\r\n\r\nvoid overlay_FLASH_Unlock(void)\r\n{\r\n\tFLASH_UNLOCK = FLASH_UNLOCK_UNLOCK_BITS_UNLOCK;\r\n}\r\n\r\nuint32_t overlay_FLASH_ReadByAHB(uint32_t Offset)\r\n{\r\n\r\n\treturn pFlash[(Offset & ~3U) / 4];\r\n}\r\n\r\nuint32_t overlay_FLASH_ReadByAPB(uint32_t Offset)\r\n{\r\n\tuint32_t Data;\r\n\r\n\twhile (overlay_FLASH_IsBusy()) {}\r\n\r\n\toverlay_FLASH_SetMode(FLASH_MODE_READ_APB);\r\n\tFLASH_ADDR = Offset >> 2;\r\n\r\n\toverlay_FLASH_Start();\r\n\r\n\twhile (overlay_FLASH_IsBusy()) {}\r\n\r\n\tData = FLASH_RDATA;\r\n\r\n\toverlay_FLASH_SetMode(FLASH_MODE_READ_AHB);\r\n\toverlay_FLASH_Lock();\r\n\r\n\treturn Data;\r\n}\r\n\r\nvoid overlay_FLASH_SetArea(FLASH_AREA Area)\r\n{\r\n\tFLASH_CFG = (FLASH_CFG & ~FLASH_CFG_NVR_SEL_MASK) | ((Area << FLASH_CFG_NVR_SEL_SHIFT) & FLASH_CFG_NVR_SEL_MASK);\r\n}\r\n\r\nvoid overlay_FLASH_SetReadMode(FLASH_READ_MODE Mode)\r\n{\r\n\tif (Mode == FLASH_READ_MODE_1_CYCLE)\r\n\t\tFLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_BITS_1_CYCLE;\r\n\telse\r\n\tif (Mode == FLASH_READ_MODE_2_CYCLE)\r\n\t\tFLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_BITS_2_CYCLE;\r\n}\r\n\r\nvoid overlay_FLASH_SetEraseTime(void)\r\n{\r\n\tFLASH_ERASETIME = ((overlay_FLASH_ClockMultiplier & 0xFFFFU) * 0x1A00000U) + (overlay_FLASH_ClockMultiplier * 3600U);\r\n}\r\n\r\nvoid overlay_FLASH_WakeFromDeepSleep(void)\r\n{\r\n\tFLASH_CFG = (FLASH_CFG & ~FLASH_CFG_DEEP_PD_MASK) | FLASH_CFG_DEEP_PD_BITS_NORMAL;\r\n\twhile (!overlay_FLASH_IsInitComplete()) {}\r\n}\r\n\r\nvoid overlay_FLASH_SetMode(FLASH_MODE Mode)\r\n{\r\n\tFLASH_CFG = (FLASH_CFG & ~FLASH_CFG_MODE_MASK) | ((Mode << FLASH_CFG_MODE_SHIFT) & FLASH_CFG_MODE_MASK);\r\n}\r\n\r\nvoid overlay_FLASH_SetProgramTime(void)\r\n{\r\n\tFLASH_PROGTIME = overlay_FLASH_ClockMultiplier * 45074;\r\n}\r\n\r\nvoid overlay_SystemReset(void)\r\n{\r\n\t// Lifted from core_cm0.h to preserve function order in the object file.\r\n\r\n\t__DSB();     // Ensure all outstanding memory accesses included buffered write are completed before reset\r\n\tSCB->AIRCR = (0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk;\r\n\t__DSB();     // Ensure completion of memory access\r\n\r\n\tfor (;;)     // wait until reset\r\n\t\t__NOP();\r\n}\r\n\r\nuint32_t overlay_FLASH_ReadNvrWord(uint32_t Offset)\r\n{\r\n\tuint32_t Data;\r\n\toverlay_FLASH_SetArea(FLASH_AREA_NVR);\r\n\tData = overlay_FLASH_ReadByAHB(Offset);\r\n\toverlay_FLASH_SetArea(FLASH_AREA_MAIN);\r\n\treturn Data;\r\n}\r\n\r\nvoid overlay_FLASH_ConfigureTrimValues(void)\r\n{\r\n\tuint32_t Data;\r\n\r\n\toverlay_FLASH_SetArea(FLASH_AREA_NVR);\r\n\r\n\tSYSCON_CHIP_ID0 = overlay_FLASH_ReadByAPB(0xF018);\r\n\tSYSCON_CHIP_ID1 = overlay_FLASH_ReadByAPB(0xF01C);\r\n\tSYSCON_CHIP_ID2 = overlay_FLASH_ReadByAPB(0xF020);\r\n\tSYSCON_CHIP_ID3 = overlay_FLASH_ReadByAPB(0xF024);\r\n\r\n\tSYSCON_RC_FREQ_DELTA   = overlay_FLASH_ReadByAHB(0x07C8);\r\n\tSYSCON_VREF_VOLT_DELTA = overlay_FLASH_ReadByAHB(0x07C4);\r\n\r\n\tPMU_TRIM_POW0 = overlay_FLASH_ReadByAHB(0x07E4);\r\n\tPMU_TRIM_POW1 = overlay_FLASH_ReadByAHB(0x07E0);\r\n\tPMU_TRIM_RCHF = overlay_FLASH_ReadByAHB(0x07D8);\r\n\tPMU_TRIM_RCLF = overlay_FLASH_ReadByAHB(0x07D4);\r\n\tPMU_TRIM_OPA  = overlay_FLASH_ReadByAHB(0x07D0);\r\n\tPMU_TRIM_PLL  = overlay_FLASH_ReadByAHB(0x07CC);\r\n\r\n\toverlay_0x20000478 = overlay_FLASH_ReadByAHB(0x07B8);\r\n\r\n\tData                = overlay_FLASH_ReadByAHB(0x07BC);\r\n\tSYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SARADC_MASK) | SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE;\r\n\tSARADC_CALIB_OFFSET = ((Data & 0xFFFF) << SARADC_CALIB_OFFSET_OFFSET_SHIFT) & SARADC_CALIB_OFFSET_OFFSET_MASK;\r\n\tSARADC_CALIB_KD     = (((Data >> 16) & 0xFFFF) << SARADC_CALIB_KD_KD_SHIFT) & SARADC_CALIB_KD_KD_MASK;\r\n\toverlay_FLASH_SetArea(FLASH_AREA_MAIN);\r\n}\r\n\r\n\r\nvoid ProgramMoreWords(uint32_t DestAddr, const uint32_t *words,uint32_t num)\r\n{\r\n    const uint32_t *pWord = (const uint32_t *)words;\r\n\r\n    while (overlay_FLASH_IsBusy()) {}//ѯFLASHæ־ȴREADY״̬\r\n    overlay_FLASH_SetMode(FLASH_MODE_PROGRAM); //ģʽΪ̲\r\n\r\n    for (uint32_t  i = 0; i < num; i++) { //дݣж PROG_BUF_EMPTY λǷΪ 0Ϊ 0 ʱдһ̵֣Ϊ 1 ʱȴд룩ֱдȫдɣ\r\n        FLASH_ADDR = (DestAddr+i*4)>>2 ; //д̵ַΪλ\r\n\r\n        FLASH_WDATA= *pWord++; //ݷŵݼĴУ\r\n        overlay_FLASH_Start();//FLASHSTART\r\n       if(i)\r\n        while(overlay_FLASH_IsNotEmpty()){\r\n        };\r\n\r\n    }\r\n    while (overlay_FLASH_IsBusy()) {}//ѯFLASHæ־ȴREADY״̬\r\n    overlay_FLASH_SetMode(FLASH_CFG_MODE_VALUE_READ_AHB); //ģʽΪ̲\r\n    overlay_FLASH_Lock();\r\n}\r\n\r\nvoid ProgramWords(uint32_t DestAddr,uint32_t words)\r\n{\r\n    while (overlay_FLASH_IsBusy()) {}//ѯFLASHæ־ȴREADY״̬\r\n\r\n    overlay_FLASH_SetMode(FLASH_MODE_PROGRAM); //ģʽΪ̲\r\n\r\n    FLASH_ADDR = DestAddr>>2 ; //д̵ַΪλ\r\n    FLASH_WDATA= words; //ݷŵݼĴУ\r\n    overlay_FLASH_Start();//FLASHSTART\r\n    while (overlay_FLASH_IsBusy()) {}//ѯFLASHæ־ȴREADY״̬\r\n    overlay_FLASH_SetMode(FLASH_CFG_MODE_VALUE_READ_AHB); //ģʽΪ̲\r\n    overlay_FLASH_Lock();\r\n}\r\n\r\n//CP_EEPROM_TO_FLASH(0x5000,0xa000,10*1024);\r\n\r\nvoid CP_EEPROM_TO_FLASH(uint32_t eeprom_add,uint32_t flash_add,uint32_t size)\r\n{\r\n    for (int i = 0; i < size/4; ++i) {\r\n        uint32_t c;\r\n        EEPROM_ReadBuffer(eeprom_add + i * 4, (uint8_t*)&c, 4);\r\n        __disable_irq();\r\n        ProgramWords(i*4+flash_add, c);\r\n    }\r\n}\r\n"
  },
  {
    "path": "sram-overlay.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef SRAM_OVERLAY_H\r\n#define SRAM_OVERLAY_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n#include \"driver/flash.h\"\r\n\r\nextern uint32_t overlay_FLASH_MainClock __attribute__((section(\".srambss\")));\r\nextern uint32_t overlay_FLASH_ClockMultiplier __attribute__((section(\".srambss\")));\r\nextern uint32_t overlay_0x20000478 __attribute__((section(\".srambss\")));\r\n\r\nvoid overlay_FLASH_RebootToBootloader(void)  __attribute__((section(\".sramtext\")));\r\nbool overlay_FLASH_IsBusy(void) __attribute__((section(\".sramtext\")));\r\nbool overlay_FLASH_IsInitComplete(void) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_Start(void) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_Init(FLASH_READ_MODE ReadMode) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_MaskLock(void) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_SetMaskSel(FLASH_MASK_SELECTION Mask) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_MaskUnlock(void) __attribute__((noreturn)) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_Lock(void) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_Unlock(void) __attribute__((section(\".sramtext\")));\r\nuint32_t overlay_FLASH_ReadByAHB(uint32_t Offset) __attribute__((section(\".sramtext\")));\r\nuint32_t overlay_FLASH_ReadByAPB(uint32_t Offset) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_SetArea(FLASH_AREA Area) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_SetReadMode(FLASH_READ_MODE Mode) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_SetEraseTime(void) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_WakeFromDeepSleep(void) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_SetMode(FLASH_MODE Mode) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_SetProgramTime(void) __attribute__((section(\".sramtext\")));\r\nvoid overlay_SystemReset(void) __attribute__((noreturn)) __attribute__((section(\".sramtext\")));\r\nuint32_t overlay_FLASH_ReadNvrWord(uint32_t Offset) __attribute__((section(\".sramtext\")));\r\nvoid overlay_FLASH_ConfigureTrimValues(void) __attribute__((section(\".sramtext\")));\r\nvoid ProgramWords(uint32_t DestAddr,uint32_t words)__attribute__((section(\".sramtext\")));\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "start.S",
    "content": "# Copyright 2023 Dual Tachyon\r\n# https://github.com/DualTachyon\r\n#\r\n# Licensed under the Apache License, Version 2.0 (the \"License\");\r\n# you may not use this file except in compliance with the License.\r\n# You may obtain a copy of the License at\r\n#\r\n#     http://www.apache.org/licenses/LICENSE-2.0\r\n#\r\n# Unless required by applicable law or agreed to in writing, software\r\n# distributed under the License is distributed on an \"AS IS\" BASIS,\r\n# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n# See the License for the specific language governing permissions and\r\n# limitations under the License.\r\n\r\n\t.cpu cortex-m0\r\n\t.fpu softvfp\r\n\t.thumb\r\n\r\n\t.global Stack\r\n\t.global HandlerReset\r\n\t.global Main\r\n\r\n\t.global OVERLAY_Install\r\n\t.global BOARD_FLASH_Init\r\n\t.global BSS_Init\r\n\t.global TIM0Handler\r\n\t.global RTCHandler\r\n\r\n\t.global SystickHandler\r\n\t.weak SystickHandler\r\n    .weak TIM0Handler\r\n    .weak RTCHandler\r\n\r\n\r\n\t.section .text.isr\r\n\r\nStack:\r\n\t.long\t0x20003FF0\r\nReset:\r\n\t.long\tHandlerReset + 1\r\nNMI:\r\n\t.long\tHandlerNMI + 1\r\nHardFault:\r\n\t.long\tHandlerHardFault + 1\r\nReserved_10:\r\n\t.long\t0\r\nReserved_14:\r\n\t.long\t0\r\nReserved_18:\r\n\t.long\t0\r\nReserved_1C:\r\n\t.long\t0\r\nReserved_20:\r\n\t.long\t0\r\nReserved_24:\r\n\t.long\t0\r\nReserved_28:\r\n\t.long\t0\r\nSVCall:\r\n\t.long\tHandlerSVCall + 1\r\nReserved_30:\r\n\t.long\t0\r\nReserved_34:\r\n\t.long\t0\r\nPendSV:\r\n\t.long\tHandlerPendSV + 1\r\nSysTick:\r\n\t.long\tSystickHandler + 1\r\nWWDT:\r\n\t.long\tHandlerWWDT + 1\r\nIWDT:\r\n\t.long\tHandlerIWDT + 1\r\nRTC:\r\n\t.long\tRTCHandler + 1\r\nDMA:\r\n\t.long\tHandlerDMA + 1\r\nSARADC:\r\n\t.long\tHandlerSARADC + 1\r\nTIMER_BASE0:\r\n\t.long\tTIM0Handler + 1\r\nTIMER_BASE1:\r\n\t.long\tHandlerTIMER_BASE1 + 1\r\nTIMER_PLUS0:\r\n\t.long\tHandlerTIMER_PLUS0 + 1\r\nTIMER_PLUS1:\r\n\t.long\tHandlerTIMER_PLUS1 + 1\r\nPWM_BASE0:\r\n\t.long\tHandlerPWM_BASE0 + 1\r\nPWM_BASE1:\r\n\t.long\tHandlerPWM_BASE1 + 1\r\nPWM_PLUS0:\r\n\t.long\tHandlerPWM_PLUS0 + 1\r\nPWM_PLUS1:\r\n\t.long\tHandlerPWM_PLUS1 + 1\r\nUART0:\r\n\t.long\tHandlerUART0 + 1\r\nUART1:\r\n\t.long\tHandlerUART1 + 1\r\nUART2:\r\n\t.long\tHandlerUART2 + 1\r\nSPI0:\r\n\t.long\tHandlerSPI0 + 1\r\nSPI1:\r\n\t.long\tHandlerSPI1 + 1\r\nIIC0:\r\n\t.long\tHandlerIIC0 + 1\r\nIIC1:\r\n\t.long\tHandlerIIC1 + 1\r\nCMP:\r\n\t.long\tHandlerCMP + 1\r\nTIMER_BASE2:\r\n\t.long\tHandlerTIMER_BASE2 + 1\r\nGPIOA5:\r\n\t.long\tHandlerGPIOA5 + 1\r\nGPIOA6:\r\n\t.long\tHandlerGPIOA6 + 1\r\nGPIOA7:\r\n\t.long\tHandlerGPIOA7 + 1\r\nGPIOB0:\r\n\t.long\tHandlerGPIOB0 + 1\r\nGPIOB1:\r\n\t.long\tHandlerGPIOB1 + 1\r\nGPIOC0:\r\n\t.long\tHandlerGPIOC0 + 1\r\nGPIOC1:\r\n\t.long\tHandlerGPIOC1 + 1\r\nGPIOA:\r\n\t.long\tHandlerGPIOA + 1\r\nGPIOB:\r\n\t.long\tHandlerGPIOB + 1\r\nGPIOC:\r\n\t.long\tHandlerGPIOC + 1\r\n\r\n\t.section .text\r\n\r\nHandlerNMI:\r\n\tb\t.\r\n\r\nHandlerHardFault:\r\n\tb\t.\r\n\r\nHandlerSVCall:\r\n\tb\t.\r\n\r\nHandlerPendSV:\r\n\tb\t.\r\n\r\nSystickHandler:\r\n\tbx\tlr\r\n\r\nHandlerWWDT:\r\n\tb\t.\r\n\r\nHandlerIWDT:\r\n\tb\t.\r\n\r\nRTCHandler:\r\n\tbx\tlr\r\n\r\nHandlerDMA:\r\n\tb\t.\r\n\r\nHandlerSARADC:\r\n\tb\t.\r\n\r\nTIM0Handler:\r\n\tbx\tlr\r\n\r\nHandlerTIMER_BASE1:\r\n\tb\t.\r\n\r\nHandlerTIMER_PLUS0:\r\n\tb\t.\r\n\r\nHandlerTIMER_PLUS1:\r\n\tb\t.\r\n\r\nHandlerPWM_BASE0:\r\n\tb\t.\r\n\r\nHandlerPWM_BASE1:\r\n\tb\t.\r\n\r\nHandlerPWM_PLUS0:\r\n\tb\t.\r\n\r\nHandlerPWM_PLUS1:\r\n\tb\t.\r\n\r\nHandlerUART0:\r\n\tb\t.\r\n\r\nHandlerUART1:\r\n\tb\t.\r\n\r\nHandlerUART2:\r\n\tb\t.\r\n\r\nHandlerSPI0:\r\n\tb\t.\r\n\r\nHandlerSPI1:\r\n\tb\t.\r\n\r\nHandlerIIC0:\r\n\tb\t.\r\n\r\nHandlerIIC1:\r\n\tb\t.\r\n\r\nHandlerCMP:\r\n\tb\t.\r\n\r\nHandlerTIMER_BASE2:\r\n\tb\t.\r\n\r\nHandlerGPIOA5:\r\n\tb\t.\r\n\r\nHandlerGPIOA6:\r\n\tb\t.\r\n\r\nHandlerGPIOA7:\r\n\tb\t.\r\n\r\nHandlerGPIOB0:\r\n\tb\t.\r\n\r\nHandlerGPIOB1:\r\n\tb\t.\r\n\r\nHandlerGPIOC0:\r\n\tb\t.\r\n\r\nHandlerGPIOC1:\r\n\tb\t.\r\n\r\nHandlerGPIOA:\r\n\tb\t.\r\n\r\nHandlerGPIOB:\r\n\tb\t.\r\n\r\nHandlerGPIOC:\r\n\tb\t.\r\n\r\nHandlerReset:\r\n\tldr\tr0, =0x20003FF0\r\n\tmov\tsp, r0\r\n\tbl\tDATA_Init\r\n\tbl\tBSS_Init\r\n#if defined(ENABLE_OVERLAY)\r\n\tbl\tBOARD_FLASH_Init\r\n#endif\r\n\tbl\tMain\r\n\tb \t.\r\n\r\n"
  },
  {
    "path": "ui/aircopy.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n\r\n#include <string.h>\r\n\r\n#include \"app/aircopy.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"ui/aircopy.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/inputbox.h\"\r\n\r\nvoid UI_DisplayAircopy(void)\r\n{\r\nchar String[16] = {0};\r\n    char *pPrintStr = { 0 };\r\nUI_DisplayClear();\r\n    if (gAircopyState == AIRCOPY_READY) {\r\n        pPrintStr = \"AIR COPY(RDY)\";\r\n    } else if (gAircopyState == AIRCOPY_TRANSFER) {\r\n        pPrintStr = \"AIR COPY\";\r\n    } else {\r\n        pPrintStr = \"AIR COPY(CMP)\";\r\n    }\r\n\r\n    UI_PrintStringSmall(String, 2, 127, 0);\r\n\r\n    if (gInputBoxIndex == 0)\r\n    {\r\n        uint32_t frequency = gRxVfo->freq_config_RX.Frequency;\r\n        sprintf(String, \"%3u.%05u\", frequency / 100000, frequency % 100000);\r\n        // show the remaining 2 small frequency digits\r\n        UI_PrintStringSmall(String + 7, 97, 0, 3);\r\n        String[7] = 0;\r\n        // show the main large frequency digits\r\n        UI_DisplayFrequency(String, 16, 2, false);\r\n    }\r\n    else {\r\n        const char * ascii = INPUTBOX_GetAscii();\r\n        sprintf(String, \"%.3s.%.3s\",ascii, ascii + 3);\r\n        UI_DisplayFrequency(String, 16, 2, false);\r\n    }\r\n\r\n    memset(String, 0, sizeof(String));\r\n    if (gAirCopyIsSendMode == 0){\r\n        sprintf(String, \"RCV:%u E:%u\", gAirCopyBlockNumber, gErrorsDuringAirCopy);\r\n} else if (gAirCopyIsSendMode == 1) {\r\n        sprintf(String, \"SND:%u\", gAirCopyBlockNumber);\r\n        }\r\n    UI_PrintStringSmall(String, 2, 127, 4);\r\n\r\n    ST7565_BlitFullScreen();\r\n}\r\n\r\n#endif\r\n"
  },
  {
    "path": "ui/aircopy.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_AIRCOPY_H\r\n#define UI_AIRCOPY_H\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n\tvoid UI_DisplayAircopy(void);\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "ui/battery.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include <assert.h>\r\n#include <stddef.h>\r\n#include <string.h>\r\n\r\n#include \"bitmaps.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"functions.h\"\r\n#include \"ui/battery.h\"\r\n#include \"../misc.h\"\r\n\r\nvoid UI_DrawBattery(uint8_t *bitmap, uint8_t level, uint8_t blink) {\r\n    if (level < 2 && blink == 1) {\r\n        memset(bitmap, 0, sizeof(BITMAP_BatteryLevel1));\r\n        return;\r\n    }\r\n\r\n    memcpy(bitmap, BITMAP_BatteryLevel1, sizeof(BITMAP_BatteryLevel1));\r\n\r\n    if (level <= 2) {\r\n        return;\r\n    }\r\n\r\n    const uint8_t bars = MIN(4, level - 2);\r\n    for (int i = 0; i < bars; i++) {\r\n#ifndef ENABLE_REVERSE_BAT_SYMBOL\r\n        memcpy(bitmap + sizeof(BITMAP_BatteryLevel1) - 4 - (i * 3), BITMAP_BatteryLevel, 2);\r\n#else\r\n        memcpy(bitmap + 3 + (i * 3) + 0, BITMAP_BatteryLevel, 2);\r\n#endif\r\n    }\r\n}\r\n\r\nvoid UI_DisplayBattery(uint8_t level, uint8_t blink) {\r\n    uint8_t bitmap[sizeof(BITMAP_BatteryLevel1)];\r\n    UI_DrawBattery(bitmap, level, blink);\r\n    ST7565_DrawLine(LCD_WIDTH - sizeof(bitmap), 0, bitmap, sizeof(bitmap));\r\n}"
  },
  {
    "path": "ui/battery.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_BATTERY_H\r\n#define UI_BATTERY_H\r\n\r\n#include <stdint.h>\r\nvoid UI_DrawBattery(uint8_t* bitmap, uint8_t level, uint8_t blink);\r\nvoid UI_DisplayBattery(uint8_t Level, uint8_t blink);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "ui/fmradio.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifdef ENABLE_FMRADIO\r\n\r\n#include <string.h>\r\n\r\n#include \"app/fm.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/fmradio.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/ui.h\"\r\n#include \"chinese.h\"\r\nvoid UI_DisplayFM(void)\r\n{\r\n    char String[16] = {0};\r\n    char *pPrintStr = String;\r\nUI_DisplayClear();\r\n    UI_PrintStringSmall(\"FM\", 0, 127, 0);\r\n\r\n    if (gAskToSave) {\r\n        pPrintStr = 存置问;\r\n    } else if (gAskToDelete) {\r\n        pPrintStr = 删除问;\r\n    } else if (gFM_ScanState == FM_SCAN_OFF) {\r\n        if (gEeprom.FM_IsMrMode) {\r\n            sprintf(String, \"MR(CH%02u)\", gEeprom.FM_SelectedChannel + 1);\r\n            pPrintStr = String;\r\n        } else {\r\n            pPrintStr = \"VFO\";\r\n            for (unsigned int i = 0; i < 20; i++) {\r\n                if (gEeprom.FM_FrequencyPlaying == gFM_Channels[i]) {\r\n                    sprintf(String, \"VFO(CH%02u)\", i + 1);\r\n                    pPrintStr = String;\r\n                    break;\r\n                }\r\n            }\r\n        }\r\n    } else if (gFM_AutoScan) {\r\n        sprintf(String, \"A-SCAN(%u)\", gFM_ChannelPosition + 1);\r\n        pPrintStr = String;\r\n    } else {\r\n        pPrintStr = \"M-SCAN\";\r\n    }\r\n\r\n    UI_PrintStringSmall(pPrintStr, 0, 127, 2);\r\n\r\n    memset(String, 0, sizeof(String));\r\n    if (gAskToSave || (gEeprom.FM_IsMrMode && gInputBoxIndex > 0)) {\r\n        UI_GenerateChannelString(String, gFM_ChannelPosition);\r\n    } else if (gAskToDelete) {\r\n        sprintf(String, \"CH-%02u\", gEeprom.FM_SelectedChannel + 1);\r\n    } else {\r\n        if (gInputBoxIndex == 0) {\r\n            sprintf(String, \"%3d.%d\", gEeprom.FM_FrequencyPlaying / 10, gEeprom.FM_FrequencyPlaying % 10);\r\n        } else {\r\n            const char * ascii = INPUTBOX_GetAscii();\r\n            sprintf(String, \"%.3s.%.1s\",ascii, ascii + 3);\r\n        }\r\n\r\n        UI_DisplayFrequency(String, 32, 4, gInputBoxIndex == 0);\r\n        ST7565_BlitFullScreen();\r\n        return;\r\n    }\r\n\r\n    UI_PrintStringSmall(String, 0, 127, 4);\r\n\r\n    ST7565_BlitFullScreen();\r\n}\r\n\r\n#endif\r\n"
  },
  {
    "path": "ui/fmradio.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_FM_H\r\n#define UI_FM_H\r\n\r\n#ifdef ENABLE_FMRADIO\r\n\tvoid UI_DisplayFM(void);\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "ui/helper.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <string.h>\r\n#include \"driver/uart.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"font.h\"\r\n#include \"ui/menu.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"misc.h\"\r\n#include \"chinese.h\"\r\n#include \"driver/eeprom.h\"\r\n\r\n#ifndef ARRAY_SIZE\r\n#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0]))\r\n#endif\r\n#define IS_BIT_SET(byte, bit) ((byte>>bit) & (1))\r\n\r\nvoid set_bit(uint8_t *value, uint8_t bit_position) {\r\n//    if (bit_value == 0) {\r\n//        *value = *value & ~(1 << bit_position);\r\n//    } else {\r\n    *value = *value | (1 << bit_position);\r\n//    }\r\n}\r\n\r\nuint8_t is_chn(uint8_t num) {\r\n#if ENABLE_CHINESE_FULL != 0\r\n    if (num >= 0x80) return 1;\r\n    return 255;\r\n#else\r\n    if (num >= 1 && num < 10)return num - 1;\r\n    else if (num > 10 && num < 32)return num - 2;\r\n    else if (num > 126 && num <= 233)return num - 97;\r\n    else return 255;\r\n\r\n#endif\r\n}\r\n\r\nbool isChineseChar(char a, uint8_t now_index, uint8_t sum_index) {\r\n    if ((uint8_t) a >= 0x80 && now_index < sum_index) return 1;\r\n    return 0;\r\n}\r\n\r\nvoid UI_GenerateChannelString(char *pString, const uint8_t Channel) {\r\n    unsigned int i;\r\n\r\n    if (gInputBoxIndex == 0) {\r\n        sprintf(pString, \"CH-%02u\", Channel + 1);\r\n        return;\r\n    }\r\n\r\n    pString[0] = 'C';\r\n    pString[1] = 'H';\r\n    pString[2] = '-';\r\n    for (i = 0; i < 2; i++)\r\n        pString[i + 3] = (gInputBox[i] == 10) ? '-' : gInputBox[i] + '0';\r\n}\r\n\r\nbool CHINESE_JUDGE(char *name, uint8_t len) {\r\n    for (int i = 0; i < len; i++)\r\n        if ((uint8_t) name[i] >= 0x80 && i != len - 1 && name[i + 1] != 0)return 1;\r\n\r\n    return 0;\r\n}\r\n\r\n\r\nvoid UI_GenerateChannelStringEx(char *pString, const bool bShowPrefix, const uint8_t ChannelNumber) {\r\n    if (gInputBoxIndex > 0) {\r\n        for (unsigned int i = 0; i < 3; i++) {\r\n            pString[i] = (gInputBox[i] == 10) ? '-' : gInputBox[i] + '0';\r\n        }\r\n\r\n        pString[3] = 0;\r\n        return;\r\n    }\r\n\r\n    if (bShowPrefix) {\r\n        // BUG here? Prefixed NULLs are allowed\r\n        sprintf(pString, \"CH-%03u\", ChannelNumber + 1);\r\n    } else if (ChannelNumber == 0xFF) {\r\n        strcpy(pString, \"NULL\");\r\n    } else {\r\n        sprintf(pString, \"%03u\", ChannelNumber + 1);\r\n    }\r\n}\r\n\r\n\r\n// Example usage:\r\n// UI_PrintChar('A', 0, 0, 16);\r\n\r\n// Example usage:\r\n// UI_PrintChar('A', 0, 0, 8);\r\n\r\n//void UI_PrintCharSmall(char character, uint8_t Start, uint8_t Line) {\r\n//    const uint8_t char_width = ARRAY_SIZE(gFontSmall[0]);\r\n//\r\n//    // Calculate the position for the character\r\n//    uint8_t *pFb = gFrameBuffer[Line] + Start + (char_width + 1) / 2;\r\n//\r\n//    // Display the character if it's a printable charactergFontBigDigits\r\n//    if (character > ' ') {\r\n//        const unsigned int index = (unsigned int) character - ' ' - 1;\r\n//        if (index < ARRAY_SIZE(gFontSmall)) {\r\n//            memmove(pFb, &gFontSmall[index], char_width);\r\n//        }\r\n//    }\r\n//}\r\n\r\nvoid UI_PrintStringSmall(const char *pString, uint8_t Start, uint8_t End, uint8_t Line) {\r\n\r\n#ifdef ENABLE_ENGLISH\r\n    const size_t Length = strlen(pString);\r\n\tsize_t       i;\r\n\r\n\tconst unsigned int char_width   = ARRAY_SIZE(gFontSmall[0]);\r\n\tconst unsigned int char_spacing = char_width + 1;\r\n\r\n\tif (End > Start)\r\n\t\tStart += (((End - Start) - (Length * char_spacing)) + 1) / 2;\r\n\r\n\r\n\tuint8_t            *pFb         = gFrameBuffer[Line] + Start;\r\n\tfor (i = 0; i < Length; i++)\r\n\t{\r\n\t\tif (pString[i] > ' ')\r\n\t\t{\r\n\t\t\tconst unsigned int index = (unsigned int)pString[i] - ' ' - 1;\r\n\t\t\tif (index < ARRAY_SIZE(gFontSmall))\r\n\t\t\t\tmemmove(pFb + (i * char_spacing) + 1, &gFontSmall[index], char_width);\r\n\t\t}\r\n\t}\r\n#else\r\n\r\n    bool flag_move = 0;\r\n\r\n    uint8_t Length = strlen(pString);\r\n\r\n    if (show_move_flag) {\r\n#if ENABLE_CHINESE_FULL == 0\r\n        Length = Length > 7 ? 7 : Length;\r\n//#else\r\n//        #ifdef ENABLE_PINYIN == 0\r\n////        if(PINYIN_NUM==0) //拼音判断\r\n//            #endif\r\n//        Length = Length > 14 ? 14 : Length;\r\n\r\n#endif\r\n        flag_move = 1;\r\n        show_move_flag = 0;\r\n\r\n    }\r\n    uint8_t sum_pixel = 0;\r\n    uint16_t true_char[Length];\r\n    uint8_t cn_flag[Length];\r\n    uint8_t char_num = 0;\r\n    for (size_t j = 0; j < Length; j++) {\r\n\r\n        uint8_t chn_judge = is_chn(pString[j]);\r\n        if (chn_judge == 255 && pString[j] != '\\n' && pString[j] != '\\0') {\r\n            true_char[char_num] = pString[j];\r\n            cn_flag[char_num] = 0;\r\n\r\n            char_num++;\r\n            sum_pixel += 7;\r\n        } else if (chn_judge != 255) {\r\n            cn_flag[char_num] = 1;\r\n\r\n#if ENABLE_CHINESE_FULL != 0\r\n\r\n            true_char[char_num] = (pString[j] << 8) | pString[j + 1];\r\n            j++;\r\n#else\r\n            true_char[char_num] = chn_judge;\r\n#endif\r\n\r\n            flag_move = 1;\r\n            char_num++;\r\n            sum_pixel += 13;\r\n        }\r\n    }\r\n    if (End > Start)\r\n        Start += (((End - Start) - (sum_pixel)) + 1) / 2;\r\n    uint8_t *pFb = gFrameBuffer[Line] + Start;\r\n    uint8_t *pFb1 = gFrameBuffer[Line + 1] + Start;\r\n    uint8_t now_pixel = 0;\r\n    for (unsigned short i = 0; i < char_num; i++) {\r\n        if (cn_flag[i] == 0) {\r\n            if (true_char[i] > ' ') {\r\n                const unsigned int index = (unsigned int) true_char[i] - ' ' - 1;\r\n#if ENABLE_CHINESE_FULL == 0\r\n\r\n                if (index < ARRAY_SIZE(gFontSmall)) {\r\n                    if (flag_move) {\r\n                        uint8_t gFontSmall_More[12] = {0};\r\n                        for (int j = 0; j < 12; ++j) {\r\n                            if (j < 6) gFontSmall_More[j] = (gFontSmall[index][j] & 0x1F) << 3;//00011111\r\n                            else gFontSmall_More[j] = (gFontSmall[index][j - 6] & 0XE0)\r\n                                        >> 5;//|(0xFB& *(pFb1+ now_pixel + 1+j-6));//11100000\r\n                        }\r\n                        memcpy(pFb + now_pixel + 1, &gFontSmall_More[0], 6);\r\n                        memcpy(pFb1 + now_pixel + 1, &gFontSmall_More[6], 6);\r\n                    } else\r\n                        memcpy(pFb + now_pixel + 1, &gFontSmall[index], 6);\r\n                }\r\n#else\r\n                if (index < 94) {\r\n                    uint8_t read_gFontSmall[6];\r\n                    EEPROM_ReadBuffer(0x0267C + index * 6, read_gFontSmall, 6);\r\n                    if (flag_move) {\r\n                        uint8_t gFontSmall_More[12] = {0};\r\n\r\n                        for (int j = 0; j < 12; ++j) {\r\n                            if (j < 6) gFontSmall_More[j] = (read_gFontSmall[j] & 0x1F) << 3;//00011111\r\n                            else gFontSmall_More[j] = (read_gFontSmall[j - 6] & 0XE0)\r\n                                        >> 5;//|(0xFB& *(pFb1+ now_pixel + 1+j-6));//11100000\r\n                        }\r\n                        memcpy(pFb + now_pixel + 1, &gFontSmall_More[0], 6);\r\n                        memcpy(pFb1 + now_pixel + 1, &gFontSmall_More[6], 6);\r\n                    } else\r\n                        memcpy(pFb + now_pixel + 1, &read_gFontSmall, 6);\r\n                }\r\n\r\n#endif\r\n                now_pixel += 7;\r\n            } else if (true_char[i] == ' ')\r\n                now_pixel += 7;\r\n        } else {\r\n//            uint8_t gFontChinese[22] = {0};\r\n\r\n#if ENABLE_CHINESE_FULL != 0\r\n            true_char[i] =\r\n                    true_char[i] < 0XD8A1 ? ((true_char[i] - 0xB0A0) >> 8) * 94 + ((true_char[i] - 0xB0A0) & 0xff) - 1 :\r\n                    ((true_char[i] - 0xB0A0) >> 8) * 94 + ((true_char[i] - 0xB0A0) & 0xFF) - 6;\r\n            uint8_t tmp[17] = {0};\r\n            unsigned int local = (CHN_FONT_HIGH * CHN_FONT_WIDTH * true_char[i]) >> 3;\r\n            unsigned int local_bit = (CHN_FONT_HIGH * CHN_FONT_WIDTH * true_char[i]) & 7;\r\n            EEPROM_ReadBuffer(local + 0x02E00, tmp, 17);\r\n            local = 0;\r\n            for (unsigned char k = 0; k < CHN_FONT_WIDTH * 2; ++k) {\r\n                unsigned char j_end = 8;\r\n                if (k >= CHN_FONT_WIDTH)\r\n                    j_end = CHN_FONT_HIGH - 8;\r\n                for (unsigned char j = 0; j < j_end; ++j) {\r\n                    if (IS_BIT_SET(tmp[local], local_bit))\r\n//                        set_bit(&gFontChinese[k], j, 1);\r\n                        if (k < CHN_FONT_WIDTH) set_bit(pFb + now_pixel + 1 + k, j);\r\n\r\n                        else set_bit(pFb1 + now_pixel + 1 + k - CHN_FONT_WIDTH, j);\r\n\r\n                    local_bit++;\r\n                    if (local_bit == 8) {\r\n                        local_bit = 0;\r\n                        local++;\r\n                    }\r\n                }\r\n            }\r\n\r\n#else\r\n            unsigned int local = (CHN_FONT_HIGH * CHN_FONT_WIDTH * true_char[i]) / 8;\r\n            unsigned int local_bit = (CHN_FONT_HIGH * CHN_FONT_WIDTH * true_char[i]) % 8;\r\n            for (unsigned char k = 0; k < CHN_FONT_WIDTH * 2; ++k) {\r\n                unsigned char j_end = 8;\r\n                if (k >= CHN_FONT_WIDTH)\r\n                    j_end = CHN_FONT_HIGH - 8;\r\n                for (unsigned char j = 0; j < j_end; ++j) {\r\n                    if (IS_BIT_SET(gFontChinese_out[local], local_bit))\r\n//                        set_bit(&gFontChinese[k], j, 1);\r\n\r\n                    //                        set_bit(&gFontChinese[k], j, 1);\r\n\r\n                        if(k<CHN_FONT_WIDTH)                         set_bit(pFb + now_pixel + 1+k, j);\r\n                        else set_bit(pFb1 + now_pixel + 1+k-CHN_FONT_WIDTH, j);\r\n\r\n                    local_bit++;\r\n                    if (local_bit == 8) {\r\n                        local_bit = 0;\r\n                        local++;\r\n                    }\r\n                }\r\n            }\r\n//            memcpy(pFb + now_pixel + 1, &gFontChinese[0], 11);\r\n//            memcpy(pFb1 + now_pixel + 1, &gFontChinese[11], 11);\r\n#endif\r\n\r\n            now_pixel += 13;\r\n        }\r\n    }\r\n#endif\r\n}\r\n\r\n\r\nvoid UI_PrintStringSmallBuffer(const char *pString, uint8_t *buffer) {\r\n    size_t i;\r\n    const unsigned int char_width = ARRAY_SIZE(gFontSmall[0]);\r\n    for (i = 0; i < strlen(pString); i++) {\r\n        if (pString[i] > ' ') {\r\n            const unsigned int index = (unsigned int) pString[i] - ' ' - 1;\r\n#if ENABLE_CHINESE_FULL == 4\r\n            if (index < 94) {\r\n                uint8_t read_gFontSmall[6];\r\n                EEPROM_ReadBuffer(0x267C + index * 6, read_gFontSmall, 6);\r\n                memcpy(buffer + (i * (char_width + 1)) + 1, &read_gFontSmall, char_width);\r\n            }\r\n#else\r\n            if (index < ARRAY_SIZE(gFontSmall))\r\n                memcpy(buffer + (i * (char_width + 1)) + 1, &gFontSmall[index], char_width);\r\n#endif\r\n\r\n        }\r\n    }\r\n}\r\n\r\nvoid UI_DisplayFrequency(const char *string, uint8_t X, uint8_t Y, bool center) {\r\n    const unsigned int char_width = 13;\r\n    uint8_t *pFb0 = gFrameBuffer[Y] + X;\r\n    uint8_t *pFb1 = pFb0 + 128;\r\n    bool bCanDisplay = false;\r\n\r\n    uint8_t len = strlen(string);\r\n    for (int i = 0; i < len; i++) {\r\n        char c = string[i];\r\n        if (c == '-') c = '9' + 1;\r\n        if (bCanDisplay || c != ' ') {\r\n            bCanDisplay = true;\r\n            if (c >= '0' && c <= '9' + 1) {\r\n#if ENABLE_CHINESE_FULL == 4\r\n                uint8_t read_gFontBigDigits[20];\r\n                EEPROM_ReadBuffer(0x02480 + 20 * (c - '0'), read_gFontBigDigits, 20);\r\n\r\n                memcpy(pFb0 + 2, read_gFontBigDigits, char_width - 3);\r\n                memcpy(pFb1 + 2, read_gFontBigDigits + char_width - 3, char_width - 3);\r\n#else\r\n                memcpy(pFb0 + 2, gFontBigDigits[c - '0'], char_width - 3);\r\n                memcpy(pFb1 + 2, gFontBigDigits[c - '0'] + char_width - 3, char_width - 3);\r\n#endif\r\n            } else if (c == '.') {\r\n                *pFb1 = 0x60;\r\n                pFb0++;\r\n                pFb1++;\r\n                *pFb1 = 0x60;\r\n                pFb0++;\r\n                pFb1++;\r\n                *pFb1 = 0x60;\r\n                pFb0++;\r\n                pFb1++;\r\n                continue;\r\n            }\r\n\r\n        } else if (center) {\r\n            pFb0 -= 6;\r\n            pFb1 -= 6;\r\n        }\r\n        pFb0 += char_width;\r\n        pFb1 += char_width;\r\n    }\r\n}\r\n\r\n\r\nvoid UI_DrawPixelBuffer(uint8_t (*buffer)[128], uint8_t x, uint8_t y, bool black) {\r\n    const uint8_t pattern = 1 << (y % 8);\r\n    if (black)\r\n        buffer[y / 8][x] |= pattern;\r\n    else\r\n        buffer[y / 8][x] &= ~pattern;\r\n}\r\n\r\n\r\nvoid UI_DisplayPopup(const char *string) {\r\n    for (uint8_t i = 0; i < 7; i++) {\r\n        memset(gFrameBuffer[i], 0x00, 128);\r\n    }\r\n\r\n    // for(uint8_t i = 1; i < 5; i++) {\r\n    // \tmemset(gFrameBuffer[i]+8, 0x00, 111);\r\n    // }\r\n\r\n    // for(uint8_t x = 10; x < 118; x++) {\r\n    // \tUI_DrawPixel(x, 10, true);\r\n    // \tUI_DrawPixel(x, 46-9, true);\r\n    // }\r\n\r\n    // for(uint8_t y = 11; y < 37; y++) {\r\n    // \tUI_DrawPixel(10, y, true);\r\n    // \tUI_DrawPixel(117, y, true);\r\n    // }\r\n    // DrawRectangle(9,9, 118,38, true);\r\n\r\n    UI_PrintStringSmall(string, 9, 118, 2);\r\n    //按EXIT键\r\n    UI_PrintStringSmall(按EXIT键, 9, 118, 5);\r\n}\r\n\r\nvoid UI_DisplayClear() {\r\n    memset(gFrameBuffer, 0, sizeof(gFrameBuffer));\r\n\r\n}\r\n// GUI functions\r\n\r\nvoid PutPixel(uint8_t x, uint8_t y, bool fill) {\r\n    UI_DrawPixelBuffer(gFrameBuffer, x, y, fill);\r\n}\r\n\r\nvoid PutPixelStatus(uint8_t x, uint8_t y, bool fill) {\r\n    UI_DrawPixelBuffer(&gStatusLine, x, y, fill);\r\n}\r\n\r\n\r\nvoid DrawVLine(int sy, int ey, int nx, bool fill) {\r\n    for (int i = sy; i <= ey; i++) {\r\n        if (i < 56 && nx < 128) {\r\n            PutPixel(nx, i, fill);\r\n        }\r\n    }\r\n}\r\n\r\nvoid GUI_DisplaySmallest(const char *pString, uint8_t x, uint8_t y,\r\n                         bool statusbar, bool fill) {\r\n    uint8_t c;\r\n    uint8_t pixels;\r\n    const uint8_t *p = (const uint8_t *) pString;\r\n\r\n    while ((c = *p++) && c != '\\0') {\r\n        c -= 0x20;\r\n#if ENABLE_CHINESE_FULL != 0\r\n        uint8_t read_gFont3x5[3];\r\n        EEPROM_ReadBuffer(0x0255C + c * 3, read_gFont3x5, 3);\r\n        for (int i = 0; i < 3; ++i) {\r\n            pixels = read_gFont3x5[i];\r\n#else\r\n            for (int i = 0; i < 3; ++i) {\r\n                pixels = gFont3x5[c][i];\r\n#endif\r\n            for (int j = 0; j < 6; ++j) {\r\n                if (pixels & 1) {\r\n                    if (statusbar)\r\n                        PutPixelStatus(x + i, y + j, fill);\r\n                    else\r\n                        PutPixel(x + i, y + j, fill);\r\n                }\r\n                pixels >>= 1;\r\n            }\r\n        }\r\n        x += 4;\r\n    }\r\n}\r\n\r\nvoid show_uint32(uint32_t num, uint8_t line) {\r\n    memset(gFrameBuffer[line],0,128);\r\n    char str[20] = {0};\r\n    sprintf(str, \"%d\", num);\r\n    UI_PrintStringSmall(str, 0, 127, line);\r\n    ST7565_BlitFullScreen();\r\n}\r\n\r\nvoid show_hex(uint32_t num, uint8_t line) {\r\n    memset(gFrameBuffer[line],0,128);\r\n    char str[20] = {0};\r\n    sprintf(str, \"%X\", num);\r\n    UI_PrintStringSmall(str, 0, 127, line);\r\n    ST7565_BlitFullScreen();\r\n}\r\n"
  },
  {
    "path": "ui/helper.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_UI_H\r\n#define UI_UI_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n//#define ENABLE_PINYIN\r\n//#define test 0\r\nvoid UI_GenerateChannelString(char *pString, const uint8_t Channel);\r\n\r\nvoid UI_GenerateChannelStringEx(char *pString, const bool bShowPrefix, const uint8_t ChannelNumber);\r\n\r\nvoid UI_PrintStringSmall(const char *pString, uint8_t Start, uint8_t End, uint8_t Line);\r\n\r\nvoid UI_PrintCharSmall(char character, uint8_t Start, uint8_t Line);\r\n\r\nuint8_t is_chn(uint8_t num);\r\n\r\nbool CHINESE_JUDGE(char *name, uint8_t len);\r\n\r\nvoid UI_DisplayClear();\r\n\r\n\r\nvoid UI_PrintStringSmallBuffer(const char *pString, uint8_t *buffer);\r\n\r\nvoid UI_DisplayFrequency(const char *string, uint8_t X, uint8_t Y, bool center);\r\n\r\nvoid UI_DrawPixelBuffer(uint8_t (*buffer)[128], uint8_t x, uint8_t y, bool black);\r\n\r\nvoid UI_DisplayPopup(const char *string);\r\n\r\n#endif\r\nbool isChineseChar(char a ,uint8_t now_index,uint8_t sum_index) ;\r\n\r\nvoid GUI_DisplaySmallest(const char *pString, uint8_t x, uint8_t y, bool statusbar, bool fill);\r\n\r\nvoid PutPixelStatus(uint8_t x, uint8_t y, bool fill);\r\n\r\nvoid PutPixel(uint8_t x, uint8_t y, bool fill);\r\n\r\nvoid DrawVLine(int sy, int ey, int nx, bool fill);\r\nvoid show_uint32(uint32_t num,uint8_t  line);\r\nvoid show_hex(uint32_t num, uint8_t line) ;\r\n\r\n//void UI_DrawPixel(uint8_t x, uint8_t y, bool black);\r\n//void UI_DrawLine(int16_t x1, int16_t y1, int16_t x2, int16_t y2, bool black);\r\n//\r\n"
  },
  {
    "path": "ui/inputbox.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <string.h>\r\n\r\n#include \"ui/inputbox.h\"\r\n\r\nchar gInputBox[8];\r\nchar inputBoxAscii[9];\r\nuint8_t gInputBoxIndex;\r\n\r\nvoid INPUTBOX_Append(const KEY_Code_t Digit) {\r\n    if (gInputBoxIndex >= sizeof(gInputBox))\r\n        return;\r\n\r\n    if (gInputBoxIndex == 0)\r\n        memset(gInputBox, 10, sizeof(gInputBox));\r\n\r\n    if (Digit != KEY_INVALID)\r\n        gInputBox[gInputBoxIndex++] = (char) (Digit - KEY_0);\r\n}\r\n\r\nconst char *INPUTBOX_GetAscii() {\r\n    for (int i = 0; i < 8; i++) {\r\n        char c = gInputBox[i];\r\n        inputBoxAscii[i] = (c == 10) ? '-' : '0' + c;\r\n    }\r\n    return inputBoxAscii;\r\n}"
  },
  {
    "path": "ui/inputbox.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_INPUTBOX_H\r\n#define UI_INPUTBOX_H\r\n\r\n#include <stdint.h>\r\n\r\n#include \"driver/keyboard.h\"\r\n\r\nextern char    gInputBox[8];\r\nextern uint8_t gInputBoxIndex;\r\n\r\nvoid INPUTBOX_Append(const KEY_Code_t Digit);\r\nconst char* INPUTBOX_GetAscii();\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "ui/lock.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifdef ENABLE_PWRON_PASSWORD\r\n\r\n#include <string.h>\r\n\r\n#include \"ARMCM0.h\"\r\n#include \"app/uart.h\"\r\n#include \"audio.h\"\r\n#include \"driver/keyboard.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/lock.h\"\r\n\r\nstatic void Render(void)\r\n{\r\n    unsigned int i;\r\n    char         String[7];\r\n\r\n    memset(gStatusLine,  0, sizeof(gStatusLine));\r\n    UI_DisplayClear();\r\n    UI_PrintStringSmall(\"LOCK\", 0, 127, 1);\r\n    for (i = 0; i < 6; i++)\r\n        String[i] = (gInputBox[i] == 10) ? '-' : '*';\r\n    String[6] = 0;\r\n    UI_PrintStringSmall(String, 0, 127, 3);\r\n\r\n    ST7565_BlitStatusLine();\r\n    ST7565_BlitFullScreen();\r\n}\r\n\r\nvoid UI_DisplayLock(void)\r\n{\r\n    KEY_Code_t  Key;\r\n    BEEP_Type_t Beep;\r\n\r\n    gUpdateDisplay = true;\r\n\r\n    memset(gInputBox, 10, sizeof(gInputBox));\r\n\r\n    while (1)\r\n    {\r\n        while (!gNextTimeslice) {}\r\n\r\n        // TODO: Original code doesn't do the below, but is needed for proper key debounce\r\n\r\n        gNextTimeslice = false;\r\n\r\n        Key = KEYBOARD_Poll();\r\n\r\n        if (gKeyReading0 == Key)\r\n        {\r\n            if (++gDebounceCounter == key_debounce_10ms)\r\n            {\r\n                if (Key == KEY_INVALID)\r\n                {\r\n                    gKeyReading1 = KEY_INVALID;\r\n                }\r\n                else\r\n                {\r\n                    gKeyReading1 = Key;\r\n\r\n                    switch (Key)\r\n                    {\r\n                        case KEY_0:\r\n                        case KEY_1:\r\n                        case KEY_2:\r\n                        case KEY_3:\r\n                        case KEY_4:\r\n                        case KEY_5:\r\n                        case KEY_6:\r\n                        case KEY_7:\r\n                        case KEY_8:\r\n                        case KEY_9:\r\n                            INPUTBOX_Append(Key - KEY_0);\r\n\r\n                            if (gInputBoxIndex < 6)   // 6 frequency digits\r\n                            {\r\n                                Beep = BEEP_1KHZ_60MS_OPTIONAL;\r\n                            }\r\n                            else\r\n                            {\r\n                                uint32_t Password;\r\n\r\n                                gInputBoxIndex = 0;\r\n                                Password = StrToUL(INPUTBOX_GetAscii());\r\n\r\n                                if ((gEeprom.POWER_ON_PASSWORD) == Password)\r\n                                {\r\n#ifdef    ENABLE_WARNING\r\n\r\n                                    AUDIO_PlayBeep(BEEP_1KHZ_60MS_OPTIONAL);\r\n#endif\r\n                                    return;\r\n                                }\r\n\r\n                                memset(gInputBox, 10, sizeof(gInputBox));\r\n\r\n                                Beep = BEEP_500HZ_60MS_DOUBLE_BEEP_OPTIONAL;\r\n                            }\r\n#ifdef    ENABLE_WARNING\r\n\r\n                            AUDIO_PlayBeep(Beep);\r\n#endif\r\n                            gUpdateDisplay = true;\r\n                            break;\r\n\r\n                        case KEY_EXIT:\r\n                            if (gInputBoxIndex > 0)\r\n                            {\r\n                                gInputBox[--gInputBoxIndex] = 10;\r\n                                gUpdateDisplay = true;\r\n                            }\r\n#ifdef    ENABLE_WARNING\r\n\r\n                            AUDIO_PlayBeep(BEEP_1KHZ_60MS_OPTIONAL);\r\n\r\n#endif\r\n                        default:\r\n                            break;\r\n                    }\r\n                }\r\n\r\n                gKeyBeingHeld = false;\r\n            }\r\n        }\r\n        else\r\n        {\r\n            gDebounceCounter = 0;\r\n            gKeyReading0     = Key;\r\n        }\r\n#ifdef ENABLE_UART\r\n        if (UART_IsCommandAvailable())\r\n        {\r\n            __disable_irq();\r\n            UART_HandleCommand();\r\n            __enable_irq();\r\n        }\r\n#endif\r\n        if (gUpdateDisplay)\r\n        {\r\n            Render();\r\n            gUpdateDisplay = false;\r\n        }\r\n    }\r\n}\r\n\r\n#endif\r\n"
  },
  {
    "path": "ui/lock.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_LOCK_H\r\n#define UI_LOCK_H\r\n\r\n#ifdef ENABLE_PWRON_PASSWORD\r\n\tvoid UI_DisplayLock(void);\r\n#endif\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "ui/main.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include \"app/mdc1200.h\"\r\n#include \"chinese.h\"\r\n#include <string.h>\r\n#include <stdlib.h>  // abs()\r\n#include \"driver/uart.h\"\r\n#include \"app/dtmf.h\"\r\n#include \"font.h\"\r\n#include \"app/chFrScanner.h\"\r\n\r\n#ifdef ENABLE_AM_FIX\r\n#include \"am_fix.h\"\r\n#endif\r\n\r\n#include \"bitmaps.h\"\r\n#include \"board.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"functions.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"radio.h\"\r\n#include \"settings.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/main.h\"\r\n#include \"ui/ui.h\"\r\n\r\ncenter_line_t center_line = CENTER_LINE_NONE;\r\nconst int8_t dBmCorrTable[7] = {\r\n        -15, // band 1\r\n        -25, // band 2\r\n        -20, // band 3\r\n        -4, // band 4\r\n        -7, // band 5\r\n        -6, // band 6\r\n        -1  // band 7\r\n};\r\n\r\nconst char *VfoStateStr[] = {\r\n        [VFO_STATE_NORMAL]=\"\",\r\n        [VFO_STATE_BUSY]=遇忙,\r\n        [VFO_STATE_BAT_LOW]=低电压,\r\n        [VFO_STATE_TX_DISABLE]=禁止发射,\r\n        [VFO_STATE_TIMEOUT]=发送超时,\r\n        [VFO_STATE_ALARM]=\"ALARM\",\r\n        [VFO_STATE_VOLTAGE_HIGH]=高电压\r\n};\r\n// ***************************************************************************\r\n\r\nstatic void DrawSmallAntennaAndBars(uint8_t *p, unsigned int level) {\r\n    if (level > 6)\r\n        level = 6;\r\n\r\n    memcpy(p, BITMAP_Antenna, ARRAY_SIZE(BITMAP_Antenna));\r\n\r\n    for (uint8_t i = 1; i <= level; i++) {\r\n        char bar = (0xff << (6 - i)) & 0x7F;\r\n        memset(p + 2 + i * 3, bar, 2);\r\n    }\r\n}\r\n\r\n//#if defined ENABLE_AUDIO_BAR || defined ENABLE_RSSI_BAR\r\n\r\nstatic void DrawLevelBar(uint8_t xpos, uint8_t line, uint8_t level) {\r\n    const char hollowBar[] = {\r\n            0b01111111,\r\n            0b01000001,\r\n            0b01000001,\r\n            0b01111111\r\n    };\r\n\r\n    uint8_t *p_line = gFrameBuffer[line];\r\n    level = MIN(level, 13);\r\n#ifndef ENABLE_AUDIO_BAR_DEFAULT\r\n    if (xpos == 35) {\r\n\r\n        p_line[xpos] = 0x3E;\r\n\r\n        for (uint8_t i = 0; i < 91; i++) {\r\n            if (i < level * 7) {\r\n                p_line[xpos + i + 1] = 0x3E;\r\n            } else {\r\n                p_line[xpos + i + 1] = 0X22;\r\n            }\r\n        }\r\n        p_line[xpos + 91 + 1] = 0x3E;\r\n    } else {\r\n#endif\r\n        for (uint8_t i = 0; i < level; i++) {\r\n            if (i < 9) {\r\n                for (uint8_t j = 0; j < 4; j++)\r\n                    p_line[xpos + i * 5 + j] = (~(0x7F >> (i + 1))) & 0x7F;\r\n            } else {\r\n                memcpy(p_line + (xpos + i * 5), &hollowBar, ARRAY_SIZE(hollowBar));\r\n            }\r\n        }\r\n#ifndef ENABLE_AUDIO_BAR_DEFAULT\r\n\r\n    }\r\n#endif\r\n\r\n}\r\n//#endif\r\n\r\n//#ifdef ENABLE_AUDIO_BAR\r\n\r\nunsigned int sqrt16(unsigned int value) {    // return square root of 'value'\r\n    unsigned int shift = 16;         // number of bits supplied in 'value' .. 2 ~ 32\r\n    unsigned int bit = 1u << --shift;\r\n    unsigned int sqrti = 0;\r\n    while (bit) {\r\n        const unsigned int temp = ((sqrti << 1) | bit) << shift--;\r\n        if (value >= temp) {\r\n            value -= temp;\r\n            sqrti |= bit;\r\n        }\r\n        bit >>= 1;\r\n    }\r\n    return sqrti;\r\n}\r\n\r\nvoid UI_DisplayAudioBar(void) {\r\n\r\n    if (gLowBattery && !gLowBatteryConfirmed)\r\n        return;\r\n\r\n    const unsigned int line = 3;\r\n\r\n    if (gCurrentFunction != FUNCTION_TRANSMIT ||\r\n        gScreenToDisplay != DISPLAY_MAIN\r\n#ifdef ENABLE_DTMF_CALLING\r\n        || gDTMF_CallState != DTMF_CALL_STATE_NONE\r\n        || gDTMF_IsTx\r\n#endif\r\n            ) {\r\n        return;  // screen is in use\r\n    }\r\n\r\n#if defined(ENABLE_ALARM) || defined(ENABLE_TX1750)\r\n    if (gAlarmState != ALARM_STATE_OFF)\r\n        return;\r\n#endif\r\n    const unsigned int voice_amp = BK4819_GetVoiceAmplitudeOut();  // 15:0\r\n\r\n    // make non-linear to make more sensitive at low values\r\n    const unsigned int level = MIN(voice_amp * 8, 65535u);\r\n    const unsigned int sqrt_level = MIN(sqrt16(level), 124u);\r\n    uint8_t bars = 13 * sqrt_level / 124;\r\n\r\n    uint8_t *p_line = gFrameBuffer[line];\r\n#if ENABLE_CHINESE_FULL == 4 &&!defined(ENABLE_ENGLISH)\r\n    if (audio_keep_flag) {\r\n        //audio_keep_flag=false;\r\n\r\n#ifndef ENABLE_AUDIO_BAR_DEFAULT\r\n        memset(p_line + 35, 0, LCD_WIDTH - 35);\r\n#else\r\n       memset(p_line+62, 0, LCD_WIDTH-62);\r\n#endif\r\n    } else\r\n#endif\r\n    memset(p_line, 0, LCD_WIDTH);\r\n\r\n#ifndef ENABLE_AUDIO_BAR_DEFAULT\r\n\r\n    DrawLevelBar(35, line, bars);\r\n#else\r\n    DrawLevelBar(62, line, bars);\r\n\r\n#endif\r\n    if (gCurrentFunction == FUNCTION_TRANSMIT)\r\n        ST7565_BlitFullScreen();\r\n\r\n}\r\n//#endif\r\n\r\n\r\nvoid DisplayRSSIBar(const bool now) {\r\n#if defined(ENABLE_RSSI_BAR)\r\n\r\n    const unsigned int txt_width    = 7 * 8;                 // 8 text chars\r\n    const unsigned int bar_x        = 2 + txt_width + 4;     // X coord of bar graph\r\n\r\n    const unsigned int line         = 3;\r\n    uint8_t           *p_line        = gFrameBuffer[line];\r\n    char               str[16];\r\n\r\n    const char plus[] = {\r\n        0b00011000,\r\n        0b00011000,\r\n        0b01111110,\r\n        0b01111110,\r\n        0b01111110,\r\n        0b00011000,\r\n        0b00011000,\r\n    };\r\n\r\n        if ((gEeprom.KEY_LOCK && gKeypadLocked > 0) || center_line != CENTER_LINE_RSSI)\r\n        return;     // display is in use\r\n\r\n    if (gCurrentFunction == FUNCTION_TRANSMIT ||\r\n        gScreenToDisplay != DISPLAY_MAIN\r\n#ifdef ENABLE_DTMF_CALLING\r\n        || gDTMF_CallState != DTMF_CALL_STATE_NONE\r\n#endif\r\n    ) {\r\n        return; // display is in use\r\n    }\r\n    if (now) {\r\n        memset(p_line, 0, LCD_WIDTH);\r\n    }\r\n\r\n\r\n    const int16_t s0_dBm = -gEeprom.S0_LEVEL; // S0 .. base level\r\n    const int16_t rssi_dBm =\r\n        BK4819_GetRSSI_dBm()\r\n#ifdef ENABLE_AM_FIX\r\n        + ((gSetting_AM_fix && gRxVfo->Modulation == MODULATION_AM) ? AM_fix_get_gain_diff() : 0)\r\n#endif\r\n        + dBmCorrTable[gRxVfo->Band];\r\n\r\n    int s0_9 = gEeprom.S0_LEVEL - gEeprom.S9_LEVEL;\r\n    const uint8_t s_level = MIN(MAX((int32_t)(rssi_dBm - s0_dBm)*100 / (s0_9*100/9), 0), 9); // S0 - S9\r\n    uint8_t overS9dBm = MIN(MAX(rssi_dBm + gEeprom.S9_LEVEL, 0), 99);\r\n    uint8_t overS9Bars = MIN(overS9dBm/10, 4);\r\n\r\n    if (overS9Bars == 0) {\r\n        sprintf(str, \"% 4d S%d\", rssi_dBm, s_level);\r\n    } else {\r\n        sprintf(str, \"% 4d  %2d\", rssi_dBm, overS9dBm);\r\n        memcpy(p_line + 2 + 7 * 5, &plus, ARRAY_SIZE(plus));\r\n    }\r\n    UI_PrintStringSmall(str, 2, 0, line);\r\n    DrawLevelBar(bar_x, line, s_level + overS9Bars);\r\n    if (now)\r\n        ST7565_BlitLine(line);\r\n#else\r\n    int16_t rssi = BK4819_GetRSSI();\r\n\r\n    uint8_t Level;\r\n\r\n    if (rssi >= gEEPROM_RSSI_CALIB[gRxVfo->Band][3]) {\r\n        Level = 6;\r\n    } else if (rssi >= gEEPROM_RSSI_CALIB[gRxVfo->Band][2]) {\r\n        Level = 4;\r\n    } else if (rssi >= gEEPROM_RSSI_CALIB[gRxVfo->Band][1]) {\r\n        Level = 2;\r\n    } else if (rssi >= gEEPROM_RSSI_CALIB[gRxVfo->Band][0]) {\r\n        Level = 1;\r\n    } else {\r\n        Level = 0;\r\n    }\r\n\r\n    uint8_t *pLine = (gEeprom.RX_VFO == 0) ? gFrameBuffer[2] : gFrameBuffer[6];\r\n    if (now)\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n        memset(pLine, 0, 23);\r\n\r\n    DrawSmallAntennaAndBars(pLine, Level);\r\n#else\r\n    if(IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num]) )\r\n        {\r\n                memset(gFrameBuffer[3], 0, 23);\r\n\r\n    DrawSmallAntennaAndBars(gFrameBuffer[3], Level);\r\n                         audio_keep_flag=true;\r\n    }\r\nelse{\r\n    audio_keep_flag=false;\r\n            memset(pLine, 0, 23);\r\n    DrawSmallAntennaAndBars(pLine, Level);\r\n}\r\n#endif\r\n    if (now)\r\n        ST7565_BlitFullScreen();\r\n#endif\r\n}\r\n\r\n\r\n#ifdef ENABLE_AGC_SHOW_DATA\r\nvoid UI_MAIN_PrintAGC(bool now){\r\n    char buf[20];\r\n    memset(gFrameBuffer[3], 0, 128);\r\n    union {\r\n        struct {\r\n            uint16_t _ : 5;\r\n            uint16_t agcSigStrength : 7;\r\n            int16_t gainIdx : 3;\r\n            uint16_t agcEnab : 1;\r\n        };\r\n        uint16_t __raw;\r\n    } reg7e;\r\n    reg7e.__raw = BK4819_ReadRegister(0x7E);\r\n    uint8_t gainAddr = reg7e.gainIdx < 0 ? 0x14 : 0x10 + reg7e.gainIdx;\r\n    union {\r\n        struct {\r\n            uint16_t pga:3;\r\n            uint16_t mixer:2;\r\n            uint16_t lna:3;\r\n            uint16_t lnaS:2;\r\n        };\r\n        uint16_t __raw;\r\n    } agcGainReg;\r\n    agcGainReg.__raw = BK4819_ReadRegister(gainAddr);\r\n    int8_t lnaShortTab[] = {-28, -24, -19, 0};\r\n    int8_t lnaTab[] = {-24, -19, -14, -9, -6, -4, -2, 0};\r\n    int8_t mixerTab[] = {-8, -6, -3, 0};\r\n    int8_t pgaTab[] = {-33, -27, -21, -15, -9, -6, -3, 0};\r\n    int16_t agcGain = lnaShortTab[agcGainReg.lnaS] + lnaTab[agcGainReg.lna] + mixerTab[agcGainReg.mixer] + pgaTab[agcGainReg.pga];\r\n\r\n    sprintf(buf, \"%d%2d %2d %2d %3d\", reg7e.agcEnab, reg7e.gainIdx, -agcGain, reg7e.agcSigStrength, BK4819_GetRSSI());\r\n    UI_PrintStringSmall(buf, 2, 0, 3);\r\n    if(now)\r\n        ST7565_BlitLine(3);\r\n}\r\n#endif\r\n\r\nvoid UI_MAIN_TimeSlice500ms(void) {\r\n    if (gScreenToDisplay == DISPLAY_MAIN) {\r\n#ifdef ENABLE_AGC_SHOW_DATA\r\n        UI_MAIN_PrintAGC(true);\r\n        return;\r\n#endif\r\n        if (FUNCTION_IsRx()) {\r\n            DisplayRSSIBar(true);\r\n        }\r\n    }\r\n}\r\n// ***************************************************************************\r\n\r\nvoid UI_DisplayMain(void) {\r\n\r\n    char String[22];\r\n\r\n    center_line = CENTER_LINE_NONE;\r\n\r\n    // clear the screen\r\n    UI_DisplayClear();\r\n\r\n    if (gLowBattery && !gLowBatteryConfirmed) {\r\n        //低电压\r\n        UI_DisplayPopup(低电压);\r\n        ST7565_BlitFullScreen();\r\n        return;\r\n    }\r\n\r\n    if (gEeprom.KEY_LOCK && gKeypadLocked > 0) {    // tell user how to unlock the keyboard\r\n        //translate\r\n\r\n\r\n\r\n#ifdef test\r\n        UI_PrintStringSmall(\"press # long\", 0, LCD_WIDTH, 1);\r\n\r\n\r\n        UI_PrintStringSmall(\"to unlock\",    0, LCD_WIDTH, 3);\r\n#else\r\n#ifdef ENABLE_ENGLISH\r\n        UI_PrintStringSmall(\"press # long\", 0, LCD_WIDTH, 1);\r\n\r\n\r\n        UI_PrintStringSmall(\"to unlock\",    0, LCD_WIDTH, 3);\r\n#else\r\n//长按 # 键解锁\r\n\r\n        UI_PrintStringSmall(长按井键解锁, 0, LCD_WIDTH, 1);\r\n#endif\r\n\r\n#endif\r\n\r\n\r\n        ST7565_BlitFullScreen();\r\n        return;\r\n    }\r\n\r\n    unsigned int activeTxVFO = gRxVfoIsActive ? gEeprom.RX_VFO : gEeprom.TX_VFO;\r\n    for (unsigned int vfo_num = 0; vfo_num < 2; vfo_num++) {\r\n        const unsigned int line0 = 0;  // text screen line\r\n        const unsigned int line1 = 4;\r\n\r\n        const unsigned int line = (vfo_num == 0) ? line0 : line1;\r\n        const bool isMainVFO = (vfo_num == gEeprom.TX_VFO);\r\n        uint8_t *p_line0 = gFrameBuffer[line + 0];\r\n        uint8_t *p_line1 = gFrameBuffer[line + 1];\r\n\r\n        enum Vfo_txtr_mode mode = VFO_MODE_NONE;\r\n        if (activeTxVFO != vfo_num) // this is not active TX VFO\r\n        {\r\n#ifdef ENABLE_SCAN_RANGES\r\n            if (gScanRangeStart) {\r\n                UI_PrintStringSmall(\"ScnRng\", 5, 0, line);\r\n                sprintf(String, \"%3u.%05u\", gScanRangeStart / 100000, gScanRangeStart % 100000);\r\n                UI_PrintStringSmall(String, 56, 0, line);\r\n                sprintf(String, \"%3u.%05u\", gScanRangeStop / 100000, gScanRangeStop % 100000);\r\n                UI_PrintStringSmall(String, 56, 0, line + 1);\r\n                continue;\r\n            }\r\n#endif\r\n\r\n\r\n            if (gDTMF_InputMode\r\n#ifdef ENABLE_DTMF_CALLING\r\n                || gDTMF_CallState != DTMF_CALL_STATE_NONE || gDTMF_IsTx\r\n#endif\r\n                    ) {\r\n                char *pPrintStr = \"\";\r\n\r\n                // show DTMF stuff\r\n#ifdef ENABLE_DTMF_CALLING\r\n                char Contact[16];\r\n                if (!gDTMF_InputMode) {\r\n                    if (gDTMF_CallState == DTMF_CALL_STATE_CALL_OUT) {\r\n                        pPrintStr = DTMF_FindContact(gDTMF_String, Contact) ? Contact : gDTMF_String;\r\n                    } else if (gDTMF_CallState == DTMF_CALL_STATE_RECEIVED || gDTMF_CallState == DTMF_CALL_STATE_RECEIVED_STAY){\r\n                        pPrintStr = DTMF_FindContact(gDTMF_Callee, Contact) ? Contact : gDTMF_Callee;\r\n                    }else if (gDTMF_IsTx) {\r\n                        pPrintStr = gDTMF_String;\r\n                    }\r\n                }\r\n\r\n                UI_PrintStringSmall(pPrintStr, 2, 0, 2 + (vfo_num * 3));\r\n\r\n                pPrintStr = \"\";\r\n                if (!gDTMF_InputMode) {\r\n                    if (gDTMF_CallState == DTMF_CALL_STATE_CALL_OUT) {\r\n                        pPrintStr = (gDTMF_State == DTMF_STATE_CALL_OUT_RSP) ? \"CALL OUT(RSP)\" : \"CALL OUT\";\r\n                    } else if (gDTMF_CallState == DTMF_CALL_STATE_RECEIVED || gDTMF_CallState == DTMF_CALL_STATE_RECEIVED_STAY) {\r\n                        sprintf(String, \"CALL FRM:%s\", (DTMF_FindContact(gDTMF_Caller, Contact)) ? Contact : gDTMF_Caller);\r\n                        pPrintStr = String;\r\n                    } else if (gDTMF_IsTx) {\r\n                        pPrintStr = (gDTMF_State == DTMF_STATE_TX_SUCC) ? \"DTMF TX(SUCC)\" : \"DTMF TX\";\r\n                    }\r\n                }\r\n                else\r\n#endif\r\n                {\r\n                    sprintf(String, \">%s\", gDTMF_InputBox);\r\n                    pPrintStr = String;\r\n\r\n                }\r\n                UI_PrintStringSmall(pPrintStr, 2, 0, 0 + (vfo_num * 3));\r\n                center_line = CENTER_LINE_IN_USE;\r\n\r\n                continue;\r\n            }\r\n\r\n            // highlight the selected/used VFO with a marker\r\n            if (isMainVFO)\r\n                memcpy(p_line0 + 1, BITMAP_VFO_Default, sizeof(BITMAP_VFO_Default));\r\n        } else // active TX VFO\r\n        {    // highlight the selected/used VFO with a marker\r\n            if (isMainVFO)\r\n                memcpy(p_line0 + 1, BITMAP_VFO_Default, sizeof(BITMAP_VFO_Default));\r\n            else\r\n                memcpy(p_line0 + 1, BITMAP_VFO_NotDefault, sizeof(BITMAP_VFO_NotDefault));\r\n        }\r\n\r\n        if (gCurrentFunction == FUNCTION_TRANSMIT) {    // transmitting\r\n\r\n#ifdef ENABLE_ALARM\r\n            if (gAlarmState == ALARM_STATE_SITE_ALARM)\r\n                mode = VFO_MODE_RX;\r\n            else\r\n#endif\r\n            {\r\n\r\n                if (activeTxVFO == vfo_num) {    // show the TX symbol\r\n                    mode = VFO_MODE_TX;\r\n\r\n                    memcpy(gFrameBuffer[line + 0] + 14, BITMAP_SEND, sizeof(BITMAP_SEND));\r\n\r\n                }\r\n            }\r\n        } else {    // receiving .. show the RX symbol\r\n            mode = VFO_MODE_RX;\r\n            if (FUNCTION_IsRx()) {\r\n                last_rx_vfo = gEeprom.RX_VFO;\r\n                if (gEeprom.RX_VFO == vfo_num)\r\n                    memcpy(gFrameBuffer[line + 0] + 14, BITMAP_RECV, sizeof(BITMAP_RECV));\r\n            }\r\n        }\r\n\r\n        if (IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num])) {    // channel mode\r\n            const unsigned int x = 2;\r\n            const bool inputting = gInputBoxIndex != 0 && gEeprom.TX_VFO == vfo_num;\r\n            if (!inputting) {\r\n                const char *format = last_rx_vfo == vfo_num ? \"M%u.\" : \"M%u\";\r\n                sprintf(String, format, gEeprom.ScreenChannel[vfo_num] + 1);\r\n            } else {\r\n                sprintf(String, \"M%.3s\", INPUTBOX_GetAscii());  // show the input text\r\n            }\r\n            UI_PrintStringSmall(String, x, 0, line + 1);\r\n        } else if (IS_FREQ_CHANNEL(gEeprom.ScreenChannel[vfo_num])) {    // frequency mode\r\n            // show the frequency band number\r\n            const unsigned int x = 2;\r\n            char *buf = gEeprom.VfoInfo[vfo_num].pRX->Frequency < _1GHz_in_KHz ? \"\" : \"+\";\r\n            const char *format = last_rx_vfo == vfo_num ? \"F%u%s.\" : \"F%u%s\";\r\n            sprintf(String, format, 1 + gEeprom.ScreenChannel[vfo_num] - FREQ_CHANNEL_FIRST, buf);\r\n            UI_PrintStringSmall(String, x, 0, line + 1);\r\n        }\r\n#ifdef ENABLE_NOAA\r\n        else\r\n        {\r\n            if (gInputBoxIndex == 0 || gEeprom.TX_VFO != vfo_num)\r\n            {\t// channel number\r\n                sprintf(String, \"N%u\", 1 + gEeprom.ScreenChannel[vfo_num] - NOAA_CHANNEL_FIRST);\r\n            }\r\n            else\r\n            {\t// user entering channel number\r\n                sprintf(String, \"N%u%u\", '0' + gInputBox[0], '0' + gInputBox[1]);\r\n            }\r\n            UI_PrintStringSmall(String, 7, 0, line + 1);\r\n        }\r\n#endif\r\n\r\n        // ************\r\n\r\n        enum VfoState_t state = VfoState[vfo_num];\r\n#ifdef ENABLE_ALARM\r\n        if (gCurrentFunction == FUNCTION_TRANSMIT && gAlarmState == ALARM_STATE_SITE_ALARM) {\r\n            if (activeTxVFO == vfo_num)\r\n                state = VFO_STATE_ALARM;\r\n        }\r\n#endif\r\n\r\n        uint32_t frequency = gEeprom.VfoInfo[vfo_num].pRX->Frequency;\r\n\r\n        if (state != VFO_STATE_NORMAL) {\r\n\r\n            if (state < ARRAY_SIZE(VfoStateStr))\r\n                UI_PrintStringSmall(VfoStateStr[state], 31, 0, line);\r\n        } else if (gInputBoxIndex > 0 && IS_FREQ_CHANNEL(gEeprom.ScreenChannel[vfo_num]) &&\r\n                   gEeprom.TX_VFO == vfo_num) {    // user entering a frequency\r\n\r\n\r\n            const char *ascii = INPUTBOX_GetAscii();\r\n            bool isGigaF = frequency >= _1GHz_in_KHz;\r\n            sprintf(String, \"%.*s.%.3s\", 3 + isGigaF, ascii, ascii + 3 + isGigaF);\r\n#ifdef ENABLE_BIG_FREQ\r\n            if(!isGigaF) {\r\n                // show the remaining 2 small frequency digits\r\n                UI_PrintStringSmall(String + 7, 113, 0, line + 1);\r\n                String[7] = 0;\r\n                // show the main large frequency digits\r\n\r\n                UI_DisplayFrequency(String, 32, line, false);\r\n            }\r\n            else\r\n#endif\r\n            {\r\n                // show the frequency in the main font\r\n                UI_PrintStringSmall(String, 32, 0, line);\r\n            }\r\n            continue;\r\n            //\tif(vfo_num==1)\tbreak;\r\n        } else {\r\n\r\n            if (gCurrentFunction == FUNCTION_TRANSMIT) {    // transmitting\r\n                if (activeTxVFO == vfo_num)\r\n                    frequency = gEeprom.VfoInfo[vfo_num].pTX->Frequency;\r\n            }\r\n\r\n            if (IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num])) {    // it's a channel\r\n\r\n                // show the scan list assigment symbols\r\n\r\n                const ChannelAttributes_t att = gMR_ChannelAttributes[gEeprom.ScreenChannel[vfo_num]];\r\n                if (att.scanlist1) {\r\n#if ENABLE_CHINESE_FULL != 4|| defined(ENABLE_ENGLISH)\r\n                    memcpy(p_line0 + 115, BITMAP_ScanList1, sizeof(BITMAP_ScanList1));\r\n#else\r\n                    if(IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num])      )\r\n                        memcpy(gFrameBuffer[line + 2] + 115, BITMAP_ScanList1, sizeof(BITMAP_ScanList1));\r\n                    else\r\n                        memcpy(p_line0 + 115, BITMAP_ScanList1, sizeof(BITMAP_ScanList1));\r\n#endif\r\n\r\n                }\r\n\r\n\r\n                if (att.scanlist2) {\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n                    memcpy(p_line0 + 121, BITMAP_ScanList2, sizeof(BITMAP_ScanList2));\r\n#else\r\n                    if(IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num])        )\r\n                    memcpy(gFrameBuffer[line + 2] + 121, BITMAP_ScanList2, sizeof(BITMAP_ScanList2));\r\n            else\r\n                        memcpy(p_line0 + 121, BITMAP_ScanList2, sizeof(BITMAP_ScanList2));\r\n#endif\r\n\r\n                }\r\n\r\n\r\n                // compander symbol\r\n#ifndef ENABLE_BIG_FREQ\r\n                if (att.compander)\r\n                    memcpy(p_line0 + 121 + LCD_WIDTH, BITMAP_compand, sizeof(BITMAP_compand));\r\n#else\r\n                // TODO:  // find somewhere else to put the symbol\r\n#endif\r\n\r\n                switch (gEeprom.CHANNEL_DISPLAY_MODE) {\r\n                    case MDF_FREQUENCY:    // show the channel frequency\r\n                        sprintf(String, \"%3u.%05u\", frequency / 100000, frequency % 100000);\r\n#ifdef ENABLE_BIG_FREQ\r\n                        if(frequency < _1GHz_in_KHz) {\r\n                            // show the remaining 2 small frequency digits\r\n                            UI_PrintStringSmall(String + 7, 113, 0, line + 1);\r\n                            String[7] = 0;\r\n                            // show the main large frequency digits\r\n\r\n\r\n                            UI_DisplayFrequency(String, 32, line, false);\r\n                        }\r\n                        else\r\n#endif\r\n                        {\r\n                            // show the frequency in the main font\r\n                            UI_PrintStringSmall(String, 32, 0, line);\r\n                        }\r\n\r\n                        break;\r\n\r\n                    case MDF_CHANNEL:    // show the channel number\r\n                        sprintf(String, \"CH-%03u\", gEeprom.ScreenChannel[vfo_num] + 1);\r\n                        UI_PrintStringSmall(String, 32, 0, line);\r\n                        break;\r\n\r\n                    case MDF_NAME:        // show the channel name\r\n                    case MDF_NAME_FREQ:    // show the channel name and frequency\r\n\r\n                        SETTINGS_FetchChannelName(String, gEeprom.ScreenChannel[vfo_num]);\r\n                        if (String[0] == 0) {    // no channel name, show the channel number instead\r\n                            sprintf(String, \"CH-%03u\", gEeprom.ScreenChannel[vfo_num] + 1);\r\n                        }\r\n\r\n                        if (gEeprom.CHANNEL_DISPLAY_MODE == MDF_NAME) {\r\n#if ENABLE_CHINESE_FULL == 4&&! defined(ENABLE_ENGLISH)\r\n                            show_move_flag=1;\r\n#endif\r\n                            UI_PrintStringSmall(String, 32, 0, line);\r\n                        } else {\r\n#if ENABLE_CHINESE_FULL == 4 && !defined(ENABLE_ENGLISH)\r\n                            show_move_flag=1;\r\n#endif\r\n                            UI_PrintStringSmall(String, 32 + 4, 0, line);\r\n\r\n                            // show the channel frequency below the channel number/name\r\n                            sprintf(String, \"%03u.%05u\", frequency / 100000, frequency % 100000);\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n                            UI_PrintStringSmall(String, 32 + 4, 0, line + 1);\r\n#else\r\n                            UI_PrintStringSmall(String, 32 + 4, 0, line + 2);\r\n\r\n#endif\r\n\r\n                        }\r\n\r\n                        break;\r\n                }\r\n            } else {    // frequency mode\r\n\r\n                sprintf(String, \"%3u.%05u\", frequency / 100000, frequency % 100000);\r\n\r\n#ifdef ENABLE_BIG_FREQ\r\n                if(frequency < _1GHz_in_KHz) {\r\n                    // show the remaining 2 small frequency digits\r\n                    UI_PrintStringSmall(String + 7, 113, 0, line + 1);\r\n                    String[7] = 0;\r\n                    // show the main large frequency digits\r\n                    UI_DisplayFrequency(String, 32, line, false);\r\n                }\r\n                else\r\n#endif\r\n                {\r\n                    // show the frequency in the main font\r\n                    UI_PrintStringSmall(String, 32, 0, line);\r\n                }\r\n\r\n                // show the channel symbols\r\n                const ChannelAttributes_t att = gMR_ChannelAttributes[gEeprom.ScreenChannel[vfo_num]];\r\n                if (att.compander)\r\n\r\n#ifdef ENABLE_BIG_FREQ\r\n                    memcpy(p_line0 + 121, BITMAP_compand, sizeof(BITMAP_compand));\r\n#else\r\n                    memcpy(p_line0 + 121 + LCD_WIDTH, BITMAP_compand, sizeof(BITMAP_compand));\r\n#endif\r\n            }\r\n        }\r\n\r\n        // ************\r\n\r\n        {    // show the TX/RX level\r\n            uint8_t Level = 0;\r\n\r\n            if (mode == VFO_MODE_TX) {    // TX power level\r\n                switch (gRxVfo->OUTPUT_POWER) {\r\n                    case OUTPUT_POWER_LOW:\r\n                        Level = 2;\r\n                        break;\r\n                    case OUTPUT_POWER_MID:\r\n                        Level = 4;\r\n                        break;\r\n                    case OUTPUT_POWER_HIGH:\r\n                        Level = 6;\r\n                        break;\r\n                }\r\n            } else if (mode == VFO_MODE_RX) {    // RX signal level\r\n#ifndef ENABLE_RSSI_BAR\r\n                // bar graph\r\n                if (gVFO_RSSI_bar_level[vfo_num] > 0)\r\n                    Level = gVFO_RSSI_bar_level[vfo_num];\r\n#endif\r\n            }\r\n            if (Level) {\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n                DrawSmallAntennaAndBars(p_line1 + LCD_WIDTH, Level);\r\n#else\r\n                if (IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num])) {\r\n                    if (!gDTMF_IsTx\r\n                        && gDTMF_CallState != DTMF_CALL_STATE_CALL_OUT\r\n                        && gDTMF_CallState != DTMF_CALL_STATE_RECEIVED\r\n                        && gDTMF_CallState != DTMF_CALL_STATE_RECEIVED_STAY\r\n                    ) {\r\n                        DrawSmallAntennaAndBars(gFrameBuffer[2] + LCD_WIDTH, Level);\r\n                        audio_keep_flag = true;\r\n                    }\r\n                } else {\r\n                    DrawSmallAntennaAndBars(p_line1 + LCD_WIDTH, Level);\r\n                }\r\n#endif\r\n            }\r\n        }\r\n\r\n        // ************\r\n\r\n        String[0] = '\\0';\r\n        const VFO_Info_t *vfoInfo = &gEeprom.VfoInfo[vfo_num];\r\n        // show the modulation symbol\r\n        const char *s = \"\";\r\n        const ModulationMode_t mod = vfoInfo->Modulation;\r\n        switch (mod) {\r\n            case MODULATION_FM: {\r\n                const FREQ_Config_t *pConfig = (mode == VFO_MODE_TX) ? vfoInfo->pTX : vfoInfo->pRX;\r\n                const unsigned int code_type = pConfig->CodeType;\r\n                const char *code_list[] = {\"\", \"CT\", \"DCS\", \"DCR\"};\r\n                //   UART_Send((uint8_t*)&code_type,1);\r\n                if (code_type < ARRAY_SIZE(code_list))\r\n                    s = code_list[code_type];\r\n                break;\r\n            }\r\n            default:\r\n                s = gModulationStr[mod];\r\n                break;\r\n        }\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n        UI_PrintStringSmall(s, LCD_WIDTH + 24, 0, line + 1); //中文信道1\r\n#else\r\n        if (IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num]))\r\n            UI_PrintStringSmall(s, LCD_WIDTH + 0, 0, line + 1); //中文信道1\r\n        else\r\n            UI_PrintStringSmall(s, LCD_WIDTH + 24, 0, line + 1); //中文信道1\r\n\r\n\r\n        const bool bFlagMr = IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num]) && !(FUNCTION_IsRx() && gEeprom.RX_VFO == vfo_num) && !(gCurrentFunction == FUNCTION_TRANSMIT && activeTxVFO == vfo_num);\r\n        const bool bFlagFreq = !IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num]);\r\n\r\n#endif\r\n        if (state == VFO_STATE_NORMAL || state == VFO_STATE_ALARM) {    // show the TX power\r\n\r\n            const char pwr_list[][2] = {\"L\", \"M\", \"H\"};\r\n            const unsigned int i = vfoInfo->OUTPUT_POWER % 3;\r\n\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n            UI_PrintStringSmall(pwr_list[i], LCD_WIDTH + 46, 0, line + 1); //中文信道1\r\n#else\r\n\r\n            if (bFlagMr)\r\n                UI_PrintStringSmall(pwr_list[i], LCD_WIDTH + 9, 0, line - 1); //中文信道1\r\n            else if (bFlagFreq)\r\n                UI_PrintStringSmall(pwr_list[i], LCD_WIDTH + 46, 0, line + 1); //中文信道1\r\n\r\n#endif\r\n        }\r\n\r\n        if (vfoInfo->freq_config_RX.Frequency !=\r\n            vfoInfo->freq_config_TX.Frequency) {    // show the TX offset symbol\r\n            const char dir_list[][2] = {\"\", \"+\", \"-\"};\r\n            const unsigned int i = vfoInfo->TX_OFFSET_FREQUENCY_DIRECTION % 3;\r\n\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n            UI_PrintStringSmall(dir_list[i], LCD_WIDTH + 54, 0, line + 1);//中文信道1\r\n#else\r\n            if (bFlagMr)\r\n                UI_PrintStringSmall(dir_list[i], LCD_WIDTH + 17, 0, line - 1); //中文信道1\r\n            else if (bFlagFreq)\r\n                UI_PrintStringSmall(dir_list[i], LCD_WIDTH + 54, 0, line + 1); //中文信道1\r\n#endif\r\n        }\r\n\r\n        // show the TX/RX reverse symbol\r\n        if (vfoInfo->FrequencyReverse) {\r\n            char *flag = vfoInfo->FrequencyReverse == 1 ? \"R\" : \"T\";\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n            UI_PrintStringSmall(flag, LCD_WIDTH + 62, 0, line + 1);//中文信道1\r\n#else\r\n            if (bFlagMr)\r\n                UI_PrintStringSmall(flag, LCD_WIDTH + 24, 0, line - 1); //中文信道1\r\n            else if (bFlagFreq)\r\n                UI_PrintStringSmall(flag, LCD_WIDTH + 62, 0, line + 1); //中文信道1\r\n\r\n#endif\r\n        }\r\n        {\r\n            // show the narrow band symbol\r\n            if (vfoInfo->CHANNEL_BANDWIDTH == BANDWIDTH_NARROW) {\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n                UI_PrintStringSmall(\"N\", LCD_WIDTH + 70, 0, line + 1);\r\n#else\r\n                if (IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num]))\r\n                    UI_PrintStringSmall(\"N\", LCD_WIDTH + 21, 0, line + 1);\r\n                else\r\n                    UI_PrintStringSmall(\"N\", LCD_WIDTH + 70, 0, line + 1);\r\n#endif\r\n            }\r\n        }\r\n#ifdef ENABLE_DTMF_CALLING\r\n        // show the DTMF decoding symbol\r\n        if (vfoInfo->DTMF_DECODING_ENABLE || gSetting_KILLED) {\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n            UI_PrintStringSmall(\"DTMF\", LCD_WIDTH + 78, 0, line + 1);//中文信道1\r\n#else\r\n            if (IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num]))\r\n                UI_PrintStringSmall(\"D\", LCD_WIDTH + 105, 0, line + 1); //中文信道1\r\n            else\r\n                UI_PrintStringSmall(\"DTMF\", LCD_WIDTH + 78, 0, line + 1); //中文信道1\r\n#endif\r\n        }\r\n\r\n#endif\r\n        // show the audio scramble symbol\r\n        if (vfoInfo->SCRAMBLING_TYPE > 0/* && gSetting_ScrambleEnable*/) {\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n            UI_PrintStringSmall(\"ENC\", LCD_WIDTH + 106, 0, line + 1);//中文信道1\r\n#else\r\n            if (IS_MR_CHANNEL(gEeprom.ScreenChannel[vfo_num]))\r\n                UI_PrintStringSmall(\"E\", LCD_WIDTH + 29, 0, line + 1); //中文信道1 ok\r\n            else\r\n                UI_PrintStringSmall(\"ENC\", LCD_WIDTH + 106, 0, line + 1); //中文信道1\r\n#endif\r\n        }\r\n    }\r\n#ifdef ENABLE_AGC_SHOW_DATA\r\n    center_line = CENTER_LINE_IN_USE;\r\n  UI_MAIN_PrintAGC(false);\r\n#endif\r\n    if (center_line == CENTER_LINE_NONE) {    // we're free to use the middle line\r\n\r\n        const bool rx = FUNCTION_IsRx();\r\n#ifdef ENABLE_MDC1200\r\n\r\n        if (mdc1200_rx_ready_tick_500ms > 0) {\r\n            char mdc1200_contact[14];\r\n            center_line = CENTER_LINE_MDC1200;\r\n            uint8_t print_col = 0;\r\n            if (mdc1200_contact_find(mdc1200_unit_id, mdc1200_contact))//\r\n            {\r\n\r\n                memcpy(String, mdc1200_contact, 14);\r\n                String[14] = 0;\r\n                print_col = 29;\r\n            } else {\r\n                sprintf(String, \"ID %04X\", mdc1200_unit_id);\r\n                print_col = 40;\r\n            }\r\n\r\n//#ifdef ENABLE_MDC1200_SHOW_OP_ARG\r\n//                sprintf(String, \"MDC1200 %02X %02X %04X\", mdc1200_op, mdc1200_arg, mdc1200_unit_id);\r\n//#else\r\n//                sprintf(String, \"MDC1200 ID %04X\", mdc1200_unit_id);\r\n//#endif\r\n\r\n            UI_PrintStringSmall(String, print_col, 0, 3);\r\n\r\n\r\n        } else\r\n#endif\r\n\r\n//#ifdef ENABLE_AUDIO_BAR\r\n        if (gCurrentFunction == FUNCTION_TRANSMIT) {\r\n            center_line = CENTER_LINE_AUDIO_BAR;\r\n            UI_DisplayAudioBar();\r\n        } else\r\n//#endif\r\n\r\n#if defined(ENABLE_AM_FIX) && defined(ENABLE_AM_FIX_SHOW_DATA)\r\n            if (rx && gEeprom.VfoInfo[gEeprom.RX_VFO].Modulation == MODULATION_AM && gSetting_AM_fix)\r\n            {\r\n                if (gScreenToDisplay != DISPLAY_MAIN\r\n#ifdef ENABLE_DTMF_CALLING\r\n                    || gDTMF_CallState != DTMF_CALL_STATE_NONE\r\n#endif\r\n                    )\r\n                    return;\r\n\r\n                center_line = CENTER_LINE_AM_FIX_DATA;\r\n                AM_fix_print_data(gEeprom.RX_VFO, String);\r\n                UI_PrintStringSmall(String, 2, 0, 3);\r\n            }\r\n            else\r\n#endif\r\n\r\n#ifdef ENABLE_RSSI_BAR\r\n            if (rx) {\r\n                center_line = CENTER_LINE_RSSI;\r\n          DisplayRSSIBar(false);\r\n            }\r\n            else\r\n#endif\r\n\r\n        if (rx || gCurrentFunction == FUNCTION_FOREGROUND || gCurrentFunction == FUNCTION_POWER_SAVE) {\r\n#if 1\r\n            if (gSetting_live_DTMF_decoder && gDTMF_RX_live[0] != 0) {    // show live DTMF decode\r\n                const unsigned int len = strlen(gDTMF_RX_live);\r\n                const unsigned int idx = (len > (17 - 5)) ? len - (17 - 5) : 0;  // limit to last 'n' chars\r\n\r\n                if (gScreenToDisplay != DISPLAY_MAIN ||\r\n                    gDTMF_CallState != DTMF_CALL_STATE_NONE)\r\n                    return;\r\n\r\n                center_line = CENTER_LINE_DTMF_DEC;\r\n\r\n                sprintf(String, \"DTMF %s\", gDTMF_RX_live + idx);\r\n                UI_PrintStringSmall(String, 2, 0, 3);\r\n            }\r\n#else\r\n            if (gSetting_live_DTMF_decoder && gDTMF_RX_index > 0)\r\n            {\t// show live DTMF decode\r\n                const unsigned int len = gDTMF_RX_index;\r\n                const unsigned int idx = (len > (17 - 5)) ? len - (17 - 5) : 0;  // limit to last 'n' chars\r\n\r\n                if (gScreenToDisplay != DISPLAY_MAIN ||\r\n                    gDTMF_CallState != DTMF_CALL_STATE_NONE)\r\n                    return;\r\n\r\n                center_line = CENTER_LINE_DTMF_DEC;\r\n\r\n                sprintf(String, \"DTMF %s\", gDTMF_RX_live + idx);\r\n                UI_PrintStringSmall(String, 2, 0, 3);\r\n            }\r\n#endif\r\n\r\n#ifdef ENABLE_SHOW_CHARGE_LEVEL\r\n            else if (gChargingWithTypeC)\r\n            {\t// charging .. show the battery state\r\n                if (gScreenToDisplay != DISPLAY_MAIN\r\n#ifdef ENABLE_DTMF_CALLING\r\n                    || gDTMF_CallState != DTMF_CALL_STATE_NONE\r\n#endif\r\n                    )\r\n                    return;\r\n\r\n                center_line = CENTER_LINE_CHARGE_DATA;\r\n\r\n                sprintf(String, \"Charge %u.%02uV %u%%\",\r\n                    gBatteryVoltageAverage / 100, gBatteryVoltageAverage % 100,\r\n                    BATTERY_VoltsToPercent(gBatteryVoltageAverage));\r\n                UI_PrintStringSmall(String, 2, 0, 3);\r\n            }\r\n#endif\r\n\r\n\r\n        }\r\n    }\r\n\r\n    ST7565_BlitFullScreen();\r\n}\r\n\r\n// ***************************************************************************\r\n"
  },
  {
    "path": "ui/main.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_MAIN_H\r\n#define UI_MAIN_H\r\n\r\nenum center_line_t {\r\n\tCENTER_LINE_NONE = 0,\r\n\tCENTER_LINE_IN_USE,\r\n\tCENTER_LINE_AUDIO_BAR,\r\n\tCENTER_LINE_RSSI,\r\n\tCENTER_LINE_AM_FIX_DATA,\r\n\tCENTER_LINE_DTMF_DEC,\r\n\tCENTER_LINE_CHARGE_DATA,\r\n    CENTER_LINE_MDC1200\r\n};\r\nenum Vfo_txtr_mode{\r\n    VFO_MODE_NONE = 0,\r\n    VFO_MODE_TX = 1,\r\n    VFO_MODE_RX = 2,\r\n};\r\ntypedef enum center_line_t center_line_t;\r\n#ifdef ENABLE_AGC_SHOW_DATA\r\nvoid UI_MAIN_PrintAGC(bool force);\r\n#endif\r\nextern center_line_t center_line;\r\n\r\nvoid UI_DisplayAudioBar(void);\r\n\r\nvoid UI_DisplayMain(void);\r\nvoid UI_MAIN_TimeSlice500ms(void);\r\nextern const int8_t dBmCorrTable[7];\r\n#endif\r\n\r\n"
  },
  {
    "path": "ui/menu.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include \"driver/eeprom.h\"\r\n#include <string.h>\r\n#include <stdlib.h>  // abs()\r\n#include \"bitmaps.h\"\r\n#include \"driver/uart.h\"\r\n#include \"app/dtmf.h\"\r\n#include \"app/menu.h\"\r\n#include \"board.h\"\r\n#include \"dcs.h\"\r\n#include \"driver/backlight.h\"\r\n#include \"driver/bk4819.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"frequencies.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/menu.h\"\r\n#include \"ui/ui.h\"\r\n#include \"chinese.h\"\r\n\r\nvoid insertNewline(char a[], int index, int len) {\r\n\r\n    if (index < 0 || index >= len || len >= 63) {\r\n        return;\r\n    }\r\n    for (int i = len; i >= index; i--) {\r\n        a[i + 1] = a[i];\r\n    }\r\n    a[index] = '\\n';\r\n    a[len + 1] = '\\0'; // Null-terminate the string\r\n}\r\n\r\nconst t_menu_item MenuList[] =\r\n        {\r\n//   text,     voice ID,                               menu ID\r\n                {/*\"Step\",*/   VOICE_ID_FREQUENCY_STEP, MENU_STEP, 步进频率},\r\n                {/*\"RxDCS\",*/  VOICE_ID_DCS, MENU_R_DCS, 接收数字亚音}, // was \"R_DCS\"\r\n                {/*\"RxCTCS\",*/ VOICE_ID_CTCSS, MENU_R_CTCS, 接收模拟亚音}, // was \"R_CTCS\"\r\n                {/*\"TxDCS\",*/  VOICE_ID_DCS, MENU_T_DCS, 发送数字亚音}, // was \"T_DCS\"\r\n                {/*\"TxCTCS\",*/ VOICE_ID_CTCSS, MENU_T_CTCS, 发送模拟亚音}, // was \"T_CTCS\"\r\n                {/*\"TxODir\",*/ VOICE_ID_TX_OFFSET_FREQUENCY_DIRECTION, MENU_SFT_D, 频差方向}, // was \"SFT_D\"\r\n                {/*\"TxOffs\",*/ VOICE_ID_TX_OFFSET_FREQUENCY, MENU_OFFSET, 频差频率}, // was \"OFFSET\"\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n                {/*\"W/N\",*/    VOICE_ID_CHANNEL_BANDWIDTH,             MENU_W_N           ,宽窄带},\r\n#endif\r\n\r\n                {/*\"Scramb\",*/ VOICE_ID_SCRAMBLER_ON, MENU_SCR, 加密}, // was \"SCR\"\r\n                {/*\"BusyCL\",*/ VOICE_ID_BUSY_LOCKOUT, MENU_BCL, 遇忙禁发}, // was \"BCL\"\r\n                {/*\"Compnd\",*/ VOICE_ID_INVALID, MENU_COMPAND, 压扩},\r\n                {/*\"ChSave\",*/ VOICE_ID_MEMORY_CHANNEL, MENU_MEM_CH, 存置信道}, // was \"MEM-CH\"\r\n                {/*\"ChDele\",*/ VOICE_ID_DELETE_CHANNEL, MENU_DEL_CH, 删除信道}, // was \"DEL-CH\"\r\n                {/*\"ChName\",*/ VOICE_ID_INVALID, MENU_MEM_NAME, 命名信道},\r\n                {/*\"SList\",*/  VOICE_ID_INVALID, MENU_S_LIST, 信道扫描列表},\r\n                {/*\"SList1\",*/ VOICE_ID_INVALID, MENU_SLIST1, 扫描列表1},\r\n                {/*\"SList2\",*/ VOICE_ID_INVALID, MENU_SLIST2, 扫描列表2},\r\n                {/*\"ScnRev\",*/ VOICE_ID_INVALID, MENU_SC_REV, 搜索恢复模式},\r\n                {/*\"TxTOut\",*/ VOICE_ID_TRANSMIT_OVER_TIME, MENU_TOT, 发送超时}, // was \"TOT\"\r\n                {/*\"BatSav\",*/ VOICE_ID_SAVE_MODE, MENU_SAVE, 省电模式}, // was \"SAVE\"\r\n                {/*\"Mic\",*/    VOICE_ID_INVALID, MENU_MIC, 麦克风增益},\r\n                {/*\"ChDisp\",*/ VOICE_ID_INVALID, MENU_MDF, 信道显示模式}, // was \"MDF\"\r\n#if ENABLE_CHINESE_FULL == 4\r\n                {/*\"POnMsg\",*/ VOICE_ID_INVALID,                       MENU_PONMSG        ,开机显示},\r\n#endif\r\n                {/*\"BackLt\",*/ VOICE_ID_INVALID, MENU_ABR, 自动背光}, // was \"ABR\"\r\n                {/*\"BLMax\",*/  VOICE_ID_INVALID, MENU_ABR_MAX, 背光亮度},\r\n                {/*\"MDCID\",*/  VOICE_ID_INVALID, MENU_MDC_ID, MDC_ID},\r\n\r\n                {/*\"Roger\",*/  VOICE_ID_INVALID, MENU_ROGER, 首尾音},\r\n\r\n                {/*\"STE\",*/    VOICE_ID_INVALID, MENU_STE, 尾音消除},\r\n                {/*\"RP STE\",*/ VOICE_ID_INVALID, MENU_RP_STE, 过中继尾音消除},\r\n                {/*\"1 Call\",*/ VOICE_ID_INVALID, MENU_1_CALL, 按键即呼},\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n                {/*\"F1Shrt\",*/ VOICE_ID_INVALID,                       MENU_F1SHRT        ,侧键1短按},\r\n                {/*\"F1Long\",*/ VOICE_ID_INVALID,                       MENU_F1LONG        ,侧键1长按},\r\n                {/*\"F2Shrt\",*/ VOICE_ID_INVALID,                       MENU_F2SHRT        ,侧键2短按},\r\n                {/*\"F2Long\",*/ VOICE_ID_INVALID,                       MENU_F2LONG        ,侧键2长按},\r\n                {/*\"M Long\",*/ VOICE_ID_INVALID,                       MENU_MLONG         ,M键长按},\r\n#endif\r\n\r\n#ifdef ENABLE_DTMF_CALLING\r\n\r\n                {/*\"ANI ID\",*/ VOICE_ID_ANI_CODE,                      MENU_ANI_ID        ,DTMF_ID},\r\n#endif\r\n                {/*\"UPCode\",*/ VOICE_ID_INVALID, MENU_UPCODE, DTMF上线码},\r\n                {/*\"DWCode\",*/ VOICE_ID_INVALID, MENU_DWCODE, DTMF下线码},\r\n                {/*\"PTT ID\",*/ VOICE_ID_INVALID, MENU_PTT_ID, DTMF发送},\r\n                {/*\"D ST\",*/   VOICE_ID_INVALID, MENU_D_ST, DTMF侧音},\r\n#ifdef ENABLE_DTMF_CALLING\r\n\r\n                {/*\"D Resp\",*/ VOICE_ID_INVALID,                       MENU_D_RSP         ,DTMF响应},\r\n                {/*\"D Hold\",*/ VOICE_ID_INVALID,                       MENU_D_HOLD        ,DTMF复位},\r\n#endif\r\n                {/*\"D Prel\",*/ VOICE_ID_INVALID, MENU_D_PRE, DTMF预载波},\r\n#ifdef ENABLE_DTMF_CALLING\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n                {/*\"D Decd\",*/ VOICE_ID_INVALID,                       MENU_D_DCD         ,DTMF解码},\r\n#endif\r\n                {/*\"D List\",*/ VOICE_ID_INVALID,                       MENU_D_LIST        ,DTMF联系人},\r\n#endif\r\n                {/*\"D Live\",*/ VOICE_ID_INVALID, MENU_D_LIVE_DEC, DTMF显示}, // live DTMF decoder\r\n#ifdef ENABLE_AM_FIX//1\r\n                {/*\"AM Fix\",*/ VOICE_ID_INVALID,                       MENU_AM_FIX        ,AM自动增益},\r\n#endif\r\n#ifdef ENABLE_AM_FIX_TEST1//0\r\n                {/*\"AM FT1\",*/ VOICE_ID_INVALID,                       MENU_AM_FIX_TEST1  ,\"\"},\r\n#endif\r\n\r\n                {/*\"RxMode\",*/ VOICE_ID_DUAL_STANDBY, MENU_TDR, 收发模式},\r\n                {/*\"Sql\",*/    VOICE_ID_SQUELCH, MENU_SQL, 静噪等级},\r\n\r\n                // hidden menu items from here on\r\n                // enabled if pressing both the PTT and upper side button at power-on\r\n                {/*\"F Lock\",*/ VOICE_ID_INVALID, MENU_F_LOCK, 频段解锁},\r\n//                {/*\"Tx 200\",*/ VOICE_ID_INVALID,                       MENU_200TX         ,两百M发射}, // was \"200TX\"\r\n//                {/*\"Tx 350\",*/ VOICE_ID_INVALID,                       MENU_350TX         ,三百五十M发射}, // was \"350TX\"\r\n//                {/*\"Tx 500\",*/ VOICE_ID_INVALID,                       MENU_500TX         ,五百M发射}, // was \"500TX\"\r\n//                {/*\"350 En\",*/ VOICE_ID_INVALID,                       MENU_350EN         ,三百五十M接收}, // was \"350EN\"\r\n#ifdef ENABLE_F_CAL_MENU//0\r\n                {/*\"FrCali\",*/ VOICE_ID_INVALID,                       MENU_F_CALI        ,\"\"}, // reference xtal calibration\r\n#endif\r\n                {/*\"BatCal\",*/ VOICE_ID_INVALID, MENU_BATCAL, 电池调压}, // battery voltage calibration\r\n                {/*\"BatTyp\",*/ VOICE_ID_INVALID, MENU_BATTYP, 电池大小}, // battery type 1600/2200mAh\r\n                {/*\"Reset\",*/  VOICE_ID_INITIALISATION, MENU_RESET,\r\n                               参数复位}, // might be better to move this to the hidden menu items ?\r\n\r\n                {/*\"\",*/       VOICE_ID_INVALID, 0xff, \"\\x00\"}  // end of list - DO NOT delete or move this this\r\n        };\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n#if ENABLE_CHINESE_FULL==0 || defined(ENABLE_ENGLISH)\r\n#ifdef ENABLE_ENGLISH\r\nconst char gSubMenu_W_N[][7] =//7\r\n\r\n#else\r\nconst char gSubMenu_W_N[][3] =//7\r\n\r\n#endif\r\n#else\r\n        const char gSubMenu_W_N[][5] =//7\r\n#endif\r\n        {\r\n//                \"WIDE\",\r\n//                \"NARROW\"\r\n                宽带,\r\n               窄带\r\n        };\r\n#endif\r\n#if ENABLE_CHINESE_FULL == 4\r\nconst char gSubMenu_PONMSG[][5]={\r\n        关闭,\r\n        图片,\r\n        信息\r\n};\r\n#endif\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n#ifdef ENABLE_ENGLISH\r\nconst char gSubMenu_SFT_D[][4] =\r\n\r\n#else\r\nconst char gSubMenu_SFT_D[][10] =//4\r\n#endif\r\n#else\r\n        const char gSubMenu_SFT_D[][16] =//4\r\n#endif\r\n        {\r\n//                \"OFF\",\r\n//                \"+\",\r\n//                \"-\"\r\n                发送等于接收,\r\n                发送等于接收加偏移,\r\n                发送等于接收减偏移\r\n\r\n        };\r\n\r\n\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n#ifdef ENABLE_ENGLISH\r\nconst char gSubMenu_OFF_ON[][4] =\r\n\r\n#else\r\nconst char gSubMenu_OFF_ON[][3] =//4\r\n#endif\r\n\r\n#else\r\n        const char gSubMenu_OFF_ON[][5] =//4\r\n#endif\r\n        {\r\n//                \"OFF\",\r\n//                \"ON\"\r\n                关闭,\r\n                开启\r\n        };\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\nconst char gSubMenu_SAVE[][4] =//4\r\n#else\r\n        const char gSubMenu_SAVE[][6] =//4\r\n#endif\r\n        {\r\n//                \"OFF\",\r\n//                \"1:1\",\r\n//                \"1:2\",\r\n//                \"1:3\",\r\n//                \"1:4\"\r\n\r\n                关闭,\r\n                一级,\r\n                二级,\r\n                三级,\r\n                四级\r\n\r\n        };\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\nconst char gSubMenu_TOT[][7] = //7\r\n#else\r\n        const char gSubMenu_TOT[][6] = //7\r\n#endif\r\n        {\r\n//                \"30 sec\",\r\n//                \"1 min\",\r\n//                \"2 min\",\r\n//                \"3 min\",\r\n//                \"4 min\",\r\n//                \"5 min\",\r\n//                \"6 min\",\r\n//                \"7 min\",\r\n//                \"8 min\",\r\n//                \"9 min\",\r\n//                \"15 min\"\r\n\r\n                三十秒,\r\n                一分,\r\n                两分,\r\n                三分,\r\n                四分,\r\n                五分,\r\n                六分,\r\n                七分,\r\n                八分,\r\n                九分,\r\n                十五分\r\n\r\n        };\r\n\r\nconst char *const gSubMenu_RXMode[] =\r\n        {\r\n\r\n//                \"MAIN\\nONLY\",        // TX and RX on main only\r\n//                \"DUAL RX\\nRESPOND\", // Watch both and respond\r\n//                \"CROSS\\nBAND\",        // TX on main, RX on secondary\r\n//                \"MAIN TX\\nDUAL RX\"    // always TX on main, but RX on both\r\n                主信道接收发射,        // TX and RX on main only\r\n                双信道接收, // Watch both and respond\r\n                主信道发射副信道接收,        // TX on main, RX on secondary\r\n                主信道发射双信道接收    // always TX on main, but RX on both\r\n\r\n        };\r\n\r\n#ifdef ENABLE_VOICE\r\nconst char gSubMenu_VOICE[][4] =\r\n{\r\n    \"OFF\",\r\n    \"CHI\",\r\n    \"ENG\"\r\n};\r\n#endif\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n#ifdef ENABLE_ENGLISH\r\nconst char gSubMenu_SC_REV[][8] =//8\r\n\r\n#else\r\nconst char gSubMenu_SC_REV[][10] =//8\r\n#endif\r\n\r\n#else\r\n        const char gSubMenu_SC_REV[][18] =//8\r\n#endif\r\n        {\r\n//                \"TIMEOUT\",\r\n//                \"CARRIER\",\r\n//                \"STOP\"\r\n                遇信号5秒后搜索,\r\n                信号停止后搜索,\r\n                遇信号后停止搜索\r\n\r\n        };\r\n\r\nconst char *const gSubMenu_MDF[] =\r\n        {\r\n//                \"FREQ\",\r\n//                \"CHANNEL\\nNUMBER\",\r\n//                \"NAME\",\r\n//                \"NAME\\n+\\nFREQ\"\r\n                频率,\r\n                信道号,\r\n                名称,\r\n                名称加频率\r\n        };\r\n\r\n#ifdef ENABLE_ALARM\r\nconst char gSubMenu_AL_MOD[][5] =\r\n{\r\n    \"SITE\",\r\n    \"TONE\"\r\n};\r\n#endif\r\n#ifdef ENABLE_DTMF_CALLING\r\n#if ENABLE_CHINESE_FULL!=4 || defined(ENABLE_ENGLISH)\r\n\r\n#ifdef ENABLE_ENGLISH\r\nconst char gSubMenu_D_RSP[][11] =//11\r\n\r\n#else\r\nconst char gSubMenu_D_RSP[][10] =//11\r\n#endif\r\n#else\r\nconst char gSubMenu_D_RSP[][18] =//11\r\n#endif\r\n        {\r\n//                \"DO\\nNOTHING\",\r\n//                \"RING\",\r\n//                \"REPLY\",\r\n//                \"BOTH\"\r\n                不响应,\r\n                本地响铃,\r\n                回复响应,\r\n               本地响铃回复响应\r\n        };\r\n#endif\r\n\r\nconst char *const gSubMenu_PTT_ID[] =\r\n        {\r\n//                \"OFF\",\r\n//                \"UP CODE\",\r\n//                \"DOWN CODE\",\r\n//                \"UP+DOWN\\nCODE\",\r\n//                \"APOLLO\\nQUINDAR\"\r\n                不发送,\r\n                上线码,\r\n                下线码,\r\n                上线加下线码,\r\n                Quindar码\r\n        };\r\n\r\n\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n\r\n#ifdef ENABLE_ENGLISH\r\nconst char gSubMenu_ROGER[][15] =\r\n\r\n#else\r\nconst char gSubMenu_ROGER[][13] =\r\n#endif\r\n#else\r\n        const char gSubMenu_ROGER[][15] =\r\n#endif\r\n        {\r\n//                \"OFF\",\r\n//                \"ROGER\",\r\n//                \"MDC\"\r\n\r\n                关闭,\r\n                ROGER尾音,\r\n                MDC尾音,\r\n                MDC首音,\r\n                MDC首尾音,\r\n                MDC首音加ROGER\r\n        };\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n#ifdef ENABLE_ENGLISH\r\nconst char gSubMenu_RESET[][4] =//4\r\n\r\n#else\r\nconst char gSubMenu_RESET[][6] =//4\r\n#endif\r\n\r\n#else\r\n        const char gSubMenu_RESET[][11] =//4\r\n#endif\r\n        {\r\n//                \"VFO\",\r\n//                \"ALL\"\r\n                除信道参数,\r\n                全部参数\r\n        };\r\n\r\nconst char *const gSubMenu_F_LOCK[] =\r\n        {\r\n                \"DEFAULT+\\n137-174\\n400-470\",\r\n                \"FCC HAM\\n144-148\\n420-450\",\r\n                \"CE HAM\\n144-146\\n430-440\",\r\n                \"GB HAM\\n144-148\\n430-440\",\r\n\r\n//                \"DISABLE\\nALL\",\r\n//                \"UNLOCK\\nALL\",\r\n                禁用全部,\r\n                解锁全部,\r\n        };\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n#ifdef ENABLE_ENGLISH\r\nconst char gSubMenu_BACKLIGHT[][7] =//7\r\n\r\n#else\r\nconst char gSubMenu_BACKLIGHT[][5] =//7\r\n#endif\r\n#else\r\n        const char gSubMenu_BACKLIGHT[][6] =//7\r\n#endif\r\n        {\r\n//                \"OFF\",\r\n//                \"5 sec\",\r\n//                \"10 sec\",\r\n//                \"20 sec\",\r\n//                \"1 min\",\r\n//                \"2 min\",\r\n//                \"4 min\",\r\n//                \"ON\"\r\n                关闭,\r\n                五秒,\r\n                十秒,\r\n                二十秒,\r\n                一分,\r\n                两分,\r\n                四分,\r\n                开启\r\n\r\n        };\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n\r\n#ifdef ENABLE_ENGLISH\r\nconst char gSubMenu_RX_TX[][6] =//6\r\n\r\n#else\r\nconst char gSubMenu_RX_TX[][7] =//6\r\n#endif\r\n#else\r\n        const char gSubMenu_RX_TX[][12] =//6\r\n#endif\r\n        {\r\n//                \"OFF\",\r\n//                \"TX\",\r\n//                \"RX\",\r\n//                \"TX/RX\"\r\n                关闭,\r\n                发送时,\r\n                接收时,\r\n                发送接收时\r\n        };\r\n\r\n#ifdef ENABLE_AM_FIX_TEST1\r\nconst char gSubMenu_AM_fix_test1[][8] =\r\n{\r\n    \"LNA-S 0\",\r\n    \"LNA-S 1\",\r\n    \"LNA-S 2\",\r\n    \"LNA-S 3\"\r\n};\r\n#endif\r\n\r\n\r\nconst char gSubMenu_BATTYP[][8] =\r\n        {\r\n                \"1600mAh\",\r\n                \"2200mAh\"\r\n        };\r\n\r\nconst char gSubMenu_SCRAMBLER[][7] =\r\n        {\r\n//                \"OFF\",\r\n                关闭,\r\n\r\n                \"2600Hz\",\r\n                \"2700Hz\",\r\n                \"2800Hz\",\r\n                \"2900Hz\",\r\n                \"3000Hz\",\r\n                \"3100Hz\",\r\n                \"3200Hz\",\r\n                \"3300Hz\",\r\n                \"3400Hz\",\r\n                \"3500Hz\"\r\n        };\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\nconst t_sidefunction SIDEFUNCTIONS[] =\r\n        {\r\n               {关闭, ACTION_OPT_NONE},\r\n#ifdef ENABLE_FLASHLIGHT\r\n               {手电, ACTION_OPT_FLASHLIGHT},\r\n#endif\r\n               {切换发射功率, ACTION_OPT_POWER},\r\n               {监听, ACTION_OPT_MONITOR},\r\n               {扫描, ACTION_OPT_SCAN},\r\n#ifdef ENABLE_VOX\r\n               {声控发射,\t\t\t\tACTION_OPT_VOX},\r\n#endif\r\n#ifdef ENABLE_ALARM\r\n                {\"ALARM\",\t\t\tACTION_OPT_ALARM},\r\n#endif\r\n#ifdef ENABLE_FMRADIO\r\n               {FM收音机,\t\tACTION_OPT_FM},\r\n#endif\r\n#ifdef ENABLE_TX1750\r\n                {\"1750HZ\",\t\t\tACTION_OPT_1750},\r\n#endif\r\n               {锁定按键, ACTION_OPT_KEYLOCK},\r\n               {切换信道, ACTION_OPT_A_B},\r\n               {切换信道模式, ACTION_OPT_VFO_MR},\r\n               {切换调制模式, ACTION_OPT_SWITCH_DEMODUL},\r\n               {DTMF解码, ACTION_OPT_D_DCD},\r\n               {切换宽窄带, ACTION_OPT_WIDTH},\r\n#ifdef ENABLE_SIDEFUNCTIONS_SEND\r\n               {主信道发射, ACTION_OPT_SEND_CURRENT},\r\n               {副信道发射, ACTION_OPT_SEND_OTHER},\r\n#endif\r\n#ifdef ENABLE_BLMIN_TMP_OFF\r\n                {\"BLMIN\\nTMP OFF\",  ACTION_OPT_BLMIN_TMP_OFF}, \t\t//BackLight Minimum Temporay OFF\r\n#endif\r\n        };\r\nconst t_sidefunction *gSubMenu_SIDEFUNCTIONS = SIDEFUNCTIONS;\r\nconst uint8_t gSubMenu_SIDEFUNCTIONS_size = ARRAY_SIZE(SIDEFUNCTIONS);\r\n#endif\r\n\r\nbool gIsInSubMenu;\r\nuint8_t gMenuCursor;\r\n\r\nint UI_MENU_GetCurrentMenuId() {\r\n\r\n    if (gMenuCursor < ARRAY_SIZE(MenuList))\r\n        return MenuList[gMenuCursor].menu_id;\r\n    else\r\n        return MenuList[ARRAY_SIZE(MenuList) - 1].menu_id;\r\n}\r\n\r\nuint8_t UI_MENU_GetMenuIdx(uint8_t id) {\r\n    for (uint8_t i = 0; i < ARRAY_SIZE(MenuList); i++)\r\n        if (MenuList[i].menu_id == id)\r\n            return i;\r\n    return 0;\r\n}\r\n\r\nint32_t gSubMenuSelection;\r\n\r\n// edit box\r\nchar edit_original[17]; // a copy of the text before editing so that we can easily test for changes/difference\r\nchar edit[17];\r\nint edit_index;\r\n\r\n\r\nvoid UI_DisplayMenu(void) {\r\n    const unsigned int menu_list_width = 6; // max no. of characters on the menu list (left side)\r\n    const unsigned int menu_item_x1 = (8 * menu_list_width);//+ 2;\r\n    const unsigned int menu_item_x2 = LCD_WIDTH - 1;\r\n    unsigned int i;\r\n    char String[64];  // bigger cuz we can now do multi-line in one string (use '\\n' char)\r\n#ifdef ENABLE_DTMF_CALLING\r\n    char               Contact[16];\r\n#endif\r\n\r\n    // clear the screen buffer\r\n    UI_DisplayClear();\r\n\r\n#if 1\r\n    // original menu layout\r\n\r\n\r\n\r\n    // invert the current menu list item pixels反转当前菜单项的像素值 ：\r\n\r\n\r\n    // draw vertical separating dotted line绘制垂直分隔的点线 ：\r\n//    for (i = 0; i < 7; i++)\r\n//        gFrameBuffer[i][(8 * menu_list_width) + 1] = 0xAA;\r\n\r\n\r\n    // draw the little sub-menu triangle marker绘制子菜单三角标志：\r\n    //const void *BITMAP_CurrentIndicator = BITMAP_MARKER;\r\n\r\n    if (gIsInSubMenu)\r\n        memmove(gFrameBuffer[2] + 41, BITMAP_VFO_Default, sizeof(BITMAP_VFO_Default));\r\n#ifndef ENABLE_MDC1200\r\n    uint8_t add = 1;\r\n\r\n    if (gMenuCursor + 1 >= 26)\r\n        add = 0;\r\n\r\n    sprintf(String, \"%2u/%u\", add + gMenuCursor, gMenuListCount - 1);\r\n\r\n#else\r\n    sprintf(String, \"%2u/%u\", 1 + gMenuCursor, gMenuListCount);\r\n#endif\r\n\r\n#ifdef ENABLE_PINYIN //拼音取消显示\r\n    const bool isInPinyin = UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME && gIsInSubMenu && edit_index >= 0;\r\n    if (!isInPinyin)\r\n#endif\r\n    UI_PrintStringSmall(String, 2, 0, 6);\r\n#ifdef ENABLE_PINYIN//拼音取消显示\r\n    if (!isInPinyin)\r\n#endif\r\n\r\n\r\n#ifdef ENABLE_ENGLISH\r\n    {\r\n    uint8_t size_menu = strlen(MenuList[gMenuCursor].name)*7;\r\n    UI_PrintStringSmall(MenuList[gMenuCursor].name, size_menu < 48 ? (48 - size_menu) / 2 : 0, 0, 0);\r\n    }\r\n#else\r\n    {\r\n        UI_ShowChineseMenu();\r\n    }\r\n#endif\r\n\r\n#else\r\n    {\t// new menu layout .. experimental & unfinished\r\n\r\n        const int menu_index = gMenuCursor;  // current selected menu item\r\n        i = 1;\r\n\r\n        if (!gIsInSubMenu)\r\n        {\r\n            while (i < 2)\r\n            {\t// leading menu items - small text\r\n                const int k = menu_index + i - 2;\r\n                if (k < 0)\r\n                    UI_PrintStringSmall(MenuList[gMenuListCount + k].name, 0, 0, i);  // wrap-a-round\r\n                else\r\n                if (k >= 0 && k < (int)gMenuListCount)\r\n                    UI_PrintStringSmall(MenuList[k].name, 0, 0, i);\r\n                i++;\r\n            }\r\n\r\n            // current menu item - keep big n fat\r\n            if (menu_index >= 0 && menu_index < (int)gMenuListCount)\r\n                UI_PrintStringSmall(MenuList[menu_index].name, 0, 0, 2);\r\n            i++;\r\n\r\n            while (i < 4)\r\n            {\t// trailing menu item - small text\r\n                const int k = menu_index + i - 2;\r\n                if (k >= 0 && k < (int)gMenuListCount)\r\n                    UI_PrintStringSmall(MenuList[k].name, 0, 0, 1 + i);\r\n                else\r\n                if (k >= (int)gMenuListCount)\r\n                    UI_PrintStringSmall(MenuList[gMenuListCount - k].name, 0, 0, 1 + i);  // wrap-a-round\r\n                i++;\r\n            }\r\n\r\n            // draw the menu index number/count\r\n            sprintf(String, \"%2u.%u\", 1 + gMenuCursor, gMenuListCount);\r\n            UI_PrintStringSmall(String, 2, 0, 6);\r\n        }\r\n        else\r\n        if (menu_index >= 0 && menu_index < (int)gMenuListCount)\r\n        {\t// current menu item\r\n\r\n            UI_PrintStringSmall(MenuList[menu_index].name, 0, 0, 0);\r\n//\t\t\tUI_PrintStringSmall(String, 0, 0, 0);\r\n        }\r\n    }\r\n#endif\r\n\r\n    // **************\r\n\r\n    memset(String, 0, sizeof(String));\r\n\r\n    bool already_printed = false;\r\n/* Brightness is set to max in some entries of this menu. Return it to the configured brightness\r\n\t   level the \"next\" time we enter here.I.e., when we move from one menu to another.\r\n\t   It also has to be set back to max when pressing the Exit key. */\r\n\r\n    BACKLIGHT_TurnOn();\r\n    switch (UI_MENU_GetCurrentMenuId()) {\r\n        case MENU_SQL:\r\n            sprintf(String, \"%d\", gSubMenuSelection);\r\n            break;\r\n\r\n        case MENU_MIC: {    // display the mic gain in actual dB rather than just an index number\r\n            const uint8_t mic = gMicGain_dB2[gSubMenuSelection];\r\n            sprintf(String, \"+%u.%01udB\", mic / 2, mic % 2);\r\n        }\r\n            break;\r\n\r\n//#ifdef ENABLE_AUDIO_BAR\r\n//            case MENU_MIC_BAR:\r\n//                strcpy(String, gSubMenu_OFF_ON[gSubMenuSelection]);\r\n//                break;\r\n//#endif\r\n\r\n        case MENU_STEP: {\r\n            uint16_t step = gStepFrequencyTable[FREQUENCY_GetStepIdxFromSortedIdx(gSubMenuSelection)];\r\n            sprintf(String, \"%d.%02ukHz\", step / 100, step % 100);\r\n            break;\r\n        }\r\n\r\n//        case MENU_TXP:\r\n//            strncpy(String, gSubMenu_TXP[gSubMenuSelection], sizeof(gSubMenu_TXP[gSubMenuSelection]));\r\n//            String[sizeof(gSubMenu_TXP[gSubMenuSelection])] = '\\0';\r\n//\r\n//\r\n//            break;\r\n\r\n        case MENU_R_DCS:\r\n        case MENU_T_DCS:\r\n            if (gSubMenuSelection == 0)\r\n                //translate\r\n#ifdef test\r\n                strcpy(String, \"OFF\");\r\n\r\n#else\r\n                strcpy(String, 关闭);\r\n\r\n#endif\r\n\r\n\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n            else if (gSubMenuSelection < 105)\r\n                sprintf(String, \"D%03oN\", DCS_Options[gSubMenuSelection - 1]);\r\n            else\r\n                sprintf(String, \"D%03oI\", DCS_Options[gSubMenuSelection - 105]);\r\n#else\r\n\r\n            else if (gSubMenuSelection < 105)\r\n                {\r\n                  uint8_t read_tmp[2];\r\n         EEPROM_ReadBuffer(0x02C64+(gSubMenuSelection - 1)*2, read_tmp, 2);\r\n         uint16_t DCS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\n             sprintf(String, \"D%03oN\", DCS_Options_read);\r\n             }\r\n         else{\r\n               uint8_t read_tmp[2];\r\n         EEPROM_ReadBuffer(0x02C64+(gSubMenuSelection - 105)*2, read_tmp, 2);\r\n         uint16_t DCS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\n             sprintf(String, \"D%03oI\",DCS_Options_read);\r\n             }\r\n\r\n#endif\r\n\r\n            break;\r\n\r\n        case MENU_R_CTCS:\r\n        case MENU_T_CTCS: {\r\n            if (gSubMenuSelection == 0)\r\n                // translate\r\n#ifdef test\r\n                strcpy(String, \"OFF\");\r\n\r\n#else\r\n                //关闭\r\n                strcpy(String, 关闭);\r\n\r\n#endif\r\n\r\n            else {\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n                sprintf(String, \"%u.%uHz\", CTCSS_Options[gSubMenuSelection - 1] / 10,\r\n                        CTCSS_Options[gSubMenuSelection - 1] % 10);\r\n#else\r\n                uint8_t read_tmp[2];\r\n            EEPROM_ReadBuffer(0x02C00+(gSubMenuSelection - 1)*2, read_tmp, 2);\r\n            uint16_t CTCSS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\n            sprintf(String, \"%u.%uHz\", CTCSS_Options_read / 10,CTCSS_Options_read % 10);\r\n\r\n#endif\r\n            }\r\n\r\n            break;\r\n        }\r\n\r\n        case MENU_SFT_D:\r\n            strncpy(String, gSubMenu_SFT_D[gSubMenuSelection], sizeof(gSubMenu_SFT_D[gSubMenuSelection]));\r\n            String[sizeof(gSubMenu_SFT_D[gSubMenuSelection])] = '\\0';\r\n            break;\r\n\r\n        case MENU_OFFSET:\r\n            if (!gIsInSubMenu || gInputBoxIndex == 0) {\r\n                sprintf(String, \"%3d.%05u\", gSubMenuSelection / 100000, abs(gSubMenuSelection) % 100000);\r\n                UI_PrintStringSmall(String, menu_item_x1, menu_item_x2, 2);\r\n            } else {\r\n                const char *ascii = INPUTBOX_GetAscii();\r\n                sprintf(String, \"%.3s.%.3s  \", ascii, ascii + 3);\r\n                UI_PrintStringSmall(String, menu_item_x1, menu_item_x2, 2);\r\n            }\r\n\r\n            UI_PrintStringSmall(\"MHz\", menu_item_x1, menu_item_x2, 4);\r\n\r\n            already_printed = true;\r\n            break;\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n            case MENU_W_N:\r\n\r\n                strcpy(String, gSubMenu_W_N[gSubMenuSelection]);\r\n                break;\r\n#endif\r\n\r\n        case MENU_SCR:\r\n            strcpy(String, gSubMenu_SCRAMBLER[gSubMenuSelection]);\r\n\r\n#if 1\r\n            //  if (gSubMenuSelection > 0 && gSetting_ScrambleEnable)\r\n            if (gSubMenuSelection > 0)\r\n                BK4819_EnableScramble(gSubMenuSelection - 1);\r\n            else\r\n                BK4819_DisableScramble();\r\n#endif\r\n            break;\r\n\r\n\r\n        case MENU_ABR:\r\n            strcpy(String, gSubMenu_BACKLIGHT[gSubMenuSelection]);\r\n\r\n\r\n//            BACKLIGHT_SetBrightness(-1);\r\n            break;\r\n\r\n            // case MENU_ABR_MIN:\r\n        case MENU_ABR_MAX:\r\n            sprintf(String, \"%d\", gSubMenuSelection);\r\n            if (gIsInSubMenu)\r\n                BACKLIGHT_SetBrightness(gSubMenuSelection);\r\n//            else\r\n//                BACKLIGHT_SetBrightness(-1);\r\n            break;\r\n\r\n//        case MENU_AM:\r\n//            strcpy(String, gModulationStr[gSubMenuSelection]);\r\n//\r\n//            break;\r\n\r\n#ifdef ENABLE_AM_FIX_TEST1\r\n            case MENU_AM_FIX_TEST1:\r\n                strcpy(String, gSubMenu_AM_fix_test1[gSubMenuSelection]);\r\n//\t\t\t\tgSetting_AM_fix = gSubMenuSelection;\r\n                break;\r\n#endif\r\n\r\n\r\n        case MENU_COMPAND:\r\n            strcpy(String, gSubMenu_RX_TX[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n#ifdef ENABLE_AM_FIX\r\n            case MENU_AM_FIX:\r\n#endif\r\n        case MENU_BCL:\r\n            //     case MENU_BEEP:\r\n//        case MENU_S_ADD1:\r\n//        case MENU_S_ADD2:\r\n        case MENU_STE:\r\n        case MENU_D_ST:\r\n#ifdef ENABLE_DTMF_CALLING\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n            case MENU_D_DCD:\r\n#endif\r\n#endif\r\n        case MENU_D_LIVE_DEC:\r\n#ifdef ENABLE_NOAA\r\n            case MENU_NOAA_S:\r\n#endif\r\n//        case MENU_350TX:\r\n//        case MENU_200TX:\r\n//        case MENU_500TX:\r\n//        case MENU_350EN:\r\n            strcpy(String, gSubMenu_OFF_ON[gSubMenuSelection]);\r\n\r\n            break;\r\n//        case MENU_SCREN:\r\n//            strcpy(String, gSubMenu_OFF_ON[gSubMenuSelection]);\r\n//\r\n//\r\n//            break;\r\n\r\n        case MENU_MEM_CH:\r\n        case MENU_1_CALL:\r\n        case MENU_DEL_CH: {\r\n            const bool valid = RADIO_CheckValidChannel(gSubMenuSelection, false, 1);\r\n\r\n            UI_GenerateChannelStringEx(String, valid, gSubMenuSelection);\r\n            UI_PrintStringSmall(String, menu_item_x1 - 12, menu_item_x2, 2);\r\n\r\n            if (valid && !gAskForConfirmation) {    // show the frequency so that the user knows the channels frequency\r\n                const uint32_t frequency = SETTINGS_FetchChannelFrequency(gSubMenuSelection);\r\n                sprintf(String, \"%u.%05u\", frequency / 100000, frequency % 100000);\r\n                UI_PrintStringSmall(String, menu_item_x1 - 12, menu_item_x2, 5);\r\n            }\r\n            SETTINGS_FetchChannelName(String, gSubMenuSelection);\r\n#if ENABLE_CHINESE_FULL == 4 && !defined(ENABLE_ENGLISH)\r\n            show_move_flag=1;\r\n#endif\r\n            UI_PrintStringSmall(String[0] ? String : \"--\", menu_item_x1 - 12, menu_item_x2, 3);\r\n            already_printed = true;\r\n            break;\r\n        }\r\n#ifdef ENABLE_MDC1200\r\n        case MENU_MDC_ID: {\r\n#ifdef ENABLE_MDC1200_EDIT\r\n            if (gIsInSubMenu) {\r\n                // show the channel name being edited\r\n                UI_PrintStringSmall(edit, menu_item_x1, menu_item_x2, 3);\r\n                if (edit_index < 4)\r\n                    UI_PrintStringSmall(\"^\", menu_item_x1 + (((menu_item_x2 - menu_item_x1) - (28)) + 1) / 2 + (7 * edit_index), 0, 4); // show the cursor\r\n            } else {\r\n#endif\r\n                sprintf(String, \"%04X\", gEeprom.MDC1200_ID); // %04X确保输出是4个字符长度的十六进制数\r\n                UI_PrintStringSmall(String, menu_item_x1, menu_item_x2, 3); //4\r\n\r\n#ifdef ENABLE_MDC1200_EDIT\r\n\r\n                edit_index = -1;\r\n                edit[0] = String[0];\r\n                edit[1] = String[1];\r\n                edit[2] = String[2];\r\n                edit[3] = String[3];\r\n                edit[4] = '\\0';\r\n#endif\r\n#ifdef ENABLE_MDC1200_EDIT\r\n            }\r\n#endif\r\n            already_printed = true;\r\n            break;\r\n        }\r\n#endif\r\n        case MENU_MEM_NAME: { //输入法显示\r\n//ok\r\n\r\n\r\n            const bool valid = RADIO_CheckValidChannel(gSubMenuSelection, false, 1);\r\n            UI_GenerateChannelStringEx(String, valid, gSubMenuSelection);\r\n            UI_PrintStringSmall(String, menu_item_x1 - 12, menu_item_x2, 2);\r\n\r\n            if (valid) {\r\n                const uint32_t frequency = SETTINGS_FetchChannelFrequency(gSubMenuSelection);\r\n                //bug way\r\n                char tmp_name[17] = {0};\r\n                SETTINGS_FetchChannelName(tmp_name, gSubMenuSelection);\r\n\r\n                if (!gIsInSubMenu)\r\n                    edit_index = -1;\r\n                if (edit_index < 0) {    // show the channel name\r\n                    SETTINGS_FetchChannelName(String, gSubMenuSelection);\r\n                    char *pPrintStr = String[0] ? String : \"--\";\r\n#if ENABLE_CHINESE_FULL == 4 && !defined(ENABLE_ENGLISH)\r\n                    show_move_flag=1;\r\n#endif\r\n                    UI_PrintStringSmall(pPrintStr, menu_item_x1 - 12, menu_item_x2, 3);\r\n\r\n                }\r\n\r\n//\r\n#if ENABLE_CHINESE_FULL == 4 && !defined(ENABLE_PINYIN) && !defined(ENABLE_ENGLISH)\r\n\r\n                else if (CHINESE_JUDGE(tmp_name, strlen(tmp_name))) {\r\n                    edit_index = -1;\r\n                }else if (!CHINESE_JUDGE(tmp_name, strlen(tmp_name))) {    // show the channel name being edited\r\n#else\r\n                else {\r\n#endif\r\n\r\n\r\n#if ENABLE_CHINESE_FULL == 4 && !defined(ENABLE_ENGLISH)\r\n                    show_move_flag=1;\r\n#endif\r\n                    UI_PrintStringSmall(edit, menu_item_x1 - 12, menu_item_x2, 3);\r\n\r\n                    if (edit_index < MAX_EDIT_INDEX) {\r\n//#if ENABLE_CHINESE_FULL == 4\r\n//                        show_move_flag=1;\r\n//#endif\r\n\r\n#ifdef ENABLE_PINYIN\r\n                        uint8_t cnt_chn = 0;\r\n                        uint8_t sum_pxl = 0;\r\n\r\n                        for (int j = 0; j < MAX_EDIT_INDEX; ++j) {\r\n                            if (edit[j] >= 0xb0 && j != MAX_EDIT_INDEX - 1) {\r\n                                if (j < edit_index) {\r\n                                    sum_pxl += 13;\r\n                                }\r\n                                edit_chn[j] = 1;\r\n                                j++;\r\n                                edit_chn[j] = 2;\r\n                                cnt_chn++;\r\n                            } else {\r\n                                if (j < edit_index) {\r\n                                    sum_pxl += 7;\r\n                                }\r\n                                edit_chn[j] = 0;\r\n                            }\r\n                        }\r\n\r\n                        uint8_t add_point = 3 << edit_chn[edit_index];\r\n\r\n                        uint8_t pointY = menu_item_x1 - 12 + sum_pxl +\r\n                                        (((menu_item_x2 - menu_item_x1 + 12) -\r\n                                          (7 * (MAX_EDIT_INDEX - 2 * cnt_chn) + 13 * cnt_chn)) + 1) / 2 + add_point;\r\n\r\n                        gFrameBuffer[4][pointY] |= 3 << 5;\r\n                        gFrameBuffer[4][pointY + 1] |= 3 << 5;\r\n#else\r\n\r\n                        gFrameBuffer[4][menu_item_x1 - 12 + 7 * edit_index +\r\n                                        (((menu_item_x2 - menu_item_x1 + 12) - (7 * MAX_EDIT_INDEX)) + 1) / 2 + 3] |=\r\n                                3 << 6;\r\n                        gFrameBuffer[4][menu_item_x1 - 12 + 7 * edit_index +\r\n                                        (((menu_item_x2 - menu_item_x1 + 12) - (7 * MAX_EDIT_INDEX)) + 1) / 2 + 4] |=\r\n                                3 << 6;\r\n\r\n#endif\r\n\r\n#ifdef ENABLE_PINYIN //拼音显示\r\n                        //OK\r\n                        if (INPUT_MODE == 0)memcpy(&gFrameBuffer[3][0], BITMAP_CN, 7);\r\n                        else if (INPUT_MODE == 1) UI_PrintStringSmall(\"A\", 0, 0, 3);\r\n                        else if (INPUT_MODE == 2) UI_PrintStringSmall(\"1\", 0, 0, 3);\r\n                        else if (INPUT_MODE == 3) UI_PrintStringSmall(\"*\", 0, 0, 3);\r\n                        if (INPUT_MODE == 0) {\r\n                            sprintf(String, \"%06d\", PINYIN_CODE);\r\n                            GUI_DisplaySmallest(String, 0, 18, 0, 1);\r\n                            uint8_t tmp[12];\r\n\r\n\r\n                            if (INPUT_STAGE >= 1)//显示拼音\r\n                            {\r\n                                uint8_t num = (PINYIN_NUM_SELECT) / 3;\r\n                                if ((PINYIN_NOW_NUM + 2) / 3 > 1 + num)memcpy(&gFrameBuffer[1][123], BITMAP_ARRAY_DOWN, 5);\r\n                                if (num)memcpy(&gFrameBuffer[0][123], BITMAP_ARRAY_UP, 5);\r\n\r\n                                if (PINYIN_SEARCH_MODE == 1)//准确的组合\r\n                                {\r\n\r\n\r\n\r\n//OK\r\n                                    //目前有多少个拼音\r\n                                    uint8_t HAVE_PINYIN = PINYIN_NOW_NUM - num * 3 > 3 ? 3 : PINYIN_NOW_NUM - num * 3;\r\n\r\n//OK\r\n//                                    show_uint32(PINYIN_NOW_NUM,0);\r\n//                                    sprintf(String,\"%d\",PINYIN_NUM_SELECT);\r\n//                                    UI_PrintStringSmall(String, 0, 0, 4);\r\n//                                    show_uint32(PINYIN_NOW_NUM,1);\r\n//                                    show_uint32(HAVE_PINYIN,1);\r\n                                    for (int j = 0; j < HAVE_PINYIN; ++j) {\r\n                                        EEPROM_ReadBuffer(\r\n                                                PINYIN_NOW_INDEX * 128 + 0X20000 + 16 + num * 3 * 16 +\r\n                                                j * 16, tmp, 6);\r\n                                        memcpy(&String[6 * j], tmp, 6);//0 1 2 3 4 5\r\n                                    }\r\n//#include \"ui/menu.h\"\r\n//#include \"ui/helper.h\"\r\n//\r\n//                                    if (PINYIN_CODE == 200000 && test_flag) {\r\n//                                        show_uint32(edit_index, 0);\r\n//                                        show_uint32(gIsInSubMenu, 1);\r\n//                                        show_uint32(1, 2);\r\n//                                        while (1);\r\n//                                    }\r\n                                    //NOT OK\r\n                                    String[6 * HAVE_PINYIN] = 0;\r\n                                    UI_PrintStringSmall(String, 0, 0, 0);\r\n//NOT OK\r\n\r\n                                }\r\n                            }\r\n                            if (INPUT_STAGE == 2) {\r\n\r\n                                if (PINYIN_SEARCH_MODE == 1)//准确的组合\r\n                                {\r\n                                    memcpy(&gFrameBuffer[1][(PINYIN_NUM_SELECT % 3) * 7 * 6], BITMAP_ARRAY_UP, 5);\r\n\r\n                                    uint8_t SHOW_NUM =\r\n                                            CHN_NOW_NUM - CHN_NOW_PAGE * 6 > 6 ? 6 : CHN_NOW_NUM - CHN_NOW_PAGE * 6;\r\n                                    EEPROM_ReadBuffer(CHN_NOW_ADD + CHN_NOW_PAGE * 6 * 2, tmp, SHOW_NUM * 2);\r\n//                                    show_uint32(PINYIN_NOW_INDEX * 128 + 0X20000 + 16 + PINYIN_NUM_SELECT * 16 + 6, 5);\r\n                                    for (int j = 0; j < SHOW_NUM; ++j) {\r\n                                        String[j * 3] = '0' + j + 1;\r\n                                        String[j * 3 + 1] = tmp[j * 2];\r\n                                        String[j * 3 + 2] = tmp[j * 2 + 1];\r\n                                    }\r\n                                    String[SHOW_NUM * 3] = 0;\r\n                                    show_move_flag = 1;\r\n\r\n                                    UI_PrintStringSmall(String, 0, 0, 5);\r\n                                    if (CHN_NOW_PAGE) memcpy(&gFrameBuffer[5][123], BITMAP_ARRAY_UP, 5);\r\n                                    if ((CHN_NOW_PAGE + 1) * 6 < CHN_NOW_NUM)\r\n                                        memcpy(&gFrameBuffer[6][123], BITMAP_ARRAY_DOWN, 5);\r\n                                }\r\n                            }\r\n//NOT OK\r\n\r\n\r\n                        } else if (INPUT_MODE == 1) {\r\n                            if (INPUT_STAGE == 1) {\r\n                                char tmp[22] = {0};\r\n                                if (num_size[INPUT_SELECT - 2] == 3) {\r\n                                    sprintf(tmp, \"1.%c 2.%c 3.%c\", num_excel[INPUT_SELECT - 2][0],\r\n                                            num_excel[INPUT_SELECT - 2][1], num_excel[INPUT_SELECT - 2][2]);\r\n                                    UI_PrintStringSmall(tmp, 0, 127, 0);\r\n                                    tmp[0] = '4', tmp[4] = '5', tmp[8] = '6';//flash?\r\n                                    tmp[2] -= 32, tmp[6] -= 32, tmp[10] -= 32;\r\n\r\n                                } else {\r\n                                    sprintf(tmp, \"1.%c 2.%c 3.%c 4.%c\", num_excel[INPUT_SELECT - 2][0],\r\n                                            num_excel[INPUT_SELECT - 2][1], num_excel[INPUT_SELECT - 2][2],\r\n                                            num_excel[INPUT_SELECT - 2][3]);\r\n                                    UI_PrintStringSmall(tmp, 0, 127, 0);\r\n\r\n                                    tmp[0] ='5', tmp[4] = '6', tmp[8] = '7', tmp[12] = '8';\r\n                                    tmp[2] -= 32, tmp[6] -= 32, tmp[10] -= 32, tmp[14] -= 32;\r\n                                }\r\n                                UI_PrintStringSmall(tmp, 0, 127, 1);\r\n\r\n                            }\r\n                        }\r\n#endif\r\n\r\n                    }\r\n                }\r\n\r\n//NOT OK\r\n//                sprintf(String, \"%d\", edit_index);\r\n//                UI_PrintStringSmall(String, 0, 0, 1);\r\n//                sprintf(String, \"%d\", gIsInSubMenu);\r\n//                UI_PrintStringSmall(String, 20, 0, 1);\r\n//\r\n//                sprintf(String,\"%d\",edit[2]);\r\n//                UI_PrintStringSmall(String, 0, 0, 3);\r\n\r\n\r\n                if (!gAskForConfirmation) {    // show the frequency so that the user knows the channels frequency\r\n                    sprintf(String, \"%u.%05u\", frequency / 100000, frequency % 100000);\r\n#ifdef ENABLE_PINYIN\r\n\r\n                    if (edit_index == MAX_EDIT_INDEX - 1 && INPUT_MODE == 0)\r\n                        INPUT_MODE = 1;\r\n                    if (!(gIsInSubMenu && edit_index >= 0))\r\n\r\n#endif\r\n                    {\r\n//                        show_move_flag = 1;\r\n                        UI_PrintStringSmall(String, menu_item_x1 - 12, menu_item_x2, 5);\r\n                    }\r\n                }\r\n            }\r\n\r\n            already_printed = true;\r\n\r\n            break;\r\n        }\r\n\r\n        case MENU_SAVE:\r\n            strcpy(String, gSubMenu_SAVE[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n        case MENU_TDR:\r\n            strcpy(String, gSubMenu_RXMode[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n        case MENU_TOT:\r\n            strcpy(String, gSubMenu_TOT[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n#ifdef ENABLE_VOICE\r\n            case MENU_VOICE:\r\n                strcpy(String, gSubMenu_VOICE[gSubMenuSelection]);\r\n                break;\r\n#endif\r\n\r\n        case MENU_SC_REV:\r\n\r\n\r\n            strcpy(String, gSubMenu_SC_REV[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n        case MENU_MDF:\r\n\r\n\r\n            strcpy(String, gSubMenu_MDF[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n        case MENU_RP_STE:\r\n            if (gSubMenuSelection == 0)\r\n//translate\r\n#ifdef test\r\n                strcpy(String, \"OFF\");\r\n\r\n#else\r\n                //关闭\r\n                strcpy(String, 关闭);\r\n\r\n#endif\r\n\r\n\r\n            else\r\n                sprintf(String, \"%d*100ms\", gSubMenuSelection);\r\n            break;\r\n\r\n        case MENU_S_LIST:\r\n            if (gSubMenuSelection < 2)\r\n\r\n                //translate\r\n\r\n#ifdef test\r\n                sprintf(String, \"list %u\", 1 + gSubMenuSelection);\r\n\r\n#else  //！！列表\r\n                sprintf(String, 列表\" %u\", 1 + gSubMenuSelection);\r\n\r\n#endif\r\n\r\n            else\r\n\r\n#ifdef test\r\n                strcpy(String, \"ALL\");\r\n\r\n#else\r\n                //全部\r\n                strcpy(String, 全部);\r\n\r\n#endif\r\n            break;\r\n\r\n#ifdef ENABLE_ALARM\r\n            case MENU_AL_MOD:\r\n                sprintf(String, gSubMenu_AL_MOD[gSubMenuSelection]);\r\n                break;\r\n#endif\r\n#ifdef ENABLE_DTMF_CALLING\r\n            case MENU_ANI_ID:\r\n\r\n                strcpy(String, gEeprom.ANI_DTMF_ID);\r\n                break;\r\n#endif\r\n\r\n        case MENU_UPCODE:\r\n\r\n            sprintf(String, \"%.8s\\n%.8s\", gEeprom.DTMF_UP_CODE, gEeprom.DTMF_UP_CODE + 8);\r\n            break;\r\n\r\n        case MENU_DWCODE:\r\n            sprintf(String, \"%.8s\\n%.8s\", gEeprom.DTMF_DOWN_CODE, gEeprom.DTMF_DOWN_CODE + 8);\r\n            break;\r\n#ifdef ENABLE_DTMF_CALLING\r\n            case MENU_D_RSP:\r\n                strcpy(String, gSubMenu_D_RSP[gSubMenuSelection]);\r\n\r\n\r\n                break;\r\n\r\n            case MENU_D_HOLD:\r\n                sprintf(String, \"%ds\", gSubMenuSelection);\r\n                break;\r\n#endif\r\n        case MENU_D_PRE:\r\n            sprintf(String, \"%d*10ms\", gSubMenuSelection);\r\n            break;\r\n\r\n        case MENU_PTT_ID:\r\n            strcpy(String, gSubMenu_PTT_ID[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n//        case MENU_BAT_TXT:\r\n//            strcpy(String, gSubMenu_BAT_TXT[gSubMenuSelection]);\r\n//\r\n//\r\n//            break;\r\n#ifdef ENABLE_DTMF_CALLING\r\n            case MENU_D_LIST:\r\n                gIsDtmfContactValid = DTMF_GetContact((int) gSubMenuSelection - 1, Contact);\r\n                if (!gIsDtmfContactValid)\r\n                    strcpy(String, \"NULL\");\r\n                else\r\n                    memcpy(String, Contact, 8);\r\n                break;\r\n#endif\r\n#if ENABLE_CHINESE_FULL == 4\r\n\r\n            case MENU_PONMSG:\r\n                strcpy(String, gSubMenu_PONMSG[gSubMenuSelection]);\r\n                break;\r\n#endif\r\n        case MENU_ROGER:\r\n            strcpy(String, gSubMenu_ROGER[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n//        case MENU_VOL:\r\n//            sprintf(String, \"%u.%02uV\\n%u%%\",\r\n//                    gBatteryVoltageAverage / 100, gBatteryVoltageAverage % 100,\r\n//                    BATTERY_VoltsToPercent(gBatteryVoltageAverage));\r\n//            break;\r\n\r\n        case MENU_RESET:\r\n            strcpy(String, gSubMenu_RESET[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n        case MENU_F_LOCK:\r\n//            if (!gIsInSubMenu && gUnlockAllTxConfCnt > 0&& gUnlockAllTxConfCnt < 10)\r\n//                strcpy(String, \"READ\\nMANUAL\");\r\n//\r\n//            else\r\n            strcpy(String, gSubMenu_F_LOCK[gSubMenuSelection]);\r\n\r\n\r\n            break;\r\n\r\n#ifdef ENABLE_F_CAL_MENU\r\n            case MENU_F_CALI:\r\n                {\r\n                    const uint32_t value   = 22656 + gSubMenuSelection;\r\n                    const uint32_t xtal_Hz = (0x4f0000u + value) * 5;\r\n\r\n                    writeXtalFreqCal(gSubMenuSelection, false);\r\n\r\n                    sprintf(String, \"%d\\n%u.%06u\\nMHz\",\r\n                        gSubMenuSelection,\r\n                        xtal_Hz / 1000000, xtal_Hz % 1000000);\r\n                }\r\n                break;\r\n#endif\r\n\r\n        case MENU_BATCAL: {\r\n            const uint16_t vol = (uint32_t) gBatteryVoltageAverage * gBatteryCalibration[3] / gSubMenuSelection;\r\n            sprintf(String, \"%u.%02uV\\n%u\", vol / 100, vol % 100, gSubMenuSelection);\r\n            break;\r\n        }\r\n\r\n        case MENU_BATTYP:\r\n            strcpy(String, gSubMenu_BATTYP[gSubMenuSelection]);\r\n\r\n            break;\r\n\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n            case MENU_F1SHRT:\r\n            case MENU_F1LONG:\r\n            case MENU_F2SHRT:\r\n            case MENU_F2LONG:\r\n            case MENU_MLONG:\r\n                strcpy(String, gSubMenu_SIDEFUNCTIONS[gSubMenuSelection].name);\r\n                break;\r\n#endif\r\n\r\n    }\r\n\r\n    if (!already_printed) {    // we now do multi-line text in a single string\r\n\r\n        unsigned int y;\r\n        unsigned int lines = 1;\r\n        unsigned int len = strlen(String);\r\n        bool small = false;\r\n\r\n        if (len > 0) {\r\n            // count number of lines\r\n            for (i = 0; i < len; i++) {\r\n                if (String[i] == '\\n' && i < (len - 1)) {    // found new line char\r\n                    lines += 1;\r\n                    String[i] = 0;  // null terminate the line\r\n                }\r\n            }\r\n\r\n            if (lines > 3) {    // use small text\r\n                small = true;\r\n                if (lines > 7)\r\n                    lines = 7;\r\n            }\r\n\r\n            // center vertically'ish\r\n            if (small)\r\n                y = 3 - ((lines + 0) / 2);  // untested\r\n            else\r\n                y = 2 - ((lines + 0) / 2);\r\n\r\n            // draw the text lines\r\n            for (i = 0; i < len && lines > 0; lines--) {\r\n                if (small)\r\n                    UI_PrintStringSmall(String + i, menu_item_x1, menu_item_x2, y + 1);\r\n                else\r\n                    UI_PrintStringSmall(String + i, menu_item_x1, menu_item_x2, y + 1);\r\n\r\n                // look for start of next line\r\n                while (i < len && String[i] != 0 && String[i] != '\\n')\r\n                    i++;\r\n\r\n                // hop over the null term char(s)\r\n                while (i < len && (String[i] == 0 || String[i] == '\\n'))\r\n                    i++;\r\n\r\n                y += small ? 1 : 2;\r\n            }\r\n        }\r\n    }\r\n\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_SLIST1 || UI_MENU_GetCurrentMenuId() == MENU_SLIST2) {\r\n        i = (UI_MENU_GetCurrentMenuId() == MENU_SLIST1) ? 0 : 1;\r\n\r\n        char *pPrintStr = String;\r\n\r\n        if (gSubMenuSelection < 0) {\r\n            pPrintStr = \"NULL\";\r\n        } else {\r\n            UI_GenerateChannelStringEx(String, true, gSubMenuSelection);\r\n            pPrintStr = String;\r\n        }\r\n\r\n        // channel number\r\n        UI_PrintStringSmall(pPrintStr, menu_item_x1 - 12, menu_item_x2, 2);\r\n\r\n#if ENABLE_CHINESE_FULL == 4 && !defined(ENABLE_ENGLISH)\r\n        show_move_flag=1;\r\n#endif\r\n        SETTINGS_FetchChannelName(String, gSubMenuSelection);\r\n        pPrintStr = String[0] ? String : \"--\";\r\n\r\n\r\n// channel name and scan-list\r\n        if (gSubMenuSelection < 0 || !gEeprom.SCAN_LIST_ENABLED[i]) {\r\n            UI_PrintStringSmall(pPrintStr, menu_item_x1 - 12, menu_item_x2, 4);\r\n        } else {\r\n            UI_PrintStringSmall(pPrintStr, menu_item_x1 - 12, menu_item_x2, 4);\r\n\r\n//\r\n//            if (IS_MR_CHANNEL(gEeprom.SCANLIST_PRIORITY_CH1[i])) {\r\n//                sprintf(String, \"PRI%d:%u\", 1, gEeprom.SCANLIST_PRIORITY_CH1[i] + 1);\r\n//                UI_PrintStringSmall(String, menu_item_x1 - 12, menu_item_x2, 3);\r\n//            }\r\n//\r\n//            if (IS_MR_CHANNEL(gEeprom.SCANLIST_PRIORITY_CH2[i])) {\r\n//                sprintf(String, \"PRI%d:%u\", 2, gEeprom.SCANLIST_PRIORITY_CH2[i] + 1);\r\n//                UI_PrintStringSmall(String, menu_item_x1 - 12, menu_item_x2, 6);\r\n//            }\r\n\r\n        }\r\n    }\r\n\r\n\r\n    if ((UI_MENU_GetCurrentMenuId() == MENU_R_CTCS || UI_MENU_GetCurrentMenuId() == MENU_R_DCS) && gCssBackgroundScan)\r\n        //扫描\r\n        UI_PrintStringSmall(扫描, menu_item_x1, menu_item_x2, 5);\r\n\r\n//\r\n//    if (UI_MENU_GetCurrentMenuId() == MENU_UPCODE)\r\n//        if (strlen(gEeprom.DTMF_UP_CODE) > 12)\r\n//            UI_PrintStringSmall(gEeprom.DTMF_UP_CODE + 12, menu_item_x1, menu_item_x2, 5);\r\n//\r\n//    if (UI_MENU_GetCurrentMenuId() == MENU_DWCODE)\r\n//        if (strlen(gEeprom.DTMF_DOWN_CODE) > 12)\r\n//            UI_PrintStringSmall(gEeprom.DTMF_DOWN_CODE + 12, menu_item_x1, menu_item_x2, 5);\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_D_LIST && gIsDtmfContactValid) {\r\n\r\n        Contact[11] = 0;\r\n        memcpy(&gDTMF_ID, Contact + 8, 4);\r\n        sprintf(String, \"ID:%4s\", gDTMF_ID);\r\n        UI_PrintStringSmall(String, menu_item_x1, menu_item_x2, 5);\r\n    }\r\n#endif\r\n    if (UI_MENU_GetCurrentMenuId() == MENU_R_CTCS ||\r\n        UI_MENU_GetCurrentMenuId() == MENU_T_CTCS ||\r\n        UI_MENU_GetCurrentMenuId() == MENU_R_DCS ||\r\n        UI_MENU_GetCurrentMenuId() == MENU_T_DCS\r\n#ifdef ENABLE_DTMF_CALLING\r\n        || UI_MENU_GetCurrentMenuId() == MENU_D_LIST\r\n#endif\r\n            ) {\r\n\r\n        sprintf(String, \"%2d\", gSubMenuSelection);\r\n        UI_PrintStringSmall(String, 105, 0, 1);//small\r\n    }\r\n\r\n    if ((UI_MENU_GetCurrentMenuId() == MENU_RESET ||\r\n         UI_MENU_GetCurrentMenuId() == MENU_MEM_CH ||\r\n         UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME ||\r\n         #ifdef ENABLE_MDC1200_EDIT\r\n\r\n         UI_MENU_GetCurrentMenuId() == MENU_MDC_ID ||\r\n         #endif\r\n         UI_MENU_GetCurrentMenuId() == MENU_DEL_CH) && gAskForConfirmation) {    // display confirmation\r\n        char *pPrintStr = (gAskForConfirmation == 1) ? \"SURE?\" : \"WAIT!\";\r\n        if (UI_MENU_GetCurrentMenuId() == MENU_MEM_CH || UI_MENU_GetCurrentMenuId() == MENU_MEM_NAME ||\r\n             UI_MENU_GetCurrentMenuId() == MENU_DEL_CH)\r\n            UI_PrintStringSmall(pPrintStr, menu_item_x1 - 12, menu_item_x2, 5);\r\n        else UI_PrintStringSmall(pPrintStr, menu_item_x1, menu_item_x2, 5);\r\n\r\n        gRequestSaveSettings = 1;\r\n\r\n    }\r\n\r\n    ST7565_BlitFullScreen();\r\n}\r\n\r\n//\r\n\r\n#ifndef ENABLE_ENGLISH\r\nvoid UI_ShowChineseMenu() {\r\n\r\n\r\n    uint8_t size_menu = 0;\r\n    uint8_t cnt_menu = 0;\r\n\r\n\r\n#if ENABLE_CHINESE_FULL == 4 && !defined(ENABLE_ENGLISH)\r\n    uint8_t name[15];\r\n    name[15] = 0;\r\n    EEPROM_ReadBuffer(0x028B0 + gMenuCursor * 14, name, 14);\r\n    for (cnt_menu = 0; cnt_menu < 7 && name[cnt_menu]!= 0; cnt_menu++) {\r\n        if (is_chn(/*MenuList[gMenuCursor].name[cnt_menu]*/name[cnt_menu]) != 255)//中文\r\n#else\r\n    for (cnt_menu = 0; cnt_menu < 7 && MenuList[gMenuCursor].name[cnt_menu] != 0; cnt_menu++) {\r\n        if (is_chn(MenuList[gMenuCursor].name[cnt_menu]) != 255)//中文\r\n#endif\r\n        {\r\n            size_menu += 12;\r\n#if ENABLE_CHINESE_FULL != 0\r\n            cnt_menu++;\r\n#endif\r\n        } else//英文\r\n        {\r\n            size_menu += 7;\r\n        }\r\n    }\r\n\r\n    show_move_flag = 1;\r\n\r\n#if ENABLE_CHINESE_FULL == 4\r\n\r\n    UI_PrintStringSmall((const char *)name, size_menu < 48 ? (48 - size_menu) / 2 : 0, 0, 0);\r\n#else\r\n\r\n    UI_PrintStringSmall(MenuList[gMenuCursor].name, size_menu < 48 ? (48 - size_menu) / 2 : 0, 0, 0);\r\n\r\n#endif\r\n\r\n}\r\n#endif\r\n#ifdef ENABLE_PINYIN\r\nuint8_t INPUT_SELECT = 0;//选择的按键\r\nuint8_t INPUT_MODE_LAST = 0;\r\nuint8_t INPUT_MODE = 0;//0中文 1英文 2数字、符号\r\nuint8_t INPUT_STAGE = 0;//中文：0 还没输入，不显示拼音和汉字 1输入了\r\nuint32_t PINYIN_CODE = 0;\r\nuint32_t PINYIN_CODE_INDEX = 100000;\r\nuint8_t PINYIN_SEARCH_INDEX = 0;\r\nuint8_t PINYIN_SEARCH_FOUND = 0;\r\nuint8_t PINYIN_SEARCH_NUM = 0;\r\nuint8_t PINYIN_NOW_INDEX = 0;//当前拼音组合地址\r\nuint8_t PINYIN_NOW_NUM = 0;\r\nuint8_t PINYIN_SEARCH_MODE = 0;\r\nuint8_t PINYIN_START_INDEX = 0;\r\nuint8_t PINYIN_END_INDEX = 0;\r\nuint8_t PINYIN_NOW_PAGE = 0;\r\nuint8_t PINYIN_NUM_SELECT = 0;\r\nuint32_t CHN_NOW_ADD = 0;\r\nuint8_t CHN_NOW_NUM = 0;\r\nuint8_t CHN_NOW_PAGE = 0;\r\nuint8_t edit_chn[MAX_EDIT_INDEX];\r\n//英语：0 未选字 1选字\r\n//数字：0正常模式 1按了上下的轮询模式，需要按MENU确定\r\nchar input1[22];\r\nchar input2[22];\r\nchar num_excel[8][4] = {\r\n        {'a','b','c','\\0'},\r\n        {'d','e','f','\\0'},\r\n        {'g','h','i','\\0'},\r\n        {'j','k','l','\\0'},\r\n        {'m','n','o','\\0'},\r\n        {'p','q','r','s'},\r\n        {'t','u','v','\\0'},\r\n        {'w','x','y','z'},\r\n\r\n};\r\nuint8_t num_size[8]={3,3,3,3,3,4,3,4};\r\n\r\nuint32_t formatInt(uint32_t number) {//数字转拼音编码\r\n    uint32_t formatted = number;\r\n    uint32_t length = 0;\r\n    // 计算整数的位数\r\n    while (number != 0) {\r\n        number /= 10;\r\n        length++;\r\n    }\r\n    // 如果位数不足6位，则在后面补0\r\n    if (length < 6) {\r\n        for (uint8_t i = 0; i < 6 - length; ++i) {\r\n            formatted *= 10;\r\n        }\r\n    }\r\n    return formatted;\r\n}\r\n\r\n\r\nuint32_t get_num(const char *a) {//拼音转数字\r\n    uint32_t num = 0;\r\n    uint32_t bin = 100000;\r\n    for (unsigned int j = 0; j < strlen(a); j++) {\r\n        uint32_t now_num = 0;\r\n        for (int i = 0; i < 8; ++i) {\r\n            for (int k = 0; k < num_size[i]; ++k) {\r\n                if (num_excel[i][k] == a[j]) {\r\n                    now_num = i + 2;\r\n                    goto end_loop;\r\n                }\r\n            }\r\n        }\r\n        end_loop:\r\n        num += bin * now_num;\r\n        bin /= 10;\r\n    }\r\n    return num;\r\n}\r\n\r\nbool judge_belong(uint32_t a, uint32_t b)//拼音归属判断\r\n{\r\n    for (uint32_t i = 100000; i >= 1; i /= 10) {\r\n        if (a / i == 0)break;\r\n        if (a / i != b / i)return false;\r\n        a = a - a / i * i;\r\n        b = b - b / i * i;\r\n\r\n    }\r\n    return true;\r\n}\r\n\r\nuint8_t sear_pinyin_code(uint32_t target, uint8_t *pinyin_num, uint8_t *found)//返回拼音索引0~213，以及是否找到\r\n{\r\n    int left = 0;\r\n    int right = 213;\r\n    *found = 0; // 初始设定未找到\r\n\r\n    while (left <= right) {\r\n        int mid = left + (right - left) / 2;\r\n        uint8_t tmp[5];\r\n        EEPROM_ReadBuffer(mid * 128 + 0x20000, tmp, 5);\r\n        uint32_t mid_num = tmp[0] | tmp[1] << 8 | tmp[2] << 16 | tmp[3] << 24;\r\n        *pinyin_num = tmp[4];\r\n        if (mid_num == target) {\r\n            *found = 1; // 找到了\r\n            return mid;\r\n        } else if (target < mid_num) {\r\n            right = mid - 1;\r\n        } else {\r\n            left = mid + 1;\r\n        }\r\n    }\r\n\r\n    // 找不到目标值，返回比目标值大一个的值\r\n    if (left <= 213) {\r\n        uint8_t tmp[5];\r\n        EEPROM_ReadBuffer(left * 128 + 0x20000, tmp, 5);\r\n        uint32_t left_num = tmp[0] | tmp[1] << 8 | tmp[2] << 16 | tmp[3] << 24;\r\n\r\n\r\n        if (judge_belong(target, left_num)) {\r\n            return left;\r\n        }\r\n    }\r\n    return 255;\r\n\r\n}\r\n\r\n#endif"
  },
  {
    "path": "ui/menu.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_MENU_H\r\n#define UI_MENU_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\n\r\n#include \"audio.h\"     // VOICE_ID_t\r\n#include \"settings.h\"\r\n#include \"font.h\"\r\n\r\ntypedef struct {\r\n    VOICE_ID_t voice_id;\r\n    uint8_t menu_id;\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n    const char name[7]; // 使用指针而不是固定长度数组\r\n\r\n\r\n#endif\r\n} t_menu_item;\r\n\r\nenum {\r\n    MENU_SQL = 0,\r\n    MENU_STEP,\r\n    //MENU_TXP,\r\n    MENU_R_DCS,\r\n    MENU_R_CTCS,\r\n    MENU_T_DCS,\r\n    MENU_T_CTCS,\r\n    MENU_SFT_D,\r\n    MENU_OFFSET,\r\n    MENU_TOT,\r\n    MENU_W_N,\r\n    MENU_SCR,\r\n    MENU_BCL,\r\n    MENU_MEM_CH,\r\n    MENU_DEL_CH,\r\n    MENU_MEM_NAME,\r\n    MENU_MDF,\r\n    MENU_SAVE,\r\n#ifdef ENABLE_VOX\r\n    //MENU_VOX,\r\n#endif\r\n    MENU_ABR,\r\n    //MENU_ABR_ON_TX_RX,\r\n    //MENU_ABR_MIN,\r\n    MENU_ABR_MAX,\r\n    MENU_TDR,\r\n    //MENU_BEEP,\r\n#ifdef ENABLE_VOICE\r\n    MENU_VOICE,\r\n#endif\r\n    MENU_SC_REV,\r\n    //MENU_AUTOLK,\r\n    MENU_S_ADD1,\r\n    MENU_S_ADD2,\r\n    MENU_STE,\r\n    MENU_RP_STE,\r\n    MENU_MIC,\r\n//#ifdef ENABLE_AUDIO_BAR\r\n    //MENU_MIC_BAR,\r\n//#endif\r\n    MENU_COMPAND,\r\n    MENU_1_CALL,\r\n    MENU_S_LIST,\r\n    MENU_SLIST1,\r\n    MENU_SLIST2,\r\n#ifdef ENABLE_ALARM\r\n    MENU_AL_MOD,\r\n#endif\r\n#ifdef ENABLE_DTMF_CALLING\r\n    MENU_ANI_ID,\r\n#endif\r\n\r\n    MENU_MDC_ID,\r\n\r\n\r\n    MENU_UPCODE,\r\n    MENU_DWCODE,\r\n    MENU_PTT_ID,\r\n    MENU_D_ST,\r\n#ifdef ENABLE_DTMF_CALLING\r\n    MENU_D_RSP,\r\n    MENU_D_HOLD,\r\n#endif\r\n\r\n    MENU_D_PRE,\r\n#ifdef ENABLE_DTMF_CALLING\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n\r\n    MENU_D_DCD,\r\n#endif\r\n    MENU_D_LIST,\r\n#endif\r\n\r\n    MENU_D_LIVE_DEC,\r\n#if ENABLE_CHINESE_FULL == 4\r\n\r\n    MENU_PONMSG,\r\n#endif\r\n\r\n    MENU_ROGER,\r\n    // MENU_VOL,\r\n    //MENU_BAT_TXT,\r\n    //MENU_AM,\r\n#ifdef ENABLE_AM_FIX\r\n    MENU_AM_FIX,\r\n#endif\r\n#ifdef ENABLE_AM_FIX_TEST1\r\n    MENU_AM_FIX_TEST1,\r\n#endif\r\n#ifdef ENABLE_NOAA\r\n    MENU_NOAA_S,\r\n#endif\r\n    MENU_RESET,\r\n    MENU_F_LOCK,\r\n//    MENU_200TX,\r\n//    MENU_350TX,\r\n//    MENU_500TX,\r\n//    MENU_350EN,\r\n    //  MENU_SCREN,\r\n#ifdef ENABLE_F_CAL_MENU\r\n    MENU_F_CALI,  // reference xtal calibration\r\n#endif\r\n    MENU_BATCAL,  // battery voltage calibration\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n    MENU_F1SHRT,\r\n    MENU_F1LONG,\r\n    MENU_F2SHRT,\r\n    MENU_F2LONG,\r\n    MENU_MLONG,\r\n#endif\r\n    MENU_BATTYP\r\n};\r\n\r\nextern const t_menu_item MenuList[];\r\n#if ENABLE_CHINESE_FULL == 4\r\n\r\nextern const char gSubMenu_PONMSG[3][5];\r\n#endif\r\n\r\n//extern const char        gSubMenu_TXP[3][2];//5\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n#ifdef ENABLE_ENGLISH\r\nextern const char        gSubMenu_SFT_D[3][4];//3\r\n#else\r\nextern const char        gSubMenu_SFT_D[3][10];//3\r\n#endif\r\n#else\r\n\r\nextern const char gSubMenu_SFT_D[3][16];//3\r\n#endif\r\n#ifdef ENABLE_CUSTOM_SIDEFUNCTIONS\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n#ifdef ENABLE_ENGLISH\r\nextern const char        gSubMenu_W_N[2][7];//7\r\n#else\r\nextern const char        gSubMenu_W_N[2][3];//7\r\n#endif\r\n#else\r\nextern const char gSubMenu_W_N[2][5];//7\r\n#endif\r\n#endif\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n#ifdef ENABLE_ENGLISH\r\nextern const char        gSubMenu_OFF_ON[2][4];//4\r\n#else\r\nextern const char        gSubMenu_OFF_ON[2][3];//4\r\n#endif\r\n#else\r\nextern const char gSubMenu_OFF_ON[2][5];//4\r\n#endif\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\nextern const char        gSubMenu_SAVE[5][4];//4\r\n#else\r\nextern const char gSubMenu_SAVE[5][6];//4\r\n#endif\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\nextern const char        gSubMenu_TOT[11][7];//7\r\n#else\r\nextern const char gSubMenu_TOT[11][6];//7\r\n#endif\r\nextern const char *const gSubMenu_RXMode[4];\r\n\r\n#ifdef ENABLE_VOICE\r\nextern const char    gSubMenu_VOICE[3][4];\r\n#endif\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n\r\n#ifdef ENABLE_ENGLISH\r\nextern const char        gSubMenu_SC_REV[3][8];//8\r\n#else\r\nextern const char        gSubMenu_SC_REV[3][10];//8\r\n#endif\r\n\r\n\r\n#else\r\nextern const char gSubMenu_SC_REV[3][18];//8\r\n#endif\r\nextern const char *const gSubMenu_MDF[4];\r\n#ifdef ENABLE_ALARM\r\nextern const char    gSubMenu_AL_MOD[2][5];\r\n#endif\r\n#ifdef ENABLE_DTMF_CALLING\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n#ifdef ENABLE_ENGLISH\r\nextern const char        gSubMenu_D_RSP[4][11];//11\r\n#else\r\nextern const char        gSubMenu_D_RSP[4][10];//11\r\n#endif\r\n#else\r\nextern const char gSubMenu_D_RSP[4][18];//11\r\n#endif\r\n#endif\r\n\r\nextern const char *const gSubMenu_PTT_ID[5];\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n#ifdef ENABLE_ENGLISH\r\nextern const char        gSubMenu_ROGER[6][15];\r\n#else\r\nextern const char        gSubMenu_ROGER[6][13];\r\n#endif\r\n\r\n#else\r\nextern const char gSubMenu_ROGER[6][15];\r\n#endif\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n#ifdef ENABLE_ENGLISH\r\nextern const char        gSubMenu_RESET[2][4];//4\r\n#else\r\nextern const char        gSubMenu_RESET[2][6];//4\r\n#endif\r\n\r\n#else\r\nextern const char gSubMenu_RESET[2][11];//4\r\n#endif\r\nextern const char *const gSubMenu_F_LOCK[F_LOCK_LEN];\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n\r\n#ifdef ENABLE_ENGLISH\r\nextern const char        gSubMenu_BACKLIGHT[8][7];//7\r\n#else\r\nextern const char        gSubMenu_BACKLIGHT[8][5];//7\r\n#endif\r\n#else\r\nextern const char gSubMenu_BACKLIGHT[8][6];//7\r\n#endif\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n#ifdef ENABLE_ENGLISH\r\nextern const char        gSubMenu_RX_TX[4][6];//6\r\n\r\n#else\r\nextern const char        gSubMenu_RX_TX[4][7];//6\r\n#endif\r\n\r\n#else\r\nextern const char gSubMenu_RX_TX[4][12];//6\r\n#endif\r\n#ifdef ENABLE_AM_FIX_TEST1\r\nextern const char    gSubMenu_AM_fix_test1[4][8];\r\n#endif\r\n//extern const char        gSubMenu_BAT_TXT[3][3];//8\r\nextern const char gSubMenu_BATTYP[2][8];\r\nextern const char gSubMenu_SCRAMBLER[11][7];\r\n\r\ntypedef struct {\r\n    char *name;\r\n    uint8_t id;\r\n} t_sidefunction;\r\nextern const uint8_t gSubMenu_SIDEFUNCTIONS_size;\r\nextern const t_sidefunction *gSubMenu_SIDEFUNCTIONS;\r\n//extern const t_sidefunction SIDEFUNCTIONS[];\r\n\r\nextern bool gIsInSubMenu;\r\n\r\nextern uint8_t gMenuCursor;\r\n\r\nextern int32_t gSubMenuSelection;\r\n\r\nextern char edit_original[17];\r\nextern char edit[17];\r\nextern int edit_index;\r\nextern uint8_t num_size[8];\r\n\r\nvoid UI_DisplayMenu(void);\r\n\r\nuint8_t pinyin_search(uint8_t *target, uint8_t size, uint32_t *add);\r\n\r\nuint8_t pinyin_cmp(uint8_t *a, uint8_t *b);\r\n\r\nint UI_MENU_GetCurrentMenuId();\r\n\r\nuint8_t UI_MENU_GetMenuIdx(uint8_t id);\r\n\r\nvoid UI_ShowChineseMenu(void);\r\n\r\n#ifdef ENABLE_PINYIN\r\nextern char num_excel[8][4] ;\r\nbool judge_belong(uint32_t a,uint32_t b);//拼音归属判断\r\n\r\nuint8_t sear_pinyin_code(uint32_t target,uint8_t *pinyin_num,uint8_t *found);//返回拼音索引0~213，以及是否找到\r\n\r\n\r\n\r\nextern uint8_t INPUT_MODE;//0中文 1英文 2数字、符号\r\nextern uint8_t INPUT_STAGE;//中文：0 还没输入，不显示拼音和汉字 1输入了\r\n//英语：0 未选字 1选字\r\n//数字：0正常模式 1按了上下的轮询模式，需要按MENU确定\r\n\r\nextern uint8_t INPUT_SELECT;//选择的按键\r\nextern uint8_t INPUT_MODE_LAST;\r\nextern uint32_t PINYIN_CODE;\r\nextern uint32_t PINYIN_CODE_INDEX;\r\nextern uint8_t PINYIN_SEARCH_INDEX;\r\nextern uint8_t PINYIN_SEARCH_FOUND;\r\nextern uint8_t PINYIN_SEARCH_NUM;\r\nextern uint8_t PINYIN_NOW_INDEX;//当前拼音组合地址\r\nextern uint8_t PINYIN_NOW_NUM;//当前拼音组合地址\r\nextern uint8_t PINYIN_SEARCH_MODE;\r\nextern uint8_t PINYIN_START_INDEX;\r\nextern uint8_t PINYIN_NUM_SELECT;\r\nextern uint32_t CHN_NOW_ADD;\r\nextern uint8_t CHN_NOW_NUM;\r\nextern uint8_t CHN_NOW_PAGE;\r\nextern uint8_t edit_chn[MAX_EDIT_INDEX];\r\n\r\n#endif\r\n#endif\r\n"
  },
  {
    "path": "ui/messenger.c",
    "content": "\n#ifdef ENABLE_MESSENGER\n\n#include <string.h>\n#include \"app/spectrum.h\"\n#include <string.h>\n#include \"app/messenger.h\"\n#include \"driver/st7565.h\"\n#include \"external/printf/printf.h\"\n#include \"misc.h\"\n#include \"settings.h\"\n#include \"ui/messenger.h\"\n#include \"ui/helper.h\"\n#include \"ui/inputbox.h\"\n#include \"ui/ui.h\"\n#ifdef ENABLE_DOCK\n#include \"app/uart.h\"\n#endif\n\nvoid UI_DisplayMSG(void) {\n\n\n    UI_DisplayClear();\n    UI_PrintStringSmall(\"MES\", 1, 127, 0);\n\n\n\n    uint8_t mPos = 8;\n    const uint8_t mLine = 7;\n    for (int i = 0; i < 4; ++i) {\n        GUI_DisplaySmallest(rxMessage[i], 2, mPos, false, true);\n        mPos += mLine;\n    }\n\n\nconst uint8_t *p;\n    if (keyboardType == NUMERIC) {\n        p= BITMAP_1;\n    } else if (keyboardType == UPPERCASE) {\n        p= BITMAP_TX;\n    } else {\n        p= BITMAP_t;\n    }\n    memcpy(gFrameBuffer[0], p, 6);\n\n\n    cMessage[cIndex]='_';\n    cMessage[cIndex+1]='\\0';\n\n    GUI_DisplaySmallest(cMessage, 5, 48, false, true);\n    cMessage[cIndex]='\\0';\n\n\n\n\n\n    ST7565_BlitFullScreen();\n}\n\n#endif\n"
  },
  {
    "path": "ui/messenger.h",
    "content": "\n#ifndef UI_MSG_H\n#define UI_MSG_H\n\n#ifdef ENABLE_MESSENGER\n\tvoid UI_DisplayMSG(void);\n#endif\n\n#endif\n\n"
  },
  {
    "path": "ui/scanner.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include \"chinese.h\"\r\n#include <stdbool.h>\r\n#include <string.h>\r\n#include \"app/scanner.h\"\r\n#include \"dcs.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"misc.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/scanner.h\"\r\n\r\nvoid UI_DisplayScanner(void) {\r\n    char String[16] = {0};\r\n    char *pPrintStr = String;\r\n    bool bCentered;\r\n    uint8_t Start;\r\n\r\n    UI_DisplayClear();\r\n    if (gScanSingleFrequency || (gScanCssState != SCAN_CSS_STATE_OFF && gScanCssState != SCAN_CSS_STATE_FAILED)) {\r\n//频率\r\n        sprintf(String, 频率\":%u.%05u\", gScanFrequency / 100000, gScanFrequency % 100000);\r\n\r\n        pPrintStr = String;\r\n    } else {\r\n        pPrintStr = 频率\":**.*****\";\r\n    }\r\n\r\n\r\n    UI_PrintStringSmall(pPrintStr, 2, 0, 1);\r\n\r\n    if (gScanCssState < SCAN_CSS_STATE_FOUND || !gScanUseCssResult) {\r\n        pPrintStr = 模拟亚音\":******\";\r\n    } else if (gScanCssResultType == CODE_TYPE_CONTINUOUS_TONE) {\r\n        //模拟亚音\r\n#ifdef TEST_UNDE_CTCSS\r\n\r\n        sprintf(String, 模拟亚音\":%u.%uHz\", gScanCssResultCode_all/10, gScanCssResultCode_all% 10);\r\n#else\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n        sprintf(String, 模拟亚音\":%u.%uHz\", CTCSS_Options[gScanCssResultCode] / 10,\r\n                CTCSS_Options[gScanCssResultCode] % 10);\r\n\r\n#else\r\n        uint8_t read_tmp[2];\r\n    EEPROM_ReadBuffer(0x02C00+gScanCssResultCode*2, read_tmp, 2);\r\n    uint16_t CTCSS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\n          sprintf(String, 模拟亚音\":%u.%uHz\", CTCSS_Options_read/ 10,CTCSS_Options_read % 10);\r\n\r\n\r\n#endif\r\n#endif\r\n        pPrintStr = String;\r\n    } else {\r\n//数字亚音\r\n#if ENABLE_CHINESE_FULL == 0 || defined(ENABLE_ENGLISH)\r\n        sprintf(String, 数字亚音\":D%03oN\", DCS_Options[gScanCssResultCode]);\r\n#else\r\n        uint8_t read_tmp[2];\r\n        EEPROM_ReadBuffer(0x02C64+(gScanCssResultCode)*2, read_tmp, 2);\r\n        uint16_t DCS_Options_read=read_tmp[0]|(read_tmp[1]<<8);\r\n        sprintf(String, 数字亚音\":D%03oN\",DCS_Options_read);\r\n#endif\r\n\r\n        pPrintStr = String;\r\n    }\r\n    UI_PrintStringSmall(pPrintStr, 2, 0, 3);\r\n    memset(String, 0, sizeof(String));\r\n\r\n    if (gScannerSaveState == SCAN_SAVE_CHANNEL) {\r\n        pPrintStr = 存置问;\r\n        Start = 0;\r\n        bCentered = 1;\r\n    } else {\r\n        Start = 2;\r\n        bCentered = 0;\r\n        if (gScannerSaveState == SCAN_SAVE_CHAN_SEL) {\r\n\r\n//存置\r\n            strcpy(String, 存置了);\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n\r\n            UI_GenerateChannelStringEx(String + 3, gShowChPrefix, gScanChannel);\r\n#else\r\n            UI_GenerateChannelStringEx(String + 5, gShowChPrefix, gScanChannel);\r\n\r\n#endif\r\n\r\n            pPrintStr = String;\r\n        } else if (gScanCssState < SCAN_CSS_STATE_FOUND) {\r\n\r\n            //扫描\r\n            strcpy(String, 扫描);\r\n#if ENABLE_CHINESE_FULL != 4 || defined(ENABLE_ENGLISH)\r\n            memset(String + 2, '.', (gScanProgressIndicator & 7) + 1);\r\n\r\n#else\r\n            memset(String + 4, '.', (gScanProgressIndicator & 7) + 1);\r\n\r\n#endif\r\n            pPrintStr = String;\r\n        } else if (gScanCssState == SCAN_CSS_STATE_FOUND) {\r\n            pPrintStr = 扫描\" OK.\";\r\n        } else {\r\n            pPrintStr = 扫描\" FAIL.\";\r\n        }\r\n\r\n\r\n    }\r\n    UI_PrintStringSmall(pPrintStr, Start, bCentered ? 127 : 0, 5);\r\n    ST7565_BlitFullScreen();\r\n}\r\n"
  },
  {
    "path": "ui/scanner.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_SCANNER_H\r\n#define UI_SCANNER_H\r\n\r\nvoid UI_DisplayScanner(void);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "ui/status.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#ifdef ENABLE_MESSENGER\r\n#include \"app/messenger.h\"\r\n#endif\r\n#ifdef ENABLE_DOPPLER\r\n#include \"app/doppler.h\"\r\n#endif\r\n\r\n#include <string.h>\r\n\r\n#include \"app/chFrScanner.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"app/scanner.h\"\r\n#include \"bitmaps.h\"\r\n#include \"driver/keyboard.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"functions.h\"\r\n#include \"helper/battery.h\"\r\n#include \"misc.h\"\r\n#include \"settings.h\"\r\n#include \"ui/battery.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/ui.h\"\r\n#include \"ui/status.h\"\r\n\r\nvoid UI_DisplayStatus() {\r\n    gUpdateStatus = false;\r\n    memset(gStatusLine, 0, sizeof(gStatusLine));\r\n\r\n    uint8_t *line = gStatusLine;\r\n    unsigned int x = 0;\r\n    // **************\r\n\r\n    // POWER-SAVE indicator\r\n    if (gCurrentFunction == FUNCTION_TRANSMIT) {\r\n        memcpy(line + x, BITMAP_TX, sizeof(BITMAP_TX));\r\n    } else if (FUNCTION_IsRx()) {\r\n        memcpy(line + x, BITMAP_RX, sizeof(BITMAP_RX));\r\n    } else if (gCurrentFunction == FUNCTION_POWER_SAVE) {\r\n        memcpy(line + x, BITMAP_POWERSAVE, sizeof(BITMAP_POWERSAVE));\r\n    }\r\n    x += 8;\r\n    unsigned int x1 = x;\r\n\r\n#ifdef ENABLE_NOAA\r\n    if (gIsNoaaMode) { // NOASS SCAN indicator\r\n        memcpy(line + x, BITMAP_NOAA, sizeof(BITMAP_NOAA));\r\n        x1 = x + sizeof(BITMAP_NOAA);\r\n    }\r\n    x += sizeof(BITMAP_NOAA);\r\n#endif\r\n#ifdef ENABLE_MESSENGER\r\n    if (hasNewMessage > 0) { // New Message indicator\r\n        if (hasNewMessage == 1)\r\n            memcpy(line + x+1, BITMAP_NEWMSG, sizeof(BITMAP_NEWMSG));\r\n        x1 = x + sizeof(BITMAP_NEWMSG);\r\n    }\r\n    x += sizeof(BITMAP_NEWMSG);\r\n#endif\r\n#ifdef ENABLE_DTMF_CALLING\r\n    if (gSetting_KILLED) {\r\n        memset(line + x, 0xFF, 10);\r\n        x1 = x + 10;\r\n    }\r\n    else\r\n#endif\r\n#ifdef ENABLE_FMRADIO\r\n    if (gFmRadioMode) { // FM indicator\r\n        memcpy(line + x, BITMAP_FM, sizeof(BITMAP_FM));\r\n        x1 = x + sizeof(BITMAP_FM);\r\n    }\r\n    else\r\n#endif\r\n    { // SCAN indicator\r\n        if (gScanStateDir != SCAN_OFF || SCANNER_IsScanning()) {\r\n            char *s = \"\";\r\n            if (IS_MR_CHANNEL(gNextMrChannel) && !SCANNER_IsScanning()) { // channel mode\r\n                switch (gEeprom.SCAN_LIST_DEFAULT) {\r\n                    case 0:\r\n                        s = \"1\";\r\n                        break;\r\n                    case 1:\r\n                        s = \"2\";\r\n                        break;\r\n                    case 2:\r\n                        s = \"*\";\r\n                        break;\r\n                }\r\n            } else {    // frequency mode\r\n                s = \"S\";\r\n            }\r\n            UI_PrintStringSmallBuffer(s, line + x + 1);\r\n            x1 = x + 10;\r\n        }\r\n    }\r\n    x += 10;  // font character width\r\n\r\n#ifdef ENABLE_VOICE\r\n    // VOICE indicator\r\n    if (gEeprom.VOICE_PROMPT != VOICE_PROMPT_OFF){\r\n        memcpy(line + x, BITMAP_VoicePrompt, sizeof(BITMAP_VoicePrompt));\r\n        x1 = x + sizeof(BITMAP_VoicePrompt);\r\n    }\r\n    x += sizeof(BITMAP_VoicePrompt);\r\n#endif\r\n\r\n    if (!SCANNER_IsScanning()) {\r\n        uint8_t dw = (gEeprom.DUAL_WATCH != DUAL_WATCH_OFF) + (gEeprom.CROSS_BAND_RX_TX != CROSS_BAND_OFF) * 2;\r\n        if (dw == 1 || dw == 3) { // DWR - dual watch + respond\r\n            if (gDualWatchActive)\r\n                memcpy(line + x + (dw == 1 ? 0 : 2), BITMAP_TDR1, sizeof(BITMAP_TDR1) - (dw == 1 ? 0 : 5));\r\n            else\r\n                memcpy(line + x + 3 + 1, BITMAP_TDR2, sizeof(BITMAP_TDR2));\r\n        } else if (dw == 2) { // XB - crossband\r\n            memcpy(line + x + 2, BITMAP_XB, sizeof(BITMAP_XB));\r\n        }\r\n    }\r\n    x += sizeof(BITMAP_TDR1) + 1;\r\n\r\n#ifdef ENABLE_VOX\r\n    // VOX indicator\r\n    if (gEeprom.VOX_SWITCH) {\r\n        memcpy(line + x, BITMAP_VOX, sizeof(BITMAP_VOX));\r\n        x1 = x + sizeof(BITMAP_VOX) + 1;\r\n    }\r\n    x += sizeof(BITMAP_VOX) + 1;\r\n#endif\r\n\r\n    x = MAX(x1, 61u);\r\n\r\n    // KEY-LOCK indicator\r\n    if (gEeprom.KEY_LOCK) {\r\n        memcpy(line + x, BITMAP_KeyLock, sizeof(BITMAP_KeyLock));\r\n        x += sizeof(BITMAP_KeyLock);\r\n        x1 = x;\r\n    } else if (gWasFKeyPressed) {\r\n        memcpy(line + x, BITMAP_F_Key, sizeof(BITMAP_F_Key));\r\n        x += sizeof(BITMAP_F_Key);\r\n        x1 = x;\r\n    }\r\n\r\n    {    // battery voltage or percentage\r\n        char s[8] = \"\";\r\n        unsigned int x2 = LCD_WIDTH - sizeof(BITMAP_BatteryLevel1) - 0;\r\n\r\n        if (gChargingWithTypeC)\r\n            x2 -= sizeof(BITMAP_USB_C);  // the radio is on charge\r\n\r\n//        switch (gSetting_battery_text) {\r\n//            default:\r\n//            case 0:\r\n//                break;\r\n//\r\n//            case 1:\t{\t// voltage\r\n//                const uint16_t voltage = (gBatteryVoltageAverage <= 999) ? gBatteryVoltageAverage : 999; // limit to 9.99V\r\n//                sprintf(s, \"%u.%02uV\", voltage / 100, voltage % 100);\r\n//                break;\r\n//            }\r\n//\r\n//            case 2:\t\t// percentage\r\n        sprintf(s, \"%u%%\", BATTERY_VoltsToPercent(gBatteryVoltageAverage));\r\n//                break;\r\n//        }\r\n\r\n        unsigned int space_needed = (7 * strlen(s));\r\n        if (x2 >= (x1 + space_needed))\r\n            UI_PrintStringSmallBuffer(s, line + x2 - space_needed);\r\n    }\r\n\r\n    // move to right side of the screen\r\n    x = LCD_WIDTH - sizeof(BITMAP_BatteryLevel1) - sizeof(BITMAP_USB_C);\r\n\r\n    // USB-C charge indicator\r\n    if (gChargingWithTypeC)\r\n        memcpy(line + x, BITMAP_USB_C, sizeof(BITMAP_USB_C));\r\n    x += sizeof(BITMAP_USB_C);\r\n\r\n    // BATTERY LEVEL indicator\r\n    UI_DrawBattery(line + x, gBatteryDisplayLevel, gLowBatteryBlink);\r\n\r\n    // **************\r\n\r\n    ST7565_BlitStatusLine();\r\n}"
  },
  {
    "path": "ui/status.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_STATUS_H\r\n#define UI_STATUS_H\r\n\r\nvoid UI_DisplayStatus();\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "ui/ui.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include \"../misc.h\"\r\n#include <assert.h>\r\n#include <string.h>\r\n\r\n#ifdef ENABLE_MESSENGER\r\n#include \"ui/messenger.h\"\r\n#endif\r\n\r\n#include \"app/chFrScanner.h\"\r\n#include \"app/dtmf.h\"\r\n\r\n#ifdef ENABLE_FMRADIO\r\n#include \"app/fm.h\"\r\n#endif\r\n\r\n#include \"driver/keyboard.h\"\r\n#include \"misc.h\"\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n#include \"ui/aircopy.h\"\r\n#endif\r\n#ifdef ENABLE_FMRADIO\r\n#include \"ui/fmradio.h\"\r\n#endif\r\n\r\n#include \"ui/inputbox.h\"\r\n#include \"ui/main.h\"\r\n#include \"ui/menu.h\"\r\n#include \"ui/scanner.h\"\r\n#include \"ui/ui.h\"\r\n\r\nGUI_DisplayType_t gScreenToDisplay;\r\nGUI_DisplayType_t gRequestDisplayScreen = DISPLAY_INVALID;\r\n\r\nuint8_t gAskForConfirmation;\r\nbool gAskToSave;\r\nbool gAskToDelete;\r\n\r\n\r\nvoid (*UI_DisplayFunctions[])(void) = {\r\n        [DISPLAY_MAIN] = &UI_DisplayMain,\r\n        [DISPLAY_MENU] = &UI_DisplayMenu,\r\n        [DISPLAY_SCANNER] = &UI_DisplayScanner,\r\n\r\n#ifdef ENABLE_FMRADIO\r\n        [DISPLAY_FM] = &UI_DisplayFM,\r\n#endif\r\n#ifdef ENABLE_MESSENGER\r\n        [DISPLAY_MSG] = &UI_DisplayMSG,\r\n#endif\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n        [DISPLAY_AIRCOPY] = &UI_DisplayAircopy,\r\n#endif\r\n\r\n};\r\n\r\nstatic_assert(ARRAY_SIZE(UI_DisplayFunctions) == DISPLAY_N_ELEM);\r\n\r\nvoid GUI_DisplayScreen(void) {\r\n    if (gScreenToDisplay != DISPLAY_INVALID) {\r\n        UI_DisplayFunctions[gScreenToDisplay]();\r\n    }\r\n}\r\n\r\nvoid GUI_SelectNextDisplay(GUI_DisplayType_t Display) {\r\n    if (Display == DISPLAY_INVALID)\r\n        return;\r\n\r\n    if (gScreenToDisplay != Display) {\r\n        DTMF_clear_input_box();\r\n\r\n        gInputBoxIndex = 0;\r\n        gIsInSubMenu = false;\r\n\r\n        gCssBackgroundScan = false;\r\n        gScanStateDir = SCAN_OFF;\r\n#ifdef ENABLE_FMRADIO\r\n        gFM_ScanState    = FM_SCAN_OFF;\r\n#endif\r\n        gAskForConfirmation = 0;\r\n        gAskToSave = false;\r\n        gAskToDelete = false;\r\n        gWasFKeyPressed = false;\r\n\r\n        gUpdateStatus = true;\r\n    }\r\n\r\n    gScreenToDisplay = Display;\r\n    gUpdateDisplay = true;\r\n}\r\n"
  },
  {
    "path": "ui/ui.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef GUI_H\r\n#define GUI_H\r\n\r\n#include <stdbool.h>\r\n#include <stdint.h>\r\nenum GUI_DisplayType_t\r\n{\r\n    DISPLAY_MAIN = 0,\r\n    DISPLAY_MENU,\r\n    DISPLAY_SCANNER,\r\n\r\n#ifdef ENABLE_FMRADIO\r\n    DISPLAY_FM,\r\n#endif\r\n#ifdef ENABLE_MESSENGER\r\n    DISPLAY_MSG,\r\n#endif\r\n\r\n#ifdef ENABLE_AIRCOPY\r\n    DISPLAY_AIRCOPY,\r\n#endif\r\n\r\n    DISPLAY_N_ELEM,\r\n    DISPLAY_INVALID = 0xFFu\r\n};\r\ntypedef enum GUI_DisplayType_t GUI_DisplayType_t;\r\n\r\nextern GUI_DisplayType_t gScreenToDisplay;\r\nextern GUI_DisplayType_t gRequestDisplayScreen;\r\n\r\nextern uint8_t           gAskForConfirmation;\r\nextern bool              gAskToSave;\r\nextern bool              gAskToDelete;\r\n\r\nvoid GUI_DisplayScreen(void);\r\nvoid GUI_SelectNextDisplay(GUI_DisplayType_t Display);\r\n\r\n#endif\r\n"
  },
  {
    "path": "ui/welcome.c",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n#include \"driver/uart.h\"\r\n#include \"chinese.h\"\r\n#include <string.h>\r\n#include \"driver/keyboard.h\"\r\n#include \"driver/eeprom.h\"\r\n#include \"driver/st7565.h\"\r\n#include \"external/printf/printf.h\"\r\n#include \"helper/battery.h\"\r\n#include \"settings.h\"\r\n#include \"misc.h\"\r\n#include \"ui/helper.h\"\r\n#include \"ui/welcome.h\"\r\n#include \"ui/status.h\"\r\n#include \"version.h\"\r\n#include \"driver/system.h\"\r\n//void UI_DisplayReleaseKeys(BOOT_Mode_t BootMode) {\r\n//    memset(gStatusLine, 0, sizeof(gStatusLine));\r\n//    memset(gFrameBuffer, 0, sizeof(gFrameBuffer));\r\n//\r\n//    if (BootMode == BOOT_MODE_F_LOCK) {\r\n//        //解锁，全部按键\r\n//        UI_PrintStringSmall(解锁, 0, 127, 1);\r\n//        UI_PrintStringSmall(全部按键, 0, 127, 3);\r\n//        ST7565_BlitStatusLine();  // blank status line\r\n//        ST7565_BlitFullScreen();\r\n//    }\r\n//\r\n//\r\n//}\r\n\r\nvoid UI_DisplayWelcome(void) {\r\n\r\n    char WelcomeString0[19] = {0};\r\n    char WelcomeString1[19] = {0};\r\n\r\n    memset(gStatusLine, 0, sizeof(gStatusLine));\r\n    UI_DisplayClear();\r\n    ST7565_BlitStatusLine();  // blank status line\r\n    ST7565_BlitFullScreen();\r\n#if ENABLE_CHINESE_FULL == 4\r\n\r\n    if (gEeprom.POWER_ON_DISPLAY_MODE == POWER_ON_DISPLAY_MODE_MESSAGE) {\r\n\r\n    uint8_t welcome_len[2];\r\n    EEPROM_ReadBuffer(0x02024, welcome_len, 2) ;\r\n    welcome_len[0]=welcome_len[0]>18?0:welcome_len[0];\r\n    welcome_len[1]=welcome_len[1]>18?0:welcome_len[1];\r\n    EEPROM_ReadBuffer(0x02000, WelcomeString0, welcome_len[0]) ;\r\n    EEPROM_ReadBuffer(0x02012, WelcomeString1, welcome_len[1]);\r\n\r\n#elif ENABLE_CHINESE_FULL == 0\r\n\r\n    EEPROM_ReadBuffer(0x0EB0, WelcomeString0, 16);\r\n    EEPROM_ReadBuffer(0x0EC0, WelcomeString1, 16);\r\n\r\n#endif\r\n    UI_PrintStringSmall(WelcomeString0, 0, 127, 0);\r\n    UI_PrintStringSmall(WelcomeString1, 0, 127, 2);\r\n    sprintf(WelcomeString1, \"%u.%02uV %u%%\",\r\n            gBatteryVoltageAverage / 100,\r\n            gBatteryVoltageAverage % 100,\r\n            BATTERY_VoltsToPercent(gBatteryVoltageAverage));\r\n    UI_PrintStringSmall(WelcomeString1, 0, 127, 4);\r\n    UI_PrintStringSmall(Version, 0, 127, 6);\r\n#if ENABLE_CHINESE_FULL == 4\r\n    }\r\n    else if(gEeprom.POWER_ON_DISPLAY_MODE == POWER_ON_DISPLAY_MODE_PIC)\r\n        {\r\n             EEPROM_ReadBuffer( 0x02080, gStatusLine, 128);\r\n    for (int i = 0; i < 7; ++i)  EEPROM_ReadBuffer(0x02080+128+128*i, &gFrameBuffer[i], 128);\r\n        }\r\n\r\n#endif\r\n\r\n\r\n    ST7565_BlitStatusLine();  // blank status line\r\n    ST7565_BlitFullScreen();\r\n    BACKLIGHT_TurnOn();\r\n\r\n\r\n}\r\n\r\n"
  },
  {
    "path": "ui/welcome.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef UI_WELCOME_H\r\n#define UI_WELCOME_H\r\n#include \"helper/boot.h\"\r\n//void UI_DisplayReleaseKeys(BOOT_Mode_t BootMode);\r\nvoid UI_DisplayWelcome(void);\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "utils/clean.bat",
    "content": "@echo off\r\n\r\ndel /S /Q *.~*\r\ndel /S /Q *.map\r\ndel /S /Q *.tds\r\ndel /S /Q *.obj\r\ndel /S /Q *.db\r\ndel /S /Q *.ilc\r\ndel /S /Q *.ild\r\ndel /S /Q *.ilf\r\ndel /S /Q *.ils\r\ndel /S /Q *.dcu\r\ndel /S /Q *.dsk\r\n\r\nrd /S /Q Debug\r\nrd /S /Q Release\r\nrd /S /Q ipch\r\n\r\ndel /S gain_table.c\r\ndel /S uv-k5_small.c\r\ndel /S uv-k5_small_bold.c\r\n\r\n::pause\r\n@echo on\r\n"
  },
  {
    "path": "utils/main.cpp",
    "content": "\r\n/* Copyright 2023 OneOfEleven\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#include <stdint.h>\r\n#include <stdio.h>\r\n#include <string.h>\r\n#include <vector>\r\n\r\n// ************************************************************************\r\n// create a front end gain table for the firmware\r\n\r\n\t//   <9:8> = LNA Gain Short\r\n\t//           3 =   0dB   < original value\r\n\t//           2 = -24dB   // was -11\r\n\t//           1 = -30dB   // was -16\r\n\t//           0 = -33dB   // was -19\r\n\t//\r\n\t//   <7:5> = LNA Gain\r\n\t//           7 =   0dB\r\n\t//           6 =  -2dB\r\n\t//           5 =  -4dB\r\n\t//           4 =  -6dB\r\n\t//           3 =  -9dB\r\n\t//           2 = -14dB   < original value\r\n\t//           1 = -19dB\r\n\t//           0 = -24dB\r\n\t//\r\n\t//   <4:3> = MIXER Gain\r\n\t//           3 =   0dB   < original value\r\n\t//           2 =  -3dB\r\n\t//           1 =  -6dB\r\n\t//           0 =  -8dB\r\n\t//\r\n\t//   <2:0> = PGA Gain\r\n\t//           7 =   0dB\r\n\t//           6 =  -3dB   < original value\r\n\t//           5 =  -6dB\r\n\t//           4 =  -9dB\r\n\t//           3 = -15dB\r\n\t//           2 = -21dB\r\n\t//           1 = -27dB\r\n\t//           0 = -33dB\r\n\r\ntypedef struct\r\n{\r\n\tuint8_t lna_short;\r\n\tuint8_t lna;\r\n\tuint8_t mixer;\r\n\tuint8_t pga;\r\n\tint16_t lna_short_dB;\r\n\tint16_t lna_dB;\r\n\tint16_t mixer_dB;\r\n\tint16_t pga_dB;\r\n\tint16_t sum_dB;\r\n} t_gain_table;\r\n\r\nvoid create_gain_table(const char *filename)\r\n{\r\n\tstd::vector <t_gain_table> gain_table;\r\n\r\n\tif (filename == NULL)\r\n\t\treturn;\r\n\r\n\t// front end register dB values\r\n//\tconst int16_t lna_short_dB[4] = { (-19), (-16), (-11), (0)};  // was\r\n\tconst int16_t lna_short_dB[4] = { (-33), (-30), (-24), (0)};  // corrected\r\n\tconst int16_t lna_dB[8]       = { (-24), (-19), (-14), (-9), (-6), (-4), (-2), (0)};\r\n\tconst int16_t mixer_dB[4]     = { (-8), (-6), (-3), (0)};\r\n\tconst int16_t pga_dB[8]       = { (-33), (-27), (-21), (-15), (-9), (-6), (-3), (0)};\r\n\r\n\tconst uint8_t orig_lna_short = 3;\r\n\tconst uint8_t orig_lna       = 2;\r\n\tconst uint8_t orig_mixer     = 3;\r\n\tconst uint8_t orig_pga       = 6;\r\n\r\n\tconst int16_t orig_gain_dB =\r\n\t\tlna_short_dB[orig_lna_short] +\r\n\t\tlna_dB[orig_lna] +\r\n\t\tmixer_dB[orig_mixer] +\r\n\t\tpga_dB[orig_pga];\r\n\r\n\t#if 1\r\n\t\t// full table\r\n\t\tconst uint8_t lna_short_min = 0;  // 0\r\n\t\tconst uint8_t lna_min       = 0;  // 0\r\n\t\tconst uint8_t mixer_min     = 0;  // 0\r\n\t\tconst uint8_t pga_min       = 0;  // 0\r\n\r\n\t\tconst uint8_t lna_short_max = 3;  // 3\r\n\t\tconst uint8_t lna_max       = 7;  // 5\r\n\t\tconst uint8_t mixer_max     = 3;  // 3\r\n\t\tconst uint8_t pga_max       = 7;  // 7\r\n\t#else\r\n\t\t// just one register changes\r\n\t\tconst uint8_t lna_short_min = 0;\r\n\t\tconst uint8_t lna_min       = 2;\r\n\t\tconst uint8_t mixer_min     = 3;\r\n\t\tconst uint8_t pga_min       = 6;\r\n\r\n\t\tconst uint8_t lna_short_max = 3;\r\n\t\tconst uint8_t lna_max       = 2;\r\n\t\tconst uint8_t mixer_max     = 3;\r\n\t\tconst uint8_t pga_max       = 6;\r\n\t#endif\r\n\r\n\tuint8_t lna_short = lna_short_min;\r\n\tuint8_t lna       = lna_min;\r\n\tuint8_t mixer     = mixer_min;\r\n\tuint8_t pga       = pga_min;\r\n\r\n\tunsigned int original_index = 0;\r\n\r\n\twhile (true)\r\n\t{\r\n\t\tt_gain_table entry;\r\n\r\n\t\tentry.lna_short    = lna_short;\r\n\t\tentry.lna          = lna;\r\n\t\tentry.mixer        = mixer;\r\n\t\tentry.pga          = pga;\r\n\r\n\t\tentry.lna_short_dB = lna_short_dB[lna_short];\r\n\t\tentry.lna_dB       = lna_dB[lna];\r\n\t\tentry.mixer_dB     = mixer_dB[mixer];\r\n\t\tentry.pga_dB       = pga_dB[pga];\r\n\r\n\t\tentry.sum_dB       = lna_short_dB[lna_short] + lna_dB[lna] + mixer_dB[mixer] + pga_dB[pga];\r\n\r\n\t\tif (entry.sum_dB != orig_gain_dB)\r\n\t\t\tgain_table.push_back(entry);\r\n\t\telse\r\n\t\tif (lna_short == orig_lna_short && lna == orig_lna && mixer == orig_mixer && pga == orig_pga)\r\n\t\t\tgain_table.push_back(entry);\r\n\r\n\t\tif (++pga <= pga_max)\r\n\t\t\tcontinue;\r\n\t\tpga = pga_min;\r\n\r\n\t\tif (++mixer <= mixer_max)\r\n\t\t\tcontinue;\r\n\t\tmixer = mixer_min;\r\n\r\n\t\tif (++lna <= lna_max)\r\n\t\t\tcontinue;\r\n\t\tlna = lna_min;\r\n\r\n\t\tif (++lna_short <= lna_short_max)\r\n\t\t\tcontinue;\r\n//\t\tlna_short = lna_short_min;\r\n\r\n\t\tbreak;\r\n\t}\r\n\r\n\t// sort the table according top the sum dB\r\n\tfor (unsigned int i = 0; i < (gain_table.size() - 1); i++)\r\n\t{\r\n\t\tt_gain_table entry1 = gain_table[i];\r\n\t\tfor (unsigned int k = i + 1; k < gain_table.size(); k++)\r\n\t\t{\r\n\t\t\tt_gain_table entry2 = gain_table[k];\r\n\t\t\tif (entry2.sum_dB < entry1.sum_dB)\r\n\t\t\t{\t// swap\r\n\t\t\t\tconst t_gain_table entry = entry1;\r\n\t\t\t\tentry1 = entry2;\r\n\t\t\t\tentry2 = entry;\r\n\t\t\t\tgain_table[i] = entry1;\r\n\t\t\t\tgain_table[k] = entry2;\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n\t{\t// remove sum_dB duplicates\r\n\t\tunsigned int i = 0;\r\n\t\twhile (i < gain_table.size())\r\n\t\t{\r\n\t\t\tconst t_gain_table entry1 = gain_table[i++];\r\n\r\n\t\t\tif (entry1.lna_short == orig_lna_short &&\r\n\t\t\t    entry1.lna       == orig_lna &&\r\n\t\t\t    entry1.mixer     == orig_mixer &&\r\n\t\t\t    entry1.pga       == orig_pga)\r\n\t\t\t\tcontinue;\t\t// leave the original inplace\r\n\r\n\t\t\twhile (i < gain_table.size())\r\n\t\t\t{\r\n\t\t\t\tconst t_gain_table entry2 = gain_table[i];\r\n\r\n\t\t\t\tif (entry2.lna_short == orig_lna_short &&\r\n\t\t\t\t    entry2.lna       == orig_lna &&\r\n\t\t\t\t    entry2.mixer     == orig_mixer &&\r\n\t\t\t\t    entry2.pga       == orig_pga)\r\n\t\t\t\t\tbreak;\t\t// leave the original inplace\r\n\r\n\t\t\t\tif (entry2.sum_dB != entry1.sum_dB)\r\n\t\t\t\t\tbreak;\r\n\r\n\t\t\t\tgain_table.erase(gain_table.begin() + i, gain_table.begin() + i + 1);\r\n\t\t\t}\r\n\t\t}\r\n\t}\r\n\r\n\t// find the index for the original Quansheng register settings\r\n\tfor (int i = (int)gain_table.size() - 1; i >= 0; i--)\r\n\t{\r\n\t\tconst t_gain_table entry = gain_table[i];\r\n\r\n\t\tif (entry.sum_dB != orig_gain_dB)\r\n\t\t\tcontinue;\r\n\r\n\t\tif (entry.lna_short != orig_lna_short ||\r\n\t\t    entry.lna       != orig_lna       ||\r\n\t\t    entry.mixer     != orig_mixer     ||\r\n\t\t    entry.pga       != orig_pga)\r\n\t\t\tcontinue;\r\n\r\n\t\toriginal_index = i;\r\n\t\tbreak;\r\n\t}\r\n\r\n\t// ***************************\r\n\t// save the table to a file\r\n\r\n/*\r\n\ttypedef struct\r\n\t{\r\n\t\t#if 1\r\n\t\t\t// bitfields take up less flash bytes\r\n\t\t\tuint8_t lna_short:2;   // 0 ~ 3\r\n\t\t\tuint8_t       lna:3;   // 0 ~ 7\r\n\t\t\tuint8_t     mixer:2;   // 0 ~ 3\r\n\t\t\tuint8_t       pga:3;   // 0 ~ 7\r\n\t\t#else\r\n\t\t\tuint8_t lna_short;     // 0 ~ 3\r\n\t\t\tuint8_t       lna;     // 0 ~ 7\r\n\t\t\tuint8_t     mixer;     // 0 ~ 3\r\n\t\t\tuint8_t       pga;     // 0 ~ 7\r\n\t\t#endif\r\n\t} t_am_fix_gain_table;\r\n\t//} __attribute__((packed)) t_am_fix_gain_table;\r\n*/\r\n\r\n\tFILE *file = fopen(filename, \"w\");\r\n\tif (file == NULL)\r\n\t\treturn;\r\n\r\n\tfprintf(file, \"\\n\");\r\n\tfprintf(file, \"\\tstatic const t_am_fix_gain_table am_fix_gain_table[] =\\n\");\r\n\tfprintf(file, \"\\t{\\n\");\r\n\r\n\t#if 0\r\n\t\tfprintf(file, \"\\t\\t{.lna_short = 3, .lna = 2, .mixer = 3, .pga = 6},      //  0 0dB -14dB  0dB  -3dB .. -17dB original\\n\\n\");\r\n\r\n\t\tfor (unsigned int i = 0; i < gain_table.size(); i++)\r\n\t\t{\r\n\t\t\tchar s[1024];\r\n\r\n\t\t\tconst t_gain_table entry = gain_table[i];\r\n\r\n\t\t\tsprintf(s, \"\\t\\t{%u, %u, %u, %u},         // %3u .. %3ddB %3ddB %2ddB %3ddB .. %3ddB\",\r\n\t\t\t\tentry.lna_short,\r\n\t\t\t\tentry.lna,\r\n\t\t\t\tentry.mixer,\r\n\t\t\t\tentry.pga,\r\n\t\t\t\t1 + i,\r\n\t\t\t\tentry.lna_short_dB,\r\n\t\t\t\tentry.lna_dB,\r\n\t\t\t\tentry.mixer_dB,\r\n\t\t\t\tentry.pga_dB,\r\n\t\t\t\tentry.sum_dB);\r\n\r\n\t\t\tif (i == original_index)\r\n\t\t\t\tstrcat(s, \" original\");\r\n\r\n\t\t\tfprintf(file, \"%s\\n\", s);\r\n\t\t}\r\n\t#else\r\n\t{\r\n\t\t//BK4819_WriteRegister(BK4819_REG_13, ((uint16_t)gains.lna_short << 8) | ((uint16_t)gains.lna << 5) | ((uint16_t)gains.mixer << 3) | ((uint16_t)gains.pga << 0));\r\n\r\n\t\tuint16_t reg_val;\r\n\t\tint16_t  sum_dB;\r\n\r\n\t\treg_val = ((uint16_t)orig_lna_short << 8) | ((uint16_t)orig_lna << 5) | ((uint16_t)orig_mixer << 3) | ((uint16_t)orig_pga << 0);\r\n\t\tsum_dB  = lna_short_dB[orig_lna_short] + lna_dB[orig_lna] + mixer_dB[orig_mixer] + pga_dB[orig_pga];\r\n\t\tfprintf(file, \"\\t\\t{0x%04X, %-3d},       //   0 ..   %u %u %u %u .. 0dB -14dB  0dB  -3dB .. -17dB original\\n\\n\",\r\n\t\t\treg_val,\r\n\t\t\tsum_dB,\r\n\t\t\torig_lna_short,\r\n\t\t\torig_lna,\r\n\t\t\torig_mixer,\r\n\t\t\torig_pga);\r\n\r\n\t\tfor (unsigned int i = 0; i < gain_table.size(); i++)\r\n\t\t{\r\n\t\t\tchar s[1024];\r\n\r\n\t\t\tconst t_gain_table entry = gain_table[i];\r\n\r\n\t\t\treg_val = ((uint16_t)entry.lna_short << 8) | ((uint16_t)entry.lna << 5) | ((uint16_t)entry.mixer << 3) | ((uint16_t)entry.pga << 0);\r\n\t\t\tsum_dB  = lna_short_dB[entry.lna_short] + lna_dB[entry.lna] + mixer_dB[entry.mixer] + pga_dB[entry.pga];\r\n\r\n\t\t\tsprintf(s, \"\\t\\t{0x%04X, %-3d},         // %3u .. %u %u %u %u .. %3ddB %3ddB %2ddB %3ddB .. %3ddB\",\r\n\t\t\t\treg_val,\r\n\t\t\t\tsum_dB,\r\n\r\n\t\t\t\t1 + i,\r\n\r\n\t\t\t\tentry.lna_short,\r\n\t\t\t\tentry.lna,\r\n\t\t\t\tentry.mixer,\r\n\t\t\t\tentry.pga,\r\n\r\n\t\t\t\tentry.lna_short_dB,\r\n\t\t\t\tentry.lna_dB,\r\n\t\t\t\tentry.mixer_dB,\r\n\t\t\t\tentry.pga_dB,\r\n\r\n\t\t\t\tentry.sum_dB);\r\n\r\n\t\t\tif (i == original_index)\r\n\t\t\t\tstrcat(s, \" original\");\r\n\r\n\t\t\tfprintf(file, \"%s\\n\", s);\r\n\t\t}\r\n\t}\r\n\t#endif\r\n\r\n\tfprintf(file, \"\\t};\\n\\n\");\r\n\r\n\tfprintf(file, \"\\tstatic const unsigned int original_index = %u;\\n\", 1 + original_index);\r\n\r\n\tfclose(file);\r\n}\r\n\r\n\t// ************************************************************************\r\n// \"rotate_font()\" has nothing to do with this program at all, I just needed\r\n// to write a bit of code to rotate some fonts I've drawn\r\n\r\nvoid rotate_font(const char *filename1, const char *filename2)\r\n{\r\n\tstd::vector <uint8_t> data;\r\n\r\n\tif (filename1 == NULL || filename2 == NULL)\r\n\t\treturn;\r\n\r\n\t// ****************************\r\n\t// load the file\r\n\r\n\tFILE *file = fopen(filename1, \"rb\");\r\n\tif (file == NULL)\r\n\t\treturn;\r\n\r\n\tif (fseek(file, 0, SEEK_END) != 0)\r\n\t{\r\n\t\tfclose(file);\r\n\t\treturn;\r\n\t}\r\n\tconst size_t file_size = ftell(file);\r\n\tif (file_size <= 0)\r\n\t{\r\n\t\tfclose(file);\r\n\t\treturn;\r\n\t}\r\n\tif (fseek(file, 0, SEEK_SET) != 0)\r\n\t{\r\n\t\tfclose(file);\r\n\t\treturn;\r\n\t}\r\n\r\n\tdata.resize(file_size);\r\n\r\n\tconst size_t bytes_loaded = fread(&data[0], 1, file_size, file);\r\n\r\n\tfclose(file);\r\n\r\n\tif (bytes_loaded != file_size)\r\n\t\treturn;\r\n\r\n\t// ***************************\r\n\t// rotate the font 90-deg clockwise\r\n\r\n\tfor (unsigned int i = 0; i <= (data.size() - 8); i += 8)\r\n\t{\r\n\t\tuint8_t c1[8];\r\n\t\tuint8_t c2[8];\r\n\t\tmemcpy(c1, &data[i], 8);\r\n\t\tmemset(c2, 0, 8);\r\n\t\tfor (unsigned int k = 0; k < 8; k++)\r\n\t\t{\r\n\t\t\tuint8_t b = c1[k];\r\n\t\t\tfor (unsigned int m = 0; m < 8; m++)\r\n\t\t\t{\r\n\t\t\t\tif (b & 0x80)\r\n\t\t\t\t\tc2[m] |= 1u << k;\r\n\t\t\t\tb <<= 1;\r\n\t\t\t}\r\n\t\t}\r\n\t\tmemcpy(&data[i], c2, 8);\r\n\t}\r\n\r\n\t// ***************************\r\n\t// save the file\r\n\r\n\tfile = fopen(filename2, \"wt\");\r\n\tif (file == NULL)\r\n\t\treturn;\r\n\r\n\tfprintf(file, \"const uint8_t gFontSmall[95][7] =\\n\");\r\n\tfprintf(file, \"{\\n\");\r\n\r\n\tfor (unsigned int i = 0; i < data.size(); )\r\n\t{\r\n\t\tchar s[1024]={0};\r\n//\t\tmemset(s, 0, sizeof(s));\r\n\r\n//\t\tfor (unsigned int k = 0; k < 8 && i < data.size(); k++)\r\n\t\tfor (unsigned int k = 0; k < 7 && i < data.size(); k++)\r\n\t\t{\r\n\t\t\tchar s2[16];\r\n\t\t\tsprintf(s2, \"0x%02X\", data[i++]);\r\n\r\n\t\t\tif (k == 0)\r\n\t\t\t\tstrcat(s, \"\\t{\");\r\n\r\n//\t\t\tif (k < 7)\r\n\t\t\tif (k < 6)\r\n\t\t\t{\r\n\t\t\t\tstrcat(s,  s2);\r\n\t\t\t\tstrcat(s, \", \");\r\n\t\t\t}\r\n\t\t\telse\r\n\t\t\t{\r\n\t\t\t\tstrcat(s, s2);\r\n\t\t\t\tstrcat(s, \"},\\n\");\r\n\t\t\t}\r\n\t\t}\r\n\r\n\t\ti++;\r\n\r\n\t\tfprintf(file, \"%s\", s);\r\n\t}\r\n\r\n\tfprintf(file, \"};\\n\");\r\n\r\n\tfclose(file);\r\n\r\n\t// ***************************\r\n}\r\n\r\n#pragma argsused\r\nint main(int argc, char* argv[])\r\n{\r\n\tcreate_gain_table(\"gain_table.c\");\r\n\r\n\trotate_font(\"uv-k5_small.bin\",      \"uv-k5_small.c\");\r\n\trotate_font(\"uv-k5_small_bold.bin\", \"uv-k5_small_bold.c\");\r\n\r\n\treturn 0;\r\n}\r\n"
  },
  {
    "path": "utils/misc.bpf",
    "content": "This file is used by the project manager only and should be treated like the project file\r\n\r\nmain \r\n"
  },
  {
    "path": "utils/misc.bpr",
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    "path": "uv-k5font/chinese_array.txt",
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    "path": "uv-k5font/font-pixel-made/chinese.txt",
    "content": "/opt/homebrew/anaconda3/bin/python3.11 /Users/rubo/uv-k5font/font-pixel-made/font.py\r\n{0x77,0xb7,0xd1,0xf7,0xf7,0x80,0x75,0xb5,0xd5,0xf7,0xff,0x57,0xf9,0xff},/*步*/\r\n{0xf6,0x05,0xff,0x6b,0xab,0xc0,0xeb,0x00,0xeb,0xeb,0xff,0x59,0x55,0x75},/*进*/\r\n{0xb1,0xd7,0x80,0x75,0x95,0xff,0x82,0xf8,0x02,0xfa,0x82,0xe5,0x9f,0x9b},/*频*/\r\n{0x7d,0x55,0x6d,0x3d,0x0c,0x0d,0x3d,0x6d,0x55,0x7d,0xff,0xff,0xfc,0xff},/*率*/\r\n{0xfb,0x78,0x9b,0xe3,0xf8,0xcb,0x2b,0xaa,0xca,0xfd,0xfb,0x79,0xa9,0x96},/*发*/\r\n{0xbf,0x81,0x34,0xad,0x01,0xff,0xfb,0x9b,0xfb,0x00,0xfb,0x79,0x7c,0x71},/*射*/\r\n{0x7d,0x01,0x7d,0x7d,0xff,0xfb,0xfb,0x3b,0xc0,0xfb,0x03,0xff,0xe5,0xe7},/*功*/\r\n{0xdb,0x00,0xeb,0xff,0xd5,0x11,0xc4,0x55,0x91,0xd5,0xff,0x71,0xa5,0xb5},/*接*/\r\n{0x01,0x7f,0xbf,0x00,0xff,0xf7,0xfb,0xc4,0x3d,0x81,0xfd,0x3f,0x5f,0x5a},/*收*/\r\n{0xaa,0x31,0x93,0xa0,0xb1,0x2a,0xf7,0x80,0x7b,0x83,0xfb,0xa5,0x96,0x9b},/*数*/\r\n{0xb1,0xbd,0xb5,0xb5,0xb5,0x14,0xa5,0xbd,0xbd,0xb1,0xff,0x7f,0xf1,0xff},/*字*/\r\n{0xe6,0x9e,0xfe,0x00,0xfe,0xfe,0x00,0xfe,0x9e,0xe6,0xff,0x15,0x45,0x75},/*亚*/\r\n{0xf7,0xf5,0x11,0x51,0x54,0x55,0x51,0x11,0xf5,0xf7,0xff,0x4f,0x15,0x3f},/*音*/\r\n{0xbb,0xcb,0x00,0xeb,0xbf,0x85,0xa0,0x25,0x90,0x85,0xbf,0xcf,0xe5,0xd6},/*模*/\r\n{0xdb,0x00,0xeb,0xff,0x01,0xbf,0xdd,0x73,0x3f,0xc0,0xff,0xf1,0xe7,0xdb},/*拟*/\r\n{0xf6,0x05,0xff,0x6b,0x6a,0x81,0xa9,0x6a,0x6b,0xff,0xff,0x59,0x55,0x75},/*送*/\r\n{0xed,0x65,0x85,0xe4,0xa1,0xa5,0x24,0xa5,0xa5,0xed,0xed,0x5e,0x45,0x75},/*差*/\r\n{0xfb,0xfb,0xfb,0x7b,0x82,0xeb,0xeb,0xeb,0xeb,0x0b,0xfb,0xe5,0x5f,0x79},/*方*/\r\n{0x01,0xfd,0xfd,0x05,0x74,0x75,0x05,0xfd,0xfd,0x01,0xff,0xfc,0x7f,0x71},/*向*/\r\n{0xf9,0xf5,0x05,0xe1,0xe5,0x24,0xe5,0x01,0xf5,0xf9,0xff,0x55,0x4e,0x71},/*宽*/\r\n{0xb9,0xb5,0xd5,0xe9,0x0d,0xac,0xa9,0xa5,0xa5,0xe9,0xff,0xff,0xa8,0xbe},/*窄*/\r\n{0xed,0x0d,0xc8,0xcd,0xcd,0x08,0xcd,0xcd,0xc8,0x0d,0xed,0xfb,0xb3,0xba},/*带*/\r\n{0x02,0x50,0x62,0x50,0x02,0xff,0x0e,0xee,0xee,0x60,0xff,0x54,0x4c,0x71},/*配*/\r\n{0xf4,0xf2,0x12,0x94,0x02,0x52,0xd4,0x12,0xf2,0xf4,0xff,0x45,0x01,0x35},/*置*/\r\n{0xfb,0x7b,0x80,0xfb,0xfb,0x03,0xff,0x01,0xfd,0xfd,0x01,0x79,0xb9,0xaa},/*加*/\r\n{0xc9,0x55,0xed,0xc5,0xc9,0x44,0xd9,0xcd,0x75,0xe9,0xff,0x53,0x51,0x7c},/*密*/\r\n{0xee,0x0d,0xff,0x07,0x56,0x54,0x02,0x54,0x56,0x07,0xff,0x19,0x45,0x51},/*通*/\r\n{0xf6,0x05,0xff,0xff,0xf7,0x35,0xb5,0x81,0xb6,0x36,0xf7,0x93,0x53,0x71},/*话*/\r\n{0xf6,0x05,0xff,0x10,0xd2,0x52,0x00,0x52,0xd2,0x10,0xff,0x59,0x55,0x75},/*遇*/\r\n{0xe3,0xff,0x00,0xf7,0xff,0xfb,0x03,0xf8,0xfb,0xfb,0xfb,0xcf,0x4f,0x55},/*忙*/\r\n{0xb5,0xa9,0xa0,0xa9,0xa5,0x2f,0xa5,0xa9,0xa0,0xa9,0xb5,0xe5,0xf1,0xd6},/*禁*/\r\n{0xff,0x00,0xfe,0xee,0xee,0x02,0xee,0xae,0x6e,0xfe,0xff,0x59,0x51,0x75},/*压*/\r\n{0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x54,0x55,0x45},/*扩*/\r\n{0xf6,0x05,0xff,0xff,0x00,0xfe,0x1a,0x40,0x1a,0xfe,0x00,0x93,0xfe,0xc5},/*调*/\r\n{0x1b,0xd4,0xd5,0x00,0xd5,0xd5,0x1f,0xff,0x81,0xff,0x00,0x3e,0xeb,0xc5},/*制*/\r\n{0xeb,0xeb,0x0b,0xeb,0xeb,0xeb,0xfb,0xc0,0x3b,0xfa,0x79,0x45,0xfa,0xcb},/*式*/\r\n{0xdb,0x00,0xeb,0xff,0xe1,0xa5,0x2f,0x80,0xaf,0x25,0xa1,0xf1,0x85,0x96},/*搜*/\r\n{0xe7,0x75,0x55,0x55,0x25,0x20,0x55,0x65,0x75,0xf5,0xe7,0xe5,0xbc,0xb5},/*索*/\r\n{0xde,0xe6,0xf0,0xd6,0x06,0xff,0x83,0xff,0xff,0x00,0xff,0x97,0x7f,0x71},/*列*/\r\n{0xdf,0xd5,0x55,0x55,0x95,0xc0,0x95,0x55,0xd5,0x55,0xdf,0x3b,0xf9,0xd6},/*表*/\r\n{0xdd,0xed,0x05,0xf9,0xbc,0xb5,0xb5,0x15,0xa5,0xbd,0xfd,0xcf,0x1f,0x3f},/*存*/\r\n{0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x54,0x55,0x45},/*储*/\r\n{0xf7,0x03,0xfc,0xff,0x7d,0x55,0x54,0x55,0x55,0x7d,0xff,0xf3,0x54,0x71},/*信*/\r\n{0xf6,0x05,0xff,0xfd,0x05,0x24,0xa9,0x24,0x05,0xfd,0xff,0x59,0x55,0x75},/*道*/\r\n{0x00,0xee,0x00,0xef,0x00,0xee,0x00,0xff,0x81,0xff,0x00,0xce,0xce,0xc7},/*删*/\r\n{0x00,0x7e,0x00,0xff,0xfb,0x5d,0xd6,0x06,0xd6,0x55,0xfb,0xfc,0x1e,0x2f},/*除*/\r\n{0xf7,0x17,0xdb,0x15,0xf5,0x16,0xd5,0xd5,0x1b,0xf7,0xf7,0xab,0xb3,0xbe},/*命*/\r\n{0xff,0x7b,0x2b,0xdd,0x0c,0xc5,0xd5,0xd5,0xd9,0xdf,0x1f,0xfe,0x54,0x45},/*名*/\r\n{0xdb,0x00,0xeb,0xff,0xee,0xee,0xee,0xee,0xee,0xee,0x00,0xf1,0x55,0x45},/*扫*/\r\n{0xdb,0x00,0xeb,0xff,0x05,0xb5,0xb0,0x05,0xb5,0xb0,0x05,0xf1,0x14,0x05},/*描*/\r\n{0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x54,0x55,0x45},/*恢*/\r\n{0x7b,0x7c,0xa1,0x05,0xa5,0xa5,0xa5,0x25,0xa1,0xfd,0xff,0x55,0x6a,0x75},/*复*/\r\n{0xeb,0x6c,0x81,0x6d,0xff,0xfe,0x22,0xea,0xea,0x22,0xfe,0x39,0x17,0x14},/*短*/\r\n{0xdb,0x00,0xeb,0xff,0xe9,0xad,0x44,0x6d,0x8d,0xe9,0xff,0xf1,0x95,0x95},/*按*/\r\n{0x01,0xfe,0x81,0xfd,0x05,0xfd,0x81,0xff,0x81,0xff,0x00,0x9c,0xdb,0xc5},/*侧*/\r\n{0xd3,0x04,0xd5,0x09,0xf7,0xa5,0xa5,0x00,0xa5,0xa1,0xff,0x63,0x16,0x35},/*键*/\r\n{0xef,0xef,0x00,0xef,0xe7,0xab,0x6d,0xee,0xef,0xef,0xff,0x4f,0xbe,0xb5},/*长*/\r\n{0xef,0xaf,0x41,0x6d,0x65,0x6c,0x6d,0x4d,0x6d,0x81,0xef,0x45,0x44,0x54},/*盘*/\r\n{0xff,0x01,0xad,0xad,0xad,0xac,0xad,0xad,0x01,0xff,0xff,0x53,0x55,0x7c},/*自*/\r\n{0x77,0x95,0xe5,0x75,0x35,0xff,0xfb,0x7b,0x80,0xfb,0x03,0xea,0x9e,0xa7},/*动*/\r\n{0xb3,0x04,0xb5,0xff,0x86,0xf5,0x77,0x90,0x77,0xf5,0x86,0xe3,0xf9,0xdb},/*锁*/\r\n{0xf9,0xf5,0x15,0xf5,0xf5,0x04,0xb5,0xb5,0xb5,0xf5,0xf9,0xb9,0x5a,0x55},/*定*/\r\n{0xf7,0x15,0xf5,0x00,0xb5,0xb5,0xff,0x0c,0x6e,0x6a,0x08,0xac,0x55,0x55},/*超*/\r\n{0x01,0xed,0xed,0x01,0xff,0xfb,0xeb,0x9b,0xfb,0x00,0xfb,0xaa,0x7f,0x71},/*时*/\r\n{0xeb,0xed,0x0e,0x57,0x57,0x50,0x57,0x52,0x05,0xfb,0xff,0x4f,0x55,0x7c},/*省*/\r\n{0x81,0xb5,0xb5,0xb5,0x00,0xb5,0xb5,0xb5,0x81,0xff,0x7f,0xff,0x54,0x45},/*电*/\r\n{0xef,0x6d,0x65,0x25,0x85,0xa0,0xa5,0x25,0xa5,0xed,0xef,0x55,0x6a,0x55},/*麦*/\r\n{0xfd,0xfd,0xc5,0xd5,0x15,0xd0,0x15,0xd5,0xc5,0xfd,0x7d,0x95,0x6f,0x45},/*克*/\r\n{0xff,0x00,0xfe,0x7a,0xb6,0xce,0xb6,0x7a,0xfe,0x00,0xff,0xf9,0xff,0xcb},/*风*/\r\n{0x77,0x01,0x77,0xff,0xe1,0x04,0xad,0x21,0x4c,0x05,0xe1,0xff,0x43,0x71},/*增*/\r\n{0xed,0x2d,0xb4,0x35,0xbd,0xbd,0x35,0xb4,0x2d,0xed,0xff,0x11,0x45,0x74},/*益*/\r\n{0xdf,0xa0,0x6a,0x0a,0xea,0xea,0x0a,0x6a,0xa0,0xdf,0xff,0x15,0x45,0x75},/*显*/\r\n{0xf7,0x76,0x96,0xf6,0xf6,0x06,0xf6,0xf6,0xd6,0xb7,0x77,0x7e,0xf1,0xef},/*示*/\r\n{0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x54,0x55,0x45},/*条*/\r\n{0xef,0xee,0x6e,0x80,0xee,0xee,0xee,0x00,0xee,0xee,0xef,0xe7,0x3f,0x3f},/*开*/\r\n{0xbb,0xcb,0x00,0xdb,0xff,0x00,0xfe,0xfe,0x00,0xff,0x7f,0xcf,0xf9,0xc4},/*机*/\r\n{0xff,0x7f,0x81,0x2d,0xa4,0x25,0xb5,0x81,0x7f,0xff,0xff,0xb9,0x05,0x33},/*息*/\r\n{0xf7,0x2e,0xfd,0xff,0xef,0x01,0xf7,0x80,0xf7,0xdb,0x43,0xfc,0x53,0x45},/*池*/\r\n{0xed,0xf5,0xf0,0x0f,0xaf,0xaf,0xaf,0x10,0xed,0xee,0xf7,0x3f,0x2a,0x3f},/*背*/\r\n{0xef,0xed,0xeb,0x27,0xcf,0xe0,0x0f,0xe7,0xeb,0xed,0x6f,0xe5,0x4f,0x45},/*光*/\r\n{0xef,0x00,0xca,0x4a,0x0a,0x8a,0x4a,0xca,0x50,0x8f,0xff,0xea,0x94,0xb5},/*最*/\r\n{0xbf,0xcf,0xf3,0xff,0xff,0x00,0xff,0xff,0xfb,0xe7,0x9f,0x7f,0xf1,0xff},/*小*/\r\n{0xcd,0xed,0xe9,0x25,0xe4,0xe5,0x25,0xe9,0xed,0xcd,0xff,0xe5,0x4f,0x71},/*亮*/\r\n{0xff,0x01,0xf5,0xb5,0x21,0xa4,0xa5,0x21,0xb5,0xfd,0xff,0x59,0x69,0x75},/*度*/\r\n{0xfb,0xfb,0x7b,0x9b,0xe0,0xdb,0xbb,0x7b,0xfb,0xfb,0xff,0xe5,0xbf,0xb5},/*大*/\r\n{0xff,0x7f,0x81,0x15,0xd5,0xd5,0xd4,0xd5,0xd5,0x11,0xff,0x39,0x55,0x71},/*启*/\r\n{0xb7,0x93,0xa4,0xb7,0xfb,0x2b,0xab,0xa0,0xab,0x2b,0xfb,0xa5,0x53,0x71},/*结*/\r\n{0xfd,0xc5,0x55,0x95,0xd5,0x00,0x95,0x55,0xd5,0xc5,0xfd,0xfa,0xf3,0xda},/*束*/\r\n{0xff,0x00,0xfa,0x5a,0x4a,0x4a,0x0a,0xa2,0xaa,0xba,0xb8,0xf9,0x4f,0x45},/*尾*/\r\n{0xfb,0x36,0xfd,0xff,0x06,0x55,0x50,0x57,0x53,0x05,0xfe,0xfc,0xfc,0xf1},/*消*/\r\n{0xf6,0x05,0xff,0xfb,0xeb,0x4b,0x7b,0x00,0xfb,0xfb,0xff,0x59,0x55,0x55},/*过*/\r\n{0xc3,0xdb,0xdb,0xdb,0xdb,0x00,0xdb,0xdb,0xdb,0xdb,0xc3,0xff,0xf3,0xff},/*中*/\r\n{0x93,0xac,0xb7,0xff,0x00,0xff,0x29,0xc7,0x01,0xc7,0x29,0xe5,0x54,0x55},/*继*/\r\n{0xff,0xef,0xef,0xef,0xef,0xef,0xef,0xef,0xef,0xef,0xff,0xff,0xff,0xff},/*一*/\r\n{0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x54,0x55,0x45},/*即*/\r\n{0x01,0x7d,0x01,0xff,0xdb,0xd9,0xd5,0x00,0xde,0xd6,0xdb,0xff,0x1f,0x3f},/*呼*/\r\n{0xbf,0xbf,0x81,0xb5,0xa4,0x25,0xad,0x01,0xdf,0xef,0xff,0x95,0x1e,0x3f},/*身*/\r\n{0xf7,0x03,0xfc,0xf7,0x6b,0x8c,0xef,0xec,0x0b,0xf7,0xff,0x73,0x5e,0x7e},/*份*/\r\n{0xf6,0x02,0xf4,0x06,0xff,0x7e,0x60,0x6e,0xe0,0x0f,0xff,0xab,0x5f,0x79},/*码*/\r\n{0xff,0xff,0xff,0xff,0xff,0x00,0xf7,0xf7,0xf7,0xff,0xff,0x55,0x51,0x55},/*上*/\r\n{0xa7,0x8b,0xac,0xb7,0xff,0xd7,0xd7,0x80,0x6b,0x6a,0xa9,0xa5,0x97,0x86},/*线*/\r\n{0xfe,0xfe,0xfe,0xfe,0x00,0xfe,0xf6,0xee,0xde,0xfe,0xff,0xff,0xfc,0xff},/*下*/\r\n{0x01,0x7d,0x01,0xff,0x03,0xfb,0x09,0x6a,0x0b,0xfb,0x03,0xff,0xfc,0xc7},/*响*/\r\n{0xff,0x01,0xfd,0xed,0x9d,0xf5,0xcc,0x3d,0xc5,0xfd,0xff,0x59,0x15,0x35},/*应*/\r\n{0xf7,0x03,0xfc,0xfb,0xc3,0x3b,0xfa,0xf9,0x3b,0xc3,0xfb,0x73,0x15,0x15},/*位*/\r\n{0xf6,0xf2,0x02,0xb4,0xc6,0xff,0x82,0xfa,0x00,0xfa,0x82,0xc6,0x9f,0x9b},/*预*/\r\n{0xd7,0x85,0xa5,0x00,0xa5,0x95,0xf7,0xc0,0x37,0xd6,0x65,0x2a,0x9a,0x8b},/*载*/\r\n{0xff,0x36,0xed,0xff,0x03,0xf9,0xcd,0xad,0x60,0xad,0xc9,0x7c,0x9e,0x9b},/*波*/\r\n{0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x54,0x55,0x45},/*解*/\r\n{0xfe,0x00,0x5a,0x00,0xbf,0xff,0xda,0xd9,0x03,0xd9,0xda,0x3e,0x9f,0x9b},/*联*/\r\n{0xdf,0xdd,0x45,0xc5,0xc9,0x0d,0xd5,0x5a,0xee,0xdf,0xff,0xfa,0xf1,0xfa},/*系*/\r\n{0xff,0xff,0x7f,0x9f,0xe7,0xf8,0xe7,0x1f,0xff,0xff,0xff,0xf9,0xff,0xf6},/*人*/\r\n{0xfd,0x15,0x55,0x15,0x55,0x50,0x55,0x15,0x55,0x15,0xfd,0xf9,0xff,0xff},/*声*/\r\n{0xdb,0x00,0xeb,0xff,0xe9,0xcd,0xd1,0x1c,0xd1,0xcd,0xe9,0xf1,0x15,0x15},/*控*/\r\n{0xed,0x09,0xa0,0xa9,0x0d,0xef,0xab,0xa8,0x01,0xab,0x83,0xa3,0x7c,0x7c},/*静*/\r\n{0x01,0x7d,0x01,0xff,0x63,0x6b,0x60,0x3a,0x60,0x6b,0x63,0x7f,0x39,0x1b},/*噪*/\r\n{0xbb,0xac,0xa9,0x25,0xad,0xab,0xac,0x85,0x2d,0xa9,0xa5,0xff,0x5e,0x7c},/*等*/\r\n{0x93,0xa4,0xbf,0xff,0xff,0x7e,0x80,0xbe,0x76,0xb0,0xc7,0xe5,0x99,0x9b},/*级*/\r\n{0xd1,0xdb,0x00,0xeb,0xff,0xd7,0x95,0x50,0xd5,0x05,0xd7,0xcf,0xff,0xf1},/*特*/\r\n{0xf7,0x00,0xb7,0xff,0xdf,0x01,0xef,0x80,0xd7,0xb7,0x87,0xfe,0x53,0x45},/*地*/\r\n{0x00,0xfe,0xfe,0x7a,0xb6,0xd6,0xee,0x96,0x7a,0xfe,0xff,0x54,0x55,0x75},/*区*/\r\n{0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x54,0x55,0x45},/*段*/\r\n{0xdf,0xdb,0xda,0x59,0x83,0x9b,0x59,0xda,0xdb,0xdf,0xff,0xe5,0xbf,0xb5},/*关*/\r\n{0xaf,0xab,0x49,0x6a,0x43,0x8b,0xab,0x4d,0xab,0xaf,0xff,0x57,0xe9,0xff},/*参*/\r\n{0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x54,0x55,0x45},/*低*/\r\n{0x0d,0xed,0xe9,0x25,0xa5,0xa4,0x25,0xe9,0xed,0x0d,0xff,0xbc,0xea,0xf1},/*高*/\r\n{0xf7,0x03,0xfc,0xff,0x01,0x55,0x15,0x54,0x15,0x55,0x11,0x73,0xcc,0xcc},/*偏*/\r\n{0x6d,0x8d,0x01,0xae,0x7f,0xab,0x45,0xcc,0xcd,0x55,0x99,0xcf,0x95,0xbe},/*移*/\r\n{0x06,0xfd,0x6f,0x6e,0xae,0x02,0xee,0xee,0xee,0xfe,0x00,0xfc,0xf1,0xc7},/*闭*/\r\n{0xff,0xfb,0xdb,0xdb,0xda,0x01,0xdb,0xdb,0xdb,0xfb,0xff,0x57,0x51,0x75},/*主*/\r\n{0xf8,0x66,0x9e,0x66,0xf8,0xff,0xf8,0x66,0x9e,0x66,0xf8,0xb9,0x9d,0x9b},/*双*/\r\n{0xff,0xff,0xfd,0xfd,0xfd,0xfd,0xfd,0xfd,0xfd,0xff,0xff,0xab,0xaa,0xba},/*二*/\r\n{0xdf,0xdf,0xd0,0x16,0x56,0x56,0x56,0x50,0x5f,0xdf,0xff,0xff,0x57,0x7e},/*号*/\r\n{0xff,0x01,0xf5,0x15,0xd5,0xd5,0xd6,0xd6,0x16,0xf7,0xff,0x39,0x55,0x7c},/*后*/\r\n{0xcf,0xd7,0xd8,0x5b,0x9b,0x80,0x5b,0xdb,0xdb,0xdf,0xff,0xe5,0xbf,0xb5},/*失*/\r\n{0xf7,0x03,0xfc,0xff,0xcd,0xad,0xa9,0x28,0xa9,0xad,0xcd,0xf3,0x17,0x3f},/*停*/\r\n{0xff,0xff,0x07,0xff,0xff,0x00,0xf7,0xf7,0xf7,0xff,0xff,0x45,0x51,0x55},/*止*/\r\n{0x75,0x95,0x01,0xd6,0x7e,0x93,0xfc,0x01,0xfd,0xcd,0x39,0xcf,0x1f,0x3f},/*称*/\r\n{0xde,0xde,0xee,0xf6,0x02,0xfc,0xf6,0xee,0xde,0xbe,0xff,0xff,0xfc,0xff},/*不*/\r\n{0x7b,0xbb,0x5b,0x63,0x7b,0x00,0x7b,0x63,0x5b,0xbb,0x7b,0xff,0xf3,0xff},/*本*/\r\n{0xd3,0x04,0xd5,0xff,0xd7,0x5b,0x5d,0x56,0x5d,0x5b,0xd7,0xd3,0x5f,0x7e},/*铃*/\r\n{0x00,0xfe,0xfe,0x86,0xb6,0xb6,0x86,0xfe,0xfe,0x00,0xff,0x54,0x55,0x71},/*回*/\r\n{0xf7,0xfb,0xbb,0xb5,0xb5,0x06,0xb5,0xb5,0xbb,0xfb,0xf7,0x57,0x51,0x75},/*全*/\r\n{0xef,0x2d,0xa5,0xac,0xa5,0x2d,0xef,0x00,0x76,0x76,0x88,0x53,0x31,0x3f},/*部*/\r\n{0xc3,0xdb,0x00,0xdb,0x43,0xff,0xf7,0xb5,0x10,0xb5,0xf7,0xa1,0x5c,0x54},/*蛙*/\r\n{0x01,0x7d,0x7d,0x01,0xff,0x01,0x7f,0x7f,0xbf,0x00,0xff,0xff,0xff,0xf3},/*叫*/\r\n{0xff,0x01,0xd5,0xd6,0xc6,0xff,0x01,0xed,0xee,0x0e,0xef,0xf9,0xf9,0xf3},/*所*/\r\n{0xdd,0xed,0x05,0x51,0x54,0x55,0x55,0x55,0x05,0xfd,0xff,0xcf,0x5f,0x7c},/*有*/\r\n{0xff,0x00,0xb6,0xb6,0xb6,0x00,0xb6,0xb6,0xb6,0x00,0xff,0xf9,0xf3,0xf1},/*用*/\r\n{0x00,0xf7,0xf7,0xf7,0x77,0xff,0x00,0xf7,0xf7,0xfb,0x7d,0x94,0x4f,0x45},/*比*/\r\n{0xf7,0x03,0xfc,0xdf,0xee,0xd0,0x06,0xff,0x81,0xff,0x00,0xf3,0x79,0x45},/*例*/\r\n{0xbf,0xb5,0xb5,0xb5,0x01,0xb6,0xb6,0xb6,0xb6,0xbf,0xff,0x7f,0xfc,0xff},/*手*/\r\n{0xfb,0x04,0xf5,0xf1,0x15,0xd7,0xd3,0x14,0xf5,0xf1,0x05,0xf3,0xaa,0x87},/*筒*/\r\n{0xee,0x0d,0xff,0xff,0x8f,0x50,0xde,0xde,0x50,0x8f,0xff,0xe3,0xa5,0x95},/*设*/\r\n{0xff,0x31,0xbf,0x20,0xb7,0xb8,0x33,0xab,0x3b,0xff,0xff,0x11,0x45,0x74},/*监*/\r\n{0x01,0x7d,0x01,0xff,0x01,0xf5,0xf5,0x06,0xf6,0xf7,0xff,0x7f,0x3e,0x3f},/*听*/\r\n{0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x54,0x55,0x45},/*切*/\r\n{0xdb,0x00,0xeb,0xbf,0x87,0xb3,0x24,0x15,0xb1,0x87,0xbf,0x71,0xf9,0xf6},/*换*/\r\n\r\n"
  },
  {
    "path": "uv-k5font/font-pixel-made/font.py",
    "content": "import subprocess\r\n\r\n\r\n\r\nfrom PIL import Image, ImageDraw, ImageFont\r\n\r\n# 字体文件和字符\r\nfont_path = './ark-pixel-12px-proportional.ttc'  # 替换为你的字体文件路径\r\n\r\n# 图像大小和字体大小\r\nimage_size = (11, 10)  # 图像大小//列 行\r\nfont_size = 11  # 字体大小\r\n\r\n\r\nchar_num=2\r\nchar_sum=['步','进']\r\nfor i in range(char_num):\r\n    character = char_sum[i]\r\n    out_path=\"./image/\"+character+\".png\"\r\n    # 创建图像\r\n    image = Image.new('1', image_size, color=1)  # '1'表示二值图像，初始为白色\r\n\r\n    # 加载字体\r\n    font = ImageFont.truetype(font_path, font_size)\r\n\r\n    # 设置字符在画布上的位置\r\n    x_pos = 0  # 横坐标位置\r\n    y_pos = -4  # 纵坐标位置\r\n\r\n    # 在图像上绘制字符\r\n    draw = ImageDraw.Draw(image)\r\n    draw.text((x_pos, y_pos), character, font=font, fill=0)  # fill=0 表示黑色\r\n\r\n    # 显示图像或保存图像\r\n    image.save(out_path, format=\"PNG\")\r\n\r\n\r\n    # 执行代码\r\n    path_name = out_path\r\n\r\n    # 在b.py中运行，传递路径名作为参数\r\n    subprocess.run([\"python\", \"pic.py\", path_name])\r\n\r\n\r\n"
  },
  {
    "path": "uv-k5font/font-pixel-made/pic.py",
    "content": "import math\r\n\r\nimport cv2\r\nimport sys\r\nimport os\r\nimport numpy as np\r\n\r\n# 在获取图像路径输入之前，对路径进行解码\r\n# 读取命令行参数\r\narguments = sys.argv[1]  # 忽略第一个参数，因为它是脚本的名称\r\n\r\n# 缩放倍数\r\nscale_factor = 20  # 可根据需要调整放大倍数\r\n\r\n# 是否输出图像内容\r\noutput_image = False\r\n\r\ndef process_file_path(file_path):\r\n    file_name_with_extension = os.path.basename(file_path)  # 获取包含后缀的文件名\r\n    file_name_without_extension, extension = os.path.splitext(file_name_with_extension)  # 分离文件名和后缀\r\n\r\n    # 提取不带路径的文件名\r\n    file_name_without_path = os.path.splitext(os.path.basename(file_path))[0]\r\n\r\n    return {\r\n        \"file_name_with_extension\": file_name_with_extension,\r\n        \"file_name_without_extension\": file_name_without_extension,\r\n        \"file_name_without_path\": file_name_without_path\r\n    }\r\n\r\ndef clear_bit(byte_value, byte_bit):\r\n    mask = ~(1 << byte_bit)  # 创建一个掩码，将特定位设置为0\r\n    result = byte_value & mask  # 将特定位设置为0\r\n    return result\r\n\r\n\r\ndef set_bit(byte_value, byte_bit):\r\n    mask = 1 << byte_bit  # 创建一个掩码，将特定位设置为1\r\n    result = byte_value | mask  # 将特定位设置为1\r\n    return result\r\n\r\n\r\n# 创建一个回调函数来获取鼠标事件的坐标和操作\r\ndef get_mouse_event(event, x, y, flags, param):\r\n    global output_image\r\n\r\n    if event == cv2.EVENT_LBUTTONDOWN:  # 左键点击\r\n        # 计算在原始图像中的坐标\r\n        original_x = x // scale_factor\r\n        original_y = y // scale_factor\r\n\r\n        # 反转点击位置的像素\r\n        if 0 <= original_x < image.shape[1] and 0 <= original_y < image.shape[0]:\r\n            if image[original_y, original_x] == 0:  # 如果是黑色像素，变为白色\r\n                image[original_y, original_x] = 255\r\n            else:  # 如果是白色像素，变为黑色\r\n                image[original_y, original_x] = 0\r\n\r\n        # 更新放大图像\r\n        scaled_img = cv2.resize(image, (0, 0), fx=scale_factor, fy=scale_factor, interpolation=cv2.INTER_NEAREST)\r\n        cv2.imshow('Scaled Image', scaled_img)\r\n\r\n\r\ndef on_space_pressed():\r\n    global output_image\r\n    output_image = True\r\n\r\n\r\n# 获取图像路径输入\r\n\r\n# 读取图像\r\n#image_path = arguments\r\ncv2.imdecode(np.fromfile(arguments, dtype=np.uint8), cv2.IMREAD_UNCHANGED)\r\n# image_path= os.path.abspath(os.path.realpath(arguments)).encode('utf-8').decode('utf-8')\r\n# print(image_path)\r\nimage = cv2.imread(image_path, 0)  # 以灰度模式读取图像\r\n\r\nif image is None:\r\n    print(f\"Error: Couldn't read the image from path: {image_path}\")\r\n    sys.exit(1)  # Exit the script with an error code\r\nimage2=image.copy()\r\nif image is None:\r\n    print(\"Error: Couldn't read the image.\")\r\nelse:\r\n    result = process_file_path(image_path)\r\n\r\n    filename = result[\"file_name_without_path\"]\r\n    # 创建放大图像\r\n    scaled_image = cv2.resize(image, (0, 0), fx=scale_factor, fy=scale_factor, interpolation=cv2.INTER_NEAREST)\r\n\r\n    # 创建窗口并将回调函数与窗口绑定\r\n    cv2.namedWindow('Scaled Image')\r\n    cv2.setMouseCallback('Scaled Image', get_mouse_event)\r\n\r\n    # 显示放大后的图像\r\n    cv2.imshow('Scaled Image', scaled_image)\r\n\r\n    while True:\r\n        key = cv2.waitKey(1)\r\n        if key == ord(' '):  # 当按下空格键时\r\n            cv2.imwrite(image_path, image)\r\n            _, image = cv2.threshold(image, 127, 255, cv2.THRESH_BINARY)\r\n            height, width = image.shape\r\n            byte_value = 0\r\n            byte_bit = 0\r\n            print(\"{\",end=\"\")\r\n\r\n            for i in range(math.ceil(height / 8)* width) :\r\n                if i  >= height // 8*width :\r\n                    now_height = height - math.floor(height / 8) * 8\r\n                else:\r\n                    now_height = 8\r\n                now_col = i % width\r\n\r\n                for j in range(now_height):\r\n                    if j + i // width*8==10:\r\n                        print(i,j,now_height)\r\n                    if image[j + i // width*8,now_col] == 255:\r\n                        byte_value= set_bit(byte_value, byte_bit)\r\n                    else:\r\n                        byte_value=  clear_bit(byte_value, byte_bit)\r\n                    byte_bit = byte_bit + 1\r\n                    if byte_bit == 8:\r\n                        byte_bit = 0\r\n                        print(\"0x\",end=\"\")\r\n                        print(hex(byte_value)[2:].zfill(2),end=\",\")  # 输出两位十六进\r\n            if byte_bit % 8 != 0:\r\n                print(hex(byte_value)[2:].zfill(2),end=\"},/*\")  # 输出两位十六进\r\n            else:\r\n                print(\"\",end=\"},/*\")  # 输出两位十六进\r\n            print(filename,end=\"*/\\n\")\r\n            break\r\n        elif key == 27:  # 按下ESC键退出\r\n            break\r\n        elif  key == ord('B') or key == ord('b'):\r\n            image=image2.copy()\r\n\r\n            scaled_img = cv2.resize(image, (0, 0), fx=scale_factor, fy=scale_factor, interpolation=cv2.INTER_NEAREST)\r\n            cv2.imshow('Scaled Image', scaled_img)\r\n    cv2.destroyAllWindows()\r\n"
  },
  {
    "path": "uv-k5font/font-pixel-made/text.py",
    "content": "扩储恢条最即解段低切\r\n键\r\n\r\n"
  },
  {
    "path": "uv-k5font/font.cpp",
    "content": "//\r\n// Created by RUPC on 2023/11/17.\r\n//\r\n\r\n#include \"font.h\"\r\n\r\nunsigned char chn_font[CHAR_NUM][14] = {\r\n        {0x77, 0xb7, 0xd1, 0xf7, 0xf7, 0x80, 0x75, 0xb5, 0xd5, 0xf7, 0xff, 0x57, 0xf9, 0xff},/*步*/\r\n        {0xf6, 0x05, 0xff, 0x6b, 0xab, 0xc0, 0xeb, 0x00, 0xeb, 0xeb, 0xff, 0x59, 0x55, 0x75},/*进*/\r\n        {0xb1, 0xd7, 0x80, 0x75, 0x95, 0xff, 0x82, 0xf8, 0x02, 0xfa, 0x82, 0xe5, 0x9f, 0x9b},/*频*/\r\n        {0x7d, 0x55, 0x6d, 0x3d, 0x0c, 0x0d, 0x3d, 0x6d, 0x55, 0x7d, 0xff, 0xff, 0xfc, 0xff},/*率*/\r\n        {0xdb, 0x00, 0xeb, 0xff, 0xd5, 0x11, 0xc4, 0x55, 0x91, 0xd5, 0xff, 0x71, 0xa5, 0xb5},/*接*/\r\n        {0x01, 0x7f, 0xbf, 0x00, 0xff, 0xf7, 0xfb, 0xc4, 0x3d, 0x81, 0xfd, 0x3f, 0x5f, 0x5a},/*收*/\r\n        {0xaa, 0x31, 0x93, 0xa0, 0xb1, 0x2a, 0xf7, 0x80, 0x7b, 0x83, 0xfb, 0xa5, 0x96, 0x9b},/*数*/\r\n        {0xb1, 0xbd, 0xb5, 0xb5, 0xb5, 0x14, 0xa5, 0xbd, 0xbd, 0xb1, 0xff, 0x7f, 0xf1, 0xff},/*字*/\r\n        {0xe6, 0x9e, 0xfe, 0x00, 0xfe, 0xfe, 0x00, 0xfe, 0x9e, 0xe6, 0xff, 0x15, 0x45, 0x75},/*亚*/\r\n        {0xf7, 0xf5, 0x11, 0x51, 0x54, 0x55, 0x51, 0x11, 0xf5, 0xf7, 0xff, 0x4f, 0x15, 0x3f},/*音*/\r\n        {0xbb, 0xcb, 0x00, 0xeb, 0xbf, 0x85, 0xa0, 0x25, 0x90, 0x85, 0xbf, 0xcf, 0xe5, 0xd6},/*模*/\r\n        {0xdb, 0x00, 0xeb, 0xff, 0x01, 0xbf, 0xdd, 0x73, 0x3f, 0xc0, 0xff, 0xf1, 0xe7, 0xdb},/*拟*/\r\n        {0xfb, 0x78, 0x9b, 0xe3, 0xf8, 0xcb, 0x2b, 0xaa, 0xca, 0xfd, 0xfb, 0x79, 0xa9, 0x96},/*发*/\r\n        {0xf6, 0x05, 0xff, 0x6b, 0x6a, 0x81, 0xa9, 0x6a, 0x6b, 0xff, 0xff, 0x59, 0x55, 0x75},/*送*/\r\n        {0xed, 0x65, 0x85, 0xe4, 0xa1, 0xa5, 0x24, 0xa5, 0xa5, 0xed, 0xed, 0x5e, 0x45, 0x75},/*差*/\r\n        {0xfb, 0xfb, 0xfb, 0x7b, 0x82, 0xeb, 0xeb, 0xeb, 0xeb, 0x0b, 0xfb, 0xe5, 0x5f, 0x79},/*方*/\r\n        {0x01, 0xfd, 0xfd, 0x05, 0x74, 0x75, 0x05, 0xfd, 0xfd, 0x01, 0xff, 0xfc, 0x7f, 0x71},/*向*/\r\n        {0xfb, 0x7b, 0x80, 0xfb, 0xfb, 0x03, 0xff, 0x01, 0xfd, 0xfd, 0x01, 0x79, 0xb9, 0xaa},/*加*/\r\n        {0xc9, 0x55, 0xed, 0xc5, 0xc9, 0x44, 0xd9, 0xcd, 0x75, 0xe9, 0xff, 0x53, 0x51, 0x7c},/*密*/\r\n        {0xf6, 0x05, 0xff, 0x10, 0xd2, 0x52, 0x00, 0x52, 0xd2, 0x10, 0xff, 0x59, 0x55, 0x75},/*遇*/\r\n        {0xe3, 0xff, 0x00, 0xf7, 0xff, 0xfb, 0x03, 0xf8, 0xfb, 0xfb, 0xfb, 0xcf, 0x4f, 0x55},/*忙*/\r\n        {0xb5, 0xa9, 0xa0, 0xa9, 0xa5, 0x2f, 0xa5, 0xa9, 0xa0, 0xa9, 0xb5, 0xe5, 0xf1, 0xd6},/*禁*/\r\n        {0xff, 0x00, 0xfe, 0xee, 0xee, 0x02, 0xee, 0xae, 0x6e, 0xfe, 0xff, 0x59, 0x51, 0x75},/*压*/\r\n        {0xed, 0x00, 0xf5, 0xff, 0x07, 0xfb, 0xfb, 0xfa, 0xfb, 0xfb, 0xff, 0x73, 0xfe, 0xff},/*扩*/\r\n        {0xdd, 0xed, 0x05, 0xf9, 0xbc, 0xb5, 0xb5, 0x15, 0xa5, 0xbd, 0xfd, 0xcf, 0x1f, 0x3f},/*存*/\r\n        {0xf4, 0xf2, 0x12, 0x94, 0x02, 0x52, 0xd4, 0x12, 0xf2, 0xf4, 0xff, 0x45, 0x01, 0x35},/*置*/\r\n        {0xf7, 0x03, 0xfc, 0xff, 0x7d, 0x55, 0x54, 0x55, 0x55, 0x7d, 0xff, 0xf3, 0x54, 0x71},/*信*/\r\n        {0xf6, 0x05, 0xff, 0xfd, 0x05, 0x24, 0xa9, 0x24, 0x05, 0xfd, 0xff, 0x59, 0x55, 0x75},/*道*/\r\n        {0x00, 0xee, 0x00, 0xef, 0x00, 0xee, 0x00, 0xff, 0x81, 0xff, 0x00, 0xce, 0xce, 0xc7},/*删*/\r\n        {0x00, 0x7e, 0x00, 0xff, 0xfb, 0x5d, 0xd6, 0x06, 0xd6, 0x55, 0xfb, 0xfc, 0x1e, 0x2f},/*除*/\r\n        {0xf7, 0x17, 0xdb, 0x15, 0xf5, 0x16, 0xd5, 0xd5, 0x1b, 0xf7, 0xf7, 0xab, 0xb3, 0xbe},/*命*/\r\n        {0xff, 0x7b, 0x2b, 0xdd, 0x0c, 0xc5, 0xd5, 0xd5, 0xd9, 0xdf, 0x1f, 0xfe, 0x54, 0x45},/*名*/\r\n        {0xdb, 0x00, 0xeb, 0xff, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x00, 0xf1, 0x55, 0x45},/*扫*/\r\n        {0xdb, 0x00, 0xeb, 0xff, 0x05, 0xb5, 0xb0, 0x05, 0xb5, 0xb0, 0x05, 0xf1, 0x14, 0x05},/*描*/\r\n        {0xde, 0xe6, 0xf0, 0xd6, 0x06, 0xff, 0x83, 0xff, 0xff, 0x00, 0xff, 0x97, 0x7f, 0x71},/*列*/\r\n        {0xdf, 0xd5, 0x55, 0x55, 0x95, 0xc0, 0x95, 0x55, 0xd5, 0x55, 0xdf, 0x3b, 0xf9, 0xd6},/*表*/\r\n        {0xdb, 0x00, 0xeb, 0xff, 0xe1, 0xa5, 0x2f, 0x80, 0xaf, 0x25, 0xa1, 0xf1, 0x85, 0x96},/*搜*/\r\n        {0xe7, 0x75, 0x55, 0x55, 0x25, 0x20, 0x55, 0x65, 0x75, 0xf5, 0xe7, 0xe5, 0xbc, 0xb5},/*索*/\r\n        {0xf7, 0x03, 0xfc, 0xb3, 0xdf, 0xe5, 0x99, 0xbc, 0x05, 0xdd, 0xed, 0xf3, 0x97, 0x9b},/*恢*/\r\n        {0x7b, 0x7c, 0xa1, 0x05, 0xa5, 0xa5, 0xa5, 0x25, 0xa1, 0xfd, 0xff, 0x55, 0x6a, 0x75},/*复*/\r\n        {0xeb, 0xeb, 0x0b, 0xeb, 0xeb, 0xeb, 0xfb, 0xc0, 0x3b, 0xfa, 0x79, 0x45, 0xfa, 0xcb},/*式*/\r\n        {0xf7, 0x15, 0xf5, 0x00, 0xb5, 0xb5, 0xff, 0x0c, 0x6e, 0x6a, 0x08, 0xac, 0x55, 0x55},/*超*/\r\n        {0x01, 0xed, 0xed, 0x01, 0xff, 0xfb, 0xeb, 0x9b, 0xfb, 0x00, 0xfb, 0xaa, 0x7f, 0x71},/*时*/\r\n        {0xeb, 0xed, 0x0e, 0x57, 0x57, 0x50, 0x57, 0x52, 0x05, 0xfb, 0xff, 0x4f, 0x55, 0x7c},/*省*/\r\n        {0x81, 0xb5, 0xb5, 0xb5, 0x00, 0xb5, 0xb5, 0xb5, 0x81, 0xff, 0x7f, 0xff, 0x54, 0x45},/*电*/\r\n        {0xef, 0x6d, 0x65, 0x25, 0x85, 0xa0, 0xa5, 0x25, 0xa5, 0xed, 0xef, 0x55, 0x6a, 0x55},/*麦*/\r\n        {0xfd, 0xfd, 0xc5, 0xd5, 0x15, 0xd0, 0x15, 0xd5, 0xc5, 0xfd, 0x7d, 0x95, 0x6f, 0x45},/*克*/\r\n        {0xff, 0x00, 0xfe, 0x7a, 0xb6, 0xce, 0xb6, 0x7a, 0xfe, 0x00, 0xff, 0xf9, 0xff, 0xcb},/*风*/\r\n        {0x77, 0x01, 0x77, 0xff, 0xe1, 0x04, 0xad, 0x21, 0x4c, 0x05, 0xe1, 0xff, 0x43, 0x71},/*增*/\r\n        {0xed, 0x2d, 0xb4, 0x35, 0xbd, 0xbd, 0x35, 0xb4, 0x2d, 0xed, 0xff, 0x11, 0x45, 0x74},/*益*/\r\n        {0xdf, 0xa0, 0x6a, 0x0a, 0xea, 0xea, 0x0a, 0x6a, 0xa0, 0xdf, 0xff, 0x15, 0x45, 0x75},/*显*/\r\n        {0xf7, 0x76, 0x96, 0xf6, 0xf6, 0x06, 0xf6, 0xf6, 0xd6, 0xb7, 0x77, 0x7e, 0xf1, 0xef},/*示*/\r\n        {0xff, 0x01, 0xad, 0xad, 0xad, 0xac, 0xad, 0xad, 0x01, 0xff, 0xff, 0x53, 0x55, 0x7c},/*自*/\r\n        {0x77, 0x95, 0xe5, 0x75, 0x35, 0xff, 0xfb, 0x7b, 0x80, 0xfb, 0x03, 0xea, 0x9e, 0xa7},/*动*/\r\n        {0xed, 0xf5, 0xf0, 0x0f, 0xaf, 0xaf, 0xaf, 0x10, 0xed, 0xee, 0xf7, 0x3f, 0x2a, 0x3f},/*背*/\r\n        {0xef, 0xed, 0xeb, 0x27, 0xcf, 0xe0, 0x0f, 0xe7, 0xeb, 0xed, 0x6f, 0xe5, 0x4f, 0x45},/*光*/\r\n        {0xcd, 0xed, 0xe9, 0x25, 0xe4, 0xe5, 0x25, 0xe9, 0xed, 0xcd, 0xff, 0xe5, 0x4f, 0x71},/*亮*/\r\n        {0xff, 0x01, 0xf5, 0xb5, 0x21, 0xa4, 0xa5, 0x21, 0xb5, 0xfd, 0xff, 0x59, 0x69, 0x75},/*度*/\r\n        {0xff, 0xfd, 0x05, 0x54, 0x55, 0x51, 0x55, 0x54, 0x05, 0xfd, 0xff, 0x4f, 0x55, 0x7c},/*首*/\r\n        {0xff, 0x00, 0xfa, 0x5a, 0x4a, 0x4a, 0x0a, 0xa2, 0xaa, 0xba, 0xb8, 0xf9, 0x4f, 0x45},/*尾*/\r\n        {0xfb, 0x36, 0xfd, 0xff, 0x06, 0x55, 0x50, 0x57, 0x53, 0x05, 0xfe, 0xfc, 0xfc, 0xf1},/*消*/\r\n        {0xf6, 0x05, 0xff, 0xfb, 0xeb, 0x4b, 0x7b, 0x00, 0xfb, 0xfb, 0xff, 0x59, 0x55, 0x55},/*过*/\r\n        {0xc3, 0xdb, 0xdb, 0xdb, 0xdb, 0x00, 0xdb, 0xdb, 0xdb, 0xdb, 0xc3, 0xff, 0xf3, 0xff},/*中*/\r\n        {0x93, 0xac, 0xb7, 0xff, 0x00, 0xff, 0x29, 0xc7, 0x01, 0xc7, 0x29, 0xe5, 0x54, 0x55},/*继*/\r\n        {0xdb, 0x00, 0xeb, 0xff, 0xe9, 0xad, 0x44, 0x6d, 0x8d, 0xe9, 0xff, 0xf1, 0x95, 0x95},/*按*/\r\n        {0xd3, 0x04, 0xd5, 0xfb, 0x06, 0xff, 0xd5, 0x55, 0x00, 0x55, 0xc1, 0xd3, 0x54, 0x54},/*键*/\r\n        {0x00, 0xea, 0xaa, 0x60, 0xff, 0xff, 0x00, 0xbe, 0x7e, 0x80, 0xff, 0xe4, 0xce, 0xff},/*即*/\r\n        {0x01, 0x7d, 0x01, 0xff, 0xdb, 0xd9, 0xd5, 0x00, 0xde, 0xd6, 0xdb, 0xff, 0x1f, 0x3f},/*呼*/\r\n        {0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xf7, 0xf7, 0xf7, 0xff, 0xff, 0x55, 0x51, 0x55},/*上*/\r\n        {0xa7, 0x8b, 0xac, 0xb7, 0xff, 0xd7, 0xd7, 0x80, 0x6b, 0x6a, 0xa9, 0xa5, 0x97, 0x86},/*线*/\r\n        {0xf6, 0x02, 0xf4, 0x06, 0xff, 0x7e, 0x60, 0x6e, 0xe0, 0x0f, 0xff, 0xab, 0x5f, 0x79},/*码*/\r\n        {0xfe, 0xfe, 0xfe, 0xfe, 0x00, 0xfe, 0xf6, 0xee, 0xde, 0xfe, 0xff, 0xff, 0xfc, 0xff},/*下*/\r\n        {0x01, 0xfe, 0x81, 0xfd, 0x05, 0xfd, 0x81, 0xff, 0x81, 0xff, 0x00, 0x9c, 0xdb, 0xc5},/*侧*/\r\n        {0x01, 0x7d, 0x01, 0xff, 0x03, 0xfb, 0x09, 0x6a, 0x0b, 0xfb, 0x03, 0xff, 0xfc, 0xc7},/*响*/\r\n        {0xff, 0x01, 0xfd, 0xed, 0x9d, 0xf5, 0xcc, 0x3d, 0xc5, 0xfd, 0xff, 0x59, 0x15, 0x35},/*应*/\r\n        {0xf7, 0x03, 0xfc, 0xfb, 0xc3, 0x3b, 0xfa, 0xf9, 0x3b, 0xc3, 0xfb, 0x73, 0x15, 0x15},/*位*/\r\n        {0xf6, 0xf2, 0x02, 0xb4, 0xc6, 0xff, 0x82, 0xfa, 0x00, 0xfa, 0x82, 0xc6, 0x9f, 0x9b},/*预*/\r\n        {0xd7, 0x85, 0xa5, 0x00, 0xa5, 0x95, 0xf7, 0xc0, 0x37, 0xd6, 0x65, 0x2a, 0x9a, 0x8b},/*载*/\r\n        {0xff, 0x36, 0xed, 0xff, 0x03, 0xf9, 0xcd, 0xad, 0x60, 0xad, 0xc9, 0x7c, 0x9e, 0x9b},/*波*/\r\n        {0xfe, 0x00, 0x5a, 0x00, 0xbf, 0xff, 0xda, 0xd9, 0x03, 0xd9, 0xda, 0x3e, 0x9f, 0x9b},/*联*/\r\n        {0xdf, 0xdd, 0x45, 0xc5, 0xc9, 0x0d, 0xd5, 0x5a, 0xee, 0xdf, 0xff, 0xfa, 0xf1, 0xfa},/*系*/\r\n        {0xff, 0xff, 0x7f, 0x9f, 0xe7, 0xf8, 0xe7, 0x1f, 0xff, 0xff, 0xff, 0xf9, 0xff, 0xf6},/*人*/\r\n        {0xed, 0x09, 0xa0, 0xa9, 0x0d, 0xef, 0xab, 0xa8, 0x01, 0xab, 0x83, 0xa3, 0x7c, 0x7c},/*静*/\r\n        {0x01, 0x7d, 0x01, 0xff, 0x63, 0x6b, 0x60, 0x3a, 0x60, 0x6b, 0x63, 0x7f, 0x39, 0x1b},/*噪*/\r\n        {0xbb, 0xac, 0xa9, 0x25, 0xad, 0xab, 0xac, 0x85, 0x2d, 0xa9, 0xa5, 0xff, 0x5e, 0x7c},/*等*/\r\n        {0x93, 0xa4, 0xbf, 0xff, 0xff, 0x7e, 0x80, 0xbe, 0x76, 0xb0, 0xc7, 0xe5, 0x99, 0x9b},/*级*/\r\n        {0xff, 0x01, 0xd5, 0x7e, 0xf7, 0xd9, 0xae, 0x6e, 0xae, 0xd9, 0xf7, 0xe2, 0xe7, 0xf6},/*段*/\r\n        {0x0b, 0x55, 0x04, 0x55, 0x09, 0xff, 0xb6, 0x98, 0x0e, 0xb6, 0xf0, 0x6e, 0xac, 0xa8},/*解*/\r\n        {0xb3, 0x04, 0xb5, 0xff, 0x86, 0xf5, 0x77, 0x90, 0x77, 0xf5, 0x86, 0xe3, 0xf9, 0xdb},/*锁*/\r\n        {0xbf, 0x81, 0x34, 0xad, 0x01, 0xff, 0xfb, 0x9b, 0xfb, 0x00, 0xfb, 0x79, 0x7c, 0x71},/*射*/\r\n        {0xf7, 0x2e, 0xfd, 0xff, 0xef, 0x01, 0xf7, 0x80, 0xf7, 0xdb, 0x43, 0xfc, 0x53, 0x45},/*池*/\r\n        {0xf6, 0x05, 0xff, 0xff, 0x00, 0xfe, 0x1a, 0x40, 0x1a, 0xfe, 0x00, 0x93, 0xfe, 0xc5},/*调*/\r\n        {0xfb, 0xfb, 0x7b, 0x9b, 0xe0, 0xdb, 0xbb, 0x7b, 0xfb, 0xfb, 0xff, 0xe5, 0xbf, 0xb5},/*大*/\r\n        {0xbf, 0xcf, 0xf3, 0xff, 0xff, 0x00, 0xff, 0xff, 0xfb, 0xe7, 0x9f, 0x7f, 0xf1, 0xff},/*小*/\r\n        {0xaf, 0xab, 0x49, 0x6a, 0x43, 0x8b, 0xab, 0x4d, 0xab, 0xaf, 0xff, 0x57, 0xe9, 0xff},/*参*/\r\n        {0xf7, 0x03, 0xfc, 0xff, 0x01, 0x55, 0x15, 0x54, 0x15, 0x55, 0x11, 0x73, 0xcc, 0xcc},/*偏*/\r\n        {0x6d, 0x8d, 0x01, 0xae, 0x7f, 0xab, 0x45, 0xcc, 0xcd, 0x55, 0x99, 0xcf, 0x95, 0xbe},/*移*/\r\n        {0xdf, 0xdb, 0xda, 0x59, 0x83, 0x9b, 0x59, 0xda, 0xdb, 0xdf, 0xff, 0xe5, 0xbf, 0xb5},/*关*/\r\n        {0x06, 0xfd, 0x6f, 0x6e, 0xae, 0x02, 0xee, 0xee, 0xee, 0xfe, 0x00, 0xfc, 0xf1, 0xc7},/*闭*/\r\n        {0xef, 0xee, 0x6e, 0x80, 0xee, 0xee, 0xee, 0x00, 0xee, 0xee, 0xef, 0xe7, 0x3f, 0x3f},/*开*/\r\n        {0xff, 0x7f, 0x81, 0x15, 0xd5, 0xd5, 0xd4, 0xd5, 0xd5, 0x11, 0xff, 0x39, 0x55, 0x71},/*启*/\r\n        {0x75, 0x95, 0x01, 0xb6, 0xff, 0xe3, 0xff, 0xc0, 0x7f, 0xbb, 0xd7, 0xcf, 0xa7, 0xbf},/*秒*/\r\n        {0xef, 0xf7, 0xeb, 0x6c, 0x8f, 0xef, 0xec, 0x0b, 0xf7, 0xef, 0xff, 0xe5, 0x9f, 0xbf},/*分*/\r\n        {0xff, 0xfb, 0xdb, 0xdb, 0xda, 0x01, 0xdb, 0xdb, 0xdb, 0xfb, 0xff, 0x57, 0x51, 0x75},/*主*/\r\n        {0xf8, 0x66, 0x9e, 0x66, 0xf8, 0xff, 0xf8, 0x66, 0x9e, 0x66, 0xf8, 0xb9, 0x9d, 0x9b},/*双*/\r\n        {0x1e, 0x52, 0x56, 0x12, 0x5a, 0x52, 0x1e, 0xff, 0x83, 0xff, 0x00, 0x14, 0xc5, 0xc5},/*副*/\r\n        {0xdf, 0xdf, 0xd0, 0x16, 0x56, 0x56, 0x56, 0x50, 0x5f, 0xdf, 0xff, 0xff, 0x57, 0x7e},/*号*/\r\n        {0xff, 0x01, 0xf5, 0x15, 0xd5, 0xd5, 0xd6, 0xd6, 0x16, 0xf7, 0xff, 0x39, 0x55, 0x7c},/*后*/\r\n        {0xf7, 0x03, 0xfc, 0xff, 0xcd, 0xad, 0xa9, 0x28, 0xa9, 0xad, 0xcd, 0xf3, 0x17, 0x3f},/*停*/\r\n        {0xff, 0xff, 0x07, 0xff, 0xff, 0x00, 0xf7, 0xf7, 0xf7, 0xff, 0xff, 0x45, 0x51, 0x55},/*止*/\r\n        {0x75, 0x95, 0x01, 0xd6, 0x7e, 0x93, 0xfc, 0x01, 0xfd, 0xcd, 0x39, 0xcf, 0x1f, 0x3f},/*称*/\r\n        {0xde, 0xde, 0xee, 0xf6, 0x02, 0xfc, 0xf6, 0xee, 0xde, 0xbe, 0xff, 0xff, 0xfc, 0xff},/*不*/\r\n        {0x7b, 0xbb, 0x5b, 0x63, 0x7b, 0x00, 0x7b, 0x63, 0x5b, 0xbb, 0x7b, 0xff, 0xf3, 0xff},/*本*/\r\n        {0xf7, 0x00, 0xb7, 0xff, 0xdf, 0x01, 0xef, 0x80, 0xd7, 0xb7, 0x87, 0xfe, 0x53, 0x45},/*地*/\r\n        {0xd3, 0x04, 0xd5, 0xff, 0xd7, 0x5b, 0x5d, 0x56, 0x5d, 0x5b, 0xd7, 0xd3, 0x5f, 0x7e},/*铃*/\r\n        {0x00, 0xfe, 0xfe, 0x86, 0xb6, 0xb6, 0x86, 0xfe, 0xfe, 0x00, 0xff, 0x54, 0x55, 0x71},/*回*/\r\n        {0xf7, 0xfb, 0xbb, 0xb5, 0xb5, 0x06, 0xb5, 0xb5, 0xbb, 0xfb, 0xf7, 0x57, 0x51, 0x75},/*全*/\r\n        {0xef, 0x2d, 0xa5, 0xac, 0xa5, 0x2d, 0xef, 0x00, 0x76, 0x76, 0x88, 0x53, 0x31, 0x3f},/*部*/\r\n        {0xff, 0x00, 0xb6, 0xb6, 0xb6, 0x00, 0xb6, 0xb6, 0xb6, 0x00, 0xff, 0xf9, 0xf3, 0xf1},/*用*/\r\n        {0xfb, 0x01, 0xfe, 0x06, 0xdb, 0xdd, 0xdd, 0x01, 0xdd, 0xde, 0xff, 0xb3, 0xd9, 0xe6},/*低*/\r\n        {0xef, 0xef, 0x00, 0xef, 0xe7, 0xab, 0x6d, 0xee, 0xef, 0xef, 0xff, 0x4f, 0xbe, 0xb5},/*长*/\r\n        {0x0d, 0xed, 0xe9, 0x25, 0xa5, 0xa4, 0x25, 0xe9, 0xed, 0x0d, 0xff, 0xbc, 0xea, 0xf1},/*高*/\r\n\r\n\r\n};\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n"
  },
  {
    "path": "uv-k5font/font.h",
    "content": "//\r\n// Created by RUPC on 2023/11/17.\r\n//\r\n\r\n#ifndef UV_K5FONT_FONT_H\r\n#define UV_K5FONT_FONT_H\r\n#include \"bits/stdc++.h\"\r\n#define SUM_BYTE 1678\r\n#define CHAR_NUM 122\r\nextern unsigned char chn_font[CHAR_NUM][14]  ;\r\n\r\n#endif //UV_K5FONT_FONT_H\r\n"
  },
  {
    "path": "uv-k5font/font_new/chinese_array.txt",
    "content": ""
  },
  {
    "path": "uv-k5font/font_new/font.cpp",
    "content": "//\n// Created by RUPC on 2023/12/17.\n//\n#include \"font.h\"\n\nunsigned char new_font[CHN_FONT_NUM][22] = {{0x20,0x20,0x3E,0xA0,0x20,0xBF,0x24,0x24,0x24,0xA4,0x20,0x00,0x0A,0x09,0x08,0x04,\n0x07,0x02,0x02,0x01,0x00,0x00,}/*\"步\",0*/,{\n\n0x10,0x11,0xF2,0x40,0x44,0xFF,0x44,0x44,0xFF,0x44,0x40,0x08,0x04,0x03,0x04,0x0A,\n0x09,0x08,0x08,0x0B,0x08,0x08,}/*\"进\",1*/,{\n\n0x10,0xDE,0x10,0xFF,0x12,0x92,0xF9,0x0D,0xEB,0x09,0xF9,0x09,0x08,0x04,0x02,0x01,\n0x00,0x09,0x04,0x03,0x04,0x09,}/*\"频\",2*/,{\n\n0x02,0x8A,0x52,0x9A,0xD6,0xB3,0xD2,0x8A,0x52,0x8A,0x02,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,}/*\"率\",3*/,{\n\n0x88,0x88,0xFF,0x48,0xA4,0xAC,0xB5,0xE6,0xB4,0xAC,0xA4,0x00,0x08,0x0F,0x00,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,}/*\"接\",4*/,{\n\n0xFE,0x00,0x80,0xFF,0x20,0x10,0xEF,0x08,0x88,0x78,0x08,0x03,0x01,0x00,0x0F,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,}/*\"收\",5*/,{\n\n0x48,0x2A,0x98,0x7F,0x28,0x4A,0x10,0xEF,0x08,0xF8,0x08,0x09,0x0B,0x05,0x05,0x0B,\n0x00,0x08,0x05,0x02,0x05,0x08,}/*\"数\",6*/,{\n\n0x0C,0x04,0x24,0x24,0x25,0x26,0xA4,0x64,0x24,0x04,0x0C,0x01,0x01,0x01,0x09,0x09,\n0x0F,0x01,0x01,0x01,0x01,0x01,}/*\"字\",7*/,{\n\n0x20,0x42,0x82,0xFE,0x02,0x02,0x02,0xFE,0x82,0x42,0x20,0x08,0x08,0x08,0x0F,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,}/*\"亚\",8*/,{\n\n0x10,0xD2,0x56,0x5A,0x52,0x53,0x52,0x5A,0x56,0xD2,0x10,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,}/*\"音\",9*/,{\n\n0x88,0x68,0xFF,0x48,0x02,0xFA,0xAF,0xAA,0xAF,0xFA,0x02,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,}/*\"模\",10*/,{\n\n0x88,0xFF,0x48,0x00,0xFE,0x00,0x82,0x0C,0xE0,0x1F,0x00,0x08,0x0F,0x00,0x00,0x03,\n0x09,0x04,0x03,0x00,0x03,0x0C,}/*\"拟\",11*/,{\n\n0x0E,0x08,0x88,0x78,0xCF,0x48,0x48,0x49,0xCA,0x08,0x08,0x04,0x02,0x09,0x08,0x04,\n0x05,0x02,0x05,0x04,0x08,0x08,}/*\"发\",12*/,{\n\n0x11,0xF2,0x40,0x48,0x49,0x4A,0xF8,0x4A,0x49,0x48,0x40,0x08,0x07,0x08,0x0C,0x0A,\n0x09,0x08,0x09,0x0A,0x0C,0x08,}/*\"送\",13*/,{\n\n0x44,0x54,0x55,0xD6,0x74,0x5C,0x54,0x56,0x55,0x54,0x44,0x04,0x02,0x09,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x08,}/*\"差\",14*/,{\n\n0x04,0x04,0x04,0xFC,0x25,0x26,0x24,0x24,0x24,0xE4,0x04,0x08,0x04,0x03,0x00,0x00,\n0x00,0x08,0x08,0x08,0x07,0x00,}/*\"方\",15*/,{\n\n0xFC,0x04,0x04,0xE6,0x25,0x24,0x24,0xE4,0x04,0x04,0xFC,0x0F,0x00,0x00,0x03,0x02,\n0x02,0x02,0x03,0x08,0x08,0x0F,}/*\"向\",16*/,{\n\n0x08,0x08,0xFF,0x08,0x08,0xF8,0x00,0xFC,0x04,0x04,0xFC,0x08,0x06,0x01,0x08,0x08,\n0x07,0x00,0x0F,0x04,0x04,0x0F,}/*\"加\",17*/,{\n\n0x46,0x32,0x82,0xB2,0x46,0x6B,0x52,0x4A,0x62,0x12,0x66,0x00,0x0E,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0E,0x00,}/*\"密\",18*/,{\n\n0x21,0xE2,0x00,0xC0,0x5F,0x55,0xFF,0x55,0xD5,0x5F,0xC0,0x08,0x07,0x08,0x0B,0x08,\n0x09,0x09,0x09,0x09,0x0A,0x0B,}/*\"遇\",19*/,{\n\n0x78,0x00,0xFF,0x04,0x08,0xF8,0x09,0x0A,0x08,0x08,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x08,0x08,0x08,0x08,0x00,}/*\"忙\",20*/,{\n\n0x12,0x4A,0x7F,0x4A,0x52,0x40,0x52,0x4A,0x7F,0x4A,0x12,0x01,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x01,}/*\"禁\",21*/,{\n\n0x00,0xFE,0x02,0x42,0x42,0x42,0xFA,0x42,0x42,0x42,0x02,0x08,0x07,0x08,0x08,0x08,\n0x08,0x0F,0x08,0x09,0x0A,0x08,}/*\"压\",22*/,{\n\n0x88,0x88,0xFF,0x48,0x00,0xFC,0x04,0x05,0x06,0x04,0x04,0x00,0x08,0x0F,0x00,0x08,\n0x07,0x00,0x00,0x00,0x00,0x00,}/*\"扩\",23*/,{\n\n0x84,0x44,0xF4,0x0C,0x87,0x94,0x94,0xD4,0xB4,0x94,0x84,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x08,0x0F,0x00,0x00,0x00,}/*\"存\",24*/,{\n\n0x10,0x17,0xD5,0x55,0x57,0x7D,0x57,0x55,0xD5,0x17,0x10,0x08,0x08,0x0F,0x08,0x08,\n0x0E,0x08,0x08,0x0F,0x08,0x08,}/*\"置\",25*/,{\n\n0x10,0xFC,0x03,0x04,0x54,0x54,0x55,0x56,0x54,0x54,0x04,0x00,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,}/*\"信\",26*/,{\n\n0x10,0x11,0xF2,0x00,0xFA,0xAB,0xAE,0xAA,0xAA,0xAB,0xFA,0x08,0x04,0x03,0x04,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0A,0x0B,}/*\"道\",27*/,{\n\n0xFE,0x22,0xFE,0x20,0xFE,0x22,0xFE,0x20,0xFC,0x00,0xFF,0x07,0x08,0x0F,0x00,0x07,\n0x08,0x0F,0x00,0x01,0x08,0x0F,}/*\"删\",28*/,{\n\n0xFE,0x32,0xCE,0x00,0x48,0x54,0x52,0xF1,0x52,0x54,0x48,0x0F,0x02,0x01,0x04,0x02,\n0x01,0x08,0x0F,0x00,0x01,0x06,}/*\"除\",29*/,{\n\n0x10,0xD0,0x48,0x54,0xD2,0x11,0xD2,0x54,0x48,0xD0,0x10,0x00,0x07,0x02,0x02,0x07,\n0x00,0x0F,0x00,0x04,0x07,0x00,}/*\"命\",30*/,{\n\n0x00,0x10,0x88,0x94,0xE7,0xC4,0xA4,0xA4,0x94,0x8C,0x80,0x01,0x01,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,}/*\"名\",31*/,{\n\n0x88,0x88,0xFF,0x48,0x48,0x02,0x22,0x22,0x22,0x22,0xFE,0x00,0x08,0x0F,0x00,0x00,\n0x04,0x04,0x04,0x04,0x04,0x0F,}/*\"扫\",32*/,{\n\n0x88,0x88,0xFF,0x48,0xF2,0x97,0x92,0xF2,0x92,0x97,0xF2,0x00,0x08,0x0F,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,}/*\"描\",33*/,{\n\n0x42,0x22,0x5E,0x92,0x12,0xF2,0x00,0xFC,0x00,0x00,0xFF,0x00,0x08,0x04,0x02,0x01,\n0x00,0x00,0x01,0x08,0x08,0x0F,}/*\"列\",34*/,{\n\n0x40,0x44,0x54,0x54,0xD4,0x7F,0xD4,0x54,0x54,0x44,0x40,0x04,0x04,0x02,0x0F,0x08,\n0x04,0x01,0x02,0x04,0x0A,0x09,}/*\"表\",35*/,{\n\n0x88,0x88,0xFF,0x48,0xBC,0xAA,0xA0,0xFF,0xA0,0xAA,0xBE,0x00,0x08,0x0F,0x00,0x08,\n0x09,0x0A,0x04,0x04,0x0A,0x09,}/*\"搜\",36*/,{\n\n0x18,0x0A,0x4A,0x6A,0xDA,0x4F,0x4A,0x2A,0x8A,0x0A,0x18,0x00,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x00,}/*\"索\",37*/,{\n\n0x78,0x00,0xFF,0x08,0xC4,0x3F,0xC4,0x04,0xF4,0x44,0x24,0x00,0x00,0x0F,0x04,0x03,\n0x08,0x04,0x02,0x01,0x06,0x08,}/*\"恢\",38*/,{\n\n0x04,0x02,0x7D,0xD5,0x55,0x55,0x55,0x55,0x55,0x7D,0x01,0x00,0x0A,0x09,0x0B,0x05,\n0x05,0x05,0x05,0x0B,0x09,0x08,}/*\"复\",39*/,{\n\n0x08,0x48,0x48,0xC8,0x48,0x48,0x08,0xFF,0x08,0x09,0x0A,0x08,0x08,0x08,0x07,0x04,\n0x04,0x04,0x00,0x03,0x04,0x0E,}/*\"式\",40*/,{\n\n0x20,0xA4,0x24,0xFF,0x24,0x20,0xD2,0x4E,0x42,0x52,0xDE,0x08,0x07,0x04,0x0F,0x09,\n0x09,0x0B,0x0A,0x0A,0x0A,0x0B,}/*\"超\",41*/,{\n\n0xFE,0x22,0x22,0xFE,0x00,0x08,0x48,0x88,0x08,0xFF,0x08,0x07,0x02,0x02,0x07,0x00,\n0x00,0x00,0x09,0x08,0x0F,0x00,}/*\"时\",42*/,{\n\n0x28,0x24,0xE2,0xB0,0xB0,0xAF,0xA8,0xA4,0xA2,0xE4,0x08,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,}/*\"省\",43*/,{\n\n0xFC,0x24,0x24,0x24,0xFF,0x24,0x24,0x24,0xFC,0x00,0x00,0x03,0x01,0x01,0x01,0x07,\n0x09,0x09,0x09,0x09,0x08,0x0E,}/*\"电\",44*/,{\n\n0x20,0x22,0x2A,0xEA,0xAA,0xBF,0xAA,0xAA,0xAA,0x22,0x20,0x08,0x0A,0x09,0x0A,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x08,}/*\"麦\",45*/,{\n\n0x04,0xF4,0x94,0x94,0x94,0x9F,0x94,0x94,0x94,0xF4,0x04,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0C,}/*\"克\",46*/,{\n\n0x00,0xFE,0x12,0x22,0xC2,0x22,0x1A,0x02,0xFE,0x00,0x00,0x08,0x07,0x02,0x01,0x00,\n0x01,0x02,0x00,0x03,0x04,0x0F,}/*\"风\",47*/,{\n\n0x10,0x10,0xFF,0x10,0x3E,0xAB,0xA2,0xBE,0xA2,0xAB,0x3E,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,}/*\"增\",48*/,{\n\n0x48,0xA9,0x9A,0x8C,0x88,0x88,0x88,0x8C,0x9A,0xA9,0x48,0x08,0x0F,0x08,0x08,0x0F,\n0x08,0x0F,0x08,0x08,0x0F,0x08,}/*\"益\",49*/,{\n\n0x80,0x3E,0x2A,0xEA,0x2A,0x2A,0x2A,0xEA,0x2A,0x3E,0x80,0x08,0x09,0x0A,0x0F,0x08,\n0x08,0x08,0x0F,0x0A,0x09,0x08,}/*\"显\",50*/,{\n\n0x10,0x10,0x92,0x12,0x12,0xF2,0x12,0x12,0x92,0x10,0x10,0x04,0x02,0x01,0x00,0x08,\n0x0F,0x00,0x00,0x00,0x01,0x06,}/*\"示\",51*/,{\n\n0x00,0xFC,0x24,0x24,0x26,0x25,0x24,0x24,0x24,0xFC,0x00,0x00,0x0F,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0F,0x00,}/*\"自\",52*/,{\n\n0x10,0xD2,0x32,0x92,0x10,0x00,0x08,0xFF,0x08,0x08,0xF8,0x03,0x02,0x02,0x02,0x03,\n0x08,0x06,0x01,0x08,0x08,0x07,}/*\"动\",53*/,{\n\n0x12,0x12,0xEA,0xBF,0xA0,0xA0,0xA7,0xAA,0xEA,0x09,0x0C,0x00,0x00,0x0F,0x02,0x02,\n0x02,0x02,0x0A,0x0F,0x00,0x00,}/*\"背\",54*/,{\n\n0x20,0x22,0x24,0xE8,0x20,0x3F,0x20,0xE8,0x24,0x22,0x20,0x08,0x04,0x02,0x01,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,}/*\"光\",55*/,{\n\n0x82,0x82,0xBA,0xAA,0xAA,0xAB,0xAA,0xAA,0xBA,0x82,0x82,0x09,0x08,0x06,0x02,0x02,\n0x02,0x02,0x06,0x08,0x08,0x0D,}/*\"亮\",56*/,{\n\n0x00,0xFE,0x0A,0x8A,0xBE,0xAA,0xAB,0xAA,0xBE,0x8A,0x0A,0x08,0x07,0x00,0x08,0x09,\n0x0A,0x04,0x04,0x0A,0x09,0x08,}/*\"度\",57*/,{\n\n0x04,0xF4,0x55,0x56,0x54,0x5C,0x54,0x56,0x55,0xF4,0x04,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,}/*\"首\",58*/,{\n\n0x00,0xFF,0x05,0xA5,0xA5,0xA5,0xE5,0x55,0x55,0x15,0x07,0x08,0x07,0x02,0x02,0x02,\n0x02,0x07,0x09,0x09,0x09,0x0C,}/*\"尾\",59*/,{\n\n0x10,0x22,0x04,0x00,0xF2,0x54,0x50,0x5F,0x50,0x54,0xF2,0x04,0x02,0x01,0x00,0x0F,\n0x01,0x01,0x01,0x01,0x09,0x0F,}/*\"消\",60*/,{\n\n0x10,0x11,0xF2,0x00,0x08,0x28,0xC8,0x08,0x08,0xFF,0x08,0x08,0x04,0x03,0x04,0x08,\n0x08,0x08,0x0A,0x0A,0x0B,0x08,}/*\"过\",61*/,{\n\n0x00,0xF8,0x88,0x88,0x88,0xFF,0x88,0x88,0x88,0xF8,0x00,0x00,0x01,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x01,0x00,}/*\"中\",62*/,{\n\n0x98,0xD4,0xB3,0x88,0x00,0xFE,0x24,0xA8,0xFF,0xA8,0x24,0x04,0x04,0x02,0x02,0x00,\n0x0F,0x09,0x08,0x0F,0x08,0x09,}/*\"继\",63*/,{\n\n0x88,0x88,0xFF,0x48,0x00,0x4C,0xC4,0x75,0x46,0xC4,0x4C,0x00,0x08,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x02,0x05,0x08,}/*\"按\",64*/,{\n\n0x94,0xF3,0x92,0x64,0xDC,0x88,0xAA,0xFF,0xAA,0xBE,0x08,0x00,0x0F,0x04,0x0A,0x07,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,}/*\"键\",65*/,{\n\n0x00,0xFE,0x2A,0xAA,0x2A,0x3E,0x00,0xFE,0x02,0x02,0xFE,0x00,0x0F,0x04,0x02,0x01,\n0x06,0x00,0x0F,0x00,0x02,0x03,}/*\"即\",66*/,{\n\n0xFE,0x02,0xFE,0x00,0x4A,0x52,0x42,0xFE,0x41,0x51,0x49,0x03,0x01,0x03,0x00,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,}/*\"呼\",67*/,{\n\n0x00,0x00,0x00,0x00,0xFF,0x10,0x10,0x10,0x10,0x10,0x00,0x08,0x08,0x08,0x08,0x0F,\n0x08,0x08,0x08,0x08,0x08,0x08,}/*\"上\",68*/,{\n\n0x98,0xD4,0xB3,0x88,0x00,0x48,0x48,0xFF,0x24,0xA5,0x26,0x04,0x04,0x02,0x02,0x08,\n0x08,0x04,0x03,0x05,0x08,0x0E,}/*\"线\",69*/,{\n\n0x42,0xF2,0x2E,0xE2,0x01,0x3D,0x21,0x21,0x21,0x3F,0xE0,0x00,0x07,0x02,0x07,0x01,\n0x01,0x01,0x01,0x09,0x08,0x07,}/*\"码\",70*/,{\n\n0x02,0x02,0x02,0x02,0xFE,0x02,0x12,0x22,0x42,0x82,0x02,0x00,0x00,0x00,0x00,0x0F,\n0x00,0x00,0x00,0x00,0x01,0x00,}/*\"下\",71*/,{\n\n0x10,0xFC,0x03,0xFE,0xC2,0x02,0xFE,0x00,0xFC,0x00,0xFF,0x00,0x0F,0x08,0x04,0x03,\n0x04,0x08,0x00,0x01,0x08,0x0F,}/*\"侧\",72*/,{\n\n0xFC,0x04,0xFC,0x00,0xFC,0x04,0xE6,0x25,0xE4,0x04,0xFC,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,}/*\"响\",73*/,{\n\n0x00,0xFC,0x04,0x44,0x84,0x15,0xE6,0x04,0x04,0xE4,0x04,0x08,0x07,0x08,0x08,0x0B,\n0x08,0x08,0x0C,0x0B,0x08,0x08,}/*\"应\",74*/,{\n\n0x10,0xFC,0x03,0x08,0x68,0x88,0x09,0x0A,0x08,0xE8,0x08,0x00,0x0F,0x00,0x08,0x08,\n0x0B,0x08,0x0C,0x0B,0x08,0x08,}/*\"位\",75*/,{\n\n0x20,0x2A,0xF2,0x2E,0x60,0x00,0xF2,0x1A,0xD6,0x12,0xF2,0x00,0x08,0x0F,0x00,0x00,\n0x00,0x09,0x04,0x03,0x04,0x09,}/*\"预\",76*/,{\n\n0x28,0xEA,0xBA,0xEF,0xAA,0xAA,0x08,0xFF,0x08,0xE9,0x0A,0x04,0x04,0x04,0x0F,0x02,\n0x02,0x08,0x04,0x03,0x04,0x0E,}/*\"载\",77*/,{\n\n0x22,0x44,0x00,0xFC,0x24,0xE4,0x24,0x3F,0x24,0xE4,0x0C,0x04,0x02,0x08,0x07,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,}/*\"波\",78*/,{\n\n0x02,0xFE,0x52,0xFE,0x42,0x49,0x4A,0xF8,0x4A,0x49,0x40,0x02,0x03,0x02,0x0F,0x09,\n0x04,0x03,0x00,0x03,0x04,0x08,}/*\"联\",79*/,{\n\n0x00,0x82,0x92,0xDA,0xD6,0xB2,0xB1,0x91,0x89,0xC1,0x80,0x08,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x09,}/*\"系\",80*/,{\n\n0x00,0x00,0x00,0x80,0x60,0x1F,0x60,0x80,0x00,0x00,0x00,0x08,0x04,0x02,0x01,0x00,\n0x00,0x00,0x01,0x02,0x04,0x08,}/*\"人\",81*/,{\n\n0x22,0xEA,0xBF,0xEA,0x2A,0x54,0x53,0xFA,0x56,0xF0,0x40,0x00,0x0F,0x02,0x0F,0x00,\n0x01,0x09,0x0F,0x01,0x03,0x00,}/*\"静\",82*/,{\n\n0xFE,0x02,0xFE,0x00,0x70,0x57,0x75,0x85,0x75,0x57,0x70,0x03,0x01,0x03,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,}/*\"噪\",83*/,{\n\n0x44,0x53,0x52,0x56,0x52,0x7C,0x53,0xD2,0x56,0x52,0x42,0x01,0x01,0x03,0x05,0x01,\n0x09,0x09,0x0F,0x01,0x01,0x01,}/*\"等\",84*/,{\n\n0x98,0xD4,0xB3,0x88,0x02,0xFE,0x82,0x02,0x32,0x2E,0xE0,0x04,0x04,0x02,0x0A,0x06,\n0x01,0x08,0x05,0x02,0x05,0x08,}/*\"级\",85*/,{\n\n0x00,0xFE,0x2A,0xA9,0x00,0x28,0xE7,0x21,0x21,0xEF,0x08,0x02,0x0F,0x01,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,}/*\"段\",86*/,{\n\n0x08,0xF4,0x53,0xFA,0x56,0xF0,0x89,0x67,0x41,0xE9,0x4F,0x08,0x07,0x01,0x07,0x09,\n0x0F,0x00,0x02,0x02,0x0F,0x02,}/*\"解\",87*/,{\n\n0x94,0xF3,0x92,0x00,0xF2,0x14,0x10,0xDF,0x10,0x14,0xF2,0x00,0x0F,0x04,0x08,0x09,\n0x04,0x02,0x01,0x02,0x04,0x09,}/*\"锁\",88*/,{\n\n0x22,0x44,0x40,0xFC,0x20,0x10,0xFF,0x08,0x04,0xFC,0x00,0x04,0x02,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x09,0x09,0x0C,}/*\"池\",89*/,{\n\n0x11,0xF2,0x00,0x00,0xFF,0x21,0xA9,0xBD,0xA9,0x21,0xFF,0x00,0x07,0x02,0x08,0x07,\n0x00,0x03,0x02,0x0B,0x08,0x0F,}/*\"调\",90*/,{\n\n0x10,0x10,0x10,0x10,0xD0,0x3F,0xD0,0x10,0x10,0x10,0x10,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x03,0x04,0x08,0x08,}/*\"大\",91*/,{\n\n0x00,0xC0,0x30,0x00,0x00,0xFF,0x00,0x00,0x10,0x60,0x80,0x01,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x01,}/*\"小\",92*/,{\n\n0x90,0x54,0xB6,0x95,0x5C,0x54,0x34,0x94,0x36,0x54,0x90,0x00,0x0A,0x0A,0x0A,0x0A,\n0x09,0x05,0x04,0x04,0x02,0x00,}/*\"参\",93*/,{\n\n0x10,0xFC,0x03,0x80,0xFE,0x2A,0xEA,0x2B,0xEA,0x2A,0xEE,0x00,0x0F,0x01,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,}/*\"偏\",94*/,{\n\n0x12,0xD2,0xFE,0x91,0x08,0x44,0xAB,0x52,0x6A,0x46,0xC0,0x01,0x00,0x0F,0x00,0x08,\n0x09,0x04,0x05,0x02,0x01,0x00,}/*\"移\",95*/,{\n\n0x40,0x48,0x49,0x4A,0x48,0xF8,0x48,0x4A,0x49,0x48,0x40,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,}/*\"关\",96*/,{\n\n0x00,0xF9,0x02,0x20,0x20,0xA2,0xFA,0x22,0x22,0x02,0xFE,0x00,0x0F,0x00,0x02,0x01,\n0x04,0x07,0x00,0x08,0x08,0x0F,}/*\"闭\",97*/,{\n\n0x40,0x42,0x42,0xFE,0x42,0x42,0x42,0xFE,0x42,0x42,0x40,0x00,0x08,0x06,0x01,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,}/*\"开\",98*/,{\n\n0x00,0x00,0xFC,0xA4,0xA4,0xA5,0xA6,0xA4,0xA4,0xA4,0xBC,0x08,0x06,0x01,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,}/*\"启\",99*/,{\n\n0x12,0xD2,0xFE,0x91,0x40,0x38,0x00,0xFF,0x00,0x04,0xB8,0x01,0x00,0x0F,0x00,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,}/*\"秒\",100*/,{\n\n0x20,0x10,0x2C,0x23,0xE0,0x20,0x20,0x23,0xEC,0x10,0x20,0x00,0x08,0x04,0x03,0x00,\n0x08,0x08,0x08,0x07,0x00,0x00,}/*\"分\",101*/,{\n\n0x00,0x88,0x88,0x88,0x89,0xFA,0x88,0x88,0x88,0x88,0x00,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,}/*\"主\",102*/,{\n\n0x80,0xFE,0xAB,0xAA,0xFE,0x00,0x48,0x88,0x08,0xFF,0x08,0x04,0x02,0x01,0x08,0x0F,\n0x00,0x00,0x09,0x08,0x0F,0x00,}/*\"射\",103*/,{\n\n0x12,0x62,0x82,0x62,0x1E,0x00,0x1E,0x62,0x82,0x62,0x1E,0x08,0x06,0x01,0x06,0x00,\n0x08,0x04,0x02,0x01,0x06,0x08,}/*\"双\",104*/,{\n\n0xC1,0x5D,0x55,0xD5,0x55,0x5D,0xC1,0x00,0xFC,0x00,0xFF,0x0F,0x05,0x05,0x07,0x05,\n0x05,0x0F,0x00,0x01,0x08,0x0F,}/*\"副\",105*/,{\n\n0x20,0x20,0xAF,0x69,0x29,0x29,0x29,0x29,0x2F,0x20,0x20,0x00,0x00,0x01,0x01,0x01,\n0x01,0x01,0x09,0x09,0x07,0x00,}/*\"号\",106*/,{\n\n0x00,0x00,0xFE,0x12,0x92,0x92,0x92,0x91,0x91,0x91,0x90,0x08,0x06,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,}/*\"后\",107*/,{\n\n0x20,0x10,0xFC,0x03,0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x00,0x00,0x0F,0x00,0x01,\n0x02,0x0A,0x0E,0x02,0x02,0x01,}/*\"停\",108*/,{\n\n0x00,0x00,0xF8,0x00,0x00,0x00,0xFF,0x10,0x10,0x10,0x00,0x08,0x08,0x0F,0x08,0x08,\n0x08,0x0F,0x08,0x08,0x08,0x08,}/*\"止\",109*/,{\n\n0x12,0xD2,0xFE,0x51,0x90,0xC8,0x07,0xF4,0x04,0x54,0x8C,0x01,0x00,0x0F,0x00,0x02,\n0x01,0x08,0x0F,0x00,0x00,0x03,}/*\"称\",110*/,{\n\n0x02,0x02,0x82,0x42,0x22,0xF2,0x0E,0x22,0x42,0x82,0x02,0x01,0x01,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x01,}/*\"不\",111*/,{\n\n0x04,0x04,0x84,0x64,0x14,0xFF,0x14,0x64,0x84,0x04,0x04,0x02,0x01,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x01,0x02,}/*\"本\",112*/,{\n\n0x10,0x10,0xFF,0x10,0x20,0xFC,0x10,0xFF,0x08,0x84,0xFC,0x04,0x04,0x03,0x02,0x00,\n0x07,0x08,0x09,0x08,0x08,0x0E,}/*\"地\",113*/,{\n\n0x98,0xF7,0x94,0x84,0x10,0x48,0x44,0x53,0x64,0xC8,0x10,0x00,0x0F,0x04,0x02,0x00,\n0x00,0x02,0x04,0x0B,0x00,0x00,}/*\"铃\",114*/,{\n\n0x00,0xFE,0x02,0x02,0xF2,0x92,0x92,0xF2,0x02,0x02,0xFE,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,}/*\"回\",115*/,{\n\n0x10,0x10,0x28,0x24,0x22,0xE1,0x22,0x24,0x28,0x10,0x10,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,}/*\"全\",116*/,{\n\n0x20,0xAA,0xB2,0xA3,0xB2,0xAA,0x20,0xFE,0x02,0x32,0xCE,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x00,0x0F,0x02,0x02,0x01,}/*\"部\",117*/,{\n\n0x00,0xFE,0x92,0x92,0x92,0xFE,0x92,0x92,0x92,0xFE,0x00,0x08,0x07,0x00,0x00,0x00,\n0x07,0x00,0x08,0x08,0x0F,0x00,}/*\"用\",118*/,{\n\n0x20,0x10,0xFC,0x03,0xFE,0x22,0x22,0xFE,0x21,0x21,0x20,0x00,0x00,0x0F,0x00,0x07,\n0x02,0x05,0x08,0x03,0x04,0x0F,}/*\"低\",119*/,{\n\n0x20,0x20,0x20,0xFF,0x28,0x28,0xE4,0x24,0x22,0x22,0x20,0x00,0x00,0x00,0x0F,0x04,\n0x02,0x00,0x01,0x02,0x04,0x04,}/*\"长\",120*/,{\n\n0x82,0x82,0xBA,0xAA,0xAA,0xAB,0xAA,0xAA,0xBA,0x82,0x82,0x0F,0x00,0x00,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x00,0x08,0x0F,}/*\"高\",121*/,{\n\n0x48,0x47,0xFC,0x44,0x02,0x7A,0x4A,0x4A,0x4A,0x7A,0x02,0x08,0x06,0x01,0x06,0x08,\n0x09,0x0A,0x08,0x0A,0x09,0x08,}/*\"短\",122*/,{\n\n0x80,0x92,0x92,0x92,0x92,0xFE,0x91,0x91,0x91,0x91,0x80,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x00,}/*\"手\",123*/,{\n\n0x10,0x10,0xFF,0x08,0x08,0x02,0x02,0xFE,0x02,0x02,0xFE,0x00,0x00,0x07,0x02,0x09,\n0x04,0x03,0x00,0x08,0x08,0x07,}/*\"切\",124*/,{\n\n0x88,0x88,0xFF,0x48,0x08,0xF4,0x13,0xFA,0x16,0xF0,0x00,0x00,0x08,0x0F,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,}/*\"换\",125*/,{\n\n0x04,0x04,0xFC,0x04,0x04,0x08,0xFF,0x08,0x08,0x08,0xF8,0x02,0x02,0x01,0x09,0x05,\n0x03,0x00,0x00,0x08,0x08,0x07,}/*\"功\",126*/,{\n\n0x00,0x9E,0x80,0x80,0xBF,0x90,0x88,0x87,0x94,0xA4,0x04,0x08,0x0F,0x08,0x08,0x0F,\n0x08,0x0F,0x08,0x08,0x0F,0x08,}/*\"监\",127*/,{\n\n0xFE,0x02,0x02,0xFE,0x00,0xFE,0x12,0x12,0xF1,0x11,0x10,0x03,0x01,0x01,0x03,0x08,\n0x07,0x00,0x00,0x0F,0x00,0x00,}/*\"听\",128*/,{\n\n0x02,0xEA,0x2A,0x2A,0x2A,0xEF,0x2A,0x2A,0x2A,0xEA,0x02,0x08,0x07,0x01,0x01,0x01,\n0x01,0x01,0x01,0x01,0x03,0x00,}/*\"声\",129*/,{\n\n0x88,0xFF,0x48,0x00,0x4C,0xA4,0x95,0x86,0x94,0xA4,0x4C,0x08,0x0F,0x00,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,}/*\"控\",130*/,{\n\n0x88,0x68,0xFF,0x28,0x40,0xFE,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,}/*\"机\",131*/,{\n\n0x2C,0x24,0xA4,0x24,0x25,0xE6,0x24,0x24,0x24,0x24,0x2C,0x08,0x04,0x03,0x04,0x08,\n0x0F,0x09,0x09,0x09,0x09,0x08,}/*\"定\",132*/,{\n\n0x18,0xD6,0x54,0xFF,0x54,0xD4,0x10,0xFC,0x00,0x00,0xFF,0x00,0x07,0x00,0x0F,0x04,\n0x07,0x00,0x01,0x08,0x08,0x0F,}/*\"制\",133*/,{\n\n0x06,0xEA,0x2A,0x3E,0x2A,0xAB,0x2A,0x3E,0x2A,0xEA,0x06,0x08,0x09,0x04,0x04,0x02,\n0x01,0x06,0x08,0x08,0x09,0x0C,}/*\"宽\",134*/,{\n\n0x86,0x4A,0x26,0x3A,0xE2,0xA3,0xA2,0xA2,0xA6,0xAA,0x26,0x00,0x00,0x00,0x00,0x0F,\n0x02,0x02,0x02,0x02,0x02,0x02,}/*\"窄\",135*/,{\n\n0x32,0x92,0x97,0x92,0x92,0xD7,0x92,0x92,0x97,0x92,0x32,0x00,0x07,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x04,0x07,0x00,}/*\"带\",136*/\n\n\n\n\n};\n\n#ifdef ENABLE_CHINESE_FULL1\n uint8_t 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ENABLE_CHINESE_FULL2\n\n uint8_t  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  },
  {
    "path": "uv-k5font/font_new/font.h",
    "content": "#define CHN_FONT_WIDTH 11\n#define CHN_FONT_HIGH   12\n#define CHN_FONT_NUM  137\nextern unsigned char new_font[CHN_FONT_NUM][22] ;\n"
  },
  {
    "path": "uv-k5font/font_new/main.cpp",
    "content": "#include <bits/stdc++.h>\n#include \"font.h\"\n\nusing namespace std;\nofstream out_chinese_array(\"../chinese_array.txt\");\n\nvoid set_bit(uint8_t *value, uint8_t bit_position, uint8_t bit_value) {\n    if (bit_value == 0) {\n        *value = *value & ~(1 << bit_position);\n    } else {\n        *value = *value | (1 << bit_position);\n    }\n}\n\n#define IS_BIT_SET(byte, bit) ((byte>>bit) & (1))\n\nvoid show_font(unsigned char show_font[22]) {\n    unsigned char bitmap[CHN_FONT_HIGH][CHN_FONT_WIDTH] = {0};\n    for (int i = 0; i < CHN_FONT_WIDTH * 2; i++) {\n        if (i < CHN_FONT_WIDTH) {\n            for (int j = 0; j < 8; j++) {\n                if (IS_BIT_SET(show_font[i], j))\n                    bitmap[j][i] = 1;\n            }\n        } else {\n            for (int j = 0; j < CHN_FONT_HIGH - 8; ++j) {\n                bitmap[j + 8][i - CHN_FONT_WIDTH] = IS_BIT_SET(show_font[i], j);\n            }\n        }\n\n    }\n    for (int i = 0; i < CHN_FONT_HIGH; ++i) {\n        for (int j = 0; j < CHN_FONT_WIDTH; ++j) {\n            if (bitmap[i][j])\n                printf(\"1\");\n            else\n                printf(\"0\");\n        }\n        printf(\"\\n\");\n\n    }\n}\nbool check_font(unsigned char *font1,unsigned char *font2)\n{\n    return (memcmp(font1,font2,CHN_FONT_WIDTH*2)==0);\n}\nvoid back_font(int num_show, unsigned char *font) { //压缩转显存显示\n    unsigned int local = CHN_FONT_HIGH * CHN_FONT_WIDTH * num_show / 8;\n    unsigned int local_bit = (CHN_FONT_HIGH * CHN_FONT_WIDTH * num_show) % 8;\n    unsigned char now_font[CHN_FONT_WIDTH * 2] = {0};\n    for (int i = 0; i < CHN_FONT_WIDTH*2; ++i) {\n        unsigned char j_end=8;\n        if(i>=CHN_FONT_WIDTH)\n            j_end=CHN_FONT_HIGH-8 ;\n\n        for (int j = 0; j < j_end; ++j) {\n\n            if (IS_BIT_SET(font[local], local_bit))\n                set_bit(&now_font[i], j, 1);\n            local_bit++;\n            if (local_bit == 8) {\n                local_bit = 0;\n                local++;\n            }\n        }\n\n    }\n if(!check_font(now_font,new_font[num_show]))\n {\n     printf(\"SB\\n\");\n }\n}\n\nint main() {\n    unsigned int NEW_FONT_BYTE = ceil((float) (CHN_FONT_NUM) * (float) (CHN_FONT_HIGH) * (float) (CHN_FONT_WIDTH) / 8);\n    cout << NEW_FONT_BYTE << endl;\n    unsigned char gFontChinese_out[NEW_FONT_BYTE] = {0};\n\n//    show_font(new_font[0]);\n//    return 0;\n    int now_byte_index = 0;\n    int now_bit_index = 0;\n    for (int k = 0; k < CHN_FONT_NUM; k++) {//压缩\n        unsigned char bitmap[CHN_FONT_HIGH][CHN_FONT_WIDTH] = {0};\n        for (int i = 0; i < CHN_FONT_WIDTH * 2; i++) {\n            if (i < CHN_FONT_WIDTH) {\n                for (int j = 0; j < 8; j++) {\n                    if (IS_BIT_SET(new_font[k][i], j))\n                        bitmap[j][i] = 1;\n                }\n            } else {\n                for (int j = 0; j < CHN_FONT_HIGH - 8; ++j) {\n                    bitmap[j + 8][i - CHN_FONT_WIDTH] = IS_BIT_SET(new_font[k][i], j);\n                }\n            }\n        }\n\n        for (int i = 0; i < CHN_FONT_WIDTH; ++i) {\n            for (int j = 0; j < 8; ++j) {\n                if (bitmap[j][i])\n                    set_bit(&gFontChinese_out[now_byte_index], now_bit_index, 1);\n\n                now_bit_index++;\n                if (now_bit_index == 8) {\n                    now_bit_index = 0;\n                    now_byte_index++;\n                }\n\n            }\n        }\n\n        for (int i = 0; i < CHN_FONT_WIDTH; ++i) {\n            for (int j = 8; j < CHN_FONT_HIGH; ++j) {\n                if (bitmap[j][i])\n                    set_bit(&gFontChinese_out[now_byte_index], now_bit_index, 1);\n                now_bit_index++;\n                if (now_bit_index == 8) {\n                    now_bit_index = 0;\n                    now_byte_index++;\n                }\n\n            }\n        }\n\n        back_font(k, gFontChinese_out);\n\n    }\n    out_chinese_array<<\"gFontChinese_out[SUM_BYTE]={\"<<endl;\n    for (int i = 0; i < NEW_FONT_BYTE; i++) {\n        out_chinese_array << \"0X\" << hex << setw(2) << setfill('0') << uppercase << (int) gFontChinese_out[i]<<\",\";\n        if(i%6==0&&i!=0)out_chinese_array<<endl;\n    }\n    out_chinese_array<<\"};\";\n    out_chinese_array.close();\n\n\n}\n"
  },
  {
    "path": "uv-k5font/main.cpp",
    "content": "\n#include<iostream>\n#include<fstream>\n#include<string>\n#include <vector>\n#include <array>\n#include <map>\n#include \"bits/stdc++.h\"\n#include \"font.h\"\n\nusing namespace std;\n#define IS_BIT_SET(byte, bit) ((byte>>bit) & (1))\n\nifstream file(\"../name.txt\"); // 滻ļ·\nofstream outFile(\"../name_tmp.txt\");\nofstream out_chinese_array(\"../chinese_array.txt\");\nofstream out_chinese_map(\"../chinese_map.txt\");\n\nstring names[1000];\nunsigned char chinese[1000][2];\nunsigned char english[1000];\nbool en_flag[256] = {false};\n\nint init_file() {\n    int lines = 0;\n    if (file.is_open()) {\n        string line;\n        while (getline(file, line)) {\n            // Զȡÿһִвӡ̨\n            names[lines] = line;\n            lines++;\n\n        }\n\n        file.close();\n    } else {\n        cout << \"޷ļ\" << endl;\n    }\n    return lines;\n\n}\n\nbool sortByValue(const pair<array<unsigned char, 2>, int> &a, const pair<array<unsigned char, 2>, int> &b) {\n    return a.second < b.second;\n}\n\nmap<array<unsigned char, 2>, unsigned char> map_str;\nmap<array<unsigned char, 2>, unsigned char> all_code;\n\nbool isGBKChineseCharacter(const string &str, size_t index) {\n    // GBKַǷΪ\n    if (index < str.size() - 1) {\n        unsigned char firstByte = static_cast<unsigned char>(str[index]);\n        unsigned char secondByte = static_cast<unsigned char>(str[index + 1]);\n        if (firstByte >= 0x81 && firstByte <= 0xFE &&\n            ((secondByte >= 0x40 && secondByte <= 0x7E) || (secondByte >= 0x80 && secondByte <= 0xFE))) {\n            return true;\n        }\n    }\n    return false;\n}\n\nvoid removeNullStrings(const std::string &inputFile, const std::string &outputFile) {\n    std::ifstream input(inputFile, std::ios::binary);\n    std::ofstream output(outputFile, std::ios::binary);\n\n    if (!input.is_open()) {\n        std::cerr << \"Unable to open input file\" << std::endl;\n        return;\n    }\n\n    if (!output.is_open()) {\n        std::cerr << \"Unable to open output file\" << std::endl;\n        return;\n    }\n\n    std::string buffer;\n    while (getline(input, buffer)) {\n        size_t found = buffer.find(\"\\\\x00\");\n        while (found != std::string::npos) {\n            buffer.erase(found, 4); // Erase 4 characters starting from found position\n            found = buffer.find(\"\\\\x00\", found);\n        }\n        output << buffer << std::endl;\n    }\n\n    input.close();\n    output.close();\n}\n\nvoid check_num(int k) {\n\n    ::uint8_t img[10][11] = {0};\n    int cnt = 0;\n    int row = 0, col = 0;\n    bool flag = 0;\n    for (int i = 0; i < 14; i++) {\n        for (int j = 0; j < 8; j++) {\n            if (IS_BIT_SET(chn_font[k][i], j % 8) == 1) {\n                img[row][col] = 1;\n               // printf(\"%d %d\\n\", row, col);\n            } else {\n              //  printf(\"%d %d\\n\", row, col);\n\n                img[row][col] = 0;\n            }\n\n            cnt++;\n            if (cnt <= 88) {\n                if (cnt % 8 == 0 && cnt != 0) {\n                    if (cnt % (8 * 11) == 0) {\n                        row += 1;\n                        col = 0;\n                    } else {\n\n                        row -= 7;\n                        col++;\n\n                    }\n                } else {\n                    row++;\n                }\n            } else {\n                if ((cnt - 88) % 2 == 0) {\n                    row = row - 1;\n                    col++;\n                } else\n\n                    row++;\n\n            }\n            if (flag) {\n                break;\n            }\n            if (row == 9 && col == 10) {\n                flag = 1;\n\n            }\n\n        }\n\n    }\n    for (int i = 0; i < 10; i++) {\n        for (int j = 0; j < 11; ++j) {\n            ::printf(\"%d\", img[i][j]);\n        }\n        cout << endl;\n\n    }\n}\nvoid set_bit(uint8_t* value, uint8_t bit_position, uint8_t bit_value) {\n    if (bit_value == 0) {\n        *value= *value & ~(1 << bit_position); // ָλΪ 0\n    } else {\n        *value= *value | (1 << bit_position);  // ָλΪ 1\n    }\n}\nint main() {\n\n    int num_names = init_file();\n    // cout << num_names << endl;\n\n    int num_chinese = 0;\n    int num_english = 0;\n    if (!outFile.is_open()) {\n        return -5;\n    }\n    // дݵļ\n\n\n//        // رļ\n//    outFile << \"Hello, this is some text.\\n\";\n//    outFile << \"This is a new line.\";\n    for (int i = 0; i < num_names; i++) {\n\n\n        for (size_t j = 0; j < names[i].size(); ++j) {\n            if (isGBKChineseCharacter(names[i], j)) {\n\n                array<unsigned char, 2> tmp = {0};\n                tmp[0] = names[i][j];\n                tmp[1] = names[i][j + 1];\n\n                if (map_str.find(tmp) != map_str.end()) {\n                } else {\n                    // ӳУµļóִΪ1\n                    map_str[tmp] = num_chinese;\n//                       cout<<num_chinese<<\":\"<<tmp[0]<< tmp[1]<<endl;\n\n                    chinese[num_chinese][0] = tmp[0];\n                    chinese[num_chinese][0] = tmp[1];\n                    //   outFile <<\"\\\\x\"<< hex << setw(2) << setfill('0') << uppercase <<  num_chinese << endl;\n\n                    num_chinese++;\n                }\n                j++; // һֽڣΪռֽ\n\n            } else {\n\n                if (en_flag[names[i][j]]) {\n\n                } else {\n                    //         ӳУµļóִΪ1\n                    en_flag[names[i][j]] = true;\n                    english[num_english] = names[i][j];\n                    num_english++;\n                }\n            }\n        }\n    }\n\n\n\n\n    // outFile <<\"\\\\x\"<< hex << setw(2) << setfill('0') << uppercase <<   map_str[tmp] << endl;\n\n\n\n    vector<pair<array<unsigned char, 2>, int>> vec(map_str.begin(), map_str.end());\n\n    // ʹԶıȽϺֵ\n    sort(vec.begin(), vec.end(), sortByValue);\n    en_flag['\\n'] = true;\n    en_flag[' '] = true;\n\n    for (int i = '!'; i <= '~'; i++) {\n        en_flag[i] = true;\n    }\n    // ļֵ\n    int now_code = 1;\n    for (const auto &pair: vec) {\n      // cout << \"{\" << static_cast<int>(pair.first[0]) << \", \" << static_cast<int>(pair.first[1]) << \"} : \" << pair.second << endl;\n        array<unsigned char, 2> tmp = {0};\n        tmp[0] = pair.first[0];\n        tmp[1] = pair.first[1];\n        map_str[tmp] = now_code;\n        while (en_flag[map_str[tmp]]) {\n            cout << (char) map_str[tmp] << \":\" << (int) map_str[tmp] << endl;\n            array<unsigned char, 2> tmp1;\n            tmp1[0] = 5;\n            tmp1[1] = map_str[tmp];\n            all_code[tmp1] = map_str[tmp];\n            map_str[tmp] += 1;\n            now_code++;\n        }\n        array<unsigned char, 2> tmp1;\n        tmp1[0] = tmp[0];\n        tmp1[1] = tmp[1];\n        all_code[tmp1] = map_str[tmp];\n\n        now_code++;\n        cout << tmp[0] << tmp[1] << \":\" << (int) map_str[tmp] << endl;\n        //   cout << tmp[0] << tmp[1]<<\"','\\\\\" <<endl;\n\n    }\n\n\n\n    for (int i = 0; i < num_names; i++) {\n        for (size_t j = 0; j < names[i].size(); ++j) {\n            if (isGBKChineseCharacter(names[i], j)) {\n\n                array<unsigned char, 2> tmp = {0};\n                tmp[0] = names[i][j];\n                tmp[1] = names[i][j + 1];\n               outFile << \"\\\\x\" << hex << setw(2) << setfill('0') << uppercase << (int) all_code[tmp];\n             //   outFile << \"\\\\x\" << hex << setw(2) << setfill('0') << uppercase << static_cast<unsigned int>(all_code[tmp]);\nj++;\n            } else {\n                array<unsigned char, 2> tmp = {0};\n                tmp[0] = 5;\n                tmp[1] = names[i][j];\n               outFile << \"\\\\x\" << hex << setw(2) << setfill('0') << uppercase << (int) tmp[1];\n              //  outFile << \"\\\\x\" << hex << setw(2) << setfill('0') << uppercase << static_cast<unsigned int>(all_code[tmp]);\n\n            }\n\n        }\n\n        outFile << endl;\n    }\n\n    outFile.close();\n\n    std::string inputFile = \"../name_tmp.txt\"; // Replace with your input file name\n    std::string outputFile = \"../name_out.txt\"; // Replace with your output file name\n    removeNullStrings(inputFile, outputFile);\n\n\n    cout << \"chinese num:\" << num_chinese << endl;\n    cout << \"english num\" << num_english << endl;\n\n    for (int i = 0; i < CHAR_NUM; i++) {\n        for (int j = 0; j < 14; j++) {\n            if(j==13) {\n                set_bit(&chn_font[i][j], 6, 1);\n                set_bit(&chn_font[i][j], 7, 1);\n\n            }\n            chn_font[i][j] = ~chn_font[i][j];\n        }\n    }\n   // check_num(0);\n\n    cout << endl;\n    uint8_t chinese_font[SUM_BYTE] = {0};\n    int cnt_bit = 0;\n    int cnt = 0;\n    for (int i = 0; i < CHAR_NUM; i++) {\n        for (int j = 0; j < 14; j++) {\n            int up = 0;\n            if (j == 13)up = 6;\n            else up = 8;\n            for (int k = 0; k < up; k++) {\n                set_bit(&chinese_font[cnt], cnt_bit, IS_BIT_SET(chn_font[i][j], k));\n                cnt_bit++;\n                if (cnt_bit == 8) {\n                    cnt_bit = 0;\n                    cnt++;\n                }\n            }\n        }\n    }\n    cout<<\"ok\"<<endl;\n\n    {\n        int num_in=50;\n           //int num_in = 2;\n           int num = 0;\n           if (num_in >= 1 && num_in < 10)num = num_in - 1;\n           else if (num_in > 10 && num_in < 32)num = num_in - 2;\n           else if (num_in > 126 && num_in <= 250)num = num_in - 97;\n           uint8_t bit_cnt = 0;\n           uint8_t cntt = 0;\n           uint8_t get[22] = {0};\n           for (int i = 0; i < 110; i++) {\n               //    cout << IS_BIT_SET(chinese_font[(i + num * 110) / 8], (i + num * 110\n               //    ) % 8);\n               if (IS_BIT_SET(chinese_font[(i + num * 110) / 8], (i + num * 110) % 8))\n                   set_bit(&get[cntt], bit_cnt, 1);\n               bit_cnt++;\n               if (bit_cnt == 8 && cntt < 11) {\n                   bit_cnt = 0;\n                   cntt++;\n               } else if (bit_cnt == 2 && cntt >= 11) {\n                   bit_cnt = 0;\n                   cntt++;\n               }\n           }\n           for (int o = 0; o < 22; o++) {\n               ::printf(\"%02X \", get[o]);\n           }\n\n\n           cout << endl;\n           for (int o = 0; o < 14; o++) {\n               ::printf(\"%02X \", chn_font[num][o]);\n           }\n       }\n\n    out_chinese_array<<\"gFontChinese_out[SUM_BYTE]={\"<<endl;\n    for (int i = 0; i < sizeof (chinese_font); i++) {\n        out_chinese_array << \"0X\" << hex << setw(2) << setfill('0') << uppercase << (int) chinese_font[i]<<\",\";\n        if(i%6==0&&i!=0)out_chinese_array<<endl;\n    }\n    out_chinese_array<<\"};\";\n    out_chinese_array.close();\n\nreturn 0;\n\n}\n\n\n\n"
  },
  {
    "path": "uv-k5font/name.txt",
    "content": "Ƶ\r\n\r\nģ\r\n\r\nģ\r\nƵ\r\nƵƵ\r\n\r\næ\r\nѹ\r\nŵ\r\nɾŵ\r\nŵ\r\nŵɨб\r\nɨб1\r\nɨб2\r\nָģʽ\r\nͳʱ\r\nʡģʽ\r\n˷\r\nŵʾģʽ\r\nԶ\r\n\r\nβ\r\nMDC ID\r\nβ\r\nмβ\r\n\r\nDTMF ID\r\nDTMF\r\nDTMF\r\nDTMF\r\nDTMF\r\nDTMFӦ\r\nDTMFλ\r\nDTMFԤز\r\nDTMFϵ\r\nDTMFʾ\r\nAMԶ\r\nշģʽ\r\nȼ\r\nƵν\r\nصѹ\r\nشС\r\nλ\r\n=\r\n=+ƫ\r\n=-ƫ\r\nر\r\n\r\n1 \r\n2 \r\n3 \r\n4 \r\n30 \r\n1 \r\n2 \r\n3 \r\n4 \r\n5 \r\n6 \r\n7 \r\n8 \r\n9 \r\n15 \r\nŵշ\r\n˫ŵ\r\nŵ丱ŵ\r\nŵ˫ŵ\r\nź5\r\nźֹͣ\r\nźźֹͣ\r\nƵ\r\nŵ\r\n\r\n+Ƶ\r\nӦ\r\n\r\nظӦ\r\nظӦ\r\n\r\n\r\n\r\n+\r\nQuindar\r\nر\r\nROGERβ\r\nMDCβ\r\nMDC\r\nMDCβ\r\nMDC+ROGER\r\nŵ\r\nȫ\r\nȫ\r\nȫ\r\n5 \r\n10 \r\n20 \r\nʱ\r\nʱ\r\n/ʱ\r\nб\r\nȫ\r\nɨ\r\n͵ѹ\r\n # \r\næ\r\nֹ\r\nͳʱ\r\nߵѹ\r\n EXIT \r\nȫ\r\n\r\nģ\r\n\r\nƵ\r\n?\r\n:\r\nɨ\r\nɾ?\r\n1̰\r\n1\r\n2̰\r\n2\r\nM\r\nֵ\r\nл书\r\n\r\nط\r\nFM\r\n\r\nлŵ\r\nлŵģʽ\r\nлģʽ\r\nDTMF\r\nлխ\r\nDTMF\r\nխ\r\n\r\nխ"
  },
  {
    "path": "uv-k5font/name_out.txt",
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  },
  {
    "path": "uv-k5font/name_out_fina.txt",
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  },
  {
    "path": "uv-k5font/name_tmp.txt",
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  },
  {
    "path": "uv-k5font/uv-k5font_full/font.cpp",
    "content": "#include \"font.h\"\n\n#ifdef JIAN\nunsigned char new_font[CHN_FONT_NUM][22] = {\n        {\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x32, 0xCE, 0xF8, 0x8A, 0xFE, 0x02, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x02, 0x01, 0x00, 0x08, 0x0F, 0x00,/*啊0*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0xF2, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x03, 0x01, 0x09, 0x08, 0x0F, 0x00,/*阿1*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x48, 0x3C, 0x2A, 0xE9, 0x28, 0x2C, 0x18, 0x04, 0x04, 0x03, 0x02, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*埃2*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x48, 0x3C, 0x2A, 0xE9, 0x28, 0x2C, 0x18, 0x08, 0x0F, 0x00, 0x08, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*挨3*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x04, 0x6F, 0x84, 0x04, 0x84, 0x6F, 0x04, 0x04, 0x03, 0x01, 0x0B, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*哎4*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x48, 0x3C, 0x2A, 0xE9, 0x28, 0x2C, 0x18, 0x03, 0x01, 0x03, 0x08, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*唉5*/},\n        {\n\n                0x04, 0x74, 0x54, 0x54, 0xD5, 0xD6, 0x54, 0x54, 0x54, 0x74, 0x04, 0x04, 0x04, 0x02, 0x0F, 0x08,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*哀6*/},\n        {\n\n                0xFC, 0x46, 0x45, 0xFC, 0x00, 0x2E, 0x28, 0x2F, 0x28, 0xEE, 0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x07, 0x09, 0x09, 0x09, 0x09, 0x0C,/*皑7*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xC2, 0x7A, 0xEB, 0x2A, 0xEA, 0x7A, 0xC2, 0x09, 0x04, 0x03, 0x00, 0x0D,\n                0x09, 0x09, 0x0E, 0x09, 0x09, 0x0D,/*癌8*/},\n        {\n\n                0x42, 0xCA, 0x12, 0x07, 0xFA, 0xAA, 0xAA, 0xAF, 0xAA, 0xFA, 0x82, 0x00, 0x0F, 0x04, 0x01, 0x06,\n                0x04, 0x06, 0x05, 0x06, 0x08, 0x0F,/*蔼9*/},\n        {\n\n                0x48, 0x47, 0xFC, 0x44, 0xA8, 0x9A, 0x8A, 0xFE, 0x89, 0x99, 0xA8, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x0A, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*矮10*/},\n        {\n\n                0x04, 0x04, 0x04, 0x6F, 0x84, 0x04, 0x84, 0x6F, 0x04, 0x04, 0x04, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x04, 0x08, 0x08,/*艾11*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x5F, 0x55, 0x55, 0x55, 0xD5, 0x5F, 0x00, 0x07, 0x02, 0x07, 0x01,\n                0x03, 0x05, 0x01, 0x09, 0x0F, 0x01,/*碍12*/},\n        {\n\n                0x32, 0x56, 0x5A, 0xD2, 0x76, 0x5A, 0x51, 0x51, 0x59, 0x55, 0x31, 0x08, 0x04, 0x0A, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x0B, 0x08, 0x08,/*爱13*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0xA9, 0x9A, 0x88, 0x88, 0x88, 0x9A, 0xA9, 0x40, 0x0F, 0x02, 0x09, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*隘14*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x4C, 0xC4, 0x75, 0x46, 0xC4, 0x4C, 0x02, 0x02, 0x0F, 0x02, 0x0A,\n                0x08, 0x05, 0x02, 0x02, 0x05, 0x08,/*鞍15*/},\n        {\n\n                0xC4, 0x52, 0x55, 0xD5, 0x75, 0x55, 0x55, 0xD5, 0xF5, 0x01, 0x00, 0x00, 0x09, 0x0B, 0x05, 0x05,\n                0x0B, 0x09, 0x00, 0x03, 0x04, 0x0E,/*氨16*/},\n        {\n\n                0x2C, 0x24, 0xA4, 0x64, 0x3D, 0x26, 0x24, 0x24, 0xE4, 0x24, 0x2C, 0x08, 0x08, 0x09, 0x05, 0x05,\n                0x02, 0x02, 0x05, 0x04, 0x08, 0x00,/*安17*/},\n        {\n\n                0x10, 0xFC, 0x23, 0x12, 0xEA, 0xA6, 0xF3, 0xA6, 0xEA, 0x12, 0x10, 0x00, 0x0F, 0x00, 0x00, 0x07,\n                0x02, 0x07, 0x0A, 0x0B, 0x08, 0x0E,/*俺18*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x4C, 0xC4, 0x75, 0x46, 0xC4, 0x4C, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x02, 0x05, 0x08,/*按19*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x24, 0xAC, 0xB4, 0xA5, 0xA6, 0xB4, 0xAC, 0x24, 0x07, 0x02, 0x07, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*暗20*/},\n        {\n\n                0x00, 0xF6, 0x14, 0x54, 0x54, 0x57, 0xD4, 0x54, 0x54, 0x56, 0x00, 0x08, 0x07, 0x01, 0x01, 0x01,\n                0x01, 0x0F, 0x01, 0x01, 0x01, 0x01,/*岸21*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x4C, 0xC5, 0x76, 0x44, 0xC4, 0x4C, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x09, 0x05, 0x02, 0x02, 0x05, 0x08,/*胺22*/},\n        {\n\n                0x46, 0x4A, 0x4A, 0x5A, 0x2E, 0xAB, 0x2A, 0x5A, 0x4A, 0x4A, 0x06, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*案23*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x04, 0xE4, 0x25, 0x26, 0xE4, 0x04, 0x04, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*肮24*/},\n        {\n\n                0xC0, 0x5F, 0x55, 0x35, 0x15, 0x15, 0xD5, 0x55, 0x55, 0x5F, 0xC0, 0x07, 0x04, 0x04, 0x02, 0x02,\n                0x00, 0x0F, 0x00, 0x00, 0x04, 0x07,/*昂25*/},\n        {\n\n                0x90, 0x90, 0x5E, 0x52, 0x32, 0x1F, 0x32, 0x52, 0x5E, 0x90, 0x90, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盎26*/},\n        {\n\n                0xFE, 0x02, 0x02, 0x7E, 0x40, 0x40, 0x40, 0x7E, 0x02, 0x02, 0xFE, 0x0F, 0x04, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*凹27*/},\n        {\n\n                0x44, 0x54, 0xD4, 0x7F, 0x54, 0x44, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x08, 0x04, 0x03, 0x09, 0x0F,\n                0x00, 0x08, 0x05, 0x02, 0x05, 0x08,/*敖28*/},\n        {\n\n                0x22, 0xEA, 0xBF, 0xAA, 0xA2, 0x10, 0x08, 0xB7, 0x44, 0xBC, 0x04, 0x0A, 0x05, 0x00, 0x06, 0x0B,\n                0x00, 0x05, 0x08, 0x00, 0x04, 0x09,/*熬29*/},\n        {\n\n                0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0x10, 0xA2, 0xFE, 0x10, 0xA2, 0xFE, 0x02, 0x05, 0x0E, 0x05, 0x02,\n                0x01, 0x08, 0x0F, 0x01, 0x08, 0x0F,/*翱30*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*袄31*/},\n        {\n\n                0x10, 0xFC, 0x23, 0xEA, 0xBF, 0xAA, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x00, 0x0F, 0x08, 0x07, 0x08,\n                0x0F, 0x08, 0x05, 0x02, 0x05, 0x08,/*傲32*/},\n        {\n\n                0x00, 0xFE, 0x12, 0x5A, 0x13, 0x7E, 0x12, 0x5A, 0x12, 0xFE, 0x00, 0x0A, 0x0A, 0x0A, 0x06, 0x02,\n                0x03, 0x02, 0x06, 0x0A, 0x0A, 0x0A,/*奥33*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x5A, 0x13, 0x7E, 0x12, 0x5A, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*懊34*/},\n        {\n\n                0x11, 0x22, 0xFE, 0x12, 0x5A, 0x13, 0x7E, 0x12, 0x5A, 0x12, 0xFE, 0x04, 0x02, 0x0A, 0x0A, 0x06,\n                0x02, 0x03, 0x02, 0x06, 0x0A, 0x0A,/*澳35*/},\n        {\n\n                0x02, 0xF2, 0x92, 0x97, 0x92, 0xF2, 0x92, 0x97, 0x92, 0xF2, 0x02, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*芭36*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x80, 0x9E, 0xF2, 0x9E, 0x00, 0xFC, 0x00, 0xFF, 0x08, 0x0F, 0x08, 0x04, 0x03,\n                0x08, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*捌37*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x08, 0x0F, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x01, 0x06, 0x08,/*扒38*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x03, 0x01, 0x03, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x01, 0x06, 0x08,/*叭39*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x42, 0x42, 0x7E, 0x42, 0x42, 0x7E, 0x03, 0x01, 0x03, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*吧40*/},\n        {\n\n                0x04, 0xF3, 0x92, 0x96, 0x92, 0xF4, 0x93, 0x92, 0x96, 0xF2, 0x02, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*笆41*/},\n        {\n\n                0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x7F, 0x80, 0x00, 0x00, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x01, 0x06, 0x08,/*八42*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0xF4, 0x95, 0x96, 0xF4, 0x94, 0x94, 0xF4, 0x09, 0x04, 0x03, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*疤43*/},\n        {\n\n                0x00, 0xFE, 0x42, 0x42, 0x42, 0x7E, 0x42, 0x42, 0x42, 0x7E, 0x00, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*巴44*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xC8, 0x3F, 0xE8, 0x29, 0x2A, 0xE8, 0x00, 0x08, 0x0F, 0x08, 0x06,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*拔45*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x08, 0xC8, 0x3F, 0xE8, 0x29, 0x2A, 0xE8, 0x07, 0x04, 0x03, 0x0A, 0x06,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*跋46*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x00, 0xFE, 0x42, 0x7E, 0x42, 0x7E, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*靶47*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x42, 0x42, 0x7E, 0x42, 0x42, 0x7E, 0x08, 0x0F, 0x00, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*把48*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x00, 0xFE, 0x42, 0x7E, 0x42, 0x42, 0x7E, 0x02, 0x01, 0x0F, 0x01, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*耙49*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x00, 0xFE, 0x02, 0x02, 0xFA, 0x02, 0x02, 0xFE, 0x02, 0x03, 0x01, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*坝50*/},\n        {\n\n                0x4C, 0xE5, 0x4D, 0x45, 0x45, 0xEF, 0x45, 0xE5, 0xAD, 0xA5, 0xEC, 0x04, 0x05, 0x05, 0x0F, 0x05,\n                0x05, 0x08, 0x07, 0x02, 0x0A, 0x0F,/*霸51*/},\n        {\n\n                0x80, 0xAF, 0xA9, 0xA9, 0xAF, 0xF9, 0xAF, 0xA9, 0xA9, 0xAF, 0x80, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x04, 0x06, 0x0C, 0x00,/*罢52*/},\n        {\n\n                0x20, 0x24, 0xD2, 0x55, 0x48, 0xC8, 0x48, 0x55, 0xD2, 0x24, 0x20, 0x00, 0x00, 0x07, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0C, 0x00,/*爸53*/},\n        {\n\n                0x00, 0xFC, 0x44, 0x46, 0x45, 0x44, 0x44, 0x44, 0x44, 0xFC, 0x00, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*白54*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFC, 0x44, 0x46, 0x45, 0x44, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*柏55*/},\n        {\n\n                0x02, 0xF2, 0x92, 0x92, 0x9A, 0x96, 0x92, 0x92, 0x92, 0xF2, 0x02, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*百56*/},\n        {\n\n                0x84, 0x84, 0xFF, 0x44, 0x8F, 0xA9, 0xAF, 0xF9, 0xAF, 0xA9, 0x8F, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*摆57*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xF2, 0x92, 0x9A, 0x96, 0x92, 0x92, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*佰58*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x10, 0xEC, 0x0B, 0x08, 0xF8, 0x08, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*败59*/},\n        {\n\n                0x92, 0x92, 0xFE, 0x91, 0x91, 0x00, 0x29, 0x29, 0xFF, 0x29, 0x29, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x01, 0x01, 0x0F, 0x01, 0x01,/*拜60*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x01, 0x00, 0x0F, 0x00, 0x02,\n                0x03, 0x02, 0x02, 0x0F, 0x02, 0x02,/*稗61*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x08, 0x69, 0x8A, 0x78, 0x08, 0x42, 0xFE, 0x42, 0x04, 0x07, 0x02, 0x04, 0x02,\n                0x01, 0x06, 0x00, 0x08, 0x0F, 0x08,/*斑62*/},\n        {\n\n                0x22, 0xFE, 0xA2, 0x78, 0x00, 0xFF, 0x00, 0x42, 0xFE, 0x42, 0x42, 0x04, 0x07, 0x02, 0x08, 0x06,\n                0x01, 0x08, 0x08, 0x0F, 0x08, 0x08,/*班63*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xFC, 0x56, 0xFD, 0x10, 0xCE, 0x42, 0xDE, 0x10, 0x08, 0x0F, 0x08, 0x07, 0x09,\n                0x0F, 0x08, 0x05, 0x02, 0x05, 0x08,/*搬64*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFE, 0x12, 0xF2, 0x12, 0x91, 0x71, 0x00, 0x08, 0x0F, 0x08, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*扳65*/},\n        {\n\n                0x40, 0xFC, 0x56, 0x65, 0xFC, 0x10, 0xCE, 0x42, 0x42, 0xDE, 0x10, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x08, 0x05, 0x02, 0x02, 0x05, 0x08,/*般66*/},\n        {\n\n                0x28, 0xE6, 0x20, 0x23, 0xEC, 0x00, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颁67*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFE, 0x12, 0xF2, 0x12, 0x91, 0x71, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*板68*/},\n        {\n\n                0x00, 0xFE, 0x90, 0x9F, 0x10, 0xFE, 0x12, 0xF2, 0x12, 0x91, 0x71, 0x08, 0x07, 0x00, 0x0F, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*版69*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0x2C, 0xE3, 0x20, 0x23, 0xEC, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x08, 0x08, 0x07, 0x00,/*扮70*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x82, 0x94, 0x90, 0xFF, 0x90, 0x94, 0x82, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*拌71*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x82, 0x94, 0x90, 0xFF, 0x90, 0x94, 0x82, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*伴72*/},\n        {\n\n                0x55, 0xE6, 0x54, 0x00, 0xFE, 0x02, 0xFD, 0x20, 0x55, 0xE6, 0x54, 0x09, 0x07, 0x09, 0x06, 0x01,\n                0x0E, 0x09, 0x0C, 0x01, 0x0F, 0x01,/*瓣73*/},\n        {\n\n                0x80, 0x90, 0x92, 0x94, 0x90, 0xFF, 0x90, 0x94, 0x92, 0x90, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*半74*/},\n        {\n\n                0x00, 0xE8, 0x08, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x00, 0x20, 0xC0, 0x01, 0x08, 0x04, 0x03, 0x08,\n                0x08, 0x08, 0x07, 0x00, 0x00, 0x01,/*办75*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x82, 0x94, 0x90, 0xFF, 0x90, 0x94, 0x82, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*绊76*/},\n        {\n\n                0x80, 0x92, 0x92, 0xFF, 0x92, 0x92, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邦77*/},\n        {\n\n                0x22, 0xAA, 0x6A, 0x3F, 0x2A, 0xAA, 0x00, 0xFE, 0x42, 0x4A, 0x36, 0x01, 0x07, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x05, 0x07, 0x00,/*帮78*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x92, 0xFF, 0x92, 0x00, 0xFE, 0x32, 0xCE, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x02, 0x01,/*梆79*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xB2, 0x96, 0x9A, 0xD3, 0x9A, 0x96, 0xB2, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x02, 0x0A, 0x0A, 0x06,/*榜80*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xB2, 0x96, 0xBB, 0xDA, 0x96, 0xB2, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x08, 0x07, 0x02, 0x0A, 0x0A, 0x06,/*膀81*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0x24, 0xFF, 0x24, 0x00, 0xFE, 0x32, 0xCE, 0x04, 0x04, 0x02, 0x08, 0x05,\n                0x03, 0x01, 0x00, 0x0F, 0x02, 0x01,/*绑82*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xA2, 0x6A, 0x3A, 0xAF, 0x2A, 0x6A, 0xA2, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x04,/*棒83*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xB2, 0x96, 0xBB, 0xDA, 0x96, 0xB2, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x08, 0x07, 0x02, 0x0A, 0x0A, 0x06,/*磅84*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x01, 0x01, 0x0F, 0x01, 0x01,/*蚌85*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xB2, 0x96, 0x9A, 0xD3, 0x9A, 0x96, 0xB2, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x04, 0x03, 0x02, 0x0A, 0x0A, 0x06,/*镑86*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xB2, 0x96, 0x9A, 0xD3, 0x9A, 0x96, 0xB2, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x02, 0x0A, 0x0A, 0x06,/*傍87*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xB2, 0x96, 0x9A, 0xB3, 0xD2, 0x9A, 0x96, 0xB2, 0x00, 0x07, 0x02, 0x08, 0x04,\n                0x03, 0x02, 0x02, 0x0A, 0x0A, 0x06,/*谤88*/},\n        {\n\n                0x42, 0x22, 0xDA, 0x57, 0x52, 0x52, 0xD2, 0x17, 0x12, 0xF2, 0x02, 0x00, 0x00, 0x07, 0x09, 0x09,\n                0x09, 0x09, 0x08, 0x0A, 0x0B, 0x0C,/*苞89*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x08, 0xF4, 0x97, 0x94, 0xF4, 0x04, 0xFC, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x09, 0x0D,/*胞90*/},\n        {\n\n                0x10, 0x08, 0xF7, 0x94, 0x94, 0x94, 0xF4, 0x04, 0x04, 0xFC, 0x00, 0x00, 0x00, 0x07, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x09, 0x09, 0x0E,/*包91*/},\n        {\n\n                0x12, 0x0A, 0xFE, 0x02, 0xA2, 0xEF, 0x2A, 0xFA, 0x2A, 0x6E, 0xA2, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*褒92*/},\n        {\n\n                0x51, 0x95, 0x15, 0xF5, 0x15, 0x9F, 0x50, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x09, 0x0F, 0x01,\n                0x02, 0x04, 0x00, 0x01, 0x08, 0x0F,/*剥93*/},\n        {\n\n                0x4A, 0x92, 0x02, 0x17, 0xF2, 0x52, 0xFA, 0x57, 0x52, 0xFA, 0x12, 0x08, 0x04, 0x00, 0x01, 0x03,\n                0x05, 0x01, 0x09, 0x0F, 0x01, 0x01,/*薄94*/},\n        {\n\n                0x8C, 0x45, 0xB5, 0xAD, 0xA5, 0xAF, 0xA5, 0x2D, 0x25, 0xE5, 0x0C, 0x00, 0x00, 0x07, 0x0A, 0x0A,\n                0x0A, 0x0B, 0x08, 0x0A, 0x0B, 0x0C,/*雹95*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x40, 0x5E, 0x52, 0xF2, 0x52, 0x5E, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*保96*/},\n        {\n\n                0x08, 0x04, 0xFE, 0x01, 0x50, 0x37, 0x15, 0xFD, 0x15, 0x37, 0x50, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*堡97*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x2C, 0x10, 0xFC, 0x97, 0x94, 0xF4, 0x04, 0xFC, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x09, 0x0D,/*饱98*/},\n        {\n\n                0x0C, 0x24, 0x24, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x24, 0x24, 0x0C, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x0B, 0x0D, 0x09, 0x08,/*宝99*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x08, 0xF4, 0x97, 0x94, 0xF4, 0x04, 0xFC, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x09, 0x0D,/*抱100*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFE, 0x42, 0xC2, 0x52, 0x52, 0xCE, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x08, 0x05, 0x02, 0x05, 0x08,/*报101*/},\n        {\n\n                0x00, 0x5F, 0x55, 0xF5, 0x55, 0x55, 0x55, 0xF5, 0x55, 0x5F, 0x00, 0x05, 0x05, 0x0B, 0x05, 0x09,\n                0x0F, 0x01, 0x05, 0x0B, 0x05, 0x05,/*暴102*/},\n        {\n\n                0xA4, 0xAA, 0x55, 0xA8, 0xC4, 0x10, 0x08, 0x27, 0xC4, 0x04, 0xFC, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*豹103*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x08, 0xF4, 0x97, 0xF4, 0x04, 0xFC, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x07, 0x08, 0x08, 0x09, 0x0D,/*鲍104*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x00, 0x5F, 0xF5, 0x55, 0xF5, 0x5F, 0x00, 0x08, 0x06, 0x01, 0x06, 0x05,\n                0x0B, 0x05, 0x0F, 0x05, 0x0B, 0x05,/*爆105*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x42, 0x22, 0xFA, 0x06, 0x22, 0xC2, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*杯106*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x00, 0x0F, 0x04, 0x0F, 0x02,\n                0x03, 0x02, 0x02, 0x0F, 0x02, 0x02,/*碑107*/},\n        {\n\n                0x22, 0x2A, 0x2A, 0x7F, 0x00, 0x80, 0x00, 0x7F, 0x2A, 0x2A, 0x22, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*悲108*/},\n        {\n\n                0x00, 0x7C, 0x54, 0xD4, 0x76, 0x5D, 0xD4, 0x54, 0x54, 0x7C, 0x00, 0x02, 0x02, 0x03, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*卑109*/},\n        {\n\n                0x10, 0x10, 0x10, 0xFF, 0x00, 0x00, 0xFF, 0x20, 0x10, 0x08, 0x04, 0x02, 0x02, 0x01, 0x0F, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*北110*/},\n        {\n\n                0x0A, 0x4A, 0x4A, 0xDF, 0x60, 0xC0, 0x40, 0x5F, 0x4A, 0x4A, 0x0A, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x05, 0x04, 0x04,/*辈111*/},\n        {\n\n                0x12, 0x12, 0xEA, 0xBF, 0xA0, 0xA0, 0xA7, 0xAA, 0xEA, 0x09, 0x0C, 0x00, 0x00, 0x0F, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0F, 0x00, 0x00,/*背112*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0x02, 0xFA, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x08, 0x09, 0x04, 0x02, 0x01,\n                0x00, 0x02, 0x02, 0x04, 0x05, 0x08,/*贝113*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x02, 0x02, 0xFA, 0x02, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*钡114*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x20, 0xAA, 0xB2, 0xA2, 0xA3, 0xB2, 0xAA, 0x20, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*倍115*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xFE, 0x02, 0x02, 0xFA, 0x02, 0x02, 0xFE, 0x08, 0x08, 0x07, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*狈116*/},\n        {\n\n                0x20, 0x24, 0xD2, 0x57, 0x4A, 0xCA, 0x4A, 0x56, 0xD2, 0x20, 0x20, 0x00, 0x00, 0x0F, 0x05, 0x05,\n                0x07, 0x05, 0x05, 0x0F, 0x00, 0x00,/*备117*/},\n        {\n\n                0x10, 0x12, 0xF9, 0x5B, 0x55, 0xF5, 0x55, 0x5B, 0xF9, 0x10, 0x10, 0x08, 0x06, 0x01, 0x07, 0x09,\n                0x0B, 0x0D, 0x09, 0x0D, 0x02, 0x0C,/*惫118*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x20, 0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x20, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*焙119*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0xFC, 0x24, 0xE4, 0x3F, 0xE4, 0x0C, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*被120*/},\n        {\n\n                0x20, 0x24, 0x14, 0xAC, 0x26, 0x75, 0x24, 0xAC, 0x14, 0x24, 0x20, 0x01, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*奔121*/},\n        {\n\n                0x12, 0x12, 0x12, 0x97, 0x52, 0xFA, 0x52, 0x97, 0x12, 0x12, 0x12, 0x02, 0x02, 0x01, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x01, 0x02, 0x02,/*苯122*/},\n        {\n\n                0x04, 0x04, 0x84, 0x64, 0x14, 0xFF, 0x14, 0x64, 0x84, 0x04, 0x04, 0x02, 0x01, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x01, 0x02,/*本123*/},\n        {\n\n                0x14, 0x13, 0x12, 0x96, 0x52, 0xFC, 0x53, 0x92, 0x16, 0x12, 0x12, 0x02, 0x02, 0x01, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x01, 0x02, 0x02,/*笨124*/},\n        {\n\n                0x00, 0xF6, 0x54, 0x54, 0xF4, 0x07, 0xF4, 0x54, 0x54, 0xF6, 0x00, 0x08, 0x07, 0x01, 0x09, 0x0F,\n                0x08, 0x07, 0x01, 0x09, 0x0F, 0x00,/*崩125*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x92, 0xFE, 0x04, 0x04, 0x02, 0x08, 0x07,\n                0x08, 0x0F, 0x08, 0x07, 0x08, 0x0F,/*绷126*/},\n        {\n\n                0x09, 0xE9, 0xA9, 0xA5, 0xA5, 0xEF, 0xA1, 0xA5, 0xA5, 0xE9, 0x09, 0x08, 0x07, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*甭127*/},\n        {\n\n                0x91, 0x89, 0xBD, 0xA7, 0x25, 0xE5, 0xA5, 0x25, 0xA5, 0x7D, 0x01, 0x04, 0x04, 0x02, 0x01, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*泵128*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0xF6, 0x54, 0xF4, 0x07, 0xF4, 0x54, 0xF6, 0x07, 0x04, 0x03, 0x0A, 0x07,\n                0x09, 0x0F, 0x08, 0x07, 0x09, 0x0F,/*蹦129*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x44, 0x45, 0xFE, 0x44, 0x44, 0xFE, 0x45, 0x44, 0x08, 0x07, 0x08, 0x0C, 0x0A,\n                0x09, 0x08, 0x08, 0x0F, 0x08, 0x08,/*迸130*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xE1, 0xAF, 0xAB, 0xEB, 0xAB, 0xAF, 0xE1, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x0B,/*逼131*/},\n        {\n\n                0x00, 0xE0, 0xBE, 0xAA, 0xAB, 0xEA, 0xAA, 0xAA, 0xBE, 0xE0, 0x00, 0x02, 0x0B, 0x06, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x0E, 0x03, 0x02,/*鼻132*/},\n        {\n\n                0x00, 0xFF, 0x10, 0x10, 0x10, 0x00, 0xFF, 0x20, 0x10, 0x08, 0x04, 0x00, 0x0F, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*比133*/},\n        {\n\n                0xD0, 0x57, 0x55, 0x7D, 0x55, 0x57, 0xD0, 0x00, 0xFF, 0x31, 0xCF, 0x0F, 0x08, 0x0F, 0x0D, 0x0F,\n                0x08, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*鄙134*/},\n        {\n\n                0x08, 0x24, 0xA3, 0xA6, 0xAA, 0xE2, 0x54, 0x53, 0x56, 0x1A, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x07, 0x09, 0x09, 0x09, 0x09, 0x0C,/*笔135*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0xFC, 0x24, 0xE4, 0x3F, 0x24, 0xE4, 0x0C, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*彼136*/},\n        {\n\n                0xAA, 0xAA, 0xBE, 0xAA, 0xAA, 0x80, 0xBE, 0xAB, 0xAA, 0xAA, 0xBE, 0x08, 0x04, 0x0E, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*碧137*/},\n        {\n\n                0x02, 0xFA, 0x8A, 0xDF, 0xAA, 0xAE, 0xAA, 0xDF, 0x8A, 0xFA, 0x02, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x00, 0x07, 0x0A, 0x0A, 0x09, 0x0C,/*蓖138*/},\n        {\n\n                0xCA, 0x52, 0x47, 0xFA, 0x52, 0xCA, 0x42, 0xBA, 0x27, 0xE2, 0x22, 0x0F, 0x02, 0x01, 0x07, 0x09,\n                0x0F, 0x08, 0x05, 0x02, 0x05, 0x08,/*蔽139*/},\n        {\n\n                0x00, 0x3F, 0x24, 0x14, 0x14, 0xC0, 0x1F, 0x24, 0x22, 0x21, 0x38, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*毕140*/},\n        {\n\n                0x40, 0x5F, 0xD2, 0x4A, 0x4A, 0x40, 0xCF, 0x54, 0x52, 0x51, 0x58, 0x0A, 0x0B, 0x05, 0x05, 0x03,\n                0x00, 0x07, 0x0A, 0x0A, 0x09, 0x0C,/*毙141*/},\n        {\n\n                0x00, 0x3F, 0x24, 0x14, 0x54, 0x80, 0x1F, 0x24, 0xA2, 0x21, 0x38, 0x0A, 0x09, 0x08, 0x07, 0x0C,\n                0x0A, 0x0A, 0x09, 0x0C, 0x02, 0x04,/*毖142*/},\n        {\n\n                0x02, 0xF2, 0x12, 0x12, 0x12, 0xFE, 0x11, 0x11, 0x11, 0xF1, 0x01, 0x00, 0x07, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x04, 0x07, 0x00,/*币143*/},\n        {\n\n                0x00, 0xFC, 0x04, 0xF4, 0x44, 0x45, 0x06, 0xF4, 0x04, 0x84, 0x64, 0x08, 0x07, 0x00, 0x0F, 0x08,\n                0x04, 0x00, 0x07, 0x09, 0x08, 0x0E,/*庇144*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xFA, 0xAA, 0xAB, 0xFA, 0xAA, 0xAA, 0xFA, 0x09, 0x04, 0x03, 0x08, 0x0A,\n                0x06, 0x02, 0x02, 0x02, 0x0E, 0x02,/*痹145*/},\n        {\n\n                0x00, 0xF9, 0x02, 0x20, 0x20, 0xA2, 0xFA, 0x22, 0x22, 0x02, 0xFE, 0x00, 0x0F, 0x00, 0x02, 0x01,\n                0x04, 0x07, 0x00, 0x08, 0x08, 0x0F,/*闭146*/},\n        {\n\n                0xF2, 0x94, 0x50, 0xFF, 0x94, 0xF2, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x0F, 0x00, 0x00, 0x03, 0x08,\n                0x0F, 0x08, 0x05, 0x02, 0x05, 0x08,/*敝147*/},\n        {\n\n                0x7D, 0x26, 0x14, 0xBF, 0x16, 0x3D, 0x44, 0xAB, 0x12, 0x2E, 0x42, 0x01, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*弊148*/},\n        {\n\n                0x80, 0x70, 0x00, 0xFC, 0x01, 0x86, 0x60, 0x18, 0x06, 0x20, 0xC0, 0x00, 0x08, 0x04, 0x07, 0x09,\n                0x08, 0x08, 0x08, 0x0E, 0x00, 0x00,/*必149*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x9E, 0x40, 0x54, 0x65, 0xC6, 0x64, 0x54, 0x40, 0x01, 0x0F, 0x04, 0x0F, 0x00,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x00,/*辟150*/},\n        {\n\n                0x40, 0x3E, 0xEA, 0xAA, 0xEE, 0x00, 0x12, 0x56, 0xFB, 0x56, 0x12, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*壁151*/},\n        {\n\n                0x20, 0x9F, 0xF5, 0xD5, 0xF7, 0x80, 0x8A, 0xAE, 0xFB, 0xAE, 0x0A, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*臂152*/},\n        {\n\n                0x11, 0xF2, 0x80, 0xFE, 0x52, 0xDE, 0x20, 0x2A, 0xF3, 0x2A, 0x20, 0x08, 0x07, 0x08, 0x0B, 0x0A,\n                0x0B, 0x08, 0x09, 0x0F, 0x09, 0x08,/*避153*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x00, 0x3F, 0x24, 0x14, 0xC0, 0x1F, 0x24, 0x32, 0x0F, 0x02, 0x01, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*陛154*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0x12, 0xFC, 0xAB, 0xAA, 0xFE, 0xAA, 0xFA, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x0F, 0x01, 0x0A, 0x07, 0x08, 0x08,/*鞭155*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x08, 0x88, 0x7F, 0x08, 0x08, 0x08, 0xF8, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x09, 0x08, 0x0A, 0x0A, 0x0A, 0x09,/*边156*/},\n        {\n\n                0xDC, 0xB3, 0x08, 0x80, 0xFE, 0x2A, 0xEA, 0x2B, 0xEA, 0x2A, 0xEE, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*编157*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x22, 0x2A, 0x32, 0xA1, 0x61, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x04, 0x06, 0x09, 0x08, 0x08,/*贬158*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xEA, 0x2A, 0xEA, 0x2B, 0xEA, 0x2A, 0x2A, 0xEE, 0x08, 0x07, 0x00, 0x0F, 0x01,\n                0x07, 0x01, 0x07, 0x01, 0x09, 0x0F,/*扁159*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xFA, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x05, 0x02, 0x05, 0x08, 0x08, 0x08,/*便160*/},\n        {\n\n                0x12, 0x4A, 0xC2, 0x5E, 0x42, 0x43, 0x42, 0x5E, 0xC2, 0x0A, 0x12, 0x08, 0x08, 0x04, 0x05, 0x02,\n                0x02, 0x02, 0x05, 0x04, 0x08, 0x08,/*变161*/},\n        {\n\n                0x08, 0x08, 0x08, 0x08, 0x09, 0xFA, 0x08, 0x48, 0x88, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x01, 0x00,/*卞162*/},\n        {\n\n                0x44, 0x55, 0xE6, 0x54, 0x20, 0xFF, 0x40, 0x55, 0xE6, 0x54, 0x40, 0x00, 0x09, 0x07, 0x01, 0x08,\n                0x07, 0x00, 0x01, 0x0F, 0x01, 0x00,/*辨163*/},\n        {\n\n                0x44, 0x55, 0xE6, 0x54, 0x08, 0xFA, 0x40, 0x55, 0xE6, 0x54, 0x40, 0x00, 0x09, 0x07, 0x01, 0x00,\n                0x07, 0x02, 0x01, 0x0F, 0x01, 0x00,/*辩164*/},\n        {\n\n                0x55, 0xE6, 0x54, 0x00, 0xDC, 0xB3, 0x88, 0x00, 0x55, 0xE6, 0x54, 0x09, 0x07, 0x01, 0x00, 0x04,\n                0x04, 0x02, 0x00, 0x01, 0x0F, 0x01,/*辫165*/},\n        {\n\n                0x11, 0xF2, 0x40, 0xFE, 0xAA, 0xEA, 0xAB, 0xEA, 0xAA, 0xEE, 0x00, 0x08, 0x07, 0x08, 0x0B, 0x08,\n                0x09, 0x08, 0x09, 0x0A, 0x0B, 0x08,/*遍166*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0x92, 0x12, 0xF2, 0x12, 0x92, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*标167*/},\n        {\n\n                0x00, 0xF8, 0x48, 0x7F, 0xAA, 0xAA, 0xD8, 0x00, 0x24, 0x92, 0x49, 0x08, 0x07, 0x08, 0x06, 0x02,\n                0x06, 0x08, 0x0A, 0x09, 0x08, 0x0C,/*彪168*/},\n        {\n\n                0xFF, 0x49, 0xFF, 0x00, 0x1D, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x07, 0x08, 0x0F, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*膘169*/},\n        {\n\n                0x40, 0x44, 0x54, 0x54, 0xD4, 0x7F, 0xD4, 0x54, 0x54, 0x44, 0x40, 0x04, 0x04, 0x02, 0x0F, 0x08,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*表170*/},\n        {\n\n                0x3D, 0x94, 0xFF, 0xAC, 0xB6, 0xBD, 0xE4, 0xB7, 0x8A, 0x16, 0x22, 0x08, 0x08, 0x0F, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x08, 0x08,/*鳖171*/},\n        {\n\n                0xFD, 0x24, 0xFF, 0x14, 0xA6, 0xFD, 0x84, 0x5B, 0x22, 0x5E, 0x82, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x0A, 0x0C, 0x08, 0x0C, 0x02, 0x0C,/*憋172*/},\n        {\n\n                0x40, 0x5F, 0x51, 0xF1, 0x51, 0x51, 0xDF, 0x00, 0xFC, 0x00, 0xFF, 0x08, 0x04, 0x03, 0x08, 0x08,\n                0x08, 0x07, 0x00, 0x01, 0x08, 0x0F,/*别173*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xFA, 0xAE, 0xCB, 0x9A, 0xAA, 0xFA, 0x02, 0x09, 0x04, 0x03, 0x04, 0x02,\n                0x07, 0x0A, 0x0A, 0x0D, 0x02, 0x04,/*瘪174*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xC8, 0xFF, 0x48, 0x88, 0x44, 0x33, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x0F, 0x00, 0x08, 0x04, 0x03,/*彬175*/},\n        {\n\n                0xC9, 0x0A, 0xF8, 0x08, 0x90, 0x12, 0xF2, 0x90, 0xFF, 0x12, 0x14, 0x0C, 0x03, 0x04, 0x08, 0x0F,\n                0x08, 0x07, 0x04, 0x03, 0x04, 0x0E,/*斌176*/},\n        {\n\n                0x22, 0x44, 0x10, 0x9E, 0x10, 0xDF, 0x14, 0xF2, 0x9A, 0x16, 0xF2, 0x04, 0x02, 0x08, 0x09, 0x04,\n                0x03, 0x09, 0x04, 0x03, 0x04, 0x08,/*濒177*/},\n        {\n\n                0x22, 0x44, 0x00, 0x06, 0xFA, 0x2A, 0x2B, 0x2A, 0xE6, 0x22, 0x26, 0x04, 0x02, 0x00, 0x09, 0x05,\n                0x01, 0x01, 0x01, 0x05, 0x09, 0x01,/*滨178*/},\n        {\n\n                0x06, 0x02, 0xFA, 0x2A, 0x2A, 0x2B, 0x2A, 0xE6, 0x22, 0x22, 0x06, 0x01, 0x09, 0x05, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x05, 0x09, 0x01,/*宾179*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x06, 0xFA, 0x2A, 0x2B, 0xE6, 0x22, 0x26, 0x00, 0x08, 0x0F, 0x00, 0x09,\n                0x05, 0x01, 0x01, 0x05, 0x09, 0x01,/*摈180*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x00, 0x01, 0x09, 0x05, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x05, 0x09, 0x01,/*兵181*/},\n        {\n\n                0x02, 0x04, 0x90, 0x10, 0xF0, 0x00, 0xFF, 0x18, 0xE0, 0x10, 0x08, 0x02, 0x01, 0x04, 0x03, 0x00,\n                0x08, 0x0F, 0x00, 0x00, 0x03, 0x04,/*冰182*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xF2, 0x12, 0x92, 0x7E, 0x92, 0x12, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x00, 0x00, 0x00, 0x09, 0x0F,/*柄183*/},\n        {\n\n                0xF2, 0x12, 0x12, 0x12, 0x92, 0x7E, 0x92, 0x12, 0x12, 0x12, 0xF2, 0x0F, 0x00, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x01, 0x02, 0x08, 0x0F,/*丙184*/},\n        {\n\n                0x88, 0xA8, 0xAA, 0xAA, 0xAA, 0xFE, 0xA9, 0xA9, 0xA9, 0xE8, 0x88, 0x00, 0x0A, 0x0A, 0x06, 0x02,\n                0x0F, 0x02, 0x06, 0x0A, 0x0B, 0x00,/*秉185*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x80, 0x89, 0xFA, 0x88, 0x88, 0xFA, 0x89, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*饼186*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xF6, 0x12, 0x92, 0x7E, 0x92, 0x12, 0xF2, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x01, 0x00, 0x00, 0x00, 0x09, 0x0F,/*炳187*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0xD4, 0x55, 0x56, 0xF4, 0x54, 0x54, 0xD4, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x02, 0x01, 0x00, 0x01, 0x0A, 0x0F,/*病188*/},\n        {\n\n                0x80, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x88, 0xFA, 0x89, 0x88, 0x80, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*并189*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xFC, 0x24, 0xE4, 0x3F, 0x24, 0xE4, 0x0C, 0x04, 0x07, 0x02, 0x08, 0x07,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*玻190*/},\n        {\n\n                0x22, 0x4A, 0x12, 0x07, 0xF2, 0x92, 0x92, 0xFF, 0x92, 0x92, 0x32, 0x04, 0x02, 0x09, 0x04, 0x03,\n                0x08, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*菠191*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xD6, 0xBA, 0x92, 0xBE, 0x91, 0xB9, 0xD5, 0x90, 0x08, 0x0F, 0x00, 0x0F, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0F, 0x00,/*播192*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x0E, 0xC8, 0x78, 0x4F, 0x48, 0xC9, 0x0A, 0x08, 0x0F, 0x00, 0x04, 0x0B,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*拨193*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xC4, 0x34, 0xFF, 0x34, 0xC4, 0x04, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x01,/*钵194*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFC, 0x24, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x0C, 0x04, 0x02, 0x08, 0x07, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*波195*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFA, 0x2A, 0x2A, 0xFF, 0x2A, 0x2B, 0xFA, 0x00, 0x0F, 0x00, 0x00, 0x02,\n                0x06, 0x0A, 0x02, 0x0A, 0x0F, 0x02,/*博196*/},\n        {\n\n                0x18, 0x2A, 0x2A, 0xAF, 0x6A, 0x2A, 0x18, 0x10, 0xFF, 0x10, 0xF0, 0x02, 0x02, 0x0A, 0x0F, 0x01,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*勃197*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFA, 0x2A, 0x2A, 0xFF, 0x2A, 0x2B, 0xFA, 0x08, 0x0F, 0x00, 0x00, 0x02,\n                0x06, 0x0A, 0x02, 0x0A, 0x0F, 0x02,/*搏198*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFC, 0x44, 0x46, 0x45, 0x44, 0xFC, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*铂199*/},\n        {\n\n                0x44, 0x8B, 0x16, 0x02, 0xF2, 0x94, 0x93, 0x9A, 0x96, 0x92, 0xF2, 0x08, 0x04, 0x02, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*箔200*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x00, 0xFC, 0x44, 0x46, 0x45, 0x44, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*伯201*/},\n        {\n\n                0x80, 0xBE, 0xAA, 0xAA, 0xAB, 0xEA, 0xAA, 0xAA, 0xAA, 0xBE, 0x80, 0x07, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x04, 0x07,/*帛202*/},\n        {\n\n                0x40, 0xFC, 0x56, 0x65, 0xFC, 0x00, 0xFC, 0x46, 0x45, 0x44, 0xFC, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*舶203*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x1A, 0x2A, 0x2A, 0xAF, 0x6A, 0x1A, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x01, 0x01, 0x09, 0x0F, 0x01, 0x01,/*脖204*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x00, 0xFA, 0x2A, 0xFF, 0x2A, 0xFB, 0x02, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x06, 0x02, 0x0A, 0x0F, 0x02, 0x02,/*膊205*/},\n        {\n\n                0x22, 0x44, 0x1A, 0x2A, 0xAF, 0x6A, 0x1A, 0x04, 0xFF, 0x04, 0xFC, 0x04, 0x02, 0x00, 0x09, 0x0F,\n                0x01, 0x09, 0x06, 0x09, 0x08, 0x07,/*渤206*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFC, 0x44, 0x46, 0x45, 0x44, 0x44, 0x44, 0xFC, 0x04, 0x02, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*泊207*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x00, 0xD1, 0x0A, 0x04, 0x0A, 0xD1, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x08, 0x08, 0x05, 0x02, 0x05, 0x08,/*驳208*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xF4, 0x54, 0x54, 0xFF, 0x54, 0x55, 0xF6, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*捕209*/},\n        {\n\n                0x00, 0x00, 0x00, 0xFF, 0x00, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*卜210*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xF4, 0x54, 0x54, 0xFF, 0x54, 0x55, 0xF6, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*哺211*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0xA0, 0x00, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*补212*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0xFE, 0xAA, 0xAB, 0xAA, 0xAE, 0xE0, 0x02, 0x02, 0x01, 0x01, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*埠213*/},\n        {\n\n                0x02, 0x02, 0x82, 0x42, 0x22, 0xF2, 0x0E, 0x22, 0x42, 0x82, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x01,/*不214*/},\n        {\n\n                0x04, 0xC4, 0x34, 0xEC, 0x27, 0x24, 0xFC, 0x24, 0x24, 0xE4, 0x04, 0x01, 0x00, 0x00, 0x07, 0x00,\n                0x00, 0x0F, 0x00, 0x04, 0x07, 0x00,/*布215*/},\n        {\n\n                0x20, 0x20, 0x3E, 0xA0, 0x20, 0xBF, 0x24, 0x24, 0x24, 0xA4, 0x20, 0x00, 0x0A, 0x09, 0x08, 0x04,\n                0x07, 0x02, 0x02, 0x01, 0x00, 0x00,/*步216*/},\n        {\n\n                0x4C, 0x93, 0x02, 0x16, 0xF2, 0x54, 0xFB, 0x52, 0x56, 0xFA, 0x12, 0x08, 0x04, 0x00, 0x01, 0x03,\n                0x05, 0x01, 0x09, 0x0F, 0x01, 0x01,/*簿217*/},\n        {\n\n                0x20, 0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x20, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x0F, 0x00, 0x0F, 0x02, 0x02, 0x01,/*部218*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x48, 0x24, 0xFC, 0x27, 0xF4, 0x24, 0x24, 0xE4, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x00, 0x0F, 0x00, 0x04, 0x07,/*怖219*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x20, 0x56, 0x2A, 0x5A, 0x43, 0x5A, 0x2A, 0x5E, 0x08, 0x0F, 0x00, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*擦220*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xAA, 0xEA, 0x22, 0x08, 0x08, 0x07, 0x00, 0x0F,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*猜221*/},\n        {\n\n                0x48, 0x4A, 0x5A, 0xEF, 0x4A, 0x4A, 0x08, 0xFF, 0x08, 0xE9, 0x0A, 0x04, 0x02, 0x0F, 0x04, 0x01,\n                0x06, 0x09, 0x04, 0x03, 0x04, 0x0E,/*裁222*/},\n        {\n\n                0x08, 0x88, 0x68, 0xFF, 0x28, 0x48, 0x80, 0x48, 0x28, 0xFF, 0x08, 0x01, 0x00, 0x00, 0x0F, 0x00,\n                0x01, 0x00, 0x00, 0x08, 0x0F, 0x00,/*材223*/},\n        {\n\n                0x00, 0x08, 0x08, 0x08, 0x88, 0x48, 0x28, 0x18, 0xFF, 0x08, 0x08, 0x02, 0x02, 0x01, 0x01, 0x00,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*才224*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x08, 0x88, 0x68, 0xFF, 0x08, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x02, 0x01, 0x00, 0x08, 0x0F, 0x00,/*财225*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x4A, 0x52, 0x46, 0xEA, 0x41, 0x51, 0x4D, 0x0F, 0x04, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*睬226*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x80, 0x4A, 0x52, 0x46, 0xEA, 0x41, 0x51, 0x4D, 0x0F, 0x08, 0x07, 0x04, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*踩227*/},\n        {\n\n                0x40, 0x4A, 0x52, 0x42, 0xC6, 0xEA, 0xC1, 0x41, 0x51, 0x49, 0x40, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*采228*/},\n        {\n\n                0x4A, 0x52, 0x46, 0xE9, 0x51, 0x4D, 0x00, 0x88, 0x44, 0x23, 0x18, 0x04, 0x02, 0x01, 0x0F, 0x01,\n                0x02, 0x08, 0x08, 0x04, 0x02, 0x01,/*彩229*/},\n        {\n\n                0x12, 0x32, 0x52, 0x17, 0x32, 0xD2, 0x12, 0x4F, 0x2A, 0x0A, 0x02, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*菜230*/},\n        {\n\n                0x22, 0xB2, 0x5F, 0x2A, 0x5A, 0x42, 0x5A, 0x2A, 0x6F, 0x9A, 0x82, 0x01, 0x08, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x08, 0x00,/*蔡231*/},\n        {\n\n                0xA8, 0xA6, 0xDC, 0xD7, 0xAD, 0xD5, 0xA0, 0xD5, 0xC9, 0x97, 0xA0, 0x00, 0x00, 0x0F, 0x0A, 0x02,\n                0x03, 0x02, 0x06, 0x0B, 0x0C, 0x0A,/*餐232*/},\n        {\n\n                0x90, 0x54, 0xB6, 0x95, 0x5C, 0x54, 0x34, 0x94, 0x36, 0x54, 0x90, 0x00, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x09, 0x05, 0x04, 0x04, 0x02, 0x00,/*参233*/},\n        {\n\n                0x24, 0x24, 0xD5, 0x4D, 0x47, 0xF5, 0x45, 0x4D, 0xD5, 0x24, 0x24, 0x00, 0x04, 0x05, 0x05, 0x05,\n                0x07, 0x05, 0x05, 0x05, 0x0E, 0x00,/*蚕234*/},\n        {\n\n                0x82, 0x62, 0x9E, 0x12, 0xF2, 0x48, 0x48, 0xFF, 0x24, 0xA5, 0x26, 0x08, 0x04, 0x02, 0x01, 0x08,\n                0x08, 0x04, 0x03, 0x05, 0x08, 0x0E,/*残235*/},\n        {\n\n                0x30, 0xFF, 0x08, 0x34, 0x2C, 0xF7, 0xA4, 0xFE, 0x12, 0xF2, 0x11, 0x00, 0x0F, 0x00, 0x01, 0x01,\n                0x0F, 0x08, 0x07, 0x00, 0x0F, 0x00,/*惭236*/},\n        {\n\n                0x30, 0xFF, 0x08, 0x90, 0x54, 0xB6, 0x5D, 0xB4, 0x56, 0x94, 0x90, 0x00, 0x0F, 0x00, 0x08, 0x0A,\n                0x0A, 0x05, 0x04, 0x02, 0x00, 0x00,/*惨237*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xF8, 0x00, 0xFF, 0x00, 0x00, 0xF8, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x07, 0x04, 0x07, 0x04, 0x04, 0x0F,/*灿238*/},\n        {\n\n                0x42, 0x42, 0xE7, 0x52, 0x4A, 0x46, 0x4A, 0xD2, 0x27, 0x42, 0x42, 0x00, 0x00, 0x07, 0x08, 0x08,\n                0x0A, 0x0A, 0x09, 0x08, 0x0C, 0x00,/*苍239*/},\n        {\n\n                0x40, 0xFC, 0x56, 0x65, 0xFC, 0x10, 0xE8, 0x24, 0x23, 0xE4, 0x08, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x07, 0x08, 0x09, 0x09, 0x0C,/*舱240*/},\n        {\n\n                0x10, 0x10, 0xE8, 0x24, 0x22, 0x21, 0x22, 0xE4, 0x08, 0x10, 0x10, 0x00, 0x00, 0x07, 0x08, 0x08,\n                0x0A, 0x0A, 0x09, 0x08, 0x0E, 0x00,/*仓241*/},\n        {\n\n                0x10, 0x21, 0x02, 0x10, 0xE8, 0x24, 0x23, 0x24, 0xE8, 0x10, 0x10, 0x04, 0x02, 0x01, 0x00, 0x07,\n                0x08, 0x09, 0x09, 0x08, 0x08, 0x0E,/*沧242*/},\n        {\n\n                0xBA, 0xA2, 0xFA, 0x0F, 0xEA, 0xAA, 0xEA, 0xAF, 0xFA, 0x0E, 0xCA, 0x03, 0x08, 0x07, 0x00, 0x0F,\n                0x0A, 0x0E, 0x0B, 0x04, 0x07, 0x0C,/*藏243*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x70, 0x57, 0x75, 0x85, 0x75, 0x57, 0x70, 0x00, 0x08, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*操244*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x11, 0xF2, 0x08, 0xA6, 0xA4, 0xBF, 0xA4, 0x01, 0x00, 0x0F, 0x01, 0x08,\n                0x07, 0x08, 0x0B, 0x0A, 0x0A, 0x0B,/*糙245*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFA, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*槽246*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xAA, 0xFA, 0x02, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*曹247*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0xAA, 0xFA, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*草248*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xFA, 0x8A, 0x0A, 0xFA, 0x02, 0xF2, 0x02, 0xFA, 0x08, 0x07, 0x08, 0x04, 0x03,\n                0x04, 0x09, 0x00, 0x03, 0x08, 0x0F,/*厕249*/},\n        {\n\n                0x14, 0xD3, 0x52, 0x56, 0x52, 0xF8, 0x54, 0x53, 0x52, 0xD6, 0x12, 0x04, 0x05, 0x02, 0x02, 0x01,\n                0x0F, 0x01, 0x02, 0x03, 0x05, 0x04,/*策250*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xFE, 0xC2, 0x02, 0xFE, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x0F, 0x08, 0x04, 0x03,\n                0x04, 0x08, 0x00, 0x01, 0x08, 0x0F,/*侧251*/},\n        {\n\n                0x40, 0xFE, 0x42, 0x42, 0xFE, 0x40, 0xFE, 0x42, 0x42, 0xFE, 0x40, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x08, 0x07, 0x00, 0x08, 0x0F, 0x00,/*册252*/},\n        {\n\n                0x22, 0x44, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x09, 0x04, 0x03,\n                0x04, 0x09, 0x00, 0x01, 0x08, 0x0F,/*测253*/},\n        {\n\n                0x00, 0xFF, 0x85, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x87, 0x08, 0x07, 0x00, 0x04, 0x06,\n                0x05, 0x04, 0x04, 0x04, 0x06, 0x0C,/*层254*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0x3E, 0xAB, 0xA2, 0xBE, 0xA2, 0xAB, 0x3E, 0x07, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*蹭255*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xC8, 0x2A, 0x0A, 0xFE, 0x09, 0x49, 0xC8, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x04, 0x07, 0x04, 0x05, 0x0F,/*插256*/},\n        {\n\n                0x00, 0x02, 0x1E, 0x62, 0x82, 0x0A, 0x92, 0x42, 0x32, 0x0E, 0x00, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x04, 0x08, 0x08,/*叉257*/},\n        {\n\n                0x12, 0x92, 0xD2, 0x37, 0x1A, 0x12, 0x12, 0xD7, 0x12, 0x12, 0x12, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*茬258*/},\n        {\n\n                0x42, 0x42, 0xA2, 0xA7, 0x92, 0xCA, 0x92, 0xA7, 0xA2, 0x42, 0x42, 0x00, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x00,/*茶259*/},\n        {\n\n                0x12, 0x12, 0xEA, 0xA6, 0xA2, 0xBF, 0xA2, 0xA6, 0xEA, 0x12, 0x12, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0B, 0x08, 0x08,/*查260*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x14, 0xEC, 0xA4, 0xBF, 0xA4, 0xEC, 0x14, 0x00, 0x07, 0x02, 0x0B, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*碴261*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x42, 0xA7, 0x92, 0xCA, 0x92, 0xA7, 0x42, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*搽262*/},\n        {\n\n                0x26, 0xB2, 0x5E, 0x2A, 0x5A, 0x43, 0x5A, 0x2A, 0x6A, 0x9A, 0x86, 0x01, 0x08, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x08, 0x00,/*察263*/},\n        {\n\n                0x04, 0x44, 0x2A, 0x19, 0x08, 0x88, 0x48, 0x49, 0x3A, 0x04, 0x04, 0x00, 0x0F, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x00,/*岔264*/},\n        {\n\n                0x44, 0x54, 0x55, 0xD6, 0x74, 0x5C, 0x54, 0x56, 0x55, 0x54, 0x44, 0x04, 0x02, 0x09, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x08,/*差265*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x0C, 0x24, 0x25, 0xE6, 0x94, 0x94, 0x8C, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x01, 0x01, 0x07, 0x08, 0x08, 0x0E,/*诧266*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x88, 0x00, 0xFE, 0x12, 0x92, 0xF1, 0x11, 0x10, 0x01, 0x09, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x01, 0x02,/*拆267*/},\n        {\n\n                0xA0, 0xBE, 0xA0, 0x9F, 0x94, 0xD4, 0x80, 0x9F, 0xA8, 0xA4, 0xB2, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*柴268*/},\n        {\n\n                0xA4, 0xAA, 0x55, 0xA8, 0xC4, 0x00, 0x08, 0x88, 0x68, 0xFF, 0x08, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x02, 0x01, 0x00, 0x08, 0x0F, 0x00,/*豺269*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x04, 0xBB, 0x6A, 0x3A, 0xEE, 0x38, 0x80, 0x00, 0x08, 0x0F, 0x00, 0x01,\n                0x04, 0x05, 0x09, 0x0A, 0x01, 0x01,/*搀270*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x90, 0x54, 0xB6, 0x5D, 0xB4, 0x56, 0x94, 0x90, 0x08, 0x0F, 0x00, 0x08, 0x0A,\n                0x0A, 0x05, 0x04, 0x02, 0x00, 0x00,/*掺271*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFD, 0x96, 0xFC, 0x96, 0xFD, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x02, 0x02, 0x0F, 0x02, 0x02,/*蝉272*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0x04, 0xBB, 0x6A, 0x3A, 0xEE, 0x38, 0x80, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x04, 0x05, 0x09, 0x0A, 0x01, 0x01,/*馋273*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x04, 0xBB, 0x6A, 0x3A, 0x2E, 0xE8, 0x38, 0x80, 0x00, 0x0F, 0x04, 0x01, 0x04,\n                0x05, 0x09, 0x0A, 0x00, 0x01, 0x01,/*谗274*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xFE, 0x02, 0xFA, 0xAB, 0xFA, 0xAA, 0xFA, 0x04, 0x04, 0x02, 0x08, 0x07,\n                0x00, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*缠275*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xC4, 0x54, 0x65, 0x66, 0x54, 0x44, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*铲276*/},\n        {\n\n                0x00, 0xC4, 0x44, 0x54, 0x65, 0x46, 0x44, 0x64, 0x54, 0x44, 0x44, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*产277*/},\n        {\n\n                0xF9, 0x02, 0xF8, 0xAB, 0xAD, 0xF9, 0xAD, 0xAB, 0xF9, 0x01, 0xFF, 0x0F, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x0A, 0x0F,/*阐278*/},\n        {\n\n                0xFA, 0x8A, 0xBB, 0xAA, 0xFA, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x08, 0x0F, 0x0A, 0x0F, 0x08,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颤279*/},\n        {\n\n                0x00, 0xC0, 0x5F, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*昌280*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xC0, 0x5F, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x08, 0x08, 0x07, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*猖281*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0x22, 0xF2, 0x2A, 0xE6, 0x22, 0xE0, 0x02, 0x02, 0x01, 0x01, 0x02,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*场282*/},\n        {\n\n                0x4C, 0x45, 0x56, 0x54, 0xD4, 0x57, 0x54, 0x54, 0x56, 0x45, 0x4C, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x05, 0x06, 0x0C, 0x00,/*尝283*/},\n        {\n\n                0x0C, 0x04, 0x75, 0x56, 0x54, 0xD7, 0x54, 0x56, 0x75, 0x04, 0x0C, 0x00, 0x07, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x05, 0x07, 0x00,/*常284*/},\n        {\n\n                0x20, 0x20, 0x20, 0xFF, 0x28, 0x28, 0xE4, 0x24, 0x22, 0x22, 0x20, 0x00, 0x00, 0x00, 0x0F, 0x04,\n                0x02, 0x00, 0x01, 0x02, 0x04, 0x04,/*长285*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x9A, 0xAC, 0xA8, 0xAF, 0xA8, 0xAC, 0x9A, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*偿286*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x22, 0xF2, 0x2A, 0xE6, 0x22, 0xE0, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*肠287*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*厂288*/},\n        {\n\n                0xF2, 0x14, 0xD0, 0x5F, 0xD4, 0xF2, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x0F, 0x00, 0x03, 0x02, 0x0B,\n                0x0F, 0x08, 0x05, 0x02, 0x05, 0x08,/*敞289*/},\n        {\n\n                0xFC, 0x24, 0xFF, 0x24, 0xFC, 0x22, 0xF2, 0x2A, 0xE6, 0x22, 0xE0, 0x03, 0x01, 0x0F, 0x01, 0x03,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*畅290*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xC0, 0x5F, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*唱291*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xC0, 0x5F, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*倡292*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xFF, 0x24, 0x20, 0xD2, 0x4E, 0x42, 0x52, 0xDE, 0x08, 0x07, 0x04, 0x0F, 0x09,\n                0x09, 0x0B, 0x0A, 0x0A, 0x0A, 0x0B,/*超293*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x40, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*抄294*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x40, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*钞295*/},\n        {\n\n                0x00, 0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x02, 0x02, 0x02, 0x0F, 0x02,\n                0x02, 0x0A, 0x07, 0x00, 0x08, 0x0F,/*朝296*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFA, 0xAF, 0xFA, 0x00, 0xFE, 0x92, 0xFE, 0x03, 0x01, 0x03, 0x00, 0x02,\n                0x0F, 0x02, 0x08, 0x07, 0x08, 0x0F,/*嘲297*/},\n        {\n\n                0x22, 0x44, 0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x00, 0xFE, 0x92, 0xFE, 0x04, 0x02, 0x02, 0x02, 0x0F,\n                0x02, 0x02, 0x08, 0x07, 0x08, 0x0F,/*潮298*/},\n        {\n\n                0x00, 0xFA, 0xAD, 0xA8, 0xAA, 0xFD, 0xA8, 0xAA, 0xAD, 0xF8, 0x00, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*巢299*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x40, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*吵300*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x44, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*炒301*/},\n        {\n\n                0x04, 0x64, 0x54, 0x4C, 0x47, 0xF4, 0x44, 0x44, 0x44, 0x44, 0x04, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*车302*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xF8, 0x00, 0x00, 0xFF, 0x10, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x0F, 0x08, 0x08, 0x0F, 0x08, 0x08,/*扯303*/},\n        {\n\n                0x88, 0xFF, 0x4A, 0xEE, 0xAB, 0xEE, 0x12, 0xEC, 0x0B, 0xF8, 0x08, 0x08, 0x0F, 0x00, 0x0F, 0x02,\n                0x0F, 0x08, 0x04, 0x03, 0x04, 0x08,/*撤304*/},\n        {\n\n                0x04, 0x5B, 0x4A, 0x7F, 0x4A, 0xDA, 0x40, 0x5E, 0x40, 0x20, 0x3F, 0x04, 0x04, 0x05, 0x05, 0x0D,\n                0x0F, 0x05, 0x05, 0x05, 0x04, 0x04,/*掣305*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x10, 0xFF, 0x88, 0x02, 0xFE, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*彻306*/},\n        {\n\n                0x22, 0x44, 0x0A, 0xEE, 0xAB, 0xEE, 0x12, 0xEC, 0x0B, 0xF8, 0x08, 0x04, 0x02, 0x00, 0x0F, 0x02,\n                0x0F, 0x08, 0x04, 0x03, 0x04, 0x08,/*澈307*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0xC8, 0xFF, 0x48, 0x80, 0xFF, 0x31, 0xCF, 0x00, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x00, 0x00, 0x0F, 0x02, 0x01,/*郴308*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0x92, 0x92, 0x9E, 0x92, 0x92, 0x92, 0xF2, 0x00, 0x0F, 0x08, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x08,/*臣309*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x2A, 0xEA, 0x2A, 0x2A, 0xEA, 0x2A, 0x2A, 0xA2, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x04, 0x00, 0x01, 0x02, 0x05, 0x08,/*辰310*/},\n        {\n\n                0x10, 0x08, 0x06, 0x00, 0x00, 0xDF, 0x00, 0x00, 0x02, 0x04, 0x18, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*尘311*/},\n        {\n\n                0x00, 0xF0, 0x1F, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5F, 0x10, 0x08, 0x07, 0x01, 0x0F, 0x09,\n                0x01, 0x03, 0x05, 0x05, 0x0B, 0x09,/*晨312*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x1C, 0x04, 0xC4, 0x3F, 0xC4, 0x04, 0x1C, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0C,/*忱313*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x06, 0xF2, 0x12, 0x12, 0xF2, 0x02, 0x06, 0x04, 0x02, 0x01, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*沉314*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x00, 0x64, 0x5C, 0x47, 0xF4, 0x44, 0x44, 0x44, 0x0F, 0x02, 0x01, 0x04, 0x03,\n                0x00, 0x08, 0x0F, 0x00, 0x01, 0x06,/*陈315*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xFF, 0x24, 0x10, 0xAC, 0xA3, 0x94, 0x48, 0x10, 0x08, 0x07, 0x04, 0x0F, 0x09,\n                0x08, 0x0A, 0x0A, 0x0A, 0x09, 0x08,/*趁316*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0xA0, 0x08, 0x48, 0x88, 0x08, 0xFF, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x09, 0x08, 0x0F, 0x00,/*衬317*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x06, 0x43, 0x5E, 0xD7, 0x5E, 0x43, 0x06, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x05, 0x0D, 0x0F, 0x05, 0x05, 0x04,/*撑318*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x90, 0xC8, 0x07, 0xF4, 0x04, 0x54, 0x8C, 0x01, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*称319*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x00, 0xFC, 0x24, 0xE4, 0x04, 0xFF, 0x84, 0x65, 0x02, 0x03, 0x09, 0x06, 0x01,\n                0x02, 0x0B, 0x04, 0x03, 0x04, 0x0E,/*城320*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x25, 0xD9, 0x57, 0x50, 0x57, 0xDA, 0x25, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0B, 0x0D, 0x09, 0x0D, 0x0B, 0x08,/*橙321*/},\n        {\n\n                0x00, 0xFC, 0x24, 0x24, 0xE4, 0x04, 0xFF, 0x04, 0x85, 0x66, 0x04, 0x08, 0x07, 0x00, 0x02, 0x0B,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x0F,/*成322*/},\n        {\n\n                0x00, 0x2F, 0x29, 0x29, 0x29, 0xE9, 0x29, 0x29, 0x29, 0x2F, 0x00, 0x08, 0x08, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x08, 0x08,/*呈323*/},\n        {\n\n                0x28, 0x2A, 0xAA, 0xFA, 0x0A, 0xFE, 0x09, 0xF9, 0x49, 0x29, 0x88, 0x09, 0x09, 0x04, 0x02, 0x01,\n                0x0F, 0x01, 0x02, 0x05, 0x09, 0x09,/*乘324*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0x2F, 0x29, 0xE9, 0x29, 0x2F, 0x00, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*程325*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x82, 0xF2, 0x82, 0xFE, 0x92, 0x92, 0x82, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x0A, 0x0C, 0x08, 0x0C, 0x02, 0x0C,/*惩326*/},\n        {\n\n                0x10, 0x21, 0x02, 0x20, 0xD5, 0x49, 0x57, 0x50, 0x4F, 0xD2, 0x29, 0x04, 0x02, 0x01, 0x08, 0x0B,\n                0x0D, 0x09, 0x09, 0x0D, 0x0B, 0x08,/*澄327*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFC, 0x24, 0x24, 0xE4, 0x1F, 0xE4, 0x85, 0x66, 0x00, 0x07, 0x0A, 0x07, 0x00,\n                0x02, 0x0B, 0x04, 0x03, 0x04, 0x0E,/*诚328*/},\n        {\n\n                0x08, 0x08, 0xF9, 0x11, 0x51, 0xFD, 0x55, 0x13, 0xF9, 0x20, 0x18, 0x04, 0x03, 0x00, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x00, 0x03, 0x04,/*承329*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x20, 0xAF, 0xA9, 0xE9, 0xA9, 0xAF, 0x20, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x0A,/*逞330*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0xBE, 0xAA, 0xBF, 0xAA, 0xAA, 0xBE, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x00, 0x03, 0x02, 0x0A, 0x0A, 0x06,/*骋331*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x88, 0xB2, 0x82, 0xFE, 0x82, 0xA2, 0x98, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*秤332*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x10, 0x28, 0x27, 0x24, 0xA4, 0xA4, 0x64, 0x04, 0x03, 0x01, 0x03, 0x00, 0x06,\n                0x09, 0x09, 0x08, 0x08, 0x08, 0x0E,/*吃333*/},\n        {\n\n                0x08, 0x90, 0xFE, 0xA2, 0x9A, 0xF2, 0x93, 0x82, 0xF2, 0x12, 0xF2, 0x09, 0x04, 0x03, 0x08, 0x04,\n                0x03, 0x04, 0x08, 0x07, 0x02, 0x07,/*痴334*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0x54, 0x54, 0x5F, 0xF4, 0x54, 0x50, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x01, 0x0A, 0x08, 0x0F, 0x00, 0x00,/*持335*/},\n        {\n\n                0x40, 0x5F, 0x55, 0xD5, 0x5F, 0x40, 0x00, 0xFF, 0x10, 0x08, 0x84, 0x08, 0x07, 0x08, 0x0F, 0x09,\n                0x08, 0x08, 0x09, 0x0A, 0x0A, 0x0B,/*匙336*/},\n        {\n\n                0x22, 0x44, 0x40, 0xFC, 0x20, 0x10, 0xFF, 0x08, 0x04, 0xFC, 0x00, 0x04, 0x02, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x09, 0x09, 0x0C,/*池337*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0xFF, 0x11, 0x11, 0x31, 0xD1, 0x1F, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x09, 0x08, 0x08, 0x08, 0x08, 0x0B,/*迟338*/},\n        {\n\n                0xF2, 0x92, 0x92, 0x9E, 0x20, 0xFC, 0x10, 0xFF, 0x08, 0x84, 0xFC, 0x00, 0x08, 0x08, 0x07, 0x00,\n                0x07, 0x08, 0x09, 0x08, 0x08, 0x0E,/*弛339*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x20, 0xFC, 0x10, 0xFF, 0x88, 0xFC, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x00, 0x07, 0x08, 0x09, 0x08, 0x0E,/*驰340*/},\n        {\n\n                0x02, 0xFE, 0x52, 0x52, 0xFE, 0x02, 0xF8, 0x00, 0xFF, 0x10, 0x10, 0x02, 0x03, 0x02, 0x02, 0x0F,\n                0x09, 0x0F, 0x08, 0x0F, 0x08, 0x08,/*耻341*/},\n        {\n\n                0x20, 0xA0, 0x3E, 0x20, 0x20, 0xBF, 0x24, 0x24, 0x24, 0xA4, 0x20, 0x00, 0x0F, 0x08, 0x0C, 0x0A,\n                0x09, 0x0A, 0x0C, 0x08, 0x0F, 0x00,/*齿342*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x08, 0x44, 0xAB, 0x52, 0x6A, 0x46, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x04, 0x05, 0x02, 0x01, 0x00,/*侈343*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x22, 0x22, 0x22, 0xE2, 0x22, 0x22, 0x3E, 0x00, 0x08, 0x06, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x03, 0x04, 0x08, 0x08,/*尺344*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x24, 0xA4, 0x20, 0x02, 0x09, 0x04, 0x03, 0x00,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x03,/*赤345*/},\n        {\n\n                0x24, 0xE4, 0x3F, 0xE4, 0x89, 0x51, 0xFF, 0x88, 0x51, 0xFF, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x0A, 0x0B, 0x08, 0x0A, 0x0B, 0x08,/*翅346*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x12, 0x12, 0x92, 0x92, 0xF1, 0x11, 0x11, 0x10, 0x08, 0x06, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x01, 0x02, 0x00,/*斥347*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x10, 0x08, 0xFE, 0x82, 0x82, 0x82, 0xFE, 0x00, 0x08, 0x06, 0x01, 0x02, 0x08,\n                0x04, 0x02, 0x00, 0x02, 0x04, 0x08,/*炽348*/},\n        {\n\n                0x04, 0x44, 0x64, 0xD4, 0x4D, 0x46, 0x44, 0xD4, 0x64, 0xC4, 0x04, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*充349*/},\n        {\n\n                0x02, 0x04, 0x80, 0x00, 0xFC, 0x84, 0x84, 0xFF, 0x84, 0x84, 0xFC, 0x02, 0x01, 0x00, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*冲350*/},\n        {\n\n                0x00, 0xF8, 0x88, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x88, 0xF8, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x06, 0x0C,/*虫351*/},\n        {\n\n                0x30, 0x16, 0x54, 0x54, 0x54, 0x5F, 0x54, 0x54, 0x54, 0x16, 0x30, 0x01, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x01,/*崇352*/},\n        {\n\n                0x0C, 0x24, 0x24, 0xFC, 0x25, 0x26, 0xEC, 0x34, 0x24, 0xA4, 0x0C, 0x08, 0x04, 0x03, 0x08, 0x08,\n                0x04, 0x07, 0x0A, 0x09, 0x08, 0x0E,/*宠353*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFC, 0x44, 0x44, 0xFF, 0x44, 0x44, 0xFC, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*抽354*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x20, 0xFF, 0x10, 0xFE, 0x10, 0xFF, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x08, 0x07, 0x00, 0x07, 0x00, 0x0F,/*酬355*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x20, 0xEA, 0xBA, 0xAF, 0xEA, 0xA2, 0x07, 0x02, 0x03, 0x02, 0x0B,\n                0x06, 0x01, 0x02, 0x08, 0x0F, 0x00,/*畴356*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x20, 0x2A, 0xEA, 0xBF, 0xAA, 0xEA, 0xA2, 0x07, 0x04, 0x03, 0x0A, 0x04,\n                0x03, 0x00, 0x02, 0x08, 0x0F, 0x00,/*踌357*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0xFF, 0x21, 0xA9, 0xBD, 0xA9, 0x21, 0xFF, 0x01, 0x00, 0x0F, 0x08, 0x07,\n                0x00, 0x03, 0x02, 0x0B, 0x08, 0x0F,/*稠358*/},\n        {\n\n                0x48, 0x2A, 0xFE, 0x29, 0x48, 0x10, 0x8C, 0x60, 0x1F, 0x68, 0x84, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*愁359*/},\n        {\n\n                0x8C, 0xAB, 0xAA, 0xEE, 0xBA, 0xAC, 0xAB, 0xAA, 0xAE, 0xAA, 0x8A, 0x04, 0x02, 0x01, 0x02, 0x06,\n                0x0A, 0x02, 0x0A, 0x0F, 0x02, 0x02,/*筹360*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x08, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x07, 0x08, 0x0E,/*仇361*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xFF, 0x21, 0xA9, 0xBD, 0xA9, 0x21, 0xFF, 0x04, 0x04, 0x02, 0x08, 0x07,\n                0x00, 0x03, 0x02, 0x0B, 0x08, 0x0F,/*绸362*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x92, 0xFE, 0x51, 0x08, 0xFF, 0x10, 0x0C, 0x0F, 0x04, 0x0F, 0x01, 0x00,\n                0x0F, 0x08, 0x07, 0x00, 0x07, 0x08,/*瞅363*/},\n        {\n\n                0x00, 0x42, 0x42, 0xC2, 0x7E, 0x42, 0x42, 0x42, 0xFE, 0x00, 0x00, 0x08, 0x08, 0x08, 0x0F, 0x08,\n                0x08, 0x08, 0x08, 0x0F, 0x08, 0x08,/*丑364*/},\n        {\n\n                0x00, 0xFE, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xAA, 0xFE, 0x00, 0x0A, 0x0A, 0x0A, 0x06, 0x02,\n                0x03, 0x02, 0x06, 0x0B, 0x0A, 0x0A,/*臭365*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0xA0, 0x02, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*初366*/},\n        {\n\n                0x80, 0x1E, 0x10, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x10, 0x1E, 0x80, 0x07, 0x04, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x04, 0x0F,/*出367*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0xAA, 0xAA, 0xEA, 0x52, 0xFE, 0x12, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x05, 0x06, 0x05, 0x08, 0x0F, 0x00,/*橱368*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xEA, 0xAA, 0xEA, 0x02, 0x92, 0x12, 0xFE, 0x12, 0x08, 0x07, 0x08, 0x0A, 0x04,\n                0x06, 0x04, 0x00, 0x09, 0x0F, 0x00,/*厨369*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x22, 0xA7, 0xEA, 0xBE, 0xAA, 0xB7, 0x2A, 0x07, 0x04, 0x03, 0x02, 0x01,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*躇370*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x52, 0xFE, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0x0F, 0x04, 0x02, 0x03,\n                0x02, 0x09, 0x05, 0x03, 0x08, 0x0F,/*锄371*/},\n        {\n\n                0x94, 0x93, 0x9A, 0xF6, 0x10, 0xFC, 0xA7, 0xA4, 0xFD, 0xA6, 0xA4, 0x04, 0x04, 0x04, 0x0F, 0x00,\n                0x0F, 0x04, 0x04, 0x07, 0x04, 0x04,/*雏372*/},\n        {\n\n                0x22, 0x44, 0xFE, 0x12, 0xEE, 0x88, 0x94, 0xF3, 0x94, 0x88, 0x10, 0x04, 0x02, 0x0F, 0x01, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*滁373*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x00, 0x48, 0x54, 0x52, 0xF1, 0x52, 0x54, 0x48, 0x0F, 0x02, 0x01, 0x04, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x01, 0x06,/*除374*/},\n        {\n\n                0x52, 0x4A, 0x7F, 0x4A, 0x52, 0xC0, 0x52, 0x4A, 0x7F, 0x4A, 0xD2, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*楚375*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0x22, 0xE2, 0x00, 0xBC, 0x20, 0xFF, 0x20, 0xBC, 0x00, 0x07, 0x02, 0x02, 0x07,\n                0x00, 0x07, 0x04, 0x07, 0x04, 0x0F,/*础376*/},\n        {\n\n                0x10, 0xFC, 0x13, 0xF4, 0x00, 0x90, 0xD4, 0x7F, 0x54, 0xD8, 0x14, 0x00, 0x0F, 0x00, 0x07, 0x02,\n                0x00, 0x0F, 0x05, 0x05, 0x0F, 0x00,/*储377*/},\n        {\n\n                0x40, 0x42, 0x7A, 0xCA, 0x4A, 0x6F, 0x4A, 0xCA, 0x7A, 0x42, 0x40, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x08, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*矗378*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xA2, 0xAA, 0xAE, 0xBB, 0xAA, 0xA6, 0xB2, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0F,/*搐379*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x07, 0x01, 0x07, 0x09, 0x0F,\n                0x00, 0x08, 0x08, 0x0F, 0x04, 0x0E,/*触380*/},\n        {\n\n                0x40, 0x30, 0xCF, 0x04, 0xC4, 0x3C, 0x00, 0xFF, 0x08, 0x10, 0x60, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x04, 0x08, 0x0B, 0x08, 0x08, 0x08,/*处381*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xAE, 0xA8, 0xA8, 0xEF, 0xA8, 0xA8, 0xAE, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0F,/*揣382*/},\n        {\n\n                0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0xFF, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x07, 0x00, 0x00, 0x00, 0x0F,/*川383*/},\n        {\n\n                0x06, 0xD2, 0x9A, 0x96, 0x92, 0x93, 0x92, 0xF6, 0x9A, 0x92, 0x86, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x00,/*穿384*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xA0, 0xAC, 0x6B, 0xAA, 0x3A, 0xA6, 0x60, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x0A, 0x05, 0x0A, 0x0F, 0x02, 0x04,/*椽385*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x23, 0x24, 0xE4, 0xBC, 0xA7, 0xA4, 0xA4, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x02, 0x02, 0x04, 0x06, 0x09, 0x00,/*传386*/},\n        {\n\n                0x40, 0xFC, 0x56, 0x65, 0xFC, 0x10, 0xCE, 0x42, 0x42, 0xCE, 0x10, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*船387*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xAE, 0xA8, 0xA8, 0xEF, 0xA8, 0xA8, 0xAE, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0F,/*喘388*/},\n        {\n\n                0xC0, 0x5E, 0x52, 0x52, 0x52, 0xFF, 0x52, 0x52, 0x52, 0x5E, 0xC0, 0x07, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x07,/*串389*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x22, 0xD2, 0x4A, 0x47, 0x4A, 0xD2, 0x22, 0x22, 0x09, 0x04, 0x03, 0x00, 0x07,\n                0x08, 0x08, 0x0A, 0x0B, 0x08, 0x0E,/*疮390*/},\n        {\n\n                0x06, 0xE2, 0x2A, 0xA6, 0xF2, 0xAB, 0xA2, 0xA6, 0x2A, 0xE2, 0x06, 0x00, 0x0F, 0x09, 0x0D, 0x0A,\n                0x0A, 0x0D, 0x08, 0x08, 0x0F, 0x00,/*窗391*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x08, 0xFA, 0xAE, 0xFB, 0xAE, 0xFA, 0x01, 0x00, 0x0F, 0x01, 0x01,\n                0x08, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*幢392*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x24, 0x24, 0xA5, 0xFE, 0xA4, 0x24, 0x24, 0x04, 0x08, 0x07, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x01, 0x02, 0x04,/*床393*/},\n        {\n\n                0xF9, 0x02, 0x08, 0x69, 0x49, 0x49, 0x49, 0x79, 0xC1, 0x01, 0xFF, 0x0F, 0x00, 0x01, 0x01, 0x01,\n                0x01, 0x05, 0x04, 0x03, 0x08, 0x0F,/*闯394*/},\n        {\n\n                0x08, 0xF4, 0x12, 0x11, 0x12, 0xF4, 0x08, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x07, 0x08, 0x09, 0x09,\n                0x08, 0x0E, 0x00, 0x01, 0x08, 0x0F,/*创395*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x20, 0x18, 0x07, 0xE4, 0x04, 0x14, 0x0C, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*吹396*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x24, 0x18, 0x07, 0xE4, 0x04, 0x14, 0x0C, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*炊397*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x48, 0xFA, 0x4A, 0xFE, 0x49, 0xF9, 0x48, 0x08, 0x0F, 0x00, 0x00, 0x02,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x02,/*捶398*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x48, 0xFA, 0x4A, 0xFE, 0x49, 0xF9, 0x48, 0x00, 0x0F, 0x04, 0x00, 0x02,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x02,/*锤399*/},\n        {\n\n                0x40, 0x4A, 0xFA, 0x4A, 0x4A, 0xFE, 0x49, 0x49, 0xF9, 0x49, 0x40, 0x00, 0x02, 0x0B, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0B, 0x02, 0x00,/*垂400*/},\n        {\n\n                0x20, 0xA2, 0xEA, 0xBA, 0xAE, 0xAB, 0xAA, 0xAA, 0xEA, 0xA2, 0x20, 0x01, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x01,/*春401*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xA2, 0xEA, 0xBA, 0xAF, 0xAA, 0xEA, 0xA2, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*椿402*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0xBA, 0xAA, 0xAB, 0xAA, 0x3A, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x02, 0x0A, 0x0E, 0x03, 0x02,/*醇403*/},\n        {\n\n                0x00, 0xFF, 0x11, 0xF5, 0x95, 0x15, 0x35, 0x55, 0x55, 0xB5, 0x91, 0x04, 0x03, 0x00, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*唇404*/},\n        {\n\n                0x22, 0x44, 0x00, 0x02, 0xBA, 0xAA, 0xAA, 0xAB, 0xAA, 0xBA, 0x02, 0x04, 0x02, 0x01, 0x02, 0x02,\n                0x02, 0x0A, 0x0E, 0x03, 0x02, 0x02,/*淳405*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xF4, 0x84, 0x84, 0xFF, 0x84, 0x84, 0xF4, 0x04, 0x04, 0x02, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*纯406*/},\n        {\n\n                0xA8, 0xAA, 0xDA, 0xFA, 0xAE, 0xAB, 0xAA, 0xFA, 0xDA, 0xAA, 0xA8, 0x0B, 0x0A, 0x0F, 0x0A, 0x0B,\n                0x00, 0x0B, 0x0A, 0x0F, 0x0A, 0x0B,/*蠢407*/},\n        {\n\n                0x2B, 0xF5, 0xAF, 0xA0, 0xEB, 0xB5, 0xAF, 0x10, 0xFF, 0x88, 0x6A, 0x00, 0x0F, 0x0A, 0x0A, 0x0F,\n                0x0A, 0x0A, 0x04, 0x03, 0x05, 0x0E,/*戳408*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xF8, 0xA8, 0xAF, 0xAA, 0xAA, 0xFA, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*绰409*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0xC4, 0x05, 0xF6, 0x84, 0xF4, 0x44, 0x24, 0x09, 0x04, 0x03, 0x08, 0x0F,\n                0x08, 0x07, 0x04, 0x07, 0x08, 0x0E,/*疵410*/},\n        {\n\n                0x0A, 0x12, 0x22, 0x07, 0x42, 0x22, 0x1A, 0xD7, 0x12, 0x52, 0x32, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*茨411*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0xE8, 0x99, 0x4A, 0x08, 0xEC, 0x9B, 0x48, 0x07, 0x02, 0x07, 0x00, 0x06,\n                0x05, 0x0E, 0x00, 0x06, 0x05, 0x0E,/*磁412*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x20, 0xFF, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x24, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x02, 0x0F, 0x09, 0x0F, 0x09, 0x09,/*雌413*/},\n        {\n\n                0x92, 0x92, 0xFE, 0x91, 0x91, 0x40, 0x54, 0x65, 0xC6, 0x64, 0x54, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x01, 0x01, 0x0F, 0x01, 0x01,/*辞414*/},\n        {\n\n                0x04, 0xB4, 0xED, 0xA6, 0xD4, 0x04, 0xB4, 0xEE, 0xA5, 0xD4, 0x04, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*慈415*/},\n        {\n\n                0x50, 0x51, 0xCA, 0x40, 0x54, 0x53, 0x4A, 0x46, 0x4A, 0x52, 0x56, 0x00, 0x0C, 0x0B, 0x09, 0x0B,\n                0x05, 0x01, 0x07, 0x08, 0x08, 0x0E,/*瓷416*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x08, 0xEA, 0x2A, 0x2A, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x03,\n                0x01, 0x01, 0x09, 0x09, 0x08, 0x07,/*词417*/},\n        {\n\n                0x00, 0xF8, 0x00, 0xFF, 0x20, 0x20, 0x00, 0xFF, 0x20, 0x10, 0x0C, 0x08, 0x0F, 0x08, 0x07, 0x04,\n                0x04, 0x00, 0x07, 0x08, 0x08, 0x0E,/*此418*/},\n        {\n\n                0xF4, 0x14, 0x14, 0xFF, 0x14, 0x94, 0xF4, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x01, 0x0F, 0x01,\n                0x02, 0x04, 0x00, 0x01, 0x08, 0x0F,/*刺419*/},\n        {\n\n                0xFF, 0x01, 0xF9, 0x01, 0xFF, 0x80, 0x5F, 0xF5, 0x55, 0xD5, 0xDF, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x02, 0x09, 0x04, 0x0B, 0x08, 0x07,/*赐420*/},\n        {\n\n                0x02, 0x04, 0x80, 0x20, 0x18, 0x87, 0x74, 0x84, 0x04, 0x14, 0x0C, 0x02, 0x01, 0x08, 0x04, 0x02,\n                0x01, 0x00, 0x01, 0x02, 0x04, 0x08,/*次421*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x02, 0x3D, 0xA6, 0x24, 0x26, 0x3D, 0x00, 0x02, 0x03, 0x02, 0x0F, 0x05,\n                0x02, 0x0C, 0x09, 0x0C, 0x01, 0x06,/*聪422*/},\n        {\n\n                0x02, 0x52, 0x5A, 0xAF, 0xBA, 0x4A, 0x7A, 0x8F, 0x8A, 0x7A, 0x02, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*葱423*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x44, 0x26, 0x5D, 0x94, 0x54, 0x34, 0x04, 0xFC, 0x00, 0x0F, 0x04, 0x04, 0x06,\n                0x05, 0x04, 0x05, 0x04, 0x04, 0x0F,/*囱424*/},\n        {\n\n                0x20, 0x18, 0xA7, 0x64, 0x5C, 0x44, 0x84, 0x7C, 0x04, 0x04, 0xFC, 0x02, 0x01, 0x00, 0x08, 0x04,\n                0x02, 0x01, 0x09, 0x0A, 0x08, 0x07,/*匆425*/},\n        {\n\n                0x00, 0x00, 0xE0, 0x1F, 0xE0, 0x00, 0xC0, 0x3F, 0xC0, 0x00, 0x00, 0x08, 0x06, 0x01, 0x00, 0x09,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*从426*/},\n        {\n\n                0x00, 0x80, 0x60, 0x1F, 0x60, 0x80, 0x70, 0x0F, 0x70, 0x80, 0x00, 0x0A, 0x09, 0x08, 0x08, 0x0A,\n                0x09, 0x08, 0x08, 0x08, 0x09, 0x0A,/*丛427*/},\n        {\n\n                0x04, 0x88, 0x20, 0xA2, 0x6A, 0xBA, 0xAF, 0xAA, 0x6A, 0xA2, 0x20, 0x01, 0x00, 0x01, 0x0A, 0x0A,\n                0x06, 0x03, 0x02, 0x06, 0x0A, 0x01,/*凑428*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x24, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x08, 0x0F, 0x08, 0x08, 0x0F, 0x08,/*粗429*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x14, 0xDF, 0x54, 0x54, 0xDF, 0x14, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x05, 0x05, 0x0F, 0x00,/*醋430*/},\n        {\n\n                0x24, 0xEB, 0xB2, 0xA6, 0x22, 0x98, 0x74, 0xD3, 0x52, 0x56, 0x12, 0x08, 0x07, 0x08, 0x0F, 0x01,\n                0x09, 0x05, 0x03, 0x05, 0x09, 0x09,/*簇431*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xDF, 0x11, 0x11, 0xF1, 0x91, 0x91, 0x9F, 0x00, 0x0F, 0x08, 0x04, 0x03,\n                0x04, 0x08, 0x0F, 0x08, 0x08, 0x08,/*促432*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0x06, 0x7A, 0x56, 0xFB, 0x56, 0x7A, 0x06, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x07,/*蹿433*/},\n        {\n\n                0x84, 0xFB, 0x8A, 0x9E, 0xAA, 0xCC, 0x9B, 0xAA, 0xCE, 0xFA, 0x82, 0x04, 0x02, 0x09, 0x0C, 0x0A,\n                0x08, 0x08, 0x0C, 0x09, 0x02, 0x04,/*篡434*/},\n        {\n\n                0x06, 0x0A, 0x76, 0x52, 0x52, 0xFB, 0x52, 0x52, 0x76, 0x0A, 0x06, 0x00, 0x07, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x05, 0x07, 0x00,/*窜435*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x26, 0xF4, 0xAC, 0xA7, 0xEC, 0xB4, 0xA6, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*摧436*/},\n        {\n\n                0x40, 0x26, 0xF4, 0xAC, 0xA4, 0xA7, 0xEC, 0xB4, 0xA4, 0xA6, 0x20, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*崔437*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x43, 0x26, 0xF4, 0xAC, 0xA7, 0xEC, 0xB4, 0xA6, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*催438*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x08, 0xF4, 0x13, 0xD2, 0x5A, 0x56, 0xD0, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x07, 0x00, 0x07, 0x08, 0x09, 0x0D,/*脆439*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0x92, 0x72, 0x93, 0x1A, 0x92, 0x72, 0x92, 0x09, 0x04, 0x03, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*瘁440*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x24, 0x1C, 0x25, 0x86, 0x24, 0x1C, 0x24, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*粹441*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x24, 0x1C, 0x25, 0x86, 0x24, 0x1C, 0x24, 0x04, 0x02, 0x01, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*淬442*/},\n        {\n\n                0x01, 0xAB, 0x65, 0xA1, 0x2F, 0x30, 0x21, 0xAB, 0x65, 0xA1, 0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*翠443*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x00, 0x48, 0x88, 0x08, 0xFF, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x09, 0x08, 0x0F, 0x00,/*村444*/},\n        {\n\n                0x84, 0x44, 0xF4, 0x0C, 0x87, 0x94, 0x94, 0xD4, 0xB4, 0x94, 0x84, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x00,/*存445*/},\n        {\n\n                0x08, 0x08, 0x48, 0x88, 0x08, 0x08, 0x08, 0xFF, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x01, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*寸446*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x44, 0xD5, 0x76, 0x5C, 0x56, 0x55, 0x00, 0x0F, 0x04, 0x0F, 0x04,\n                0x0A, 0x09, 0x09, 0x0F, 0x09, 0x09,/*磋447*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x10, 0xF0, 0x5F, 0xF5, 0x15, 0xD5, 0x5F, 0xD0, 0x08, 0x0F, 0x00, 0x04, 0x07,\n                0x05, 0x0F, 0x0A, 0x05, 0x02, 0x0D,/*撮448*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x44, 0xD5, 0x76, 0x5C, 0x56, 0x55, 0x44, 0x08, 0x0F, 0x00, 0x04, 0x0A,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*搓449*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0xD4, 0x5F, 0x54, 0x54, 0x5F, 0xD4, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*措450*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x20, 0x1C, 0x20, 0xFF, 0x20, 0x1C, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*挫451*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x10, 0xD4, 0x5F, 0x54, 0x54, 0x5F, 0xD4, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*错452*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x42, 0x27, 0x52, 0x4A, 0x52, 0x27, 0x42, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*搭453*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x08, 0x08, 0xC8, 0x3F, 0x48, 0x88, 0x08, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x09, 0x08, 0x08, 0x08, 0x08, 0x0B,/*达454*/},\n        {\n\n                0x24, 0x23, 0x96, 0xB2, 0xAA, 0xA4, 0xAB, 0xB2, 0x96, 0x22, 0x22, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x0F, 0x00, 0x00,/*答455*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x8A, 0x5E, 0xAA, 0x9B, 0xAA, 0x5E, 0x8A, 0x8A, 0x09, 0x04, 0x03, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*瘩456*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x48, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*打457*/},\n        {\n\n                0x10, 0x10, 0x10, 0x10, 0xD0, 0x3F, 0xD0, 0x10, 0x10, 0x10, 0x10, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x03, 0x04, 0x08, 0x08,/*大458*/},\n        {\n\n                0x40, 0x4F, 0x49, 0x49, 0xC9, 0xF9, 0xC9, 0x49, 0x49, 0x4F, 0x40, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*呆459*/},\n        {\n\n                0x82, 0x42, 0x22, 0x5A, 0x96, 0x12, 0x12, 0x12, 0xD2, 0x32, 0x02, 0x08, 0x08, 0x08, 0x04, 0x05,\n                0x02, 0x02, 0x01, 0x00, 0x00, 0x00,/*歹460*/},\n        {\n\n                0x10, 0xFC, 0x23, 0xAA, 0x6A, 0x3A, 0xAF, 0x2A, 0x6A, 0xAA, 0x20, 0x00, 0x0F, 0x01, 0x08, 0x05,\n                0x0A, 0x0F, 0x02, 0x05, 0x08, 0x01,/*傣461*/},\n        {\n\n                0x08, 0xFA, 0xAA, 0xFF, 0xAA, 0xFA, 0x08, 0xFF, 0x08, 0xE9, 0x0A, 0x02, 0x0A, 0x07, 0x02, 0x07,\n                0x0A, 0x0A, 0x04, 0x03, 0x04, 0x0E,/*戴462*/},\n        {\n\n                0x32, 0x92, 0x97, 0x92, 0x92, 0xD7, 0x92, 0x92, 0x97, 0x92, 0x32, 0x00, 0x07, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x04, 0x07, 0x00,/*带463*/},\n        {\n\n                0x82, 0x62, 0x9E, 0x12, 0xF2, 0x00, 0xD0, 0x5C, 0x53, 0x50, 0xD8, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*殆464*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x10, 0x10, 0xFF, 0x10, 0x09, 0x0A, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x01, 0x02, 0x04, 0x0F,/*代465*/},\n        {\n\n                0x08, 0xC4, 0x7E, 0x41, 0x48, 0xC8, 0x4F, 0x48, 0x55, 0xE6, 0x34, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贷466*/},\n        {\n\n                0x88, 0x84, 0xBE, 0x81, 0x88, 0xC8, 0x8F, 0x88, 0x95, 0xA6, 0xB4, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*袋467*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x50, 0x54, 0x54, 0x5F, 0xF4, 0x54, 0x50, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x0A, 0x08, 0x0F, 0x00, 0x00,/*待468*/},\n        {\n\n                0x11, 0xF2, 0x08, 0xAA, 0x2A, 0xAA, 0xFF, 0xAA, 0x2A, 0xBE, 0x08, 0x08, 0x07, 0x08, 0x0A, 0x09,\n                0x0A, 0x0B, 0x08, 0x09, 0x0A, 0x08,/*逮469*/},\n        {\n\n                0x04, 0x76, 0x55, 0x54, 0x54, 0x54, 0x54, 0x54, 0x54, 0x76, 0x0C, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*怠470*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x02, 0x1C, 0xC4, 0x3F, 0xC4, 0x04, 0x1C, 0x02, 0x03, 0x02, 0x0F, 0x09,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0C,/*耽471*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFE, 0x22, 0x22, 0x22, 0xFE, 0x00, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*担472*/},\n        {\n\n                0x40, 0x40, 0xFE, 0x42, 0x42, 0x4A, 0x52, 0x42, 0x42, 0xFE, 0x40, 0x08, 0x06, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x0F, 0x00,/*丹473*/},\n        {\n\n                0x00, 0x7C, 0x55, 0x56, 0x54, 0xFC, 0x54, 0x56, 0x55, 0x7C, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*单474*/},\n        {\n\n                0x7C, 0x55, 0x56, 0xFC, 0x56, 0x55, 0x7C, 0x00, 0xFE, 0x32, 0xCE, 0x01, 0x01, 0x01, 0x0F, 0x01,\n                0x01, 0x01, 0x00, 0x0F, 0x02, 0x01,/*郸475*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x7C, 0x55, 0x56, 0xFC, 0x56, 0x55, 0x7C, 0x00, 0x08, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*掸476*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0xFE, 0x12, 0x12, 0x12, 0xFE, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x09, 0x09, 0x09, 0x09, 0x09,/*胆477*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0xFE, 0x00, 0x00, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*旦478*/},\n        {\n\n                0x04, 0x52, 0x35, 0x95, 0x75, 0x55, 0xB5, 0x15, 0xF5, 0x01, 0x00, 0x00, 0x09, 0x0B, 0x04, 0x03,\n                0x04, 0x0A, 0x00, 0x03, 0x04, 0x0E,/*氮479*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x08, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x08,/*但480*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x7C, 0x55, 0x56, 0xFC, 0x56, 0x55, 0x7C, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*惮481*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x28, 0xA6, 0x10, 0xCF, 0x10, 0x14, 0xA2, 0x04, 0x02, 0x01, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x05, 0x08,/*淡482*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x72, 0xCE, 0x00, 0xF2, 0x02, 0xFE, 0x11, 0x11, 0x00, 0x07, 0x0A, 0x04, 0x0B,\n                0x08, 0x09, 0x09, 0x09, 0x09, 0x09,/*诞483*/},\n        {\n\n                0xF2, 0x92, 0x9E, 0x00, 0x7C, 0x55, 0x56, 0xFC, 0x56, 0x55, 0x7C, 0x08, 0x08, 0x07, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*弹484*/},\n        {\n\n                0x21, 0x91, 0x8D, 0x91, 0xA1, 0xFF, 0xA9, 0xA9, 0xA9, 0xA9, 0x23, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*蛋485*/},\n        {\n\n                0x00, 0x12, 0x94, 0x90, 0x90, 0x9F, 0x90, 0x90, 0x94, 0xF2, 0x00, 0x00, 0x04, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*当486*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x12, 0x94, 0x90, 0x9F, 0x90, 0x94, 0xF2, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*挡487*/},\n        {\n\n                0x0C, 0x05, 0xF6, 0x94, 0x94, 0x97, 0x94, 0x94, 0xF6, 0x05, 0x0C, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*党488*/},\n        {\n\n                0x42, 0x8A, 0x12, 0x07, 0x4A, 0x6A, 0xEA, 0x5F, 0xCA, 0x42, 0xC2, 0x08, 0x04, 0x02, 0x00, 0x0A,\n                0x09, 0x04, 0x02, 0x09, 0x08, 0x07,/*荡489*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x12, 0x94, 0x90, 0x9F, 0x90, 0x94, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*档490*/},\n        {\n\n                0x00, 0x02, 0x02, 0xC2, 0x3E, 0x02, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x08, 0x07,/*刀491*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x7E, 0xC3, 0x4A, 0x52, 0x5E, 0xC0, 0x00, 0x08, 0x0F, 0x00, 0x03,\n                0x02, 0x03, 0x02, 0x0B, 0x08, 0x07,/*捣492*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0xCA, 0x52, 0x26, 0x09, 0x51, 0xCD, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x0F, 0x05, 0x04, 0x04, 0x05, 0x0F,/*蹈493*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x9A, 0xF6, 0x92, 0xBA, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x0F, 0x00, 0x04, 0x07,\n                0x02, 0x02, 0x00, 0x01, 0x08, 0x0F,/*倒494*/},\n        {\n\n                0x00, 0x7E, 0x42, 0x42, 0xCB, 0x52, 0x42, 0x52, 0x5E, 0x40, 0xC0, 0x07, 0x04, 0x04, 0x04, 0x07,\n                0x04, 0x04, 0x04, 0x07, 0x08, 0x0F,/*岛495*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0xA0, 0x2A, 0xEA, 0xBF, 0xAA, 0xEA, 0xA2, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x03, 0x00, 0x02, 0x08, 0x0F, 0x00,/*祷496*/},\n        {\n\n                0x00, 0x1F, 0x25, 0x25, 0x25, 0x25, 0x25, 0x25, 0xA5, 0x27, 0x30, 0x01, 0x01, 0x03, 0x05, 0x01,\n                0x01, 0x09, 0x09, 0x0F, 0x01, 0x01,/*导497*/},\n        {\n\n                0x92, 0x9A, 0x96, 0xF2, 0x92, 0x9A, 0xB2, 0x00, 0xFC, 0x00, 0xFF, 0x08, 0x08, 0x08, 0x07, 0x04,\n                0x04, 0x04, 0x00, 0x01, 0x08, 0x0F,/*到498*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x00, 0xCA, 0x52, 0x26, 0x09, 0x51, 0xCD, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x05, 0x04, 0x04, 0x05, 0x0F,/*稻499*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0xF8, 0xA8, 0xAF, 0xAA, 0xAA, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*悼500*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xFA, 0xAB, 0xAE, 0xAA, 0xAA, 0xAB, 0xFA, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B,/*道501*/},\n        {\n\n                0x42, 0x24, 0x00, 0x44, 0x23, 0x12, 0x0E, 0x12, 0x22, 0x4A, 0x46, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盗502*/},\n        {\n\n                0x24, 0xF2, 0x09, 0x80, 0xBA, 0xAA, 0xBA, 0xAF, 0xBA, 0xAA, 0xBA, 0x00, 0x0F, 0x00, 0x08, 0x06,\n                0x00, 0x06, 0x09, 0x0C, 0x02, 0x0C,/*德503*/},\n        {\n\n                0x24, 0xF2, 0x09, 0x00, 0x5F, 0x55, 0x55, 0x55, 0xD5, 0x5F, 0x00, 0x00, 0x0F, 0x00, 0x01, 0x03,\n                0x05, 0x01, 0x09, 0x0F, 0x01, 0x01,/*得504*/},\n        {\n\n                0xFC, 0x46, 0x45, 0x44, 0xFC, 0x10, 0x08, 0x27, 0xC4, 0x04, 0xFC, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*的505*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x25, 0xD9, 0x57, 0x50, 0x57, 0xDA, 0x25, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x0B, 0x0D, 0x09, 0x0D, 0x0B, 0x08,/*蹬506*/},\n        {\n\n                0x38, 0x00, 0xFF, 0x10, 0x08, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x08, 0x06, 0x01, 0x02, 0x0C,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*灯507*/},\n        {\n\n                0x44, 0x29, 0xD1, 0x4D, 0x53, 0x50, 0x53, 0x4C, 0xD2, 0x29, 0x44, 0x08, 0x08, 0x09, 0x0B, 0x0D,\n                0x09, 0x0D, 0x0B, 0x09, 0x08, 0x08,/*登508*/},\n        {\n\n                0x44, 0x53, 0x52, 0x56, 0x52, 0x7C, 0x53, 0xD2, 0x56, 0x52, 0x42, 0x01, 0x01, 0x03, 0x05, 0x01,\n                0x09, 0x09, 0x0F, 0x01, 0x01, 0x01,/*等509*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x20, 0xD5, 0x49, 0x57, 0x50, 0x4F, 0xD2, 0x29, 0x0F, 0x04, 0x0F, 0x08, 0x0B,\n                0x0D, 0x09, 0x09, 0x0D, 0x0B, 0x08,/*瞪510*/},\n        {\n\n                0x95, 0x89, 0xBD, 0xEB, 0xAA, 0xAA, 0xAA, 0xEB, 0xBE, 0x89, 0x94, 0x08, 0x08, 0x06, 0x02, 0x02,\n                0x02, 0x02, 0x06, 0x08, 0x08, 0x0C,/*凳511*/},\n        {\n\n                0x12, 0x62, 0x82, 0x62, 0x1E, 0x00, 0xFE, 0x02, 0x12, 0x2A, 0xC6, 0x04, 0x03, 0x00, 0x01, 0x06,\n                0x00, 0x0F, 0x00, 0x02, 0x02, 0x01,/*邓512*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x40, 0x5F, 0x55, 0xD5, 0x55, 0x5F, 0x40, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x07, 0x08, 0x0F, 0x09, 0x09, 0x08,/*堤513*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x07,\n                0x02, 0x05, 0x08, 0x03, 0x04, 0x0F,/*低514*/},\n        {\n\n                0x22, 0x44, 0xF2, 0x16, 0x5A, 0x52, 0xF3, 0x52, 0x5A, 0x16, 0xF2, 0x04, 0x02, 0x0F, 0x00, 0x07,\n                0x05, 0x05, 0x05, 0x07, 0x08, 0x0F,/*滴515*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xFC, 0x24, 0x24, 0xFF, 0x24, 0x24, 0xFC, 0x08, 0x04, 0x03, 0x04, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x09,/*迪516*/},\n        {\n\n                0x92, 0x92, 0xFE, 0x91, 0x91, 0x20, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x08, 0x05, 0x02, 0x05, 0x08,/*敌517*/},\n        {\n\n                0x04, 0xE3, 0x26, 0x2A, 0x22, 0xF8, 0x24, 0x23, 0x26, 0xEA, 0x02, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x0F, 0x00,/*笛518*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x20, 0x1C, 0x80, 0x7F, 0x80, 0x10, 0x0C, 0x01, 0x08, 0x08, 0x07, 0x08,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*狄519*/},\n        {\n\n                0x22, 0x44, 0x20, 0xA4, 0x96, 0x8B, 0xEA, 0x8A, 0x96, 0xA0, 0x20, 0x04, 0x02, 0x08, 0x04, 0x02,\n                0x08, 0x0F, 0x00, 0x02, 0x04, 0x08,/*涤520*/},\n        {\n\n                0x81, 0x4B, 0xE5, 0xB1, 0xAF, 0xA0, 0xF1, 0xAB, 0xA5, 0xA1, 0x2F, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*翟521*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xF2, 0x16, 0x5A, 0xF3, 0x5A, 0x16, 0xF2, 0x0D, 0x02, 0x05, 0x00, 0x0F,\n                0x00, 0x07, 0x05, 0x07, 0x08, 0x0F,/*嫡522*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x07,\n                0x02, 0x05, 0x08, 0x03, 0x04, 0x0F,/*抵523*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xF2, 0x92, 0x92, 0x93, 0xFA, 0x8A, 0x8A, 0x82, 0x08, 0x07, 0x00, 0x0F, 0x04,\n                0x02, 0x04, 0x09, 0x02, 0x04, 0x0E,/*底524*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x20, 0xFC, 0x10, 0xFF, 0x08, 0x84, 0xFC, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x07, 0x08, 0x09, 0x08, 0x08, 0x0E,/*地525*/},\n        {\n\n                0xC2, 0x52, 0x52, 0x77, 0x52, 0xDA, 0x52, 0x77, 0x52, 0x52, 0xC2, 0x00, 0x07, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x05, 0x07, 0x00,/*蒂526*/},\n        {\n\n                0x04, 0xD3, 0x52, 0x56, 0x52, 0xF4, 0x53, 0x52, 0x56, 0x72, 0x02, 0x08, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x01, 0x09, 0x09, 0x07,/*第527*/},\n        {\n\n                0x32, 0x92, 0x96, 0x9A, 0x92, 0xD3, 0x92, 0x9A, 0x96, 0x92, 0x32, 0x00, 0x07, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x04, 0x07, 0x00,/*帝528*/},\n        {\n\n                0x00, 0x74, 0x55, 0x56, 0xD4, 0xFC, 0x54, 0x56, 0x55, 0x5C, 0xC0, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x00, 0x02, 0x02, 0x01,/*弟529*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x74, 0x55, 0xD6, 0xFC, 0x56, 0x55, 0x5C, 0xC0, 0x08, 0x07, 0x08, 0x0A, 0x09,\n                0x08, 0x0F, 0x08, 0x0A, 0x0A, 0x09,/*递530*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xB2, 0x96, 0x9A, 0xD3, 0x9A, 0x96, 0xB2, 0x04, 0x04, 0x02, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*缔531*/},\n        {\n\n                0x00, 0xFA, 0xAA, 0xAF, 0xFA, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x0A, 0x07, 0x02, 0x02, 0x07,\n                0x0A, 0x09, 0x04, 0x03, 0x04, 0x09,/*颠532*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFC, 0x04, 0x05, 0xFE, 0x24, 0x24, 0x00, 0x08, 0x0F, 0x04, 0x03,\n                0x00, 0x0F, 0x09, 0x09, 0x09, 0x0F,/*掂533*/},\n        {\n\n                0x22, 0x44, 0x00, 0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xFA, 0x02, 0x04, 0x02, 0x01, 0x02, 0x0B,\n                0x06, 0x02, 0x02, 0x06, 0x0B, 0x02,/*滇534*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0xFC, 0x24, 0xFF, 0x24, 0xFF, 0x24, 0xFC, 0x07, 0x02, 0x07, 0x01, 0x09,\n                0x05, 0x01, 0x01, 0x01, 0x05, 0x09,/*碘535*/},\n        {\n\n                0x00, 0xF0, 0x10, 0x10, 0x10, 0x1F, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x08, 0x05, 0x01, 0x05, 0x09,\n                0x01, 0x05, 0x09, 0x01, 0x05, 0x08,/*点536*/},\n        {\n\n                0x00, 0xFC, 0x24, 0x24, 0xFF, 0x24, 0xFF, 0x24, 0x24, 0xFC, 0x00, 0x01, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x03, 0x05, 0x09, 0x01,/*典537*/},\n        {\n\n                0x22, 0xEA, 0xBF, 0xEA, 0x22, 0x0C, 0xA4, 0x25, 0xE6, 0x24, 0x2C, 0x00, 0x0F, 0x02, 0x0F, 0x08,\n                0x04, 0x03, 0x04, 0x0F, 0x09, 0x09,/*靛538*/},\n        {\n\n                0x24, 0xA4, 0xFF, 0x14, 0x80, 0x54, 0x3F, 0x44, 0x3C, 0x40, 0xF0, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*垫539*/},\n        {\n\n                0xFC, 0x24, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x24, 0xFC, 0x00, 0x00, 0x03, 0x01, 0x01, 0x01, 0x07,\n                0x09, 0x09, 0x09, 0x09, 0x08, 0x0E,/*电540*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x22, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*佃541*/},\n        {\n\n                0x08, 0xFC, 0x4B, 0x4A, 0xFA, 0x4A, 0x4A, 0xFA, 0x02, 0x02, 0xFE, 0x00, 0x07, 0x02, 0x02, 0x03,\n                0x02, 0x02, 0x0B, 0x08, 0x08, 0x07,/*甸542*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x04, 0x04, 0x05, 0xFE, 0x24, 0x24, 0x24, 0x24, 0x08, 0x07, 0x00, 0x0F, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x0F,/*店543*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0xFC, 0x04, 0x05, 0xFE, 0x24, 0x24, 0x00, 0x00, 0x0F, 0x04, 0x03,\n                0x00, 0x0F, 0x09, 0x09, 0x09, 0x0F,/*惦544*/},\n        {\n\n                0x02, 0xFA, 0xAB, 0x9E, 0xAA, 0xAA, 0xAA, 0x9E, 0xAB, 0xFA, 0x02, 0x0A, 0x0A, 0x0A, 0x06, 0x02,\n                0x03, 0x02, 0x06, 0x0A, 0x0A, 0x0A,/*奠545*/},\n        {\n\n                0x22, 0x44, 0x00, 0x2C, 0xA4, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x2C, 0x04, 0x02, 0x08, 0x04, 0x03,\n                0x04, 0x08, 0x0F, 0x09, 0x09, 0x08,/*淀546*/},\n        {\n\n                0x00, 0xFE, 0x4A, 0xEA, 0x4A, 0xEE, 0x50, 0xCE, 0x42, 0xDE, 0x10, 0x08, 0x07, 0x09, 0x05, 0x01,\n                0x05, 0x09, 0x05, 0x02, 0x05, 0x08,/*殿547*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFF, 0xA9, 0xBD, 0xA9, 0x21, 0xFF, 0x00, 0x07, 0x02, 0x0B, 0x06,\n                0x01, 0x03, 0x02, 0x0B, 0x08, 0x0F,/*碉548*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x82, 0x42, 0x22, 0x12, 0x02, 0xFE, 0x03, 0x01, 0x01, 0x03, 0x01,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*叼549*/},\n        {\n\n                0xFF, 0xA9, 0xBD, 0xA9, 0x01, 0xFF, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x07, 0x03, 0x02, 0x0B, 0x08,\n                0x0F, 0x00, 0x0F, 0x09, 0x0F, 0x09,/*雕550*/},\n        {\n\n                0x04, 0x08, 0x00, 0xFF, 0x21, 0xA9, 0xBD, 0xA9, 0xA9, 0x21, 0xFF, 0x02, 0x09, 0x04, 0x03, 0x00,\n                0x03, 0x02, 0x02, 0x0B, 0x08, 0x0F,/*凋551*/},\n        {\n\n                0x00, 0x02, 0x82, 0x82, 0x42, 0x42, 0x22, 0x12, 0x02, 0xFE, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00,\n                0x00, 0x08, 0x08, 0x08, 0x07, 0x00,/*刁552*/},\n        {\n\n                0x84, 0x84, 0xFF, 0x44, 0xF8, 0xA8, 0xA8, 0xAF, 0xAA, 0xAA, 0xFA, 0x00, 0x08, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*掉553*/},\n        {\n\n                0xC0, 0x4F, 0x49, 0x49, 0x49, 0xF9, 0x49, 0x49, 0x49, 0x4F, 0xC0, 0x07, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x04, 0x07,/*吊554*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x08, 0x27, 0xC4, 0x04, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*钓555*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x00, 0xFF, 0x21, 0xA9, 0xBD, 0xA9, 0x21, 0xFF, 0x00, 0x07, 0x02, 0x08, 0x07,\n                0x00, 0x03, 0x02, 0x0B, 0x08, 0x0F,/*调556*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x50, 0x4C, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*跌557*/},\n        {\n\n                0x10, 0x52, 0x29, 0xEA, 0x94, 0x54, 0x34, 0x8A, 0x49, 0x12, 0x10, 0x00, 0x09, 0x09, 0x0A, 0x0A,\n                0x0F, 0x09, 0x05, 0x05, 0x03, 0x00,/*爹558*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x04, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x00, 0x07, 0x02, 0x07, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*碟559*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x04, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x04, 0x04, 0x03, 0x02, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*蝶560*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x28, 0x26, 0xA4, 0x7F, 0xA4, 0x24, 0x20, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x09, 0x08, 0x08, 0x08, 0x09, 0x0A,/*迭561*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x04, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*谍562*/},\n        {\n\n                0x80, 0xD9, 0xAB, 0xAD, 0xDD, 0x85, 0xDD, 0xAB, 0xA9, 0xD8, 0x80, 0x09, 0x08, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x08, 0x09,/*叠563*/},\n        {\n\n                0x02, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*丁564*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x00, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*盯565*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*叮566*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*钉567*/},\n        {\n\n                0x02, 0x02, 0xFE, 0x02, 0xF9, 0x09, 0x0D, 0xEB, 0x09, 0x09, 0xF9, 0x00, 0x04, 0x07, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*顶568*/},\n        {\n\n                0x78, 0x40, 0x7F, 0x55, 0xD5, 0x55, 0xD5, 0x55, 0x7F, 0x40, 0x78, 0x09, 0x07, 0x01, 0x01, 0x0F,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x0F,/*鼎569*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xAC, 0x24, 0xE5, 0x26, 0x24, 0x2C, 0x00, 0x0F, 0x04, 0x0A, 0x04,\n                0x03, 0x04, 0x0F, 0x09, 0x09, 0x08,/*锭570*/},\n        {\n\n                0x2C, 0x24, 0xA4, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x24, 0x24, 0x2C, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*定571*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*订572*/},\n        {\n\n                0x80, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x91, 0x91, 0x80, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x04, 0x06, 0x0C, 0x00,/*丢573*/},\n        {\n\n                0x04, 0x64, 0x54, 0x4C, 0x47, 0xF4, 0x44, 0x44, 0x44, 0x44, 0x04, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x04,/*东574*/},\n        {\n\n                0x90, 0x88, 0x84, 0x4B, 0x52, 0x22, 0x52, 0x4A, 0x86, 0x80, 0x80, 0x00, 0x00, 0x00, 0x04, 0x05,\n                0x05, 0x0A, 0x0A, 0x08, 0x00, 0x00,/*冬575*/},\n        {\n\n                0x22, 0x2A, 0xEA, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xEA, 0x2A, 0x22, 0x08, 0x0A, 0x0B, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0B, 0x0A, 0x08,/*董576*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x12, 0xEA, 0xAF, 0xFA, 0xAF, 0xEA, 0x0A, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x0A,/*懂577*/},\n        {\n\n                0x10, 0xD2, 0x32, 0x92, 0x10, 0x00, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x03, 0x02, 0x02, 0x02, 0x03,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*动578*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x64, 0x5C, 0xF7, 0x44, 0x44, 0x44, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x03, 0x08, 0x0F, 0x00, 0x01, 0x06,/*栋579*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xFE, 0x02, 0xEA, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*侗580*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x02, 0xEA, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*恫581*/},\n        {\n\n                0x04, 0x08, 0x00, 0x64, 0x5C, 0x47, 0xF4, 0x44, 0x44, 0x44, 0x40, 0x02, 0x01, 0x04, 0x02, 0x01,\n                0x08, 0x0F, 0x00, 0x01, 0x02, 0x04,/*冻582*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x02, 0xEA, 0x2A, 0x2A, 0xEA, 0x02, 0xFE, 0x04, 0x02, 0x00, 0x0F, 0x00,\n                0x01, 0x01, 0x01, 0x01, 0x08, 0x0F,/*洞583*/},\n        {\n\n                0x7C, 0x42, 0x00, 0x7C, 0x56, 0x55, 0x54, 0x7C, 0x00, 0x42, 0x7E, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*兜584*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x08, 0x00, 0x12, 0x24, 0x00, 0xFF, 0x80, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x01, 0x01, 0x0F, 0x00,/*抖585*/},\n        {\n\n                0x00, 0x10, 0x20, 0x42, 0x04, 0x08, 0x00, 0xFF, 0x80, 0x80, 0x80, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x0F, 0x00, 0x00, 0x00,/*斗586*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0xA4, 0x24, 0xFF, 0x24, 0x24, 0x20, 0x0F, 0x02, 0x02, 0x09, 0x04,\n                0x03, 0x04, 0x0F, 0x09, 0x09, 0x08,/*陡587*/},\n        {\n\n                0x02, 0x7A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x7A, 0x02, 0x08, 0x09, 0x0A, 0x0C, 0x08,\n                0x08, 0x08, 0x0C, 0x0A, 0x09, 0x08,/*豆588*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x02, 0xBA, 0x2A, 0x2A, 0x2A, 0xBA, 0x02, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0A,/*逗589*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x0A, 0xEA, 0xAA, 0xAB, 0xAA, 0xAA, 0xEA, 0x0A, 0x09, 0x04, 0x03, 0x08, 0x0A,\n                0x0C, 0x08, 0x08, 0x0C, 0x0A, 0x08,/*痘590*/},\n        {\n\n                0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD6, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x0F, 0x00, 0x0F, 0x02, 0x02, 0x01,/*都591*/},\n        {\n\n                0x28, 0x18, 0xE8, 0xBF, 0xAA, 0xBA, 0xA8, 0xB7, 0xE9, 0x17, 0x20, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*督592*/},\n        {\n\n                0xA2, 0xAA, 0xEA, 0xAA, 0xEA, 0xBF, 0xAA, 0xAA, 0xEA, 0xAA, 0xA2, 0x00, 0x03, 0x02, 0x02, 0x02,\n                0x0B, 0x0A, 0x0A, 0x07, 0x02, 0x00,/*毒593*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x00, 0x4A, 0xAA, 0x4F, 0xEA, 0x0A, 0x18, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x09, 0x05, 0x03, 0x01, 0x05, 0x09,/*犊594*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xF8, 0x88, 0x88, 0xFF, 0x88, 0x88, 0xF8, 0x08, 0x08, 0x07, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x04, 0x04, 0x0E,/*独595*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x48, 0x8A, 0x2A, 0x4F, 0xEA, 0x0A, 0x0A, 0x18, 0x00, 0x07, 0x02, 0x09, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*读596*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD4, 0x12, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*堵597*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD4, 0x12, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*睹598*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD4, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x0F, 0x05, 0x05, 0x05, 0x0F,/*赌599*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*杜600*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x8A, 0xBE, 0xAB, 0xAA, 0xBE, 0x0A, 0x00, 0x0F, 0x04, 0x08, 0x07,\n                0x08, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*镀601*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,/*肚602*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0x8A, 0xBE, 0xAA, 0xAB, 0xAA, 0xBE, 0x8A, 0x0A, 0x08, 0x07, 0x00, 0x08, 0x09,\n                0x0A, 0x04, 0x04, 0x0A, 0x09, 0x08,/*度603*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x8A, 0xBE, 0xAA, 0xAB, 0xAA, 0xBE, 0x0A, 0x04, 0x02, 0x08, 0x07, 0x08,\n                0x0B, 0x04, 0x04, 0x0A, 0x09, 0x08,/*渡604*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFC, 0x44, 0x45, 0x46, 0x44, 0xFC, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*妒605*/},\n        {\n\n                0xE9, 0x0A, 0xE8, 0x00, 0xAE, 0xA8, 0xA8, 0xEF, 0xA8, 0xA8, 0xAE, 0x04, 0x05, 0x02, 0x00, 0x0F,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0F,/*端606*/},\n        {\n\n                0x48, 0x47, 0xFC, 0x44, 0x02, 0x7A, 0x4A, 0x4A, 0x4A, 0x7A, 0x02, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0A, 0x09, 0x08,/*短607*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x25, 0x08, 0xE7, 0x21, 0xEF, 0x08, 0x00, 0x0F, 0x04, 0x02, 0x0F,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*锻608*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xA9, 0x00, 0x28, 0xE7, 0x21, 0x21, 0xEF, 0x08, 0x02, 0x0F, 0x01, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*段609*/},\n        {\n\n                0xFC, 0x92, 0x54, 0xFF, 0x54, 0x92, 0x00, 0xFE, 0x12, 0xF2, 0x11, 0x07, 0x04, 0x04, 0x07, 0x04,\n                0x04, 0x08, 0x07, 0x00, 0x0F, 0x00,/*断610*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xFE, 0x25, 0x08, 0xE7, 0x21, 0xEF, 0x08, 0x04, 0x04, 0x02, 0x02, 0x0F,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*缎611*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x28, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*堆612*/},\n        {\n\n                0x00, 0x7C, 0x45, 0xC6, 0x44, 0x44, 0x44, 0xC6, 0x45, 0x7C, 0x00, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*兑613*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0x00, 0xC0, 0x3F, 0xC0, 0x00, 0x00, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*队614*/},\n        {\n\n                0x24, 0xC4, 0x04, 0xC4, 0x3C, 0x00, 0x48, 0x88, 0x08, 0xFF, 0x08, 0x08, 0x06, 0x01, 0x02, 0x0C,\n                0x00, 0x00, 0x09, 0x08, 0x0F, 0x00,/*对615*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xBA, 0xAB, 0xBA, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x02, 0x03, 0x01, 0x0A, 0x0E,\n                0x03, 0x0A, 0x05, 0x02, 0x05, 0x08,/*墩616*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xF4, 0x84, 0x84, 0xFF, 0x84, 0x84, 0xF4, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*吨617*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0xFA, 0xAB, 0xDE, 0xCA, 0xBE, 0xAB, 0xFA, 0x07, 0x04, 0x03, 0x02, 0x02,\n                0x06, 0x0A, 0x02, 0x0A, 0x0F, 0x02,/*蹲618*/},\n        {\n\n                0x02, 0xBA, 0xAA, 0xAB, 0xAA, 0x3A, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x02, 0x02, 0x0A, 0x0E, 0x03,\n                0x02, 0x08, 0x05, 0x02, 0x05, 0x08,/*敦619*/},\n        {\n\n                0xF4, 0x84, 0xFF, 0x84, 0xF4, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*顿620*/},\n        {\n\n                0x00, 0xFF, 0x05, 0x75, 0x45, 0xFF, 0x45, 0x75, 0x05, 0x01, 0xFF, 0x00, 0x0F, 0x08, 0x08, 0x08,\n                0x09, 0x0A, 0x0A, 0x0B, 0x08, 0x0F,/*囤621*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xF4, 0x84, 0x84, 0xFF, 0x84, 0x84, 0xF4, 0x00, 0x0F, 0x04, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*钝622*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xEA, 0xAA, 0xAA, 0xBE, 0xA9, 0xA9, 0xE9, 0x08, 0x08, 0x07, 0x00, 0x0F, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*盾623*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFE, 0x05, 0xF5, 0x55, 0x5F, 0x55, 0xF5, 0x04, 0x08, 0x07, 0x0A, 0x09, 0x08,\n                0x0F, 0x0D, 0x0D, 0x0D, 0x0F, 0x08,/*遁624*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xAA, 0x92, 0xAE, 0x00, 0xAA, 0x92, 0xAE, 0x08, 0x0F, 0x00, 0x08, 0x0A,\n                0x04, 0x0B, 0x00, 0x0B, 0x04, 0x0B,/*掇625*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x08, 0x44, 0xAB, 0x52, 0x6A, 0x46, 0xC0, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x09, 0x04, 0x05, 0x02, 0x01, 0x00,/*哆626*/},\n        {\n\n                0x90, 0x90, 0x48, 0x54, 0x23, 0x92, 0x4A, 0x66, 0x52, 0xC0, 0x40, 0x08, 0x08, 0x08, 0x09, 0x05,\n                0x04, 0x03, 0x02, 0x01, 0x00, 0x00,/*多627*/},\n        {\n\n                0xA4, 0xA4, 0x94, 0x94, 0x8C, 0x87, 0x8C, 0xF4, 0x94, 0xA4, 0xA4, 0x00, 0x00, 0x01, 0x02, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*夺628*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x50, 0x4F, 0x41, 0xF1, 0x41, 0x4F, 0x50, 0x02, 0x02, 0x01, 0x01, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*垛629*/},\n        {\n\n                0x80, 0xFE, 0xAB, 0xAA, 0xFE, 0x50, 0x4E, 0xE2, 0x4E, 0x50, 0x50, 0x04, 0x02, 0x01, 0x08, 0x0F,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*躲630*/},\n        {\n\n                0x50, 0x48, 0x47, 0x41, 0xC1, 0xF1, 0xC1, 0x41, 0x47, 0x48, 0x48, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*朵631*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x10, 0x4F, 0x41, 0xF1, 0x41, 0x4F, 0x50, 0x07, 0x04, 0x03, 0x02, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*跺632*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0x00, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x2C, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*舵633*/},\n        {\n\n                0x50, 0x4F, 0x41, 0xF1, 0x41, 0x4F, 0x50, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x01, 0x0F, 0x01,\n                0x02, 0x04, 0x00, 0x01, 0x08, 0x0F,/*剁634*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x2A, 0xE6, 0xAB, 0xBA, 0xAA, 0xEA, 0x22, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*惰635*/},\n        {\n\n                0x00, 0xFF, 0x49, 0x37, 0x10, 0x0A, 0xFE, 0x2B, 0xAA, 0xFA, 0x02, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*堕636*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x92, 0xFE, 0x51, 0xFF, 0x92, 0x54, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x0F, 0x04, 0x03, 0x04, 0x0E,/*蛾637*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x92, 0xFE, 0x51, 0xFF, 0x92, 0x54, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x0F, 0x04, 0x03, 0x04, 0x0E,/*峨638*/},\n        {\n\n                0x92, 0xFE, 0x51, 0xFF, 0x92, 0x54, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x08, 0x0F, 0x04, 0x03, 0x04,\n                0x0E, 0x00, 0x02, 0x0A, 0x0A, 0x07,/*鹅639*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x93, 0x92, 0xFE, 0x51, 0x10, 0xFF, 0x92, 0x54, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0F, 0x04, 0x02, 0x03, 0x04, 0x0E,/*俄640*/},\n        {\n\n                0x96, 0x5A, 0x2E, 0x2B, 0x5A, 0x86, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x00, 0x0F, 0x05, 0x05, 0x0F,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*额641*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x10, 0xFC, 0x83, 0x40, 0xFF, 0x10, 0x08, 0x04, 0x00, 0x07, 0x02, 0x00, 0x0F,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*讹642*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x90, 0x92, 0xFE, 0x51, 0xFF, 0x92, 0x54, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x08, 0x0F, 0x02, 0x03, 0x04, 0x0E,/*娥643*/},\n        {\n\n                0x40, 0x4A, 0x52, 0x42, 0x7E, 0x42, 0x7E, 0x42, 0x52, 0x4A, 0x40, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*恶644*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0xF2, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x08, 0x07, 0x00, 0x00, 0x07,\n                0x08, 0x08, 0x09, 0x09, 0x08, 0x0E,/*厄645*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xFE, 0x02, 0xFA, 0x0A, 0x8A, 0xFA, 0x02, 0x00, 0x08, 0x0F, 0x08, 0x07,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*扼646*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x80, 0x5F, 0x75, 0x55, 0xD5, 0x55, 0x5F, 0xC0, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x0A, 0x0B, 0x0A, 0x0B, 0x0C, 0x0B,/*遏647*/},\n        {\n\n                0x47, 0xD5, 0x57, 0x50, 0x57, 0x55, 0x47, 0x00, 0xFF, 0x31, 0xCF, 0x00, 0x01, 0x01, 0x09, 0x09,\n                0x07, 0x00, 0x00, 0x0F, 0x02, 0x01,/*鄂648*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x92, 0xFE, 0x51, 0x10, 0xFF, 0x92, 0x54, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x0F, 0x04, 0x02, 0x03, 0x04, 0x0E,/*饿649*/},\n        {\n\n                0x00, 0x7F, 0x41, 0x65, 0x55, 0x4F, 0x55, 0x65, 0x41, 0x7F, 0x00, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*恩650*/},\n        {\n\n                0x02, 0xF2, 0x12, 0x12, 0xFA, 0x16, 0xF2, 0x12, 0x12, 0xF2, 0x02, 0x00, 0x0F, 0x00, 0x00, 0x07,\n                0x00, 0x07, 0x00, 0x08, 0x0F, 0x00,/*而651*/},\n        {\n\n                0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*儿652*/},\n        {\n\n                0x02, 0x02, 0xFE, 0x52, 0x52, 0x52, 0x52, 0x52, 0xFE, 0x02, 0x02, 0x02, 0x02, 0x03, 0x02, 0x02,\n                0x02, 0x01, 0x01, 0x0F, 0x01, 0x01,/*耳653*/},\n        {\n\n                0x10, 0x08, 0xC7, 0x04, 0x04, 0xF4, 0x04, 0x04, 0x44, 0x94, 0x0C, 0x02, 0x01, 0x00, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x03,/*尔654*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x02, 0xFE, 0x52, 0x52, 0x52, 0xFE, 0x02, 0x00, 0x07, 0x02, 0x01, 0x02,\n                0x03, 0x02, 0x02, 0x02, 0x0F, 0x01,/*饵655*/},\n        {\n\n                0x22, 0x44, 0x00, 0x02, 0xFE, 0x52, 0x52, 0x52, 0xFE, 0x02, 0x00, 0x04, 0x02, 0x01, 0x02, 0x03,\n                0x02, 0x02, 0x02, 0x0F, 0x01, 0x01,/*洱656*/},\n        {\n\n                0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x04,/*二657*/},\n        {\n\n                0x02, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0x02, 0xFF, 0x02, 0x03, 0x02, 0x00, 0x0B, 0x04, 0x02, 0x04,\n                0x0B, 0x00, 0x00, 0x03, 0x04, 0x0E,/*贰658*/},\n        {\n\n                0x0E, 0x08, 0x88, 0x78, 0xCF, 0x48, 0x48, 0x49, 0xCA, 0x08, 0x08, 0x04, 0x02, 0x09, 0x08, 0x04,\n                0x05, 0x02, 0x05, 0x04, 0x08, 0x08,/*发659*/},\n        {\n\n                0x80, 0x8F, 0x99, 0x29, 0x0F, 0x09, 0x09, 0xCF, 0x09, 0x09, 0xEF, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x02, 0x00, 0x03, 0x08, 0x08, 0x0F,/*罚660*/},\n        {\n\n                0x84, 0x43, 0xE2, 0x56, 0x42, 0x44, 0xF3, 0x22, 0x26, 0xB2, 0x22, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x0E,/*筏661*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x10, 0x10, 0xFF, 0x08, 0x89, 0x6A, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x0F,/*伐662*/},\n        {\n\n                0x22, 0x22, 0x22, 0x22, 0x2A, 0x32, 0xA1, 0xA1, 0x61, 0x21, 0x01, 0x08, 0x04, 0x04, 0x0A, 0x09,\n                0x09, 0x08, 0x08, 0x08, 0x08, 0x08,/*乏663*/},\n        {\n\n                0xF9, 0x12, 0xF8, 0x25, 0x21, 0xFD, 0x11, 0xD5, 0x11, 0x01, 0xFF, 0x0F, 0x00, 0x07, 0x00, 0x04,\n                0x02, 0x01, 0x02, 0x07, 0x08, 0x0F,/*阀664*/},\n        {\n\n                0x10, 0x21, 0x42, 0x48, 0x48, 0xC8, 0x7F, 0x48, 0x48, 0x48, 0x40, 0x04, 0x02, 0x01, 0x04, 0x06,\n                0x05, 0x04, 0x04, 0x05, 0x06, 0x0C,/*法665*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x40, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x04, 0x04, 0x03, 0x02, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*珐666*/},\n        {\n\n                0x4A, 0x92, 0xA7, 0xEA, 0xBA, 0xAA, 0xFA, 0xAA, 0xB7, 0xE2, 0xA2, 0x04, 0x02, 0x00, 0x0F, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0F, 0x00,/*藩667*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xFE, 0x22, 0x42, 0xFE, 0x00, 0x01, 0x00, 0x0F, 0x01, 0x09,\n                0x04, 0x03, 0x00, 0x00, 0x07, 0x0C,/*帆668*/},\n        {\n\n                0x90, 0x52, 0xB6, 0x9A, 0x92, 0xBE, 0x91, 0x99, 0xB5, 0x51, 0x90, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*番669*/},\n        {\n\n                0xD6, 0xB2, 0xFE, 0x91, 0xB5, 0x10, 0xA2, 0xFE, 0x10, 0xA2, 0xFE, 0x0F, 0x0A, 0x0F, 0x0A, 0x0F,\n                0x01, 0x08, 0x0F, 0x01, 0x08, 0x0F,/*翻670*/},\n        {\n\n                0x24, 0x14, 0x7F, 0x14, 0x2D, 0x92, 0x2D, 0x14, 0x7F, 0x14, 0x24, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*樊671*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0x22, 0x42, 0xFE, 0x00, 0x00, 0x00, 0x07, 0x02, 0x0B, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*矾672*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFE, 0x22, 0x42, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x04, 0x0A, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*钒673*/},\n        {\n\n                0x04, 0x3F, 0xAA, 0xFE, 0xAA, 0xBE, 0x84, 0x6B, 0x12, 0x2E, 0x42, 0x00, 0x0A, 0x06, 0x02, 0x0B,\n                0x0E, 0x02, 0x02, 0x07, 0x0A, 0x00,/*繁674*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x02, 0x12, 0x62, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*凡675*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x02, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x05, 0x02, 0x01, 0x02, 0x05, 0x08,/*烦676*/},\n        {\n\n                0x00, 0xFE, 0x12, 0x72, 0x92, 0x12, 0x11, 0x11, 0x91, 0x71, 0x00, 0x08, 0x07, 0x08, 0x08, 0x04,\n                0x05, 0x02, 0x05, 0x04, 0x08, 0x08,/*反677*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xFE, 0x0A, 0x2A, 0x4A, 0x89, 0x49, 0x39, 0x08, 0x04, 0x03, 0x06, 0x09,\n                0x08, 0x0A, 0x09, 0x08, 0x09, 0x0A,/*返678*/},\n        {\n\n                0x42, 0x8A, 0x12, 0x07, 0xF2, 0x12, 0x12, 0x17, 0x12, 0xF2, 0x02, 0x08, 0x04, 0x02, 0x00, 0x07,\n                0x08, 0x08, 0x09, 0x09, 0x08, 0x0E,/*范679*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0xFE, 0x12, 0xF2, 0x11, 0xF1, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x04, 0x03, 0x08, 0x05, 0x02, 0x0D,/*贩680*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x00, 0xFE, 0x02, 0x02, 0x82, 0xFE, 0x00, 0x01, 0x08, 0x08, 0x07, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*犯681*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x00, 0xFE, 0x12, 0xF2, 0x12, 0x91, 0x71, 0x00, 0x07, 0x02, 0x09, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*饭682*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x22, 0x22, 0x2A, 0xB1, 0x61, 0x21, 0x00, 0x04, 0x02, 0x01, 0x08, 0x04,\n                0x02, 0x05, 0x08, 0x08, 0x08, 0x08,/*泛683*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x04, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*坊684*/},\n        {\n\n                0x12, 0x12, 0x17, 0xF2, 0x92, 0x96, 0x9A, 0x92, 0x97, 0x92, 0x12, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x07, 0x00,/*芳685*/},\n        {\n\n                0x04, 0x04, 0x04, 0xFC, 0x25, 0x26, 0x24, 0x24, 0x24, 0xE4, 0x04, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x08, 0x08, 0x08, 0x07, 0x00,/*方686*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x04, 0x04, 0xFD, 0x26, 0x24, 0xE4, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*肪687*/},\n        {\n\n                0x00, 0xFE, 0x4A, 0x4A, 0xCA, 0x5A, 0x6B, 0x4A, 0x4A, 0x4A, 0x4E, 0x08, 0x07, 0x08, 0x04, 0x03,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*房688*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x04, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*防689*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*妨690*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x04, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*仿691*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x04, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*访692*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*纺693*/},\n        {\n\n                0x08, 0xF9, 0x4A, 0x48, 0xC8, 0x20, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x08, 0x05, 0x02, 0x05, 0x08,/*放694*/},\n        {\n\n                0x12, 0x52, 0x52, 0x57, 0xFA, 0x02, 0xFA, 0x57, 0x52, 0x52, 0x12, 0x02, 0x02, 0x02, 0x02, 0x0F,\n                0x00, 0x0F, 0x02, 0x02, 0x02, 0x02,/*菲695*/},\n        {\n\n                0x04, 0x24, 0x24, 0x24, 0xFF, 0x00, 0xFF, 0x24, 0x24, 0x24, 0x04, 0x01, 0x01, 0x01, 0x01, 0x0F,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*非696*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0x24, 0x24, 0xFF, 0x00, 0xFF, 0x24, 0x24, 0x03, 0x01, 0x03, 0x00, 0x01,\n                0x01, 0x0F, 0x00, 0x0F, 0x01, 0x01,/*啡697*/},\n        {\n\n                0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x7E, 0x90, 0x28, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x01, 0x02, 0x04, 0x0F,/*飞698*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x42, 0x7E, 0x42, 0x42, 0x7E, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*肥699*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x52, 0x52, 0xFE, 0x02, 0x02, 0xFE, 0x52, 0x52, 0x00, 0x0F, 0x08, 0x09, 0x09,\n                0x0F, 0x08, 0x08, 0x0F, 0x09, 0x09,/*匪700*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x24, 0x24, 0xFF, 0x00, 0xFF, 0x24, 0x24, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x01, 0x0F, 0x00, 0x0F, 0x01, 0x01,/*诽701*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x10, 0x10, 0xD0, 0x3F, 0xD0, 0x12, 0x14, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*吠702*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xE4, 0x24, 0xFF, 0x24, 0x24, 0xE4, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x03, 0x00, 0x0F, 0x00, 0x02, 0x03,/*肺703*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x32, 0x22, 0xE2, 0xBB, 0xA2, 0xAA, 0xB2, 0x22, 0x08, 0x07, 0x08, 0x04, 0x03,\n                0x08, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*废704*/},\n        {\n\n                0x22, 0x44, 0x00, 0xF2, 0x92, 0xFF, 0x92, 0xFF, 0x92, 0x9E, 0x80, 0x04, 0x02, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x0F, 0x04, 0x04, 0x03,/*沸705*/},\n        {\n\n                0x02, 0xBA, 0xAA, 0xEA, 0xBF, 0xAA, 0xFF, 0xAA, 0xAA, 0xAE, 0xE0, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*费706*/},\n        {\n\n                0x42, 0x42, 0xA2, 0x97, 0x8A, 0x82, 0x8A, 0x97, 0xA2, 0x42, 0x42, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x08, 0x08, 0x07, 0x00, 0x00,/*芬707*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x10, 0x2C, 0xE3, 0x20, 0xE3, 0x0C, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x08, 0x06, 0x01, 0x08, 0x0F, 0x00,/*酚708*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x10, 0x2C, 0xE3, 0x20, 0x23, 0xEC, 0x10, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x06, 0x01, 0x08, 0x08, 0x07, 0x00,/*吩709*/},\n        {\n\n                0x08, 0xA4, 0x6B, 0x2A, 0x2A, 0x6A, 0xAA, 0x2A, 0xEA, 0x0A, 0x02, 0x01, 0x08, 0x05, 0x03, 0x09,\n                0x0F, 0x00, 0x01, 0x03, 0x04, 0x0E,/*氛710*/},\n        {\n\n                0x20, 0x10, 0x2C, 0x23, 0xE0, 0x20, 0x20, 0x23, 0xEC, 0x10, 0x20, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x08, 0x08, 0x08, 0x07, 0x00, 0x00,/*分711*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0x2C, 0xE3, 0x20, 0x23, 0xEC, 0x10, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x06, 0x01, 0x08, 0x08, 0x07, 0x00,/*纷712*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x04, 0x3C, 0xC5, 0x06, 0xC4, 0x3C, 0x04, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*坟713*/},\n        {\n\n                0x12, 0x0A, 0xBF, 0x0A, 0x12, 0xC0, 0x12, 0x0A, 0x3F, 0x8A, 0x12, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x05, 0x08, 0x08,/*焚714*/},\n        {\n\n                0x10, 0x21, 0x22, 0x10, 0x2C, 0x23, 0xE0, 0x20, 0x23, 0xEC, 0x10, 0x04, 0x02, 0x01, 0x08, 0x04,\n                0x03, 0x00, 0x08, 0x08, 0x07, 0x00,/*汾715*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x10, 0x2C, 0xE3, 0x20, 0x23, 0xEC, 0x10, 0x01, 0x00, 0x0F, 0x01, 0x08,\n                0x06, 0x01, 0x08, 0x08, 0x07, 0x00,/*粉716*/},\n        {\n\n                0x24, 0xE4, 0x54, 0x54, 0x4C, 0xC7, 0x4C, 0x54, 0x54, 0xE4, 0x24, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x07, 0x05, 0x05, 0x05, 0x0F, 0x00,/*奋717*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x10, 0x2C, 0xE3, 0x20, 0x20, 0x23, 0xEC, 0x10, 0x00, 0x0F, 0x00, 0x08, 0x06,\n                0x01, 0x00, 0x08, 0x08, 0x07, 0x00,/*份718*/},\n        {\n\n                0x08, 0x84, 0x4A, 0x29, 0x18, 0x08, 0x88, 0x89, 0x7A, 0x04, 0x08, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*忿719*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xD2, 0x7A, 0x52, 0x57, 0x52, 0x7A, 0xD2, 0x00, 0x00, 0x0F, 0x00, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*愤720*/},\n        {\n\n                0x04, 0x54, 0x4D, 0xE6, 0x44, 0x5F, 0x44, 0xE6, 0x4D, 0x54, 0x04, 0x02, 0x0A, 0x06, 0x03, 0x02,\n                0x02, 0x02, 0x03, 0x06, 0x0A, 0x02,/*粪721*/},\n        {\n\n                0x04, 0x24, 0x24, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x24, 0x24, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*丰722*/},\n        {\n\n                0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x48, 0x88, 0x08, 0xFF, 0x08, 0x08, 0x09, 0x09, 0x07, 0x05,\n                0x05, 0x00, 0x09, 0x08, 0x0F, 0x00,/*封723*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0xFE, 0x92, 0x62, 0x92, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x07, 0x0C,/*枫724*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x54, 0x57, 0xEA, 0x4A, 0x56, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x05, 0x05, 0x0F, 0x05, 0x05,/*蜂725*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0x54, 0x57, 0xEA, 0x4A, 0x56, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x05, 0x05, 0x0F, 0x05, 0x05,/*峰726*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x54, 0x57, 0xEA, 0x4A, 0x56, 0x10, 0x00, 0x0F, 0x04, 0x02, 0x04,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x04,/*锋727*/},\n        {\n\n                0x00, 0xFE, 0x12, 0x22, 0xC2, 0x22, 0x1A, 0x02, 0xFE, 0x00, 0x00, 0x08, 0x07, 0x02, 0x01, 0x00,\n                0x01, 0x02, 0x00, 0x03, 0x04, 0x0F,/*风728*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0xF4, 0x55, 0x96, 0x54, 0x14, 0xF4, 0x04, 0x09, 0x04, 0x0B, 0x04, 0x03,\n                0x04, 0x03, 0x04, 0x00, 0x07, 0x0C,/*疯729*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x14, 0x56, 0x4B, 0xEA, 0x4A, 0x56, 0x10, 0x08, 0x06, 0x01, 0x06, 0x04,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x04,/*烽730*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x14, 0xB6, 0xAB, 0xFA, 0xAA, 0xB6, 0x10, 0x10, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*逢731*/},\n        {\n\n                0x02, 0x04, 0x80, 0x01, 0x3D, 0x21, 0x21, 0x21, 0x21, 0x3F, 0xE0, 0x02, 0x01, 0x00, 0x01, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x08, 0x07,/*冯732*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x21, 0xE2, 0x10, 0x94, 0xAB, 0xFA, 0xAA, 0x96, 0x04, 0x04, 0x02, 0x08, 0x07,\n                0x08, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*缝733*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFE, 0x0A, 0x92, 0x62, 0x92, 0x0A, 0xFE, 0x00, 0x00, 0x07, 0x0A, 0x07, 0x01,\n                0x00, 0x00, 0x00, 0x01, 0x07, 0x0C,/*讽734*/},\n        {\n\n                0x20, 0xA2, 0x6A, 0xBA, 0xAE, 0xEB, 0xAA, 0xAA, 0x6A, 0xA2, 0x20, 0x01, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x01,/*奉735*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x52, 0x92, 0x12, 0xF2, 0x02, 0xFE, 0x00, 0x00, 0x08, 0x07, 0x00, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x03, 0x04, 0x0F,/*凤736*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xF2, 0x92, 0xFF, 0x92, 0xFF, 0x92, 0x9E, 0x80, 0x00, 0x0F, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x0F, 0x04, 0x04, 0x03,/*佛737*/},\n        {\n\n                0x11, 0x91, 0x89, 0x89, 0x85, 0xBF, 0x81, 0x85, 0x85, 0x89, 0x11, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*否738*/},\n        {\n\n                0x40, 0x48, 0x48, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x48, 0x48, 0x40, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*夫739*/},\n        {\n\n                0x82, 0xFA, 0xAA, 0xFF, 0xAA, 0xFB, 0x92, 0xEF, 0x08, 0xF8, 0x08, 0x08, 0x04, 0x03, 0x0A, 0x0A,\n                0x06, 0x08, 0x05, 0x02, 0x05, 0x08,/*敷740*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x40, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*肤741*/},\n        {\n\n                0xFE, 0x92, 0xFD, 0x00, 0xFE, 0x92, 0xFE, 0x00, 0x2A, 0xB2, 0x69, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x00, 0x00, 0x01, 0x09, 0x0F, 0x01,/*孵742*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*扶743*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xF2, 0x92, 0xFF, 0x92, 0xFF, 0x92, 0x9E, 0x80, 0x08, 0x0F, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x0F, 0x04, 0x04, 0x03,/*拂744*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0xC1, 0x5D, 0x55, 0xD5, 0x55, 0x5D, 0xC1, 0x01, 0x01, 0x0F, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*辐745*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xDD, 0x55, 0xD5, 0x55, 0xDD, 0x01, 0x00, 0x0F, 0x01, 0x01,\n                0x00, 0x0F, 0x05, 0x07, 0x05, 0x0F,/*幅746*/},\n        {\n\n                0xA8, 0xA4, 0xFB, 0xAA, 0xFA, 0xAA, 0xEA, 0x0A, 0xFA, 0x02, 0x02, 0x0B, 0x0A, 0x07, 0x02, 0x0F,\n                0x02, 0x0A, 0x0E, 0x03, 0x04, 0x0E,/*氟747*/},\n        {\n\n                0x84, 0x43, 0xE2, 0x16, 0x42, 0x44, 0x43, 0x42, 0xF6, 0x42, 0x42, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x02, 0x08, 0x08, 0x0F, 0x00, 0x00,/*符748*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x10, 0x10, 0xD0, 0x3F, 0xD0, 0x12, 0x14, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*伏749*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x2A, 0x32, 0x26, 0xAA, 0x61, 0x29, 0x05, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x09, 0x0F, 0x01, 0x01, 0x01,/*俘750*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0xFE, 0x42, 0xD2, 0x52, 0xCE, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x0F, 0x08, 0x05, 0x02, 0x0D,/*服751*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0x2A, 0x32, 0x26, 0xAA, 0x61, 0x29, 0x05, 0x04, 0x02, 0x01, 0x00, 0x01,\n                0x01, 0x09, 0x0F, 0x01, 0x01, 0x01,/*浮752*/},\n        {\n\n                0x10, 0x21, 0x02, 0x20, 0xAA, 0xB2, 0xA2, 0xA3, 0xB2, 0xAA, 0x20, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*涪753*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0xC1, 0x5D, 0x55, 0xD5, 0x55, 0x5D, 0xC1, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*福754*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x10, 0xFC, 0x03, 0x10, 0xFF, 0x12, 0x14, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x08, 0x07, 0x00, 0x07, 0x08,/*袱755*/},\n        {\n\n                0xF2, 0x92, 0x92, 0xFF, 0x92, 0x92, 0xFF, 0x92, 0x92, 0x9E, 0x80, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x0F, 0x00, 0x04, 0x04, 0x03,/*弗756*/},\n        {\n\n                0x04, 0xF4, 0x54, 0x54, 0x54, 0xFF, 0x54, 0x54, 0x55, 0xF6, 0x04, 0x00, 0x0F, 0x01, 0x01, 0x01,\n                0x07, 0x01, 0x01, 0x09, 0x0F, 0x00,/*甫757*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x20, 0x22, 0xE2, 0x3E, 0xE2, 0x22, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*抚758*/},\n        {\n\n                0x74, 0x4F, 0xF4, 0x40, 0xF4, 0x54, 0x54, 0xFF, 0x54, 0x55, 0xF6, 0x02, 0x02, 0x0F, 0x01, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*辅759*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xFC, 0x44, 0xE4, 0x15, 0x46, 0x44, 0xF4, 0x44, 0x00, 0x0F, 0x08, 0x07, 0x00,\n                0x0F, 0x00, 0x01, 0x0A, 0x0F, 0x00,/*俯760*/},\n        {\n\n                0x20, 0x24, 0x52, 0x55, 0x48, 0xC8, 0x48, 0x55, 0x52, 0x24, 0x20, 0x08, 0x09, 0x0B, 0x0D, 0x09,\n                0x0F, 0x09, 0x0D, 0x0B, 0x09, 0x08,/*釜761*/},\n        {\n\n                0x20, 0x24, 0xD2, 0x55, 0x48, 0x48, 0x28, 0x35, 0x12, 0x24, 0x20, 0x08, 0x04, 0x03, 0x01, 0x01,\n                0x01, 0x0F, 0x01, 0x01, 0x01, 0x00,/*斧762*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x04, 0xF4, 0x54, 0xFF, 0x54, 0x55, 0xF6, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x01, 0x07, 0x01, 0x09, 0x0F,/*脯763*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFC, 0x44, 0xE4, 0x55, 0x46, 0xF4, 0x44, 0x07, 0x08, 0x0F, 0x08, 0x07,\n                0x00, 0x0F, 0x01, 0x0A, 0x0F, 0x00,/*腑764*/},\n        {\n\n                0x00, 0xFC, 0x44, 0x24, 0xF4, 0x0D, 0xA6, 0x24, 0x24, 0xFC, 0x24, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x09, 0x08, 0x0F, 0x00,/*府765*/},\n        {\n\n                0x00, 0xFE, 0x12, 0x8A, 0xBE, 0x82, 0xCB, 0x9A, 0xAA, 0xBE, 0x8A, 0x08, 0x07, 0x00, 0x0F, 0x00,\n                0x0A, 0x05, 0x0A, 0x00, 0x08, 0x0F,/*腐766*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xFF, 0x24, 0x20, 0x00, 0xFF, 0x08, 0x10, 0x60, 0x08, 0x07, 0x04, 0x0F, 0x09,\n                0x09, 0x08, 0x0B, 0x08, 0x08, 0x08,/*赴767*/},\n        {\n\n                0xC1, 0x5D, 0x55, 0xD5, 0x55, 0x5D, 0xC1, 0x00, 0xFC, 0x00, 0xFF, 0x0F, 0x05, 0x05, 0x07, 0x05,\n                0x05, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*副768*/},\n        {\n\n                0x81, 0x5D, 0xB5, 0x55, 0x1F, 0xF5, 0x55, 0x5F, 0x55, 0xF5, 0x1D, 0x02, 0x01, 0x0F, 0x00, 0x0A,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*覆769*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x90, 0x12, 0xF2, 0x90, 0xFF, 0x12, 0x14, 0x08, 0x06, 0x08, 0x08, 0x0F,\n                0x08, 0x07, 0x04, 0x03, 0x04, 0x0E,/*赋770*/},\n        {\n\n                0x04, 0x02, 0x7D, 0xD5, 0x55, 0x55, 0x55, 0x55, 0x55, 0x7D, 0x01, 0x00, 0x0A, 0x09, 0x0B, 0x05,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x08,/*复771*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xFA, 0x2A, 0x2A, 0xFF, 0x2A, 0x2B, 0xFA, 0x02, 0x00, 0x0F, 0x00, 0x02, 0x06,\n                0x0A, 0x02, 0x0A, 0x0F, 0x02, 0x02,/*傅772*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x08, 0x48, 0x88, 0x08, 0x08, 0xFF, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x01, 0x08, 0x08, 0x0F, 0x00,/*付773*/},\n        {\n\n                0x00, 0xFE, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xAE, 0xE0, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*阜774*/},\n        {\n\n                0x08, 0x04, 0x0B, 0x30, 0x40, 0x80, 0x40, 0x30, 0x09, 0x02, 0x0C, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*父775*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x02, 0x7D, 0xD5, 0x55, 0x55, 0x7D, 0x01, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*腹776*/},\n        {\n\n                0x08, 0xF4, 0x13, 0x12, 0x12, 0xD2, 0x1A, 0x16, 0x10, 0xF0, 0x00, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*负777*/},\n        {\n\n                0x06, 0x8A, 0xEA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xEA, 0x8A, 0x06, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*富778*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*讣779*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x10, 0xFC, 0x03, 0x48, 0x88, 0xFF, 0x08, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x00, 0x08, 0x0F, 0x00,/*附780*/},\n        {\n\n                0x88, 0x78, 0x0F, 0x88, 0x78, 0x02, 0x22, 0x22, 0x22, 0x22, 0xFE, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*妇781*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xFA, 0x2A, 0x2A, 0xFF, 0x2A, 0x2B, 0xFA, 0x04, 0x04, 0x02, 0x00, 0x02,\n                0x06, 0x0A, 0x02, 0x0A, 0x0F, 0x02,/*缚782*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x10, 0xFC, 0x03, 0x28, 0xC8, 0x08, 0xFF, 0x08, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x08, 0x0F, 0x00,/*咐783*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x02, 0xFA, 0xAF, 0xAA, 0xAA, 0xAF, 0xFA, 0x82, 0x03, 0x01, 0x03, 0x01, 0x06,\n                0x04, 0x06, 0x05, 0x06, 0x08, 0x0F,/*噶784*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x01, 0x7D, 0xD5, 0x57, 0x55, 0xD5, 0x7D, 0x01, 0x03, 0x01, 0x03, 0x02, 0x0A,\n                0x0A, 0x0B, 0x05, 0x05, 0x0B, 0x0D,/*嘎785*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x44, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x09, 0x04, 0x02, 0x03, 0x04, 0x08,/*该786*/},\n        {\n\n                0xE2, 0x22, 0x22, 0x3E, 0x20, 0x10, 0xEF, 0x08, 0x88, 0x78, 0x08, 0x0F, 0x04, 0x02, 0x01, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*改787*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0xFE, 0x92, 0xFE, 0x00, 0x3A, 0xA2, 0x7E, 0x22, 0x00, 0x0F, 0x00, 0x0F, 0x0A,\n                0x04, 0x08, 0x06, 0x01, 0x0F, 0x08,/*概788*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xF2, 0x82, 0x82, 0xFE, 0x92, 0x92, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*钙789*/},\n        {\n\n                0x40, 0x54, 0x55, 0x56, 0x54, 0x7C, 0x54, 0x56, 0x55, 0x54, 0x40, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盖790*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x92, 0xFE, 0x00, 0x3A, 0xA2, 0x7E, 0x22, 0x04, 0x02, 0x00, 0x0F, 0x0A,\n                0x04, 0x08, 0x06, 0x01, 0x0F, 0x08,/*溉791*/},\n        {\n\n                0x40, 0x42, 0x42, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x42, 0x42, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*干792*/},\n        {\n\n                0x04, 0x04, 0xFF, 0x44, 0x44, 0x44, 0x44, 0x44, 0xFF, 0x04, 0x04, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x0F, 0x00, 0x00,/*甘793*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*杆794*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x44, 0xFF, 0x44, 0x44, 0x44, 0xFF, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*柑795*/},\n        {\n\n                0x08, 0x24, 0x23, 0x26, 0x2A, 0xE2, 0x24, 0x23, 0x26, 0x2A, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*竿796*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x40, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*肝797*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xFF, 0x24, 0x20, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x08, 0x07, 0x04, 0x0F, 0x09,\n                0x09, 0x08, 0x08, 0x0F, 0x08, 0x08,/*赶798*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xEA, 0xAA, 0xEA, 0x02, 0x9F, 0x62, 0x9B, 0xC2, 0x09, 0x06, 0x00, 0x06, 0x08,\n                0x0A, 0x0D, 0x08, 0x0C, 0x02, 0x0D,/*感799*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x90, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*秆800*/},\n        {\n\n                0x08, 0xFA, 0xAA, 0xAE, 0xF8, 0x28, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x02, 0x03, 0x02, 0x02, 0x0F,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*敢801*/},\n        {\n\n                0x0A, 0xFE, 0xAB, 0xFE, 0x0A, 0x94, 0xB7, 0xEA, 0xAA, 0xB6, 0x90, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x0B, 0x04, 0x02, 0x04, 0x0B, 0x00,/*赣802*/},\n        {\n\n                0x00, 0xFF, 0x01, 0x09, 0x89, 0x51, 0x21, 0x51, 0x8D, 0x01, 0xFF, 0x00, 0x0F, 0x00, 0x01, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x0F,/*冈803*/},\n        {\n\n                0xFE, 0x12, 0xA2, 0x42, 0xA2, 0x12, 0xFE, 0x00, 0xFC, 0x00, 0xFF, 0x0F, 0x01, 0x00, 0x00, 0x00,\n                0x09, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*刚804*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x12, 0xA2, 0x42, 0xA2, 0x12, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x01, 0x00, 0x00, 0x00, 0x09, 0x0F,/*钢805*/},\n        {\n\n                0x48, 0x47, 0xFC, 0x44, 0x44, 0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x0F, 0x08, 0x07, 0x04, 0x0F,\n                0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,/*缸806*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,/*肛807*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xFE, 0x12, 0xA2, 0x42, 0xA2, 0x12, 0xFE, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x01, 0x00, 0x00, 0x00, 0x09, 0x0F,/*纲808*/},\n        {\n\n                0x00, 0xF6, 0x14, 0x34, 0x54, 0x97, 0x54, 0x34, 0x14, 0xF6, 0x00, 0x00, 0x0F, 0x00, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x08, 0x0F, 0x00,/*岗809*/},\n        {\n\n                0x22, 0x44, 0x90, 0x54, 0xBF, 0x94, 0x94, 0x94, 0xBF, 0x54, 0x90, 0x08, 0x04, 0x02, 0x00, 0x07,\n                0x0A, 0x0A, 0x0A, 0x0B, 0x0C, 0x00,/*港810*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*杠811*/},\n        {\n\n                0x8C, 0x8B, 0xEA, 0xAE, 0xAA, 0xAC, 0xAB, 0xAA, 0xEE, 0x8A, 0x8A, 0x0F, 0x00, 0x00, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0E, 0x00, 0x08, 0x0F,/*篙812*/},\n        {\n\n                0x80, 0xBE, 0xAA, 0xAA, 0xEB, 0xAA, 0xAA, 0xAA, 0xAA, 0xBE, 0x80, 0x04, 0x02, 0x05, 0x04, 0x04,\n                0x0E, 0x04, 0x04, 0x05, 0x02, 0x04,/*皋813*/},\n        {\n\n                0x82, 0x82, 0xBA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBA, 0x82, 0x82, 0x0F, 0x00, 0x00, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0E, 0x00, 0x08, 0x0F,/*高814*/},\n        {\n\n                0x62, 0x22, 0xEE, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xEE, 0x22, 0x62, 0x00, 0x00, 0x0F, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0F, 0x00, 0x00,/*膏815*/},\n        {\n\n                0x00, 0x24, 0x25, 0x26, 0x24, 0xFC, 0x24, 0x26, 0x25, 0x24, 0x00, 0x09, 0x05, 0x01, 0x05, 0x09,\n                0x01, 0x05, 0x09, 0x01, 0x05, 0x09,/*羔816*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x04, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x04, 0x01, 0x00, 0x0F, 0x00, 0x0D,\n                0x01, 0x0D, 0x01, 0x0D, 0x01, 0x0D,/*糕817*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x82, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x82, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x00, 0x0E, 0x0A, 0x0E, 0x00, 0x0F,/*搞818*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x82, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x82, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x00, 0x0E, 0x0A, 0x0E, 0x00, 0x0F,/*镐819*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x82, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x82, 0x01, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x0E, 0x0A, 0x0E, 0x00, 0x0F,/*稿820*/},\n        {\n\n                0x20, 0xA8, 0xA6, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0xA4, 0xA4, 0x20, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*告821*/},\n        {\n\n                0x41, 0x5D, 0x55, 0x55, 0x55, 0x55, 0x5D, 0x41, 0x41, 0xDF, 0x41, 0x00, 0x07, 0x05, 0x05, 0x05,\n                0x05, 0x07, 0x00, 0x08, 0x0F, 0x00,/*哥822*/},\n        {\n\n                0x5D, 0x55, 0x5D, 0x41, 0xDF, 0x41, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x07, 0x05, 0x07, 0x08, 0x0F,\n                0x00, 0x08, 0x06, 0x01, 0x06, 0x08,/*歌823*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xFD, 0xA2, 0x5C, 0x2A, 0x5A, 0x82, 0xFE, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x00, 0x07, 0x05, 0x07, 0x08, 0x0F,/*搁824*/},\n        {\n\n                0x10, 0x10, 0x10, 0x10, 0x3F, 0xD0, 0x08, 0x89, 0x4A, 0x28, 0x08, 0x00, 0x08, 0x08, 0x04, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x0F,/*戈825*/},\n        {\n\n                0x10, 0xA8, 0xA4, 0xA3, 0xA4, 0x08, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x00, 0x0F, 0x04, 0x04, 0x0F,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸽826*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*胳827*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x44, 0x24, 0x5D, 0x56, 0x54, 0xD4, 0x54, 0x04, 0x09, 0x04, 0x03, 0x00, 0x04,\n                0x0A, 0x09, 0x09, 0x08, 0x08, 0x0C,/*疙828*/},\n        {\n\n                0x86, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0x86, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x0E, 0x0A, 0x0B, 0x0A,\n                0x0E, 0x00, 0x00, 0x01, 0x08, 0x0F,/*割829*/},\n        {\n\n                0x02, 0xE2, 0xAF, 0xAA, 0xAA, 0xFA, 0xAA, 0xAA, 0xAF, 0xE2, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*革830*/},\n        {\n\n                0x02, 0x82, 0xFA, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0xAA, 0xFA, 0x82, 0x02, 0x01, 0x06, 0x04, 0x06,\n                0x05, 0x06, 0x04, 0x04, 0x08, 0x0F,/*葛831*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*格832*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x10, 0xAC, 0xA3, 0xA4, 0xA8, 0x10, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*蛤833*/},\n        {\n\n                0xF9, 0x82, 0x90, 0x49, 0x57, 0x25, 0x55, 0x4D, 0x81, 0x81, 0xFF, 0x0F, 0x00, 0x00, 0x0F, 0x05,\n                0x05, 0x05, 0x0F, 0x00, 0x08, 0x0F,/*阁834*/},\n        {\n\n                0xFF, 0x31, 0xCF, 0x00, 0xC1, 0x5D, 0xD5, 0x55, 0xD5, 0x5D, 0xC1, 0x0F, 0x02, 0x01, 0x00, 0x0F,\n                0x00, 0x02, 0x0F, 0x02, 0x08, 0x0F,/*隔835*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*铬836*/},\n        {\n\n                0x20, 0x20, 0x10, 0x08, 0x04, 0xF3, 0x04, 0x08, 0x10, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*个837*/},\n        {\n\n                0x48, 0x44, 0xA7, 0xAA, 0x92, 0x92, 0x92, 0xAA, 0xA6, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x0F, 0x00, 0x00,/*各838*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0x10, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*给839*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*根840*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x07, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*跟841*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x44, 0x88, 0xFF, 0x88, 0x88, 0xFF, 0x88, 0x02, 0x01, 0x0F, 0x01, 0x0A,\n                0x04, 0x03, 0x00, 0x00, 0x0F, 0x00,/*耕842*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xAA, 0xFA, 0x02, 0x08, 0x09, 0x0A, 0x04, 0x04,\n                0x0B, 0x08, 0x08, 0x08, 0x08, 0x08,/*更843*/},\n        {\n\n                0x00, 0xFC, 0x44, 0x54, 0x54, 0x55, 0xFE, 0x54, 0x54, 0xF4, 0x44, 0x08, 0x07, 0x08, 0x09, 0x05,\n                0x03, 0x01, 0x03, 0x05, 0x09, 0x08,/*庚844*/},\n        {\n\n                0x28, 0x9A, 0x8A, 0xCB, 0x9A, 0x8E, 0x9A, 0xCB, 0x8A, 0x9A, 0x28, 0x0A, 0x0A, 0x0A, 0x06, 0x02,\n                0x03, 0x02, 0x06, 0x0A, 0x0A, 0x0A,/*羹845*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFA, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xFA, 0x04, 0x07, 0x02, 0x00, 0x08,\n                0x05, 0x02, 0x05, 0x08, 0x08, 0x08,/*埂846*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x22, 0x1C, 0x80, 0x7F, 0x80, 0x10, 0x0C, 0x02, 0x03, 0x02, 0x0F, 0x09,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*耿847*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFA, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x05, 0x02, 0x05, 0x08, 0x08, 0x08,/*梗848*/},\n        {\n\n                0x00, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x02, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*工849*/},\n        {\n\n                0x04, 0x04, 0xFC, 0x04, 0x24, 0x10, 0xEF, 0x08, 0x88, 0x78, 0x08, 0x02, 0x02, 0x01, 0x01, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*攻850*/},\n        {\n\n                0x04, 0x04, 0xFC, 0x04, 0x04, 0x08, 0xFF, 0x08, 0x08, 0x08, 0xF8, 0x02, 0x02, 0x01, 0x09, 0x05,\n                0x03, 0x00, 0x00, 0x08, 0x08, 0x07,/*功851*/},\n        {\n\n                0x10, 0x94, 0x54, 0x3F, 0xD4, 0x14, 0x14, 0x3F, 0x54, 0x94, 0x10, 0x01, 0x04, 0x02, 0x08, 0x0F,\n                0x01, 0x06, 0x01, 0x06, 0x00, 0x01,/*恭852*/},\n        {\n\n                0x24, 0xA4, 0x94, 0xCC, 0xA7, 0xA4, 0x9C, 0xF5, 0xAE, 0xA4, 0x34, 0x02, 0x0A, 0x06, 0x03, 0x02,\n                0x02, 0x02, 0x03, 0x06, 0x0A, 0x02,/*龚853*/},\n        {\n\n                0x10, 0xFC, 0x83, 0x88, 0xFF, 0x88, 0x88, 0x88, 0xFF, 0x88, 0x80, 0x00, 0x0F, 0x08, 0x04, 0x02,\n                0x00, 0x00, 0x00, 0x02, 0x04, 0x08,/*供854*/},\n        {\n\n                0x80, 0xFE, 0xAB, 0xAA, 0xFE, 0x00, 0xF2, 0x92, 0x92, 0x92, 0x9E, 0x04, 0x02, 0x01, 0x08, 0x0F,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*躬855*/},\n        {\n\n                0x40, 0x20, 0x18, 0x07, 0xC0, 0x30, 0x00, 0x07, 0x18, 0x20, 0x40, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x05, 0x06, 0x0C, 0x00,/*公856*/},\n        {\n\n                0x06, 0x02, 0x7A, 0x4A, 0x4A, 0x4B, 0x4A, 0x4A, 0x7A, 0x02, 0x06, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x00,/*宫857*/},\n        {\n\n                0x00, 0xF2, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x9E, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*弓858*/},\n        {\n\n                0x04, 0x04, 0xFC, 0x04, 0x00, 0xFE, 0x22, 0x42, 0xFE, 0x00, 0x00, 0x02, 0x02, 0x01, 0x09, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*巩859*/},\n        {\n\n                0x88, 0x89, 0x89, 0x89, 0x09, 0xEF, 0x89, 0x09, 0x89, 0x49, 0x08, 0x04, 0x04, 0x02, 0x01, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*汞860*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x80, 0x88, 0xFF, 0x88, 0x88, 0xFF, 0x88, 0x80, 0x08, 0x0F, 0x00, 0x08, 0x04,\n                0x02, 0x00, 0x00, 0x02, 0x04, 0x08,/*拱861*/},\n        {\n\n                0x08, 0xE9, 0x29, 0x29, 0x29, 0xAF, 0x29, 0x29, 0x29, 0xE9, 0x08, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贡862*/},\n        {\n\n                0x80, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x80, 0x00, 0x08, 0x04, 0x02, 0x00,\n                0x00, 0x00, 0x02, 0x04, 0x08, 0x00,/*共863*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x10, 0x8C, 0x47, 0x34, 0x84, 0x04, 0xFC, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x01, 0x01, 0x01, 0x0B, 0x08, 0x07,/*钩864*/},\n        {\n\n                0x20, 0x10, 0x8C, 0x47, 0x34, 0x04, 0x44, 0x84, 0x04, 0x04, 0xFC, 0x00, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x0B, 0x08, 0x08, 0x07,/*勾865*/},\n        {\n\n                0x10, 0x21, 0x02, 0x10, 0x88, 0x47, 0x34, 0x84, 0x04, 0x04, 0xFC, 0x04, 0x02, 0x01, 0x00, 0x01,\n                0x01, 0x01, 0x01, 0x0B, 0x08, 0x07,/*沟866*/},\n        {\n\n                0x42, 0x22, 0xDA, 0x57, 0x52, 0x52, 0x52, 0xD7, 0x12, 0x12, 0xF2, 0x00, 0x00, 0x07, 0x02, 0x02,\n                0x02, 0x02, 0x0B, 0x08, 0x08, 0x07,/*苟867*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x10, 0xE8, 0x27, 0x24, 0xE4, 0x04, 0xFC, 0x01, 0x08, 0x08, 0x07, 0x00,\n                0x03, 0x01, 0x01, 0x09, 0x08, 0x07,/*狗868*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0xFE, 0x92, 0x92, 0x91, 0x91, 0x91, 0x02, 0x02, 0x01, 0x09, 0x06,\n                0x01, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*垢869*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0x8C, 0x47, 0x34, 0x84, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x01, 0x0B, 0x08, 0x07,/*构870*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x08, 0xC7, 0x34, 0x84, 0x04, 0xFC, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x01, 0x01, 0x0B, 0x08, 0x07,/*购871*/},\n        {\n\n                0xE8, 0x27, 0xE4, 0x04, 0xFC, 0x00, 0x24, 0xAB, 0x52, 0x4A, 0xC6, 0x03, 0x01, 0x09, 0x08, 0x07,\n                0x00, 0x09, 0x08, 0x05, 0x02, 0x01,/*够872*/},\n        {\n\n                0x02, 0xBA, 0xAA, 0xAA, 0xAA, 0xEF, 0xAA, 0xAA, 0xAA, 0xBA, 0x02, 0x02, 0x02, 0x02, 0x03, 0x02,\n                0x0E, 0x02, 0x03, 0x02, 0x02, 0x02,/*辜873*/},\n        {\n\n                0xA2, 0x62, 0x3A, 0x27, 0xE2, 0x02, 0xA2, 0xA7, 0xFA, 0xA2, 0xA2, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*菇874*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x08, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x08, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*咕875*/},\n        {\n\n                0x24, 0x23, 0xFA, 0xA6, 0xF2, 0x14, 0xD3, 0x52, 0xF6, 0x52, 0xD2, 0x01, 0x09, 0x0F, 0x00, 0x0F,\n                0x08, 0x0B, 0x08, 0x0F, 0x0A, 0x0B,/*箍876*/},\n        {\n\n                0x10, 0xFC, 0x0B, 0xC8, 0x48, 0x48, 0x7F, 0x48, 0x48, 0xC8, 0x08, 0x00, 0x0F, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*估877*/},\n        {\n\n                0x10, 0x21, 0x0A, 0xC8, 0x48, 0x48, 0x7F, 0x48, 0x48, 0xC8, 0x08, 0x04, 0x02, 0x01, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*沽878*/},\n        {\n\n                0x82, 0x82, 0xF2, 0x4E, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x01, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x0F, 0x0A, 0x0C, 0x03,/*孤879*/},\n        {\n\n                0x88, 0x78, 0x0F, 0x88, 0x78, 0x00, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*姑880*/},\n        {\n\n                0x02, 0xEA, 0xAA, 0xAF, 0xAA, 0xEA, 0x24, 0xE4, 0x3F, 0xE4, 0x04, 0x08, 0x09, 0x0A, 0x04, 0x06,\n                0x05, 0x08, 0x05, 0x02, 0x05, 0x08,/*鼓881*/},\n        {\n\n                0x08, 0xC8, 0x48, 0x48, 0x48, 0x7F, 0x48, 0x48, 0x48, 0xC8, 0x08, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*古882*/},\n        {\n\n                0x40, 0x5C, 0x54, 0x54, 0x54, 0x7F, 0x54, 0x54, 0x54, 0x5C, 0x60, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*蛊883*/},\n        {\n\n                0x30, 0x10, 0xDF, 0x55, 0x55, 0x55, 0x5D, 0x51, 0xDF, 0x10, 0x30, 0x00, 0x00, 0x0F, 0x05, 0x05,\n                0x05, 0x05, 0x0D, 0x0F, 0x00, 0x00,/*骨884*/},\n        {\n\n                0x40, 0x44, 0xA2, 0x91, 0x88, 0x84, 0x88, 0x91, 0xA2, 0x44, 0x40, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x0F, 0x00, 0x00,/*谷885*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x50, 0xCE, 0x42, 0x42, 0xDE, 0x10, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*股886*/},\n        {\n\n                0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x10, 0xEF, 0x08, 0x08, 0xF8, 0x08, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*故887*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x8A, 0xFA, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x07, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*顾888*/},\n        {\n\n                0xFF, 0x01, 0x09, 0xE9, 0x29, 0x3F, 0x29, 0xE9, 0x09, 0x01, 0xFF, 0x0F, 0x04, 0x04, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x04, 0x04, 0x0F,/*固889*/},\n        {\n\n                0x00, 0xFE, 0x4A, 0xEA, 0xBA, 0xAA, 0xAB, 0xFA, 0xAA, 0xAA, 0xAE, 0x08, 0x07, 0x00, 0x0F, 0x0A,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0A,/*雇890*/},\n        {\n\n                0x10, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x10, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x0F, 0x00, 0x01, 0x08, 0x08, 0x0F,/*刮891*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x7F, 0x81, 0x01, 0x00, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x08, 0x05, 0x0E, 0x01, 0x06, 0x08,/*瓜892*/},\n        {\n\n                0xE0, 0x2F, 0x29, 0xF9, 0x29, 0x2F, 0xE0, 0x00, 0xFC, 0x00, 0xFF, 0x0F, 0x02, 0x01, 0x00, 0x01,\n                0x0A, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*剐893*/},\n        {\n\n                0x86, 0x8A, 0xEA, 0xAA, 0xBA, 0xEB, 0xAA, 0xAA, 0xEA, 0x8A, 0x86, 0x04, 0x02, 0x09, 0x0A, 0x06,\n                0x02, 0x0A, 0x0E, 0x01, 0x02, 0x04,/*寡894*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*挂895*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x10, 0x94, 0xDF, 0x94, 0x10, 0xFF, 0x10, 0x60, 0x00, 0x0F, 0x00, 0x04, 0x04,\n                0x03, 0x02, 0x02, 0x0F, 0x00, 0x00,/*褂896*/},\n        {\n\n                0x48, 0x48, 0x4A, 0xFA, 0x0A, 0xFE, 0x09, 0xF9, 0x49, 0x28, 0x88, 0x02, 0x02, 0x01, 0x03, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x02, 0x03,/*乖897*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x9E, 0x92, 0xF2, 0x92, 0x92, 0x9E, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*拐898*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x52, 0x46, 0x2A, 0xD2, 0x2A, 0x46, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*怪899*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x0C, 0xF4, 0x54, 0x55, 0x56, 0x74, 0x0C, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*棺900*/},\n        {\n\n                0x40, 0x48, 0x49, 0x4A, 0x48, 0xF8, 0x48, 0x4A, 0x49, 0x48, 0x40, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*关901*/},\n        {\n\n                0x0C, 0x04, 0xF4, 0x54, 0x55, 0x56, 0x54, 0x54, 0x74, 0x04, 0x0C, 0x00, 0x00, 0x0F, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*官902*/},\n        {\n\n                0x46, 0xCA, 0x4A, 0xCA, 0x42, 0x02, 0x52, 0x92, 0x12, 0xFA, 0x16, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x08, 0x08, 0x08, 0x0A, 0x0B, 0x0C,/*冠903*/},\n        {\n\n                0x14, 0x64, 0x84, 0x7C, 0x00, 0xFE, 0x02, 0xF2, 0x02, 0xFE, 0x00, 0x04, 0x02, 0x01, 0x06, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*观904*/},\n        {\n\n                0x1C, 0x0B, 0xEA, 0xAE, 0xAA, 0xAC, 0xAB, 0xAA, 0xEE, 0x0A, 0x1A, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*管905*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0x0C, 0xF4, 0x54, 0x55, 0x56, 0x74, 0x0C, 0x00, 0x0F, 0x04, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*馆906*/},\n        {\n\n                0x48, 0x47, 0xFC, 0x44, 0xBA, 0xEF, 0xBA, 0xC2, 0xBA, 0xAF, 0xBA, 0x0F, 0x08, 0x07, 0x05, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*罐907*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xDF, 0x55, 0x5F, 0x55, 0xDF, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0B, 0x04, 0x03, 0x04, 0x0B, 0x00,/*惯908*/},\n        {\n\n                0x22, 0x44, 0x00, 0xBA, 0xEF, 0xBA, 0xC2, 0xBA, 0xAF, 0xBA, 0x82, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*灌909*/},\n        {\n\n                0x04, 0xDF, 0x55, 0x55, 0x55, 0xDF, 0x55, 0x55, 0x55, 0xDF, 0x04, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贯910*/},\n        {\n\n                0x20, 0x22, 0x24, 0xE8, 0x20, 0x3F, 0x20, 0xE8, 0x24, 0x22, 0x20, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*光911*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x04, 0x04, 0x05, 0x06, 0x04, 0x04, 0x04, 0x04, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*广912*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x45, 0x22, 0xFD, 0x02, 0x22, 0xFE, 0x22, 0x02, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x09, 0x0A, 0x0A, 0x0B, 0x0A, 0x0A,/*逛913*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x7C, 0x54, 0xF6, 0x5D, 0xD4, 0x7C, 0x00, 0x04, 0x07, 0x02, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x0A, 0x0B, 0x0C,/*瑰914*/},\n        {\n\n                0x40, 0x48, 0xFF, 0x48, 0x40, 0xFE, 0x02, 0xF2, 0x02, 0xFE, 0x00, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*规915*/},\n        {\n\n                0x20, 0x24, 0x24, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x24, 0x24, 0x20, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*圭916*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*硅917*/},\n        {\n\n                0xFC, 0x00, 0x00, 0xFF, 0x00, 0x02, 0x22, 0x22, 0x22, 0x22, 0xFE, 0x01, 0x08, 0x06, 0x01, 0x00,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*归918*/},\n        {\n\n                0x10, 0xF8, 0x54, 0x53, 0x52, 0xF2, 0x5A, 0x56, 0x50, 0xF0, 0x00, 0x00, 0x03, 0x01, 0x01, 0x01,\n                0x07, 0x09, 0x09, 0x09, 0x09, 0x0C,/*龟919*/},\n        {\n\n                0xF9, 0x02, 0x20, 0xA9, 0xA9, 0xFD, 0xA9, 0xA9, 0x21, 0x01, 0xFF, 0x0F, 0x00, 0x02, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x02, 0x08, 0x0F,/*闺920*/},\n        {\n\n                0x74, 0x4C, 0xF7, 0x44, 0x44, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0x00, 0x02, 0x02, 0x0F, 0x01, 0x09,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*轨921*/},\n        {\n\n                0x00, 0x7C, 0x54, 0x54, 0xD6, 0x7D, 0x54, 0x54, 0xD4, 0x7C, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x07, 0x0A, 0x0B, 0x0A, 0x0B, 0x0C,/*鬼922*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x08, 0xF4, 0x13, 0xD2, 0x52, 0x5A, 0xD6, 0x10, 0x00, 0x07, 0x02, 0x08, 0x07,\n                0x00, 0x07, 0x08, 0x09, 0x09, 0x0C,/*诡923*/},\n        {\n\n                0x20, 0x15, 0x29, 0x25, 0x23, 0xE0, 0x20, 0x23, 0x2C, 0x12, 0x28, 0x00, 0x09, 0x09, 0x05, 0x03,\n                0x01, 0x01, 0x03, 0x05, 0x09, 0x00,/*癸924*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*桂925*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x09,/*柜926*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x08, 0xF4, 0x13, 0xD2, 0x5A, 0x56, 0xD0, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x07, 0x00, 0x07, 0x08, 0x09, 0x0D,/*跪927*/},\n        {\n\n                0x20, 0xAE, 0xAA, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xAA, 0xAE, 0x20, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*贵928*/},\n        {\n\n                0x48, 0x54, 0xD2, 0x51, 0x52, 0x44, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x06, 0x05, 0x04, 0x05,\n                0x0E, 0x00, 0x01, 0x08, 0x08, 0x0F,/*刽929*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x00, 0xDF, 0x95, 0x15, 0xD5, 0x15, 0x9F, 0x01, 0x01, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x00, 0x07, 0x09, 0x0C,/*辊930*/},\n        {\n\n                0x22, 0x44, 0x00, 0x4A, 0x66, 0xD2, 0x4A, 0xC3, 0x52, 0x66, 0xCA, 0x04, 0x02, 0x04, 0x02, 0x0F,\n                0x08, 0x04, 0x01, 0x02, 0x05, 0x08,/*滚931*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xDF, 0x95, 0x15, 0xD5, 0x15, 0x9F, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x00, 0x07, 0x09, 0x0C,/*棍932*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0xE0, 0x2F, 0x29, 0xF9, 0x29, 0x2F, 0xE0, 0x00, 0x0F, 0x04, 0x02, 0x0F,\n                0x02, 0x01, 0x00, 0x01, 0x0A, 0x0F,/*锅933*/},\n        {\n\n                0x02, 0xBA, 0xAA, 0xAB, 0xAA, 0x3A, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x02, 0x02, 0x0A, 0x0E, 0x03,\n                0x02, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郭934*/},\n        {\n\n                0xFF, 0x01, 0x25, 0x25, 0x25, 0xFD, 0x25, 0x65, 0xA5, 0x01, 0xFF, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*国935*/},\n        {\n\n                0x80, 0xBE, 0xAA, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xAA, 0xBE, 0x80, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*果936*/},\n        {\n\n                0x82, 0xBE, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAA, 0xBE, 0x82, 0x08, 0x0A, 0x05, 0x0C, 0x0A,\n                0x01, 0x02, 0x04, 0x05, 0x0A, 0x08,/*裹937*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x08, 0x28, 0xC8, 0x08, 0x08, 0xFF, 0x08, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x08, 0x08, 0x0A, 0x0A, 0x0B, 0x08,/*过938*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x10, 0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0x10, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*哈939*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xA9, 0xEF, 0x18, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x00, 0x09, 0x04, 0x02, 0x05, 0x08,/*骸940*/},\n        {\n\n                0x82, 0x82, 0xF2, 0x4E, 0x00, 0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x04, 0x02, 0x05, 0x08,/*孩941*/},\n        {\n\n                0x11, 0x22, 0x48, 0xC4, 0x7B, 0x4A, 0x6A, 0x4A, 0x4A, 0xFA, 0x42, 0x04, 0x02, 0x00, 0x03, 0x02,\n                0x02, 0x03, 0x0A, 0x0A, 0x07, 0x02,/*海942*/},\n        {\n\n                0x44, 0xD2, 0x55, 0x75, 0xD5, 0x55, 0x55, 0x15, 0xF5, 0x01, 0x00, 0x05, 0x05, 0x0B, 0x09, 0x04,\n                0x02, 0x05, 0x08, 0x03, 0x04, 0x0E,/*氦943*/},\n        {\n\n                0x04, 0x24, 0x34, 0xAC, 0xA5, 0x66, 0x24, 0x94, 0x44, 0x04, 0x04, 0x08, 0x09, 0x09, 0x04, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x00,/*亥944*/},\n        {\n\n                0x86, 0xAA, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAA, 0xAA, 0x86, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*害945*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x09, 0x09, 0x04, 0x02, 0x05, 0x08,/*骇946*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x04, 0xFF, 0x44, 0x44, 0xFF, 0x04, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*酣947*/},\n        {\n\n                0x04, 0xFD, 0x55, 0x57, 0xFC, 0x94, 0x08, 0xB7, 0x44, 0xBC, 0x04, 0x09, 0x05, 0x01, 0x05, 0x0B,\n                0x0C, 0x09, 0x0C, 0x00, 0x04, 0x09,/*憨948*/},\n        {\n\n                0x04, 0xFF, 0x44, 0x44, 0xFF, 0x04, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0F, 0x04, 0x04, 0x0F,\n                0x00, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邯949*/},\n        {\n\n                0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x44, 0x54, 0xFF, 0x54, 0x54, 0xC4, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*韩950*/},\n        {\n\n                0x10, 0x10, 0x28, 0x24, 0x2A, 0x31, 0xA2, 0x64, 0x08, 0x10, 0x10, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x00,/*含951*/},\n        {\n\n                0x11, 0x22, 0xF8, 0x01, 0x11, 0xA1, 0xF9, 0xA5, 0x13, 0x00, 0xF8, 0x04, 0x02, 0x0F, 0x08, 0x09,\n                0x0C, 0x0F, 0x08, 0x09, 0x08, 0x0F,/*涵952*/},\n        {\n\n                0x86, 0xAA, 0xAA, 0xFE, 0xAA, 0xAB, 0xAA, 0xFE, 0xAA, 0xAA, 0x86, 0x04, 0x02, 0x01, 0x04, 0x04,\n                0x09, 0x0A, 0x00, 0x01, 0x02, 0x04,/*寒953*/},\n        {\n\n                0xFC, 0x01, 0x89, 0x51, 0x01, 0xF9, 0x05, 0x53, 0x89, 0x00, 0xFC, 0x0F, 0x08, 0x08, 0x08, 0x0A,\n                0x0B, 0x08, 0x08, 0x08, 0x08, 0x0F,/*函954*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFC, 0x54, 0xD4, 0x04, 0xFF, 0x84, 0x65, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x02, 0x0B, 0x04, 0x03, 0x05, 0x0E,/*喊955*/},\n        {\n\n                0x06, 0x12, 0x2A, 0x26, 0x22, 0xE2, 0x22, 0x26, 0x2A, 0x12, 0x06, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*罕956*/},\n        {\n\n                0xFA, 0xAF, 0xFA, 0x48, 0x94, 0xF2, 0x01, 0x52, 0x94, 0xF8, 0x08, 0x02, 0x0F, 0x02, 0x02, 0x09,\n                0x0F, 0x00, 0x02, 0x09, 0x0F, 0x00,/*翰957*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0xAA, 0xEA, 0x82, 0x7F, 0xA2, 0xDB, 0x08, 0x0F, 0x00, 0x02, 0x09,\n                0x04, 0x09, 0x0A, 0x08, 0x04, 0x09,/*撼958*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x5F, 0x55, 0xD5, 0x55, 0x5F, 0x00, 0x00, 0x08, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*捍959*/},\n        {\n\n                0x00, 0x5F, 0x55, 0x55, 0x55, 0xD5, 0x55, 0x55, 0x55, 0x5F, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*旱960*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xFE, 0xAA, 0xEA, 0x82, 0x7F, 0xA2, 0xDB, 0x00, 0x00, 0x0F, 0x02, 0x09,\n                0x04, 0x09, 0x0A, 0x08, 0x04, 0x09,/*憾961*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0x5F, 0x55, 0xD5, 0x55, 0x5F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*悍962*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0x5F, 0x55, 0xD5, 0x55, 0x5F, 0x00, 0x08, 0x06, 0x01, 0x02, 0x05,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*焊963*/},\n        {\n\n                0x11, 0x22, 0x40, 0x42, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x42, 0x40, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x00, 0x0F, 0x00, 0x00, 0x00, 0x00,/*汗964*/},\n        {\n\n                0x11, 0x22, 0x00, 0x02, 0x3E, 0xC2, 0x02, 0x82, 0x62, 0x1E, 0x00, 0x04, 0x02, 0x09, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*汉965*/},\n        {\n\n                0x44, 0x44, 0xA4, 0x94, 0xEC, 0x87, 0x8C, 0x94, 0xA4, 0x44, 0x44, 0x00, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x08, 0x08, 0x07, 0x00, 0x00,/*夯966*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x04, 0xE4, 0x25, 0x26, 0xE4, 0x04, 0x04, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*杭967*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x04, 0xE4, 0x25, 0xE6, 0x04, 0x04, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*航968*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x62, 0xBA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBA, 0x62, 0x02, 0x03, 0x01, 0x0A, 0x0A,\n                0x05, 0x0B, 0x0E, 0x02, 0x04, 0x0A,/*壕969*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x62, 0xBA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBA, 0x62, 0x03, 0x01, 0x03, 0x0A, 0x0A,\n                0x05, 0x0B, 0x0E, 0x02, 0x04, 0x0A,/*嚎970*/},\n        {\n\n                0x62, 0xA2, 0xBA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBA, 0xA2, 0x62, 0x00, 0x0A, 0x0A, 0x09, 0x05,\n                0x0A, 0x0C, 0x02, 0x04, 0x0A, 0x08,/*豪971*/},\n        {\n\n                0x62, 0x22, 0xBA, 0xAA, 0xAA, 0xAB, 0x6A, 0x6A, 0x3A, 0x22, 0x62, 0x00, 0x08, 0x0A, 0x0A, 0x0A,\n                0x07, 0x0D, 0x0D, 0x09, 0x08, 0x0C,/*毫972*/},\n        {\n\n                0x20, 0xA4, 0xE4, 0x3F, 0xE4, 0xA4, 0x20, 0xFE, 0x02, 0x32, 0xCE, 0x09, 0x04, 0x03, 0x08, 0x0F,\n                0x00, 0x03, 0x0F, 0x02, 0x02, 0x01,/*郝973*/},\n        {\n\n                0x88, 0x78, 0x0F, 0x88, 0x78, 0x42, 0x42, 0xF2, 0x4A, 0x46, 0x40, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x00,/*好974*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x44, 0x92, 0x92, 0xFE, 0x49, 0x49, 0x40, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*耗975*/},\n        {\n\n                0x20, 0x20, 0xAF, 0x69, 0x29, 0x29, 0x29, 0x29, 0x2F, 0x20, 0x20, 0x00, 0x00, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*号976*/},\n        {\n\n                0x22, 0x44, 0x00, 0x28, 0xA6, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0x20, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*浩977*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xF2, 0x12, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x03, 0x01, 0x03, 0x00, 0x03,\n                0x01, 0x01, 0x09, 0x08, 0x0F, 0x00,/*呵978*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x80, 0x5F, 0x75, 0x55, 0xD5, 0x55, 0x5F, 0xC0, 0x03, 0x01, 0x03, 0x00, 0x06,\n                0x04, 0x05, 0x04, 0x01, 0x08, 0x0F,/*喝979*/},\n        {\n\n                0x42, 0xE2, 0x1A, 0x07, 0xEA, 0x2A, 0x2A, 0xEF, 0x0A, 0xFA, 0x0A, 0x00, 0x0F, 0x00, 0x00, 0x03,\n                0x01, 0x01, 0x09, 0x08, 0x0F, 0x00,/*荷980*/},\n        {\n\n                0x4A, 0x92, 0x02, 0xD7, 0x52, 0x52, 0x52, 0xD7, 0x12, 0xF2, 0x12, 0x08, 0x04, 0x00, 0x07, 0x02,\n                0x02, 0x02, 0x0B, 0x08, 0x0F, 0x00,/*菏981*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x44, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x09, 0x04, 0x02, 0x03, 0x04, 0x08,/*核982*/},\n        {\n\n                0x10, 0x10, 0x12, 0xD2, 0x32, 0xFE, 0x31, 0xD1, 0x11, 0x10, 0x10, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x04,/*禾983*/},\n        {\n\n                0x10, 0x92, 0x52, 0xFE, 0x51, 0x90, 0xFC, 0x04, 0x04, 0x04, 0xFC, 0x01, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x07, 0x02, 0x02, 0x02, 0x07,/*和984*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xF2, 0x12, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x00, 0x0F, 0x00, 0x00, 0x03,\n                0x01, 0x01, 0x09, 0x08, 0x0F, 0x00,/*何985*/},\n        {\n\n                0x10, 0x90, 0xA8, 0xA4, 0xA2, 0xA1, 0xA2, 0xA4, 0xA8, 0x90, 0x10, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*合986*/},\n        {\n\n                0x08, 0x08, 0xE4, 0xAC, 0xAA, 0xA9, 0xAA, 0xAC, 0xE4, 0x08, 0x08, 0x08, 0x0E, 0x0A, 0x0A, 0x0E,\n                0x0A, 0x0E, 0x0A, 0x0A, 0x0E, 0x08,/*盒987*/},\n        {\n\n                0xA4, 0xAA, 0x55, 0xE8, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*貉988*/},\n        {\n\n                0xF9, 0x02, 0x08, 0x69, 0xD9, 0x4B, 0x2D, 0x89, 0x49, 0x01, 0xFF, 0x0F, 0x00, 0x05, 0x05, 0x02,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x0F,/*阂989*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xF2, 0x12, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x04, 0x02, 0x01, 0x00, 0x03,\n                0x01, 0x01, 0x09, 0x08, 0x0F, 0x00,/*河990*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFF, 0x09, 0xE9, 0x3F, 0x29, 0xE9, 0x09, 0xFF, 0x04, 0x02, 0x00, 0x0F, 0x04,\n                0x05, 0x05, 0x05, 0x05, 0x04, 0x0F,/*涸991*/},\n        {\n\n                0xA4, 0xE4, 0x3F, 0xE4, 0xA4, 0x00, 0xA4, 0xE4, 0x3F, 0xE4, 0x24, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x01, 0x08, 0x07, 0x08, 0x0F, 0x01,/*赫992*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0x9F, 0x75, 0xD5, 0x55, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x06, 0x05, 0x04, 0x0D, 0x08, 0x07,/*褐993*/},\n        {\n\n                0x26, 0xFA, 0x56, 0xFB, 0x52, 0x56, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x00, 0x0F, 0x05, 0x07, 0x05,\n                0x05, 0x00, 0x02, 0x0A, 0x0A, 0x07,/*鹤994*/},\n        {\n\n                0x12, 0xCA, 0x47, 0x52, 0x52, 0xCE, 0x40, 0x5E, 0x52, 0xD2, 0x1E, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贺995*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x5F, 0x55, 0x51, 0xFF, 0x51, 0x55, 0x5F, 0x03, 0x01, 0x03, 0x00, 0x0D,\n                0x01, 0x0D, 0x01, 0x0D, 0x01, 0x0D,/*嘿996*/},\n        {\n\n                0x00, 0x5F, 0x51, 0x55, 0x51, 0xFF, 0x51, 0x55, 0x51, 0x5F, 0x00, 0x09, 0x05, 0x01, 0x05, 0x09,\n                0x01, 0x05, 0x09, 0x01, 0x05, 0x09,/*黑997*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xFA, 0xAA, 0xAB, 0xAA, 0xAA, 0xFA, 0x02, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*痕998*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*很999*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x01, 0x08, 0x08, 0x07, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*狠1000*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*恨1001*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x02, 0xBA, 0xAA, 0xAA, 0xAB, 0xAA, 0xBA, 0x02, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x00, 0x08, 0x0E, 0x01, 0x00, 0x00,/*哼1002*/},\n        {\n\n                0x02, 0x82, 0xBA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBA, 0x82, 0x02, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0E, 0x02, 0x01, 0x01, 0x00, 0x00,/*亨1003*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0xEA, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xEA, 0x00, 0x00, 0x0F, 0x00, 0x0B,\n                0x06, 0x02, 0x03, 0x02, 0x06, 0x0B,/*横1004*/},\n        {\n\n                0x24, 0xF2, 0x09, 0xFC, 0xAB, 0xFA, 0xAE, 0xF8, 0x12, 0xF2, 0x12, 0x00, 0x0F, 0x00, 0x0A, 0x06,\n                0x03, 0x06, 0x0A, 0x08, 0x0F, 0x00,/*衡1005*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x12, 0xFA, 0x4A, 0x4A, 0x4A, 0xFA, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*恒1006*/},\n        {\n\n                0x20, 0xA2, 0xAA, 0xAE, 0xAB, 0x7E, 0xAA, 0xAA, 0xAA, 0xA2, 0x20, 0x00, 0x08, 0x0A, 0x04, 0x0B,\n                0x00, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*轰1007*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x80, 0x88, 0xFF, 0x88, 0x88, 0xFF, 0x88, 0x80, 0x03, 0x01, 0x03, 0x08, 0x04,\n                0x02, 0x00, 0x00, 0x02, 0x04, 0x08,/*哄1008*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x84, 0x88, 0xFF, 0x88, 0xFF, 0x88, 0x80, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x04, 0x02, 0x00, 0x02, 0x04, 0x08,/*烘1009*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x04, 0x04, 0x03, 0x02, 0x0B,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*虹1010*/},\n        {\n\n                0x22, 0x44, 0x02, 0xFE, 0x02, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x04, 0x02, 0x04, 0x07, 0x02,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸿1011*/},\n        {\n\n                0x10, 0x21, 0x02, 0x80, 0x88, 0xFF, 0x88, 0x88, 0xFF, 0x88, 0x80, 0x04, 0x02, 0x01, 0x08, 0x04,\n                0x02, 0x00, 0x00, 0x02, 0x04, 0x08,/*洪1012*/},\n        {\n\n                0x2C, 0x24, 0x24, 0xE4, 0x3D, 0x26, 0xA4, 0x24, 0x24, 0x24, 0x2C, 0x08, 0x04, 0x03, 0x08, 0x0C,\n                0x0A, 0x09, 0x08, 0x0A, 0x0C, 0x08,/*宏1013*/},\n        {\n\n                0xF2, 0x92, 0x92, 0x9E, 0x00, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x07, 0x00,\n                0x06, 0x05, 0x04, 0x04, 0x05, 0x0E,/*弘1014*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*红1015*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x10, 0xFC, 0x03, 0x48, 0x3A, 0xEA, 0x2E, 0x28, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x09, 0x05, 0x03, 0x05, 0x09,/*喉1016*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x48, 0x3A, 0x2A, 0xEA, 0x2E, 0x28, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*侯1017*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x10, 0xFC, 0x03, 0x48, 0x3A, 0xEA, 0x2E, 0x28, 0x08, 0x08, 0x07, 0x00, 0x0F,\n                0x00, 0x09, 0x05, 0x03, 0x05, 0x09,/*猴1018*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x80, 0x82, 0xFA, 0x26, 0x10, 0xFF, 0x00, 0x00, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x07, 0x08, 0x0E,/*吼1019*/},\n        {\n\n                0x00, 0xFF, 0x01, 0x5F, 0x55, 0x55, 0x55, 0xD5, 0xD5, 0x5F, 0x01, 0x08, 0x07, 0x02, 0x02, 0x02,\n                0x0A, 0x0F, 0x02, 0x02, 0x02, 0x02,/*厚1020*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xFC, 0x48, 0x3A, 0x2A, 0xEA, 0x2E, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x03,\n                0x08, 0x09, 0x05, 0x03, 0x05, 0x09,/*候1021*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x12, 0x92, 0x92, 0x92, 0x91, 0x91, 0x91, 0x90, 0x08, 0x06, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*后1022*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x4A, 0x52, 0x42, 0xFE, 0x41, 0x51, 0x49, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*呼1023*/},\n        {\n\n                0x40, 0x4A, 0x52, 0x42, 0x42, 0xFE, 0x41, 0x41, 0x51, 0x49, 0x40, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*乎1024*/},\n        {\n\n                0x08, 0x44, 0x23, 0x12, 0x4E, 0x22, 0x12, 0x4E, 0x42, 0x42, 0x3E, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*忽1025*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xE4, 0x3F, 0xE4, 0x00, 0xFE, 0x92, 0xFE, 0x04, 0x07, 0x02, 0x00, 0x07,\n                0x02, 0x03, 0x08, 0x07, 0x08, 0x0F,/*瑚1026*/},\n        {\n\n                0x62, 0x2A, 0x2A, 0x2A, 0xAA, 0x2F, 0xAA, 0x2A, 0x2A, 0x2A, 0x62, 0x08, 0x09, 0x0A, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0A, 0x09, 0x08,/*壶1027*/},\n        {\n\n                0xA2, 0xA2, 0xFA, 0xA7, 0xA2, 0x02, 0xF2, 0x57, 0x52, 0x52, 0xF2, 0x0F, 0x04, 0x04, 0x04, 0x07,\n                0x08, 0x07, 0x01, 0x01, 0x09, 0x0F,/*葫1028*/},\n        {\n\n                0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x07, 0x02, 0x02, 0x02, 0x0B,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x0F,/*胡1029*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xE4, 0x3F, 0xE4, 0x00, 0xFE, 0x92, 0xFE, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x02, 0x03, 0x08, 0x07, 0x08, 0x0F,/*蝴1030*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x01, 0x00, 0x08, 0x08, 0x07, 0x08, 0x07,\n                0x00, 0x0F, 0x0A, 0x0C, 0x03, 0x04,/*狐1031*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0xE4, 0x3F, 0xE4, 0x00, 0xFF, 0x89, 0xFF, 0x01, 0x00, 0x0F, 0x00, 0x07,\n                0x02, 0x0B, 0x04, 0x03, 0x08, 0x0F,/*糊1032*/},\n        {\n\n                0x22, 0x44, 0x00, 0xE4, 0x3F, 0xE4, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x04, 0x02, 0x00, 0x07, 0x02,\n                0x03, 0x08, 0x07, 0x00, 0x08, 0x0F,/*湖1033*/},\n        {\n\n                0xF2, 0x92, 0x9E, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x01, 0x00, 0x08, 0x08, 0x07, 0x08, 0x07,\n                0x00, 0x0F, 0x0A, 0x0C, 0x03, 0x04,/*弧1034*/},\n        {\n\n                0x00, 0xF8, 0x48, 0x48, 0x48, 0x7F, 0xAA, 0xAA, 0xAA, 0x8A, 0xD8, 0x08, 0x07, 0x08, 0x08, 0x06,\n                0x02, 0x02, 0x02, 0x06, 0x08, 0x0C,/*虎1035*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xF8, 0x48, 0x48, 0x7F, 0xAA, 0xAA, 0xD8, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x08, 0x07, 0x01, 0x07, 0x08, 0x0C,/*唬1036*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFC, 0x44, 0x45, 0x46, 0x44, 0xFC, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*护1037*/},\n        {\n\n                0x02, 0xC2, 0x3E, 0x12, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x02, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x0F, 0x08, 0x08, 0x08,/*互1038*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0xFC, 0x44, 0x45, 0x46, 0x44, 0x44, 0xFC, 0x04, 0x02, 0x09, 0x06, 0x01,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*沪1039*/},\n        {\n\n                0x00, 0x00, 0xFC, 0x44, 0x44, 0x45, 0x46, 0x44, 0x44, 0x44, 0xFC, 0x08, 0x06, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*户1040*/},\n        {\n\n                0x82, 0x42, 0xE2, 0x17, 0x02, 0x02, 0xF2, 0x87, 0x42, 0x22, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x07, 0x08, 0x08, 0x08, 0x0E,/*花1041*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0x04, 0x7E, 0x21, 0x90, 0x3F, 0x44, 0x72, 0x03, 0x01, 0x03, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*哗1042*/},\n        {\n\n                0x10, 0x08, 0x7C, 0x03, 0x10, 0x90, 0x3F, 0x48, 0x44, 0x42, 0x70, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*华1043*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x30, 0xDF, 0x55, 0x55, 0x5D, 0x51, 0xDF, 0x30, 0x08, 0x08, 0x07, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x0D, 0x0F, 0x00,/*猾1044*/},\n        {\n\n                0x11, 0x22, 0x30, 0xDF, 0x55, 0x55, 0x5D, 0x51, 0x51, 0xDF, 0x30, 0x04, 0x02, 0x00, 0x0F, 0x05,\n                0x05, 0x05, 0x05, 0x0D, 0x0F, 0x00,/*滑1045*/},\n        {\n\n                0xFD, 0x01, 0xFD, 0x25, 0x25, 0xFD, 0x25, 0x25, 0xFD, 0x01, 0xFD, 0x07, 0x04, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x04, 0x0F,/*画1046*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x08, 0x89, 0x6A, 0x08, 0x00, 0xFC, 0x00, 0xFF, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x04, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*划1047*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x00, 0x80, 0xFF, 0x20, 0x10, 0x08, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*化1048*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x10, 0x92, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x91, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*话1049*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFC, 0x54, 0xF6, 0x5D, 0xD4, 0x7C, 0x00, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x0A, 0x0B, 0x0C,/*槐1050*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0xFE, 0x02, 0xF2, 0x92, 0xF2, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*徊1051*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0x82, 0x42, 0xF2, 0x0E, 0x22, 0xC2, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*怀1052*/},\n        {\n\n                0x10, 0x21, 0x02, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x04, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*淮1053*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x80, 0x42, 0x22, 0xFA, 0x06, 0x22, 0xC2, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*坏1054*/},\n        {\n\n                0x0A, 0x32, 0xC2, 0x32, 0x1E, 0x08, 0x07, 0xE4, 0x04, 0x14, 0x0C, 0x04, 0x03, 0x00, 0x03, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*欢1055*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x80, 0x42, 0x22, 0xFA, 0x06, 0x22, 0xC2, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*环1056*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x02, 0xFA, 0x4A, 0x4A, 0x4A, 0xFA, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*桓1057*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x42, 0x22, 0x12, 0xFA, 0x06, 0x12, 0x62, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x08, 0x08, 0x0B, 0x08, 0x08, 0x08,/*还1058*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x56, 0x5A, 0xD6, 0x7A, 0x52, 0x59, 0x55, 0x04, 0x04, 0x02, 0x04, 0x0A,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*缓1059*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x08, 0xF4, 0x13, 0xFA, 0x16, 0xF0, 0x00, 0x00, 0x08, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*换1060*/},\n        {\n\n                0x00, 0xE0, 0xAE, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAE, 0xE0, 0x00, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*患1061*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0xF4, 0x13, 0xF2, 0x1A, 0x16, 0xF0, 0x00, 0x03, 0x01, 0x03, 0x09, 0x05,\n                0x03, 0x01, 0x03, 0x05, 0x09, 0x09,/*唤1062*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x22, 0xF2, 0x2E, 0xEB, 0x2A, 0x3A, 0xE2, 0x02, 0x09, 0x04, 0x0B, 0x09, 0x05,\n                0x03, 0x01, 0x03, 0x05, 0x09, 0x09,/*痪1063*/},\n        {\n\n                0x48, 0x2A, 0x9B, 0xAA, 0x6E, 0xAB, 0x2A, 0x2A, 0x9B, 0x2A, 0x48, 0x00, 0x0A, 0x0A, 0x0A, 0x05,\n                0x0A, 0x0F, 0x01, 0x02, 0x04, 0x00,/*豢1064*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x08, 0xF4, 0x13, 0xFA, 0x16, 0xF0, 0x00, 0x08, 0x06, 0x01, 0x06, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*焕1065*/},\n        {\n\n                0x22, 0x44, 0x08, 0xF4, 0x13, 0x12, 0xF2, 0x1A, 0x16, 0xF0, 0x00, 0x04, 0x02, 0x09, 0x09, 0x05,\n                0x03, 0x01, 0x03, 0x05, 0x09, 0x09,/*涣1066*/},\n        {\n\n                0x06, 0xFA, 0x2A, 0x2A, 0x2A, 0x3B, 0x2A, 0x2A, 0x2A, 0xEA, 0x06, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*宦1067*/},\n        {\n\n                0x30, 0x2C, 0xA3, 0x60, 0x18, 0x02, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x03, 0x02, 0x02, 0x03,\n                0x06, 0x00, 0x00, 0x08, 0x08, 0x07,/*幻1068*/},\n        {\n\n                0x12, 0x12, 0x77, 0x52, 0x52, 0x56, 0x5A, 0x52, 0x57, 0x52, 0x12, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x07, 0x08, 0x0C,/*荒1069*/},\n        {\n\n                0x30, 0xFF, 0x08, 0x12, 0x72, 0x57, 0x5A, 0x52, 0x57, 0x52, 0x12, 0x00, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0C,/*慌1070*/},\n        {\n\n                0x08, 0xEA, 0xAA, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xAA, 0xEA, 0x08, 0x00, 0x0B, 0x06, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x06, 0x0B, 0x00,/*黄1071*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x08, 0xEA, 0xAF, 0xFA, 0xAF, 0xEA, 0x08, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x0B, 0x06, 0x03, 0x06, 0x0B, 0x00,/*磺1072*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xBE, 0xAB, 0xAA, 0xAA, 0xBE, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*蝗1073*/},\n        {\n\n                0x24, 0xEB, 0xAA, 0xBE, 0xAA, 0xEC, 0xAB, 0xBE, 0xAA, 0xEA, 0x22, 0x00, 0x0B, 0x06, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x06, 0x0B, 0x00,/*簧1074*/},\n        {\n\n                0x00, 0xBE, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xAA, 0xBE, 0x00, 0x08, 0x08, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x08, 0x08,/*皇1075*/},\n        {\n\n                0x00, 0xFF, 0x41, 0x7D, 0x55, 0xD7, 0x55, 0x7D, 0x41, 0xFF, 0x00, 0x08, 0x07, 0x00, 0x05, 0x05,\n                0x07, 0x05, 0x05, 0x00, 0x07, 0x0C,/*凰1076*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x90, 0xBE, 0xAB, 0xAA, 0xAA, 0xBE, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*惶1077*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x10, 0x88, 0xBE, 0xAB, 0xAA, 0xAA, 0xBE, 0x80, 0x08, 0x06, 0x01, 0x02, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*煌1078*/},\n        {\n\n                0x00, 0x5F, 0x95, 0x15, 0x15, 0xF5, 0x15, 0x15, 0x95, 0x5F, 0x00, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x07, 0x09, 0x09, 0x09, 0x0D,/*晃1079*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x5F, 0x95, 0xF5, 0x95, 0x5F, 0x00, 0x03, 0x00, 0x0F, 0x02, 0x0B,\n                0x05, 0x03, 0x01, 0x07, 0x09, 0x0D,/*幌1080*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x24, 0x28, 0xE0, 0x3F, 0xE0, 0x28, 0x24, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*恍1081*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x12, 0x72, 0x57, 0x5A, 0x52, 0x57, 0x52, 0x12, 0x00, 0x07, 0x02, 0x08, 0x07,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0C,/*谎1082*/},\n        {\n\n                0x04, 0x04, 0xFF, 0x04, 0xE4, 0x04, 0xF4, 0x04, 0x84, 0x64, 0x04, 0x04, 0x03, 0x08, 0x09, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*灰1083*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x16, 0xD2, 0xB2, 0xDA, 0x92, 0x92, 0x06, 0x08, 0x0F, 0x00, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*挥1084*/},\n        {\n\n                0x24, 0xE8, 0x3F, 0xE8, 0x24, 0x0B, 0x69, 0x5F, 0xE9, 0x49, 0x4B, 0x08, 0x07, 0x00, 0x0F, 0x04,\n                0x02, 0x02, 0x02, 0x0F, 0x02, 0x02,/*辉1085*/},\n        {\n\n                0x24, 0xF2, 0x09, 0xB6, 0xEC, 0xA7, 0x94, 0x16, 0xE8, 0x07, 0xFC, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x0F, 0x02, 0x0C, 0x04, 0x03, 0x0C,/*徽1086*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xC4, 0x3F, 0xC4, 0x04, 0xF4, 0x44, 0x24, 0x00, 0x00, 0x0F, 0x04, 0x03,\n                0x08, 0x04, 0x02, 0x01, 0x06, 0x08,/*恢1087*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xFE, 0x02, 0xF2, 0x92, 0xF2, 0x02, 0xFE, 0x04, 0x04, 0x03, 0x02, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*蛔1088*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0xF2, 0x92, 0x92, 0xF2, 0x02, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*回1089*/},\n        {\n\n                0xBE, 0xA9, 0xA0, 0xAA, 0xBE, 0x10, 0xCE, 0x42, 0x42, 0xDE, 0x10, 0x08, 0x08, 0x0F, 0x04, 0x04,\n                0x08, 0x05, 0x02, 0x02, 0x05, 0x08,/*毁1090*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x48, 0xC4, 0x7B, 0x4A, 0x6A, 0x4A, 0xFA, 0x42, 0x00, 0x00, 0x0F, 0x00, 0x03,\n                0x02, 0x02, 0x0B, 0x0A, 0x07, 0x02,/*悔1091*/},\n        {\n\n                0x2A, 0xAA, 0xBF, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA, 0xBF, 0xEA, 0x2A, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*慧1092*/},\n        {\n\n                0x84, 0x84, 0xF4, 0x84, 0x84, 0xBF, 0x84, 0x84, 0xF4, 0x84, 0x84, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,/*卉1093*/},\n        {\n\n                0x82, 0x82, 0xFA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xFA, 0x82, 0xC2, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*惠1094*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x48, 0xC4, 0x7B, 0x4A, 0x6A, 0x4A, 0xFA, 0x42, 0x07, 0x02, 0x07, 0x00, 0x03,\n                0x02, 0x02, 0x0B, 0x0A, 0x07, 0x02,/*晦1095*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x24, 0xFC, 0x57, 0x54, 0x54, 0xF4, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x0F, 0x01, 0x01, 0x09, 0x0F,/*贿1096*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x8E, 0x48, 0xB8, 0x2F, 0x28, 0x28, 0xEE, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x04, 0x05, 0x02, 0x01, 0x00,/*秽1097*/},\n        {\n\n                0x90, 0x90, 0x88, 0x94, 0x92, 0x91, 0x92, 0x94, 0x88, 0x90, 0x90, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x04, 0x06, 0x0C, 0x00,/*会1098*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x88, 0x94, 0x92, 0x91, 0x92, 0x94, 0x88, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*烩1099*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFE, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0x02, 0x01, 0x0F, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*汇1100*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x44, 0x54, 0x54, 0xFF, 0x54, 0x54, 0xC4, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*讳1101*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x48, 0xC4, 0x7B, 0x4A, 0x6A, 0x4A, 0xFA, 0x42, 0x00, 0x07, 0x02, 0x00, 0x03,\n                0x02, 0x02, 0x0B, 0x0A, 0x07, 0x02,/*诲1102*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x88, 0x94, 0x92, 0x91, 0x92, 0x94, 0x88, 0x04, 0x04, 0x02, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*绘1103*/},\n        {\n\n                0x1A, 0x2A, 0xAA, 0xEF, 0xBA, 0xEA, 0xAA, 0xAF, 0xAA, 0x2A, 0x1A, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*荤1104*/},\n        {\n\n                0x00, 0x7E, 0xCA, 0xAA, 0x8A, 0x8A, 0x8E, 0x99, 0xA9, 0xC9, 0x68, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*昏1105*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xBE, 0xAA, 0xAA, 0x9E, 0xA9, 0x70, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*婚1106*/},\n        {\n\n                0x92, 0x72, 0x12, 0x00, 0x3E, 0xAA, 0x7B, 0x2E, 0xEA, 0x3E, 0x00, 0x03, 0x02, 0x07, 0x08, 0x06,\n                0x01, 0x07, 0x0B, 0x0A, 0x0B, 0x0C,/*魂1107*/},\n        {\n\n                0x11, 0x22, 0x00, 0x0B, 0x69, 0x59, 0x4F, 0xE9, 0x49, 0x49, 0x0B, 0x04, 0x02, 0x01, 0x02, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*浑1108*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0xDF, 0x15, 0x15, 0x15, 0xD5, 0x1F, 0x80, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x09, 0x05, 0x00, 0x07, 0x09, 0x0C,/*混1109*/},\n        {\n\n                0x86, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xA6, 0x91, 0x88, 0x91, 0x22, 0x00, 0x0E, 0x0A, 0x0B, 0x0A,\n                0x0E, 0x00, 0x0F, 0x04, 0x0F, 0x00,/*豁1110*/},\n        {\n\n                0x22, 0x44, 0x10, 0x92, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x91, 0x10, 0x04, 0x02, 0x01, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*活1111*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x20, 0x1C, 0x80, 0x7F, 0x80, 0x10, 0x0C, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*伙1112*/},\n        {\n\n                0x00, 0x20, 0x1C, 0x00, 0xC0, 0x3F, 0xC0, 0x00, 0x10, 0x0C, 0x00, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x03, 0x04, 0x08, 0x08,/*火1113*/},\n        {\n\n                0x4A, 0x52, 0x27, 0xD2, 0x4A, 0x42, 0x42, 0xF2, 0x47, 0x4A, 0x52, 0x02, 0x0A, 0x09, 0x07, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*获1114*/},\n        {\n\n                0x04, 0xF4, 0x94, 0x94, 0xF4, 0x04, 0xFF, 0x04, 0xC5, 0x36, 0x04, 0x04, 0x04, 0x04, 0x02, 0x0A,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x0F,/*或1115*/},\n        {\n\n                0x02, 0x3A, 0x2A, 0xAA, 0xBA, 0x02, 0xBF, 0x42, 0xA2, 0x1B, 0xC2, 0x09, 0x05, 0x01, 0x04, 0x0A,\n                0x0D, 0x08, 0x0C, 0x00, 0x05, 0x09,/*惑1116*/},\n        {\n\n                0x8C, 0x45, 0xED, 0xB5, 0xA5, 0xAF, 0xF5, 0xA5, 0xAD, 0xA5, 0x2C, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*霍1117*/},\n        {\n\n                0x08, 0xC4, 0x7E, 0x41, 0x50, 0xD0, 0x4F, 0x54, 0x52, 0xD1, 0x18, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*货1118*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0xE0, 0x2F, 0x29, 0xF9, 0x29, 0x2F, 0xE0, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x02, 0x01, 0x00, 0x01, 0x0A, 0x0F,/*祸1119*/},\n        {\n\n                0x20, 0xA4, 0x24, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x24, 0xA4, 0x20, 0x00, 0x07, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x0F, 0x00,/*击1120*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x02, 0xFE, 0x82, 0x02, 0x32, 0x2E, 0xE0, 0x02, 0x02, 0x01, 0x09, 0x06,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*圾1121*/},\n        {\n\n                0x82, 0x82, 0xFF, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xFF, 0x82, 0x82, 0x0A, 0x09, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x09, 0x0A,/*基1122*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*机1123*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x10, 0xDA, 0x56, 0xD3, 0x16, 0xFA, 0x07, 0x02, 0x03, 0x02, 0x07,\n                0x00, 0x07, 0x02, 0x03, 0x08, 0x0F,/*畸1124*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x8A, 0xB6, 0xD3, 0xD6, 0xDB, 0xCA, 0x6C, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*稽1125*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x00, 0xFE, 0x82, 0x82, 0x82, 0xFE, 0x00, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x00, 0x02, 0x04, 0x08,/*积1126*/},\n        {\n\n                0x0C, 0x0B, 0xFE, 0xAA, 0xAA, 0xAC, 0xAB, 0xAA, 0xFE, 0x0A, 0x0A, 0x02, 0x0A, 0x07, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x07, 0x0A, 0x02,/*箕1127*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0xFE, 0x02, 0xFE, 0x00, 0x00, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*肌1128*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x00, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x07, 0x02, 0x09, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*饥1129*/},\n        {\n\n                0x11, 0xF2, 0x80, 0x64, 0x04, 0xFC, 0x05, 0x06, 0xFC, 0x24, 0xC4, 0x08, 0x07, 0x08, 0x0A, 0x09,\n                0x08, 0x08, 0x0A, 0x0B, 0x08, 0x08,/*迹1130*/},\n        {\n\n                0x22, 0x44, 0x80, 0xBE, 0xEB, 0xBE, 0x10, 0xEC, 0x0B, 0xF8, 0x08, 0x04, 0x02, 0x08, 0x07, 0x0A,\n                0x0E, 0x08, 0x04, 0x03, 0x04, 0x08,/*激1131*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x07, 0x0A, 0x04, 0x03,\n                0x00, 0x00, 0x00, 0x07, 0x08, 0x0E,/*讥1132*/},\n        {\n\n                0x0A, 0x32, 0xC2, 0x3E, 0x00, 0x7E, 0x43, 0x4A, 0x52, 0x5E, 0xC0, 0x04, 0x03, 0x00, 0x07, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸡1133*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFE, 0x02, 0xF2, 0x1E, 0x12, 0xF2, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x08, 0x09, 0x0F, 0x09, 0x09,/*姬1134*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xA2, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xA2, 0x04, 0x04, 0x02, 0x00, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*绩1135*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0xF7, 0x55, 0x55, 0x55, 0xF7, 0x10, 0x04, 0x04, 0x02, 0x02, 0x04,\n                0x07, 0x05, 0x05, 0x05, 0x0F, 0x02,/*缉1136*/},\n        {\n\n                0x04, 0xA4, 0xA4, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0xA4, 0xA4, 0x04, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*吉1137*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x02, 0xFE, 0x82, 0x02, 0x32, 0x2E, 0xE0, 0x00, 0x00, 0x0F, 0x08, 0x06,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*极1138*/},\n        {\n\n                0x74, 0x14, 0xFF, 0x54, 0x74, 0x00, 0x74, 0x14, 0xFF, 0x54, 0x74, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x00, 0x02, 0x01, 0x0F, 0x01, 0x02,/*棘1139*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x10, 0xF7, 0x55, 0x55, 0x55, 0xF7, 0x10, 0x02, 0x02, 0x0F, 0x01, 0x04,\n                0x07, 0x05, 0x05, 0x05, 0x0F, 0x02,/*辑1140*/},\n        {\n\n                0x8A, 0xA9, 0xFD, 0xAB, 0x01, 0xAA, 0xBD, 0xA9, 0xBD, 0xAB, 0x21, 0x04, 0x02, 0x0F, 0x02, 0x04,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*籍1141*/},\n        {\n\n                0x08, 0x04, 0xFE, 0xAB, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAA, 0x82, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*集1142*/},\n        {\n\n                0x00, 0x02, 0xC2, 0x3E, 0x62, 0x82, 0x02, 0x32, 0x2A, 0xA6, 0x60, 0x08, 0x06, 0x01, 0x08, 0x08,\n                0x04, 0x05, 0x02, 0x05, 0x08, 0x08,/*及1143*/},\n        {\n\n                0x08, 0x84, 0xAB, 0xAA, 0xAA, 0xAA, 0xAA, 0xAE, 0xA8, 0xF8, 0x00, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*急1144*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x44, 0x35, 0x26, 0xE4, 0x24, 0x24, 0x04, 0x09, 0x04, 0x03, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*疾1145*/},\n        {\n\n                0x22, 0x44, 0x00, 0x02, 0xFE, 0x82, 0x02, 0x32, 0x2E, 0xE0, 0x00, 0x04, 0x02, 0x08, 0x06, 0x01,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*汲1146*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xAA, 0x2A, 0x3E, 0x00, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x02, 0x01,\n                0x06, 0x00, 0x0F, 0x00, 0x02, 0x03,/*即1147*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x90, 0xFC, 0x44, 0x3D, 0xE6, 0x24, 0x24, 0x08, 0x05, 0x02, 0x0D, 0x04,\n                0x03, 0x09, 0x05, 0x03, 0x05, 0x09,/*嫉1148*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x02, 0xFE, 0x82, 0x02, 0x32, 0x2E, 0xE0, 0x04, 0x04, 0x02, 0x0A, 0x06,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*级1149*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x44, 0xAC, 0x15, 0x16, 0xAC, 0x44, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*挤1150*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*几1151*/},\n        {\n\n                0x48, 0x25, 0xF2, 0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0xF2, 0x25, 0x48, 0x00, 0x00, 0x0F, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0F, 0x00, 0x00,/*脊1152*/},\n        {\n\n                0x00, 0xE2, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x3E, 0x00, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0F,/*己1153*/},\n        {\n\n                0x12, 0xEE, 0xAA, 0xEF, 0xAA, 0xBA, 0xE2, 0x07, 0xF2, 0x02, 0xFA, 0x08, 0x0B, 0x0A, 0x0B, 0x0A,\n                0x0A, 0x0B, 0x08, 0x03, 0x08, 0x0F,/*蓟1154*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x24, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x04, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*技1155*/},\n        {\n\n                0x0A, 0x0A, 0xFA, 0x5F, 0x50, 0xF0, 0x57, 0x5A, 0xFA, 0x09, 0x0C, 0x04, 0x05, 0x0D, 0x07, 0x05,\n                0x05, 0x05, 0x07, 0x0D, 0x05, 0x04,/*冀1156*/},\n        {\n\n                0x48, 0x48, 0x2A, 0x5A, 0x4A, 0x7E, 0xC9, 0x59, 0x29, 0x48, 0x48, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*季1157*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x24, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*伎1158*/},\n        {\n\n                0x44, 0xAA, 0x97, 0xAA, 0xA6, 0xA0, 0xA7, 0xAA, 0x92, 0xAA, 0x46, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*祭1159*/},\n        {\n\n                0x84, 0x94, 0x55, 0x26, 0x34, 0x4C, 0x84, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x08, 0x07, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x01, 0x08, 0x0F,/*剂1160*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x48, 0x2A, 0x5A, 0x7E, 0xD9, 0x29, 0x48, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x0A, 0x0F, 0x02, 0x02, 0x02,/*悸1161*/},\n        {\n\n                0x22, 0x44, 0x00, 0x44, 0x44, 0xAC, 0x15, 0x16, 0xAC, 0x44, 0x44, 0x04, 0x02, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x0F, 0x00, 0x00,/*济1162*/},\n        {\n\n                0x46, 0x4A, 0x6A, 0x5A, 0x4A, 0x4F, 0x4A, 0x5A, 0xEA, 0x4A, 0x46, 0x00, 0x07, 0x05, 0x05, 0x05,\n                0x07, 0x00, 0x08, 0x0F, 0x00, 0x00,/*寄1163*/},\n        {\n\n                0x46, 0x42, 0xFA, 0x52, 0x52, 0x03, 0xF2, 0x12, 0x12, 0xF2, 0x06, 0x02, 0x09, 0x0F, 0x01, 0x02,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*寂1164*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x20, 0x20, 0x20, 0xFF, 0x20, 0x20, 0x20, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*计1165*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0xE2, 0x22, 0x22, 0x22, 0x3E, 0x00, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*记1166*/},\n        {\n\n                0xFE, 0x2A, 0xAA, 0x3E, 0x00, 0x3A, 0x22, 0xFE, 0x22, 0x22, 0x20, 0x0F, 0x04, 0x02, 0x01, 0x0A,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*既1167*/},\n        {\n\n                0x00, 0x72, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x9E, 0xC0, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*忌1168*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x10, 0x92, 0x12, 0xF2, 0x12, 0x92, 0x10, 0x0F, 0x02, 0x02, 0x01, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*际1169*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x04, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*妓1170*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xFE, 0x24, 0xA8, 0xFF, 0xA8, 0x24, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x09, 0x08, 0x0F, 0x08, 0x09,/*继1171*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xE2, 0x22, 0x22, 0x22, 0x3E, 0x00, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*纪1172*/},\n        {\n\n                0x82, 0x8A, 0xBA, 0xEA, 0xAA, 0xAF, 0xAA, 0xEA, 0xBA, 0x8A, 0x82, 0x0A, 0x0A, 0x07, 0x02, 0x0A,\n                0x0E, 0x00, 0x0E, 0x0A, 0x0A, 0x0E,/*嘉1173*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0xFC, 0x04, 0xFC, 0x00, 0x0F, 0x08, 0x04, 0x03,\n                0x08, 0x0F, 0x00, 0x0F, 0x04, 0x0F,/*枷1174*/},\n        {\n\n                0x80, 0x84, 0x94, 0xA4, 0x84, 0xFF, 0x84, 0xA4, 0x94, 0x84, 0x80, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*夹1175*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*佳1176*/},\n        {\n\n                0x06, 0x4A, 0x4A, 0xAA, 0x5A, 0x2B, 0xCA, 0x8A, 0x4A, 0x2A, 0x06, 0x04, 0x05, 0x05, 0x02, 0x0A,\n                0x09, 0x07, 0x00, 0x01, 0x02, 0x02,/*家1177*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x00, 0xFC, 0x04, 0x04, 0xFC, 0x08, 0x06, 0x01, 0x08, 0x08,\n                0x07, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*加1178*/},\n        {\n\n                0x02, 0x12, 0x52, 0x97, 0x12, 0xFA, 0x12, 0x97, 0x52, 0x12, 0x02, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*荚1179*/},\n        {\n\n                0x94, 0xA4, 0xFF, 0xA4, 0x94, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颊1180*/},\n        {\n\n                0x1D, 0xD5, 0x55, 0x5F, 0x55, 0xD5, 0x55, 0x5F, 0x55, 0xD5, 0x1D, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贾1181*/},\n        {\n\n                0x00, 0xFF, 0x89, 0x89, 0x89, 0xFF, 0x89, 0x89, 0x89, 0xFF, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x01, 0x00,/*甲1182*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*钾1183*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xFE, 0x52, 0x5E, 0x00, 0xD2, 0x52, 0x52, 0xDE, 0x00, 0x0F, 0x00, 0x0F, 0x01,\n                0x01, 0x08, 0x05, 0x02, 0x06, 0x09,/*假1184*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x46, 0xAA, 0x5A, 0xAB, 0xCA, 0x4A, 0x26, 0x01, 0x00, 0x0F, 0x00, 0x05,\n                0x02, 0x09, 0x08, 0x07, 0x01, 0x02,/*稼1185*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x10, 0xE8, 0x04, 0x03, 0x04, 0xE8, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x0F, 0x00,/*价1186*/},\n        {\n\n                0xA2, 0x92, 0x8F, 0xA2, 0xA2, 0xDE, 0x80, 0xBE, 0xA2, 0xA2, 0xBE, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*架1187*/},\n        {\n\n                0x12, 0x4A, 0xC7, 0x52, 0x52, 0x4E, 0x40, 0x5E, 0xD2, 0x12, 0x1E, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x01, 0x09, 0x09, 0x07,/*驾1188*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x46, 0x2A, 0x9A, 0x6B, 0xCA, 0x4A, 0x26, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x05, 0x0A, 0x09, 0x07, 0x01, 0x02,/*嫁1189*/},\n        {\n\n                0x82, 0x62, 0x9E, 0x12, 0xF2, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,/*歼1190*/},\n        {\n\n                0x00, 0x9E, 0x80, 0x80, 0xBF, 0x90, 0x88, 0x87, 0x94, 0xA4, 0x04, 0x08, 0x0F, 0x08, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x08, 0x0F, 0x08,/*监1191*/},\n        {\n\n                0x3E, 0x00, 0x00, 0x7F, 0x00, 0xC6, 0x2A, 0x12, 0x2A, 0x46, 0x40, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*坚1192*/},\n        {\n\n                0x90, 0x88, 0x86, 0x80, 0x80, 0xDF, 0x80, 0x80, 0x82, 0x84, 0x98, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*尖1193*/},\n        {\n\n                0x04, 0x43, 0x46, 0x4A, 0xF2, 0x20, 0xAC, 0xB3, 0xA6, 0xAA, 0x82, 0x01, 0x09, 0x09, 0x09, 0x09,\n                0x07, 0x04, 0x0A, 0x09, 0x08, 0x0C,/*笺1194*/},\n        {\n\n                0x00, 0xF9, 0x02, 0xF8, 0x49, 0x49, 0x49, 0x49, 0xF9, 0x01, 0xFF, 0x00, 0x0F, 0x00, 0x03, 0x02,\n                0x02, 0x02, 0x02, 0x0B, 0x08, 0x0F,/*间1195*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAB, 0xAA, 0xFA, 0x02, 0xF3, 0x02, 0xFA, 0x02, 0x00, 0x0B, 0x00, 0x00, 0x0A,\n                0x03, 0x08, 0x01, 0x02, 0x0B, 0x00,/*煎1196*/},\n        {\n\n                0x44, 0x54, 0x55, 0x56, 0xFC, 0x54, 0xFC, 0x56, 0x55, 0xF4, 0x44, 0x08, 0x05, 0x03, 0x01, 0x0F,\n                0x01, 0x0F, 0x01, 0x03, 0x05, 0x08,/*兼1197*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xEA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xEE, 0x08, 0x07, 0x00, 0x0F, 0x02,\n                0x02, 0x02, 0x02, 0x02, 0x0A, 0x0F,/*肩1198*/},\n        {\n\n                0x0A, 0x32, 0xC2, 0x3E, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x04, 0x03, 0x00, 0x07, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*艰1199*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x40, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*奸1200*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xFC, 0x54, 0xD4, 0x04, 0xFF, 0x84, 0x65, 0x04, 0x04, 0x02, 0x08, 0x07,\n                0x02, 0x0B, 0x04, 0x03, 0x05, 0x0E,/*缄1201*/},\n        {\n\n                0x02, 0xF2, 0x92, 0x97, 0x92, 0xFA, 0x92, 0x97, 0x92, 0xF2, 0x02, 0x04, 0x04, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x06, 0x0C,/*茧1202*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*检1203*/},\n        {\n\n                0x02, 0xFA, 0x8A, 0xAA, 0xCA, 0xFF, 0xCA, 0xAA, 0x8A, 0xFA, 0x02, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*柬1204*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0xFC, 0x54, 0xD4, 0x04, 0xFF, 0x84, 0x65, 0x07, 0x02, 0x07, 0x08, 0x07,\n                0x02, 0x0B, 0x04, 0x03, 0x05, 0x0E,/*碱1205*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x00, 0x0F, 0x04, 0x0F, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*硷1206*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x14, 0x74, 0x5C, 0xF7, 0x44, 0x44, 0x44, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x03, 0x08, 0x0F, 0x00, 0x01, 0x06,/*拣1207*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*捡1208*/},\n        {\n\n                0x04, 0xCB, 0x12, 0xE6, 0xAA, 0xAC, 0xAB, 0xEA, 0x0E, 0xFA, 0x02, 0x00, 0x0F, 0x00, 0x03, 0x02,\n                0x02, 0x02, 0x0B, 0x08, 0x0F, 0x00,/*简1209*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*俭1210*/},\n        {\n\n                0x02, 0xFE, 0x2A, 0x2B, 0xAA, 0xFE, 0x02, 0x3B, 0x82, 0xFE, 0x02, 0x08, 0x0A, 0x0A, 0x06, 0x02,\n                0x02, 0x02, 0x0A, 0x0A, 0x06, 0x00,/*剪1211*/},\n        {\n\n                0x04, 0x08, 0xFC, 0x04, 0xD4, 0x54, 0xD4, 0x04, 0xFF, 0x84, 0x65, 0x02, 0x09, 0x07, 0x00, 0x03,\n                0x02, 0x0B, 0x04, 0x03, 0x05, 0x0E,/*减1212*/},\n        {\n\n                0x12, 0x92, 0xD7, 0x32, 0x1A, 0x52, 0x52, 0x52, 0xD7, 0x52, 0x12, 0x01, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x0A, 0x0F, 0x02, 0x02, 0x02,/*荐1213*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x9E, 0x80, 0xBF, 0x88, 0x87, 0x94, 0xA4, 0x00, 0x00, 0x0F, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*槛1214*/},\n        {\n\n                0x20, 0x2E, 0x50, 0x5F, 0x48, 0xC4, 0x4B, 0x52, 0x56, 0x2A, 0x22, 0x08, 0x09, 0x0B, 0x0D, 0x09,\n                0x0F, 0x09, 0x0D, 0x0B, 0x09, 0x08,/*鉴1215*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0x48, 0x48, 0xFF, 0x24, 0xA5, 0x26, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x08, 0x04, 0x03, 0x05, 0x08, 0x0E,/*践1216*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x48, 0x48, 0xFF, 0x24, 0xA5, 0x26, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x04, 0x03, 0x05, 0x08, 0x0E,/*贱1217*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0x82, 0x7A, 0x82, 0x02, 0x02, 0xFE, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*见1218*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x64, 0xDC, 0x88, 0xAA, 0xFF, 0xAA, 0xBE, 0x08, 0x00, 0x0F, 0x04, 0x0A, 0x07,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0A,/*键1219*/},\n        {\n\n                0x24, 0xE3, 0xAA, 0xB6, 0xA2, 0xE4, 0x23, 0xB2, 0x26, 0xE2, 0x22, 0x00, 0x0F, 0x02, 0x02, 0x0A,\n                0x0F, 0x00, 0x03, 0x08, 0x0F, 0x00,/*箭1220*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x90, 0x8E, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x88, 0x00, 0x0F, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*件1221*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x64, 0xDC, 0x88, 0xAA, 0xFF, 0xAA, 0xBE, 0x08, 0x00, 0x0F, 0x00, 0x0A, 0x07,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0A,/*健1222*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x08, 0x04, 0x03, 0x06, 0x08, 0x0C,/*舰1223*/},\n        {\n\n                0x20, 0x90, 0x28, 0x64, 0xA3, 0x24, 0xA8, 0x10, 0xFC, 0x00, 0xFF, 0x08, 0x08, 0x0B, 0x08, 0x05,\n                0x06, 0x05, 0x00, 0x01, 0x08, 0x0F,/*剑1224*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x4C, 0x48, 0x48, 0xFF, 0x48, 0x25, 0xA6, 0x24, 0x00, 0x0F, 0x04, 0x0A, 0x08,\n                0x04, 0x04, 0x03, 0x05, 0x08, 0x0E,/*饯1225*/},\n        {\n\n                0x22, 0x44, 0x34, 0x2C, 0xF7, 0xA4, 0x00, 0xFE, 0x12, 0xF2, 0x11, 0x04, 0x02, 0x01, 0x01, 0x0F,\n                0x00, 0x08, 0x07, 0x00, 0x0F, 0x00,/*渐1226*/},\n        {\n\n                0x22, 0x44, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x28, 0xFF, 0x14, 0xD5, 0x04, 0x02, 0x09, 0x04, 0x03,\n                0x04, 0x09, 0x04, 0x03, 0x05, 0x0E,/*溅1227*/},\n        {\n\n                0x22, 0x44, 0x00, 0xF9, 0x02, 0xF8, 0x4A, 0x4A, 0xFA, 0x02, 0xFE, 0x04, 0x02, 0x00, 0x0F, 0x00,\n                0x03, 0x02, 0x02, 0x0B, 0x08, 0x0F,/*涧1228*/},\n        {\n\n                0x32, 0x2A, 0xE6, 0x08, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xBE, 0x08, 0x09, 0x06, 0x05, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x0A,/*建1229*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x82, 0xBE, 0xAA, 0xBE, 0xAA, 0xAA, 0xBE, 0x82, 0x00, 0x0F, 0x00, 0x08, 0x0F,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0F, 0x08,/*僵1230*/},\n        {\n\n                0x40, 0x54, 0x55, 0x56, 0xD4, 0x7C, 0x54, 0x56, 0x55, 0x54, 0x40, 0x09, 0x09, 0x0B, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*姜1231*/},\n        {\n\n                0x04, 0x88, 0xFF, 0x40, 0x48, 0x64, 0x6B, 0x52, 0x4A, 0xE6, 0x40, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x02, 0x08, 0x08, 0x0F, 0x00,/*将1232*/},\n        {\n\n                0xA2, 0x94, 0x80, 0xBF, 0x00, 0xE8, 0xA4, 0x2B, 0x92, 0x4A, 0x06, 0x04, 0x04, 0x02, 0x01, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*浆1233*/},\n        {\n\n                0x22, 0x44, 0x00, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x00, 0x04, 0x02, 0x09, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x08,/*江1234*/},\n        {\n\n                0xBA, 0xEA, 0xAA, 0xEE, 0x82, 0xBE, 0xAA, 0xBE, 0xAA, 0xBE, 0x82, 0x02, 0x0B, 0x0A, 0x07, 0x08,\n                0x0F, 0x0A, 0x0F, 0x0A, 0x0F, 0x08,/*疆1235*/},\n        {\n\n                0x12, 0x22, 0xFA, 0x27, 0x92, 0xBA, 0x52, 0x57, 0xB2, 0x12, 0x02, 0x02, 0x01, 0x0F, 0x01, 0x03,\n                0x05, 0x01, 0x09, 0x0F, 0x01, 0x01,/*蒋1236*/},\n        {\n\n                0xA2, 0x94, 0x80, 0xBF, 0x80, 0xC8, 0xA4, 0xAB, 0x92, 0x8A, 0x86, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*桨1237*/},\n        {\n\n                0x22, 0x14, 0x00, 0x7F, 0x00, 0x88, 0x44, 0x2B, 0x12, 0x0A, 0x06, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*奖1238*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x88, 0x88, 0xFF, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x00, 0x07, 0x02, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x0F, 0x00, 0x00,/*讲1239*/},\n        {\n\n                0x00, 0xFF, 0x01, 0x01, 0xF9, 0x49, 0x49, 0x49, 0xC5, 0x45, 0x41, 0x00, 0x0F, 0x08, 0x0C, 0x0B,\n                0x08, 0x08, 0x08, 0x0F, 0x08, 0x08,/*匠1240*/},\n        {\n\n                0x20, 0xB1, 0xAA, 0xFF, 0xA0, 0xB4, 0xB6, 0xEB, 0xAA, 0xA6, 0x22, 0x00, 0x0F, 0x0A, 0x09, 0x0A,\n                0x0A, 0x0A, 0x09, 0x0A, 0x0F, 0x00,/*酱1241*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0x54, 0x57, 0xEA, 0x4A, 0x56, 0x10, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x03, 0x02, 0x0F, 0x02, 0x02, 0x02,/*降1242*/},\n        {\n\n                0x22, 0x12, 0xFA, 0xAF, 0xAA, 0xAE, 0xFA, 0xAF, 0xAA, 0xAA, 0x0A, 0x08, 0x04, 0x03, 0x06, 0x0A,\n                0x02, 0x07, 0x0A, 0x02, 0x06, 0x0A,/*蕉1243*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0xDF, 0x14, 0x12, 0xFE, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x02, 0x09,\n                0x0F, 0x01, 0x0A, 0x04, 0x03, 0x0C,/*椒1244*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x08, 0xFC, 0x57, 0x54, 0xFD, 0x56, 0x54, 0x00, 0x07, 0x02, 0x03, 0x0C,\n                0x03, 0x0D, 0x01, 0x0D, 0x01, 0x0D,/*礁1245*/},\n        {\n\n                0x08, 0x04, 0xFE, 0x55, 0x54, 0x54, 0xFD, 0x56, 0x54, 0x54, 0x04, 0x08, 0x04, 0x03, 0x05, 0x09,\n                0x01, 0x05, 0x09, 0x01, 0x05, 0x09,/*焦1246*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x40, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*胶1247*/},\n        {\n\n                0x04, 0x44, 0x24, 0x54, 0x85, 0x06, 0x84, 0x54, 0x24, 0x44, 0x04, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x04, 0x08, 0x08,/*交1248*/},\n        {\n\n                0x44, 0x34, 0x85, 0x06, 0x94, 0x24, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x04, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郊1249*/},\n        {\n\n                0x22, 0x44, 0x00, 0x84, 0xA4, 0xA4, 0xAF, 0x92, 0xAA, 0xA6, 0xB2, 0x04, 0x02, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0C,/*浇1250*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x2A, 0x9A, 0x0E, 0x19, 0xA9, 0x48, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*骄1251*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x40, 0x2A, 0x9A, 0x0E, 0x19, 0xA9, 0x48, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*娇1252*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xBA, 0xAE, 0xBA, 0x2E, 0xB9, 0xED, 0xB9, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x0A, 0x07, 0x08, 0x0A, 0x0F, 0x00,/*嚼1253*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x0D, 0xF6, 0x15, 0xD6, 0x14, 0xF6, 0x0D, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x05, 0x02, 0x01, 0x06, 0x09, 0x0E,/*搅1254*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x80, 0x44, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*铰1255*/},\n        {\n\n                0x48, 0x47, 0xFC, 0x44, 0x40, 0x2A, 0x9A, 0x0E, 0x19, 0xA9, 0x48, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*矫1256*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x84, 0xA4, 0xA4, 0xAF, 0x92, 0xAA, 0xA6, 0xB2, 0x00, 0x0F, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0C,/*侥1257*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xA4, 0x7F, 0x24, 0x00, 0xFE, 0x02, 0xFE, 0x07, 0x08, 0x0F, 0x00, 0x03,\n                0x02, 0x03, 0x00, 0x0F, 0x02, 0x03,/*脚1258*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x44, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x01, 0x08, 0x08, 0x07, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*狡1259*/},\n        {\n\n                0x08, 0xF4, 0x53, 0x52, 0x52, 0xF2, 0x5A, 0x56, 0x50, 0xF0, 0x00, 0x08, 0x07, 0x01, 0x01, 0x01,\n                0x07, 0x01, 0x01, 0x09, 0x0F, 0x00,/*角1260*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x40, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*饺1261*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0xBE, 0xEB, 0xBE, 0xD0, 0x0F, 0xF8, 0x08, 0x04, 0x04, 0x02, 0x08, 0x07,\n                0x0A, 0x0E, 0x05, 0x02, 0x05, 0x08,/*缴1262*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x40, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*绞1263*/},\n        {\n\n                0x02, 0xFD, 0xAA, 0xFD, 0xAA, 0xFD, 0x00, 0x00, 0xFC, 0x00, 0xFF, 0x0A, 0x06, 0x02, 0x0F, 0x02,\n                0x06, 0x0A, 0x00, 0x01, 0x08, 0x0F,/*剿1264*/},\n        {\n\n                0xA8, 0x6A, 0x3F, 0xAA, 0x6C, 0x0A, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x02, 0x02, 0x0A, 0x0F, 0x01,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*教1265*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0xA8, 0x6A, 0x3F, 0xAA, 0x6C, 0x0A, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x01, 0x09, 0x0F, 0x01, 0x01,/*酵1266*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x48, 0xAA, 0x1A, 0x0E, 0x19, 0xA9, 0x48, 0x02, 0x02, 0x0F, 0x01, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x0F, 0x00,/*轿1267*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x40, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x02, 0x02, 0x0F, 0x01, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*较1268*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0xFE, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x03, 0x01, 0x01, 0x00, 0x0F, 0x00,/*叫1269*/},\n        {\n\n                0x86, 0xCA, 0xB6, 0xA2, 0xA2, 0xFB, 0xA2, 0xA2, 0xA6, 0xAA, 0x86, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*窖1270*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x80, 0x5F, 0x75, 0x55, 0xD5, 0x55, 0x5F, 0xC0, 0x08, 0x0F, 0x00, 0x00, 0x06,\n                0x04, 0x05, 0x04, 0x01, 0x08, 0x0F,/*揭1271*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xA4, 0xAC, 0xB5, 0xE6, 0xB4, 0xAC, 0xA4, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x0A, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*接1272*/},\n        {\n\n                0x00, 0xDF, 0x52, 0x4A, 0x6A, 0x40, 0x4F, 0x54, 0x52, 0xD1, 0x18, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*皆1273*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x04, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0x04, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*秸1274*/},\n        {\n\n                0x24, 0xF2, 0x09, 0x20, 0x24, 0xBF, 0x24, 0x20, 0x12, 0xF2, 0x12, 0x00, 0x0F, 0x00, 0x08, 0x09,\n                0x07, 0x05, 0x04, 0x08, 0x0F, 0x00,/*街1275*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x10, 0x08, 0xE4, 0x03, 0x04, 0xE8, 0x10, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x06, 0x01, 0x00, 0x00, 0x0F, 0x00,/*阶1276*/},\n        {\n\n                0x48, 0xEA, 0xBA, 0xAF, 0xFA, 0xAA, 0xA8, 0xFF, 0x08, 0xE9, 0x0A, 0x00, 0x0F, 0x0A, 0x0A, 0x0F,\n                0x0A, 0x0A, 0x04, 0x03, 0x04, 0x0E,/*截1277*/},\n        {\n\n                0x20, 0x24, 0xA4, 0x7F, 0x24, 0x24, 0x28, 0xFF, 0x08, 0x08, 0xF8, 0x00, 0x03, 0x02, 0x02, 0x0B,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*劫1278*/},\n        {\n\n                0x24, 0x24, 0x24, 0x2F, 0xE4, 0x24, 0x24, 0x2F, 0x24, 0xE4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x02, 0x03, 0x00,/*节1279*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x44, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*桔1280*/},\n        {\n\n                0x84, 0x84, 0x44, 0x24, 0x14, 0xFF, 0x14, 0x24, 0x44, 0x84, 0x84, 0x08, 0x04, 0x00, 0x04, 0x08,\n                0x01, 0x04, 0x08, 0x00, 0x04, 0x08,/*杰1281*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x06, 0x08, 0x0F, 0x0A, 0x0A, 0x0A,/*捷1282*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x20, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xFA, 0x22, 0x0F, 0x04, 0x0F, 0x08, 0x06,\n                0x08, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*睫1283*/},\n        {\n\n                0x28, 0xC9, 0x0A, 0xE8, 0x80, 0x5F, 0x75, 0xD5, 0x55, 0x5F, 0xC0, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x06, 0x05, 0x04, 0x09, 0x08, 0x07,/*竭1284*/},\n        {\n\n                0x22, 0x44, 0x00, 0xA4, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0xA4, 0x04, 0x04, 0x02, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*洁1285*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x04, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*结1286*/},\n        {\n\n                0x08, 0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x89, 0x67, 0x41, 0xE9, 0x4F, 0x08, 0x07, 0x01, 0x07, 0x09,\n                0x0F, 0x00, 0x02, 0x02, 0x0F, 0x02,/*解1287*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*姐1288*/},\n        {\n\n                0x44, 0x44, 0xF4, 0x44, 0xF4, 0x44, 0x44, 0xFF, 0x04, 0xC5, 0x34, 0x08, 0x04, 0x03, 0x00, 0x0F,\n                0x00, 0x08, 0x04, 0x03, 0x04, 0x0E,/*戒1289*/},\n        {\n\n                0x8A, 0xAA, 0xFE, 0xAB, 0x02, 0xAA, 0xBE, 0xAB, 0xBE, 0xAA, 0x22, 0x04, 0x02, 0x0F, 0x02, 0x04,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*藉1290*/},\n        {\n\n                0x42, 0x42, 0x22, 0xA7, 0x12, 0x0A, 0x12, 0xA7, 0x22, 0x42, 0x42, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*芥1291*/},\n        {\n\n                0x80, 0x9F, 0x95, 0x55, 0x55, 0x3F, 0x55, 0x55, 0x95, 0x9F, 0x80, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*界1292*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x10, 0xD4, 0x5F, 0x54, 0x54, 0x5F, 0xD4, 0x10, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*借1293*/},\n        {\n\n                0x20, 0x20, 0x10, 0xC8, 0x04, 0x03, 0x04, 0xC8, 0x10, 0x20, 0x20, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*介1294*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x44, 0x24, 0x95, 0x0E, 0x14, 0xA4, 0x44, 0x44, 0x09, 0x04, 0x03, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x0F, 0x00, 0x00,/*疥1295*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x44, 0xF4, 0x44, 0xF4, 0x44, 0xFF, 0x84, 0x65, 0x00, 0x07, 0x02, 0x04, 0x03,\n                0x00, 0x0B, 0x04, 0x03, 0x05, 0x0E,/*诫1296*/},\n        {\n\n                0x00, 0xFF, 0x05, 0xE5, 0x25, 0x25, 0xFD, 0x25, 0x25, 0x25, 0xE7, 0x08, 0x07, 0x00, 0x0F, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x0F,/*届1297*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x04, 0x04, 0xFF, 0x04, 0x04, 0x04, 0xFC, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x02, 0x03, 0x00,/*巾1298*/},\n        {\n\n                0x04, 0xF3, 0x56, 0x5A, 0xF2, 0x00, 0x24, 0xF3, 0x26, 0x2A, 0xE2, 0x08, 0x07, 0x01, 0x09, 0x0F,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*筋1299*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0xE1, 0x21, 0x21, 0x20, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*斤1300*/},\n        {\n\n                0x10, 0x90, 0x88, 0x94, 0x92, 0xF1, 0x92, 0x94, 0x88, 0x90, 0x10, 0x08, 0x08, 0x0A, 0x0C, 0x08,\n                0x0F, 0x08, 0x0C, 0x0A, 0x08, 0x08,/*金1301*/},\n        {\n\n                0x10, 0x90, 0x88, 0x84, 0x92, 0xA1, 0x82, 0x84, 0x88, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x08, 0x04, 0x02, 0x01, 0x00, 0x00,/*今1302*/},\n        {\n\n                0x22, 0x44, 0x00, 0x08, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xBE, 0x08, 0x04, 0x02, 0x01, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*津1303*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x0A, 0x5F, 0x52, 0x4A, 0x5F, 0x4A, 0x12, 0x00, 0x00, 0x0F, 0x00, 0x05,\n                0x03, 0x09, 0x0F, 0x01, 0x03, 0x05,/*襟1304*/},\n        {\n\n                0x0E, 0x00, 0x40, 0x6F, 0xD0, 0x49, 0x4B, 0x25, 0x85, 0x0B, 0x10, 0x00, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x00,/*紧1305*/},\n        {\n\n                0x54, 0xF3, 0x52, 0x52, 0x80, 0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0x80, 0x00, 0x07, 0x02, 0x01, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*锦1306*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x02, 0x3E, 0xC2, 0x02, 0x82, 0x62, 0x1E, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*仅1307*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xE2, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xE2, 0x00, 0x00, 0x0F, 0x04, 0x0A,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0A,/*谨1308*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x40, 0x44, 0xFF, 0x44, 0x44, 0xFF, 0x44, 0x40, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x09, 0x08, 0x08, 0x0B, 0x08, 0x08,/*进1309*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x02, 0x02, 0x0F, 0x02, 0x0A,\n                0x04, 0x03, 0x00, 0x00, 0x0F, 0x00,/*靳1310*/},\n        {\n\n                0x10, 0xD5, 0x59, 0x51, 0x5F, 0x51, 0x5F, 0x51, 0x59, 0xD5, 0x10, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*晋1311*/},\n        {\n\n                0x12, 0x4A, 0x7F, 0x4A, 0x52, 0x40, 0x52, 0x4A, 0x7F, 0x4A, 0x12, 0x01, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x01,/*禁1312*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x09, 0x08, 0x08, 0x0B, 0x08, 0x08,/*近1313*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x84, 0x7E, 0x12, 0xB2, 0x52, 0x9E, 0x00, 0x08, 0x06, 0x01, 0x03, 0x04,\n                0x00, 0x02, 0x04, 0x09, 0x00, 0x01,/*烬1314*/},\n        {\n\n                0x11, 0x22, 0x00, 0xC0, 0x51, 0x55, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x04, 0x02, 0x00, 0x08, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*浸1315*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x12, 0x52, 0x52, 0x92, 0x72, 0x92, 0x1E, 0x00, 0x02, 0x01, 0x00, 0x02, 0x02,\n                0x04, 0x04, 0x08, 0x00, 0x01, 0x02,/*尽1316*/},\n        {\n\n                0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x08, 0x08, 0x07, 0x04, 0x04,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*劲1317*/},\n        {\n\n                0x82, 0x92, 0xF7, 0x92, 0x92, 0xF7, 0x92, 0x82, 0xFC, 0x00, 0xFF, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x01, 0x08, 0x0F,/*荆1318*/},\n        {\n\n                0xF4, 0x94, 0x9F, 0x94, 0xF4, 0x00, 0xF4, 0x94, 0x9F, 0x94, 0xF4, 0x08, 0x07, 0x00, 0x0F, 0x04,\n                0x08, 0x04, 0x02, 0x07, 0x08, 0x0C,/*兢1319*/},\n        {\n\n                0x82, 0x8A, 0x8A, 0x4F, 0x4A, 0x2A, 0x2A, 0x5F, 0x5A, 0x8A, 0x82, 0x08, 0x08, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x08, 0x08,/*茎1320*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0x22, 0x0F, 0x04, 0x0F, 0x00, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*睛1321*/},\n        {\n\n                0xC0, 0x40, 0x5F, 0x55, 0xD5, 0x15, 0xD5, 0x55, 0x5F, 0x40, 0xC0, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x05, 0x05, 0x05, 0x0F,/*晶1322*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x04, 0xF4, 0x95, 0x96, 0x94, 0xF4, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x04, 0x02, 0x08, 0x0F, 0x02, 0x04,/*鲸1323*/},\n        {\n\n                0x04, 0xF4, 0x94, 0x94, 0x95, 0x96, 0x94, 0x94, 0x94, 0xF4, 0x04, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*京1324*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xF4, 0x95, 0x96, 0x94, 0xF4, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*惊1325*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0x22, 0x01, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*精1326*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0xFA, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xFA, 0x01, 0x00, 0x0F, 0x01, 0x08,\n                0x05, 0x02, 0x05, 0x08, 0x08, 0x08,/*粳1327*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x40, 0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*经1328*/},\n        {\n\n                0x80, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x80, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*井1329*/},\n        {\n\n                0x92, 0xBF, 0xAA, 0xBA, 0xCF, 0xBA, 0xC4, 0xAB, 0x92, 0xAE, 0xC2, 0x00, 0x02, 0x0E, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0E, 0x02, 0x00,/*警1330*/},\n        {\n\n                0x40, 0x40, 0xDF, 0x55, 0x55, 0x75, 0x55, 0x55, 0xDF, 0x40, 0x40, 0x00, 0x08, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x08, 0x00,/*景1331*/},\n        {\n\n                0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x08, 0x08, 0x07, 0x04, 0x04,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颈1332*/},\n        {\n\n                0x22, 0xEA, 0xBF, 0xEA, 0x2A, 0x54, 0x53, 0xFA, 0x56, 0xF0, 0x40, 0x00, 0x0F, 0x02, 0x0F, 0x00,\n                0x01, 0x09, 0x0F, 0x01, 0x03, 0x00,/*静1333*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x08, 0xEA, 0xAE, 0xAB, 0xAA, 0xAE, 0xEA, 0x08, 0x04, 0x07, 0x02, 0x08, 0x0B,\n                0x06, 0x02, 0x02, 0x0E, 0x0B, 0x0C,/*境1334*/},\n        {\n\n                0x22, 0xD7, 0x5A, 0xD2, 0x17, 0xF2, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x00, 0x07, 0x02, 0x0B, 0x08,\n                0x07, 0x08, 0x05, 0x02, 0x05, 0x08,/*敬1335*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x08, 0xEA, 0xAE, 0xAB, 0xAA, 0xAE, 0xEA, 0x08, 0x00, 0x0F, 0x04, 0x08, 0x0B,\n                0x06, 0x02, 0x02, 0x0E, 0x0B, 0x0C,/*镜1336*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x40, 0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*径1337*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x94, 0x95, 0x56, 0x54, 0x34, 0x54, 0x84, 0x09, 0x04, 0x03, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*痉1338*/},\n        {\n\n                0x28, 0xC9, 0x0A, 0xE8, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0x22, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*靖1339*/},\n        {\n\n                0x08, 0xEA, 0xAA, 0xAE, 0xAA, 0xAB, 0xAA, 0xAE, 0xAA, 0xEA, 0x08, 0x08, 0x0B, 0x0A, 0x06, 0x02,\n                0x02, 0x02, 0x06, 0x0A, 0x0B, 0x0C,/*竟1340*/},\n        {\n\n                0x10, 0xD2, 0x56, 0x5A, 0x52, 0x53, 0x52, 0x5A, 0x56, 0xD2, 0x10, 0x08, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x07, 0x09, 0x09, 0x09, 0x0C,/*竞1341*/},\n        {\n\n                0x04, 0x08, 0x40, 0x54, 0x53, 0x52, 0xF2, 0x5A, 0x56, 0xF0, 0x40, 0x02, 0x01, 0x00, 0x01, 0x09,\n                0x09, 0x0F, 0x01, 0x01, 0x03, 0x00,/*净1342*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x02, 0xF2, 0x12, 0xF2, 0x02, 0xFE, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*炯1343*/},\n        {\n\n                0x26, 0xAA, 0xAE, 0xEA, 0xBA, 0xAB, 0xAA, 0xAA, 0xFE, 0x2A, 0x26, 0x04, 0x02, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*窘1344*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x92, 0xFE, 0x51, 0x08, 0xFF, 0x10, 0x0C, 0x00, 0x08, 0x0F, 0x01, 0x00,\n                0x0F, 0x08, 0x07, 0x00, 0x07, 0x08,/*揪1345*/},\n        {\n\n                0x0C, 0xA4, 0x94, 0x8C, 0xE5, 0x86, 0x84, 0x8C, 0x14, 0x24, 0x0C, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*究1346*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xFE, 0x00, 0x00, 0x80, 0xFF, 0x00, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x03, 0x01, 0x01, 0x00, 0x0F, 0x00,/*纠1347*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x20, 0x18, 0x07, 0x84, 0x64, 0x1C, 0x00, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*玖1348*/},\n        {\n\n                0x24, 0x24, 0x24, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0x24, 0x24, 0x24, 0x09, 0x09, 0x09, 0x0F, 0x08,\n                0x08, 0x08, 0x0F, 0x09, 0x09, 0x09,/*韭1349*/},\n        {\n\n                0x40, 0x30, 0x0F, 0x04, 0x04, 0x84, 0x44, 0x34, 0x0C, 0x00, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*久1350*/},\n        {\n\n                0x20, 0x28, 0xA4, 0x13, 0x12, 0xCA, 0x0A, 0x16, 0x12, 0xA0, 0x00, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x05, 0x08, 0x08,/*灸1351*/},\n        {\n\n                0x08, 0x08, 0x08, 0xFF, 0x08, 0x08, 0x08, 0xF8, 0x00, 0x00, 0x00, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*九1352*/},\n        {\n\n                0x22, 0x44, 0x02, 0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x02, 0x04, 0x02, 0x00, 0x0F, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*酒1353*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xFA, 0xAA, 0xFA, 0x02, 0x6A, 0xCA, 0x7A, 0x4A, 0x08, 0x07, 0x00, 0x0F, 0x0A,\n                0x04, 0x08, 0x06, 0x01, 0x0F, 0x08,/*厩1354*/},\n        {\n\n                0x28, 0x48, 0xFF, 0x48, 0x2A, 0x10, 0xEF, 0x08, 0x88, 0x78, 0x08, 0x02, 0x09, 0x0F, 0x01, 0x0A,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*救1355*/},\n        {\n\n                0x00, 0xFE, 0x00, 0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0xFE, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*旧1356*/},\n        {\n\n                0x00, 0xFC, 0x44, 0x42, 0x42, 0x01, 0x00, 0x44, 0x44, 0x44, 0xFC, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*臼1357*/},\n        {\n\n                0x00, 0x3E, 0xEA, 0xAA, 0xA9, 0xE0, 0xAA, 0xAA, 0xEA, 0x3E, 0x00, 0x0A, 0x0A, 0x0B, 0x06, 0x02,\n                0x03, 0x02, 0x02, 0x0B, 0x0A, 0x06,/*舅1358*/},\n        {\n\n                0x48, 0x44, 0xAB, 0x92, 0xAA, 0xA6, 0xA0, 0xBF, 0xA0, 0xA2, 0x2C, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*咎1359*/},\n        {\n\n                0xF4, 0x95, 0x96, 0x94, 0xF4, 0x08, 0xFF, 0x08, 0xFA, 0x0C, 0x08, 0x06, 0x08, 0x0F, 0x02, 0x04,\n                0x08, 0x07, 0x00, 0x07, 0x08, 0x0E,/*就1360*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x84, 0x45, 0x36, 0x24, 0xA4, 0x64, 0x04, 0x09, 0x04, 0x03, 0x08, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*疚1361*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x54, 0x43, 0xFA, 0x42, 0x52, 0xFE, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x02, 0x01, 0x07, 0x09, 0x0A, 0x07,/*鞠1362*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0xE8, 0x27, 0x24, 0xE4, 0x04, 0xFC, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x03, 0x01, 0x01, 0x09, 0x08, 0x07,/*拘1363*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x01, 0x08, 0x08, 0x07, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*狙1364*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xFA, 0x4A, 0x4B, 0x4A, 0x4A, 0xFA, 0x02, 0x09, 0x04, 0x03, 0x08, 0x0F,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x08,/*疽1365*/},\n        {\n\n                0x00, 0xFF, 0x29, 0xA9, 0xA9, 0xA9, 0xF9, 0xA9, 0xA9, 0xAF, 0x20, 0x08, 0x07, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*居1366*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x10, 0xE8, 0x27, 0xE4, 0x04, 0xFC, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x00, 0x03, 0x01, 0x09, 0x08, 0x07,/*驹1367*/},\n        {\n\n                0x92, 0xAE, 0xCA, 0x8F, 0xFA, 0x8A, 0xCA, 0xAF, 0x0A, 0xFA, 0x02, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x00, 0x09, 0x0A, 0x08, 0x07, 0x00,/*菊1368*/},\n        {\n\n                0x00, 0xFF, 0x15, 0xD5, 0x55, 0x55, 0x55, 0x55, 0xD5, 0x17, 0xF0, 0x08, 0x07, 0x00, 0x07, 0x02,\n                0x02, 0x02, 0x0A, 0x0B, 0x08, 0x07,/*局1369*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*咀1370*/},\n        {\n\n                0x48, 0x47, 0xFC, 0x44, 0x40, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x09,/*矩1371*/},\n        {\n\n                0x48, 0xCA, 0xAC, 0x98, 0x89, 0xEA, 0x88, 0x98, 0xAC, 0xCA, 0x48, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*举1372*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xFE, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x04, 0x02, 0x09, 0x08, 0x0F,\n                0x08, 0x08, 0x08, 0x08, 0x0F, 0x08,/*沮1373*/},\n        {\n\n                0x11, 0x9F, 0x95, 0x95, 0xBF, 0x89, 0x48, 0x51, 0x55, 0x49, 0x17, 0x0A, 0x0A, 0x09, 0x04, 0x02,\n                0x0F, 0x01, 0x02, 0x04, 0x0A, 0x09,/*聚1374*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x09,/*拒1375*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xAE, 0x00, 0x08, 0x0F, 0x08, 0x06,\n                0x01, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*据1376*/},\n        {\n\n                0x00, 0xFE, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x08,/*巨1377*/},\n        {\n\n                0x00, 0x00, 0xFF, 0x55, 0x55, 0x55, 0x55, 0x55, 0xFF, 0x00, 0x00, 0x01, 0x09, 0x05, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x05, 0x09, 0x01,/*具1378*/},\n        {\n\n                0x00, 0x9E, 0x12, 0xF2, 0x9E, 0x00, 0xFE, 0x12, 0x12, 0x12, 0xF2, 0x08, 0x0F, 0x08, 0x07, 0x04,\n                0x00, 0x0F, 0x09, 0x09, 0x09, 0x09,/*距1379*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x00, 0xFF, 0x09, 0xA9, 0xF9, 0xA9, 0xAF, 0x07, 0x04, 0x03, 0x0A, 0x04,\n                0x03, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*踞1380*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xAE, 0x00, 0x0F, 0x04, 0x08, 0x06,\n                0x01, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*锯1381*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFF, 0x55, 0x55, 0x55, 0x55, 0xFF, 0x00, 0x00, 0x0F, 0x00, 0x01, 0x09,\n                0x05, 0x01, 0x01, 0x05, 0x09, 0x01,/*俱1382*/},\n        {\n\n                0x08, 0x04, 0xF3, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x03, 0x01, 0x01,\n                0x01, 0x01, 0x09, 0x08, 0x08, 0x07,/*句1383*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFF, 0x55, 0x55, 0x55, 0x55, 0xFF, 0x00, 0x00, 0x00, 0x0F, 0x01, 0x09,\n                0x05, 0x01, 0x01, 0x05, 0x09, 0x01,/*惧1384*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x09,/*炬1385*/},\n        {\n\n                0x00, 0xFF, 0xA9, 0xA9, 0xF9, 0xA9, 0xAF, 0x00, 0xFC, 0x00, 0xFF, 0x02, 0x01, 0x0F, 0x04, 0x04,\n                0x04, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*剧1386*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xF7, 0x55, 0x55, 0x55, 0x55, 0xF7, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x01, 0x01, 0x01, 0x09, 0x0F,/*捐1387*/},\n        {\n\n                0xEE, 0xAA, 0xAA, 0xAA, 0xEE, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x0F, 0x02, 0x02, 0x0A, 0x0F,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鹃1388*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xF7, 0x55, 0x55, 0x55, 0x55, 0xF7, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x01, 0x01, 0x01, 0x09, 0x0F,/*娟1389*/},\n        {\n\n                0x10, 0xFC, 0x93, 0x55, 0xB6, 0x9C, 0x97, 0x94, 0xB6, 0x55, 0x90, 0x00, 0x0F, 0x00, 0x00, 0x07,\n                0x08, 0x08, 0x0A, 0x0B, 0x0C, 0x00,/*倦1390*/},\n        {\n\n                0x48, 0x2A, 0xFB, 0xAA, 0xAE, 0xAB, 0xAA, 0xAA, 0xFB, 0x2A, 0x48, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*眷1391*/},\n        {\n\n                0x90, 0x54, 0xB5, 0x96, 0x9C, 0x97, 0x94, 0x96, 0x35, 0x54, 0x90, 0x00, 0x00, 0x07, 0x08, 0x08,\n                0x0A, 0x0A, 0x09, 0x08, 0x0C, 0x00,/*卷1392*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xF7, 0x55, 0x55, 0x55, 0x55, 0xF7, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x01, 0x01, 0x01, 0x09, 0x0F,/*绢1393*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x2A, 0xF2, 0x2A, 0xA2, 0xDE, 0x32, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x09, 0x07, 0x09, 0x05, 0x03, 0x0C,/*撅1394*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x80, 0x5F, 0xF5, 0x5F, 0x40, 0xFF, 0x55, 0x5F, 0x08, 0x0F, 0x00, 0x00, 0x08,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x09,/*攫1395*/},\n        {\n\n                0x08, 0xFF, 0x88, 0x40, 0x44, 0x44, 0xFF, 0x44, 0x44, 0x7C, 0x40, 0x09, 0x0F, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x03, 0x04, 0x08, 0x08,/*抉1396*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x0A, 0xEA, 0x8A, 0xFA, 0x8A, 0xEE, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x0E, 0x08, 0x0F, 0x08, 0x0E,/*掘1397*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xFE, 0x0A, 0xEA, 0x8A, 0xFA, 0x8A, 0xEA, 0x0E, 0x00, 0x0F, 0x04, 0x03, 0x0E,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x0E,/*倔1398*/},\n        {\n\n                0x02, 0xBA, 0xAE, 0xAA, 0xBA, 0xAE, 0x39, 0x29, 0x2D, 0xBB, 0x01, 0x00, 0x0F, 0x0A, 0x07, 0x0A,\n                0x03, 0x01, 0x05, 0x09, 0x0F, 0x01,/*爵1399*/},\n        {\n\n                0x1C, 0x05, 0xF6, 0x14, 0x15, 0xD6, 0x14, 0x14, 0xF6, 0x05, 0x1C, 0x08, 0x08, 0x05, 0x04, 0x02,\n                0x01, 0x06, 0x08, 0x09, 0x08, 0x0C,/*觉1400*/},\n        {\n\n                0x04, 0x08, 0x40, 0x44, 0x44, 0x44, 0xFF, 0x44, 0x44, 0x7C, 0x40, 0x02, 0x01, 0x08, 0x08, 0x04,\n                0x03, 0x00, 0x03, 0x04, 0x08, 0x08,/*决1401*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x40, 0x44, 0x44, 0xFF, 0x44, 0x44, 0x7C, 0x40, 0x00, 0x07, 0x02, 0x08, 0x04,\n                0x03, 0x00, 0x03, 0x04, 0x08, 0x08,/*诀1402*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x08, 0xF4, 0x93, 0xF2, 0x9A, 0x96, 0xF0, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*绝1403*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x10, 0x08, 0x17, 0x24, 0x84, 0x44, 0xFC, 0x02, 0x02, 0x01, 0x01, 0x00,\n                0x02, 0x02, 0x01, 0x08, 0x08, 0x07,/*均1404*/},\n        {\n\n                0x02, 0xFA, 0x8A, 0xAF, 0xAA, 0xEA, 0xAA, 0x9F, 0x8A, 0xFA, 0x02, 0x00, 0x0F, 0x0A, 0x09, 0x08,\n                0x0F, 0x08, 0x09, 0x0A, 0x0F, 0x00,/*菌1405*/},\n        {\n\n                0x90, 0xA8, 0xE7, 0xA4, 0x94, 0x08, 0x17, 0x24, 0x84, 0x44, 0xFC, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x04, 0x02, 0x01, 0x08, 0x08, 0x07,/*钧1406*/},\n        {\n\n                0x03, 0x09, 0x69, 0x59, 0x4F, 0xE9, 0x49, 0x49, 0x49, 0x09, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*军1407*/},\n        {\n\n                0x08, 0x2A, 0xAA, 0xEA, 0xBE, 0xAA, 0xAA, 0xAA, 0xAA, 0xBE, 0x08, 0x02, 0x01, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*君1408*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x20, 0x96, 0x65, 0x44, 0xD6, 0x2C, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*峻1409*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x24, 0x96, 0x65, 0x44, 0x44, 0xD6, 0x2C, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*俊1410*/},\n        {\n\n                0xE9, 0x0A, 0xE8, 0x00, 0x24, 0x96, 0x65, 0x44, 0x44, 0xD6, 0x2C, 0x04, 0x05, 0x02, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*竣1411*/},\n        {\n\n                0x22, 0x44, 0x00, 0x24, 0x96, 0x6D, 0x44, 0x44, 0xCC, 0x16, 0x2C, 0x04, 0x02, 0x08, 0x09, 0x04,\n                0x05, 0x02, 0x05, 0x04, 0x08, 0x08,/*浚1412*/},\n        {\n\n                0xAA, 0xEA, 0xBE, 0xAA, 0xAA, 0xBE, 0x08, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x0F, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郡1413*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x24, 0x96, 0x65, 0x44, 0x44, 0xD6, 0x2C, 0x02, 0x0A, 0x09, 0x07, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*骏1414*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x46, 0xD2, 0xAE, 0xAB, 0xAA, 0xDA, 0x46, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*喀1415*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0xFC, 0x04, 0xFC, 0x03, 0x01, 0x09, 0x04, 0x03,\n                0x08, 0x0F, 0x00, 0x0F, 0x04, 0x0F,/*咖1416*/},\n        {\n\n                0x20, 0x20, 0x20, 0x20, 0xFF, 0xA4, 0xA4, 0x24, 0x24, 0x24, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x01, 0x01, 0x02, 0x00,/*卡1417*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x28, 0xA4, 0xAB, 0x92, 0x92, 0xAA, 0xA6, 0x20, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*咯1418*/},\n        {\n\n                0x40, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*开1419*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xDF, 0x52, 0x4A, 0x60, 0x4F, 0x52, 0xD9, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*揩1420*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xDF, 0x52, 0x6A, 0x4F, 0x52, 0xD9, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*楷1421*/},\n        {\n\n                0xAE, 0xA8, 0xAF, 0xA8, 0xEE, 0x00, 0xFE, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x08, 0x04, 0x04, 0x0A,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*凯1422*/},\n        {\n\n                0x30, 0xFF, 0x08, 0xFE, 0x92, 0xFE, 0x00, 0x3A, 0xA2, 0x7E, 0x22, 0x00, 0x0F, 0x00, 0x0F, 0x0A,\n                0x04, 0x08, 0x06, 0x01, 0x0F, 0x08,/*慨1423*/},\n        {\n\n                0x20, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x20, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x00, 0x01, 0x08, 0x08, 0x0F,/*刊1424*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x80, 0x82, 0xFF, 0xAA, 0xAA, 0xAA, 0xFF, 0x82, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x0A, 0x09, 0x08, 0x09, 0x0A, 0x08,/*堪1425*/},\n        {\n\n                0x80, 0x82, 0xFF, 0xAA, 0xAA, 0xFF, 0x82, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0x0F, 0x0A, 0x09, 0x08,\n                0x09, 0x0A, 0x06, 0x09, 0x08, 0x07,/*勘1426*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x20, 0x18, 0x07, 0xE4, 0x04, 0x14, 0x0C, 0x02, 0x02, 0x01, 0x01, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*坎1427*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x20, 0x18, 0x07, 0xE4, 0x04, 0x14, 0x0C, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*砍1428*/},\n        {\n\n                0x20, 0xAA, 0xEA, 0xAA, 0xBA, 0xAE, 0xA9, 0xA9, 0xA9, 0xE9, 0x20, 0x01, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*看1429*/},\n        {\n\n                0x00, 0xFE, 0x22, 0xAA, 0xAA, 0xAB, 0xFE, 0xAA, 0xAA, 0xFA, 0x22, 0x08, 0x07, 0x00, 0x0A, 0x04,\n                0x0A, 0x0F, 0x02, 0x04, 0x0A, 0x08,/*康1430*/},\n        {\n\n                0x30, 0xFF, 0x08, 0xFE, 0x22, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x00, 0x0F, 0x08, 0x07, 0x08,\n                0x05, 0x0A, 0x0F, 0x02, 0x05, 0x08,/*慷1431*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0xFE, 0x22, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x01, 0x00, 0x0F, 0x09, 0x07,\n                0x05, 0x0A, 0x0F, 0x02, 0x05, 0x08,/*糠1432*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x48, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*扛1433*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x04, 0xE4, 0x25, 0x26, 0xE4, 0x04, 0x04, 0x00, 0x08, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*抗1434*/},\n        {\n\n                0x04, 0x04, 0xE4, 0x24, 0x25, 0x26, 0x24, 0xE4, 0x04, 0x04, 0x04, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*亢1435*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x10, 0x0C, 0xE4, 0x25, 0x26, 0xE4, 0x04, 0x04, 0x08, 0x06, 0x01, 0x0A, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*炕1436*/},\n        {\n\n                0x10, 0x14, 0x94, 0xD4, 0x7F, 0x54, 0x5C, 0x54, 0x52, 0x50, 0x10, 0x02, 0x01, 0x00, 0x01, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*考1437*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x94, 0xD4, 0x7F, 0x54, 0x58, 0x54, 0x12, 0x08, 0x0F, 0x00, 0x01, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*拷1438*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x94, 0xD4, 0x7F, 0x54, 0x58, 0x54, 0x12, 0x08, 0x06, 0x01, 0x03, 0x04,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*烤1439*/},\n        {\n\n                0x88, 0x8C, 0xBB, 0xAA, 0xEA, 0x2F, 0xEA, 0xAA, 0xBA, 0x8A, 0x88, 0x02, 0x02, 0x02, 0x02, 0x0F,\n                0x00, 0x0F, 0x02, 0x02, 0x02, 0x02,/*靠1440*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x02, 0xF2, 0x12, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x04, 0x07, 0x02, 0x00, 0x03,\n                0x01, 0x01, 0x09, 0x08, 0x0F, 0x00,/*坷1441*/},\n        {\n\n                0x12, 0xD2, 0x52, 0x57, 0x52, 0xD2, 0x12, 0x17, 0xF2, 0x12, 0x12, 0x00, 0x07, 0x02, 0x02, 0x02,\n                0x03, 0x08, 0x08, 0x0F, 0x00, 0x00,/*苛1442*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x42, 0xF2, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x03, 0x01, 0x01, 0x08, 0x0F, 0x00,/*柯1443*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*棵1444*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x4A, 0x6A, 0x5F, 0x4A, 0x6A, 0x00, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x0F, 0x09, 0x0F, 0x09, 0x0F, 0x08,/*磕1445*/},\n        {\n\n                0xBE, 0xAA, 0xFE, 0xAA, 0xBE, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x04, 0x02, 0x0F, 0x02, 0x04,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颗1446*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x90, 0x12, 0x24, 0x00, 0xFF, 0x80, 0x80, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x01, 0x0F, 0x00, 0x00,/*科1447*/},\n        {\n\n                0x62, 0x2A, 0x2A, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0x2A, 0x2A, 0x62, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*壳1448*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x44, 0x03, 0x01, 0x03, 0x00, 0x09,\n                0x09, 0x04, 0x02, 0x03, 0x04, 0x08,/*咳1449*/},\n        {\n\n                0x02, 0xF2, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x02, 0xFE, 0x02, 0x00, 0x03, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x08, 0x08, 0x0F, 0x00,/*可1450*/},\n        {\n\n                0x11, 0x22, 0x00, 0x80, 0x5F, 0x75, 0x55, 0xD5, 0x55, 0x5F, 0xC0, 0x04, 0x02, 0x00, 0x00, 0x06,\n                0x04, 0x05, 0x04, 0x01, 0x08, 0x0F,/*渴1451*/},\n        {\n\n                0x04, 0xF4, 0x94, 0x94, 0x94, 0x9F, 0x94, 0x94, 0x94, 0xF4, 0x04, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*克1452*/},\n        {\n\n                0x00, 0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x00, 0xFC, 0x00, 0xFF, 0x08, 0x09, 0x09, 0x04, 0x02,\n                0x05, 0x08, 0x00, 0x01, 0x08, 0x0F,/*刻1453*/},\n        {\n\n                0x86, 0xA2, 0x92, 0xAE, 0x4A, 0x4B, 0x4A, 0xAA, 0x9A, 0x82, 0x86, 0x00, 0x00, 0x0F, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0F, 0x00, 0x00,/*客1454*/},\n        {\n\n                0x11, 0xF2, 0x40, 0x5F, 0x55, 0x55, 0xFF, 0x55, 0x55, 0x5F, 0x40, 0x00, 0x07, 0x02, 0x04, 0x02,\n                0x01, 0x0F, 0x01, 0x02, 0x04, 0x04,/*课1455*/},\n        {\n\n                0x08, 0xE8, 0xAE, 0xA8, 0xA8, 0xAF, 0xAA, 0xAA, 0xAA, 0xEA, 0x08, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*肯1456*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0xEE, 0xA8, 0xA8, 0xAF, 0xAA, 0xEA, 0x08, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*啃1457*/},\n        {\n\n                0x00, 0xFF, 0x95, 0x55, 0x15, 0x35, 0x55, 0x95, 0x95, 0x5F, 0x20, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x09,/*垦1458*/},\n        {\n\n                0x00, 0xFF, 0x95, 0x55, 0x15, 0x35, 0x55, 0x95, 0x95, 0x5F, 0x20, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x03, 0x0D,/*恳1459*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0x04, 0xE4, 0x25, 0x26, 0xE4, 0x04, 0x04, 0x04, 0x07, 0x02, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*坑1460*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0x04, 0xE4, 0x25, 0x26, 0xE4, 0x04, 0x04, 0x03, 0x01, 0x03, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*吭1461*/},\n        {\n\n                0x0C, 0xA4, 0x94, 0x8C, 0x85, 0x86, 0x84, 0x8C, 0x94, 0xA4, 0x0C, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*空1462*/},\n        {\n\n                0x21, 0x21, 0x3F, 0x51, 0x20, 0x9F, 0x05, 0x09, 0x3F, 0x40, 0x70, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*恐1463*/},\n        {\n\n                0x80, 0x82, 0x82, 0xF2, 0x4A, 0x46, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x0F, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*孔1464*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x4C, 0xA4, 0x95, 0x86, 0x94, 0xA4, 0x4C, 0x08, 0x0F, 0x00, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*控1465*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x02, 0x0A, 0x32, 0xC2, 0x3A, 0x02, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x08, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*抠1466*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x07, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x02, 0x07, 0x00,/*口1467*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFC, 0x04, 0x04, 0x04, 0x04, 0xFC, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*扣1468*/},\n        {\n\n                0x86, 0x92, 0x92, 0x92, 0x82, 0x23, 0xA2, 0x3E, 0xAA, 0x6A, 0x06, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x0C, 0x0A, 0x09, 0x0E, 0x08, 0x0C,/*寇1469*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*枯1470*/},\n        {\n\n                0x40, 0x4F, 0x49, 0x49, 0x4F, 0xF0, 0x4F, 0x49, 0x59, 0x6F, 0x40, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*哭1471*/},\n        {\n\n                0x06, 0xFA, 0x2A, 0xAE, 0x2A, 0x2B, 0xEA, 0x2E, 0x2A, 0xBA, 0x06, 0x08, 0x07, 0x00, 0x0D, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x0D, 0x00,/*窟1472*/},\n        {\n\n                0x12, 0x92, 0x97, 0x92, 0x92, 0xFA, 0x92, 0x92, 0x97, 0x92, 0x12, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*苦1473*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x28, 0xA6, 0xA4, 0xBF, 0xA4, 0xA4, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*酷1474*/},\n        {\n\n                0x00, 0xFE, 0x12, 0xD2, 0xB2, 0x9A, 0xD3, 0x92, 0x92, 0x92, 0x12, 0x08, 0x07, 0x02, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*库1475*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xFE, 0x12, 0xD2, 0xB3, 0xDE, 0x92, 0x92, 0x00, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x02, 0x02, 0x0F, 0x02, 0x02,/*裤1476*/},\n        {\n\n                0x12, 0x52, 0x4A, 0xDA, 0x56, 0x53, 0x56, 0x5A, 0x4A, 0x52, 0x12, 0x00, 0x00, 0x00, 0x01, 0x01,\n                0x01, 0x09, 0x09, 0x07, 0x00, 0x00,/*夸1477*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x52, 0xCA, 0x56, 0x53, 0x56, 0x4A, 0x52, 0x02, 0x02, 0x01, 0x01, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*垮1478*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x88, 0x52, 0xCA, 0x56, 0x53, 0x56, 0x4A, 0x52, 0x01, 0x09, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*挎1479*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x50, 0xCA, 0x56, 0x53, 0x56, 0x4A, 0x52, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*跨1480*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x50, 0xCA, 0x56, 0x53, 0x56, 0x4A, 0x52, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*胯1481*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x40, 0x44, 0x44, 0xFF, 0x44, 0x44, 0x7C, 0x40, 0x02, 0x03, 0x01, 0x08, 0x04,\n                0x03, 0x00, 0x03, 0x04, 0x08, 0x08,/*块1482*/},\n        {\n\n                0xE4, 0x03, 0xFA, 0x26, 0x02, 0x24, 0xFB, 0x22, 0x26, 0xE2, 0x02, 0x01, 0x00, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*筷1483*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x88, 0x94, 0x92, 0x91, 0x92, 0x94, 0x88, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*侩1484*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x48, 0x44, 0x44, 0xFF, 0x44, 0x44, 0x7C, 0x40, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x03, 0x04, 0x08, 0x08,/*快1485*/},\n        {\n\n                0x06, 0xEA, 0x2A, 0x3E, 0x2A, 0xAB, 0x2A, 0x3E, 0x2A, 0xEA, 0x06, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x06, 0x08, 0x08, 0x09, 0x0C,/*宽1486*/},\n        {\n\n                0x82, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0x92, 0x0F, 0xC4, 0x14, 0x0C, 0x04, 0x02, 0x08, 0x0F, 0x00,\n                0x02, 0x0C, 0x06, 0x01, 0x06, 0x08,/*款1487*/},\n        {\n\n                0x00, 0xFF, 0x01, 0x05, 0x25, 0x25, 0xFD, 0x25, 0x25, 0x05, 0x01, 0x00, 0x0F, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x0A, 0x0A, 0x08,/*匡1488*/},\n        {\n\n                0x04, 0xFB, 0x0A, 0x2E, 0xAA, 0xAC, 0xEB, 0xAA, 0xAE, 0xAA, 0x0A, 0x00, 0x0F, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A,/*筐1489*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x42, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x42, 0x08, 0x08, 0x07, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*狂1490*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0x02, 0x4A, 0x4A, 0xFA, 0x4A, 0x4A, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x08, 0x0A, 0x0A, 0x0B, 0x0A, 0x0A,/*框1491*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFC, 0x04, 0x05, 0x06, 0x04, 0x04, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*矿1492*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x02, 0x4A, 0x4A, 0xFA, 0x4A, 0x4A, 0x0F, 0x04, 0x0F, 0x00, 0x0F,\n                0x08, 0x0A, 0x0A, 0x0B, 0x0A, 0x0A,/*眶1493*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x00, 0xFC, 0x04, 0x05, 0x06, 0x04, 0x04, 0x07, 0x02, 0x02, 0x03, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*旷1494*/},\n        {\n\n                0x04, 0x08, 0x00, 0x7E, 0x42, 0xC2, 0x42, 0xC2, 0x42, 0x7E, 0x00, 0x04, 0x02, 0x09, 0x04, 0x02,\n                0x01, 0x00, 0x07, 0x08, 0x08, 0x0E,/*况1495*/},\n        {\n\n                0x10, 0x12, 0xD2, 0xB2, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x07, 0x00,/*亏1496*/},\n        {\n\n                0x82, 0x72, 0x0F, 0xA2, 0x5A, 0x22, 0x1E, 0x22, 0x52, 0x8A, 0x82, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盔1497*/},\n        {\n\n                0xE0, 0x06, 0x04, 0xFC, 0x04, 0x17, 0x94, 0x94, 0x94, 0x96, 0xF0, 0x01, 0x08, 0x04, 0x03, 0x00,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*岿1498*/},\n        {\n\n                0x86, 0xAA, 0xF6, 0xA2, 0x02, 0xF3, 0x12, 0xD2, 0x16, 0xFA, 0x06, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x05, 0x02, 0x01, 0x06, 0x09, 0x0E,/*窥1499*/},\n        {\n\n                0x92, 0xAA, 0x4A, 0x6F, 0x5A, 0xC2, 0x4A, 0x57, 0x32, 0x4A, 0xA2, 0x00, 0x08, 0x09, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x08, 0x00,/*葵1500*/},\n        {\n\n                0x12, 0x92, 0xAA, 0xAA, 0xA6, 0xFB, 0xA6, 0xAA, 0xAA, 0x92, 0x12, 0x08, 0x08, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x08, 0x08,/*奎1501*/},\n        {\n\n                0x7C, 0x56, 0xFD, 0x54, 0xFC, 0x00, 0x52, 0x64, 0x40, 0xFF, 0x20, 0x08, 0x07, 0x00, 0x07, 0x0A,\n                0x0B, 0x08, 0x08, 0x08, 0x0B, 0x0C,/*魁1502*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x7C, 0x54, 0xF6, 0x5D, 0xD4, 0x7C, 0x00, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x0A, 0x0B, 0x0C,/*傀1503*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x20, 0xAE, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xAE, 0x00, 0x0F, 0x04, 0x00, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*馈1504*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x7C, 0x54, 0xF6, 0x5D, 0xD4, 0x7C, 0x00, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x0A, 0x0B, 0x0C,/*愧1505*/},\n        {\n\n                0x22, 0x44, 0x20, 0xAE, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xAE, 0x20, 0x04, 0x02, 0x00, 0x0B, 0x08,\n                0x04, 0x03, 0x04, 0x04, 0x0B, 0x00,/*溃1506*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFC, 0x24, 0x24, 0xFF, 0x24, 0x24, 0xFC, 0x04, 0x07, 0x02, 0x00, 0x03,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x03,/*坤1507*/},\n        {\n\n                0x00, 0xDF, 0x95, 0x95, 0x95, 0x15, 0xD5, 0x15, 0x15, 0x9F, 0x40, 0x00, 0x0F, 0x08, 0x04, 0x04,\n                0x00, 0x07, 0x09, 0x09, 0x08, 0x0E,/*昆1508*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xFE, 0x92, 0x52, 0xFE, 0x52, 0x92, 0xFE, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*捆1509*/},\n        {\n\n                0xFF, 0x01, 0x89, 0x49, 0x29, 0xFF, 0x29, 0x49, 0x89, 0x01, 0xFF, 0x0F, 0x04, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x04, 0x0F,/*困1510*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x92, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x91, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*括1511*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFC, 0x04, 0x05, 0x06, 0x04, 0x04, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*扩1512*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xBA, 0xAE, 0xBA, 0x0B, 0x02, 0xFA, 0x4A, 0xBA, 0x04, 0x03, 0x02, 0x0A, 0x0E,\n                0x03, 0x02, 0x00, 0x0F, 0x02, 0x01,/*廓1513*/},\n        {\n\n                0xF9, 0x4A, 0x90, 0x21, 0xA9, 0xA9, 0xF9, 0xA5, 0xA5, 0x21, 0xFF, 0x0F, 0x04, 0x02, 0x00, 0x07,\n                0x04, 0x04, 0x04, 0x07, 0x08, 0x0F,/*阔1514*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x00, 0x28, 0xC8, 0x09, 0x0A, 0xE8, 0x08, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x08, 0x09, 0x0C, 0x0B, 0x08, 0x08,/*垃1515*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x28, 0xC8, 0x09, 0x0A, 0xE8, 0x08, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x08, 0x09, 0x0C, 0x0B, 0x08, 0x08,/*拉1516*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x74, 0x54, 0xFF, 0x54, 0x74, 0xF8, 0x00, 0xFF, 0x03, 0x01, 0x03, 0x02, 0x01,\n                0x0F, 0x01, 0x02, 0x01, 0x08, 0x0F,/*喇1517*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x10, 0xD4, 0x5F, 0x54, 0x5F, 0xD4, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x05, 0x05, 0x05, 0x0F,/*蜡1518*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xD4, 0x5F, 0x54, 0x5F, 0xD4, 0x10, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*腊1519*/},\n        {\n\n                0x44, 0x55, 0xE6, 0x54, 0x00, 0x74, 0x54, 0xFF, 0x54, 0x54, 0x74, 0x00, 0x09, 0x07, 0x01, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*辣1520*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x88, 0xFF, 0x48, 0x00, 0xE8, 0x09, 0x0A, 0xE8, 0x03, 0x01, 0x03, 0x08, 0x0F,\n                0x00, 0x08, 0x09, 0x0C, 0x0B, 0x08,/*啦1521*/},\n        {\n\n                0x82, 0x92, 0xB2, 0xD7, 0x92, 0xFA, 0x92, 0xD7, 0xB2, 0x92, 0x82, 0x04, 0x04, 0x02, 0x02, 0x01,\n                0x0F, 0x01, 0x02, 0x02, 0x04, 0x04,/*莱1522*/},\n        {\n\n                0x40, 0x44, 0x54, 0x64, 0xC4, 0xFF, 0xC4, 0x64, 0x54, 0x44, 0x40, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*来1523*/},\n        {\n\n                0x74, 0x54, 0xFF, 0x54, 0x74, 0x08, 0xF4, 0x13, 0xDA, 0x16, 0xF0, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x08, 0x05, 0x02, 0x01, 0x02, 0x0D,/*赖1524*/},\n        {\n\n                0x02, 0x72, 0x07, 0x7A, 0x02, 0x22, 0x1A, 0x12, 0x37, 0x52, 0x12, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*蓝1525*/},\n        {\n\n                0x92, 0x8A, 0xBF, 0x8A, 0xD2, 0x80, 0x92, 0x8A, 0xBF, 0x8A, 0x92, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*婪1526*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0x89, 0x8E, 0x88, 0x8C, 0x8B, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*栏1527*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x89, 0x8E, 0x88, 0x8C, 0x8B, 0x00, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*拦1528*/},\n        {\n\n                0x04, 0x73, 0x06, 0x7A, 0x02, 0x24, 0x1B, 0x12, 0x36, 0x52, 0x12, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*篮1529*/},\n        {\n\n                0xF9, 0x02, 0xF4, 0x55, 0x15, 0xFF, 0x15, 0x55, 0xF5, 0x01, 0xFF, 0x0F, 0x00, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x08, 0x0F,/*阑1530*/},\n        {\n\n                0x00, 0x08, 0x89, 0x8E, 0x88, 0x88, 0x88, 0x8C, 0x8B, 0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*兰1531*/},\n        {\n\n                0x22, 0x44, 0xF9, 0x02, 0xF4, 0x55, 0xFF, 0x55, 0xF5, 0x01, 0xFF, 0x04, 0x02, 0x0F, 0x00, 0x05,\n                0x03, 0x0F, 0x03, 0x05, 0x08, 0x0F,/*澜1532*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFD, 0xF4, 0x55, 0xFF, 0x55, 0xF5, 0x01, 0xFF, 0x00, 0x0F, 0x04, 0x0F, 0x05,\n                0x03, 0x0F, 0x03, 0x05, 0x08, 0x0F,/*谰1533*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xEE, 0x20, 0xBF, 0x24, 0x23, 0xE6, 0x0A, 0x08, 0x0F, 0x00, 0x08, 0x05,\n                0x02, 0x01, 0x06, 0x08, 0x09, 0x0C,/*揽1534*/},\n        {\n\n                0x0E, 0xE0, 0x20, 0x3F, 0x20, 0xA8, 0x27, 0x22, 0x26, 0xEA, 0x02, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x06, 0x08, 0x08, 0x09, 0x0C,/*览1535*/},\n        {\n\n                0x30, 0xFF, 0x08, 0x74, 0x54, 0xFF, 0x54, 0x74, 0xF3, 0x1A, 0xF6, 0x00, 0x0F, 0x00, 0x02, 0x01,\n                0x0F, 0x01, 0x08, 0x05, 0x02, 0x0D,/*懒1536*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xEE, 0x20, 0xBF, 0x24, 0x23, 0xE6, 0x0A, 0x04, 0x04, 0x02, 0x08, 0x05,\n                0x02, 0x01, 0x06, 0x08, 0x09, 0x0C,/*缆1537*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0x89, 0x8E, 0x88, 0x8C, 0x8B, 0x00, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*烂1538*/},\n        {\n\n                0x22, 0x44, 0x00, 0x9E, 0x80, 0xBF, 0x88, 0x87, 0x94, 0xA4, 0x04, 0x04, 0x02, 0x08, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*滥1539*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x00, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x80, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*琅1540*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFD, 0x56, 0x7C, 0x00, 0xFE, 0x32, 0xCE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x05, 0x02, 0x04, 0x0F, 0x02, 0x01,/*榔1541*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x00, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x80, 0x01, 0x08, 0x08, 0x07, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*狼1542*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xFA, 0xAA, 0xAE, 0xFB, 0x02, 0xFA, 0x4A, 0xBA, 0x08, 0x07, 0x00, 0x0F, 0x04,\n                0x02, 0x04, 0x00, 0x0F, 0x02, 0x01,/*廊1543*/},\n        {\n\n                0x00, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0F, 0x04, 0x02, 0x01,\n                0x06, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郎1544*/},\n        {\n\n                0x00, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x0F, 0x04, 0x02, 0x01,\n                0x06, 0x08, 0x07, 0x00, 0x08, 0x0F,/*朗1545*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFC, 0x54, 0x55, 0xD6, 0x54, 0x54, 0x7C, 0x00, 0x04, 0x02, 0x01, 0x0F, 0x08,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*浪1546*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xB2, 0x97, 0xD2, 0x92, 0x92, 0x97, 0xB2, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*捞1547*/},\n        {\n\n                0x32, 0x92, 0x92, 0x97, 0xF2, 0x92, 0x92, 0x97, 0x92, 0x92, 0x32, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x07, 0x00,/*劳1548*/},\n        {\n\n                0x06, 0x42, 0x32, 0x22, 0x22, 0xFB, 0x22, 0x22, 0x22, 0x22, 0x06, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*牢1549*/},\n        {\n\n                0x20, 0x24, 0x24, 0xA4, 0xE4, 0x3F, 0x34, 0x2C, 0x24, 0xA2, 0x20, 0x04, 0x02, 0x01, 0x00, 0x07,\n                0x0A, 0x0A, 0x09, 0x09, 0x08, 0x0E,/*老1550*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x23, 0x24, 0xA4, 0x7F, 0x24, 0x34, 0xA8, 0x26, 0x00, 0x00, 0x0F, 0x02, 0x01,\n                0x07, 0x0A, 0x09, 0x09, 0x08, 0x0C,/*佬1551*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xA4, 0xE4, 0x3F, 0x34, 0xA8, 0xA6, 0x08, 0x05, 0x02, 0x05, 0x09,\n                0x00, 0x07, 0x09, 0x09, 0x08, 0x0C,/*姥1552*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x44, 0xAB, 0x92, 0x92, 0xAE, 0x40, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*酪1553*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*烙1554*/},\n        {\n\n                0x22, 0x44, 0x00, 0xB2, 0x92, 0x97, 0xF2, 0x92, 0x97, 0x92, 0xB2, 0x04, 0x02, 0x00, 0x08, 0x04,\n                0x02, 0x01, 0x00, 0x08, 0x08, 0x07,/*涝1555*/},\n        {\n\n                0x02, 0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x02, 0x08, 0xFF, 0x08, 0xF8, 0x02, 0x02, 0x02, 0x0F, 0x02,\n                0x02, 0x0A, 0x06, 0x09, 0x08, 0x07,/*勒1556*/},\n        {\n\n                0x00, 0x3E, 0xA2, 0x22, 0x22, 0xFA, 0x21, 0x21, 0xA1, 0x20, 0x00, 0x04, 0x02, 0x01, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x01, 0x06,/*乐1557*/},\n        {\n\n                0x0C, 0xA5, 0xAD, 0xAD, 0x85, 0xBF, 0x85, 0xAD, 0xAD, 0xA5, 0x0C, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*雷1558*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xCD, 0x55, 0x45, 0xDF, 0x45, 0x55, 0xCD, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*镭1559*/},\n        {\n\n                0x62, 0xAA, 0xEF, 0xAA, 0xAA, 0xFA, 0xAA, 0xAA, 0xEF, 0xAA, 0x62, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*蕾1560*/},\n        {\n\n                0x40, 0x51, 0xC9, 0x5D, 0x57, 0x15, 0x55, 0xD5, 0x5D, 0x41, 0x40, 0x02, 0x0F, 0x05, 0x05, 0x0F,\n                0x02, 0x01, 0x0F, 0x05, 0x05, 0x0F,/*磊1561*/},\n        {\n\n                0x00, 0x1F, 0x55, 0x75, 0xD5, 0x5F, 0x55, 0x35, 0x95, 0x1F, 0x00, 0x00, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x00,/*累1562*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xC0, 0x5F, 0xD5, 0x5F, 0xD5, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x05, 0x07, 0x05, 0x07, 0x05, 0x0F,/*儡1563*/},\n        {\n\n                0x60, 0x54, 0x4E, 0x65, 0xC4, 0x04, 0x64, 0x54, 0x4E, 0x64, 0xC0, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*垒1564*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xCD, 0x55, 0x45, 0xDF, 0x45, 0x55, 0xCD, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*擂1565*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x08, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*肋1566*/},\n        {\n\n                0x08, 0x48, 0x2A, 0x1C, 0x08, 0xBF, 0x08, 0x1C, 0x2A, 0x48, 0x08, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*类1567*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xFE, 0x92, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*泪1568*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0x28, 0x9A, 0x6A, 0x4F, 0x4A, 0xDA, 0x28, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*棱1569*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xAF, 0x29, 0xEF, 0xB9, 0xAF, 0xA9, 0xAF, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*楞1570*/},\n        {\n\n                0x04, 0x08, 0x00, 0x10, 0x48, 0x44, 0x53, 0x64, 0x48, 0xD0, 0x10, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x02, 0x04, 0x0A, 0x01, 0x00, 0x00,/*冷1571*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xFA, 0xAA, 0xAA, 0xFA, 0xAA, 0xAA, 0xFA, 0x02, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*厘1572*/},\n        {\n\n                0x48, 0x2A, 0x1A, 0x7E, 0x19, 0xA9, 0x00, 0x1E, 0x00, 0x40, 0x7F, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*梨1573*/},\n        {\n\n                0x48, 0x2A, 0x9A, 0x7E, 0x19, 0xA9, 0x00, 0x1E, 0x00, 0x40, 0x7F, 0x04, 0x06, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x04,/*犁1574*/},\n        {\n\n                0xA4, 0x95, 0x4D, 0x7F, 0x2D, 0x94, 0x23, 0x52, 0x4E, 0xA2, 0xBE, 0x00, 0x08, 0x05, 0x02, 0x08,\n                0x0F, 0x00, 0x02, 0x05, 0x08, 0x00,/*黎1575*/},\n        {\n\n                0x0C, 0xEB, 0x8A, 0xDE, 0xAA, 0xAC, 0xAB, 0xDA, 0x8E, 0xEA, 0x0A, 0x0E, 0x02, 0x0A, 0x0E, 0x0A,\n                0x0B, 0x0E, 0x0A, 0x02, 0x0A, 0x0E,/*篱1576*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x7F, 0x49, 0x49, 0xFF, 0x49, 0x49, 0x7F, 0x08, 0x08, 0x07, 0x08, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x09,/*狸1577*/},\n        {\n\n                0x82, 0xBA, 0xA2, 0xB6, 0xAA, 0xEB, 0xAA, 0xB6, 0xA2, 0xBA, 0x82, 0x0F, 0x00, 0x04, 0x06, 0x05,\n                0x04, 0x06, 0x0C, 0x00, 0x08, 0x0F,/*离1578*/},\n        {\n\n                0x22, 0x44, 0x82, 0xBA, 0xA2, 0xB6, 0xEB, 0xB6, 0xA2, 0xBA, 0x82, 0x04, 0x02, 0x0F, 0x00, 0x06,\n                0x05, 0x04, 0x06, 0x04, 0x08, 0x0F,/*漓1579*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x7F, 0x49, 0x49, 0xFF, 0x49, 0x49, 0x7F, 0x04, 0x07, 0x02, 0x08, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x09,/*理1580*/},\n        {\n\n                0x12, 0x12, 0x2A, 0x26, 0x22, 0xBF, 0x62, 0x26, 0x0A, 0x12, 0x12, 0x01, 0x01, 0x01, 0x09, 0x09,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*李1581*/},\n        {\n\n                0x00, 0x7F, 0x49, 0x49, 0x49, 0xFF, 0x49, 0x49, 0x49, 0x7F, 0x00, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*里1582*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0x7F, 0x49, 0xFF, 0x49, 0x7F, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x08, 0x09, 0x09, 0x0F, 0x09, 0x09,/*鲤1583*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0x80, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0F,/*礼1584*/},\n        {\n\n                0x42, 0x52, 0x52, 0xF7, 0x4A, 0x4A, 0x02, 0xF7, 0x02, 0xFA, 0x02, 0x04, 0x02, 0x01, 0x0F, 0x01,\n                0x02, 0x00, 0x03, 0x08, 0x0F, 0x00,/*莉1585*/},\n        {\n\n                0x02, 0x52, 0xD2, 0x37, 0x1A, 0x12, 0x12, 0xD7, 0x52, 0x32, 0x02, 0x09, 0x05, 0x03, 0x09, 0x0F,\n                0x00, 0x09, 0x07, 0x01, 0x09, 0x0F,/*荔1586*/},\n        {\n\n                0x04, 0xF4, 0x94, 0x94, 0x94, 0xFF, 0x94, 0x94, 0x94, 0xF4, 0x04, 0x08, 0x08, 0x05, 0x02, 0x03,\n                0x04, 0x04, 0x08, 0x08, 0x08, 0x08,/*吏1587*/},\n        {\n\n                0x81, 0xBD, 0xA5, 0xA5, 0xBF, 0xE5, 0xBF, 0xA5, 0xA5, 0xBD, 0x81, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*栗1588*/},\n        {\n\n                0x02, 0xFA, 0x4A, 0x8A, 0xFA, 0x02, 0xFA, 0x4A, 0x8A, 0xFA, 0x02, 0x00, 0x0F, 0x00, 0x08, 0x0F,\n                0x00, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*丽1589*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x12, 0x12, 0xF2, 0x92, 0x92, 0x92, 0x92, 0x02, 0x08, 0x07, 0x00, 0x08, 0x06,\n                0x01, 0x00, 0x08, 0x08, 0x07, 0x00,/*厉1590*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xFA, 0x4A, 0xCA, 0x02, 0x08, 0xFF, 0x08, 0xF8, 0x08, 0x07, 0x08, 0x07, 0x08,\n                0x0F, 0x08, 0x06, 0x09, 0x08, 0x07,/*励1591*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xBE, 0x22, 0xFA, 0x21, 0xA1, 0x20, 0x00, 0x07, 0x02, 0x07, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*砾1592*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x12, 0x12, 0xFE, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x08, 0x07, 0x08, 0x04, 0x03,\n                0x00, 0x08, 0x08, 0x08, 0x07, 0x00,/*历1593*/},\n        {\n\n                0x10, 0x92, 0x52, 0xFE, 0x51, 0x91, 0x10, 0xFC, 0x00, 0x00, 0xFF, 0x01, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x00, 0x01, 0x08, 0x08, 0x0F,/*利1594*/},\n        {\n\n                0x10, 0xFC, 0x83, 0xBD, 0xA5, 0xBF, 0xE5, 0xBF, 0xA5, 0xBD, 0x81, 0x00, 0x0F, 0x04, 0x04, 0x02,\n                0x01, 0x0F, 0x01, 0x02, 0x04, 0x04,/*傈1595*/},\n        {\n\n                0x10, 0xFC, 0x83, 0x62, 0x9E, 0x12, 0xF2, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x0F, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x09, 0x08, 0x0F,/*例1596*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x10, 0x92, 0xFE, 0x91, 0x10, 0xFC, 0x00, 0xFF, 0x00, 0x0F, 0x00, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x01, 0x08, 0x0F,/*俐1597*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x42, 0x52, 0xF2, 0x4B, 0x42, 0xE2, 0x02, 0xFA, 0x09, 0x04, 0x03, 0x02, 0x01,\n                0x0F, 0x01, 0x02, 0x03, 0x08, 0x0F,/*痢1598*/},\n        {\n\n                0x00, 0x08, 0x48, 0x88, 0x09, 0x0A, 0x08, 0x08, 0xE8, 0x08, 0x00, 0x08, 0x08, 0x08, 0x0B, 0x08,\n                0x08, 0x0C, 0x0B, 0x08, 0x08, 0x08,/*立1599*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x04, 0x28, 0xC8, 0x09, 0x0A, 0xE8, 0x08, 0x01, 0x00, 0x0F, 0x00, 0x09,\n                0x08, 0x09, 0x0C, 0x0B, 0x08, 0x08,/*粒1600*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x02, 0x22, 0x22, 0xFA, 0x22, 0x22, 0xE2, 0x04, 0x0A, 0x04, 0x03, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*沥1601*/},\n        {\n\n                0x08, 0x48, 0xAA, 0x2A, 0xAA, 0xFF, 0xAA, 0x2A, 0xBE, 0x48, 0x08, 0x04, 0x04, 0x02, 0x01, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*隶1602*/},\n        {\n\n                0x08, 0x08, 0x08, 0x88, 0x7F, 0x08, 0x08, 0x08, 0x08, 0xF8, 0x00, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x08, 0x08, 0x08, 0x07, 0x00,/*力1603*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xBA, 0xA2, 0xB6, 0xEB, 0xB6, 0xA2, 0xBA, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x00, 0x06, 0x05, 0x06, 0x08, 0x0F,/*璃1604*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x7F, 0x49, 0x49, 0xFF, 0x49, 0x49, 0x7F, 0x03, 0x01, 0x03, 0x08, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x09,/*哩1605*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xF2, 0x12, 0xFE, 0x12, 0xFE, 0x12, 0xF2, 0x02, 0x00, 0x0F, 0x00, 0x0F, 0x01,\n                0x00, 0x01, 0x00, 0x09, 0x0F, 0x00,/*俩1606*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x42, 0x49, 0x4A, 0xF8, 0x4A, 0x49, 0x40, 0x02, 0x03, 0x02, 0x0F, 0x09,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*联1607*/},\n        {\n\n                0x4A, 0xD2, 0x02, 0x17, 0x52, 0x72, 0x5A, 0xF7, 0x52, 0x52, 0x12, 0x08, 0x07, 0x08, 0x09, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x09,/*莲1608*/},\n        {\n\n                0x21, 0xE2, 0x00, 0x04, 0x34, 0x2C, 0x27, 0xF4, 0x24, 0x24, 0x04, 0x08, 0x07, 0x08, 0x09, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x09,/*连1609*/},\n        {\n\n                0x58, 0xF7, 0x54, 0xFE, 0x8A, 0xAA, 0xFE, 0xAB, 0xFA, 0xAE, 0xEA, 0x00, 0x07, 0x0A, 0x07, 0x08,\n                0x06, 0x0F, 0x02, 0x0F, 0x06, 0x0B,/*镰1610*/},\n        {\n\n                0x00, 0xFE, 0x8A, 0xAA, 0xAE, 0xFA, 0xAB, 0xFA, 0xAE, 0xEA, 0x8A, 0x08, 0x07, 0x08, 0x0A, 0x06,\n                0x0F, 0x02, 0x0F, 0x06, 0x0B, 0x08,/*廉1611*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x14, 0x48, 0x44, 0x53, 0x64, 0x48, 0xD0, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x02, 0x04, 0x0A, 0x01, 0x00, 0x00,/*怜1612*/},\n        {\n\n                0x22, 0x44, 0x11, 0xF2, 0x00, 0x34, 0x2C, 0xF7, 0x24, 0x24, 0x00, 0x04, 0x0A, 0x04, 0x03, 0x04,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*涟1613*/},\n        {\n\n                0x1C, 0xC4, 0x54, 0x4C, 0x45, 0xF6, 0x44, 0x4C, 0x54, 0xC4, 0x1C, 0x00, 0x07, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x04, 0x07, 0x00,/*帘1614*/},\n        {\n\n                0x90, 0x28, 0x64, 0xA3, 0x24, 0xA8, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x08, 0x0B, 0x08, 0x05, 0x06,\n                0x05, 0x08, 0x05, 0x02, 0x05, 0x08,/*敛1615*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x08, 0x07, 0x08, 0x0F, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*脸1616*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x11, 0xF2, 0x00, 0x34, 0x2C, 0xF7, 0x24, 0x00, 0x0F, 0x04, 0x08, 0x04,\n                0x03, 0x04, 0x09, 0x09, 0x0F, 0x09,/*链1617*/},\n        {\n\n                0x44, 0x34, 0x04, 0x7C, 0x05, 0x06, 0x04, 0x7C, 0x04, 0x14, 0x64, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*恋1618*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x14, 0x74, 0x5C, 0xF7, 0x44, 0x44, 0x44, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x03, 0x08, 0x0F, 0x00, 0x01, 0x06,/*炼1619*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x14, 0x74, 0x5C, 0xF7, 0x44, 0x44, 0x44, 0x04, 0x04, 0x02, 0x02, 0x04,\n                0x03, 0x08, 0x0F, 0x00, 0x01, 0x06,/*练1620*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x24, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x80, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*粮1621*/},\n        {\n\n                0x04, 0x08, 0x04, 0xF4, 0x94, 0x95, 0x96, 0x94, 0x94, 0xF4, 0x04, 0x02, 0x01, 0x04, 0x02, 0x00,\n                0x08, 0x0F, 0x00, 0x00, 0x02, 0x04,/*凉1622*/},\n        {\n\n                0xC4, 0xA9, 0x82, 0x88, 0xA5, 0xD1, 0x8F, 0xA1, 0xBF, 0x84, 0x88, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*梁1623*/},\n        {\n\n                0x44, 0x29, 0x42, 0x88, 0x25, 0xD1, 0x0F, 0xA1, 0x7F, 0x04, 0x08, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*粱1624*/},\n        {\n\n                0x00, 0xFC, 0x54, 0x54, 0x55, 0xD6, 0x54, 0x54, 0x54, 0x7C, 0x80, 0x00, 0x0F, 0x08, 0x08, 0x04,\n                0x00, 0x01, 0x02, 0x06, 0x09, 0x08,/*良1625*/},\n        {\n\n                0xF2, 0x12, 0x92, 0x7E, 0x92, 0x12, 0x92, 0x7E, 0x92, 0x12, 0xF2, 0x0F, 0x01, 0x00, 0x00, 0x02,\n                0x01, 0x00, 0x00, 0x00, 0x09, 0x0F,/*两1626*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0xF2, 0x12, 0xFE, 0x12, 0xFE, 0x12, 0xF2, 0x01, 0x01, 0x0F, 0x00, 0x0F,\n                0x01, 0x00, 0x01, 0x00, 0x09, 0x0F,/*辆1627*/},\n        {\n\n                0x08, 0xFF, 0xA9, 0xA9, 0xA9, 0xFB, 0xAD, 0xA9, 0xA9, 0xFF, 0x08, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*量1628*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0x04, 0xF4, 0x95, 0x96, 0x94, 0xF4, 0x04, 0x07, 0x02, 0x07, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*晾1629*/},\n        {\n\n                0x82, 0x82, 0xBA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBA, 0x82, 0x82, 0x09, 0x08, 0x06, 0x02, 0x02,\n                0x02, 0x02, 0x06, 0x08, 0x08, 0x0D,/*亮1630*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x04, 0xF4, 0x95, 0x96, 0x94, 0xF4, 0x04, 0x00, 0x00, 0x07, 0x02, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*谅1631*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x2A, 0xF2, 0xAA, 0xA7, 0xAA, 0xF2, 0x2A, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x07, 0x0A, 0x0E, 0x02, 0x07, 0x08,/*撩1632*/},\n        {\n\n                0x01, 0xFF, 0x49, 0xFF, 0x01, 0xFC, 0xE2, 0x01, 0xFE, 0x02, 0xFE, 0x02, 0x03, 0x02, 0x0F, 0x01,\n                0x08, 0x07, 0x00, 0x0F, 0x02, 0x03,/*聊1633*/},\n        {\n\n                0x10, 0xFC, 0x2B, 0x12, 0xFA, 0x56, 0x53, 0x56, 0xFA, 0x12, 0x2A, 0x00, 0x0F, 0x00, 0x08, 0x05,\n                0x09, 0x0F, 0x01, 0x05, 0x08, 0x00,/*僚1634*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x14, 0x15, 0x16, 0x94, 0x54, 0x34, 0x04, 0x09, 0x04, 0x03, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*疗1635*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x10, 0x2A, 0xF2, 0xAA, 0xA7, 0xAA, 0xF2, 0x2A, 0x08, 0x06, 0x01, 0x02, 0x08,\n                0x07, 0x0A, 0x0E, 0x02, 0x07, 0x08,/*燎1636*/},\n        {\n\n                0x06, 0x5A, 0x2A, 0x8A, 0xBA, 0x43, 0xDA, 0xAA, 0x0A, 0x7A, 0x06, 0x01, 0x09, 0x09, 0x0A, 0x0A,\n                0x0A, 0x05, 0x04, 0x05, 0x01, 0x01,/*寥1637*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x02, 0x02, 0x02, 0xF2, 0x12, 0x0A, 0x06, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x08, 0x0A, 0x0B, 0x08, 0x08, 0x08,/*辽1638*/},\n        {\n\n                0x11, 0x22, 0x28, 0x12, 0xFA, 0x56, 0x53, 0x56, 0xFA, 0x12, 0x2A, 0x04, 0x02, 0x09, 0x04, 0x01,\n                0x09, 0x0F, 0x01, 0x01, 0x04, 0x08,/*潦1639*/},\n        {\n\n                0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0xE2, 0x12, 0x0A, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,\n                0x08, 0x0F, 0x00, 0x00, 0x00, 0x00,/*了1640*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x88, 0x5F, 0xF5, 0x55, 0x5F, 0x55, 0xD5, 0x5F, 0x01, 0x09, 0x0F, 0x00, 0x02,\n                0x0E, 0x0B, 0x0A, 0x0B, 0x0E, 0x02,/*撂1641*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x2A, 0xF2, 0xAA, 0xA7, 0xAA, 0xF2, 0x2A, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x07, 0x0A, 0x0E, 0x02, 0x07, 0x08,/*镣1642*/},\n        {\n\n                0x00, 0xFE, 0x82, 0x96, 0x4A, 0x5E, 0xA3, 0x56, 0x4A, 0x9E, 0x82, 0x08, 0x07, 0x00, 0x08, 0x09,\n                0x09, 0x0A, 0x05, 0x04, 0x02, 0x00,/*廖1643*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x24, 0x80, 0x92, 0xA4, 0x80, 0xFF, 0x40, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x00, 0x00, 0x00, 0x0F, 0x00,/*料1644*/},\n        {\n\n                0x42, 0x22, 0x5E, 0x92, 0x12, 0xF2, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x00, 0x01, 0x08, 0x08, 0x0F,/*列1645*/},\n        {\n\n                0xA8, 0xA5, 0xAF, 0x95, 0x95, 0xCD, 0x80, 0x8E, 0x80, 0xA0, 0xBF, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*裂1646*/},\n        {\n\n                0x22, 0x12, 0xAE, 0x4A, 0x2A, 0x1A, 0x00, 0x7C, 0x00, 0xFF, 0x00, 0x09, 0x05, 0x00, 0x04, 0x08,\n                0x00, 0x04, 0x08, 0x01, 0x05, 0x08,/*烈1647*/},\n        {\n\n                0x28, 0xA4, 0xA2, 0x90, 0xD0, 0x9F, 0x88, 0x88, 0x82, 0x84, 0x08, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x00, 0x08, 0x08, 0x07, 0x00,/*劣1648*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x10, 0xD4, 0x5F, 0x54, 0x54, 0x5F, 0xD4, 0x10, 0x08, 0x08, 0x07, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*猎1649*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x88, 0x48, 0xFF, 0xA8, 0x48, 0xFF, 0x48, 0x88, 0x04, 0x07, 0x02, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x0F, 0x00, 0x00,/*琳1650*/},\n        {\n\n                0x08, 0x88, 0x68, 0xFF, 0x48, 0x80, 0x68, 0xFF, 0x68, 0x88, 0x08, 0x02, 0x01, 0x00, 0x0F, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*林1651*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x95, 0x6E, 0xC4, 0x1F, 0x44, 0xEE, 0x55, 0x00, 0x07, 0x02, 0x07, 0x09,\n                0x06, 0x01, 0x03, 0x02, 0x0F, 0x02,/*磷1652*/},\n        {\n\n                0x8C, 0xA5, 0xED, 0xAD, 0x85, 0x3F, 0x85, 0xAD, 0xED, 0xA5, 0x8C, 0x04, 0x02, 0x0F, 0x02, 0x04,\n                0x00, 0x04, 0x02, 0x0F, 0x02, 0x04,/*霖1653*/},\n        {\n\n                0xFC, 0x00, 0xFF, 0x10, 0xC8, 0x47, 0x44, 0xCC, 0x54, 0x44, 0xC4, 0x01, 0x00, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*临1654*/},\n        {\n\n                0x10, 0x48, 0x44, 0x53, 0x64, 0xC8, 0x10, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x00, 0x02, 0x04, 0x0B,\n                0x00, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邻1655*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0x95, 0x6E, 0xC4, 0x1F, 0x44, 0xEE, 0x55, 0x09, 0x09, 0x05, 0x05, 0x09,\n                0x06, 0x01, 0x03, 0x02, 0x0F, 0x02,/*鳞1656*/},\n        {\n\n                0x11, 0x22, 0x88, 0x68, 0xFF, 0x48, 0x00, 0xC8, 0xFF, 0x48, 0x88, 0x04, 0x02, 0x00, 0x00, 0x0F,\n                0x00, 0x01, 0x00, 0x0F, 0x00, 0x00,/*淋1657*/},\n        {\n\n                0x04, 0x08, 0x02, 0xFA, 0x8A, 0xEA, 0xAB, 0xEA, 0x8A, 0xFA, 0x02, 0x02, 0x01, 0x0A, 0x06, 0x02,\n                0x0A, 0x0E, 0x02, 0x02, 0x06, 0x0A,/*凛1658*/},\n        {\n\n                0x08, 0x84, 0xBE, 0x81, 0x88, 0xAA, 0xAA, 0xBE, 0xA9, 0xA9, 0x08, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*赁1659*/},\n        {\n\n                0x84, 0x84, 0x4C, 0x54, 0x25, 0x26, 0x24, 0x54, 0x4C, 0x84, 0x84, 0x00, 0x00, 0x0F, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x0F, 0x00, 0x00,/*吝1660*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0x48, 0x44, 0x53, 0x64, 0xC8, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x02, 0x04, 0x0B, 0x00, 0x00,/*拎1661*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x10, 0x48, 0x44, 0x53, 0x64, 0xC8, 0x10, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x00, 0x02, 0x04, 0x0B, 0x00, 0x00,/*玲1662*/},\n        {\n\n                0x22, 0xAA, 0x6A, 0x2F, 0xAA, 0x3E, 0x2A, 0x2F, 0x6A, 0xAA, 0x22, 0x09, 0x08, 0x0A, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x08, 0x08, 0x09,/*菱1663*/},\n        {\n\n                0x0C, 0x25, 0xAD, 0xAD, 0x45, 0xBF, 0x45, 0xAD, 0xAD, 0x25, 0x0C, 0x01, 0x01, 0x00, 0x05, 0x05,\n                0x05, 0x0B, 0x09, 0x00, 0x01, 0x01,/*零1664*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x10, 0x4C, 0x53, 0x64, 0xC8, 0x10, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x00, 0x02, 0x04, 0x0B, 0x00, 0x00,/*龄1665*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x10, 0x48, 0x44, 0x53, 0x64, 0xC8, 0x10, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x02, 0x04, 0x0B, 0x00, 0x00,/*铃1666*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x13, 0x48, 0x44, 0x53, 0x64, 0x48, 0xD0, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x02, 0x04, 0x0A, 0x01, 0x00, 0x00,/*伶1667*/},\n        {\n\n                0x89, 0xAA, 0xF8, 0xAA, 0x11, 0x48, 0x44, 0x53, 0x64, 0xC8, 0x10, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x02, 0x04, 0x0B, 0x00, 0x00,/*羚1668*/},\n        {\n\n                0x02, 0x04, 0x88, 0x2A, 0x9A, 0x6A, 0x4F, 0x4A, 0xDA, 0x2A, 0x08, 0x02, 0x01, 0x08, 0x09, 0x04,\n                0x05, 0x02, 0x05, 0x04, 0x08, 0x08,/*凌1669*/},\n        {\n\n                0x00, 0x22, 0xAA, 0x2A, 0x2A, 0xEA, 0x2A, 0x2A, 0x2A, 0xBE, 0x00, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x05, 0x08, 0x08,/*灵1670*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x00, 0x28, 0x9A, 0x6A, 0x4F, 0x4A, 0xDA, 0x28, 0x0F, 0x02, 0x01, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*陵1671*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x48, 0x44, 0x53, 0x64, 0xC8, 0x10, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x02, 0x04, 0x0B, 0x00, 0x00,/*岭1672*/},\n        {\n\n                0x48, 0x44, 0x53, 0x64, 0xC8, 0x10, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x00, 0x02, 0x04, 0x0B, 0x00,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*领1673*/},\n        {\n\n                0x00, 0x80, 0x9F, 0x91, 0xF1, 0x91, 0x91, 0x91, 0x91, 0x9F, 0x80, 0x00, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*另1674*/},\n        {\n\n                0x10, 0x50, 0x48, 0x44, 0x52, 0x61, 0x42, 0x44, 0xC8, 0x10, 0x10, 0x00, 0x00, 0x02, 0x02, 0x04,\n                0x04, 0x0A, 0x09, 0x00, 0x00, 0x00,/*令1675*/},\n        {\n\n                0x22, 0x44, 0x3E, 0xD2, 0x49, 0x50, 0xE2, 0x5E, 0x42, 0xD2, 0x1E, 0x04, 0x02, 0x00, 0x0F, 0x05,\n                0x05, 0x07, 0x05, 0x05, 0x0F, 0x00,/*溜1676*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xA4, 0x34, 0xAD, 0x26, 0xA4, 0x34, 0x64, 0x04, 0x07, 0x02, 0x08, 0x07,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0C,/*琉1677*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0xDE, 0x52, 0x69, 0xD2, 0x4E, 0x52, 0xDE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*榴1678*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xA4, 0x34, 0xAD, 0x26, 0xB4, 0x64, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x07, 0x00, 0x07, 0x00, 0x0F, 0x08,/*硫1679*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0xDE, 0x52, 0x69, 0xD2, 0x4E, 0x52, 0xDE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*馏1680*/},\n        {\n\n                0x1E, 0xD2, 0x56, 0x49, 0x51, 0xC0, 0x52, 0x4E, 0x42, 0xD2, 0x1E, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x07, 0x05, 0x05, 0x05, 0x0F, 0x00,/*留1681*/},\n        {\n\n                0x08, 0x48, 0x89, 0x0A, 0xF8, 0x08, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x0C, 0x00, 0x01, 0x08, 0x08, 0x0F,/*刘1682*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xBA, 0xAA, 0x97, 0xAA, 0x9A, 0xAA, 0xBA, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0F,/*瘤1683*/},\n        {\n\n                0x22, 0x44, 0x00, 0x24, 0xB4, 0x2C, 0xA5, 0x26, 0xA4, 0x34, 0x64, 0x04, 0x02, 0x08, 0x04, 0x03,\n                0x00, 0x0F, 0x00, 0x07, 0x08, 0x0E,/*流1684*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0x82, 0xFD, 0x00, 0xFE, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x04, 0x03, 0x00, 0x0F, 0x01, 0x01,/*柳1685*/},\n        {\n\n                0x10, 0x10, 0x10, 0xD0, 0x11, 0x16, 0x10, 0x50, 0x90, 0x10, 0x10, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x03, 0x0C,/*六1686*/},\n        {\n\n                0x08, 0x08, 0x08, 0xE8, 0x1F, 0x08, 0xF8, 0x09, 0x8A, 0x48, 0x08, 0x08, 0x04, 0x03, 0x00, 0x08,\n                0x04, 0x07, 0x09, 0x08, 0x08, 0x0E,/*龙1687*/},\n        {\n\n                0x52, 0x52, 0xCA, 0x56, 0x53, 0x52, 0x4E, 0x5B, 0xD6, 0x52, 0x5A, 0x04, 0x04, 0x07, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0F, 0x02, 0x02,/*聋1688*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0x08, 0xFF, 0x08, 0xF8, 0x89, 0x4A, 0x28, 0x03, 0x01, 0x0B, 0x04, 0x03,\n                0x04, 0x02, 0x07, 0x08, 0x08, 0x0E,/*咙1689*/},\n        {\n\n                0x24, 0x23, 0x22, 0xA6, 0x72, 0xA4, 0x2B, 0x32, 0xA6, 0x22, 0x22, 0x08, 0x04, 0x02, 0x09, 0x08,\n                0x07, 0x0A, 0x09, 0x08, 0x08, 0x0C,/*笼1690*/},\n        {\n\n                0x06, 0xF2, 0x9A, 0x76, 0x82, 0xA3, 0x5A, 0x56, 0x5A, 0xB2, 0x86, 0x00, 0x0F, 0x04, 0x03, 0x0C,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*窿1691*/},\n        {\n\n                0xFE, 0x12, 0xEE, 0x00, 0xD4, 0x96, 0xAB, 0xEA, 0xAA, 0x96, 0x90, 0x0F, 0x01, 0x00, 0x09, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*隆1692*/},\n        {\n\n                0x84, 0x44, 0x24, 0x9C, 0x87, 0x44, 0x7C, 0xA5, 0x96, 0x84, 0xC4, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*垄1693*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x08, 0xFF, 0x08, 0xF9, 0x8A, 0x48, 0x00, 0x08, 0x0F, 0x08, 0x04,\n                0x03, 0x04, 0x02, 0x07, 0x08, 0x0E,/*拢1694*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x08, 0x08, 0xFF, 0x08, 0xF8, 0x89, 0x4A, 0x28, 0x0F, 0x02, 0x09, 0x04, 0x03,\n                0x04, 0x02, 0x07, 0x08, 0x08, 0x0E,/*陇1695*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xAA, 0x9C, 0xC8, 0xBF, 0x88, 0x9C, 0xAA, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0A, 0x05, 0x04, 0x04, 0x0B, 0x08,/*楼1696*/},\n        {\n\n                0x84, 0xA4, 0x95, 0x8E, 0xC4, 0x9F, 0x84, 0x8E, 0x95, 0xA4, 0x84, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*娄1697*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xAA, 0x9C, 0xC8, 0xBF, 0x88, 0x9C, 0xAA, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x0A, 0x05, 0x04, 0x04, 0x0B, 0x08,/*搂1698*/},\n        {\n\n                0x14, 0x53, 0x56, 0x3A, 0x92, 0x7C, 0x13, 0x3A, 0x56, 0x52, 0x12, 0x01, 0x09, 0x09, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*篓1699*/},\n        {\n\n                0x22, 0x44, 0xFF, 0x15, 0xD5, 0x55, 0x55, 0xF5, 0x55, 0x55, 0xD7, 0x04, 0x0A, 0x07, 0x00, 0x0F,\n                0x05, 0x00, 0x0F, 0x05, 0x08, 0x0F,/*漏1700*/},\n        {\n\n                0xFF, 0x31, 0xCF, 0x00, 0xF8, 0x01, 0xF9, 0x49, 0x3F, 0x49, 0xF9, 0x0F, 0x02, 0x01, 0x00, 0x0F,\n                0x08, 0x0B, 0x08, 0x08, 0x0A, 0x0B,/*陋1701*/},\n        {\n\n                0x02, 0xF2, 0x97, 0x92, 0x96, 0x9A, 0x92, 0x92, 0x97, 0xF2, 0x02, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x01, 0x00,/*芦1702*/},\n        {\n\n                0x00, 0xF0, 0x90, 0x90, 0x90, 0x9F, 0x92, 0x92, 0x92, 0xF2, 0x02, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x01, 0x00,/*卢1703*/},\n        {\n\n                0x00, 0xF0, 0x9F, 0x94, 0xF4, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x08, 0x07, 0x00, 0x00, 0x01,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颅1704*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xF2, 0x92, 0x96, 0x9B, 0x92, 0x92, 0x92, 0xF2, 0x08, 0x07, 0x08, 0x07, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x01,/*庐1705*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xFC, 0x44, 0x45, 0x46, 0x44, 0xFC, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*炉1706*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xFC, 0x24, 0x24, 0xBF, 0x55, 0x55, 0x6C, 0x00, 0x08, 0x0F, 0x08, 0x07,\n                0x09, 0x05, 0x03, 0x09, 0x09, 0x07,/*掳1707*/},\n        {\n\n                0x00, 0xF8, 0x08, 0x18, 0xA8, 0x4F, 0xAA, 0x1A, 0x0A, 0xFA, 0x02, 0x00, 0x0F, 0x04, 0x05, 0x04,\n                0x04, 0x04, 0x05, 0x04, 0x0F, 0x00,/*卤1708*/},\n        {\n\n                0x00, 0xFC, 0x24, 0x24, 0x24, 0xBF, 0x55, 0x55, 0x55, 0x45, 0x6C, 0x08, 0x07, 0x00, 0x09, 0x05,\n                0x03, 0x01, 0x09, 0x09, 0x07, 0x00,/*虏1709*/},\n        {\n\n                0x88, 0xFC, 0xAB, 0xAA, 0xAA, 0xFA, 0xAA, 0xAE, 0xA8, 0xF8, 0x80, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*鲁1710*/},\n        {\n\n                0x0A, 0xE6, 0xBF, 0xA6, 0xEA, 0xB0, 0xAA, 0xE6, 0xBF, 0xA6, 0x2A, 0x08, 0x07, 0x02, 0x0E, 0x0B,\n                0x0A, 0x02, 0x0F, 0x0A, 0x0B, 0x0C,/*麓1711*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x50, 0x95, 0x15, 0xF5, 0x15, 0x9F, 0x50, 0x00, 0x0F, 0x04, 0x0F, 0x04,\n                0x02, 0x09, 0x0F, 0x01, 0x02, 0x04,/*碌1712*/},\n        {\n\n                0x0C, 0xE5, 0xAD, 0xA5, 0xE5, 0x0F, 0x45, 0xB5, 0xAD, 0x65, 0x0C, 0x08, 0x0E, 0x08, 0x0F, 0x0A,\n                0x01, 0x0F, 0x0A, 0x0A, 0x0F, 0x01,/*露1713*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*路1714*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x44, 0xAB, 0x92, 0x92, 0xAE, 0x40, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*赂1715*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xAA, 0x3E, 0x2A, 0x2B, 0xBE, 0x2A, 0x2A, 0xBA, 0x08, 0x07, 0x00, 0x0F, 0x09,\n                0x05, 0x00, 0x07, 0x0A, 0x09, 0x0C,/*鹿1716*/},\n        {\n\n                0x22, 0x44, 0x9E, 0x12, 0xF2, 0x9E, 0x44, 0xAB, 0x92, 0xAE, 0x40, 0x04, 0x0A, 0x0F, 0x08, 0x07,\n                0x04, 0x00, 0x0F, 0x04, 0x0F, 0x00,/*潞1717*/},\n        {\n\n                0x08, 0x89, 0xEA, 0x98, 0x50, 0x95, 0x15, 0xF5, 0x15, 0x9F, 0x50, 0x01, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x09, 0x0F, 0x01, 0x02, 0x04,/*禄1718*/},\n        {\n\n                0x10, 0x51, 0x95, 0x15, 0x95, 0xF5, 0x95, 0x15, 0x9F, 0x50, 0x10, 0x04, 0x04, 0x02, 0x01, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*录1719*/},\n        {\n\n                0xFE, 0x12, 0xEE, 0x20, 0xA4, 0x24, 0x24, 0xFF, 0x24, 0x24, 0xA4, 0x0F, 0x01, 0x00, 0x00, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*陆1720*/},\n        {\n\n                0x8B, 0x45, 0xAF, 0x5A, 0xA5, 0x5F, 0x10, 0xFF, 0x08, 0xE9, 0x0A, 0x00, 0x0A, 0x0A, 0x09, 0x04,\n                0x0A, 0x04, 0x02, 0x03, 0x04, 0x0E,/*戮1721*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x00, 0xFC, 0x45, 0x46, 0x44, 0xFC, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x08, 0x07, 0x00, 0x00, 0x00, 0x00,/*驴1722*/},\n        {\n\n                0x00, 0xC0, 0x5F, 0x51, 0x51, 0x51, 0x51, 0x51, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*吕1723*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0xC0, 0x5F, 0x51, 0x51, 0x51, 0x5F, 0xC0, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*铝1724*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xC0, 0x5F, 0x51, 0x51, 0x51, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*侣1725*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x10, 0xEC, 0x27, 0xE4, 0x24, 0x94, 0x54, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x04, 0x00, 0x03, 0x04, 0x08,/*旅1726*/},\n        {\n\n                0x00, 0xFF, 0x25, 0x95, 0x4D, 0x15, 0xFD, 0x55, 0x55, 0xF5, 0x17, 0x08, 0x07, 0x01, 0x0F, 0x00,\n                0x0A, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*履1727*/},\n        {\n\n                0x00, 0xFF, 0x25, 0xAD, 0x75, 0xA5, 0x7D, 0x25, 0x75, 0xAD, 0x27, 0x08, 0x07, 0x09, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x09,/*屡1728*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xAA, 0x9C, 0xC8, 0xBF, 0x88, 0x9C, 0xAA, 0x04, 0x04, 0x02, 0x00, 0x08,\n                0x0A, 0x05, 0x04, 0x04, 0x0B, 0x08,/*缕1729*/},\n        {\n\n                0x00, 0xF8, 0x48, 0x48, 0x48, 0x7F, 0xAA, 0xAA, 0xAA, 0x8A, 0xD8, 0x08, 0x07, 0x08, 0x06, 0x00,\n                0x06, 0x09, 0x0A, 0x0C, 0x02, 0x0C,/*虑1730*/},\n        {\n\n                0x04, 0x52, 0x55, 0x55, 0x55, 0x55, 0xF5, 0x15, 0xF5, 0x01, 0x00, 0x01, 0x0B, 0x05, 0x09, 0x0F,\n                0x01, 0x05, 0x0B, 0x03, 0x04, 0x0E,/*氯1731*/},\n        {\n\n                0x24, 0xF2, 0x09, 0x08, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xBE, 0x08, 0x00, 0x0F, 0x00, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*律1732*/},\n        {\n\n                0x02, 0x8A, 0x52, 0x9A, 0xD6, 0xB3, 0xD2, 0x8A, 0x52, 0x8A, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*率1733*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFC, 0x24, 0x24, 0xBF, 0x55, 0x55, 0x45, 0x6C, 0x04, 0x02, 0x08, 0x07, 0x04,\n                0x02, 0x0C, 0x09, 0x0C, 0x02, 0x04,/*滤1734*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x50, 0x95, 0x15, 0xF5, 0x15, 0x9F, 0x50, 0x04, 0x04, 0x02, 0x00, 0x04,\n                0x02, 0x09, 0x0F, 0x01, 0x02, 0x04,/*绿1735*/},\n        {\n\n                0x44, 0x34, 0x04, 0x7C, 0x05, 0x86, 0x04, 0x7C, 0x04, 0x14, 0x64, 0x00, 0x0F, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x00,/*峦1736*/},\n        {\n\n                0x12, 0x8A, 0xA2, 0xAE, 0xA2, 0xE3, 0xA2, 0xAE, 0x92, 0x8A, 0x12, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*挛1737*/},\n        {\n\n                0x12, 0x0A, 0x42, 0x5E, 0x42, 0x43, 0xC2, 0x5E, 0x02, 0x0A, 0x12, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*孪1738*/},\n        {\n\n                0x22, 0x44, 0x80, 0x92, 0x8A, 0xBE, 0xC3, 0x82, 0xBE, 0x8A, 0x92, 0x04, 0x02, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x01, 0x02, 0x04,/*滦1739*/},\n        {\n\n                0xFE, 0x0A, 0x92, 0x81, 0xF9, 0x00, 0xFE, 0x12, 0x22, 0x02, 0xFE, 0x01, 0x09, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x00, 0x01, 0x01,/*卵1740*/},\n        {\n\n                0x10, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x10, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x0F, 0x00, 0x07, 0x08, 0x08, 0x0E,/*乱1741*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x04, 0xF4, 0x95, 0x96, 0x94, 0xF4, 0x04, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*掠1742*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x44, 0xAB, 0x92, 0x92, 0xAE, 0x40, 0x07, 0x02, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*略1743*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0xE8, 0x04, 0x83, 0x84, 0x48, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x07, 0x09, 0x08, 0x08, 0x08, 0x0E,/*抡1744*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x10, 0xE8, 0x04, 0x83, 0x84, 0x48, 0x10, 0x02, 0x02, 0x0F, 0x01, 0x00,\n                0x07, 0x09, 0x08, 0x08, 0x08, 0x0E,/*轮1745*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x10, 0xE8, 0x04, 0x83, 0x84, 0x48, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x09, 0x08, 0x08, 0x08, 0x0E,/*伦1746*/},\n        {\n\n                0x10, 0x10, 0xE8, 0x04, 0x02, 0x81, 0x82, 0x44, 0x48, 0x10, 0x10, 0x00, 0x00, 0x07, 0x09, 0x09,\n                0x08, 0x08, 0x08, 0x08, 0x0E, 0x00,/*仑1747*/},\n        {\n\n                0x10, 0x21, 0x02, 0x10, 0xE8, 0x04, 0x83, 0x84, 0x48, 0x10, 0x10, 0x04, 0x02, 0x01, 0x00, 0x07,\n                0x09, 0x08, 0x08, 0x08, 0x0E, 0x00,/*沦1748*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0xE8, 0x04, 0x83, 0x84, 0x48, 0x10, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x07, 0x09, 0x08, 0x08, 0x08, 0x0E,/*纶1749*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x10, 0xE8, 0x04, 0x83, 0x84, 0x48, 0x10, 0x10, 0x00, 0x0F, 0x04, 0x00, 0x07,\n                0x09, 0x08, 0x08, 0x08, 0x0E, 0x00,/*论1750*/},\n        {\n\n                0x02, 0x3A, 0xAA, 0xEF, 0xBA, 0xAA, 0xBA, 0xAF, 0xAA, 0xBA, 0x02, 0x09, 0x09, 0x08, 0x05, 0x06,\n                0x04, 0x02, 0x02, 0x01, 0x00, 0x00,/*萝1751*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x5F, 0xF5, 0x5F, 0x35, 0x9F, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x05, 0x09, 0x0F, 0x05, 0x09,/*螺1752*/},\n        {\n\n                0x00, 0x0F, 0x89, 0x79, 0x4F, 0x49, 0x49, 0x4F, 0x49, 0xC9, 0x0F, 0x08, 0x09, 0x08, 0x09, 0x06,\n                0x04, 0x02, 0x02, 0x01, 0x00, 0x00,/*罗1753*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x4F, 0x49, 0xBF, 0x29, 0x2F, 0xA9, 0x6F, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x0A, 0x0A, 0x09, 0x09, 0x08, 0x08,/*逻1754*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x1E, 0x92, 0x7E, 0x52, 0x5E, 0x52, 0xDE, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x08, 0x05, 0x06, 0x02, 0x01, 0x00,/*锣1755*/},\n        {\n\n                0x04, 0x3B, 0xAA, 0xEE, 0xBA, 0xAC, 0xBB, 0xAA, 0xAE, 0xBA, 0x02, 0x09, 0x09, 0x08, 0x05, 0x06,\n                0x04, 0x02, 0x02, 0x01, 0x00, 0x00,/*箩1756*/},\n        {\n\n                0x3D, 0x21, 0xBF, 0xE0, 0x00, 0x5F, 0x75, 0xD5, 0x5F, 0x35, 0x9F, 0x01, 0x09, 0x08, 0x07, 0x08,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*骡1757*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x40, 0x5F, 0x55, 0x55, 0xFF, 0x55, 0x55, 0x5F, 0x00, 0x0F, 0x00, 0x04, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*裸1758*/},\n        {\n\n                0x42, 0x8A, 0x12, 0xA7, 0x92, 0xBA, 0x52, 0x57, 0xB2, 0x82, 0x82, 0x08, 0x04, 0x02, 0x00, 0x0E,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*落1759*/},\n        {\n\n                0x10, 0x21, 0x02, 0x28, 0xA4, 0xAB, 0x92, 0x92, 0xAA, 0xA6, 0x20, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*洛1760*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x44, 0xAB, 0x92, 0x92, 0xAE, 0x40, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*骆1761*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*络1762*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x01, 0x3D, 0x21, 0x21, 0x21, 0x3F, 0xE0, 0x08, 0x05, 0x02, 0x05, 0x09,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x07,/*妈1763*/},\n        {\n\n                0x00, 0xFC, 0x24, 0xA4, 0xFC, 0xA5, 0x26, 0xA4, 0xFC, 0xA4, 0x24, 0x08, 0x07, 0x01, 0x00, 0x0F,\n                0x00, 0x01, 0x00, 0x0F, 0x00, 0x01,/*麻1764*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x01, 0x3D, 0x21, 0x21, 0x21, 0x3F, 0xE0, 0x04, 0x04, 0x03, 0x02, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x07,/*玛1765*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x01, 0x3D, 0x21, 0x21, 0x21, 0x3F, 0xE0, 0x00, 0x07, 0x02, 0x07, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x07,/*码1766*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x01, 0x3D, 0x21, 0x21, 0x3F, 0xE0, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x07,/*蚂1767*/},\n        {\n\n                0x00, 0x01, 0x3D, 0x21, 0x21, 0x21, 0x21, 0x21, 0x3F, 0x20, 0xE0, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x08, 0x07,/*马1768*/},\n        {\n\n                0x00, 0x17, 0xD5, 0x95, 0x97, 0x90, 0x97, 0x95, 0xF5, 0x87, 0x80, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x08, 0x08, 0x07,/*骂1769*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFE, 0x22, 0xFA, 0xA3, 0xFA, 0xA2, 0x22, 0x03, 0x01, 0x01, 0x08, 0x07,\n                0x01, 0x0F, 0x00, 0x0F, 0x00, 0x01,/*嘛1770*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x01, 0x3D, 0x21, 0x21, 0x21, 0x3F, 0xE0, 0x03, 0x01, 0x03, 0x00, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x07,/*吗1771*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0x7F, 0x49, 0x49, 0xFF, 0x49, 0x49, 0x7F, 0x04, 0x07, 0x02, 0x08, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x09,/*埋1772*/},\n        {\n\n                0x80, 0x82, 0xA2, 0xCA, 0x92, 0x82, 0xFA, 0x82, 0x82, 0x86, 0x80, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x00, 0x02, 0x02, 0x04, 0x08,/*买1773*/},\n        {\n\n                0x20, 0x22, 0x2A, 0xEA, 0xAA, 0xBF, 0xAA, 0xAA, 0xAA, 0x22, 0x20, 0x08, 0x0A, 0x09, 0x0A, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x08,/*麦1774*/},\n        {\n\n                0x08, 0x0A, 0x4A, 0x9A, 0x2A, 0x0F, 0xEA, 0x0A, 0x0A, 0x2A, 0x18, 0x01, 0x09, 0x09, 0x05, 0x05,\n                0x03, 0x01, 0x03, 0x05, 0x05, 0x09,/*卖1775*/},\n        {\n\n                0x21, 0xE2, 0x00, 0x02, 0x82, 0x7E, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x08, 0x07, 0x08, 0x0A, 0x09,\n                0x08, 0x08, 0x0A, 0x0A, 0x09, 0x08,/*迈1776*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x20, 0xE9, 0x09, 0xFA, 0x62, 0x90, 0x08, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x01, 0x02,/*脉1777*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xD2, 0x57, 0xF2, 0x52, 0xF2, 0x57, 0xD2, 0x0F, 0x04, 0x0F, 0x00, 0x0F,\n                0x02, 0x01, 0x02, 0x01, 0x0A, 0x0F,/*瞒1778*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x70, 0x5F, 0x75, 0x55, 0x55, 0x75, 0x5F, 0x70, 0x00, 0x0F, 0x04, 0x08, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*馒1779*/},\n        {\n\n                0x12, 0xCA, 0x42, 0x5E, 0x42, 0xE3, 0x42, 0x5E, 0x42, 0xCA, 0x12, 0x04, 0x05, 0x05, 0x05, 0x05,\n                0x07, 0x05, 0x05, 0x05, 0x05, 0x0E,/*蛮1780*/},\n        {\n\n                0x22, 0x44, 0xD2, 0x52, 0x57, 0xF2, 0x52, 0xF2, 0x57, 0x52, 0xD2, 0x04, 0x02, 0x0F, 0x00, 0x02,\n                0x01, 0x02, 0x01, 0x02, 0x08, 0x0F,/*满1781*/},\n        {\n\n                0xC2, 0x7A, 0x4A, 0xCF, 0x5A, 0x6A, 0x4A, 0xCF, 0x4A, 0x7A, 0xC2, 0x09, 0x09, 0x0B, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x09,/*蔓1782*/},\n        {\n\n                0x70, 0x5F, 0x55, 0x75, 0x55, 0x55, 0x55, 0x75, 0x55, 0x5F, 0x70, 0x08, 0x09, 0x0B, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x08,/*曼1783*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x70, 0x5F, 0x75, 0x55, 0x75, 0x5F, 0x70, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*慢1784*/},\n        {\n\n                0x10, 0x21, 0x02, 0x70, 0x5F, 0x75, 0x55, 0x55, 0x75, 0x5F, 0x70, 0x04, 0x02, 0x01, 0x08, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*漫1785*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x70, 0x5F, 0x75, 0x55, 0x55, 0x75, 0x5F, 0x70, 0x00, 0x07, 0x02, 0x08, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*谩1786*/},\n        {\n\n                0x44, 0x44, 0xC4, 0x4F, 0x44, 0x54, 0x64, 0x4F, 0x44, 0x44, 0x44, 0x00, 0x00, 0x0F, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x00,/*芒1787*/},\n        {\n\n                0x94, 0x24, 0x44, 0x4F, 0xC4, 0x44, 0x54, 0x6F, 0x44, 0x44, 0x44, 0x08, 0x05, 0x00, 0x00, 0x0F,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x00,/*茫1788*/},\n        {\n\n                0x02, 0xEE, 0xAA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xEA, 0x02, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*盲1789*/},\n        {\n\n                0x08, 0xF9, 0x0A, 0x08, 0x00, 0xFF, 0x49, 0x49, 0xF9, 0x49, 0x4F, 0x00, 0x07, 0x04, 0x04, 0x00,\n                0x0F, 0x04, 0x00, 0x03, 0x04, 0x0E,/*氓1790*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x08, 0xF8, 0x09, 0x0A, 0x08, 0x08, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x00,/*忙1791*/},\n        {\n\n                0x82, 0x92, 0x52, 0xB7, 0x12, 0x1A, 0x12, 0xB7, 0x5A, 0x92, 0x82, 0x02, 0x02, 0x0A, 0x07, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*莽1792*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xF2, 0x97, 0x92, 0xF2, 0x92, 0x97, 0xF2, 0x08, 0x08, 0x07, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*猫1793*/},\n        {\n\n                0x42, 0x4A, 0x4A, 0x4F, 0xDA, 0x6A, 0xCA, 0x6F, 0x5A, 0x4A, 0xC2, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x08, 0x0F, 0x00, 0x00, 0x01, 0x00,/*茅1794*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xF2, 0x97, 0x92, 0xF2, 0x92, 0x97, 0xF2, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*锚1795*/},\n        {\n\n                0x80, 0x82, 0x92, 0x92, 0x92, 0xFE, 0x49, 0x49, 0x49, 0x41, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*毛1796*/},\n        {\n\n                0x10, 0x10, 0x11, 0x91, 0x55, 0x35, 0xF9, 0x15, 0x13, 0x91, 0x70, 0x02, 0x02, 0x01, 0x00, 0x08,\n                0x08, 0x0F, 0x00, 0x00, 0x00, 0x00,/*矛1797*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x82, 0xFD, 0x00, 0xFE, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x04, 0x03, 0x00, 0x0F, 0x01, 0x01,/*铆1798*/},\n        {\n\n                0xFE, 0x02, 0x82, 0x81, 0xF9, 0x00, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x01, 0x09, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x00, 0x01, 0x01,/*卯1799*/},\n        {\n\n                0x02, 0xF2, 0x12, 0x17, 0x12, 0x12, 0xFA, 0x17, 0x1A, 0xD2, 0x12, 0x08, 0x07, 0x00, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x0E,/*茂1800*/},\n        {\n\n                0x00, 0x0F, 0xE1, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xE1, 0x0F, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*冒1801*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xEF, 0xA1, 0xA5, 0xA1, 0xEF, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x00, 0x0F, 0x0A, 0x0A, 0x0A, 0x0F,/*帽1802*/},\n        {\n\n                0xA4, 0xAA, 0x55, 0xE8, 0x00, 0x7C, 0xD6, 0x55, 0xD4, 0x54, 0x7C, 0x02, 0x0A, 0x09, 0x07, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*貌1803*/},\n        {\n\n                0x1E, 0xD2, 0x56, 0x49, 0x51, 0xC0, 0x52, 0x4E, 0x42, 0xD2, 0x1E, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贸1804*/},\n        {\n\n                0x80, 0x40, 0x20, 0x10, 0x0C, 0x83, 0x40, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x04, 0x06, 0x05,\n                0x04, 0x04, 0x04, 0x05, 0x06, 0x0C,/*么1805*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x22, 0x10, 0xEC, 0x0B, 0x88, 0x78, 0x08, 0x04, 0x04, 0x07, 0x02, 0x0A,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*玫1806*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x10, 0xEC, 0x0B, 0x88, 0x78, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*枚1807*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xC4, 0x7B, 0x4A, 0x6A, 0x4A, 0xFA, 0x42, 0x00, 0x00, 0x0F, 0x00, 0x03,\n                0x02, 0x02, 0x0B, 0x0A, 0x07, 0x02,/*梅1808*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x44, 0xFB, 0x4A, 0x6A, 0x4A, 0xFA, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x03, 0x02, 0x0B, 0x0A, 0x07,/*酶1809*/},\n        {\n\n                0x0C, 0x25, 0xD5, 0x5D, 0x55, 0xDF, 0x55, 0x5D, 0xD5, 0x15, 0x0C, 0x01, 0x07, 0x05, 0x05, 0x07,\n                0x05, 0x05, 0x05, 0x0F, 0x05, 0x01,/*霉1810*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x10, 0x8A, 0xBF, 0xAA, 0xEA, 0xAA, 0xBF, 0x82, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*煤1811*/},\n        {\n\n                0x10, 0x21, 0x02, 0x28, 0xE7, 0x21, 0x21, 0x21, 0xA7, 0x68, 0x08, 0x04, 0x02, 0x09, 0x08, 0x04,\n                0x05, 0x02, 0x05, 0x04, 0x08, 0x08,/*没1812*/},\n        {\n\n                0x00, 0xFF, 0x09, 0xE9, 0xA9, 0xA9, 0xAF, 0xA9, 0xA9, 0xA9, 0xEF, 0x08, 0x07, 0x00, 0x0F, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0F,/*眉1813*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x82, 0xBF, 0xAA, 0xEA, 0xAA, 0xBF, 0x82, 0x08, 0x05, 0x02, 0x0D, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*媒1814*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x44, 0x55, 0x56, 0xFC, 0x56, 0x55, 0x44, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*镁1815*/},\n        {\n\n                0x48, 0xC4, 0x7B, 0x4A, 0xCA, 0x5A, 0x6A, 0x4A, 0x4A, 0xFA, 0x42, 0x00, 0x03, 0x02, 0x02, 0x02,\n                0x03, 0x0A, 0x0A, 0x0A, 0x07, 0x02,/*每1816*/},\n        {\n\n                0x40, 0x54, 0x55, 0x56, 0x54, 0xFC, 0x54, 0x56, 0x55, 0x54, 0x40, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*美1817*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x20, 0x24, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x07, 0x02, 0x02, 0x07, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*昧1818*/},\n        {\n\n                0x86, 0xBA, 0xA2, 0xFE, 0x42, 0x53, 0x52, 0xFE, 0x52, 0x52, 0x46, 0x08, 0x07, 0x00, 0x0F, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*寐1819*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0x24, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x08, 0x05, 0x02, 0x0D, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*妹1820*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFF, 0x09, 0xE9, 0xAF, 0xA9, 0xEF, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x07, 0x00, 0x0F, 0x0A, 0x0A, 0x0F,/*媚1821*/},\n        {\n\n                0x00, 0xF9, 0x02, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFF, 0x00, 0x0F, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x0F,/*门1822*/},\n        {\n\n                0xF9, 0x02, 0xC0, 0x00, 0xC5, 0x19, 0x01, 0x21, 0xC1, 0x01, 0xFF, 0x0F, 0x02, 0x01, 0x00, 0x03,\n                0x04, 0x04, 0x06, 0x08, 0x08, 0x0F,/*闷1823*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFD, 0x02, 0x00, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*们1824*/},\n        {\n\n                0xF2, 0x52, 0x52, 0x57, 0xF2, 0x02, 0xFA, 0x4F, 0x4A, 0x4A, 0xFA, 0x07, 0x02, 0x02, 0x02, 0x0B,\n                0x04, 0x03, 0x01, 0x09, 0x09, 0x0F,/*萌1825*/},\n        {\n\n                0x1A, 0x8A, 0xAA, 0x6F, 0x6A, 0xAA, 0x2A, 0x2F, 0xAA, 0x4A, 0x1A, 0x08, 0x0A, 0x0A, 0x05, 0x05,\n                0x0A, 0x0F, 0x01, 0x02, 0x04, 0x04,/*蒙1826*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x9A, 0xAF, 0x6A, 0xAA, 0x2A, 0xAF, 0x5A, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x0A, 0x05, 0x0A, 0x0F, 0x02, 0x04,/*檬1827*/},\n        {\n\n                0x3E, 0x2A, 0x2A, 0x2A, 0xBE, 0x40, 0x3F, 0x15, 0x15, 0x55, 0x7F, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盟1828*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x88, 0x89, 0xA9, 0xBD, 0x8B, 0x89, 0x88, 0x00, 0x0F, 0x04, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*锰1829*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x88, 0x89, 0xA9, 0xBD, 0x8B, 0x89, 0x88, 0x08, 0x08, 0x07, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*猛1830*/},\n        {\n\n                0x12, 0x0A, 0x3F, 0x8A, 0xD2, 0x80, 0x92, 0x8A, 0xBF, 0x8A, 0x12, 0x08, 0x09, 0x09, 0x0A, 0x04,\n                0x04, 0x04, 0x02, 0x02, 0x01, 0x00,/*梦1831*/},\n        {\n\n                0x08, 0x08, 0x09, 0x49, 0x49, 0x79, 0x0D, 0x0B, 0x09, 0x08, 0x08, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*孟1832*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x24, 0x28, 0xA0, 0xFF, 0xA0, 0x28, 0x24, 0x0F, 0x04, 0x04, 0x0F, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*眯1833*/},\n        {\n\n                0xFD, 0xA5, 0x9F, 0xA5, 0xFD, 0x22, 0xE4, 0x82, 0x54, 0xFF, 0x94, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x08, 0x07, 0x08, 0x08, 0x0B, 0x08,/*醚1834*/},\n        {\n\n                0x00, 0xFE, 0x6A, 0x5A, 0x7E, 0xEA, 0x13, 0xEA, 0x7E, 0x5A, 0x6A, 0x08, 0x07, 0x05, 0x05, 0x05,\n                0x0F, 0x00, 0x0F, 0x05, 0x05, 0x05,/*靡1835*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0x5A, 0xBE, 0x0A, 0xD3, 0x0A, 0xBE, 0x5A, 0x2A, 0x08, 0x07, 0x09, 0x05, 0x03,\n                0x01, 0x0F, 0x01, 0x03, 0x05, 0x09,/*糜1836*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x12, 0x94, 0x50, 0xFF, 0x50, 0x94, 0x12, 0x08, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x09,/*迷1837*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x11, 0xF2, 0x00, 0x92, 0x54, 0xFF, 0x54, 0x92, 0x00, 0x07, 0x0A, 0x04, 0x03,\n                0x04, 0x08, 0x08, 0x0B, 0x08, 0x08,/*谜1838*/},\n        {\n\n                0xF2, 0x92, 0x9E, 0x00, 0x10, 0xC8, 0x07, 0xF4, 0x04, 0x54, 0x8C, 0x08, 0x08, 0x07, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*弥1839*/},\n        {\n\n                0x10, 0x12, 0x14, 0x98, 0x50, 0xFF, 0x50, 0x98, 0x14, 0x12, 0x10, 0x02, 0x02, 0x01, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x02,/*米1840*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x70, 0x00, 0xF1, 0x86, 0x60, 0x1C, 0xE0, 0x01, 0x00, 0x0F, 0x08, 0x04,\n                0x02, 0x07, 0x08, 0x08, 0x0E, 0x00,/*秘1841*/},\n        {\n\n                0x02, 0xE6, 0x2A, 0x22, 0x26, 0xAA, 0x21, 0x21, 0x29, 0xE5, 0x01, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x06, 0x08, 0x08, 0x09, 0x0C,/*觅1842*/},\n        {\n\n                0x20, 0x42, 0x04, 0xE0, 0x00, 0xF9, 0x02, 0xC4, 0x30, 0x4C, 0x80, 0x08, 0x04, 0x01, 0x08, 0x04,\n                0x07, 0x09, 0x08, 0x08, 0x0C, 0x01,/*泌1843*/},\n        {\n\n                0x26, 0x9A, 0xC2, 0xDA, 0xA6, 0xEB, 0xB2, 0xAA, 0xB2, 0x8A, 0x36, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*蜜1844*/},\n        {\n\n                0x46, 0x32, 0x82, 0xB2, 0x46, 0x6B, 0x52, 0x4A, 0x62, 0x12, 0x66, 0x00, 0x0E, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0E, 0x00,/*密1845*/},\n        {\n\n                0x43, 0x41, 0xDF, 0x55, 0x75, 0xD5, 0x55, 0x55, 0xDF, 0x41, 0x43, 0x02, 0x01, 0x07, 0x01, 0x01,\n                0x0F, 0x01, 0x05, 0x07, 0x01, 0x02,/*幂1846*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x80, 0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*棉1847*/},\n        {\n\n                0xFF, 0x49, 0x49, 0xFF, 0x00, 0xFF, 0x49, 0x49, 0xF9, 0x49, 0x4F, 0x07, 0x02, 0x02, 0x07, 0x00,\n                0x0F, 0x04, 0x00, 0x03, 0x04, 0x0E,/*眠1848*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x80, 0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0x80, 0x04, 0x04, 0x02, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*绵1849*/},\n        {\n\n                0x40, 0xEF, 0x51, 0x55, 0x55, 0xD5, 0x55, 0x75, 0x41, 0xCF, 0x00, 0x08, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x07, 0x09, 0x09, 0x09, 0x0C,/*冕1850*/},\n        {\n\n                0x10, 0xF8, 0x94, 0x93, 0x92, 0xF2, 0x9A, 0x96, 0x90, 0xF0, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0C,/*免1851*/},\n        {\n\n                0x08, 0xF4, 0x93, 0xFA, 0x96, 0xF0, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0x08, 0x04, 0x02, 0x01, 0x06,\n                0x08, 0x0A, 0x09, 0x0A, 0x0B, 0x0C,/*勉1852*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xF4, 0x93, 0xFA, 0x96, 0xF0, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*娩1853*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xF2, 0x12, 0xFA, 0x56, 0xF2, 0x12, 0xF2, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x04, 0x07, 0x05, 0x07, 0x04, 0x0F,/*缅1854*/},\n        {\n\n                0x02, 0xF2, 0x12, 0x12, 0xFA, 0x56, 0x52, 0xF2, 0x12, 0x12, 0xF2, 0x00, 0x0F, 0x04, 0x04, 0x07,\n                0x05, 0x05, 0x07, 0x04, 0x04, 0x0F,/*面1855*/},\n        {\n\n                0x02, 0xF2, 0x92, 0x97, 0x92, 0xF2, 0x92, 0x97, 0x92, 0xF2, 0x02, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x0F, 0x00,/*苗1856*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xF2, 0x97, 0x92, 0xF2, 0x92, 0x97, 0xF2, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*描1857*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xF2, 0x97, 0x92, 0xF2, 0x92, 0x97, 0xF2, 0x0F, 0x04, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*瞄1858*/},\n        {\n\n                0x52, 0x72, 0xAA, 0xD7, 0x02, 0xF2, 0x5A, 0x57, 0x52, 0xF2, 0x02, 0x05, 0x0D, 0x0A, 0x07, 0x08,\n                0x05, 0x03, 0x01, 0x07, 0x09, 0x0C,/*藐1859*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x40, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*秒1860*/},\n        {\n\n                0x22, 0x44, 0xFE, 0x52, 0xFE, 0x40, 0x38, 0x00, 0xFF, 0x04, 0xB8, 0x04, 0x02, 0x07, 0x02, 0x03,\n                0x08, 0x08, 0x04, 0x02, 0x01, 0x00,/*渺1861*/},\n        {\n\n                0x00, 0xFC, 0x04, 0xE4, 0x24, 0x25, 0xFE, 0x24, 0x24, 0xE4, 0x04, 0x08, 0x07, 0x00, 0x0F, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x00,/*庙1862*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x40, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*妙1863*/},\n        {\n\n                0x02, 0xBA, 0xAA, 0xAF, 0xBA, 0xEA, 0xBA, 0xEF, 0xAA, 0xBA, 0x82, 0x08, 0x07, 0x02, 0x04, 0x00,\n                0x09, 0x0A, 0x04, 0x0A, 0x09, 0x0C,/*蔑1864*/},\n        {\n\n                0x82, 0x72, 0x02, 0x02, 0x82, 0x7E, 0x82, 0x02, 0x42, 0x32, 0x02, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*灭1865*/},\n        {\n\n                0x00, 0xFF, 0x49, 0x49, 0x49, 0x49, 0xF9, 0x49, 0x49, 0x4F, 0x40, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x00, 0x01, 0x02, 0x04, 0x0E,/*民1866*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFF, 0x49, 0x49, 0xF9, 0x49, 0x4F, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x00, 0x03, 0x04, 0x0E,/*抿1867*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0xFE, 0x02, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x08, 0x0F, 0x08, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x08, 0x0F, 0x08,/*皿1868*/},\n        {\n\n                0x44, 0xFB, 0x4A, 0x6A, 0x4A, 0xFA, 0x50, 0xEF, 0x08, 0xF8, 0x08, 0x00, 0x03, 0x02, 0x0B, 0x0A,\n                0x07, 0x0A, 0x05, 0x02, 0x05, 0x08,/*敏1869*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xF9, 0x12, 0x51, 0x95, 0x71, 0x11, 0xFF, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x02, 0x01, 0x00, 0x0B, 0x08, 0x0F,/*悯1870*/},\n        {\n\n                0xF9, 0x02, 0x78, 0x49, 0x49, 0xFF, 0x49, 0x49, 0x79, 0x01, 0xFF, 0x0F, 0x00, 0x02, 0x02, 0x02,\n                0x03, 0x02, 0x03, 0x06, 0x08, 0x0F,/*闽1871*/},\n        {\n\n                0xFF, 0x11, 0x11, 0x11, 0xFF, 0x00, 0xFF, 0x49, 0x49, 0x49, 0xFF, 0x03, 0x01, 0x01, 0x01, 0x09,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x0F,/*明1872*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x03, 0x7D, 0x55, 0xD5, 0x7D, 0x03, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x09, 0x05, 0x01, 0x01, 0x05, 0x09,/*螟1873*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x7E, 0x43, 0x4A, 0x52, 0x5E, 0xC0, 0x03, 0x01, 0x01, 0x03, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸣1874*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x10, 0x88, 0xD4, 0xA7, 0xA4, 0x94, 0x8C, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*铭1875*/},\n        {\n\n                0x00, 0x10, 0x88, 0x94, 0xE7, 0xC4, 0xA4, 0xA4, 0x94, 0x8C, 0x80, 0x01, 0x01, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*名1876*/},\n        {\n\n                0x10, 0xD0, 0x48, 0x54, 0xD2, 0x11, 0xD2, 0x54, 0x48, 0xD0, 0x10, 0x00, 0x07, 0x02, 0x02, 0x07,\n                0x00, 0x0F, 0x00, 0x04, 0x07, 0x00,/*命1877*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x40, 0x4B, 0xA5, 0xAF, 0x50, 0x2B, 0x45, 0x4F, 0x00, 0x0F, 0x04, 0x00, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x05, 0x04, 0x02,/*谬1878*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x02, 0xFA, 0xAF, 0xAA, 0xAA, 0xAF, 0xFA, 0x02, 0x08, 0x0F, 0x00, 0x0A, 0x0A,\n                0x06, 0x03, 0x02, 0x06, 0x0A, 0x0A,/*摸1879*/},\n        {\n\n                0x42, 0x42, 0xFA, 0x4F, 0x5A, 0xEA, 0x4A, 0x4F, 0xFA, 0x42, 0x42, 0x02, 0x05, 0x04, 0x05, 0x0D,\n                0x0F, 0x05, 0x05, 0x04, 0x05, 0x02,/*摹1880*/},\n        {\n\n                0x02, 0xFA, 0x6F, 0xAA, 0xFA, 0xAE, 0xCA, 0xAA, 0xFF, 0xAA, 0x6A, 0x08, 0x07, 0x04, 0x02, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*蘑1881*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x02, 0xFA, 0xAF, 0xAA, 0xAF, 0xFA, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*模1882*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x02, 0xFA, 0xAF, 0xAA, 0xAF, 0xFA, 0x02, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*膜1883*/},\n        {\n\n                0x00, 0xFE, 0xAA, 0x9A, 0xBE, 0x8A, 0x93, 0x8A, 0xBE, 0x9A, 0xAA, 0x08, 0x07, 0x04, 0x02, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*磨1884*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0x5A, 0x7E, 0x4A, 0xD3, 0x4A, 0x7E, 0x5A, 0x2A, 0x08, 0x07, 0x04, 0x05, 0x05,\n                0x0D, 0x0F, 0x05, 0x05, 0x05, 0x04,/*摩1885*/},\n        {\n\n                0x00, 0xFE, 0x1A, 0xEA, 0xBE, 0xAA, 0xF3, 0xAA, 0xBE, 0xEA, 0x1A, 0x08, 0x07, 0x08, 0x0B, 0x06,\n                0x03, 0x06, 0x0A, 0x0E, 0x0B, 0x0C,/*魔1886*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x04, 0x24, 0xA4, 0xFF, 0xA4, 0x24, 0x04, 0x00, 0x08, 0x0F, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*抹1887*/},\n        {\n\n                0x04, 0x24, 0x24, 0xA4, 0x64, 0xFF, 0x64, 0xA4, 0x24, 0x24, 0x04, 0x02, 0x02, 0x01, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x02,/*末1888*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0xAA, 0xFA, 0x02, 0x0A, 0x0A, 0x0A, 0x06, 0x03,\n                0x02, 0x02, 0x06, 0x0A, 0x0A, 0x0A,/*莫1889*/},\n        {\n\n                0x40, 0xD7, 0x55, 0x57, 0xD5, 0x7F, 0xD5, 0x57, 0x55, 0xD7, 0x40, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*墨1890*/},\n        {\n\n                0x5F, 0x55, 0x51, 0xFF, 0x55, 0x5F, 0x00, 0x10, 0xFF, 0x12, 0x14, 0x0A, 0x06, 0x0A, 0x05, 0x09,\n                0x05, 0x08, 0x07, 0x00, 0x07, 0x08,/*默1891*/},\n        {\n\n                0x22, 0x44, 0x00, 0x04, 0x24, 0xA4, 0xFF, 0xA4, 0x24, 0x24, 0x04, 0x04, 0x02, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x01, 0x02, 0x04,/*沫1892*/},\n        {\n\n                0x22, 0x44, 0x02, 0xFA, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0xFA, 0x02, 0x04, 0x02, 0x08, 0x0A, 0x0A,\n                0x06, 0x03, 0x06, 0x0A, 0x0A, 0x0A,/*漠1893*/},\n        {\n\n                0x06, 0xEA, 0xAA, 0xBE, 0xAA, 0xAB, 0xAA, 0xBE, 0xAA, 0xEA, 0x06, 0x0A, 0x0B, 0x0A, 0x06, 0x02,\n                0x02, 0x02, 0x06, 0x0A, 0x0B, 0x0A,/*寞1894*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0xF2, 0x92, 0x9A, 0x96, 0x92, 0xF2, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*陌1895*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x82, 0xBF, 0xAA, 0xEA, 0xAA, 0xBF, 0x82, 0x00, 0x00, 0x07, 0x02, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*谋1896*/},\n        {\n\n                0x00, 0x88, 0x6C, 0x4A, 0x49, 0xF8, 0x48, 0x4A, 0x4C, 0x58, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*牟1897*/},\n        {\n\n                0x82, 0x82, 0xBF, 0xAA, 0xAA, 0xEA, 0xAA, 0xAA, 0xBF, 0x82, 0x82, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*某1898*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xA0, 0x7E, 0xAA, 0x32, 0x22, 0xFE, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x03,\n                0x02, 0x02, 0x0B, 0x0A, 0x07, 0x02,/*拇1899*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x00, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*牡1900*/},\n        {\n\n                0x04, 0xF4, 0x94, 0x94, 0x95, 0xF6, 0x94, 0x94, 0x94, 0xF4, 0x04, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x0F, 0x00,/*亩1901*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0xFE, 0xAA, 0x32, 0x22, 0xFE, 0x20, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x03, 0x02, 0x0B, 0x0A, 0x07, 0x02,/*姆1902*/},\n        {\n\n                0x20, 0xFE, 0x22, 0x22, 0xA2, 0x2A, 0x32, 0x22, 0x22, 0xFE, 0x20, 0x00, 0x03, 0x02, 0x02, 0x02,\n                0x03, 0x0A, 0x0A, 0x0A, 0x07, 0x02,/*母1903*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xEF, 0xAA, 0xBA, 0xAA, 0xAF, 0xAA, 0xBA, 0x82, 0x04, 0x02, 0x09, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x09, 0x02, 0x04,/*墓1904*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xEF, 0xAA, 0xBA, 0xAA, 0xAF, 0xAA, 0xBA, 0x82, 0x04, 0x02, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x02, 0x04,/*暮1905*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xEF, 0xAA, 0xBA, 0xAA, 0xAF, 0xAA, 0xBA, 0x82, 0x04, 0x02, 0x0F, 0x02, 0x02,\n                0x0F, 0x02, 0x0A, 0x0F, 0x02, 0x04,/*幕1906*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xEF, 0xAA, 0xBA, 0xAA, 0xAF, 0xAA, 0xBA, 0x82, 0x04, 0x0A, 0x0B, 0x06, 0x03,\n                0x02, 0x0A, 0x0A, 0x07, 0x02, 0x04,/*募1907*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xEF, 0xAA, 0xBA, 0xAA, 0xAF, 0xAA, 0xBA, 0x82, 0x02, 0x01, 0x04, 0x02, 0x08,\n                0x0F, 0x02, 0x04, 0x02, 0x05, 0x02,/*慕1908*/},\n        {\n\n                0x08, 0x08, 0x88, 0x68, 0x18, 0xFF, 0x18, 0x68, 0x88, 0x08, 0x08, 0x02, 0x01, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x01, 0x02,/*木1909*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*目1910*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x90, 0x54, 0x34, 0x9F, 0x34, 0x54, 0x90, 0x0F, 0x04, 0x04, 0x0F, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*睦1911*/},\n        {\n\n                0x90, 0x8E, 0x88, 0xFF, 0x48, 0x10, 0xEC, 0x0B, 0x88, 0x78, 0x08, 0x00, 0x00, 0x00, 0x0F, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*牧1912*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0x7E, 0xAB, 0xEA, 0x2A, 0x7E, 0x80, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x09, 0x0A, 0x0A, 0x05, 0x04, 0x00,/*穆1913*/},\n        {\n\n                0x08, 0x88, 0xBC, 0xAC, 0xAA, 0xA9, 0xAA, 0xAC, 0xBC, 0x48, 0x08, 0x02, 0x02, 0x02, 0x02, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*拿1914*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x92, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x32, 0xCE, 0x03, 0x01, 0x0B, 0x04, 0x03,\n                0x08, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*哪1915*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFC, 0x84, 0x44, 0x3F, 0x44, 0x84, 0xFC, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*呐1916*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFC, 0x84, 0x44, 0x3F, 0x44, 0x84, 0xFC, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*钠1917*/},\n        {\n\n                0x92, 0x92, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x08, 0x04, 0x03, 0x08, 0x08,\n                0x07, 0x00, 0x0F, 0x02, 0x02, 0x01,/*那1918*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x92, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x32, 0xCE, 0x0D, 0x02, 0x0D, 0x04, 0x03,\n                0x08, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*娜1919*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xFC, 0x84, 0x44, 0x3F, 0x44, 0x84, 0xFC, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*纳1920*/},\n        {\n\n                0x08, 0xA4, 0xAB, 0xAA, 0xAA, 0xAA, 0x2A, 0x2A, 0xEA, 0x0A, 0x02, 0x08, 0x04, 0x03, 0x00, 0x0A,\n                0x0B, 0x06, 0x00, 0x03, 0x04, 0x0E,/*氖1921*/},\n        {\n\n                0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x62, 0x5A, 0x46, 0xC0, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x08, 0x07,/*乃1922*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x02, 0xFE, 0x02, 0x72, 0x4E, 0xC0, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*奶1923*/},\n        {\n\n                0xF2, 0x12, 0xFA, 0x16, 0xF2, 0x12, 0xF2, 0x48, 0x88, 0xFF, 0x08, 0x0F, 0x00, 0x07, 0x00, 0x07,\n                0x08, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*耐1924*/},\n        {\n\n                0x92, 0x92, 0xAA, 0xAA, 0xA6, 0xA3, 0xA6, 0xAA, 0xAA, 0x92, 0x92, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*奈1925*/},\n        {\n\n                0x02, 0xFA, 0x0A, 0x5A, 0x6A, 0xCF, 0x6A, 0x5A, 0x0A, 0xFA, 0x02, 0x00, 0x0F, 0x01, 0x01, 0x01,\n                0x07, 0x01, 0x09, 0x09, 0x0F, 0x00,/*南1926*/},\n        {\n\n                0x00, 0x7F, 0x49, 0x49, 0xC9, 0x7F, 0x49, 0x49, 0x49, 0x7F, 0x00, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x09, 0x07,/*男1927*/},\n        {\n\n                0x0A, 0x32, 0xC2, 0x3E, 0x10, 0xFC, 0xA7, 0xA4, 0xFD, 0xA6, 0xA4, 0x04, 0x03, 0x00, 0x07, 0x00,\n                0x0F, 0x04, 0x04, 0x07, 0x04, 0x04,/*难1928*/},\n        {\n\n                0x62, 0xAE, 0xAA, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0xAA, 0xAE, 0x62, 0x0A, 0x0A, 0x06, 0x0F, 0x0A,\n                0x02, 0x02, 0x07, 0x0A, 0x0A, 0x0A,/*囊1929*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*挠1930*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xE4, 0x04, 0x15, 0xE6, 0x14, 0xE4, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x07, 0x04, 0x05, 0x04, 0x05, 0x0F,/*脑1931*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xE4, 0x04, 0x15, 0xE6, 0x14, 0x04, 0xE4, 0x00, 0x00, 0x0F, 0x00, 0x07,\n                0x04, 0x05, 0x04, 0x05, 0x04, 0x0F,/*恼1932*/},\n        {\n\n                0xF9, 0x02, 0xC8, 0x49, 0x49, 0xFB, 0x4D, 0x49, 0xC9, 0x01, 0xFF, 0x0F, 0x00, 0x03, 0x00, 0x00,\n                0x0F, 0x00, 0x02, 0x03, 0x08, 0x0F,/*闹1933*/},\n        {\n\n                0x22, 0x44, 0x00, 0xF8, 0xA8, 0xA8, 0xAF, 0xAA, 0xAA, 0xFA, 0x02, 0x04, 0x02, 0x00, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*淖1934*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0xFE, 0x12, 0xD2, 0x12, 0x92, 0x5E, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x07, 0x00, 0x07, 0x09, 0x08, 0x0E,/*呢1935*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x4A, 0x52, 0xC6, 0x6A, 0x41, 0xC9, 0x45, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x09, 0x05, 0x02, 0x02, 0x05, 0x08,/*馁1936*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x84, 0x64, 0x1F, 0x24, 0xC4, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x0F, 0x00,/*内1937*/},\n        {\n\n                0xF8, 0x0F, 0xFC, 0x94, 0xFF, 0x94, 0xF4, 0x10, 0xEC, 0x0B, 0xF8, 0x0D, 0x02, 0x05, 0x02, 0x0F,\n                0x02, 0x04, 0x08, 0x04, 0x03, 0x0C,/*嫩1938*/},\n        {\n\n                0x04, 0xF6, 0x55, 0x54, 0xF6, 0x00, 0xCF, 0x14, 0x12, 0x91, 0x18, 0x00, 0x0F, 0x01, 0x09, 0x0F,\n                0x00, 0x07, 0x0A, 0x09, 0x08, 0x0E,/*能1939*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFE, 0x12, 0xD2, 0x12, 0x92, 0x5E, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x07, 0x00, 0x07, 0x09, 0x08, 0x0E,/*妮1940*/},\n        {\n\n                0x0C, 0xE5, 0xAD, 0xA5, 0x95, 0x0F, 0xA5, 0xA5, 0xAD, 0xE5, 0x0C, 0x08, 0x0B, 0x0A, 0x06, 0x02,\n                0x02, 0x02, 0x06, 0x0A, 0x0B, 0x0C,/*霓1941*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFE, 0x92, 0x81, 0x90, 0x92, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0C,/*倪1942*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0xFE, 0x12, 0xD2, 0x12, 0x92, 0x52, 0x1E, 0x04, 0x02, 0x09, 0x04, 0x03,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*泥1943*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x12, 0xD2, 0x12, 0x12, 0x92, 0x92, 0x5E, 0x00, 0x08, 0x06, 0x01, 0x00, 0x07,\n                0x09, 0x09, 0x08, 0x08, 0x08, 0x0E,/*尼1944*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x00, 0x82, 0x0C, 0xE0, 0x1F, 0x00, 0x08, 0x0F, 0x00, 0x00, 0x03,\n                0x09, 0x04, 0x03, 0x00, 0x03, 0x0C,/*拟1945*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x10, 0xCF, 0x04, 0xF4, 0x04, 0x54, 0x8C, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*你1946*/},\n        {\n\n                0x00, 0xFF, 0x25, 0xA5, 0xEF, 0xB5, 0xA5, 0xA5, 0xAF, 0xA5, 0x25, 0x00, 0x0F, 0x09, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*匿1947*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xAA, 0xAA, 0xAA, 0x7F, 0x82, 0x03, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0B, 0x04, 0x0B, 0x00, 0x07, 0x0C,/*腻1948*/},\n        {\n\n                0x11, 0xF2, 0x04, 0xF4, 0x85, 0x86, 0xFC, 0x86, 0x85, 0xF4, 0x04, 0x08, 0x07, 0x08, 0x08, 0x0C,\n                0x0A, 0x09, 0x08, 0x08, 0x08, 0x08,/*逆1949*/},\n        {\n\n                0x22, 0x44, 0x39, 0xA9, 0x29, 0xEF, 0x00, 0x39, 0xA9, 0x29, 0xEF, 0x04, 0x02, 0x04, 0x0A, 0x09,\n                0x07, 0x00, 0x04, 0x0A, 0x09, 0x07,/*溺1950*/},\n        {\n\n                0x8A, 0x8A, 0xEA, 0x8F, 0x8A, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0x8A, 0x00, 0x0B, 0x02, 0x0A, 0x02,\n                0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x0E,/*蔫1951*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x08, 0xC0, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*拈1952*/},\n        {\n\n                0x10, 0x08, 0xE7, 0x24, 0x24, 0x24, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x0F, 0x01, 0x01, 0x01, 0x01,/*年1953*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xFA, 0xAE, 0x07, 0x02, 0x07, 0x08, 0x07,\n                0x00, 0x0F, 0x04, 0x03, 0x04, 0x0A,/*碾1954*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x6A, 0xDF, 0x6A, 0xC0, 0x6A, 0x5F, 0x6A, 0x08, 0x0F, 0x00, 0x00, 0x05,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x04,/*撵1955*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x08, 0x14, 0x92, 0x19, 0x52, 0x34, 0x08, 0x08, 0x0F, 0x00, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*捻1956*/},\n        {\n\n                0x10, 0x10, 0x28, 0x24, 0x2A, 0x31, 0xA2, 0x64, 0x08, 0x10, 0x10, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*念1957*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x80, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*娘1958*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x04, 0x01, 0x06, 0x09,/*酿1959*/},\n        {\n\n                0x00, 0x00, 0x7E, 0x42, 0x4B, 0x52, 0x42, 0x52, 0x5E, 0x40, 0xC0, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0A, 0x08, 0x07,/*鸟1960*/},\n        {\n\n                0x00, 0xFF, 0x49, 0x49, 0xC9, 0x09, 0xF9, 0x69, 0x89, 0x49, 0x2F, 0x08, 0x07, 0x04, 0x02, 0x01,\n                0x08, 0x0F, 0x00, 0x01, 0x02, 0x04,/*尿1961*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x7F, 0x49, 0x49, 0xC9, 0x49, 0x49, 0x7F, 0x08, 0x0F, 0x00, 0x08, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x09,/*捏1962*/},\n        {\n\n                0x41, 0x41, 0x7F, 0x55, 0x55, 0x55, 0x55, 0x55, 0xFF, 0x21, 0x21, 0x09, 0x0B, 0x05, 0x05, 0x0B,\n                0x00, 0x09, 0x0B, 0x05, 0x05, 0x0B,/*聂1963*/},\n        {\n\n                0x02, 0xFA, 0xAE, 0xBB, 0xE2, 0x82, 0xAA, 0xBB, 0xEE, 0xBA, 0x2A, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0E, 0x03, 0x02, 0x02, 0x02, 0x02,/*孽1964*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x10, 0x9E, 0x10, 0x10, 0xDF, 0x14, 0x14, 0x94, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x0A, 0x09, 0x08, 0x09, 0x0A, 0x0F,/*啮1965*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x41, 0x7F, 0x55, 0x55, 0x55, 0xFF, 0x21, 0x00, 0x0F, 0x04, 0x00, 0x0B,\n                0x05, 0x0B, 0x00, 0x0B, 0x05, 0x0B,/*镊1966*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFE, 0xAA, 0xAB, 0xAA, 0xFE, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x0A,\n                0x06, 0x02, 0x0F, 0x02, 0x06, 0x0A,/*镍1967*/},\n        {\n\n                0x11, 0x22, 0x00, 0x7F, 0x49, 0x49, 0xC9, 0x49, 0x49, 0x7F, 0x00, 0x04, 0x02, 0x08, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x08,/*涅1968*/},\n        {\n\n                0x10, 0x08, 0xFC, 0x03, 0x48, 0x27, 0x84, 0xFC, 0x04, 0x24, 0x4C, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*您1969*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x2C, 0x24, 0x25, 0xE6, 0x24, 0x2C, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*柠1970*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x2C, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x2C, 0x08, 0x08, 0x07, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*狞1971*/},\n        {\n\n                0x04, 0x08, 0x40, 0x37, 0xEA, 0x2D, 0x90, 0x15, 0xF9, 0x95, 0xB3, 0x02, 0x01, 0x08, 0x05, 0x03,\n                0x0D, 0x07, 0x08, 0x0F, 0x08, 0x08,/*凝1972*/},\n        {\n\n                0x2C, 0x24, 0x24, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x24, 0x24, 0x2C, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*宁1973*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x2C, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x2C, 0x08, 0x0F, 0x00, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*拧1974*/},\n        {\n\n                0x22, 0x44, 0x00, 0x2C, 0x24, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x2C, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*泞1975*/},\n        {\n\n                0xA0, 0x90, 0x8E, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x88, 0x88, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*牛1976*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x42, 0xC2, 0x7E, 0x42, 0x42, 0xFE, 0x00, 0x08, 0x0F, 0x00, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*扭1977*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x42, 0xC2, 0x7E, 0x42, 0x42, 0xFE, 0x00, 0x00, 0x0F, 0x04, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*钮1978*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x42, 0xC2, 0x7E, 0x42, 0x42, 0xFE, 0x00, 0x04, 0x04, 0x02, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*纽1979*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x0C, 0x84, 0xE4, 0x1F, 0xE4, 0x04, 0x8C, 0x08, 0x07, 0x08, 0x0F, 0x01,\n                0x00, 0x0F, 0x04, 0x00, 0x03, 0x04,/*脓1980*/},\n        {\n\n                0x22, 0x44, 0x00, 0x8C, 0x44, 0xE4, 0x1C, 0x67, 0x84, 0x44, 0x2C, 0x04, 0x02, 0x00, 0x00, 0x00,\n                0x0F, 0x04, 0x00, 0x01, 0x02, 0x04,/*浓1981*/},\n        {\n\n                0x1C, 0x04, 0x84, 0xE4, 0x1C, 0x37, 0xC4, 0x04, 0x84, 0x44, 0x1C, 0x02, 0x01, 0x00, 0x0F, 0x04,\n                0x02, 0x00, 0x01, 0x02, 0x04, 0x04,/*农1982*/},\n        {\n\n                0x20, 0x22, 0x2A, 0xAA, 0x2A, 0x3E, 0x2A, 0xAA, 0x2A, 0x22, 0x20, 0x01, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*弄1983*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x02, 0x3E, 0xC2, 0x02, 0xC2, 0x3E, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*奴1984*/},\n        {\n\n                0x84, 0x5C, 0x27, 0x24, 0xDC, 0x00, 0x82, 0x5E, 0x22, 0x52, 0x8E, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*努1985*/},\n        {\n\n                0x84, 0x5C, 0x27, 0x24, 0x5C, 0x00, 0x82, 0x5E, 0x22, 0x52, 0x8E, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*怒1986*/},\n        {\n\n                0x08, 0x08, 0x48, 0xB8, 0x8F, 0x08, 0x88, 0x48, 0x38, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x08, 0x00,/*女1987*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0x56, 0x5A, 0xD6, 0x7A, 0x52, 0x59, 0x55, 0x07, 0x02, 0x07, 0x04, 0x0A,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*暖1988*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x94, 0x94, 0x9F, 0xB5, 0xAD, 0xA5, 0xB5, 0x0C, 0x08, 0x07, 0x02, 0x0F, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x02,/*虐1989*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0xE4, 0x25, 0x26, 0x24, 0x24, 0x24, 0x04, 0x09, 0x04, 0x03, 0x01, 0x0F,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x01,/*疟1990*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x92, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x32, 0xCE, 0x08, 0x0F, 0x08, 0x04, 0x03,\n                0x08, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*挪1991*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x4C, 0x55, 0x45, 0xDF, 0x45, 0x55, 0x4C, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*懦1992*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x4C, 0x55, 0x45, 0xDF, 0x45, 0x55, 0x4C, 0x01, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*糯1993*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x24, 0x24, 0xEF, 0xB4, 0xA4, 0xAF, 0xA4, 0x24, 0x00, 0x0F, 0x04, 0x02, 0x01,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*诺1994*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x90, 0x92, 0xFE, 0x51, 0x10, 0xFF, 0x92, 0x54, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x0F, 0x04, 0x02, 0x03, 0x04, 0x0E,/*哦1995*/},\n        {\n\n                0xFE, 0x02, 0x9A, 0x62, 0x9A, 0x00, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x07, 0x04, 0x05, 0x04, 0x05,\n                0x00, 0x08, 0x06, 0x01, 0x06, 0x08,/*欧1996*/},\n        {\n\n                0xFE, 0x02, 0x9A, 0x62, 0x9A, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x07, 0x04, 0x05, 0x04, 0x05,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸥1997*/},\n        {\n\n                0xFE, 0x02, 0x9A, 0x62, 0x9A, 0x10, 0xCE, 0x42, 0x42, 0xDE, 0x10, 0x07, 0x04, 0x05, 0x04, 0x05,\n                0x08, 0x05, 0x02, 0x02, 0x05, 0x08,/*殴1998*/},\n        {\n\n                0x02, 0x52, 0xFA, 0x57, 0x02, 0xFA, 0xAA, 0xFF, 0xAA, 0xFA, 0x02, 0x05, 0x03, 0x0F, 0x05, 0x0E,\n                0x02, 0x0A, 0x0F, 0x0A, 0x02, 0x0E,/*藕1999*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFE, 0x02, 0x0A, 0x32, 0xC2, 0x3A, 0x02, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x08, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*呕2000*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xC0, 0x5F, 0x55, 0xFF, 0x55, 0x55, 0x5F, 0xC0, 0x00, 0x0F, 0x00, 0x0F, 0x00,\n                0x02, 0x03, 0x02, 0x07, 0x08, 0x0F,/*偶2001*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x02, 0x0A, 0xB2, 0x42, 0xB2, 0x0E, 0x02, 0x04, 0x02, 0x00, 0x0F, 0x08,\n                0x0A, 0x09, 0x08, 0x08, 0x0B, 0x08,/*沤2002*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x88, 0x88, 0xFF, 0x48, 0xFC, 0x46, 0x45, 0xFC, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x0F, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*啪2003*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x07, 0x04, 0x03, 0x0A, 0x06,\n                0x01, 0x00, 0x00, 0x01, 0x06, 0x08,/*趴2004*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x01, 0xFE, 0x22, 0x3E, 0x22, 0xBE, 0x0F, 0x00, 0x0F, 0x00, 0x03,\n                0x04, 0x09, 0x0A, 0x0A, 0x0A, 0x0B,/*爬2005*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xFC, 0x46, 0x45, 0x44, 0xFC, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*帕2006*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0xFC, 0x44, 0x46, 0x45, 0x44, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*怕2007*/},\n        {\n\n                0x11, 0xD5, 0x5F, 0x55, 0x51, 0xC0, 0x51, 0x55, 0x5F, 0xD5, 0x11, 0x00, 0x07, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x0C,/*琶2008*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFC, 0x44, 0x46, 0x45, 0x44, 0xFC, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*拍2009*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x24, 0x24, 0xFF, 0x00, 0xFF, 0x24, 0x24, 0x00, 0x08, 0x0F, 0x00, 0x01,\n                0x01, 0x0F, 0x00, 0x0F, 0x01, 0x01,/*排2010*/},\n        {\n\n                0x00, 0xFE, 0x90, 0x9F, 0x10, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x08, 0x07, 0x00, 0x0F, 0x02,\n                0x03, 0x02, 0x02, 0x0F, 0x02, 0x02,/*牌2011*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x24, 0x24, 0xFF, 0x00, 0xFF, 0x24, 0x24, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x0F, 0x00, 0x0F, 0x01, 0x01,/*徘2012*/},\n        {\n\n                0x22, 0x44, 0x92, 0x92, 0xFF, 0x91, 0x00, 0x29, 0xFF, 0x29, 0x29, 0x04, 0x02, 0x08, 0x04, 0x03,\n                0x00, 0x00, 0x01, 0x0F, 0x01, 0x01,/*湃2013*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xFE, 0x02, 0xFA, 0x0A, 0xF9, 0x45, 0x20, 0x04, 0x02, 0x01, 0x08, 0x07,\n                0x00, 0x0F, 0x04, 0x01, 0x06, 0x08,/*派2014*/},\n        {\n\n                0x2A, 0xA6, 0x7F, 0xAA, 0xB5, 0xAA, 0xB5, 0xAA, 0x7F, 0xA6, 0x2A, 0x01, 0x00, 0x02, 0x02, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x00, 0x01,/*攀2015*/},\n        {\n\n                0x22, 0x44, 0x90, 0xD6, 0xBA, 0x92, 0xBE, 0x91, 0xB9, 0xD5, 0x90, 0x04, 0x02, 0x00, 0x0F, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0F, 0x00,/*潘2016*/},\n        {\n\n                0x90, 0x50, 0x3E, 0x12, 0x37, 0x5A, 0x12, 0x52, 0x7E, 0x10, 0x10, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盘2017*/},\n        {\n\n                0xC8, 0xBE, 0x8B, 0xAE, 0xCA, 0xFE, 0x84, 0xDB, 0xA9, 0xDB, 0x84, 0x08, 0x04, 0x0E, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*磐2018*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x10, 0x2C, 0xE3, 0x20, 0x23, 0xEC, 0x10, 0x0F, 0x04, 0x04, 0x07, 0x08,\n                0x06, 0x01, 0x08, 0x08, 0x07, 0x00,/*盼2019*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x80, 0x92, 0x94, 0xFF, 0x94, 0x92, 0x07, 0x02, 0x03, 0x02, 0x07,\n                0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,/*畔2020*/},\n        {\n\n                0x80, 0x92, 0x94, 0xFF, 0x94, 0x92, 0x80, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x01, 0x08, 0x08, 0x0F,/*判2021*/},\n        {\n\n                0x92, 0x94, 0xFF, 0x94, 0x82, 0xFC, 0x24, 0xE4, 0x24, 0x22, 0xE2, 0x08, 0x04, 0x03, 0x08, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*叛2022*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x03, 0x05, 0x09, 0x01,/*乓2023*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x22, 0xFA, 0x22, 0xE3, 0x2A, 0x32, 0xA2, 0x22, 0x08, 0x07, 0x08, 0x06, 0x01,\n                0x08, 0x07, 0x0A, 0x09, 0x08, 0x0E,/*庞2024*/},\n        {\n\n                0xB0, 0x92, 0x96, 0x9A, 0xB2, 0xD3, 0x92, 0x9A, 0x96, 0x92, 0xB0, 0x08, 0x08, 0x04, 0x03, 0x02,\n                0x02, 0x02, 0x0A, 0x0A, 0x06, 0x00,/*旁2025*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x00, 0xB2, 0x96, 0xBB, 0xDA, 0x96, 0xB2, 0x02, 0x01, 0x0F, 0x01, 0x00,\n                0x08, 0x07, 0x02, 0x0A, 0x0A, 0x06,/*耪2026*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x82, 0x94, 0x90, 0xFF, 0x90, 0x94, 0x82, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*胖2027*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x10, 0xFF, 0x10, 0xF0, 0x04, 0xFF, 0x04, 0xFC, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x07, 0x09, 0x08, 0x09, 0x0D,/*抛2028*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x08, 0xF7, 0x94, 0x94, 0xF4, 0x04, 0xFC, 0x00, 0x03, 0x01, 0x03, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x09, 0x09, 0x0E,/*咆2029*/},\n        {\n\n                0x10, 0xFC, 0x97, 0x94, 0xF4, 0x04, 0xFC, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x09, 0x0D, 0x00, 0x01, 0x08, 0x0F,/*刨2030*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x08, 0xF4, 0x97, 0x94, 0xF4, 0x04, 0xFC, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x09, 0x0D,/*炮2031*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x08, 0xF4, 0x97, 0x94, 0xF4, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x09, 0x0D,/*袍2032*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x08, 0xF4, 0x97, 0x94, 0xF4, 0x04, 0xFC, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x09, 0x0D,/*跑2033*/},\n        {\n\n                0x22, 0x44, 0x10, 0x08, 0xF7, 0x94, 0x94, 0xF4, 0x04, 0xFC, 0x00, 0x04, 0x02, 0x01, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x09, 0x09, 0x0E,/*泡2034*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x82, 0x42, 0x22, 0xFA, 0x06, 0x22, 0xC2, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x08, 0x08, 0x0B, 0x08, 0x08, 0x08,/*呸2035*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x80, 0x42, 0x22, 0xFA, 0x06, 0x22, 0xC2, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x08, 0x08, 0x0B, 0x08, 0x08, 0x08,/*胚2036*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x20, 0xAA, 0xB2, 0xA2, 0xA3, 0xB2, 0xAA, 0x20, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*培2037*/},\n        {\n\n                0xA2, 0xAA, 0xAA, 0xFF, 0x80, 0xC0, 0x80, 0xFF, 0xAA, 0xAA, 0xA2, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*裴2038*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*赔2039*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x20, 0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x20, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*陪2040*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x00, 0xE2, 0x22, 0x3E, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x07, 0x08, 0x0E,/*配2041*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xFE, 0x2A, 0xFA, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x08, 0x07, 0x00,\n                0x0F, 0x02, 0x03, 0x00, 0x07, 0x0C,/*佩2042*/},\n        {\n\n                0x11, 0x22, 0x04, 0xE4, 0x24, 0x24, 0xFF, 0x24, 0x24, 0xE4, 0x04, 0x04, 0x02, 0x00, 0x07, 0x00,\n                0x00, 0x0F, 0x00, 0x04, 0x07, 0x00,/*沛2043*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xD2, 0x7A, 0x52, 0x57, 0x52, 0x7A, 0xD2, 0x03, 0x01, 0x03, 0x00, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*喷2044*/},\n        {\n\n                0x08, 0x44, 0x4A, 0x29, 0x18, 0x08, 0x48, 0x49, 0x3A, 0x04, 0x08, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盆2045*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x88, 0xB2, 0x82, 0xFE, 0x82, 0xA2, 0x98, 0x00, 0x0F, 0x04, 0x0F, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*砰2046*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x88, 0xB2, 0x82, 0xFE, 0x82, 0xA2, 0x98, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*抨2047*/},\n        {\n\n                0x02, 0x82, 0xBA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBA, 0x02, 0x02, 0x08, 0x04, 0x00, 0x04, 0x08,\n                0x04, 0x06, 0x09, 0x00, 0x04, 0x08,/*烹2048*/},\n        {\n\n                0x22, 0x44, 0x02, 0xEA, 0xAA, 0xAF, 0xAA, 0xEA, 0x44, 0x22, 0x11, 0x04, 0x02, 0x08, 0x09, 0x0A,\n                0x04, 0x06, 0x05, 0x08, 0x04, 0x02,/*澎2049*/},\n        {\n\n                0x02, 0xEA, 0xAA, 0xAF, 0xAA, 0xEA, 0x00, 0x88, 0x44, 0x23, 0x18, 0x08, 0x09, 0x0A, 0x04, 0x06,\n                0x05, 0x08, 0x08, 0x04, 0x02, 0x01,/*彭2050*/},\n        {\n\n                0x26, 0xEA, 0x42, 0x57, 0xDA, 0xAE, 0xEA, 0xAF, 0xDA, 0x42, 0x42, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*蓬2051*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x92, 0xFE, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x08, 0x0F, 0x08, 0x07, 0x08, 0x0F,/*棚2052*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0x22, 0xFF, 0x49, 0xFF, 0x00, 0xFF, 0x91, 0xFF, 0x00, 0x07, 0x02, 0x0A, 0x07,\n                0x08, 0x0F, 0x04, 0x03, 0x08, 0x0F,/*硼2053*/},\n        {\n\n                0x24, 0xEB, 0x42, 0x56, 0xDA, 0xAC, 0xEB, 0xAA, 0xDE, 0x42, 0x42, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*篷2054*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x02, 0xEA, 0xAF, 0xEA, 0x02, 0x88, 0x66, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x06, 0x04, 0x06, 0x04, 0x08, 0x06,/*膨2055*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x08, 0x07, 0x00, 0x08, 0x0F,/*朋2056*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0xAB, 0x9E, 0x07, 0x08, 0x0F, 0x08, 0x07,\n                0x08, 0x0F, 0x00, 0x0A, 0x0A, 0x07,/*鹏2057*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xA2, 0x6A, 0x3A, 0xAF, 0x2A, 0x6A, 0xA2, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x04,/*捧2058*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x48, 0x89, 0xFA, 0x08, 0xFA, 0x89, 0x48, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x08,/*碰2059*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x82, 0x42, 0x22, 0xFA, 0x06, 0x22, 0xC2, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x08, 0x08, 0x0B, 0x08, 0x08, 0x08,/*坯2060*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFF, 0x10, 0x10, 0xFF, 0x10, 0x0C, 0x00, 0x0F, 0x04, 0x0F, 0x00,\n                0x0F, 0x04, 0x02, 0x07, 0x08, 0x0E,/*砒2061*/},\n        {\n\n                0x0C, 0xE5, 0xA5, 0xAD, 0xE5, 0x0F, 0x25, 0x6D, 0xB5, 0x65, 0x2C, 0x04, 0x03, 0x0E, 0x0A, 0x0E,\n                0x00, 0x01, 0x05, 0x0F, 0x05, 0x01,/*霹2062*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFF, 0x10, 0x10, 0xFF, 0x20, 0x10, 0x0C, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x02, 0x07, 0x08, 0x08, 0x0E,/*批2063*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xFC, 0x24, 0xE4, 0x3F, 0xE4, 0x0C, 0x00, 0x08, 0x0F, 0x08, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*披2064*/},\n        {\n\n                0x20, 0x1F, 0x75, 0x55, 0x77, 0x00, 0x0A, 0x2E, 0x7B, 0x2E, 0x0A, 0x00, 0x09, 0x09, 0x05, 0x03,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*劈2065*/},\n        {\n\n                0x11, 0xD5, 0x1F, 0x15, 0x11, 0x00, 0xD1, 0x15, 0x9F, 0x55, 0x11, 0x00, 0x0F, 0x09, 0x05, 0x05,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*琵2066*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x00, 0xFF, 0x10, 0xFF, 0x10, 0x0C, 0x07, 0x02, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x04, 0x07, 0x08, 0x0E,/*毗2067*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x00, 0x03, 0x01, 0x03, 0x02, 0x03,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*啤2068*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x03, 0x02, 0x02, 0x0F, 0x02, 0x02,/*脾2069*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0xF4, 0x95, 0x96, 0xFC, 0x94, 0x94, 0x34, 0x09, 0x04, 0x0B, 0x04, 0x03,\n                0x08, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*疲2070*/},\n        {\n\n                0x00, 0xFC, 0x24, 0x64, 0xA4, 0x24, 0x3F, 0x24, 0xA4, 0x64, 0x0C, 0x08, 0x07, 0x08, 0x08, 0x04,\n                0x05, 0x02, 0x05, 0x04, 0x08, 0x08,/*皮2071*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x82, 0x7E, 0x02, 0x02, 0xFE, 0x02, 0x02, 0xC2, 0x00, 0x0F, 0x0A, 0x09, 0x08,\n                0x08, 0x08, 0x08, 0x09, 0x09, 0x09,/*匹2072*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x94, 0x95, 0x56, 0xF4, 0x14, 0x54, 0x94, 0x09, 0x04, 0x03, 0x00, 0x0E,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x0E,/*痞2073*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xFE, 0x92, 0x9E, 0x40, 0x55, 0xE6, 0x54, 0x40, 0x00, 0x0F, 0x01, 0x0F, 0x04,\n                0x0F, 0x00, 0x02, 0x0F, 0x02, 0x00,/*僻2074*/},\n        {\n\n                0x00, 0xFF, 0x05, 0xF5, 0x45, 0x45, 0x05, 0xF5, 0x05, 0x87, 0x60, 0x08, 0x07, 0x00, 0x0F, 0x08,\n                0x04, 0x00, 0x07, 0x09, 0x08, 0x0E,/*屁2075*/},\n        {\n\n                0xA0, 0x9F, 0xF5, 0xD5, 0xF7, 0x80, 0xCA, 0xAE, 0xFB, 0xAE, 0x8A, 0x00, 0x02, 0x0E, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0E, 0x02, 0x00,/*譬2076*/},\n        {\n\n                0x04, 0xFB, 0xAA, 0xAE, 0xAA, 0xAC, 0xAB, 0xAA, 0xAE, 0xAA, 0xBA, 0x02, 0x01, 0x0F, 0x02, 0x02,\n                0x07, 0x02, 0x07, 0x02, 0x0A, 0x0F,/*篇2077*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x80, 0xFE, 0x2A, 0xEA, 0x2B, 0xEA, 0x2A, 0xEE, 0x00, 0x0F, 0x01, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*偏2078*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x90, 0x90, 0x90, 0x90, 0x9F, 0x90, 0x10, 0x10, 0x08, 0x06, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,/*片2079*/},\n        {\n\n                0x7A, 0x42, 0xDE, 0x80, 0xFE, 0x2A, 0xEA, 0x2B, 0xEA, 0x2A, 0xEE, 0x0A, 0x09, 0x07, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*骗2080*/},\n        {\n\n                0x1D, 0x55, 0x5F, 0x55, 0x1D, 0xFE, 0x12, 0xE2, 0x12, 0xFE, 0x00, 0x05, 0x09, 0x0F, 0x01, 0x0D,\n                0x07, 0x01, 0x00, 0x01, 0x07, 0x0C,/*飘2081*/},\n        {\n\n                0x11, 0x22, 0x01, 0x5D, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x5D, 0x01, 0x04, 0x02, 0x09, 0x05, 0x01,\n                0x09, 0x0F, 0x01, 0x01, 0x05, 0x09,/*漂2082*/},\n        {\n\n                0x1D, 0x55, 0x5F, 0x55, 0x1D, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x05, 0x09, 0x0F, 0x01, 0x05,\n                0x08, 0x07, 0x00, 0x0F, 0x0A, 0x0C,/*瓢2083*/},\n        {\n\n                0x01, 0x5D, 0x55, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x55, 0x5D, 0x01, 0x01, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x01,/*票2084*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xF2, 0x94, 0xFF, 0x54, 0xFA, 0x0F, 0xF8, 0x08, 0x08, 0x0F, 0x00, 0x0F, 0x00,\n                0x07, 0x08, 0x05, 0x02, 0x05, 0x08,/*撇2085*/},\n        {\n\n                0x7D, 0x26, 0x14, 0x7F, 0x16, 0x3D, 0x44, 0x2B, 0x12, 0x2E, 0x42, 0x00, 0x0F, 0x09, 0x0B, 0x0D,\n                0x09, 0x0B, 0x0D, 0x09, 0x0F, 0x00,/*瞥2086*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x80, 0x89, 0xFA, 0x88, 0x88, 0xFA, 0x89, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*拼2087*/},\n        {\n\n                0x10, 0xDE, 0x10, 0xFF, 0x12, 0x92, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x09, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*频2088*/},\n        {\n\n                0x04, 0xE2, 0x55, 0x4C, 0x44, 0xC4, 0x54, 0x54, 0x4D, 0xC2, 0x04, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贫2089*/},\n        {\n\n                0xC0, 0x40, 0x5F, 0x51, 0xD1, 0x11, 0xD1, 0x51, 0x5F, 0x40, 0xC0, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*品2090*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x02, 0xBE, 0xAA, 0xBF, 0xAA, 0xAA, 0xBE, 0x02, 0x03, 0x02, 0x0F, 0x01,\n                0x00, 0x03, 0x02, 0x0A, 0x0A, 0x06,/*聘2091*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x00, 0x01, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x01, 0x01, 0x01, 0x01,/*乒2092*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x88, 0xB2, 0x82, 0xFE, 0x82, 0xA2, 0x98, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*坪2093*/},\n        {\n\n                0x02, 0x12, 0x52, 0x97, 0x12, 0xF2, 0x12, 0x97, 0x52, 0x12, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*苹2094*/},\n        {\n\n                0x4A, 0x92, 0x02, 0x57, 0x92, 0x12, 0xF2, 0x17, 0x92, 0x52, 0x02, 0x08, 0x04, 0x01, 0x01, 0x01,\n                0x01, 0x0F, 0x01, 0x01, 0x01, 0x01,/*萍2095*/},\n        {\n\n                0x80, 0x8A, 0xB2, 0x82, 0x82, 0xFE, 0x82, 0x82, 0xA2, 0x9A, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*平2096*/},\n        {\n\n                0x08, 0x04, 0xBE, 0x81, 0x88, 0xAA, 0xAA, 0xBE, 0x29, 0x29, 0x08, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*凭2097*/},\n        {\n\n                0x89, 0xFA, 0x88, 0xFA, 0x89, 0xC2, 0xBE, 0x12, 0xF2, 0x02, 0x00, 0x08, 0x07, 0x00, 0x0F, 0x00,\n                0x0F, 0x04, 0x01, 0x07, 0x08, 0x0E,/*瓶2098*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x88, 0xB2, 0x82, 0xFE, 0x82, 0xA2, 0x98, 0x00, 0x00, 0x07, 0x02, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*评2099*/},\n        {\n\n                0x00, 0xFF, 0x05, 0x25, 0x2D, 0xF5, 0x25, 0x25, 0xF5, 0x2D, 0x27, 0x08, 0x07, 0x01, 0x09, 0x05,\n                0x03, 0x01, 0x01, 0x0F, 0x01, 0x01,/*屏2100*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0xFC, 0x24, 0xE4, 0x3F, 0x24, 0xE4, 0x0C, 0x02, 0x02, 0x01, 0x09, 0x07,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*坡2101*/},\n        {\n\n                0x22, 0x44, 0x00, 0x0E, 0x88, 0x78, 0xCF, 0x48, 0x48, 0x49, 0xCA, 0x04, 0x02, 0x08, 0x06, 0x01,\n                0x08, 0x08, 0x05, 0x02, 0x05, 0x08,/*泼2102*/},\n        {\n\n                0x00, 0xFC, 0x24, 0x3F, 0xE4, 0x0C, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x04, 0x0B, 0x05, 0x02, 0x0D,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颇2103*/},\n        {\n\n                0x44, 0x29, 0x02, 0x40, 0xBE, 0x4A, 0x5A, 0x2F, 0x2A, 0x5A, 0x46, 0x09, 0x09, 0x0B, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*婆2104*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFC, 0x24, 0xE4, 0x3F, 0xE4, 0x0C, 0x00, 0x07, 0x02, 0x0B, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*破2105*/},\n        {\n\n                0xFC, 0x26, 0xFD, 0x00, 0x7C, 0x54, 0xF6, 0x5D, 0xD4, 0x7C, 0x00, 0x07, 0x02, 0x03, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x0A, 0x0B, 0x0C,/*魄2106*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xFC, 0x24, 0x26, 0x25, 0x24, 0x24, 0xFC, 0x08, 0x04, 0x03, 0x04, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x09,/*迫2107*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x24, 0x00, 0xFC, 0x46, 0x45, 0x44, 0xFC, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*粕2108*/},\n        {\n\n                0x20, 0xAA, 0xB2, 0xA2, 0xA3, 0xB2, 0xAA, 0x20, 0xFC, 0x00, 0xFF, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*剖2109*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x48, 0x00, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*扑2110*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xF4, 0x54, 0x54, 0xFF, 0x54, 0x55, 0xF6, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*铺2111*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x00, 0x00, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*仆2112*/},\n        {\n\n                0x0A, 0xEA, 0xAA, 0xAF, 0xAA, 0xFE, 0xAA, 0xAF, 0xAA, 0xEE, 0x0A, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x07, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*莆2113*/},\n        {\n\n                0x32, 0xEE, 0xAA, 0xAF, 0xFA, 0xAA, 0xBA, 0xEF, 0x2A, 0x0A, 0xFA, 0x00, 0x0F, 0x02, 0x02, 0x07,\n                0x02, 0x0A, 0x0F, 0x00, 0x08, 0x0F,/*葡2114*/},\n        {\n\n                0x42, 0x52, 0x72, 0x57, 0x52, 0x5A, 0x52, 0x57, 0x72, 0x52, 0x42, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*菩2115*/},\n        {\n\n                0x4A, 0x92, 0x0A, 0xEF, 0xAA, 0xAA, 0xFE, 0xAF, 0xAA, 0xEE, 0x0A, 0x04, 0x02, 0x00, 0x0F, 0x02,\n                0x02, 0x07, 0x02, 0x0A, 0x0F, 0x00,/*蒲2116*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xF4, 0x54, 0x54, 0xFF, 0x54, 0x55, 0xF6, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*埔2117*/},\n        {\n\n                0x08, 0x88, 0x68, 0xFF, 0x28, 0x48, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x01, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*朴2118*/},\n        {\n\n                0xFF, 0x05, 0xF5, 0x55, 0x55, 0xFF, 0x55, 0x55, 0xF7, 0x05, 0xFF, 0x0F, 0x08, 0x0F, 0x09, 0x09,\n                0x0B, 0x09, 0x0D, 0x0F, 0x08, 0x0F,/*圃2119*/},\n        {\n\n                0x20, 0x22, 0xAA, 0xB3, 0xBE, 0xA2, 0xA2, 0xBE, 0xB3, 0xAA, 0x22, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*普2120*/},\n        {\n\n                0x11, 0x22, 0x04, 0xF4, 0x54, 0x54, 0xFF, 0x54, 0x55, 0xF6, 0x04, 0x04, 0x02, 0x01, 0x0F, 0x01,\n                0x01, 0x07, 0x01, 0x09, 0x0F, 0x00,/*浦2121*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x2A, 0xA3, 0xBE, 0xA2, 0xBE, 0xA3, 0x2A, 0x00, 0x00, 0x07, 0x02, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*谱2122*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0x5F, 0xF5, 0x55, 0x55, 0xF5, 0x5F, 0x00, 0x07, 0x02, 0x07, 0x05, 0x0B,\n                0x05, 0x09, 0x0F, 0x05, 0x0B, 0x05,/*曝2123*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0x5F, 0xF5, 0x55, 0x55, 0xF5, 0x5F, 0x00, 0x04, 0x02, 0x01, 0x05, 0x0B,\n                0x05, 0x09, 0x0F, 0x05, 0x0B, 0x05,/*瀑2124*/},\n        {\n\n                0x04, 0xFF, 0x54, 0x54, 0xFF, 0x04, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x09, 0x05, 0x01, 0x01, 0x05,\n                0x09, 0x08, 0x07, 0x00, 0x08, 0x0F,/*期2125*/},\n        {\n\n                0x04, 0xFF, 0x54, 0x54, 0xFF, 0x04, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x09, 0x05, 0x01, 0x01, 0x05,\n                0x09, 0x08, 0x06, 0x01, 0x06, 0x08,/*欺2126*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xF2, 0x12, 0xFE, 0x12, 0xFE, 0x92, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x04, 0x0F,/*栖2127*/},\n        {\n\n                0x00, 0xFC, 0x44, 0x44, 0xFC, 0x54, 0x54, 0x04, 0xFF, 0x04, 0xE5, 0x08, 0x07, 0x02, 0x09, 0x0F,\n                0x01, 0x0A, 0x04, 0x03, 0x05, 0x0E,/*戚2128*/},\n        {\n\n                0x22, 0x2A, 0x2A, 0x2A, 0xAA, 0x7F, 0x2A, 0x2A, 0x2A, 0x7A, 0x22, 0x09, 0x09, 0x0B, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*妻2129*/},\n        {\n\n                0x20, 0x20, 0x20, 0x20, 0xFF, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*七2130*/},\n        {\n\n                0x04, 0x08, 0x22, 0x2A, 0x2A, 0xAA, 0x7F, 0x2A, 0x2A, 0x7A, 0x22, 0x04, 0x02, 0x09, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x09,/*凄2131*/},\n        {\n\n                0x22, 0x44, 0x00, 0x4A, 0xA6, 0x12, 0xCF, 0x12, 0xA6, 0x4A, 0x40, 0x04, 0x02, 0x00, 0x04, 0x02,\n                0x09, 0x0F, 0x01, 0x02, 0x04, 0x00,/*漆2132*/},\n        {\n\n                0x84, 0xC9, 0xA2, 0x88, 0x88, 0xC8, 0x9F, 0xA4, 0xA4, 0xA4, 0xB4, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*柒2133*/},\n        {\n\n                0x22, 0x44, 0x10, 0xFF, 0x10, 0x92, 0x02, 0xFE, 0x02, 0x02, 0xFE, 0x04, 0x02, 0x00, 0x03, 0x09,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*沏2134*/},\n        {\n\n                0x04, 0x04, 0xFF, 0x54, 0x54, 0x54, 0x54, 0x54, 0xFF, 0x04, 0x04, 0x01, 0x09, 0x05, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x05, 0x09, 0x01,/*其2135*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x04, 0xFF, 0x54, 0x54, 0x54, 0xFF, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x05, 0x01, 0x01, 0x01, 0x05, 0x09,/*棋2136*/},\n        {\n\n                0x10, 0xD2, 0x5A, 0x56, 0x53, 0xD2, 0x16, 0x1A, 0xF2, 0x12, 0x10, 0x00, 0x07, 0x02, 0x02, 0x02,\n                0x03, 0x08, 0x08, 0x0F, 0x00, 0x00,/*奇2137*/},\n        {\n\n                0x00, 0xF8, 0x00, 0xFF, 0x08, 0x20, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x04, 0x07, 0x04, 0x03, 0x02,\n                0x08, 0x08, 0x05, 0x02, 0x05, 0x08,/*歧2138*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x00, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x07, 0x02, 0x03, 0x02, 0x07,\n                0x08, 0x09, 0x09, 0x0F, 0x09, 0x09,/*畦2139*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x10, 0xDA, 0x56, 0xD3, 0x16, 0xFA, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x07, 0x02, 0x03, 0x08, 0x0F,/*崎2140*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x44, 0xAC, 0x15, 0x16, 0xAC, 0x44, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*脐2141*/},\n        {\n\n                0x84, 0x84, 0x4C, 0xD4, 0x24, 0x25, 0x26, 0xD4, 0x4C, 0x84, 0x84, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*齐2142*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x04, 0x0B, 0xFE, 0xAA, 0xAA, 0xFE, 0x0A, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0A, 0x07, 0x02, 0x02, 0x07, 0x0A,/*旗2143*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x00, 0x0F, 0x00,/*祈2144*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0x80, 0x00, 0xFE, 0x02, 0x12, 0x2A, 0xC6, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x00, 0x02, 0x02, 0x01,/*祁2145*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x10, 0xDA, 0x56, 0xD3, 0x16, 0xFA, 0x10, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x07, 0x02, 0x03, 0x08, 0x0F, 0x00,/*骑2146*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xFF, 0x24, 0x00, 0xF2, 0x12, 0x12, 0x1E, 0x80, 0x08, 0x07, 0x04, 0x0F, 0x09,\n                0x08, 0x09, 0x0A, 0x0A, 0x0A, 0x0B,/*起2147*/},\n        {\n\n                0x00, 0x2E, 0x28, 0x28, 0x28, 0x2F, 0x28, 0x28, 0x28, 0xEE, 0x00, 0x00, 0x07, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x0C,/*岂2148*/},\n        {\n\n                0x20, 0x18, 0x27, 0x24, 0xA4, 0xA4, 0x64, 0x64, 0x24, 0x04, 0x00, 0x00, 0x00, 0x06, 0x09, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x0E, 0x00,/*乞2149*/},\n        {\n\n                0x10, 0x10, 0xC8, 0x04, 0x02, 0xF1, 0x82, 0x84, 0x88, 0x90, 0x10, 0x08, 0x08, 0x0F, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*企2150*/},\n        {\n\n                0x00, 0x00, 0xFC, 0xA4, 0xA4, 0xA5, 0xA6, 0xA4, 0xA4, 0xA4, 0xBC, 0x08, 0x06, 0x01, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*启2151*/},\n        {\n\n                0x22, 0x2A, 0x7F, 0x2A, 0x22, 0xC0, 0x22, 0x1E, 0x42, 0x42, 0x3E, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*契2152*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x10, 0xFF, 0x88, 0x02, 0xFE, 0x02, 0xFE, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*砌2153*/},\n        {\n\n                0x20, 0x27, 0xA5, 0xA5, 0x67, 0x38, 0x67, 0xA5, 0xAD, 0x37, 0x20, 0x01, 0x0F, 0x0A, 0x0A, 0x0E,\n                0x00, 0x0E, 0x0A, 0x0A, 0x0F, 0x01,/*器2154*/},\n        {\n\n                0x08, 0x24, 0x2B, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0xEA, 0x0A, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x0E,/*气2155*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x08, 0x04, 0x17, 0x94, 0x54, 0x34, 0x14, 0x84, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B,/*迄2156*/},\n        {\n\n                0x04, 0x24, 0x34, 0xEC, 0x25, 0x26, 0x24, 0xE4, 0x34, 0x64, 0x04, 0x01, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*弃2157*/},\n        {\n\n                0x22, 0x44, 0x08, 0x24, 0x2B, 0x2A, 0x2A, 0x2A, 0xEA, 0x02, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x0F,/*汽2158*/},\n        {\n\n                0x22, 0x44, 0x00, 0x08, 0x48, 0x88, 0x09, 0x0A, 0x08, 0xE8, 0x08, 0x04, 0x02, 0x09, 0x08, 0x08,\n                0x0B, 0x08, 0x0C, 0x0B, 0x08, 0x08,/*泣2159*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x10, 0x28, 0x27, 0x24, 0xA4, 0xA4, 0x64, 0x04, 0x00, 0x0F, 0x04, 0x00, 0x06,\n                0x09, 0x09, 0x08, 0x08, 0x08, 0x0E,/*讫2160*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x08, 0xE4, 0xA3, 0x92, 0x02, 0xAA, 0xA6, 0xE0, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*掐2161*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x10, 0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*恰2162*/},\n        {\n\n                0x22, 0x44, 0x20, 0x90, 0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0x90, 0x20, 0x04, 0x02, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*洽2163*/},\n        {\n\n                0x30, 0x12, 0xD2, 0x9A, 0x96, 0xD3, 0x96, 0x9A, 0x92, 0x92, 0x30, 0x02, 0x03, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*牵2164*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*扦2165*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*钎2166*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x10, 0xCF, 0x41, 0x41, 0x41, 0xCF, 0x10, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*铅2167*/},\n        {\n\n                0x40, 0x44, 0x44, 0x44, 0x44, 0xFC, 0x42, 0x42, 0x42, 0x42, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*千2168*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*迁2169*/},\n        {\n\n                0x44, 0x43, 0xA6, 0xAA, 0x92, 0x88, 0x94, 0xA3, 0xA6, 0x4A, 0x42, 0x08, 0x08, 0x0A, 0x0C, 0x09,\n                0x0A, 0x08, 0x0C, 0x0A, 0x08, 0x08,/*签2170*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*仟2171*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x54, 0x55, 0xFE, 0x54, 0xFE, 0x55, 0xF4, 0x44, 0x00, 0x07, 0x02, 0x05, 0x03,\n                0x0F, 0x01, 0x0F, 0x03, 0x05, 0x08,/*谦2172*/},\n        {\n\n                0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x08, 0x24, 0x27, 0xA4, 0x64, 0x04, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x00, 0x06, 0x09, 0x08, 0x08, 0x0E,/*乾2173*/},\n        {\n\n                0x5F, 0x55, 0x51, 0xFF, 0x55, 0x7F, 0x90, 0x8C, 0xA3, 0x8C, 0x90, 0x0A, 0x06, 0x0A, 0x05, 0x09,\n                0x05, 0x08, 0x00, 0x08, 0x06, 0x01,/*黔2174*/},\n        {\n\n                0x98, 0xF7, 0x94, 0xC4, 0x48, 0x48, 0xFF, 0x48, 0x25, 0xA6, 0x24, 0x00, 0x0F, 0x04, 0x0A, 0x08,\n                0x04, 0x04, 0x03, 0x05, 0x08, 0x0E,/*钱2175*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x80, 0x04, 0xFF, 0x44, 0x44, 0x44, 0xFF, 0x04, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*钳2176*/},\n        {\n\n                0x04, 0xF4, 0x55, 0x56, 0x54, 0xF4, 0x04, 0xE6, 0x05, 0xF4, 0x04, 0x00, 0x0F, 0x01, 0x01, 0x09,\n                0x0F, 0x00, 0x03, 0x08, 0x0F, 0x00,/*前2177*/},\n        {\n\n                0x22, 0x44, 0x48, 0xAA, 0x9F, 0xAA, 0xC0, 0xAA, 0x9F, 0xAA, 0x48, 0x04, 0x02, 0x00, 0x0F, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*潜2178*/},\n        {\n\n                0x11, 0xF2, 0x20, 0x2E, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0x2E, 0x20, 0x08, 0x07, 0x08, 0x08, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x08,/*遣2179*/},\n        {\n\n                0x10, 0x22, 0x04, 0x40, 0x48, 0x48, 0xFF, 0x48, 0x25, 0xA6, 0x24, 0x04, 0x02, 0x01, 0x08, 0x08,\n                0x04, 0x04, 0x03, 0x05, 0x08, 0x0E,/*浅2180*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x42, 0xC4, 0x2E, 0xEA, 0xBF, 0xAA, 0xEE, 0x20, 0x00, 0x07, 0x02, 0x08, 0x07,\n                0x08, 0x0F, 0x0A, 0x0A, 0x0E, 0x08,/*谴2181*/},\n        {\n\n                0x42, 0x5A, 0x56, 0xFB, 0x52, 0x80, 0x7E, 0x0A, 0xFA, 0x09, 0x08, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*堑2182*/},\n        {\n\n                0x20, 0xF6, 0x24, 0x24, 0xF4, 0x27, 0x44, 0x3C, 0xA4, 0x26, 0x60, 0x00, 0x0F, 0x09, 0x09, 0x0F,\n                0x00, 0x08, 0x06, 0x01, 0x06, 0x08,/*嵌2183*/},\n        {\n\n                0x20, 0x18, 0x07, 0x04, 0x84, 0x74, 0x84, 0x04, 0x24, 0x1C, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*欠2184*/},\n        {\n\n                0x44, 0x55, 0xFE, 0x54, 0xFE, 0x55, 0xF4, 0x50, 0x0F, 0xC4, 0x1C, 0x05, 0x03, 0x0F, 0x01, 0x0F,\n                0x03, 0x05, 0x08, 0x06, 0x01, 0x0E,/*歉2185*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0xE8, 0x24, 0x23, 0x24, 0xE8, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x09, 0x09, 0x0C,/*枪2186*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x10, 0xE8, 0x24, 0x23, 0x24, 0xE8, 0x10, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x07, 0x08, 0x08, 0x09, 0x09, 0x0C,/*呛2187*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x4C, 0xA4, 0x95, 0x86, 0x94, 0xA4, 0x4C, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*腔2188*/},\n        {\n\n                0x40, 0x44, 0x55, 0x56, 0xF4, 0x5C, 0xD4, 0x56, 0x55, 0x44, 0x40, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0C,/*羌2189*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xEA, 0x2E, 0xAA, 0xAF, 0xAA, 0x2E, 0xEA, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x08, 0x0B, 0x0A, 0x0B, 0x08, 0x0F,/*墙2190*/},\n        {\n\n                0x82, 0x92, 0xB2, 0xD7, 0x92, 0xFA, 0x92, 0xD7, 0xB2, 0x92, 0x82, 0x00, 0x0F, 0x08, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0E, 0x08, 0x0F, 0x00,/*蔷2191*/},\n        {\n\n                0xF2, 0x92, 0x9E, 0x00, 0xE0, 0x2F, 0x29, 0xF9, 0x29, 0x2F, 0xE0, 0x08, 0x08, 0x07, 0x00, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x0D, 0x09,/*强2192*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0xE8, 0x24, 0x23, 0x24, 0xE8, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x09, 0x09, 0x0C,/*抢2193*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0x20, 0x2A, 0xAA, 0x3E, 0x55, 0x55, 0xD0, 0x60, 0x00, 0x0F, 0x00, 0x05, 0x0F,\n                0x0A, 0x00, 0x05, 0x0F, 0x0A, 0x0C,/*橇2194*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x92, 0xFE, 0x51, 0x08, 0xFF, 0x10, 0x0C, 0x00, 0x0F, 0x04, 0x01, 0x00,\n                0x0F, 0x08, 0x07, 0x00, 0x07, 0x08,/*锹2195*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x82, 0x20, 0xE0, 0x3F, 0xE4, 0x0F, 0x00, 0x0E, 0x0A, 0x0E,\n                0x00, 0x0F, 0x08, 0x05, 0x02, 0x0D,/*敲2196*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xF2, 0x54, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x01, 0x09, 0x0F,/*悄2197*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0x48, 0xAA, 0x1A, 0x0E, 0x19, 0xA9, 0x48, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x0F, 0x00,/*桥2198*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x10, 0xFC, 0x57, 0x54, 0xFD, 0x56, 0x54, 0x04, 0x0F, 0x04, 0x07, 0x0C, 0x03,\n                0x05, 0x09, 0x05, 0x09, 0x05, 0x09,/*瞧2199*/},\n        {\n\n                0x88, 0x8A, 0x4A, 0xAA, 0x1A, 0x0E, 0x19, 0xA9, 0x49, 0x88, 0x88, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*乔2200*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x48, 0xAA, 0x1A, 0x0E, 0x19, 0xA9, 0x48, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x0F, 0x00,/*侨2201*/},\n        {\n\n                0x04, 0x04, 0xFC, 0x04, 0x00, 0x62, 0x5A, 0x46, 0x42, 0x42, 0xC2, 0x02, 0x02, 0x01, 0x01, 0x01,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*巧2202*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x00, 0xF2, 0x54, 0x5F, 0x54, 0xF2, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x00, 0x0F, 0x01, 0x01, 0x09, 0x0F,/*鞘2203*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x20, 0x2A, 0xAA, 0x3E, 0x55, 0x55, 0xD0, 0x60, 0x08, 0x0F, 0x00, 0x05, 0x0F,\n                0x0A, 0x00, 0x05, 0x0F, 0x0A, 0x0C,/*撬2204*/},\n        {\n\n                0xA4, 0xAF, 0x92, 0xAA, 0xB0, 0x8A, 0x52, 0xFE, 0x88, 0x52, 0xFE, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x08, 0x0A, 0x0B, 0x08, 0x0A, 0x0B,/*翘2205*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xF2, 0x54, 0x5F, 0x54, 0xF2, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x01, 0x01, 0x09, 0x0F,/*峭2206*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xF2, 0x54, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x01, 0x09, 0x0F,/*俏2207*/},\n        {\n\n                0x26, 0x22, 0xEA, 0x26, 0x02, 0x23, 0xA2, 0x66, 0x2A, 0x22, 0x26, 0x04, 0x04, 0x03, 0x02, 0x02,\n                0x00, 0x01, 0x01, 0x09, 0x09, 0x07,/*窍2208*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x08, 0x08, 0x02, 0x02, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*切2209*/},\n        {\n\n                0x22, 0x22, 0xF2, 0x27, 0x22, 0xE2, 0x02, 0xE7, 0x22, 0x22, 0xE2, 0x08, 0x06, 0x01, 0x08, 0x08,\n                0x07, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*茄2210*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x92, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x0F, 0x08, 0x08,/*且2211*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x50, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*怯2212*/},\n        {\n\n                0x86, 0x8A, 0xF6, 0x42, 0x42, 0x13, 0x12, 0xF2, 0x16, 0x1A, 0xF6, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*窃2213*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x20, 0x18, 0x07, 0xE4, 0x04, 0x14, 0x0C, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*钦2214*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xC0, 0x51, 0x55, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x00, 0x0F, 0x00, 0x08, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*侵2215*/},\n        {\n\n                0x10, 0x92, 0x96, 0x9A, 0x92, 0xF3, 0x92, 0x9A, 0x96, 0x92, 0x10, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*亲2216*/},\n        {\n\n                0x20, 0xA2, 0x6A, 0xBA, 0xAE, 0xAB, 0xAA, 0xAA, 0x6A, 0xA2, 0x20, 0x01, 0x02, 0x0A, 0x06, 0x02,\n                0x0F, 0x02, 0x06, 0x0A, 0x02, 0x01,/*秦2217*/},\n        {\n\n                0x11, 0x15, 0x9F, 0x95, 0x51, 0xA0, 0x51, 0x95, 0x9F, 0x15, 0x11, 0x01, 0x01, 0x02, 0x02, 0x02,\n                0x02, 0x0B, 0x06, 0x02, 0x01, 0x01,/*琴2218*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x00, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*勤2219*/},\n        {\n\n                0x02, 0x02, 0xF2, 0x97, 0x92, 0x92, 0x92, 0x8F, 0x8A, 0x8A, 0x82, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*芹2220*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x72, 0x46, 0x6D, 0xD7, 0x6D, 0x46, 0x72, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x01, 0x07, 0x05, 0x0F, 0x01, 0x0F,/*擒2221*/},\n        {\n\n                0x04, 0xE4, 0x8C, 0xDA, 0xAA, 0xAD, 0xAA, 0xDA, 0x8C, 0xE4, 0x04, 0x0E, 0x02, 0x0A, 0x0E, 0x0A,\n                0x0B, 0x0E, 0x0A, 0x02, 0x0A, 0x0E,/*禽2222*/},\n        {\n\n                0x16, 0x22, 0xFA, 0x82, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xFA, 0x86, 0x02, 0x01, 0x0F, 0x09, 0x08,\n                0x0B, 0x05, 0x05, 0x0B, 0x08, 0x09,/*寝2223*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xE0, 0x00, 0xF0, 0x01, 0x06, 0x10, 0xE0, 0x04, 0x02, 0x01, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x0E, 0x00,/*沁2224*/},\n        {\n\n                0x22, 0x2A, 0xEA, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xEA, 0x2A, 0x22, 0x00, 0x00, 0x0F, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0F, 0x00, 0x00,/*青2225*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x40, 0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x01, 0x01, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*轻2226*/},\n        {\n\n                0x04, 0x52, 0x55, 0xD5, 0xD5, 0x55, 0x15, 0x15, 0xF5, 0x01, 0x00, 0x09, 0x0B, 0x0B, 0x0E, 0x0A,\n                0x0B, 0x09, 0x00, 0x03, 0x04, 0x0E,/*氢2227*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xFC, 0x20, 0x02, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x00, 0x0F, 0x00, 0x07, 0x02,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*倾2228*/},\n        {\n\n                0xFE, 0x82, 0xF9, 0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x02, 0xFE, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x04, 0x02, 0x04, 0x0F, 0x02, 0x03,/*卿2229*/},\n        {\n\n                0x22, 0x44, 0x22, 0xEA, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xEA, 0x22, 0x04, 0x02, 0x00, 0x0F, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*清2230*/},\n        {\n\n                0x12, 0xBF, 0xAA, 0xBA, 0xCF, 0xBA, 0xC4, 0xAB, 0x92, 0x2E, 0x42, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*擎2231*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0x22, 0x07, 0x02, 0x07, 0x00, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*晴2232*/},\n        {\n\n                0x88, 0xA4, 0xAB, 0xFA, 0xAA, 0xAA, 0xAA, 0x8A, 0xFA, 0x02, 0x02, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x0A, 0x0F, 0x00, 0x03, 0x04, 0x0E,/*氰2233*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0x22, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*情2234*/},\n        {\n\n                0xFF, 0x10, 0x10, 0x00, 0xF9, 0x09, 0x0D, 0xEB, 0x09, 0x09, 0xF9, 0x07, 0x02, 0x01, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*顷2235*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xAA, 0xEA, 0x22, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*请2236*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x44, 0x44, 0x45, 0xF6, 0x44, 0x44, 0x44, 0x44, 0x08, 0x07, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x03, 0x04, 0x08, 0x08,/*庆2237*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x04, 0xF4, 0x95, 0x96, 0x94, 0xF4, 0x04, 0x04, 0x04, 0x03, 0x02, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*琼2238*/},\n        {\n\n                0x0C, 0xA4, 0x94, 0x8C, 0xE5, 0x86, 0x84, 0x8C, 0x94, 0xA4, 0x0C, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x07, 0x00,/*穷2239*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x20, 0x1C, 0x80, 0x7F, 0x80, 0x10, 0x0C, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*秋2240*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0xE1, 0x21, 0x20, 0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*丘2241*/},\n        {\n\n                0x00, 0xFE, 0x12, 0x12, 0xF1, 0x10, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x04, 0x07, 0x04, 0x02, 0x03,\n                0x02, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邱2242*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x08, 0x28, 0xC8, 0xFF, 0x68, 0x89, 0x4A, 0x04, 0x04, 0x03, 0x02, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x01, 0x02,/*球2243*/},\n        {\n\n                0x04, 0x14, 0x24, 0x84, 0x44, 0xFF, 0x34, 0xC4, 0x25, 0x16, 0x04, 0x02, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x04,/*求2244*/},\n        {\n\n                0x00, 0xFF, 0x01, 0x81, 0x61, 0x1D, 0x21, 0x41, 0x81, 0x01, 0xFF, 0x00, 0x0F, 0x09, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x09, 0x08, 0x0F,/*囚2245*/},\n        {\n\n                0x04, 0xF4, 0x95, 0x56, 0x3C, 0x14, 0x7C, 0x56, 0x55, 0xF4, 0x04, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*酋2246*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x02, 0x82, 0x7A, 0x82, 0x02, 0x02, 0xFE, 0x04, 0x02, 0x00, 0x0F, 0x05,\n                0x04, 0x04, 0x04, 0x05, 0x04, 0x0F,/*泅2247*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xFF, 0x24, 0x10, 0xAC, 0xA7, 0xA4, 0xB4, 0xEC, 0x08, 0x07, 0x04, 0x0F, 0x09,\n                0x08, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B,/*趋2248*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x0A, 0x12, 0xA2, 0x42, 0xA2, 0x12, 0x0A, 0x02, 0x00, 0x0F, 0x08, 0x0A, 0x09,\n                0x08, 0x08, 0x08, 0x09, 0x0A, 0x08,/*区2249*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x0F, 0x08, 0x08, 0x0F, 0x08,/*蛆2250*/},\n        {\n\n                0x00, 0xFC, 0x44, 0x44, 0xFF, 0x44, 0x44, 0xFF, 0x44, 0x44, 0xFC, 0x00, 0x0F, 0x04, 0x04, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*曲2251*/},\n        {\n\n                0x80, 0xFE, 0xAB, 0xFE, 0x00, 0xFE, 0x0A, 0x32, 0xC2, 0x3A, 0x02, 0x04, 0x02, 0x09, 0x0F, 0x00,\n                0x0F, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*躯2252*/},\n        {\n\n                0x00, 0x00, 0xFF, 0x05, 0x75, 0x45, 0x45, 0xFD, 0x45, 0x45, 0x77, 0x08, 0x06, 0x01, 0x00, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*屈2253*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x00, 0xFE, 0x0A, 0x32, 0xC2, 0x3A, 0x02, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x0F, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*驱2254*/},\n        {\n\n                0x04, 0x49, 0x22, 0x00, 0x7F, 0xD5, 0x55, 0x55, 0x55, 0x5D, 0x41, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*渠2255*/},\n        {\n\n                0x02, 0xFE, 0x52, 0x52, 0xFE, 0x02, 0x04, 0xFC, 0x04, 0xFC, 0x00, 0x02, 0x03, 0x02, 0x02, 0x0F,\n                0x01, 0x08, 0x04, 0x03, 0x04, 0x08,/*取2256*/},\n        {\n\n                0x41, 0x7F, 0x55, 0x55, 0xFF, 0x21, 0x82, 0x5E, 0x22, 0x52, 0x8E, 0x09, 0x09, 0x0B, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*娶2257*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x00, 0xBA, 0xAA, 0xFE, 0xA9, 0xB9, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x00, 0x0F, 0x02, 0x03, 0x0A, 0x0F,/*龋2258*/},\n        {\n\n                0xA4, 0x24, 0xFF, 0x25, 0xFF, 0x29, 0xFF, 0x81, 0x3A, 0xC2, 0x3E, 0x0F, 0x04, 0x0F, 0x09, 0x09,\n                0x09, 0x0F, 0x0A, 0x09, 0x08, 0x0B,/*趣2259*/},\n        {\n\n                0x40, 0x48, 0x48, 0x48, 0xC8, 0x7F, 0x48, 0x48, 0x48, 0x48, 0x40, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x05, 0x06, 0x0C, 0x00,/*去2260*/},\n        {\n\n                0xFF, 0x91, 0x55, 0xF7, 0x5D, 0x57, 0x55, 0xF7, 0x55, 0x91, 0xFF, 0x0F, 0x08, 0x08, 0x09, 0x0A,\n                0x0B, 0x0B, 0x0A, 0x0B, 0x08, 0x0F,/*圈2261*/},\n        {\n\n                0xBA, 0xEF, 0xBA, 0xC2, 0xBA, 0xAF, 0xBA, 0x00, 0xFD, 0x0B, 0xF9, 0x00, 0x0F, 0x0A, 0x0A, 0x0F,\n                0x0A, 0x0A, 0x00, 0x08, 0x06, 0x08,/*颧2262*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x02, 0x3E, 0xC2, 0x02, 0xC2, 0x3E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*权2263*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0x22, 0x57, 0xCA, 0x57, 0x22, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x08, 0x09, 0x0F, 0x09, 0x08,/*醛2264*/},\n        {\n\n                0x80, 0xBE, 0xAA, 0xAA, 0x2B, 0xEA, 0xAA, 0x2A, 0xAA, 0x7E, 0x00, 0x04, 0x04, 0x02, 0x01, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*泉2265*/},\n        {\n\n                0x10, 0x10, 0x28, 0x24, 0x22, 0xE1, 0x22, 0x24, 0x28, 0x10, 0x10, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*全2266*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0x22, 0x52, 0x4B, 0xC6, 0x4A, 0x52, 0x22, 0x09, 0x04, 0x03, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*痊2267*/},\n        {\n\n                0x48, 0x2A, 0x9B, 0xAA, 0xAE, 0xEB, 0xAA, 0x9A, 0x9B, 0x2A, 0x48, 0x00, 0x02, 0x02, 0x02, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x00,/*拳2268*/},\n        {\n\n                0x10, 0x10, 0x10, 0x10, 0xD0, 0x3F, 0xD0, 0x10, 0x12, 0x14, 0x10, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x03, 0x04, 0x08, 0x08,/*犬2269*/},\n        {\n\n                0x90, 0x54, 0xB5, 0x96, 0x9C, 0x97, 0x94, 0x96, 0xB5, 0x54, 0x90, 0x00, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x08, 0x08, 0x07, 0x00, 0x00,/*券2270*/},\n        {\n\n                0x14, 0x64, 0x84, 0x64, 0x1C, 0x00, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*劝2271*/},\n        {\n\n                0xA4, 0x23, 0xFE, 0x22, 0xA2, 0x44, 0x44, 0xFF, 0x44, 0x7C, 0x40, 0x07, 0x04, 0x03, 0x02, 0x0F,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*缺2272*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x44, 0x44, 0x44, 0xFF, 0x44, 0x7C, 0x40, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*炔2273*/},\n        {\n\n                0x88, 0xFE, 0x02, 0xAA, 0x9E, 0xAA, 0xFB, 0x82, 0xBA, 0xAA, 0xBA, 0x08, 0x07, 0x00, 0x0F, 0x00,\n                0x0A, 0x05, 0x0A, 0x00, 0x08, 0x0F,/*瘸2274*/},\n        {\n\n                0x20, 0x24, 0xA4, 0x7F, 0x24, 0x24, 0x20, 0xFE, 0x02, 0x02, 0xFE, 0x02, 0x03, 0x02, 0x02, 0x03,\n                0x06, 0x00, 0x0F, 0x00, 0x02, 0x03,/*却2275*/},\n        {\n\n                0x10, 0xD4, 0x5F, 0x54, 0x5F, 0xD4, 0x10, 0xFE, 0x8B, 0xA2, 0xBE, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x0F, 0x00, 0x02, 0x0A, 0x0A, 0x07,/*鹊2276*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x26, 0xF2, 0xAA, 0xA7, 0xEA, 0xB2, 0xA6, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*榷2277*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xF4, 0x53, 0xF2, 0x5A, 0x56, 0xF0, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x07, 0x01, 0x07, 0x01, 0x09, 0x0F,/*确2278*/},\n        {\n\n                0x28, 0x24, 0xE2, 0xB0, 0xB0, 0xAF, 0xE8, 0xB4, 0xA2, 0xA4, 0x28, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*雀2279*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xAA, 0xEA, 0xBE, 0xAA, 0xAA, 0xBE, 0x08, 0x00, 0x0F, 0x00, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*裙2280*/},\n        {\n\n                0x08, 0xAA, 0xFE, 0xAA, 0xBE, 0x08, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x02, 0x01, 0x0F, 0x04, 0x0F,\n                0x00, 0x01, 0x01, 0x0F, 0x01, 0x01,/*群2281*/},\n        {\n\n                0x10, 0xAC, 0x4B, 0x32, 0x0E, 0x88, 0x68, 0x1F, 0x68, 0x89, 0x0A, 0x09, 0x04, 0x00, 0x04, 0x09,\n                0x00, 0x04, 0x08, 0x00, 0x04, 0x09,/*然2282*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x24, 0x58, 0xD7, 0x3C, 0xC8, 0x3F, 0xC8, 0x0A, 0x08, 0x06, 0x01, 0x06, 0x0D,\n                0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0D,/*燃2283*/},\n        {\n\n                0x00, 0xFC, 0x24, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x24, 0xFC, 0x00, 0x01, 0x0F, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x0F, 0x01,/*冉2284*/},\n        {\n\n                0xA4, 0x91, 0x82, 0xA0, 0x92, 0xCF, 0x82, 0x82, 0x9E, 0xA0, 0xB0, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*染2285*/},\n        {\n\n                0xBA, 0xAA, 0xFA, 0x83, 0xFA, 0xAA, 0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x0A, 0x06, 0x0F, 0x0A, 0x07,\n                0x0A, 0x07, 0x00, 0x0F, 0x0A, 0x0C,/*瓤2286*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xBA, 0xAA, 0xFA, 0x83, 0xFA, 0xAA, 0xBA, 0x04, 0x07, 0x02, 0x00, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*壤2287*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xBA, 0xAA, 0xFA, 0x83, 0xFA, 0xAA, 0xBA, 0x08, 0x0F, 0x00, 0x00, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*攘2288*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xBA, 0xAA, 0xFA, 0x83, 0xFA, 0xAA, 0xBA, 0x03, 0x01, 0x03, 0x00, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*嚷2289*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x10, 0x10, 0x00, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*让2290*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x80, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*饶2291*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x08, 0xFF, 0x08, 0xF8, 0x09, 0x0A, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*扰2292*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x04, 0x04, 0x02, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*绕2293*/},\n        {\n\n                0x4A, 0x4A, 0x2A, 0xEF, 0xBA, 0xAE, 0xAA, 0xAF, 0xAA, 0xEA, 0x0A, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*惹2294*/},\n        {\n\n                0x24, 0x24, 0xFF, 0x14, 0x00, 0xD4, 0x3F, 0x44, 0x7C, 0x80, 0xE0, 0x08, 0x05, 0x01, 0x04, 0x09,\n                0x00, 0x04, 0x08, 0x00, 0x04, 0x09,/*热2295*/},\n        {\n\n                0x40, 0x44, 0x44, 0x44, 0x44, 0xFC, 0x42, 0x42, 0x42, 0x42, 0x40, 0x00, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x00,/*壬2296*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x04,/*仁2297*/},\n        {\n\n                0x00, 0x00, 0x00, 0x80, 0x60, 0x1F, 0x60, 0x80, 0x00, 0x00, 0x00, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x01, 0x02, 0x04, 0x08,/*人2298*/},\n        {\n\n                0x00, 0x51, 0x4D, 0x21, 0x11, 0x8F, 0x21, 0x21, 0x21, 0x1F, 0x00, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*忍2299*/},\n        {\n\n                0x54, 0x54, 0xFF, 0x54, 0xD4, 0x80, 0x72, 0x02, 0xFE, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x02, 0x03,\n                0x00, 0x08, 0x04, 0x03, 0x08, 0x0F,/*韧2300*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x40, 0x44, 0x44, 0xFC, 0x42, 0x42, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x00,/*任2301*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*认2302*/},\n        {\n\n                0x00, 0x82, 0x72, 0x02, 0x82, 0x7E, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x00, 0x08, 0x08, 0x08, 0x07,/*刃2303*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x40, 0x44, 0x44, 0xFC, 0x42, 0x42, 0x40, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x00,/*妊2304*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x80, 0x72, 0x02, 0xFE, 0x02, 0x02, 0xFE, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*纫2305*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x02, 0xFE, 0x02, 0x02, 0x72, 0x4E, 0xC0, 0x00, 0x08, 0x0F, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x08, 0x08, 0x07,/*扔2306*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0x02, 0xFE, 0x02, 0x02, 0x72, 0x4E, 0xC0, 0x00, 0x0F, 0x00, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x08, 0x08, 0x07,/*仍2307*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0xFE, 0x00, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*日2308*/},\n        {\n\n                0x44, 0x44, 0xF4, 0x44, 0x44, 0x04, 0xFF, 0x04, 0xC5, 0x36, 0x04, 0x08, 0x06, 0x01, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x0F,/*戎2309*/},\n        {\n\n                0x02, 0x12, 0xF2, 0x57, 0x52, 0x52, 0x52, 0x57, 0xF2, 0x12, 0x02, 0x04, 0x04, 0x07, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0F, 0x02, 0x02,/*茸2310*/},\n        {\n\n                0x1A, 0x0A, 0xAA, 0x9F, 0x4A, 0x2E, 0x4A, 0x9F, 0xAA, 0x0A, 0x1A, 0x01, 0x01, 0x0E, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0E, 0x01, 0x01,/*蓉2311*/},\n        {\n\n                0xB2, 0x92, 0x92, 0x97, 0x92, 0xF2, 0x92, 0x97, 0x92, 0x92, 0xB2, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*荣2312*/},\n        {\n\n                0xC1, 0xDD, 0x55, 0xDD, 0xC1, 0x00, 0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x0F, 0x02, 0x07, 0x0A, 0x0F,\n                0x00, 0x08, 0x08, 0x0F, 0x04, 0x0E,/*融2313*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x96, 0x4A, 0x22, 0x13, 0x22, 0x4A, 0x96, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*熔2314*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x96, 0x4A, 0x22, 0x13, 0x22, 0x4A, 0x96, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*溶2315*/},\n        {\n\n                0x46, 0x42, 0xAA, 0xA6, 0x92, 0x8B, 0x92, 0xA6, 0xAA, 0x42, 0x46, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x0F, 0x00, 0x00,/*容2316*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x88, 0xE8, 0x88, 0xFF, 0x08, 0xE9, 0x0A, 0x04, 0x04, 0x02, 0x08, 0x04,\n                0x03, 0x08, 0x04, 0x03, 0x04, 0x0E,/*绒2317*/},\n        {\n\n                0x0E, 0x02, 0x02, 0xF2, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x02, 0x0E, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*冗2318*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x48, 0x29, 0x1B, 0xCD, 0x7D, 0x0B, 0x18, 0x08, 0x0F, 0x00, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*揉2319*/},\n        {\n\n                0x28, 0x28, 0x29, 0x19, 0x0B, 0xAD, 0x3D, 0x0B, 0x09, 0x08, 0x18, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*柔2320*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x24, 0x14, 0xCF, 0x14, 0x24, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x02, 0x01,\n                0x00, 0x01, 0x0A, 0x08, 0x0F, 0x00,/*肉2321*/},\n        {\n\n                0x22, 0x22, 0xE2, 0x37, 0x22, 0xE2, 0x02, 0xE7, 0x22, 0x22, 0xE2, 0x08, 0x09, 0x05, 0x02, 0x05,\n                0x08, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*茹2322*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x4C, 0x55, 0x45, 0xDF, 0x45, 0x55, 0x4C, 0x04, 0x04, 0x03, 0x02, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*蠕2323*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x4C, 0x55, 0x45, 0xDF, 0x45, 0x55, 0x4C, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*儒2324*/},\n        {\n\n                0x41, 0xF9, 0x27, 0x00, 0x4C, 0x55, 0x45, 0xDF, 0x45, 0x55, 0x4C, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*孺2325*/},\n        {\n\n                0x88, 0x78, 0x0F, 0x88, 0x78, 0x00, 0xFC, 0x04, 0x04, 0x04, 0xFC, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*如2326*/},\n        {\n\n                0x80, 0x7F, 0x11, 0xF5, 0x95, 0x15, 0x35, 0x55, 0x55, 0xB5, 0x91, 0x02, 0x02, 0x06, 0x0A, 0x02,\n                0x02, 0x02, 0x0A, 0x0F, 0x02, 0x02,/*辱2327*/},\n        {\n\n                0x2A, 0x32, 0x26, 0xAA, 0x61, 0x29, 0x05, 0x00, 0xFF, 0x00, 0x00, 0x02, 0x02, 0x0A, 0x0F, 0x01,\n                0x01, 0x01, 0x00, 0x07, 0x08, 0x0E,/*乳2328*/},\n        {\n\n                0x11, 0x22, 0x08, 0x48, 0x78, 0x8F, 0x08, 0x88, 0x78, 0x08, 0x08, 0x04, 0x02, 0x08, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x00,/*汝2329*/},\n        {\n\n                0x00, 0x00, 0x01, 0x81, 0x72, 0x0C, 0x70, 0x80, 0x00, 0x00, 0x00, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x01, 0x02, 0x04, 0x08,/*入2330*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xFF, 0x11, 0xF5, 0x95, 0x35, 0x55, 0xB5, 0x00, 0x0F, 0x00, 0x08, 0x07,\n                0x02, 0x06, 0x02, 0x0A, 0x0F, 0x02,/*褥2331*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x20, 0x18, 0x07, 0xE4, 0x04, 0x14, 0x0C, 0x02, 0x02, 0x0F, 0x01, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*软2332*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x10, 0x12, 0xF2, 0x12, 0xF2, 0x12, 0x10, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*阮2333*/},\n        {\n\n                0x42, 0x22, 0x87, 0x22, 0x4A, 0x52, 0xC2, 0x62, 0x07, 0x22, 0x42, 0x06, 0x00, 0x06, 0x09, 0x0C,\n                0x02, 0x06, 0x09, 0x0C, 0x01, 0x02,/*蕊2334*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xAE, 0xA8, 0xA8, 0xEF, 0xA8, 0xA8, 0xAE, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0F,/*瑞2335*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x79, 0xCA, 0x48, 0xCA, 0x79, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*锐2336*/},\n        {\n\n                0xF9, 0x02, 0x00, 0x49, 0x49, 0xF9, 0x49, 0x49, 0x01, 0x01, 0xFF, 0x0F, 0x00, 0x02, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x02, 0x08, 0x0F,/*闰2337*/},\n        {\n\n                0x22, 0x44, 0xF9, 0x02, 0x48, 0x49, 0xF9, 0x49, 0x49, 0x01, 0xFF, 0x04, 0x02, 0x0F, 0x00, 0x02,\n                0x02, 0x03, 0x02, 0x0A, 0x08, 0x0F,/*润2338*/},\n        {\n\n                0x12, 0x12, 0x92, 0xD7, 0xB2, 0x9E, 0x92, 0x97, 0x92, 0x92, 0x12, 0x02, 0x01, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*若2339*/},\n        {\n\n                0x40, 0xB9, 0x29, 0x29, 0xEF, 0x00, 0x40, 0xB9, 0x29, 0x29, 0xEF, 0x04, 0x02, 0x09, 0x08, 0x07,\n                0x00, 0x04, 0x02, 0x09, 0x08, 0x07,/*弱2340*/},\n        {\n\n                0x88, 0xFF, 0x4A, 0xEF, 0xAA, 0xEF, 0x1A, 0xEC, 0x0B, 0xF8, 0x08, 0x08, 0x0F, 0x00, 0x0F, 0x02,\n                0x0F, 0x08, 0x04, 0x03, 0x04, 0x08,/*撒2341*/},\n        {\n\n                0x22, 0x44, 0x00, 0xF2, 0x12, 0xFE, 0x12, 0x12, 0xFE, 0x92, 0xF2, 0x04, 0x02, 0x00, 0x0F, 0x05,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*洒2342*/},\n        {\n\n                0xFA, 0x0A, 0x4A, 0xBF, 0x02, 0x92, 0xB2, 0xD7, 0xDA, 0xB2, 0x92, 0x0F, 0x01, 0x02, 0x09, 0x04,\n                0x03, 0x00, 0x00, 0x00, 0x00, 0x00,/*萨2343*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x00, 0x7F, 0x49, 0xFF, 0x49, 0x7F, 0x00, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x01, 0x06, 0x08, 0x09, 0x0C, 0x03,/*腮2344*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0x7F, 0x49, 0x7F, 0x49, 0x7F, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x02, 0x01, 0x06, 0x09, 0x0C, 0x03,/*鳃2345*/},\n        {\n\n                0x86, 0xAA, 0xAA, 0xFE, 0xAA, 0xAB, 0xAA, 0xFE, 0xAA, 0xAA, 0x86, 0x04, 0x0A, 0x09, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x09, 0x0A, 0x04,/*塞2346*/},\n        {\n\n                0x26, 0xAA, 0xEA, 0xBE, 0xAA, 0xAB, 0xAA, 0xBE, 0xEA, 0xAA, 0x26, 0x01, 0x00, 0x0B, 0x08, 0x04,\n                0x03, 0x04, 0x04, 0x0B, 0x00, 0x01,/*赛2347*/},\n        {\n\n                0x00, 0x02, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x02, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*三2348*/},\n        {\n\n                0x10, 0x94, 0x56, 0xB5, 0x9C, 0x94, 0x94, 0xB4, 0x56, 0x9C, 0x10, 0x01, 0x08, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x08, 0x01,/*叁2349*/},\n        {\n\n                0x10, 0x10, 0x48, 0x84, 0x02, 0xF1, 0x02, 0x84, 0x48, 0x10, 0x10, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*伞2350*/},\n        {\n\n                0x0A, 0xEF, 0xAA, 0xAA, 0xEF, 0x0A, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x00, 0x08, 0x05, 0x02, 0x05, 0x08,/*散2351*/},\n        {\n\n                0x00, 0xB1, 0x5B, 0x55, 0xB5, 0x05, 0xB5, 0x5B, 0x51, 0xB0, 0x00, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*桑2352*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xB0, 0x5B, 0xB5, 0x05, 0xB5, 0x5B, 0xB0, 0x03, 0x01, 0x03, 0x00, 0x0A,\n                0x06, 0x02, 0x0F, 0x02, 0x06, 0x0A,/*嗓2353*/},\n        {\n\n                0x40, 0x44, 0xD4, 0x64, 0x44, 0xFF, 0x44, 0x64, 0x54, 0xC4, 0x40, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x00, 0x01, 0x02, 0x05, 0x08, 0x08,/*丧2354*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x22, 0xAE, 0x92, 0xD6, 0x92, 0xAA, 0x26, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x0C,/*搔2355*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x22, 0xAE, 0x92, 0xD6, 0x92, 0xAA, 0x26, 0x02, 0x0A, 0x09, 0x07, 0x08,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x0C,/*骚2356*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x48, 0x02, 0x22, 0x22, 0x22, 0x22, 0xFE, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*扫2357*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xBC, 0xAA, 0xA0, 0xFF, 0xA0, 0xAA, 0xBE, 0x0D, 0x02, 0x05, 0x00, 0x08,\n                0x09, 0x0A, 0x04, 0x04, 0x0A, 0x09,/*嫂2358*/},\n        {\n\n                0x11, 0x95, 0x1F, 0x15, 0x51, 0x80, 0x11, 0x95, 0x1F, 0x95, 0x11, 0x02, 0x09, 0x08, 0x07, 0x0C,\n                0x0A, 0x09, 0x08, 0x0E, 0x00, 0x03,/*瑟2359*/},\n        {\n\n                0x08, 0xF4, 0x92, 0x93, 0x92, 0xF2, 0x92, 0x9A, 0x96, 0xF0, 0x00, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*色2360*/},\n        {\n\n                0x22, 0x44, 0x10, 0x4A, 0x22, 0x1E, 0xC2, 0x22, 0x22, 0x1E, 0x00, 0x04, 0x02, 0x08, 0x0F, 0x08,\n                0x08, 0x0F, 0x09, 0x09, 0x09, 0x08,/*涩2361*/},\n        {\n\n                0x92, 0x92, 0x8A, 0xE6, 0x82, 0x1F, 0x82, 0xE6, 0x8A, 0x92, 0x92, 0x04, 0x02, 0x01, 0x0F, 0x02,\n                0x04, 0x02, 0x0F, 0x01, 0x02, 0x04,/*森2362*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x3E, 0xAB, 0xA2, 0xBE, 0xA2, 0xAB, 0x3E, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*僧2363*/},\n        {\n\n                0x42, 0x92, 0x22, 0x87, 0x62, 0x02, 0xF2, 0x07, 0x22, 0x42, 0x82, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x01, 0x00, 0x01,/*莎2364*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x40, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x00, 0x07, 0x02, 0x03, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*砂2365*/},\n        {\n\n                0x40, 0x50, 0x51, 0x4A, 0x44, 0xF4, 0x44, 0x4A, 0x49, 0x50, 0x40, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x04,/*杀2366*/},\n        {\n\n                0x40, 0x51, 0x4A, 0xE4, 0x4A, 0x51, 0x40, 0x00, 0xFC, 0x00, 0xFF, 0x02, 0x01, 0x08, 0x0F, 0x00,\n                0x01, 0x02, 0x00, 0x01, 0x08, 0x0F,/*刹2367*/},\n        {\n\n                0x10, 0x21, 0x02, 0x40, 0x30, 0x0C, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x04, 0x02, 0x09, 0x08, 0x08,\n                0x04, 0x04, 0x02, 0x02, 0x01, 0x00,/*沙2368*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x40, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*纱2369*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xBE, 0x62, 0xB6, 0x2B, 0x36, 0x62, 0xBE, 0x00, 0x00, 0x0F, 0x00, 0x0A, 0x09,\n                0x0B, 0x05, 0x05, 0x0B, 0x08, 0x08,/*傻2370*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x28, 0xA4, 0xAA, 0xF9, 0xAA, 0xA4, 0x28, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*啥2371*/},\n        {\n\n                0x08, 0x54, 0x53, 0x5A, 0xF6, 0x10, 0x08, 0xB7, 0x44, 0xBC, 0x04, 0x08, 0x05, 0x01, 0x05, 0x09,\n                0x00, 0x05, 0x08, 0x00, 0x04, 0x09,/*煞2372*/},\n        {\n\n                0xE4, 0x03, 0xF2, 0x06, 0xD2, 0x50, 0x54, 0xF3, 0x52, 0x56, 0xD2, 0x01, 0x08, 0x07, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*筛2373*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0xF2, 0x12, 0xFE, 0x12, 0xFE, 0x92, 0xF2, 0x07, 0x02, 0x07, 0x00, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x04, 0x0F,/*晒2374*/},\n        {\n\n                0x22, 0xFE, 0x22, 0xFF, 0x21, 0xFF, 0x20, 0xFF, 0x21, 0xFF, 0x20, 0x02, 0x0B, 0x05, 0x03, 0x08,\n                0x0F, 0x04, 0x03, 0x08, 0x0F, 0x00,/*珊2375*/},\n        {\n\n                0x02, 0x82, 0x82, 0x87, 0x82, 0xFA, 0x92, 0x97, 0x92, 0x92, 0x12, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*苫2376*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x00, 0x88, 0x44, 0x22, 0x11, 0x88, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x08, 0x08, 0x04, 0x02, 0x01, 0x00,/*杉2377*/},\n        {\n\n                0x00, 0xF8, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x07, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x0F, 0x00,/*山2378*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x20, 0xFE, 0x22, 0xFE, 0x20, 0xFC, 0x00, 0xFF, 0x07, 0x08, 0x0F, 0x00, 0x07,\n                0x08, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*删2379*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0xAA, 0x2A, 0xEB, 0x8A, 0x2A, 0xEE, 0x08, 0x06, 0x01, 0x0A, 0x07,\n                0x02, 0x09, 0x0F, 0x02, 0x09, 0x0F,/*煽2380*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0xA0, 0x00, 0x88, 0x44, 0x22, 0x11, 0x88, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x08, 0x08, 0x04, 0x02, 0x01, 0x00,/*衫2381*/},\n        {\n\n                0x00, 0xF9, 0x02, 0x80, 0x61, 0x1D, 0x21, 0x41, 0x81, 0x01, 0xFF, 0x00, 0x0F, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x09, 0x08, 0x0F,/*闪2382*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x94, 0xA4, 0x84, 0xFF, 0x84, 0xA4, 0x94, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*陕2383*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFA, 0x8A, 0xBA, 0xAB, 0xBA, 0x8A, 0xFA, 0x08, 0x0F, 0x00, 0x00, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x08,/*擅2384*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x15, 0xAD, 0xB5, 0xA7, 0xAC, 0x14, 0x08, 0x06, 0x08, 0x08, 0x07,\n                0x00, 0x0E, 0x0A, 0x0A, 0x0E, 0x00,/*赡2385*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0xA2, 0xEB, 0xAA, 0xFE, 0xAA, 0xEB, 0xA2, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*膳2386*/},\n        {\n\n                0x82, 0xAA, 0xEA, 0xAB, 0xAA, 0xFE, 0xAA, 0xAB, 0xEA, 0xAA, 0x82, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*善2387*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0xF8, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xF8, 0x04, 0x02, 0x01, 0x00, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*汕2388*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xAA, 0x2A, 0xEA, 0x0B, 0x2A, 0xAA, 0x2A, 0xEE, 0x08, 0x07, 0x04, 0x02, 0x09,\n                0x0F, 0x00, 0x04, 0x02, 0x09, 0x0F,/*扇2389*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xA2, 0xEB, 0xAA, 0xFE, 0xAA, 0xEB, 0xA2, 0x04, 0x04, 0x02, 0x00, 0x00,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*缮2390*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xF2, 0x56, 0xBA, 0x93, 0xBA, 0x56, 0xF2, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*墒2391*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x10, 0x48, 0x47, 0xF4, 0x44, 0x44, 0xC4, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*伤2392*/},\n        {\n\n                0x02, 0xF2, 0x96, 0x5A, 0xB2, 0x93, 0xB2, 0x5A, 0x96, 0xF2, 0x02, 0x00, 0x0F, 0x00, 0x00, 0x03,\n                0x02, 0x03, 0x00, 0x08, 0x0F, 0x00,/*商2393*/},\n        {\n\n                0x06, 0x82, 0xBB, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBB, 0x82, 0x06, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*赏2394*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0xFC, 0x04, 0xE6, 0x25, 0xE4, 0x04, 0xFC, 0x07, 0x02, 0x07, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*晌2395*/},\n        {\n\n                0x00, 0x00, 0x00, 0x00, 0xFF, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x08, 0x08, 0x08, 0x08, 0x0F,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*上2396*/},\n        {\n\n                0x00, 0xF2, 0x14, 0xD0, 0x50, 0x5F, 0x50, 0xD0, 0x14, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x03, 0x02,\n                0x02, 0x02, 0x03, 0x08, 0x0F, 0x00,/*尚2397*/},\n        {\n\n                0x0C, 0x04, 0x75, 0x56, 0x54, 0xD7, 0x54, 0x56, 0x75, 0x04, 0x0C, 0x09, 0x09, 0x05, 0x0D, 0x0B,\n                0x01, 0x03, 0x05, 0x05, 0x0B, 0x09,/*裳2398*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x02, 0xF4, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x01, 0x01, 0x01, 0x09, 0x0F,/*梢2399*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xF2, 0x54, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x01, 0x09, 0x0F,/*捎2400*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x02, 0xF4, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x01, 0x01, 0x01, 0x09, 0x0F,/*稍2401*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*烧2402*/},\n        {\n\n                0x42, 0x22, 0x1A, 0x97, 0x12, 0x12, 0x12, 0x17, 0x12, 0xF2, 0x02, 0x00, 0x00, 0x00, 0x00, 0x03,\n                0x00, 0x08, 0x08, 0x08, 0x07, 0x00,/*芍2403*/},\n        {\n\n                0x20, 0x10, 0x0C, 0x07, 0x44, 0x84, 0x04, 0x04, 0x04, 0x04, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x01, 0x00, 0x08, 0x08, 0x08, 0x07,/*勺2404*/},\n        {\n\n                0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x40, 0xA2, 0x9E, 0x82, 0xA2, 0xBE, 0x0F, 0x0A, 0x0A, 0x0A, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*韶2405*/},\n        {\n\n                0x20, 0x10, 0x0C, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x84, 0x08, 0x30, 0x08, 0x08, 0x08, 0x04, 0x04,\n                0x02, 0x02, 0x01, 0x00, 0x00, 0x00,/*少2406*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xF2, 0x54, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x01, 0x09, 0x0F,/*哨2407*/},\n        {\n\n                0x40, 0xA2, 0x9E, 0x82, 0xA2, 0xBE, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x0F, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邵2408*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x20, 0x92, 0x8E, 0x82, 0xA2, 0xA2, 0x9E, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*绍2409*/},\n        {\n\n                0x52, 0x52, 0x4A, 0xDA, 0x56, 0x7B, 0x56, 0x6A, 0xCA, 0x52, 0x52, 0x02, 0x02, 0x01, 0x0F, 0x05,\n                0x05, 0x05, 0x05, 0x0F, 0x00, 0x00,/*奢2410*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x48, 0x54, 0xD3, 0x54, 0x48, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x04, 0x03, 0x08, 0x0F, 0x01, 0x06,/*赊2411*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x2C, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*蛇2412*/},\n        {\n\n                0x10, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x91, 0x91, 0x10, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*舌2413*/},\n        {\n\n                0x48, 0x48, 0x54, 0x54, 0x52, 0xF1, 0x52, 0x54, 0x54, 0x48, 0x48, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*舍2414*/},\n        {\n\n                0x20, 0xA4, 0xE4, 0x3F, 0xE4, 0x20, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x09, 0x04, 0x03, 0x08, 0x0F,\n                0x01, 0x08, 0x04, 0x03, 0x04, 0x08,/*赦2415*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x41, 0x7F, 0x55, 0x55, 0x55, 0xFF, 0x21, 0x00, 0x08, 0x0F, 0x00, 0x0B,\n                0x05, 0x0B, 0x00, 0x0B, 0x05, 0x0B,/*摄2416*/},\n        {\n\n                0x80, 0xFE, 0xAB, 0xAA, 0xFE, 0x00, 0x48, 0x88, 0x08, 0xFF, 0x08, 0x04, 0x02, 0x01, 0x08, 0x0F,\n                0x00, 0x00, 0x09, 0x08, 0x0F, 0x00,/*射2417*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x41, 0x7F, 0x55, 0x55, 0x55, 0xFF, 0x21, 0x00, 0x00, 0x0F, 0x00, 0x0B,\n                0x05, 0x0B, 0x00, 0x0B, 0x05, 0x0B,/*慑2418*/},\n        {\n\n                0x10, 0x22, 0x04, 0x10, 0x9E, 0x10, 0x10, 0xDF, 0x12, 0x12, 0x90, 0x04, 0x02, 0x01, 0x0A, 0x09,\n                0x08, 0x04, 0x05, 0x02, 0x01, 0x00,/*涉2419*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*社2420*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x50, 0xCF, 0x41, 0x41, 0x4F, 0xD0, 0x10, 0x00, 0x00, 0x07, 0x02, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*设2421*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFC, 0x24, 0xFF, 0x24, 0x24, 0xFC, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x03, 0x01, 0x0F, 0x01, 0x01, 0x03,/*砷2422*/},\n        {\n\n                0x00, 0xFC, 0x24, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x24, 0xFC, 0x00, 0x00, 0x03, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x03, 0x00,/*申2423*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFC, 0x24, 0x24, 0xFF, 0x24, 0x24, 0xFC, 0x03, 0x01, 0x03, 0x00, 0x03,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x03,/*呻2424*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xFC, 0x24, 0x24, 0xFF, 0x24, 0x24, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x03,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x03,/*伸2425*/},\n        {\n\n                0x80, 0x80, 0xFE, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xFE, 0x40, 0x20, 0x04, 0x04, 0x04, 0x02, 0x02,\n                0x01, 0x09, 0x08, 0x0F, 0x00, 0x00,/*身2426*/},\n        {\n\n                0x22, 0x44, 0x06, 0x52, 0x4A, 0x46, 0xF2, 0x46, 0x4A, 0x52, 0x46, 0x04, 0x02, 0x04, 0x04, 0x02,\n                0x01, 0x0F, 0x01, 0x02, 0x04, 0x04,/*深2427*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFE, 0xE2, 0x2A, 0xEA, 0x2A, 0xA2, 0x08, 0x05, 0x02, 0x0D, 0x07,\n                0x00, 0x0F, 0x04, 0x03, 0x05, 0x08,/*娠2428*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xFC, 0x24, 0x24, 0xFF, 0x24, 0x24, 0xFC, 0x04, 0x04, 0x02, 0x00, 0x03,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x03,/*绅2429*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xFC, 0x24, 0xFF, 0x24, 0x24, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x03, 0x01, 0x0F, 0x01, 0x01, 0x03,/*神2430*/},\n        {\n\n                0x22, 0x44, 0x00, 0x1C, 0x04, 0xC4, 0x3F, 0xC4, 0x04, 0x04, 0x1C, 0x04, 0x02, 0x08, 0x04, 0x03,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*沈2431*/},\n        {\n\n                0x06, 0xF2, 0x52, 0x52, 0x52, 0xFB, 0x52, 0x52, 0x52, 0xF2, 0x06, 0x00, 0x03, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x03, 0x00,/*审2432*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xF6, 0x52, 0x52, 0xFB, 0x52, 0x52, 0xF6, 0x0D, 0x02, 0x05, 0x00, 0x03,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x03,/*婶2433*/},\n        {\n\n                0x82, 0x82, 0xFF, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xFF, 0x82, 0x82, 0x00, 0x0F, 0x08, 0x0A, 0x09,\n                0x08, 0x08, 0x09, 0x0A, 0x08, 0x00,/*甚2434*/},\n        {\n\n                0x0E, 0xE0, 0xA0, 0xAF, 0xA0, 0xA9, 0xAB, 0xA5, 0xA5, 0xEB, 0x10, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*肾2435*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x0B, 0x06, 0x02, 0x06, 0x0B, 0x02,/*慎2436*/},\n        {\n\n                0x22, 0x44, 0x90, 0x54, 0xB6, 0x9D, 0x54, 0x14, 0xB6, 0x5C, 0x90, 0x04, 0x02, 0x00, 0x08, 0x0A,\n                0x0A, 0x09, 0x05, 0x04, 0x02, 0x00,/*渗2437*/},\n        {\n\n                0x02, 0xEA, 0x2A, 0x2A, 0x2A, 0xEF, 0x2A, 0x2A, 0x2A, 0xEA, 0x02, 0x08, 0x07, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x01, 0x03, 0x00,/*声2438*/},\n        {\n\n                0x20, 0x10, 0x8E, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x88, 0x08, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*生2439*/},\n        {\n\n                0x20, 0x5C, 0x48, 0xFF, 0x48, 0x08, 0xBE, 0xEA, 0xBE, 0xAA, 0xBE, 0x04, 0x04, 0x04, 0x03, 0x02,\n                0x02, 0x08, 0x07, 0x00, 0x08, 0x0F,/*甥2440*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x20, 0x9C, 0x88, 0xFF, 0x88, 0x88, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*牲2441*/},\n        {\n\n                0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x20, 0xFF, 0x20, 0x20, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,/*升2442*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0xF0, 0x57, 0x55, 0xFD, 0x55, 0x57, 0xF0, 0x00, 0x04, 0x04, 0x02, 0x03, 0x01,\n                0x01, 0x07, 0x09, 0x09, 0x09, 0x0C,/*绳2443*/},\n        {\n\n                0x28, 0x24, 0xE2, 0xB0, 0xB0, 0xAF, 0xA8, 0xA4, 0xA2, 0xE4, 0x08, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*省2444*/},\n        {\n\n                0x80, 0x7E, 0x0A, 0x0A, 0x4A, 0x7A, 0x82, 0x5F, 0x22, 0x53, 0xEA, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盛2445*/},\n        {\n\n                0xA8, 0xFA, 0x0A, 0xFE, 0x09, 0xF9, 0xA8, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x01, 0x0F, 0x01,\n                0x02, 0x04, 0x00, 0x01, 0x08, 0x0F,/*剩2446*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x20, 0x9C, 0x88, 0xFF, 0x88, 0x88, 0x00, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*胜2447*/},\n        {\n\n                0x40, 0x42, 0x26, 0x2A, 0x12, 0xD2, 0x12, 0x2A, 0x26, 0x42, 0x40, 0x08, 0x08, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x08, 0x08,/*圣2448*/},\n        {\n\n                0xFC, 0x00, 0xFF, 0x00, 0xF2, 0x12, 0x12, 0xFE, 0x12, 0x12, 0xF2, 0x09, 0x04, 0x03, 0x00, 0x03,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*师2449*/},\n        {\n\n                0xA0, 0x90, 0x8E, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x88, 0x80, 0x80, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*失2450*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xFF, 0x00, 0xF2, 0x12, 0xFE, 0x12, 0xF2, 0x08, 0x08, 0x07, 0x08, 0x07,\n                0x00, 0x03, 0x00, 0x0F, 0x02, 0x03,/*狮2451*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x44, 0xF3, 0x42, 0xFE, 0x22, 0x12, 0xF2, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x07, 0x08, 0x0B, 0x08, 0x09, 0x0D,/*施2452*/},\n        {\n\n                0x11, 0x22, 0x80, 0x3E, 0x2A, 0xEA, 0x2A, 0xEA, 0x2A, 0x3E, 0x80, 0x04, 0x02, 0x08, 0x09, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x09, 0x08,/*湿2453*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x50, 0x54, 0x54, 0x54, 0x5F, 0xF4, 0x54, 0x50, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x02, 0x00, 0x08, 0x0F, 0x00, 0x00,/*诗2454*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x7E, 0x08, 0x06, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*尸2455*/},\n        {\n\n                0xE8, 0xA9, 0xA9, 0xF9, 0xA5, 0xA5, 0xE5, 0x01, 0xFF, 0x00, 0x00, 0x04, 0x04, 0x04, 0x07, 0x04,\n                0x06, 0x0C, 0x00, 0x03, 0x04, 0x0F,/*虱2456*/},\n        {\n\n                0x20, 0x20, 0x20, 0x20, 0x20, 0xFF, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*十2457*/},\n        {\n\n                0x02, 0x82, 0x42, 0xF2, 0x2E, 0x22, 0x22, 0x22, 0x22, 0xE2, 0x02, 0x01, 0x00, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*石2458*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*拾2459*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x00, 0x08, 0x48, 0x88, 0x08, 0xFF, 0x08, 0x07, 0x02, 0x02, 0x07, 0x00,\n                0x00, 0x00, 0x09, 0x08, 0x0F, 0x00,/*时2460*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x20, 0x20, 0x20, 0xFF, 0x20, 0x20, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*什2461*/},\n        {\n\n                0x08, 0x08, 0xF4, 0x54, 0x52, 0x59, 0x52, 0x54, 0xF4, 0x08, 0x08, 0x00, 0x00, 0x0F, 0x09, 0x05,\n                0x01, 0x03, 0x05, 0x05, 0x0A, 0x01,/*食2462*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0xF8, 0x88, 0x88, 0xFF, 0x88, 0x88, 0xF8, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x08, 0x08, 0x0F, 0x04, 0x04, 0x0E,/*蚀2463*/},\n        {\n\n                0x86, 0x82, 0xA2, 0xCA, 0x92, 0x83, 0xFA, 0x82, 0x82, 0x82, 0x86, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x00, 0x02, 0x02, 0x04, 0x08,/*实2464*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0x7E, 0x42, 0x42, 0x42, 0x42, 0x7E, 0x00, 0x00, 0x07, 0x02, 0x08, 0x04,\n                0x02, 0x00, 0x00, 0x02, 0x04, 0x08,/*识2465*/},\n        {\n\n                0x00, 0x7C, 0x44, 0x44, 0x44, 0xFF, 0x44, 0x44, 0x44, 0x7C, 0x00, 0x08, 0x08, 0x05, 0x02, 0x03,\n                0x04, 0x04, 0x08, 0x08, 0x08, 0x08,/*史2466*/},\n        {\n\n                0x50, 0x48, 0x47, 0x44, 0x44, 0xFC, 0x44, 0x44, 0x44, 0x44, 0x40, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*矢2467*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xF4, 0x54, 0x54, 0xFF, 0x54, 0x54, 0x74, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x05, 0x02, 0x05, 0x04, 0x08, 0x08,/*使2468*/},\n        {\n\n                0x00, 0xFF, 0x85, 0x95, 0xA5, 0x85, 0xF5, 0x85, 0xA5, 0x95, 0x87, 0x08, 0x07, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x01, 0x02, 0x04,/*屎2469*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x80, 0x7C, 0x44, 0xFF, 0x44, 0x7C, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*驶2470*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*始2471*/},\n        {\n\n                0x08, 0x48, 0x48, 0xC8, 0x48, 0x48, 0x08, 0xFF, 0x08, 0x09, 0x0A, 0x08, 0x08, 0x08, 0x07, 0x04,\n                0x04, 0x04, 0x00, 0x03, 0x04, 0x0E,/*式2472*/},\n        {\n\n                0x10, 0x10, 0x92, 0x12, 0x12, 0xF2, 0x12, 0x12, 0x92, 0x10, 0x10, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x01, 0x06,/*示2473*/},\n        {\n\n                0x10, 0x10, 0x10, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x00,/*士2474*/},\n        {\n\n                0x10, 0x10, 0xFE, 0x10, 0x10, 0xFF, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x00, 0x00, 0x0F, 0x08, 0x08,\n                0x09, 0x09, 0x09, 0x09, 0x08, 0x08,/*世2475*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xE4, 0x24, 0x25, 0xFE, 0x24, 0x24, 0xE4, 0x00, 0x00, 0x0F, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*柿2476*/},\n        {\n\n                0x82, 0xA2, 0xAE, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAE, 0xE2, 0x82, 0x00, 0x02, 0x02, 0x02, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x03, 0x00,/*事2477*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x24, 0xE4, 0x24, 0x04, 0xFF, 0x04, 0x05, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x07, 0x02, 0x00, 0x03, 0x04, 0x0E,/*拭2478*/},\n        {\n\n                0x8A, 0xAA, 0xBF, 0x8A, 0xE0, 0x9E, 0x8A, 0x8A, 0xB9, 0x89, 0x88, 0x00, 0x02, 0x0E, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0E, 0x02, 0x00,/*誓2479*/},\n        {\n\n                0x11, 0xF2, 0x48, 0x48, 0xFF, 0x28, 0x00, 0xFE, 0x12, 0xF2, 0x11, 0x08, 0x07, 0x08, 0x0A, 0x0B,\n                0x08, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*逝2480*/},\n        {\n\n                0x12, 0x52, 0x7F, 0x0A, 0xC0, 0x2A, 0x1F, 0x22, 0x1E, 0x20, 0x78, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*势2481*/},\n        {\n\n                0x40, 0x40, 0x5F, 0x55, 0x55, 0xD5, 0x55, 0x55, 0x5F, 0x40, 0x40, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*是2482*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x48, 0xAA, 0x9A, 0xBF, 0xCA, 0xEC, 0xDA, 0x68, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*嗜2483*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x04, 0x13, 0xD6, 0x12, 0xF4, 0x13, 0xD6, 0x12, 0x03, 0x01, 0x03, 0x0A, 0x09,\n                0x08, 0x09, 0x0F, 0x09, 0x08, 0x09,/*噬2484*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x10, 0xD2, 0x52, 0x7E, 0x51, 0xD1, 0x10, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*适2485*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x10, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x00,/*仕2486*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x50, 0x54, 0x54, 0x5F, 0xF4, 0x54, 0x50, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x0A, 0x08, 0x0F, 0x00, 0x00,/*侍2487*/},\n        {\n\n                0x4A, 0x52, 0xFE, 0x51, 0x08, 0x21, 0xA3, 0x95, 0xE9, 0x95, 0xA3, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x02, 0x02, 0x02, 0x0F, 0x02, 0x02,/*释2488*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0xE8, 0x24, 0x27, 0xFC, 0x24, 0x24, 0xE4, 0x00, 0x0F, 0x04, 0x00, 0x03,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*饰2489*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x7E, 0xA1, 0x21, 0x21, 0x20, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x00, 0x01, 0x02, 0x04, 0x0F,/*氏2490*/},\n        {\n\n                0x04, 0xE4, 0x24, 0x24, 0x25, 0xFE, 0x24, 0x24, 0x24, 0xE4, 0x04, 0x00, 0x07, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x04, 0x07, 0x00,/*市2491*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x50, 0x54, 0x54, 0x5F, 0xF4, 0x54, 0x50, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x0A, 0x08, 0x0F, 0x00, 0x00,/*恃2492*/},\n        {\n\n                0x1C, 0x04, 0x94, 0xD4, 0xB5, 0x96, 0x94, 0xD4, 0x94, 0x04, 0x1C, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*室2493*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*视2494*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x00, 0x24, 0xE4, 0x24, 0x04, 0xFF, 0x04, 0x05, 0x00, 0x0F, 0x04, 0x00, 0x04,\n                0x07, 0x02, 0x00, 0x03, 0x04, 0x0E,/*试2495*/},\n        {\n\n                0xFE, 0x00, 0x80, 0xFF, 0x20, 0x10, 0xEF, 0x08, 0x88, 0x78, 0x08, 0x03, 0x01, 0x00, 0x0F, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*收2496*/},\n        {\n\n                0x80, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x91, 0x91, 0x80, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*手2497*/},\n        {\n\n                0x04, 0xF4, 0x55, 0x56, 0x54, 0x5C, 0x54, 0x56, 0x55, 0xF4, 0x04, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*首2498*/},\n        {\n\n                0x4C, 0x44, 0x44, 0x44, 0x45, 0x46, 0x44, 0xF4, 0x44, 0x44, 0x4C, 0x00, 0x00, 0x01, 0x02, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*守2499*/},\n        {\n\n                0x20, 0x22, 0xAA, 0xEA, 0xBA, 0xAF, 0xAA, 0xAA, 0xEA, 0xA2, 0xA0, 0x04, 0x02, 0x01, 0x00, 0x01,\n                0x02, 0x08, 0x08, 0x0F, 0x00, 0x00,/*寿2500*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x32, 0xD6, 0x5A, 0x56, 0x5A, 0x52, 0xD9, 0x35, 0x08, 0x0F, 0x00, 0x08, 0x08,\n                0x05, 0x02, 0x02, 0x05, 0x08, 0x08,/*授2501*/},\n        {\n\n                0x08, 0xFC, 0xAB, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAA, 0x82, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*售2502*/},\n        {\n\n                0x72, 0x16, 0xDA, 0x52, 0x56, 0x5A, 0x51, 0x51, 0xD9, 0x15, 0x71, 0x08, 0x08, 0x04, 0x05, 0x02,\n                0x02, 0x02, 0x05, 0x04, 0x08, 0x08,/*受2503*/},\n        {\n\n                0x08, 0xFE, 0x02, 0x7A, 0x56, 0x43, 0xFE, 0x42, 0x56, 0x7E, 0x02, 0x09, 0x07, 0x08, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x05, 0x0B, 0x08,/*瘦2504*/},\n        {\n\n                0x80, 0xBE, 0xAA, 0xAB, 0xAA, 0xBE, 0xAA, 0xAB, 0xAA, 0xBE, 0x80, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*兽2505*/},\n        {\n\n                0x92, 0x12, 0xD2, 0xB7, 0x02, 0x92, 0xD2, 0xB7, 0x9A, 0xD2, 0x92, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x06, 0x00, 0x0E, 0x00, 0x0E, 0x09,/*蔬2506*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0x02, 0x0A, 0x32, 0xC2, 0x3A, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x08, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*枢2507*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xA4, 0x34, 0xAD, 0x26, 0xA4, 0x34, 0x64, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0C,/*梳2508*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x28, 0x26, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*殊2509*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x20, 0x22, 0x2A, 0xF2, 0x2A, 0x26, 0x60, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*抒2510*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0xE8, 0xA4, 0xEA, 0x09, 0xCA, 0x04, 0xE8, 0x01, 0x01, 0x0F, 0x00, 0x0F,\n                0x02, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*输2511*/},\n        {\n\n                0x10, 0x90, 0x10, 0xDF, 0x92, 0x12, 0x00, 0x7E, 0x82, 0x62, 0x1E, 0x02, 0x01, 0x08, 0x0F, 0x00,\n                0x09, 0x04, 0x02, 0x01, 0x06, 0x08,/*叔2512*/},\n        {\n\n                0xA4, 0xAA, 0xF9, 0xAA, 0xA4, 0x00, 0x22, 0x2A, 0xF2, 0x2A, 0x66, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*舒2513*/},\n        {\n\n                0x22, 0x44, 0x10, 0x10, 0xDF, 0x14, 0x12, 0xFE, 0x02, 0xFE, 0x00, 0x04, 0x02, 0x02, 0x09, 0x0F,\n                0x01, 0x0A, 0x04, 0x03, 0x04, 0x08,/*淑2514*/},\n        {\n\n                0xE2, 0x02, 0xFA, 0x46, 0x00, 0xA4, 0x34, 0xAD, 0x26, 0xB4, 0x64, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x07, 0x00, 0x07, 0x00, 0x0F, 0x08,/*疏2515*/},\n        {\n\n                0x40, 0x44, 0x44, 0x44, 0xFF, 0x44, 0x44, 0x44, 0x7D, 0x42, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x04, 0x04, 0x03,/*书2516*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x4A, 0xAA, 0x4F, 0xEA, 0x1A, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x09, 0x05, 0x03, 0x05, 0x09,/*赎2517*/},\n        {\n\n                0x02, 0xBA, 0xAA, 0xAB, 0xBA, 0x02, 0x24, 0xFF, 0x44, 0xFC, 0x00, 0x02, 0x02, 0x0A, 0x0E, 0x03,\n                0x0A, 0x04, 0x03, 0x00, 0x07, 0x0C,/*孰2518*/},\n        {\n\n                0x82, 0xAE, 0xAB, 0xAA, 0xEE, 0x82, 0x24, 0xFF, 0x44, 0xFC, 0x00, 0x08, 0x04, 0x02, 0x07, 0x08,\n                0x02, 0x05, 0x08, 0x00, 0x05, 0x0B,/*熟2519*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xAF, 0xFA, 0xAA, 0xBA, 0xAF, 0xAA, 0xBA, 0x82, 0x04, 0x02, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*薯2520*/},\n        {\n\n                0x80, 0x8F, 0xA9, 0xA9, 0xF9, 0xAB, 0xCD, 0xA9, 0x99, 0x8F, 0x80, 0x04, 0x04, 0x02, 0x0F, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*暑2521*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x40, 0x47, 0xD5, 0x7F, 0x55, 0x67, 0xD5, 0x47, 0x07, 0x02, 0x07, 0x02, 0x01,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*曙2522*/},\n        {\n\n                0x40, 0x47, 0x55, 0xD5, 0x57, 0x7D, 0x57, 0x65, 0xDD, 0x47, 0x40, 0x02, 0x02, 0x01, 0x0F, 0x05,\n                0x05, 0x05, 0x05, 0x0F, 0x00, 0x00,/*署2523*/},\n        {\n\n                0x40, 0xE7, 0x5D, 0x55, 0xF7, 0x55, 0x57, 0xD5, 0x15, 0x17, 0xF0, 0x04, 0x05, 0x05, 0x05, 0x07,\n                0x05, 0x05, 0x05, 0x0E, 0x08, 0x07,/*蜀2524*/},\n        {\n\n                0x88, 0xA8, 0x5A, 0x4A, 0x2A, 0x9E, 0x29, 0x49, 0x59, 0xA8, 0x88, 0x00, 0x08, 0x05, 0x02, 0x08,\n                0x0F, 0x00, 0x02, 0x05, 0x08, 0x00,/*黍2525*/},\n        {\n\n                0x00, 0xFE, 0xAA, 0x2A, 0x29, 0xE0, 0xAA, 0x2A, 0xEA, 0x3E, 0x00, 0x00, 0x0F, 0x0A, 0x00, 0x00,\n                0x0F, 0x0A, 0x00, 0x03, 0x04, 0x0E,/*鼠2526*/},\n        {\n\n                0x00, 0xFF, 0x05, 0x75, 0x55, 0x55, 0xFD, 0x55, 0x55, 0x75, 0x07, 0x08, 0x07, 0x0F, 0x01, 0x05,\n                0x05, 0x07, 0x05, 0x07, 0x09, 0x0F,/*属2527*/},\n        {\n\n                0x08, 0x08, 0x88, 0x68, 0x18, 0xFF, 0x18, 0x68, 0x89, 0x0A, 0x08, 0x02, 0x01, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x01, 0x02,/*术2528*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x88, 0x48, 0x28, 0xFF, 0x28, 0x49, 0x8A, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x08, 0x08, 0x0B, 0x08, 0x08, 0x08,/*述2529*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x34, 0xC4, 0x3C, 0x48, 0x88, 0xFF, 0x08, 0x00, 0x00, 0x0F, 0x02, 0x01,\n                0x00, 0x03, 0x00, 0x08, 0x0F, 0x00,/*树2530*/},\n        {\n\n                0x02, 0x7A, 0x4A, 0x4A, 0xCA, 0xFF, 0xCA, 0x4A, 0x4A, 0x7A, 0x02, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*束2531*/},\n        {\n\n                0x00, 0xF8, 0x48, 0x88, 0x08, 0x08, 0xFF, 0x08, 0x89, 0x6A, 0x08, 0x08, 0x07, 0x00, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x0F,/*戍2532*/},\n        {\n\n                0x1E, 0x80, 0x80, 0xBF, 0x80, 0xE1, 0x95, 0x89, 0x95, 0xA3, 0x00, 0x08, 0x08, 0x0A, 0x0C, 0x08,\n                0x08, 0x08, 0x0C, 0x0A, 0x08, 0x08,/*竖2533*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x00, 0x11, 0x95, 0xF9, 0x17, 0x30, 0x09, 0x09, 0x09, 0x0B, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x08, 0x08,/*墅2534*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x22, 0xFA, 0x22, 0x23, 0x22, 0xFA, 0x22, 0x22, 0x08, 0x07, 0x08, 0x04, 0x01,\n                0x05, 0x09, 0x05, 0x09, 0x04, 0x08,/*庶2535*/},\n        {\n\n                0x48, 0x2A, 0x98, 0x7F, 0x28, 0x4A, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x09, 0x0B, 0x05, 0x05, 0x0B,\n                0x00, 0x08, 0x05, 0x02, 0x05, 0x08,/*数2536*/},\n        {\n\n                0x22, 0x44, 0x74, 0x54, 0xFF, 0x54, 0x74, 0x08, 0xE7, 0x04, 0x1C, 0x04, 0x02, 0x04, 0x02, 0x0F,\n                0x01, 0x0A, 0x06, 0x01, 0x06, 0x08,/*漱2537*/},\n        {\n\n                0x84, 0x5C, 0x27, 0x24, 0x5C, 0x00, 0x7E, 0x42, 0x42, 0x7E, 0x00, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*恕2538*/},\n        {\n\n                0x00, 0xFF, 0xC9, 0x49, 0xF9, 0x49, 0xCF, 0x00, 0xFC, 0x00, 0xFF, 0x01, 0x00, 0x07, 0x00, 0x0F,\n                0x04, 0x07, 0x00, 0x01, 0x08, 0x0F,/*刷2539*/},\n        {\n\n                0x02, 0x7A, 0x0A, 0x0A, 0xBA, 0x0E, 0x3A, 0x0A, 0x4A, 0x7A, 0x02, 0x09, 0x09, 0x0B, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*耍2540*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x52, 0x22, 0xDA, 0xB7, 0xDA, 0x22, 0x52, 0x00, 0x08, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*摔2541*/},\n        {\n\n                0x22, 0x22, 0xFA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xFA, 0x22, 0x22, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*衰2542*/},\n        {\n\n                0x00, 0xFF, 0x49, 0x49, 0x49, 0xFF, 0x49, 0x49, 0x49, 0xFF, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00,\n                0x07, 0x08, 0x0A, 0x0A, 0x0B, 0x0C,/*甩2543*/},\n        {\n\n                0xFC, 0x00, 0xFF, 0x00, 0xFC, 0x04, 0x04, 0xFF, 0x04, 0x04, 0xFC, 0x09, 0x04, 0x03, 0x00, 0x03,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*帅2544*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0x28, 0x24, 0xE3, 0x24, 0x28, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*栓2545*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0x28, 0x24, 0xE3, 0x24, 0x28, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*拴2546*/},\n        {\n\n                0x4C, 0x45, 0xF5, 0x4D, 0x45, 0xEF, 0xA5, 0xAD, 0xA5, 0xA5, 0xEC, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x0F,/*霜2547*/},\n        {\n\n                0x12, 0x62, 0x82, 0x62, 0x1E, 0x00, 0x1E, 0x62, 0x82, 0x62, 0x1E, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x08, 0x04, 0x02, 0x01, 0x06, 0x08,/*双2548*/},\n        {\n\n                0x02, 0x56, 0x8A, 0x56, 0x02, 0xFF, 0x02, 0x56, 0x8A, 0x56, 0x02, 0x08, 0x09, 0x04, 0x05, 0x02,\n                0x01, 0x02, 0x05, 0x04, 0x09, 0x08,/*爽2549*/},\n        {\n\n                0x10, 0xF1, 0x22, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x04, 0x00, 0x07, 0x02, 0x00, 0x0F,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*谁2550*/},\n        {\n\n                0x00, 0x08, 0x88, 0x78, 0x00, 0xFF, 0x18, 0x60, 0x90, 0x08, 0x04, 0x04, 0x02, 0x01, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x04,/*水2551*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x40, 0x48, 0xFA, 0x4A, 0xFE, 0x49, 0xF9, 0x48, 0x0F, 0x04, 0x0F, 0x00, 0x02,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x02,/*睡2552*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x00, 0x79, 0xCA, 0x48, 0xCA, 0x79, 0x00, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*税2553*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x10, 0x18, 0xF4, 0x13, 0xF0, 0x14, 0x38, 0x00, 0x03, 0x01, 0x03, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x08, 0x08, 0x0E,/*吮2554*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x36, 0xDA, 0x96, 0x1A, 0x91, 0xD9, 0xB5, 0x0F, 0x04, 0x0F, 0x00, 0x09,\n                0x06, 0x01, 0x03, 0x02, 0x0F, 0x02,/*瞬2555*/},\n        {\n\n                0xFE, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x07, 0x00, 0x03, 0x00, 0x0F,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*顺2556*/},\n        {\n\n                0x32, 0x96, 0x7A, 0x52, 0xD6, 0x1A, 0x51, 0x51, 0xF9, 0x55, 0x31, 0x01, 0x08, 0x05, 0x02, 0x01,\n                0x00, 0x03, 0x02, 0x0F, 0x02, 0x02,/*舜2557*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xF9, 0x8A, 0x88, 0x88, 0x8A, 0xF9, 0x00, 0x00, 0x07, 0x02, 0x09, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0C,/*说2558*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x02, 0x00, 0x07, 0x02, 0x03, 0x08,\n                0x05, 0x02, 0x01, 0x02, 0x05, 0x08,/*硕2559*/},\n        {\n\n                0x08, 0xE9, 0x8A, 0xF8, 0x8A, 0xE9, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x01, 0x08, 0x07, 0x00, 0x08, 0x0F,/*朔2560*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xBE, 0x22, 0xFA, 0x21, 0xA1, 0x20, 0x08, 0x06, 0x01, 0x02, 0x06,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*烁2561*/},\n        {\n\n                0x04, 0xFF, 0x54, 0x54, 0xFF, 0x04, 0xFE, 0x12, 0x12, 0xF1, 0x10, 0x09, 0x05, 0x01, 0x01, 0x05,\n                0x09, 0x07, 0x00, 0x00, 0x0F, 0x00,/*斯2562*/},\n        {\n\n                0x84, 0xFF, 0x44, 0xFF, 0x54, 0xFF, 0x04, 0xFE, 0x12, 0xF2, 0x11, 0x08, 0x0F, 0x09, 0x05, 0x01,\n                0x05, 0x09, 0x07, 0x00, 0x0F, 0x00,/*撕2563*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x04, 0xFF, 0x54, 0xFF, 0x04, 0xFE, 0x12, 0xF1, 0x03, 0x01, 0x03, 0x09, 0x05,\n                0x01, 0x05, 0x09, 0x07, 0x00, 0x0F,/*嘶2564*/},\n        {\n\n                0x00, 0x7F, 0x49, 0x49, 0x49, 0xFF, 0x49, 0x49, 0x49, 0x7F, 0x00, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*思2565*/},\n        {\n\n                0x10, 0x92, 0x52, 0xFE, 0x51, 0x90, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0F, 0x00,\n                0x04, 0x06, 0x05, 0x04, 0x05, 0x0E,/*私2566*/},\n        {\n\n                0x08, 0xEA, 0x2A, 0x2A, 0x2A, 0x2A, 0xEA, 0x0A, 0x02, 0xFE, 0x00, 0x00, 0x07, 0x02, 0x02, 0x02,\n                0x02, 0x0B, 0x08, 0x08, 0x07, 0x00,/*司2567*/},\n        {\n\n                0x98, 0x54, 0x32, 0x11, 0x08, 0x00, 0x98, 0x54, 0x33, 0x10, 0x08, 0x09, 0x09, 0x09, 0x09, 0x09,\n                0x08, 0x09, 0x09, 0x09, 0x09, 0x09,/*丝2568*/},\n        {\n\n                0x42, 0x22, 0x5E, 0x92, 0x72, 0x02, 0xFE, 0x82, 0x42, 0x22, 0x12, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*死2569*/},\n        {\n\n                0x80, 0xFE, 0xAA, 0xAA, 0x00, 0xAA, 0xAA, 0xFF, 0xAA, 0xBE, 0x08, 0x06, 0x05, 0x04, 0x06, 0x0C,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*肆2570*/},\n        {\n\n                0x90, 0x92, 0x92, 0x92, 0x92, 0x9F, 0x92, 0xF2, 0x92, 0x92, 0x90, 0x00, 0x00, 0x01, 0x02, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*寺2571*/},\n        {\n\n                0xF7, 0x95, 0xF5, 0x95, 0xF7, 0x00, 0xF5, 0x15, 0xF5, 0x01, 0xFF, 0x0F, 0x00, 0x07, 0x08, 0x0F,\n                0x00, 0x03, 0x01, 0x09, 0x08, 0x07,/*嗣2572*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x82, 0x7E, 0x02, 0x02, 0x7E, 0x82, 0x82, 0xFE, 0x00, 0x0F, 0x05, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*四2573*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x08, 0xEA, 0x2A, 0x2A, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x0F, 0x00, 0x00, 0x03,\n                0x01, 0x01, 0x09, 0x09, 0x08, 0x07,/*伺2574*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFE, 0x00, 0x82, 0x0C, 0xE0, 0x1F, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x03,\n                0x09, 0x04, 0x03, 0x00, 0x03, 0x0C,/*似2575*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0xEA, 0x2A, 0x2A, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x03,\n                0x01, 0x01, 0x09, 0x09, 0x08, 0x07,/*饲2576*/},\n        {\n\n                0x00, 0xFE, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x7E, 0x00, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*巳2577*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x20, 0x18, 0x87, 0x60, 0x07, 0x18, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x06, 0x05, 0x04, 0x05, 0x0E, 0x00,/*松2578*/},\n        {\n\n                0x10, 0x18, 0xF4, 0x53, 0x54, 0x58, 0x54, 0x53, 0xF4, 0x18, 0x10, 0x04, 0x04, 0x07, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0F, 0x02, 0x02,/*耸2579*/},\n        {\n\n                0x20, 0x10, 0x08, 0x07, 0x28, 0x90, 0x08, 0x07, 0x08, 0x10, 0x20, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*怂2580*/},\n        {\n\n                0x18, 0x86, 0x60, 0x03, 0x1C, 0x00, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x06, 0x05, 0x04, 0x05, 0x0E,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颂2581*/},\n        {\n\n                0x11, 0xF2, 0x40, 0x48, 0x49, 0x4A, 0xF8, 0x4A, 0x49, 0x48, 0x40, 0x08, 0x07, 0x08, 0x0C, 0x0A,\n                0x09, 0x08, 0x09, 0x0A, 0x0C, 0x08,/*送2582*/},\n        {\n\n                0x4C, 0x44, 0x44, 0x44, 0xC5, 0xF6, 0xC4, 0x44, 0x44, 0x44, 0x4C, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*宋2583*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x20, 0x18, 0x87, 0x60, 0x00, 0x07, 0x18, 0x20, 0x00, 0x07, 0x02, 0x01, 0x06,\n                0x05, 0x04, 0x04, 0x05, 0x0E, 0x00,/*讼2584*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xF1, 0x51, 0x55, 0xF9, 0x55, 0x53, 0xF0, 0x00, 0x07, 0x02, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*诵2585*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xBC, 0xAA, 0xA0, 0xFF, 0xA0, 0xAA, 0xBE, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x09, 0x0A, 0x04, 0x04, 0x0A, 0x09,/*搜2586*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0x00, 0xBC, 0xAA, 0xFF, 0xA0, 0xAA, 0xBE, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x08, 0x09, 0x06, 0x04, 0x0A, 0x09,/*艘2587*/},\n        {\n\n                0x84, 0xFF, 0x44, 0x4A, 0xA8, 0x7F, 0x28, 0x4A, 0xFC, 0x0B, 0xF8, 0x08, 0x0F, 0x00, 0x09, 0x0B,\n                0x05, 0x0B, 0x08, 0x05, 0x02, 0x0D,/*擞2588*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x54, 0xFF, 0x54, 0x74, 0x08, 0xE7, 0x04, 0x1C, 0x03, 0x01, 0x05, 0x02, 0x0F,\n                0x01, 0x0A, 0x06, 0x01, 0x06, 0x08,/*嗽2589*/},\n        {\n\n                0x02, 0xD2, 0x12, 0x17, 0xFA, 0x12, 0x12, 0x17, 0xF2, 0x42, 0x82, 0x02, 0x09, 0x04, 0x03, 0x00,\n                0x08, 0x08, 0x08, 0x07, 0x00, 0x01,/*苏2590*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x10, 0x92, 0xFE, 0x91, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x01, 0x00, 0x0F, 0x00,/*酥2591*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x44, 0xA2, 0x91, 0x8C, 0x91, 0xA2, 0x44, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*俗2592*/},\n        {\n\n                0x22, 0x2A, 0xAA, 0xEA, 0xAA, 0xBF, 0xAA, 0x6A, 0x2A, 0x2A, 0x22, 0x00, 0x0A, 0x06, 0x02, 0x0B,\n                0x0E, 0x02, 0x02, 0x07, 0x0A, 0x00,/*素2593*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x7A, 0x4A, 0xCA, 0xFF, 0xCA, 0x4A, 0x7A, 0x02, 0x08, 0x07, 0x08, 0x0A, 0x09,\n                0x08, 0x0F, 0x08, 0x09, 0x0A, 0x08,/*速2594*/},\n        {\n\n                0x01, 0x3D, 0x65, 0xA5, 0x3F, 0xE5, 0x3F, 0xA5, 0x65, 0x3D, 0x01, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*粟2595*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x1D, 0x55, 0x1F, 0xF5, 0x1F, 0x55, 0x1D, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*僳2596*/},\n        {\n\n                0x84, 0xB5, 0x66, 0x3C, 0x26, 0xB5, 0x40, 0x3F, 0x15, 0x95, 0xFF, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*塑2597*/},\n        {\n\n                0x22, 0x44, 0xE9, 0x8A, 0xF8, 0x8A, 0xE9, 0x00, 0xFE, 0x92, 0xFE, 0x04, 0x02, 0x08, 0x04, 0x03,\n                0x00, 0x00, 0x08, 0x07, 0x08, 0x0F,/*溯2598*/},\n        {\n\n                0x4C, 0xE4, 0x14, 0xD4, 0x55, 0x76, 0x54, 0x54, 0x54, 0xD4, 0x0C, 0x00, 0x0F, 0x00, 0x0F, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*宿2599*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFE, 0x12, 0x92, 0x91, 0xF1, 0x11, 0x10, 0x00, 0x07, 0x02, 0x09, 0x07,\n                0x00, 0x00, 0x00, 0x0F, 0x01, 0x02,/*诉2600*/},\n        {\n\n                0x08, 0xAA, 0x2A, 0x2A, 0x2A, 0xFF, 0x2A, 0x2A, 0x2A, 0xBE, 0x08, 0x08, 0x07, 0x00, 0x02, 0x01,\n                0x0F, 0x01, 0x02, 0x00, 0x0F, 0x00,/*肃2601*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x20, 0x96, 0x65, 0x44, 0xD6, 0x2C, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*酸2602*/},\n        {\n\n                0x42, 0x52, 0xD2, 0x57, 0x42, 0x02, 0x42, 0x57, 0xD2, 0x52, 0x42, 0x02, 0x09, 0x0F, 0x01, 0x02,\n                0x00, 0x02, 0x09, 0x0F, 0x01, 0x02,/*蒜2603*/},\n        {\n\n                0x04, 0x03, 0xFA, 0xAE, 0xAA, 0xA8, 0xAC, 0xAB, 0xFA, 0x06, 0x02, 0x02, 0x02, 0x0B, 0x06, 0x02,\n                0x02, 0x02, 0x0E, 0x03, 0x02, 0x02,/*算2604*/},\n        {\n\n                0x00, 0xE0, 0x2F, 0x29, 0x29, 0xF9, 0x29, 0x29, 0x2F, 0xE0, 0x00, 0x04, 0x05, 0x05, 0x05, 0x05,\n                0x07, 0x05, 0x05, 0x05, 0x05, 0x0E,/*虽2605*/},\n        {\n\n                0xFF, 0x31, 0xCF, 0x00, 0x2A, 0xE6, 0xAB, 0xBA, 0xAA, 0xEA, 0x22, 0x0F, 0x02, 0x01, 0x00, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*隋2606*/},\n        {\n\n                0xFF, 0x31, 0xCF, 0x48, 0xD2, 0x0A, 0xFE, 0xAB, 0xAA, 0xFA, 0x02, 0x0F, 0x02, 0x01, 0x08, 0x07,\n                0x08, 0x0B, 0x08, 0x0A, 0x0B, 0x08,/*随2607*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x4A, 0x52, 0xC6, 0x6A, 0x41, 0xC9, 0x45, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x09, 0x05, 0x02, 0x02, 0x05, 0x08,/*绥2608*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xEF, 0x58, 0xD0, 0x2A, 0xEE, 0xBB, 0xAA, 0xEA, 0x00, 0x0F, 0x02, 0x0F, 0x08,\n                0x07, 0x08, 0x0B, 0x08, 0x0A, 0x0B,/*髓2609*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x24, 0x1C, 0x25, 0x86, 0x24, 0x1C, 0x24, 0x00, 0x07, 0x02, 0x07, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*碎2610*/},\n        {\n\n                0x00, 0x8E, 0x88, 0x48, 0x78, 0x4F, 0x48, 0x48, 0x48, 0xCE, 0x00, 0x08, 0x08, 0x08, 0x05, 0x06,\n                0x04, 0x02, 0x02, 0x01, 0x00, 0x00,/*岁2611*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x82, 0xFA, 0xAA, 0xFF, 0xAA, 0xFA, 0x82, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x0D, 0x0A, 0x0C, 0x02, 0x0C,/*穗2612*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xA4, 0x95, 0x4E, 0xB4, 0xE4, 0x46, 0xA5, 0x14, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0D, 0x0C, 0x0B, 0x08, 0x08, 0x0B,/*遂2613*/},\n        {\n\n                0xFF, 0x31, 0xCF, 0x22, 0xE4, 0xA5, 0x56, 0xAC, 0xF6, 0xA5, 0x14, 0x0F, 0x02, 0x01, 0x08, 0x07,\n                0x0A, 0x09, 0x0A, 0x0B, 0x08, 0x09,/*隧2614*/},\n        {\n\n                0x18, 0x56, 0x54, 0x54, 0x54, 0x5F, 0x54, 0x54, 0x54, 0x56, 0x18, 0x01, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x01,/*祟2615*/},\n        {\n\n                0x82, 0x82, 0xF2, 0x4E, 0x00, 0xF0, 0x00, 0xFF, 0x00, 0x30, 0xC0, 0x00, 0x08, 0x0F, 0x00, 0x01,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x01,/*孙2616*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xF0, 0x17, 0x15, 0xD5, 0x15, 0x17, 0xF0, 0x08, 0x0F, 0x00, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*损2617*/},\n        {\n\n                0x44, 0x53, 0x56, 0x5A, 0xF2, 0x50, 0x54, 0x53, 0xF6, 0x4A, 0x42, 0x08, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x01, 0x03, 0x00, 0x00,/*笋2618*/},\n        {\n\n                0x4A, 0x4A, 0xFA, 0x5F, 0x5A, 0x5E, 0x5A, 0x5F, 0xFA, 0x4A, 0x4A, 0x08, 0x08, 0x05, 0x03, 0x0F,\n                0x09, 0x03, 0x05, 0x05, 0x0A, 0x08,/*蓑2619*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x24, 0x96, 0x65, 0x44, 0x44, 0xD6, 0x2C, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*梭2620*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x24, 0x96, 0x65, 0x44, 0x44, 0xD6, 0x2C, 0x03, 0x01, 0x03, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*唆2621*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x26, 0xF2, 0x0A, 0xD3, 0x72, 0x52, 0xD6, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x00, 0x0F, 0x05, 0x05, 0x0F,/*缩2622*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xF2, 0x14, 0x10, 0xDF, 0x10, 0x14, 0xF2, 0x04, 0x07, 0x02, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*琐2623*/},\n        {\n\n                0x18, 0x0A, 0x4A, 0x6A, 0xDA, 0x4F, 0x4A, 0x2A, 0x8A, 0x0A, 0x18, 0x00, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x00,/*索2624*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xF2, 0x14, 0x10, 0xDF, 0x10, 0x14, 0xF2, 0x00, 0x0F, 0x04, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*锁2625*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xF1, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x08, 0x07, 0x00, 0x00, 0x09,\n                0x04, 0x03, 0x00, 0x00, 0x0F, 0x00,/*所2626*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0x40, 0x5F, 0xD5, 0x15, 0x55, 0x5F, 0xC0, 0x04, 0x07, 0x02, 0x00, 0x05,\n                0x0A, 0x0F, 0x00, 0x05, 0x0A, 0x0F,/*塌2627*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x20, 0xFC, 0x10, 0xFF, 0x08, 0x84, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x09, 0x08, 0x08, 0x0E,/*他2628*/},\n        {\n\n                0x1C, 0x04, 0xF4, 0x84, 0x85, 0x46, 0x44, 0x24, 0x24, 0x04, 0x1C, 0x00, 0x00, 0x07, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x0E, 0x00,/*它2629*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0xFC, 0x10, 0xFF, 0x08, 0x84, 0xFC, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x07, 0x08, 0x09, 0x08, 0x08, 0x0E,/*她2630*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x42, 0x27, 0x52, 0x4A, 0x52, 0x27, 0x42, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*塔2631*/},\n        {\n\n                0x8A, 0xFC, 0x03, 0x74, 0x54, 0xFF, 0x54, 0x74, 0xF3, 0x1A, 0xF6, 0x08, 0x07, 0x00, 0x02, 0x01,\n                0x0F, 0x01, 0x08, 0x05, 0x02, 0x0D,/*獭2632*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x11, 0xF2, 0x00, 0x88, 0x7F, 0x88, 0x08, 0x00, 0x08, 0x0F, 0x08, 0x04,\n                0x07, 0x0A, 0x09, 0x08, 0x08, 0x0B,/*挞2633*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x40, 0x5F, 0xD5, 0x15, 0x55, 0x5F, 0xC0, 0x0F, 0x08, 0x07, 0x04, 0x05,\n                0x0A, 0x0F, 0x00, 0x05, 0x0A, 0x0F,/*蹋2634*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x80, 0xD2, 0x4E, 0x50, 0x5F, 0x42, 0x4C, 0xD2, 0x0F, 0x08, 0x07, 0x04, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*踏2635*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*胎2636*/},\n        {\n\n                0x22, 0xB2, 0xAA, 0xA7, 0xA2, 0xA2, 0xA2, 0xA7, 0xA2, 0xB2, 0x62, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*苔2637*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*抬2638*/},\n        {\n\n                0x10, 0xD8, 0x54, 0x52, 0x51, 0x50, 0x50, 0x50, 0x54, 0xD8, 0x30, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*台2639*/},\n        {\n\n                0x20, 0xA2, 0x6A, 0x3A, 0x2E, 0xEB, 0x2A, 0x2A, 0x6A, 0xA2, 0x20, 0x09, 0x08, 0x05, 0x02, 0x09,\n                0x0F, 0x01, 0x02, 0x05, 0x08, 0x09,/*泰2640*/},\n        {\n\n                0xFD, 0xA5, 0x9F, 0xA5, 0xFD, 0x08, 0xC8, 0x3F, 0xC8, 0x08, 0x08, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x06, 0x01, 0x06, 0x01, 0x06, 0x08,/*酞2641*/},\n        {\n\n                0x08, 0x08, 0x08, 0x88, 0x68, 0x1F, 0xE8, 0x08, 0x08, 0x08, 0x08, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x04, 0x00, 0x03, 0x04, 0x08, 0x08,/*太2642*/},\n        {\n\n                0x44, 0x44, 0x24, 0x14, 0x0C, 0xA7, 0x4C, 0x14, 0x24, 0x44, 0x44, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*态2643*/},\n        {\n\n                0x10, 0x21, 0x0A, 0x08, 0x08, 0xE8, 0x1F, 0xE8, 0x08, 0x08, 0x08, 0x04, 0x02, 0x09, 0x04, 0x03,\n                0x02, 0x04, 0x00, 0x03, 0x04, 0x08,/*汰2644*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x40, 0xFE, 0x4A, 0x52, 0x42, 0xFE, 0x40, 0x02, 0x02, 0x01, 0x09, 0x04,\n                0x03, 0x00, 0x00, 0x08, 0x0F, 0x00,/*坍2645*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x32, 0xC2, 0x3E, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x08, 0x0F, 0x04, 0x03, 0x00,\n                0x07, 0x00, 0x0F, 0x09, 0x0F, 0x09,/*摊2646*/},\n        {\n\n                0x08, 0xC8, 0x54, 0x54, 0x52, 0xD9, 0x52, 0x74, 0x54, 0xC8, 0x08, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贪2647*/},\n        {\n\n                0x88, 0xFE, 0x52, 0x92, 0x72, 0x22, 0xF3, 0x5E, 0xF6, 0x5A, 0x52, 0x08, 0x07, 0x02, 0x01, 0x06,\n                0x00, 0x0F, 0x05, 0x07, 0x05, 0x05,/*瘫2648*/},\n        {\n\n                0x22, 0x44, 0x00, 0x32, 0xC2, 0x3E, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x04, 0x02, 0x04, 0x03, 0x00,\n                0x07, 0x00, 0x0F, 0x09, 0x0F, 0x09,/*滩2649*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x20, 0x22, 0xA2, 0x62, 0x22, 0x22, 0x20, 0x04, 0x04, 0x03, 0x02, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*坛2650*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFA, 0x8A, 0xBA, 0xAB, 0xBA, 0x8A, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x08,/*檀2651*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x22, 0x1A, 0x42, 0x23, 0x9A, 0x22, 0x52, 0x8A, 0x09, 0x04, 0x03, 0x04, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x09, 0x08,/*痰2652*/},\n        {\n\n                0x11, 0x22, 0x1C, 0xF5, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0xF5, 0x1C, 0x04, 0x02, 0x04, 0x05, 0x05,\n                0x05, 0x0F, 0x05, 0x05, 0x05, 0x04,/*潭2653*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x1D, 0xF5, 0x5F, 0x55, 0x5F, 0xF5, 0x1D, 0x00, 0x00, 0x07, 0x02, 0x04,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x04,/*谭2654*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x28, 0xA6, 0x10, 0xCF, 0x10, 0x14, 0xA2, 0x00, 0x00, 0x07, 0x0A, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x05, 0x08,/*谈2655*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xFE, 0x00, 0x04, 0x07, 0x02, 0x08, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x08,/*坦2656*/},\n        {\n\n                0x12, 0x12, 0xFE, 0x89, 0x04, 0xD2, 0x08, 0xE7, 0x88, 0x52, 0x01, 0x01, 0x01, 0x07, 0x08, 0x09,\n                0x0C, 0x0A, 0x09, 0x0A, 0x0C, 0x0C,/*毯2657*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0xFE, 0x12, 0x12, 0x12, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x08,/*袒2658*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x16, 0x94, 0x7C, 0x17, 0xD4, 0x14, 0x96, 0x00, 0x07, 0x02, 0x0B, 0x06,\n                0x01, 0x0A, 0x05, 0x03, 0x05, 0x08,/*碳2659*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x88, 0x46, 0x52, 0x4A, 0xE2, 0x4A, 0x52, 0x46, 0x01, 0x09, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*探2660*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x02, 0x3E, 0xC2, 0x02, 0x82, 0x62, 0x1E, 0x03, 0x01, 0x03, 0x08, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*叹2661*/},\n        {\n\n                0x10, 0x16, 0xFC, 0x14, 0xD4, 0x17, 0xF4, 0x14, 0x94, 0x56, 0x10, 0x08, 0x07, 0x00, 0x09, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*炭2662*/},\n        {\n\n                0x22, 0x44, 0x00, 0x22, 0x32, 0xF2, 0x2A, 0x2A, 0xE6, 0x22, 0xE0, 0x04, 0x02, 0x00, 0x04, 0x03,\n                0x08, 0x04, 0x03, 0x08, 0x08, 0x07,/*汤2663*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xFE, 0x22, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x02, 0x03, 0x09, 0x07, 0x00,\n                0x0E, 0x0A, 0x0B, 0x0A, 0x0E, 0x00,/*塘2664*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xFE, 0x22, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x08, 0x0F, 0x08, 0x07, 0x00,\n                0x0E, 0x0A, 0x0B, 0x0A, 0x0E, 0x00,/*搪2665*/},\n        {\n\n                0x0C, 0x05, 0xF6, 0x94, 0x94, 0x97, 0x94, 0x94, 0xF6, 0x05, 0x0C, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*堂2666*/},\n        {\n\n                0x0C, 0x04, 0x75, 0x56, 0x54, 0xD7, 0x54, 0x56, 0x75, 0x04, 0x0C, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*棠2667*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x0D, 0xF6, 0x94, 0x97, 0x94, 0xF6, 0x0D, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*膛2668*/},\n        {\n\n                0x00, 0xFE, 0x22, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xFA, 0x22, 0x08, 0x07, 0x00, 0x0E, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x0A, 0x0E, 0x00,/*唐2669*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0xFE, 0x22, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x01, 0x00, 0x0F, 0x08, 0x07,\n                0x00, 0x0E, 0x0B, 0x0A, 0x0E, 0x00,/*糖2670*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xF2, 0x14, 0xD0, 0x5F, 0xD0, 0x14, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*倘2671*/},\n        {\n\n                0x80, 0xFE, 0xAB, 0xFE, 0x00, 0xF2, 0x14, 0xDF, 0x50, 0xD4, 0xF2, 0x04, 0x02, 0x09, 0x0F, 0x00,\n                0x0F, 0x00, 0x03, 0x02, 0x0B, 0x0F,/*躺2672*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xF2, 0x14, 0xD0, 0x5F, 0xD0, 0x14, 0xF2, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*淌2673*/},\n        {\n\n                0xA4, 0x24, 0xFF, 0x24, 0xF9, 0x0A, 0xE8, 0xAF, 0xE8, 0x0A, 0xF9, 0x0F, 0x04, 0x0F, 0x09, 0x0B,\n                0x08, 0x08, 0x08, 0x08, 0x0A, 0x0B,/*趟2674*/},\n        {\n\n                0x88, 0x51, 0x02, 0x40, 0x49, 0x2D, 0x1D, 0x4B, 0x3B, 0x89, 0xF8, 0x08, 0x0A, 0x09, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x0A, 0x09, 0x08,/*烫2675*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x04, 0x53, 0x4E, 0xFA, 0x4A, 0x4A, 0x02, 0xFE, 0x08, 0x0F, 0x00, 0x00, 0x03,\n                0x02, 0x03, 0x02, 0x0B, 0x08, 0x07,/*掏2676*/},\n        {\n\n                0x22, 0x44, 0x00, 0x22, 0xAA, 0xFA, 0xAF, 0xAA, 0xAA, 0xEA, 0xA2, 0x04, 0x02, 0x08, 0x06, 0x01,\n                0x00, 0x01, 0x02, 0x08, 0x0F, 0x00,/*涛2677*/},\n        {\n\n                0x22, 0x44, 0x02, 0xEA, 0x32, 0x22, 0x16, 0x09, 0x31, 0x29, 0xE5, 0x04, 0x02, 0x00, 0x0F, 0x09,\n                0x09, 0x08, 0x08, 0x09, 0x09, 0x0F,/*滔2678*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xA8, 0xA4, 0xAB, 0xD2, 0xAA, 0xA6, 0xA0, 0x04, 0x04, 0x02, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*绦2679*/},\n        {\n\n                0x92, 0xCE, 0xBA, 0xAF, 0xEA, 0xAA, 0xAA, 0xAF, 0x8A, 0x0A, 0xFA, 0x00, 0x06, 0x04, 0x04, 0x07,\n                0x04, 0x04, 0x06, 0x08, 0x08, 0x07,/*萄2680*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x84, 0x48, 0xFF, 0x00, 0xFF, 0x48, 0x84, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*桃2681*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x44, 0x28, 0xFF, 0x00, 0xFF, 0x28, 0x44, 0x00, 0x08, 0x07, 0x08, 0x0A, 0x09,\n                0x08, 0x08, 0x09, 0x0A, 0x0A, 0x0B,/*逃2682*/},\n        {\n\n                0x22, 0x44, 0x08, 0x44, 0x53, 0x4E, 0xFA, 0x4A, 0x4A, 0x02, 0xFE, 0x04, 0x02, 0x01, 0x00, 0x03,\n                0x02, 0x03, 0x02, 0x0B, 0x08, 0x07,/*淘2683*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x44, 0x53, 0x4E, 0xFA, 0x4A, 0x4A, 0x02, 0xFE, 0x0F, 0x02, 0x01, 0x00, 0x03,\n                0x02, 0x03, 0x02, 0x0B, 0x08, 0x07,/*陶2684*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x08, 0x48, 0x88, 0x08, 0x08, 0xFF, 0x08, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x01, 0x08, 0x08, 0x0F, 0x00,/*讨2685*/},\n        {\n\n                0x12, 0x12, 0xFA, 0xAE, 0xAB, 0xAA, 0xAA, 0xAE, 0x0A, 0x12, 0x12, 0x02, 0x0A, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0E, 0x0A, 0x02,/*套2686*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x10, 0x54, 0x54, 0x5F, 0xF4, 0x54, 0x50, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x0A, 0x08, 0x0F, 0x00, 0x00,/*特2687*/},\n        {\n\n                0x02, 0xFA, 0x4F, 0xFA, 0x82, 0xAA, 0xE2, 0xBA, 0xA7, 0xAA, 0x82, 0x08, 0x07, 0x09, 0x0F, 0x0A,\n                0x05, 0x08, 0x0E, 0x00, 0x05, 0x0A,/*藤2688*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x50, 0xF5, 0x5C, 0x57, 0xD4, 0x35, 0x50, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x05, 0x05, 0x05, 0x05, 0x09, 0x0F,/*腾2689*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x22, 0x12, 0xAE, 0x4B, 0x4A, 0xAA, 0x1A, 0x02, 0x09, 0x04, 0x03, 0x01, 0x01,\n                0x04, 0x05, 0x09, 0x0A, 0x01, 0x01,/*疼2690*/},\n        {\n\n                0x48, 0xAA, 0xBB, 0xAA, 0xAE, 0xBB, 0xAA, 0xAA, 0xBB, 0xAA, 0x48, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*誊2691*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0x75, 0x56, 0xFC, 0x56, 0x5D, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x00, 0x02, 0x03,/*梯2692*/},\n        {\n\n                0x80, 0x5F, 0xF5, 0x55, 0xD5, 0x5F, 0xC0, 0x00, 0xFC, 0x00, 0xFF, 0x02, 0x09, 0x04, 0x02, 0x09,\n                0x08, 0x07, 0x00, 0x01, 0x08, 0x0F,/*剔2693*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x80, 0x5F, 0xF5, 0x55, 0xD5, 0x5F, 0xC0, 0x07, 0x04, 0x03, 0x02, 0x02,\n                0x09, 0x04, 0x02, 0x09, 0x08, 0x07,/*踢2694*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x75, 0x56, 0xFC, 0x56, 0x5D, 0xC0, 0x00, 0x0F, 0x04, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x00, 0x02, 0x03,/*锑2695*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x08, 0x5F, 0x55, 0xD5, 0x55, 0x5F, 0x40, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x07, 0x08, 0x0F, 0x09, 0x09, 0x08,/*提2696*/},\n        {\n\n                0x40, 0x5F, 0x55, 0xD5, 0x5F, 0x40, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x08, 0x07, 0x08, 0x0F, 0x09,\n                0x08, 0x0A, 0x09, 0x08, 0x09, 0x0A,/*题2697*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x32, 0xD6, 0x5A, 0xF3, 0x5A, 0xD6, 0x32, 0x07, 0x04, 0x03, 0x02, 0x00,\n                0x03, 0x00, 0x0F, 0x02, 0x03, 0x00,/*蹄2698*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xB2, 0x96, 0x9A, 0xD3, 0x9A, 0x96, 0xB2, 0x03, 0x01, 0x03, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*啼2699*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x88, 0x48, 0x28, 0xFF, 0x28, 0x48, 0x88, 0x00, 0x00, 0x0F, 0x01, 0x00, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x00, 0x01,/*体2700*/},\n        {\n\n                0x48, 0x2A, 0xDA, 0x4F, 0x5A, 0x68, 0x5A, 0x4F, 0xDA, 0x2A, 0x48, 0x00, 0x00, 0x0F, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0F, 0x00, 0x00,/*替2701*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x98, 0x8A, 0xFA, 0xAA, 0xFF, 0xAA, 0xFA, 0x9A, 0x03, 0x01, 0x03, 0x08, 0x06,\n                0x08, 0x08, 0x0F, 0x0A, 0x0A, 0x09,/*嚏2702*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x80, 0x5F, 0xF5, 0x55, 0xD5, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x09, 0x04, 0x02, 0x09, 0x08, 0x07,/*惕2703*/},\n        {\n\n                0x22, 0x44, 0x00, 0x74, 0x55, 0xD6, 0xFC, 0x56, 0x55, 0x5C, 0xC0, 0x04, 0x02, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x02, 0x02, 0x01,/*涕2704*/},\n        {\n\n                0x74, 0x55, 0x56, 0xFC, 0x56, 0x5D, 0xC0, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x01, 0x0F, 0x00,\n                0x02, 0x03, 0x00, 0x01, 0x08, 0x0F,/*剃2705*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xE9, 0x49, 0x49, 0xF9, 0x49, 0x49, 0xF9, 0x4F, 0x08, 0x07, 0x00, 0x0F, 0x08,\n                0x08, 0x0B, 0x0A, 0x0A, 0x0B, 0x08,/*屉2706*/},\n        {\n\n                0x20, 0x22, 0x22, 0x22, 0xA2, 0x7E, 0xA2, 0x22, 0x22, 0x22, 0x20, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*天2707*/},\n        {\n\n                0x22, 0x44, 0x00, 0x48, 0x29, 0x19, 0xCF, 0x09, 0x19, 0x29, 0x48, 0x04, 0x02, 0x01, 0x04, 0x02,\n                0x08, 0x0F, 0x01, 0x06, 0x01, 0x06,/*添2708*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xFA, 0x02, 0x02, 0x03, 0x01, 0x02, 0x0B,\n                0x06, 0x02, 0x02, 0x06, 0x0B, 0x02,/*填2709*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x22, 0xFE, 0x00, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x0F, 0x00,/*田2710*/},\n        {\n\n                0x92, 0x92, 0xFE, 0x91, 0x91, 0x04, 0xFF, 0x44, 0x44, 0xFF, 0x04, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*甜2711*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*恬2712*/},\n        {\n\n                0x92, 0xFE, 0x91, 0x48, 0x29, 0x19, 0xCF, 0x09, 0x19, 0x29, 0x48, 0x0F, 0x04, 0x0F, 0x04, 0x02,\n                0x08, 0x0F, 0x01, 0x06, 0x01, 0x06,/*舔2713*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x24, 0xFF, 0x24, 0xFF, 0x24, 0xFC, 0x00, 0x08, 0x07, 0x08, 0x0F, 0x01,\n                0x09, 0x05, 0x01, 0x05, 0x09, 0x01,/*腆2714*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x84, 0x48, 0xFF, 0x00, 0xFF, 0x48, 0x84, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*挑2715*/},\n        {\n\n                0x20, 0xA4, 0x92, 0x97, 0x8A, 0xEA, 0x8A, 0x96, 0x92, 0xA0, 0x20, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*条2716*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x21, 0xD1, 0x4F, 0x41, 0x51, 0x51, 0xCF, 0x00, 0x08, 0x07, 0x08, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*迢2717*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x84, 0x48, 0xFF, 0x00, 0xFF, 0x48, 0x84, 0x0F, 0x04, 0x04, 0x07, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*眺2718*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x84, 0x48, 0xFF, 0x00, 0xFF, 0x48, 0x84, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*跳2719*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0xC0, 0x40, 0x7F, 0x48, 0xC8, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*贴2720*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x50, 0x4C, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*铁2721*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xC0, 0x40, 0x7F, 0x48, 0xC8, 0x01, 0x00, 0x0F, 0x01, 0x01,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*帖2722*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x12, 0x12, 0x12, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*厅2723*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x00, 0x00,/*听2724*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x44, 0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*烃2725*/},\n        {\n\n                0x22, 0x44, 0x00, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*汀2726*/},\n        {\n\n                0x02, 0x32, 0x2A, 0xE6, 0x00, 0x12, 0x12, 0xFE, 0x11, 0x11, 0x00, 0x08, 0x05, 0x02, 0x05, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x09,/*廷2727*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x82, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x82, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x02, 0x0A, 0x0E, 0x02, 0x02, 0x01,/*停2728*/},\n        {\n\n                0x82, 0x82, 0xBA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBA, 0x82, 0x82, 0x01, 0x02, 0x02, 0x0A, 0x0A,\n                0x0E, 0x02, 0x02, 0x02, 0x02, 0x01,/*亭2729*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xCA, 0xBA, 0x02, 0x53, 0x52, 0xF2, 0x4A, 0x4A, 0x08, 0x07, 0x0A, 0x04, 0x0B,\n                0x08, 0x0A, 0x0A, 0x0B, 0x0A, 0x0A,/*庭2730*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x72, 0xCE, 0x00, 0x22, 0xFE, 0x21, 0x00, 0x08, 0x0F, 0x00, 0x0A, 0x04,\n                0x0B, 0x08, 0x0A, 0x0B, 0x0A, 0x08,/*挺2731*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0x00, 0x72, 0xCE, 0x00, 0x22, 0xFE, 0x21, 0x08, 0x07, 0x08, 0x0F, 0x0A,\n                0x04, 0x0B, 0x08, 0x0A, 0x0B, 0x0A,/*艇2732*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xF9, 0xA9, 0xAB, 0xFD, 0xAD, 0xAB, 0xF8, 0x00, 0x08, 0x07, 0x08, 0x0B, 0x08,\n                0x08, 0x0B, 0x08, 0x0A, 0x0B, 0x08,/*通2733*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0x02, 0xEA, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*桐2734*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0xFE, 0x2A, 0xEA, 0x02, 0xFE, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x01, 0x01, 0x08, 0x0F,/*酮2735*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x08, 0xFA, 0xAE, 0xFB, 0xAE, 0xFA, 0x08, 0x0F, 0x04, 0x04, 0x07, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*瞳2736*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xEA, 0x2A, 0x2A, 0x2A, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x0F, 0x00, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x0F,/*同2737*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x02, 0xEA, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*铜2738*/},\n        {\n\n                0x40, 0xFE, 0x4A, 0x52, 0x42, 0xFE, 0x40, 0x88, 0x44, 0x23, 0x18, 0x08, 0x07, 0x00, 0x00, 0x08,\n                0x0F, 0x08, 0x08, 0x04, 0x02, 0x01,/*彤2739*/},\n        {\n\n                0x08, 0xFA, 0xAA, 0xAE, 0xAA, 0xFB, 0xAA, 0xAE, 0xAA, 0xFA, 0x08, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*童2740*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xF1, 0x51, 0x55, 0xF9, 0x55, 0x53, 0xF0, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*桶2741*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xF1, 0x51, 0x55, 0xF9, 0x55, 0x53, 0xF0, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*捅2742*/},\n        {\n\n                0x04, 0xFB, 0x0A, 0xAE, 0xAA, 0xAC, 0xAB, 0xAA, 0x0E, 0xFA, 0x02, 0x00, 0x0F, 0x00, 0x03, 0x02,\n                0x02, 0x02, 0x0B, 0x08, 0x0F, 0x00,/*筒2743*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0x64, 0xD4, 0x4D, 0xC6, 0x54, 0xE4, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*统2744*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xEA, 0xAA, 0xBB, 0xEA, 0xBA, 0xAA, 0xE2, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x02, 0x02, 0x07, 0x02, 0x0A, 0x0F,/*痛2745*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xE8, 0xA4, 0xAA, 0xE9, 0x0A, 0xC4, 0x08, 0xE8, 0x00, 0x0F, 0x00, 0x0F, 0x02,\n                0x0A, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*偷2746*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x88, 0x50, 0xCF, 0x41, 0x41, 0x4F, 0xD0, 0x10, 0x01, 0x09, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*投2747*/},\n        {\n\n                0x40, 0x48, 0x50, 0x42, 0x44, 0xC0, 0x7F, 0x40, 0x40, 0x40, 0x40, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x00, 0x01, 0x02, 0x04, 0x08,/*头2748*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x28, 0x5A, 0xCA, 0x7E, 0x4A, 0xDA, 0x29, 0x08, 0x08, 0x07, 0x08, 0x0C, 0x0A,\n                0x09, 0x08, 0x0D, 0x0D, 0x0B, 0x08,/*透2749*/},\n        {\n\n                0xF0, 0x10, 0x10, 0x1F, 0x01, 0x01, 0x01, 0x1F, 0x10, 0x10, 0xF0, 0x0F, 0x04, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*凸2750*/},\n        {\n\n                0x48, 0x48, 0x2A, 0x9A, 0x8A, 0xBE, 0x89, 0x99, 0x29, 0x48, 0x48, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*秃2751*/},\n        {\n\n                0x9C, 0x84, 0x94, 0x8C, 0x85, 0xE6, 0x84, 0xAC, 0xD4, 0x84, 0x9C, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*突2752*/},\n        {\n\n                0xFF, 0x21, 0x29, 0x2D, 0x57, 0x55, 0x95, 0x2D, 0x21, 0x21, 0xFF, 0x0F, 0x04, 0x04, 0x05, 0x05,\n                0x06, 0x06, 0x04, 0x04, 0x04, 0x0F,/*图2753*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x00, 0xA4, 0x24, 0xFF, 0x24, 0x24, 0x20, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x04, 0x0F, 0x09, 0x09, 0x08,/*徒2754*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x28, 0xA4, 0x2A, 0xF9, 0x2A, 0xA4, 0x28, 0x08, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x0A, 0x0B, 0x08, 0x08, 0x09,/*途2755*/},\n        {\n\n                0x22, 0x44, 0x00, 0x48, 0x54, 0x52, 0xF1, 0x52, 0x54, 0x48, 0x08, 0x04, 0x02, 0x04, 0x02, 0x01,\n                0x08, 0x0F, 0x00, 0x01, 0x06, 0x00,/*涂2756*/},\n        {\n\n                0x00, 0xFF, 0x45, 0x55, 0xD5, 0x55, 0x7D, 0x55, 0x65, 0xDD, 0x47, 0x08, 0x07, 0x02, 0x01, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*屠2757*/},\n        {\n\n                0x00, 0x10, 0x10, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x10, 0x10, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*土2758*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x00, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x00, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*吐2759*/},\n        {\n\n                0x10, 0xF8, 0x94, 0x93, 0x92, 0xF2, 0x9A, 0x96, 0x90, 0xF0, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x0A, 0x08, 0x0C,/*兔2760*/},\n        {\n\n                0x22, 0x44, 0xA0, 0xAE, 0xA8, 0xA8, 0xEF, 0xA8, 0xA8, 0xAE, 0xA0, 0x04, 0x02, 0x0F, 0x00, 0x00,\n                0x07, 0x00, 0x07, 0x00, 0x08, 0x0F,/*湍2761*/},\n        {\n\n                0xFF, 0x01, 0x89, 0x49, 0x29, 0x19, 0xFF, 0x09, 0x09, 0x01, 0xFF, 0x0F, 0x04, 0x04, 0x04, 0x04,\n                0x05, 0x05, 0x04, 0x04, 0x04, 0x0F,/*团2762*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*推2763*/},\n        {\n\n                0x4A, 0x2A, 0xFE, 0x29, 0x49, 0x00, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x08, 0x07, 0x01, 0x0F, 0x04,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颓2764*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x22, 0xEC, 0x00, 0xFF, 0x35, 0xD5, 0x5F, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x07, 0x04, 0x0B, 0x09, 0x08, 0x0B,/*腿2765*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x00, 0xF9, 0x8A, 0x88, 0x8A, 0xF9, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x00, 0x08, 0x07, 0x00, 0x0F, 0x08,/*蜕2766*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x22, 0xEC, 0x00, 0xFF, 0x35, 0xD5, 0x5F, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x04, 0x0B, 0x09, 0x08, 0x0B,/*褪2767*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xFF, 0x15, 0xB5, 0x55, 0x95, 0x5F, 0x20, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x09, 0x08, 0x08, 0x08, 0x0B, 0x08,/*退2768*/},\n        {\n\n                0x88, 0x49, 0xA9, 0x99, 0x8D, 0x8B, 0x89, 0x99, 0xA9, 0x49, 0x88, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x0F, 0x00, 0x00,/*吞2769*/},\n        {\n\n                0x04, 0xF4, 0x84, 0x84, 0x84, 0xFF, 0x84, 0x84, 0x84, 0xF4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*屯2770*/},\n        {\n\n                0x40, 0xBF, 0xD5, 0xBD, 0x95, 0xBF, 0xD4, 0xDB, 0xA9, 0xDB, 0x42, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*臀2771*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x48, 0xF4, 0x47, 0xFC, 0x24, 0x14, 0xF4, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x0B, 0x08, 0x09, 0x0D,/*拖2772*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x42, 0x42, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*托2773*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x79, 0xCA, 0x48, 0xCA, 0x79, 0x00, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*脱2774*/},\n        {\n\n                0x7E, 0x4B, 0x52, 0x5E, 0xC0, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x2C, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*鸵2775*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x2C, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*陀2776*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x08, 0x88, 0x7F, 0x88, 0x08, 0x08, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x08, 0x07, 0x00, 0x03, 0x04, 0x08,/*驮2777*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x2C, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*驼2778*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0xFE, 0x32, 0xCE, 0x24, 0xFC, 0x57, 0x54, 0xF4, 0x00, 0x0F, 0x00, 0x0F, 0x02,\n                0x01, 0x00, 0x0F, 0x01, 0x09, 0x0F,/*椭2779*/},\n        {\n\n                0x82, 0x8A, 0x92, 0x82, 0xCA, 0x92, 0x81, 0x81, 0x91, 0x8D, 0x81, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*妥2780*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x88, 0x42, 0xF2, 0x2E, 0x22, 0x22, 0xE2, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*拓2781*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x48, 0xFA, 0x4A, 0xFE, 0x49, 0xF9, 0x48, 0x03, 0x01, 0x03, 0x00, 0x02,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x02,/*唾2782*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x4C, 0x54, 0x4D, 0x46, 0xCC, 0x54, 0x0C, 0x08, 0x0F, 0x00, 0x00, 0x04,\n                0x0A, 0x09, 0x09, 0x08, 0x08, 0x0C,/*挖2783*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*哇2784*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x00, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x08, 0x09, 0x09, 0x0F, 0x09, 0x09,/*蛙2785*/},\n        {\n\n                0x22, 0x44, 0x20, 0x24, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x24, 0x20, 0x04, 0x02, 0x09, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x08,/*洼2786*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*娃2787*/},\n        {\n\n                0x02, 0x02, 0xE2, 0x1E, 0x52, 0x92, 0x12, 0xF2, 0x02, 0x02, 0x02, 0x00, 0x0F, 0x08, 0x04, 0x04,\n                0x01, 0x00, 0x07, 0x08, 0x08, 0x0E,/*瓦2788*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0x24, 0xA4, 0xFF, 0xA4, 0x24, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*袜2789*/},\n        {\n\n                0x51, 0x51, 0x49, 0x49, 0x45, 0xDF, 0x41, 0x45, 0x45, 0x49, 0x51, 0x08, 0x08, 0x0F, 0x08, 0x08,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*歪2790*/},\n        {\n\n                0x40, 0x30, 0x4F, 0x88, 0x78, 0x00, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*外2791*/},\n        {\n\n                0x7A, 0x4A, 0x7A, 0x80, 0x66, 0x9A, 0xF2, 0x03, 0xF2, 0x92, 0xF6, 0x09, 0x0A, 0x05, 0x04, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*豌2792*/},\n        {\n\n                0x12, 0xAA, 0xA2, 0xBE, 0xA2, 0xA3, 0xA2, 0xBE, 0xA2, 0xEA, 0x12, 0x00, 0x03, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0A, 0x06,/*弯2793*/},\n        {\n\n                0x22, 0x44, 0x00, 0x12, 0xAA, 0xBE, 0xA2, 0xA3, 0xBE, 0xEA, 0x12, 0x04, 0x02, 0x01, 0x00, 0x03,\n                0x02, 0x02, 0x0A, 0x0A, 0x0A, 0x06,/*湾2794*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x10, 0x12, 0xF2, 0x12, 0xF2, 0x12, 0x10, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*玩2795*/},\n        {\n\n                0x10, 0xF2, 0x12, 0xF2, 0x10, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x08, 0x07, 0x00, 0x07, 0x02,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*顽2796*/},\n        {\n\n                0x08, 0x28, 0x48, 0xFF, 0x08, 0x08, 0x08, 0xF8, 0x00, 0x00, 0x00, 0x08, 0x04, 0x03, 0x00, 0x01,\n                0x02, 0x00, 0x07, 0x08, 0x08, 0x0E,/*丸2797*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x8C, 0xA4, 0xA5, 0xA6, 0xA4, 0xA4, 0x8C, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*烷2798*/},\n        {\n\n                0x86, 0x82, 0x92, 0x92, 0x92, 0x93, 0x92, 0x92, 0x92, 0x82, 0x86, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*完2799*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x80, 0x66, 0x9A, 0xF2, 0x03, 0xF2, 0x92, 0xF6, 0x07, 0x02, 0x07, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*碗2800*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xF8, 0x94, 0x93, 0xF2, 0x9A, 0x96, 0xF0, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*挽2801*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0xF8, 0x94, 0x93, 0xF2, 0x9A, 0x96, 0xF0, 0x07, 0x02, 0x07, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*晚2802*/},\n        {\n\n                0xFC, 0x46, 0xFD, 0x00, 0x8C, 0xA4, 0xA5, 0xA6, 0xA4, 0xA4, 0x8C, 0x0F, 0x04, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*皖2803*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x88, 0x66, 0x9A, 0xF2, 0x03, 0xF2, 0x92, 0xF6, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*惋2804*/},\n        {\n\n                0x86, 0x62, 0x9A, 0x12, 0xF2, 0x03, 0xF2, 0x12, 0x12, 0xF2, 0x06, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x07, 0x08, 0x09, 0x09, 0x0C,/*宛2805*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x66, 0x9A, 0xF2, 0x03, 0xF2, 0x92, 0xF6, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*婉2806*/},\n        {\n\n                0x02, 0x02, 0x02, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0xE2, 0x02, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x08, 0x08, 0x08, 0x07, 0x00,/*万2807*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x80, 0x66, 0x9A, 0xF2, 0x03, 0xF2, 0x92, 0xF6, 0x07, 0x08, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*腕2808*/},\n        {\n\n                0x22, 0x44, 0x00, 0x42, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x42, 0x00, 0x04, 0x02, 0x09, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x08,/*汪2809*/},\n        {\n\n                0x00, 0x42, 0x42, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x42, 0x42, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*王2810*/},\n        {\n\n                0x08, 0x08, 0xF8, 0x08, 0x09, 0x0A, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x0F, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*亡2811*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*枉2812*/},\n        {\n\n                0xFF, 0x09, 0x91, 0x61, 0x91, 0x09, 0x91, 0x61, 0x91, 0x09, 0xFF, 0x0F, 0x01, 0x00, 0x00, 0x00,\n                0x01, 0x00, 0x00, 0x08, 0x09, 0x0F,/*网2813*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x00, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*往2814*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x00, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x00, 0x07, 0x02, 0x02, 0x03, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*旺2815*/},\n        {\n\n                0x04, 0xBC, 0xA5, 0xA6, 0xA4, 0xC0, 0xBF, 0x95, 0x95, 0xD5, 0x7F, 0x08, 0x08, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x08, 0x08,/*望2816*/},\n        {\n\n                0x04, 0x04, 0x3C, 0x24, 0x24, 0xA5, 0x26, 0x24, 0x24, 0x24, 0x04, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*忘2817*/},\n        {\n\n                0x84, 0x84, 0xBC, 0xA4, 0xE4, 0xA5, 0xA6, 0xA4, 0xA4, 0xA4, 0x84, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*妄2818*/},\n        {\n\n                0x00, 0xFC, 0x54, 0xF4, 0x54, 0xD4, 0x04, 0xFF, 0x04, 0xC5, 0x36, 0x08, 0x07, 0x05, 0x02, 0x02,\n                0x05, 0x08, 0x04, 0x03, 0x04, 0x0F,/*威2819*/},\n        {\n\n                0xA0, 0x6B, 0xFA, 0x66, 0xA2, 0xF3, 0x5A, 0xF6, 0x52, 0xF3, 0x00, 0x09, 0x0B, 0x05, 0x05, 0x0B,\n                0x09, 0x05, 0x07, 0x09, 0x0B, 0x0C,/*巍2820*/},\n        {\n\n                0x24, 0xF2, 0x09, 0x0E, 0xA8, 0xAF, 0xA8, 0x1E, 0xE8, 0x07, 0xFC, 0x00, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x07, 0x0A, 0x04, 0x03, 0x0C,/*微2821*/},\n        {\n\n                0x10, 0x08, 0xFC, 0x0B, 0xEA, 0x2A, 0x2A, 0x2A, 0x2E, 0xE8, 0x08, 0x08, 0x06, 0x01, 0x00, 0x07,\n                0x08, 0x08, 0x09, 0x09, 0x08, 0x0E,/*危2822*/},\n        {\n\n                0x44, 0x54, 0x54, 0x54, 0x54, 0xFF, 0x54, 0x54, 0x54, 0x54, 0xC4, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x04, 0x04, 0x03,/*韦2823*/},\n        {\n\n                0x11, 0xF2, 0x40, 0x54, 0x54, 0x54, 0xFF, 0x54, 0x54, 0x54, 0xC4, 0x08, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x0A, 0x0A, 0x09,/*违2824*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x08, 0xF4, 0x13, 0xD2, 0x5A, 0x56, 0xD0, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x07, 0x08, 0x09, 0x0D,/*桅2825*/},\n        {\n\n                0xFF, 0x01, 0x89, 0xA9, 0xA9, 0xFD, 0xA9, 0xA9, 0x89, 0x01, 0xFF, 0x0F, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x0A, 0x0B, 0x08, 0x0F,/*围2826*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x04, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*唯2827*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x24, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*惟2828*/},\n        {\n\n                0x00, 0x08, 0x0A, 0x0C, 0xC8, 0x38, 0x4F, 0x88, 0x08, 0x08, 0xF8, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x09, 0x08, 0x08, 0x07,/*为2829*/},\n        {\n\n                0x11, 0x22, 0xDC, 0xB3, 0x88, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x24, 0x04, 0x02, 0x04, 0x04, 0x02,\n                0x00, 0x0F, 0x09, 0x0F, 0x09, 0x09,/*潍2830*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*维2831*/},\n        {\n\n                0x12, 0x52, 0x52, 0x57, 0x52, 0xFA, 0x52, 0x57, 0x52, 0x52, 0x12, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x05, 0x05, 0x03,/*苇2832*/},\n        {\n\n                0x22, 0xAA, 0x6A, 0x2F, 0xAA, 0x7A, 0x2A, 0x2F, 0x6A, 0xA6, 0x22, 0x01, 0x09, 0x09, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*萎2833*/},\n        {\n\n                0xA8, 0xAA, 0x9A, 0x8A, 0xCA, 0xBE, 0x8A, 0x8A, 0x99, 0xA9, 0xA8, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*委2834*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x44, 0x54, 0x54, 0xFF, 0x54, 0x54, 0x54, 0xC4, 0x00, 0x0F, 0x00, 0x00, 0x00,\n                0x00, 0x0F, 0x00, 0x04, 0x04, 0x03,/*伟2835*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x0A, 0x0C, 0xE8, 0x5F, 0x88, 0x08, 0xF8, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x08, 0x09, 0x08, 0x07,/*伪2836*/},\n        {\n\n                0x00, 0xFF, 0x05, 0xA5, 0xA5, 0xA5, 0xE5, 0x55, 0x55, 0x15, 0x07, 0x08, 0x07, 0x02, 0x02, 0x02,\n                0x02, 0x07, 0x09, 0x09, 0x09, 0x0C,/*尾2837*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x44, 0x54, 0x54, 0xFF, 0x54, 0x54, 0xC4, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*纬2838*/},\n        {\n\n                0x20, 0x24, 0x24, 0xA4, 0x64, 0xFF, 0x64, 0xA4, 0x24, 0x24, 0x20, 0x02, 0x02, 0x01, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x02,/*未2839*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xBA, 0x02, 0xA7, 0x22, 0xFA, 0x22, 0x04, 0x03, 0x04, 0x0A, 0x0F,\n                0x02, 0x04, 0x00, 0x09, 0x0F, 0x00,/*蔚2840*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x20, 0x24, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x03, 0x01, 0x01, 0x03, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*味2841*/},\n        {\n\n                0x40, 0xDF, 0x55, 0x55, 0xD5, 0x5F, 0x55, 0x55, 0x55, 0xDF, 0x40, 0x00, 0x0F, 0x08, 0x04, 0x04,\n                0x01, 0x02, 0x06, 0x05, 0x08, 0x08,/*畏2842*/},\n        {\n\n                0x00, 0x1F, 0xF5, 0x55, 0x55, 0x5F, 0x55, 0x55, 0xF5, 0x1F, 0x00, 0x00, 0x00, 0x0F, 0x01, 0x01,\n                0x01, 0x01, 0x09, 0x0F, 0x00, 0x00,/*胃2843*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x40, 0xDF, 0x55, 0x55, 0xDF, 0x55, 0x55, 0x5F, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x08, 0x04, 0x01, 0x02, 0x06, 0x09,/*喂2844*/},\n        {\n\n                0xAA, 0x9A, 0xFE, 0x99, 0xA9, 0x7C, 0xD6, 0x7D, 0xD4, 0x7C, 0x00, 0x0A, 0x0B, 0x04, 0x06, 0x09,\n                0x06, 0x01, 0x07, 0x0A, 0x0B, 0x0C,/*魏2845*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x08, 0x68, 0x88, 0x09, 0x0A, 0x08, 0xE8, 0x08, 0x00, 0x0F, 0x00, 0x08, 0x08,\n                0x0B, 0x08, 0x0C, 0x0B, 0x08, 0x08,/*位2846*/},\n        {\n\n                0x11, 0x22, 0x1F, 0xF5, 0x55, 0x55, 0x5F, 0x55, 0x55, 0xF5, 0x1F, 0x04, 0x02, 0x00, 0x0F, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x0F, 0x00,/*渭2847*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x1F, 0xF5, 0x55, 0x55, 0x5F, 0x55, 0xF5, 0x1F, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x09, 0x0F, 0x00,/*谓2848*/},\n        {\n\n                0x00, 0xFF, 0x45, 0x55, 0xD5, 0x55, 0x47, 0x48, 0x88, 0xFF, 0x08, 0x08, 0x07, 0x02, 0x09, 0x0F,\n                0x01, 0x02, 0x00, 0x08, 0x0F, 0x00,/*尉2849*/},\n        {\n\n                0xA0, 0x5F, 0x95, 0xF5, 0x15, 0x57, 0x80, 0x0A, 0x92, 0xFF, 0x02, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*慰2850*/},\n        {\n\n                0x00, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x82, 0x82, 0x82, 0x7E, 0x00, 0x08, 0x08, 0x08, 0x08, 0x0F,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*卫2851*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xFA, 0xAA, 0xAB, 0xAA, 0xFA, 0x02, 0x02, 0x09, 0x04, 0x0B, 0x0E, 0x0A,\n                0x0E, 0x0A, 0x0E, 0x0A, 0x0E, 0x08,/*瘟2852*/},\n        {\n\n                0x22, 0x44, 0x00, 0xC0, 0x5F, 0xD5, 0x55, 0xD5, 0x5F, 0xC0, 0x00, 0x04, 0x02, 0x09, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*温2853*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x08, 0xF8, 0x09, 0x0A, 0xF8, 0x08, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*蚊2854*/},\n        {\n\n                0x04, 0x04, 0x1C, 0x64, 0x85, 0x06, 0x84, 0x64, 0x1C, 0x04, 0x04, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x04, 0x08, 0x08,/*文2855*/},\n        {\n\n                0xF9, 0x02, 0x08, 0xF8, 0xA9, 0xA9, 0xA9, 0xF9, 0x09, 0x01, 0xFF, 0x0F, 0x00, 0x02, 0x03, 0x02,\n                0x02, 0x02, 0x07, 0x09, 0x08, 0x0F,/*闻2856*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x04, 0x3C, 0xC5, 0x06, 0xC4, 0x3C, 0x04, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*纹2857*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x20, 0x18, 0xC7, 0x3C, 0x84, 0x7C, 0x04, 0xFC, 0x03, 0x01, 0x03, 0x02, 0x09,\n                0x04, 0x02, 0x01, 0x08, 0x08, 0x07,/*吻2858*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x84, 0xAB, 0xAA, 0xAA, 0xAE, 0xF8, 0x00, 0x01, 0x00, 0x0F, 0x04, 0x02,\n                0x0C, 0x09, 0x0A, 0x0C, 0x02, 0x04,/*稳2859*/},\n        {\n\n                0x22, 0x22, 0x52, 0xD6, 0x6A, 0x5B, 0x4A, 0x36, 0x92, 0x22, 0x22, 0x00, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x00,/*紊2860*/},\n        {\n\n                0x00, 0xF9, 0x02, 0x00, 0xF0, 0x12, 0x12, 0xF2, 0x02, 0x02, 0xFE, 0x00, 0x0F, 0x00, 0x00, 0x01,\n                0x01, 0x01, 0x01, 0x08, 0x08, 0x0F,/*问2861*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x44, 0x52, 0xD9, 0x14, 0x50, 0x59, 0xD2, 0x03, 0x01, 0x03, 0x00, 0x05,\n                0x0A, 0x0F, 0x00, 0x05, 0x0A, 0x0F,/*嗡2862*/},\n        {\n\n                0x04, 0x44, 0x52, 0x59, 0xD4, 0x10, 0x50, 0x59, 0x52, 0xC4, 0x04, 0x00, 0x05, 0x02, 0x08, 0x0F,\n                0x00, 0x05, 0x02, 0x08, 0x0F, 0x00,/*翁2863*/},\n        {\n\n                0x44, 0x44, 0xD2, 0x59, 0x54, 0x52, 0x50, 0x59, 0x52, 0x64, 0x44, 0x00, 0x0C, 0x0B, 0x09, 0x0B,\n                0x05, 0x01, 0x07, 0x08, 0x08, 0x0E,/*瓮2864*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x11, 0xF2, 0x00, 0x24, 0x44, 0xFF, 0x04, 0x00, 0x08, 0x0F, 0x08, 0x04,\n                0x03, 0x04, 0x08, 0x0A, 0x0B, 0x08,/*挝2865*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xEF, 0x29, 0xF9, 0x29, 0xEF, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x01, 0x00, 0x09, 0x0F,/*蜗2866*/},\n        {\n\n                0x22, 0x44, 0xE0, 0x2F, 0x29, 0xA9, 0x79, 0xA9, 0x29, 0x2F, 0xE0, 0x04, 0x02, 0x0F, 0x00, 0x01,\n                0x00, 0x00, 0x00, 0x01, 0x08, 0x0F,/*涡2867*/},\n        {\n\n                0x06, 0x0A, 0x76, 0x52, 0x52, 0xD3, 0x52, 0x52, 0x76, 0x0A, 0x06, 0x00, 0x0F, 0x01, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x09, 0x0F, 0x00,/*窝2868*/},\n        {\n\n                0x10, 0x12, 0x12, 0xFF, 0x91, 0x10, 0xFF, 0x10, 0x90, 0x52, 0x14, 0x02, 0x02, 0x09, 0x0F, 0x00,\n                0x04, 0x02, 0x03, 0x04, 0x08, 0x0E,/*我2869*/},\n        {\n\n                0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x04, 0x52, 0x01, 0xFA, 0x84, 0x88, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x01, 0x01, 0x01, 0x0F, 0x00, 0x00,/*斡2870*/},\n        {\n\n                0xFE, 0x92, 0x92, 0x9E, 0x92, 0xF2, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x0F, 0x08, 0x08, 0x0F, 0x08,\n                0x08, 0x00, 0x0F, 0x00, 0x00, 0x00,/*卧2871*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFF, 0x05, 0x95, 0xD5, 0xB5, 0x95, 0xD7, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x08, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*握2872*/},\n        {\n\n                0x11, 0x22, 0x00, 0x22, 0x22, 0xE2, 0x3E, 0xE1, 0x21, 0x21, 0x20, 0x04, 0x02, 0x09, 0x04, 0x03,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x08,/*沃2873*/},\n        {\n\n                0x00, 0x82, 0x7A, 0x82, 0x02, 0xFE, 0x02, 0x82, 0x7A, 0x82, 0x00, 0x09, 0x08, 0x08, 0x08, 0x09,\n                0x0F, 0x09, 0x08, 0x08, 0x08, 0x09,/*巫2874*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x00, 0x7E, 0x43, 0x42, 0x52, 0x5E, 0xC0, 0x03, 0x01, 0x03, 0x00, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x08, 0x07,/*呜2875*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x7E, 0x43, 0x42, 0x52, 0x5E, 0xC0, 0x00, 0x0F, 0x04, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x08, 0x07,/*钨2876*/},\n        {\n\n                0x00, 0x00, 0x7E, 0x42, 0x43, 0x42, 0x42, 0x52, 0x5E, 0x40, 0xC0, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0A, 0x08, 0x07,/*乌2877*/},\n        {\n\n                0x11, 0x22, 0x10, 0x12, 0xD2, 0xB2, 0x92, 0x92, 0x92, 0x92, 0x10, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x07, 0x00,/*污2878*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x82, 0x7A, 0x82, 0xFE, 0x82, 0x7A, 0x82, 0x00, 0x00, 0x0F, 0x05, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x09,/*诬2879*/},\n        {\n\n                0x00, 0xFF, 0x05, 0x95, 0xD5, 0xB5, 0x95, 0x95, 0xD5, 0x95, 0x07, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*屋2880*/},\n        {\n\n                0x20, 0x22, 0x22, 0x22, 0xE2, 0x3E, 0xE2, 0x22, 0x22, 0x22, 0x20, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*无2881*/},\n        {\n\n                0x82, 0x92, 0x92, 0x97, 0x92, 0xF2, 0x92, 0x97, 0x92, 0x92, 0x82, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0C,/*芜2882*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x21, 0xA5, 0xBD, 0xA7, 0xA5, 0xBD, 0x21, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*梧2883*/},\n        {\n\n                0x40, 0x49, 0x49, 0x79, 0x4F, 0x49, 0x49, 0x49, 0x79, 0x41, 0x40, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x00,/*吾2884*/},\n        {\n\n                0x80, 0xA0, 0xAF, 0xA9, 0xA9, 0xE9, 0xA9, 0xA9, 0xAF, 0xA0, 0x80, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x04, 0x08, 0x08,/*吴2885*/},\n        {\n\n                0x10, 0xF0, 0x1F, 0x11, 0xF1, 0x1F, 0x11, 0x11, 0xFF, 0x10, 0x10, 0x00, 0x09, 0x05, 0x03, 0x01,\n                0x09, 0x09, 0x09, 0x07, 0x01, 0x00,/*毋2886*/},\n        {\n\n                0x10, 0x92, 0x12, 0xF2, 0x92, 0x92, 0x10, 0xFF, 0x10, 0x12, 0x14, 0x08, 0x0F, 0x08, 0x07, 0x04,\n                0x04, 0x00, 0x00, 0x03, 0x04, 0x0E,/*武2887*/},\n        {\n\n                0x02, 0x22, 0x22, 0xE2, 0x3E, 0x22, 0x22, 0x22, 0xE2, 0x02, 0x00, 0x08, 0x08, 0x0E, 0x09, 0x08,\n                0x08, 0x08, 0x08, 0x0F, 0x08, 0x08,/*五2888*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x21, 0xA5, 0xBD, 0xA7, 0xA5, 0xA5, 0xBD, 0x21, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*捂2889*/},\n        {\n\n                0x90, 0x88, 0x87, 0x84, 0x84, 0xFC, 0x84, 0x84, 0x84, 0x84, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*午2890*/},\n        {\n\n                0x24, 0xAA, 0xFF, 0xAA, 0xBE, 0x2A, 0xBE, 0xAA, 0xFE, 0xAA, 0x22, 0x09, 0x0A, 0x04, 0x02, 0x01,\n                0x06, 0x04, 0x04, 0x0F, 0x04, 0x04,/*舞2891*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0x22, 0x22, 0xFE, 0x22, 0x22, 0xE2, 0x00, 0x00, 0x0F, 0x00, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*伍2892*/},\n        {\n\n                0x10, 0xFC, 0x4B, 0xC4, 0x7B, 0x4A, 0x6A, 0x4A, 0x4A, 0xFA, 0x42, 0x00, 0x0F, 0x00, 0x03, 0x02,\n                0x02, 0x03, 0x0A, 0x0A, 0x07, 0x02,/*侮2893*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0x7E, 0x43, 0x42, 0x52, 0x5E, 0xC0, 0x02, 0x02, 0x01, 0x01, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x08, 0x07,/*坞2894*/},\n        {\n\n                0x00, 0xF8, 0x08, 0x08, 0x08, 0x08, 0xFF, 0x08, 0x89, 0x6A, 0x08, 0x08, 0x07, 0x00, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x0F,/*戊2895*/},\n        {\n\n                0x0C, 0x25, 0x9D, 0xB5, 0x55, 0x5F, 0x55, 0xB5, 0x9D, 0x05, 0x0C, 0x01, 0x09, 0x0A, 0x06, 0x03,\n                0x02, 0x02, 0x0A, 0x0E, 0x01, 0x01,/*雾2896*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x21, 0xA5, 0xBD, 0xA7, 0xA5, 0xA5, 0xBD, 0x21, 0x07, 0x02, 0x07, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*晤2897*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x08, 0xC7, 0x3C, 0x84, 0x7C, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x08, 0x08, 0x07,/*物2898*/},\n        {\n\n                0x20, 0x18, 0x87, 0x64, 0x1C, 0x04, 0x84, 0x7C, 0x04, 0x04, 0xFC, 0x02, 0x01, 0x00, 0x08, 0x04,\n                0x02, 0x01, 0x08, 0x08, 0x08, 0x07,/*勿2899*/},\n        {\n\n                0x20, 0xA4, 0x92, 0x97, 0xEA, 0x8A, 0x8A, 0x96, 0x92, 0x20, 0x20, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x08, 0x08, 0x07, 0x00, 0x00,/*务2900*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x21, 0xA5, 0xBD, 0xA7, 0xA5, 0xBD, 0x21, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*悟2901*/},\n        {\n\n                0x11, 0xF2, 0x80, 0xA0, 0xAF, 0xA9, 0xE9, 0xA9, 0xAF, 0xA0, 0x80, 0x00, 0x07, 0x02, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*误2902*/},\n        {\n\n                0x10, 0x12, 0xD2, 0x5F, 0x52, 0x52, 0x52, 0x5F, 0xD2, 0x12, 0x10, 0x00, 0x00, 0x0F, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0F, 0x00, 0x00,/*昔2903*/},\n        {\n\n                0xFF, 0x01, 0x3D, 0xE7, 0x3D, 0x01, 0x00, 0xFF, 0x11, 0x11, 0xDF, 0x09, 0x05, 0x01, 0x05, 0x09,\n                0x01, 0x04, 0x08, 0x01, 0x05, 0x09,/*熙2904*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x11, 0x00, 0x00, 0x0F, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x0F, 0x00, 0x00,/*析2905*/},\n        {\n\n                0x01, 0xF9, 0x09, 0x89, 0x7F, 0x09, 0x7F, 0x89, 0x89, 0xF9, 0x01, 0x00, 0x0F, 0x05, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*西2906*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0x22, 0xF0, 0x12, 0xFE, 0x12, 0xFE, 0x92, 0xF2, 0x00, 0x07, 0x02, 0x02, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x04, 0x0F,/*硒2907*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0x22, 0xE2, 0x20, 0x18, 0x67, 0x84, 0x64, 0x1C, 0x00, 0x07, 0x02, 0x02, 0x07,\n                0x08, 0x04, 0x02, 0x01, 0x00, 0x00,/*矽2908*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x88, 0x68, 0xFF, 0x48, 0xFE, 0x12, 0xF2, 0x11, 0x07, 0x02, 0x07, 0x00, 0x00,\n                0x0F, 0x04, 0x03, 0x00, 0x0F, 0x00,/*晰2909*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x02, 0xEA, 0xAA, 0xAF, 0xAA, 0xAA, 0xEA, 0x02, 0x03, 0x01, 0x03, 0x02, 0x0E,\n                0x0B, 0x0A, 0x0A, 0x0B, 0x0E, 0x02,/*嘻2910*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x02, 0xFE, 0x82, 0x02, 0x32, 0x2E, 0xE0, 0x03, 0x01, 0x03, 0x08, 0x06,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*吸2911*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x80, 0x5F, 0xF5, 0x55, 0xD5, 0x5F, 0xC0, 0x00, 0x0F, 0x04, 0x00, 0x02,\n                0x09, 0x04, 0x02, 0x09, 0x08, 0x07,/*锡2912*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0xF2, 0x12, 0xFE, 0x12, 0xFE, 0x92, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x04, 0x0F,/*牺2913*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0xD5, 0xB2, 0xDA, 0x92, 0x95, 0x90, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x00, 0x0F, 0x00, 0x04, 0x07,/*稀2914*/},\n        {\n\n                0x00, 0xFE, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xAA, 0xFE, 0x00, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*息2915*/},\n        {\n\n                0x20, 0xA9, 0xE9, 0xBA, 0xAA, 0xE4, 0xA4, 0xAA, 0xAA, 0xB1, 0x20, 0x01, 0x00, 0x07, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x04, 0x07, 0x00,/*希2916*/},\n        {\n\n                0x90, 0x92, 0x56, 0x3A, 0x12, 0x7E, 0x11, 0x39, 0x55, 0x91, 0x90, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*悉2917*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x4A, 0xA6, 0x12, 0xCF, 0x12, 0xA6, 0x4A, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x02, 0x09, 0x0F, 0x01, 0x02, 0x04,/*膝2918*/},\n        {\n\n                0x40, 0x20, 0x10, 0x2C, 0xC7, 0x04, 0x04, 0x84, 0x44, 0x34, 0x0C, 0x08, 0x08, 0x08, 0x04, 0x04,\n                0x03, 0x01, 0x00, 0x00, 0x00, 0x00,/*夕2919*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0xD4, 0x5F, 0x54, 0x54, 0x5F, 0xD4, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*惜2920*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xFE, 0xAA, 0xAB, 0xAA, 0xFE, 0x00, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x02, 0x0C, 0x09, 0x0C, 0x02, 0x04,/*熄2921*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x90, 0xD5, 0xB2, 0xDA, 0x92, 0x95, 0x90, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x07, 0x00, 0x0F, 0x00, 0x04, 0x07,/*烯2922*/},\n        {\n\n                0x22, 0x44, 0x00, 0x82, 0xD6, 0xAA, 0xA6, 0x8A, 0xD1, 0x89, 0x01, 0x04, 0x02, 0x00, 0x0A, 0x0A,\n                0x06, 0x03, 0x06, 0x0A, 0x0B, 0x02,/*溪2923*/},\n        {\n\n                0x10, 0x21, 0x02, 0x40, 0x20, 0x18, 0x27, 0x44, 0x84, 0x64, 0x1C, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x08, 0x04, 0x02, 0x01, 0x00, 0x00,/*汐2924*/},\n        {\n\n                0x00, 0xFF, 0x05, 0x2D, 0xD5, 0x85, 0xDD, 0x85, 0x95, 0xAD, 0x07, 0x08, 0x07, 0x02, 0x03, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*犀2925*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0x80, 0xBE, 0xEB, 0xBE, 0xD0, 0x0F, 0xF8, 0x08, 0x00, 0x0F, 0x00, 0x08, 0x07,\n                0x0A, 0x0E, 0x05, 0x02, 0x05, 0x08,/*檄2926*/},\n        {\n\n                0xA2, 0x92, 0x8A, 0xA7, 0xA2, 0xD2, 0x9E, 0xAA, 0xA7, 0xA2, 0xB2, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*袭2927*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0x8A, 0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0x8A, 0x0A, 0x04, 0x03, 0x00, 0x07, 0x00,\n                0x00, 0x0F, 0x00, 0x04, 0x07, 0x00,/*席2928*/},\n        {\n\n                0x00, 0x02, 0x0A, 0x12, 0x22, 0x82, 0x82, 0x42, 0x02, 0xFE, 0x00, 0x02, 0x02, 0x02, 0x01, 0x01,\n                0x00, 0x08, 0x08, 0x08, 0x07, 0x00,/*习2929*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFE, 0xAA, 0xAB, 0xAA, 0xFE, 0x00, 0x08, 0x05, 0x02, 0x0D, 0x04,\n                0x02, 0x0C, 0x09, 0x0C, 0x02, 0x04,/*媳2930*/},\n        {\n\n                0x02, 0xEA, 0xAA, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0xAA, 0xEA, 0x02, 0x02, 0x0E, 0x0B, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0B, 0x0E, 0x02,/*喜2931*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x50, 0x4E, 0xC8, 0x7F, 0xC8, 0x48, 0x40, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*铣2932*/},\n        {\n\n                0x22, 0x44, 0x00, 0x50, 0xCE, 0x48, 0x7F, 0xC8, 0x48, 0x48, 0x40, 0x04, 0x02, 0x08, 0x04, 0x03,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*洗2933*/},\n        {\n\n                0x00, 0x82, 0x92, 0xDA, 0xD6, 0xB2, 0xB1, 0x91, 0x89, 0xC1, 0x80, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x09,/*系2934*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x04, 0xFA, 0xA8, 0xAF, 0xA8, 0xFA, 0x04, 0x0F, 0x02, 0x02, 0x01, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*隙2935*/},\n        {\n\n                0x14, 0x64, 0x84, 0x64, 0x1C, 0x10, 0x10, 0xFF, 0x08, 0xE9, 0x0A, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x08, 0x04, 0x02, 0x03, 0x04, 0x0E,/*戏2936*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x22, 0xFE, 0x04, 0x04, 0x02, 0x02, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*细2937*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x86, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0x86, 0x0F, 0x04, 0x0F, 0x00, 0x00,\n                0x0E, 0x0A, 0x0B, 0x0A, 0x0E, 0x00,/*瞎2938*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x7A, 0x02, 0x02, 0xFE, 0x22, 0x42, 0x82, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*虾2939*/},\n        {\n\n                0x00, 0xFF, 0x01, 0xFD, 0x25, 0x25, 0xFD, 0x25, 0x25, 0xFD, 0x01, 0x00, 0x0F, 0x08, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x08,/*匣2940*/},\n        {\n\n                0x0C, 0xF5, 0x5D, 0x55, 0x75, 0x0F, 0x55, 0x55, 0x5D, 0x75, 0x0C, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x08, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*霞2941*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x86, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0x86, 0x02, 0x02, 0x0F, 0x01, 0x00,\n                0x0E, 0x0A, 0x0B, 0x0A, 0x0E, 0x00,/*辖2942*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0xFF, 0x49, 0x4F, 0x00, 0xC9, 0x49, 0xCF, 0x07, 0x02, 0x07, 0x00, 0x0F,\n                0x02, 0x02, 0x08, 0x05, 0x02, 0x0D,/*暇2943*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0x94, 0xA4, 0xFF, 0xA4, 0x94, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x08, 0x04, 0x02, 0x01, 0x06, 0x08,/*峡2944*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x94, 0xA4, 0x84, 0xFF, 0x84, 0xA4, 0x94, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*侠2945*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x94, 0xA4, 0x84, 0xFF, 0x84, 0xA4, 0x94, 0x08, 0x08, 0x07, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*狭2946*/},\n        {\n\n                0x02, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x12, 0x22, 0x42, 0x82, 0x02, 0x00, 0x00, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x01, 0x00,/*下2947*/},\n        {\n\n                0x00, 0xFF, 0x05, 0xF5, 0x55, 0x5D, 0x55, 0x55, 0x55, 0xF5, 0x05, 0x08, 0x07, 0x0A, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x08,/*厦2948*/},\n        {\n\n                0x01, 0x7D, 0x55, 0xD5, 0x55, 0x57, 0x55, 0x55, 0x55, 0x7D, 0x01, 0x08, 0x0A, 0x09, 0x0B, 0x05,\n                0x05, 0x05, 0x05, 0x0B, 0x08, 0x08,/*夏2949*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x02, 0x02, 0x02, 0xFE, 0x22, 0x42, 0x82, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*吓2950*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xFE, 0x12, 0xF2, 0x11, 0x08, 0xE7, 0x04, 0x1C, 0x08, 0x0F, 0x04, 0x03, 0x00,\n                0x07, 0x08, 0x06, 0x01, 0x06, 0x08,/*掀2951*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x12, 0xF1, 0x10, 0x0F, 0xC4, 0x1C, 0x00, 0x07, 0x02, 0x08, 0x07,\n                0x00, 0x07, 0x08, 0x06, 0x01, 0x0E,/*锨2952*/},\n        {\n\n                0x40, 0x50, 0x4E, 0x48, 0xC8, 0x7F, 0x48, 0xC8, 0x48, 0x48, 0x40, 0x00, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*先2953*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xF8, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x0F, 0x00, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*仙2954*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x01, 0x01, 0x0F, 0x01, 0x01,/*鲜2955*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*纤2956*/},\n        {\n\n                0x00, 0xFC, 0x04, 0xD4, 0x54, 0x54, 0xD4, 0x04, 0xFF, 0x04, 0xE5, 0x08, 0x07, 0x00, 0x03, 0x02,\n                0x02, 0x0B, 0x04, 0x03, 0x05, 0x0E,/*咸2957*/},\n        {\n\n                0x0E, 0xC0, 0x40, 0x5F, 0x40, 0xD1, 0x4B, 0x45, 0x45, 0xCB, 0x10, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贤2958*/},\n        {\n\n                0x24, 0xF2, 0x09, 0x98, 0xF7, 0x94, 0x94, 0x00, 0x12, 0xF2, 0x12, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x02, 0x00, 0x08, 0x0F, 0x00,/*衔2959*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0x64, 0x55, 0xCE, 0x44, 0x24, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x06, 0x05, 0x04, 0x06, 0x0C,/*舷2960*/},\n        {\n\n                0xF9, 0x02, 0x10, 0x91, 0x51, 0xFD, 0x51, 0x91, 0x11, 0x01, 0xFF, 0x0F, 0x00, 0x01, 0x00, 0x00,\n                0x07, 0x00, 0x00, 0x01, 0x08, 0x0F,/*闲2961*/},\n        {\n\n                0x11, 0x22, 0x00, 0x72, 0xCE, 0x00, 0xF2, 0x02, 0xFE, 0x11, 0x11, 0x04, 0x02, 0x0A, 0x04, 0x0B,\n                0x08, 0x09, 0x09, 0x09, 0x09, 0x09,/*涎2962*/},\n        {\n\n                0xF2, 0x92, 0x9E, 0x00, 0x44, 0x64, 0x55, 0xCE, 0x44, 0x24, 0x04, 0x08, 0x08, 0x07, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*弦2963*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x55, 0xFE, 0x54, 0xFE, 0x55, 0xF4, 0x40, 0x08, 0x05, 0x02, 0x0D, 0x03,\n                0x0F, 0x01, 0x0F, 0x03, 0x05, 0x08,/*嫌2964*/},\n        {\n\n                0x80, 0x3E, 0x2A, 0xEA, 0x2A, 0x2A, 0x2A, 0xEA, 0x2A, 0x3E, 0x80, 0x08, 0x09, 0x0A, 0x0F, 0x08,\n                0x08, 0x08, 0x0F, 0x0A, 0x09, 0x08,/*显2965*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x0F, 0x02, 0x02, 0x01, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*险2966*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x00, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*现2967*/},\n        {\n\n                0xFA, 0x0A, 0x5A, 0xEF, 0x5A, 0xFA, 0x02, 0x10, 0xFF, 0x12, 0x14, 0x0F, 0x01, 0x01, 0x07, 0x09,\n                0x0F, 0x08, 0x07, 0x00, 0x07, 0x08,/*献2968*/},\n        {\n\n                0x40, 0x40, 0x7F, 0x55, 0xD5, 0x55, 0x55, 0x55, 0x7F, 0x40, 0x40, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x05, 0x06, 0x0C, 0x00,/*县2969*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x80, 0xBE, 0x2A, 0xEB, 0xAA, 0x3E, 0x80, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x03, 0x08, 0x0F, 0x00, 0x03, 0x04,/*腺2970*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x00, 0xE4, 0x93, 0x02, 0x8A, 0xA6, 0xE0, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*馅2971*/},\n        {\n\n                0xA2, 0x2A, 0x2A, 0x2B, 0xEA, 0xBE, 0xAA, 0xAB, 0xAA, 0xAA, 0xA2, 0x08, 0x05, 0x00, 0x09, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x0A, 0x09,/*羡2972*/},\n        {\n\n                0x86, 0xA2, 0x9A, 0x92, 0x92, 0xFB, 0x92, 0x92, 0x92, 0x92, 0x86, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*宪2973*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0xE4, 0x93, 0x02, 0x8A, 0xA6, 0xE0, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*陷2974*/},\n        {\n\n                0xFF, 0x01, 0x19, 0xE7, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*限2975*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0x48, 0x48, 0xFF, 0x24, 0xA5, 0x26, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x08, 0x04, 0x03, 0x05, 0x08, 0x0E,/*线2976*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xFE, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*相2977*/},\n        {\n\n                0x00, 0xFF, 0x11, 0x91, 0xFD, 0x91, 0x11, 0xFD, 0xA5, 0xA5, 0xFD, 0x08, 0x07, 0x01, 0x00, 0x0F,\n                0x00, 0x01, 0x0F, 0x04, 0x04, 0x0F,/*厢2978*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xBA, 0xAA, 0xFA, 0x83, 0xFA, 0xAA, 0xBA, 0x00, 0x0F, 0x04, 0x00, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*镶2979*/},\n        {\n\n                0x48, 0x48, 0xAA, 0x9A, 0x8A, 0xFE, 0x89, 0x99, 0xA9, 0x48, 0x48, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*香2980*/},\n        {\n\n                0x24, 0xA3, 0xFA, 0xA6, 0x22, 0xF4, 0x53, 0x52, 0x56, 0x52, 0xF2, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*箱2981*/},\n        {\n\n                0x02, 0xBA, 0xAA, 0xEA, 0xBA, 0x83, 0xBA, 0xEA, 0xAA, 0xBA, 0x02, 0x0A, 0x0A, 0x06, 0x0F, 0x0A,\n                0x02, 0x02, 0x07, 0x0A, 0x0A, 0x0A,/*襄2982*/},\n        {\n\n                0x11, 0x22, 0x88, 0x48, 0xFF, 0x28, 0x48, 0xFE, 0x92, 0x92, 0xFE, 0x04, 0x02, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*湘2983*/},\n        {\n\n                0x00, 0x98, 0xD4, 0xD2, 0xB1, 0xB0, 0x90, 0x88, 0x84, 0x80, 0x60, 0x08, 0x08, 0x08, 0x08, 0x04,\n                0x04, 0x02, 0x02, 0x01, 0x00, 0x00,/*乡2984*/},\n        {\n\n                0x89, 0xAA, 0xF8, 0xAA, 0x01, 0x12, 0xA2, 0xFE, 0x10, 0xA2, 0xFE, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x01, 0x08, 0x0F, 0x01, 0x08, 0x0F,/*翔2985*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*祥2986*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0x24, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x24, 0x00, 0x07, 0x02, 0x01, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*详2987*/},\n        {\n\n                0x44, 0x24, 0x14, 0xFF, 0x14, 0x24, 0xFE, 0xAA, 0xAA, 0xAA, 0xFE, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*想2988*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFC, 0x04, 0xE6, 0x25, 0xE4, 0x04, 0xFC, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*响2989*/},\n        {\n\n                0x02, 0xBA, 0xAA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0x3A, 0x02, 0x02, 0x02, 0x02, 0x02, 0x0A,\n                0x0A, 0x0E, 0x03, 0x02, 0x02, 0x02,/*享2990*/},\n        {\n\n                0x02, 0xFE, 0x02, 0x00, 0xF9, 0x09, 0x0D, 0xEB, 0x09, 0x09, 0xF9, 0x02, 0x01, 0x01, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*项2991*/},\n        {\n\n                0x90, 0x54, 0xF4, 0x5F, 0x54, 0x54, 0x54, 0x5F, 0xF4, 0x54, 0x90, 0x00, 0x00, 0x07, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0C, 0x00,/*巷2992*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xBC, 0xAB, 0x6A, 0xBA, 0x2A, 0xAE, 0x78, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x0A, 0x05, 0x0A, 0x0F, 0x02, 0x04,/*橡2993*/},\n        {\n\n                0x10, 0xFC, 0x0B, 0xBC, 0xAB, 0x6A, 0xBA, 0x2A, 0x2E, 0xB8, 0x00, 0x00, 0x0F, 0x00, 0x0A, 0x0A,\n                0x05, 0x0A, 0x0F, 0x01, 0x02, 0x04,/*像2994*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xE6, 0x25, 0x24, 0x24, 0xE4, 0x04, 0x04, 0xFC, 0x0F, 0x00, 0x00, 0x03, 0x02,\n                0x02, 0x02, 0x03, 0x08, 0x08, 0x0F,/*向2995*/},\n        {\n\n                0x08, 0xBC, 0xAA, 0x6B, 0x6A, 0xBA, 0x2A, 0x2E, 0xA8, 0x78, 0x00, 0x08, 0x0A, 0x0A, 0x05, 0x05,\n                0x0A, 0x0F, 0x01, 0x02, 0x04, 0x04,/*象2996*/},\n        {\n\n                0x22, 0xAA, 0xAA, 0xAF, 0xAA, 0xFE, 0xAA, 0xAF, 0xAA, 0xFA, 0x22, 0x08, 0x06, 0x00, 0x04, 0x02,\n                0x0F, 0x02, 0x04, 0x00, 0x0E, 0x00,/*萧2997*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x02, 0xF4, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x00, 0x0F, 0x04, 0x0F, 0x00,\n                0x0F, 0x01, 0x01, 0x01, 0x09, 0x0F,/*硝2998*/},\n        {\n\n                0x0C, 0xE5, 0xAD, 0xB5, 0xA5, 0xBF, 0xA5, 0xB5, 0xAD, 0xE5, 0x0C, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*霄2999*/},\n        {\n\n                0xF2, 0x54, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x00, 0xFC, 0x00, 0xFF, 0x0F, 0x01, 0x01, 0x01, 0x01,\n                0x09, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*削3000*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0xAA, 0x6A, 0x2F, 0xBA, 0xAA, 0x6C, 0x0A, 0x03, 0x01, 0x03, 0x01, 0x00,\n                0x01, 0x09, 0x0F, 0x01, 0x01, 0x01,/*哮3001*/},\n        {\n\n                0x04, 0x77, 0x15, 0x95, 0x97, 0x5C, 0x97, 0x95, 0x95, 0x77, 0x04, 0x01, 0x0F, 0x0B, 0x0A, 0x0E,\n                0x00, 0x0E, 0x0A, 0x0A, 0x0F, 0x01,/*嚣3002*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xF2, 0x54, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x01, 0x09, 0x0F,/*销3003*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xF2, 0x54, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x01, 0x09, 0x0F,/*消3004*/},\n        {\n\n                0x06, 0xE2, 0xAA, 0xB2, 0xA2, 0xBB, 0xA2, 0xB2, 0xAA, 0xE2, 0x06, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*宵3005*/},\n        {\n\n                0x11, 0x22, 0x80, 0x48, 0xED, 0xBA, 0xAE, 0xAA, 0xAA, 0xED, 0x08, 0x04, 0x02, 0x00, 0x00, 0x0F,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*淆3006*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x84, 0xA4, 0xA4, 0xAF, 0x92, 0xAA, 0xA6, 0xB2, 0x07, 0x02, 0x07, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0C,/*晓3007*/},\n        {\n\n                0x00, 0xC0, 0x30, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x10, 0x60, 0x80, 0x01, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x01,/*小3008*/},\n        {\n\n                0x08, 0x2A, 0xAA, 0x6A, 0x2F, 0x3A, 0xAA, 0x6C, 0x2A, 0x09, 0x08, 0x02, 0x01, 0x01, 0x01, 0x09,\n                0x09, 0x0F, 0x01, 0x01, 0x01, 0x01,/*孝3009*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x44, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*校3010*/},\n        {\n\n                0x00, 0xF2, 0x54, 0x50, 0x50, 0x5F, 0x50, 0x50, 0x54, 0xF2, 0x00, 0x00, 0x0F, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x0F, 0x00,/*肖3011*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0xAA, 0x2A, 0xFF, 0x2A, 0x2A, 0xBE, 0x08, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x01, 0x0F, 0x01, 0x02, 0x0F, 0x00,/*啸3012*/},\n        {\n\n                0x88, 0x84, 0xA3, 0xA6, 0xAA, 0xE2, 0x94, 0x93, 0x96, 0x8A, 0x82, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*笑3013*/},\n        {\n\n                0x44, 0x34, 0x85, 0x06, 0x94, 0x24, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x04, 0x08, 0x04, 0x03, 0x04, 0x08,/*效3014*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0x2A, 0x7F, 0x2A, 0xC2, 0x3E, 0x42, 0x7E, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*楔3015*/},\n        {\n\n                0x40, 0x7E, 0x40, 0x3F, 0x24, 0x24, 0x00, 0x3F, 0x48, 0x44, 0x72, 0x08, 0x08, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x08, 0x08,/*些3016*/},\n        {\n\n                0x9F, 0x75, 0xD5, 0x55, 0x5F, 0xC0, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x06, 0x05, 0x04, 0x0D, 0x08,\n                0x07, 0x08, 0x06, 0x01, 0x06, 0x08,/*歇3017*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x9F, 0x75, 0xD5, 0x5F, 0xC0, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x06, 0x05, 0x04, 0x09, 0x0F,/*蝎3018*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x02, 0x02, 0x0F, 0x02, 0x0A,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*鞋3019*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x88, 0x48, 0xFF, 0x08, 0x08, 0xF8, 0x40, 0x80, 0x00, 0x0F, 0x00, 0x08, 0x06,\n                0x01, 0x08, 0x08, 0x07, 0x00, 0x01,/*协3020*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x94, 0xA4, 0x84, 0xFF, 0x84, 0xA4, 0x94, 0x08, 0x0F, 0x00, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*挟3021*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x84, 0xFE, 0xAB, 0xAA, 0xFF, 0xAA, 0xAA, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x0A, 0x0B, 0x06,/*携3022*/},\n        {\n\n                0x00, 0x32, 0xAA, 0x62, 0xFE, 0x22, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x04, 0x02, 0x01, 0x08, 0x0F,\n                0x00, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邪3023*/},\n        {\n\n                0x08, 0x44, 0x4A, 0xF9, 0x4A, 0x44, 0x92, 0xA4, 0x80, 0xFF, 0x40, 0x02, 0x01, 0x08, 0x0F, 0x01,\n                0x02, 0x00, 0x00, 0x00, 0x0F, 0x00,/*斜3024*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x40, 0x24, 0xFF, 0x04, 0xFC, 0x20, 0xC0, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x03, 0x08, 0x08, 0x07, 0x00, 0x00,/*胁3025*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x00, 0xDF, 0x52, 0x4A, 0x60, 0x4F, 0x52, 0xD9, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*谐3026*/},\n        {\n\n                0x03, 0x61, 0x5F, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0xC9, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x02, 0x0A, 0x0A, 0x08, 0x07, 0x00,/*写3027*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xF4, 0x44, 0xF4, 0x44, 0xFF, 0x84, 0x65, 0x00, 0x00, 0x0F, 0x04, 0x03,\n                0x00, 0x0B, 0x04, 0x03, 0x05, 0x0E,/*械3028*/},\n        {\n\n                0x14, 0xD3, 0x12, 0xFE, 0x92, 0x92, 0x00, 0xFE, 0x02, 0x02, 0xFE, 0x04, 0x07, 0x04, 0x03, 0x02,\n                0x02, 0x00, 0x0F, 0x00, 0x02, 0x03,/*卸3029*/},\n        {\n\n                0x42, 0xBD, 0x95, 0xBD, 0x97, 0xFC, 0x89, 0x97, 0xF9, 0x95, 0x17, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*蟹3030*/},\n        {\n\n                0x30, 0xFF, 0x08, 0xF4, 0x53, 0xFA, 0x56, 0xF9, 0x27, 0xF9, 0x2F, 0x00, 0x0F, 0x08, 0x07, 0x01,\n                0x07, 0x09, 0x0F, 0x01, 0x0F, 0x01,/*懈3031*/},\n        {\n\n                0x11, 0x22, 0x10, 0xFE, 0x10, 0x10, 0xFF, 0x10, 0x10, 0xFF, 0x10, 0x04, 0x02, 0x00, 0x0F, 0x08,\n                0x08, 0x09, 0x09, 0x09, 0x09, 0x08,/*泄3032*/},\n        {\n\n                0x11, 0x22, 0x00, 0x03, 0x61, 0x5F, 0x49, 0x49, 0x49, 0x49, 0xCB, 0x04, 0x02, 0x01, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0A, 0x08, 0x07,/*泻3033*/},\n        {\n\n                0x11, 0xF2, 0x80, 0xFE, 0xAB, 0xAA, 0xFE, 0x40, 0x88, 0xFF, 0x08, 0x00, 0x0F, 0x04, 0x02, 0x01,\n                0x08, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*谢3034*/},\n        {\n\n                0x00, 0xFF, 0x05, 0xED, 0xB5, 0xA5, 0xBD, 0xA5, 0xA5, 0xB5, 0xEF, 0x08, 0x07, 0x00, 0x0F, 0x02,\n                0x02, 0x02, 0x02, 0x02, 0x0A, 0x0F,/*屑3035*/},\n        {\n\n                0x42, 0x52, 0x77, 0xDA, 0x72, 0x52, 0x42, 0xF2, 0x97, 0x8A, 0x8A, 0x08, 0x05, 0x09, 0x0F, 0x01,\n                0x05, 0x08, 0x07, 0x00, 0x0F, 0x00,/*薪3036*/},\n        {\n\n                0x04, 0x84, 0x04, 0xCF, 0x04, 0x24, 0xC4, 0x0F, 0x04, 0x84, 0x04, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x08, 0x08, 0x0E, 0x00, 0x07,/*芯3037*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x40, 0x54, 0x65, 0xC6, 0x64, 0x54, 0x40, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x00,/*锌3038*/},\n        {\n\n                0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x00, 0x08, 0x06, 0x01, 0x06, 0x08,/*欣3039*/},\n        {\n\n                0x20, 0x24, 0x2C, 0x34, 0x25, 0xE6, 0x24, 0x34, 0x2C, 0x24, 0x20, 0x00, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x00,/*辛3040*/},\n        {\n\n                0x20, 0xAA, 0xB2, 0xE3, 0xB2, 0xAA, 0x00, 0xFE, 0x12, 0xF2, 0x11, 0x04, 0x02, 0x08, 0x0F, 0x00,\n                0x0A, 0x04, 0x03, 0x00, 0x0F, 0x00,/*新3041*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x00, 0x00,/*忻3042*/},\n        {\n\n                0x00, 0xC0, 0x00, 0xF0, 0x02, 0x04, 0x18, 0x00, 0x00, 0x20, 0xC0, 0x02, 0x01, 0x00, 0x07, 0x08,\n                0x08, 0x08, 0x08, 0x0E, 0x00, 0x01,/*心3043*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x04, 0x54, 0x54, 0x55, 0x56, 0x54, 0x54, 0x04, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*信3044*/},\n        {\n\n                0x00, 0xF8, 0x0C, 0xFB, 0x08, 0xF8, 0x92, 0x94, 0xFF, 0x94, 0x92, 0x04, 0x07, 0x04, 0x07, 0x02,\n                0x03, 0x02, 0x00, 0x0F, 0x00, 0x00,/*衅3045*/},\n        {\n\n                0x00, 0xDF, 0x95, 0x95, 0x95, 0xF5, 0x95, 0x95, 0x95, 0x9F, 0x00, 0x09, 0x08, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x08, 0x08,/*星3046*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x00, 0xDF, 0x95, 0xF5, 0x95, 0x9F, 0x00, 0x08, 0x07, 0x08, 0x0F, 0x09,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*腥3047*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x00, 0xDF, 0x95, 0xF5, 0x95, 0x9F, 0x00, 0x01, 0x08, 0x08, 0x07, 0x09,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*猩3048*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0xDF, 0x95, 0xF5, 0x95, 0x9F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*惺3049*/},\n        {\n\n                0x40, 0x42, 0x4C, 0x40, 0x41, 0x46, 0x40, 0x50, 0x4C, 0x43, 0x40, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x01, 0x02, 0x04, 0x08,/*兴3050*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x01, 0x08, 0x08, 0x0F,/*刑3051*/},\n        {\n\n                0x90, 0x52, 0x3E, 0x12, 0x12, 0x7E, 0x12, 0x00, 0x3E, 0x80, 0xFF, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*型3052*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x00, 0x88, 0x44, 0x23, 0x18, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x00, 0x08, 0x08, 0x04, 0x02, 0x01,/*形3053*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邢3054*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x10, 0x12, 0x12, 0x12, 0xF2, 0x12, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*行3055*/},\n        {\n\n                0xFD, 0xA5, 0x9F, 0xA5, 0xFD, 0x00, 0xDF, 0x95, 0xF5, 0x95, 0x9F, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x01, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*醒3056*/},\n        {\n\n                0x10, 0x94, 0xB4, 0xD4, 0x94, 0x9F, 0x94, 0xD4, 0xB4, 0x94, 0x10, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*幸3057*/},\n        {\n\n                0x44, 0x44, 0xA4, 0x94, 0x8C, 0xFF, 0x8C, 0x94, 0xA4, 0x44, 0x44, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x0F, 0x00, 0x00,/*杏3058*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x20, 0x9C, 0x88, 0xFF, 0x88, 0x88, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*性3059*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0x9C, 0x88, 0xFF, 0x88, 0x88, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*姓3060*/},\n        {\n\n                0x00, 0x7E, 0x42, 0xC2, 0x42, 0x42, 0x42, 0xC2, 0x42, 0x7E, 0x00, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*兄3061*/},\n        {\n\n                0xFC, 0x00, 0x82, 0x44, 0x28, 0x10, 0x2C, 0xC3, 0x00, 0x00, 0xFC, 0x07, 0x04, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*凶3062*/},\n        {\n\n                0xFF, 0x49, 0xFF, 0x08, 0xE4, 0x97, 0x64, 0x94, 0xE4, 0x04, 0xFC, 0x07, 0x08, 0x0F, 0x00, 0x03,\n                0x02, 0x02, 0x02, 0x0B, 0x08, 0x07,/*胸3063*/},\n        {\n\n                0x20, 0x10, 0xEC, 0x07, 0x94, 0x64, 0x94, 0x04, 0xE4, 0x04, 0xFC, 0x00, 0x00, 0x03, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0B, 0x08, 0x07,/*匈3064*/},\n        {\n\n                0x11, 0x22, 0xF8, 0x00, 0x02, 0xCC, 0x30, 0x4C, 0x83, 0x00, 0xF8, 0x04, 0x02, 0x07, 0x04, 0x05,\n                0x04, 0x04, 0x04, 0x05, 0x04, 0x0F,/*汹3065*/},\n        {\n\n                0x84, 0x74, 0x8F, 0x64, 0x04, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x24, 0x00, 0x06, 0x05, 0x04, 0x0E,\n                0x00, 0x0F, 0x09, 0x0F, 0x09, 0x09,/*雄3066*/},\n        {\n\n                0x00, 0xF6, 0x55, 0x54, 0x54, 0xF6, 0x00, 0xE7, 0x8A, 0x49, 0x2C, 0x08, 0x07, 0x01, 0x05, 0x09,\n                0x03, 0x04, 0x09, 0x02, 0x06, 0x0B,/*熊3067*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x08, 0x88, 0x68, 0xFF, 0x68, 0x88, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*休3068*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xF8, 0x10, 0x94, 0x8B, 0x4A, 0x2A, 0x96, 0x10, 0x00, 0x0F, 0x00, 0x03, 0x08,\n                0x0A, 0x0A, 0x09, 0x05, 0x04, 0x02,/*修3069*/},\n        {\n\n                0x22, 0x2A, 0xAA, 0xEB, 0xBA, 0xAE, 0xAA, 0xAB, 0xAA, 0x22, 0x22, 0x04, 0x0A, 0x09, 0x0A, 0x0E,\n                0x0B, 0x0A, 0x0A, 0x0F, 0x08, 0x08,/*羞3070*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x8A, 0x62, 0x5A, 0x46, 0x42, 0x42, 0xC2, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*朽3071*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0xAA, 0xAB, 0xAA, 0xAA, 0xFE, 0x00, 0x03, 0x01, 0x03, 0x0A, 0x0A,\n                0x06, 0x03, 0x06, 0x0B, 0x0A, 0x0A,/*嗅3072*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x28, 0x5A, 0xCA, 0x7E, 0x49, 0xD9, 0x28, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x09, 0x09, 0x07,/*锈3073*/},\n        {\n\n                0x48, 0x48, 0x6A, 0xDA, 0x4A, 0x7E, 0x49, 0xD9, 0x29, 0x48, 0x48, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x08, 0x09, 0x09, 0x07, 0x00,/*秀3074*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xF8, 0x48, 0x48, 0xFF, 0x48, 0x48, 0xF8, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*袖3075*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x28, 0x5A, 0xCA, 0x7E, 0x49, 0xD9, 0x28, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x09, 0x09, 0x07,/*绣3076*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFC, 0x24, 0xA4, 0x3F, 0xD5, 0x55, 0x6C, 0x04, 0x07, 0x02, 0x08, 0x07,\n                0x0A, 0x0F, 0x08, 0x0F, 0x0A, 0x09,/*墟3077*/},\n        {\n\n                0x00, 0xF8, 0x88, 0x88, 0x88, 0x08, 0xFF, 0x08, 0x89, 0x6A, 0x08, 0x08, 0x07, 0x00, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x0F,/*戌3078*/},\n        {\n\n                0x8C, 0xA5, 0xAD, 0xAD, 0x85, 0xBF, 0x85, 0xAD, 0xAD, 0xA5, 0x8C, 0x00, 0x0E, 0x02, 0x02, 0x0E,\n                0x03, 0x0E, 0x02, 0x0A, 0x0E, 0x00,/*需3079*/},\n        {\n\n                0x00, 0xF8, 0x48, 0x48, 0x48, 0x7F, 0xAA, 0xAA, 0xAA, 0x8A, 0xD8, 0x08, 0x07, 0x08, 0x0A, 0x0C,\n                0x0F, 0x08, 0x0F, 0x0C, 0x0A, 0x08,/*虚3080*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFC, 0x24, 0xA4, 0x3F, 0xD5, 0x55, 0x6C, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x0A, 0x0F, 0x08, 0x0F, 0x0A, 0x09,/*嘘3081*/},\n        {\n\n                0x44, 0x22, 0x11, 0x00, 0xF9, 0x09, 0x0D, 0xEB, 0x09, 0x09, 0xF9, 0x04, 0x02, 0x01, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*须3082*/},\n        {\n\n                0x44, 0x22, 0xF1, 0x08, 0x48, 0x54, 0x52, 0xF1, 0x52, 0x54, 0x48, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x03, 0x08, 0x0F, 0x00, 0x01, 0x06,/*徐3083*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x88, 0x87, 0x84, 0xFC, 0x84, 0x84, 0x80, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*许3084*/},\n        {\n\n                0x8A, 0xAA, 0xBA, 0xAF, 0xEA, 0xAE, 0xAA, 0x9F, 0x8A, 0xCA, 0x8A, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x00, 0x01,/*蓄3085*/},\n        {\n\n                0xFD, 0xA5, 0x9F, 0xA5, 0xFD, 0x00, 0xF1, 0x86, 0x78, 0x86, 0xF1, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x07, 0x04, 0x04, 0x04, 0x0F,/*酗3086*/},\n        {\n\n                0x08, 0x44, 0x4A, 0xF9, 0x4A, 0x44, 0x02, 0x7E, 0x82, 0x62, 0x1E, 0x02, 0x01, 0x08, 0x0F, 0x01,\n                0x02, 0x08, 0x06, 0x01, 0x06, 0x08,/*叙3087*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xF8, 0x00, 0xFF, 0x11, 0x11, 0x11, 0xFF, 0x00, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x0C,/*旭3088*/},\n        {\n\n                0x00, 0xFE, 0x82, 0x8A, 0xAA, 0xAA, 0xCB, 0xAA, 0x9A, 0x8A, 0x82, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x08, 0x0F, 0x00, 0x00, 0x02, 0x01,/*序3089*/},\n        {\n\n                0x22, 0xAA, 0xAE, 0xAA, 0xBA, 0xAB, 0xAA, 0xA6, 0xA2, 0xB2, 0x62, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*畜3090*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xF8, 0x08, 0xFC, 0x0B, 0xF8, 0x08, 0xF8, 0x00, 0x00, 0x0F, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*恤3091*/},\n        {\n\n                0x02, 0x2A, 0xAE, 0xD3, 0x92, 0xAE, 0x80, 0x5E, 0x12, 0x12, 0x1E, 0x00, 0x0A, 0x06, 0x02, 0x0B,\n                0x0E, 0x02, 0x02, 0x07, 0x0A, 0x00,/*絮3092*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x11, 0xCD, 0x51, 0x5F, 0x55, 0xD5, 0x13, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x01, 0x01, 0x09, 0x0F, 0x00,/*婿3093*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD4, 0x12, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*绪3094*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0x4A, 0xAA, 0x4F, 0xEA, 0x0A, 0x18, 0x04, 0x04, 0x02, 0x02, 0x09,\n                0x09, 0x05, 0x03, 0x01, 0x05, 0x09,/*续3095*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x40, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x01, 0x01, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*轩3096*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x06, 0xEA, 0xAA, 0xAB, 0xAA, 0xEA, 0x06, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*喧3097*/},\n        {\n\n                0x06, 0xEA, 0xAA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xEA, 0x06, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*宣3098*/},\n        {\n\n                0x40, 0x40, 0xFF, 0x55, 0x55, 0x55, 0x55, 0x55, 0xFF, 0x40, 0x40, 0x08, 0x05, 0x01, 0x05, 0x0B,\n                0x0D, 0x09, 0x0D, 0x01, 0x07, 0x08,/*悬3099*/},\n        {\n\n                0x08, 0xF8, 0x49, 0x4A, 0xD0, 0x08, 0xD7, 0x14, 0xF4, 0x14, 0x34, 0x08, 0x07, 0x08, 0x08, 0x07,\n                0x08, 0x07, 0x08, 0x0F, 0x09, 0x09,/*旋3100*/},\n        {\n\n                0x04, 0x44, 0x64, 0x54, 0x4D, 0xC6, 0x44, 0x24, 0x04, 0x04, 0x04, 0x00, 0x04, 0x04, 0x06, 0x05,\n                0x04, 0x04, 0x04, 0x05, 0x0E, 0x00,/*玄3101*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x28, 0x26, 0xE4, 0x3F, 0xE4, 0x24, 0x20, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x09, 0x08, 0x08, 0x09, 0x0A, 0x0B,/*选3102*/},\n        {\n\n                0x88, 0xFE, 0x22, 0xF2, 0xAE, 0xEA, 0xBB, 0xE2, 0x56, 0xFA, 0x56, 0x08, 0x07, 0x08, 0x0B, 0x0A,\n                0x0B, 0x0A, 0x0B, 0x01, 0x0F, 0x01,/*癣3103*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x44, 0x64, 0x55, 0xCE, 0x44, 0x24, 0x04, 0x0F, 0x04, 0x0F, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*眩3104*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x04, 0xFB, 0x4A, 0x4A, 0xFA, 0x02, 0xFE, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x07, 0x02, 0x02, 0x0B, 0x08, 0x07,/*绚3105*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xF2, 0x0C, 0xFB, 0x40, 0xFF, 0x10, 0x0C, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x00, 0x0F, 0x00, 0x07, 0x08, 0x0E,/*靴3106*/},\n        {\n\n                0x02, 0xF2, 0x5A, 0x57, 0x72, 0x02, 0x92, 0xB7, 0xDA, 0xB2, 0x92, 0x00, 0x0F, 0x05, 0x05, 0x0F,\n                0x00, 0x00, 0x02, 0x0F, 0x02, 0x00,/*薛3107*/},\n        {\n\n                0x8C, 0x85, 0x96, 0x94, 0x95, 0x96, 0xD4, 0xB4, 0x96, 0x85, 0x8C, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*学3108*/},\n        {\n\n                0x1C, 0x04, 0x04, 0xF4, 0x05, 0x06, 0x04, 0xF4, 0x04, 0x04, 0x1C, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x08,/*穴3109*/},\n        {\n\n                0x0C, 0xA5, 0xAD, 0xAD, 0x85, 0xBF, 0x85, 0xAD, 0xAD, 0xA5, 0x0C, 0x00, 0x08, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*雪3110*/},\n        {\n\n                0x00, 0xF8, 0x08, 0x0C, 0xFB, 0x08, 0xF8, 0x08, 0x08, 0xF8, 0x00, 0x08, 0x0F, 0x08, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x08, 0x0F, 0x08,/*血3111*/},\n        {\n\n                0xF7, 0x15, 0xD5, 0x15, 0xF7, 0x00, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*勋3112*/},\n        {\n\n                0x08, 0x7A, 0x4A, 0x6A, 0x4A, 0xFE, 0x49, 0x69, 0x49, 0x79, 0x08, 0x04, 0x0D, 0x05, 0x05, 0x0D,\n                0x07, 0x0D, 0x05, 0x05, 0x0D, 0x04,/*熏3113*/},\n        {\n\n                0x24, 0xF2, 0x09, 0x00, 0xFE, 0x0A, 0xEA, 0xAA, 0xBE, 0xA9, 0xE9, 0x00, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x0F, 0x0A, 0x0A, 0x0A, 0x0F,/*循3114*/},\n        {\n\n                0x08, 0x04, 0xFB, 0x4A, 0x4A, 0x4A, 0x4A, 0xFA, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x07, 0x02, 0x02,\n                0x02, 0x02, 0x0B, 0x08, 0x08, 0x07,/*旬3115*/},\n        {\n\n                0x11, 0xF2, 0x08, 0x04, 0xFB, 0x4A, 0x4A, 0x4A, 0xFA, 0x02, 0xFE, 0x00, 0x07, 0x02, 0x00, 0x07,\n                0x02, 0x02, 0x02, 0x0B, 0x08, 0x07,/*询3116*/},\n        {\n\n                0x40, 0x51, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xF5, 0x5F, 0x40, 0x00, 0x00, 0x01, 0x06, 0x00,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*寻3117*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x00, 0xFF, 0x00, 0xFE, 0x00, 0xFF, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x08, 0x07, 0x00, 0x07, 0x00, 0x0F,/*驯3118*/},\n        {\n\n                0x21, 0xE2, 0x10, 0x6C, 0x83, 0x10, 0x6C, 0x83, 0x10, 0x6C, 0x83, 0x08, 0x07, 0x08, 0x08, 0x09,\n                0x08, 0x08, 0x09, 0x08, 0x08, 0x09,/*巡3119*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x04, 0xFB, 0x4A, 0x4A, 0xFA, 0x02, 0xFE, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x07, 0x02, 0x02, 0x0B, 0x08, 0x07,/*殉3120*/},\n        {\n\n                0x22, 0x44, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x22, 0xFE, 0x00, 0x80, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x0F,/*汛3121*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFF, 0x00, 0x07, 0x0A, 0x05, 0x03,\n                0x00, 0x00, 0x07, 0x00, 0x00, 0x0F,/*训3122*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x22, 0xFE, 0x22, 0x22, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x07, 0x02, 0x00,\n                0x0F, 0x00, 0x00, 0x03, 0x04, 0x0E,/*讯3123*/},\n        {\n\n                0x21, 0xE2, 0x40, 0x42, 0xFA, 0xA6, 0x70, 0x00, 0xFF, 0x10, 0xE0, 0x08, 0x07, 0x08, 0x0A, 0x0B,\n                0x08, 0x08, 0x0A, 0x0B, 0x08, 0x08,/*逊3124*/},\n        {\n\n                0x21, 0xE2, 0x00, 0x22, 0x22, 0xFE, 0x22, 0x22, 0xFE, 0x00, 0x80, 0x08, 0x07, 0x08, 0x08, 0x08,\n                0x0B, 0x08, 0x08, 0x08, 0x09, 0x0B,/*迅3125*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x42, 0x42, 0x42, 0xFA, 0x42, 0x42, 0x42, 0x02, 0x08, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x09, 0x0A, 0x08,/*压3126*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xFE, 0x92, 0x92, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x08, 0x0F, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*押3127*/},\n        {\n\n                0x32, 0xAA, 0x62, 0xFE, 0x22, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x02, 0x01, 0x08, 0x0F, 0x00,\n                0x02, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸦3128*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x02, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸭3129*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x32, 0x2A, 0xA2, 0x62, 0xFE, 0x22, 0x03, 0x01, 0x01, 0x03, 0x04,\n                0x02, 0x01, 0x00, 0x08, 0x0F, 0x00,/*呀3130*/},\n        {\n\n                0x01, 0x02, 0x04, 0x08, 0x10, 0xE0, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*丫3131*/},\n        {\n\n                0x02, 0xD2, 0x92, 0x97, 0x92, 0x92, 0x92, 0xF7, 0x92, 0x92, 0x82, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x00,/*芽3132*/},\n        {\n\n                0x00, 0x32, 0x2A, 0x22, 0x22, 0xA2, 0x62, 0xFE, 0x22, 0x22, 0x20, 0x04, 0x04, 0x02, 0x02, 0x01,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*牙3133*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x32, 0xAA, 0x62, 0xFE, 0x22, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x04, 0x02, 0x01, 0x08, 0x0F, 0x00,/*蚜3134*/},\n        {\n\n                0x00, 0xFB, 0x8A, 0xAA, 0xAA, 0xAB, 0xFA, 0xAA, 0xAA, 0xAB, 0x88, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*崖3135*/},\n        {\n\n                0x24, 0xF2, 0x49, 0x7A, 0x4E, 0x4A, 0x7A, 0x40, 0x12, 0xF2, 0x12, 0x00, 0x0F, 0x00, 0x0F, 0x09,\n                0x09, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*衙3136*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x42, 0x52, 0x52, 0x7E, 0x52, 0x52, 0x42, 0x04, 0x02, 0x08, 0x07, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*涯3137*/},\n        {\n\n                0x32, 0xAA, 0x62, 0xFE, 0x22, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x24, 0x02, 0x01, 0x08, 0x0F, 0x00,\n                0x00, 0x0F, 0x09, 0x0F, 0x09, 0x09,/*雅3138*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x22, 0x42, 0xFE, 0x02, 0x02, 0xFE, 0x42, 0x22, 0x03, 0x01, 0x03, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x0F, 0x08, 0x08,/*哑3139*/},\n        {\n\n                0x20, 0x42, 0x82, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x82, 0x42, 0x20, 0x08, 0x08, 0x08, 0x0F, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*亚3140*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x02, 0x3A, 0x22, 0x22, 0xA2, 0x62, 0xFE, 0x22, 0x00, 0x07, 0x02, 0x09, 0x04,\n                0x02, 0x01, 0x08, 0x08, 0x0F, 0x00,/*讶3141*/},\n        {\n\n                0x11, 0x91, 0x7D, 0x51, 0x51, 0x5F, 0x55, 0x55, 0x55, 0x55, 0x11, 0x0C, 0x01, 0x0D, 0x01, 0x0D,\n                0x01, 0x0D, 0x01, 0x09, 0x09, 0x07,/*焉3142*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFF, 0x11, 0x91, 0x7D, 0x91, 0x11, 0xFF, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x05, 0x0F,/*咽3143*/},\n        {\n\n                0xF9, 0x42, 0x24, 0xF5, 0xAD, 0xF7, 0xAD, 0xF5, 0x25, 0x41, 0xFF, 0x0F, 0x00, 0x00, 0x07, 0x02,\n                0x07, 0x0A, 0x0B, 0x00, 0x08, 0x0F,/*阉3144*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFF, 0x11, 0x91, 0x7D, 0x91, 0x11, 0xFF, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x05, 0x0F,/*烟3145*/},\n        {\n\n                0x22, 0x44, 0x22, 0xF2, 0xAA, 0xA6, 0xF3, 0xA6, 0xAA, 0xF2, 0x22, 0x04, 0x02, 0x00, 0x07, 0x02,\n                0x02, 0x07, 0x0A, 0x0A, 0x0B, 0x0C,/*淹3146*/},\n        {\n\n                0x20, 0xA4, 0xA4, 0xBF, 0x94, 0x94, 0x80, 0xBF, 0x84, 0x88, 0x10, 0x08, 0x0F, 0x08, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x08, 0x0F, 0x08,/*盐3147*/},\n        {\n\n                0x00, 0xC2, 0x4A, 0x52, 0x7E, 0x42, 0x42, 0x7E, 0x52, 0x4A, 0x42, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*严3148*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x22, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*研3149*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x32, 0xCE, 0x00, 0xF2, 0x02, 0xFF, 0x11, 0x04, 0x04, 0x03, 0x02, 0x0A,\n                0x07, 0x08, 0x09, 0x09, 0x09, 0x09,/*蜒3150*/},\n        {\n\n                0x20, 0x2E, 0xA8, 0xE8, 0xA8, 0xAF, 0xA8, 0xA8, 0xA8, 0xAE, 0x20, 0x02, 0x01, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*岩3151*/},\n        {\n\n                0x02, 0x32, 0x2A, 0xE6, 0x00, 0xF2, 0x02, 0x02, 0xFE, 0x21, 0x21, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0B, 0x0A, 0x0A,/*延3152*/},\n        {\n\n                0x04, 0x54, 0x54, 0x54, 0x55, 0x56, 0x54, 0x54, 0x54, 0x54, 0x04, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*言3153*/},\n        {\n\n                0x00, 0xF2, 0x56, 0x5B, 0xB6, 0x12, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x08, 0x07, 0x09, 0x09, 0x04,\n                0x02, 0x09, 0x04, 0x03, 0x04, 0x09,/*颜3154*/},\n        {\n\n                0xF9, 0x02, 0xD0, 0x49, 0x27, 0x05, 0x55, 0x4D, 0xC1, 0x01, 0xFF, 0x0F, 0x00, 0x07, 0x05, 0x05,\n                0x04, 0x05, 0x05, 0x07, 0x08, 0x0F,/*阎3155*/},\n        {\n\n                0x20, 0x24, 0x92, 0x10, 0x08, 0xC7, 0x08, 0x08, 0x14, 0x92, 0x20, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x05, 0x08, 0x08,/*炎3156*/},\n        {\n\n                0x10, 0x21, 0x02, 0xD0, 0x4F, 0x41, 0x41, 0x41, 0x4F, 0xD0, 0x10, 0x04, 0x02, 0x01, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*沿3157*/},\n        {\n\n                0x12, 0x12, 0xEA, 0xAA, 0xA6, 0xF3, 0xA6, 0xAA, 0xEA, 0x12, 0x12, 0x00, 0x00, 0x07, 0x02, 0x02,\n                0x07, 0x0A, 0x0A, 0x0B, 0x08, 0x0E,/*奄3158*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x12, 0xEA, 0xA6, 0xF3, 0xA6, 0xEA, 0x12, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x07, 0x02, 0x07, 0x0A, 0x0B, 0x0C,/*掩3159*/},\n        {\n\n                0xFF, 0x49, 0x49, 0xFF, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x07, 0x02, 0x02, 0x07, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*眼3160*/},\n        {\n\n                0x44, 0x22, 0xF1, 0x08, 0x10, 0x21, 0x02, 0x00, 0x12, 0xF2, 0x12, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x00, 0x08, 0x0F, 0x00,/*衍3161*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xE6, 0xAA, 0xAA, 0xFB, 0xAA, 0xAA, 0xE6, 0x04, 0x02, 0x01, 0x00, 0x0B,\n                0x06, 0x02, 0x03, 0x02, 0x06, 0x0B,/*演3162*/},\n        {\n\n                0x04, 0x24, 0xFF, 0x24, 0x08, 0xF4, 0x93, 0xF2, 0x9A, 0x96, 0xF0, 0x01, 0x01, 0x0F, 0x01, 0x01,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*艳3163*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFF, 0x81, 0xBF, 0xEB, 0xAB, 0xBF, 0x81, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x08, 0x0D, 0x0A, 0x0A, 0x0D, 0x08,/*堰3164*/},\n        {\n\n                0x12, 0x92, 0xFA, 0x02, 0xEF, 0x2A, 0xEF, 0x02, 0xFA, 0x22, 0x92, 0x09, 0x04, 0x01, 0x04, 0x09,\n                0x01, 0x05, 0x08, 0x00, 0x05, 0x09,/*燕3165*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x22, 0x22, 0xA2, 0x7E, 0xA2, 0x2A, 0x32, 0x22, 0x08, 0x07, 0x08, 0x04, 0x02,\n                0x01, 0x00, 0x01, 0x02, 0x04, 0x08,/*厌3166*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*砚3167*/},\n        {\n\n                0x00, 0xFF, 0x11, 0xF9, 0x27, 0xF9, 0x4F, 0x49, 0xFB, 0x4D, 0x49, 0x08, 0x07, 0x00, 0x0F, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*雁3168*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x04, 0x54, 0x54, 0x55, 0x56, 0x54, 0x54, 0x04, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*唁3169*/},\n        {\n\n                0x00, 0xF2, 0x12, 0x96, 0x9A, 0x53, 0x52, 0x3A, 0x96, 0x92, 0x12, 0x08, 0x07, 0x00, 0x0A, 0x0A,\n                0x0A, 0x05, 0x05, 0x04, 0x02, 0x02,/*彦3170*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x00, 0xE4, 0x93, 0x02, 0x8A, 0xA6, 0xE0, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*焰3171*/},\n        {\n\n                0x06, 0x02, 0x7E, 0x56, 0xD6, 0x57, 0x56, 0x56, 0x7E, 0x02, 0x06, 0x01, 0x09, 0x09, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*宴3172*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xF2, 0x16, 0x5A, 0x53, 0xBA, 0x96, 0x12, 0x00, 0x07, 0x02, 0x08, 0x07,\n                0x08, 0x09, 0x09, 0x04, 0x04, 0x02,/*谚3173*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x02, 0x0A, 0x09, 0x07, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*验3174*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x80, 0xFC, 0x84, 0xFF, 0x84, 0xFC, 0x80, 0x08, 0x04, 0x02, 0x01, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*殃3175*/},\n        {\n\n                0x80, 0xFC, 0x84, 0x84, 0x84, 0xFF, 0x84, 0x84, 0x84, 0xFC, 0x80, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*央3176*/},\n        {\n\n                0x28, 0x2E, 0xEA, 0x5A, 0xEA, 0x4F, 0x4A, 0x5A, 0xEA, 0x2E, 0x28, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x03, 0x0B, 0x0A, 0x06,/*鸯3177*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0xFC, 0x84, 0xFF, 0x84, 0xFC, 0x80, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*秧3178*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x22, 0xF2, 0x2A, 0xE6, 0x22, 0xE0, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*杨3179*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x08, 0x22, 0xF2, 0x2A, 0xE6, 0x22, 0xE0, 0x00, 0x08, 0x0F, 0x00, 0x02,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*扬3180*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x04, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*佯3181*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0x4A, 0x6A, 0xEB, 0x5A, 0xDA, 0x4A, 0xC2, 0x09, 0x04, 0x03, 0x00, 0x0A,\n                0x09, 0x04, 0x02, 0x09, 0x08, 0x07,/*疡3182*/},\n        {\n\n                0x00, 0x24, 0x25, 0x26, 0x24, 0xFC, 0x24, 0x26, 0x25, 0x24, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*羊3183*/},\n        {\n\n                0x22, 0x44, 0x00, 0x24, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x24, 0x00, 0x04, 0x02, 0x01, 0x01, 0x01,\n                0x01, 0x0F, 0x01, 0x01, 0x01, 0x01,/*洋3184*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0xFE, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*阳3185*/},\n        {\n\n                0x08, 0x24, 0xAB, 0xBA, 0xEA, 0xBA, 0xAA, 0x2A, 0xFA, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x0F,\n                0x02, 0x02, 0x02, 0x03, 0x04, 0x0E,/*氧3186*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xFC, 0x02, 0x81, 0xFC, 0x04, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x03,\n                0x01, 0x00, 0x0F, 0x00, 0x02, 0x03,/*仰3187*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0x12, 0x56, 0x5B, 0xF2, 0x5A, 0x56, 0x12, 0x09, 0x04, 0x03, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*痒3188*/},\n        {\n\n                0x40, 0x54, 0xD5, 0x56, 0x74, 0x5C, 0x54, 0x56, 0xD5, 0x54, 0x40, 0x02, 0x01, 0x08, 0x07, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x01, 0x02,/*养3189*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x04, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*样3190*/},\n        {\n\n                0x22, 0x44, 0x22, 0x2A, 0xAB, 0xEA, 0xBE, 0x2A, 0x2B, 0x2A, 0xA2, 0x04, 0x02, 0x09, 0x05, 0x03,\n                0x08, 0x0F, 0x01, 0x02, 0x05, 0x08,/*漾3191*/},\n        {\n\n                0x11, 0xF2, 0x80, 0xBE, 0xEB, 0xBE, 0x88, 0x77, 0x84, 0x7C, 0x04, 0x08, 0x07, 0x0C, 0x0B, 0x0A,\n                0x0E, 0x0C, 0x0A, 0x09, 0x0A, 0x0C,/*邀3192*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xBA, 0xAA, 0xBE, 0xEA, 0xBE, 0xAA, 0xBA, 0x07, 0x08, 0x0F, 0x00, 0x08,\n                0x0A, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*腰3193*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*妖3194*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x4A, 0x32, 0x26, 0xEA, 0x21, 0x29, 0x05, 0x04, 0x07, 0x02, 0x00, 0x0D,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x0D,/*瑶3195*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x4A, 0x32, 0x26, 0xEA, 0x21, 0x29, 0x05, 0x00, 0x08, 0x0F, 0x00, 0x0D,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x0D,/*摇3196*/},\n        {\n\n                0x84, 0xA4, 0xA4, 0xA4, 0xA7, 0x9C, 0x92, 0xAA, 0xA6, 0xA2, 0xB2, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*尧3197*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x42, 0x66, 0x5A, 0x56, 0xFA, 0x51, 0x59, 0x45, 0x08, 0x07, 0x08, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x0B,/*遥3198*/},\n        {\n\n                0x06, 0x4A, 0x36, 0x22, 0x22, 0xE3, 0x22, 0x22, 0x26, 0x2A, 0x06, 0x01, 0x0D, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x0D, 0x01,/*窑3199*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x00, 0x4A, 0x32, 0x26, 0xEA, 0x21, 0x29, 0x05, 0x00, 0x0F, 0x04, 0x00, 0x0D,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x0D,/*谣3200*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x84, 0x48, 0xFF, 0x00, 0xFF, 0x48, 0x84, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*姚3201*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x44, 0x24, 0xD4, 0x05, 0x06, 0xD4, 0x24, 0x44, 0x03, 0x01, 0x03, 0x08, 0x08,\n                0x05, 0x02, 0x02, 0x05, 0x08, 0x08,/*咬3202*/},\n        {\n\n                0x00, 0xCA, 0x52, 0x42, 0x26, 0x0A, 0x41, 0x41, 0x51, 0xC9, 0x00, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x04, 0x05, 0x05, 0x05, 0x0F, 0x00,/*舀3203*/},\n        {\n\n                0x22, 0xB2, 0x6A, 0x27, 0x12, 0x22, 0x9A, 0x17, 0x12, 0x12, 0xF2, 0x09, 0x09, 0x09, 0x05, 0x05,\n                0x04, 0x00, 0x01, 0x08, 0x08, 0x07,/*药3204*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xAA, 0xFE, 0xAA, 0xBE, 0xAA, 0xAA, 0xBA, 0x82, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*要3205*/},\n        {\n\n                0x24, 0xE8, 0x3F, 0xE8, 0x24, 0x4A, 0xF5, 0xAF, 0xEA, 0xB5, 0xAF, 0x08, 0x07, 0x00, 0x0F, 0x04,\n                0x00, 0x0F, 0x0A, 0x0F, 0x0A, 0x0A,/*耀3206*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x4A, 0xFE, 0x52, 0xFE, 0x02, 0xFE, 0x32, 0xCE, 0x00, 0x00, 0x0F, 0x02, 0x03,\n                0x02, 0x0F, 0x01, 0x0F, 0x02, 0x01,/*椰3207*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0x62, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0x62, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x0B, 0x0E, 0x0A, 0x0E, 0x0B, 0x08,/*噎3208*/},\n        {\n\n                0x02, 0xFE, 0x52, 0x52, 0xFE, 0x02, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x02, 0x03, 0x02, 0x02, 0x0F,\n                0x01, 0x00, 0x0F, 0x02, 0x02, 0x01,/*耶3209*/},\n        {\n\n                0x20, 0xA4, 0x92, 0x95, 0x88, 0x88, 0x88, 0x95, 0x92, 0xA4, 0x20, 0x00, 0x00, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x04, 0x07, 0x00,/*爷3210*/},\n        {\n\n                0xBE, 0xAA, 0xFE, 0xAA, 0xBE, 0x00, 0x22, 0x2A, 0xF2, 0x2A, 0x66, 0x04, 0x04, 0x07, 0x02, 0x02,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*野3211*/},\n        {\n\n                0x04, 0x08, 0x00, 0x10, 0xD8, 0x54, 0x53, 0x50, 0x50, 0xD8, 0x30, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*冶3212*/},\n        {\n\n                0x20, 0x20, 0xFE, 0x10, 0x10, 0xFF, 0x08, 0x08, 0x84, 0xFC, 0x00, 0x00, 0x00, 0x07, 0x08, 0x08,\n                0x09, 0x08, 0x08, 0x08, 0x08, 0x0E,/*也3213*/},\n        {\n\n                0x01, 0xF9, 0x09, 0x09, 0x0D, 0xCB, 0x09, 0x09, 0x09, 0xF9, 0x01, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*页3214*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x84, 0xE4, 0x1C, 0xC5, 0x3E, 0x54, 0x94, 0x74, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*掖3215*/},\n        {\n\n                0x10, 0x20, 0x40, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0x40, 0x20, 0x10, 0x08, 0x08, 0x08, 0x0F, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*业3216*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x20, 0x20, 0x20, 0xFF, 0x20, 0x20, 0x20, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*叶3217*/},\n        {\n\n                0x00, 0x7C, 0x54, 0x54, 0x54, 0xFF, 0x54, 0x54, 0xD4, 0x7C, 0x00, 0x08, 0x08, 0x08, 0x04, 0x04,\n                0x03, 0x02, 0x05, 0x04, 0x08, 0x0E,/*曳3218*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x80, 0xE4, 0x1C, 0xC5, 0x3E, 0x54, 0x94, 0x74, 0x07, 0x08, 0x0F, 0x00, 0x0F,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*腋3219*/},\n        {\n\n                0x84, 0x44, 0xE4, 0x9C, 0x45, 0xA6, 0x1C, 0x54, 0x94, 0x74, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*夜3220*/},\n        {\n\n                0x22, 0x44, 0x80, 0xE4, 0x1C, 0xC5, 0x3E, 0x54, 0x94, 0x74, 0x04, 0x04, 0x02, 0x00, 0x0F, 0x01,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*液3221*/},\n        {\n\n                0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*一3222*/},\n        {\n\n                0x62, 0xAA, 0xAA, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0xAA, 0xAA, 0x62, 0x08, 0x0B, 0x0A, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0E, 0x0A, 0x0B, 0x08,/*壹3223*/},\n        {\n\n                0x00, 0xFE, 0xA2, 0x92, 0x9E, 0x92, 0xF2, 0x92, 0x92, 0x92, 0x82, 0x00, 0x0F, 0x08, 0x0C, 0x0A,\n                0x09, 0x08, 0x09, 0x0A, 0x0C, 0x08,/*医3224*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0xF7, 0x55, 0x55, 0x55, 0xF7, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x07, 0x05, 0x05, 0x05, 0x0F, 0x02,/*揖3225*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x80, 0x44, 0xE4, 0x15, 0x6E, 0x84, 0x44, 0x24, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x00, 0x01, 0x02, 0x04,/*铱3226*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x83, 0x44, 0xE4, 0x15, 0x6E, 0x84, 0x44, 0x24, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x00, 0x01, 0x02, 0x04,/*依3227*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x10, 0x92, 0x92, 0xFE, 0x92, 0x92, 0xFE, 0x10, 0x00, 0x0F, 0x00, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x00, 0x01, 0x00,/*伊3228*/},\n        {\n\n                0x04, 0x84, 0x44, 0xF4, 0x0C, 0x35, 0xC6, 0x44, 0x24, 0x14, 0x04, 0x01, 0x00, 0x00, 0x0F, 0x04,\n                0x02, 0x00, 0x01, 0x02, 0x04, 0x04,/*衣3229*/},\n        {\n\n                0xFE, 0x02, 0xF2, 0x1E, 0xF2, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x0F, 0x08, 0x09, 0x0F, 0x09,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颐3230*/},\n        {\n\n                0x02, 0xEA, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAA, 0xBA, 0x82, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x04, 0x0A, 0x0B,/*夷3231*/},\n        {\n\n                0x11, 0xF2, 0x20, 0xAE, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xAE, 0x20, 0x08, 0x07, 0x08, 0x0B, 0x0C,\n                0x0A, 0x09, 0x0A, 0x0C, 0x0B, 0x08,/*遗3232*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x08, 0x44, 0xAB, 0x52, 0x6A, 0x46, 0xC0, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x04, 0x05, 0x02, 0x01, 0x00,/*移3233*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x18, 0x60, 0x81, 0x06, 0x80, 0x60, 0x1C, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*仪3234*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x00, 0xEA, 0xAA, 0xFF, 0xAA, 0xAA, 0xBA, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x08, 0x04, 0x03, 0x04, 0x0A, 0x0B,/*胰3235*/},\n        {\n\n                0x40, 0x37, 0x2A, 0xE9, 0x2C, 0x00, 0x91, 0x15, 0xF9, 0x95, 0xB3, 0x01, 0x09, 0x05, 0x03, 0x05,\n                0x09, 0x07, 0x08, 0x0F, 0x08, 0x08,/*疑3236*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0xFE, 0x12, 0x12, 0x11, 0xF1, 0x11, 0x10, 0x04, 0x02, 0x09, 0x06, 0x01,\n                0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,/*沂3237*/},\n        {\n\n                0x0C, 0x04, 0xF4, 0x54, 0x55, 0x56, 0x54, 0x54, 0xF4, 0x04, 0x0C, 0x08, 0x08, 0x0F, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x0F, 0x08, 0x08,/*宜3238*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xEA, 0xAA, 0xFF, 0xAA, 0xAA, 0xBA, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x08, 0x04, 0x03, 0x04, 0x0A, 0x0B,/*姨3239*/},\n        {\n\n                0xAC, 0x24, 0xFE, 0x25, 0xAD, 0x45, 0xD5, 0x5D, 0xF7, 0x54, 0xCC, 0x02, 0x02, 0x0A, 0x07, 0x02,\n                0x03, 0x02, 0x0F, 0x03, 0x02, 0x02,/*彝3240*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0xDA, 0x56, 0xD3, 0x16, 0xFA, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x02, 0x03, 0x08, 0x0F, 0x00,/*椅3241*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x00, 0x38, 0xC1, 0x06, 0xC0, 0x3C, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x00, 0x08, 0x04, 0x03, 0x04, 0x08,/*蚁3242*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x10, 0xDA, 0x56, 0x53, 0xD2, 0x16, 0xFA, 0x10, 0x00, 0x0F, 0x00, 0x00, 0x07,\n                0x02, 0x02, 0x0B, 0x08, 0x0F, 0x00,/*倚3243*/},\n        {\n\n                0x00, 0xF2, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x7E, 0x00, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*已3244*/},\n        {\n\n                0x02, 0x02, 0x82, 0x42, 0x22, 0x12, 0x0A, 0x06, 0x02, 0x00, 0x00, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x0F, 0x00,/*乙3245*/},\n        {\n\n                0x00, 0x48, 0x2C, 0x3A, 0x29, 0xE8, 0x28, 0x2A, 0x2C, 0x18, 0x00, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*矣3246*/},\n        {\n\n                0x00, 0xFE, 0x00, 0x80, 0x42, 0x0C, 0x00, 0x80, 0x7F, 0x00, 0x00, 0x00, 0x03, 0x09, 0x08, 0x04,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*以3247*/},\n        {\n\n                0x02, 0x12, 0x12, 0x17, 0x92, 0x92, 0x52, 0x57, 0x32, 0x12, 0x02, 0x00, 0x06, 0x09, 0x09, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*艺3248*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xFC, 0x02, 0x81, 0xFC, 0x04, 0x04, 0xFC, 0x00, 0x08, 0x0F, 0x00, 0x03,\n                0x01, 0x00, 0x0F, 0x00, 0x02, 0x03,/*抑3249*/},\n        {\n\n                0x00, 0x9F, 0x75, 0x55, 0xD5, 0x55, 0x55, 0xD5, 0x55, 0x5F, 0xC0, 0x01, 0x08, 0x04, 0x02, 0x09,\n                0x04, 0x02, 0x09, 0x08, 0x08, 0x07,/*易3250*/},\n        {\n\n                0x00, 0xF0, 0x97, 0x95, 0x95, 0xF5, 0x95, 0x95, 0x97, 0xF0, 0x00, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*邑3251*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x08, 0x24, 0x27, 0xA4, 0x64, 0x04, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x06, 0x09, 0x08, 0x08, 0x0E,/*屹3252*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x02, 0xC2, 0x22, 0x12, 0x0A, 0x06, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0F,/*亿3253*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x50, 0xCF, 0x41, 0x41, 0x4F, 0xD0, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*役3254*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x08, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x02, 0x0C, 0x09, 0x0C, 0x02, 0x0C,/*臆3255*/},\n        {\n\n                0x11, 0xF2, 0x08, 0x3C, 0xAB, 0x6A, 0xBA, 0x6A, 0xAE, 0x38, 0x00, 0x08, 0x07, 0x0A, 0x09, 0x08,\n                0x08, 0x09, 0x0A, 0x0A, 0x0A, 0x0B,/*逸3256*/},\n        {\n\n                0x40, 0x37, 0xEA, 0x2D, 0x00, 0xAA, 0xAA, 0xFF, 0xAA, 0xBE, 0x08, 0x09, 0x05, 0x03, 0x05, 0x09,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*肄3257*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x42, 0xA2, 0x9A, 0x8B, 0x8A, 0x9A, 0xA2, 0x22, 0x09, 0x04, 0x03, 0x08, 0x08,\n                0x0B, 0x04, 0x04, 0x0A, 0x09, 0x08,/*疫3258*/},\n        {\n\n                0x04, 0xC4, 0x04, 0xFC, 0x05, 0x06, 0x04, 0xFC, 0x04, 0x44, 0x84, 0x01, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x01,/*亦3259*/},\n        {\n\n                0x12, 0xD2, 0x4A, 0xFE, 0x52, 0x47, 0x4A, 0xD2, 0x5A, 0xE6, 0x22, 0x00, 0x0F, 0x01, 0x00, 0x07,\n                0x05, 0x07, 0x00, 0x09, 0x0F, 0x00,/*裔3260*/},\n        {\n\n                0x08, 0x0A, 0xFA, 0xAE, 0xAA, 0xAB, 0xAA, 0xAE, 0xFA, 0x0A, 0x08, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*意3261*/},\n        {\n\n                0x56, 0x5A, 0xB3, 0x5A, 0x96, 0x50, 0x08, 0xE7, 0x21, 0xEF, 0x08, 0x05, 0x05, 0x0A, 0x09, 0x07,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*毅3262*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x12, 0xC2, 0x22, 0x12, 0x0A, 0x06, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0F,/*忆3263*/},\n        {\n\n                0x00, 0x0C, 0x10, 0x20, 0x41, 0x86, 0x40, 0x20, 0x18, 0x06, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*义3264*/},\n        {\n\n                0x48, 0xA9, 0x9A, 0x8C, 0x88, 0x88, 0x88, 0x8C, 0x9A, 0xA9, 0x48, 0x08, 0x0F, 0x08, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x08, 0x0F, 0x08,/*益3265*/},\n        {\n\n                0x11, 0x22, 0x48, 0xA9, 0x9A, 0x88, 0x88, 0x88, 0x9A, 0xA9, 0x48, 0x04, 0x02, 0x08, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*溢3266*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x00, 0xCF, 0x54, 0x54, 0x54, 0x52, 0x52, 0xD9, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*诣3267*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x18, 0x60, 0x81, 0x06, 0x80, 0x60, 0x1C, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*议3268*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x0C, 0xF4, 0x54, 0x55, 0x56, 0x54, 0xF4, 0x0C, 0x00, 0x0F, 0x04, 0x08, 0x0F,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x08,/*谊3269*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0x21, 0xA3, 0x95, 0xE9, 0x95, 0xA3, 0x20, 0x00, 0x07, 0x02, 0x01, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*译3270*/},\n        {\n\n                0x00, 0x1F, 0x25, 0xE5, 0x25, 0x25, 0x25, 0x25, 0xE5, 0x27, 0x30, 0x01, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x01, 0x0F, 0x01, 0x01,/*异3271*/},\n        {\n\n                0x01, 0x8B, 0xFD, 0xA9, 0xAF, 0xF8, 0xA9, 0xAB, 0xFD, 0x81, 0x0F, 0x02, 0x0A, 0x06, 0x03, 0x02,\n                0x02, 0x02, 0x03, 0x06, 0x0A, 0x02,/*翼3272*/},\n        {\n\n                0x00, 0x95, 0x89, 0x81, 0xBF, 0xC0, 0x95, 0x89, 0x81, 0x9F, 0x00, 0x08, 0x08, 0x0A, 0x0C, 0x08,\n                0x08, 0x08, 0x0C, 0x0A, 0x08, 0x08,/*翌3273*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x21, 0xA3, 0x95, 0xE9, 0x95, 0xA3, 0x20, 0x04, 0x04, 0x02, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*绎3274*/},\n        {\n\n                0x02, 0xFA, 0x0A, 0x4F, 0x4A, 0xEA, 0x4A, 0x4F, 0x0A, 0xFA, 0x02, 0x00, 0x0F, 0x08, 0x0A, 0x09,\n                0x08, 0x09, 0x0A, 0x08, 0x0F, 0x00,/*茵3275*/},\n        {\n\n                0x02, 0xFA, 0x0A, 0x4F, 0xBA, 0x02, 0xFA, 0x4F, 0x4A, 0x4A, 0xFA, 0x00, 0x0F, 0x01, 0x02, 0x09,\n                0x04, 0x03, 0x01, 0x09, 0x09, 0x0F,/*荫3276*/},\n        {\n\n                0xFF, 0x01, 0x11, 0x91, 0x51, 0x3D, 0x51, 0x91, 0x11, 0x01, 0xFF, 0x0F, 0x04, 0x05, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x05, 0x04, 0x0F,/*因3277*/},\n        {\n\n                0x00, 0xFE, 0x55, 0x55, 0x7D, 0x10, 0xCE, 0x42, 0x42, 0xDE, 0x10, 0x08, 0x07, 0x01, 0x09, 0x0F,\n                0x08, 0x05, 0x02, 0x02, 0x05, 0x08,/*殷3278*/},\n        {\n\n                0x10, 0xD2, 0x56, 0x5A, 0x52, 0x53, 0x52, 0x5A, 0x56, 0xD2, 0x10, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*音3279*/},\n        {\n\n                0xFF, 0x01, 0x19, 0xE7, 0x00, 0xFF, 0x49, 0x49, 0x49, 0xFF, 0x00, 0x0F, 0x02, 0x02, 0x09, 0x04,\n                0x03, 0x00, 0x08, 0x08, 0x0F, 0x00,/*阴3280*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFE, 0xA2, 0x7A, 0xA2, 0x22, 0xFE, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x05, 0x0F,/*姻3281*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x20, 0x90, 0x8C, 0xA3, 0x8C, 0x90, 0x20, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x00, 0x08, 0x06, 0x01, 0x00,/*吟3282*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*银3283*/},\n        {\n\n                0x22, 0x44, 0x02, 0x2A, 0x32, 0x26, 0xEA, 0x11, 0x19, 0x15, 0x01, 0x04, 0x02, 0x01, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x01,/*淫3284*/},\n        {\n\n                0x06, 0xEA, 0xAA, 0xAA, 0xAA, 0xFB, 0xAA, 0xAA, 0xAA, 0xEA, 0x06, 0x00, 0x0B, 0x06, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x06, 0x0B, 0x00,/*寅3285*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x20, 0x18, 0x07, 0xE4, 0x04, 0x14, 0x0C, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*饮3286*/},\n        {\n\n                0x10, 0x92, 0x92, 0x92, 0xF2, 0x9E, 0x92, 0x92, 0x92, 0xFE, 0x10, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x01, 0x00,/*尹3287*/},\n        {\n\n                0x00, 0xF2, 0x92, 0x92, 0x92, 0x9E, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x08, 0x08, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x0F, 0x00,/*引3288*/},\n        {\n\n                0xFE, 0x12, 0xEE, 0x08, 0x84, 0xAB, 0xAA, 0xAA, 0xAE, 0xF8, 0x00, 0x0F, 0x01, 0x08, 0x06, 0x00,\n                0x06, 0x09, 0x0A, 0x0C, 0x02, 0x0C,/*隐3289*/},\n        {\n\n                0xFE, 0x12, 0x12, 0x11, 0x91, 0x00, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x03, 0x02, 0x01, 0x01, 0x00,\n                0x00, 0x0F, 0x00, 0x02, 0x02, 0x03,/*印3290*/},\n        {\n\n                0x02, 0xF2, 0x12, 0x17, 0x12, 0xFA, 0x12, 0x17, 0x12, 0xF2, 0x02, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*英3291*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0x80, 0xAF, 0x91, 0xEF, 0x80, 0xAF, 0x91, 0xAF, 0x00, 0x0F, 0x00, 0x08, 0x0A,\n                0x0B, 0x04, 0x04, 0x0B, 0x08, 0x00,/*樱3292*/},\n        {\n\n                0xAF, 0x91, 0x8D, 0x91, 0xEF, 0x80, 0xAF, 0x91, 0x8D, 0x91, 0xAF, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*婴3293*/},\n        {\n\n                0x00, 0xFE, 0x22, 0xFA, 0x96, 0xFA, 0xAF, 0xAA, 0xFE, 0xAA, 0xAA, 0x04, 0x03, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x02, 0x0B, 0x0E,/*鹰3294*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x44, 0x84, 0x15, 0xE6, 0x04, 0x04, 0xE4, 0x04, 0x08, 0x07, 0x08, 0x08, 0x0B,\n                0x08, 0x08, 0x0C, 0x0B, 0x08, 0x08,/*应3295*/},\n        {\n\n                0xDC, 0xB3, 0x08, 0x80, 0xAF, 0x91, 0xEF, 0x80, 0xAF, 0x91, 0xAF, 0x04, 0x04, 0x02, 0x08, 0x0A,\n                0x0B, 0x04, 0x04, 0x0B, 0x08, 0x00,/*缨3296*/},\n        {\n\n                0x1A, 0x2A, 0x2A, 0x2F, 0x2A, 0xEA, 0x2A, 0x2F, 0x2A, 0x2A, 0x1A, 0x08, 0x08, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x0B, 0x0D, 0x08, 0x08,/*莹3297*/},\n        {\n\n                0x1A, 0xEA, 0x2A, 0x2F, 0x2A, 0xFA, 0x2A, 0x2F, 0x2A, 0xEA, 0x1A, 0x04, 0x05, 0x05, 0x05, 0x05,\n                0x07, 0x05, 0x05, 0x05, 0x05, 0x0E,/*萤3298*/},\n        {\n\n                0x1A, 0x0A, 0xEA, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0xEA, 0x0A, 0x1A, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*营3299*/},\n        {\n\n                0x32, 0x12, 0xD2, 0x17, 0x92, 0x72, 0x92, 0x17, 0x12, 0xD2, 0x32, 0x08, 0x09, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x05, 0x08, 0x08,/*荧3300*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xF7, 0x55, 0xFD, 0x55, 0xF7, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x03, 0x01, 0x07, 0x09, 0x0D,/*蝇3301*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFE, 0x82, 0x41, 0x00, 0xFE, 0x02, 0x02, 0xFE, 0x08, 0x07, 0x08, 0x09, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x09, 0x09,/*迎3302*/},\n        {\n\n                0xE2, 0xAE, 0xEA, 0x0A, 0xCA, 0x4B, 0x4A, 0x4A, 0xEA, 0x2A, 0xE2, 0x07, 0x0A, 0x0F, 0x00, 0x0B,\n                0x04, 0x07, 0x08, 0x07, 0x01, 0x0F,/*赢3303*/},\n        {\n\n                0x42, 0x32, 0x0E, 0x5A, 0x2A, 0x5A, 0x02, 0x5A, 0x56, 0x30, 0x00, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盈3304*/},\n        {\n\n                0x40, 0xDF, 0x55, 0x75, 0x55, 0xDF, 0x40, 0x00, 0x88, 0x44, 0x33, 0x08, 0x05, 0x09, 0x0F, 0x01,\n                0x05, 0x08, 0x00, 0x08, 0x04, 0x03,/*影3305*/},\n        {\n\n                0x87, 0xAA, 0xEA, 0x99, 0x8C, 0x00, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x04, 0x02, 0x0F, 0x02, 0x04,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颖3306*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFA, 0xAA, 0xFE, 0xAA, 0xFA, 0x02, 0x00, 0x0F, 0x04, 0x0F, 0x01,\n                0x0A, 0x04, 0x07, 0x08, 0x08, 0x08,/*硬3307*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x80, 0xFC, 0x84, 0xFF, 0x84, 0xFC, 0x80, 0x07, 0x02, 0x02, 0x07, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*映3308*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xDC, 0xB3, 0x88, 0x28, 0xC7, 0x04, 0xFC, 0x03, 0x01, 0x03, 0x00, 0x04,\n                0x04, 0x02, 0x00, 0x08, 0x08, 0x07,/*哟3309*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x92, 0x92, 0xFE, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0F,/*拥3310*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0F,/*佣3311*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0xB2, 0x6E, 0x92, 0xFB, 0x56, 0xFA, 0x52, 0x08, 0x07, 0x08, 0x0F, 0x05,\n                0x03, 0x00, 0x0F, 0x05, 0x07, 0x05,/*臃3312*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0xF4, 0x55, 0x56, 0xF4, 0x54, 0x54, 0xF4, 0x09, 0x04, 0x03, 0x08, 0x07,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*痈3313*/},\n        {\n\n                0x00, 0xFE, 0x22, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xFA, 0x22, 0x04, 0x03, 0x00, 0x0F, 0x02,\n                0x02, 0x07, 0x02, 0x0A, 0x0F, 0x00,/*庸3314*/},\n        {\n\n                0xB2, 0x6E, 0x22, 0x9A, 0x22, 0xF3, 0x5E, 0x52, 0xF6, 0x5A, 0x52, 0x09, 0x05, 0x03, 0x01, 0x00,\n                0x0F, 0x05, 0x05, 0x07, 0x05, 0x05,/*雍3315*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x00, 0xF1, 0x55, 0xF9, 0x55, 0x53, 0xF0, 0x07, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x01, 0x07, 0x01, 0x09, 0x0F,/*踊3316*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xF1, 0x55, 0xF9, 0x57, 0xF0, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x01, 0x07, 0x09, 0x0F,/*蛹3317*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x20, 0xE9, 0x09, 0xFA, 0xC2, 0x20, 0x10, 0x03, 0x01, 0x03, 0x04, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x03, 0x04,/*咏3318*/},\n        {\n\n                0x22, 0x44, 0x20, 0x28, 0xE8, 0x09, 0xF9, 0x72, 0x82, 0x40, 0x20, 0x04, 0x02, 0x04, 0x03, 0x00,\n                0x08, 0x0F, 0x00, 0x01, 0x02, 0x04,/*泳3319*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0xF1, 0x51, 0x55, 0xF9, 0x55, 0x53, 0xF0, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*涌3320*/},\n        {\n\n                0x20, 0x20, 0xA4, 0x64, 0x05, 0xFD, 0x32, 0xC2, 0x40, 0x20, 0x10, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x04,/*永3321*/},\n        {\n\n                0x00, 0xFD, 0x55, 0x55, 0x57, 0xFD, 0x55, 0x57, 0x55, 0xFC, 0x00, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x0A, 0x0C, 0x08, 0x0D, 0x03, 0x0C,/*恿3322*/},\n        {\n\n                0x00, 0xFD, 0x55, 0x55, 0x57, 0xFD, 0x55, 0x57, 0x55, 0xFC, 0x00, 0x02, 0x0A, 0x0A, 0x06, 0x03,\n                0x02, 0x02, 0x0A, 0x0A, 0x06, 0x00,/*勇3323*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x07, 0x00, 0x08, 0x08, 0x0F, 0x00,/*用3324*/},\n        {\n\n                0xFC, 0x00, 0xB8, 0x66, 0x90, 0xFF, 0x00, 0xB8, 0x66, 0x90, 0xFC, 0x07, 0x04, 0x05, 0x05, 0x05,\n                0x07, 0x04, 0x05, 0x05, 0x05, 0x0F,/*幽3325*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x08, 0x08, 0xFF, 0x08, 0xF8, 0x09, 0x0A, 0x08, 0x00, 0x0F, 0x08, 0x04, 0x03,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*优3326*/},\n        {\n\n                0x10, 0x08, 0xFC, 0x03, 0x7C, 0x10, 0x8C, 0x57, 0x24, 0x5C, 0x84, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*悠3327*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0x08, 0xFF, 0x08, 0xF9, 0x0A, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*忧3328*/},\n        {\n\n                0x08, 0x08, 0x08, 0xE8, 0x1F, 0x08, 0xF8, 0x09, 0x0A, 0x08, 0x08, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*尤3329*/},\n        {\n\n                0x00, 0xFC, 0x44, 0x44, 0x44, 0xFF, 0x44, 0x44, 0x44, 0xFC, 0x00, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x07, 0x04, 0x04, 0x04, 0x0F, 0x00,/*由3330*/},\n        {\n\n                0xF8, 0x48, 0x48, 0xFF, 0x48, 0x48, 0xF8, 0x00, 0xFE, 0x32, 0xCE, 0x0F, 0x04, 0x04, 0x07, 0x04,\n                0x04, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*邮3331*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0xF8, 0x48, 0x48, 0xFF, 0x48, 0x48, 0xF8, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*铀3332*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x00, 0x08, 0xFF, 0x08, 0xF8, 0x09, 0x0A, 0x01, 0x08, 0x08, 0x07, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*犹3333*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xFC, 0x44, 0x44, 0xFF, 0x44, 0x44, 0xFC, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*油3334*/},\n        {\n\n                0x22, 0x44, 0x04, 0xFD, 0x26, 0xE4, 0x88, 0x97, 0xD4, 0xB4, 0x84, 0x04, 0x02, 0x08, 0x07, 0x08,\n                0x0F, 0x00, 0x08, 0x0F, 0x00, 0x00,/*游3335*/},\n        {\n\n                0x02, 0xFA, 0x8A, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0x4A, 0xFA, 0x02, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*酉3336*/},\n        {\n\n                0x44, 0x24, 0xF4, 0x5C, 0x57, 0x54, 0x54, 0x54, 0x54, 0xF4, 0x04, 0x00, 0x00, 0x0F, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x0F, 0x00,/*有3337*/},\n        {\n\n                0x04, 0x04, 0xC4, 0x3C, 0xE7, 0x24, 0x24, 0x24, 0xE4, 0x04, 0x04, 0x04, 0x03, 0x08, 0x08, 0x04,\n                0x05, 0x02, 0x05, 0x04, 0x08, 0x08,/*友3338*/},\n        {\n\n                0x04, 0x04, 0x84, 0xE4, 0x5C, 0x47, 0x44, 0x44, 0x44, 0xC4, 0x04, 0x02, 0x01, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*右3339*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x84, 0xC4, 0x74, 0x4F, 0x44, 0x44, 0xC4, 0x00, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*佑3340*/},\n        {\n\n                0x4A, 0x52, 0xFE, 0x51, 0x08, 0xF8, 0x48, 0xFF, 0x48, 0x48, 0xF8, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x0F, 0x04, 0x07, 0x04, 0x04, 0x0F,/*釉3341*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x28, 0x5A, 0xCA, 0x7E, 0x49, 0xD9, 0x28, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x06, 0x01, 0x00, 0x09, 0x09, 0x07,/*诱3342*/},\n        {\n\n                0x00, 0x02, 0x1E, 0x62, 0x82, 0x02, 0x82, 0x42, 0x32, 0x0E, 0x00, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x04, 0x08, 0x08,/*又3343*/},\n        {\n\n                0x30, 0xAC, 0x63, 0x30, 0x0C, 0x00, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x03, 0x02, 0x02, 0x03, 0x06,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*幼3344*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x20, 0x22, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x22, 0x08, 0x07, 0x08, 0x08, 0x08,\n                0x0A, 0x0A, 0x0B, 0x08, 0x08, 0x08,/*迂3345*/},\n        {\n\n                0x22, 0x44, 0x08, 0xF9, 0x4A, 0xC8, 0x10, 0x0C, 0x23, 0xCC, 0x10, 0x04, 0x02, 0x08, 0x07, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x0C, 0x00,/*淤3346*/},\n        {\n\n                0x20, 0x21, 0x21, 0x21, 0x21, 0xFF, 0x21, 0x21, 0x21, 0x21, 0x20, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*于3347*/},\n        {\n\n                0x08, 0x09, 0x09, 0x49, 0x49, 0x7F, 0x09, 0x09, 0x09, 0x09, 0x08, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盂3348*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xE8, 0xA4, 0xEA, 0x09, 0xCA, 0x04, 0xE8, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x02, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*榆3349*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x14, 0xD4, 0xBF, 0xB5, 0xAD, 0xE5, 0x35, 0x0C, 0x08, 0x07, 0x00, 0x0A, 0x0A,\n                0x06, 0x03, 0x06, 0x0A, 0x0A, 0x08,/*虞3350*/},\n        {\n\n                0xC0, 0x5F, 0x55, 0x55, 0x55, 0xFF, 0x55, 0xD5, 0x55, 0x5F, 0xC0, 0x09, 0x04, 0x00, 0x05, 0x0B,\n                0x0D, 0x09, 0x0D, 0x00, 0x05, 0x09,/*愚3351*/},\n        {\n\n                0x00, 0xFE, 0x49, 0x00, 0x5A, 0xF7, 0x52, 0x00, 0x49, 0xFF, 0x00, 0x01, 0x09, 0x05, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x05, 0x09, 0x01,/*舆3352*/},\n        {\n\n                0x10, 0x90, 0x88, 0x94, 0x92, 0xF1, 0x92, 0x94, 0x88, 0x90, 0x10, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*余3353*/},\n        {\n\n                0x08, 0xE8, 0xA4, 0xAC, 0xAA, 0xE9, 0x0A, 0xCC, 0x04, 0xE8, 0x08, 0x00, 0x0F, 0x02, 0x02, 0x0A,\n                0x0F, 0x00, 0x03, 0x08, 0x0F, 0x00,/*俞3354*/},\n        {\n\n                0x21, 0xE2, 0x08, 0xE8, 0xA4, 0xEA, 0x09, 0xCA, 0x04, 0xE8, 0x08, 0x08, 0x07, 0x08, 0x0F, 0x0A,\n                0x0F, 0x08, 0x09, 0x0C, 0x0F, 0x08,/*逾3355*/},\n        {\n\n                0x08, 0xFC, 0x4A, 0x4B, 0x4A, 0xFA, 0x4A, 0x4E, 0x48, 0xF8, 0x00, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*鱼3356*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xE8, 0xA4, 0xEA, 0x09, 0xCA, 0x04, 0xE8, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x02, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*愉3357*/},\n        {\n\n                0x10, 0x21, 0x02, 0xE8, 0xA4, 0xAA, 0xE9, 0x0A, 0xC4, 0x08, 0xE8, 0x04, 0x02, 0x01, 0x0F, 0x02,\n                0x0A, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*渝3358*/},\n        {\n\n                0x22, 0x44, 0x08, 0xFC, 0x4B, 0x4A, 0xFA, 0x4E, 0x48, 0xF8, 0x00, 0x04, 0x02, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x0A, 0x0B, 0x08,/*渔3359*/},\n        {\n\n                0xFF, 0x31, 0xCF, 0x00, 0x80, 0xBF, 0xA5, 0xFF, 0xA5, 0xBF, 0x80, 0x0F, 0x02, 0x01, 0x00, 0x0F,\n                0x00, 0x02, 0x03, 0x06, 0x08, 0x0F,/*隅3360*/},\n        {\n\n                0x20, 0x21, 0x21, 0x25, 0x25, 0xE9, 0x29, 0x35, 0x23, 0xA1, 0x60, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x01, 0x00, 0x00,/*予3361*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x2F, 0x29, 0xE9, 0x29, 0x2F, 0x00, 0x08, 0x05, 0x02, 0x05, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*娱3362*/},\n        {\n\n                0xF9, 0x09, 0x29, 0x49, 0x09, 0xFF, 0x09, 0x29, 0x49, 0x09, 0xF9, 0x0F, 0x00, 0x01, 0x02, 0x00,\n                0x07, 0x00, 0x01, 0x0A, 0x08, 0x0F,/*雨3363*/},\n        {\n\n                0x00, 0x38, 0x27, 0x24, 0x24, 0x24, 0x24, 0x24, 0x24, 0xE4, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x09, 0x09, 0x08, 0x07, 0x00,/*与3364*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0x30, 0x2F, 0x24, 0x24, 0xE4, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x07,/*屿3365*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xAA, 0xAA, 0xFE, 0xA9, 0xA9, 0xA9, 0xB9, 0x81, 0x0F, 0x00, 0x02, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x06, 0x08, 0x0F,/*禹3366*/},\n        {\n\n                0x1C, 0x04, 0x24, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x24, 0x04, 0x1C, 0x01, 0x01, 0x01, 0x09, 0x09,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*宇3367*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x21, 0xA5, 0xBD, 0xA7, 0xA5, 0xA5, 0xBD, 0x21, 0x00, 0x07, 0x02, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*语3368*/},\n        {\n\n                0x0A, 0x12, 0xA2, 0x02, 0xFE, 0x00, 0x0A, 0x12, 0xA2, 0x02, 0xFE, 0x02, 0x01, 0x08, 0x08, 0x0F,\n                0x00, 0x02, 0x01, 0x08, 0x08, 0x0F,/*羽3369*/},\n        {\n\n                0x00, 0x42, 0x42, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x42, 0x42, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x09, 0x0A, 0x08, 0x08,/*玉3370*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xF4, 0x94, 0xF4, 0x04, 0xFF, 0x84, 0x65, 0x04, 0x07, 0x02, 0x00, 0x04,\n                0x04, 0x0A, 0x04, 0x03, 0x05, 0x0E,/*域3371*/},\n        {\n\n                0x82, 0x92, 0x92, 0x97, 0x92, 0xF2, 0x92, 0x97, 0x92, 0x92, 0x82, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*芋3372*/},\n        {\n\n                0x24, 0xFC, 0x57, 0x54, 0x54, 0xF4, 0x04, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0F, 0x01, 0x01, 0x09,\n                0x0F, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郁3373*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x20, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x20, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*吁3374*/},\n        {\n\n                0x21, 0xE2, 0x00, 0xC0, 0x5F, 0x55, 0xFF, 0x55, 0xD5, 0x5F, 0xC0, 0x08, 0x07, 0x08, 0x0B, 0x08,\n                0x09, 0x09, 0x09, 0x09, 0x0A, 0x0B,/*遇3375*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xE8, 0xA4, 0xEA, 0x09, 0xCA, 0x04, 0xE8, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x02, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*喻3376*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xFC, 0x22, 0x91, 0x88, 0x91, 0xA2, 0x24, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*峪3377*/},\n        {\n\n                0x24, 0xF2, 0x09, 0xA4, 0x27, 0xFC, 0xA4, 0x20, 0xFE, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x07, 0x04,\n                0x03, 0x02, 0x00, 0x0F, 0x02, 0x03,/*御3378*/},\n        {\n\n                0x04, 0xF4, 0x52, 0x56, 0x55, 0xF5, 0x05, 0xE6, 0x02, 0xF4, 0x04, 0x08, 0x03, 0x05, 0x09, 0x0B,\n                0x0B, 0x0C, 0x08, 0x0E, 0x03, 0x08,/*愈3379*/},\n        {\n\n                0x44, 0xA2, 0x91, 0x8C, 0x91, 0xA2, 0x54, 0x0F, 0xC4, 0x14, 0x0C, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x0F, 0x08, 0x06, 0x01, 0x06, 0x08,/*欲3380*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x10, 0xF1, 0x02, 0x10, 0x10, 0xFF, 0x12, 0x14, 0x08, 0x08, 0x07, 0x00, 0x07,\n                0x02, 0x08, 0x07, 0x00, 0x07, 0x08,/*狱3381*/},\n        {\n\n                0x02, 0xEA, 0xAE, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAE, 0xFA, 0x02, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*育3382*/},\n        {\n\n                0x24, 0x95, 0xAE, 0xA4, 0xA5, 0xB6, 0xA4, 0xA4, 0xAE, 0x95, 0x24, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*誉3383*/},\n        {\n\n                0x11, 0x22, 0x04, 0xA2, 0x91, 0x88, 0x84, 0x88, 0x91, 0xA2, 0x24, 0x04, 0x02, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*浴3384*/},\n        {\n\n                0x06, 0xFA, 0xAA, 0xAA, 0xAA, 0xFB, 0xAA, 0xAA, 0xAA, 0xFA, 0x06, 0x0E, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0E, 0x02, 0x0A, 0x0E,/*寓3385*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0x44, 0xA2, 0x91, 0x8C, 0x91, 0xA2, 0x44, 0x00, 0x0F, 0x00, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*裕3386*/},\n        {\n\n                0x20, 0x2A, 0xF2, 0x2E, 0x60, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*预3387*/},\n        {\n\n                0x4A, 0x52, 0xEA, 0x46, 0xC8, 0xBC, 0x6B, 0xFA, 0xAE, 0x2A, 0xB8, 0x00, 0x08, 0x0F, 0x00, 0x0A,\n                0x0A, 0x05, 0x0A, 0x0F, 0x03, 0x04,/*豫3388*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x02, 0x3E, 0xC2, 0x02, 0xC2, 0x3E, 0x00, 0x02, 0x0A, 0x09, 0x07, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*驭3389*/},\n        {\n\n                0x44, 0x2A, 0xF3, 0x2A, 0x76, 0xA0, 0x2F, 0xB1, 0xF5, 0x17, 0x18, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x01, 0x09, 0x0F,/*鸳3390*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xFF, 0x24, 0xA8, 0xFE, 0xA8, 0x24, 0xFF, 0x04, 0x02, 0x09, 0x06, 0x01,\n                0x01, 0x00, 0x07, 0x00, 0x01, 0x0F,/*渊3391*/},\n        {\n\n                0x46, 0x22, 0xF2, 0xAE, 0xAA, 0xEA, 0xAA, 0xBA, 0xA2, 0xE2, 0x06, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x0A, 0x08, 0x0E,/*冤3392*/},\n        {\n\n                0x20, 0x22, 0x22, 0xE2, 0x22, 0x22, 0x22, 0xE2, 0x22, 0x22, 0x20, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*元3393*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x02, 0xFA, 0x4A, 0x4A, 0x4A, 0x4A, 0xFA, 0x02, 0x04, 0x07, 0x02, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*垣3394*/},\n        {\n\n                0x08, 0xEA, 0xAA, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0xAA, 0xEA, 0x08, 0x04, 0x04, 0x02, 0x0F, 0x08,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*袁3395*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xFA, 0xAA, 0xAE, 0xAA, 0xAA, 0xAA, 0xFA, 0x02, 0x08, 0x07, 0x08, 0x04, 0x02,\n                0x08, 0x0F, 0x00, 0x02, 0x04, 0x08,/*原3396*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x56, 0x5A, 0xD6, 0x7A, 0x52, 0x59, 0x55, 0x08, 0x0F, 0x00, 0x04, 0x0A,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*援3397*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x08, 0xEA, 0xAA, 0xAF, 0xAA, 0xAA, 0xEA, 0x01, 0x01, 0x0F, 0x00, 0x04,\n                0x02, 0x0F, 0x08, 0x03, 0x04, 0x0A,/*辕3398*/},\n        {\n\n                0x00, 0xFF, 0x21, 0x25, 0xE5, 0x25, 0xE5, 0x25, 0x21, 0x01, 0xFF, 0x00, 0x0F, 0x0A, 0x09, 0x08,\n                0x08, 0x09, 0x0A, 0x0B, 0x08, 0x0F,/*园3399*/},\n        {\n\n                0x00, 0xF0, 0x17, 0x15, 0x15, 0xD5, 0x15, 0x15, 0x17, 0xF0, 0x00, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*员3400*/},\n        {\n\n                0xFF, 0x01, 0xC1, 0x5D, 0x55, 0xD5, 0x55, 0x5D, 0xC1, 0x01, 0xFF, 0x0F, 0x08, 0x09, 0x0C, 0x0A,\n                0x09, 0x0A, 0x0C, 0x09, 0x08, 0x0F,/*圆3401*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x08, 0xEA, 0xAA, 0xAF, 0xAA, 0xAA, 0xEA, 0x08, 0x08, 0x08, 0x07, 0x04, 0x02,\n                0x0F, 0x08, 0x03, 0x04, 0x0A, 0x09,/*猿3402*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFF, 0x01, 0xF9, 0xAD, 0xAB, 0xA9, 0xF9, 0x01, 0x04, 0x02, 0x08, 0x07, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*源3403*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xAC, 0x6B, 0xAA, 0x2A, 0x3A, 0xA6, 0x20, 0x04, 0x04, 0x02, 0x08, 0x0A,\n                0x05, 0x0A, 0x0F, 0x01, 0x06, 0x08,/*缘3404*/},\n        {\n\n                0x21, 0xE2, 0x00, 0x10, 0x12, 0xF2, 0x12, 0x12, 0xF2, 0x12, 0x10, 0x08, 0x07, 0x08, 0x0A, 0x09,\n                0x08, 0x08, 0x08, 0x09, 0x0A, 0x0B,/*远3405*/},\n        {\n\n                0x82, 0x62, 0x9A, 0x17, 0xF2, 0x02, 0xF2, 0x17, 0x12, 0xF2, 0x02, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x07, 0x08, 0x09, 0x09, 0x0C,/*苑3406*/},\n        {\n\n                0x00, 0xFF, 0x01, 0x7D, 0xD5, 0x57, 0xD5, 0x55, 0xD5, 0x7D, 0x01, 0x08, 0x07, 0x08, 0x05, 0x00,\n                0x0D, 0x09, 0x0A, 0x0C, 0x01, 0x0C,/*愿3407*/},\n        {\n\n                0x90, 0x88, 0x57, 0x24, 0x1C, 0x00, 0x7E, 0x82, 0x92, 0x9E, 0xC0, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*怨3408*/},\n        {\n\n                0xFE, 0x12, 0xEE, 0x00, 0x8C, 0xA4, 0xA5, 0xA6, 0xA4, 0xA4, 0x8C, 0x0F, 0x01, 0x00, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*院3409*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x02, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*曰3410*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0x08, 0x27, 0xC4, 0x04, 0x04, 0xFC, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*约3411*/},\n        {\n\n                0xA4, 0x24, 0xFF, 0x24, 0x00, 0xFC, 0x44, 0x24, 0xFF, 0x44, 0xB5, 0x0F, 0x04, 0x0F, 0x09, 0x08,\n                0x08, 0x0A, 0x09, 0x08, 0x09, 0x0B,/*越3412*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*跃3413*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x08, 0x07, 0x00, 0x08, 0x08, 0x0F,/*钥3414*/},\n        {\n\n                0x80, 0x80, 0xFE, 0x92, 0x92, 0x92, 0x91, 0xF1, 0x91, 0x90, 0x80, 0x00, 0x0E, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0E, 0x00,/*岳3415*/},\n        {\n\n                0x80, 0xFE, 0x92, 0xDA, 0x93, 0xFE, 0x92, 0xDA, 0x92, 0xFE, 0x80, 0x00, 0x00, 0x03, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0A, 0x06, 0x00,/*粤3416*/},\n        {\n\n                0x00, 0x00, 0xFE, 0x92, 0x92, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x08, 0x06, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x0F, 0x00,/*月3417*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0x79, 0xCA, 0x48, 0xCA, 0x79, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*悦3418*/},\n        {\n\n                0xF9, 0x02, 0xF0, 0x95, 0x99, 0x91, 0x99, 0x95, 0xF1, 0x01, 0xFF, 0x0F, 0x00, 0x04, 0x02, 0x01,\n                0x00, 0x03, 0x04, 0x06, 0x08, 0x0F,/*阅3419*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x44, 0x20, 0xA2, 0x62, 0x22, 0x22, 0x20, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*耘3420*/},\n        {\n\n                0x20, 0x20, 0x22, 0x22, 0xA2, 0x62, 0x22, 0x22, 0x22, 0x20, 0x20, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x05, 0x06, 0x0C, 0x00,/*云3421*/},\n        {\n\n                0xF0, 0x17, 0x15, 0xD5, 0x15, 0x17, 0xF0, 0x00, 0xFF, 0x31, 0xCF, 0x09, 0x04, 0x02, 0x01, 0x02,\n                0x04, 0x09, 0x00, 0x0F, 0x02, 0x01,/*郧3422*/},\n        {\n\n                0x20, 0x18, 0x07, 0x14, 0x64, 0x04, 0x84, 0x84, 0x04, 0xFC, 0x00, 0x00, 0x02, 0x02, 0x02, 0x01,\n                0x01, 0x08, 0x08, 0x08, 0x07, 0x00,/*匀3423*/},\n        {\n\n                0xFF, 0x31, 0xCF, 0x00, 0xF0, 0x17, 0x15, 0xD5, 0x15, 0x17, 0xF0, 0x0F, 0x02, 0x01, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*陨3424*/},\n        {\n\n                0x10, 0x18, 0x14, 0xF2, 0x11, 0x10, 0x10, 0xF0, 0x14, 0x18, 0x30, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*允3425*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x10, 0x92, 0x52, 0x32, 0x12, 0x92, 0x10, 0x08, 0x04, 0x03, 0x04, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x0B,/*运3426*/},\n        {\n\n                0xB2, 0x6A, 0x22, 0x17, 0xFA, 0xAA, 0xAA, 0xAF, 0xFA, 0x02, 0x02, 0x05, 0x05, 0x09, 0x0E, 0x0A,\n                0x0E, 0x0A, 0x0E, 0x0A, 0x0E, 0x08,/*蕴3427*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x20, 0xE2, 0x22, 0x20, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x06, 0x05, 0x04, 0x0E,/*酝3428*/},\n        {\n\n                0x30, 0x50, 0x5F, 0xD5, 0x75, 0xD5, 0x55, 0x55, 0x5F, 0x50, 0x30, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x05, 0x04, 0x04,/*晕3429*/},\n        {\n\n                0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x10, 0x08, 0x17, 0x24, 0x84, 0xFC, 0x0F, 0x0A, 0x0A, 0x0A, 0x0F,\n                0x00, 0x02, 0x02, 0x09, 0x08, 0x07,/*韵3430*/},\n        {\n\n                0x41, 0x31, 0x0F, 0x11, 0x11, 0xD1, 0x31, 0x07, 0x44, 0x7C, 0x00, 0x01, 0x01, 0x01, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*孕3431*/},\n        {\n\n                0x00, 0xFF, 0x01, 0xF9, 0x09, 0x09, 0xFF, 0x09, 0x09, 0xF9, 0x01, 0x00, 0x0F, 0x08, 0x09, 0x08,\n                0x08, 0x0F, 0x08, 0x09, 0x09, 0x08,/*匝3432*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0x02, 0xF2, 0x12, 0xFE, 0x12, 0xF2, 0x07, 0x02, 0x07, 0x00, 0x0F,\n                0x08, 0x09, 0x08, 0x0F, 0x09, 0x09,/*砸3433*/},\n        {\n\n                0x80, 0xA4, 0x94, 0x8C, 0x87, 0xE4, 0x84, 0x9C, 0xA0, 0xA0, 0xB0, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*杂3434*/},\n        {\n\n                0x48, 0x4A, 0x4A, 0xEF, 0x4A, 0x4A, 0x08, 0xFF, 0x08, 0xE9, 0x0A, 0x04, 0x02, 0x01, 0x0F, 0x01,\n                0x02, 0x08, 0x04, 0x03, 0x04, 0x0E,/*栽3435*/},\n        {\n\n                0x10, 0x92, 0x92, 0x9F, 0x92, 0x92, 0x10, 0xFF, 0x10, 0x92, 0x54, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x0F, 0x04, 0x03, 0x05, 0x08, 0x0E,/*哉3436*/},\n        {\n\n                0x0C, 0x84, 0x64, 0x04, 0x85, 0x76, 0x84, 0x04, 0x84, 0x64, 0x0C, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*灾3437*/},\n        {\n\n                0x86, 0x92, 0xB2, 0xD2, 0x96, 0x9B, 0x92, 0xD2, 0xB2, 0x92, 0x86, 0x00, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x00,/*宰3438*/},\n        {\n\n                0x28, 0xEA, 0xBA, 0xEF, 0xAA, 0xAA, 0x08, 0xFF, 0x08, 0xE9, 0x0A, 0x04, 0x04, 0x04, 0x0F, 0x02,\n                0x02, 0x08, 0x04, 0x03, 0x04, 0x0E,/*载3439*/},\n        {\n\n                0x01, 0xFD, 0x25, 0x25, 0x25, 0xFF, 0x25, 0x25, 0x25, 0xFD, 0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x0F, 0x01,/*再3440*/},\n        {\n\n                0x84, 0x44, 0xE4, 0x1C, 0x07, 0x84, 0x84, 0xF4, 0x84, 0x84, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*在3441*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x00, 0xFC, 0x26, 0x25, 0x24, 0x24, 0xFC, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x0F,/*咱3442*/},\n        {\n\n                0x84, 0xFF, 0x44, 0xAB, 0x9A, 0x8F, 0xBA, 0xAB, 0x9A, 0xBF, 0x2A, 0x08, 0x0F, 0x00, 0x0B, 0x08,\n                0x04, 0x03, 0x04, 0x04, 0x0B, 0x00,/*攒3443*/},\n        {\n\n                0x22, 0x2E, 0xAB, 0xFE, 0xAA, 0xC0, 0xBE, 0x8A, 0x89, 0x79, 0x08, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*暂3444*/},\n        {\n\n                0x44, 0xAB, 0x9A, 0xFF, 0xAA, 0xC4, 0xAB, 0x9A, 0xBF, 0xCA, 0x6A, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*赞3445*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0xFC, 0x45, 0xF6, 0x44, 0x44, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x07, 0x08, 0x0F, 0x08, 0x08,/*赃3446*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFC, 0x44, 0x45, 0xF6, 0x44, 0x44, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x07, 0x08, 0x08, 0x0F, 0x08, 0x08,/*脏3447*/},\n        {\n\n                0x4A, 0x6A, 0xBA, 0xAF, 0x6A, 0x0A, 0x7A, 0xAF, 0xAA, 0x9A, 0xCA, 0x01, 0x03, 0x0A, 0x07, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x00,/*葬3448*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFA, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFA, 0x02, 0x08, 0x07, 0x08, 0x08, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x08, 0x08,/*遭3449*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0xFA, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFA, 0x01, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*糟3450*/},\n        {\n\n                0x08, 0xEA, 0x0C, 0x58, 0x6F, 0xC8, 0x6F, 0x58, 0x0C, 0xEA, 0x08, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x0F, 0x00,/*凿3451*/},\n        {\n\n                0x4A, 0x92, 0x02, 0xE7, 0xBA, 0xEA, 0x2A, 0xEF, 0xBA, 0xE2, 0x02, 0x08, 0x04, 0x00, 0x0A, 0x06,\n                0x02, 0x0F, 0x02, 0x06, 0x0A, 0x02,/*藻3452*/},\n        {\n\n                0x82, 0xBA, 0x4A, 0x2A, 0x9A, 0xBF, 0x1A, 0x2A, 0x4A, 0xBA, 0x82, 0x00, 0x00, 0x00, 0x02, 0x02,\n                0x04, 0x05, 0x08, 0x00, 0x00, 0x00,/*枣3453*/},\n        {\n\n                0x00, 0x3F, 0x25, 0x25, 0x25, 0xE5, 0x25, 0x25, 0x25, 0x3F, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*早3454*/},\n        {\n\n                0x10, 0x21, 0x72, 0x50, 0x57, 0x75, 0x85, 0x75, 0x57, 0x50, 0x70, 0x04, 0x02, 0x09, 0x05, 0x03,\n                0x01, 0x0F, 0x01, 0x03, 0x05, 0x09,/*澡3455*/},\n        {\n\n                0x20, 0x21, 0xD3, 0x55, 0x49, 0xEB, 0x49, 0x55, 0xD3, 0x21, 0x20, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x07, 0x05, 0x05, 0x05, 0x06, 0x0C,/*蚤3456*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x70, 0x57, 0x75, 0x85, 0x75, 0x57, 0x70, 0x07, 0x04, 0x03, 0x02, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*躁3457*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x70, 0x57, 0x75, 0x85, 0x75, 0x57, 0x70, 0x03, 0x01, 0x03, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*噪3458*/},\n        {\n\n                0x11, 0xF2, 0x28, 0xA6, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0xA4, 0x20, 0x08, 0x07, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*造3459*/},\n        {\n\n                0x00, 0x7C, 0x54, 0x54, 0xD6, 0x55, 0x54, 0x54, 0x54, 0x7C, 0x00, 0x02, 0x02, 0x02, 0x02, 0x07,\n                0x0A, 0x09, 0x09, 0x09, 0x09, 0x0D,/*皂3460*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x00, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*灶3461*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x70, 0x57, 0x75, 0x85, 0x75, 0x57, 0x70, 0x08, 0x06, 0x01, 0x06, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*燥3462*/},\n        {\n\n                0x22, 0xAA, 0xAA, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xAA, 0xAA, 0x22, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*责3463*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x21, 0xA3, 0x95, 0xE9, 0x95, 0xA3, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*择3464*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFA, 0x02, 0x02, 0xFE, 0x00, 0xFC, 0x00, 0xFF, 0x09, 0x04, 0x02, 0x01, 0x02,\n                0x04, 0x09, 0x00, 0x01, 0x08, 0x0F,/*则3465*/},\n        {\n\n                0x21, 0x42, 0x20, 0xA1, 0x93, 0x95, 0xE9, 0x95, 0x93, 0xA1, 0x20, 0x08, 0x04, 0x02, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*泽3466*/},\n        {\n\n                0xFF, 0x01, 0xF9, 0x01, 0xFF, 0x44, 0xF4, 0x44, 0xFF, 0x84, 0x65, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x02, 0x09, 0x04, 0x03, 0x04, 0x0E,/*贼3467*/},\n        {\n\n                0x08, 0x04, 0x03, 0xFE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x22, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*怎3468*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x3E, 0xAB, 0xA2, 0xBE, 0xA2, 0xAB, 0x3E, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*增3469*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x3E, 0xAB, 0xA2, 0xBE, 0xA2, 0xAB, 0x3E, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*憎3470*/},\n        {\n\n                0x3C, 0xA4, 0xAD, 0xB6, 0xA4, 0xBC, 0xA4, 0xB6, 0xAD, 0xA4, 0x3C, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*曾3471*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0xAB, 0xA2, 0xBE, 0xA2, 0xAB, 0x3E, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*赠3472*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x48, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0F,/*扎3473*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x12, 0xEA, 0xA6, 0xBF, 0xA6, 0xEA, 0x12, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*喳3474*/},\n        {\n\n                0x22, 0x44, 0x20, 0x14, 0xEC, 0xA4, 0xBF, 0xA4, 0xEC, 0x14, 0x24, 0x04, 0x02, 0x08, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0B, 0x08, 0x08,/*渣3475*/},\n        {\n\n                0x08, 0x88, 0x68, 0xFF, 0x28, 0x48, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0F,/*札3476*/},\n        {\n\n                0x04, 0x64, 0x5C, 0xE7, 0x44, 0x44, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x02, 0x02, 0x02, 0x0F, 0x01,\n                0x01, 0x00, 0x07, 0x08, 0x08, 0x0E,/*轧3477*/},\n        {\n\n                0x94, 0xF3, 0x92, 0xFE, 0xC2, 0x02, 0xFE, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x07, 0x0A, 0x04, 0x03,\n                0x04, 0x08, 0x00, 0x01, 0x08, 0x0F,/*铡3478*/},\n        {\n\n                0xF9, 0x02, 0xF8, 0xA9, 0xA9, 0xF9, 0xA9, 0xA9, 0xF9, 0x01, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00,\n                0x07, 0x00, 0x00, 0x00, 0x08, 0x0F,/*闸3479*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x00, 0x22, 0x22, 0x2A, 0xB1, 0x61, 0x21, 0x0F, 0x04, 0x04, 0x07, 0x08,\n                0x04, 0x02, 0x05, 0x08, 0x08, 0x08,/*眨3480*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0xFE, 0x22, 0xFE, 0x20, 0xFE, 0x22, 0xFE, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x08, 0x0F, 0x08, 0x07, 0x08, 0x0F,/*栅3481*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x96, 0x4A, 0xF6, 0xA3, 0xA6, 0xAA, 0x16, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x02, 0x02, 0x02, 0x02,/*榨3482*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*咋3483*/},\n        {\n\n                0x20, 0x18, 0x07, 0x04, 0xFC, 0x24, 0x24, 0x24, 0x24, 0x24, 0x04, 0x00, 0x00, 0x00, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x01, 0x01, 0x01,/*乍3484*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x10, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*炸3485*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*诈3486*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xF2, 0x16, 0x5A, 0xF3, 0x5A, 0x16, 0xF2, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x00, 0x07, 0x05, 0x07, 0x08, 0x0F,/*摘3487*/},\n        {\n\n                0x12, 0x52, 0x52, 0x56, 0x4A, 0xCB, 0x4A, 0x56, 0x52, 0x52, 0x12, 0x00, 0x0F, 0x01, 0x01, 0x07,\n                0x01, 0x07, 0x01, 0x09, 0x0F, 0x00,/*斋3488*/},\n        {\n\n                0x0C, 0x24, 0x24, 0x24, 0x25, 0xE6, 0x94, 0x94, 0x94, 0x94, 0x8C, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*宅3489*/},\n        {\n\n                0x86, 0x4A, 0x26, 0x3A, 0xE2, 0xA3, 0xA2, 0xA2, 0xA6, 0xAA, 0x26, 0x00, 0x00, 0x00, 0x00, 0x0F,\n                0x02, 0x02, 0x02, 0x02, 0x02, 0x02,/*窄3490*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xA2, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xA2, 0x00, 0x00, 0x0F, 0x00, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*债3491*/},\n        {\n\n                0x86, 0xAA, 0xAA, 0xFE, 0xAA, 0xAB, 0xAA, 0xFE, 0xAA, 0xAA, 0x86, 0x04, 0x02, 0x0B, 0x06, 0x0A,\n                0x0F, 0x02, 0x06, 0x0B, 0x02, 0x04,/*寨3492*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x15, 0xAD, 0xB5, 0xA7, 0xAC, 0x14, 0x0F, 0x04, 0x0F, 0x08, 0x07,\n                0x00, 0x0E, 0x0A, 0x0A, 0x0E, 0x00,/*瞻3493*/},\n        {\n\n                0x12, 0x12, 0xFE, 0x89, 0x00, 0xE0, 0x20, 0x3F, 0x24, 0xE4, 0x04, 0x01, 0x01, 0x07, 0x08, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*毡3494*/},\n        {\n\n                0x04, 0xFE, 0x25, 0x95, 0xAD, 0xA5, 0xB5, 0xA5, 0xAF, 0x94, 0x24, 0x08, 0x07, 0x00, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*詹3495*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x24, 0xC0, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*粘3496*/},\n        {\n\n                0x10, 0x21, 0x02, 0xC0, 0x40, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x08, 0x04, 0x02, 0x01, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*沾3497*/},\n        {\n\n                0x14, 0x54, 0x54, 0x54, 0x57, 0x5A, 0x2A, 0x6B, 0x9A, 0x8A, 0xC0, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盏3498*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x02, 0x02, 0x0F, 0x01, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x00, 0x00,/*斩3499*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xFA, 0xAE, 0x02, 0x02, 0x0F, 0x09, 0x07,\n                0x00, 0x0F, 0x04, 0x03, 0x04, 0x0A,/*辗3500*/},\n        {\n\n                0xD0, 0xB6, 0x9C, 0xD4, 0x94, 0x07, 0xF4, 0x94, 0x94, 0x8E, 0x88, 0x04, 0x04, 0x04, 0x0F, 0x02,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*崭3501*/},\n        {\n\n                0x00, 0xFF, 0x45, 0xD5, 0x7D, 0x55, 0xD5, 0x55, 0x7D, 0x55, 0x47, 0x08, 0x07, 0x00, 0x0F, 0x08,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*展3502*/},\n        {\n\n                0xEA, 0xAA, 0x7A, 0xAF, 0xEA, 0x12, 0xFA, 0x57, 0xFA, 0x52, 0x52, 0x0F, 0x0A, 0x0A, 0x0A, 0x0F,\n                0x00, 0x0D, 0x01, 0x0D, 0x01, 0x0D,/*蘸3503*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0x48, 0x48, 0xFF, 0x24, 0xA5, 0x26, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x04, 0x03, 0x05, 0x08, 0x0E,/*栈3504*/},\n        {\n\n                0x00, 0xC0, 0x40, 0x40, 0x40, 0x7F, 0x48, 0x48, 0x48, 0xC8, 0x08, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*占3505*/},\n        {\n\n                0xE0, 0x20, 0x3F, 0x24, 0xE4, 0x10, 0x10, 0xFF, 0x08, 0xE9, 0x0A, 0x07, 0x02, 0x02, 0x02, 0x03,\n                0x08, 0x04, 0x02, 0x03, 0x04, 0x0E,/*战3506*/},\n        {\n\n                0x28, 0xC9, 0x0A, 0xE8, 0x08, 0xC0, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*站3507*/},\n        {\n\n                0x11, 0x22, 0x80, 0x82, 0xFF, 0xAA, 0xAA, 0xAA, 0xFF, 0x82, 0x80, 0x04, 0x02, 0x00, 0x0F, 0x0A,\n                0x09, 0x08, 0x09, 0x0A, 0x08, 0x00,/*湛3508*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x2C, 0xA4, 0x24, 0xE5, 0x26, 0x24, 0x2C, 0x04, 0x04, 0x02, 0x0A, 0x04,\n                0x03, 0x04, 0x0F, 0x09, 0x09, 0x08,/*绽3509*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*樟3510*/},\n        {\n\n                0x08, 0x0A, 0xFA, 0xAE, 0xAA, 0xAB, 0xAA, 0xAE, 0xFA, 0x0A, 0x08, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*章3511*/},\n        {\n\n                0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x08, 0x88, 0x44, 0x23, 0x18, 0x02, 0x02, 0x02, 0x0F, 0x02,\n                0x02, 0x0A, 0x08, 0x04, 0x02, 0x01,/*彰3512*/},\n        {\n\n                0x11, 0x22, 0x08, 0xFA, 0xAE, 0xAA, 0xAB, 0xAA, 0xAE, 0xFA, 0x08, 0x04, 0x02, 0x02, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*漳3513*/},\n        {\n\n                0xF2, 0x92, 0x92, 0x9E, 0x00, 0x20, 0xFF, 0x28, 0xE4, 0x22, 0x20, 0x00, 0x08, 0x08, 0x07, 0x00,\n                0x00, 0x0F, 0x04, 0x00, 0x03, 0x04,/*张3514*/},\n        {\n\n                0x06, 0x42, 0x43, 0x5E, 0x56, 0xD7, 0x56, 0x5E, 0x43, 0x02, 0x06, 0x04, 0x04, 0x05, 0x05, 0x0D,\n                0x0F, 0x05, 0x05, 0x05, 0x04, 0x04,/*掌3515*/},\n        {\n\n                0x22, 0x44, 0xF2, 0x92, 0x9E, 0x20, 0xFF, 0x28, 0xE4, 0x22, 0x20, 0x04, 0x02, 0x08, 0x08, 0x07,\n                0x00, 0x0F, 0x04, 0x00, 0x03, 0x04,/*涨3516*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0x68, 0x88, 0x08, 0xFF, 0x08, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*杖3517*/},\n        {\n\n                0x08, 0x08, 0x68, 0x88, 0x08, 0x08, 0x88, 0x7F, 0x08, 0x08, 0x08, 0x00, 0x08, 0x08, 0x04, 0x05,\n                0x02, 0x05, 0x04, 0x08, 0x08, 0x08,/*丈3518*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x20, 0xFF, 0x28, 0xE4, 0x22, 0x20, 0x01, 0x00, 0x0F, 0x01, 0x01,\n                0x00, 0x0F, 0x04, 0x00, 0x03, 0x04,/*帐3519*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x20, 0xFF, 0x28, 0xE4, 0x22, 0x20, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x0F, 0x04, 0x00, 0x03, 0x04,/*账3520*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x28, 0xC8, 0x08, 0x88, 0x7F, 0x08, 0x08, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*仗3521*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x00, 0x20, 0xFF, 0x28, 0xE4, 0x22, 0x20, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x00, 0x0F, 0x04, 0x00, 0x03, 0x04,/*胀3522*/},\n        {\n\n                0x88, 0xFE, 0x22, 0xEA, 0xBA, 0xAA, 0xAF, 0xAA, 0xBA, 0xEA, 0x22, 0x08, 0x07, 0x02, 0x03, 0x02,\n                0x02, 0x0E, 0x02, 0x02, 0x03, 0x02,/*瘴3523*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x08, 0x0F, 0x02, 0x02, 0x01, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*障3524*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x22, 0x92, 0x8E, 0x82, 0xA2, 0xA2, 0x9E, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*招3525*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x20, 0x92, 0x8E, 0x82, 0xA2, 0xA2, 0x9E, 0x07, 0x02, 0x02, 0x07, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*昭3526*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x48, 0x10, 0xFF, 0x08, 0x89, 0x6A, 0x08, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x0F,/*找3527*/},\n        {\n\n                0x22, 0x44, 0x00, 0x42, 0xB2, 0x8E, 0x82, 0x82, 0xA2, 0xA2, 0x9E, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*沼3528*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xFF, 0x24, 0x20, 0x02, 0x9C, 0x60, 0x98, 0x06, 0x08, 0x07, 0x04, 0x0F, 0x09,\n                0x09, 0x0A, 0x09, 0x08, 0x08, 0x0B,/*赵3529*/},\n        {\n\n                0xFE, 0x12, 0x12, 0xFE, 0x20, 0xD2, 0x4E, 0x42, 0x52, 0x52, 0xCE, 0x09, 0x05, 0x01, 0x05, 0x08,\n                0x01, 0x05, 0x09, 0x01, 0x05, 0x09,/*照3530*/},\n        {\n\n                0x00, 0xC7, 0x45, 0x45, 0x47, 0x7D, 0x57, 0x55, 0x55, 0xD7, 0x00, 0x04, 0x07, 0x05, 0x05, 0x05,\n                0x0D, 0x05, 0x05, 0x05, 0x07, 0x04,/*罩3531*/},\n        {\n\n                0x04, 0x88, 0x50, 0xFF, 0x00, 0x00, 0xFF, 0x50, 0x88, 0x04, 0x00, 0x01, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*兆3532*/},\n        {\n\n                0x20, 0x5E, 0x4A, 0x4B, 0x4E, 0xE4, 0x53, 0x56, 0xEA, 0x56, 0x52, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x05, 0x04, 0x04,/*肇3533*/},\n        {\n\n                0x40, 0x22, 0x92, 0x8E, 0x82, 0x82, 0x82, 0xA2, 0xA2, 0x9E, 0x00, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*召3534*/},\n        {\n\n                0x21, 0xE2, 0x00, 0xFE, 0x12, 0x7A, 0x52, 0x53, 0x52, 0x7A, 0x12, 0x08, 0x07, 0x09, 0x08, 0x0B,\n                0x08, 0x0B, 0x08, 0x0B, 0x08, 0x0B,/*遮3535*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x08, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x00, 0x00,/*折3536*/},\n        {\n\n                0x12, 0x52, 0x7F, 0x0A, 0x40, 0x3E, 0x0A, 0x0A, 0x7A, 0x09, 0x08, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x00,/*哲3537*/},\n        {\n\n                0x0A, 0xAA, 0xBF, 0x8A, 0xA0, 0xDA, 0x8F, 0x92, 0x8E, 0x90, 0x38, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*蛰3538*/},\n        {\n\n                0x74, 0x4F, 0xF4, 0x4A, 0xEE, 0xAB, 0xEE, 0x12, 0xEC, 0x0B, 0xF8, 0x02, 0x02, 0x0F, 0x01, 0x0F,\n                0x02, 0x0F, 0x08, 0x04, 0x03, 0x0C,/*辙3539*/},\n        {\n\n                0x90, 0x94, 0xD4, 0x54, 0x74, 0x5F, 0x54, 0x5C, 0x54, 0xD2, 0x10, 0x00, 0x00, 0x0F, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*者3540*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD4, 0x12, 0x00, 0x0F, 0x04, 0x01, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*锗3541*/},\n        {\n\n                0x02, 0xF2, 0x52, 0x57, 0xF2, 0x56, 0x5A, 0x57, 0xF2, 0x52, 0x52, 0x08, 0x07, 0x08, 0x04, 0x01,\n                0x05, 0x09, 0x05, 0x09, 0x04, 0x08,/*蔗3542*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x04, 0x14, 0xA5, 0x46, 0xA4, 0x1C, 0x04, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x09, 0x08, 0x08, 0x08, 0x09, 0x0A,/*这3543*/},\n        {\n\n                0x11, 0x22, 0x88, 0x88, 0xFF, 0x48, 0x00, 0xFE, 0x12, 0xF2, 0x11, 0x04, 0x02, 0x00, 0x08, 0x0F,\n                0x00, 0x08, 0x07, 0x00, 0x0F, 0x00,/*浙3544*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x10, 0x48, 0x24, 0x93, 0x44, 0x08, 0x90, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x09, 0x05, 0x04, 0x02, 0x01, 0x00,/*珍3545*/},\n        {\n\n                0x80, 0x82, 0xFF, 0xAA, 0xAA, 0xFF, 0x82, 0x12, 0x24, 0xFF, 0x80, 0x00, 0x0F, 0x0A, 0x09, 0x08,\n                0x09, 0x0A, 0x01, 0x01, 0x0F, 0x00,/*斟3546*/},\n        {\n\n                0x00, 0x02, 0xFA, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0xFA, 0x02, 0x00, 0x02, 0x02, 0x0B, 0x06, 0x02,\n                0x02, 0x02, 0x06, 0x0B, 0x02, 0x02,/*真3547*/},\n        {\n\n                0x7A, 0x4A, 0x7E, 0xCA, 0x7E, 0x4A, 0x78, 0xE2, 0x9E, 0xF2, 0x02, 0x08, 0x09, 0x09, 0x07, 0x05,\n                0x05, 0x00, 0x0F, 0x08, 0x07, 0x08,/*甄3548*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xC0, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x00, 0x0F, 0x04, 0x0F, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*砧3549*/},\n        {\n\n                0x3A, 0xE6, 0x32, 0x00, 0xA2, 0x6A, 0xBA, 0xAF, 0xAA, 0x6A, 0xA2, 0x09, 0x0F, 0x05, 0x00, 0x0A,\n                0x06, 0x02, 0x0F, 0x02, 0x06, 0x0A,/*臻3550*/},\n        {\n\n                0x00, 0xF0, 0x10, 0x10, 0x10, 0xDF, 0x14, 0x14, 0x14, 0xF4, 0x04, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*贞3551*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x20, 0x20, 0xFF, 0x20, 0x20, 0x20, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*针3552*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xF0, 0x10, 0x10, 0xDF, 0x14, 0x14, 0xF4, 0x04, 0x00, 0x0F, 0x00, 0x09, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x09, 0x00,/*侦3553*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x9C, 0x04, 0xC4, 0x3F, 0xC4, 0x04, 0x1C, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0C,/*枕3554*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x22, 0x52, 0x4A, 0x27, 0xAA, 0x92, 0x22, 0x22, 0x09, 0x04, 0x03, 0x08, 0x09,\n                0x09, 0x09, 0x04, 0x04, 0x02, 0x00,/*疹3555*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x10, 0x48, 0x24, 0x93, 0x44, 0x08, 0x90, 0x10, 0x00, 0x07, 0x02, 0x08, 0x09,\n                0x05, 0x04, 0x02, 0x01, 0x00, 0x00,/*诊3556*/},\n        {\n\n                0x0C, 0xD5, 0x55, 0x55, 0x45, 0x5F, 0x45, 0x55, 0x55, 0x55, 0x4C, 0x08, 0x07, 0x01, 0x0F, 0x09,\n                0x01, 0x03, 0x05, 0x05, 0x0B, 0x09,/*震3557*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x22, 0xEA, 0x2A, 0xEA, 0x2A, 0xA2, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x0F, 0x04, 0x03, 0x05, 0x08,/*振3558*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xFA, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x0B,\n                0x06, 0x02, 0x02, 0x06, 0x0B, 0x02,/*镇3559*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0x64, 0x5C, 0x47, 0xF4, 0x44, 0x44, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x02, 0x02, 0x02, 0x0F, 0x02, 0x02,/*阵3560*/},\n        {\n\n                0x22, 0xAA, 0x6A, 0x2F, 0x8A, 0xEA, 0x1A, 0x2F, 0x42, 0xA2, 0x92, 0x09, 0x04, 0x01, 0x05, 0x09,\n                0x01, 0x05, 0x09, 0x01, 0x04, 0x08,/*蒸3561*/},\n        {\n\n                0x84, 0xFF, 0x44, 0x48, 0x54, 0x53, 0xF2, 0x5A, 0x56, 0xF0, 0x40, 0x08, 0x0F, 0x00, 0x00, 0x09,\n                0x09, 0x0F, 0x01, 0x01, 0x03, 0x00,/*挣3562*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x48, 0x54, 0x53, 0xF2, 0x5A, 0x56, 0xF0, 0x40, 0x0F, 0x04, 0x0F, 0x00, 0x09,\n                0x09, 0x0F, 0x01, 0x01, 0x03, 0x00,/*睁3563*/},\n        {\n\n                0x24, 0xF2, 0x09, 0x00, 0xE2, 0x02, 0x02, 0xFE, 0x42, 0x42, 0x42, 0x00, 0x0F, 0x00, 0x08, 0x0F,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*征3564*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x48, 0x54, 0x53, 0xF2, 0x5A, 0x56, 0xF0, 0x40, 0x08, 0x08, 0x07, 0x00, 0x09,\n                0x09, 0x0F, 0x01, 0x01, 0x03, 0x00,/*狰3565*/},\n        {\n\n                0x48, 0x54, 0x52, 0x53, 0x52, 0xF2, 0x5A, 0x56, 0x50, 0xF0, 0x40, 0x00, 0x01, 0x01, 0x09, 0x09,\n                0x0F, 0x01, 0x01, 0x01, 0x03, 0x00,/*争3566*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x02, 0xE2, 0x02, 0xFE, 0x42, 0x42, 0x42, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x08, 0x08,/*怔3567*/},\n        {\n\n                0xC2, 0xAE, 0x9A, 0xFF, 0x9A, 0xAE, 0xC4, 0xAB, 0x92, 0xAE, 0xC2, 0x08, 0x08, 0x0E, 0x08, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*整3568*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x10, 0x92, 0x72, 0x02, 0xFA, 0x26, 0xC2, 0x30, 0x08, 0x0F, 0x00, 0x09, 0x08,\n                0x08, 0x0A, 0x0B, 0x08, 0x08, 0x09,/*拯3569*/},\n        {\n\n                0x00, 0x02, 0xE2, 0x02, 0x02, 0xFE, 0x42, 0x42, 0x42, 0x42, 0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*正3570*/},\n        {\n\n                0x02, 0xF2, 0x02, 0xFE, 0x22, 0x22, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x04, 0x07, 0x04, 0x03, 0x02,\n                0x02, 0x08, 0x05, 0x02, 0x05, 0x08,/*政3571*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xF0, 0x10, 0xDF, 0x14, 0xF4, 0x01, 0x00, 0x0F, 0x01, 0x01,\n                0x00, 0x0B, 0x04, 0x03, 0x04, 0x0B,/*帧3572*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x94, 0x15, 0x16, 0xF4, 0x94, 0x94, 0x94, 0x09, 0x04, 0x03, 0x08, 0x0F,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*症3573*/},\n        {\n\n                0x40, 0x49, 0x4A, 0xF8, 0x4A, 0x49, 0x40, 0xFE, 0x02, 0x32, 0xCE, 0x08, 0x04, 0x03, 0x00, 0x01,\n                0x06, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郑3574*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x02, 0xE2, 0x02, 0x02, 0xFE, 0x42, 0x42, 0x42, 0x00, 0x07, 0x02, 0x09, 0x0F,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*证3575*/},\n        {\n\n                0x22, 0x22, 0x22, 0x27, 0x2A, 0x32, 0xA2, 0xA7, 0x62, 0x22, 0x02, 0x08, 0x04, 0x04, 0x0A, 0x09,\n                0x09, 0x08, 0x08, 0x08, 0x08, 0x08,/*芝3576*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x24, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*枝3577*/},\n        {\n\n                0x04, 0x24, 0x64, 0xA4, 0x24, 0x3F, 0x24, 0x24, 0xA4, 0x64, 0x04, 0x08, 0x08, 0x08, 0x04, 0x05,\n                0x02, 0x02, 0x05, 0x04, 0x08, 0x08,/*支3578*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0x24, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x04, 0x03, 0x01, 0x03, 0x08, 0x08,\n                0x04, 0x05, 0x02, 0x05, 0x08, 0x08,/*吱3579*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x47, 0xFC, 0x44, 0xFE, 0x02, 0xFE, 0x04, 0x04, 0x03, 0x02, 0x0B,\n                0x06, 0x01, 0x0E, 0x07, 0x02, 0x07,/*蜘3580*/},\n        {\n\n                0x50, 0x48, 0x47, 0xFC, 0x44, 0x44, 0x40, 0xFC, 0x04, 0x04, 0xFC, 0x08, 0x04, 0x03, 0x00, 0x01,\n                0x06, 0x00, 0x07, 0x02, 0x02, 0x07,/*知3581*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x20, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x04, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*肢3582*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x00, 0xCF, 0x54, 0x54, 0x52, 0x52, 0xD9, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*脂3583*/},\n        {\n\n                0x10, 0x21, 0x02, 0x20, 0x20, 0x20, 0xFF, 0x20, 0x20, 0x20, 0x20, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x00, 0x0F, 0x00, 0x00, 0x00, 0x00,/*汁3584*/},\n        {\n\n                0x00, 0x08, 0x08, 0x08, 0x09, 0x8A, 0x48, 0x28, 0x18, 0x08, 0x00, 0x00, 0x08, 0x04, 0x02, 0x05,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*之3585*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xFE, 0x82, 0x82, 0x82, 0xFE, 0x00, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x04, 0x02, 0x00, 0x02, 0x04, 0x08,/*织3586*/},\n        {\n\n                0x01, 0xFF, 0x49, 0x49, 0xFF, 0x01, 0x7E, 0x42, 0x42, 0x42, 0x7E, 0x02, 0x03, 0x02, 0x02, 0x0F,\n                0x01, 0x08, 0x06, 0x00, 0x02, 0x0C,/*职3587*/},\n        {\n\n                0x00, 0x02, 0xFA, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0xAA, 0xFA, 0x02, 0x00, 0x08, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x08,/*直3588*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x08,/*植3589*/},\n        {\n\n                0x62, 0x9E, 0xF2, 0x00, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xFA, 0x02, 0x08, 0x06, 0x01, 0x08, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x08,/*殖3590*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x48, 0xFF, 0x08, 0x08, 0xF8, 0x00, 0x00, 0x08, 0x0F, 0x08, 0x04, 0x03,\n                0x00, 0x03, 0x00, 0x03, 0x04, 0x0E,/*执3591*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xFA, 0x02, 0x00, 0x0F, 0x00, 0x08, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x08,/*值3592*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x00, 0x32, 0x2A, 0xE6, 0x22, 0x32, 0x62, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*侄3593*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x00, 0xF8, 0x00, 0x00, 0xFF, 0x10, 0x10, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x0F, 0x08, 0x08, 0x0F, 0x08, 0x08,/*址3594*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xCF, 0x54, 0x54, 0x52, 0x52, 0xD9, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*指3595*/},\n        {\n\n                0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0xFF, 0x10, 0x10, 0x10, 0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x08,/*止3596*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0xF8, 0x00, 0x00, 0xFF, 0x10, 0x10, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x0F, 0x08, 0x08, 0x0F, 0x08, 0x08,/*趾3597*/},\n        {\n\n                0x00, 0x7E, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x7E, 0x00, 0x08, 0x04, 0x02, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x02, 0x04, 0x08,/*只3598*/},\n        {\n\n                0x00, 0xCF, 0x54, 0x54, 0x52, 0x52, 0x52, 0x51, 0x51, 0xDC, 0x00, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*旨3599*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xFE, 0x22, 0x22, 0xFF, 0x21, 0x21, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x04, 0x02, 0x03, 0x04, 0x0E,/*纸3600*/},\n        {\n\n                0x04, 0x24, 0x24, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x24, 0x24, 0x04, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*志3601*/},\n        {\n\n                0x0A, 0x2A, 0xBF, 0x8A, 0xA0, 0x9A, 0x8F, 0x52, 0x0E, 0x10, 0x38, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*挚3602*/},\n        {\n\n                0x08, 0xFF, 0x88, 0x40, 0x49, 0xFA, 0x49, 0x40, 0xFE, 0x32, 0xCE, 0x09, 0x0F, 0x00, 0x08, 0x06,\n                0x01, 0x06, 0x00, 0x0F, 0x02, 0x01,/*掷3603*/},\n        {\n\n                0x02, 0x22, 0x32, 0x2A, 0x26, 0xE2, 0x22, 0x2A, 0x32, 0x62, 0x02, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*至3604*/},\n        {\n\n                0x92, 0x9A, 0xF6, 0x92, 0x9A, 0x20, 0xD8, 0x0F, 0x88, 0x78, 0x08, 0x04, 0x04, 0x07, 0x02, 0x0A,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*致3605*/},\n        {\n\n                0x10, 0x17, 0xD5, 0x55, 0x57, 0x7D, 0x57, 0x55, 0xD5, 0x17, 0x10, 0x08, 0x08, 0x0F, 0x08, 0x08,\n                0x0E, 0x08, 0x08, 0x0F, 0x08, 0x08,/*置3606*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0x7E, 0x42, 0x42, 0x42, 0x7E, 0x01, 0x00, 0x0F, 0x01, 0x01,\n                0x00, 0x08, 0x06, 0x00, 0x02, 0x0C,/*帜3607*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x10, 0x54, 0x54, 0x5F, 0xF4, 0x54, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x01, 0x0A, 0x08, 0x0F, 0x00,/*峙3608*/},\n        {\n\n                0x18, 0xD6, 0x54, 0xFF, 0x54, 0xD4, 0x10, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x07, 0x00, 0x0F, 0x04,\n                0x07, 0x00, 0x01, 0x08, 0x08, 0x0F,/*制3609*/},\n        {\n\n                0x94, 0x53, 0xB2, 0x9E, 0xB2, 0xD2, 0x80, 0xBE, 0xA2, 0xA2, 0x3E, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*智3610*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x90, 0x4C, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*秩3611*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x90, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*稚3612*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xEA, 0x2A, 0x2A, 0xBE, 0x29, 0x29, 0xE9, 0x08, 0x04, 0x03, 0x00, 0x0B, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x0B, 0x00,/*质3613*/},\n        {\n\n                0x20, 0x24, 0xA4, 0x2A, 0x13, 0xD6, 0x0A, 0x0A, 0x06, 0x82, 0x00, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x05, 0x08, 0x08,/*炙3614*/},\n        {\n\n                0x08, 0x90, 0xFE, 0xA2, 0xAA, 0xAA, 0xAB, 0xBE, 0xEA, 0xAA, 0xA2, 0x09, 0x04, 0x03, 0x00, 0x01,\n                0x02, 0x08, 0x08, 0x0F, 0x00, 0x00,/*痔3615*/},\n        {\n\n                0x22, 0x44, 0x32, 0x92, 0x97, 0x92, 0xD7, 0x92, 0x97, 0x92, 0x32, 0x04, 0x02, 0x00, 0x07, 0x00,\n                0x00, 0x0F, 0x00, 0x04, 0x07, 0x00,/*滞3616*/},\n        {\n\n                0x10, 0x22, 0x04, 0x10, 0xD8, 0x54, 0x53, 0x50, 0x50, 0xD8, 0x30, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*治3617*/},\n        {\n\n                0x16, 0x0A, 0x96, 0xD2, 0xB2, 0x93, 0x92, 0xD2, 0x96, 0x0A, 0x16, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*窒3618*/},\n        {\n\n                0x00, 0xF8, 0x88, 0x88, 0x88, 0xFF, 0x88, 0x88, 0x88, 0xF8, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x01, 0x00,/*中3619*/},\n        {\n\n                0x00, 0x3C, 0x24, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x24, 0x3C, 0x00, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盅3620*/},\n        {\n\n                0x00, 0x3C, 0x24, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x24, 0x3C, 0x00, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*忠3621*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x01, 0x00, 0x0F, 0x00, 0x01,/*钟3622*/},\n        {\n\n                0x04, 0x74, 0x54, 0x54, 0xD5, 0xFE, 0x54, 0x54, 0x54, 0x74, 0x04, 0x04, 0x04, 0x02, 0x0F, 0x08,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*衷3623*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x48, 0x44, 0xAB, 0x92, 0x2A, 0x46, 0x40, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x02, 0x02, 0x04, 0x05, 0x08, 0x00,/*终3624*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0xF8, 0x88, 0x88, 0xFF, 0x88, 0x88, 0xF8, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*种3625*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x01, 0x00, 0x0F, 0x00, 0x01,/*肿3626*/},\n        {\n\n                0x08, 0xFA, 0xAA, 0xAA, 0xAA, 0xFE, 0xA9, 0xA9, 0xA9, 0xF9, 0x08, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*重3627*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xF8, 0x88, 0x88, 0xFF, 0x88, 0x88, 0xF8, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*仲3628*/},\n        {\n\n                0x20, 0x20, 0x10, 0xC8, 0x04, 0x03, 0x04, 0xC8, 0x10, 0x20, 0x20, 0x08, 0x04, 0x02, 0x01, 0x0A,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*众3629*/},\n        {\n\n                0x40, 0x40, 0xFC, 0x44, 0x56, 0x65, 0x44, 0x44, 0xFC, 0x40, 0x40, 0x08, 0x06, 0x01, 0x00, 0x01,\n                0x02, 0x00, 0x08, 0x0F, 0x00, 0x00,/*舟3630*/},\n        {\n\n                0x00, 0x00, 0xFF, 0x21, 0xA9, 0xA9, 0xBD, 0xA9, 0xA9, 0x21, 0xFF, 0x08, 0x04, 0x03, 0x00, 0x03,\n                0x02, 0x02, 0x02, 0x0B, 0x08, 0x0F,/*周3631*/},\n        {\n\n                0x20, 0x18, 0x00, 0xFF, 0x10, 0x20, 0xFE, 0x00, 0x10, 0x20, 0xFF, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x07, 0x00, 0x00, 0x00, 0x0F,/*州3632*/},\n        {\n\n                0x22, 0x44, 0x20, 0x10, 0xFF, 0x10, 0x20, 0xFE, 0x10, 0x20, 0xFF, 0x04, 0x02, 0x09, 0x04, 0x03,\n                0x00, 0x00, 0x07, 0x00, 0x00, 0x0F,/*洲3633*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x08, 0x14, 0x92, 0x93, 0x92, 0x9A, 0x96, 0xF0, 0x00, 0x07, 0x02, 0x01, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*诌3634*/},\n        {\n\n                0xF2, 0x92, 0x9E, 0x24, 0xA8, 0xFF, 0xA8, 0x24, 0xF2, 0x92, 0x9E, 0x08, 0x08, 0x07, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x08, 0x08, 0x07,/*粥3635*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0xF8, 0x48, 0x48, 0xFF, 0x48, 0x48, 0xF8, 0x01, 0x01, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*轴3636*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x28, 0xC8, 0x08, 0xFF, 0x08, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x00, 0x00, 0x08, 0x0F, 0x00,/*肘3637*/},\n        {\n\n                0xC0, 0x51, 0x55, 0x55, 0x55, 0xD5, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x00, 0x07, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x05, 0x07, 0x00,/*帚3638*/},\n        {\n\n                0x00, 0x1E, 0x12, 0xD2, 0x5E, 0x40, 0x5E, 0xD2, 0x12, 0x1E, 0x00, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*咒3639*/},\n        {\n\n                0x94, 0x93, 0x9A, 0xF6, 0x00, 0xFC, 0x24, 0xE4, 0x3F, 0xE4, 0x0C, 0x04, 0x04, 0x04, 0x07, 0x08,\n                0x07, 0x08, 0x05, 0x02, 0x05, 0x08,/*皱3640*/},\n        {\n\n                0x0C, 0xE4, 0x24, 0x24, 0x25, 0xFE, 0x24, 0x24, 0x24, 0xE4, 0x0C, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x0F, 0x00,/*宙3641*/},\n        {\n\n                0x40, 0x3F, 0xE5, 0xA5, 0xA5, 0xA5, 0xA5, 0xAD, 0xF5, 0x27, 0x40, 0x00, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0B, 0x08, 0x00,/*昼3642*/},\n        {\n\n                0x3D, 0x21, 0xBF, 0xE0, 0x51, 0xDF, 0x55, 0xFF, 0xA9, 0x12, 0xAE, 0x01, 0x09, 0x08, 0x07, 0x09,\n                0x04, 0x02, 0x0F, 0x00, 0x03, 0x04,/*骤3643*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x28, 0x26, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x04, 0x07, 0x02, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*珠3644*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x28, 0x26, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*株3645*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x26, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*蛛3646*/},\n        {\n\n                0x20, 0x28, 0x26, 0xA4, 0x64, 0xFF, 0x64, 0xA4, 0x24, 0x20, 0x20, 0x02, 0x02, 0x01, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x02,/*朱3647*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x10, 0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD4, 0x12, 0x08, 0x08, 0x07, 0x01, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*猪3648*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x10, 0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD4, 0x12, 0x00, 0x0F, 0x04, 0x01, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*诸3649*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x28, 0x26, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x00, 0x00, 0x07, 0x02, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*诛3650*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x52, 0x4A, 0xA6, 0x5A, 0xF2, 0x22, 0x52, 0x8A, 0x08, 0x07, 0x08, 0x09, 0x09,\n                0x0A, 0x0A, 0x09, 0x08, 0x08, 0x09,/*逐3651*/},\n        {\n\n                0x20, 0x10, 0x0C, 0xFB, 0x08, 0x28, 0x10, 0x0C, 0x0B, 0xF8, 0x08, 0x00, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x0F, 0x00,/*竹3652*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xF8, 0x88, 0x88, 0xFF, 0x88, 0x88, 0xF8, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x08, 0x08, 0x0F, 0x04, 0x04, 0x0E,/*烛3653*/},\n        {\n\n                0x48, 0x48, 0xEA, 0xAA, 0xBA, 0xAF, 0xAA, 0xAC, 0xAA, 0xE8, 0x08, 0x08, 0x04, 0x03, 0x06, 0x0A,\n                0x02, 0x06, 0x0A, 0x02, 0x07, 0x08,/*煮3654*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x08, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*拄3655*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFF, 0x75, 0x55, 0xFD, 0x55, 0x77, 0x00, 0x0F, 0x04, 0x0F, 0x06, 0x01,\n                0x0F, 0x05, 0x07, 0x05, 0x09, 0x0F,/*瞩3656*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFF, 0x75, 0x55, 0xFD, 0x55, 0x77, 0x00, 0x03, 0x01, 0x0B, 0x06, 0x01,\n                0x0F, 0x05, 0x07, 0x05, 0x09, 0x0F,/*嘱3657*/},\n        {\n\n                0x00, 0x88, 0x88, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x88, 0x88, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*主3658*/},\n        {\n\n                0x22, 0x22, 0xAA, 0xAF, 0xEA, 0xBE, 0xAA, 0xB7, 0xAA, 0xA2, 0x22, 0x01, 0x01, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*著3659*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*柱3660*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x04, 0x07, 0x04, 0x02, 0x03,\n                0x0A, 0x06, 0x01, 0x08, 0x08, 0x07,/*助3661*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,/*蛀3662*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x38, 0x09, 0x0A, 0x08, 0x38, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x04, 0x04, 0x04, 0x04, 0x04,/*贮3663*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x20, 0x2A, 0xEA, 0xBF, 0xAA, 0xEA, 0xA2, 0x00, 0x0F, 0x04, 0x00, 0x04,\n                0x03, 0x00, 0x02, 0x08, 0x0F, 0x00,/*铸3664*/},\n        {\n\n                0x24, 0x23, 0xE6, 0x2A, 0x02, 0xE0, 0xA4, 0x23, 0xE6, 0x0A, 0x02, 0x04, 0x04, 0x03, 0x0A, 0x04,\n                0x03, 0x00, 0x01, 0x07, 0x08, 0x0E,/*筑3665*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x08, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*住3666*/},\n        {\n\n                0x22, 0x44, 0x00, 0x88, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x88, 0x00, 0x04, 0x02, 0x08, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x08,/*注3667*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0x80, 0x7E, 0xC2, 0x42, 0xC2, 0x7E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*祝3668*/},\n        {\n\n                0x02, 0x7A, 0x42, 0x7E, 0xC0, 0x08, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x08, 0x08, 0x08, 0x0F, 0x08, 0x08,/*驻3669*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFE, 0x01, 0x00, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x0F, 0x00, 0x01, 0x06, 0x08,/*抓3670*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x7F, 0x81, 0x01, 0x00, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x01, 0x06, 0x08,/*爪3671*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x7C, 0x54, 0x54, 0xFF, 0x54, 0xD4, 0x7C, 0x08, 0x0F, 0x00, 0x00, 0x08,\n                0x08, 0x04, 0x02, 0x03, 0x04, 0x0E,/*拽3672*/},\n        {\n\n                0x20, 0x24, 0xA4, 0xE4, 0xBC, 0xA7, 0xA4, 0xA4, 0xA4, 0x24, 0x20, 0x00, 0x00, 0x02, 0x02, 0x02,\n                0x04, 0x04, 0x06, 0x09, 0x00, 0x00,/*专3673*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x24, 0xE4, 0xBC, 0xA7, 0xA4, 0xA4, 0x20, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x02, 0x02, 0x04, 0x06, 0x09, 0x00,/*砖3674*/},\n        {\n\n                0x74, 0x4F, 0xF4, 0x40, 0x24, 0xE4, 0xBC, 0xA7, 0xA4, 0xA4, 0x20, 0x02, 0x02, 0x0F, 0x01, 0x00,\n                0x02, 0x02, 0x04, 0x06, 0x09, 0x00,/*转3675*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x9F, 0xE5, 0xB7, 0x80, 0x9F, 0xE5, 0xB7, 0x08, 0x0F, 0x00, 0x02, 0x0A,\n                0x07, 0x02, 0x02, 0x02, 0x07, 0x0A,/*撰3676*/},\n        {\n\n                0xFE, 0x02, 0xF2, 0x44, 0x55, 0xFE, 0x54, 0xFE, 0x55, 0xF4, 0x44, 0x09, 0x04, 0x03, 0x0C, 0x03,\n                0x0F, 0x01, 0x0F, 0x03, 0x05, 0x08,/*赚3677*/},\n        {\n\n                0x24, 0xA3, 0xB2, 0x6E, 0x6A, 0xAC, 0x2B, 0x3A, 0xA6, 0x62, 0x22, 0x08, 0x0A, 0x0A, 0x05, 0x05,\n                0x0A, 0x0F, 0x01, 0x02, 0x04, 0x04,/*篆3678*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xFC, 0x44, 0x45, 0xF6, 0x44, 0x44, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x08, 0x08, 0x0F, 0x08, 0x08,/*桩3679*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x44, 0x44, 0x45, 0xF6, 0x44, 0x44, 0x44, 0x04, 0x08, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x08,/*庄3680*/},\n        {\n\n                0xA1, 0x92, 0x88, 0xBF, 0x84, 0xE4, 0xA4, 0xBF, 0xA4, 0xA4, 0x84, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*装3681*/},\n        {\n\n                0x04, 0x88, 0x50, 0xFF, 0x00, 0x48, 0xB8, 0x0F, 0x88, 0x78, 0x08, 0x01, 0x00, 0x00, 0x0F, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*妆3682*/},\n        {\n\n                0x84, 0x84, 0xFF, 0x44, 0x08, 0xFA, 0xAE, 0xFB, 0xAE, 0xFA, 0x08, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*撞3683*/},\n        {\n\n                0x04, 0x88, 0xFF, 0x00, 0x10, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x10, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x00,/*壮3684*/},\n        {\n\n                0x04, 0x88, 0xFF, 0x00, 0x10, 0x10, 0xD0, 0x3F, 0xD0, 0x12, 0x14, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*状3685*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x50, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*椎3686*/},\n        {\n\n                0x98, 0xF7, 0x94, 0xA4, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*锥3687*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFC, 0x54, 0x56, 0x55, 0x54, 0x54, 0xDC, 0x00, 0x08, 0x07, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*追3688*/},\n        {\n\n                0x48, 0x2A, 0xBA, 0xAF, 0xEA, 0x8A, 0xC4, 0xAB, 0x92, 0x2E, 0x42, 0x08, 0x08, 0x0B, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x0B, 0x08, 0x00,/*赘3689*/},\n        {\n\n                0x00, 0xFF, 0x21, 0x25, 0x9B, 0x40, 0x30, 0x0F, 0x30, 0x40, 0x80, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*坠3690*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xAA, 0x92, 0xAE, 0x00, 0xAA, 0x92, 0xAE, 0x04, 0x04, 0x02, 0x00, 0x0A,\n                0x04, 0x0B, 0x00, 0x0B, 0x04, 0x0B,/*缀3691*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x02, 0xBA, 0xAA, 0xAA, 0xAB, 0xAA, 0xBA, 0x02, 0x00, 0x07, 0x02, 0x00, 0x02,\n                0x02, 0x0A, 0x0E, 0x03, 0x02, 0x02,/*谆3692*/},\n        {\n\n                0x04, 0x08, 0x20, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x04, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*准3693*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0xDF, 0x11, 0xF1, 0x91, 0x9F, 0x80, 0x00, 0x08, 0x0F, 0x08, 0x04,\n                0x03, 0x04, 0x0F, 0x08, 0x08, 0x08,/*捉3694*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xBC, 0x20, 0x20, 0xFF, 0x20, 0x20, 0xBC, 0x00, 0x08, 0x0F, 0x00, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*拙3695*/},\n        {\n\n                0x00, 0xF8, 0xA8, 0xA8, 0xA8, 0xAF, 0xAA, 0xAA, 0xAA, 0xFA, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*卓3696*/},\n        {\n\n                0x00, 0xF8, 0xA8, 0xA8, 0xA8, 0xAF, 0xAA, 0xAA, 0xAA, 0xFA, 0x00, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*桌3697*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x92, 0x6A, 0xA6, 0x9A, 0xF2, 0xA2, 0x12, 0x04, 0x07, 0x02, 0x00, 0x04,\n                0x02, 0x09, 0x08, 0x07, 0x00, 0x01,/*琢3698*/},\n        {\n\n                0x02, 0x72, 0x42, 0x47, 0x42, 0xFA, 0x42, 0x47, 0x42, 0x72, 0x02, 0x00, 0x0F, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x00,/*茁3699*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x28, 0xC7, 0x04, 0xFC, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x08, 0x08, 0x07,/*酌3700*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x92, 0x6A, 0xA6, 0x9A, 0xF2, 0xA2, 0x12, 0x03, 0x01, 0x03, 0x00, 0x04,\n                0x02, 0x09, 0x08, 0x07, 0x00, 0x01,/*啄3701*/},\n        {\n\n                0x22, 0xAA, 0xEA, 0xBB, 0xAE, 0xAA, 0xAA, 0xAB, 0xEA, 0x22, 0x22, 0x01, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*着3702*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x14, 0x08, 0x27, 0xC4, 0x04, 0x04, 0xFC, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*灼3703*/},\n        {\n\n                0x10, 0x21, 0x02, 0xF8, 0x88, 0x88, 0xFF, 0x88, 0x88, 0xF8, 0x00, 0x04, 0x02, 0x05, 0x04, 0x04,\n                0x04, 0x07, 0x04, 0x04, 0x06, 0x0C,/*浊3704*/},\n        {\n\n                0x64, 0x54, 0xCD, 0x46, 0x24, 0x04, 0x64, 0x56, 0xCD, 0x44, 0x24, 0x06, 0x05, 0x04, 0x06, 0x0C,\n                0x00, 0x06, 0x05, 0x04, 0x06, 0x0C,/*兹3705*/},\n        {\n\n                0x42, 0xA4, 0x80, 0xC4, 0xA3, 0x92, 0x8E, 0x92, 0xA2, 0xCA, 0x46, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*咨3706*/},\n        {\n\n                0x10, 0xD1, 0x4A, 0x40, 0x54, 0xD3, 0x4A, 0x46, 0x4A, 0xD2, 0x16, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*资3707*/},\n        {\n\n                0xA2, 0x94, 0x80, 0xA4, 0xD3, 0x8A, 0x86, 0x8A, 0x92, 0xAA, 0xA6, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*姿3708*/},\n        {\n\n                0x11, 0x22, 0x00, 0x64, 0x5D, 0xC6, 0x34, 0x64, 0x5E, 0xC5, 0x34, 0x04, 0x02, 0x01, 0x06, 0x05,\n                0x0E, 0x00, 0x06, 0x05, 0x04, 0x0E,/*滋3709*/},\n        {\n\n                0x22, 0x44, 0x04, 0xCA, 0x51, 0x44, 0xCA, 0x51, 0x44, 0x4A, 0xD1, 0x04, 0x02, 0x00, 0x0F, 0x05,\n                0x05, 0x07, 0x05, 0x05, 0x05, 0x0F,/*淄3710*/},\n        {\n\n                0x82, 0x82, 0xF2, 0x4E, 0x00, 0x20, 0xD8, 0x0F, 0x88, 0x78, 0x08, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*孜3711*/},\n        {\n\n                0x10, 0x1E, 0x50, 0x6F, 0xDA, 0x4A, 0x40, 0x2F, 0x94, 0x12, 0x19, 0x00, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x00,/*紫3712*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x40, 0x42, 0x42, 0xF2, 0x4A, 0x46, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x00,/*仔3713*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x24, 0x42, 0x42, 0xF2, 0x4A, 0x46, 0x40, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x00,/*籽3714*/},\n        {\n\n                0x22, 0x44, 0x86, 0x92, 0xB2, 0xD6, 0x9B, 0xD2, 0xB2, 0x92, 0x86, 0x04, 0x02, 0x00, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x00,/*滓3715*/},\n        {\n\n                0x40, 0x40, 0x42, 0x42, 0x42, 0xF2, 0x4A, 0x46, 0x42, 0x40, 0x40, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*子3716*/},\n        {\n\n                0x00, 0xFC, 0x24, 0x24, 0x26, 0x25, 0x24, 0x24, 0x24, 0xFC, 0x00, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x00,/*自3717*/},\n        {\n\n                0x22, 0x44, 0x22, 0xAA, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xAA, 0x22, 0x04, 0x02, 0x08, 0x0B, 0x04,\n                0x04, 0x03, 0x04, 0x04, 0x0B, 0x08,/*渍3718*/},\n        {\n\n                0x0C, 0x04, 0x24, 0x24, 0x25, 0x26, 0xA4, 0x64, 0x24, 0x04, 0x0C, 0x01, 0x01, 0x01, 0x09, 0x09,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*字3719*/},\n        {\n\n                0xD4, 0x5F, 0x54, 0x56, 0x5D, 0x74, 0x40, 0x44, 0x52, 0x49, 0xC4, 0x00, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x00,/*鬃3720*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x06, 0x92, 0x92, 0x93, 0x92, 0x92, 0x86, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*棕3721*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0x96, 0x92, 0x93, 0x92, 0x92, 0x86, 0x0F, 0x08, 0x07, 0x04, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*踪3722*/},\n        {\n\n                0x86, 0x82, 0x92, 0x92, 0x92, 0x93, 0x92, 0x92, 0x92, 0x82, 0x86, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*宗3723*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x86, 0x92, 0x92, 0x93, 0x92, 0x92, 0x86, 0x04, 0x04, 0x02, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*综3724*/},\n        {\n\n                0x00, 0x7C, 0x45, 0x46, 0x44, 0x44, 0x44, 0x46, 0x45, 0x7C, 0x00, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*总3725*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x04, 0x04, 0x0A, 0x04, 0x03,\n                0x08, 0x05, 0x03, 0x00, 0x07, 0x08,/*纵3726*/},\n        {\n\n                0x08, 0x94, 0x93, 0x92, 0x9A, 0xF6, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x04, 0x04, 0x04, 0x04,\n                0x0F, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邹3727*/},\n        {\n\n                0x20, 0x24, 0xA4, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x24, 0x24, 0x20, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*走3728*/},\n        {\n\n                0x20, 0xA2, 0x6A, 0xBA, 0xAE, 0xAB, 0xAA, 0xAA, 0x6A, 0xA2, 0x20, 0x01, 0x02, 0x0A, 0x0A, 0x06,\n                0x03, 0x02, 0x06, 0x0A, 0x02, 0x01,/*奏3729*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xA2, 0x6A, 0xBA, 0xAF, 0xAA, 0x6A, 0xA2, 0x00, 0x08, 0x0F, 0x00, 0x02,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x02,/*揍3730*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*租3731*/},\n        {\n\n                0x00, 0x1F, 0x91, 0x11, 0x11, 0xF1, 0x91, 0x91, 0x91, 0x9F, 0x00, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*足3732*/},\n        {\n\n                0x00, 0x44, 0x24, 0x1C, 0x25, 0xC6, 0x24, 0x1C, 0x24, 0x44, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*卒3733*/},\n        {\n\n                0x08, 0xF8, 0x49, 0x4A, 0xD0, 0x08, 0x47, 0x34, 0xE4, 0x24, 0x24, 0x08, 0x07, 0x08, 0x08, 0x07,\n                0x00, 0x09, 0x05, 0x03, 0x05, 0x09,/*族3734*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*祖3735*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFE, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x00, 0x07, 0x0A, 0x09, 0x0F,\n                0x08, 0x08, 0x08, 0x08, 0x0F, 0x08,/*诅3736*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*阻3737*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*组3738*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xC0, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*钻3739*/},\n        {\n\n                0x44, 0xC3, 0x7A, 0x4E, 0x5A, 0x68, 0x5C, 0x6B, 0x7A, 0xC6, 0x42, 0x01, 0x0A, 0x06, 0x03, 0x0A,\n                0x0E, 0x02, 0x02, 0x07, 0x0A, 0x01,/*纂3740*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x4E, 0xE8, 0x5F, 0x55, 0xD0, 0x77, 0x4A, 0xCD, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x0F,/*嘴3741*/},\n        {\n\n                0xFD, 0xA5, 0x9F, 0xA5, 0xFD, 0x00, 0x24, 0x1D, 0xA6, 0x1C, 0x24, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x01, 0x01, 0x0F, 0x01, 0x01,/*醉3742*/},\n        {\n\n                0x10, 0xF0, 0x5F, 0x55, 0xF5, 0x15, 0x55, 0xD5, 0x5F, 0xD0, 0x10, 0x04, 0x07, 0x05, 0x05, 0x0F,\n                0x02, 0x08, 0x05, 0x02, 0x05, 0x08,/*最3743*/},\n        {\n\n                0x20, 0xAF, 0xA9, 0xA9, 0xFF, 0x09, 0xFF, 0xA9, 0xA9, 0xAF, 0x20, 0x02, 0x02, 0x02, 0x02, 0x0F,\n                0x00, 0x0F, 0x02, 0x02, 0x02, 0x02,/*罪3744*/},\n        {\n\n                0x02, 0xFA, 0xAB, 0x9E, 0xAA, 0xAA, 0xAA, 0x9E, 0xAB, 0xFA, 0x02, 0x02, 0x02, 0x06, 0x0A, 0x02,\n                0x02, 0x02, 0x0A, 0x0F, 0x02, 0x02,/*尊3745*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFA, 0xAB, 0xDE, 0xCA, 0xBE, 0xAB, 0xFA, 0x00, 0x08, 0x07, 0x08, 0x0A, 0x0E,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*遵3746*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x07, 0x02, 0x02, 0x07, 0x00,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*昨3747*/},\n        {\n\n                0x04, 0x04, 0x84, 0x74, 0x4F, 0x44, 0xC4, 0x44, 0x44, 0x44, 0x04, 0x04, 0x02, 0x09, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x08,/*左3748*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x84, 0x74, 0x4F, 0xC4, 0x44, 0x44, 0x04, 0x00, 0x00, 0x0F, 0x02, 0x09,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*佐3749*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*柞3750*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xC8, 0x7F, 0xC8, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x00, 0x0F, 0x00, 0x07, 0x02,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*做3751*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*作3752*/},\n        {\n\n                0x40, 0x20, 0x1E, 0x20, 0x40, 0xFF, 0x40, 0x20, 0x1E, 0x20, 0x40, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*坐3753*/},\n        {\n\n                0x00, 0xFC, 0x84, 0x44, 0x34, 0x45, 0xFE, 0x44, 0x34, 0x44, 0x84, 0x08, 0x07, 0x08, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x08,/*座3754*/},\n        {\n\n                0x20, 0x22, 0x22, 0x22, 0x22, 0xE2, 0x22, 0x22, 0x22, 0x22, 0x20, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*亍3755*/},\n        {\n\n                0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*丌3756*/},\n        {\n\n                0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*兀3757*/},\n        {\n\n                0x02, 0xF2, 0x82, 0x82, 0x82, 0xFE, 0x92, 0x92, 0x92, 0x92, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*丐3758*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x10, 0x10, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x0F, 0x00, 0x00,/*廿3759*/},\n        {\n\n                0x20, 0x20, 0xFF, 0x20, 0x20, 0xFE, 0x20, 0x20, 0xFF, 0x20, 0x20, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x07, 0x00, 0x00, 0x0F, 0x00, 0x00,/*卅3760*/},\n        {\n\n                0x82, 0x82, 0x42, 0x22, 0x12, 0xFA, 0x06, 0x12, 0x12, 0x22, 0x42, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0B, 0x08, 0x08, 0x08, 0x08, 0x08,/*丕3761*/},\n        {\n\n                0x02, 0xFA, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0x4A, 0xFA, 0x02, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*亘3762*/},\n        {\n\n                0x10, 0x90, 0x51, 0x31, 0x01, 0xF9, 0x25, 0x53, 0x90, 0x08, 0x00, 0x09, 0x08, 0x08, 0x0A, 0x0A,\n                0x0B, 0x08, 0x08, 0x08, 0x09, 0x09,/*丞3763*/},\n        {\n\n                0xC1, 0x41, 0x5D, 0xD5, 0x55, 0x55, 0x55, 0xD5, 0x5D, 0x41, 0xC1, 0x0F, 0x00, 0x02, 0x02, 0x03,\n                0x0E, 0x03, 0x02, 0x02, 0x08, 0x0F,/*鬲3764*/},\n        {\n\n                0x49, 0xC9, 0x69, 0x45, 0xC5, 0x1F, 0x21, 0x25, 0xA5, 0x69, 0x09, 0x09, 0x05, 0x02, 0x02, 0x05,\n                0x08, 0x01, 0x09, 0x0F, 0x01, 0x01,/*孬3765*/},\n        {\n\n                0x21, 0xAF, 0xAB, 0xAF, 0x21, 0xFF, 0x21, 0xAF, 0xAB, 0xAF, 0x21, 0x08, 0x0B, 0x0A, 0x0B, 0x08,\n                0x0F, 0x08, 0x0B, 0x0A, 0x0B, 0x08,/*噩3766*/},\n        {\n\n                0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*丨3767*/},\n        {\n\n                0xC0, 0x5F, 0x55, 0x55, 0x55, 0xFF, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x0F, 0x00, 0x02, 0x02, 0x02,\n                0x03, 0x02, 0x03, 0x06, 0x08, 0x0F,/*禺3768*/},\n        {\n\n                0x00, 0x00, 0x00, 0x00, 0xC0, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x06, 0x01,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*丿3769*/},\n        {\n\n                0x00, 0xFF, 0x20, 0x20, 0x20, 0x10, 0x10, 0x08, 0x08, 0x04, 0x80, 0x00, 0x03, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x07,/*匕3770*/},\n        {\n\n                0x40, 0x42, 0x42, 0x42, 0x42, 0xFE, 0x21, 0x21, 0x21, 0x21, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*乇3771*/},\n        {\n\n                0x20, 0x22, 0x22, 0x22, 0xA2, 0x7E, 0xA1, 0x21, 0x21, 0x20, 0x20, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*夭3772*/},\n        {\n\n                0x20, 0x22, 0x22, 0x94, 0x14, 0x08, 0x08, 0x14, 0x92, 0x11, 0x20, 0x08, 0x08, 0x08, 0x04, 0x05,\n                0x02, 0x02, 0x05, 0x04, 0x08, 0x08,/*爻3773*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xEA, 0x2A, 0x2A, 0x2A, 0x29, 0x29, 0xE9, 0x08, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x08, 0x08, 0x09, 0x09, 0x08, 0x0E,/*卮3774*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x7E, 0xA1, 0x21, 0x21, 0x20, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x04, 0x08, 0x01, 0x02, 0x04, 0x0F,/*氐3775*/},\n        {\n\n                0xFC, 0x04, 0x04, 0x16, 0xA5, 0x44, 0xA4, 0x14, 0x04, 0x04, 0xFC, 0x0F, 0x04, 0x04, 0x05, 0x04,\n                0x04, 0x04, 0x05, 0x04, 0x04, 0x0F,/*囟3776*/},\n        {\n\n                0x00, 0xFF, 0x00, 0xD6, 0x5D, 0x54, 0xDA, 0x00, 0xFF, 0x00, 0x00, 0x08, 0x07, 0x00, 0x0F, 0x05,\n                0x0D, 0x0F, 0x00, 0x07, 0x08, 0x0E,/*胤3777*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xF8, 0x02, 0xFA, 0xAB, 0xAE, 0xAA, 0xFB, 0x02, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*馗3778*/},\n        {\n\n                0xFB, 0x4A, 0x6A, 0xFA, 0x40, 0xA4, 0x34, 0xAD, 0x26, 0xB4, 0x64, 0x03, 0x0A, 0x0B, 0x07, 0x08,\n                0x07, 0x00, 0x07, 0x00, 0x0F, 0x08,/*毓3779*/},\n        {\n\n                0x20, 0xAE, 0xEA, 0xAB, 0xAE, 0xBA, 0xAE, 0xAA, 0xEA, 0xAE, 0x20, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*睾3780*/},\n        {\n\n                0xD5, 0x52, 0x78, 0x57, 0xD0, 0x10, 0xA7, 0xAA, 0xFA, 0xA9, 0x2C, 0x0B, 0x0D, 0x09, 0x0D, 0x0B,\n                0x00, 0x08, 0x0B, 0x04, 0x0B, 0x08,/*鼗3781*/},\n        {\n\n                0x00, 0x00, 0x00, 0x10, 0x20, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x03, 0x00, 0x00, 0x00, 0x00,/*丶3782*/},\n        {\n\n                0xF8, 0x89, 0x89, 0xF9, 0x01, 0xF9, 0x05, 0xAB, 0x49, 0xA8, 0x18, 0x08, 0x08, 0x08, 0x08, 0x0A,\n                0x0B, 0x09, 0x08, 0x08, 0x08, 0x09,/*亟3783*/},\n        {\n\n                0xE9, 0x87, 0x81, 0xFF, 0xD5, 0x55, 0xFF, 0x81, 0x95, 0x97, 0xEC, 0x0A, 0x06, 0x02, 0x02, 0x0F,\n                0x00, 0x0F, 0x02, 0x02, 0x02, 0x0E,/*鼐3784*/},\n        {\n\n                0x40, 0x40, 0xFE, 0x20, 0x10, 0x10, 0x08, 0x08, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x07, 0x08, 0x08,\n                0x09, 0x09, 0x09, 0x08, 0x08, 0x0E,/*乜3785*/},\n        {\n\n                0xC0, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x0F, 0x04, 0x04, 0x04, 0x04,\n                0x0F, 0x00, 0x07, 0x08, 0x08, 0x0E,/*乩3786*/},\n        {\n\n                0x10, 0x11, 0xF1, 0x11, 0x11, 0x11, 0x11, 0x11, 0xF1, 0x11, 0x10, 0x08, 0x06, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,/*亓3787*/},\n        {\n\n                0x04, 0x24, 0x24, 0x3F, 0x20, 0xFF, 0x20, 0x3F, 0x24, 0x24, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*芈3788*/},\n        {\n\n                0x18, 0x0A, 0x2A, 0x2A, 0x2A, 0xAF, 0x6A, 0x2A, 0x0A, 0x0A, 0x18, 0x01, 0x01, 0x01, 0x09, 0x09,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*孛3789*/},\n        {\n\n                0x08, 0xEA, 0x2E, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0x2E, 0xEA, 0x08, 0x00, 0x0F, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0B, 0x08, 0x0F, 0x00,/*啬3790*/},\n        {\n\n                0xC8, 0x7F, 0xC8, 0x00, 0xFF, 0x49, 0x4F, 0x00, 0xC9, 0x49, 0xCF, 0x0F, 0x04, 0x0F, 0x00, 0x0F,\n                0x02, 0x02, 0x08, 0x05, 0x02, 0x0D,/*嘏3791*/},\n        {\n\n                0x00, 0xFE, 0x02, 0x02, 0x02, 0xC2, 0x3E, 0xC2, 0x02, 0x02, 0x02, 0x08, 0x07, 0x08, 0x04, 0x03,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x08,/*仄3792*/},\n        {\n\n                0x00, 0xFF, 0x09, 0x69, 0x59, 0x4F, 0xE9, 0x49, 0x49, 0x49, 0x09, 0x08, 0x07, 0x02, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*厍3793*/},\n        {\n\n                0x00, 0xFF, 0x11, 0xD5, 0x5F, 0x55, 0x55, 0x55, 0x5F, 0xD5, 0x11, 0x08, 0x07, 0x00, 0x0F, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*厝3794*/},\n        {\n\n                0x00, 0xFF, 0x15, 0xF5, 0xAD, 0xA5, 0xE7, 0xA5, 0xAD, 0xF7, 0x15, 0x08, 0x07, 0x00, 0x07, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x07, 0x00,/*厣3795*/},\n        {\n\n                0x00, 0xFF, 0xEB, 0x8D, 0xF9, 0x8D, 0xEB, 0x11, 0xCF, 0x09, 0x39, 0x08, 0x07, 0x08, 0x04, 0x03,\n                0x00, 0x08, 0x06, 0x01, 0x06, 0x08,/*厥3796*/},\n        {\n\n                0x00, 0xFF, 0x09, 0xFF, 0xA9, 0xFF, 0x09, 0xFD, 0x25, 0xE5, 0x23, 0x08, 0x07, 0x0A, 0x07, 0x02,\n                0x07, 0x0A, 0x07, 0x00, 0x0F, 0x00,/*厮3797*/},\n        {\n\n                0x00, 0xFF, 0x15, 0x95, 0xAD, 0xA5, 0xE7, 0xA5, 0xAD, 0x97, 0x15, 0x08, 0x07, 0x00, 0x0F, 0x08,\n                0x0F, 0x0A, 0x0F, 0x08, 0x0F, 0x00,/*靥3798*/},\n        {\n\n                0x00, 0xFF, 0x11, 0x7D, 0x0B, 0x7D, 0x57, 0x55, 0x7F, 0x55, 0x55, 0x08, 0x07, 0x08, 0x0B, 0x09,\n                0x05, 0x03, 0x05, 0x05, 0x0B, 0x08,/*赝3799*/},\n        {\n\n                0x00, 0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x0F, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*匚3800*/},\n        {\n\n                0x00, 0xFF, 0x01, 0x01, 0xF9, 0x09, 0x09, 0x09, 0xF9, 0x01, 0x01, 0x00, 0x0F, 0x08, 0x08, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x08, 0x08,/*叵3801*/},\n        {\n\n                0xFF, 0x01, 0x69, 0x59, 0xEF, 0x49, 0x11, 0xFF, 0x11, 0xF1, 0x01, 0x0F, 0x08, 0x09, 0x09, 0x0F,\n                0x09, 0x0C, 0x0B, 0x08, 0x0B, 0x0E,/*匦3802*/},\n        {\n\n                0x00, 0xFF, 0x11, 0xDD, 0x55, 0x55, 0xDF, 0x55, 0x55, 0xDD, 0x11, 0x00, 0x0F, 0x08, 0x0D, 0x0C,\n                0x0A, 0x09, 0x0A, 0x0A, 0x0D, 0x08,/*匮3803*/},\n        {\n\n                0xFF, 0x01, 0xFD, 0xD5, 0x55, 0xD7, 0x55, 0xD5, 0x55, 0xDD, 0x01, 0x0F, 0x09, 0x08, 0x0F, 0x09,\n                0x0B, 0x09, 0x0B, 0x0D, 0x0F, 0x08,/*匾3804*/},\n        {\n\n                0xFE, 0x02, 0xF2, 0x1E, 0xF2, 0x20, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0x0F, 0x08, 0x09, 0x0F, 0x09,\n                0x00, 0x0B, 0x04, 0x03, 0x04, 0x0B,/*赜3805*/},\n        {\n\n                0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x08, 0x09, 0x09, 0x07, 0x05,\n                0x05, 0x00, 0x0F, 0x00, 0x00, 0x00,/*卦3806*/},\n        {\n\n                0x00, 0xF8, 0x28, 0x28, 0x28, 0x2F, 0x2A, 0xEA, 0x0A, 0x0A, 0xFA, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x04, 0x04, 0x0F,/*卣3807*/},\n        {\n\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x01, 0x08, 0x08, 0x0F, 0x00,/*刂3808*/},\n        {\n\n                0x08, 0x10, 0x20, 0xC0, 0x30, 0x0E, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x08, 0x04, 0x03, 0x00, 0x01,\n                0x06, 0x00, 0x01, 0x08, 0x08, 0x0F,/*刈3809*/},\n        {\n\n                0x08, 0xC7, 0x3C, 0x84, 0x7C, 0x04, 0xFC, 0x00, 0xFC, 0x00, 0xFF, 0x09, 0x04, 0x02, 0x01, 0x08,\n                0x08, 0x07, 0x00, 0x01, 0x08, 0x0F,/*刎3810*/},\n        {\n\n                0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x08, 0x08, 0x07, 0x04, 0x04,\n                0x00, 0x00, 0x01, 0x08, 0x08, 0x0F,/*刭3811*/},\n        {\n\n                0x52, 0xCA, 0x56, 0x53, 0x56, 0x4A, 0x52, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x01, 0x01, 0x09, 0x09,\n                0x07, 0x00, 0x00, 0x01, 0x08, 0x0F,/*刳3812*/},\n        {\n\n                0x8E, 0x48, 0xB8, 0x2F, 0x28, 0xE8, 0x0E, 0x00, 0xFC, 0x00, 0xFF, 0x08, 0x08, 0x04, 0x05, 0x02,\n                0x01, 0x00, 0x00, 0x01, 0x08, 0x0F,/*刿3813*/},\n        {\n\n                0xAE, 0xA8, 0xA8, 0xAF, 0xA8, 0xA8, 0xEE, 0x00, 0xFC, 0x00, 0xFF, 0x0F, 0x08, 0x08, 0x04, 0x04,\n                0x02, 0x02, 0x00, 0x01, 0x08, 0x0F,/*剀3814*/},\n        {\n\n                0xF4, 0x94, 0x94, 0xFF, 0x94, 0x94, 0xF4, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x01, 0x0F, 0x01,\n                0x02, 0x04, 0x00, 0x01, 0x08, 0x0F,/*剌3815*/},\n        {\n\n                0x10, 0xDA, 0x56, 0x53, 0xD2, 0x16, 0xFA, 0x10, 0xFC, 0x00, 0xFF, 0x00, 0x07, 0x02, 0x02, 0x0B,\n                0x08, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*剞3816*/},\n        {\n\n                0x08, 0xA6, 0x10, 0xCF, 0x14, 0xA2, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x0A, 0x09, 0x04, 0x03, 0x05,\n                0x08, 0x00, 0x01, 0x08, 0x08, 0x0F,/*剡3817*/},\n        {\n\n                0xE6, 0x1A, 0xF2, 0x03, 0xF2, 0x92, 0xF6, 0x00, 0xFC, 0x00, 0xFF, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x04, 0x02, 0x00, 0x01, 0x08, 0x0F,/*剜3818*/},\n        {\n\n                0xFA, 0xAF, 0xFA, 0x02, 0xFA, 0xAF, 0xFA, 0x00, 0xFC, 0x00, 0xFF, 0x07, 0x08, 0x0F, 0x08, 0x07,\n                0x08, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*蒯3819*/},\n        {\n\n                0x1D, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x00, 0xFC, 0x00, 0xFF, 0x09, 0x05, 0x09, 0x0F, 0x01,\n                0x05, 0x09, 0x00, 0x01, 0x08, 0x0F,/*剽3820*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xF2, 0x2A, 0xA2, 0xDE, 0x32, 0xFC, 0x00, 0xFF, 0x08, 0x07, 0x09, 0x07, 0x09,\n                0x05, 0x03, 0x0C, 0x01, 0x08, 0x0F,/*劂3821*/},\n        {\n\n                0x08, 0xFC, 0x57, 0x54, 0xFD, 0x56, 0x54, 0x00, 0xFC, 0x00, 0xFF, 0x0C, 0x03, 0x0D, 0x01, 0x0D,\n                0x01, 0x0D, 0x00, 0x01, 0x08, 0x0F,/*劁3822*/},\n        {\n\n                0x12, 0xFA, 0x57, 0x52, 0xFA, 0x57, 0x52, 0x00, 0xFC, 0x00, 0xFF, 0x08, 0x09, 0x0B, 0x05, 0x05,\n                0x0B, 0x09, 0x00, 0x01, 0x08, 0x0F,/*劐3823*/},\n        {\n\n                0x00, 0xE0, 0xBE, 0xEB, 0xAA, 0xBE, 0xE0, 0x00, 0xFC, 0x00, 0xFF, 0x02, 0x0B, 0x06, 0x03, 0x02,\n                0x0E, 0x03, 0x02, 0x01, 0x08, 0x0F,/*劓3824*/},\n        {\n\n                0x00, 0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFF, 0x00, 0x0F, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x0F,/*冂3825*/},\n        {\n\n                0xFF, 0x11, 0x51, 0xD5, 0x59, 0x71, 0x59, 0x55, 0x51, 0x11, 0xFF, 0x0F, 0x00, 0x00, 0x03, 0x02,\n                0x02, 0x02, 0x02, 0x08, 0x08, 0x0F,/*罔3826*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*亻3827*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x00, 0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*仃3828*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x00, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*仉3829*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x08, 0x08, 0xFF, 0x08, 0x08, 0x08, 0xF8, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x08, 0x08, 0x08, 0x07,/*仂3830*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0x42, 0x42, 0x42, 0x42, 0x42, 0x42, 0x00, 0x00, 0x0F, 0x00, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*仨3831*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x13, 0x28, 0x27, 0x24, 0xA4, 0xA4, 0x64, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x06,\n                0x09, 0x09, 0x08, 0x08, 0x08, 0x0E,/*仡3832*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x20, 0x10, 0x0C, 0x83, 0x60, 0x18, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*仫3833*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x80, 0x72, 0x02, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*仞3834*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFE, 0x02, 0x0A, 0x32, 0xC2, 0x3A, 0x02, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x08, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*伛3835*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFF, 0x10, 0x10, 0xFF, 0x20, 0x10, 0x0C, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x02, 0x07, 0x08, 0x08, 0x0E,/*仳3836*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x00, 0x32, 0x2A, 0xA2, 0x62, 0xFE, 0x22, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x00, 0x08, 0x0F, 0x00,/*伢3837*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0x82, 0x7E, 0x92, 0x12, 0xF2, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x08, 0x04, 0x00, 0x07, 0x08, 0x0E,/*佤3838*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x88, 0x87, 0x84, 0xFC, 0x84, 0x84, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*仵3839*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x23, 0x20, 0xFF, 0x28, 0x24, 0xE4, 0x22, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x02, 0x00, 0x03, 0x04,/*伥3840*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x10, 0xE8, 0x24, 0x23, 0x24, 0xE8, 0x10, 0x10, 0x00, 0x0F, 0x00, 0x00, 0x07,\n                0x08, 0x09, 0x09, 0x08, 0x08, 0x0E,/*伧3841*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x04, 0xE4, 0x25, 0x26, 0xE4, 0x04, 0x04, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*伉3842*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x38, 0x08, 0x09, 0x0A, 0x08, 0x08, 0x38, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x04,/*伫3843*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x48, 0x4A, 0xCA, 0x7A, 0x4A, 0xCA, 0x4A, 0x48, 0x00, 0x0F, 0x00, 0x08, 0x09,\n                0x05, 0x02, 0x02, 0x05, 0x08, 0x00,/*佞3844*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x23, 0x20, 0x20, 0xFF, 0xA4, 0x24, 0x24, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x00, 0x01, 0x02, 0x00,/*佧3845*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xF8, 0x20, 0x10, 0xEF, 0x08, 0x88, 0x78, 0x08, 0x00, 0x0F, 0x00, 0x03, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*攸3846*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x50, 0x4C, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*佚3847*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x13, 0xEC, 0x27, 0x24, 0x24, 0xE4, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x03,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x07,/*佝3848*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x48, 0x44, 0xAB, 0x92, 0x2A, 0x46, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x02, 0x02, 0x04, 0x05, 0x08, 0x00,/*佟3849*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x24, 0x0C, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x09, 0x08, 0x08, 0x08, 0x0E,/*佗3850*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFE, 0x12, 0xD2, 0x12, 0x92, 0x52, 0x1E, 0x00, 0x0F, 0x08, 0x04, 0x03,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*伲3851*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0xFC, 0x04, 0xFC, 0x00, 0x0F, 0x08, 0x04, 0x03,\n                0x08, 0x0F, 0x00, 0x0F, 0x04, 0x0F,/*伽3852*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xA4, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0xA4, 0x04, 0x00, 0x0F, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*佶3853*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x02, 0xFE, 0x52, 0x52, 0x52, 0xFE, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x03, 0x02, 0x02, 0x02, 0x0F, 0x01,/*佴3854*/},\n        {\n\n                0x10, 0xFC, 0x43, 0x24, 0xF4, 0x5C, 0x57, 0x54, 0x54, 0xF4, 0x04, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x09, 0x0F, 0x00,/*侑3855*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x52, 0xCA, 0x56, 0x53, 0x56, 0x4A, 0x52, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*侉3856*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xDE, 0x12, 0xD2, 0x12, 0xD2, 0x1E, 0x00, 0x00, 0x0F, 0x08, 0x04, 0x03,\n                0x00, 0x0F, 0x00, 0x07, 0x08, 0x0C,/*侃3857*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x28, 0x26, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*侏3858*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x08, 0xF4, 0x53, 0x50, 0x50, 0x53, 0xF4, 0x08, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x09, 0x0F, 0x00,/*佾3859*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x88, 0x50, 0xFF, 0x00, 0x00, 0xFF, 0x50, 0x88, 0x00, 0x0F, 0x00, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x07, 0x08, 0x0E,/*佻3860*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x44, 0x44, 0xAC, 0x15, 0x16, 0xAC, 0x44, 0x44, 0x00, 0x0F, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x0F, 0x00, 0x00,/*侪3861*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x44, 0x24, 0xD4, 0x05, 0x06, 0xD4, 0x24, 0x44, 0x00, 0x0F, 0x00, 0x08, 0x08,\n                0x05, 0x02, 0x02, 0x05, 0x08, 0x08,/*佼3862*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x8C, 0x44, 0xE4, 0x1C, 0x67, 0x84, 0x44, 0x2C, 0x00, 0x0F, 0x01, 0x00, 0x00,\n                0x0F, 0x04, 0x00, 0x01, 0x02, 0x04,/*侬3863*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x80, 0x6C, 0x4A, 0xF9, 0x48, 0x4C, 0x18, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*侔3864*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x22, 0xAA, 0xFA, 0xAF, 0xAA, 0xAA, 0xEA, 0xA2, 0x00, 0x0F, 0x08, 0x06, 0x01,\n                0x00, 0x01, 0x02, 0x08, 0x0F, 0x00,/*俦3865*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xCA, 0x52, 0x7E, 0x42, 0x42, 0x7E, 0x52, 0x4A, 0x00, 0x0F, 0x08, 0x07, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*俨3866*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xFA, 0x8A, 0xFA, 0x02, 0xFA, 0x8A, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F,/*俪3867*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x28, 0x48, 0x88, 0xFF, 0x68, 0x89, 0x4A, 0x28, 0x00, 0x0F, 0x00, 0x02, 0x01,\n                0x08, 0x0F, 0x00, 0x01, 0x02, 0x04,/*俅3868*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0x7F, 0x49, 0x49, 0xFF, 0x49, 0x49, 0x7F, 0x00, 0x0F, 0x00, 0x08, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x09,/*俚3869*/},\n        {\n\n                0x10, 0xFC, 0x83, 0xA0, 0xAF, 0xA9, 0xE9, 0xA9, 0xAF, 0xA0, 0x80, 0x00, 0x0F, 0x00, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*俣3870*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xBE, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xBE, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x03,\n                0x02, 0x02, 0x0A, 0x0A, 0x06, 0x00,/*俜3871*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xF0, 0x51, 0x55, 0xF9, 0x55, 0x53, 0xF0, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*俑3872*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x48, 0x3C, 0x2A, 0xE9, 0x28, 0x2C, 0x18, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*俟3873*/},\n        {\n\n                0x10, 0xFC, 0x23, 0xAA, 0x6A, 0x3A, 0xAF, 0x2A, 0x6A, 0xAA, 0x22, 0x00, 0x0F, 0x01, 0x04, 0x05,\n                0x05, 0x0F, 0x05, 0x05, 0x04, 0x01,/*俸3874*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xAA, 0xEA, 0x22, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*倩3875*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x24, 0x24, 0xEF, 0xB4, 0xA4, 0xAF, 0xA4, 0x24, 0x00, 0x0F, 0x00, 0x02, 0x01,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*偌3876*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x24, 0x24, 0xFF, 0x00, 0x00, 0xFF, 0x24, 0x24, 0x00, 0x0F, 0x00, 0x01, 0x01,\n                0x0F, 0x00, 0x00, 0x0F, 0x01, 0x01,/*俳3877*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xF8, 0xA8, 0xA8, 0xAF, 0xAA, 0xAA, 0xFA, 0x02, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*倬3878*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xF8, 0x10, 0x94, 0x8B, 0xEA, 0x8A, 0xD6, 0x90, 0x00, 0x0F, 0x00, 0x03, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*倏3879*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xBE, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xBE, 0x80, 0x00, 0x0F, 0x00, 0x04, 0x02,\n                0x01, 0x0F, 0x01, 0x02, 0x04, 0x04,/*倮3880*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xA8, 0x9A, 0x8A, 0xFE, 0x89, 0x99, 0xA8, 0x88, 0x00, 0x0F, 0x00, 0x08, 0x0A,\n                0x0B, 0x04, 0x04, 0x0B, 0x08, 0x00,/*倭3881*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x00, 0x00, 0x00, 0x0F, 0x02, 0x03,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*俾3882*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFF, 0x21, 0xA9, 0xBD, 0xA9, 0x21, 0xFF, 0x00, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x03, 0x02, 0x0B, 0x08, 0x0F,/*倜3883*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x0C, 0xF4, 0x54, 0x55, 0x56, 0x54, 0x74, 0x0C, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*倌3884*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0x4C, 0xA4, 0x95, 0x86, 0x94, 0xA4, 0x4C, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*倥3885*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xAA, 0xAE, 0x00, 0x0F, 0x08, 0x06, 0x01,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*倨3886*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xD2, 0x7A, 0x52, 0x57, 0x52, 0x7A, 0xD2, 0x00, 0x00, 0x0F, 0x00, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*偾3887*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xFF, 0x81, 0xBF, 0xEB, 0xAB, 0xBF, 0x81, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x08, 0x0D, 0x0A, 0x0A, 0x0D, 0x08,/*偃3888*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x00, 0xDF, 0x52, 0x4A, 0x60, 0x4F, 0x52, 0xD9, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*偕3889*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x80, 0x5F, 0x75, 0x55, 0xD5, 0x55, 0x5F, 0xC0, 0x00, 0x0F, 0x00, 0x00, 0x06,\n                0x04, 0x05, 0x04, 0x01, 0x08, 0x0F,/*偈3890*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x40, 0xDF, 0x55, 0x55, 0xDF, 0x55, 0x55, 0x5F, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x08, 0x04, 0x01, 0x02, 0x06, 0x09,/*偎3891*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x08, 0x24, 0x5B, 0xAE, 0x12, 0x6E, 0x42, 0x3E, 0x00, 0x0F, 0x00, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*偬3892*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x03, 0xAA, 0x9C, 0xC8, 0xBF, 0x88, 0x9C, 0xAA, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0A, 0x05, 0x04, 0x04, 0x0B, 0x08,/*偻3893*/},\n        {\n\n                0x10, 0xFC, 0x0B, 0x05, 0xF6, 0x94, 0x97, 0x94, 0xF6, 0x05, 0x0C, 0x00, 0x0F, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x08, 0x08, 0x0C,/*傥3894*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x06, 0xFA, 0x2A, 0x2B, 0x2A, 0xE6, 0x22, 0x26, 0x00, 0x0F, 0x00, 0x09, 0x05,\n                0x01, 0x01, 0x01, 0x05, 0x09, 0x01,/*傧3895*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x32, 0xC2, 0x3E, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x00, 0x0F, 0x04, 0x03, 0x00,\n                0x07, 0x00, 0x0F, 0x09, 0x0F, 0x09,/*傩3896*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x48, 0xB7, 0x9A, 0xAE, 0xA0, 0xA7, 0x9A, 0xA6, 0x00, 0x0F, 0x00, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*傺3897*/},\n        {\n\n                0x10, 0xFC, 0x03, 0xEA, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0xEA, 0x02, 0x00, 0x0F, 0x02, 0x0E, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0B, 0x0E, 0x02,/*僖3898*/},\n        {\n\n                0x10, 0xFC, 0x23, 0xDA, 0x57, 0xF2, 0x27, 0xFA, 0x0F, 0xF8, 0x08, 0x00, 0x0F, 0x00, 0x0B, 0x0A,\n                0x07, 0x08, 0x04, 0x03, 0x04, 0x08,/*儆3899*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x2C, 0xD9, 0x4F, 0x79, 0x6C, 0x59, 0xFF, 0x29, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*僭3900*/},\n        {\n\n                0x10, 0xFC, 0x23, 0x10, 0xFC, 0x57, 0x54, 0xFD, 0x56, 0x54, 0x04, 0x00, 0x0F, 0x00, 0x0C, 0x03,\n                0x05, 0x09, 0x05, 0x09, 0x05, 0x09,/*僬3901*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x7A, 0xCB, 0x7A, 0x10, 0xFF, 0xD0, 0x12, 0x14, 0x00, 0x0F, 0x02, 0x09, 0x0F,\n                0x09, 0x06, 0x01, 0x07, 0x08, 0x0E,/*僦3902*/},\n        {\n\n                0x10, 0xFC, 0x0B, 0xFA, 0xAE, 0xAA, 0xFB, 0xAA, 0xAE, 0xFA, 0x08, 0x00, 0x0F, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*僮3903*/},\n        {\n\n                0x10, 0xFC, 0x03, 0x10, 0xD7, 0x55, 0x57, 0x55, 0x57, 0x55, 0xD7, 0x00, 0x0F, 0x00, 0x08, 0x05,\n                0x0F, 0x09, 0x01, 0x03, 0x05, 0x0B,/*儇3904*/},\n        {\n\n                0x10, 0xFC, 0x0B, 0xFC, 0x16, 0xAD, 0xA5, 0xB5, 0xA7, 0xAC, 0x14, 0x00, 0x0F, 0x08, 0x07, 0x00,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*儋3905*/},\n        {\n\n                0x10, 0x50, 0x48, 0x44, 0x42, 0xC1, 0x42, 0x44, 0x48, 0x50, 0x10, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*仝3906*/},\n        {\n\n                0x10, 0x50, 0x48, 0xC4, 0x02, 0xF1, 0xC2, 0x04, 0x88, 0x50, 0x10, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*氽3907*/},\n        {\n\n                0x08, 0x88, 0x84, 0x94, 0x92, 0x91, 0x92, 0x94, 0x84, 0x88, 0x08, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*佘3908*/},\n        {\n\n                0x10, 0x90, 0x08, 0x14, 0x52, 0x91, 0x12, 0x14, 0xC8, 0x10, 0x10, 0x08, 0x08, 0x0B, 0x08, 0x08,\n                0x09, 0x0C, 0x0B, 0x08, 0x08, 0x08,/*佥3909*/},\n        {\n\n                0x20, 0x18, 0xC7, 0x08, 0x10, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x04, 0x03, 0x00, 0x01, 0x0A,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*俎3910*/},\n        {\n\n                0x74, 0x54, 0x72, 0x06, 0x75, 0x55, 0x75, 0x06, 0x72, 0x54, 0x74, 0x0F, 0x05, 0x05, 0x0F, 0x05,\n                0x05, 0x05, 0x0F, 0x05, 0x0D, 0x0F,/*龠3911*/},\n        {\n\n                0x10, 0x50, 0x48, 0xC9, 0x05, 0xF2, 0xC4, 0x08, 0x88, 0x50, 0x10, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*汆3912*/},\n        {\n\n                0x90, 0x90, 0xA8, 0xC9, 0x85, 0xF2, 0x84, 0xC8, 0xA8, 0x90, 0x90, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*籴3913*/},\n        {\n\n                0x10, 0x08, 0xD4, 0xB3, 0x90, 0x90, 0x90, 0x93, 0x94, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x08, 0x08, 0x07, 0x00, 0x00,/*兮3914*/},\n        {\n\n                0x00, 0x9F, 0xA5, 0xE5, 0xB7, 0x80, 0x9F, 0xE5, 0xA5, 0xB7, 0x00, 0x02, 0x0A, 0x06, 0x03, 0x02,\n                0x02, 0x02, 0x03, 0x06, 0x0A, 0x02,/*巽3915*/},\n        {\n\n                0x26, 0xEA, 0xAB, 0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0xAB, 0xEA, 0x26, 0x00, 0x0B, 0x06, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x06, 0x0B, 0x00,/*黉3916*/},\n        {\n\n                0xF5, 0x5E, 0xF5, 0x00, 0xF4, 0x94, 0xF4, 0x04, 0xFF, 0x84, 0x65, 0x0F, 0x05, 0x0F, 0x00, 0x04,\n                0x04, 0x0A, 0x04, 0x03, 0x05, 0x0E,/*馘3917*/},\n        {\n\n                0x7C, 0x55, 0xFE, 0x55, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xFA, 0xAE, 0x01, 0x01, 0x0F, 0x09, 0x07,\n                0x00, 0x0F, 0x04, 0x03, 0x04, 0x0A,/*冁3918*/},\n        {\n\n                0xFA, 0x82, 0x7E, 0x4B, 0xFA, 0x56, 0xFA, 0x03, 0x7A, 0xAA, 0xBA, 0x0A, 0x09, 0x0A, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x08, 0x09, 0x0A,/*夔3919*/},\n        {\n\n                0x20, 0x10, 0x0C, 0x07, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x08, 0x07,/*勹3920*/},\n        {\n\n                0x0C, 0xEB, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xEE, 0x0A, 0x02, 0xFE, 0x00, 0x0F, 0x02, 0x02, 0x07,\n                0x02, 0x0A, 0x0F, 0x00, 0x08, 0x0F,/*匍3921*/},\n        {\n\n                0x04, 0xAB, 0xAA, 0xAA, 0xAE, 0xAA, 0xAA, 0xAA, 0x0A, 0x02, 0xFE, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0E, 0x00, 0x08, 0x0F,/*訇3922*/},\n        {\n\n                0x04, 0x8B, 0xEA, 0xAA, 0xAA, 0xAA, 0xEA, 0x8A, 0x02, 0x02, 0xFE, 0x00, 0x0F, 0x0A, 0x0A, 0x0F,\n                0x0A, 0x0A, 0x0F, 0x00, 0x08, 0x0F,/*匐3923*/},\n        {\n\n                0x00, 0x3E, 0xA2, 0xA6, 0xAB, 0xA2, 0xAA, 0x2E, 0x20, 0xE0, 0x00, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x07, 0x08, 0x09, 0x09, 0x0C,/*凫3924*/},\n        {\n\n                0x00, 0xFF, 0x41, 0x25, 0x5D, 0x95, 0x75, 0x01, 0xFF, 0x00, 0x00, 0x08, 0x07, 0x00, 0x04, 0x02,\n                0x01, 0x00, 0x00, 0x03, 0x04, 0x0F,/*夙3925*/},\n        {\n\n                0x00, 0x7F, 0x41, 0xC1, 0x4F, 0x48, 0x4F, 0xC1, 0x41, 0x7F, 0x00, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*兕3926*/},\n        {\n\n                0x04, 0x04, 0x04, 0x04, 0x05, 0x06, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*亠3927*/},\n        {\n\n                0x24, 0x94, 0xCC, 0xA4, 0x95, 0x86, 0xA4, 0xCC, 0x94, 0x24, 0x04, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x07, 0x08, 0x09, 0x08, 0x0C,/*兖3928*/},\n        {\n\n                0x62, 0x22, 0x3A, 0x2A, 0x2A, 0xAB, 0xAA, 0xAA, 0x3A, 0x22, 0x62, 0x04, 0x05, 0x05, 0x05, 0x07,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x08, 0x0C,/*亳3929*/},\n        {\n\n                0x12, 0x12, 0x4A, 0x66, 0x52, 0xCB, 0x42, 0x66, 0x4A, 0x92, 0x12, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*衮3930*/},\n        {\n\n                0xA2, 0xAA, 0xAA, 0x6A, 0x3A, 0xAB, 0xEA, 0x3A, 0x2A, 0x22, 0x62, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*袤3931*/},\n        {\n\n                0x2A, 0xAA, 0xFE, 0x2A, 0x82, 0xEB, 0x3E, 0x4A, 0x3A, 0x42, 0xE2, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*亵3932*/},\n        {\n\n                0x12, 0xCA, 0x42, 0x5E, 0xC2, 0x63, 0xC2, 0x5E, 0x42, 0xCA, 0x12, 0x00, 0x0F, 0x00, 0x01, 0x04,\n                0x02, 0x04, 0x01, 0x08, 0x0F, 0x00,/*脔3933*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAA, 0xA6, 0x83, 0xAA, 0xAA, 0xAA, 0xFA, 0x02, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*裒3934*/},\n        {\n\n                0x02, 0x3E, 0xA2, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0xA2, 0x3E, 0x02, 0x02, 0x0A, 0x06, 0x02, 0x0A,\n                0x0E, 0x02, 0x02, 0x06, 0x0A, 0x02,/*禀3935*/},\n        {\n\n                0xE2, 0xAE, 0xEA, 0x4A, 0xCA, 0x7B, 0xCA, 0x0A, 0xEA, 0x2A, 0xE2, 0x07, 0x0A, 0x0F, 0x00, 0x0B,\n                0x04, 0x0B, 0x08, 0x07, 0x01, 0x0F,/*嬴3936*/},\n        {\n\n                0xE2, 0xAE, 0xEA, 0xCA, 0x4A, 0xEB, 0x4A, 0xCA, 0xEA, 0x2A, 0xE2, 0x07, 0x0A, 0x0F, 0x05, 0x05,\n                0x07, 0x05, 0x0D, 0x07, 0x01, 0x0F,/*蠃3937*/},\n        {\n\n                0xE2, 0xAE, 0xEA, 0x0A, 0x5A, 0xEB, 0x5A, 0x0A, 0xEA, 0x2A, 0xE2, 0x07, 0x0A, 0x0F, 0x00, 0x05,\n                0x0F, 0x05, 0x08, 0x07, 0x01, 0x0F,/*羸3938*/},\n        {\n\n                0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*冫3939*/},\n        {\n\n                0x04, 0x08, 0x02, 0xC2, 0x3E, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x02, 0x02, 0x01, 0x08, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x0F, 0x08, 0x08,/*冱3940*/},\n        {\n\n                0x04, 0x08, 0x82, 0x62, 0x9E, 0x12, 0xF2, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x09, 0x08, 0x0F,/*冽3941*/},\n        {\n\n                0x04, 0x08, 0x40, 0x50, 0xCE, 0x48, 0x7F, 0xC8, 0x48, 0x48, 0x40, 0x02, 0x01, 0x08, 0x04, 0x03,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*冼3942*/},\n        {\n\n                0x04, 0x08, 0x80, 0x48, 0xFF, 0x28, 0x58, 0x87, 0x60, 0x07, 0x18, 0x04, 0x02, 0x00, 0x00, 0x0F,\n                0x00, 0x06, 0x05, 0x04, 0x05, 0x0E,/*凇3943*/},\n        {\n\n                0x0E, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*冖3944*/},\n        {\n\n                0x23, 0x25, 0xD5, 0x95, 0x4D, 0xB5, 0xE5, 0x45, 0xA5, 0x15, 0x03, 0x05, 0x05, 0x02, 0x02, 0x09,\n                0x08, 0x07, 0x00, 0x01, 0x02, 0x04,/*冢3945*/},\n        {\n\n                0x03, 0x01, 0x7D, 0x55, 0x55, 0xD5, 0x55, 0x55, 0x7D, 0x01, 0x03, 0x01, 0x09, 0x05, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x05, 0x09, 0x01,/*冥3946*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*讠3947*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x40, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*讦3948*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*讧3949*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xF8, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xF8, 0x00, 0x07, 0x02, 0x01, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*讪3950*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFE, 0x02, 0x0A, 0x32, 0xC2, 0x3A, 0x02, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x08, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*讴3951*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0xFE, 0x12, 0x12, 0x12, 0x12, 0xF2, 0x00, 0x00, 0x07, 0x02, 0x01,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x09,/*讵3952*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFC, 0x84, 0x44, 0x3F, 0x44, 0x84, 0xFC, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*讷3953*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x08, 0xC8, 0x48, 0x48, 0x7F, 0x48, 0x48, 0xC8, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*诂3954*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x02, 0xF2, 0x12, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x00, 0x07, 0x02, 0x01, 0x03,\n                0x01, 0x01, 0x09, 0x08, 0x0F, 0x00,/*诃3955*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x07, 0x02, 0x01, 0x07,\n                0x02, 0x05, 0x08, 0x03, 0x04, 0x0F,/*诋3956*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0x22, 0x92, 0x8E, 0x82, 0xA2, 0xA2, 0x9E, 0x00, 0x07, 0x02, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*诏3957*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xBC, 0x20, 0x20, 0xFF, 0x20, 0x20, 0xBC, 0x00, 0x07, 0x02, 0x01, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*诎3958*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x10, 0xD8, 0x54, 0x53, 0x50, 0x50, 0xD8, 0x30, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*诒3959*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFE, 0x02, 0x4A, 0x4A, 0xFA, 0x4A, 0x4A, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x08, 0x0A, 0x0A, 0x0B, 0x0A, 0x0A,/*诓3960*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x44, 0x54, 0x54, 0xFF, 0x54, 0x54, 0x44, 0x00, 0x00, 0x07, 0x02, 0x05,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*诔3961*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x00, 0x00, 0x07, 0x02, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*诖3962*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xA4, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0xA4, 0x04, 0x00, 0x07, 0x02, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*诘3963*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x04, 0xC4, 0x3F, 0xC4, 0x04, 0xF4, 0x44, 0x24, 0x00, 0x07, 0x02, 0x04, 0x03,\n                0x08, 0x04, 0x02, 0x01, 0x06, 0x08,/*诙3964*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x50, 0xCE, 0x48, 0x7F, 0xC8, 0x48, 0x48, 0x40, 0x00, 0x07, 0x0A, 0x04, 0x03,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*诜3965*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFE, 0x12, 0x92, 0x92, 0x91, 0x91, 0x90, 0x00, 0x07, 0x02, 0x09, 0x07,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*诟3966*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x10, 0x28, 0x24, 0xE3, 0x24, 0x28, 0x10, 0x00, 0x00, 0x07, 0x02, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*诠3967*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x48, 0x54, 0x53, 0xF2, 0x5A, 0x56, 0xF0, 0x40, 0x00, 0x07, 0x02, 0x00, 0x09,\n                0x09, 0x0F, 0x01, 0x01, 0x03, 0x00,/*诤3968*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x0B, 0x69, 0x59, 0x4F, 0xE9, 0x49, 0x49, 0x0B, 0x00, 0x07, 0x02, 0x01, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*诨3969*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0x12, 0xA2, 0xFE, 0x00, 0x12, 0xA2, 0xFE, 0x00, 0x07, 0x02, 0x00, 0x01,\n                0x08, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*诩3970*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xF2, 0x54, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x01, 0x01, 0x01, 0x01, 0x09, 0x0F,/*诮3971*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x28, 0xA6, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0x20, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*诰3972*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x8A, 0x44, 0xFB, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x00, 0x07, 0x02, 0x08, 0x08,\n                0x07, 0x08, 0x08, 0x0F, 0x08, 0x08,/*诳3973*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x48, 0x3C, 0x2A, 0xE9, 0x28, 0x2C, 0x18, 0x00, 0x00, 0x07, 0x02, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*诶3974*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x01, 0xFF, 0x49, 0xFF, 0x01, 0xFE, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x02, 0x03,\n                0x02, 0x0F, 0x09, 0x04, 0x03, 0x0C,/*诹3975*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x92, 0x6A, 0xA6, 0x9A, 0xF2, 0xA2, 0x12, 0x00, 0x00, 0x07, 0x02, 0x04,\n                0x02, 0x09, 0x08, 0x07, 0x00, 0x01,/*诼3976*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xA8, 0x9A, 0x8A, 0xFE, 0x89, 0x99, 0xA8, 0x88, 0x00, 0x07, 0x02, 0x08, 0x0A,\n                0x0B, 0x04, 0x04, 0x0B, 0x08, 0x00,/*诿3977*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFC, 0x92, 0x80, 0xFF, 0x80, 0x92, 0xFE, 0x00, 0x07, 0x02, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*谀3978*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0x08, 0x14, 0x92, 0x19, 0x52, 0x34, 0x08, 0x00, 0x07, 0x02, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*谂3979*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x08, 0xE4, 0xA3, 0x92, 0x02, 0xAA, 0xA6, 0xE0, 0x00, 0x07, 0x02, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*谄3980*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0x24, 0x1C, 0x25, 0x86, 0x24, 0x1C, 0x24, 0x00, 0x07, 0x02, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*谇3981*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x80, 0x82, 0xFF, 0xAA, 0xAA, 0xAA, 0xFF, 0x82, 0x00, 0x07, 0x02, 0x00, 0x0F,\n                0x0A, 0x09, 0x08, 0x09, 0x0A, 0x08,/*谌3982*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xFA, 0xAA, 0x8A, 0xFF, 0x8A, 0xAA, 0xFA, 0x00, 0x00, 0x07, 0x02, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*谏3983*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xFC, 0x14, 0x9F, 0xB5, 0xAD, 0xB5, 0x0C, 0x00, 0x07, 0x02, 0x09, 0x07,\n                0x02, 0x0F, 0x0A, 0x0A, 0x0A, 0x02,/*谑3984*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x80, 0x5F, 0x75, 0x55, 0xD5, 0x55, 0x5F, 0xC0, 0x00, 0x07, 0x02, 0x00, 0x06,\n                0x04, 0x05, 0x04, 0x01, 0x08, 0x0F,/*谒3985*/},\n        {\n\n                0x11, 0xF2, 0x40, 0x57, 0xD5, 0x57, 0x50, 0x57, 0x55, 0x57, 0x40, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*谔3986*/},\n        {\n\n                0x10, 0xF1, 0x02, 0xE8, 0xA4, 0xAA, 0xE9, 0x0A, 0xC4, 0x08, 0xE8, 0x00, 0x07, 0x02, 0x0F, 0x02,\n                0x0A, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*谕3987*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x42, 0x56, 0x5A, 0xD6, 0x7A, 0x52, 0x59, 0x55, 0x00, 0x07, 0x02, 0x05, 0x0A,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*谖3988*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x12, 0xD6, 0x5A, 0x53, 0x52, 0x5A, 0xD6, 0x12, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*谙3989*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xB2, 0x96, 0x9A, 0xD3, 0x9A, 0x96, 0xB2, 0x00, 0x07, 0x02, 0x01, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*谛3990*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x21, 0x92, 0xA4, 0x93, 0x8E, 0x92, 0xA2, 0xA6, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*谘3991*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x80, 0xFE, 0x2A, 0xEA, 0x2B, 0xEA, 0x2A, 0xEE, 0x00, 0x07, 0x02, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*谝3992*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x02, 0xFA, 0xAF, 0xAA, 0xAA, 0xAF, 0xFA, 0x02, 0x00, 0x0F, 0x04, 0x0A, 0x0A,\n                0x06, 0x03, 0x02, 0x06, 0x0A, 0x0A,/*谟3993*/},\n        {\n\n                0x11, 0xF2, 0x0C, 0x05, 0xF6, 0x94, 0x97, 0x94, 0xF6, 0x05, 0x0C, 0x00, 0x07, 0x02, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x08, 0x08, 0x0C,/*谠3994*/},\n        {\n\n                0x11, 0xF2, 0x80, 0x5F, 0x35, 0xD5, 0x9F, 0x95, 0xB5, 0x5F, 0x80, 0x00, 0x0F, 0x04, 0x0A, 0x09,\n                0x0A, 0x04, 0x04, 0x0B, 0x08, 0x08,/*谡3995*/},\n        {\n\n                0x11, 0xF2, 0x48, 0xA9, 0x9A, 0x88, 0x88, 0x88, 0x9A, 0xA9, 0x48, 0x00, 0x07, 0x0A, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*谥3996*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xAC, 0xA0, 0x9D, 0xAA, 0xA4, 0xB2, 0x85, 0x18, 0x00, 0x07, 0x0A, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*谧3997*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x00, 0xF2, 0x16, 0x5A, 0xF3, 0x5A, 0x16, 0xF2, 0x00, 0x07, 0x02, 0x01, 0x0F,\n                0x00, 0x07, 0x05, 0x07, 0x08, 0x0F,/*谪3998*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFA, 0x2A, 0xAB, 0xFA, 0x02, 0x3B, 0x82, 0xFA, 0x00, 0x0F, 0x04, 0x0A, 0x06,\n                0x02, 0x02, 0x02, 0x0A, 0x0A, 0x06,/*谫3999*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x2C, 0xD9, 0x4F, 0x79, 0x6C, 0x59, 0xFF, 0x29, 0x00, 0x07, 0x02, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*谮4000*/},\n        {\n\n                0x10, 0xF1, 0x22, 0x10, 0xFC, 0x57, 0x54, 0xFD, 0x56, 0x54, 0x04, 0x00, 0x07, 0x02, 0x0C, 0x03,\n                0x05, 0x09, 0x05, 0x09, 0x05, 0x09,/*谯4001*/},\n        {\n\n                0x10, 0xF1, 0x02, 0x48, 0xE9, 0x59, 0xEB, 0x7D, 0xCD, 0x4B, 0xD8, 0x00, 0x07, 0x02, 0x00, 0x0F,\n                0x01, 0x0E, 0x0A, 0x0E, 0x01, 0x0F,/*谲4002*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFA, 0xAA, 0xCF, 0xAA, 0xFA, 0x10, 0xFF, 0x12, 0x00, 0x07, 0x02, 0x0F, 0x02,\n                0x07, 0x0A, 0x0F, 0x04, 0x03, 0x0C,/*谳4003*/},\n        {\n\n                0x11, 0xF2, 0x08, 0xFC, 0x16, 0xAD, 0xA5, 0xB5, 0xA7, 0xAC, 0x14, 0x00, 0x07, 0x0A, 0x07, 0x00,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*谵4004*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xAC, 0xFB, 0x0C, 0xFB, 0xAC, 0xFF, 0x8A, 0x4C, 0x00, 0x0F, 0x04, 0x0A, 0x0F,\n                0x08, 0x0F, 0x0A, 0x03, 0x04, 0x0E,/*谶4005*/},\n        {\n\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x0F, 0x00, 0x01, 0x01, 0x00,/*卩4006*/},\n        {\n\n                0x24, 0x95, 0xAD, 0xA5, 0xB1, 0xBD, 0xA3, 0xA5, 0xA8, 0x14, 0x12, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x0A, 0x0B, 0x08, 0x0C,/*卺4007*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*阝4008*/},\n        {\n\n                0xFF, 0x01, 0x19, 0xE7, 0x02, 0xFE, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x0F, 0x02, 0x02, 0x09, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*阢4009*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*阡4010*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x80, 0x88, 0xFF, 0x88, 0x88, 0xFF, 0x88, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x04, 0x03, 0x00, 0x00, 0x0F, 0x00,/*阱4011*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0xFE, 0x12, 0xF2, 0x12, 0x91, 0x71, 0x0F, 0x02, 0x02, 0x09, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*阪4012*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0xC0, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*阽4013*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*阼4014*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0xFC, 0x24, 0xE4, 0x3F, 0xE4, 0x0C, 0x0F, 0x02, 0x02, 0x09, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*陂4015*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x40, 0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*陉4016*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x00, 0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x09, 0x09, 0x04, 0x02, 0x05, 0x08,/*陔4017*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x20, 0xBC, 0x20, 0xFF, 0x24, 0x24, 0xA4, 0x0F, 0x02, 0x02, 0x01, 0x09,\n                0x08, 0x04, 0x05, 0x02, 0x01, 0x00,/*陟4018*/},\n        {\n\n                0xFF, 0x01, 0x19, 0xE7, 0x00, 0x7F, 0x49, 0xC9, 0x49, 0x7F, 0x00, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*陧4019*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x01, 0xFF, 0x49, 0xFF, 0x01, 0xFE, 0x02, 0xFE, 0x0F, 0x02, 0x01, 0x02, 0x03,\n                0x02, 0x0F, 0x09, 0x04, 0x03, 0x0C,/*陬4020*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x48, 0xFA, 0x4A, 0xFE, 0x49, 0xF9, 0x48, 0x40, 0x0F, 0x02, 0x01, 0x02, 0x0B,\n                0x0A, 0x0F, 0x0A, 0x0B, 0x02, 0x00,/*陲4021*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x00, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x00, 0x0F, 0x02, 0x01, 0x02, 0x03,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*陴4022*/},\n        {\n\n                0xFF, 0x01, 0x19, 0xE7, 0x40, 0xDF, 0x55, 0xDF, 0x55, 0x5F, 0x40, 0x0F, 0x02, 0x02, 0x01, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*隈4023*/},\n        {\n\n                0xFE, 0x02, 0x32, 0xCE, 0x80, 0xBE, 0xAB, 0xAA, 0xAA, 0xBE, 0x80, 0x0F, 0x02, 0x02, 0x01, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*隍4024*/},\n        {\n\n                0xFE, 0x32, 0xCE, 0x00, 0x7C, 0x54, 0xF6, 0x5D, 0xD4, 0x7C, 0x00, 0x0F, 0x02, 0x01, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x0A, 0x0B, 0x0C,/*隗4025*/},\n        {\n\n                0xFF, 0x31, 0xCF, 0x00, 0x5F, 0xB5, 0x55, 0x15, 0x55, 0xB5, 0x5F, 0x0F, 0x02, 0x01, 0x00, 0x0B,\n                0x02, 0x0B, 0x00, 0x0B, 0x02, 0x0B,/*隰4026*/},\n        {\n\n                0x20, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x20, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邗4027*/},\n        {\n\n                0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x02, 0x02, 0x02, 0x01, 0x01,\n                0x01, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邛4028*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x05, 0x06, 0x04, 0x04, 0xFE, 0x02, 0x32, 0xCE, 0x08, 0x07, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邝4029*/},\n        {\n\n                0x08, 0xF8, 0x09, 0x0A, 0x08, 0x08, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x07, 0x04, 0x04, 0x04,\n                0x00, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邙4030*/},\n        {\n\n                0x00, 0x7C, 0x46, 0x45, 0x54, 0xDC, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x02, 0x02, 0x01, 0x09, 0x08,\n                0x07, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邬4031*/},\n        {\n\n                0x04, 0x04, 0xFD, 0x26, 0x24, 0xE4, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x08, 0x06, 0x01, 0x08, 0x08,\n                0x07, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邡4032*/},\n        {\n\n                0xF2, 0x12, 0x92, 0x7E, 0x92, 0x12, 0xF2, 0x00, 0xFE, 0x32, 0xCE, 0x0F, 0x01, 0x00, 0x00, 0x00,\n                0x09, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*邴4033*/},\n        {\n\n                0x42, 0x22, 0x12, 0xFE, 0x12, 0x62, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x04, 0x04, 0x04, 0x03, 0x02,\n                0x02, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邳4034*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x00, 0xFF, 0x10, 0x10, 0xFE, 0x02, 0x32, 0xCE, 0x02, 0x01, 0x0F, 0x00, 0x0F,\n                0x04, 0x02, 0x0F, 0x02, 0x02, 0x01,/*邶4035*/},\n        {\n\n                0x10, 0x20, 0xFF, 0x00, 0xFF, 0x20, 0x10, 0xFE, 0x02, 0x32, 0xCE, 0x04, 0x04, 0x07, 0x02, 0x03,\n                0x02, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邺4036*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x0F, 0x04, 0x08, 0x03, 0x04,\n                0x0E, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邸4037*/},\n        {\n\n                0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邰4038*/},\n        {\n\n                0x94, 0xA4, 0x84, 0xFF, 0x84, 0xA4, 0x94, 0x00, 0xFE, 0x32, 0xCE, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x04, 0x08, 0x00, 0x0F, 0x02, 0x01,/*郏4039*/},\n        {\n\n                0x92, 0x9A, 0x96, 0xF2, 0x9A, 0xB2, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x08, 0x08, 0x08, 0x07, 0x04,\n                0x04, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郅4040*/},\n        {\n\n                0x28, 0x26, 0xA4, 0xFF, 0xA4, 0x24, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x02, 0x01, 0x00, 0x0F, 0x00,\n                0x01, 0x00, 0x0F, 0x02, 0x02, 0x01,/*邾4041*/},\n        {\n\n                0x48, 0x54, 0xD2, 0x51, 0x52, 0x44, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x06, 0x05, 0x04, 0x05,\n                0x0E, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郐4042*/},\n        {\n\n                0x20, 0xA9, 0x65, 0x32, 0xA2, 0x25, 0x28, 0x00, 0xFE, 0x32, 0xCE, 0x01, 0x04, 0x06, 0x05, 0x04,\n                0x06, 0x0C, 0x00, 0x0F, 0x02, 0x01,/*郄4043*/},\n        {\n\n                0x04, 0xFB, 0x4A, 0xFA, 0x02, 0xFE, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x07, 0x02, 0x0B, 0x08,\n                0x07, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郇4044*/},\n        {\n\n                0xD6, 0xB2, 0x9A, 0xD2, 0x92, 0x96, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x04, 0x04, 0x04, 0x0F, 0x02,\n                0x02, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郓4045*/},\n        {\n\n                0xFA, 0x8A, 0xFA, 0x02, 0xFA, 0x8A, 0xFA, 0x00, 0xFE, 0x32, 0xCE, 0x0F, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*郦4046*/},\n        {\n\n                0x00, 0x5E, 0x52, 0xD2, 0x52, 0x5E, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x08, 0x09, 0x09, 0x07, 0x05,\n                0x05, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郢4047*/},\n        {\n\n                0x28, 0xA6, 0xA4, 0xBF, 0xA4, 0xA4, 0x20, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x0F, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郜4048*/},\n        {\n\n                0x90, 0xD5, 0xBA, 0xD2, 0x92, 0x95, 0x90, 0x00, 0xFE, 0x32, 0xCE, 0x00, 0x07, 0x00, 0x0F, 0x00,\n                0x04, 0x07, 0x00, 0x0F, 0x02, 0x01,/*郗4049*/},\n        {\n\n                0x2A, 0x32, 0x26, 0xAA, 0x61, 0x29, 0x05, 0xFE, 0x02, 0x32, 0xCE, 0x02, 0x02, 0x0A, 0x0F, 0x01,\n                0x01, 0x01, 0x0F, 0x02, 0x02, 0x01,/*郛4050*/},\n        {\n\n                0x00, 0x7C, 0xD6, 0x7D, 0x54, 0x7C, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x02, 0x03, 0x02, 0x0F, 0x02,\n                0x02, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郫4051*/},\n        {\n\n                0x08, 0xA6, 0x10, 0xCF, 0x14, 0xA2, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x0A, 0x09, 0x04, 0x03, 0x05,\n                0x08, 0x00, 0x0F, 0x02, 0x02, 0x01,/*郯4052*/},\n        {\n\n                0xFF, 0x81, 0xBF, 0xEB, 0xAB, 0xBF, 0x81, 0x80, 0xFF, 0x31, 0xCF, 0x0F, 0x08, 0x0D, 0x0A, 0x0A,\n                0x0D, 0x08, 0x08, 0x0F, 0x02, 0x01,/*郾4053*/},\n        {\n\n                0x7A, 0x4A, 0x7E, 0xCA, 0x7E, 0x4A, 0x7A, 0x00, 0xFE, 0x32, 0xCE, 0x08, 0x09, 0x09, 0x07, 0x05,\n                0x05, 0x00, 0x00, 0x0F, 0x02, 0x01,/*鄄4054*/},\n        {\n\n                0x11, 0x9D, 0x71, 0x5F, 0x55, 0x55, 0x51, 0x00, 0xFF, 0x31, 0xCF, 0x04, 0x09, 0x05, 0x09, 0x05,\n                0x09, 0x07, 0x00, 0x0F, 0x02, 0x01,/*鄢4055*/},\n        {\n\n                0x02, 0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x00, 0xFE, 0x02, 0x32, 0xCE, 0x08, 0x0A, 0x0A, 0x0F, 0x0A,\n                0x0A, 0x00, 0x0F, 0x02, 0x02, 0x01,/*鄞4056*/},\n        {\n\n                0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x08, 0xFE, 0x02, 0x32, 0xCE, 0x02, 0x02, 0x02, 0x0F, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x01,/*鄣4057*/},\n        {\n\n                0x52, 0xB6, 0x9A, 0xBE, 0x99, 0xB5, 0x50, 0xFE, 0x02, 0x32, 0xCE, 0x00, 0x0F, 0x0A, 0x0F, 0x0A,\n                0x0F, 0x00, 0x0F, 0x02, 0x02, 0x01,/*鄱4058*/},\n        {\n\n                0xA2, 0xEB, 0xAA, 0xFE, 0xAA, 0xEB, 0xA2, 0x00, 0xFE, 0x32, 0xCE, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0E, 0x00, 0x00, 0x0F, 0x02, 0x01,/*鄯4059*/},\n        {\n\n                0x51, 0xDF, 0x55, 0xFF, 0xA9, 0x12, 0xAE, 0x00, 0xFF, 0x31, 0xCF, 0x09, 0x04, 0x02, 0x0F, 0x00,\n                0x03, 0x04, 0x00, 0x0F, 0x02, 0x01,/*鄹4060*/},\n        {\n\n                0x0C, 0x55, 0x05, 0x7F, 0x05, 0x55, 0x0C, 0x00, 0xFF, 0x31, 0xCF, 0x0F, 0x09, 0x0F, 0x09, 0x0F,\n                0x09, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*酃4061*/},\n        {\n\n                0xBC, 0xAA, 0xBF, 0xAA, 0xBF, 0xAA, 0xBC, 0x00, 0xFE, 0x32, 0xCE, 0x08, 0x0B, 0x0E, 0x0A, 0x0E,\n                0x0B, 0x08, 0x00, 0x0F, 0x02, 0x01,/*酆4062*/},\n        {\n\n                0x10, 0x08, 0x94, 0x93, 0x92, 0x92, 0x92, 0x92, 0x9A, 0x96, 0xF0, 0x00, 0x04, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*刍4063*/},\n        {\n\n                0x10, 0xF8, 0x14, 0x13, 0x12, 0xF2, 0x12, 0x1A, 0x16, 0xF0, 0x00, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*奂4064*/},\n        {\n\n                0x02, 0x02, 0xFE, 0x12, 0x12, 0xF2, 0x00, 0x08, 0xFF, 0x08, 0xF8, 0x08, 0x06, 0x01, 0x08, 0x08,\n                0x07, 0x08, 0x06, 0x09, 0x08, 0x07,/*劢4065*/},\n        {\n\n                0x10, 0xE8, 0x27, 0xE4, 0x04, 0xFC, 0x00, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0x03, 0x01, 0x09, 0x08,\n                0x07, 0x08, 0x06, 0x09, 0x08, 0x07,/*劬4066*/},\n        {\n\n                0x22, 0x92, 0x8E, 0xA2, 0xA2, 0x9E, 0x00, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x0F, 0x08, 0x06, 0x09, 0x08, 0x07,/*劭4067*/},\n        {\n\n                0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x00, 0x08, 0xFF, 0x08, 0xF8, 0x09, 0x09, 0x04, 0x02, 0x05,\n                0x08, 0x08, 0x06, 0x09, 0x08, 0x07,/*劾4068*/},\n        {\n\n                0x52, 0x4A, 0x47, 0x52, 0x52, 0x4E, 0x40, 0x5E, 0x52, 0xD2, 0x5E, 0x00, 0x07, 0x05, 0x05, 0x05,\n                0x05, 0x07, 0x00, 0x08, 0x0F, 0x00,/*哿4069*/},\n        {\n\n                0x88, 0x89, 0xA9, 0xBD, 0x87, 0x85, 0x84, 0x08, 0xFF, 0x08, 0xF8, 0x0F, 0x08, 0x0F, 0x08, 0x07,\n                0x04, 0x07, 0x0C, 0x07, 0x08, 0x0F,/*勐4070*/},\n        {\n\n                0x07, 0xF1, 0x55, 0x55, 0x55, 0xF1, 0x07, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x0F, 0x00, 0x08, 0x07, 0x08, 0x0F,/*勖4071*/},\n        {\n\n                0x92, 0xCF, 0x82, 0xD2, 0x9E, 0x80, 0x7F, 0xC9, 0x7F, 0x49, 0x7F, 0x08, 0x07, 0x08, 0x07, 0x08,\n                0x0F, 0x04, 0x0E, 0x09, 0x0C, 0x03,/*勰4072*/},\n        {\n\n                0x00, 0xBE, 0xAA, 0xA9, 0xA0, 0xFF, 0xA0, 0xAA, 0xAA, 0x3E, 0x00, 0x08, 0x08, 0x09, 0x0A, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x08,/*叟4073*/},\n        {\n\n                0x9C, 0x40, 0x3F, 0x44, 0xEA, 0xAB, 0xEA, 0x44, 0x3F, 0x44, 0x82, 0x08, 0x09, 0x0B, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0B, 0x08, 0x08,/*燮4074*/},\n        {\n\n                0x80, 0x5F, 0xF5, 0x55, 0x5F, 0x60, 0xDF, 0x55, 0x55, 0x5F, 0x00, 0x08, 0x09, 0x0B, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x08,/*矍4075*/},\n        {\n\n                0x02, 0x32, 0x2A, 0xE6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*廴4076*/},\n        {\n\n                0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x04, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*凵4077*/},\n        {\n\n                0xFC, 0x80, 0x48, 0x38, 0x00, 0xFF, 0x28, 0x44, 0x80, 0x00, 0xFC, 0x07, 0x04, 0x04, 0x04, 0x05,\n                0x05, 0x04, 0x04, 0x04, 0x04, 0x0F,/*凼4078*/},\n        {\n\n                0x00, 0x7E, 0x48, 0x62, 0x54, 0x69, 0x54, 0x62, 0x48, 0x7E, 0x00, 0x00, 0x07, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x09, 0x09, 0x09, 0x0C,/*鬯4079*/},\n        {\n\n                0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x40, 0x80, 0x00, 0x00, 0x02, 0x03, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x02, 0x03, 0x0E,/*厶4080*/},\n        {\n\n                0x80, 0x88, 0x8C, 0xEB, 0x88, 0x88, 0x88, 0xE8, 0x8C, 0x98, 0x80, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*弁4081*/},\n        {\n\n                0x10, 0x94, 0xD6, 0xB5, 0x9C, 0x94, 0x94, 0xB4, 0xD6, 0x9C, 0x10, 0x01, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x00, 0x01,/*畚4082*/},\n        {\n\n                0x22, 0x52, 0xCA, 0x56, 0x20, 0xA4, 0x34, 0xAD, 0x26, 0xB4, 0x64, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x07, 0x00, 0x07, 0x00, 0x0F, 0x08,/*巯4083*/},\n        {\n\n                0x04, 0x44, 0x2A, 0x19, 0x08, 0x88, 0x48, 0x49, 0x3A, 0x04, 0x04, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*坌4084*/},\n        {\n\n                0x20, 0x25, 0x29, 0x21, 0x3F, 0xA1, 0x3F, 0x21, 0x29, 0x25, 0x20, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*垩4085*/},\n        {\n\n                0x08, 0x04, 0xFE, 0x05, 0x04, 0x84, 0x5F, 0x22, 0x52, 0x8B, 0xE2, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*垡4086*/},\n        {\n\n                0x22, 0xAE, 0xEA, 0x3B, 0x2E, 0xA2, 0x54, 0x3F, 0x24, 0x7C, 0xC0, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*塾4087*/},\n        {\n\n                0xC2, 0xBE, 0xAA, 0xFF, 0xAA, 0xBE, 0xCA, 0xB7, 0x51, 0xB7, 0x84, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*墼4088*/},\n        {\n\n                0xAA, 0xB6, 0xB2, 0x6A, 0x22, 0x13, 0xFE, 0xAA, 0xFA, 0xAE, 0xAA, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*壅4089*/},\n        {\n\n                0x2C, 0xF4, 0xAF, 0xAD, 0xF5, 0x2C, 0x82, 0x5E, 0x22, 0x5E, 0x80, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*壑4090*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x20, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x20, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*圩4091*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x10, 0xD2, 0xB2, 0x92, 0x92, 0x92, 0x10, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x07, 0x00,/*圬4092*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x10, 0x28, 0x27, 0xA4, 0x64, 0x24, 0x04, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x06, 0x09, 0x08, 0x08, 0x08, 0x0E,/*圪4093*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x00, 0xFF, 0x00, 0x00, 0xFE, 0x00, 0x00, 0xFF, 0x02, 0x03, 0x09, 0x04, 0x03,\n                0x00, 0x00, 0x07, 0x00, 0x00, 0x0F,/*圳4094*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0xFC, 0x04, 0x05, 0x06, 0x04, 0x04, 0x02, 0x02, 0x01, 0x01, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*圹4095*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0xE2, 0x22, 0x22, 0x22, 0x3E, 0x00, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*圮4096*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0xFE, 0x42, 0x42, 0x42, 0x7E, 0x00, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*圯4097*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x00, 0xFE, 0x02, 0x22, 0xFA, 0x22, 0x22, 0xE2, 0x02, 0x03, 0x09, 0x04, 0x0B,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*坜4098*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x00, 0x00,/*圻4099*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x00, 0xFE, 0x12, 0xF2, 0x12, 0x91, 0x71, 0x04, 0x04, 0x03, 0x0A, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*坂4100*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x04, 0xFF, 0x44, 0x44, 0x44, 0xFF, 0x04, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*坩4101*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0x08, 0xFF, 0x08, 0xF9, 0x8A, 0x48, 0x02, 0x02, 0x01, 0x09, 0x04,\n                0x03, 0x04, 0x02, 0x07, 0x08, 0x0E,/*垅4102*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x00, 0xC0, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*坫4103*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0xF0, 0x90, 0x9F, 0x92, 0x92, 0xF2, 0x02, 0x02, 0x01, 0x01, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x01,/*垆4104*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0xFE, 0x12, 0x92, 0xF1, 0x11, 0x10, 0x02, 0x02, 0x01, 0x01, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x01, 0x02,/*坼4105*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x00, 0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x08, 0x03, 0x04, 0x0E,/*坻4106*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x24, 0x0C, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x07, 0x09, 0x08, 0x08, 0x08, 0x0E,/*坨4107*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x00, 0xFE, 0x12, 0xD2, 0x12, 0x92, 0x5E, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x07, 0x00, 0x07, 0x09, 0x08, 0x0E,/*坭4108*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xA0, 0x7E, 0xAA, 0x32, 0x22, 0xFE, 0x20, 0x04, 0x07, 0x02, 0x00, 0x03,\n                0x02, 0x02, 0x0B, 0x0A, 0x07, 0x02,/*坶4109*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0x38, 0xE7, 0x30, 0x08, 0xFF, 0x08, 0xF8, 0x04, 0x07, 0x02, 0x00, 0x03,\n                0x02, 0x0B, 0x06, 0x01, 0x08, 0x0F,/*坳4110*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x22, 0x42, 0xFE, 0x02, 0x02, 0xFE, 0x42, 0x22, 0x04, 0x07, 0x02, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x0F, 0x08, 0x08,/*垭4111*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x00, 0x32, 0x2A, 0xE6, 0x22, 0x32, 0x62, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*垤4112*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFE, 0x02, 0xEA, 0x2A, 0xEA, 0x02, 0xFE, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*垌4113*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x00, 0x2E, 0x28, 0x2F, 0x28, 0xEE, 0x00, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x07, 0x09, 0x09, 0x09, 0x09, 0x0C,/*垲4114*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0x32, 0xCE, 0x00, 0xF2, 0x02, 0xFF, 0x11, 0x04, 0x07, 0x02, 0x00, 0x0A,\n                0x07, 0x08, 0x09, 0x09, 0x09, 0x09,/*埏4115*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFC, 0x04, 0xE6, 0x25, 0xE4, 0x04, 0xFC, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*垧4116*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xE4, 0x04, 0x15, 0xE6, 0x14, 0x04, 0xE4, 0x04, 0x07, 0x02, 0x00, 0x07,\n                0x04, 0x05, 0x04, 0x05, 0x04, 0x0F,/*垴4117*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x44, 0x04, 0x04, 0x03, 0x02, 0x09,\n                0x09, 0x04, 0x02, 0x03, 0x04, 0x08,/*垓4118*/},\n        {\n\n                0x08, 0x08, 0xFF, 0x08, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x02, 0x02, 0x01, 0x01, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*垠4119*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x20, 0x2F, 0x29, 0xE9, 0x29, 0x2F, 0x20, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*埕4120*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFE, 0x22, 0xFE, 0x48, 0x88, 0xFF, 0x08, 0x04, 0x07, 0x02, 0x00, 0x07,\n                0x02, 0x07, 0x00, 0x08, 0x0F, 0x00,/*埘4121*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xE0, 0x2F, 0x29, 0xF9, 0x29, 0x2F, 0xE0, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x02, 0x01, 0x00, 0x01, 0x0A, 0x0F,/*埚4122*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x00, 0xF0, 0x17, 0x15, 0xD5, 0x15, 0x17, 0xF0, 0x02, 0x03, 0x01, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*埙4123*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x4A, 0x52, 0x46, 0x4A, 0x41, 0xE9, 0x45, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x01, 0x02, 0x00, 0x08, 0x0F, 0x00,/*埒4124*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x8C, 0xA4, 0xA5, 0xA6, 0xA4, 0xA4, 0x8C, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*垸4125*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xFA, 0x02, 0x04, 0x07, 0x02, 0x08, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x08,/*埴4126*/},\n        {\n\n                0x08, 0xFF, 0x28, 0x12, 0xEA, 0xA6, 0xF3, 0xA6, 0xEA, 0x12, 0x10, 0x02, 0x03, 0x01, 0x00, 0x07,\n                0x02, 0x07, 0x0A, 0x0B, 0x08, 0x0E,/*埯4127*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x80, 0x5F, 0xF5, 0x55, 0xD5, 0x5F, 0xC0, 0x04, 0x04, 0x03, 0x02, 0x02,\n                0x09, 0x04, 0x02, 0x09, 0x08, 0x07,/*埸4128*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x00, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x00, 0x02, 0x03, 0x01, 0x02, 0x03,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*埤4129*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0x08, 0x14, 0x92, 0x19, 0x52, 0x34, 0x08, 0x04, 0x07, 0x02, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*埝4130*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x92, 0xFE, 0x04, 0x07, 0x02, 0x08, 0x07,\n                0x08, 0x0F, 0x08, 0x07, 0x08, 0x0F,/*堋4131*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x08, 0xF4, 0x93, 0xD2, 0xBA, 0x96, 0xF0, 0x00, 0x04, 0x07, 0x02, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x08, 0x0A, 0x0C,/*堍4132*/},\n        {\n\n                0x10, 0xFF, 0x10, 0xC0, 0x55, 0x55, 0xD5, 0x55, 0x55, 0x5F, 0xC0, 0x04, 0x07, 0x02, 0x00, 0x07,\n                0x01, 0x0F, 0x01, 0x05, 0x07, 0x00,/*埽4133*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x48, 0xAA, 0x2A, 0xFF, 0x2A, 0xAA, 0x7E, 0x08, 0x04, 0x07, 0x02, 0x04, 0x02,\n                0x09, 0x0F, 0x01, 0x02, 0x04, 0x04,/*埭4134*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xFE, 0x0A, 0xEA, 0x8A, 0xFA, 0x8A, 0xEE, 0x04, 0x07, 0x02, 0x08, 0x07,\n                0x00, 0x0E, 0x08, 0x0F, 0x08, 0x0E,/*堀4135*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x04, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x04, 0x04, 0x03, 0x02, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*堞4136*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0x7A, 0x4A, 0x7E, 0xCA, 0x7E, 0x4A, 0x7A, 0x04, 0x07, 0x02, 0x08, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x09,/*堙4137*/},\n        {\n\n                0x10, 0x10, 0xFF, 0x10, 0x2F, 0x29, 0xEF, 0xB9, 0xAF, 0xA9, 0xAF, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*塄4138*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x10, 0xFC, 0x03, 0x48, 0x3A, 0xEA, 0x2E, 0x28, 0x02, 0x03, 0x01, 0x00, 0x0F,\n                0x00, 0x09, 0x05, 0x03, 0x05, 0x09,/*堠4139*/},\n        {\n\n                0x10, 0xFF, 0x10, 0x00, 0xC1, 0x5D, 0xD5, 0x55, 0xD5, 0x5D, 0xC1, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x00, 0x02, 0x0F, 0x02, 0x08, 0x0F,/*塥4140*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xFF, 0x01, 0xF9, 0xAD, 0xAB, 0xA9, 0xF9, 0x01, 0x02, 0x03, 0x09, 0x07, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*塬4141*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x70, 0x5F, 0x75, 0x55, 0x55, 0x75, 0x5F, 0x70, 0x02, 0x03, 0x01, 0x08, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*墁4142*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xFE, 0x22, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x02, 0x03, 0x09, 0x07, 0x00,\n                0x0F, 0x02, 0x07, 0x0A, 0x0F, 0x00,/*墉4143*/},\n        {\n\n                0x10, 0xFF, 0x10, 0xA5, 0x88, 0xA5, 0xDF, 0xA1, 0xBF, 0x84, 0x98, 0x04, 0x07, 0x02, 0x04, 0x02,\n                0x01, 0x0F, 0x01, 0x02, 0x04, 0x04,/*墚4144*/},\n        {\n\n                0x08, 0xFF, 0x08, 0x00, 0xFF, 0x05, 0xAD, 0x15, 0xBD, 0x15, 0x2F, 0x02, 0x03, 0x09, 0x06, 0x01,\n                0x06, 0x05, 0x05, 0x0F, 0x05, 0x05,/*墀4145*/},\n        {\n\n                0x42, 0x3A, 0xAA, 0xFF, 0xAA, 0xFA, 0xA4, 0xEF, 0x95, 0x2F, 0x24, 0x02, 0x01, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x01, 0x02,/*馨4146*/},\n        {\n\n                0x0A, 0x3A, 0xEF, 0x7A, 0x4A, 0xE0, 0x42, 0x5A, 0xEF, 0x5A, 0x82, 0x04, 0x04, 0x07, 0x05, 0x07,\n                0x05, 0x0D, 0x05, 0x07, 0x04, 0x04,/*鼙4147*/},\n        {\n\n                0x1A, 0xEA, 0xAF, 0xEA, 0x1A, 0x21, 0x92, 0x48, 0x37, 0x44, 0x8C, 0x08, 0x0A, 0x0C, 0x0A, 0x08,\n                0x04, 0x06, 0x08, 0x0D, 0x00, 0x0C,/*懿4148*/},\n        {\n\n                0x02, 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x07, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*艹4149*/},\n        {\n\n                0x02, 0x22, 0x22, 0x27, 0xFA, 0x22, 0x22, 0x27, 0xE2, 0x02, 0x02, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x00, 0x07, 0x08, 0x0E,/*艽4150*/},\n        {\n\n                0x02, 0x12, 0x12, 0xF7, 0x12, 0x12, 0x12, 0xD7, 0xB2, 0x92, 0x82, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x08, 0x07,/*艿4151*/},\n        {\n\n                0x04, 0x84, 0x84, 0x8F, 0x84, 0xF4, 0x84, 0x8F, 0x84, 0x84, 0x04, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*芏4152*/},\n        {\n\n                0x82, 0x92, 0x92, 0x97, 0x92, 0xF2, 0x92, 0x97, 0x8A, 0x8A, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*芊4153*/},\n        {\n\n                0x02, 0x12, 0x12, 0xF7, 0x12, 0x92, 0x12, 0x77, 0x52, 0xC2, 0x02, 0x08, 0x04, 0x03, 0x08, 0x08,\n                0x04, 0x05, 0x02, 0x05, 0x08, 0x08,/*芨4154*/},\n        {\n\n                0x02, 0xA2, 0xA2, 0x27, 0xFA, 0x22, 0x22, 0x27, 0xE2, 0x02, 0x02, 0x08, 0x08, 0x04, 0x03, 0x02,\n                0x04, 0x00, 0x00, 0x07, 0x08, 0x0E,/*芄4155*/},\n        {\n\n                0x02, 0xD2, 0x52, 0x57, 0x52, 0x52, 0x52, 0x57, 0x52, 0x72, 0x02, 0x00, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x09, 0x07,/*芎4156*/},\n        {\n\n                0x02, 0x92, 0x92, 0x97, 0x92, 0x92, 0x92, 0x97, 0x92, 0xF2, 0x02, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0C,/*芑4157*/},\n        {\n\n                0x02, 0x02, 0x22, 0xB7, 0xAA, 0x62, 0x62, 0x27, 0x12, 0x82, 0x42, 0x08, 0x09, 0x09, 0x09, 0x05,\n                0x05, 0x03, 0x03, 0x01, 0x00, 0x00,/*芗4158*/},\n        {\n\n                0x82, 0x92, 0x92, 0x97, 0x92, 0xFA, 0x92, 0x97, 0x92, 0x92, 0x82, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*芙4159*/},\n        {\n\n                0x82, 0x92, 0x92, 0x97, 0x92, 0x92, 0x92, 0x97, 0x92, 0x92, 0x82, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*芫4160*/},\n        {\n\n                0x82, 0x92, 0x92, 0x97, 0x92, 0x92, 0x92, 0x97, 0x92, 0x92, 0x82, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x04, 0x06, 0x0C, 0x00,/*芸4161*/},\n        {\n\n                0x12, 0xD2, 0x52, 0x57, 0x52, 0xFA, 0x52, 0x57, 0x52, 0xD2, 0x12, 0x00, 0x07, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x04, 0x07, 0x00,/*芾4162*/},\n        {\n\n                0x12, 0x52, 0xD2, 0x57, 0x52, 0x7A, 0x52, 0x57, 0xD2, 0x12, 0x12, 0x08, 0x08, 0x04, 0x05, 0x02,\n                0x02, 0x02, 0x05, 0x04, 0x08, 0x08,/*芰4163*/},\n        {\n\n                0x02, 0xF2, 0x12, 0x97, 0x92, 0xF2, 0x92, 0x97, 0x92, 0x92, 0x12, 0x08, 0x07, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x08, 0x08, 0x07, 0x00,/*苈4164*/},\n        {\n\n                0x02, 0xF2, 0x12, 0xD7, 0x52, 0x52, 0x52, 0x57, 0x52, 0xD2, 0x12, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x08, 0x08, 0x08, 0x0A, 0x0B, 0x0C,/*苊4165*/},\n        {\n\n                0x02, 0xF2, 0x52, 0x57, 0x52, 0x52, 0x52, 0x57, 0x52, 0xD2, 0x12, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*苣4166*/},\n        {\n\n                0x02, 0xF2, 0x42, 0x47, 0x42, 0x02, 0xF2, 0x07, 0x82, 0x42, 0x22, 0x00, 0x0F, 0x08, 0x04, 0x04,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*芘4167*/},\n        {\n\n                0x04, 0x04, 0xC4, 0x0F, 0x04, 0xF4, 0x84, 0x8F, 0x84, 0x84, 0x04, 0x08, 0x08, 0x0F, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*芷4168*/},\n        {\n\n                0x02, 0xF2, 0x17, 0x12, 0x92, 0x7A, 0x92, 0x12, 0x17, 0xF2, 0x02, 0x00, 0x0F, 0x00, 0x01, 0x00,\n                0x00, 0x00, 0x01, 0x08, 0x0F, 0x00,/*芮4169*/},\n        {\n\n                0x02, 0xF2, 0x12, 0x17, 0x12, 0xF2, 0x12, 0x17, 0x12, 0xF2, 0x02, 0x08, 0x09, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x09, 0x0E,/*苋4170*/},\n        {\n\n                0x82, 0x82, 0xFA, 0xA7, 0xA2, 0xA2, 0x92, 0x97, 0x8A, 0x82, 0x82, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*苌4171*/},\n        {\n\n                0x02, 0x02, 0x82, 0x77, 0x82, 0x02, 0x02, 0xF7, 0x02, 0x02, 0x02, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x05, 0x03, 0x00, 0x03, 0x04, 0x08,/*苁4172*/},\n        {\n\n                0x42, 0x42, 0x22, 0x27, 0x12, 0x4A, 0x92, 0x27, 0x22, 0x42, 0x42, 0x00, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x09, 0x05, 0x03, 0x01, 0x00,/*芩4173*/},\n        {\n\n                0x42, 0x22, 0x1A, 0x97, 0x72, 0x12, 0xF2, 0x17, 0x12, 0xF2, 0x02, 0x02, 0x02, 0x09, 0x08, 0x04,\n                0x02, 0x09, 0x08, 0x08, 0x07, 0x00,/*芴4174*/},\n        {\n\n                0x42, 0x22, 0x1A, 0x17, 0x12, 0xD2, 0x12, 0x17, 0x12, 0x52, 0x32, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*芡4175*/},\n        {\n\n                0x02, 0xF2, 0x92, 0x97, 0x92, 0x92, 0xF2, 0x8F, 0x8A, 0x8A, 0x82, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x0E,/*芪4176*/},\n        {\n\n                0x42, 0xA2, 0x9A, 0x8F, 0x8A, 0x8A, 0x8A, 0x8F, 0xBA, 0x42, 0x42, 0x08, 0x08, 0x09, 0x0A, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x08,/*芟4177*/},\n        {\n\n                0x22, 0x22, 0x22, 0x27, 0xE2, 0x2A, 0xB2, 0x27, 0x22, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x01, 0x02, 0x00, 0x00,/*苄4178*/},\n        {\n\n                0xE2, 0x22, 0x27, 0x22, 0x2A, 0x32, 0x22, 0x22, 0x27, 0x22, 0xE2, 0x08, 0x08, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*苎4179*/},\n        {\n\n                0x02, 0x12, 0x12, 0xD7, 0xB2, 0x92, 0x02, 0xF7, 0x02, 0x02, 0x02, 0x01, 0x01, 0x09, 0x0F, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*芤4180*/},\n        {\n\n                0x02, 0xF2, 0x02, 0x07, 0x12, 0x62, 0x02, 0x87, 0x72, 0x02, 0x02, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x02, 0x01, 0x01, 0x02, 0x0C,/*苡4181*/},\n        {\n\n                0x12, 0x92, 0x92, 0x97, 0x92, 0xFA, 0x92, 0x97, 0x92, 0x92, 0x12, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*茉4182*/},\n        {\n\n                0x12, 0x12, 0xFA, 0x97, 0x92, 0x92, 0x92, 0x97, 0xFA, 0x12, 0x12, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x0F, 0x00, 0x00,/*苷4183*/},\n        {\n\n                0x02, 0x12, 0x12, 0x97, 0x52, 0xF2, 0x12, 0x57, 0x92, 0x12, 0x02, 0x08, 0x09, 0x09, 0x08, 0x08,\n                0x0B, 0x08, 0x08, 0x08, 0x09, 0x08,/*苤4184*/},\n        {\n\n                0x22, 0x22, 0x27, 0xA2, 0x7A, 0x22, 0xE2, 0x2A, 0x37, 0xA2, 0x22, 0x08, 0x04, 0x02, 0x09, 0x08,\n                0x04, 0x07, 0x0A, 0x09, 0x08, 0x0E,/*茏4185*/},\n        {\n\n                0x22, 0x22, 0x27, 0xE2, 0xBA, 0xA2, 0xA2, 0xAA, 0xB7, 0xA2, 0x22, 0x08, 0x04, 0x03, 0x08, 0x09,\n                0x0A, 0x04, 0x04, 0x0A, 0x09, 0x08,/*茇4186*/},\n        {\n\n                0x02, 0xF2, 0x52, 0x57, 0x52, 0x52, 0x52, 0x57, 0x52, 0xF2, 0x02, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*苜4187*/},\n        {\n\n                0x02, 0xF2, 0x52, 0x57, 0x52, 0x52, 0x52, 0x57, 0x52, 0xF2, 0x02, 0x08, 0x0F, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x08,/*苴4188*/},\n        {\n\n                0x02, 0xF2, 0x52, 0x57, 0x52, 0xFE, 0x52, 0x57, 0x52, 0xF2, 0x02, 0x01, 0x0F, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x0F, 0x01,/*苒4189*/},\n        {\n\n                0x02, 0xF2, 0x12, 0xD7, 0x52, 0x52, 0x52, 0xD7, 0x12, 0xF2, 0x02, 0x00, 0x0F, 0x00, 0x03, 0x02,\n                0x02, 0x02, 0x03, 0x08, 0x0F, 0x00,/*苘4190*/},\n        {\n\n                0x82, 0x42, 0xE2, 0x17, 0x42, 0x42, 0x42, 0xF7, 0x42, 0x42, 0x42, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x00,/*茌4191*/},\n        {\n\n                0x82, 0x42, 0xE2, 0x17, 0x42, 0x42, 0x42, 0x47, 0xF2, 0x42, 0x42, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x02, 0x08, 0x08, 0x0F, 0x00, 0x00,/*苻4192*/},\n        {\n\n                0x42, 0x42, 0xA2, 0xA7, 0x92, 0xCA, 0x92, 0xA7, 0xA2, 0x42, 0x42, 0x00, 0x00, 0x00, 0x02, 0x02,\n                0x04, 0x04, 0x0A, 0x01, 0x00, 0x00,/*苓4193*/},\n        {\n\n                0x02, 0x02, 0xF2, 0x17, 0x32, 0x5A, 0x12, 0x57, 0x72, 0x02, 0x02, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x09, 0x09, 0x07,/*茑4194*/},\n        {\n\n                0xF2, 0x52, 0x52, 0x4F, 0x4A, 0x02, 0xF2, 0x17, 0x12, 0x12, 0xF2, 0x03, 0x02, 0x02, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x00, 0x02, 0x03,/*茚4195*/},\n        {\n\n                0xF2, 0x12, 0x0A, 0x8F, 0xE2, 0x02, 0xF2, 0x17, 0x12, 0x12, 0xF2, 0x03, 0x02, 0x09, 0x04, 0x03,\n                0x00, 0x0F, 0x00, 0x00, 0x02, 0x03,/*茆4196*/},\n        {\n\n                0x32, 0x12, 0x12, 0x17, 0x12, 0xD2, 0x12, 0x17, 0x12, 0x12, 0x32, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*茔4197*/},\n        {\n\n                0x1A, 0x2A, 0x2A, 0xEF, 0x2A, 0x2A, 0x2A, 0x2F, 0xEA, 0x0A, 0x1A, 0x01, 0x01, 0x01, 0x0F, 0x01,\n                0x01, 0x01, 0x00, 0x03, 0x04, 0x0E,/*茕4198*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xEA, 0xAF, 0xAA, 0xBA, 0x82, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x0E,/*苠4199*/},\n        {\n\n                0x42, 0x4A, 0xAA, 0x9F, 0x8A, 0x8A, 0x8A, 0xAF, 0xAA, 0x9A, 0x02, 0x00, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*苕4200*/},\n        {\n\n                0x0A, 0xEA, 0x2A, 0x2F, 0xFA, 0x2A, 0xFA, 0x2F, 0x2A, 0xEA, 0x0A, 0x00, 0x0F, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x05, 0x05, 0x0F, 0x00,/*茜4201*/},\n        {\n\n                0x0A, 0xEA, 0xAA, 0xAF, 0xAA, 0xFE, 0xAA, 0xAF, 0xAA, 0xBA, 0x8A, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x06, 0x0A, 0x09,/*荑4202*/},\n        {\n\n                0x12, 0x52, 0x57, 0x52, 0x5E, 0x32, 0x2A, 0x2A, 0x5F, 0x4A, 0x6A, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x07, 0x09, 0x09, 0x09, 0x0D,/*荛4203*/},\n        {\n\n                0x02, 0xFA, 0x92, 0x57, 0x52, 0x02, 0x7A, 0xA7, 0x92, 0x8A, 0xC2, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*荜4204*/},\n        {\n\n                0x02, 0xC2, 0x02, 0xF7, 0x82, 0x82, 0x02, 0xF7, 0x82, 0x42, 0x22, 0x08, 0x0F, 0x08, 0x07, 0x04,\n                0x04, 0x00, 0x07, 0x08, 0x08, 0x0E,/*茈4205*/},\n        {\n\n                0x02, 0x02, 0x7A, 0x4F, 0x4A, 0x4A, 0x4A, 0x4F, 0x7A, 0x02, 0x02, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x00,/*莒4206*/},\n        {\n\n                0x02, 0xFA, 0x0A, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0x0A, 0xFA, 0x02, 0x00, 0x0F, 0x00, 0x03, 0x02,\n                0x02, 0x02, 0x0B, 0x08, 0x0F, 0x00,/*茼4207*/},\n        {\n\n                0x02, 0xFA, 0x0A, 0xEF, 0x2A, 0x2A, 0x2A, 0xEF, 0x0A, 0xFA, 0x02, 0x00, 0x07, 0x04, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x04, 0x07, 0x00,/*茴4208*/},\n        {\n\n                0x82, 0xA2, 0x9A, 0x97, 0x92, 0xFA, 0x92, 0x97, 0x92, 0x92, 0x82, 0x04, 0x04, 0x02, 0x02, 0x01,\n                0x0F, 0x01, 0x02, 0x02, 0x04, 0x04,/*茱4209*/},\n        {\n\n                0x02, 0x92, 0xD2, 0xB7, 0x02, 0xA2, 0xA2, 0xE7, 0x92, 0x92, 0x02, 0x08, 0x0A, 0x04, 0x0B, 0x08,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x08,/*莛4210*/},\n        {\n\n                0x42, 0x42, 0x52, 0xD7, 0x52, 0x72, 0x4A, 0xCF, 0x4A, 0x42, 0x42, 0x02, 0x02, 0x09, 0x06, 0x00,\n                0x00, 0x00, 0x0E, 0x01, 0x02, 0x02,/*荞4211*/},\n        {\n\n                0x42, 0x22, 0xF7, 0x2A, 0x22, 0x22, 0xFA, 0x22, 0x2F, 0x32, 0x22, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x00, 0x03, 0x04, 0x08, 0x08,/*茯4212*/},\n        {\n\n                0x42, 0x22, 0xF2, 0x0F, 0x82, 0x92, 0x92, 0xF7, 0x8A, 0x8A, 0x82, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x00,/*荏4213*/},\n        {\n\n                0x42, 0x22, 0x92, 0x4F, 0x02, 0x82, 0x92, 0x97, 0x92, 0x92, 0x82, 0x02, 0x01, 0x0F, 0x00, 0x00,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*荇4214*/},\n        {\n\n                0x22, 0x22, 0x52, 0x57, 0x4A, 0xC6, 0x4A, 0x57, 0x52, 0x22, 0x22, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*荃4215*/},\n        {\n\n                0xA2, 0xA2, 0x92, 0xB7, 0xAA, 0xA6, 0xAA, 0xB7, 0x92, 0xA2, 0xA2, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x04, 0x06, 0x0C, 0x00,/*荟4216*/},\n        {\n\n                0x42, 0x22, 0xDA, 0x57, 0x52, 0x52, 0x52, 0xD7, 0x12, 0x12, 0xF2, 0x00, 0x00, 0x0F, 0x05, 0x05,\n                0x05, 0x05, 0x0F, 0x08, 0x08, 0x07,/*荀4217*/},\n        {\n\n                0x02, 0x42, 0x22, 0x57, 0x9A, 0x92, 0x52, 0x57, 0x32, 0x12, 0x02, 0x02, 0x02, 0x0F, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x00,/*茗4218*/},\n        {\n\n                0x92, 0x92, 0xB2, 0x57, 0x52, 0x5A, 0x52, 0x57, 0xB2, 0x92, 0x92, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*荠4219*/},\n        {\n\n                0x12, 0x92, 0x57, 0xB2, 0x12, 0x1A, 0x12, 0xB2, 0x57, 0x92, 0x12, 0x08, 0x08, 0x08, 0x04, 0x05,\n                0x02, 0x05, 0x04, 0x08, 0x08, 0x08,/*茭4220*/},\n        {\n\n                0x12, 0x92, 0xD7, 0xB2, 0x96, 0x9A, 0x92, 0x92, 0xD7, 0x92, 0x12, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x09, 0x0C,/*茺4221*/},\n        {\n\n                0x4A, 0x92, 0x02, 0x17, 0x12, 0x12, 0xF2, 0x17, 0x12, 0x12, 0x02, 0x08, 0x04, 0x0A, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x08,/*茳4222*/},\n        {\n\n                0x1A, 0x8A, 0x6A, 0x4F, 0x4A, 0xEA, 0x4A, 0x4F, 0x4A, 0x4A, 0x1A, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*荦4223*/},\n        {\n\n                0x1A, 0x4A, 0x4A, 0xCF, 0x0A, 0xFA, 0xCA, 0x0F, 0x8A, 0x4A, 0x1A, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*荥4224*/},\n        {\n\n                0x02, 0x8A, 0xAA, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0xAA, 0xFA, 0x02, 0x02, 0x02, 0x06, 0x0A, 0x02,\n                0x02, 0x0A, 0x0A, 0x0F, 0x02, 0x02,/*荨4225*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0xAA, 0xFA, 0x02, 0x00, 0x0F, 0x08, 0x04, 0x04,\n                0x01, 0x02, 0x04, 0x04, 0x0A, 0x08,/*茛4226*/},\n        {\n\n                0x02, 0x02, 0xFA, 0x2F, 0xAA, 0xAA, 0x2A, 0x6F, 0xAA, 0x3A, 0x02, 0x02, 0x01, 0x00, 0x02, 0x02,\n                0x04, 0x05, 0x0A, 0x00, 0x01, 0x01,/*荩4227*/},\n        {\n\n                0x0A, 0x0A, 0x4A, 0x9F, 0x2A, 0x0A, 0xEA, 0x0F, 0x0A, 0x2A, 0x1A, 0x01, 0x09, 0x09, 0x05, 0x05,\n                0x03, 0x01, 0x03, 0x05, 0x05, 0x09,/*荬4228*/},\n        {\n\n                0x12, 0x12, 0xD2, 0xB7, 0x02, 0xC2, 0x02, 0xF7, 0x02, 0x42, 0x82, 0x01, 0x09, 0x0F, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*荪4229*/},\n        {\n\n                0x22, 0xB2, 0x6A, 0x27, 0x02, 0x12, 0x12, 0xF7, 0x12, 0x12, 0x02, 0x09, 0x09, 0x05, 0x05, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*荭4230*/},\n        {\n\n                0x22, 0xB2, 0x6A, 0x27, 0x02, 0xA2, 0x22, 0x27, 0x22, 0xFA, 0x22, 0x09, 0x09, 0x05, 0x05, 0x00,\n                0x00, 0x03, 0x08, 0x08, 0x0F, 0x00,/*荮4231*/},\n        {\n\n                0x42, 0x42, 0xFA, 0x47, 0x42, 0x22, 0x1A, 0xD7, 0x12, 0x52, 0x32, 0x04, 0x04, 0x07, 0x02, 0x0A,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*莰4232*/},\n        {\n\n                0x62, 0x2A, 0xAA, 0xAF, 0xAA, 0xBE, 0xAA, 0xAF, 0x2A, 0x2A, 0x62, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0E, 0x03, 0x02, 0x02, 0x02, 0x02,/*荸4233*/},\n        {\n\n                0xF2, 0x92, 0x92, 0xF7, 0x02, 0x22, 0xA2, 0x27, 0x22, 0xFA, 0x22, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x00, 0x00, 0x09, 0x08, 0x0F, 0x00,/*莳4234*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xAF, 0xAA, 0xEA, 0xAA, 0xAF, 0xAA, 0xBA, 0x82, 0x0F, 0x00, 0x00, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x00, 0x08, 0x0F,/*莴4235*/},\n        {\n\n                0x22, 0xA2, 0x6A, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0x6A, 0xA2, 0x22, 0x01, 0x08, 0x08, 0x04, 0x03,\n                0x00, 0x0A, 0x0B, 0x0A, 0x06, 0x01,/*莠4236*/},\n        {\n\n                0x42, 0x52, 0x52, 0xF7, 0x4A, 0x42, 0xFA, 0x47, 0x4A, 0xD2, 0x42, 0x00, 0x02, 0x0A, 0x0F, 0x01,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x0E,/*莪4237*/},\n        {\n\n                0x82, 0x92, 0xEA, 0xAF, 0xAA, 0xEA, 0xAA, 0xAF, 0xEA, 0x8A, 0x82, 0x00, 0x03, 0x02, 0x02, 0x03,\n                0x0A, 0x0A, 0x0A, 0x07, 0x02, 0x00,/*莓4238*/},\n        {\n\n                0x42, 0xE2, 0x1A, 0xE7, 0x02, 0x42, 0xB2, 0x2F, 0x22, 0xE2, 0x22, 0x00, 0x0F, 0x00, 0x03, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*莜4239*/},\n        {\n\n                0x82, 0xE2, 0x1A, 0x07, 0xA2, 0x22, 0x2A, 0x37, 0x22, 0xA2, 0x02, 0x00, 0x0F, 0x00, 0x08, 0x08,\n                0x0B, 0x08, 0x08, 0x0E, 0x09, 0x08,/*莅4240*/},\n        {\n\n                0x22, 0xA2, 0x92, 0xB7, 0xAA, 0xE6, 0xAA, 0xB7, 0x92, 0xA2, 0x22, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*荼4241*/},\n        {\n\n                0x42, 0x42, 0xA2, 0xA7, 0x92, 0x8A, 0x92, 0xA7, 0xA2, 0x42, 0x42, 0x08, 0x08, 0x0A, 0x0C, 0x09,\n                0x0A, 0x08, 0x0C, 0x0A, 0x08, 0x08,/*莶4242*/},\n        {\n\n                0x12, 0x32, 0xD2, 0x97, 0xB2, 0xD2, 0x92, 0xCF, 0xAA, 0x0A, 0x0A, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0E, 0x02, 0x03, 0x02, 0x02, 0x02,/*莩4243*/},\n        {\n\n                0x12, 0x32, 0x52, 0x17, 0xB2, 0x52, 0x0A, 0x0F, 0x4A, 0x2A, 0x0A, 0x01, 0x09, 0x09, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*荽4244*/},\n        {\n\n                0x42, 0x2A, 0x92, 0xEF, 0x02, 0x22, 0xFA, 0x27, 0xE2, 0x2A, 0x32, 0x02, 0x09, 0x08, 0x07, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*莸4245*/},\n        {\n\n                0x42, 0x2A, 0x97, 0xEA, 0x82, 0x62, 0x02, 0xFA, 0x07, 0x42, 0x22, 0x02, 0x09, 0x08, 0x07, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*荻4246*/},\n        {\n\n                0x82, 0x92, 0xB7, 0xD2, 0x92, 0x9A, 0x92, 0xD2, 0xB7, 0x92, 0x82, 0x00, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x00,/*莘4247*/},\n        {\n\n                0x32, 0x12, 0x52, 0x57, 0x52, 0x5A, 0x52, 0x57, 0x52, 0x12, 0x32, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x07, 0x09, 0x09, 0x09, 0x0D,/*莞4248*/},\n        {\n\n                0x02, 0xF2, 0x52, 0x57, 0x52, 0x5A, 0x52, 0x57, 0x52, 0xF2, 0x02, 0x00, 0x0F, 0x09, 0x05, 0x05,\n                0x01, 0x03, 0x05, 0x05, 0x0B, 0x08,/*莨4249*/},\n        {\n\n                0x1A, 0x0A, 0xEA, 0x2F, 0x7A, 0xAA, 0x2A, 0xAF, 0xEA, 0x0A, 0x1A, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x01, 0x09, 0x0F,/*莺4250*/},\n        {\n\n                0x22, 0xB2, 0x6A, 0x27, 0x12, 0xD2, 0x12, 0xFF, 0x12, 0xD2, 0x12, 0x09, 0x09, 0x05, 0x05, 0x00,\n                0x01, 0x01, 0x07, 0x09, 0x09, 0x0C,/*莼4251*/},\n        {\n\n                0x82, 0xAA, 0xAA, 0xAF, 0xAA, 0xFE, 0xAA, 0xAF, 0xAA, 0xAA, 0x82, 0x00, 0x00, 0x0F, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0F, 0x00, 0x00,/*菁4252*/},\n        {\n\n                0x0A, 0x0A, 0xFE, 0xAB, 0xAA, 0xAA, 0xAA, 0xAB, 0xFE, 0x0A, 0x0A, 0x02, 0x0A, 0x07, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x07, 0x0A, 0x02,/*萁4253*/},\n        {\n\n                0x22, 0xA2, 0xFA, 0xA7, 0x22, 0xF2, 0x92, 0x97, 0x8A, 0x8A, 0x82, 0x01, 0x00, 0x0F, 0x00, 0x09,\n                0x07, 0x00, 0x00, 0x0F, 0x00, 0x00,/*菥4254*/},\n        {\n\n                0x22, 0xA2, 0xFA, 0xA7, 0x02, 0x42, 0x32, 0x87, 0x02, 0x32, 0x42, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*菘4255*/},\n        {\n\n                0x02, 0xE2, 0xAF, 0xAA, 0xAA, 0xFA, 0xAA, 0xAA, 0xAF, 0xE2, 0x02, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*堇4256*/},\n        {\n\n                0x92, 0x92, 0x52, 0x37, 0x52, 0x5A, 0x52, 0x37, 0x52, 0x92, 0x92, 0x00, 0x08, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x08, 0x00,/*萘4257*/},\n        {\n\n                0x42, 0x52, 0x52, 0x57, 0xFA, 0x52, 0x52, 0x57, 0xF2, 0x42, 0x42, 0x09, 0x09, 0x0B, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*萋4258*/},\n        {\n\n                0x22, 0x22, 0xFA, 0xA7, 0x22, 0xE2, 0xBA, 0xA7, 0xAA, 0xB2, 0x22, 0x01, 0x09, 0x0F, 0x04, 0x03,\n                0x08, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*菝4259*/},\n        {\n\n                0x42, 0x42, 0xFA, 0x57, 0x52, 0x02, 0xF2, 0x17, 0x12, 0xF2, 0x02, 0x02, 0x09, 0x0F, 0x01, 0x02,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*菽4260*/},\n        {\n\n                0x02, 0x82, 0xFA, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0xFA, 0x82, 0x02, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*菖4261*/},\n        {\n\n                0xE2, 0x22, 0xFA, 0x27, 0xE2, 0x02, 0x82, 0x87, 0xFA, 0xA2, 0xA2, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*萜4262*/},\n        {\n\n                0x02, 0xF2, 0x52, 0x57, 0x0A, 0xFE, 0x02, 0x57, 0x52, 0xF2, 0x02, 0x08, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x08,/*萸4263*/},\n        {\n\n                0x42, 0x22, 0xF7, 0x5A, 0x56, 0x52, 0xF6, 0x5A, 0x57, 0x52, 0x12, 0x00, 0x00, 0x0F, 0x05, 0x05,\n                0x05, 0x07, 0x05, 0x05, 0x05, 0x04,/*萑4264*/},\n        {\n\n                0x02, 0xF2, 0x52, 0x57, 0xDA, 0x72, 0x52, 0x57, 0x52, 0xF2, 0x02, 0x04, 0x05, 0x07, 0x05, 0x05,\n                0x05, 0x0F, 0x05, 0x05, 0x05, 0x04,/*萆4265*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAF, 0xFA, 0x02, 0xFA, 0x8F, 0xAA, 0xAA, 0x9A, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x0F, 0x00, 0x0B, 0x04, 0x0B,/*菔4266*/},\n        {\n\n                0x82, 0x42, 0xE7, 0x5A, 0x52, 0xD2, 0x52, 0x72, 0x47, 0xC2, 0x02, 0x08, 0x08, 0x05, 0x05, 0x03,\n                0x01, 0x07, 0x09, 0x0B, 0x09, 0x0E,/*菟4267*/},\n        {\n\n                0x22, 0xD2, 0x4A, 0x4F, 0x2A, 0x0A, 0x4A, 0x6F, 0x5A, 0xC2, 0x02, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x04, 0x05, 0x05, 0x05, 0x0F, 0x00,/*萏4268*/},\n        {\n\n                0x02, 0x12, 0x92, 0x77, 0x92, 0x1A, 0x92, 0x77, 0x92, 0x12, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*萃4269*/},\n        {\n\n                0x22, 0xEA, 0xB2, 0xA7, 0xA2, 0x42, 0x22, 0x9F, 0x22, 0x42, 0x82, 0x08, 0x07, 0x08, 0x08, 0x07,\n                0x00, 0x02, 0x04, 0x09, 0x00, 0x00,/*菸4270*/},\n        {\n\n                0x42, 0x8A, 0x12, 0x07, 0xFA, 0x4A, 0x4A, 0x4F, 0x4A, 0xFA, 0x02, 0x08, 0x04, 0x02, 0x08, 0x0F,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x08,/*菹4271*/},\n        {\n\n                0x32, 0x52, 0x52, 0xD7, 0x52, 0x5A, 0x52, 0x57, 0x52, 0x52, 0x32, 0x04, 0x02, 0x0F, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*菪4272*/},\n        {\n\n                0x1A, 0x0A, 0xEA, 0xAF, 0xAA, 0xAE, 0xAA, 0xAF, 0xEA, 0x0A, 0x1A, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*菅4273*/},\n        {\n\n                0x32, 0x92, 0x72, 0x57, 0xD2, 0x1A, 0xD2, 0x57, 0x52, 0xD2, 0x32, 0x09, 0x08, 0x05, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x0A, 0x0B, 0x0C,/*菀4274*/},\n        {\n\n                0x1A, 0x0A, 0x4A, 0x6F, 0xDA, 0x4A, 0x4A, 0x2F, 0x8A, 0x0A, 0x1A, 0x00, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x00,/*萦4275*/},\n        {\n\n                0x12, 0xD2, 0xB2, 0x07, 0xF2, 0x12, 0xF2, 0x17, 0xEA, 0x0A, 0x02, 0x09, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x0F, 0x0A, 0x0C, 0x03, 0x0C,/*菰4276*/},\n        {\n\n                0xE2, 0x0A, 0x4A, 0x8F, 0x0A, 0xEA, 0x2A, 0x9F, 0x4A, 0x02, 0xE2, 0x0F, 0x08, 0x09, 0x08, 0x0A,\n                0x0B, 0x08, 0x08, 0x09, 0x08, 0x0F,/*菡4277*/},\n        {\n\n                0x8A, 0xAA, 0xFF, 0xAA, 0x8A, 0x02, 0x4A, 0x3A, 0x8F, 0x8A, 0x7A, 0x0A, 0x0A, 0x0B, 0x06, 0x02,\n                0x03, 0x02, 0x06, 0x0A, 0x0A, 0x0A,/*葜4278*/},\n        {\n\n                0x42, 0x52, 0x57, 0xFA, 0x52, 0x52, 0xA2, 0x22, 0x27, 0xFA, 0x22, 0x08, 0x09, 0x09, 0x07, 0x05,\n                0x05, 0x00, 0x09, 0x08, 0x0F, 0x00,/*葑4279*/},\n        {\n\n                0x02, 0x12, 0xFA, 0x57, 0x52, 0x52, 0x52, 0x57, 0xFA, 0x12, 0x02, 0x01, 0x0F, 0x09, 0x0D, 0x0B,\n                0x09, 0x09, 0x0B, 0x0D, 0x09, 0x01,/*葚4280*/},\n        {\n\n                0x22, 0xA2, 0xFA, 0xA7, 0x22, 0xF2, 0x52, 0x57, 0x52, 0x52, 0xF2, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*葙4281*/},\n        {\n\n                0x02, 0xF2, 0x57, 0xD2, 0x52, 0x52, 0x12, 0xFA, 0x17, 0xDA, 0x12, 0x08, 0x07, 0x09, 0x0B, 0x05,\n                0x0B, 0x08, 0x04, 0x03, 0x04, 0x0E,/*葳4282*/},\n        {\n\n                0x02, 0xFA, 0x0A, 0xEF, 0x2A, 0xAA, 0x2A, 0xFF, 0x0A, 0xEE, 0x0A, 0x08, 0x07, 0x00, 0x05, 0x02,\n                0x01, 0x0A, 0x05, 0x03, 0x04, 0x0E,/*蒇4283*/},\n        {\n\n                0x02, 0xBE, 0xAA, 0xAF, 0xAA, 0xC2, 0x9A, 0xB7, 0xAA, 0xAA, 0x32, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*蒈4284*/},\n        {\n\n                0x22, 0x22, 0xE7, 0xBA, 0xAA, 0xAA, 0xAA, 0xBA, 0xE7, 0x22, 0x22, 0x04, 0x04, 0x07, 0x04, 0x04,\n                0x02, 0x02, 0x02, 0x0F, 0x02, 0x02,/*葺4285*/},\n        {\n\n                0x22, 0xBA, 0xAA, 0xAF, 0xAA, 0xBE, 0xAA, 0xAF, 0xAA, 0xBA, 0x22, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*蒉4286*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x02, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*葸4287*/},\n        {\n\n                0x82, 0xBA, 0xAA, 0xAF, 0xBA, 0x82, 0xBA, 0xAF, 0xAA, 0xBA, 0x82, 0x00, 0x00, 0x03, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0A, 0x06, 0x00,/*萼4288*/},\n        {\n\n                0x82, 0x42, 0xE2, 0x1F, 0x82, 0xBA, 0xAA, 0xEF, 0xAA, 0xBA, 0x82, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*葆4289*/},\n        {\n\n                0xF2, 0x9A, 0x92, 0xF7, 0x02, 0xF2, 0x92, 0xF7, 0x92, 0xF2, 0x02, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*葩4290*/},\n        {\n\n                0x8A, 0x8A, 0xEA, 0xAF, 0xAA, 0xAE, 0xAA, 0xAF, 0xEA, 0x8A, 0x8A, 0x01, 0x02, 0x02, 0x02, 0x0A,\n                0x0E, 0x02, 0x02, 0x02, 0x02, 0x01,/*葶4291*/},\n        {\n\n                0x12, 0x52, 0x57, 0x3A, 0x92, 0x7E, 0x12, 0x3A, 0x57, 0x52, 0x12, 0x01, 0x09, 0x09, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*蒌4292*/},\n        {\n\n                0x42, 0x8A, 0x12, 0x07, 0xF2, 0x12, 0xD2, 0x57, 0xCA, 0x2A, 0x02, 0x08, 0x04, 0x02, 0x08, 0x07,\n                0x00, 0x0F, 0x04, 0x01, 0x06, 0x09,/*蒎4293*/},\n        {\n\n                0x1A, 0xEA, 0xAF, 0xAA, 0xAA, 0xAE, 0xAA, 0xAA, 0xAF, 0xEA, 0x1A, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*萱4294*/},\n        {\n\n                0x02, 0xFA, 0xAA, 0xAF, 0xBA, 0x02, 0xAA, 0xAF, 0xAA, 0xBA, 0x02, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x08, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*葭4295*/},\n        {\n\n                0x22, 0x22, 0xAA, 0xEF, 0xBA, 0xAE, 0xAA, 0x6F, 0xAA, 0x22, 0x22, 0x01, 0x0B, 0x0A, 0x06, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0B, 0x01,/*蓁4296*/},\n        {\n\n                0x22, 0x22, 0xAA, 0xAF, 0xEA, 0x3E, 0xAA, 0x77, 0x2A, 0x26, 0xA2, 0x01, 0x01, 0x0E, 0x0A, 0x0A,\n                0x0F, 0x0B, 0x0B, 0x0F, 0x01, 0x01,/*蓍4297*/},\n        {\n\n                0x02, 0xFA, 0x2A, 0x2F, 0xEA, 0xAA, 0x2A, 0x6F, 0xAA, 0xEA, 0xAA, 0x04, 0x03, 0x02, 0x06, 0x0A,\n                0x02, 0x02, 0x0A, 0x0F, 0x02, 0x02,/*蓐4298*/},\n        {\n\n                0x22, 0xBA, 0xEA, 0xAF, 0xAA, 0xBA, 0xAA, 0xAF, 0x6A, 0xBA, 0x22, 0x01, 0x08, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x03, 0x0A, 0x0E, 0x01,/*蓦4299*/},\n        {\n\n                0x02, 0xFA, 0x0A, 0xAF, 0x6A, 0x3A, 0x6A, 0xAF, 0x0A, 0xFA, 0x02, 0x08, 0x05, 0x01, 0x05, 0x0B,\n                0x0D, 0x09, 0x0D, 0x01, 0x05, 0x08,/*蒽4300*/},\n        {\n\n                0x42, 0xE2, 0x1A, 0x97, 0xB2, 0xD2, 0x92, 0x9F, 0xD2, 0xB2, 0x92, 0x00, 0x0F, 0x00, 0x00, 0x0E,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*蓓4301*/},\n        {\n\n                0x12, 0x92, 0xAA, 0xB7, 0xAA, 0x22, 0xA2, 0xB7, 0xAA, 0x92, 0x12, 0x00, 0x04, 0x05, 0x0A, 0x0F,\n                0x00, 0x04, 0x05, 0x0A, 0x0F, 0x00,/*蓊4302*/},\n        {\n\n                0x8A, 0x8A, 0xEA, 0xAF, 0xAA, 0xAE, 0xAA, 0xAF, 0xEA, 0x8A, 0x8A, 0x0F, 0x00, 0x00, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0E, 0x00, 0x08, 0x0F,/*蒿4303*/},\n        {\n\n                0x22, 0x42, 0xF2, 0x97, 0x52, 0x76, 0xDA, 0x57, 0x52, 0x52, 0x12, 0x0A, 0x05, 0x0B, 0x09, 0x05,\n                0x03, 0x01, 0x03, 0x05, 0x09, 0x09,/*蒺4304*/},\n        {\n\n                0x0A, 0x6A, 0x4F, 0x4A, 0x5A, 0xEE, 0x5A, 0x4A, 0x4F, 0x6A, 0x0A, 0x0F, 0x01, 0x01, 0x0D, 0x0B,\n                0x09, 0x0D, 0x09, 0x01, 0x09, 0x0F,/*蓠4305*/},\n        {\n\n                0x62, 0xAA, 0xAF, 0xBA, 0xEA, 0xAE, 0xAA, 0xBA, 0xAF, 0xAA, 0x62, 0x00, 0x08, 0x04, 0x03, 0x02,\n                0x02, 0x02, 0x0A, 0x0A, 0x06, 0x00,/*蒡4306*/},\n        {\n\n                0x52, 0x52, 0x57, 0x5A, 0xF2, 0x52, 0xF2, 0x5A, 0x57, 0xF2, 0x52, 0x08, 0x05, 0x03, 0x01, 0x0F,\n                0x01, 0x0F, 0x01, 0x03, 0x05, 0x08,/*蒹4307*/},\n        {\n\n                0xAA, 0x32, 0xE2, 0x37, 0xAA, 0x02, 0xF2, 0x57, 0x52, 0x52, 0xF2, 0x09, 0x05, 0x03, 0x01, 0x09,\n                0x04, 0x03, 0x01, 0x01, 0x09, 0x0F,/*蒴4308*/},\n        {\n\n                0x4A, 0x92, 0x07, 0xFA, 0xAA, 0xAE, 0xAA, 0xAA, 0xAF, 0xFA, 0x02, 0x08, 0x04, 0x00, 0x0F, 0x08,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*蒗4309*/},\n        {\n\n                0x5A, 0x4A, 0xCA, 0xAF, 0xAA, 0x9A, 0xAA, 0xAF, 0xCA, 0x4A, 0x5A, 0x08, 0x0A, 0x0A, 0x0E, 0x0A,\n                0x0F, 0x0A, 0x0E, 0x0A, 0x0A, 0x08,/*蓥4310*/},\n        {\n\n                0x8A, 0xAA, 0xCA, 0xBF, 0x82, 0x0A, 0xEA, 0x2F, 0xBA, 0x2A, 0xEA, 0x00, 0x08, 0x0F, 0x00, 0x01,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*蓣4311*/},\n        {\n\n                0x02, 0xD2, 0x57, 0xFA, 0x52, 0xD2, 0x42, 0x3A, 0x97, 0x12, 0x72, 0x08, 0x05, 0x03, 0x0F, 0x03,\n                0x05, 0x08, 0x06, 0x01, 0x06, 0x08,/*蔌4312*/},\n        {\n\n                0x62, 0xBA, 0xAA, 0xAF, 0xBA, 0xAA, 0xBA, 0xAF, 0xAA, 0xBA, 0x62, 0x00, 0x0C, 0x0B, 0x0A, 0x06,\n                0x0A, 0x02, 0x06, 0x08, 0x08, 0x0C,/*甍4313*/},\n        {\n\n                0xF2, 0x0A, 0x02, 0xF7, 0x5A, 0x56, 0x52, 0xF7, 0x02, 0x0A, 0xFA, 0x09, 0x09, 0x08, 0x05, 0x03,\n                0x01, 0x07, 0x09, 0x08, 0x09, 0x0D,/*蔸4314*/},\n        {\n\n                0x42, 0xA2, 0xD2, 0x2F, 0x42, 0x72, 0x42, 0x7F, 0x52, 0x52, 0x42, 0x01, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x08, 0x0F, 0x0A, 0x0A, 0x08,/*蓰4315*/},\n        {\n\n                0x42, 0x22, 0x57, 0x4A, 0x52, 0xA2, 0x42, 0xBA, 0x27, 0xE2, 0x22, 0x09, 0x0A, 0x08, 0x09, 0x06,\n                0x05, 0x08, 0x05, 0x02, 0x05, 0x08,/*蔹4316*/},\n        {\n\n                0x22, 0xEA, 0xB2, 0xA7, 0x22, 0x9A, 0x72, 0xD7, 0x52, 0x52, 0x12, 0x08, 0x07, 0x08, 0x0F, 0x01,\n                0x09, 0x05, 0x03, 0x05, 0x09, 0x09,/*蔟4317*/},\n        {\n\n                0xEA, 0x12, 0x42, 0xEF, 0xBA, 0xEA, 0xBA, 0xAF, 0x0A, 0x0A, 0xFA, 0x0F, 0x00, 0x00, 0x0F, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x00, 0x08, 0x0F,/*蔺4318*/},\n        {\n\n                0x22, 0x4A, 0x92, 0x07, 0xFA, 0xAA, 0xAA, 0xAF, 0xAA, 0xEA, 0x8A, 0x0A, 0x0B, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*蕖4319*/},\n        {\n\n                0x9A, 0xAA, 0xAA, 0xAF, 0x8A, 0x0E, 0x8A, 0xFF, 0xAA, 0xAA, 0x1A, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x08, 0x0D, 0x0A, 0x0A, 0x0D, 0x08,/*蔻4320*/},\n        {\n\n                0x9A, 0x4A, 0xEA, 0x1F, 0xAA, 0xAE, 0xEA, 0xAF, 0xAA, 0xAA, 0x1A, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*蓿4321*/},\n        {\n\n                0x02, 0x5A, 0x2A, 0x8F, 0xBA, 0x42, 0xDA, 0xAF, 0x0A, 0x7A, 0x02, 0x01, 0x09, 0x09, 0x0A, 0x0A,\n                0x0A, 0x05, 0x04, 0x05, 0x01, 0x01,/*蓼4322*/},\n        {\n\n                0x82, 0x8A, 0xFA, 0xAF, 0xAA, 0xFE, 0xAA, 0xAF, 0xFA, 0x8A, 0xC2, 0x04, 0x02, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x05,/*蕙4323*/},\n        {\n\n                0x0A, 0xEA, 0xAA, 0xAF, 0xFA, 0xAA, 0xFA, 0xAF, 0xAA, 0xEA, 0x0A, 0x04, 0x04, 0x07, 0x04, 0x04,\n                0x0D, 0x06, 0x04, 0x07, 0x04, 0x04,/*蕈4324*/},\n        {\n\n                0x02, 0xFA, 0x5A, 0x6F, 0xCA, 0x6A, 0x5A, 0x8F, 0x7A, 0x4A, 0xCA, 0x08, 0x07, 0x0B, 0x0A, 0x07,\n                0x02, 0x0B, 0x04, 0x03, 0x04, 0x08,/*蕨4325*/},\n        {\n\n                0x4A, 0xAA, 0x5A, 0xEF, 0x2A, 0x42, 0xB2, 0xA7, 0xFA, 0xA2, 0xA2, 0x05, 0x02, 0x09, 0x0F, 0x01,\n                0x06, 0x0A, 0x0A, 0x0B, 0x0A, 0x0A,/*蕤4326*/},\n        {\n\n                0x42, 0xC2, 0x7A, 0x4F, 0xDA, 0x6A, 0x4A, 0x4F, 0x7A, 0x42, 0x42, 0x04, 0x07, 0x05, 0x05, 0x0F,\n                0x02, 0x09, 0x0B, 0x05, 0x0B, 0x08,/*蕞4327*/},\n        {\n\n                0x42, 0xF2, 0x57, 0x52, 0xF2, 0x42, 0x42, 0xFA, 0x47, 0x52, 0x42, 0x04, 0x07, 0x05, 0x05, 0x0F,\n                0x02, 0x08, 0x05, 0x02, 0x05, 0x0E,/*蕺4328*/},\n        {\n\n                0x62, 0x3A, 0xEA, 0xAF, 0xBA, 0xAA, 0xBA, 0xAF, 0xEA, 0x3A, 0x62, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*瞢4329*/},\n        {\n\n                0x22, 0xAA, 0xFA, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xF6, 0xA2, 0x22, 0x01, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x00, 0x01,/*蕃4330*/},\n        {\n\n                0x02, 0xF6, 0x5A, 0xF7, 0x5A, 0xF6, 0x02, 0xF7, 0x52, 0xCA, 0x4A, 0x04, 0x05, 0x05, 0x0F, 0x05,\n                0x05, 0x08, 0x07, 0x00, 0x0F, 0x00,/*蕲4331*/},\n        {\n\n                0x82, 0xFA, 0xAF, 0xAA, 0xAA, 0x82, 0x22, 0xFA, 0x27, 0xFA, 0x22, 0x04, 0x06, 0x05, 0x04, 0x06,\n                0x04, 0x09, 0x05, 0x01, 0x05, 0x09,/*蕻4332*/},\n        {\n\n                0x92, 0x72, 0x52, 0xD7, 0xA2, 0xA2, 0xFA, 0x07, 0xFA, 0xA2, 0xA2, 0x08, 0x05, 0x02, 0x09, 0x0A,\n                0x0A, 0x0F, 0x08, 0x0F, 0x0A, 0x0A,/*薤4333*/},\n        {\n\n                0x62, 0xBA, 0xAA, 0xAF, 0xBA, 0xAA, 0xBA, 0xAF, 0xAA, 0xBA, 0x62, 0x08, 0x0A, 0x0E, 0x0B, 0x06,\n                0x00, 0x07, 0x0C, 0x0A, 0x09, 0x0C,/*薨4334*/},\n        {\n\n                0x92, 0xCA, 0x32, 0xA7, 0xBA, 0xA2, 0x32, 0xC7, 0x3A, 0xE2, 0x22, 0x00, 0x0F, 0x08, 0x06, 0x02,\n                0x0E, 0x08, 0x05, 0x02, 0x05, 0x08,/*薇4335*/},\n        {\n\n                0x22, 0xEA, 0x3A, 0x2F, 0x2A, 0x6E, 0xAA, 0x2F, 0x3A, 0xEA, 0x22, 0x08, 0x05, 0x01, 0x05, 0x09,\n                0x0B, 0x09, 0x0D, 0x01, 0x05, 0x08,/*薏4336*/},\n        {\n\n                0xCA, 0xBA, 0x8A, 0x6F, 0x4A, 0xEE, 0xBA, 0xAF, 0xFA, 0xAA, 0xAA, 0x02, 0x0B, 0x06, 0x03, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*蕹4337*/},\n        {\n\n                0x52, 0x3A, 0x92, 0x7F, 0x32, 0x5A, 0x12, 0xA7, 0x1A, 0xF2, 0x12, 0x09, 0x0B, 0x05, 0x05, 0x05,\n                0x0B, 0x08, 0x05, 0x02, 0x05, 0x08,/*薮4338*/},\n        {\n\n                0x02, 0xF2, 0x52, 0x57, 0x72, 0x02, 0x92, 0xB7, 0xDA, 0xB2, 0x92, 0x04, 0x03, 0x0F, 0x09, 0x0F,\n                0x00, 0x00, 0x02, 0x0F, 0x02, 0x00,/*薜4339*/},\n        {\n\n                0x22, 0xE2, 0x3A, 0xE7, 0x02, 0xFA, 0x2A, 0xEF, 0xAA, 0x6A, 0xAA, 0x04, 0x02, 0x01, 0x0A, 0x04,\n                0x03, 0x06, 0x02, 0x0A, 0x0F, 0x02,/*薅4340*/},\n        {\n\n                0x8A, 0xAA, 0xEF, 0xAA, 0xAA, 0xBE, 0xAA, 0xAA, 0xEF, 0xAA, 0x8A, 0x09, 0x08, 0x0A, 0x0B, 0x0A,\n                0x0E, 0x0A, 0x0B, 0x0A, 0x08, 0x09,/*薹4341*/},\n        {\n\n                0x62, 0xAA, 0xEA, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xEA, 0xAA, 0x62, 0x00, 0x0E, 0x02, 0x02, 0x0E,\n                0x03, 0x0E, 0x02, 0x0A, 0x0E, 0x00,/*薷4342*/},\n        {\n\n                0x22, 0xEA, 0x2A, 0xAF, 0x2A, 0xFA, 0x2A, 0xAF, 0x2A, 0xEA, 0x22, 0x04, 0x0D, 0x05, 0x05, 0x0D,\n                0x07, 0x0D, 0x05, 0x05, 0x0D, 0x04,/*薰4343*/},\n        {\n\n                0x12, 0xEE, 0xAA, 0xEF, 0xBA, 0xE2, 0x2A, 0xB7, 0xE2, 0xB2, 0x2A, 0x08, 0x0B, 0x0A, 0x0B, 0x0A,\n                0x0B, 0x02, 0x02, 0x0F, 0x02, 0x02,/*藓4344*/},\n        {\n\n                0xEA, 0x2A, 0x3A, 0xEF, 0xAA, 0xAE, 0xAA, 0xEF, 0x3A, 0xAA, 0xEA, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*藁4345*/},\n        {\n\n                0xA2, 0x6A, 0x2F, 0xFA, 0xAA, 0x62, 0x9A, 0x52, 0x37, 0x92, 0xF2, 0x02, 0x02, 0x09, 0x05, 0x0A,\n                0x0F, 0x02, 0x05, 0x09, 0x02, 0x02,/*藜4346*/},\n        {\n\n                0x62, 0x2A, 0xAA, 0xEF, 0xAA, 0xFA, 0xAA, 0xEF, 0xAA, 0xAA, 0x62, 0x02, 0x01, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*藿4347*/},\n        {\n\n                0x4A, 0xD2, 0x02, 0xE7, 0x22, 0xBE, 0x6A, 0xAF, 0x2A, 0xAA, 0x62, 0x08, 0x07, 0x04, 0x0B, 0x09,\n                0x0A, 0x0D, 0x0F, 0x09, 0x0A, 0x08,/*蘧4348*/},\n        {\n\n                0x92, 0xCA, 0x27, 0xF2, 0xAA, 0xEE, 0xBA, 0xE2, 0x4F, 0xCA, 0x4A, 0x00, 0x0F, 0x02, 0x0B, 0x06,\n                0x03, 0x06, 0x0B, 0x0A, 0x0F, 0x00,/*蘅4349*/},\n        {\n\n                0x12, 0xFE, 0xAA, 0xFF, 0xAA, 0xFA, 0x12, 0xAF, 0x4A, 0xBA, 0x0A, 0x00, 0x0A, 0x06, 0x03, 0x0A,\n                0x0E, 0x02, 0x02, 0x07, 0x0A, 0x01,/*蘩4350*/},\n        {\n\n                0x02, 0xFA, 0xAF, 0xBA, 0xE2, 0x02, 0x2A, 0xBA, 0xEF, 0xBA, 0x2A, 0x0A, 0x0A, 0x0A, 0x06, 0x02,\n                0x0F, 0x02, 0x06, 0x0B, 0x0A, 0x0A,/*蘖4351*/},\n        {\n\n                0x02, 0xFA, 0xAF, 0x6A, 0xFA, 0xAA, 0x4E, 0xAA, 0xFF, 0x6A, 0xAA, 0x08, 0x07, 0x00, 0x05, 0x05,\n                0x0F, 0x00, 0x0F, 0x05, 0x05, 0x00,/*蘼4352*/},\n        {\n\n                0x40, 0x40, 0x40, 0xFE, 0x40, 0x40, 0x40, 0xFE, 0x40, 0x40, 0x40, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*廾4353*/},\n        {\n\n                0x12, 0x0A, 0x22, 0x9E, 0x02, 0x03, 0x22, 0xBE, 0x02, 0x0A, 0x12, 0x01, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*弈4354*/},\n        {\n\n                0x24, 0x24, 0xD4, 0x14, 0x0C, 0xC7, 0x0C, 0x14, 0xD4, 0x24, 0x24, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x07, 0x00, 0x00, 0x0F, 0x00, 0x00,/*夼4355*/},\n        {\n\n                0x12, 0xF2, 0x2A, 0xAA, 0xA6, 0x23, 0x26, 0xAA, 0xAA, 0x32, 0x12, 0x00, 0x0F, 0x08, 0x0A, 0x0A,\n                0x09, 0x09, 0x0A, 0x0A, 0x08, 0x00,/*奁4356*/},\n        {\n\n                0x12, 0x12, 0xFA, 0x56, 0x52, 0x53, 0x52, 0x56, 0xFA, 0x12, 0x12, 0x04, 0x04, 0x07, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0F, 0x02, 0x02,/*耷4357*/},\n        {\n\n                0x24, 0x14, 0x44, 0x3C, 0x05, 0x86, 0x44, 0x7C, 0x04, 0x14, 0x24, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*奕4358*/},\n        {\n\n                0x00, 0x42, 0x56, 0x5A, 0x72, 0xD6, 0x49, 0x49, 0x65, 0x41, 0x00, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*奚4359*/},\n        {\n\n                0x50, 0x36, 0x14, 0x7F, 0x00, 0xA4, 0x24, 0x3F, 0x24, 0x24, 0x04, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*奘4360*/},\n        {\n\n                0x4A, 0xD6, 0x53, 0x56, 0x4A, 0x08, 0xF4, 0x97, 0xF4, 0x04, 0xFC, 0x00, 0x01, 0x09, 0x0F, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x09, 0x0D,/*匏4361*/},\n        {\n\n                0x08, 0x08, 0x08, 0xE8, 0x1F, 0x08, 0xF8, 0x08, 0x08, 0x08, 0x08, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*尢4362*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xF8, 0x08, 0x08, 0x27, 0x44, 0x04, 0xFC, 0x00, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x08, 0x08, 0x0A, 0x0A, 0x09, 0x0C,/*尥4363*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xF8, 0x08, 0x08, 0xF4, 0x03, 0xF4, 0x08, 0x08, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x0A, 0x09, 0x08, 0x0B, 0x08, 0x0C,/*尬4364*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xF8, 0x08, 0xDE, 0x40, 0xDF, 0x48, 0xC7, 0x14, 0x08, 0x07, 0x00, 0x07, 0x0A,\n                0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0E,/*尴4365*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*扌4366*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFD, 0x02, 0x00, 0x02, 0x02, 0x02, 0xFE, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*扪4367*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x24, 0xE4, 0xBC, 0xA7, 0xA4, 0xA4, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x02, 0x02, 0x04, 0x06, 0x09, 0x00,/*抟4368*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFC, 0x24, 0x24, 0xFF, 0x24, 0x24, 0xFC, 0x08, 0x0F, 0x00, 0x00, 0x03,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x03,/*抻4369*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x10, 0xFC, 0x03, 0x48, 0x88, 0xFF, 0x08, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x08, 0x0F, 0x00,/*拊4370*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x00, 0x8C, 0xEA, 0x89, 0x88, 0xEC, 0x98, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x00, 0x0F, 0x00,/*拚4371*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x38, 0xE7, 0x30, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x08, 0x0F, 0x00, 0x03, 0x02,\n                0x0B, 0x06, 0x01, 0x08, 0x08, 0x07,/*拗4372*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x04, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0x04, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*拮4373*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x48, 0xAA, 0x1A, 0x0E, 0x19, 0xA9, 0x48, 0x08, 0x0F, 0x00, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x0F, 0x00,/*挢4374*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x04, 0x9B, 0xC0, 0xA4, 0x9B, 0x80, 0x84, 0x1B, 0x08, 0x0F, 0x00, 0x09, 0x08,\n                0x0A, 0x04, 0x04, 0x02, 0x01, 0x00,/*拶4375*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xF0, 0x97, 0x95, 0xF5, 0x95, 0x97, 0xF0, 0x08, 0x0F, 0x00, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*挹4376*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x4A, 0x52, 0x46, 0x4A, 0x41, 0xE9, 0x45, 0x08, 0x0F, 0x00, 0x00, 0x00,\n                0x01, 0x02, 0x00, 0x08, 0x0F, 0x00,/*捋4377*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xAA, 0xEA, 0xBE, 0xAA, 0xAA, 0xBE, 0x08, 0x08, 0x0F, 0x00, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*捃4378*/},\n        {\n\n                0x84, 0xFF, 0x44, 0x48, 0x29, 0x19, 0xCF, 0x09, 0x19, 0x29, 0x48, 0x08, 0x0F, 0x00, 0x04, 0x02,\n                0x08, 0x0F, 0x01, 0x06, 0x01, 0x06,/*掭4379*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x02, 0xFE, 0x52, 0xFE, 0x02, 0xFE, 0x32, 0xCE, 0x08, 0x0F, 0x00, 0x02, 0x03,\n                0x02, 0x0F, 0x01, 0x0F, 0x02, 0x01,/*揶4380*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x42, 0x52, 0x52, 0x7E, 0x52, 0x52, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x08, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*捱4381*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xA4, 0x94, 0xAC, 0xA7, 0xAC, 0x94, 0xA4, 0x00, 0x08, 0x0F, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*捺4382*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x10, 0xDA, 0x56, 0x53, 0xD2, 0x16, 0xFA, 0x10, 0x08, 0x0F, 0x00, 0x00, 0x07,\n                0x02, 0x02, 0x0B, 0x08, 0x0F, 0x00,/*掎4383*/},\n        {\n\n                0x84, 0xFF, 0x44, 0x00, 0xFF, 0x25, 0x25, 0xFD, 0x25, 0xA5, 0xFF, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x0F,/*掴4384*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x00, 0x08, 0x0F, 0x00, 0x02, 0x03,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*捭4385*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x54, 0x43, 0xFA, 0x42, 0x52, 0x02, 0xFE, 0x08, 0x0F, 0x00, 0x00, 0x02,\n                0x01, 0x07, 0x01, 0x0A, 0x08, 0x07,/*掬4386*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x20, 0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x20, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*掊4387*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFC, 0x94, 0x95, 0xF6, 0x94, 0xD4, 0x9C, 0x08, 0x0F, 0x08, 0x04, 0x0B,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*捩4388*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x0A, 0xEA, 0xAB, 0xAA, 0xAA, 0xEE, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x0F, 0x02, 0x02, 0x0A, 0x0F,/*掮4389*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x04, 0xDF, 0x55, 0x5F, 0x55, 0xDF, 0x04, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x0B, 0x04, 0x03, 0x04, 0x0B, 0x00,/*掼4390*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x04, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x00, 0x08, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*揲4391*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x12, 0xEA, 0xA6, 0xBF, 0xA6, 0xEA, 0x12, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*揸4392*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xFF, 0x81, 0xBF, 0xEB, 0xAB, 0xBF, 0x81, 0x00, 0x08, 0x0F, 0x00, 0x0F,\n                0x08, 0x0D, 0x0A, 0x0A, 0x0D, 0x08,/*揠4393*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x94, 0xF3, 0x92, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x04, 0x08, 0x06, 0x01, 0x06, 0x08,/*揿4394*/},\n        {\n\n                0x84, 0xFF, 0x44, 0xE8, 0xA4, 0xAA, 0xE9, 0x0A, 0xC4, 0x08, 0xE8, 0x08, 0x0F, 0x00, 0x0F, 0x02,\n                0x0A, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*揄4395*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x12, 0xD6, 0x5A, 0x53, 0x52, 0x5A, 0xD6, 0x12, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*揞4396*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x06, 0xEA, 0xAA, 0xAB, 0xAA, 0xAA, 0xEA, 0x06, 0x08, 0x0F, 0x00, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*揎4397*/},\n        {\n\n                0x84, 0xFF, 0x44, 0x00, 0xFF, 0x2D, 0xF5, 0x25, 0x25, 0xF5, 0x2F, 0x08, 0x0F, 0x00, 0x04, 0x03,\n                0x09, 0x07, 0x01, 0x01, 0x0F, 0x01,/*摒4398*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x4A, 0x32, 0x4E, 0xC0, 0x4F, 0x32, 0x49, 0x08, 0x0F, 0x00, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*揆4399*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xAC, 0x6B, 0xAA, 0x2A, 0x3A, 0xA6, 0x20, 0x08, 0x0F, 0x00, 0x08, 0x0A,\n                0x05, 0x0A, 0x0F, 0x01, 0x06, 0x08,/*掾4400*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xFC, 0x24, 0x24, 0xBF, 0x55, 0x55, 0x45, 0x6C, 0x08, 0x0F, 0x08, 0x07, 0x04,\n                0x02, 0x0C, 0x09, 0x0C, 0x02, 0x04,/*摅4401*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x7F, 0x65, 0xD5, 0x4F, 0x55, 0x65, 0x7F, 0x08, 0x0F, 0x00, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*摁4402*/},\n        {\n\n                0x84, 0xFF, 0x44, 0xFE, 0x02, 0xF2, 0x52, 0xFF, 0x55, 0x15, 0xB1, 0x08, 0x0F, 0x08, 0x07, 0x02,\n                0x09, 0x06, 0x02, 0x07, 0x09, 0x0D,/*搋4403*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x44, 0x55, 0xFE, 0x54, 0xFE, 0x55, 0xF4, 0x44, 0x08, 0x0F, 0x00, 0x05, 0x03,\n                0x0F, 0x01, 0x0F, 0x03, 0x05, 0x08,/*搛4404*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xE1, 0x8A, 0xF8, 0x8A, 0xE1, 0xFE, 0x92, 0xFE, 0x08, 0x0F, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x08, 0x07, 0x08, 0x0F,/*搠4405*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xFA, 0xAE, 0x08, 0x0F, 0x00, 0x08, 0x07,\n                0x00, 0x0F, 0x04, 0x03, 0x04, 0x0A,/*搌4406*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xB9, 0x29, 0xEF, 0x00, 0xB9, 0x29, 0xEF, 0x08, 0x0F, 0x00, 0x00, 0x0A,\n                0x09, 0x07, 0x00, 0x0A, 0x09, 0x07,/*搦4407*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0xB0, 0x5B, 0xB5, 0x05, 0xB5, 0x5B, 0xB0, 0x00, 0x08, 0x0F, 0x00, 0x0A,\n                0x06, 0x02, 0x0F, 0x02, 0x06, 0x0A,/*搡4408*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0x5F, 0x75, 0xD5, 0x5F, 0x35, 0x95, 0x1F, 0x08, 0x0F, 0x00, 0x08, 0x05,\n                0x01, 0x09, 0x0F, 0x01, 0x05, 0x09,/*摞4409*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x80, 0xAF, 0x91, 0xEF, 0x80, 0xAF, 0x91, 0xAF, 0x08, 0x0F, 0x00, 0x08, 0x0A,\n                0x0B, 0x04, 0x04, 0x0B, 0x08, 0x00,/*撄4410*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x22, 0xFA, 0x23, 0x22, 0xFA, 0x22, 0x08, 0x0F, 0x08, 0x04, 0x0B,\n                0x04, 0x09, 0x05, 0x09, 0x05, 0x08,/*摭4411*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xF9, 0xAD, 0xFB, 0x10, 0xEC, 0x0B, 0xF8, 0x08, 0x08, 0x0F, 0x02, 0x03, 0x02,\n                0x0F, 0x09, 0x04, 0x03, 0x04, 0x08,/*撖4412*/},\n        {\n\n                0x84, 0xFF, 0x44, 0x00, 0xD5, 0x49, 0x5F, 0x60, 0x55, 0x49, 0xDF, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*摺4413*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xA4, 0xBF, 0xA4, 0x00, 0xF2, 0x9A, 0x16, 0xF2, 0x08, 0x0F, 0x00, 0x0F, 0x04,\n                0x0F, 0x08, 0x05, 0x03, 0x04, 0x09,/*撷4414*/},\n        {\n\n                0x08, 0xFF, 0x88, 0xFC, 0xAA, 0xAB, 0xFA, 0xAA, 0xAE, 0xF8, 0x80, 0x09, 0x0F, 0x00, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*撸4415*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x02, 0xFA, 0xAB, 0xDE, 0xCA, 0xBE, 0xAB, 0xFA, 0x08, 0x0F, 0x00, 0x00, 0x02,\n                0x06, 0x0A, 0x02, 0x0A, 0x0F, 0x02,/*撙4416*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x06, 0x7A, 0x56, 0xFB, 0x56, 0x7A, 0x06, 0x00, 0x08, 0x0F, 0x00, 0x07,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x07,/*撺4417*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xFA, 0xAF, 0xFA, 0x04, 0x12, 0xF1, 0x12, 0x04, 0x08, 0x0F, 0x00, 0x02, 0x0F,\n                0x02, 0x01, 0x01, 0x0F, 0x01, 0x01,/*擀4418*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x17, 0xD5, 0x57, 0x55, 0x57, 0xD5, 0x17, 0x00, 0x08, 0x0F, 0x00, 0x08,\n                0x05, 0x0F, 0x09, 0x03, 0x05, 0x0A,/*擐4419*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x00, 0xFE, 0x92, 0x9E, 0x40, 0x55, 0xE6, 0x54, 0x08, 0x0F, 0x00, 0x01, 0x0F,\n                0x04, 0x0F, 0x00, 0x02, 0x0F, 0x02,/*擗4420*/},\n        {\n\n                0x88, 0xFF, 0x48, 0xE0, 0xBE, 0xAB, 0xEA, 0xAA, 0xBE, 0xE0, 0x00, 0x08, 0x0F, 0x02, 0x0B, 0x06,\n                0x02, 0x03, 0x02, 0x0E, 0x03, 0x02,/*擤4421*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x20, 0xFB, 0xA5, 0xAF, 0xA0, 0xEB, 0xB5, 0xAF, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*擢4422*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x80, 0xCD, 0x75, 0x45, 0xDF, 0x65, 0x55, 0x4D, 0x08, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x04,/*攉4423*/},\n        {\n\n                0x88, 0xFF, 0x48, 0x84, 0xFB, 0x9E, 0xAA, 0xDC, 0xAB, 0xFE, 0x82, 0x08, 0x0F, 0x00, 0x02, 0x09,\n                0x06, 0x0B, 0x0E, 0x02, 0x05, 0x0A,/*攥4424*/},\n        {\n\n                0x88, 0x88, 0xFF, 0x48, 0x62, 0xAE, 0xEA, 0xBF, 0xEA, 0xAE, 0x62, 0x00, 0x08, 0x0F, 0x00, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*攮4425*/},\n        {\n\n                0x10, 0x10, 0x10, 0x10, 0x3F, 0xD0, 0x08, 0x09, 0x0A, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x0F,/*弋4426*/},\n        {\n\n                0x08, 0x08, 0x28, 0x48, 0x08, 0x08, 0x08, 0xFF, 0x08, 0x09, 0x0A, 0x07, 0x00, 0x07, 0x08, 0x0C,\n                0x01, 0x06, 0x00, 0x03, 0x04, 0x0E,/*忒4427*/},\n        {\n\n                0x48, 0xE8, 0x48, 0x48, 0x48, 0xE8, 0x48, 0xFF, 0x08, 0x09, 0x0A, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x0F, 0x00, 0x00, 0x03, 0x04, 0x0E,/*甙4428*/},\n        {\n\n                0x49, 0x45, 0xF2, 0x45, 0x49, 0x24, 0xE4, 0x24, 0xFF, 0x04, 0x05, 0x02, 0x09, 0x0F, 0x01, 0x02,\n                0x04, 0x07, 0x02, 0x03, 0x04, 0x0E,/*弑4429*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*卟4430*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x80, 0xFF, 0x20, 0x10, 0x08, 0x04, 0x03, 0x01, 0x01, 0x03, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*叱4431*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x03, 0x01, 0x01, 0x0B, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*叽4432*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x0F, 0x00, 0x02, 0x02, 0x01,/*叩4433*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x02, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*叨4434*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x08, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*叻4435*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x40, 0x42, 0x42, 0xFE, 0x21, 0x21, 0x20, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*吒4436*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x01, 0x02, 0x04, 0xF8, 0x04, 0x02, 0x01, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*吖4437*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0x30, 0x2C, 0xE3, 0x20, 0x18, 0x00, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x06, 0x05, 0x04, 0x04, 0x05, 0x0E,/*吆4438*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x40, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*呋4439*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x20, 0x22, 0xA2, 0x7E, 0xA2, 0x22, 0x22, 0x20, 0x03, 0x01, 0x0B, 0x04, 0x02,\n                0x01, 0x00, 0x07, 0x08, 0x08, 0x0F,/*呒4440*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x04, 0x24, 0x2F, 0x24, 0xA4, 0xAF, 0x64, 0x04, 0x03, 0x01, 0x03, 0x00, 0x06,\n                0x09, 0x09, 0x08, 0x08, 0x08, 0x0E,/*呓4441*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0x08, 0xE8, 0x1F, 0xE8, 0x08, 0x08, 0x08, 0x03, 0x01, 0x0B, 0x04, 0x03,\n                0x02, 0x04, 0x00, 0x03, 0x04, 0x08,/*呔4442*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x02, 0x22, 0xFA, 0x22, 0x22, 0xE2, 0x03, 0x01, 0x0B, 0x04, 0x0B,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*呖4443*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x02, 0xFA, 0x0A, 0x8A, 0xFA, 0x02, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*呃4444*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFF, 0x10, 0x10, 0xFF, 0x20, 0x10, 0x0C, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x04, 0x02, 0x07, 0x08, 0x08, 0x0E,/*吡4445*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x02, 0x02, 0xFA, 0x02, 0x02, 0xFE, 0x03, 0x01, 0x03, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*呗4446*/},\n        {\n\n                0xE0, 0x2F, 0x29, 0x29, 0xA9, 0x79, 0xA9, 0x29, 0x29, 0x2F, 0xE0, 0x0F, 0x00, 0x00, 0x01, 0x00,\n                0x00, 0x00, 0x01, 0x00, 0x08, 0x0F,/*呙4447*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xE0, 0x00, 0xF0, 0x01, 0x06, 0x10, 0xE0, 0x03, 0x01, 0x01, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x0E, 0x00,/*吣4448*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xF2, 0x92, 0x92, 0x9E, 0x00, 0x00, 0xFF, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x0F,/*吲4449*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFE, 0x02, 0xF2, 0x12, 0xFE, 0x12, 0xF2, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x08, 0x09, 0x08, 0x0F, 0x09, 0x09,/*咂4450*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x20, 0x20, 0xFF, 0xA4, 0x24, 0x24, 0x20, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x00, 0x0F, 0x00, 0x01, 0x02, 0x00,/*咔4451*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x92, 0x92, 0xFE, 0x03, 0x01, 0x03, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*呷4452*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x01, 0x00, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x00, 0x0F, 0x0A, 0x0C, 0x03, 0x04,/*呱4453*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x10, 0x48, 0x44, 0x53, 0x64, 0x48, 0xD0, 0x10, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x02, 0x04, 0x0A, 0x01, 0x00, 0x00,/*呤4454*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x48, 0x44, 0xAB, 0x92, 0x2A, 0x46, 0x40, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x02, 0x02, 0x04, 0x05, 0x08, 0x00,/*咚4455*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x2C, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x2C, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*咛4456*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xBC, 0x20, 0x20, 0xFF, 0x20, 0x20, 0xBC, 0x03, 0x01, 0x03, 0x00, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*咄4457*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0xF8, 0x0F, 0xF8, 0x04, 0xFC, 0x04, 0xFC, 0x03, 0x01, 0x03, 0x08, 0x05,\n                0x02, 0x05, 0x08, 0x04, 0x03, 0x0C,/*呶4458*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x38, 0xE7, 0x30, 0x08, 0xFF, 0x08, 0xF8, 0x03, 0x01, 0x03, 0x00, 0x03,\n                0x02, 0x0B, 0x06, 0x01, 0x08, 0x0F,/*呦4459*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xB8, 0x67, 0x10, 0x00, 0xB8, 0x67, 0x10, 0x03, 0x01, 0x03, 0x08, 0x0B,\n                0x0A, 0x0A, 0x08, 0x0B, 0x0A, 0x0A,/*咝4460*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFE, 0x02, 0x4A, 0x4A, 0xFA, 0x4A, 0x4A, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x08, 0x0A, 0x0A, 0x0B, 0x0A, 0x0A,/*哐4461*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x04, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0x04, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*咭4462*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xF2, 0x12, 0xFE, 0x12, 0xFE, 0x92, 0xF2, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x04, 0x0F,/*哂4463*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xC4, 0x3F, 0xC4, 0x04, 0xF4, 0x44, 0x24, 0x03, 0x01, 0x03, 0x04, 0x03,\n                0x08, 0x04, 0x02, 0x01, 0x06, 0x08,/*咴4464*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x11, 0xF2, 0x00, 0x88, 0x7F, 0x88, 0x08, 0x03, 0x01, 0x03, 0x08, 0x04,\n                0x07, 0x0A, 0x09, 0x08, 0x08, 0x0B,/*哒4465*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x62, 0x9E, 0x12, 0xF2, 0x00, 0xFC, 0x00, 0xFF, 0x03, 0x01, 0x03, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x09, 0x08, 0x0F,/*咧4466*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xEA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xBA, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x08, 0x04, 0x03, 0x04, 0x0A, 0x0B,/*咦4467*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*哓4468*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x3F, 0x24, 0x14, 0xC0, 0x1F, 0x24, 0x32, 0x03, 0x01, 0x03, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*哔4469*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xF8, 0x00, 0xFF, 0x20, 0xFF, 0x10, 0x08, 0x03, 0x01, 0x03, 0x08, 0x0F,\n                0x08, 0x07, 0x04, 0x07, 0x08, 0x0E,/*呲4470*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x24, 0x28, 0xE0, 0x3F, 0xE0, 0x28, 0x24, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*咣4471*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x8E, 0x48, 0xB8, 0x2F, 0x28, 0x28, 0xEE, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x08, 0x04, 0x05, 0x02, 0x01, 0x00,/*哕4472*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x10, 0xFC, 0x8B, 0x68, 0xFF, 0x28, 0xC8, 0x08, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*咻4473*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x08, 0xFC, 0x13, 0x92, 0xFE, 0x92, 0xFE, 0x10, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x08, 0x07, 0x00, 0x01, 0x00,/*咿4474*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x02, 0xFA, 0x0A, 0xF9, 0x45, 0x20, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x00, 0x0F, 0x04, 0x01, 0x06, 0x08,/*哌4475*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x88, 0x94, 0x92, 0x91, 0x92, 0x94, 0x88, 0x03, 0x01, 0x03, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*哙4476*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x50, 0x4F, 0x41, 0xF1, 0x41, 0x4F, 0x50, 0x03, 0x01, 0x03, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*哚4477*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x44, 0x44, 0xAC, 0x15, 0x16, 0xAC, 0x44, 0x44, 0x03, 0x01, 0x03, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x0F, 0x00, 0x00,/*哜4478*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x04, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x04, 0x03, 0x01, 0x03, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*咩4479*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x24, 0x28, 0xA0, 0xFF, 0xA0, 0x28, 0x24, 0x03, 0x01, 0x03, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*咪4480*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0x0C, 0x24, 0x25, 0xE6, 0x94, 0x94, 0x8C, 0x03, 0x01, 0x03, 0x00, 0x01,\n                0x01, 0x01, 0x07, 0x08, 0x08, 0x0E,/*咤4481*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x0C, 0x84, 0xE4, 0x1F, 0xE4, 0x04, 0x8C, 0x03, 0x01, 0x03, 0x00, 0x01,\n                0x00, 0x0F, 0x04, 0x00, 0x03, 0x04,/*哝4482*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*哏4483*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x80, 0x6C, 0x4A, 0xF9, 0x48, 0x4C, 0x18, 0x03, 0x01, 0x03, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*哞4484*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x22, 0x2A, 0xEA, 0xBF, 0xAA, 0xAA, 0x22, 0x03, 0x01, 0x03, 0x00, 0x0A,\n                0x09, 0x0A, 0x04, 0x0A, 0x09, 0x08,/*唛4485*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0x20, 0xA4, 0xE4, 0x3F, 0xE4, 0xA4, 0x20, 0x03, 0x01, 0x03, 0x00, 0x09,\n                0x04, 0x03, 0x08, 0x0F, 0x00, 0x03,/*哧4486*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xB2, 0x97, 0xD2, 0x92, 0x92, 0x97, 0xB2, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*唠4487*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFA, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xFA, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x05, 0x02, 0x05, 0x08, 0x08, 0x08,/*哽4488*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x21, 0xA5, 0xBD, 0xA7, 0xA5, 0xA5, 0xBD, 0x21, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*唔4489*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x88, 0xFF, 0x48, 0x00, 0xFE, 0x12, 0xF2, 0x11, 0x03, 0x01, 0x03, 0x08, 0x0F,\n                0x00, 0x08, 0x07, 0x00, 0x0F, 0x00,/*哳4490*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xF2, 0x14, 0x10, 0xDF, 0x10, 0x14, 0xF2, 0x03, 0x01, 0x03, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*唢4491*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x7C, 0x54, 0xD6, 0x55, 0x54, 0x7C, 0x00, 0x03, 0x01, 0x03, 0x02, 0x02,\n                0x02, 0x07, 0x09, 0x09, 0x09, 0x0C,/*唣4492*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x90, 0xD5, 0xB2, 0x9A, 0xD2, 0x92, 0x95, 0x90, 0x03, 0x01, 0x03, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*唏4493*/},\n        {\n\n                0xFE, 0x02, 0x02, 0xFE, 0x20, 0x1C, 0x20, 0xFF, 0x20, 0x1C, 0x20, 0x03, 0x01, 0x01, 0x03, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*唑4494*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x02, 0xFE, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x04, 0x02, 0x04, 0x0F, 0x01, 0x01,/*唧4495*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xA2, 0x6A, 0x3A, 0xAF, 0x2A, 0x6A, 0xA2, 0x03, 0x01, 0x03, 0x00, 0x04,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x04,/*唪4496*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xA2, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xA2, 0x03, 0x01, 0x03, 0x00, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*啧4497*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x24, 0x24, 0xEF, 0xB4, 0xA4, 0xAF, 0xA4, 0x24, 0x03, 0x01, 0x03, 0x02, 0x01,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*喏4498*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xF2, 0x97, 0x92, 0xF2, 0x92, 0x97, 0xF2, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*喵4499*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x88, 0x48, 0xFF, 0xA8, 0x48, 0xFF, 0x48, 0x88, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x0F, 0x00, 0x00,/*啉4500*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x64, 0x5C, 0xF7, 0x44, 0x10, 0xD4, 0xBF, 0x94, 0x03, 0x01, 0x03, 0x02, 0x02,\n                0x0F, 0x01, 0x00, 0x02, 0x0C, 0x03,/*啭4501*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFF, 0x21, 0xA9, 0xBD, 0xA9, 0x21, 0xFF, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x00, 0x03, 0x02, 0x0B, 0x08, 0x0F,/*啁4502*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x04, 0x53, 0x4E, 0xFA, 0x4A, 0x4A, 0x02, 0xFE, 0x03, 0x01, 0x03, 0x00, 0x03,\n                0x02, 0x03, 0x02, 0x0B, 0x08, 0x07,/*啕4503*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0x24, 0x53, 0xAE, 0x12, 0x4E, 0x42, 0x3E, 0x03, 0x01, 0x03, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*唿4504*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x24, 0x1C, 0x25, 0x86, 0x24, 0x1C, 0x24, 0x03, 0x01, 0x03, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*啐4505*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xA4, 0xAC, 0xB5, 0xE6, 0xB4, 0xAC, 0xA4, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x0A, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*唼4506*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x02, 0xEE, 0xAA, 0xAB, 0xAA, 0xAA, 0xEE, 0x1A, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*唷4507*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x28, 0xA6, 0x10, 0xCF, 0x10, 0x14, 0xA2, 0x03, 0x01, 0x03, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x05, 0x08,/*啖4508*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x22, 0x44, 0xFC, 0x24, 0xE4, 0x3F, 0xE4, 0x0C, 0x03, 0x01, 0x01, 0x04, 0x0A,\n                0x07, 0x08, 0x05, 0x02, 0x05, 0x08,/*啵4509*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x2C, 0xA4, 0x24, 0xE5, 0x26, 0x24, 0x2C, 0x03, 0x01, 0x03, 0x08, 0x04,\n                0x03, 0x04, 0x0F, 0x09, 0x09, 0x08,/*啶4510*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFD, 0x56, 0x7C, 0x00, 0xFE, 0x32, 0xCE, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x05, 0x02, 0x04, 0x0F, 0x02, 0x01,/*啷4511*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFC, 0x94, 0x95, 0xF6, 0x94, 0xD4, 0x9C, 0x03, 0x01, 0x0B, 0x04, 0x0B,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*唳4512*/},\n        {\n\n                0xFE, 0x02, 0xFF, 0x29, 0xF9, 0x29, 0xEF, 0x00, 0xFC, 0x00, 0xFF, 0x03, 0x09, 0x07, 0x00, 0x0F,\n                0x02, 0x03, 0x00, 0x09, 0x08, 0x0F,/*唰4513*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xAA, 0x92, 0xAE, 0x00, 0xAA, 0x92, 0xAE, 0x03, 0x01, 0x03, 0x08, 0x0A,\n                0x04, 0x0B, 0x00, 0x0B, 0x04, 0x0B,/*啜4514*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x04, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x03, 0x01, 0x03, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*喋4515*/},\n        {\n\n                0xFC, 0x04, 0x04, 0xFC, 0x42, 0x27, 0x52, 0x4A, 0x52, 0x27, 0x42, 0x03, 0x01, 0x01, 0x03, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*嗒4516*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFA, 0x0A, 0x5A, 0xEF, 0x5A, 0x0A, 0xFA, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*喃4517*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFF, 0x01, 0x7D, 0x55, 0xFD, 0x55, 0x7D, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x00, 0x09, 0x09, 0x0F, 0x09, 0x09,/*喱4518*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x92, 0xAA, 0xA6, 0xF3, 0xA6, 0xAA, 0x92, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*喹4519*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xDF, 0x52, 0x4A, 0x60, 0x4F, 0x52, 0xD9, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*喈4520*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x80, 0xBF, 0xA5, 0xFF, 0xA5, 0xBF, 0x80, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x02, 0x03, 0x06, 0x08, 0x0F,/*喁4521*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x1F, 0xF5, 0x55, 0x5F, 0x55, 0xF5, 0x1F, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x0F, 0x01, 0x01, 0x09, 0x0F, 0x00,/*喟4522*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0x92, 0xFE, 0x51, 0x08, 0xFF, 0x10, 0x0C, 0x03, 0x01, 0x03, 0x01, 0x00,\n                0x0F, 0x08, 0x07, 0x00, 0x07, 0x08,/*啾4523*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xBC, 0xAA, 0xA0, 0xFF, 0xA0, 0xAA, 0xBE, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x09, 0x0A, 0x04, 0x04, 0x0A, 0x09,/*嗖4524*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x12, 0xD6, 0x5A, 0x53, 0x52, 0x5A, 0xD6, 0x12, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*喑4525*/},\n        {\n\n                0x18, 0xEA, 0x2A, 0x2E, 0x2A, 0xFB, 0x2A, 0x2E, 0xAA, 0xEA, 0x18, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*啻4526*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x44, 0xD5, 0x76, 0x5C, 0x56, 0x55, 0x44, 0x03, 0x01, 0x03, 0x04, 0x0A,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*嗟4527*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xAA, 0x9C, 0xC8, 0xBF, 0x88, 0x9C, 0xAA, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x0A, 0x05, 0x04, 0x04, 0x0B, 0x08,/*喽4528*/},\n        {\n\n                0x4C, 0x65, 0x5E, 0x54, 0x55, 0x7E, 0x54, 0x54, 0x56, 0x55, 0x4C, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*喾4529*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFF, 0x05, 0x95, 0xD5, 0xB5, 0x95, 0xD7, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x08, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*喔4530*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xAC, 0x6B, 0xAA, 0x2A, 0x3A, 0xA6, 0x20, 0x03, 0x01, 0x03, 0x08, 0x0A,\n                0x05, 0x0A, 0x0F, 0x01, 0x06, 0x08,/*喙4531*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xA2, 0x6A, 0xBA, 0xAF, 0xAA, 0x6A, 0xA2, 0x03, 0x01, 0x03, 0x00, 0x0A,\n                0x06, 0x02, 0x0F, 0x02, 0x06, 0x0A,/*嗪4532*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x20, 0xEA, 0xBF, 0xAA, 0x10, 0xEF, 0x08, 0xF8, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x08, 0x0F, 0x08, 0x05, 0x02, 0x0D,/*嗷4533*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x22, 0xAA, 0xEA, 0xBF, 0xAA, 0x6A, 0x22, 0x03, 0x01, 0x03, 0x00, 0x0A,\n                0x06, 0x0A, 0x0F, 0x02, 0x06, 0x0B,/*嗉4534*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x50, 0xF2, 0x5F, 0xDA, 0x14, 0xFE, 0x32, 0xCE, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x05, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*嘟4535*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x48, 0x6A, 0x5A, 0x4F, 0x4A, 0x6A, 0x48, 0x03, 0x01, 0x03, 0x08, 0x0F,\n                0x09, 0x0F, 0x09, 0x0F, 0x09, 0x0F,/*嗑4536*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x41, 0x7F, 0x55, 0x55, 0x55, 0xFF, 0x21, 0x03, 0x01, 0x03, 0x00, 0x0B,\n                0x05, 0x0B, 0x00, 0x0B, 0x05, 0x0B,/*嗫4537*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x22, 0xF2, 0x0F, 0xD2, 0x52, 0xD7, 0xF2, 0x12, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x0B, 0x0F, 0x00,/*嗬4538*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xAA, 0xFA, 0x02, 0x03, 0x01, 0x01, 0x02, 0x0B,\n                0x06, 0x02, 0x02, 0x06, 0x0B, 0x02,/*嗔4539*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x1A, 0x6A, 0xDA, 0x4F, 0x2A, 0x8A, 0x1A, 0x03, 0x01, 0x03, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*嗦4540*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xC1, 0x5D, 0xD5, 0x55, 0xD5, 0x5D, 0xC1, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x02, 0x0F, 0x02, 0x08, 0x0F,/*嗝4541*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x01, 0x7D, 0x55, 0xD7, 0x55, 0x55, 0x7D, 0x01, 0x03, 0x01, 0x03, 0x08, 0x0A,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*嗄4542*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x7F, 0x65, 0xD5, 0x4F, 0x55, 0x65, 0x7F, 0x03, 0x01, 0x03, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*嗯4543*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x80, 0xBE, 0xEA, 0xAB, 0xAA, 0xAA, 0xBE, 0x80, 0x03, 0x01, 0x05, 0x02, 0x05,\n                0x04, 0x0E, 0x04, 0x05, 0x02, 0x04,/*嗥4544*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x10, 0x52, 0xA9, 0x3A, 0xA4, 0x6A, 0x11, 0x12, 0x03, 0x01, 0x03, 0x0A, 0x0A,\n                0x09, 0x0B, 0x05, 0x05, 0x03, 0x00,/*嗲4545*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x30, 0x56, 0xDA, 0x76, 0x5A, 0x51, 0x59, 0x35, 0x03, 0x01, 0x03, 0x04, 0x02,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*嗳4546*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0xA9, 0x9A, 0x88, 0x88, 0x88, 0x9A, 0xA9, 0x00, 0x03, 0x01, 0x09, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*嗌4547*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0xE1, 0x8A, 0xF8, 0x8A, 0xE1, 0xFE, 0x92, 0xFE, 0x03, 0x01, 0x03, 0x08, 0x04,\n                0x03, 0x00, 0x08, 0x07, 0x08, 0x0F,/*嗍4548*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x22, 0x44, 0xFB, 0x4A, 0x6A, 0x4A, 0xFA, 0x42, 0x03, 0x01, 0x03, 0x04, 0x02,\n                0x03, 0x02, 0x0B, 0x0A, 0x07, 0x02,/*嗨4549*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x11, 0xF2, 0x00, 0xF9, 0xAB, 0xFD, 0xAB, 0xF8, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0B,/*嗵4550*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x96, 0x94, 0x94, 0xDF, 0x94, 0x94, 0x96, 0x03, 0x01, 0x03, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0F,/*嗤4551*/},\n        {\n\n                0x6C, 0x5B, 0x44, 0x1A, 0x56, 0xFB, 0x52, 0x0C, 0x6B, 0x58, 0x44, 0x01, 0x0F, 0x0B, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x0A, 0x0B, 0x0F, 0x01,/*辔4552*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0xE2, 0xAF, 0xFA, 0xAF, 0xEA, 0xFF, 0x08, 0xF8, 0x03, 0x01, 0x01, 0x02, 0x02,\n                0x0F, 0x02, 0x0A, 0x07, 0x08, 0x0F,/*嘞4553*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFA, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFA, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*嘈4554*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x1D, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x03, 0x01, 0x03, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*嘌4555*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFC, 0x44, 0xFC, 0x54, 0xFF, 0x04, 0xE5, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x0A, 0x0F, 0x05, 0x03, 0x05, 0x0E,/*嘁4556*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x80, 0xAF, 0x91, 0xEF, 0x80, 0xAF, 0x91, 0xAF, 0x03, 0x01, 0x03, 0x08, 0x0A,\n                0x0B, 0x04, 0x04, 0x0B, 0x08, 0x00,/*嘤4557*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xF6, 0x54, 0xF4, 0x07, 0xF4, 0x54, 0xF6, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x09, 0x0F, 0x08, 0x07, 0x09, 0x0F,/*嘣4558*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x04, 0xFD, 0x26, 0xE4, 0xA3, 0x9A, 0xF2, 0x92, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x08, 0x07, 0x08, 0x04, 0x03, 0x0C,/*嗾4559*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xF2, 0x16, 0x5A, 0xF3, 0x5A, 0x16, 0xF2, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x07, 0x05, 0x07, 0x08, 0x0F,/*嘀4560*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x20, 0x96, 0x72, 0xC6, 0xAB, 0xD2, 0x0A, 0x66, 0x03, 0x01, 0x03, 0x00, 0x0E,\n                0x08, 0x08, 0x0E, 0x08, 0x08, 0x0E,/*嘧4561*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x02, 0xEA, 0xAA, 0xAF, 0xAA, 0xEA, 0x44, 0x22, 0x03, 0x01, 0x03, 0x08, 0x09,\n                0x0A, 0x04, 0x06, 0x05, 0x08, 0x04,/*嘭4562*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x00, 0xFE, 0x2A, 0xF2, 0x2A, 0xA2, 0xDE, 0x32, 0x03, 0x01, 0x03, 0x08, 0x07,\n                0x09, 0x07, 0x09, 0x05, 0x03, 0x0C,/*噘4563*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x2A, 0xF2, 0xAA, 0xA7, 0xAA, 0xF2, 0x2A, 0x03, 0x01, 0x03, 0x00, 0x08,\n                0x07, 0x0A, 0x0E, 0x02, 0x07, 0x08,/*嘹4564*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x25, 0xAC, 0xB7, 0xE4, 0xB7, 0xAC, 0x25, 0x03, 0x01, 0x03, 0x00, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*噗4565*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x10, 0xF0, 0x5F, 0xF5, 0x15, 0xD5, 0x5F, 0xD0, 0x03, 0x01, 0x03, 0x04, 0x07,\n                0x05, 0x0F, 0x0A, 0x05, 0x02, 0x0D,/*嘬4566*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x10, 0xFC, 0x57, 0x54, 0xFD, 0x56, 0x54, 0x04, 0x03, 0x01, 0x03, 0x0C, 0x03,\n                0x05, 0x09, 0x05, 0x09, 0x05, 0x09,/*噍4567*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x5A, 0x13, 0x7E, 0x12, 0x5A, 0xFE, 0x03, 0x01, 0x03, 0x00, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*噢4568*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x72, 0x46, 0x6D, 0xD7, 0x6D, 0x46, 0x72, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x01, 0x07, 0x05, 0x0F, 0x01, 0x0F,/*噙4569*/},\n        {\n\n                0xFC, 0x04, 0xFC, 0x84, 0xFA, 0xAB, 0xFA, 0xAE, 0xA8, 0xF8, 0x80, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*噜4570*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x3E, 0xAB, 0xA2, 0xBE, 0xA2, 0xAB, 0x3E, 0x03, 0x01, 0x03, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*噌4571*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x20, 0xD5, 0x49, 0x57, 0x50, 0x4F, 0xD2, 0x29, 0x03, 0x01, 0x03, 0x08, 0x0B,\n                0x0D, 0x09, 0x09, 0x0D, 0x0B, 0x08,/*噔4572*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x8A, 0xEF, 0xAA, 0xAE, 0xAA, 0xEF, 0x8A, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x00, 0x0E, 0x0A, 0x0E, 0x00, 0x0F,/*嚆4573*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x0A, 0x5F, 0x52, 0x4A, 0x5F, 0x4A, 0x12, 0x03, 0x01, 0x03, 0x00, 0x05,\n                0x03, 0x09, 0x0F, 0x01, 0x03, 0x05,/*噤4574*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFC, 0x54, 0x54, 0xFF, 0x55, 0x55, 0x6D, 0x03, 0x01, 0x03, 0x04, 0x03,\n                0x05, 0x05, 0x0A, 0x0F, 0x02, 0x05,/*噱4575*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x08, 0xFA, 0xAE, 0xAB, 0xAA, 0xAE, 0xFA, 0x08, 0x03, 0x01, 0x03, 0x04, 0x02,\n                0x0C, 0x09, 0x0A, 0x0C, 0x02, 0x04,/*噫4576*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xA6, 0xAA, 0xFE, 0xAB, 0xFE, 0xAA, 0xA6, 0x03, 0x01, 0x03, 0x00, 0x0A,\n                0x09, 0x0A, 0x0F, 0x0A, 0x09, 0x0A,/*噻4577*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0xFE, 0x92, 0x9E, 0x40, 0x55, 0xE6, 0x54, 0x03, 0x01, 0x03, 0x01, 0x0F,\n                0x04, 0x0F, 0x00, 0x02, 0x0F, 0x02,/*噼4578*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x4C, 0x55, 0x45, 0xDF, 0x45, 0x55, 0x4C, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*嚅4579*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x20, 0x56, 0x2A, 0x5A, 0x43, 0x5A, 0x2A, 0x5E, 0x03, 0x01, 0x03, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*嚓4580*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x80, 0xCD, 0x75, 0x45, 0xDF, 0x65, 0x55, 0x4D, 0x03, 0x01, 0x03, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x04,/*嚯4581*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x00, 0x62, 0xAE, 0xEA, 0xBF, 0xEA, 0xAE, 0x62, 0x03, 0x01, 0x03, 0x00, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*囔4582*/},\n        {\n\n                0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFF, 0x0F, 0x08, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0F,/*囗4583*/},\n        {\n\n                0xFF, 0x01, 0x41, 0x45, 0x45, 0xE5, 0x55, 0x4D, 0x41, 0x01, 0xFF, 0x0F, 0x08, 0x08, 0x08, 0x0A,\n                0x0B, 0x08, 0x08, 0x08, 0x08, 0x0F,/*囝4584*/},\n        {\n\n                0xFF, 0x01, 0x09, 0x29, 0x59, 0x8F, 0x49, 0x39, 0x09, 0x01, 0xFF, 0x0F, 0x08, 0x0A, 0x0A, 0x09,\n                0x08, 0x09, 0x0A, 0x08, 0x08, 0x0F,/*囡4585*/},\n        {\n\n                0xFF, 0x11, 0x11, 0xE9, 0x85, 0x43, 0x25, 0x09, 0x11, 0x11, 0xFF, 0x0F, 0x08, 0x08, 0x09, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0B, 0x08, 0x0F,/*囵4586*/},\n        {\n\n                0xFF, 0x21, 0x91, 0x4F, 0x39, 0x89, 0x79, 0x09, 0xF9, 0x01, 0xFF, 0x0F, 0x08, 0x08, 0x0A, 0x09,\n                0x08, 0x0A, 0x0A, 0x09, 0x08, 0x0F,/*囫4587*/},\n        {\n\n                0xFF, 0x21, 0x51, 0x49, 0x45, 0x53, 0x65, 0xC9, 0x51, 0x21, 0xFF, 0x0F, 0x08, 0x08, 0x08, 0x09,\n                0x0A, 0x0D, 0x08, 0x08, 0x08, 0x0F,/*囹4588*/},\n        {\n\n                0xFF, 0x21, 0x15, 0xFD, 0x55, 0x57, 0x55, 0xF5, 0x05, 0x01, 0xFF, 0x0F, 0x08, 0x08, 0x0F, 0x09,\n                0x09, 0x0D, 0x0F, 0x08, 0x08, 0x0F,/*囿4589*/},\n        {\n\n                0xFF, 0x41, 0x55, 0x75, 0x5D, 0x55, 0x55, 0x75, 0x45, 0x41, 0xFF, 0x0F, 0x08, 0x08, 0x0F, 0x0D,\n                0x0D, 0x0D, 0x0F, 0x08, 0x08, 0x0F,/*圄4590*/},\n        {\n\n                0xFF, 0x41, 0x55, 0xD5, 0x55, 0x7F, 0x55, 0xD5, 0x55, 0x01, 0xFF, 0x0F, 0x08, 0x08, 0x0F, 0x09,\n                0x09, 0x0D, 0x0F, 0x08, 0x08, 0x0F,/*圊4591*/},\n        {\n\n                0xFF, 0x11, 0x55, 0x75, 0x55, 0xDF, 0x55, 0x75, 0x55, 0x11, 0xFF, 0x0F, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x0F,/*圉4592*/},\n        {\n\n                0xFF, 0x11, 0x1D, 0x75, 0xDD, 0x55, 0xDD, 0x75, 0x1D, 0x11, 0xFF, 0x0F, 0x08, 0x0A, 0x09, 0x0F,\n                0x0A, 0x09, 0x0A, 0x0D, 0x08, 0x0F,/*圜4593*/},\n        {\n\n                0xF8, 0x08, 0xFF, 0x08, 0xF8, 0x44, 0x54, 0xFF, 0x54, 0x54, 0xC4, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*帏4594*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x50, 0x4E, 0x48, 0xFF, 0x48, 0x48, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x08, 0x04, 0x03, 0x00, 0x07, 0x08,/*帙4595*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xFC, 0xE4, 0x3F, 0xE4, 0x0C, 0x03, 0x00, 0x0F, 0x02, 0x0B,\n                0x04, 0x0B, 0x05, 0x02, 0x05, 0x08,/*帔4596*/},\n        {\n\n                0x42, 0xAE, 0x93, 0x92, 0xAE, 0xC0, 0xA1, 0x97, 0x89, 0x95, 0x23, 0x00, 0x07, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x04, 0x07, 0x00,/*帑4597*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x2A, 0xEA, 0xBF, 0xAA, 0xEA, 0xA2, 0x01, 0x00, 0x0F, 0x01, 0x05,\n                0x03, 0x00, 0x02, 0x08, 0x0F, 0x00,/*帱4598*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xA2, 0xAA, 0xBF, 0xAA, 0xAA, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x00, 0x0B, 0x04, 0x03, 0x04, 0x0B,/*帻4599*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xFF, 0x25, 0xFD, 0xA5, 0xFF, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x00, 0x0F, 0x0A, 0x0B, 0x0A, 0x0F,/*帼4600*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x10, 0xFC, 0x27, 0xFD, 0x26, 0x24, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x00, 0x0F, 0x09, 0x0F, 0x09, 0x09,/*帷4601*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xFF, 0x05, 0xD5, 0xB5, 0xD7, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x04, 0x03, 0x08, 0x0A, 0x0F, 0x0A,/*幄4602*/},\n        {\n\n                0xF8, 0x08, 0xFF, 0x08, 0x70, 0x5F, 0x75, 0x55, 0x75, 0x5F, 0x70, 0x03, 0x00, 0x0F, 0x00, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*幔4603*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x01, 0x00, 0x0F, 0x01, 0x01,\n                0x02, 0x02, 0x02, 0x0F, 0x02, 0x02,/*幛4604*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0xAA, 0xBF, 0xE8, 0xBF, 0xAA, 0x01, 0x00, 0x0F, 0x01, 0x01,\n                0x02, 0x0A, 0x06, 0x03, 0x06, 0x0A,/*幞4605*/},\n        {\n\n                0xFC, 0x04, 0xFF, 0x04, 0xFC, 0x52, 0xB6, 0x9A, 0xBE, 0x99, 0xB5, 0x03, 0x00, 0x0F, 0x02, 0x03,\n                0x00, 0x0F, 0x0A, 0x0F, 0x0A, 0x0F,/*幡4606*/},\n        {\n\n                0x00, 0x16, 0x14, 0xF4, 0x14, 0x97, 0x14, 0x74, 0x54, 0xC6, 0x00, 0x08, 0x04, 0x03, 0x08, 0x08,\n                0x04, 0x05, 0x02, 0x05, 0x08, 0x08,/*岌4607*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xE2, 0x22, 0x22, 0x22, 0x3E, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*屺4608*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x22, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*岍4609*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x20, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x08, 0x08, 0x05, 0x02, 0x05, 0x08,/*岐4610*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xFE, 0x0A, 0x32, 0xC2, 0x3A, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x0F, 0x0A, 0x09, 0x08, 0x0B,/*岖4611*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0x32, 0xAA, 0x62, 0xFE, 0x22, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x04, 0x02, 0x01, 0x08, 0x0F, 0x00,/*岈4612*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x08, 0x04, 0x03, 0x06, 0x08, 0x0C,/*岘4613*/},\n        {\n\n                0x48, 0x48, 0x2A, 0x1A, 0x0A, 0x8E, 0x09, 0x19, 0x29, 0x48, 0x48, 0x00, 0x0F, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x00,/*岙4614*/},\n        {\n\n                0x40, 0x46, 0x24, 0x24, 0x14, 0x4F, 0x94, 0x24, 0x24, 0x46, 0x40, 0x00, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x09, 0x05, 0x03, 0x01, 0x00,/*岑4615*/},\n        {\n\n                0x00, 0xF6, 0x14, 0x54, 0x94, 0x17, 0x94, 0x54, 0x14, 0xF6, 0x00, 0x08, 0x07, 0x00, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x00, 0x07, 0x0C,/*岚4616*/},\n        {\n\n                0x00, 0xF6, 0x94, 0x94, 0x94, 0xF7, 0x94, 0x94, 0x94, 0xF6, 0x00, 0x00, 0x07, 0x08, 0x08, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*岜4617*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*岵4618*/},\n        {\n\n                0x10, 0xD6, 0x54, 0x54, 0x54, 0xD7, 0x14, 0x14, 0xF4, 0x16, 0x10, 0x00, 0x07, 0x02, 0x02, 0x02,\n                0x03, 0x08, 0x08, 0x0F, 0x00, 0x00,/*岢4619*/},\n        {\n\n                0x10, 0xD6, 0xB4, 0x94, 0x9C, 0xD7, 0x94, 0x94, 0x94, 0x96, 0x10, 0x08, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x08,/*岽4620*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xFE, 0x92, 0xFE, 0x92, 0xFE, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x01, 0x00, 0x0F, 0x00, 0x01,/*岬4621*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xF8, 0x48, 0xFF, 0x48, 0xF8, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x04, 0x07, 0x04, 0x0F,/*岫4622*/},\n        {\n\n                0x10, 0x08, 0x7C, 0x03, 0x08, 0x88, 0x0F, 0x18, 0x25, 0x46, 0x74, 0x00, 0x0F, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x00,/*岱4623*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x10, 0xE8, 0x27, 0xE4, 0x04, 0xFC, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x03, 0x01, 0x09, 0x08, 0x07,/*岣4624*/},\n        {\n\n                0xE0, 0x26, 0x14, 0x94, 0xC4, 0x07, 0xE4, 0x24, 0x24, 0x26, 0xE0, 0x03, 0x02, 0x09, 0x04, 0x03,\n                0x00, 0x0F, 0x00, 0x00, 0x02, 0x03,/*峁4625*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xFF, 0x49, 0xF9, 0x49, 0x4F, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x0F, 0x04, 0x03, 0x04, 0x0E,/*岷4626*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF9, 0xA3, 0x95, 0xE9, 0x95, 0xA3, 0x20, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*峄4627*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xFE, 0x02, 0xEA, 0x2A, 0xEA, 0x02, 0xFE, 0x03, 0x02, 0x01, 0x01, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*峒4628*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x2A, 0x9A, 0x0E, 0x19, 0xA9, 0x48, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*峤4629*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x04, 0xFB, 0x4A, 0xFA, 0x02, 0xFE, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x07, 0x02, 0x0B, 0x08, 0x07,/*峋4630*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x54, 0x53, 0xFA, 0x56, 0xF0, 0x40, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x01, 0x09, 0x0F, 0x01, 0x03, 0x00,/*峥4631*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0xB2, 0x97, 0xD2, 0x92, 0x97, 0xB2, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x08, 0x04, 0x03, 0x08, 0x08, 0x07,/*崂4632*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xFC, 0x54, 0x64, 0xFF, 0x64, 0x54, 0x44, 0x03, 0x02, 0x01, 0x01, 0x05,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*崃4633*/},\n        {\n\n                0x20, 0xA6, 0xFC, 0xA4, 0x04, 0x47, 0x34, 0x84, 0x04, 0x36, 0x40, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*崧4634*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0x12, 0xEA, 0xA6, 0xF3, 0xA6, 0xEA, 0x12, 0x03, 0x02, 0x01, 0x01, 0x00,\n                0x07, 0x02, 0x07, 0x0A, 0x0B, 0x0C,/*崦4635*/},\n        {\n\n                0x00, 0xFB, 0x2A, 0xAA, 0xAA, 0xFB, 0xAA, 0xAA, 0x2A, 0xFB, 0x00, 0x00, 0x0F, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0B, 0x08, 0x0F, 0x00,/*崮4636*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x4D, 0xFA, 0xAE, 0xAA, 0xED, 0x08, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x0F, 0x02, 0x0A, 0x0F, 0x00,/*崤4637*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xBA, 0xAA, 0xAB, 0xAA, 0x3A, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x02, 0x0A, 0x0E, 0x03, 0x02,/*崞4638*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xAC, 0x95, 0x86, 0x94, 0xAC, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,/*崆4639*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xFE, 0x0A, 0xEA, 0x8A, 0xFA, 0x8A, 0xEE, 0x03, 0x02, 0x01, 0x09, 0x07,\n                0x00, 0x0E, 0x08, 0x0F, 0x08, 0x0E,/*崛4640*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xB2, 0x97, 0xD2, 0x97, 0xB2, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x04, 0x02, 0x0F, 0x02, 0x04,/*嵘4641*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xBA, 0xAA, 0xBE, 0xEA, 0xBE, 0xAA, 0xBA, 0x03, 0x02, 0x01, 0x01, 0x08,\n                0x0A, 0x0B, 0x04, 0x04, 0x0B, 0x08,/*崾4642*/},\n        {\n\n                0x00, 0xF6, 0x54, 0xD4, 0x54, 0x57, 0x14, 0xFC, 0x14, 0xDE, 0x10, 0x08, 0x07, 0x09, 0x0B, 0x05,\n                0x0B, 0x08, 0x04, 0x03, 0x04, 0x0E,/*崴4643*/},\n        {\n\n                0x00, 0xF6, 0x54, 0x54, 0x54, 0xF7, 0x54, 0x54, 0x54, 0xF6, 0x00, 0x08, 0x05, 0x01, 0x05, 0x0B,\n                0x0D, 0x09, 0x0D, 0x01, 0x05, 0x08,/*崽4644*/},\n        {\n\n                0x00, 0xFB, 0xAA, 0xAA, 0xEE, 0xBB, 0xAA, 0xAA, 0xAA, 0xFB, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x06, 0x0B, 0x0A, 0x0B, 0x0A, 0x0C,/*嵬4645*/},\n        {\n\n                0x20, 0xE6, 0xB4, 0xB4, 0xAC, 0xE7, 0x0C, 0xD4, 0x14, 0xE6, 0x20, 0x00, 0x0F, 0x02, 0x02, 0x0A,\n                0x0F, 0x00, 0x03, 0x08, 0x0F, 0x00,/*嵛4646*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x44, 0xD5, 0x76, 0x5C, 0x56, 0x55, 0x03, 0x02, 0x01, 0x01, 0x05,\n                0x0A, 0x09, 0x09, 0x0F, 0x09, 0x09,/*嵯4647*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x80, 0x95, 0xCC, 0xBF, 0x8C, 0x95, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x0A, 0x05, 0x04, 0x0B, 0x00,/*嵝4648*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xE8, 0x99, 0x4A, 0x08, 0xEC, 0x9B, 0x48, 0x03, 0x02, 0x01, 0x01, 0x06,\n                0x05, 0x0E, 0x00, 0x06, 0x05, 0x0E,/*嵫4649*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x00, 0xFF, 0x09, 0xEF, 0xA9, 0xEF, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x08, 0x07, 0x00, 0x0F, 0x0A, 0x0F,/*嵋4650*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xA8, 0xFA, 0x0A, 0xFE, 0x09, 0xF9, 0xA8, 0x03, 0x02, 0x01, 0x01, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*嵊4651*/},\n        {\n\n                0x88, 0x8B, 0xEA, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0xEA, 0x8B, 0x88, 0x0F, 0x00, 0x00, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0E, 0x00, 0x08, 0x0F,/*嵩4652*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x15, 0xEA, 0xA7, 0xA8, 0xF2, 0x25, 0x03, 0x02, 0x01, 0x01, 0x03,\n                0x00, 0x0F, 0x02, 0x0A, 0x0F, 0x00,/*嵴4653*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x07, 0x04, 0x03, 0x02, 0x07,\n                0x02, 0x02, 0x02, 0x0F, 0x02, 0x02,/*嶂4654*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0x95, 0x6E, 0xC4, 0x1F, 0x44, 0xEE, 0x55, 0x03, 0x02, 0x01, 0x01, 0x09,\n                0x06, 0x01, 0x03, 0x02, 0x0F, 0x02,/*嶙4655*/},\n        {\n\n                0xF8, 0x00, 0xFF, 0x00, 0xF5, 0x09, 0xD7, 0x50, 0xD7, 0x0A, 0x15, 0x03, 0x02, 0x01, 0x01, 0x0B,\n                0x08, 0x0D, 0x09, 0x0D, 0x08, 0x08,/*嶝4656*/},\n        {\n\n                0xFC, 0xAA, 0x56, 0xFA, 0x50, 0xFF, 0xAA, 0x56, 0xFA, 0x50, 0xFC, 0x0F, 0x08, 0x0A, 0x0B, 0x08,\n                0x0F, 0x08, 0x0A, 0x0B, 0x08, 0x0F,/*豳4657*/},\n        {\n\n                0x00, 0xDB, 0xAA, 0xA6, 0xB2, 0x03, 0x4A, 0x5A, 0xEA, 0x5B, 0xC0, 0x0B, 0x06, 0x03, 0x06, 0x0A,\n                0x08, 0x07, 0x08, 0x0F, 0x0A, 0x08,/*嶷4658*/},\n        {\n\n                0xE8, 0x2B, 0xBE, 0x2A, 0xEA, 0x03, 0xEA, 0x2A, 0xBA, 0x2B, 0xE8, 0x0B, 0x06, 0x03, 0x06, 0x0B,\n                0x02, 0x09, 0x04, 0x03, 0x04, 0x09,/*巅4659*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*彳4660*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x04, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*彷4661*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*徂4662*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x04, 0xFB, 0x4A, 0x4A, 0xFA, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x02, 0x02, 0x0B, 0x08, 0x07,/*徇4663*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x00, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*徉4664*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x20, 0x24, 0xF6, 0xAD, 0xA4, 0xB2, 0x60, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x09, 0x0A, 0x04, 0x0A, 0x09, 0x08,/*後4665*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x44, 0x54, 0x64, 0xFF, 0x64, 0x54, 0x44, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*徕4666*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x20, 0xBC, 0x20, 0xBF, 0x24, 0x24, 0x24, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x04, 0x0F, 0x09, 0x09, 0x09,/*徙4667*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0xF2, 0x14, 0xD0, 0x5F, 0xD0, 0x14, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*徜4668*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x80, 0xBE, 0xAB, 0xAA, 0xAA, 0xBE, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*徨4669*/},\n        {\n\n                0x48, 0x24, 0xF2, 0x09, 0x4A, 0x32, 0x26, 0xEA, 0x21, 0x29, 0x05, 0x00, 0x00, 0x0F, 0x00, 0x0D,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x0D,/*徭4670*/},\n        {\n\n                0x24, 0xF2, 0x0F, 0x54, 0xD7, 0x54, 0x16, 0xEC, 0x0B, 0xF8, 0x08, 0x00, 0x0F, 0x00, 0x05, 0x07,\n                0x05, 0x08, 0x04, 0x03, 0x04, 0x08,/*徵4671*/},\n        {\n\n                0x24, 0xF2, 0x89, 0xBE, 0xEB, 0xBE, 0x10, 0xEC, 0x0B, 0xF8, 0x08, 0x00, 0x0F, 0x08, 0x07, 0x0A,\n                0x0E, 0x08, 0x04, 0x03, 0x04, 0x08,/*徼4672*/},\n        {\n\n                0x24, 0xF2, 0x89, 0xDF, 0x75, 0xDF, 0x75, 0x5F, 0x12, 0xF2, 0x12, 0x00, 0x0F, 0x00, 0x0F, 0x05,\n                0x07, 0x05, 0x05, 0x08, 0x0F, 0x00,/*衢4673*/},\n        {\n\n                0x00, 0x00, 0x88, 0x88, 0x44, 0x44, 0x22, 0x11, 0x88, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x04,\n                0x04, 0x02, 0x01, 0x00, 0x00, 0x00,/*彡4674*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x08, 0x08, 0x07, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*犭4675*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x08, 0xFF, 0x08, 0x08, 0xF8, 0x00, 0x00, 0x08, 0x08, 0x07, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x07, 0x08, 0x0E,/*犰4676*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x40, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x08, 0x08, 0x07, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*犴4677*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x00, 0xFC, 0x04, 0x05, 0x06, 0x04, 0x04, 0x01, 0x08, 0x08, 0x07, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*犷4678*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x01, 0x3D, 0x21, 0x21, 0x21, 0x3F, 0xE0, 0x08, 0x08, 0x07, 0x00, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x07,/*犸4679*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x42, 0xC2, 0x7E, 0x42, 0x42, 0xFE, 0x00, 0x08, 0x08, 0x07, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*狃4680*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x10, 0x18, 0xF4, 0x13, 0xF0, 0x14, 0x38, 0x00, 0x08, 0x08, 0x07, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x08, 0x08, 0x0E,/*狁4681*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x92, 0x92, 0xFE, 0x08, 0x08, 0x07, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*狎4682*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x08, 0xF4, 0x97, 0x94, 0xF4, 0x04, 0xFC, 0x01, 0x08, 0x08, 0x07, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x09, 0x0D,/*狍4683*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xF2, 0x92, 0xFF, 0x92, 0xFF, 0x92, 0x9E, 0x08, 0x08, 0x07, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x0F, 0x04, 0x07,/*狒4684*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x88, 0xE8, 0x88, 0xFF, 0x08, 0xE9, 0x0A, 0x08, 0x08, 0x07, 0x08, 0x04,\n                0x03, 0x08, 0x04, 0x03, 0x04, 0x0E,/*狨4685*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x88, 0x94, 0x92, 0x91, 0x92, 0x94, 0x88, 0x08, 0x08, 0x07, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*狯4686*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x2C, 0xA4, 0x25, 0x26, 0xF4, 0x24, 0x2C, 0x08, 0x08, 0x07, 0x00, 0x00,\n                0x00, 0x09, 0x08, 0x0F, 0x00, 0x00,/*狩4687*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x42, 0xFA, 0xA6, 0x70, 0x00, 0xFF, 0x10, 0xE0, 0x08, 0x08, 0x07, 0x08, 0x0F,\n                0x00, 0x00, 0x08, 0x0F, 0x00, 0x00,/*狲4688*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x3F, 0x24, 0x14, 0xC0, 0x1F, 0x24, 0x32, 0x08, 0x08, 0x07, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*狴4689*/},\n        {\n\n                0x10, 0x8A, 0x44, 0xFB, 0x00, 0xF7, 0x55, 0x55, 0x55, 0x55, 0xF7, 0x01, 0x08, 0x08, 0x07, 0x00,\n                0x0F, 0x01, 0x01, 0x01, 0x09, 0x0F,/*狷4690*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x10, 0x92, 0xFE, 0x91, 0x10, 0xFC, 0x00, 0xFF, 0x08, 0x08, 0x07, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x01, 0x08, 0x0F,/*猁4691*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x48, 0x54, 0x52, 0xF1, 0x52, 0x54, 0x48, 0x08, 0x08, 0x07, 0x00, 0x04,\n                0x03, 0x08, 0x0F, 0x00, 0x01, 0x06,/*狳4692*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x08, 0x08, 0x07, 0x00, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*猃4693*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x04, 0x54, 0x54, 0x55, 0x56, 0x54, 0x54, 0x04, 0x08, 0x08, 0x07, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*狺4694*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x24, 0x96, 0x65, 0x44, 0x44, 0xD6, 0x2C, 0x08, 0x08, 0x07, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*狻4695*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x10, 0xDA, 0x56, 0x53, 0xD2, 0x16, 0xFA, 0x10, 0x08, 0x08, 0x07, 0x00, 0x07,\n                0x02, 0x02, 0x0B, 0x08, 0x0F, 0x00,/*猗4696*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xBE, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xBE, 0x08, 0x08, 0x07, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*猓4697*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x1E, 0x92, 0x7E, 0x52, 0x5E, 0x52, 0xDE, 0x08, 0x08, 0x07, 0x00, 0x09,\n                0x08, 0x05, 0x06, 0x02, 0x01, 0x00,/*猡4698*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xFE, 0x92, 0x81, 0x90, 0x92, 0xFE, 0x00, 0x08, 0x08, 0x07, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0C,/*猊4699*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x28, 0xA4, 0xAA, 0xF9, 0xAA, 0xA4, 0x28, 0x08, 0x08, 0x07, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*猞4700*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x24, 0x1C, 0x25, 0x86, 0x24, 0x1C, 0x24, 0x08, 0x08, 0x07, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*猝4701*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x79, 0xCF, 0x10, 0xCF, 0xF4, 0x44, 0x8C, 0x08, 0x08, 0x07, 0x00, 0x08,\n                0x0F, 0x01, 0x08, 0x0F, 0x00, 0x01,/*猕4702*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xE4, 0x3F, 0xE4, 0x00, 0xFF, 0x89, 0xFF, 0x08, 0x08, 0x07, 0x00, 0x07,\n                0x02, 0x0B, 0x04, 0x03, 0x08, 0x0F,/*猢4703*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x12, 0xEA, 0xA6, 0xBF, 0xA6, 0xEA, 0x12, 0x08, 0x08, 0x07, 0x00, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*猹4704*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x40, 0xDF, 0x55, 0x55, 0xDF, 0x55, 0x55, 0x5F, 0x08, 0x08, 0x07, 0x00, 0x0F,\n                0x08, 0x04, 0x01, 0x02, 0x06, 0x09,/*猥4705*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x1F, 0xF5, 0x55, 0x5F, 0x55, 0xF5, 0x1F, 0x08, 0x08, 0x07, 0x00, 0x00,\n                0x0F, 0x01, 0x01, 0x09, 0x0F, 0x00,/*猬4706*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xFF, 0x09, 0xE9, 0xAF, 0xA9, 0xA9, 0xEF, 0x08, 0x08, 0x07, 0x08, 0x07,\n                0x00, 0x0F, 0x0A, 0x0A, 0x0A, 0x0F,/*猸4707*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x48, 0x29, 0x1B, 0xCD, 0x7D, 0x0B, 0x18, 0x08, 0x08, 0x07, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*猱4708*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x08, 0x08, 0x08, 0x07, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*獐4709*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x08, 0xEA, 0xAE, 0xAB, 0xAA, 0xAE, 0xEA, 0x08, 0x08, 0x08, 0x07, 0x08, 0x0B,\n                0x06, 0x02, 0x02, 0x0E, 0x0B, 0x0C,/*獍4710*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xFE, 0x2A, 0xF2, 0x2A, 0xA2, 0xDE, 0x32, 0x08, 0x08, 0x07, 0x08, 0x07,\n                0x09, 0x07, 0x09, 0x05, 0x03, 0x0C,/*獗4711*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0x2A, 0xF2, 0xAA, 0xA7, 0xAA, 0xF2, 0x2A, 0x08, 0x08, 0x07, 0x00, 0x08,\n                0x07, 0x0A, 0x0E, 0x02, 0x07, 0x08,/*獠4712*/},\n        {\n\n                0x8A, 0xFC, 0x0B, 0xF4, 0x53, 0xFA, 0x56, 0xF9, 0x27, 0xF9, 0x2F, 0x08, 0x07, 0x08, 0x07, 0x01,\n                0x07, 0x09, 0x0F, 0x01, 0x0F, 0x01,/*獬4713*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xF4, 0x55, 0x15, 0xFF, 0x15, 0x55, 0xF4, 0x08, 0x08, 0x07, 0x00, 0x0D,\n                0x05, 0x0D, 0x07, 0x0D, 0x05, 0x0D,/*獯4714*/},\n        {\n\n                0x8A, 0x44, 0xFB, 0x00, 0xBA, 0xEF, 0xBA, 0xC2, 0xBA, 0xAF, 0xBA, 0x08, 0x08, 0x07, 0x01, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*獾4715*/},\n        {\n\n                0x40, 0x30, 0x4F, 0x88, 0x78, 0x00, 0xF4, 0x04, 0xFF, 0x04, 0x04, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x01, 0x01, 0x0F, 0x01, 0x01,/*舛4716*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x00, 0x24, 0xAB, 0x52, 0x4A, 0xC6, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x00, 0x09, 0x08, 0x05, 0x02, 0x01,/*夥4717*/},\n        {\n\n                0x20, 0x5F, 0x84, 0x7C, 0x08, 0xF4, 0x52, 0x59, 0x52, 0xF4, 0x08, 0x08, 0x06, 0x01, 0x00, 0x00,\n                0x0F, 0x05, 0x01, 0x03, 0x05, 0x0A,/*飧4718*/},\n        {\n\n                0x10, 0xF4, 0xB4, 0xAA, 0xAB, 0xFE, 0xAA, 0xAE, 0xAA, 0xE8, 0x18, 0x00, 0x0B, 0x06, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x06, 0x0B, 0x00,/*夤4719*/},\n        {\n\n                0x40, 0x20, 0x10, 0x6C, 0x8B, 0x08, 0x88, 0x48, 0x38, 0x00, 0x00, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x04, 0x08, 0x08,/*夂4720*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x02, 0x01, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*饣4721*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x00, 0x22, 0xF2, 0x2A, 0xE6, 0x22, 0xE0, 0x00, 0x07, 0x02, 0x01, 0x02,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*饧4722*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0xF4, 0x84, 0x84, 0xFF, 0x84, 0x84, 0xF4, 0x00, 0x0F, 0x04, 0x00, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*饨4723*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x48, 0x57, 0x54, 0x54, 0xD4, 0x04, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x0E,/*饩4724*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x40, 0x44, 0x44, 0xFC, 0x42, 0x42, 0x40, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x00,/*饪4725*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*饫4726*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x10, 0x48, 0x47, 0xF4, 0x44, 0x44, 0xC4, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*饬4727*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x10, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*饴4728*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0xFC, 0x04, 0xE6, 0x25, 0xE4, 0x04, 0xFC, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*饷4729*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0x1A, 0x2A, 0x2A, 0xAF, 0x6A, 0x2A, 0x1A, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x01, 0x09, 0x0F, 0x01, 0x01, 0x01,/*饽4730*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0x48, 0x54, 0x52, 0xF1, 0x52, 0x54, 0x48, 0x00, 0x0F, 0x04, 0x00, 0x04,\n                0x03, 0x08, 0x0F, 0x00, 0x01, 0x06,/*馀4731*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0xDF, 0x15, 0x15, 0x15, 0xD5, 0x1F, 0x80, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x09, 0x05, 0x00, 0x07, 0x09, 0x0C,/*馄4732*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x12, 0xEA, 0xA6, 0xBF, 0xA6, 0xEA, 0x12, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*馇4733*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0xBC, 0xAA, 0xA0, 0xFF, 0xA0, 0xAA, 0xBE, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x09, 0x0A, 0x04, 0x04, 0x0A, 0x09,/*馊4734*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x02, 0xFA, 0xAF, 0xAA, 0xAF, 0xFA, 0x02, 0x00, 0x07, 0x02, 0x01, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*馍4735*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0xA2, 0x6B, 0xBA, 0xAE, 0xAA, 0xAB, 0x22, 0x00, 0x0F, 0x04, 0x01, 0x08,\n                0x0A, 0x0E, 0x0B, 0x0A, 0x0F, 0x08,/*馐4736*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0xE2, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xE2, 0x00, 0x0F, 0x04, 0x00, 0x0A,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0A,/*馑4737*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x0A, 0xEF, 0xAA, 0xEF, 0x1A, 0xEC, 0x0B, 0xF8, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x02, 0x0F, 0x08, 0x04, 0x03, 0x0C,/*馓4738*/},\n        {\n\n                0x08, 0xE7, 0x0C, 0x00, 0x9F, 0xE5, 0xB7, 0x80, 0x9F, 0xE5, 0xB7, 0x00, 0x0F, 0x04, 0x02, 0x0A,\n                0x07, 0x02, 0x02, 0x02, 0x07, 0x0A,/*馔4739*/},\n        {\n\n                0x08, 0xE7, 0x14, 0x0C, 0x62, 0xAE, 0xEA, 0xBF, 0xEA, 0xAE, 0x62, 0x00, 0x0F, 0x04, 0x02, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*馕4740*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x04, 0xF4, 0x85, 0x86, 0x44, 0x44, 0x24, 0x04, 0x08, 0x07, 0x00, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*庀4741*/},\n        {\n\n                0x00, 0xFC, 0x84, 0x94, 0x94, 0x95, 0xF6, 0x94, 0x94, 0x94, 0x84, 0x08, 0x07, 0x08, 0x08, 0x04,\n                0x02, 0x01, 0x07, 0x08, 0x08, 0x0C,/*庑4742*/},\n        {\n\n                0x00, 0xFE, 0x12, 0x52, 0xD2, 0x52, 0x7F, 0x52, 0x52, 0xD2, 0x12, 0x08, 0x07, 0x00, 0x08, 0x08,\n                0x05, 0x02, 0x02, 0x05, 0x08, 0x08,/*庋4743*/},\n        {\n\n                0x00, 0xFE, 0x22, 0x12, 0xEE, 0x2A, 0x2B, 0xEA, 0x0A, 0xFA, 0x02, 0x08, 0x07, 0x00, 0x00, 0x07,\n                0x09, 0x09, 0x09, 0x0A, 0x0B, 0x0C,/*庖4744*/},\n        {\n\n                0x00, 0xFE, 0x22, 0xF2, 0x0A, 0x22, 0xA3, 0xFA, 0xA2, 0x22, 0x22, 0x08, 0x07, 0x00, 0x0F, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*庥4745*/},\n        {\n\n                0x00, 0xFC, 0x04, 0x24, 0xAC, 0xB5, 0xE6, 0xB4, 0xAC, 0x24, 0x04, 0x08, 0x07, 0x02, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x02, 0x02,/*庠4746*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0x8A, 0xBE, 0xAA, 0xAB, 0xAA, 0xBE, 0x8A, 0x0A, 0x08, 0x07, 0x08, 0x07, 0x02,\n                0x02, 0x02, 0x02, 0x06, 0x0B, 0x08,/*庹4747*/},\n        {\n\n                0x00, 0xFE, 0x4A, 0xEA, 0xBA, 0xAE, 0xFB, 0xAA, 0xBA, 0xEA, 0x4A, 0x08, 0x07, 0x00, 0x07, 0x02,\n                0x02, 0x07, 0x0A, 0x0A, 0x0B, 0x0C,/*庵4748*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xE2, 0x52, 0x02, 0xFB, 0x02, 0x52, 0xF2, 0x02, 0x08, 0x07, 0x08, 0x09, 0x05,\n                0x03, 0x01, 0x03, 0x05, 0x09, 0x08,/*庾4749*/},\n        {\n\n                0x00, 0xFE, 0x02, 0xFA, 0xAA, 0xEE, 0xBB, 0xAA, 0xAA, 0xFA, 0x02, 0x08, 0x07, 0x02, 0x02, 0x03,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*庳4750*/},\n        {\n\n                0x00, 0xFE, 0x22, 0xAA, 0xEA, 0xAB, 0xBE, 0xAA, 0xAA, 0xFA, 0x22, 0x08, 0x07, 0x01, 0x0B, 0x08,\n                0x04, 0x03, 0x04, 0x04, 0x0B, 0x01,/*赓4751*/},\n        {\n\n                0x00, 0xFE, 0x82, 0xAA, 0xFE, 0xAA, 0x43, 0xFE, 0x12, 0xF2, 0x12, 0x08, 0x07, 0x08, 0x07, 0x0A,\n                0x0E, 0x08, 0x05, 0x02, 0x05, 0x08,/*廒4752*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xEA, 0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0xEA, 0x0A, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*廑4753*/},\n        {\n\n                0x00, 0xFE, 0x82, 0xFA, 0xAA, 0xAA, 0xFB, 0xAA, 0xAA, 0xFA, 0x82, 0x08, 0x07, 0x04, 0x0A, 0x09,\n                0x0A, 0x0F, 0x0A, 0x09, 0x0A, 0x04,/*廛4754*/},\n        {\n\n                0x00, 0xFE, 0x12, 0xEA, 0xAE, 0xFA, 0xA3, 0xEA, 0x9A, 0xEA, 0xBA, 0x08, 0x07, 0x08, 0x07, 0x02,\n                0x07, 0x0A, 0x0F, 0x02, 0x0F, 0x02,/*廨4755*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xFA, 0x8A, 0xEB, 0xAE, 0xEA, 0x8A, 0xFA, 0x0A, 0x08, 0x07, 0x02, 0x0A, 0x06,\n                0x0A, 0x0E, 0x02, 0x06, 0x0A, 0x02,/*廪4756*/},\n        {\n\n                0x00, 0xFE, 0x22, 0xFA, 0x96, 0xFA, 0xAF, 0xAA, 0xFE, 0xAA, 0xAA, 0x08, 0x07, 0x00, 0x0F, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*膺4757*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*忄4758*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0x02, 0xFE, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*忉4759*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x00, 0x48, 0x88, 0x08, 0x08, 0xFF, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x01, 0x08, 0x08, 0x0F, 0x00,/*忖4760*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x20, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*忏4761*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x20, 0x22, 0xE2, 0x3E, 0xE2, 0x22, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*怃4762*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x24, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*忮4763*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x02, 0x0A, 0x32, 0xC2, 0x3A, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x08, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*怄4764*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xF8, 0x88, 0x88, 0xFF, 0x88, 0x88, 0xF8, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*忡4765*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x88, 0x87, 0x84, 0xFC, 0x84, 0x84, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*忤4766*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x48, 0x57, 0x54, 0x54, 0xD4, 0x04, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x0E,/*忾4767*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x20, 0xFF, 0x28, 0x24, 0xE4, 0x22, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x02, 0x00, 0x03, 0x04,/*怅4768*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0xE8, 0x24, 0x23, 0x24, 0xE8, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x09, 0x09, 0x0C,/*怆4769*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x24, 0x18, 0x87, 0x60, 0x00, 0x07, 0x18, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x06,\n                0x05, 0x04, 0x04, 0x05, 0x0E, 0x00,/*忪4770*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0x08, 0x08, 0xF9, 0x4A, 0x88, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*忭4771*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x42, 0xC2, 0x7E, 0x42, 0x42, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*忸4772*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x08, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*怙4773*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x08, 0x88, 0x68, 0xFF, 0x68, 0x89, 0x0A, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*怵4774*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x88, 0xB2, 0x82, 0xFE, 0x82, 0xA2, 0x98, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*怦4775*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x00, 0xFE, 0x22, 0x22, 0x22, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*怛4776*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x80, 0xFC, 0x84, 0xFF, 0x84, 0xFC, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*怏4777*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*怍4778*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x00, 0xFE, 0x12, 0xD2, 0x12, 0x92, 0x5E, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x07, 0x09, 0x08, 0x0E,/*怩4779*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xF2, 0x92, 0xFF, 0x92, 0xFF, 0x92, 0x9E, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x0F, 0x04, 0x07,/*怫4780*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x22, 0x92, 0x8E, 0x82, 0xA2, 0xA2, 0x9E, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*怊4781*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x21, 0xA3, 0x95, 0xE9, 0x95, 0xA3, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*怿4782*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*怡4783*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x92, 0x72, 0x92, 0x04, 0xFF, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x0B, 0x04, 0x03, 0x08, 0x0F,/*恸4784*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x26, 0x2A, 0x00, 0x00, 0x0F, 0x04, 0x0B,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*恹4785*/},\n        {\n\n                0x30, 0xFF, 0x08, 0xFE, 0xC2, 0x02, 0xFE, 0x00, 0xFC, 0x00, 0xFF, 0x00, 0x0F, 0x08, 0x04, 0x03,\n                0x04, 0x08, 0x00, 0x01, 0x08, 0x0F,/*恻4786*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x2E, 0x28, 0x28, 0x2F, 0x28, 0xE8, 0x0E, 0x00, 0x00, 0x0F, 0x00, 0x07,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x0C,/*恺4787*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x14, 0xFB, 0x4A, 0x4A, 0xFA, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x02, 0x02, 0x0B, 0x08, 0x07,/*恂4788*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*恪4789*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x16, 0xD2, 0xB2, 0xDA, 0x92, 0x92, 0x06, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*恽4790*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x1A, 0x2A, 0x2A, 0xAF, 0x6A, 0x2A, 0x1A, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x09, 0x0F, 0x01, 0x01, 0x01,/*悖4791*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xF4, 0x94, 0x94, 0xFF, 0x94, 0x94, 0xF4, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*悚4792*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x3E, 0x00, 0x7F, 0x82, 0x5E, 0x22, 0x5E, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*悭4793*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x10, 0x7F, 0x49, 0xFF, 0x49, 0x7F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*悝4794*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x92, 0x52, 0xFE, 0x52, 0x92, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*悃4795*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xF0, 0x97, 0x95, 0xF5, 0x95, 0x97, 0xF0, 0x00, 0x00, 0x0F, 0x00, 0x07,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*悒4796*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x74, 0x55, 0x56, 0xFC, 0x56, 0x5D, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x00, 0x02, 0x03,/*悌4797*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x24, 0x96, 0x65, 0x44, 0x44, 0xD6, 0x2C, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*悛4798*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x02, 0xAA, 0x8A, 0xFE, 0x8A, 0xAA, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x08, 0x0C, 0x0A, 0x09, 0x0A, 0x0C,/*惬4799*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x08, 0x5A, 0x6A, 0xCF, 0x6A, 0x5A, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*悻4800*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x24, 0x24, 0xFF, 0x00, 0xFF, 0x24, 0x24, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x0F, 0x00, 0x0F, 0x01, 0x01,/*悱4801*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xF2, 0x14, 0xD0, 0x5F, 0xD0, 0x14, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*惝4802*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x56, 0xDA, 0x72, 0x5A, 0x56, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x02, 0x08, 0x0F,/*惘4803*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFF, 0x21, 0xA9, 0xBD, 0xA9, 0x21, 0xFF, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x00, 0x03, 0x02, 0x0B, 0x08, 0x0F,/*惆4804*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x24, 0x53, 0xAE, 0x12, 0x4E, 0x42, 0x3E, 0x00, 0x00, 0x0F, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*惚4805*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x24, 0x1C, 0x25, 0x86, 0x24, 0x1C, 0x24, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*悴4806*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xC0, 0x5F, 0xD5, 0x55, 0xD5, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*愠4807*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x20, 0xAE, 0xAA, 0xBF, 0xAA, 0xAA, 0xAE, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0B, 0x04, 0x03, 0x04, 0x04, 0x0B,/*愦4808*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x47, 0xD5, 0x57, 0x50, 0x57, 0x55, 0x47, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*愕4809*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x2F, 0x29, 0xEF, 0xB9, 0xAF, 0xA9, 0xAF, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*愣4810*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xAE, 0xA8, 0xA8, 0xEF, 0xA8, 0xA8, 0xAE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0F,/*惴4811*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x92, 0xFE, 0x51, 0x08, 0xFF, 0x10, 0x0C, 0x00, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x08, 0x07, 0x00, 0x07, 0x08,/*愀4812*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x02, 0x7D, 0xD5, 0x55, 0x55, 0x7D, 0x01, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*愎4813*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x22, 0xAA, 0xEA, 0xBF, 0xAA, 0x6A, 0x22, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x06, 0x0A, 0x0F, 0x02, 0x06, 0x0B,/*愫4814*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x48, 0x55, 0xFE, 0x54, 0xFE, 0x55, 0xF4, 0x40, 0x00, 0x00, 0x0F, 0x04, 0x03,\n                0x0F, 0x01, 0x0F, 0x03, 0x05, 0x08,/*慊4815*/},\n        {\n\n                0x30, 0xFF, 0x08, 0xFE, 0x22, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x00, 0x0F, 0x08, 0x07, 0x00,\n                0x0F, 0x02, 0x07, 0x0A, 0x0F, 0x00,/*慵4816*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x40, 0xDF, 0x55, 0x75, 0x55, 0xDF, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x08,/*憬4817*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x08, 0xFC, 0x57, 0x54, 0xFD, 0x56, 0x54, 0x00, 0x00, 0x0F, 0x00, 0x0C,\n                0x03, 0x0D, 0x01, 0x0D, 0x01, 0x0D,/*憔4818*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x08, 0xFA, 0xAE, 0xFB, 0xAE, 0xFA, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*憧4819*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x52, 0x7F, 0x4A, 0xD2, 0x7F, 0x4A, 0xD2, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x04, 0x0F, 0x09, 0x09, 0x08,/*憷4820*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xFA, 0x8A, 0xEA, 0xAB, 0xEA, 0x8A, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x06, 0x0A, 0x0E, 0x02, 0x06, 0x0A,/*懔4821*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0xBA, 0xAF, 0xBA, 0xAA, 0xBA, 0xAF, 0xBA, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x0F, 0x0A, 0x0F, 0x00, 0x01,/*懵4822*/},\n        {\n\n                0x48, 0x48, 0x29, 0x19, 0x0D, 0xCB, 0x09, 0x19, 0x29, 0x48, 0x48, 0x00, 0x04, 0x02, 0x01, 0x08,\n                0x0F, 0x00, 0x01, 0x06, 0x01, 0x06,/*忝4823*/},\n        {\n\n                0x00, 0x7F, 0xA5, 0x9B, 0x50, 0x4A, 0x7E, 0xAB, 0xAE, 0x7A, 0x0A, 0x01, 0x01, 0x04, 0x02, 0x08,\n                0x0F, 0x02, 0x04, 0x02, 0x05, 0x01,/*隳4824*/},\n        {\n\n                0xF9, 0x02, 0x40, 0x41, 0x41, 0x41, 0x41, 0x41, 0x41, 0x01, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*闩4825*/},\n        {\n\n                0xF9, 0x02, 0x00, 0x49, 0x49, 0x49, 0x49, 0x49, 0x01, 0x01, 0xFF, 0x0F, 0x00, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x02, 0x08, 0x0F,/*闫4826*/},\n        {\n\n                0xF9, 0x02, 0x88, 0xA9, 0xA9, 0xFD, 0xA9, 0xA9, 0x89, 0x01, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x02, 0x03, 0x08, 0x0F,/*闱4827*/},\n        {\n\n                0xF9, 0x02, 0x10, 0xD1, 0x3D, 0x11, 0xD1, 0x11, 0x11, 0x01, 0xFF, 0x0F, 0x02, 0x01, 0x00, 0x06,\n                0x05, 0x04, 0x06, 0x04, 0x08, 0x0F,/*闳4828*/},\n        {\n\n                0xF9, 0x02, 0x10, 0x51, 0x95, 0x19, 0xF1, 0x11, 0x11, 0x01, 0xFF, 0x0F, 0x00, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x00, 0x08, 0x0F,/*闵4829*/},\n        {\n\n                0xF9, 0x02, 0x10, 0xD1, 0x55, 0x59, 0xD1, 0x11, 0x11, 0x01, 0xFF, 0x0F, 0x04, 0x02, 0x01, 0x00,\n                0x00, 0x03, 0x04, 0x06, 0x08, 0x0F,/*闶4830*/},\n        {\n\n                0xF9, 0x02, 0x28, 0xE1, 0x11, 0x91, 0x7D, 0x91, 0x11, 0x01, 0xFF, 0x0F, 0x00, 0x04, 0x03, 0x05,\n                0x04, 0x04, 0x04, 0x05, 0x08, 0x0F,/*闼4831*/},\n        {\n\n                0xF9, 0x02, 0x80, 0xBD, 0xA5, 0xA5, 0xA5, 0xBD, 0x81, 0x01, 0xFF, 0x0F, 0x00, 0x07, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x07, 0x08, 0x0F,/*闾4832*/},\n        {\n\n                0xF9, 0x02, 0xFC, 0x25, 0xA5, 0xFD, 0xA5, 0x25, 0xFD, 0x01, 0xFF, 0x0F, 0x00, 0x07, 0x05, 0x04,\n                0x07, 0x04, 0x05, 0x07, 0x08, 0x0F,/*阃4833*/},\n        {\n\n                0xF9, 0x02, 0x10, 0xF9, 0x57, 0xF5, 0x5D, 0xF1, 0x01, 0x01, 0xFF, 0x0F, 0x00, 0x00, 0x01, 0x01,\n                0x03, 0x05, 0x05, 0x06, 0x08, 0x0F,/*阄4834*/},\n        {\n\n                0xF9, 0x02, 0xF8, 0xA9, 0xAB, 0xAD, 0xA9, 0xA9, 0xF9, 0x01, 0xFF, 0x0F, 0x00, 0x0F, 0x04, 0x00,\n                0x01, 0x02, 0x04, 0x0A, 0x09, 0x0F,/*阆4835*/},\n        {\n\n                0xF9, 0x02, 0xE8, 0x29, 0xE9, 0x09, 0xFF, 0x09, 0xCB, 0x01, 0xFF, 0x0F, 0x00, 0x05, 0x05, 0x0B,\n                0x04, 0x03, 0x05, 0x0E, 0x08, 0x0F,/*阈4836*/},\n        {\n\n                0xF9, 0x02, 0xC0, 0x7D, 0x55, 0x55, 0x55, 0x7D, 0xC1, 0x01, 0xFF, 0x0F, 0x00, 0x07, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x07, 0x08, 0x0F,/*阊4837*/},\n        {\n\n                0xF9, 0x02, 0x7C, 0xD5, 0x43, 0xC1, 0x55, 0x7D, 0x01, 0x01, 0xFF, 0x0F, 0x04, 0x02, 0x01, 0x00,\n                0x03, 0x04, 0x04, 0x07, 0x08, 0x0F,/*阋4838*/},\n        {\n\n                0xF9, 0x02, 0x68, 0xB9, 0xA9, 0xB9, 0xA9, 0xB5, 0x65, 0x01, 0xFF, 0x0F, 0x00, 0x04, 0x05, 0x02,\n                0x02, 0x02, 0x05, 0x04, 0x08, 0x0F,/*阌4839*/},\n        {\n\n                0xF9, 0x02, 0x7C, 0xD5, 0x95, 0x9D, 0xB5, 0xD5, 0x93, 0xC1, 0xFF, 0x0F, 0x00, 0x00, 0x0F, 0x0A,\n                0x0A, 0x0A, 0x0F, 0x00, 0x08, 0x0F,/*阍4840*/},\n        {\n\n                0xF9, 0x12, 0xF4, 0x59, 0xD1, 0x21, 0x11, 0x4D, 0x91, 0x21, 0xFF, 0x0F, 0x08, 0x07, 0x08, 0x0F,\n                0x00, 0x02, 0x04, 0x09, 0x08, 0x0F,/*阏4841*/},\n        {\n\n                0xF9, 0x02, 0x00, 0x7F, 0x55, 0xD5, 0x55, 0x7F, 0x01, 0x01, 0xFF, 0x0F, 0x00, 0x0A, 0x0A, 0x06,\n                0x03, 0x06, 0x0B, 0x02, 0x08, 0x0F,/*阒4842*/},\n        {\n\n                0xF9, 0x02, 0x94, 0x65, 0x9D, 0x81, 0x9F, 0x65, 0x93, 0x01, 0xFF, 0x0F, 0x00, 0x02, 0x0A, 0x06,\n                0x03, 0x06, 0x0A, 0x02, 0x08, 0x0F,/*阕4843*/},\n        {\n\n                0xF9, 0x02, 0x54, 0x75, 0x55, 0x5F, 0x55, 0x75, 0x55, 0x11, 0xFF, 0x0F, 0x04, 0x07, 0x05, 0x07,\n                0x05, 0x07, 0x05, 0x07, 0x0C, 0x0F,/*阖4844*/},\n        {\n\n                0xF9, 0x02, 0x00, 0xF5, 0x15, 0xDF, 0x15, 0xF5, 0x01, 0x01, 0xFF, 0x0F, 0x00, 0x01, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x01, 0x08, 0x0F,/*阗4845*/},\n        {\n\n                0xF9, 0xA2, 0x28, 0xF1, 0x29, 0xA1, 0x1D, 0xD1, 0x31, 0x01, 0xFF, 0x0F, 0x01, 0x09, 0x07, 0x01,\n                0x09, 0x04, 0x03, 0x04, 0x08, 0x0F,/*阙4846*/},\n        {\n\n                0xF9, 0x12, 0xF4, 0x5D, 0xF1, 0x11, 0xEF, 0x09, 0xF9, 0x09, 0xFF, 0x0F, 0x04, 0x07, 0x05, 0x0F,\n                0x0A, 0x05, 0x02, 0x05, 0x08, 0x0F,/*阚4847*/},\n        {\n\n                0x04, 0x88, 0x50, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*丬4848*/},\n        {\n\n                0x00, 0x40, 0x40, 0xCF, 0x48, 0x48, 0x48, 0x48, 0x48, 0xFF, 0x00, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x0F, 0x00,/*爿4849*/},\n        {\n\n                0x40, 0xDE, 0x50, 0xFF, 0x10, 0x10, 0xFF, 0x08, 0x89, 0x6A, 0x08, 0x08, 0x07, 0x00, 0x0F, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x0F,/*戕4850*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*氵4851*/},\n        {\n\n                0x10, 0x22, 0x04, 0x10, 0x28, 0x27, 0x24, 0xA4, 0xA4, 0x64, 0x04, 0x04, 0x02, 0x01, 0x00, 0x06,\n                0x09, 0x09, 0x08, 0x08, 0x08, 0x0E,/*汔4852*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x42, 0x42, 0x42, 0x42, 0x42, 0x7E, 0x00, 0x04, 0x02, 0x00, 0x07, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x0E,/*汜4853*/},\n        {\n\n                0x22, 0x44, 0x00, 0x02, 0x3E, 0xC2, 0x0A, 0x92, 0x62, 0x1E, 0x00, 0x04, 0x02, 0x09, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*汊4854*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x04, 0x24, 0x24, 0xFF, 0x24, 0x24, 0x04, 0x04, 0x02, 0x01, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*沣4855*/},\n        {\n\n                0x10, 0x22, 0x04, 0x10, 0x12, 0xF2, 0x12, 0x12, 0xF2, 0x12, 0x10, 0x04, 0x02, 0x01, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x07, 0x08, 0x0E,/*沅4856*/},\n        {\n\n                0x22, 0x44, 0x00, 0x08, 0x88, 0x68, 0xFF, 0x68, 0x88, 0x08, 0x00, 0x04, 0x02, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x01, 0x02, 0x04,/*沐4857*/},\n        {\n\n                0x11, 0x22, 0x00, 0xF2, 0x82, 0x82, 0xFE, 0x92, 0x92, 0xF2, 0x02, 0x04, 0x02, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x08, 0x07, 0x00,/*沔4858*/},\n        {\n\n                0x11, 0x22, 0x04, 0xF4, 0x84, 0x84, 0xFF, 0x84, 0x84, 0xF4, 0x04, 0x04, 0x02, 0x00, 0x00, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*沌4859*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0xFE, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*汨4860*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xFE, 0x22, 0x22, 0x22, 0x22, 0x02, 0xFE, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*汩4861*/},\n        {\n\n                0x10, 0x21, 0x02, 0x08, 0x08, 0x08, 0xF9, 0x2A, 0x48, 0x88, 0x08, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x00, 0x0F, 0x00, 0x00, 0x00, 0x00,/*汴4862*/},\n        {\n\n                0x22, 0x44, 0x00, 0x04, 0x3C, 0xC5, 0x06, 0xC4, 0x3C, 0x04, 0x04, 0x04, 0x02, 0x01, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*汶4863*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x04, 0xE4, 0x25, 0x26, 0xE4, 0x04, 0x04, 0x04, 0x02, 0x01, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*沆4864*/},\n        {\n\n                0x11, 0x22, 0x00, 0x0A, 0x0C, 0xE8, 0x1F, 0x48, 0x88, 0x08, 0xF8, 0x04, 0x02, 0x08, 0x04, 0x03,\n                0x00, 0x00, 0x08, 0x09, 0x08, 0x07,/*沩4865*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x12, 0xEE, 0x08, 0x08, 0xFF, 0x08, 0xF8, 0x04, 0x02, 0x00, 0x0F, 0x01,\n                0x08, 0x04, 0x03, 0x08, 0x08, 0x07,/*泐4866*/},\n        {\n\n                0x22, 0x44, 0x00, 0x04, 0xFF, 0x44, 0x44, 0x44, 0x44, 0xFF, 0x04, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*泔4867*/},\n        {\n\n                0x11, 0x22, 0x00, 0x08, 0x88, 0x68, 0xFF, 0x68, 0x89, 0x0A, 0x08, 0x04, 0x02, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x01, 0x02, 0x04,/*沭4868*/},\n        {\n\n                0x10, 0x21, 0x02, 0x08, 0x08, 0xFF, 0x08, 0xF8, 0x89, 0x4A, 0x28, 0x04, 0x02, 0x09, 0x04, 0x03,\n                0x04, 0x02, 0x07, 0x08, 0x08, 0x0E,/*泷4869*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xF0, 0x90, 0x90, 0x9F, 0x92, 0x92, 0xF2, 0x04, 0x02, 0x01, 0x08, 0x07,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x01,/*泸4870*/},\n        {\n\n                0x22, 0x44, 0x80, 0xFC, 0x84, 0x84, 0xFF, 0x84, 0x84, 0xFC, 0x80, 0x04, 0x02, 0x08, 0x04, 0x02,\n                0x01, 0x00, 0x01, 0x02, 0x04, 0x08,/*泱4871*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0x02, 0xFE, 0x82, 0xFE, 0x04, 0x02, 0x00, 0x0F, 0x05,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*泗4872*/},\n        {\n\n                0x22, 0x44, 0x00, 0x48, 0xF4, 0x47, 0xFC, 0x24, 0x14, 0xF4, 0x04, 0x04, 0x02, 0x01, 0x00, 0x07,\n                0x08, 0x0B, 0x08, 0x09, 0x09, 0x0C,/*沲4873*/},\n        {\n\n                0x10, 0x22, 0x04, 0x10, 0x48, 0x44, 0x53, 0x64, 0x48, 0xD0, 0x10, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x02, 0x04, 0x0A, 0x01, 0x00, 0x00,/*泠4874*/},\n        {\n\n                0x22, 0x44, 0xFE, 0x02, 0x82, 0xFD, 0x00, 0xFE, 0x02, 0x02, 0xFE, 0x04, 0x02, 0x01, 0x09, 0x04,\n                0x03, 0x00, 0x0F, 0x00, 0x01, 0x01,/*泖4875*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xBE, 0x22, 0x22, 0xFA, 0x21, 0xA1, 0x20, 0x04, 0x02, 0x01, 0x02, 0x01,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x03,/*泺4876*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x44, 0x64, 0x55, 0xCE, 0x44, 0x24, 0x04, 0x04, 0x02, 0x01, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*泫4877*/},\n        {\n\n                0x11, 0x22, 0x80, 0x92, 0x94, 0x90, 0xFF, 0x90, 0x94, 0x92, 0x80, 0x04, 0x02, 0x00, 0x00, 0x00,\n                0x00, 0x0F, 0x00, 0x00, 0x00, 0x00,/*泮4878*/},\n        {\n\n                0x22, 0x44, 0x00, 0x0C, 0xE4, 0x04, 0x05, 0x86, 0x84, 0x44, 0x0C, 0x04, 0x02, 0x01, 0x00, 0x07,\n                0x09, 0x09, 0x08, 0x08, 0x08, 0x0E,/*沱4879*/},\n        {\n\n                0x11, 0x22, 0x00, 0x79, 0x49, 0xCF, 0x00, 0xE0, 0x1F, 0x00, 0x00, 0x04, 0x02, 0x00, 0x08, 0x08,\n                0x07, 0x00, 0x07, 0x04, 0x05, 0x0E,/*泓4880*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFF, 0x49, 0x49, 0x49, 0xF9, 0x49, 0x4F, 0x40, 0x04, 0x02, 0x00, 0x0F, 0x04,\n                0x02, 0x00, 0x01, 0x02, 0x04, 0x0E,/*泯4881*/},\n        {\n\n                0x22, 0x44, 0x00, 0xA2, 0xA2, 0x92, 0x92, 0x8A, 0x96, 0x92, 0x20, 0x04, 0x02, 0x08, 0x08, 0x08,\n                0x08, 0x0F, 0x08, 0x08, 0x08, 0x08,/*泾4882*/},\n        {\n\n                0x10, 0x22, 0x04, 0x02, 0xFA, 0x4A, 0x4A, 0x4A, 0x4A, 0xFA, 0x02, 0x04, 0x02, 0x01, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*洹4883*/},\n        {\n\n                0x11, 0x22, 0x40, 0x24, 0xF4, 0x5C, 0x57, 0x54, 0x54, 0xF4, 0x04, 0x04, 0x02, 0x00, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x09, 0x0F, 0x00,/*洧4884*/},\n        {\n\n                0x22, 0x44, 0x82, 0x62, 0x9E, 0x12, 0xF2, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x09, 0x08, 0x0F,/*洌4885*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x94, 0xA4, 0x84, 0xFF, 0x84, 0xA4, 0x94, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*浃4886*/},\n        {\n\n                0x22, 0x44, 0x00, 0xF0, 0x10, 0x10, 0xDF, 0x14, 0x14, 0xF4, 0x04, 0x04, 0x02, 0x00, 0x09, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x09, 0x00,/*浈4887*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0xFF, 0x11, 0x91, 0x7D, 0x91, 0x11, 0xFF, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x05, 0x0F,/*洇4888*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFE, 0x02, 0xF2, 0x92, 0x92, 0xF2, 0x02, 0xFE, 0x04, 0x02, 0x00, 0x0F, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*洄4889*/},\n        {\n\n                0x10, 0x21, 0x02, 0x20, 0x28, 0xA6, 0x64, 0xFF, 0xA4, 0x24, 0x20, 0x04, 0x02, 0x01, 0x02, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x01, 0x02,/*洙4890*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0xFC, 0x24, 0x26, 0x25, 0x24, 0x24, 0xFC, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x0F,/*洎4891*/},\n        {\n\n                0x22, 0x44, 0x00, 0xF8, 0x08, 0xFC, 0x0B, 0xF8, 0x08, 0xF8, 0x00, 0x04, 0x02, 0x08, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*洫4892*/},\n        {\n\n                0x11, 0x22, 0x10, 0x88, 0x94, 0x92, 0x91, 0x92, 0x94, 0x88, 0x10, 0x04, 0x02, 0x00, 0x04, 0x06,\n                0x05, 0x04, 0x04, 0x06, 0x0C, 0x00,/*浍4893*/},\n        {\n\n                0x22, 0x44, 0x00, 0x88, 0x50, 0xFF, 0x00, 0x00, 0xFF, 0x50, 0x88, 0x04, 0x02, 0x00, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x07, 0x08, 0x0E,/*洮4894*/},\n        {\n\n                0x11, 0x22, 0x08, 0x04, 0xFB, 0x4A, 0x4A, 0x4A, 0xFA, 0x02, 0xFE, 0x04, 0x02, 0x01, 0x00, 0x07,\n                0x02, 0x02, 0x02, 0x0B, 0x08, 0x07,/*洵4895*/},\n        {\n\n                0x10, 0x21, 0x02, 0x28, 0xA4, 0xAB, 0x92, 0xD2, 0xAA, 0xA6, 0x20, 0x04, 0x02, 0x01, 0x06, 0x04,\n                0x04, 0x04, 0x0F, 0x04, 0x04, 0x04,/*洚4896*/},\n        {\n\n                0x11, 0x22, 0x00, 0x28, 0xC9, 0x0A, 0xF8, 0x08, 0xFC, 0x00, 0xFF, 0x04, 0x02, 0x01, 0x08, 0x06,\n                0x01, 0x06, 0x00, 0x01, 0x08, 0x0F,/*浏4897*/},\n        {\n\n                0x22, 0x44, 0x11, 0xF2, 0x00, 0x88, 0x87, 0xFC, 0x84, 0x84, 0x80, 0x04, 0x02, 0x00, 0x07, 0x02,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*浒4898*/},\n        {\n\n                0x11, 0x22, 0x80, 0xA2, 0xAA, 0xAA, 0xAA, 0xAA, 0xEA, 0xBE, 0x80, 0x04, 0x02, 0x00, 0x00, 0x01,\n                0x02, 0x00, 0x08, 0x0F, 0x00, 0x00,/*浔4899*/},\n        {\n\n                0x11, 0x22, 0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFC, 0x04, 0x04, 0xFC, 0x04, 0x02, 0x08, 0x05, 0x02,\n                0x05, 0x08, 0x07, 0x02, 0x02, 0x07,/*洳4900*/},\n        {\n\n                0x22, 0x44, 0x00, 0xF4, 0x94, 0x94, 0xFF, 0x94, 0x94, 0xF4, 0x04, 0x04, 0x02, 0x00, 0x04, 0x02,\n                0x01, 0x0F, 0x01, 0x02, 0x04, 0x04,/*涑4901*/},\n        {\n\n                0x11, 0x22, 0x00, 0x21, 0xA5, 0xBD, 0xA7, 0xA5, 0xA5, 0xBD, 0x21, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*浯4902*/},\n        {\n\n                0x11, 0x22, 0x40, 0x54, 0x64, 0xC4, 0xFF, 0xC4, 0x64, 0x54, 0x40, 0x04, 0x02, 0x04, 0x02, 0x01,\n                0x00, 0x0F, 0x00, 0x01, 0x02, 0x04,/*涞4903*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFF, 0x45, 0x55, 0xFF, 0x55, 0xC5, 0x01, 0xFF, 0x04, 0x02, 0x00, 0x0F, 0x04,\n                0x04, 0x07, 0x05, 0x05, 0x04, 0x0F,/*涠4904*/},\n        {\n\n                0x22, 0x44, 0x00, 0x1F, 0x91, 0x11, 0xF1, 0x91, 0x91, 0x9F, 0x00, 0x04, 0x02, 0x09, 0x04, 0x03,\n                0x04, 0x0F, 0x08, 0x08, 0x08, 0x08,/*浞4905*/},\n        {\n\n                0x11, 0x22, 0x00, 0xF0, 0x57, 0x55, 0x55, 0x55, 0x55, 0x57, 0xF0, 0x04, 0x02, 0x00, 0x0F, 0x01,\n                0x01, 0x01, 0x01, 0x01, 0x09, 0x0F,/*涓4906*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0x46, 0x24, 0x14, 0x4F, 0x94, 0x24, 0x46, 0x04, 0x02, 0x01, 0x00, 0x00,\n                0x01, 0x01, 0x09, 0x05, 0x03, 0x00,/*涔4907*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0xFE, 0x12, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x04, 0x02, 0x01, 0x09, 0x05,\n                0x01, 0x01, 0x01, 0x01, 0x05, 0x09,/*浜4908*/},\n        {\n\n                0x11, 0x22, 0x00, 0x90, 0xD5, 0xB2, 0x9A, 0xD2, 0x92, 0x95, 0x90, 0x04, 0x02, 0x00, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*浠4909*/},\n        {\n\n                0x22, 0x44, 0x08, 0xF4, 0x93, 0x92, 0xF2, 0x9A, 0x96, 0xF0, 0x00, 0x04, 0x02, 0x08, 0x08, 0x04,\n                0x03, 0x00, 0x07, 0x08, 0x08, 0x0C,/*浼4910*/},\n        {\n\n                0x11, 0x22, 0x4C, 0x44, 0xD4, 0x55, 0x56, 0xD4, 0x54, 0x44, 0x4C, 0x04, 0x02, 0x08, 0x04, 0x03,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*浣4911*/},\n        {\n\n                0x22, 0x44, 0x90, 0x94, 0xD4, 0x74, 0x5F, 0x54, 0x5C, 0x54, 0xD2, 0x04, 0x02, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*渚4912*/},\n        {\n\n                0x11, 0x22, 0x04, 0x04, 0xFF, 0x54, 0x54, 0x54, 0x54, 0xFF, 0x04, 0x04, 0x02, 0x01, 0x09, 0x05,\n                0x01, 0x01, 0x01, 0x01, 0x05, 0x09,/*淇4913*/},\n        {\n\n                0x11, 0x22, 0x88, 0x68, 0xFF, 0x48, 0x88, 0xFE, 0x12, 0xF1, 0x11, 0x04, 0x02, 0x00, 0x00, 0x0F,\n                0x08, 0x04, 0x03, 0x00, 0x0F, 0x00,/*淅4914*/},\n        {\n\n                0x11, 0x22, 0x88, 0x48, 0xFF, 0x28, 0x58, 0x87, 0x60, 0x07, 0x18, 0x04, 0x02, 0x00, 0x00, 0x0F,\n                0x00, 0x06, 0x05, 0x04, 0x05, 0x0E,/*淞4915*/},\n        {\n\n                0x11, 0x22, 0x00, 0x48, 0x8A, 0x2A, 0x4F, 0xEA, 0x0A, 0x0A, 0x18, 0x04, 0x02, 0x00, 0x09, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*渎4916*/},\n        {\n\n                0x11, 0x22, 0x00, 0x92, 0x6A, 0xA6, 0x9A, 0xF2, 0xA2, 0x12, 0x0A, 0x04, 0x02, 0x00, 0x04, 0x02,\n                0x09, 0x08, 0x07, 0x00, 0x01, 0x02,/*涿4917*/},\n        {\n\n                0x11, 0x22, 0x00, 0x7F, 0x49, 0x49, 0x7F, 0x49, 0x49, 0x7F, 0x00, 0x04, 0x02, 0x01, 0x09, 0x07,\n                0x01, 0x01, 0x01, 0x0F, 0x01, 0x01,/*淠4918*/},\n        {\n\n                0x11, 0x22, 0x00, 0xF0, 0x57, 0x55, 0xFD, 0x55, 0x57, 0xF0, 0x00, 0x04, 0x02, 0x00, 0x03, 0x01,\n                0x01, 0x07, 0x09, 0x09, 0x09, 0x0C,/*渑4919*/},\n        {\n\n                0x22, 0x44, 0x10, 0x88, 0x94, 0x92, 0xF1, 0x92, 0x94, 0x88, 0x10, 0x04, 0x02, 0x08, 0x0A, 0x0C,\n                0x08, 0x0F, 0x08, 0x0C, 0x0A, 0x08,/*淦4920*/},\n        {\n\n                0x22, 0x44, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x42, 0x7E, 0x42, 0x7E, 0x04, 0x0A, 0x07, 0x08, 0x0F,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*淝4921*/},\n        {\n\n                0x10, 0x22, 0x04, 0x00, 0x86, 0x92, 0x92, 0x93, 0x92, 0x92, 0x86, 0x04, 0x02, 0x01, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*淙4922*/},\n        {\n\n                0x11, 0x22, 0x0C, 0xE4, 0xA4, 0xA5, 0xF6, 0xA4, 0xA4, 0xE4, 0x0C, 0x04, 0x02, 0x00, 0x07, 0x02,\n                0x02, 0x0F, 0x02, 0x02, 0x07, 0x00,/*渖4923*/},\n        {\n\n                0x22, 0x44, 0x00, 0x0C, 0xF4, 0x54, 0x55, 0x56, 0x54, 0x74, 0x0C, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*涫4924*/},\n        {\n\n                0x10, 0x21, 0x02, 0x50, 0x95, 0x15, 0xF5, 0x15, 0x9F, 0x50, 0x00, 0x04, 0x02, 0x01, 0x04, 0x02,\n                0x09, 0x0F, 0x01, 0x02, 0x04, 0x04,/*渌4925*/},\n        {\n\n                0x22, 0x44, 0xFF, 0x29, 0xF9, 0x29, 0xEF, 0x00, 0xFC, 0x00, 0xFF, 0x04, 0x0A, 0x07, 0x00, 0x0F,\n                0x02, 0x03, 0x00, 0x09, 0x08, 0x0F,/*涮4926*/},\n        {\n\n                0x22, 0x44, 0x00, 0x04, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x04, 0x04, 0x02, 0x01, 0x09, 0x05,\n                0x03, 0x0F, 0x03, 0x05, 0x09, 0x09,/*渫4927*/},\n        {\n\n                0x11, 0x22, 0x00, 0x7A, 0x4A, 0x7E, 0xCA, 0x7E, 0x4A, 0x7A, 0x00, 0x04, 0x02, 0x08, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x08,/*湮4928*/},\n        {\n\n                0x11, 0x22, 0x00, 0xF9, 0x09, 0xF9, 0xAD, 0xAB, 0xF9, 0x09, 0xF9, 0x04, 0x02, 0x00, 0x0F, 0x04,\n                0x07, 0x04, 0x04, 0x07, 0x04, 0x0F,/*湎4929*/},\n        {\n\n                0x11, 0x22, 0x10, 0xD2, 0xFE, 0x52, 0x91, 0x08, 0xFF, 0x10, 0x0C, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x00, 0x08, 0x06, 0x01, 0x06, 0x08,/*湫4930*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0xBC, 0xAA, 0xA0, 0xFF, 0xA0, 0xAA, 0xBE, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x09, 0x0A, 0x04, 0x04, 0x0A, 0x09,/*溲4931*/},\n        {\n\n                0x22, 0x44, 0x00, 0xBE, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xBE, 0x00, 0x04, 0x02, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*湟4932*/},\n        {\n\n                0x22, 0x44, 0x44, 0x4A, 0xF9, 0x4A, 0x44, 0xFE, 0x02, 0xFE, 0x00, 0x04, 0x02, 0x02, 0x09, 0x0F,\n                0x01, 0x0A, 0x04, 0x03, 0x04, 0x08,/*溆4933*/},\n        {\n\n                0x11, 0x22, 0x00, 0x44, 0x2A, 0x19, 0x08, 0x48, 0x49, 0x3A, 0x04, 0x04, 0x02, 0x08, 0x0F, 0x09,\n                0x0F, 0x09, 0x0F, 0x09, 0x0F, 0x08,/*湓4934*/},\n        {\n\n                0x22, 0x44, 0x00, 0xF4, 0x55, 0x56, 0xF4, 0x04, 0xE6, 0x05, 0xF4, 0x04, 0x02, 0x00, 0x0F, 0x01,\n                0x09, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*湔4935*/},\n        {\n\n                0x22, 0x44, 0x00, 0x06, 0xEA, 0xAA, 0xAB, 0xAA, 0xAA, 0xEA, 0x06, 0x04, 0x02, 0x00, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*渲4936*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFF, 0x05, 0x95, 0xD5, 0xB5, 0x95, 0xD5, 0x97, 0x04, 0x02, 0x08, 0x07, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*渥4937*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFF, 0x09, 0xE9, 0xA9, 0xAF, 0xA9, 0xA9, 0xEF, 0x04, 0x02, 0x08, 0x07, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x0F,/*湄4938*/},\n        {\n\n                0x22, 0x44, 0x24, 0x24, 0xFF, 0x24, 0xF4, 0x93, 0xFA, 0x96, 0xF0, 0x04, 0x02, 0x01, 0x01, 0x0F,\n                0x01, 0x07, 0x08, 0x08, 0x08, 0x0E,/*滟4939*/},\n        {\n\n                0x22, 0x44, 0x00, 0xA2, 0x6A, 0xBA, 0xAF, 0xAA, 0x6A, 0xA2, 0x20, 0x04, 0x02, 0x00, 0x0A, 0x06,\n                0x02, 0x0F, 0x02, 0x06, 0x0A, 0x01,/*溱4940*/},\n        {\n\n                0x22, 0x44, 0x00, 0x48, 0x6A, 0x5A, 0x4F, 0x4A, 0x6A, 0x48, 0x08, 0x04, 0x02, 0x08, 0x0F, 0x09,\n                0x0F, 0x09, 0x0F, 0x09, 0x0F, 0x08,/*溘4941*/},\n        {\n\n                0x11, 0x22, 0x41, 0x7F, 0x55, 0x55, 0x55, 0x55, 0x55, 0xFF, 0x21, 0x04, 0x02, 0x0B, 0x05, 0x05,\n                0x0B, 0x00, 0x0B, 0x05, 0x05, 0x0B,/*滠4942*/},\n        {\n\n                0x22, 0x44, 0x00, 0x52, 0x52, 0xB7, 0x1A, 0x12, 0xB7, 0x5A, 0x52, 0x04, 0x02, 0x00, 0x01, 0x09,\n                0x07, 0x01, 0x01, 0x0F, 0x01, 0x01,/*漭4943*/},\n        {\n\n                0x22, 0x44, 0x1A, 0x2A, 0x2F, 0x2A, 0xEA, 0x2A, 0x2F, 0x2A, 0x1A, 0x04, 0x02, 0x08, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x0B, 0x0D, 0x08,/*滢4944*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFA, 0x2A, 0x2A, 0xFF, 0x2A, 0x2B, 0xFA, 0x02, 0x04, 0x02, 0x00, 0x02, 0x06,\n                0x0A, 0x02, 0x0A, 0x0F, 0x02, 0x02,/*溥4945*/},\n        {\n\n                0x11, 0x22, 0x81, 0xBD, 0xA5, 0xBF, 0xE5, 0xBF, 0xA5, 0xBD, 0x81, 0x04, 0x02, 0x04, 0x04, 0x02,\n                0x01, 0x0F, 0x01, 0x02, 0x04, 0x04,/*溧4946*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFF, 0x11, 0xF5, 0x95, 0x35, 0x55, 0xB5, 0x91, 0x04, 0x02, 0x08, 0x07, 0x02,\n                0x06, 0x02, 0x0A, 0x0F, 0x02, 0x02,/*溽4947*/},\n        {\n\n                0x11, 0x22, 0x40, 0xC0, 0x5F, 0xD5, 0x15, 0x55, 0xD5, 0x5F, 0xC0, 0x04, 0x02, 0x04, 0x02, 0x09,\n                0x0F, 0x00, 0x04, 0x02, 0x09, 0x0F,/*溻4948*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFF, 0xA5, 0x55, 0xAD, 0xF5, 0xA5, 0x15, 0xFF, 0x04, 0x02, 0x00, 0x0F, 0x0A,\n                0x09, 0x0A, 0x0B, 0x08, 0x09, 0x0F,/*溷4949*/},\n        {\n\n                0x11, 0x22, 0x04, 0x23, 0xA6, 0xAA, 0xE2, 0x54, 0x53, 0x16, 0x0A, 0x04, 0x02, 0x00, 0x02, 0x02,\n                0x02, 0x07, 0x09, 0x09, 0x09, 0x0C,/*滗4950*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xFE, 0x00, 0x04, 0x02, 0x0A, 0x0A, 0x0A,\n                0x06, 0x03, 0x06, 0x0B, 0x0A, 0x0A,/*溴4951*/},\n        {\n\n                0x22, 0x44, 0x20, 0x22, 0x51, 0x54, 0xC8, 0x54, 0x51, 0x22, 0x20, 0x04, 0x02, 0x08, 0x09, 0x0D,\n                0x09, 0x0F, 0x09, 0x0D, 0x09, 0x08,/*滏4952*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x22, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x04, 0x02, 0x08, 0x07, 0x00,\n                0x0E, 0x0A, 0x0B, 0x0A, 0x0E, 0x00,/*溏4953*/},\n        {\n\n                0x22, 0x44, 0x00, 0xB2, 0x96, 0x9A, 0xB3, 0xD2, 0x9A, 0x96, 0xB2, 0x04, 0x02, 0x00, 0x08, 0x04,\n                0x03, 0x02, 0x02, 0x0A, 0x0A, 0x06,/*滂4954*/},\n        {\n\n                0x22, 0x44, 0x03, 0x7D, 0x55, 0x55, 0xD5, 0x55, 0x55, 0x7D, 0x03, 0x04, 0x02, 0x01, 0x09, 0x05,\n                0x01, 0x01, 0x01, 0x05, 0x09, 0x01,/*溟4955*/},\n        {\n\n                0x11, 0x22, 0x08, 0xEA, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xEA, 0x08, 0x04, 0x02, 0x00, 0x0B, 0x06,\n                0x02, 0x03, 0x02, 0x06, 0x0B, 0x00,/*潢4956*/},\n        {\n\n                0x22, 0x44, 0x00, 0x1A, 0x4A, 0x6F, 0xDA, 0x4A, 0x2F, 0x8A, 0x1A, 0x04, 0x02, 0x01, 0x08, 0x05,\n                0x01, 0x09, 0x0F, 0x01, 0x05, 0x09,/*潆4957*/},\n        {\n\n                0x22, 0x44, 0x22, 0xAA, 0xAF, 0xAA, 0xFE, 0xAA, 0xAF, 0xFA, 0x22, 0x04, 0x02, 0x08, 0x06, 0x04,\n                0x02, 0x0F, 0x02, 0x04, 0x0E, 0x00,/*潇4958*/},\n        {\n\n                0x22, 0x44, 0x12, 0x8A, 0xBF, 0x8A, 0xD0, 0x8A, 0xBF, 0x8A, 0x92, 0x04, 0x02, 0x00, 0x08, 0x0A,\n                0x0B, 0x04, 0x04, 0x0B, 0x08, 0x00,/*漤4959*/},\n        {\n\n                0x22, 0x44, 0x02, 0xFA, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFA, 0x02, 0x04, 0x02, 0x00, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*漕4960*/},\n        {\n\n                0x11, 0x22, 0x00, 0xFC, 0x94, 0x94, 0xBF, 0xD5, 0x55, 0x45, 0x6C, 0x04, 0x02, 0x08, 0x07, 0x02,\n                0x03, 0x0A, 0x0F, 0x02, 0x03, 0x02,/*滹4961*/},\n        {\n\n                0x10, 0x21, 0x02, 0x00, 0x5F, 0x75, 0xD5, 0x5F, 0x35, 0x95, 0x1F, 0x04, 0x02, 0x01, 0x08, 0x05,\n                0x01, 0x09, 0x0F, 0x01, 0x05, 0x09,/*漯4962*/},\n        {\n\n                0x22, 0x44, 0x00, 0xEE, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xEE, 0x00, 0x04, 0x02, 0x08, 0x06, 0x00,\n                0x06, 0x09, 0x0A, 0x0C, 0x02, 0x0C,/*漶4963*/},\n        {\n\n                0x11, 0x22, 0x88, 0x14, 0x53, 0x94, 0x68, 0xD0, 0x0F, 0xF8, 0x08, 0x04, 0x02, 0x04, 0x05, 0x04,\n                0x02, 0x0A, 0x05, 0x02, 0x05, 0x08,/*潋4964*/},\n        {\n\n                0x22, 0x44, 0x8A, 0x44, 0xFB, 0x90, 0xD4, 0x7F, 0x54, 0xD8, 0x14, 0x04, 0x02, 0x08, 0x08, 0x07,\n                0x00, 0x0F, 0x05, 0x05, 0x0F, 0x00,/*潴4965*/},\n        {\n\n                0x22, 0x44, 0x8A, 0x44, 0xFB, 0x10, 0xDA, 0x56, 0xD3, 0x16, 0xFA, 0x04, 0x02, 0x08, 0x08, 0x07,\n                0x00, 0x07, 0x02, 0x03, 0x08, 0x0F,/*漪4966*/},\n        {\n\n                0x22, 0x44, 0x00, 0xFE, 0x2A, 0xAA, 0x3E, 0x2B, 0xBE, 0x2A, 0xBA, 0x04, 0x02, 0x08, 0x07, 0x00,\n                0x0F, 0x09, 0x00, 0x07, 0x09, 0x0C,/*漉4967*/},\n        {\n\n                0x22, 0x44, 0xFD, 0x26, 0xE4, 0x08, 0xD7, 0x14, 0xF4, 0x14, 0x34, 0x04, 0x0A, 0x07, 0x08, 0x0F,\n                0x08, 0x07, 0x08, 0x0F, 0x09, 0x09,/*漩4968*/},\n        {\n\n                0x11, 0x22, 0x08, 0xF9, 0xAD, 0xFB, 0x10, 0xEC, 0x0B, 0xF8, 0x08, 0x04, 0x02, 0x02, 0x03, 0x02,\n                0x0F, 0x09, 0x04, 0x03, 0x04, 0x08,/*澉4969*/},\n        {\n\n                0x22, 0x44, 0x02, 0xEA, 0xAF, 0xEA, 0x02, 0x48, 0x88, 0xFF, 0x08, 0x04, 0x02, 0x08, 0x0A, 0x04,\n                0x06, 0x04, 0x00, 0x08, 0x0F, 0x00,/*澍4970*/},\n        {\n\n                0x11, 0x22, 0x04, 0xFF, 0x54, 0xFF, 0x04, 0xFE, 0x12, 0xF2, 0x11, 0x04, 0x02, 0x09, 0x05, 0x01,\n                0x05, 0x09, 0x07, 0x00, 0x0F, 0x00,/*澌4971*/},\n        {\n\n                0x22, 0x44, 0x12, 0xEA, 0xBF, 0xAA, 0xB0, 0xAA, 0xBF, 0xEA, 0x12, 0x04, 0x02, 0x00, 0x0F, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*潸4972*/},\n        {\n\n                0x22, 0x44, 0x12, 0xD2, 0xFE, 0x91, 0xF2, 0x54, 0x5F, 0x54, 0xF2, 0x04, 0x02, 0x01, 0x00, 0x0F,\n                0x00, 0x0F, 0x01, 0x01, 0x09, 0x0F,/*潲4973*/},\n        {\n\n                0x11, 0x22, 0x08, 0xFA, 0xAE, 0xAA, 0xFB, 0xAA, 0xAE, 0xFA, 0x08, 0x04, 0x02, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*潼4974*/},\n        {\n\n                0x22, 0x44, 0xFF, 0x05, 0x45, 0x55, 0xD5, 0x3D, 0x55, 0x55, 0xC7, 0x04, 0x0A, 0x07, 0x00, 0x0A,\n                0x0F, 0x02, 0x00, 0x0A, 0x0F, 0x02,/*潺4975*/},\n        {\n\n                0x22, 0x44, 0xF4, 0x94, 0xFF, 0x94, 0xF4, 0x04, 0xF3, 0x1A, 0xF6, 0x04, 0x02, 0x04, 0x02, 0x0F,\n                0x02, 0x04, 0x08, 0x05, 0x02, 0x0D,/*濑4976*/},\n        {\n\n                0x22, 0x44, 0xFE, 0x92, 0xFE, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x00, 0x04, 0x02, 0x0F, 0x04, 0x0F,\n                0x00, 0x0F, 0x09, 0x0F, 0x09, 0x00,/*濉4977*/},\n        {\n\n                0x22, 0x44, 0x20, 0xBE, 0xAA, 0xBF, 0xAA, 0xBF, 0xAA, 0xBE, 0x20, 0x04, 0x02, 0x08, 0x0B, 0x0E,\n                0x0A, 0x0A, 0x0A, 0x0E, 0x0B, 0x08,/*澧4978*/},\n        {\n\n                0x11, 0x22, 0x08, 0xFC, 0x16, 0xAD, 0xA5, 0xB5, 0xA7, 0xAC, 0x14, 0x04, 0x02, 0x08, 0x07, 0x00,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*澹4979*/},\n        {\n\n                0x22, 0x44, 0x02, 0xFA, 0x8A, 0xBA, 0xAB, 0xBA, 0x8A, 0xFA, 0x02, 0x04, 0x02, 0x08, 0x08, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x08, 0x08,/*澶4980*/},\n        {\n\n                0x22, 0x44, 0xFE, 0x8A, 0xAA, 0xFE, 0xAB, 0xFA, 0xAE, 0xEA, 0x8A, 0x04, 0x0A, 0x07, 0x08, 0x06,\n                0x0F, 0x02, 0x0F, 0x06, 0x0B, 0x00,/*濂4981*/},\n        {\n\n                0x11, 0x22, 0x4C, 0x55, 0x55, 0x45, 0xDF, 0x45, 0x55, 0x55, 0x4C, 0x04, 0x02, 0x0F, 0x01, 0x01,\n                0x07, 0x01, 0x07, 0x01, 0x09, 0x0F,/*濡4982*/},\n        {\n\n                0x22, 0x44, 0x10, 0xFC, 0x03, 0xAA, 0xBF, 0xE8, 0xBF, 0xAA, 0x00, 0x04, 0x02, 0x00, 0x0F, 0x02,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x02,/*濮4983*/},\n        {\n\n                0x22, 0x44, 0x00, 0xE0, 0xBE, 0xAB, 0xEA, 0xAA, 0xBE, 0xE0, 0x00, 0x04, 0x02, 0x02, 0x0B, 0x06,\n                0x02, 0x03, 0x02, 0x0E, 0x03, 0x02,/*濞4984*/},\n        {\n\n                0x11, 0x22, 0x00, 0x62, 0xBA, 0xAA, 0xAB, 0xAA, 0xAA, 0xBA, 0x62, 0x04, 0x02, 0x00, 0x0A, 0x0A,\n                0x05, 0x0B, 0x0E, 0x02, 0x04, 0x0A,/*濠4985*/},\n        {\n\n                0x22, 0x44, 0x20, 0xFB, 0xA5, 0xAF, 0xA0, 0xEB, 0xB5, 0xAF, 0x20, 0x04, 0x02, 0x00, 0x0F, 0x0A,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*濯4986*/},\n        {\n\n                0x22, 0x44, 0xFA, 0xAF, 0xFA, 0x40, 0x94, 0xF2, 0x41, 0x92, 0xF4, 0x04, 0x02, 0x02, 0x0F, 0x02,\n                0x01, 0x08, 0x0F, 0x01, 0x08, 0x0F,/*瀚4987*/},\n        {\n\n                0x22, 0x44, 0x10, 0xD8, 0xAF, 0xDA, 0x00, 0xEE, 0x92, 0xAE, 0x20, 0x04, 0x02, 0x08, 0x0A, 0x0A,\n                0x0F, 0x08, 0x0F, 0x0A, 0x0A, 0x08,/*瀣4988*/},\n        {\n\n                0x22, 0x44, 0x00, 0x42, 0xCE, 0x6A, 0xCB, 0x0A, 0xEA, 0x2A, 0xE2, 0x04, 0x02, 0x01, 0x08, 0x05,\n                0x02, 0x05, 0x08, 0x07, 0x01, 0x0F,/*瀛4989*/},\n        {\n\n                0x11, 0x22, 0x04, 0xBC, 0xAA, 0xBA, 0xA9, 0xBA, 0xAA, 0xBC, 0x04, 0x04, 0x02, 0x00, 0x0F, 0x02,\n                0x07, 0x02, 0x07, 0x0A, 0x0F, 0x00,/*瀹4990*/},\n        {\n\n                0x11, 0x22, 0x94, 0xF5, 0xAE, 0xA4, 0xFF, 0xA4, 0xAE, 0xF5, 0x94, 0x04, 0x02, 0x02, 0x0A, 0x07,\n                0x02, 0x02, 0x02, 0x07, 0x0A, 0x02,/*瀵4991*/},\n        {\n\n                0x11, 0x22, 0x40, 0xDF, 0x75, 0x55, 0xDF, 0x40, 0xFD, 0x0B, 0xF9, 0x04, 0x02, 0x08, 0x05, 0x09,\n                0x0F, 0x01, 0x04, 0x08, 0x06, 0x08,/*灏4992*/},\n        {\n\n                0x11, 0x22, 0x4C, 0xE5, 0x4D, 0xE5, 0x4F, 0x05, 0xED, 0xA5, 0xEC, 0x04, 0x02, 0x04, 0x05, 0x0F,\n                0x05, 0x04, 0x08, 0x07, 0x0A, 0x0F,/*灞4993*/},\n        {\n\n                0x1C, 0x04, 0x04, 0x04, 0x05, 0x06, 0x04, 0x04, 0x04, 0x04, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*宀4994*/},\n        {\n\n                0x0C, 0x24, 0x24, 0x24, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x04, 0x0C, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x00, 0x07, 0x08, 0x0E,/*宄4995*/},\n        {\n\n                0x16, 0x92, 0xD2, 0xB2, 0x92, 0x93, 0x92, 0x92, 0x92, 0x92, 0x16, 0x01, 0x00, 0x0F, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*宕4996*/},\n        {\n\n                0x0C, 0xC4, 0x04, 0xC4, 0x0D, 0x36, 0x84, 0x44, 0x24, 0x84, 0x0C, 0x09, 0x08, 0x04, 0x07, 0x0A,\n                0x09, 0x08, 0x08, 0x0E, 0x00, 0x03,/*宓4997*/},\n        {\n\n                0x86, 0x4A, 0xEA, 0xBA, 0xAA, 0xAF, 0xAA, 0xAA, 0xAA, 0xEA, 0x06, 0x00, 0x00, 0x0F, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*宥4998*/},\n        {\n\n                0x06, 0xFA, 0x8A, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0x8A, 0x06, 0x08, 0x07, 0x00, 0x0F, 0x08,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*宸4999*/},\n        {\n\n                0x16, 0xCA, 0x42, 0x4A, 0x56, 0xDB, 0x52, 0x5A, 0x42, 0xCA, 0x16, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x0D, 0x0F, 0x00,/*甯5000*/},\n        {\n\n                0x26, 0xAA, 0x6A, 0xBE, 0xAA, 0xAB, 0xAA, 0xBE, 0x6A, 0xAA, 0x26, 0x01, 0x08, 0x08, 0x0B, 0x0A,\n                0x0A, 0x02, 0x0B, 0x0A, 0x06, 0x01,/*骞5001*/},\n        {\n\n                0x26, 0xAA, 0xEA, 0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0xEA, 0xAA, 0x26, 0x01, 0x02, 0x02, 0x02, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x01,/*搴5002*/},\n        {\n\n                0x06, 0x72, 0x42, 0xFA, 0x02, 0xAB, 0xEA, 0xBA, 0xAA, 0xEA, 0x86, 0x09, 0x07, 0x01, 0x0F, 0x00,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*寤5003*/},\n        {\n\n                0xA6, 0x4A, 0xEA, 0xBA, 0xAA, 0xAF, 0xAA, 0xBA, 0xEA, 0x4A, 0xA6, 0x00, 0x08, 0x07, 0x02, 0x0A,\n                0x0E, 0x02, 0x02, 0x07, 0x08, 0x00,/*寮5004*/},\n        {\n\n                0x26, 0xAA, 0x6A, 0x3E, 0x6A, 0xAB, 0x2A, 0x3E, 0x6A, 0xAA, 0x26, 0x09, 0x08, 0x05, 0x0D, 0x0B,\n                0x01, 0x03, 0x05, 0x05, 0x0A, 0x09,/*褰5005*/},\n        {\n\n                0x26, 0x3A, 0xEA, 0xAA, 0xBA, 0xAB, 0xBA, 0xAA, 0xEA, 0x3A, 0x26, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x09,/*寰5006*/},\n        {\n\n                0x26, 0xAA, 0x6A, 0xFE, 0xAA, 0xAB, 0xAA, 0xFE, 0x6A, 0xAA, 0x26, 0x09, 0x04, 0x02, 0x04, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x08, 0x09,/*蹇5007*/},\n        {\n\n                0x26, 0xAA, 0x6A, 0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0x6A, 0xAA, 0x26, 0x01, 0x00, 0x0E, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0E, 0x00, 0x01,/*謇5008*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x08, 0x08, 0x08, 0x08, 0x08, 0x08,/*辶5009*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x19, 0x95, 0x51, 0x31, 0xFF, 0x11, 0x11, 0x08, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x08, 0x0A, 0x0B, 0x08, 0x08,/*迓5010*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x48, 0x47, 0x44, 0xFC, 0x44, 0x44, 0x40, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*迕5011*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xFE, 0x02, 0xFA, 0x8A, 0xFA, 0x02, 0xFE, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x08, 0x08, 0x08, 0x08, 0x0A, 0x0B,/*迥5012*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x08, 0x0F, 0x09, 0x09, 0x09, 0x09,/*迮5013*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x24, 0xFA, 0x23, 0xFE, 0x12, 0x8A, 0xFA, 0x02, 0x08, 0x07, 0x08, 0x08, 0x09,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0B,/*迤5014*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x88, 0x67, 0x04, 0xF4, 0x04, 0x24, 0xCC, 0x08, 0x04, 0x03, 0x04, 0x08,\n                0x08, 0x0A, 0x0B, 0x08, 0x08, 0x08,/*迩5015*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x84, 0x7F, 0x04, 0xFC, 0x00, 0xFC, 0x04, 0xFC, 0x08, 0x07, 0x0A, 0x09, 0x08,\n                0x0A, 0x0B, 0x08, 0x0B, 0x0A, 0x0B,/*迦5016*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x22, 0x52, 0x52, 0xCA, 0x56, 0x52, 0x20, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x0A,/*迳5017*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x08, 0xEC, 0x2A, 0x29, 0x28, 0x2A, 0xEC, 0x18, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*迨5018*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFE, 0x12, 0xD2, 0x52, 0x51, 0x51, 0xD1, 0x10, 0x08, 0x07, 0x0A, 0x09, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*逅5019*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x14, 0x56, 0x4B, 0xEA, 0x4A, 0x56, 0x10, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0A,/*逄5020*/},\n        {\n\n                0x11, 0xF2, 0x02, 0xFA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xFB, 0x02, 0x08, 0x07, 0x08, 0x0B, 0x08,\n                0x08, 0x09, 0x08, 0x0A, 0x0B, 0x08,/*逋5021*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFD, 0x25, 0xFD, 0x01, 0xFD, 0x25, 0xFD, 0x00, 0x08, 0x07, 0x08, 0x0B, 0x08,\n                0x0B, 0x08, 0x0B, 0x08, 0x0B, 0x08,/*逦5022*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x14, 0xA4, 0x44, 0xFF, 0x44, 0xA5, 0x14, 0x08, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x0A, 0x0B, 0x08, 0x08, 0x09,/*逑5023*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xF9, 0xAA, 0xA8, 0xAF, 0xA8, 0xAA, 0xF9, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x08, 0x08, 0x08, 0x08, 0x0A, 0x0B,/*逍5024*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x4A, 0x24, 0xFB, 0x00, 0x90, 0x7F, 0x90, 0x12, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x09, 0x0A, 0x09, 0x08, 0x08, 0x0B,/*逖5025*/},\n        {\n\n                0x11, 0xF2, 0x20, 0x94, 0x4E, 0xB5, 0x24, 0x24, 0xEC, 0x16, 0x24, 0x08, 0x07, 0x08, 0x08, 0x0C,\n                0x0A, 0x09, 0x09, 0x0A, 0x0C, 0x08,/*逡5026*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0x48, 0xAA, 0x9A, 0xCF, 0x9A, 0xAA, 0x48, 0x08, 0x04, 0x03, 0x04, 0x0A,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x0A,/*逵5027*/},\n        {\n\n                0x11, 0xF2, 0x08, 0xAA, 0x9A, 0xCA, 0xBF, 0x89, 0x99, 0xA8, 0x88, 0x08, 0x07, 0x08, 0x08, 0x0D,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0D, 0x08,/*逶5028*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x06, 0xFA, 0xAA, 0xAA, 0xAB, 0xAA, 0xBA, 0x06, 0x08, 0x07, 0x08, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*逭5029*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x51, 0x95, 0x15, 0xF5, 0x15, 0x95, 0x5F, 0x10, 0x08, 0x07, 0x0A, 0x09, 0x08,\n                0x0A, 0x0B, 0x08, 0x08, 0x09, 0x0A,/*逯5030*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xD6, 0x54, 0xD4, 0x77, 0xD4, 0x54, 0xD6, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x08, 0x09, 0x08, 0x09, 0x0A, 0x0B,/*遄5031*/},\n        {\n\n                0x11, 0xF2, 0x20, 0xBE, 0xAA, 0xAB, 0xEA, 0xAA, 0xAA, 0xBE, 0x20, 0x08, 0x07, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A,/*遑5032*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFA, 0xAB, 0x9E, 0x8A, 0x9E, 0xAB, 0xFA, 0x02, 0x08, 0x07, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*遒5033*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFF, 0xA9, 0xAF, 0x00, 0x55, 0x95, 0x77, 0x00, 0x08, 0x07, 0x08, 0x0B, 0x08,\n                0x08, 0x0A, 0x09, 0x08, 0x09, 0x0A,/*遐5034*/},\n        {\n\n                0x11, 0xF2, 0x20, 0xEA, 0xBF, 0xAA, 0x28, 0x34, 0xC7, 0x3C, 0x04, 0x08, 0x07, 0x0A, 0x09, 0x0A,\n                0x0B, 0x0A, 0x09, 0x08, 0x0B, 0x08,/*遨5035*/},\n        {\n\n                0x11, 0xF2, 0x08, 0xEA, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xEA, 0x08, 0x08, 0x07, 0x0A, 0x0F, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x0A, 0x0F, 0x0A,/*遘5036*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xC0, 0x5F, 0xD5, 0x15, 0xD5, 0x5F, 0xC0, 0x00, 0x08, 0x07, 0x08, 0x0A, 0x0D,\n                0x0F, 0x08, 0x0A, 0x0D, 0x0F, 0x08,/*遢5037*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xEF, 0xA9, 0xB4, 0xE9, 0xA7, 0xA9, 0xEF, 0x00, 0x08, 0x07, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x0A, 0x0B, 0x08,/*遛5038*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x8F, 0xE9, 0xB9, 0xAB, 0xFD, 0xA9, 0xA9, 0x2F, 0x08, 0x07, 0x08, 0x08, 0x0F,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*暹5039*/},\n        {\n\n                0x11, 0xF2, 0x00, 0x95, 0x6E, 0xC4, 0x1F, 0x44, 0xEE, 0x55, 0x44, 0x08, 0x07, 0x0A, 0x09, 0x0E,\n                0x09, 0x0B, 0x0A, 0x0F, 0x0A, 0x0A,/*遴5040*/},\n        {\n\n                0x10, 0x11, 0xF2, 0x00, 0xFC, 0x54, 0x54, 0xFF, 0x55, 0x55, 0x6D, 0x08, 0x04, 0x03, 0x04, 0x0B,\n                0x0D, 0x0D, 0x0A, 0x0F, 0x0A, 0x0D,/*遽5041*/},\n        {\n\n                0x21, 0xE2, 0x04, 0xFB, 0xAA, 0xFA, 0xAE, 0xF9, 0x27, 0xF9, 0x2F, 0x08, 0x07, 0x0A, 0x09, 0x08,\n                0x09, 0x0A, 0x0B, 0x09, 0x0F, 0x09,/*邂5042*/},\n        {\n\n                0x21, 0xE2, 0xA4, 0x5A, 0xAD, 0xC4, 0x3E, 0xEB, 0x2A, 0xEA, 0x3E, 0x08, 0x07, 0x0A, 0x09, 0x0A,\n                0x0B, 0x0C, 0x0B, 0x08, 0x0B, 0x0A,/*邈5043*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xA6, 0xAA, 0x76, 0xE3, 0xA2, 0x36, 0xAA, 0x26, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0D, 0x0A, 0x0F, 0x09, 0x0A, 0x0C,/*邃5044*/},\n        {\n\n                0x11, 0xF2, 0x00, 0xFA, 0x8D, 0xD8, 0xAA, 0xAD, 0xD8, 0x8A, 0xFD, 0x08, 0x07, 0x08, 0x0F, 0x0A,\n                0x08, 0x0F, 0x0A, 0x08, 0x0B, 0x0C,/*邋5045*/},\n        {\n\n                0x02, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0xFE, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*彐5046*/},\n        {\n\n                0x2A, 0xAA, 0xFF, 0xAA, 0xAA, 0x80, 0xAA, 0xAA, 0xFF, 0xAA, 0x2A, 0x00, 0x08, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*彗5047*/},\n        {\n\n                0x20, 0xA0, 0xAC, 0x6B, 0x6A, 0xAA, 0x2A, 0x3A, 0xA6, 0x60, 0x20, 0x08, 0x0A, 0x0A, 0x05, 0x05,\n                0x0A, 0x0F, 0x01, 0x02, 0x04, 0x04,/*彖5048*/},\n        {\n\n                0x20, 0xE0, 0x2C, 0x2B, 0xEA, 0xAA, 0xAA, 0x3A, 0xE6, 0x20, 0xA0, 0x00, 0x0F, 0x09, 0x05, 0x0A,\n                0x07, 0x0A, 0x00, 0x07, 0x09, 0x0C,/*彘5049*/},\n        {\n\n                0x00, 0xFF, 0x09, 0x49, 0x49, 0xF9, 0x49, 0x49, 0xC9, 0x09, 0x0F, 0x08, 0x07, 0x00, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0C,/*尻5050*/},\n        {\n\n                0x00, 0xFF, 0x21, 0xE1, 0x3F, 0x00, 0x1F, 0xD1, 0x11, 0x51, 0x9F, 0x08, 0x07, 0x00, 0x00, 0x01,\n                0x02, 0x05, 0x08, 0x08, 0x08, 0x09,/*咫5051*/},\n        {\n\n                0x00, 0xFF, 0x25, 0x95, 0x4D, 0xA5, 0xA5, 0xFD, 0xA5, 0xA5, 0x27, 0x08, 0x07, 0x01, 0x0F, 0x00,\n                0x08, 0x0B, 0x04, 0x06, 0x09, 0x08,/*屐5052*/},\n        {\n\n                0x00, 0xFF, 0x05, 0xF5, 0x55, 0xB5, 0xC5, 0x55, 0xD5, 0xF5, 0x17, 0x08, 0x07, 0x00, 0x0F, 0x02,\n                0x01, 0x03, 0x02, 0x0B, 0x0F, 0x00,/*屙5053*/},\n        {\n\n                0x00, 0xFF, 0x85, 0x95, 0x95, 0x55, 0x75, 0x9D, 0x95, 0x95, 0x07, 0x08, 0x07, 0x0A, 0x0E, 0x03,\n                0x02, 0x00, 0x0A, 0x0E, 0x03, 0x02,/*孱5054*/},\n        {\n\n                0x00, 0xFF, 0xA5, 0xD5, 0x2D, 0x45, 0x75, 0x45, 0x7D, 0x55, 0x57, 0x08, 0x07, 0x00, 0x0F, 0x00,\n                0x08, 0x06, 0x08, 0x0F, 0x0A, 0x0A,/*屣5055*/},\n        {\n\n                0x00, 0xFF, 0x95, 0xCD, 0x25, 0x5D, 0x35, 0xFD, 0x15, 0x3D, 0x57, 0x08, 0x07, 0x00, 0x0F, 0x00,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x09,/*屦5056*/},\n        {\n\n                0x00, 0xFF, 0x05, 0x55, 0x9D, 0x55, 0x35, 0x55, 0x9D, 0x55, 0x07, 0x08, 0x07, 0x04, 0x0D, 0x07,\n                0x05, 0x00, 0x05, 0x0F, 0x05, 0x05,/*羼5057*/},\n        {\n\n                0xF2, 0x92, 0x92, 0x9E, 0x40, 0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x00, 0x08, 0x08, 0x07, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*弪5058*/},\n        {\n\n                0x12, 0xB6, 0xAB, 0xAA, 0xB6, 0xA0, 0xB6, 0xAA, 0xAA, 0xF6, 0x10, 0x00, 0x03, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0A, 0x06,/*弩5059*/},\n        {\n\n                0xF2, 0x92, 0x9E, 0x00, 0x02, 0xFE, 0x52, 0x52, 0x52, 0xFE, 0x02, 0x08, 0x08, 0x07, 0x00, 0x02,\n                0x03, 0x02, 0x02, 0x02, 0x0F, 0x01,/*弭5060*/},\n        {\n\n                0x74, 0x54, 0xFF, 0x54, 0xFF, 0x54, 0xFC, 0x93, 0xFA, 0x96, 0xF0, 0x08, 0x06, 0x01, 0x00, 0x0F,\n                0x02, 0x07, 0x08, 0x08, 0x08, 0x0E,/*艴5061*/},\n        {\n\n                0xF2, 0x92, 0x9E, 0x00, 0xFA, 0x4E, 0xFA, 0x00, 0xF2, 0x92, 0x9E, 0x08, 0x08, 0x07, 0x00, 0x0F,\n                0x04, 0x0F, 0x00, 0x08, 0x08, 0x07,/*弼5062*/},\n        {\n\n                0x5D, 0x77, 0xC0, 0x55, 0x4C, 0x7F, 0x4C, 0x55, 0xC0, 0x5D, 0x77, 0x0F, 0x01, 0x05, 0x07, 0x05,\n                0x0D, 0x05, 0x07, 0x05, 0x09, 0x0F,/*鬻5063*/},\n        {\n\n                0x7C, 0x40, 0x40, 0x40, 0x40, 0xFF, 0x40, 0x40, 0x40, 0x40, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*屮5064*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x10, 0x08, 0x27, 0xC4, 0x04, 0x04, 0xFC, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*妁5065*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xE2, 0x22, 0x22, 0x22, 0x3E, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*妃5066*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x22, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x06, 0x01, 0x00, 0x00, 0x0F, 0x00,/*妍5067*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0x22, 0xE2, 0x3E, 0xE2, 0x22, 0x20, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*妩5068*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFE, 0x02, 0x0A, 0x32, 0xC2, 0x3A, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x08, 0x0A, 0x09, 0x08, 0x0B,/*妪5069*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFF, 0x10, 0x10, 0xFF, 0x10, 0x0C, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x04, 0x02, 0x07, 0x08, 0x0E,/*妣5070*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0x90, 0x8C, 0xA3, 0x8C, 0x90, 0x20, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x00, 0x00, 0x08, 0x06, 0x01, 0x00,/*妗5071*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x78, 0x48, 0xFF, 0x44, 0x44, 0xC0, 0x08, 0x05, 0x02, 0x0D, 0x04,\n                0x02, 0x01, 0x0F, 0x00, 0x02, 0x03,/*姊5072*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x0A, 0xCC, 0x3F, 0xC8, 0x08, 0xF8, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x06, 0x01, 0x00, 0x09, 0x08, 0x07,/*妫5073*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x42, 0xC2, 0x7E, 0x42, 0x42, 0xFE, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*妞5074*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0x22, 0x2A, 0xF2, 0x2A, 0x26, 0x60, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x00,/*妤5075*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xF8, 0x82, 0x44, 0x00, 0xFF, 0x00, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x01, 0x08, 0x04, 0x02, 0x01, 0x0E,/*姒5076*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFE, 0x12, 0x12, 0x12, 0xFE, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x08,/*妲5077*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xF8, 0x48, 0xFF, 0x48, 0x48, 0xF8, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x04, 0x07, 0x04, 0x04, 0x0F,/*妯5078*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x20, 0xFE, 0x22, 0xFE, 0x20, 0xFE, 0x22, 0xFE, 0x0D, 0x02, 0x05, 0x08, 0x07,\n                0x08, 0x0F, 0x08, 0x07, 0x08, 0x0F,/*姗5079*/},\n        {\n\n                0xA0, 0xA4, 0xAC, 0xB4, 0xE5, 0xA6, 0xA4, 0xB4, 0xAC, 0xA4, 0xA0, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*妾5080*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x22, 0x42, 0xFE, 0x02, 0xFE, 0x42, 0x22, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x08,/*娅5081*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*娆5082*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x28, 0x26, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x08, 0x05, 0x02, 0x05, 0x0A,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*姝5083*/},\n        {\n\n                0xA4, 0x94, 0x84, 0xBC, 0xC5, 0x86, 0x84, 0xBC, 0x84, 0x94, 0xA4, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*娈5084*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x40, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*姣5085*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x80, 0x89, 0xFA, 0x88, 0x88, 0xFA, 0x89, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*姘5086*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x2C, 0x24, 0xE5, 0x96, 0x94, 0x8C, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x01, 0x01, 0x07, 0x08, 0x08, 0x0E,/*姹5087*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x7F, 0x49, 0xFF, 0x49, 0x7F, 0x00, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*娌5088*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xBE, 0xAA, 0xBF, 0xAA, 0xAA, 0xBE, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x00, 0x03, 0x02, 0x0A, 0x0A, 0x06,/*娉5089*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xE0, 0x2F, 0x29, 0xF9, 0x29, 0x2F, 0xE0, 0x0D, 0x02, 0x05, 0x00, 0x0F,\n                0x02, 0x01, 0x00, 0x01, 0x0A, 0x0F,/*娲5090*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xFD, 0x92, 0x50, 0xFA, 0x52, 0x92, 0xFE, 0x0D, 0x02, 0x05, 0x00, 0x0F,\n                0x00, 0x00, 0x03, 0x00, 0x08, 0x0F,/*娴5091*/},\n        {\n\n                0xA2, 0x94, 0x81, 0xA2, 0xE8, 0xA6, 0xA0, 0x9F, 0x90, 0x92, 0x84, 0x08, 0x08, 0x0A, 0x0B, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x00,/*娑5092*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x75, 0x56, 0xFC, 0x56, 0x5D, 0xC0, 0x08, 0x05, 0x02, 0x05, 0x0C,\n                0x02, 0x01, 0x0F, 0x00, 0x02, 0x03,/*娣5093*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFF, 0xA5, 0xA5, 0xE5, 0x55, 0x57, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x07, 0x02, 0x02, 0x07, 0x09, 0x0D,/*娓5094*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xFE, 0x32, 0xCE, 0xF8, 0x8A, 0xFE, 0x02, 0x0D, 0x02, 0x05, 0x00, 0x0F,\n                0x02, 0x01, 0x00, 0x08, 0x0F, 0x00,/*婀5095*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0x22, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*婧5096*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x44, 0x54, 0xD4, 0x7F, 0xD4, 0x54, 0x44, 0x08, 0x05, 0x02, 0x0D, 0x02,\n                0x01, 0x0F, 0x04, 0x01, 0x06, 0x09,/*婊5097*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x20, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x06, 0x08, 0x0F, 0x0A, 0x0A, 0x08,/*婕5098*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xC0, 0x5F, 0x55, 0x55, 0x5F, 0xC0, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*娼5099*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x08, 0x05, 0x02, 0x05, 0x0A,\n                0x03, 0x02, 0x02, 0x0F, 0x02, 0x02,/*婢5100*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFD, 0x96, 0xFC, 0x96, 0xFD, 0x00, 0x08, 0x05, 0x02, 0x05, 0x0A,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*婵5101*/},\n        {\n\n                0x12, 0xD6, 0x4B, 0x4A, 0xD6, 0x60, 0xD6, 0x4A, 0x4A, 0xD6, 0x10, 0x00, 0x0F, 0x00, 0x01, 0x04,\n                0x02, 0x04, 0x01, 0x08, 0x0F, 0x00,/*胬5102*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xC0, 0x5F, 0xD5, 0x55, 0xD5, 0x5F, 0xC0, 0x0D, 0x02, 0x05, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*媪5103*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0x56, 0x5A, 0xD6, 0x7A, 0x52, 0x59, 0x55, 0x0D, 0x02, 0x05, 0x00, 0x0A,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*媛5104*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x82, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x82, 0x08, 0x05, 0x02, 0x0D, 0x01,\n                0x02, 0x0A, 0x0E, 0x02, 0x02, 0x01,/*婷5105*/},\n        {\n\n                0x48, 0x29, 0x5B, 0x7D, 0x8B, 0x18, 0x44, 0x2B, 0x12, 0x2E, 0x42, 0x09, 0x09, 0x0B, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*婺5106*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x08, 0xEA, 0xAF, 0xFA, 0xAF, 0xEA, 0x08, 0x08, 0x05, 0x02, 0x0D, 0x02,\n                0x0F, 0x02, 0x03, 0x0A, 0x0F, 0x02,/*媾5107*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x02, 0xFA, 0xAF, 0xAA, 0xAF, 0xFA, 0x02, 0x08, 0x05, 0x02, 0x0D, 0x02,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*嫫5108*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0xBE, 0x36, 0x2B, 0xB6, 0x22, 0xBE, 0x08, 0x05, 0x02, 0x0D, 0x00,\n                0x0F, 0x09, 0x00, 0x07, 0x09, 0x0C,/*媲5109*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x30, 0x56, 0xDA, 0x76, 0x5A, 0x51, 0x59, 0x35, 0x0D, 0x02, 0x05, 0x04, 0x02,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*嫒5110*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x06, 0xFA, 0x2A, 0x2B, 0xE6, 0x22, 0x26, 0x08, 0x05, 0x02, 0x05, 0x09,\n                0x05, 0x01, 0x01, 0x05, 0x09, 0x01,/*嫔5111*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x16, 0x94, 0x94, 0xDF, 0x94, 0x94, 0x16, 0x08, 0x05, 0x02, 0x0D, 0x08,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x0C,/*媸5112*/},\n        {\n\n                0x48, 0xEA, 0x5A, 0x7F, 0x5A, 0xE8, 0x44, 0x6B, 0x52, 0x6E, 0x42, 0x08, 0x07, 0x09, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x09,/*嫠5113*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x10, 0x91, 0x7D, 0x51, 0x5F, 0x55, 0x55, 0x11, 0x0D, 0x02, 0x05, 0x08, 0x05,\n                0x09, 0x05, 0x09, 0x05, 0x09, 0x0F,/*嫣5114*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xEA, 0x2E, 0xAA, 0xAF, 0xAA, 0x2E, 0xEA, 0x0D, 0x02, 0x05, 0x00, 0x0F,\n                0x08, 0x0B, 0x0A, 0x0B, 0x08, 0x0F,/*嫱5115*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0x1D, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x0D, 0x02, 0x05, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*嫖5116*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0x0D, 0x76, 0x54, 0xD7, 0x54, 0x76, 0x0D, 0x0D, 0x02, 0x05, 0x00, 0x07,\n                0x01, 0x01, 0x0F, 0x01, 0x05, 0x07,/*嫦5117*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x00, 0x5F, 0x75, 0xD5, 0x5F, 0x35, 0x9F, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*嫘5118*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x08, 0x08, 0x05, 0x02, 0x05, 0x0A,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*嫜5119*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x02, 0xEA, 0xAA, 0xAF, 0xAA, 0xEA, 0x02, 0x08, 0x05, 0x02, 0x0D, 0x02,\n                0x0E, 0x0B, 0x0A, 0x0B, 0x0E, 0x02,/*嬉5120*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xFA, 0x8A, 0xBA, 0xAB, 0xBA, 0x8A, 0xFA, 0x0D, 0x02, 0x05, 0x00, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x08,/*嬗5121*/},\n        {\n\n                0x20, 0x1F, 0x75, 0x55, 0xF7, 0x00, 0x0A, 0x2E, 0x7B, 0x2E, 0x0A, 0x09, 0x09, 0x0B, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*嬖5122*/},\n        {\n\n                0xBF, 0xE5, 0xBF, 0xA5, 0xFC, 0x07, 0xFC, 0xA5, 0xFF, 0xA5, 0xBF, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x03, 0x04, 0x08, 0x07, 0x08, 0x0F,/*嬲5123*/},\n        {\n\n                0xF8, 0x0F, 0xF8, 0x00, 0xFE, 0x2A, 0x7E, 0xAB, 0x1A, 0x7E, 0x2A, 0x0D, 0x02, 0x05, 0x08, 0x07,\n                0x02, 0x09, 0x0C, 0x0A, 0x09, 0x0C,/*嬷5124*/},\n        {\n\n                0x88, 0x78, 0x0F, 0xF8, 0x8C, 0x95, 0xE5, 0x9F, 0xC5, 0x55, 0xCC, 0x08, 0x05, 0x02, 0x0D, 0x04,\n                0x02, 0x0F, 0x02, 0x0F, 0x05, 0x0F,/*孀5125*/},\n        {\n\n                0x41, 0x21, 0x19, 0x07, 0x01, 0xC1, 0x01, 0x0D, 0x4B, 0x48, 0x38, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x04,/*尕5126*/},\n        {\n\n                0x28, 0xA4, 0x62, 0x30, 0x20, 0xAF, 0x20, 0x20, 0x62, 0xA4, 0x28, 0x01, 0x04, 0x02, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x02, 0x04, 0x01,/*尜5127*/},\n        {\n\n                0x00, 0x02, 0x26, 0x2A, 0x22, 0x26, 0xA9, 0x61, 0x29, 0x05, 0x00, 0x01, 0x01, 0x01, 0x09, 0x09,\n                0x0F, 0x01, 0x01, 0x01, 0x01, 0x01,/*孚5128*/},\n        {\n\n                0x12, 0x16, 0x4B, 0x4A, 0x56, 0x40, 0xD6, 0x4A, 0x0A, 0x16, 0x10, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*孥5129*/},\n        {\n\n                0x02, 0x2A, 0xB6, 0xAB, 0xB6, 0x82, 0xAA, 0xB7, 0x2A, 0x36, 0x02, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0E, 0x03, 0x02, 0x02, 0x02, 0x02,/*孳5130*/},\n        {\n\n                0x00, 0x02, 0x02, 0x82, 0x82, 0xE2, 0x52, 0x4A, 0x46, 0x20, 0x20, 0x01, 0x01, 0x01, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*孑5131*/},\n        {\n\n                0x10, 0x22, 0x42, 0x42, 0x82, 0xE2, 0x12, 0x0A, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x01, 0x01, 0x02, 0x02, 0x02,/*孓5132*/},\n        {\n\n                0x82, 0x82, 0xF2, 0x4E, 0x08, 0xF4, 0x97, 0x94, 0xF4, 0x04, 0xFC, 0x00, 0x08, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x09, 0x0D,/*孢5133*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x02, 0x0A, 0x09, 0x07, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*驵5134*/},\n        {\n\n                0x7A, 0x42, 0xDE, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFE, 0x82, 0xFE, 0x0A, 0x09, 0x07, 0x00, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x04, 0x0F,/*驷5135*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x10, 0xFC, 0x03, 0x48, 0x88, 0xFF, 0x08, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x0F, 0x00, 0x00, 0x08, 0x0F, 0x00,/*驸5136*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x08, 0x94, 0x93, 0x92, 0x9A, 0x96, 0xF0, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*驺5137*/},\n        {\n\n                0x3D, 0x21, 0xBF, 0xE0, 0x01, 0xA3, 0x95, 0xE9, 0x95, 0xA3, 0x20, 0x01, 0x09, 0x08, 0x07, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*驿5138*/},\n        {\n\n                0x12, 0x56, 0xCB, 0x4A, 0x56, 0x40, 0x56, 0x4A, 0xCA, 0x16, 0x10, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x01, 0x09, 0x09, 0x07,/*驽5139*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x10, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*骀5140*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x02, 0x0A, 0x09, 0x07, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*骁5141*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC8, 0x04, 0x7E, 0x21, 0x90, 0x3F, 0x44, 0x72, 0x02, 0x0A, 0x09, 0x07, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*骅5142*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x00, 0x89, 0xFA, 0x88, 0x88, 0xFA, 0x89, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*骈5143*/},\n        {\n\n                0x7A, 0x42, 0xDE, 0x00, 0xFA, 0x8A, 0xFA, 0x02, 0xFA, 0x8A, 0xFA, 0x0A, 0x09, 0x07, 0x00, 0x0F,\n                0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F,/*骊5144*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x04, 0xFF, 0x54, 0x54, 0x54, 0xFF, 0x04, 0x02, 0x0A, 0x09, 0x07, 0x09,\n                0x05, 0x01, 0x01, 0x01, 0x05, 0x09,/*骐5145*/},\n        {\n\n                0x3D, 0x21, 0xBF, 0xE0, 0x40, 0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x40, 0x01, 0x09, 0x08, 0x07, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*骒5146*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*骓5147*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x90, 0x54, 0xB6, 0x5D, 0xB4, 0x56, 0x94, 0x02, 0x0A, 0x09, 0x07, 0x08,\n                0x0A, 0x0A, 0x05, 0x04, 0x02, 0x00,/*骖5148*/},\n        {\n\n                0x7F, 0xA1, 0xA5, 0x9B, 0xA4, 0xD7, 0xC4, 0xB7, 0xA5, 0x15, 0x04, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x02, 0x0B, 0x0A, 0x06,/*骘5149*/},\n        {\n\n                0x28, 0x99, 0xAB, 0xBD, 0x8B, 0x98, 0xA4, 0x97, 0x8A, 0x16, 0x22, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x02, 0x0B, 0x0A, 0x06,/*骛5150*/},\n        {\n\n                0x48, 0xAA, 0xBA, 0xAF, 0xEA, 0x8A, 0xC4, 0xAB, 0x92, 0x2E, 0x42, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x02, 0x0B, 0x0A, 0x06,/*骜5151*/},\n        {\n\n                0x7A, 0x42, 0xDE, 0x00, 0xDE, 0x52, 0x69, 0xD2, 0x4E, 0x52, 0xDE, 0x0A, 0x09, 0x07, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*骝5152*/},\n        {\n\n                0x7A, 0x42, 0xDE, 0x00, 0xFE, 0xAA, 0x2A, 0xEB, 0x8A, 0x2A, 0xEE, 0x0A, 0x09, 0x07, 0x08, 0x07,\n                0x02, 0x09, 0x0F, 0x02, 0x09, 0x0F,/*骟5153*/},\n        {\n\n                0x3D, 0x21, 0xBF, 0xE0, 0x1D, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x01, 0x09, 0x08, 0x07, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*骠5154*/},\n        {\n\n                0x7A, 0x42, 0xDE, 0x00, 0xFE, 0x92, 0xDE, 0xAB, 0xDA, 0x82, 0xFE, 0x0A, 0x09, 0x07, 0x08, 0x06,\n                0x00, 0x06, 0x09, 0x0C, 0x02, 0x0C,/*骢5155*/},\n        {\n\n                0x7A, 0x42, 0xDE, 0x00, 0xFF, 0x15, 0x55, 0xF5, 0x1D, 0x55, 0xD7, 0x0A, 0x09, 0x07, 0x08, 0x07,\n                0x0A, 0x0F, 0x02, 0x0A, 0x0F, 0x02,/*骣5156*/},\n        {\n\n                0x7A, 0x42, 0x7E, 0xC0, 0x0A, 0x7A, 0xD7, 0x70, 0xD7, 0x7A, 0x0D, 0x02, 0x0A, 0x09, 0x07, 0x04,\n                0x0D, 0x07, 0x05, 0x07, 0x0D, 0x04,/*骥5157*/},\n        {\n\n                0x7A, 0x42, 0xDE, 0x00, 0xBA, 0xAA, 0xFA, 0x83, 0xFA, 0xAA, 0xBA, 0x0A, 0x09, 0x07, 0x00, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*骧5158*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*纟5159*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x20, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x20, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*纡5160*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0x08, 0x48, 0x88, 0x08, 0xFF, 0x08, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x00, 0x00, 0x09, 0x08, 0x0F, 0x00,/*纣5161*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0x28, 0x27, 0xA4, 0x64, 0x24, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x06, 0x09, 0x08, 0x08, 0x08, 0x0E,/*纥5162*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0x48, 0xFF, 0x08, 0xF8, 0x00, 0x00, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x06, 0x01, 0x02, 0x03, 0x04, 0x0F,/*纨5163*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xFC, 0x04, 0x05, 0x06, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x00,/*纩5164*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x20, 0x22, 0xA2, 0x62, 0x22, 0x22, 0x20, 0x04, 0x04, 0x02, 0x02, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*纭5165*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xFF, 0x10, 0x10, 0xFF, 0x20, 0x10, 0x0C, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x04, 0x02, 0x07, 0x08, 0x08, 0x0E,/*纰5166*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x20, 0x22, 0x2A, 0xF2, 0x2A, 0x26, 0x60, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*纾5167*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x04, 0xFF, 0x44, 0x44, 0x44, 0xFF, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*绀5168*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0xFE, 0x10, 0xFF, 0x10, 0xFF, 0x10, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x08, 0x09, 0x09, 0x09, 0x08,/*绁5169*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0xC8, 0x3F, 0xE8, 0x29, 0xEA, 0x08, 0x04, 0x04, 0x02, 0x02, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*绂5170*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x08, 0x94, 0x93, 0x92, 0x9A, 0x96, 0xF0, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*绉5171*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xF2, 0x92, 0xFF, 0x92, 0xFF, 0x92, 0x9E, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x0F, 0x04, 0x07,/*绋5172*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xBC, 0x20, 0x20, 0xFF, 0x20, 0x20, 0xBC, 0x04, 0x04, 0x02, 0x00, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*绌5173*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*绐5174*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x52, 0xCA, 0x56, 0x53, 0x56, 0x4A, 0x52, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*绔5175*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x24, 0xF2, 0x09, 0x10, 0x12, 0xF2, 0x12, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x00, 0x08, 0x08, 0x0F, 0x00,/*绗5176*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x00, 0x54, 0x57, 0xEA, 0x4A, 0x56, 0x10, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x03, 0x02, 0x0F, 0x02, 0x02, 0x02,/*绛5177*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xFA, 0xAA, 0xAA, 0xFE, 0xAA, 0xAA, 0xFA, 0x04, 0x04, 0x02, 0x00, 0x08,\n                0x05, 0x02, 0x05, 0x08, 0x08, 0x08,/*绠5178*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xF2, 0x54, 0x50, 0x5F, 0x50, 0x54, 0xF2, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x01, 0x01, 0x01, 0x01, 0x09, 0x0F,/*绡5179*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x74, 0x55, 0x56, 0xFC, 0x56, 0x5D, 0xC0, 0x04, 0x04, 0x02, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x00, 0x02, 0x03,/*绨5180*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x28, 0x9A, 0x6A, 0x4F, 0x4A, 0xDA, 0x28, 0x04, 0x04, 0x02, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*绫5181*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x10, 0xDA, 0x56, 0xD3, 0x16, 0xFA, 0x10, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x07, 0x02, 0x03, 0x08, 0x0F, 0x00,/*绮5182*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x24, 0x24, 0xFF, 0x00, 0xFF, 0x24, 0x24, 0x04, 0x04, 0x02, 0x02, 0x01,\n                0x01, 0x0F, 0x00, 0x0F, 0x01, 0x01,/*绯5183*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xF2, 0x14, 0xD0, 0x5F, 0xD0, 0x14, 0xF2, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*绱5184*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xDF, 0x15, 0x15, 0x15, 0xD5, 0x1F, 0x80, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x09, 0x05, 0x00, 0x07, 0x09, 0x0C,/*绲5185*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x48, 0xFA, 0x4A, 0xFE, 0x49, 0xF9, 0x48, 0x04, 0x04, 0x02, 0x00, 0x02,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x02,/*缍5186*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x32, 0xD6, 0x5A, 0x56, 0x5A, 0x52, 0xD9, 0x35, 0x04, 0x04, 0x02, 0x08, 0x08,\n                0x05, 0x02, 0x02, 0x05, 0x08, 0x08,/*绶5187*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x44, 0xAB, 0x92, 0xAE, 0xA0, 0xBF, 0xA4, 0x28, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*绺5188*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x50, 0xB5, 0x9C, 0x97, 0x94, 0xB5, 0x50, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x0A, 0x0B, 0x0C,/*绻5189*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x0C, 0xF4, 0x54, 0x55, 0x56, 0x74, 0x0C, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*绾5190*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xC4, 0x4A, 0x55, 0xCA, 0x55, 0x4A, 0xD1, 0x04, 0x04, 0x02, 0x02, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*缁5191*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xE2, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xE2, 0x04, 0x04, 0x02, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*缂5192*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x48, 0xFF, 0x28, 0x48, 0xFE, 0x92, 0x92, 0xFE, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x00, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*缃5193*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x40, 0x5F, 0x55, 0xD5, 0x55, 0x5F, 0x40, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x07, 0x08, 0x0F, 0x09, 0x09, 0x08,/*缇5194*/},\n        {\n\n                0xDC, 0xB3, 0x08, 0xFE, 0x92, 0xFE, 0x10, 0x08, 0x7F, 0x04, 0xD8, 0x04, 0x04, 0x02, 0x07, 0x02,\n                0x03, 0x08, 0x04, 0x02, 0x01, 0x00,/*缈5195*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x20, 0xAE, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xAE, 0x04, 0x04, 0x02, 0x00, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*缋5196*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0x7F, 0x49, 0xC9, 0x7F, 0x49, 0x49, 0x7F, 0x04, 0x04, 0x02, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*缌5197*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x10, 0xFC, 0x03, 0xFA, 0xAA, 0xFE, 0xAA, 0xFA, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x00, 0x0A, 0x04, 0x0B, 0x08, 0x08,/*缏5198*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x10, 0xFC, 0x03, 0x48, 0x3A, 0xEA, 0x2E, 0x28, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x00, 0x09, 0x05, 0x03, 0x05, 0x09,/*缑5199*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x11, 0xF2, 0x00, 0xFC, 0x56, 0x55, 0xDC, 0x04, 0x04, 0x02, 0x0A, 0x04,\n                0x03, 0x04, 0x0B, 0x0A, 0x0A, 0x0B,/*缒5200*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x7F, 0xD5, 0x95, 0x9D, 0xB5, 0xD7, 0x60, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*缗5201*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x24, 0xA9, 0xBF, 0xA1, 0xA1, 0xBF, 0xA9, 0x24, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*缙5202*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x02, 0x04, 0x04, 0x02, 0x02, 0x02,\n                0x0B, 0x06, 0x02, 0x06, 0x0B, 0x02,/*缜5203*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xFF, 0x11, 0xF5, 0x95, 0x35, 0x55, 0xB5, 0x04, 0x04, 0x02, 0x08, 0x07,\n                0x02, 0x06, 0x02, 0x0A, 0x0F, 0x02,/*缛5204*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x82, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x82, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x00, 0x0E, 0x0A, 0x0E, 0x00, 0x0F,/*缟5205*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0xBA, 0xA2, 0xB6, 0xEB, 0xB6, 0xA2, 0xBA, 0x04, 0x04, 0x02, 0x00, 0x0F,\n                0x00, 0x06, 0x05, 0x06, 0x08, 0x0F,/*缡5206*/},\n        {\n\n                0xDC, 0xB3, 0x08, 0xA9, 0x9A, 0x88, 0x88, 0x88, 0x9A, 0xA9, 0x00, 0x04, 0x04, 0x0A, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*缢5207*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x54, 0x55, 0xFE, 0x54, 0xFE, 0x55, 0xF4, 0x44, 0x04, 0x04, 0x02, 0x05, 0x03,\n                0x0F, 0x01, 0x0F, 0x03, 0x05, 0x08,/*缣5208*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x06, 0xFA, 0x2A, 0x2B, 0xE6, 0x22, 0x26, 0x04, 0x04, 0x02, 0x02, 0x09,\n                0x05, 0x01, 0x01, 0x05, 0x09, 0x01,/*缤5209*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x1D, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x04, 0x04, 0x02, 0x02, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*缥5210*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x70, 0x5F, 0x75, 0x55, 0x75, 0x5F, 0x70, 0x04, 0x04, 0x02, 0x02, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*缦5211*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x00, 0x5F, 0x75, 0xD5, 0x5F, 0x35, 0x95, 0x1F, 0x04, 0x04, 0x02, 0x08, 0x05,\n                0x01, 0x09, 0x0F, 0x01, 0x05, 0x09,/*缧5212*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x40, 0x4B, 0xA5, 0xAF, 0x50, 0x2B, 0x45, 0x4F, 0x04, 0x04, 0x02, 0x00, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x05, 0x04, 0x02,/*缪5213*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0xFA, 0xAD, 0xAA, 0xFD, 0xAA, 0xAD, 0xF8, 0x04, 0x04, 0x02, 0x00, 0x0A,\n                0x06, 0x02, 0x0F, 0x02, 0x06, 0x0A,/*缫5214*/},\n        {\n\n                0xDC, 0xB3, 0x08, 0xA4, 0xBF, 0xA4, 0x00, 0xF2, 0x9A, 0x16, 0xF2, 0x04, 0x04, 0x02, 0x0F, 0x04,\n                0x0F, 0x08, 0x05, 0x03, 0x04, 0x09,/*缬5215*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x2A, 0xF2, 0xAA, 0xA7, 0xAA, 0xF2, 0x2A, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x07, 0x0A, 0x0E, 0x02, 0x07, 0x08,/*缭5216*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x3E, 0xAB, 0xA2, 0xBE, 0xA2, 0xAB, 0x3E, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*缯5217*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x08, 0x82, 0xBE, 0xAA, 0xBE, 0xAA, 0xBE, 0x82, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x0F, 0x0A, 0x0F, 0x0A, 0x0F, 0x08,/*缰5218*/},\n        {\n\n                0xDC, 0xB3, 0x88, 0x42, 0xC4, 0x2E, 0xEA, 0xBF, 0xAA, 0xEE, 0x20, 0x04, 0x04, 0x02, 0x08, 0x07,\n                0x08, 0x0F, 0x0A, 0x0A, 0x0E, 0x08,/*缱5219*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x70, 0x57, 0x75, 0x85, 0x75, 0x57, 0x70, 0x04, 0x04, 0x02, 0x02, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*缲5220*/},\n        {\n\n                0x98, 0xD4, 0xB3, 0x88, 0x17, 0xD5, 0x57, 0x55, 0x57, 0xD5, 0x17, 0x04, 0x04, 0x02, 0x02, 0x08,\n                0x05, 0x0F, 0x09, 0x03, 0x05, 0x0A,/*缳5221*/},\n        {\n\n                0xDC, 0xB3, 0x0C, 0xAB, 0x9A, 0x8F, 0xBA, 0xAB, 0x9A, 0xBF, 0x2A, 0x04, 0x04, 0x02, 0x0B, 0x08,\n                0x04, 0x03, 0x04, 0x04, 0x0B, 0x00,/*缵5222*/},\n        {\n\n                0x00, 0x20, 0x30, 0x28, 0xA4, 0x63, 0x20, 0x10, 0x0C, 0x00, 0x00, 0x00, 0x04, 0x06, 0x05, 0x04,\n                0x04, 0x04, 0x04, 0x05, 0x06, 0x0C,/*幺5223*/},\n        {\n\n                0x40, 0xDA, 0x55, 0xDA, 0x40, 0xDF, 0x60, 0xDA, 0x75, 0x5A, 0x40, 0x00, 0x0F, 0x05, 0x07, 0x05,\n                0x0F, 0x08, 0x05, 0x02, 0x05, 0x0E,/*畿5224*/},\n        {\n\n                0x00, 0x60, 0x98, 0x06, 0x60, 0x98, 0x06, 0x60, 0x98, 0x06, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00,\n                0x01, 0x06, 0x00, 0x01, 0x06, 0x00,/*巛5225*/},\n        {\n\n                0x04, 0xEA, 0x31, 0x20, 0x24, 0xEA, 0x31, 0x20, 0x24, 0xEA, 0x11, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x0F, 0x00,/*甾5226*/},\n        {\n\n                0x00, 0x82, 0xBD, 0xA8, 0xAA, 0xAD, 0xA8, 0xAA, 0xBD, 0x80, 0x00, 0x00, 0x07, 0x0A, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*邕5227*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x22, 0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x04, 0x04, 0x07, 0x02, 0x02,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*玎5228*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x00, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x04, 0x04, 0x03, 0x0A, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*玑5229*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x44, 0x54, 0x54, 0xFF, 0x54, 0x54, 0xC4, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*玮5230*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x10, 0x2C, 0xE3, 0x20, 0x23, 0xEC, 0x10, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x06, 0x01, 0x08, 0x08, 0x07, 0x00,/*玢5231*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x04, 0x3C, 0xC5, 0x06, 0xC4, 0x3C, 0x04, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*玟5232*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x00, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x00, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x09, 0x0A,/*珏5233*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x00, 0xF2, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x03, 0x01, 0x09, 0x08, 0x0F, 0x00,/*珂5234*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x08, 0x08, 0xFF, 0x08, 0xF9, 0x8A, 0x48, 0x04, 0x04, 0x03, 0x0A, 0x04,\n                0x03, 0x04, 0x02, 0x07, 0x08, 0x0E,/*珑5235*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x00, 0xC0, 0x40, 0x7F, 0x48, 0x48, 0xC8, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*玷5236*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x10, 0xFC, 0x23, 0x20, 0xFF, 0x12, 0x14, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x00, 0x00, 0x03, 0x04, 0x0E,/*玳5237*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x00, 0xFC, 0x44, 0x46, 0x45, 0x44, 0xFC, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*珀5238*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x00, 0xFF, 0x49, 0x49, 0xF9, 0x49, 0x4F, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x00, 0x03, 0x04, 0x0E,/*珉5239*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0xFC, 0x04, 0xFC, 0x04, 0x07, 0x0A, 0x04, 0x03,\n                0x08, 0x0F, 0x00, 0x0F, 0x04, 0x0F,/*珈5240*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x02, 0xFE, 0x52, 0x52, 0x52, 0xFE, 0x02, 0x04, 0x07, 0x02, 0x00, 0x02,\n                0x03, 0x02, 0x02, 0x02, 0x0F, 0x01,/*珥5241*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x80, 0x88, 0xFF, 0x88, 0x88, 0xFF, 0x88, 0x80, 0x04, 0x07, 0x02, 0x08, 0x04,\n                0x02, 0x00, 0x00, 0x02, 0x04, 0x08,/*珙5242*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xF9, 0x09, 0x0D, 0xEB, 0x09, 0x09, 0xF9, 0x04, 0x03, 0x02, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*顼5243*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x3D, 0xA1, 0xFF, 0x21, 0xFE, 0x32, 0xCE, 0x04, 0x07, 0x02, 0x02, 0x01,\n                0x08, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*琊5244*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x24, 0xF2, 0x09, 0x10, 0x12, 0xF2, 0x12, 0x04, 0x07, 0x02, 0x00, 0x00,\n                0x0F, 0x00, 0x08, 0x08, 0x0F, 0x00,/*珩5245*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x88, 0x50, 0xFF, 0x00, 0x00, 0xFF, 0x50, 0x88, 0x04, 0x07, 0x02, 0x08, 0x06,\n                0x01, 0x00, 0x00, 0x07, 0x08, 0x0E,/*珧5246*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*珞5247*/},\n        {\n\n                0x00, 0xA4, 0x93, 0x8A, 0xA2, 0xBE, 0x82, 0x8A, 0x92, 0xA6, 0x00, 0x08, 0x08, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0E, 0x0A, 0x08, 0x08,/*玺5248*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x16, 0xD2, 0xB2, 0xDA, 0x92, 0x92, 0x06, 0x04, 0x07, 0x02, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*珲5249*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x11, 0xF2, 0x00, 0x34, 0x2C, 0xF7, 0x24, 0x24, 0x04, 0x07, 0x0A, 0x04, 0x03,\n                0x04, 0x09, 0x09, 0x0F, 0x09, 0x09,/*琏5250*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x04, 0xFF, 0x54, 0x54, 0x54, 0xFF, 0x04, 0x04, 0x04, 0x03, 0x02, 0x09,\n                0x05, 0x01, 0x01, 0x01, 0x05, 0x09,/*琪5251*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x02, 0xF7, 0x12, 0xFA, 0x12, 0xF7, 0x02, 0x04, 0x07, 0x02, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*瑛5252*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x10, 0xDA, 0x56, 0xD3, 0x16, 0xFA, 0x10, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x07, 0x02, 0x03, 0x08, 0x0F, 0x00,/*琦5253*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xF8, 0x48, 0x48, 0x7F, 0xAA, 0xAA, 0xD8, 0x04, 0x07, 0x02, 0x08, 0x07,\n                0x08, 0x07, 0x01, 0x07, 0x08, 0x0C,/*琥5254*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xDF, 0x15, 0x15, 0x15, 0xD5, 0x1F, 0x80, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x09, 0x05, 0x00, 0x07, 0x09, 0x0C,/*琨5255*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x28, 0xA6, 0x10, 0xCF, 0x10, 0x14, 0xA2, 0x04, 0x07, 0x02, 0x08, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x05, 0x08,/*琰5256*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x86, 0x92, 0x92, 0x93, 0x92, 0x92, 0x86, 0x04, 0x07, 0x02, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*琮5257*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x80, 0x66, 0x9A, 0xF2, 0x03, 0xF2, 0x92, 0xF6, 0x04, 0x07, 0x02, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*琬5258*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x46, 0x52, 0x4A, 0xE2, 0x4A, 0x52, 0x46, 0x04, 0x07, 0x02, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*琛5259*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x00, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xAE, 0x04, 0x04, 0x03, 0x0A, 0x06,\n                0x01, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*琚5260*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x07, 0xF1, 0x55, 0x55, 0x55, 0xF1, 0x07, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*瑁5261*/},\n        {\n\n                0x22, 0xFE, 0x22, 0xE8, 0xA4, 0xAA, 0xE9, 0x0A, 0xC4, 0x08, 0xE8, 0x04, 0x07, 0x02, 0x0F, 0x02,\n                0x0A, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*瑜5262*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x56, 0x5A, 0xD6, 0x7A, 0x52, 0x59, 0x55, 0x04, 0x07, 0x02, 0x04, 0x0A,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*瑗5263*/},\n        {\n\n                0x22, 0xFE, 0x22, 0xFF, 0x49, 0x4F, 0x00, 0xC9, 0x49, 0xCF, 0x00, 0x04, 0x07, 0x02, 0x0F, 0x02,\n                0x02, 0x08, 0x05, 0x02, 0x05, 0x08,/*瑕5264*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xC4, 0x6A, 0xD5, 0x4A, 0xD5, 0x4A, 0xD1, 0x04, 0x07, 0x02, 0x00, 0x0F,\n                0x04, 0x06, 0x05, 0x06, 0x04, 0x0F,/*瑙5265*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x30, 0x56, 0xDA, 0x76, 0x5A, 0x51, 0x59, 0x35, 0x04, 0x07, 0x02, 0x04, 0x02,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*瑷5266*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xFE, 0x22, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x04, 0x07, 0x02, 0x08, 0x07,\n                0x00, 0x0E, 0x0B, 0x0A, 0x0E, 0x00,/*瑭5267*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xE2, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xE2, 0x04, 0x07, 0x02, 0x00, 0x0A,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0A,/*瑾5268*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x08, 0xEA, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xEA, 0x04, 0x07, 0x02, 0x00, 0x0B,\n                0x06, 0x02, 0x03, 0x02, 0x06, 0x0B,/*璜5269*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x80, 0xAF, 0x91, 0xEF, 0x80, 0xAF, 0x91, 0xAF, 0x04, 0x07, 0x02, 0x08, 0x0A,\n                0x0B, 0x04, 0x04, 0x0B, 0x08, 0x00,/*璎5270*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x40, 0x26, 0xF4, 0xAC, 0xA7, 0xEC, 0xB4, 0xA6, 0x04, 0x07, 0x02, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*璀5271*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xFE, 0x92, 0xDE, 0xAB, 0xDA, 0x82, 0xFE, 0x04, 0x07, 0x02, 0x08, 0x06,\n                0x00, 0x06, 0x09, 0x0C, 0x02, 0x0C,/*璁5272*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x04, 0xFD, 0x26, 0xE4, 0x13, 0xF2, 0x92, 0xB2, 0x04, 0x07, 0x02, 0x08, 0x07,\n                0x08, 0x0F, 0x04, 0x0F, 0x08, 0x08,/*璇5273*/},\n        {\n\n                0x22, 0x22, 0xFE, 0x22, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x08, 0x02, 0x02, 0x01, 0x01, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*璋5274*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0x25, 0xAC, 0xB7, 0xE4, 0xB7, 0xAC, 0x25, 0x04, 0x07, 0x02, 0x00, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*璞5275*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x10, 0x58, 0xAF, 0x1A, 0xC0, 0x2A, 0x92, 0x2E, 0x04, 0x07, 0x02, 0x01, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*璨5276*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x00, 0xFC, 0x54, 0x54, 0xFF, 0x55, 0x55, 0x6D, 0x04, 0x07, 0x02, 0x04, 0x03,\n                0x05, 0x05, 0x0A, 0x0F, 0x02, 0x05,/*璩5277*/},\n        {\n\n                0x22, 0xFE, 0x22, 0x9E, 0x12, 0xF2, 0x9E, 0x44, 0xAB, 0x92, 0xAE, 0x04, 0x07, 0x0A, 0x0F, 0x08,\n                0x07, 0x04, 0x00, 0x0F, 0x04, 0x0F,/*璐5278*/},\n        {\n\n                0xA0, 0x9F, 0xF5, 0xD5, 0xF7, 0x80, 0x8A, 0xAE, 0xFB, 0xAE, 0x8A, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0E, 0x0A, 0x08,/*璧5279*/},\n        {\n\n                0x22, 0xFE, 0x26, 0xAB, 0x9A, 0x8F, 0xBA, 0xAB, 0x9A, 0xBF, 0x2A, 0x04, 0x07, 0x02, 0x0B, 0x08,\n                0x04, 0x03, 0x04, 0x04, 0x0B, 0x00,/*瓒5280*/},\n        {\n\n                0x60, 0xBE, 0xA5, 0xA0, 0xBF, 0xA5, 0xBF, 0xA0, 0xA5, 0xBF, 0x60, 0x08, 0x08, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0E, 0x0A, 0x08, 0x08,/*璺5281*/},\n        {\n\n                0x40, 0x5F, 0x55, 0xD5, 0x5F, 0x62, 0x2A, 0xFF, 0x2A, 0x2A, 0xE2, 0x08, 0x07, 0x08, 0x0F, 0x09,\n                0x08, 0x08, 0x0F, 0x08, 0x09, 0x09,/*韪5282*/},\n        {\n\n                0x54, 0xFF, 0x54, 0xD4, 0x00, 0xDF, 0x55, 0xD5, 0x55, 0xDF, 0x00, 0x00, 0x0F, 0x02, 0x03, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*韫5283*/},\n        {\n\n                0x54, 0xFF, 0x54, 0xD4, 0x00, 0xCA, 0x52, 0x26, 0x09, 0x51, 0xCD, 0x00, 0x0F, 0x02, 0x03, 0x00,\n                0x0F, 0x05, 0x04, 0x04, 0x05, 0x0F,/*韬5284*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x42, 0x02, 0xFE, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*杌5285*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x50, 0x08, 0x27, 0xC4, 0x04, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*杓5286*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0xE2, 0x22, 0x22, 0x22, 0x3E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*杞5287*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x42, 0x3E, 0xC2, 0x0A, 0xD2, 0x3E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*杈5288*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x41, 0x3D, 0x21, 0x21, 0x21, 0x3F, 0xE0, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x08, 0x07,/*杩5289*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFE, 0x22, 0x22, 0xFA, 0x22, 0xE2, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x08, 0x06, 0x09, 0x08, 0x07,/*枥5290*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0xFF, 0x10, 0x10, 0xFF, 0x10, 0x0C, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x02, 0x07, 0x08, 0x0E,/*枇5291*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*杪5292*/},\n        {\n\n                0x24, 0xE4, 0x54, 0x4C, 0x44, 0x7F, 0x44, 0x4C, 0x54, 0xE4, 0x24, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*杳5293*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFC, 0x84, 0x44, 0x3F, 0x44, 0x84, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*枘5294*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*枧5295*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0x88, 0x87, 0x84, 0xFC, 0x84, 0x84, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*杵5296*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x20, 0xFF, 0x28, 0xE4, 0x22, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x04, 0x00, 0x03, 0x04,/*枨5297*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x04, 0x03,\n                0x08, 0x05, 0x03, 0x00, 0x07, 0x08,/*枞5298*/},\n        {\n\n                0x80, 0xBE, 0xA2, 0xA6, 0xAB, 0xE2, 0xA2, 0xAA, 0xAE, 0x20, 0xE0, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x05, 0x05,/*枭5299*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*枋5300*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0xFE, 0x42, 0x7E, 0x42, 0x7E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*杷5301*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x20, 0x22, 0x2A, 0xF2, 0x2A, 0x26, 0x60, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*杼5302*/},\n        {\n\n                0x12, 0x12, 0x4A, 0x46, 0x42, 0x5F, 0x42, 0x46, 0x4A, 0x12, 0x12, 0x01, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x01,/*柰5303*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x24, 0x2F, 0xE4, 0x24, 0x2F, 0xE4, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*栉5304*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x80, 0x42, 0xF2, 0x2E, 0x22, 0x22, 0xE2, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*柘5305*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x08, 0xFF, 0x08, 0xF9, 0x8A, 0x48, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x04, 0x02, 0x07, 0x08, 0x0E,/*栊5306*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFE, 0x42, 0x32, 0x9E, 0x52, 0x32, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x09, 0x08, 0x09, 0x0A,/*柩5307*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0x88, 0xB2, 0x82, 0xFE, 0x82, 0xA2, 0x98, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*枰5308*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xF0, 0x90, 0x9F, 0x92, 0x92, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x01,/*栌5309*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0x92, 0x92, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x01,/*柙5310*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x20, 0xAF, 0x69, 0x29, 0x29, 0x2F, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*枵5311*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0xFC, 0x44, 0x44, 0xFF, 0x44, 0x44, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*柚5312*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFE, 0x82, 0x82, 0x82, 0xFE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x00, 0x02, 0x04, 0x08,/*枳5313*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFE, 0x12, 0x92, 0xF1, 0x11, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x01, 0x02,/*柝5314*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xFE, 0x0A, 0xEA, 0x2A, 0x29, 0xE9, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x07, 0x08, 0x09, 0x0D,/*栀5315*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0x48, 0x44, 0x53, 0x64, 0xC8, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x02, 0x04, 0x0B, 0x00, 0x00,/*柃5316*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0xE8, 0x27, 0x24, 0xE4, 0x04, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x03, 0x01, 0x01, 0x09, 0x08, 0x07,/*枸5317*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x08, 0x03, 0x04, 0x0E,/*柢5318*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xBE, 0x22, 0xFA, 0x21, 0xA1, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*栎5319*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x2C, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*柁5320*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x42, 0x46, 0x2A, 0xD2, 0x2A, 0x46, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*柽5321*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x94, 0xD4, 0x7F, 0x54, 0x58, 0x54, 0x12, 0x00, 0x00, 0x0F, 0x01, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*栲5322*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x20, 0xA4, 0xE4, 0x3F, 0x34, 0xA8, 0xA6, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x07, 0x09, 0x09, 0x08, 0x0C,/*栳5323*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x22, 0x42, 0xFE, 0x02, 0xFE, 0x42, 0x22, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x08,/*桠5324*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*桡5325*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x32, 0x2A, 0xE6, 0x22, 0x32, 0x62, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*桎5326*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xF0, 0x10, 0x10, 0xDF, 0x14, 0x14, 0xF4, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*桢5327*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x24, 0x28, 0xE0, 0x3F, 0xE0, 0x28, 0x24, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*桄5328*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0x2E, 0x28, 0x2F, 0x28, 0xEE, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x09, 0x09, 0x09, 0x09, 0x0C,/*桤5329*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x72, 0xCE, 0x00, 0x22, 0xFE, 0x21, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x04, 0x0B, 0x08, 0x0A, 0x0B, 0x0A,/*梃5330*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*栝5331*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0xFC, 0x44, 0x42, 0x01, 0x44, 0x44, 0xFC, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*桕5332*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x04, 0x7E, 0x21, 0x90, 0x3F, 0x44, 0x72, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*桦5333*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x24, 0xF2, 0x09, 0x10, 0x12, 0xF2, 0x12, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x00, 0x08, 0x08, 0x0F, 0x00,/*桁5334*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0x88, 0x94, 0x92, 0x91, 0x92, 0x94, 0x88, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*桧5335*/},\n        {\n\n                0x88, 0xC4, 0xAB, 0x92, 0x8E, 0xC0, 0x9A, 0x92, 0xFF, 0x92, 0x90, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*桀5336*/},\n        {\n\n                0xA2, 0x9A, 0x82, 0xBE, 0x82, 0xC3, 0x82, 0xBE, 0x82, 0x8A, 0xB2, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*栾5337*/},\n        {\n\n                0x90, 0x54, 0xB5, 0x96, 0x9C, 0xD7, 0x94, 0x96, 0xB5, 0x54, 0x90, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x00,/*桊5338*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0x4C, 0xC4, 0x75, 0x46, 0xC4, 0x4C, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x08, 0x05, 0x02, 0x02, 0x05, 0x08,/*桉5339*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x12, 0xA2, 0xFE, 0x00, 0x12, 0xA2, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x08, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*栩5340*/},\n        {\n\n                0x12, 0x0A, 0x3F, 0xCA, 0x52, 0x40, 0x52, 0xCA, 0x3F, 0x0A, 0x12, 0x08, 0x08, 0x04, 0x03, 0x01,\n                0x02, 0x00, 0x07, 0x08, 0x08, 0x0E,/*梵5341*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x28, 0xA6, 0xA4, 0xBF, 0xA4, 0xA4, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*梏5342*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x2A, 0x32, 0x26, 0xAA, 0x61, 0x29, 0x05, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x01, 0x09, 0x0F, 0x01, 0x01, 0x01,/*桴5343*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xF4, 0x53, 0xF2, 0x5A, 0x56, 0xF0, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x07, 0x01, 0x07, 0x01, 0x09, 0x0F,/*桷5344*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x54, 0x65, 0xC6, 0x64, 0x54, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x00,/*梓5345*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x11, 0x22, 0x18, 0x00, 0xFF, 0x08, 0xB0, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x09, 0x08, 0x04, 0x02, 0x01, 0x00,/*桫5346*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x22, 0xAA, 0x2A, 0xEA, 0x2A, 0x3E, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x05, 0x08,/*棂5347*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD4, 0x12, 0x00, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*楮5348*/},\n        {\n\n                0x92, 0x8A, 0xBF, 0x4A, 0x12, 0x00, 0x12, 0x4A, 0xBF, 0x8A, 0x92, 0x00, 0x08, 0x09, 0x07, 0x01,\n                0x01, 0x09, 0x09, 0x07, 0x00, 0x00,/*棼5349*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0x4A, 0xAA, 0x4F, 0xEA, 0x0A, 0x18, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x09, 0x05, 0x03, 0x01, 0x05, 0x09,/*椟5350*/},\n        {\n\n                0x22, 0x2E, 0x2B, 0x7E, 0x2A, 0xC0, 0x3E, 0x0A, 0x09, 0x79, 0x08, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*椠5351*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0xF8, 0xA8, 0xAF, 0xAA, 0xAA, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*棹5352*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x1E, 0x92, 0x7E, 0x52, 0x5E, 0x52, 0xDE, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x08, 0x05, 0x06, 0x02, 0x01, 0x00,/*椤5353*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0x48, 0xFA, 0x4A, 0xFE, 0x49, 0xF9, 0x48, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x0B, 0x02,/*棰5354*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x44, 0xF4, 0x95, 0x96, 0x94, 0xF4, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*椋5355*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x42, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x0A, 0x0E, 0x03, 0x02, 0x02,/*椁5356*/},\n        {\n\n                0xC8, 0xFF, 0x28, 0x64, 0xDC, 0x88, 0xAA, 0xFF, 0xAA, 0xBE, 0x08, 0x00, 0x0F, 0x00, 0x0A, 0x07,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0A,/*楗5357*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xAA, 0x2A, 0xFF, 0x2A, 0xBE, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x09, 0x0F, 0x01, 0x02, 0x04,/*棣5358*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x00, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xAE, 0x00, 0x00, 0x0F, 0x08, 0x06,\n                0x01, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*椐5359*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xA2, 0x6A, 0xBA, 0xAF, 0xAA, 0x6A, 0xA2, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x02,/*楱5360*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x88, 0x82, 0xFF, 0xAA, 0xAA, 0xFF, 0x82, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x0A, 0x09, 0x08, 0x09, 0x0A,/*椹5361*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0xFA, 0x0A, 0x5A, 0xEF, 0x5A, 0x0A, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*楠5362*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x12, 0xEA, 0xA6, 0xBF, 0xA6, 0xEA, 0x12, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*楂5363*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x44, 0xFA, 0xAA, 0x8A, 0xFF, 0x8A, 0xAA, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*楝5364*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xEE, 0x20, 0xBF, 0x24, 0x23, 0xE6, 0x0A, 0x00, 0x00, 0x0F, 0x08, 0x05,\n                0x02, 0x01, 0x06, 0x08, 0x09, 0x0C,/*榄5365*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x10, 0xF7, 0x55, 0x55, 0x55, 0xF7, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x07, 0x05, 0x05, 0x05, 0x0F, 0x02,/*楫5366*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0xC0, 0x5E, 0xD2, 0x12, 0xD2, 0x5E, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x04, 0x0F, 0x00, 0x0F, 0x04, 0x0F,/*榀5367*/},\n        {\n\n                0x4C, 0x2B, 0x1E, 0x2A, 0x4A, 0x80, 0x7F, 0x55, 0x55, 0x5D, 0x41, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*榘5368*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x92, 0xFE, 0x51, 0x08, 0xFF, 0x10, 0x0C, 0x00, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x08, 0x07, 0x00, 0x07, 0x08,/*楸5369*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0x00, 0xFE, 0x25, 0x08, 0xE7, 0x21, 0xEF, 0x08, 0x00, 0x0F, 0x00, 0x02, 0x0F,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*椴5370*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x11, 0xF2, 0x00, 0xFC, 0x56, 0x55, 0xDC, 0x00, 0x00, 0x0F, 0x08, 0x04,\n                0x03, 0x04, 0x0B, 0x0A, 0x0A, 0x0B,/*槌5371*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x24, 0xAC, 0xB5, 0xE6, 0xB4, 0xAC, 0x24, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*榇5372*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFD, 0x02, 0xB8, 0xAA, 0xBA, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*榈5373*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x44, 0xD5, 0x76, 0x5C, 0x56, 0x55, 0x44, 0x00, 0x00, 0x0F, 0x04, 0x0A,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*槎5374*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x41, 0xAA, 0x99, 0xCA, 0x9C, 0xAA, 0x49, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*榉5375*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x06, 0xEA, 0xAA, 0xAB, 0xAA, 0xEA, 0x06, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*楦5376*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0xFF, 0x09, 0xE9, 0xAF, 0xA9, 0xA9, 0xEF, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x00, 0x0F, 0x0A, 0x0A, 0x0A, 0x0F,/*楣5377*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0xB9, 0x87, 0xAD, 0x95, 0xAD, 0xC3, 0xBE, 0x00, 0x00, 0x0F, 0x08, 0x0F, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x0F, 0x08,/*楹5378*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xA2, 0x6A, 0xBA, 0xAF, 0xAA, 0x6A, 0xA2, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x06, 0x02, 0x0F, 0x02, 0x06, 0x0A,/*榛5379*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0x52, 0xFE, 0x02, 0xFE, 0x52, 0x52, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x09, 0x0F, 0x08, 0x0F, 0x09, 0x09,/*榧5380*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x40, 0x5F, 0xD5, 0x15, 0x55, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x05,\n                0x0A, 0x0F, 0x00, 0x05, 0x0A, 0x0F,/*榻5381*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x44, 0xFE, 0xAB, 0xAA, 0xFF, 0xAA, 0xAA, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*榫5382*/},\n        {\n\n                0x84, 0x64, 0xFF, 0xA4, 0xFE, 0xAB, 0xFE, 0x40, 0x88, 0xFF, 0x08, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x09, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*榭5383*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x80, 0xBE, 0xEA, 0xAB, 0xAA, 0xBE, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x05, 0x04, 0x0E, 0x04, 0x05, 0x02,/*槔5384*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x22, 0xFA, 0xAA, 0xAB, 0xAA, 0xFA, 0x22, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x0F, 0x09, 0x02, 0x04, 0x0A,/*榱5385*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x82, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x82, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x0E, 0x0A, 0x0E, 0x00, 0x0F,/*槁5386*/},\n        {\n\n                0x84, 0xB5, 0x66, 0x3C, 0x26, 0xB5, 0x40, 0x3F, 0x15, 0x95, 0xFF, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*槊5387*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x06, 0xFA, 0x2A, 0x2B, 0xE6, 0x22, 0x26, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x05, 0x01, 0x01, 0x05, 0x09, 0x01,/*槟5388*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x96, 0x4A, 0x22, 0x13, 0x22, 0x4A, 0x96, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*榕5389*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x22, 0xE4, 0x90, 0xD4, 0x7F, 0x54, 0xD8, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x02, 0x0F, 0x05, 0x05, 0x0F,/*槠5390*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFF, 0x05, 0xED, 0xB5, 0xBD, 0xB5, 0xEF, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x00, 0x0F, 0x02, 0x02, 0x0A, 0x0F,/*榍5391*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xE2, 0xAF, 0xAA, 0xFA, 0xAA, 0xAF, 0xE2, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0A,/*槿5392*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0xEA, 0x2E, 0xAA, 0xAF, 0xAA, 0x2E, 0xEA, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x08, 0x0B, 0x0A, 0x0B, 0x08, 0x0F,/*樯5393*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFC, 0x44, 0xFC, 0x54, 0xFF, 0x04, 0xE5, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x0A, 0x0F, 0x05, 0x03, 0x05, 0x0E,/*槭5394*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x4C, 0xD5, 0x45, 0x5F, 0x45, 0x55, 0x4C, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*樗5395*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x0D, 0xF6, 0x94, 0x97, 0x94, 0xF6, 0x0D, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*樘5396*/},\n        {\n\n                0x28, 0x95, 0x8A, 0x7D, 0x40, 0x2A, 0xFA, 0xAF, 0xAA, 0xAC, 0xFA, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*橥5397*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0xF4, 0x53, 0xFA, 0x56, 0xF2, 0x24, 0xFF, 0x80, 0x00, 0x0F, 0x08, 0x07, 0x01,\n                0x07, 0x09, 0x0F, 0x01, 0x0F, 0x00,/*槲5398*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0xF9, 0xAD, 0xFB, 0x10, 0xEC, 0x0B, 0xF8, 0x08, 0x00, 0x0F, 0x02, 0x03, 0x02,\n                0x0F, 0x09, 0x04, 0x03, 0x04, 0x08,/*橄5399*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0xA4, 0x24, 0xFF, 0xA4, 0xF8, 0x08, 0xFF, 0x4A, 0x00, 0x0F, 0x00, 0x0F, 0x04,\n                0x0F, 0x08, 0x0B, 0x09, 0x09, 0x0B,/*樾5400*/},\n        {\n\n                0x12, 0xEA, 0xAF, 0xEA, 0x8F, 0x7A, 0x88, 0x57, 0x24, 0x5C, 0x84, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*檠5401*/},\n        {\n\n                0x9A, 0x4A, 0xEE, 0xBA, 0xAA, 0xAF, 0xAA, 0xAA, 0xAE, 0xEA, 0x1A, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*橐5402*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0x2A, 0xF2, 0x2A, 0xA2, 0xDE, 0x32, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x09, 0x07, 0x09, 0x05, 0x03, 0x0C,/*橛5403*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0x08, 0xFC, 0x57, 0x54, 0xFD, 0x56, 0x54, 0x00, 0x00, 0x0F, 0x00, 0x0C,\n                0x03, 0x0D, 0x01, 0x0D, 0x01, 0x0D,/*樵5404*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0x72, 0x46, 0x6D, 0xD7, 0x6D, 0x46, 0x72, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x07, 0x05, 0x0F, 0x01, 0x0F,/*檎5405*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0x84, 0xFA, 0xAB, 0xFA, 0xAE, 0xA8, 0xF8, 0x80, 0x00, 0x0F, 0x00, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*橹5406*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0xFA, 0xAB, 0xDE, 0xCA, 0xBE, 0xAB, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x06, 0x0A, 0x02, 0x0A, 0x0F, 0x02,/*樽5407*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFF, 0x05, 0xAD, 0x15, 0xBD, 0x15, 0x2F, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x02, 0x05, 0x05, 0x0F, 0x05, 0x05,/*樨5408*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0xE8, 0x59, 0xEB, 0x7D, 0xCD, 0x4B, 0xD8, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x0E, 0x0A, 0x0E, 0x01, 0x0F,/*橘5409*/},\n        {\n\n                0xC8, 0xFF, 0x48, 0xD8, 0xB4, 0x0B, 0x50, 0xB7, 0xDA, 0x96, 0x50, 0x00, 0x0F, 0x00, 0x02, 0x02,\n                0x04, 0x05, 0x0A, 0x0F, 0x02, 0x04,/*橼5410*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0xCD, 0x55, 0x45, 0xDF, 0x45, 0x55, 0xCD, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*檑5411*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x48, 0xFE, 0x15, 0xAD, 0xB5, 0xA7, 0xAC, 0x14, 0x00, 0x00, 0x0F, 0x08, 0x07,\n                0x00, 0x0E, 0x0A, 0x0A, 0x0E, 0x00,/*檐5412*/},\n        {\n\n                0x84, 0x64, 0xFF, 0x24, 0xFA, 0x8A, 0xEA, 0xAB, 0xEA, 0x8A, 0xFA, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x06, 0x0A, 0x0E, 0x02, 0x06, 0x0A,/*檩5413*/},\n        {\n\n                0x20, 0x1F, 0x75, 0x55, 0x77, 0x80, 0x0A, 0x2E, 0x7B, 0x2E, 0x0A, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*檗5414*/},\n        {\n\n                0x88, 0x68, 0xFF, 0x28, 0x56, 0x2A, 0x5A, 0x43, 0x5A, 0x2A, 0x5E, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*檫5415*/},\n        {\n\n                0x04, 0xF5, 0x96, 0x7C, 0x96, 0xF5, 0x04, 0x10, 0xFF, 0x12, 0x14, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x08, 0x07, 0x00, 0x07, 0x08,/*猷5416*/},\n        {\n\n                0x48, 0x2A, 0x3A, 0xAF, 0xEA, 0x0A, 0x44, 0x2B, 0x12, 0x2E, 0x42, 0x0A, 0x0A, 0x0A, 0x06, 0x02,\n                0x03, 0x02, 0x06, 0x0B, 0x0A, 0x0A,/*獒5417*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x50, 0xCF, 0x41, 0x41, 0x4F, 0xD0, 0x10, 0x08, 0x04, 0x02, 0x01, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*殁5418*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x08, 0x04, 0x02, 0x01, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x08,/*殂5419*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x04, 0x4B, 0xEA, 0x6A, 0xDA, 0x4A, 0xC2, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x09, 0x04, 0x02, 0x09, 0x08, 0x07,/*殇5420*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x10, 0x48, 0x24, 0x93, 0x44, 0x08, 0x90, 0x08, 0x04, 0x02, 0x01, 0x08,\n                0x09, 0x05, 0x04, 0x02, 0x01, 0x00,/*殄5421*/},\n        {\n\n                0x62, 0x9E, 0xF2, 0x00, 0xF0, 0x17, 0x15, 0xD5, 0x15, 0x17, 0xF0, 0x08, 0x06, 0x01, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x09,/*殒5422*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x08, 0x04, 0x02, 0x01, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*殓5423*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x00, 0x2A, 0x32, 0x26, 0xAA, 0x71, 0x2D, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x01, 0x01, 0x09, 0x0F, 0x01, 0x01,/*殍5424*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x00, 0xFD, 0x96, 0xFC, 0x96, 0xFD, 0x00, 0x08, 0x04, 0x02, 0x01, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*殚5425*/},\n        {\n\n                0x82, 0x7E, 0x92, 0xF2, 0x00, 0xF2, 0x92, 0xFA, 0x46, 0x92, 0x70, 0x08, 0x04, 0x02, 0x01, 0x08,\n                0x08, 0x0A, 0x0B, 0x09, 0x08, 0x0B,/*殛5426*/},\n        {\n\n                0x62, 0x9E, 0xF2, 0x00, 0x06, 0xFA, 0x2A, 0x2B, 0xE6, 0x22, 0x26, 0x08, 0x06, 0x01, 0x00, 0x09,\n                0x05, 0x01, 0x01, 0x05, 0x09, 0x01,/*殡5427*/},\n        {\n\n                0x62, 0x9E, 0xF2, 0x00, 0x62, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0x62, 0x08, 0x06, 0x01, 0x00, 0x08,\n                0x0B, 0x0E, 0x0A, 0x0E, 0x0B, 0x08,/*殪5428*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x80, 0x72, 0x02, 0xFE, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x0F, 0x01, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*轫5429*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0xFE, 0x02, 0xFA, 0x0A, 0x8A, 0xFA, 0x02, 0x01, 0x01, 0x0F, 0x08, 0x07,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*轭5430*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x08, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x08, 0x01, 0x01, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*轱5431*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x02, 0xF2, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x01, 0x01, 0x0F, 0x00, 0x00,\n                0x03, 0x01, 0x01, 0x08, 0x0F, 0x00,/*轲5432*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x00, 0xF0, 0x90, 0x9F, 0x92, 0x92, 0xF2, 0x01, 0x01, 0x0F, 0x00, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x00, 0x01,/*轳5433*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x00, 0xFE, 0x82, 0x82, 0x82, 0xFE, 0x00, 0x01, 0x01, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x00, 0x02, 0x04, 0x08,/*轵5434*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x50, 0x4C, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x01, 0x01, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*轶5435*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x10, 0x48, 0x24, 0x93, 0x44, 0x08, 0x90, 0x01, 0x01, 0x0F, 0x00, 0x08,\n                0x09, 0x05, 0x04, 0x02, 0x01, 0x00,/*轸5436*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x00, 0x4A, 0x52, 0xFE, 0x41, 0x51, 0x49, 0x01, 0x01, 0x0F, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*轷5437*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x00, 0xBE, 0x22, 0xFA, 0x21, 0xA1, 0x20, 0x01, 0x01, 0x0F, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*轹5438*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x22, 0x92, 0x8E, 0x82, 0xA2, 0xA2, 0x9E, 0x02, 0x02, 0x0F, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*轺5439*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x20, 0xE4, 0x24, 0x04, 0xFF, 0x04, 0x05, 0x02, 0x02, 0x0F, 0x01, 0x04,\n                0x07, 0x02, 0x00, 0x03, 0x04, 0x0E,/*轼5440*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x00, 0x32, 0x2A, 0xE6, 0x22, 0x32, 0x62, 0x02, 0x02, 0x0F, 0x01, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*轾5441*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0x10, 0x28, 0x24, 0xE3, 0x24, 0x28, 0x10, 0x02, 0x02, 0x0F, 0x01, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*辁5442*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x01, 0x01, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*辂5443*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x02, 0xFE, 0x52, 0xFE, 0x02, 0xFA, 0x02, 0x01, 0x01, 0x0F, 0x00, 0x02,\n                0x03, 0x02, 0x0F, 0x01, 0x07, 0x08,/*辄5444*/},\n        {\n\n                0x28, 0x5A, 0x4F, 0xDA, 0x68, 0xC0, 0x68, 0x5A, 0x4F, 0x5A, 0x28, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x05, 0x04, 0x04,/*辇5445*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0xFE, 0x56, 0xDA, 0x72, 0x5A, 0x56, 0xFE, 0x01, 0x01, 0x0F, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x02, 0x08, 0x0F,/*辋5446*/},\n        {\n\n                0x74, 0x4F, 0xF4, 0x40, 0xAA, 0x92, 0xAE, 0x00, 0xAA, 0x92, 0xAE, 0x02, 0x02, 0x0F, 0x01, 0x0A,\n                0x04, 0x0B, 0x00, 0x0B, 0x04, 0x0B,/*辍5447*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0xC4, 0x4A, 0x55, 0xCA, 0x55, 0x4A, 0xD1, 0x01, 0x01, 0x0F, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*辎5448*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0xA2, 0x6A, 0xBA, 0xAF, 0xAA, 0x6A, 0xA2, 0x02, 0x02, 0x0F, 0x01, 0x02,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x02,/*辏5449*/},\n        {\n\n                0x64, 0x5C, 0xF7, 0x44, 0xFE, 0x2A, 0xBE, 0x2B, 0xBE, 0x2A, 0xBA, 0x02, 0x02, 0x0F, 0x09, 0x07,\n                0x00, 0x0F, 0x09, 0x07, 0x09, 0x0C,/*辘5450*/},\n        {\n\n                0x34, 0x2C, 0xF7, 0xA4, 0x95, 0x6E, 0xC4, 0x1F, 0x44, 0xEE, 0x55, 0x01, 0x01, 0x0F, 0x02, 0x09,\n                0x06, 0x01, 0x03, 0x02, 0x0F, 0x02,/*辚5451*/},\n        {\n\n                0x82, 0xFA, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAA, 0xFA, 0x82, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*軎5452*/},\n        {\n\n                0x40, 0x48, 0x48, 0x48, 0xFF, 0x44, 0x24, 0x25, 0xA6, 0x24, 0x20, 0x00, 0x08, 0x08, 0x08, 0x04,\n                0x05, 0x02, 0x05, 0x08, 0x08, 0x0E,/*戋5453*/},\n        {\n\n                0x08, 0xF4, 0x12, 0x11, 0xF2, 0x14, 0x10, 0xFF, 0x08, 0xE9, 0x0A, 0x00, 0x07, 0x08, 0x09, 0x0D,\n                0x08, 0x04, 0x02, 0x03, 0x04, 0x0E,/*戗5454*/},\n        {\n\n                0x01, 0x7D, 0x55, 0xD5, 0x57, 0x55, 0x55, 0xD5, 0x55, 0x7D, 0x01, 0x02, 0x0A, 0x0A, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x0C,/*戛5455*/},\n        {\n\n                0x00, 0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x00, 0x10, 0xFF, 0x88, 0x6A, 0x02, 0x02, 0x02, 0x0F, 0x02,\n                0x02, 0x0A, 0x04, 0x03, 0x05, 0x0E,/*戟5456*/},\n        {\n\n                0x10, 0xF7, 0x55, 0x55, 0x55, 0xF7, 0x10, 0xFF, 0x10, 0x92, 0x54, 0x04, 0x07, 0x05, 0x05, 0x05,\n                0x0F, 0x04, 0x03, 0x05, 0x08, 0x0E,/*戢5457*/},\n        {\n\n                0x80, 0x82, 0xFF, 0xAA, 0xAA, 0xFF, 0x82, 0x10, 0xFF, 0x88, 0x6A, 0x00, 0x0F, 0x0A, 0x09, 0x08,\n                0x09, 0x0A, 0x04, 0x03, 0x05, 0x0E,/*戡5458*/},\n        {\n\n                0x00, 0xDF, 0x95, 0xF5, 0x95, 0x9F, 0x00, 0x10, 0xFF, 0x88, 0x6A, 0x09, 0x0A, 0x0A, 0x0F, 0x0A,\n                0x0A, 0x08, 0x04, 0x03, 0x05, 0x0E,/*戥5459*/},\n        {\n\n                0x91, 0xAF, 0x95, 0xAD, 0x81, 0xA7, 0xBC, 0x10, 0xFF, 0x88, 0x6A, 0x0F, 0x08, 0x0F, 0x08, 0x07,\n                0x04, 0x0F, 0x04, 0x03, 0x05, 0x0E,/*戤5460*/},\n        {\n\n                0x24, 0xA9, 0xBF, 0xA1, 0xBF, 0xA9, 0x24, 0x10, 0xFF, 0x88, 0x6A, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x08, 0x04, 0x03, 0x05, 0x0E,/*戬5461*/},\n        {\n\n                0x9C, 0x90, 0xFC, 0x04, 0xF4, 0x54, 0x74, 0xD4, 0x0F, 0xF4, 0x46, 0x03, 0x08, 0x07, 0x00, 0x07,\n                0x05, 0x07, 0x0D, 0x04, 0x07, 0x0C,/*臧5462*/},\n        {\n\n                0xFE, 0x02, 0x9A, 0x62, 0x9A, 0x00, 0xE2, 0x9E, 0xF2, 0x02, 0x00, 0x07, 0x04, 0x05, 0x04, 0x05,\n                0x00, 0x0F, 0x08, 0x07, 0x08, 0x0E,/*瓯5463*/},\n        {\n\n                0x48, 0x44, 0x53, 0x64, 0xC8, 0x00, 0xE2, 0x9E, 0xF2, 0x02, 0x00, 0x00, 0x02, 0x04, 0x0B, 0x00,\n                0x00, 0x0F, 0x08, 0x07, 0x08, 0x0E,/*瓴5464*/},\n        {\n\n                0xAA, 0xB2, 0xB3, 0xAA, 0x20, 0xC2, 0xBE, 0x12, 0xF2, 0x02, 0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x0F, 0x04, 0x01, 0x07, 0x08, 0x0E,/*瓿5465*/},\n        {\n\n                0x8A, 0xBA, 0xEA, 0xAF, 0xEA, 0xBA, 0x8A, 0xC0, 0xD4, 0xAA, 0x95, 0x00, 0x0C, 0x0B, 0x0A, 0x06,\n                0x0A, 0x02, 0x06, 0x08, 0x08, 0x0C,/*甏5466*/},\n        {\n\n                0x3E, 0xAB, 0xBE, 0xAB, 0x3E, 0x00, 0xE2, 0x9E, 0xF2, 0x02, 0x00, 0x00, 0x0F, 0x0A, 0x0F, 0x00,\n                0x00, 0x0F, 0x08, 0x07, 0x08, 0x0E,/*甑5467*/},\n        {\n\n                0xA0, 0x9F, 0xF5, 0xD5, 0xF7, 0x80, 0x8A, 0xAE, 0xFB, 0xAE, 0x8A, 0x00, 0x0C, 0x0B, 0x0A, 0x06,\n                0x0A, 0x02, 0x06, 0x08, 0x08, 0x0C,/*甓5468*/},\n        {\n\n                0x00, 0x20, 0x60, 0xA0, 0x20, 0x3F, 0x24, 0x24, 0xA4, 0x64, 0x00, 0x08, 0x08, 0x08, 0x04, 0x05,\n                0x02, 0x02, 0x05, 0x04, 0x08, 0x08,/*攴5469*/},\n        {\n\n                0x40, 0xA4, 0x94, 0x8C, 0x87, 0x84, 0x84, 0x9C, 0xA0, 0xA0, 0x30, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*旮5470*/},\n        {\n\n                0x00, 0x9F, 0x95, 0x95, 0xF5, 0x95, 0x95, 0x95, 0x15, 0x1F, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*旯5471*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x40, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x07, 0x02, 0x02, 0x07, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*旰5472*/},\n        {\n\n                0x00, 0x5F, 0x55, 0x55, 0x55, 0xD5, 0x55, 0x55, 0x55, 0x5F, 0x00, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x01, 0x03, 0x05, 0x05, 0x09, 0x09,/*昊5473*/},\n        {\n\n                0x00, 0x5F, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x5F, 0x00, 0x01, 0x09, 0x0D, 0x0B, 0x09,\n                0x09, 0x09, 0x09, 0x0D, 0x09, 0x01,/*昙5474*/},\n        {\n\n                0x40, 0x5F, 0x55, 0x55, 0xD5, 0xF5, 0xD5, 0x55, 0x55, 0x5F, 0x40, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*杲5475*/},\n        {\n\n                0x00, 0xDF, 0x55, 0x55, 0x55, 0x55, 0xD5, 0x55, 0x55, 0x5F, 0x40, 0x08, 0x07, 0x08, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*昃5476*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x07, 0x02, 0x02, 0x0B, 0x04,\n                0x03, 0x00, 0x00, 0x0F, 0x00, 0x00,/*昕5477*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x10, 0x08, 0x17, 0x24, 0x84, 0x44, 0xFC, 0x07, 0x02, 0x02, 0x07, 0x00,\n                0x02, 0x02, 0x01, 0x08, 0x08, 0x07,/*昀5478*/},\n        {\n\n                0x00, 0x1F, 0xD5, 0x15, 0x15, 0xF5, 0x15, 0x15, 0x95, 0x5F, 0x00, 0x08, 0x09, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*炅5479*/},\n        {\n\n                0x00, 0x9F, 0x55, 0x75, 0x55, 0xD5, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x01, 0x06, 0x04, 0x06, 0x05,\n                0x04, 0x05, 0x0A, 0x08, 0x08, 0x07,/*曷5480*/},\n        {\n\n                0x48, 0x44, 0xAB, 0x92, 0xAA, 0xA6, 0xA0, 0xBF, 0xA0, 0xA2, 0x2C, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*昝5481*/},\n        {\n\n                0xC0, 0x5F, 0x35, 0x35, 0xD5, 0x15, 0xD5, 0x55, 0x55, 0x5F, 0xC0, 0x07, 0x04, 0x0A, 0x05, 0x03,\n                0x00, 0x0F, 0x00, 0x00, 0x04, 0x07,/*昴5482*/},\n        {\n\n                0x00, 0x9F, 0x95, 0x95, 0xB5, 0xD5, 0x95, 0x95, 0x95, 0x9F, 0x00, 0x08, 0x08, 0x0A, 0x0C, 0x08,\n                0x08, 0x08, 0x0C, 0x0A, 0x08, 0x08,/*昱5483*/},\n        {\n\n                0x40, 0xC8, 0x08, 0xF9, 0x42, 0xA0, 0x10, 0xFE, 0x12, 0x12, 0xFE, 0x04, 0x03, 0x08, 0x0F, 0x00,\n                0x01, 0x02, 0x05, 0x09, 0x09, 0x09,/*昶5484*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x00, 0xFE, 0x12, 0xD2, 0x12, 0x92, 0x5E, 0x07, 0x02, 0x02, 0x07, 0x08,\n                0x07, 0x00, 0x07, 0x09, 0x08, 0x0E,/*昵5485*/},\n        {\n\n                0x48, 0x48, 0xAA, 0xAA, 0xBA, 0xCF, 0xEA, 0xDC, 0xCA, 0x49, 0x68, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*耆5486*/},\n        {\n\n                0x00, 0xDF, 0x55, 0x55, 0x55, 0x55, 0x55, 0xF5, 0x55, 0x7F, 0xC0, 0x08, 0x07, 0x01, 0x01, 0x05,\n                0x07, 0x08, 0x05, 0x02, 0x05, 0x0E,/*晟5487*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x08, 0x04, 0x7E, 0x21, 0x90, 0x3F, 0x44, 0x72, 0x07, 0x02, 0x07, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*晔5488*/},\n        {\n\n                0x00, 0x5F, 0x95, 0x15, 0xF5, 0x15, 0xF5, 0x15, 0x95, 0x5F, 0x00, 0x08, 0x09, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x09, 0x0C,/*晁5489*/},\n        {\n\n                0xC0, 0x5F, 0x55, 0x55, 0xD5, 0x75, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x08, 0x09, 0x09, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x00,/*晏5490*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0x16, 0xD2, 0xB2, 0xDA, 0x92, 0x92, 0x06, 0x07, 0x02, 0x07, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*晖5491*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0xF4, 0x54, 0x54, 0xFF, 0x54, 0x55, 0xF6, 0x07, 0x02, 0x07, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*晡5492*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x08, 0x24, 0x22, 0x29, 0xB2, 0x64, 0x08, 0x08, 0x07, 0x02, 0x07, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*晗5493*/},\n        {\n\n                0x80, 0x5F, 0x75, 0x55, 0xD5, 0x15, 0x15, 0xF5, 0x55, 0x9F, 0x00, 0x04, 0x05, 0x0E, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0B, 0x0E, 0x02, 0x02,/*晷5494*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0x06, 0xEA, 0xAA, 0xAB, 0xAA, 0xEA, 0x06, 0x07, 0x02, 0x07, 0x00, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*暄5495*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0x4A, 0x32, 0x4E, 0xC0, 0x4F, 0x32, 0x49, 0x07, 0x02, 0x07, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*暌5496*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x30, 0x56, 0xDA, 0x76, 0x5A, 0x51, 0x59, 0x35, 0x07, 0x02, 0x07, 0x04, 0x02,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*暧5497*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0x03, 0x7D, 0x55, 0xD5, 0x55, 0x7D, 0x03, 0x07, 0x02, 0x07, 0x00, 0x09,\n                0x05, 0x01, 0x01, 0x01, 0x05, 0x09,/*暝5498*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0xBA, 0xAB, 0xBA, 0x10, 0xEF, 0x08, 0xF8, 0x07, 0x02, 0x07, 0x00, 0x0A,\n                0x0E, 0x03, 0x0A, 0x05, 0x02, 0x0D,/*暾5499*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0xF4, 0x55, 0x15, 0xFF, 0x15, 0x55, 0xF4, 0x07, 0x02, 0x07, 0x00, 0x0D,\n                0x05, 0x0D, 0x07, 0x0D, 0x05, 0x0D,/*曛5500*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0x2B, 0xF5, 0xAF, 0xA0, 0xEB, 0xB5, 0xAF, 0x07, 0x02, 0x07, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*曜5501*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x00, 0xA2, 0xEA, 0xAB, 0xBE, 0xEB, 0xAA, 0xE2, 0x07, 0x02, 0x07, 0x01, 0x02,\n                0x0B, 0x06, 0x08, 0x07, 0x0A, 0x0D,/*曦5502*/},\n        {\n\n                0x20, 0xEF, 0xA9, 0xA9, 0xE9, 0x3B, 0xED, 0xA9, 0xA9, 0xEF, 0x20, 0x08, 0x0A, 0x06, 0x0F, 0x0A,\n                0x02, 0x02, 0x07, 0x0A, 0x0A, 0x08,/*曩5503*/},\n        {\n\n                0x10, 0x92, 0xBA, 0x92, 0x92, 0x97, 0x92, 0x92, 0xBA, 0x92, 0x10, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*贲5504*/},\n        {\n\n                0x02, 0xBF, 0xA2, 0xA2, 0xAF, 0xAA, 0xAA, 0xAA, 0xAF, 0xA2, 0x02, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*贳5505*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x7E, 0xC2, 0xC2, 0x7E, 0x00, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x08, 0x06, 0x01, 0x07, 0x08, 0x0C,/*贶5506*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x10, 0xDC, 0x53, 0x50, 0xD8, 0x30, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*贻5507*/},\n        {\n\n                0x0A, 0xAA, 0xBF, 0x8A, 0xA0, 0x9A, 0x8F, 0x92, 0x8E, 0x90, 0x38, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*贽5508*/},\n        {\n\n                0x10, 0xDE, 0x50, 0x4F, 0x4A, 0xCA, 0x40, 0x4F, 0x54, 0xD2, 0x19, 0x08, 0x09, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x02, 0x04, 0x05, 0x08,/*赀5509*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x09, 0x04, 0x02, 0x05, 0x08,/*赅5510*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x80, 0x7E, 0x92, 0x32, 0xD2, 0x1E, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x00, 0x02, 0x04, 0x09, 0x00, 0x01,/*赆5511*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0xFE, 0xE2, 0x2A, 0xEA, 0x2A, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x07, 0x00, 0x0F, 0x04, 0x03, 0x05,/*赈5512*/},\n        {\n\n                0x90, 0x52, 0xB6, 0x9A, 0x92, 0xBF, 0x92, 0x9A, 0xB6, 0x52, 0x90, 0x08, 0x08, 0x0B, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x0B, 0x08, 0x00,/*赉5513*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x28, 0xC8, 0xFF, 0x68, 0x89, 0x4A, 0x09, 0x04, 0x03, 0x04, 0x0B,\n                0x01, 0x08, 0x0F, 0x00, 0x01, 0x02,/*赇5514*/},\n        {\n\n                0x60, 0xAA, 0xA6, 0xAA, 0xA2, 0xBF, 0xA2, 0xAA, 0xA6, 0xAA, 0x60, 0x08, 0x0B, 0x08, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x04, 0x0B, 0x08,/*赍5515*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x08, 0xA6, 0x10, 0xCF, 0x14, 0xA2, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x02, 0x09, 0x04, 0x03, 0x05, 0x08,/*赕5516*/},\n        {\n\n                0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0xFA, 0x2A, 0xFF, 0x2A, 0xFB, 0x09, 0x04, 0x03, 0x04, 0x09,\n                0x02, 0x06, 0x02, 0x0A, 0x0F, 0x02,/*赙5517*/},\n        {\n\n                0xC0, 0x40, 0x7F, 0x48, 0xC8, 0x00, 0xFE, 0x02, 0xF2, 0x02, 0xFE, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x08, 0x04, 0x03, 0x06, 0x08, 0x0E,/*觇5518*/},\n        {\n\n                0xAE, 0xA8, 0xAF, 0xA8, 0xEE, 0x00, 0xFE, 0x02, 0xF2, 0x02, 0xFE, 0x0F, 0x08, 0x04, 0x04, 0x02,\n                0x08, 0x04, 0x03, 0x06, 0x08, 0x0E,/*觊5519*/},\n        {\n\n                0x80, 0x72, 0x82, 0xFE, 0x82, 0x72, 0x80, 0x7E, 0xC2, 0x02, 0x7E, 0x08, 0x08, 0x08, 0x07, 0x04,\n                0x04, 0x08, 0x04, 0x07, 0x08, 0x0E,/*觋5520*/},\n        {\n\n                0x4A, 0xAA, 0x4F, 0xEA, 0x1A, 0x00, 0xFE, 0x02, 0xF2, 0x02, 0xFE, 0x09, 0x05, 0x03, 0x05, 0x09,\n                0x08, 0x04, 0x03, 0x06, 0x08, 0x0E,/*觌5521*/},\n        {\n\n                0xE8, 0xA4, 0xEA, 0x09, 0xCA, 0x04, 0xE8, 0x7E, 0xC2, 0x02, 0x7E, 0x0F, 0x02, 0x0F, 0x00, 0x03,\n                0x08, 0x0F, 0x04, 0x07, 0x08, 0x0E,/*觎5522*/},\n        {\n\n                0x08, 0xEA, 0xAF, 0xFA, 0xAF, 0xEA, 0x08, 0x7E, 0xC2, 0x02, 0x7E, 0x02, 0x0F, 0x02, 0x03, 0x0A,\n                0x0F, 0x0A, 0x04, 0x07, 0x08, 0x0E,/*觏5523*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x00, 0xFE, 0x02, 0xF2, 0x02, 0xFE, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,\n                0x08, 0x04, 0x03, 0x06, 0x08, 0x0E,/*觐5524*/},\n        {\n\n                0xFC, 0x24, 0xBF, 0x55, 0xD5, 0x6D, 0x00, 0x7E, 0xC2, 0x02, 0x7E, 0x07, 0x0A, 0x0F, 0x08, 0x0F,\n                0x0A, 0x09, 0x04, 0x07, 0x08, 0x0E,/*觑5525*/},\n        {\n\n                0x08, 0x04, 0xDE, 0x81, 0x88, 0xC8, 0x8F, 0x88, 0x95, 0xA6, 0x34, 0x02, 0x03, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*牮5526*/},\n        {\n\n                0x9D, 0x95, 0xF7, 0x00, 0x5C, 0xD7, 0x55, 0x7D, 0x55, 0x77, 0xDC, 0x04, 0x06, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x04,/*犟5527*/},\n        {\n\n                0x90, 0x8E, 0x88, 0xFF, 0x48, 0x00, 0xFF, 0x20, 0x10, 0x08, 0x04, 0x00, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*牝5528*/},\n        {\n\n                0x90, 0x8E, 0x88, 0xFF, 0x48, 0x92, 0x92, 0xFE, 0x49, 0x49, 0x40, 0x00, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*牦5529*/},\n        {\n\n                0x90, 0x8E, 0x88, 0xFF, 0x48, 0x00, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x00, 0x00, 0x00, 0x0F, 0x00,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*牯5530*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x21, 0xA5, 0xBD, 0xA7, 0xA5, 0xBD, 0x21, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*牾5531*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x28, 0xA6, 0xA4, 0xBF, 0xA4, 0xA4, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*牿5532*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x10, 0xDA, 0x56, 0xD3, 0x16, 0xFA, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x02, 0x03, 0x08, 0x0F, 0x00,/*犄5533*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x00, 0xFF, 0x55, 0x55, 0x55, 0xFF, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x01,\n                0x09, 0x05, 0x01, 0x05, 0x09, 0x01,/*犋5534*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x64, 0xDC, 0x88, 0xAA, 0xFF, 0xAA, 0xBE, 0x00, 0x00, 0x0F, 0x00, 0x0A,\n                0x07, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*犍5535*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0xFE, 0x2A, 0xEA, 0x2B, 0xEA, 0x2A, 0xEE, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*犏5536*/},\n        {\n\n                0x9C, 0x88, 0xFF, 0x48, 0x82, 0xBA, 0xAA, 0xAB, 0xAA, 0xBA, 0x82, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x0E, 0x0A, 0x0E, 0x00, 0x0F,/*犒5537*/},\n        {\n\n                0x22, 0xAA, 0xFF, 0xAA, 0xA2, 0xC0, 0xA2, 0x9E, 0xC2, 0x42, 0x3E, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*挈5538*/},\n        {\n\n                0x22, 0x14, 0x81, 0xA2, 0xA8, 0xA6, 0xA0, 0x5F, 0x10, 0x12, 0x04, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*挲5539*/},\n        {\n\n                0x92, 0xFE, 0x91, 0x28, 0xE6, 0x20, 0xE7, 0x08, 0x92, 0xFE, 0x91, 0x08, 0x07, 0x00, 0x08, 0x07,\n                0x08, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*掰5540*/},\n        {\n\n                0x92, 0xFE, 0x91, 0x08, 0xD4, 0x53, 0xD4, 0x08, 0x92, 0xFE, 0x91, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x04, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*搿5541*/},\n        {\n\n                0x20, 0x9F, 0xF5, 0xD5, 0xF7, 0x80, 0x8A, 0xAE, 0xFB, 0x2E, 0x0A, 0x02, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*擘5542*/},\n        {\n\n                0x48, 0x48, 0x2A, 0x2A, 0x3A, 0xCF, 0xEA, 0xDC, 0x4A, 0x49, 0x68, 0x04, 0x05, 0x05, 0x05, 0x07,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x08, 0x0C,/*耄5543*/},\n        {\n\n                0x12, 0x12, 0xFE, 0x89, 0x40, 0x36, 0x25, 0xFC, 0x24, 0x26, 0x0C, 0x01, 0x01, 0x07, 0x08, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x0D,/*毪5544*/},\n        {\n\n                0x20, 0x2A, 0x2A, 0xAA, 0x3E, 0x55, 0x55, 0x55, 0xD0, 0xC0, 0x60, 0x05, 0x05, 0x0F, 0x0A, 0x02,\n                0x04, 0x05, 0x07, 0x0A, 0x0A, 0x0C,/*毳5545*/},\n        {\n\n                0x12, 0xFE, 0x89, 0x32, 0xEE, 0x08, 0xAA, 0xFF, 0xAA, 0xBE, 0x08, 0x01, 0x07, 0x08, 0x0D, 0x0B,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0C,/*毽5546*/},\n        {\n\n                0x54, 0xB6, 0x5D, 0xB6, 0x54, 0x00, 0x92, 0x92, 0xFE, 0x49, 0x49, 0x08, 0x0A, 0x05, 0x04, 0x02,\n                0x00, 0x00, 0x00, 0x07, 0x08, 0x0E,/*毵5547*/},\n        {\n\n                0xE8, 0xA4, 0xEA, 0x09, 0xCA, 0x04, 0xE8, 0x92, 0xFE, 0x49, 0x49, 0x0F, 0x02, 0x0F, 0x00, 0x03,\n                0x08, 0x0F, 0x00, 0x07, 0x08, 0x0E,/*毹5548*/},\n        {\n\n                0xFD, 0x06, 0x74, 0x57, 0x74, 0x86, 0xFD, 0xD4, 0x23, 0x5E, 0x82, 0x04, 0x05, 0x05, 0x05, 0x07,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x08, 0x0C,/*氅5549*/},\n        {\n\n                0x12, 0xFE, 0x89, 0x84, 0xFA, 0xAB, 0xFA, 0xAE, 0xA8, 0xF8, 0x80, 0x01, 0x07, 0x08, 0x08, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x08, 0x0C,/*氇5550*/},\n        {\n\n                0x12, 0xFE, 0x89, 0x00, 0x2A, 0xE3, 0xBE, 0xA2, 0xBE, 0xE3, 0x2A, 0x01, 0x07, 0x08, 0x08, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*氆5551*/},\n        {\n\n                0x9F, 0xD5, 0x7F, 0x40, 0xFF, 0x55, 0x5F, 0x92, 0xFE, 0x49, 0x49, 0x00, 0x0F, 0x05, 0x05, 0x07,\n                0x05, 0x05, 0x00, 0x07, 0x08, 0x0E,/*氍5552*/},\n        {\n\n                0x08, 0x24, 0x2B, 0xAA, 0x2A, 0x2A, 0x2A, 0x2A, 0xEA, 0x0A, 0x02, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x0E,/*氕5553*/},\n        {\n\n                0x08, 0x24, 0xAB, 0x2A, 0x2A, 0xAA, 0x2A, 0x2A, 0xEA, 0x0A, 0x02, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x03, 0x04, 0x0E,/*氘5554*/},\n        {\n\n                0x88, 0x24, 0x2B, 0xEA, 0x2A, 0x2A, 0xAA, 0x2A, 0xEA, 0x0A, 0x02, 0x07, 0x04, 0x04, 0x07, 0x04,\n                0x04, 0x0F, 0x00, 0x03, 0x04, 0x0E,/*氙5555*/},\n        {\n\n                0x08, 0x24, 0xAB, 0x2A, 0xAA, 0x2A, 0xAA, 0x2A, 0xEA, 0x0A, 0x02, 0x00, 0x08, 0x07, 0x00, 0x07,\n                0x00, 0x0F, 0x00, 0x03, 0x04, 0x0E,/*氚5556*/},\n        {\n\n                0x84, 0x52, 0xF5, 0x55, 0x55, 0x55, 0xD5, 0x15, 0xF5, 0x01, 0x00, 0x02, 0x02, 0x06, 0x09, 0x03,\n                0x05, 0x02, 0x02, 0x03, 0x04, 0x0E,/*氡5557*/},\n        {\n\n                0x88, 0xA4, 0xAB, 0xAA, 0xAA, 0xAA, 0xAA, 0x2A, 0xEA, 0x0A, 0x02, 0x0A, 0x08, 0x0F, 0x08, 0x0F,\n                0x08, 0x0A, 0x08, 0x03, 0x04, 0x0E,/*氩5558*/},\n        {\n\n                0xC4, 0x52, 0x55, 0xD5, 0x55, 0x55, 0xD5, 0x15, 0xF5, 0x01, 0x00, 0x0F, 0x08, 0x0D, 0x0B, 0x0D,\n                0x08, 0x0F, 0x00, 0x03, 0x04, 0x0E,/*氤5559*/},\n        {\n\n                0x14, 0xD2, 0x55, 0x7D, 0x55, 0xD5, 0x15, 0x05, 0xFD, 0x01, 0x01, 0x08, 0x05, 0x03, 0x01, 0x07,\n                0x09, 0x0C, 0x00, 0x03, 0x04, 0x0E,/*氪5560*/},\n        {\n\n                0x04, 0x02, 0xF5, 0x55, 0x55, 0x55, 0xF5, 0x05, 0xFD, 0x01, 0x01, 0x08, 0x0F, 0x09, 0x0F, 0x09,\n                0x0F, 0x09, 0x0F, 0x0B, 0x04, 0x0E,/*氲5561*/},\n        {\n\n                0x40, 0x20, 0x10, 0x6C, 0x8B, 0x08, 0x88, 0x48, 0x38, 0x08, 0x08, 0x08, 0x08, 0x04, 0x04, 0x02,\n                0x01, 0x02, 0x04, 0x04, 0x08, 0x08,/*攵5562*/},\n        {\n\n                0x00, 0xF4, 0x94, 0xFF, 0x94, 0xF4, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x04, 0x02, 0x01, 0x0F, 0x01,\n                0x02, 0x08, 0x05, 0x02, 0x05, 0x08,/*敕5563*/},\n        {\n\n                0x80, 0xBE, 0xEB, 0xAA, 0xBE, 0x80, 0x10, 0xEF, 0x08, 0xF8, 0x08, 0x08, 0x07, 0x02, 0x0A, 0x0E,\n                0x00, 0x08, 0x05, 0x02, 0x05, 0x08,/*敫5564*/},\n        {\n\n                0x00, 0xFE, 0x90, 0x9F, 0x10, 0x4A, 0xAA, 0x4F, 0xEA, 0x0A, 0x18, 0x08, 0x07, 0x00, 0x0F, 0x09,\n                0x09, 0x05, 0x03, 0x01, 0x05, 0x09,/*牍5565*/},\n        {\n\n                0xFE, 0x90, 0x9F, 0x10, 0x04, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x07, 0x00, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*牒5566*/},\n        {\n\n                0xFE, 0x90, 0x9F, 0x10, 0xFE, 0xAA, 0xAA, 0xFB, 0xAA, 0xBA, 0xAE, 0x07, 0x00, 0x0F, 0x02, 0x01,\n                0x0F, 0x02, 0x07, 0x02, 0x0A, 0x0F,/*牖5567*/},\n        {\n\n                0x40, 0x52, 0x56, 0xDA, 0x72, 0x56, 0x59, 0x51, 0x59, 0x55, 0x40, 0x04, 0x02, 0x09, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x0B, 0x08, 0x08,/*爰5568*/},\n        {\n\n                0x4A, 0x52, 0x46, 0xE9, 0x45, 0xF8, 0x48, 0x7F, 0xAA, 0xAA, 0xD8, 0x01, 0x02, 0x08, 0x0F, 0x02,\n                0x09, 0x06, 0x02, 0x06, 0x08, 0x0C,/*虢5569*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x00, 0x01, 0x08, 0x08, 0x0F,/*刖5570*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x10, 0xD2, 0xB2, 0x92, 0x92, 0x92, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*肟5571*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x88, 0x44, 0x22, 0x11, 0x08, 0x07, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x08, 0x04, 0x02, 0x01,/*肜5572*/},\n        {\n\n                0x02, 0xEE, 0xAA, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xEA, 0x02, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*肓5573*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x88, 0xFF, 0x88, 0x88, 0xFF, 0x88, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x04, 0x03, 0x00, 0x00, 0x0F, 0x00,/*肼5574*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x12, 0xF2, 0x12, 0xF2, 0x12, 0x10, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*朊5575*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x08, 0xC8, 0x3F, 0xC8, 0x08, 0x08, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x06, 0x01, 0x06, 0x01, 0x06, 0x08,/*肽5576*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x08, 0xE8, 0x1F, 0x88, 0x68, 0x08, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x07, 0x00, 0x06, 0x05, 0x04, 0x0E,/*肱5577*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xF4, 0x84, 0xFF, 0x84, 0xF4, 0x04, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*肫5578*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFC, 0x44, 0x3F, 0x44, 0x84, 0xFC, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x08, 0x0F,/*肭5579*/},\n        {\n\n                0x88, 0x48, 0xED, 0xBA, 0xAA, 0xAE, 0xAA, 0xAA, 0xAD, 0xE8, 0x08, 0x00, 0x00, 0x0F, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*肴5580*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x20, 0x18, 0x07, 0xE4, 0x04, 0x14, 0x0C, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*肷5581*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x08, 0x08, 0xFF, 0x08, 0xF9, 0x8A, 0x48, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x03, 0x04, 0x02, 0x07, 0x08, 0x0E,/*胧5582*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x04, 0x64, 0x5C, 0xF7, 0x44, 0x44, 0x44, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x03, 0x08, 0x0F, 0x00, 0x01, 0x06,/*胨5583*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x20, 0x20, 0xFF, 0xA4, 0x24, 0x24, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x00, 0x0F, 0x00, 0x01, 0x02,/*胩5584*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0xF0, 0x90, 0x9F, 0x92, 0xF2, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x08, 0x07, 0x00, 0x00, 0x00, 0x01,/*胪5585*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0xFE, 0x92, 0xFE, 0x92, 0xFE, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x01, 0x00, 0x0F, 0x00, 0x01,/*胛5586*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0xFC, 0x24, 0xFF, 0x24, 0xFC, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x03, 0x01, 0x0F, 0x01, 0x03,/*胂5587*/},\n        {\n\n                0x3E, 0xEA, 0xAA, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xAA, 0xEA, 0x3E, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*胄5588*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*胙5589*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x01, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x07, 0x00, 0x0F, 0x0A, 0x0C, 0x03,/*胍5590*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x10, 0x48, 0x24, 0x93, 0x44, 0x08, 0x90, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x09, 0x05, 0x04, 0x02, 0x01, 0x00,/*胗5591*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x92, 0xFE, 0x10, 0xE8, 0x27, 0xE4, 0x04, 0xFC, 0x08, 0x07, 0x00, 0x08, 0x0F,\n                0x00, 0x03, 0x01, 0x09, 0x08, 0x07,/*朐5592*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x04, 0x08, 0x03, 0x04, 0x0E,/*胝5593*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x40, 0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*胫5594*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x24, 0x28, 0xE0, 0x3F, 0xE0, 0x28, 0x24, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*胱5595*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x02, 0xEA, 0x2A, 0xEA, 0x02, 0xFE, 0x07, 0x08, 0x0F, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*胴5596*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0xA2, 0x7A, 0xA2, 0x22, 0xFE, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x05, 0x0F,/*胭5597*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x88, 0x94, 0x92, 0x91, 0x92, 0x94, 0x88, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*脍5598*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x40, 0x51, 0x4A, 0xE4, 0x4A, 0x51, 0x40, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x01, 0x02,/*脎5599*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x09, 0x09, 0x04, 0x02, 0x05, 0x08,/*胲5600*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x89, 0xFA, 0x88, 0x88, 0xFA, 0x89, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*胼5601*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x40, 0x49, 0x4A, 0xF8, 0x4A, 0x49, 0x40, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*朕5602*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x24, 0x28, 0xA0, 0xFF, 0xA0, 0x28, 0x24, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*脒5603*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x92, 0x4A, 0x26, 0xFA, 0xA2, 0x12, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x04, 0x0A, 0x09, 0x07, 0x00, 0x01,/*豚5604*/},\n        {\n\n                0xFF, 0x49, 0xFF, 0x00, 0xE0, 0x2F, 0x29, 0xF9, 0x29, 0x2F, 0xE0, 0x07, 0x08, 0x0F, 0x00, 0x0F,\n                0x02, 0x01, 0x00, 0x01, 0x0A, 0x0F,/*脶5605*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x20, 0x1C, 0x20, 0xFF, 0x20, 0x1C, 0x20, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*脞5606*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x2A, 0x32, 0x26, 0xAA, 0x71, 0x2D, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x01, 0x01, 0x09, 0x0F, 0x01, 0x01,/*脬5607*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x4C, 0xD4, 0x55, 0xD6, 0x54, 0x4C, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*脘5608*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x4A, 0xCA, 0xFA, 0x8A, 0x4E, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x07, 0x02, 0x09, 0x0F, 0x00, 0x03,/*脲5609*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0x22, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*腈5610*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x12, 0xEA, 0xA6, 0xF3, 0xA6, 0xEA, 0x12, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x07, 0x02, 0x07, 0x0A, 0x0B, 0x0C,/*腌5611*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x24, 0x24, 0xFF, 0x00, 0xFF, 0x24, 0x24, 0x08, 0x07, 0x08, 0x0F, 0x01,\n                0x01, 0x0F, 0x00, 0x0F, 0x01, 0x01,/*腓5612*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFC, 0x92, 0x80, 0xFF, 0x80, 0x92, 0xFE, 0x07, 0x08, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*腴5613*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0x86, 0x92, 0x93, 0x92, 0x92, 0x86, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*腙5614*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x00, 0xAC, 0x24, 0xE5, 0x26, 0x24, 0x2C, 0x08, 0x07, 0x08, 0x0F, 0x04,\n                0x03, 0x04, 0x0F, 0x09, 0x09, 0x08,/*腚5615*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x64, 0xDC, 0x88, 0xAA, 0xFF, 0xAA, 0xBE, 0x07, 0x08, 0x0F, 0x00, 0x0A,\n                0x07, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*腱5616*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0xA2, 0x6A, 0xBA, 0xAF, 0xAA, 0x6A, 0xA2, 0x08, 0x07, 0x08, 0x0F, 0x02,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x02,/*腠5617*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFA, 0x0A, 0x5A, 0xEF, 0x5A, 0x0A, 0xFA, 0x07, 0x08, 0x0F, 0x00, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*腩5618*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xF2, 0x12, 0xFA, 0x56, 0xF2, 0x12, 0xF2, 0x07, 0x08, 0x0F, 0x00, 0x0F,\n                0x04, 0x07, 0x05, 0x07, 0x04, 0x0F,/*腼5619*/},\n        {\n\n                0xFF, 0x49, 0xFF, 0x00, 0xC0, 0x5F, 0xD5, 0x55, 0xD5, 0x5F, 0xC0, 0x07, 0x08, 0x0F, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*腽5620*/},\n        {\n\n                0xFF, 0x49, 0xFF, 0x00, 0x47, 0xD5, 0x57, 0x50, 0x57, 0x55, 0x47, 0x07, 0x08, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*腭5621*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xE8, 0xA4, 0xEA, 0x09, 0xCA, 0x04, 0xE8, 0x07, 0x08, 0x0F, 0x00, 0x0F,\n                0x02, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*腧5622*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x20, 0xAA, 0x68, 0x3F, 0x68, 0xAA, 0x20, 0x08, 0x07, 0x08, 0x0F, 0x09,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x09,/*塍5623*/},\n        {\n\n                0x00, 0xFF, 0x49, 0xFF, 0x50, 0x35, 0x1C, 0xD7, 0x14, 0x35, 0x50, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x09,/*媵5624*/},\n        {\n\n                0xFF, 0x49, 0xFF, 0x00, 0xC1, 0x5D, 0xD5, 0x55, 0xD5, 0x5D, 0xC1, 0x07, 0x08, 0x0F, 0x00, 0x0F,\n                0x00, 0x02, 0x0F, 0x02, 0x08, 0x0F,/*膈5625*/},\n        {\n\n                0x22, 0x9E, 0xAB, 0xAA, 0x9A, 0x84, 0xBB, 0xAA, 0x9A, 0xA6, 0x52, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*膂5626*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x06, 0xFA, 0x2A, 0x2B, 0xE6, 0x22, 0x26, 0x07, 0x08, 0x0F, 0x00, 0x09,\n                0x05, 0x01, 0x01, 0x05, 0x09, 0x01,/*膑5627*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0xA0, 0x6A, 0x38, 0xAF, 0x28, 0x6A, 0xA0, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x05, 0x0A, 0x0F, 0x02, 0x05, 0x00,/*滕5628*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x06, 0xDA, 0xB6, 0x93, 0x96, 0xDA, 0x06, 0x07, 0x08, 0x0F, 0x00, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*膣5629*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x18, 0x6A, 0x2E, 0xFB, 0x2E, 0x6A, 0x18, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*膪5630*/},\n        {\n\n                0xFF, 0x49, 0xFF, 0x02, 0xEA, 0xAF, 0xEA, 0x02, 0xE4, 0x3F, 0xE4, 0x07, 0x08, 0x0F, 0x08, 0x0A,\n                0x04, 0x06, 0x0C, 0x05, 0x02, 0x0D,/*臌5631*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x9A, 0xAF, 0x6A, 0xAA, 0x2A, 0xAF, 0x5A, 0x07, 0x08, 0x0F, 0x00, 0x0A,\n                0x0A, 0x05, 0x0A, 0x0F, 0x02, 0x04,/*朦5632*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x70, 0x57, 0x75, 0x85, 0x75, 0x57, 0x70, 0x07, 0x08, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*臊5633*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFA, 0x8A, 0xBA, 0xAB, 0xBA, 0x8A, 0xFA, 0x07, 0x08, 0x0F, 0x00, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x08,/*膻5634*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFE, 0xAA, 0xFE, 0xAB, 0xFA, 0xAE, 0xEA, 0x07, 0x08, 0x0F, 0x04, 0x0B,\n                0x06, 0x0F, 0x02, 0x0F, 0x06, 0x0B,/*臁5635*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x95, 0x6E, 0xC4, 0x1F, 0x44, 0xEE, 0x55, 0x07, 0x08, 0x0F, 0x02, 0x09,\n                0x06, 0x01, 0x03, 0x02, 0x0F, 0x02,/*膦5636*/},\n        {\n\n                0x00, 0x30, 0x2F, 0x24, 0x24, 0xE4, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x02, 0x02, 0x01, 0x09, 0x08,\n                0x07, 0x08, 0x06, 0x01, 0x06, 0x08,/*欤5637*/},\n        {\n\n                0x90, 0xD5, 0xBA, 0xD2, 0x95, 0x90, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x00, 0x07, 0x00, 0x0F, 0x04,\n                0x07, 0x08, 0x06, 0x01, 0x06, 0x08,/*欷5638*/},\n        {\n\n                0x10, 0xDA, 0x56, 0xD3, 0x16, 0xFA, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x00, 0x07, 0x02, 0x03, 0x08,\n                0x0F, 0x08, 0x06, 0x01, 0x06, 0x08,/*欹5639*/},\n        {\n\n                0xCA, 0x2A, 0xFE, 0x09, 0x49, 0xC8, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x0F, 0x05, 0x07, 0x04, 0x05,\n                0x07, 0x08, 0x06, 0x01, 0x06, 0x08,/*歃5640*/},\n        {\n\n                0x12, 0xD6, 0x5A, 0x53, 0x5A, 0xD6, 0x12, 0x0F, 0xC4, 0x14, 0x0C, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x0F, 0x08, 0x06, 0x01, 0x06, 0x08,/*歆5641*/},\n        {\n\n                0x04, 0x72, 0x55, 0x55, 0x72, 0x04, 0x10, 0x0F, 0xC4, 0x14, 0x0C, 0x0B, 0x05, 0x0F, 0x0A, 0x05,\n                0x0F, 0x08, 0x06, 0x01, 0x06, 0x08,/*歙5642*/},\n        {\n\n                0xFE, 0x12, 0xE2, 0x12, 0xFE, 0x04, 0xFB, 0x2A, 0x3A, 0x42, 0x7E, 0x07, 0x01, 0x00, 0x01, 0x07,\n                0x08, 0x09, 0x0A, 0x0A, 0x0A, 0x0F,/*飑5643*/},\n        {\n\n                0xE9, 0x0A, 0xE8, 0x00, 0xFE, 0x0A, 0x92, 0x62, 0x92, 0xFE, 0x00, 0x04, 0x05, 0x02, 0x08, 0x07,\n                0x01, 0x00, 0x00, 0x00, 0x07, 0x0C,/*飒5644*/},\n        {\n\n                0x00, 0xFE, 0x12, 0xE2, 0x12, 0xFE, 0x00, 0xFF, 0x55, 0xFF, 0x00, 0x08, 0x07, 0x01, 0x00, 0x01,\n                0x07, 0x0D, 0x0B, 0x09, 0x0B, 0x0D,/*飓5645*/},\n        {\n\n                0xFE, 0x12, 0xE2, 0x12, 0xFE, 0xAA, 0xA0, 0xFF, 0xA0, 0xAA, 0x3E, 0x07, 0x01, 0x00, 0x01, 0x07,\n                0x08, 0x0D, 0x0A, 0x0A, 0x0D, 0x0C,/*飕5646*/},\n        {\n\n                0x24, 0x9C, 0x47, 0x8C, 0x55, 0xFE, 0x12, 0xE2, 0x12, 0xFE, 0x00, 0x09, 0x07, 0x09, 0x07, 0x09,\n                0x07, 0x01, 0x00, 0x01, 0x07, 0x0C,/*飙5647*/},\n        {\n\n                0xFE, 0x12, 0xE2, 0x12, 0xFE, 0x00, 0x51, 0xE8, 0x87, 0xEA, 0x51, 0x07, 0x01, 0x00, 0x01, 0x07,\n                0x08, 0x0A, 0x09, 0x0A, 0x09, 0x0E,/*飚5648*/},\n        {\n\n                0x00, 0x10, 0x28, 0xE7, 0x21, 0x21, 0x21, 0x21, 0xA7, 0x68, 0x08, 0x00, 0x08, 0x08, 0x04, 0x05,\n                0x02, 0x02, 0x05, 0x04, 0x08, 0x08,/*殳5649*/},\n        {\n\n                0x1A, 0xAA, 0xAA, 0xAF, 0xEA, 0x1A, 0x08, 0xE7, 0x21, 0xEF, 0x08, 0x00, 0x03, 0x0A, 0x0A, 0x0E,\n                0x00, 0x08, 0x05, 0x02, 0x05, 0x08,/*彀5650*/},\n        {\n\n                0x1A, 0xAA, 0x7A, 0xAF, 0x2A, 0x1A, 0x08, 0xE7, 0x21, 0xEF, 0x08, 0x04, 0x05, 0x05, 0x0F, 0x05,\n                0x05, 0x08, 0x05, 0x02, 0x05, 0x08,/*毂5651*/},\n        {\n\n                0x5A, 0xAA, 0xBA, 0xAF, 0xEA, 0x9A, 0x08, 0xE7, 0x21, 0xEF, 0x08, 0x08, 0x07, 0x02, 0x07, 0x0A,\n                0x0F, 0x08, 0x05, 0x02, 0x05, 0x08,/*觳5652*/},\n        {\n\n                0x22, 0x2A, 0x2A, 0x2A, 0x7F, 0x80, 0x7F, 0x2A, 0x2A, 0x2A, 0x22, 0x09, 0x09, 0x0B, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x09,/*斐5653*/},\n        {\n\n                0x12, 0xD2, 0x12, 0x56, 0xEA, 0x0B, 0xEA, 0x56, 0x12, 0xD2, 0x12, 0x08, 0x07, 0x00, 0x05, 0x07,\n                0x04, 0x07, 0x05, 0x00, 0x0F, 0x00,/*齑5654*/},\n        {\n\n                0xC9, 0x0A, 0xF8, 0x08, 0xFD, 0x6A, 0xA8, 0xFD, 0xA9, 0x69, 0xFF, 0x0C, 0x03, 0x0C, 0x00, 0x0F,\n                0x09, 0x05, 0x0F, 0x05, 0x09, 0x0F,/*斓5655*/},\n        {\n\n                0x04, 0xFC, 0x25, 0x26, 0xE4, 0x10, 0x4C, 0x43, 0x8C, 0x10, 0x20, 0x08, 0x07, 0x08, 0x08, 0x07,\n                0x00, 0x02, 0x02, 0x04, 0x08, 0x00,/*於5656*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x14, 0xD3, 0x52, 0xFE, 0x52, 0x52, 0xD2, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x07, 0x00, 0x0F, 0x00, 0x04, 0x07,/*旆5657*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x04, 0x53, 0x52, 0xF2, 0xAA, 0xAA, 0x82, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x01, 0x01, 0x07, 0x08, 0x08, 0x0E,/*旄5658*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x04, 0x83, 0xFA, 0xAA, 0xCA, 0xFA, 0x82, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x08, 0x07, 0x00, 0x08, 0x0F, 0x00,/*旃5659*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x04, 0x43, 0x32, 0x22, 0xFA, 0x22, 0x22, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x08, 0x09, 0x09, 0x0F, 0x09, 0x09,/*旌5660*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x04, 0xFB, 0x2A, 0xEA, 0x2A, 0xBA, 0x02, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x07, 0x00, 0x07, 0x09, 0x08, 0x0E,/*旎5661*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x04, 0x6B, 0x5A, 0x4E, 0x4A, 0x6A, 0x02, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x07, 0x00, 0x0F, 0x00, 0x0F, 0x08,/*旒5662*/},\n        {\n\n                0x04, 0xFD, 0x26, 0xE4, 0x44, 0x6B, 0x5A, 0x4E, 0x5A, 0xEA, 0x42, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x07, 0x05, 0x07, 0x08, 0x0F, 0x00,/*旖5663*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0x22, 0xF2, 0x2A, 0xE6, 0x22, 0xE0, 0x08, 0x06, 0x01, 0x06, 0x02,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*炀5664*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x44, 0x54, 0x54, 0xFF, 0x54, 0x54, 0xC4, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x00, 0x00, 0x0F, 0x00, 0x02, 0x03,/*炜5665*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xF4, 0x84, 0xFF, 0x84, 0xF4, 0x04, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*炖5666*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x14, 0xE8, 0x24, 0x23, 0x24, 0xE8, 0x10, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x07, 0x08, 0x08, 0x09, 0x09, 0x0C,/*炝5667*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x84, 0x42, 0xF2, 0x2E, 0x22, 0x22, 0xE2, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*炻5668*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x10, 0x4A, 0x52, 0x42, 0xFE, 0x41, 0x51, 0x49, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x00, 0x08, 0x0F, 0x00, 0x00, 0x00,/*烀5669*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0x88, 0x89, 0xFA, 0x88, 0x88, 0x08, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*炷5670*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x44, 0x64, 0x55, 0xCE, 0x44, 0x24, 0x04, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*炫5671*/},\n        {\n\n                0x04, 0x76, 0x55, 0x54, 0x54, 0x54, 0x54, 0x54, 0x54, 0x76, 0x0C, 0x08, 0x0A, 0x09, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x0A, 0x09, 0x08,/*炱5672*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0x7E, 0x21, 0x90, 0x3F, 0x44, 0x72, 0x08, 0x06, 0x01, 0x06, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*烨5673*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x00, 0x08, 0x06, 0x01, 0x02, 0x05,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*烊5674*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x25, 0xA5, 0xBD, 0xA7, 0xA5, 0xBD, 0x21, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*焐5675*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x14, 0x28, 0x24, 0xB3, 0x64, 0x08, 0x10, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*焓5676*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFD, 0x42, 0xE0, 0x0A, 0x12, 0x42, 0xFE, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x00, 0x01, 0x02, 0x03, 0x08, 0x0F,/*焖5677*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0xF8, 0xA8, 0xAF, 0xAA, 0xFA, 0x02, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*焯5678*/},\n        {\n\n                0xA0, 0x24, 0xD2, 0x10, 0x88, 0x07, 0x88, 0x10, 0xD4, 0x22, 0xA0, 0x09, 0x04, 0x03, 0x05, 0x08,\n                0x00, 0x09, 0x04, 0x03, 0x05, 0x08,/*焱5679*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xE4, 0x3F, 0xE4, 0x00, 0xFF, 0x89, 0xFF, 0x08, 0x06, 0x01, 0x02, 0x07,\n                0x02, 0x0B, 0x04, 0x03, 0x08, 0x0F,/*煳5680*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x04, 0x9F, 0x95, 0xB5, 0xD5, 0x95, 0x9F, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x0A, 0x0C, 0x08, 0x08, 0x0C, 0x0A,/*煜5681*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x44, 0xDF, 0x55, 0xDF, 0x55, 0x5F, 0x40, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*煨5682*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x25, 0x08, 0xE7, 0x21, 0xEF, 0x08, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*煅5683*/},\n        {\n\n                0x08, 0x04, 0x7E, 0x01, 0x50, 0x37, 0x15, 0x7D, 0x15, 0x37, 0x50, 0x08, 0x0A, 0x09, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x0A, 0x09, 0x08,/*煲5684*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x06, 0xEA, 0xAA, 0xAB, 0xAA, 0xEA, 0x06, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*煊5685*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x48, 0xFE, 0x2A, 0xEA, 0x2B, 0xEA, 0x2A, 0xEE, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*煸5686*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x22, 0xEC, 0x00, 0xFF, 0x35, 0xD5, 0x5F, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x07, 0x04, 0x0B, 0x09, 0x08, 0x0B,/*煺5687*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xDE, 0x52, 0x69, 0xD2, 0x4E, 0x52, 0xDE, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*熘5688*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0x74, 0x5F, 0x75, 0x55, 0x75, 0x5F, 0x70, 0x08, 0x06, 0x01, 0x06, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*熳5689*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x10, 0xFA, 0x56, 0xBA, 0x93, 0xBA, 0x56, 0xF2, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*熵5690*/},\n        {\n\n                0xA0, 0x5F, 0x95, 0xF5, 0x15, 0x57, 0x80, 0x0A, 0x92, 0xFF, 0x02, 0x08, 0x08, 0x0A, 0x04, 0x04,\n                0x02, 0x04, 0x04, 0x0A, 0x08, 0x08,/*熨5691*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xD5, 0x49, 0x5F, 0x60, 0x55, 0x49, 0xDF, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*熠5692*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x08, 0xFE, 0x5A, 0x13, 0x7E, 0x12, 0x5A, 0xFE, 0x08, 0x06, 0x01, 0x06, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*燠5693*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x52, 0xB6, 0x9A, 0xBE, 0x99, 0xB5, 0x50, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x0A, 0x0F, 0x0A, 0x0F, 0x00,/*燔5694*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x04, 0x11, 0xF2, 0xA5, 0x56, 0xAC, 0xF6, 0xA5, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x07, 0x0A, 0x09, 0x0A, 0x0B, 0x08,/*燧5695*/},\n        {\n\n                0x55, 0x2B, 0x55, 0x79, 0x14, 0x25, 0x2B, 0x55, 0x79, 0x29, 0x45, 0x08, 0x0A, 0x09, 0x04, 0x04,\n                0x03, 0x04, 0x04, 0x0A, 0x09, 0x08,/*燹5696*/},\n        {\n\n                0x78, 0x00, 0xFF, 0x10, 0xBA, 0xAE, 0xBA, 0x2E, 0xB9, 0xED, 0xB9, 0x08, 0x06, 0x01, 0x02, 0x0F,\n                0x0A, 0x07, 0x08, 0x0A, 0x0F, 0x00,/*爝5697*/},\n        {\n\n                0x30, 0x5F, 0xD5, 0xF0, 0x5F, 0x95, 0x5F, 0xF0, 0xD5, 0x5F, 0x30, 0x0A, 0x0B, 0x0A, 0x07, 0x02,\n                0x03, 0x02, 0x07, 0x0A, 0x0B, 0x0A,/*爨5698*/},\n        {\n\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x04, 0x00, 0x04, 0x08,\n                0x00, 0x04, 0x08, 0x00, 0x04, 0x08,/*灬5699*/},\n        {\n\n                0x22, 0xAA, 0x6A, 0xBA, 0xAE, 0xAB, 0xAA, 0xAA, 0xEA, 0xAA, 0xA2, 0x09, 0x04, 0x00, 0x04, 0x09,\n                0x02, 0x04, 0x0A, 0x03, 0x04, 0x08,/*焘5700*/},\n        {\n\n                0x00, 0xFE, 0x12, 0xFE, 0x08, 0xF4, 0x97, 0xF4, 0x04, 0xFC, 0x00, 0x08, 0x05, 0x01, 0x05, 0x08,\n                0x00, 0x04, 0x0A, 0x02, 0x05, 0x08,/*煦5701*/},\n        {\n\n                0x82, 0x8A, 0xBA, 0xEA, 0xAA, 0xAF, 0xAA, 0xEA, 0xBA, 0x8A, 0x82, 0x08, 0x07, 0x02, 0x06, 0x0A,\n                0x02, 0x06, 0x0A, 0x02, 0x07, 0x08,/*熹5702*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0x8A, 0x8A, 0x8A, 0xEB, 0x8A, 0xAA, 0xCA, 0x8E, 0x08, 0x07, 0x08, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x08, 0x08,/*戾5703*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0x8A, 0x0A, 0x2A, 0x4B, 0x0A, 0xEA, 0x0A, 0x0E, 0x08, 0x07, 0x02, 0x02, 0x03,\n                0x02, 0x02, 0x02, 0x0F, 0x01, 0x01,/*戽5704*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0xEA, 0x2A, 0xAA, 0xAB, 0xAA, 0xAA, 0x2A, 0xEE, 0x08, 0x07, 0x00, 0x0F, 0x00,\n                0x03, 0x02, 0x02, 0x03, 0x08, 0x0F,/*扃5705*/},\n        {\n\n                0x00, 0xFE, 0x0A, 0x8A, 0xEA, 0xAA, 0xAB, 0xAA, 0xEA, 0x8A, 0x0E, 0x08, 0x07, 0x00, 0x07, 0x0A,\n                0x0A, 0x0B, 0x0A, 0x0A, 0x0B, 0x0C,/*扈5706*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xAA, 0xAA, 0xFA, 0x0B, 0xFA, 0xAA, 0xAA, 0x2E, 0x08, 0x07, 0x02, 0x02, 0x02,\n                0x0F, 0x00, 0x0F, 0x02, 0x02, 0x02,/*扉5707*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*礻5708*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xFE, 0x42, 0x42, 0x42, 0x7E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*祀5709*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*祆5710*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xF8, 0x00, 0x00, 0xFF, 0x10, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x0F, 0x08, 0x08, 0x0F, 0x08, 0x08,/*祉5711*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*祛5712*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x48, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*祜5713*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xC8, 0x3F, 0xE8, 0x29, 0xEA, 0x08, 0x00, 0x00, 0x0F, 0x00, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*祓5714*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x48, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*祚5715*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0x90, 0xC8, 0x07, 0xF4, 0x04, 0x54, 0x8C, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*祢5716*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x08, 0x03, 0x04, 0x0E,/*祗5717*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xEA, 0x2A, 0x2A, 0xEA, 0x02, 0xFE, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x03, 0x01, 0x01, 0x09, 0x08, 0x07,/*祠5718*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xF0, 0x10, 0xDF, 0x14, 0x14, 0xF4, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x09, 0x06, 0x01, 0x02, 0x04, 0x09,/*祯5719*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0x84, 0x48, 0xFF, 0x00, 0xFF, 0x48, 0x84, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*祧5720*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0x04, 0xFF, 0x54, 0x54, 0xFF, 0x04, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x09, 0x05, 0x01, 0x01, 0x05, 0x09,/*祺5721*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x40, 0xFD, 0x96, 0xFC, 0x96, 0xFD, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*禅5722*/},\n        {\n\n                0x45, 0xF6, 0x2C, 0x40, 0x2A, 0x7F, 0x2A, 0xC2, 0x3E, 0x42, 0x7E, 0x00, 0x0F, 0x00, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*禊5723*/},\n        {\n\n                0x45, 0xF6, 0x2C, 0x40, 0x04, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x04, 0x00, 0x0F, 0x00, 0x00, 0x0D,\n                0x01, 0x0D, 0x01, 0x0D, 0x01, 0x0D,/*禚5724*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x2C, 0x42, 0xEA, 0xAA, 0xAF, 0xAA, 0xEA, 0x02, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x0E, 0x0B, 0x0A, 0x0B, 0x0E, 0x02,/*禧5725*/},\n        {\n\n                0x45, 0xF6, 0x2C, 0x40, 0xBA, 0xAA, 0xFA, 0x83, 0xFA, 0xAA, 0xBA, 0x00, 0x0F, 0x00, 0x00, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*禳5726*/},\n        {\n\n                0x02, 0x02, 0x02, 0x02, 0x7E, 0x82, 0x0A, 0x12, 0x22, 0x02, 0x02, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*忑5727*/},\n        {\n\n                0x20, 0x20, 0x20, 0x20, 0x3F, 0xA4, 0x24, 0x24, 0x24, 0x24, 0x20, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*忐5728*/},\n        {\n\n                0x82, 0x52, 0x22, 0xDA, 0x06, 0x10, 0x24, 0x04, 0x84, 0xFF, 0x04, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*怼5729*/},\n        {\n\n                0x22, 0x2A, 0x7F, 0x2A, 0x22, 0x40, 0x22, 0x1E, 0x42, 0x42, 0x3E, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*恝5730*/},\n        {\n\n                0x88, 0xAA, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAA, 0xAA, 0x88, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*恚5731*/},\n        {\n\n                0x01, 0xFD, 0x05, 0x05, 0x7D, 0x07, 0x7D, 0x05, 0x85, 0xFD, 0x01, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*恧5732*/},\n        {\n\n                0x08, 0x04, 0xFE, 0x01, 0x08, 0x4A, 0x4A, 0x7E, 0x49, 0x49, 0x08, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*恁5733*/},\n        {\n\n                0x40, 0x54, 0x55, 0x56, 0x54, 0xFC, 0x54, 0x56, 0x55, 0x54, 0x40, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*恙5734*/},\n        {\n\n                0x42, 0x24, 0x00, 0x44, 0x23, 0x92, 0x0E, 0x12, 0x22, 0x4A, 0x46, 0x04, 0x03, 0x00, 0x07, 0x08,\n                0x08, 0x0B, 0x08, 0x0C, 0x01, 0x06,/*恣5735*/},\n        {\n\n                0x62, 0x2A, 0x2A, 0xAA, 0xAA, 0xAF, 0xAA, 0xAA, 0x2A, 0x2A, 0x62, 0x0A, 0x06, 0x01, 0x04, 0x0A,\n                0x0C, 0x08, 0x0D, 0x02, 0x06, 0x0B,/*悫5736*/},\n        {\n\n                0x24, 0x12, 0xF9, 0x04, 0x89, 0x52, 0x00, 0x89, 0x89, 0xF9, 0x09, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*愆5737*/},\n        {\n\n                0xFF, 0x95, 0x15, 0x7D, 0x97, 0x50, 0x84, 0x5B, 0x22, 0x5E, 0x82, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x01, 0x06,/*愍5738*/},\n        {\n\n                0x00, 0xFF, 0x55, 0x35, 0x77, 0x5D, 0x55, 0x55, 0x77, 0x15, 0x01, 0x08, 0x05, 0x01, 0x05, 0x0B,\n                0x0D, 0x09, 0x0D, 0x01, 0x05, 0x09,/*慝5739*/},\n        {\n\n                0x08, 0xEA, 0xAA, 0xBE, 0xA9, 0xE9, 0x00, 0xFE, 0xAB, 0xAA, 0xFE, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x0A, 0x0C, 0x08, 0x0C, 0x02, 0x0C,/*憩5740*/},\n        {\n\n                0x22, 0xAE, 0xEA, 0x3B, 0x2E, 0x22, 0x84, 0x5B, 0x22, 0x5E, 0x82, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*憝5741*/},\n        {\n\n                0x24, 0xFF, 0x14, 0x49, 0xAB, 0xFD, 0x0B, 0x18, 0x24, 0xFF, 0x14, 0x08, 0x06, 0x00, 0x06, 0x08,\n                0x09, 0x0A, 0x08, 0x0C, 0x02, 0x0C,/*懋5742*/},\n        {\n\n                0x89, 0x52, 0x00, 0xEA, 0xAA, 0x7F, 0xAA, 0xAA, 0x7F, 0xAA, 0xEA, 0x08, 0x04, 0x00, 0x05, 0x0A,\n                0x0C, 0x08, 0x0C, 0x00, 0x05, 0x09,/*懑5743*/},\n        {\n\n                0x8A, 0xBE, 0xEB, 0xBE, 0x8A, 0x14, 0xF7, 0xAA, 0xAA, 0xF6, 0x10, 0x08, 0x04, 0x01, 0x04, 0x08,\n                0x0E, 0x09, 0x0C, 0x00, 0x05, 0x0A,/*戆5744*/},\n        {\n\n                0x08, 0x08, 0x2A, 0x2A, 0x2A, 0xFF, 0x2A, 0x2A, 0x3E, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*肀5745*/},\n        {\n\n                0x08, 0x88, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xBE, 0x88, 0x08, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*聿5746*/},\n        {\n\n                0x12, 0xD2, 0x4A, 0x46, 0x50, 0x5F, 0x42, 0x44, 0x4A, 0xD1, 0x10, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*沓5747*/},\n        {\n\n                0x98, 0x89, 0x8A, 0x88, 0x09, 0xEA, 0x88, 0x08, 0x8A, 0x49, 0x18, 0x04, 0x04, 0x02, 0x01, 0x08,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*泶5748*/},\n        {\n\n                0x92, 0x92, 0x0A, 0xE6, 0x10, 0x9F, 0x82, 0xE4, 0x8A, 0x11, 0x90, 0x04, 0x03, 0x08, 0x0F, 0x01,\n                0x02, 0x09, 0x0F, 0x00, 0x03, 0x04,/*淼5749*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0x02, 0x02, 0xFE, 0x00, 0x00, 0x00, 0x07, 0x02, 0x0B, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*矶5750*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x40, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x40, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*矸5751*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x22, 0xF2, 0x2A, 0xE6, 0x22, 0xE0, 0x00, 0x07, 0x02, 0x07, 0x02,\n                0x09, 0x04, 0x03, 0x08, 0x08, 0x07,/*砀5752*/},\n        {\n\n                0xA2, 0xAA, 0xAA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xAA, 0xAA, 0xA2, 0x08, 0x04, 0x0E, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*砉5753*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x64, 0x5C, 0x47, 0xF4, 0x44, 0x44, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x02, 0x02, 0x02, 0x0F, 0x02, 0x02,/*砗5754*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xF4, 0x84, 0xFF, 0x84, 0xF4, 0x04, 0x00, 0x0F, 0x04, 0x0F, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*砘5755*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x32, 0x2A, 0xA2, 0x62, 0xFE, 0x22, 0x00, 0x07, 0x02, 0x03, 0x04,\n                0x02, 0x01, 0x00, 0x08, 0x0F, 0x00,/*砑5756*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0x12, 0x12, 0xF1, 0x11, 0x10, 0x00, 0x07, 0x02, 0x03, 0x08,\n                0x07, 0x00, 0x00, 0x0F, 0x00, 0x00,/*斫5757*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x22, 0x22, 0x2A, 0xB1, 0x61, 0x21, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x04, 0x02, 0x05, 0x08, 0x08, 0x08,/*砭5758*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0x92, 0x62, 0x92, 0xFE, 0x00, 0x00, 0x07, 0x02, 0x03, 0x08,\n                0x07, 0x00, 0x00, 0x00, 0x07, 0x0C,/*砜5759*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*砝5760*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x04, 0x6F, 0x84, 0x04, 0x84, 0x6F, 0x04, 0x00, 0x07, 0x02, 0x03, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*砹5761*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0x0A, 0xFA, 0x4A, 0x4A, 0xCA, 0x00, 0x07, 0x02, 0x0B, 0x04,\n                0x0B, 0x04, 0x03, 0x08, 0x08, 0x07,/*砺5762*/},\n        {\n\n                0xA4, 0xA4, 0x94, 0x8C, 0xA7, 0xA4, 0x9C, 0xB5, 0xAE, 0xA4, 0xB4, 0x08, 0x04, 0x0E, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*砻5763*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x24, 0x04, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x00, 0x0F, 0x01, 0x01, 0x01, 0x01,/*砟5764*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x10, 0x48, 0x44, 0xC3, 0x44, 0x48, 0x10, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*砼5765*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x0F, 0x04, 0x08, 0x03, 0x04, 0x0E,/*砥5766*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x28, 0xC8, 0x09, 0x0A, 0xE8, 0x08, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x08, 0x09, 0x0C, 0x0B, 0x08, 0x08,/*砬5767*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x24, 0x0C, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x07, 0x09, 0x08, 0x08, 0x08, 0x0E,/*砣5768*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0xF0, 0x92, 0xFF, 0x92, 0xFF, 0x92, 0x9E, 0x00, 0x07, 0x02, 0x03, 0x08,\n                0x04, 0x03, 0x00, 0x0F, 0x04, 0x07,/*砩5769*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x22, 0xFE, 0x22, 0xFE, 0x22, 0xFC, 0x00, 0xFF, 0x07, 0x02, 0x07, 0x08, 0x07,\n                0x00, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*硎5770*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x44, 0xCF, 0x44, 0x54, 0x64, 0x4F, 0x44, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x00,/*硭5771*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x94, 0xA4, 0x84, 0xFF, 0x84, 0xA4, 0x94, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*硖5772*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*硗5773*/},\n        {\n\n                0x50, 0x5E, 0x50, 0xCF, 0x4A, 0x4A, 0x40, 0x4F, 0x54, 0x52, 0x59, 0x04, 0x02, 0x0F, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x05, 0x0F, 0x00,/*砦5774*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0xFE, 0x02, 0xEA, 0x2A, 0xEA, 0x02, 0xFE, 0x07, 0x02, 0x07, 0x00, 0x0F,\n                0x00, 0x01, 0x01, 0x01, 0x08, 0x0F,/*硐5775*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0xFC, 0x14, 0xE6, 0x15, 0x04, 0xFC, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x0F, 0x05, 0x04, 0x05, 0x04, 0x0F,/*硇5776*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*硌5777*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x90, 0x92, 0xFE, 0x51, 0xFF, 0x92, 0x54, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x08, 0x0F, 0x02, 0x03, 0x04, 0x0E,/*硪5778*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0xA2, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xA2, 0x07, 0x02, 0x07, 0x00, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*碛5779*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*碓5780*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x20, 0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x20, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*碚5781*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x2C, 0xA4, 0x24, 0xE5, 0x26, 0x24, 0x2C, 0x00, 0x07, 0x02, 0x0B, 0x04,\n                0x03, 0x04, 0x0F, 0x09, 0x09, 0x08,/*碇5782*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x90, 0x54, 0xB6, 0x5D, 0xB4, 0x56, 0x94, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x0A, 0x0A, 0x05, 0x04, 0x02, 0x00,/*碜5783*/},\n        {\n\n                0x22, 0xFA, 0x16, 0xF2, 0xA0, 0xEA, 0xAA, 0xFF, 0xAA, 0xEA, 0xA2, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x03, 0x02, 0x0B, 0x0A, 0x07, 0x02,/*碡5784*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x80, 0x5F, 0x75, 0xD5, 0x55, 0x5F, 0xC0, 0x00, 0x07, 0x02, 0x07, 0x00,\n                0x06, 0x05, 0x04, 0x09, 0x08, 0x07,/*碣5785*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0xB2, 0x96, 0x9A, 0xD3, 0x9A, 0x96, 0xB2, 0x07, 0x02, 0x07, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*碲5786*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x06, 0xEA, 0xAA, 0xAB, 0xAA, 0xEA, 0x06, 0x00, 0x07, 0x02, 0x03, 0x08,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*碹5787*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0xC0, 0x3E, 0xEA, 0x2B, 0xEA, 0x2A, 0xEE, 0x00, 0x07, 0x02, 0x03, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*碥5788*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0xA4, 0x9B, 0x86, 0xD8, 0x92, 0xBF, 0x92, 0x00, 0x07, 0x02, 0x03, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*磔5789*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x00, 0x4A, 0x66, 0xD3, 0x42, 0x66, 0x4A, 0x00, 0x07, 0x02, 0x07, 0x04,\n                0x02, 0x0F, 0x04, 0x01, 0x06, 0x09,/*磙5790*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0xB0, 0x5B, 0xB5, 0x05, 0xB5, 0x5B, 0xB0, 0x00, 0x07, 0x02, 0x03, 0x0A,\n                0x06, 0x02, 0x0F, 0x02, 0x06, 0x0A,/*磉5791*/},\n        {\n\n                0x82, 0xFA, 0xAA, 0xBF, 0xAA, 0xBA, 0x84, 0xDB, 0xA9, 0xDB, 0x82, 0x08, 0x04, 0x0E, 0x0B, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*磬5792*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x04, 0x49, 0x22, 0x00, 0xFF, 0x55, 0x55, 0x5D, 0x07, 0x02, 0x07, 0x00, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*磲5793*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0xBA, 0xAB, 0xBA, 0x10, 0xEF, 0x08, 0xF8, 0x07, 0x02, 0x07, 0x00, 0x0A,\n                0x0E, 0x03, 0x0A, 0x05, 0x02, 0x0D,/*礅5794*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x25, 0xD9, 0x57, 0x50, 0x57, 0xDA, 0x25, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x0B, 0x0D, 0x09, 0x0D, 0x0B, 0x08,/*磴5795*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x82, 0xBE, 0xAA, 0xBE, 0xAA, 0xBE, 0x82, 0x00, 0x07, 0x02, 0x07, 0x08,\n                0x0F, 0x0A, 0x0F, 0x0A, 0x0F, 0x08,/*礓5796*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0xA0, 0x52, 0x2F, 0x5A, 0x42, 0x5A, 0x2F, 0x5A, 0x07, 0x02, 0x07, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*礤5797*/},\n        {\n\n                0xF2, 0x2E, 0xE2, 0x00, 0x9A, 0xAF, 0x6A, 0xAA, 0x2A, 0xAF, 0x5A, 0x07, 0x02, 0x07, 0x00, 0x0A,\n                0x0A, 0x05, 0x0A, 0x0F, 0x02, 0x04,/*礞5798*/},\n        {\n\n                0x42, 0xF2, 0x2E, 0xE2, 0x48, 0x92, 0xF7, 0x52, 0xFA, 0x57, 0xFA, 0x00, 0x07, 0x02, 0x03, 0x04,\n                0x02, 0x06, 0x02, 0x0A, 0x0F, 0x02,/*礴5799*/},\n        {\n\n                0x04, 0x04, 0x72, 0x56, 0xD5, 0x55, 0x55, 0x56, 0x72, 0x84, 0x04, 0x09, 0x09, 0x05, 0x03, 0x09,\n                0x09, 0x07, 0x0D, 0x0B, 0x09, 0x0D,/*龛5800*/},\n        {\n\n                0x08, 0xCA, 0x5C, 0x68, 0x4F, 0xF8, 0x4F, 0x68, 0x5C, 0xCA, 0x08, 0x00, 0x0F, 0x00, 0x02, 0x01,\n                0x0F, 0x01, 0x02, 0x08, 0x0F, 0x00,/*黹5801*/},\n        {\n\n                0xAA, 0x8F, 0xF8, 0x8F, 0xAA, 0x00, 0xC8, 0x3F, 0xE8, 0x29, 0xEA, 0x0F, 0x04, 0x0F, 0x02, 0x0F,\n                0x04, 0x03, 0x08, 0x05, 0x02, 0x0D,/*黻5802*/},\n        {\n\n                0xAA, 0x8F, 0xF8, 0x8F, 0xAA, 0x00, 0xF4, 0x54, 0xFF, 0x54, 0xF5, 0x0F, 0x04, 0x0F, 0x02, 0x0F,\n                0x00, 0x0F, 0x01, 0x07, 0x09, 0x0F,/*黼5803*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x20, 0x22, 0x22, 0xFE, 0x22, 0x22, 0x20, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*盱5804*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x00, 0xF2, 0x82, 0xFE, 0x92, 0x92, 0xF2, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*眄5805*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x00, 0xFE, 0x02, 0x0A, 0x32, 0xC2, 0x3A, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x0F, 0x08, 0x0A, 0x09, 0x08, 0x0B,/*眍5806*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x00, 0xF4, 0x84, 0xFF, 0x84, 0x84, 0xF4, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*盹5807*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x40, 0x38, 0x00, 0xFF, 0x00, 0x04, 0xB8, 0x0F, 0x04, 0x04, 0x07, 0x08,\n                0x08, 0x04, 0x04, 0x02, 0x01, 0x00,/*眇5808*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x1C, 0x04, 0xC4, 0x3F, 0xC4, 0x04, 0x1C, 0x0F, 0x04, 0x0F, 0x00, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0C,/*眈5809*/},\n        {\n\n                0x24, 0x2B, 0xEA, 0xAA, 0xAA, 0xBF, 0xAA, 0xAA, 0xEA, 0x2A, 0x20, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*眚5810*/},\n        {\n\n                0x44, 0x2A, 0xF3, 0xAA, 0xA6, 0xA0, 0xAF, 0xB1, 0xF5, 0x17, 0x18, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*眢5811*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x00, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*眙5812*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x0F, 0x04, 0x04, 0x07, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*眭5813*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xF8, 0x00, 0xFF, 0x20, 0xFF, 0x10, 0x08, 0x0F, 0x04, 0x07, 0x08, 0x0F,\n                0x08, 0x07, 0x04, 0x07, 0x08, 0x0E,/*眦5814*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x08, 0x44, 0xAB, 0x52, 0x6A, 0x46, 0xC0, 0x0F, 0x04, 0x04, 0x0F, 0x08,\n                0x09, 0x04, 0x05, 0x02, 0x01, 0x00,/*眵5815*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x80, 0x6C, 0x4A, 0xF9, 0x48, 0x4C, 0x18, 0x0F, 0x04, 0x04, 0x0F, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*眸5816*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x44, 0x54, 0x64, 0xFF, 0x64, 0x54, 0x44, 0x0F, 0x04, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*睐5817*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x0F, 0x04, 0x0F, 0x00, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*睑5818*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x00, 0x75, 0x56, 0xFC, 0x56, 0x5D, 0xC0, 0x0F, 0x04, 0x04, 0x0F, 0x04,\n                0x02, 0x01, 0x0F, 0x00, 0x02, 0x03,/*睇5819*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x24, 0x96, 0x65, 0x44, 0x44, 0xD6, 0x2C, 0x0F, 0x04, 0x0F, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*睃5820*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x42, 0x52, 0x52, 0x7E, 0x52, 0x52, 0x0F, 0x04, 0x07, 0x08, 0x07,\n                0x08, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*睚5821*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x92, 0x81, 0x90, 0x92, 0xFE, 0x00, 0x0F, 0x04, 0x07, 0x08, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0C,/*睨5822*/},\n        {\n\n                0xFE, 0x92, 0x92, 0xFE, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*睢5823*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x00, 0x0F, 0x04, 0x0F, 0x02, 0x03,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*睥5824*/},\n        {\n\n                0x4C, 0x54, 0xEC, 0xA4, 0xB4, 0xAF, 0xB5, 0xA5, 0xED, 0x55, 0x4C, 0x00, 0x00, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*睿5825*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0xBC, 0xAA, 0xA0, 0xFF, 0xA0, 0xAA, 0xBE, 0x0F, 0x04, 0x0F, 0x00, 0x08,\n                0x09, 0x0A, 0x04, 0x04, 0x0A, 0x09,/*瞍5826*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x4A, 0x32, 0x4E, 0xC0, 0x4F, 0x32, 0x49, 0x0F, 0x04, 0x0F, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*睽5827*/},\n        {\n\n                0x14, 0xED, 0xB7, 0xBD, 0xA7, 0xAC, 0xB4, 0xAB, 0xAA, 0xF6, 0x12, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*瞀5828*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x48, 0x6A, 0x5A, 0x4F, 0x4A, 0x6A, 0x48, 0x0F, 0x04, 0x07, 0x08, 0x0F,\n                0x09, 0x0F, 0x09, 0x0F, 0x09, 0x0F,/*瞌5829*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x03, 0x7D, 0x55, 0xD5, 0x55, 0x7D, 0x03, 0x0F, 0x04, 0x0F, 0x00, 0x09,\n                0x05, 0x01, 0x01, 0x01, 0x05, 0x09,/*瞑5830*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x1D, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x0F, 0x04, 0x0F, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*瞟5831*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x0D, 0xF6, 0x94, 0x97, 0x94, 0xF6, 0x0D, 0x0F, 0x04, 0x0F, 0x00, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*瞠5832*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x08, 0xF9, 0xAD, 0xFB, 0x10, 0xEC, 0x0B, 0xF8, 0x0F, 0x04, 0x0F, 0x02, 0x03,\n                0x02, 0x0F, 0x09, 0x04, 0x03, 0x0C,/*瞰5833*/},\n        {\n\n                0xFE, 0x92, 0xFE, 0x00, 0x95, 0x6E, 0xC4, 0x1F, 0x44, 0xEE, 0x55, 0x0F, 0x04, 0x0F, 0x02, 0x09,\n                0x06, 0x01, 0x03, 0x02, 0x0F, 0x02,/*瞵5834*/},\n        {\n\n                0xBA, 0xEA, 0xAF, 0xEA, 0xBA, 0x80, 0xDA, 0xAA, 0xAF, 0xDA, 0x42, 0x00, 0x0F, 0x09, 0x0A, 0x0C,\n                0x08, 0x09, 0x0A, 0x0C, 0x0F, 0x00,/*瞽5835*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x07, 0x02, 0x03, 0x02, 0x07,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*町5836*/},\n        {\n\n                0x80, 0xBE, 0xAA, 0xAA, 0xAA, 0xBE, 0xAA, 0xAA, 0xAA, 0xBE, 0x80, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,/*畀5837*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x08, 0xC8, 0x3F, 0xC8, 0x09, 0x0A, 0x07, 0x02, 0x03, 0x02, 0x0B,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*畎5838*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x10, 0xEC, 0x0B, 0x88, 0x78, 0x08, 0x07, 0x02, 0x03, 0x02, 0x0B,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*畋5839*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x00, 0xFE, 0x12, 0xF2, 0x11, 0xF1, 0x07, 0x02, 0x03, 0x02, 0x03,\n                0x04, 0x03, 0x08, 0x05, 0x02, 0x0D,/*畈5840*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x48, 0x24, 0x93, 0x44, 0x08, 0x90, 0x07, 0x02, 0x03, 0x02, 0x0B,\n                0x09, 0x05, 0x04, 0x02, 0x01, 0x00,/*畛5841*/},\n        {\n\n                0x54, 0xB4, 0x92, 0x96, 0xD5, 0xF5, 0x95, 0x96, 0x92, 0xB4, 0x54, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*畲5842*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xCC, 0x34, 0xE5, 0x06, 0xE4, 0x24, 0xEC, 0x07, 0x02, 0x03, 0x0A, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x09, 0x0D,/*畹5843*/},\n        {\n\n                0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x08, 0xFA, 0xAE, 0xFB, 0xAE, 0xFA, 0x07, 0x02, 0x03, 0x02, 0x07,\n                0x08, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*疃5844*/},\n        {\n\n                0x20, 0x2F, 0x29, 0x29, 0x2F, 0xA9, 0x6F, 0x29, 0x29, 0x2F, 0x20, 0x04, 0x04, 0x02, 0x02, 0x01,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x04,/*罘5845*/},\n        {\n\n                0x20, 0x2F, 0xA9, 0x29, 0x2F, 0xE9, 0x2F, 0x29, 0x29, 0x2F, 0x20, 0x08, 0x08, 0x0F, 0x08, 0x08,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*罡5846*/},\n        {\n\n                0x20, 0xAF, 0xA9, 0xA9, 0xAF, 0xF9, 0xAF, 0xA9, 0xA9, 0xAF, 0x20, 0x00, 0x0F, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*罟5847*/},\n        {\n\n                0x20, 0xAF, 0xA9, 0xA9, 0xAF, 0xB9, 0xAF, 0xA9, 0xA9, 0xAF, 0x20, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*詈5848*/},\n        {\n\n                0x20, 0xAF, 0xE9, 0xA9, 0xBF, 0xE9, 0xAF, 0xA9, 0xE9, 0x6F, 0xA0, 0x01, 0x00, 0x07, 0x02, 0x02,\n                0x07, 0x0A, 0x0A, 0x0B, 0x0C, 0x00,/*罨5849*/},\n        {\n\n                0x40, 0x57, 0xD5, 0x55, 0x57, 0x7D, 0x57, 0x55, 0xD5, 0x57, 0x40, 0x08, 0x05, 0x01, 0x05, 0x09,\n                0x01, 0x05, 0x09, 0x01, 0x05, 0x08,/*罴5850*/},\n        {\n\n                0x10, 0xD7, 0x55, 0x55, 0xD7, 0x7D, 0xD7, 0x55, 0x55, 0xD7, 0x10, 0x00, 0x0F, 0x04, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x08, 0x0F, 0x00,/*罱5851*/},\n        {\n\n                0xE0, 0x07, 0xFD, 0x55, 0xE7, 0xBD, 0xA7, 0xED, 0xB5, 0xA7, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*罹5852*/},\n        {\n\n                0xD0, 0x7F, 0xD5, 0x7D, 0xD7, 0x05, 0xD7, 0x95, 0x95, 0xF7, 0x80, 0x05, 0x05, 0x0F, 0x05, 0x05,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*羁5853*/},\n        {\n\n                0xF0, 0x97, 0xB5, 0xDD, 0x97, 0xF5, 0x97, 0xDD, 0xB5, 0x97, 0xF0, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*罾5854*/},\n        {\n\n                0x08, 0x4A, 0x6A, 0x5A, 0x4A, 0x4F, 0x4A, 0x4A, 0x6A, 0x4A, 0x08, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盍5855*/},\n        {\n\n                0x7E, 0x2A, 0x01, 0x24, 0x5C, 0x7F, 0x18, 0x24, 0x00, 0x2A, 0x7E, 0x08, 0x0F, 0x09, 0x09, 0x0F,\n                0x09, 0x0F, 0x09, 0x09, 0x0F, 0x08,/*盥5856*/},\n        {\n\n                0xA5, 0x96, 0x84, 0x96, 0xA5, 0x20, 0xD7, 0x5D, 0xF7, 0x55, 0xF7, 0x0F, 0x08, 0x0F, 0x04, 0x07,\n                0x04, 0x05, 0x05, 0x07, 0x0D, 0x0F,/*蠲5857*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*钅5858*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0E,/*钆5859*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x02, 0xC2, 0x32, 0x0A, 0x06, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*钇5860*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0x00, 0xFF, 0x10, 0x20, 0xC0, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*钋5861*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0xFC, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x01, 0x08, 0x08, 0x0F, 0x00,/*钊5862*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0x02, 0x02, 0xF2, 0x0A, 0x06, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x00, 0x08, 0x0F, 0x00, 0x00,/*钌5863*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x10, 0x10, 0xFF, 0x10, 0x10, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*钍5864*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0xFF, 0x00, 0xFE, 0x00, 0xFF, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x08, 0x07, 0x00, 0x07, 0x00, 0x0F,/*钏5865*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0x88, 0x44, 0x22, 0x11, 0x88, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x08, 0x08, 0x04, 0x02, 0x01, 0x00,/*钐5866*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFD, 0x02, 0x00, 0x02, 0x02, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*钔5867*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x02, 0x3E, 0xC2, 0x0A, 0xD2, 0x3E, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*钗5868*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x48, 0xB8, 0x0F, 0x88, 0x78, 0x08, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*钕5869*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x42, 0x22, 0xFA, 0x06, 0x22, 0xC2, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*钚5870*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x08, 0xC8, 0x3F, 0xC8, 0x08, 0x08, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x06, 0x01, 0x06, 0x01, 0x06, 0x08,/*钛5871*/},\n        {\n\n                0x88, 0x97, 0xF4, 0x94, 0x94, 0x00, 0xFE, 0x12, 0x12, 0x12, 0xF2, 0x00, 0x00, 0x0F, 0x04, 0x02,\n                0x00, 0x0F, 0x09, 0x09, 0x09, 0x09,/*钜5872*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFE, 0x12, 0xF2, 0x12, 0x91, 0x71, 0x00, 0x0F, 0x04, 0x0A, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*钣5873*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x20, 0x90, 0x8C, 0xA3, 0x8C, 0x90, 0x20, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x00, 0x08, 0x06, 0x01, 0x00,/*钤5874*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*钫5875*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x80, 0x04, 0xE4, 0x25, 0x26, 0xE4, 0x04, 0x04, 0x00, 0x0F, 0x04, 0x0A, 0x04,\n                0x03, 0x00, 0x00, 0x07, 0x08, 0x0E,/*钪5876*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x12, 0x24, 0x00, 0xFF, 0x80, 0x80, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x01, 0x01, 0x01, 0x0F, 0x00, 0x00,/*钭5877*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x20, 0x1C, 0x80, 0x7F, 0x80, 0x10, 0x0C, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x01, 0x06, 0x08,/*钬5878*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFE, 0x42, 0x7E, 0x42, 0x42, 0x7E, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*钯5879*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x42, 0x42, 0xFE, 0x42, 0x42, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x09, 0x0A,/*钰5880*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x02, 0xE2, 0x02, 0xFE, 0x42, 0x42, 0x42, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x0F, 0x08, 0x0F, 0x08, 0x08, 0x08,/*钲5881*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x08, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x08, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*钴5882*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xF2, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x03, 0x01, 0x09, 0x08, 0x0F, 0x00,/*钶5883*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFE, 0x02, 0xF2, 0x12, 0xF2, 0x02, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x08, 0x09, 0x09, 0x09, 0x08,/*钷5884*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x40, 0x24, 0xF4, 0x2C, 0xF7, 0x24, 0x24, 0xE4, 0x00, 0x0F, 0x04, 0x00, 0x00,\n                0x07, 0x00, 0x0F, 0x00, 0x04, 0x07,/*钸5885*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xC8, 0x3F, 0xE8, 0x29, 0xEA, 0x08, 0x00, 0x0F, 0x04, 0x02, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*钹5886*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xF8, 0x08, 0x08, 0xFF, 0x08, 0xE9, 0x0A, 0x00, 0x0F, 0x04, 0x00, 0x07,\n                0x02, 0x08, 0x04, 0x03, 0x04, 0x0E,/*钺5887*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFE, 0x92, 0x92, 0x92, 0x92, 0xFE, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*钼5888*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFE, 0x12, 0x12, 0x12, 0xFE, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x09, 0x09, 0x09, 0x09, 0x09, 0x08,/*钽5889*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x22, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*钿5890*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xBE, 0x22, 0xFA, 0x21, 0xA1, 0x20, 0x00, 0x0F, 0x04, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*铄5891*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xE4, 0x24, 0x25, 0xFE, 0x24, 0x24, 0xE4, 0x00, 0x0F, 0x04, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*铈5892*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x44, 0x64, 0x55, 0xCE, 0x44, 0x24, 0x04, 0x00, 0x0F, 0x04, 0x00, 0x04,\n                0x06, 0x05, 0x04, 0x04, 0x06, 0x0C,/*铉5893*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x2C, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*铊5894*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x80, 0x70, 0x00, 0xF1, 0x86, 0x60, 0x1C, 0xE0, 0x00, 0x0F, 0x04, 0x08, 0x04,\n                0x02, 0x07, 0x08, 0x08, 0x0E, 0x00,/*铋5895*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFE, 0x12, 0xD2, 0x12, 0x92, 0x5E, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x07, 0x00, 0x07, 0x09, 0x08, 0x0E,/*铌5896*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFC, 0x24, 0xE4, 0x3F, 0x24, 0xE4, 0x0C, 0x00, 0x0F, 0x04, 0x08, 0x07,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*铍5897*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x21, 0xA3, 0x95, 0xE9, 0x95, 0xA3, 0x20, 0x00, 0x0F, 0x04, 0x00, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*铎5898*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x94, 0xD4, 0x7F, 0x54, 0x58, 0x54, 0x12, 0x00, 0x0F, 0x04, 0x01, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*铐5899*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x20, 0xA4, 0xE4, 0x3F, 0x34, 0xA8, 0xA6, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x00, 0x07, 0x09, 0x09, 0x08, 0x0C,/*铑5900*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x02, 0xFE, 0x52, 0x52, 0x52, 0xFE, 0x02, 0x00, 0x0F, 0x04, 0x00, 0x02,\n                0x03, 0x02, 0x02, 0x02, 0x0F, 0x01,/*铒5901*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x40, 0x24, 0xF4, 0x5C, 0x57, 0x54, 0xF4, 0x04, 0x00, 0x0F, 0x04, 0x00, 0x00,\n                0x0F, 0x01, 0x01, 0x09, 0x0F, 0x00,/*铕5902*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFC, 0x24, 0xE4, 0x04, 0xFF, 0x84, 0x65, 0x00, 0x07, 0x0A, 0x06, 0x01,\n                0x02, 0x0B, 0x04, 0x03, 0x04, 0x0E,/*铖5903*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x94, 0xA4, 0x84, 0xFF, 0x84, 0xA4, 0x94, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*铗5904*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*铙5905*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x3D, 0xA1, 0xFF, 0x21, 0xFE, 0x32, 0xCE, 0x00, 0x0F, 0x04, 0x02, 0x01,\n                0x08, 0x0F, 0x00, 0x0F, 0x02, 0x01,/*铘5906*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x12, 0x94, 0x90, 0x9F, 0x90, 0x94, 0xF2, 0x00, 0x0F, 0x04, 0x00, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*铛5907*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0xC0, 0x5E, 0x52, 0xF2, 0x52, 0x5E, 0xC0, 0x00, 0x0F, 0x04, 0x00, 0x07,\n                0x00, 0x00, 0x0F, 0x00, 0x04, 0x07,/*铞5908*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x22, 0xA2, 0x7A, 0xA2, 0x22, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x05, 0x0F,/*铟5909*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x2E, 0x28, 0x2F, 0x28, 0xEE, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x07, 0x09, 0x09, 0x09, 0x09, 0x0C,/*铠5910*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x28, 0x26, 0xA4, 0xFF, 0xA4, 0x24, 0x20, 0x00, 0x0F, 0x04, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*铢5911*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x72, 0xCE, 0x00, 0x22, 0xFE, 0x21, 0x00, 0x00, 0x0F, 0x04, 0x0A, 0x04,\n                0x0B, 0x08, 0x0A, 0x0B, 0x0A, 0x08,/*铤5912*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x80, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0C, 0x0A, 0x09, 0x08, 0x0C, 0x08,/*铥5913*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x08, 0x04, 0x7E, 0x21, 0x90, 0x3F, 0x44, 0x72, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*铧5914*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x10, 0x28, 0x24, 0xE3, 0x24, 0x28, 0x10, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*铨5915*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x10, 0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0x10, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*铪5916*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x40, 0x51, 0x4A, 0xE4, 0x4A, 0x51, 0x40, 0x00, 0x0F, 0x04, 0x00, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x01, 0x02,/*铩5917*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x84, 0x48, 0xFF, 0x00, 0xFF, 0x48, 0x84, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*铫5918*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x48, 0x54, 0x53, 0xF2, 0x5A, 0x56, 0xF0, 0x40, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x09, 0x0F, 0x01, 0x01, 0x03, 0x00,/*铮5919*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x08, 0xF4, 0x93, 0xF2, 0x9A, 0x96, 0xF0, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*铯5920*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x64, 0xD4, 0x4D, 0xC6, 0x54, 0xE4, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*铳5921*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x08, 0x91, 0x42, 0x91, 0x79, 0x95, 0x73, 0xF0, 0x00, 0x0F, 0x04, 0x01, 0x04,\n                0x02, 0x09, 0x06, 0x09, 0x08, 0x07,/*铴5922*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x4C, 0xC4, 0x75, 0x46, 0xC4, 0x4C, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x08, 0x05, 0x02, 0x02, 0x05, 0x08,/*铵5923*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x88, 0x78, 0x0F, 0xF8, 0x00, 0xFC, 0x04, 0xFC, 0x00, 0x0F, 0x04, 0x08, 0x05,\n                0x02, 0x0D, 0x00, 0x07, 0x02, 0x07,/*铷5924*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xB2, 0x97, 0xD2, 0x92, 0x92, 0x97, 0xB2, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x08, 0x08, 0x07,/*铹5925*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x44, 0x54, 0x64, 0xFF, 0x64, 0x54, 0x44, 0x00, 0x0F, 0x04, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*铼5926*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xD4, 0x24, 0x84, 0x3F, 0xC4, 0x05, 0x00, 0x0F, 0x04, 0x00, 0x01,\n                0x03, 0x04, 0x06, 0x01, 0x07, 0x0C,/*铽5927*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x3E, 0x00, 0x7F, 0x82, 0x5E, 0x22, 0x5E, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*铿5928*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x20, 0x2F, 0x29, 0xE9, 0x29, 0x2F, 0x20, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*锃5929*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x7F, 0x49, 0xFF, 0x49, 0x7F, 0x00, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*锂5930*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x28, 0xA6, 0xA4, 0xBF, 0xA4, 0xA4, 0x20, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*锆5931*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x92, 0xFE, 0x51, 0x10, 0xFF, 0x92, 0x54, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x0F, 0x04, 0x02, 0x03, 0x04, 0x0E,/*锇5932*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x20, 0x1C, 0x20, 0xFF, 0x20, 0x1C, 0x20, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*锉5933*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x4A, 0x52, 0x46, 0x4A, 0x41, 0xE9, 0x45, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x01, 0x02, 0x00, 0x08, 0x0F, 0x00,/*锊5934*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xA4, 0x34, 0xAD, 0x26, 0xA4, 0x34, 0x64, 0x00, 0x0F, 0x04, 0x08, 0x07,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0C,/*锍5935*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFD, 0x4A, 0xF8, 0x4A, 0xFA, 0x4A, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0F,/*锎5936*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xF9, 0x02, 0xF8, 0x4A, 0xFA, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*锏5937*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x80, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*锒5938*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0xC0, 0x55, 0x55, 0x55, 0x55, 0x5F, 0xC0, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*锓5939*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFF, 0x15, 0xD5, 0x55, 0xD5, 0x17, 0xF0, 0x00, 0x07, 0x02, 0x08, 0x07,\n                0x00, 0x03, 0x02, 0x0B, 0x08, 0x07,/*锔5940*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x32, 0xCE, 0xF8, 0x8A, 0xFE, 0x02, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x02, 0x01, 0x00, 0x08, 0x0F, 0x00,/*锕5941*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x22, 0xEA, 0xAA, 0xBF, 0xAA, 0xEA, 0x22, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*锖5942*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x24, 0x24, 0xEF, 0xB4, 0xA4, 0xAF, 0xA4, 0x24, 0x00, 0x0F, 0x04, 0x02, 0x01,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*锘5943*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x12, 0xAA, 0x26, 0x73, 0x26, 0xAA, 0x12, 0x00, 0x0F, 0x04, 0x08, 0x05,\n                0x03, 0x01, 0x01, 0x01, 0x0F, 0x01,/*锛5944*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x5F, 0x55, 0x55, 0x55, 0xD5, 0x5F, 0x00, 0x00, 0x0F, 0x04, 0x01, 0x03,\n                0x05, 0x01, 0x09, 0x0F, 0x01, 0x01,/*锝5945*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x40, 0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x40, 0x00, 0x0F, 0x04, 0x02, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*锞5946*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xDF, 0x15, 0x15, 0x15, 0xD5, 0x1F, 0x80, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x09, 0x05, 0x00, 0x07, 0x09, 0x0C,/*锟5947*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x02, 0xD2, 0x7E, 0xD2, 0x02, 0xFE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x04, 0x05, 0x05, 0x05, 0x04, 0x0F,/*锢5948*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x08, 0x24, 0x53, 0xAE, 0x12, 0x4E, 0x42, 0x3E, 0x00, 0x0F, 0x04, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*锪5949*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x20, 0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x20, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*锫5950*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x50, 0xB5, 0x9C, 0x97, 0x94, 0xB5, 0x50, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x07, 0x08, 0x08, 0x0A, 0x0B, 0x0C,/*锩5951*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x28, 0xA6, 0x10, 0xCF, 0x10, 0x14, 0xA2, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x05, 0x08,/*锬5952*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xC4, 0x4A, 0x55, 0xCA, 0x55, 0x4A, 0xD1, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*锱5953*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x2A, 0x7F, 0x2A, 0xC2, 0x3E, 0x42, 0x7E, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*锲5954*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xDF, 0x52, 0x4A, 0x60, 0x4F, 0x52, 0xD9, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*锴5955*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x00, 0x7F, 0x49, 0xFF, 0x49, 0x7F, 0x00, 0x00, 0x0F, 0x04, 0x00, 0x02,\n                0x01, 0x06, 0x08, 0x09, 0x0C, 0x03,/*锶5956*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x80, 0x47, 0xD5, 0x57, 0x50, 0x57, 0x55, 0x47, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x01, 0x01, 0x09, 0x09, 0x07, 0x00,/*锷5957*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0xC8, 0x2A, 0x0A, 0xFE, 0x09, 0x49, 0xC8, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x05, 0x04, 0x07, 0x04, 0x05, 0x0F,/*锸5958*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xBC, 0xAA, 0xA0, 0xFF, 0xA0, 0xAA, 0xBE, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x09, 0x0A, 0x04, 0x04, 0x0A, 0x09,/*锼5959*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x56, 0x5A, 0xD6, 0x7A, 0x52, 0x59, 0x55, 0x00, 0x0F, 0x04, 0x00, 0x0A,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*锾5960*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x7A, 0x4A, 0xCB, 0x4A, 0x4A, 0x7A, 0x82, 0x00, 0x0F, 0x04, 0x04, 0x02,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x04,/*锿5961*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xAA, 0x9C, 0xC8, 0xBF, 0x88, 0x9C, 0xAA, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x0A, 0x05, 0x04, 0x04, 0x0B, 0x08,/*镂5962*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x04, 0x88, 0xFF, 0x24, 0xAA, 0x93, 0xEA, 0x86, 0x00, 0x0F, 0x04, 0x01, 0x00,\n                0x0F, 0x01, 0x02, 0x08, 0x0F, 0x00,/*锵5963*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xBA, 0xEA, 0xBF, 0xAA, 0xFF, 0xAA, 0x6E, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x0B, 0x04, 0x03, 0x04, 0x0B, 0x00,/*镄5964*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFF, 0x09, 0xE9, 0xAF, 0xA9, 0xA9, 0xEF, 0x00, 0x0F, 0x04, 0x08, 0x07,\n                0x00, 0x0F, 0x0A, 0x0A, 0x0A, 0x0F,/*镅5965*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x02, 0xFA, 0xAF, 0xAA, 0xAF, 0xFA, 0x02, 0x00, 0x0F, 0x04, 0x00, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*镆5966*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0xC1, 0x5D, 0xD5, 0x55, 0xD5, 0x5D, 0xC1, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x00, 0x02, 0x0F, 0x02, 0x08, 0x0F,/*镉5967*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x84, 0xFE, 0xAB, 0xAA, 0xFF, 0xAA, 0xAA, 0x00, 0x0F, 0x04, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x0A, 0x0B, 0x06,/*镌5968*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x04, 0xBC, 0xAA, 0xAA, 0xA9, 0xAA, 0xBA, 0x44, 0x00, 0x0F, 0x04, 0x02, 0x02,\n                0x02, 0x0A, 0x0F, 0x02, 0x02, 0x02,/*镎5969*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xDE, 0x52, 0x69, 0xD2, 0x4E, 0x52, 0xDE, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x05, 0x05, 0x07, 0x05, 0x05, 0x0F,/*镏5970*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xA9, 0x9A, 0x88, 0x88, 0x88, 0x9A, 0xA9, 0x00, 0x0F, 0x04, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*镒5971*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x46, 0xAA, 0x5A, 0xAB, 0xCA, 0x4A, 0x26, 0x00, 0x0F, 0x04, 0x00, 0x05,\n                0x02, 0x09, 0x08, 0x07, 0x01, 0x02,/*镓5972*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x06, 0xFA, 0x2A, 0x2B, 0xE6, 0x22, 0x26, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x05, 0x01, 0x01, 0x05, 0x09, 0x01,/*镔5973*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x1D, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*镖5974*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x80, 0x0D, 0xF6, 0x94, 0x97, 0x94, 0xF6, 0x0D, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*镗5975*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x70, 0x5F, 0x75, 0x55, 0x75, 0x5F, 0x70, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*镘5976*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x5F, 0x75, 0xD5, 0x5F, 0x35, 0x95, 0x1F, 0x00, 0x0F, 0x04, 0x08, 0x05,\n                0x01, 0x09, 0x0F, 0x01, 0x05, 0x09,/*镙5977*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x22, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x00, 0x0F, 0x04, 0x08, 0x07,\n                0x00, 0x0F, 0x02, 0x07, 0x0A, 0x0F,/*镛5978*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x04, 0xFD, 0x26, 0xE4, 0xA3, 0x9A, 0xF2, 0x92, 0x00, 0x0F, 0x04, 0x08, 0x07,\n                0x08, 0x07, 0x08, 0x04, 0x03, 0x0C,/*镞5979*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x04, 0xFD, 0x26, 0xE4, 0x13, 0xF2, 0x92, 0xB2, 0x00, 0x0F, 0x04, 0x08, 0x07,\n                0x08, 0x0F, 0x04, 0x0F, 0x08, 0x08,/*镟5980*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xF2, 0x16, 0x5A, 0xF3, 0x5A, 0x16, 0xF2, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x00, 0x07, 0x05, 0x07, 0x08, 0x0F,/*镝5981*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x1D, 0xF5, 0x5F, 0x55, 0x5F, 0xF5, 0x1D, 0x00, 0x0F, 0x04, 0x00, 0x04,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x04,/*镡5982*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x2A, 0xF2, 0x2A, 0xA2, 0xDE, 0x32, 0x00, 0x0F, 0x04, 0x08, 0x07,\n                0x09, 0x07, 0x09, 0x05, 0x03, 0x0C,/*镢5983*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x25, 0xAC, 0xB7, 0xE4, 0xB7, 0xAC, 0x25, 0x00, 0x0F, 0x04, 0x00, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*镤5984*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x84, 0xFA, 0xAB, 0xFA, 0xAE, 0xA8, 0xF8, 0x80, 0x00, 0x0F, 0x04, 0x00, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x00, 0x00,/*镥5985*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xBA, 0xAB, 0xBA, 0x10, 0xEF, 0x08, 0xF8, 0x00, 0x0F, 0x04, 0x00, 0x0A,\n                0x0E, 0x03, 0x0A, 0x05, 0x02, 0x0D,/*镦5986*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFD, 0x6A, 0xA8, 0xFD, 0xA9, 0x69, 0xFF, 0x00, 0x0F, 0x04, 0x00, 0x0F,\n                0x09, 0x05, 0x0F, 0x05, 0x09, 0x0F,/*镧5987*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x80, 0x2A, 0xA3, 0xBE, 0xA2, 0xBE, 0xA3, 0x2A, 0x00, 0x0F, 0x04, 0x02, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*镨5988*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0x06, 0x7A, 0x56, 0xFB, 0x56, 0x7A, 0x06, 0x00, 0x0F, 0x04, 0x00, 0x07,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x07,/*镩5989*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x84, 0x79, 0xCF, 0xF0, 0x97, 0xFD, 0x97, 0xF0, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x0F, 0x04, 0x04, 0x07, 0x04, 0x0E,/*镪5990*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x20, 0xD5, 0x49, 0x57, 0x50, 0x4F, 0xD2, 0x29, 0x00, 0x0F, 0x04, 0x08, 0x0B,\n                0x0D, 0x09, 0x09, 0x0D, 0x0B, 0x08,/*镫5991*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x20, 0xFA, 0x57, 0x52, 0xF6, 0x5A, 0x57, 0x52, 0x00, 0x0F, 0x04, 0x08, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x09,/*镬5992*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x20, 0xD7, 0x5D, 0xF7, 0x55, 0xD7, 0x15, 0xF7, 0x00, 0x0F, 0x04, 0x00, 0x05,\n                0x05, 0x07, 0x05, 0x0D, 0x08, 0x07,/*镯5993*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x08, 0x00, 0x0F, 0x04, 0x02, 0x0C,\n                0x00, 0x0C, 0x0A, 0x0C, 0x02, 0x0C,/*镱5994*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x20, 0x56, 0x2A, 0x5A, 0x43, 0x5A, 0x2A, 0x5E, 0x00, 0x0F, 0x04, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*镲5995*/},\n        {\n\n                0x94, 0xF3, 0x92, 0x00, 0xFE, 0x2A, 0xFE, 0xAB, 0xFE, 0xAA, 0x7A, 0x00, 0x07, 0x02, 0x04, 0x0B,\n                0x00, 0x0B, 0x02, 0x09, 0x02, 0x0B,/*镳5996*/},\n        {\n\n                0x98, 0xF7, 0x94, 0x94, 0x08, 0xFA, 0xAA, 0xFE, 0xA9, 0xF9, 0x08, 0x00, 0x0F, 0x04, 0x02, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*锺5997*/},\n        {\n\n                0x48, 0x47, 0xFC, 0x44, 0x00, 0xF2, 0x92, 0x9E, 0x00, 0xFF, 0x00, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x08, 0x08, 0x07, 0x00, 0x0F, 0x00,/*矧5998*/},\n        {\n\n                0x48, 0x47, 0xFC, 0x44, 0x20, 0x1C, 0x20, 0xFF, 0x20, 0x1C, 0x20, 0x08, 0x06, 0x01, 0x06, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*矬5999*/},\n        {\n\n                0x48, 0x47, 0xFC, 0x44, 0x10, 0xFC, 0x27, 0x24, 0xFD, 0x26, 0x24, 0x08, 0x06, 0x01, 0x06, 0x00,\n                0x0F, 0x09, 0x09, 0x0F, 0x09, 0x09,/*雉6000*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0xFF, 0x10, 0x10, 0xFF, 0x10, 0x0C, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x02, 0x07, 0x08, 0x0E,/*秕6001*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0x78, 0x48, 0xFF, 0x44, 0x44, 0xC0, 0x01, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x00, 0x02, 0x03,/*秭6002*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x94, 0x24, 0xA4, 0xFF, 0xA4, 0x24, 0x04, 0x01, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*秣6003*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x00, 0x88, 0x68, 0xFF, 0x68, 0x89, 0x0A, 0x01, 0x00, 0x0F, 0x00, 0x02,\n                0x01, 0x00, 0x0F, 0x00, 0x01, 0x02,/*秫6004*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x90, 0xC0, 0x5F, 0x51, 0x51, 0x5F, 0xC0, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*稆6005*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x44, 0x34, 0x0F, 0x7C, 0x85, 0x86, 0xE4, 0x01, 0x00, 0x0F, 0x00, 0x0E,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x0E,/*嵇6006*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x00, 0x2A, 0x32, 0x26, 0xAA, 0x71, 0x2D, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x01, 0x01, 0x09, 0x0F, 0x01, 0x01,/*稃6007*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x80, 0x01, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*稂6008*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x40, 0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x40, 0x01, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*稞6009*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x08, 0x14, 0x92, 0x19, 0x52, 0x34, 0x08, 0x01, 0x00, 0x0F, 0x04, 0x03,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*稔6010*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0x02, 0xFA, 0xAA, 0xAF, 0xAA, 0xFA, 0x02, 0x01, 0x00, 0x0F, 0x00, 0x02,\n                0x0B, 0x06, 0x02, 0x06, 0x0B, 0x02,/*稹6011*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0x80, 0x5F, 0xB5, 0x1F, 0x35, 0x5F, 0x80, 0x01, 0x00, 0x0F, 0x00, 0x02,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*稷6012*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x91, 0xEA, 0x2E, 0xAA, 0xAF, 0xAA, 0x2E, 0xEA, 0x01, 0x00, 0x0F, 0x00, 0x0F,\n                0x08, 0x0B, 0x0A, 0x0B, 0x08, 0x0F,/*穑6013*/},\n        {\n\n                0x54, 0x4D, 0xBF, 0x2D, 0x54, 0x00, 0xC0, 0x40, 0x7F, 0x48, 0xC8, 0x05, 0x0A, 0x0F, 0x02, 0x05,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*黏6014*/},\n        {\n\n                0x4A, 0xAA, 0xFE, 0xA9, 0x48, 0x02, 0x7D, 0xD5, 0x55, 0x7D, 0x01, 0x00, 0x0F, 0x0A, 0x0F, 0x00,\n                0x0A, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*馥6015*/},\n        {\n\n                0x12, 0xD2, 0xFE, 0x51, 0xBA, 0xAA, 0xFA, 0x83, 0xFA, 0xAA, 0xBA, 0x01, 0x00, 0x0F, 0x00, 0x0A,\n                0x06, 0x0F, 0x0A, 0x03, 0x06, 0x0A,/*穰6016*/},\n        {\n\n                0xFC, 0x26, 0x25, 0xFC, 0x00, 0xFE, 0x12, 0xF2, 0x12, 0x91, 0x71, 0x07, 0x02, 0x02, 0x0F, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*皈6017*/},\n        {\n\n                0xFC, 0x26, 0x25, 0xFC, 0x40, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x07, 0x02, 0x02, 0x07, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*皎6018*/},\n        {\n\n                0xFC, 0x46, 0x45, 0xFC, 0x28, 0xA6, 0xA4, 0xBF, 0xA4, 0xA4, 0x20, 0x0F, 0x04, 0x04, 0x0F, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*皓6019*/},\n        {\n\n                0x12, 0x8A, 0xBF, 0xCA, 0x92, 0xA0, 0x9E, 0x8A, 0x8A, 0xBA, 0x09, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*皙6020*/},\n        {\n\n                0xFC, 0x26, 0x25, 0xFC, 0x52, 0xB6, 0x9A, 0xBE, 0x99, 0xB5, 0x50, 0x07, 0x02, 0x02, 0x07, 0x00,\n                0x0F, 0x0A, 0x0F, 0x0A, 0x0F, 0x00,/*皤6021*/},\n        {\n\n                0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x28, 0x26, 0xA4, 0x7F, 0xA4, 0x24, 0x07, 0x00, 0x0F, 0x0A, 0x0D,\n                0x02, 0x05, 0x04, 0x08, 0x08, 0x09,/*瓞6022*/},\n        {\n\n                0x4A, 0xD6, 0x53, 0x56, 0x4A, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x00, 0x01, 0x09, 0x0F, 0x00,\n                0x08, 0x07, 0x00, 0x0F, 0x0A, 0x0C,/*瓠6023*/},\n        {\n\n                0x00, 0xF1, 0x51, 0x51, 0x55, 0xF9, 0x55, 0x53, 0x51, 0xF0, 0x00, 0x00, 0x0F, 0x01, 0x01, 0x01,\n                0x07, 0x01, 0x01, 0x09, 0x0F, 0x00,/*甬6024*/},\n        {\n\n                0x08, 0xFF, 0x08, 0xF8, 0x00, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x08, 0x07, 0x00, 0x07, 0x02,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸠6025*/},\n        {\n\n                0x04, 0x04, 0xE4, 0x24, 0x73, 0xA6, 0x2A, 0xAA, 0xF3, 0x12, 0x1A, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x05, 0x05, 0x05, 0x01, 0x09, 0x0F,/*鸢6026*/},\n        {\n\n                0x00, 0x1F, 0xA4, 0x22, 0x38, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x01, 0x01, 0x0F, 0x01, 0x01,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸨6027*/},\n        {\n\n                0x1C, 0xC4, 0x3F, 0xC4, 0x1C, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x08, 0x07, 0x00, 0x07, 0x02,\n                0x01, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸩6028*/},\n        {\n\n                0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸪6029*/},\n        {\n\n                0x74, 0x4C, 0xF7, 0x44, 0x44, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x02, 0x09, 0x0F, 0x01, 0x02,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸫6030*/},\n        {\n\n                0x00, 0xF0, 0x9F, 0x94, 0xF4, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x08, 0x07, 0x00, 0x00, 0x01,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸬6031*/},\n        {\n\n                0xE8, 0x27, 0xE4, 0x04, 0xFC, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x03, 0x01, 0x09, 0x08, 0x07,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸲6032*/},\n        {\n\n                0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x0F, 0x04, 0x08, 0x03, 0x04,\n                0x0E, 0x00, 0x02, 0x0A, 0x0A, 0x07,/*鸱6033*/},\n        {\n\n                0x22, 0x2B, 0xAE, 0xAA, 0xE9, 0xA0, 0xA2, 0xAB, 0xAE, 0x2A, 0x29, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x02, 0x0B, 0x0A, 0x06,/*鸶6034*/},\n        {\n\n                0xF2, 0x12, 0xFA, 0x16, 0xF2, 0x12, 0xF2, 0x00, 0xFE, 0xAB, 0x9E, 0x0F, 0x00, 0x07, 0x00, 0x07,\n                0x08, 0x0F, 0x00, 0x0A, 0x0A, 0x07,/*鸸6035*/},\n        {\n\n                0x12, 0x52, 0xFF, 0x8A, 0xC0, 0xAA, 0x9F, 0xA2, 0x9E, 0x20, 0x78, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x02, 0x0B, 0x0A, 0x06,/*鸷6036*/},\n        {\n\n                0x92, 0x92, 0xFE, 0x91, 0x91, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鸹6037*/},\n        {\n\n                0x10, 0xFC, 0x83, 0x48, 0xFF, 0x48, 0x80, 0xFE, 0x8B, 0xA2, 0xBE, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x02, 0x0A, 0x0A, 0x07,/*鸺6038*/},\n        {\n\n                0x12, 0x0A, 0xC2, 0x5E, 0xE2, 0x53, 0x42, 0x5E, 0x42, 0xCA, 0x12, 0x00, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x02, 0x0B, 0x0A, 0x06,/*鸾6039*/},\n        {\n\n                0x1A, 0x2A, 0xAF, 0x6A, 0x1A, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x02, 0x0A, 0x0F, 0x01, 0x01,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鹁6040*/},\n        {\n\n                0xFA, 0x8A, 0xFA, 0x02, 0xFA, 0x8A, 0xFA, 0x00, 0xFE, 0xAB, 0x9E, 0x0F, 0x00, 0x0F, 0x00, 0x0F,\n                0x00, 0x0F, 0x00, 0x0A, 0x0A, 0x07,/*鹂6041*/},\n        {\n\n                0x28, 0xA6, 0xA4, 0xBF, 0xA4, 0x20, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x00, 0x0F, 0x04, 0x04, 0x0F,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鹄6042*/},\n        {\n\n                0xA2, 0x91, 0x8C, 0x91, 0xA2, 0x44, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鹆6043*/},\n        {\n\n                0xFD, 0x92, 0x50, 0xFA, 0x52, 0x92, 0xFE, 0x00, 0xFE, 0xAB, 0x9E, 0x0F, 0x00, 0x00, 0x03, 0x00,\n                0x08, 0x0F, 0x00, 0x0A, 0x0A, 0x07,/*鹇6044*/},\n        {\n\n                0x75, 0x56, 0xFC, 0x56, 0xDD, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x02, 0x01, 0x0F, 0x02, 0x03,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鹈6045*/},\n        {\n\n                0x90, 0x12, 0xF2, 0x90, 0xFF, 0x12, 0x14, 0xFE, 0x8B, 0xA2, 0xBE, 0x0F, 0x08, 0x07, 0x04, 0x03,\n                0x04, 0x0E, 0x02, 0x0A, 0x0A, 0x07,/*鹉6046*/},\n        {\n\n                0xF2, 0x97, 0xF2, 0x97, 0xF2, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x0F, 0x04, 0x07, 0x04, 0x0F,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鹋6047*/},\n        {\n\n                0x12, 0xEA, 0xA6, 0xF3, 0xA6, 0xEA, 0x10, 0xFE, 0x8B, 0xA2, 0xBE, 0x00, 0x07, 0x02, 0x0F, 0x0A,\n                0x0B, 0x04, 0x02, 0x0A, 0x0A, 0x07,/*鹌6048*/},\n        {\n\n                0x00, 0x7C, 0xD6, 0x7D, 0x54, 0x7C, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x02, 0x03, 0x02, 0x0F, 0x02,\n                0x02, 0x00, 0x02, 0x0A, 0x0A, 0x07,/*鹎6049*/},\n        {\n\n                0xBA, 0xAA, 0xAB, 0xAA, 0x3A, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x02, 0x0A, 0x0E, 0x03, 0x02,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鹑6050*/},\n        {\n\n                0xE4, 0x3F, 0xE4, 0x00, 0xFF, 0x89, 0xFF, 0x00, 0xFE, 0xAB, 0x9E, 0x07, 0x02, 0x0B, 0x04, 0x03,\n                0x08, 0x0F, 0x00, 0x0A, 0x0A, 0x07,/*鹕6051*/},\n        {\n\n                0x47, 0xD5, 0x57, 0x50, 0x57, 0x55, 0x47, 0x00, 0xFE, 0xAB, 0x9E, 0x00, 0x01, 0x01, 0x09, 0x09,\n                0x07, 0x00, 0x00, 0x0A, 0x0A, 0x07,/*鹗6052*/},\n        {\n\n                0xE8, 0x99, 0x4A, 0x08, 0xEC, 0x9B, 0x48, 0x00, 0xFE, 0xAB, 0x9E, 0x06, 0x05, 0x0E, 0x00, 0x06,\n                0x05, 0x0E, 0x00, 0x0A, 0x0A, 0x07,/*鹚6053*/},\n        {\n\n                0x00, 0xFF, 0x09, 0xEF, 0xA9, 0xEF, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x08, 0x07, 0x00, 0x0F, 0x0A,\n                0x0F, 0x00, 0x02, 0x0A, 0x0A, 0x07,/*鹛6054*/},\n        {\n\n                0x28, 0x19, 0xAB, 0xBD, 0xCB, 0x98, 0xA4, 0x97, 0x8A, 0x16, 0x22, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x02, 0x0B, 0x0A, 0x06,/*鹜6055*/},\n        {\n\n                0xA6, 0x9A, 0xF6, 0x9A, 0x95, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x0E, 0x08, 0x07, 0x04, 0x0E,\n                0x00, 0x02, 0x02, 0x0A, 0x08, 0x07,/*鹞6056*/},\n        {\n\n                0x44, 0x55, 0xFE, 0x54, 0xFE, 0x55, 0xF4, 0x44, 0xFE, 0xAB, 0x9E, 0x05, 0x03, 0x0F, 0x01, 0x0F,\n                0x03, 0x05, 0x08, 0x0A, 0x0A, 0x07,/*鹣6057*/},\n        {\n\n                0xAF, 0x91, 0xAF, 0xC0, 0xAF, 0x91, 0xAF, 0x00, 0xFE, 0xAB, 0x9E, 0x08, 0x0A, 0x0B, 0x04, 0x04,\n                0x0B, 0x08, 0x00, 0x0A, 0x0A, 0x07,/*鹦6058*/},\n        {\n\n                0x00, 0xFE, 0x22, 0xFA, 0x23, 0xFA, 0x22, 0x00, 0xFE, 0xAB, 0x9E, 0x04, 0x0B, 0x04, 0x09, 0x05,\n                0x09, 0x04, 0x08, 0x0A, 0x0A, 0x07,/*鹧6059*/},\n        {\n\n                0x8B, 0x45, 0xAF, 0x5A, 0xA5, 0x4F, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x00, 0x0A, 0x0A, 0x09, 0x04,\n                0x02, 0x00, 0x02, 0x0A, 0x0A, 0x07,/*鹨6060*/},\n        {\n\n                0x2A, 0xF2, 0xAA, 0xA7, 0xAA, 0xF2, 0x2A, 0x00, 0xFE, 0xAB, 0x9E, 0x08, 0x07, 0x0A, 0x0E, 0x02,\n                0x07, 0x08, 0x00, 0x0A, 0x0A, 0x07,/*鹩6061*/},\n        {\n\n                0x08, 0xFC, 0x57, 0xFC, 0x55, 0x54, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x0C, 0x03, 0x0D, 0x01, 0x0D,\n                0x01, 0x0C, 0x02, 0x0A, 0x0A, 0x07,/*鹪6062*/},\n        {\n\n                0x12, 0x2E, 0xBB, 0x8E, 0xD2, 0xA4, 0x9C, 0x87, 0x9C, 0x25, 0x34, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x02, 0x0B, 0x0A, 0x06,/*鹫6063*/},\n        {\n\n                0xE8, 0x59, 0xEB, 0x7D, 0xCD, 0x4B, 0xD8, 0x00, 0xFE, 0xAB, 0x9E, 0x0F, 0x01, 0x0E, 0x0A, 0x0E,\n                0x01, 0x0F, 0x00, 0x0A, 0x0A, 0x07,/*鹬6064*/},\n        {\n\n                0xFE, 0x8B, 0xA2, 0xBE, 0x80, 0x12, 0xFA, 0x57, 0xFA, 0x57, 0x52, 0x02, 0x02, 0x0A, 0x08, 0x07,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x09,/*鹱6065*/},\n        {\n\n                0xEE, 0x8A, 0xFA, 0xAE, 0xC0, 0x94, 0xF7, 0xAA, 0xAA, 0xF6, 0x10, 0x08, 0x08, 0x0B, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x02, 0x0B, 0x0A, 0x06,/*鹭6066*/},\n        {\n\n                0xBA, 0xEF, 0xBA, 0xC2, 0xBA, 0xAF, 0xBA, 0x00, 0xFE, 0xAB, 0x9E, 0x00, 0x0F, 0x0A, 0x0A, 0x0F,\n                0x0A, 0x0A, 0x00, 0x0A, 0x0A, 0x07,/*鹳6067*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x04, 0x05, 0x06, 0x04, 0x04, 0x04, 0x04, 0x09, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*疒6068*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x24, 0x24, 0x25, 0x26, 0xE4, 0x24, 0x24, 0x24, 0x09, 0x04, 0x03, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x00, 0x00, 0x00,/*疔6069*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x24, 0x25, 0xE6, 0x24, 0x24, 0x24, 0xE4, 0x09, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x0F, 0x00, 0x00, 0x02, 0x03,/*疖6070*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x14, 0xF5, 0x96, 0x94, 0x94, 0x94, 0x04, 0x09, 0x04, 0x03, 0x08, 0x04,\n                0x03, 0x00, 0x08, 0x08, 0x07, 0x00,/*疠6071*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0xC4, 0x05, 0x06, 0xF4, 0x04, 0x04, 0xC4, 0x09, 0x04, 0x03, 0x00, 0x07,\n                0x04, 0x04, 0x07, 0x04, 0x04, 0x0F,/*疝6072*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xFA, 0x4A, 0x4B, 0xEA, 0x4A, 0x4A, 0xCA, 0x09, 0x04, 0x0B, 0x04, 0x03,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*疬6073*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x22, 0x22, 0xFA, 0x23, 0xE2, 0x2A, 0x32, 0x22, 0x09, 0x04, 0x03, 0x08, 0x06,\n                0x01, 0x00, 0x07, 0x08, 0x08, 0x0E,/*疣6074*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x12, 0xFA, 0x92, 0x93, 0x92, 0x92, 0xFA, 0x12, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x04, 0x04, 0x04, 0x04, 0x0F, 0x00,/*疳6075*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x14, 0xD4, 0x55, 0x56, 0xD4, 0x14, 0xF4, 0x14, 0x09, 0x04, 0x03, 0x00, 0x07,\n                0x02, 0x02, 0x0B, 0x08, 0x0F, 0x00,/*疴6076*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xFA, 0x4A, 0x4B, 0x4A, 0x4A, 0xFA, 0x02, 0x09, 0x04, 0x03, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*疸6077*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x84, 0x44, 0x3D, 0xE6, 0xA4, 0xA4, 0xA4, 0x24, 0x09, 0x04, 0x03, 0x00, 0x00,\n                0x00, 0x0F, 0x02, 0x02, 0x02, 0x02,/*痄6078*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x12, 0xEE, 0x2A, 0x2B, 0xEA, 0x0A, 0xFA, 0x02, 0x09, 0x04, 0x03, 0x00, 0x07,\n                0x09, 0x09, 0x09, 0x0A, 0x0B, 0x0C,/*疱6079*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x04, 0x24, 0x25, 0x2E, 0xF4, 0x24, 0x24, 0x24, 0x09, 0x04, 0x03, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*疰6080*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0x92, 0xD2, 0xB7, 0x9A, 0x92, 0x52, 0x12, 0x09, 0x04, 0x03, 0x00, 0x04,\n                0x04, 0x06, 0x05, 0x04, 0x06, 0x0C,/*痃6081*/},\n        {\n\n                0x88, 0xFE, 0x02, 0x12, 0xFE, 0x12, 0xF3, 0x02, 0xF2, 0x12, 0xF2, 0x08, 0x07, 0x08, 0x06, 0x09,\n                0x08, 0x07, 0x00, 0x0F, 0x04, 0x0F,/*痂6082*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x4A, 0x8A, 0xFA, 0x0B, 0x0A, 0xFA, 0x8A, 0x4A, 0x09, 0x04, 0x03, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x0F, 0x08, 0x08,/*痖6083*/},\n        {\n\n                0x88, 0xFE, 0x02, 0xEA, 0xAA, 0xAA, 0xFF, 0xAA, 0xAA, 0xBA, 0x82, 0x08, 0x07, 0x08, 0x08, 0x04,\n                0x02, 0x01, 0x02, 0x04, 0x0A, 0x0B,/*痍6084*/},\n        {\n\n                0x88, 0xFE, 0x12, 0x92, 0x92, 0x92, 0xFB, 0x92, 0x92, 0x92, 0x12, 0x08, 0x07, 0x08, 0x06, 0x00,\n                0x06, 0x09, 0x0A, 0x0C, 0x02, 0x0C,/*痣6085*/},\n        {\n\n                0x88, 0xFE, 0x02, 0x6A, 0xAA, 0xBE, 0xEB, 0xAA, 0xBE, 0xAA, 0x6A, 0x08, 0x07, 0x00, 0x08, 0x04,\n                0x02, 0x01, 0x08, 0x08, 0x07, 0x00,/*痨6086*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x82, 0xAA, 0xEA, 0xBB, 0xAA, 0xEA, 0x8A, 0x82, 0x09, 0x04, 0x03, 0x00, 0x0E,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*痦6087*/},\n        {\n\n                0x08, 0x90, 0xFC, 0x44, 0x34, 0x45, 0xFE, 0x44, 0x34, 0x44, 0x84, 0x09, 0x04, 0x0B, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x08,/*痤6088*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xF6, 0x4A, 0x43, 0xEA, 0x4A, 0x4A, 0xFA, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x02, 0x01, 0x0F, 0x01, 0x0A, 0x0F,/*痫6089*/},\n        {\n\n                0x88, 0xFE, 0x02, 0x26, 0x4A, 0x82, 0x73, 0x02, 0xFE, 0x12, 0x62, 0x08, 0x07, 0x00, 0x04, 0x02,\n                0x08, 0x08, 0x04, 0x04, 0x02, 0x01,/*痧6090*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0x4A, 0xAA, 0xDB, 0x2A, 0xCA, 0x4A, 0x2A, 0x09, 0x04, 0x03, 0x00, 0x05,\n                0x04, 0x0A, 0x09, 0x07, 0x01, 0x02,/*瘃6091*/},\n        {\n\n                0x88, 0xFE, 0x02, 0x92, 0x92, 0xFE, 0x03, 0x02, 0xFE, 0x92, 0x92, 0x08, 0x07, 0x00, 0x04, 0x04,\n                0x0F, 0x00, 0x00, 0x0F, 0x04, 0x04,/*痱6092*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xFA, 0x0A, 0xAB, 0xFA, 0xAA, 0x0A, 0xFA, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x08, 0x0B, 0x0A, 0x0B, 0x08, 0x0F,/*痼6093*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xA2, 0x6A, 0xAB, 0x7A, 0x2A, 0x66, 0xA2, 0x09, 0x04, 0x03, 0x09, 0x09,\n                0x0B, 0x05, 0x05, 0x0B, 0x09, 0x01,/*痿6094*/},\n        {\n\n                0x88, 0xFE, 0x02, 0xE2, 0x52, 0x02, 0xFB, 0x02, 0x52, 0xF2, 0x02, 0x08, 0x07, 0x08, 0x09, 0x05,\n                0x03, 0x01, 0x03, 0x05, 0x09, 0x08,/*瘐6095*/},\n        {\n\n                0x88, 0xFE, 0x12, 0xF6, 0x5A, 0xD2, 0x23, 0x12, 0x4E, 0x92, 0x22, 0x08, 0x07, 0x08, 0x07, 0x08,\n                0x0F, 0x00, 0x02, 0x04, 0x09, 0x00,/*瘀6096*/},\n        {\n\n                0x88, 0xFE, 0x02, 0xF2, 0x56, 0x5A, 0xF3, 0x5A, 0x56, 0xF2, 0x02, 0x08, 0x07, 0x04, 0x05, 0x05,\n                0x05, 0x0F, 0x05, 0x05, 0x05, 0x04,/*瘅6097*/},\n        {\n\n                0x10, 0xFE, 0xEA, 0xAA, 0xFE, 0xAA, 0xEB, 0x02, 0xF2, 0x02, 0xFA, 0x09, 0x07, 0x04, 0x02, 0x0F,\n                0x02, 0x04, 0x00, 0x03, 0x08, 0x0F,/*瘌6098*/},\n        {\n\n                0x08, 0xFE, 0x02, 0x4A, 0xDA, 0x6B, 0x7E, 0x6A, 0xDA, 0x4A, 0x42, 0x09, 0x07, 0x08, 0x09, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x09, 0x08,/*瘗6099*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x12, 0xFA, 0x26, 0xEB, 0xAA, 0xAA, 0xBA, 0xA2, 0x09, 0x04, 0x03, 0x00, 0x0F,\n                0x01, 0x0A, 0x06, 0x03, 0x06, 0x0A,/*瘊6100*/},\n        {\n\n                0x88, 0xFE, 0x02, 0x8A, 0xAE, 0xEA, 0xBB, 0xAA, 0xAA, 0xAE, 0x8A, 0x08, 0x07, 0x04, 0x02, 0x09,\n                0x0A, 0x0A, 0x0E, 0x0A, 0x0A, 0x08,/*瘥6101*/},\n        {\n\n                0x88, 0xFE, 0x12, 0x56, 0x3A, 0x92, 0x7F, 0x12, 0x3A, 0x56, 0x12, 0x08, 0x07, 0x09, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x09,/*瘘6102*/},\n        {\n\n                0x88, 0xFE, 0x02, 0xFA, 0xAA, 0xBA, 0x03, 0xAA, 0xAA, 0xBA, 0x02, 0x08, 0x07, 0x00, 0x0F, 0x02,\n                0x02, 0x08, 0x05, 0x02, 0x05, 0x08,/*瘕6103*/},\n        {\n\n                0x88, 0xFE, 0x42, 0xCA, 0xDA, 0xAA, 0xFB, 0xAA, 0xAA, 0xDA, 0x42, 0x08, 0x07, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0B, 0x0C,/*瘙6104*/},\n        {\n\n                0x88, 0xFE, 0x02, 0xAA, 0xFE, 0xAA, 0x8B, 0x7A, 0x8A, 0xFA, 0x02, 0x08, 0x07, 0x08, 0x06, 0x01,\n                0x06, 0x09, 0x0A, 0x0C, 0x02, 0x0C,/*瘛6105*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x0A, 0xEA, 0xBE, 0xAB, 0xAA, 0xBE, 0xEA, 0x0A, 0x09, 0x04, 0x03, 0x0A, 0x0B,\n                0x06, 0x02, 0x02, 0x06, 0x0B, 0x0A,/*瘼6106*/},\n        {\n\n                0x08, 0xFE, 0x82, 0xFA, 0xAE, 0xFB, 0x22, 0x9A, 0x8A, 0xBA, 0x22, 0x09, 0x07, 0x08, 0x07, 0x0A,\n                0x0F, 0x00, 0x0B, 0x04, 0x0B, 0x08,/*瘢6107*/},\n        {\n\n                0x88, 0xFE, 0x42, 0x56, 0xEA, 0xB2, 0xAF, 0xB2, 0xEA, 0x56, 0x42, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x02, 0x02, 0x0A, 0x0F, 0x00, 0x00,/*瘠6108*/},\n        {\n\n                0x88, 0xFE, 0x22, 0xEA, 0xBE, 0xAA, 0xEB, 0xAA, 0xBE, 0xEA, 0x22, 0x08, 0x07, 0x00, 0x0B, 0x06,\n                0x02, 0x03, 0x02, 0x06, 0x0B, 0x00,/*癀6109*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xEA, 0xAA, 0xFB, 0xAA, 0xFA, 0xAA, 0xEA, 0x09, 0x04, 0x03, 0x00, 0x0A,\n                0x06, 0x0A, 0x0E, 0x02, 0x06, 0x0A,/*瘭6110*/},\n        {\n\n                0x88, 0xFE, 0x02, 0x3E, 0xAA, 0xEA, 0xBF, 0xAA, 0x6A, 0x3E, 0x02, 0x08, 0x07, 0x00, 0x0A, 0x06,\n                0x0A, 0x0F, 0x02, 0x06, 0x0B, 0x00,/*瘰6111*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xBA, 0x4A, 0xBB, 0x02, 0xBA, 0x4A, 0xBA, 0x09, 0x04, 0x03, 0x09, 0x09,\n                0x0B, 0x05, 0x05, 0x0B, 0x09, 0x09,/*瘿6112*/},\n        {\n\n                0x08, 0x90, 0xFE, 0xA2, 0x5E, 0x2A, 0x5B, 0x42, 0x5A, 0x2A, 0x5A, 0x09, 0x04, 0x03, 0x00, 0x09,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*瘵6113*/},\n        {\n\n                0x88, 0xFE, 0x02, 0xFA, 0x4A, 0xBA, 0x53, 0xDE, 0xAA, 0xDA, 0x42, 0x08, 0x07, 0x00, 0x0F, 0x02,\n                0x01, 0x08, 0x0A, 0x0F, 0x0A, 0x08,/*癃6114*/},\n        {\n\n                0x88, 0xFE, 0x02, 0xFA, 0x2A, 0xDA, 0x93, 0xAE, 0xBA, 0xEA, 0x02, 0x08, 0x07, 0x00, 0x0F, 0x02,\n                0x05, 0x0C, 0x09, 0x0C, 0x02, 0x04,/*瘾6115*/},\n        {\n\n                0x08, 0xFE, 0x82, 0x96, 0x4A, 0x5F, 0xA2, 0x56, 0x4A, 0x9E, 0x82, 0x09, 0x07, 0x00, 0x08, 0x09,\n                0x09, 0x0A, 0x05, 0x04, 0x02, 0x00,/*瘳6116*/},\n        {\n\n                0x10, 0xFE, 0x8A, 0xFA, 0x8A, 0xA2, 0x2B, 0xE2, 0xAA, 0xFA, 0x8A, 0x09, 0x07, 0x08, 0x0F, 0x04,\n                0x02, 0x01, 0x06, 0x08, 0x0F, 0x08,/*癍6117*/},\n        {\n\n                0x10, 0xFE, 0xEA, 0xAA, 0xFE, 0xAA, 0xEB, 0x12, 0xEE, 0x3A, 0xE2, 0x09, 0x07, 0x04, 0x02, 0x0F,\n                0x02, 0x04, 0x08, 0x05, 0x02, 0x0D,/*癞6118*/},\n        {\n\n                0x88, 0xFE, 0x22, 0xEA, 0x3A, 0x2A, 0x6F, 0xAA, 0x3A, 0xEA, 0x22, 0x08, 0x07, 0x0C, 0x01, 0x0D,\n                0x0B, 0x0D, 0x09, 0x0D, 0x01, 0x0C,/*癔6119*/},\n        {\n\n                0x10, 0xFE, 0xAA, 0xEA, 0xAA, 0xEA, 0xBB, 0x42, 0xBA, 0x8A, 0xBA, 0x09, 0x07, 0x0A, 0x07, 0x02,\n                0x07, 0x0A, 0x00, 0x0B, 0x04, 0x0B,/*癜6120*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xFA, 0x4A, 0x7B, 0x02, 0xAA, 0xCE, 0xAA, 0x09, 0x04, 0x03, 0x02, 0x0F,\n                0x09, 0x0F, 0x00, 0x02, 0x0F, 0x02,/*癖6121*/},\n        {\n\n                0x08, 0x90, 0xFE, 0x02, 0xEA, 0xBE, 0xEB, 0x02, 0xEA, 0x3A, 0xEA, 0x09, 0x04, 0x03, 0x0A, 0x07,\n                0x02, 0x07, 0x0A, 0x05, 0x02, 0x0D,/*癫6122*/},\n        {\n\n                0x88, 0xFE, 0x02, 0xBE, 0xEA, 0xBE, 0xC3, 0xBE, 0xAA, 0xBE, 0x82, 0x08, 0x07, 0x01, 0x0F, 0x0A,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*癯6123*/},\n        {\n\n                0x28, 0xC9, 0x0A, 0xE8, 0x00, 0x12, 0xA2, 0xFE, 0x10, 0xA2, 0xFE, 0x04, 0x04, 0x02, 0x02, 0x00,\n                0x01, 0x08, 0x0F, 0x01, 0x08, 0x0F,/*翊6124*/},\n        {\n\n                0x28, 0xC9, 0x0A, 0xE8, 0x04, 0x74, 0x54, 0xFF, 0x54, 0x74, 0x04, 0x04, 0x04, 0x02, 0x02, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*竦6125*/},\n        {\n\n                0x06, 0x82, 0x4A, 0xA6, 0x3A, 0x23, 0x22, 0x26, 0xAA, 0x62, 0x06, 0x08, 0x08, 0x08, 0x04, 0x05,\n                0x02, 0x02, 0x01, 0x00, 0x00, 0x00,/*穸6126*/},\n        {\n\n                0x06, 0xD2, 0x5A, 0x56, 0x52, 0x53, 0x52, 0x56, 0x5A, 0x72, 0x06, 0x00, 0x01, 0x01, 0x01, 0x01,\n                0x01, 0x01, 0x01, 0x09, 0x09, 0x07,/*穹6127*/},\n        {\n\n                0x16, 0xD2, 0x1A, 0x16, 0x12, 0xFB, 0x12, 0x16, 0x1A, 0xD2, 0x16, 0x00, 0x01, 0x01, 0x01, 0x01,\n                0x07, 0x09, 0x09, 0x09, 0x09, 0x0C,/*窀6128*/},\n        {\n\n                0x86, 0x92, 0x9A, 0x96, 0x92, 0xB3, 0xCA, 0x8E, 0x8A, 0x8A, 0x06, 0x08, 0x08, 0x04, 0x04, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x09, 0x08, 0x08,/*窆6129*/},\n        {\n\n                0x86, 0xCA, 0xA6, 0x92, 0x42, 0x03, 0x22, 0xF2, 0x26, 0x2A, 0xE6, 0x04, 0x06, 0x05, 0x04, 0x06,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*窈6130*/},\n        {\n\n                0x06, 0x12, 0xAA, 0x06, 0xF2, 0x03, 0xF2, 0x06, 0xAA, 0x12, 0x06, 0x08, 0x09, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x09, 0x0C,/*窕6131*/},\n        {\n\n                0x06, 0x4A, 0x56, 0x52, 0xD2, 0x7B, 0xD2, 0x52, 0x56, 0xCA, 0x06, 0x02, 0x0A, 0x0B, 0x0A, 0x06,\n                0x02, 0x03, 0x02, 0x06, 0x0A, 0x02,/*窦6132*/},\n        {\n\n                0x06, 0x0A, 0xFE, 0xAA, 0xAA, 0xFB, 0xAA, 0xAA, 0xFE, 0x0A, 0x06, 0x02, 0x0A, 0x0A, 0x06, 0x02,\n                0x0F, 0x02, 0x06, 0x0A, 0x0A, 0x02,/*窠6133*/},\n        {\n\n                0x26, 0xEA, 0x56, 0x4A, 0x56, 0xD3, 0x16, 0x8A, 0x16, 0xEA, 0x26, 0x00, 0x0F, 0x05, 0x05, 0x0D,\n                0x0F, 0x00, 0x03, 0x08, 0x0F, 0x00,/*窬6134*/},\n        {\n\n                0x26, 0xAA, 0xAE, 0xBA, 0xAA, 0xAF, 0xAA, 0xBA, 0xAE, 0xAA, 0x26, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*窨6135*/},\n        {\n\n                0x16, 0x5A, 0x56, 0x3A, 0x92, 0x7F, 0x12, 0x3A, 0x56, 0x5A, 0x16, 0x01, 0x09, 0x09, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*窭6136*/},\n        {\n\n                0xF6, 0x1A, 0xF6, 0x52, 0x8A, 0xF3, 0x12, 0xF2, 0x16, 0xEA, 0x06, 0x07, 0x00, 0x0F, 0x0A, 0x0C,\n                0x03, 0x00, 0x0F, 0x0A, 0x0C, 0x01,/*窳6137*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x00, 0x00, 0x00, 0x00,/*衤6138*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0xA2, 0x3E, 0xC2, 0x0A, 0xD2, 0x3E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*衩6139*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xFC, 0x84, 0x44, 0x3F, 0x44, 0x84, 0xFC, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x00, 0x08, 0x0F,/*衲6140*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x40, 0x44, 0x44, 0xFC, 0x42, 0x42, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x00,/*衽6141*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0x90, 0x8C, 0xA3, 0x8C, 0x90, 0x20, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x06, 0x01, 0x00,/*衿6142*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x40, 0x44, 0x44, 0xFF, 0x44, 0x7C, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*袂6143*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0x82, 0x94, 0x90, 0xFF, 0x90, 0x94, 0x82, 0x00, 0x0F, 0x00, 0x00, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*袢6144*/},\n        {\n\n                0x84, 0x45, 0xF6, 0x4C, 0xA2, 0x14, 0x90, 0x9F, 0x90, 0x94, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x0F,/*裆6145*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x10, 0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*袷6146*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x48, 0xC4, 0xAB, 0x92, 0xAA, 0xC6, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*袼6147*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0xFF, 0x49, 0xC9, 0x49, 0x7F, 0x80, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*裉6148*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x11, 0xF2, 0x00, 0x34, 0x2C, 0xF7, 0x24, 0x24, 0x00, 0x0F, 0x08, 0x04, 0x03,\n                0x04, 0x09, 0x09, 0x0F, 0x09, 0x09,/*裢6149*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0x2F, 0x29, 0xE9, 0x29, 0x2F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*裎6150*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x10, 0x28, 0xA4, 0x23, 0x24, 0xA8, 0x10, 0x00, 0x00, 0x0F, 0x00, 0x09,\n                0x0E, 0x08, 0x0B, 0x0C, 0x0B, 0x08,/*裣6151*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xF9, 0x02, 0xF8, 0x4A, 0xFA, 0x02, 0xFE, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*裥6152*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0x44, 0x54, 0xD4, 0x7F, 0xD4, 0x54, 0x44, 0x00, 0x0F, 0x00, 0x00, 0x02,\n                0x01, 0x0F, 0x04, 0x01, 0x06, 0x09,/*裱6153*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x10, 0x90, 0xD4, 0x7F, 0x54, 0x58, 0xD4, 0x12, 0x00, 0x0F, 0x00, 0x01, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*褚6154*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x80, 0x5F, 0xF5, 0x55, 0xD5, 0x5F, 0xC0, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x09, 0x04, 0x02, 0x09, 0x08, 0x07,/*裼6155*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0x7C, 0xD6, 0x75, 0x5C, 0x54, 0x7C, 0x00, 0x00, 0x0F, 0x00, 0x02,\n                0x03, 0x02, 0x02, 0x0F, 0x02, 0x02,/*裨6156*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x00, 0xFE, 0xAA, 0xAA, 0xFA, 0xAA, 0xAE, 0x00, 0x00, 0x0F, 0x08, 0x06,\n                0x01, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*裾6157*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xAA, 0x92, 0xAE, 0x00, 0xAA, 0x92, 0xAE, 0x00, 0x0F, 0x00, 0x08, 0x0A,\n                0x04, 0x0B, 0x00, 0x0B, 0x04, 0x0B,/*裰6158*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x42, 0x27, 0x52, 0x4A, 0x52, 0x27, 0x42, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*褡6159*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x12, 0xEA, 0xBF, 0xA0, 0xAF, 0xF2, 0x19, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*褙6160*/},\n        {\n\n                0x84, 0x45, 0xF6, 0xAC, 0x10, 0xFC, 0x43, 0x5E, 0xF2, 0x5E, 0x40, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x0F, 0x02, 0x01, 0x0F, 0x01, 0x02,/*褓6161*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xAA, 0x9C, 0xC8, 0xBF, 0x88, 0x9C, 0xAA, 0x00, 0x0F, 0x00, 0x00, 0x08,\n                0x0A, 0x05, 0x04, 0x04, 0x0B, 0x08,/*褛6162*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x40, 0xFE, 0x2A, 0xEA, 0x2B, 0xEA, 0x2A, 0xEE, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*褊6163*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0x9E, 0x80, 0xBF, 0x88, 0x87, 0x94, 0xA4, 0x00, 0x0F, 0x00, 0x08, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*褴6164*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0xFE, 0x02, 0xF2, 0x52, 0xFF, 0x55, 0x15, 0xB1, 0x00, 0x0F, 0x08, 0x07, 0x02,\n                0x09, 0x06, 0x02, 0x07, 0x09, 0x0D,/*褫6165*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xD5, 0x49, 0x5F, 0x60, 0x55, 0x49, 0xDF, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*褶6166*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0x79, 0xCF, 0xF0, 0x97, 0xFD, 0x97, 0xF0, 0x00, 0x0F, 0x00, 0x00, 0x08,\n                0x0F, 0x04, 0x04, 0x07, 0x04, 0x0E,/*襁6167*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0x4C, 0x55, 0x45, 0xDF, 0x45, 0x55, 0x4C, 0x00, 0x0F, 0x00, 0x00, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*襦6168*/},\n        {\n\n                0x45, 0xF6, 0xAC, 0x00, 0xAA, 0x7F, 0xAA, 0xB4, 0xAA, 0x7F, 0xAA, 0x00, 0x0F, 0x00, 0x00, 0x02,\n                0x02, 0x0A, 0x0F, 0x02, 0x02, 0x02,/*襻6169*/},\n        {\n\n                0x02, 0x02, 0xE2, 0x02, 0x02, 0xFE, 0x42, 0x42, 0x42, 0x4A, 0x06, 0x08, 0x06, 0x01, 0x02, 0x04,\n                0x0F, 0x08, 0x08, 0x08, 0x08, 0x08,/*疋6170*/},\n        {\n\n                0x21, 0x11, 0xED, 0xB1, 0xA1, 0xBF, 0xA9, 0xA9, 0xE9, 0x29, 0x23, 0x00, 0x00, 0x0F, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0F, 0x00, 0x00,/*胥6171*/},\n        {\n\n                0xD6, 0xBA, 0xD2, 0x96, 0x00, 0xFC, 0x24, 0xE4, 0x3F, 0xE4, 0x0C, 0x04, 0x04, 0x0F, 0x02, 0x08,\n                0x07, 0x08, 0x05, 0x02, 0x05, 0x08,/*皲6172*/},\n        {\n\n                0x94, 0x6E, 0x45, 0xCC, 0x16, 0xFC, 0x24, 0xE4, 0x3F, 0xE4, 0x0C, 0x08, 0x05, 0x02, 0x05, 0x08,\n                0x07, 0x08, 0x05, 0x02, 0x05, 0x08,/*皴6173*/},\n        {\n\n                0x20, 0xAA, 0xF2, 0x2E, 0x60, 0x90, 0x8C, 0xA3, 0x8C, 0x90, 0x20, 0x01, 0x08, 0x0F, 0x00, 0x00,\n                0x00, 0x00, 0x08, 0x06, 0x01, 0x00,/*矜6174*/},\n        {\n\n                0x40, 0x44, 0x54, 0x54, 0xD4, 0xFF, 0xD4, 0x54, 0x54, 0x44, 0x40, 0x04, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x00, 0x01, 0x02, 0x04, 0x04,/*耒6175*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x44, 0x00, 0x42, 0x42, 0xF2, 0x4A, 0x46, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x00, 0x00, 0x08, 0x0F, 0x00, 0x00,/*耔6176*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x44, 0x20, 0x18, 0x00, 0xFF, 0x08, 0xB0, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x08, 0x08, 0x04, 0x02, 0x01, 0x00,/*耖6177*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x44, 0x00, 0xFE, 0x92, 0x92, 0x92, 0x9E, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*耜6178*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x10, 0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0x10, 0x02, 0x01, 0x0F, 0x01, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*耠6179*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x00, 0xB2, 0x97, 0xD2, 0x92, 0x97, 0xB2, 0x02, 0x01, 0x0F, 0x01, 0x00,\n                0x08, 0x04, 0x03, 0x08, 0x08, 0x07,/*耢6180*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0xF2, 0x14, 0xD0, 0x5F, 0xD0, 0x14, 0xF2, 0x02, 0x01, 0x0F, 0x01, 0x0F,\n                0x00, 0x03, 0x02, 0x03, 0x08, 0x0F,/*耥6181*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x80, 0xBF, 0xA5, 0xFF, 0xA5, 0xBF, 0x80, 0x02, 0x01, 0x0F, 0x01, 0x0F,\n                0x00, 0x02, 0x03, 0x06, 0x08, 0x0F,/*耦6182*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0xAA, 0x9C, 0xC8, 0xBF, 0x88, 0x9C, 0xAA, 0x02, 0x01, 0x0F, 0x01, 0x08,\n                0x0A, 0x05, 0x04, 0x04, 0x0B, 0x08,/*耧6183*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0x08, 0xEA, 0xAF, 0xFA, 0xAF, 0xEA, 0x08, 0x02, 0x01, 0x0F, 0x01, 0x02,\n                0x0F, 0x02, 0x03, 0x0A, 0x0F, 0x02,/*耩6184*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0xFF, 0x11, 0xF5, 0x95, 0x35, 0x55, 0xB5, 0x02, 0x01, 0x0F, 0x09, 0x07,\n                0x02, 0x06, 0x02, 0x0A, 0x0F, 0x02,/*耨6185*/},\n        {\n\n                0x44, 0x54, 0xFF, 0x54, 0xFE, 0xAA, 0xFE, 0x9A, 0xAB, 0xFE, 0xAA, 0x02, 0x01, 0x0F, 0x09, 0x07,\n                0x04, 0x0E, 0x0B, 0x0A, 0x0A, 0x0E,/*耱6186*/},\n        {\n\n                0x48, 0x4A, 0xAA, 0xEA, 0xBF, 0xAA, 0xAE, 0xFA, 0xA9, 0x28, 0x30, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*耋6187*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x02, 0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x03, 0x02, 0x0F, 0x01,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*耵6188*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x02, 0xFC, 0x24, 0xFF, 0x24, 0xFC, 0x00, 0x02, 0x03, 0x02, 0x0F, 0x01,\n                0x0F, 0x01, 0x01, 0x09, 0x0F, 0x01,/*聃6189*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x12, 0x48, 0x44, 0x53, 0x64, 0xC8, 0x10, 0x02, 0x03, 0x02, 0x0F, 0x01,\n                0x00, 0x02, 0x04, 0x0B, 0x00, 0x00,/*聆6190*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x02, 0x2C, 0x24, 0x25, 0xE6, 0x24, 0x2C, 0x02, 0x03, 0x02, 0x0F, 0x01,\n                0x00, 0x08, 0x08, 0x0F, 0x00, 0x00,/*聍6191*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x02, 0x00, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x02, 0x03, 0x02, 0x0F, 0x01,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*聒6192*/},\n        {\n\n                0x02, 0xFE, 0x52, 0xFE, 0x02, 0x20, 0xAE, 0xAA, 0xBF, 0xAA, 0xAE, 0x02, 0x03, 0x02, 0x0F, 0x01,\n                0x00, 0x0B, 0x04, 0x03, 0x04, 0x0B,/*聩6193*/},\n        {\n\n                0xC8, 0xAA, 0xBA, 0xAF, 0xEA, 0x8A, 0xC4, 0xAB, 0x92, 0xAE, 0xC2, 0x04, 0x04, 0x07, 0x05, 0x06,\n                0x04, 0x05, 0x06, 0x0F, 0x02, 0x02,/*聱6194*/},\n        {\n\n                0x01, 0x1D, 0xF5, 0x55, 0x5F, 0x55, 0x5F, 0x55, 0xF5, 0x1D, 0x01, 0x04, 0x04, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x05, 0x04, 0x04,/*覃6195*/},\n        {\n\n                0x40, 0x42, 0xFE, 0x42, 0x40, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x00, 0x00, 0x0F, 0x00, 0x00,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*顸6196*/},\n        {\n\n                0x00, 0xFE, 0x12, 0xF2, 0x11, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x08, 0x07, 0x00, 0x0F, 0x00,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颀6197*/},\n        {\n\n                0x08, 0xE8, 0x29, 0xEA, 0x08, 0x00, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x08, 0x07, 0x00, 0x07, 0x02,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颃6198*/},\n        {\n\n                0x04, 0xA4, 0xA4, 0xBF, 0xA4, 0x04, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x00, 0x0F, 0x04, 0x04, 0x0F,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颉6199*/},\n        {\n\n                0xA8, 0xA4, 0xA3, 0xA4, 0xA8, 0x10, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颌6200*/},\n        {\n\n                0x80, 0x8F, 0x14, 0xF2, 0x99, 0x40, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x04, 0x03, 0x08, 0x0F, 0x02,\n                0x04, 0x09, 0x04, 0x03, 0x04, 0x09,/*颍6201*/},\n        {\n\n                0x24, 0x34, 0xAD, 0x66, 0x24, 0x94, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x09, 0x09, 0x04, 0x02, 0x05,\n                0x08, 0x09, 0x04, 0x03, 0x04, 0x09,/*颏6202*/},\n        {\n\n                0x08, 0x24, 0x2A, 0xB1, 0x62, 0x04, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x00, 0x0F, 0x05, 0x05, 0x0F,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颔6203*/},\n        {\n\n                0x47, 0xD5, 0x57, 0x50, 0x57, 0x55, 0x47, 0x00, 0xFD, 0x0B, 0xF9, 0x00, 0x01, 0x01, 0x09, 0x09,\n                0x07, 0x00, 0x00, 0x08, 0x06, 0x08,/*颚6204*/},\n        {\n\n                0xAE, 0xA8, 0xA8, 0xEF, 0xA8, 0xA8, 0xAE, 0x00, 0xFD, 0x0B, 0xF9, 0x0F, 0x00, 0x07, 0x00, 0x07,\n                0x08, 0x0F, 0x00, 0x08, 0x06, 0x08,/*颛6205*/},\n        {\n\n                0x41, 0x7F, 0x55, 0x55, 0xFF, 0x21, 0xF2, 0x1A, 0xD6, 0x12, 0xF2, 0x0B, 0x05, 0x0B, 0x05, 0x0B,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x09,/*颞6206*/},\n        {\n\n                0xD2, 0x57, 0xF2, 0x52, 0xF2, 0x57, 0xD2, 0x00, 0xFD, 0x0B, 0xF9, 0x0F, 0x02, 0x01, 0x02, 0x01,\n                0x0A, 0x0F, 0x00, 0x08, 0x06, 0x08,/*颟6207*/},\n        {\n\n                0xB0, 0x5B, 0xB5, 0x05, 0xB5, 0x5B, 0xB0, 0x00, 0xFD, 0x0B, 0xF9, 0x0A, 0x06, 0x02, 0x0F, 0x02,\n                0x06, 0x0A, 0x00, 0x08, 0x06, 0x08,/*颡6208*/},\n        {\n\n                0x40, 0xDF, 0x75, 0x55, 0xDF, 0x40, 0xF9, 0x0D, 0xEB, 0x09, 0xF9, 0x08, 0x05, 0x09, 0x0F, 0x01,\n                0x04, 0x09, 0x04, 0x03, 0x04, 0x09,/*颢6209*/},\n        {\n\n                0x4C, 0x55, 0x45, 0xDF, 0x45, 0x55, 0x4C, 0x00, 0xFD, 0x0B, 0xF9, 0x0F, 0x01, 0x07, 0x01, 0x07,\n                0x09, 0x0F, 0x00, 0x08, 0x06, 0x08,/*颥6210*/},\n        {\n\n                0x54, 0x4F, 0xE4, 0x5F, 0x55, 0xE4, 0x5D, 0x77, 0xDD, 0x35, 0x5D, 0x04, 0x04, 0x07, 0x05, 0x07,\n                0x05, 0x0D, 0x05, 0x07, 0x04, 0x04,/*颦6211*/},\n        {\n\n                0x00, 0xF8, 0x08, 0x08, 0x08, 0xEF, 0x8A, 0x8A, 0x8A, 0x8A, 0x18, 0x08, 0x07, 0x01, 0x01, 0x01,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*虍6212*/},\n        {\n\n                0x00, 0xFC, 0x24, 0x24, 0x24, 0x3F, 0xD5, 0x55, 0x55, 0x45, 0x6C, 0x08, 0x07, 0x09, 0x09, 0x0B,\n                0x05, 0x05, 0x05, 0x0B, 0x09, 0x09,/*虔6213*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x07, 0x08, 0x08, 0x08, 0x0F,/*虬6214*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFE, 0x02, 0xFE, 0x00, 0x00, 0x04, 0x04, 0x03, 0x02, 0x0B,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*虮6215*/},\n        {\n\n                0x21, 0xA1, 0x91, 0x8F, 0x85, 0xC5, 0x85, 0xA5, 0xA5, 0x9D, 0x01, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*虿6216*/},\n        {\n\n                0x02, 0xFE, 0x02, 0xFE, 0x02, 0x3C, 0x24, 0xFF, 0x24, 0xBC, 0x00, 0x08, 0x07, 0x00, 0x07, 0x08,\n                0x0A, 0x0A, 0x09, 0x09, 0x0B, 0x0C,/*虺6217*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x08, 0x24, 0x27, 0xA4, 0x64, 0x04, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x06, 0x09, 0x08, 0x08, 0x0E,/*虼6218*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x00, 0x08, 0xF9, 0x0A, 0x08, 0x08, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x00, 0x00, 0x0F, 0x08, 0x08, 0x08,/*虻6219*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x40, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x04, 0x04, 0x03, 0x02, 0x0B,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*蚨6220*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFF, 0x10, 0xFF, 0x20, 0x10, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x04, 0x07, 0x08, 0x0E,/*蚍6221*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x00, 0xFC, 0x84, 0x7F, 0x84, 0xFC, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x00, 0x0F, 0x00, 0x00, 0x08, 0x0F,/*蚋6222*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x04, 0x03, 0x06, 0x08, 0x0C,/*蚬6223*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x92, 0x92, 0xFE, 0x49, 0x49, 0x40, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0E,/*蚝6224*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x08, 0xE4, 0x03, 0x04, 0xE8, 0x10, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*蚧6225*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x20, 0x18, 0x87, 0x60, 0x07, 0x18, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x06, 0x05, 0x04, 0x05, 0x0E,/*蚣6226*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x12, 0x24, 0x00, 0xFF, 0x80, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x01, 0x01, 0x01, 0x0F, 0x00,/*蚪6227*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xF2, 0x92, 0x9E, 0x00, 0xFF, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x08, 0x08, 0x07, 0x00, 0x0F,/*蚓6228*/},\n        {\n\n                0x10, 0x96, 0x94, 0x94, 0x94, 0xDF, 0x94, 0x94, 0x94, 0x96, 0x10, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*蚩6229*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x04, 0xFF, 0x44, 0x44, 0xFF, 0x04, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*蚶6230*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*蛄6231*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xF2, 0x12, 0xF2, 0xFE, 0x02, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x03, 0x09, 0x09, 0x0F, 0x00,/*蚵6232*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFE, 0x0A, 0xFA, 0x4A, 0xCA, 0x04, 0x04, 0x03, 0x02, 0x0B,\n                0x04, 0x0B, 0x04, 0x03, 0x08, 0x0F,/*蛎6233*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x00, 0xF8, 0x48, 0xFF, 0x48, 0xF8, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x00, 0x0F, 0x04, 0x07, 0x04, 0x0F,/*蚰6234*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFC, 0x24, 0xFF, 0x24, 0xFC, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x01, 0x0F, 0x01, 0x01, 0x09, 0x0F,/*蚺6235*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x04, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x00, 0x0F, 0x01, 0x01, 0x01,/*蚱6236*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFE, 0x22, 0x22, 0xE1, 0x21, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x0F, 0x08, 0x08, 0x0F, 0x08,/*蚯6237*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x10, 0x4C, 0x53, 0x64, 0xC8, 0x10, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x02, 0x04, 0x0B, 0x00, 0x00,/*蛉6238*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x46, 0x2A, 0x92, 0x2A, 0x46, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x09, 0x09, 0x0F, 0x09, 0x09,/*蛏6239*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0xE7, 0x30, 0x08, 0xFF, 0x08, 0xF8, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x02, 0x0B, 0x06, 0x01, 0x08, 0x0F,/*蚴6240*/},\n        {\n\n                0x10, 0x91, 0x8F, 0x89, 0xA0, 0xDF, 0x85, 0x89, 0x9F, 0xA0, 0x30, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*蛩6241*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x94, 0xA4, 0xFF, 0xA4, 0x94, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x04, 0x02, 0x01, 0x06, 0x08,/*蛱6242*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*蛲6243*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x32, 0x2A, 0xE6, 0x22, 0x32, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x09, 0x09, 0x0F, 0x09, 0x09,/*蛭6244*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xFF, 0x00, 0xF2, 0x12, 0xFE, 0x12, 0xF2, 0x04, 0x04, 0x03, 0x0A, 0x07,\n                0x00, 0x03, 0x00, 0x0F, 0x02, 0x03,/*蛳6245*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xFC, 0x44, 0xFF, 0x44, 0xFF, 0x44, 0xFC, 0x04, 0x04, 0x03, 0x02, 0x0F,\n                0x04, 0x07, 0x04, 0x07, 0x04, 0x0F,/*蛐6246*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0xB2, 0x2E, 0xE0, 0x12, 0xFE, 0x11, 0x04, 0x04, 0x03, 0x02, 0x03,\n                0x09, 0x06, 0x09, 0x0A, 0x0B, 0x0A,/*蜓6247*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x92, 0x92, 0xFE, 0x91, 0x91, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*蛞6248*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x44, 0xAC, 0x15, 0x16, 0xAC, 0x44, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*蛴6249*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x40, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x08, 0x05, 0x02, 0x05, 0x08,/*蛟6250*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x25, 0x26, 0xFC, 0x26, 0x25, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x01, 0x01, 0x0F, 0x01, 0x01,/*蛘6251*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x80, 0x6C, 0x4A, 0xF9, 0x48, 0x4C, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x02, 0x02, 0x02, 0x0F, 0x02, 0x02,/*蛑6252*/},\n        {\n\n                0x00, 0xFF, 0x05, 0xBD, 0xA5, 0x85, 0xCD, 0x95, 0x95, 0xAD, 0x25, 0x08, 0x07, 0x08, 0x0B, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0B, 0x0C,/*蜃6253*/},\n        {\n\n                0x0A, 0xAA, 0xBF, 0x8A, 0xA0, 0xDE, 0x8A, 0x8A, 0xB9, 0x89, 0x08, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*蜇6254*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x00, 0xF2, 0x54, 0x5F, 0x54, 0xF2, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x00, 0x0F, 0x01, 0x01, 0x09, 0x0F,/*蛸6255*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x2F, 0x29, 0xE9, 0x29, 0x2F, 0x00, 0x04, 0x04, 0x03, 0x02, 0x0B,\n                0x05, 0x03, 0x01, 0x03, 0x05, 0x09,/*蜈6256*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x92, 0xFE, 0x91, 0xFC, 0x00, 0xFF, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x00, 0x01, 0x08, 0x0F,/*蜊6257*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x48, 0x54, 0xF3, 0x54, 0x48, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x04, 0x03, 0x08, 0x0F, 0x01, 0x06,/*蜍6258*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x2A, 0x32, 0x26, 0xAA, 0x71, 0x2D, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x01, 0x01, 0x09, 0x0F, 0x01, 0x01,/*蜉6259*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x45, 0xD6, 0x7C, 0xD6, 0x55, 0x54, 0x04, 0x04, 0x03, 0x02, 0x0B,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0C,/*蜣6260*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x22, 0xEA, 0xAA, 0xBF, 0xEA, 0x22, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x02, 0x0A, 0x0F, 0x00,/*蜻6261*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x04, 0xFF, 0x54, 0x54, 0xFF, 0x04, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x09, 0x05, 0x01, 0x01, 0x05, 0x09,/*蜞6262*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x28, 0xFF, 0x48, 0xFE, 0x12, 0xF2, 0x11, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x03, 0x00, 0x0F, 0x00,/*蜥6263*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xF4, 0x94, 0xF4, 0x04, 0xFF, 0x84, 0x65, 0x04, 0x04, 0x03, 0x02, 0x04,\n                0x04, 0x0A, 0x04, 0x03, 0x05, 0x0E,/*蜮6264*/},\n        {\n\n                0x22, 0xAA, 0xAA, 0xFF, 0x80, 0xC0, 0x80, 0xFF, 0xAA, 0xAA, 0x22, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*蜚6265*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x04, 0x02, 0x01, 0x0F, 0x01, 0x02,/*蜾6266*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFF, 0x25, 0xFD, 0xA5, 0xFF, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x0A, 0x0B, 0x0A, 0x0F,/*蝈6267*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x80, 0x5F, 0xF5, 0x55, 0xD5, 0xDF, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x02, 0x09, 0x04, 0x0B, 0x08, 0x07,/*蜴6268*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x7C, 0xD6, 0x7D, 0x54, 0x7C, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x02, 0x03, 0x02, 0x0F, 0x02, 0x02,/*蜱6269*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFF, 0xA9, 0xBD, 0xA9, 0xFF, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x07, 0x03, 0x0A, 0x0B, 0x0F,/*蜩6270*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x55, 0xB4, 0x9F, 0x94, 0xB5, 0x50, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x07, 0x08, 0x0A, 0x0B, 0x0C,/*蜷6271*/},\n        {\n\n                0x78, 0x48, 0xFF, 0xC8, 0x66, 0x9A, 0xF2, 0x03, 0xF2, 0x92, 0xF6, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*蜿6272*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xFD, 0x56, 0x7C, 0x00, 0xFE, 0x32, 0xCE, 0x04, 0x04, 0x03, 0x02, 0x0F,\n                0x05, 0x02, 0x04, 0x0F, 0x02, 0x01,/*螂6273*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xF8, 0x89, 0xA9, 0xBD, 0x8B, 0x89, 0x88, 0x04, 0x04, 0x03, 0x0A, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*蜢6274*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0xA2, 0xEA, 0xBA, 0xAF, 0xEA, 0xA2, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x0A, 0x0A, 0x0F, 0x00,/*蝽6275*/},\n        {\n\n                0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x00, 0xB2, 0x97, 0xD2, 0x97, 0xB2, 0x08, 0x08, 0x07, 0x04, 0x0E,\n                0x00, 0x04, 0x02, 0x0F, 0x02, 0x04,/*蝾6276*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xFA, 0x0A, 0x5A, 0xEF, 0x5A, 0x0A, 0xFA, 0x04, 0x04, 0x03, 0x02, 0x0F,\n                0x01, 0x01, 0x07, 0x01, 0x09, 0x0F,/*蝻6277*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xDD, 0x55, 0xD5, 0x55, 0xDD, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x05, 0x07, 0x05, 0x0F,/*蝠6278*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0xAA, 0xA6, 0xF3, 0xA6, 0xAA, 0x92, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*蝰6279*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x92, 0xFE, 0x53, 0x24, 0xFF, 0x80, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x01, 0x01, 0x0F, 0x00,/*蝌6280*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x02, 0x7D, 0xD5, 0x55, 0x7D, 0x01, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x0A, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*蝮6281*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0xBC, 0xAA, 0xFF, 0xA0, 0xAA, 0xBE, 0x04, 0x04, 0x03, 0x02, 0x03,\n                0x08, 0x09, 0x06, 0x04, 0x0A, 0x09,/*螋6282*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xE8, 0xA4, 0xEA, 0x09, 0xCA, 0x04, 0xE8, 0x04, 0x04, 0x03, 0x02, 0x0F,\n                0x02, 0x0F, 0x00, 0x03, 0x08, 0x0F,/*蝓6283*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x08, 0xF9, 0x4A, 0xC8, 0x27, 0xA4, 0x64, 0x04, 0x04, 0x03, 0x0A, 0x04,\n                0x0B, 0x08, 0x07, 0x09, 0x0F, 0x01,/*蝣6284*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x80, 0x95, 0xCC, 0xBF, 0x8C, 0x95, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0A, 0x05, 0x04, 0x0B, 0x00,/*蝼6285*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xF4, 0x55, 0x3E, 0x14, 0x7E, 0x55, 0xF4, 0x04, 0x04, 0x03, 0x02, 0x0F,\n                0x05, 0x05, 0x05, 0x05, 0x05, 0x0F,/*蝤6286*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x80, 0xFE, 0x2A, 0xEB, 0x2A, 0xEE, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x01, 0x07, 0x09, 0x0F,/*蝙6287*/},\n        {\n\n                0x28, 0x99, 0xAB, 0xBD, 0x8B, 0xD8, 0xA4, 0x97, 0x8A, 0x96, 0x22, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*蝥6288*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0xA0, 0x6A, 0xBA, 0xAF, 0xEA, 0xA2, 0x04, 0x04, 0x03, 0x02, 0x03,\n                0x00, 0x0A, 0x06, 0x0F, 0x06, 0x0A,/*螓6289*/},\n        {\n\n                0x48, 0xAA, 0xBA, 0xAF, 0xEA, 0xCA, 0xC4, 0xAB, 0x92, 0xAE, 0x42, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*螯6290*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xD2, 0x57, 0xF2, 0x52, 0xF2, 0x57, 0xD2, 0x04, 0x04, 0x03, 0x02, 0x0F,\n                0x02, 0x01, 0x02, 0x01, 0x0A, 0x0F,/*螨6291*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x52, 0xB7, 0x1A, 0x12, 0xB7, 0x5A, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x09, 0x07, 0x01, 0x01, 0x0F, 0x01,/*蟒6292*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFA, 0xAF, 0xAA, 0xAF, 0xFA, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0A, 0x06, 0x03, 0x06, 0x0A,/*蟆6293*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xFE, 0x02, 0xFA, 0xAA, 0xAE, 0xAA, 0xFA, 0x04, 0x04, 0x03, 0x0A, 0x07,\n                0x04, 0x02, 0x08, 0x0F, 0x02, 0x04,/*螈6294*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFE, 0xAA, 0xAB, 0xAA, 0xFE, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x04, 0x02, 0x0C, 0x09, 0x0C, 0x02,/*螅6295*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xBA, 0xA2, 0xB6, 0xEB, 0xB6, 0xA2, 0xBA, 0x04, 0x04, 0x03, 0x02, 0x0F,\n                0x00, 0x06, 0x05, 0x06, 0x08, 0x0F,/*螭6296*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xFE, 0x22, 0xAA, 0xFF, 0xAA, 0xFA, 0x22, 0x04, 0x04, 0x03, 0x0A, 0x07,\n                0x00, 0x0E, 0x0B, 0x0A, 0x0E, 0x00,/*螗6297*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xB2, 0x96, 0xDB, 0x96, 0xB2, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x08, 0x07, 0x02, 0x0A, 0x0E,/*螃6298*/},\n        {\n\n                0x28, 0xCA, 0xBA, 0x8F, 0xFA, 0xCA, 0xD4, 0xAB, 0x92, 0xAE, 0x42, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*螫6299*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xEA, 0xAF, 0xFA, 0xAF, 0xEA, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0B, 0x06, 0x03, 0x06, 0x0B,/*蟥6300*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xFA, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFA, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*螬6301*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x7D, 0x15, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x04, 0x04, 0x03, 0x02, 0x0B,\n                0x05, 0x09, 0x0F, 0x01, 0x05, 0x09,/*螵6302*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0x0D, 0xF4, 0x97, 0xF4, 0x0D, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x08, 0x0A, 0x0F, 0x0A, 0x08,/*螳6303*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x52, 0xB6, 0x12, 0x7E, 0x31, 0x55, 0x04, 0x04, 0x03, 0x0A, 0x07,\n                0x00, 0x06, 0x09, 0x0C, 0x01, 0x06,/*蟋6304*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x04, 0xBA, 0x6B, 0xBA, 0x2E, 0xB8, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0A, 0x05, 0x0A, 0x0F, 0x02,/*蟓6305*/},\n        {\n\n                0x90, 0x94, 0xD2, 0x97, 0xAA, 0x4A, 0x9A, 0xAA, 0xD6, 0x90, 0x90, 0x0B, 0x0A, 0x0F, 0x0A, 0x0F,\n                0x00, 0x0B, 0x0A, 0x0F, 0x0A, 0x0F,/*螽6306*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x08, 0xFA, 0xAE, 0xAB, 0xAE, 0xFA, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x02, 0x02, 0x02, 0x0F, 0x02, 0x02,/*蟑6307*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x7A, 0x22, 0xDA, 0xB7, 0xDA, 0x22, 0x52, 0x04, 0x04, 0x03, 0x02, 0x03,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*蟀6308*/},\n        {\n\n                0xA8, 0xA8, 0xE9, 0x99, 0x8B, 0x2D, 0xBD, 0x8B, 0xC9, 0x88, 0x98, 0x0B, 0x0A, 0x0F, 0x0A, 0x0F,\n                0x00, 0x0B, 0x0A, 0x0F, 0x0A, 0x0F,/*蟊6309*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xEA, 0xAF, 0xEA, 0x44, 0x33, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x0A, 0x04, 0x0E, 0x04, 0x03,/*蟛6310*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x82, 0xFA, 0xAA, 0xFF, 0xAA, 0xFA, 0x82, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x04, 0x0D, 0x0A, 0x0C, 0x02, 0x0C,/*蟪6311*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x52, 0xB6, 0x9A, 0xBE, 0x99, 0xB5, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x00, 0x0F, 0x0A, 0x0F, 0x0A, 0x0F,/*蟠6312*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xA2, 0xEB, 0xAA, 0xFE, 0xAA, 0xEB, 0xA2, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*蟮6313*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x12, 0xFA, 0x57, 0xFA, 0x57, 0x52, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x09, 0x0B, 0x05, 0x05, 0x0B, 0x09,/*蠖6314*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x9A, 0x6F, 0xAA, 0x2A, 0xAF, 0x5A, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x0A, 0x05, 0x0A, 0x0F, 0x02, 0x04,/*蠓6315*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0x78, 0x00, 0xFE, 0x15, 0xAD, 0xB7, 0xAC, 0x04, 0x04, 0x03, 0x02, 0x07,\n                0x08, 0x07, 0x00, 0x0E, 0x0A, 0x0E,/*蟾6316*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xFE, 0xAA, 0xFE, 0xAB, 0xFA, 0xAE, 0xEA, 0x04, 0x04, 0x0B, 0x06, 0x0B,\n                0x06, 0x0F, 0x02, 0x0F, 0x06, 0x0B,/*蠊6317*/},\n        {\n\n                0x78, 0x48, 0xFF, 0x48, 0xBA, 0xAF, 0xBA, 0xEA, 0xBA, 0xEF, 0xBA, 0x04, 0x04, 0x03, 0x0A, 0x07,\n                0x02, 0x04, 0x0B, 0x04, 0x0A, 0x0C,/*蠛6318*/},\n        {\n\n                0x84, 0xD4, 0xD6, 0xCD, 0xAD, 0x55, 0xE5, 0x95, 0xA7, 0xD4, 0xC0, 0x0B, 0x0A, 0x0F, 0x0A, 0x0B,\n                0x00, 0x0B, 0x0A, 0x0F, 0x0A, 0x0B,/*蠡6319*/},\n        {\n\n                0x98, 0xAA, 0xEA, 0xBA, 0xAA, 0xAF, 0xAA, 0xAA, 0xEA, 0x8A, 0x98, 0x0B, 0x0A, 0x0F, 0x0A, 0x0B,\n                0x00, 0x0B, 0x0A, 0x0F, 0x0A, 0x0B,/*蠹6320*/},\n        {\n\n                0x78, 0x48, 0xFF, 0xC8, 0x5F, 0xF5, 0x5F, 0x40, 0xFF, 0x55, 0x5F, 0x04, 0x04, 0x03, 0x02, 0x08,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x09,/*蠼6321*/},\n        {\n\n                0x50, 0x48, 0x47, 0x44, 0x44, 0xFC, 0x44, 0x44, 0x44, 0x44, 0x40, 0x00, 0x0F, 0x08, 0x08, 0x08,\n                0x0F, 0x08, 0x08, 0x08, 0x0F, 0x00,/*缶6322*/},\n        {\n\n                0x2F, 0x11, 0x8D, 0xD1, 0xAF, 0x80, 0xAF, 0x91, 0x8D, 0x11, 0x2F, 0x02, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0E, 0x02,/*罂6323*/},\n        {\n\n                0x82, 0x7A, 0xAA, 0xFF, 0xAA, 0xBA, 0x84, 0xDB, 0xA9, 0x5B, 0x82, 0x02, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0E, 0x02,/*罄6324*/},\n        {\n\n                0xA4, 0x23, 0xFE, 0x22, 0xFE, 0xA4, 0xA4, 0xBF, 0xD5, 0x55, 0x6C, 0x07, 0x04, 0x03, 0x0A, 0x07,\n                0x02, 0x03, 0x0A, 0x0F, 0x02, 0x03,/*罅6325*/},\n        {\n\n                0x92, 0x92, 0xFE, 0x91, 0x91, 0x00, 0xFE, 0x22, 0xFE, 0x21, 0x21, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x0F, 0x04, 0x03, 0x04, 0x0E,/*舐6326*/},\n        {\n\n                0x08, 0x24, 0x23, 0x26, 0x2A, 0x22, 0x24, 0x23, 0x26, 0x2A, 0x02, 0x04, 0x04, 0x04, 0x04, 0x04,\n                0x04, 0x04, 0x04, 0x04, 0x04, 0x04,/*竺6327*/},\n        {\n\n                0x84, 0x93, 0x96, 0x9A, 0x92, 0xF0, 0x94, 0x93, 0x96, 0x9A, 0x82, 0x00, 0x00, 0x00, 0x08, 0x08,\n                0x0F, 0x00, 0x00, 0x00, 0x00, 0x00,/*竽6328*/},\n        {\n\n                0x04, 0x13, 0x16, 0xFA, 0x12, 0x90, 0x14, 0x73, 0x56, 0xCA, 0x02, 0x08, 0x04, 0x03, 0x08, 0x08,\n                0x04, 0x05, 0x02, 0x05, 0x08, 0x08,/*笈6329*/},\n        {\n\n                0x04, 0x13, 0xD6, 0x9A, 0x92, 0x90, 0x94, 0x93, 0xF6, 0x8A, 0x82, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x08, 0x08, 0x07,/*笃6330*/},\n        {\n\n                0x84, 0x93, 0x96, 0xFA, 0x92, 0x90, 0x94, 0xF3, 0x96, 0x9A, 0x82, 0x00, 0x08, 0x06, 0x01, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*笄6331*/},\n        {\n\n                0x04, 0xF3, 0x16, 0x1A, 0x12, 0xF0, 0x14, 0x13, 0x16, 0xFA, 0x02, 0x08, 0x09, 0x04, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x08, 0x09, 0x0E,/*笕6332*/},\n        {\n\n                0x04, 0xE3, 0x26, 0x2A, 0xE2, 0x20, 0x24, 0xF3, 0x16, 0x1A, 0x02, 0x08, 0x07, 0x00, 0x00, 0x0F,\n                0x00, 0x00, 0x00, 0x03, 0x04, 0x08,/*笊6333*/},\n        {\n\n                0x04, 0xE3, 0xA6, 0xAA, 0xA2, 0xF8, 0x94, 0x93, 0x96, 0x8A, 0x02, 0x04, 0x04, 0x02, 0x02, 0x01,\n                0x0F, 0x00, 0x00, 0x04, 0x07, 0x00,/*笫6334*/},\n        {\n\n                0x88, 0x44, 0x33, 0x26, 0xEA, 0x22, 0x24, 0xE3, 0x26, 0x2A, 0xE2, 0x04, 0x04, 0x0A, 0x09, 0x04,\n                0x04, 0x02, 0x09, 0x08, 0x08, 0x07,/*笏6335*/},\n        {\n\n                0x24, 0x23, 0xE6, 0x2A, 0x22, 0x00, 0xE4, 0x23, 0x26, 0xAA, 0x62, 0x04, 0x04, 0x07, 0x02, 0x02,\n                0x00, 0x0F, 0x00, 0x04, 0x04, 0x03,/*筇6336*/},\n        {\n\n                0x04, 0xF3, 0x16, 0x1A, 0xD2, 0x50, 0x54, 0x53, 0xD6, 0x1A, 0x12, 0x00, 0x0F, 0x08, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0A, 0x0B, 0x08, 0x08,/*笸6337*/},\n        {\n\n                0x04, 0xE3, 0xA6, 0xAA, 0xA2, 0xA0, 0xA4, 0xA3, 0xA6, 0xEA, 0x02, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*笪6338*/},\n        {\n\n                0x44, 0x23, 0x36, 0x2A, 0x22, 0xF8, 0x24, 0x23, 0x26, 0x2A, 0x02, 0x08, 0x08, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x08, 0x08,/*笙6339*/},\n        {\n\n                0x84, 0x43, 0x26, 0x3A, 0xE2, 0xA0, 0xA4, 0xA3, 0xA6, 0xAA, 0x22, 0x00, 0x00, 0x00, 0x00, 0x0F,\n                0x02, 0x02, 0x02, 0x02, 0x02, 0x02,/*笮6340*/},\n        {\n\n                0x44, 0x23, 0xDA, 0x56, 0x52, 0x54, 0x53, 0xD2, 0x16, 0x12, 0xF2, 0x00, 0x00, 0x07, 0x02, 0x02,\n                0x02, 0x02, 0x0B, 0x08, 0x08, 0x07,/*笱6341*/},\n        {\n\n                0x08, 0x24, 0xA3, 0x26, 0x2A, 0x32, 0x24, 0x23, 0xA6, 0x2A, 0x02, 0x08, 0x08, 0x08, 0x0B, 0x08,\n                0x08, 0x0C, 0x0A, 0x09, 0x08, 0x08,/*笠6342*/},\n        {\n\n                0x44, 0x53, 0x56, 0x5A, 0x52, 0x50, 0x54, 0x53, 0x16, 0xFA, 0x02, 0x00, 0x0F, 0x05, 0x05, 0x05,\n                0x05, 0x07, 0x08, 0x08, 0x07, 0x00,/*笥6343*/},\n        {\n\n                0x84, 0x93, 0x52, 0x36, 0x12, 0x14, 0x13, 0x52, 0x56, 0x32, 0x02, 0x00, 0x00, 0x0F, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x00,/*笤6344*/},\n        {\n\n                0x24, 0x23, 0xF6, 0x2A, 0x22, 0xE0, 0x04, 0xE3, 0x26, 0x2A, 0xE2, 0x08, 0x06, 0x01, 0x08, 0x08,\n                0x07, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*笳6345*/},\n        {\n\n                0x84, 0x93, 0xA6, 0x0A, 0x22, 0x20, 0xF4, 0x23, 0x26, 0xEA, 0x02, 0x08, 0x04, 0x07, 0x08, 0x0A,\n                0x09, 0x08, 0x0A, 0x0A, 0x09, 0x08,/*笾6346*/},\n        {\n\n                0x44, 0x63, 0x56, 0x4A, 0x42, 0x40, 0x44, 0x43, 0x46, 0x6A, 0xC2, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x09, 0x09, 0x09, 0x09, 0x0F, 0x00,/*笞6347*/},\n        {\n\n                0x24, 0x23, 0xF6, 0xAA, 0x02, 0xE0, 0x24, 0x23, 0x26, 0xEA, 0x02, 0x01, 0x09, 0x0F, 0x00, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*筘6348*/},\n        {\n\n                0x04, 0xFB, 0x92, 0x56, 0x52, 0x04, 0x7B, 0xA2, 0x96, 0x8A, 0xC2, 0x02, 0x02, 0x02, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*筚6349*/},\n        {\n\n                0x84, 0xA3, 0x9A, 0x96, 0x92, 0xFC, 0x93, 0x92, 0x96, 0x92, 0x82, 0x08, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x07, 0x08, 0x08, 0x0C,/*筅6350*/},\n        {\n\n                0x94, 0xD3, 0xB6, 0x0A, 0xD2, 0x10, 0x14, 0xF3, 0x4E, 0x4A, 0x02, 0x0A, 0x04, 0x0B, 0x08, 0x0B,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x0A,/*筵6351*/},\n        {\n\n                0x44, 0x43, 0xA6, 0xAA, 0x92, 0x88, 0x94, 0xA3, 0xA6, 0x4A, 0x42, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*筌6352*/},\n        {\n\n                0xA4, 0x93, 0xAE, 0xAA, 0xAA, 0xE8, 0xAC, 0xBB, 0xA6, 0xEA, 0x82, 0x00, 0x02, 0x02, 0x0A, 0x0A,\n                0x0F, 0x02, 0x02, 0x02, 0x07, 0x00,/*筝6353*/},\n        {\n\n                0x24, 0x23, 0xFA, 0x26, 0x22, 0x1C, 0x53, 0x92, 0x16, 0x12, 0xF2, 0x04, 0x04, 0x03, 0x02, 0x00,\n                0x04, 0x04, 0x02, 0x09, 0x08, 0x07,/*筠6354*/},\n        {\n\n                0x04, 0x23, 0xA6, 0x2A, 0x22, 0xE0, 0x24, 0x23, 0xA6, 0x2A, 0x02, 0x08, 0x0A, 0x09, 0x0A, 0x08,\n                0x0F, 0x08, 0x0A, 0x09, 0x0A, 0x08,/*筮6355*/},\n        {\n\n                0x0C, 0xEB, 0xAA, 0xAE, 0xAA, 0xFC, 0xAB, 0xAA, 0xAE, 0xEA, 0x0A, 0x08, 0x0B, 0x0A, 0x06, 0x06,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*筻6356*/},\n        {\n\n                0x24, 0x23, 0xF6, 0xAA, 0x02, 0xF0, 0x94, 0xF3, 0x96, 0xFA, 0x02, 0x01, 0x09, 0x0F, 0x00, 0x00,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*筢6357*/},\n        {\n\n                0x04, 0xE3, 0xAA, 0xB6, 0xA2, 0xB8, 0xA4, 0xB3, 0xAA, 0xE6, 0x02, 0x00, 0x0F, 0x02, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*筲6358*/},\n        {\n\n                0x44, 0xE3, 0x1A, 0xE6, 0x02, 0x40, 0xB4, 0x2B, 0x22, 0xE6, 0x22, 0x00, 0x0F, 0x00, 0x03, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*筱6359*/},\n        {\n\n                0x84, 0xAB, 0xAA, 0xAE, 0xAA, 0xFC, 0xAB, 0xAA, 0xAE, 0xAA, 0x82, 0x00, 0x00, 0x0F, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0F, 0x00, 0x00,/*箐6360*/},\n        {\n\n                0x42, 0x45, 0x55, 0x57, 0x55, 0x7E, 0x55, 0x55, 0x57, 0x45, 0x41, 0x08, 0x0B, 0x09, 0x05, 0x05,\n                0x03, 0x05, 0x05, 0x05, 0x0B, 0x08,/*箦6361*/},\n        {\n\n                0x04, 0xF3, 0x16, 0x5A, 0xD2, 0x50, 0xF4, 0x53, 0xD6, 0x5A, 0x12, 0x00, 0x0F, 0x09, 0x09, 0x0D,\n                0x0B, 0x09, 0x0B, 0x0D, 0x09, 0x09,/*箧6362*/},\n        {\n\n                0x24, 0x23, 0xAA, 0xAE, 0xEA, 0xBC, 0xAB, 0xB2, 0xAE, 0xA2, 0x22, 0x01, 0x01, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*箸6363*/},\n        {\n\n                0x94, 0x93, 0x96, 0xBA, 0xD2, 0x94, 0x93, 0xBA, 0x96, 0x92, 0x92, 0x04, 0x02, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*箬6364*/},\n        {\n\n                0x24, 0x23, 0xF6, 0xAA, 0x22, 0xF0, 0x24, 0x23, 0x26, 0xFA, 0x22, 0x01, 0x09, 0x0F, 0x00, 0x00,\n                0x0F, 0x09, 0x09, 0x09, 0x0F, 0x00,/*箝6365*/},\n        {\n\n                0x24, 0x23, 0xFA, 0xA6, 0x4A, 0x5C, 0x2B, 0xAA, 0x2E, 0x5A, 0x42, 0x01, 0x09, 0x0F, 0x00, 0x04,\n                0x05, 0x05, 0x0F, 0x05, 0x05, 0x04,/*箨6366*/},\n        {\n\n                0x04, 0xFB, 0xAA, 0xAE, 0xAA, 0xFC, 0xAB, 0xAA, 0xAE, 0xFA, 0x02, 0x02, 0x0A, 0x06, 0x02, 0x02,\n                0x02, 0x02, 0x02, 0x0E, 0x02, 0x02,/*箅6367*/},\n        {\n\n                0x04, 0xF3, 0x56, 0x5A, 0x52, 0xF4, 0x53, 0x5A, 0x56, 0xF2, 0x02, 0x04, 0x05, 0x05, 0x05, 0x05,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x04,/*箪6368*/},\n        {\n\n                0x34, 0x13, 0x52, 0x36, 0x12, 0x1C, 0x13, 0x32, 0x56, 0x12, 0x32, 0x08, 0x09, 0x09, 0x09, 0x09,\n                0x0F, 0x09, 0x09, 0x09, 0x09, 0x08,/*箜6369*/},\n        {\n\n                0x34, 0x93, 0x72, 0x56, 0xD2, 0x1C, 0xD3, 0x52, 0x56, 0xD2, 0x32, 0x09, 0x08, 0x05, 0x02, 0x01,\n                0x00, 0x07, 0x08, 0x0A, 0x0B, 0x0C,/*箢6370*/},\n        {\n\n                0x24, 0xAB, 0xAA, 0xAE, 0xAA, 0xFC, 0xAB, 0xAA, 0xAE, 0xFA, 0x22, 0x08, 0x06, 0x00, 0x04, 0x02,\n                0x0F, 0x02, 0x04, 0x00, 0x0E, 0x00,/*箫6371*/},\n        {\n\n                0x04, 0xF3, 0x12, 0x56, 0x52, 0x54, 0x13, 0xFA, 0x16, 0xDA, 0x12, 0x08, 0x07, 0x00, 0x07, 0x05,\n                0x07, 0x08, 0x04, 0x03, 0x04, 0x0E,/*箴6372*/},\n        {\n\n                0x42, 0x5D, 0x55, 0x57, 0x55, 0x7E, 0x55, 0x55, 0x57, 0x5D, 0x41, 0x08, 0x0B, 0x09, 0x05, 0x05,\n                0x03, 0x05, 0x05, 0x05, 0x0B, 0x08,/*篑6373*/},\n        {\n\n                0x84, 0xFB, 0xAE, 0xAA, 0xAE, 0xAC, 0xAB, 0xAA, 0xAE, 0xFA, 0x82, 0x08, 0x0A, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x08,/*篁6374*/},\n        {\n\n                0x84, 0xE3, 0x1A, 0x26, 0x22, 0xE8, 0xAC, 0xAB, 0xBA, 0xA6, 0x22, 0x00, 0x0F, 0x00, 0x02, 0x0B,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*篌6375*/},\n        {\n\n                0x22, 0xE9, 0xAB, 0xBD, 0xA9, 0xEA, 0xA9, 0xBD, 0xAB, 0xE9, 0x21, 0x02, 0x0F, 0x02, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x0A, 0x0F, 0x02,/*篝6376*/},\n        {\n\n                0x04, 0xFB, 0x2A, 0xAE, 0xAA, 0xFC, 0x0B, 0xFA, 0xAE, 0xAA, 0x2A, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x0F, 0x08, 0x0F, 0x0A, 0x0A, 0x0A,/*篚6377*/},\n        {\n\n                0x0C, 0xEB, 0xAA, 0xAE, 0xFA, 0xAC, 0xFB, 0xAA, 0xAE, 0xEA, 0x0A, 0x0A, 0x0A, 0x0A, 0x06, 0x02,\n                0x0F, 0x02, 0x06, 0x0A, 0x0A, 0x0A,/*篥6378*/},\n        {\n\n                0x04, 0xFB, 0x8A, 0xDE, 0xAA, 0xAC, 0xAB, 0xDA, 0x8E, 0xFA, 0x02, 0x00, 0x0F, 0x0A, 0x0A, 0x0A,\n                0x00, 0x07, 0x0A, 0x0A, 0x09, 0x0C,/*篦6379*/},\n        {\n\n                0x04, 0xF3, 0x0A, 0xEE, 0xAA, 0xAC, 0xFB, 0xAA, 0x6E, 0xAA, 0x62, 0x08, 0x07, 0x08, 0x07, 0x08,\n                0x06, 0x02, 0x03, 0x07, 0x09, 0x0C,/*篪6380*/},\n        {\n\n                0x04, 0xD3, 0x56, 0xFA, 0x52, 0xD4, 0x43, 0x3A, 0x96, 0x12, 0x72, 0x08, 0x05, 0x03, 0x0F, 0x03,\n                0x05, 0x08, 0x06, 0x01, 0x06, 0x08,/*簌6381*/},\n        {\n\n                0x04, 0xBB, 0xAA, 0xAE, 0xBA, 0xEC, 0xBB, 0xEA, 0xAE, 0xBA, 0x82, 0x08, 0x07, 0x02, 0x04, 0x00,\n                0x09, 0x0A, 0x04, 0x0A, 0x09, 0x0C,/*篾6382*/},\n        {\n\n                0xF4, 0x0B, 0x02, 0xF6, 0x5A, 0x54, 0x53, 0xF2, 0x06, 0x0A, 0xFA, 0x09, 0x09, 0x08, 0x05, 0x03,\n                0x01, 0x07, 0x09, 0x08, 0x09, 0x0D,/*篼6383*/},\n        {\n\n                0x04, 0xFB, 0xAA, 0xAE, 0xFA, 0xAC, 0xAB, 0xFA, 0xAE, 0xEA, 0x0A, 0x08, 0x07, 0x00, 0x0F, 0x0A,\n                0x0A, 0x00, 0x07, 0x0A, 0x0A, 0x0D,/*簏6384*/},\n        {\n\n                0xF4, 0x53, 0x66, 0xFA, 0x42, 0x54, 0x03, 0xF2, 0x56, 0xD2, 0x4A, 0x07, 0x05, 0x04, 0x07, 0x04,\n                0x05, 0x08, 0x07, 0x00, 0x0F, 0x00,/*簖6385*/},\n        {\n\n                0x02, 0x01, 0xFD, 0x57, 0x55, 0x56, 0xD5, 0x55, 0x7F, 0x81, 0x01, 0x08, 0x0E, 0x0B, 0x0B, 0x0E,\n                0x0A, 0x0E, 0x0B, 0x0B, 0x0E, 0x0A,/*簋6386*/},\n        {\n\n                0x0C, 0xEB, 0xAA, 0xAE, 0xFA, 0xAC, 0xFB, 0xAA, 0xAE, 0xEA, 0x0A, 0x04, 0x04, 0x07, 0x04, 0x04,\n                0x0D, 0x06, 0x04, 0x07, 0x04, 0x04,/*簟6387*/},\n        {\n\n                0xB4, 0x6B, 0x3A, 0xEE, 0xAA, 0x04, 0xB3, 0x6A, 0x3E, 0xEA, 0xAA, 0x00, 0x0F, 0x09, 0x09, 0x09,\n                0x0B, 0x0D, 0x09, 0x09, 0x0F, 0x00,/*簪6388*/},\n        {\n\n                0xA4, 0x4B, 0xAE, 0x9A, 0xA2, 0xA4, 0xAB, 0x92, 0xB6, 0x4A, 0xA2, 0x08, 0x08, 0x0B, 0x0E, 0x0A,\n                0x0A, 0x0A, 0x0E, 0x0B, 0x08, 0x08,/*簦6389*/},\n        {\n\n                0x0A, 0xFD, 0xAB, 0xFD, 0x09, 0xFA, 0x49, 0xC9, 0x7F, 0xC9, 0x19, 0x0A, 0x07, 0x02, 0x07, 0x0A,\n                0x07, 0x08, 0x05, 0x02, 0x05, 0x08,/*簸6390*/},\n        {\n\n                0xD4, 0x53, 0xFA, 0x56, 0xD2, 0x04, 0xE3, 0x5A, 0x56, 0x72, 0xC2, 0x05, 0x03, 0x0F, 0x03, 0x05,\n                0x00, 0x0B, 0x04, 0x03, 0x04, 0x0B,/*籁6391*/},\n        {\n\n                0x12, 0x11, 0xFD, 0x93, 0xB9, 0xAA, 0x95, 0xA9, 0x9B, 0xA9, 0xB9, 0x01, 0x09, 0x0F, 0x00, 0x0F,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x0F,/*籀6392*/},\n        {\n\n                0x00, 0xFE, 0x92, 0x91, 0x80, 0xFF, 0x80, 0x92, 0x92, 0xFE, 0x00, 0x08, 0x08, 0x04, 0x02, 0x01,\n                0x00, 0x01, 0x02, 0x04, 0x08, 0x08,/*臾6393*/},\n        {\n\n                0x00, 0x3E, 0x2A, 0xEA, 0x29, 0x20, 0x2A, 0xEA, 0x2A, 0x3E, 0x00, 0x01, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*舁6394*/},\n        {\n\n                0x20, 0xA2, 0x6A, 0xBA, 0xAE, 0x2B, 0xAA, 0xAA, 0xEA, 0xA2, 0x20, 0x01, 0x00, 0x0F, 0x0A, 0x0A,\n                0x08, 0x0A, 0x0A, 0x0F, 0x00, 0x01,/*舂6395*/},\n        {\n\n                0x00, 0xBE, 0xEA, 0xAA, 0xA9, 0xA0, 0xAA, 0xAA, 0xAA, 0xBE, 0x80, 0x09, 0x06, 0x00, 0x06, 0x00,\n                0x06, 0x00, 0x06, 0x08, 0x08, 0x07,/*舄6396*/},\n        {\n\n                0x00, 0xFE, 0xAA, 0xAA, 0xAB, 0xAA, 0xAA, 0xAA, 0xAA, 0xFE, 0x00, 0x0A, 0x0A, 0x06, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x06, 0x0A, 0x0A,/*臬6397*/},\n        {\n\n                0xF8, 0x0C, 0xFB, 0x08, 0xF8, 0x08, 0xF8, 0x22, 0xFE, 0x22, 0xFE, 0x07, 0x04, 0x07, 0x04, 0x03,\n                0x02, 0x03, 0x0A, 0x0F, 0x08, 0x0F,/*衄6398*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x08, 0x08, 0x0F, 0x08, 0x08,/*舡6399*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x07, 0x04, 0x07, 0x04, 0x0F,/*舢6400*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0x38, 0xC1, 0x06, 0xC0, 0x3C, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x08, 0x04, 0x03, 0x04, 0x08,/*舣6401*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0x00, 0xFF, 0x10, 0x10, 0xFF, 0x10, 0x0C, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x04, 0x02, 0x07, 0x08, 0x0E,/*舭6402*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0xF8, 0x88, 0xFF, 0x88, 0xF8, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x01, 0x00, 0x0F, 0x00, 0x01,/*舯6403*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0xFE, 0x12, 0xF2, 0x11, 0xF1, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x04, 0x03, 0x08, 0x05, 0x02, 0x0D,/*舨6404*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0x04, 0xFD, 0x26, 0x24, 0xE4, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x08, 0x07, 0x00, 0x08, 0x0F,/*舫6405*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0x00, 0xF2, 0x12, 0xF2, 0x02, 0xFE, 0x02, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x03, 0x01, 0x09, 0x08, 0x0F, 0x00,/*舸6406*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0xF0, 0x90, 0x9F, 0x92, 0xF2, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x08, 0x07, 0x00, 0x00, 0x00, 0x01,/*舻6407*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0xF8, 0x48, 0xFF, 0x48, 0xF8, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x0F, 0x04, 0x07, 0x04, 0x0F,/*舳6408*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x08, 0x07, 0xFC, 0x24, 0x24, 0x04, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x00, 0x0F, 0x01, 0x01, 0x01,/*舴6409*/},\n        {\n\n                0x40, 0xFC, 0x56, 0x65, 0xFE, 0x12, 0xFE, 0x12, 0xFE, 0x92, 0xF2, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x04, 0x0F,/*舾6410*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x00, 0xF2, 0x54, 0x5F, 0x54, 0xF2, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x00, 0x0F, 0x01, 0x01, 0x09, 0x0F,/*艄6411*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0x00, 0xFF, 0xA5, 0xA5, 0xE5, 0x55, 0x57, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x07, 0x02, 0x02, 0x07, 0x09, 0x0D,/*艉6412*/},\n        {\n\n                0x40, 0xFE, 0x4B, 0x52, 0xFE, 0x89, 0xA9, 0xBD, 0x8B, 0x89, 0x88, 0x08, 0x07, 0x01, 0x0A, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*艋6413*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0x00, 0xF5, 0x56, 0x5C, 0x56, 0xF5, 0x04, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x05, 0x05, 0x05, 0x0F, 0x00,/*艏6414*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0xF8, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFA, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0F, 0x00,/*艚6415*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0x08, 0xFA, 0xAE, 0xFB, 0xAE, 0xFA, 0x08, 0x08, 0x07, 0x08, 0x0F, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*艟6416*/},\n        {\n\n                0x20, 0xFE, 0xAB, 0xFE, 0x00, 0x9A, 0x6F, 0xAA, 0x2A, 0xAF, 0x5A, 0x08, 0x07, 0x08, 0x0F, 0x00,\n                0x0A, 0x05, 0x0A, 0x0F, 0x02, 0x04,/*艨6417*/},\n        {\n\n                0x88, 0x88, 0x94, 0x94, 0x92, 0xD9, 0x92, 0xB4, 0x94, 0x88, 0x88, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*衾6418*/},\n        {\n\n                0x80, 0x9E, 0x92, 0x97, 0x9A, 0xD2, 0x9A, 0xDE, 0xD0, 0xB0, 0x80, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*袅6419*/},\n        {\n\n                0xA2, 0x92, 0x8F, 0xA2, 0xA2, 0xDE, 0x80, 0xBE, 0xA2, 0xA2, 0xBE, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*袈6420*/},\n        {\n\n                0x82, 0x92, 0x96, 0x8A, 0x82, 0xDF, 0x8A, 0x8A, 0x97, 0x92, 0x82, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*裘6421*/},\n        {\n\n                0xA2, 0x94, 0x81, 0xA2, 0xA8, 0xE6, 0xA0, 0x9F, 0x90, 0x92, 0x84, 0x04, 0x04, 0x02, 0x0E, 0x09,\n                0x04, 0x01, 0x02, 0x04, 0x0A, 0x08,/*裟6422*/},\n        {\n\n                0x20, 0x1F, 0x75, 0x55, 0x77, 0x80, 0x0A, 0x2E, 0x7B, 0x2E, 0x0A, 0x09, 0x09, 0x05, 0x0D, 0x0B,\n                0x01, 0x03, 0x05, 0x05, 0x0B, 0x09,/*襞6423*/},\n        {\n\n                0x89, 0xAA, 0xF8, 0xAA, 0x01, 0xFE, 0x22, 0x22, 0xFE, 0x21, 0x21, 0x08, 0x04, 0x03, 0x00, 0x00,\n                0x0F, 0x04, 0x08, 0x03, 0x04, 0x0E,/*羝6424*/},\n        {\n\n                0x89, 0xAA, 0xF8, 0xAA, 0x41, 0xA2, 0x92, 0x8A, 0x96, 0xA2, 0x40, 0x08, 0x04, 0x03, 0x00, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*羟6425*/},\n        {\n\n                0x25, 0xFE, 0x25, 0x00, 0x24, 0x96, 0x65, 0x44, 0x44, 0xD6, 0x2C, 0x09, 0x07, 0x01, 0x00, 0x09,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*羧6426*/},\n        {\n\n                0x89, 0xAA, 0xF8, 0xAA, 0x01, 0x9F, 0x75, 0xD5, 0x55, 0x5F, 0xC0, 0x08, 0x04, 0x03, 0x00, 0x01,\n                0x06, 0x05, 0x04, 0x0D, 0x08, 0x07,/*羯6427*/},\n        {\n\n                0x25, 0xFE, 0x25, 0x00, 0x16, 0x94, 0x7C, 0x17, 0xD4, 0x14, 0x96, 0x09, 0x07, 0x01, 0x08, 0x06,\n                0x01, 0x0A, 0x05, 0x03, 0x05, 0x08,/*羰6428*/},\n        {\n\n                0xA2, 0xAA, 0xAA, 0xEB, 0xAA, 0xBE, 0xAA, 0xEB, 0xAA, 0xEA, 0xA2, 0x02, 0x01, 0x0A, 0x0B, 0x06,\n                0x01, 0x0A, 0x05, 0x02, 0x05, 0x0E,/*羲6429*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x24, 0x00, 0xF8, 0x00, 0xFF, 0x00, 0xF8, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x00, 0x07, 0x04, 0x07, 0x04, 0x0F,/*籼6430*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x24, 0x10, 0xEC, 0x0B, 0x88, 0x78, 0x08, 0x01, 0x00, 0x0F, 0x00, 0x09,\n                0x04, 0x02, 0x01, 0x02, 0x04, 0x08,/*敉6431*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x04, 0xFE, 0x42, 0x7E, 0x42, 0x42, 0x7E, 0x01, 0x00, 0x0F, 0x00, 0x01,\n                0x07, 0x08, 0x08, 0x08, 0x08, 0x0E,/*粑6432*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0xA8, 0x04, 0xFE, 0x0A, 0xFA, 0x4A, 0x4A, 0xCA, 0x01, 0x00, 0x0F, 0x08, 0x05,\n                0x0B, 0x04, 0x03, 0x08, 0x08, 0x07,/*粝6433*/},\n        {\n\n                0x18, 0x16, 0x54, 0x94, 0x14, 0xDF, 0x14, 0x94, 0x54, 0x16, 0x18, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*粜6434*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0xF2, 0x12, 0xFE, 0x12, 0xFE, 0x92, 0xF2, 0x01, 0x00, 0x0F, 0x01, 0x0F,\n                0x05, 0x04, 0x04, 0x04, 0x04, 0x0F,/*粞6435*/},\n        {\n\n                0x10, 0x11, 0x4A, 0x80, 0x24, 0xD3, 0x0A, 0x86, 0x4A, 0x12, 0x26, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*粢6436*/},\n        {\n\n                0x28, 0x26, 0x5C, 0x97, 0x0D, 0xC5, 0x20, 0x95, 0x49, 0x17, 0x20, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x0F, 0x01, 0x03, 0x05, 0x09, 0x09,/*粲6437*/},\n        {\n\n                0x95, 0x6E, 0xC4, 0x1F, 0x44, 0xEE, 0x55, 0x88, 0x67, 0x98, 0x07, 0x09, 0x06, 0x01, 0x03, 0x02,\n                0x0F, 0x02, 0x01, 0x0E, 0x01, 0x0E,/*粼6438*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x86, 0x92, 0x92, 0x93, 0x92, 0x92, 0x86, 0x01, 0x00, 0x0F, 0x01, 0x04,\n                0x02, 0x08, 0x0F, 0x00, 0x02, 0x04,/*粽6439*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x90, 0x54, 0xB6, 0x5D, 0xB4, 0x56, 0x94, 0x01, 0x00, 0x0F, 0x01, 0x08,\n                0x0A, 0x0A, 0x05, 0x04, 0x02, 0x00,/*糁6440*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x10, 0xFC, 0x4B, 0x38, 0xEA, 0x2E, 0x08, 0x01, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x09, 0x05, 0x03, 0x05, 0x09,/*糇6441*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x44, 0xAB, 0x92, 0xAE, 0xA0, 0xBF, 0xA4, 0x01, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x0A, 0x0F,/*糌6442*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0xE8, 0x99, 0x4A, 0x08, 0xEC, 0x9B, 0x48, 0x01, 0x00, 0x0F, 0x01, 0x06,\n                0x05, 0x0E, 0x00, 0x06, 0x05, 0x0E,/*糍6443*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x11, 0xCD, 0x51, 0x5F, 0x55, 0xD5, 0x13, 0x01, 0x00, 0x0F, 0x01, 0x00,\n                0x0F, 0x01, 0x01, 0x09, 0x0F, 0x00,/*糈6444*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x48, 0x29, 0x1B, 0xCD, 0x7D, 0x0B, 0x18, 0x01, 0x00, 0x0F, 0x01, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*糅6445*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x00, 0xFE, 0xAB, 0xAA, 0xAA, 0xFE, 0x00, 0x01, 0x00, 0x0F, 0x01, 0x08,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0B,/*糗6446*/},\n        {\n\n                0x24, 0xA8, 0xFF, 0x24, 0x79, 0xCF, 0xF0, 0x97, 0xFD, 0x97, 0xF0, 0x01, 0x00, 0x0F, 0x01, 0x08,\n                0x0F, 0x04, 0x04, 0x07, 0x04, 0x0E,/*糨6447*/},\n        {\n\n                0x00, 0xFF, 0x49, 0x49, 0xC9, 0x49, 0x49, 0x49, 0x49, 0x7F, 0x80, 0x00, 0x0F, 0x08, 0x04, 0x00,\n                0x01, 0x02, 0x04, 0x06, 0x09, 0x08,/*艮6448*/},\n        {\n\n                0x7F, 0x55, 0xB5, 0xDF, 0xC0, 0xAD, 0x99, 0x8F, 0xB9, 0x49, 0x68, 0x08, 0x08, 0x0F, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0F, 0x08, 0x08,/*暨6449*/},\n        {\n\n                0x80, 0x95, 0x89, 0xE1, 0x9F, 0x80, 0x95, 0xE9, 0x81, 0x9F, 0x80, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x0F, 0x00, 0x00, 0x00,/*羿6450*/},\n        {\n\n                0x48, 0x44, 0x53, 0x64, 0xC8, 0x08, 0x91, 0xFF, 0x08, 0x91, 0xFF, 0x00, 0x02, 0x04, 0x0B, 0x00,\n                0x01, 0x08, 0x0F, 0x01, 0x08, 0x0F,/*翎6451*/},\n        {\n\n                0x08, 0x08, 0x74, 0x54, 0x56, 0x55, 0x56, 0x54, 0x74, 0x08, 0x08, 0x09, 0x0B, 0x05, 0x09, 0x0F,\n                0x00, 0x09, 0x0B, 0x05, 0x09, 0x0F,/*翕6452*/},\n        {\n\n                0x48, 0x48, 0x2A, 0xFA, 0xAF, 0xAA, 0xAA, 0xAC, 0xFA, 0x09, 0x08, 0x09, 0x0B, 0x05, 0x09, 0x0F,\n                0x00, 0x09, 0x0B, 0x05, 0x09, 0x0F,/*翥6453*/},\n        {\n\n                0x22, 0x2A, 0x2A, 0x2A, 0x7F, 0x00, 0x7F, 0x2A, 0x2A, 0x2A, 0x22, 0x09, 0x0B, 0x05, 0x09, 0x0F,\n                0x00, 0x09, 0x0B, 0x05, 0x09, 0x0F,/*翡6454*/},\n        {\n\n                0x02, 0xFE, 0x2A, 0x2B, 0xAA, 0xFE, 0x02, 0x3B, 0x82, 0xFE, 0x02, 0x09, 0x0B, 0x05, 0x09, 0x0F,\n                0x00, 0x09, 0x0B, 0x05, 0x09, 0x0F,/*翦6455*/},\n        {\n\n                0x80, 0xFE, 0x2A, 0xEB, 0x2A, 0xEE, 0x91, 0xFF, 0x08, 0x91, 0xFF, 0x00, 0x0F, 0x01, 0x07, 0x09,\n                0x0F, 0x08, 0x0F, 0x01, 0x08, 0x0F,/*翩6456*/},\n        {\n\n                0xC1, 0xDD, 0x55, 0xDD, 0xC1, 0x08, 0x91, 0xFF, 0x08, 0x91, 0xFF, 0x0F, 0x02, 0x07, 0x0A, 0x0F,\n                0x01, 0x08, 0x0F, 0x01, 0x08, 0x0F,/*翮6457*/},\n        {\n\n                0x7F, 0x59, 0x77, 0x5D, 0x75, 0x51, 0x04, 0x5B, 0x29, 0x5B, 0x42, 0x09, 0x0B, 0x05, 0x09, 0x0F,\n                0x00, 0x09, 0x0B, 0x05, 0x09, 0x0F,/*翳6458*/},\n        {\n\n                0x00, 0x40, 0x48, 0x6C, 0x6A, 0xD9, 0x58, 0x48, 0x64, 0x40, 0x00, 0x04, 0x02, 0x01, 0x00, 0x08,\n                0x0F, 0x00, 0x00, 0x01, 0x02, 0x04,/*糸6459*/},\n        {\n\n                0x0A, 0x2A, 0xBF, 0xCA, 0xA0, 0x9A, 0x8F, 0x52, 0x0E, 0x10, 0x38, 0x00, 0x0A, 0x06, 0x02, 0x0B,\n                0x0E, 0x02, 0x02, 0x07, 0x0A, 0x00,/*絷6460*/},\n        {\n\n                0x20, 0xA2, 0x7F, 0xAA, 0xEA, 0xAA, 0xAA, 0x6A, 0x7F, 0xA2, 0x20, 0x01, 0x00, 0x0A, 0x06, 0x0A,\n                0x0F, 0x02, 0x06, 0x0B, 0x02, 0x01,/*綦6461*/},\n        {\n\n                0x40, 0x3E, 0x4A, 0x6B, 0xDA, 0x4E, 0x44, 0x2B, 0x92, 0x2E, 0x42, 0x00, 0x09, 0x05, 0x01, 0x09,\n                0x0F, 0x01, 0x01, 0x05, 0x09, 0x00,/*綮6462*/},\n        {\n\n                0xA6, 0x9A, 0xF6, 0x9A, 0x95, 0x00, 0x92, 0xDA, 0xB6, 0x91, 0xC9, 0x0E, 0x08, 0x07, 0x04, 0x0E,\n                0x04, 0x02, 0x08, 0x0F, 0x02, 0x04,/*繇6463*/},\n        {\n\n                0x22, 0xA2, 0xFA, 0xAA, 0xEA, 0xBF, 0xAA, 0xAA, 0xFA, 0x22, 0x22, 0x0A, 0x07, 0x0A, 0x0F, 0x02,\n                0x0B, 0x04, 0x05, 0x0E, 0x05, 0x0C,/*纛6464*/},\n        {\n\n                0x22, 0xEA, 0xBF, 0xAA, 0x40, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x09, 0x05, 0x02, 0x05, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*麸6465*/},\n        {\n\n                0x92, 0x4A, 0xBF, 0x4A, 0x92, 0x54, 0x43, 0xFA, 0x42, 0x52, 0xFE, 0x0A, 0x0B, 0x05, 0x0B, 0x00,\n                0x02, 0x01, 0x07, 0x09, 0x0A, 0x07,/*麴6466*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xFF, 0x24, 0x00, 0xFE, 0x80, 0x40, 0xFF, 0x00, 0x08, 0x07, 0x04, 0x0F, 0x09,\n                0x08, 0x09, 0x08, 0x08, 0x0B, 0x08,/*赳6467*/},\n        {\n\n                0x20, 0xA4, 0x24, 0xFF, 0x24, 0x00, 0xFE, 0x52, 0x52, 0xFE, 0x00, 0x08, 0x07, 0x04, 0x0F, 0x09,\n                0x0A, 0x0B, 0x0A, 0x0A, 0x0B, 0x0A,/*趄6468*/},\n        {\n\n                0xA4, 0x24, 0xFF, 0xA4, 0x32, 0x4E, 0xFA, 0x02, 0xFC, 0x00, 0xFE, 0x0F, 0x04, 0x0F, 0x08, 0x0A,\n                0x09, 0x08, 0x08, 0x08, 0x0A, 0x0B,/*趔6469*/},\n        {\n\n                0xA4, 0x24, 0xFF, 0xA4, 0x02, 0x84, 0x50, 0x0F, 0xE4, 0x04, 0x1C, 0x0F, 0x04, 0x0F, 0x08, 0x09,\n                0x08, 0x0A, 0x09, 0x08, 0x09, 0x0A,/*趑6470*/},\n        {\n\n                0xA4, 0x24, 0xFF, 0x24, 0x2B, 0xDA, 0x7F, 0x6A, 0x5A, 0xFF, 0x2A, 0x0F, 0x04, 0x0F, 0x09, 0x08,\n                0x0D, 0x0A, 0x09, 0x0A, 0x0D, 0x08,/*趱6471*/},\n        {\n\n                0x20, 0xA4, 0xE4, 0x3F, 0xE4, 0x20, 0xFE, 0x42, 0xD2, 0x52, 0xCE, 0x09, 0x04, 0x03, 0x08, 0x0F,\n                0x01, 0x0F, 0x08, 0x05, 0x02, 0x0D,/*赧6472*/},\n        {\n\n                0x20, 0xE4, 0x3F, 0xE4, 0x20, 0x90, 0xD4, 0x7F, 0x54, 0xD8, 0x14, 0x09, 0x07, 0x08, 0x0F, 0x01,\n                0x00, 0x0F, 0x05, 0x05, 0x0F, 0x00,/*赭6473*/},\n        {\n\n                0x7A, 0x4A, 0x4A, 0x7A, 0x00, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x00, 0x0B, 0x08, 0x06, 0x05, 0x08,\n                0x08, 0x08, 0x0F, 0x08, 0x08, 0x08,/*豇6474*/},\n        {\n\n                0x7A, 0x4A, 0x4A, 0x7A, 0x24, 0xE4, 0x24, 0x3F, 0x24, 0xE4, 0x04, 0x0B, 0x08, 0x06, 0x05, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*豉6475*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x00, 0x02, 0xFE, 0x02, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*酊6476*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x00, 0x42, 0xFE, 0x42, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x00, 0x0F, 0x00,/*酐6477*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x28, 0x48, 0xFF, 0x08, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*酎6478*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x20, 0xFC, 0x10, 0xFF, 0x88, 0xFC, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x07, 0x08, 0x09, 0x08, 0x0E,/*酏6479*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x00, 0xC8, 0x7F, 0xC8, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x0F, 0x04, 0x0F,/*酤6480*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x08, 0xFF, 0x24, 0x24, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x0F, 0x01, 0x01,/*酢6481*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x0C, 0xE5, 0x86, 0x4C, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x07, 0x08, 0x0E,/*酡6482*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x50, 0xCE, 0x48, 0xFF, 0x48, 0x40, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*酰6483*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x88, 0xD7, 0xA4, 0x9C, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x0F, 0x04, 0x0F,/*酩6484*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x00, 0xCF, 0x52, 0xD9, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x0F, 0x05, 0x0F,/*酯6485*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0xCA, 0x7E, 0x42, 0x7E, 0x4A, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x08, 0x07, 0x00, 0x00, 0x00, 0x00,/*酽6486*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xF8, 0x8A, 0xFA, 0x02, 0xFA, 0x8A, 0xFA, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F,/*酾6487*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x00, 0x2F, 0xE9, 0x2F, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x09, 0x0F, 0x09,/*酲6488*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0x48, 0x54, 0xF3, 0x54, 0x48, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x04, 0x03, 0x08, 0x0F, 0x01, 0x06,/*酴6489*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0x4A, 0x52, 0x46, 0xE9, 0x45, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x01, 0x02, 0x08, 0x0F, 0x00,/*酹6490*/},\n        {\n\n                0xFD, 0xA5, 0x9F, 0xA5, 0xFD, 0x00, 0xDF, 0x15, 0xD5, 0x9F, 0x40, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x00, 0x0F, 0x09, 0x07, 0x08, 0x0E,/*醌6491*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x0A, 0x3E, 0x4A, 0xFA, 0x00, 0xAA, 0xB3, 0xAA, 0x0F, 0x05, 0x05, 0x05, 0x05,\n                0x05, 0x0F, 0x00, 0x0F, 0x04, 0x0F,/*醅6492*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0xE4, 0x3F, 0xE4, 0xFE, 0x92, 0xFE, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x07, 0x02, 0x0B, 0x07, 0x08, 0x0F,/*醐6493*/},\n        {\n\n                0xFD, 0xA5, 0x9F, 0xA5, 0xFD, 0x40, 0x5F, 0x55, 0xD5, 0x55, 0x5F, 0x0F, 0x04, 0x04, 0x04, 0x0F,\n                0x08, 0x07, 0x08, 0x0F, 0x09, 0x09,/*醍6494*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x11, 0xCD, 0x51, 0x5F, 0xD5, 0x13, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x01, 0x09, 0x0F, 0x00,/*醑6495*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x10, 0xBA, 0xAE, 0xAB, 0xAA, 0xBA, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x08, 0x0F, 0x08, 0x0F, 0x08, 0x0F,/*醢6496*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0xFE, 0xAA, 0xFF, 0xAA, 0xFA, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x04, 0x03, 0x0E, 0x0B, 0x0A, 0x0E,/*醣6497*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x8B, 0x45, 0xAF, 0x5A, 0xA5, 0x4F, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0A, 0x0A, 0x09, 0x04, 0x02,/*醪6498*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0xAA, 0xBF, 0xE8, 0xBF, 0xAA, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0A, 0x06, 0x03, 0x06, 0x0A,/*醭6499*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x08, 0xFC, 0x57, 0x54, 0xFD, 0x56, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0D, 0x01, 0x0D, 0x01, 0x0D,/*醮6500*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x80, 0x6A, 0x0E, 0xEB, 0x0E, 0xEA, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x08, 0x0E, 0x0A, 0x0E, 0x0A, 0x0E,/*醯6501*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0x00, 0xFC, 0x54, 0xFF, 0x55, 0x55, 0x6C, 0x0F, 0x05, 0x05, 0x05, 0x02,\n                0x05, 0x05, 0x0A, 0x0F, 0x02, 0x05,/*醵6502*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xBE, 0xAA, 0xBF, 0xAA, 0xBF, 0xAA, 0xBE, 0x0F, 0x05, 0x05, 0x05, 0x08,\n                0x0B, 0x0E, 0x0A, 0x0E, 0x0B, 0x08,/*醴6503*/},\n        {\n\n                0xFA, 0x4A, 0x3E, 0x4A, 0xFA, 0x00, 0xFA, 0xAA, 0xFE, 0xA9, 0xF9, 0x0F, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0A, 0x02, 0x0B, 0x02, 0x0A,/*醺6504*/},\n        {\n\n                0x92, 0x92, 0x4A, 0x4A, 0x26, 0x9A, 0xF2, 0x22, 0xD2, 0x0A, 0x02, 0x04, 0x04, 0x02, 0x02, 0x09,\n                0x08, 0x07, 0x00, 0x00, 0x01, 0x02,/*豕6505*/},\n        {\n\n                0xF8, 0x28, 0xCF, 0x2A, 0xFA, 0x40, 0xD5, 0x76, 0x5C, 0x56, 0x55, 0x0F, 0x05, 0x04, 0x05, 0x0F,\n                0x02, 0x09, 0x09, 0x0F, 0x09, 0x09,/*鹾6506*/},\n        {\n\n                0x11, 0x11, 0xE9, 0xA7, 0xA5, 0xA5, 0xA5, 0xB5, 0xF5, 0x0D, 0x01, 0x08, 0x08, 0x06, 0x08, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x08, 0x08,/*趸6507*/},\n        {\n\n                0x10, 0x11, 0xEF, 0xA9, 0xB0, 0xAF, 0xA5, 0xA9, 0xEF, 0x10, 0x18, 0x08, 0x08, 0x06, 0x08, 0x08,\n                0x0F, 0x0A, 0x0A, 0x0A, 0x08, 0x08,/*跫6508*/},\n        {\n\n                0x0A, 0xAA, 0xBF, 0x8A, 0xA0, 0x9E, 0x8A, 0x8A, 0xB9, 0x89, 0x08, 0x08, 0x0B, 0x06, 0x0A, 0x0A,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*踅6509*/},\n        {\n\n                0x20, 0xDE, 0xAA, 0xCA, 0xFE, 0xAA, 0xCA, 0xAF, 0x92, 0xAB, 0x72, 0x08, 0x0B, 0x06, 0x0A, 0x0A,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*蹙6510*/},\n        {\n\n                0x7D, 0xA6, 0x94, 0xBF, 0x96, 0xBD, 0xC4, 0xAB, 0x92, 0xAE, 0x42, 0x08, 0x0B, 0x06, 0x0A, 0x0A,\n                0x0E, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*蹩6511*/},\n        {\n\n                0x00, 0x9E, 0x12, 0xF2, 0x9E, 0x08, 0x27, 0xC4, 0x04, 0x04, 0xFC, 0x08, 0x0F, 0x08, 0x07, 0x04,\n                0x00, 0x00, 0x00, 0x08, 0x08, 0x07,/*趵6512*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0x02, 0xFE, 0x02, 0x32, 0x2E, 0xE0, 0x07, 0x04, 0x03, 0x02, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*趿6513*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0x22, 0xFE, 0x22, 0x22, 0xFE, 0x22, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x06, 0x01, 0x00, 0x00, 0x0F, 0x00,/*趼6514*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x40, 0x48, 0x48, 0xFF, 0x48, 0x48, 0x40, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x04, 0x03, 0x00, 0x03, 0x04, 0x08,/*趺6515*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x10, 0xE8, 0x24, 0x23, 0x24, 0xE8, 0x10, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x07, 0x08, 0x08, 0x09, 0x09, 0x0C,/*跄6516*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x80, 0x42, 0xF2, 0x2E, 0x22, 0x22, 0xE2, 0x07, 0x04, 0x03, 0x02, 0x00,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*跖6517*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x10, 0xFC, 0x03, 0x48, 0x88, 0xFF, 0x08, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x0F, 0x00, 0x00, 0x08, 0x0F, 0x00,/*跗6518*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x20, 0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x20, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x07, 0x00, 0x07, 0x08, 0x0F, 0x00,/*跚6519*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0xBE, 0x22, 0xFA, 0x21, 0xA1, 0x20, 0x07, 0x04, 0x03, 0x02, 0x02,\n                0x01, 0x08, 0x0F, 0x00, 0x00, 0x03,/*跞6520*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0x0C, 0xE4, 0x05, 0x86, 0x44, 0x2C, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x00, 0x07, 0x09, 0x08, 0x08, 0x0E,/*跎6521*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x48, 0xFF, 0x08, 0xF8, 0x00, 0xFC, 0x04, 0xFC, 0x07, 0x04, 0x0B, 0x06, 0x03,\n                0x08, 0x0F, 0x00, 0x0F, 0x04, 0x0F,/*跏6522*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0xFC, 0x24, 0xE4, 0x3F, 0xE4, 0x0C, 0x07, 0x04, 0x03, 0x0A, 0x04,\n                0x03, 0x08, 0x05, 0x02, 0x05, 0x08,/*跛6523*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x30, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*跆6524*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x20, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*跬6525*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x84, 0xA4, 0xAF, 0x92, 0xAA, 0xA2, 0xB8, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*跷6526*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0x3F, 0x24, 0xD4, 0x1F, 0x24, 0x32, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x01, 0x01, 0x0F, 0x01, 0x01, 0x01,/*跸6527*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x50, 0x4E, 0xC8, 0x7F, 0xC8, 0x48, 0x40, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*跣6528*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x21, 0xE2, 0x10, 0x12, 0xFE, 0x11, 0x10, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x07, 0x08, 0x08, 0x0B, 0x08, 0x08,/*跹6529*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0x44, 0xAC, 0x15, 0x16, 0xAC, 0x44, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*跻6530*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x40, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*跤6531*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0xFC, 0x55, 0xD6, 0x54, 0x7C, 0x80, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x0F, 0x04, 0x01, 0x02, 0x05, 0x08,/*踉6532*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x00, 0x39, 0xC9, 0x49, 0x49, 0x4F, 0x60, 0x07, 0x04, 0x03, 0x02, 0x04,\n                0x02, 0x0C, 0x09, 0x0C, 0x01, 0x06,/*跽6533*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0xF8, 0xA8, 0xAF, 0xAA, 0xAA, 0xFA, 0x0F, 0x08, 0x07, 0x04, 0x02,\n                0x02, 0x02, 0x0F, 0x02, 0x02, 0x02,/*踔6534*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x00, 0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x40, 0x07, 0x04, 0x03, 0x02, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*踝6535*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x48, 0x47, 0xFC, 0x44, 0x40, 0xFE, 0x02, 0xFE, 0x07, 0x04, 0x03, 0x0A, 0x06,\n                0x01, 0x06, 0x00, 0x07, 0x02, 0x07,/*踟6536*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0xFE, 0x0A, 0xEA, 0x2A, 0xBE, 0x29, 0xE9, 0x07, 0x04, 0x03, 0x0A, 0x07,\n                0x00, 0x0B, 0x04, 0x03, 0x04, 0x0B,/*踬6537*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0xFC, 0x04, 0x85, 0xFE, 0xA4, 0xA4, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x07, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*踮6538*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x20, 0xAA, 0xB2, 0xA3, 0xB2, 0xAA, 0x20, 0x07, 0x04, 0x03, 0x02, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x0F, 0x00,/*踣6539*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x49, 0xFA, 0x49, 0x40, 0xFE, 0x32, 0xCE, 0x07, 0x04, 0x03, 0x0A, 0x06,\n                0x01, 0x06, 0x00, 0x0F, 0x02, 0x01,/*踯6540*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x64, 0xDC, 0x88, 0xAA, 0xFF, 0xAA, 0xBE, 0x0F, 0x08, 0x07, 0x04, 0x0A,\n                0x07, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*踺6541*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x04, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x07, 0x04, 0x03, 0x02, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*蹀6542*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0xAE, 0xA8, 0xA8, 0xEF, 0xA8, 0xA8, 0xAE, 0x07, 0x04, 0x03, 0x02, 0x0F,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0F,/*踹6543*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x08, 0xFA, 0xAA, 0xFE, 0xA9, 0xF9, 0x08, 0x0F, 0x08, 0x07, 0x04, 0x08,\n                0x0A, 0x0A, 0x0F, 0x0A, 0x0A, 0x08,/*踵6544*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x80, 0xBA, 0xAA, 0xFE, 0xA9, 0xB9, 0x80, 0x07, 0x04, 0x03, 0x02, 0x0F,\n                0x00, 0x02, 0x03, 0x06, 0x08, 0x0F,/*踽6545*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0xFE, 0x8A, 0xBE, 0xAB, 0xBE, 0x8A, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x07, 0x08, 0x0B, 0x04, 0x0A, 0x09,/*踱6546*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x44, 0xD5, 0x76, 0x5C, 0x56, 0x55, 0x44, 0x0F, 0x08, 0x07, 0x04, 0x0A,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*蹉6547*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0xFE, 0x2A, 0xEA, 0x2B, 0xEA, 0x2A, 0xEE, 0x07, 0x04, 0x03, 0x02, 0x0F,\n                0x01, 0x07, 0x01, 0x07, 0x09, 0x0F,/*蹁6548*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0x00, 0x48, 0x29, 0xDB, 0x7D, 0x0B, 0x18, 0x07, 0x04, 0x03, 0x02, 0x08,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*蹂6549*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x41, 0x7F, 0x55, 0x55, 0x55, 0xFF, 0x21, 0x0F, 0x08, 0x07, 0x04, 0x0B,\n                0x05, 0x0B, 0x00, 0x0B, 0x05, 0x0B,/*蹑6550*/},\n        {\n\n                0xCF, 0x09, 0xF9, 0x4F, 0xD2, 0x57, 0xF2, 0x52, 0xF2, 0x57, 0xD2, 0x07, 0x04, 0x03, 0x02, 0x0F,\n                0x02, 0x01, 0x02, 0x01, 0x0A, 0x0F,/*蹒6551*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0x86, 0xAA, 0xF6, 0xAA, 0xA1, 0xD5, 0x83, 0x07, 0x04, 0x03, 0x02, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*蹊6552*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0xFE, 0xAA, 0xAA, 0xEA, 0x52, 0xFE, 0x12, 0x07, 0x04, 0x03, 0x0A, 0x07,\n                0x05, 0x06, 0x05, 0x08, 0x0F, 0x00,/*蹰6553*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0xFE, 0x2A, 0xF2, 0x2A, 0xA2, 0xDE, 0x32, 0x07, 0x04, 0x03, 0x0A, 0x07,\n                0x09, 0x07, 0x09, 0x05, 0x03, 0x0C,/*蹶6554*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x25, 0xAC, 0xB7, 0xE4, 0xB7, 0xAC, 0x25, 0x0F, 0x08, 0x07, 0x04, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*蹼6555*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x40, 0xB6, 0x9A, 0xBE, 0x99, 0xB5, 0x50, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x0F, 0x0A, 0x0F, 0x0A, 0x0F, 0x00,/*蹯6556*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0x7A, 0xCB, 0x7A, 0x10, 0xFF, 0x12, 0x14, 0x07, 0x04, 0x03, 0x02, 0x09,\n                0x0F, 0x01, 0x0A, 0x07, 0x08, 0x0F,/*蹴6557*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x60, 0xD7, 0x5D, 0xF7, 0x55, 0xD7, 0x15, 0xF7, 0x07, 0x04, 0x03, 0x02, 0x05,\n                0x05, 0x07, 0x05, 0x0D, 0x08, 0x07,/*躅6558*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x40, 0xEA, 0x82, 0xEF, 0x5A, 0xEF, 0x4A, 0xFA, 0x07, 0x04, 0x03, 0x02, 0x0F,\n                0x00, 0x0F, 0x05, 0x07, 0x05, 0x0F,/*躏6559*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0xFE, 0xAA, 0xFF, 0xAA, 0xBE, 0x82, 0x07, 0x04, 0x03, 0x0A, 0x04,\n                0x0B, 0x0A, 0x0F, 0x0A, 0x09, 0x02,/*躔6560*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x9E, 0x00, 0xFA, 0x8D, 0xDA, 0xAD, 0xDA, 0xFD, 0x0F, 0x08, 0x07, 0x04, 0x00,\n                0x0F, 0x0A, 0x07, 0x0A, 0x07, 0x0C,/*躐6561*/},\n        {\n\n                0x9E, 0x12, 0xFE, 0x44, 0xAB, 0x9A, 0xBF, 0xAA, 0x9A, 0xBF, 0xAA, 0x07, 0x04, 0x03, 0x02, 0x0B,\n                0x08, 0x04, 0x03, 0x04, 0x04, 0x0B,/*躜6562*/},\n        {\n\n                0x9E, 0x12, 0xF2, 0x5E, 0x00, 0xEA, 0xAB, 0xEA, 0x44, 0x3F, 0x48, 0x07, 0x04, 0x03, 0x02, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*躞6563*/},\n        {\n\n                0x00, 0x24, 0x24, 0xAA, 0x92, 0x55, 0x29, 0xC8, 0x04, 0x00, 0x00, 0x00, 0x01, 0x05, 0x04, 0x02,\n                0x0A, 0x09, 0x07, 0x00, 0x00, 0x00,/*豸6564*/},\n        {\n\n                0xA4, 0xAA, 0x55, 0xA8, 0xC4, 0x20, 0x92, 0x8E, 0xA2, 0xA2, 0x9E, 0x02, 0x02, 0x09, 0x08, 0x07,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*貂6565*/},\n        {\n\n                0xA4, 0xAA, 0x55, 0xE8, 0x00, 0xF2, 0x92, 0x9A, 0x96, 0x92, 0xF2, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x0F, 0x04, 0x04, 0x04, 0x04, 0x0F,/*貊6566*/},\n        {\n\n                0xA4, 0xAA, 0x55, 0xE8, 0x10, 0xFC, 0x8B, 0x48, 0xFF, 0x48, 0x88, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x0F, 0x00, 0x00, 0x0F, 0x00, 0x00,/*貅6567*/},\n        {\n\n                0xA4, 0xAA, 0x55, 0xE8, 0x02, 0xFA, 0xAF, 0xAA, 0xAF, 0xFA, 0x02, 0x02, 0x0A, 0x09, 0x07, 0x0A,\n                0x0A, 0x06, 0x03, 0x06, 0x0A, 0x0A,/*貘6568*/},\n        {\n\n                0xA4, 0xAA, 0x55, 0xE8, 0x00, 0xBE, 0x36, 0x2B, 0xB6, 0x22, 0xBE, 0x02, 0x0A, 0x09, 0x07, 0x00,\n                0x0F, 0x09, 0x00, 0x07, 0x09, 0x0C,/*貔6569*/},\n        {\n\n                0x08, 0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x92, 0xA4, 0x80, 0xFF, 0x40, 0x08, 0x07, 0x01, 0x07, 0x09,\n                0x0F, 0x00, 0x00, 0x00, 0x0F, 0x00,/*斛6570*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x44, 0x44, 0xFF, 0x44, 0x7C, 0x40, 0x07, 0x01, 0x07, 0x09, 0x0F,\n                0x08, 0x06, 0x01, 0x02, 0x04, 0x08,/*觖6571*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x04, 0xCB, 0x6A, 0xDA, 0x4A, 0xC2, 0x07, 0x01, 0x07, 0x09, 0x0F,\n                0x01, 0x04, 0x02, 0x09, 0x08, 0x07,/*觞6572*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xFE, 0x02, 0xFE, 0x02, 0xFD, 0x07, 0x01, 0x07, 0x09, 0x0F,\n                0x04, 0x03, 0x00, 0x0F, 0x0A, 0x0C,/*觚6573*/},\n        {\n\n                0x10, 0x9E, 0xD0, 0xAF, 0xAA, 0xAA, 0xE0, 0xAF, 0x94, 0x92, 0x19, 0x01, 0x08, 0x07, 0x02, 0x02,\n                0x07, 0x02, 0x02, 0x0A, 0x0F, 0x00,/*觜6574*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x24, 0xE8, 0x3F, 0xE0, 0x28, 0x24, 0x07, 0x01, 0x07, 0x09, 0x0F,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*觥6575*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xF4, 0x94, 0xFF, 0x94, 0xF4, 0x07, 0x01, 0x07, 0x09, 0x0F,\n                0x00, 0x04, 0x02, 0x0F, 0x02, 0x04,/*觫6576*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xFD, 0x96, 0xFC, 0x96, 0xFD, 0x07, 0x01, 0x07, 0x09, 0x0F,\n                0x00, 0x02, 0x02, 0x0F, 0x02, 0x02,/*觯6577*/},\n        {\n\n                0x28, 0xAE, 0xA8, 0xAF, 0xAA, 0xB0, 0xA7, 0xAA, 0xAA, 0xA9, 0x2C, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*訾6578*/},\n        {\n\n                0xC2, 0xBA, 0xAA, 0xBF, 0xEA, 0xBA, 0x84, 0xDB, 0xA9, 0xDB, 0x82, 0x00, 0x02, 0x0E, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0E, 0x02, 0x00,/*謦6579*/},\n        {\n\n                0x22, 0xEA, 0xBF, 0xEA, 0x22, 0x00, 0xFE, 0x02, 0xFA, 0x02, 0xFE, 0x00, 0x0F, 0x02, 0x0F, 0x00,\n                0x08, 0x04, 0x03, 0x06, 0x08, 0x0C,/*靓6580*/},\n        {\n\n                0x8C, 0x85, 0xAD, 0xA5, 0xA5, 0xAF, 0xA5, 0xA5, 0xAD, 0x85, 0x8C, 0x00, 0x00, 0x03, 0x02, 0x02,\n                0x02, 0x02, 0x0A, 0x0A, 0x06, 0x00,/*雩6581*/},\n        {\n\n                0x0C, 0xA5, 0xAD, 0xAD, 0x85, 0xBF, 0x85, 0xAD, 0xAD, 0xA5, 0x8C, 0x08, 0x07, 0x00, 0x0A, 0x0A,\n                0x07, 0x02, 0x0A, 0x0A, 0x06, 0x00,/*雳6582*/},\n        {\n\n                0x8C, 0xA5, 0xAD, 0xAD, 0x85, 0xDF, 0x85, 0xAD, 0xAD, 0xA5, 0x8C, 0x08, 0x08, 0x09, 0x0A, 0x04,\n                0x04, 0x04, 0x0A, 0x09, 0x08, 0x08,/*雯6583*/},\n        {\n\n                0x0C, 0x25, 0xA5, 0x6D, 0x05, 0xAF, 0xA5, 0xED, 0xA5, 0x95, 0x0C, 0x09, 0x0A, 0x04, 0x0B, 0x08,\n                0x0A, 0x0A, 0x0B, 0x0A, 0x0A, 0x08,/*霆6584*/},\n        {\n\n                0x4C, 0x55, 0xDD, 0x55, 0x45, 0x6F, 0x45, 0x55, 0xDD, 0x55, 0x4C, 0x02, 0x02, 0x0A, 0x05, 0x01,\n                0x01, 0x01, 0x0D, 0x02, 0x02, 0x02,/*霁6585*/},\n        {\n\n                0x0C, 0x65, 0xAD, 0x2D, 0x85, 0xBF, 0x85, 0xED, 0xAD, 0xA5, 0x8C, 0x01, 0x0A, 0x04, 0x00, 0x0E,\n                0x02, 0x02, 0x0F, 0x02, 0x0A, 0x0E,/*霈6586*/},\n        {\n\n                0x4C, 0x55, 0x55, 0x55, 0xE5, 0x1F, 0xE5, 0x55, 0x55, 0x55, 0x4C, 0x04, 0x05, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x05, 0x05, 0x05, 0x04,/*霏6587*/},\n        {\n\n                0x4C, 0x55, 0x5D, 0x75, 0xD5, 0x5F, 0x55, 0x75, 0x5D, 0x55, 0x4C, 0x09, 0x09, 0x0B, 0x0B, 0x05,\n                0x05, 0x05, 0x0B, 0x09, 0x09, 0x01,/*霎6588*/},\n        {\n\n                0x4C, 0x95, 0x2D, 0x85, 0xE5, 0xAF, 0xE5, 0x95, 0xDD, 0xA5, 0x0C, 0x08, 0x04, 0x02, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x02,/*霪6589*/},\n        {\n\n                0x8C, 0x95, 0x2D, 0x05, 0xF5, 0x5F, 0x55, 0x55, 0x5D, 0xF5, 0x0C, 0x00, 0x0F, 0x04, 0x02, 0x0D,\n                0x09, 0x0D, 0x0B, 0x05, 0x09, 0x0F,/*霭6590*/},\n        {\n\n                0x8C, 0xA5, 0xFD, 0xA5, 0xF5, 0xAF, 0x85, 0x75, 0x4D, 0xC5, 0x4C, 0x00, 0x0F, 0x02, 0x02, 0x0A,\n                0x0F, 0x08, 0x05, 0x02, 0x05, 0x08,/*霰6591*/},\n        {\n\n                0xAC, 0xE5, 0x9D, 0x75, 0x45, 0x0F, 0xE5, 0xA5, 0xED, 0xA5, 0xEC, 0x0A, 0x0A, 0x05, 0x0B, 0x0E,\n                0x00, 0x0B, 0x0A, 0x0F, 0x0A, 0x0B,/*霾6592*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x00, 0x80, 0xFF, 0x20, 0x10, 0x0C, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x01, 0x00, 0x07, 0x08, 0x08, 0x0E,/*龀6593*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x00, 0xFE, 0x92, 0x92, 0xFE, 0x00, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x08, 0x0F, 0x08, 0x08, 0x0F, 0x08,/*龃6594*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x08, 0xF4, 0x97, 0xF4, 0x04, 0xFC, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x00, 0x07, 0x08, 0x08, 0x09, 0x0D,/*龅6595*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x40, 0xA2, 0x9E, 0x82, 0xA2, 0xBE, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*龆6596*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xFA, 0x00, 0xFF, 0x20, 0xFF, 0x10, 0x08, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x08, 0x0F, 0x04, 0x07, 0x08, 0x0E,/*龇6597*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x00, 0xFF, 0x49, 0xC9, 0x7F, 0x00, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x00, 0x0F, 0x04, 0x01, 0x06, 0x09,/*龈6598*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x24, 0xBD, 0xA7, 0xA5, 0xBD, 0x20, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*龉6599*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x00, 0xDF, 0x11, 0xF1, 0x91, 0x9F, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x04, 0x03, 0x04, 0x0F, 0x08, 0x08,/*龊6600*/},\n        {\n\n                0xDE, 0x10, 0xDF, 0x12, 0xD2, 0x00, 0xFF, 0x05, 0xD5, 0xB5, 0xD7, 0x07, 0x05, 0x04, 0x05, 0x0F,\n                0x04, 0x03, 0x08, 0x0A, 0x0F, 0x0A,/*龌6601*/},\n        {\n\n                0x00, 0xF0, 0x57, 0x55, 0x55, 0xFD, 0x55, 0x55, 0x57, 0xF0, 0x00, 0x00, 0x03, 0x01, 0x01, 0x01,\n                0x07, 0x09, 0x09, 0x09, 0x09, 0x0C,/*黾6602*/},\n        {\n\n                0x24, 0x14, 0xCD, 0x75, 0x55, 0xD5, 0x55, 0x7D, 0xD5, 0x14, 0x18, 0x00, 0x00, 0x07, 0x05, 0x05,\n                0x07, 0x0D, 0x0D, 0x0F, 0x08, 0x0E,/*鼋6603*/},\n        {\n\n                0x27, 0xE5, 0xBD, 0xAD, 0xAF, 0xF8, 0xAF, 0xAD, 0xBD, 0xE5, 0x27, 0x00, 0x07, 0x02, 0x02, 0x02,\n                0x07, 0x0A, 0x0A, 0x0A, 0x0B, 0x0C,/*鼍6604*/},\n        {\n\n                0x20, 0x10, 0xFC, 0x27, 0x24, 0x24, 0xFD, 0x26, 0x24, 0x24, 0x04, 0x00, 0x00, 0x0F, 0x09, 0x09,\n                0x09, 0x0F, 0x09, 0x09, 0x09, 0x08,/*隹6605*/},\n        {\n\n                0x08, 0x04, 0xFE, 0xAB, 0xAA, 0xAA, 0xFE, 0xAB, 0xAA, 0xAA, 0x82, 0x02, 0x02, 0x03, 0x02, 0x02,\n                0x0F, 0x02, 0x02, 0x02, 0x02, 0x02,/*隼6606*/},\n        {\n\n                0x08, 0x84, 0xFE, 0xAB, 0xAA, 0xAA, 0xBE, 0xAB, 0xAA, 0xAA, 0x22, 0x00, 0x08, 0x04, 0x03, 0x00,\n                0x00, 0x00, 0x0A, 0x0B, 0x0A, 0x06,/*隽6607*/},\n        {\n\n                0x00, 0xFE, 0x92, 0xFE, 0x10, 0xFC, 0xA7, 0xA4, 0xFD, 0xA6, 0xA4, 0x04, 0x07, 0x04, 0x03, 0x02,\n                0x0F, 0x04, 0x04, 0x07, 0x04, 0x04,/*雎6608*/},\n        {\n\n                0x44, 0xAB, 0x92, 0xAE, 0x40, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x24, 0x00, 0x0F, 0x04, 0x0F, 0x00,\n                0x00, 0x0F, 0x09, 0x0F, 0x09, 0x09,/*雒6609*/},\n        {\n\n                0x00, 0x9F, 0xD5, 0x75, 0x5F, 0x40, 0xDF, 0x75, 0x55, 0x5F, 0x40, 0x01, 0x00, 0x0F, 0x05, 0x05,\n                0x05, 0x07, 0x05, 0x05, 0x05, 0x04,/*瞿6610*/},\n        {\n\n                0xFC, 0x27, 0xFC, 0x25, 0x08, 0xFA, 0x10, 0xFC, 0x27, 0xFC, 0x25, 0x0F, 0x09, 0x0F, 0x09, 0x00,\n                0x07, 0x02, 0x0F, 0x09, 0x0F, 0x09,/*雠6611*/},\n        {\n\n                0x90, 0x91, 0x4F, 0xC9, 0xA0, 0x9F, 0xA5, 0xC9, 0x5F, 0xA0, 0xB0, 0x08, 0x0A, 0x0E, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0E, 0x0A, 0x08,/*銎6612*/},\n        {\n\n                0x92, 0x8A, 0x42, 0xDE, 0xA2, 0x93, 0xA2, 0xDE, 0x42, 0x8A, 0x92, 0x08, 0x0A, 0x0E, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0E, 0x0A, 0x08,/*銮6613*/},\n        {\n\n                0x44, 0x29, 0x92, 0xA4, 0xD5, 0xAD, 0xC7, 0x8D, 0x95, 0x25, 0x04, 0x09, 0x09, 0x0A, 0x0E, 0x0A,\n                0x0F, 0x0A, 0x0E, 0x0A, 0x09, 0x09,/*鋈6614*/},\n        {\n\n                0x22, 0x2E, 0xAB, 0xFE, 0xCA, 0xA0, 0xDE, 0x8A, 0x89, 0x79, 0x08, 0x09, 0x09, 0x0A, 0x0E, 0x0A,\n                0x0F, 0x0A, 0x0E, 0x0A, 0x09, 0x09,/*錾6615*/},\n        {\n\n                0x94, 0x8D, 0x57, 0xDD, 0xA7, 0x9C, 0xB4, 0xCB, 0x4A, 0x96, 0x92, 0x08, 0x0A, 0x0E, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0E, 0x0A, 0x08,/*鍪6616*/},\n        {\n\n                0x48, 0x2A, 0xBA, 0xAF, 0xEA, 0xAA, 0xC4, 0xAB, 0x92, 0x2E, 0x42, 0x09, 0x09, 0x0A, 0x0E, 0x0A,\n                0x0F, 0x0A, 0x0E, 0x0A, 0x09, 0x09,/*鏊6617*/},\n        {\n\n                0x44, 0x29, 0x92, 0x80, 0xCA, 0xBE, 0xCA, 0xBB, 0x8A, 0x3E, 0x6A, 0x09, 0x09, 0x0A, 0x0E, 0x0A,\n                0x0F, 0x0A, 0x0E, 0x0A, 0x09, 0x09,/*鎏6618*/},\n        {\n\n                0x20, 0x1F, 0x75, 0xD5, 0xF7, 0xA0, 0xCA, 0xAE, 0xFB, 0x2E, 0x0A, 0x01, 0x09, 0x0B, 0x0E, 0x0A,\n                0x0F, 0x0A, 0x0E, 0x0A, 0x09, 0x01,/*鐾6619*/},\n        {\n\n                0x04, 0xA4, 0x6C, 0xBA, 0x2A, 0x39, 0x2A, 0xBA, 0x6C, 0xA4, 0x04, 0x0D, 0x0A, 0x0E, 0x0A, 0x0D,\n                0x00, 0x0D, 0x0A, 0x0E, 0x0A, 0x0D,/*鑫6620*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x08, 0xFF, 0x08, 0xF9, 0x0A, 0x08, 0x09, 0x09, 0x05, 0x05, 0x09,\n                0x06, 0x01, 0x00, 0x07, 0x08, 0x0E,/*鱿6621*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x04, 0xFD, 0x26, 0x24, 0x24, 0xE4, 0x09, 0x09, 0x05, 0x05, 0x09,\n                0x06, 0x01, 0x00, 0x08, 0x08, 0x07,/*鲂6622*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xC8, 0x3F, 0xE8, 0x29, 0xEA, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x04, 0x03, 0x08, 0x05, 0x02, 0x0D,/*鲅6623*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x08, 0xB2, 0x82, 0xFE, 0xA2, 0x9A, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x00, 0x00, 0x0F, 0x00, 0x00,/*鲆6624*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xC0, 0x40, 0x7F, 0x48, 0xC8, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*鲇6625*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xF0, 0x90, 0x9F, 0x92, 0xF2, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x08, 0x07, 0x00, 0x00, 0x00, 0x01,/*鲈6626*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0x12, 0x92, 0xFF, 0x91, 0x10, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x01, 0x00, 0x0F, 0x00, 0x01,/*稣6627*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x10, 0xFC, 0x4B, 0x88, 0xFF, 0x08, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x00, 0x08, 0x0F, 0x00,/*鲋6628*/},\n        {\n\n                0x26, 0xF2, 0xAB, 0xAE, 0xAA, 0xEB, 0xAA, 0xBA, 0xA3, 0xE2, 0x06, 0x08, 0x0B, 0x0A, 0x0A, 0x0A,\n                0x0B, 0x0A, 0x0A, 0x0A, 0x0B, 0x08,/*鲎6629*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xD8, 0x54, 0x53, 0x50, 0xD8, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*鲐6630*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x24, 0x24, 0xBF, 0x24, 0x24, 0x20, 0x09, 0x09, 0x05, 0x05, 0x09,\n                0x09, 0x09, 0x0F, 0x09, 0x09, 0x08,/*鲑6631*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x04, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*鲒6632*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x24, 0xF4, 0x5C, 0x57, 0x54, 0xF4, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x01, 0x01, 0x09, 0x0F,/*鲔6633*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x12, 0xFA, 0x16, 0xF2, 0x12, 0xF2, 0x09, 0x09, 0x05, 0x05, 0x0F,\n                0x00, 0x07, 0x00, 0x07, 0x08, 0x0F,/*鲕6634*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x44, 0xAC, 0x15, 0x16, 0xAC, 0x44, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*鲚6635*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x24, 0xD5, 0x06, 0xD4, 0x24, 0x44, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x08, 0x05, 0x02, 0x05, 0x08, 0x08,/*鲛6636*/},\n        {\n\n                0x48, 0xAA, 0xDB, 0xAA, 0xBE, 0xAB, 0xEA, 0xAA, 0x9B, 0x2A, 0x48, 0x08, 0x08, 0x0F, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x08, 0x08,/*鲞6637*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0xAA, 0xAA, 0xAA, 0xAA, 0xEA, 0xBE, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x01, 0x02, 0x08, 0x0F, 0x00,/*鲟6638*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xFA, 0xAA, 0xFE, 0xAA, 0xFA, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0A, 0x04, 0x0B, 0x08, 0x08,/*鲠6639*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF8, 0x8A, 0xFA, 0x02, 0xFA, 0x8A, 0xFA, 0x09, 0x09, 0x05, 0x05, 0x0F,\n                0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F,/*鲡6640*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x11, 0xF2, 0x34, 0x2C, 0xF7, 0x24, 0x09, 0x09, 0x05, 0x05, 0x09,\n                0x04, 0x07, 0x09, 0x09, 0x0F, 0x09,/*鲢6641*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x1E, 0x00, 0x3F, 0xAA, 0x12, 0x2E, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x08, 0x09, 0x09, 0x0F, 0x09, 0x09,/*鲣6642*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0xFE, 0x22, 0xFE, 0x48, 0xFF, 0x08, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x07, 0x02, 0x07, 0x08, 0x0F, 0x00,/*鲥6643*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xA4, 0x97, 0xEA, 0x96, 0xA0, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x04, 0x0A, 0x0F, 0x02, 0x04,/*鲦6644*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0x92, 0xDA, 0xB6, 0x91, 0xC9, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x04, 0x02, 0x08, 0x0F, 0x02, 0x04,/*鲧6645*/},\n        {\n\n                0x22, 0x94, 0xC1, 0xA2, 0xB8, 0xA6, 0xE0, 0xBF, 0x90, 0x12, 0x04, 0x08, 0x08, 0x0F, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x08, 0x08,/*鲨6646*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x4C, 0xD4, 0x55, 0xD6, 0x54, 0x4C, 0x09, 0x09, 0x05, 0x05, 0x09,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*鲩6647*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xFE, 0x92, 0xFE, 0x00, 0xFE, 0x02, 0xFE, 0x09, 0x09, 0x05, 0x05, 0x0F,\n                0x04, 0x02, 0x04, 0x0F, 0x01, 0x01,/*鲫6648*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x22, 0xEA, 0xAA, 0xBF, 0xEA, 0x22, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x02, 0x0A, 0x0F, 0x00,/*鲭6649*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x28, 0x9A, 0x6F, 0x4A, 0xDA, 0x28, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x09, 0x08, 0x05, 0x02, 0x05, 0x08,/*鲮6650*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xFE, 0x52, 0xFE, 0x02, 0xFC, 0x04, 0xFC, 0x09, 0x09, 0x05, 0x05, 0x03,\n                0x02, 0x0F, 0x09, 0x04, 0x03, 0x0C,/*鲰6651*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0x24, 0xFF, 0x00, 0xFF, 0x24, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x01, 0x0F, 0x00, 0x0F, 0x01,/*鲱6652*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xDF, 0x15, 0xD5, 0x9F, 0x40, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x09, 0x07, 0x08, 0x0E,/*鲲6653*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0xC0, 0x5F, 0x55, 0x55, 0x5F, 0xC0, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x0F, 0x05, 0x05, 0x05, 0x05, 0x0F,/*鲳6654*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xFE, 0x02, 0xD2, 0x7E, 0xD2, 0x02, 0xFE, 0x09, 0x09, 0x05, 0x05, 0x0F,\n                0x04, 0x05, 0x05, 0x05, 0x04, 0x0F,/*鲴6655*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0xFE, 0x92, 0x81, 0x92, 0xFE, 0x00, 0x09, 0x09, 0x05, 0x05, 0x09,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0C,/*鲵6656*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF8, 0x24, 0xAA, 0x31, 0xA2, 0x64, 0x08, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x02, 0x0C, 0x09, 0x0C, 0x02, 0x04,/*鲶6657*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xFF, 0xA9, 0xBD, 0xA9, 0xFF, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x08, 0x07, 0x03, 0x0A, 0x0B, 0x0F,/*鲷6658*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0xAA, 0xFA, 0xA6, 0xE2, 0xFE, 0x00, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x04, 0x07, 0x04, 0x0E, 0x03, 0x0C,/*鲺6659*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x04, 0xDB, 0x44, 0xDB, 0x44, 0xDB, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x05, 0x07, 0x05, 0x0F,/*鲻6660*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xD2, 0x7A, 0x57, 0x7A, 0xD2, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0B, 0x04, 0x03, 0x04, 0x0B,/*鲼6661*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF4, 0x7E, 0x44, 0xDF, 0x54, 0x5F, 0x44, 0x09, 0x09, 0x05, 0x05, 0x09,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*鲽6662*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF7, 0x45, 0xD7, 0x50, 0x57, 0x55, 0x47, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x01, 0x09, 0x09, 0x07, 0x00,/*鳄6663*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x92, 0xFE, 0x51, 0x08, 0xFF, 0x10, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x08, 0x07, 0x00, 0x07,/*鳅6664*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x02, 0x7D, 0xD5, 0x55, 0x7D, 0x01, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x0A, 0x0B, 0x05, 0x05, 0x0B, 0x08,/*鳆6665*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xBE, 0xAB, 0xAA, 0xAA, 0xBE, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0A, 0x0A, 0x0F, 0x0A, 0x0A,/*鳇6666*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x80, 0xFE, 0x2A, 0xEB, 0x2A, 0xEE, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x01, 0x07, 0x09, 0x0F,/*鳊6667*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xD3, 0x55, 0xEB, 0x55, 0xD3, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x05, 0x05, 0x07, 0x05, 0x0D,/*鳋6668*/},\n        {\n\n                0x48, 0xAA, 0xDA, 0xAF, 0xBA, 0xAA, 0xE4, 0xAB, 0x92, 0x2E, 0x42, 0x08, 0x08, 0x0F, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x08, 0x08,/*鳌6669*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x4A, 0xAA, 0xBF, 0xEA, 0xDC, 0x6A, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0F, 0x0A, 0x0A, 0x0F, 0x00,/*鳍6670*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0x5F, 0xD5, 0x15, 0x55, 0xDF, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x05, 0x0A, 0x0F, 0x05, 0x0A, 0x0F,/*鳎6671*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xFF, 0x49, 0x2F, 0xF9, 0x0F, 0x29, 0x4F, 0x09, 0x09, 0x05, 0x05, 0x01,\n                0x02, 0x01, 0x0F, 0x00, 0x01, 0x02,/*鳏6672*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x42, 0x36, 0x2A, 0xE6, 0x29, 0x25, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0D, 0x09, 0x0F, 0x09, 0x0D,/*鳐6673*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xAF, 0xFA, 0xAF, 0xEA, 0xFF, 0x08, 0xF8, 0x09, 0x09, 0x05, 0x05, 0x02,\n                0x0F, 0x02, 0x08, 0x07, 0x08, 0x0F,/*鳓6674*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xFD, 0x15, 0x5F, 0x55, 0x5F, 0x55, 0x1D, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x03, 0x09, 0x0F, 0x01, 0x03, 0x05,/*鳔6675*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x00, 0xAD, 0xA5, 0x9F, 0xA5, 0xAD, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0x0F,/*鳕6676*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0x5F, 0x75, 0x55, 0x75, 0x5F, 0x70, 0x09, 0x09, 0x05, 0x05, 0x09,\n                0x0B, 0x05, 0x05, 0x05, 0x0B, 0x08,/*鳗6677*/},\n        {\n\n                0x04, 0xBF, 0xEA, 0xBE, 0xAA, 0xBE, 0xE4, 0xAB, 0x92, 0x2E, 0x42, 0x08, 0x08, 0x0F, 0x0A, 0x0A,\n                0x0F, 0x0A, 0x0A, 0x0F, 0x08, 0x08,/*鳘6678*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xFE, 0x22, 0xAA, 0xAA, 0xFF, 0xAA, 0xFA, 0x09, 0x09, 0x05, 0x0D, 0x07,\n                0x00, 0x0F, 0x02, 0x07, 0x0A, 0x0F,/*鳙6679*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xFE, 0x2A, 0xF2, 0x2A, 0xA2, 0xDE, 0x32, 0x09, 0x09, 0x05, 0x0D, 0x07,\n                0x09, 0x07, 0x09, 0x05, 0x03, 0x0C,/*鳜6680*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xF0, 0xA2, 0xEB, 0xAA, 0xFE, 0xAA, 0xEB, 0x09, 0x09, 0x05, 0x05, 0x05,\n                0x00, 0x0E, 0x0A, 0x0A, 0x0A, 0x0E,/*鳝6681*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xFA, 0xAB, 0xDE, 0xCA, 0xBE, 0xAB, 0xFA, 0x09, 0x09, 0x05, 0x05, 0x02,\n                0x06, 0x0A, 0x02, 0x0A, 0x0F, 0x02,/*鳟6682*/},\n        {\n\n                0xF4, 0x53, 0xFA, 0x56, 0xBE, 0xAA, 0xBF, 0xAA, 0xBF, 0xAA, 0xBE, 0x09, 0x09, 0x05, 0x05, 0x08,\n                0x0B, 0x0E, 0x0A, 0x0E, 0x0B, 0x08,/*鳢6683*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x00, 0xFE, 0x12, 0x12, 0xFE, 0x00, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x08, 0x09, 0x09, 0x09, 0x09, 0x08,/*靼6684*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0xFC, 0x84, 0xFF, 0x84, 0xFC, 0x80, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x08, 0x06, 0x01, 0x06, 0x08, 0x00,/*鞅6685*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x11, 0xF2, 0x00, 0x88, 0x7F, 0x88, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x08, 0x07, 0x0A, 0x09, 0x08, 0x0B,/*鞑6686*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x2A, 0x9A, 0x0E, 0x19, 0xA9, 0x48, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x08, 0x07, 0x00, 0x00, 0x0F, 0x00,/*鞒6687*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xEA, 0x04, 0xF3, 0x92, 0xFA, 0x96, 0xF0, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x08, 0x06, 0x01, 0x07, 0x08, 0x0C,/*鞔6688*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x90, 0xD2, 0x37, 0x5A, 0x57, 0xD2, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x00, 0x0F, 0x00, 0x0A, 0x0F, 0x02,/*鞯6689*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x04, 0xAB, 0xAE, 0xAA, 0x02, 0xFE, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x00, 0x0E, 0x0A, 0x0E, 0x08, 0x0F,/*鞫6690*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x48, 0x29, 0xDB, 0x7D, 0x0B, 0x18, 0x02, 0x02, 0x0F, 0x02, 0x0A,\n                0x05, 0x03, 0x0F, 0x03, 0x05, 0x09,/*鞣6691*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x08, 0xEA, 0xAF, 0xFA, 0xAF, 0xEA, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x02, 0x0F, 0x02, 0x03, 0x0A, 0x0F,/*鞲6692*/},\n        {\n\n                0xE2, 0xAF, 0xFA, 0xAF, 0xE2, 0x40, 0xEA, 0xBF, 0xEA, 0xAF, 0xEA, 0x02, 0x02, 0x0F, 0x02, 0x02,\n                0x00, 0x0F, 0x02, 0x07, 0x0A, 0x0F,/*鞴6693*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xA9, 0xEF, 0x18, 0x10, 0xEC, 0x03, 0xEC, 0x10, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x00, 0x08, 0x07, 0x00, 0x0F, 0x00,/*骱6694*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xA9, 0xEF, 0x18, 0x50, 0xCF, 0x41, 0xDF, 0x10, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x00, 0x08, 0x05, 0x02, 0x05, 0x08,/*骰6695*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xA9, 0xEF, 0x18, 0xC8, 0x48, 0x7F, 0x48, 0xC8, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*骷6696*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xA9, 0xEF, 0x18, 0x00, 0xFE, 0x8B, 0xA2, 0xBE, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x00, 0x02, 0x02, 0x02, 0x08, 0x0F,/*鹘6697*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xA9, 0xEF, 0x18, 0xFE, 0x22, 0xFE, 0x21, 0x21, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x00, 0x0F, 0x04, 0x0B, 0x04, 0x0E,/*骶6698*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xEF, 0x18, 0xFE, 0x12, 0x92, 0x91, 0x91, 0x90, 0x00, 0x0F, 0x02, 0x0F, 0x08,\n                0x07, 0x00, 0x0F, 0x04, 0x04, 0x0F,/*骺6699*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xEF, 0x18, 0x44, 0xAB, 0x92, 0x92, 0xAE, 0x40, 0x00, 0x0F, 0x02, 0x0F, 0x00,\n                0x00, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*骼6700*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xEF, 0x18, 0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x40, 0x00, 0x0F, 0x02, 0x0F, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*髁6701*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xA9, 0xEF, 0x18, 0x7C, 0xD6, 0x7D, 0x54, 0x7C, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x02, 0x03, 0x02, 0x0F, 0x02, 0x02,/*髀6702*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xA9, 0xEF, 0x98, 0x95, 0xCC, 0xBF, 0x8C, 0x95, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x00, 0x0A, 0x05, 0x04, 0x0B, 0x00,/*髅6703*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xEF, 0x18, 0x46, 0x52, 0x2E, 0x2B, 0x5A, 0x46, 0x00, 0x0F, 0x02, 0x0F, 0x00,\n                0x00, 0x0F, 0x05, 0x05, 0x0F, 0x00,/*髂6704*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xEF, 0x18, 0xD6, 0x7A, 0x53, 0x7A, 0xD2, 0x16, 0x00, 0x0F, 0x02, 0x0F, 0x00,\n                0x0B, 0x04, 0x03, 0x04, 0x0B, 0x0C,/*髋6705*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xEF, 0x18, 0x06, 0xFA, 0x2B, 0xEA, 0x22, 0x26, 0x00, 0x0F, 0x02, 0x0F, 0x00,\n                0x09, 0x05, 0x01, 0x01, 0x05, 0x09,/*髌6706*/},\n        {\n\n                0x18, 0xEF, 0xA9, 0xA9, 0xEF, 0x38, 0xD7, 0x5D, 0xF7, 0x55, 0xF7, 0x00, 0x0F, 0x02, 0x0A, 0x0F,\n                0x00, 0x05, 0x05, 0x07, 0x0D, 0x0F,/*髑6707*/},\n        {\n\n                0x7C, 0x56, 0xFD, 0x54, 0xFC, 0x00, 0x90, 0x54, 0xFF, 0x54, 0x90, 0x08, 0x07, 0x00, 0x07, 0x0A,\n                0x0B, 0x08, 0x08, 0x0B, 0x08, 0x0C,/*魅6708*/},\n        {\n\n                0x7C, 0x56, 0xFD, 0x54, 0xFC, 0x00, 0xC4, 0x3F, 0x54, 0x95, 0x74, 0x08, 0x07, 0x00, 0x07, 0x0A,\n                0x0B, 0x08, 0x0A, 0x09, 0x08, 0x0D,/*魃6709*/},\n        {\n\n                0x00, 0xFF, 0x15, 0xF5, 0xAD, 0xA5, 0xF7, 0xA5, 0xAD, 0xF7, 0x15, 0x08, 0x07, 0x08, 0x0B, 0x06,\n                0x03, 0x06, 0x0A, 0x0E, 0x0B, 0x0C,/*魇6710*/},\n        {\n\n                0x7C, 0x56, 0xFD, 0x54, 0xFD, 0x49, 0x3F, 0x49, 0x3F, 0x49, 0xF9, 0x08, 0x07, 0x00, 0x07, 0x0A,\n                0x0B, 0x08, 0x08, 0x08, 0x09, 0x0D,/*魉6711*/},\n        {\n\n                0x7C, 0x56, 0xFD, 0x54, 0xFC, 0x00, 0xFD, 0x54, 0x57, 0x54, 0xFD, 0x08, 0x07, 0x00, 0x07, 0x0A,\n                0x0B, 0x09, 0x08, 0x08, 0x09, 0x0D,/*魈6712*/},\n        {\n\n                0x7C, 0x56, 0xFD, 0x54, 0xFE, 0x2A, 0xEE, 0xBA, 0xAE, 0x2A, 0xFE, 0x08, 0x07, 0x00, 0x07, 0x0A,\n                0x0B, 0x08, 0x08, 0x08, 0x09, 0x0D,/*魍6713*/},\n        {\n\n                0x7C, 0x56, 0xFD, 0x54, 0xFC, 0x00, 0xBA, 0xB6, 0xEB, 0xB6, 0xBA, 0x08, 0x07, 0x00, 0x07, 0x0A,\n                0x0B, 0x0F, 0x08, 0x0B, 0x0A, 0x0F,/*魑6714*/},\n        {\n\n                0xCC, 0xAB, 0x98, 0xCC, 0x08, 0xF4, 0x52, 0x59, 0x52, 0xF4, 0x08, 0x08, 0x04, 0x02, 0x01, 0x00,\n                0x0F, 0x05, 0x01, 0x03, 0x05, 0x0A,/*飨6715*/},\n        {\n\n                0x00, 0xFF, 0x55, 0xD5, 0xAD, 0xA7, 0xD5, 0xA5, 0xAF, 0xD5, 0x55, 0x08, 0x07, 0x00, 0x0F, 0x0A,\n                0x02, 0x07, 0x0A, 0x0E, 0x0B, 0x08,/*餍6716*/},\n        {\n\n                0xA9, 0xAF, 0xD5, 0xCD, 0xA1, 0xD4, 0xAA, 0xD5, 0xEA, 0x94, 0x88, 0x00, 0x00, 0x0F, 0x0A, 0x02,\n                0x03, 0x02, 0x06, 0x0B, 0x0C, 0x0A,/*餮6717*/},\n        {\n\n                0x84, 0x97, 0xDD, 0xF7, 0xA4, 0xDC, 0xA4, 0xDF, 0xD5, 0xB5, 0xAC, 0x00, 0x00, 0x0F, 0x0A, 0x02,\n                0x03, 0x02, 0x06, 0x0B, 0x0C, 0x0A,/*饕6718*/},\n        {\n\n                0x52, 0x5A, 0xB6, 0x92, 0x4A, 0xBF, 0x6A, 0xAA, 0xBE, 0x2A, 0x2A, 0x01, 0x01, 0x0F, 0x0D, 0x05,\n                0x07, 0x05, 0x0F, 0x08, 0x09, 0x01,/*饔6719*/},\n        {\n\n                0x40, 0x7F, 0xD5, 0x55, 0x55, 0x41, 0x00, 0x88, 0x44, 0x22, 0x11, 0x06, 0x05, 0x04, 0x04, 0x05,\n                0x06, 0x08, 0x08, 0x04, 0x02, 0x01,/*髟6720*/},\n        {\n\n                0x50, 0x7F, 0x55, 0x55, 0x75, 0x50, 0x04, 0x12, 0x49, 0x24, 0x10, 0x09, 0x09, 0x05, 0x03, 0x01,\n                0x01, 0x01, 0x07, 0x09, 0x09, 0x0D,/*髡6721*/},\n        {\n\n                0x14, 0x5F, 0x54, 0x56, 0xDD, 0xB4, 0xA0, 0xA4, 0x12, 0x09, 0x04, 0x04, 0x05, 0x05, 0x05, 0x07,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x08, 0x0C,/*髦6722*/},\n        {\n\n                0x0A, 0xEF, 0xAA, 0xAB, 0xAE, 0xFA, 0xA0, 0xAA, 0xAA, 0xEA, 0x05, 0x02, 0x0F, 0x02, 0x02, 0x02,\n                0x03, 0x02, 0x02, 0x0A, 0x0F, 0x02,/*髯6723*/},\n        {\n\n                0x54, 0x5F, 0xD4, 0x56, 0x5D, 0x54, 0x40, 0x44, 0x52, 0x49, 0xC4, 0x02, 0x01, 0x0E, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0F, 0x01,/*髫6724*/},\n        {\n\n                0x2A, 0xAF, 0xAA, 0xAB, 0xAE, 0xFA, 0xA0, 0xAA, 0xAA, 0xAA, 0x25, 0x00, 0x0E, 0x0A, 0x0A, 0x0A,\n                0x0A, 0x0A, 0x0A, 0x0A, 0x0E, 0x00,/*髻6725*/},\n        {\n\n                0x50, 0x7F, 0x55, 0xD5, 0x75, 0x50, 0x04, 0x92, 0x49, 0x24, 0x90, 0x08, 0x0F, 0x08, 0x07, 0x05,\n                0x05, 0x00, 0x07, 0x0A, 0x09, 0x0C,/*髭6726*/},\n        {\n\n                0x14, 0x9F, 0xD4, 0x36, 0x9D, 0x94, 0x80, 0xE4, 0x92, 0x89, 0x84, 0x01, 0x00, 0x0F, 0x00, 0x04,\n                0x02, 0x01, 0x0F, 0x01, 0x02, 0x04,/*髹6727*/},\n        {\n\n                0x4A, 0x4F, 0x6A, 0xCB, 0x4E, 0x6A, 0x40, 0xCA, 0x6A, 0x4A, 0x45, 0x02, 0x02, 0x01, 0x07, 0x09,\n                0x09, 0x0D, 0x0F, 0x09, 0x0E, 0x02,/*鬈6728*/},\n        {\n\n                0x8A, 0xAF, 0xEA, 0x9B, 0x8E, 0x0A, 0xC0, 0x0A, 0xEA, 0x8A, 0x45, 0x04, 0x02, 0x0F, 0x02, 0x04,\n                0x00, 0x09, 0x04, 0x03, 0x04, 0x08,/*鬏6729*/},\n        {\n\n                0x14, 0xDF, 0x54, 0xD6, 0x5D, 0x74, 0x40, 0x44, 0x52, 0xC9, 0x04, 0x04, 0x04, 0x0C, 0x07, 0x05,\n                0x05, 0x05, 0x07, 0x0D, 0x04, 0x04,/*鬓6730*/},\n        {\n\n                0x14, 0xDF, 0x54, 0x56, 0xDD, 0x54, 0xC0, 0x44, 0x52, 0xC9, 0x04, 0x09, 0x09, 0x05, 0x0F, 0x09,\n                0x03, 0x05, 0x05, 0x0B, 0x09, 0x09,/*鬟6731*/},\n        {\n\n                0x14, 0xDF, 0xB4, 0x96, 0xDD, 0xB4, 0x80, 0xC4, 0xB2, 0x89, 0x04, 0x00, 0x0F, 0x0A, 0x02, 0x00,\n                0x0F, 0x0A, 0x00, 0x03, 0x04, 0x0E,/*鬣6732*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0x1A, 0x3E, 0x8A, 0x13, 0x8A, 0x3E, 0x1A, 0x2A, 0x08, 0x07, 0x00, 0x02, 0x09,\n                0x0C, 0x0A, 0x09, 0x08, 0x0C, 0x08,/*麽6733*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0x1A, 0x7E, 0x4A, 0xD3, 0xAA, 0xBE, 0x1A, 0x2A, 0x08, 0x07, 0x00, 0x04, 0x05,\n                0x05, 0x07, 0x0A, 0x0A, 0x0A, 0x0C,/*麾6734*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0x9A, 0xFE, 0x8A, 0x93, 0x8A, 0x7E, 0x1A, 0x2A, 0x08, 0x07, 0x0A, 0x06, 0x02,\n                0x0B, 0x0E, 0x02, 0x02, 0x07, 0x0A,/*縻6735*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xEA, 0xBE, 0xAA, 0x2B, 0xFE, 0xAA, 0xBA, 0xC2, 0x08, 0x07, 0x00, 0x08, 0x06,\n                0x02, 0x02, 0x06, 0x08, 0x0C, 0x00,/*麂6736*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xAA, 0xBE, 0xAA, 0xAB, 0xBE, 0xAA, 0x7A, 0x02, 0x08, 0x07, 0x0A, 0x0A, 0x06,\n                0x02, 0x0F, 0x02, 0x06, 0x0A, 0x0A,/*麇6737*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xAA, 0xBE, 0xAA, 0xEB, 0xBE, 0xAA, 0xBA, 0x02, 0x08, 0x07, 0x08, 0x0A, 0x0A,\n                0x0A, 0x0F, 0x0A, 0x0A, 0x0A, 0x08,/*麈6738*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xAA, 0x3E, 0x2A, 0xAB, 0x3E, 0x2A, 0xBA, 0x02, 0x08, 0x07, 0x02, 0x0A, 0x07,\n                0x02, 0x0F, 0x02, 0x07, 0x0A, 0x02,/*麋6739*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xFF, 0xAA, 0x3A, 0x04, 0xFF, 0x54, 0xFF, 0x04, 0x08, 0x07, 0x00, 0x0F, 0x04,\n                0x02, 0x09, 0x05, 0x01, 0x05, 0x09,/*麒6740*/},\n        {\n\n                0x00, 0xFE, 0xAA, 0xAA, 0x7E, 0xEA, 0xAB, 0xFE, 0x6A, 0xBA, 0x82, 0x08, 0x07, 0x08, 0x0A, 0x0E,\n                0x0A, 0x0F, 0x0A, 0x0E, 0x0A, 0x08,/*鏖6741*/},\n        {\n\n                0x00, 0xFE, 0x2A, 0xEA, 0xBE, 0xEA, 0x2B, 0xBE, 0xAA, 0xFA, 0x82, 0x08, 0x07, 0x0A, 0x07, 0x0A,\n                0x0F, 0x00, 0x02, 0x08, 0x0F, 0x00,/*麝6742*/},\n        {\n\n                0xFE, 0x2A, 0xFF, 0xAA, 0x3A, 0x95, 0x6E, 0xC4, 0x5F, 0xEE, 0x55, 0x07, 0x00, 0x0F, 0x04, 0x02,\n                0x09, 0x06, 0x01, 0x02, 0x0F, 0x02,/*麟6743*/},\n        {\n\n                0x08, 0xE4, 0x3E, 0xA1, 0x28, 0xE8, 0x2F, 0xA8, 0x35, 0xE6, 0x34, 0x04, 0x0D, 0x05, 0x05, 0x0D,\n                0x07, 0x0D, 0x05, 0x05, 0x0D, 0x04,/*黛6744*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x00, 0xBC, 0x20, 0xFF, 0x20, 0xBC, 0x0A, 0x02, 0x0D, 0x01, 0x0D,\n                0x00, 0x07, 0x04, 0x07, 0x04, 0x0F,/*黜6745*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x9F, 0x56, 0xB9, 0x04, 0xFF, 0x04, 0xFC, 0x0A, 0x02, 0x0D, 0x01, 0x0D,\n                0x01, 0x09, 0x06, 0x09, 0x08, 0x07,/*黝6746*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x00, 0xA4, 0xA4, 0xBF, 0xA4, 0xA4, 0x0A, 0x02, 0x0D, 0x01, 0x0D,\n                0x00, 0x0F, 0x04, 0x04, 0x04, 0x0F,/*黠6747*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x00, 0x44, 0xAB, 0x52, 0x6E, 0xC0, 0x0A, 0x02, 0x0D, 0x01, 0x0D,\n                0x00, 0x09, 0x08, 0x05, 0x02, 0x01,/*黟6748*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x20, 0x96, 0x65, 0x44, 0xD6, 0x2C, 0x0A, 0x02, 0x0D, 0x01, 0x0D,\n                0x01, 0x08, 0x05, 0x02, 0x05, 0x08,/*黢6749*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x00, 0x4A, 0xAA, 0x4F, 0xEA, 0x1A, 0x0A, 0x02, 0x0D, 0x01, 0x0D,\n                0x00, 0x09, 0x05, 0x03, 0x05, 0x09,/*黩6750*/},\n        {\n\n                0x14, 0xED, 0x25, 0xBF, 0x25, 0xEC, 0x33, 0xAA, 0x26, 0xF2, 0x1E, 0x04, 0x0D, 0x05, 0x05, 0x0D,\n                0x07, 0x0D, 0x05, 0x05, 0x0D, 0x04,/*黧6751*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x00, 0xF4, 0x95, 0x96, 0x94, 0xF4, 0x0A, 0x02, 0x0D, 0x01, 0x0D,\n                0x04, 0x02, 0x08, 0x0F, 0x02, 0x04,/*黥6752*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x00, 0x54, 0xB6, 0x5D, 0xB6, 0x54, 0x0A, 0x02, 0x0D, 0x01, 0x0D,\n                0x00, 0x0A, 0x0A, 0x05, 0x04, 0x02,/*黪6753*/},\n        {\n\n                0x5F, 0x55, 0xFF, 0x55, 0x5F, 0x00, 0xD6, 0x5A, 0x53, 0x5A, 0xD6, 0x0A, 0x02, 0x0D, 0x01, 0x0D,\n                0x00, 0x0F, 0x05, 0x05, 0x05, 0x0F,/*黯6754*/},\n        {\n\n                0xDE, 0x95, 0xD0, 0x95, 0xDF, 0x10, 0x2C, 0xE3, 0x20, 0x23, 0xEC, 0x0F, 0x0A, 0x07, 0x0A, 0x07,\n                0x08, 0x06, 0x01, 0x08, 0x08, 0x07,/*鼢6755*/},\n        {\n\n                0xDE, 0x95, 0xD0, 0x95, 0xDF, 0x00, 0xF8, 0x48, 0xFF, 0x48, 0xF8, 0x0F, 0x0A, 0x07, 0x0A, 0x07,\n                0x08, 0x0F, 0x04, 0x07, 0x04, 0x0F,/*鼬6756*/},\n        {\n\n                0xDE, 0x95, 0xD0, 0x95, 0xDF, 0x00, 0xA5, 0xBD, 0xA7, 0xBD, 0x21, 0x0F, 0x0A, 0x07, 0x0A, 0x07,\n                0x08, 0x0F, 0x04, 0x04, 0x0F, 0x00,/*鼯6757*/},\n        {\n\n                0xDE, 0x95, 0xD0, 0x95, 0xDF, 0x30, 0x9F, 0xD5, 0x95, 0x9F, 0xB0, 0x0F, 0x0A, 0x07, 0x0A, 0x07,\n                0x08, 0x0A, 0x05, 0x04, 0x0B, 0x08,/*鼹6758*/},\n        {\n\n                0xDE, 0x95, 0xD0, 0x95, 0xDF, 0x02, 0xB6, 0xEA, 0xA5, 0x91, 0xC5, 0x0F, 0x0A, 0x07, 0x0A, 0x07,\n                0x08, 0x0A, 0x06, 0x03, 0x06, 0x0A,/*鼷6759*/},\n        {\n\n                0xF8, 0xAE, 0xFB, 0xAE, 0xF8, 0x08, 0xFF, 0x08, 0xF8, 0x00, 0x00, 0x0A, 0x06, 0x02, 0x0E, 0x0A,\n                0x04, 0x03, 0x00, 0x07, 0x08, 0x0E,/*鼽6760*/},\n        {\n\n                0x00, 0xF8, 0xAE, 0xFB, 0xAE, 0xF8, 0x40, 0x42, 0xFE, 0x42, 0x40, 0x02, 0x0A, 0x06, 0x02, 0x0E,\n                0x02, 0x02, 0x00, 0x0F, 0x00, 0x00,/*鼾6761*/},\n        {\n\n                0xF8, 0xAE, 0xFB, 0xAE, 0xF8, 0x12, 0xEA, 0xA6, 0xBF, 0xA6, 0xEA, 0x0A, 0x06, 0x02, 0x0E, 0x02,\n                0x08, 0x0B, 0x0A, 0x0A, 0x0A, 0x0B,/*齄6762*/}\n\n\n};\n\n\n#else\nunsigned char new_font[CHN_FONT_NUM][22] = {{\n0xFE,0x02,0xFE,0x00,0xFE,0x32,0xCE,0xF8,0x8A,0xFE,0x02,0x03,0x01,0x03,0x00,0x0F,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"啊\",0*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0xF2,0x12,0xF2,0x02,0xFE,0x02,0x0F,0x02,0x02,0x01,0x00,\n0x03,0x01,0x09,0x08,0x0F,0x00,/*\"阿\",1*/},{\n\n0x10,0x10,0xFF,0x10,0x48,0x3C,0x2A,0xE9,0x28,0x2C,0x18,0x04,0x04,0x03,0x02,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"埃\",2*/},{\n\n0x88,0xFF,0x48,0x00,0x48,0x3C,0x2A,0xE9,0x28,0x2C,0x18,0x08,0x0F,0x00,0x08,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"挨\",3*/},{\n\n0xFE,0x02,0xFE,0x04,0x6F,0x84,0x04,0x84,0x6F,0x04,0x04,0x03,0x01,0x0B,0x08,0x04,\n0x02,0x01,0x02,0x04,0x08,0x08,/*\"哎\",4*/},{\n\n0xFE,0x02,0xFE,0x00,0x48,0x3C,0x2A,0xE9,0x28,0x2C,0x18,0x03,0x01,0x03,0x08,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"唉\",5*/},{\n\n0x04,0x74,0x54,0x54,0xD5,0xD6,0x54,0x54,0x54,0x74,0x04,0x04,0x04,0x02,0x0F,0x08,\n0x04,0x01,0x02,0x04,0x0A,0x09,/*\"哀\",6*/},{\n\n0xFC,0x46,0xFD,0x00,0xD6,0x54,0x54,0x57,0x54,0x54,0xD6,0x0F,0x04,0x0F,0x00,0x09,\n0x0B,0x0D,0x09,0x0D,0x0B,0x09,/*\"皚\",7*/},{\n\n0x08,0x90,0xFE,0x02,0xC2,0x7A,0xEB,0x2A,0xEA,0x7A,0xC2,0x09,0x04,0x03,0x00,0x0D,\n0x09,0x09,0x0E,0x09,0x09,0x0D,/*\"癌\",8*/},{\n\n0xAA,0xAA,0xAF,0xAA,0x02,0xFA,0xAA,0xAA,0xAF,0xFA,0x82,0x0E,0x0A,0x0A,0x0E,0x01,\n0x06,0x04,0x06,0x05,0x0A,0x0F,/*\"藹\",9*/},{\n\n0x48,0x47,0xFC,0x44,0xA8,0x9A,0x8A,0xFE,0x89,0x99,0xA8,0x08,0x06,0x01,0x06,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"矮\",10*/},{\n\n0x04,0x04,0x04,0x6F,0x84,0x04,0x84,0x6F,0x04,0x04,0x04,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x04,0x08,0x08,/*\"艾\",11*/},{\n\n0xF2,0x2E,0xE2,0x40,0x37,0xEA,0x2D,0x90,0x15,0xF9,0xB7,0x07,0x02,0x03,0x08,0x05,\n0x03,0x0D,0x07,0x08,0x0F,0x08,/*\"礙\",12*/},{\n\n0x5A,0x2A,0x0E,0xAA,0x5A,0x6E,0x49,0x69,0x0D,0x2B,0x59,0x08,0x0A,0x09,0x0B,0x05,\n0x05,0x05,0x05,0x0B,0x08,0x08,/*\"愛\",13*/},{\n\n0xFE,0x32,0xCE,0xA9,0x9A,0x88,0x88,0x88,0x9A,0xA9,0x40,0x0F,0x02,0x09,0x0F,0x08,\n0x0F,0x08,0x0F,0x08,0x0F,0x08,/*\"隘\",14*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x4C,0xC4,0x75,0x46,0xC4,0x4C,0x02,0x02,0x0F,0x02,0x0A,\n0x08,0x05,0x02,0x02,0x05,0x08,/*\"鞍\",15*/},{\n\n0xC4,0x52,0x55,0xD5,0x75,0x55,0x55,0xD5,0xF5,0x01,0x00,0x00,0x09,0x0B,0x05,0x05,\n0x0B,0x09,0x00,0x03,0x04,0x0E,/*\"氨\",16*/},{\n\n0x2C,0x24,0xA4,0x64,0x3D,0x26,0x24,0x24,0xE4,0x24,0x2C,0x08,0x08,0x09,0x05,0x05,\n0x02,0x02,0x05,0x04,0x08,0x00,/*\"安\",17*/},{\n\n0x10,0xFC,0x23,0x12,0xEA,0xA6,0xF3,0xA6,0xEA,0x12,0x10,0x00,0x0F,0x00,0x00,0x07,\n0x02,0x07,0x0A,0x0B,0x08,0x0E,/*\"俺\",18*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0x4C,0xC4,0x75,0x46,0xC4,0x4C,0x00,0x08,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x02,0x05,0x08,/*\"按\",19*/},{\n\n0xFE,0x22,0xFE,0x24,0xAC,0xB4,0xA5,0xA6,0xB4,0xAC,0x24,0x07,0x02,0x07,0x00,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"暗\",20*/},{\n\n0x00,0xF6,0x14,0x54,0x54,0x57,0xD4,0x54,0x54,0x56,0x00,0x08,0x07,0x01,0x01,0x01,\n0x01,0x0F,0x01,0x01,0x01,0x01,/*\"岸\",21*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x4C,0xC5,0x76,0x44,0xC4,0x4C,0x08,0x07,0x08,0x0F,0x00,\n0x09,0x05,0x02,0x02,0x05,0x08,/*\"胺\",22*/},{\n\n0x46,0x4A,0x4A,0x5A,0x2E,0xAB,0x2A,0x5A,0x4A,0x4A,0x06,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"案\",23*/},{\n\n0x18,0xEF,0xA9,0xEF,0x18,0x04,0xE4,0x25,0xE6,0x04,0x04,0x00,0x0F,0x02,0x0F,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"骯\",24*/},{\n\n0xC0,0x5F,0x55,0x35,0x15,0x15,0xD5,0x55,0x55,0x5F,0xC0,0x07,0x04,0x04,0x02,0x02,\n0x00,0x0F,0x00,0x00,0x04,0x07,/*\"昂\",25*/},{\n\n0x90,0x90,0x5E,0x52,0x32,0x1F,0x32,0x52,0x5E,0x90,0x90,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盎\",26*/},{\n\n0xFE,0x02,0x02,0x7E,0x40,0x40,0x40,0x7E,0x02,0x02,0xFE,0x0F,0x04,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"凹\",27*/},{\n\n0x44,0x54,0xD4,0x7F,0x54,0x44,0x10,0xEF,0x08,0xF8,0x08,0x08,0x04,0x03,0x09,0x0F,\n0x00,0x08,0x05,0x02,0x05,0x08,/*\"敖\",28*/},{\n\n0x22,0xEA,0xBF,0xAA,0xA2,0x10,0x08,0xB7,0x44,0xBC,0x04,0x0A,0x05,0x00,0x06,0x0B,\n0x00,0x05,0x08,0x00,0x04,0x09,/*\"熬\",29*/},{\n\n0xBE,0xAA,0xEB,0xAA,0xBE,0x10,0xA2,0xFE,0x10,0xA2,0xFE,0x02,0x05,0x0E,0x05,0x02,\n0x01,0x08,0x0F,0x01,0x08,0x0F,/*\"翱\",30*/},{\n\n0x45,0xF6,0xAC,0x00,0xFE,0x5A,0x13,0x7E,0x12,0x5A,0xFE,0x00,0x0F,0x00,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"襖\",31*/},{\n\n0x10,0xFC,0x23,0xEA,0xBF,0xAA,0x10,0xEF,0x08,0xF8,0x08,0x00,0x0F,0x08,0x07,0x08,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"傲\",32*/},{\n\n0x00,0xFE,0x42,0xDA,0x4B,0xFA,0x4A,0xD6,0x42,0xFE,0x00,0x0A,0x0A,0x0A,0x06,0x02,\n0x03,0x02,0x06,0x0A,0x0A,0x0A,/*\"奧\",33*/},{\n\n0x78,0x00,0xFF,0x08,0xFE,0x5A,0x13,0x7E,0x12,0x5A,0xFE,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"懊\",34*/},{\n\n0x11,0x22,0xFE,0x12,0x5A,0x13,0x7E,0x12,0x5A,0x12,0xFE,0x04,0x02,0x0A,0x0A,0x06,\n0x02,0x03,0x02,0x06,0x0A,0x0A,/*\"澳\",35*/},{\n\n0x02,0xF2,0x92,0x97,0x92,0xF2,0x92,0x97,0x92,0xF2,0x02,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"芭\",36*/},{\n\n0x88,0xFF,0x48,0x80,0x9E,0xF2,0x9E,0x00,0xFC,0x00,0xFF,0x08,0x0F,0x08,0x04,0x03,\n0x08,0x0F,0x00,0x01,0x08,0x0F,/*\"捌\",37*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xFE,0x00,0x00,0xFF,0x00,0x00,0x00,0x08,0x0F,0x08,0x06,\n0x01,0x00,0x00,0x01,0x06,0x08,/*\"扒\",38*/},{\n\n0xFE,0x02,0xFE,0x00,0x00,0xFE,0x00,0x00,0xFF,0x00,0x00,0x03,0x01,0x03,0x08,0x06,\n0x01,0x00,0x00,0x01,0x06,0x08,/*\"叭\",39*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0x42,0x42,0x7E,0x42,0x42,0x7E,0x03,0x01,0x03,0x00,0x07,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"吧\",40*/},{\n\n0x04,0xF3,0x92,0x96,0x92,0xF4,0x93,0x92,0x96,0xF2,0x02,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"笆\",41*/},{\n\n0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x7F,0x80,0x00,0x00,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x00,0x01,0x06,0x08,/*\"八\",42*/},{\n\n0x08,0x90,0xFC,0x04,0xF4,0x95,0x96,0xF4,0x94,0x94,0xF4,0x09,0x04,0x03,0x00,0x07,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"疤\",43*/},{\n\n0x00,0xFE,0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x7E,0x00,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"巴\",44*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xC8,0x3F,0xE8,0x29,0x2A,0xE8,0x00,0x08,0x0F,0x08,0x06,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"拔\",45*/},{\n\n0x9E,0x12,0xF2,0x5E,0x08,0xC8,0x3F,0xE8,0x29,0x2A,0xE8,0x07,0x04,0x03,0x0A,0x06,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"跋\",46*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x00,0xFE,0x42,0x7E,0x42,0x7E,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"靶\",47*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x42,0x42,0x7E,0x42,0x42,0x7E,0x08,0x0F,0x00,0x00,0x07,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"把\",48*/},{\n\n0x44,0x54,0xFF,0x54,0x00,0xFE,0x42,0x7E,0x42,0x42,0x7E,0x02,0x01,0x0F,0x01,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"耙\",49*/},{\n\n0x08,0xFF,0x08,0x40,0xED,0x55,0xE5,0x5F,0xE5,0xB5,0xED,0x02,0x03,0x01,0x04,0x05,\n0x0F,0x05,0x0C,0x07,0x0A,0x0F,/*\"壩\",50*/},{\n\n0x4C,0xE5,0x4D,0x45,0x45,0xEF,0x45,0xE5,0xAD,0xA5,0xEC,0x04,0x05,0x05,0x0F,0x05,\n0x05,0x08,0x07,0x02,0x0A,0x0F,/*\"霸\",51*/},{\n\n0x20,0xB7,0xAD,0xA5,0xB7,0xA5,0x07,0x3D,0x55,0x4F,0x60,0x00,0x0F,0x02,0x02,0x0A,\n0x0F,0x00,0x07,0x0A,0x09,0x0C,/*\"罷\",52*/},{\n\n0x20,0x24,0xD2,0x55,0x48,0xC8,0x48,0x55,0xD2,0x24,0x20,0x00,0x00,0x07,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0C,0x00,/*\"爸\",53*/},{\n\n0x00,0xFC,0x44,0x46,0x45,0x44,0x44,0x44,0x44,0xFC,0x00,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"白\",54*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xFC,0x44,0x46,0x45,0x44,0xFC,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"柏\",55*/},{\n\n0x02,0xF2,0x92,0x92,0x9A,0x96,0x92,0x92,0x92,0xF2,0x02,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"百\",56*/},{\n\n0x84,0xFF,0x44,0x00,0xB7,0xAD,0xB7,0x05,0x3F,0x55,0x6F,0x08,0x0F,0x00,0x00,0x0F,\n0x02,0x0F,0x00,0x07,0x0A,0x0D,/*\"擺\",57*/},{\n\n0x20,0x10,0xFC,0x03,0xF2,0x92,0x9A,0x96,0x92,0x92,0xF2,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"佰\",58*/},{\n\n0xFE,0x2A,0x2A,0x2A,0xFE,0x20,0x10,0xEF,0x08,0xF8,0x08,0x09,0x05,0x01,0x05,0x09,\n0x00,0x08,0x05,0x02,0x05,0x08,/*\"敗\",59*/},{\n\n0x92,0x92,0xFE,0x91,0x91,0x00,0x29,0x29,0xFF,0x29,0x29,0x08,0x04,0x03,0x00,0x00,\n0x00,0x01,0x01,0x0F,0x01,0x01,/*\"拜\",60*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x01,0x00,0x0F,0x00,0x02,\n0x03,0x02,0x02,0x0F,0x02,0x02,/*\"稗\",61*/},{\n\n0x22,0xFE,0x22,0x08,0x69,0x8A,0x78,0x08,0x42,0xFE,0x42,0x04,0x07,0x02,0x04,0x02,\n0x01,0x06,0x00,0x08,0x0F,0x08,/*\"斑\",62*/},{\n\n0x22,0xFE,0xA2,0x78,0x00,0xFF,0x00,0x42,0xFE,0x42,0x42,0x04,0x07,0x02,0x08,0x06,\n0x01,0x08,0x08,0x0F,0x08,0x08,/*\"班\",63*/},{\n\n0x88,0xFF,0x48,0xFC,0x56,0xFD,0x10,0xCE,0x42,0xDE,0x10,0x08,0x0F,0x08,0x07,0x09,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"搬\",64*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xFE,0x12,0xF2,0x12,0x91,0x71,0x00,0x08,0x0F,0x08,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"扳\",65*/},{\n\n0x40,0xFC,0x56,0x65,0xFC,0x10,0xCE,0x42,0x42,0xDE,0x10,0x08,0x07,0x01,0x0A,0x0F,\n0x08,0x05,0x02,0x02,0x05,0x08,/*\"般\",66*/},{\n\n0x28,0xE6,0x20,0x23,0xEC,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頒\",67*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xFE,0x12,0xF2,0x12,0x91,0x71,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"板\",68*/},{\n\n0x00,0xFE,0x90,0x9F,0x10,0xFE,0x12,0xF2,0x12,0x91,0x71,0x08,0x07,0x00,0x0F,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"版\",69*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0x2C,0xE3,0x20,0x23,0xEC,0x10,0x00,0x08,0x0F,0x00,0x08,\n0x06,0x01,0x08,0x08,0x07,0x00,/*\"扮\",70*/},{\n\n0x88,0x88,0xFF,0x48,0x82,0x94,0x90,0xFF,0x90,0x94,0x82,0x00,0x08,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"拌\",71*/},{\n\n0x20,0x10,0xFC,0x03,0x82,0x94,0x90,0xFF,0x90,0x94,0x82,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"伴\",72*/},{\n\n0x55,0xE6,0x54,0x00,0xFE,0x02,0xFD,0x20,0x55,0xE6,0x54,0x09,0x07,0x09,0x06,0x01,\n0x0E,0x09,0x0C,0x01,0x0F,0x01,/*\"瓣\",73*/},{\n\n0x80,0x90,0x92,0x94,0x90,0xFF,0x90,0x94,0x92,0x90,0x80,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"半\",74*/},{\n\n0x55,0xE6,0x54,0x08,0xFF,0x08,0xF8,0x00,0x55,0xE6,0x54,0x09,0x07,0x01,0x08,0x07,\n0x08,0x0F,0x00,0x01,0x0F,0x01,/*\"辦\",75*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x92,0x94,0xFF,0x94,0x92,0x80,0x0C,0x02,0x04,0x02,0x04,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"絆\",76*/},{\n\n0x80,0x92,0x92,0xFF,0x92,0x92,0x00,0xFE,0x02,0x32,0xCE,0x00,0x08,0x06,0x01,0x00,\n0x00,0x00,0x0F,0x02,0x02,0x01,/*\"邦\",77*/},{\n\n0x28,0x2A,0xEA,0xBF,0xAA,0xBA,0xA0,0xAA,0xF2,0x1F,0x02,0x00,0x0E,0x03,0x02,0x02,\n0x0E,0x02,0x02,0x0B,0x0E,0x00,/*\"幫\",78*/},{\n\n0x88,0x68,0xFF,0x48,0x92,0xFF,0x92,0x00,0xFE,0x32,0xCE,0x00,0x00,0x0F,0x00,0x08,\n0x07,0x00,0x00,0x0F,0x02,0x01,/*\"梆\",79*/},{\n\n0x88,0x68,0xFF,0x48,0xB2,0x96,0x9A,0xD3,0x9A,0x96,0xB2,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x02,0x0A,0x0A,0x06,/*\"榜\",80*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xB2,0x96,0xBB,0xDA,0x96,0xB2,0x08,0x07,0x08,0x0F,0x00,\n0x08,0x07,0x02,0x0A,0x0A,0x06,/*\"膀\",81*/},{\n\n0xDC,0xB3,0xC8,0x00,0x92,0xFF,0x92,0x00,0xFE,0x32,0xCE,0x0E,0x00,0x06,0x00,0x08,\n0x07,0x00,0x00,0x0F,0x02,0x01,/*\"綁\",82*/},{\n\n0x88,0x68,0xFF,0x48,0xA2,0x6A,0x3A,0xAF,0x2A,0x6A,0xA2,0x00,0x00,0x0F,0x00,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"棒\",83*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xB2,0x96,0xBB,0xDA,0x96,0xB2,0x00,0x07,0x02,0x07,0x00,\n0x08,0x07,0x02,0x0A,0x0A,0x06,/*\"磅\",84*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x24,0x24,0xFF,0x24,0x24,0x04,0x04,0x03,0x02,0x07,\n0x00,0x01,0x01,0x0F,0x01,0x01,/*\"蚌\",85*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xB2,0x96,0xBB,0xDA,0x96,0xB2,0x08,0x09,0x07,0x04,0x00,\n0x08,0x07,0x02,0x0A,0x0A,0x06,/*\"鎊\",86*/},{\n\n0x20,0x10,0xFC,0x03,0xB2,0x96,0x9A,0xD3,0x9A,0x96,0xB2,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x02,0x0A,0x0A,0x06,/*\"傍\",87*/},{\n\n0x55,0x56,0x54,0x00,0xB2,0x96,0x9A,0xD3,0x9A,0x96,0xB2,0x0F,0x05,0x0F,0x00,0x08,\n0x04,0x03,0x02,0x0A,0x0A,0x06,/*\"謗\",88*/},{\n\n0x42,0x22,0xDA,0x57,0x52,0x52,0xD2,0x17,0x12,0xF2,0x02,0x00,0x00,0x07,0x09,0x09,\n0x09,0x09,0x08,0x0A,0x0B,0x0C,/*\"苞\",89*/},{\n\n0x00,0xFE,0x92,0xFE,0x08,0xF4,0x97,0x94,0xF4,0x04,0xFC,0x08,0x07,0x08,0x0F,0x00,\n0x07,0x08,0x08,0x08,0x09,0x0D,/*\"胞\",90*/},{\n\n0x10,0x08,0xF7,0x94,0x94,0x94,0xF4,0x04,0x04,0xFC,0x00,0x00,0x00,0x07,0x08,0x08,\n0x08,0x08,0x08,0x09,0x09,0x0E,/*\"包\",91*/},{\n\n0x12,0x0A,0xFE,0x02,0xA2,0xEF,0x2A,0xFA,0x2A,0x6E,0xA2,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"褒\",92*/},{\n\n0x20,0xAC,0x2B,0xEA,0x3A,0xA6,0x20,0xFC,0x00,0x00,0xFF,0x04,0x02,0x09,0x0F,0x01,\n0x02,0x04,0x01,0x08,0x08,0x0F,/*\"剝\",93*/},{\n\n0x4A,0x92,0x02,0x17,0xF2,0x52,0xFA,0x57,0x52,0xFA,0x12,0x08,0x04,0x00,0x01,0x03,\n0x05,0x01,0x09,0x0F,0x01,0x01,/*\"薄\",94*/},{\n\n0x8C,0x45,0xB5,0xAD,0xA5,0xAF,0xA5,0x2D,0x25,0xE5,0x0C,0x00,0x00,0x07,0x0A,0x0A,\n0x0A,0x0B,0x08,0x0A,0x0B,0x0C,/*\"雹\",95*/},{\n\n0x20,0x10,0xFC,0x03,0x40,0x5E,0x52,0xF2,0x52,0x5E,0x40,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"保\",96*/},{\n\n0x08,0x04,0xFE,0x01,0x50,0x37,0x15,0xFD,0x15,0x37,0x50,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"堡\",97*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x24,0xF8,0x97,0xF4,0x04,0xFC,0x00,0x0F,0x04,0x02,0x04,\n0x00,0x07,0x08,0x08,0x09,0x0D,/*\"飽\",98*/},{\n\n0x06,0xAA,0xFA,0xAA,0x82,0xB3,0xAE,0xFA,0xAA,0xA2,0x06,0x00,0x03,0x0A,0x06,0x02,\n0x03,0x02,0x06,0x0A,0x03,0x00,/*\"寶\",99*/},{\n\n0x88,0x88,0xFF,0x48,0x08,0xF4,0x97,0x94,0xF4,0x04,0xFC,0x00,0x08,0x0F,0x00,0x00,\n0x07,0x08,0x08,0x08,0x09,0x0D,/*\"抱\",100*/},{\n\n0x10,0xB4,0xDF,0xB4,0x10,0xFE,0x42,0xC2,0x52,0xDE,0x00,0x02,0x02,0x0F,0x02,0x02,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"報\",101*/},{\n\n0x00,0x5F,0x55,0xF5,0x55,0x55,0x55,0xF5,0x55,0x5F,0x00,0x05,0x05,0x0B,0x05,0x09,\n0x0F,0x01,0x05,0x0B,0x05,0x05,/*\"暴\",102*/},{\n\n0xA4,0xAA,0x55,0xA8,0xC4,0x10,0x08,0x27,0xC4,0x04,0xFC,0x02,0x02,0x09,0x08,0x07,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"豹\",103*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x08,0xF4,0x97,0xF4,0x04,0xFC,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x07,0x08,0x08,0x09,0x0D,/*\"鮑\",104*/},{\n\n0x78,0x00,0xFF,0x04,0x00,0x5F,0xF5,0x55,0xF5,0x5F,0x00,0x08,0x06,0x01,0x06,0x05,\n0x0B,0x05,0x0F,0x05,0x0B,0x05,/*\"爆\",105*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0x42,0x22,0xFA,0x06,0x22,0xC2,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"杯\",106*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x00,0x0F,0x04,0x0F,0x02,\n0x03,0x02,0x02,0x0F,0x02,0x02,/*\"碑\",107*/},{\n\n0x22,0x2A,0x2A,0x7F,0x00,0x80,0x00,0x7F,0x2A,0x2A,0x22,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"悲\",108*/},{\n\n0x00,0x7C,0x54,0xD4,0x76,0x5D,0xD4,0x54,0x54,0x7C,0x00,0x02,0x02,0x03,0x02,0x02,\n0x02,0x0F,0x02,0x02,0x02,0x02,/*\"卑\",109*/},{\n\n0x10,0x10,0x10,0xFF,0x00,0x00,0xFF,0x20,0x10,0x08,0x04,0x02,0x02,0x01,0x0F,0x00,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"北\",110*/},{\n\n0x0A,0x4A,0xCA,0x5F,0x40,0xE0,0x40,0x5F,0xCA,0x4A,0x0A,0x04,0x04,0x07,0x05,0x05,\n0x0F,0x05,0x05,0x07,0x04,0x04,/*\"輩\",111*/},{\n\n0x12,0x12,0xEA,0xBF,0xA0,0xA0,0xA7,0xAA,0xEA,0x09,0x0C,0x00,0x00,0x0F,0x02,0x02,\n0x02,0x02,0x0A,0x0F,0x00,0x00,/*\"背\",112*/},{\n\n0x00,0xFE,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0xFE,0x00,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"貝\",113*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0xFE,0x52,0x52,0x52,0x52,0xFE,0x08,0x09,0x07,0x05,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"鋇\",114*/},{\n\n0x10,0xFC,0x03,0x20,0xAA,0xB2,0xA2,0xA3,0xB2,0xAA,0x20,0x00,0x0F,0x00,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"倍\",115*/},{\n\n0x10,0x8A,0x44,0xFB,0x00,0xFE,0x52,0x52,0x52,0x52,0xFE,0x01,0x08,0x08,0x07,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"狽\",116*/},{\n\n0x10,0xFC,0x03,0x48,0xEA,0xBF,0xAA,0xEA,0xAF,0xAA,0xEA,0x00,0x0F,0x00,0x00,0x0F,\n0x02,0x02,0x07,0x02,0x0A,0x0F,/*\"備\",117*/},{\n\n0x10,0xFC,0x43,0x28,0xFA,0xAF,0xAA,0xEA,0xAF,0xAA,0xEA,0x08,0x07,0x00,0x06,0x09,\n0x0A,0x0C,0x09,0x0C,0x02,0x0D,/*\"憊\",118*/},{\n\n0x78,0x00,0xFF,0x04,0x20,0xAA,0xB2,0xA3,0xB2,0xAA,0x20,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"焙\",119*/},{\n\n0x84,0x45,0xF6,0xAC,0x00,0xFC,0x24,0xE4,0x3F,0xE4,0x0C,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"被\",120*/},{\n\n0x20,0x24,0x14,0xAC,0x26,0x75,0x24,0xAC,0x14,0x24,0x20,0x01,0x09,0x05,0x03,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"奔\",121*/},{\n\n0x12,0x12,0x12,0x97,0x52,0xFA,0x52,0x97,0x12,0x12,0x12,0x02,0x02,0x01,0x02,0x02,\n0x0F,0x02,0x02,0x01,0x02,0x02,/*\"苯\",122*/},{\n\n0x04,0x04,0x84,0x64,0x14,0xFF,0x14,0x64,0x84,0x04,0x04,0x02,0x01,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x01,0x02,/*\"本\",123*/},{\n\n0x14,0x13,0x12,0x96,0x52,0xFC,0x53,0x92,0x16,0x12,0x12,0x02,0x02,0x01,0x02,0x02,\n0x0F,0x02,0x02,0x01,0x02,0x02,/*\"笨\",124*/},{\n\n0x00,0xF6,0x54,0x54,0xF4,0x07,0xF4,0x54,0x54,0xF6,0x00,0x08,0x07,0x01,0x09,0x0F,\n0x08,0x07,0x01,0x09,0x0F,0x00,/*\"崩\",125*/},{\n\n0xDC,0xB3,0xC8,0x00,0xF6,0x54,0xF4,0x07,0xF4,0x54,0xF6,0x0E,0x00,0x06,0x08,0x07,\n0x09,0x0F,0x08,0x07,0x09,0x0F,/*\"繃\",126*/},{\n\n0x09,0xE9,0xA9,0xA5,0xA5,0xEF,0xA1,0xA5,0xA5,0xE9,0x09,0x08,0x07,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"甭\",127*/},{\n\n0x91,0x89,0xBD,0xA7,0x25,0xE5,0xA5,0x25,0xA5,0x7D,0x01,0x04,0x04,0x02,0x01,0x08,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"泵\",128*/},{\n\n0x9E,0x12,0xFE,0x40,0xF6,0x54,0xF4,0x07,0xF4,0x54,0xF6,0x07,0x04,0x03,0x0A,0x07,\n0x09,0x0F,0x08,0x07,0x09,0x0F,/*\"蹦\",129*/},{\n\n0x11,0xF2,0x00,0x44,0x45,0xFE,0x44,0x44,0xFE,0x45,0x44,0x08,0x07,0x08,0x0C,0x0A,\n0x09,0x08,0x08,0x0F,0x08,0x08,/*\"迸\",130*/},{\n\n0x10,0x11,0xF2,0x00,0xE1,0xAF,0xAB,0xEB,0xAB,0xAF,0xE1,0x08,0x04,0x03,0x04,0x0B,\n0x0A,0x0A,0x0B,0x0A,0x0A,0x0B,/*\"逼\",131*/},{\n\n0x00,0xE0,0xBE,0xAA,0xAB,0xEA,0xAA,0xAA,0xBE,0xE0,0x00,0x02,0x0B,0x06,0x02,0x02,\n0x03,0x02,0x02,0x0E,0x03,0x02,/*\"鼻\",132*/},{\n\n0x00,0xFF,0x10,0x10,0x10,0x00,0xFF,0x20,0x10,0x08,0x04,0x00,0x0F,0x04,0x02,0x01,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"比\",133*/},{\n\n0xD0,0x57,0x55,0x7D,0x55,0x57,0xD0,0x00,0xFF,0x31,0xCF,0x0F,0x08,0x0F,0x0D,0x0F,\n0x08,0x0F,0x00,0x0F,0x02,0x01,/*\"鄙\",134*/},{\n\n0x44,0x43,0x52,0x56,0x52,0xFC,0x53,0x52,0xF6,0x42,0x42,0x04,0x04,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x04,0x04,/*\"筆\",135*/},{\n\n0x48,0x24,0xF2,0x09,0xFC,0x24,0xE4,0x3F,0x24,0xE4,0x0C,0x00,0x00,0x0F,0x08,0x07,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"彼\",136*/},{\n\n0xAA,0xAA,0xBE,0xAA,0xAA,0x80,0xBE,0xAB,0xAA,0xAA,0xBE,0x08,0x04,0x0E,0x0B,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"碧\",137*/},{\n\n0x02,0xFA,0x8A,0xDF,0xAA,0xAE,0xAA,0xDF,0x8A,0xFA,0x02,0x00,0x0F,0x0A,0x0A,0x0A,\n0x00,0x07,0x0A,0x0A,0x09,0x0C,/*\"蓖\",138*/},{\n\n0xCA,0x52,0x47,0xFA,0x52,0xCA,0x42,0xBA,0x27,0xE2,0x22,0x0F,0x02,0x01,0x07,0x09,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"蔽\",139*/},{\n\n0x40,0x5F,0xF5,0x55,0x55,0xFF,0x55,0x55,0xF5,0x5F,0x40,0x04,0x05,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x05,0x04,/*\"畢\",140*/},{\n\n0x7D,0x66,0xD4,0x7F,0x56,0x7D,0xC4,0x6B,0x52,0x6E,0x42,0x0A,0x0B,0x05,0x05,0x03,\n0x00,0x07,0x0A,0x0A,0x09,0x0C,/*\"斃\",141*/},{\n\n0x00,0x3F,0x24,0x14,0x54,0x80,0x1F,0x24,0xA2,0x21,0x38,0x0A,0x09,0x08,0x07,0x0C,\n0x0A,0x0A,0x09,0x0C,0x02,0x04,/*\"毖\",142*/},{\n\n0x7D,0x26,0x14,0x7F,0x16,0xBD,0x44,0x2B,0x12,0x2E,0x42,0x00,0x07,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x05,0x07,0x00,/*\"幣\",143*/},{\n\n0x00,0xFC,0x04,0xF4,0x44,0x45,0x06,0xF4,0x04,0x84,0x64,0x08,0x07,0x00,0x0F,0x08,\n0x04,0x00,0x07,0x09,0x08,0x0E,/*\"庇\",144*/},{\n\n0x08,0x90,0xFE,0x02,0xFA,0xAA,0xAB,0xFA,0xAA,0xAA,0xFA,0x09,0x04,0x03,0x08,0x0A,\n0x06,0x02,0x02,0x02,0x0E,0x02,/*\"痹\",145*/},{\n\n0xFF,0x15,0x55,0x5F,0x40,0xC0,0xE0,0x5F,0x55,0x15,0xFF,0x0F,0x00,0x04,0x02,0x01,\n0x04,0x07,0x00,0x00,0x08,0x0F,/*\"閉\",146*/},{\n\n0xF2,0x94,0x50,0xFF,0x94,0xF2,0x10,0xEF,0x08,0xF8,0x08,0x0F,0x00,0x00,0x03,0x08,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"敝\",147*/},{\n\n0x7D,0x26,0x14,0xBF,0x16,0x3D,0x44,0xAB,0x12,0x2E,0x42,0x01,0x09,0x05,0x03,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"弊\",148*/},{\n\n0x80,0x70,0x00,0xFC,0x01,0x86,0x60,0x18,0x06,0x20,0xC0,0x00,0x08,0x04,0x07,0x09,\n0x08,0x08,0x08,0x0E,0x00,0x00,/*\"必\",149*/},{\n\n0xFF,0x15,0xF5,0xBF,0xE0,0x00,0xC0,0x7F,0xD5,0x15,0xFF,0x0F,0x04,0x0F,0x0A,0x0E,\n0x01,0x05,0x0F,0x05,0x01,0x0F,/*\"闢\",150*/},{\n\n0x40,0x3E,0xEA,0xAA,0xEE,0x00,0x12,0x56,0xFB,0x56,0x12,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"壁\",151*/},{\n\n0x20,0x9F,0xF5,0xD5,0xF7,0x80,0x8A,0xAE,0xFB,0xAE,0x0A,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"臂\",152*/},{\n\n0x11,0xF2,0x80,0xFE,0x52,0xDE,0x20,0x2A,0xF3,0x2A,0x20,0x08,0x07,0x08,0x0B,0x0A,\n0x0B,0x08,0x09,0x0F,0x09,0x08,/*\"避\",153*/},{\n\n0xFE,0x32,0xCE,0x00,0x3F,0x24,0x14,0xC0,0x1F,0x24,0x32,0x0F,0x02,0x01,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"陛\",154*/},{\n\n0xE2,0xAF,0xFA,0xAF,0x12,0xFC,0xAB,0xAA,0xFE,0xAA,0xFA,0x02,0x02,0x0F,0x02,0x02,\n0x0F,0x01,0x0A,0x07,0x08,0x08,/*\"鞭\",155*/},{\n\n0x11,0xF2,0x00,0xB0,0xDE,0xB6,0xDB,0x96,0xBA,0xDE,0xB0,0x08,0x07,0x08,0x0C,0x0A,\n0x0B,0x0A,0x0A,0x0A,0x0E,0x08,/*\"邊\",156*/},{\n\n0xDC,0xB3,0xC8,0x80,0xFE,0x2A,0xEA,0x2B,0xEA,0x2A,0xEE,0x0E,0x00,0x06,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"編\",157*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x00,0x22,0x22,0x2A,0xB1,0x61,0x21,0x09,0x05,0x05,0x09,0x08,\n0x04,0x02,0x05,0x08,0x08,0x08,/*\"貶\",158*/},{\n\n0x00,0xFE,0x0A,0xEA,0x2A,0xEA,0x2B,0xEA,0x2A,0x2A,0xEE,0x08,0x07,0x00,0x0F,0x01,\n0x07,0x01,0x07,0x01,0x09,0x0F,/*\"扁\",159*/},{\n\n0x20,0x10,0xFC,0x03,0xFA,0xAA,0xAA,0xFE,0xAA,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x08,\n0x05,0x02,0x05,0x08,0x08,0x08,/*\"便\",160*/},{\n\n0x56,0x1D,0x54,0x80,0x3A,0x2B,0x3A,0x00,0x56,0x1D,0x54,0x08,0x0A,0x09,0x0B,0x05,\n0x05,0x05,0x05,0x0B,0x09,0x09,/*\"變\",161*/},{\n\n0x08,0x08,0x08,0x08,0x09,0xFA,0x08,0x48,0x88,0x08,0x08,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x01,0x00,/*\"卞\",162*/},{\n\n0x44,0x55,0xE6,0x54,0x20,0xFF,0x40,0x55,0xE6,0x54,0x40,0x00,0x09,0x07,0x01,0x08,\n0x07,0x00,0x01,0x0F,0x01,0x00,/*\"辨\",163*/},{\n\n0x55,0xE6,0x54,0x00,0x55,0x56,0x54,0x00,0x55,0xE6,0x54,0x09,0x07,0x01,0x00,0x0F,\n0x05,0x0F,0x00,0x01,0x0F,0x01,/*\"辯\",164*/},{\n\n0x55,0xE6,0x54,0x00,0xDC,0xB3,0xC8,0x00,0x55,0xE6,0x54,0x09,0x07,0x01,0x04,0x0A,\n0x0F,0x02,0x04,0x01,0x0F,0x01,/*\"辮\",165*/},{\n\n0x11,0xF2,0x40,0xFE,0xAA,0xEA,0xAB,0xEA,0xAA,0xEE,0x00,0x08,0x07,0x08,0x0B,0x08,\n0x09,0x08,0x09,0x0A,0x0B,0x08,/*\"遍\",166*/},{\n\n0x88,0x68,0xFF,0x48,0x1D,0x55,0x5F,0x55,0x5F,0x55,0x1D,0x00,0x00,0x0F,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"標\",167*/},{\n\n0x00,0xF8,0x48,0x7F,0xAA,0xAA,0xD8,0x00,0x24,0x92,0x49,0x08,0x07,0x08,0x06,0x02,\n0x06,0x08,0x0A,0x09,0x08,0x0C,/*\"彪\",168*/},{\n\n0xFF,0x49,0xFF,0x00,0x1D,0x55,0x5F,0x55,0x5F,0x55,0x1D,0x07,0x08,0x0F,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"膘\",169*/},{\n\n0x40,0x44,0x54,0x54,0xD4,0x7F,0xD4,0x54,0x54,0x44,0x40,0x04,0x04,0x02,0x0F,0x08,\n0x04,0x01,0x02,0x04,0x0A,0x09,/*\"表\",170*/},{\n\n0x3D,0x94,0xFF,0xAC,0xB6,0xBD,0xE4,0xB7,0x8A,0x16,0x22,0x08,0x00,0x07,0x0A,0x02,\n0x07,0x02,0x0A,0x07,0x00,0x08,/*\"鱉\",171*/},{\n\n0xFD,0x24,0xFF,0x14,0xA6,0xFD,0x84,0x5B,0x22,0x5E,0x82,0x08,0x06,0x00,0x06,0x08,\n0x0A,0x0C,0x08,0x0C,0x02,0x0C,/*\"憋\",172*/},{\n\n0x00,0x1E,0xF2,0x92,0x92,0x92,0x9E,0x00,0xFC,0x00,0xFF,0x08,0x06,0x01,0x00,0x08,\n0x08,0x07,0x00,0x01,0x08,0x0F,/*\"別\",173*/},{\n\n0x88,0xFE,0x02,0x7A,0xDA,0x6E,0x5B,0x6A,0xCA,0x7A,0x02,0x08,0x07,0x02,0x0F,0x05,\n0x0F,0x05,0x0F,0x05,0x0F,0x02,/*\"癟\",174*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xC8,0xFF,0x48,0x88,0x44,0x33,0x00,0x00,0x0F,0x00,0x01,\n0x00,0x0F,0x00,0x08,0x04,0x03,/*\"彬\",175*/},{\n\n0xC9,0x0A,0xF8,0x08,0x90,0x12,0xF2,0x90,0xFF,0x12,0x14,0x0C,0x03,0x04,0x08,0x0F,\n0x08,0x07,0x04,0x03,0x04,0x0E,/*\"斌\",176*/},{\n\n0x11,0x22,0x90,0x5E,0x10,0xFF,0x12,0xFD,0x57,0x55,0xFD,0x04,0x02,0x08,0x08,0x04,\n0x02,0x01,0x09,0x05,0x05,0x09,/*\"瀕\",177*/},{\n\n0x22,0x44,0x00,0x56,0xEA,0xAA,0xBB,0xAA,0xBA,0xEA,0x06,0x04,0x02,0x01,0x00,0x0B,\n0x06,0x02,0x02,0x06,0x0B,0x00,/*\"濱\",178*/},{\n\n0x86,0xEA,0x5A,0xCA,0x6A,0x7B,0xEA,0x5A,0x4A,0xCA,0x06,0x00,0x0B,0x06,0x02,0x03,\n0x02,0x02,0x03,0x06,0x0B,0x00,/*\"賓\",179*/},{\n\n0x88,0xFF,0x48,0x56,0xEA,0xAA,0xBB,0xAA,0xBA,0xEA,0x06,0x08,0x0F,0x00,0x00,0x0B,\n0x06,0x02,0x02,0x06,0x0B,0x00,/*\"擯\",180*/},{\n\n0x00,0x00,0xFE,0x12,0x12,0x12,0x12,0xF1,0x11,0x10,0x00,0x01,0x09,0x05,0x01,0x01,\n0x01,0x01,0x01,0x05,0x09,0x01,/*\"兵\",181*/},{\n\n0x02,0x04,0x90,0x10,0xF0,0x00,0xFF,0x18,0xE0,0x10,0x08,0x02,0x01,0x04,0x03,0x00,\n0x08,0x0F,0x00,0x00,0x03,0x04,/*\"冰\",182*/},{\n\n0x88,0x68,0xFF,0x48,0xF2,0x12,0x92,0x7E,0x92,0x12,0xF2,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x00,0x00,0x00,0x09,0x0F,/*\"柄\",183*/},{\n\n0xF2,0x12,0x12,0x12,0x92,0x7E,0x92,0x12,0x12,0x12,0xF2,0x0F,0x00,0x02,0x01,0x00,\n0x00,0x00,0x01,0x02,0x08,0x0F,/*\"丙\",184*/},{\n\n0x88,0xA8,0xAA,0xAA,0xAA,0xFE,0xA9,0xA9,0xA9,0xE8,0x88,0x00,0x0A,0x0A,0x06,0x02,\n0x0F,0x02,0x06,0x0A,0x0B,0x00,/*\"秉\",185*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0x89,0xFA,0x88,0x88,0xFA,0x89,0x00,0x0F,0x04,0x02,0x04,\n0x08,0x07,0x00,0x00,0x0F,0x00,/*\"餅\",186*/},{\n\n0x78,0x00,0xFF,0x08,0xF6,0x12,0x92,0x7E,0x92,0x12,0xF2,0x08,0x06,0x01,0x02,0x0F,\n0x01,0x00,0x00,0x00,0x09,0x0F,/*\"炳\",187*/},{\n\n0x08,0x90,0xFC,0x04,0xD4,0x55,0x56,0xF4,0x54,0x54,0xD4,0x09,0x04,0x03,0x00,0x0F,\n0x02,0x01,0x00,0x01,0x0A,0x0F,/*\"病\",188*/},{\n\n0x48,0x88,0x09,0xFA,0x08,0x08,0x08,0xFA,0x09,0x88,0x48,0x08,0x08,0x09,0x0F,0x08,\n0x08,0x08,0x0F,0x09,0x08,0x08,/*\"並\",189*/},{\n\n0x22,0xFE,0x22,0x00,0xFC,0x24,0xE4,0x3F,0x24,0xE4,0x0C,0x04,0x07,0x02,0x08,0x07,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"玻\",190*/},{\n\n0x22,0x4A,0x12,0x07,0xF2,0x92,0x92,0xFF,0x92,0x92,0x32,0x04,0x02,0x09,0x04,0x03,\n0x08,0x0B,0x04,0x04,0x0B,0x08,/*\"菠\",191*/},{\n\n0x88,0xFF,0x48,0xD6,0xBA,0x92,0xBE,0x91,0xB9,0xD5,0x90,0x08,0x0F,0x00,0x0F,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0F,0x00,/*\"播\",192*/},{\n\n0x88,0xFF,0x48,0x00,0xB5,0xE9,0x87,0x60,0x27,0xEA,0x95,0x08,0x0F,0x00,0x00,0x0B,\n0x0E,0x00,0x0B,0x05,0x0B,0x00,/*\"撥\",193*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x04,0xC4,0x34,0xFF,0x34,0xC4,0x04,0x08,0x09,0x07,0x04,0x01,\n0x02,0x02,0x0F,0x02,0x02,0x01,/*\"鉢\",194*/},{\n\n0x22,0x44,0x00,0xFC,0x24,0xE4,0x24,0x3F,0x24,0xE4,0x0C,0x04,0x02,0x08,0x07,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"波\",195*/},{\n\n0x10,0xFF,0x10,0x00,0xFA,0x2A,0x2A,0xFF,0x2A,0x2B,0xFA,0x00,0x0F,0x00,0x00,0x02,\n0x06,0x0A,0x02,0x0A,0x0F,0x02,/*\"博\",196*/},{\n\n0x18,0x2A,0x2A,0xAF,0x6A,0x2A,0x18,0x10,0xFF,0x10,0xF0,0x02,0x02,0x0A,0x0F,0x01,\n0x09,0x04,0x03,0x08,0x08,0x07,/*\"勃\",197*/},{\n\n0x88,0xFF,0x48,0x00,0xFA,0x2A,0x2A,0xFF,0x2A,0x2B,0xFA,0x08,0x0F,0x00,0x00,0x02,\n0x06,0x0A,0x02,0x0A,0x0F,0x02,/*\"搏\",198*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xFC,0x46,0x45,0x44,0xFC,0x08,0x09,0x07,0x05,0x04,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"鉑\",199*/},{\n\n0x44,0x8B,0x16,0x02,0xF2,0x94,0x93,0x9A,0x96,0x92,0xF2,0x08,0x04,0x02,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"箔\",200*/},{\n\n0x20,0x10,0xFC,0x03,0x00,0xFC,0x44,0x46,0x45,0x44,0xFC,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"伯\",201*/},{\n\n0x80,0xBE,0xAA,0xAA,0xAB,0xEA,0xAA,0xAA,0xAA,0xBE,0x80,0x07,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x04,0x07,/*\"帛\",202*/},{\n\n0x40,0xFC,0x56,0x65,0xFC,0x00,0xFC,0x46,0x45,0x44,0xFC,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"舶\",203*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x1A,0x2A,0x2A,0xAF,0x6A,0x1A,0x08,0x07,0x08,0x0F,0x00,\n0x01,0x01,0x09,0x0F,0x01,0x01,/*\"脖\",204*/},{\n\n0x00,0xFF,0x49,0xFF,0x00,0xFA,0x2A,0xFF,0x2A,0xFB,0x02,0x08,0x07,0x08,0x0F,0x02,\n0x06,0x02,0x0A,0x0F,0x02,0x02,/*\"膊\",205*/},{\n\n0x22,0x44,0x1A,0x2A,0xAF,0x6A,0x1A,0x04,0xFF,0x04,0xFC,0x04,0x02,0x00,0x09,0x0F,\n0x01,0x09,0x06,0x09,0x08,0x07,/*\"渤\",206*/},{\n\n0x22,0x44,0x00,0xFC,0x44,0x46,0x45,0x44,0x44,0x44,0xFC,0x04,0x02,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"泊\",207*/},{\n\n0x7F,0x55,0x7F,0x55,0xC1,0x00,0xD1,0x0A,0x04,0x0A,0xD1,0x07,0x00,0x0B,0x08,0x07,\n0x08,0x08,0x05,0x02,0x05,0x08,/*\"駁\",208*/},{\n\n0x88,0x88,0xFF,0x48,0xF4,0x54,0x54,0xFF,0x54,0x55,0xF6,0x00,0x08,0x0F,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"捕\",209*/},{\n\n0x00,0x00,0x00,0xFF,0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,0x00,0x00,0x0F,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"卜\",210*/},{\n\n0xFE,0x02,0xFE,0x00,0xF4,0x54,0x54,0xFF,0x54,0x55,0xF6,0x03,0x01,0x03,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"哺\",211*/},{\n\n0x45,0xF6,0xAC,0x00,0xF4,0x54,0x54,0xFF,0x54,0x55,0xF6,0x00,0x0F,0x00,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"補\",212*/},{\n\n0x08,0x08,0xFF,0x08,0x00,0xFE,0xAA,0xAB,0xAA,0xAE,0xE0,0x02,0x02,0x01,0x01,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"埠\",213*/},{\n\n0x02,0x02,0x82,0x42,0x22,0xF2,0x0E,0x22,0x42,0x82,0x02,0x01,0x01,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x01,/*\"不\",214*/},{\n\n0x04,0xC4,0x34,0xEC,0x27,0x24,0xFC,0x24,0x24,0xE4,0x04,0x01,0x00,0x00,0x07,0x00,\n0x00,0x0F,0x00,0x04,0x07,0x00,/*\"布\",215*/},{\n\n0x20,0x20,0x3E,0xA0,0x20,0xBF,0x24,0x24,0x24,0xA4,0x20,0x00,0x0A,0x09,0x08,0x04,\n0x07,0x02,0x02,0x01,0x00,0x00,/*\"步\",216*/},{\n\n0x4C,0x93,0x02,0x16,0xF2,0x54,0xFB,0x52,0x56,0xFA,0x12,0x08,0x04,0x00,0x01,0x03,\n0x05,0x01,0x09,0x0F,0x01,0x01,/*\"簿\",217*/},{\n\n0x20,0xAA,0xB2,0xA3,0xB2,0xAA,0x20,0xFE,0x02,0x32,0xCE,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x00,0x0F,0x02,0x02,0x01,/*\"部\",218*/},{\n\n0x78,0x00,0xFF,0x48,0x24,0xFC,0x27,0xF4,0x24,0x24,0xE4,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x00,0x0F,0x00,0x04,0x07,/*\"怖\",219*/},{\n\n0x88,0xFF,0x48,0x20,0x56,0x2A,0x5A,0x43,0x5A,0x2A,0x5E,0x08,0x0F,0x00,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"擦\",220*/},{\n\n0x8A,0x44,0xFB,0x22,0xEA,0xAA,0xBF,0xAA,0xAA,0xEA,0x22,0x08,0x08,0x07,0x00,0x0F,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"猜\",221*/},{\n\n0x48,0x4A,0x5A,0xEF,0x4A,0x4A,0x08,0xFF,0x08,0xE9,0x0A,0x04,0x02,0x0F,0x04,0x01,\n0x06,0x09,0x04,0x03,0x04,0x0E,/*\"裁\",222*/},{\n\n0x08,0x88,0x68,0xFF,0x28,0x48,0x80,0x48,0x28,0xFF,0x08,0x01,0x00,0x00,0x0F,0x00,\n0x01,0x00,0x00,0x08,0x0F,0x00,/*\"材\",223*/},{\n\n0x00,0x08,0x08,0x08,0x88,0x48,0x28,0x18,0xFF,0x08,0x08,0x02,0x02,0x01,0x01,0x00,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"才\",224*/},{\n\n0xFE,0x2A,0x2A,0x2A,0xFE,0x00,0x08,0x88,0x68,0xFF,0x08,0x09,0x05,0x01,0x05,0x09,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"財\",225*/},{\n\n0xFE,0x92,0xFE,0x00,0x4A,0x52,0x46,0xEA,0x41,0x51,0x4D,0x0F,0x04,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"睬\",226*/},{\n\n0x9E,0x12,0xFE,0x80,0x4A,0x52,0x46,0xEA,0x41,0x51,0x4D,0x0F,0x08,0x07,0x04,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"踩\",227*/},{\n\n0x08,0x08,0xFF,0x88,0x4A,0x52,0x46,0xEA,0x41,0x51,0x4D,0x01,0x09,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"採\",228*/},{\n\n0x4A,0x52,0x46,0xE9,0x51,0x4D,0x00,0x88,0x44,0x23,0x18,0x04,0x02,0x01,0x0F,0x01,\n0x02,0x08,0x08,0x04,0x02,0x01,/*\"彩\",229*/},{\n\n0x12,0x32,0x52,0x17,0x32,0xD2,0x12,0x4F,0x2A,0x0A,0x02,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"菜\",230*/},{\n\n0x22,0xB2,0x5F,0x2A,0x5A,0x42,0x5A,0x2A,0x6F,0x9A,0x82,0x01,0x08,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x08,0x00,/*\"蔡\",231*/},{\n\n0xA8,0xA6,0xDC,0xD7,0xAD,0xD5,0xA0,0xD5,0xC9,0x97,0xA0,0x00,0x00,0x0F,0x0A,0x02,\n0x03,0x02,0x06,0x0B,0x0C,0x0A,/*\"餐\",232*/},{\n\n0x30,0x2C,0xA6,0xB5,0x44,0x24,0x44,0xB4,0xAE,0x24,0x30,0x01,0x09,0x0A,0x0A,0x0A,\n0x09,0x05,0x04,0x04,0x01,0x01,/*\"參\",233*/},{\n\n0x96,0x8D,0xE7,0xBD,0xB5,0xE0,0xB6,0xAD,0xE7,0x9D,0x95,0x0B,0x0A,0x0F,0x0A,0x0B,\n0x00,0x0B,0x0A,0x0F,0x0A,0x0B,/*\"蠶\",234*/},{\n\n0x82,0x7E,0x92,0xF2,0x24,0x24,0xD7,0x8A,0xD7,0xA2,0xBA,0x08,0x04,0x02,0x01,0x09,\n0x09,0x05,0x02,0x05,0x08,0x0E,/*\"殘\",235*/},{\n\n0x78,0x00,0xFF,0x04,0xFA,0xAA,0xFF,0xAA,0xFE,0x12,0xF1,0x00,0x00,0x0F,0x00,0x02,\n0x02,0x0F,0x0A,0x07,0x00,0x0F,/*\"慚\",236*/},{\n\n0x78,0x00,0xFF,0x04,0x58,0x56,0xBB,0x22,0x5B,0x56,0x58,0x00,0x00,0x0F,0x00,0x05,\n0x05,0x0A,0x0A,0x05,0x04,0x02,/*\"慘\",237*/},{\n\n0x78,0x00,0xFF,0x14,0x58,0xAF,0x1A,0xC0,0x2A,0x92,0x2E,0x08,0x06,0x01,0x07,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"燦\",238*/},{\n\n0x12,0x12,0xF7,0xAA,0xAA,0xB6,0xAA,0xAA,0xF7,0x12,0x12,0x08,0x04,0x03,0x0E,0x0A,\n0x0A,0x0A,0x0A,0x0B,0x0E,0x00,/*\"蒼\",239*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x04,0xFC,0xAA,0xAD,0xFA,0x04,0x08,0x07,0x01,0x0A,0x0F,\n0x01,0x0E,0x0A,0x0A,0x0A,0x0E,/*\"艙\",240*/},{\n\n0x04,0x04,0xFC,0xAA,0xAA,0xAD,0xAA,0xAA,0xFC,0x04,0x04,0x08,0x06,0x01,0x0E,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"倉\",241*/},{\n\n0x22,0x44,0x00,0x08,0xFC,0xAA,0xAD,0xA9,0xAA,0xFC,0x08,0x04,0x02,0x04,0x03,0x0E,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"滄\",242*/},{\n\n0xBA,0xA2,0xFA,0x0F,0xEA,0xAA,0xEA,0xAF,0xFA,0x0E,0xCA,0x03,0x08,0x07,0x00,0x0F,\n0x0A,0x0E,0x0B,0x04,0x07,0x0C,/*\"藏\",243*/},{\n\n0x88,0x88,0xFF,0x48,0x70,0x57,0x75,0x85,0x75,0x57,0x70,0x00,0x08,0x0F,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"操\",244*/},{\n\n0x24,0xA8,0xFF,0x24,0x11,0xF2,0x08,0xA6,0xA4,0xBF,0xA4,0x01,0x00,0x0F,0x01,0x08,\n0x07,0x08,0x0B,0x0A,0x0A,0x0B,/*\"糙\",245*/},{\n\n0x88,0x68,0xFF,0x48,0xFA,0xAA,0xFF,0xAA,0xFF,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"槽\",246*/},{\n\n0x02,0xFA,0xAA,0xAA,0xFF,0xAA,0xFF,0xAA,0xAA,0xFA,0x02,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"曹\",247*/},{\n\n0x02,0xFA,0xAA,0xAF,0xAA,0xAA,0xAA,0xAF,0xAA,0xFA,0x02,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"草\",248*/},{\n\n0x00,0xFE,0x02,0xFA,0xAA,0xAA,0xFB,0x02,0xF2,0x02,0xFA,0x08,0x07,0x00,0x0B,0x06,\n0x06,0x0B,0x00,0x03,0x08,0x0F,/*\"廁\",249*/},{\n\n0x14,0xD3,0x52,0x56,0x52,0xF8,0x54,0x53,0x52,0xD6,0x12,0x04,0x05,0x02,0x02,0x01,\n0x0F,0x01,0x02,0x03,0x05,0x04,/*\"策\",250*/},{\n\n0x10,0xFC,0x03,0xFE,0x2A,0x2A,0xFE,0x00,0xFC,0x00,0xFF,0x00,0x0F,0x08,0x05,0x01,\n0x01,0x05,0x08,0x01,0x08,0x0F,/*\"側\",251*/},{\n\n0x40,0xFE,0x42,0x42,0xFE,0x42,0xFE,0x42,0x42,0xFE,0x40,0x00,0x0F,0x00,0x00,0x07,\n0x00,0x07,0x00,0x08,0x0F,0x00,/*\"冊\",252*/},{\n\n0x11,0x22,0x00,0xFE,0x2A,0x2A,0xFE,0x00,0xFC,0x00,0xFF,0x04,0x02,0x08,0x05,0x01,\n0x01,0x05,0x08,0x01,0x08,0x0F,/*\"測\",253*/},{\n\n0x00,0xFF,0x05,0xF5,0xB5,0xDD,0xF5,0x95,0xDD,0xB5,0xF7,0x08,0x07,0x00,0x00,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"層\",254*/},{\n\n0x9E,0x12,0xFE,0x40,0x3E,0xAB,0xA2,0xBE,0xA2,0xAB,0x3E,0x07,0x04,0x03,0x02,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"蹭\",255*/},{\n\n0x88,0xFF,0x48,0x00,0xC8,0x2A,0x0A,0xFE,0x09,0x49,0xC8,0x08,0x0F,0x00,0x00,0x0F,\n0x05,0x04,0x07,0x04,0x05,0x0F,/*\"插\",256*/},{\n\n0x00,0x02,0x1E,0x62,0x82,0x0A,0x92,0x42,0x32,0x0E,0x00,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x04,0x08,0x08,/*\"叉\",257*/},{\n\n0x12,0x92,0xD2,0x37,0x1A,0x12,0x12,0xD7,0x12,0x12,0x12,0x01,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"茬\",258*/},{\n\n0x42,0x42,0xA2,0xA7,0x92,0xCA,0x92,0xA7,0xA2,0x42,0x42,0x00,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x00,/*\"茶\",259*/},{\n\n0x12,0x12,0xEA,0xA6,0xA2,0xBF,0xA2,0xA6,0xEA,0x12,0x12,0x08,0x08,0x0B,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0B,0x08,0x08,/*\"查\",260*/},{\n\n0x42,0xF2,0x2E,0xE2,0x14,0xEC,0xA4,0xBF,0xA4,0xEC,0x14,0x00,0x07,0x02,0x0B,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"碴\",261*/},{\n\n0x88,0x88,0xFF,0x48,0x42,0xA7,0x92,0xCA,0x92,0xA7,0x42,0x00,0x08,0x0F,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"搽\",262*/},{\n\n0x26,0xB2,0x5E,0x2A,0x5A,0x43,0x5A,0x2A,0x6A,0x9A,0x86,0x01,0x08,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x08,0x00,/*\"察\",263*/},{\n\n0x04,0x44,0x2A,0x19,0x08,0x88,0x48,0x49,0x3A,0x04,0x04,0x00,0x0F,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x00,/*\"岔\",264*/},{\n\n0x44,0x54,0x55,0xD6,0x74,0x5C,0x54,0x56,0x55,0x54,0x44,0x04,0x02,0x09,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x08,/*\"差\",265*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x2C,0x24,0xE5,0x96,0x94,0x8C,0x0F,0x05,0x05,0x0F,0x00,\n0x01,0x01,0x07,0x08,0x08,0x0E,/*\"詫\",266*/},{\n\n0x08,0x08,0xFF,0x88,0x00,0xFE,0x12,0x92,0xF1,0x11,0x10,0x01,0x09,0x0F,0x00,0x08,\n0x07,0x00,0x00,0x0F,0x01,0x02,/*\"拆\",267*/},{\n\n0xA0,0xBE,0xA0,0x9F,0x94,0xD4,0x80,0x9F,0xA8,0xA4,0xB2,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"柴\",268*/},{\n\n0xA4,0xAA,0x55,0xA8,0xC4,0x00,0x08,0x88,0x68,0xFF,0x08,0x02,0x02,0x09,0x08,0x07,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"豺\",269*/},{\n\n0x84,0xFF,0x44,0x88,0xFC,0xAB,0xAA,0xEA,0xAE,0xB8,0x00,0x08,0x0F,0x00,0x08,0x0B,\n0x06,0x03,0x06,0x0A,0x0B,0x0C,/*\"攙\",270*/},{\n\n0x84,0xFF,0x44,0x00,0x58,0x56,0xBB,0x22,0x5B,0x56,0x58,0x08,0x0F,0x00,0x00,0x05,\n0x05,0x0A,0x0A,0x05,0x04,0x02,/*\"摻\",271*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xF7,0x55,0xF7,0x55,0xF7,0x04,0x04,0x03,0x02,0x07,\n0x00,0x05,0x05,0x0F,0x05,0x05,/*\"蟬\",272*/},{\n\n0xFA,0xAD,0xFA,0x88,0xFC,0xAB,0xAA,0xEA,0xAE,0xB8,0x00,0x0F,0x04,0x02,0x0C,0x0B,\n0x06,0x03,0x06,0x0A,0x0B,0x0C,/*\"饞\",273*/},{\n\n0x55,0x56,0x54,0x88,0xFC,0xAB,0xAA,0xEA,0xAE,0xB8,0x00,0x0F,0x05,0x07,0x08,0x0B,\n0x06,0x03,0x06,0x0A,0x0B,0x0C,/*\"讒\",274*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0xFE,0xAA,0xFF,0xAA,0xBE,0x82,0x0C,0x02,0x04,0x0A,0x04,\n0x0B,0x0A,0x0F,0x0A,0x09,0x02,/*\"纏\",275*/},{\n\n0x4A,0xF9,0x4A,0x00,0xF2,0x16,0xDA,0x93,0xFA,0x96,0x92,0x0A,0x0F,0x05,0x08,0x07,\n0x09,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"鏟\",276*/},{\n\n0x00,0xE2,0x22,0xF6,0xAA,0xAA,0xEB,0xAA,0xB6,0xA2,0x22,0x08,0x07,0x09,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"產\",277*/},{\n\n0xFF,0x05,0x1F,0xF4,0x5C,0xF0,0x5C,0xF4,0x1F,0x05,0xFF,0x0F,0x00,0x04,0x05,0x05,\n0x0F,0x05,0x05,0x04,0x08,0x0F,/*\"闡\",278*/},{\n\n0xFA,0x8A,0xBB,0xAA,0xFA,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x08,0x0F,0x0A,0x0F,0x08,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"顫\",279*/},{\n\n0x00,0xC0,0x5F,0x55,0x55,0x55,0x55,0x55,0x5F,0xC0,0x00,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"昌\",280*/},{\n\n0x8A,0x44,0xFB,0x00,0xC0,0x5F,0x55,0x55,0x55,0x5F,0xC0,0x08,0x08,0x07,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"猖\",281*/},{\n\n0x08,0x08,0xFF,0x08,0x40,0xDF,0x55,0x55,0x55,0x5F,0x40,0x02,0x02,0x01,0x01,0x0A,\n0x05,0x0B,0x05,0x0B,0x09,0x07,/*\"場\",282*/},{\n\n0x06,0x72,0xA3,0xAE,0xAA,0xAB,0xAA,0x9E,0x93,0xC2,0x06,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"嘗\",283*/},{\n\n0x0C,0x04,0x75,0x56,0x54,0xD7,0x54,0x56,0x75,0x04,0x0C,0x00,0x07,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x05,0x07,0x00,/*\"常\",284*/},{\n\n0x40,0xC0,0x7F,0x55,0x55,0xD5,0x55,0x55,0x55,0xC1,0x40,0x00,0x0F,0x04,0x02,0x00,\n0x00,0x01,0x02,0x05,0x08,0x08,/*\"長\",285*/},{\n\n0x20,0x10,0xFC,0x03,0xE6,0xBB,0xAA,0xAB,0xAA,0xBB,0xE6,0x00,0x00,0x0F,0x00,0x0B,\n0x06,0x02,0x02,0x02,0x06,0x0B,/*\"償\",286*/},{\n\n0x00,0xFF,0x49,0xFF,0x40,0xDF,0x55,0x55,0x55,0x5F,0x40,0x08,0x07,0x08,0x0F,0x0A,\n0x05,0x0B,0x05,0x0B,0x09,0x07,/*\"腸\",287*/},{\n\n0xFE,0x02,0xEA,0xA2,0xBE,0x23,0xEA,0xA2,0x3E,0xE2,0x22,0x07,0x00,0x0F,0x02,0x03,\n0x08,0x0F,0x05,0x02,0x05,0x08,/*\"廠\",288*/},{\n\n0xF2,0x14,0xD0,0x5F,0xD4,0xF2,0x10,0xEF,0x08,0xF8,0x08,0x0F,0x00,0x03,0x02,0x0B,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"敞\",289*/},{\n\n0xFC,0x24,0xFF,0x24,0xFC,0x40,0x5F,0xD5,0x55,0x55,0x5F,0x03,0x01,0x0F,0x01,0x03,\n0x02,0x05,0x0B,0x05,0x0B,0x0F,/*\"暢\",290*/},{\n\n0xFE,0x02,0xFE,0x00,0xC0,0x5F,0x55,0x55,0x55,0x5F,0xC0,0x03,0x01,0x03,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"唱\",291*/},{\n\n0x20,0x10,0xFC,0x03,0xC0,0x5F,0x55,0x55,0x55,0x5F,0xC0,0x00,0x00,0x0F,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"倡\",292*/},{\n\n0x20,0xA4,0x24,0xFF,0x24,0x20,0xD2,0x4E,0x42,0x52,0xDE,0x08,0x07,0x04,0x0F,0x09,\n0x09,0x0B,0x0A,0x0A,0x0A,0x0B,/*\"超\",293*/},{\n\n0x88,0x88,0xFF,0x48,0x40,0x38,0x00,0xFF,0x00,0x04,0xB8,0x00,0x08,0x0F,0x00,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,/*\"抄\",294*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x40,0x38,0x00,0xFF,0x00,0x04,0xB8,0x08,0x09,0x07,0x04,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,/*\"鈔\",295*/},{\n\n0x00,0xFA,0xAA,0xAF,0xAA,0xFA,0x00,0xFE,0x92,0x92,0xFE,0x02,0x02,0x02,0x0F,0x02,\n0x02,0x0A,0x07,0x00,0x08,0x0F,/*\"朝\",296*/},{\n\n0xFC,0x04,0xFC,0x00,0xFA,0xAF,0xFA,0x00,0xFE,0x92,0xFE,0x03,0x01,0x03,0x00,0x02,\n0x0F,0x02,0x08,0x07,0x08,0x0F,/*\"嘲\",297*/},{\n\n0x22,0x44,0xFA,0xAA,0xAF,0xAA,0xFA,0x00,0xFE,0x92,0xFE,0x04,0x02,0x02,0x02,0x0F,\n0x02,0x02,0x08,0x07,0x08,0x0F,/*\"潮\",298*/},{\n\n0x00,0xFA,0xAD,0xA8,0xAA,0xFD,0xA8,0xAA,0xAD,0xF8,0x00,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"巢\",299*/},{\n\n0xFE,0x02,0x02,0xFE,0x40,0x38,0x00,0xFF,0x00,0x04,0xB8,0x03,0x01,0x01,0x03,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,/*\"吵\",300*/},{\n\n0x78,0x00,0xFF,0x08,0x44,0x38,0x00,0xFF,0x00,0x04,0xB8,0x08,0x06,0x01,0x06,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,/*\"炒\",301*/},{\n\n0x02,0xFA,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xFA,0x02,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"車\",302*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xF8,0x00,0x00,0xFF,0x10,0x10,0x00,0x08,0x0F,0x00,0x08,\n0x0F,0x08,0x08,0x0F,0x08,0x08,/*\"扯\",303*/},{\n\n0x88,0xFF,0x4A,0xEE,0xAB,0xEE,0x12,0xEC,0x0B,0xF8,0x08,0x08,0x0F,0x00,0x0F,0x02,\n0x0F,0x08,0x04,0x03,0x04,0x08,/*\"撤\",304*/},{\n\n0x04,0x5B,0x4A,0x7F,0x4A,0xDA,0x40,0x5E,0x40,0x20,0x3F,0x04,0x04,0x05,0x05,0x0D,\n0x0F,0x05,0x05,0x05,0x04,0x04,/*\"掣\",305*/},{\n\n0x24,0xF2,0x09,0x0A,0xEE,0xAB,0xEE,0x12,0xE8,0x07,0xFC,0x00,0x0F,0x00,0x00,0x0F,\n0x02,0x0F,0x08,0x04,0x03,0x0C,/*\"徹\",306*/},{\n\n0x22,0x44,0x0A,0xEE,0xAB,0xEE,0x12,0xEC,0x0B,0xF8,0x08,0x04,0x02,0x00,0x0F,0x02,\n0x0F,0x08,0x04,0x03,0x04,0x08,/*\"澈\",307*/},{\n\n0x88,0x68,0xFF,0x28,0xC8,0xFF,0x48,0x80,0xFF,0x31,0xCF,0x00,0x00,0x0F,0x01,0x00,\n0x0F,0x00,0x00,0x0F,0x02,0x01,/*\"郴\",308*/},{\n\n0x00,0xFE,0x92,0x92,0x92,0x92,0x9E,0x92,0x92,0x92,0xF2,0x00,0x0F,0x08,0x08,0x08,\n0x08,0x0F,0x08,0x08,0x08,0x08,/*\"臣\",309*/},{\n\n0x00,0xFE,0x22,0x2A,0xEA,0x2A,0x2A,0xEA,0x2A,0x2A,0xA2,0x08,0x07,0x00,0x00,0x0F,\n0x04,0x00,0x01,0x02,0x05,0x08,/*\"辰\",310*/},{\n\n0x00,0xFE,0x2A,0xEA,0xBE,0xAA,0x2B,0xFE,0xAA,0xBA,0xC2,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"塵\",311*/},{\n\n0x00,0xF0,0x1F,0x55,0x55,0x55,0x55,0x55,0x55,0x5F,0x10,0x08,0x07,0x01,0x0F,0x09,\n0x01,0x03,0x05,0x05,0x0B,0x09,/*\"晨\",312*/},{\n\n0x78,0x00,0xFF,0x08,0x1C,0x04,0xC4,0x3F,0xC4,0x04,0x1C,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0C,/*\"忱\",313*/},{\n\n0x10,0x22,0x04,0x00,0x06,0xF2,0x12,0x12,0xF2,0x02,0x06,0x04,0x02,0x01,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"沉\",314*/},{\n\n0xFE,0x32,0xCE,0x00,0xFA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x0F,0x02,0x01,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"陳\",315*/},{\n\n0x20,0xA4,0x24,0xFF,0x24,0x10,0xAC,0xA3,0x94,0x48,0x10,0x08,0x07,0x04,0x0F,0x09,\n0x08,0x0A,0x0A,0x0A,0x09,0x08,/*\"趁\",316*/},{\n\n0x45,0xF6,0xAC,0x00,0xAA,0xF3,0xAA,0xFE,0xAA,0xAA,0xFE,0x00,0x0F,0x00,0x04,0x0A,\n0x0F,0x02,0x0C,0x07,0x08,0x0E,/*\"襯\",317*/},{\n\n0x88,0x88,0xFF,0x48,0x86,0xBB,0xAA,0xAB,0xAA,0xBB,0x86,0x00,0x08,0x0F,0x00,0x08,\n0x0B,0x06,0x0A,0x0F,0x02,0x02,/*\"撐\",318*/},{\n\n0x12,0xD2,0xFE,0x91,0x0A,0xF2,0xA6,0xFA,0xA1,0xE9,0x05,0x01,0x00,0x0F,0x00,0x02,\n0x0F,0x02,0x03,0x0A,0x0F,0x02,/*\"稱\",319*/},{\n\n0x08,0xFF,0x08,0x00,0xFC,0x24,0xE4,0x04,0xFF,0x84,0x65,0x02,0x03,0x09,0x06,0x01,\n0x02,0x0B,0x04,0x03,0x04,0x0E,/*\"城\",320*/},{\n\n0x88,0x68,0xFF,0x48,0x25,0xD9,0x57,0x50,0x57,0xDA,0x25,0x00,0x00,0x0F,0x00,0x08,\n0x0B,0x0D,0x09,0x0D,0x0B,0x08,/*\"橙\",321*/},{\n\n0x00,0xFC,0x24,0x24,0xE4,0x04,0xFF,0x04,0x85,0x66,0x04,0x08,0x07,0x00,0x02,0x0B,\n0x04,0x02,0x01,0x02,0x04,0x0F,/*\"成\",322*/},{\n\n0x00,0x2F,0x29,0x29,0x29,0xE9,0x29,0x29,0x29,0x2F,0x00,0x08,0x08,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x08,0x08,/*\"呈\",323*/},{\n\n0x28,0x2A,0xAA,0xFA,0x0A,0xFE,0x09,0xF9,0x49,0x29,0x88,0x09,0x09,0x04,0x02,0x01,\n0x0F,0x01,0x02,0x05,0x09,0x09,/*\"乘\",324*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0x2F,0x29,0xE9,0x29,0x2F,0x00,0x01,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"程\",325*/},{\n\n0x12,0xF9,0x06,0x54,0xF7,0x54,0x06,0xB8,0x47,0xBC,0x04,0x08,0x05,0x00,0x05,0x0B,\n0x0D,0x09,0x0C,0x00,0x04,0x09,/*\"懲\",326*/},{\n\n0x10,0x21,0x02,0x20,0xD5,0x49,0x57,0x50,0x4F,0xD2,0x29,0x04,0x02,0x01,0x08,0x0B,\n0x0D,0x09,0x09,0x0D,0x0B,0x08,/*\"澄\",327*/},{\n\n0x55,0x56,0x54,0x00,0xFC,0x24,0xE4,0x04,0xFF,0x84,0x65,0x0F,0x05,0x07,0x08,0x07,\n0x02,0x09,0x04,0x03,0x04,0x0E,/*\"誠\",328*/},{\n\n0x08,0x08,0xF9,0x11,0x51,0xFD,0x55,0x13,0xF9,0x20,0x18,0x04,0x03,0x00,0x01,0x09,\n0x0F,0x01,0x01,0x00,0x03,0x04,/*\"承\",329*/},{\n\n0x10,0x11,0xF2,0x00,0x20,0xAF,0xA9,0xE9,0xA9,0xAF,0x20,0x08,0x04,0x03,0x04,0x0A,\n0x0A,0x0A,0x0B,0x0A,0x0A,0x0A,/*\"逞\",330*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x00,0xBE,0xAA,0xBF,0xAA,0xAA,0xBE,0x04,0x0A,0x08,0x07,0x00,\n0x00,0x03,0x02,0x0A,0x0A,0x06,/*\"騁\",331*/},{\n\n0x12,0xD2,0xFE,0x51,0x88,0xB2,0x82,0xFE,0x82,0xA2,0x98,0x01,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"秤\",332*/},{\n\n0xFC,0x04,0xFC,0x00,0x2A,0x7F,0x2A,0xC2,0x3E,0x42,0x7E,0x03,0x01,0x03,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"喫\",333*/},{\n\n0x88,0xFE,0x02,0xDE,0xAA,0xB6,0x43,0x4A,0xDA,0x6A,0xDA,0x08,0x07,0x01,0x0A,0x07,\n0x0A,0x07,0x08,0x0F,0x0A,0x0A,/*\"癡\",334*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0x54,0x54,0x5F,0xF4,0x54,0x50,0x00,0x08,0x0F,0x00,0x00,\n0x01,0x0A,0x08,0x0F,0x00,0x00,/*\"持\",335*/},{\n\n0x40,0x5F,0x55,0xD5,0x5F,0x40,0x00,0xFF,0x10,0x08,0x84,0x08,0x07,0x08,0x0F,0x09,\n0x08,0x08,0x09,0x0A,0x0A,0x0B,/*\"匙\",336*/},{\n\n0x22,0x44,0x40,0xFC,0x20,0x10,0xFF,0x08,0x04,0xFC,0x00,0x04,0x02,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x09,0x09,0x0C,/*\"池\",337*/},{\n\n0x11,0xF2,0x00,0xFF,0x05,0xED,0x95,0xFD,0x95,0xAD,0x07,0x08,0x07,0x0A,0x09,0x0B,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"遲\",338*/},{\n\n0xF2,0x92,0x92,0x9E,0x20,0xFC,0x10,0xFF,0x08,0x84,0xFC,0x00,0x08,0x08,0x07,0x00,\n0x07,0x08,0x09,0x08,0x08,0x0E,/*\"弛\",339*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x20,0xFC,0x10,0xFF,0x88,0xFC,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x07,0x08,0x09,0x08,0x0E,/*\"馳\",340*/},{\n\n0x02,0xFE,0x52,0xFE,0x02,0xC0,0x00,0xF1,0x06,0x10,0xE0,0x02,0x03,0x02,0x0F,0x05,\n0x03,0x00,0x07,0x08,0x08,0x0E,/*\"恥\",341*/},{\n\n0x08,0xE8,0x8E,0xC8,0xB8,0xCF,0xBA,0xCA,0x8A,0xEA,0x08,0x00,0x0F,0x08,0x0C,0x0B,\n0x0C,0x0B,0x0C,0x08,0x0F,0x00,/*\"齒\",342*/},{\n\n0x20,0x10,0xFC,0x03,0x08,0x44,0xAB,0x52,0x6A,0x46,0xC0,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x04,0x05,0x02,0x01,0x00,/*\"侈\",343*/},{\n\n0x00,0x00,0xFE,0x22,0x22,0x22,0xE2,0x22,0x22,0x3E,0x00,0x08,0x06,0x01,0x00,0x00,\n0x00,0x00,0x03,0x04,0x08,0x08,/*\"尺\",344*/},{\n\n0x20,0xA4,0x24,0xE4,0x24,0x3F,0x24,0xE4,0x24,0xA4,0x20,0x02,0x09,0x04,0x03,0x00,\n0x00,0x08,0x0F,0x00,0x00,0x03,/*\"赤\",345*/},{\n\n0x24,0xE4,0x3F,0xE4,0x89,0x51,0xFF,0x88,0x51,0xFF,0x00,0x08,0x05,0x02,0x05,0x08,\n0x0A,0x0B,0x08,0x0A,0x0B,0x08,/*\"翅\",346*/},{\n\n0x00,0x00,0xFE,0x12,0x12,0x92,0x92,0xF1,0x11,0x11,0x10,0x08,0x06,0x01,0x00,0x00,\n0x00,0x00,0x0F,0x01,0x02,0x00,/*\"斥\",347*/},{\n\n0x78,0x00,0xFF,0x08,0xD6,0x5B,0xD6,0x10,0xFF,0x12,0xD4,0x08,0x06,0x01,0x02,0x0F,\n0x05,0x0F,0x04,0x03,0x05,0x0E,/*\"熾\",348*/},{\n\n0x04,0x44,0x64,0xD4,0x4D,0x46,0x44,0xD4,0x64,0xC4,0x04,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"充\",349*/},{\n\n0x24,0xF2,0x09,0xFA,0xAA,0xFE,0xA9,0xF9,0x08,0x12,0xF2,0x00,0x0F,0x00,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x00,0x08,0x0F,/*\"衝\",350*/},{\n\n0xA0,0xAE,0xEA,0xAA,0xAA,0x3F,0xAA,0xAA,0xEA,0xAE,0xB0,0x0B,0x0A,0x0F,0x0A,0x0B,\n0x00,0x0B,0x0A,0x0F,0x0A,0x0B,/*\"蟲\",351*/},{\n\n0x30,0x16,0x54,0x54,0x54,0x5F,0x54,0x54,0x54,0x16,0x30,0x01,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x01,/*\"崇\",352*/},{\n\n0x26,0xEA,0xBA,0xAE,0xBA,0xEB,0x22,0xBE,0xAA,0xEA,0x06,0x00,0x0F,0x02,0x02,0x0A,\n0x0F,0x00,0x07,0x0A,0x0A,0x0C,/*\"寵\",353*/},{\n\n0x88,0xFF,0x48,0x00,0xFC,0x44,0x44,0xFF,0x44,0x44,0xFC,0x08,0x0F,0x00,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"抽\",354*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x20,0xFF,0x10,0xFE,0x10,0xFF,0x0F,0x05,0x05,0x05,0x0F,\n0x08,0x07,0x00,0x07,0x00,0x0F,/*\"酬\",355*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0xAA,0xAA,0xEF,0xAA,0xAA,0x6A,0x07,0x02,0x03,0x02,0x0F,\n0x0A,0x0E,0x02,0x0A,0x0F,0x02,/*\"疇\",356*/},{\n\n0x9E,0x12,0xF2,0x9E,0x22,0xAA,0xAA,0xEF,0xAA,0xAA,0x6A,0x0F,0x08,0x07,0x04,0x0E,\n0x0A,0x0E,0x02,0x0A,0x0F,0x02,/*\"躊\",357*/},{\n\n0x12,0xD2,0xFE,0x91,0xFF,0x21,0xA9,0xBD,0xA9,0x21,0xFF,0x01,0x00,0x0F,0x08,0x07,\n0x00,0x03,0x02,0x0B,0x08,0x0F,/*\"稠\",358*/},{\n\n0x48,0x2A,0xFE,0x29,0x48,0x10,0x8C,0x60,0x1F,0x68,0x84,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"愁\",359*/},{\n\n0x24,0xAB,0xAA,0xAE,0xAA,0xFC,0xAB,0xAA,0xAE,0xAA,0x62,0x0E,0x0A,0x0A,0x0E,0x00,\n0x02,0x06,0x0A,0x0F,0x02,0x02,/*\"籌\",360*/},{\n\n0x10,0xFC,0x03,0x08,0x08,0xFF,0x08,0x08,0xF8,0x00,0x00,0x00,0x0F,0x00,0x08,0x06,\n0x01,0x00,0x00,0x07,0x08,0x0E,/*\"仇\",361*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFF,0x21,0xA9,0xBD,0xA9,0x21,0xFF,0x0E,0x00,0x06,0x08,0x07,\n0x00,0x03,0x02,0x0B,0x08,0x0F,/*\"綢\",362*/},{\n\n0xFE,0x92,0xFE,0x00,0x92,0xFE,0x51,0x08,0xFF,0x10,0x0C,0x0F,0x04,0x0F,0x01,0x00,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"瞅\",363*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x00,0x7C,0xD6,0x7D,0xD4,0x7C,0x0F,0x05,0x05,0x05,0x0F,\n0x08,0x06,0x01,0x07,0x0A,0x0B,/*\"醜\",364*/},{\n\n0x00,0xFE,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xAA,0xFE,0x00,0x0A,0x0A,0x0A,0x06,0x02,\n0x03,0x02,0x06,0x0B,0x0A,0x0A,/*\"臭\",365*/},{\n\n0x84,0x45,0xF6,0x4C,0xA0,0x02,0xFE,0x02,0x02,0x02,0xFE,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"初\",366*/},{\n\n0x80,0x1E,0x10,0x10,0x10,0xFF,0x10,0x10,0x10,0x1E,0x80,0x07,0x04,0x04,0x04,0x04,\n0x07,0x04,0x04,0x04,0x04,0x0F,/*\"出\",367*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0xAA,0xBE,0xAB,0x52,0xFE,0x12,0x00,0x00,0x0F,0x04,0x0B,\n0x0E,0x0A,0x0F,0x08,0x0F,0x00,/*\"櫥\",368*/},{\n\n0x00,0xFE,0x8A,0xAA,0xBE,0xAA,0x8B,0x52,0x92,0xFE,0x12,0x08,0x07,0x0B,0x0E,0x0A,\n0x0E,0x0B,0x00,0x08,0x0F,0x00,/*\"廚\",369*/},{\n\n0xCF,0x09,0xF9,0x4F,0x22,0xA7,0xEA,0xBE,0xAA,0xB7,0x2A,0x07,0x04,0x03,0x02,0x01,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"躇\",370*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFE,0x52,0xFE,0x04,0xFF,0x04,0xFC,0x0A,0x0F,0x05,0x02,0x03,\n0x02,0x09,0x05,0x03,0x08,0x0F,/*\"鋤\",371*/},{\n\n0x2C,0xDB,0x8E,0xAA,0xBE,0x10,0xFC,0x27,0xFC,0x25,0x24,0x0B,0x06,0x03,0x0A,0x0F,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"雛\",372*/},{\n\n0x22,0x44,0xFE,0x12,0xEE,0x88,0x94,0xF3,0x94,0x88,0x10,0x04,0x02,0x0F,0x01,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"滁\",373*/},{\n\n0xFE,0x32,0xCE,0x00,0x48,0x54,0x52,0xF1,0x52,0x54,0x48,0x0F,0x02,0x01,0x04,0x02,\n0x01,0x08,0x0F,0x00,0x01,0x06,/*\"除\",374*/},{\n\n0x52,0x4A,0x7F,0x4A,0x52,0xC0,0x52,0x4A,0x7F,0x4A,0xD2,0x08,0x04,0x03,0x04,0x08,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"楚\",375*/},{\n\n0x42,0xF2,0x2E,0xE2,0x52,0x7F,0x4A,0xD2,0x7F,0x4A,0xD2,0x00,0x07,0x02,0x0B,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"礎\",376*/},{\n\n0x10,0xFC,0x03,0x55,0x56,0x54,0x80,0xD2,0x7F,0x5A,0xD4,0x00,0x0F,0x00,0x0F,0x05,\n0x0F,0x00,0x0F,0x05,0x05,0x0F,/*\"儲\",377*/},{\n\n0x40,0x42,0x7A,0xCA,0x4A,0x6F,0x4A,0xCA,0x7A,0x42,0x40,0x08,0x0F,0x09,0x09,0x0F,\n0x08,0x0F,0x09,0x09,0x0F,0x08,/*\"矗\",378*/},{\n\n0x88,0x88,0xFF,0x48,0xA2,0xAA,0xAE,0xBB,0xAA,0xA6,0xB2,0x00,0x08,0x0F,0x00,0x0F,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0F,/*\"搐\",379*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x20,0xD7,0x5D,0xF7,0x55,0xF7,0x07,0x01,0x07,0x09,0x0F,\n0x00,0x05,0x05,0x07,0x0D,0x0F,/*\"觸\",380*/},{\n\n0x00,0xFC,0x04,0xD4,0x94,0x9F,0x35,0xAD,0xA5,0xB5,0x0C,0x08,0x07,0x09,0x0A,0x04,\n0x0B,0x0C,0x0B,0x08,0x0B,0x0A,/*\"處\",381*/},{\n\n0x88,0xFF,0x48,0x00,0xAE,0xA8,0xA8,0xEF,0xA8,0xA8,0xAE,0x08,0x0F,0x00,0x00,0x0F,\n0x00,0x07,0x00,0x07,0x08,0x0F,/*\"揣\",382*/},{\n\n0x00,0x00,0xFF,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0xFF,0x08,0x04,0x03,0x00,0x00,\n0x00,0x07,0x00,0x00,0x00,0x0F,/*\"川\",383*/},{\n\n0x06,0xD2,0x9A,0x96,0x92,0x93,0x92,0xF6,0x9A,0x92,0x86,0x08,0x08,0x04,0x04,0x02,\n0x01,0x08,0x0F,0x00,0x00,0x00,/*\"穿\",384*/},{\n\n0x88,0x68,0xFF,0x48,0xA0,0xAC,0x6B,0xAA,0x3A,0xA6,0x60,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x05,0x0A,0x0F,0x02,0x04,/*\"椽\",385*/},{\n\n0x10,0xFC,0x83,0xFA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x82,0x00,0x0F,0x02,0x06,0x0A,\n0x02,0x02,0x0A,0x0F,0x02,0x02,/*\"傳\",386*/},{\n\n0x40,0xFC,0x56,0x65,0xFC,0x10,0xCE,0x42,0x42,0xCE,0x10,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"船\",387*/},{\n\n0xFE,0x02,0xFE,0x00,0xAE,0xA8,0xA8,0xEF,0xA8,0xA8,0xAE,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x07,0x00,0x07,0x08,0x0F,/*\"喘\",388*/},{\n\n0xC0,0x5E,0x52,0x52,0x52,0xFF,0x52,0x52,0x52,0x5E,0xC0,0x07,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x07,/*\"串\",389*/},{\n\n0x08,0x90,0xFE,0x12,0xEA,0xAA,0xB7,0xAA,0xAA,0xF2,0x12,0x09,0x04,0x0B,0x04,0x03,\n0x0E,0x0A,0x0A,0x0A,0x0B,0x0E,/*\"瘡\",390*/},{\n\n0x06,0xE2,0x2A,0xA6,0xF2,0xAB,0xA2,0xA6,0x2A,0xE2,0x06,0x00,0x0F,0x09,0x0D,0x0A,\n0x0A,0x0D,0x08,0x08,0x0F,0x00,/*\"窗\",391*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x08,0xFA,0xAE,0xFB,0xAE,0xFA,0x01,0x00,0x0F,0x01,0x01,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"幢\",392*/},{\n\n0x40,0xDE,0x50,0xFF,0x00,0x88,0x68,0xFF,0x68,0x88,0x08,0x08,0x07,0x00,0x0F,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"牀\",393*/},{\n\n0xFF,0x15,0x15,0xFF,0xA0,0xE0,0xA0,0xBF,0x15,0x15,0xFF,0x0F,0x00,0x08,0x03,0x0A,\n0x03,0x0A,0x0E,0x00,0x08,0x0F,/*\"闖\",394*/},{\n\n0x10,0x08,0xFC,0xAA,0xAD,0xAA,0xFC,0x08,0xFC,0x00,0xFF,0x04,0x03,0x0E,0x0A,0x0A,\n0x0A,0x0E,0x00,0x01,0x08,0x0F,/*\"創\",395*/},{\n\n0xFE,0x02,0x02,0xFE,0x20,0x18,0x07,0xE4,0x04,0x14,0x0C,0x03,0x01,0x01,0x03,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"吹\",396*/},{\n\n0x78,0x00,0xFF,0x08,0x24,0x18,0x07,0xE4,0x04,0x14,0x0C,0x08,0x06,0x01,0x06,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"炊\",397*/},{\n\n0x88,0xFF,0x48,0x00,0x48,0xFA,0x4A,0xFE,0x49,0xF9,0x48,0x08,0x0F,0x00,0x00,0x02,\n0x0B,0x0A,0x0F,0x0A,0x0B,0x02,/*\"捶\",398*/},{\n\n0x4A,0xF9,0x4A,0x00,0x48,0xFA,0x4A,0xFE,0x49,0xF9,0x48,0x0A,0x0F,0x05,0x00,0x02,\n0x0B,0x0A,0x0F,0x0A,0x0B,0x02,/*\"錘\",399*/},{\n\n0x40,0x4A,0xFA,0x4A,0x4A,0xFE,0x49,0x49,0xF9,0x49,0x40,0x00,0x02,0x0B,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0B,0x02,0x00,/*\"垂\",400*/},{\n\n0x20,0xA2,0xEA,0xBA,0xAE,0xAB,0xAA,0xAA,0xEA,0xA2,0x20,0x01,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x01,/*\"春\",401*/},{\n\n0x88,0x68,0xFF,0x48,0xA2,0xEA,0xBA,0xAF,0xAA,0xEA,0xA2,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"椿\",402*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x00,0xBA,0xAA,0xAB,0xAA,0x3A,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x02,0x0A,0x0E,0x03,0x02,/*\"醇\",403*/},{\n\n0x00,0xFF,0x05,0x85,0xBD,0xA5,0x8D,0x95,0xA5,0xD5,0x4D,0x08,0x07,0x00,0x0F,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"脣\",404*/},{\n\n0x22,0x44,0x00,0x02,0xBA,0xAA,0xAA,0xAB,0xAA,0xBA,0x02,0x04,0x02,0x01,0x02,0x02,\n0x02,0x0A,0x0E,0x03,0x02,0x02,/*\"淳\",405*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0xF4,0x84,0xFF,0x84,0xF4,0x04,0x0C,0x02,0x04,0x02,0x04,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"純\",406*/},{\n\n0xA8,0xAA,0xDA,0xFA,0xAE,0xAB,0xAA,0xFA,0xDA,0xAA,0xA8,0x0B,0x0A,0x0F,0x0A,0x0B,\n0x00,0x0B,0x0A,0x0F,0x0A,0x0B,/*\"蠢\",407*/},{\n\n0x2B,0xF5,0xAF,0xA0,0xEB,0xB5,0xAF,0x10,0xFF,0x88,0x6A,0x00,0x0F,0x0A,0x0A,0x0F,\n0x0A,0x0A,0x04,0x03,0x05,0x0E,/*\"戳\",408*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0xF8,0xA8,0xAF,0xAA,0xAA,0xFA,0x0C,0x02,0x04,0x02,0x04,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"綽\",409*/},{\n\n0x08,0x90,0xFC,0x04,0xC4,0x05,0xF6,0x84,0xF4,0x44,0x24,0x09,0x04,0x03,0x08,0x0F,\n0x08,0x07,0x04,0x07,0x08,0x0E,/*\"疵\",410*/},{\n\n0x0A,0x12,0x22,0x07,0x42,0x22,0x1A,0xD7,0x12,0x52,0x32,0x04,0x02,0x01,0x00,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"茨\",411*/},{\n\n0xF2,0x2E,0xE2,0x00,0xE8,0x99,0x4A,0x08,0xEC,0x9B,0x48,0x07,0x02,0x07,0x00,0x06,\n0x05,0x0E,0x00,0x06,0x05,0x0E,/*\"磁\",412*/},{\n\n0xF8,0x00,0xFF,0x20,0xFF,0x10,0xFC,0x27,0xFC,0x25,0x24,0x07,0x04,0x03,0x02,0x07,\n0x02,0x0F,0x09,0x0F,0x09,0x09,/*\"雌\",413*/},{\n\n0xCA,0x4E,0xDA,0x6E,0x59,0xCD,0x00,0x55,0xE6,0x54,0x44,0x0F,0x0B,0x05,0x0B,0x00,\n0x0F,0x00,0x01,0x0F,0x01,0x00,/*\"辭\",414*/},{\n\n0x04,0xB4,0xED,0xA6,0xD4,0x04,0xB4,0xEE,0xA5,0xD4,0x04,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"慈\",415*/},{\n\n0x50,0x51,0xCA,0x40,0x54,0x53,0x4A,0x46,0x4A,0x52,0x56,0x00,0x0C,0x0B,0x09,0x0B,\n0x05,0x01,0x07,0x08,0x08,0x0E,/*\"瓷\",416*/},{\n\n0x54,0x55,0x56,0x54,0x00,0xEA,0x2A,0x2A,0xEA,0x02,0xFE,0x0F,0x05,0x05,0x0F,0x00,\n0x03,0x01,0x01,0x09,0x08,0x07,/*\"詞\",417*/},{\n\n0x00,0xF8,0x00,0xFF,0x20,0x20,0x00,0xFF,0x20,0x10,0x0C,0x08,0x0F,0x08,0x07,0x04,\n0x04,0x00,0x07,0x08,0x08,0x0E,/*\"此\",418*/},{\n\n0xF4,0x14,0x14,0xFF,0x14,0x94,0xF4,0x00,0xFC,0x00,0xFF,0x04,0x02,0x01,0x0F,0x01,\n0x02,0x04,0x00,0x01,0x08,0x0F,/*\"刺\",419*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x80,0x5F,0xF5,0x55,0xD5,0x5F,0xC0,0x09,0x05,0x05,0x09,0x02,\n0x09,0x04,0x02,0x09,0x08,0x07,/*\"賜\",420*/},{\n\n0x02,0x04,0x80,0x20,0x18,0x87,0x74,0x84,0x04,0x14,0x0C,0x02,0x01,0x08,0x04,0x02,\n0x01,0x00,0x01,0x02,0x04,0x08,/*\"次\",421*/},{\n\n0x01,0xFF,0x49,0xFF,0x01,0xFE,0xD2,0xAF,0xDA,0x82,0xFE,0x02,0x03,0x02,0x0F,0x05,\n0x02,0x0D,0x0A,0x0C,0x02,0x04,/*\"聰\",422*/},{\n\n0x02,0xFA,0x4A,0xAF,0xFA,0xAE,0x6A,0x2F,0x0A,0xFA,0x02,0x08,0x05,0x01,0x05,0x0B,\n0x0D,0x09,0x0D,0x01,0x05,0x08,/*\"蔥\",423*/},{\n\n0x00,0xFE,0x42,0x2A,0x13,0xAA,0x46,0xA2,0x1A,0x02,0xFE,0x00,0x0F,0x04,0x06,0x05,\n0x04,0x04,0x04,0x05,0x04,0x0F,/*\"囪\",424*/},{\n\n0x20,0x18,0xA7,0x64,0x5C,0x44,0x84,0x7C,0x04,0x04,0xFC,0x02,0x01,0x00,0x08,0x04,\n0x02,0x01,0x09,0x0A,0x08,0x07,/*\"匆\",425*/},{\n\n0x48,0x24,0xF2,0x09,0x84,0x23,0x14,0xE8,0x87,0x88,0x90,0x00,0x00,0x0F,0x04,0x03,\n0x04,0x08,0x0F,0x08,0x08,0x08,/*\"從\",426*/},{\n\n0x44,0xD5,0x56,0x5C,0xD7,0x74,0x57,0x5C,0x56,0x55,0x44,0x04,0x07,0x05,0x05,0x0F,\n0x02,0x08,0x0B,0x05,0x0B,0x08,/*\"叢\",427*/},{\n\n0x22,0x44,0x20,0xA2,0x6A,0xBA,0xAF,0xAA,0x6A,0xA2,0x20,0x04,0x02,0x01,0x0A,0x0A,\n0x06,0x03,0x02,0x06,0x0A,0x01,/*\"湊\",428*/},{\n\n0x24,0xA8,0xFF,0xA8,0x24,0x00,0xFE,0x92,0x92,0xFE,0x00,0x01,0x00,0x0F,0x00,0x01,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"粗\",429*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x14,0xDF,0x54,0x54,0xDF,0x14,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x0F,0x05,0x05,0x0F,0x00,/*\"醋\",430*/},{\n\n0x24,0xEB,0xB2,0xA6,0x22,0x98,0x74,0xD3,0x52,0x56,0x12,0x08,0x07,0x08,0x0F,0x01,\n0x09,0x05,0x03,0x05,0x09,0x09,/*\"簇\",431*/},{\n\n0x10,0xFC,0x03,0x00,0xDF,0x11,0x11,0xF1,0x91,0x91,0x9F,0x00,0x0F,0x08,0x04,0x03,\n0x04,0x08,0x0F,0x08,0x08,0x08,/*\"促\",432*/},{\n\n0x9E,0x12,0xFE,0x40,0x06,0xEA,0x56,0x03,0x56,0xFA,0x06,0x07,0x04,0x03,0x02,0x00,\n0x0F,0x05,0x0F,0x05,0x07,0x08,/*\"躥\",433*/},{\n\n0x84,0xFB,0x8A,0x9E,0xAA,0xCC,0x9B,0xAA,0xCE,0xFA,0x82,0x04,0x02,0x09,0x0C,0x0A,\n0x08,0x08,0x0C,0x09,0x02,0x04,/*\"篡\",434*/},{\n\n0x06,0xFA,0xAE,0xAA,0xA6,0x83,0xAA,0xAA,0xAE,0xFA,0x06,0x00,0x0F,0x0A,0x00,0x00,\n0x0F,0x0A,0x00,0x03,0x04,0x0E,/*\"竄\",435*/},{\n\n0x88,0x88,0xFF,0x48,0x26,0xF4,0xAC,0xA7,0xEC,0xB4,0xA6,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"摧\",436*/},{\n\n0x40,0x26,0xF4,0xAC,0xA4,0xA7,0xEC,0xB4,0xA4,0xA6,0x20,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"崔\",437*/},{\n\n0x20,0x10,0xFC,0x43,0x26,0xF4,0xAC,0xA7,0xEC,0xB4,0xA6,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"催\",438*/},{\n\n0x00,0xFE,0x92,0xFE,0x08,0xF4,0x13,0xD2,0x5A,0x56,0xD0,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x00,0x07,0x08,0x09,0x0D,/*\"脆\",439*/},{\n\n0x08,0x90,0xFE,0x02,0x92,0x72,0x93,0x1A,0x92,0x72,0x92,0x09,0x04,0x03,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"瘁\",440*/},{\n\n0x24,0xA8,0xFF,0xA8,0x24,0x1C,0x25,0x86,0x24,0x1C,0x24,0x01,0x00,0x0F,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"粹\",441*/},{\n\n0x10,0x22,0x04,0x00,0x24,0x1C,0x25,0x86,0x24,0x1C,0x24,0x04,0x02,0x01,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"淬\",442*/},{\n\n0x01,0xAB,0x65,0xA1,0x2F,0x30,0x21,0xAB,0x65,0xA1,0x0F,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"翠\",443*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0x00,0x48,0x88,0x08,0xFF,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x09,0x08,0x0F,0x00,/*\"村\",444*/},{\n\n0x84,0x44,0xF4,0x0C,0x87,0x94,0x94,0xD4,0xB4,0x94,0x84,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x08,0x0F,0x00,0x00,0x00,/*\"存\",445*/},{\n\n0x08,0x08,0x48,0x88,0x08,0x08,0x08,0xFF,0x08,0x08,0x08,0x00,0x00,0x00,0x01,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"寸\",446*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x44,0xD5,0x76,0x5C,0x56,0x55,0x00,0x0F,0x04,0x0F,0x04,\n0x0A,0x09,0x09,0x0F,0x09,0x09,/*\"磋\",447*/},{\n\n0x88,0xFF,0x48,0x10,0xF0,0x5F,0xF5,0x15,0xD5,0x5F,0xD0,0x08,0x0F,0x00,0x04,0x07,\n0x05,0x0F,0x0A,0x05,0x02,0x0D,/*\"撮\",448*/},{\n\n0x88,0xFF,0x48,0x00,0x44,0xD5,0x76,0x5C,0x56,0x55,0x44,0x08,0x0F,0x00,0x04,0x0A,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"搓\",449*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0xD4,0x5F,0x54,0x54,0x5F,0xD4,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"措\",450*/},{\n\n0x88,0x88,0xFF,0x48,0x20,0x1C,0x20,0xFF,0x20,0x1C,0x20,0x00,0x08,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"挫\",451*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x10,0xD4,0x5F,0x54,0x5F,0xD4,0x10,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"錯\",452*/},{\n\n0x88,0x88,0xFF,0x48,0x42,0x27,0x52,0x4A,0x52,0x27,0x42,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"搭\",453*/},{\n\n0x10,0x11,0xF2,0x00,0x28,0xAA,0xBA,0xEF,0xBA,0xAA,0x28,0x08,0x04,0x03,0x04,0x0A,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"達\",454*/},{\n\n0x24,0x23,0x96,0xB2,0xAA,0xA4,0xAB,0xB2,0x96,0x22,0x22,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x0F,0x00,0x00,/*\"答\",455*/},{\n\n0x08,0x90,0xFE,0x8A,0x5E,0xAA,0x9B,0xAA,0x5E,0x8A,0x8A,0x09,0x04,0x03,0x0E,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"瘩\",456*/},{\n\n0x88,0x88,0xFF,0x48,0x48,0x02,0x02,0x02,0xFE,0x02,0x02,0x00,0x08,0x0F,0x00,0x00,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"打\",457*/},{\n\n0x10,0x10,0x10,0x10,0xD0,0x3F,0xD0,0x10,0x10,0x10,0x10,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x03,0x04,0x08,0x08,/*\"大\",458*/},{\n\n0x40,0x4F,0x49,0x49,0xC9,0xF9,0xC9,0x49,0x49,0x4F,0x40,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"呆\",459*/},{\n\n0x82,0x42,0x22,0x5A,0x96,0x12,0x12,0x12,0xD2,0x32,0x02,0x08,0x08,0x08,0x04,0x05,\n0x02,0x02,0x01,0x00,0x00,0x00,/*\"歹\",460*/},{\n\n0x10,0xFC,0x23,0xAA,0x6A,0x3A,0xAF,0x2A,0x6A,0xAA,0x20,0x00,0x0F,0x01,0x08,0x05,\n0x0A,0x0F,0x02,0x05,0x08,0x01,/*\"傣\",461*/},{\n\n0x08,0xFA,0xAA,0xFF,0xAA,0xFA,0x08,0xFF,0x08,0xE9,0x0A,0x02,0x0A,0x07,0x02,0x07,\n0x0A,0x0A,0x04,0x03,0x04,0x0E,/*\"戴\",462*/},{\n\n0x62,0x2A,0x27,0x22,0x2F,0xAA,0x2F,0x22,0x27,0x2A,0x6A,0x00,0x07,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x05,0x07,0x00,/*\"帶\",463*/},{\n\n0x82,0x62,0x9E,0x12,0xF2,0x00,0xD0,0x5C,0x53,0x50,0xD8,0x08,0x04,0x02,0x01,0x00,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"殆\",464*/},{\n\n0x20,0x10,0xFC,0x03,0x10,0x10,0xFF,0x10,0x09,0x0A,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x01,0x02,0x04,0x0F,/*\"代\",465*/},{\n\n0x08,0xE4,0xBE,0xA1,0xA8,0xA8,0xAF,0xA8,0xB5,0xE6,0x34,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"貸\",466*/},{\n\n0x88,0x84,0xBE,0x81,0x88,0xC8,0x8F,0x88,0x95,0xA6,0xB4,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"袋\",467*/},{\n\n0x48,0x24,0xF2,0x09,0x50,0x54,0x54,0x5F,0xF4,0x54,0x50,0x00,0x00,0x0F,0x00,0x00,\n0x01,0x0A,0x08,0x0F,0x00,0x00,/*\"待\",468*/},{\n\n0x11,0xF2,0x08,0xAA,0x2A,0xAA,0xFF,0xAA,0x2A,0xBE,0x08,0x08,0x07,0x08,0x0A,0x09,\n0x0A,0x0B,0x08,0x09,0x0A,0x08,/*\"逮\",469*/},{\n\n0x04,0x76,0x55,0x54,0x54,0x54,0x54,0x54,0x54,0x76,0x0C,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"怠\",470*/},{\n\n0x02,0xFE,0x52,0xFE,0x02,0x1C,0xC4,0x3F,0xC4,0x04,0x1C,0x02,0x03,0x02,0x0F,0x09,\n0x06,0x01,0x00,0x07,0x08,0x0C,/*\"耽\",471*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x15,0xAD,0xB5,0xA7,0xAC,0x14,0x08,0x0F,0x00,0x08,0x07,\n0x00,0x0E,0x0A,0x0A,0x0E,0x00,/*\"擔\",472*/},{\n\n0x40,0x40,0xFE,0x42,0x42,0x4A,0x52,0x42,0x42,0xFE,0x40,0x08,0x06,0x01,0x00,0x00,\n0x00,0x00,0x08,0x08,0x0F,0x00,/*\"丹\",473*/},{\n\n0x00,0xF7,0x55,0x55,0x57,0xF0,0x57,0x55,0x55,0xF7,0x00,0x04,0x05,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x05,0x04,/*\"單\",474*/},{\n\n0xF7,0x55,0x57,0xF0,0x57,0x55,0xF7,0x00,0xFF,0x31,0xCF,0x05,0x05,0x05,0x0F,0x05,\n0x05,0x05,0x00,0x0F,0x02,0x01,/*\"鄲\",475*/},{\n\n0x88,0xFF,0x48,0x00,0xF7,0x55,0x57,0xF0,0x57,0x55,0xF7,0x08,0x0F,0x00,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"撣\",476*/},{\n\n0x00,0xFF,0x49,0xFF,0x00,0xFE,0x15,0xAD,0xB7,0xAC,0x14,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x00,0x0E,0x0A,0x0E,0x00,/*\"膽\",477*/},{\n\n0x00,0x00,0xFE,0x22,0x22,0x22,0x22,0x22,0x22,0xFE,0x00,0x00,0x08,0x0B,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"旦\",478*/},{\n\n0x04,0x52,0x35,0x95,0x75,0x55,0xB5,0x15,0xF5,0x01,0x00,0x00,0x09,0x0B,0x04,0x03,\n0x04,0x0A,0x00,0x03,0x04,0x0E,/*\"氮\",479*/},{\n\n0x10,0xFC,0x03,0x00,0xFE,0x12,0x12,0x12,0x12,0xFE,0x00,0x00,0x0F,0x00,0x08,0x09,\n0x09,0x09,0x09,0x09,0x09,0x08,/*\"但\",480*/},{\n\n0x78,0x00,0xFF,0x08,0xF7,0x55,0x57,0xF0,0x57,0x55,0xF7,0x00,0x00,0x0F,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"憚\",481*/},{\n\n0x10,0x22,0x04,0x00,0x28,0xA6,0x10,0xCF,0x10,0x14,0xA2,0x04,0x02,0x01,0x08,0x09,\n0x04,0x02,0x01,0x02,0x05,0x08,/*\"淡\",482*/},{\n\n0x55,0x56,0x54,0x00,0x32,0xCE,0x00,0xF2,0x02,0xFF,0x11,0x0F,0x05,0x0F,0x00,0x0A,\n0x07,0x08,0x09,0x09,0x09,0x09,/*\"誕\",483*/},{\n\n0x79,0x49,0xCF,0x00,0xF7,0x55,0x57,0xF0,0x57,0x55,0xF7,0x08,0x08,0x07,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"彈\",484*/},{\n\n0x21,0x91,0x8D,0x91,0xA1,0xFF,0xA9,0xA9,0xA9,0xA9,0x23,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蛋\",485*/},{\n\n0x06,0x82,0xBB,0xAA,0xAA,0xAB,0xAA,0xAA,0xBB,0x82,0x06,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"當\",486*/},{\n\n0x88,0xFF,0x48,0x00,0x86,0xBB,0xAA,0xAB,0xAA,0xBB,0x86,0x08,0x0F,0x00,0x00,0x0F,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0F,/*\"擋\",487*/},{\n\n0x06,0xE2,0x3B,0xAA,0x2A,0xEB,0x2A,0xAA,0x3B,0xE2,0x06,0x04,0x0D,0x05,0x05,0x0D,\n0x07,0x0D,0x05,0x05,0x0D,0x04,/*\"黨\",488*/},{\n\n0x42,0x8A,0x12,0x87,0xFA,0xAA,0xAA,0xAF,0xAA,0xFA,0x82,0x08,0x04,0x02,0x04,0x02,\n0x0B,0x06,0x0A,0x06,0x0A,0x0E,/*\"蕩\",489*/},{\n\n0x88,0x68,0xFF,0x48,0x86,0xBB,0xAA,0xAB,0xAA,0xBB,0x86,0x00,0x00,0x0F,0x00,0x0F,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0F,/*\"檔\",490*/},{\n\n0x00,0x02,0x02,0xC2,0x3E,0x02,0x02,0x02,0x02,0x02,0xFE,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x08,0x08,0x08,0x07,/*\"刀\",491*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xFE,0xAA,0xAB,0xAA,0xBE,0xA0,0x00,0x08,0x0F,0x00,0x06,\n0x04,0x07,0x04,0x06,0x08,0x0F,/*\"搗\",492*/},{\n\n0x9E,0x12,0xF2,0x9E,0x00,0xCA,0x52,0x26,0x09,0x51,0xCD,0x0F,0x08,0x07,0x04,0x00,\n0x0F,0x05,0x04,0x04,0x05,0x0F,/*\"蹈\",493*/},{\n\n0x10,0xFC,0x03,0x9A,0xF6,0x92,0xBA,0x00,0xFC,0x00,0xFF,0x00,0x0F,0x00,0x04,0x07,\n0x02,0x02,0x00,0x01,0x08,0x0F,/*\"倒\",494*/},{\n\n0x00,0x00,0xFE,0xAA,0xAB,0xAA,0xAA,0xAA,0xBE,0xA0,0xA0,0x00,0x06,0x04,0x04,0x07,\n0x04,0x04,0x06,0x08,0x08,0x07,/*\"島\",495*/},{\n\n0x84,0x45,0xF6,0x4C,0xA2,0xAA,0xAA,0xEF,0xAA,0xAA,0x6A,0x00,0x00,0x0F,0x00,0x0E,\n0x0A,0x0E,0x02,0x0A,0x0F,0x02,/*\"禱\",496*/},{\n\n0x89,0x7A,0x80,0x82,0xFA,0xAB,0xAE,0xAA,0xAB,0xFA,0x82,0x02,0x02,0x06,0x0A,0x02,\n0x02,0x02,0x0A,0x0F,0x02,0x02,/*\"導\",497*/},{\n\n0x92,0x9A,0x96,0xF2,0x92,0x9A,0xB2,0x00,0xFC,0x00,0xFF,0x08,0x08,0x08,0x07,0x04,\n0x04,0x04,0x00,0x01,0x08,0x0F,/*\"到\",498*/},{\n\n0x12,0xD2,0xFE,0x91,0x00,0xCA,0x52,0x26,0x09,0x51,0xCD,0x01,0x00,0x0F,0x00,0x00,\n0x0F,0x05,0x04,0x04,0x05,0x0F,/*\"稻\",499*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0xF8,0xA8,0xAF,0xAA,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"悼\",500*/},{\n\n0x10,0x11,0xF2,0x00,0xFA,0xAB,0xAE,0xAA,0xAA,0xAB,0xFA,0x08,0x04,0x03,0x04,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0A,0x0B,/*\"道\",501*/},{\n\n0x84,0x49,0x22,0x88,0x44,0x23,0x1A,0x22,0x42,0x8A,0x86,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盜\",502*/},{\n\n0x24,0xF2,0x09,0x80,0xBA,0xAA,0xBA,0xAF,0xBA,0xAA,0xBA,0x00,0x0F,0x00,0x08,0x06,\n0x00,0x06,0x09,0x0C,0x02,0x0C,/*\"德\",503*/},{\n\n0x24,0xF2,0x09,0x00,0x5F,0x55,0x55,0x55,0xD5,0x5F,0x00,0x00,0x0F,0x00,0x01,0x03,\n0x05,0x01,0x09,0x0F,0x01,0x01,/*\"得\",504*/},{\n\n0xFC,0x46,0x45,0x44,0xFC,0x10,0x08,0x27,0xC4,0x04,0xFC,0x0F,0x04,0x04,0x04,0x0F,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"的\",505*/},{\n\n0x9E,0x12,0xF2,0x9E,0x25,0xD9,0x57,0x50,0x57,0xDA,0x25,0x0F,0x08,0x07,0x04,0x08,\n0x0B,0x0D,0x09,0x0D,0x0B,0x08,/*\"蹬\",506*/},{\n\n0x78,0x00,0xFF,0x08,0x25,0xD9,0x57,0x50,0x57,0xDA,0x25,0x08,0x06,0x01,0x06,0x08,\n0x0B,0x0D,0x09,0x0D,0x0B,0x08,/*\"燈\",507*/},{\n\n0x44,0x29,0xD1,0x4D,0x53,0x50,0x53,0x4C,0xD2,0x29,0x44,0x08,0x08,0x09,0x0B,0x0D,\n0x09,0x0D,0x0B,0x09,0x08,0x08,/*\"登\",508*/},{\n\n0x44,0x53,0x52,0x56,0x52,0x7C,0x53,0xD2,0x56,0x52,0x42,0x01,0x01,0x03,0x05,0x01,\n0x09,0x09,0x0F,0x01,0x01,0x01,/*\"等\",509*/},{\n\n0xFE,0x92,0xFE,0x20,0xD5,0x49,0x57,0x50,0x4F,0xD2,0x29,0x0F,0x04,0x0F,0x08,0x0B,\n0x0D,0x09,0x09,0x0D,0x0B,0x08,/*\"瞪\",510*/},{\n\n0x95,0x89,0xBD,0xEB,0xAA,0xAA,0xAA,0xEB,0xBE,0x89,0x94,0x08,0x08,0x06,0x02,0x02,\n0x02,0x02,0x06,0x08,0x08,0x0C,/*\"凳\",511*/},{\n\n0x12,0xED,0xAB,0xA8,0xA9,0xEE,0x05,0xFE,0x02,0x32,0xCE,0x08,0x09,0x0A,0x04,0x06,\n0x05,0x00,0x0F,0x02,0x02,0x01,/*\"鄧\",512*/},{\n\n0x10,0x10,0xFF,0x10,0x40,0x5F,0x55,0xD5,0x55,0x5F,0x40,0x04,0x04,0x03,0x02,0x08,\n0x07,0x08,0x0F,0x09,0x09,0x08,/*\"堤\",513*/},{\n\n0x20,0x10,0xFC,0x03,0xFE,0x22,0x22,0xFE,0x21,0x21,0x20,0x00,0x00,0x0F,0x00,0x07,\n0x02,0x05,0x08,0x03,0x04,0x0F,/*\"低\",514*/},{\n\n0x22,0x44,0xF2,0x16,0x5A,0x52,0xF3,0x52,0x5A,0x16,0xF2,0x04,0x02,0x0F,0x00,0x07,\n0x05,0x05,0x05,0x07,0x08,0x0F,/*\"滴\",515*/},{\n\n0x10,0x11,0xF2,0x00,0xFC,0x24,0x24,0xFF,0x24,0x24,0xFC,0x08,0x04,0x03,0x04,0x09,\n0x09,0x09,0x09,0x09,0x09,0x09,/*\"迪\",516*/},{\n\n0xF2,0x16,0x5A,0xF3,0x5A,0x16,0xF2,0x10,0xEF,0x08,0xF8,0x0F,0x00,0x07,0x05,0x07,\n0x08,0x0F,0x08,0x04,0x03,0x0C,/*\"敵\",517*/},{\n\n0x04,0xE3,0x26,0x2A,0x22,0xF8,0x24,0x23,0x26,0xEA,0x02,0x00,0x0F,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x0F,0x00,/*\"笛\",518*/},{\n\n0x10,0x8A,0x44,0xFB,0x20,0x1C,0x80,0x7F,0x80,0x10,0x0C,0x01,0x08,0x08,0x07,0x08,\n0x06,0x01,0x00,0x01,0x06,0x08,/*\"狄\",519*/},{\n\n0x22,0x44,0x10,0xFC,0x03,0xF8,0xA4,0x97,0xEA,0x96,0xA0,0x04,0x02,0x00,0x0F,0x00,\n0x03,0x04,0x0A,0x0F,0x02,0x04,/*\"滌\",520*/},{\n\n0x81,0x4B,0xE5,0xB1,0xAF,0xA0,0xF1,0xAB,0xA5,0xA1,0x2F,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"翟\",521*/},{\n\n0xF8,0x0F,0xF8,0x00,0xF2,0x16,0x5A,0xF3,0x5A,0x16,0xF2,0x0D,0x02,0x05,0x00,0x0F,\n0x00,0x07,0x05,0x07,0x08,0x0F,/*\"嫡\",522*/},{\n\n0x88,0x88,0xFF,0x48,0xFE,0x22,0x22,0xFE,0x21,0x21,0x20,0x00,0x08,0x0F,0x00,0x07,\n0x02,0x05,0x08,0x03,0x04,0x0F,/*\"抵\",523*/},{\n\n0x00,0xFE,0x02,0xF2,0x92,0x92,0x93,0xFA,0x8A,0x8A,0x82,0x08,0x07,0x00,0x0F,0x04,\n0x02,0x04,0x09,0x02,0x04,0x0E,/*\"底\",524*/},{\n\n0x10,0x10,0xFF,0x10,0x20,0xFC,0x10,0xFF,0x08,0x84,0xFC,0x04,0x04,0x03,0x02,0x00,\n0x07,0x08,0x09,0x08,0x08,0x0E,/*\"地\",525*/},{\n\n0xC2,0x52,0x52,0x77,0x52,0xDA,0x52,0x77,0x52,0x52,0xC2,0x00,0x07,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x05,0x07,0x00,/*\"蒂\",526*/},{\n\n0x04,0xD3,0x52,0x56,0x52,0xF4,0x53,0x52,0x56,0x72,0x02,0x08,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x01,0x09,0x09,0x07,/*\"第\",527*/},{\n\n0x32,0x92,0x96,0x9A,0x92,0xD3,0x92,0x9A,0x96,0x92,0x32,0x00,0x07,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x04,0x07,0x00,/*\"帝\",528*/},{\n\n0x00,0x74,0x55,0x56,0xD4,0xFC,0x54,0x56,0x55,0x5C,0xC0,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x00,0x02,0x02,0x01,/*\"弟\",529*/},{\n\n0x11,0xF2,0x00,0xFE,0x02,0xF2,0x52,0x7E,0xB5,0xD5,0x31,0x08,0x07,0x0A,0x09,0x0A,\n0x0D,0x0B,0x09,0x0B,0x0C,0x0E,/*\"遞\",530*/},{\n\n0xD8,0xB4,0x93,0xC8,0x32,0xD6,0x5A,0xF3,0x5A,0xD6,0x32,0x0C,0x02,0x04,0x02,0x04,\n0x03,0x00,0x0F,0x02,0x03,0x00,/*\"締\",531*/},{\n\n0x00,0xFA,0xAA,0xAF,0xAA,0xFA,0x00,0xFA,0xAE,0xAA,0xFA,0x02,0x0B,0x06,0x02,0x06,\n0x0B,0x02,0x0B,0x06,0x06,0x0B,/*\"顛\",532*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xFC,0x04,0x05,0xFE,0x24,0x24,0x00,0x08,0x0F,0x04,0x03,\n0x00,0x0F,0x09,0x09,0x09,0x0F,/*\"掂\",533*/},{\n\n0x22,0x44,0x00,0x02,0xFA,0xAA,0xAF,0xAA,0xAA,0xFA,0x02,0x04,0x02,0x01,0x02,0x0B,\n0x06,0x02,0x02,0x06,0x0B,0x02,/*\"滇\",534*/},{\n\n0xF2,0x2E,0xE2,0x00,0xFC,0x24,0xFF,0x24,0xFF,0x24,0xFC,0x07,0x02,0x07,0x01,0x09,\n0x05,0x01,0x01,0x01,0x05,0x09,/*\"碘\",535*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x00,0xC0,0x40,0x7F,0x48,0xC8,0x0A,0x02,0x0D,0x01,0x0D,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"點\",536*/},{\n\n0x00,0xFC,0x24,0x24,0xFF,0x24,0xFF,0x24,0x24,0xFC,0x00,0x01,0x09,0x05,0x03,0x01,\n0x01,0x01,0x03,0x05,0x09,0x01,/*\"典\",537*/},{\n\n0x22,0xEA,0xBF,0xEA,0x22,0x0C,0xA4,0x25,0xE6,0x24,0x2C,0x00,0x0F,0x02,0x0F,0x08,\n0x04,0x03,0x04,0x0F,0x09,0x09,/*\"靛\",538*/},{\n\n0xA8,0xBA,0xEF,0xBA,0xA8,0x00,0x94,0x7F,0x24,0xFC,0x80,0x08,0x0A,0x0B,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x09,/*\"墊\",539*/},{\n\n0x0C,0xE5,0xAD,0xA5,0xA5,0xEF,0xA5,0xA5,0xAD,0xE5,0x0C,0x00,0x07,0x02,0x02,0x02,\n0x07,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"電\",540*/},{\n\n0x20,0x10,0xFC,0x03,0xFE,0x22,0x22,0xFE,0x22,0x22,0xFE,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"佃\",541*/},{\n\n0x08,0xFC,0x4B,0x4A,0xFA,0x4A,0x4A,0xFA,0x02,0x02,0xFE,0x00,0x07,0x02,0x02,0x03,\n0x02,0x02,0x0B,0x08,0x08,0x07,/*\"甸\",542*/},{\n\n0x00,0xFC,0x04,0x04,0x04,0x05,0xFE,0x24,0x24,0x24,0x24,0x08,0x07,0x00,0x0F,0x09,\n0x09,0x09,0x09,0x09,0x09,0x0F,/*\"店\",543*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0xFC,0x04,0x05,0xFE,0x24,0x24,0x00,0x00,0x0F,0x04,0x03,\n0x00,0x0F,0x09,0x09,0x09,0x0F,/*\"惦\",544*/},{\n\n0x02,0xFA,0xAB,0x9E,0xAA,0xAA,0xAA,0x9E,0xAB,0xFA,0x02,0x0A,0x0A,0x0A,0x06,0x02,\n0x03,0x02,0x06,0x0A,0x0A,0x0A,/*\"奠\",545*/},{\n\n0x22,0x44,0xFE,0x4A,0xEA,0x4A,0xEE,0x50,0xCE,0x42,0xDE,0x04,0x0A,0x07,0x09,0x05,\n0x01,0x05,0x09,0x05,0x02,0x0D,/*\"澱\",546*/},{\n\n0x00,0xFE,0x4A,0xEA,0x4A,0xEE,0x50,0xCE,0x42,0xDE,0x10,0x08,0x07,0x09,0x05,0x01,\n0x05,0x09,0x05,0x02,0x05,0x08,/*\"殿\",547*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFF,0xA9,0xBD,0xA9,0x21,0xFF,0x00,0x07,0x02,0x0B,0x06,\n0x01,0x03,0x02,0x0B,0x08,0x0F,/*\"碉\",548*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0x82,0x42,0x22,0x12,0x02,0xFE,0x03,0x01,0x01,0x03,0x01,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"叼\",549*/},{\n\n0xFF,0xA9,0xBD,0xA9,0x01,0xFF,0x10,0xFC,0x27,0xFC,0x25,0x07,0x03,0x02,0x0B,0x08,\n0x0F,0x00,0x0F,0x09,0x0F,0x09,/*\"雕\",550*/},{\n\n0x04,0x08,0x00,0xFF,0x21,0xA9,0xBD,0xA9,0xA9,0x21,0xFF,0x02,0x09,0x04,0x03,0x00,\n0x03,0x02,0x02,0x0B,0x08,0x0F,/*\"凋\",551*/},{\n\n0x00,0x02,0x82,0x82,0x42,0x42,0x22,0x12,0x02,0xFE,0x00,0x01,0x01,0x00,0x00,0x00,\n0x00,0x08,0x08,0x08,0x07,0x00,/*\"刁\",552*/},{\n\n0x84,0x84,0xFF,0x44,0xF8,0xA8,0xA8,0xAF,0xAA,0xAA,0xFA,0x00,0x08,0x0F,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"掉\",553*/},{\n\n0xC0,0x4F,0x49,0x49,0x49,0xF9,0x49,0x49,0x49,0x4F,0xC0,0x07,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x04,0x07,/*\"吊\",554*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xB4,0x08,0x27,0xC4,0x04,0x04,0xFC,0x08,0x09,0x07,0x05,0x04,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"釣\",555*/},{\n\n0x55,0x56,0x54,0x00,0xFF,0x21,0xA9,0xBD,0xA9,0x21,0xFF,0x0F,0x05,0x07,0x08,0x07,\n0x00,0x03,0x02,0x0B,0x08,0x0F,/*\"調\",556*/},{\n\n0x9E,0x12,0xF2,0x9E,0x50,0x4C,0x48,0xFF,0x48,0x48,0x40,0x0F,0x08,0x07,0x04,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"跌\",557*/},{\n\n0x10,0x52,0x29,0xEA,0x94,0x54,0x34,0x8A,0x49,0x12,0x10,0x00,0x09,0x09,0x0A,0x0A,\n0x0F,0x09,0x05,0x05,0x03,0x00,/*\"爹\",558*/},{\n\n0x42,0xF2,0x2E,0xE2,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x00,0x07,0x02,0x07,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"碟\",559*/},{\n\n0x78,0x48,0xFF,0x48,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x04,0x04,0x03,0x02,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"蝶\",560*/},{\n\n0x10,0x11,0xF2,0x00,0x28,0x26,0xA4,0x7F,0xA4,0x24,0x20,0x08,0x04,0x03,0x04,0x0A,\n0x09,0x08,0x08,0x08,0x09,0x0A,/*\"迭\",561*/},{\n\n0x55,0x56,0x54,0x00,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x0F,0x05,0x0F,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"諜\",562*/},{\n\n0xC0,0x7C,0x57,0x7D,0x55,0x7F,0x55,0x7D,0x57,0x7C,0xC0,0x08,0x08,0x0F,0x0B,0x0D,\n0x09,0x0B,0x0D,0x0F,0x08,0x08,/*\"疊\",563*/},{\n\n0x02,0x02,0x02,0x02,0x02,0xFE,0x02,0x02,0x02,0x02,0x02,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"丁\",564*/},{\n\n0xFE,0x92,0x92,0xFE,0x00,0x02,0x02,0x02,0xFE,0x02,0x02,0x0F,0x04,0x04,0x0F,0x00,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"盯\",565*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0x02,0x02,0x02,0xFE,0x02,0x02,0x03,0x01,0x01,0x03,0x00,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"叮\",566*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x02,0x02,0x02,0xFE,0x02,0x02,0x08,0x09,0x07,0x05,0x04,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"釘\",567*/},{\n\n0x02,0x02,0xFE,0x02,0x00,0xFA,0xAA,0xAE,0xAA,0xAA,0xFA,0x00,0x08,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"頂\",568*/},{\n\n0x78,0x40,0x7F,0x55,0xD5,0x55,0xD5,0x55,0x7F,0x40,0x78,0x09,0x07,0x01,0x01,0x0F,\n0x00,0x0F,0x01,0x01,0x01,0x0F,/*\"鼎\",569*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xAC,0x24,0xE5,0x26,0x24,0x2C,0x08,0x09,0x07,0x0C,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"錠\",570*/},{\n\n0x2C,0x24,0xA4,0x24,0x25,0xE6,0x24,0x24,0x24,0x24,0x2C,0x08,0x04,0x03,0x04,0x08,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"定\",571*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0x02,0x02,0xFE,0x02,0x02,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"訂\",572*/},{\n\n0x40,0x49,0x49,0x49,0xC9,0x7F,0x49,0x49,0x49,0x49,0x40,0x00,0x04,0x06,0x05,0x04,\n0x04,0x04,0x05,0x06,0x0C,0x00,/*\"丟\",573*/},{\n\n0x02,0xFA,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xFA,0x02,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"東\",574*/},{\n\n0x90,0x88,0x84,0x4B,0x52,0x22,0x52,0x4A,0x86,0x80,0x80,0x00,0x00,0x00,0x04,0x05,\n0x05,0x0A,0x0A,0x08,0x00,0x00,/*\"冬\",575*/},{\n\n0x22,0x2A,0xEA,0xAF,0xAA,0xFA,0xAA,0xAF,0xEA,0x2A,0x22,0x08,0x0A,0x0B,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0B,0x0A,0x08,/*\"董\",576*/},{\n\n0x78,0x00,0xFF,0x08,0x12,0xEA,0xAF,0xFA,0xAF,0xEA,0x0A,0x00,0x00,0x0F,0x00,0x0A,\n0x0B,0x0A,0x0F,0x0A,0x0B,0x0A,/*\"懂\",577*/},{\n\n0x08,0xFA,0xAA,0xFE,0xA9,0xF9,0x08,0x04,0xFF,0x04,0xFC,0x08,0x0A,0x0A,0x0F,0x0A,\n0x0A,0x08,0x04,0x03,0x08,0x0F,/*\"動\",578*/},{\n\n0x88,0x68,0xFF,0x48,0xFA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"棟\",579*/},{\n\n0x20,0x10,0xFC,0x03,0xFE,0x02,0xEA,0x2A,0xEA,0x02,0xFE,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"侗\",580*/},{\n\n0x78,0x00,0xFF,0x08,0xFE,0x02,0xEA,0x2A,0xEA,0x02,0xFE,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"恫\",581*/},{\n\n0x04,0x08,0x02,0xFA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x02,0x02,0x01,0x04,0x02,0x01,\n0x00,0x0F,0x00,0x01,0x02,0x04,/*\"凍\",582*/},{\n\n0x22,0x44,0x00,0xFE,0x02,0xEA,0x2A,0x2A,0xEA,0x02,0xFE,0x04,0x02,0x00,0x0F,0x00,\n0x01,0x01,0x01,0x01,0x08,0x0F,/*\"洞\",583*/},{\n\n0x7C,0x42,0x00,0x7C,0x56,0x55,0x54,0x7C,0x00,0x42,0x7E,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"兜\",584*/},{\n\n0x88,0x88,0xFF,0x48,0x08,0x00,0x12,0x24,0x00,0xFF,0x80,0x00,0x08,0x0F,0x00,0x00,\n0x01,0x01,0x01,0x01,0x0F,0x00,/*\"抖\",585*/},{\n\n0xFF,0x00,0x15,0x1F,0x15,0x00,0x15,0x1F,0x15,0x00,0xFF,0x0F,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x08,0x0F,/*\"鬥\",586*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0xA4,0x24,0xFF,0x24,0x24,0x20,0x0F,0x02,0x02,0x09,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"陡\",587*/},{\n\n0x02,0x7A,0x4A,0x4A,0x4A,0x4A,0x4A,0x4A,0x4A,0x7A,0x02,0x08,0x09,0x0A,0x0C,0x08,\n0x08,0x08,0x0C,0x0A,0x09,0x08,/*\"豆\",588*/},{\n\n0x10,0x11,0xF2,0x00,0x02,0xBA,0x2A,0x2A,0x2A,0xBA,0x02,0x08,0x04,0x03,0x04,0x0A,\n0x0A,0x0B,0x0A,0x0B,0x0A,0x0A,/*\"逗\",589*/},{\n\n0x08,0x90,0xFE,0x0A,0xEA,0xAA,0xAB,0xAA,0xAA,0xEA,0x0A,0x09,0x04,0x03,0x08,0x0A,\n0x0C,0x08,0x08,0x0C,0x0A,0x08,/*\"痘\",590*/},{\n\n0x90,0xD4,0x7F,0x54,0x58,0xD6,0x00,0xFE,0x02,0x32,0xCE,0x00,0x0F,0x05,0x05,0x05,\n0x0F,0x00,0x0F,0x02,0x02,0x01,/*\"都\",591*/},{\n\n0x28,0x18,0xE8,0xBF,0xAA,0xBA,0xA8,0xB7,0xE9,0x17,0x20,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"督\",592*/},{\n\n0xA2,0xAA,0xEA,0xAA,0xEA,0xBF,0xAA,0xAA,0xEA,0xAA,0xA2,0x00,0x03,0x02,0x02,0x02,\n0x0B,0x0A,0x0A,0x07,0x02,0x00,/*\"毒\",593*/},{\n\n0x9C,0x88,0xFF,0x48,0x3A,0xEA,0xBA,0xAF,0xBA,0xEA,0x3A,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"犢\",594*/},{\n\n0x8A,0x44,0xFB,0x20,0xD7,0x5D,0xF7,0x55,0xD7,0x15,0xF7,0x08,0x08,0x07,0x00,0x05,\n0x05,0x07,0x05,0x0D,0x08,0x07,/*\"獨\",595*/},{\n\n0x55,0x56,0x54,0x00,0x3A,0xEA,0xBA,0xAF,0xBA,0xEA,0x3A,0x0F,0x05,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"讀\",596*/},{\n\n0x08,0x08,0xFF,0x08,0x90,0xD4,0x7F,0x54,0x58,0xD4,0x12,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"堵\",597*/},{\n\n0xFE,0x92,0x92,0xFE,0x90,0xD4,0x7F,0x54,0x58,0xD4,0x12,0x0F,0x04,0x04,0x0F,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"睹\",598*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x10,0x90,0xD4,0x7F,0x54,0x58,0xD4,0x09,0x05,0x05,0x09,0x01,\n0x00,0x0F,0x05,0x05,0x05,0x0F,/*\"賭\",599*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0x10,0x10,0xFF,0x10,0x10,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"杜\",600*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xFE,0x8A,0xBE,0xAB,0xBE,0x8A,0x08,0x09,0x07,0x04,0x08,\n0x07,0x08,0x0B,0x04,0x0A,0x09,/*\"鍍\",601*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0x10,0x10,0xFF,0x10,0x10,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x08,0x08,0x0F,0x08,0x08,/*\"肚\",602*/},{\n\n0x00,0xFE,0x0A,0x8A,0xBE,0xAA,0xAB,0xAA,0xBE,0x8A,0x0A,0x08,0x07,0x00,0x08,0x09,\n0x0A,0x04,0x04,0x0A,0x09,0x08,/*\"度\",603*/},{\n\n0x22,0x44,0x00,0xFE,0x8A,0xBE,0xAA,0xAB,0xAA,0xBE,0x0A,0x04,0x02,0x08,0x07,0x08,\n0x0B,0x04,0x04,0x0A,0x09,0x08,/*\"渡\",604*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFC,0x44,0x45,0x46,0x44,0xFC,0x08,0x05,0x02,0x05,0x08,\n0x07,0x00,0x00,0x00,0x00,0x00,/*\"妒\",605*/},{\n\n0xE9,0x0A,0xE8,0x00,0xAE,0xA8,0xA8,0xEF,0xA8,0xA8,0xAE,0x04,0x05,0x02,0x00,0x0F,\n0x00,0x07,0x00,0x07,0x08,0x0F,/*\"端\",606*/},{\n\n0x48,0x47,0xFC,0x44,0x02,0x7A,0x4A,0x4A,0x4A,0x7A,0x02,0x08,0x06,0x01,0x06,0x08,\n0x09,0x0A,0x08,0x0A,0x09,0x08,/*\"短\",607*/},{\n\n0x2A,0xF9,0xAA,0x00,0xFE,0x25,0x08,0xE7,0x21,0xEF,0x08,0x05,0x07,0x02,0x02,0x0F,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"鍛\",608*/},{\n\n0x00,0xFE,0x2A,0xA9,0x00,0x28,0xE7,0x21,0x21,0xEF,0x08,0x02,0x0F,0x01,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"段\",609*/},{\n\n0xFF,0x5A,0xB5,0x10,0x5A,0xB5,0x5A,0x00,0xFE,0x12,0xF1,0x0F,0x0B,0x0A,0x08,0x0B,\n0x0A,0x0B,0x08,0x07,0x00,0x0F,/*\"斷\",610*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFE,0x25,0x08,0xE7,0x21,0xEF,0x08,0x0E,0x00,0x06,0x02,0x0F,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"緞\",611*/},{\n\n0x08,0x08,0xFF,0x28,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"堆\",612*/},{\n\n0x08,0x04,0xFA,0x89,0x88,0x88,0x88,0x89,0xFA,0x04,0x08,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"兌\",613*/},{\n\n0xFE,0x02,0x32,0xCE,0xA4,0x95,0x4E,0x34,0xE6,0x45,0x24,0x0F,0x02,0x02,0x01,0x04,\n0x04,0x0A,0x09,0x07,0x01,0x02,/*\"隊\",614*/},{\n\n0x12,0xB4,0xDF,0x90,0xDF,0xB4,0x12,0x48,0x88,0xFF,0x08,0x08,0x0A,0x0A,0x0F,0x0A,\n0x0A,0x08,0x00,0x08,0x0F,0x00,/*\"對\",615*/},{\n\n0x08,0xFF,0x08,0xBA,0xAB,0xBA,0x10,0xEF,0x08,0xF8,0x08,0x02,0x03,0x01,0x0A,0x0E,\n0x03,0x0A,0x05,0x02,0x05,0x08,/*\"墩\",616*/},{\n\n0xFE,0x02,0xFE,0x84,0xFF,0x84,0xF4,0x00,0xFA,0xAE,0xFA,0x03,0x01,0x03,0x00,0x0F,\n0x04,0x02,0x00,0x0B,0x06,0x0B,/*\"噸\",617*/},{\n\n0x9E,0x12,0xFE,0x40,0xFA,0xAB,0xDE,0xCA,0xBE,0xAB,0xFA,0x07,0x04,0x03,0x02,0x02,\n0x06,0x0A,0x02,0x0A,0x0F,0x02,/*\"蹲\",618*/},{\n\n0x02,0xBA,0xAA,0xAB,0xAA,0x3A,0x10,0xEF,0x08,0xF8,0x08,0x02,0x02,0x0A,0x0E,0x03,\n0x02,0x08,0x05,0x02,0x05,0x08,/*\"敦\",619*/},{\n\n0xF4,0x84,0xFF,0x84,0xF4,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x00,0x00,0x0F,0x04,0x02,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頓\",620*/},{\n\n0x00,0xFF,0x05,0x75,0x45,0xFF,0x45,0x75,0x05,0x01,0xFF,0x00,0x0F,0x08,0x08,0x08,\n0x09,0x0A,0x0A,0x0B,0x08,0x0F,/*\"囤\",621*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xF4,0x84,0xFF,0x84,0xF4,0x08,0x09,0x07,0x05,0x04,\n0x00,0x00,0x00,0x07,0x08,0x0E,/*\"鈍\",622*/},{\n\n0x00,0xFE,0x0A,0xEA,0xAA,0xAA,0xBE,0xA9,0xA9,0xE9,0x08,0x08,0x07,0x00,0x0F,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"盾\",623*/},{\n\n0x11,0xF2,0x00,0xFE,0x05,0xF5,0x55,0x5F,0x55,0xF5,0x04,0x08,0x07,0x0A,0x09,0x08,\n0x0F,0x0D,0x0D,0x0D,0x0F,0x08,/*\"遁\",624*/},{\n\n0x88,0xFF,0x48,0x00,0xAA,0x92,0xAE,0x00,0xAA,0x92,0xAE,0x08,0x0F,0x00,0x08,0x0A,\n0x04,0x0B,0x00,0x0B,0x04,0x0B,/*\"掇\",625*/},{\n\n0xFE,0x02,0x02,0xFE,0x08,0x44,0xAB,0x52,0x6A,0x46,0xC0,0x03,0x01,0x01,0x03,0x08,\n0x09,0x04,0x05,0x02,0x01,0x00,/*\"哆\",626*/},{\n\n0x90,0x90,0x48,0x54,0x23,0x92,0x4A,0x66,0x52,0xC0,0x40,0x08,0x08,0x08,0x09,0x05,\n0x04,0x03,0x02,0x01,0x00,0x00,/*\"多\",627*/},{\n\n0x12,0x2A,0xF6,0xAA,0xAF,0xFA,0xAE,0xAA,0xA6,0x8A,0x12,0x02,0x02,0x07,0x0A,0x02,\n0x0A,0x0A,0x0F,0x02,0x02,0x02,/*\"奪\",628*/},{\n\n0x08,0x08,0xFF,0x08,0x50,0x4F,0x41,0xF1,0x41,0x4F,0x50,0x02,0x02,0x01,0x01,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"垛\",629*/},{\n\n0x80,0xFE,0xAB,0xAA,0xFE,0x50,0x4E,0xE2,0x4E,0x50,0x50,0x04,0x02,0x01,0x08,0x0F,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"躲\",630*/},{\n\n0x50,0x48,0x47,0x41,0xC1,0xF1,0xC1,0x41,0x47,0x48,0x48,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"朵\",631*/},{\n\n0xCF,0x09,0xF9,0x4F,0x10,0x4F,0x41,0xF1,0x41,0x4F,0x50,0x07,0x04,0x03,0x02,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"跺\",632*/},{\n\n0x20,0xFE,0xAB,0xFE,0x00,0x0C,0xE4,0x05,0x86,0x44,0x2C,0x08,0x07,0x08,0x0F,0x00,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"舵\",633*/},{\n\n0x50,0x4F,0x41,0xF1,0x41,0x4F,0x50,0x00,0xFC,0x00,0xFF,0x04,0x02,0x01,0x0F,0x01,\n0x02,0x04,0x00,0x01,0x08,0x0F,/*\"剁\",634*/},{\n\n0x78,0x00,0xFF,0x04,0x2A,0xE6,0xAB,0xBA,0xAA,0xEA,0x22,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"惰\",635*/},{\n\n0x00,0xFF,0x25,0x1B,0x10,0x0A,0xFE,0x2B,0xAE,0xFA,0x0A,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"墮\",636*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x92,0xFE,0x51,0xFF,0x92,0x54,0x04,0x04,0x03,0x02,0x07,\n0x08,0x0F,0x04,0x03,0x04,0x0E,/*\"蛾\",637*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x92,0xFE,0x51,0xFF,0x92,0x54,0x07,0x04,0x03,0x02,0x07,\n0x08,0x0F,0x04,0x03,0x04,0x0E,/*\"峨\",638*/},{\n\n0x92,0xFE,0x51,0xFF,0x92,0x54,0x00,0xFE,0xAB,0xBE,0xA0,0x08,0x0F,0x04,0x03,0x04,\n0x0E,0x00,0x08,0x06,0x08,0x0F,/*\"鵝\",639*/},{\n\n0x20,0x10,0xFC,0x93,0x92,0xFE,0x51,0x10,0xFF,0x92,0x54,0x00,0x00,0x0F,0x00,0x08,\n0x0F,0x04,0x02,0x03,0x04,0x0E,/*\"俄\",640*/},{\n\n0x96,0x5A,0x2E,0x2B,0x5A,0x86,0x00,0xFA,0xAE,0xAA,0xFA,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x00,0x0B,0x06,0x06,0x0B,/*\"額\",641*/},{\n\n0x54,0x55,0x56,0x54,0x10,0xFC,0x83,0x40,0xFF,0x10,0x0C,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x00,0x00,0x07,0x08,0x0E,/*\"訛\",642*/},{\n\n0x88,0x78,0x0F,0xF8,0x90,0x92,0xFE,0x51,0xFF,0x92,0x54,0x08,0x05,0x02,0x0D,0x00,\n0x08,0x0F,0x02,0x03,0x04,0x0E,/*\"娥\",643*/},{\n\n0x82,0xBA,0xAA,0xEE,0x82,0x82,0x82,0xEE,0xAA,0xBA,0x82,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"惡\",644*/},{\n\n0x00,0xFE,0x02,0x02,0xF2,0x12,0x12,0x12,0x12,0xF2,0x02,0x08,0x07,0x00,0x00,0x07,\n0x08,0x08,0x09,0x09,0x08,0x0E,/*\"厄\",645*/},{\n\n0x88,0x88,0xFF,0x48,0xFE,0x02,0xFA,0x0A,0x8A,0xFA,0x02,0x00,0x08,0x0F,0x08,0x07,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"扼\",646*/},{\n\n0x10,0x11,0xF2,0x80,0x5F,0x75,0x55,0xD5,0x55,0x5F,0xC0,0x08,0x04,0x03,0x04,0x0B,\n0x0A,0x0B,0x0A,0x0B,0x0C,0x0B,/*\"遏\",647*/},{\n\n0x47,0xD5,0x57,0x50,0x57,0x55,0x47,0x00,0xFF,0x31,0xCF,0x00,0x01,0x01,0x09,0x09,\n0x07,0x00,0x00,0x0F,0x02,0x01,/*\"鄂\",648*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0x92,0xFE,0x51,0xFF,0x92,0x54,0x00,0x0F,0x04,0x02,0x04,\n0x08,0x0F,0x04,0x03,0x04,0x0E,/*\"餓\",649*/},{\n\n0x00,0x7F,0x41,0x65,0x55,0x4F,0x55,0x65,0x41,0x7F,0x00,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"恩\",650*/},{\n\n0x02,0xF2,0x12,0x12,0xFA,0x16,0xF2,0x12,0x12,0xF2,0x02,0x00,0x0F,0x00,0x00,0x07,\n0x00,0x07,0x00,0x08,0x0F,0x00,/*\"而\",651*/},{\n\n0x00,0xFE,0x92,0x92,0x91,0x80,0x92,0x92,0x92,0xFE,0x00,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"兒\",652*/},{\n\n0x02,0x02,0xFE,0x52,0x52,0x52,0x52,0x52,0xFE,0x02,0x02,0x02,0x02,0x03,0x02,0x02,\n0x02,0x01,0x01,0x0F,0x01,0x01,/*\"耳\",653*/},{\n\n0x09,0xFD,0xAB,0x49,0xA9,0xFF,0xA9,0x49,0xAB,0xFD,0x09,0x00,0x0F,0x02,0x01,0x02,\n0x0F,0x02,0x09,0x0A,0x0F,0x00,/*\"爾\",654*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0x02,0xFE,0x52,0x52,0xFE,0x02,0x00,0x0F,0x04,0x02,0x04,\n0x02,0x03,0x02,0x02,0x0F,0x01,/*\"餌\",655*/},{\n\n0x22,0x44,0x00,0x02,0xFE,0x52,0x52,0x52,0xFE,0x02,0x00,0x04,0x02,0x01,0x02,0x03,\n0x02,0x02,0x02,0x0F,0x01,0x01,/*\"洱\",656*/},{\n\n0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00,0x04,0x04,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x04,/*\"二\",657*/},{\n\n0x02,0xEA,0xAA,0xAA,0xAA,0xEA,0x02,0xFF,0x02,0x03,0x02,0x00,0x0B,0x06,0x02,0x06,\n0x0B,0x00,0x00,0x03,0x04,0x0E,/*\"貳\",658*/},{\n\n0x20,0xD5,0x59,0x55,0x73,0x80,0x70,0x13,0x7C,0x52,0x28,0x00,0x01,0x09,0x09,0x07,\n0x08,0x0B,0x05,0x05,0x0B,0x00,/*\"發\",659*/},{\n\n0x10,0x57,0x55,0x5D,0x57,0x55,0x17,0x05,0xE5,0x07,0xF0,0x00,0x0F,0x05,0x05,0x05,\n0x0F,0x00,0x00,0x03,0x08,0x0F,/*\"罰\",660*/},{\n\n0x84,0x43,0xE2,0x56,0x42,0x44,0xF3,0x22,0x26,0xB2,0x22,0x00,0x00,0x0F,0x00,0x00,\n0x08,0x05,0x02,0x05,0x08,0x0E,/*\"筏\",661*/},{\n\n0x20,0x10,0xFC,0x03,0x10,0x10,0xFF,0x08,0x89,0x6A,0x08,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x0F,/*\"伐\",662*/},{\n\n0x22,0x22,0x22,0x22,0x2A,0x32,0xA1,0xA1,0x61,0x21,0x01,0x08,0x04,0x04,0x0A,0x09,\n0x09,0x08,0x08,0x08,0x08,0x08,/*\"乏\",663*/},{\n\n0xFF,0x95,0xD5,0xBF,0x80,0xE0,0x40,0x7F,0x55,0x15,0xFF,0x0F,0x00,0x0F,0x00,0x08,\n0x05,0x02,0x05,0x0E,0x00,0x0F,/*\"閥\",664*/},{\n\n0x10,0x21,0x42,0x48,0x48,0xC8,0x7F,0x48,0x48,0x48,0x40,0x04,0x02,0x01,0x04,0x06,\n0x05,0x04,0x04,0x05,0x06,0x0C,/*\"法\",665*/},{\n\n0x22,0x22,0xFE,0x22,0x10,0x21,0x42,0x44,0xFF,0x44,0x40,0x04,0x04,0x03,0x02,0x06,\n0x01,0x06,0x05,0x04,0x06,0x0C,/*\"琺\",666*/},{\n\n0x4A,0x92,0xA7,0xEA,0xBA,0xAA,0xFA,0xAA,0xB7,0xE2,0xA2,0x04,0x02,0x00,0x0F,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0F,0x00,/*\"藩\",667*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x00,0xFE,0x22,0x42,0xFE,0x00,0x01,0x00,0x0F,0x01,0x09,\n0x04,0x03,0x00,0x00,0x07,0x0C,/*\"帆\",668*/},{\n\n0x90,0x52,0xB6,0x9A,0x92,0xBE,0x91,0x99,0xB5,0x51,0x90,0x00,0x00,0x0F,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0F,0x00,0x00,/*\"番\",669*/},{\n\n0xD6,0xB2,0xFE,0x91,0xB5,0x10,0xA2,0xFE,0x10,0xA2,0xFE,0x0F,0x0A,0x0F,0x0A,0x0F,\n0x01,0x08,0x0F,0x01,0x08,0x0F,/*\"翻\",670*/},{\n\n0x24,0x14,0x7F,0x14,0x2D,0x92,0x2D,0x14,0x7F,0x14,0x24,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"樊\",671*/},{\n\n0x2A,0xA6,0xFF,0xAA,0xB5,0xAA,0xB5,0xAA,0xFF,0xA6,0x2A,0x01,0x00,0x04,0x0E,0x0B,\n0x0A,0x0A,0x0A,0x0E,0x00,0x01,/*\"礬\",672*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xFE,0x22,0x42,0xFE,0x00,0x00,0x08,0x09,0x07,0x0C,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"釩\",673*/},{\n\n0x04,0x3F,0xAA,0xFE,0xAA,0xBE,0x84,0x6B,0x12,0x2E,0x42,0x00,0x0A,0x06,0x02,0x0B,\n0x0E,0x02,0x02,0x07,0x0A,0x00,/*\"繁\",674*/},{\n\n0x00,0x00,0xFE,0x02,0x12,0x62,0x02,0xFE,0x00,0x00,0x00,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"凡\",675*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0xFA,0xAA,0xAE,0xAA,0xAA,0xFA,0x08,0x06,0x01,0x06,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"煩\",676*/},{\n\n0x00,0xFE,0x12,0x72,0x92,0x12,0x11,0x11,0x91,0x71,0x00,0x08,0x07,0x08,0x08,0x04,\n0x05,0x02,0x05,0x04,0x08,0x08,/*\"反\",677*/},{\n\n0x10,0x11,0xF2,0x00,0xFE,0x0A,0x2A,0x4A,0x89,0x49,0x39,0x08,0x04,0x03,0x06,0x09,\n0x08,0x0A,0x09,0x08,0x09,0x0A,/*\"返\",678*/},{\n\n0x14,0xD3,0x56,0xFA,0x52,0xD4,0x03,0xF2,0x16,0x12,0xF2,0x04,0x07,0x05,0x0F,0x05,\n0x07,0x04,0x07,0x08,0x09,0x0D,/*\"範\",679*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x00,0xFE,0x12,0xF2,0x12,0x91,0x71,0x09,0x05,0x05,0x09,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"販\",680*/},{\n\n0x10,0x8A,0x44,0xFB,0x00,0xFE,0x02,0x02,0x82,0xFE,0x00,0x01,0x08,0x08,0x07,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"犯\",681*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0xFE,0x12,0xF2,0x12,0x91,0x71,0x00,0x0F,0x04,0x0A,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"飯\",682*/},{\n\n0x10,0x22,0x04,0x00,0x22,0x22,0x2A,0xB1,0x61,0x21,0x00,0x04,0x02,0x01,0x08,0x04,\n0x02,0x05,0x08,0x08,0x08,0x08,/*\"泛\",683*/},{\n\n0x10,0x10,0xFF,0x10,0x04,0x04,0xFD,0x26,0x24,0x24,0xE4,0x04,0x04,0x03,0x02,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"坊\",684*/},{\n\n0x12,0x12,0x17,0xF2,0x92,0x96,0x9A,0x92,0x97,0x92,0x12,0x08,0x04,0x02,0x01,0x00,\n0x00,0x00,0x08,0x08,0x07,0x00,/*\"芳\",685*/},{\n\n0x04,0x04,0x04,0xFC,0x25,0x26,0x24,0x24,0x24,0xE4,0x04,0x08,0x04,0x03,0x00,0x00,\n0x00,0x08,0x08,0x08,0x07,0x00,/*\"方\",686*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x04,0x04,0xFD,0x26,0x24,0xE4,0x08,0x07,0x00,0x08,0x0F,\n0x08,0x06,0x01,0x08,0x08,0x07,/*\"肪\",687*/},{\n\n0x00,0xFE,0x4A,0x4A,0xCA,0x5A,0x6B,0x4A,0x4A,0x4A,0x4E,0x08,0x07,0x08,0x04,0x03,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"房\",688*/},{\n\n0xFE,0x02,0x32,0xCE,0x04,0x04,0xFD,0x26,0x24,0x24,0xE4,0x0F,0x02,0x02,0x01,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"防\",689*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x04,0xFD,0x26,0x24,0x24,0xE4,0x08,0x05,0x02,0x05,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"妨\",690*/},{\n\n0x20,0x10,0xFC,0x03,0x04,0x04,0xFD,0x26,0x24,0x24,0xE4,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"仿\",691*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x04,0xFD,0x26,0x24,0xE4,0x04,0x0F,0x05,0x05,0x07,0x08,\n0x06,0x01,0x08,0x08,0x07,0x00,/*\"訪\",692*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x04,0x04,0xFD,0x26,0x24,0xE4,0x0E,0x00,0x06,0x00,0x06,\n0x08,0x06,0x01,0x08,0x08,0x07,/*\"紡\",693*/},{\n\n0x08,0xF9,0x4A,0x48,0xC8,0x20,0x10,0xEF,0x08,0xF8,0x08,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x08,0x05,0x02,0x05,0x08,/*\"放\",694*/},{\n\n0x12,0x52,0x52,0x57,0xFA,0x02,0xFA,0x57,0x52,0x52,0x12,0x02,0x02,0x02,0x02,0x0F,\n0x00,0x0F,0x02,0x02,0x02,0x02,/*\"菲\",695*/},{\n\n0x04,0x24,0x24,0x24,0xFF,0x00,0xFF,0x24,0x24,0x24,0x04,0x01,0x01,0x01,0x01,0x0F,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"非\",696*/},{\n\n0xFC,0x04,0xFC,0x00,0x24,0x24,0xFF,0x00,0xFF,0x24,0x24,0x03,0x01,0x03,0x00,0x01,\n0x01,0x0F,0x00,0x0F,0x01,0x01,/*\"啡\",697*/},{\n\n0x41,0x49,0xF9,0x45,0xF9,0x41,0x4F,0xD0,0x22,0xA5,0x30,0x08,0x06,0x01,0x00,0x0F,\n0x00,0x00,0x03,0x05,0x0A,0x0C,/*\"飛\",698*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xFE,0x42,0x7E,0x42,0x42,0x7E,0x08,0x07,0x08,0x0F,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"肥\",699*/},{\n\n0x00,0xFE,0x02,0x52,0x52,0xFE,0x02,0x02,0xFE,0x52,0x52,0x00,0x0F,0x08,0x09,0x09,\n0x0F,0x08,0x08,0x0F,0x09,0x09,/*\"匪\",700*/},{\n\n0x55,0x56,0x54,0x00,0x24,0x24,0xFF,0x00,0xFF,0x24,0x24,0x0F,0x05,0x0F,0x00,0x01,\n0x01,0x0F,0x00,0x0F,0x01,0x01,/*\"誹\",701*/},{\n\n0xFE,0x02,0x02,0xFE,0x10,0x10,0xD0,0x3F,0xD0,0x12,0x14,0x03,0x01,0x01,0x03,0x08,\n0x06,0x01,0x00,0x01,0x06,0x08,/*\"吠\",702*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xE4,0x24,0xFF,0x24,0x24,0xE4,0x08,0x07,0x08,0x0F,0x00,\n0x03,0x00,0x0F,0x00,0x02,0x03,/*\"肺\",703*/},{\n\n0x00,0xFE,0x4A,0xB6,0xEE,0x82,0x63,0x26,0x2A,0x76,0xAA,0x08,0x07,0x00,0x0B,0x0E,\n0x00,0x0B,0x05,0x05,0x0B,0x00,/*\"廢\",704*/},{\n\n0x22,0x44,0x00,0xF2,0x92,0xFF,0x92,0xFF,0x92,0x9E,0x80,0x04,0x02,0x00,0x08,0x04,\n0x03,0x00,0x0F,0x04,0x04,0x03,/*\"沸\",705*/},{\n\n0x02,0xBA,0xAA,0xEA,0xBF,0xAA,0xFF,0xAA,0xAA,0xAE,0xE0,0x00,0x07,0x0C,0x05,0x06,\n0x04,0x05,0x06,0x0C,0x07,0x00,/*\"費\",706*/},{\n\n0x42,0x42,0xA2,0x97,0x8A,0x82,0x8A,0x97,0xA2,0x42,0x42,0x00,0x08,0x04,0x03,0x00,\n0x00,0x08,0x08,0x07,0x00,0x00,/*\"芬\",707*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x10,0x2C,0xE3,0x20,0xE3,0x0C,0x0F,0x05,0x05,0x05,0x0F,\n0x08,0x06,0x01,0x08,0x0F,0x00,/*\"酚\",708*/},{\n\n0xFE,0x02,0x02,0xFE,0x10,0x2C,0xE3,0x20,0x23,0xEC,0x10,0x03,0x01,0x01,0x03,0x08,\n0x06,0x01,0x08,0x08,0x07,0x00,/*\"吩\",709*/},{\n\n0x08,0xA4,0x6B,0x2A,0x2A,0x6A,0xAA,0x2A,0xEA,0x0A,0x02,0x01,0x08,0x05,0x03,0x09,\n0x0F,0x00,0x01,0x03,0x04,0x0E,/*\"氛\",710*/},{\n\n0x20,0x10,0x2C,0x23,0xE0,0x20,0x20,0x23,0xEC,0x10,0x20,0x00,0x08,0x04,0x03,0x00,\n0x08,0x08,0x08,0x07,0x00,0x00,/*\"分\",711*/},{\n\n0xD8,0xB4,0x93,0xC8,0x10,0x2C,0xE3,0x20,0x23,0xEC,0x10,0x0C,0x02,0x04,0x02,0x0C,\n0x06,0x01,0x08,0x08,0x07,0x00,/*\"紛\",712*/},{\n\n0x08,0xFF,0x08,0x00,0xEA,0xBE,0xAA,0xAF,0xAA,0xBE,0xEA,0x02,0x03,0x01,0x00,0x0B,\n0x06,0x02,0x02,0x02,0x06,0x0B,/*\"墳\",713*/},{\n\n0x12,0x0A,0xBF,0x0A,0x12,0xC0,0x12,0x0A,0x3F,0x8A,0x12,0x08,0x09,0x04,0x04,0x02,\n0x01,0x02,0x04,0x05,0x08,0x08,/*\"焚\",714*/},{\n\n0x10,0x21,0x22,0x10,0x2C,0x23,0xE0,0x20,0x23,0xEC,0x10,0x04,0x02,0x01,0x08,0x04,\n0x03,0x00,0x08,0x08,0x07,0x00,/*\"汾\",715*/},{\n\n0x24,0xA8,0xFF,0x24,0x10,0x2C,0xE3,0x20,0x23,0xEC,0x10,0x01,0x00,0x0F,0x01,0x08,\n0x06,0x01,0x08,0x08,0x07,0x00,/*\"粉\",716*/},{\n\n0x12,0xAA,0x96,0xFA,0xAF,0xAA,0xFE,0xAA,0xAE,0x8A,0x12,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"奮\",717*/},{\n\n0x10,0xFC,0x03,0x10,0x2C,0xE3,0x20,0x20,0x23,0xEC,0x10,0x00,0x0F,0x00,0x08,0x06,\n0x01,0x00,0x08,0x08,0x07,0x00,/*\"份\",718*/},{\n\n0x08,0x84,0x4A,0x29,0x18,0x08,0x88,0x89,0x7A,0x04,0x08,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"忿\",719*/},{\n\n0x78,0x00,0xFF,0x04,0xEA,0xBE,0xAA,0xAF,0xAA,0xBE,0xEA,0x00,0x00,0x0F,0x00,0x0B,\n0x06,0x02,0x02,0x02,0x06,0x0B,/*\"憤\",720*/},{\n\n0x24,0x14,0xFD,0x56,0x54,0xFF,0x54,0x56,0xFD,0x14,0x24,0x04,0x05,0x0D,0x07,0x05,\n0x05,0x05,0x07,0x0D,0x05,0x04,/*\"糞\",721*/},{\n\n0xBC,0xAA,0xBF,0xAA,0xA0,0xBF,0xA0,0xAA,0xBF,0xAA,0xBC,0x08,0x0B,0x0A,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x0A,0x0B,0x08,/*\"豐\",722*/},{\n\n0x20,0x24,0x24,0xBF,0x24,0x24,0x48,0x88,0x08,0xFF,0x08,0x08,0x09,0x09,0x07,0x05,\n0x05,0x00,0x09,0x08,0x0F,0x00,/*\"封\",723*/},{\n\n0xC8,0xFF,0x48,0xFE,0x52,0xF2,0x4A,0xCA,0x02,0xFE,0x00,0x00,0x0F,0x08,0x07,0x05,\n0x07,0x05,0x0D,0x00,0x07,0x0C,/*\"楓\",724*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x54,0x57,0xEA,0x4A,0x56,0x04,0x04,0x03,0x02,0x07,\n0x00,0x05,0x05,0x0F,0x05,0x05,/*\"蜂\",725*/},{\n\n0x40,0x53,0x4A,0x5E,0x2A,0xAB,0x2A,0x2A,0x5A,0x43,0x40,0x04,0x04,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x04,0x04,/*\"峯\",726*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x54,0x57,0xEA,0x4A,0x56,0x10,0x08,0x09,0x07,0x04,0x00,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"鋒\",727*/},{\n\n0x00,0xFF,0x01,0xE9,0xA9,0xF9,0xA5,0xE5,0x01,0xFF,0x00,0x08,0x07,0x00,0x04,0x04,\n0x07,0x04,0x0E,0x00,0x07,0x0C,/*\"風\",728*/},{\n\n0x08,0xFE,0x02,0xFA,0xAA,0xEB,0x9A,0x8A,0x0A,0xFA,0x02,0x09,0x07,0x08,0x07,0x0A,\n0x0F,0x0A,0x0F,0x00,0x07,0x0C,/*\"瘋\",729*/},{\n\n0x78,0x00,0xFF,0x08,0x14,0x56,0x4B,0xEA,0x4A,0x56,0x10,0x08,0x06,0x01,0x06,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"烽\",730*/},{\n\n0x11,0xF2,0x00,0x14,0xB6,0xAB,0xFA,0xAA,0xB6,0x10,0x10,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"逢\",731*/},{\n\n0x04,0x08,0x00,0xFE,0xAA,0xAA,0xFE,0xAA,0xAA,0xAA,0x82,0x02,0x01,0x06,0x00,0x06,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"馮\",732*/},{\n\n0xDC,0xB3,0xC8,0x21,0xE2,0x10,0x94,0xAB,0xFA,0xAA,0x96,0x0E,0x00,0x06,0x08,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"縫\",733*/},{\n\n0x55,0x56,0x54,0x00,0xFE,0x52,0xF2,0x4A,0xCA,0x02,0xFE,0x0F,0x05,0x0F,0x08,0x07,\n0x05,0x07,0x05,0x0D,0x00,0x07,/*\"諷\",734*/},{\n\n0x20,0xA2,0x6A,0xBA,0xAE,0xEB,0xAA,0xAA,0x6A,0xA2,0x20,0x01,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x01,/*\"奉\",735*/},{\n\n0x00,0xFF,0x01,0xF5,0x5D,0x55,0xF5,0x01,0x01,0xFF,0x00,0x08,0x07,0x08,0x07,0x0D,\n0x05,0x0D,0x0D,0x00,0x07,0x0C,/*\"鳳\",736*/},{\n\n0x10,0xFC,0x03,0xF2,0x92,0xFF,0x92,0xFF,0x92,0x9E,0x80,0x00,0x0F,0x00,0x08,0x04,\n0x03,0x00,0x0F,0x04,0x04,0x03,/*\"佛\",737*/},{\n\n0x11,0x91,0x89,0x89,0x85,0xBF,0x81,0x85,0x85,0x89,0x11,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"否\",738*/},{\n\n0x40,0x48,0x48,0x48,0x48,0xFF,0x48,0x48,0x48,0x48,0x40,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"夫\",739*/},{\n\n0x82,0xFA,0xAA,0xFF,0xAA,0xFB,0x92,0xEF,0x08,0xF8,0x08,0x08,0x04,0x03,0x0A,0x0A,\n0x06,0x08,0x05,0x02,0x05,0x08,/*\"敷\",740*/},{\n\n0x00,0xFC,0x04,0xD4,0x54,0x7F,0xD5,0x55,0x55,0xC5,0x6C,0x04,0x03,0x00,0x01,0x0F,\n0x05,0x05,0x05,0x0F,0x01,0x00,/*\"膚\",741*/},{\n\n0xFE,0x92,0xFD,0x00,0xFE,0x92,0xFE,0x00,0x2A,0xB2,0x69,0x09,0x04,0x03,0x00,0x0F,\n0x00,0x00,0x01,0x09,0x0F,0x01,/*\"孵\",742*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0x48,0x48,0xFF,0x48,0x48,0x40,0x00,0x08,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"扶\",743*/},{\n\n0x88,0xFF,0x48,0xF2,0x92,0xFF,0x92,0xFF,0x92,0x9E,0x80,0x08,0x0F,0x00,0x08,0x04,\n0x03,0x00,0x0F,0x04,0x04,0x03,/*\"拂\",744*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xDD,0x55,0xD5,0x55,0xDD,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x05,0x07,0x05,0x0F,/*\"輻\",745*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x00,0xDD,0x55,0xD5,0x55,0xDD,0x01,0x00,0x0F,0x01,0x01,\n0x00,0x0F,0x05,0x07,0x05,0x0F,/*\"幅\",746*/},{\n\n0xA8,0xA4,0xFB,0xAA,0xFA,0xAA,0xEA,0x0A,0xFA,0x02,0x02,0x0B,0x0A,0x07,0x02,0x0F,\n0x02,0x0A,0x0E,0x03,0x04,0x0E,/*\"氟\",747*/},{\n\n0x84,0x43,0xE2,0x16,0x42,0x44,0x43,0x42,0xF6,0x42,0x42,0x00,0x00,0x0F,0x00,0x01,\n0x02,0x08,0x08,0x0F,0x00,0x00,/*\"符\",748*/},{\n\n0x20,0x10,0xFC,0x03,0x10,0x10,0xD0,0x3F,0xD0,0x12,0x14,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x01,0x06,0x08,/*\"伏\",749*/},{\n\n0x20,0x10,0xFC,0x03,0x2A,0x32,0x26,0xAA,0x61,0x29,0x05,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x09,0x0F,0x01,0x01,0x01,/*\"俘\",750*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0xFE,0x42,0xD2,0x52,0xCE,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x0F,0x08,0x05,0x02,0x0D,/*\"服\",751*/},{\n\n0x10,0x21,0x02,0x00,0x2A,0x32,0x26,0xAA,0x61,0x29,0x05,0x04,0x02,0x01,0x00,0x01,\n0x01,0x09,0x0F,0x01,0x01,0x01,/*\"浮\",752*/},{\n\n0x10,0x21,0x02,0x20,0xAA,0xB2,0xA2,0xA3,0xB2,0xAA,0x20,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"涪\",753*/},{\n\n0x84,0x45,0xF6,0x2C,0xC1,0x5D,0x55,0xD5,0x55,0x5D,0xC1,0x00,0x00,0x0F,0x00,0x0F,\n0x05,0x05,0x07,0x05,0x05,0x0F,/*\"福\",754*/},{\n\n0x84,0x45,0xF6,0xAC,0x10,0xFC,0x03,0x10,0xFF,0x12,0x14,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"袱\",755*/},{\n\n0xF2,0x92,0x92,0xFF,0x92,0x92,0xFF,0x92,0x92,0x9E,0x80,0x00,0x08,0x06,0x01,0x00,\n0x00,0x0F,0x00,0x04,0x04,0x03,/*\"弗\",756*/},{\n\n0x04,0xF4,0x54,0x54,0x54,0xFF,0x54,0x54,0x55,0xF6,0x04,0x00,0x0F,0x01,0x01,0x01,\n0x07,0x01,0x01,0x09,0x0F,0x00,/*\"甫\",757*/},{\n\n0x88,0x88,0xFF,0x48,0x24,0xFF,0x24,0xFC,0x24,0xFC,0x24,0x00,0x08,0x0F,0x00,0x0D,\n0x01,0x0D,0x01,0x0D,0x01,0x0D,/*\"撫\",758*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xF4,0x54,0xFF,0x54,0xF5,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x01,0x07,0x09,0x0F,/*\"輔\",759*/},{\n\n0x10,0xFC,0x03,0xFC,0x44,0xE4,0x15,0x46,0x44,0xF4,0x44,0x00,0x0F,0x08,0x07,0x00,\n0x0F,0x00,0x01,0x0A,0x0F,0x00,/*\"俯\",760*/},{\n\n0x20,0x24,0x52,0x55,0x48,0xC8,0x48,0x55,0x52,0x24,0x20,0x08,0x09,0x0B,0x0D,0x09,\n0x0F,0x09,0x0D,0x0B,0x09,0x08,/*\"釜\",761*/},{\n\n0x20,0x24,0xD2,0x55,0x48,0x48,0x28,0x35,0x12,0x24,0x20,0x08,0x04,0x03,0x01,0x01,\n0x01,0x0F,0x01,0x01,0x01,0x00,/*\"斧\",762*/},{\n\n0x00,0xFE,0x92,0xFE,0x04,0xF4,0x54,0xFF,0x54,0x55,0xF6,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x01,0x07,0x01,0x09,0x0F,/*\"脯\",763*/},{\n\n0xFE,0x92,0xFE,0x00,0xFC,0x44,0xE4,0x55,0x46,0xF4,0x44,0x07,0x08,0x0F,0x08,0x07,\n0x00,0x0F,0x01,0x0A,0x0F,0x00,/*\"腑\",764*/},{\n\n0x00,0xFC,0x44,0x24,0xF4,0x0D,0xA6,0x24,0x24,0xFC,0x24,0x08,0x07,0x00,0x00,0x0F,\n0x00,0x00,0x09,0x08,0x0F,0x00,/*\"府\",765*/},{\n\n0x00,0xFE,0x12,0x8A,0xBE,0x82,0xCB,0x9A,0xAA,0xBE,0x8A,0x08,0x07,0x00,0x0F,0x00,\n0x0A,0x05,0x0A,0x00,0x08,0x0F,/*\"腐\",766*/},{\n\n0x20,0xA4,0x24,0xFF,0x24,0x20,0x00,0xFF,0x08,0x10,0x60,0x08,0x07,0x04,0x0F,0x09,\n0x09,0x08,0x0B,0x08,0x08,0x08,/*\"赴\",767*/},{\n\n0xC1,0x5D,0x55,0xD5,0x55,0x5D,0xC1,0x00,0xFC,0x00,0xFF,0x0F,0x05,0x05,0x07,0x05,\n0x05,0x0F,0x00,0x01,0x08,0x0F,/*\"副\",768*/},{\n\n0x81,0x5D,0xB5,0x55,0x1F,0xF5,0x55,0x5F,0x55,0xF5,0x1D,0x02,0x01,0x0F,0x00,0x0A,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"覆\",769*/},{\n\n0xFE,0x2A,0xFE,0x00,0x90,0x12,0xF2,0x90,0xFF,0x12,0x14,0x09,0x05,0x09,0x08,0x0F,\n0x08,0x07,0x04,0x03,0x04,0x0E,/*\"賦\",770*/},{\n\n0x24,0xF2,0x09,0x02,0x7D,0xD5,0x55,0x55,0x55,0x7D,0x01,0x00,0x0F,0x00,0x0A,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"復\",771*/},{\n\n0x10,0xFC,0x03,0xFA,0x2A,0x2A,0xFF,0x2A,0x2B,0xFA,0x02,0x00,0x0F,0x00,0x02,0x06,\n0x0A,0x02,0x0A,0x0F,0x02,0x02,/*\"傅\",772*/},{\n\n0x20,0x10,0xFC,0x03,0x08,0x48,0x88,0x08,0x08,0xFF,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x01,0x08,0x08,0x0F,0x00,/*\"付\",773*/},{\n\n0x00,0xFE,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xAE,0xE0,0x00,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"阜\",774*/},{\n\n0x08,0x04,0x0B,0x30,0x40,0x80,0x40,0x30,0x09,0x02,0x0C,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"父\",775*/},{\n\n0x00,0xFF,0x49,0xFF,0x02,0x7D,0xD5,0x55,0x55,0x7D,0x01,0x08,0x07,0x08,0x0F,0x02,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"腹\",776*/},{\n\n0x08,0xFC,0xAA,0xAB,0xAA,0xAA,0xAA,0xAA,0xAE,0xF8,0x00,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"負\",777*/},{\n\n0x06,0x8A,0xEA,0xAA,0xAA,0xAB,0xAA,0xAA,0xEA,0x8A,0x06,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"富\",778*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0x00,0xFF,0x10,0x20,0xC0,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"訃\",779*/},{\n\n0xFE,0x02,0x32,0xCE,0x10,0xFC,0x03,0x48,0x88,0xFF,0x08,0x0F,0x02,0x02,0x01,0x00,\n0x0F,0x00,0x00,0x08,0x0F,0x00,/*\"附\",780*/},{\n\n0x88,0x78,0x0F,0xF8,0xC0,0x55,0x55,0xD5,0x55,0x5F,0xC0,0x08,0x05,0x02,0x0D,0x00,\n0x07,0x01,0x0F,0x05,0x07,0x00,/*\"婦\",781*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFA,0x2A,0x2A,0xFF,0x2A,0x2B,0xFA,0x0E,0x00,0x06,0x00,0x02,\n0x06,0x0A,0x02,0x0A,0x0F,0x02,/*\"縛\",782*/},{\n\n0xFE,0x02,0xFE,0x10,0xFC,0x03,0x28,0xC8,0x08,0xFF,0x08,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x00,0x00,0x08,0x0F,0x00,/*\"咐\",783*/},{\n\n0xFC,0x04,0xFC,0x02,0xFA,0xAF,0xAA,0xAA,0xAF,0xFA,0x82,0x03,0x01,0x03,0x01,0x06,\n0x04,0x06,0x05,0x06,0x08,0x0F,/*\"噶\",784*/},{\n\n0xFC,0x04,0xFC,0x01,0x7D,0xD5,0x57,0x55,0xD5,0x7D,0x01,0x03,0x01,0x03,0x02,0x0A,\n0x0A,0x0B,0x05,0x05,0x0B,0x0D,/*\"嘎\",785*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x24,0x34,0xAD,0x66,0x24,0x94,0x0F,0x05,0x05,0x0F,0x00,\n0x09,0x09,0x04,0x02,0x05,0x08,/*\"該\",786*/},{\n\n0xE2,0x22,0x22,0x3E,0x20,0x10,0xEF,0x08,0x88,0x78,0x08,0x0F,0x04,0x02,0x01,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"改\",787*/},{\n\n0xC8,0xFF,0x48,0xFE,0x92,0xFE,0x00,0x3A,0xA2,0x7E,0x22,0x00,0x0F,0x00,0x0F,0x0A,\n0x04,0x08,0x06,0x01,0x0F,0x08,/*\"概\",788*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xF2,0x82,0xFE,0x92,0x92,0x08,0x09,0x07,0x05,0x04,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"鈣\",789*/},{\n\n0x22,0xAA,0xEA,0xAF,0xAA,0xBE,0xAA,0xAF,0xAA,0xEA,0xA2,0x08,0x0E,0x0A,0x0A,0x0E,\n0x0A,0x0E,0x0A,0x0A,0x0E,0x09,/*\"蓋\",790*/},{\n\n0x22,0x44,0x00,0xFE,0x92,0xFE,0x00,0x3A,0xA2,0x7E,0x22,0x04,0x02,0x00,0x0F,0x0A,\n0x04,0x08,0x06,0x01,0x0F,0x08,/*\"溉\",791*/},{\n\n0xFA,0xAA,0xAF,0xAA,0xFA,0x00,0x04,0x12,0xF1,0x12,0x04,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x01,0x01,0x0F,0x01,0x01,/*\"幹\",792*/},{\n\n0x04,0x04,0xFF,0x44,0x44,0x44,0x44,0x44,0xFF,0x04,0x04,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x0F,0x00,0x00,/*\"甘\",793*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0x42,0x42,0xFE,0x42,0x42,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"杆\",794*/},{\n\n0x88,0x68,0xFF,0x28,0x44,0xFF,0x44,0x44,0x44,0xFF,0x04,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"柑\",795*/},{\n\n0x08,0x24,0x23,0x26,0x2A,0xE2,0x24,0x23,0x26,0x2A,0x02,0x01,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"竿\",796*/},{\n\n0x00,0xFE,0x92,0xFE,0x40,0x42,0x42,0xFE,0x42,0x42,0x40,0x08,0x07,0x08,0x0F,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"肝\",797*/},{\n\n0x20,0xA4,0x24,0xFF,0x24,0x00,0x5F,0x55,0xD5,0x55,0x5F,0x08,0x07,0x04,0x0F,0x09,\n0x08,0x09,0x09,0x0F,0x09,0x09,/*\"趕\",798*/},{\n\n0x00,0xFE,0x02,0xEA,0xAA,0xEA,0x02,0x9F,0x62,0x9B,0xC2,0x09,0x06,0x00,0x06,0x08,\n0x0A,0x0D,0x08,0x0C,0x02,0x0D,/*\"感\",799*/},{\n\n0x12,0xD2,0xFE,0x91,0x00,0x5F,0x55,0xD5,0x55,0x5F,0x00,0x01,0x00,0x0F,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"稈\",800*/},{\n\n0x08,0xFA,0xAA,0xAE,0xF8,0x28,0x10,0xEF,0x08,0xF8,0x08,0x02,0x03,0x02,0x02,0x0F,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"敢\",801*/},{\n\n0x0A,0xFE,0xAB,0xFE,0x0A,0x94,0xB7,0xAA,0xEA,0xB6,0x90,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0B,0x06,0x06,0x0B,0x00,/*\"贛\",802*/},{\n\n0xFF,0x11,0xD5,0x19,0x11,0xF1,0x11,0x19,0xD5,0x11,0xFF,0x0F,0x00,0x03,0x02,0x02,\n0x03,0x02,0x02,0x0B,0x08,0x0F,/*\"岡\",803*/},{\n\n0xFE,0xAA,0x32,0xE2,0x32,0xAA,0xFE,0x00,0xFC,0x00,0xFF,0x0F,0x03,0x02,0x03,0x02,\n0x0B,0x0F,0x00,0x01,0x08,0x0F,/*\"剛\",804*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFE,0xAA,0x32,0xE2,0x32,0xAA,0xFE,0x0A,0x0F,0x05,0x00,0x0F,\n0x03,0x02,0x03,0x02,0x0B,0x0F,/*\"鋼\",805*/},{\n\n0x48,0x47,0xFC,0x44,0x44,0x00,0x02,0x02,0xFE,0x02,0x02,0x0F,0x08,0x07,0x04,0x0F,\n0x00,0x08,0x08,0x0F,0x08,0x08,/*\"缸\",806*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0x02,0x02,0xFE,0x02,0x02,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x08,0x08,0x0F,0x08,0x08,/*\"肛\",807*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFE,0xAA,0x32,0xE2,0x32,0xAA,0xFE,0x0E,0x00,0x06,0x00,0x0F,\n0x03,0x02,0x03,0x02,0x0B,0x0F,/*\"綱\",808*/},{\n\n0x00,0xF6,0x94,0xB4,0xD4,0x97,0xD4,0xB4,0x94,0xF6,0x00,0x00,0x0F,0x00,0x06,0x04,\n0x07,0x04,0x06,0x08,0x0F,0x00,/*\"崗\",809*/},{\n\n0x22,0x44,0x90,0x54,0xBF,0x94,0x94,0x94,0xBF,0x54,0x90,0x08,0x04,0x02,0x00,0x07,\n0x0A,0x0A,0x0A,0x0B,0x0C,0x00,/*\"港\",810*/},{\n\n0x88,0x68,0xFF,0x48,0xF4,0x55,0x55,0x57,0x55,0x55,0xF4,0x00,0x00,0x0F,0x00,0x07,\n0x0D,0x05,0x05,0x05,0x0D,0x07,/*\"槓\",811*/},{\n\n0x8C,0x8B,0xEA,0xAE,0xAA,0xAC,0xAB,0xAA,0xEE,0x8A,0x8A,0x0F,0x00,0x00,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x00,0x08,0x0F,/*\"篙\",812*/},{\n\n0x80,0xBE,0xAA,0xAA,0xEB,0xAA,0xAA,0xAA,0xAA,0xBE,0x80,0x04,0x02,0x05,0x04,0x04,\n0x0E,0x04,0x04,0x05,0x02,0x04,/*\"皋\",813*/},{\n\n0x82,0x82,0xBA,0xAA,0xAA,0xAB,0xAA,0xAA,0xBA,0x82,0x82,0x0F,0x00,0x00,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x00,0x08,0x0F,/*\"高\",814*/},{\n\n0x62,0x22,0xEE,0xAA,0xAA,0xAB,0xAA,0xAA,0xEE,0x22,0x62,0x00,0x00,0x0F,0x02,0x02,\n0x02,0x02,0x0A,0x0F,0x00,0x00,/*\"膏\",815*/},{\n\n0x00,0x24,0x25,0x26,0x24,0xFC,0x24,0x26,0x25,0x24,0x00,0x09,0x05,0x01,0x05,0x09,\n0x01,0x05,0x09,0x01,0x05,0x09,/*\"羔\",816*/},{\n\n0x24,0xA8,0xFF,0xA8,0x04,0x25,0x26,0xFC,0x26,0x25,0x04,0x01,0x00,0x0F,0x00,0x0D,\n0x01,0x0D,0x01,0x0D,0x01,0x0D,/*\"糕\",817*/},{\n\n0x88,0x88,0xFF,0x48,0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x00,0x08,0x0F,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"搞\",818*/},{\n\n0x4A,0xF9,0x4A,0x00,0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x0A,0x0F,0x05,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"鎬\",819*/},{\n\n0x12,0xD2,0xFE,0x51,0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x01,0x00,0x0F,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"稿\",820*/},{\n\n0x20,0xA8,0xA6,0xA4,0xA4,0xBF,0xA4,0xA4,0xA4,0xA4,0x20,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"告\",821*/},{\n\n0x41,0x5D,0x55,0x55,0x55,0x55,0x5D,0x41,0x41,0xDF,0x41,0x00,0x07,0x05,0x05,0x05,\n0x05,0x07,0x00,0x08,0x0F,0x00,/*\"哥\",822*/},{\n\n0x5D,0x55,0x5D,0x41,0xDF,0x41,0x10,0x0F,0xC4,0x14,0x0C,0x07,0x05,0x07,0x08,0x0F,\n0x00,0x08,0x06,0x01,0x06,0x08,/*\"歌\",823*/},{\n\n0x88,0xFF,0x48,0xFF,0x15,0x5F,0xA0,0xA0,0x7F,0x15,0xFF,0x08,0x0F,0x00,0x0F,0x01,\n0x0F,0x0A,0x0A,0x0F,0x09,0x0F,/*\"擱\",824*/},{\n\n0x10,0x10,0x10,0x10,0x3F,0xD0,0x08,0x89,0x4A,0x28,0x08,0x00,0x08,0x08,0x04,0x04,\n0x02,0x01,0x02,0x04,0x08,0x0F,/*\"戈\",825*/},{\n\n0x10,0xA8,0xA4,0xA3,0xA4,0x08,0xFE,0xAB,0xAA,0xBE,0xA0,0x00,0x0F,0x04,0x04,0x0F,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鴿\",826*/},{\n\n0x00,0xFE,0x92,0xFE,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"胳\",827*/},{\n\n0x08,0x90,0xFC,0x44,0x24,0x5D,0x56,0x54,0xD4,0x54,0x04,0x09,0x04,0x03,0x00,0x04,\n0x0A,0x09,0x09,0x08,0x08,0x0C,/*\"疙\",828*/},{\n\n0x86,0xAA,0xAA,0xFF,0xAA,0xAA,0x86,0x00,0xFC,0x00,0xFF,0x00,0x0E,0x0A,0x0B,0x0A,\n0x0E,0x00,0x00,0x01,0x08,0x0F,/*\"割\",829*/},{\n\n0x02,0xE2,0xAF,0xAA,0xAA,0xFA,0xAA,0xAA,0xAF,0xE2,0x02,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"革\",830*/},{\n\n0x02,0x82,0xFA,0xAF,0xAA,0xAA,0xAA,0xAF,0xAA,0xFA,0x82,0x02,0x01,0x06,0x04,0x06,\n0x05,0x06,0x04,0x04,0x08,0x0F,/*\"葛\",831*/},{\n\n0x88,0x68,0xFF,0x28,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"格\",832*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x10,0xAC,0xA3,0xA4,0xA8,0x10,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"蛤\",833*/},{\n\n0xFF,0x15,0x55,0x5F,0xA0,0xB0,0xA0,0x7F,0x15,0x15,0xFF,0x0F,0x00,0x01,0x0F,0x0A,\n0x0A,0x0A,0x0F,0x01,0x08,0x0F,/*\"閣\",834*/},{\n\n0xFF,0x31,0xCF,0x00,0xC1,0x5D,0xD5,0x55,0xD5,0x5D,0xC1,0x0F,0x02,0x01,0x00,0x0F,\n0x00,0x02,0x0F,0x02,0x08,0x0F,/*\"隔\",835*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x44,0xAB,0x92,0x92,0xAE,0x40,0x08,0x09,0x07,0x05,0x04,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"鉻\",836*/},{\n\n0x20,0x10,0xFC,0x03,0xFE,0x02,0xD2,0x7E,0xD2,0x02,0xFE,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x05,0x05,0x05,0x04,0x0F,/*\"個\",837*/},{\n\n0x48,0x44,0xA7,0xAA,0x92,0x92,0x92,0xAA,0xA6,0x40,0x40,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x0F,0x00,0x00,/*\"各\",838*/},{\n\n0xD8,0xB4,0x93,0xC8,0x10,0xA8,0xA4,0xA3,0xA4,0xA8,0x10,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"給\",839*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"根\",840*/},{\n\n0xCF,0x09,0xF9,0x4F,0x00,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x07,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"跟\",841*/},{\n\n0x44,0x54,0xFF,0x54,0x44,0x88,0xFF,0x88,0x88,0xFF,0x88,0x02,0x01,0x0F,0x01,0x0A,\n0x04,0x03,0x00,0x00,0x0F,0x00,/*\"耕\",842*/},{\n\n0x02,0xFA,0xAA,0xAA,0xAA,0xFE,0xAA,0xAA,0xAA,0xFA,0x02,0x08,0x09,0x0A,0x04,0x04,\n0x0B,0x08,0x08,0x08,0x08,0x08,/*\"更\",843*/},{\n\n0x00,0xFC,0x44,0x54,0x54,0x55,0xFE,0x54,0x54,0xF4,0x44,0x08,0x07,0x08,0x09,0x05,\n0x03,0x01,0x03,0x05,0x09,0x08,/*\"庚\",844*/},{\n\n0x28,0x9A,0x8A,0xCB,0x9A,0x8E,0x9A,0xCB,0x8A,0x9A,0x28,0x0A,0x0A,0x0A,0x06,0x02,\n0x03,0x02,0x06,0x0A,0x0A,0x0A,/*\"羹\",845*/},{\n\n0x10,0xFF,0x10,0x00,0xFA,0xAA,0xAA,0xFE,0xAA,0xAA,0xFA,0x04,0x07,0x02,0x00,0x08,\n0x05,0x02,0x05,0x08,0x08,0x08,/*\"埂\",846*/},{\n\n0x02,0xFE,0x52,0xFE,0x22,0x1C,0x80,0x7F,0x80,0x10,0x0C,0x02,0x03,0x02,0x0F,0x09,\n0x06,0x01,0x00,0x01,0x06,0x08,/*\"耿\",847*/},{\n\n0x88,0x68,0xFF,0x48,0xFA,0xAA,0xAA,0xFE,0xAA,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x08,\n0x05,0x02,0x05,0x08,0x08,0x08,/*\"梗\",848*/},{\n\n0x00,0x02,0x02,0x02,0x02,0xFE,0x02,0x02,0x02,0x02,0x00,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"工\",849*/},{\n\n0x04,0x04,0xFC,0x04,0x24,0x10,0xEF,0x08,0x88,0x78,0x08,0x02,0x02,0x01,0x01,0x09,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"攻\",850*/},{\n\n0x04,0x04,0xFC,0x04,0x04,0x08,0xFF,0x08,0x08,0x08,0xF8,0x02,0x02,0x01,0x09,0x05,\n0x03,0x00,0x00,0x08,0x08,0x07,/*\"功\",851*/},{\n\n0x10,0x94,0x54,0x3F,0xD4,0x14,0x14,0x3F,0x54,0x94,0x10,0x01,0x04,0x02,0x08,0x0F,\n0x01,0x06,0x01,0x06,0x00,0x01,/*\"恭\",852*/},{\n\n0x08,0x7A,0x2E,0xAB,0x2E,0x7A,0x08,0xB7,0x55,0x5D,0x60,0x04,0x05,0x0D,0x07,0x05,\n0x05,0x05,0x07,0x0D,0x05,0x04,/*\"龔\",853*/},{\n\n0x10,0xFC,0x83,0x88,0xFF,0x88,0x88,0x88,0xFF,0x88,0x80,0x00,0x0F,0x08,0x04,0x02,\n0x00,0x00,0x00,0x02,0x04,0x08,/*\"供\",854*/},{\n\n0x80,0xFE,0xAB,0xAA,0xFE,0x00,0xF2,0x92,0x92,0x92,0x9E,0x04,0x02,0x01,0x08,0x0F,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"躬\",855*/},{\n\n0x40,0x20,0x18,0x07,0xC0,0x30,0x00,0x07,0x18,0x20,0x40,0x00,0x04,0x06,0x05,0x04,\n0x04,0x04,0x05,0x06,0x0C,0x00,/*\"公\",856*/},{\n\n0x06,0x02,0x7A,0x4A,0xCA,0x4B,0x4A,0x4A,0x7A,0x02,0x06,0x00,0x0F,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0F,0x00,/*\"宮\",857*/},{\n\n0x00,0xF2,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x9E,0x80,0x00,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"弓\",858*/},{\n\n0x10,0x51,0x4F,0xE9,0x50,0x4F,0x45,0xE9,0x4F,0x50,0x18,0x04,0x04,0x07,0x05,0x05,\n0x0F,0x05,0x05,0x07,0x04,0x04,/*\"鞏\",859*/},{\n\n0x88,0x89,0x89,0x89,0x09,0xEF,0x89,0x09,0x89,0x49,0x08,0x04,0x04,0x02,0x01,0x08,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"汞\",860*/},{\n\n0x88,0xFF,0x48,0x80,0x88,0xFF,0x88,0x88,0xFF,0x88,0x80,0x08,0x0F,0x00,0x08,0x04,\n0x02,0x00,0x00,0x02,0x04,0x08,/*\"拱\",861*/},{\n\n0x04,0xF5,0x55,0x55,0x55,0x57,0x55,0x55,0x55,0xF5,0x04,0x00,0x07,0x0D,0x05,0x05,\n0x05,0x05,0x05,0x0D,0x07,0x00,/*\"貢\",862*/},{\n\n0x80,0x88,0x88,0xFF,0x88,0x88,0x88,0xFF,0x88,0x88,0x80,0x00,0x08,0x04,0x02,0x00,\n0x00,0x00,0x02,0x04,0x08,0x00,/*\"共\",863*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x10,0xE8,0x27,0xE4,0x04,0xFC,0x08,0x09,0x07,0x05,0x04,\n0x00,0x03,0x01,0x09,0x08,0x07,/*\"鉤\",864*/},{\n\n0x20,0x10,0x8C,0x47,0x34,0x04,0x44,0x84,0x04,0x04,0xFC,0x00,0x01,0x01,0x01,0x01,\n0x01,0x01,0x0B,0x08,0x08,0x07,/*\"勾\",865*/},{\n\n0x22,0x44,0x08,0xEA,0xAF,0xAA,0xFA,0xAA,0xAF,0xEA,0x08,0x04,0x02,0x02,0x0F,0x02,\n0x02,0x03,0x02,0x0A,0x0F,0x02,/*\"溝\",866*/},{\n\n0x42,0x22,0xDA,0x57,0x52,0x52,0x52,0xD7,0x12,0x12,0xF2,0x00,0x00,0x07,0x02,0x02,\n0x02,0x02,0x0B,0x08,0x08,0x07,/*\"苟\",867*/},{\n\n0x10,0x8A,0x44,0xFB,0x10,0xE8,0x27,0x24,0xE4,0x04,0xFC,0x01,0x08,0x08,0x07,0x00,\n0x03,0x01,0x01,0x09,0x08,0x07,/*\"狗\",868*/},{\n\n0x08,0x08,0xFF,0x08,0x00,0xFE,0x92,0x92,0x91,0x91,0x91,0x02,0x02,0x01,0x09,0x06,\n0x01,0x0F,0x04,0x04,0x04,0x0F,/*\"垢\",869*/},{\n\n0x84,0x64,0xFF,0x24,0x08,0xEA,0xAF,0xFA,0xAF,0xEA,0x08,0x00,0x00,0x0F,0x00,0x02,\n0x0F,0x02,0x03,0x0A,0x0F,0x02,/*\"構\",870*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x08,0xEA,0xAF,0xFA,0xAF,0xEA,0x08,0x09,0x05,0x05,0x09,0x02,\n0x0F,0x02,0x03,0x0A,0x0F,0x02,/*\"購\",871*/},{\n\n0x44,0xAB,0x52,0x6E,0xC0,0x10,0xE8,0x27,0xE4,0x04,0xFC,0x09,0x08,0x05,0x02,0x01,\n0x00,0x03,0x01,0x09,0x08,0x07,/*\"夠\",872*/},{\n\n0x02,0xBA,0xAA,0xAA,0xAA,0xEF,0xAA,0xAA,0xAA,0xBA,0x02,0x02,0x02,0x02,0x03,0x02,\n0x0E,0x02,0x03,0x02,0x02,0x02,/*\"辜\",873*/},{\n\n0xA2,0x62,0x3A,0x27,0xE2,0x02,0xA2,0xA7,0xFA,0xA2,0xA2,0x08,0x05,0x02,0x05,0x08,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"菇\",874*/},{\n\n0xFC,0x04,0x04,0xFC,0x08,0xC8,0x48,0x7F,0x48,0xC8,0x08,0x03,0x01,0x01,0x03,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"咕\",875*/},{\n\n0x24,0x23,0xFA,0xA6,0xF2,0x14,0xD3,0x52,0xF6,0x52,0xD2,0x01,0x09,0x0F,0x00,0x0F,\n0x08,0x0B,0x08,0x0F,0x0A,0x0B,/*\"箍\",876*/},{\n\n0x10,0xFC,0x0B,0xC8,0x48,0x48,0x7F,0x48,0x48,0xC8,0x08,0x00,0x0F,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"估\",877*/},{\n\n0x10,0x21,0x0A,0xC8,0x48,0x48,0x7F,0x48,0x48,0xC8,0x08,0x04,0x02,0x01,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"沽\",878*/},{\n\n0x82,0x82,0xF2,0x4E,0x00,0xFE,0x02,0xFE,0x02,0xFD,0x01,0x00,0x08,0x0F,0x00,0x08,\n0x07,0x00,0x0F,0x0A,0x0C,0x03,/*\"孤\",879*/},{\n\n0x88,0x78,0x0F,0x88,0x78,0x00,0xC8,0x48,0x7F,0x48,0xC8,0x08,0x05,0x02,0x05,0x08,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"姑\",880*/},{\n\n0x02,0xEA,0xAA,0xAF,0xAA,0xEA,0x24,0xE4,0x3F,0xE4,0x04,0x08,0x09,0x0A,0x04,0x06,\n0x05,0x08,0x05,0x02,0x05,0x08,/*\"鼓\",881*/},{\n\n0x08,0xC8,0x48,0x48,0x48,0x7F,0x48,0x48,0x48,0xC8,0x08,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"古\",882*/},{\n\n0xA0,0xAE,0xEA,0xAA,0xAA,0x3F,0xAA,0xAA,0xEA,0xAE,0xB0,0x0B,0x0E,0x0B,0x0A,0x0F,\n0x0A,0x0F,0x0A,0x0B,0x0E,0x0B,/*\"蠱\",883*/},{\n\n0x30,0x10,0xDF,0x55,0x55,0x55,0x5D,0x51,0xDF,0x10,0x30,0x00,0x00,0x0F,0x05,0x05,\n0x05,0x05,0x0D,0x0F,0x00,0x00,/*\"骨\",884*/},{\n\n0x40,0x44,0xA2,0x91,0x88,0x84,0x88,0x91,0xA2,0x44,0x40,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x0F,0x00,0x00,/*\"谷\",885*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x50,0xCE,0x42,0x42,0xDE,0x10,0x08,0x07,0x00,0x08,0x0F,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"股\",886*/},{\n\n0xC8,0x48,0x7F,0x48,0xC8,0x10,0xEF,0x08,0x08,0xF8,0x08,0x0F,0x04,0x04,0x04,0x0F,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"故\",887*/},{\n\n0x00,0xFE,0x4A,0xFA,0xAB,0xFA,0xAE,0x00,0xFA,0xAE,0xFA,0x08,0x07,0x00,0x0F,0x0A,\n0x0F,0x0A,0x00,0x0B,0x06,0x0B,/*\"顧\",888*/},{\n\n0xFF,0x01,0x09,0xE9,0x29,0x3F,0x29,0xE9,0x09,0x01,0xFF,0x0F,0x04,0x04,0x05,0x05,\n0x05,0x05,0x05,0x04,0x04,0x0F,/*\"固\",889*/},{\n\n0x10,0xFC,0x03,0xFE,0x4A,0xEA,0xBA,0xAB,0xFA,0xAA,0xAE,0x00,0x0F,0x04,0x03,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"僱\",890*/},{\n\n0x10,0x92,0x92,0xFE,0x91,0x91,0x10,0xFC,0x00,0x00,0xFF,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x00,0x01,0x08,0x08,0x0F,/*\"刮\",891*/},{\n\n0x00,0xFE,0x02,0x02,0xFE,0x02,0x02,0x7F,0x81,0x01,0x00,0x08,0x07,0x00,0x00,0x0F,\n0x08,0x05,0x0E,0x01,0x06,0x08,/*\"瓜\",892*/},{\n\n0xE0,0x3F,0xA5,0xBD,0xA1,0x3F,0xE0,0x00,0xFC,0x00,0xFF,0x0F,0x00,0x03,0x02,0x03,\n0x08,0x0F,0x00,0x01,0x08,0x0F,/*\"剮\",893*/},{\n\n0x86,0x8A,0xEA,0xAA,0xBA,0xEB,0xAA,0xAA,0xEA,0x8A,0x86,0x04,0x02,0x09,0x0A,0x06,\n0x02,0x0A,0x0E,0x01,0x02,0x04,/*\"寡\",894*/},{\n\n0x88,0xFF,0x48,0x10,0x94,0xDF,0x94,0x10,0xFF,0x10,0x60,0x08,0x0F,0x00,0x04,0x04,\n0x03,0x02,0x02,0x0F,0x00,0x00,/*\"掛\",895*/},{\n\n0x45,0xF6,0xAC,0x10,0x94,0xDF,0x94,0x10,0xFF,0x10,0x60,0x00,0x0F,0x00,0x04,0x04,\n0x03,0x02,0x02,0x0F,0x00,0x00,/*\"褂\",896*/},{\n\n0x48,0x48,0x4A,0xFA,0x0A,0xFE,0x09,0xF9,0x49,0x28,0x88,0x02,0x02,0x01,0x03,0x00,\n0x0F,0x00,0x01,0x02,0x02,0x03,/*\"乖\",897*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0x9E,0x92,0xF2,0x92,0x92,0x9E,0x00,0x08,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x08,0x08,0x07,/*\"拐\",898*/},{\n\n0x78,0x00,0xFF,0x08,0x52,0x46,0x2A,0xD2,0x2A,0x46,0x40,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"怪\",899*/},{\n\n0x88,0x68,0xFF,0x48,0x0C,0xF4,0x54,0x55,0x56,0x74,0x0C,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"棺\",900*/},{\n\n0xFF,0x05,0x6F,0x54,0x68,0x00,0x68,0x54,0x6F,0x05,0xFF,0x0F,0x00,0x03,0x0A,0x07,\n0x00,0x0F,0x02,0x03,0x08,0x0F,/*\"關\",901*/},{\n\n0x0C,0x04,0xF4,0x54,0x55,0x56,0x54,0x54,0x74,0x04,0x0C,0x00,0x00,0x0F,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"官\",902*/},{\n\n0x46,0xCA,0x4A,0xCA,0x42,0x02,0x52,0x92,0x12,0xFA,0x16,0x08,0x07,0x00,0x07,0x08,\n0x08,0x08,0x08,0x0A,0x0B,0x0C,/*\"冠\",903*/},{\n\n0xBA,0xEF,0xBA,0xC2,0xBA,0xAF,0xBA,0x00,0xFF,0x95,0xFF,0x00,0x0F,0x0A,0x0A,0x0F,\n0x0A,0x0A,0x00,0x08,0x07,0x0C,/*\"觀\",904*/},{\n\n0x1C,0x0B,0xEA,0xAE,0xAA,0xAC,0xAB,0xAA,0xEE,0x0A,0x1A,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"管\",905*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x0C,0xF4,0x55,0x56,0x74,0x0C,0x00,0x0F,0x04,0x02,0x04,\n0x00,0x0F,0x05,0x05,0x05,0x0F,/*\"館\",906*/},{\n\n0x48,0x47,0xFC,0x44,0xBA,0xEF,0xBA,0xC2,0xBA,0xAF,0xBA,0x0F,0x08,0x07,0x05,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"罐\",907*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0xDF,0x55,0xDF,0x55,0xDF,0x04,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x07,0x0B,0x00,/*\"慣\",908*/},{\n\n0x22,0x44,0x00,0xBA,0xEF,0xBA,0xC2,0xBA,0xAF,0xBA,0x82,0x04,0x02,0x01,0x00,0x0F,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"灌\",909*/},{\n\n0x04,0xDF,0x55,0xD5,0x55,0x5F,0xD5,0x55,0x55,0xDF,0x04,0x00,0x0B,0x06,0x02,0x03,\n0x02,0x02,0x03,0x06,0x0B,0x00,/*\"貫\",910*/},{\n\n0x20,0x22,0x24,0xE8,0x20,0x3F,0x20,0xE8,0x24,0x22,0x20,0x08,0x04,0x02,0x01,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"光\",911*/},{\n\n0x00,0xFE,0x22,0xEA,0xBE,0xAA,0xEB,0xAA,0xBE,0xEA,0x22,0x08,0x07,0x00,0x0B,0x06,\n0x02,0x03,0x02,0x06,0x0B,0x00,/*\"廣\",912*/},{\n\n0x11,0xF2,0x00,0x45,0x22,0xFD,0x02,0x22,0xFE,0x22,0x02,0x08,0x07,0x08,0x0A,0x0A,\n0x09,0x0A,0x0A,0x0B,0x0A,0x0A,/*\"逛\",913*/},{\n\n0x22,0xFE,0x22,0x00,0x7C,0x54,0xF6,0x5D,0xD4,0x7C,0x00,0x04,0x07,0x02,0x08,0x04,\n0x03,0x00,0x07,0x0A,0x0B,0x0C,/*\"瑰\",914*/},{\n\n0x40,0x48,0xFF,0x48,0x40,0xFE,0xAA,0xAA,0xAA,0xFE,0x00,0x08,0x06,0x01,0x06,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"規\",915*/},{\n\n0x20,0x24,0x24,0x24,0x24,0xBF,0x24,0x24,0x24,0x24,0x20,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"圭\",916*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x24,0x24,0xBF,0x24,0x24,0x20,0x00,0x07,0x02,0x07,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"硅\",917*/},{\n\n0xFE,0xAB,0xAA,0xEE,0xC0,0x55,0x55,0xD5,0x55,0x5F,0xC0,0x0E,0x08,0x0F,0x0A,0x00,\n0x07,0x01,0x0F,0x05,0x07,0x00,/*\"歸\",918*/},{\n\n0xA0,0xAE,0xEA,0x8A,0xFB,0x02,0xFA,0xAA,0x6A,0x2E,0xE0,0x0A,0x0A,0x0F,0x02,0x07,\n0x08,0x0F,0x0A,0x0B,0x0A,0x0B,/*\"龜\",919*/},{\n\n0xFF,0x15,0x95,0xBF,0xA0,0xF0,0xA0,0xBF,0x95,0x15,0xFF,0x0F,0x00,0x08,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x08,0x00,0x0F,/*\"閨\",920*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x08,0xFF,0x08,0xF8,0x00,0x00,0x02,0x02,0x0F,0x02,0x0A,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"軌\",921*/},{\n\n0x00,0x7C,0x54,0x54,0xD6,0x7D,0x54,0x54,0xD4,0x7C,0x00,0x08,0x08,0x04,0x02,0x01,\n0x07,0x0A,0x0B,0x0A,0x0B,0x0C,/*\"鬼\",922*/},{\n\n0x54,0x55,0x56,0x54,0x08,0xF4,0x13,0xD2,0x5A,0x56,0xD0,0x0F,0x05,0x05,0x07,0x08,\n0x07,0x00,0x07,0x08,0x09,0x0D,/*\"詭\",923*/},{\n\n0x20,0x15,0x29,0x25,0x23,0xE0,0x20,0x23,0x2C,0x12,0x28,0x00,0x09,0x09,0x05,0x03,\n0x01,0x01,0x03,0x05,0x09,0x00,/*\"癸\",924*/},{\n\n0x88,0x68,0xFF,0x48,0x20,0x24,0x24,0xBF,0x24,0x24,0x20,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"桂\",925*/},{\n\n0xC8,0xFF,0x48,0xFF,0x11,0xFD,0x55,0x5F,0x55,0xFD,0x11,0x00,0x0F,0x00,0x0F,0x08,\n0x0D,0x0B,0x09,0x0B,0x0D,0x08,/*\"櫃\",926*/},{\n\n0x9E,0x12,0xF2,0x5E,0x08,0xF4,0x13,0xD2,0x5A,0x56,0xD0,0x07,0x04,0x03,0x02,0x08,\n0x07,0x00,0x07,0x08,0x09,0x0D,/*\"跪\",927*/},{\n\n0x20,0xEE,0xAA,0xAA,0xAA,0xBF,0xAA,0xAA,0xAA,0xEE,0x20,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"貴\",928*/},{\n\n0xF4,0xB2,0xD5,0xF5,0xD5,0xB2,0xF4,0x00,0xFC,0x00,0xFF,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x00,0x00,0x01,0x08,0x0F,/*\"劊\",929*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xDF,0x15,0xD5,0x9F,0x40,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x09,0x07,0x08,0x0E,/*\"輥\",930*/},{\n\n0x22,0x44,0x00,0x0A,0x76,0x52,0xD2,0x53,0x52,0x76,0x8A,0x04,0x02,0x00,0x04,0x02,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"滾\",931*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xDF,0x95,0x15,0xD5,0x15,0x9F,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x00,0x07,0x09,0x0C,/*\"棍\",932*/},{\n\n0x4A,0xF9,0x4A,0x00,0xE0,0x3F,0xA5,0xBD,0xA1,0x3F,0xE0,0x0A,0x0F,0x05,0x00,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"鍋\",933*/},{\n\n0x02,0xBA,0xAA,0xAB,0xAA,0x3A,0x00,0xFE,0x02,0x32,0xCE,0x02,0x02,0x0A,0x0E,0x03,\n0x02,0x00,0x0F,0x02,0x02,0x01,/*\"郭\",934*/},{\n\n0xFF,0x05,0x75,0x55,0x75,0x05,0x7F,0x85,0x77,0x05,0xFF,0x0F,0x0A,0x0A,0x09,0x09,\n0x0C,0x0A,0x09,0x0A,0x0C,0x0F,/*\"國\",935*/},{\n\n0x80,0xBE,0xAA,0xAA,0xAA,0xFE,0xAA,0xAA,0xAA,0xBE,0x80,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"果\",936*/},{\n\n0x82,0xBE,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xBE,0x82,0x08,0x0A,0x05,0x0C,0x0A,\n0x01,0x02,0x04,0x05,0x0A,0x08,/*\"裹\",937*/},{\n\n0x10,0x11,0xF2,0x00,0xF0,0x1F,0xD5,0x5D,0xD1,0x1F,0xF0,0x08,0x04,0x03,0x04,0x0B,\n0x08,0x09,0x09,0x09,0x0A,0x0B,/*\"過\",938*/},{\n\n0xFC,0x04,0x04,0xFC,0x10,0xA8,0xA4,0xA3,0xA4,0xA8,0x10,0x03,0x01,0x01,0x03,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"哈\",939*/},{\n\n0x18,0xEF,0xA9,0xA9,0xEF,0x18,0x34,0xAD,0x66,0x24,0x94,0x00,0x0F,0x02,0x0A,0x0F,\n0x00,0x09,0x04,0x02,0x05,0x08,/*\"骸\",940*/},{\n\n0x82,0x82,0xF2,0x4E,0x00,0x24,0x34,0xAD,0x66,0x24,0x94,0x00,0x08,0x0F,0x00,0x08,\n0x09,0x09,0x04,0x02,0x05,0x08,/*\"孩\",941*/},{\n\n0x11,0x22,0x48,0xC4,0x7B,0x4A,0x6A,0x4A,0x4A,0xFA,0x42,0x04,0x02,0x00,0x03,0x02,\n0x02,0x03,0x0A,0x0A,0x07,0x02,/*\"海\",942*/},{\n\n0x44,0xD2,0x55,0x75,0xD5,0x55,0x55,0x15,0xF5,0x01,0x00,0x05,0x05,0x0B,0x09,0x04,\n0x02,0x05,0x08,0x03,0x04,0x0E,/*\"氦\",943*/},{\n\n0x04,0x24,0x34,0xAC,0xA5,0x66,0x24,0x94,0x44,0x04,0x04,0x08,0x09,0x09,0x04,0x04,\n0x02,0x01,0x02,0x04,0x08,0x00,/*\"亥\",944*/},{\n\n0x86,0xAA,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xAA,0x86,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0B,0x0A,0x0A,0x0A,0x0E,0x00,/*\"害\",945*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x24,0x34,0xAD,0x66,0x24,0x94,0x06,0x00,0x0A,0x08,0x07,\n0x09,0x09,0x04,0x02,0x05,0x08,/*\"駭\",946*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x04,0xFF,0x44,0x44,0xFF,0x04,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"酣\",947*/},{\n\n0x04,0xFD,0x55,0x57,0xFC,0x94,0x08,0xB7,0x44,0xBC,0x04,0x09,0x05,0x01,0x05,0x0B,\n0x0C,0x09,0x0C,0x00,0x04,0x09,/*\"憨\",948*/},{\n\n0x04,0xFF,0x44,0x44,0xFF,0x04,0x00,0xFE,0x02,0x32,0xCE,0x00,0x0F,0x04,0x04,0x0F,\n0x00,0x00,0x0F,0x02,0x02,0x01,/*\"邯\",949*/},{\n\n0xFA,0xAA,0xAF,0xAA,0xFA,0x08,0x3A,0xAE,0xEB,0xBE,0x88,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x03,0x02,0x0F,0x02,0x02,/*\"韓\",950*/},{\n\n0x10,0x10,0x28,0x24,0x2A,0x31,0xA2,0x64,0x08,0x10,0x10,0x00,0x0F,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0F,0x00,/*\"含\",951*/},{\n\n0x11,0x22,0xF8,0x01,0x11,0xA1,0xF9,0xA5,0x13,0x00,0xF8,0x04,0x02,0x0F,0x08,0x09,\n0x0C,0x0F,0x08,0x09,0x08,0x0F,/*\"涵\",952*/},{\n\n0x86,0xAA,0xAA,0xFE,0xAA,0xAB,0xAA,0xFE,0xAA,0xAA,0x86,0x04,0x02,0x01,0x04,0x04,\n0x09,0x0A,0x00,0x01,0x02,0x04,/*\"寒\",953*/},{\n\n0xFC,0x01,0x89,0x51,0x01,0xF9,0x05,0x53,0x89,0x00,0xFC,0x0F,0x08,0x08,0x08,0x0A,\n0x0B,0x08,0x08,0x08,0x08,0x0F,/*\"函\",954*/},{\n\n0xFC,0x04,0xFC,0x00,0xFC,0x54,0xD4,0x04,0xFF,0x84,0x65,0x03,0x01,0x03,0x08,0x07,\n0x02,0x0B,0x04,0x03,0x05,0x0E,/*\"喊\",955*/},{\n\n0x06,0x12,0x2A,0x26,0x22,0xE2,0x22,0x26,0x2A,0x12,0x06,0x01,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"罕\",956*/},{\n\n0xFA,0xAF,0xFA,0x48,0x94,0xF2,0x01,0x52,0x94,0xF8,0x08,0x02,0x0F,0x02,0x02,0x09,\n0x0F,0x00,0x02,0x09,0x0F,0x00,/*\"翰\",957*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0xAA,0xEA,0x82,0x7F,0xA2,0xDB,0x08,0x0F,0x00,0x02,0x09,\n0x04,0x09,0x0A,0x08,0x04,0x09,/*\"撼\",958*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0x5F,0x55,0xD5,0x55,0x5F,0x00,0x00,0x08,0x0F,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"捍\",959*/},{\n\n0x00,0x5F,0x55,0x55,0x55,0xD5,0x55,0x55,0x55,0x5F,0x00,0x01,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"旱\",960*/},{\n\n0x78,0x00,0xFF,0x04,0xFE,0xAA,0xEA,0x82,0x7F,0xA2,0xDB,0x00,0x00,0x0F,0x02,0x09,\n0x04,0x09,0x0A,0x08,0x04,0x09,/*\"憾\",961*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0x5F,0x55,0xD5,0x55,0x5F,0x00,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"悍\",962*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0x5F,0x55,0xD5,0x55,0x5F,0x00,0x08,0x06,0x01,0x02,0x05,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"焊\",963*/},{\n\n0x11,0x22,0x40,0x42,0x42,0x42,0xFE,0x42,0x42,0x42,0x40,0x04,0x02,0x01,0x00,0x00,\n0x00,0x0F,0x00,0x00,0x00,0x00,/*\"汗\",964*/},{\n\n0x22,0x44,0x02,0xE2,0xAF,0xAA,0xFA,0xAA,0xAF,0xE2,0x02,0x04,0x02,0x02,0x0A,0x0A,\n0x06,0x03,0x06,0x0A,0x0A,0x02,/*\"漢\",965*/},{\n\n0x44,0x44,0xA4,0x94,0xEC,0x87,0x8C,0x94,0xA4,0x44,0x44,0x00,0x08,0x04,0x02,0x01,\n0x00,0x08,0x08,0x07,0x00,0x00,/*\"夯\",966*/},{\n\n0x88,0x68,0xFF,0x48,0x04,0xE4,0x25,0x26,0xE4,0x04,0x04,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"杭\",967*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x04,0xE4,0x25,0xE6,0x04,0x04,0x08,0x07,0x01,0x0A,0x0F,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"航\",968*/},{\n\n0x08,0xFF,0x08,0x62,0xBA,0xAA,0xAB,0xAA,0xAA,0xBA,0x62,0x02,0x03,0x01,0x0A,0x0A,\n0x05,0x0B,0x0E,0x02,0x04,0x0A,/*\"壕\",969*/},{\n\n0xFC,0x04,0xFC,0x62,0xBA,0xAA,0xAB,0xAA,0xAA,0xBA,0x62,0x03,0x01,0x03,0x0A,0x0A,\n0x05,0x0B,0x0E,0x02,0x04,0x0A,/*\"嚎\",970*/},{\n\n0x62,0xA2,0xBA,0xAA,0xAA,0xAB,0xAA,0xAA,0xBA,0xA2,0x62,0x00,0x0A,0x0A,0x09,0x05,\n0x0A,0x0C,0x02,0x04,0x0A,0x08,/*\"豪\",971*/},{\n\n0x62,0x22,0xBA,0xAA,0xAA,0xAB,0x6A,0x6A,0x3A,0x22,0x62,0x00,0x08,0x0A,0x0A,0x0A,\n0x07,0x0D,0x0D,0x09,0x08,0x0C,/*\"毫\",972*/},{\n\n0x20,0xA4,0xE4,0x3F,0xE4,0xA4,0x20,0xFE,0x02,0x32,0xCE,0x09,0x04,0x03,0x08,0x0F,\n0x00,0x03,0x0F,0x02,0x02,0x01,/*\"郝\",973*/},{\n\n0x88,0x78,0x0F,0x88,0x78,0x42,0x42,0xF2,0x4A,0x46,0x40,0x08,0x05,0x02,0x05,0x08,\n0x00,0x08,0x0F,0x00,0x00,0x00,/*\"好\",974*/},{\n\n0x44,0x54,0xFF,0x54,0x44,0x92,0x92,0xFE,0x49,0x49,0x40,0x02,0x01,0x0F,0x01,0x02,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"耗\",975*/},{\n\n0xAF,0x69,0x29,0x2F,0x00,0xF8,0x48,0x7F,0xAA,0xAA,0xD8,0x01,0x09,0x09,0x07,0x02,\n0x09,0x06,0x02,0x06,0x08,0x0C,/*\"號\",976*/},{\n\n0x22,0x44,0x00,0x28,0xA6,0xA4,0xA4,0xBF,0xA4,0xA4,0x20,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"浩\",977*/},{\n\n0xFE,0x02,0xFE,0x00,0xF2,0x12,0x12,0xF2,0x02,0xFE,0x02,0x03,0x01,0x03,0x00,0x03,\n0x01,0x01,0x09,0x08,0x0F,0x00,/*\"呵\",978*/},{\n\n0xFE,0x02,0xFE,0x80,0x5F,0x75,0x55,0xD5,0x55,0x5F,0xC0,0x03,0x01,0x03,0x00,0x06,\n0x04,0x05,0x04,0x01,0x08,0x0F,/*\"喝\",979*/},{\n\n0x42,0xE2,0x1A,0x07,0xEA,0x2A,0x2A,0xEF,0x0A,0xFA,0x0A,0x00,0x0F,0x00,0x00,0x03,\n0x01,0x01,0x09,0x08,0x0F,0x00,/*\"荷\",980*/},{\n\n0x4A,0x92,0x02,0xD7,0x52,0x52,0x52,0xD7,0x12,0xF2,0x12,0x08,0x04,0x00,0x07,0x02,\n0x02,0x02,0x0B,0x08,0x0F,0x00,/*\"菏\",981*/},{\n\n0x88,0x68,0xFF,0x48,0x24,0x34,0xAD,0x66,0x24,0x94,0x44,0x00,0x00,0x0F,0x00,0x09,\n0x09,0x04,0x02,0x03,0x04,0x08,/*\"核\",982*/},{\n\n0x10,0x10,0x12,0xD2,0x32,0xFE,0x31,0xD1,0x11,0x10,0x10,0x04,0x02,0x01,0x00,0x00,\n0x0F,0x00,0x00,0x01,0x02,0x04,/*\"禾\",983*/},{\n\n0x10,0x92,0x52,0xFE,0x51,0x90,0xFC,0x04,0x04,0x04,0xFC,0x01,0x00,0x00,0x0F,0x00,\n0x00,0x07,0x02,0x02,0x02,0x07,/*\"和\",984*/},{\n\n0x10,0xFC,0x03,0x00,0xF2,0x12,0x12,0xF2,0x02,0xFE,0x02,0x00,0x0F,0x00,0x00,0x03,\n0x01,0x01,0x09,0x08,0x0F,0x00,/*\"何\",985*/},{\n\n0x10,0x90,0xA8,0xA4,0xA2,0xA1,0xA2,0xA4,0xA8,0x90,0x10,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"合\",986*/},{\n\n0x08,0x08,0xE4,0xAC,0xAA,0xA9,0xAA,0xAC,0xE4,0x08,0x08,0x08,0x0E,0x0A,0x0A,0x0E,\n0x0A,0x0E,0x0A,0x0A,0x0E,0x08,/*\"盒\",987*/},{\n\n0xA4,0xAA,0x55,0xE8,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x02,0x0A,0x09,0x07,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"貉\",988*/},{\n\n0xFF,0x15,0x55,0xDF,0x40,0x60,0xC0,0x5F,0x55,0x15,0xFF,0x0F,0x00,0x05,0x05,0x0B,\n0x09,0x04,0x02,0x05,0x08,0x0F,/*\"閡\",989*/},{\n\n0x10,0x22,0x04,0x00,0xF2,0x12,0x12,0xF2,0x02,0xFE,0x02,0x04,0x02,0x01,0x00,0x03,\n0x01,0x01,0x09,0x08,0x0F,0x00,/*\"河\",990*/},{\n\n0x11,0x22,0x00,0xFF,0x09,0xE9,0x3F,0x29,0xE9,0x09,0xFF,0x04,0x02,0x00,0x0F,0x04,\n0x05,0x05,0x05,0x05,0x04,0x0F,/*\"涸\",991*/},{\n\n0xA4,0xE4,0x3F,0xE4,0xA4,0x00,0xA4,0xE4,0x3F,0xE4,0x24,0x08,0x07,0x08,0x0F,0x00,\n0x01,0x08,0x07,0x08,0x0F,0x01,/*\"赫\",992*/},{\n\n0x84,0x45,0xF6,0xAC,0x00,0x9F,0x75,0xD5,0x55,0x5F,0xC0,0x00,0x00,0x0F,0x00,0x01,\n0x06,0x05,0x04,0x0D,0x08,0x07,/*\"褐\",993*/},{\n\n0x26,0xFA,0x56,0xFB,0x52,0x56,0x00,0xFE,0xAB,0xBE,0xA0,0x00,0x0F,0x05,0x07,0x05,\n0x05,0x00,0x08,0x06,0x08,0x0F,/*\"鶴\",994*/},{\n\n0x12,0xEA,0xA7,0xA2,0xAA,0xAE,0xA0,0xAE,0xAA,0xEA,0x0E,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"賀\",995*/},{\n\n0xFE,0x02,0xFE,0x00,0x5F,0x55,0x51,0xFF,0x51,0x55,0x5F,0x03,0x01,0x03,0x00,0x0D,\n0x01,0x0D,0x01,0x0D,0x01,0x0D,/*\"嘿\",996*/},{\n\n0x00,0x5F,0x51,0x55,0x51,0xFF,0x51,0x55,0x51,0x5F,0x00,0x09,0x05,0x01,0x05,0x09,\n0x01,0x05,0x09,0x01,0x05,0x09,/*\"黑\",997*/},{\n\n0x08,0x90,0xFE,0x02,0xFA,0xAA,0xAB,0xAA,0xAA,0xFA,0x02,0x09,0x04,0x03,0x00,0x0F,\n0x04,0x01,0x02,0x04,0x0A,0x09,/*\"痕\",998*/},{\n\n0x48,0x24,0xF2,0x09,0x00,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"很\",999*/},{\n\n0x10,0x8A,0x44,0xFB,0x00,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x01,0x08,0x08,0x07,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"狠\",1000*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"恨\",1001*/},{\n\n0xFC,0x04,0xFC,0x02,0xBA,0xAA,0xAA,0xAB,0xAA,0xBA,0x02,0x03,0x01,0x03,0x00,0x00,\n0x00,0x08,0x0E,0x01,0x00,0x00,/*\"哼\",1002*/},{\n\n0x02,0x82,0xBA,0xAA,0xAA,0xAB,0xAA,0xAA,0xBA,0x82,0x02,0x00,0x00,0x00,0x08,0x08,\n0x0E,0x02,0x01,0x01,0x00,0x00,/*\"亨\",1003*/},{\n\n0x88,0x68,0xFF,0x48,0x22,0xE2,0xAF,0xEA,0xAF,0xE2,0x22,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x03,0x06,0x0B,0x00,/*\"橫\",1004*/},{\n\n0x24,0xF2,0x09,0xFC,0xAB,0xFA,0xAE,0xF8,0x12,0xF2,0x12,0x00,0x0F,0x00,0x0A,0x06,\n0x03,0x06,0x0A,0x08,0x0F,0x00,/*\"衡\",1005*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0xC2,0x3E,0x12,0x52,0x92,0xF2,0x00,0x00,0x0F,0x00,0x00,\n0x09,0x08,0x09,0x0A,0x0F,0x08,/*\"恆\",1006*/},{\n\n0xA0,0xA2,0xBE,0xEA,0xAA,0xFF,0xAA,0xEA,0xBE,0xA2,0xA0,0x04,0x07,0x04,0x0F,0x04,\n0x07,0x04,0x0F,0x04,0x07,0x04,/*\"轟\",1007*/},{\n\n0xFE,0x02,0xFE,0x80,0x88,0xFF,0x88,0x88,0xFF,0x88,0x80,0x03,0x01,0x03,0x08,0x04,\n0x02,0x00,0x00,0x02,0x04,0x08,/*\"哄\",1008*/},{\n\n0x78,0x00,0xFF,0x08,0x84,0x88,0xFF,0x88,0xFF,0x88,0x80,0x08,0x06,0x01,0x06,0x08,\n0x04,0x02,0x00,0x02,0x04,0x08,/*\"烘\",1009*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x02,0x02,0xFE,0x02,0x02,0x00,0x04,0x04,0x03,0x02,0x0B,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"虹\",1010*/},{\n\n0x22,0x44,0x02,0xFE,0x02,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x04,0x02,0x04,0x07,0x02,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鴻\",1011*/},{\n\n0x10,0x21,0x02,0x80,0x88,0xFF,0x88,0x88,0xFF,0x88,0x80,0x04,0x02,0x01,0x08,0x04,\n0x02,0x00,0x00,0x02,0x04,0x08,/*\"洪\",1012*/},{\n\n0x2C,0x24,0x24,0xE4,0x3D,0x26,0xA4,0x24,0x24,0x24,0x2C,0x08,0x04,0x03,0x08,0x0C,\n0x0A,0x09,0x08,0x0A,0x0C,0x08,/*\"宏\",1013*/},{\n\n0xF2,0x92,0x92,0x9E,0x00,0x00,0xE0,0x1F,0x00,0x00,0x00,0x00,0x08,0x08,0x07,0x00,\n0x06,0x05,0x04,0x04,0x05,0x0E,/*\"弘\",1014*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x02,0x02,0xFE,0x02,0x02,0x00,0x0C,0x02,0x04,0x02,0x0C,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"紅\",1015*/},{\n\n0xFC,0x04,0xFC,0x10,0xFC,0x03,0x48,0x3A,0xEA,0x2E,0x28,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x09,0x05,0x03,0x05,0x09,/*\"喉\",1016*/},{\n\n0x20,0x10,0xFC,0x03,0x48,0x3A,0x2A,0xEA,0x2E,0x28,0x08,0x00,0x00,0x0F,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"侯\",1017*/},{\n\n0x8A,0x44,0xFB,0x10,0xFC,0x03,0x48,0x3A,0xEA,0x2E,0x28,0x08,0x08,0x07,0x00,0x0F,\n0x00,0x09,0x05,0x03,0x05,0x09,/*\"猴\",1018*/},{\n\n0xFC,0x04,0xFC,0x80,0x82,0xFA,0x26,0x10,0xFF,0x00,0x00,0x03,0x01,0x03,0x00,0x08,\n0x0F,0x00,0x00,0x07,0x08,0x0E,/*\"吼\",1019*/},{\n\n0x00,0xFF,0x01,0x5F,0x55,0x55,0x55,0xD5,0xD5,0x5F,0x01,0x08,0x07,0x02,0x02,0x02,\n0x0A,0x0F,0x02,0x02,0x02,0x02,/*\"厚\",1020*/},{\n\n0x20,0x10,0xFC,0x03,0xFC,0x48,0x3A,0x2A,0xEA,0x2E,0x08,0x00,0x00,0x0F,0x00,0x03,\n0x08,0x09,0x05,0x03,0x05,0x09,/*\"候\",1021*/},{\n\n0x48,0x24,0xF2,0x09,0x20,0x24,0xF6,0xAD,0xA4,0xB2,0x60,0x00,0x00,0x0F,0x00,0x0A,\n0x09,0x0A,0x04,0x0A,0x09,0x08,/*\"後\",1022*/},{\n\n0xFE,0x02,0xFE,0x00,0x4A,0x52,0x42,0xFE,0x41,0x51,0x49,0x03,0x01,0x03,0x00,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"呼\",1023*/},{\n\n0x40,0x4A,0x52,0x42,0x42,0xFE,0x41,0x41,0x51,0x49,0x40,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"乎\",1024*/},{\n\n0x08,0x44,0x23,0x12,0x4E,0x22,0x12,0x4E,0x42,0x42,0x3E,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"忽\",1025*/},{\n\n0x22,0xFE,0x22,0x00,0xE4,0x3F,0xE4,0x00,0xFE,0x92,0xFE,0x04,0x07,0x02,0x00,0x07,\n0x02,0x03,0x08,0x07,0x08,0x0F,/*\"瑚\",1026*/},{\n\n0x62,0xAA,0xAA,0xAA,0xEA,0x2F,0xEA,0xAA,0xAA,0xAA,0x62,0x08,0x0B,0x0A,0x0A,0x0E,\n0x08,0x0E,0x0A,0x0A,0x0B,0x08,/*\"壺\",1027*/},{\n\n0xA2,0xA2,0xFA,0xA7,0xA2,0x02,0xF2,0x57,0x52,0x52,0xF2,0x0F,0x04,0x04,0x04,0x07,\n0x08,0x07,0x01,0x01,0x09,0x0F,/*\"葫\",1028*/},{\n\n0xE4,0x24,0x3F,0x24,0xE4,0x00,0xFE,0x92,0x92,0x92,0xFE,0x07,0x02,0x02,0x02,0x0B,\n0x04,0x03,0x00,0x08,0x08,0x0F,/*\"胡\",1029*/},{\n\n0x78,0x48,0xFF,0x48,0xE4,0x3F,0xE4,0x00,0xFE,0x92,0xFE,0x04,0x04,0x03,0x02,0x07,\n0x02,0x03,0x08,0x07,0x08,0x0F,/*\"蝴\",1030*/},{\n\n0x8A,0x44,0xFB,0x00,0xFE,0x02,0xFE,0x02,0xFD,0x01,0x00,0x08,0x08,0x07,0x08,0x07,\n0x00,0x0F,0x0A,0x0C,0x03,0x04,/*\"狐\",1031*/},{\n\n0x24,0xA8,0xFF,0xA8,0xE4,0x3F,0xE4,0x00,0xFF,0x89,0xFF,0x01,0x00,0x0F,0x00,0x07,\n0x02,0x0B,0x04,0x03,0x08,0x0F,/*\"糊\",1032*/},{\n\n0x22,0x44,0x00,0xE4,0x3F,0xE4,0x00,0xFE,0x92,0x92,0xFE,0x04,0x02,0x00,0x07,0x02,\n0x03,0x08,0x07,0x00,0x08,0x0F,/*\"湖\",1033*/},{\n\n0xF2,0x92,0x9E,0x00,0xFE,0x02,0xFE,0x02,0xFD,0x01,0x00,0x08,0x08,0x07,0x08,0x07,\n0x00,0x0F,0x0A,0x0C,0x03,0x04,/*\"弧\",1034*/},{\n\n0x00,0xF8,0x48,0x48,0x48,0x7F,0xAA,0xAA,0xAA,0x8A,0xD8,0x08,0x07,0x08,0x08,0x06,\n0x02,0x02,0x02,0x06,0x08,0x0C,/*\"虎\",1035*/},{\n\n0xFC,0x04,0xFC,0x00,0xF8,0x48,0x48,0x7F,0xAA,0xAA,0xD8,0x03,0x01,0x03,0x08,0x07,\n0x08,0x07,0x01,0x07,0x08,0x0C,/*\"唬\",1036*/},{\n\n0x55,0x56,0x54,0x20,0xFA,0x57,0x52,0xF6,0x5A,0x57,0x52,0x0F,0x05,0x0F,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"護\",1037*/},{\n\n0x02,0xC2,0x3E,0x12,0x12,0x12,0x12,0x12,0xF2,0x02,0x02,0x08,0x09,0x09,0x09,0x09,\n0x09,0x09,0x0F,0x08,0x08,0x08,/*\"互\",1038*/},{\n\n0x22,0x44,0x00,0xFE,0x0A,0xBA,0xAA,0xAB,0xAA,0xBA,0x0E,0x04,0x02,0x08,0x07,0x00,\n0x07,0x0A,0x0B,0x0A,0x0B,0x0C,/*\"滬\",1039*/},{\n\n0x00,0x00,0xFE,0x4A,0x4A,0x4A,0x4A,0x49,0x49,0x49,0xF8,0x08,0x06,0x01,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"戶\",1040*/},{\n\n0x82,0x42,0xE2,0x17,0x02,0x02,0xF2,0x87,0x42,0x22,0x02,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x07,0x08,0x08,0x08,0x0E,/*\"花\",1041*/},{\n\n0x55,0x56,0x54,0x00,0xAA,0xFA,0xAF,0xFA,0xAF,0xFA,0xAA,0x0F,0x05,0x0F,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"譁\",1042*/},{\n\n0x22,0xAA,0xFA,0xAF,0xAA,0xFA,0xAA,0xAF,0xFA,0xAA,0x22,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"華\",1043*/},{\n\n0x8A,0x44,0xFB,0x30,0xDF,0x55,0x55,0x5D,0x51,0xDF,0x30,0x08,0x08,0x07,0x00,0x0F,\n0x05,0x05,0x05,0x0D,0x0F,0x00,/*\"猾\",1044*/},{\n\n0x11,0x22,0x30,0xDF,0x55,0x55,0x5D,0x51,0x51,0xDF,0x30,0x04,0x02,0x00,0x0F,0x05,\n0x05,0x05,0x05,0x0D,0x0F,0x00,/*\"滑\",1045*/},{\n\n0x08,0x2A,0xEA,0xAA,0xAA,0xFF,0xAA,0xAA,0xEA,0x3E,0x28,0x08,0x08,0x0B,0x0A,0x0A,\n0x0B,0x0A,0x0A,0x0B,0x08,0x08,/*\"畫\",1046*/},{\n\n0x08,0xAA,0xAA,0xBF,0xAA,0xBE,0x28,0x08,0xFC,0x00,0xFF,0x08,0x0F,0x0A,0x0F,0x0A,\n0x0F,0x08,0x08,0x01,0x08,0x0F,/*\"劃\",1047*/},{\n\n0x20,0x10,0xFC,0x03,0x00,0x80,0xFF,0x20,0x10,0x08,0x04,0x00,0x00,0x0F,0x00,0x01,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"化\",1048*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x92,0x92,0xFE,0x91,0x91,0x10,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"話\",1049*/},{\n\n0x88,0x68,0xFF,0x48,0xFC,0x54,0xF6,0x5D,0xD4,0x7C,0x00,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x07,0x0A,0x0B,0x0C,/*\"槐\",1050*/},{\n\n0x48,0x24,0xF2,0x09,0xFE,0x02,0xF2,0x92,0xF2,0x02,0xFE,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"徊\",1051*/},{\n\n0x78,0x00,0xFF,0x04,0x7A,0xAA,0x3A,0xEB,0x3A,0xAA,0x7A,0x00,0x00,0x0F,0x00,0x05,\n0x02,0x0F,0x08,0x03,0x04,0x0B,/*\"懷\",1052*/},{\n\n0x10,0x21,0x02,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x04,0x04,0x02,0x01,0x00,0x0F,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"淮\",1053*/},{\n\n0x10,0xFF,0x10,0x00,0x7A,0xAA,0x3A,0xEB,0x3A,0xAA,0x7A,0x04,0x07,0x02,0x04,0x05,\n0x02,0x0F,0x08,0x03,0x04,0x0B,/*\"壞\",1054*/},{\n\n0xBA,0xEF,0xBA,0xC2,0xBA,0xAF,0xBA,0x10,0x0F,0xC4,0x1C,0x00,0x0F,0x0A,0x0A,0x0F,\n0x0A,0x0A,0x08,0x06,0x01,0x0E,/*\"歡\",1055*/},{\n\n0x22,0xFE,0x22,0x10,0xD7,0x55,0x57,0x55,0x57,0x55,0xD7,0x04,0x07,0x02,0x08,0x05,\n0x0F,0x09,0x01,0x03,0x05,0x0B,/*\"環\",1056*/},{\n\n0x88,0x68,0xFF,0x48,0x02,0xFA,0x4A,0x4A,0x4A,0xFA,0x02,0x00,0x00,0x0F,0x00,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"桓\",1057*/},{\n\n0x21,0xE2,0x10,0xD7,0x55,0x57,0x55,0x57,0x55,0xD7,0x10,0x08,0x07,0x08,0x0D,0x0B,\n0x0F,0x0D,0x09,0x0B,0x0D,0x0A,/*\"還\",1058*/},{\n\n0xDC,0xB3,0xC8,0x00,0x56,0x5A,0xD6,0x7A,0x52,0x59,0x55,0x0E,0x00,0x06,0x00,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"緩\",1059*/},{\n\n0x84,0xFF,0x44,0x08,0x7C,0x2B,0x1A,0xCA,0x1E,0x28,0x78,0x08,0x0F,0x00,0x00,0x09,\n0x09,0x05,0x03,0x05,0x09,0x09,/*\"換\",1060*/},{\n\n0x00,0xE0,0xAE,0xAA,0xAA,0xFF,0xAA,0xAA,0xAE,0xE0,0x00,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"患\",1061*/},{\n\n0xFE,0x02,0xFE,0x08,0x7C,0x2B,0x1A,0xCA,0x1E,0x28,0x78,0x03,0x01,0x03,0x00,0x09,\n0x09,0x05,0x03,0x05,0x09,0x09,/*\"喚\",1062*/},{\n\n0x88,0xFE,0x22,0xF2,0xAE,0x6A,0x2B,0x6A,0xBA,0xE2,0x02,0x08,0x07,0x0A,0x0A,0x06,\n0x03,0x02,0x02,0x06,0x0A,0x0A,/*\"瘓\",1063*/},{\n\n0x48,0x2A,0x9B,0xAA,0x6E,0xAB,0x2A,0x2A,0x9B,0x2A,0x48,0x00,0x0A,0x0A,0x0A,0x05,\n0x0A,0x0F,0x01,0x02,0x04,0x00,/*\"豢\",1064*/},{\n\n0x78,0x00,0xFF,0x08,0x7C,0x2B,0x1A,0xCA,0x1E,0x28,0x78,0x08,0x06,0x01,0x06,0x09,\n0x09,0x05,0x03,0x05,0x09,0x09,/*\"煥\",1065*/},{\n\n0x22,0x44,0x08,0x7C,0x2B,0x1A,0xCA,0x1E,0x28,0x78,0x00,0x04,0x02,0x09,0x09,0x05,\n0x03,0x01,0x03,0x05,0x09,0x09,/*\"渙\",1066*/},{\n\n0x06,0xFA,0x2A,0x2A,0x2A,0x3B,0x2A,0x2A,0x2A,0xEA,0x06,0x00,0x0F,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"宦\",1067*/},{\n\n0x30,0x2C,0xA3,0x60,0x18,0x02,0x02,0x02,0x02,0x02,0xFE,0x02,0x03,0x02,0x02,0x03,\n0x06,0x00,0x00,0x08,0x08,0x07,/*\"幻\",1068*/},{\n\n0x12,0x12,0x77,0x52,0x52,0x56,0x5A,0x52,0x57,0x52,0x12,0x08,0x04,0x03,0x00,0x00,\n0x0F,0x00,0x00,0x07,0x08,0x0C,/*\"荒\",1069*/},{\n\n0x30,0xFF,0x08,0x12,0x72,0x57,0x5A,0x52,0x57,0x52,0x12,0x00,0x0F,0x00,0x08,0x07,\n0x00,0x07,0x00,0x07,0x08,0x0C,/*\"慌\",1070*/},{\n\n0x20,0xE2,0xA2,0xAF,0xAA,0xEA,0xAA,0xAF,0xA2,0xE2,0x20,0x00,0x0B,0x06,0x02,0x02,\n0x03,0x02,0x02,0x06,0x0B,0x00,/*\"黃\",1071*/},{\n\n0x42,0xF2,0x2E,0xE2,0x08,0xEA,0xAF,0xFA,0xAF,0xEA,0x08,0x00,0x07,0x02,0x07,0x00,\n0x0B,0x06,0x03,0x06,0x0B,0x00,/*\"磺\",1072*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xBE,0xAB,0xAA,0xAA,0xBE,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"蝗\",1073*/},{\n\n0x24,0xEB,0xAA,0xBE,0xAA,0xEC,0xAB,0xBE,0xAA,0xEA,0x22,0x00,0x0B,0x06,0x02,0x02,\n0x03,0x02,0x02,0x06,0x0B,0x00,/*\"簧\",1074*/},{\n\n0x00,0xBE,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xAA,0xBE,0x00,0x08,0x08,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x08,0x08,/*\"皇\",1075*/},{\n\n0x00,0xFF,0x41,0x7D,0x55,0xD7,0x55,0x7D,0x41,0xFF,0x00,0x08,0x07,0x00,0x05,0x05,\n0x07,0x05,0x05,0x00,0x07,0x0C,/*\"凰\",1076*/},{\n\n0x78,0x00,0xFF,0x08,0x90,0xBE,0xAB,0xAA,0xAA,0xBE,0x80,0x00,0x00,0x0F,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"惶\",1077*/},{\n\n0x78,0x00,0xFF,0x10,0x88,0xBE,0xAB,0xAA,0xAA,0xBE,0x80,0x08,0x06,0x01,0x02,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"煌\",1078*/},{\n\n0x00,0x5F,0x95,0x15,0x15,0xF5,0x15,0x15,0x95,0x5F,0x00,0x09,0x09,0x05,0x03,0x01,\n0x01,0x07,0x09,0x09,0x09,0x0D,/*\"晃\",1079*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x5F,0x95,0xF5,0x95,0x5F,0x00,0x03,0x00,0x0F,0x02,0x0B,\n0x05,0x03,0x01,0x07,0x09,0x0D,/*\"幌\",1080*/},{\n\n0x78,0x00,0xFF,0x08,0x24,0x28,0xE0,0x3F,0xE0,0x28,0x24,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"恍\",1081*/},{\n\n0x55,0x56,0x54,0x00,0x12,0x77,0x52,0x5A,0x52,0x57,0x12,0x0F,0x05,0x0F,0x00,0x08,\n0x07,0x00,0x07,0x00,0x0F,0x08,/*\"謊\",1082*/},{\n\n0x04,0x04,0xFF,0x04,0xE4,0x04,0xF4,0x04,0x84,0x64,0x04,0x04,0x03,0x08,0x09,0x04,\n0x02,0x01,0x02,0x04,0x08,0x08,/*\"灰\",1083*/},{\n\n0x88,0x88,0xFF,0x48,0xF3,0x55,0x55,0xFF,0x55,0x55,0xF3,0x00,0x08,0x0F,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"揮\",1084*/},{\n\n0x24,0xE8,0x3F,0xE8,0x27,0xF5,0x55,0xFF,0x55,0xF5,0x03,0x08,0x07,0x00,0x0F,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"輝\",1085*/},{\n\n0x24,0xF2,0x09,0xB6,0xEC,0xA7,0x94,0x16,0xE8,0x07,0xFC,0x00,0x0F,0x04,0x02,0x08,\n0x0F,0x02,0x0C,0x04,0x03,0x0C,/*\"徽\",1086*/},{\n\n0x78,0x00,0xFF,0x08,0xC4,0x3F,0xC4,0x04,0xF4,0x44,0x24,0x00,0x00,0x0F,0x04,0x03,\n0x08,0x04,0x02,0x01,0x06,0x08,/*\"恢\",1087*/},{\n\n0x78,0x48,0xFF,0x48,0xFE,0x02,0xF2,0x92,0xF2,0x02,0xFE,0x04,0x04,0x03,0x02,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"蛔\",1088*/},{\n\n0x00,0xFE,0x02,0x02,0xF2,0x92,0x92,0xF2,0x02,0x02,0xFE,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"回\",1089*/},{\n\n0xBE,0xA9,0xE0,0xAA,0xBE,0x10,0xCE,0x42,0x42,0xDE,0x10,0x08,0x08,0x0F,0x04,0x04,\n0x08,0x05,0x02,0x02,0x05,0x08,/*\"毀\",1090*/},{\n\n0x78,0x00,0xFF,0x48,0xC4,0x7B,0x4A,0x6A,0x4A,0xFA,0x42,0x00,0x00,0x0F,0x00,0x03,\n0x02,0x02,0x0B,0x0A,0x07,0x02,/*\"悔\",1091*/},{\n\n0x2A,0xAA,0xBF,0xAA,0xAA,0xA0,0xAA,0xAA,0xBF,0xEA,0x2A,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"慧\",1092*/},{\n\n0x84,0x84,0xF4,0x84,0x84,0xBF,0x84,0x84,0xF4,0x84,0x84,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"卉\",1093*/},{\n\n0x82,0x82,0xFA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x82,0xC2,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"惠\",1094*/},{\n\n0xFE,0x22,0xFE,0x48,0xC4,0x7B,0x4A,0x6A,0x4A,0xFA,0x42,0x07,0x02,0x07,0x00,0x03,\n0x02,0x02,0x0B,0x0A,0x07,0x02,/*\"晦\",1095*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x40,0x24,0xFC,0x57,0x54,0x54,0xF4,0x09,0x05,0x05,0x09,0x00,\n0x00,0x0F,0x01,0x01,0x09,0x0F,/*\"賄\",1096*/},{\n\n0x12,0xD2,0xFE,0x91,0xE8,0xAE,0xA8,0xAF,0xFA,0x2A,0xB0,0x01,0x00,0x0F,0x08,0x07,\n0x0A,0x0F,0x04,0x03,0x05,0x0E,/*\"穢\",1097*/},{\n\n0xF4,0x94,0xB4,0xD2,0x96,0xF5,0x96,0xD2,0xB4,0x94,0xF4,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"會\",1098*/},{\n\n0x78,0x00,0xFF,0x08,0xF4,0xB2,0xD5,0xF5,0xD5,0xB2,0xF4,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"燴\",1099*/},{\n\n0xFF,0x25,0x49,0x11,0xF9,0xAF,0xA9,0xFB,0xAD,0xA9,0x01,0x0F,0x0A,0x09,0x08,0x0F,\n0x0A,0x0A,0x0B,0x0A,0x0A,0x08,/*\"匯\",1100*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x8A,0xBA,0xAF,0xEA,0xBE,0x88,0x0F,0x05,0x05,0x0F,0x00,\n0x06,0x04,0x04,0x0F,0x04,0x04,/*\"諱\",1101*/},{\n\n0x55,0x56,0x54,0x00,0x44,0xFB,0x4A,0x6A,0x4A,0xFA,0x42,0x0F,0x05,0x0F,0x00,0x00,\n0x03,0x02,0x0B,0x0A,0x07,0x02,/*\"誨\",1102*/},{\n\n0xDC,0xB3,0xC8,0x00,0xF4,0xB2,0xD5,0xF5,0xD5,0xB2,0xF4,0x0E,0x00,0x06,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"繪\",1103*/},{\n\n0x1A,0x2A,0xEA,0xAF,0xAA,0xFA,0xAA,0xAF,0xEA,0x2A,0x1A,0x02,0x02,0x03,0x02,0x02,\n0x0F,0x02,0x02,0x03,0x02,0x02,/*\"葷\",1104*/},{\n\n0x00,0x7E,0xCA,0xAA,0x8A,0x8A,0x8E,0x99,0xA9,0xC9,0x68,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"昏\",1105*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xBE,0xAA,0xAA,0x9E,0xA9,0x70,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"婚\",1106*/},{\n\n0x92,0x72,0x12,0x00,0x3E,0xAA,0x7B,0x2E,0xEA,0x3E,0x00,0x03,0x02,0x07,0x08,0x06,\n0x01,0x07,0x0B,0x0A,0x0B,0x0C,/*\"魂\",1107*/},{\n\n0x22,0x44,0x03,0xF5,0x55,0x55,0xFF,0x55,0x55,0xF5,0x03,0x04,0x02,0x05,0x05,0x05,\n0x05,0x0F,0x05,0x05,0x05,0x04,/*\"渾\",1108*/},{\n\n0x10,0x21,0x02,0x00,0xDF,0x15,0x15,0x15,0xD5,0x1F,0x80,0x04,0x02,0x01,0x00,0x0F,\n0x09,0x05,0x00,0x07,0x09,0x0C,/*\"混\",1109*/},{\n\n0x86,0xAA,0xAA,0xFF,0xAA,0xAA,0xA6,0x91,0x88,0x91,0x22,0x00,0x0E,0x0A,0x0B,0x0A,\n0x0E,0x00,0x0F,0x04,0x0F,0x00,/*\"豁\",1110*/},{\n\n0x22,0x44,0x10,0x92,0x92,0x92,0xFE,0x91,0x91,0x91,0x10,0x04,0x02,0x01,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"活\",1111*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x00,0x24,0xAB,0x52,0x4A,0xC6,0x02,0x01,0x0F,0x01,0x02,\n0x00,0x09,0x08,0x05,0x02,0x01,/*\"夥\",1112*/},{\n\n0x00,0x20,0x1C,0x00,0xC0,0x3F,0xC0,0x00,0x10,0x0C,0x00,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x03,0x04,0x08,0x08,/*\"火\",1113*/},{\n\n0x8A,0x44,0xFB,0x20,0xFA,0x57,0x52,0xF6,0x5A,0x57,0x52,0x08,0x08,0x07,0x08,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"獲\",1114*/},{\n\n0x04,0xF4,0x94,0x94,0xF4,0x04,0xFF,0x04,0xC5,0x36,0x04,0x04,0x04,0x04,0x02,0x0A,\n0x04,0x02,0x01,0x02,0x04,0x0F,/*\"或\",1115*/},{\n\n0x02,0x3A,0x2A,0xAA,0xBA,0x02,0xBF,0x42,0xA2,0x1B,0xC2,0x09,0x05,0x01,0x04,0x0A,\n0x0D,0x08,0x0C,0x00,0x05,0x09,/*\"惑\",1116*/},{\n\n0x8C,0x45,0xED,0xB5,0xA5,0xAF,0xF5,0xA5,0xAD,0xA5,0x2C,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"霍\",1117*/},{\n\n0x08,0xE4,0xBE,0xA1,0xA4,0xA4,0xA7,0xAA,0xAA,0xE9,0x0C,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"貨\",1118*/},{\n\n0x84,0x45,0xF6,0x4C,0xE0,0x3F,0xA5,0xBD,0xA1,0x3F,0xE0,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"禍\",1119*/},{\n\n0xC2,0xBE,0xAA,0xFF,0xAA,0xBE,0xCA,0xB7,0x51,0xB7,0x84,0x02,0x02,0x02,0x02,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"擊\",1120*/},{\n\n0x08,0x08,0xFF,0x08,0x02,0xFE,0x82,0x02,0x32,0x2E,0xE0,0x02,0x02,0x01,0x09,0x06,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"圾\",1121*/},{\n\n0x82,0x82,0xFF,0xAA,0xAA,0xAA,0xAA,0xAA,0xFF,0x82,0x82,0x0A,0x09,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x09,0x0A,/*\"基\",1122*/},{\n\n0xC8,0xFF,0x48,0xB4,0xEB,0xB4,0x80,0xFF,0xB4,0xEB,0xB4,0x00,0x0F,0x00,0x08,0x07,\n0x02,0x08,0x05,0x02,0x05,0x0E,/*\"機\",1123*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x10,0xDA,0x56,0xD3,0x16,0xFA,0x07,0x02,0x03,0x02,0x07,\n0x00,0x07,0x02,0x03,0x08,0x0F,/*\"畸\",1124*/},{\n\n0x12,0xD2,0xFE,0x51,0x8A,0xB6,0xD3,0xD6,0xDB,0xCA,0x6C,0x01,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"稽\",1125*/},{\n\n0x12,0xD2,0xFE,0x91,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x01,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"積\",1126*/},{\n\n0x0C,0x0B,0xFE,0xAA,0xAA,0xAC,0xAB,0xAA,0xFE,0x0A,0x0A,0x02,0x0A,0x07,0x02,0x02,\n0x02,0x02,0x02,0x07,0x0A,0x02,/*\"箕\",1127*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0xFE,0x02,0xFE,0x00,0x00,0x08,0x07,0x00,0x08,0x0F,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"肌\",1128*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x04,0xFE,0x02,0xFE,0x00,0x00,0x00,0x0F,0x04,0x02,0x0C,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"飢\",1129*/},{\n\n0x9E,0x12,0xF2,0x5E,0x88,0x48,0xF9,0x0A,0xF8,0x48,0x88,0x07,0x04,0x03,0x02,0x08,\n0x04,0x03,0x08,0x0F,0x00,0x01,/*\"跡\",1130*/},{\n\n0x22,0x44,0x80,0xBE,0xEB,0xBE,0x10,0xEC,0x0B,0xF8,0x08,0x04,0x02,0x08,0x07,0x0A,\n0x0E,0x08,0x04,0x03,0x04,0x08,/*\"激\",1131*/},{\n\n0x55,0x56,0x54,0xB4,0xEB,0xB4,0x80,0xFF,0xB4,0xEB,0xB4,0x0F,0x05,0x07,0x08,0x07,\n0x02,0x08,0x05,0x02,0x05,0x0E,/*\"譏\",1132*/},{\n\n0xB6,0xEA,0xA5,0x91,0xC5,0x10,0xFC,0x27,0xFC,0x25,0x24,0x0A,0x06,0x03,0x06,0x0A,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"雞\",1133*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFE,0x02,0xF2,0x1E,0x12,0xF2,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x08,0x09,0x0F,0x09,0x09,/*\"姬\",1134*/},{\n\n0xD8,0xB4,0x93,0xC8,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x0C,0x02,0x04,0x02,0x04,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"績\",1135*/},{\n\n0xD8,0xB4,0x93,0xC8,0x10,0xF7,0x55,0x55,0x55,0xF7,0x10,0x0C,0x02,0x04,0x02,0x04,\n0x07,0x05,0x05,0x05,0x0F,0x02,/*\"緝\",1136*/},{\n\n0x04,0xA4,0xA4,0xA4,0xA4,0xBF,0xA4,0xA4,0xA4,0xA4,0x04,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"吉\",1137*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xF2,0x92,0xFA,0x46,0x92,0x70,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x0A,0x0B,0x09,0x08,0x0B,/*\"極\",1138*/},{\n\n0x74,0x14,0xFF,0x54,0x74,0x00,0x74,0x14,0xFF,0x54,0x74,0x02,0x01,0x0F,0x01,0x02,\n0x00,0x02,0x01,0x0F,0x01,0x02,/*\"棘\",1139*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x10,0xF7,0x55,0x55,0xF7,0x10,0x02,0x02,0x0F,0x02,0x02,\n0x04,0x07,0x05,0x05,0x0F,0x02,/*\"輯\",1140*/},{\n\n0x8A,0xA9,0xFD,0xAB,0x01,0xAA,0xBD,0xA9,0xBD,0xAB,0x21,0x04,0x02,0x0F,0x02,0x04,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"籍\",1141*/},{\n\n0x08,0x04,0xFE,0xAB,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0x82,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"集\",1142*/},{\n\n0x00,0x02,0xC2,0x3E,0x62,0x82,0x02,0x32,0x2A,0xA6,0x60,0x08,0x06,0x01,0x08,0x08,\n0x04,0x05,0x02,0x05,0x08,0x08,/*\"及\",1143*/},{\n\n0x08,0x84,0xAB,0xAA,0xAA,0xAA,0xAA,0xAE,0xA8,0xF8,0x00,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"急\",1144*/},{\n\n0x08,0x90,0xFC,0x04,0x44,0x35,0x26,0xE4,0x24,0x24,0x04,0x09,0x04,0x03,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"疾\",1145*/},{\n\n0x22,0x44,0x00,0x02,0xFE,0x82,0x02,0x32,0x2E,0xE0,0x00,0x04,0x02,0x08,0x06,0x01,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"汲\",1146*/},{\n\n0x00,0xFE,0x2A,0xAA,0x2A,0x3E,0x00,0xFE,0x02,0x02,0xFE,0x00,0x0F,0x04,0x02,0x01,\n0x06,0x00,0x0F,0x00,0x02,0x03,/*\"即\",1147*/},{\n\n0x88,0x78,0x0F,0xF8,0x90,0xFC,0x44,0x3D,0xE6,0x24,0x24,0x08,0x05,0x02,0x0D,0x04,\n0x03,0x09,0x05,0x03,0x05,0x09,/*\"嫉\",1148*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x02,0xFE,0x02,0x32,0x2E,0xE0,0x0C,0x02,0x04,0x02,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"級\",1149*/},{\n\n0x84,0xFF,0x44,0x28,0xDA,0x7A,0x06,0x7B,0x06,0x7A,0xD6,0x08,0x0F,0x00,0x08,0x07,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"擠\",1150*/},{\n\n0xB6,0xED,0xA4,0xB2,0x80,0xFF,0x80,0xB6,0xAD,0xE4,0xB2,0x08,0x07,0x02,0x04,0x00,\n0x08,0x05,0x02,0x05,0x08,0x0E,/*\"幾\",1151*/},{\n\n0x48,0x25,0xF2,0xA8,0xA4,0xA3,0xA4,0xA8,0xF2,0x25,0x48,0x00,0x00,0x0F,0x02,0x02,\n0x02,0x02,0x0A,0x0F,0x00,0x00,/*\"脊\",1152*/},{\n\n0x00,0xE2,0x22,0x22,0x22,0x22,0x22,0x22,0x22,0x3E,0x00,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0F,/*\"己\",1153*/},{\n\n0x12,0xEE,0xAA,0xEF,0xBA,0xE2,0x02,0xF7,0x02,0x02,0xFA,0x08,0x03,0x0A,0x03,0x0A,\n0x03,0x08,0x03,0x00,0x08,0x0F,/*\"薊\",1154*/},{\n\n0x88,0x88,0xFF,0x48,0x24,0xE4,0x24,0x3F,0x24,0xE4,0x04,0x00,0x08,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"技\",1155*/},{\n\n0x0A,0x0A,0xFA,0x5F,0x50,0xF0,0x57,0x5A,0xFA,0x09,0x0C,0x04,0x05,0x0D,0x07,0x05,\n0x05,0x05,0x07,0x0D,0x05,0x04,/*\"冀\",1156*/},{\n\n0x48,0x48,0x2A,0x5A,0x4A,0x7E,0xC9,0x59,0x29,0x48,0x48,0x02,0x02,0x02,0x0A,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"季\",1157*/},{\n\n0x20,0x10,0xFC,0x03,0x24,0xE4,0x24,0x3F,0x24,0xE4,0x04,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"伎\",1158*/},{\n\n0x44,0xAA,0x97,0xAA,0xA6,0xA0,0xA7,0xAA,0x92,0xAA,0x46,0x08,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x08,/*\"祭\",1159*/},{\n\n0x48,0x7A,0x86,0x7B,0x06,0xFA,0x56,0x00,0xFC,0x00,0xFF,0x00,0x08,0x07,0x05,0x05,\n0x0F,0x00,0x00,0x01,0x08,0x0F,/*\"劑\",1160*/},{\n\n0x78,0x00,0xFF,0x04,0x48,0x2A,0x5A,0x7E,0xD9,0x29,0x48,0x00,0x00,0x0F,0x00,0x02,\n0x02,0x0A,0x0F,0x02,0x02,0x02,/*\"悸\",1161*/},{\n\n0x11,0x22,0x28,0xDA,0x7A,0x06,0x7B,0x06,0x7A,0xD6,0x22,0x04,0x02,0x08,0x07,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"濟\",1162*/},{\n\n0x46,0x4A,0x6A,0x5A,0x4A,0x4F,0x4A,0x5A,0xEA,0x4A,0x46,0x00,0x07,0x05,0x05,0x05,\n0x07,0x00,0x08,0x0F,0x00,0x00,/*\"寄\",1163*/},{\n\n0x46,0x42,0xFA,0x52,0x52,0x03,0xF2,0x12,0x12,0xF2,0x06,0x02,0x09,0x0F,0x01,0x02,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"寂\",1164*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0x20,0x20,0xFF,0x20,0x20,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"計\",1165*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0xE2,0x22,0x22,0x22,0x3E,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"記\",1166*/},{\n\n0xFE,0x2A,0xAA,0x3E,0x00,0x3A,0x22,0xFE,0x22,0x22,0x20,0x0F,0x04,0x02,0x01,0x0A,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"既\",1167*/},{\n\n0x00,0x72,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x9E,0xC0,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"忌\",1168*/},{\n\n0xFE,0x32,0xCE,0x48,0xB7,0x9A,0xAE,0xA0,0xA7,0x9A,0xA6,0x0F,0x02,0x01,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"際\",1169*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0xE4,0x24,0x3F,0x24,0xE4,0x04,0x08,0x05,0x02,0x05,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"妓\",1170*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFF,0x5A,0xB5,0x10,0x5A,0xB5,0x5A,0x0E,0x00,0x06,0x00,0x0F,\n0x0B,0x0A,0x08,0x0B,0x0A,0x0B,/*\"繼\",1171*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0xE2,0x22,0x22,0x22,0x3E,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"紀\",1172*/},{\n\n0x82,0x8A,0xBA,0xEA,0xAA,0xAF,0xAA,0xEA,0xBA,0x8A,0x82,0x0A,0x0A,0x07,0x02,0x0A,\n0x0E,0x00,0x0E,0x0A,0x0A,0x0E,/*\"嘉\",1173*/},{\n\n0xC8,0xFF,0x48,0x08,0xFF,0x08,0xF8,0x00,0xFC,0x04,0xFC,0x00,0x0F,0x08,0x04,0x03,\n0x08,0x0F,0x00,0x0F,0x04,0x0F,/*\"枷\",1174*/},{\n\n0x80,0x44,0x34,0x44,0x84,0xFF,0x84,0x44,0x34,0x44,0x80,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x04,0x08,0x08,/*\"夾\",1175*/},{\n\n0x20,0x10,0xFC,0x03,0x20,0x24,0x24,0xBF,0x24,0x24,0x20,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"佳\",1176*/},{\n\n0x06,0x4A,0x4A,0xAA,0x5A,0x2B,0xCA,0x8A,0x4A,0x2A,0x06,0x04,0x05,0x05,0x02,0x0A,\n0x09,0x07,0x00,0x01,0x02,0x02,/*\"家\",1177*/},{\n\n0x08,0x08,0xFF,0x08,0x08,0xF8,0x00,0xFC,0x04,0x04,0xFC,0x08,0x06,0x01,0x08,0x08,\n0x07,0x00,0x0F,0x04,0x04,0x0F,/*\"加\",1178*/},{\n\n0x12,0x92,0x72,0x97,0x12,0xFA,0x12,0x97,0x72,0x92,0x12,0x09,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x09,/*\"莢\",1179*/},{\n\n0x84,0x74,0x84,0xFF,0x84,0x74,0x84,0xFA,0xAE,0xAA,0xFA,0x08,0x04,0x02,0x01,0x02,\n0x04,0x08,0x0B,0x06,0x06,0x0B,/*\"頰\",1180*/},{\n\n0x1D,0xF5,0x55,0x5F,0x55,0x55,0x55,0x5F,0x55,0xF5,0x1D,0x00,0x07,0x0D,0x05,0x05,\n0x05,0x05,0x05,0x0D,0x07,0x00,/*\"賈\",1181*/},{\n\n0x00,0xFF,0x89,0x89,0x89,0xFF,0x89,0x89,0x89,0xFF,0x00,0x00,0x01,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x01,0x00,/*\"甲\",1182*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xFE,0x92,0xFE,0x92,0xFE,0x08,0x09,0x07,0x05,0x04,\n0x00,0x01,0x00,0x0F,0x00,0x01,/*\"鉀\",1183*/},{\n\n0x10,0xFC,0x03,0xFE,0x52,0x5E,0x00,0xD2,0x52,0x52,0xDE,0x00,0x0F,0x00,0x0F,0x01,\n0x01,0x08,0x05,0x02,0x06,0x09,/*\"假\",1184*/},{\n\n0x12,0xD2,0xFE,0x91,0x46,0xAA,0x5A,0xAB,0xCA,0x4A,0x26,0x01,0x00,0x0F,0x00,0x05,\n0x02,0x09,0x08,0x07,0x01,0x02,/*\"稼\",1185*/},{\n\n0x20,0x10,0xFC,0x03,0x3A,0xEA,0xBE,0xAA,0xBE,0xEA,0x3A,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"價\",1186*/},{\n\n0xA2,0x92,0x8F,0xA2,0xA2,0xDE,0x80,0xBE,0xA2,0xA2,0xBE,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"架\",1187*/},{\n\n0x12,0xEA,0xA7,0xA2,0xAA,0xEE,0xA0,0xAE,0xAA,0x2A,0x0E,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0A,0x0A,0x06,/*\"駕\",1188*/},{\n\n0x88,0x78,0x0F,0xF8,0x46,0x2A,0x9A,0x6B,0xCA,0x4A,0x26,0x08,0x05,0x02,0x0D,0x00,\n0x05,0x0A,0x09,0x07,0x01,0x02,/*\"嫁\",1189*/},{\n\n0x62,0x9E,0xF2,0xAC,0xFB,0x0C,0xFB,0xAC,0xFF,0x8A,0x4C,0x08,0x06,0x01,0x0A,0x0F,\n0x08,0x0F,0x0A,0x03,0x04,0x0E,/*\"殲\",1190*/},{\n\n0x00,0x7F,0x55,0x77,0x5D,0x20,0x18,0x07,0x14,0x64,0x04,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"監\",1191*/},{\n\n0x7F,0x55,0x55,0x77,0x5D,0x80,0x41,0x2F,0x11,0x29,0x47,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"堅\",1192*/},{\n\n0x90,0x88,0x86,0x80,0x80,0xDF,0x80,0x80,0x82,0x84,0x98,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"尖\",1193*/},{\n\n0x04,0xA3,0xA2,0xA6,0xBA,0x54,0x53,0xBA,0xD6,0x12,0x02,0x02,0x0A,0x0A,0x0A,0x0B,\n0x05,0x05,0x0B,0x09,0x09,0x0C,/*\"箋\",1194*/},{\n\n0xFF,0x15,0x15,0xDF,0x40,0x40,0x40,0xDF,0x15,0x15,0xFF,0x0F,0x00,0x00,0x07,0x05,\n0x05,0x05,0x07,0x00,0x08,0x0F,/*\"間\",1195*/},{\n\n0x02,0xFA,0xAA,0xAB,0xAA,0xFA,0x02,0xF3,0x02,0xFA,0x02,0x00,0x0B,0x00,0x00,0x0A,\n0x03,0x08,0x01,0x02,0x0B,0x00,/*\"煎\",1196*/},{\n\n0x44,0x54,0x55,0x56,0xFC,0x54,0xFC,0x56,0x55,0xF4,0x44,0x08,0x05,0x03,0x01,0x0F,\n0x01,0x0F,0x01,0x03,0x05,0x08,/*\"兼\",1197*/},{\n\n0x00,0xFE,0x0A,0xEA,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xEE,0x08,0x07,0x00,0x0F,0x02,\n0x02,0x02,0x02,0x02,0x0A,0x0F,/*\"肩\",1198*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x00,0xFF,0x49,0xC9,0x7F,0x80,0x0A,0x06,0x03,0x06,0x0A,\n0x00,0x0F,0x04,0x03,0x05,0x08,/*\"艱\",1199*/},{\n\n0x88,0x78,0x0F,0xF8,0x40,0x42,0x42,0xFE,0x42,0x42,0x40,0x08,0x05,0x02,0x0D,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"奸\",1200*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFC,0x54,0xD4,0x04,0xFF,0x84,0x65,0x0E,0x00,0x06,0x08,0x07,\n0x02,0x0B,0x04,0x03,0x05,0x0E,/*\"緘\",1201*/},{\n\n0xFA,0xAA,0x5A,0xAF,0x0A,0xFA,0x4A,0xEF,0x4A,0xCA,0xFA,0x0F,0x05,0x01,0x05,0x00,\n0x0F,0x05,0x07,0x05,0x09,0x0F,/*\"繭\",1202*/},{\n\n0x88,0x68,0xFF,0x48,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x00,0x00,0x0F,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"檢\",1203*/},{\n\n0x02,0xFA,0x8A,0xAA,0xCA,0xFF,0xCA,0xAA,0x8A,0xFA,0x02,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"柬\",1204*/},{\n\n0xF8,0x48,0x9F,0x4A,0xFA,0x08,0xD4,0x52,0xD1,0x52,0xD4,0x0F,0x09,0x0C,0x09,0x0F,\n0x00,0x09,0x07,0x09,0x07,0x09,/*\"鹼\",1205*/},{\n\n0xF2,0x2E,0xE2,0x00,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x07,0x02,0x07,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"礆\",1206*/},{\n\n0x84,0xFF,0x44,0x00,0xFA,0xAA,0x8A,0xFF,0x8A,0xAA,0xFA,0x08,0x0F,0x00,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"揀\",1207*/},{\n\n0x88,0x88,0xFF,0x48,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x00,0x08,0x0F,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"撿\",1208*/},{\n\n0x04,0xFB,0xAA,0xFE,0x82,0x84,0x83,0xFA,0xAE,0xFA,0x02,0x00,0x0F,0x00,0x00,0x0F,\n0x0A,0x0F,0x00,0x08,0x0F,0x00,/*\"簡\",1209*/},{\n\n0x20,0x10,0xFC,0x03,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x00,0x00,0x0F,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"儉\",1210*/},{\n\n0x02,0xFE,0x2A,0x2B,0xAA,0xFE,0x02,0x3B,0x82,0xFE,0x02,0x08,0x0A,0x0A,0x06,0x02,\n0x02,0x02,0x0A,0x0A,0x06,0x00,/*\"剪\",1211*/},{\n\n0x11,0x22,0xFC,0x04,0xD4,0x54,0xD4,0x04,0xFF,0x84,0x65,0x04,0x0A,0x07,0x00,0x03,\n0x02,0x0B,0x04,0x03,0x05,0x0E,/*\"減\",1212*/},{\n\n0x02,0xFA,0xAF,0xAA,0xFA,0xAA,0xAE,0xFA,0xAF,0xEA,0x0A,0x04,0x0B,0x00,0x0B,0x02,\n0x0A,0x02,0x0A,0x02,0x0A,0x0E,/*\"薦\",1213*/},{\n\n0xC8,0xFF,0x48,0x7F,0x55,0x77,0x5D,0x10,0x0F,0x34,0x04,0x00,0x0F,0x08,0x0F,0x09,\n0x0F,0x09,0x0F,0x09,0x0F,0x08,/*\"檻\",1214*/},{\n\n0x4A,0xF9,0x4A,0x00,0x7F,0x55,0x77,0x5D,0x10,0x0F,0x34,0x0A,0x0F,0x05,0x08,0x0F,\n0x09,0x0F,0x09,0x0F,0x09,0x0F,/*\"鑑\",1215*/},{\n\n0x9E,0x12,0xF2,0x5E,0x24,0x24,0xD7,0x8A,0xD7,0xA2,0xBA,0x07,0x04,0x03,0x02,0x09,\n0x09,0x05,0x02,0x05,0x08,0x0E,/*\"踐\",1216*/},{\n\n0xFE,0x2A,0xFE,0x00,0x24,0x24,0xD7,0x8A,0xD7,0xA2,0xBA,0x09,0x05,0x09,0x00,0x09,\n0x09,0x05,0x02,0x05,0x08,0x0E,/*\"賤\",1217*/},{\n\n0x00,0xFE,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xFE,0x00,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"見\",1218*/},{\n\n0x4A,0xF9,0x4A,0x64,0xDC,0x88,0xAA,0xFF,0xAA,0xBE,0x08,0x0A,0x0F,0x05,0x0A,0x07,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"鍵\",1219*/},{\n\n0x24,0xE3,0xAA,0xB6,0xA2,0xE4,0x23,0xB2,0x26,0xE2,0x22,0x00,0x0F,0x02,0x02,0x0A,\n0x0F,0x00,0x03,0x08,0x0F,0x00,/*\"箭\",1220*/},{\n\n0x10,0xFC,0x03,0x90,0x8E,0x88,0x88,0xFF,0x88,0x88,0x88,0x00,0x0F,0x00,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"件\",1221*/},{\n\n0x10,0xFC,0x03,0x64,0xDC,0x88,0xAA,0xFF,0xAA,0xBE,0x08,0x00,0x0F,0x00,0x0A,0x07,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"健\",1222*/},{\n\n0x40,0xFE,0x4B,0x52,0xFF,0x55,0x77,0x5D,0x10,0x0F,0x34,0x08,0x07,0x01,0x0A,0x0F,\n0x09,0x0F,0x09,0x0F,0x09,0x0F,/*\"艦\",1223*/},{\n\n0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x00,0xFC,0x00,0xFF,0x09,0x07,0x09,0x00,0x09,\n0x07,0x09,0x00,0x01,0x08,0x0F,/*\"劍\",1224*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x04,0x24,0xD7,0x8A,0xD7,0x9A,0x00,0x0F,0x04,0x02,0x0C,\n0x01,0x09,0x0B,0x04,0x0A,0x0C,/*\"餞\",1225*/},{\n\n0x22,0x44,0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xFE,0x12,0xF1,0x04,0x02,0x02,0x02,0x0F,\n0x02,0x02,0x08,0x07,0x00,0x0F,/*\"漸\",1226*/},{\n\n0x22,0x44,0x00,0xFE,0x2A,0xFE,0x24,0xD7,0x8A,0xD7,0x9A,0x04,0x02,0x00,0x09,0x05,\n0x09,0x09,0x0B,0x04,0x0A,0x0C,/*\"濺\",1227*/},{\n\n0x11,0x22,0xFF,0x15,0xD5,0x5F,0x40,0x5F,0xD5,0x15,0xFF,0x04,0x02,0x0F,0x00,0x07,\n0x05,0x05,0x05,0x07,0x08,0x0F,/*\"澗\",1228*/},{\n\n0x32,0x2A,0xE6,0x08,0xAA,0xAA,0xFF,0xAA,0xAA,0xBE,0x08,0x09,0x06,0x05,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x0A,/*\"建\",1229*/},{\n\n0x10,0xFC,0x03,0x82,0xBE,0xAA,0xBE,0xAA,0xAA,0xBE,0x82,0x00,0x0F,0x00,0x08,0x0F,\n0x0A,0x0F,0x0A,0x0A,0x0F,0x08,/*\"僵\",1230*/},{\n\n0x40,0x54,0x55,0x56,0xD4,0x7C,0x54,0x56,0x55,0x54,0x40,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"姜\",1231*/},{\n\n0x40,0xDE,0x50,0xFF,0x00,0x48,0x54,0x6B,0x52,0xEA,0x46,0x08,0x07,0x00,0x0F,0x00,\n0x00,0x01,0x0A,0x08,0x0F,0x00,/*\"將\",1232*/},{\n\n0x90,0x77,0x14,0xFF,0x00,0x2A,0x6E,0x29,0xA7,0xF5,0x23,0x08,0x0A,0x06,0x02,0x08,\n0x0F,0x00,0x02,0x04,0x0A,0x08,/*\"漿\",1233*/},{\n\n0x22,0x44,0x00,0x02,0x02,0x02,0xFE,0x02,0x02,0x02,0x00,0x04,0x02,0x09,0x08,0x08,\n0x08,0x0F,0x08,0x08,0x08,0x08,/*\"江\",1234*/},{\n\n0xBA,0xEA,0xAA,0xEE,0x82,0xBE,0xAA,0xBE,0xAA,0xBE,0x82,0x02,0x0B,0x0A,0x07,0x08,\n0x0F,0x0A,0x0F,0x0A,0x0F,0x08,/*\"疆\",1235*/},{\n\n0x82,0xBA,0xA2,0xFF,0x02,0x92,0xAA,0x5F,0x6A,0xAA,0x1A,0x08,0x07,0x00,0x0F,0x01,\n0x03,0x05,0x01,0x09,0x0F,0x01,/*\"蔣\",1236*/},{\n\n0x90,0x77,0x14,0x7F,0x00,0xAA,0x6E,0x29,0xA7,0xF5,0x23,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"槳\",1237*/},{\n\n0x90,0x77,0x14,0xFF,0x00,0x2A,0x6E,0x29,0xA7,0xF5,0x23,0x0A,0x0A,0x0A,0x06,0x02,\n0x03,0x02,0x06,0x0B,0x0A,0x0A,/*\"獎\",1238*/},{\n\n0x54,0x55,0x56,0x54,0x08,0xEA,0xAF,0xFA,0xAF,0xEA,0x08,0x0F,0x05,0x05,0x0F,0x02,\n0x0F,0x02,0x03,0x0A,0x0F,0x02,/*\"講\",1239*/},{\n\n0x00,0xFF,0x01,0x01,0xF9,0x49,0x49,0x49,0xC5,0x45,0x41,0x00,0x0F,0x08,0x0C,0x0B,\n0x08,0x08,0x08,0x0F,0x08,0x08,/*\"匠\",1240*/},{\n\n0x68,0x5B,0x4A,0xDF,0x40,0x4A,0x5B,0xCD,0x6B,0x7D,0x48,0x00,0x0F,0x0D,0x0B,0x0D,\n0x0D,0x0D,0x0B,0x0D,0x0F,0x00,/*\"醬\",1241*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0x54,0x57,0xEA,0x4A,0x56,0x10,0x0F,0x02,0x02,0x01,0x00,\n0x03,0x02,0x0F,0x02,0x02,0x02,/*\"降\",1242*/},{\n\n0x22,0x12,0xFA,0xAF,0xAA,0xAE,0xFA,0xAF,0xAA,0xAA,0x0A,0x08,0x04,0x03,0x06,0x0A,\n0x02,0x07,0x0A,0x02,0x06,0x0A,/*\"蕉\",1243*/},{\n\n0x88,0x68,0xFF,0x48,0x10,0xDF,0x14,0x12,0xFE,0x02,0xFE,0x00,0x00,0x0F,0x02,0x09,\n0x0F,0x01,0x0A,0x04,0x03,0x0C,/*\"椒\",1244*/},{\n\n0x42,0xF2,0x2E,0xE2,0x08,0xFC,0x57,0x54,0xFD,0x56,0x54,0x00,0x07,0x02,0x03,0x0C,\n0x03,0x0D,0x01,0x0D,0x01,0x0D,/*\"礁\",1245*/},{\n\n0x08,0x04,0xFE,0x55,0x54,0x54,0xFD,0x56,0x54,0x54,0x04,0x08,0x04,0x03,0x05,0x09,\n0x01,0x05,0x09,0x01,0x05,0x09,/*\"焦\",1246*/},{\n\n0x00,0xFF,0x49,0xFF,0x00,0x8B,0x45,0xAF,0x5A,0xA5,0x4F,0x08,0x07,0x08,0x0F,0x00,\n0x00,0x0A,0x0A,0x09,0x04,0x02,/*\"膠\",1247*/},{\n\n0x04,0x44,0x24,0x54,0x85,0x06,0x84,0x54,0x24,0x44,0x04,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x04,0x08,0x08,/*\"交\",1248*/},{\n\n0x44,0x34,0x85,0x06,0x94,0x24,0x00,0xFE,0x02,0x32,0xCE,0x08,0x04,0x02,0x01,0x02,\n0x04,0x00,0x0F,0x02,0x02,0x01,/*\"郊\",1249*/},{\n\n0x11,0x22,0x88,0xAA,0xFA,0xAA,0x0F,0xAA,0xFA,0xAA,0x88,0x04,0x02,0x08,0x0A,0x06,\n0x02,0x02,0x06,0x0A,0x0A,0x0C,/*\"澆\",1250*/},{\n\n0x7F,0x55,0x7F,0x55,0xE9,0x9A,0xEE,0xAA,0xE9,0x99,0xA8,0x07,0x00,0x0B,0x08,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"驕\",1251*/},{\n\n0xF8,0x0F,0xF8,0x00,0xA8,0x9A,0xEE,0xAA,0xE9,0x99,0xA8,0x0D,0x02,0x05,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"嬌\",1252*/},{\n\n0xFE,0x02,0xFE,0x00,0xBA,0xAE,0xBA,0x2E,0xB9,0xED,0xB9,0x03,0x01,0x03,0x00,0x0F,\n0x0A,0x07,0x08,0x0A,0x0F,0x00,/*\"嚼\",1253*/},{\n\n0x84,0xFF,0x64,0x1F,0xF5,0x5A,0x54,0x5A,0xF5,0x1F,0x30,0x08,0x0F,0x00,0x08,0x05,\n0x03,0x01,0x07,0x09,0x08,0x0E,/*\"攪\",1254*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x44,0x24,0xD5,0x06,0xD4,0x24,0x44,0x08,0x09,0x07,0x04,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"鉸\",1255*/},{\n\n0x48,0x47,0xFC,0x44,0xA8,0x9A,0xEE,0xAA,0xE9,0x99,0xA8,0x08,0x06,0x01,0x02,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"矯\",1256*/},{\n\n0x20,0x10,0xFC,0x03,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"僥\",1257*/},{\n\n0xFE,0x92,0xFE,0x24,0x92,0x88,0x92,0x24,0xFE,0x02,0xFE,0x07,0x08,0x0F,0x00,0x0F,\n0x04,0x0F,0x00,0x0F,0x02,0x03,/*\"腳\",1258*/},{\n\n0x10,0x8A,0x44,0xFB,0x44,0x24,0xD5,0x06,0xD4,0x24,0x44,0x01,0x08,0x08,0x07,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"狡\",1259*/},{\n\n0x08,0xF4,0x53,0x52,0x52,0xF2,0x5A,0x56,0x50,0xF0,0x00,0x08,0x07,0x01,0x01,0x01,\n0x07,0x01,0x01,0x09,0x0F,0x00,/*\"角\",1260*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x24,0xD5,0x06,0xD4,0x24,0x44,0x00,0x0F,0x04,0x02,0x04,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"餃\",1261*/},{\n\n0xDC,0xB3,0xC8,0x80,0xBE,0xEB,0xBE,0xD0,0x0F,0xF8,0x08,0x0E,0x00,0x06,0x08,0x07,\n0x0A,0x0E,0x05,0x02,0x05,0x08,/*\"繳\",1262*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x24,0xD5,0x06,0xD4,0x24,0x44,0x0E,0x00,0x06,0x00,0x06,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"絞\",1263*/},{\n\n0x02,0xFD,0xAA,0xFD,0xAA,0xFD,0x00,0x00,0xFC,0x00,0xFF,0x0A,0x06,0x02,0x0F,0x02,\n0x06,0x0A,0x00,0x01,0x08,0x0F,/*\"剿\",1264*/},{\n\n0xA8,0x6A,0x3F,0xAA,0x6C,0x0A,0x10,0xEF,0x08,0xF8,0x08,0x02,0x02,0x0A,0x0F,0x01,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"教\",1265*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0xA8,0x6A,0x3F,0xAA,0x6C,0x0A,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x01,0x09,0x0F,0x01,0x01,/*\"酵\",1266*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xA8,0x9A,0xEE,0xAA,0xE9,0x99,0xA8,0x02,0x02,0x0F,0x02,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"轎\",1267*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x24,0xD5,0x06,0xD4,0x24,0x44,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"較\",1268*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0xFE,0x00,0x00,0x80,0xFF,0x00,0x03,0x01,0x01,0x03,0x00,\n0x03,0x01,0x01,0x00,0x0F,0x00,/*\"叫\",1269*/},{\n\n0x86,0xCA,0xB6,0xA2,0xA2,0xFB,0xA2,0xA2,0xA6,0xAA,0x86,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"窖\",1270*/},{\n\n0x88,0xFF,0x48,0x80,0x5F,0x75,0x55,0xD5,0x55,0x5F,0xC0,0x08,0x0F,0x00,0x00,0x06,\n0x04,0x05,0x04,0x01,0x08,0x0F,/*\"揭\",1271*/},{\n\n0x88,0x88,0xFF,0x48,0xA4,0xAC,0xB5,0xE6,0xB4,0xAC,0xA4,0x00,0x08,0x0F,0x00,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"接\",1272*/},{\n\n0x00,0xDF,0x52,0x4A,0x6A,0x40,0x4F,0x54,0x52,0xD1,0x18,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"皆\",1273*/},{\n\n0x12,0xD2,0xFE,0x91,0x04,0xA4,0xA4,0xBF,0xA4,0xA4,0x04,0x01,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"秸\",1274*/},{\n\n0x24,0xF2,0x09,0x20,0x24,0xBF,0x24,0x20,0x12,0xF2,0x12,0x00,0x0F,0x00,0x08,0x09,\n0x07,0x05,0x04,0x08,0x0F,0x00,/*\"街\",1275*/},{\n\n0xFE,0x32,0xCE,0x00,0xDF,0x52,0x4A,0x60,0x4F,0x52,0xD9,0x0F,0x02,0x01,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"階\",1276*/},{\n\n0x48,0xEA,0xBA,0xAF,0xFA,0xAA,0xA8,0xFF,0x08,0xE9,0x0A,0x00,0x0F,0x0A,0x0A,0x0F,\n0x0A,0x0A,0x04,0x03,0x04,0x0E,/*\"截\",1277*/},{\n\n0x20,0x24,0xA4,0x7F,0x24,0x24,0x28,0xFF,0x08,0x08,0xF8,0x00,0x03,0x02,0x02,0x0B,\n0x04,0x03,0x00,0x08,0x08,0x07,/*\"劫\",1278*/},{\n\n0x04,0xFB,0xAA,0xAE,0xAA,0xFC,0x03,0xFA,0x0E,0x0A,0xFA,0x00,0x0F,0x08,0x05,0x02,\n0x04,0x00,0x0F,0x00,0x02,0x03,/*\"節\",1279*/},{\n\n0x88,0x68,0xFF,0x28,0x44,0xA4,0xA4,0xBF,0xA4,0xA4,0x04,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"桔\",1280*/},{\n\n0x10,0xFC,0x8B,0xC4,0xAB,0x92,0xCE,0x98,0x92,0xFF,0x92,0x00,0x0F,0x04,0x04,0x02,\n0x01,0x0F,0x01,0x02,0x04,0x04,/*\"傑\",1281*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xAA,0xAA,0xFF,0xAA,0xFA,0x22,0x00,0x08,0x0F,0x00,0x08,\n0x06,0x08,0x0F,0x0A,0x0A,0x0A,/*\"捷\",1282*/},{\n\n0xFE,0x92,0xFE,0x20,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x22,0x0F,0x04,0x0F,0x08,0x06,\n0x08,0x0F,0x0A,0x0A,0x0A,0x08,/*\"睫\",1283*/},{\n\n0x28,0xC9,0x0A,0xE8,0x80,0x5F,0x75,0xD5,0x55,0x5F,0xC0,0x04,0x04,0x02,0x02,0x00,\n0x06,0x05,0x04,0x09,0x08,0x07,/*\"竭\",1284*/},{\n\n0x22,0x44,0x00,0x22,0xAA,0xFF,0xAA,0xA2,0x5E,0x22,0x3E,0x04,0x02,0x01,0x0A,0x06,\n0x0A,0x0F,0x02,0x06,0x0B,0x02,/*\"潔\",1285*/},{\n\n0xD8,0xB4,0x93,0xC8,0x04,0xA4,0xA4,0xBF,0xA4,0xA4,0x04,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"結\",1286*/},{\n\n0x08,0xF4,0x53,0xFA,0x56,0xF0,0x89,0x67,0x41,0xE9,0x4F,0x08,0x07,0x01,0x07,0x09,\n0x0F,0x00,0x02,0x02,0x0F,0x02,/*\"解\",1287*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFE,0x92,0x92,0x92,0xFE,0x00,0x08,0x05,0x02,0x05,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"姐\",1288*/},{\n\n0x44,0x44,0xF4,0x44,0xF4,0x44,0x44,0xFF,0x04,0xC5,0x34,0x08,0x04,0x03,0x00,0x0F,\n0x00,0x08,0x04,0x03,0x04,0x0E,/*\"戒\",1289*/},{\n\n0x8A,0xAA,0xFE,0xAB,0x02,0xAA,0xBE,0xAB,0xBE,0xAA,0x22,0x04,0x02,0x0F,0x02,0x04,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"藉\",1290*/},{\n\n0x42,0x42,0x22,0xA7,0x12,0x0A,0x12,0xA7,0x22,0x42,0x42,0x00,0x08,0x04,0x03,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"芥\",1291*/},{\n\n0x80,0x9F,0x95,0x55,0x55,0x3F,0x55,0x55,0x95,0x9F,0x80,0x00,0x08,0x04,0x03,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"界\",1292*/},{\n\n0x10,0xFC,0x03,0x10,0xD4,0x5F,0x54,0x54,0x5F,0xD4,0x10,0x00,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"借\",1293*/},{\n\n0x20,0x20,0x10,0xC8,0x04,0x03,0x04,0xC8,0x10,0x20,0x20,0x00,0x08,0x06,0x01,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"介\",1294*/},{\n\n0x08,0x90,0xFC,0x44,0x24,0x95,0x0E,0x14,0xA4,0x44,0x44,0x09,0x04,0x03,0x08,0x04,\n0x03,0x00,0x00,0x0F,0x00,0x00,/*\"疥\",1295*/},{\n\n0x55,0x56,0x54,0x40,0xF4,0x44,0xF4,0x44,0xFF,0x84,0x65,0x0F,0x05,0x0F,0x04,0x03,\n0x00,0x0B,0x04,0x03,0x05,0x0E,/*\"誡\",1296*/},{\n\n0x00,0x00,0xFF,0x05,0xE5,0x05,0x45,0xF5,0x45,0x05,0xE7,0x08,0x06,0x01,0x00,0x07,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"屆\",1297*/},{\n\n0x00,0xFC,0x04,0x04,0x04,0xFF,0x04,0x04,0x04,0xFC,0x00,0x00,0x03,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x02,0x03,0x00,/*\"巾\",1298*/},{\n\n0x04,0xF3,0x56,0x5A,0xF2,0x00,0x24,0xF3,0x26,0x2A,0xE2,0x08,0x07,0x01,0x09,0x0F,\n0x08,0x06,0x01,0x08,0x08,0x07,/*\"筋\",1299*/},{\n\n0x00,0xFE,0x22,0x22,0x22,0x22,0x22,0xE1,0x21,0x21,0x20,0x08,0x07,0x00,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"斤\",1300*/},{\n\n0x10,0x90,0x88,0x94,0x92,0xF1,0x92,0x94,0x88,0x90,0x10,0x08,0x08,0x0A,0x0C,0x08,\n0x0F,0x08,0x0C,0x0A,0x08,0x08,/*\"金\",1301*/},{\n\n0x10,0x90,0x88,0x84,0x92,0xA1,0x82,0x84,0x88,0x10,0x10,0x00,0x00,0x00,0x00,0x00,\n0x08,0x04,0x02,0x01,0x00,0x00,/*\"今\",1302*/},{\n\n0x22,0x44,0x00,0x08,0xAA,0xAA,0xFF,0xAA,0xAA,0xBE,0x08,0x04,0x02,0x01,0x02,0x02,\n0x02,0x0F,0x02,0x02,0x02,0x02,/*\"津\",1303*/},{\n\n0x84,0x45,0xF6,0xAC,0x0A,0x5F,0x52,0x4A,0x5F,0x4A,0x12,0x00,0x00,0x0F,0x00,0x05,\n0x03,0x09,0x0F,0x01,0x03,0x05,/*\"襟\",1304*/},{\n\n0x3F,0x25,0xA5,0xF7,0xAD,0x80,0xA1,0x57,0x09,0x15,0x23,0x00,0x0A,0x06,0x02,0x0B,\n0x0E,0x02,0x02,0x07,0x0A,0x00,/*\"緊\",1305*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x80,0xBE,0xAA,0xEB,0xAA,0xBE,0x80,0x08,0x09,0x07,0x04,0x07,\n0x00,0x00,0x0F,0x00,0x04,0x07,/*\"錦\",1306*/},{\n\n0x20,0x10,0xFC,0x03,0xE2,0xAF,0xAA,0xFA,0xAA,0xAF,0xE2,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"僅\",1307*/},{\n\n0x55,0x56,0x54,0x00,0xE2,0xAF,0xAA,0xFA,0xAA,0xAF,0xE2,0x0F,0x05,0x0F,0x00,0x0A,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"謹\",1308*/},{\n\n0x10,0x11,0xF2,0x08,0xFC,0x57,0x54,0xFD,0x56,0x54,0x04,0x08,0x04,0x03,0x04,0x0B,\n0x09,0x09,0x09,0x09,0x09,0x09,/*\"進\",1309*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x00,0xFE,0x12,0x12,0xF1,0x11,0x02,0x02,0x0F,0x02,0x0A,\n0x04,0x03,0x00,0x00,0x0F,0x00,/*\"靳\",1310*/},{\n\n0x20,0xAD,0xAB,0xA9,0xAD,0xA1,0xAD,0xAB,0xA9,0xAD,0x20,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"晉\",1311*/},{\n\n0x12,0x4A,0x7F,0x4A,0x52,0x40,0x52,0x4A,0x7F,0x4A,0x12,0x01,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x01,/*\"禁\",1312*/},{\n\n0x10,0x11,0xF2,0x00,0x00,0xFE,0x12,0x12,0xF1,0x11,0x10,0x08,0x04,0x03,0x04,0x0A,\n0x09,0x08,0x08,0x0B,0x08,0x08,/*\"近\",1313*/},{\n\n0x38,0xFF,0x04,0x88,0xAA,0xAA,0xFF,0xAA,0xAA,0xBE,0x88,0x06,0x01,0x0A,0x0E,0x0B,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x09,/*\"燼\",1314*/},{\n\n0x11,0x22,0x00,0xC0,0x51,0x55,0x55,0x55,0x55,0x5F,0xC0,0x04,0x02,0x00,0x08,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"浸\",1315*/},{\n\n0x88,0xAA,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xBE,0x88,0x08,0x0E,0x0B,0x0A,0x0F,\n0x0A,0x0F,0x0A,0x0B,0x0E,0x08,/*\"盡\",1316*/},{\n\n0x92,0xAA,0x92,0xAA,0x92,0xAA,0x00,0x08,0xFF,0x08,0xF8,0x08,0x08,0x08,0x07,0x04,\n0x04,0x08,0x06,0x09,0x08,0x07,/*\"勁\",1317*/},{\n\n0x92,0xF2,0x92,0x97,0xF2,0x92,0x02,0xE7,0x02,0x02,0xFA,0x08,0x07,0x00,0x00,0x0F,\n0x00,0x00,0x03,0x08,0x08,0x0F,/*\"荊\",1318*/},{\n\n0xF4,0x94,0x9F,0x94,0xF4,0x00,0xF4,0x94,0x9F,0x94,0xF4,0x08,0x07,0x00,0x0F,0x04,\n0x08,0x04,0x02,0x07,0x08,0x0C,/*\"兢\",1319*/},{\n\n0x02,0x4A,0xAA,0x0F,0x4A,0xAA,0x0A,0x4F,0xAA,0x0A,0x02,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0E,0x0A,0x0A,0x0A,0x0A,0x08,/*\"莖\",1320*/},{\n\n0xFE,0x92,0xFE,0x00,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x0F,0x04,0x0F,0x00,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"睛\",1321*/},{\n\n0xC0,0x40,0x5F,0x55,0xD5,0x15,0xD5,0x55,0x5F,0x40,0xC0,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x0F,0x05,0x05,0x05,0x0F,/*\"晶\",1322*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x04,0xF4,0x95,0x96,0x94,0xF4,0x0D,0x01,0x0D,0x01,0x0D,\n0x04,0x02,0x08,0x0F,0x02,0x04,/*\"鯨\",1323*/},{\n\n0x04,0xF4,0x94,0x94,0x95,0x96,0x94,0x94,0x94,0xF4,0x04,0x08,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x08,/*\"京\",1324*/},{\n\n0x12,0xBF,0xAA,0xBA,0xCF,0xBA,0xC4,0xAB,0x92,0xAE,0x42,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0A,0x0A,0x06,/*\"驚\",1325*/},{\n\n0x24,0xA8,0xFF,0x24,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x01,0x00,0x0F,0x01,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"精\",1326*/},{\n\n0x24,0xA8,0xFF,0x24,0xFA,0xAA,0xAA,0xFE,0xAA,0xAA,0xFA,0x01,0x00,0x0F,0x01,0x08,\n0x05,0x02,0x05,0x08,0x08,0x08,/*\"粳\",1327*/},{\n\n0xD8,0xB4,0x93,0xC8,0x12,0xAA,0x92,0xAA,0x92,0xAA,0x02,0x0C,0x02,0x04,0x02,0x0C,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"經\",1328*/},{\n\n0x80,0x88,0x88,0xFF,0x88,0x88,0x88,0xFF,0x88,0x88,0x80,0x00,0x08,0x04,0x03,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"井\",1329*/},{\n\n0x92,0xBF,0xAA,0xBA,0xCF,0xBA,0xC4,0xAB,0x92,0xAE,0xC2,0x00,0x02,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x02,0x00,/*\"警\",1330*/},{\n\n0x40,0x40,0xDF,0x55,0x55,0x75,0x55,0x55,0xDF,0x40,0x40,0x00,0x08,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x08,0x00,/*\"景\",1331*/},{\n\n0x92,0xAA,0x92,0xAA,0x92,0xAA,0x00,0xFA,0xAE,0xAA,0xFA,0x08,0x08,0x08,0x07,0x04,\n0x04,0x00,0x0B,0x06,0x06,0x0B,/*\"頸\",1332*/},{\n\n0x22,0xEA,0xBF,0xEA,0x22,0x56,0x5A,0xF6,0x59,0xF5,0x40,0x00,0x0F,0x02,0x0F,0x00,\n0x01,0x09,0x0F,0x01,0x03,0x00,/*\"靜\",1333*/},{\n\n0x10,0xFF,0x10,0x08,0xEA,0xAE,0xAB,0xAA,0xAE,0xEA,0x08,0x04,0x07,0x02,0x08,0x0B,\n0x06,0x02,0x02,0x0E,0x0B,0x0C,/*\"境\",1334*/},{\n\n0x22,0xD7,0x5A,0xD2,0x17,0xF2,0x10,0xEF,0x08,0xF8,0x08,0x00,0x07,0x02,0x0B,0x08,\n0x07,0x08,0x05,0x02,0x05,0x08,/*\"敬\",1335*/},{\n\n0x4A,0xF9,0x4A,0x08,0xEA,0xAE,0xAB,0xAA,0xAE,0xEA,0x08,0x0A,0x0F,0x05,0x08,0x0B,\n0x06,0x02,0x02,0x0E,0x0B,0x0C,/*\"鏡\",1336*/},{\n\n0x48,0x24,0xF2,0x09,0x12,0xAA,0x92,0xAA,0x92,0xAA,0x02,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"徑\",1337*/},{\n\n0x08,0x90,0xFE,0x02,0x4A,0xAA,0x4B,0xAA,0x4A,0xAA,0x0A,0x09,0x04,0x03,0x08,0x0A,\n0x0A,0x0A,0x0E,0x0A,0x0A,0x0A,/*\"痙\",1338*/},{\n\n0x28,0xC9,0x0A,0xE8,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x04,0x04,0x02,0x02,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"靖\",1339*/},{\n\n0x08,0xEA,0xAA,0xAE,0xAA,0xAB,0xAA,0xAE,0xAA,0xEA,0x08,0x08,0x0B,0x0A,0x06,0x02,\n0x02,0x02,0x06,0x0A,0x0B,0x0C,/*\"竟\",1340*/},{\n\n0xD2,0x56,0x5B,0x56,0xD2,0x00,0xD2,0x56,0x5B,0x56,0xD2,0x09,0x07,0x01,0x0F,0x05,\n0x08,0x05,0x03,0x07,0x09,0x0D,/*\"競\",1341*/},{\n\n0x11,0x22,0x40,0x56,0x5A,0x56,0xFA,0x52,0x59,0xF5,0x40,0x04,0x02,0x00,0x01,0x09,\n0x09,0x0F,0x01,0x01,0x03,0x00,/*\"淨\",1342*/},{\n\n0x78,0x00,0xFF,0x08,0xFE,0x02,0xF2,0x12,0xF2,0x02,0xFE,0x08,0x06,0x01,0x02,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"炯\",1343*/},{\n\n0x26,0xAA,0xAE,0xEA,0xBA,0xAB,0xAA,0xAA,0xFE,0x2A,0x26,0x04,0x02,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"窘\",1344*/},{\n\n0x88,0x88,0xFF,0x48,0x92,0xFE,0x51,0x08,0xFF,0x10,0x0C,0x00,0x08,0x0F,0x01,0x00,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"揪\",1345*/},{\n\n0x0C,0xA4,0x94,0x8C,0xE5,0x86,0x84,0x8C,0x14,0x24,0x0C,0x08,0x08,0x04,0x02,0x01,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"究\",1346*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0xFC,0x00,0x80,0x40,0xFF,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x01,0x01,0x00,0x00,0x0F,/*\"糾\",1347*/},{\n\n0x22,0x22,0xFE,0x22,0x20,0x18,0x07,0x84,0x64,0x1C,0x00,0x04,0x04,0x03,0x02,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"玖\",1348*/},{\n\n0x24,0x24,0x24,0xFF,0x00,0x00,0x00,0xFF,0x24,0x24,0x24,0x09,0x09,0x09,0x0F,0x08,\n0x08,0x08,0x0F,0x09,0x09,0x09,/*\"韭\",1349*/},{\n\n0x40,0x30,0x0F,0x04,0x04,0x84,0x44,0x34,0x0C,0x00,0x00,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"久\",1350*/},{\n\n0x20,0x28,0xA4,0x13,0x12,0xCA,0x0A,0x16,0x12,0xA0,0x00,0x08,0x09,0x04,0x04,0x02,\n0x01,0x02,0x04,0x05,0x08,0x08,/*\"灸\",1351*/},{\n\n0x08,0x08,0x08,0xFF,0x08,0x08,0x08,0xF8,0x00,0x00,0x00,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"九\",1352*/},{\n\n0x22,0x44,0x02,0xFA,0x4A,0x3E,0x0A,0x3E,0x4A,0xFA,0x02,0x04,0x02,0x00,0x0F,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"酒\",1353*/},{\n\n0x00,0xFE,0x02,0xFA,0xAA,0xFA,0x43,0xBA,0x8A,0xBA,0x22,0x08,0x07,0x00,0x0F,0x05,\n0x02,0x0C,0x05,0x02,0x05,0x08,/*\"廄\",1354*/},{\n\n0x28,0x48,0xFF,0x48,0x2A,0x10,0xEF,0x08,0x88,0x78,0x08,0x02,0x09,0x0F,0x01,0x0A,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"救\",1355*/},{\n\n0x22,0x12,0xFA,0xAF,0xAA,0xAA,0xFA,0xAF,0xAA,0xAA,0x8A,0x00,0x0F,0x0A,0x0A,0x0A,\n0x08,0x0A,0x0A,0x0A,0x0F,0x00,/*\"舊\",1356*/},{\n\n0x00,0xFC,0x44,0x42,0x42,0x01,0x00,0x44,0x44,0x44,0xFC,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"臼\",1357*/},{\n\n0x00,0x3E,0xEA,0xAA,0xA9,0xE0,0xAA,0xAA,0xEA,0x3E,0x00,0x0A,0x0A,0x0B,0x06,0x02,\n0x03,0x02,0x02,0x0B,0x0A,0x06,/*\"舅\",1358*/},{\n\n0x48,0x44,0xAB,0x92,0xAA,0xA6,0xA0,0xBF,0xA0,0xA2,0x2C,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"咎\",1359*/},{\n\n0xF4,0x95,0x96,0x94,0xF4,0x08,0xFF,0x08,0xFA,0x0C,0x08,0x06,0x08,0x0F,0x02,0x04,\n0x08,0x07,0x00,0x07,0x08,0x0E,/*\"就\",1360*/},{\n\n0x08,0x90,0xFC,0x04,0x84,0x45,0x36,0x24,0xA4,0x64,0x04,0x09,0x04,0x03,0x08,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"疚\",1361*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x54,0x43,0xFA,0x42,0x52,0xFE,0x02,0x02,0x0F,0x02,0x02,\n0x02,0x01,0x07,0x09,0x0A,0x07,/*\"鞠\",1362*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0xE8,0x27,0x24,0xE4,0x04,0xFC,0x00,0x08,0x0F,0x00,0x00,\n0x03,0x01,0x01,0x09,0x08,0x07,/*\"拘\",1363*/},{\n\n0x10,0x8A,0x44,0xFB,0x00,0xFE,0x92,0x92,0x92,0xFE,0x00,0x01,0x08,0x08,0x07,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"狙\",1364*/},{\n\n0x08,0x90,0xFE,0x02,0xFA,0x4A,0x4B,0x4A,0x4A,0xFA,0x02,0x09,0x04,0x03,0x08,0x0F,\n0x09,0x09,0x09,0x09,0x0F,0x08,/*\"疽\",1365*/},{\n\n0x00,0xFF,0x29,0xA9,0xA9,0xA9,0xF9,0xA9,0xA9,0xAF,0x20,0x08,0x07,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"居\",1366*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x10,0xE8,0x27,0xE4,0x04,0xFC,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x03,0x01,0x09,0x08,0x07,/*\"駒\",1367*/},{\n\n0x92,0xAE,0xCA,0x8F,0xFA,0x8A,0xCA,0xAF,0x0A,0xFA,0x02,0x04,0x02,0x01,0x00,0x0F,\n0x00,0x09,0x0A,0x08,0x07,0x00,/*\"菊\",1368*/},{\n\n0x00,0xFF,0x15,0xD5,0x55,0x55,0x55,0x55,0xD5,0x17,0xF0,0x08,0x07,0x00,0x07,0x02,\n0x02,0x02,0x0A,0x0B,0x08,0x07,/*\"局\",1369*/},{\n\n0xFC,0x04,0x04,0xFC,0x00,0xFE,0x92,0x92,0x92,0xFE,0x00,0x03,0x01,0x01,0x03,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"咀\",1370*/},{\n\n0x48,0x47,0xFC,0x44,0x40,0xFE,0x12,0x12,0x12,0x12,0xF2,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x09,0x09,0x09,0x09,0x09,/*\"矩\",1371*/},{\n\n0x40,0xFE,0x55,0x40,0x6F,0xCA,0x7A,0x40,0x55,0xFF,0x40,0x01,0x04,0x04,0x05,0x05,\n0x0F,0x05,0x05,0x04,0x04,0x01,/*\"舉\",1372*/},{\n\n0x10,0x22,0x04,0x00,0xFE,0x92,0x92,0x92,0x92,0xFE,0x00,0x04,0x02,0x09,0x08,0x0F,\n0x08,0x08,0x08,0x08,0x0F,0x08,/*\"沮\",1373*/},{\n\n0x11,0x9F,0x95,0x95,0xBF,0x89,0x48,0x51,0x55,0x49,0x17,0x0A,0x0A,0x09,0x04,0x02,\n0x0F,0x01,0x02,0x04,0x0A,0x09,/*\"聚\",1374*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xFE,0x12,0x12,0x12,0x12,0xF2,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x09,0x09,0x09,0x09,0x09,/*\"拒\",1375*/},{\n\n0x88,0xFF,0x48,0x00,0xFC,0x54,0x54,0xFF,0x55,0x55,0x6D,0x08,0x0F,0x00,0x04,0x03,\n0x05,0x05,0x0A,0x0F,0x02,0x05,/*\"據\",1376*/},{\n\n0x00,0xFE,0x12,0x12,0x12,0x12,0x12,0x12,0x12,0xF2,0x02,0x00,0x0F,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x09,0x08,/*\"巨\",1377*/},{\n\n0x00,0x00,0xFF,0x55,0x55,0x55,0x55,0x55,0xFF,0x00,0x00,0x01,0x09,0x05,0x01,0x01,\n0x01,0x01,0x01,0x05,0x09,0x01,/*\"具\",1378*/},{\n\n0x00,0x9E,0x12,0xF2,0x9E,0x00,0xFE,0x12,0x12,0x12,0xF2,0x08,0x0F,0x08,0x07,0x04,\n0x00,0x0F,0x09,0x09,0x09,0x09,/*\"距\",1379*/},{\n\n0xCF,0x09,0xF9,0x4F,0x00,0xFF,0x09,0xA9,0xF9,0xA9,0xAF,0x07,0x04,0x03,0x0A,0x04,\n0x03,0x00,0x0F,0x04,0x04,0x0F,/*\"踞\",1380*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xFF,0xA9,0xA9,0xF9,0xA9,0xAF,0x08,0x09,0x07,0x04,0x02,\n0x01,0x0F,0x04,0x04,0x04,0x0F,/*\"鋸\",1381*/},{\n\n0x10,0xFC,0x03,0x00,0xFF,0x55,0x55,0x55,0x55,0xFF,0x00,0x00,0x0F,0x00,0x01,0x09,\n0x05,0x01,0x01,0x05,0x09,0x01,/*\"俱\",1382*/},{\n\n0x08,0x04,0xF3,0x12,0x12,0x12,0x12,0xF2,0x02,0x02,0xFE,0x00,0x00,0x03,0x01,0x01,\n0x01,0x01,0x09,0x08,0x08,0x07,/*\"句\",1383*/},{\n\n0x78,0x00,0xFF,0x84,0xDF,0x75,0x5F,0xC0,0x7F,0x55,0x5F,0x00,0x00,0x0F,0x00,0x0F,\n0x05,0x05,0x07,0x05,0x05,0x04,/*\"懼\",1384*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0xFE,0x12,0x12,0x12,0x12,0xF2,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x09,0x09,0x09,0x09,0x09,/*\"炬\",1385*/},{\n\n0x00,0xFC,0x54,0xFF,0x55,0x55,0x6C,0x00,0xFC,0x00,0xFF,0x02,0x05,0x05,0x0A,0x0F,\n0x02,0x05,0x00,0x01,0x08,0x0F,/*\"劇\",1386*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xF7,0x55,0x55,0x55,0x55,0xF7,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x01,0x01,0x01,0x09,0x0F,/*\"捐\",1387*/},{\n\n0xEE,0xAA,0xAA,0xAA,0xEE,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x0F,0x02,0x02,0x0A,0x0F,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鵑\",1388*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xF7,0x55,0x55,0x55,0x55,0xF7,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x01,0x01,0x01,0x09,0x0F,/*\"娟\",1389*/},{\n\n0x10,0xFC,0x93,0x55,0xB6,0x9C,0x97,0x94,0xB6,0x55,0x90,0x00,0x0F,0x00,0x00,0x07,\n0x08,0x08,0x0A,0x0B,0x0C,0x00,/*\"倦\",1390*/},{\n\n0x48,0x2A,0xFB,0xAA,0xAE,0xAB,0xAA,0xAA,0xFB,0x2A,0x48,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"眷\",1391*/},{\n\n0x90,0x54,0xB5,0x96,0x9C,0x97,0x94,0x96,0x35,0x54,0x90,0x00,0x00,0x07,0x08,0x08,\n0x0A,0x0A,0x09,0x08,0x0C,0x00,/*\"卷\",1392*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0xF7,0x55,0x55,0x55,0x55,0xF7,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x01,0x01,0x01,0x09,0x0F,/*\"絹\",1393*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x2A,0xF2,0x2A,0xA2,0xDE,0x32,0x08,0x0F,0x00,0x08,0x07,\n0x09,0x07,0x09,0x05,0x03,0x0C,/*\"撅\",1394*/},{\n\n0x88,0xFF,0x48,0x80,0x5F,0xF5,0x5F,0x40,0xFF,0x55,0x5F,0x08,0x0F,0x00,0x00,0x08,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"攫\",1395*/},{\n\n0x08,0xFF,0x88,0x40,0x44,0x44,0xFF,0x44,0x44,0x7C,0x40,0x09,0x0F,0x00,0x08,0x04,\n0x03,0x00,0x03,0x04,0x08,0x08,/*\"抉\",1396*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x0A,0xEA,0x8A,0xFA,0x8A,0xEE,0x08,0x0F,0x00,0x08,0x07,\n0x00,0x0E,0x08,0x0F,0x08,0x0E,/*\"掘\",1397*/},{\n\n0x10,0xFC,0x03,0xFE,0x0A,0xEA,0x8A,0xFA,0x8A,0xEA,0x0E,0x00,0x0F,0x04,0x03,0x0E,\n0x08,0x08,0x0F,0x08,0x08,0x0E,/*\"倔\",1398*/},{\n\n0x02,0xBA,0xAE,0xAA,0xBA,0xAE,0x39,0x29,0x2D,0xBB,0x01,0x00,0x0F,0x0A,0x07,0x0A,\n0x03,0x01,0x05,0x09,0x0F,0x01,/*\"爵\",1399*/},{\n\n0x60,0x3F,0xE5,0xA0,0xB5,0xAA,0xB5,0xA0,0xE5,0x3F,0x60,0x08,0x08,0x0B,0x06,0x02,\n0x02,0x06,0x0A,0x0B,0x08,0x0C,/*\"覺\",1400*/},{\n\n0x10,0x21,0x02,0x40,0x44,0x44,0xFF,0x44,0x44,0x7C,0x40,0x04,0x02,0x01,0x08,0x04,\n0x03,0x00,0x03,0x04,0x08,0x08,/*\"決\",1401*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x44,0x44,0xFF,0x44,0x7C,0x40,0x0F,0x05,0x05,0x07,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"訣\",1402*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x10,0xE9,0x27,0xE1,0x29,0xEF,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x07,0x09,0x09,0x09,0x0D,/*\"絕\",1403*/},{\n\n0x08,0x08,0xFF,0x08,0x10,0x08,0x17,0x24,0x84,0x44,0xFC,0x02,0x02,0x01,0x01,0x00,\n0x02,0x02,0x01,0x08,0x08,0x07,/*\"均\",1404*/},{\n\n0x02,0xFA,0x8A,0xAF,0xAA,0xEA,0xAA,0x9F,0x8A,0xFA,0x02,0x00,0x0F,0x0A,0x09,0x08,\n0x0F,0x08,0x09,0x0A,0x0F,0x00,/*\"菌\",1405*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x10,0x08,0x17,0x24,0x84,0xFC,0x08,0x09,0x07,0x05,0x04,\n0x00,0x02,0x02,0x09,0x08,0x07,/*\"鈞\",1406*/},{\n\n0x03,0xF5,0x55,0x55,0x55,0xFF,0x55,0x55,0x55,0xF5,0x03,0x04,0x05,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x05,0x04,/*\"軍\",1407*/},{\n\n0x08,0x2A,0xAA,0xEA,0xBE,0xAA,0xAA,0xAA,0xAA,0xBE,0x08,0x02,0x01,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"君\",1408*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x20,0x96,0x65,0x44,0xD6,0x2C,0x07,0x04,0x03,0x02,0x07,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"峻\",1409*/},{\n\n0x20,0x10,0xFC,0x03,0x24,0x96,0x65,0x44,0x44,0xD6,0x2C,0x00,0x00,0x0F,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"俊\",1410*/},{\n\n0xE9,0x0A,0xE8,0x00,0x24,0x96,0x65,0x44,0x44,0xD6,0x2C,0x04,0x05,0x02,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"竣\",1411*/},{\n\n0x22,0x44,0x00,0x24,0x96,0x6D,0x44,0x44,0xCC,0x16,0x2C,0x04,0x02,0x08,0x09,0x04,\n0x05,0x02,0x05,0x04,0x08,0x08,/*\"浚\",1412*/},{\n\n0xAA,0xEA,0xBE,0xAA,0xAA,0xBE,0x08,0xFE,0x02,0x32,0xCE,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x00,0x0F,0x02,0x02,0x01,/*\"郡\",1413*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x20,0x96,0x65,0x44,0xD6,0x2C,0x06,0x00,0x0A,0x08,0x07,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"駿\",1414*/},{\n\n0xFE,0x02,0xFE,0x00,0x46,0xD2,0xAE,0xAB,0xAA,0xDA,0x46,0x03,0x01,0x03,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"喀\",1415*/},{\n\n0xFC,0x04,0xFC,0x08,0xFF,0x08,0xF8,0x00,0xFC,0x04,0xFC,0x03,0x01,0x09,0x04,0x03,\n0x08,0x0F,0x00,0x0F,0x04,0x0F,/*\"咖\",1416*/},{\n\n0x20,0x20,0x20,0x20,0xFF,0xA4,0xA4,0x24,0x24,0x24,0x20,0x00,0x00,0x00,0x00,0x0F,\n0x00,0x00,0x01,0x01,0x02,0x00,/*\"卡\",1417*/},{\n\n0xFE,0x02,0xFE,0x28,0xA4,0xAB,0x92,0x92,0xAA,0xA6,0x20,0x03,0x01,0x03,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"咯\",1418*/},{\n\n0xFF,0x15,0x15,0x5F,0xC0,0x40,0xC0,0x5F,0x15,0x15,0xFF,0x0F,0x00,0x01,0x09,0x07,\n0x01,0x0F,0x01,0x01,0x08,0x0F,/*\"開\",1419*/},{\n\n0x88,0x88,0xFF,0x48,0xDF,0x52,0x4A,0x60,0x4F,0x52,0xD9,0x00,0x08,0x0F,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"揩\",1420*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xDF,0x52,0x6A,0x4F,0x52,0xD9,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"楷\",1421*/},{\n\n0xD6,0x54,0x57,0x54,0xD6,0x00,0xFE,0x02,0xFE,0x00,0x00,0x09,0x0B,0x05,0x07,0x0D,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"凱\",1422*/},{\n\n0x30,0xFF,0x08,0xFE,0x92,0xFE,0x00,0x3A,0xA2,0x7E,0x22,0x00,0x0F,0x00,0x0F,0x0A,\n0x04,0x08,0x06,0x01,0x0F,0x08,/*\"慨\",1423*/},{\n\n0x20,0x22,0x22,0xFE,0x22,0x22,0x20,0xFC,0x00,0x00,0xFF,0x00,0x00,0x00,0x0F,0x00,\n0x00,0x00,0x01,0x08,0x08,0x0F,/*\"刊\",1424*/},{\n\n0x10,0xFF,0x10,0x80,0x82,0xFF,0xAA,0xAA,0xAA,0xFF,0x82,0x04,0x07,0x02,0x00,0x0F,\n0x0A,0x09,0x08,0x09,0x0A,0x08,/*\"堪\",1425*/},{\n\n0x80,0x82,0xFF,0xAA,0xAA,0xFF,0x82,0x08,0xFF,0x08,0xF8,0x00,0x0F,0x0A,0x09,0x08,\n0x09,0x0A,0x06,0x09,0x08,0x07,/*\"勘\",1426*/},{\n\n0x08,0x08,0xFF,0x08,0x20,0x18,0x07,0xE4,0x04,0x14,0x0C,0x02,0x02,0x01,0x01,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"坎\",1427*/},{\n\n0x42,0xF2,0x2E,0xE2,0x20,0x18,0x07,0xE4,0x04,0x14,0x0C,0x00,0x07,0x02,0x07,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"砍\",1428*/},{\n\n0x20,0xAA,0xEA,0xAA,0xBA,0xAE,0xA9,0xA9,0xA9,0xE9,0x20,0x01,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"看\",1429*/},{\n\n0x00,0xFE,0x22,0xAA,0xAA,0xAB,0xFE,0xAA,0xAA,0xFA,0x22,0x08,0x07,0x00,0x0A,0x04,\n0x0A,0x0F,0x02,0x04,0x0A,0x08,/*\"康\",1430*/},{\n\n0x30,0xFF,0x08,0xFE,0x22,0xAA,0xAA,0xFF,0xAA,0xFA,0x22,0x00,0x0F,0x08,0x07,0x08,\n0x05,0x0A,0x0F,0x02,0x05,0x08,/*\"慷\",1431*/},{\n\n0x24,0xA8,0xFF,0x24,0xFE,0x22,0xAA,0xFF,0xAA,0xFA,0x22,0x01,0x00,0x0F,0x09,0x07,\n0x05,0x0A,0x0F,0x02,0x05,0x08,/*\"糠\",1432*/},{\n\n0x88,0x88,0xFF,0x48,0x48,0x02,0x02,0xFE,0x02,0x02,0x00,0x00,0x08,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"扛\",1433*/},{\n\n0x88,0x88,0xFF,0x48,0x04,0xE4,0x25,0x26,0xE4,0x04,0x04,0x00,0x08,0x0F,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"抗\",1434*/},{\n\n0x04,0x04,0xE4,0x24,0x25,0x26,0x24,0xE4,0x04,0x04,0x04,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"亢\",1435*/},{\n\n0x78,0x00,0xFF,0x10,0x0C,0xE4,0x25,0x26,0xE4,0x04,0x04,0x08,0x06,0x01,0x0A,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"炕\",1436*/},{\n\n0x10,0x14,0x94,0xD4,0x7F,0x54,0x5C,0x54,0x52,0x50,0x10,0x02,0x01,0x00,0x01,0x01,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"考\",1437*/},{\n\n0x88,0xFF,0x48,0x00,0x94,0xD4,0x7F,0x54,0x58,0x54,0x12,0x08,0x0F,0x00,0x01,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"拷\",1438*/},{\n\n0x78,0x00,0xFF,0x08,0x94,0xD4,0x7F,0x54,0x58,0x54,0x12,0x08,0x06,0x01,0x03,0x04,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"烤\",1439*/},{\n\n0x88,0x8C,0xBB,0xAA,0xEA,0x2F,0xEA,0xAA,0xBA,0x8A,0x88,0x02,0x02,0x02,0x02,0x0F,\n0x00,0x0F,0x02,0x02,0x02,0x02,/*\"靠\",1440*/},{\n\n0x10,0xFF,0x10,0x02,0xF2,0x12,0x12,0xF2,0x02,0xFE,0x02,0x04,0x07,0x02,0x00,0x03,\n0x01,0x01,0x09,0x08,0x0F,0x00,/*\"坷\",1441*/},{\n\n0x12,0xD2,0x52,0x57,0x52,0xD2,0x12,0x17,0xF2,0x12,0x12,0x00,0x07,0x02,0x02,0x02,\n0x03,0x08,0x08,0x0F,0x00,0x00,/*\"苛\",1442*/},{\n\n0x88,0x68,0xFF,0x28,0x42,0xF2,0x12,0xF2,0x02,0xFE,0x02,0x00,0x00,0x0F,0x00,0x00,\n0x03,0x01,0x01,0x08,0x0F,0x00,/*\"柯\",1443*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0x5F,0x55,0xFF,0x55,0x5F,0x40,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"棵\",1444*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x4A,0x6A,0x5F,0x4A,0x6A,0x00,0x00,0x07,0x02,0x07,0x08,\n0x0F,0x09,0x0F,0x09,0x0F,0x08,/*\"磕\",1445*/},{\n\n0xBE,0xAA,0xFE,0xAA,0xBE,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x04,0x02,0x0F,0x02,0x04,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"顆\",1446*/},{\n\n0x12,0xD2,0xFE,0x51,0x90,0x12,0x24,0x00,0xFF,0x80,0x80,0x01,0x00,0x0F,0x00,0x00,\n0x01,0x01,0x01,0x0F,0x00,0x00,/*\"科\",1447*/},{\n\n0x62,0xAA,0xAA,0xAF,0xAA,0x62,0x08,0xE7,0x21,0xEF,0x08,0x08,0x06,0x02,0x02,0x0E,\n0x04,0x08,0x05,0x02,0x05,0x08,/*\"殼\",1448*/},{\n\n0xFC,0x04,0xFC,0x00,0x24,0x34,0xAD,0x66,0x24,0x94,0x44,0x03,0x01,0x03,0x00,0x09,\n0x09,0x04,0x02,0x03,0x04,0x08,/*\"咳\",1449*/},{\n\n0x02,0xF2,0x12,0x12,0x12,0x12,0xF2,0x02,0x02,0xFE,0x02,0x00,0x03,0x01,0x01,0x01,\n0x01,0x01,0x08,0x08,0x0F,0x00,/*\"可\",1450*/},{\n\n0x11,0x22,0x00,0x80,0x5F,0x75,0x55,0xD5,0x55,0x5F,0xC0,0x04,0x02,0x00,0x00,0x06,\n0x04,0x05,0x04,0x01,0x08,0x0F,/*\"渴\",1451*/},{\n\n0x04,0xF4,0x94,0x94,0x94,0x9F,0x94,0x94,0x94,0xF4,0x04,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"克\",1452*/},{\n\n0x00,0x24,0x34,0xAD,0x66,0x24,0x94,0x00,0xFC,0x00,0xFF,0x08,0x09,0x09,0x04,0x02,\n0x05,0x08,0x00,0x01,0x08,0x0F,/*\"刻\",1453*/},{\n\n0x86,0xA2,0x92,0xAE,0x4A,0x4B,0x4A,0xAA,0x9A,0x82,0x86,0x00,0x00,0x0F,0x05,0x05,\n0x05,0x05,0x05,0x0F,0x00,0x00,/*\"客\",1454*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x5F,0x55,0xFF,0x55,0x5F,0x40,0x0F,0x05,0x05,0x0F,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"課\",1455*/},{\n\n0x08,0xE8,0xAE,0xA8,0xA8,0xAF,0xAA,0xAA,0xAA,0xEA,0x08,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"肯\",1456*/},{\n\n0xFE,0x02,0xFE,0x08,0xEE,0xA8,0xA8,0xAF,0xAA,0xEA,0x08,0x03,0x01,0x03,0x00,0x0F,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"啃\",1457*/},{\n\n0x52,0xB6,0x5A,0x2D,0xC9,0x04,0xFF,0x95,0x35,0x5F,0xA0,0x09,0x0A,0x0A,0x0B,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"墾\",1458*/},{\n\n0x52,0xB6,0x5A,0x2D,0xC9,0x04,0xFF,0x95,0x35,0x5F,0xA0,0x09,0x06,0x00,0x07,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"懇\",1459*/},{\n\n0x10,0xFF,0x10,0x00,0x04,0xE4,0x25,0x26,0xE4,0x04,0x04,0x04,0x07,0x02,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"坑\",1460*/},{\n\n0xFC,0x04,0xFC,0x00,0x04,0xE4,0x25,0x26,0xE4,0x04,0x04,0x03,0x01,0x03,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"吭\",1461*/},{\n\n0x0C,0xA4,0x94,0x8C,0x85,0x86,0x84,0x8C,0x94,0xA4,0x0C,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"空\",1462*/},{\n\n0x21,0x21,0x3F,0x51,0x20,0x9F,0x05,0x09,0x3F,0x40,0x70,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"恐\",1463*/},{\n\n0x80,0x82,0x82,0xF2,0x4A,0x46,0x00,0xFF,0x00,0x00,0x00,0x00,0x08,0x08,0x0F,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"孔\",1464*/},{\n\n0x88,0xFF,0x48,0x00,0x4C,0xA4,0x95,0x86,0x94,0xA4,0x4C,0x08,0x0F,0x00,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"控\",1465*/},{\n\n0x88,0xFF,0x48,0xFE,0x82,0xBA,0xAA,0x2A,0xAA,0xBA,0x82,0x08,0x0F,0x00,0x0F,0x0B,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"摳\",1466*/},{\n\n0x00,0xFE,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0xFE,0x00,0x00,0x07,0x02,0x02,0x02,\n0x02,0x02,0x02,0x02,0x07,0x00,/*\"口\",1467*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xFC,0x04,0x04,0x04,0x04,0xFC,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"扣\",1468*/},{\n\n0x86,0x92,0x92,0x92,0x82,0x23,0xA2,0x3E,0xAA,0x6A,0x06,0x08,0x07,0x00,0x07,0x08,\n0x0C,0x0A,0x09,0x0E,0x08,0x0C,/*\"寇\",1469*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xC8,0x48,0x7F,0x48,0xC8,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"枯\",1470*/},{\n\n0x40,0x4F,0x49,0x49,0x4F,0xF0,0x4F,0x49,0x59,0x6F,0x40,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"哭\",1471*/},{\n\n0x06,0xFA,0x2A,0xAE,0x2A,0x2B,0xEA,0x2E,0x2A,0xBA,0x06,0x08,0x07,0x00,0x0D,0x09,\n0x09,0x0F,0x09,0x09,0x0D,0x00,/*\"窟\",1472*/},{\n\n0x12,0x92,0x97,0x92,0x92,0xFA,0x92,0x92,0x97,0x92,0x12,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"苦\",1473*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x28,0xA6,0xA4,0xBF,0xA4,0xA4,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"酷\",1474*/},{\n\n0x00,0xFE,0x02,0xEA,0xAA,0xAA,0xFF,0xAA,0xAA,0xEA,0x02,0x08,0x07,0x02,0x03,0x02,\n0x02,0x0F,0x02,0x02,0x03,0x02,/*\"庫\",1475*/},{\n\n0x45,0xF6,0xAC,0xFE,0x02,0xEA,0xAA,0xFF,0xAA,0xEA,0x02,0x00,0x0F,0x08,0x07,0x02,\n0x03,0x02,0x0F,0x02,0x03,0x02,/*\"褲\",1476*/},{\n\n0x55,0x56,0x54,0x00,0x52,0xCA,0x56,0x53,0x56,0x4A,0x52,0x0F,0x05,0x0F,0x00,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"誇\",1477*/},{\n\n0x08,0x08,0xFF,0x08,0x52,0xCA,0x56,0x53,0x56,0x4A,0x52,0x02,0x02,0x01,0x01,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"垮\",1478*/},{\n\n0x08,0x08,0xFF,0x88,0x52,0xCA,0x56,0x53,0x56,0x4A,0x52,0x01,0x09,0x0F,0x00,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"挎\",1479*/},{\n\n0x9E,0x12,0xF2,0x9E,0x50,0xCA,0x56,0x53,0x56,0x4A,0x52,0x0F,0x08,0x07,0x04,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"跨\",1480*/},{\n\n0x00,0xFE,0x92,0xFE,0x50,0xCA,0x56,0x53,0x56,0x4A,0x52,0x08,0x07,0x08,0x0F,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"胯\",1481*/},{\n\n0x08,0x08,0xFF,0x08,0x7C,0x54,0xF6,0x5D,0xD4,0x7C,0x00,0x02,0x02,0x01,0x09,0x04,\n0x03,0x00,0x07,0x0A,0x0B,0x0C,/*\"塊\",1482*/},{\n\n0xE4,0x03,0xFA,0x26,0x02,0x24,0xFB,0x22,0x26,0xE2,0x02,0x01,0x00,0x0F,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"筷\",1483*/},{\n\n0x20,0x10,0xFC,0x03,0xF4,0xB2,0xD5,0xF5,0xD5,0xB2,0xF4,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"儈\",1484*/},{\n\n0x78,0x00,0xFF,0x48,0x44,0x44,0xFF,0x44,0x44,0x7C,0x40,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x03,0x04,0x08,0x08,/*\"快\",1485*/},{\n\n0x06,0xEA,0xAA,0xBE,0xAA,0xAB,0xAA,0xBE,0xAA,0xEA,0x06,0x08,0x0B,0x0A,0x06,0x02,\n0x02,0x06,0x0A,0x0E,0x0B,0x0C,/*\"寬\",1486*/},{\n\n0x82,0xAA,0xAA,0xAF,0xAA,0xAA,0x92,0x0F,0xC4,0x14,0x0C,0x04,0x02,0x08,0x0F,0x00,\n0x02,0x0C,0x06,0x01,0x06,0x08,/*\"款\",1487*/},{\n\n0x00,0xFF,0x01,0x05,0x25,0x25,0xFD,0x25,0x25,0x05,0x01,0x00,0x0F,0x08,0x0A,0x0A,\n0x0A,0x0B,0x0A,0x0A,0x0A,0x08,/*\"匡\",1488*/},{\n\n0x04,0xFB,0x0A,0x2E,0xAA,0xAC,0xEB,0xAA,0xAE,0xAA,0x0A,0x00,0x0F,0x08,0x0A,0x0A,\n0x0A,0x0B,0x0A,0x0A,0x0A,0x0A,/*\"筐\",1489*/},{\n\n0x8A,0x44,0xFB,0x00,0x42,0x42,0x42,0xFE,0x42,0x42,0x42,0x08,0x08,0x07,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"狂\",1490*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x02,0x4A,0x4A,0xFA,0x4A,0x4A,0x00,0x00,0x0F,0x00,0x0F,\n0x08,0x0A,0x0A,0x0B,0x0A,0x0A,/*\"框\",1491*/},{\n\n0xF2,0x2E,0xE2,0x00,0xFE,0x22,0xEA,0xBE,0xEB,0xBE,0xEA,0x07,0x02,0x03,0x08,0x07,\n0x00,0x0B,0x06,0x03,0x06,0x0B,/*\"礦\",1492*/},{\n\n0xFE,0x92,0xFE,0x00,0xFE,0x02,0x4A,0x4A,0xFA,0x4A,0x4A,0x0F,0x04,0x0F,0x00,0x0F,\n0x08,0x0A,0x0A,0x0B,0x0A,0x0A,/*\"眶\",1493*/},{\n\n0xFE,0x22,0xFE,0x00,0xFE,0x22,0xEA,0xBE,0xEB,0xBE,0xEA,0x07,0x02,0x03,0x08,0x07,\n0x00,0x0B,0x06,0x03,0x06,0x0B,/*\"曠\",1494*/},{\n\n0x22,0x44,0x00,0x7E,0x42,0xC2,0x42,0xC2,0x42,0x7E,0x00,0x04,0x02,0x08,0x04,0x02,\n0x01,0x00,0x07,0x08,0x08,0x0E,/*\"況\",1495*/},{\n\n0x00,0xFC,0xA4,0xFF,0x55,0xF5,0x4C,0x00,0xD2,0xB2,0x92,0x08,0x07,0x00,0x0F,0x05,\n0x07,0x05,0x00,0x08,0x08,0x07,/*\"虧\",1496*/},{\n\n0x82,0x72,0x0F,0xA2,0x5A,0x22,0x1E,0x22,0x52,0x8A,0x82,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盔\",1497*/},{\n\n0xF8,0xAF,0xBA,0xE2,0x02,0x8B,0xAA,0xAA,0xAA,0xFB,0x80,0x0E,0x08,0x0F,0x0A,0x01,\n0x06,0x02,0x0F,0x02,0x06,0x01,/*\"巋\",1498*/},{\n\n0x86,0xA2,0xFA,0xA6,0x02,0xFB,0xAA,0xAE,0xAA,0xFA,0x06,0x08,0x06,0x01,0x02,0x04,\n0x0B,0x06,0x02,0x06,0x0B,0x0C,/*\"窺\",1499*/},{\n\n0x92,0xAA,0x4A,0x6F,0x5A,0xC2,0x4A,0x57,0x32,0x4A,0xA2,0x00,0x08,0x09,0x05,0x03,\n0x01,0x03,0x05,0x05,0x08,0x00,/*\"葵\",1500*/},{\n\n0x12,0x92,0xAA,0xAA,0xA6,0xFB,0xA6,0xAA,0xAA,0x92,0x12,0x08,0x08,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x08,0x08,/*\"奎\",1501*/},{\n\n0x7C,0x56,0xFD,0x54,0xFC,0x00,0x52,0x64,0x40,0xFF,0x20,0x08,0x07,0x00,0x07,0x0A,\n0x0B,0x08,0x08,0x08,0x0B,0x0C,/*\"魁\",1502*/},{\n\n0x20,0x10,0xFC,0x03,0x7C,0x54,0xF6,0x5D,0xD4,0x7C,0x00,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x07,0x0A,0x0B,0x0C,/*\"傀\",1503*/},{\n\n0x04,0xFA,0xAD,0xFA,0x24,0xEE,0xAA,0xBF,0xAA,0xEE,0x20,0x00,0x0F,0x04,0x02,0x04,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"饋\",1504*/},{\n\n0x78,0x00,0xFF,0x08,0x7C,0x54,0xF6,0x5D,0xD4,0x7C,0x00,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x07,0x0A,0x0B,0x0C,/*\"愧\",1505*/},{\n\n0x22,0x44,0x20,0xEE,0xAA,0xAA,0xBF,0xAA,0xAA,0xEE,0x20,0x04,0x02,0x00,0x0B,0x06,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"潰\",1506*/},{\n\n0x10,0xFF,0x10,0x00,0xFC,0x24,0x24,0xFF,0x24,0x24,0xFC,0x04,0x07,0x02,0x00,0x03,\n0x01,0x01,0x0F,0x01,0x01,0x03,/*\"坤\",1507*/},{\n\n0x00,0xDF,0x95,0x95,0x95,0x15,0xD5,0x15,0x15,0x9F,0x40,0x00,0x0F,0x08,0x04,0x04,\n0x00,0x07,0x09,0x09,0x08,0x0E,/*\"昆\",1508*/},{\n\n0x88,0x88,0xFF,0x48,0xFE,0x92,0x52,0xFE,0x52,0x92,0xFE,0x00,0x08,0x0F,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"捆\",1509*/},{\n\n0xFF,0x01,0x89,0x49,0x29,0xFF,0x29,0x49,0x89,0x01,0xFF,0x0F,0x04,0x04,0x04,0x04,\n0x07,0x04,0x04,0x04,0x04,0x0F,/*\"困\",1510*/},{\n\n0x88,0x88,0xFF,0x48,0x92,0x92,0x92,0xFE,0x91,0x91,0x91,0x00,0x08,0x0F,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"括\",1511*/},{\n\n0x88,0xFF,0x48,0xFE,0x22,0xEA,0xBE,0xEB,0xBE,0xEA,0x22,0x08,0x0F,0x08,0x07,0x00,\n0x0B,0x06,0x03,0x06,0x0B,0x00,/*\"擴\",1512*/},{\n\n0x00,0xFE,0x0A,0xBA,0xAE,0xBA,0x0B,0x02,0xFA,0x4A,0xBA,0x04,0x03,0x02,0x0A,0x0E,\n0x03,0x02,0x00,0x0F,0x02,0x01,/*\"廓\",1513*/},{\n\n0xFF,0x95,0x35,0x5F,0x80,0xA0,0xE0,0x9F,0x95,0x15,0xFF,0x0F,0x00,0x09,0x04,0x00,\n0x0E,0x0B,0x0E,0x00,0x08,0x0F,/*\"闊\",1514*/},{\n\n0x10,0x10,0xFF,0x10,0x00,0x28,0xC8,0x09,0x0A,0xE8,0x08,0x04,0x04,0x03,0x02,0x08,\n0x08,0x09,0x0C,0x0B,0x08,0x08,/*\"垃\",1515*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0x28,0xC8,0x09,0x0A,0xE8,0x08,0x00,0x08,0x0F,0x00,0x08,\n0x08,0x09,0x0C,0x0B,0x08,0x08,/*\"拉\",1516*/},{\n\n0xFE,0x02,0xFE,0x74,0x54,0xFF,0x54,0x74,0xF8,0x00,0xFF,0x03,0x01,0x03,0x02,0x01,\n0x0F,0x01,0x02,0x01,0x08,0x0F,/*\"喇\",1517*/},{\n\n0x78,0x48,0xFF,0x48,0x00,0xFA,0x8D,0xDA,0xAD,0xDA,0xFD,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x0A,0x07,0x0A,0x07,0x0C,/*\"蠟\",1518*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xFA,0x8D,0xDA,0xAD,0xDA,0xFD,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x0A,0x07,0x0A,0x07,0x0C,/*\"臘\",1519*/},{\n\n0x44,0x55,0xE6,0x54,0x00,0x74,0x54,0xFF,0x54,0x54,0x74,0x00,0x09,0x07,0x01,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"辣\",1520*/},{\n\n0xFE,0x02,0xFE,0x88,0xFF,0x48,0x00,0xE8,0x09,0x0A,0xE8,0x03,0x01,0x03,0x08,0x0F,\n0x00,0x08,0x09,0x0C,0x0B,0x08,/*\"啦\",1521*/},{\n\n0x12,0x92,0x72,0x97,0x12,0xFA,0x12,0x97,0x72,0x92,0x12,0x04,0x04,0x02,0x02,0x01,\n0x0F,0x01,0x02,0x02,0x04,0x04,/*\"萊\",1522*/},{\n\n0x40,0x24,0x1C,0x24,0xC4,0xFF,0xC4,0x24,0x1C,0x24,0x40,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"來\",1523*/},{\n\n0x74,0x54,0xFF,0x54,0x74,0x04,0xFA,0xAB,0xAA,0xAE,0xF8,0x02,0x01,0x0F,0x01,0x02,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"賴\",1524*/},{\n\n0x02,0xFA,0xAF,0xBA,0xEA,0x42,0x22,0x3A,0x67,0xA2,0x22,0x08,0x0F,0x0A,0x0B,0x0E,\n0x0A,0x0E,0x0A,0x0A,0x0E,0x08,/*\"藍\",1525*/},{\n\n0x92,0x8A,0xBF,0x8A,0xD2,0x80,0x92,0x8A,0xBF,0x8A,0x92,0x08,0x08,0x0A,0x0B,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x00,/*\"婪\",1526*/},{\n\n0x84,0x64,0xFF,0x24,0xFF,0xD5,0x57,0xF8,0x57,0xD5,0xFF,0x00,0x00,0x0F,0x00,0x0F,\n0x0A,0x06,0x0F,0x06,0x0A,0x0F,/*\"欄\",1527*/},{\n\n0x84,0xFF,0x44,0x00,0xFF,0xD5,0x57,0xF8,0x57,0xD5,0xFF,0x08,0x0F,0x00,0x00,0x0F,\n0x0A,0x06,0x0F,0x06,0x0A,0x0F,/*\"攔\",1528*/},{\n\n0x04,0xFB,0xAA,0xBE,0xEA,0x44,0x23,0x3A,0x66,0xA2,0x22,0x08,0x0F,0x0A,0x0B,0x0E,\n0x0A,0x0E,0x0A,0x0A,0x0E,0x08,/*\"籃\",1529*/},{\n\n0xFF,0x15,0xD5,0xDF,0x50,0xF8,0x50,0xDF,0xD5,0x15,0xFF,0x0F,0x00,0x0B,0x06,0x03,\n0x0F,0x03,0x06,0x0B,0x00,0x0F,/*\"闌\",1530*/},{\n\n0xFA,0xAA,0xAF,0xBA,0x82,0xC2,0x82,0xBA,0xAF,0xAA,0xFA,0x0F,0x00,0x07,0x0D,0x06,\n0x0F,0x06,0x0D,0x07,0x00,0x0F,/*\"蘭\",1531*/},{\n\n0x22,0x44,0xFF,0x05,0xF7,0x94,0xFE,0x54,0xF7,0x05,0xFF,0x04,0x02,0x0F,0x00,0x0B,\n0x06,0x0F,0x06,0x0B,0x00,0x0F,/*\"瀾\",1532*/},{\n\n0x55,0x56,0x54,0x00,0xFF,0xD5,0x57,0xF8,0x57,0xD5,0xFF,0x0F,0x05,0x0F,0x00,0x0F,\n0x0A,0x06,0x0F,0x06,0x0A,0x0F,/*\"讕\",1533*/},{\n\n0x88,0xFF,0x48,0x7F,0xD5,0x77,0xDD,0x4A,0x7B,0xCE,0x7A,0x08,0x0F,0x00,0x08,0x0B,\n0x06,0x02,0x07,0x0A,0x0B,0x0C,/*\"攬\",1534*/},{\n\n0x7F,0xD5,0x77,0xDD,0x48,0x74,0xD3,0x76,0x5A,0xD2,0x72,0x08,0x0B,0x0A,0x06,0x03,\n0x02,0x02,0x07,0x0A,0x0B,0x0C,/*\"覽\",1535*/},{\n\n0x30,0xFF,0x08,0xF4,0x94,0xFF,0x94,0xF4,0xFB,0xAE,0xF8,0x00,0x0F,0x00,0x04,0x02,\n0x0F,0x02,0x04,0x0B,0x06,0x0B,/*\"懶\",1536*/},{\n\n0xDC,0xB3,0xC8,0x7F,0xD5,0x77,0xDD,0x4A,0x7B,0xCE,0x7A,0x0E,0x00,0x06,0x08,0x0B,\n0x06,0x02,0x07,0x0A,0x0B,0x0C,/*\"纜\",1537*/},{\n\n0x78,0x00,0xFF,0x08,0xFF,0xD5,0x57,0xF8,0x57,0xD5,0xFF,0x08,0x06,0x01,0x02,0x0F,\n0x0A,0x06,0x0F,0x06,0x0A,0x0F,/*\"爛\",1538*/},{\n\n0x11,0x22,0x00,0x7F,0x55,0x77,0x5D,0x10,0x0F,0x34,0x04,0x04,0x02,0x08,0x0F,0x09,\n0x0F,0x09,0x0F,0x09,0x0F,0x08,/*\"濫\",1539*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0xFC,0x55,0xD6,0x54,0x7C,0x80,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"琅\",1540*/},{\n\n0x88,0x68,0xFF,0x48,0xFD,0x56,0x7C,0x00,0xFE,0x32,0xCE,0x00,0x00,0x0F,0x00,0x0F,\n0x05,0x02,0x04,0x0F,0x02,0x01,/*\"榔\",1541*/},{\n\n0x10,0x8A,0x44,0xFB,0x00,0xFC,0x55,0xD6,0x54,0x7C,0x80,0x01,0x08,0x08,0x07,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"狼\",1542*/},{\n\n0x00,0xFE,0x02,0xFA,0xAA,0xAE,0xFB,0x02,0xFA,0x4A,0xBA,0x08,0x07,0x00,0x0F,0x04,\n0x02,0x04,0x00,0x0F,0x02,0x01,/*\"廊\",1543*/},{\n\n0x00,0xFC,0x55,0xD6,0x54,0x7C,0x00,0xFE,0x02,0x32,0xCE,0x00,0x0F,0x04,0x02,0x01,\n0x06,0x00,0x0F,0x02,0x02,0x01,/*\"郎\",1544*/},{\n\n0x00,0xFC,0x55,0xD6,0x54,0x7C,0x00,0xFE,0x92,0x92,0xFE,0x00,0x0F,0x04,0x02,0x01,\n0x06,0x08,0x07,0x00,0x08,0x0F,/*\"朗\",1545*/},{\n\n0x22,0x44,0x00,0xFC,0x54,0x55,0xD6,0x54,0x54,0x7C,0x00,0x04,0x02,0x01,0x0F,0x08,\n0x04,0x01,0x02,0x04,0x0A,0x09,/*\"浪\",1546*/},{\n\n0x84,0x84,0xFF,0x44,0x6A,0x27,0xAA,0x21,0x2A,0x27,0x6A,0x00,0x08,0x0F,0x00,0x08,\n0x05,0x03,0x09,0x09,0x07,0x00,/*\"撈\",1547*/},{\n\n0x3A,0x94,0x93,0x94,0xDA,0x90,0x9A,0x94,0x93,0x94,0x3A,0x00,0x08,0x04,0x02,0x01,\n0x00,0x00,0x08,0x08,0x07,0x00,/*\"勞\",1548*/},{\n\n0x06,0x42,0x32,0x22,0x22,0xFB,0x22,0x22,0x22,0x22,0x06,0x01,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"牢\",1549*/},{\n\n0x20,0x24,0x24,0xA4,0xE4,0x3F,0x34,0x2C,0x24,0xA2,0x20,0x04,0x02,0x01,0x00,0x07,\n0x0A,0x0A,0x09,0x09,0x08,0x0E,/*\"老\",1550*/},{\n\n0x20,0x10,0xFC,0x23,0x24,0xA4,0x7F,0x24,0x34,0xA8,0x26,0x00,0x00,0x0F,0x02,0x01,\n0x07,0x0A,0x09,0x09,0x08,0x0C,/*\"佬\",1551*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xA4,0xE4,0x3F,0x34,0xA8,0xA6,0x08,0x05,0x02,0x05,0x09,\n0x00,0x07,0x09,0x09,0x08,0x0C,/*\"姥\",1552*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x44,0xAB,0x92,0x92,0xAE,0x40,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"酪\",1553*/},{\n\n0x78,0x00,0xFF,0x04,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"烙\",1554*/},{\n\n0x11,0x22,0x64,0x32,0x2F,0xB4,0x22,0x34,0x2F,0x34,0x62,0x04,0x02,0x00,0x09,0x05,\n0x03,0x01,0x09,0x09,0x07,0x00,/*\"澇\",1555*/},{\n\n0x02,0xE2,0xAF,0xFA,0xAF,0xE2,0x02,0x08,0xFF,0x08,0xF8,0x02,0x02,0x02,0x0F,0x02,\n0x02,0x0A,0x06,0x09,0x08,0x07,/*\"勒\",1556*/},{\n\n0xB6,0xAD,0xB6,0x80,0xBE,0xEB,0xBE,0x80,0xB6,0xAD,0xB6,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"樂\",1557*/},{\n\n0x0C,0xA5,0xAD,0xAD,0x85,0xBF,0x85,0xAD,0xAD,0xA5,0x0C,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"雷\",1558*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x0C,0xD5,0x45,0xDF,0x45,0xD5,0x0C,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x05,0x07,0x05,0x0F,0x00,/*\"鐳\",1559*/},{\n\n0x62,0xAA,0xEF,0xAA,0xAA,0xFA,0xAA,0xAA,0xEF,0xAA,0x62,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"蕾\",1560*/},{\n\n0x40,0x51,0xC9,0x5D,0x57,0x15,0x55,0xD5,0x5D,0x41,0x40,0x02,0x0F,0x05,0x05,0x0F,\n0x02,0x01,0x0F,0x05,0x05,0x0F,/*\"磊\",1561*/},{\n\n0x00,0x1F,0x55,0x75,0xD5,0x5F,0x55,0x35,0x95,0x1F,0x00,0x00,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x00,/*\"累\",1562*/},{\n\n0x20,0x10,0xFC,0x03,0xC0,0x5F,0xD5,0x5F,0xD5,0x5F,0xC0,0x00,0x00,0x0F,0x00,0x0F,\n0x05,0x07,0x05,0x07,0x05,0x0F,/*\"儡\",1563*/},{\n\n0xF0,0x50,0xFF,0x55,0xF5,0x1F,0xF5,0x55,0xFF,0x50,0xF0,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"壘\",1564*/},{\n\n0x88,0x88,0xFF,0x48,0xCD,0x55,0x45,0xDF,0x45,0x55,0xCD,0x00,0x08,0x0F,0x00,0x0F,\n0x05,0x05,0x07,0x05,0x05,0x0F,/*\"擂\",1565*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x08,0x08,0xFF,0x08,0x08,0xF8,0x08,0x07,0x00,0x08,0x0F,\n0x04,0x03,0x00,0x08,0x08,0x07,/*\"肋\",1566*/},{\n\n0x25,0x14,0xBF,0x14,0xA5,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x09,0x05,0x03,0x05,0x09,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"類\",1567*/},{\n\n0x11,0x22,0x00,0xFC,0x94,0x94,0x95,0xF6,0x94,0xB4,0xDC,0x02,0x09,0x04,0x03,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"淚\",1568*/},{\n\n0x84,0x64,0xFF,0x24,0x28,0x9A,0x6A,0x4F,0x4A,0xDA,0x28,0x00,0x00,0x0F,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"棱\",1569*/},{\n\n0x88,0x68,0xFF,0x48,0xAF,0x29,0xEF,0xB9,0xAF,0xA9,0xAF,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"楞\",1570*/},{\n\n0x04,0x08,0x00,0x10,0x48,0x44,0x53,0x64,0x48,0xD0,0x10,0x04,0x02,0x01,0x00,0x00,\n0x02,0x04,0x0A,0x01,0x00,0x00,/*\"冷\",1571*/},{\n\n0x28,0xFA,0x2A,0xFF,0xAA,0xBA,0xE4,0xB7,0xAA,0xF6,0x22,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0B,0x08,/*\"釐\",1572*/},{\n\n0x48,0x2A,0x1A,0x7E,0x19,0xA9,0x00,0x1E,0x00,0x40,0x7F,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"梨\",1573*/},{\n\n0x48,0x2A,0x9A,0x7E,0x19,0xA9,0x00,0x1E,0x00,0x40,0x7F,0x04,0x06,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x05,0x04,/*\"犁\",1574*/},{\n\n0xA4,0x95,0x4D,0x7F,0x2D,0x94,0x23,0x52,0x4E,0xA2,0xBE,0x00,0x08,0x05,0x02,0x08,\n0x0F,0x00,0x02,0x05,0x08,0x00,/*\"黎\",1575*/},{\n\n0xD4,0xB3,0xDA,0xB6,0xD2,0x24,0xF3,0xAA,0xF6,0xA2,0x22,0x0E,0x02,0x07,0x0A,0x0E,\n0x00,0x0F,0x0A,0x0F,0x0A,0x08,/*\"籬\",1576*/},{\n\n0x8A,0x44,0xFB,0x00,0x7F,0x49,0x49,0xFF,0x49,0x49,0x7F,0x08,0x08,0x07,0x08,0x09,\n0x09,0x09,0x0F,0x09,0x09,0x09,/*\"狸\",1577*/},{\n\n0xBA,0xB6,0xEB,0xB6,0xBA,0x10,0xFC,0x27,0xFC,0x25,0x24,0x0F,0x00,0x03,0x0A,0x0F,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"離\",1578*/},{\n\n0x22,0x44,0x82,0xBA,0xA2,0xB6,0xEB,0xB6,0xA2,0xBA,0x82,0x04,0x02,0x0F,0x00,0x06,\n0x05,0x04,0x06,0x04,0x08,0x0F,/*\"漓\",1579*/},{\n\n0x22,0xFE,0x22,0x00,0x7F,0x49,0x49,0xFF,0x49,0x49,0x7F,0x04,0x07,0x02,0x08,0x09,\n0x09,0x09,0x0F,0x09,0x09,0x09,/*\"理\",1580*/},{\n\n0x12,0x12,0x2A,0x26,0x22,0xBF,0x62,0x26,0x0A,0x12,0x12,0x01,0x01,0x01,0x09,0x09,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"李\",1581*/},{\n\n0x02,0x82,0xFA,0xAA,0xAA,0xFB,0xAA,0xAA,0xFA,0x82,0x02,0x0A,0x0A,0x06,0x0E,0x0A,\n0x03,0x06,0x0A,0x0E,0x0A,0x0A,/*\"裏\",1582*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0x7F,0x49,0xFF,0x49,0x7F,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x09,0x09,0x0F,0x09,0x09,/*\"鯉\",1583*/},{\n\n0x45,0xF6,0x2C,0x40,0xBE,0xAA,0xBF,0xAA,0xBF,0xAA,0xBE,0x00,0x0F,0x00,0x00,0x08,\n0x0B,0x0E,0x0A,0x0E,0x0B,0x08,/*\"禮\",1584*/},{\n\n0x42,0x52,0x52,0xF7,0x4A,0x4A,0x02,0xF7,0x02,0xFA,0x02,0x04,0x02,0x01,0x0F,0x01,\n0x02,0x00,0x03,0x08,0x0F,0x00,/*\"莉\",1585*/},{\n\n0x02,0x52,0xD2,0x37,0x1A,0x12,0x12,0xD7,0x52,0x32,0x02,0x09,0x05,0x03,0x09,0x0F,\n0x00,0x09,0x07,0x01,0x09,0x0F,/*\"荔\",1586*/},{\n\n0x04,0xF4,0x94,0x94,0x94,0xFF,0x94,0x94,0x94,0xF4,0x04,0x08,0x08,0x05,0x02,0x03,\n0x04,0x04,0x08,0x08,0x08,0x08,/*\"吏\",1587*/},{\n\n0x78,0x00,0xFF,0x08,0xBD,0xA5,0xBF,0xE5,0xBF,0xA5,0xBD,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"慄\",1588*/},{\n\n0x00,0xED,0xA5,0xA5,0xED,0xB0,0xAD,0xE5,0xA5,0xAD,0x20,0x08,0x07,0x02,0x0E,0x0B,\n0x0A,0x02,0x0F,0x0A,0x0B,0x0C,/*\"麗\",1589*/},{\n\n0x00,0xFF,0x05,0xF5,0x5F,0x55,0xF5,0x55,0x5F,0xF5,0x05,0x08,0x07,0x0F,0x01,0x05,\n0x05,0x07,0x05,0x07,0x09,0x0F,/*\"厲\",1590*/},{\n\n0xFF,0x01,0xF5,0x5F,0xF5,0x5F,0xF5,0x08,0xFF,0x08,0xF8,0x03,0x0F,0x01,0x05,0x07,\n0x09,0x0F,0x08,0x07,0x08,0x0F,/*\"勵\",1591*/},{\n\n0xF2,0x2E,0xE2,0x00,0xB6,0xAD,0xBE,0xEB,0xBE,0x94,0xAB,0x07,0x02,0x07,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"礫\",1592*/},{\n\n0x00,0xFF,0x91,0x55,0xFD,0x53,0x81,0x55,0xFD,0x53,0x91,0x08,0x07,0x08,0x08,0x0E,\n0x08,0x0F,0x0A,0x0A,0x0A,0x08,/*\"歷\",1593*/},{\n\n0x10,0x92,0x52,0xFE,0x51,0x91,0x10,0xFC,0x00,0x00,0xFF,0x01,0x00,0x00,0x0F,0x00,\n0x00,0x00,0x01,0x08,0x08,0x0F,/*\"利\",1594*/},{\n\n0x10,0xFC,0x83,0xBD,0xA5,0xBF,0xE5,0xBF,0xA5,0xBD,0x81,0x00,0x0F,0x04,0x04,0x02,\n0x01,0x0F,0x01,0x02,0x04,0x04,/*\"傈\",1595*/},{\n\n0x10,0xFC,0x83,0x62,0x9E,0x12,0xF2,0x00,0xFC,0x00,0xFF,0x00,0x0F,0x00,0x08,0x04,\n0x03,0x00,0x00,0x09,0x08,0x0F,/*\"例\",1596*/},{\n\n0x10,0xFC,0x03,0x10,0x92,0xFE,0x91,0x10,0xFC,0x00,0xFF,0x00,0x0F,0x00,0x01,0x00,\n0x0F,0x00,0x01,0x01,0x08,0x0F,/*\"俐\",1597*/},{\n\n0x08,0x90,0xFE,0x42,0x52,0xF2,0x4B,0x42,0xE2,0x02,0xFA,0x09,0x04,0x03,0x02,0x01,\n0x0F,0x01,0x02,0x03,0x08,0x0F,/*\"痢\",1598*/},{\n\n0x00,0x08,0x48,0x88,0x09,0x0A,0x08,0x08,0xE8,0x08,0x00,0x08,0x08,0x08,0x0B,0x08,\n0x08,0x0C,0x0B,0x08,0x08,0x08,/*\"立\",1599*/},{\n\n0x24,0xA8,0xFF,0xA8,0x04,0x28,0xC8,0x09,0x0A,0xE8,0x08,0x01,0x00,0x0F,0x00,0x09,\n0x08,0x09,0x0C,0x0B,0x08,0x08,/*\"粒\",1600*/},{\n\n0x11,0x22,0x00,0xFF,0x51,0x35,0xFD,0x53,0x35,0xFD,0x53,0x04,0x02,0x08,0x07,0x08,\n0x0E,0x08,0x0F,0x0A,0x0A,0x08,/*\"瀝\",1601*/},{\n\n0x92,0xAA,0xBF,0xAA,0x12,0xA8,0x2A,0xFF,0xAA,0x3E,0x88,0x04,0x0A,0x0F,0x02,0x04,\n0x02,0x09,0x0F,0x00,0x03,0x04,/*\"隸\",1602*/},{\n\n0x08,0x08,0x08,0x88,0x7F,0x08,0x08,0x08,0x08,0xF8,0x00,0x08,0x04,0x02,0x01,0x00,\n0x00,0x08,0x08,0x08,0x07,0x00,/*\"力\",1603*/},{\n\n0x22,0xFE,0x22,0x00,0xBA,0xA2,0xB6,0xEB,0xB6,0xA2,0xBA,0x04,0x07,0x02,0x00,0x0F,\n0x00,0x06,0x05,0x06,0x08,0x0F,/*\"璃\",1604*/},{\n\n0xFE,0x02,0xFE,0x00,0x7F,0x49,0x49,0xFF,0x49,0x49,0x7F,0x03,0x01,0x03,0x08,0x09,\n0x09,0x09,0x0F,0x09,0x09,0x09,/*\"哩\",1605*/},{\n\n0x20,0x10,0xFC,0x03,0xF2,0x52,0x92,0xFE,0x52,0x92,0xF2,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x00,0x0F,0x01,0x08,0x0F,/*\"倆\",1606*/},{\n\n0xFE,0x52,0xFE,0x02,0xB4,0x2A,0xB5,0x00,0xB6,0x29,0xB4,0x03,0x02,0x0F,0x01,0x03,\n0x0A,0x07,0x00,0x0F,0x02,0x03,/*\"聯\",1607*/},{\n\n0x4A,0xD2,0x07,0x0A,0xEA,0xAA,0xFE,0xAA,0xEF,0x0A,0x02,0x08,0x07,0x08,0x0A,0x0B,\n0x0A,0x0F,0x0A,0x0B,0x0A,0x08,/*\"蓮\",1608*/},{\n\n0x11,0xF2,0x00,0xFA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x00,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x0A,/*\"連\",1609*/},{\n\n0x2A,0xF9,0xAA,0x00,0xFE,0xAA,0xFE,0xAB,0xFA,0xAE,0xEA,0x05,0x07,0x0A,0x04,0x0B,\n0x06,0x0F,0x02,0x0F,0x06,0x0B,/*\"鐮\",1610*/},{\n\n0x00,0xFE,0x8A,0xAA,0xAE,0xFA,0xAB,0xFA,0xAE,0xEA,0x8A,0x08,0x07,0x08,0x0A,0x06,\n0x0F,0x02,0x0F,0x06,0x0B,0x08,/*\"廉\",1611*/},{\n\n0x78,0x00,0xFF,0x08,0x95,0x6E,0xC4,0x1F,0x44,0xEE,0x55,0x00,0x00,0x0F,0x02,0x09,\n0x06,0x01,0x03,0x02,0x0F,0x02,/*\"憐\",1612*/},{\n\n0x22,0x44,0x00,0x22,0xE4,0x00,0xFA,0xAA,0xFF,0xAA,0xFA,0x04,0x02,0x01,0x08,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"漣\",1613*/},{\n\n0x04,0xFB,0x8A,0xAE,0xFA,0xA8,0xAC,0xFB,0xAA,0xEE,0x8A,0x08,0x07,0x08,0x06,0x0F,\n0x02,0x02,0x0F,0x06,0x0B,0x00,/*\"簾\",1614*/},{\n\n0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x10,0xEF,0x08,0xF8,0x09,0x07,0x09,0x00,0x09,\n0x07,0x09,0x08,0x04,0x03,0x0C,/*\"斂\",1615*/},{\n\n0xFE,0x92,0xFE,0x00,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x07,0x08,0x0F,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"臉\",1616*/},{\n\n0x4A,0xF9,0x4A,0x11,0xF2,0x00,0xFA,0xAA,0xFF,0xAA,0xFA,0x0A,0x0F,0x05,0x08,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"鏈\",1617*/},{\n\n0xB6,0x2D,0xB4,0x00,0xAA,0xAB,0xAA,0x00,0xB6,0x2D,0xB4,0x09,0x04,0x01,0x04,0x0B,\n0x0E,0x0B,0x0C,0x01,0x04,0x09,/*\"戀\",1618*/},{\n\n0x78,0x00,0xFF,0x10,0xFA,0xAA,0x8A,0xFF,0x8A,0xAA,0xFA,0x08,0x06,0x01,0x02,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"煉\",1619*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFA,0xAA,0x8A,0xFF,0x8A,0xAA,0xFA,0x0E,0x00,0x06,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"練\",1620*/},{\n\n0x24,0xA8,0xFF,0x24,0x08,0xFF,0xAB,0xFD,0xA9,0xFF,0x08,0x01,0x00,0x0F,0x01,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"糧\",1621*/},{\n\n0x11,0x22,0x04,0xF4,0x94,0x95,0x96,0x94,0x94,0xF4,0x04,0x04,0x02,0x04,0x02,0x00,\n0x08,0x0F,0x00,0x00,0x02,0x04,/*\"涼\",1622*/},{\n\n0xC4,0xA9,0x82,0x88,0xA5,0xD1,0x8F,0xA1,0xBF,0x84,0x88,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"梁\",1623*/},{\n\n0x44,0x29,0x42,0x88,0x25,0xD1,0x0F,0xA1,0x7F,0x04,0x08,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"粱\",1624*/},{\n\n0x00,0xFC,0x54,0x54,0x55,0xD6,0x54,0x54,0x54,0x7C,0x80,0x00,0x0F,0x08,0x08,0x04,\n0x00,0x01,0x02,0x06,0x09,0x08,/*\"良\",1625*/},{\n\n0xF2,0x12,0x52,0x92,0x12,0xFE,0x12,0x52,0x92,0x12,0xF2,0x0F,0x02,0x01,0x00,0x01,\n0x0F,0x02,0x01,0x00,0x09,0x0F,/*\"兩\",1626*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xF0,0x52,0x92,0xFE,0x52,0x92,0xF2,0x02,0x02,0x0F,0x02,0x0F,\n0x01,0x00,0x07,0x01,0x08,0x0F,/*\"輛\",1627*/},{\n\n0x08,0xFF,0xA9,0xA9,0xA9,0xFB,0xAD,0xA9,0xA9,0xFF,0x08,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"量\",1628*/},{\n\n0xFE,0x22,0xFE,0x00,0x04,0xF4,0x95,0x96,0x94,0xF4,0x04,0x07,0x02,0x07,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"晾\",1629*/},{\n\n0x82,0x82,0xBA,0xAA,0xAA,0xAB,0xAA,0xAA,0xBA,0x82,0x82,0x09,0x08,0x06,0x02,0x02,\n0x02,0x02,0x06,0x08,0x08,0x0D,/*\"亮\",1630*/},{\n\n0x54,0x55,0x56,0x54,0x00,0xF4,0x95,0x96,0x94,0xF4,0x04,0x0F,0x05,0x05,0x0F,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"諒\",1631*/},{\n\n0x88,0x88,0xFF,0x48,0x2A,0xF2,0xAA,0xA7,0xAA,0xF2,0x2A,0x00,0x08,0x0F,0x00,0x08,\n0x07,0x0A,0x0E,0x02,0x07,0x08,/*\"撩\",1632*/},{\n\n0x01,0xFF,0x49,0xFF,0x01,0xFC,0xE2,0x01,0xFE,0x02,0xFE,0x02,0x03,0x02,0x0F,0x01,\n0x08,0x07,0x00,0x0F,0x02,0x03,/*\"聊\",1633*/},{\n\n0x10,0xFC,0x2B,0x12,0xFA,0x56,0x53,0x56,0xFA,0x12,0x2A,0x00,0x0F,0x00,0x08,0x05,\n0x09,0x0F,0x01,0x05,0x08,0x00,/*\"僚\",1634*/},{\n\n0x10,0xFE,0xA2,0x4A,0xEA,0xBA,0xAF,0xBA,0xEA,0x4A,0xA2,0x09,0x07,0x00,0x08,0x07,\n0x0A,0x0E,0x02,0x07,0x08,0x00,/*\"療\",1635*/},{\n\n0x78,0x00,0xFF,0x10,0x2A,0xF2,0xAA,0xA7,0xAA,0xF2,0x2A,0x08,0x06,0x01,0x02,0x08,\n0x07,0x0A,0x0E,0x02,0x07,0x08,/*\"燎\",1636*/},{\n\n0x06,0x5A,0x2A,0x8A,0xBA,0x43,0xDA,0xAA,0x0A,0x7A,0x06,0x01,0x09,0x09,0x0A,0x0A,\n0x0A,0x05,0x04,0x05,0x01,0x01,/*\"寥\",1637*/},{\n\n0x11,0xF2,0x28,0x12,0xFA,0xAE,0xAB,0xAE,0xFA,0x12,0x28,0x08,0x07,0x08,0x0A,0x09,\n0x0A,0x0B,0x08,0x09,0x0A,0x08,/*\"遼\",1638*/},{\n\n0x11,0x22,0x28,0x12,0xFA,0x56,0x53,0x56,0xFA,0x12,0x2A,0x04,0x02,0x09,0x04,0x01,\n0x09,0x0F,0x01,0x01,0x04,0x08,/*\"潦\",1639*/},{\n\n0x00,0x02,0x02,0x02,0x02,0x02,0xE2,0x12,0x0A,0x06,0x00,0x00,0x00,0x00,0x00,0x08,\n0x08,0x0F,0x00,0x00,0x00,0x00,/*\"了\",1640*/},{\n\n0x08,0x08,0xFF,0x88,0x5F,0xF5,0x55,0x5F,0x55,0xD5,0x5F,0x01,0x09,0x0F,0x00,0x02,\n0x0E,0x0B,0x0A,0x0B,0x0E,0x02,/*\"撂\",1641*/},{\n\n0x4A,0xF9,0x4A,0x00,0x2A,0xF2,0xAA,0xA7,0xAA,0xF2,0x2A,0x0A,0x0F,0x05,0x00,0x08,\n0x07,0x0A,0x0E,0x02,0x07,0x08,/*\"鐐\",1642*/},{\n\n0x00,0xFE,0x82,0x96,0x4A,0x5E,0xA3,0x56,0x4A,0x9E,0x82,0x08,0x07,0x00,0x08,0x09,\n0x09,0x0A,0x05,0x04,0x02,0x00,/*\"廖\",1643*/},{\n\n0x24,0xA8,0xFF,0xA8,0x24,0x80,0x92,0xA4,0x80,0xFF,0x40,0x01,0x00,0x0F,0x00,0x01,\n0x00,0x00,0x00,0x00,0x0F,0x00,/*\"料\",1644*/},{\n\n0x42,0x22,0x5E,0x92,0x12,0xF2,0x00,0xFC,0x00,0x00,0xFF,0x00,0x08,0x04,0x02,0x01,\n0x00,0x00,0x01,0x08,0x08,0x0F,/*\"列\",1645*/},{\n\n0xA8,0xA5,0xAF,0x95,0x95,0xCD,0x80,0x8E,0x80,0xA0,0xBF,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"裂\",1646*/},{\n\n0x22,0x12,0xAE,0x4A,0x2A,0x1A,0x00,0x7C,0x00,0xFF,0x00,0x09,0x05,0x00,0x04,0x08,\n0x00,0x04,0x08,0x01,0x05,0x08,/*\"烈\",1647*/},{\n\n0x28,0xA4,0xA2,0x90,0xD0,0x9F,0x88,0x88,0x82,0x84,0x08,0x08,0x08,0x04,0x02,0x01,\n0x00,0x00,0x08,0x08,0x07,0x00,/*\"劣\",1648*/},{\n\n0x8A,0x44,0xFB,0x00,0xFA,0x8D,0xDA,0xAD,0xDA,0x8D,0xF8,0x08,0x08,0x07,0x00,0x0F,\n0x0A,0x00,0x0F,0x0A,0x07,0x0C,/*\"獵\",1649*/},{\n\n0x22,0xFE,0x22,0x88,0x48,0xFF,0xA8,0x48,0xFF,0x48,0x88,0x04,0x07,0x02,0x00,0x00,\n0x0F,0x00,0x00,0x0F,0x00,0x00,/*\"琳\",1650*/},{\n\n0x08,0x88,0x68,0xFF,0x48,0x80,0x68,0xFF,0x68,0x88,0x08,0x02,0x01,0x00,0x0F,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"林\",1651*/},{\n\n0x42,0xF2,0x2E,0xE2,0x95,0x6E,0xC4,0x1F,0x44,0xEE,0x55,0x00,0x07,0x02,0x07,0x09,\n0x06,0x01,0x03,0x02,0x0F,0x02,/*\"磷\",1652*/},{\n\n0x8C,0xA5,0xED,0xAD,0x85,0x3F,0x85,0xAD,0xED,0xA5,0x8C,0x04,0x02,0x0F,0x02,0x04,\n0x00,0x04,0x02,0x0F,0x02,0x04,/*\"霖\",1653*/},{\n\n0xFE,0x92,0x9E,0xF2,0x84,0xBB,0xAA,0x2A,0xAA,0xBA,0x82,0x07,0x04,0x07,0x04,0x0F,\n0x04,0x0F,0x00,0x0F,0x04,0x0F,/*\"臨\",1654*/},{\n\n0x95,0x6E,0xC4,0x1F,0x44,0xEE,0x55,0x00,0xFE,0x32,0xCE,0x09,0x06,0x01,0x03,0x02,\n0x0F,0x02,0x00,0x0F,0x02,0x01,/*\"鄰\",1655*/},{\n\n0xF4,0x5B,0xF6,0x50,0x95,0x6E,0xC4,0x1F,0x44,0xEE,0x55,0x0D,0x01,0x0D,0x01,0x09,\n0x06,0x01,0x03,0x02,0x0F,0x02,/*\"鱗\",1656*/},{\n\n0x11,0x22,0x88,0x68,0xFF,0x48,0x00,0xC8,0xFF,0x48,0x88,0x04,0x02,0x00,0x00,0x0F,\n0x00,0x01,0x00,0x0F,0x00,0x00,/*\"淋\",1657*/},{\n\n0x02,0x04,0x82,0x3E,0xA2,0xBA,0xAB,0xBA,0x62,0x3E,0x02,0x02,0x01,0x02,0x0A,0x06,\n0x02,0x0F,0x02,0x06,0x0A,0x02,/*\"凜\",1658*/},{\n\n0x08,0xC4,0x5E,0xC1,0x44,0x55,0xD5,0x5F,0x55,0xD5,0x04,0x00,0x0B,0x06,0x02,0x03,\n0x02,0x02,0x03,0x06,0x0B,0x00,/*\"賃\",1659*/},{\n\n0x84,0x84,0x4C,0x54,0x25,0x26,0x24,0x54,0x4C,0x84,0x84,0x00,0x00,0x0F,0x09,0x09,\n0x09,0x09,0x09,0x0F,0x00,0x00,/*\"吝\",1660*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0x48,0x44,0x53,0x64,0xC8,0x10,0x00,0x08,0x0F,0x00,0x00,\n0x00,0x02,0x04,0x0B,0x00,0x00,/*\"拎\",1661*/},{\n\n0x22,0x22,0xFE,0x22,0x10,0x48,0x44,0x53,0x64,0xC8,0x10,0x04,0x04,0x03,0x02,0x00,\n0x00,0x02,0x04,0x0B,0x00,0x00,/*\"玲\",1662*/},{\n\n0x22,0xAA,0x6A,0x2F,0xAA,0x3E,0x2A,0x2F,0x6A,0xAA,0x22,0x09,0x08,0x0A,0x0B,0x05,\n0x05,0x05,0x0B,0x08,0x08,0x09,/*\"菱\",1663*/},{\n\n0x0C,0x25,0xAD,0xAD,0x45,0xBF,0x45,0xAD,0xAD,0x25,0x0C,0x01,0x01,0x00,0x05,0x05,\n0x05,0x0B,0x09,0x00,0x01,0x01,/*\"零\",1664*/},{\n\n0xEE,0xA8,0x9F,0xAA,0xEA,0x10,0x4C,0x53,0x64,0xC8,0x10,0x0F,0x0A,0x09,0x0A,0x0F,\n0x00,0x02,0x04,0x0B,0x00,0x00,/*\"齡\",1665*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x10,0x4C,0x53,0x64,0xC8,0x10,0x08,0x09,0x07,0x05,0x04,\n0x00,0x02,0x04,0x0B,0x00,0x00,/*\"鈴\",1666*/},{\n\n0x20,0x10,0xFC,0x13,0x48,0x44,0x53,0x64,0x48,0xD0,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x02,0x04,0x0A,0x01,0x00,0x00,/*\"伶\",1667*/},{\n\n0x89,0xAA,0xF8,0xAA,0x11,0x48,0x44,0x53,0x64,0xC8,0x10,0x08,0x04,0x03,0x00,0x00,\n0x00,0x02,0x04,0x0B,0x00,0x00,/*\"羚\",1668*/},{\n\n0x02,0x04,0x88,0x2A,0x9A,0x6A,0x4F,0x4A,0xDA,0x2A,0x08,0x02,0x01,0x08,0x09,0x04,\n0x05,0x02,0x05,0x04,0x08,0x08,/*\"凌\",1669*/},{\n\n0xCC,0x55,0xD5,0x15,0xC5,0x5F,0xC5,0x15,0xD5,0x55,0xCC,0x09,0x0D,0x0B,0x0D,0x09,\n0x0F,0x09,0x0D,0x0B,0x0D,0x09,/*\"靈\",1670*/},{\n\n0xFE,0x32,0xCE,0x00,0x28,0x9A,0x6A,0x4F,0x4A,0xDA,0x28,0x0F,0x02,0x01,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"陵\",1671*/},{\n\n0xA0,0x93,0xAA,0xD2,0xA2,0x03,0xEA,0xAA,0xBA,0xAB,0xE8,0x00,0x02,0x04,0x0A,0x01,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"嶺\",1672*/},{\n\n0x48,0x44,0x53,0x64,0xC8,0x10,0xFA,0xAA,0xAE,0xAA,0xFA,0x00,0x02,0x04,0x0B,0x00,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"領\",1673*/},{\n\n0x00,0x80,0x9F,0x91,0xF1,0x91,0x91,0x91,0x91,0x9F,0x80,0x00,0x08,0x04,0x02,0x01,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"另\",1674*/},{\n\n0x10,0x50,0x48,0x44,0x52,0x61,0x42,0x44,0xC8,0x10,0x10,0x00,0x00,0x02,0x02,0x04,\n0x04,0x0A,0x09,0x00,0x00,0x00,/*\"令\",1675*/},{\n\n0x22,0x44,0x3E,0xD2,0x49,0x50,0xE2,0x5E,0x42,0xD2,0x1E,0x04,0x02,0x00,0x0F,0x05,\n0x05,0x07,0x05,0x05,0x0F,0x00,/*\"溜\",1676*/},{\n\n0x22,0xFE,0x22,0x00,0xA4,0x34,0xAD,0x26,0xA4,0x34,0x64,0x04,0x07,0x02,0x08,0x07,\n0x00,0x07,0x00,0x07,0x08,0x0C,/*\"琉\",1677*/},{\n\n0x88,0x68,0xFF,0x28,0xDE,0x52,0x69,0xD2,0x4E,0x52,0xDE,0x00,0x00,0x0F,0x00,0x0F,\n0x05,0x05,0x07,0x05,0x05,0x0F,/*\"榴\",1678*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xA4,0x34,0xAD,0x26,0xB4,0x64,0x00,0x07,0x02,0x07,0x08,\n0x07,0x00,0x07,0x00,0x0F,0x08,/*\"硫\",1679*/},{\n\n0xFA,0xAD,0xFA,0x00,0xDE,0x52,0x69,0xD2,0x4E,0x52,0xDE,0x0F,0x04,0x02,0x04,0x0F,\n0x05,0x05,0x07,0x05,0x05,0x0F,/*\"餾\",1680*/},{\n\n0x1E,0xD2,0x56,0x49,0x51,0xC0,0x52,0x4E,0x42,0xD2,0x1E,0x00,0x0F,0x05,0x05,0x05,\n0x07,0x05,0x05,0x05,0x0F,0x00,/*\"留\",1681*/},{\n\n0x4E,0x29,0x54,0xC9,0x57,0x29,0x4F,0x00,0xFC,0x00,0xFF,0x09,0x0D,0x09,0x0F,0x09,\n0x0D,0x09,0x00,0x01,0x08,0x0F,/*\"劉\",1682*/},{\n\n0x08,0x90,0xFE,0x02,0xBA,0xAA,0x97,0xAA,0x9A,0xAA,0xBA,0x09,0x04,0x03,0x00,0x0F,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0F,/*\"瘤\",1683*/},{\n\n0x22,0x44,0x00,0x24,0xB4,0x2C,0xA5,0x26,0xA4,0x34,0x64,0x04,0x02,0x08,0x04,0x03,\n0x00,0x0F,0x00,0x07,0x08,0x0E,/*\"流\",1684*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x82,0xFD,0x00,0xFE,0x02,0xFE,0x00,0x00,0x0F,0x00,0x09,\n0x04,0x03,0x00,0x0F,0x01,0x01,/*\"柳\",1685*/},{\n\n0x10,0x10,0x10,0xD0,0x11,0x16,0x10,0x50,0x90,0x10,0x10,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x00,0x00,0x03,0x0C,/*\"六\",1686*/},{\n\n0x08,0xEA,0xAE,0xAB,0xAE,0xEA,0x08,0xF7,0x55,0x55,0x5D,0x00,0x0F,0x02,0x02,0x0A,\n0x0F,0x00,0x07,0x09,0x09,0x0D,/*\"龍\",1687*/},{\n\n0x88,0xFA,0xAE,0xAB,0xAE,0xFA,0x88,0xEF,0xAA,0xBA,0xC0,0x04,0x04,0x07,0x05,0x06,\n0x04,0x05,0x06,0x0F,0x02,0x02,/*\"聾\",1688*/},{\n\n0xFC,0x04,0xFC,0x0A,0xEE,0xAB,0xEE,0x0A,0xF7,0x55,0x5D,0x03,0x01,0x03,0x00,0x0F,\n0x02,0x0F,0x00,0x07,0x09,0x0D,/*\"嚨\",1689*/},{\n\n0x22,0xE9,0xBB,0xAD,0xB9,0xEA,0x21,0xBD,0xAB,0xE9,0x01,0x00,0x0F,0x02,0x02,0x0A,\n0x0F,0x00,0x07,0x0A,0x0A,0x0C,/*\"籠\",1690*/},{\n\n0x06,0xF2,0x9A,0x76,0x82,0xA3,0x5A,0x56,0x5A,0xB2,0x86,0x00,0x0F,0x04,0x03,0x0C,\n0x0B,0x0A,0x0F,0x0A,0x0A,0x08,/*\"窿\",1691*/},{\n\n0xFE,0x12,0xEE,0x00,0xD4,0x96,0xAB,0xEA,0xAA,0x96,0x90,0x0F,0x01,0x00,0x09,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"隆\",1692*/},{\n\n0x08,0xFA,0x2E,0x2B,0xAE,0xFA,0x08,0x6F,0xAA,0xBA,0xC0,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"壟\",1693*/},{\n\n0x84,0xFF,0x44,0xEA,0xAE,0xAB,0xEE,0x0A,0xF7,0x55,0x5D,0x08,0x0F,0x00,0x0F,0x02,\n0x0A,0x0F,0x00,0x07,0x09,0x0D,/*\"攏\",1694*/},{\n\n0xFF,0x31,0xCF,0x0A,0xEE,0xAB,0xEE,0x0A,0xF7,0x55,0x5D,0x0F,0x02,0x01,0x00,0x0F,\n0x02,0x0F,0x00,0x07,0x09,0x0D,/*\"隴\",1695*/},{\n\n0x84,0x64,0xFF,0x24,0x88,0xBE,0xAA,0xFF,0xAA,0xBE,0x88,0x00,0x00,0x0F,0x00,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"樓\",1696*/},{\n\n0x08,0x3E,0x2A,0x2A,0xAA,0x7F,0x2A,0x2A,0x2A,0x3E,0x08,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"婁\",1697*/},{\n\n0x84,0x84,0xFF,0x44,0x88,0xBE,0xAA,0xFF,0xAA,0xBE,0x88,0x00,0x08,0x0F,0x00,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"摟\",1698*/},{\n\n0x44,0x43,0xF2,0x56,0x52,0xFC,0x53,0x52,0xF6,0x42,0x42,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"簍\",1699*/},{\n\n0x22,0x44,0xFF,0x15,0xD5,0x55,0x55,0xF5,0x55,0x55,0xD7,0x04,0x0A,0x07,0x00,0x0F,\n0x05,0x00,0x0F,0x05,0x08,0x0F,/*\"漏\",1700*/},{\n\n0xFF,0x31,0xCF,0x00,0xF8,0x01,0xF9,0x49,0x3F,0x49,0xF9,0x0F,0x02,0x01,0x00,0x0F,\n0x08,0x0B,0x08,0x08,0x0A,0x0B,/*\"陋\",1701*/},{\n\n0x02,0xFA,0x0A,0x2F,0xAA,0xFE,0xAA,0xAF,0xAA,0x8A,0xDA,0x08,0x07,0x08,0x0E,0x0B,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"蘆\",1702*/},{\n\n0x00,0xFC,0x24,0x24,0xA4,0xBF,0xD5,0xD5,0xD5,0x45,0x6C,0x08,0x07,0x08,0x0E,0x0B,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"盧\",1703*/},{\n\n0x00,0xF8,0x28,0xFF,0xAA,0xAA,0xDA,0x00,0xFA,0xAE,0xFA,0x06,0x09,0x0E,0x0B,0x0E,\n0x0B,0x0E,0x08,0x0B,0x06,0x0B,/*\"顱\",1704*/},{\n\n0x00,0xFE,0x02,0xFA,0x0A,0x2A,0xFF,0xAA,0xAA,0xAA,0xDA,0x08,0x07,0x08,0x07,0x08,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"廬\",1705*/},{\n\n0x78,0x00,0xFF,0x04,0xF8,0x28,0xA8,0xFF,0xAA,0xAA,0xDA,0x08,0x06,0x01,0x06,0x0B,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"爐\",1706*/},{\n\n0x88,0xFF,0x48,0x00,0xFC,0x04,0xE4,0xBF,0xE5,0xA5,0xED,0x08,0x0F,0x00,0x08,0x07,\n0x02,0x0A,0x07,0x02,0x0A,0x0E,/*\"擄\",1707*/},{\n\n0x11,0x22,0xF8,0x88,0x28,0x48,0x9F,0x4A,0x2A,0x8A,0xFA,0x04,0x02,0x0F,0x08,0x0A,\n0x09,0x0A,0x09,0x0A,0x08,0x0F,/*\"滷\",1708*/},{\n\n0x00,0xFC,0x04,0xD4,0x94,0x9F,0xF5,0xAD,0xA5,0xF5,0x0C,0x08,0x07,0x00,0x0A,0x0A,\n0x06,0x03,0x02,0x0A,0x0A,0x06,/*\"虜\",1709*/},{\n\n0x44,0xBE,0x95,0xD5,0x95,0xBD,0x95,0xD7,0x95,0xBC,0x40,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"魯\",1710*/},{\n\n0x0A,0xE6,0xBF,0xA6,0xEA,0xB0,0xAA,0xE6,0xBF,0xA6,0x2A,0x08,0x07,0x02,0x0E,0x0B,\n0x0A,0x02,0x0F,0x0A,0x0B,0x0C,/*\"麓\",1711*/},{\n\n0x42,0xF2,0x2E,0xE2,0x50,0x95,0x15,0xF5,0x15,0x9F,0x50,0x00,0x0F,0x04,0x0F,0x04,\n0x02,0x09,0x0F,0x01,0x02,0x04,/*\"碌\",1712*/},{\n\n0x0C,0xE5,0xAD,0xA5,0xE5,0x0F,0x45,0xB5,0xAD,0x65,0x0C,0x08,0x0E,0x08,0x0F,0x0A,\n0x01,0x0F,0x0A,0x0A,0x0F,0x01,/*\"露\",1713*/},{\n\n0x9E,0x12,0xF2,0x9E,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x0F,0x08,0x07,0x04,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"路\",1714*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x09,0x05,0x05,0x09,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"賂\",1715*/},{\n\n0x00,0xFE,0x2A,0xAA,0x3E,0x2A,0x2B,0xBE,0x2A,0x2A,0xBA,0x08,0x07,0x00,0x0F,0x09,\n0x05,0x00,0x07,0x0A,0x09,0x0C,/*\"鹿\",1716*/},{\n\n0x22,0x44,0x9E,0x12,0xF2,0x9E,0x44,0xAB,0x92,0xAE,0x40,0x04,0x0A,0x0F,0x08,0x07,\n0x04,0x00,0x0F,0x04,0x0F,0x00,/*\"潞\",1717*/},{\n\n0x08,0x89,0xEA,0x98,0x20,0xAC,0x2B,0xEA,0xBA,0x26,0xA0,0x01,0x00,0x0F,0x00,0x04,\n0x02,0x09,0x0F,0x00,0x03,0x04,/*\"祿\",1718*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xAC,0x2B,0xEA,0xBA,0x26,0xA0,0x08,0x09,0x07,0x04,0x04,\n0x02,0x09,0x0F,0x00,0x03,0x04,/*\"錄\",1719*/},{\n\n0xFE,0x02,0x32,0xCE,0x90,0x54,0x34,0x9F,0x34,0x54,0x90,0x0F,0x02,0x02,0x01,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"陸\",1720*/},{\n\n0x8B,0x45,0xAF,0x5A,0xA5,0x5F,0x10,0xFF,0x08,0xE9,0x0A,0x00,0x0A,0x0A,0x09,0x04,\n0x0A,0x04,0x02,0x03,0x04,0x0E,/*\"戮\",1721*/},{\n\n0xFE,0xAA,0xFE,0xAA,0xF8,0x28,0xFF,0xAA,0xAA,0xDA,0x00,0x04,0x0A,0x08,0x07,0x09,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"驢\",1722*/},{\n\n0x80,0x9E,0x92,0x92,0xD2,0xB2,0x92,0x92,0x92,0x9E,0x80,0x0F,0x04,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"呂\",1723*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0xC0,0x5F,0x51,0x51,0x5F,0xC0,0x08,0x09,0x07,0x05,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"鋁\",1724*/},{\n\n0x20,0x10,0xFC,0x03,0x80,0x9E,0xD2,0xB2,0x92,0x9E,0x80,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"侶\",1725*/},{\n\n0x04,0xFD,0x26,0xE4,0x10,0xEC,0x27,0xE4,0x24,0x94,0x54,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x04,0x00,0x03,0x04,0x08,/*\"旅\",1726*/},{\n\n0x00,0xFF,0x25,0x95,0x4D,0x15,0xFD,0x55,0x55,0xF5,0x17,0x08,0x07,0x01,0x0F,0x00,\n0x0A,0x0B,0x05,0x05,0x0B,0x08,/*\"履\",1727*/},{\n\n0x00,0xFF,0x45,0xF5,0x55,0x55,0xFD,0x55,0x55,0xF7,0x40,0x08,0x07,0x09,0x09,0x0B,\n0x05,0x05,0x05,0x0B,0x09,0x09,/*\"屢\",1728*/},{\n\n0xDC,0xB3,0xC8,0x00,0x88,0xBE,0xAA,0xFF,0xAA,0xBE,0x88,0x0E,0x00,0x06,0x00,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"縷\",1729*/},{\n\n0x00,0xFC,0x04,0xD4,0x54,0xDF,0x75,0x6D,0xE5,0x35,0x0C,0x08,0x07,0x08,0x05,0x09,\n0x0B,0x0D,0x09,0x0D,0x02,0x04,/*\"慮\",1730*/},{\n\n0x04,0x52,0x55,0x55,0x55,0x55,0xF5,0x15,0xF5,0x01,0x00,0x01,0x0B,0x05,0x09,0x0F,\n0x01,0x05,0x0B,0x03,0x04,0x0E,/*\"氯\",1731*/},{\n\n0x24,0xF2,0x09,0x08,0xAA,0xAA,0xFF,0xAA,0xAA,0xBE,0x08,0x00,0x0F,0x00,0x02,0x02,\n0x02,0x0F,0x02,0x02,0x02,0x02,/*\"律\",1732*/},{\n\n0x02,0x8A,0x52,0x9A,0xD6,0xB3,0xD2,0x8A,0x52,0x8A,0x02,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"率\",1733*/},{\n\n0x22,0x44,0x00,0xFC,0x04,0xD4,0x7F,0xD5,0x55,0xD5,0x6C,0x04,0x02,0x04,0x03,0x08,\n0x05,0x09,0x0B,0x0D,0x01,0x0C,/*\"濾\",1734*/},{\n\n0xD8,0xB4,0x93,0xC8,0x20,0xAC,0x2B,0xEA,0xBA,0x26,0xA0,0x0C,0x02,0x04,0x02,0x04,\n0x02,0x09,0x0F,0x00,0x03,0x04,/*\"綠\",1735*/},{\n\n0xB6,0x2D,0xB4,0x00,0xAA,0xAB,0xAA,0x00,0xB6,0x2D,0xB4,0x01,0x0C,0x09,0x08,0x0B,\n0x0E,0x0B,0x08,0x09,0x0C,0x01,/*\"巒\",1736*/},{\n\n0x56,0x1D,0xD4,0x80,0xBA,0xAB,0xBA,0x40,0x56,0x1D,0x54,0x02,0x02,0x02,0x0A,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"攣\",1737*/},{\n\n0x56,0x1D,0xD4,0x80,0xBA,0xAB,0xBA,0x80,0x56,0x1D,0x54,0x02,0x02,0x02,0x0A,0x0A,\n0x0E,0x03,0x02,0x02,0x02,0x02,/*\"孿\",1738*/},{\n\n0x22,0x44,0x5A,0x15,0x40,0x3A,0xAB,0x3A,0x40,0x1A,0x55,0x04,0x02,0x09,0x05,0x03,\n0x01,0x0F,0x01,0x03,0x05,0x09,/*\"灤\",1739*/},{\n\n0xFE,0x0A,0x92,0x81,0xF9,0x00,0xFE,0x12,0x22,0x02,0xFE,0x01,0x09,0x04,0x02,0x01,\n0x00,0x0F,0x00,0x00,0x01,0x01,/*\"卵\",1740*/},{\n\n0xCA,0x4E,0xDA,0x6E,0x59,0xCD,0x00,0xFF,0x00,0x00,0x00,0x0F,0x0B,0x05,0x0B,0x00,\n0x0F,0x00,0x07,0x08,0x08,0x0E,/*\"亂\",1741*/},{\n\n0x88,0x88,0xFF,0x48,0x04,0xF4,0x95,0x96,0x94,0xF4,0x04,0x00,0x08,0x0F,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"掠\",1742*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x44,0xAB,0x92,0x92,0xAE,0x40,0x07,0x02,0x03,0x02,0x07,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"略\",1743*/},{\n\n0x88,0xFF,0x48,0x00,0xE8,0x24,0xEA,0x29,0xEA,0x24,0xE8,0x08,0x0F,0x00,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"掄\",1744*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x24,0xEA,0x29,0xEA,0x24,0xE8,0x02,0x02,0x0F,0x02,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"輪\",1745*/},{\n\n0x20,0x10,0xFC,0x03,0xE8,0x24,0xEA,0x29,0xEA,0x24,0xE8,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"倫\",1746*/},{\n\n0x08,0xC8,0x54,0x54,0xD2,0x51,0xD2,0x54,0x54,0xC8,0x08,0x00,0x0F,0x01,0x01,0x07,\n0x01,0x07,0x01,0x09,0x0F,0x00,/*\"侖\",1747*/},{\n\n0x10,0x21,0x02,0xE8,0x24,0xEA,0x29,0xEA,0x24,0xE8,0x08,0x04,0x02,0x01,0x0F,0x01,\n0x07,0x01,0x07,0x09,0x0F,0x00,/*\"淪\",1748*/},{\n\n0xDC,0xB3,0xC8,0x00,0xE8,0x24,0xEA,0x29,0xEA,0x24,0xE8,0x0E,0x00,0x06,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"綸\",1749*/},{\n\n0x55,0x56,0x54,0x00,0xE8,0x24,0xEA,0x29,0xEA,0x24,0xE8,0x0F,0x05,0x0F,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"論\",1750*/},{\n\n0xC2,0xBA,0xAA,0x6F,0x3A,0xAA,0xFA,0xAF,0xEA,0xBA,0x82,0x0A,0x03,0x0A,0x02,0x05,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"蘿\",1751*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x5F,0xF5,0x5F,0x35,0x9F,0x04,0x04,0x03,0x02,0x07,\n0x08,0x05,0x09,0x0F,0x05,0x09,/*\"螺\",1752*/},{\n\n0xB0,0x6F,0x25,0x95,0x47,0xE5,0xBF,0xA5,0xED,0xB7,0xA0,0x09,0x05,0x09,0x05,0x08,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"羅\",1753*/},{\n\n0x11,0xF2,0x00,0xB7,0x4D,0xA7,0x45,0xF5,0xAF,0xF5,0xA7,0x08,0x07,0x08,0x0D,0x09,\n0x0D,0x08,0x0F,0x0A,0x0B,0x0A,/*\"邏\",1754*/},{\n\n0x4A,0xF9,0x4A,0x00,0xB7,0x4D,0xA7,0xFD,0x57,0xFD,0x57,0x0A,0x0F,0x05,0x00,0x0D,\n0x01,0x05,0x0F,0x05,0x07,0x05,/*\"鑼\",1755*/},{\n\n0xC4,0xBB,0xAA,0x6E,0x3A,0xAC,0xFB,0xAA,0xEE,0xBA,0x82,0x0A,0x03,0x0A,0x02,0x05,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"籮\",1756*/},{\n\n0x7F,0x55,0x7F,0xD5,0x00,0x5F,0x75,0xD5,0x5F,0x35,0x9F,0x04,0x0B,0x08,0x07,0x08,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"騾\",1757*/},{\n\n0x45,0xF6,0xAC,0x40,0x5F,0x55,0x55,0xFF,0x55,0x55,0x5F,0x00,0x0F,0x00,0x04,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"裸\",1758*/},{\n\n0x42,0x8A,0x12,0xA7,0x92,0xBA,0x52,0x57,0xB2,0x82,0x82,0x08,0x04,0x02,0x00,0x0E,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"落\",1759*/},{\n\n0x10,0x21,0x02,0x28,0xA4,0xAB,0x92,0x92,0xAA,0xA6,0x20,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"洛\",1760*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x44,0xAB,0x92,0x92,0xAE,0x40,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"駱\",1761*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x44,0xAB,0x92,0x92,0xAE,0x40,0x0C,0x02,0x04,0x02,0x04,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"絡\",1762*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x7F,0x55,0x55,0x7F,0x55,0xD5,0x08,0x05,0x02,0x0D,0x02,\n0x01,0x02,0x01,0x0A,0x09,0x07,/*\"媽\",1763*/},{\n\n0x00,0xFC,0x24,0xA4,0xFC,0xA5,0x26,0xA4,0xFC,0xA4,0x24,0x08,0x07,0x01,0x00,0x0F,\n0x00,0x01,0x00,0x0F,0x00,0x01,/*\"麻\",1764*/},{\n\n0x22,0xFE,0x22,0x00,0x7F,0x55,0x55,0x7F,0x55,0x55,0xC1,0x04,0x07,0x02,0x02,0x01,\n0x02,0x01,0x0A,0x09,0x0A,0x07,/*\"瑪\",1765*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x7F,0x55,0x55,0x7F,0x55,0xD5,0x00,0x07,0x02,0x07,0x02,\n0x01,0x02,0x01,0x0A,0x09,0x07,/*\"碼\",1766*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFE,0xAA,0xFE,0xAA,0x82,0x04,0x04,0x03,0x02,0x07,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"螞\",1767*/},{\n\n0x00,0x7F,0x55,0x55,0x55,0x7F,0x55,0x55,0x55,0x55,0xC1,0x04,0x03,0x00,0x03,0x00,\n0x03,0x00,0x0B,0x08,0x08,0x07,/*\"馬\",1768*/},{\n\n0x00,0xF7,0x55,0x55,0x57,0xF5,0x57,0x55,0x55,0x57,0x10,0x00,0x0D,0x01,0x0D,0x01,\n0x0D,0x01,0x0D,0x01,0x09,0x0F,/*\"罵\",1769*/},{\n\n0xFC,0x04,0xFC,0x00,0xFE,0x22,0xFA,0xA3,0xFA,0xA2,0x22,0x03,0x01,0x01,0x08,0x07,\n0x01,0x0F,0x00,0x0F,0x00,0x01,/*\"嘛\",1770*/},{\n\n0xFE,0x02,0xFE,0x00,0x7F,0x55,0x55,0x7F,0x55,0x55,0xC1,0x03,0x01,0x03,0x02,0x01,\n0x02,0x01,0x0A,0x09,0x0A,0x07,/*\"嗎\",1771*/},{\n\n0x10,0xFF,0x10,0x00,0x7F,0x49,0x49,0xFF,0x49,0x49,0x7F,0x04,0x07,0x02,0x08,0x09,\n0x09,0x09,0x0F,0x09,0x09,0x09,/*\"埋\",1772*/},{\n\n0x07,0xF5,0x55,0x57,0x55,0x55,0x55,0x57,0x55,0xF5,0x07,0x00,0x07,0x0D,0x05,0x05,\n0x05,0x05,0x05,0x0D,0x07,0x00,/*\"買\",1773*/},{\n\n0x52,0x4A,0x26,0xAA,0xD2,0xBF,0x92,0xAA,0xA6,0x4A,0x52,0x08,0x09,0x09,0x0A,0x04,\n0x04,0x04,0x0A,0x01,0x00,0x00,/*\"麥\",1774*/},{\n\n0x3A,0xEA,0xAA,0xBA,0xAA,0xAF,0xAA,0xBA,0xAA,0xEA,0x3A,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"賣\",1775*/},{\n\n0x11,0xF2,0x00,0x82,0xFA,0xAF,0xFA,0xAF,0xFA,0x82,0x00,0x08,0x07,0x08,0x0F,0x08,\n0x0A,0x0B,0x0A,0x0C,0x0F,0x08,/*\"邁\",1776*/},{\n\n0xFE,0x92,0xFE,0x00,0xFE,0x02,0xFA,0x0A,0xF9,0x45,0x20,0x07,0x08,0x0F,0x08,0x07,\n0x00,0x0F,0x04,0x01,0x06,0x08,/*\"脈\",1777*/},{\n\n0xFE,0x92,0xFE,0x00,0xE2,0xAF,0x2A,0xFA,0xAA,0x2F,0xE2,0x0F,0x04,0x0F,0x00,0x0F,\n0x02,0x01,0x0F,0x02,0x09,0x0F,/*\"瞞\",1778*/},{\n\n0xFA,0xAD,0xFA,0x00,0x70,0x5F,0x75,0x55,0x75,0x5F,0x70,0x0F,0x04,0x02,0x04,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"饅\",1779*/},{\n\n0x56,0x9D,0xD4,0x80,0xBA,0xEB,0xBA,0x80,0xD6,0x9D,0x54,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蠻\",1780*/},{\n\n0x22,0x44,0x02,0xE2,0xAF,0x2A,0xFA,0xAA,0x2F,0xE2,0x02,0x04,0x02,0x00,0x0F,0x02,\n0x01,0x0F,0x02,0x09,0x0F,0x00,/*\"滿\",1781*/},{\n\n0xC2,0x7A,0x4A,0xCF,0x5A,0x6A,0x4A,0xCF,0x4A,0x7A,0xC2,0x09,0x09,0x0B,0x05,0x05,\n0x05,0x05,0x05,0x0B,0x09,0x09,/*\"蔓\",1782*/},{\n\n0x70,0x5F,0x55,0x75,0x55,0x55,0x55,0x75,0x55,0x5F,0x70,0x08,0x09,0x0B,0x05,0x05,\n0x05,0x05,0x05,0x0B,0x09,0x08,/*\"曼\",1783*/},{\n\n0x78,0x00,0xFF,0x04,0x70,0x5F,0x75,0x55,0x75,0x5F,0x70,0x00,0x00,0x0F,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"慢\",1784*/},{\n\n0x10,0x21,0x02,0x70,0x5F,0x75,0x55,0x55,0x75,0x5F,0x70,0x04,0x02,0x01,0x08,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"漫\",1785*/},{\n\n0x55,0x56,0x54,0x00,0x70,0x5F,0x75,0x55,0x75,0x5F,0x70,0x0F,0x05,0x0F,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"謾\",1786*/},{\n\n0x44,0x44,0xC4,0x4F,0x44,0x54,0x64,0x4F,0x44,0x44,0x44,0x00,0x00,0x0F,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x00,/*\"芒\",1787*/},{\n\n0x94,0x24,0x44,0x4F,0xC4,0x44,0x54,0x6F,0x44,0x44,0x44,0x08,0x05,0x00,0x00,0x0F,\n0x08,0x08,0x08,0x08,0x08,0x00,/*\"茫\",1788*/},{\n\n0x02,0xEE,0xAA,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xEA,0x02,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"盲\",1789*/},{\n\n0x08,0xF9,0x0A,0x08,0x00,0xFF,0x49,0x49,0xF9,0x49,0x4F,0x00,0x07,0x04,0x04,0x00,\n0x0F,0x04,0x00,0x03,0x04,0x0E,/*\"氓\",1790*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0xF8,0x09,0x0A,0x08,0x08,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x08,0x08,0x08,0x08,0x00,/*\"忙\",1791*/},{\n\n0x82,0x92,0x52,0xB7,0x12,0x1A,0x12,0xB7,0x5A,0x92,0x82,0x02,0x02,0x0A,0x07,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"莽\",1792*/},{\n\n0xA4,0xAA,0x55,0xA8,0xC4,0x00,0xF2,0x97,0xF2,0x97,0xF2,0x02,0x02,0x09,0x08,0x07,\n0x00,0x0F,0x04,0x07,0x04,0x0F,/*\"貓\",1793*/},{\n\n0x42,0x4A,0x4A,0x4F,0xDA,0x6A,0xCA,0x6F,0x5A,0x4A,0xC2,0x04,0x04,0x02,0x01,0x00,\n0x08,0x0F,0x00,0x00,0x01,0x00,/*\"茅\",1794*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xF2,0x97,0xF2,0x97,0xF2,0x08,0x09,0x07,0x05,0x04,\n0x00,0x0F,0x04,0x07,0x04,0x0F,/*\"錨\",1795*/},{\n\n0x80,0x82,0x92,0x92,0x92,0xFE,0x49,0x49,0x49,0x41,0x40,0x00,0x00,0x00,0x00,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"毛\",1796*/},{\n\n0x10,0x10,0x11,0x91,0x55,0x35,0xF9,0x15,0x13,0x91,0x70,0x02,0x02,0x01,0x00,0x08,\n0x08,0x0F,0x00,0x00,0x00,0x00,/*\"矛\",1797*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFE,0x82,0xFD,0x00,0xFE,0x02,0xFE,0x0A,0x0F,0x05,0x00,0x09,\n0x04,0x03,0x00,0x0F,0x01,0x01,/*\"鉚\",1798*/},{\n\n0xFE,0x02,0x82,0x81,0xF9,0x00,0xFE,0x02,0x02,0x02,0xFE,0x01,0x09,0x04,0x02,0x01,\n0x00,0x0F,0x00,0x00,0x01,0x01,/*\"卯\",1799*/},{\n\n0x02,0xF2,0x12,0x17,0x12,0x12,0xFA,0x17,0x1A,0xD2,0x12,0x08,0x07,0x00,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x0E,/*\"茂\",1800*/},{\n\n0x00,0x0F,0xE1,0xA5,0xA5,0xA5,0xA5,0xA5,0xA5,0xE1,0x0F,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"冒\",1801*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x00,0xEF,0xA1,0xA5,0xA1,0xEF,0x03,0x00,0x0F,0x02,0x03,\n0x00,0x0F,0x0A,0x0A,0x0A,0x0F,/*\"帽\",1802*/},{\n\n0xA4,0xAA,0x55,0xE8,0x00,0x7C,0xD6,0x55,0xD4,0x54,0x7C,0x02,0x0A,0x09,0x07,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"貌\",1803*/},{\n\n0x0E,0xEA,0xAA,0xA5,0xA8,0xA2,0xAA,0xA6,0xA2,0xEA,0x0E,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"貿\",1804*/},{\n\n0x00,0xFE,0x2A,0x1A,0x3E,0x8A,0x53,0x0A,0x3E,0x9A,0x2A,0x08,0x07,0x00,0x08,0x0D,\n0x0D,0x0B,0x0B,0x09,0x0C,0x08,/*\"麼\",1805*/},{\n\n0x22,0x22,0xFE,0x22,0x22,0x10,0xEC,0x0B,0x88,0x78,0x08,0x04,0x04,0x07,0x02,0x0A,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"玫\",1806*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0x10,0xEC,0x0B,0x88,0x78,0x08,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"枚\",1807*/},{\n\n0x88,0x68,0xFF,0x48,0xC4,0x7B,0x4A,0x6A,0x4A,0xFA,0x42,0x00,0x00,0x0F,0x00,0x03,\n0x02,0x02,0x0B,0x0A,0x07,0x02,/*\"梅\",1808*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x44,0xFB,0x4A,0x6A,0x4A,0xFA,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x03,0x02,0x0B,0x0A,0x07,/*\"酶\",1809*/},{\n\n0x24,0xF2,0x09,0xF6,0x54,0xF7,0x54,0xF6,0xE8,0x07,0xFC,0x00,0x0F,0x04,0x0D,0x05,\n0x0F,0x05,0x0D,0x04,0x03,0x0C,/*\"黴\",1810*/},{\n\n0x78,0x00,0xFF,0x10,0x8A,0xBF,0xAA,0xEA,0xAA,0xBF,0x82,0x08,0x06,0x01,0x02,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"煤\",1811*/},{\n\n0x10,0x21,0x02,0x10,0xC8,0x47,0x42,0x52,0x52,0xCE,0x00,0x04,0x02,0x01,0x08,0x08,\n0x05,0x02,0x02,0x05,0x08,0x08,/*\"沒\",1812*/},{\n\n0x00,0xFF,0x09,0xE9,0xA9,0xA9,0xAF,0xA9,0xA9,0xA9,0xEF,0x08,0x07,0x00,0x0F,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0A,0x0F,/*\"眉\",1813*/},{\n\n0x88,0x78,0x0F,0xF8,0x82,0xBF,0xAA,0xEA,0xAA,0xBF,0x82,0x08,0x05,0x02,0x0D,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"媒\",1814*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x40,0x55,0x56,0xFC,0x56,0x55,0x44,0x08,0x09,0x07,0x04,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"鎂\",1815*/},{\n\n0x48,0xC4,0x7B,0x4A,0xCA,0x5A,0x6A,0x4A,0x4A,0xFA,0x42,0x00,0x03,0x02,0x02,0x02,\n0x03,0x0A,0x0A,0x0A,0x07,0x02,/*\"每\",1816*/},{\n\n0x40,0x54,0x55,0x56,0x54,0xFC,0x54,0x56,0x55,0x54,0x40,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"美\",1817*/},{\n\n0xFE,0x22,0x22,0xFE,0x20,0x24,0xA4,0xFF,0xA4,0x24,0x20,0x07,0x02,0x02,0x07,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"昧\",1818*/},{\n\n0x86,0xBA,0xA2,0xFE,0x42,0x53,0x52,0xFE,0x52,0x52,0x46,0x08,0x07,0x00,0x0F,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"寐\",1819*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0x24,0xA4,0xFF,0xA4,0x24,0x20,0x08,0x05,0x02,0x0D,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"妹\",1820*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFF,0x09,0xE9,0xAF,0xA9,0xEF,0x08,0x05,0x02,0x05,0x08,\n0x07,0x00,0x0F,0x0A,0x0A,0x0F,/*\"媚\",1821*/},{\n\n0x00,0xFF,0x49,0x49,0x7F,0x00,0x00,0x7F,0x49,0x49,0xFF,0x00,0x0F,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x08,0x0F,/*\"門\",1822*/},{\n\n0xFF,0x15,0x15,0x1F,0x20,0x40,0x00,0x9F,0x15,0x15,0xFF,0x0F,0x04,0x03,0x00,0x07,\n0x08,0x0C,0x00,0x03,0x08,0x0F,/*\"悶\",1823*/},{\n\n0x10,0xFC,0x03,0x00,0xFF,0x49,0x7F,0x00,0x7F,0x49,0xFF,0x00,0x0F,0x00,0x00,0x0F,\n0x00,0x00,0x00,0x00,0x08,0x0F,/*\"們\",1824*/},{\n\n0xF2,0x52,0x52,0x57,0xF2,0x02,0xFA,0x4F,0x4A,0x4A,0xFA,0x07,0x02,0x02,0x02,0x0B,\n0x04,0x03,0x01,0x09,0x09,0x0F,/*\"萌\",1825*/},{\n\n0x1A,0x8A,0xAA,0x6F,0x6A,0xAA,0x2A,0x2F,0xAA,0x4A,0x1A,0x08,0x0A,0x0A,0x05,0x05,\n0x0A,0x0F,0x01,0x02,0x04,0x04,/*\"蒙\",1826*/},{\n\n0x88,0x68,0xFF,0x48,0x9A,0xAF,0x6A,0xAA,0x2A,0xAF,0x5A,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x05,0x0A,0x0F,0x02,0x04,/*\"檬\",1827*/},{\n\n0x3E,0x2A,0x2A,0x2A,0xBE,0x40,0x3F,0x15,0x15,0x55,0x7F,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盟\",1828*/},{\n\n0x4A,0xF9,0x4A,0x00,0x88,0x89,0xA9,0xBD,0x8B,0x89,0x88,0x0A,0x0F,0x05,0x08,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"錳\",1829*/},{\n\n0x8A,0x44,0xFB,0x00,0x88,0x89,0xA9,0xBD,0x8B,0x89,0x88,0x08,0x08,0x07,0x08,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"猛\",1830*/},{\n\n0x82,0xBA,0xAA,0xAF,0xBA,0xAA,0xBA,0xAF,0xAA,0xBA,0x82,0x01,0x08,0x0A,0x0E,0x0B,\n0x0A,0x06,0x06,0x02,0x00,0x01,/*\"夢\",1831*/},{\n\n0x08,0x08,0x09,0x49,0x49,0x79,0x0D,0x0B,0x09,0x08,0x08,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"孟\",1832*/},{\n\n0xFE,0x92,0x92,0xFE,0x24,0x28,0xA0,0xFF,0xA0,0x28,0x24,0x0F,0x04,0x04,0x0F,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"眯\",1833*/},{\n\n0xFD,0xA5,0x9F,0xA5,0xFD,0x22,0xE4,0x82,0x54,0xFF,0x94,0x0F,0x04,0x04,0x04,0x0F,\n0x08,0x07,0x08,0x08,0x0B,0x08,/*\"醚\",1834*/},{\n\n0x00,0xFE,0x6A,0x5A,0x7E,0xEA,0x13,0xEA,0x7E,0x5A,0x6A,0x08,0x07,0x05,0x05,0x05,\n0x0F,0x00,0x0F,0x05,0x05,0x05,/*\"靡\",1835*/},{\n\n0x00,0xFE,0x2A,0x5A,0xBE,0x0A,0xD3,0x0A,0xBE,0x5A,0x2A,0x08,0x07,0x09,0x05,0x03,\n0x01,0x0F,0x01,0x03,0x05,0x09,/*\"糜\",1836*/},{\n\n0x10,0x11,0xF2,0x00,0x12,0x94,0x50,0xFF,0x50,0x94,0x12,0x08,0x04,0x03,0x04,0x09,\n0x08,0x08,0x0F,0x08,0x08,0x09,/*\"迷\",1837*/},{\n\n0x55,0x56,0x54,0x11,0xF2,0x00,0x92,0x54,0xFF,0x54,0x92,0x0F,0x05,0x0F,0x04,0x03,\n0x04,0x08,0x08,0x0B,0x08,0x08,/*\"謎\",1838*/},{\n\n0xF2,0x9E,0x00,0xFD,0xAB,0x49,0xFF,0xA9,0x49,0xAB,0xFD,0x08,0x0F,0x00,0x0F,0x02,\n0x01,0x0F,0x02,0x01,0x0A,0x0F,/*\"彌\",1839*/},{\n\n0x10,0x12,0x14,0x98,0x50,0xFF,0x50,0x98,0x14,0x12,0x10,0x02,0x02,0x01,0x00,0x00,\n0x0F,0x00,0x00,0x01,0x02,0x02,/*\"米\",1840*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0x20,0xF8,0x01,0xC2,0x30,0xCC,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x07,0x09,0x08,0x0E,0x00,/*\"祕\",1841*/},{\n\n0x02,0xFA,0xAE,0xAA,0xAA,0xAE,0xA9,0xA9,0xAD,0xFB,0x01,0x08,0x0B,0x0A,0x06,0x02,\n0x02,0x06,0x0A,0x0A,0x0B,0x0C,/*\"覓\",1842*/},{\n\n0x20,0x42,0x04,0xE0,0x00,0xF9,0x02,0xC4,0x30,0x4C,0x80,0x08,0x04,0x01,0x08,0x04,\n0x07,0x09,0x08,0x08,0x0C,0x01,/*\"泌\",1843*/},{\n\n0x26,0x9A,0xC2,0xDA,0xA6,0xEB,0xB2,0xAA,0xB2,0x8A,0x36,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蜜\",1844*/},{\n\n0x46,0x32,0x82,0xB2,0x46,0x6B,0x52,0x4A,0x62,0x12,0x66,0x00,0x0E,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0E,0x00,/*\"密\",1845*/},{\n\n0x03,0x75,0x55,0xDF,0x55,0x75,0x55,0x5F,0x55,0x75,0x03,0x05,0x03,0x0D,0x05,0x05,\n0x0F,0x05,0x05,0x0D,0x03,0x05,/*\"冪\",1846*/},{\n\n0x88,0x68,0xFF,0x48,0x80,0xBE,0xAA,0xEB,0xAA,0xBE,0x80,0x00,0x00,0x0F,0x00,0x07,\n0x00,0x00,0x0F,0x00,0x04,0x07,/*\"棉\",1847*/},{\n\n0xFF,0x49,0x49,0xFF,0x00,0xFF,0x49,0x49,0xF9,0x49,0x4F,0x07,0x02,0x02,0x07,0x00,\n0x0F,0x04,0x00,0x03,0x04,0x0E,/*\"眠\",1848*/},{\n\n0xDC,0xB3,0xC8,0x00,0x80,0xBE,0xAA,0xEB,0xAA,0xBE,0x80,0x0E,0x00,0x06,0x00,0x07,\n0x00,0x00,0x0F,0x00,0x04,0x07,/*\"綿\",1849*/},{\n\n0x40,0xEF,0x51,0x55,0x55,0xD5,0x55,0x75,0x41,0xCF,0x00,0x08,0x09,0x05,0x05,0x03,\n0x01,0x07,0x09,0x09,0x09,0x0C,/*\"冕\",1850*/},{\n\n0x10,0xF8,0x94,0x93,0x92,0xF2,0x9A,0x96,0x90,0xF0,0x00,0x08,0x08,0x04,0x02,0x01,\n0x00,0x07,0x08,0x08,0x08,0x0C,/*\"免\",1851*/},{\n\n0x08,0xF4,0x93,0xFA,0x96,0xF0,0x08,0xFF,0x08,0xF8,0x00,0x08,0x04,0x02,0x01,0x06,\n0x08,0x0A,0x09,0x0A,0x0B,0x0C,/*\"勉\",1852*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xF4,0x93,0xFA,0x96,0xF0,0x00,0x08,0x05,0x02,0x05,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"娩\",1853*/},{\n\n0xDC,0xB3,0xC8,0x00,0xF2,0x12,0xFA,0x56,0xF2,0x12,0xF2,0x0E,0x00,0x06,0x00,0x0F,\n0x04,0x07,0x05,0x07,0x04,0x0F,/*\"緬\",1854*/},{\n\n0x02,0xF2,0x12,0x12,0xFA,0x56,0x52,0xF2,0x12,0x12,0xF2,0x00,0x0F,0x04,0x04,0x07,\n0x05,0x05,0x07,0x04,0x04,0x0F,/*\"面\",1855*/},{\n\n0x02,0xF2,0x92,0x97,0x92,0xF2,0x92,0x97,0x92,0xF2,0x02,0x00,0x0F,0x04,0x04,0x04,\n0x07,0x04,0x04,0x04,0x0F,0x00,/*\"苗\",1856*/},{\n\n0x88,0x88,0xFF,0x48,0xF2,0x97,0x92,0xF2,0x92,0x97,0xF2,0x00,0x08,0x0F,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"描\",1857*/},{\n\n0xFE,0x92,0xFE,0x00,0xF2,0x97,0x92,0xF2,0x92,0x97,0xF2,0x0F,0x04,0x0F,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"瞄\",1858*/},{\n\n0x52,0x72,0xAA,0xD7,0x02,0xF2,0x5A,0x57,0x52,0xF2,0x02,0x05,0x0D,0x0A,0x07,0x08,\n0x05,0x03,0x01,0x07,0x09,0x0C,/*\"藐\",1859*/},{\n\n0x12,0xD2,0xFE,0x91,0x40,0x38,0x00,0xFF,0x00,0x04,0xB8,0x01,0x00,0x0F,0x00,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,/*\"秒\",1860*/},{\n\n0x22,0x44,0xFE,0x52,0xFE,0x40,0x38,0x00,0xFF,0x04,0xB8,0x04,0x02,0x07,0x02,0x03,\n0x08,0x08,0x04,0x02,0x01,0x00,/*\"渺\",1861*/},{\n\n0x00,0xFE,0x02,0xEA,0xBE,0xEA,0x03,0xFA,0x4A,0xFA,0x02,0x08,0x07,0x02,0x03,0x0E,\n0x03,0x0A,0x07,0x09,0x0F,0x00,/*\"廟\",1862*/},{\n\n0x88,0x78,0x0F,0xF8,0x40,0x38,0x00,0xFF,0x00,0x04,0xB8,0x08,0x05,0x02,0x05,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,/*\"妙\",1863*/},{\n\n0x02,0xBA,0xAA,0xAF,0xBA,0xEA,0xBA,0xEF,0xAA,0xBA,0x82,0x08,0x07,0x02,0x04,0x00,\n0x09,0x0A,0x04,0x0A,0x09,0x0C,/*\"蔑\",1864*/},{\n\n0x22,0x44,0x00,0xFC,0x54,0xF4,0x94,0x54,0xFF,0xC4,0x35,0x04,0x02,0x08,0x07,0x02,\n0x01,0x0A,0x04,0x03,0x04,0x0E,/*\"滅\",1865*/},{\n\n0x00,0xFF,0x49,0x49,0x49,0x49,0xF9,0x49,0x49,0x4F,0x40,0x00,0x0F,0x04,0x02,0x00,\n0x00,0x00,0x01,0x02,0x04,0x0E,/*\"民\",1866*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xFF,0x49,0x49,0xF9,0x49,0x4F,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x04,0x00,0x03,0x04,0x0E,/*\"抿\",1867*/},{\n\n0x00,0xFE,0x02,0x02,0xFE,0x02,0xFE,0x02,0x02,0xFE,0x00,0x08,0x0F,0x08,0x08,0x0F,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"皿\",1868*/},{\n\n0x44,0xFB,0x4A,0x6A,0x4A,0xFA,0x50,0xEF,0x08,0xF8,0x08,0x00,0x03,0x02,0x0B,0x0A,\n0x07,0x0A,0x05,0x02,0x05,0x08,/*\"敏\",1869*/},{\n\n0x78,0x00,0xFF,0x08,0xFF,0x55,0x5F,0x60,0xDF,0x55,0xFF,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x05,0x02,0x05,0x08,0x0F,/*\"憫\",1870*/},{\n\n0xFF,0x15,0x15,0xDF,0x40,0xE0,0x40,0xDF,0x15,0x15,0xFF,0x0F,0x00,0x04,0x05,0x05,\n0x07,0x05,0x05,0x06,0x08,0x0F,/*\"閩\",1871*/},{\n\n0xFF,0x11,0x11,0x11,0xFF,0x00,0xFF,0x49,0x49,0x49,0xFF,0x03,0x01,0x01,0x01,0x09,\n0x04,0x03,0x00,0x08,0x08,0x0F,/*\"明\",1872*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x03,0x7D,0x55,0xD5,0x7D,0x03,0x04,0x04,0x03,0x02,0x07,\n0x09,0x05,0x01,0x01,0x05,0x09,/*\"螟\",1873*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0xAA,0xAB,0xAA,0xAA,0xBE,0xA0,0x03,0x01,0x03,0x00,0x06,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鳴\",1874*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x10,0x88,0xD4,0xA7,0xA4,0x94,0x8C,0x08,0x09,0x07,0x04,0x01,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"銘\",1875*/},{\n\n0x00,0x10,0x88,0x94,0xE7,0xC4,0xA4,0xA4,0x94,0x8C,0x80,0x01,0x01,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"名\",1876*/},{\n\n0x10,0xD0,0x48,0x54,0xD2,0x11,0xD2,0x54,0x48,0xD0,0x10,0x00,0x07,0x02,0x02,0x07,\n0x00,0x0F,0x00,0x04,0x07,0x00,/*\"命\",1877*/},{\n\n0x55,0x56,0x54,0x40,0x4B,0xA5,0xAF,0x50,0x2B,0x45,0x4F,0x0F,0x05,0x0F,0x00,0x0A,\n0x0A,0x0A,0x0A,0x05,0x04,0x02,/*\"謬\",1878*/},{\n\n0x88,0xFF,0x48,0x02,0xFA,0xAF,0xAA,0xAA,0xAF,0xFA,0x02,0x08,0x0F,0x00,0x0A,0x0A,\n0x06,0x03,0x02,0x06,0x0A,0x0A,/*\"摸\",1879*/},{\n\n0x42,0x42,0xFA,0x4F,0x5A,0xEA,0x4A,0x4F,0xFA,0x42,0x42,0x02,0x05,0x04,0x05,0x0D,\n0x0F,0x05,0x05,0x04,0x05,0x02,/*\"摹\",1880*/},{\n\n0x02,0xFA,0x6F,0xAA,0xFA,0xAE,0xCA,0xAA,0xFF,0xAA,0x6A,0x08,0x07,0x04,0x02,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"蘑\",1881*/},{\n\n0x88,0x68,0xFF,0x48,0x02,0xFA,0xAF,0xAA,0xAF,0xFA,0x02,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"模\",1882*/},{\n\n0x00,0xFF,0x49,0xFF,0x02,0xFA,0xAF,0xAA,0xAF,0xFA,0x02,0x08,0x07,0x08,0x0F,0x02,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"膜\",1883*/},{\n\n0x00,0xFE,0xAA,0x9A,0xBE,0x8A,0x93,0x8A,0xBE,0x9A,0xAA,0x08,0x07,0x04,0x02,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"磨\",1884*/},{\n\n0x00,0xFE,0x2A,0x5A,0x7E,0x4A,0xD3,0x4A,0x7E,0x5A,0x2A,0x08,0x07,0x04,0x05,0x05,\n0x0D,0x0F,0x05,0x05,0x05,0x04,/*\"摩\",1885*/},{\n\n0x00,0xFE,0x1A,0xEA,0xBE,0xAA,0xF3,0xAA,0xBE,0xEA,0x1A,0x08,0x07,0x08,0x0B,0x06,\n0x03,0x06,0x0A,0x0E,0x0B,0x0C,/*\"魔\",1886*/},{\n\n0x88,0x88,0xFF,0x48,0x04,0x24,0xA4,0xFF,0xA4,0x24,0x04,0x00,0x08,0x0F,0x00,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"抹\",1887*/},{\n\n0x04,0x24,0x24,0xA4,0x64,0xFF,0x64,0xA4,0x24,0x24,0x04,0x02,0x02,0x01,0x00,0x00,\n0x0F,0x00,0x00,0x01,0x02,0x02,/*\"末\",1888*/},{\n\n0x02,0xFA,0xAA,0xAF,0xAA,0xAA,0xAA,0xAF,0xAA,0xFA,0x02,0x0A,0x0A,0x0A,0x06,0x03,\n0x02,0x02,0x06,0x0A,0x0A,0x0A,/*\"莫\",1889*/},{\n\n0x40,0xD7,0x55,0x57,0xD5,0x7F,0xD5,0x57,0x55,0xD7,0x40,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"墨\",1890*/},{\n\n0x5F,0x55,0x51,0xFF,0x55,0x5F,0x00,0x10,0xFF,0x12,0x14,0x0A,0x06,0x0A,0x05,0x09,\n0x05,0x08,0x07,0x00,0x07,0x08,/*\"默\",1891*/},{\n\n0x22,0x44,0x00,0x04,0x24,0xA4,0xFF,0xA4,0x24,0x24,0x04,0x04,0x02,0x04,0x02,0x01,\n0x00,0x0F,0x00,0x01,0x02,0x04,/*\"沫\",1892*/},{\n\n0x22,0x44,0x02,0xFA,0xAF,0xAA,0xAA,0xAA,0xAF,0xFA,0x02,0x04,0x02,0x08,0x0A,0x0A,\n0x06,0x03,0x06,0x0A,0x0A,0x0A,/*\"漠\",1893*/},{\n\n0x06,0xEA,0xAA,0xBE,0xAA,0xAB,0xAA,0xBE,0xAA,0xEA,0x06,0x0A,0x0B,0x0A,0x06,0x02,\n0x02,0x02,0x06,0x0A,0x0B,0x0A,/*\"寞\",1894*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0xF2,0x92,0x9A,0x96,0x92,0xF2,0x0F,0x02,0x02,0x01,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"陌\",1895*/},{\n\n0x54,0x55,0x56,0x54,0x82,0xBF,0xAA,0xEA,0xAA,0xBF,0x82,0x0F,0x05,0x05,0x0F,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"謀\",1896*/},{\n\n0x00,0x88,0x6C,0x4A,0x49,0xF8,0x48,0x4A,0x4C,0x58,0x00,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"牟\",1897*/},{\n\n0x82,0x82,0xBF,0xAA,0xAA,0xEA,0xAA,0xAA,0xBF,0x82,0x82,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"某\",1898*/},{\n\n0x88,0x88,0xFF,0x48,0xA0,0x7E,0xAA,0x32,0x22,0xFE,0x20,0x00,0x08,0x0F,0x00,0x03,\n0x02,0x02,0x0B,0x0A,0x07,0x02,/*\"拇\",1899*/},{\n\n0x9C,0x88,0xFF,0x48,0x00,0x10,0x10,0xFF,0x10,0x10,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"牡\",1900*/},{\n\n0xF4,0x95,0xF6,0x94,0xF4,0x20,0x18,0x07,0xC4,0x3C,0x00,0x0F,0x04,0x07,0x04,0x0F,\n0x08,0x04,0x03,0x02,0x04,0x08,/*\"畝\",1901*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0xFE,0xAA,0x32,0x22,0xFE,0x20,0x08,0x05,0x02,0x05,0x08,\n0x03,0x02,0x0B,0x0A,0x07,0x02,/*\"姆\",1902*/},{\n\n0x20,0xFE,0x22,0x22,0xA2,0x2A,0x32,0x22,0x22,0xFE,0x20,0x00,0x03,0x02,0x02,0x02,\n0x03,0x0A,0x0A,0x0A,0x07,0x02,/*\"母\",1903*/},{\n\n0x82,0xBA,0xAA,0xEF,0xAA,0xBA,0xAA,0xAF,0xAA,0xBA,0x82,0x04,0x02,0x09,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x09,0x02,0x04,/*\"墓\",1904*/},{\n\n0x82,0xBA,0xAA,0xEF,0xAA,0xBA,0xAA,0xAF,0xAA,0xBA,0x82,0x04,0x02,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x02,0x04,/*\"暮\",1905*/},{\n\n0x82,0xBA,0xAA,0xEF,0xAA,0xBA,0xAA,0xAF,0xAA,0xBA,0x82,0x04,0x02,0x0F,0x02,0x02,\n0x0F,0x02,0x0A,0x0F,0x02,0x04,/*\"幕\",1906*/},{\n\n0x82,0xBA,0xAA,0xEF,0xAA,0xBA,0xAA,0xAF,0xAA,0xBA,0x82,0x04,0x0A,0x0B,0x06,0x03,\n0x02,0x0A,0x0A,0x07,0x02,0x04,/*\"募\",1907*/},{\n\n0x82,0xBA,0xAA,0xEF,0xAA,0xBA,0xAA,0xAF,0xAA,0xBA,0x82,0x02,0x01,0x04,0x02,0x08,\n0x0F,0x02,0x04,0x02,0x05,0x02,/*\"慕\",1908*/},{\n\n0x08,0x08,0x88,0x68,0x18,0xFF,0x18,0x68,0x88,0x08,0x08,0x02,0x01,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x01,0x02,/*\"木\",1909*/},{\n\n0x00,0xFE,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0xFE,0x00,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"目\",1910*/},{\n\n0xFE,0x92,0x92,0xFE,0x90,0x54,0x34,0x9F,0x34,0x54,0x90,0x0F,0x04,0x04,0x0F,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"睦\",1911*/},{\n\n0x90,0x8E,0x88,0xFF,0x48,0x10,0xEC,0x0B,0x88,0x78,0x08,0x00,0x00,0x00,0x0F,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"牧\",1912*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0x7E,0xAB,0xEA,0x2A,0x7E,0x80,0x01,0x00,0x0F,0x00,0x00,\n0x09,0x0A,0x0A,0x05,0x04,0x00,/*\"穆\",1913*/},{\n\n0x08,0x88,0xBC,0xAC,0xAA,0xA9,0xAA,0xAC,0xBC,0x48,0x08,0x02,0x02,0x02,0x02,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"拿\",1914*/},{\n\n0xFC,0x04,0xFC,0x92,0xFE,0x92,0xFE,0x00,0xFE,0x32,0xCE,0x03,0x01,0x0B,0x04,0x03,\n0x08,0x0F,0x00,0x0F,0x02,0x01,/*\"哪\",1915*/},{\n\n0xFC,0x04,0xFC,0x00,0xF8,0x08,0xC9,0x3E,0xC8,0x08,0xF8,0x03,0x01,0x03,0x00,0x0F,\n0x01,0x00,0x00,0x01,0x08,0x0F,/*\"吶\",1916*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xFC,0x84,0x7F,0x84,0xFC,0x08,0x09,0x07,0x05,0x04,\n0x00,0x0F,0x00,0x00,0x08,0x0F,/*\"鈉\",1917*/},{\n\n0x92,0x92,0xFE,0x92,0x92,0xFE,0x00,0xFE,0x02,0x32,0xCE,0x08,0x04,0x03,0x08,0x08,\n0x07,0x00,0x0F,0x02,0x02,0x01,/*\"那\",1918*/},{\n\n0xF8,0x0F,0xF8,0x92,0xFE,0x92,0xFE,0x00,0xFE,0x32,0xCE,0x0D,0x02,0x0D,0x04,0x03,\n0x08,0x0F,0x00,0x0F,0x02,0x01,/*\"娜\",1919*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0xFC,0x84,0x7F,0x84,0xFC,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x0F,0x00,0x00,0x08,0x0F,/*\"納\",1920*/},{\n\n0x08,0xA4,0xAB,0xAA,0xAA,0xAA,0x2A,0x2A,0xEA,0x0A,0x02,0x08,0x04,0x03,0x00,0x0A,\n0x0B,0x06,0x00,0x03,0x04,0x0E,/*\"氖\",1921*/},{\n\n0x00,0x02,0x02,0xFE,0x02,0x02,0x02,0x62,0x5A,0x46,0xC0,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x08,0x08,0x08,0x07,/*\"乃\",1922*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x02,0xFE,0x02,0x72,0x4E,0xC0,0x08,0x05,0x02,0x05,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"奶\",1923*/},{\n\n0xF2,0x12,0xFA,0x16,0xF2,0x12,0xF2,0x48,0x88,0xFF,0x08,0x0F,0x00,0x07,0x00,0x07,\n0x08,0x0F,0x00,0x08,0x0F,0x00,/*\"耐\",1924*/},{\n\n0x92,0x92,0xAA,0xAA,0xA6,0xA3,0xA6,0xAA,0xAA,0x92,0x92,0x08,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x08,/*\"奈\",1925*/},{\n\n0x02,0xFA,0x0A,0x5A,0x6A,0xCF,0x6A,0x5A,0x0A,0xFA,0x02,0x00,0x0F,0x01,0x01,0x01,\n0x07,0x01,0x09,0x09,0x0F,0x00,/*\"南\",1926*/},{\n\n0x00,0x7F,0x49,0x49,0xC9,0x7F,0x49,0x49,0x49,0x7F,0x00,0x09,0x09,0x05,0x03,0x01,\n0x01,0x01,0x09,0x09,0x09,0x07,/*\"男\",1927*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x10,0xFC,0x27,0xFC,0x25,0x24,0x0A,0x06,0x03,0x06,0x0A,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"難\",1928*/},{\n\n0x62,0xAE,0xAA,0xEA,0xAA,0xBF,0xAA,0xEA,0xAA,0xAE,0x62,0x0A,0x0A,0x06,0x0F,0x0A,\n0x02,0x02,0x07,0x0A,0x0A,0x0A,/*\"囊\",1929*/},{\n\n0x84,0x84,0xFF,0x44,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x00,0x08,0x0F,0x00,0x0A,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"撓\",1930*/},{\n\n0x00,0xFF,0x49,0xFF,0x00,0xE6,0xA9,0x36,0x29,0xA6,0xE9,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x0A,0x09,0x09,0x0A,0x0F,/*\"腦\",1931*/},{\n\n0x78,0x00,0xFF,0x08,0xC4,0x6A,0xD5,0x4A,0xD5,0x4A,0xD1,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x06,0x05,0x06,0x04,0x0F,/*\"惱\",1932*/},{\n\n0xFF,0x00,0x55,0x5F,0x55,0xE0,0x55,0x5F,0x55,0x00,0xFF,0x0F,0x00,0x07,0x01,0x01,\n0x0F,0x01,0x05,0x07,0x08,0x0F,/*\"鬧\",1933*/},{\n\n0x22,0x44,0x00,0xF8,0xA8,0xA8,0xAF,0xAA,0xAA,0xFA,0x02,0x04,0x02,0x00,0x02,0x02,\n0x02,0x0F,0x02,0x02,0x02,0x02,/*\"淖\",1934*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0xFE,0x12,0xD2,0x12,0x92,0x5E,0x03,0x01,0x01,0x03,0x08,\n0x07,0x00,0x07,0x09,0x08,0x0E,/*\"呢\",1935*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0x4A,0xD2,0x66,0x4A,0xD1,0x4D,0x00,0x0F,0x04,0x02,0x04,\n0x08,0x05,0x02,0x02,0x05,0x08,/*\"餒\",1936*/},{\n\n0xFC,0x04,0x05,0x85,0x66,0x1C,0x64,0x84,0x04,0x04,0xFC,0x0F,0x00,0x01,0x00,0x00,\n0x00,0x00,0x00,0x09,0x08,0x0F,/*\"內\",1937*/},{\n\n0xF8,0x0F,0xFC,0x94,0xFF,0x94,0xF4,0x10,0xEC,0x0B,0xF8,0x0D,0x02,0x05,0x02,0x0F,\n0x02,0x04,0x08,0x04,0x03,0x0C,/*\"嫩\",1938*/},{\n\n0x04,0xF6,0x55,0x54,0xF6,0x00,0xCF,0x14,0x12,0x91,0x18,0x00,0x0F,0x01,0x09,0x0F,\n0x00,0x07,0x0A,0x09,0x08,0x0E,/*\"能\",1939*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFE,0x12,0xD2,0x12,0x92,0x5E,0x08,0x05,0x02,0x05,0x08,\n0x07,0x00,0x07,0x09,0x08,0x0E,/*\"妮\",1940*/},{\n\n0x0C,0xE5,0xAD,0xA5,0x95,0x0F,0xA5,0xA5,0xAD,0xE5,0x0C,0x08,0x0B,0x0A,0x06,0x02,\n0x02,0x02,0x06,0x0A,0x0B,0x0C,/*\"霓\",1941*/},{\n\n0x10,0xFC,0x03,0x00,0xFE,0x92,0x81,0x90,0x92,0xFE,0x00,0x00,0x0F,0x00,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0C,/*\"倪\",1942*/},{\n\n0x10,0x21,0x02,0x00,0xFE,0x12,0xD2,0x12,0x92,0x52,0x1E,0x04,0x02,0x09,0x04,0x03,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"泥\",1943*/},{\n\n0x00,0x00,0xFE,0x12,0xD2,0x12,0x12,0x92,0x92,0x5E,0x00,0x08,0x06,0x01,0x00,0x07,\n0x09,0x09,0x08,0x08,0x08,0x0E,/*\"尼\",1944*/},{\n\n0x88,0xFF,0x48,0x37,0xEA,0x2D,0x90,0x15,0xF9,0x95,0xB3,0x08,0x0F,0x08,0x05,0x03,\n0x0D,0x07,0x08,0x0F,0x08,0x08,/*\"擬\",1945*/},{\n\n0x20,0x10,0xFC,0x03,0x10,0xCF,0x04,0xF4,0x04,0x54,0x8C,0x00,0x00,0x0F,0x00,0x02,\n0x01,0x08,0x0F,0x00,0x00,0x03,/*\"你\",1946*/},{\n\n0x00,0xFF,0x25,0xA5,0xEF,0xB5,0xA5,0xA5,0xAF,0xA5,0x25,0x00,0x0F,0x09,0x08,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"匿\",1947*/},{\n\n0xFF,0x49,0xFF,0x00,0xEA,0xAA,0xEA,0x02,0xFF,0x02,0x03,0x07,0x08,0x0F,0x00,0x0B,\n0x06,0x0B,0x00,0x03,0x04,0x0E,/*\"膩\",1948*/},{\n\n0x11,0xF2,0x04,0xF4,0x85,0x86,0xFC,0x86,0x85,0xF4,0x04,0x08,0x07,0x08,0x08,0x0C,\n0x0A,0x09,0x08,0x08,0x08,0x08,/*\"逆\",1949*/},{\n\n0x22,0x44,0x39,0xA9,0x29,0xEF,0x00,0x39,0xA9,0x29,0xEF,0x04,0x02,0x04,0x0A,0x09,\n0x07,0x00,0x04,0x0A,0x09,0x07,/*\"溺\",1950*/},{\n\n0x8A,0x8A,0xEA,0x8F,0x8A,0xFA,0xAA,0xAF,0xAA,0xAA,0x8A,0x00,0x0B,0x02,0x0A,0x02,\n0x0A,0x02,0x0A,0x02,0x0A,0x0E,/*\"蔫\",1951*/},{\n\n0x88,0x88,0xFF,0x48,0x08,0xC0,0x40,0x7F,0x48,0x48,0xC8,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"拈\",1952*/},{\n\n0x10,0x08,0xE7,0x24,0x24,0x24,0xFC,0x24,0x24,0x24,0x04,0x01,0x01,0x01,0x01,0x01,\n0x01,0x0F,0x01,0x01,0x01,0x01,/*\"年\",1953*/},{\n\n0xF2,0x2E,0xE2,0x00,0xFE,0xAA,0xAA,0xFA,0xAA,0xFA,0xAE,0x07,0x02,0x07,0x08,0x07,\n0x00,0x0F,0x04,0x03,0x04,0x0A,/*\"碾\",1954*/},{\n\n0x88,0xFF,0x48,0x00,0x6A,0xDF,0x6A,0xE0,0x6A,0xDF,0x6A,0x08,0x0F,0x00,0x00,0x04,\n0x07,0x05,0x0F,0x05,0x07,0x04,/*\"攆\",1955*/},{\n\n0x88,0xFF,0x48,0x00,0x08,0x14,0x92,0x19,0x52,0x34,0x08,0x08,0x0F,0x00,0x04,0x03,\n0x00,0x06,0x09,0x0C,0x01,0x06,/*\"捻\",1956*/},{\n\n0x10,0x10,0x28,0x24,0x2A,0x31,0xA2,0x64,0x08,0x10,0x10,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"念\",1957*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFC,0x55,0xD6,0x54,0x7C,0x80,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"娘\",1958*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x00,0xBA,0xEA,0xBB,0xEA,0xBA,0x0F,0x05,0x05,0x05,0x0F,\n0x0A,0x06,0x0F,0x0A,0x07,0x0A,/*\"釀\",1959*/},{\n\n0x00,0xFE,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xBE,0x80,0x80,0x08,0x03,0x0A,0x02,0x0A,\n0x02,0x0A,0x02,0x0A,0x0A,0x06,/*\"鳥\",1960*/},{\n\n0x00,0xFF,0x49,0x49,0xC9,0x09,0xF9,0x69,0x89,0x49,0x2F,0x08,0x07,0x04,0x02,0x01,\n0x08,0x0F,0x00,0x01,0x02,0x04,/*\"尿\",1961*/},{\n\n0x88,0xFF,0x48,0x00,0x7F,0x49,0x49,0xC9,0x49,0x49,0x7F,0x08,0x0F,0x00,0x08,0x09,\n0x09,0x09,0x0F,0x09,0x09,0x09,/*\"捏\",1962*/},{\n\n0x50,0xD1,0x5F,0xD5,0x55,0x15,0x55,0xD5,0x7F,0xC9,0x48,0x04,0x07,0x05,0x0F,0x02,\n0x00,0x04,0x07,0x05,0x0F,0x02,/*\"聶\",1963*/},{\n\n0x02,0xFA,0xAE,0xBB,0xE2,0x82,0xAA,0xBB,0xEE,0xBA,0x2A,0x02,0x02,0x02,0x0A,0x0A,\n0x0E,0x03,0x02,0x02,0x02,0x02,/*\"孽\",1964*/},{\n\n0x22,0x2A,0xFF,0x2A,0x22,0xE0,0x52,0x4E,0x62,0x22,0x1E,0x01,0x0F,0x09,0x0D,0x0B,\n0x0D,0x0B,0x0D,0x09,0x0F,0x01,/*\"齧\",1965*/},{\n\n0x2A,0xF9,0xAA,0x40,0xD1,0x5F,0xD5,0x55,0x7F,0xC9,0x40,0x05,0x07,0x02,0x04,0x07,\n0x05,0x0F,0x05,0x05,0x0F,0x02,/*\"鑷\",1966*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xFE,0xAA,0xAB,0xAA,0xFE,0x00,0x08,0x09,0x07,0x04,0x0A,\n0x06,0x02,0x0F,0x02,0x06,0x0A,/*\"鎳\",1967*/},{\n\n0x11,0x22,0x00,0x7F,0x49,0x49,0xC9,0x49,0x49,0x7F,0x00,0x04,0x02,0x08,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x08,/*\"涅\",1968*/},{\n\n0x10,0x08,0xFC,0x03,0x48,0x27,0x84,0xFC,0x04,0x24,0x4C,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"您\",1969*/},{\n\n0x88,0x68,0xFF,0x48,0x26,0x9A,0xA6,0xAB,0xB2,0x8A,0x36,0x00,0x00,0x0F,0x00,0x02,\n0x03,0x0A,0x0F,0x02,0x03,0x02,/*\"檸\",1970*/},{\n\n0x8A,0x44,0xFB,0x00,0x26,0x9A,0xA6,0xAB,0xB2,0x8A,0x36,0x08,0x08,0x07,0x00,0x02,\n0x03,0x0A,0x0F,0x02,0x03,0x02,/*\"獰\",1971*/},{\n\n0x04,0x08,0x40,0x37,0xEA,0x2D,0x90,0x15,0xF9,0x95,0xB3,0x02,0x01,0x08,0x05,0x03,\n0x0D,0x07,0x08,0x0F,0x08,0x08,/*\"凝\",1972*/},{\n\n0x96,0xEA,0xA6,0xAA,0xEE,0xAB,0xEA,0xAE,0xA2,0xEA,0x96,0x00,0x02,0x02,0x0A,0x0A,\n0x0E,0x02,0x02,0x02,0x02,0x00,/*\"寧\",1973*/},{\n\n0x88,0xFF,0x48,0xA6,0x9A,0xA6,0xAB,0xB2,0x8A,0xB6,0x00,0x08,0x0F,0x02,0x03,0x02,\n0x0B,0x0E,0x03,0x02,0x03,0x02,/*\"擰\",1974*/},{\n\n0x22,0x44,0x00,0xA6,0x9A,0xA6,0xAB,0xB2,0x8A,0xB6,0x00,0x04,0x02,0x02,0x03,0x02,\n0x0B,0x0E,0x03,0x02,0x03,0x02,/*\"濘\",1975*/},{\n\n0xA0,0x90,0x8E,0x88,0x88,0xFF,0x88,0x88,0x88,0x88,0x80,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"牛\",1976*/},{\n\n0x88,0xFF,0x48,0x00,0x42,0xC2,0x7E,0x42,0x42,0xFE,0x00,0x08,0x0F,0x00,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"扭\",1977*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x42,0xC2,0x7E,0x42,0xFE,0x00,0x08,0x09,0x07,0x05,0x00,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"鈕\",1978*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x42,0xC2,0x7E,0x42,0xFE,0x00,0x0E,0x00,0x06,0x00,0x06,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"紐\",1979*/},{\n\n0xFE,0x92,0xFE,0x00,0xBE,0xAA,0xBF,0xAA,0xBF,0xAA,0xBE,0x07,0x08,0x0F,0x08,0x07,\n0x02,0x0E,0x0A,0x06,0x0A,0x0A,/*\"膿\",1980*/},{\n\n0x10,0x21,0x02,0x00,0xBE,0xAA,0xBF,0xAA,0xBF,0xAA,0xBE,0x04,0x02,0x01,0x08,0x07,\n0x02,0x0E,0x0A,0x06,0x0A,0x0A,/*\"濃\",1981*/},{\n\n0x00,0xBE,0xAA,0xAA,0xBF,0xAA,0xBF,0xAA,0xAA,0xBE,0x80,0x08,0x07,0x02,0x0E,0x0A,\n0x02,0x06,0x0A,0x0E,0x0A,0x0A,/*\"農\",1982*/},{\n\n0x20,0x22,0x2A,0xAA,0x2A,0x3E,0x2A,0xAA,0x2A,0x22,0x20,0x01,0x09,0x05,0x03,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"弄\",1983*/},{\n\n0x88,0x78,0x0F,0xF8,0x02,0x3E,0xC2,0x02,0xC2,0x3E,0x00,0x08,0x05,0x02,0x05,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"奴\",1984*/},{\n\n0x84,0x5C,0x27,0x24,0xDC,0x00,0x82,0x5E,0x22,0x52,0x8E,0x09,0x09,0x05,0x03,0x01,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"努\",1985*/},{\n\n0x84,0x5C,0x27,0x24,0x5C,0x00,0x82,0x5E,0x22,0x52,0x8E,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"怒\",1986*/},{\n\n0x08,0x08,0x48,0xB8,0x8F,0x08,0x88,0x48,0x38,0x08,0x08,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x02,0x04,0x08,0x00,/*\"女\",1987*/},{\n\n0xFE,0x22,0xFE,0x00,0x56,0x5A,0xD6,0x7A,0x52,0x59,0x55,0x07,0x02,0x07,0x04,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"暖\",1988*/},{\n\n0x00,0xFC,0x04,0x94,0x94,0x9F,0xB5,0xAD,0xA5,0xB5,0x0C,0x08,0x07,0x02,0x0F,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0A,0x02,/*\"虐\",1989*/},{\n\n0x08,0x90,0xFE,0x02,0xFA,0x2A,0xAB,0xFE,0xAA,0xAA,0x1A,0x09,0x04,0x03,0x08,0x07,\n0x02,0x0F,0x0A,0x0A,0x0A,0x02,/*\"瘧\",1990*/},{\n\n0x88,0xFF,0x48,0x92,0xFE,0x92,0xFE,0x00,0xFE,0x32,0xCE,0x08,0x0F,0x08,0x04,0x03,\n0x08,0x0F,0x00,0x0F,0x02,0x01,/*\"挪\",1991*/},{\n\n0x78,0x00,0xFF,0x08,0x4C,0x55,0x45,0xDF,0x45,0x55,0x4C,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"懦\",1992*/},{\n\n0x24,0xA8,0xFF,0xA8,0x4C,0x55,0x45,0xDF,0x45,0x55,0x4C,0x01,0x00,0x0F,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"糯\",1993*/},{\n\n0x54,0x55,0x56,0x54,0x00,0xA4,0xEF,0xB4,0xA4,0xAF,0xA4,0x0F,0x05,0x05,0x0F,0x01,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"諾\",1994*/},{\n\n0xFC,0x04,0xFC,0x90,0x92,0xFE,0x51,0x10,0xFF,0x92,0x54,0x03,0x01,0x03,0x00,0x08,\n0x0F,0x04,0x02,0x03,0x04,0x0E,/*\"哦\",1995*/},{\n\n0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x10,0x0F,0xC4,0x1C,0x0F,0x0A,0x0B,0x08,0x0B,\n0x0A,0x0B,0x08,0x06,0x01,0x0E,/*\"歐\",1996*/},{\n\n0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x00,0xFE,0xAB,0xBE,0x0F,0x0A,0x0B,0x08,0x0B,\n0x0A,0x0B,0x00,0x06,0x08,0x0F,/*\"鷗\",1997*/},{\n\n0xFE,0x82,0xBA,0xAA,0xBA,0x82,0x10,0xCE,0x42,0xDE,0x10,0x0F,0x0B,0x0A,0x0B,0x0A,\n0x0B,0x08,0x05,0x02,0x05,0x08,/*\"毆\",1998*/},{\n\n0x02,0x52,0xFA,0x57,0x02,0xFA,0xAA,0xFF,0xAA,0xFA,0x02,0x05,0x03,0x0F,0x05,0x0E,\n0x02,0x0A,0x0F,0x0A,0x02,0x0E,/*\"藕\",1999*/},{\n\n0xFC,0x04,0xFC,0x00,0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x03,0x01,0x03,0x00,0x0F,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"嘔\",2000*/},{\n\n0x10,0xFC,0x03,0xC0,0x5F,0x55,0xFF,0x55,0x55,0x5F,0xC0,0x00,0x0F,0x00,0x0F,0x00,\n0x02,0x03,0x02,0x07,0x08,0x0F,/*\"偶\",2001*/},{\n\n0x22,0x44,0x00,0xFE,0x82,0xBA,0xAA,0x2A,0xAA,0xBA,0x82,0x04,0x02,0x00,0x0F,0x0B,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"漚\",2002*/},{\n\n0xFE,0x02,0xFE,0x88,0x88,0xFF,0x48,0xFC,0x46,0x45,0xFC,0x03,0x01,0x03,0x00,0x08,\n0x0F,0x00,0x0F,0x04,0x04,0x0F,/*\"啪\",2003*/},{\n\n0x9E,0x12,0xF2,0x5E,0x00,0xFE,0x00,0x00,0xFF,0x00,0x00,0x07,0x04,0x03,0x0A,0x06,\n0x01,0x00,0x00,0x01,0x06,0x08,/*\"趴\",2004*/},{\n\n0xFE,0x02,0xFE,0x02,0xFD,0x01,0xFE,0x22,0x3E,0x22,0xBE,0x0F,0x00,0x0F,0x00,0x03,\n0x04,0x09,0x0A,0x0A,0x0A,0x0B,/*\"爬\",2005*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x00,0xFC,0x46,0x45,0x44,0xFC,0x03,0x00,0x0F,0x02,0x03,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"帕\",2006*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0xFC,0x44,0x46,0x45,0x44,0xFC,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"怕\",2007*/},{\n\n0x11,0xD5,0x5F,0x55,0x51,0xC0,0x51,0x55,0x5F,0xD5,0x11,0x00,0x07,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x09,0x0C,/*\"琶\",2008*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xFC,0x44,0x46,0x45,0x44,0xFC,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"拍\",2009*/},{\n\n0x88,0x88,0xFF,0x48,0x24,0x24,0xFF,0x00,0xFF,0x24,0x24,0x00,0x08,0x0F,0x00,0x01,\n0x01,0x0F,0x00,0x0F,0x01,0x01,/*\"排\",2010*/},{\n\n0x00,0xFE,0x90,0x9F,0x10,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x08,0x07,0x00,0x0F,0x02,\n0x03,0x02,0x02,0x0F,0x02,0x02,/*\"牌\",2011*/},{\n\n0x48,0x24,0xF2,0x09,0x24,0x24,0xFF,0x00,0xFF,0x24,0x24,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x0F,0x00,0x0F,0x01,0x01,/*\"徘\",2012*/},{\n\n0x22,0x44,0x92,0x92,0xFF,0x91,0x00,0x29,0xFF,0x29,0x29,0x04,0x02,0x08,0x04,0x03,\n0x00,0x00,0x01,0x0F,0x01,0x01,/*\"湃\",2013*/},{\n\n0x10,0x22,0x04,0x00,0xFE,0x02,0xFA,0x0A,0xF9,0x45,0x20,0x04,0x02,0x01,0x08,0x07,\n0x00,0x0F,0x04,0x01,0x06,0x08,/*\"派\",2014*/},{\n\n0x2A,0xA6,0x7F,0xAA,0xB5,0xAA,0xB5,0xAA,0x7F,0xA6,0x2A,0x01,0x00,0x02,0x02,0x0A,\n0x0F,0x02,0x02,0x02,0x00,0x01,/*\"攀\",2015*/},{\n\n0x22,0x44,0x90,0xD6,0xBA,0x92,0xBE,0x91,0xB9,0xD5,0x90,0x04,0x02,0x00,0x0F,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0F,0x00,/*\"潘\",2016*/},{\n\n0x48,0x3E,0x0B,0x2E,0x4A,0x7E,0x04,0x5B,0x29,0x5B,0x44,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盤\",2017*/},{\n\n0xC8,0xBE,0x8B,0xAE,0xCA,0xFE,0x84,0xDB,0xA9,0xDB,0x84,0x08,0x04,0x0E,0x0B,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"磐\",2018*/},{\n\n0xFE,0x92,0x92,0xFE,0x10,0x2C,0xE3,0x20,0x23,0xEC,0x10,0x0F,0x04,0x04,0x07,0x08,\n0x06,0x01,0x08,0x08,0x07,0x00,/*\"盼\",2019*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x80,0x92,0x94,0xFF,0x94,0x92,0x07,0x02,0x03,0x02,0x07,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"畔\",2020*/},{\n\n0x80,0x92,0x94,0xFF,0x94,0x92,0x80,0xFC,0x00,0x00,0xFF,0x00,0x08,0x06,0x01,0x00,\n0x00,0x00,0x01,0x08,0x08,0x0F,/*\"判\",2021*/},{\n\n0x92,0x94,0xFF,0x94,0x82,0xFC,0x24,0xE4,0x24,0x22,0xE2,0x08,0x04,0x03,0x08,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"叛\",2022*/},{\n\n0x00,0x00,0xFE,0x12,0x12,0x12,0x12,0xF1,0x11,0x10,0x00,0x01,0x01,0x01,0x01,0x01,\n0x01,0x01,0x03,0x05,0x09,0x01,/*\"乓\",2023*/},{\n\n0x00,0xFE,0x2A,0xFA,0xAE,0xBA,0xEB,0x22,0xBE,0xAA,0xEA,0x04,0x03,0x00,0x0F,0x02,\n0x0A,0x0F,0x00,0x07,0x0A,0x0A,/*\"龐\",2024*/},{\n\n0xB0,0x92,0x96,0x9A,0xB2,0xD3,0x92,0x9A,0x96,0x92,0xB0,0x08,0x08,0x04,0x03,0x02,\n0x02,0x02,0x0A,0x0A,0x06,0x00,/*\"旁\",2025*/},{\n\n0x44,0x54,0xFF,0x54,0x00,0xB2,0x96,0xBB,0xDA,0x96,0xB2,0x02,0x01,0x0F,0x01,0x00,\n0x08,0x07,0x02,0x0A,0x0A,0x06,/*\"耪\",2026*/},{\n\n0x00,0xFF,0x49,0xFF,0x82,0x94,0x90,0xFF,0x90,0x94,0x82,0x08,0x07,0x08,0x0F,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"胖\",2027*/},{\n\n0x88,0xFF,0x48,0x10,0xFF,0x10,0xF0,0x14,0xFF,0x04,0xFC,0x08,0x0F,0x00,0x08,0x07,\n0x00,0x07,0x09,0x08,0x09,0x0D,/*\"拋\",2028*/},{\n\n0xFC,0x04,0xFC,0x08,0xF7,0x94,0x94,0xF4,0x04,0xFC,0x00,0x03,0x01,0x03,0x00,0x07,\n0x08,0x08,0x08,0x09,0x09,0x0E,/*\"咆\",2029*/},{\n\n0x10,0xFC,0x97,0x94,0xF4,0x04,0xFC,0x00,0xFC,0x00,0xFF,0x00,0x07,0x08,0x08,0x08,\n0x09,0x0D,0x00,0x01,0x08,0x0F,/*\"刨\",2030*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0xF4,0x97,0x94,0xF4,0x04,0xFC,0x08,0x06,0x01,0x06,0x00,\n0x07,0x08,0x08,0x08,0x09,0x0D,/*\"炮\",2031*/},{\n\n0x84,0x45,0xF6,0xAC,0x08,0xF4,0x97,0x94,0xF4,0x04,0xFC,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x08,0x08,0x08,0x09,0x0D,/*\"袍\",2032*/},{\n\n0x9E,0x12,0xF2,0x9E,0x08,0xF4,0x97,0x94,0xF4,0x04,0xFC,0x0F,0x08,0x07,0x04,0x00,\n0x07,0x08,0x08,0x08,0x09,0x0D,/*\"跑\",2033*/},{\n\n0x22,0x44,0x10,0x08,0xF7,0x94,0x94,0xF4,0x04,0xFC,0x00,0x04,0x02,0x01,0x00,0x07,\n0x08,0x08,0x08,0x09,0x09,0x0E,/*\"泡\",2034*/},{\n\n0xFE,0x02,0xFE,0x00,0x82,0x42,0x22,0xFA,0x06,0x22,0xC2,0x03,0x01,0x03,0x00,0x08,\n0x08,0x08,0x0B,0x08,0x08,0x08,/*\"呸\",2035*/},{\n\n0x00,0xFE,0x92,0xFE,0x80,0x42,0x22,0xFA,0x06,0x22,0xC2,0x08,0x07,0x08,0x0F,0x00,\n0x08,0x08,0x0B,0x08,0x08,0x08,/*\"胚\",2036*/},{\n\n0x10,0xFF,0x10,0x20,0xAA,0xB2,0xA2,0xA3,0xB2,0xAA,0x20,0x04,0x07,0x02,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"培\",2037*/},{\n\n0xA2,0xAA,0xAA,0xFF,0x80,0xC0,0x80,0xFF,0xAA,0xAA,0xA2,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"裴\",2038*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x20,0xAA,0xB2,0xA3,0xB2,0xAA,0x20,0x09,0x05,0x05,0x09,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"賠\",2039*/},{\n\n0xFE,0x02,0x32,0xCE,0x20,0xAA,0xB2,0xA3,0xB2,0xAA,0x20,0x0F,0x02,0x02,0x01,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"陪\",2040*/},{\n\n0xFA,0x4A,0x3E,0x0A,0x3E,0x4A,0xFA,0x00,0xE2,0x22,0x3E,0x0F,0x05,0x05,0x05,0x05,\n0x05,0x0F,0x00,0x07,0x08,0x0E,/*\"配\",2041*/},{\n\n0x10,0xFC,0x03,0xFE,0x2A,0xFA,0x2A,0xEA,0x02,0xFE,0x00,0x00,0x0F,0x08,0x07,0x00,\n0x0F,0x02,0x03,0x00,0x07,0x0C,/*\"佩\",2042*/},{\n\n0x11,0x22,0x04,0xE4,0x24,0x24,0xFF,0x24,0x24,0xE4,0x04,0x04,0x02,0x00,0x07,0x00,\n0x00,0x0F,0x00,0x04,0x07,0x00,/*\"沛\",2043*/},{\n\n0xFC,0x04,0xFC,0x08,0xEA,0xBE,0xAA,0xAF,0xAA,0xBE,0xEA,0x03,0x01,0x03,0x00,0x0B,\n0x06,0x02,0x02,0x02,0x06,0x0B,/*\"噴\",2044*/},{\n\n0x08,0x44,0x4A,0x29,0x18,0x08,0x48,0x49,0x3A,0x04,0x08,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盆\",2045*/},{\n\n0x42,0xF2,0x2E,0xE2,0x88,0xB2,0x82,0xFE,0x82,0xA2,0x98,0x00,0x0F,0x04,0x0F,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"砰\",2046*/},{\n\n0x88,0x88,0xFF,0x48,0x88,0xB2,0x82,0xFE,0x82,0xA2,0x98,0x00,0x08,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"抨\",2047*/},{\n\n0x02,0x82,0xBA,0xAA,0xAA,0xAB,0xAA,0xAA,0xBA,0x02,0x02,0x08,0x04,0x00,0x04,0x08,\n0x04,0x06,0x09,0x00,0x04,0x08,/*\"烹\",2048*/},{\n\n0x22,0x44,0x02,0xEA,0xAA,0xAF,0xAA,0xEA,0x44,0x22,0x11,0x04,0x02,0x08,0x09,0x0A,\n0x04,0x06,0x05,0x08,0x04,0x02,/*\"澎\",2049*/},{\n\n0x02,0xEA,0xAA,0xAF,0xAA,0xEA,0x00,0x88,0x44,0x23,0x18,0x08,0x09,0x0A,0x04,0x06,\n0x05,0x08,0x08,0x04,0x02,0x01,/*\"彭\",2050*/},{\n\n0x26,0xEA,0x42,0x57,0xDA,0xAE,0xEA,0xAF,0xDA,0x42,0x42,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"蓬\",2051*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x92,0xFE,0x00,0xFE,0x92,0xFE,0x00,0x00,0x0F,0x08,0x07,\n0x08,0x0F,0x08,0x07,0x08,0x0F,/*\"棚\",2052*/},{\n\n0x42,0xF2,0x2E,0x22,0xFF,0x49,0xFF,0x00,0xFF,0x91,0xFF,0x00,0x07,0x02,0x0A,0x07,\n0x08,0x0F,0x04,0x03,0x08,0x0F,/*\"硼\",2053*/},{\n\n0x24,0xEB,0x42,0x56,0xDA,0xAC,0xEB,0xAA,0xDE,0x42,0x42,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"篷\",2054*/},{\n\n0x00,0xFF,0x49,0xFF,0x02,0xEA,0xAF,0xEA,0x02,0x88,0x66,0x08,0x07,0x08,0x0F,0x04,\n0x06,0x04,0x06,0x04,0x08,0x06,/*\"膨\",2055*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0x00,0xFE,0x92,0x92,0xFE,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x08,0x07,0x00,0x08,0x0F,/*\"朋\",2056*/},{\n\n0xFE,0x92,0xFE,0x00,0xFE,0x92,0xFE,0x00,0xFE,0xAB,0xBE,0x07,0x08,0x0F,0x08,0x07,\n0x08,0x0F,0x00,0x06,0x08,0x0F,/*\"鵬\",2057*/},{\n\n0x88,0x88,0xFF,0x48,0xA2,0x6A,0x3A,0xAF,0x2A,0x6A,0xA2,0x00,0x08,0x0F,0x00,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"捧\",2058*/},{\n\n0x42,0xF2,0x2E,0xE2,0x48,0x89,0xFA,0x08,0xFA,0x89,0x48,0x00,0x07,0x02,0x07,0x08,\n0x08,0x0F,0x08,0x0F,0x08,0x08,/*\"碰\",2059*/},{\n\n0x10,0x10,0xFF,0x10,0x82,0x42,0x22,0xFA,0x06,0x22,0xC2,0x04,0x04,0x03,0x02,0x08,\n0x08,0x08,0x0B,0x08,0x08,0x08,/*\"坯\",2060*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFF,0x10,0x10,0xFF,0x10,0x0C,0x00,0x0F,0x04,0x0F,0x00,\n0x0F,0x04,0x02,0x07,0x08,0x0E,/*\"砒\",2061*/},{\n\n0x0C,0xE5,0xA5,0xAD,0xE5,0x0F,0x25,0x6D,0xB5,0x65,0x2C,0x04,0x03,0x0E,0x0A,0x0E,\n0x00,0x01,0x05,0x0F,0x05,0x01,/*\"霹\",2062*/},{\n\n0x88,0xFF,0x48,0x00,0xFF,0x10,0x10,0xFF,0x20,0x10,0x0C,0x08,0x0F,0x00,0x00,0x0F,\n0x04,0x02,0x07,0x08,0x08,0x0E,/*\"批\",2063*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xFC,0x24,0xE4,0x3F,0xE4,0x0C,0x00,0x08,0x0F,0x08,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"披\",2064*/},{\n\n0x20,0x1F,0x75,0x55,0x77,0x00,0x0A,0x2E,0x7B,0x2E,0x0A,0x00,0x09,0x09,0x05,0x03,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"劈\",2065*/},{\n\n0x11,0xD5,0x1F,0x15,0x11,0x00,0xD1,0x15,0x9F,0x55,0x11,0x00,0x0F,0x09,0x05,0x05,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"琵\",2066*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x00,0xFF,0x10,0xFF,0x10,0x0C,0x07,0x02,0x03,0x02,0x07,\n0x00,0x0F,0x04,0x07,0x08,0x0E,/*\"毗\",2067*/},{\n\n0xFC,0x04,0xFC,0x00,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x00,0x03,0x01,0x03,0x02,0x03,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"啤\",2068*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x08,0x07,0x08,0x0F,0x02,\n0x03,0x02,0x02,0x0F,0x02,0x02,/*\"脾\",2069*/},{\n\n0x08,0x90,0xFC,0x04,0xF4,0x95,0x96,0xFC,0x94,0x94,0x34,0x09,0x04,0x0B,0x04,0x03,\n0x08,0x0B,0x04,0x04,0x0B,0x08,/*\"疲\",2070*/},{\n\n0x00,0xFC,0x24,0x64,0xA4,0x24,0x3F,0x24,0xA4,0x64,0x0C,0x08,0x07,0x08,0x08,0x04,\n0x05,0x02,0x05,0x04,0x08,0x08,/*\"皮\",2071*/},{\n\n0x00,0xFE,0x02,0x82,0x7E,0x02,0x02,0xFE,0x02,0x02,0xC2,0x00,0x0F,0x0A,0x09,0x08,\n0x08,0x08,0x08,0x09,0x09,0x09,/*\"匹\",2072*/},{\n\n0x08,0x90,0xFC,0x04,0x94,0x95,0x56,0xF4,0x14,0x54,0x94,0x09,0x04,0x03,0x00,0x0E,\n0x0A,0x0A,0x0B,0x0A,0x0A,0x0E,/*\"痞\",2073*/},{\n\n0x10,0xFC,0x03,0xFE,0x92,0x9E,0x40,0x55,0xE6,0x54,0x40,0x00,0x0F,0x01,0x0F,0x04,\n0x0F,0x00,0x02,0x0F,0x02,0x00,/*\"僻\",2074*/},{\n\n0x00,0xFF,0x05,0xF5,0x45,0x45,0x05,0xF5,0x05,0x87,0x60,0x08,0x07,0x00,0x0F,0x08,\n0x04,0x00,0x07,0x09,0x08,0x0E,/*\"屁\",2075*/},{\n\n0xA0,0x9F,0xF5,0xD5,0xF7,0x80,0xCA,0xAE,0xFB,0xAE,0x8A,0x00,0x02,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x02,0x00,/*\"譬\",2076*/},{\n\n0x04,0xFB,0xAA,0xAE,0xAA,0xAC,0xAB,0xAA,0xAE,0xAA,0xBA,0x02,0x01,0x0F,0x02,0x02,\n0x07,0x02,0x07,0x02,0x0A,0x0F,/*\"篇\",2077*/},{\n\n0x10,0xFC,0x03,0x80,0xFE,0x2A,0xEA,0x2B,0xEA,0x2A,0xEE,0x00,0x0F,0x01,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"偏\",2078*/},{\n\n0x00,0x00,0xFE,0x90,0x90,0x90,0x90,0x9F,0x90,0x10,0x10,0x08,0x06,0x01,0x00,0x00,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"片\",2079*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x80,0xFE,0x2A,0xEB,0x2A,0xEE,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x0F,0x01,0x07,0x09,0x0F,/*\"騙\",2080*/},{\n\n0x1D,0x55,0x5F,0x55,0x1D,0x00,0xFE,0x52,0xF2,0x4A,0xFE,0x05,0x09,0x0F,0x01,0x05,\n0x08,0x07,0x05,0x07,0x0D,0x03,/*\"飄\",2081*/},{\n\n0x11,0x22,0x01,0x5D,0x55,0x5F,0x55,0x5F,0x55,0x5D,0x01,0x04,0x02,0x09,0x05,0x01,\n0x09,0x0F,0x01,0x01,0x05,0x09,/*\"漂\",2082*/},{\n\n0x1D,0x55,0x5F,0x55,0x1D,0x00,0xFE,0x02,0xFE,0x02,0xFD,0x05,0x09,0x0F,0x01,0x05,\n0x08,0x07,0x00,0x0F,0x0A,0x0C,/*\"瓢\",2083*/},{\n\n0x01,0x5D,0x55,0x55,0x5F,0x55,0x5F,0x55,0x55,0x5D,0x01,0x01,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x01,/*\"票\",2084*/},{\n\n0x88,0xFF,0x48,0xF2,0x94,0xFF,0x54,0xFA,0x0F,0xF8,0x08,0x08,0x0F,0x00,0x0F,0x00,\n0x07,0x08,0x05,0x02,0x05,0x08,/*\"撇\",2085*/},{\n\n0x7D,0x26,0x14,0x7F,0x16,0x3D,0x44,0x2B,0x12,0x2E,0x42,0x00,0x0F,0x09,0x0B,0x0D,\n0x09,0x0B,0x0D,0x09,0x0F,0x00,/*\"瞥\",2086*/},{\n\n0x88,0x88,0xFF,0x48,0x80,0x89,0xFA,0x88,0x88,0xFA,0x89,0x00,0x08,0x0F,0x00,0x00,\n0x08,0x07,0x00,0x00,0x0F,0x00,/*\"拼\",2087*/},{\n\n0x10,0xDE,0x10,0xFF,0x12,0x92,0xF9,0xAD,0xAB,0xA9,0xF9,0x09,0x08,0x04,0x02,0x01,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頻\",2088*/},{\n\n0x04,0xF2,0x5B,0x56,0x52,0x52,0x5A,0x5A,0x57,0xF2,0x04,0x00,0x07,0x0D,0x05,0x05,\n0x05,0x05,0x05,0x0D,0x07,0x00,/*\"貧\",2089*/},{\n\n0xC0,0x40,0x5F,0x51,0xD1,0x11,0xD1,0x51,0x5F,0x40,0xC0,0x0F,0x04,0x04,0x04,0x0F,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"品\",2090*/},{\n\n0x02,0xFE,0x52,0xFE,0x02,0xBE,0xAA,0xBF,0xAA,0xAA,0xBE,0x02,0x03,0x02,0x0F,0x01,\n0x00,0x03,0x02,0x0A,0x0A,0x06,/*\"聘\",2091*/},{\n\n0x00,0x00,0xFE,0x12,0x12,0x12,0x12,0xF1,0x11,0x10,0x00,0x01,0x09,0x05,0x03,0x01,\n0x01,0x01,0x01,0x01,0x01,0x01,/*\"乒\",2092*/},{\n\n0x10,0x10,0xFF,0x10,0x88,0xB2,0x82,0xFE,0x82,0xA2,0x98,0x04,0x04,0x03,0x02,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"坪\",2093*/},{\n\n0x42,0x72,0x47,0xFA,0x52,0x52,0xEA,0xAA,0xBF,0xAA,0xEA,0x0A,0x09,0x04,0x05,0x02,\n0x01,0x0B,0x06,0x02,0x06,0x0B,/*\"蘋\",2094*/},{\n\n0x4A,0x92,0x02,0x57,0x92,0x12,0xF2,0x17,0x92,0x52,0x02,0x08,0x04,0x01,0x01,0x01,\n0x01,0x0F,0x01,0x01,0x01,0x01,/*\"萍\",2095*/},{\n\n0x80,0x8A,0xB2,0x82,0x82,0xFE,0x82,0x82,0xA2,0x9A,0x80,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"平\",2096*/},{\n\n0x42,0x24,0x80,0x7F,0xD5,0x55,0xD5,0x7F,0xD5,0x55,0xC1,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x03,0x0D,/*\"憑\",2097*/},{\n\n0x89,0xFA,0x88,0xFA,0x89,0xC2,0xBE,0x12,0xF2,0x02,0x00,0x08,0x07,0x00,0x0F,0x00,\n0x0F,0x04,0x01,0x07,0x08,0x0E,/*\"瓶\",2098*/},{\n\n0x54,0x55,0x56,0x54,0x88,0xB2,0x82,0xFE,0x82,0xA2,0x98,0x0F,0x05,0x05,0x0F,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"評\",2099*/},{\n\n0x00,0xFF,0x05,0x25,0x2D,0xF5,0x25,0x25,0xF5,0x2D,0x27,0x08,0x07,0x01,0x09,0x05,\n0x03,0x01,0x01,0x0F,0x01,0x01,/*\"屏\",2100*/},{\n\n0x08,0x08,0xFF,0x08,0xFC,0x24,0xE4,0x3F,0x24,0xE4,0x0C,0x02,0x02,0x01,0x09,0x07,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"坡\",2101*/},{\n\n0x22,0x44,0x20,0xD5,0x59,0x77,0x80,0x73,0x16,0x79,0x54,0x04,0x02,0x00,0x09,0x09,\n0x07,0x00,0x0B,0x05,0x0B,0x00,/*\"潑\",2102*/},{\n\n0x00,0xFC,0x24,0xBF,0x24,0xEC,0x00,0xFA,0xAE,0xAA,0xFA,0x04,0x0B,0x04,0x02,0x01,\n0x06,0x00,0x0B,0x06,0x06,0x0B,/*\"頗\",2103*/},{\n\n0x44,0x29,0x02,0x40,0xBE,0x4A,0x5A,0x2F,0x2A,0x5A,0x46,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"婆\",2104*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFC,0x24,0xE4,0x3F,0xE4,0x0C,0x00,0x07,0x02,0x0B,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"破\",2105*/},{\n\n0xFC,0x26,0xFD,0x00,0x7C,0x54,0xF6,0x5D,0xD4,0x7C,0x00,0x07,0x02,0x03,0x08,0x04,\n0x03,0x00,0x07,0x0A,0x0B,0x0C,/*\"魄\",2106*/},{\n\n0x10,0x11,0xF2,0x00,0xFC,0x24,0x26,0x25,0x24,0x24,0xFC,0x08,0x04,0x03,0x04,0x09,\n0x09,0x09,0x09,0x09,0x09,0x09,/*\"迫\",2107*/},{\n\n0x24,0xA8,0xFF,0xA8,0x24,0x00,0xFC,0x46,0x45,0x44,0xFC,0x01,0x00,0x0F,0x00,0x01,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"粕\",2108*/},{\n\n0x20,0xAA,0xB2,0xA2,0xA3,0xB2,0xAA,0x20,0xFC,0x00,0xFF,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x0F,0x00,0x01,0x08,0x0F,/*\"剖\",2109*/},{\n\n0x88,0x88,0xFF,0x48,0x25,0xAC,0xB7,0xE4,0xB7,0xAC,0x25,0x00,0x08,0x0F,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"撲\",2110*/},{\n\n0x4A,0xF9,0x4A,0x00,0xF4,0x54,0x54,0xFF,0x54,0x55,0xF6,0x0A,0x0F,0x05,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"鋪\",2111*/},{\n\n0x10,0xFC,0x03,0x00,0x25,0xAC,0xB7,0xE4,0xB7,0xAC,0x25,0x00,0x0F,0x00,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"僕\",2112*/},{\n\n0x0A,0xEA,0xAA,0xAF,0xAA,0xFE,0xAA,0xAF,0xAA,0xEE,0x0A,0x00,0x0F,0x02,0x02,0x02,\n0x07,0x02,0x02,0x0A,0x0F,0x00,/*\"莆\",2113*/},{\n\n0x32,0xEE,0xAA,0xAF,0xFA,0xAA,0xBA,0xEF,0x2A,0x0A,0xFA,0x00,0x0F,0x02,0x02,0x07,\n0x02,0x0A,0x0F,0x00,0x08,0x0F,/*\"葡\",2114*/},{\n\n0x42,0x52,0x72,0x57,0x52,0x5A,0x52,0x57,0x72,0x52,0x42,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"菩\",2115*/},{\n\n0x4A,0x92,0x0A,0xEF,0xAA,0xAA,0xFE,0xAF,0xAA,0xEE,0x0A,0x04,0x02,0x00,0x0F,0x02,\n0x02,0x07,0x02,0x0A,0x0F,0x00,/*\"蒲\",2116*/},{\n\n0x10,0xFF,0x10,0x00,0xF4,0x54,0x54,0xFF,0x54,0x55,0xF6,0x04,0x07,0x02,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"埔\",2117*/},{\n\n0x88,0x68,0xFF,0x48,0x25,0xAC,0xB7,0xE4,0xB7,0xAC,0x25,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"樸\",2118*/},{\n\n0xFF,0x05,0xF5,0x55,0x55,0xFF,0x55,0x55,0xF7,0x05,0xFF,0x0F,0x08,0x0F,0x09,0x09,\n0x0B,0x09,0x0D,0x0F,0x08,0x0F,/*\"圃\",2119*/},{\n\n0x20,0x22,0xAA,0xB3,0xBE,0xA2,0xA2,0xBE,0xB3,0xAA,0x22,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"普\",2120*/},{\n\n0x11,0x22,0x04,0xF4,0x54,0x54,0xFF,0x54,0x55,0xF6,0x04,0x04,0x02,0x01,0x0F,0x01,\n0x01,0x07,0x01,0x09,0x0F,0x00,/*\"浦\",2121*/},{\n\n0x54,0x55,0x56,0x54,0x2A,0xA3,0xBE,0xA2,0xBE,0xA3,0x2A,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"譜\",2122*/},{\n\n0xFE,0x22,0xFE,0x00,0x5F,0xF5,0x55,0x55,0xF5,0x5F,0x00,0x07,0x02,0x07,0x05,0x0B,\n0x05,0x09,0x0F,0x05,0x0B,0x05,/*\"曝\",2123*/},{\n\n0x10,0x21,0x02,0x00,0x5F,0xF5,0x55,0x55,0xF5,0x5F,0x00,0x04,0x02,0x01,0x05,0x0B,\n0x05,0x09,0x0F,0x05,0x0B,0x05,/*\"瀑\",2124*/},{\n\n0x04,0xFF,0x54,0x54,0xFF,0x04,0x00,0xFE,0x92,0x92,0xFE,0x09,0x05,0x01,0x01,0x05,\n0x09,0x08,0x07,0x00,0x08,0x0F,/*\"期\",2125*/},{\n\n0x04,0xFF,0x54,0x54,0xFF,0x04,0x10,0x0F,0xC4,0x14,0x0C,0x09,0x05,0x01,0x01,0x05,\n0x09,0x08,0x06,0x01,0x06,0x08,/*\"欺\",2126*/},{\n\n0x88,0x68,0xFF,0x48,0x22,0x2A,0xAA,0x7F,0x2A,0x7A,0x22,0x00,0x00,0x0F,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"棲\",2127*/},{\n\n0x00,0xFC,0x44,0x44,0xFC,0x54,0x54,0x04,0xFF,0x04,0xE5,0x08,0x07,0x02,0x09,0x0F,\n0x01,0x0A,0x04,0x03,0x05,0x0E,/*\"戚\",2128*/},{\n\n0x22,0x2A,0x2A,0x2A,0xAA,0x7F,0x2A,0x2A,0x2A,0x7A,0x22,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"妻\",2129*/},{\n\n0x20,0x20,0x20,0x20,0xFF,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x07,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"七\",2130*/},{\n\n0x78,0x00,0xFF,0x08,0x22,0x2A,0xAA,0x7F,0x2A,0x7A,0x22,0x00,0x00,0x0F,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"悽\",2131*/},{\n\n0x22,0x44,0x00,0x4A,0xA6,0x12,0xCF,0x12,0xA6,0x4A,0x40,0x04,0x02,0x00,0x04,0x02,\n0x09,0x0F,0x01,0x02,0x04,0x00,/*\"漆\",2132*/},{\n\n0x84,0xC9,0xA2,0x88,0x88,0xC8,0x9F,0xA4,0xA4,0xA4,0xB4,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"柒\",2133*/},{\n\n0x22,0x44,0x10,0xFF,0x10,0x92,0x02,0xFE,0x02,0x02,0xFE,0x04,0x02,0x00,0x03,0x09,\n0x04,0x03,0x00,0x08,0x08,0x07,/*\"沏\",2134*/},{\n\n0x04,0x04,0xFF,0x54,0x54,0x54,0x54,0x54,0xFF,0x04,0x04,0x01,0x09,0x05,0x01,0x01,\n0x01,0x01,0x01,0x05,0x09,0x01,/*\"其\",2135*/},{\n\n0x88,0x68,0xFF,0x48,0x04,0xFF,0x54,0x54,0x54,0xFF,0x04,0x00,0x00,0x0F,0x00,0x09,\n0x05,0x01,0x01,0x01,0x05,0x09,/*\"棋\",2136*/},{\n\n0x10,0xD2,0x5A,0x56,0x53,0xD2,0x16,0x1A,0xF2,0x12,0x10,0x00,0x07,0x02,0x02,0x02,\n0x03,0x08,0x08,0x0F,0x00,0x00,/*\"奇\",2137*/},{\n\n0x00,0xF8,0x00,0xFF,0x08,0x20,0xE4,0x24,0x3F,0x24,0xE4,0x04,0x07,0x04,0x03,0x02,\n0x08,0x08,0x05,0x02,0x05,0x08,/*\"歧\",2138*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x00,0x24,0x24,0xBF,0x24,0x24,0x07,0x02,0x03,0x02,0x07,\n0x08,0x09,0x09,0x0F,0x09,0x09,/*\"畦\",2139*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x10,0xDA,0x56,0xD3,0x16,0xFA,0x07,0x04,0x03,0x02,0x07,\n0x00,0x07,0x02,0x03,0x08,0x0F,/*\"崎\",2140*/},{\n\n0xFE,0x92,0xFE,0x28,0xDA,0x7A,0x06,0x7B,0x06,0x7A,0xD6,0x07,0x08,0x0F,0x08,0x07,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"臍\",2141*/},{\n\n0x2A,0xDA,0xAA,0xBA,0x86,0xBB,0x86,0xBA,0xAA,0xD6,0x22,0x08,0x07,0x02,0x02,0x02,\n0x02,0x02,0x02,0x02,0x0F,0x00,/*\"齊\",2142*/},{\n\n0x04,0xFD,0x26,0xE4,0x04,0x0B,0xFE,0xAA,0xAA,0xFE,0x0A,0x08,0x07,0x08,0x0F,0x00,\n0x0A,0x07,0x02,0x02,0x07,0x0A,/*\"旗\",2143*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0x00,0xFE,0x12,0x12,0xF1,0x11,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x00,0x0F,0x00,/*\"祈\",2144*/},{\n\n0x84,0x45,0xF6,0x4C,0x80,0x00,0xFE,0x02,0x12,0x2A,0xC6,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x0F,0x00,0x02,0x02,0x01,/*\"祁\",2145*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x10,0xDA,0x56,0xD3,0x16,0xFA,0x10,0x04,0x0A,0x08,0x07,0x00,\n0x07,0x02,0x03,0x08,0x0F,0x00,/*\"騎\",2146*/},{\n\n0x20,0xA4,0x24,0xFF,0x24,0x00,0xF2,0x12,0x12,0x1E,0x80,0x08,0x07,0x04,0x0F,0x09,\n0x08,0x09,0x0A,0x0A,0x0A,0x0B,/*\"起\",2147*/},{\n\n0x10,0xD6,0x54,0x54,0x54,0x57,0x54,0x54,0x54,0xD6,0x10,0x08,0x09,0x0B,0x0D,0x09,\n0x09,0x09,0x0D,0x0B,0x09,0x08,/*\"豈\",2148*/},{\n\n0x20,0x18,0x27,0x24,0xA4,0xA4,0x64,0x64,0x24,0x04,0x00,0x00,0x00,0x06,0x09,0x08,\n0x08,0x08,0x08,0x08,0x0E,0x00,/*\"乞\",2149*/},{\n\n0x10,0x10,0xC8,0x04,0x02,0xF1,0x82,0x84,0x88,0x90,0x10,0x08,0x08,0x0F,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"企\",2150*/},{\n\n0x40,0xBE,0x8A,0x8B,0x8A,0x8E,0xC4,0xAB,0x92,0xAE,0x42,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"啓\",2151*/},{\n\n0x22,0x2A,0x7F,0x2A,0x22,0xC0,0x22,0x1E,0x42,0x42,0x3E,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"契\",2152*/},{\n\n0x42,0xF2,0x2E,0xE2,0x10,0xFF,0x88,0x02,0xFE,0x02,0xFE,0x00,0x07,0x02,0x07,0x00,\n0x09,0x04,0x03,0x08,0x08,0x07,/*\"砌\",2153*/},{\n\n0x20,0x27,0xA5,0xA5,0x67,0x38,0x67,0xA5,0xAD,0x37,0x20,0x01,0x0F,0x0A,0x0A,0x0E,\n0x00,0x0E,0x0A,0x0A,0x0F,0x01,/*\"器\",2154*/},{\n\n0x48,0xA4,0x2B,0xEA,0x2A,0xAA,0x6A,0x2A,0xEA,0x0A,0x02,0x09,0x05,0x03,0x0F,0x03,\n0x05,0x09,0x00,0x03,0x04,0x0E,/*\"氣\",2155*/},{\n\n0x10,0x11,0xF2,0x08,0x04,0x17,0x94,0x54,0x34,0x14,0x84,0x08,0x04,0x03,0x04,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0A,0x0B,/*\"迄\",2156*/},{\n\n0x22,0x2A,0xFE,0xAA,0xAA,0xFB,0xAA,0xAA,0xFE,0x2A,0x22,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"棄\",2157*/},{\n\n0x22,0x44,0x08,0x24,0x2B,0x2A,0x2A,0x2A,0xEA,0x02,0x00,0x04,0x02,0x00,0x00,0x00,\n0x00,0x00,0x00,0x03,0x04,0x0F,/*\"汽\",2158*/},{\n\n0x22,0x44,0x00,0x08,0x48,0x88,0x09,0x0A,0x08,0xE8,0x08,0x04,0x02,0x09,0x08,0x08,\n0x0B,0x08,0x0C,0x0B,0x08,0x08,/*\"泣\",2159*/},{\n\n0x54,0x55,0x56,0x54,0x10,0x28,0x27,0xA4,0x64,0x24,0x04,0x0F,0x05,0x05,0x0F,0x00,\n0x06,0x09,0x08,0x08,0x08,0x0E,/*\"訖\",2160*/},{\n\n0x88,0xFF,0x48,0x08,0xE4,0xA3,0x92,0x02,0xAA,0xA6,0xE0,0x08,0x0F,0x00,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"掐\",2161*/},{\n\n0x78,0x00,0xFF,0x04,0x10,0xA8,0xA4,0xA3,0xA4,0xA8,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"恰\",2162*/},{\n\n0x22,0x44,0x20,0x90,0xA8,0xA4,0xA3,0xA4,0xA8,0x90,0x20,0x04,0x02,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"洽\",2163*/},{\n\n0x60,0x22,0xAA,0x2E,0x2A,0xBB,0x2A,0x26,0x22,0x22,0x60,0x04,0x06,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x05,0x04,/*\"牽\",2164*/},{\n\n0x88,0x88,0xFF,0x48,0x20,0x22,0x22,0xFE,0x21,0x21,0x20,0x00,0x08,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"扦\",2165*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0x22,0x22,0xFE,0x21,0x21,0x08,0x09,0x07,0x05,0x04,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"釺\",2166*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x10,0xCE,0x42,0x42,0xCE,0x10,0x08,0x09,0x07,0x05,0x04,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"鉛\",2167*/},{\n\n0x40,0x44,0x44,0x44,0x44,0xFC,0x42,0x42,0x42,0x42,0x40,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"千\",2168*/},{\n\n0x11,0xF2,0x41,0xDD,0x55,0xFF,0x55,0xDF,0x55,0xDD,0x41,0x08,0x07,0x09,0x08,0x08,\n0x0B,0x0D,0x0D,0x0E,0x08,0x09,/*\"遷\",2169*/},{\n\n0xB4,0xAB,0xF2,0x26,0xF2,0xA8,0xB4,0xFB,0x22,0xB6,0x22,0x0A,0x0A,0x0F,0x08,0x0F,\n0x0A,0x0A,0x04,0x03,0x04,0x0E,/*\"籤\",2170*/},{\n\n0x20,0x10,0xFC,0x03,0x20,0x22,0x22,0xFE,0x21,0x21,0x20,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"仟\",2171*/},{\n\n0x55,0x56,0x54,0x40,0x55,0xFE,0x54,0xFE,0x55,0xF4,0x40,0x0F,0x05,0x0F,0x04,0x03,\n0x0F,0x01,0x0F,0x03,0x05,0x08,/*\"謙\",2172*/},{\n\n0xFA,0xAA,0xAF,0xAA,0xFA,0x08,0x24,0x27,0xA4,0x64,0x04,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x06,0x09,0x08,0x08,0x0E,/*\"乾\",2173*/},{\n\n0x5F,0x55,0x51,0xFF,0x55,0x7F,0x90,0x8C,0xA3,0x8C,0x90,0x0A,0x06,0x0A,0x05,0x09,\n0x05,0x08,0x00,0x08,0x06,0x01,/*\"黔\",2174*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x04,0x24,0xD7,0x8A,0xD7,0x9A,0x08,0x09,0x07,0x05,0x04,\n0x01,0x09,0x0B,0x04,0x0A,0x0C,/*\"錢\",2175*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x04,0xFF,0x44,0x44,0xFF,0x04,0x08,0x09,0x07,0x05,0x04,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"鉗\",2176*/},{\n\n0x04,0xF4,0x55,0x56,0x54,0xF4,0x04,0xE6,0x05,0xF4,0x04,0x00,0x0F,0x01,0x01,0x09,\n0x0F,0x00,0x03,0x08,0x0F,0x00,/*\"前\",2177*/},{\n\n0x11,0x22,0x00,0x2C,0xD9,0x4F,0x79,0x6C,0x59,0xFF,0x29,0x04,0x02,0x01,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"潛\",2178*/},{\n\n0x11,0xF2,0x20,0x2E,0xEA,0xAA,0xBF,0xAA,0xEA,0x2E,0x20,0x08,0x07,0x08,0x08,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x08,/*\"遣\",2179*/},{\n\n0x10,0x21,0x02,0x00,0x24,0x24,0xD7,0x8A,0xD7,0xA2,0xBA,0x04,0x02,0x01,0x00,0x09,\n0x09,0x05,0x02,0x05,0x08,0x0E,/*\"淺\",2180*/},{\n\n0x55,0x56,0x54,0x22,0xE4,0x2E,0xEA,0xBF,0xAA,0xEE,0x20,0x0F,0x05,0x07,0x08,0x07,\n0x08,0x0F,0x0A,0x0A,0x0E,0x08,/*\"譴\",2181*/},{\n\n0x82,0xBE,0xAA,0xFF,0xAA,0xBE,0x02,0xFC,0x14,0xF2,0x12,0x08,0x0A,0x0A,0x0B,0x0A,\n0x0F,0x0B,0x0A,0x0A,0x0B,0x08,/*\"塹\",2182*/},{\n\n0x20,0xF6,0x24,0x24,0xF4,0x27,0x44,0x3C,0xA4,0x26,0x60,0x00,0x0F,0x09,0x09,0x0F,\n0x00,0x08,0x06,0x01,0x06,0x08,/*\"嵌\",2183*/},{\n\n0x20,0x18,0x07,0x04,0x84,0x74,0x84,0x04,0x24,0x1C,0x00,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"欠\",2184*/},{\n\n0x44,0x55,0xFE,0x54,0xFE,0x55,0xF4,0x50,0x0F,0xC4,0x1C,0x05,0x03,0x0F,0x01,0x0F,\n0x03,0x05,0x08,0x06,0x01,0x0E,/*\"歉\",2185*/},{\n\n0x84,0x64,0xFF,0x24,0x08,0xFC,0xAA,0xAD,0xAA,0xFC,0x08,0x00,0x00,0x0F,0x04,0x03,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"槍\",2186*/},{\n\n0xFC,0x04,0xFC,0x00,0x08,0xFC,0xAA,0xAD,0xAA,0xFC,0x08,0x03,0x01,0x03,0x04,0x03,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"嗆\",2187*/},{\n\n0x00,0xFE,0x92,0xFE,0x4C,0xA4,0x95,0x86,0x94,0xA4,0x4C,0x08,0x07,0x08,0x0F,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"腔\",2188*/},{\n\n0x40,0x44,0x55,0x56,0xF4,0x5C,0xD4,0x56,0x55,0x44,0x40,0x00,0x08,0x04,0x03,0x00,\n0x00,0x07,0x08,0x08,0x08,0x0C,/*\"羌\",2189*/},{\n\n0xDE,0x50,0xFF,0x00,0xDA,0x56,0x5A,0x5F,0x5A,0x56,0xDA,0x07,0x00,0x0F,0x00,0x0F,\n0x08,0x0F,0x0D,0x0F,0x08,0x0F,/*\"牆\",2190*/},{\n\n0x82,0xD2,0xB2,0xD7,0x92,0xFA,0x92,0xD7,0xB2,0xD2,0x82,0x00,0x0F,0x08,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x08,0x0F,0x00,/*\"薔\",2191*/},{\n\n0xF2,0x92,0x9E,0x00,0xE8,0xAC,0xAA,0xF9,0xA8,0xAC,0xE8,0x08,0x08,0x07,0x00,0x04,\n0x04,0x04,0x07,0x04,0x04,0x0E,/*\"強\",2192*/},{\n\n0x84,0xFF,0x44,0x08,0xFC,0xAA,0xAD,0xA9,0xAA,0xFC,0x08,0x08,0x0F,0x04,0x03,0x0E,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"搶\",2193*/},{\n\n0xC8,0xFF,0x48,0x20,0x2A,0xAA,0x3E,0x55,0x55,0xD0,0x60,0x00,0x0F,0x00,0x05,0x0F,\n0x0A,0x00,0x05,0x0F,0x0A,0x0C,/*\"橇\",2194*/},{\n\n0x4A,0xF9,0x4A,0x00,0x92,0xFE,0x51,0x08,0xFF,0x10,0x0C,0x0A,0x0F,0x05,0x01,0x00,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"鍬\",2195*/},{\n\n0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x20,0xE0,0x3F,0xE4,0x0F,0x00,0x0E,0x0A,0x0E,\n0x00,0x0F,0x08,0x05,0x02,0x0D,/*\"敲\",2196*/},{\n\n0x78,0x00,0xFF,0x08,0xF2,0x54,0x50,0x5F,0x50,0x54,0xF2,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x01,0x01,0x01,0x09,0x0F,/*\"悄\",2197*/},{\n\n0x84,0x64,0xFF,0x24,0xA8,0x9A,0xEE,0xAA,0xE9,0x99,0xA8,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"橋\",2198*/},{\n\n0xFE,0x92,0xFE,0x10,0xFC,0x57,0x54,0xFD,0x56,0x54,0x04,0x0F,0x04,0x07,0x0C,0x03,\n0x05,0x09,0x05,0x09,0x05,0x09,/*\"瞧\",2199*/},{\n\n0x14,0x94,0x8D,0xFD,0xD7,0xD5,0xD5,0xF5,0x8D,0x94,0x14,0x00,0x0F,0x00,0x00,0x0E,\n0x0A,0x0E,0x00,0x08,0x0F,0x00,/*\"喬\",2200*/},{\n\n0x20,0x10,0xFC,0x03,0xA8,0x9A,0xEE,0xAA,0xE9,0x99,0xA8,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"僑\",2201*/},{\n\n0x04,0x04,0xFC,0x04,0x00,0x62,0x5A,0x46,0x42,0x42,0xC2,0x02,0x02,0x01,0x01,0x01,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"巧\",2202*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x00,0xF2,0x54,0x5F,0x54,0xF2,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x01,0x01,0x09,0x0F,/*\"鞘\",2203*/},{\n\n0x88,0xFF,0x48,0x20,0x2A,0xAA,0x3E,0x55,0x55,0xD0,0x60,0x08,0x0F,0x00,0x05,0x0F,\n0x0A,0x00,0x05,0x0F,0x0A,0x0C,/*\"撬\",2204*/},{\n\n0xA8,0xFA,0xAF,0xFA,0xA8,0x45,0x29,0xFF,0x44,0x29,0xFF,0x0A,0x06,0x02,0x06,0x0A,\n0x08,0x09,0x09,0x08,0x09,0x0D,/*\"翹\",2205*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xF2,0x54,0x5F,0x54,0xF2,0x07,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x01,0x01,0x09,0x0F,/*\"峭\",2206*/},{\n\n0x10,0xFC,0x03,0x00,0xF2,0x54,0x50,0x5F,0x50,0x54,0xF2,0x00,0x0F,0x00,0x00,0x0F,\n0x01,0x01,0x01,0x01,0x09,0x0F,/*\"俏\",2207*/},{\n\n0x86,0xBA,0xEE,0xBA,0xAA,0xBB,0x42,0xBA,0x26,0xEA,0x26,0x08,0x07,0x02,0x0A,0x0A,\n0x06,0x08,0x05,0x02,0x05,0x08,/*\"竅\",2208*/},{\n\n0x10,0x10,0xFF,0x08,0x08,0x02,0x02,0xFE,0x02,0x02,0xFE,0x00,0x00,0x07,0x02,0x09,\n0x04,0x03,0x00,0x08,0x08,0x07,/*\"切\",2209*/},{\n\n0x22,0x22,0xF2,0x27,0x22,0xE2,0x02,0xE7,0x22,0x22,0xE2,0x08,0x06,0x01,0x08,0x08,\n0x07,0x00,0x0F,0x04,0x04,0x0F,/*\"茄\",2210*/},{\n\n0x00,0x00,0xFE,0x92,0x92,0x92,0x92,0x92,0xFE,0x00,0x00,0x08,0x08,0x0F,0x08,0x08,\n0x08,0x08,0x08,0x0F,0x08,0x08,/*\"且\",2211*/},{\n\n0x78,0x00,0xFF,0x08,0x50,0x48,0x48,0xFF,0x48,0x48,0x40,0x00,0x00,0x0F,0x00,0x04,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"怯\",2212*/},{\n\n0x56,0x1A,0xF6,0x12,0x4A,0x03,0xC2,0x7A,0x56,0xDA,0x06,0x05,0x03,0x0F,0x03,0x05,\n0x0F,0x01,0x07,0x05,0x09,0x0F,/*\"竊\",2213*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0x10,0x0F,0xC4,0x14,0x0C,0x08,0x09,0x07,0x05,0x04,\n0x00,0x08,0x06,0x01,0x06,0x08,/*\"欽\",2214*/},{\n\n0x10,0xFC,0x03,0xC0,0x51,0x55,0x55,0x55,0x55,0x5F,0xC0,0x00,0x0F,0x00,0x08,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"侵\",2215*/},{\n\n0x22,0xAA,0xF3,0xAA,0x22,0x00,0xFE,0xAA,0xAA,0xFE,0x00,0x04,0x0A,0x0F,0x02,0x04,\n0x08,0x06,0x01,0x07,0x08,0x0C,/*\"親\",2216*/},{\n\n0x20,0xA2,0x6A,0xBA,0xAE,0xAB,0xAA,0xAA,0x6A,0xA2,0x20,0x01,0x02,0x0A,0x06,0x02,\n0x0F,0x02,0x06,0x0A,0x02,0x01,/*\"秦\",2217*/},{\n\n0x11,0x15,0x9F,0x95,0x51,0xA0,0x51,0x95,0x9F,0x15,0x11,0x01,0x01,0x02,0x02,0x02,\n0x02,0x0B,0x06,0x02,0x01,0x01,/*\"琴\",2218*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x00,0x08,0xFF,0x08,0x08,0xF8,0x0A,0x0A,0x0F,0x0A,0x0A,\n0x08,0x06,0x01,0x08,0x08,0x07,/*\"勤\",2219*/},{\n\n0x02,0x02,0xF2,0x97,0x92,0x92,0x92,0x8F,0x8A,0x8A,0x82,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"芹\",2220*/},{\n\n0x88,0x88,0xFF,0x48,0x72,0x46,0x6D,0xD7,0x6D,0x46,0x72,0x00,0x08,0x0F,0x00,0x0F,\n0x01,0x07,0x05,0x0F,0x01,0x0F,/*\"擒\",2221*/},{\n\n0x04,0xE4,0x8C,0xDA,0xAA,0xAD,0xAA,0xDA,0x8C,0xE4,0x04,0x0E,0x02,0x0A,0x0E,0x0A,\n0x0B,0x0E,0x0A,0x02,0x0A,0x0E,/*\"禽\",2222*/},{\n\n0x86,0xBA,0xA2,0xFE,0x02,0xAB,0xAA,0xAA,0xAA,0xFA,0x86,0x08,0x07,0x00,0x0F,0x01,\n0x08,0x05,0x02,0x05,0x08,0x09,/*\"寢\",2223*/},{\n\n0x10,0x22,0x04,0x00,0xE0,0x00,0xF0,0x01,0x06,0x10,0xE0,0x04,0x02,0x01,0x02,0x01,\n0x00,0x07,0x08,0x08,0x0E,0x00,/*\"沁\",2224*/},{\n\n0x22,0x2A,0xEA,0xAA,0xAA,0xBF,0xAA,0xAA,0xEA,0x2A,0x22,0x00,0x00,0x0F,0x02,0x02,\n0x02,0x02,0x0A,0x0F,0x00,0x00,/*\"青\",2225*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x10,0xAA,0x92,0xAA,0x92,0xAA,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x08,0x08,0x0F,0x08,0x08,/*\"輕\",2226*/},{\n\n0x08,0xA4,0x6B,0xAA,0x6A,0xAA,0x6A,0x2A,0xFA,0x02,0x02,0x08,0x0A,0x0B,0x0A,0x0F,\n0x0A,0x0B,0x0A,0x0B,0x04,0x0E,/*\"氫\",2227*/},{\n\n0x10,0xFC,0x03,0xFC,0x10,0x10,0xFA,0xAA,0xAE,0xAA,0xFA,0x00,0x0F,0x00,0x07,0x02,\n0x01,0x0B,0x06,0x02,0x06,0x0B,/*\"傾\",2228*/},{\n\n0xFE,0x82,0xF9,0x00,0xFE,0x92,0xFE,0x00,0xFE,0x02,0xFE,0x09,0x04,0x03,0x00,0x0F,\n0x04,0x02,0x04,0x0F,0x02,0x03,/*\"卿\",2229*/},{\n\n0x22,0x44,0x22,0xEA,0xAA,0xAA,0xBF,0xAA,0xAA,0xEA,0x22,0x04,0x02,0x00,0x0F,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"清\",2230*/},{\n\n0x12,0xBF,0xAA,0xBA,0xCF,0xBA,0xC4,0xAB,0x92,0x2E,0x42,0x02,0x02,0x02,0x0A,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"擎\",2231*/},{\n\n0xFE,0x22,0xFE,0x00,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x07,0x02,0x07,0x00,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"晴\",2232*/},{\n\n0x88,0xA4,0xAB,0xFA,0xAA,0xAA,0xAA,0x8A,0xFA,0x02,0x02,0x00,0x0F,0x02,0x02,0x02,\n0x0A,0x0F,0x00,0x03,0x04,0x0E,/*\"氰\",2233*/},{\n\n0x78,0x00,0xFF,0x04,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"情\",2234*/},{\n\n0x00,0xFF,0x10,0x10,0x00,0xFA,0xAA,0xAE,0xAA,0xAA,0xFA,0x00,0x07,0x02,0x01,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"頃\",2235*/},{\n\n0x54,0x55,0x56,0x54,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"請\",2236*/},{\n\n0x00,0xFE,0x2A,0xAA,0x3E,0xAA,0x6B,0x3E,0xAA,0x3A,0x62,0x08,0x07,0x01,0x08,0x0A,\n0x0B,0x05,0x05,0x0B,0x08,0x09,/*\"慶\",2237*/},{\n\n0x22,0xFE,0x22,0x04,0xEE,0x25,0x75,0xAD,0x77,0xA4,0xEC,0x02,0x03,0x01,0x02,0x09,\n0x0B,0x05,0x05,0x0B,0x09,0x09,/*\"瓊\",2238*/},{\n\n0x06,0xFA,0xAE,0xAA,0xFA,0x03,0xCA,0x4A,0x4E,0x7A,0x06,0x0A,0x0B,0x06,0x0A,0x0F,\n0x00,0x01,0x01,0x09,0x09,0x07,/*\"窮\",2239*/},{\n\n0x12,0xD2,0xFE,0x91,0x20,0x1C,0x80,0x7F,0x80,0x10,0x0C,0x01,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x01,0x06,0x08,/*\"秋\",2240*/},{\n\n0x00,0x00,0xFE,0x22,0x22,0x22,0x22,0xE1,0x21,0x20,0x00,0x08,0x08,0x0F,0x08,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"丘\",2241*/},{\n\n0x00,0xFE,0x12,0x12,0xF1,0x10,0x00,0xFE,0x02,0x32,0xCE,0x04,0x07,0x04,0x02,0x03,\n0x02,0x00,0x0F,0x02,0x02,0x01,/*\"邱\",2242*/},{\n\n0x22,0x22,0xFE,0x22,0x08,0x28,0xC8,0xFF,0x68,0x89,0x4A,0x04,0x04,0x03,0x02,0x02,\n0x01,0x08,0x0F,0x00,0x01,0x02,/*\"球\",2243*/},{\n\n0x04,0x14,0x24,0x84,0x44,0xFF,0x34,0xC4,0x25,0x16,0x04,0x02,0x02,0x01,0x00,0x08,\n0x0F,0x00,0x00,0x01,0x02,0x04,/*\"求\",2244*/},{\n\n0x00,0xFF,0x01,0x81,0x61,0x1D,0x21,0x41,0x81,0x01,0xFF,0x00,0x0F,0x09,0x08,0x08,\n0x08,0x08,0x08,0x09,0x08,0x0F,/*\"囚\",2245*/},{\n\n0x04,0xF4,0x95,0x56,0x3C,0x14,0x7C,0x56,0x55,0xF4,0x04,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"酋\",2246*/},{\n\n0x22,0x44,0x00,0xFE,0x02,0x82,0x7A,0x82,0x02,0x02,0xFE,0x04,0x02,0x00,0x0F,0x05,\n0x04,0x04,0x04,0x05,0x04,0x0F,/*\"泅\",2247*/},{\n\n0xA4,0x24,0xFF,0x24,0x00,0x2C,0xDB,0x8E,0xAA,0xBE,0x00,0x0F,0x04,0x0F,0x09,0x08,\n0x0B,0x0E,0x0B,0x0A,0x0F,0x08,/*\"趨\",2248*/},{\n\n0x00,0xFF,0x01,0xC1,0x5D,0xD5,0x15,0xD5,0x5D,0xC1,0x01,0x00,0x0F,0x08,0x0B,0x0A,\n0x0B,0x08,0x0B,0x0A,0x0B,0x08,/*\"區\",2249*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFE,0x92,0x92,0xFE,0x00,0x04,0x04,0x03,0x02,0x07,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"蛆\",2250*/},{\n\n0x00,0xFC,0x44,0x44,0xFF,0x44,0x44,0xFF,0x44,0x44,0xFC,0x00,0x0F,0x04,0x04,0x07,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"曲\",2251*/},{\n\n0xFE,0xAB,0xFE,0x00,0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x02,0x09,0x0F,0x00,0x0F,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"軀\",2252*/},{\n\n0x00,0x00,0xFF,0x05,0x75,0x45,0x45,0xFD,0x45,0x45,0x77,0x08,0x06,0x01,0x00,0x07,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"屈\",2253*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x00,0xFE,0x82,0xBA,0xAA,0xBA,0x82,0x04,0x0A,0x08,0x07,0x00,\n0x0F,0x0B,0x0A,0x0B,0x0A,0x0B,/*\"驅\",2254*/},{\n\n0x04,0x49,0x22,0x00,0x7F,0xD5,0x55,0x55,0x55,0x5D,0x41,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"渠\",2255*/},{\n\n0x02,0xFE,0x52,0x52,0xFE,0x02,0x04,0xFC,0x04,0xFC,0x00,0x02,0x03,0x02,0x02,0x0F,\n0x01,0x08,0x04,0x03,0x04,0x08,/*\"取\",2256*/},{\n\n0x41,0x7F,0x55,0x55,0xFF,0x21,0x82,0x5E,0x22,0x52,0x8E,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"娶\",2257*/},{\n\n0xEE,0xA8,0x9F,0xAA,0xEA,0x00,0xBA,0xAA,0xFE,0xA9,0xB9,0x0F,0x0A,0x09,0x0A,0x0F,\n0x00,0x0F,0x02,0x03,0x0A,0x0F,/*\"齲\",2258*/},{\n\n0xA4,0x24,0xFF,0x25,0xFF,0x29,0xFF,0x81,0x3A,0xC2,0x3E,0x0F,0x04,0x0F,0x09,0x09,\n0x09,0x0F,0x0A,0x09,0x08,0x0B,/*\"趣\",2259*/},{\n\n0x40,0x48,0x48,0x48,0xC8,0x7F,0x48,0x48,0x48,0x48,0x40,0x00,0x04,0x06,0x05,0x04,\n0x04,0x04,0x05,0x06,0x0C,0x00,/*\"去\",2260*/},{\n\n0xFF,0x91,0x55,0xF7,0x5D,0x57,0x55,0xF7,0x55,0x91,0xFF,0x0F,0x08,0x08,0x09,0x0A,\n0x0B,0x0B,0x0A,0x0B,0x08,0x0F,/*\"圈\",2261*/},{\n\n0xBA,0xEF,0xBA,0xC2,0xBA,0xAF,0xBA,0x00,0xFD,0xAB,0xF9,0x00,0x0F,0x0A,0x0A,0x0F,\n0x0A,0x0A,0x00,0x0B,0x06,0x0B,/*\"顴\",2262*/},{\n\n0x88,0x68,0xFF,0x48,0xBA,0xEF,0xBA,0xC2,0xBA,0xAF,0xBA,0x00,0x00,0x0F,0x01,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"權\",2263*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x00,0x22,0x57,0xCA,0x57,0x22,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x08,0x09,0x0F,0x09,0x08,/*\"醛\",2264*/},{\n\n0x80,0xBE,0xAA,0xAA,0x2B,0xEA,0xAA,0x2A,0xAA,0x7E,0x00,0x04,0x04,0x02,0x01,0x08,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"泉\",2265*/},{\n\n0x10,0x10,0x28,0x24,0x22,0xE1,0x22,0x24,0x28,0x10,0x10,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"全\",2266*/},{\n\n0x08,0x90,0xFE,0x02,0x22,0x52,0x4B,0xC6,0x4A,0x52,0x22,0x09,0x04,0x03,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"痊\",2267*/},{\n\n0x48,0x2A,0x9B,0xAA,0xAE,0xEB,0xAA,0x9A,0x9B,0x2A,0x48,0x00,0x02,0x02,0x02,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x00,/*\"拳\",2268*/},{\n\n0x10,0x10,0x10,0x10,0xD0,0x3F,0xD0,0x10,0x12,0x14,0x10,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x03,0x04,0x08,0x08,/*\"犬\",2269*/},{\n\n0x90,0x54,0xB5,0x96,0x9C,0x97,0x94,0x96,0xB5,0x54,0x90,0x00,0x08,0x04,0x02,0x01,\n0x00,0x08,0x08,0x07,0x00,0x00,/*\"券\",2270*/},{\n\n0xBA,0xEF,0xBA,0xC2,0xBA,0xAF,0xBA,0x04,0xFF,0x04,0xFC,0x00,0x0F,0x0A,0x0A,0x0F,\n0x0A,0x0A,0x04,0x03,0x08,0x0F,/*\"勸\",2271*/},{\n\n0xA4,0x23,0xFE,0x22,0xA2,0x44,0x44,0xFF,0x44,0x7C,0x40,0x07,0x04,0x03,0x02,0x0F,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"缺\",2272*/},{\n\n0x78,0x00,0xFF,0x08,0x44,0x44,0x44,0xFF,0x44,0x7C,0x40,0x08,0x06,0x01,0x06,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"炔\",2273*/},{\n\n0x88,0xFE,0x02,0xAA,0x9E,0xAA,0xFB,0x82,0xBA,0xAA,0xBA,0x08,0x07,0x00,0x0F,0x00,\n0x0A,0x05,0x0A,0x00,0x08,0x0F,/*\"瘸\",2274*/},{\n\n0x44,0xA2,0x91,0x8C,0x91,0xA2,0x44,0xFE,0x02,0x02,0xFE,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x00,0x0F,0x00,0x02,0x03,/*\"卻\",2275*/},{\n\n0x14,0xDF,0x54,0xDF,0x14,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x00,0x0F,0x05,0x0F,0x00,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鵲\",2276*/},{\n\n0x88,0x68,0xFF,0x48,0x26,0xF2,0xAA,0xA7,0xEA,0xB2,0xA6,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"榷\",2277*/},{\n\n0x42,0xF2,0x2E,0xE2,0x4C,0xE4,0xBC,0xA7,0xEC,0xB4,0xAC,0x00,0x0F,0x04,0x0F,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"確\",2278*/},{\n\n0x28,0x24,0xE2,0xB0,0xB0,0xAF,0xE8,0xB4,0xA2,0xA4,0x28,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"雀\",2279*/},{\n\n0x45,0xF6,0xAC,0x00,0xAA,0xEA,0xBE,0xAA,0xAA,0xBE,0x08,0x00,0x0F,0x00,0x01,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"裙\",2280*/},{\n\n0x84,0x55,0x75,0x5D,0x77,0xD5,0x55,0x75,0x55,0x5F,0x04,0x04,0x04,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x05,0x04,/*\"羣\",2281*/},{\n\n0x10,0xAC,0x4B,0x32,0x0E,0x88,0x68,0x1F,0x68,0x89,0x0A,0x09,0x04,0x00,0x04,0x09,\n0x00,0x04,0x08,0x00,0x04,0x09,/*\"然\",2282*/},{\n\n0x78,0x00,0xFF,0x24,0x58,0xD7,0x3C,0xC8,0x3F,0xC8,0x0A,0x08,0x06,0x01,0x06,0x0D,\n0x00,0x0D,0x00,0x0C,0x00,0x0D,/*\"燃\",2283*/},{\n\n0x00,0xFC,0x24,0x24,0x24,0xFF,0x24,0x24,0x24,0xFC,0x00,0x01,0x0F,0x01,0x01,0x01,\n0x01,0x01,0x09,0x09,0x0F,0x01,/*\"冉\",2284*/},{\n\n0xA4,0x91,0x82,0xA0,0x92,0xCF,0x82,0x82,0x9E,0xA0,0xB0,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"染\",2285*/},{\n\n0xBA,0xAA,0xFA,0x83,0xFA,0xAA,0xFE,0x02,0xFE,0x02,0xFD,0x0A,0x06,0x0F,0x0A,0x07,\n0x0A,0x07,0x00,0x0F,0x0A,0x0C,/*\"瓤\",2286*/},{\n\n0x10,0xFF,0x10,0x00,0xBA,0xAA,0xFA,0x83,0xFA,0xAA,0xBA,0x04,0x07,0x02,0x00,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"壤\",2287*/},{\n\n0x88,0xFF,0x48,0x00,0xBA,0xAA,0xFA,0x83,0xFA,0xAA,0xBA,0x08,0x0F,0x00,0x00,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"攘\",2288*/},{\n\n0xFE,0x02,0xFE,0x00,0xBA,0xAA,0xFA,0x83,0xFA,0xAA,0xBA,0x03,0x01,0x03,0x00,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"嚷\",2289*/},{\n\n0x55,0x56,0x54,0x00,0xBA,0xAA,0xFA,0x83,0xFA,0xAA,0xBA,0x0F,0x05,0x0F,0x00,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"讓\",2290*/},{\n\n0xFA,0xAD,0xFA,0x00,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x0F,0x04,0x02,0x04,0x0A,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"饒\",2291*/},{\n\n0x88,0xFF,0x48,0x00,0xB1,0x5D,0x95,0x37,0x95,0x5D,0xB1,0x08,0x0F,0x00,0x00,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"擾\",2292*/},{\n\n0xDC,0xB3,0xC8,0x00,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x0E,0x00,0x06,0x00,0x0A,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"繞\",2293*/},{\n\n0x4A,0x4A,0x2A,0xEF,0xBA,0xAE,0xAA,0xAF,0xAA,0xEA,0x0A,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"惹\",2294*/},{\n\n0x28,0x5A,0xEF,0x5A,0x28,0x94,0x7F,0x24,0x7C,0x80,0xC0,0x09,0x05,0x01,0x05,0x09,\n0x00,0x04,0x08,0x00,0x04,0x09,/*\"熱\",2295*/},{\n\n0x40,0x44,0x44,0x44,0x44,0xFC,0x42,0x42,0x42,0x42,0x40,0x00,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x00,/*\"壬\",2296*/},{\n\n0x20,0x10,0xFC,0x03,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x04,/*\"仁\",2297*/},{\n\n0x00,0x00,0x00,0x80,0x60,0x1F,0x60,0x80,0x00,0x00,0x00,0x08,0x04,0x02,0x01,0x00,\n0x00,0x00,0x01,0x02,0x04,0x08,/*\"人\",2298*/},{\n\n0x00,0x51,0x4D,0x21,0x11,0x8F,0x21,0x21,0x21,0x1F,0x00,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"忍\",2299*/},{\n\n0x8A,0xBE,0xAB,0xEA,0xBE,0x88,0x72,0x02,0xFE,0x02,0xFE,0x06,0x04,0x04,0x0F,0x04,\n0x0C,0x04,0x03,0x08,0x08,0x07,/*\"韌\",2300*/},{\n\n0x20,0x10,0xFC,0x03,0x40,0x44,0x44,0xFC,0x42,0x42,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x08,0x08,0x0F,0x08,0x08,0x00,/*\"任\",2301*/},{\n\n0x54,0x55,0x56,0x54,0x10,0x4A,0xA2,0x1E,0x42,0x42,0x3E,0x0F,0x05,0x05,0x0F,0x04,\n0x02,0x0C,0x09,0x0C,0x01,0x06,/*\"認\",2302*/},{\n\n0x00,0x82,0x72,0x02,0x82,0x7E,0x02,0x02,0x02,0x02,0xFE,0x08,0x08,0x04,0x02,0x01,\n0x00,0x00,0x08,0x08,0x08,0x07,/*\"刃\",2303*/},{\n\n0x88,0x78,0x0F,0xF8,0x40,0x44,0x44,0xFC,0x42,0x42,0x40,0x08,0x05,0x02,0x0D,0x00,\n0x08,0x08,0x0F,0x08,0x08,0x00,/*\"妊\",2304*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x80,0x72,0x02,0xFE,0x02,0xFE,0x0E,0x00,0x06,0x00,0x06,\n0x08,0x04,0x03,0x08,0x08,0x07,/*\"紉\",2305*/},{\n\n0x88,0x88,0xFF,0x48,0x02,0xFE,0x02,0x02,0x72,0x4E,0xC0,0x00,0x08,0x0F,0x08,0x06,\n0x01,0x00,0x00,0x08,0x08,0x07,/*\"扔\",2306*/},{\n\n0x10,0xFC,0x03,0x00,0x02,0xFE,0x02,0x02,0x72,0x4E,0xC0,0x00,0x0F,0x00,0x08,0x06,\n0x01,0x00,0x00,0x08,0x08,0x07,/*\"仍\",2307*/},{\n\n0x00,0xFE,0x22,0x22,0x22,0x22,0x22,0x22,0x22,0xFE,0x00,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"日\",2308*/},{\n\n0x44,0x44,0xF4,0x44,0x44,0x04,0xFF,0x04,0xC5,0x36,0x04,0x08,0x06,0x01,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x0F,/*\"戎\",2309*/},{\n\n0x02,0x12,0xF2,0x57,0x52,0x52,0x52,0x57,0xF2,0x12,0x02,0x04,0x04,0x07,0x05,0x05,\n0x05,0x05,0x05,0x0F,0x02,0x02,/*\"茸\",2310*/},{\n\n0x1A,0x0A,0xAA,0x9F,0x4A,0x2E,0x4A,0x9F,0xAA,0x0A,0x1A,0x01,0x01,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x01,0x01,/*\"蓉\",2311*/},{\n\n0xBA,0x94,0x93,0x94,0x9A,0xD0,0x9A,0x94,0x93,0x94,0xBA,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"榮\",2312*/},{\n\n0xC1,0xDD,0x55,0xDD,0xC1,0x00,0xF8,0x88,0xFF,0x88,0xF8,0x0F,0x02,0x07,0x0A,0x0F,\n0x00,0x08,0x08,0x0F,0x04,0x0E,/*\"融\",2313*/},{\n\n0x78,0x00,0xFF,0x08,0x96,0x4A,0x22,0x13,0x22,0x4A,0x96,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"熔\",2314*/},{\n\n0x10,0x22,0x04,0x00,0x96,0x4A,0x22,0x13,0x22,0x4A,0x96,0x04,0x02,0x01,0x00,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"溶\",2315*/},{\n\n0x46,0x42,0xAA,0xA6,0x92,0x8B,0x92,0xA6,0xAA,0x42,0x46,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x0F,0x00,0x00,/*\"容\",2316*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x44,0xF4,0x44,0xFF,0x84,0x65,0x0C,0x02,0x04,0x02,0x04,\n0x02,0x09,0x04,0x03,0x04,0x0E,/*\"絨\",2317*/},{\n\n0x0E,0x02,0x02,0xF2,0x12,0x12,0x12,0xF2,0x02,0x02,0x0E,0x08,0x04,0x02,0x01,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"冗\",2318*/},{\n\n0x88,0xFF,0x48,0x00,0x48,0x29,0x1B,0xCD,0x7D,0x0B,0x18,0x08,0x0F,0x00,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"揉\",2319*/},{\n\n0x28,0x28,0x29,0x19,0x0B,0xAD,0x3D,0x0B,0x09,0x08,0x18,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"柔\",2320*/},{\n\n0x00,0xFC,0x04,0x24,0x14,0xCF,0x14,0x24,0x04,0xFC,0x00,0x00,0x0F,0x00,0x02,0x01,\n0x00,0x01,0x0A,0x08,0x0F,0x00,/*\"肉\",2321*/},{\n\n0x22,0x22,0xE2,0x37,0x22,0xE2,0x02,0xE7,0x22,0x22,0xE2,0x08,0x09,0x05,0x02,0x05,\n0x08,0x00,0x0F,0x04,0x04,0x0F,/*\"茹\",2322*/},{\n\n0x78,0x48,0xFF,0x48,0x4C,0x55,0x45,0xDF,0x45,0x55,0x4C,0x04,0x04,0x03,0x02,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"蠕\",2323*/},{\n\n0x20,0x10,0xFC,0x03,0x4C,0x55,0x45,0xDF,0x45,0x55,0x4C,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"儒\",2324*/},{\n\n0x41,0xF9,0x27,0x00,0x4C,0x55,0x45,0xDF,0x45,0x55,0x4C,0x08,0x0F,0x00,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"孺\",2325*/},{\n\n0x88,0x78,0x0F,0x88,0x78,0x00,0xFC,0x04,0x04,0x04,0xFC,0x08,0x05,0x02,0x05,0x08,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"如\",2326*/},{\n\n0x80,0x7F,0x11,0xF5,0x95,0x15,0x35,0x55,0x55,0xB5,0x91,0x02,0x02,0x06,0x0A,0x02,\n0x02,0x02,0x0A,0x0F,0x02,0x02,/*\"辱\",2327*/},{\n\n0x2A,0x32,0x26,0xAA,0x61,0x29,0x05,0x00,0xFF,0x00,0x00,0x02,0x02,0x0A,0x0F,0x01,\n0x01,0x01,0x00,0x07,0x08,0x0E,/*\"乳\",2328*/},{\n\n0x11,0x22,0x08,0x48,0x78,0x8F,0x08,0x88,0x78,0x08,0x08,0x04,0x02,0x08,0x08,0x04,\n0x02,0x01,0x02,0x04,0x08,0x00,/*\"汝\",2329*/},{\n\n0x00,0x00,0x01,0x81,0x72,0x0C,0x70,0x80,0x00,0x00,0x00,0x08,0x04,0x02,0x01,0x00,\n0x00,0x00,0x01,0x02,0x04,0x08,/*\"入\",2330*/},{\n\n0x45,0xF6,0xAC,0x00,0xFF,0x11,0xF5,0x95,0x35,0x55,0xB5,0x00,0x0F,0x00,0x08,0x07,\n0x02,0x06,0x02,0x0A,0x0F,0x02,/*\"褥\",2331*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x20,0x18,0xE7,0x04,0x14,0x0C,0x02,0x02,0x0F,0x02,0x0A,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"軟\",2332*/},{\n\n0xFE,0x02,0x32,0xCE,0x10,0x12,0xF2,0x12,0xF2,0x12,0x10,0x0F,0x02,0x02,0x01,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"阮\",2333*/},{\n\n0x42,0x22,0x87,0x22,0x4A,0x52,0xC2,0x62,0x07,0x22,0x42,0x06,0x00,0x06,0x09,0x0C,\n0x02,0x06,0x09,0x0C,0x01,0x02,/*\"蕊\",2334*/},{\n\n0x22,0xFE,0x22,0x00,0xAE,0xA8,0xA8,0xEF,0xA8,0xA8,0xAE,0x04,0x07,0x02,0x00,0x0F,\n0x00,0x07,0x00,0x07,0x08,0x0F,/*\"瑞\",2335*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x04,0xFA,0x89,0x88,0x89,0xFA,0x04,0x08,0x09,0x07,0x04,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"銳\",2336*/},{\n\n0xFF,0x15,0x55,0x5F,0x40,0xC0,0x40,0x5F,0x55,0x15,0xFF,0x0F,0x00,0x04,0x05,0x05,\n0x07,0x05,0x05,0x04,0x08,0x0F,/*\"閏\",2337*/},{\n\n0x11,0x22,0xFF,0x15,0x55,0x5F,0xC0,0x5F,0x55,0x15,0xFF,0x04,0x02,0x0F,0x00,0x05,\n0x05,0x07,0x05,0x05,0x08,0x0F,/*\"潤\",2338*/},{\n\n0x12,0x12,0x92,0xD7,0xB2,0x9E,0x92,0x97,0x92,0x92,0x12,0x02,0x01,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"若\",2339*/},{\n\n0x40,0xB9,0x29,0x29,0xEF,0x00,0x40,0xB9,0x29,0x29,0xEF,0x04,0x02,0x09,0x08,0x07,\n0x00,0x04,0x02,0x09,0x08,0x07,/*\"弱\",2340*/},{\n\n0x88,0xFF,0x4A,0xEF,0xAA,0xEF,0x1A,0xEC,0x0B,0xF8,0x08,0x08,0x0F,0x00,0x0F,0x02,\n0x0F,0x08,0x04,0x03,0x04,0x08,/*\"撒\",2341*/},{\n\n0x10,0x21,0x02,0x00,0xED,0xA5,0xED,0xB0,0xED,0xA5,0xAD,0x04,0x02,0x01,0x08,0x07,\n0x02,0x0F,0x0A,0x03,0x0E,0x0B,/*\"灑\",2342*/},{\n\n0xFA,0x4A,0xBA,0x07,0xEA,0x2A,0xFA,0xAF,0xEA,0xBA,0xAA,0x0F,0x02,0x01,0x08,0x07,\n0x01,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"薩\",2343*/},{\n\n0x00,0xFF,0x49,0xFF,0x00,0x7F,0x49,0xFF,0x49,0x7F,0x00,0x08,0x07,0x08,0x0F,0x02,\n0x01,0x06,0x08,0x09,0x0C,0x03,/*\"腮\",2344*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0x7F,0x49,0x7F,0x49,0x7F,0x0D,0x01,0x0D,0x01,0x0D,\n0x02,0x01,0x06,0x09,0x0C,0x03,/*\"鰓\",2345*/},{\n\n0x86,0xAA,0xAA,0xFE,0xAA,0xAB,0xAA,0xFE,0xAA,0xAA,0x86,0x04,0x0A,0x09,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x09,0x0A,0x04,/*\"塞\",2346*/},{\n\n0x26,0xAA,0xEA,0xBE,0xAA,0xAB,0xAA,0xBE,0xEA,0xAA,0x26,0x01,0x00,0x07,0x0C,0x05,\n0x06,0x05,0x0E,0x07,0x00,0x01,/*\"賽\",2347*/},{\n\n0x00,0x02,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x02,0x00,0x08,0x08,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x08,/*\"三\",2348*/},{\n\n0x30,0x2C,0xA6,0xB5,0x44,0x24,0x44,0xB4,0xAE,0x24,0x30,0x01,0x09,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x09,0x01,/*\"叄\",2349*/},{\n\n0x08,0x28,0x94,0x24,0x02,0xF9,0x02,0x24,0x94,0x28,0x08,0x02,0x03,0x02,0x03,0x02,\n0x0F,0x02,0x03,0x02,0x03,0x02,/*\"傘\",2350*/},{\n\n0x0A,0xEF,0xAA,0xAA,0xEF,0x0A,0x10,0xEF,0x08,0xF8,0x08,0x00,0x0F,0x02,0x0A,0x0F,\n0x00,0x08,0x05,0x02,0x05,0x08,/*\"散\",2351*/},{\n\n0x00,0xB1,0x5B,0x55,0xB5,0x05,0xB5,0x5B,0x51,0xB0,0x00,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"桑\",2352*/},{\n\n0xFE,0x02,0xFE,0x00,0xB0,0x5B,0xB5,0x05,0xB5,0x5B,0xB0,0x03,0x01,0x03,0x00,0x0A,\n0x06,0x02,0x0F,0x02,0x06,0x0A,/*\"嗓\",2353*/},{\n\n0x80,0xBA,0xAA,0xBA,0x82,0xFF,0x82,0xBA,0xAA,0xBA,0x80,0x00,0x00,0x0F,0x08,0x04,\n0x00,0x01,0x02,0x04,0x0A,0x08,/*\"喪\",2354*/},{\n\n0x88,0x88,0xFF,0x48,0x22,0xAE,0x92,0xD6,0x92,0xAA,0x26,0x00,0x08,0x0F,0x00,0x08,\n0x0B,0x0A,0x0F,0x0A,0x0B,0x0C,/*\"搔\",2355*/},{\n\n0x7F,0x55,0x7F,0x55,0xC1,0x00,0xD3,0x55,0xEB,0x55,0xD3,0x07,0x00,0x0B,0x08,0x07,\n0x00,0x05,0x05,0x07,0x05,0x0D,/*\"騷\",2356*/},{\n\n0x88,0x88,0xFF,0x48,0xC0,0x55,0x55,0xD5,0x55,0x5F,0xC0,0x00,0x08,0x0F,0x00,0x00,\n0x07,0x01,0x0F,0x05,0x07,0x00,/*\"掃\",2357*/},{\n\n0xF8,0x0F,0xF8,0x00,0xBC,0xAA,0xA0,0xFF,0xA0,0xAA,0xBE,0x0D,0x02,0x05,0x00,0x08,\n0x09,0x0A,0x04,0x04,0x0A,0x09,/*\"嫂\",2358*/},{\n\n0x11,0x95,0x1F,0x15,0x51,0x80,0x11,0x95,0x1F,0x95,0x11,0x02,0x09,0x08,0x07,0x0C,\n0x0A,0x09,0x08,0x0E,0x00,0x03,/*\"瑟\",2359*/},{\n\n0x08,0xF4,0x92,0x93,0x92,0xF2,0x92,0x9A,0x96,0xF0,0x00,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"色\",2360*/},{\n\n0x11,0x22,0x15,0x0F,0xD1,0x9F,0x00,0x15,0x0F,0xD1,0x9F,0x04,0x02,0x0F,0x08,0x07,\n0x04,0x08,0x0F,0x08,0x0F,0x08,/*\"澀\",2361*/},{\n\n0x92,0x92,0x8A,0xE6,0x82,0x1F,0x82,0xE6,0x8A,0x92,0x92,0x04,0x02,0x01,0x0F,0x02,\n0x04,0x02,0x0F,0x01,0x02,0x04,/*\"森\",2362*/},{\n\n0x20,0x10,0xFC,0x03,0x3E,0xAB,0xA2,0xBE,0xA2,0xAB,0x3E,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"僧\",2363*/},{\n\n0x42,0x92,0x22,0x87,0x62,0x02,0xF2,0x07,0x22,0x42,0x82,0x08,0x04,0x02,0x00,0x08,\n0x08,0x05,0x02,0x01,0x00,0x01,/*\"莎\",2364*/},{\n\n0x42,0xF2,0x2E,0xE2,0x40,0x38,0x00,0xFF,0x00,0x04,0xB8,0x00,0x07,0x02,0x03,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,/*\"砂\",2365*/},{\n\n0x00,0x51,0x4A,0xE4,0x4A,0x51,0x08,0xE7,0x21,0xEF,0x08,0x02,0x01,0x08,0x0F,0x00,\n0x01,0x0A,0x05,0x02,0x05,0x08,/*\"殺\",2366*/},{\n\n0x40,0x49,0x45,0xF2,0x42,0x55,0x68,0x00,0xFC,0x00,0xFF,0x04,0x02,0x01,0x0F,0x01,\n0x02,0x04,0x00,0x01,0x08,0x0F,/*\"剎\",2367*/},{\n\n0x10,0x21,0x02,0x40,0x30,0x0C,0x00,0xFF,0x00,0x04,0xB8,0x04,0x02,0x09,0x08,0x08,\n0x04,0x04,0x02,0x02,0x01,0x00,/*\"沙\",2368*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x20,0x18,0x00,0xFF,0x08,0xB0,0x0E,0x00,0x06,0x00,0x06,\n0x08,0x08,0x04,0x02,0x01,0x00,/*\"紗\",2369*/},{\n\n0x10,0xFC,0x03,0xBE,0x62,0xB6,0x2B,0x36,0x62,0xBE,0x00,0x00,0x0F,0x00,0x0A,0x09,\n0x0B,0x05,0x05,0x0B,0x08,0x08,/*\"傻\",2370*/},{\n\n0xFE,0x02,0xFE,0x00,0x28,0xA4,0xAA,0xF9,0xAA,0xA4,0x28,0x03,0x01,0x03,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"啥\",2371*/},{\n\n0x08,0x54,0x53,0x5A,0xF6,0x10,0x08,0xB7,0x44,0xBC,0x04,0x08,0x05,0x01,0x05,0x09,\n0x00,0x05,0x08,0x00,0x04,0x09,/*\"煞\",2372*/},{\n\n0xF4,0x5B,0x52,0x76,0x02,0xD4,0x53,0xF2,0x56,0x52,0xD2,0x0F,0x05,0x05,0x07,0x00,\n0x07,0x00,0x0F,0x00,0x04,0x07,/*\"篩\",2373*/},{\n\n0xFE,0x22,0xFE,0x00,0xED,0xA5,0xED,0xB0,0xED,0xA5,0xAD,0x07,0x02,0x03,0x08,0x07,\n0x02,0x0F,0x0A,0x03,0x0E,0x0B,/*\"曬\",2374*/},{\n\n0x22,0xFE,0x22,0xFF,0x21,0xFF,0x20,0xFF,0x21,0xFF,0x20,0x02,0x0B,0x05,0x03,0x08,\n0x0F,0x04,0x03,0x08,0x0F,0x00,/*\"珊\",2375*/},{\n\n0x02,0x82,0x82,0x87,0x82,0xFA,0x92,0x97,0x92,0x92,0x12,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"苫\",2376*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0x00,0x88,0x44,0x22,0x11,0x88,0x00,0x00,0x0F,0x00,0x00,\n0x08,0x08,0x04,0x02,0x01,0x00,/*\"杉\",2377*/},{\n\n0x00,0xF8,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0xF8,0x00,0x00,0x07,0x04,0x04,0x04,\n0x07,0x04,0x04,0x04,0x0F,0x00,/*\"山\",2378*/},{\n\n0xFE,0x42,0xFE,0x42,0xFE,0x42,0xFE,0x40,0xFC,0x00,0xFF,0x0F,0x00,0x03,0x00,0x03,\n0x08,0x0F,0x00,0x01,0x08,0x0F,/*\"刪\",2379*/},{\n\n0x78,0x00,0xFF,0x08,0xFE,0xAA,0x2A,0xEB,0x8A,0x2A,0xEE,0x08,0x06,0x01,0x0A,0x07,\n0x02,0x09,0x0F,0x02,0x09,0x0F,/*\"煽\",2380*/},{\n\n0x84,0x45,0xF6,0x4C,0xA0,0x00,0x88,0x44,0x22,0x11,0x88,0x00,0x00,0x0F,0x00,0x00,\n0x08,0x08,0x04,0x02,0x01,0x00,/*\"衫\",2381*/},{\n\n0xFF,0x15,0x15,0x1F,0x00,0xE0,0x00,0x1F,0x15,0x15,0xFF,0x0F,0x00,0x00,0x02,0x01,\n0x00,0x01,0x02,0x00,0x08,0x0F,/*\"閃\",2382*/},{\n\n0xFE,0x02,0x32,0xCE,0x54,0x24,0x44,0xFF,0x54,0x24,0x44,0x0F,0x02,0x02,0x01,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"陝\",2383*/},{\n\n0x88,0xFF,0x48,0x00,0xFA,0x8A,0xBA,0xAB,0xBA,0x8A,0xFA,0x08,0x0F,0x00,0x00,0x08,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x08,/*\"擅\",2384*/},{\n\n0xFE,0x2A,0xFE,0x00,0xFE,0x15,0xAD,0xB5,0xA7,0xAC,0x14,0x09,0x05,0x09,0x08,0x07,\n0x00,0x0E,0x0A,0x0A,0x0E,0x00,/*\"贍\",2385*/},{\n\n0x00,0xFF,0x49,0xFF,0xA2,0xEB,0xAA,0xFE,0xAA,0xEB,0xA2,0x08,0x07,0x08,0x0F,0x00,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"膳\",2386*/},{\n\n0x82,0xAA,0xEA,0xAB,0xAA,0xFE,0xAA,0xAB,0xEA,0xAA,0x82,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"善\",2387*/},{\n\n0x10,0x21,0x02,0x00,0xF8,0x00,0x00,0xFF,0x00,0x00,0xF8,0x04,0x02,0x01,0x00,0x07,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"汕\",2388*/},{\n\n0x00,0xFE,0x2A,0xAA,0x2A,0xEA,0x0B,0x2A,0xAA,0x2A,0xEE,0x08,0x07,0x04,0x02,0x09,\n0x0F,0x00,0x04,0x02,0x09,0x0F,/*\"扇\",2389*/},{\n\n0xDC,0xB3,0xC8,0x00,0xA2,0xEB,0xAA,0xFE,0xAA,0xEB,0xA2,0x0E,0x00,0x06,0x00,0x00,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"繕\",2390*/},{\n\n0x10,0xFF,0x10,0x00,0xF2,0x56,0xBA,0x93,0xBA,0x56,0xF2,0x04,0x07,0x02,0x00,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"墒\",2391*/},{\n\n0x20,0x10,0xFC,0x03,0x84,0xFB,0xAA,0xAA,0xAA,0xFA,0x82,0x00,0x00,0x0F,0x00,0x04,\n0x0B,0x06,0x0A,0x06,0x0A,0x0E,/*\"傷\",2392*/},{\n\n0x02,0xF2,0x96,0x5A,0xB2,0x93,0xB2,0x5A,0x96,0xF2,0x02,0x00,0x0F,0x00,0x00,0x03,\n0x02,0x03,0x00,0x08,0x0F,0x00,/*\"商\",2393*/},{\n\n0x06,0xE2,0xBB,0xAA,0xAA,0xAB,0xAA,0xAA,0xBB,0xE2,0x06,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"賞\",2394*/},{\n\n0xFE,0x22,0xFE,0x00,0xFC,0x04,0xE6,0x25,0xE4,0x04,0xFC,0x07,0x02,0x07,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"晌\",2395*/},{\n\n0x00,0x00,0x00,0x00,0xFF,0x10,0x10,0x10,0x10,0x10,0x00,0x08,0x08,0x08,0x08,0x0F,\n0x08,0x08,0x08,0x08,0x08,0x08,/*\"上\",2396*/},{\n\n0x00,0xF2,0x14,0xD0,0x50,0x5F,0x50,0xD0,0x14,0xF2,0x00,0x00,0x0F,0x00,0x03,0x02,\n0x02,0x02,0x03,0x08,0x0F,0x00,/*\"尚\",2397*/},{\n\n0x0C,0x04,0x75,0x56,0x54,0xD7,0x54,0x56,0x75,0x04,0x0C,0x09,0x09,0x05,0x0D,0x0B,\n0x01,0x03,0x05,0x05,0x0B,0x09,/*\"裳\",2398*/},{\n\n0x88,0x68,0xFF,0x48,0x02,0xF4,0x50,0x5F,0x50,0x54,0xF2,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x01,0x01,0x01,0x09,0x0F,/*\"梢\",2399*/},{\n\n0x88,0xFF,0x48,0x00,0xF2,0x54,0x50,0x5F,0x50,0x54,0xF2,0x08,0x0F,0x00,0x00,0x0F,\n0x01,0x01,0x01,0x01,0x09,0x0F,/*\"捎\",2400*/},{\n\n0x12,0xD2,0xFE,0x91,0x02,0xF4,0x50,0x5F,0x50,0x54,0xF2,0x01,0x00,0x0F,0x00,0x00,\n0x0F,0x01,0x01,0x01,0x09,0x0F,/*\"稍\",2401*/},{\n\n0x78,0x00,0xFF,0x04,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x08,0x06,0x01,0x06,0x08,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"燒\",2402*/},{\n\n0x42,0x22,0x1A,0x97,0x12,0x12,0x12,0x17,0x12,0xF2,0x02,0x00,0x00,0x00,0x00,0x03,\n0x00,0x08,0x08,0x08,0x07,0x00,/*\"芍\",2403*/},{\n\n0x20,0x10,0x0C,0x07,0x44,0x84,0x04,0x04,0x04,0x04,0xFC,0x00,0x00,0x00,0x00,0x00,\n0x01,0x00,0x08,0x08,0x08,0x07,/*\"勺\",2404*/},{\n\n0xAA,0xB2,0xA3,0xB2,0xAA,0x40,0xA2,0x9E,0x82,0xA2,0xBE,0x0F,0x0A,0x0A,0x0A,0x0F,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"韶\",2405*/},{\n\n0x20,0x10,0x0C,0x00,0x00,0xFF,0x00,0x00,0x84,0x08,0x30,0x08,0x08,0x08,0x04,0x04,\n0x02,0x02,0x01,0x00,0x00,0x00,/*\"少\",2406*/},{\n\n0xFC,0x04,0xFC,0x00,0xF2,0x54,0x50,0x5F,0x50,0x54,0xF2,0x03,0x01,0x03,0x00,0x0F,\n0x01,0x01,0x01,0x01,0x09,0x0F,/*\"哨\",2407*/},{\n\n0x40,0xA2,0x9E,0x82,0xA2,0xBE,0x00,0xFE,0x02,0x32,0xCE,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x00,0x0F,0x02,0x02,0x01,/*\"邵\",2408*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x22,0x92,0x8E,0xA2,0xA2,0x9E,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"紹\",2409*/},{\n\n0x52,0x52,0x4A,0xDA,0x56,0x7B,0x56,0x6A,0xCA,0x52,0x52,0x02,0x02,0x01,0x0F,0x05,\n0x05,0x05,0x05,0x0F,0x00,0x00,/*\"奢\",2410*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x48,0x54,0x52,0xD1,0x52,0x54,0x48,0x09,0x05,0x05,0x09,0x04,\n0x03,0x08,0x0F,0x00,0x01,0x06,/*\"賒\",2411*/},{\n\n0xF8,0x88,0xFF,0x88,0xF8,0x0C,0xE4,0x05,0x86,0x44,0x2C,0x08,0x08,0x07,0x04,0x0E,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"蛇\",2412*/},{\n\n0x10,0x92,0x92,0x92,0x92,0xFE,0x91,0x91,0x91,0x91,0x10,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"舌\",2413*/},{\n\n0x48,0x48,0x54,0x54,0x52,0xF1,0x52,0x54,0x54,0x48,0x48,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"舍\",2414*/},{\n\n0x20,0xA4,0xE4,0x3F,0xE4,0x20,0x10,0xEF,0x08,0xF8,0x08,0x09,0x04,0x03,0x08,0x0F,\n0x01,0x08,0x04,0x03,0x04,0x08,/*\"赦\",2415*/},{\n\n0x84,0xFF,0x44,0xD1,0x5F,0xD5,0x55,0xD5,0x7F,0xC9,0x40,0x08,0x0F,0x04,0x07,0x05,\n0x0F,0x04,0x07,0x05,0x0F,0x02,/*\"攝\",2416*/},{\n\n0x80,0xFE,0xAB,0xAA,0xFE,0x00,0x48,0x88,0x08,0xFF,0x08,0x04,0x02,0x01,0x08,0x0F,\n0x00,0x00,0x09,0x08,0x0F,0x00,/*\"射\",2417*/},{\n\n0x30,0xFF,0x48,0xD1,0x5F,0xD5,0x55,0xD5,0x7F,0xC9,0x40,0x00,0x0F,0x04,0x07,0x05,\n0x0F,0x04,0x07,0x05,0x0F,0x02,/*\"懾\",2418*/},{\n\n0x10,0x22,0x04,0x10,0x9E,0x10,0x10,0xDF,0x12,0x12,0x90,0x04,0x02,0x01,0x0A,0x09,\n0x08,0x04,0x05,0x02,0x01,0x00,/*\"涉\",2419*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0x10,0x10,0xFF,0x10,0x10,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"社\",2420*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x50,0xCE,0x42,0x42,0xDE,0x10,0x0F,0x05,0x05,0x0F,0x00,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"設\",2421*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFC,0x24,0xFF,0x24,0x24,0xFC,0x00,0x07,0x02,0x07,0x00,\n0x03,0x01,0x0F,0x01,0x01,0x03,/*\"砷\",2422*/},{\n\n0x00,0xFC,0x24,0x24,0x24,0xFF,0x24,0x24,0x24,0xFC,0x00,0x00,0x03,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x03,0x00,/*\"申\",2423*/},{\n\n0xFC,0x04,0xFC,0x00,0xFC,0x24,0x24,0xFF,0x24,0x24,0xFC,0x03,0x01,0x03,0x00,0x03,\n0x01,0x01,0x0F,0x01,0x01,0x03,/*\"呻\",2424*/},{\n\n0x20,0x10,0xFC,0x03,0xFC,0x24,0x24,0xFF,0x24,0x24,0xFC,0x00,0x00,0x0F,0x00,0x03,\n0x01,0x01,0x0F,0x01,0x01,0x03,/*\"伸\",2425*/},{\n\n0x80,0x80,0xFE,0xAA,0xAB,0xAA,0xAA,0xAA,0xFE,0x40,0x20,0x04,0x04,0x04,0x02,0x02,\n0x01,0x09,0x08,0x0F,0x00,0x00,/*\"身\",2426*/},{\n\n0x22,0x44,0x06,0x52,0x4A,0x46,0xF2,0x46,0x4A,0x52,0x46,0x04,0x02,0x04,0x04,0x02,\n0x01,0x0F,0x01,0x02,0x04,0x04,/*\"深\",2427*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFE,0xE2,0x2A,0xEA,0x2A,0xA2,0x08,0x05,0x02,0x0D,0x07,\n0x00,0x0F,0x04,0x03,0x05,0x08,/*\"娠\",2428*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0xFC,0x24,0xFF,0x24,0xFC,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x03,0x01,0x0F,0x01,0x03,/*\"紳\",2429*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0xFC,0x24,0xFF,0x24,0x24,0xFC,0x00,0x00,0x0F,0x00,0x00,\n0x03,0x01,0x0F,0x01,0x01,0x03,/*\"神\",2430*/},{\n\n0x22,0x44,0x00,0x1C,0x04,0xC4,0x3F,0xC4,0x04,0x04,0x1C,0x04,0x02,0x08,0x04,0x03,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"沈\",2431*/},{\n\n0x26,0xAA,0xFA,0xAA,0xAA,0xFB,0xAA,0xAA,0xF6,0xA2,0x26,0x01,0x00,0x0F,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0F,0x00,0x01,/*\"審\",2432*/},{\n\n0x88,0x78,0x0F,0xF8,0x46,0xDA,0x4A,0xFB,0x46,0xD2,0x46,0x08,0x05,0x02,0x0D,0x01,\n0x0E,0x0A,0x0F,0x0A,0x0E,0x01,/*\"嬸\",2433*/},{\n\n0x82,0x82,0xFF,0xAA,0xAA,0xAA,0xAA,0xAA,0xFF,0x82,0x82,0x00,0x0F,0x08,0x0A,0x09,\n0x08,0x08,0x09,0x0A,0x08,0x00,/*\"甚\",2434*/},{\n\n0x3F,0xA5,0xA5,0xB7,0xAD,0x80,0xA1,0x97,0x89,0x95,0x23,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"腎\",2435*/},{\n\n0x78,0x00,0xFF,0x08,0x02,0xFA,0xAA,0xAF,0xAA,0xFA,0x02,0x00,0x00,0x0F,0x00,0x02,\n0x0B,0x06,0x02,0x06,0x0B,0x02,/*\"慎\",2436*/},{\n\n0x10,0x21,0x02,0x58,0x56,0xBB,0xA2,0x5A,0x37,0x52,0x58,0x04,0x02,0x01,0x00,0x0A,\n0x0A,0x0A,0x0A,0x05,0x04,0x02,/*\"滲\",2437*/},{\n\n0x82,0xFA,0xAA,0xBF,0xAA,0xBA,0x84,0xDB,0xA9,0xDB,0x82,0x04,0x04,0x07,0x05,0x06,\n0x04,0x05,0x06,0x0F,0x02,0x02,/*\"聲\",2438*/},{\n\n0x20,0x10,0x8E,0x88,0x88,0xFF,0x88,0x88,0x88,0x08,0x00,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"生\",2439*/},{\n\n0x20,0x5C,0x48,0xFF,0x48,0x08,0xBE,0xEA,0xBE,0xAA,0xBE,0x04,0x04,0x04,0x03,0x02,\n0x02,0x08,0x07,0x00,0x08,0x0F,/*\"甥\",2440*/},{\n\n0x9C,0x88,0xFF,0x48,0x20,0x9C,0x88,0xFF,0x88,0x88,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"牲\",2441*/},{\n\n0x20,0x22,0x22,0xFE,0x21,0x21,0x20,0x20,0xFF,0x20,0x20,0x00,0x08,0x06,0x01,0x00,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"升\",2442*/},{\n\n0xDC,0xB3,0xC8,0x00,0xF7,0x55,0xFF,0x01,0xFF,0x55,0xF7,0x0E,0x00,0x06,0x00,0x01,\n0x01,0x07,0x08,0x0F,0x09,0x0D,/*\"繩\",2443*/},{\n\n0x28,0x24,0xE2,0xB0,0xB0,0xAF,0xA8,0xA4,0xA2,0xE4,0x08,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"省\",2444*/},{\n\n0x80,0x7E,0x0A,0x0A,0x4A,0x7A,0x82,0x5F,0x22,0x53,0xEA,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盛\",2445*/},{\n\n0xA8,0xFA,0x0A,0xFE,0x09,0xF9,0xA8,0x00,0xFC,0x00,0xFF,0x04,0x02,0x01,0x0F,0x01,\n0x02,0x04,0x00,0x01,0x08,0x0F,/*\"剩\",2446*/},{\n\n0x00,0xFE,0x92,0xFE,0x50,0xB5,0xDC,0x97,0x94,0xB5,0x50,0x08,0x07,0x08,0x0F,0x08,\n0x04,0x03,0x08,0x08,0x07,0x00,/*\"勝\",2447*/},{\n\n0x11,0x9F,0x95,0x95,0x95,0xBF,0x89,0xBE,0xA2,0xA2,0x3E,0x08,0x08,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x08,0x08,/*\"聖\",2448*/},{\n\n0xFC,0xA6,0xBD,0x00,0xF2,0x12,0x12,0xFE,0x12,0x12,0xF2,0x0F,0x04,0x07,0x00,0x03,\n0x00,0x00,0x0F,0x00,0x02,0x03,/*\"師\",2449*/},{\n\n0xA0,0x90,0x8E,0x88,0x88,0xFF,0x88,0x88,0x88,0x80,0x80,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"失\",2450*/},{\n\n0x8A,0x44,0xFB,0x00,0xFE,0xA5,0xBC,0x12,0xFE,0x12,0xF2,0x08,0x08,0x07,0x00,0x0F,\n0x04,0x07,0x00,0x0F,0x02,0x03,/*\"獅\",2451*/},{\n\n0x04,0xFD,0x26,0xE4,0x44,0xF3,0x42,0xFE,0x22,0x12,0xF2,0x08,0x07,0x08,0x0F,0x00,\n0x07,0x08,0x0B,0x08,0x09,0x0D,/*\"施\",2452*/},{\n\n0x22,0x44,0x02,0xDA,0xB6,0xDA,0x02,0xDA,0xB6,0xDA,0x02,0x04,0x02,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"溼\",2453*/},{\n\n0x55,0x56,0x54,0x00,0x50,0x54,0x54,0x5F,0xF4,0x54,0x50,0x0F,0x05,0x0F,0x00,0x00,\n0x01,0x0A,0x08,0x0F,0x00,0x00,/*\"詩\",2454*/},{\n\n0x00,0xFF,0x95,0x75,0x55,0xD5,0x15,0xF5,0x15,0x95,0x57,0x08,0x07,0x08,0x05,0x02,\n0x01,0x00,0x07,0x09,0x08,0x0E,/*\"屍\",2455*/},{\n\n0x80,0x89,0xC9,0x89,0xBF,0x09,0x89,0x81,0xCF,0x90,0xB8,0x0B,0x0A,0x0F,0x0A,0x0B,\n0x00,0x0B,0x0A,0x0F,0x0A,0x0B,/*\"蝨\",2456*/},{\n\n0x20,0x20,0x20,0x20,0x20,0xFF,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"十\",2457*/},{\n\n0x02,0x82,0x42,0xF2,0x2E,0x22,0x22,0x22,0x22,0xE2,0x02,0x01,0x00,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"石\",2458*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0xA8,0xA4,0xA3,0xA4,0xA8,0x10,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"拾\",2459*/},{\n\n0xFE,0x22,0x22,0xFE,0x10,0x54,0x54,0x5F,0xF4,0x54,0x50,0x07,0x02,0x02,0x07,0x00,\n0x01,0x0A,0x08,0x0F,0x00,0x00,/*\"時\",2460*/},{\n\n0x20,0x10,0xFC,0x03,0x20,0x20,0x20,0xFF,0x20,0x20,0x20,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"什\",2461*/},{\n\n0x08,0x08,0xF4,0x54,0x52,0x59,0x52,0x54,0xF4,0x08,0x08,0x00,0x00,0x0F,0x09,0x05,\n0x01,0x03,0x05,0x05,0x0A,0x01,/*\"食\",2462*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x04,0xF8,0x88,0xFF,0x88,0xF8,0x00,0x0F,0x04,0x02,0x0C,\n0x00,0x08,0x08,0x0F,0x04,0x0E,/*\"蝕\",2463*/},{\n\n0x26,0xE2,0xBA,0xAA,0xAA,0xFB,0xAA,0xAA,0xAA,0xFA,0x26,0x00,0x00,0x07,0x0D,0x06,\n0x04,0x05,0x0E,0x07,0x00,0x00,/*\"實\",2464*/},{\n\n0x55,0x56,0x54,0x00,0xD6,0x5B,0xD6,0x10,0xFF,0x12,0xD4,0x0F,0x05,0x0F,0x00,0x0F,\n0x05,0x0F,0x04,0x03,0x05,0x0E,/*\"識\",2465*/},{\n\n0x00,0x7C,0x44,0x44,0x44,0xFF,0x44,0x44,0x44,0x7C,0x00,0x08,0x08,0x05,0x02,0x03,\n0x04,0x04,0x08,0x08,0x08,0x08,/*\"史\",2466*/},{\n\n0x50,0x48,0x47,0x44,0x44,0xFC,0x44,0x44,0x44,0x44,0x40,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"矢\",2467*/},{\n\n0x20,0x10,0xFC,0x03,0xF4,0x54,0x54,0xFF,0x54,0x54,0x74,0x00,0x00,0x0F,0x00,0x08,\n0x05,0x02,0x05,0x04,0x08,0x08,/*\"使\",2468*/},{\n\n0x00,0xFF,0x85,0x95,0xA5,0x85,0xF5,0x85,0xA5,0x95,0x87,0x08,0x07,0x04,0x02,0x01,\n0x00,0x0F,0x00,0x01,0x02,0x04,/*\"屎\",2469*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x00,0x7C,0x44,0xFF,0x44,0x7C,0x06,0x00,0x0A,0x08,0x07,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"駛\",2470*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xD8,0x54,0x53,0x50,0xD8,0x30,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"始\",2471*/},{\n\n0x08,0x48,0x48,0xC8,0x48,0x48,0x08,0xFF,0x08,0x09,0x0A,0x08,0x08,0x08,0x07,0x04,\n0x04,0x04,0x00,0x03,0x04,0x0E,/*\"式\",2472*/},{\n\n0x10,0x10,0x92,0x12,0x12,0xF2,0x12,0x12,0x92,0x10,0x10,0x04,0x02,0x01,0x00,0x08,\n0x0F,0x00,0x00,0x00,0x01,0x06,/*\"示\",2473*/},{\n\n0x10,0x10,0x10,0x10,0x10,0xFF,0x10,0x10,0x10,0x10,0x10,0x00,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x00,/*\"士\",2474*/},{\n\n0x10,0x10,0xFE,0x10,0x10,0xFF,0x10,0x10,0xFF,0x10,0x10,0x00,0x00,0x0F,0x08,0x08,\n0x09,0x09,0x09,0x09,0x08,0x08,/*\"世\",2475*/},{\n\n0x88,0x68,0xFF,0x48,0xE4,0x24,0x25,0xFE,0x24,0x24,0xE4,0x00,0x00,0x0F,0x00,0x07,\n0x00,0x00,0x0F,0x00,0x04,0x07,/*\"柿\",2476*/},{\n\n0x82,0xA2,0xAE,0xAA,0xAA,0xFF,0xAA,0xAA,0xAE,0xE2,0x82,0x00,0x02,0x02,0x02,0x0A,\n0x0F,0x02,0x02,0x02,0x03,0x00,/*\"事\",2477*/},{\n\n0x88,0x88,0xFF,0x48,0x24,0xE4,0x24,0x04,0xFF,0x04,0x05,0x00,0x08,0x0F,0x00,0x04,\n0x07,0x02,0x00,0x03,0x04,0x0E,/*\"拭\",2478*/},{\n\n0x8A,0xAA,0xBF,0x8A,0xE0,0x9E,0x8A,0x8A,0xB9,0x89,0x88,0x00,0x02,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x02,0x00,/*\"誓\",2479*/},{\n\n0x11,0xF2,0x48,0x48,0xFF,0x28,0x00,0xFE,0x12,0xF2,0x11,0x08,0x07,0x08,0x0A,0x0B,\n0x08,0x0A,0x09,0x08,0x0B,0x08,/*\"逝\",2480*/},{\n\n0x28,0x5A,0xEF,0x5A,0xA8,0x54,0x3F,0x44,0x3C,0x40,0xE0,0x09,0x09,0x05,0x03,0x01,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"勢\",2481*/},{\n\n0x40,0x40,0x5F,0x55,0x55,0xD5,0x55,0x55,0x5F,0x40,0x40,0x08,0x04,0x03,0x04,0x08,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"是\",2482*/},{\n\n0xFE,0x02,0xFE,0x48,0xAA,0x9A,0xBF,0xCA,0xEC,0xDA,0x68,0x03,0x01,0x03,0x00,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"嗜\",2483*/},{\n\n0xFC,0x04,0xFC,0x04,0x13,0xD6,0x12,0xF4,0x13,0xD6,0x12,0x03,0x01,0x03,0x0A,0x09,\n0x08,0x09,0x0F,0x09,0x08,0x09,/*\"噬\",2484*/},{\n\n0x10,0x11,0xF2,0x00,0xFA,0x0A,0xAE,0xFB,0xAE,0x0A,0xFA,0x08,0x04,0x03,0x04,0x0B,\n0x08,0x0B,0x0A,0x0B,0x08,0x0B,/*\"適\",2485*/},{\n\n0x20,0x10,0xFC,0x03,0x10,0x10,0x10,0xFF,0x10,0x10,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x04,0x04,0x07,0x04,0x04,0x00,/*\"仕\",2486*/},{\n\n0x20,0x10,0xFC,0x03,0x50,0x54,0x54,0x5F,0xF4,0x54,0x50,0x00,0x00,0x0F,0x00,0x00,\n0x01,0x0A,0x08,0x0F,0x00,0x00,/*\"侍\",2487*/},{\n\n0x4A,0x52,0xFE,0x51,0x4F,0x55,0xD7,0x7D,0xD7,0x55,0x47,0x02,0x01,0x0F,0x01,0x06,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"釋\",2488*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x04,0xE8,0x27,0xFC,0x24,0xE4,0x00,0x0F,0x04,0x02,0x04,\n0x00,0x03,0x00,0x0F,0x02,0x03,/*\"飾\",2489*/},{\n\n0x00,0xFE,0x22,0x22,0x22,0x22,0x7E,0xA1,0x21,0x21,0x20,0x00,0x0F,0x04,0x02,0x00,\n0x00,0x00,0x01,0x02,0x04,0x0F,/*\"氏\",2490*/},{\n\n0x04,0xE4,0x24,0x24,0x25,0xFE,0x24,0x24,0x24,0xE4,0x04,0x00,0x07,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x04,0x07,0x00,/*\"市\",2491*/},{\n\n0x78,0x00,0xFF,0x08,0x50,0x54,0x54,0x5F,0xF4,0x54,0x50,0x00,0x00,0x0F,0x00,0x00,\n0x01,0x0A,0x08,0x0F,0x00,0x00,/*\"恃\",2492*/},{\n\n0x1C,0x04,0x94,0xD4,0xB5,0x96,0x94,0xD4,0x94,0x04,0x1C,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"室\",2493*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0xFE,0xAA,0xAA,0xAA,0xFE,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"視\",2494*/},{\n\n0x55,0x56,0x54,0x00,0x24,0xE4,0x24,0x04,0xFF,0x04,0x05,0x0F,0x05,0x0F,0x00,0x04,\n0x07,0x02,0x00,0x03,0x04,0x0E,/*\"試\",2495*/},{\n\n0xFE,0x00,0x80,0xFF,0x20,0x10,0xEF,0x08,0x88,0x78,0x08,0x03,0x01,0x00,0x0F,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"收\",2496*/},{\n\n0x80,0x92,0x92,0x92,0x92,0xFE,0x91,0x91,0x91,0x91,0x80,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"手\",2497*/},{\n\n0x04,0xF4,0x55,0x56,0x54,0x5C,0x54,0x56,0x55,0xF4,0x04,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"首\",2498*/},{\n\n0x4C,0x44,0x44,0x44,0x45,0x46,0x44,0xF4,0x44,0x44,0x4C,0x00,0x00,0x01,0x02,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"守\",2499*/},{\n\n0x22,0xAA,0xAA,0xAA,0xAA,0xEF,0xAA,0xAA,0xAA,0x2A,0x62,0x0E,0x0A,0x0A,0x0E,0x00,\n0x02,0x06,0x02,0x0A,0x0F,0x02,/*\"壽\",2500*/},{\n\n0x88,0xFF,0x48,0x32,0xD6,0x5A,0x56,0x5A,0x52,0xD9,0x35,0x08,0x0F,0x00,0x08,0x08,\n0x05,0x02,0x02,0x05,0x08,0x08,/*\"授\",2501*/},{\n\n0x08,0xFC,0xAB,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0x82,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"售\",2502*/},{\n\n0x72,0x16,0xDA,0x52,0x56,0x5A,0x51,0x51,0xD9,0x15,0x71,0x08,0x08,0x04,0x05,0x02,\n0x02,0x02,0x05,0x04,0x08,0x08,/*\"受\",2503*/},{\n\n0x08,0xFE,0x02,0x7A,0x56,0x43,0xFE,0x42,0x56,0x7E,0x02,0x09,0x07,0x08,0x09,0x0B,\n0x05,0x05,0x05,0x05,0x0B,0x08,/*\"瘦\",2504*/},{\n\n0x07,0xFD,0xAF,0xF8,0xAF,0xFD,0x07,0x10,0xFF,0x12,0x14,0x02,0x0E,0x0A,0x0A,0x0A,\n0x0E,0x0A,0x07,0x00,0x07,0x08,/*\"獸\",2505*/},{\n\n0x92,0x12,0xD2,0xB7,0x02,0x92,0xD2,0xB7,0x9A,0xD2,0x92,0x0F,0x08,0x07,0x04,0x08,\n0x06,0x00,0x0E,0x00,0x0E,0x09,/*\"蔬\",2506*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x00,0x00,0x0F,0x00,0x0F,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"樞\",2507*/},{\n\n0x88,0x68,0xFF,0x48,0xA4,0x34,0xAD,0x26,0xA4,0x34,0x64,0x00,0x00,0x0F,0x08,0x07,\n0x00,0x07,0x00,0x07,0x08,0x0C,/*\"梳\",2508*/},{\n\n0x82,0x7E,0x92,0xF2,0x28,0x26,0xA4,0xFF,0xA4,0x24,0x20,0x08,0x04,0x02,0x01,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"殊\",2509*/},{\n\n0x88,0x88,0xFF,0x48,0x20,0x22,0x2A,0xF2,0x2A,0x26,0x60,0x00,0x08,0x0F,0x00,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"抒\",2510*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xE4,0xAA,0xE9,0x0A,0xE4,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x02,0x0F,0x08,0x0F,/*\"輸\",2511*/},{\n\n0x10,0x90,0x10,0xDF,0x92,0x12,0x00,0x7E,0x82,0x62,0x1E,0x02,0x01,0x08,0x0F,0x00,\n0x09,0x04,0x02,0x01,0x06,0x08,/*\"叔\",2512*/},{\n\n0xA4,0xAA,0xF9,0xAA,0xA4,0x00,0x22,0x2A,0xF2,0x2A,0x66,0x0F,0x04,0x04,0x04,0x0F,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"舒\",2513*/},{\n\n0x22,0x44,0x10,0x10,0xDF,0x14,0x12,0xFE,0x02,0xFE,0x00,0x04,0x02,0x02,0x09,0x0F,\n0x01,0x0A,0x04,0x03,0x04,0x08,/*\"淑\",2514*/},{\n\n0xE2,0x02,0xFA,0x46,0x00,0xA4,0x34,0xAD,0x26,0xB4,0x64,0x07,0x04,0x03,0x02,0x08,\n0x07,0x00,0x07,0x00,0x0F,0x08,/*\"疏\",2515*/},{\n\n0x88,0x88,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xBE,0x88,0x88,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"書\",2516*/},{\n\n0xFE,0x2A,0xFE,0x00,0x3A,0xEA,0xBA,0xAF,0xBA,0xEA,0x3A,0x09,0x05,0x09,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"贖\",2517*/},{\n\n0x02,0xBA,0xAA,0xAB,0xBA,0x02,0x24,0xFF,0x44,0xFC,0x00,0x02,0x02,0x0A,0x0E,0x03,\n0x0A,0x04,0x03,0x00,0x07,0x0C,/*\"孰\",2518*/},{\n\n0x82,0xAE,0xAB,0xAA,0xEE,0x82,0x24,0xFF,0x44,0xFC,0x00,0x08,0x04,0x02,0x07,0x08,\n0x02,0x05,0x08,0x00,0x05,0x0B,/*\"熟\",2519*/},{\n\n0x82,0xBA,0xAA,0xAF,0xFA,0xAA,0xBA,0xAF,0xAA,0xBA,0x82,0x04,0x02,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"薯\",2520*/},{\n\n0x80,0x8F,0xA9,0xA9,0xF9,0xAB,0xCD,0xA9,0x99,0x8F,0x80,0x04,0x04,0x02,0x0F,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"暑\",2521*/},{\n\n0xFE,0x22,0xFE,0x40,0x47,0xD5,0x7F,0x55,0x67,0xD5,0x47,0x07,0x02,0x07,0x02,0x01,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"曙\",2522*/},{\n\n0x40,0x47,0x55,0xD5,0x57,0x7D,0x57,0x65,0xDD,0x47,0x40,0x02,0x02,0x01,0x0F,0x05,\n0x05,0x05,0x05,0x0F,0x00,0x00,/*\"署\",2523*/},{\n\n0x40,0xE7,0x5D,0x55,0xF7,0x55,0x57,0xD5,0x15,0x17,0xF0,0x04,0x05,0x05,0x05,0x07,\n0x05,0x05,0x05,0x0E,0x08,0x07,/*\"蜀\",2524*/},{\n\n0x88,0xA8,0x5A,0x4A,0x2A,0x9E,0x29,0x49,0x59,0xA8,0x88,0x00,0x08,0x05,0x02,0x08,\n0x0F,0x00,0x02,0x05,0x08,0x00,/*\"黍\",2525*/},{\n\n0x00,0xFE,0xAA,0x2A,0x29,0xE0,0xAA,0x2A,0xEA,0x3E,0x00,0x00,0x0F,0x0A,0x00,0x00,\n0x0F,0x0A,0x00,0x03,0x04,0x0E,/*\"鼠\",2526*/},{\n\n0x00,0xFF,0x45,0xED,0x55,0xC5,0x7D,0xC5,0x55,0x6D,0xC7,0x08,0x07,0x04,0x05,0x05,\n0x07,0x05,0x05,0x04,0x08,0x0F,/*\"屬\",2527*/},{\n\n0x24,0xF2,0x09,0x10,0xD0,0xFF,0x52,0x84,0x12,0xF2,0x12,0x00,0x0F,0x00,0x01,0x00,\n0x0F,0x00,0x00,0x08,0x0F,0x00,/*\"術\",2528*/},{\n\n0x10,0x11,0xF2,0x00,0x88,0x48,0x28,0xFF,0x28,0x49,0x8A,0x08,0x04,0x03,0x04,0x08,\n0x08,0x08,0x0B,0x08,0x08,0x08,/*\"述\",2529*/},{\n\n0xC8,0xFF,0x48,0x02,0xEA,0xAF,0xEA,0x42,0x88,0xFF,0x08,0x00,0x0F,0x00,0x08,0x0A,\n0x04,0x06,0x04,0x08,0x0F,0x00,/*\"樹\",2530*/},{\n\n0x02,0x7A,0x4A,0x4A,0xCA,0xFF,0xCA,0x4A,0x4A,0x7A,0x02,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"束\",2531*/},{\n\n0x00,0xF8,0x48,0x88,0x08,0x08,0xFF,0x08,0x89,0x6A,0x08,0x08,0x07,0x00,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x0F,/*\"戍\",2532*/},{\n\n0xBF,0xA5,0xA5,0xB7,0xAD,0x80,0xA3,0x95,0x89,0x95,0xA3,0x08,0x0B,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x0B,0x08,/*\"豎\",2533*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x00,0x11,0x95,0xF9,0x17,0x30,0x09,0x09,0x09,0x0B,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x08,0x08,/*\"墅\",2534*/},{\n\n0x00,0xFE,0x22,0x22,0xFA,0x22,0x23,0x22,0xFA,0x22,0x22,0x08,0x07,0x08,0x04,0x01,\n0x05,0x09,0x05,0x09,0x04,0x08,/*\"庶\",2535*/},{\n\n0x88,0xBE,0xAA,0xFF,0xAA,0xBE,0x08,0x10,0xEF,0x08,0xF8,0x08,0x0A,0x0B,0x04,0x06,\n0x09,0x00,0x08,0x04,0x03,0x0C,/*\"數\",2536*/},{\n\n0x22,0x44,0x74,0x54,0xFF,0x54,0x74,0x08,0xE7,0x04,0x1C,0x04,0x02,0x04,0x02,0x0F,\n0x01,0x0A,0x06,0x01,0x06,0x08,/*\"漱\",2537*/},{\n\n0x84,0x5C,0x27,0x24,0x5C,0x00,0x7E,0x42,0x42,0x7E,0x00,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"恕\",2538*/},{\n\n0x00,0xFF,0xC9,0x49,0xF9,0x49,0xCF,0x00,0xFC,0x00,0xFF,0x01,0x00,0x07,0x00,0x0F,\n0x04,0x07,0x00,0x01,0x08,0x0F,/*\"刷\",2539*/},{\n\n0x02,0x7A,0x0A,0x0A,0xBA,0x0E,0x3A,0x0A,0x4A,0x7A,0x02,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"耍\",2540*/},{\n\n0x88,0x88,0xFF,0x48,0x52,0x22,0xDA,0xB7,0xDA,0x22,0x52,0x00,0x08,0x0F,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"摔\",2541*/},{\n\n0x22,0x22,0xFA,0xAA,0xAA,0xAB,0xAA,0xAA,0xFA,0x22,0x22,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"衰\",2542*/},{\n\n0x00,0xFF,0x49,0x49,0x49,0xFF,0x49,0x49,0x49,0xFF,0x00,0x04,0x03,0x00,0x00,0x00,\n0x07,0x08,0x0A,0x0A,0x0B,0x0C,/*\"甩\",2543*/},{\n\n0xFC,0xA6,0xBD,0x00,0xFC,0x04,0x04,0xFF,0x04,0x04,0xFC,0x0F,0x04,0x07,0x00,0x03,\n0x00,0x00,0x0F,0x00,0x02,0x03,/*\"帥\",2544*/},{\n\n0x88,0x68,0xFF,0x48,0x10,0x28,0x24,0xE3,0x24,0x28,0x10,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"栓\",2545*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0x28,0x24,0xE3,0x24,0x28,0x10,0x00,0x08,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"拴\",2546*/},{\n\n0x4C,0x45,0xF5,0x4D,0x45,0xEF,0xA5,0xAD,0xA5,0xA5,0xEC,0x02,0x01,0x0F,0x01,0x02,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x0F,/*\"霜\",2547*/},{\n\n0x04,0xFF,0xAA,0xBF,0xAA,0x84,0xFE,0xAB,0xBE,0x2B,0x2A,0x08,0x08,0x09,0x0A,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x08,/*\"雙\",2548*/},{\n\n0x02,0x56,0x8A,0x56,0x02,0xFF,0x02,0x56,0x8A,0x56,0x02,0x08,0x09,0x04,0x05,0x02,\n0x01,0x02,0x05,0x04,0x09,0x08,/*\"爽\",2549*/},{\n\n0x54,0x55,0x56,0x54,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"誰\",2550*/},{\n\n0x00,0x08,0x88,0x78,0x00,0xFF,0x18,0x60,0x90,0x08,0x04,0x04,0x02,0x01,0x08,0x08,\n0x0F,0x00,0x00,0x01,0x02,0x04,/*\"水\",2551*/},{\n\n0xFE,0x92,0xFE,0x40,0x48,0xFA,0x4A,0xFE,0x49,0xF9,0x48,0x0F,0x04,0x0F,0x00,0x02,\n0x0B,0x0A,0x0F,0x0A,0x0B,0x02,/*\"睡\",2552*/},{\n\n0x12,0xD2,0xFE,0x91,0x04,0xFA,0x89,0x88,0x89,0xFA,0x04,0x01,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"稅\",2553*/},{\n\n0xFC,0x04,0xFC,0x10,0x18,0xF4,0x13,0xF0,0x14,0x38,0x00,0x03,0x01,0x03,0x08,0x04,\n0x03,0x00,0x07,0x08,0x08,0x0E,/*\"吮\",2554*/},{\n\n0xFE,0x92,0xFE,0x00,0x36,0xDA,0x96,0x1A,0x91,0xD9,0xB5,0x0F,0x04,0x0F,0x00,0x09,\n0x06,0x01,0x03,0x02,0x0F,0x02,/*\"瞬\",2555*/},{\n\n0x00,0xFF,0x00,0xFE,0x00,0xFF,0x00,0xFA,0xAE,0xAA,0xFA,0x08,0x07,0x00,0x07,0x00,\n0x0F,0x00,0x0B,0x06,0x06,0x0B,/*\"順\",2556*/},{\n\n0x32,0x96,0x7A,0x52,0xD6,0x1A,0x51,0x51,0xF9,0x55,0x31,0x01,0x08,0x05,0x02,0x01,\n0x00,0x03,0x02,0x0F,0x02,0x02,/*\"舜\",2557*/},{\n\n0x54,0x55,0x56,0x54,0x04,0xFA,0x89,0x88,0x89,0xFA,0x04,0x0F,0x05,0x05,0x0F,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"說\",2558*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFA,0xAA,0xAE,0xAA,0xAA,0xFA,0x00,0x07,0x02,0x07,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"碩\",2559*/},{\n\n0x08,0xE9,0x8A,0xF8,0x8A,0xE9,0x00,0xFE,0x92,0x92,0xFE,0x00,0x08,0x04,0x03,0x00,\n0x01,0x08,0x07,0x00,0x08,0x0F,/*\"朔\",2560*/},{\n\n0x78,0x00,0xFF,0x08,0xB6,0xAD,0xBE,0xEB,0xBE,0x94,0xAB,0x08,0x06,0x01,0x02,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"爍\",2561*/},{\n\n0x04,0xFF,0x54,0x54,0xFF,0x04,0xFE,0x12,0x12,0xF1,0x10,0x09,0x05,0x01,0x01,0x05,\n0x09,0x07,0x00,0x00,0x0F,0x00,/*\"斯\",2562*/},{\n\n0x84,0xFF,0x44,0xFF,0x54,0xFF,0x04,0xFE,0x12,0xF2,0x11,0x08,0x0F,0x09,0x05,0x01,\n0x05,0x09,0x07,0x00,0x0F,0x00,/*\"撕\",2563*/},{\n\n0xFE,0x02,0xFE,0x04,0xFF,0x54,0xFF,0x04,0xFE,0x12,0xF1,0x03,0x01,0x03,0x09,0x05,\n0x01,0x05,0x09,0x07,0x00,0x0F,/*\"嘶\",2564*/},{\n\n0x00,0x7F,0x49,0x49,0x49,0xFF,0x49,0x49,0x49,0x7F,0x00,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"思\",2565*/},{\n\n0x10,0x92,0x52,0xFE,0x51,0x90,0x00,0xE0,0x1F,0x00,0x00,0x01,0x00,0x00,0x0F,0x00,\n0x04,0x06,0x05,0x04,0x05,0x0E,/*\"私\",2566*/},{\n\n0x08,0xEA,0x2A,0x2A,0x2A,0x2A,0xEA,0x0A,0x02,0xFE,0x00,0x00,0x07,0x02,0x02,0x02,\n0x02,0x0B,0x08,0x08,0x07,0x00,/*\"司\",2567*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0x4C,0x6A,0xD9,0x48,0x64,0x0E,0x00,0x06,0x00,0x06,\n0x04,0x03,0x08,0x0F,0x01,0x06,/*\"絲\",2568*/},{\n\n0x42,0x22,0x5E,0x92,0x72,0x02,0xFE,0x82,0x42,0x22,0x12,0x08,0x04,0x02,0x01,0x00,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"死\",2569*/},{\n\n0x80,0xFE,0xAA,0xAA,0x00,0xAA,0xAA,0xFF,0xAA,0xBE,0x08,0x06,0x05,0x04,0x06,0x0C,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"肆\",2570*/},{\n\n0x90,0x92,0x92,0x92,0x92,0x9F,0x92,0xF2,0x92,0x92,0x90,0x00,0x00,0x01,0x02,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"寺\",2571*/},{\n\n0xF7,0x95,0xF5,0x95,0xF7,0x00,0xF5,0x15,0xF5,0x01,0xFF,0x0F,0x00,0x07,0x08,0x0F,\n0x00,0x03,0x01,0x09,0x08,0x07,/*\"嗣\",2572*/},{\n\n0x00,0xFE,0x02,0x82,0x7E,0x02,0x02,0x7E,0x82,0x82,0xFE,0x00,0x0F,0x05,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"四\",2573*/},{\n\n0x10,0xFC,0x03,0x08,0xEA,0x2A,0x2A,0x2A,0xEA,0x02,0xFE,0x00,0x0F,0x00,0x00,0x03,\n0x01,0x01,0x09,0x09,0x08,0x07,/*\"伺\",2574*/},{\n\n0x10,0xFC,0x03,0x00,0xFE,0x00,0x82,0x0C,0xE0,0x1F,0x00,0x00,0x0F,0x00,0x00,0x03,\n0x09,0x04,0x03,0x00,0x03,0x0C,/*\"似\",2575*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0xEA,0x2A,0x2A,0xEA,0x02,0xFE,0x00,0x0F,0x04,0x02,0x04,\n0x03,0x01,0x01,0x09,0x08,0x07,/*\"飼\",2576*/},{\n\n0x00,0xFE,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x7E,0x00,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"巳\",2577*/},{\n\n0x88,0x68,0xFF,0x48,0x20,0x18,0x87,0x60,0x07,0x18,0x20,0x00,0x00,0x0F,0x00,0x00,\n0x06,0x05,0x04,0x05,0x0E,0x00,/*\"松\",2578*/},{\n\n0x94,0xBA,0x85,0xA0,0x9A,0xA1,0xA2,0xBC,0xAA,0xA9,0xA2,0x04,0x04,0x07,0x05,0x06,\n0x04,0x05,0x06,0x0F,0x02,0x02,/*\"聳\",2579*/},{\n\n0x24,0x72,0x09,0x40,0x34,0xC3,0x44,0x78,0x54,0x53,0x44,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"慫\",2580*/},{\n\n0x18,0x86,0x60,0x03,0x1C,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x06,0x05,0x04,0x05,0x0E,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頌\",2581*/},{\n\n0x11,0xF2,0x40,0x48,0x49,0x4A,0xF8,0x4A,0x49,0x48,0x40,0x08,0x07,0x08,0x0C,0x0A,\n0x09,0x08,0x09,0x0A,0x0C,0x08,/*\"送\",2582*/},{\n\n0x4C,0x44,0x44,0x44,0xC5,0xF6,0xC4,0x44,0x44,0x44,0x4C,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"宋\",2583*/},{\n\n0x54,0x55,0x56,0x54,0x20,0x18,0x87,0x60,0x07,0x18,0x20,0x0F,0x05,0x05,0x0F,0x00,\n0x06,0x05,0x04,0x05,0x0E,0x00,/*\"訟\",2584*/},{\n\n0x55,0x56,0x54,0x00,0xF1,0x51,0x55,0xF9,0x55,0x53,0xF0,0x0F,0x05,0x0F,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"誦\",2585*/},{\n\n0x88,0x88,0xFF,0x48,0xBC,0xAA,0xA0,0xFF,0xA0,0xAA,0xBE,0x00,0x08,0x0F,0x00,0x08,\n0x09,0x0A,0x04,0x04,0x0A,0x09,/*\"搜\",2586*/},{\n\n0x20,0xFE,0xAB,0xFE,0x00,0xBC,0xAA,0xFF,0xA0,0xAA,0xBE,0x08,0x07,0x08,0x0F,0x00,\n0x08,0x09,0x06,0x04,0x0A,0x09,/*\"艘\",2587*/},{\n\n0x88,0xFF,0x48,0xBE,0xAA,0xFF,0xAA,0x3E,0xE8,0x07,0xFC,0x08,0x0F,0x00,0x0A,0x0B,\n0x04,0x0B,0x08,0x04,0x03,0x0C,/*\"擻\",2588*/},{\n\n0xFE,0x02,0xFE,0x54,0xFF,0x54,0x74,0x08,0xE7,0x04,0x1C,0x03,0x01,0x05,0x02,0x0F,\n0x01,0x0A,0x06,0x01,0x06,0x08,/*\"嗽\",2589*/},{\n\n0x12,0xEE,0xAA,0xEF,0xBA,0xE2,0x52,0x57,0xF2,0x4A,0x4A,0x08,0x03,0x0A,0x03,0x0A,\n0x03,0x0A,0x01,0x0F,0x01,0x02,/*\"蘇\",2590*/},{\n\n0xFA,0x4A,0x3E,0x0A,0x3E,0x4A,0xFA,0x10,0x92,0xFE,0x91,0x0F,0x05,0x05,0x05,0x05,\n0x05,0x0F,0x01,0x00,0x0F,0x00,/*\"酥\",2591*/},{\n\n0x20,0x10,0xFC,0x03,0x44,0xA2,0x91,0x8C,0x91,0xA2,0x44,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"俗\",2592*/},{\n\n0x22,0x2A,0xAA,0xEA,0xAA,0xBF,0xAA,0x6A,0x2A,0x2A,0x22,0x00,0x0A,0x06,0x02,0x0B,\n0x0E,0x02,0x02,0x07,0x0A,0x00,/*\"素\",2593*/},{\n\n0x11,0xF2,0x00,0x7A,0x4A,0xCA,0xFF,0xCA,0x4A,0x7A,0x02,0x08,0x07,0x08,0x0A,0x09,\n0x08,0x0F,0x08,0x09,0x0A,0x08,/*\"速\",2594*/},{\n\n0x01,0x3D,0x65,0xA5,0x3F,0xE5,0x3F,0xA5,0x65,0x3D,0x01,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"粟\",2595*/},{\n\n0x20,0x10,0xFC,0x03,0x1D,0x55,0x1F,0xF5,0x1F,0x55,0x1D,0x00,0x00,0x0F,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"僳\",2596*/},{\n\n0x84,0xB5,0x66,0x3C,0x26,0xB5,0x40,0x3F,0x15,0x95,0xFF,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"塑\",2597*/},{\n\n0x22,0x44,0xE9,0x8A,0xF8,0x8A,0xE9,0x00,0xFE,0x92,0xFE,0x04,0x02,0x08,0x04,0x03,\n0x00,0x00,0x08,0x07,0x08,0x0F,/*\"溯\",2598*/},{\n\n0x4C,0xE4,0x14,0xD4,0x55,0x76,0x54,0x54,0x54,0xD4,0x0C,0x00,0x0F,0x00,0x0F,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"宿\",2599*/},{\n\n0x54,0x55,0x56,0x54,0x00,0xFE,0x12,0x92,0xF1,0x11,0x10,0x0F,0x05,0x05,0x0F,0x08,\n0x07,0x00,0x00,0x0F,0x01,0x02,/*\"訴\",2600*/},{\n\n0x08,0xC8,0xAA,0xEA,0x2A,0xFF,0x2A,0xEA,0xBE,0xC8,0x08,0x08,0x07,0x02,0x0E,0x00,\n0x0F,0x00,0x0E,0x02,0x0F,0x00,/*\"肅\",2601*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x20,0x96,0x65,0x44,0xD6,0x2C,0x0F,0x05,0x05,0x05,0x0F,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"酸\",2602*/},{\n\n0x42,0x52,0xD2,0x57,0x42,0x02,0x42,0x57,0xD2,0x52,0x42,0x02,0x09,0x0F,0x01,0x02,\n0x00,0x02,0x09,0x0F,0x01,0x02,/*\"蒜\",2603*/},{\n\n0x04,0x03,0xFA,0xAE,0xAA,0xA8,0xAC,0xAB,0xFA,0x06,0x02,0x02,0x02,0x0B,0x06,0x02,\n0x02,0x02,0x0E,0x03,0x02,0x02,/*\"算\",2604*/},{\n\n0xF0,0x97,0xFD,0x97,0xF0,0x10,0xFC,0x27,0xFC,0x25,0x24,0x04,0x04,0x07,0x04,0x0E,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"雖\",2605*/},{\n\n0xFF,0x31,0xCF,0x00,0x2A,0xE6,0xAB,0xBA,0xAA,0xEA,0x22,0x0F,0x02,0x01,0x00,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"隋\",2606*/},{\n\n0xFE,0x32,0xCE,0x48,0xD0,0x2A,0xEE,0xBB,0xAA,0xEA,0x22,0x0F,0x02,0x01,0x08,0x07,\n0x08,0x0B,0x08,0x0A,0x0B,0x08,/*\"隨\",2607*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x4A,0xD2,0x66,0x4A,0xD1,0x4D,0x0C,0x02,0x04,0x02,0x04,\n0x08,0x05,0x02,0x02,0x05,0x08,/*\"綏\",2608*/},{\n\n0x18,0xEF,0xA9,0xEF,0x58,0xD0,0x2A,0xEE,0xBB,0xAA,0xEA,0x00,0x0F,0x02,0x0F,0x08,\n0x07,0x08,0x0B,0x08,0x0A,0x0B,/*\"髓\",2609*/},{\n\n0x42,0xF2,0x2E,0xE2,0x24,0x1C,0x25,0x86,0x24,0x1C,0x24,0x00,0x07,0x02,0x07,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"碎\",2610*/},{\n\n0x04,0xF4,0x57,0x54,0xD4,0x57,0x55,0xFD,0x15,0x1D,0xD4,0x08,0x07,0x0A,0x09,0x07,\n0x02,0x09,0x05,0x02,0x05,0x0E,/*\"歲\",2611*/},{\n\n0x12,0xD2,0xFE,0x51,0x82,0xFA,0xAA,0xFF,0xAA,0xFA,0x82,0x01,0x00,0x0F,0x00,0x08,\n0x04,0x0D,0x0A,0x0C,0x02,0x0C,/*\"穗\",2612*/},{\n\n0x11,0xF2,0x00,0xA4,0x95,0x4E,0xB4,0xE4,0x46,0xA5,0x14,0x08,0x07,0x08,0x0A,0x0A,\n0x0D,0x0C,0x0B,0x08,0x08,0x0B,/*\"遂\",2613*/},{\n\n0xFF,0x31,0xCF,0x22,0xE4,0xA5,0x56,0xAC,0xF6,0xA5,0x14,0x0F,0x02,0x01,0x08,0x07,\n0x0A,0x09,0x0A,0x0B,0x08,0x09,/*\"隧\",2614*/},{\n\n0x18,0x56,0x54,0x54,0x54,0x5F,0x54,0x54,0x54,0x56,0x18,0x01,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x01,/*\"祟\",2615*/},{\n\n0x82,0x82,0xF2,0x4E,0x80,0x92,0xDA,0xB6,0x91,0xC9,0x80,0x00,0x08,0x0F,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x05,/*\"孫\",2616*/},{\n\n0x88,0x88,0xFF,0x48,0xF0,0x57,0x55,0x55,0x55,0x57,0xF0,0x00,0x08,0x0F,0x00,0x07,\n0x0D,0x05,0x05,0x05,0x0D,0x07,/*\"損\",2617*/},{\n\n0x44,0x23,0xDA,0x56,0x52,0x50,0x54,0xD3,0x12,0x16,0xF2,0x00,0x00,0x0F,0x05,0x05,\n0x05,0x05,0x0F,0x08,0x08,0x07,/*\"筍\",2618*/},{\n\n0x4A,0x4A,0xFA,0x5F,0x5A,0x5E,0x5A,0x5F,0xFA,0x4A,0x4A,0x08,0x08,0x05,0x03,0x0F,\n0x09,0x03,0x05,0x05,0x0A,0x08,/*\"蓑\",2619*/},{\n\n0x88,0x68,0xFF,0x48,0x24,0x96,0x65,0x44,0x44,0xD6,0x2C,0x00,0x00,0x0F,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"梭\",2620*/},{\n\n0xFE,0x02,0xFE,0x00,0x24,0x96,0x65,0x44,0x44,0xD6,0x2C,0x03,0x01,0x03,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"唆\",2621*/},{\n\n0xD8,0xB4,0x93,0xC8,0x26,0xF2,0x0A,0xD3,0x72,0x52,0xD6,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x00,0x0F,0x05,0x05,0x0F,/*\"縮\",2622*/},{\n\n0x22,0xFE,0x22,0x00,0xF9,0xAA,0xA8,0xAF,0xA8,0xAA,0xF9,0x04,0x07,0x02,0x00,0x0B,\n0x06,0x02,0x02,0x02,0x06,0x0B,/*\"瑣\",2623*/},{\n\n0x18,0x0A,0x4A,0x6A,0xDA,0x4F,0x4A,0x2A,0x8A,0x0A,0x18,0x00,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x00,/*\"索\",2624*/},{\n\n0x4A,0xF9,0x4A,0x00,0xF9,0xAA,0xA8,0xAF,0xA8,0xAA,0xF9,0x0A,0x0F,0x05,0x00,0x0B,\n0x06,0x02,0x02,0x02,0x06,0x0B,/*\"鎖\",2625*/},{\n\n0x00,0xFE,0x92,0x92,0xF1,0x00,0xFE,0x12,0x12,0xF1,0x11,0x08,0x07,0x00,0x00,0x09,\n0x04,0x03,0x00,0x00,0x0F,0x00,/*\"所\",2626*/},{\n\n0x10,0xFF,0x10,0x00,0x40,0x5F,0xD5,0x15,0x55,0x5F,0xC0,0x04,0x07,0x02,0x00,0x05,\n0x0A,0x0F,0x00,0x05,0x0A,0x0F,/*\"塌\",2627*/},{\n\n0x20,0x10,0xFC,0x03,0x20,0xFC,0x10,0xFF,0x08,0x84,0xFC,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x08,0x09,0x08,0x08,0x0E,/*\"他\",2628*/},{\n\n0x1C,0x04,0xF4,0x84,0x85,0x46,0x44,0x24,0x24,0x04,0x1C,0x00,0x00,0x07,0x08,0x08,\n0x08,0x08,0x08,0x08,0x0E,0x00,/*\"它\",2629*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0xFC,0x10,0xFF,0x08,0x84,0xFC,0x08,0x05,0x02,0x0D,0x00,\n0x07,0x08,0x09,0x08,0x08,0x0E,/*\"她\",2630*/},{\n\n0x10,0x10,0xFF,0x10,0x42,0x27,0x52,0x4A,0x52,0x27,0x42,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"塔\",2631*/},{\n\n0x8A,0xFC,0x03,0xF4,0x94,0xFF,0x94,0xF4,0xFB,0xAE,0xF8,0x08,0x07,0x00,0x04,0x02,\n0x0F,0x02,0x04,0x0B,0x06,0x0B,/*\"獺\",2632*/},{\n\n0x88,0xFF,0x48,0x21,0xE2,0x08,0xAA,0xBA,0xEF,0xBA,0xAA,0x08,0x0F,0x00,0x08,0x07,\n0x0A,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"撻\",2633*/},{\n\n0x9E,0x12,0xF2,0x9E,0x40,0x5F,0xD5,0x15,0x55,0x5F,0xC0,0x0F,0x08,0x07,0x04,0x05,\n0x0A,0x0F,0x00,0x05,0x0A,0x0F,/*\"蹋\",2634*/},{\n\n0x9E,0x12,0xFE,0x80,0xD2,0x4E,0x50,0x5F,0x42,0x4C,0xD2,0x0F,0x08,0x07,0x04,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"踏\",2635*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xD8,0x54,0x53,0x50,0xD8,0x30,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"胎\",2636*/},{\n\n0x22,0xB2,0xAA,0xA7,0xA2,0xA2,0xA2,0xA7,0xA2,0xB2,0x62,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"苔\",2637*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0xD8,0x54,0x53,0x50,0xD8,0x30,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"抬\",2638*/},{\n\n0x62,0xAA,0xBA,0xAA,0xAA,0xAF,0xAA,0xAA,0xBA,0xAA,0x62,0x08,0x0A,0x0B,0x0A,0x0A,\n0x0E,0x0A,0x0A,0x0B,0x0A,0x08,/*\"臺\",2639*/},{\n\n0x20,0xA2,0x6A,0x3A,0x2E,0xEB,0x2A,0x2A,0x6A,0xA2,0x20,0x09,0x08,0x05,0x02,0x09,\n0x0F,0x01,0x02,0x05,0x08,0x09,/*\"泰\",2640*/},{\n\n0xFD,0xA5,0x9F,0xA5,0xFD,0x08,0xC8,0x3F,0xC8,0x08,0x08,0x0F,0x04,0x04,0x04,0x0F,\n0x06,0x01,0x06,0x01,0x06,0x08,/*\"酞\",2641*/},{\n\n0x08,0x08,0x08,0x88,0x68,0x1F,0xE8,0x08,0x08,0x08,0x08,0x08,0x04,0x02,0x01,0x02,\n0x04,0x00,0x03,0x04,0x08,0x08,/*\"太\",2642*/},{\n\n0x04,0xF6,0x55,0x54,0x56,0xF4,0x00,0xE7,0x4A,0x29,0x8C,0x08,0x05,0x00,0x04,0x0B,\n0x0D,0x08,0x0C,0x01,0x05,0x09,/*\"態\",2643*/},{\n\n0x10,0x21,0x0A,0x08,0x08,0xE8,0x1F,0xE8,0x08,0x08,0x08,0x04,0x02,0x09,0x04,0x03,\n0x02,0x04,0x00,0x03,0x04,0x08,/*\"汰\",2644*/},{\n\n0x08,0x08,0xFF,0x08,0x40,0xFE,0x4A,0x52,0x42,0xFE,0x40,0x02,0x02,0x01,0x09,0x04,\n0x03,0x00,0x00,0x08,0x0F,0x00,/*\"坍\",2645*/},{\n\n0x88,0xFF,0x48,0xE2,0xAF,0xFA,0xAF,0xFC,0x27,0xFC,0x25,0x08,0x0F,0x00,0x0A,0x0A,\n0x07,0x0A,0x0F,0x09,0x0F,0x09,/*\"攤\",2646*/},{\n\n0x08,0xC8,0x54,0xD4,0x52,0x59,0xD2,0x74,0x54,0xC8,0x08,0x00,0x0B,0x06,0x02,0x03,\n0x02,0x02,0x03,0x06,0x0B,0x00,/*\"貪\",2647*/},{\n\n0x10,0xFE,0xEA,0xBE,0xEA,0xBE,0xEB,0xF2,0x5E,0xF6,0x5A,0x09,0x07,0x0A,0x06,0x03,\n0x06,0x0A,0x0F,0x05,0x07,0x05,/*\"癱\",2648*/},{\n\n0x22,0x44,0xE2,0xAF,0xFA,0xAF,0xF2,0xFC,0x27,0xFC,0x25,0x04,0x02,0x0A,0x0A,0x07,\n0x0A,0x02,0x0F,0x09,0x0F,0x09,/*\"灘\",2649*/},{\n\n0x10,0xFF,0x10,0x00,0xFA,0x8A,0xBA,0xAB,0xBA,0x8A,0xFA,0x04,0x07,0x02,0x00,0x08,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x08,/*\"壇\",2650*/},{\n\n0x88,0x68,0xFF,0x48,0xFA,0x8A,0xBA,0xAB,0xBA,0x8A,0xFA,0x00,0x00,0x0F,0x00,0x08,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x08,/*\"檀\",2651*/},{\n\n0x08,0x90,0xFE,0x22,0x1A,0x42,0x23,0x9A,0x22,0x52,0x8A,0x09,0x04,0x03,0x04,0x0B,\n0x08,0x04,0x03,0x04,0x09,0x08,/*\"痰\",2652*/},{\n\n0x11,0x22,0x1C,0xF5,0x55,0x5F,0x55,0x5F,0x55,0xF5,0x1C,0x04,0x02,0x04,0x05,0x05,\n0x05,0x0F,0x05,0x05,0x05,0x04,/*\"潭\",2653*/},{\n\n0x55,0x56,0x54,0x00,0x1D,0xF5,0x5F,0x55,0x5F,0xF5,0x1D,0x0F,0x05,0x0F,0x00,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"譚\",2654*/},{\n\n0x55,0x56,0x54,0x00,0x28,0xA6,0x10,0xCF,0x10,0x14,0xA2,0x0F,0x05,0x0F,0x00,0x09,\n0x04,0x02,0x01,0x02,0x05,0x08,/*\"談\",2655*/},{\n\n0x10,0xFF,0x10,0x00,0xFE,0x12,0x12,0x12,0x12,0xFE,0x00,0x04,0x07,0x02,0x08,0x09,\n0x09,0x09,0x09,0x09,0x09,0x08,/*\"坦\",2656*/},{\n\n0x12,0x12,0xFE,0x89,0x04,0xD2,0x08,0xE7,0x88,0x52,0x01,0x01,0x01,0x07,0x08,0x09,\n0x0C,0x0A,0x09,0x0A,0x0C,0x0C,/*\"毯\",2657*/},{\n\n0x84,0x45,0xF6,0xAC,0x00,0xFE,0x12,0x12,0x12,0xFE,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x09,0x09,0x09,0x08,/*\"袒\",2658*/},{\n\n0x42,0xF2,0x2E,0xE2,0x16,0x94,0x7C,0x17,0xD4,0x14,0x96,0x00,0x07,0x02,0x0B,0x06,\n0x01,0x0A,0x05,0x03,0x05,0x08,/*\"碳\",2659*/},{\n\n0x08,0x08,0xFF,0x88,0x46,0x52,0x4A,0xE2,0x4A,0x52,0x46,0x01,0x09,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"探\",2660*/},{\n\n0xFC,0x04,0xFC,0x00,0xE2,0xAF,0xAA,0xFA,0xAA,0xAF,0xE2,0x03,0x01,0x03,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"嘆\",2661*/},{\n\n0x10,0x16,0xFC,0x14,0xD4,0x17,0xF4,0x14,0x94,0x56,0x10,0x08,0x07,0x00,0x09,0x04,\n0x02,0x01,0x02,0x04,0x08,0x08,/*\"炭\",2662*/},{\n\n0x11,0x22,0x00,0x40,0xDF,0x55,0x55,0x55,0x55,0x5F,0x40,0x04,0x02,0x04,0x02,0x09,\n0x05,0x0B,0x05,0x0B,0x09,0x07,/*\"湯\",2663*/},{\n\n0x08,0xFF,0x08,0xFE,0x22,0xAA,0xAA,0xFF,0xAA,0xFA,0x22,0x02,0x03,0x09,0x07,0x00,\n0x0E,0x0A,0x0B,0x0A,0x0E,0x00,/*\"塘\",2664*/},{\n\n0x88,0xFF,0x48,0xFE,0x22,0xAA,0xAA,0xFF,0xAA,0xFA,0x22,0x08,0x0F,0x08,0x07,0x00,\n0x0E,0x0A,0x0B,0x0A,0x0E,0x00,/*\"搪\",2665*/},{\n\n0x0C,0x05,0xF6,0x94,0x94,0x97,0x94,0x94,0xF6,0x05,0x0C,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"堂\",2666*/},{\n\n0x0C,0x04,0x75,0x56,0x54,0xD7,0x54,0x56,0x75,0x04,0x0C,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"棠\",2667*/},{\n\n0x00,0xFE,0x92,0xFE,0x0D,0xF6,0x94,0x97,0x94,0xF6,0x0D,0x08,0x07,0x08,0x0F,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"膛\",2668*/},{\n\n0x00,0xFE,0x22,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x22,0x08,0x07,0x00,0x0E,0x0A,\n0x0A,0x0B,0x0A,0x0A,0x0E,0x00,/*\"唐\",2669*/},{\n\n0x24,0xA8,0xFF,0xA8,0xFE,0x22,0xAA,0xFF,0xAA,0xFA,0x22,0x01,0x00,0x0F,0x08,0x07,\n0x00,0x0E,0x0B,0x0A,0x0E,0x00,/*\"糖\",2670*/},{\n\n0x20,0x10,0xFC,0x03,0xF2,0x14,0xD0,0x5F,0xD0,0x14,0xF2,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"倘\",2671*/},{\n\n0x80,0xFE,0xAB,0xFE,0x00,0xF2,0x14,0xDF,0x50,0xD4,0xF2,0x04,0x02,0x09,0x0F,0x00,\n0x0F,0x00,0x03,0x02,0x0B,0x0F,/*\"躺\",2672*/},{\n\n0x10,0x22,0x04,0x00,0xF2,0x14,0xD0,0x5F,0xD0,0x14,0xF2,0x04,0x02,0x01,0x00,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"淌\",2673*/},{\n\n0xA4,0x24,0xFF,0x24,0xF9,0x0A,0xE8,0xAF,0xE8,0x0A,0xF9,0x0F,0x04,0x0F,0x09,0x0B,\n0x08,0x08,0x08,0x08,0x0A,0x0B,/*\"趟\",2674*/},{\n\n0x08,0x91,0x42,0x90,0x5F,0x75,0xD5,0x55,0xD5,0x5F,0xD0,0x09,0x08,0x0A,0x04,0x04,\n0x03,0x04,0x05,0x0A,0x09,0x09,/*\"燙\",2675*/},{\n\n0x88,0xFF,0x48,0x04,0x53,0x4E,0xFA,0x4A,0x4A,0x02,0xFE,0x08,0x0F,0x00,0x00,0x03,\n0x02,0x03,0x02,0x0B,0x08,0x07,/*\"掏\",2676*/},{\n\n0x11,0x22,0x00,0xAA,0xAA,0xAA,0xEF,0xAA,0xAA,0xAA,0x62,0x04,0x02,0x00,0x0E,0x0A,\n0x0E,0x02,0x06,0x0A,0x0F,0x02,/*\"濤\",2677*/},{\n\n0x22,0x44,0x02,0xEA,0x32,0x22,0x16,0x09,0x31,0x29,0xE5,0x04,0x02,0x00,0x0F,0x09,\n0x09,0x08,0x08,0x09,0x09,0x0F,/*\"滔\",2678*/},{\n\n0x10,0xFC,0x03,0xF8,0x10,0x54,0x6B,0xDA,0x4A,0x36,0x90,0x00,0x0F,0x00,0x03,0x08,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"絛\",2679*/},{\n\n0x92,0xCE,0xBA,0xAF,0xEA,0xAA,0xAA,0xAF,0x8A,0x0A,0xFA,0x00,0x06,0x04,0x04,0x07,\n0x04,0x04,0x06,0x08,0x08,0x07,/*\"萄\",2680*/},{\n\n0x88,0x68,0xFF,0x48,0x84,0x48,0xFF,0x00,0xFF,0x48,0x84,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"桃\",2681*/},{\n\n0x11,0xF2,0x00,0x44,0x28,0xFF,0x00,0xFF,0x28,0x44,0x00,0x08,0x07,0x08,0x0A,0x09,\n0x08,0x08,0x09,0x0A,0x0A,0x0B,/*\"逃\",2682*/},{\n\n0x22,0x44,0x08,0x44,0x53,0x4E,0xFA,0x4A,0x4A,0x02,0xFE,0x04,0x02,0x01,0x00,0x03,\n0x02,0x03,0x02,0x0B,0x08,0x07,/*\"淘\",2683*/},{\n\n0xFE,0x32,0xCE,0x44,0x53,0x4E,0xFA,0x4A,0x4A,0x02,0xFE,0x0F,0x02,0x01,0x00,0x03,\n0x02,0x03,0x02,0x0B,0x08,0x07,/*\"陶\",2684*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0x28,0xC8,0x08,0xFF,0x08,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x00,0x00,0x08,0x0F,0x00,/*\"討\",2685*/},{\n\n0x12,0x12,0xFA,0xAE,0xAB,0xAA,0xAA,0xAE,0x0A,0x12,0x12,0x02,0x0A,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x0A,0x02,/*\"套\",2686*/},{\n\n0x9C,0x88,0xFF,0x48,0x10,0x54,0x54,0x5F,0xF4,0x54,0x50,0x00,0x00,0x0F,0x00,0x00,\n0x01,0x0A,0x08,0x0F,0x00,0x00,/*\"特\",2687*/},{\n\n0x02,0xFA,0x4F,0xFA,0x82,0xAA,0xE2,0xBA,0xA7,0xAA,0x82,0x08,0x07,0x09,0x0F,0x0A,\n0x05,0x08,0x0E,0x00,0x05,0x0A,/*\"藤\",2688*/},{\n\n0x00,0xFF,0x49,0xFF,0x50,0xF5,0x5C,0xD7,0x54,0x75,0x50,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x0D,0x07,0x0D,0x05,0x0C,/*\"騰\",2689*/},{\n\n0x08,0x90,0xFE,0x22,0x12,0xAE,0x4B,0x4A,0xAA,0x1A,0x02,0x09,0x04,0x03,0x01,0x01,\n0x04,0x05,0x09,0x0A,0x01,0x01,/*\"疼\",2690*/},{\n\n0x00,0xFE,0x92,0xFE,0x55,0xB6,0x9C,0xD7,0x94,0xB6,0x55,0x08,0x07,0x08,0x0F,0x00,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"謄\",2691*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0x75,0x56,0xFC,0x56,0x5D,0xC0,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x00,0x02,0x03,/*\"梯\",2692*/},{\n\n0x80,0x5F,0xF5,0x55,0xD5,0x5F,0xC0,0x00,0xFC,0x00,0xFF,0x02,0x09,0x04,0x02,0x09,\n0x08,0x07,0x00,0x01,0x08,0x0F,/*\"剔\",2693*/},{\n\n0xCF,0x09,0xF9,0x4F,0x80,0x5F,0xF5,0x55,0xD5,0x5F,0xC0,0x07,0x04,0x03,0x02,0x02,\n0x09,0x04,0x02,0x09,0x08,0x07,/*\"踢\",2694*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x75,0x56,0xFC,0x56,0x5D,0xC0,0x08,0x09,0x07,0x04,0x04,\n0x02,0x01,0x0F,0x00,0x02,0x03,/*\"銻\",2695*/},{\n\n0x88,0x88,0xFF,0x48,0x08,0x5F,0x55,0xD5,0x55,0x5F,0x40,0x00,0x08,0x0F,0x00,0x08,\n0x07,0x08,0x0F,0x09,0x09,0x08,/*\"提\",2696*/},{\n\n0x40,0x5F,0x55,0xD5,0x5F,0x40,0xFD,0x55,0x57,0x55,0xFD,0x08,0x07,0x08,0x0F,0x09,\n0x08,0x0D,0x0B,0x09,0x0B,0x0D,/*\"題\",2697*/},{\n\n0xCF,0x09,0xF9,0x4F,0x32,0xD6,0x5A,0xF3,0x5A,0xD6,0x32,0x07,0x04,0x03,0x02,0x00,\n0x03,0x00,0x0F,0x02,0x03,0x00,/*\"蹄\",2698*/},{\n\n0xFE,0x02,0xFE,0x00,0xB2,0x96,0x9A,0xD3,0x9A,0x96,0xB2,0x03,0x01,0x03,0x00,0x07,\n0x00,0x00,0x0F,0x00,0x04,0x07,/*\"啼\",2699*/},{\n\n0x18,0xEF,0xA9,0xEF,0xBE,0xAA,0xBF,0xAA,0xBF,0xAA,0xBE,0x00,0x0F,0x02,0x0F,0x08,\n0x0B,0x0E,0x0A,0x0E,0x0B,0x08,/*\"體\",2700*/},{\n\n0x48,0x2A,0xDA,0x4F,0x5A,0x68,0x5A,0x4F,0xDA,0x2A,0x48,0x00,0x00,0x0F,0x05,0x05,\n0x05,0x05,0x05,0x0F,0x00,0x00,/*\"替\",2701*/},{\n\n0xFC,0x04,0xFC,0x98,0x8A,0xFA,0xAA,0xFF,0xAA,0xFA,0x9A,0x03,0x01,0x03,0x08,0x06,\n0x08,0x08,0x0F,0x0A,0x0A,0x09,/*\"嚏\",2702*/},{\n\n0x78,0x00,0xFF,0x08,0x80,0x5F,0xF5,0x55,0xD5,0x5F,0xC0,0x00,0x00,0x0F,0x00,0x02,\n0x09,0x04,0x02,0x09,0x08,0x07,/*\"惕\",2703*/},{\n\n0x22,0x44,0x00,0x74,0x55,0xD6,0xFC,0x56,0x55,0x5C,0xC0,0x04,0x02,0x04,0x02,0x01,\n0x00,0x0F,0x00,0x02,0x02,0x01,/*\"涕\",2704*/},{\n\n0x74,0x55,0x56,0xFC,0x56,0x5D,0xC0,0x00,0xFC,0x00,0xFF,0x04,0x02,0x01,0x0F,0x00,\n0x02,0x03,0x00,0x01,0x08,0x0F,/*\"剃\",2705*/},{\n\n0x00,0xFF,0x25,0x95,0x4D,0xE5,0x45,0xF5,0x45,0xF5,0x47,0x08,0x07,0x01,0x0F,0x00,\n0x0F,0x08,0x0B,0x0A,0x0B,0x08,/*\"屜\",2706*/},{\n\n0x20,0x22,0x22,0x22,0xA2,0x7E,0xA2,0x22,0x22,0x22,0x20,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"天\",2707*/},{\n\n0x22,0x44,0x00,0x48,0x29,0x19,0xCF,0x09,0x19,0x29,0x48,0x04,0x02,0x01,0x04,0x02,\n0x08,0x0F,0x01,0x06,0x01,0x06,/*\"添\",2708*/},{\n\n0x08,0xFF,0x08,0x02,0xFA,0xAA,0xAF,0xAA,0xAA,0xFA,0x02,0x02,0x03,0x01,0x02,0x0B,\n0x06,0x02,0x02,0x06,0x0B,0x02,/*\"填\",2709*/},{\n\n0x00,0xFE,0x22,0x22,0x22,0xFE,0x22,0x22,0x22,0xFE,0x00,0x00,0x0F,0x04,0x04,0x04,\n0x07,0x04,0x04,0x04,0x0F,0x00,/*\"田\",2710*/},{\n\n0x92,0x92,0xFE,0x91,0x91,0x04,0xFF,0x44,0x44,0xFF,0x04,0x0F,0x04,0x04,0x04,0x0F,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"甜\",2711*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0x92,0x92,0xFE,0x91,0x91,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"恬\",2712*/},{\n\n0x92,0xFE,0x91,0x48,0x29,0x19,0xCF,0x09,0x19,0x29,0x48,0x0F,0x04,0x0F,0x04,0x02,\n0x08,0x0F,0x01,0x06,0x01,0x06,/*\"舔\",2713*/},{\n\n0x00,0xFE,0x92,0xFE,0x24,0xFF,0x24,0xFF,0x24,0xFC,0x00,0x08,0x07,0x08,0x0F,0x01,\n0x09,0x05,0x01,0x05,0x09,0x01,/*\"腆\",2714*/},{\n\n0x88,0x88,0xFF,0x48,0x84,0x48,0xFF,0x00,0xFF,0x48,0x84,0x00,0x08,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"挑\",2715*/},{\n\n0x10,0xFC,0x03,0xF8,0x10,0x54,0x4B,0xEA,0x4A,0x56,0x10,0x00,0x0F,0x00,0x03,0x02,\n0x01,0x08,0x0F,0x00,0x01,0x02,/*\"條\",2716*/},{\n\n0x11,0xF2,0x00,0x21,0xD1,0x4F,0x41,0x51,0x51,0xCF,0x00,0x08,0x07,0x08,0x08,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"迢\",2717*/},{\n\n0xFE,0x92,0x92,0xFE,0x84,0x48,0xFF,0x00,0xFF,0x48,0x84,0x0F,0x04,0x04,0x07,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"眺\",2718*/},{\n\n0xCF,0x09,0xF9,0x4F,0x84,0x48,0xFF,0x00,0xFF,0x48,0x84,0x07,0x04,0x03,0x02,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"跳\",2719*/},{\n\n0xFE,0x2A,0x2A,0x2A,0xFE,0x00,0xC0,0x40,0x7F,0x48,0xC8,0x09,0x05,0x01,0x05,0x09,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"貼\",2720*/},{\n\n0x4A,0xF9,0x4A,0x00,0xBA,0xAF,0xBA,0x08,0xFF,0x08,0xCA,0x0A,0x0F,0x05,0x00,0x0A,\n0x0F,0x0A,0x04,0x03,0x05,0x0E,/*\"鐵\",2721*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x00,0xC0,0x40,0x7F,0x48,0xC8,0x01,0x00,0x0F,0x01,0x01,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"帖\",2722*/},{\n\n0x00,0xFE,0x8A,0xFA,0xAA,0xFA,0xEB,0xAA,0xFE,0xAA,0xEA,0x08,0x07,0x0A,0x0F,0x0A,\n0x0F,0x08,0x05,0x0A,0x0C,0x02,/*\"廳\",2723*/},{\n\n0x41,0x7F,0x55,0xFF,0x01,0xAA,0xBA,0xAF,0xBA,0xAA,0xBA,0x0A,0x0F,0x0A,0x0F,0x04,\n0x02,0x0C,0x09,0x0C,0x02,0x0C,/*\"聽\",2724*/},{\n\n0x78,0x00,0xFF,0x04,0x12,0xAA,0x92,0xAA,0x92,0xAA,0x02,0x08,0x06,0x01,0x06,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"烴\",2725*/},{\n\n0x22,0x44,0x00,0x02,0x02,0x02,0x02,0xFE,0x02,0x02,0x02,0x04,0x02,0x01,0x00,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"汀\",2726*/},{\n\n0x02,0x32,0x2A,0xE6,0x00,0x12,0x12,0xFE,0x11,0x11,0x00,0x08,0x05,0x02,0x05,0x09,\n0x09,0x09,0x09,0x09,0x09,0x09,/*\"廷\",2727*/},{\n\n0x20,0x10,0xFC,0x03,0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x00,0x00,0x0F,0x00,0x01,\n0x02,0x0A,0x0E,0x02,0x02,0x01,/*\"停\",2728*/},{\n\n0x82,0x82,0xBA,0xAA,0xAA,0xAB,0xAA,0xAA,0xBA,0x82,0x82,0x01,0x02,0x02,0x0A,0x0A,\n0x0E,0x02,0x02,0x02,0x02,0x01,/*\"亭\",2729*/},{\n\n0x00,0xFE,0x02,0xCA,0xBA,0x02,0x53,0x52,0xF2,0x4A,0x4A,0x08,0x07,0x0A,0x04,0x0B,\n0x08,0x0A,0x0A,0x0B,0x0A,0x0A,/*\"庭\",2730*/},{\n\n0x88,0xFF,0x48,0x00,0x72,0xCE,0x00,0x22,0xFE,0x21,0x00,0x08,0x0F,0x00,0x0A,0x04,\n0x0B,0x08,0x0A,0x0B,0x0A,0x08,/*\"挺\",2731*/},{\n\n0x20,0xFE,0xAB,0xFE,0x00,0x72,0xCE,0x00,0x22,0xFE,0x21,0x08,0x07,0x08,0x0F,0x0A,\n0x04,0x0B,0x08,0x0A,0x0B,0x0A,/*\"艇\",2732*/},{\n\n0x11,0xF2,0x00,0xF9,0xA9,0xAB,0xFD,0xAD,0xAB,0xF8,0x00,0x08,0x07,0x08,0x0B,0x08,\n0x08,0x0B,0x08,0x0A,0x0B,0x08,/*\"通\",2733*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x02,0xEA,0x2A,0xEA,0x02,0xFE,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"桐\",2734*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x00,0xFE,0x2A,0xEA,0x02,0xFE,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x0F,0x01,0x01,0x08,0x0F,/*\"酮\",2735*/},{\n\n0xFE,0x92,0x92,0xFE,0x08,0xFA,0xAE,0xFB,0xAE,0xFA,0x08,0x0F,0x04,0x04,0x07,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"瞳\",2736*/},{\n\n0x00,0xFE,0x02,0xEA,0x2A,0x2A,0x2A,0x2A,0xEA,0x02,0xFE,0x00,0x0F,0x00,0x01,0x01,\n0x01,0x01,0x01,0x09,0x08,0x0F,/*\"同\",2737*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFE,0x02,0xEA,0x2A,0xEA,0x02,0xFE,0x0A,0x0F,0x05,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"銅\",2738*/},{\n\n0x40,0xFE,0x4A,0x52,0x42,0xFE,0x40,0x88,0x44,0x23,0x18,0x08,0x07,0x00,0x00,0x08,\n0x0F,0x08,0x08,0x04,0x02,0x01,/*\"彤\",2739*/},{\n\n0x08,0xFA,0xAA,0xAE,0xAA,0xFB,0xAA,0xAE,0xAA,0xFA,0x08,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"童\",2740*/},{\n\n0x88,0x68,0xFF,0x48,0xF1,0x51,0x55,0xF9,0x55,0x53,0xF0,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"桶\",2741*/},{\n\n0x88,0x88,0xFF,0x48,0xF1,0x51,0x55,0xF9,0x55,0x53,0xF0,0x00,0x08,0x0F,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"捅\",2742*/},{\n\n0x04,0xFB,0x0A,0xAE,0xAA,0xAC,0xAB,0xAA,0x0E,0xFA,0x02,0x00,0x0F,0x00,0x03,0x02,\n0x02,0x02,0x0B,0x08,0x0F,0x00,/*\"筒\",2743*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x64,0xD4,0x4D,0xC6,0x54,0xE4,0x0C,0x02,0x04,0x02,0x0C,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"統\",2744*/},{\n\n0x08,0x90,0xFE,0x02,0xEA,0xAA,0xBB,0xEA,0xBA,0xAA,0xE2,0x09,0x04,0x03,0x00,0x0F,\n0x02,0x02,0x07,0x02,0x0A,0x0F,/*\"痛\",2745*/},{\n\n0x10,0xFC,0x03,0xE8,0xA4,0xAA,0xE9,0x0A,0xC4,0x08,0xE8,0x00,0x0F,0x00,0x0F,0x02,\n0x0A,0x0F,0x00,0x03,0x08,0x0F,/*\"偷\",2746*/},{\n\n0x08,0x08,0xFF,0x88,0x50,0xCF,0x41,0x41,0x4F,0xD0,0x10,0x01,0x09,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"投\",2747*/},{\n\n0x7A,0x4A,0x4A,0x4A,0x7A,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x09,0x0A,0x04,0x06,0x05,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頭\",2748*/},{\n\n0x11,0xF2,0x00,0x28,0x5A,0xCA,0x7E,0x4A,0xDA,0x29,0x08,0x08,0x07,0x08,0x0C,0x0A,\n0x09,0x08,0x0D,0x0D,0x0B,0x08,/*\"透\",2749*/},{\n\n0xF0,0x10,0x10,0x1F,0x01,0x01,0x01,0x1F,0x10,0x10,0xF0,0x0F,0x04,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"凸\",2750*/},{\n\n0x48,0x48,0x2A,0x9A,0x0A,0x3E,0x09,0x99,0x29,0x48,0x48,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"禿\",2751*/},{\n\n0x9C,0x84,0x94,0x8C,0x85,0xE6,0x84,0xAC,0xD4,0x84,0x9C,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"突\",2752*/},{\n\n0xFF,0x01,0xD1,0x57,0x55,0x7D,0x55,0x57,0xD1,0x01,0xFF,0x0F,0x04,0x07,0x04,0x07,\n0x05,0x07,0x04,0x07,0x04,0x0F,/*\"圖\",2753*/},{\n\n0x48,0x24,0xF2,0x09,0x00,0xA4,0x24,0xFF,0x24,0x24,0x20,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"徒\",2754*/},{\n\n0x10,0x11,0xF2,0x00,0x28,0xA4,0x2A,0xF9,0x2A,0xA4,0x28,0x08,0x04,0x03,0x04,0x09,\n0x08,0x0A,0x0B,0x08,0x08,0x09,/*\"途\",2755*/},{\n\n0x84,0x49,0x22,0x00,0xA8,0x64,0xAA,0xF9,0x2A,0x64,0xA8,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"塗\",2756*/},{\n\n0x00,0xFF,0x45,0x55,0xD5,0x55,0x7D,0x55,0x65,0xDD,0x47,0x08,0x07,0x02,0x01,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"屠\",2757*/},{\n\n0x00,0x10,0x10,0x10,0x10,0xFF,0x10,0x10,0x10,0x10,0x00,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"土\",2758*/},{\n\n0xFC,0x04,0x04,0xFC,0x00,0x10,0x10,0xFF,0x10,0x10,0x00,0x03,0x01,0x01,0x03,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"吐\",2759*/},{\n\n0x10,0xF8,0x94,0x93,0x92,0xF2,0x9A,0x96,0x90,0xF0,0x00,0x08,0x08,0x04,0x02,0x01,\n0x00,0x07,0x08,0x0A,0x08,0x0C,/*\"兔\",2760*/},{\n\n0x22,0x44,0xA0,0xAE,0xA8,0xA8,0xEF,0xA8,0xA8,0xAE,0xA0,0x04,0x02,0x0F,0x00,0x00,\n0x07,0x00,0x07,0x00,0x08,0x0F,/*\"湍\",2761*/},{\n\n0xFF,0x45,0x7D,0x55,0x55,0x7F,0x55,0xD5,0x7D,0x45,0xFF,0x0F,0x09,0x0B,0x0D,0x09,\n0x0D,0x0D,0x0F,0x09,0x09,0x0F,/*\"團\",2762*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"推\",2763*/},{\n\n0x4A,0x2A,0xFE,0x29,0x49,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x08,0x07,0x00,0x0F,0x04,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頹\",2764*/},{\n\n0x00,0xFF,0x49,0xFF,0x22,0xEC,0x00,0xFF,0x35,0xD5,0x5F,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x04,0x0B,0x09,0x08,0x0B,/*\"腿\",2765*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x04,0xFA,0x89,0x88,0x89,0xFA,0x04,0x04,0x03,0x02,0x03,\n0x08,0x04,0x03,0x00,0x07,0x0C,/*\"蛻\",2766*/},{\n\n0x84,0x45,0xF6,0xAC,0x22,0xEC,0x00,0xFF,0x35,0xD5,0x5F,0x00,0x00,0x0F,0x00,0x08,\n0x07,0x04,0x0B,0x09,0x08,0x0B,/*\"褪\",2767*/},{\n\n0x10,0x11,0xF2,0x00,0xFF,0x15,0xB5,0x55,0x95,0x5F,0x20,0x08,0x04,0x03,0x04,0x0B,\n0x09,0x08,0x08,0x08,0x0B,0x08,/*\"退\",2768*/},{\n\n0x88,0x49,0xA9,0x99,0x8D,0x8B,0x89,0x99,0xA9,0x49,0x88,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x0F,0x00,0x00,/*\"吞\",2769*/},{\n\n0x04,0xF4,0x84,0x84,0x84,0xFF,0x84,0x84,0x84,0xF4,0x04,0x00,0x00,0x00,0x00,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"屯\",2770*/},{\n\n0x40,0xBF,0xD5,0xBD,0x95,0xBF,0xD4,0xDB,0xA9,0xDB,0x42,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"臀\",2771*/},{\n\n0x88,0x88,0xFF,0x48,0x48,0xF4,0x47,0xFC,0x24,0x14,0xF4,0x00,0x08,0x0F,0x00,0x00,\n0x07,0x08,0x0B,0x08,0x09,0x0D,/*\"拖\",2772*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x42,0x42,0xFE,0x21,0x21,0x20,0x0F,0x05,0x05,0x0F,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"託\",2773*/},{\n\n0x00,0xFF,0x49,0xFF,0x04,0xFA,0x89,0x88,0x89,0xFA,0x04,0x08,0x07,0x08,0x0F,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"脫\",2774*/},{\n\n0xFE,0xAB,0xAA,0xBE,0xA0,0x0C,0xE4,0x05,0x86,0x44,0x2C,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"鴕\",2775*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0x0C,0xE4,0x05,0x86,0x44,0x2C,0x0F,0x02,0x02,0x01,0x00,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"陀\",2776*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x08,0x88,0x7F,0x88,0x08,0x08,0x06,0x00,0x0A,0x08,0x07,\n0x08,0x07,0x00,0x03,0x04,0x08,/*\"馱\",2777*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x0C,0xE4,0x05,0x86,0x44,0x2C,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"駝\",2778*/},{\n\n0xC8,0xFF,0x48,0xFF,0x19,0xE7,0x12,0xAA,0xAE,0xBB,0xAA,0x00,0x0F,0x00,0x0F,0x01,\n0x00,0x00,0x0F,0x02,0x0A,0x0F,/*\"橢\",2779*/},{\n\n0x82,0x8A,0x92,0x82,0xCA,0x92,0x81,0x81,0x91,0x8D,0x81,0x08,0x08,0x0A,0x0B,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x00,/*\"妥\",2780*/},{\n\n0x88,0x88,0xFF,0x48,0x88,0x42,0xF2,0x2E,0x22,0x22,0xE2,0x00,0x08,0x0F,0x00,0x00,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"拓\",2781*/},{\n\n0xFE,0x02,0xFE,0x00,0x48,0xFA,0x4A,0xFE,0x49,0xF9,0x48,0x03,0x01,0x03,0x00,0x02,\n0x0B,0x0A,0x0F,0x0A,0x0B,0x02,/*\"唾\",2782*/},{\n\n0x88,0xFF,0x48,0x00,0x4C,0x54,0x4D,0x46,0xCC,0x54,0x0C,0x08,0x0F,0x00,0x00,0x04,\n0x0A,0x09,0x09,0x08,0x08,0x0C,/*\"挖\",2783*/},{\n\n0xFC,0x04,0x04,0xFC,0x20,0x24,0x24,0xBF,0x24,0x24,0x20,0x03,0x01,0x01,0x03,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"哇\",2784*/},{\n\n0xF8,0x88,0xFF,0x88,0xF8,0x00,0x24,0x24,0xBF,0x24,0x24,0x08,0x08,0x07,0x04,0x0E,\n0x08,0x09,0x09,0x0F,0x09,0x09,/*\"蛙\",2785*/},{\n\n0x46,0x92,0x2A,0x86,0xA2,0xA3,0xF2,0xA6,0xAA,0xA2,0x86,0x08,0x04,0x0A,0x08,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"窪\",2786*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0x24,0x24,0xBF,0x24,0x24,0x20,0x08,0x05,0x02,0x05,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"娃\",2787*/},{\n\n0x02,0x02,0xE2,0x1E,0x52,0x92,0x12,0xF2,0x02,0x02,0x02,0x00,0x0F,0x08,0x04,0x04,\n0x01,0x00,0x07,0x08,0x08,0x0E,/*\"瓦\",2788*/},{\n\n0x45,0xF6,0xAC,0x00,0xBA,0xAF,0xBA,0xEA,0xBA,0xEF,0xBA,0x00,0x0F,0x00,0x08,0x07,\n0x02,0x04,0x0B,0x04,0x0A,0x0C,/*\"襪\",2789*/},{\n\n0x51,0x51,0x49,0x49,0x45,0xDF,0x41,0x45,0x45,0x49,0x51,0x08,0x08,0x0F,0x08,0x08,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"歪\",2790*/},{\n\n0x40,0x30,0x4F,0x88,0x78,0x00,0x00,0xFF,0x10,0x20,0xC0,0x08,0x04,0x02,0x01,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"外\",2791*/},{\n\n0x7A,0x4A,0x7A,0x80,0x66,0x9A,0xF2,0x03,0xF2,0x92,0xF6,0x09,0x0A,0x05,0x04,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"豌\",2792*/},{\n\n0x56,0x9D,0xD4,0x80,0xBA,0xAB,0xBA,0x80,0xD6,0x9D,0x54,0x00,0x03,0x02,0x02,0x02,\n0x02,0x02,0x0A,0x0A,0x0A,0x06,/*\"彎\",2793*/},{\n\n0x22,0x44,0x00,0x5A,0x95,0xEA,0xAB,0xEA,0x80,0x9A,0x55,0x04,0x02,0x01,0x00,0x03,\n0x02,0x02,0x02,0x0A,0x0A,0x06,/*\"灣\",2794*/},{\n\n0x22,0x22,0xFE,0x22,0x10,0x12,0xF2,0x12,0xF2,0x12,0x10,0x04,0x04,0x03,0x02,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"玩\",2795*/},{\n\n0x10,0xF2,0x12,0xF2,0x10,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x08,0x07,0x00,0x07,0x02,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頑\",2796*/},{\n\n0x08,0x28,0x48,0xFF,0x08,0x08,0x08,0xF8,0x00,0x00,0x00,0x08,0x04,0x03,0x00,0x01,\n0x02,0x00,0x07,0x08,0x08,0x0E,/*\"丸\",2797*/},{\n\n0x78,0x00,0xFF,0x08,0x8C,0xA4,0xA5,0xA6,0xA4,0xA4,0x8C,0x08,0x06,0x01,0x06,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"烷\",2798*/},{\n\n0x86,0x82,0x92,0x92,0x92,0x93,0x92,0x92,0x92,0x82,0x86,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"完\",2799*/},{\n\n0xF2,0x2E,0xE2,0x80,0x66,0x9A,0xF2,0x03,0xF2,0x92,0xF6,0x07,0x02,0x07,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"碗\",2800*/},{\n\n0x88,0x88,0xFF,0x48,0xF8,0x94,0x93,0xF2,0x9A,0x96,0xF0,0x00,0x08,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"挽\",2801*/},{\n\n0xFE,0x22,0xFE,0x00,0xF8,0x94,0x93,0xF2,0x9A,0x96,0xF0,0x07,0x02,0x07,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"晚\",2802*/},{\n\n0xFC,0x46,0xFD,0x00,0x8C,0xA4,0xA5,0xA6,0xA4,0xA4,0x8C,0x0F,0x04,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"皖\",2803*/},{\n\n0x78,0x00,0xFF,0x88,0x66,0x9A,0xF2,0x03,0xF2,0x92,0xF6,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"惋\",2804*/},{\n\n0x86,0x62,0x9A,0x12,0xF2,0x03,0xF2,0x12,0x12,0xF2,0x06,0x00,0x08,0x04,0x03,0x00,\n0x00,0x07,0x08,0x09,0x09,0x0C,/*\"宛\",2805*/},{\n\n0x88,0x78,0x0F,0xF8,0x66,0x9A,0xF2,0x03,0xF2,0x92,0xF6,0x08,0x05,0x02,0x05,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"婉\",2806*/},{\n\n0x02,0xFA,0xAA,0xAF,0xAA,0xFA,0xAA,0xAF,0xAA,0xFA,0x02,0x0E,0x02,0x02,0x0A,0x0A,\n0x0F,0x0A,0x0E,0x02,0x0A,0x0E,/*\"萬\",2807*/},{\n\n0xFE,0x92,0xFE,0x80,0x66,0x9A,0xF2,0x03,0xF2,0x92,0xF6,0x07,0x08,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"腕\",2808*/},{\n\n0x22,0x44,0x00,0x42,0x42,0x42,0xFE,0x42,0x42,0x42,0x00,0x04,0x02,0x09,0x08,0x08,\n0x08,0x0F,0x08,0x08,0x08,0x08,/*\"汪\",2809*/},{\n\n0x00,0x42,0x42,0x42,0x42,0xFE,0x42,0x42,0x42,0x42,0x00,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"王\",2810*/},{\n\n0x08,0x08,0xF8,0x08,0x09,0x0A,0x08,0x08,0x08,0x08,0x08,0x00,0x00,0x0F,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x08,/*\"亡\",2811*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0x42,0x42,0xFE,0x42,0x42,0x02,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"枉\",2812*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFE,0x52,0xDA,0x72,0x5A,0x52,0xFE,0x0E,0x00,0x06,0x00,0x0F,\n0x00,0x03,0x02,0x02,0x08,0x0F,/*\"網\",2813*/},{\n\n0x48,0x24,0xF2,0x09,0x00,0x88,0x89,0xFA,0x88,0x88,0x08,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"往\",2814*/},{\n\n0xFE,0x22,0x22,0xFE,0x00,0x42,0x42,0xFE,0x42,0x42,0x00,0x07,0x02,0x02,0x03,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"旺\",2815*/},{\n\n0x04,0xBC,0xA5,0xA6,0xA4,0xC0,0xBF,0x95,0x95,0xD5,0x7F,0x08,0x08,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x08,0x08,/*\"望\",2816*/},{\n\n0x04,0x04,0x3C,0x24,0x24,0xA5,0x26,0x24,0x24,0x24,0x04,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"忘\",2817*/},{\n\n0x84,0x84,0xBC,0xA4,0xE4,0xA5,0xA6,0xA4,0xA4,0xA4,0x84,0x08,0x08,0x0A,0x0B,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x00,/*\"妄\",2818*/},{\n\n0x00,0xFC,0x54,0xF4,0x54,0xD4,0x04,0xFF,0x04,0xC5,0x36,0x08,0x07,0x05,0x02,0x02,\n0x05,0x08,0x04,0x03,0x04,0x0F,/*\"威\",2819*/},{\n\n0xA0,0x6B,0xFA,0x66,0xA2,0xF3,0x5A,0xF6,0x52,0xF3,0x00,0x09,0x0B,0x05,0x05,0x0B,\n0x09,0x05,0x07,0x09,0x0B,0x0C,/*\"巍\",2820*/},{\n\n0x24,0xF2,0x09,0x0E,0xA8,0xAF,0xA8,0x1E,0xE8,0x07,0xFC,0x00,0x0F,0x00,0x08,0x07,\n0x00,0x07,0x0A,0x04,0x03,0x0C,/*\"微\",2821*/},{\n\n0x10,0x08,0xFC,0x0B,0xEA,0x2A,0x2A,0x2A,0x2E,0xE8,0x08,0x08,0x06,0x01,0x00,0x07,\n0x08,0x08,0x09,0x09,0x08,0x0E,/*\"危\",2822*/},{\n\n0x88,0x8A,0xBA,0xAE,0xAB,0xEA,0xAA,0xAA,0xBE,0x88,0x08,0x00,0x06,0x04,0x04,0x04,\n0x0F,0x04,0x04,0x04,0x04,0x00,/*\"韋\",2823*/},{\n\n0x21,0xE2,0x08,0x0A,0xBA,0xAE,0xAB,0xEA,0xAA,0xBE,0x08,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"違\",2824*/},{\n\n0x88,0x68,0xFF,0x48,0x08,0xF4,0x13,0xD2,0x5A,0x56,0xD0,0x00,0x00,0x0F,0x00,0x08,\n0x07,0x00,0x07,0x08,0x09,0x0D,/*\"桅\",2825*/},{\n\n0xFF,0x11,0x95,0x7D,0x57,0xD5,0x55,0x7D,0x11,0x11,0xFF,0x0F,0x08,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x08,0x0F,/*\"圍\",2826*/},{\n\n0xFE,0x02,0xFE,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x04,0x03,0x01,0x03,0x00,0x0F,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"唯\",2827*/},{\n\n0x78,0x00,0xFF,0x24,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"惟\",2828*/},{\n\n0x02,0x86,0x7A,0x52,0x56,0x5A,0x51,0x51,0x79,0xC5,0x01,0x02,0x0D,0x01,0x0D,0x01,\n0x0D,0x01,0x0D,0x01,0x09,0x0F,/*\"爲\",2829*/},{\n\n0x11,0x22,0xDC,0xB3,0xC8,0x10,0xFC,0x27,0xFC,0x25,0x24,0x04,0x02,0x0E,0x00,0x06,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"濰\",2830*/},{\n\n0xD8,0xB4,0x93,0xC8,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"維\",2831*/},{\n\n0x42,0x42,0xD2,0x77,0x5A,0x52,0x52,0x77,0xC2,0x42,0x42,0x06,0x04,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x04,0x04,/*\"葦\",2832*/},{\n\n0x22,0xAA,0x6A,0x2F,0xAA,0x7A,0x2A,0x2F,0x6A,0xA6,0x22,0x01,0x09,0x09,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"萎\",2833*/},{\n\n0xA8,0xAA,0x9A,0x8A,0xCA,0xBE,0x8A,0x8A,0x99,0xA9,0xA8,0x08,0x08,0x0A,0x0B,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x00,/*\"委\",2834*/},{\n\n0x20,0x10,0xFC,0x03,0x88,0xBA,0xAE,0xEB,0xAA,0xBE,0x08,0x00,0x00,0x0F,0x00,0x06,\n0x04,0x04,0x0F,0x04,0x04,0x04,/*\"偉\",2835*/},{\n\n0x10,0xFC,0x03,0x02,0xF6,0x5A,0x56,0x5A,0x79,0xC5,0x01,0x00,0x0F,0x04,0x0A,0x05,\n0x09,0x05,0x09,0x05,0x09,0x0F,/*\"僞\",2836*/},{\n\n0x00,0xFF,0x05,0xA5,0xA5,0xA5,0xE5,0x55,0x55,0x15,0x07,0x08,0x07,0x02,0x02,0x02,\n0x02,0x07,0x09,0x09,0x09,0x0C,/*\"尾\",2837*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x8A,0xBA,0xAF,0xEA,0xBE,0x88,0x0C,0x02,0x04,0x02,0x04,\n0x06,0x04,0x04,0x0F,0x04,0x04,/*\"緯\",2838*/},{\n\n0x20,0x24,0x24,0xA4,0x64,0xFF,0x64,0xA4,0x24,0x24,0x20,0x02,0x02,0x01,0x00,0x00,\n0x0F,0x00,0x00,0x01,0x02,0x02,/*\"未\",2839*/},{\n\n0x02,0xFA,0xAA,0xAF,0xAA,0xBA,0x02,0xA7,0x22,0xFA,0x22,0x04,0x03,0x04,0x0A,0x0F,\n0x02,0x04,0x00,0x09,0x0F,0x00,/*\"蔚\",2840*/},{\n\n0xFE,0x02,0x02,0xFE,0x20,0x24,0xA4,0xFF,0xA4,0x24,0x20,0x03,0x01,0x01,0x03,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"味\",2841*/},{\n\n0x40,0xDF,0x55,0x55,0xD5,0x5F,0x55,0x55,0x55,0xDF,0x40,0x00,0x0F,0x08,0x04,0x04,\n0x01,0x02,0x06,0x05,0x08,0x08,/*\"畏\",2842*/},{\n\n0x00,0x1F,0xF5,0x55,0x55,0x5F,0x55,0x55,0xF5,0x1F,0x00,0x00,0x00,0x0F,0x01,0x01,\n0x01,0x01,0x09,0x0F,0x00,0x00,/*\"胃\",2843*/},{\n\n0xFE,0x02,0xFE,0x40,0xDF,0x55,0x55,0xDF,0x55,0x55,0x5F,0x03,0x01,0x03,0x00,0x0F,\n0x08,0x04,0x01,0x02,0x06,0x09,/*\"喂\",2844*/},{\n\n0xAA,0x9A,0xFE,0x99,0xA9,0x7C,0xD6,0x7D,0xD4,0x7C,0x00,0x0A,0x0B,0x04,0x06,0x09,\n0x06,0x01,0x07,0x0A,0x0B,0x0C,/*\"魏\",2845*/},{\n\n0x10,0xFC,0x03,0x08,0x68,0x88,0x09,0x0A,0x08,0xE8,0x08,0x00,0x0F,0x00,0x08,0x08,\n0x0B,0x08,0x0C,0x0B,0x08,0x08,/*\"位\",2846*/},{\n\n0x11,0x22,0x1F,0xF5,0x55,0x55,0x5F,0x55,0x55,0xF5,0x1F,0x04,0x02,0x00,0x0F,0x01,\n0x01,0x01,0x01,0x09,0x0F,0x00,/*\"渭\",2847*/},{\n\n0x55,0x56,0x54,0x00,0x1F,0xF5,0x55,0x5F,0x55,0xF5,0x1F,0x0F,0x05,0x0F,0x00,0x00,\n0x0F,0x01,0x01,0x09,0x0F,0x00,/*\"謂\",2848*/},{\n\n0x00,0xFF,0x45,0x55,0xD5,0x55,0x47,0x48,0x88,0xFF,0x08,0x08,0x07,0x02,0x09,0x0F,\n0x01,0x02,0x00,0x08,0x0F,0x00,/*\"尉\",2849*/},{\n\n0xA0,0x5F,0x95,0xF5,0x15,0x57,0x80,0x0A,0x92,0xFF,0x02,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"慰\",2850*/},{\n\n0x24,0xF2,0x09,0x3A,0xAE,0xEB,0xBE,0x88,0x12,0xF2,0x12,0x00,0x0F,0x00,0x03,0x02,\n0x0F,0x02,0x02,0x08,0x0F,0x00,/*\"衛\",2851*/},{\n\n0x08,0x90,0xFE,0x02,0xFA,0xAA,0xAB,0xAA,0xFA,0x02,0x02,0x09,0x04,0x0B,0x0E,0x0A,\n0x0E,0x0A,0x0E,0x0A,0x0E,0x08,/*\"瘟\",2852*/},{\n\n0x10,0x21,0x02,0x80,0xBF,0xA9,0xA7,0xA9,0xBF,0x80,0x00,0x04,0x02,0x09,0x0F,0x08,\n0x0F,0x08,0x0F,0x08,0x0F,0x08,/*\"溫\",2853*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x08,0xF8,0x09,0x0A,0xF8,0x08,0x04,0x04,0x03,0x02,0x07,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"蚊\",2854*/},{\n\n0x04,0x04,0x1C,0x64,0x85,0x06,0x84,0x64,0x1C,0x04,0x04,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x04,0x08,0x08,/*\"文\",2855*/},{\n\n0xFF,0x15,0x15,0xFF,0x50,0x50,0x50,0xFF,0x15,0x15,0xFF,0x0F,0x00,0x04,0x07,0x05,\n0x05,0x05,0x0F,0x02,0x08,0x0F,/*\"聞\",2856*/},{\n\n0xD8,0xB4,0x93,0xC8,0x04,0x3C,0xC5,0x06,0xC4,0x3C,0x04,0x0C,0x02,0x04,0x02,0x0C,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"紋\",2857*/},{\n\n0xFE,0x02,0xFE,0x20,0x18,0xC7,0x3C,0x84,0x7C,0x04,0xFC,0x03,0x01,0x03,0x02,0x09,\n0x04,0x02,0x01,0x08,0x08,0x07,/*\"吻\",2858*/},{\n\n0x12,0xD2,0xFE,0x91,0x55,0x57,0x55,0x5F,0x55,0xF7,0x15,0x01,0x00,0x0F,0x08,0x05,\n0x01,0x0D,0x0B,0x0D,0x01,0x0C,/*\"穩\",2859*/},{\n\n0x22,0x22,0x52,0xD6,0x6A,0x5B,0x4A,0x36,0x92,0x22,0x22,0x00,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x00,/*\"紊\",2860*/},{\n\n0x00,0xFF,0x15,0xD5,0x5F,0x40,0x40,0x5F,0xD5,0x15,0xFF,0x00,0x0F,0x00,0x03,0x02,\n0x02,0x02,0x02,0x03,0x08,0x0F,/*\"問\",2861*/},{\n\n0xFE,0x02,0xFE,0x00,0x44,0x52,0xD9,0x14,0x50,0x59,0xD2,0x03,0x01,0x03,0x00,0x05,\n0x0A,0x0F,0x00,0x05,0x0A,0x0F,/*\"嗡\",2862*/},{\n\n0x04,0x44,0x52,0x59,0xD4,0x10,0x50,0x59,0x52,0xC4,0x04,0x00,0x05,0x02,0x08,0x0F,\n0x00,0x05,0x02,0x08,0x0F,0x00,/*\"翁\",2863*/},{\n\n0xAA,0xB6,0xB2,0xEA,0xA2,0x93,0xFE,0xAA,0xFA,0xAE,0xAA,0x00,0x0C,0x0B,0x0A,0x06,\n0x0A,0x02,0x06,0x08,0x08,0x0C,/*\"甕\",2864*/},{\n\n0x88,0xFF,0x48,0x11,0xF2,0x00,0xF8,0xAF,0xE9,0x0F,0xF8,0x08,0x0F,0x00,0x08,0x07,\n0x08,0x0B,0x08,0x08,0x0A,0x0B,/*\"撾\",2865*/},{\n\n0x78,0x48,0xFF,0x48,0xE0,0x3F,0xA5,0xBD,0xA1,0x3F,0xE0,0x04,0x04,0x03,0x02,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"蝸\",2866*/},{\n\n0x10,0x21,0x02,0xE0,0x3F,0xA5,0xA5,0xBD,0xA1,0x3F,0xE0,0x04,0x02,0x01,0x0F,0x00,\n0x03,0x02,0x02,0x03,0x08,0x0F,/*\"渦\",2867*/},{\n\n0x86,0x8A,0xFE,0xAA,0xAA,0xEB,0x8A,0x8A,0xFE,0x8A,0x86,0x0F,0x00,0x00,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x00,0x08,0x0F,/*\"窩\",2868*/},{\n\n0x10,0x12,0x12,0xFF,0x91,0x10,0xFF,0x10,0x90,0x52,0x14,0x02,0x02,0x09,0x0F,0x00,\n0x04,0x02,0x03,0x04,0x08,0x0E,/*\"我\",2869*/},{\n\n0xFA,0xAA,0xAF,0xAA,0xFA,0x04,0x52,0x01,0xFA,0x84,0x88,0x02,0x02,0x0F,0x02,0x02,\n0x01,0x01,0x01,0x0F,0x00,0x00,/*\"斡\",2870*/},{\n\n0xFE,0x92,0x9E,0xF2,0x00,0x00,0xC0,0x3F,0xC0,0x00,0x00,0x07,0x04,0x07,0x04,0x08,\n0x06,0x01,0x00,0x01,0x06,0x08,/*\"臥\",2871*/},{\n\n0x88,0xFF,0x48,0x00,0xFF,0x05,0x95,0xD5,0xB5,0x95,0xD7,0x08,0x0F,0x00,0x08,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"握\",2872*/},{\n\n0x11,0x22,0x00,0x22,0x22,0xE2,0x3E,0xE1,0x21,0x21,0x20,0x04,0x02,0x09,0x04,0x03,\n0x00,0x00,0x00,0x03,0x04,0x08,/*\"沃\",2873*/},{\n\n0x00,0x82,0x7A,0x82,0x02,0xFE,0x02,0x82,0x7A,0x82,0x00,0x09,0x08,0x08,0x08,0x09,\n0x0F,0x09,0x08,0x08,0x08,0x09,/*\"巫\",2874*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0xAA,0xAB,0xAA,0xAA,0xAE,0xA0,0x03,0x01,0x03,0x06,0x00,\n0x06,0x00,0x06,0x08,0x0A,0x07,/*\"嗚\",2875*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFE,0xAA,0xAB,0xAA,0xAA,0xAE,0xA0,0x0A,0x0F,0x05,0x06,0x00,\n0x06,0x00,0x06,0x08,0x0A,0x07,/*\"鎢\",2876*/},{\n\n0x00,0xFE,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xAA,0xAE,0xA0,0x08,0x06,0x00,0x06,0x00,\n0x06,0x00,0x06,0x00,0x08,0x0F,/*\"烏\",2877*/},{\n\n0x11,0x22,0x10,0x12,0xD2,0xB2,0x92,0x92,0x92,0x92,0x10,0x04,0x02,0x01,0x00,0x00,\n0x00,0x00,0x08,0x08,0x07,0x00,/*\"污\",2878*/},{\n\n0x54,0x55,0x56,0x54,0x82,0x7A,0x82,0xFE,0x82,0x7A,0x82,0x0F,0x05,0x05,0x07,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"誣\",2879*/},{\n\n0x00,0xFF,0x05,0x95,0xD5,0xB5,0x95,0x95,0xD5,0x95,0x07,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"屋\",2880*/},{\n\n0x08,0x24,0xFF,0x24,0xFC,0x24,0xFC,0x24,0xFC,0x24,0x00,0x09,0x05,0x01,0x05,0x09,\n0x01,0x05,0x09,0x01,0x05,0x09,/*\"無\",2881*/},{\n\n0x22,0x52,0xFA,0x57,0xF2,0x52,0xF2,0x57,0xF2,0x52,0x02,0x0A,0x06,0x03,0x06,0x0B,\n0x02,0x07,0x0A,0x03,0x06,0x0A,/*\"蕪\",2882*/},{\n\n0x88,0x68,0xFF,0x48,0x21,0xA5,0xBD,0xA7,0xA5,0xBD,0x21,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"梧\",2883*/},{\n\n0x40,0x49,0x49,0x79,0x4F,0x49,0x49,0x49,0x79,0x41,0x40,0x00,0x0F,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0F,0x00,/*\"吾\",2884*/},{\n\n0x00,0x3C,0x20,0x2F,0x29,0xE9,0x29,0x29,0xEF,0x00,0x00,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"吳\",2885*/},{\n\n0x10,0xF0,0x1F,0x11,0xF1,0x1F,0x11,0x11,0xFF,0x10,0x10,0x00,0x09,0x05,0x03,0x01,\n0x09,0x09,0x09,0x07,0x01,0x00,/*\"毋\",2886*/},{\n\n0x10,0x92,0x12,0xF2,0x92,0x92,0x10,0xFF,0x10,0x12,0x14,0x08,0x0F,0x08,0x07,0x04,\n0x04,0x00,0x00,0x03,0x04,0x0E,/*\"武\",2887*/},{\n\n0x02,0x22,0x22,0xE2,0x3E,0x22,0x22,0x22,0xE2,0x02,0x00,0x08,0x08,0x0E,0x09,0x08,\n0x08,0x08,0x08,0x0F,0x08,0x08,/*\"五\",2888*/},{\n\n0x88,0xFF,0x48,0x21,0xA5,0xBD,0xA7,0xA5,0xA5,0xBD,0x21,0x08,0x0F,0x00,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"捂\",2889*/},{\n\n0x90,0x88,0x87,0x84,0x84,0xFC,0x84,0x84,0x84,0x84,0x80,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"午\",2890*/},{\n\n0x24,0xAA,0xFF,0xAA,0xBE,0x2A,0xBE,0xAA,0xFE,0xAA,0x22,0x09,0x0A,0x04,0x02,0x01,\n0x06,0x04,0x04,0x0F,0x04,0x04,/*\"舞\",2891*/},{\n\n0x10,0xFC,0x03,0x00,0x22,0x22,0xFE,0x22,0x22,0xE2,0x00,0x00,0x0F,0x00,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"伍\",2892*/},{\n\n0x10,0xFC,0x4B,0xC4,0x7B,0x4A,0x6A,0x4A,0x4A,0xFA,0x42,0x00,0x0F,0x00,0x03,0x02,\n0x02,0x03,0x0A,0x0A,0x07,0x02,/*\"侮\",2893*/},{\n\n0x08,0xFF,0x08,0x00,0xFE,0xAA,0xAB,0xAA,0xAA,0xAE,0xA0,0x02,0x03,0x01,0x06,0x00,\n0x06,0x00,0x06,0x08,0x0A,0x07,/*\"塢\",2894*/},{\n\n0x00,0xF8,0x08,0x08,0x08,0x08,0xFF,0x08,0x89,0x6A,0x08,0x08,0x07,0x00,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x0F,/*\"戊\",2895*/},{\n\n0x2C,0x65,0xA5,0x6D,0x05,0x4F,0xA5,0xAD,0xA5,0x65,0x0C,0x05,0x0B,0x0F,0x01,0x03,\n0x01,0x0A,0x07,0x0A,0x0F,0x01,/*\"霧\",2896*/},{\n\n0xFE,0x22,0xFE,0x21,0xA5,0xBD,0xA7,0xA5,0xA5,0xBD,0x21,0x07,0x02,0x07,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"晤\",2897*/},{\n\n0x9C,0x88,0xFF,0x48,0x08,0xC7,0x3C,0x84,0x7C,0x04,0xFC,0x00,0x00,0x0F,0x00,0x09,\n0x04,0x02,0x01,0x08,0x08,0x07,/*\"物\",2898*/},{\n\n0x20,0x18,0x87,0x64,0x1C,0x04,0x84,0x7C,0x04,0x04,0xFC,0x02,0x01,0x00,0x08,0x04,\n0x02,0x01,0x08,0x08,0x08,0x07,/*\"勿\",2899*/},{\n\n0x22,0xAA,0xF2,0x2E,0x60,0x94,0x97,0xEA,0x8A,0x96,0x90,0x01,0x08,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x08,0x08,0x07,/*\"務\",2900*/},{\n\n0x78,0x00,0xFF,0x08,0x21,0xA5,0xBD,0xA7,0xA5,0xBD,0x21,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"悟\",2901*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x2F,0x29,0xE9,0x29,0x2F,0x00,0x0F,0x05,0x05,0x0F,0x08,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"誤\",2902*/},{\n\n0x10,0x12,0xD2,0x5F,0x52,0x52,0x52,0x5F,0xD2,0x12,0x10,0x00,0x00,0x0F,0x05,0x05,\n0x05,0x05,0x05,0x0F,0x00,0x00,/*\"昔\",2903*/},{\n\n0xFF,0x01,0x3D,0xE7,0x3D,0x01,0x00,0xFF,0x11,0x11,0xDF,0x09,0x05,0x01,0x05,0x09,\n0x01,0x04,0x08,0x01,0x05,0x09,/*\"熙\",2904*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xFE,0x12,0x12,0xF1,0x11,0x11,0x00,0x00,0x0F,0x08,0x06,\n0x01,0x00,0x00,0x0F,0x00,0x00,/*\"析\",2905*/},{\n\n0x01,0xF9,0x09,0x89,0x7F,0x09,0x7F,0x89,0x89,0xF9,0x01,0x00,0x0F,0x05,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"西\",2906*/},{\n\n0x42,0xF2,0x2E,0x22,0xF0,0x12,0xFE,0x12,0xFE,0x92,0xF2,0x00,0x07,0x02,0x02,0x0F,\n0x05,0x04,0x04,0x04,0x04,0x0F,/*\"硒\",2907*/},{\n\n0x42,0xF2,0x2E,0x22,0xE2,0x20,0x18,0x67,0x84,0x64,0x1C,0x00,0x07,0x02,0x02,0x07,\n0x08,0x04,0x02,0x01,0x00,0x00,/*\"矽\",2908*/},{\n\n0xFE,0x22,0xFE,0x88,0x68,0xFF,0x48,0xFE,0x12,0xF2,0x11,0x07,0x02,0x07,0x00,0x00,\n0x0F,0x04,0x03,0x00,0x0F,0x00,/*\"晰\",2909*/},{\n\n0xFC,0x04,0xFC,0x02,0xEA,0xAA,0xAF,0xAA,0xAA,0xEA,0x02,0x03,0x01,0x03,0x02,0x0E,\n0x0B,0x0A,0x0A,0x0B,0x0E,0x02,/*\"嘻\",2910*/},{\n\n0xFE,0x02,0xFE,0x00,0x02,0xFE,0x82,0x02,0x32,0x2E,0xE0,0x03,0x01,0x03,0x08,0x06,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"吸\",2911*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x80,0x5F,0xF5,0x55,0xD5,0x5F,0xC0,0x08,0x09,0x07,0x04,0x02,\n0x09,0x04,0x02,0x09,0x08,0x07,/*\"錫\",2912*/},{\n\n0x9C,0x88,0xFF,0x48,0xA2,0xEA,0xAB,0xBE,0xEB,0xAA,0xE2,0x00,0x00,0x0F,0x01,0x02,\n0x0B,0x06,0x08,0x07,0x0A,0x0D,/*\"犧\",2913*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0xD5,0xB2,0xDA,0x92,0x95,0x90,0x01,0x00,0x0F,0x00,0x00,\n0x07,0x00,0x0F,0x00,0x04,0x07,/*\"稀\",2914*/},{\n\n0x00,0xFE,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xAA,0xFE,0x00,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"息\",2915*/},{\n\n0x20,0xA9,0xE9,0xBA,0xAA,0xE4,0xA4,0xAA,0xAA,0xB1,0x20,0x01,0x00,0x07,0x00,0x00,\n0x0F,0x00,0x00,0x04,0x07,0x00,/*\"希\",2916*/},{\n\n0x90,0x92,0x56,0x3A,0x12,0x7E,0x11,0x39,0x55,0x91,0x90,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"悉\",2917*/},{\n\n0x00,0xFF,0x49,0xFF,0x4A,0xA6,0x12,0xCF,0x12,0xA6,0x4A,0x08,0x07,0x08,0x0F,0x04,\n0x02,0x09,0x0F,0x01,0x02,0x04,/*\"膝\",2918*/},{\n\n0x40,0x20,0x10,0x2C,0xC7,0x04,0x04,0x84,0x44,0x34,0x0C,0x08,0x08,0x08,0x04,0x04,\n0x03,0x01,0x00,0x00,0x00,0x00,/*\"夕\",2919*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0xD4,0x5F,0x54,0x54,0x5F,0xD4,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"惜\",2920*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0xFE,0xAA,0xAB,0xAA,0xFE,0x00,0x08,0x06,0x01,0x02,0x04,\n0x02,0x0C,0x09,0x0C,0x02,0x04,/*\"熄\",2921*/},{\n\n0x78,0x00,0xFF,0x04,0x90,0xD5,0xB2,0xDA,0x92,0x95,0x90,0x08,0x06,0x01,0x06,0x00,\n0x07,0x00,0x0F,0x00,0x04,0x07,/*\"烯\",2922*/},{\n\n0x22,0x44,0x00,0x82,0xD6,0xAA,0xA6,0x8A,0xD1,0x89,0x01,0x04,0x02,0x00,0x0A,0x0A,\n0x06,0x03,0x06,0x0A,0x0B,0x02,/*\"溪\",2923*/},{\n\n0x10,0x21,0x02,0x40,0x20,0x18,0x27,0x44,0x84,0x64,0x1C,0x04,0x02,0x01,0x00,0x00,\n0x08,0x04,0x02,0x01,0x00,0x00,/*\"汐\",2924*/},{\n\n0x00,0xFF,0x05,0x2D,0xD5,0x85,0xDD,0x85,0x95,0xAD,0x07,0x08,0x07,0x02,0x03,0x02,\n0x02,0x0F,0x02,0x02,0x02,0x02,/*\"犀\",2925*/},{\n\n0xC8,0xFF,0x48,0x80,0xBE,0xEB,0xBE,0xD0,0x0F,0xF8,0x08,0x00,0x0F,0x00,0x08,0x07,\n0x0A,0x0E,0x05,0x02,0x05,0x08,/*\"檄\",2926*/},{\n\n0x88,0xFA,0xAE,0xAB,0xAE,0xFA,0x88,0xEF,0xAA,0xBA,0xC0,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"襲\",2927*/},{\n\n0x00,0xFE,0x0A,0x8A,0xBE,0xAA,0xEB,0xAA,0xBE,0x8A,0x0A,0x04,0x03,0x00,0x07,0x00,\n0x00,0x0F,0x00,0x04,0x07,0x00,/*\"席\",2928*/},{\n\n0x00,0xD5,0x49,0x41,0x5F,0x60,0x55,0x49,0x41,0xDF,0x00,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"習\",2929*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFE,0xAA,0xAB,0xAA,0xFE,0x00,0x08,0x05,0x02,0x0D,0x04,\n0x02,0x0C,0x09,0x0C,0x02,0x04,/*\"媳\",2930*/},{\n\n0x02,0xEA,0xAA,0xAA,0xAA,0xAF,0xAA,0xAA,0xAA,0xEA,0x02,0x02,0x0E,0x0B,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0B,0x0E,0x02,/*\"喜\",2931*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x50,0x4E,0xC8,0x7F,0xC8,0x48,0x40,0x08,0x09,0x07,0x04,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"銑\",2932*/},{\n\n0x22,0x44,0x00,0x50,0xCE,0x48,0x7F,0xC8,0x48,0x48,0x40,0x04,0x02,0x08,0x04,0x03,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"洗\",2933*/},{\n\n0x00,0x82,0x92,0xDA,0xD6,0xB2,0xB1,0x91,0x89,0xC1,0x80,0x08,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x09,/*\"系\",2934*/},{\n\n0xFE,0x02,0x32,0xCE,0x04,0xFA,0xA8,0xAF,0xA8,0xFA,0x04,0x0F,0x02,0x02,0x01,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"隙\",2935*/},{\n\n0x00,0xFC,0x24,0xBF,0x55,0xD5,0x6C,0x10,0xFF,0x88,0x6A,0x08,0x07,0x08,0x0D,0x09,\n0x0D,0x08,0x04,0x03,0x05,0x0E,/*\"戲\",2936*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0xFE,0x22,0xFE,0x22,0xFE,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x0F,0x04,0x07,0x04,0x0F,/*\"細\",2937*/},{\n\n0xFE,0x92,0xFE,0x00,0x86,0xAA,0xAA,0xFF,0xAA,0xAA,0x86,0x0F,0x04,0x0F,0x00,0x00,\n0x0E,0x0A,0x0B,0x0A,0x0E,0x00,/*\"瞎\",2938*/},{\n\n0x78,0x48,0xFF,0x48,0xFF,0x49,0x4F,0x00,0xC9,0x49,0xCF,0x04,0x04,0x03,0x02,0x0F,\n0x02,0x02,0x08,0x05,0x02,0x0D,/*\"蝦\",2939*/},{\n\n0x00,0xFF,0x01,0xFD,0x25,0x25,0xFD,0x25,0x25,0xFD,0x01,0x00,0x0F,0x08,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x08,/*\"匣\",2940*/},{\n\n0x0C,0xF5,0x5D,0x55,0x75,0x0F,0x55,0x55,0x5D,0x75,0x0C,0x00,0x0F,0x05,0x05,0x05,\n0x08,0x0B,0x05,0x05,0x0B,0x08,/*\"霞\",2941*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xA6,0xAA,0xFF,0xAA,0xA6,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0E,0x0A,0x0B,0x0A,0x0E,/*\"轄\",2942*/},{\n\n0xFE,0x22,0xFE,0x00,0xFF,0x49,0x4F,0x00,0xC9,0x49,0xCF,0x07,0x02,0x07,0x00,0x0F,\n0x02,0x02,0x08,0x05,0x02,0x0D,/*\"暇\",2943*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x74,0x84,0xFF,0x84,0x74,0x84,0x03,0x02,0x01,0x01,0x0B,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"峽\",2944*/},{\n\n0x20,0x10,0xFC,0x03,0x84,0x74,0x84,0xFF,0x84,0x74,0x84,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"俠\",2945*/},{\n\n0x8A,0x44,0xFB,0x00,0x84,0x74,0x84,0xFF,0x84,0x74,0x84,0x08,0x08,0x07,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"狹\",2946*/},{\n\n0x02,0x02,0x02,0x02,0xFE,0x02,0x12,0x22,0x42,0x82,0x02,0x00,0x00,0x00,0x00,0x0F,\n0x00,0x00,0x00,0x00,0x01,0x00,/*\"下\",2947*/},{\n\n0x00,0xFE,0x0A,0xEA,0x2A,0x7A,0xAB,0x6A,0xAA,0xEA,0x0A,0x08,0x07,0x0A,0x09,0x0B,\n0x05,0x05,0x05,0x0B,0x09,0x08,/*\"廈\",2948*/},{\n\n0x01,0x7D,0x55,0xD5,0x55,0x57,0x55,0x55,0x55,0x7D,0x01,0x08,0x0A,0x09,0x0B,0x05,\n0x05,0x05,0x05,0x0B,0x08,0x08,/*\"夏\",2949*/},{\n\n0xFE,0x02,0xFE,0xA0,0xE4,0x3F,0xA4,0xE4,0x3F,0xE4,0x20,0x03,0x01,0x03,0x08,0x07,\n0x01,0x08,0x07,0x08,0x0F,0x01,/*\"嚇\",2950*/},{\n\n0x88,0xFF,0x48,0xFE,0x12,0xF2,0x11,0x08,0xE7,0x04,0x1C,0x08,0x0F,0x04,0x03,0x00,\n0x07,0x08,0x06,0x01,0x06,0x08,/*\"掀\",2951*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFE,0x12,0xF1,0x10,0x0F,0xC4,0x1C,0x0A,0x0F,0x05,0x08,0x07,\n0x00,0x07,0x08,0x06,0x01,0x0E,/*\"鍁\",2952*/},{\n\n0x40,0x50,0x4E,0x48,0xC8,0x7F,0x48,0xC8,0x48,0x48,0x40,0x00,0x08,0x04,0x02,0x01,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"先\",2953*/},{\n\n0x20,0x10,0xFC,0x03,0xF8,0x00,0x00,0xFF,0x00,0x00,0xF8,0x00,0x00,0x0F,0x00,0x07,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"仙\",2954*/},{\n\n0x08,0xF4,0x53,0xFA,0x56,0xF0,0x25,0x26,0xFC,0x26,0x25,0x08,0x05,0x09,0x05,0x09,\n0x05,0x09,0x01,0x0F,0x01,0x01,/*\"鮮\",2955*/},{\n\n0xDC,0xB3,0xC8,0x00,0xAC,0xFB,0x0C,0xFB,0xAC,0xFF,0x4A,0x0E,0x00,0x06,0x00,0x0A,\n0x0F,0x08,0x0F,0x0A,0x07,0x0C,/*\"纖\",2956*/},{\n\n0xF8,0x48,0x9F,0x4A,0xFE,0x54,0xD4,0x04,0xFF,0x84,0x65,0x0F,0x09,0x0C,0x09,0x0F,\n0x02,0x0B,0x04,0x03,0x05,0x0E,/*\"鹹\",2957*/},{\n\n0x3F,0xA5,0xA5,0xB7,0xAD,0x80,0xA1,0x97,0x89,0x95,0x23,0x00,0x07,0x0C,0x05,0x06,\n0x04,0x05,0x06,0x0C,0x07,0x00,/*\"賢\",2958*/},{\n\n0x24,0xF2,0x09,0xA4,0x2A,0xF9,0x2A,0xA4,0x12,0xF2,0x12,0x00,0x0F,0x00,0x08,0x09,\n0x07,0x05,0x04,0x08,0x0F,0x00,/*\"銜\",2959*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x00,0x64,0x55,0xCE,0x44,0x24,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x06,0x05,0x04,0x06,0x0C,/*\"舷\",2960*/},{\n\n0xFF,0x15,0x15,0xFF,0xA0,0xA0,0xA0,0xFF,0x15,0x15,0xFF,0x0F,0x00,0x08,0x07,0x02,\n0x02,0x0A,0x0F,0x00,0x08,0x0F,/*\"閒\",2961*/},{\n\n0x11,0x22,0x00,0x72,0xCE,0x00,0xF2,0x02,0xFE,0x11,0x11,0x04,0x02,0x0A,0x04,0x0B,\n0x08,0x09,0x09,0x09,0x09,0x09,/*\"涎\",2962*/},{\n\n0xF2,0x92,0x9E,0x00,0x44,0x64,0x55,0xCE,0x44,0x24,0x04,0x08,0x08,0x07,0x00,0x04,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"弦\",2963*/},{\n\n0x88,0x78,0x0F,0xF8,0x55,0xFE,0x54,0xFE,0x55,0xF4,0x40,0x08,0x05,0x02,0x0D,0x03,\n0x0F,0x01,0x0F,0x03,0x05,0x08,/*\"嫌\",2964*/},{\n\n0x5F,0xB5,0x55,0x15,0x55,0xB5,0x5F,0x00,0xFD,0xAB,0xF9,0x0B,0x02,0x0B,0x00,0x0B,\n0x02,0x0B,0x00,0x0B,0x06,0x0B,/*\"顯\",2965*/},{\n\n0xFE,0x32,0xCE,0x00,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x0F,0x02,0x01,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"險\",2966*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0xFE,0xAA,0xAA,0xAA,0xFE,0x00,0x04,0x04,0x03,0x02,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"現\",2967*/},{\n\n0x00,0xF8,0xA8,0xFF,0xAA,0xDA,0x00,0x10,0xFF,0x12,0x14,0x08,0x07,0x05,0x0E,0x05,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"獻\",2968*/},{\n\n0x00,0xFF,0x55,0x55,0xFF,0x00,0x92,0xDA,0xB6,0x91,0xC9,0x05,0x03,0x09,0x0F,0x03,\n0x05,0x02,0x08,0x0F,0x02,0x04,/*\"縣\",2969*/},{\n\n0x00,0xFE,0x92,0xFE,0x80,0xBE,0x2A,0xEB,0xAA,0x3E,0x80,0x08,0x07,0x08,0x0F,0x04,\n0x03,0x08,0x0F,0x00,0x03,0x04,/*\"腺\",2970*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x04,0xE4,0x93,0x02,0xAA,0xE6,0x00,0x0F,0x04,0x02,0x0C,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"餡\",2971*/},{\n\n0x22,0x6A,0xAA,0x2B,0x2A,0xFE,0xAA,0xAB,0xAA,0xAA,0x22,0x09,0x04,0x00,0x08,0x09,\n0x04,0x03,0x04,0x04,0x09,0x08,/*\"羨\",2972*/},{\n\n0x26,0xEA,0xAA,0xAA,0xEA,0xBF,0xEA,0xAA,0xAA,0xEA,0x26,0x08,0x06,0x00,0x06,0x08,\n0x0A,0x0C,0x08,0x0C,0x02,0x0C,/*\"憲\",2973*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0xE4,0x93,0x02,0x8A,0xA6,0xE0,0x0F,0x02,0x02,0x01,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"陷\",2974*/},{\n\n0xFF,0x01,0x19,0xE7,0x00,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x0F,0x02,0x02,0x01,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"限\",2975*/},{\n\n0xDC,0xB3,0xC8,0x00,0x80,0xBE,0x2A,0xEB,0xAA,0x3E,0x80,0x0E,0x00,0x06,0x00,0x04,\n0x03,0x08,0x0F,0x00,0x03,0x04,/*\"線\",2976*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xFE,0x92,0x92,0x92,0x92,0xFE,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"相\",2977*/},{\n\n0x00,0xFE,0x22,0xA2,0xFA,0xA3,0x22,0xFA,0x4A,0x4A,0xFA,0x08,0x07,0x01,0x00,0x0F,\n0x00,0x01,0x0F,0x05,0x05,0x0F,/*\"廂\",2978*/},{\n\n0x4A,0xF9,0x4A,0x00,0xBA,0xAA,0xFA,0x83,0xFA,0xAA,0xBA,0x0A,0x0F,0x05,0x00,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"鑲\",2979*/},{\n\n0x48,0x48,0xAA,0x9A,0x8A,0xFE,0x89,0x99,0xA9,0x48,0x48,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"香\",2980*/},{\n\n0x24,0xA3,0xFA,0xA6,0x22,0xF4,0x53,0x52,0x56,0x52,0xF2,0x01,0x00,0x0F,0x00,0x01,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"箱\",2981*/},{\n\n0x02,0xBA,0xAA,0xEA,0xBA,0x83,0xBA,0xEA,0xAA,0xBA,0x02,0x0A,0x0A,0x06,0x0F,0x0A,\n0x02,0x02,0x07,0x0A,0x0A,0x0A,/*\"襄\",2982*/},{\n\n0x11,0x22,0x88,0x48,0xFF,0x28,0x48,0xFE,0x92,0x92,0xFE,0x04,0x02,0x00,0x00,0x0F,\n0x00,0x00,0x0F,0x04,0x04,0x0F,/*\"湘\",2983*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFD,0x56,0x7C,0x00,0xFE,0x32,0xCE,0x08,0x06,0x01,0x00,0x0F,\n0x05,0x02,0x04,0x0F,0x02,0x01,/*\"鄉\",2984*/},{\n\n0x89,0xAA,0xF8,0xAA,0x01,0x12,0xA2,0xFE,0x10,0xA2,0xFE,0x08,0x04,0x03,0x00,0x00,\n0x01,0x08,0x0F,0x01,0x08,0x0F,/*\"翔\",2985*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0x25,0x26,0xFC,0x26,0x25,0x00,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"祥\",2986*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x25,0x26,0xFC,0x26,0x25,0x00,0x0F,0x05,0x05,0x0F,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"詳\",2987*/},{\n\n0x44,0x24,0x14,0xFF,0x14,0x24,0xFE,0xAA,0xAA,0xAA,0xFE,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"想\",2988*/},{\n\n0x5A,0xB5,0x9A,0x80,0xFE,0xCB,0xAE,0xC0,0xFF,0xA5,0x1B,0x02,0x0E,0x0A,0x0B,0x0A,\n0x0E,0x0A,0x0B,0x0A,0x0E,0x02,/*\"響\",2989*/},{\n\n0x02,0xBA,0xAA,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0x3A,0x02,0x02,0x02,0x02,0x02,0x0A,\n0x0A,0x0E,0x03,0x02,0x02,0x02,/*\"享\",2990*/},{\n\n0x04,0x04,0xFC,0x04,0x00,0xFA,0xAA,0xAE,0xAA,0xAA,0xFA,0x02,0x02,0x01,0x01,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"項\",2991*/},{\n\n0x90,0x54,0xF4,0x5F,0x54,0x54,0x54,0x5F,0xF4,0x54,0x90,0x00,0x00,0x07,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0C,0x00,/*\"巷\",2992*/},{\n\n0x88,0x68,0xFF,0x48,0xBC,0xAB,0x6A,0xBA,0x2A,0xAE,0x78,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x05,0x0A,0x0F,0x02,0x04,/*\"橡\",2993*/},{\n\n0x10,0xFC,0x0B,0xBC,0xAB,0x6A,0xBA,0x2A,0x2E,0xB8,0x00,0x00,0x0F,0x00,0x0A,0x0A,\n0x05,0x0A,0x0F,0x01,0x02,0x04,/*\"像\",2994*/},{\n\n0xFC,0x04,0x04,0xE6,0x25,0x24,0x24,0xE4,0x04,0x04,0xFC,0x0F,0x00,0x00,0x03,0x02,\n0x02,0x02,0x03,0x08,0x08,0x0F,/*\"向\",2995*/},{\n\n0x08,0xBC,0xAA,0x6B,0x6A,0xBA,0x2A,0x2E,0xA8,0x78,0x00,0x08,0x0A,0x0A,0x05,0x05,\n0x0A,0x0F,0x01,0x02,0x04,0x04,/*\"象\",2996*/},{\n\n0x22,0x22,0xAA,0xAF,0xAA,0xFE,0xAA,0xAF,0xFA,0x22,0x22,0x08,0x07,0x02,0x0E,0x00,\n0x0F,0x00,0x0E,0x02,0x0F,0x00,/*\"蕭\",2997*/},{\n\n0x42,0xF2,0x2E,0xE2,0x02,0xF4,0x50,0x5F,0x50,0x54,0xF2,0x00,0x0F,0x04,0x0F,0x00,\n0x0F,0x01,0x01,0x01,0x09,0x0F,/*\"硝\",2998*/},{\n\n0x0C,0xE5,0xAD,0xB5,0xA5,0xBF,0xA5,0xB5,0xAD,0xE5,0x0C,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"霄\",2999*/},{\n\n0xF2,0x54,0x50,0x5F,0x50,0x54,0xF2,0x00,0xFC,0x00,0xFF,0x0F,0x01,0x01,0x01,0x01,\n0x09,0x0F,0x00,0x01,0x08,0x0F,/*\"削\",3000*/},{\n\n0xFE,0x02,0xFE,0x08,0xAA,0x6A,0x2F,0xBA,0xAA,0x6C,0x0A,0x03,0x01,0x03,0x01,0x00,\n0x01,0x09,0x0F,0x01,0x01,0x01,/*\"哮\",3001*/},{\n\n0x04,0xF7,0x95,0xB5,0xD7,0x9C,0xB7,0xD5,0x95,0xF7,0x04,0x00,0x0E,0x0B,0x0A,0x0E,\n0x00,0x0E,0x0A,0x0B,0x0E,0x00,/*\"囂\",3002*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xF2,0x54,0x5F,0x54,0xF2,0x08,0x09,0x07,0x05,0x04,\n0x00,0x0F,0x01,0x01,0x09,0x0F,/*\"銷\",3003*/},{\n\n0x10,0x22,0x04,0x00,0xF2,0x54,0x50,0x5F,0x50,0x54,0xF2,0x04,0x02,0x01,0x00,0x0F,\n0x01,0x01,0x01,0x01,0x09,0x0F,/*\"消\",3004*/},{\n\n0x06,0xE2,0xAA,0xB2,0xA2,0xBB,0xA2,0xB2,0xAA,0xE2,0x06,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"宵\",3005*/},{\n\n0x11,0x22,0x80,0x48,0xED,0xBA,0xAE,0xAA,0xAA,0xED,0x08,0x04,0x02,0x00,0x00,0x0F,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"淆\",3006*/},{\n\n0xFE,0x22,0xFE,0x00,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x07,0x02,0x07,0x00,0x0A,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"曉\",3007*/},{\n\n0x00,0xC0,0x30,0x00,0x00,0xFF,0x00,0x00,0x10,0x60,0x80,0x01,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x01,/*\"小\",3008*/},{\n\n0x08,0x2A,0xAA,0x6A,0x2F,0x3A,0xAA,0x6C,0x2A,0x09,0x08,0x02,0x01,0x01,0x01,0x09,\n0x09,0x0F,0x01,0x01,0x01,0x01,/*\"孝\",3009*/},{\n\n0x88,0x68,0xFF,0x28,0x44,0x24,0xD5,0x06,0xD4,0x24,0x44,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"校\",3010*/},{\n\n0x00,0xF2,0x54,0x50,0x50,0x5F,0x50,0x50,0x54,0xF2,0x00,0x00,0x0F,0x01,0x01,0x01,\n0x01,0x01,0x01,0x09,0x0F,0x00,/*\"肖\",3011*/},{\n\n0xFE,0x02,0xFE,0x08,0xEA,0xAA,0xFF,0x2A,0xEA,0xBE,0xC8,0x03,0x01,0x03,0x08,0x07,\n0x02,0x0F,0x00,0x0E,0x02,0x0F,/*\"嘯\",3012*/},{\n\n0x88,0x84,0xA3,0xA6,0xAA,0xE2,0x94,0x93,0x96,0x8A,0x82,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"笑\",3013*/},{\n\n0x44,0x34,0x85,0x06,0x94,0x24,0x10,0xEF,0x08,0xF8,0x08,0x08,0x04,0x02,0x01,0x02,\n0x04,0x08,0x04,0x03,0x04,0x08,/*\"效\",3014*/},{\n\n0x84,0x64,0xFF,0x24,0x2A,0x7F,0x2A,0xC2,0x3E,0x42,0x7E,0x00,0x00,0x0F,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"楔\",3015*/},{\n\n0x40,0x7E,0x40,0x3F,0x24,0x24,0x00,0x3F,0x48,0x44,0x72,0x08,0x08,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x08,0x08,/*\"些\",3016*/},{\n\n0x9F,0x75,0xD5,0x55,0x5F,0xC0,0x10,0x0F,0xC4,0x14,0x0C,0x06,0x05,0x04,0x0D,0x08,\n0x07,0x08,0x06,0x01,0x06,0x08,/*\"歇\",3017*/},{\n\n0x78,0x48,0xFF,0x48,0x1F,0xF5,0x5F,0xD0,0x0F,0xC4,0x1C,0x04,0x04,0x03,0x02,0x07,\n0x04,0x05,0x0F,0x06,0x01,0x0E,/*\"蠍\",3018*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x24,0x24,0xBF,0x24,0x24,0x20,0x02,0x02,0x0F,0x02,0x0A,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"鞋\",3019*/},{\n\n0x10,0xFF,0x10,0x80,0xD2,0x8A,0x87,0x82,0xD2,0x9E,0x80,0x00,0x0F,0x00,0x08,0x07,\n0x08,0x0F,0x04,0x03,0x08,0x0F,/*\"協\",3020*/},{\n\n0x88,0x88,0xFF,0x48,0x84,0x74,0x84,0xFF,0x84,0x74,0x84,0x00,0x08,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"挾\",3021*/},{\n\n0x88,0xFF,0x48,0x20,0xF6,0x5C,0xD4,0x57,0xFC,0x54,0xD6,0x08,0x0F,0x00,0x00,0x0F,\n0x01,0x0E,0x0A,0x0E,0x01,0x0F,/*\"攜\",3022*/},{\n\n0x00,0x32,0xAA,0x62,0xFE,0x22,0x00,0xFE,0x02,0x32,0xCE,0x04,0x02,0x01,0x08,0x0F,\n0x00,0x00,0x0F,0x02,0x02,0x01,/*\"邪\",3023*/},{\n\n0x08,0x44,0x4A,0xF9,0x4A,0x44,0x92,0xA4,0x80,0xFF,0x40,0x02,0x01,0x08,0x0F,0x01,\n0x02,0x00,0x00,0x00,0x0F,0x00,/*\"斜\",3024*/},{\n\n0x50,0xB2,0x9A,0xD6,0xF3,0x82,0xD2,0xBA,0x9A,0xD6,0x70,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"脅\",3025*/},{\n\n0x54,0x55,0x56,0x54,0x00,0xDF,0x52,0x6A,0x4F,0x52,0xD9,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"諧\",3026*/},{\n\n0x06,0xFA,0xAA,0xAA,0xA6,0x83,0xAA,0xAA,0xAA,0xFA,0x06,0x04,0x0A,0x03,0x0A,0x02,\n0x0A,0x02,0x0A,0x02,0x0A,0x0E,/*\"寫\",3027*/},{\n\n0x88,0x68,0xFF,0x48,0xF4,0x44,0xF4,0x44,0xFF,0x84,0x65,0x00,0x00,0x0F,0x04,0x03,\n0x00,0x0B,0x04,0x03,0x05,0x0E,/*\"械\",3028*/},{\n\n0x14,0xD3,0x12,0xFE,0x92,0x92,0x00,0xFE,0x02,0x02,0xFE,0x04,0x07,0x04,0x03,0x02,\n0x02,0x00,0x0F,0x00,0x02,0x03,/*\"卸\",3029*/},{\n\n0x42,0xBD,0x95,0xBD,0x97,0xFC,0x89,0x97,0xF9,0x95,0x17,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蟹\",3030*/},{\n\n0x30,0xFF,0x08,0xF4,0x53,0xFA,0x56,0xF9,0x27,0xF9,0x2F,0x00,0x0F,0x08,0x07,0x01,\n0x07,0x09,0x0F,0x01,0x0F,0x01,/*\"懈\",3031*/},{\n\n0x11,0x22,0x10,0xFE,0x10,0x10,0xFF,0x10,0x10,0xFF,0x10,0x04,0x02,0x00,0x0F,0x08,\n0x08,0x09,0x09,0x09,0x09,0x08,/*\"泄\",3032*/},{\n\n0x22,0x44,0x06,0xFA,0xAA,0xA6,0x83,0xAA,0xAA,0xFA,0x06,0x04,0x02,0x04,0x0A,0x03,\n0x0A,0x02,0x0A,0x02,0x0A,0x0E,/*\"瀉\",3033*/},{\n\n0x55,0x56,0x54,0x80,0xFE,0xAB,0xFE,0x40,0x88,0xFF,0x08,0x0F,0x05,0x0F,0x04,0x02,\n0x09,0x0F,0x00,0x08,0x0F,0x00,/*\"謝\",3034*/},{\n\n0x00,0xFF,0x05,0xED,0xB5,0xA5,0xBD,0xA5,0xA5,0xB5,0xEF,0x08,0x07,0x00,0x0F,0x02,\n0x02,0x02,0x02,0x02,0x0A,0x0F,/*\"屑\",3035*/},{\n\n0x42,0x52,0x77,0xDA,0x72,0x52,0x42,0xF2,0x97,0x8A,0x8A,0x08,0x05,0x09,0x0F,0x01,\n0x05,0x08,0x07,0x00,0x0F,0x00,/*\"薪\",3036*/},{\n\n0x04,0x84,0x04,0xCF,0x04,0x24,0xC4,0x0F,0x04,0x84,0x04,0x04,0x03,0x00,0x07,0x08,\n0x08,0x08,0x08,0x0E,0x00,0x07,/*\"芯\",3037*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x40,0x54,0x65,0xC6,0x64,0x54,0x40,0x08,0x09,0x07,0x04,0x00,\n0x01,0x01,0x0F,0x01,0x01,0x00,/*\"鋅\",3038*/},{\n\n0x00,0xFE,0x12,0x12,0xF1,0x11,0x10,0x0F,0xC4,0x14,0x0C,0x08,0x07,0x00,0x00,0x0F,\n0x00,0x08,0x06,0x01,0x06,0x08,/*\"欣\",3039*/},{\n\n0x20,0x24,0x2C,0x34,0x25,0xE6,0x24,0x34,0x2C,0x24,0x20,0x00,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x00,/*\"辛\",3040*/},{\n\n0x20,0xAA,0xB2,0xE3,0xB2,0xAA,0x00,0xFE,0x12,0xF2,0x11,0x04,0x02,0x08,0x0F,0x00,\n0x0A,0x04,0x03,0x00,0x0F,0x00,/*\"新\",3041*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0xFE,0x12,0x12,0xF1,0x11,0x10,0x00,0x00,0x0F,0x00,0x08,\n0x07,0x00,0x00,0x0F,0x00,0x00,/*\"忻\",3042*/},{\n\n0x00,0xC0,0x00,0xF0,0x02,0x04,0x18,0x00,0x00,0x20,0xC0,0x02,0x01,0x00,0x07,0x08,\n0x08,0x08,0x08,0x0E,0x00,0x01,/*\"心\",3043*/},{\n\n0x10,0xFC,0x03,0x04,0x54,0x54,0x55,0x56,0x54,0x54,0x04,0x00,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"信\",3044*/},{\n\n0x30,0x1E,0xF5,0xD0,0xBF,0x95,0xBF,0xD0,0xF5,0x1F,0x30,0x02,0x02,0x09,0x0A,0x06,\n0x02,0x0A,0x0E,0x01,0x02,0x02,/*\"釁\",3045*/},{\n\n0x00,0xDF,0x95,0x95,0x95,0xF5,0x95,0x95,0x95,0x9F,0x00,0x09,0x08,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x08,0x08,/*\"星\",3046*/},{\n\n0x00,0xFF,0x49,0xFF,0x00,0xDF,0x95,0xF5,0x95,0x9F,0x00,0x08,0x07,0x08,0x0F,0x09,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"腥\",3047*/},{\n\n0x10,0x8A,0x44,0xFB,0x00,0xDF,0x95,0xF5,0x95,0x9F,0x00,0x01,0x08,0x08,0x07,0x09,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"猩\",3048*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0xDF,0x95,0xF5,0x95,0x9F,0x00,0x00,0x00,0x0F,0x00,0x09,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"惺\",3049*/},{\n\n0x00,0xFE,0x49,0x00,0xFF,0x29,0xFF,0x00,0x49,0xFF,0x00,0x01,0x09,0x05,0x01,0x01,\n0x01,0x01,0x01,0x05,0x09,0x01,/*\"興\",3050*/},{\n\n0x22,0xFE,0x22,0x22,0xFE,0x22,0x00,0xFC,0x00,0x00,0xFF,0x08,0x07,0x00,0x00,0x0F,\n0x00,0x00,0x01,0x08,0x08,0x0F,/*\"刑\",3051*/},{\n\n0x90,0x52,0x3E,0x12,0x12,0x7E,0x12,0x00,0x3E,0x80,0xFF,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"型\",3052*/},{\n\n0x22,0xFE,0x22,0x22,0xFE,0x22,0x00,0x88,0x44,0x23,0x18,0x08,0x07,0x00,0x00,0x0F,\n0x00,0x08,0x08,0x04,0x02,0x01,/*\"形\",3053*/},{\n\n0x22,0xFE,0x22,0x22,0xFE,0x22,0x00,0xFE,0x02,0x32,0xCE,0x08,0x07,0x00,0x00,0x0F,\n0x00,0x00,0x0F,0x02,0x02,0x01,/*\"邢\",3054*/},{\n\n0x48,0x24,0xF2,0x09,0x10,0x12,0x12,0x12,0xF2,0x12,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"行\",3055*/},{\n\n0xFD,0xA5,0x9F,0xA5,0xFD,0x00,0xDF,0x95,0xF5,0x95,0x9F,0x0F,0x04,0x04,0x04,0x0F,\n0x01,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"醒\",3056*/},{\n\n0x10,0x94,0xB4,0xD4,0x94,0x9F,0x94,0xD4,0xB4,0x94,0x10,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"幸\",3057*/},{\n\n0x44,0x44,0xA4,0x94,0x8C,0xFF,0x8C,0x94,0xA4,0x44,0x44,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x0F,0x00,0x00,/*\"杏\",3058*/},{\n\n0x78,0x00,0xFF,0x08,0x20,0x9C,0x88,0xFF,0x88,0x88,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"性\",3059*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0x9C,0x88,0xFF,0x88,0x88,0x00,0x08,0x05,0x02,0x05,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"姓\",3060*/},{\n\n0x00,0x7E,0x42,0xC2,0x42,0x42,0x42,0xC2,0x42,0x7E,0x00,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"兄\",3061*/},{\n\n0x00,0x7C,0x40,0xD1,0x4A,0x44,0x4A,0xD1,0x40,0x7C,0x00,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"兇\",3062*/},{\n\n0xFF,0x49,0xFF,0x08,0xE4,0x97,0x64,0x94,0xE4,0x04,0xFC,0x07,0x08,0x0F,0x00,0x03,\n0x02,0x02,0x02,0x0B,0x08,0x07,/*\"胸\",3063*/},{\n\n0x20,0x10,0xEC,0x07,0x94,0x64,0x94,0x04,0xE4,0x04,0xFC,0x00,0x00,0x03,0x02,0x02,\n0x02,0x02,0x0A,0x0B,0x08,0x07,/*\"匈\",3064*/},{\n\n0x11,0x22,0x08,0xE4,0x07,0x94,0x64,0x94,0xE4,0x04,0xFC,0x04,0x02,0x00,0x03,0x02,\n0x02,0x02,0x0A,0x0B,0x08,0x07,/*\"洶\",3065*/},{\n\n0x84,0x74,0x8F,0x64,0x04,0x10,0xFC,0x27,0xFC,0x25,0x24,0x00,0x06,0x05,0x04,0x0E,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"雄\",3066*/},{\n\n0x00,0xF6,0x55,0x54,0x54,0xF6,0x00,0xE7,0x8A,0x49,0x2C,0x08,0x07,0x01,0x05,0x09,\n0x03,0x04,0x09,0x02,0x06,0x0B,/*\"熊\",3067*/},{\n\n0x20,0x10,0xFC,0x03,0x08,0x88,0x68,0xFF,0x68,0x88,0x08,0x00,0x00,0x0F,0x00,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"休\",3068*/},{\n\n0x10,0xFC,0x03,0xF8,0x10,0x94,0x8B,0x4A,0x2A,0x96,0x10,0x00,0x0F,0x00,0x03,0x08,\n0x0A,0x0A,0x09,0x05,0x04,0x02,/*\"修\",3069*/},{\n\n0x22,0x2A,0xAA,0xEB,0xBA,0xAE,0xAA,0xAB,0xAA,0x22,0x22,0x04,0x0A,0x09,0x0A,0x0E,\n0x0B,0x0A,0x0A,0x0F,0x08,0x08,/*\"羞\",3070*/},{\n\n0x88,0x68,0xFF,0x48,0x8A,0x62,0x5A,0x46,0x42,0x42,0xC2,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"朽\",3071*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0xAA,0xAB,0xAA,0xAA,0xFE,0x00,0x03,0x01,0x03,0x0A,0x0A,\n0x06,0x03,0x06,0x0B,0x0A,0x0A,/*\"嗅\",3072*/},{\n\n0x4A,0xF9,0x4A,0x08,0xEA,0xAA,0xFF,0x2A,0xEA,0xBE,0xC8,0x0A,0x0F,0x05,0x08,0x07,\n0x02,0x0F,0x00,0x0E,0x02,0x0F,/*\"鏽\",3073*/},{\n\n0x48,0x48,0x6A,0xDA,0x4A,0x7E,0x49,0xD9,0x29,0x48,0x48,0x00,0x08,0x04,0x03,0x00,\n0x00,0x08,0x09,0x09,0x07,0x00,/*\"秀\",3074*/},{\n\n0x45,0xF6,0xAC,0x00,0xF8,0x48,0x48,0xFF,0x48,0x48,0xF8,0x00,0x0F,0x00,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"袖\",3075*/},{\n\n0xDC,0xB3,0xC8,0x08,0xEA,0xAA,0xFF,0x2A,0xEA,0xBE,0xC8,0x0E,0x00,0x06,0x08,0x07,\n0x02,0x0F,0x00,0x0E,0x02,0x0F,/*\"繡\",3076*/},{\n\n0x10,0xFF,0x10,0x00,0xFC,0x24,0xA4,0x3F,0xD5,0x55,0x6C,0x04,0x07,0x02,0x08,0x07,\n0x0A,0x0F,0x08,0x0F,0x0A,0x09,/*\"墟\",3077*/},{\n\n0x00,0xF8,0x88,0x88,0x88,0x08,0xFF,0x08,0x89,0x6A,0x08,0x08,0x07,0x00,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x0F,/*\"戌\",3078*/},{\n\n0x8C,0xA5,0xAD,0xAD,0x85,0xBF,0x85,0xAD,0xAD,0xA5,0x8C,0x00,0x0E,0x02,0x02,0x0E,\n0x03,0x0E,0x02,0x0A,0x0E,0x00,/*\"需\",3079*/},{\n\n0x00,0xFC,0x24,0x24,0x24,0xBF,0x55,0xD5,0x55,0x45,0x6C,0x08,0x07,0x08,0x0B,0x0A,\n0x0F,0x08,0x0F,0x0A,0x0B,0x08,/*\"虛\",3080*/},{\n\n0xFC,0x04,0xFC,0x00,0xFC,0x24,0xA4,0x3F,0xD5,0x55,0x6C,0x03,0x01,0x03,0x08,0x07,\n0x0A,0x0F,0x08,0x0F,0x0A,0x0B,/*\"噓\",3081*/},{\n\n0x88,0x44,0x23,0x98,0x00,0xFA,0xAA,0xAE,0xAA,0xAA,0xFA,0x08,0x04,0x02,0x01,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"須\",3082*/},{\n\n0x44,0x22,0xF1,0x08,0x48,0x54,0x52,0xF1,0x52,0x54,0x48,0x00,0x00,0x0F,0x00,0x04,\n0x03,0x08,0x0F,0x00,0x01,0x06,/*\"徐\",3083*/},{\n\n0x54,0x55,0x56,0x54,0x88,0x87,0x84,0xFC,0x84,0x84,0x80,0x0F,0x05,0x05,0x0F,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"許\",3084*/},{\n\n0x8A,0xAA,0xBA,0xAF,0xEA,0xAE,0xAA,0x9F,0x8A,0xCA,0x8A,0x00,0x00,0x0F,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0F,0x00,0x01,/*\"蓄\",3085*/},{\n\n0xFD,0xA5,0x9F,0xA5,0xFD,0x00,0xF1,0x86,0x78,0x86,0xF1,0x0F,0x04,0x04,0x04,0x0F,\n0x00,0x07,0x04,0x04,0x04,0x0F,/*\"酗\",3086*/},{\n\n0x08,0x44,0x4A,0xF9,0x4A,0x44,0x10,0xEF,0x08,0xF8,0x08,0x02,0x01,0x08,0x0F,0x01,\n0x02,0x08,0x05,0x02,0x05,0x08,/*\"敘\",3087*/},{\n\n0x08,0xFF,0x08,0xF8,0x00,0xFF,0x11,0x11,0x11,0xFF,0x00,0x08,0x07,0x00,0x07,0x08,\n0x09,0x09,0x09,0x09,0x09,0x0C,/*\"旭\",3088*/},{\n\n0x00,0xFE,0x82,0x8A,0xAA,0xAA,0xCB,0xAA,0x9A,0x8A,0x82,0x08,0x07,0x00,0x00,0x00,\n0x08,0x0F,0x00,0x00,0x02,0x01,/*\"序\",3089*/},{\n\n0x22,0xAA,0xAE,0xAA,0xBA,0xAB,0xAA,0xA6,0xA2,0xB2,0x62,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"畜\",3090*/},{\n\n0x78,0x00,0xFF,0x04,0xF8,0x08,0xFC,0x0B,0xF8,0x08,0xF8,0x00,0x00,0x0F,0x08,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"恤\",3091*/},{\n\n0x02,0x2A,0xAE,0xD3,0x92,0xAE,0x80,0x5E,0x12,0x12,0x1E,0x00,0x0A,0x06,0x02,0x0B,\n0x0E,0x02,0x02,0x07,0x0A,0x00,/*\"絮\",3092*/},{\n\n0x88,0x78,0x0F,0xF8,0x11,0xCD,0x51,0x5F,0x55,0xD5,0x13,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x01,0x01,0x09,0x0F,0x00,/*\"婿\",3093*/},{\n\n0xDC,0xB3,0xC8,0x10,0x90,0xD4,0x7F,0x54,0x58,0xD4,0x12,0x0E,0x00,0x06,0x01,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"緒\",3094*/},{\n\n0xDC,0xB3,0xC8,0x00,0x3A,0xEA,0xBA,0xAF,0xBA,0xEA,0x3A,0x0E,0x00,0x06,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"續\",3095*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xF8,0x42,0x42,0xFE,0x42,0x42,0x40,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"軒\",3096*/},{\n\n0xFC,0x04,0x04,0xFC,0x06,0xEA,0xAA,0xAB,0xAA,0xEA,0x06,0x03,0x01,0x01,0x03,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"喧\",3097*/},{\n\n0x06,0xEA,0xAA,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xEA,0x06,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"宣\",3098*/},{\n\n0x40,0xFF,0x55,0xD5,0xFF,0x40,0xAD,0x3B,0xE9,0xA5,0x31,0x09,0x04,0x01,0x05,0x0A,\n0x0D,0x08,0x0D,0x01,0x04,0x09,/*\"懸\",3099*/},{\n\n0x08,0xF8,0x49,0x4A,0xD0,0x08,0xD7,0x14,0xF4,0x14,0x34,0x08,0x07,0x08,0x08,0x07,\n0x08,0x07,0x08,0x0F,0x09,0x09,/*\"旋\",3100*/},{\n\n0x04,0x44,0x64,0x54,0x4D,0xC6,0x44,0x24,0x04,0x04,0x04,0x00,0x04,0x04,0x06,0x05,\n0x04,0x04,0x04,0x05,0x0E,0x00,/*\"玄\",3101*/},{\n\n0x11,0xF2,0x00,0x4F,0xF5,0x57,0x40,0x4F,0xF5,0x57,0x18,0x08,0x07,0x09,0x0D,0x0B,\n0x09,0x09,0x09,0x0B,0x0D,0x09,/*\"選\",3102*/},{\n\n0x88,0xFE,0x12,0xEE,0xAA,0xEA,0xBB,0xE2,0x56,0xFA,0x56,0x08,0x07,0x08,0x03,0x0A,\n0x03,0x0A,0x03,0x09,0x0F,0x01,/*\"癬\",3103*/},{\n\n0xFE,0x92,0xFE,0x00,0x44,0x64,0x55,0xCE,0x44,0x24,0x04,0x0F,0x04,0x0F,0x00,0x04,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"眩\",3104*/},{\n\n0xD8,0xB4,0x93,0xC8,0x04,0xFB,0x4A,0x4A,0xFA,0x02,0xFE,0x0C,0x02,0x04,0x02,0x04,\n0x07,0x02,0x02,0x0B,0x08,0x07,/*\"絢\",3105*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xF2,0x0C,0xFB,0x40,0xFF,0x10,0x0C,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x00,0x07,0x08,0x0E,/*\"靴\",3106*/},{\n\n0x02,0xF2,0x5A,0x57,0x72,0x02,0x92,0xB7,0xDA,0xB2,0x92,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x00,0x02,0x0F,0x02,0x00,/*\"薛\",3107*/},{\n\n0x60,0x3F,0xA5,0xA0,0xB5,0xAA,0xB5,0xA0,0x25,0x3F,0x60,0x02,0x02,0x02,0x0A,0x0A,\n0x0E,0x03,0x02,0x02,0x02,0x02,/*\"學\",3108*/},{\n\n0x1C,0x04,0x04,0xF4,0x05,0x06,0x04,0xF4,0x04,0x04,0x1C,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x00,0x03,0x04,0x08,/*\"穴\",3109*/},{\n\n0x0C,0xA5,0xAD,0xAD,0x85,0xBF,0x85,0xAD,0xAD,0xA5,0x0C,0x00,0x08,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"雪\",3110*/},{\n\n0x00,0xF8,0x08,0x0C,0xFB,0x08,0xF8,0x08,0x08,0xF8,0x00,0x08,0x0F,0x08,0x08,0x0F,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"血\",3111*/},{\n\n0xF4,0x55,0x15,0xFF,0x15,0x55,0xF4,0x08,0xFF,0x08,0xF8,0x0D,0x05,0x0D,0x07,0x0D,\n0x05,0x0D,0x08,0x07,0x08,0x0F,/*\"勳\",3112*/},{\n\n0x78,0x00,0xFF,0x08,0xF4,0x55,0x15,0xFF,0x15,0x55,0xF4,0x08,0x06,0x01,0x06,0x0D,\n0x05,0x0D,0x07,0x0D,0x05,0x0D,/*\"燻\",3113*/},{\n\n0x24,0xF2,0x09,0x00,0xFE,0x0A,0xEA,0xAA,0xBE,0xA9,0xE9,0x00,0x0F,0x00,0x08,0x07,\n0x00,0x0F,0x0A,0x0A,0x0A,0x0F,/*\"循\",3114*/},{\n\n0x08,0x04,0xFB,0x4A,0x4A,0x4A,0x4A,0xFA,0x02,0x02,0xFE,0x00,0x00,0x07,0x02,0x02,\n0x02,0x02,0x0B,0x08,0x08,0x07,/*\"旬\",3115*/},{\n\n0x54,0x55,0x56,0x54,0x04,0xFB,0x4A,0x4A,0xFA,0x02,0xFE,0x0F,0x05,0x05,0x0F,0x00,\n0x07,0x02,0x02,0x0B,0x08,0x07,/*\"詢\",3116*/},{\n\n0x00,0x51,0xD5,0x55,0x15,0x15,0xD5,0x55,0x55,0xDF,0x00,0x05,0x05,0x0D,0x05,0x05,\n0x04,0x05,0x0D,0x0F,0x05,0x04,/*\"尋\",3117*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x00,0xFF,0x00,0xFE,0x00,0xFF,0x06,0x00,0x0A,0x08,0x07,\n0x08,0x07,0x00,0x07,0x00,0x0F,/*\"馴\",3118*/},{\n\n0x21,0xE2,0x10,0x6C,0x83,0x10,0x6C,0x83,0x10,0x6C,0x83,0x08,0x07,0x08,0x08,0x09,\n0x08,0x08,0x09,0x08,0x08,0x09,/*\"巡\",3119*/},{\n\n0x82,0x7E,0x92,0xF2,0x04,0xFB,0x4A,0x4A,0xFA,0x02,0xFE,0x08,0x04,0x02,0x01,0x00,\n0x07,0x02,0x02,0x0B,0x08,0x07,/*\"殉\",3120*/},{\n\n0x22,0x44,0x22,0x22,0xFE,0x22,0x22,0x22,0xFE,0x00,0x80,0x04,0x02,0x01,0x00,0x0F,\n0x00,0x00,0x00,0x03,0x04,0x0F,/*\"汛\",3121*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0xFF,0x00,0xFE,0x00,0xFF,0x00,0x0F,0x05,0x05,0x0F,\n0x08,0x07,0x00,0x07,0x00,0x0F,/*\"訓\",3122*/},{\n\n0x54,0x55,0x56,0x54,0x22,0xFE,0x22,0x22,0xFE,0x00,0x00,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x00,0x00,0x03,0x04,0x0E,/*\"訊\",3123*/},{\n\n0x11,0xF2,0x00,0x42,0xFA,0x26,0x00,0x6A,0xDE,0x49,0x65,0x08,0x07,0x08,0x0C,0x0F,\n0x08,0x0A,0x0D,0x0F,0x09,0x0A,/*\"遜\",3124*/},{\n\n0x21,0xE2,0x00,0x22,0x22,0xFE,0x22,0x22,0xFE,0x00,0x80,0x08,0x07,0x08,0x08,0x08,\n0x0B,0x08,0x08,0x08,0x09,0x0B,/*\"迅\",3125*/},{\n\n0x00,0xFF,0x01,0xF7,0x55,0xF7,0x89,0x69,0x1F,0x69,0x8D,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"壓\",3126*/},{\n\n0x88,0x88,0xFF,0x48,0xFE,0x92,0x92,0xFE,0x92,0x92,0xFE,0x00,0x08,0x0F,0x00,0x01,\n0x00,0x00,0x0F,0x00,0x00,0x01,/*\"押\",3127*/},{\n\n0x32,0xAA,0x62,0xFE,0x22,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x02,0x01,0x08,0x0F,0x00,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鴉\",3128*/},{\n\n0xFE,0x92,0xFE,0x92,0xFE,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x01,0x00,0x0F,0x00,0x01,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鴨\",3129*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0x32,0x2A,0xA2,0x62,0xFE,0x22,0x03,0x01,0x01,0x03,0x04,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"呀\",3130*/},{\n\n0x01,0x02,0x04,0x08,0x10,0xE0,0x10,0x08,0x04,0x02,0x01,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"丫\",3131*/},{\n\n0x02,0xD2,0x92,0x97,0x92,0x92,0x92,0xF7,0x92,0x92,0x82,0x08,0x08,0x04,0x04,0x02,\n0x01,0x08,0x0F,0x00,0x00,0x00,/*\"芽\",3132*/},{\n\n0x00,0x32,0x2A,0x22,0x22,0xA2,0x62,0xFE,0x22,0x22,0x20,0x04,0x04,0x02,0x02,0x01,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"牙\",3133*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x32,0xAA,0x62,0xFE,0x22,0x04,0x04,0x03,0x02,0x07,\n0x04,0x02,0x01,0x08,0x0F,0x00,/*\"蚜\",3134*/},{\n\n0x00,0xFB,0x8A,0xAA,0xAA,0xAB,0xFA,0xAA,0xAA,0xAB,0x88,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"崖\",3135*/},{\n\n0x24,0xF2,0x49,0x7A,0x4E,0x4A,0x7A,0x40,0x12,0xF2,0x12,0x00,0x0F,0x00,0x0F,0x09,\n0x09,0x0F,0x00,0x08,0x0F,0x00,/*\"衙\",3136*/},{\n\n0x22,0x44,0x00,0xFE,0x42,0x52,0x52,0x7E,0x52,0x52,0x42,0x04,0x02,0x08,0x07,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"涯\",3137*/},{\n\n0x32,0xAA,0x62,0xFE,0x22,0x10,0xFC,0x27,0xFC,0x25,0x24,0x02,0x01,0x08,0x0F,0x00,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"雅\",3138*/},{\n\n0xFC,0x04,0xFC,0x00,0xF2,0x12,0x1E,0x02,0x1E,0x12,0xF2,0x03,0x01,0x03,0x00,0x09,\n0x09,0x0F,0x08,0x0F,0x09,0x09,/*\"啞\",3139*/},{\n\n0x02,0xF2,0x12,0x1E,0x02,0x02,0x02,0x1E,0x12,0xF2,0x02,0x08,0x09,0x09,0x0F,0x08,\n0x08,0x08,0x0F,0x09,0x09,0x08,/*\"亞\",3140*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x32,0x2A,0xA2,0x62,0xFE,0x22,0x0F,0x05,0x05,0x0F,0x04,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"訝\",3141*/},{\n\n0x11,0x91,0x7D,0x51,0x51,0x5F,0x55,0x55,0x55,0x55,0x11,0x0C,0x01,0x0D,0x01,0x0D,\n0x01,0x0D,0x01,0x09,0x09,0x07,/*\"焉\",3142*/},{\n\n0xFE,0x02,0xFE,0x00,0xFF,0x11,0x91,0x7D,0x91,0x11,0xFF,0x03,0x01,0x03,0x00,0x0F,\n0x05,0x04,0x04,0x04,0x05,0x0F,/*\"咽\",3143*/},{\n\n0xFF,0x95,0x5F,0xE8,0x58,0xEC,0x58,0xE8,0x5F,0x95,0xFF,0x0F,0x00,0x00,0x07,0x05,\n0x07,0x0D,0x0F,0x08,0x00,0x0F,/*\"閹\",3144*/},{\n\n0x78,0x00,0xFF,0x04,0x7A,0x4A,0x7E,0xCA,0x7E,0x4A,0x7A,0x08,0x06,0x01,0x0E,0x09,\n0x09,0x09,0x0F,0x09,0x09,0x09,/*\"煙\",3145*/},{\n\n0x22,0x44,0x22,0xF2,0xAA,0xA6,0xF3,0xA6,0xAA,0xF2,0x22,0x04,0x02,0x00,0x07,0x02,\n0x02,0x07,0x0A,0x0A,0x0B,0x0C,/*\"淹\",3146*/},{\n\n0xFE,0xAA,0xEE,0xBA,0x04,0xFB,0xDA,0xAE,0xDA,0x8A,0xFA,0x08,0x0E,0x0A,0x0A,0x0E,\n0x0A,0x0E,0x0A,0x0A,0x0E,0x08,/*\"鹽\",3147*/},{\n\n0x00,0xF7,0x55,0xD5,0x77,0xD0,0x57,0x95,0x75,0xD7,0x50,0x08,0x07,0x04,0x07,0x05,\n0x0F,0x0A,0x05,0x02,0x05,0x08,/*\"嚴\",3148*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x22,0xFE,0x22,0x22,0xFE,0x22,0x00,0x07,0x02,0x07,0x00,\n0x08,0x07,0x00,0x00,0x0F,0x00,/*\"研\",3149*/},{\n\n0x78,0x48,0xFF,0x48,0x32,0xCE,0x00,0xF2,0x02,0xFF,0x11,0x04,0x04,0x03,0x02,0x0A,\n0x07,0x08,0x09,0x09,0x09,0x09,/*\"蜒\",3150*/},{\n\n0x00,0xE3,0xBA,0xAA,0xFA,0xA3,0xA2,0x3A,0xEA,0xBB,0xA0,0x08,0x07,0x08,0x0F,0x0A,\n0x0F,0x04,0x0B,0x04,0x0B,0x08,/*\"巖\",3151*/},{\n\n0x02,0x32,0x2A,0xE6,0x00,0xF2,0x02,0x02,0xFE,0x21,0x21,0x08,0x05,0x02,0x05,0x08,\n0x0B,0x0A,0x0A,0x0B,0x0A,0x0A,/*\"延\",3152*/},{\n\n0x04,0x54,0x54,0x54,0x55,0x56,0x54,0x54,0x54,0x54,0x04,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"言\",3153*/},{\n\n0x00,0xF2,0x36,0xAB,0xB6,0x62,0x00,0xFA,0xAE,0xAA,0xFA,0x08,0x07,0x00,0x0A,0x0A,\n0x05,0x00,0x0B,0x06,0x06,0x0B,/*\"顏\",3154*/},{\n\n0xFF,0x15,0x15,0x5F,0xA0,0x20,0xE0,0x9F,0x15,0x15,0xFF,0x0F,0x00,0x00,0x0F,0x0A,\n0x08,0x0A,0x0F,0x00,0x08,0x0F,/*\"閻\",3155*/},{\n\n0x20,0x24,0x92,0x10,0x08,0xC7,0x08,0x08,0x14,0x92,0x20,0x08,0x09,0x04,0x04,0x02,\n0x01,0x02,0x04,0x05,0x08,0x08,/*\"炎\",3156*/},{\n\n0x10,0x21,0x02,0xD0,0x4F,0x41,0x41,0x41,0x4F,0xD0,0x10,0x04,0x02,0x01,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"沿\",3157*/},{\n\n0x12,0x12,0xEA,0xAA,0xA6,0xF3,0xA6,0xAA,0xEA,0x12,0x12,0x00,0x00,0x07,0x02,0x02,\n0x07,0x0A,0x0A,0x0B,0x08,0x0E,/*\"奄\",3158*/},{\n\n0x88,0x88,0xFF,0x48,0x12,0xEA,0xA6,0xF3,0xA6,0xEA,0x12,0x00,0x08,0x0F,0x00,0x00,\n0x07,0x02,0x07,0x0A,0x0B,0x0C,/*\"掩\",3159*/},{\n\n0xFF,0x49,0x49,0xFF,0x00,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x07,0x02,0x02,0x07,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"眼\",3160*/},{\n\n0x44,0x22,0xF1,0x08,0x10,0x21,0x02,0x00,0x12,0xF2,0x12,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"衍\",3161*/},{\n\n0x10,0x22,0x04,0x00,0xE6,0xAA,0xAA,0xFB,0xAA,0xAA,0xE6,0x04,0x02,0x01,0x00,0x0B,\n0x06,0x02,0x03,0x02,0x06,0x0B,/*\"演\",3162*/},{\n\n0xBC,0xAA,0xBF,0xAA,0xBF,0x2A,0x4A,0x6A,0x5F,0x4A,0x6A,0x0B,0x0E,0x0A,0x0E,0x0B,\n0x08,0x0F,0x09,0x0F,0x09,0x0F,/*\"豔\",3163*/},{\n\n0x10,0xFF,0x10,0x00,0xFF,0x81,0xBF,0xEB,0xAB,0xBF,0x81,0x04,0x07,0x02,0x00,0x0F,\n0x08,0x0D,0x0A,0x0A,0x0D,0x08,/*\"堰\",3164*/},{\n\n0x12,0x92,0xFA,0x02,0xEF,0x2A,0xEF,0x02,0xFA,0x22,0x92,0x09,0x04,0x01,0x04,0x09,\n0x01,0x05,0x08,0x00,0x05,0x09,/*\"燕\",3165*/},{\n\n0x00,0xFF,0x01,0xDF,0x55,0xDF,0x01,0x11,0xFF,0x13,0x15,0x08,0x07,0x00,0x0F,0x05,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"厭\",3166*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFE,0xAA,0xAA,0xAA,0xFE,0x00,0x00,0x07,0x02,0x07,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"硯\",3167*/},{\n\n0x00,0xFF,0x11,0xF9,0x27,0xF9,0x4F,0x49,0xFB,0x4D,0x49,0x08,0x07,0x00,0x0F,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"雁\",3168*/},{\n\n0xFE,0x02,0xFE,0x04,0x54,0x54,0x55,0x56,0x54,0x54,0x04,0x03,0x01,0x03,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"唁\",3169*/},{\n\n0x00,0xE2,0x22,0xB6,0xAA,0xAB,0x6A,0x36,0xA2,0x22,0x20,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x09,0x05,0x04,0x02,0x00,/*\"彥\",3170*/},{\n\n0x78,0x00,0xFF,0x04,0x00,0xE4,0x93,0x02,0x8A,0xA6,0xE0,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"焰\",3171*/},{\n\n0x06,0x02,0x7E,0x56,0xD6,0x57,0x56,0x56,0x7E,0x02,0x06,0x01,0x09,0x09,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"宴\",3172*/},{\n\n0x55,0x56,0x54,0x00,0xF2,0x16,0x5A,0x53,0xBA,0x96,0x12,0x0F,0x05,0x07,0x08,0x07,\n0x08,0x09,0x09,0x04,0x04,0x02,/*\"諺\",3173*/},{\n\n0xFE,0xAA,0xFE,0xAA,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x04,0x0A,0x08,0x07,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"驗\",3174*/},{\n\n0x82,0x7E,0x92,0xF2,0x80,0xFC,0x84,0xFF,0x84,0xFC,0x80,0x08,0x04,0x02,0x01,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"殃\",3175*/},{\n\n0x80,0xFC,0x84,0x84,0x84,0xFF,0x84,0x84,0x84,0xFC,0x80,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"央\",3176*/},{\n\n0x28,0xEE,0x6A,0x5A,0x6A,0xCF,0x4A,0x5A,0xEA,0x2E,0x28,0x08,0x07,0x05,0x0D,0x05,\n0x0D,0x05,0x0D,0x05,0x05,0x0D,/*\"鴦\",3177*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0xFC,0x84,0xFF,0x84,0xFC,0x80,0x01,0x00,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"秧\",3178*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xDF,0x55,0x55,0x55,0x5F,0x40,0x00,0x00,0x0F,0x00,0x0A,\n0x05,0x0B,0x05,0x0B,0x09,0x07,/*\"楊\",3179*/},{\n\n0x08,0x08,0xFF,0x88,0x40,0xDF,0x55,0x55,0x55,0x5F,0x40,0x01,0x09,0x0F,0x00,0x0A,\n0x05,0x0B,0x05,0x0B,0x09,0x07,/*\"揚\",3180*/},{\n\n0x20,0x10,0xFC,0x03,0x04,0x25,0x26,0xFC,0x26,0x25,0x04,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"佯\",3181*/},{\n\n0x08,0x90,0xFE,0x82,0xFA,0xAA,0xAB,0xAA,0xAA,0xFA,0x82,0x09,0x04,0x03,0x04,0x02,\n0x0B,0x06,0x0A,0x06,0x0A,0x0E,/*\"瘍\",3182*/},{\n\n0x00,0x24,0x25,0x26,0x24,0xFC,0x24,0x26,0x25,0x24,0x00,0x01,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"羊\",3183*/},{\n\n0x22,0x44,0x00,0x24,0x25,0x26,0xFC,0x26,0x25,0x24,0x00,0x04,0x02,0x01,0x01,0x01,\n0x01,0x0F,0x01,0x01,0x01,0x01,/*\"洋\",3184*/},{\n\n0xFF,0x01,0x19,0xE7,0x40,0xDF,0x55,0x55,0x55,0x5F,0x40,0x0F,0x02,0x02,0x01,0x0A,\n0x05,0x0B,0x05,0x0B,0x09,0x07,/*\"陽\",3185*/},{\n\n0x08,0x24,0xAB,0xBA,0xEA,0xBA,0xAA,0x2A,0xFA,0x02,0x02,0x02,0x02,0x02,0x02,0x0F,\n0x02,0x02,0x02,0x03,0x04,0x0E,/*\"氧\",3186*/},{\n\n0x20,0x10,0xFC,0x03,0xFC,0x02,0x81,0xFC,0x04,0x04,0xFC,0x00,0x00,0x0F,0x00,0x03,\n0x01,0x00,0x0F,0x00,0x02,0x03,/*\"仰\",3187*/},{\n\n0x88,0xFE,0x22,0xAA,0xEE,0xAA,0xBB,0xAA,0xEE,0xAA,0x22,0x08,0x07,0x01,0x00,0x0F,\n0x0A,0x03,0x06,0x0B,0x0C,0x09,/*\"癢\",3188*/},{\n\n0x20,0xAA,0xEA,0xAB,0xBA,0xEE,0xAA,0xAB,0xEA,0xAA,0x20,0x01,0x00,0x0F,0x0A,0x02,\n0x03,0x06,0x0A,0x0B,0x0C,0x09,/*\"養\",3189*/},{\n\n0x88,0x68,0xFF,0x48,0x22,0x2A,0xEB,0xBE,0x2A,0x2B,0xAA,0x00,0x00,0x0F,0x08,0x05,\n0x03,0x08,0x0F,0x03,0x05,0x08,/*\"樣\",3190*/},{\n\n0x22,0x44,0x22,0x2A,0xAB,0xEA,0xBE,0x2A,0x2B,0x2A,0xA2,0x04,0x02,0x09,0x05,0x03,\n0x08,0x0F,0x01,0x02,0x05,0x08,/*\"漾\",3191*/},{\n\n0x11,0xF2,0x80,0xBE,0xEB,0xBE,0x88,0x77,0x84,0x7C,0x04,0x08,0x07,0x0C,0x0B,0x0A,\n0x0E,0x0C,0x0A,0x09,0x0A,0x0C,/*\"邀\",3192*/},{\n\n0xFE,0x92,0xFE,0x00,0xBA,0xAA,0xBE,0xEA,0xBE,0xAA,0xBA,0x07,0x08,0x0F,0x00,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"腰\",3193*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0x22,0x22,0xFE,0x21,0x21,0x20,0x08,0x05,0x02,0x05,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"妖\",3194*/},{\n\n0x22,0xFE,0x22,0x00,0xA4,0x6A,0x53,0xD6,0x4A,0x4A,0x06,0x04,0x07,0x02,0x00,0x0D,\n0x09,0x09,0x0F,0x09,0x09,0x0D,/*\"瑤\",3195*/},{\n\n0x88,0x88,0xFF,0x48,0xA4,0x6A,0x53,0xD6,0x4A,0x4A,0x06,0x00,0x08,0x0F,0x00,0x0D,\n0x09,0x09,0x0F,0x09,0x09,0x0D,/*\"搖\",3196*/},{\n\n0x88,0xAA,0xFA,0xAA,0xAA,0x0F,0xAA,0xAA,0xFA,0xAA,0x88,0x08,0x0A,0x0A,0x06,0x02,\n0x02,0x06,0x0A,0x0A,0x0A,0x0C,/*\"堯\",3197*/},{\n\n0x11,0xF2,0xA0,0xE4,0xBC,0xB2,0xEF,0xAA,0xA6,0xA2,0x80,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0B,0x0A,0x0A,0x0B,0x08,/*\"遙\",3198*/},{\n\n0x06,0x5A,0x56,0x5A,0x52,0xF3,0x52,0x5A,0x56,0x5A,0x06,0x09,0x05,0x01,0x05,0x09,\n0x01,0x05,0x09,0x01,0x05,0x09,/*\"窯\",3199*/},{\n\n0x55,0x56,0x54,0x00,0xA4,0x6A,0x53,0xD6,0x4A,0x4A,0x06,0x0F,0x05,0x0F,0x00,0x0D,\n0x09,0x09,0x0F,0x09,0x09,0x0D,/*\"謠\",3200*/},{\n\n0x88,0x78,0x0F,0xF8,0x84,0x48,0xFF,0x00,0xFF,0x48,0x84,0x08,0x05,0x02,0x05,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"姚\",3201*/},{\n\n0xFE,0x02,0xFE,0x44,0x24,0xD4,0x05,0x06,0xD4,0x24,0x44,0x03,0x01,0x03,0x08,0x08,\n0x05,0x02,0x02,0x05,0x08,0x08,/*\"咬\",3202*/},{\n\n0x00,0xCA,0x52,0x42,0x26,0x0A,0x41,0x41,0x51,0xC9,0x00,0x00,0x0F,0x05,0x05,0x05,\n0x04,0x05,0x05,0x05,0x0F,0x00,/*\"舀\",3203*/},{\n\n0xD2,0xAA,0xD2,0x07,0xFA,0xAE,0xFA,0x07,0xD2,0xAA,0xD2,0x0A,0x0A,0x0A,0x06,0x02,\n0x0F,0x02,0x06,0x0A,0x0A,0x0A,/*\"藥\",3204*/},{\n\n0x82,0xBA,0xAA,0xAA,0xFE,0xAA,0xBE,0xAA,0xAA,0xBA,0x82,0x08,0x08,0x0A,0x0B,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x00,/*\"要\",3205*/},{\n\n0x24,0xE8,0x3F,0xE8,0x24,0x4A,0xF5,0xAF,0xEA,0xB5,0xAF,0x08,0x07,0x00,0x0F,0x04,\n0x00,0x0F,0x0A,0x0F,0x0A,0x0A,/*\"耀\",3206*/},{\n\n0x88,0x68,0xFF,0x4A,0xFE,0x52,0xFE,0x02,0xFE,0x32,0xCE,0x00,0x00,0x0F,0x02,0x03,\n0x02,0x0F,0x01,0x0F,0x02,0x01,/*\"椰\",3207*/},{\n\n0xFC,0x04,0xFC,0x00,0x62,0xAA,0xAA,0xAF,0xAA,0xAA,0x62,0x03,0x01,0x03,0x00,0x08,\n0x0B,0x0E,0x0A,0x0E,0x0B,0x08,/*\"噎\",3208*/},{\n\n0x02,0xFE,0x52,0x52,0xFE,0x02,0x00,0xFE,0x02,0x32,0xCE,0x02,0x03,0x02,0x02,0x0F,\n0x01,0x00,0x0F,0x02,0x02,0x01,/*\"耶\",3209*/},{\n\n0x50,0xD2,0x49,0x4A,0xC4,0x44,0x04,0xCA,0x49,0xD2,0x10,0x04,0x07,0x05,0x05,0x0F,\n0x02,0x00,0x0F,0x05,0x06,0x00,/*\"爺\",3210*/},{\n\n0xBE,0xAA,0xFE,0xAA,0xBE,0x00,0x22,0x2A,0xF2,0x2A,0x66,0x04,0x04,0x07,0x02,0x02,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"野\",3211*/},{\n\n0x04,0x08,0x00,0x10,0xD8,0x54,0x53,0x50,0x50,0xD8,0x30,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"冶\",3212*/},{\n\n0x20,0x20,0xFE,0x10,0x10,0xFF,0x08,0x08,0x84,0xFC,0x00,0x00,0x00,0x07,0x08,0x08,\n0x09,0x08,0x08,0x08,0x08,0x0E,/*\"也\",3213*/},{\n\n0x02,0xFA,0xAA,0xAA,0xAA,0xAE,0xAA,0xAA,0xAA,0xFA,0x02,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"頁\",3214*/},{\n\n0x88,0xFF,0x48,0x84,0xE4,0x1C,0xC5,0x3E,0x54,0x94,0x74,0x08,0x0F,0x00,0x00,0x0F,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"掖\",3215*/},{\n\n0x04,0x55,0x56,0x5C,0x57,0xF4,0x57,0x5C,0x56,0x55,0x04,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"業\",3216*/},{\n\n0x12,0x12,0xFA,0x97,0xFA,0xD2,0xD2,0xFF,0x92,0x92,0x12,0x0A,0x0A,0x0A,0x06,0x02,\n0x0F,0x02,0x06,0x0A,0x0A,0x0A,/*\"葉\",3217*/},{\n\n0x00,0x7C,0x54,0x54,0x54,0xFF,0x54,0x54,0xD4,0x7C,0x00,0x08,0x08,0x08,0x04,0x04,\n0x03,0x02,0x05,0x04,0x08,0x0E,/*\"曳\",3218*/},{\n\n0xFE,0x92,0xFE,0x80,0xE4,0x1C,0xC5,0x3E,0x54,0x94,0x74,0x07,0x08,0x0F,0x00,0x0F,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"腋\",3219*/},{\n\n0x84,0x44,0xE4,0x9C,0x45,0xA6,0x1C,0x54,0x94,0x74,0x04,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"夜\",3220*/},{\n\n0x22,0x44,0x80,0xE4,0x1C,0xC5,0x3E,0x54,0x94,0x74,0x04,0x04,0x02,0x00,0x0F,0x01,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"液\",3221*/},{\n\n0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"一\",3222*/},{\n\n0x62,0xAA,0xAA,0xAA,0xAA,0xAF,0xAA,0xAA,0xAA,0xAA,0x62,0x08,0x0B,0x0A,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x0A,0x0B,0x08,/*\"壹\",3223*/},{\n\n0x7F,0x59,0x77,0xDD,0x75,0x51,0x44,0xDB,0x69,0x5B,0x42,0x00,0x0F,0x0D,0x0B,0x0D,\n0x0D,0x0D,0x0B,0x0D,0x0F,0x00,/*\"醫\",3224*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0xF7,0x55,0x55,0x55,0xF7,0x10,0x00,0x08,0x0F,0x00,0x04,\n0x07,0x05,0x05,0x05,0x0F,0x02,/*\"揖\",3225*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x44,0xE4,0x15,0x6E,0x84,0x44,0x24,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x04,0x00,0x01,0x02,0x04,/*\"銥\",3226*/},{\n\n0x20,0x10,0xFC,0x83,0x44,0xE4,0x15,0x6E,0x84,0x44,0x24,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x00,0x01,0x02,0x04,/*\"依\",3227*/},{\n\n0x10,0xFC,0x03,0x10,0x92,0x92,0xFE,0x92,0x92,0xFE,0x10,0x00,0x0F,0x00,0x00,0x08,\n0x04,0x03,0x00,0x00,0x01,0x00,/*\"伊\",3228*/},{\n\n0x04,0x84,0x44,0xF4,0x0C,0x35,0xC6,0x44,0x24,0x14,0x04,0x01,0x00,0x00,0x0F,0x04,\n0x02,0x00,0x01,0x02,0x04,0x04,/*\"衣\",3229*/},{\n\n0xFE,0x02,0xF2,0x1E,0xF2,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x0F,0x08,0x09,0x0F,0x09,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頤\",3230*/},{\n\n0x02,0xEA,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xBA,0x82,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x04,0x0A,0x0B,/*\"夷\",3231*/},{\n\n0x11,0xF2,0x20,0xEE,0xAA,0xAA,0xBF,0xAA,0xAA,0xEE,0x20,0x08,0x07,0x08,0x0B,0x0E,\n0x0A,0x0A,0x0A,0x0E,0x0B,0x08,/*\"遺\",3232*/},{\n\n0x12,0xD2,0xFE,0x91,0x08,0x44,0xAB,0x52,0x6A,0x46,0xC0,0x01,0x00,0x0F,0x00,0x08,\n0x09,0x04,0x05,0x02,0x01,0x00,/*\"移\",3233*/},{\n\n0x20,0x10,0xFC,0x03,0x22,0xAB,0x6A,0x3E,0xAA,0x6B,0xA2,0x00,0x00,0x0F,0x00,0x05,\n0x0F,0x05,0x09,0x07,0x0B,0x0D,/*\"儀\",3234*/},{\n\n0x00,0xFF,0x49,0xFF,0x00,0xEA,0xAA,0xFF,0xAA,0xAA,0xBA,0x08,0x07,0x08,0x0F,0x00,\n0x08,0x04,0x03,0x04,0x0A,0x0B,/*\"胰\",3235*/},{\n\n0x40,0x37,0x2A,0xE9,0x2C,0x00,0x91,0x15,0xF9,0x95,0xB3,0x01,0x09,0x05,0x03,0x05,\n0x09,0x07,0x08,0x0F,0x08,0x08,/*\"疑\",3236*/},{\n\n0x10,0x21,0x02,0x00,0xFE,0x12,0x12,0x11,0xF1,0x11,0x10,0x04,0x02,0x09,0x06,0x01,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"沂\",3237*/},{\n\n0x0C,0x04,0xF4,0x54,0x55,0x56,0x54,0x54,0xF4,0x04,0x0C,0x08,0x08,0x0F,0x09,0x09,\n0x09,0x09,0x09,0x0F,0x08,0x08,/*\"宜\",3238*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xEA,0xAA,0xFF,0xAA,0xAA,0xBA,0x08,0x05,0x02,0x0D,0x00,\n0x08,0x04,0x03,0x04,0x0A,0x0B,/*\"姨\",3239*/},{\n\n0xAC,0x24,0xFE,0x25,0xAD,0x45,0xD5,0x5D,0xF7,0x54,0xCC,0x02,0x02,0x0A,0x07,0x02,\n0x03,0x02,0x0F,0x03,0x02,0x02,/*\"彝\",3240*/},{\n\n0x88,0x68,0xFF,0x48,0x10,0xDA,0x56,0xD3,0x16,0xFA,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x02,0x03,0x08,0x0F,0x00,/*\"椅\",3241*/},{\n\n0x78,0x48,0xFF,0x48,0x22,0xAB,0x6A,0x3E,0xAA,0x6B,0xA2,0x04,0x04,0x03,0x02,0x05,\n0x0F,0x05,0x09,0x07,0x0B,0x0D,/*\"蟻\",3242*/},{\n\n0x10,0xFC,0x03,0x10,0xDA,0x56,0x53,0xD2,0x16,0xFA,0x10,0x00,0x0F,0x00,0x00,0x07,\n0x02,0x02,0x0B,0x08,0x0F,0x00,/*\"倚\",3243*/},{\n\n0x00,0xF2,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x7E,0x00,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"已\",3244*/},{\n\n0x02,0x02,0x82,0x42,0x22,0x12,0x0A,0x06,0x02,0x00,0x00,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x0F,0x00,/*\"乙\",3245*/},{\n\n0x00,0x48,0x2C,0x3A,0x29,0xE8,0x28,0x2A,0x2C,0x18,0x00,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"矣\",3246*/},{\n\n0x00,0xFE,0x00,0x80,0x42,0x0C,0x00,0x80,0x7F,0x00,0x00,0x00,0x03,0x09,0x08,0x04,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"以\",3247*/},{\n\n0x02,0xAA,0x9A,0xEF,0x9A,0xAA,0xD2,0xFF,0x92,0x72,0xC2,0x02,0x0A,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x0A,0x02,/*\"藝\",3248*/},{\n\n0x88,0x88,0xFF,0x48,0xFC,0x02,0x81,0xFC,0x04,0x04,0xFC,0x00,0x08,0x0F,0x00,0x03,\n0x01,0x00,0x0F,0x00,0x02,0x03,/*\"抑\",3249*/},{\n\n0x00,0x9F,0x75,0x55,0xD5,0x55,0x55,0xD5,0x55,0x5F,0xC0,0x01,0x08,0x04,0x02,0x09,\n0x04,0x02,0x09,0x08,0x08,0x07,/*\"易\",3250*/},{\n\n0x00,0xF0,0x97,0x95,0x95,0xF5,0x95,0x95,0x97,0xF0,0x00,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"邑\",3251*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x08,0x24,0x27,0xA4,0x64,0x04,0x07,0x04,0x03,0x02,0x07,\n0x00,0x06,0x09,0x08,0x08,0x0E,/*\"屹\",3252*/},{\n\n0x10,0xFC,0x0B,0xFA,0xAE,0xAA,0xAB,0xAA,0xAE,0xFA,0x08,0x00,0x0F,0x08,0x06,0x00,\n0x06,0x09,0x0A,0x0C,0x02,0x0C,/*\"億\",3253*/},{\n\n0x48,0x24,0xF2,0x09,0x50,0xCF,0x41,0x41,0x4F,0xD0,0x10,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"役\",3254*/},{\n\n0x00,0xFE,0x92,0xFE,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0x08,0x07,0x08,0x0F,0x04,\n0x02,0x0C,0x09,0x0C,0x02,0x0C,/*\"臆\",3255*/},{\n\n0x11,0xF2,0x08,0x3C,0xAB,0x6A,0xBA,0x6A,0xAE,0x38,0x00,0x08,0x07,0x0A,0x09,0x08,\n0x08,0x09,0x0A,0x0A,0x0A,0x0B,/*\"逸\",3256*/},{\n\n0x40,0x37,0xEA,0x2D,0x00,0xAA,0xAA,0xFF,0xAA,0xBE,0x08,0x09,0x05,0x03,0x05,0x09,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"肄\",3257*/},{\n\n0x08,0x90,0xFE,0x42,0xA2,0x9A,0x8B,0x8A,0x9A,0xA2,0x22,0x09,0x04,0x03,0x08,0x08,\n0x0B,0x04,0x04,0x0A,0x09,0x08,/*\"疫\",3258*/},{\n\n0x04,0xC4,0x04,0xFC,0x05,0x06,0x04,0xFC,0x04,0x44,0x84,0x01,0x08,0x04,0x03,0x00,\n0x00,0x08,0x0F,0x00,0x00,0x01,/*\"亦\",3259*/},{\n\n0x12,0xD2,0x4A,0xFE,0x52,0x47,0x4A,0xD2,0x5A,0xE6,0x22,0x00,0x0F,0x01,0x00,0x07,\n0x05,0x07,0x00,0x09,0x0F,0x00,/*\"裔\",3260*/},{\n\n0x08,0x0A,0xFA,0xAE,0xAA,0xAB,0xAA,0xAE,0xFA,0x0A,0x08,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"意\",3261*/},{\n\n0x56,0x5A,0xB3,0x5A,0x96,0x50,0x08,0xE7,0x21,0xEF,0x08,0x05,0x05,0x0A,0x09,0x07,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"毅\",3262*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0x00,0x00,0x0F,0x00,0x0C,\n0x00,0x0C,0x0A,0x0C,0x02,0x0C,/*\"憶\",3263*/},{\n\n0xA2,0xAA,0xAA,0xEB,0xAA,0xBE,0xAA,0xEB,0xAA,0xEA,0xA2,0x02,0x02,0x0A,0x0F,0x02,\n0x02,0x00,0x0B,0x04,0x0A,0x0C,/*\"義\",3264*/},{\n\n0x48,0xA9,0x9A,0x8C,0x88,0x88,0x88,0x8C,0x9A,0xA9,0x48,0x08,0x0F,0x08,0x08,0x0F,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"益\",3265*/},{\n\n0x11,0x22,0x48,0xA9,0x9A,0x88,0x88,0x88,0x9A,0xA9,0x48,0x04,0x02,0x08,0x0F,0x08,\n0x0F,0x08,0x0F,0x08,0x0F,0x08,/*\"溢\",3266*/},{\n\n0x54,0x55,0x56,0x54,0x00,0xCF,0x54,0x54,0x52,0x52,0xD9,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"詣\",3267*/},{\n\n0x55,0x56,0x54,0x00,0x22,0xAB,0x6A,0x3E,0xAA,0x6B,0xA2,0x0F,0x05,0x0F,0x00,0x05,\n0x0F,0x05,0x09,0x07,0x0B,0x0D,/*\"議\",3268*/},{\n\n0x55,0x56,0x54,0x00,0x0C,0xF4,0x55,0x56,0x54,0xF4,0x0C,0x0F,0x05,0x0F,0x00,0x08,\n0x0F,0x09,0x09,0x09,0x0F,0x08,/*\"誼\",3269*/},{\n\n0x55,0x56,0x54,0x00,0x47,0x55,0xD7,0x7D,0xD7,0x55,0x47,0x0F,0x05,0x0F,0x00,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"譯\",3270*/},{\n\n0x00,0x5F,0x55,0xF5,0x55,0x5F,0x55,0xF5,0x55,0x5F,0x00,0x01,0x09,0x05,0x01,0x01,\n0x01,0x01,0x01,0x05,0x09,0x01,/*\"異\",3271*/},{\n\n0x01,0x8B,0xFD,0xA9,0xAF,0xF8,0xA9,0xAB,0xFD,0x81,0x0F,0x02,0x0A,0x06,0x03,0x02,\n0x02,0x02,0x03,0x06,0x0A,0x02,/*\"翼\",3272*/},{\n\n0x00,0x95,0x89,0x81,0xBF,0xC0,0x95,0x89,0x81,0x9F,0x00,0x08,0x08,0x0A,0x0C,0x08,\n0x08,0x08,0x0C,0x0A,0x08,0x08,/*\"翌\",3273*/},{\n\n0xD8,0xB4,0x93,0xC8,0x47,0x55,0xD7,0x7D,0xD7,0x55,0x47,0x0C,0x02,0x04,0x02,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"繹\",3274*/},{\n\n0x02,0xFA,0x0A,0x4F,0x4A,0xEA,0x4A,0x4F,0x0A,0xFA,0x02,0x00,0x0F,0x08,0x0A,0x09,\n0x08,0x09,0x0A,0x08,0x0F,0x00,/*\"茵\",3275*/},{\n\n0xFA,0x0A,0x4A,0xBF,0x12,0xB2,0xAA,0xB7,0xEA,0xB2,0x12,0x0F,0x01,0x02,0x01,0x02,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x0A,/*\"蔭\",3276*/},{\n\n0xFF,0x01,0x11,0x91,0x51,0x3D,0x51,0x91,0x11,0x01,0xFF,0x0F,0x04,0x05,0x04,0x04,\n0x04,0x04,0x04,0x05,0x04,0x0F,/*\"因\",3277*/},{\n\n0x00,0xFE,0x55,0x55,0x7D,0x10,0xCE,0x42,0x42,0xDE,0x10,0x08,0x07,0x01,0x09,0x0F,\n0x08,0x05,0x02,0x02,0x05,0x08,/*\"殷\",3278*/},{\n\n0x10,0xD2,0x56,0x5A,0x52,0x53,0x52,0x5A,0x56,0xD2,0x10,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"音\",3279*/},{\n\n0xFE,0x02,0x32,0xCE,0x08,0x54,0x52,0x59,0x72,0x54,0x08,0x0F,0x02,0x02,0x01,0x01,\n0x0D,0x0B,0x09,0x09,0x0D,0x09,/*\"陰\",3280*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFE,0xA2,0x7A,0xA2,0x22,0xFE,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x04,0x04,0x04,0x05,0x0F,/*\"姻\",3281*/},{\n\n0xFE,0x02,0x02,0xFE,0x20,0x90,0x8C,0xA3,0x8C,0x90,0x20,0x03,0x01,0x01,0x03,0x00,\n0x00,0x00,0x08,0x06,0x01,0x00,/*\"吟\",3282*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x08,0x09,0x07,0x05,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"銀\",3283*/},{\n\n0x22,0x44,0x02,0x2A,0x32,0x26,0xEA,0x11,0x19,0x15,0x01,0x04,0x02,0x01,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x01,/*\"淫\",3284*/},{\n\n0x06,0xEA,0xAA,0xAA,0xAA,0xFB,0xAA,0xAA,0xAA,0xEA,0x06,0x00,0x0B,0x06,0x02,0x02,\n0x03,0x02,0x02,0x06,0x0B,0x00,/*\"寅\",3285*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x04,0x10,0x0F,0xC4,0x14,0x0C,0x00,0x0F,0x04,0x02,0x0C,\n0x00,0x08,0x06,0x01,0x06,0x08,/*\"飲\",3286*/},{\n\n0x10,0x92,0x92,0x92,0xF2,0x9E,0x92,0x92,0x92,0xFE,0x10,0x00,0x08,0x04,0x03,0x00,\n0x00,0x00,0x00,0x00,0x01,0x00,/*\"尹\",3287*/},{\n\n0x00,0xF2,0x92,0x92,0x92,0x9E,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x08,0x08,0x08,\n0x07,0x00,0x00,0x00,0x0F,0x00,/*\"引\",3288*/},{\n\n0xFF,0x31,0xCF,0x10,0x55,0x57,0x55,0x5F,0x55,0xF7,0x15,0x0F,0x02,0x01,0x08,0x05,\n0x01,0x0D,0x0B,0x0D,0x01,0x0C,/*\"隱\",3289*/},{\n\n0xFE,0x12,0x12,0x11,0x91,0x00,0xFE,0x02,0x02,0x02,0xFE,0x03,0x02,0x01,0x01,0x00,\n0x00,0x0F,0x00,0x02,0x02,0x03,/*\"印\",3290*/},{\n\n0x02,0xF2,0x12,0x17,0x12,0xFA,0x12,0x17,0x12,0xF2,0x02,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"英\",3291*/},{\n\n0x88,0x68,0xFF,0x28,0x5F,0x35,0xDF,0x00,0x5F,0x35,0x5F,0x00,0x00,0x0F,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"櫻\",3292*/},{\n\n0x00,0x5F,0x35,0x35,0xDF,0x00,0x5F,0x35,0x35,0x5F,0x00,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"嬰\",3293*/},{\n\n0x00,0xFE,0x22,0xFA,0x96,0xFA,0xAF,0xAA,0xFE,0xAA,0xAA,0x08,0x07,0x00,0x0B,0x02,\n0x0A,0x03,0x0A,0x02,0x0B,0x0E,/*\"鷹\",3294*/},{\n\n0x00,0xFE,0x22,0xFA,0x16,0xFB,0xAE,0xAA,0xFE,0xAA,0xAA,0x08,0x07,0x08,0x06,0x00,\n0x06,0x09,0x0A,0x0C,0x02,0x0C,/*\"應\",3295*/},{\n\n0xDC,0xB3,0xC8,0x00,0x5F,0x35,0xDF,0x00,0x5F,0x35,0x5F,0x0E,0x00,0x06,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"纓\",3296*/},{\n\n0x3A,0x54,0x53,0x54,0x5A,0xD0,0x5A,0x54,0x53,0x54,0x3A,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x0B,0x0D,0x09,0x08,/*\"瑩\",3297*/},{\n\n0x3A,0xD4,0x53,0x54,0x5A,0xF0,0x5A,0x54,0x53,0xD4,0x3A,0x04,0x05,0x05,0x05,0x05,\n0x07,0x05,0x05,0x05,0x05,0x0E,/*\"螢\",3298*/},{\n\n0x1D,0x0A,0xE9,0xAA,0xAD,0xA8,0xAD,0xAA,0xE9,0x0A,0x1D,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"營\",3299*/},{\n\n0x6A,0x24,0xA3,0x24,0x2A,0xA0,0x2A,0x24,0x23,0xA4,0x6A,0x08,0x09,0x04,0x04,0x02,\n0x01,0x02,0x04,0x05,0x08,0x08,/*\"熒\",3300*/},{\n\n0x78,0x48,0xFF,0x48,0xF7,0x55,0xFF,0x01,0xFF,0x55,0xF7,0x04,0x04,0x03,0x02,0x01,\n0x01,0x07,0x08,0x0F,0x09,0x0D,/*\"蠅\",3301*/},{\n\n0x11,0xF2,0x00,0xFE,0x82,0x41,0x00,0xFE,0x02,0x02,0xFE,0x08,0x07,0x08,0x09,0x08,\n0x08,0x08,0x0F,0x08,0x09,0x09,/*\"迎\",3302*/},{\n\n0xE2,0xAE,0xEA,0x0A,0xEA,0xAB,0xEA,0x0A,0xEA,0x2A,0xE2,0x07,0x0A,0x0F,0x00,0x0B,\n0x06,0x0B,0x08,0x07,0x01,0x0F,/*\"贏\",3303*/},{\n\n0x42,0x32,0x0E,0x5A,0x2A,0x5A,0x02,0x5A,0x56,0x30,0x00,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盈\",3304*/},{\n\n0x40,0xDF,0x55,0x75,0x55,0xDF,0x40,0x00,0x88,0x44,0x33,0x08,0x05,0x09,0x0F,0x01,\n0x05,0x08,0x00,0x08,0x04,0x03,/*\"影\",3305*/},{\n\n0x87,0xAA,0xEA,0x99,0x8C,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x04,0x02,0x0F,0x02,0x04,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"穎\",3306*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFA,0xAA,0xFE,0xAA,0xFA,0x02,0x00,0x0F,0x04,0x0F,0x01,\n0x0A,0x04,0x07,0x08,0x08,0x08,/*\"硬\",3307*/},{\n\n0xFE,0x22,0x22,0xFE,0x80,0xFC,0x84,0xFF,0x84,0xFC,0x80,0x07,0x02,0x02,0x07,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"映\",3308*/},{\n\n0xFC,0x04,0xFC,0x00,0xDC,0xB3,0xC8,0x28,0xC7,0x04,0xFC,0x03,0x01,0x03,0x0C,0x00,\n0x0C,0x01,0x04,0x08,0x08,0x07,/*\"喲\",3309*/},{\n\n0x88,0xFF,0x48,0xBA,0x66,0x92,0x22,0xFB,0x56,0xFA,0x52,0x08,0x0F,0x00,0x09,0x05,\n0x03,0x00,0x0F,0x05,0x07,0x05,/*\"擁\",3310*/},{\n\n0x10,0xFC,0x03,0xFE,0x22,0xAA,0xAA,0xFF,0xAA,0xFA,0x22,0x00,0x0F,0x08,0x07,0x00,\n0x0F,0x02,0x07,0x0A,0x0F,0x00,/*\"傭\",3311*/},{\n\n0x00,0xFF,0x49,0xFF,0xB2,0x6E,0x92,0xFB,0x56,0xFA,0x52,0x08,0x07,0x08,0x0F,0x05,\n0x03,0x00,0x0F,0x05,0x07,0x05,/*\"臃\",3312*/},{\n\n0x88,0xFE,0x8A,0xF6,0xAA,0xF6,0xA3,0xFA,0x56,0xFA,0x52,0x08,0x07,0x07,0x0A,0x0B,\n0x0A,0x0B,0x0F,0x05,0x07,0x05,/*\"癰\",3313*/},{\n\n0x00,0xFE,0x22,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x22,0x04,0x03,0x00,0x0F,0x02,\n0x02,0x07,0x02,0x0A,0x0F,0x00,/*\"庸\",3314*/},{\n\n0xB2,0x6E,0x22,0x9A,0x22,0xF3,0x5E,0x52,0xF6,0x5A,0x52,0x09,0x05,0x03,0x01,0x00,\n0x0F,0x05,0x05,0x07,0x05,0x05,/*\"雍\",3315*/},{\n\n0xCF,0x09,0xF9,0x4F,0x00,0xF1,0x55,0xF9,0x55,0x53,0xF0,0x07,0x04,0x03,0x02,0x00,\n0x0F,0x01,0x07,0x01,0x09,0x0F,/*\"踊\",3316*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xF1,0x55,0xF9,0x57,0xF0,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x01,0x07,0x09,0x0F,/*\"蛹\",3317*/},{\n\n0x54,0x55,0x56,0x54,0x20,0xE9,0x09,0xFA,0x62,0x90,0x08,0x0F,0x05,0x05,0x0F,0x02,\n0x01,0x08,0x0F,0x00,0x01,0x02,/*\"詠\",3318*/},{\n\n0x22,0x44,0x20,0x28,0xE8,0x09,0xF9,0x72,0x82,0x40,0x20,0x04,0x02,0x04,0x03,0x00,\n0x08,0x0F,0x00,0x01,0x02,0x04,/*\"泳\",3319*/},{\n\n0x11,0x22,0x00,0xFD,0x55,0x57,0xFD,0x55,0x57,0x55,0xFC,0x02,0x01,0x0A,0x0A,0x06,\n0x03,0x02,0x02,0x0A,0x0A,0x06,/*\"湧\",3320*/},{\n\n0x20,0x20,0xA4,0x64,0x05,0xFD,0x32,0xC2,0x40,0x20,0x10,0x04,0x02,0x01,0x00,0x08,\n0x0F,0x00,0x00,0x01,0x02,0x04,/*\"永\",3321*/},{\n\n0x00,0xFD,0x55,0x55,0x57,0xFD,0x55,0x57,0x55,0xFC,0x00,0x08,0x06,0x00,0x06,0x08,\n0x0A,0x0C,0x08,0x0D,0x03,0x0C,/*\"恿\",3322*/},{\n\n0x00,0xFD,0x55,0x55,0x57,0xFD,0x55,0x57,0x55,0xFC,0x00,0x02,0x0A,0x0A,0x06,0x03,\n0x02,0x02,0x0A,0x0A,0x06,0x00,/*\"勇\",3323*/},{\n\n0x00,0xFE,0x92,0x92,0x92,0xFE,0x92,0x92,0x92,0xFE,0x00,0x08,0x07,0x00,0x00,0x00,\n0x07,0x00,0x08,0x08,0x0F,0x00,/*\"用\",3324*/},{\n\n0xFC,0x00,0xB8,0x66,0x90,0xFF,0x00,0xB8,0x66,0x90,0xFC,0x07,0x04,0x05,0x05,0x05,\n0x07,0x04,0x05,0x05,0x05,0x0F,/*\"幽\",3325*/},{\n\n0x10,0xFC,0x03,0xB1,0x5D,0x95,0x37,0x55,0x95,0x5D,0xB1,0x00,0x0F,0x00,0x0A,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"優\",3326*/},{\n\n0x10,0x08,0xFC,0x03,0x7C,0x10,0x8C,0x57,0x24,0x5C,0x84,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"悠\",3327*/},{\n\n0x61,0xBD,0x25,0xAD,0x35,0x67,0x2D,0xB5,0x25,0xBD,0x61,0x09,0x08,0x0A,0x0B,0x05,\n0x05,0x05,0x0B,0x08,0x08,0x09,/*\"憂\",3328*/},{\n\n0x08,0x08,0x08,0xE8,0x1F,0x08,0xF8,0x09,0x0A,0x08,0x08,0x08,0x04,0x03,0x00,0x00,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"尤\",3329*/},{\n\n0x00,0xFC,0x44,0x44,0x44,0xFF,0x44,0x44,0x44,0xFC,0x00,0x00,0x0F,0x04,0x04,0x04,\n0x07,0x04,0x04,0x04,0x0F,0x00,/*\"由\",3330*/},{\n\n0x48,0xFA,0x4A,0xFE,0x49,0xF9,0x48,0x00,0xFE,0x32,0xCE,0x02,0x0B,0x0A,0x0F,0x0A,\n0x0B,0x02,0x00,0x0F,0x02,0x01,/*\"郵\",3331*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xF8,0x48,0xFF,0x48,0xF8,0x08,0x09,0x07,0x05,0x04,\n0x00,0x0F,0x04,0x07,0x04,0x0F,/*\"鈾\",3332*/},{\n\n0x8A,0x44,0xFB,0x00,0xF4,0x55,0x3E,0x14,0x7E,0x55,0xF4,0x08,0x08,0x07,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"猶\",3333*/},{\n\n0x10,0x22,0x04,0x00,0xFC,0x44,0x44,0xFF,0x44,0x44,0xFC,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"油\",3334*/},{\n\n0x21,0xE2,0x04,0xFD,0x16,0xF4,0x88,0x97,0xD4,0xB4,0x84,0x08,0x07,0x0A,0x09,0x0A,\n0x0B,0x08,0x0A,0x0B,0x08,0x08,/*\"遊\",3335*/},{\n\n0x02,0xFA,0x8A,0x4A,0x3E,0x0A,0x3E,0x4A,0x4A,0xFA,0x02,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"酉\",3336*/},{\n\n0x44,0x24,0xF4,0x5C,0x57,0x54,0x54,0x54,0x54,0xF4,0x04,0x00,0x00,0x0F,0x01,0x01,\n0x01,0x01,0x01,0x09,0x0F,0x00,/*\"有\",3337*/},{\n\n0x04,0x04,0xC4,0x3C,0xE7,0x24,0x24,0x24,0xE4,0x04,0x04,0x04,0x03,0x08,0x08,0x04,\n0x05,0x02,0x05,0x04,0x08,0x08,/*\"友\",3338*/},{\n\n0x04,0x04,0x84,0xE4,0x5C,0x47,0x44,0x44,0x44,0xC4,0x04,0x02,0x01,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"右\",3339*/},{\n\n0x20,0x10,0xFC,0x03,0x84,0xC4,0x74,0x4F,0x44,0x44,0xC4,0x00,0x00,0x0F,0x01,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"佑\",3340*/},{\n\n0x4A,0x52,0xFE,0x51,0x08,0xF8,0x48,0xFF,0x48,0x48,0xF8,0x02,0x01,0x0F,0x01,0x02,\n0x0F,0x04,0x07,0x04,0x04,0x0F,/*\"釉\",3341*/},{\n\n0x54,0x55,0x56,0x54,0x28,0x5A,0xCA,0x7E,0x49,0xD9,0x28,0x0F,0x05,0x05,0x07,0x08,\n0x06,0x01,0x00,0x09,0x09,0x07,/*\"誘\",3342*/},{\n\n0x00,0x02,0x1E,0x62,0x82,0x02,0x82,0x42,0x32,0x0E,0x00,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x04,0x08,0x08,/*\"又\",3343*/},{\n\n0x30,0xAC,0x63,0x30,0x0C,0x00,0x08,0xFF,0x08,0x08,0xF8,0x03,0x02,0x02,0x03,0x06,\n0x08,0x06,0x01,0x08,0x08,0x07,/*\"幼\",3344*/},{\n\n0x11,0xF2,0x00,0x20,0x22,0x22,0x22,0xFE,0x22,0x22,0x22,0x08,0x07,0x08,0x08,0x08,\n0x0A,0x0A,0x0B,0x08,0x08,0x08,/*\"迂\",3345*/},{\n\n0x22,0x44,0x08,0xF9,0x4A,0xC8,0x10,0x0C,0x23,0xCC,0x10,0x04,0x02,0x08,0x07,0x08,\n0x0F,0x00,0x01,0x02,0x0C,0x00,/*\"淤\",3346*/},{\n\n0x04,0xFC,0x25,0x26,0xE4,0x10,0x4C,0x43,0x8C,0x10,0x20,0x08,0x07,0x08,0x08,0x07,\n0x00,0x02,0x02,0x04,0x08,0x00,/*\"於\",3347*/},{\n\n0x08,0x09,0x09,0x49,0x49,0x7F,0x09,0x09,0x09,0x09,0x08,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盂\",3348*/},{\n\n0x88,0x68,0xFF,0x48,0xE8,0xA4,0xEA,0x09,0xCA,0x04,0xE8,0x00,0x00,0x0F,0x00,0x0F,\n0x02,0x0F,0x00,0x03,0x08,0x0F,/*\"榆\",3349*/},{\n\n0x00,0xFC,0x04,0x14,0xD4,0xBF,0xB5,0xAD,0xE5,0x35,0x0C,0x08,0x07,0x00,0x0A,0x0A,\n0x06,0x03,0x06,0x0A,0x0A,0x08,/*\"虞\",3350*/},{\n\n0xC0,0x5F,0x55,0x55,0x55,0xFF,0x55,0xD5,0x55,0x5F,0xC0,0x09,0x04,0x00,0x05,0x0B,\n0x0D,0x09,0x0D,0x00,0x05,0x09,/*\"愚\",3351*/},{\n\n0x00,0xFE,0x49,0xFA,0xAA,0xFF,0xAA,0xFA,0x49,0xFF,0x00,0x02,0x0B,0x06,0x02,0x02,\n0x03,0x02,0x02,0x06,0x0B,0x02,/*\"輿\",3352*/},{\n\n0x04,0xFA,0xAD,0xFA,0x4C,0x54,0x52,0xF1,0x52,0x54,0x48,0x00,0x0F,0x04,0x02,0x04,\n0x03,0x08,0x0F,0x00,0x01,0x06,/*\"餘\",3353*/},{\n\n0x08,0xE8,0xA4,0xAC,0xAA,0xE9,0x0A,0xCC,0x04,0xE8,0x08,0x00,0x0F,0x02,0x02,0x0A,\n0x0F,0x00,0x03,0x08,0x0F,0x00,/*\"俞\",3354*/},{\n\n0x21,0xE2,0x08,0xE8,0xA4,0xEA,0x09,0xCA,0x04,0xE8,0x08,0x08,0x07,0x08,0x0F,0x0A,\n0x0F,0x08,0x09,0x0C,0x0F,0x08,/*\"逾\",3355*/},{\n\n0x08,0xF4,0x53,0x52,0x52,0xF2,0x5A,0x56,0x50,0xF0,0x00,0x08,0x05,0x01,0x05,0x09,\n0x01,0x05,0x09,0x01,0x05,0x08,/*\"魚\",3356*/},{\n\n0x78,0x00,0xFF,0x04,0xE8,0xA4,0xEA,0x09,0xCA,0x04,0xE8,0x00,0x00,0x0F,0x00,0x0F,\n0x02,0x0F,0x00,0x03,0x08,0x0F,/*\"愉\",3357*/},{\n\n0x10,0x21,0x02,0xE8,0xA4,0xAA,0xE9,0x0A,0xC4,0x08,0xE8,0x04,0x02,0x01,0x0F,0x02,\n0x0A,0x0F,0x00,0x03,0x08,0x0F,/*\"渝\",3358*/},{\n\n0x22,0x44,0x08,0xF4,0x53,0x52,0xF2,0x5A,0x56,0xF0,0x00,0x04,0x02,0x08,0x05,0x01,\n0x0D,0x01,0x0D,0x01,0x05,0x08,/*\"漁\",3359*/},{\n\n0xFF,0x31,0xCF,0x00,0x80,0xBF,0xA5,0xFF,0xA5,0xBF,0x80,0x0F,0x02,0x01,0x00,0x0F,\n0x00,0x02,0x03,0x06,0x08,0x0F,/*\"隅\",3360*/},{\n\n0x20,0x21,0x21,0x25,0x25,0xE9,0x29,0x35,0x23,0xA1,0x60,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x01,0x00,0x00,/*\"予\",3361*/},{\n\n0xF8,0x0F,0xF8,0x00,0x3C,0x20,0xEF,0x29,0x29,0xEF,0x00,0x0D,0x02,0x05,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"娛\",3362*/},{\n\n0xF9,0x09,0x29,0x49,0x09,0xFF,0x09,0x29,0x49,0x09,0xF9,0x0F,0x00,0x01,0x02,0x00,\n0x07,0x00,0x01,0x0A,0x08,0x0F,/*\"雨\",3363*/},{\n\n0x00,0xFE,0x49,0x00,0xDF,0x12,0xF2,0x00,0x49,0xFF,0x00,0x01,0x09,0x05,0x01,0x01,\n0x01,0x01,0x01,0x05,0x09,0x01,/*\"與\",3364*/},{\n\n0xF8,0x00,0xFF,0x00,0xFE,0x49,0x80,0x1F,0xF2,0x49,0xFF,0x03,0x02,0x01,0x01,0x09,\n0x05,0x01,0x01,0x01,0x05,0x09,/*\"嶼\",3365*/},{\n\n0x82,0xBA,0xAA,0xAA,0xAA,0xFE,0xA9,0xA9,0xA9,0xB9,0x81,0x0F,0x00,0x02,0x02,0x02,\n0x03,0x02,0x02,0x06,0x08,0x0F,/*\"禹\",3366*/},{\n\n0x1C,0x04,0x24,0x24,0x25,0xE6,0x24,0x24,0x24,0x04,0x1C,0x01,0x01,0x01,0x09,0x09,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"宇\",3367*/},{\n\n0x54,0x55,0x56,0x54,0x21,0xA5,0xBD,0xA7,0xA5,0xBD,0x21,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"語\",3368*/},{\n\n0x0A,0x12,0xA2,0x02,0xFE,0x00,0x0A,0x12,0xA2,0x02,0xFE,0x02,0x01,0x08,0x08,0x0F,\n0x00,0x02,0x01,0x08,0x08,0x0F,/*\"羽\",3369*/},{\n\n0x00,0x42,0x42,0x42,0x42,0xFE,0x42,0x42,0x42,0x42,0x00,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x09,0x0A,0x08,0x08,/*\"玉\",3370*/},{\n\n0x10,0xFF,0x10,0x00,0xF4,0x94,0xF4,0x04,0xFF,0x84,0x65,0x04,0x07,0x02,0x00,0x04,\n0x04,0x0A,0x04,0x03,0x05,0x0E,/*\"域\",3371*/},{\n\n0x82,0x92,0x92,0x97,0x92,0xF2,0x92,0x97,0x92,0x92,0x82,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"芋\",3372*/},{\n\n0x6A,0xBF,0x6A,0xB4,0x6B,0xBE,0x2A,0xB0,0x6A,0x3F,0x6A,0x00,0x03,0x0F,0x0A,0x0F,\n0x0B,0x00,0x0A,0x0A,0x05,0x04,/*\"鬱\",3373*/},{\n\n0xA4,0xF3,0xAA,0xE6,0xAA,0xF0,0xA4,0x03,0xEA,0xBE,0xEA,0x0F,0x02,0x07,0x02,0x07,\n0x0A,0x0F,0x00,0x0B,0x06,0x0B,/*\"籲\",3374*/},{\n\n0x21,0xE2,0x00,0xC0,0x5F,0x55,0xFF,0x55,0xD5,0x5F,0xC0,0x08,0x07,0x08,0x0B,0x08,\n0x09,0x09,0x09,0x09,0x0A,0x0B,/*\"遇\",3375*/},{\n\n0xFE,0x02,0xFE,0x00,0xE8,0xA4,0xEA,0x09,0xCA,0x04,0xE8,0x03,0x01,0x03,0x00,0x0F,\n0x02,0x0F,0x00,0x03,0x08,0x0F,/*\"喻\",3376*/},{\n\n0xF8,0x00,0xFF,0x00,0xFC,0x22,0x91,0x88,0x91,0xA2,0x24,0x07,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"峪\",3377*/},{\n\n0x24,0xF2,0x09,0xA4,0x27,0xFC,0xA4,0x20,0xFE,0x02,0xFE,0x00,0x0F,0x04,0x07,0x04,\n0x03,0x02,0x00,0x0F,0x02,0x03,/*\"御\",3378*/},{\n\n0x04,0xF4,0x52,0x56,0x55,0xF5,0x05,0xE6,0x02,0xF4,0x04,0x08,0x03,0x05,0x09,0x0B,\n0x0B,0x0C,0x08,0x0E,0x03,0x08,/*\"愈\",3379*/},{\n\n0x44,0xA2,0x91,0x8C,0x91,0xA2,0x54,0x0F,0xC4,0x14,0x0C,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x08,0x06,0x01,0x06,0x08,/*\"欲\",3380*/},{\n\n0x8A,0x44,0xFB,0x04,0x55,0x56,0x54,0x08,0xFF,0x08,0x0A,0x08,0x08,0x07,0x00,0x0F,\n0x05,0x0F,0x06,0x01,0x06,0x08,/*\"獄\",3381*/},{\n\n0x02,0xEA,0xAE,0xAA,0xAA,0xAB,0xAA,0xAA,0xAE,0xFA,0x02,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"育\",3382*/},{\n\n0x20,0xBE,0xE9,0xA0,0xB7,0xE5,0xBD,0xA0,0xE9,0xBF,0x20,0x01,0x02,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x02,0x01,/*\"譽\",3383*/},{\n\n0x11,0x22,0x04,0xA2,0x91,0x88,0x84,0x88,0x91,0xA2,0x24,0x04,0x02,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"浴\",3384*/},{\n\n0x06,0xFA,0xAA,0xAA,0xAA,0xFB,0xAA,0xAA,0xAA,0xFA,0x06,0x0E,0x02,0x02,0x0A,0x0A,\n0x0F,0x0A,0x0E,0x02,0x0A,0x0E,/*\"寓\",3385*/},{\n\n0x45,0xF6,0xAC,0x00,0x44,0xA2,0x91,0x8C,0x91,0xA2,0x44,0x00,0x0F,0x00,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"裕\",3386*/},{\n\n0x22,0x2A,0xF2,0x2A,0x66,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x08,0x08,0x0F,0x00,0x00,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"預\",3387*/},{\n\n0x4A,0x52,0xEA,0x46,0xC8,0xBC,0x6B,0xFA,0xAE,0x2A,0xB8,0x00,0x08,0x0F,0x00,0x0A,\n0x0A,0x05,0x0A,0x0F,0x03,0x04,/*\"豫\",3388*/},{\n\n0x00,0xFE,0xAA,0xAA,0xFE,0xAA,0x82,0x00,0xFE,0x02,0xFE,0x04,0x02,0x04,0x02,0x0C,\n0x0A,0x07,0x08,0x04,0x03,0x0C,/*\"馭\",3389*/},{\n\n0x44,0xEA,0xB3,0xAA,0xB6,0xE0,0xAF,0xB1,0xF5,0x97,0x98,0x08,0x03,0x0A,0x02,0x0A,\n0x02,0x0A,0x02,0x0A,0x0A,0x06,/*\"鴛\",3390*/},{\n\n0x10,0x21,0x02,0x00,0xFE,0xA8,0xAF,0x20,0xAF,0xA8,0xFE,0x04,0x02,0x01,0x08,0x07,\n0x00,0x07,0x00,0x07,0x00,0x0F,/*\"淵\",3391*/},{\n\n0x46,0x22,0xF2,0xAE,0xAA,0xEA,0xAA,0xBA,0xA2,0xE2,0x06,0x08,0x08,0x04,0x02,0x01,\n0x00,0x07,0x08,0x0A,0x08,0x0E,/*\"冤\",3392*/},{\n\n0x20,0x22,0x22,0xE2,0x22,0x22,0x22,0xE2,0x22,0x22,0x20,0x08,0x04,0x02,0x01,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"元\",3393*/},{\n\n0x10,0xFF,0x10,0x02,0xFA,0x4A,0x4A,0x4A,0x4A,0xFA,0x02,0x04,0x07,0x02,0x08,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"垣\",3394*/},{\n\n0x08,0xEA,0xAA,0xAA,0xAA,0xAF,0xAA,0xAA,0xAA,0xEA,0x08,0x04,0x04,0x02,0x0F,0x08,\n0x04,0x01,0x02,0x04,0x0A,0x09,/*\"袁\",3395*/},{\n\n0x00,0xFE,0x02,0xFA,0xAA,0xAE,0xAA,0xAA,0xAA,0xFA,0x02,0x08,0x07,0x08,0x04,0x02,\n0x08,0x0F,0x00,0x02,0x04,0x08,/*\"原\",3396*/},{\n\n0x88,0xFF,0x48,0x00,0x56,0x5A,0xD6,0x7A,0x52,0x59,0x55,0x08,0x0F,0x00,0x04,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"援\",3397*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xE8,0xAA,0xAF,0xAA,0xE8,0x02,0x02,0x0F,0x02,0x02,\n0x04,0x02,0x0F,0x08,0x07,0x0A,/*\"轅\",3398*/},{\n\n0xFF,0x11,0x75,0x55,0xD5,0xDF,0x55,0xD5,0x75,0x91,0xFF,0x0F,0x04,0x06,0x05,0x04,\n0x07,0x04,0x04,0x05,0x06,0x0F,/*\"園\",3399*/},{\n\n0x00,0xF0,0x57,0x55,0x55,0x55,0x55,0x55,0x57,0xF0,0x00,0x00,0x07,0x0D,0x05,0x05,\n0x05,0x05,0x05,0x0D,0x07,0x00,/*\"員\",3400*/},{\n\n0xFF,0x01,0xF1,0x5D,0x55,0x55,0x55,0x5D,0xF1,0x01,0xFF,0x0F,0x08,0x0D,0x0B,0x09,\n0x09,0x09,0x0B,0x0D,0x08,0x0F,/*\"圓\",3401*/},{\n\n0x8A,0x44,0xFB,0x08,0xEA,0xAA,0xAF,0xAA,0xAA,0xEA,0x08,0x08,0x08,0x07,0x04,0x02,\n0x0F,0x08,0x03,0x04,0x0A,0x09,/*\"猿\",3402*/},{\n\n0x11,0x22,0x00,0xFF,0x01,0xF9,0xAD,0xAB,0xA9,0xF9,0x01,0x04,0x02,0x08,0x07,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"源\",3403*/},{\n\n0xDC,0xB3,0xC8,0x00,0xAC,0x6B,0xAA,0x2A,0x3A,0xA6,0x20,0x0E,0x00,0x06,0x08,0x0A,\n0x05,0x0A,0x0F,0x01,0x06,0x08,/*\"緣\",3404*/},{\n\n0x11,0xF2,0x08,0xEA,0xAA,0xAA,0xAF,0xAA,0xAA,0xEA,0x08,0x08,0x07,0x08,0x0C,0x0A,\n0x09,0x0F,0x08,0x09,0x0A,0x0D,/*\"遠\",3405*/},{\n\n0x82,0x62,0x9A,0x17,0xF2,0x02,0xF2,0x17,0x12,0xF2,0x02,0x00,0x08,0x04,0x03,0x00,\n0x00,0x07,0x08,0x09,0x09,0x0C,/*\"苑\",3406*/},{\n\n0x00,0xFE,0x02,0xFA,0xAE,0xFA,0x00,0xFA,0xAE,0xAA,0xFA,0x08,0x07,0x04,0x0A,0x0F,\n0x02,0x04,0x0B,0x06,0x06,0x0B,/*\"願\",3407*/},{\n\n0x90,0x88,0x57,0x24,0x1C,0x00,0x7E,0x82,0x92,0x9E,0xC0,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"怨\",3408*/},{\n\n0xFE,0x12,0xEE,0x00,0x8C,0xA4,0xA5,0xA6,0xA4,0xA4,0x8C,0x0F,0x01,0x00,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"院\",3409*/},{\n\n0x00,0xFE,0x22,0x22,0x22,0x22,0x22,0x22,0x02,0x02,0xFE,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"曰\",3410*/},{\n\n0x98,0xD4,0xB3,0x90,0xD8,0x08,0x27,0xC4,0x04,0x04,0xFC,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"約\",3411*/},{\n\n0xA4,0x24,0xFF,0x24,0x00,0xFC,0x44,0x24,0xFF,0x44,0xB5,0x0F,0x04,0x0F,0x09,0x08,\n0x08,0x0A,0x09,0x08,0x09,0x0B,/*\"越\",3412*/},{\n\n0x9E,0x12,0xF2,0x9E,0x2B,0xF5,0xAF,0xA0,0xEB,0xB5,0xAF,0x0F,0x08,0x07,0x04,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"躍\",3413*/},{\n\n0x4A,0xF9,0x4A,0x04,0xBC,0xAA,0xBA,0xA9,0xBA,0xAA,0xBC,0x0A,0x0F,0x05,0x00,0x0F,\n0x02,0x07,0x02,0x07,0x0A,0x0F,/*\"鑰\",3414*/},{\n\n0x28,0x93,0xEA,0x02,0xAA,0xAF,0xAA,0x42,0x42,0xFB,0x50,0x09,0x08,0x07,0x00,0x0E,\n0x0A,0x0E,0x00,0x0C,0x03,0x0C,/*\"嶽\",3415*/},{\n\n0x00,0xFE,0x2A,0xBA,0x6B,0xFA,0x66,0xB6,0x22,0xFE,0x00,0x01,0x01,0x07,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0D,0x01,/*\"粵\",3416*/},{\n\n0x00,0x00,0xFE,0x92,0x92,0x92,0x92,0x92,0x92,0xFE,0x00,0x08,0x06,0x01,0x00,0x00,\n0x00,0x00,0x08,0x08,0x0F,0x00,/*\"月\",3417*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0xFA,0x89,0x88,0x89,0xFA,0x04,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"悅\",3418*/},{\n\n0xFF,0x15,0x55,0xDF,0xA0,0x80,0xA0,0xDF,0x55,0x15,0xFF,0x0F,0x00,0x08,0x0B,0x06,\n0x02,0x06,0x0B,0x0C,0x00,0x0F,/*\"閱\",3419*/},{\n\n0x44,0x54,0xFF,0x54,0x44,0x20,0xA2,0x62,0x22,0x22,0x20,0x02,0x01,0x0F,0x01,0x02,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"耘\",3420*/},{\n\n0x0C,0x55,0x55,0x55,0x45,0x5F,0x45,0x55,0x55,0x55,0x0C,0x01,0x09,0x0D,0x0B,0x09,\n0x09,0x09,0x09,0x0D,0x09,0x01,/*\"雲\",3421*/},{\n\n0xF0,0x57,0x55,0x55,0x57,0xF0,0x00,0xFE,0x02,0x32,0xCE,0x07,0x0D,0x05,0x05,0x0D,\n0x07,0x00,0x0F,0x02,0x02,0x01,/*\"鄖\",3422*/},{\n\n0x08,0x04,0x13,0x12,0x12,0x12,0x12,0x12,0x02,0x02,0xFE,0x00,0x01,0x01,0x01,0x01,\n0x01,0x01,0x09,0x09,0x08,0x07,/*\"勻\",3423*/},{\n\n0xFF,0x31,0xCF,0x00,0xF0,0x57,0x55,0x55,0x55,0x57,0xF0,0x0F,0x02,0x01,0x00,0x07,\n0x0D,0x05,0x05,0x05,0x0D,0x07,/*\"隕\",3424*/},{\n\n0x10,0x18,0x14,0xF2,0x11,0x10,0x10,0xF0,0x14,0x18,0x30,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"允\",3425*/},{\n\n0x11,0xF2,0x03,0xF5,0x55,0x55,0xFF,0x55,0x55,0xF5,0x03,0x08,0x07,0x09,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x09,/*\"運\",3426*/},{\n\n0xB2,0x6A,0xA2,0x17,0x02,0xFA,0xAA,0x9F,0xAA,0xFA,0x02,0x0D,0x01,0x0D,0x08,0x0E,\n0x0A,0x0E,0x0A,0x0E,0x0A,0x0E,/*\"蘊\",3427*/},{\n\n0xFD,0xA5,0x9F,0xA5,0xFD,0x00,0xBF,0xA9,0xA7,0xA9,0xBF,0x0F,0x04,0x04,0x04,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"醞\",3428*/},{\n\n0x30,0x50,0xDF,0x55,0x55,0xF5,0x55,0x55,0xDF,0x50,0x30,0x04,0x04,0x07,0x05,0x05,\n0x0F,0x05,0x05,0x07,0x04,0x04,/*\"暈\",3429*/},{\n\n0xAA,0xB2,0xB3,0xAA,0x00,0xF0,0x57,0x55,0x55,0x57,0xF0,0x0F,0x0A,0x0A,0x0F,0x00,\n0x07,0x0D,0x05,0x05,0x0D,0x07,/*\"韻\",3430*/},{\n\n0x41,0x31,0x0F,0x11,0x11,0xD1,0x31,0x07,0x44,0x7C,0x00,0x01,0x01,0x01,0x01,0x09,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"孕\",3431*/},{\n\n0x00,0xFF,0x01,0xF9,0x09,0x09,0xFF,0x09,0x09,0xF9,0x01,0x00,0x0F,0x08,0x09,0x08,\n0x08,0x0F,0x08,0x09,0x09,0x08,/*\"匝\",3432*/},{\n\n0xF2,0x2E,0xE2,0x00,0xFE,0x02,0xF2,0x12,0xFE,0x12,0xF2,0x07,0x02,0x07,0x00,0x0F,\n0x08,0x09,0x08,0x0F,0x09,0x09,/*\"砸\",3433*/},{\n\n0xA2,0x9A,0xE3,0x9A,0xA2,0x10,0xFC,0x27,0xFC,0x25,0x24,0x04,0x0A,0x0F,0x02,0x04,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"雜\",3434*/},{\n\n0x48,0x4A,0x4A,0xEF,0x4A,0x4A,0x08,0xFF,0x08,0xE9,0x0A,0x04,0x02,0x01,0x0F,0x01,\n0x02,0x08,0x04,0x03,0x04,0x0E,/*\"栽\",3435*/},{\n\n0x10,0x92,0x92,0x9F,0x92,0x92,0x10,0xFF,0x10,0x92,0x54,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x04,0x03,0x05,0x08,0x0E,/*\"哉\",3436*/},{\n\n0x04,0x0A,0x91,0x00,0x04,0xCA,0x11,0x00,0x04,0x8A,0x11,0x08,0x09,0x04,0x04,0x02,\n0x01,0x02,0x04,0x05,0x08,0x08,/*\"災\",3437*/},{\n\n0x86,0x92,0xB2,0xD2,0x96,0x9B,0x92,0xD2,0xB2,0x92,0x86,0x00,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x00,/*\"宰\",3438*/},{\n\n0x28,0xEA,0xAA,0xFF,0xAA,0xEA,0x28,0xFF,0x08,0xE9,0x0A,0x02,0x03,0x02,0x0F,0x02,\n0x03,0x0A,0x04,0x03,0x04,0x0E,/*\"載\",3439*/},{\n\n0x01,0xFD,0x25,0x25,0x25,0xFF,0x25,0x25,0x25,0xFD,0x01,0x01,0x0F,0x01,0x01,0x01,\n0x01,0x01,0x09,0x09,0x0F,0x01,/*\"再\",3440*/},{\n\n0x84,0x44,0xE4,0x1C,0x07,0x84,0x84,0xF4,0x84,0x84,0x04,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"在\",3441*/},{\n\n0xFC,0x04,0x04,0xFC,0x00,0xFC,0x26,0x25,0x24,0x24,0xFC,0x03,0x01,0x01,0x03,0x00,\n0x0F,0x09,0x09,0x09,0x09,0x0F,/*\"咱\",3442*/},{\n\n0x84,0xFF,0x44,0xEB,0x5A,0xFF,0x6A,0x5A,0x7F,0xEA,0x28,0x08,0x0F,0x00,0x0B,0x06,\n0x02,0x03,0x02,0x06,0x0B,0x00,/*\"攢\",3443*/},{\n\n0x22,0xBE,0xAA,0xFF,0xAA,0xBE,0xC2,0xBE,0x8A,0xF9,0x08,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"暫\",3444*/},{\n\n0x2C,0xDA,0x4F,0xFA,0x6A,0x44,0xEB,0x5A,0x4F,0xFA,0x2A,0x00,0x0B,0x06,0x02,0x03,\n0x02,0x02,0x03,0x06,0x0B,0x00,/*\"贊\",3445*/},{\n\n0xFE,0x2A,0xFE,0x90,0xFC,0x54,0x74,0xD4,0xFF,0x84,0x65,0x09,0x05,0x09,0x08,0x07,\n0x05,0x0F,0x05,0x03,0x04,0x0E,/*\"贓\",3446*/},{\n\n0x18,0xEF,0xA9,0xEF,0x18,0xEA,0xBF,0x6A,0x7A,0xAF,0xDA,0x00,0x0F,0x02,0x0F,0x00,\n0x0A,0x07,0x02,0x02,0x0F,0x02,/*\"髒\",3447*/},{\n\n0x4A,0x6A,0xBA,0xAF,0x6A,0x0A,0x7A,0xAF,0xAA,0x9A,0xCA,0x01,0x03,0x0A,0x07,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x00,/*\"葬\",3448*/},{\n\n0x11,0xF2,0x00,0xFA,0xAA,0xFF,0xAA,0xFF,0xAA,0xFA,0x02,0x08,0x07,0x08,0x08,0x0F,\n0x0A,0x0A,0x0A,0x0F,0x08,0x08,/*\"遭\",3449*/},{\n\n0x24,0xA8,0xFF,0x24,0xFA,0xAA,0xFF,0xAA,0xFF,0xAA,0xFA,0x01,0x00,0x0F,0x01,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"糟\",3450*/},{\n\n0x65,0x54,0x5F,0xF4,0xDF,0x75,0x84,0xDB,0x29,0x5B,0x04,0x09,0x09,0x0B,0x0E,0x0A,\n0x0F,0x0A,0x0E,0x0B,0x09,0x09,/*\"鑿\",3451*/},{\n\n0x4A,0x92,0x02,0xE7,0xBA,0xEA,0x2A,0xEF,0xBA,0xE2,0x02,0x08,0x04,0x00,0x0A,0x06,\n0x02,0x0F,0x02,0x06,0x0A,0x02,/*\"藻\",3452*/},{\n\n0x42,0x5A,0x6A,0x5A,0x4A,0xFF,0x4A,0x5A,0x6A,0x5A,0x42,0x08,0x0B,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x0B,0x08,/*\"棗\",3453*/},{\n\n0x00,0x3F,0x25,0x25,0x25,0xE5,0x25,0x25,0x25,0x3F,0x00,0x01,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"早\",3454*/},{\n\n0x10,0x21,0x72,0x50,0x57,0x75,0x85,0x75,0x57,0x50,0x70,0x04,0x02,0x09,0x05,0x03,\n0x01,0x0F,0x01,0x03,0x05,0x09,/*\"澡\",3455*/},{\n\n0x20,0x21,0xD3,0x55,0x49,0xEB,0x49,0x55,0xD3,0x21,0x20,0x04,0x04,0x05,0x05,0x05,\n0x07,0x05,0x05,0x05,0x06,0x0C,/*\"蚤\",3456*/},{\n\n0xCF,0x09,0xF9,0x4F,0x70,0x57,0x75,0x85,0x75,0x57,0x70,0x07,0x04,0x03,0x02,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"躁\",3457*/},{\n\n0xFE,0x02,0xFE,0x00,0x70,0x57,0x75,0x85,0x75,0x57,0x70,0x03,0x01,0x03,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"噪\",3458*/},{\n\n0x11,0xF2,0x28,0xA6,0xA4,0xA4,0xBF,0xA4,0xA4,0xA4,0x20,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"造\",3459*/},{\n\n0x00,0x7C,0x54,0x54,0x56,0xD5,0x54,0x54,0x54,0x7C,0x00,0x01,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"皁\",3460*/},{\n\n0x06,0x2A,0xE6,0xAA,0xEA,0x3F,0xEA,0xAA,0xE6,0x2A,0x06,0x00,0x00,0x0E,0x0A,0x0F,\n0x08,0x0F,0x0A,0x0E,0x08,0x0C,/*\"竈\",3461*/},{\n\n0x78,0x00,0xFF,0x04,0x70,0x57,0x75,0x85,0x75,0x57,0x70,0x08,0x06,0x01,0x06,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"燥\",3462*/},{\n\n0x22,0xEA,0xAA,0xAA,0xAA,0xBF,0xAA,0xAA,0xAA,0xEA,0x22,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"責\",3463*/},{\n\n0x08,0x08,0xFF,0x88,0x47,0x55,0xD7,0x7D,0xD7,0x55,0x47,0x01,0x09,0x0F,0x00,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"擇\",3464*/},{\n\n0xFE,0x52,0x52,0x52,0x52,0xFE,0x00,0xFC,0x00,0x00,0xFF,0x0B,0x06,0x02,0x02,0x06,\n0x0B,0x00,0x01,0x08,0x08,0x0F,/*\"則\",3465*/},{\n\n0x11,0x22,0x40,0x57,0xD5,0x57,0x7D,0x57,0xD5,0x57,0x40,0x04,0x02,0x04,0x05,0x05,\n0x05,0x0F,0x05,0x05,0x05,0x04,/*\"澤\",3466*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x88,0xE8,0x88,0xFF,0x08,0xE9,0x0A,0x09,0x05,0x05,0x09,0x04,\n0x03,0x08,0x04,0x03,0x04,0x0E,/*\"賊\",3467*/},{\n\n0x08,0x04,0x03,0xFE,0x2A,0x2A,0x2A,0x2A,0x2A,0x2A,0x22,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"怎\",3468*/},{\n\n0x10,0x10,0xFF,0x10,0x3E,0xAB,0xA2,0xBE,0xA2,0xAB,0x3E,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"增\",3469*/},{\n\n0x78,0x00,0xFF,0x08,0x3E,0xAB,0xA2,0xBE,0xA2,0xAB,0x3E,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"憎\",3470*/},{\n\n0x3C,0xA4,0xAD,0xB6,0xA4,0xBC,0xA4,0xB6,0xAD,0xA4,0x3C,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"曾\",3471*/},{\n\n0xFE,0x2A,0xFE,0x00,0x3E,0xAB,0xA2,0xBE,0xA2,0xAB,0x3E,0x09,0x05,0x09,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"贈\",3472*/},{\n\n0x88,0x88,0xFF,0x48,0x48,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x08,0x0F,0x00,0x00,\n0x00,0x07,0x08,0x08,0x08,0x0F,/*\"扎\",3473*/},{\n\n0xFC,0x04,0x04,0xFC,0x12,0xEA,0xA6,0xBF,0xA6,0xEA,0x12,0x03,0x01,0x01,0x03,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"喳\",3474*/},{\n\n0x22,0x44,0x20,0x14,0xEC,0xA4,0xBF,0xA4,0xEC,0x14,0x24,0x04,0x02,0x08,0x08,0x0B,\n0x0A,0x0A,0x0A,0x0B,0x08,0x08,/*\"渣\",3475*/},{\n\n0x08,0x88,0x68,0xFF,0x28,0x48,0x00,0xFF,0x00,0x00,0x00,0x01,0x00,0x00,0x0F,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0F,/*\"札\",3476*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xFF,0x00,0x00,0x00,0x00,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"軋\",3477*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFE,0x2A,0xFE,0x00,0xFC,0x00,0xFF,0x0A,0x0F,0x05,0x08,0x05,\n0x01,0x05,0x08,0x01,0x08,0x0F,/*\"鍘\",3478*/},{\n\n0xFF,0x15,0x15,0xFF,0xA0,0xE0,0xA0,0xFF,0x15,0x15,0xFF,0x0F,0x00,0x00,0x03,0x02,\n0x0F,0x02,0x03,0x00,0x08,0x0F,/*\"閘\",3479*/},{\n\n0xFE,0x92,0x92,0xFE,0x00,0x22,0x22,0x2A,0xB1,0x61,0x21,0x0F,0x04,0x04,0x07,0x08,\n0x04,0x02,0x05,0x08,0x08,0x08,/*\"眨\",3480*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x42,0xFE,0x42,0xFE,0x42,0xFE,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x03,0x00,0x03,0x08,0x0F,/*\"柵\",3481*/},{\n\n0x88,0x68,0xFF,0x48,0x96,0x4A,0xF6,0xA3,0xA6,0xAA,0x16,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x0F,0x02,0x02,0x02,0x02,/*\"榨\",3482*/},{\n\n0xFC,0x04,0x04,0xFC,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x03,0x01,0x01,0x03,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"咋\",3483*/},{\n\n0x20,0x18,0x07,0x04,0xFC,0x24,0x24,0x24,0x24,0x24,0x04,0x00,0x00,0x00,0x00,0x0F,\n0x01,0x01,0x01,0x01,0x01,0x01,/*\"乍\",3484*/},{\n\n0x78,0x00,0xFF,0x10,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x08,0x06,0x01,0x02,0x04,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"炸\",3485*/},{\n\n0x54,0x55,0x56,0x54,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x0F,0x05,0x05,0x0F,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"詐\",3486*/},{\n\n0x88,0x88,0xFF,0x48,0xF2,0x16,0x5A,0xF3,0x5A,0x16,0xF2,0x00,0x08,0x0F,0x00,0x0F,\n0x00,0x07,0x05,0x07,0x08,0x0F,/*\"摘\",3487*/},{\n\n0x2A,0xDA,0xAA,0xBA,0x86,0xBB,0x86,0xBA,0xAA,0xD6,0x22,0x08,0x07,0x0A,0x06,0x02,\n0x0E,0x02,0x06,0x0A,0x0F,0x00,/*\"齋\",3488*/},{\n\n0x0C,0x24,0x24,0x24,0x25,0xE6,0x94,0x94,0x94,0x94,0x8C,0x01,0x01,0x01,0x01,0x01,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"宅\",3489*/},{\n\n0x86,0x4A,0x26,0x3A,0xE2,0xA3,0xA2,0xA2,0xA6,0xAA,0x26,0x00,0x00,0x00,0x00,0x0F,\n0x02,0x02,0x02,0x02,0x02,0x02,/*\"窄\",3490*/},{\n\n0x10,0xFC,0x23,0xEA,0xAA,0xAA,0xBF,0xAA,0xAA,0xEA,0x22,0x00,0x0F,0x00,0x0B,0x06,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"債\",3491*/},{\n\n0x86,0xAA,0xAA,0xFE,0xAA,0xAB,0xAA,0xFE,0xAA,0xAA,0x86,0x04,0x02,0x0B,0x06,0x0A,\n0x0F,0x02,0x06,0x0B,0x02,0x04,/*\"寨\",3492*/},{\n\n0xFE,0x92,0xFE,0x00,0xFE,0x15,0xAD,0xB5,0xA7,0xAC,0x14,0x0F,0x04,0x0F,0x08,0x07,\n0x00,0x0E,0x0A,0x0A,0x0E,0x00,/*\"瞻\",3493*/},{\n\n0xFA,0x8A,0xBA,0xAB,0xBA,0x8A,0xFA,0x92,0xFE,0x49,0x49,0x08,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x08,0x00,0x07,0x08,0x0E,/*\"氈\",3494*/},{\n\n0x04,0xFE,0x25,0x95,0xAD,0xA5,0xB5,0xA5,0xAF,0x94,0x24,0x08,0x07,0x00,0x0E,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"詹\",3495*/},{\n\n0x24,0xA8,0xFF,0xA8,0x24,0xC0,0x40,0x7F,0x48,0x48,0xC8,0x01,0x00,0x0F,0x00,0x01,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"粘\",3496*/},{\n\n0x10,0x21,0x02,0xC0,0x40,0x40,0x7F,0x48,0x48,0xC8,0x08,0x04,0x02,0x01,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"沾\",3497*/},{\n\n0x00,0x54,0x54,0x54,0x77,0x4A,0xAE,0xAB,0x7A,0x2A,0xAC,0x08,0x0E,0x0A,0x0B,0x0F,\n0x0B,0x0E,0x0A,0x0B,0x0F,0x09,/*\"盞\",3498*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xFE,0x12,0x12,0xF1,0x10,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x07,0x00,0x00,0x0F,0x00,/*\"斬\",3499*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFE,0xAA,0xAA,0xFA,0xAA,0xFA,0xAE,0x02,0x02,0x0F,0x0A,0x07,\n0x00,0x0F,0x04,0x03,0x04,0x0A,/*\"輾\",3500*/},{\n\n0x10,0xF6,0x54,0xFC,0x54,0xF7,0x14,0xE4,0xA4,0x96,0x90,0x04,0x05,0x05,0x0F,0x05,\n0x05,0x08,0x07,0x00,0x0F,0x00,/*\"嶄\",3501*/},{\n\n0x00,0xFF,0x45,0xD5,0x7D,0x55,0xD5,0x55,0x7D,0x55,0x47,0x08,0x07,0x00,0x0F,0x08,\n0x04,0x01,0x02,0x04,0x0A,0x09,/*\"展\",3502*/},{\n\n0xEA,0xAA,0x7A,0xAF,0xEA,0x12,0xFA,0x57,0xFA,0x52,0x52,0x0F,0x0A,0x0A,0x0A,0x0F,\n0x00,0x0D,0x01,0x0D,0x01,0x0D,/*\"蘸\",3503*/},{\n\n0x88,0x68,0xFF,0x48,0x24,0x24,0xD7,0x8A,0xD7,0xA2,0xBA,0x00,0x00,0x0F,0x00,0x09,\n0x09,0x05,0x02,0x05,0x08,0x0E,/*\"棧\",3504*/},{\n\n0x20,0x10,0xFC,0x03,0xC0,0x40,0x40,0x7F,0x48,0x48,0xC8,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"佔\",3505*/},{\n\n0xF7,0x55,0x57,0xF0,0x57,0x55,0xF7,0x10,0xFF,0x88,0x6A,0x05,0x05,0x05,0x0F,0x05,\n0x05,0x0D,0x04,0x03,0x05,0x0E,/*\"戰\",3506*/},{\n\n0x28,0xC9,0x0A,0xE8,0x08,0xC0,0x40,0x7F,0x48,0x48,0xC8,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"站\",3507*/},{\n\n0x11,0x22,0x80,0x82,0xFF,0xAA,0xAA,0xAA,0xFF,0x82,0x80,0x04,0x02,0x00,0x0F,0x0A,\n0x09,0x08,0x09,0x0A,0x08,0x00,/*\"湛\",3508*/},{\n\n0xD8,0xB4,0x93,0xC8,0x2C,0xA4,0x24,0xE5,0x26,0x24,0x2C,0x0C,0x02,0x04,0x0A,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"綻\",3509*/},{\n\n0x84,0x64,0xFF,0x24,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0x00,0x00,0x0F,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"樟\",3510*/},{\n\n0x08,0x0A,0xFA,0xAE,0xAA,0xAB,0xAA,0xAE,0xFA,0x0A,0x08,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"章\",3511*/},{\n\n0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0x88,0x44,0x23,0x18,0x02,0x02,0x02,0x0F,0x02,\n0x02,0x0A,0x08,0x04,0x02,0x01,/*\"彰\",3512*/},{\n\n0x11,0x22,0x08,0xFA,0xAE,0xAA,0xAB,0xAA,0xAE,0xFA,0x08,0x04,0x02,0x02,0x02,0x02,\n0x02,0x0F,0x02,0x02,0x02,0x02,/*\"漳\",3513*/},{\n\n0xF2,0x92,0x9E,0x40,0xC0,0x7F,0x55,0xD5,0x55,0x41,0x40,0x08,0x08,0x07,0x00,0x0F,\n0x08,0x04,0x01,0x02,0x05,0x08,/*\"張\",3514*/},{\n\n0x06,0x42,0x43,0x5E,0x56,0xD7,0x56,0x5E,0x43,0x02,0x06,0x04,0x04,0x05,0x05,0x0D,\n0x0F,0x05,0x05,0x05,0x04,0x04,/*\"掌\",3515*/},{\n\n0x11,0x22,0xF9,0x89,0x8F,0x40,0xFF,0x55,0xD5,0x55,0x40,0x04,0x02,0x08,0x08,0x07,\n0x00,0x0F,0x08,0x05,0x06,0x09,/*\"漲\",3516*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0x68,0x88,0x08,0xFF,0x08,0x08,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"杖\",3517*/},{\n\n0x08,0x08,0x68,0x88,0x08,0x08,0x88,0x7F,0x08,0x08,0x08,0x00,0x08,0x08,0x04,0x05,\n0x02,0x05,0x04,0x08,0x08,0x08,/*\"丈\",3518*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x40,0xFF,0x55,0xD5,0x55,0x40,0x03,0x00,0x0F,0x02,0x03,\n0x00,0x0F,0x08,0x05,0x06,0x09,/*\"帳\",3519*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x40,0xC0,0x7F,0xD5,0x55,0x55,0x41,0x09,0x05,0x05,0x09,0x00,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"賬\",3520*/},{\n\n0x20,0x10,0xFC,0x03,0x28,0xC8,0x08,0x88,0x7F,0x08,0x08,0x00,0x00,0x0F,0x08,0x04,\n0x02,0x01,0x02,0x04,0x08,0x08,/*\"仗\",3521*/},{\n\n0x00,0xFF,0x49,0xFF,0x40,0xC0,0x7F,0xD5,0x55,0x55,0x41,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"脹\",3522*/},{\n\n0x88,0xFE,0x22,0xEA,0xBA,0xAA,0xAF,0xAA,0xBA,0xEA,0x22,0x08,0x07,0x02,0x03,0x02,\n0x02,0x0E,0x02,0x02,0x03,0x02,/*\"瘴\",3523*/},{\n\n0xFE,0x02,0x32,0xCE,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0x0F,0x02,0x02,0x01,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"障\",3524*/},{\n\n0x88,0x88,0xFF,0x48,0x22,0x92,0x8E,0x82,0xA2,0xA2,0x9E,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"招\",3525*/},{\n\n0xFE,0x22,0x22,0xFE,0x20,0x92,0x8E,0x82,0xA2,0xA2,0x9E,0x07,0x02,0x02,0x07,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"昭\",3526*/},{\n\n0x88,0x88,0xFF,0x48,0x48,0x10,0xFF,0x08,0x89,0x6A,0x08,0x00,0x08,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x0F,/*\"找\",3527*/},{\n\n0x22,0x44,0x00,0x42,0xB2,0x8E,0x82,0x82,0xA2,0xA2,0x9E,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"沼\",3528*/},{\n\n0x20,0xA4,0x24,0xFF,0xA4,0x00,0xFA,0xA8,0xAF,0xA8,0xFA,0x08,0x07,0x04,0x0F,0x08,\n0x08,0x0B,0x08,0x08,0x0A,0x0B,/*\"趙\",3529*/},{\n\n0xFE,0x12,0x12,0xFE,0x20,0xD2,0x4E,0x42,0x52,0x52,0xCE,0x09,0x05,0x01,0x05,0x08,\n0x01,0x05,0x09,0x01,0x05,0x09,/*\"照\",3530*/},{\n\n0x00,0xC7,0x45,0x45,0x47,0x7D,0x57,0x55,0x55,0xD7,0x00,0x04,0x07,0x05,0x05,0x05,\n0x0D,0x05,0x05,0x05,0x07,0x04,/*\"罩\",3531*/},{\n\n0x04,0x88,0x50,0xFF,0x00,0x00,0xFF,0x50,0x88,0x04,0x00,0x01,0x08,0x06,0x01,0x00,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"兆\",3532*/},{\n\n0x20,0x5E,0x4A,0x4B,0x4E,0xE4,0x53,0x56,0xEA,0x56,0x52,0x04,0x04,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x04,0x04,/*\"肇\",3533*/},{\n\n0x40,0x22,0x92,0x8E,0x82,0x82,0x82,0xA2,0xA2,0x9E,0x00,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"召\",3534*/},{\n\n0x21,0xE2,0x00,0xFE,0x12,0x7A,0x52,0x53,0x52,0x7A,0x12,0x08,0x07,0x09,0x08,0x0B,\n0x08,0x0B,0x08,0x0B,0x08,0x0B,/*\"遮\",3535*/},{\n\n0x88,0x88,0xFF,0x48,0x08,0xFE,0x12,0x12,0xF1,0x11,0x10,0x00,0x08,0x0F,0x00,0x08,\n0x07,0x00,0x00,0x0F,0x00,0x00,/*\"折\",3536*/},{\n\n0x12,0x52,0x7F,0x0A,0x40,0x3E,0x0A,0x0A,0x7A,0x09,0x08,0x00,0x0F,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0F,0x00,/*\"哲\",3537*/},{\n\n0x28,0xBA,0xEF,0xBA,0xA8,0xC0,0xAA,0x9F,0xA2,0xBE,0x60,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蟄\",3538*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xEE,0xAB,0xEE,0x12,0xEC,0x0B,0xF8,0x02,0x02,0x0F,0x02,0x0F,\n0x02,0x0F,0x08,0x04,0x03,0x0C,/*\"轍\",3539*/},{\n\n0x90,0x94,0xD4,0x54,0x74,0x5F,0x54,0x5C,0x54,0xD2,0x10,0x00,0x00,0x0F,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"者\",3540*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x90,0xD4,0x7F,0x54,0x58,0xD4,0x12,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"鍺\",3541*/},{\n\n0x02,0xF2,0x52,0x57,0xF2,0x56,0x5A,0x57,0xF2,0x52,0x52,0x08,0x07,0x08,0x04,0x01,\n0x05,0x09,0x05,0x09,0x04,0x08,/*\"蔗\",3542*/},{\n\n0x11,0xF2,0x02,0xAA,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0x02,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"這\",3543*/},{\n\n0x11,0x22,0x88,0x88,0xFF,0x48,0x00,0xFE,0x12,0xF2,0x11,0x04,0x02,0x00,0x08,0x0F,\n0x00,0x08,0x07,0x00,0x0F,0x00,/*\"浙\",3544*/},{\n\n0x22,0x22,0xFE,0x22,0x10,0x48,0x24,0x93,0x44,0x08,0x90,0x04,0x04,0x03,0x02,0x08,\n0x09,0x05,0x04,0x02,0x01,0x00,/*\"珍\",3545*/},{\n\n0x80,0x82,0xFF,0xAA,0xAA,0xFF,0x82,0x12,0x24,0xFF,0x80,0x00,0x0F,0x0A,0x09,0x08,\n0x09,0x0A,0x01,0x01,0x0F,0x00,/*\"斟\",3546*/},{\n\n0x00,0x02,0xFA,0xAA,0xAA,0xAF,0xAA,0xAA,0xFA,0x02,0x00,0x02,0x02,0x0B,0x06,0x02,\n0x02,0x02,0x06,0x0B,0x02,0x02,/*\"真\",3547*/},{\n\n0x7A,0x4A,0x7E,0xCA,0x7E,0x4A,0x78,0xE2,0x9E,0xF2,0x02,0x08,0x09,0x09,0x07,0x05,\n0x05,0x00,0x0F,0x08,0x07,0x08,/*\"甄\",3548*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xC0,0x40,0x7F,0x48,0x48,0xC8,0x00,0x0F,0x04,0x0F,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"砧\",3549*/},{\n\n0x3A,0xE6,0x32,0x00,0xA2,0x6A,0xBA,0xAF,0xAA,0x6A,0xA2,0x09,0x0F,0x05,0x00,0x0A,\n0x06,0x02,0x0F,0x02,0x06,0x0A,/*\"臻\",3550*/},{\n\n0x00,0xF8,0xA8,0xA8,0xA8,0xAF,0xAA,0xAA,0xAA,0xFA,0x00,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"貞\",3551*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0x20,0x20,0xFF,0x20,0x20,0x08,0x09,0x07,0x05,0x04,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"針\",3552*/},{\n\n0x20,0x10,0xFC,0x03,0xF8,0xA8,0xA8,0xAF,0xAA,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x0B,\n0x06,0x02,0x02,0x02,0x06,0x0B,/*\"偵\",3553*/},{\n\n0x88,0x68,0xFF,0x48,0x9C,0x04,0xC4,0x3F,0xC4,0x04,0x1C,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0C,/*\"枕\",3554*/},{\n\n0x08,0x90,0xFE,0x22,0x52,0x4A,0x27,0xAA,0x92,0x22,0x22,0x09,0x04,0x03,0x08,0x09,\n0x09,0x09,0x04,0x04,0x02,0x00,/*\"疹\",3555*/},{\n\n0x54,0x55,0x56,0x54,0x10,0x48,0x24,0x93,0x44,0x08,0x90,0x0F,0x05,0x05,0x0F,0x08,\n0x09,0x05,0x04,0x02,0x01,0x00,/*\"診\",3556*/},{\n\n0x0C,0xD5,0x55,0x55,0x45,0x5F,0x45,0x55,0x55,0x55,0x4C,0x08,0x07,0x01,0x0F,0x09,\n0x01,0x03,0x05,0x05,0x0B,0x09,/*\"震\",3557*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x22,0xEA,0x2A,0xEA,0x2A,0xA2,0x08,0x0F,0x00,0x08,0x07,\n0x00,0x0F,0x04,0x03,0x05,0x08,/*\"振\",3558*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xFA,0xAA,0xAF,0xAA,0xFA,0x00,0x08,0x09,0x07,0x04,0x02,\n0x0B,0x06,0x02,0x06,0x0B,0x02,/*\"鎮\",3559*/},{\n\n0xFE,0x32,0xCE,0x00,0xFA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x0F,0x02,0x01,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"陣\",3560*/},{\n\n0x22,0xAA,0x6A,0x2F,0x8A,0xEA,0x1A,0x2F,0x42,0xA2,0x92,0x09,0x04,0x01,0x05,0x09,\n0x01,0x05,0x09,0x01,0x04,0x08,/*\"蒸\",3561*/},{\n\n0x88,0xFF,0x48,0x56,0x5A,0x56,0xFA,0x52,0x59,0xF5,0x40,0x08,0x0F,0x00,0x01,0x09,\n0x09,0x0F,0x01,0x01,0x03,0x00,/*\"掙\",3562*/},{\n\n0xFE,0x92,0xFE,0x40,0x56,0x5A,0xF6,0x5A,0x59,0xF5,0x40,0x0F,0x04,0x0F,0x00,0x09,\n0x09,0x0F,0x01,0x01,0x03,0x00,/*\"睜\",3563*/},{\n\n0x24,0xF2,0x0F,0x54,0xD7,0x54,0x16,0xEC,0x0B,0xF8,0x08,0x00,0x0F,0x00,0x05,0x07,\n0x05,0x08,0x04,0x03,0x04,0x08,/*\"徵\",3564*/},{\n\n0x8A,0x44,0xFB,0x40,0x56,0x5A,0xF6,0x5A,0x59,0xF5,0x40,0x08,0x08,0x07,0x00,0x09,\n0x09,0x0F,0x01,0x01,0x03,0x00,/*\"猙\",3565*/},{\n\n0x42,0x56,0x5A,0x52,0x56,0xFA,0x51,0x51,0x59,0xF5,0x41,0x00,0x01,0x01,0x09,0x09,\n0x0F,0x01,0x01,0x01,0x03,0x00,/*\"爭\",3566*/},{\n\n0x78,0x00,0xFF,0x08,0x02,0xE2,0x02,0xFE,0x42,0x42,0x42,0x00,0x00,0x0F,0x00,0x08,\n0x0F,0x08,0x0F,0x08,0x08,0x08,/*\"怔\",3567*/},{\n\n0xC2,0xAE,0x9A,0xFF,0x9A,0xAE,0xC4,0xAB,0x92,0xAE,0xC2,0x08,0x08,0x0E,0x08,0x08,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"整\",3568*/},{\n\n0x88,0xFF,0x48,0x10,0x92,0x72,0x02,0xFA,0x26,0xC2,0x30,0x08,0x0F,0x00,0x09,0x08,\n0x08,0x0A,0x0B,0x08,0x08,0x09,/*\"拯\",3569*/},{\n\n0x00,0x02,0xE2,0x02,0x02,0xFE,0x42,0x42,0x42,0x42,0x00,0x08,0x08,0x0F,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"正\",3570*/},{\n\n0x02,0xF2,0x02,0xFE,0x22,0x22,0x10,0xEF,0x08,0xF8,0x08,0x04,0x07,0x04,0x03,0x02,\n0x02,0x08,0x05,0x02,0x05,0x08,/*\"政\",3571*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x00,0xF8,0xA8,0xAF,0xAA,0xFA,0x03,0x00,0x0F,0x02,0x03,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"幀\",3572*/},{\n\n0x08,0x90,0xFC,0x04,0x94,0x15,0x16,0xF4,0x94,0x94,0x94,0x09,0x04,0x03,0x08,0x0F,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"症\",3573*/},{\n\n0xFA,0xAB,0xDE,0xCA,0xBE,0xAB,0xFA,0x00,0xFE,0x32,0xCE,0x0A,0x0A,0x06,0x03,0x06,\n0x0A,0x02,0x00,0x0F,0x02,0x01,/*\"鄭\",3574*/},{\n\n0x55,0x56,0x54,0x20,0xD5,0x49,0x57,0x50,0x4F,0xD2,0x29,0x0F,0x05,0x0F,0x08,0x0B,\n0x0D,0x09,0x09,0x0D,0x0B,0x08,/*\"證\",3575*/},{\n\n0x22,0x22,0x22,0x27,0x2A,0x32,0xA2,0xA7,0x62,0x22,0x02,0x08,0x04,0x04,0x0A,0x09,\n0x09,0x08,0x08,0x08,0x08,0x08,/*\"芝\",3576*/},{\n\n0x88,0x68,0xFF,0x48,0x24,0xE4,0x24,0x3F,0x24,0xE4,0x04,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"枝\",3577*/},{\n\n0x04,0x24,0x64,0xA4,0x24,0x3F,0x24,0x24,0xA4,0x64,0x04,0x08,0x08,0x08,0x04,0x05,\n0x02,0x02,0x05,0x04,0x08,0x08,/*\"支\",3578*/},{\n\n0xFC,0x04,0xFC,0x00,0x24,0xE4,0x24,0x3F,0x24,0xE4,0x04,0x03,0x01,0x03,0x08,0x08,\n0x04,0x05,0x02,0x05,0x08,0x08,/*\"吱\",3579*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x47,0xFC,0x44,0xFE,0x02,0xFE,0x04,0x04,0x03,0x02,0x0B,\n0x06,0x01,0x0E,0x07,0x02,0x07,/*\"蜘\",3580*/},{\n\n0x50,0x48,0x47,0xFC,0x44,0x44,0x40,0xFC,0x04,0x04,0xFC,0x08,0x04,0x03,0x00,0x01,\n0x06,0x00,0x07,0x02,0x02,0x07,/*\"知\",3581*/},{\n\n0x00,0xFE,0x92,0xFE,0x20,0xE4,0x24,0x3F,0x24,0xE4,0x04,0x08,0x07,0x08,0x0F,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"肢\",3582*/},{\n\n0x00,0xFF,0x49,0xFF,0x00,0xCF,0x54,0x54,0x52,0x52,0xD9,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"脂\",3583*/},{\n\n0x10,0x21,0x02,0x20,0x20,0x20,0xFF,0x20,0x20,0x20,0x20,0x04,0x02,0x01,0x00,0x00,\n0x00,0x0F,0x00,0x00,0x00,0x00,/*\"汁\",3584*/},{\n\n0x00,0x08,0x08,0x08,0x09,0x8A,0x48,0x28,0x18,0x08,0x00,0x00,0x08,0x04,0x02,0x05,\n0x08,0x08,0x08,0x08,0x08,0x08,/*\"之\",3585*/},{\n\n0xDC,0xB3,0xC8,0x00,0xD6,0x5B,0xD6,0x10,0xFF,0x12,0xD4,0x0E,0x00,0x06,0x00,0x0F,\n0x05,0x0F,0x04,0x03,0x05,0x0E,/*\"織\",3586*/},{\n\n0x02,0xFE,0x52,0xFE,0x12,0xD6,0x5B,0xD6,0x10,0xFF,0xD4,0x02,0x03,0x02,0x0F,0x01,\n0x0F,0x05,0x07,0x08,0x07,0x0D,/*\"職\",3587*/},{\n\n0x00,0x02,0xFA,0xAA,0xAA,0xAF,0xAA,0xAA,0xAA,0xFA,0x02,0x00,0x08,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x08,/*\"直\",3588*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xFA,0xAA,0xAF,0xAA,0xFA,0x02,0x00,0x00,0x0F,0x00,0x08,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x08,/*\"植\",3589*/},{\n\n0x62,0x9E,0xF2,0x00,0xFA,0xAA,0xAF,0xAA,0xAA,0xFA,0x02,0x08,0x06,0x01,0x08,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x08,/*\"殖\",3590*/},{\n\n0x10,0xB4,0xDF,0xB4,0x10,0x24,0xFF,0x84,0xFC,0x00,0x00,0x02,0x02,0x0F,0x02,0x0A,\n0x04,0x03,0x00,0x03,0x04,0x0E,/*\"執\",3591*/},{\n\n0x10,0xFC,0x03,0x00,0xFA,0xAA,0xAF,0xAA,0xAA,0xFA,0x02,0x00,0x0F,0x00,0x08,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x08,/*\"值\",3592*/},{\n\n0x20,0x10,0xFC,0x03,0x00,0x32,0x2A,0xE6,0x22,0x32,0x62,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"侄\",3593*/},{\n\n0x10,0x10,0xFF,0x10,0x00,0xF8,0x00,0x00,0xFF,0x10,0x10,0x04,0x04,0x03,0x02,0x08,\n0x0F,0x08,0x08,0x0F,0x08,0x08,/*\"址\",3594*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xCF,0x54,0x54,0x52,0x52,0xD9,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"指\",3595*/},{\n\n0x00,0x00,0xF8,0x00,0x00,0x00,0xFF,0x10,0x10,0x10,0x00,0x08,0x08,0x0F,0x08,0x08,\n0x08,0x0F,0x08,0x08,0x08,0x08,/*\"止\",3596*/},{\n\n0x9E,0x12,0xF2,0x9E,0x00,0xF8,0x00,0x00,0xFF,0x10,0x10,0x0F,0x08,0x07,0x04,0x08,\n0x0F,0x08,0x08,0x0F,0x08,0x08,/*\"趾\",3597*/},{\n\n0x00,0x7E,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x7E,0x00,0x08,0x04,0x02,0x00,0x00,\n0x00,0x00,0x00,0x02,0x04,0x08,/*\"只\",3598*/},{\n\n0x00,0xCF,0x54,0x54,0x52,0x52,0x52,0x51,0x51,0xDC,0x00,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"旨\",3599*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0xFE,0x22,0x22,0xFF,0x21,0x21,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x04,0x02,0x03,0x04,0x0E,/*\"紙\",3600*/},{\n\n0x04,0x24,0x24,0x24,0x24,0xBF,0x24,0x24,0x24,0x24,0x04,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"志\",3601*/},{\n\n0x28,0x3A,0xEF,0xBA,0xA8,0xC0,0xAA,0x5F,0x22,0x3E,0x60,0x02,0x02,0x02,0x0A,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"摯\",3602*/},{\n\n0x84,0xFF,0x44,0xFA,0xAB,0x9E,0xAB,0xFA,0xFF,0x31,0xCF,0x08,0x0F,0x00,0x0A,0x06,\n0x03,0x06,0x0A,0x0F,0x02,0x01,/*\"擲\",3603*/},{\n\n0x02,0x22,0x32,0x2A,0x26,0xE2,0x22,0x2A,0x32,0x62,0x02,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"至\",3604*/},{\n\n0x92,0x9A,0xF6,0x92,0x9A,0x20,0xD8,0x0F,0x88,0x78,0x08,0x04,0x04,0x07,0x02,0x0A,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"致\",3605*/},{\n\n0x10,0x17,0xD5,0x55,0x57,0x7D,0x57,0x55,0xD5,0x17,0x10,0x08,0x08,0x0F,0x08,0x08,\n0x0E,0x08,0x08,0x0F,0x08,0x08,/*\"置\",3606*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0xD6,0x5B,0xD6,0x10,0xFF,0xD4,0x03,0x00,0x0F,0x02,0x03,\n0x0F,0x05,0x07,0x08,0x07,0x0D,/*\"幟\",3607*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x10,0x54,0x54,0x5F,0xF4,0x54,0x07,0x04,0x03,0x02,0x07,\n0x00,0x01,0x0A,0x08,0x0F,0x00,/*\"峙\",3608*/},{\n\n0x18,0xD6,0x54,0xFF,0x54,0xD4,0x10,0xFC,0x00,0x00,0xFF,0x00,0x07,0x00,0x0F,0x04,\n0x07,0x00,0x01,0x08,0x08,0x0F,/*\"制\",3609*/},{\n\n0x94,0x53,0xB2,0x9E,0xB2,0xD2,0x80,0xBE,0xA2,0xA2,0x3E,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"智\",3610*/},{\n\n0x12,0xD2,0xFE,0x51,0x90,0x4C,0x48,0xFF,0x48,0x48,0x40,0x01,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"秩\",3611*/},{\n\n0x12,0xD2,0xFE,0x51,0x90,0xFC,0x27,0x24,0xFD,0x26,0x24,0x01,0x00,0x0F,0x00,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"稚\",3612*/},{\n\n0x20,0xDE,0x4A,0xFA,0x49,0x60,0xDE,0x4A,0x7A,0xC9,0x08,0x00,0x0B,0x06,0x02,0x03,\n0x02,0x02,0x03,0x06,0x0B,0x00,/*\"質\",3613*/},{\n\n0x20,0x24,0xA4,0x2A,0x13,0xD6,0x0A,0x0A,0x06,0x82,0x00,0x08,0x09,0x04,0x04,0x02,\n0x01,0x02,0x04,0x05,0x08,0x08,/*\"炙\",3614*/},{\n\n0x08,0x90,0xFE,0xA2,0xAA,0xAA,0xAB,0xBE,0xEA,0xAA,0xA2,0x09,0x04,0x03,0x00,0x01,\n0x02,0x08,0x08,0x0F,0x00,0x00,/*\"痔\",3615*/},{\n\n0x22,0x44,0x6A,0xA7,0xA2,0xAF,0xEA,0xAF,0xA2,0xAF,0x6A,0x04,0x02,0x00,0x07,0x00,\n0x00,0x0F,0x00,0x04,0x07,0x00,/*\"滯\",3616*/},{\n\n0x10,0x22,0x04,0x10,0xD8,0x54,0x53,0x50,0x50,0xD8,0x30,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"治\",3617*/},{\n\n0x16,0x0A,0x96,0xD2,0xB2,0x93,0x92,0xD2,0x96,0x0A,0x16,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"窒\",3618*/},{\n\n0x00,0xF8,0x88,0x88,0x88,0xFF,0x88,0x88,0x88,0xF8,0x00,0x00,0x01,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x01,0x00,/*\"中\",3619*/},{\n\n0x00,0x3C,0x24,0x24,0x24,0xFF,0x24,0x24,0x24,0x3C,0x00,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盅\",3620*/},{\n\n0x00,0x3C,0x24,0x24,0x24,0xFF,0x24,0x24,0x24,0x3C,0x00,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"忠\",3621*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x08,0xFA,0xAA,0xFE,0xA9,0xF9,0x08,0x08,0x09,0x07,0x04,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"鍾\",3622*/},{\n\n0x04,0x74,0x54,0x54,0xD5,0xFE,0x54,0x54,0x54,0x74,0x04,0x04,0x04,0x02,0x0F,0x08,\n0x04,0x01,0x02,0x04,0x0A,0x09,/*\"衷\",3623*/},{\n\n0xD8,0xB4,0x93,0xC8,0x48,0x44,0xAB,0x92,0x2A,0x46,0x40,0x0C,0x02,0x04,0x02,0x04,\n0x02,0x02,0x04,0x05,0x08,0x00,/*\"終\",3624*/},{\n\n0x12,0xD2,0xFE,0x51,0x88,0xFA,0xAA,0xFE,0xA9,0xF9,0x08,0x01,0x00,0x0F,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"種\",3625*/},{\n\n0x00,0xFE,0x92,0xFE,0x08,0xFA,0xAA,0xFE,0xA9,0xF9,0x08,0x08,0x07,0x08,0x0F,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"腫\",3626*/},{\n\n0x08,0xFA,0xAA,0xAA,0xAA,0xFE,0xA9,0xA9,0xA9,0xF9,0x08,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"重\",3627*/},{\n\n0x20,0x10,0xFC,0x03,0xF8,0x88,0x88,0xFF,0x88,0x88,0xF8,0x00,0x00,0x0F,0x00,0x01,\n0x00,0x00,0x0F,0x00,0x00,0x01,/*\"仲\",3628*/},{\n\n0x10,0x9E,0x92,0x92,0x9E,0x93,0x5E,0x52,0x52,0x5E,0x10,0x0A,0x0A,0x09,0x04,0x02,\n0x0F,0x01,0x02,0x04,0x0A,0x09,/*\"衆\",3629*/},{\n\n0x40,0x40,0xFC,0x44,0x56,0x65,0x44,0x44,0xFC,0x40,0x40,0x08,0x06,0x01,0x00,0x01,\n0x02,0x00,0x08,0x0F,0x00,0x00,/*\"舟\",3630*/},{\n\n0x00,0x00,0xFF,0x21,0xA9,0xA9,0xBD,0xA9,0xA9,0x21,0xFF,0x08,0x04,0x03,0x00,0x03,\n0x02,0x02,0x02,0x0B,0x08,0x0F,/*\"周\",3631*/},{\n\n0x20,0x18,0x00,0xFF,0x10,0x20,0xFE,0x00,0x10,0x20,0xFF,0x08,0x04,0x03,0x00,0x00,\n0x00,0x07,0x00,0x00,0x00,0x0F,/*\"州\",3632*/},{\n\n0x22,0x44,0x20,0x10,0xFF,0x10,0x20,0xFE,0x10,0x20,0xFF,0x04,0x02,0x09,0x04,0x03,\n0x00,0x00,0x07,0x00,0x00,0x0F,/*\"洲\",3633*/},{\n\n0x55,0x56,0x54,0x84,0x5A,0x73,0xDE,0x52,0x5A,0x62,0xDE,0x0F,0x05,0x0F,0x00,0x0B,\n0x06,0x03,0x02,0x0B,0x08,0x07,/*\"謅\",3634*/},{\n\n0xF2,0x92,0x9E,0x24,0xA8,0xFF,0xA8,0x24,0xF2,0x92,0x9E,0x08,0x08,0x07,0x01,0x00,\n0x0F,0x00,0x01,0x08,0x08,0x07,/*\"粥\",3635*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xF8,0x48,0xFF,0x48,0xF8,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x04,0x07,0x04,0x0F,/*\"軸\",3636*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0x28,0xC8,0x08,0xFF,0x08,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x00,0x00,0x08,0x0F,0x00,/*\"肘\",3637*/},{\n\n0xC0,0x51,0x55,0x55,0x55,0xD5,0x55,0x55,0x55,0x5F,0xC0,0x00,0x07,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x05,0x07,0x00,/*\"帚\",3638*/},{\n\n0x00,0x1E,0x12,0xD2,0x5E,0x40,0x5E,0xD2,0x12,0x1E,0x00,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"咒\",3639*/},{\n\n0x2C,0xDB,0x8E,0xAA,0xBE,0x00,0xFC,0xA4,0x3F,0xE4,0x0C,0x0B,0x06,0x03,0x0A,0x0F,\n0x04,0x0B,0x05,0x02,0x05,0x08,/*\"皺\",3640*/},{\n\n0x0C,0xE4,0x24,0x24,0x25,0xFE,0x24,0x24,0x24,0xE4,0x0C,0x00,0x0F,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x0F,0x00,/*\"宙\",3641*/},{\n\n0x08,0x2A,0xEA,0xAA,0xAA,0xBF,0xAA,0xAA,0xEA,0x3E,0x28,0x08,0x08,0x0B,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0B,0x08,0x08,/*\"晝\",3642*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x51,0xDF,0x55,0xFF,0xA9,0x12,0xAE,0x04,0x0A,0x08,0x07,0x09,\n0x04,0x02,0x0F,0x00,0x03,0x04,/*\"驟\",3643*/},{\n\n0x22,0xFE,0x22,0x00,0x28,0x26,0xA4,0xFF,0xA4,0x24,0x20,0x04,0x07,0x02,0x00,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"珠\",3644*/},{\n\n0x88,0x68,0xFF,0x48,0x28,0x26,0xA4,0xFF,0xA4,0x24,0x20,0x00,0x00,0x0F,0x00,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"株\",3645*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x26,0xA4,0xFF,0xA4,0x24,0x20,0x04,0x04,0x03,0x02,0x07,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"蛛\",3646*/},{\n\n0x20,0x28,0x26,0xA4,0x64,0xFF,0x64,0xA4,0x24,0x20,0x20,0x02,0x02,0x01,0x00,0x00,\n0x0F,0x00,0x00,0x01,0x02,0x02,/*\"朱\",3647*/},{\n\n0x4A,0x26,0xFA,0x92,0x08,0x90,0xD4,0x7F,0x54,0xD8,0x14,0x0A,0x09,0x07,0x00,0x01,\n0x00,0x0F,0x05,0x05,0x0F,0x00,/*\"豬\",3648*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x90,0xD4,0x7F,0x54,0x58,0xD4,0x0F,0x05,0x05,0x0F,0x01,\n0x00,0x0F,0x05,0x05,0x05,0x0F,/*\"諸\",3649*/},{\n\n0x54,0x55,0x56,0x54,0x28,0x26,0xA4,0xFF,0xA4,0x24,0x20,0x0F,0x05,0x05,0x0F,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"誅\",3650*/},{\n\n0x11,0xF2,0x00,0x52,0x4A,0xA6,0x5A,0xF2,0x22,0x52,0x8A,0x08,0x07,0x08,0x09,0x09,\n0x0A,0x0A,0x09,0x08,0x08,0x09,/*\"逐\",3651*/},{\n\n0x20,0x10,0x0C,0xFB,0x08,0x28,0x10,0x0C,0x0B,0xF8,0x08,0x00,0x00,0x00,0x0F,0x00,\n0x00,0x00,0x08,0x08,0x0F,0x00,/*\"竹\",3652*/},{\n\n0x78,0x00,0xFF,0x28,0xD7,0x5D,0xF7,0x55,0xD7,0x15,0xF7,0x08,0x06,0x01,0x02,0x05,\n0x05,0x07,0x05,0x0D,0x08,0x07,/*\"燭\",3653*/},{\n\n0x48,0x48,0xEA,0xAA,0xBA,0xAF,0xAA,0xAC,0xAA,0xE8,0x08,0x08,0x04,0x03,0x06,0x0A,\n0x02,0x06,0x0A,0x02,0x07,0x08,/*\"煮\",3654*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0x88,0x89,0xFA,0x88,0x88,0x08,0x00,0x08,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"拄\",3655*/},{\n\n0xFE,0x92,0xFE,0x00,0xFF,0x6D,0xD5,0x7D,0xD5,0x6D,0xC7,0x0F,0x04,0x07,0x08,0x07,\n0x05,0x07,0x05,0x05,0x08,0x0F,/*\"矚\",3656*/},{\n\n0xFE,0x02,0xFE,0x00,0xFF,0x6D,0xD5,0x7D,0xD5,0x6D,0xC7,0x03,0x01,0x03,0x08,0x07,\n0x05,0x07,0x05,0x05,0x08,0x0F,/*\"囑\",3657*/},{\n\n0x00,0x88,0x88,0x88,0x89,0xFA,0x88,0x88,0x88,0x88,0x00,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"主\",3658*/},{\n\n0x22,0x22,0xAA,0xAF,0xEA,0xBE,0xAA,0xB7,0xAA,0xA2,0x22,0x01,0x01,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"著\",3659*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0x88,0x89,0xFA,0x88,0x88,0x08,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"柱\",3660*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0x08,0xFF,0x08,0x08,0xF8,0x04,0x07,0x04,0x02,0x03,\n0x0A,0x06,0x01,0x08,0x08,0x07,/*\"助\",3661*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x88,0x89,0xFA,0x88,0x88,0x04,0x04,0x03,0x02,0x07,\n0x00,0x08,0x08,0x0F,0x08,0x08,/*\"蛀\",3662*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x00,0x2C,0x24,0x25,0xE6,0x24,0x2C,0x09,0x05,0x05,0x09,0x00,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"貯\",3663*/},{\n\n0x4A,0xF9,0x4A,0x00,0x22,0xAA,0xAA,0xEF,0xAA,0xAA,0x6A,0x0A,0x0F,0x05,0x00,0x0E,\n0x0A,0x0E,0x02,0x0A,0x0F,0x02,/*\"鑄\",3664*/},{\n\n0x44,0x4B,0x3A,0x2E,0x42,0xB8,0x2C,0x4B,0x3A,0x46,0x62,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"築\",3665*/},{\n\n0x20,0x10,0xFC,0x03,0x08,0x88,0x89,0xFA,0x88,0x88,0x08,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"住\",3666*/},{\n\n0x22,0x44,0x00,0x88,0x88,0x89,0xFA,0x88,0x88,0x88,0x00,0x04,0x02,0x08,0x08,0x08,\n0x08,0x0F,0x08,0x08,0x08,0x08,/*\"注\",3667*/},{\n\n0x84,0x45,0xF6,0x4C,0x80,0x7E,0xC2,0x42,0xC2,0x7E,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"祝\",3668*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x00,0x88,0x89,0xFA,0x88,0x88,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x08,0x08,0x0F,0x08,0x08,/*\"駐\",3669*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x02,0xFE,0x02,0xFE,0x01,0x00,0x08,0x0F,0x00,0x08,0x07,\n0x00,0x0F,0x00,0x01,0x06,0x08,/*\"抓\",3670*/},{\n\n0x00,0xFE,0x02,0x02,0xFE,0x02,0x02,0x7F,0x81,0x01,0x00,0x08,0x07,0x00,0x00,0x0F,\n0x00,0x00,0x00,0x01,0x06,0x08,/*\"爪\",3671*/},{\n\n0x88,0xFF,0x48,0x00,0x7C,0x54,0x54,0xFF,0x54,0xD4,0x7C,0x08,0x0F,0x00,0x00,0x08,\n0x08,0x04,0x02,0x03,0x04,0x0E,/*\"拽\",3672*/},{\n\n0x82,0x82,0xFA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFA,0x82,0xC2,0x02,0x02,0x06,0x0A,0x02,\n0x02,0x02,0x0A,0x0F,0x02,0x02,/*\"專\",3673*/},{\n\n0x42,0xF2,0x2E,0xE2,0x80,0xFA,0xAA,0xFF,0xAA,0xFA,0x82,0x00,0x0F,0x04,0x0F,0x02,\n0x06,0x0A,0x02,0x0A,0x0F,0x02,/*\"磚\",3674*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xF8,0xAA,0xFF,0xAA,0xFA,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x02,0x06,0x0A,0x0F,0x02,/*\"轉\",3675*/},{\n\n0x88,0xFF,0x48,0x00,0x9F,0xE5,0xB7,0x80,0x9F,0xE5,0xB7,0x08,0x0F,0x00,0x02,0x0A,\n0x07,0x02,0x02,0x02,0x07,0x0A,/*\"撰\",3676*/},{\n\n0xFE,0x2A,0xFE,0x40,0x55,0xFE,0x54,0xFE,0x55,0xF4,0x40,0x09,0x05,0x09,0x04,0x03,\n0x0F,0x01,0x0F,0x03,0x05,0x08,/*\"賺\",3677*/},{\n\n0x24,0xA3,0xB2,0x6E,0x6A,0xAC,0x2B,0x3A,0xA6,0x62,0x22,0x08,0x0A,0x0A,0x05,0x05,\n0x0A,0x0F,0x01,0x02,0x04,0x04,/*\"篆\",3678*/},{\n\n0x88,0x68,0xFF,0x48,0xA2,0x6A,0xBA,0x2F,0xAA,0xEA,0xA2,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x08,0x0A,0x0F,0x00,/*\"樁\",3679*/},{\n\n0x02,0x72,0x42,0xF7,0x82,0x82,0x82,0xF7,0x82,0x82,0x82,0x09,0x07,0x01,0x0F,0x00,\n0x08,0x08,0x0F,0x08,0x08,0x00,/*\"莊\",3680*/},{\n\n0xD0,0xB6,0x94,0xFF,0x80,0xE4,0xA4,0xBF,0xA4,0xA4,0x84,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"裝\",3681*/},{\n\n0x40,0xCE,0x48,0xFF,0x00,0x48,0xB8,0x0F,0x88,0x78,0x08,0x04,0x03,0x00,0x0F,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"妝\",3682*/},{\n\n0x84,0x84,0xFF,0x44,0x08,0xFA,0xAE,0xFB,0xAE,0xFA,0x08,0x00,0x08,0x0F,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"撞\",3683*/},{\n\n0x40,0xCE,0x48,0xFF,0x10,0x10,0x10,0xFF,0x10,0x10,0x10,0x04,0x03,0x00,0x0F,0x00,\n0x04,0x04,0x07,0x04,0x04,0x00,/*\"壯\",3684*/},{\n\n0x40,0xDE,0x50,0xFF,0x10,0x10,0xD0,0x3F,0xD0,0x12,0x14,0x08,0x07,0x00,0x0F,0x08,\n0x06,0x01,0x00,0x01,0x06,0x08,/*\"狀\",3685*/},{\n\n0x88,0x68,0xFF,0x28,0x50,0xFC,0x27,0x24,0xFD,0x26,0x24,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"椎\",3686*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x10,0xFC,0x27,0x24,0xFD,0x26,0x04,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x08,/*\"錐\",3687*/},{\n\n0x11,0xF2,0x00,0xFC,0x54,0x56,0x55,0x54,0x54,0xDC,0x00,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"追\",3688*/},{\n\n0x48,0xAA,0xBA,0xAF,0xEA,0x8A,0xC4,0xAB,0x92,0xAE,0x42,0x00,0x07,0x0C,0x05,0x06,\n0x04,0x05,0x06,0x0C,0x07,0x00,/*\"贅\",3689*/},{\n\n0xFF,0x21,0x49,0x37,0xAA,0xAA,0x57,0xAE,0xFA,0x13,0x2A,0x09,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"墜\",3690*/},{\n\n0xDC,0xB3,0xC8,0x00,0xAA,0x92,0xAE,0x00,0xAA,0x92,0xAE,0x0E,0x00,0x06,0x00,0x0A,\n0x04,0x0B,0x00,0x0B,0x04,0x0B,/*\"綴\",3691*/},{\n\n0x54,0x55,0x56,0x54,0x02,0xBA,0xAA,0xAB,0xAA,0xBA,0x02,0x0F,0x05,0x05,0x0F,0x02,\n0x02,0x0A,0x0E,0x03,0x02,0x02,/*\"諄\",3692*/},{\n\n0x84,0x49,0x22,0x04,0xFE,0xAB,0xAA,0xFF,0xAA,0xAA,0xAA,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"準\",3693*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0xDF,0x11,0xF1,0x91,0x9F,0x80,0x00,0x08,0x0F,0x08,0x04,\n0x03,0x04,0x0F,0x08,0x08,0x08,/*\"捉\",3694*/},{\n\n0x88,0x88,0xFF,0x48,0xBC,0x20,0x20,0xFF,0x20,0x20,0xBC,0x00,0x08,0x0F,0x00,0x07,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"拙\",3695*/},{\n\n0x00,0xF8,0xA8,0xA8,0xA8,0xAF,0xAA,0xAA,0xAA,0xFA,0x02,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"卓\",3696*/},{\n\n0x00,0xF8,0xA8,0xA8,0xA8,0xAF,0xAA,0xAA,0xAA,0xFA,0x00,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"桌\",3697*/},{\n\n0x22,0xFE,0x22,0x00,0x92,0x6A,0xA6,0x9A,0xF2,0xA2,0x12,0x04,0x07,0x02,0x00,0x04,\n0x02,0x09,0x08,0x07,0x00,0x01,/*\"琢\",3698*/},{\n\n0x02,0x72,0x42,0x47,0x42,0xFA,0x42,0x47,0x42,0x72,0x02,0x00,0x0F,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x00,/*\"茁\",3699*/},{\n\n0xFA,0x4A,0x3E,0x0A,0x3E,0x4A,0xFA,0x28,0xC7,0x04,0xFC,0x0F,0x05,0x05,0x05,0x05,\n0x05,0x0F,0x00,0x08,0x08,0x07,/*\"酌\",3700*/},{\n\n0xFE,0x02,0xFE,0x00,0x92,0x6A,0xA6,0x9A,0xF2,0xA2,0x12,0x03,0x01,0x03,0x00,0x04,\n0x02,0x09,0x08,0x07,0x00,0x01,/*\"啄\",3701*/},{\n\n0x22,0xAA,0xEA,0xBB,0xAE,0xAA,0xAA,0xAB,0xEA,0x22,0x22,0x01,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"着\",3702*/},{\n\n0x78,0x00,0xFF,0x08,0x14,0x08,0x27,0xC4,0x04,0x04,0xFC,0x08,0x06,0x01,0x02,0x04,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"灼\",3703*/},{\n\n0x10,0x21,0x02,0x20,0xD7,0x5D,0xF7,0x55,0xD7,0x15,0xF7,0x04,0x02,0x01,0x00,0x05,\n0x05,0x07,0x05,0x0D,0x08,0x07,/*\"濁\",3704*/},{\n\n0x62,0x52,0xCA,0x47,0x22,0x02,0x62,0x57,0xCA,0x42,0x22,0x06,0x05,0x04,0x06,0x0C,\n0x00,0x06,0x05,0x04,0x06,0x0C,/*\"茲\",3705*/},{\n\n0x54,0x55,0x56,0x54,0x21,0x12,0x44,0x23,0x1A,0x22,0x46,0x0F,0x05,0x05,0x0F,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"諮\",3706*/},{\n\n0x10,0xD1,0x4A,0xC0,0x54,0x53,0xCA,0x46,0x4A,0xD2,0x16,0x00,0x0B,0x06,0x02,0x03,\n0x02,0x02,0x03,0x06,0x0B,0x00,/*\"資\",3707*/},{\n\n0xA2,0x94,0x80,0xA4,0xD3,0x8A,0x86,0x8A,0x92,0xAA,0xA6,0x08,0x08,0x0A,0x0B,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x00,/*\"姿\",3708*/},{\n\n0x11,0x22,0x00,0x64,0x5D,0xC6,0x34,0x64,0x5E,0xC5,0x34,0x04,0x02,0x01,0x06,0x05,\n0x0E,0x00,0x06,0x05,0x04,0x0E,/*\"滋\",3709*/},{\n\n0x22,0x44,0x04,0xCA,0x51,0x44,0xCA,0x51,0x44,0x4A,0xD1,0x04,0x02,0x00,0x0F,0x05,\n0x05,0x07,0x05,0x05,0x05,0x0F,/*\"淄\",3710*/},{\n\n0x82,0x82,0xF2,0x4E,0x00,0x20,0xD8,0x0F,0x88,0x78,0x08,0x00,0x08,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"孜\",3711*/},{\n\n0x10,0x1E,0x50,0x6F,0xDA,0x4A,0x40,0x2F,0x94,0x12,0x19,0x00,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x00,/*\"紫\",3712*/},{\n\n0x20,0x10,0xFC,0x03,0x40,0x42,0x42,0xF2,0x4A,0x46,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x08,0x0F,0x00,0x00,0x00,/*\"仔\",3713*/},{\n\n0x24,0xA8,0xFF,0xA8,0x24,0x42,0x42,0xF2,0x4A,0x46,0x40,0x01,0x00,0x0F,0x00,0x01,\n0x00,0x08,0x0F,0x00,0x00,0x00,/*\"籽\",3714*/},{\n\n0x22,0x44,0x86,0x92,0xB2,0xD6,0x9B,0xD2,0xB2,0x92,0x86,0x04,0x02,0x00,0x02,0x02,\n0x02,0x0F,0x02,0x02,0x02,0x00,/*\"滓\",3715*/},{\n\n0x40,0x40,0x42,0x42,0x42,0xF2,0x4A,0x46,0x42,0x40,0x40,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"子\",3716*/},{\n\n0x00,0xFC,0x24,0x24,0x26,0x25,0x24,0x24,0x24,0xFC,0x00,0x00,0x0F,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0F,0x00,/*\"自\",3717*/},{\n\n0x22,0x44,0x22,0xEA,0xAA,0xAA,0xBF,0xAA,0xAA,0xEA,0x22,0x04,0x02,0x00,0x0B,0x06,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"漬\",3718*/},{\n\n0x0C,0x04,0x24,0x24,0x25,0x26,0xA4,0x64,0x24,0x04,0x0C,0x01,0x01,0x01,0x09,0x09,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"字\",3719*/},{\n\n0xD4,0x5F,0x54,0x56,0x5D,0x74,0x40,0x44,0x52,0x49,0xC4,0x00,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x00,/*\"鬃\",3720*/},{\n\n0x88,0x68,0xFF,0x48,0x06,0x92,0x92,0x93,0x92,0x92,0x86,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"棕\",3721*/},{\n\n0x9E,0x12,0xFE,0xA4,0xF2,0x09,0x90,0x0F,0xD0,0x0F,0x10,0x0F,0x08,0x07,0x04,0x0F,\n0x08,0x07,0x08,0x0F,0x09,0x09,/*\"蹤\",3722*/},{\n\n0x86,0x82,0x92,0x92,0x92,0x93,0x92,0x92,0x92,0x82,0x86,0x08,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x08,/*\"宗\",3723*/},{\n\n0xD8,0xB4,0x93,0xC8,0x06,0x92,0x92,0x93,0x92,0x92,0x86,0x0C,0x02,0x04,0x02,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"綜\",3724*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFE,0x92,0xDE,0xAB,0xDA,0x82,0xFE,0x0E,0x00,0x06,0x08,0x06,\n0x00,0x06,0x09,0x0C,0x02,0x0C,/*\"總\",3725*/},{\n\n0xDC,0xB3,0xC8,0x24,0xF2,0x09,0x90,0x0F,0xD0,0x0F,0x10,0x0E,0x00,0x06,0x00,0x0F,\n0x08,0x07,0x08,0x0F,0x09,0x09,/*\"縱\",3726*/},{\n\n0x5A,0x73,0xDE,0x52,0x5A,0x62,0xDE,0x00,0xFE,0x32,0xCE,0x0B,0x06,0x03,0x02,0x0B,\n0x08,0x07,0x00,0x0F,0x02,0x01,/*\"鄒\",3727*/},{\n\n0x20,0x24,0xA4,0x24,0x24,0xFF,0x24,0x24,0x24,0x24,0x20,0x08,0x04,0x03,0x04,0x08,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"走\",3728*/},{\n\n0x20,0xA2,0x6A,0xBA,0xAE,0xAB,0xAA,0xAA,0x6A,0xA2,0x20,0x01,0x02,0x0A,0x0A,0x06,\n0x03,0x02,0x06,0x0A,0x02,0x01,/*\"奏\",3729*/},{\n\n0x88,0x88,0xFF,0x48,0xA2,0x6A,0xBA,0xAF,0xAA,0x6A,0xA2,0x00,0x08,0x0F,0x00,0x02,\n0x0A,0x06,0x03,0x06,0x0A,0x02,/*\"揍\",3730*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0xFE,0x92,0x92,0x92,0xFE,0x00,0x01,0x00,0x0F,0x00,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"租\",3731*/},{\n\n0x00,0x1F,0x91,0x11,0x11,0xF1,0x91,0x91,0x91,0x9F,0x00,0x08,0x04,0x03,0x04,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"足\",3732*/},{\n\n0x00,0x44,0x24,0x1C,0x25,0xC6,0x24,0x1C,0x24,0x44,0x00,0x01,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"卒\",3733*/},{\n\n0x08,0xF8,0x49,0x4A,0xD0,0x08,0x47,0x34,0xE4,0x24,0x24,0x08,0x07,0x08,0x08,0x07,\n0x00,0x09,0x05,0x03,0x05,0x09,/*\"族\",3734*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0xFE,0x92,0x92,0x92,0xFE,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"祖\",3735*/},{\n\n0x54,0x55,0x56,0x54,0x00,0xFE,0x92,0x92,0x92,0xFE,0x00,0x0F,0x05,0x05,0x0F,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"詛\",3736*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0xFE,0x92,0x92,0x92,0xFE,0x00,0x0F,0x02,0x02,0x01,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"阻\",3737*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0xFE,0x92,0x92,0xFE,0x00,0x0E,0x00,0x06,0x00,0x06,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"組\",3738*/},{\n\n0x4A,0xF9,0x4A,0x44,0xEB,0x5A,0xFF,0x6A,0x5A,0x7F,0xEA,0x0A,0x0F,0x05,0x00,0x0B,\n0x06,0x02,0x03,0x02,0x06,0x0B,/*\"鑽\",3739*/},{\n\n0x44,0xC3,0x7A,0x4E,0x5A,0x68,0x5C,0x6B,0x7A,0xC6,0x42,0x01,0x0A,0x06,0x03,0x0A,\n0x0E,0x02,0x02,0x07,0x0A,0x01,/*\"纂\",3740*/},{\n\n0xFC,0x04,0xFC,0x4E,0xE8,0x5F,0x55,0xD0,0x77,0x4A,0xCD,0x03,0x01,0x03,0x08,0x07,\n0x05,0x05,0x0F,0x05,0x05,0x0F,/*\"嘴\",3741*/},{\n\n0xFD,0xA5,0x9F,0xA5,0xFD,0x00,0x24,0x1D,0xA6,0x1C,0x24,0x0F,0x04,0x04,0x04,0x0F,\n0x00,0x01,0x01,0x0F,0x01,0x01,/*\"醉\",3742*/},{\n\n0x10,0xF0,0x5F,0x55,0xF5,0x15,0x55,0xD5,0x5F,0xD0,0x10,0x04,0x07,0x05,0x05,0x0F,\n0x02,0x08,0x05,0x02,0x05,0x08,/*\"最\",3743*/},{\n\n0x20,0xAF,0xA9,0xA9,0xFF,0x09,0xFF,0xA9,0xA9,0xAF,0x20,0x02,0x02,0x02,0x02,0x0F,\n0x00,0x0F,0x02,0x02,0x02,0x02,/*\"罪\",3744*/},{\n\n0x02,0xFA,0xAB,0x9E,0xAA,0xAA,0xAA,0x9E,0xAB,0xFA,0x02,0x02,0x02,0x06,0x0A,0x02,\n0x02,0x02,0x0A,0x0F,0x02,0x02,/*\"尊\",3745*/},{\n\n0x11,0xF2,0x00,0xFA,0xAB,0xDE,0xCA,0xBE,0xAB,0xFA,0x00,0x08,0x07,0x08,0x0A,0x0E,\n0x0A,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"遵\",3746*/},{\n\n0xFE,0x22,0x22,0xFE,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x07,0x02,0x02,0x07,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"昨\",3747*/},{\n\n0x04,0x04,0x84,0x74,0x4F,0x44,0xC4,0x44,0x44,0x44,0x04,0x04,0x02,0x09,0x08,0x08,\n0x08,0x0F,0x08,0x08,0x08,0x08,/*\"左\",3748*/},{\n\n0x20,0x10,0xFC,0x03,0x84,0x74,0x4F,0xC4,0x44,0x44,0x04,0x00,0x00,0x0F,0x02,0x09,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"佐\",3749*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0x07,0xFC,0x24,0x24,0x24,0x04,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"柞\",3750*/},{\n\n0x10,0xFC,0x03,0xC8,0x7F,0xC8,0x10,0xEF,0x08,0xF8,0x08,0x00,0x0F,0x00,0x07,0x02,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"做\",3751*/},{\n\n0x20,0x10,0xFC,0x03,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"作\",3752*/},{\n\n0x40,0x20,0x1E,0x20,0x40,0xFF,0x40,0x20,0x1E,0x20,0x40,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"坐\",3753*/},{\n\n0x00,0xFC,0x84,0x44,0x34,0x45,0xFE,0x44,0x34,0x44,0x84,0x08,0x07,0x08,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x08,/*\"座\",3754*/},{\n\n0x20,0x22,0x22,0x22,0x22,0xE2,0x22,0x22,0x22,0x22,0x20,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"亍\",3755*/},{\n\n0x02,0x02,0x02,0xFE,0x02,0x02,0x02,0xFE,0x02,0x02,0x02,0x00,0x08,0x06,0x01,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"丌\",3756*/},{\n\n0x02,0x02,0x02,0xFE,0x02,0x02,0x02,0xFE,0x02,0x02,0x02,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"兀\",3757*/},{\n\n0x02,0xF2,0x82,0x82,0x82,0xFE,0x92,0x92,0x92,0x92,0x92,0x00,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"丐\",3758*/},{\n\n0x10,0x10,0xFF,0x10,0x10,0x10,0x10,0x10,0xFF,0x10,0x10,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x0F,0x00,0x00,/*\"廿\",3759*/},{\n\n0x20,0x20,0xFF,0x20,0x20,0xFE,0x20,0x20,0xFF,0x20,0x20,0x08,0x04,0x03,0x00,0x00,\n0x07,0x00,0x00,0x0F,0x00,0x00,/*\"卅\",3760*/},{\n\n0x82,0x82,0x42,0x22,0x12,0xFA,0x06,0x12,0x12,0x22,0x42,0x08,0x08,0x08,0x08,0x08,\n0x0B,0x08,0x08,0x08,0x08,0x08,/*\"丕\",3761*/},{\n\n0x02,0xC2,0x3E,0x12,0x52,0x92,0x12,0x12,0xF2,0x02,0x02,0x08,0x09,0x08,0x09,0x0A,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"亙\",3762*/},{\n\n0x10,0x90,0x51,0x31,0x01,0xF9,0x25,0x53,0x90,0x08,0x00,0x09,0x08,0x08,0x0A,0x0A,\n0x0B,0x08,0x08,0x08,0x09,0x09,/*\"丞\",3763*/},{\n\n0xC1,0x41,0x5D,0xD5,0x55,0x55,0x55,0xD5,0x5D,0x41,0xC1,0x0F,0x00,0x02,0x02,0x03,\n0x0E,0x03,0x02,0x02,0x08,0x0F,/*\"鬲\",3764*/},{\n\n0x49,0xC9,0x69,0x45,0xC5,0x1F,0x21,0x25,0xA5,0x69,0x09,0x09,0x05,0x02,0x02,0x05,\n0x08,0x01,0x09,0x0F,0x01,0x01,/*\"孬\",3765*/},{\n\n0x21,0xAF,0xAB,0xAF,0x21,0xFF,0x21,0xAF,0xAB,0xAF,0x21,0x08,0x0B,0x0A,0x0B,0x08,\n0x0F,0x08,0x0B,0x0A,0x0B,0x08,/*\"噩\",3766*/},{\n\n0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"丨\",3767*/},{\n\n0xC0,0x5F,0x55,0x55,0x55,0xFF,0x55,0x55,0x55,0x5F,0xC0,0x0F,0x00,0x02,0x02,0x02,\n0x03,0x02,0x03,0x06,0x08,0x0F,/*\"禺\",3768*/},{\n\n0x00,0x00,0x00,0x00,0xC0,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x06,0x01,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"丿\",3769*/},{\n\n0x00,0xFF,0x20,0x20,0x20,0x10,0x10,0x08,0x08,0x04,0x80,0x00,0x03,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x07,/*\"匕\",3770*/},{\n\n0x40,0x42,0x42,0x42,0x42,0xFE,0x21,0x21,0x21,0x21,0x20,0x00,0x00,0x00,0x00,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"乇\",3771*/},{\n\n0x20,0x22,0x22,0x22,0xA2,0x7E,0xA1,0x21,0x21,0x20,0x20,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"夭\",3772*/},{\n\n0x20,0x22,0x22,0x94,0x14,0x08,0x08,0x14,0x92,0x11,0x20,0x08,0x08,0x08,0x04,0x05,\n0x02,0x02,0x05,0x04,0x08,0x08,/*\"爻\",3773*/},{\n\n0x00,0xFE,0x0A,0xEA,0x2A,0x2A,0x2A,0x29,0x29,0xE9,0x08,0x08,0x07,0x00,0x07,0x08,\n0x08,0x08,0x09,0x09,0x08,0x0E,/*\"卮\",3774*/},{\n\n0x00,0xFE,0x22,0x22,0x22,0x22,0x7E,0xA1,0x21,0x21,0x20,0x00,0x0F,0x04,0x02,0x00,\n0x04,0x08,0x01,0x02,0x04,0x0F,/*\"氐\",3775*/},{\n\n0xFC,0x04,0x04,0x16,0xA5,0x44,0xA4,0x14,0x04,0x04,0xFC,0x0F,0x04,0x04,0x05,0x04,\n0x04,0x04,0x05,0x04,0x04,0x0F,/*\"囟\",3776*/},{\n\n0x00,0xFF,0x00,0xD6,0x5D,0x54,0xDA,0x00,0xFF,0x00,0x00,0x08,0x07,0x00,0x0F,0x05,\n0x0D,0x0F,0x00,0x07,0x08,0x0E,/*\"胤\",3777*/},{\n\n0x08,0xFF,0x08,0xF8,0x02,0xFA,0xAB,0xAE,0xAA,0xFB,0x02,0x08,0x07,0x00,0x07,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"馗\",3778*/},{\n\n0xFB,0x4A,0x6A,0xFA,0x40,0xA4,0x34,0xAD,0x26,0xB4,0x64,0x03,0x0A,0x0B,0x07,0x08,\n0x07,0x00,0x07,0x00,0x0F,0x08,/*\"毓\",3779*/},{\n\n0x20,0xAE,0xEA,0xAB,0xAE,0xBA,0xAE,0xAA,0xEA,0xAE,0x20,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"睾\",3780*/},{\n\n0xD5,0x52,0x78,0x57,0xD0,0x10,0xA7,0xAA,0xFA,0xA9,0x2C,0x0B,0x0D,0x09,0x0D,0x0B,\n0x00,0x08,0x0B,0x04,0x0B,0x08,/*\"鼗\",3781*/},{\n\n0x00,0x00,0x00,0x10,0x20,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\n0x00,0x03,0x00,0x00,0x00,0x00,/*\"丶\",3782*/},{\n\n0xF8,0x89,0x89,0xF9,0x01,0xF9,0x05,0xAB,0x49,0xA8,0x18,0x08,0x08,0x08,0x08,0x0A,\n0x0B,0x09,0x08,0x08,0x08,0x09,/*\"亟\",3783*/},{\n\n0xE9,0x87,0x81,0xFF,0xD5,0x55,0xFF,0x81,0x95,0x97,0xEC,0x0A,0x06,0x02,0x02,0x0F,\n0x00,0x0F,0x02,0x02,0x02,0x0E,/*\"鼐\",3784*/},{\n\n0x40,0x40,0xFE,0x20,0x10,0x10,0x08,0x08,0xFC,0x00,0x00,0x00,0x00,0x07,0x08,0x08,\n0x09,0x09,0x09,0x08,0x08,0x0E,/*\"乜\",3785*/},{\n\n0xC0,0x40,0x7F,0x48,0x48,0xC8,0x00,0xFF,0x00,0x00,0x00,0x0F,0x04,0x04,0x04,0x04,\n0x0F,0x00,0x07,0x08,0x08,0x0E,/*\"乩\",3786*/},{\n\n0x10,0x11,0xF1,0x11,0x11,0x11,0x11,0x11,0xF1,0x11,0x10,0x08,0x06,0x01,0x00,0x00,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"亓\",3787*/},{\n\n0x04,0x44,0x44,0x5F,0x40,0xEF,0x40,0x5F,0x44,0x44,0x04,0x01,0x01,0x01,0x01,0x01,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"羋\",3788*/},{\n\n0x18,0x0A,0x2A,0x2A,0x2A,0xAF,0x6A,0x2A,0x0A,0x0A,0x18,0x01,0x01,0x01,0x09,0x09,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"孛\",3789*/},{\n\n0x10,0xDA,0x56,0x5A,0x52,0x5F,0x52,0x5A,0x56,0xDA,0x10,0x00,0x0F,0x08,0x0F,0x0D,\n0x0D,0x0D,0x0F,0x08,0x0F,0x00,/*\"嗇\",3790*/},{\n\n0xC8,0x7F,0xC8,0x00,0xFF,0x49,0x4F,0x00,0xC9,0x49,0xCF,0x0F,0x04,0x0F,0x00,0x0F,\n0x02,0x02,0x08,0x05,0x02,0x0D,/*\"嘏\",3791*/},{\n\n0x00,0xFE,0x02,0x02,0x02,0xC2,0x3E,0xC2,0x02,0x02,0x02,0x08,0x07,0x08,0x04,0x03,\n0x00,0x00,0x00,0x03,0x04,0x08,/*\"仄\",3792*/},{\n\n0x00,0xFF,0x01,0xF5,0x55,0x55,0xFF,0x55,0x55,0xF5,0x01,0x08,0x07,0x00,0x05,0x05,\n0x05,0x0F,0x05,0x05,0x05,0x04,/*\"厙\",3793*/},{\n\n0x00,0xFF,0x11,0xD5,0x5F,0x55,0x55,0x55,0x5F,0xD5,0x11,0x08,0x07,0x00,0x0F,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"厝\",3794*/},{\n\n0x00,0xFF,0x01,0xF7,0x55,0x77,0xE9,0x59,0x4F,0xD9,0x2D,0x08,0x07,0x00,0x07,0x05,\n0x05,0x0F,0x05,0x05,0x07,0x00,/*\"厴\",3795*/},{\n\n0x00,0xFF,0xEB,0x8D,0xF9,0x8D,0xEB,0x11,0xCF,0x09,0x39,0x08,0x07,0x08,0x04,0x03,\n0x00,0x08,0x06,0x01,0x06,0x08,/*\"厥\",3796*/},{\n\n0x00,0xFE,0x0A,0xFE,0xAA,0xFE,0x0B,0xFA,0x4A,0xC6,0x42,0x08,0x07,0x0A,0x07,0x02,\n0x07,0x0A,0x07,0x00,0x0F,0x00,/*\"廝\",3797*/},{\n\n0x00,0xFF,0x21,0xAF,0xA5,0xB5,0xEF,0xA1,0xB5,0xAF,0x35,0x08,0x07,0x00,0x0F,0x08,\n0x0F,0x0A,0x0F,0x08,0x0F,0x00,/*\"靨\",3798*/},{\n\n0x00,0xFF,0x09,0xFD,0x83,0xDD,0x97,0xDD,0x95,0xDD,0x71,0x08,0x07,0x00,0x07,0x0C,\n0x04,0x05,0x06,0x0C,0x07,0x00,/*\"贗\",3799*/},{\n\n0x00,0xFF,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x0F,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x08,/*\"匚\",3800*/},{\n\n0x00,0xFF,0x01,0x01,0xF9,0x09,0x09,0x09,0xF9,0x01,0x01,0x00,0x0F,0x08,0x08,0x09,\n0x09,0x09,0x09,0x09,0x08,0x08,/*\"叵\",3801*/},{\n\n0xFF,0x55,0xFF,0x55,0xF5,0x09,0xFF,0x09,0xF9,0x01,0x81,0x0F,0x09,0x0F,0x09,0x0D,\n0x0A,0x09,0x08,0x09,0x0A,0x0B,/*\"匭\",3802*/},{\n\n0x00,0xFF,0x11,0xF1,0x5D,0x55,0x5F,0x55,0x5D,0xF1,0x11,0x00,0x0F,0x08,0x0D,0x0B,\n0x09,0x09,0x09,0x0B,0x0D,0x08,/*\"匱\",3803*/},{\n\n0xFF,0x01,0xFD,0xD5,0x55,0xD7,0x55,0xD5,0x55,0xDD,0x01,0x0F,0x09,0x08,0x0F,0x09,\n0x0B,0x09,0x0B,0x0D,0x0F,0x08,/*\"匾\",3804*/},{\n\n0xFE,0x02,0xF2,0x1E,0xF2,0x20,0xEA,0xAA,0xBF,0xAA,0xEA,0x0F,0x08,0x09,0x0F,0x09,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"賾\",3805*/},{\n\n0x20,0x24,0x24,0xBF,0x24,0x24,0x00,0xFF,0x10,0x20,0xC0,0x08,0x09,0x09,0x07,0x05,\n0x05,0x00,0x0F,0x00,0x00,0x00,/*\"卦\",3806*/},{\n\n0x00,0xF8,0x28,0x28,0x28,0x2F,0x2A,0xEA,0x0A,0x0A,0xFA,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x04,0x04,0x0F,/*\"卣\",3807*/},{\n\n0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,\n0x00,0x01,0x08,0x08,0x0F,0x00,/*\"刂\",3808*/},{\n\n0x08,0x10,0x20,0xC0,0x30,0x0E,0x00,0xFC,0x00,0x00,0xFF,0x08,0x04,0x03,0x00,0x01,\n0x06,0x00,0x01,0x08,0x08,0x0F,/*\"刈\",3809*/},{\n\n0x08,0xC7,0x3C,0x84,0x7C,0x04,0xFC,0x00,0xFC,0x00,0xFF,0x09,0x04,0x02,0x01,0x08,\n0x08,0x07,0x00,0x01,0x08,0x0F,/*\"刎\",3810*/},{\n\n0x92,0xAA,0x92,0xAA,0x92,0xAA,0x00,0xFC,0x00,0x00,0xFF,0x08,0x08,0x08,0x07,0x04,\n0x04,0x00,0x01,0x08,0x08,0x0F,/*\"剄\",3811*/},{\n\n0x52,0xCA,0x56,0x53,0x56,0x4A,0x52,0x00,0xFC,0x00,0xFF,0x00,0x01,0x01,0x09,0x09,\n0x07,0x00,0x00,0x01,0x08,0x0F,/*\"刳\",3812*/},{\n\n0xE8,0xAE,0xA8,0xAF,0xFA,0x2A,0xB0,0x00,0xFC,0x00,0xFF,0x07,0x0A,0x0F,0x04,0x03,\n0x05,0x0E,0x00,0x01,0x08,0x0F,/*\"劌\",3813*/},{\n\n0xD6,0x54,0x54,0x57,0x54,0x54,0xD6,0x00,0xFC,0x00,0xFF,0x09,0x0B,0x0D,0x09,0x05,\n0x07,0x05,0x00,0x01,0x08,0x0F,/*\"剴\",3814*/},{\n\n0xF4,0x94,0x94,0xFF,0x94,0x94,0xF4,0x00,0xFC,0x00,0xFF,0x04,0x02,0x01,0x0F,0x01,\n0x02,0x04,0x00,0x01,0x08,0x0F,/*\"剌\",3815*/},{\n\n0x10,0xDA,0x56,0x53,0xD2,0x16,0xFA,0x10,0xFC,0x00,0xFF,0x00,0x07,0x02,0x02,0x0B,\n0x08,0x0F,0x00,0x01,0x08,0x0F,/*\"剞\",3816*/},{\n\n0x08,0xA6,0x10,0xCF,0x14,0xA2,0x00,0xFC,0x00,0x00,0xFF,0x0A,0x09,0x04,0x03,0x05,\n0x08,0x00,0x01,0x08,0x08,0x0F,/*\"剡\",3817*/},{\n\n0xE6,0x1A,0xF2,0x03,0xF2,0x92,0xF6,0x00,0xFC,0x00,0xFF,0x08,0x07,0x00,0x00,0x0F,\n0x04,0x02,0x00,0x01,0x08,0x0F,/*\"剜\",3818*/},{\n\n0xFA,0xAF,0xFA,0x02,0xFA,0xAF,0xFA,0x00,0xFC,0x00,0xFF,0x07,0x08,0x0F,0x08,0x07,\n0x08,0x0F,0x00,0x01,0x08,0x0F,/*\"蒯\",3819*/},{\n\n0x1D,0x55,0x5F,0x55,0x5F,0x55,0x1D,0x00,0xFC,0x00,0xFF,0x09,0x05,0x09,0x0F,0x01,\n0x05,0x09,0x00,0x01,0x08,0x0F,/*\"剽\",3820*/},{\n\n0x00,0xFE,0x2A,0xF2,0x2A,0xA2,0xDE,0x32,0xFC,0x00,0xFF,0x08,0x07,0x09,0x07,0x09,\n0x05,0x03,0x0C,0x01,0x08,0x0F,/*\"劂\",3821*/},{\n\n0x08,0xFC,0x57,0x54,0xFD,0x56,0x54,0x00,0xFC,0x00,0xFF,0x0C,0x03,0x0D,0x01,0x0D,\n0x01,0x0D,0x00,0x01,0x08,0x0F,/*\"劁\",3822*/},{\n\n0x12,0xFA,0x57,0x52,0xFA,0x57,0x52,0x00,0xFC,0x00,0xFF,0x08,0x09,0x0B,0x05,0x05,\n0x0B,0x09,0x00,0x01,0x08,0x0F,/*\"劐\",3823*/},{\n\n0x00,0xE0,0xBE,0xEB,0xAA,0xBE,0xE0,0x00,0xFC,0x00,0xFF,0x02,0x0B,0x06,0x03,0x02,\n0x0E,0x03,0x02,0x01,0x08,0x0F,/*\"劓\",3824*/},{\n\n0x00,0xFF,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0xFF,0x00,0x0F,0x00,0x00,0x00,\n0x00,0x00,0x00,0x08,0x08,0x0F,/*\"冂\",3825*/},{\n\n0xFF,0x11,0x51,0xD5,0x59,0x71,0x59,0x55,0x51,0x11,0xFF,0x0F,0x00,0x00,0x03,0x02,\n0x02,0x02,0x02,0x08,0x08,0x0F,/*\"罔\",3826*/},{\n\n0x20,0x10,0xFC,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"亻\",3827*/},{\n\n0x20,0x10,0xFC,0x03,0x00,0x02,0x02,0x02,0xFE,0x02,0x02,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"仃\",3828*/},{\n\n0x20,0x10,0xFC,0x03,0x00,0xFE,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"仉\",3829*/},{\n\n0x20,0x10,0xFC,0x03,0x08,0x08,0xFF,0x08,0x08,0x08,0xF8,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x08,0x08,0x08,0x07,/*\"仂\",3830*/},{\n\n0x10,0xFC,0x03,0x00,0x42,0x42,0x42,0x42,0x42,0x42,0x00,0x00,0x0F,0x00,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x08,/*\"仨\",3831*/},{\n\n0x20,0x10,0xFC,0x13,0x28,0x27,0x24,0xA4,0xA4,0x64,0x04,0x00,0x00,0x0F,0x00,0x06,\n0x09,0x09,0x08,0x08,0x08,0x0E,/*\"仡\",3832*/},{\n\n0x20,0x10,0xFC,0x03,0x20,0x10,0x0C,0x83,0x60,0x18,0x00,0x00,0x00,0x0F,0x00,0x04,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"仫\",3833*/},{\n\n0x20,0x10,0xFC,0x03,0x80,0x72,0x02,0xFE,0x02,0x02,0xFE,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x08,0x08,0x07,/*\"仞\",3834*/},{\n\n0x10,0xFC,0x03,0xFE,0x82,0xBA,0xAA,0x2A,0xAA,0xBA,0x82,0x00,0x0F,0x00,0x0F,0x0B,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"傴\",3835*/},{\n\n0x10,0xFC,0x03,0x00,0xFF,0x10,0x10,0xFF,0x20,0x10,0x0C,0x00,0x0F,0x00,0x00,0x0F,\n0x04,0x02,0x07,0x08,0x08,0x0E,/*\"仳\",3836*/},{\n\n0x20,0x10,0xFC,0x03,0x00,0x32,0x2A,0xA2,0x62,0xFE,0x22,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"伢\",3837*/},{\n\n0x10,0xFC,0x03,0x00,0x82,0x7E,0x92,0x12,0xF2,0x02,0x00,0x00,0x0F,0x00,0x00,0x0F,\n0x08,0x04,0x00,0x07,0x08,0x0E,/*\"佤\",3838*/},{\n\n0x20,0x10,0xFC,0x03,0x88,0x87,0x84,0xFC,0x84,0x84,0x80,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"仵\",3839*/},{\n\n0x20,0x10,0xFC,0x43,0xC0,0x7F,0x55,0xD5,0x55,0x41,0x40,0x00,0x00,0x0F,0x00,0x0F,\n0x08,0x04,0x01,0x02,0x05,0x08,/*\"倀\",3840*/},{\n\n0x10,0xFC,0x03,0x08,0xFC,0xAA,0xAD,0xA9,0xAA,0xFC,0x08,0x00,0x0F,0x04,0x03,0x0E,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"傖\",3841*/},{\n\n0x20,0x10,0xFC,0x03,0x04,0xE4,0x25,0x26,0xE4,0x04,0x04,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"伉\",3842*/},{\n\n0x10,0xFC,0x03,0x2C,0x24,0x24,0x25,0xE6,0x24,0x24,0x2C,0x00,0x0F,0x00,0x00,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"佇\",3843*/},{\n\n0x10,0xFC,0x03,0x48,0x4A,0xCA,0x7A,0x4A,0xCA,0x4A,0x48,0x00,0x0F,0x00,0x08,0x09,\n0x05,0x02,0x02,0x05,0x08,0x00,/*\"佞\",3844*/},{\n\n0x20,0x10,0xFC,0x23,0x20,0x20,0xFF,0xA4,0x24,0x24,0x20,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x0F,0x00,0x01,0x02,0x00,/*\"佧\",3845*/},{\n\n0x10,0xFC,0x03,0xF8,0x20,0x10,0xEF,0x08,0x88,0x78,0x08,0x00,0x0F,0x00,0x03,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"攸\",3846*/},{\n\n0x20,0x10,0xFC,0x03,0x50,0x4C,0x48,0xFF,0x48,0x48,0x40,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"佚\",3847*/},{\n\n0x20,0x10,0xFC,0x13,0xEC,0x27,0x24,0x24,0xE4,0x04,0xFC,0x00,0x00,0x0F,0x00,0x03,\n0x01,0x01,0x01,0x09,0x08,0x07,/*\"佝\",3848*/},{\n\n0x20,0x10,0xFC,0x03,0x48,0x44,0xAB,0x92,0x2A,0x46,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x02,0x02,0x04,0x05,0x08,0x00,/*\"佟\",3849*/},{\n\n0x20,0x10,0xFC,0x03,0x0C,0xE4,0x05,0x86,0x44,0x24,0x0C,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x09,0x08,0x08,0x08,0x0E,/*\"佗\",3850*/},{\n\n0x10,0xFC,0x03,0x00,0xFE,0x12,0xD2,0x12,0x92,0x52,0x1E,0x00,0x0F,0x08,0x04,0x03,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"伲\",3851*/},{\n\n0x10,0xFC,0x03,0x08,0xFF,0x08,0xF8,0x00,0xFC,0x04,0xFC,0x00,0x0F,0x08,0x04,0x03,\n0x08,0x0F,0x00,0x0F,0x04,0x0F,/*\"伽\",3852*/},{\n\n0x10,0xFC,0x03,0xA4,0xA4,0xA4,0xBF,0xA4,0xA4,0xA4,0x04,0x00,0x0F,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"佶\",3853*/},{\n\n0x20,0x10,0xFC,0x03,0x02,0xFE,0x52,0x52,0x52,0xFE,0x02,0x00,0x00,0x0F,0x00,0x02,\n0x03,0x02,0x02,0x02,0x0F,0x01,/*\"佴\",3854*/},{\n\n0x10,0xFC,0x43,0x24,0xF4,0x5C,0x57,0x54,0x54,0xF4,0x04,0x00,0x0F,0x00,0x00,0x0F,\n0x01,0x01,0x01,0x09,0x0F,0x00,/*\"侑\",3855*/},{\n\n0x20,0x10,0xFC,0x03,0x52,0xCA,0x56,0x53,0x56,0x4A,0x52,0x00,0x00,0x0F,0x00,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"侉\",3856*/},{\n\n0x10,0xFC,0x03,0x00,0xDE,0x12,0xD2,0x12,0xD2,0x1E,0x00,0x00,0x0F,0x08,0x04,0x03,\n0x00,0x0F,0x00,0x07,0x08,0x0C,/*\"侃\",3857*/},{\n\n0x20,0x10,0xFC,0x03,0x28,0x26,0xA4,0xFF,0xA4,0x24,0x20,0x00,0x00,0x0F,0x00,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"侏\",3858*/},{\n\n0x10,0xFC,0x03,0x08,0xF4,0x53,0x50,0x50,0x53,0xF4,0x08,0x00,0x0F,0x00,0x00,0x0F,\n0x01,0x01,0x01,0x09,0x0F,0x00,/*\"佾\",3859*/},{\n\n0x10,0xFC,0x03,0x88,0x50,0xFF,0x00,0x00,0xFF,0x50,0x88,0x00,0x0F,0x00,0x08,0x06,\n0x01,0x00,0x00,0x07,0x08,0x0E,/*\"佻\",3860*/},{\n\n0x10,0xFC,0x03,0x28,0xDA,0x7A,0x06,0x7B,0x06,0x7A,0xD6,0x00,0x0F,0x00,0x08,0x07,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"儕\",3861*/},{\n\n0x10,0xFC,0x03,0x44,0x24,0xD4,0x05,0x06,0xD4,0x24,0x44,0x00,0x0F,0x00,0x08,0x08,\n0x05,0x02,0x02,0x05,0x08,0x08,/*\"佼\",3862*/},{\n\n0x10,0xFC,0x03,0x00,0xBE,0xAA,0xBF,0xAA,0xBF,0xAA,0xBE,0x00,0x0F,0x00,0x08,0x07,\n0x02,0x0E,0x0A,0x06,0x0A,0x0A,/*\"儂\",3863*/},{\n\n0x20,0x10,0xFC,0x03,0x80,0x6C,0x4A,0xF9,0x48,0x4C,0x18,0x00,0x00,0x0F,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"侔\",3864*/},{\n\n0x10,0xFC,0x03,0xAA,0xAA,0xAA,0xEF,0xAA,0xAA,0xAA,0x62,0x00,0x0F,0x00,0x0E,0x0A,\n0x0E,0x02,0x06,0x0A,0x0F,0x02,/*\"儔\",3865*/},{\n\n0x10,0xFC,0x03,0xF0,0x57,0xD5,0x77,0xD0,0x97,0x75,0xD7,0x00,0x0F,0x08,0x07,0x04,\n0x07,0x05,0x0F,0x0A,0x04,0x0B,/*\"儼\",3866*/},{\n\n0x10,0xFC,0x03,0x00,0xED,0xA5,0xED,0xB0,0xED,0xA5,0xAD,0x00,0x0F,0x00,0x08,0x07,\n0x02,0x0F,0x0A,0x03,0x0E,0x0B,/*\"儷\",3867*/},{\n\n0x10,0xFC,0x03,0x28,0x48,0x88,0xFF,0x68,0x89,0x4A,0x28,0x00,0x0F,0x00,0x02,0x01,\n0x08,0x0F,0x00,0x01,0x02,0x04,/*\"俅\",3868*/},{\n\n0x10,0xFC,0x03,0x00,0x7F,0x49,0x49,0xFF,0x49,0x49,0x7F,0x00,0x0F,0x00,0x08,0x09,\n0x09,0x09,0x0F,0x09,0x09,0x09,/*\"俚\",3869*/},{\n\n0x20,0x10,0xFC,0x03,0x3C,0x20,0xEF,0x29,0x29,0xEF,0x00,0x00,0x00,0x0F,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"俁\",3870*/},{\n\n0x10,0xFC,0x03,0xBE,0xAA,0xAA,0xBF,0xAA,0xAA,0xBE,0x80,0x00,0x0F,0x00,0x00,0x03,\n0x02,0x02,0x0A,0x0A,0x06,0x00,/*\"俜\",3871*/},{\n\n0x20,0x10,0xFC,0x03,0xF0,0x51,0x55,0xF9,0x55,0x53,0xF0,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"俑\",3872*/},{\n\n0x20,0x10,0xFC,0x03,0x48,0x3C,0x2A,0xE9,0x28,0x2C,0x18,0x00,0x00,0x0F,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"俟\",3873*/},{\n\n0x10,0xFC,0x23,0xAA,0x6A,0x3A,0xAF,0x2A,0x6A,0xAA,0x22,0x00,0x0F,0x01,0x04,0x05,\n0x05,0x0F,0x05,0x05,0x04,0x01,/*\"俸\",3874*/},{\n\n0x10,0xFC,0x03,0x22,0xEA,0xAA,0xBF,0xAA,0xAA,0xEA,0x22,0x00,0x0F,0x00,0x00,0x0F,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"倩\",3875*/},{\n\n0x10,0xFC,0x03,0x24,0x24,0xEF,0xB4,0xA4,0xAF,0xA4,0x24,0x00,0x0F,0x00,0x02,0x01,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"偌\",3876*/},{\n\n0x10,0xFC,0x03,0x24,0x24,0xFF,0x00,0x00,0xFF,0x24,0x24,0x00,0x0F,0x00,0x01,0x01,\n0x0F,0x00,0x00,0x0F,0x01,0x01,/*\"俳\",3877*/},{\n\n0x10,0xFC,0x03,0xF8,0xA8,0xA8,0xAF,0xAA,0xAA,0xFA,0x02,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x0F,0x02,0x02,0x02,0x02,/*\"倬\",3878*/},{\n\n0x10,0xFC,0x03,0xF8,0x10,0x94,0x8B,0xEA,0x8A,0xD6,0x90,0x00,0x0F,0x00,0x03,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"倏\",3879*/},{\n\n0x10,0xFC,0x03,0xBE,0xAA,0xAA,0xFE,0xAA,0xAA,0xBE,0x80,0x00,0x0F,0x00,0x04,0x02,\n0x01,0x0F,0x01,0x02,0x04,0x04,/*\"倮\",3880*/},{\n\n0x10,0xFC,0x03,0xA8,0x9A,0x8A,0xFE,0x89,0x99,0xA8,0x88,0x00,0x0F,0x00,0x08,0x0A,\n0x0B,0x04,0x04,0x0B,0x08,0x00,/*\"倭\",3881*/},{\n\n0x20,0x10,0xFC,0x03,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x00,0x00,0x00,0x0F,0x02,0x03,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"俾\",3882*/},{\n\n0x10,0xFC,0x03,0x00,0xFF,0x21,0xA9,0xBD,0xA9,0x21,0xFF,0x00,0x0F,0x00,0x08,0x07,\n0x00,0x03,0x02,0x0B,0x08,0x0F,/*\"倜\",3883*/},{\n\n0x10,0xFC,0x03,0x0C,0xF4,0x54,0x55,0x56,0x54,0x74,0x0C,0x00,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"倌\",3884*/},{\n\n0x20,0x10,0xFC,0x03,0x4C,0xA4,0x95,0x86,0x94,0xA4,0x4C,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"倥\",3885*/},{\n\n0x10,0xFC,0x03,0x00,0xFE,0xAA,0xAA,0xFA,0xAA,0xAA,0xAE,0x00,0x0F,0x08,0x06,0x01,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"倨\",3886*/},{\n\n0x10,0xFC,0x0B,0xEA,0xBE,0xAA,0xAF,0xAA,0xBE,0xEA,0x08,0x00,0x0F,0x00,0x0B,0x06,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"僨\",3887*/},{\n\n0x10,0xFC,0x03,0x00,0xFF,0x81,0xBF,0xEB,0xAB,0xBF,0x81,0x00,0x0F,0x00,0x00,0x0F,\n0x08,0x0D,0x0A,0x0A,0x0D,0x08,/*\"偃\",3888*/},{\n\n0x10,0xFC,0x03,0x00,0xDF,0x52,0x4A,0x60,0x4F,0x52,0xD9,0x00,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"偕\",3889*/},{\n\n0x10,0xFC,0x03,0x80,0x5F,0x75,0x55,0xD5,0x55,0x5F,0xC0,0x00,0x0F,0x00,0x00,0x06,\n0x04,0x05,0x04,0x01,0x08,0x0F,/*\"偈\",3890*/},{\n\n0x10,0xFC,0x03,0x40,0xDF,0x55,0x55,0xDF,0x55,0x55,0x5F,0x00,0x0F,0x00,0x00,0x0F,\n0x08,0x04,0x01,0x02,0x06,0x09,/*\"偎\",3891*/},{\n\n0x10,0xFC,0x03,0xFE,0x92,0xDB,0xAE,0xAA,0xDA,0x82,0xFE,0x00,0x0F,0x08,0x06,0x00,\n0x06,0x09,0x0A,0x0C,0x02,0x0C,/*\"傯\",3892*/},{\n\n0x10,0xFC,0x0B,0x3E,0x2A,0xAA,0x7F,0x2A,0x2A,0x3E,0x08,0x00,0x0F,0x01,0x09,0x0B,\n0x05,0x05,0x05,0x0B,0x09,0x01,/*\"僂\",3893*/},{\n\n0x10,0xFC,0x03,0xE6,0x7B,0xAA,0xEB,0xAA,0x7B,0xE6,0x00,0x00,0x0F,0x04,0x0D,0x05,\n0x0D,0x07,0x0D,0x05,0x0D,0x04,/*\"儻\",3894*/},{\n\n0x10,0xFC,0x03,0x56,0xEA,0xAA,0xBB,0xAA,0xBA,0xEA,0x06,0x00,0x0F,0x00,0x00,0x0B,\n0x06,0x02,0x02,0x06,0x0B,0x00,/*\"儐\",3895*/},{\n\n0x10,0xFC,0x03,0xE2,0xAF,0xFA,0xAF,0xFC,0x27,0xFC,0x25,0x00,0x0F,0x00,0x0A,0x0A,\n0x07,0x0A,0x0F,0x09,0x0F,0x09,/*\"儺\",3896*/},{\n\n0x10,0xFC,0x03,0x48,0xB7,0x9A,0xAE,0xA0,0xA7,0x9A,0xA6,0x00,0x0F,0x00,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"傺\",3897*/},{\n\n0x10,0xFC,0x03,0xEA,0xAA,0xAA,0xAF,0xAA,0xAA,0xEA,0x02,0x00,0x0F,0x02,0x0E,0x0B,\n0x0A,0x0A,0x0A,0x0B,0x0E,0x02,/*\"僖\",3898*/},{\n\n0x10,0xFC,0x23,0xDA,0x57,0xF2,0x27,0xFA,0x0F,0xF8,0x08,0x00,0x0F,0x00,0x0B,0x0A,\n0x07,0x08,0x04,0x03,0x04,0x08,/*\"儆\",3899*/},{\n\n0x10,0xFC,0x03,0x2C,0xD9,0x4F,0x79,0x6C,0x59,0xFF,0x29,0x00,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"僭\",3900*/},{\n\n0x10,0xFC,0x23,0x10,0xFC,0x57,0x54,0xFD,0x56,0x54,0x04,0x00,0x0F,0x00,0x0C,0x03,\n0x05,0x09,0x05,0x09,0x05,0x09,/*\"僬\",3901*/},{\n\n0x10,0xFC,0x03,0x7A,0xCB,0x7A,0x10,0xFF,0xD0,0x12,0x14,0x00,0x0F,0x02,0x09,0x0F,\n0x09,0x06,0x01,0x07,0x08,0x0E,/*\"僦\",3902*/},{\n\n0x10,0xFC,0x0B,0xFA,0xAE,0xAA,0xFB,0xAA,0xAE,0xFA,0x08,0x00,0x0F,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"僮\",3903*/},{\n\n0x10,0xFC,0x03,0x10,0xD7,0x55,0x57,0x55,0x57,0x55,0xD7,0x00,0x0F,0x00,0x08,0x05,\n0x0F,0x09,0x01,0x03,0x05,0x0B,/*\"儇\",3904*/},{\n\n0x10,0xFC,0x0B,0xFC,0x16,0xAD,0xA5,0xB5,0xA7,0xAC,0x14,0x00,0x0F,0x08,0x07,0x00,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"儋\",3905*/},{\n\n0x10,0x50,0x48,0x44,0x42,0xC1,0x42,0x44,0x48,0x50,0x10,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"仝\",3906*/},{\n\n0x10,0x50,0x48,0xC4,0x02,0xF1,0xC2,0x04,0x88,0x50,0x10,0x04,0x02,0x01,0x00,0x08,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"氽\",3907*/},{\n\n0x08,0x88,0x84,0x94,0x92,0x91,0x92,0x94,0x84,0x88,0x08,0x08,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x08,/*\"佘\",3908*/},{\n\n0x10,0xD0,0x48,0x54,0xD2,0x11,0xD2,0x54,0x48,0xD0,0x10,0x08,0x05,0x03,0x05,0x09,\n0x00,0x09,0x05,0x03,0x05,0x08,/*\"僉\",3909*/},{\n\n0x20,0x18,0xC7,0x08,0x10,0xFE,0x92,0x92,0x92,0xFE,0x00,0x04,0x03,0x00,0x01,0x0A,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"俎\",3910*/},{\n\n0x74,0x54,0x72,0x06,0x75,0x55,0x75,0x06,0x72,0x54,0x74,0x0F,0x05,0x05,0x0F,0x05,\n0x05,0x05,0x0F,0x05,0x0D,0x0F,/*\"龠\",3911*/},{\n\n0x10,0x50,0x48,0xC9,0x05,0xF2,0xC4,0x08,0x88,0x50,0x10,0x04,0x02,0x01,0x00,0x08,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"汆\",3912*/},{\n\n0xA9,0xC5,0xF2,0xC4,0xA8,0x4A,0xF5,0xAF,0xEA,0xB5,0xAF,0x04,0x02,0x0F,0x02,0x04,\n0x00,0x0F,0x0A,0x0F,0x0A,0x0A,/*\"糴\",3913*/},{\n\n0x10,0x08,0xD4,0xB3,0x90,0x90,0x90,0x93,0x94,0x08,0x10,0x00,0x00,0x00,0x00,0x00,\n0x00,0x08,0x08,0x07,0x00,0x00,/*\"兮\",3914*/},{\n\n0x00,0x9F,0xA5,0xE5,0xB7,0x80,0x9F,0xE5,0xA5,0xB7,0x00,0x02,0x0A,0x06,0x03,0x02,\n0x02,0x02,0x03,0x06,0x0A,0x02,/*\"巽\",3915*/},{\n\n0x30,0x5F,0xD5,0x70,0x55,0xDA,0x55,0x70,0xD5,0x5F,0x30,0x00,0x00,0x07,0x0D,0x05,\n0x07,0x05,0x0D,0x07,0x00,0x00,/*\"黌\",3916*/},{\n\n0xF5,0x5E,0xF5,0x00,0xF4,0x94,0xF4,0x04,0xFF,0x84,0x65,0x0F,0x05,0x0F,0x00,0x04,\n0x04,0x0A,0x04,0x03,0x05,0x0E,/*\"馘\",3917*/},{\n\n0xF7,0x55,0xF7,0x55,0xFF,0xAA,0xAA,0xFA,0xAA,0xFA,0xAE,0x05,0x05,0x0F,0x05,0x07,\n0x00,0x0F,0x04,0x03,0x04,0x0A,/*\"囅\",3918*/},{\n\n0xFA,0x82,0x7E,0x4B,0xFA,0x56,0xFA,0x03,0x7A,0xAA,0xBA,0x0A,0x09,0x0A,0x0B,0x05,\n0x05,0x05,0x0B,0x08,0x09,0x0A,/*\"夔\",3919*/},{\n\n0x20,0x10,0x0C,0x07,0x04,0x04,0x04,0x04,0x04,0x04,0xFC,0x00,0x00,0x00,0x00,0x00,\n0x00,0x00,0x08,0x08,0x08,0x07,/*\"勹\",3920*/},{\n\n0x0C,0xEB,0xAA,0xAA,0xFE,0xAA,0xAA,0xEE,0x0A,0x02,0xFE,0x00,0x0F,0x02,0x02,0x07,\n0x02,0x0A,0x0F,0x00,0x08,0x0F,/*\"匍\",3921*/},{\n\n0x04,0xAB,0xAA,0xAA,0xAE,0xAA,0xAA,0xAA,0x0A,0x02,0xFE,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0E,0x00,0x08,0x0F,/*\"訇\",3922*/},{\n\n0x04,0x8B,0xEA,0xAA,0xAA,0xAA,0xEA,0x8A,0x02,0x02,0xFE,0x00,0x0F,0x0A,0x0A,0x0F,\n0x0A,0x0A,0x0F,0x00,0x08,0x0F,/*\"匐\",3923*/},{\n\n0x80,0x3E,0xAA,0x2A,0xAB,0x2A,0xAA,0x2A,0xBE,0xA0,0x60,0x08,0x08,0x06,0x02,0x02,\n0x02,0x02,0x06,0x08,0x08,0x0C,/*\"鳧\",3924*/},{\n\n0x00,0xFF,0x41,0x25,0x5D,0x95,0x75,0x01,0xFF,0x00,0x00,0x08,0x07,0x00,0x04,0x02,\n0x01,0x00,0x00,0x03,0x04,0x0F,/*\"夙\",3925*/},{\n\n0x00,0x7F,0x41,0xC1,0x4F,0x48,0x4F,0xC1,0x41,0x7F,0x00,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"兕\",3926*/},{\n\n0x04,0x04,0x04,0x04,0x05,0x06,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"亠\",3927*/},{\n\n0x24,0x14,0xEC,0x24,0x25,0x26,0x24,0x24,0xEC,0x14,0x24,0x08,0x08,0x05,0x03,0x01,\n0x01,0x01,0x07,0x09,0x08,0x0C,/*\"兗\",3928*/},{\n\n0x62,0x22,0x3A,0x2A,0x2A,0xAB,0xAA,0xAA,0x3A,0x22,0x62,0x04,0x05,0x05,0x05,0x07,\n0x0A,0x0A,0x0A,0x0A,0x08,0x0C,/*\"亳\",3929*/},{\n\n0x12,0x0A,0xF6,0x92,0x92,0x93,0x92,0x92,0xF6,0x0A,0x12,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"袞\",3930*/},{\n\n0xA2,0xAA,0xAA,0x6A,0x3A,0xAB,0xEA,0x3A,0x2A,0x22,0x62,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"袤\",3931*/},{\n\n0xA2,0x6A,0xBE,0x6A,0xA2,0x83,0x2A,0xFE,0x4A,0xFA,0x82,0x04,0x04,0x03,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x09,/*\"褻\",3932*/},{\n\n0x56,0x9D,0xD4,0x80,0xBA,0xEB,0xBA,0x80,0xD6,0x9D,0x54,0x00,0x0F,0x00,0x02,0x09,\n0x04,0x09,0x02,0x08,0x0F,0x00,/*\"臠\",3933*/},{\n\n0x02,0xFA,0xAA,0xAA,0xA6,0x83,0xAA,0xAA,0xAA,0xFA,0x02,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"裒\",3934*/},{\n\n0x02,0x82,0xBE,0xA2,0xBA,0xAB,0xBA,0xA2,0x7E,0x42,0x02,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"稟\",3935*/},{\n\n0xE2,0xAE,0xEA,0x4A,0xCA,0x7B,0xCA,0x0A,0xEA,0x2A,0xE2,0x07,0x0A,0x0F,0x00,0x0B,\n0x04,0x0B,0x08,0x07,0x01,0x0F,/*\"嬴\",3936*/},{\n\n0xE2,0xAE,0xEA,0xCA,0x4A,0xEB,0x4A,0xCA,0xEA,0x2A,0xE2,0x07,0x0A,0x0F,0x05,0x05,\n0x07,0x05,0x0D,0x07,0x01,0x0F,/*\"蠃\",3937*/},{\n\n0xE2,0xAE,0xEA,0x0A,0x5A,0xEB,0x5A,0x0A,0xEA,0x2A,0xE2,0x07,0x0A,0x0F,0x00,0x05,\n0x0F,0x05,0x08,0x07,0x01,0x0F,/*\"羸\",3938*/},{\n\n0x04,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x02,0x01,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"冫\",3939*/},{\n\n0x04,0x08,0x02,0xC2,0x3E,0x12,0x12,0x12,0x12,0xF2,0x02,0x02,0x01,0x08,0x09,0x09,\n0x09,0x09,0x09,0x0F,0x08,0x08,/*\"冱\",3940*/},{\n\n0x04,0x08,0x82,0x62,0x9E,0x12,0xF2,0x00,0xFC,0x00,0xFF,0x04,0x02,0x00,0x08,0x04,\n0x03,0x00,0x00,0x09,0x08,0x0F,/*\"冽\",3941*/},{\n\n0x04,0x08,0x40,0x50,0xCE,0x48,0x7F,0xC8,0x48,0x48,0x40,0x02,0x01,0x08,0x04,0x03,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"冼\",3942*/},{\n\n0x04,0x08,0x80,0x48,0xFF,0x28,0x58,0x87,0x60,0x07,0x18,0x04,0x02,0x00,0x00,0x0F,\n0x00,0x06,0x05,0x04,0x05,0x0E,/*\"凇\",3943*/},{\n\n0x0E,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x0E,0x00,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"冖\",3944*/},{\n\n0x23,0x25,0xD5,0x95,0x4D,0xB5,0xE5,0x45,0xA5,0x15,0x03,0x05,0x05,0x02,0x02,0x09,\n0x08,0x07,0x00,0x01,0x02,0x04,/*\"冢\",3945*/},{\n\n0x03,0x01,0x7D,0x55,0x55,0xD5,0x55,0x55,0x7D,0x01,0x03,0x01,0x09,0x05,0x01,0x01,\n0x01,0x01,0x01,0x05,0x09,0x01,/*\"冥\",3946*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"訁\",3947*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x42,0x42,0xFE,0x42,0x42,0x40,0x0F,0x05,0x05,0x0F,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"訐\",3948*/},{\n\n0x54,0x55,0x56,0x54,0x00,0x02,0x02,0xFE,0x02,0x02,0x00,0x0F,0x05,0x05,0x07,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"訌\",3949*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0xF8,0x00,0xFF,0x00,0xF8,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x07,0x04,0x07,0x04,0x0F,/*\"訕\",3950*/},{\n\n0x55,0x56,0x54,0x00,0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x0F,0x05,0x0F,0x00,0x0F,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"謳\",3951*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0xFE,0x12,0x12,0x12,0xF2,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x0F,0x09,0x09,0x09,0x09,/*\"詎\",3952*/},{\n\n0x55,0x56,0x54,0x00,0xFC,0x84,0x44,0x3F,0x44,0x84,0xFC,0x0F,0x05,0x0F,0x00,0x0F,\n0x00,0x00,0x00,0x00,0x08,0x0F,/*\"訥\",3953*/},{\n\n0x04,0x54,0x55,0x56,0x54,0x04,0xC8,0x48,0x7F,0x48,0xC8,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"詁\",3954*/},{\n\n0x54,0x55,0x56,0x54,0x02,0xF2,0x12,0xF2,0x02,0xFE,0x02,0x0F,0x05,0x05,0x0F,0x00,\n0x03,0x01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AA,0xAF,0xFA,0x02,0x0F,0x05,0x05,0x07,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"謨\",3993*/},{\n\n0x55,0x56,0x54,0x00,0xE6,0x7B,0xAA,0xEB,0xAA,0x7B,0xE6,0x0F,0x05,0x0F,0x04,0x0D,\n0x05,0x0D,0x07,0x0D,0x05,0x0D,/*\"讜\",3994*/},{\n\n0x55,0x56,0x54,0x00,0x5F,0x35,0xD5,0x9F,0x95,0xB5,0x5F,0x0F,0x05,0x0F,0x00,0x0A,\n0x09,0x0A,0x04,0x0A,0x09,0x08,/*\"謖\",3995*/},{\n\n0x55,0x56,0x54,0x08,0x0C,0x3B,0xA8,0xA8,0x6B,0x04,0x08,0x0F,0x05,0x07,0x08,0x0F,\n0x09,0x0F,0x09,0x0F,0x09,0x0F,/*\"諡\",3996*/},{\n\n0x55,0x56,0x54,0x00,0xAC,0xA0,0x9D,0xAA,0xA4,0xB2,0x8D,0x0F,0x05,0x0F,0x08,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"謐\",3997*/},{\n\n0x55,0x56,0x54,0x00,0xF2,0x16,0x5A,0xF3,0x5A,0x16,0xF2,0x0F,0x05,0x0F,0x00,0x0F,\n0x00,0x07,0x05,0x07,0x08,0x0F,/*\"謫\",3998*/},{\n\n0x55,0x56,0x54,0x00,0x7A,0x2B,0x7A,0x02,0x3A,0x43,0x7A,0x0F,0x05,0x0F,0x00,0x0B,\n0x05,0x0F,0x00,0x0B,0x05,0x0F,/*\"譾\",3999*/},{\n\n0x55,0x56,0x54,0x2C,0xD9,0x4F,0x79,0x6C,0x59,0xFF,0x29,0x0F,0x05,0x0F,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"譖\",4000*/},{\n\n0x55,0x56,0x54,0x00,0x08,0xFC,0x57,0x54,0xFD,0x56,0x54,0x0F,0x05,0x0F,0x00,0x0C,\n0x03,0x0D,0x01,0x0D,0x01,0x0D,/*\"譙\",4001*/},{\n\n0x55,0x56,0x54,0x00,0xE8,0x59,0xEB,0x7D,0xCD,0x4B,0xD8,0x0F,0x05,0x0F,0x00,0x0F,\n0x01,0x0E,0x0A,0x0E,0x01,0x0F,/*\"譎\",4002*/},{\n\n0x55,0x56,0x54,0x00,0xFC,0x14,0x7F,0x55,0x20,0xFF,0x24,0x0F,0x05,0x0F,0x04,0x03,\n0x0F,0x05,0x0F,0x04,0x03,0x0C,/*\"讞\",4003*/},{\n\n0x55,0x56,0x54,0x00,0xFE,0x15,0xAD,0xB5,0xA7,0xAC,0x14,0x0F,0x05,0x07,0x08,0x07,\n0x00,0x0E,0x0A,0x0A,0x0E,0x00,/*\"譫\",4004*/},{\n\n0x55,0x56,0x54,0xAC,0xFB,0x0C,0xFB,0xAC,0xFF,0x8A,0x4C,0x0F,0x05,0x07,0x0A,0x0F,\n0x08,0x0F,0x0A,0x03,0x04,0x0E,/*\"讖\",4005*/},{\n\n0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x00,\n0x00,0x0F,0x00,0x01,0x01,0x00,/*\"卩\",4006*/},{\n\n0x24,0x95,0xAD,0xA5,0xB1,0xBD,0xA3,0xA5,0xA8,0x14,0x12,0x00,0x06,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0B,0x0C,0x00,/*\"巹\",4007*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x02,0x02,0x01,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"阝\",4008*/},{\n\n0xFF,0x01,0x19,0xE7,0x02,0xFE,0x02,0x02,0xFE,0x02,0x02,0x0F,0x02,0x02,0x09,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"阢\",4009*/},{\n\n0xFE,0x02,0x32,0xCE,0x20,0x22,0x22,0xFE,0x21,0x21,0x20,0x0F,0x02,0x02,0x01,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"阡\",4010*/},{\n\n0xFE,0x02,0x32,0xCE,0x80,0x88,0xFF,0x88,0x88,0xFF,0x88,0x0F,0x02,0x02,0x01,0x08,\n0x04,0x03,0x00,0x00,0x0F,0x00,/*\"阱\",4011*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0xFE,0x12,0xF2,0x12,0x91,0x71,0x0F,0x02,0x02,0x09,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"阪\",4012*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0xC0,0x40,0x7F,0x48,0x48,0xC8,0x0F,0x02,0x02,0x01,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"阽\",4013*/},{\n\n0xFE,0x02,0x32,0xCE,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x0F,0x02,0x02,0x01,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"阼\",4014*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0xFC,0x24,0xE4,0x3F,0xE4,0x0C,0x0F,0x02,0x02,0x09,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"陂\",4015*/},{\n\n0xFE,0x32,0xCE,0x00,0x12,0xAA,0x92,0xAA,0x92,0xAA,0x02,0x0F,0x02,0x01,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"陘\",4016*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0x24,0x34,0xAD,0x66,0x24,0x94,0x0F,0x02,0x02,0x01,0x08,\n0x09,0x09,0x04,0x02,0x05,0x08,/*\"陔\",4017*/},{\n\n0xFE,0x02,0x32,0xCE,0x20,0xBC,0x20,0xFF,0x24,0x24,0xA4,0x0F,0x02,0x02,0x01,0x09,\n0x08,0x04,0x05,0x02,0x01,0x00,/*\"陟\",4018*/},{\n\n0xFE,0x02,0x32,0xCE,0x00,0x7E,0x49,0x40,0x4A,0x7E,0x00,0x0F,0x02,0x02,0x01,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"隉\",4019*/},{\n\n0xFE,0x32,0xCE,0x01,0xFF,0x49,0xFF,0x01,0xFE,0x02,0xFE,0x0F,0x02,0x01,0x02,0x03,\n0x02,0x0F,0x09,0x04,0x03,0x0C,/*\"陬\",4020*/},{\n\n0xFE,0x32,0xCE,0x48,0xFA,0x4A,0xFE,0x49,0xF9,0x48,0x40,0x0F,0x02,0x01,0x02,0x0B,\n0x0A,0x0F,0x0A,0x0B,0x02,0x00,/*\"陲\",4021*/},{\n\n0xFE,0x32,0xCE,0x00,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x00,0x0F,0x02,0x01,0x02,0x03,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"陴\",4022*/},{\n\n0xFF,0x01,0x19,0xE7,0x40,0xDF,0x55,0xDF,0x55,0x5F,0x40,0x0F,0x02,0x02,0x01,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"隈\",4023*/},{\n\n0xFE,0x02,0x32,0xCE,0x80,0xBE,0xAB,0xAA,0xAA,0xBE,0x80,0x0F,0x02,0x02,0x01,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"隍\",4024*/},{\n\n0xFE,0x32,0xCE,0x00,0x7C,0x54,0xF6,0x5D,0xD4,0x7C,0x00,0x0F,0x02,0x01,0x08,0x04,\n0x03,0x00,0x07,0x0A,0x0B,0x0C,/*\"隗\",4025*/},{\n\n0xFF,0x31,0xCF,0x00,0x5F,0xB5,0x55,0x15,0x55,0xB5,0x5F,0x0F,0x02,0x01,0x00,0x0B,\n0x02,0x0B,0x00,0x0B,0x02,0x0B,/*\"隰\",4026*/},{\n\n0x20,0x22,0x22,0xFE,0x22,0x22,0x20,0xFE,0x02,0x32,0xCE,0x00,0x00,0x00,0x0F,0x00,\n0x00,0x00,0x0F,0x02,0x02,0x01,/*\"邗\",4027*/},{\n\n0x00,0x02,0x02,0xFE,0x02,0x02,0x00,0xFE,0x02,0x32,0xCE,0x02,0x02,0x02,0x01,0x01,\n0x01,0x00,0x0F,0x02,0x02,0x01,/*\"邛\",4028*/},{\n\n0xFE,0x22,0xEA,0xBF,0xEA,0xBE,0xEA,0x20,0xFE,0x32,0xCE,0x07,0x00,0x0B,0x06,0x03,\n0x06,0x0B,0x00,0x0F,0x02,0x01,/*\"鄺\",4029*/},{\n\n0x08,0xF8,0x09,0x0A,0x08,0x08,0x00,0xFE,0x02,0x32,0xCE,0x00,0x07,0x04,0x04,0x04,\n0x00,0x00,0x0F,0x02,0x02,0x01,/*\"邙\",4030*/},{\n\n0x00,0xFE,0xAB,0xAA,0xAA,0xAA,0xAE,0x00,0xFE,0x32,0xCE,0x06,0x00,0x06,0x00,0x0E,\n0x08,0x07,0x00,0x0F,0x02,0x01,/*\"鄔\",4031*/},{\n\n0x04,0x04,0xFD,0x26,0x24,0xE4,0x00,0xFE,0x02,0x32,0xCE,0x08,0x06,0x01,0x08,0x08,\n0x07,0x00,0x0F,0x02,0x02,0x01,/*\"邡\",4032*/},{\n\n0xF2,0x12,0x92,0x7E,0x92,0x12,0xF2,0x00,0xFE,0x32,0xCE,0x0F,0x01,0x00,0x00,0x00,\n0x09,0x0F,0x00,0x0F,0x02,0x01,/*\"邴\",4033*/},{\n\n0x42,0x22,0x12,0xFE,0x12,0x62,0x00,0xFE,0x02,0x32,0xCE,0x04,0x04,0x04,0x03,0x02,\n0x02,0x00,0x0F,0x02,0x02,0x01,/*\"邳\",4034*/},{\n\n0x10,0x10,0xFF,0x00,0xFF,0x10,0x10,0xFE,0x02,0x32,0xCE,0x02,0x01,0x0F,0x00,0x0F,\n0x04,0x02,0x0F,0x02,0x02,0x01,/*\"邶\",4035*/},{\n\n0x25,0xAC,0xB7,0xE4,0xB7,0xAC,0x25,0x00,0xFE,0x32,0xCE,0x0A,0x06,0x02,0x0F,0x02,\n0x06,0x0A,0x00,0x0F,0x02,0x01,/*\"鄴\",4036*/},{\n\n0xFE,0x22,0x22,0xFE,0x21,0x21,0x00,0xFE,0x02,0x32,0xCE,0x0F,0x04,0x08,0x03,0x04,\n0x0E,0x00,0x0F,0x02,0x02,0x01,/*\"邸\",4037*/},{\n\n0xD8,0x54,0x53,0x50,0xD8,0x30,0x00,0xFE,0x02,0x32,0xCE,0x0F,0x04,0x04,0x04,0x0F,\n0x00,0x00,0x0F,0x02,0x02,0x01,/*\"邰\",4038*/},{\n\n0x84,0x74,0x84,0xFF,0x84,0x74,0x84,0x00,0xFE,0x32,0xCE,0x08,0x04,0x02,0x01,0x02,\n0x04,0x08,0x00,0x0F,0x02,0x01,/*\"郟\",4039*/},{\n\n0x92,0x9A,0x96,0xF2,0x9A,0xB2,0x00,0xFE,0x02,0x32,0xCE,0x08,0x08,0x08,0x07,0x04,\n0x04,0x00,0x0F,0x02,0x02,0x01,/*\"郅\",4040*/},{\n\n0x28,0x26,0xA4,0xFF,0xA4,0x24,0x00,0xFE,0x02,0x32,0xCE,0x02,0x01,0x00,0x0F,0x00,\n0x01,0x00,0x0F,0x02,0x02,0x01,/*\"邾\",4041*/},{\n\n0xF4,0xB2,0xD5,0xF5,0xD5,0xB2,0xF4,0x00,0xFE,0x32,0xCE,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x00,0x00,0x0F,0x02,0x01,/*\"鄶\",4042*/},{\n\n0x20,0xA9,0x65,0x32,0xA2,0x25,0x28,0x00,0xFE,0x32,0xCE,0x01,0x04,0x06,0x05,0x04,\n0x06,0x0C,0x00,0x0F,0x02,0x01,/*\"郄\",4043*/},{\n\n0x04,0xFB,0x4A,0xFA,0x02,0xFE,0x00,0xFE,0x02,0x32,0xCE,0x00,0x07,0x02,0x0B,0x08,\n0x07,0x00,0x0F,0x02,0x02,0x01,/*\"郇\",4044*/},{\n\n0xF3,0x55,0x55,0xFF,0x55,0x55,0xF3,0x00,0xFF,0x31,0xCF,0x05,0x05,0x05,0x0F,0x05,\n0x05,0x05,0x00,0x0F,0x02,0x01,/*\"鄆\",4045*/},{\n\n0xED,0xA5,0xED,0xB0,0xED,0xA5,0xAD,0x00,0xFF,0x31,0xCF,0x07,0x02,0x0F,0x0A,0x03,\n0x0E,0x0B,0x00,0x0F,0x02,0x01,/*\"酈\",4046*/},{\n\n0x00,0x5E,0x52,0xD2,0x52,0x5E,0x00,0xFE,0x02,0x32,0xCE,0x08,0x09,0x09,0x07,0x05,\n0x05,0x00,0x0F,0x02,0x02,0x01,/*\"郢\",4047*/},{\n\n0x28,0xA6,0xA4,0xBF,0xA4,0xA4,0x20,0xFE,0x02,0x32,0xCE,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x00,0x0F,0x02,0x02,0x01,/*\"郜\",4048*/},{\n\n0x90,0xD5,0xBA,0xD2,0x92,0x95,0x90,0x00,0xFE,0x32,0xCE,0x00,0x07,0x00,0x0F,0x00,\n0x04,0x07,0x00,0x0F,0x02,0x01,/*\"郗\",4049*/},{\n\n0x2A,0x32,0x26,0xAA,0x61,0x29,0x05,0xFE,0x02,0x32,0xCE,0x02,0x02,0x0A,0x0F,0x01,\n0x01,0x01,0x0F,0x02,0x02,0x01,/*\"郛\",4050*/},{\n\n0x00,0x7C,0xD6,0x7D,0x54,0x7C,0x00,0xFE,0x02,0x32,0xCE,0x02,0x03,0x02,0x0F,0x02,\n0x02,0x00,0x0F,0x02,0x02,0x01,/*\"郫\",4051*/},{\n\n0x08,0xA6,0x10,0xCF,0x14,0xA2,0x00,0xFE,0x02,0x32,0xCE,0x0A,0x09,0x04,0x03,0x05,\n0x08,0x00,0x0F,0x02,0x02,0x01,/*\"郯\",4052*/},{\n\n0xFF,0x81,0xBF,0xEB,0xAB,0xBF,0x81,0x80,0xFF,0x31,0xCF,0x0F,0x08,0x0D,0x0A,0x0A,\n0x0D,0x08,0x08,0x0F,0x02,0x01,/*\"郾\",4053*/},{\n\n0x7A,0x4A,0x7E,0xCA,0x7E,0x4A,0x7A,0x00,0xFE,0x32,0xCE,0x08,0x09,0x09,0x07,0x05,\n0x05,0x00,0x00,0x0F,0x02,0x01,/*\"鄄\",4054*/},{\n\n0x11,0x9D,0x71,0x5F,0x55,0x55,0x51,0x00,0xFF,0x31,0xCF,0x04,0x09,0x05,0x09,0x05,\n0x09,0x07,0x00,0x0F,0x02,0x01,/*\"鄢\",4055*/},{\n\n0x02,0xE2,0xAF,0xFA,0xAF,0xE2,0x00,0xFE,0x02,0x32,0xCE,0x08,0x0A,0x0A,0x0F,0x0A,\n0x0A,0x00,0x0F,0x02,0x02,0x01,/*\"鄞\",4056*/},{\n\n0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0xFE,0x02,0x32,0xCE,0x02,0x02,0x02,0x0F,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x01,/*\"鄣\",4057*/},{\n\n0x52,0xB6,0x9A,0xBE,0x99,0xB5,0x50,0xFE,0x02,0x32,0xCE,0x00,0x0F,0x0A,0x0F,0x0A,\n0x0F,0x00,0x0F,0x02,0x02,0x01,/*\"鄱\",4058*/},{\n\n0xA2,0xEB,0xAA,0xFE,0xAA,0xEB,0xA2,0x00,0xFE,0x32,0xCE,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0E,0x00,0x00,0x0F,0x02,0x01,/*\"鄯\",4059*/},{\n\n0x51,0xDF,0x55,0xFF,0xA9,0x12,0xAE,0x00,0xFF,0x31,0xCF,0x09,0x04,0x02,0x0F,0x00,\n0x03,0x04,0x00,0x0F,0x02,0x01,/*\"鄹\",4060*/},{\n\n0x0C,0x55,0x05,0x7F,0x05,0x55,0x0C,0x00,0xFF,0x31,0xCF,0x0F,0x09,0x0F,0x09,0x0F,\n0x09,0x0F,0x00,0x0F,0x02,0x01,/*\"酃\",4061*/},{\n\n0xBC,0xAA,0xBF,0xAA,0xBF,0xAA,0xBC,0x00,0xFE,0x32,0xCE,0x08,0x0B,0x0E,0x0A,0x0E,\n0x0B,0x08,0x00,0x0F,0x02,0x01,/*\"酆\",4062*/},{\n\n0x08,0x44,0xDB,0x72,0x52,0xDE,0x52,0x52,0x5A,0x62,0xDE,0x02,0x09,0x0B,0x0A,0x06,\n0x03,0x02,0x0A,0x0B,0x08,0x07,/*\"芻\",4063*/},{\n\n0x04,0x7A,0x0B,0x2A,0x1A,0xCA,0x1A,0x2E,0x08,0x78,0x00,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"奐\",4064*/},{\n\n0x02,0xFA,0xAF,0xFA,0xAF,0xFA,0x02,0x08,0xFF,0x08,0xF8,0x0E,0x02,0x0A,0x0F,0x0A,\n0x02,0x0E,0x08,0x07,0x08,0x0F,/*\"勱\",4065*/},{\n\n0x10,0xE8,0x27,0xE4,0x04,0xFC,0x00,0x08,0xFF,0x08,0xF8,0x00,0x03,0x01,0x09,0x08,\n0x07,0x08,0x06,0x09,0x08,0x07,/*\"劬\",4066*/},{\n\n0x22,0x92,0x8E,0xA2,0xA2,0x9E,0x00,0x08,0xFF,0x08,0xF8,0x00,0x0F,0x04,0x04,0x04,\n0x0F,0x08,0x06,0x09,0x08,0x07,/*\"劭\",4067*/},{\n\n0x24,0x34,0xAD,0x66,0x24,0x94,0x00,0x08,0xFF,0x08,0xF8,0x09,0x09,0x04,0x02,0x05,\n0x08,0x08,0x06,0x09,0x08,0x07,/*\"劾\",4068*/},{\n\n0x52,0x4A,0x47,0x52,0x52,0x4E,0x40,0x5E,0x52,0xD2,0x5E,0x00,0x07,0x05,0x05,0x05,\n0x05,0x07,0x00,0x08,0x0F,0x00,/*\"哿\",4069*/},{\n\n0x88,0x89,0xA9,0xBD,0x87,0x85,0x84,0x08,0xFF,0x08,0xF8,0x0F,0x08,0x0F,0x08,0x07,\n0x04,0x07,0x0C,0x07,0x08,0x0F,/*\"勐\",4070*/},{\n\n0x07,0xF1,0x55,0x55,0x55,0xF1,0x07,0x08,0xFF,0x08,0xF8,0x00,0x0F,0x05,0x05,0x05,\n0x0F,0x00,0x08,0x07,0x08,0x0F,/*\"勖\",4071*/},{\n\n0x92,0xCF,0x82,0xD2,0x9E,0x80,0x7F,0xC9,0x7F,0x49,0x7F,0x08,0x07,0x08,0x07,0x08,\n0x0F,0x04,0x0E,0x09,0x0C,0x03,/*\"勰\",4072*/},{\n\n0x00,0xBE,0xAA,0xA9,0xA0,0xFF,0xA0,0xAA,0xAA,0x3E,0x00,0x08,0x08,0x09,0x0A,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x08,/*\"叟\",4073*/},{\n\n0x9C,0x40,0x3F,0x44,0xEA,0xAB,0xEA,0x44,0x3F,0x44,0x82,0x08,0x09,0x0B,0x05,0x05,\n0x05,0x05,0x05,0x0B,0x08,0x08,/*\"燮\",4074*/},{\n\n0x80,0x5F,0xF5,0x55,0x5F,0x60,0xDF,0x55,0x55,0x5F,0x00,0x08,0x09,0x0B,0x05,0x05,\n0x05,0x05,0x05,0x0B,0x09,0x08,/*\"矍\",4075*/},{\n\n0x02,0x32,0x2A,0xE6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x05,0x02,0x05,0x08,\n0x08,0x08,0x08,0x08,0x08,0x08,/*\"廴\",4076*/},{\n\n0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x07,0x04,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"凵\",4077*/},{\n\n0xFC,0x80,0x48,0x38,0x00,0xFF,0x28,0x44,0x80,0x00,0xFC,0x07,0x04,0x04,0x04,0x05,\n0x05,0x04,0x04,0x04,0x04,0x0F,/*\"凼\",4078*/},{\n\n0x00,0x7E,0x48,0x62,0x54,0x69,0x54,0x62,0x48,0x7E,0x00,0x00,0x07,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x09,0x09,0x09,0x0C,/*\"鬯\",4079*/},{\n\n0x00,0x00,0xC0,0x30,0x0C,0x03,0x00,0x40,0x80,0x00,0x00,0x02,0x03,0x02,0x02,0x02,\n0x02,0x02,0x02,0x02,0x03,0x0E,/*\"厶\",4080*/},{\n\n0x80,0x88,0x8C,0xEB,0x88,0x88,0x88,0xE8,0x8C,0x98,0x80,0x00,0x08,0x06,0x01,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"弁\",4081*/},{\n\n0x10,0x94,0xD6,0xB5,0x9C,0x94,0x94,0xB4,0xD6,0x9C,0x10,0x01,0x00,0x0F,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0F,0x00,0x01,/*\"畚\",4082*/},{\n\n0x92,0xAA,0x92,0xAA,0x00,0xA4,0x34,0xAD,0x26,0xB4,0x64,0x08,0x08,0x07,0x04,0x08,\n0x07,0x00,0x07,0x00,0x0F,0x08,/*\"巰\",4083*/},{\n\n0x04,0x44,0x2A,0x19,0x08,0x88,0x48,0x49,0x3A,0x04,0x04,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"坌\",4084*/},{\n\n0x82,0xBA,0xAA,0xEE,0x82,0x82,0x82,0xEE,0xAA,0xBA,0x82,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"堊\",4085*/},{\n\n0x08,0x04,0xFE,0x05,0x04,0x84,0x5F,0x22,0x52,0x8B,0xE2,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"垡\",4086*/},{\n\n0x22,0xAE,0xEA,0x3B,0x2E,0xA2,0x54,0x3F,0x24,0x7C,0xC0,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"塾\",4087*/},{\n\n0xC2,0xBE,0xAA,0xFF,0xAA,0xBE,0xCA,0xB7,0x51,0xB7,0x84,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"墼\",4088*/},{\n\n0xAA,0xB6,0xB2,0x6A,0x22,0x13,0xFE,0xAA,0xFA,0xAE,0xAA,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"壅\",4089*/},{\n\n0x2C,0xF4,0xAF,0xAD,0xF5,0x2C,0x82,0x5E,0x22,0x5E,0x80,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"壑\",4090*/},{\n\n0x10,0x10,0xFF,0x10,0x20,0x22,0x22,0xFE,0x22,0x22,0x20,0x04,0x04,0x03,0x02,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"圩\",4091*/},{\n\n0x08,0x08,0xFF,0x08,0x10,0xD2,0xB2,0x92,0x92,0x92,0x10,0x04,0x04,0x03,0x02,0x00,\n0x00,0x00,0x08,0x08,0x07,0x00,/*\"圬\",4092*/},{\n\n0x08,0x08,0xFF,0x08,0x10,0x28,0x27,0xA4,0x64,0x24,0x04,0x04,0x04,0x03,0x02,0x00,\n0x06,0x09,0x08,0x08,0x08,0x0E,/*\"圪\",4093*/},{\n\n0x08,0xFF,0x08,0x00,0xFF,0x00,0x00,0xFE,0x00,0x00,0xFF,0x02,0x03,0x09,0x04,0x03,\n0x00,0x00,0x07,0x00,0x00,0x0F,/*\"圳\",4094*/},{\n\n0x08,0xFF,0x08,0xFE,0x22,0xEA,0xBE,0xEB,0xBE,0xEA,0x22,0x02,0x03,0x09,0x07,0x00,\n0x0B,0x06,0x03,0x06,0x0B,0x00,/*\"壙\",4095*/},{\n\n0x08,0x08,0xFF,0x08,0x00,0xE2,0x22,0x22,0x22,0x3E,0x00,0x04,0x04,0x03,0x02,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"圮\",4096*/},{\n\n0x08,0x08,0xFF,0x08,0x00,0xFE,0x42,0x42,0x42,0x7E,0x00,0x04,0x04,0x03,0x02,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"圯\",4097*/},{\n\n0x08,0xFF,0x08,0xFF,0x51,0x35,0xFD,0x53,0x35,0xFD,0x53,0x02,0x03,0x09,0x07,0x08,\n0x0E,0x08,0x0F,0x0A,0x0A,0x08,/*\"壢\",4098*/},{\n\n0x10,0x10,0xFF,0x10,0x00,0xFE,0x12,0x12,0xF1,0x11,0x10,0x04,0x04,0x03,0x02,0x08,\n0x07,0x00,0x00,0x0F,0x00,0x00,/*\"圻\",4099*/},{\n\n0x10,0x10,0xFF,0x10,0x00,0xFE,0x12,0xF2,0x12,0x91,0x71,0x04,0x04,0x03,0x0A,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"坂\",4100*/},{\n\n0x10,0x10,0xFF,0x10,0x04,0xFF,0x44,0x44,0x44,0xFF,0x04,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"坩\",4101*/},{\n\n0x10,0xFF,0x10,0x0A,0xEE,0xAB,0xEE,0x0A,0xF7,0x55,0x5D,0x04,0x07,0x02,0x00,0x0F,\n0x02,0x0F,0x00,0x07,0x09,0x0D,/*\"壠\",4102*/},{\n\n0x10,0x10,0xFF,0x10,0x00,0xC0,0x40,0x7F,0x48,0x48,0xC8,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"坫\",4103*/},{\n\n0x08,0xFF,0x08,0x00,0xF8,0x28,0xA8,0xFF,0xAA,0xAA,0xDA,0x02,0x03,0x01,0x04,0x0B,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"壚\",4104*/},{\n\n0x08,0x08,0xFF,0x08,0x00,0xFE,0x12,0x92,0xF1,0x11,0x10,0x02,0x02,0x01,0x01,0x08,\n0x07,0x00,0x00,0x0F,0x01,0x02,/*\"坼\",4105*/},{\n\n0x10,0x10,0xFF,0x10,0x00,0xFE,0x22,0x22,0xFE,0x21,0x21,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x08,0x03,0x04,0x0E,/*\"坻\",4106*/},{\n\n0x10,0x10,0xFF,0x10,0x0C,0xE4,0x05,0x86,0x44,0x24,0x0C,0x04,0x04,0x03,0x02,0x00,\n0x07,0x09,0x08,0x08,0x08,0x0E,/*\"坨\",4107*/},{\n\n0x10,0x10,0xFF,0x10,0x00,0xFE,0x12,0xD2,0x12,0x92,0x5E,0x04,0x04,0x03,0x02,0x08,\n0x07,0x00,0x07,0x09,0x08,0x0E,/*\"坭\",4108*/},{\n\n0x10,0xFF,0x10,0x00,0xA0,0x7E,0xAA,0x32,0x22,0xFE,0x20,0x04,0x07,0x02,0x00,0x03,\n0x02,0x02,0x0B,0x0A,0x07,0x02,/*\"坶\",4109*/},{\n\n0x10,0xFF,0x10,0x00,0x38,0xE7,0x30,0x08,0xFF,0x08,0xF8,0x04,0x07,0x02,0x00,0x03,\n0x02,0x0B,0x06,0x01,0x08,0x0F,/*\"坳\",4110*/},{\n\n0x08,0x08,0xFF,0x08,0xF2,0x12,0x1E,0x02,0x1E,0x12,0xF2,0x04,0x04,0x03,0x02,0x09,\n0x09,0x0F,0x08,0x0F,0x09,0x09,/*\"埡\",4111*/},{\n\n0x10,0x10,0xFF,0x10,0x00,0x32,0x2A,0xE6,0x22,0x32,0x62,0x04,0x04,0x03,0x02,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"垤\",4112*/},{\n\n0x10,0xFF,0x10,0x00,0xFE,0x02,0xEA,0x2A,0xEA,0x02,0xFE,0x04,0x07,0x02,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"垌\",4113*/},{\n\n0x10,0xFF,0x10,0x00,0xD6,0x54,0x54,0x57,0x54,0x54,0xD6,0x04,0x07,0x02,0x00,0x09,\n0x0B,0x0D,0x09,0x0D,0x0B,0x09,/*\"塏\",4114*/},{\n\n0x10,0xFF,0x10,0x00,0x32,0xCE,0x00,0xF2,0x02,0xFF,0x11,0x04,0x07,0x02,0x00,0x0A,\n0x07,0x08,0x09,0x09,0x09,0x09,/*\"埏\",4115*/},{\n\n0x10,0xFF,0x10,0x00,0xFC,0x04,0xE6,0x25,0xE4,0x04,0xFC,0x04,0x07,0x02,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"垧\",4116*/},{\n\n0x10,0xFF,0x10,0x00,0xC4,0x6A,0xD5,0x4A,0xD5,0x4A,0xD1,0x04,0x07,0x02,0x00,0x0F,\n0x04,0x06,0x05,0x06,0x04,0x0F,/*\"堖\",4117*/},{\n\n0x10,0x10,0xFF,0x10,0x24,0x34,0xAD,0x66,0x24,0x94,0x44,0x04,0x04,0x03,0x02,0x09,\n0x09,0x04,0x02,0x03,0x04,0x08,/*\"垓\",4118*/},{\n\n0x08,0x08,0xFF,0x08,0x00,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x02,0x02,0x01,0x01,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"垠\",4119*/},{\n\n0x10,0x10,0xFF,0x10,0x20,0x2F,0x29,0xE9,0x29,0x2F,0x20,0x04,0x04,0x03,0x02,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"埕\",4120*/},{\n\n0x08,0xFF,0x08,0xFE,0x22,0xFE,0x10,0x54,0x5F,0xF4,0x50,0x02,0x03,0x01,0x07,0x02,\n0x07,0x00,0x01,0x0A,0x0F,0x00,/*\"塒\",4121*/},{\n\n0x10,0x10,0xFF,0x10,0xE0,0x3F,0xA5,0xBD,0xA1,0x3F,0xE0,0x04,0x04,0x03,0x02,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"堝\",4122*/},{\n\n0x10,0xFF,0x10,0x00,0xF4,0x55,0x15,0xFF,0x15,0x55,0xF4,0x04,0x07,0x02,0x00,0x0D,\n0x05,0x0D,0x07,0x0D,0x05,0x0D,/*\"壎\",4123*/},{\n\n0x10,0x10,0xFF,0x10,0x4A,0x52,0x46,0x4A,0x41,0xE9,0x45,0x04,0x04,0x03,0x02,0x00,\n0x01,0x02,0x00,0x08,0x0F,0x00,/*\"埒\",4124*/},{\n\n0x10,0x10,0xFF,0x10,0x8C,0xA4,0xA5,0xA6,0xA4,0xA4,0x8C,0x04,0x04,0x03,0x02,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"垸\",4125*/},{\n\n0x10,0xFF,0x10,0x02,0xFA,0xAA,0xAF,0xAA,0xAA,0xFA,0x02,0x04,0x07,0x02,0x08,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x08,/*\"埴\",4126*/},{\n\n0x08,0xFF,0x28,0x12,0xEA,0xA6,0xF3,0xA6,0xEA,0x12,0x10,0x02,0x03,0x01,0x00,0x07,\n0x02,0x07,0x0A,0x0B,0x08,0x0E,/*\"埯\",4127*/},{\n\n0x10,0x10,0xFF,0x10,0x80,0x5F,0xF5,0x55,0xD5,0x5F,0xC0,0x04,0x04,0x03,0x02,0x02,\n0x09,0x04,0x02,0x09,0x08,0x07,/*\"埸\",4128*/},{\n\n0x08,0xFF,0x08,0x00,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x00,0x02,0x03,0x01,0x02,0x03,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"埤\",4129*/},{\n\n0x10,0xFF,0x10,0x00,0x08,0x14,0x92,0x19,0x52,0x34,0x08,0x04,0x07,0x02,0x04,0x03,\n0x00,0x06,0x09,0x0C,0x01,0x06,/*\"埝\",4130*/},{\n\n0x10,0xFF,0x10,0x00,0xFE,0x92,0xFE,0x00,0xFE,0x92,0xFE,0x04,0x07,0x02,0x08,0x07,\n0x08,0x0F,0x08,0x07,0x08,0x0F,/*\"堋\",4131*/},{\n\n0x10,0xFF,0x10,0x08,0xF4,0x93,0xD2,0xBA,0x96,0xF0,0x00,0x04,0x07,0x02,0x08,0x04,\n0x03,0x00,0x07,0x08,0x0A,0x0C,/*\"堍\",4132*/},{\n\n0x10,0xFF,0x10,0xC0,0x55,0x55,0xD5,0x55,0x55,0x5F,0xC0,0x04,0x07,0x02,0x00,0x07,\n0x01,0x0F,0x01,0x05,0x07,0x00,/*\"埽\",4133*/},{\n\n0x10,0xFF,0x10,0x48,0xAA,0x2A,0xFF,0x2A,0xAA,0x7E,0x08,0x04,0x07,0x02,0x04,0x02,\n0x09,0x0F,0x01,0x02,0x04,0x04,/*\"埭\",4134*/},{\n\n0x10,0xFF,0x10,0x00,0xFE,0x0A,0xEA,0x8A,0xFA,0x8A,0xEE,0x04,0x07,0x02,0x08,0x07,\n0x00,0x0E,0x08,0x0F,0x08,0x0E,/*\"堀\",4135*/},{\n\n0x10,0x10,0xFF,0x10,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x04,0x04,0x03,0x02,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"堞\",4136*/},{\n\n0x10,0xFF,0x10,0x00,0x7A,0x4A,0x7E,0xCA,0x7E,0x4A,0x7A,0x04,0x07,0x02,0x08,0x09,\n0x09,0x09,0x0F,0x09,0x09,0x09,/*\"堙\",4137*/},{\n\n0x10,0x10,0xFF,0x10,0x2F,0x29,0xEF,0xB9,0xAF,0xA9,0xAF,0x04,0x04,0x03,0x02,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"塄\",4138*/},{\n\n0x08,0xFF,0x08,0x10,0xFC,0x03,0x48,0x3A,0xEA,0x2E,0x28,0x02,0x03,0x01,0x00,0x0F,\n0x00,0x09,0x05,0x03,0x05,0x09,/*\"堠\",4139*/},{\n\n0x10,0xFF,0x10,0x00,0xC1,0x5D,0xD5,0x55,0xD5,0x5D,0xC1,0x04,0x07,0x02,0x00,0x0F,\n0x00,0x02,0x0F,0x02,0x08,0x0F,/*\"塥\",4140*/},{\n\n0x08,0xFF,0x08,0xFF,0x01,0xF9,0xAD,0xAB,0xA9,0xF9,0x01,0x02,0x03,0x09,0x07,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"塬\",4141*/},{\n\n0x08,0xFF,0x08,0x70,0x5F,0x75,0x55,0x55,0x75,0x5F,0x70,0x02,0x03,0x01,0x08,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"墁\",4142*/},{\n\n0x08,0xFF,0x08,0xFE,0x22,0xAA,0xAA,0xFF,0xAA,0xFA,0x22,0x02,0x03,0x09,0x07,0x00,\n0x0F,0x02,0x07,0x0A,0x0F,0x00,/*\"墉\",4143*/},{\n\n0x10,0xFF,0x10,0xA5,0x88,0xA5,0xDF,0xA1,0xBF,0x84,0x98,0x04,0x07,0x02,0x04,0x02,\n0x01,0x0F,0x01,0x02,0x04,0x04,/*\"墚\",4144*/},{\n\n0x08,0xFF,0x08,0x00,0xFF,0x05,0xAD,0x15,0xBD,0x15,0x2F,0x02,0x03,0x09,0x06,0x01,\n0x06,0x05,0x05,0x0F,0x05,0x05,/*\"墀\",4145*/},{\n\n0x42,0x3A,0xAA,0xFF,0xAA,0xFA,0xA4,0xEF,0x95,0x2F,0x24,0x02,0x01,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x01,0x02,/*\"馨\",4146*/},{\n\n0x0A,0x3A,0xEF,0x7A,0x4A,0xE0,0x42,0x5A,0xEF,0x5A,0x82,0x04,0x04,0x07,0x05,0x07,\n0x05,0x0D,0x05,0x07,0x04,0x04,/*\"鼙\",4147*/},{\n\n0x1A,0xEA,0xAF,0xEA,0x1A,0x21,0x92,0x48,0x37,0x44,0x8C,0x08,0x0A,0x0C,0x0A,0x08,\n0x04,0x06,0x08,0x0D,0x00,0x0C,/*\"懿\",4148*/},{\n\n0x02,0x02,0x02,0x07,0x02,0x02,0x02,0x07,0x02,0x02,0x02,0x00,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"艹\",4149*/},{\n\n0x02,0x22,0x22,0x27,0xFA,0x22,0x22,0x27,0xE2,0x02,0x02,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x00,0x07,0x08,0x0E,/*\"艽\",4150*/},{\n\n0x02,0x12,0x12,0xF7,0x12,0x12,0x12,0xD7,0xB2,0x92,0x82,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x08,0x08,0x08,0x07,/*\"艿\",4151*/},{\n\n0x04,0x84,0x84,0x8F,0x84,0xF4,0x84,0x8F,0x84,0x84,0x04,0x08,0x08,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"芏\",4152*/},{\n\n0x82,0x92,0x92,0x97,0x92,0xF2,0x92,0x97,0x8A,0x8A,0x82,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"芊\",4153*/},{\n\n0x02,0x12,0x12,0xF7,0x12,0x92,0x12,0x77,0x52,0xC2,0x02,0x08,0x04,0x03,0x08,0x08,\n0x04,0x05,0x02,0x05,0x08,0x08,/*\"芨\",4154*/},{\n\n0x02,0xA2,0xA2,0x27,0xFA,0x22,0x22,0x27,0xE2,0x02,0x02,0x08,0x08,0x04,0x03,0x02,\n0x04,0x00,0x00,0x07,0x08,0x0E,/*\"芄\",4155*/},{\n\n0x02,0xD2,0x52,0x57,0x52,0x52,0x52,0x57,0x52,0x72,0x02,0x00,0x01,0x01,0x01,0x01,\n0x01,0x01,0x01,0x09,0x09,0x07,/*\"芎\",4156*/},{\n\n0x02,0x92,0x92,0x97,0x92,0x92,0x92,0x97,0x92,0xF2,0x02,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0C,/*\"芑\",4157*/},{\n\n0x62,0xDA,0x62,0x07,0xF2,0x5A,0xF2,0x07,0xF2,0x52,0xB2,0x0B,0x06,0x03,0x00,0x0F,\n0x09,0x05,0x08,0x0F,0x02,0x01,/*\"薌\",4158*/},{\n\n0x82,0x92,0x92,0x97,0x92,0xFA,0x92,0x97,0x92,0x92,0x82,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"芙\",4159*/},{\n\n0x82,0x92,0x92,0x97,0x92,0x92,0x92,0x97,0x92,0x92,0x82,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"芫\",4160*/},{\n\n0x82,0x92,0x92,0x97,0x92,0x92,0x92,0x97,0x92,0x92,0x82,0x00,0x04,0x06,0x05,0x04,\n0x04,0x04,0x04,0x06,0x0C,0x00,/*\"芸\",4161*/},{\n\n0x12,0xD2,0x52,0x57,0x52,0xFA,0x52,0x57,0x52,0xD2,0x12,0x00,0x07,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x04,0x07,0x00,/*\"芾\",4162*/},{\n\n0x12,0x52,0xD2,0x57,0x52,0x7A,0x52,0x57,0xD2,0x12,0x12,0x08,0x08,0x04,0x05,0x02,\n0x02,0x02,0x05,0x04,0x08,0x08,/*\"芰\",4163*/},{\n\n0x02,0xFA,0x8A,0xAF,0xEA,0x9A,0x0A,0xAF,0xEA,0x9A,0x8A,0x08,0x07,0x0A,0x0D,0x0B,\n0x08,0x0F,0x0A,0x0B,0x09,0x0A,/*\"藶\",4164*/},{\n\n0x02,0xF2,0x12,0xD7,0x52,0x52,0x52,0x57,0x52,0xD2,0x12,0x08,0x07,0x00,0x07,0x08,\n0x08,0x08,0x08,0x0A,0x0B,0x0C,/*\"苊\",4165*/},{\n\n0x02,0xF2,0x52,0x57,0x52,0x52,0x52,0x57,0x52,0xD2,0x12,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"苣\",4166*/},{\n\n0x02,0xF2,0x42,0x47,0x42,0x02,0xF2,0x07,0x82,0x42,0x22,0x00,0x0F,0x08,0x04,0x04,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"芘\",4167*/},{\n\n0x04,0x04,0xC4,0x0F,0x04,0xF4,0x84,0x8F,0x84,0x84,0x04,0x08,0x08,0x0F,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"芷\",4168*/},{\n\n0x02,0xF2,0x17,0x12,0x92,0x7A,0x92,0x12,0x17,0xF2,0x02,0x00,0x0F,0x00,0x01,0x00,\n0x00,0x00,0x01,0x08,0x0F,0x00,/*\"芮\",4169*/},{\n\n0x02,0xFA,0xAA,0xAF,0xAA,0xAA,0xAA,0xAF,0xAA,0xFA,0x02,0x08,0x0B,0x0A,0x06,0x02,\n0x02,0x06,0x0A,0x0A,0x0B,0x0C,/*\"莧\",4170*/},{\n\n0x02,0x02,0xFA,0xAF,0xAA,0xAA,0xAA,0xAF,0xAA,0x0A,0x02,0x02,0x0E,0x0B,0x0A,0x02,\n0x02,0x06,0x0A,0x0E,0x0A,0x0A,/*\"萇\",4171*/},{\n\n0x22,0x92,0x4A,0x07,0x22,0x1A,0x22,0x87,0x22,0x1A,0x22,0x01,0x0F,0x00,0x08,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"蓯\",4172*/},{\n\n0x42,0x42,0x22,0x27,0x12,0x4A,0x92,0x27,0x22,0x42,0x42,0x00,0x01,0x01,0x01,0x01,\n0x01,0x09,0x05,0x03,0x01,0x00,/*\"芩\",4173*/},{\n\n0x42,0x22,0x1A,0x97,0x72,0x12,0xF2,0x17,0x12,0xF2,0x02,0x02,0x02,0x09,0x08,0x04,\n0x02,0x09,0x08,0x08,0x07,0x00,/*\"芴\",4174*/},{\n\n0x42,0x22,0x1A,0x17,0x12,0xD2,0x12,0x17,0x12,0x52,0x32,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"芡\",4175*/},{\n\n0x02,0xF2,0x92,0x97,0x92,0x92,0xF2,0x8F,0x8A,0x8A,0x82,0x00,0x0F,0x04,0x02,0x00,\n0x00,0x01,0x02,0x04,0x08,0x0E,/*\"芪\",4176*/},{\n\n0x42,0xA2,0x9A,0x8F,0x8A,0x8A,0x8A,0x8F,0xBA,0x42,0x42,0x08,0x08,0x09,0x0A,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x08,/*\"芟\",4177*/},{\n\n0x22,0x22,0x22,0x27,0xE2,0x2A,0xB2,0x27,0x22,0x22,0x22,0x00,0x00,0x00,0x00,0x0F,\n0x00,0x00,0x01,0x02,0x00,0x00,/*\"苄\",4178*/},{\n\n0xB2,0x92,0x92,0x97,0x92,0x9A,0x92,0x97,0x92,0x92,0xB2,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"苧\",4179*/},{\n\n0x02,0x12,0x12,0xD7,0xB2,0x92,0x02,0xF7,0x02,0x02,0x02,0x01,0x01,0x09,0x0F,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"芤\",4180*/},{\n\n0x02,0xF2,0x02,0x07,0x12,0x62,0x02,0x87,0x72,0x02,0x02,0x00,0x0F,0x04,0x02,0x08,\n0x04,0x02,0x01,0x01,0x02,0x0C,/*\"苡\",4181*/},{\n\n0x12,0x92,0x92,0x97,0x92,0xFA,0x92,0x97,0x92,0x92,0x12,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"茉\",4182*/},{\n\n0x12,0x12,0xFA,0x97,0x92,0x92,0x92,0x97,0xFA,0x12,0x12,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x0F,0x00,0x00,/*\"苷\",4183*/},{\n\n0x02,0x12,0x12,0x97,0x52,0xF2,0x12,0x57,0x92,0x12,0x02,0x08,0x09,0x09,0x08,0x08,\n0x0B,0x08,0x08,0x08,0x09,0x08,/*\"苤\",4184*/},{\n\n0x22,0xEA,0xBA,0xAF,0xBA,0xEA,0x22,0xBF,0xAA,0xEA,0x02,0x00,0x0F,0x02,0x02,0x0A,\n0x0F,0x00,0x07,0x0A,0x0A,0x0C,/*\"蘢\",4185*/},{\n\n0x22,0x22,0x27,0xE2,0xBA,0xA2,0xA2,0xAA,0xB7,0xA2,0x22,0x08,0x04,0x03,0x08,0x09,\n0x0A,0x04,0x04,0x0A,0x09,0x08,/*\"茇\",4186*/},{\n\n0x02,0xF2,0x52,0x57,0x52,0x52,0x52,0x57,0x52,0xF2,0x02,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"苜\",4187*/},{\n\n0x02,0xF2,0x52,0x57,0x52,0x52,0x52,0x57,0x52,0xF2,0x02,0x08,0x0F,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0F,0x08,/*\"苴\",4188*/},{\n\n0x02,0xF2,0x52,0x57,0x52,0xFE,0x52,0x57,0x52,0xF2,0x02,0x01,0x0F,0x01,0x01,0x01,\n0x01,0x01,0x01,0x09,0x0F,0x01,/*\"苒\",4189*/},{\n\n0x02,0xF2,0x12,0xD7,0x52,0x52,0x52,0xD7,0x12,0xF2,0x02,0x00,0x0F,0x00,0x03,0x02,\n0x02,0x02,0x03,0x08,0x0F,0x00,/*\"苘\",4190*/},{\n\n0x82,0x42,0xE2,0x17,0x42,0x42,0x42,0xF7,0x42,0x42,0x42,0x00,0x00,0x0F,0x00,0x00,\n0x08,0x08,0x0F,0x08,0x08,0x00,/*\"茌\",4191*/},{\n\n0x82,0x42,0xE2,0x17,0x42,0x42,0x42,0x47,0xF2,0x42,0x42,0x00,0x00,0x0F,0x00,0x01,\n0x02,0x08,0x08,0x0F,0x00,0x00,/*\"苻\",4192*/},{\n\n0x42,0x42,0xA2,0xA7,0x92,0xCA,0x92,0xA7,0xA2,0x42,0x42,0x00,0x00,0x00,0x02,0x02,\n0x04,0x04,0x0A,0x01,0x00,0x00,/*\"苓\",4193*/},{\n\n0x02,0x02,0xFA,0xAF,0xAA,0xAE,0xAA,0xAF,0xFA,0x82,0x82,0x00,0x08,0x03,0x0A,0x02,\n0x0A,0x02,0x0A,0x02,0x0A,0x0E,/*\"蔦\",4194*/},{\n\n0xF2,0x52,0x52,0x4F,0x4A,0x02,0xF2,0x17,0x12,0x12,0xF2,0x03,0x02,0x02,0x02,0x01,\n0x00,0x0F,0x00,0x00,0x02,0x03,/*\"茚\",4195*/},{\n\n0xF2,0x12,0x0A,0x8F,0xE2,0x02,0xF2,0x17,0x12,0x12,0xF2,0x03,0x02,0x09,0x04,0x03,\n0x00,0x0F,0x00,0x00,0x02,0x03,/*\"茆\",4196*/},{\n\n0x6A,0x24,0x23,0x24,0x2A,0xA0,0x2A,0x24,0x23,0x24,0x6A,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"塋\",4197*/},{\n\n0x3A,0x54,0x53,0x54,0xDA,0x50,0x5A,0x54,0xD3,0x14,0x3A,0x00,0x02,0x02,0x02,0x0F,\n0x02,0x02,0x00,0x03,0x04,0x0E,/*\"煢\",4198*/},{\n\n0x02,0xFA,0xAA,0xAF,0xAA,0xAA,0xEA,0xAF,0xAA,0xBA,0x82,0x00,0x0F,0x04,0x02,0x00,\n0x00,0x01,0x02,0x04,0x08,0x0E,/*\"苠\",4199*/},{\n\n0x42,0x4A,0xAA,0x9F,0x8A,0x8A,0x8A,0xAF,0xAA,0x9A,0x02,0x00,0x00,0x0F,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"苕\",4200*/},{\n\n0x0A,0xEA,0x2A,0x2F,0xFA,0x2A,0xFA,0x2F,0x2A,0xEA,0x0A,0x00,0x0F,0x06,0x05,0x04,\n0x04,0x04,0x05,0x05,0x0F,0x00,/*\"茜\",4201*/},{\n\n0x0A,0xEA,0xAA,0xAF,0xAA,0xFE,0xAA,0xAF,0xAA,0xBA,0x8A,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x06,0x0A,0x09,/*\"荑\",4202*/},{\n\n0x22,0xAA,0xEA,0xAF,0xAA,0x3E,0xAA,0xAF,0xEA,0xAA,0x22,0x0A,0x0A,0x0B,0x06,0x02,\n0x02,0x02,0x0E,0x0B,0x0A,0x0A,/*\"蕘\",4203*/},{\n\n0x82,0xBA,0xEA,0xAF,0xAA,0xFA,0xAA,0xAF,0xEA,0xBA,0x82,0x00,0x02,0x03,0x02,0x02,\n0x0F,0x02,0x02,0x03,0x02,0x00,/*\"蓽\",4204*/},{\n\n0x02,0xC2,0x02,0xF7,0x82,0x82,0x02,0xF7,0x82,0x42,0x22,0x08,0x0F,0x08,0x07,0x04,\n0x04,0x00,0x07,0x08,0x08,0x0E,/*\"茈\",4205*/},{\n\n0x02,0x02,0x7A,0x4F,0x4A,0x4A,0x4A,0x4F,0x7A,0x02,0x02,0x00,0x0F,0x09,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0F,0x00,/*\"莒\",4206*/},{\n\n0x02,0xFA,0x0A,0xAF,0xAA,0xAA,0xAA,0xAF,0x0A,0xFA,0x02,0x00,0x0F,0x00,0x03,0x02,\n0x02,0x02,0x0B,0x08,0x0F,0x00,/*\"茼\",4207*/},{\n\n0x02,0xFA,0x0A,0xEF,0x2A,0x2A,0x2A,0xEF,0x0A,0xFA,0x02,0x00,0x07,0x04,0x05,0x05,\n0x05,0x05,0x05,0x04,0x07,0x00,/*\"茴\",4208*/},{\n\n0x82,0xA2,0x9A,0x97,0x92,0xFA,0x92,0x97,0x92,0x92,0x82,0x04,0x04,0x02,0x02,0x01,\n0x0F,0x01,0x02,0x02,0x04,0x04,/*\"茱\",4209*/},{\n\n0x02,0x92,0xD2,0xB7,0x02,0xA2,0xA2,0xE7,0x92,0x92,0x02,0x08,0x0A,0x04,0x0B,0x08,\n0x0A,0x0A,0x0B,0x0A,0x0A,0x08,/*\"莛\",4210*/},{\n\n0x22,0xAA,0x6A,0xAF,0xBA,0xAA,0xAA,0xAF,0x6A,0xAA,0x22,0x01,0x0E,0x02,0x03,0x0E,\n0x0A,0x0E,0x03,0x0A,0x0E,0x01,/*\"蕎\",4211*/},{\n\n0x42,0x22,0xF7,0x2A,0x22,0x22,0xFA,0x22,0x2F,0x32,0x22,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x00,0x03,0x04,0x08,0x08,/*\"茯\",4212*/},{\n\n0x42,0x22,0xF2,0x0F,0x82,0x92,0x92,0xF7,0x8A,0x8A,0x82,0x00,0x00,0x0F,0x00,0x00,\n0x08,0x08,0x0F,0x08,0x08,0x00,/*\"荏\",4213*/},{\n\n0x42,0x22,0x92,0x4F,0x02,0x82,0x92,0x97,0x92,0x92,0x82,0x02,0x01,0x0F,0x00,0x00,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"荇\",4214*/},{\n\n0x22,0x22,0x52,0x57,0x4A,0xC6,0x4A,0x57,0x52,0x22,0x22,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"荃\",4215*/},{\n\n0x12,0xD2,0xD7,0x4A,0x5A,0xD6,0x5A,0x4A,0xD7,0xD2,0x12,0x00,0x03,0x0E,0x0B,0x0A,\n0x0B,0x0A,0x0B,0x0E,0x03,0x00,/*\"薈\",4216*/},{\n\n0x42,0x22,0xDA,0x57,0x52,0x52,0x52,0xD7,0x12,0x12,0xF2,0x00,0x00,0x0F,0x05,0x05,\n0x05,0x05,0x0F,0x08,0x08,0x07,/*\"荀\",4217*/},{\n\n0x02,0x42,0x22,0x57,0x9A,0x92,0x52,0x57,0x32,0x12,0x02,0x02,0x02,0x0F,0x09,0x09,\n0x09,0x09,0x09,0x09,0x0F,0x00,/*\"茗\",4218*/},{\n\n0xAA,0x6A,0xAF,0xEA,0x1A,0xEE,0x1A,0xEA,0xAF,0x5A,0x8A,0x08,0x07,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"薺\",4219*/},{\n\n0x12,0x92,0x57,0xB2,0x12,0x1A,0x12,0xB2,0x57,0x92,0x12,0x08,0x08,0x08,0x04,0x05,\n0x02,0x05,0x04,0x08,0x08,0x08,/*\"茭\",4220*/},{\n\n0x12,0x92,0xD7,0xB2,0x96,0x9A,0x92,0x92,0xD7,0x92,0x12,0x08,0x08,0x04,0x03,0x00,\n0x00,0x00,0x07,0x08,0x09,0x0C,/*\"茺\",4221*/},{\n\n0x4A,0x92,0x02,0x17,0x12,0x12,0xF2,0x17,0x12,0x12,0x02,0x08,0x04,0x0A,0x08,0x08,\n0x08,0x0F,0x08,0x08,0x08,0x08,/*\"茳\",4222*/},{\n\n0x3A,0x14,0xD3,0x94,0x9A,0xF0,0x9A,0x94,0x93,0x94,0x3A,0x02,0x03,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"犖\",4223*/},{\n\n0xBA,0x94,0x93,0x94,0x1A,0xF0,0x9A,0x14,0x93,0x54,0x3A,0x04,0x04,0x02,0x01,0x08,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"滎\",4224*/},{\n\n0x82,0xAA,0xEA,0xAF,0xAA,0x2A,0xEA,0xAF,0xAA,0xFA,0x02,0x02,0x02,0x06,0x0A,0x02,\n0x0A,0x0A,0x0F,0x02,0x02,0x02,/*\"蕁\",4225*/},{\n\n0x02,0xFA,0xAA,0xAF,0xAA,0xAA,0xAA,0xAF,0xAA,0xFA,0x02,0x00,0x0F,0x08,0x04,0x04,\n0x01,0x02,0x04,0x04,0x0A,0x08,/*\"茛\",4226*/},{\n\n0x22,0xAA,0xAA,0xAF,0xAA,0xFE,0xAA,0xAF,0xAA,0xFA,0x22,0x09,0x0E,0x0A,0x0A,0x0F,\n0x0A,0x0E,0x0B,0x0A,0x0E,0x09,/*\"藎\",4227*/},{\n\n0x02,0x3A,0xEA,0xAF,0xBA,0xAA,0xBA,0xAF,0xEA,0x3A,0x02,0x00,0x00,0x0B,0x06,0x02,\n0x02,0x02,0x06,0x0B,0x00,0x00,/*\"蕒\",4228*/},{\n\n0x82,0x8A,0xEA,0x5F,0x22,0x52,0x72,0xD7,0x4A,0x2A,0x8A,0x00,0x08,0x0F,0x00,0x08,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"蓀\",4229*/},{\n\n0x22,0xB2,0x6A,0x27,0x92,0x02,0x12,0x17,0xF2,0x12,0x12,0x0D,0x01,0x0D,0x01,0x0D,\n0x01,0x08,0x08,0x0F,0x08,0x08,/*\"葒\",4230*/},{\n\n0x22,0xB2,0x6A,0x27,0x92,0x22,0xA2,0x27,0x22,0xFA,0x22,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x00,0x09,0x08,0x0F,0x00,/*\"葤\",4231*/},{\n\n0x42,0x42,0xFA,0x47,0x42,0x22,0x1A,0xD7,0x12,0x52,0x32,0x04,0x04,0x07,0x02,0x0A,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"莰\",4232*/},{\n\n0x62,0x2A,0xAA,0xAF,0xAA,0xBE,0xAA,0xAF,0x2A,0x2A,0x62,0x02,0x02,0x02,0x0A,0x0A,\n0x0E,0x03,0x02,0x02,0x02,0x02,/*\"荸\",4233*/},{\n\n0xF2,0x92,0x97,0xF2,0x42,0x52,0x52,0x7A,0xD7,0x52,0x42,0x0F,0x04,0x04,0x0F,0x01,\n0x05,0x01,0x09,0x0F,0x01,0x01,/*\"蒔\",4234*/},{\n\n0x82,0x82,0xFA,0xAF,0xAA,0xEA,0x8A,0x8F,0xFA,0x82,0x82,0x0F,0x00,0x00,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x00,0x08,0x0F,/*\"萵\",4235*/},{\n\n0x22,0xA2,0x6A,0xAF,0xAA,0xFA,0xAA,0xAF,0x6A,0xA2,0x22,0x01,0x08,0x08,0x04,0x03,\n0x00,0x0A,0x0B,0x0A,0x06,0x01,/*\"莠\",4236*/},{\n\n0x42,0x52,0x52,0xF7,0x4A,0x42,0xFA,0x47,0x4A,0xD2,0x42,0x00,0x02,0x0A,0x0F,0x01,\n0x08,0x05,0x02,0x05,0x08,0x0E,/*\"莪\",4237*/},{\n\n0x82,0x92,0xEA,0xAF,0xAA,0xEA,0xAA,0xAF,0xEA,0x8A,0x82,0x00,0x03,0x02,0x02,0x03,\n0x0A,0x0A,0x0A,0x07,0x02,0x00,/*\"莓\",4238*/},{\n\n0x42,0xE2,0x1A,0xE7,0x02,0x42,0xB2,0x2F,0x22,0xE2,0x22,0x00,0x0F,0x00,0x03,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"莜\",4239*/},{\n\n0x42,0x8A,0x52,0x27,0xF2,0x0A,0x52,0x97,0x1A,0xD2,0x12,0x08,0x04,0x02,0x00,0x0F,\n0x00,0x04,0x05,0x06,0x05,0x04,/*\"蒞\",4240*/},{\n\n0x22,0xA2,0x92,0xB7,0xAA,0xE6,0xAA,0xB7,0x92,0xA2,0x22,0x08,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x08,/*\"荼\",4241*/},{\n\n0x22,0xA2,0x92,0xB7,0xAA,0x26,0xAA,0xB7,0x92,0xA2,0x22,0x00,0x0B,0x06,0x06,0x0B,\n0x00,0x0B,0x06,0x06,0x0B,0x00,/*\"薟\",4242*/},{\n\n0x12,0x32,0xD2,0x97,0xB2,0xD2,0x92,0xCF,0xAA,0x0A,0x0A,0x02,0x02,0x02,0x0A,0x0A,\n0x0E,0x02,0x03,0x02,0x02,0x02,/*\"莩\",4243*/},{\n\n0x12,0x32,0x52,0x17,0xB2,0x52,0x0A,0x0F,0x4A,0x2A,0x0A,0x01,0x09,0x09,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"荽\",4244*/},{\n\n0x2A,0x92,0xEA,0x07,0xD2,0x5A,0xF2,0x57,0xF2,0x5A,0xD2,0x09,0x08,0x07,0x00,0x0F,\n0x09,0x0A,0x0A,0x0B,0x09,0x0F,/*\"蕕\",4245*/},{\n\n0x42,0x2A,0x97,0xEA,0x82,0x62,0x02,0xFA,0x07,0x42,0x22,0x02,0x09,0x08,0x07,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"荻\",4246*/},{\n\n0x82,0x92,0xB7,0xD2,0x92,0x9A,0x92,0xD2,0xB7,0x92,0x82,0x00,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x00,/*\"莘\",4247*/},{\n\n0x32,0x12,0x52,0x57,0x52,0x5A,0x52,0x57,0x52,0x12,0x32,0x09,0x09,0x05,0x03,0x01,\n0x01,0x07,0x09,0x09,0x09,0x0D,/*\"莞\",4248*/},{\n\n0x02,0xF2,0x52,0x57,0x52,0x5A,0x52,0x57,0x52,0xF2,0x02,0x00,0x0F,0x09,0x05,0x05,\n0x01,0x03,0x05,0x05,0x0B,0x08,/*\"莨\",4249*/},{\n\n0x1D,0xEA,0xA9,0xAA,0xBD,0xE8,0xAD,0xAA,0xE9,0x8A,0x9D,0x08,0x03,0x0A,0x02,0x0A,\n0x02,0x0A,0x02,0x0A,0x0A,0x06,/*\"鶯\",4250*/},{\n\n0x8A,0x8A,0xFA,0xAF,0xAA,0xFE,0xAA,0xAF,0xFA,0x8A,0xCA,0x02,0x02,0x06,0x0A,0x02,\n0x0A,0x0A,0x0F,0x02,0x02,0x02,/*\"蓴\",4251*/},{\n\n0x82,0xAA,0xAA,0xAF,0xAA,0xFE,0xAA,0xAF,0xAA,0xAA,0x82,0x00,0x00,0x0F,0x02,0x02,\n0x02,0x02,0x0A,0x0F,0x00,0x00,/*\"菁\",4252*/},{\n\n0x0A,0x0A,0xFE,0xAB,0xAA,0xAA,0xAA,0xAB,0xFE,0x0A,0x0A,0x02,0x0A,0x07,0x02,0x02,\n0x02,0x02,0x02,0x07,0x0A,0x02,/*\"萁\",4253*/},{\n\n0x22,0xA2,0xFA,0xA7,0x22,0xF2,0x92,0x97,0x8A,0x8A,0x82,0x01,0x00,0x0F,0x00,0x09,\n0x07,0x00,0x00,0x0F,0x00,0x00,/*\"菥\",4254*/},{\n\n0x22,0xA2,0xFA,0xA7,0x02,0x42,0x32,0x87,0x02,0x32,0x42,0x01,0x00,0x0F,0x00,0x01,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"菘\",4255*/},{\n\n0x02,0xE2,0xAF,0xAA,0xAA,0xFA,0xAA,0xAA,0xAF,0xE2,0x02,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"堇\",4256*/},{\n\n0x92,0x92,0x52,0x37,0x52,0x5A,0x52,0x37,0x52,0x92,0x92,0x00,0x08,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x08,0x00,/*\"萘\",4257*/},{\n\n0x42,0x52,0x52,0x57,0xFA,0x52,0x52,0x57,0xF2,0x42,0x42,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"萋\",4258*/},{\n\n0x22,0x22,0xFA,0xA7,0x22,0xE2,0xBA,0xA7,0xAA,0xB2,0x22,0x01,0x09,0x0F,0x04,0x03,\n0x08,0x0B,0x04,0x04,0x0B,0x08,/*\"菝\",4259*/},{\n\n0x42,0x42,0xFA,0x57,0x52,0x02,0xF2,0x17,0x12,0xF2,0x02,0x02,0x09,0x0F,0x01,0x02,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"菽\",4260*/},{\n\n0x02,0x82,0xFA,0xAF,0xAA,0xAA,0xAA,0xAF,0xFA,0x82,0x02,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"菖\",4261*/},{\n\n0xE2,0x22,0xFA,0x27,0xE2,0x02,0x82,0x87,0xFA,0xA2,0xA2,0x03,0x00,0x0F,0x02,0x03,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"萜\",4262*/},{\n\n0x02,0xF2,0x52,0x57,0x0A,0xFE,0x02,0x57,0x52,0xF2,0x02,0x08,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x08,/*\"萸\",4263*/},{\n\n0x42,0x22,0xF7,0x5A,0x56,0x52,0xF6,0x5A,0x57,0x52,0x12,0x00,0x00,0x0F,0x05,0x05,\n0x05,0x07,0x05,0x05,0x05,0x04,/*\"萑\",4264*/},{\n\n0x02,0xF2,0x52,0x57,0xDA,0x72,0x52,0x57,0x52,0xF2,0x02,0x04,0x05,0x07,0x05,0x05,\n0x05,0x0F,0x05,0x05,0x05,0x04,/*\"萆\",4265*/},{\n\n0x02,0xFA,0xAA,0xAF,0xFA,0x02,0xFA,0x8F,0xAA,0xAA,0x9A,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x0F,0x00,0x0B,0x04,0x0B,/*\"菔\",4266*/},{\n\n0x82,0x42,0xE7,0x5A,0x52,0xD2,0x52,0x72,0x47,0xC2,0x02,0x08,0x08,0x05,0x05,0x03,\n0x01,0x07,0x09,0x0B,0x09,0x0E,/*\"菟\",4267*/},{\n\n0x22,0xD2,0x4A,0x4F,0x2A,0x0A,0x4A,0x6F,0x5A,0xC2,0x02,0x00,0x0F,0x05,0x05,0x05,\n0x04,0x05,0x05,0x05,0x0F,0x00,/*\"萏\",4268*/},{\n\n0x02,0x12,0x92,0x77,0x92,0x1A,0x92,0x77,0x92,0x12,0x02,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"萃\",4269*/},{\n\n0x22,0xEA,0xB2,0xA7,0xA2,0x42,0x22,0x9F,0x22,0x42,0x82,0x08,0x07,0x08,0x08,0x07,\n0x00,0x02,0x04,0x09,0x00,0x00,/*\"菸\",4270*/},{\n\n0x42,0x8A,0x12,0x07,0xFA,0x4A,0x4A,0x4F,0x4A,0xFA,0x02,0x08,0x04,0x02,0x08,0x0F,\n0x09,0x09,0x09,0x09,0x0F,0x08,/*\"菹\",4271*/},{\n\n0x32,0x52,0x52,0xD7,0x52,0x5A,0x52,0x57,0x52,0x52,0x32,0x04,0x02,0x0F,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"菪\",4272*/},{\n\n0x1A,0x0A,0xEA,0xAF,0xAA,0xAE,0xAA,0xAF,0xEA,0x0A,0x1A,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"菅\",4273*/},{\n\n0x32,0x92,0x72,0x57,0xD2,0x1A,0xD2,0x57,0x52,0xD2,0x32,0x09,0x08,0x05,0x02,0x01,\n0x00,0x07,0x08,0x0A,0x0B,0x0C,/*\"菀\",4274*/},{\n\n0x3A,0x14,0x93,0xD4,0x9A,0x90,0x9A,0x54,0x13,0x14,0x3A,0x00,0x0A,0x06,0x02,0x0B,\n0x0E,0x02,0x02,0x07,0x0A,0x00,/*\"縈\",4275*/},{\n\n0x12,0xD2,0xB2,0x07,0xF2,0x12,0xF2,0x17,0xEA,0x0A,0x02,0x09,0x0F,0x00,0x08,0x07,\n0x00,0x0F,0x0A,0x0C,0x03,0x0C,/*\"菰\",4276*/},{\n\n0xE2,0x0A,0x4A,0x8F,0x0A,0xEA,0x2A,0x9F,0x4A,0x02,0xE2,0x0F,0x08,0x09,0x08,0x0A,\n0x0B,0x08,0x08,0x09,0x08,0x0F,/*\"菡\",4277*/},{\n\n0x8A,0xAA,0xFF,0xAA,0x8A,0x02,0x4A,0x3A,0x8F,0x8A,0x7A,0x0A,0x0A,0x0B,0x06,0x02,\n0x03,0x02,0x06,0x0A,0x0A,0x0A,/*\"葜\",4278*/},{\n\n0x42,0x52,0x57,0xFA,0x52,0x52,0xA2,0x22,0x27,0xFA,0x22,0x08,0x09,0x09,0x07,0x05,\n0x05,0x00,0x09,0x08,0x0F,0x00,/*\"葑\",4279*/},{\n\n0x02,0x12,0xFA,0x57,0x52,0x52,0x52,0x57,0xFA,0x12,0x02,0x01,0x0F,0x09,0x0D,0x0B,\n0x09,0x09,0x0B,0x0D,0x09,0x01,/*\"葚\",4280*/},{\n\n0x22,0xA2,0xFA,0xA7,0x22,0xF2,0x52,0x57,0x52,0x52,0xF2,0x01,0x00,0x0F,0x00,0x01,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"葙\",4281*/},{\n\n0x02,0xF2,0x57,0xD2,0x52,0x52,0x12,0xFA,0x17,0xDA,0x12,0x08,0x07,0x09,0x0B,0x05,\n0x0B,0x08,0x04,0x03,0x04,0x0E,/*\"葳\",4282*/},{\n\n0x02,0xFA,0x0A,0xEF,0xAA,0xEA,0x0A,0xFF,0x0A,0xEE,0x0A,0x08,0x07,0x00,0x0B,0x06,\n0x0B,0x08,0x04,0x03,0x04,0x0E,/*\"蕆\",4283*/},{\n\n0x02,0xBE,0xAA,0xAF,0xAA,0xC2,0x9A,0xB7,0xAA,0xAA,0x32,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"蒈\",4284*/},{\n\n0x22,0x22,0xE7,0xBA,0xAA,0xAA,0xAA,0xBA,0xE7,0x22,0x22,0x04,0x04,0x07,0x04,0x04,\n0x02,0x02,0x02,0x0F,0x02,0x02,/*\"葺\",4285*/},{\n\n0x22,0xE2,0xBA,0xAF,0xAA,0xBE,0xAA,0xAF,0xBA,0xE2,0x22,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"蕢\",4286*/},{\n\n0x02,0xFA,0xAA,0xAF,0xAA,0xFA,0xAA,0xAF,0xAA,0xFA,0x02,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"葸\",4287*/},{\n\n0x82,0xBA,0xAA,0xAF,0xBA,0x82,0xBA,0xAF,0xAA,0xBA,0x82,0x00,0x00,0x03,0x02,0x02,\n0x02,0x02,0x0A,0x0A,0x06,0x00,/*\"萼\",4288*/},{\n\n0x82,0x42,0xE2,0x1F,0x82,0xBA,0xAA,0xEF,0xAA,0xBA,0x82,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"葆\",4289*/},{\n\n0xF2,0x9A,0x92,0xF7,0x02,0xF2,0x92,0xF7,0x92,0xF2,0x02,0x0F,0x04,0x04,0x0F,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"葩\",4290*/},{\n\n0x8A,0x8A,0xEA,0xAF,0xAA,0xAE,0xAA,0xAF,0xEA,0x8A,0x8A,0x01,0x02,0x02,0x02,0x0A,\n0x0E,0x02,0x02,0x02,0x02,0x01,/*\"葶\",4291*/},{\n\n0x42,0x42,0xF2,0x57,0x52,0xFA,0x52,0x57,0xF2,0x42,0x42,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"蔞\",4292*/},{\n\n0x42,0x8A,0x12,0x07,0xF2,0x12,0xD2,0x57,0xCA,0x2A,0x02,0x08,0x04,0x02,0x08,0x07,\n0x00,0x0F,0x04,0x01,0x06,0x09,/*\"蒎\",4293*/},{\n\n0x1A,0xEA,0xAF,0xAA,0xAA,0xAE,0xAA,0xAA,0xAF,0xEA,0x1A,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"萱\",4294*/},{\n\n0x02,0xFA,0xAA,0xAF,0xBA,0x02,0xAA,0xAF,0xAA,0xBA,0x02,0x00,0x0F,0x02,0x02,0x02,\n0x08,0x0B,0x04,0x04,0x0B,0x08,/*\"葭\",4295*/},{\n\n0x22,0x22,0xAA,0xEF,0xBA,0xAE,0xAA,0x6F,0xAA,0x22,0x22,0x01,0x0B,0x0A,0x06,0x02,\n0x0F,0x02,0x02,0x06,0x0B,0x01,/*\"蓁\",4296*/},{\n\n0x22,0x22,0xAA,0xAF,0xEA,0x3E,0xAA,0x77,0x2A,0x26,0xA2,0x01,0x01,0x0E,0x0A,0x0A,\n0x0F,0x0B,0x0B,0x0F,0x01,0x01,/*\"蓍\",4297*/},{\n\n0x02,0xFA,0x2A,0x2F,0xEA,0xAA,0x2A,0x6F,0xAA,0xEA,0xAA,0x04,0x03,0x02,0x06,0x0A,\n0x02,0x02,0x0A,0x0F,0x02,0x02,/*\"蓐\",4298*/},{\n\n0x22,0xA2,0xFA,0xAF,0xAA,0xBA,0xAA,0xAF,0x7A,0xA2,0x22,0x09,0x00,0x0B,0x02,0x0A,\n0x03,0x0A,0x02,0x0A,0x0E,0x01,/*\"驀\",4299*/},{\n\n0x02,0xFA,0x0A,0xAF,0x6A,0x3A,0x6A,0xAF,0x0A,0xFA,0x02,0x08,0x05,0x01,0x05,0x0B,\n0x0D,0x09,0x0D,0x01,0x05,0x08,/*\"蒽\",4300*/},{\n\n0x42,0xE2,0x1A,0x97,0xB2,0xD2,0x92,0x9F,0xD2,0xB2,0x92,0x00,0x0F,0x00,0x00,0x0E,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"蓓\",4301*/},{\n\n0x12,0x92,0xAA,0xB7,0xAA,0x22,0xA2,0xB7,0xAA,0x92,0x12,0x00,0x04,0x05,0x0A,0x0F,\n0x00,0x04,0x05,0x0A,0x0F,0x00,/*\"蓊\",4302*/},{\n\n0x8A,0x8A,0xEA,0xAF,0xAA,0xAE,0xAA,0xAF,0xEA,0x8A,0x8A,0x0F,0x00,0x00,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x00,0x08,0x0F,/*\"蒿\",4303*/},{\n\n0x22,0x42,0xF2,0x97,0x52,0x76,0xDA,0x57,0x52,0x52,0x12,0x0A,0x05,0x0B,0x09,0x05,\n0x03,0x01,0x03,0x05,0x09,0x09,/*\"蒺\",4304*/},{\n\n0xD2,0xB2,0xDA,0xB7,0xD2,0x22,0xF2,0xAF,0xF2,0xA2,0x22,0x0E,0x02,0x07,0x0A,0x0E,\n0x00,0x0F,0x0A,0x0F,0x0A,0x08,/*\"蘺\",4305*/},{\n\n0x62,0xAA,0xAF,0xBA,0xEA,0xAE,0xAA,0xBA,0xAF,0xAA,0x62,0x00,0x08,0x04,0x03,0x02,\n0x02,0x02,0x0A,0x0A,0x06,0x00,/*\"蒡\",4306*/},{\n\n0x52,0x52,0x57,0x5A,0xF2,0x52,0xF2,0x5A,0x57,0xF2,0x52,0x08,0x05,0x03,0x01,0x0F,\n0x01,0x0F,0x01,0x03,0x05,0x08,/*\"蒹\",4307*/},{\n\n0xAA,0x32,0xE2,0x37,0xAA,0x02,0xF2,0x57,0x52,0x52,0xF2,0x09,0x05,0x03,0x01,0x09,\n0x04,0x03,0x01,0x01,0x09,0x0F,/*\"蒴\",4308*/},{\n\n0x4A,0x92,0x07,0xFA,0xAA,0xAE,0xAA,0xAA,0xAF,0xFA,0x02,0x08,0x04,0x00,0x0F,0x08,\n0x04,0x01,0x02,0x04,0x0A,0x09,/*\"蒗\",4309*/},{\n\n0x9D,0x8A,0x49,0xCA,0xAD,0x98,0xAD,0xCA,0x49,0x8A,0x9D,0x08,0x0A,0x0E,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0E,0x0A,0x08,/*\"鎣\",4310*/},{\n\n0x8A,0xAA,0xCA,0xAF,0x9A,0x02,0xEA,0xAF,0xBA,0xAA,0xEA,0x00,0x08,0x0F,0x00,0x01,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"蕷\",4311*/},{\n\n0x02,0xD2,0x57,0xFA,0x52,0xD2,0x42,0x3A,0x97,0x12,0x72,0x08,0x05,0x03,0x0F,0x03,\n0x05,0x08,0x06,0x01,0x06,0x08,/*\"蔌\",4312*/},{\n\n0x62,0xBA,0xAA,0xAF,0xBA,0xAA,0xBA,0xAF,0xAA,0xBA,0x62,0x00,0x0C,0x0B,0x0A,0x06,\n0x0A,0x02,0x06,0x08,0x08,0x0C,/*\"甍\",4313*/},{\n\n0xF2,0x0A,0x02,0xF7,0x5A,0x56,0x52,0xF7,0x02,0x0A,0xFA,0x09,0x09,0x08,0x05,0x03,\n0x01,0x07,0x09,0x08,0x09,0x0D,/*\"蔸\",4314*/},{\n\n0x42,0xA2,0xD2,0x2F,0x42,0x72,0x42,0x7F,0x52,0x52,0x42,0x01,0x00,0x0F,0x00,0x08,\n0x06,0x08,0x0F,0x0A,0x0A,0x08,/*\"蓰\",4315*/},{\n\n0xA2,0x92,0xAA,0x27,0xAA,0x92,0xA2,0xF7,0x2E,0xE2,0x22,0x0B,0x06,0x0B,0x00,0x0B,\n0x06,0x0B,0x05,0x02,0x05,0x08,/*\"蘞\",4316*/},{\n\n0x22,0xEA,0xB2,0xA7,0x22,0x9A,0x72,0xD7,0x52,0x52,0x12,0x08,0x07,0x08,0x0F,0x01,\n0x09,0x05,0x03,0x05,0x09,0x09,/*\"蔟\",4317*/},{\n\n0xFA,0x2A,0x2F,0xBA,0xC2,0x82,0xC2,0xBA,0xAF,0x2A,0xFA,0x0F,0x02,0x01,0x0F,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x00,0x0F,/*\"藺\",4318*/},{\n\n0x22,0x4A,0x92,0x07,0xFA,0xAA,0xAA,0xAF,0xAA,0xEA,0x8A,0x0A,0x0B,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"蕖\",4319*/},{\n\n0x9A,0xAA,0xAA,0xAF,0x8A,0x0E,0x8A,0xFF,0xAA,0xAA,0x1A,0x08,0x07,0x00,0x07,0x08,\n0x08,0x0D,0x0A,0x0A,0x0D,0x08,/*\"蔻\",4320*/},{\n\n0x9A,0x4A,0xEA,0x1F,0xAA,0xAE,0xEA,0xAF,0xAA,0xAA,0x1A,0x00,0x00,0x0F,0x00,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"蓿\",4321*/},{\n\n0x02,0x5A,0x2A,0x8F,0xBA,0x42,0xDA,0xAF,0x0A,0x7A,0x02,0x01,0x09,0x09,0x0A,0x0A,\n0x0A,0x05,0x04,0x05,0x01,0x01,/*\"蓼\",4322*/},{\n\n0x82,0x8A,0xFA,0xAF,0xAA,0xFE,0xAA,0xAF,0xFA,0x8A,0xC2,0x04,0x02,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x05,/*\"蕙\",4323*/},{\n\n0x0A,0xEA,0xAA,0xAF,0xFA,0xAA,0xFA,0xAF,0xAA,0xEA,0x0A,0x04,0x04,0x07,0x04,0x04,\n0x0D,0x06,0x04,0x07,0x04,0x04,/*\"蕈\",4324*/},{\n\n0x02,0xFA,0x5A,0x6F,0xCA,0x6A,0x5A,0x8F,0x7A,0x4A,0xCA,0x08,0x07,0x0B,0x0A,0x07,\n0x02,0x0B,0x04,0x03,0x04,0x08,/*\"蕨\",4325*/},{\n\n0x4A,0xAA,0x5A,0xEF,0x2A,0x42,0xB2,0xA7,0xFA,0xA2,0xA2,0x05,0x02,0x09,0x0F,0x01,\n0x06,0x0A,0x0A,0x0B,0x0A,0x0A,/*\"蕤\",4326*/},{\n\n0x42,0xC2,0x7A,0x4F,0xDA,0x6A,0x4A,0x4F,0x7A,0x42,0x42,0x04,0x07,0x05,0x05,0x0F,\n0x02,0x09,0x0B,0x05,0x0B,0x08,/*\"蕞\",4327*/},{\n\n0x42,0xF2,0x57,0x52,0xF2,0x42,0x42,0xFA,0x47,0x52,0x42,0x04,0x07,0x05,0x05,0x0F,\n0x02,0x08,0x05,0x02,0x05,0x0E,/*\"蕺\",4328*/},{\n\n0x62,0x3A,0xEA,0xAF,0xBA,0xAA,0xBA,0xAF,0xEA,0x3A,0x62,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"瞢\",4329*/},{\n\n0x22,0xAA,0xFA,0xAF,0xAA,0xFA,0xAA,0xAF,0xF6,0xA2,0x22,0x01,0x00,0x0F,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0F,0x00,0x01,/*\"蕃\",4330*/},{\n\n0x3A,0xEA,0xBA,0xE7,0xBA,0xEA,0x3A,0xF7,0x52,0xD2,0x4A,0x02,0x03,0x02,0x0F,0x02,\n0x03,0x0A,0x07,0x00,0x0F,0x00,/*\"蘄\",4331*/},{\n\n0x82,0xFA,0xAF,0xAA,0xAA,0x82,0x22,0xFA,0x27,0xFA,0x22,0x04,0x06,0x05,0x04,0x06,\n0x04,0x09,0x05,0x01,0x05,0x09,/*\"蕻\",4332*/},{\n\n0x92,0x72,0x52,0xD7,0xA2,0xA2,0xFA,0x07,0xFA,0xA2,0xA2,0x08,0x05,0x02,0x09,0x0A,\n0x0A,0x0F,0x08,0x0F,0x0A,0x0A,/*\"薤\",4333*/},{\n\n0x62,0xBA,0xAA,0xAF,0xBA,0xAA,0xBA,0xAF,0xAA,0xBA,0x62,0x08,0x0A,0x0E,0x0B,0x06,\n0x00,0x07,0x0C,0x0A,0x09,0x0C,/*\"薨\",4334*/},{\n\n0x92,0xCA,0x32,0xA7,0xBA,0xA2,0x32,0xC7,0x3A,0xE2,0x22,0x00,0x0F,0x08,0x06,0x02,\n0x0E,0x08,0x05,0x02,0x05,0x08,/*\"薇\",4335*/},{\n\n0x22,0xEA,0x3A,0x2F,0x2A,0x6E,0xAA,0x2F,0x3A,0xEA,0x22,0x08,0x05,0x01,0x05,0x09,\n0x0B,0x09,0x0D,0x01,0x05,0x08,/*\"薏\",4336*/},{\n\n0xCA,0xBA,0x8A,0x6F,0x4A,0xEE,0xBA,0xAF,0xFA,0xAA,0xAA,0x02,0x0B,0x06,0x03,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"蕹\",4337*/},{\n\n0x42,0xF2,0x57,0xFA,0x52,0xF2,0x42,0xBA,0x27,0xE2,0x22,0x09,0x0B,0x05,0x05,0x05,\n0x0B,0x09,0x05,0x02,0x05,0x08,/*\"藪\",4338*/},{\n\n0x02,0xF2,0x52,0x57,0x72,0x02,0x92,0xB7,0xDA,0xB2,0x92,0x04,0x03,0x0F,0x09,0x0F,\n0x00,0x00,0x02,0x0F,0x02,0x00,/*\"薜\",4339*/},{\n\n0x22,0xE2,0x3A,0xE7,0x02,0xFA,0x2A,0xEF,0xAA,0x6A,0xAA,0x04,0x02,0x01,0x0A,0x04,\n0x03,0x06,0x02,0x0A,0x0F,0x02,/*\"薅\",4340*/},{\n\n0x8A,0xAA,0xEF,0xAA,0xAA,0xBE,0xAA,0xAA,0xEF,0xAA,0x8A,0x09,0x08,0x0A,0x0B,0x0A,\n0x0E,0x0A,0x0B,0x0A,0x08,0x09,/*\"薹\",4341*/},{\n\n0x62,0xAA,0xEA,0xAF,0xAA,0xFA,0xAA,0xAF,0xEA,0xAA,0x62,0x00,0x0E,0x02,0x02,0x0E,\n0x03,0x0E,0x02,0x0A,0x0E,0x00,/*\"薷\",4342*/},{\n\n0x22,0xEA,0x2A,0xAF,0x2A,0xFA,0x2A,0xAF,0x2A,0xEA,0x22,0x04,0x0D,0x05,0x05,0x0D,\n0x07,0x0D,0x05,0x05,0x0D,0x04,/*\"薰\",4343*/},{\n\n0x12,0xEE,0xAA,0xEF,0xBA,0xE2,0x2A,0xB7,0xE2,0xB2,0x2A,0x08,0x03,0x0A,0x03,0x0A,\n0x03,0x0A,0x02,0x0F,0x02,0x02,/*\"蘚\",4344*/},{\n\n0xEA,0x2A,0x3A,0xEF,0xAA,0xAE,0xAA,0xEF,0x3A,0xAA,0xEA,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"藁\",4345*/},{\n\n0xA2,0x6A,0x2F,0xFA,0xAA,0x62,0x9A,0x52,0x37,0x92,0xF2,0x02,0x02,0x09,0x05,0x0A,\n0x0F,0x02,0x05,0x09,0x02,0x02,/*\"藜\",4346*/},{\n\n0x62,0x2A,0xAA,0xEF,0xAA,0xFA,0xAA,0xEF,0xAA,0xAA,0x62,0x02,0x01,0x0F,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"藿\",4347*/},{\n\n0x4A,0xD2,0x02,0xE7,0x22,0xBE,0x6A,0xAF,0x2A,0xAA,0x62,0x08,0x07,0x04,0x0B,0x09,\n0x0A,0x0D,0x0F,0x09,0x0A,0x08,/*\"蘧\",4348*/},{\n\n0x92,0xCA,0x27,0xF2,0xAA,0xEE,0xBA,0xE2,0x4F,0xCA,0x4A,0x00,0x0F,0x02,0x0B,0x06,\n0x03,0x06,0x0B,0x0A,0x0F,0x00,/*\"蘅\",4349*/},{\n\n0x12,0xFE,0xAA,0xFF,0xAA,0xFA,0x12,0xAF,0x4A,0xBA,0x0A,0x00,0x0A,0x06,0x03,0x0A,\n0x0E,0x02,0x02,0x07,0x0A,0x01,/*\"蘩\",4350*/},{\n\n0x0B,0xFE,0xAB,0xAE,0xBB,0xE0,0x12,0x5A,0xF3,0x5A,0x12,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"櫱\",4351*/},{\n\n0x02,0xFA,0xAF,0x6A,0xFA,0xAA,0x4E,0xAA,0xFF,0x6A,0xAA,0x08,0x07,0x00,0x05,0x05,\n0x0F,0x00,0x0F,0x05,0x05,0x00,/*\"蘼\",4352*/},{\n\n0x40,0x40,0x40,0xFE,0x40,0x40,0x40,0xFE,0x40,0x40,0x40,0x00,0x08,0x06,0x01,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"廾\",4353*/},{\n\n0x12,0x0A,0x22,0x9E,0x02,0x03,0x22,0xBE,0x02,0x0A,0x12,0x01,0x09,0x05,0x03,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"弈\",4354*/},{\n\n0x24,0x24,0xD4,0x14,0x0C,0xC7,0x0C,0x14,0xD4,0x24,0x24,0x08,0x04,0x03,0x00,0x00,\n0x07,0x00,0x00,0x0F,0x00,0x00,/*\"夼\",4355*/},{\n\n0x12,0xF2,0x2A,0x2A,0xE6,0xA3,0xA6,0xAA,0xEA,0x32,0x12,0x00,0x0F,0x08,0x0E,0x0A,\n0x0E,0x08,0x0E,0x0A,0x0E,0x08,/*\"奩\",4356*/},{\n\n0x12,0x12,0xFA,0x56,0x52,0x53,0x52,0x56,0xFA,0x12,0x12,0x04,0x04,0x07,0x05,0x05,\n0x05,0x05,0x05,0x0F,0x02,0x02,/*\"耷\",4357*/},{\n\n0x24,0x14,0x44,0x3C,0x05,0x86,0x44,0x7C,0x04,0x14,0x24,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"奕\",4358*/},{\n\n0x00,0x42,0x56,0x5A,0x72,0xD6,0x49,0x49,0x65,0x41,0x00,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"奚\",4359*/},{\n\n0x50,0x36,0x14,0x7F,0x00,0xA4,0x24,0x3F,0x24,0x24,0x04,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"奘\",4360*/},{\n\n0x4A,0xD6,0x53,0x56,0x4A,0x08,0xF4,0x97,0xF4,0x04,0xFC,0x00,0x01,0x09,0x0F,0x00,\n0x00,0x07,0x08,0x08,0x09,0x0D,/*\"匏\",4361*/},{\n\n0x08,0x08,0x08,0xE8,0x1F,0x08,0xF8,0x08,0x08,0x08,0x08,0x08,0x04,0x03,0x00,0x00,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"尢\",4362*/},{\n\n0x08,0xFF,0x08,0xF8,0x08,0x08,0x27,0x44,0x04,0xFC,0x00,0x08,0x07,0x00,0x07,0x08,\n0x08,0x08,0x0A,0x0A,0x09,0x0C,/*\"尥\",4363*/},{\n\n0x08,0xFF,0x08,0xF8,0x08,0x08,0xF4,0x03,0xF4,0x08,0x08,0x08,0x07,0x00,0x07,0x08,\n0x0A,0x09,0x08,0x0B,0x08,0x0C,/*\"尬\",4364*/},{\n\n0x08,0xFF,0x08,0xF8,0x08,0xFF,0x55,0xF7,0x5C,0xC7,0x14,0x08,0x07,0x00,0x07,0x09,\n0x09,0x09,0x09,0x09,0x09,0x0D,/*\"尷\",4365*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x0F,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"扌\",4366*/},{\n\n0x88,0xFF,0x48,0x00,0xFF,0x49,0x7F,0x00,0x7F,0x49,0xFF,0x08,0x0F,0x00,0x00,0x0F,\n0x00,0x00,0x00,0x00,0x08,0x0F,/*\"捫\",4367*/},{\n\n0x88,0xFF,0x48,0x82,0xFA,0xAA,0xAA,0xFF,0xAA,0xFA,0x82,0x08,0x0F,0x00,0x02,0x06,\n0x0A,0x02,0x0A,0x0F,0x02,0x02,/*\"摶\",4368*/},{\n\n0x88,0xFF,0x48,0x00,0xFC,0x24,0x24,0xFF,0x24,0x24,0xFC,0x08,0x0F,0x00,0x00,0x03,\n0x01,0x01,0x0F,0x01,0x01,0x03,/*\"抻\",4369*/},{\n\n0x88,0x88,0xFF,0x48,0x10,0xFC,0x03,0x48,0x88,0xFF,0x08,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x00,0x00,0x08,0x0F,0x00,/*\"拊\",4370*/},{\n\n0x88,0x88,0xFF,0x48,0x00,0x8C,0xEA,0x89,0x88,0xEC,0x98,0x00,0x08,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x00,0x0F,0x00,/*\"拚\",4371*/},{\n\n0x88,0xFF,0x48,0x38,0xE7,0x30,0x08,0xFF,0x08,0x08,0xF8,0x08,0x0F,0x00,0x03,0x02,\n0x0B,0x06,0x01,0x08,0x08,0x07,/*\"拗\",4372*/},{\n\n0x88,0x88,0xFF,0x48,0x04,0xA4,0xA4,0xBF,0xA4,0xA4,0x04,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"拮\",4373*/},{\n\n0x88,0xFF,0x48,0x00,0xA8,0x9A,0xEE,0xAA,0xE9,0x99,0xA8,0x08,0x0F,0x00,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"撟\",4374*/},{\n\n0x88,0xFF,0x48,0x04,0x9B,0xC0,0xA4,0x9B,0x80,0x84,0x1B,0x08,0x0F,0x00,0x09,0x08,\n0x0A,0x04,0x04,0x02,0x01,0x00,/*\"拶\",4375*/},{\n\n0x88,0xFF,0x48,0x00,0xF0,0x97,0x95,0xF5,0x95,0x97,0xF0,0x08,0x0F,0x00,0x00,0x07,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"挹\",4376*/},{\n\n0x88,0xFF,0x48,0x00,0x4A,0x52,0x46,0x4A,0x41,0xE9,0x45,0x08,0x0F,0x00,0x00,0x00,\n0x01,0x02,0x00,0x08,0x0F,0x00,/*\"捋\",4377*/},{\n\n0x88,0xFF,0x48,0x00,0xAA,0xEA,0xBE,0xAA,0xAA,0xBE,0x08,0x08,0x0F,0x00,0x01,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"捃\",4378*/},{\n\n0x84,0xFF,0x44,0x48,0x29,0x19,0xCF,0x09,0x19,0x29,0x48,0x08,0x0F,0x00,0x04,0x02,\n0x08,0x0F,0x01,0x06,0x01,0x06,/*\"掭\",4379*/},{\n\n0x88,0xFF,0x48,0x02,0xFE,0x52,0xFE,0x02,0xFE,0x32,0xCE,0x08,0x0F,0x00,0x02,0x03,\n0x02,0x0F,0x01,0x0F,0x02,0x01,/*\"揶\",4380*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x42,0x52,0x52,0x7E,0x52,0x52,0x08,0x0F,0x00,0x08,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"捱\",4381*/},{\n\n0x88,0x88,0xFF,0x48,0xA4,0x94,0xAC,0xA7,0xAC,0x94,0xA4,0x00,0x08,0x0F,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"捺\",4382*/},{\n\n0x88,0xFF,0x48,0x10,0xDA,0x56,0x53,0xD2,0x16,0xFA,0x10,0x08,0x0F,0x00,0x00,0x07,\n0x02,0x02,0x0B,0x08,0x0F,0x00,/*\"掎\",4383*/},{\n\n0x88,0xFF,0x48,0x00,0xFF,0xA9,0xE9,0x1F,0xE9,0x0B,0xFF,0x08,0x0F,0x00,0x00,0x0F,\n0x0A,0x0A,0x0C,0x0B,0x0D,0x0F,/*\"摑\",4384*/},{\n\n0x88,0xFF,0x48,0x00,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x00,0x08,0x0F,0x00,0x02,0x03,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"捭\",4385*/},{\n\n0x88,0xFF,0x48,0x00,0x54,0x43,0xFA,0x42,0x52,0x02,0xFE,0x08,0x0F,0x00,0x00,0x02,\n0x01,0x07,0x01,0x0A,0x08,0x07,/*\"掬\",4386*/},{\n\n0x88,0x88,0xFF,0x48,0x20,0xAA,0xB2,0xA3,0xB2,0xAA,0x20,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"掊\",4387*/},{\n\n0x88,0xFF,0x48,0x00,0xFC,0x94,0x95,0xF6,0x94,0xD4,0x9C,0x08,0x0F,0x08,0x04,0x0B,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"捩\",4388*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x0A,0xEA,0xAB,0xAA,0xAA,0xEE,0x08,0x0F,0x00,0x08,0x07,\n0x00,0x0F,0x02,0x02,0x0A,0x0F,/*\"掮\",4389*/},{\n\n0x88,0x88,0xFF,0x48,0x04,0xDF,0x55,0xDF,0x55,0xDF,0x04,0x00,0x08,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x07,0x0B,0x00,/*\"摜\",4390*/},{\n\n0x88,0x88,0xFF,0x48,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x00,0x08,0x0F,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"揲\",4391*/},{\n\n0x88,0x88,0xFF,0x48,0x12,0xEA,0xA6,0xBF,0xA6,0xEA,0x12,0x00,0x08,0x0F,0x00,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"揸\",4392*/},{\n\n0x88,0x88,0xFF,0x48,0xFF,0x81,0xBF,0xEB,0xAB,0xBF,0x81,0x00,0x08,0x0F,0x00,0x0F,\n0x08,0x0D,0x0A,0x0A,0x0D,0x08,/*\"揠\",4393*/},{\n\n0x88,0xFF,0x48,0xA4,0x2A,0xF9,0xAA,0x10,0x0F,0xC4,0x1C,0x08,0x0F,0x00,0x08,0x09,\n0x07,0x04,0x08,0x06,0x01,0x0E,/*\"撳\",4394*/},{\n\n0x84,0xFF,0x44,0xE8,0xA4,0xAA,0xE9,0x0A,0xC4,0x08,0xE8,0x08,0x0F,0x00,0x0F,0x02,\n0x0A,0x0F,0x00,0x03,0x08,0x0F,/*\"揄\",4395*/},{\n\n0x88,0xFF,0x48,0x12,0xD6,0x5A,0x53,0x52,0x5A,0xD6,0x12,0x08,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"揞\",4396*/},{\n\n0x88,0xFF,0x48,0x06,0xEA,0xAA,0xAB,0xAA,0xAA,0xEA,0x06,0x08,0x0F,0x00,0x08,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"揎\",4397*/},{\n\n0x84,0xFF,0x44,0x00,0xFF,0x2D,0xF5,0x25,0x25,0xF5,0x2F,0x08,0x0F,0x00,0x04,0x03,\n0x09,0x07,0x01,0x01,0x0F,0x01,/*\"摒\",4398*/},{\n\n0x88,0xFF,0x48,0x00,0x4A,0x32,0x4E,0xC0,0x4F,0x32,0x49,0x08,0x0F,0x00,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"揆\",4399*/},{\n\n0x88,0xFF,0x48,0x00,0xAC,0x6B,0xAA,0x2A,0x3A,0xA6,0x20,0x08,0x0F,0x00,0x08,0x0A,\n0x05,0x0A,0x0F,0x01,0x06,0x08,/*\"掾\",4400*/},{\n\n0x88,0xFF,0x48,0xFC,0x04,0xD4,0x7F,0xD5,0x55,0xD5,0x6C,0x08,0x0F,0x04,0x03,0x08,\n0x05,0x09,0x0B,0x0D,0x01,0x0C,/*\"攄\",4401*/},{\n\n0x88,0xFF,0x48,0x00,0x7F,0x65,0xD5,0x4F,0x55,0x65,0x7F,0x08,0x0F,0x00,0x04,0x03,\n0x00,0x06,0x09,0x0C,0x01,0x06,/*\"摁\",4402*/},{\n\n0x84,0xFF,0x44,0xFE,0x02,0xF2,0x52,0xFF,0x55,0x15,0xB1,0x08,0x0F,0x08,0x07,0x02,\n0x09,0x06,0x02,0x07,0x09,0x0D,/*\"搋\",4403*/},{\n\n0x88,0xFF,0x48,0x44,0x55,0xFE,0x54,0xFE,0x55,0xF4,0x44,0x08,0x0F,0x00,0x05,0x03,\n0x0F,0x01,0x0F,0x03,0x05,0x08,/*\"搛\",4404*/},{\n\n0x88,0xFF,0x48,0xE1,0x8A,0xF8,0x8A,0xE1,0xFE,0x92,0xFE,0x08,0x0F,0x00,0x08,0x04,\n0x03,0x00,0x08,0x07,0x08,0x0F,/*\"搠\",4405*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0xAA,0xAA,0xFA,0xAA,0xFA,0xAE,0x08,0x0F,0x00,0x08,0x07,\n0x00,0x0F,0x04,0x03,0x04,0x0A,/*\"搌\",4406*/},{\n\n0x88,0xFF,0x48,0x00,0xB9,0x29,0xEF,0x00,0xB9,0x29,0xEF,0x08,0x0F,0x00,0x00,0x0A,\n0x09,0x07,0x00,0x0A,0x09,0x07,/*\"搦\",4407*/},{\n\n0x88,0x88,0xFF,0x48,0xB0,0x5B,0xB5,0x05,0xB5,0x5B,0xB0,0x00,0x08,0x0F,0x00,0x0A,\n0x06,0x02,0x0F,0x02,0x06,0x0A,/*\"搡\",4408*/},{\n\n0x88,0xFF,0x48,0x00,0x5F,0x75,0xD5,0x5F,0x35,0x95,0x1F,0x08,0x0F,0x00,0x08,0x05,\n0x01,0x09,0x0F,0x01,0x05,0x09,/*\"摞\",4409*/},{\n\n0x84,0xFF,0x44,0x00,0x5F,0x35,0xDF,0x00,0x5F,0x35,0x5F,0x08,0x0F,0x00,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"攖\",4410*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x22,0xFA,0x23,0x22,0xFA,0x22,0x08,0x0F,0x08,0x04,0x0B,\n0x04,0x09,0x05,0x09,0x05,0x08,/*\"摭\",4411*/},{\n\n0x88,0xFF,0x48,0xF9,0xAD,0xFB,0x10,0xEC,0x0B,0xF8,0x08,0x08,0x0F,0x02,0x03,0x02,\n0x0F,0x09,0x04,0x03,0x04,0x08,/*\"撖\",4412*/},{\n\n0x84,0xFF,0x44,0x00,0xD5,0x49,0x5F,0x60,0x55,0x49,0xDF,0x08,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"摺\",4413*/},{\n\n0x88,0xFF,0x48,0x00,0xA4,0xBF,0xA4,0x00,0xFA,0xAE,0xFA,0x08,0x0F,0x00,0x00,0x0F,\n0x04,0x0F,0x00,0x0B,0x06,0x0B,/*\"擷\",4414*/},{\n\n0x88,0x88,0xFF,0x48,0x44,0xBE,0xD5,0xBD,0xD7,0xBC,0x40,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"擼\",4415*/},{\n\n0x88,0xFF,0x48,0x02,0xFA,0xAB,0xDE,0xCA,0xBE,0xAB,0xFA,0x08,0x0F,0x00,0x00,0x02,\n0x06,0x0A,0x02,0x0A,0x0F,0x02,/*\"撙\",4416*/},{\n\n0x88,0x88,0xFF,0x48,0x06,0xEA,0x56,0x03,0x56,0xFA,0x06,0x00,0x08,0x0F,0x00,0x00,\n0x0F,0x05,0x0F,0x05,0x07,0x08,/*\"攛\",4417*/},{\n\n0x88,0xFF,0x48,0xFA,0xAF,0xFA,0x04,0x12,0xF1,0x12,0x04,0x08,0x0F,0x00,0x02,0x0F,\n0x02,0x01,0x01,0x0F,0x01,0x01,/*\"擀\",4418*/},{\n\n0x88,0x88,0xFF,0x48,0x17,0xD5,0x57,0x55,0x57,0xD5,0x17,0x00,0x08,0x0F,0x00,0x08,\n0x05,0x0F,0x09,0x03,0x05,0x0A,/*\"擐\",4419*/},{\n\n0x88,0xFF,0x48,0x00,0xFE,0x92,0x9E,0x40,0x55,0xE6,0x54,0x08,0x0F,0x00,0x01,0x0F,\n0x04,0x0F,0x00,0x02,0x0F,0x02,/*\"擗\",4420*/},{\n\n0x88,0xFF,0x48,0xE0,0xBE,0xAB,0xEA,0xAA,0xBE,0xE0,0x00,0x08,0x0F,0x02,0x0B,0x06,\n0x02,0x03,0x02,0x0E,0x03,0x02,/*\"擤\",4421*/},{\n\n0x88,0xFF,0x48,0x20,0xFB,0xA5,0xAF,0xA0,0xEB,0xB5,0xAF,0x08,0x0F,0x00,0x00,0x0F,\n0x0A,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"擢\",4422*/},{\n\n0x88,0xFF,0x48,0x80,0xCD,0x75,0x45,0xDF,0x65,0x55,0x4D,0x08,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x07,0x05,0x05,0x04,/*\"攉\",4423*/},{\n\n0x88,0xFF,0x48,0x84,0xFB,0x9E,0xAA,0xDC,0xAB,0xFE,0x82,0x08,0x0F,0x00,0x02,0x09,\n0x06,0x0B,0x0E,0x02,0x05,0x0A,/*\"攥\",4424*/},{\n\n0x88,0x88,0xFF,0x48,0x62,0xAE,0xEA,0xBF,0xEA,0xAE,0x62,0x00,0x08,0x0F,0x00,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"攮\",4425*/},{\n\n0x10,0x10,0x10,0x10,0x3F,0xD0,0x08,0x09,0x0A,0x08,0x08,0x00,0x00,0x00,0x00,0x00,\n0x00,0x01,0x02,0x04,0x08,0x0F,/*\"弋\",4426*/},{\n\n0x08,0x08,0x28,0x48,0x08,0x08,0x08,0xFF,0x08,0x09,0x0A,0x07,0x00,0x07,0x08,0x0C,\n0x01,0x06,0x00,0x03,0x04,0x0E,/*\"忒\",4427*/},{\n\n0x48,0xE8,0x48,0x48,0x48,0xE8,0x48,0xFF,0x08,0x09,0x0A,0x00,0x0F,0x05,0x05,0x05,\n0x0F,0x00,0x00,0x03,0x04,0x0E,/*\"甙\",4428*/},{\n\n0x49,0x45,0xF2,0x55,0x49,0x24,0xE4,0x24,0xFF,0x04,0x05,0x02,0x01,0x0F,0x01,0x02,\n0x04,0x07,0x02,0x03,0x04,0x0E,/*\"弒\",4429*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0x00,0x00,0xFF,0x10,0x20,0xC0,0x03,0x01,0x01,0x03,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"卟\",4430*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0x80,0xFF,0x20,0x10,0x08,0x04,0x03,0x01,0x01,0x03,0x01,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"叱\",4431*/},{\n\n0xFC,0x04,0xFC,0xB4,0xEB,0xB4,0x80,0xFF,0xB4,0xEB,0xB4,0x03,0x01,0x03,0x08,0x07,\n0x02,0x08,0x05,0x02,0x05,0x0E,/*\"嘰\",4432*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0x00,0xFE,0x02,0x02,0x02,0xFE,0x03,0x01,0x01,0x03,0x00,\n0x00,0x0F,0x00,0x02,0x02,0x01,/*\"叩\",4433*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0x02,0xFE,0x02,0x02,0x02,0xFE,0x03,0x01,0x01,0x03,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"叨\",4434*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0x08,0x08,0xFF,0x08,0x08,0xF8,0x03,0x01,0x01,0x03,0x08,\n0x04,0x03,0x00,0x08,0x08,0x07,/*\"叻\",4435*/},{\n\n0xFE,0x02,0x02,0xFE,0x40,0x42,0x42,0xFE,0x21,0x21,0x20,0x03,0x01,0x01,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"吒\",4436*/},{\n\n0xFE,0x02,0x02,0xFE,0x01,0x02,0x04,0xF8,0x04,0x02,0x01,0x03,0x01,0x01,0x03,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"吖\",4437*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0x30,0x2C,0xE3,0x20,0x18,0x00,0x03,0x01,0x01,0x03,0x00,\n0x06,0x05,0x04,0x04,0x05,0x0E,/*\"吆\",4438*/},{\n\n0xFE,0x02,0x02,0xFE,0x40,0x48,0x48,0xFF,0x48,0x48,0x40,0x03,0x01,0x01,0x03,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"呋\",4439*/},{\n\n0xFC,0x04,0xFC,0x08,0x24,0xFF,0x24,0xFC,0x24,0xFC,0x24,0x03,0x01,0x03,0x00,0x0D,\n0x01,0x0D,0x01,0x0D,0x01,0x0D,/*\"嘸\",4440*/},{\n\n0xFC,0x04,0xFC,0x42,0xAA,0xFF,0xAA,0x72,0x9F,0x72,0x82,0x03,0x01,0x01,0x02,0x0E,\n0x0B,0x0A,0x0A,0x0A,0x0E,0x0A,/*\"囈\",4441*/},{\n\n0xFE,0x02,0xFE,0x08,0x08,0xE8,0x1F,0xE8,0x08,0x08,0x08,0x03,0x01,0x0B,0x04,0x03,\n0x02,0x04,0x00,0x03,0x04,0x08,/*\"呔\",4442*/},{\n\n0xFE,0x02,0xFE,0x00,0xFF,0x55,0xFD,0x53,0x35,0xFD,0x53,0x03,0x01,0x03,0x08,0x07,\n0x08,0x0E,0x08,0x0F,0x0A,0x0A,/*\"嚦\",4443*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0x02,0xFA,0x0A,0x8A,0xFA,0x02,0x03,0x01,0x03,0x08,0x07,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"呃\",4444*/},{\n\n0xFE,0x02,0xFE,0x00,0xFF,0x10,0x10,0xFF,0x20,0x10,0x0C,0x03,0x01,0x03,0x00,0x0F,\n0x04,0x02,0x07,0x08,0x08,0x0E,/*\"吡\",4445*/},{\n\n0xFC,0x04,0x04,0xFC,0x00,0xFE,0x52,0x52,0x52,0x52,0xFE,0x03,0x01,0x01,0x03,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"唄\",4446*/},{\n\n0xE0,0x20,0x3F,0xA5,0xA5,0xBD,0xA1,0xA1,0x3F,0x20,0xE0,0x0F,0x00,0x00,0x07,0x04,\n0x04,0x04,0x07,0x00,0x08,0x0F,/*\"咼\",4447*/},{\n\n0xFC,0x04,0xFC,0x00,0xE0,0x00,0xF0,0x01,0x06,0x10,0xE0,0x03,0x01,0x01,0x02,0x01,\n0x00,0x07,0x08,0x08,0x0E,0x00,/*\"吣\",4448*/},{\n\n0xFE,0x02,0xFE,0x00,0xF2,0x92,0x92,0x9E,0x00,0x00,0xFF,0x03,0x01,0x03,0x00,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x0F,/*\"吲\",4449*/},{\n\n0xFC,0x04,0xFC,0x00,0xFE,0x02,0xF2,0x12,0xFE,0x12,0xF2,0x03,0x01,0x03,0x00,0x0F,\n0x08,0x09,0x08,0x0F,0x09,0x09,/*\"咂\",4450*/},{\n\n0xFE,0x02,0x02,0xFE,0x20,0x20,0xFF,0xA4,0x24,0x24,0x20,0x03,0x01,0x01,0x03,0x00,\n0x00,0x0F,0x00,0x01,0x02,0x00,/*\"咔\",4451*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0x92,0x92,0xFE,0x92,0x92,0xFE,0x03,0x01,0x03,0x00,0x01,\n0x00,0x00,0x0F,0x00,0x00,0x01,/*\"呷\",4452*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0x02,0xFE,0x02,0xFD,0x01,0x00,0x03,0x01,0x03,0x08,0x07,\n0x00,0x0F,0x0A,0x0C,0x03,0x04,/*\"呱\",4453*/},{\n\n0xFE,0x02,0xFE,0x10,0x48,0x44,0x53,0x64,0x48,0xD0,0x10,0x03,0x01,0x03,0x00,0x00,\n0x02,0x04,0x0A,0x01,0x00,0x00,/*\"呤\",4454*/},{\n\n0xFE,0x02,0xFE,0x00,0x48,0x44,0xAB,0x92,0x2A,0x46,0x40,0x03,0x01,0x03,0x00,0x00,\n0x02,0x02,0x04,0x05,0x08,0x00,/*\"咚\",4455*/},{\n\n0xFE,0x02,0xFE,0x00,0x26,0x9A,0xA6,0xAB,0xB2,0x8A,0x36,0x03,0x01,0x03,0x00,0x02,\n0x03,0x0A,0x0F,0x02,0x03,0x02,/*\"嚀\",4456*/},{\n\n0xFE,0x02,0xFE,0x00,0xBC,0x20,0x20,0xFF,0x20,0x20,0xBC,0x03,0x01,0x03,0x00,0x07,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"咄\",4457*/},{\n\n0xFE,0x02,0xFE,0x08,0xF8,0x0F,0xF8,0x04,0xFC,0x04,0xFC,0x03,0x01,0x03,0x08,0x05,\n0x02,0x05,0x08,0x04,0x03,0x0C,/*\"呶\",4458*/},{\n\n0xFE,0x02,0xFE,0x00,0x38,0xE7,0x30,0x08,0xFF,0x08,0xF8,0x03,0x01,0x03,0x00,0x03,\n0x02,0x0B,0x06,0x01,0x08,0x0F,/*\"呦\",4459*/},{\n\n0xFC,0x04,0xFC,0x00,0xDC,0xB3,0xC8,0x00,0xDC,0xB3,0xC8,0x03,0x01,0x03,0x04,0x02,\n0x04,0x02,0x04,0x0A,0x0F,0x02,/*\"噝\",4460*/},{\n\n0xFC,0x04,0xFC,0x00,0xFE,0x02,0x4A,0x4A,0xFA,0x4A,0x4A,0x03,0x01,0x03,0x00,0x0F,\n0x08,0x0A,0x0A,0x0B,0x0A,0x0A,/*\"哐\",4461*/},{\n\n0xFE,0x02,0x02,0xFE,0x04,0xA4,0xA4,0xBF,0xA4,0xA4,0x04,0x03,0x01,0x01,0x03,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"咭\",4462*/},{\n\n0xFC,0x04,0xFC,0x00,0xF2,0x12,0xFE,0x12,0xFE,0x92,0xF2,0x03,0x01,0x03,0x00,0x0F,\n0x05,0x04,0x04,0x04,0x04,0x0F,/*\"哂\",4463*/},{\n\n0xFE,0x02,0xFE,0x00,0xC4,0x3F,0xC4,0x04,0xF4,0x44,0x24,0x03,0x01,0x03,0x04,0x03,\n0x08,0x04,0x02,0x01,0x06,0x08,/*\"咴\",4464*/},{\n\n0xFC,0x04,0xFC,0x21,0xE2,0x08,0xAA,0xBA,0xEF,0xBA,0xAA,0x03,0x01,0x03,0x08,0x07,\n0x0A,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"噠\",4465*/},{\n\n0xFC,0x04,0xFC,0x62,0x9E,0x12,0xF2,0x00,0xFC,0x00,0xFF,0x03,0x01,0x03,0x08,0x04,\n0x03,0x00,0x00,0x09,0x08,0x0F,/*\"咧\",4466*/},{\n\n0xFE,0x02,0xFE,0x00,0xEA,0xAA,0xAA,0xFF,0xAA,0xAA,0xBA,0x03,0x01,0x03,0x00,0x08,\n0x08,0x04,0x03,0x04,0x0A,0x0B,/*\"咦\",4467*/},{\n\n0xFC,0x04,0xFC,0x00,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x03,0x01,0x03,0x00,0x0A,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"嘵\",4468*/},{\n\n0xFE,0x02,0xFE,0x00,0x5F,0xF5,0x55,0xFF,0x55,0xF5,0x5F,0x03,0x01,0x03,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"嗶\",4469*/},{\n\n0xFE,0x02,0xFE,0x00,0xF8,0x00,0xFF,0x20,0xFF,0x10,0x08,0x03,0x01,0x03,0x08,0x0F,\n0x08,0x07,0x04,0x07,0x08,0x0E,/*\"呲\",4470*/},{\n\n0xFE,0x02,0xFE,0x00,0x24,0x28,0xE0,0x3F,0xE0,0x28,0x24,0x03,0x01,0x03,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"咣\",4471*/},{\n\n0xFC,0x04,0xFC,0x00,0xE8,0xAE,0xA8,0xAF,0xFA,0x2A,0xB0,0x03,0x01,0x03,0x08,0x07,\n0x0A,0x0F,0x04,0x03,0x05,0x0E,/*\"噦\",4472*/},{\n\n0xFC,0x04,0xFC,0x10,0xFC,0x8B,0x68,0xFF,0x28,0xC8,0x08,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x00,0x0F,0x00,0x00,0x01,/*\"咻\",4473*/},{\n\n0xFC,0x04,0xFC,0x08,0xFC,0x13,0x92,0xFE,0x92,0xFE,0x10,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x08,0x07,0x00,0x01,0x00,/*\"咿\",4474*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0x02,0xFA,0x0A,0xF9,0x45,0x20,0x03,0x01,0x03,0x08,0x07,\n0x00,0x0F,0x04,0x01,0x06,0x08,/*\"哌\",4475*/},{\n\n0xFE,0x02,0xFE,0x00,0xF4,0xB2,0xD5,0xF5,0xD5,0xB2,0xF4,0x03,0x01,0x03,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"噲\",4476*/},{\n\n0xFE,0x02,0xFE,0x00,0x50,0x4F,0x41,0xF1,0x41,0x4F,0x50,0x03,0x01,0x03,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"哚\",4477*/},{\n\n0xFE,0x02,0xFE,0x28,0xDA,0x7A,0x06,0x7B,0x06,0x7A,0xD6,0x03,0x01,0x03,0x08,0x07,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"嚌\",4478*/},{\n\n0xFE,0x02,0xFE,0x00,0x04,0x25,0x26,0xFC,0x26,0x25,0x04,0x03,0x01,0x03,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"咩\",4479*/},{\n\n0xFE,0x02,0xFE,0x00,0x24,0x28,0xA0,0xFF,0xA0,0x28,0x24,0x03,0x01,0x03,0x00,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"咪\",4480*/},{\n\n0xFE,0x02,0x02,0xFE,0x40,0x42,0x42,0xFE,0x21,0x21,0x20,0x03,0x01,0x01,0x03,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"吒\",4481*/},{\n\n0xFE,0x02,0xFE,0x00,0xBE,0xAA,0xBF,0xAA,0xBF,0xAA,0xBE,0x03,0x01,0x03,0x08,0x07,\n0x02,0x0E,0x0A,0x06,0x0A,0x0A,/*\"噥\",4482*/},{\n\n0xFE,0x02,0x02,0xFE,0x00,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x03,0x01,0x01,0x03,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"哏\",4483*/},{\n\n0xFE,0x02,0xFE,0x00,0x80,0x6C,0x4A,0xF9,0x48,0x4C,0x18,0x03,0x01,0x03,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"哞\",4484*/},{\n\n0xFC,0x04,0xFC,0x00,0x52,0x2E,0x92,0x7F,0x12,0x2E,0x52,0x03,0x01,0x03,0x00,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x00,/*\"嘜\",4485*/},{\n\n0xFC,0x04,0xFC,0x00,0x20,0xA4,0xE4,0x3F,0xE4,0xA4,0x20,0x03,0x01,0x03,0x00,0x09,\n0x04,0x03,0x08,0x0F,0x00,0x03,/*\"哧\",4486*/},{\n\n0xFE,0x02,0xFE,0x00,0x6A,0x27,0xAA,0x21,0x2A,0x27,0x6A,0x03,0x01,0x03,0x00,0x08,\n0x05,0x03,0x09,0x09,0x07,0x00,/*\"嘮\",4487*/},{\n\n0xFE,0x02,0xFE,0x00,0xFA,0xAA,0xAA,0xFE,0xAA,0xAA,0xFA,0x03,0x01,0x03,0x00,0x08,\n0x05,0x02,0x05,0x08,0x08,0x08,/*\"哽\",4488*/},{\n\n0xFE,0x02,0xFE,0x21,0xA5,0xBD,0xA7,0xA5,0xA5,0xBD,0x21,0x03,0x01,0x03,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"唔\",4489*/},{\n\n0xFE,0x02,0xFE,0x88,0xFF,0x48,0x00,0xFE,0x12,0xF2,0x11,0x03,0x01,0x03,0x08,0x0F,\n0x00,0x08,0x07,0x00,0x0F,0x00,/*\"哳\",4490*/},{\n\n0xFC,0x04,0xFC,0x00,0xF9,0xAA,0xA8,0xAF,0xA8,0xAA,0xF9,0x03,0x01,0x03,0x00,0x0B,\n0x06,0x02,0x02,0x02,0x06,0x0B,/*\"嗩\",4491*/},{\n\n0xFE,0x02,0xFE,0x00,0x7C,0x54,0xD6,0x55,0x54,0x7C,0x00,0x03,0x01,0x03,0x02,0x02,\n0x02,0x07,0x09,0x09,0x09,0x0C,/*\"唣\",4492*/},{\n\n0xFE,0x02,0xFE,0x90,0xD5,0xB2,0x9A,0xD2,0x92,0x95,0x90,0x03,0x01,0x03,0x00,0x07,\n0x00,0x00,0x0F,0x00,0x04,0x07,/*\"唏\",4493*/},{\n\n0xFE,0x02,0x02,0xFE,0x20,0x1C,0x20,0xFF,0x20,0x1C,0x20,0x03,0x01,0x01,0x03,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"唑\",4494*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0x92,0xFE,0x00,0xFE,0x02,0xFE,0x03,0x01,0x03,0x00,0x0F,\n0x04,0x02,0x04,0x0F,0x01,0x01,/*\"唧\",4495*/},{\n\n0xFE,0x02,0xFE,0x00,0xA2,0x6A,0x3A,0xAF,0x2A,0x6A,0xA2,0x03,0x01,0x03,0x00,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"唪\",4496*/},{\n\n0xFE,0x02,0xFE,0x00,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x03,0x01,0x03,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"嘖\",4497*/},{\n\n0xFE,0x02,0xFE,0x24,0x24,0xEF,0xB4,0xA4,0xAF,0xA4,0x24,0x03,0x01,0x03,0x02,0x01,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"喏\",4498*/},{\n\n0xFE,0x02,0xFE,0x00,0xF2,0x97,0x92,0xF2,0x92,0x97,0xF2,0x03,0x01,0x03,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"喵\",4499*/},{\n\n0xFE,0x02,0xFE,0x88,0x48,0xFF,0xA8,0x48,0xFF,0x48,0x88,0x03,0x01,0x03,0x00,0x00,\n0x0F,0x00,0x00,0x0F,0x00,0x00,/*\"啉\",4500*/},{\n\n0xFC,0x04,0xFE,0xAA,0xFF,0xAA,0xF8,0xAA,0xFF,0xAA,0xFA,0x03,0x01,0x03,0x02,0x0F,\n0x02,0x02,0x06,0x0A,0x0F,0x02,/*\"囀\",4501*/},{\n\n0xFE,0x02,0xFE,0x00,0xFF,0x21,0xA9,0xBD,0xA9,0x21,0xFF,0x03,0x01,0x03,0x08,0x07,\n0x00,0x03,0x02,0x0B,0x08,0x0F,/*\"啁\",4502*/},{\n\n0xFE,0x02,0xFE,0x04,0x53,0x4E,0xFA,0x4A,0x4A,0x02,0xFE,0x03,0x01,0x03,0x00,0x03,\n0x02,0x03,0x02,0x0B,0x08,0x07,/*\"啕\",4503*/},{\n\n0xFE,0x02,0xFE,0x08,0x24,0x53,0xAE,0x12,0x4E,0x42,0x3E,0x03,0x01,0x03,0x04,0x03,\n0x00,0x06,0x09,0x0C,0x01,0x06,/*\"唿\",4504*/},{\n\n0xFE,0x02,0xFE,0x00,0x24,0x1C,0x25,0x86,0x24,0x1C,0x24,0x03,0x01,0x03,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"啐\",4505*/},{\n\n0xFC,0x04,0xFC,0x00,0xA4,0xAC,0xB5,0xE6,0xB4,0xAC,0xA4,0x03,0x01,0x03,0x00,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"唼\",4506*/},{\n\n0xFC,0x04,0xFC,0x02,0xEE,0xAA,0xAB,0xAA,0xAA,0xEE,0x1A,0x03,0x01,0x03,0x00,0x0F,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"唷\",4507*/},{\n\n0xFE,0x02,0xFE,0x00,0x28,0xA6,0x10,0xCF,0x10,0x14,0xA2,0x03,0x01,0x03,0x08,0x09,\n0x04,0x02,0x01,0x02,0x05,0x08,/*\"啖\",4508*/},{\n\n0xFC,0x04,0xFC,0x22,0x44,0xFC,0x24,0xE4,0x3F,0xE4,0x0C,0x03,0x01,0x01,0x04,0x0A,\n0x07,0x08,0x05,0x02,0x05,0x08,/*\"啵\",4509*/},{\n\n0xFE,0x02,0xFE,0x00,0x2C,0xA4,0x24,0xE5,0x26,0x24,0x2C,0x03,0x01,0x03,0x08,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"啶\",4510*/},{\n\n0xFE,0x02,0xFE,0x00,0xFD,0x56,0x7C,0x00,0xFE,0x32,0xCE,0x03,0x01,0x03,0x00,0x0F,\n0x05,0x02,0x04,0x0F,0x02,0x01,/*\"啷\",4511*/},{\n\n0xFE,0x02,0xFE,0x00,0xFC,0x94,0x95,0xF6,0x94,0xD4,0x9C,0x03,0x01,0x0B,0x04,0x0B,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"唳\",4512*/},{\n\n0xFE,0x02,0xFF,0x29,0xF9,0x29,0xEF,0x00,0xFC,0x00,0xFF,0x03,0x09,0x07,0x00,0x0F,\n0x02,0x03,0x00,0x09,0x08,0x0F,/*\"唰\",4513*/},{\n\n0xFE,0x02,0xFE,0x00,0xAA,0x92,0xAE,0x00,0xAA,0x92,0xAE,0x03,0x01,0x03,0x08,0x0A,\n0x04,0x0B,0x00,0x0B,0x04,0x0B,/*\"啜\",4514*/},{\n\n0xFE,0x02,0xFE,0x00,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x03,0x01,0x03,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"喋\",4515*/},{\n\n0xFC,0x04,0x04,0xFC,0x42,0x27,0x52,0x4A,0x52,0x27,0x42,0x03,0x01,0x01,0x03,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"嗒\",4516*/},{\n\n0xFE,0x02,0xFE,0x00,0xFA,0x0A,0x5A,0xEF,0x5A,0x0A,0xFA,0x03,0x01,0x03,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"喃\",4517*/},{\n\n0xFE,0x02,0xFE,0x00,0xFF,0x01,0x7D,0x55,0xFD,0x55,0x7D,0x03,0x01,0x03,0x08,0x07,\n0x00,0x09,0x09,0x0F,0x09,0x09,/*\"喱\",4518*/},{\n\n0xFE,0x02,0xFE,0x00,0x92,0xAA,0xA6,0xF3,0xA6,0xAA,0x92,0x03,0x01,0x03,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"喹\",4519*/},{\n\n0xFE,0x02,0xFE,0x00,0xDF,0x52,0x4A,0x60,0x4F,0x52,0xD9,0x03,0x01,0x03,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"喈\",4520*/},{\n\n0xFE,0x02,0xFE,0x00,0x80,0xBF,0xA5,0xFF,0xA5,0xBF,0x80,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x02,0x03,0x06,0x08,0x0F,/*\"喁\",4521*/},{\n\n0xFE,0x02,0xFE,0x00,0x1F,0xF5,0x55,0x5F,0x55,0xF5,0x1F,0x03,0x01,0x03,0x00,0x00,\n0x0F,0x01,0x01,0x09,0x0F,0x00,/*\"喟\",4522*/},{\n\n0xFC,0x04,0xFC,0x00,0x92,0xFE,0x51,0x08,0xFF,0x10,0x0C,0x03,0x01,0x03,0x01,0x00,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"啾\",4523*/},{\n\n0xFE,0x02,0xFE,0x00,0xBC,0xAA,0xA0,0xFF,0xA0,0xAA,0xBE,0x03,0x01,0x03,0x00,0x08,\n0x09,0x0A,0x04,0x04,0x0A,0x09,/*\"嗖\",4524*/},{\n\n0xFC,0x04,0xFC,0x12,0xD6,0x5A,0x53,0x52,0x5A,0xD6,0x12,0x03,0x01,0x03,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"喑\",4525*/},{\n\n0x18,0xEA,0x2A,0x2E,0x2A,0xFB,0x2A,0x2E,0xAA,0xEA,0x18,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0B,0x0A,0x0A,0x0A,0x0E,0x00,/*\"啻\",4526*/},{\n\n0xFE,0x02,0xFE,0x00,0x44,0xD5,0x76,0x5C,0x56,0x55,0x44,0x03,0x01,0x03,0x04,0x0A,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"嗟\",4527*/},{\n\n0xFC,0x04,0xFC,0x00,0x88,0xBE,0xAA,0xFF,0xAA,0xBE,0x88,0x03,0x01,0x03,0x00,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"嘍\",4528*/},{\n\n0x60,0x3F,0xE5,0xA0,0xB5,0xEA,0xB5,0xA0,0xA5,0xBF,0x60,0x02,0x03,0x0E,0x0A,0x0A,\n0x0B,0x0A,0x0A,0x0E,0x02,0x02,/*\"嚳\",4529*/},{\n\n0xFE,0x02,0xFE,0x00,0xFF,0x05,0x95,0xD5,0xB5,0x95,0xD7,0x03,0x01,0x03,0x08,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"喔\",4530*/},{\n\n0xFE,0x02,0xFE,0x00,0xAC,0x6B,0xAA,0x2A,0x3A,0xA6,0x20,0x03,0x01,0x03,0x08,0x0A,\n0x05,0x0A,0x0F,0x01,0x06,0x08,/*\"喙\",4531*/},{\n\n0xFE,0x02,0xFE,0x00,0xA2,0x6A,0xBA,0xAF,0xAA,0x6A,0xA2,0x03,0x01,0x03,0x00,0x0A,\n0x06,0x02,0x0F,0x02,0x06,0x0A,/*\"嗪\",4532*/},{\n\n0xFE,0x02,0xFE,0x20,0xEA,0xBF,0xAA,0x10,0xEF,0x08,0xF8,0x03,0x01,0x03,0x08,0x07,\n0x08,0x0F,0x08,0x05,0x02,0x0D,/*\"嗷\",4533*/},{\n\n0xFE,0x02,0xFE,0x00,0x22,0xAA,0xEA,0xBF,0xAA,0x6A,0x22,0x03,0x01,0x03,0x00,0x0A,\n0x06,0x0A,0x0F,0x02,0x06,0x0B,/*\"嗉\",4534*/},{\n\n0xFE,0x02,0xFE,0x50,0xF2,0x5F,0xDA,0x14,0xFE,0x32,0xCE,0x03,0x01,0x03,0x00,0x0F,\n0x05,0x0F,0x00,0x0F,0x02,0x01,/*\"嘟\",4535*/},{\n\n0xFE,0x02,0xFE,0x00,0x48,0x6A,0x5A,0x4F,0x4A,0x6A,0x48,0x03,0x01,0x03,0x08,0x0F,\n0x09,0x0F,0x09,0x0F,0x09,0x0F,/*\"嗑\",4536*/},{\n\n0xFC,0x04,0xFC,0xD1,0x5F,0xD5,0x55,0xD5,0x7F,0xC9,0x40,0x03,0x01,0x05,0x07,0x05,\n0x0F,0x04,0x07,0x05,0x0F,0x02,/*\"囁\",4537*/},{\n\n0xFC,0x04,0xFC,0x22,0xF2,0x0F,0xD2,0x52,0xD7,0xF2,0x12,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x03,0x02,0x0B,0x0F,0x00,/*\"嗬\",4538*/},{\n\n0xFC,0x04,0xFC,0x02,0xFA,0xAA,0xAF,0xAA,0xAA,0xFA,0x02,0x03,0x01,0x01,0x02,0x0B,\n0x06,0x02,0x02,0x06,0x0B,0x02,/*\"嗔\",4539*/},{\n\n0xFE,0x02,0xFE,0x00,0x1A,0x6A,0xDA,0x4F,0x2A,0x8A,0x1A,0x03,0x01,0x03,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"嗦\",4540*/},{\n\n0xFE,0x02,0xFE,0x00,0xC1,0x5D,0xD5,0x55,0xD5,0x5D,0xC1,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x02,0x0F,0x02,0x08,0x0F,/*\"嗝\",4541*/},{\n\n0xFE,0x02,0xFE,0x01,0x7D,0x55,0xD7,0x55,0x55,0x7D,0x01,0x03,0x01,0x03,0x08,0x0A,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"嗄\",4542*/},{\n\n0xFE,0x02,0xFE,0x00,0x7F,0x65,0xD5,0x4F,0x55,0x65,0x7F,0x03,0x01,0x03,0x04,0x03,\n0x00,0x06,0x09,0x0C,0x01,0x06,/*\"嗯\",4543*/},{\n\n0xFC,0x04,0xFC,0x80,0xBE,0xEA,0xAB,0xAA,0xAA,0xBE,0x80,0x03,0x01,0x05,0x02,0x05,\n0x04,0x0E,0x04,0x05,0x02,0x04,/*\"嗥\",4544*/},{\n\n0xFE,0x02,0xFE,0x10,0x52,0xA9,0x3A,0xA4,0x6A,0x11,0x12,0x03,0x01,0x03,0x0A,0x0A,\n0x09,0x0B,0x05,0x05,0x03,0x00,/*\"嗲\",4545*/},{\n\n0xFC,0x04,0xFC,0x00,0x5A,0x8E,0x2A,0x5E,0x69,0x0D,0x59,0x03,0x01,0x03,0x00,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"噯\",4546*/},{\n\n0xFC,0x04,0xFC,0xA9,0x9A,0x88,0x88,0x88,0x9A,0xA9,0x00,0x03,0x01,0x09,0x0F,0x08,\n0x0F,0x08,0x0F,0x08,0x0F,0x08,/*\"嗌\",4547*/},{\n\n0xFE,0x02,0xFE,0xE1,0x8A,0xF8,0x8A,0xE1,0xFE,0x92,0xFE,0x03,0x01,0x03,0x08,0x04,\n0x03,0x00,0x08,0x07,0x08,0x0F,/*\"嗍\",4548*/},{\n\n0xFC,0x04,0xFC,0x22,0x44,0xFB,0x4A,0x6A,0x4A,0xFA,0x42,0x03,0x01,0x03,0x04,0x02,\n0x03,0x02,0x0B,0x0A,0x07,0x02,/*\"嗨\",4549*/},{\n\n0xFE,0x02,0xFE,0x11,0xF2,0x00,0xF9,0xAB,0xFD,0xAB,0xF8,0x03,0x01,0x03,0x08,0x07,\n0x08,0x0B,0x08,0x09,0x0A,0x0B,/*\"嗵\",4550*/},{\n\n0xFE,0x02,0xFE,0x00,0x96,0x94,0x94,0xDF,0x94,0x94,0x96,0x03,0x01,0x03,0x08,0x0B,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0F,/*\"嗤\",4551*/},{\n\n0x6C,0x5B,0x84,0xFA,0xAA,0xFF,0xAA,0xFA,0x80,0x6C,0x5B,0x01,0x0E,0x0A,0x0A,0x0A,\n0x0B,0x0A,0x0A,0x0A,0x0E,0x01,/*\"轡\",4552*/},{\n\n0xFC,0x04,0xFC,0xE2,0xAF,0xFA,0xAF,0xEA,0xFF,0x08,0xF8,0x03,0x01,0x01,0x02,0x02,\n0x0F,0x02,0x0A,0x07,0x08,0x0F,/*\"嘞\",4553*/},{\n\n0xFE,0x02,0xFE,0x00,0xFA,0xAA,0xFF,0xAA,0xFF,0xAA,0xFA,0x03,0x01,0x03,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"嘈\",4554*/},{\n\n0xFE,0x02,0xFE,0x00,0x1D,0x55,0x5F,0x55,0x5F,0x55,0x1D,0x03,0x01,0x03,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"嘌\",4555*/},{\n\n0xFE,0x02,0xFE,0x00,0xFC,0x44,0xFC,0x54,0xFF,0x04,0xE5,0x03,0x01,0x03,0x08,0x07,\n0x0A,0x0F,0x05,0x03,0x05,0x0E,/*\"嘁\",4556*/},{\n\n0xFE,0x02,0xFE,0x00,0x5F,0x35,0xDF,0x00,0x5F,0x35,0x5F,0x03,0x01,0x03,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"嚶\",4557*/},{\n\n0xFE,0x02,0xFE,0x00,0xF6,0x54,0xF4,0x07,0xF4,0x54,0xF6,0x03,0x01,0x03,0x08,0x07,\n0x09,0x0F,0x08,0x07,0x09,0x0F,/*\"嘣\",4558*/},{\n\n0xFE,0x02,0xFE,0x04,0xFD,0x26,0xE4,0xA3,0x9A,0xF2,0x92,0x03,0x01,0x03,0x08,0x07,\n0x08,0x07,0x08,0x04,0x03,0x0C,/*\"嗾\",4559*/},{\n\n0xFE,0x02,0xFE,0x00,0xF2,0x16,0x5A,0xF3,0x5A,0x16,0xF2,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x07,0x05,0x07,0x08,0x0F,/*\"嘀\",4560*/},{\n\n0xFE,0x02,0xFE,0x20,0x96,0x72,0xC6,0xAB,0xD2,0x0A,0x66,0x03,0x01,0x03,0x00,0x0E,\n0x08,0x08,0x0E,0x08,0x08,0x0E,/*\"嘧\",4561*/},{\n\n0xFC,0x04,0xFC,0x02,0xEA,0xAA,0xAF,0xAA,0xEA,0x44,0x22,0x03,0x01,0x03,0x08,0x09,\n0x0A,0x04,0x06,0x05,0x08,0x04,/*\"嘭\",4562*/},{\n\n0xFC,0x04,0xFC,0x00,0xFE,0x2A,0xF2,0x2A,0xA2,0xDE,0x32,0x03,0x01,0x03,0x08,0x07,\n0x09,0x07,0x09,0x05,0x03,0x0C,/*\"噘\",4563*/},{\n\n0xFE,0x02,0xFE,0x00,0x2A,0xF2,0xAA,0xA7,0xAA,0xF2,0x2A,0x03,0x01,0x03,0x00,0x08,\n0x07,0x0A,0x0E,0x02,0x07,0x08,/*\"嘹\",4564*/},{\n\n0xFE,0x02,0xFE,0x00,0x25,0xAC,0xB7,0xE4,0xB7,0xAC,0x25,0x03,0x01,0x03,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"噗\",4565*/},{\n\n0xFE,0x02,0xFE,0x10,0xF0,0x5F,0xF5,0x15,0xD5,0x5F,0xD0,0x03,0x01,0x03,0x04,0x07,\n0x05,0x0F,0x0A,0x05,0x02,0x0D,/*\"嘬\",4566*/},{\n\n0xFE,0x02,0xFE,0x10,0xFC,0x57,0x54,0xFD,0x56,0x54,0x04,0x03,0x01,0x03,0x0C,0x03,\n0x05,0x09,0x05,0x09,0x05,0x09,/*\"噍\",4567*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0x5A,0x13,0x7E,0x12,0x5A,0xFE,0x03,0x01,0x03,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"噢\",4568*/},{\n\n0xFE,0x02,0xFE,0x00,0x72,0x46,0x6D,0xD7,0x6D,0x46,0x72,0x03,0x01,0x03,0x00,0x0F,\n0x01,0x07,0x05,0x0F,0x01,0x0F,/*\"噙\",4569*/},{\n\n0xFE,0x02,0x02,0xFE,0x44,0xBE,0xD5,0xBD,0xD7,0xBC,0x40,0x03,0x01,0x01,0x03,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"嚕\",4570*/},{\n\n0xFE,0x02,0xFE,0x00,0x3E,0xAB,0xA2,0xBE,0xA2,0xAB,0x3E,0x03,0x01,0x03,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"噌\",4571*/},{\n\n0xFE,0x02,0xFE,0x20,0xD5,0x49,0x57,0x50,0x4F,0xD2,0x29,0x03,0x01,0x03,0x08,0x0B,\n0x0D,0x09,0x09,0x0D,0x0B,0x08,/*\"噔\",4572*/},{\n\n0xFE,0x02,0xFE,0x00,0x8A,0xEF,0xAA,0xAE,0xAA,0xEF,0x8A,0x03,0x01,0x03,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"嚆\",4573*/},{\n\n0xFE,0x02,0xFE,0x00,0x0A,0x5F,0x52,0x4A,0x5F,0x4A,0x12,0x03,0x01,0x03,0x00,0x05,\n0x03,0x09,0x0F,0x01,0x03,0x05,/*\"噤\",4574*/},{\n\n0xFE,0x02,0xFE,0x00,0xFC,0x54,0x54,0xFF,0x55,0x55,0x6D,0x03,0x01,0x03,0x04,0x03,\n0x05,0x05,0x0A,0x0F,0x02,0x05,/*\"噱\",4575*/},{\n\n0xFE,0x02,0xFE,0x08,0xFA,0xAE,0xAB,0xAA,0xAE,0xFA,0x08,0x03,0x01,0x03,0x04,0x02,\n0x0C,0x09,0x0A,0x0C,0x02,0x04,/*\"噫\",4576*/},{\n\n0xFE,0x02,0xFE,0x00,0xA6,0xAA,0xFE,0xAB,0xFE,0xAA,0xA6,0x03,0x01,0x03,0x00,0x0A,\n0x09,0x0A,0x0F,0x0A,0x09,0x0A,/*\"噻\",4577*/},{\n\n0xFE,0x02,0xFE,0x00,0xFE,0x92,0x9E,0x40,0x55,0xE6,0x54,0x03,0x01,0x03,0x01,0x0F,\n0x04,0x0F,0x00,0x02,0x0F,0x02,/*\"噼\",4578*/},{\n\n0xFE,0x02,0xFE,0x00,0x4C,0x55,0x45,0xDF,0x45,0x55,0x4C,0x03,0x01,0x03,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"嚅\",4579*/},{\n\n0xFE,0x02,0xFE,0x20,0x56,0x2A,0x5A,0x43,0x5A,0x2A,0x5E,0x03,0x01,0x03,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"嚓\",4580*/},{\n\n0xFE,0x02,0xFE,0x80,0xCD,0x75,0x45,0xDF,0x65,0x55,0x4D,0x03,0x01,0x03,0x00,0x0F,\n0x05,0x05,0x07,0x05,0x05,0x04,/*\"嚯\",4581*/},{\n\n0xFE,0x02,0xFE,0x00,0x62,0xAE,0xEA,0xBF,0xEA,0xAE,0x62,0x03,0x01,0x03,0x00,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"囔\",4582*/},{\n\n0xFF,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0xFF,0x0F,0x08,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0F,/*\"囗\",4583*/},{\n\n0xFF,0x01,0x41,0x45,0x45,0xE5,0x55,0x4D,0x41,0x01,0xFF,0x0F,0x08,0x08,0x08,0x0A,\n0x0B,0x08,0x08,0x08,0x08,0x0F,/*\"囝\",4584*/},{\n\n0xFF,0x01,0x09,0x29,0x59,0x8F,0x49,0x39,0x09,0x01,0xFF,0x0F,0x08,0x0A,0x0A,0x09,\n0x08,0x09,0x0A,0x08,0x08,0x0F,/*\"囡\",4585*/},{\n\n0xFF,0x09,0xC9,0x55,0xD5,0x53,0xD5,0x55,0xC9,0x09,0xFF,0x0F,0x08,0x0F,0x09,0x0B,\n0x09,0x0B,0x0D,0x0F,0x08,0x0F,/*\"圇\",4586*/},{\n\n0xFF,0x21,0x91,0x4F,0x39,0x89,0x79,0x09,0xF9,0x01,0xFF,0x0F,0x08,0x08,0x0A,0x09,\n0x08,0x0A,0x0A,0x09,0x08,0x0F,/*\"囫\",4587*/},{\n\n0xFF,0x21,0x51,0x49,0x45,0x53,0x65,0xC9,0x51,0x21,0xFF,0x0F,0x08,0x08,0x08,0x09,\n0x0A,0x0D,0x08,0x08,0x08,0x0F,/*\"囹\",4588*/},{\n\n0xFF,0x21,0x15,0xFD,0x55,0x57,0x55,0xF5,0x05,0x01,0xFF,0x0F,0x08,0x08,0x0F,0x09,\n0x09,0x0D,0x0F,0x08,0x08,0x0F,/*\"囿\",4589*/},{\n\n0xFF,0x41,0x55,0x75,0x5D,0x55,0x55,0x75,0x45,0x41,0xFF,0x0F,0x08,0x08,0x0F,0x0D,\n0x0D,0x0D,0x0F,0x08,0x08,0x0F,/*\"圄\",4590*/},{\n\n0xFF,0x41,0x55,0xD5,0x55,0x7F,0x55,0xD5,0x55,0x01,0xFF,0x0F,0x08,0x08,0x0F,0x09,\n0x09,0x0D,0x0F,0x08,0x08,0x0F,/*\"圊\",4591*/},{\n\n0xFF,0x11,0x55,0x75,0x55,0xDF,0x55,0x75,0x55,0x11,0xFF,0x0F,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x0F,/*\"圉\",4592*/},{\n\n0xFF,0x11,0x1D,0x75,0xDD,0x55,0xDD,0x75,0x1D,0x11,0xFF,0x0F,0x08,0x0A,0x09,0x0F,\n0x0A,0x09,0x0A,0x0D,0x08,0x0F,/*\"圜\",4593*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x08,0x3A,0xAE,0xEB,0xBE,0x88,0x03,0x00,0x0F,0x02,0x03,\n0x00,0x03,0x02,0x0F,0x02,0x02,/*\"幃\",4594*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x50,0x4E,0x48,0xFF,0x48,0x48,0x03,0x00,0x0F,0x02,0x03,\n0x08,0x04,0x03,0x00,0x07,0x08,/*\"帙\",4595*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x00,0xFC,0xE4,0x3F,0xE4,0x0C,0x03,0x00,0x0F,0x02,0x0B,\n0x04,0x0B,0x05,0x02,0x05,0x08,/*\"帔\",4596*/},{\n\n0x42,0xAE,0x93,0x92,0xAE,0xC0,0xA1,0x97,0x89,0x95,0x23,0x00,0x07,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x04,0x07,0x00,/*\"帑\",4597*/},{\n\n0xFC,0x04,0xFF,0x04,0xFE,0xAA,0xAA,0xEF,0xAA,0xAA,0x6A,0x03,0x00,0x0F,0x02,0x0F,\n0x0A,0x0E,0x02,0x0A,0x0F,0x02,/*\"幬\",4598*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x03,0x00,0x0F,0x02,0x03,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"幘\",4599*/},{\n\n0xFC,0x04,0xFF,0x04,0xFF,0xA9,0xE9,0x1F,0xE9,0x0B,0xFF,0x03,0x00,0x0F,0x02,0x0F,\n0x0A,0x0A,0x0C,0x0B,0x0D,0x0F,/*\"幗\",4600*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x10,0xFC,0x27,0xFD,0x26,0x24,0x03,0x00,0x0F,0x02,0x03,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"帷\",4601*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x00,0xFF,0x05,0xD5,0xB5,0xD7,0x03,0x00,0x0F,0x02,0x03,\n0x04,0x03,0x08,0x0A,0x0F,0x0A,/*\"幄\",4602*/},{\n\n0xF8,0x08,0xFF,0x08,0x70,0x5F,0x75,0x55,0x75,0x5F,0x70,0x03,0x00,0x0F,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"幔\",4603*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x01,0x00,0x0F,0x01,0x01,\n0x02,0x02,0x02,0x0F,0x02,0x02,/*\"幛\",4604*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x00,0xAA,0xBF,0xE8,0xBF,0xAA,0x01,0x00,0x0F,0x01,0x01,\n0x02,0x0A,0x06,0x03,0x06,0x0A,/*\"幞\",4605*/},{\n\n0xFC,0x04,0xFF,0x04,0xFC,0x52,0xB6,0x9A,0xBE,0x99,0xB5,0x03,0x00,0x0F,0x02,0x03,\n0x00,0x0F,0x0A,0x0F,0x0A,0x0F,/*\"幡\",4606*/},{\n\n0x00,0x16,0x14,0xF4,0x14,0x97,0x14,0x74,0x54,0xC6,0x00,0x08,0x04,0x03,0x08,0x08,\n0x04,0x05,0x02,0x05,0x08,0x08,/*\"岌\",4607*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xE2,0x22,0x22,0x22,0x3E,0x03,0x02,0x01,0x01,0x03,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"屺\",4608*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x22,0xFE,0x22,0x22,0xFE,0x22,0x03,0x02,0x01,0x01,0x03,\n0x08,0x07,0x00,0x00,0x0F,0x00,/*\"岍\",4609*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x20,0xE4,0x24,0x3F,0x24,0xE4,0x03,0x02,0x01,0x01,0x03,\n0x08,0x08,0x05,0x02,0x05,0x08,/*\"岐\",4610*/},{\n\n0xF8,0x00,0xFF,0x00,0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x03,0x02,0x01,0x01,0x0F,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"嶇\",4611*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0x32,0xAA,0x62,0xFE,0x22,0x03,0x02,0x01,0x01,0x03,\n0x04,0x02,0x01,0x08,0x0F,0x00,/*\"岈\",4612*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xFE,0xAA,0xAA,0xFE,0x00,0x03,0x02,0x01,0x01,0x03,\n0x08,0x06,0x01,0x07,0x08,0x0C,/*\"峴\",4613*/},{\n\n0x48,0x48,0x2A,0x1A,0x0A,0x8E,0x09,0x19,0x29,0x48,0x48,0x00,0x0F,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x00,/*\"岙\",4614*/},{\n\n0x40,0x46,0x24,0x24,0x14,0x4F,0x94,0x24,0x24,0x46,0x40,0x00,0x01,0x01,0x01,0x01,\n0x01,0x09,0x05,0x03,0x01,0x00,/*\"岑\",4615*/},{\n\n0x00,0xFB,0x0A,0xAA,0xAA,0xEB,0xAA,0x9A,0x0A,0xFB,0x00,0x08,0x07,0x08,0x0B,0x0A,\n0x0F,0x0A,0x0F,0x08,0x07,0x0C,/*\"嵐\",4616*/},{\n\n0x00,0xF6,0x94,0x94,0x94,0xF7,0x94,0x94,0x94,0xF6,0x00,0x00,0x07,0x08,0x08,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"岜\",4617*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xC8,0x48,0x7F,0x48,0xC8,0x03,0x02,0x01,0x01,0x03,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"岵\",4618*/},{\n\n0x10,0xD6,0x54,0x54,0x54,0xD7,0x14,0x14,0xF4,0x16,0x10,0x00,0x07,0x02,0x02,0x02,\n0x03,0x08,0x08,0x0F,0x00,0x00,/*\"岢\",4619*/},{\n\n0x08,0xEB,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xEB,0x08,0x08,0x0B,0x0A,0x06,0x02,\n0x0F,0x02,0x06,0x0A,0x0B,0x08,/*\"崬\",4620*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xFE,0x92,0xFE,0x92,0xFE,0x03,0x02,0x01,0x01,0x03,\n0x00,0x01,0x00,0x0F,0x00,0x01,/*\"岬\",4621*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xF8,0x48,0xFF,0x48,0xF8,0x07,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x04,0x07,0x04,0x0F,/*\"岫\",4622*/},{\n\n0x10,0x08,0x7C,0x03,0x08,0x88,0x0F,0x18,0x25,0x46,0x74,0x00,0x0F,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x00,/*\"岱\",4623*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x10,0xE8,0x27,0xE4,0x04,0xFC,0x07,0x04,0x03,0x02,0x07,\n0x00,0x03,0x01,0x09,0x08,0x07,/*\"岣\",4624*/},{\n\n0xE0,0x26,0x14,0x94,0xC4,0x07,0xE4,0x24,0x24,0x26,0xE0,0x03,0x02,0x09,0x04,0x03,\n0x00,0x0F,0x00,0x00,0x02,0x03,/*\"峁\",4625*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xFF,0x49,0xF9,0x49,0x4F,0x03,0x02,0x01,0x01,0x03,\n0x00,0x0F,0x04,0x03,0x04,0x0E,/*\"岷\",4626*/},{\n\n0xF8,0x00,0xFF,0x00,0x47,0x55,0xD7,0x7D,0xD7,0x55,0x47,0x03,0x02,0x01,0x01,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"嶧\",4627*/},{\n\n0xF8,0x00,0xFF,0x00,0xFE,0x02,0xEA,0x2A,0xEA,0x02,0xFE,0x03,0x02,0x01,0x01,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"峒\",4628*/},{\n\n0xF8,0x00,0xFF,0x00,0xA8,0x9A,0xEE,0xAA,0xE9,0x99,0xA8,0x03,0x02,0x01,0x01,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"嶠\",4629*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x04,0xFB,0x4A,0xFA,0x02,0xFE,0x03,0x02,0x01,0x01,0x03,\n0x00,0x07,0x02,0x0B,0x08,0x07,/*\"峋\",4630*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x56,0x5A,0xF6,0x59,0xF5,0x40,0x03,0x02,0x01,0x01,0x03,\n0x01,0x09,0x0F,0x01,0x03,0x00,/*\"崢\",4631*/},{\n\n0xF8,0x00,0xFF,0x00,0x6A,0x27,0xAA,0x21,0x2A,0x27,0x6A,0x03,0x02,0x01,0x01,0x08,\n0x05,0x03,0x09,0x09,0x07,0x00,/*\"嶗\",4632*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x44,0x34,0xFF,0x44,0x34,0x44,0x03,0x02,0x01,0x01,0x01,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"崍\",4633*/},{\n\n0x20,0xA6,0xFC,0xA4,0x04,0x47,0x34,0x84,0x04,0x36,0x40,0x01,0x00,0x0F,0x00,0x01,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"崧\",4634*/},{\n\n0xF8,0x00,0xFF,0x00,0x12,0xEA,0xA6,0xF3,0xA6,0xEA,0x12,0x03,0x02,0x01,0x01,0x00,\n0x07,0x02,0x07,0x0A,0x0B,0x0C,/*\"崦\",4635*/},{\n\n0x00,0xFB,0x2A,0xAA,0xAA,0xFB,0xAA,0xAA,0x2A,0xFB,0x00,0x00,0x0F,0x08,0x0B,0x0A,\n0x0A,0x0A,0x0B,0x08,0x0F,0x00,/*\"崮\",4636*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x4D,0xFA,0xAE,0xAA,0xED,0x08,0x03,0x02,0x01,0x01,0x03,\n0x00,0x0F,0x02,0x0A,0x0F,0x00,/*\"崤\",4637*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xBA,0xAA,0xAB,0xAA,0x3A,0x03,0x02,0x01,0x01,0x03,\n0x00,0x02,0x0A,0x0E,0x03,0x02,/*\"崞\",4638*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xAC,0x95,0x86,0x94,0xAC,0x07,0x04,0x03,0x02,0x07,\n0x00,0x08,0x08,0x0F,0x08,0x08,/*\"崆\",4639*/},{\n\n0xF8,0x00,0xFF,0x00,0xFE,0x0A,0xEA,0x8A,0xFA,0x8A,0xEE,0x03,0x02,0x01,0x09,0x07,\n0x00,0x0E,0x08,0x0F,0x08,0x0E,/*\"崛\",4640*/},{\n\n0xF8,0x00,0xFF,0x04,0x72,0x2F,0x34,0xA2,0x34,0x2F,0x74,0x03,0x02,0x01,0x01,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"嶸\",4641*/},{\n\n0xF8,0x00,0xFF,0x00,0xBA,0xAA,0xBE,0xEA,0xBE,0xAA,0xBA,0x03,0x02,0x01,0x01,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"崾\",4642*/},{\n\n0x00,0xF6,0x54,0xD4,0x54,0x57,0x14,0xFC,0x14,0xDE,0x10,0x08,0x07,0x09,0x0B,0x05,\n0x0B,0x08,0x04,0x03,0x04,0x0E,/*\"崴\",4643*/},{\n\n0x00,0xF6,0x54,0x54,0x54,0xF7,0x54,0x54,0x54,0xF6,0x00,0x08,0x05,0x01,0x05,0x0B,\n0x0D,0x09,0x0D,0x01,0x05,0x08,/*\"崽\",4644*/},{\n\n0x00,0xFB,0xAA,0xAA,0xEE,0xBB,0xAA,0xAA,0xAA,0xFB,0x00,0x08,0x08,0x04,0x02,0x01,\n0x06,0x0B,0x0A,0x0B,0x0A,0x0C,/*\"嵬\",4645*/},{\n\n0x20,0xE6,0xB4,0xB4,0xAC,0xE7,0x0C,0xD4,0x14,0xE6,0x20,0x00,0x0F,0x02,0x02,0x0A,\n0x0F,0x00,0x03,0x08,0x0F,0x00,/*\"嵛\",4646*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x44,0xD5,0x76,0x5C,0x56,0x55,0x03,0x02,0x01,0x01,0x05,\n0x0A,0x09,0x09,0x0F,0x09,0x09,/*\"嵯\",4647*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x88,0xBE,0xAA,0xFF,0xAA,0xBE,0x03,0x02,0x01,0x01,0x03,\n0x08,0x0A,0x0B,0x04,0x04,0x0B,/*\"嶁\",4648*/},{\n\n0xF8,0x00,0xFF,0x00,0xE8,0x99,0x4A,0x08,0xEC,0x9B,0x48,0x03,0x02,0x01,0x01,0x06,\n0x05,0x0E,0x00,0x06,0x05,0x0E,/*\"嵫\",4649*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x00,0xFF,0x09,0xEF,0xA9,0xEF,0x03,0x02,0x01,0x01,0x03,\n0x08,0x07,0x00,0x0F,0x0A,0x0F,/*\"嵋\",4650*/},{\n\n0xF8,0x00,0xFF,0x00,0xA8,0xFA,0x0A,0xFE,0x09,0xF9,0xA8,0x03,0x02,0x01,0x01,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"嵊\",4651*/},{\n\n0x88,0x8B,0xEA,0xAA,0xAA,0xAF,0xAA,0xAA,0xEA,0x8B,0x88,0x0F,0x00,0x00,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x00,0x08,0x0F,/*\"嵩\",4652*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x15,0xEA,0xA7,0xA8,0xF2,0x25,0x03,0x02,0x01,0x01,0x03,\n0x00,0x0F,0x02,0x0A,0x0F,0x00,/*\"嵴\",4653*/},{\n\n0xF8,0x00,0xFF,0x00,0xF8,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x07,0x04,0x03,0x02,0x07,\n0x02,0x02,0x02,0x0F,0x02,0x02,/*\"嶂\",4654*/},{\n\n0xF8,0x00,0xFF,0x00,0x95,0x6E,0xC4,0x1F,0x44,0xEE,0x55,0x03,0x02,0x01,0x01,0x09,\n0x06,0x01,0x03,0x02,0x0F,0x02,/*\"嶙\",4655*/},{\n\n0xF8,0x00,0xFF,0x00,0xF5,0x09,0xD7,0x50,0xD7,0x0A,0x15,0x03,0x02,0x01,0x01,0x0B,\n0x08,0x0D,0x09,0x0D,0x08,0x08,/*\"嶝\",4656*/},{\n\n0xFC,0xAA,0x56,0xFA,0x50,0xFF,0xAA,0x56,0xFA,0x50,0xFC,0x0F,0x08,0x0A,0x0B,0x08,\n0x0F,0x08,0x0A,0x0B,0x08,0x0F,/*\"豳\",4657*/},{\n\n0x00,0xDB,0xAA,0xA6,0xB2,0x03,0x4A,0x5A,0xEA,0x5B,0xC0,0x0B,0x06,0x03,0x06,0x0A,\n0x08,0x07,0x08,0x0F,0x0A,0x08,/*\"嶷\",4658*/},{\n\n0x00,0xEB,0x2A,0xBE,0x2A,0xEB,0x02,0xEA,0xBA,0xAB,0xE8,0x02,0x0B,0x06,0x03,0x06,\n0x0B,0x02,0x0B,0x06,0x06,0x0B,/*\"巔\",4659*/},{\n\n0x48,0x24,0xF2,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"彳\",4660*/},{\n\n0x48,0x24,0xF2,0x09,0x04,0x04,0xFD,0x26,0x24,0x24,0xE4,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"彷\",4661*/},{\n\n0x48,0x24,0xF2,0x09,0x00,0xFE,0x92,0x92,0x92,0xFE,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"徂\",4662*/},{\n\n0x48,0x24,0xF2,0x09,0x04,0xFB,0x4A,0x4A,0xFA,0x02,0xFE,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x02,0x02,0x0B,0x08,0x07,/*\"徇\",4663*/},{\n\n0x48,0x24,0xF2,0x09,0x00,0x25,0x26,0xFC,0x26,0x25,0x00,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"徉\",4664*/},{\n\n0x48,0x24,0xF2,0x09,0x20,0x24,0xF6,0xAD,0xA4,0xB2,0x60,0x00,0x00,0x0F,0x00,0x0A,\n0x09,0x0A,0x04,0x0A,0x09,0x08,/*\"後\",4665*/},{\n\n0x48,0x24,0xF2,0x09,0x44,0x34,0x44,0xFF,0x44,0x34,0x44,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"徠\",4666*/},{\n\n0x48,0x24,0xF2,0x09,0x20,0xBC,0x20,0xBF,0x24,0x24,0x24,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x09,/*\"徙\",4667*/},{\n\n0x48,0x24,0xF2,0x09,0xF2,0x14,0xD0,0x5F,0xD0,0x14,0xF2,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"徜\",4668*/},{\n\n0x48,0x24,0xF2,0x09,0x80,0xBE,0xAB,0xAA,0xAA,0xBE,0x80,0x00,0x00,0x0F,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"徨\",4669*/},{\n\n0x48,0x24,0xF2,0x09,0x4A,0x32,0x26,0xEA,0x21,0x29,0x05,0x00,0x00,0x0F,0x00,0x0D,\n0x09,0x09,0x0F,0x09,0x09,0x0D,/*\"徭\",4670*/},{\n\n0x24,0xF2,0x0F,0x54,0xD7,0x54,0x16,0xEC,0x0B,0xF8,0x08,0x00,0x0F,0x00,0x05,0x07,\n0x05,0x08,0x04,0x03,0x04,0x08,/*\"徵\",4671*/},{\n\n0x24,0xF2,0x89,0xBE,0xEB,0xBE,0x10,0xEC,0x0B,0xF8,0x08,0x00,0x0F,0x08,0x07,0x0A,\n0x0E,0x08,0x04,0x03,0x04,0x08,/*\"徼\",4672*/},{\n\n0x24,0xF2,0x89,0xDF,0x75,0xDF,0x75,0x5F,0x12,0xF2,0x12,0x00,0x0F,0x00,0x0F,0x05,\n0x07,0x05,0x05,0x08,0x0F,0x00,/*\"衢\",4673*/},{\n\n0x00,0x00,0x88,0x88,0x44,0x44,0x22,0x11,0x88,0x00,0x00,0x00,0x00,0x08,0x08,0x04,\n0x04,0x02,0x01,0x00,0x00,0x00,/*\"彡\",4674*/},{\n\n0x10,0x8A,0x44,0xFB,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x08,0x08,0x07,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"犭\",4675*/},{\n\n0x8A,0x44,0xFB,0x00,0x08,0xFF,0x08,0x08,0xF8,0x00,0x00,0x08,0x08,0x07,0x08,0x06,\n0x01,0x00,0x00,0x07,0x08,0x0E,/*\"犰\",4676*/},{\n\n0x8A,0x44,0xFB,0x00,0x40,0x42,0x42,0xFE,0x42,0x42,0x40,0x08,0x08,0x07,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"犴\",4677*/},{\n\n0x8A,0x44,0xFB,0x00,0xFE,0x22,0xEA,0xBE,0xEB,0xBE,0xEA,0x08,0x08,0x07,0x08,0x07,\n0x00,0x0B,0x06,0x03,0x06,0x0B,/*\"獷\",4678*/},{\n\n0x8A,0x44,0xFB,0x00,0x7F,0x55,0x55,0x7F,0x55,0x55,0xC1,0x08,0x08,0x07,0x02,0x01,\n0x02,0x01,0x0A,0x09,0x0A,0x07,/*\"獁\",4679*/},{\n\n0x8A,0x44,0xFB,0x00,0x42,0xC2,0x7E,0x42,0x42,0xFE,0x00,0x08,0x08,0x07,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"狃\",4680*/},{\n\n0x8A,0x44,0xFB,0x10,0x18,0xF4,0x13,0xF0,0x14,0x38,0x00,0x08,0x08,0x07,0x08,0x04,\n0x03,0x00,0x07,0x08,0x08,0x0E,/*\"狁\",4681*/},{\n\n0x8A,0x44,0xFB,0x00,0xFE,0x92,0x92,0xFE,0x92,0x92,0xFE,0x08,0x08,0x07,0x00,0x01,\n0x00,0x00,0x0F,0x00,0x00,0x01,/*\"狎\",4682*/},{\n\n0x10,0x8A,0x44,0xFB,0x08,0xF4,0x97,0x94,0xF4,0x04,0xFC,0x01,0x08,0x08,0x07,0x00,\n0x07,0x08,0x08,0x08,0x09,0x0D,/*\"狍\",4683*/},{\n\n0x8A,0x44,0xFB,0x00,0xF2,0x92,0xFF,0x92,0xFF,0x92,0x9E,0x08,0x08,0x07,0x00,0x08,\n0x04,0x03,0x00,0x0F,0x04,0x07,/*\"狒\",4684*/},{\n\n0x8A,0x44,0xFB,0x00,0x88,0xE8,0x88,0xFF,0x08,0xE9,0x0A,0x08,0x08,0x07,0x08,0x04,\n0x03,0x08,0x04,0x03,0x04,0x0E,/*\"狨\",4685*/},{\n\n0x8A,0x44,0xFB,0x00,0xF4,0xB2,0xD5,0xF5,0xD5,0xB2,0xF4,0x08,0x08,0x07,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"獪\",4686*/},{\n\n0x8A,0x44,0xFB,0x00,0x2C,0xA4,0x25,0x26,0xF4,0x24,0x2C,0x08,0x08,0x07,0x00,0x00,\n0x00,0x09,0x08,0x0F,0x00,0x00,/*\"狩\",4687*/},{\n\n0x8A,0x44,0xFB,0x82,0xFA,0x46,0x80,0xDA,0xB6,0x91,0xC9,0x08,0x08,0x07,0x08,0x0F,\n0x00,0x04,0x0A,0x0F,0x02,0x04,/*\"猻\",4688*/},{\n\n0x8A,0x44,0xFB,0x00,0x3F,0x24,0x14,0xC0,0x1F,0x24,0x32,0x08,0x08,0x07,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"狴\",4689*/},{\n\n0x10,0x8A,0x44,0xFB,0x00,0xF7,0x55,0x55,0x55,0x55,0xF7,0x01,0x08,0x08,0x07,0x00,\n0x0F,0x01,0x01,0x01,0x09,0x0F,/*\"狷\",4690*/},{\n\n0x8A,0x44,0xFB,0x10,0x92,0xFE,0x91,0x10,0xFC,0x00,0xFF,0x08,0x08,0x07,0x01,0x00,\n0x0F,0x00,0x01,0x01,0x08,0x0F,/*\"猁\",4691*/},{\n\n0x8A,0x44,0xFB,0x00,0x48,0x54,0x52,0xF1,0x52,0x54,0x48,0x08,0x08,0x07,0x00,0x04,\n0x03,0x08,0x0F,0x00,0x01,0x06,/*\"狳\",4692*/},{\n\n0x8A,0x44,0xFB,0x00,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x08,0x08,0x07,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"獫\",4693*/},{\n\n0x8A,0x44,0xFB,0x04,0x54,0x54,0x55,0x56,0x54,0x54,0x04,0x08,0x08,0x07,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"狺\",4694*/},{\n\n0x8A,0x44,0xFB,0x00,0x24,0x96,0x65,0x44,0x44,0xD6,0x2C,0x08,0x08,0x07,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"狻\",4695*/},{\n\n0x8A,0x44,0xFB,0x10,0xDA,0x56,0x53,0xD2,0x16,0xFA,0x10,0x08,0x08,0x07,0x00,0x07,\n0x02,0x02,0x0B,0x08,0x0F,0x00,/*\"猗\",4696*/},{\n\n0x8A,0x44,0xFB,0x00,0xBE,0xAA,0xAA,0xFE,0xAA,0xAA,0xBE,0x08,0x08,0x07,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"猓\",4697*/},{\n\n0x8A,0x44,0xFB,0x00,0xB7,0x4D,0xA7,0xFD,0x57,0xFD,0x57,0x08,0x08,0x07,0x00,0x0D,\n0x01,0x05,0x0F,0x05,0x07,0x05,/*\"玀\",4698*/},{\n\n0x8A,0x44,0xFB,0x00,0xFE,0x92,0x81,0x90,0x92,0xFE,0x00,0x08,0x08,0x07,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0C,/*\"猊\",4699*/},{\n\n0x8A,0x44,0xFB,0x00,0x28,0xA4,0xAA,0xF9,0xAA,0xA4,0x28,0x08,0x08,0x07,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"猞\",4700*/},{\n\n0x8A,0x44,0xFB,0x00,0x24,0x1C,0x25,0x86,0x24,0x1C,0x24,0x08,0x08,0x07,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"猝\",4701*/},{\n\n0x8A,0x44,0xFB,0x00,0x79,0xCF,0x92,0xFE,0x52,0xB6,0xFA,0x08,0x08,0x07,0x00,0x08,\n0x0F,0x02,0x0F,0x01,0x0A,0x0F,/*\"獼\",4702*/},{\n\n0x8A,0x44,0xFB,0x00,0xE4,0x3F,0xE4,0x00,0xFF,0x89,0xFF,0x08,0x08,0x07,0x00,0x07,\n0x02,0x0B,0x04,0x03,0x08,0x0F,/*\"猢\",4703*/},{\n\n0x8A,0x44,0xFB,0x00,0x12,0xEA,0xA6,0xBF,0xA6,0xEA,0x12,0x08,0x08,0x07,0x00,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"猹\",4704*/},{\n\n0x8A,0x44,0xFB,0x40,0xDF,0x55,0x55,0xDF,0x55,0x55,0x5F,0x08,0x08,0x07,0x00,0x0F,\n0x08,0x04,0x01,0x02,0x06,0x09,/*\"猥\",4705*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x1F,0xF5,0x5F,0x55,0xF5,0x1F,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x01,0x09,0x0F,0x00,/*\"蝟\",4706*/},{\n\n0x8A,0x44,0xFB,0x00,0xFF,0x09,0xE9,0xAF,0xA9,0xA9,0xEF,0x08,0x08,0x07,0x08,0x07,\n0x00,0x0F,0x0A,0x0A,0x0A,0x0F,/*\"猸\",4707*/},{\n\n0x8A,0x44,0xFB,0x00,0x48,0x29,0x1B,0xCD,0x7D,0x0B,0x18,0x08,0x08,0x07,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"猱\",4708*/},{\n\n0x8A,0x44,0xFB,0x00,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0x08,0x08,0x07,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"獐\",4709*/},{\n\n0x8A,0x44,0xFB,0x08,0xEA,0xAE,0xAB,0xAA,0xAE,0xEA,0x08,0x08,0x08,0x07,0x08,0x0B,\n0x06,0x02,0x02,0x0E,0x0B,0x0C,/*\"獍\",4710*/},{\n\n0x8A,0x44,0xFB,0x00,0xFE,0x2A,0xF2,0x2A,0xA2,0xDE,0x32,0x08,0x08,0x07,0x08,0x07,\n0x09,0x07,0x09,0x05,0x03,0x0C,/*\"獗\",4711*/},{\n\n0x8A,0x44,0xFB,0x00,0x2A,0xF2,0xAA,0xA7,0xAA,0xF2,0x2A,0x08,0x08,0x07,0x00,0x08,\n0x07,0x0A,0x0E,0x02,0x07,0x08,/*\"獠\",4712*/},{\n\n0x8A,0xFC,0x0B,0xF4,0x53,0xFA,0x56,0xF9,0x27,0xF9,0x2F,0x08,0x07,0x08,0x07,0x01,\n0x07,0x09,0x0F,0x01,0x0F,0x01,/*\"獬\",4713*/},{\n\n0x8A,0x44,0xFB,0x00,0xF4,0x55,0x15,0xFF,0x15,0x55,0xF4,0x08,0x08,0x07,0x00,0x0D,\n0x05,0x0D,0x07,0x0D,0x05,0x0D,/*\"獯\",4714*/},{\n\n0x8A,0x44,0xFB,0x00,0xBA,0xEF,0xBA,0xC2,0xBA,0xAF,0xBA,0x08,0x08,0x07,0x01,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"獾\",4715*/},{\n\n0x40,0x30,0x4F,0x88,0x78,0x00,0xF4,0x04,0xFF,0x04,0x04,0x08,0x04,0x02,0x01,0x00,\n0x00,0x01,0x01,0x0F,0x01,0x01,/*\"舛\",4716*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x00,0x24,0xAB,0x52,0x4A,0xC6,0x02,0x01,0x0F,0x01,0x02,\n0x00,0x09,0x08,0x05,0x02,0x01,/*\"夥\",4717*/},{\n\n0x20,0x5F,0x84,0x7C,0x08,0xF4,0x52,0x59,0x52,0xF4,0x08,0x08,0x06,0x01,0x00,0x00,\n0x0F,0x05,0x01,0x03,0x05,0x0A,/*\"飧\",4718*/},{\n\n0x10,0xF4,0xB4,0xAA,0xAB,0xFE,0xAA,0xAE,0xAA,0xE8,0x18,0x00,0x0B,0x06,0x02,0x02,\n0x03,0x02,0x02,0x06,0x0B,0x00,/*\"夤\",4719*/},{\n\n0x40,0x20,0x10,0x6C,0x8B,0x08,0x88,0x48,0x38,0x00,0x00,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x04,0x08,0x08,/*\"夂\",4720*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x04,0x02,0x04,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"飠\",4721*/},{\n\n0x04,0xFA,0xAD,0xFA,0x44,0xDF,0x55,0x55,0x55,0x5F,0x40,0x00,0x0F,0x04,0x02,0x0E,\n0x05,0x0B,0x05,0x0B,0x09,0x07,/*\"餳\",4722*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0xF4,0x84,0xFF,0x84,0xF4,0x04,0x00,0x0F,0x04,0x02,0x04,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"飩\",4723*/},{\n\n0xFA,0xAD,0xFA,0x08,0x64,0xAB,0xEA,0xAA,0x6A,0xEA,0x02,0x0F,0x04,0x02,0x04,0x09,\n0x05,0x0F,0x05,0x09,0x07,0x0C,/*\"餼\",4724*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x44,0x44,0xFC,0x42,0x42,0x40,0x00,0x0F,0x04,0x02,0x04,\n0x08,0x08,0x0F,0x08,0x08,0x00,/*\"飪\",4725*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0x22,0x22,0xFE,0x21,0x21,0x20,0x00,0x0F,0x04,0x02,0x0C,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"飫\",4726*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x14,0x48,0xF7,0x44,0x44,0xC4,0x00,0x0F,0x04,0x02,0x0C,\n0x04,0x03,0x00,0x08,0x08,0x07,/*\"飭\",4727*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0xD8,0x54,0x53,0x50,0xD8,0x30,0x00,0x0F,0x04,0x02,0x04,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"飴\",4728*/},{\n\n0xFA,0xAD,0xFA,0x00,0xFC,0x04,0xE6,0x25,0xE4,0x04,0xFC,0x0F,0x04,0x02,0x04,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"餉\",4729*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0x1A,0x2A,0x2A,0xAF,0x6A,0x1A,0x00,0x0F,0x04,0x02,0x04,\n0x01,0x01,0x09,0x0F,0x01,0x01,/*\"餑\",4730*/},{\n\n0x04,0xFA,0xAD,0xFA,0x4C,0x54,0x52,0xF1,0x52,0x54,0x48,0x00,0x0F,0x04,0x02,0x04,\n0x03,0x08,0x0F,0x00,0x01,0x06,/*\"餘\",4731*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0xDF,0x95,0x15,0xD5,0x15,0x9F,0x00,0x0F,0x04,0x02,0x04,\n0x0F,0x04,0x00,0x07,0x09,0x0C,/*\"餛\",4732*/},{\n\n0x04,0xFA,0xAD,0xFA,0x04,0x12,0xEA,0xA6,0xBF,0xEA,0x12,0x00,0x0F,0x04,0x02,0x04,\n0x08,0x0B,0x0A,0x0A,0x0B,0x08,/*\"餷\",4733*/},{\n\n0xFA,0xAD,0xFA,0x00,0xBC,0xAA,0xA0,0xFF,0xA0,0xAA,0xBE,0x0F,0x04,0x02,0x04,0x08,\n0x09,0x0A,0x04,0x04,0x0A,0x09,/*\"餿\",4734*/},{\n\n0x08,0xFC,0xAA,0xAD,0xFA,0x04,0xFA,0xAF,0xAA,0xAF,0xFA,0x00,0x0F,0x04,0x02,0x0C,\n0x00,0x0A,0x06,0x03,0x06,0x0A,/*\"饃\",4735*/},{\n\n0xFA,0xAD,0xFA,0x00,0xA2,0x6B,0xBA,0xAE,0xAA,0xAB,0x22,0x0F,0x04,0x02,0x05,0x08,\n0x0A,0x0E,0x0B,0x0A,0x0F,0x08,/*\"饈\",4736*/},{\n\n0xFA,0xAD,0xFA,0x00,0xE2,0xAF,0xAA,0xFA,0xAA,0xAF,0xE2,0x0F,0x04,0x02,0x04,0x0A,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"饉\",4737*/},{\n\n0xFA,0xAD,0xFA,0x00,0xEA,0xAF,0xEA,0x0F,0xFA,0x0F,0xF8,0x0F,0x04,0x02,0x04,0x0F,\n0x02,0x0F,0x08,0x04,0x03,0x0C,/*\"饊\",4738*/},{\n\n0xFA,0xAD,0xFA,0x00,0x9F,0xE5,0xB7,0x80,0x9F,0xE5,0xB7,0x0F,0x04,0x02,0x04,0x0A,\n0x07,0x02,0x02,0x02,0x07,0x0A,/*\"饌\",4739*/},{\n\n0xFA,0xAD,0xFA,0x00,0x62,0xAE,0xEA,0xBF,0xEA,0xAE,0x62,0x0F,0x04,0x02,0x04,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"饢\",4740*/},{\n\n0x00,0xFC,0x04,0x04,0xF4,0x85,0x86,0x44,0x44,0x24,0x04,0x08,0x07,0x00,0x00,0x07,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"庀\",4741*/},{\n\n0x00,0xFE,0x4A,0xFE,0x4A,0xFA,0x4B,0xFA,0x4A,0xFA,0x4A,0x08,0x07,0x02,0x0B,0x02,\n0x0B,0x02,0x0B,0x02,0x03,0x0A,/*\"廡\",4742*/},{\n\n0x00,0xFE,0x12,0x52,0xD2,0x52,0x7F,0x52,0x52,0xD2,0x12,0x08,0x07,0x00,0x08,0x08,\n0x05,0x02,0x02,0x05,0x08,0x08,/*\"庋\",4743*/},{\n\n0x00,0xFE,0x22,0x12,0xEE,0x2A,0x2B,0xEA,0x0A,0xFA,0x02,0x08,0x07,0x00,0x00,0x07,\n0x09,0x09,0x09,0x0A,0x0B,0x0C,/*\"庖\",4744*/},{\n\n0x00,0xFE,0x22,0xF2,0x0A,0x22,0xA3,0xFA,0xA2,0x22,0x22,0x08,0x07,0x00,0x0F,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"庥\",4745*/},{\n\n0x00,0xFC,0x04,0x24,0xAC,0xB5,0xE6,0xB4,0xAC,0x24,0x04,0x08,0x07,0x02,0x02,0x02,\n0x02,0x0F,0x02,0x02,0x02,0x02,/*\"庠\",4746*/},{\n\n0x00,0xFE,0x0A,0x8A,0xBE,0xAA,0xAB,0xAA,0xBE,0x8A,0x0A,0x08,0x07,0x08,0x07,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x08,/*\"庹\",4747*/},{\n\n0x00,0xFE,0x4A,0xEA,0xBA,0xAE,0xFB,0xAA,0xBA,0xEA,0x4A,0x08,0x07,0x00,0x07,0x02,\n0x02,0x07,0x0A,0x0A,0x0B,0x0C,/*\"庵\",4748*/},{\n\n0x00,0xFE,0x02,0xE2,0x52,0x02,0xFB,0x02,0x52,0xF2,0x02,0x08,0x07,0x08,0x09,0x05,\n0x03,0x01,0x03,0x05,0x09,0x08,/*\"庾\",4749*/},{\n\n0x00,0xFE,0x02,0xFA,0xAA,0xEE,0xBB,0xAA,0xAA,0xFA,0x02,0x08,0x07,0x02,0x02,0x03,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"庳\",4750*/},{\n\n0x00,0xFE,0x0A,0xAA,0xEA,0xBE,0xAB,0xAA,0xEA,0xBE,0x0A,0x04,0x03,0x01,0x00,0x0B,\n0x06,0x03,0x06,0x0B,0x00,0x01,/*\"賡\",4751*/},{\n\n0x00,0xFE,0x82,0xAA,0xFE,0xAA,0x43,0xFE,0x12,0xF2,0x12,0x08,0x07,0x08,0x07,0x0A,\n0x0E,0x08,0x05,0x02,0x05,0x08,/*\"廒\",4752*/},{\n\n0x00,0xFE,0x0A,0xEA,0xBE,0xAA,0xEB,0xAA,0xBE,0xEA,0x0A,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"廑\",4753*/},{\n\n0x00,0xFE,0x82,0xFA,0xAA,0xAA,0xFB,0xAA,0xAA,0xFA,0x82,0x08,0x07,0x04,0x0A,0x09,\n0x0A,0x0F,0x0A,0x09,0x0A,0x04,/*\"廛\",4754*/},{\n\n0x00,0xFE,0x12,0xEA,0xAE,0xFA,0xA3,0xEA,0x9A,0xEA,0xBA,0x08,0x07,0x08,0x07,0x02,\n0x07,0x0A,0x0F,0x02,0x0F,0x02,/*\"廨\",4755*/},{\n\n0x00,0xFE,0x0A,0xFA,0x8A,0xEB,0xAE,0xEA,0x8A,0xFA,0x0A,0x08,0x07,0x0A,0x0A,0x06,\n0x02,0x0F,0x02,0x06,0x0A,0x0A,/*\"廩\",4756*/},{\n\n0x00,0xFE,0x22,0xFA,0x96,0xFA,0xAF,0xAA,0xFE,0xAA,0xAA,0x08,0x07,0x00,0x0F,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"膺\",4757*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"忄\",4758*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0x02,0xFE,0x02,0x02,0x02,0xFE,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"忉\",4759*/},{\n\n0x78,0x00,0xFF,0x08,0x00,0x48,0x88,0x08,0x08,0xFF,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x01,0x08,0x08,0x0F,0x00,/*\"忖\",4760*/},{\n\n0x30,0xFF,0x08,0xAC,0xFB,0x0C,0xFB,0xAC,0xFF,0x8A,0x4C,0x00,0x0F,0x00,0x0A,0x0F,\n0x08,0x0F,0x0A,0x03,0x04,0x0E,/*\"懺\",4761*/},{\n\n0x78,0x00,0xFF,0x08,0x24,0xFF,0x24,0xFC,0x24,0xFC,0x24,0x00,0x00,0x0F,0x00,0x0D,\n0x01,0x0D,0x01,0x0D,0x01,0x0D,/*\"憮\",4762*/},{\n\n0x78,0x00,0xFF,0x08,0x24,0xE4,0x24,0x3F,0x24,0xE4,0x04,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"忮\",4763*/},{\n\n0x78,0x00,0xFF,0x04,0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x00,0x00,0x0F,0x00,0x0F,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"慪\",4764*/},{\n\n0x78,0x00,0xFF,0x04,0xF8,0x88,0x88,0xFF,0x88,0x88,0xF8,0x00,0x00,0x0F,0x00,0x01,\n0x00,0x00,0x0F,0x00,0x00,0x01,/*\"忡\",4765*/},{\n\n0x78,0x00,0xFF,0x04,0x88,0x87,0x84,0xFC,0x84,0x84,0x80,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"忤\",4766*/},{\n\n0x78,0x00,0xFF,0x08,0x64,0xAB,0xEA,0xAA,0x6A,0xEA,0x02,0x00,0x00,0x0F,0x00,0x09,\n0x05,0x0F,0x05,0x09,0x07,0x0C,/*\"愾\",4767*/},{\n\n0x78,0x00,0xFF,0x48,0xC0,0x7F,0x55,0xD5,0x55,0x41,0x40,0x00,0x00,0x0F,0x00,0x0F,\n0x08,0x04,0x01,0x02,0x05,0x08,/*\"悵\",4768*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0xFC,0xAA,0xAD,0xAA,0xFC,0x08,0x00,0x00,0x0F,0x04,0x03,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"愴\",4769*/},{\n\n0x78,0x00,0xFF,0x24,0x18,0x87,0x60,0x00,0x07,0x18,0x20,0x00,0x00,0x0F,0x00,0x06,\n0x05,0x04,0x04,0x05,0x0E,0x00,/*\"忪\",4770*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0x08,0x08,0xF9,0x4A,0x88,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x01,/*\"忭\",4771*/},{\n\n0x78,0x00,0xFF,0x08,0x42,0xC2,0x7E,0x42,0x42,0xFE,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"忸\",4772*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0xC8,0x48,0x7F,0x48,0xC8,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"怙\",4773*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0x88,0x68,0xFF,0x68,0x89,0x0A,0x00,0x00,0x0F,0x00,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"怵\",4774*/},{\n\n0x78,0x00,0xFF,0x04,0x88,0xB2,0x82,0xFE,0x82,0xA2,0x98,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"怦\",4775*/},{\n\n0x78,0x00,0xFF,0x08,0x00,0xFE,0x22,0x22,0x22,0xFE,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"怛\",4776*/},{\n\n0x78,0x00,0xFF,0x08,0x80,0xFC,0x84,0xFF,0x84,0xFC,0x80,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"怏\",4777*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"怍\",4778*/},{\n\n0x78,0x00,0xFF,0x08,0x00,0xFE,0x12,0xD2,0x12,0x92,0x5E,0x00,0x00,0x0F,0x00,0x08,\n0x07,0x00,0x07,0x09,0x08,0x0E,/*\"怩\",4779*/},{\n\n0x78,0x00,0xFF,0x08,0xF2,0x92,0xFF,0x92,0xFF,0x92,0x9E,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x0F,0x04,0x07,/*\"怫\",4780*/},{\n\n0x78,0x00,0xFF,0x08,0x22,0x92,0x8E,0x82,0xA2,0xA2,0x9E,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"怊\",4781*/},{\n\n0x78,0x00,0xFF,0x08,0x47,0x55,0xD7,0x7D,0xD7,0x55,0x47,0x00,0x00,0x0F,0x00,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"懌\",4782*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0xD8,0x54,0x53,0x50,0xD8,0x30,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"怡\",4783*/},{\n\n0x30,0xFF,0x08,0xFA,0xAA,0xFE,0xA9,0x08,0xFF,0x08,0xF8,0x00,0x0F,0x00,0x0A,0x0A,\n0x0F,0x0A,0x08,0x07,0x08,0x0F,/*\"慟\",4784*/},{\n\n0x30,0xFF,0x08,0xFF,0x01,0xDF,0x55,0xDF,0x21,0xFF,0x25,0x00,0x0F,0x08,0x07,0x00,\n0x0F,0x05,0x0F,0x04,0x03,0x0C,/*\"懨\",4785*/},{\n\n0x78,0x00,0xFF,0x08,0xFE,0x2A,0xFE,0x00,0xFC,0x00,0xFF,0x00,0x00,0x0F,0x08,0x05,\n0x01,0x05,0x08,0x01,0x08,0x0F,/*\"惻\",4786*/},{\n\n0x78,0x00,0xFF,0x08,0xD6,0x54,0x54,0x57,0x54,0x54,0xD6,0x00,0x00,0x0F,0x00,0x09,\n0x0B,0x0D,0x09,0x0D,0x0B,0x09,/*\"愷\",4787*/},{\n\n0x78,0x00,0xFF,0x08,0x14,0xFB,0x4A,0x4A,0xFA,0x02,0xFE,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x02,0x02,0x0B,0x08,0x07,/*\"恂\",4788*/},{\n\n0x78,0x00,0xFF,0x04,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"恪\",4789*/},{\n\n0x78,0x00,0xFF,0x08,0xF3,0x55,0x55,0xFF,0x55,0x55,0xF3,0x00,0x00,0x0F,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"惲\",4790*/},{\n\n0x78,0x00,0xFF,0x04,0x1A,0x2A,0x2A,0xAF,0x6A,0x2A,0x1A,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x09,0x0F,0x01,0x01,0x01,/*\"悖\",4791*/},{\n\n0x78,0x00,0xFF,0x08,0xF4,0x94,0x94,0xFF,0x94,0x94,0xF4,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"悚\",4792*/},{\n\n0x30,0xFF,0x08,0xFE,0xAA,0xEE,0xBA,0x80,0x5E,0x22,0xDE,0x00,0x0F,0x00,0x08,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"慳\",4793*/},{\n\n0x78,0x00,0xFF,0x08,0x10,0x7F,0x49,0xFF,0x49,0x7F,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"悝\",4794*/},{\n\n0x78,0x00,0xFF,0x08,0xFE,0x92,0x52,0xFE,0x52,0x92,0xFE,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"悃\",4795*/},{\n\n0x78,0x00,0xFF,0x08,0xF0,0x97,0x95,0xF5,0x95,0x97,0xF0,0x00,0x00,0x0F,0x00,0x07,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"悒\",4796*/},{\n\n0x78,0x00,0xFF,0x08,0x74,0x55,0x56,0xFC,0x56,0x5D,0xC0,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x00,0x02,0x03,/*\"悌\",4797*/},{\n\n0x78,0x00,0xFF,0x08,0x24,0x96,0x65,0x44,0x44,0xD6,0x2C,0x00,0x00,0x0F,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"悛\",4798*/},{\n\n0x30,0xFF,0x08,0xFE,0x82,0x6A,0x8A,0xFE,0x8A,0x6A,0x82,0x00,0x0F,0x00,0x0F,0x08,\n0x0C,0x0A,0x09,0x0A,0x0C,0x08,/*\"愜\",4799*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0x5A,0x6A,0xCF,0x6A,0x5A,0x08,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"悻\",4800*/},{\n\n0x78,0x00,0xFF,0x08,0x24,0x24,0xFF,0x00,0xFF,0x24,0x24,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x0F,0x00,0x0F,0x01,0x01,/*\"悱\",4801*/},{\n\n0x78,0x00,0xFF,0x08,0xF2,0x14,0xD0,0x5F,0xD0,0x14,0xF2,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"惝\",4802*/},{\n\n0x78,0x00,0xFF,0x08,0xFE,0x56,0xDA,0x72,0x5A,0x56,0xFE,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x03,0x02,0x02,0x08,0x0F,/*\"惘\",4803*/},{\n\n0x78,0x00,0xFF,0x08,0xFF,0x21,0xA9,0xBD,0xA9,0x21,0xFF,0x00,0x00,0x0F,0x08,0x07,\n0x00,0x03,0x02,0x0B,0x08,0x0F,/*\"惆\",4804*/},{\n\n0x78,0x00,0xFF,0x08,0x24,0x53,0xAE,0x12,0x4E,0x42,0x3E,0x00,0x00,0x0F,0x04,0x03,\n0x00,0x06,0x09,0x0C,0x01,0x06,/*\"惚\",4805*/},{\n\n0x78,0x00,0xFF,0x08,0x24,0x1C,0x25,0x86,0x24,0x1C,0x24,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"悴\",4806*/},{\n\n0x78,0x00,0xFF,0x08,0x90,0xBF,0xA9,0xA7,0xA9,0xBF,0x80,0x00,0x00,0x0F,0x08,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"慍\",4807*/},{\n\n0x78,0x00,0xFF,0x08,0x20,0xEE,0xAA,0xBF,0xAA,0xEE,0x20,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"憒\",4808*/},{\n\n0x78,0x00,0xFF,0x08,0x47,0xD5,0x57,0x50,0x57,0x55,0x47,0x00,0x00,0x0F,0x00,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"愕\",4809*/},{\n\n0x78,0x00,0xFF,0x04,0x2F,0x29,0xEF,0xB9,0xAF,0xA9,0xAF,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"愣\",4810*/},{\n\n0x78,0x00,0xFF,0x04,0xAE,0xA8,0xA8,0xEF,0xA8,0xA8,0xAE,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x07,0x00,0x07,0x08,0x0F,/*\"惴\",4811*/},{\n\n0x78,0x00,0xFF,0x08,0x92,0xFE,0x51,0x08,0xFF,0x10,0x0C,0x00,0x00,0x0F,0x01,0x00,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"愀\",4812*/},{\n\n0x78,0x00,0xFF,0x08,0x02,0x7D,0xD5,0x55,0x55,0x7D,0x01,0x00,0x00,0x0F,0x00,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"愎\",4813*/},{\n\n0x78,0x00,0xFF,0x08,0x22,0xAA,0xEA,0xBF,0xAA,0x6A,0x22,0x00,0x00,0x0F,0x00,0x0A,\n0x06,0x0A,0x0F,0x02,0x06,0x0B,/*\"愫\",4814*/},{\n\n0x78,0x00,0xFF,0x48,0x55,0xFE,0x54,0xFE,0x55,0xF4,0x40,0x00,0x00,0x0F,0x04,0x03,\n0x0F,0x01,0x0F,0x03,0x05,0x08,/*\"慊\",4815*/},{\n\n0x30,0xFF,0x08,0xFE,0x22,0xAA,0xAA,0xFF,0xAA,0xFA,0x22,0x00,0x0F,0x08,0x07,0x00,\n0x0F,0x02,0x07,0x0A,0x0F,0x00,/*\"慵\",4816*/},{\n\n0x78,0x00,0xFF,0x08,0x40,0xDF,0x55,0x75,0x55,0xDF,0x40,0x00,0x00,0x0F,0x00,0x08,\n0x05,0x09,0x0F,0x01,0x05,0x08,/*\"憬\",4817*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0xFC,0x57,0x54,0xFD,0x56,0x54,0x00,0x00,0x0F,0x00,0x0C,\n0x03,0x0D,0x01,0x0D,0x01,0x0D,/*\"憔\",4818*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0xFA,0xAE,0xFB,0xAE,0xFA,0x08,0x00,0x00,0x0F,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"憧\",4819*/},{\n\n0x78,0x00,0xFF,0x04,0x52,0x7F,0x4A,0xD2,0x7F,0x4A,0xD2,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"憷\",4820*/},{\n\n0x30,0xFF,0x0A,0x3E,0xA2,0xBA,0xAB,0xBA,0x62,0x3E,0x02,0x00,0x0F,0x02,0x0A,0x06,\n0x02,0x0F,0x02,0x06,0x0A,0x02,/*\"懍\",4821*/},{\n\n0x78,0x00,0xFF,0x04,0xBA,0xAF,0xBA,0xAA,0xBA,0xAF,0xBA,0x00,0x00,0x0F,0x00,0x01,\n0x00,0x0F,0x0A,0x0F,0x00,0x01,/*\"懵\",4822*/},{\n\n0x48,0x48,0x29,0x19,0x0D,0xCB,0x09,0x19,0x29,0x48,0x48,0x00,0x04,0x02,0x01,0x08,\n0x0F,0x00,0x01,0x06,0x01,0x06,/*\"忝\",4823*/},{\n\n0x00,0x7F,0xA5,0x9B,0x50,0x4A,0x7E,0xAB,0xAE,0x7A,0x0A,0x01,0x01,0x04,0x02,0x08,\n0x0F,0x02,0x04,0x02,0x05,0x01,/*\"隳\",4824*/},{\n\n0xFF,0x15,0x95,0x9F,0x80,0x80,0x80,0x9F,0x95,0x15,0xFF,0x0F,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x08,0x0F,/*\"閂\",4825*/},{\n\n0xFF,0x15,0x55,0x5F,0x40,0x40,0x40,0x5F,0x15,0x15,0xFF,0x0F,0x00,0x04,0x05,0x05,\n0x05,0x05,0x04,0x00,0x08,0x0F,/*\"閆\",4826*/},{\n\n0xFF,0x45,0x55,0xF7,0x58,0x50,0x50,0xF7,0x45,0x45,0xFF,0x0F,0x00,0x06,0x05,0x05,\n0x0F,0x05,0x05,0x04,0x08,0x0F,/*\"闈\",4827*/},{\n\n0xFF,0x15,0x55,0x5F,0xE0,0x40,0x40,0x5F,0x55,0x15,0xFF,0x0F,0x04,0x02,0x01,0x0C,\n0x0A,0x09,0x0C,0x08,0x00,0x0F,/*\"閎\",4828*/},{\n\n0xFF,0x15,0x55,0x5F,0x60,0x40,0xC0,0x5F,0x55,0x15,0xFF,0x0F,0x00,0x08,0x09,0x05,\n0x02,0x05,0x08,0x00,0x08,0x0F,/*\"閔\",4829*/},{\n\n0xFF,0x15,0x15,0xBF,0xA0,0xB0,0xA0,0x3F,0x15,0x15,0xFF,0x0F,0x00,0x04,0x03,0x00,\n0x00,0x03,0x04,0x06,0x08,0x0F,/*\"閌\",4830*/},{\n\n0xFF,0x45,0xD7,0x00,0xA0,0xE8,0xBC,0xE8,0xA7,0x05,0xFF,0x0F,0x08,0x07,0x08,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x00,0x0F,/*\"闥\",4831*/},{\n\n0xFF,0x15,0x15,0xFF,0xA0,0xA0,0xA0,0xFF,0x15,0x15,0xFF,0x0F,0x00,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x08,0x0F,/*\"閭\",4832*/},{\n\n0xFF,0x15,0xF5,0xBF,0xA0,0xE0,0xA0,0xBF,0xF5,0x15,0xFF,0x0F,0x00,0x0F,0x0A,0x09,\n0x0F,0x09,0x0A,0x0F,0x00,0x0F,/*\"閫\",4833*/},{\n\n0xFF,0x80,0xF5,0x57,0xD5,0x18,0xD5,0x57,0x75,0x00,0xFF,0x0F,0x0A,0x0F,0x02,0x07,\n0x08,0x0F,0x09,0x0F,0x08,0x0F,/*\"鬮\",4834*/},{\n\n0xFF,0x15,0x15,0xFF,0x50,0x58,0x50,0xFF,0x15,0x15,0xFF,0x0F,0x00,0x00,0x0F,0x09,\n0x01,0x03,0x05,0x0A,0x08,0x0F,/*\"閬\",4835*/},{\n\n0xFF,0x15,0xBF,0xA0,0xA0,0x38,0xE0,0x28,0x9F,0x15,0xFF,0x0F,0x00,0x0B,0x0A,0x0B,\n0x04,0x03,0x05,0x0E,0x00,0x0F,/*\"閾\",4836*/},{\n\n0xFF,0x15,0x1F,0x80,0xF8,0xA8,0xF8,0x80,0x1F,0x15,0xFF,0x0F,0x00,0x00,0x0F,0x0A,\n0x0A,0x0A,0x0F,0x00,0x08,0x0F,/*\"閶\",4837*/},{\n\n0xFF,0x00,0x05,0xF7,0x4D,0x00,0x55,0xF7,0x05,0x00,0xFF,0x0F,0x00,0x08,0x05,0x03,\n0x01,0x07,0x09,0x0C,0x08,0x0F,/*\"鬩\",4838*/},{\n\n0xFF,0x15,0xDF,0x70,0x50,0x70,0x50,0x68,0xDF,0x15,0xFF,0x0F,0x00,0x08,0x0B,0x05,\n0x05,0x05,0x0B,0x08,0x00,0x0F,/*\"閿\",4839*/},{\n\n0xFF,0x05,0x7F,0xD4,0x94,0x9C,0xB4,0xD4,0x97,0xC5,0xFF,0x0F,0x00,0x00,0x0F,0x0A,\n0x0A,0x0A,0x0F,0x00,0x08,0x0F,/*\"閽\",4840*/},{\n\n0xFF,0x55,0xD5,0x7F,0x40,0x80,0x40,0x3F,0x55,0x95,0xFF,0x0F,0x08,0x07,0x09,0x0F,\n0x00,0x04,0x09,0x02,0x08,0x0F,/*\"閼\",4841*/},{\n\n0xFF,0x15,0x1F,0x00,0xFE,0xAA,0xFE,0x00,0x1F,0x15,0xFF,0x0F,0x00,0x0A,0x0A,0x06,\n0x03,0x06,0x0B,0x02,0x08,0x0F,/*\"闃\",4842*/},{\n\n0xFF,0x15,0x5F,0xA0,0xE0,0x80,0xF0,0xA0,0x5F,0x15,0xFF,0x0F,0x00,0x01,0x0A,0x06,\n0x03,0x06,0x0A,0x01,0x08,0x0F,/*\"闋\",4843*/},{\n\n0xFF,0x15,0x5F,0x70,0x54,0x5E,0x54,0x70,0x5F,0x15,0xFF,0x0F,0x04,0x07,0x05,0x07,\n0x05,0x07,0x05,0x07,0x04,0x0F,/*\"闔\",4844*/},{\n\n0xFF,0x05,0x07,0xE8,0x28,0xBC,0x28,0xE8,0x07,0x05,0xFF,0x0F,0x00,0x02,0x0B,0x06,\n0x03,0x06,0x0B,0x02,0x08,0x0F,/*\"闐\",4845*/},{\n\n0xFF,0xA5,0x2F,0xF0,0x28,0xA0,0x1C,0xD0,0x37,0x05,0xFF,0x0F,0x01,0x09,0x07,0x01,\n0x09,0x04,0x03,0x04,0x08,0x0F,/*\"闕\",4846*/},{\n\n0xFF,0x45,0xD5,0x77,0xC0,0x80,0x70,0x47,0xC5,0x45,0xFF,0x0F,0x04,0x07,0x05,0x0F,\n0x0A,0x05,0x02,0x05,0x08,0x0F,/*\"闞\",4847*/},{\n\n0x04,0x88,0x50,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x0F,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"丬\",4848*/},{\n\n0x00,0x40,0x40,0xCF,0x48,0x48,0x48,0x48,0x48,0xFF,0x00,0x00,0x08,0x04,0x03,0x00,\n0x00,0x00,0x00,0x00,0x0F,0x00,/*\"爿\",4849*/},{\n\n0x40,0xDE,0x50,0xFF,0x10,0x10,0xFF,0x08,0x89,0x6A,0x08,0x08,0x07,0x00,0x0F,0x08,\n0x04,0x02,0x01,0x02,0x04,0x0F,/*\"戕\",4850*/},{\n\n0x10,0x22,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x02,0x01,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"氵\",4851*/},{\n\n0x10,0x22,0x04,0x10,0x28,0x27,0x24,0xA4,0xA4,0x64,0x04,0x04,0x02,0x01,0x00,0x06,\n0x09,0x09,0x08,0x08,0x08,0x0E,/*\"汔\",4852*/},{\n\n0x22,0x44,0x00,0xFE,0x42,0x42,0x42,0x42,0x42,0x7E,0x00,0x04,0x02,0x00,0x07,0x08,\n0x08,0x08,0x08,0x08,0x08,0x0E,/*\"汜\",4853*/},{\n\n0x22,0x44,0x00,0x02,0x3E,0xC2,0x0A,0x92,0x62,0x1E,0x00,0x04,0x02,0x09,0x08,0x04,\n0x02,0x01,0x02,0x04,0x08,0x08,/*\"汊\",4854*/},{\n\n0x11,0x22,0xBC,0xAA,0xBF,0xAA,0xBF,0xAA,0xBF,0xAA,0xBC,0x04,0x02,0x08,0x0B,0x0A,\n0x0E,0x0A,0x0E,0x0A,0x0B,0x08,/*\"灃\",4855*/},{\n\n0x10,0x22,0x04,0x10,0x12,0xF2,0x12,0x12,0xF2,0x12,0x10,0x04,0x02,0x01,0x08,0x06,\n0x01,0x00,0x00,0x07,0x08,0x0E,/*\"沅\",4856*/},{\n\n0x22,0x44,0x00,0x08,0x88,0x68,0xFF,0x68,0x88,0x08,0x00,0x04,0x02,0x04,0x02,0x01,\n0x00,0x0F,0x00,0x01,0x02,0x04,/*\"沐\",4857*/},{\n\n0x11,0x22,0x00,0xF2,0x82,0x82,0xFE,0x92,0x92,0xF2,0x02,0x04,0x02,0x00,0x00,0x00,\n0x00,0x00,0x08,0x08,0x07,0x00,/*\"沔\",4858*/},{\n\n0x11,0x22,0x04,0xF4,0x84,0x84,0xFF,0x84,0x84,0xF4,0x04,0x04,0x02,0x00,0x00,0x00,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"沌\",4859*/},{\n\n0x10,0x22,0x04,0x00,0xFE,0x22,0x22,0x22,0x22,0x22,0xFE,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"汨\",4860*/},{\n\n0x10,0x22,0x04,0x00,0xFE,0x22,0x22,0x22,0x22,0x02,0xFE,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"汩\",4861*/},{\n\n0x10,0x21,0x02,0x08,0x08,0x08,0xF9,0x2A,0x48,0x88,0x08,0x04,0x02,0x01,0x00,0x00,\n0x00,0x0F,0x00,0x00,0x00,0x00,/*\"汴\",4862*/},{\n\n0x22,0x44,0x00,0x04,0x3C,0xC5,0x06,0xC4,0x3C,0x04,0x04,0x04,0x02,0x01,0x08,0x04,\n0x02,0x01,0x02,0x04,0x08,0x08,/*\"汶\",4863*/},{\n\n0x10,0x22,0x04,0x00,0x04,0xE4,0x25,0x26,0xE4,0x04,0x04,0x04,0x02,0x01,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0E,/*\"沆\",4864*/},{\n\n0x22,0x44,0x02,0xF6,0x5A,0x56,0x5A,0x51,0x79,0xC5,0x01,0x04,0x0A,0x04,0x0B,0x05,\n0x09,0x05,0x09,0x05,0x09,0x0F,/*\"潙\",4865*/},{\n\n0x22,0x44,0x00,0xFE,0x12,0xEE,0x08,0x08,0xFF,0x08,0xF8,0x04,0x02,0x00,0x0F,0x01,\n0x08,0x04,0x03,0x08,0x08,0x07,/*\"泐\",4866*/},{\n\n0x22,0x44,0x00,0x04,0xFF,0x44,0x44,0x44,0x44,0xFF,0x04,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"泔\",4867*/},{\n\n0x11,0x22,0x00,0x08,0x88,0x68,0xFF,0x68,0x89,0x0A,0x08,0x04,0x02,0x04,0x02,0x01,\n0x00,0x0F,0x00,0x01,0x02,0x04,/*\"沭\",4868*/},{\n\n0x11,0x22,0x00,0xEA,0xAE,0xAB,0xEE,0x0A,0xF7,0x55,0x5D,0x04,0x02,0x00,0x0F,0x02,\n0x0A,0x0F,0x00,0x07,0x09,0x0D,/*\"瀧\",4869*/},{\n\n0x22,0x44,0x00,0xF8,0x08,0xA8,0xFF,0xAA,0xAA,0xAA,0xD8,0x04,0x0A,0x04,0x0B,0x0E,\n0x0B,0x0E,0x0A,0x0E,0x0B,0x0E,/*\"瀘\",4870*/},{\n\n0x22,0x44,0x80,0xFC,0x84,0x84,0xFF,0x84,0x84,0xFC,0x80,0x04,0x02,0x08,0x04,0x02,\n0x01,0x00,0x01,0x02,0x04,0x08,/*\"泱\",4871*/},{\n\n0x22,0x44,0x00,0xFE,0x02,0xFE,0x02,0x02,0xFE,0x82,0xFE,0x04,0x02,0x00,0x0F,0x05,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"泗\",4872*/},{\n\n0x22,0x44,0x00,0x48,0xF4,0x47,0xFC,0x24,0x14,0xF4,0x04,0x04,0x02,0x01,0x00,0x07,\n0x08,0x0B,0x08,0x09,0x09,0x0C,/*\"沲\",4873*/},{\n\n0x10,0x22,0x04,0x10,0x48,0x44,0x53,0x64,0x48,0xD0,0x10,0x04,0x02,0x01,0x00,0x00,\n0x02,0x04,0x0A,0x01,0x00,0x00,/*\"泠\",4874*/},{\n\n0x22,0x44,0xFE,0x02,0x82,0xFD,0x00,0xFE,0x02,0x02,0xFE,0x04,0x02,0x01,0x09,0x04,\n0x03,0x00,0x0F,0x00,0x01,0x01,/*\"泖\",4875*/},{\n\n0x22,0x44,0x36,0x6D,0x00,0x3E,0xAB,0x3E,0x00,0x36,0x6D,0x04,0x02,0x09,0x05,0x03,\n0x01,0x0F,0x01,0x03,0x05,0x09,/*\"濼\",4876*/},{\n\n0x10,0x22,0x04,0x00,0x44,0x64,0x55,0xCE,0x44,0x24,0x04,0x04,0x02,0x01,0x00,0x04,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"泫\",4877*/},{\n\n0x11,0x22,0x80,0x92,0x94,0x90,0xFF,0x90,0x94,0x92,0x80,0x04,0x02,0x00,0x00,0x00,\n0x00,0x0F,0x00,0x00,0x00,0x00,/*\"泮\",4878*/},{\n\n0x22,0x44,0x00,0x0C,0xE4,0x04,0x05,0x86,0x84,0x44,0x0C,0x04,0x02,0x01,0x00,0x07,\n0x09,0x09,0x08,0x08,0x08,0x0E,/*\"沱\",4879*/},{\n\n0x11,0x22,0x00,0x79,0x49,0xCF,0x00,0xE0,0x1F,0x00,0x00,0x04,0x02,0x00,0x08,0x08,\n0x07,0x00,0x07,0x04,0x05,0x0E,/*\"泓\",4880*/},{\n\n0x11,0x22,0x00,0xFF,0x49,0x49,0x49,0xF9,0x49,0x4F,0x40,0x04,0x02,0x00,0x0F,0x04,\n0x02,0x00,0x01,0x02,0x04,0x0E,/*\"泯\",4881*/},{\n\n0x11,0x22,0x10,0x29,0x45,0x11,0x29,0x45,0x11,0x29,0x45,0x04,0x02,0x08,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x08,/*\"涇\",4882*/},{\n\n0x10,0x22,0x04,0x02,0xFA,0x4A,0x4A,0x4A,0x4A,0xFA,0x02,0x04,0x02,0x01,0x08,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"洹\",4883*/},{\n\n0x11,0x22,0x40,0x24,0xF4,0x5C,0x57,0x54,0x54,0xF4,0x04,0x04,0x02,0x00,0x00,0x0F,\n0x01,0x01,0x01,0x09,0x0F,0x00,/*\"洧\",4884*/},{\n\n0x22,0x44,0x82,0x62,0x9E,0x12,0xF2,0x00,0xFC,0x00,0xFF,0x04,0x02,0x00,0x08,0x04,\n0x03,0x00,0x00,0x09,0x08,0x0F,/*\"洌\",4885*/},{\n\n0x11,0x22,0x80,0x44,0x34,0x44,0xFF,0x44,0x34,0x44,0x80,0x04,0x02,0x08,0x08,0x04,\n0x02,0x01,0x02,0x04,0x08,0x08,/*\"浹\",4886*/},{\n\n0x10,0x21,0x02,0xF8,0xA8,0xA8,0xAF,0xAA,0xAA,0xFA,0x00,0x04,0x02,0x01,0x0B,0x06,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"湞\",4887*/},{\n\n0x10,0x21,0x02,0x00,0xFF,0x11,0x91,0x7D,0x91,0x11,0xFF,0x04,0x02,0x01,0x00,0x0F,\n0x05,0x04,0x04,0x04,0x05,0x0F,/*\"洇\",4888*/},{\n\n0x11,0x22,0x00,0xFE,0x02,0xF2,0x92,0x92,0xF2,0x02,0xFE,0x04,0x02,0x00,0x0F,0x04,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"洄\",4889*/},{\n\n0x10,0x21,0x02,0x20,0x28,0xA6,0x64,0xFF,0xA4,0x24,0x20,0x04,0x02,0x01,0x02,0x01,\n0x00,0x00,0x0F,0x00,0x01,0x02,/*\"洙\",4890*/},{\n\n0x10,0x22,0x04,0x00,0xFC,0x24,0x26,0x25,0x24,0x24,0xFC,0x04,0x02,0x01,0x00,0x0F,\n0x09,0x09,0x09,0x09,0x09,0x0F,/*\"洎\",4891*/},{\n\n0x22,0x44,0x00,0xF8,0x08,0xFC,0x0B,0xF8,0x08,0xF8,0x00,0x04,0x02,0x08,0x0F,0x08,\n0x0F,0x08,0x0F,0x08,0x0F,0x08,/*\"洫\",4892*/},{\n\n0x22,0x44,0x00,0xF4,0xB4,0xD2,0x95,0xF5,0xD2,0xB4,0xF4,0x04,0x02,0x01,0x00,0x0F,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"澮\",4893*/},{\n\n0x22,0x44,0x00,0x88,0x50,0xFF,0x00,0x00,0xFF,0x50,0x88,0x04,0x02,0x00,0x08,0x06,\n0x01,0x00,0x00,0x07,0x08,0x0E,/*\"洮\",4894*/},{\n\n0x11,0x22,0x08,0x04,0xFB,0x4A,0x4A,0x4A,0xFA,0x02,0xFE,0x04,0x02,0x01,0x00,0x07,\n0x02,0x02,0x02,0x0B,0x08,0x07,/*\"洵\",4895*/},{\n\n0x10,0x21,0x02,0x28,0xA4,0xAB,0x92,0xD2,0xAA,0xA6,0x20,0x04,0x02,0x01,0x06,0x04,\n0x04,0x04,0x0F,0x04,0x04,0x04,/*\"洚\",4896*/},{\n\n0x22,0xC4,0x4F,0x69,0xD6,0x69,0x4F,0x80,0xFC,0x00,0xFF,0x04,0x0A,0x0D,0x09,0x0F,\n0x09,0x0D,0x08,0x01,0x08,0x0F,/*\"瀏\",4897*/},{\n\n0x11,0x22,0x54,0x55,0x56,0x54,0x88,0x87,0xFC,0x84,0x80,0x04,0x02,0x0F,0x05,0x05,\n0x0F,0x00,0x00,0x0F,0x00,0x00,/*\"滸\",4898*/},{\n\n0x11,0x22,0x00,0x51,0x75,0x55,0x15,0x75,0xD5,0x5F,0x70,0x04,0x02,0x01,0x01,0x03,\n0x05,0x01,0x09,0x0F,0x01,0x01,/*\"潯\",4899*/},{\n\n0x11,0x22,0x88,0x78,0x0F,0xF8,0x00,0xFC,0x04,0x04,0xFC,0x04,0x02,0x08,0x05,0x02,\n0x05,0x08,0x07,0x02,0x02,0x07,/*\"洳\",4900*/},{\n\n0x22,0x44,0x00,0xF4,0x94,0x94,0xFF,0x94,0x94,0xF4,0x04,0x04,0x02,0x00,0x04,0x02,\n0x01,0x0F,0x01,0x02,0x04,0x04,/*\"涑\",4901*/},{\n\n0x11,0x22,0x00,0x21,0xA5,0xBD,0xA7,0xA5,0xA5,0xBD,0x21,0x04,0x02,0x01,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"浯\",4902*/},{\n\n0x22,0x44,0x00,0x44,0x34,0x44,0xFF,0x44,0x34,0x44,0x00,0x04,0x02,0x01,0x04,0x02,\n0x01,0x0F,0x01,0x02,0x04,0x04,/*\"淶\",4903*/},{\n\n0x11,0x22,0x00,0xFF,0x11,0x75,0x5F,0xD5,0x7D,0x11,0xFF,0x04,0x02,0x00,0x0F,0x08,\n0x0B,0x0A,0x0F,0x0A,0x08,0x0F,/*\"潿\",4904*/},{\n\n0x22,0x44,0x00,0x1F,0x91,0x11,0xF1,0x91,0x91,0x9F,0x00,0x04,0x02,0x09,0x04,0x03,\n0x04,0x0F,0x08,0x08,0x08,0x08,/*\"浞\",4905*/},{\n\n0x11,0x22,0x00,0xF0,0x57,0x55,0x55,0x55,0x55,0x57,0xF0,0x04,0x02,0x00,0x0F,0x01,\n0x01,0x01,0x01,0x01,0x09,0x0F,/*\"涓\",4906*/},{\n\n0x10,0x21,0x02,0x00,0x46,0x24,0x14,0x4F,0x94,0x24,0x46,0x04,0x02,0x01,0x00,0x00,\n0x01,0x01,0x09,0x05,0x03,0x00,/*\"涔\",4907*/},{\n\n0x10,0x21,0x02,0x00,0xFE,0x12,0x12,0x12,0xF1,0x11,0x10,0x04,0x02,0x01,0x09,0x05,\n0x01,0x01,0x01,0x01,0x05,0x09,/*\"浜\",4908*/},{\n\n0x11,0x22,0x00,0x90,0xD5,0xB2,0x9A,0xD2,0x92,0x95,0x90,0x04,0x02,0x00,0x00,0x07,\n0x00,0x00,0x0F,0x00,0x04,0x07,/*\"浠\",4909*/},{\n\n0x22,0x44,0x08,0xF4,0x93,0x92,0xF2,0x9A,0x96,0xF0,0x00,0x04,0x02,0x08,0x08,0x04,\n0x03,0x00,0x07,0x08,0x08,0x0C,/*\"浼\",4910*/},{\n\n0x11,0x22,0x4C,0x44,0xD4,0x55,0x56,0xD4,0x54,0x44,0x4C,0x04,0x02,0x08,0x04,0x03,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"浣\",4911*/},{\n\n0x22,0x44,0x90,0x94,0xD4,0x74,0x5F,0x54,0x5C,0x54,0xD2,0x04,0x02,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"渚\",4912*/},{\n\n0x11,0x22,0x04,0x04,0xFF,0x54,0x54,0x54,0x54,0xFF,0x04,0x04,0x02,0x01,0x09,0x05,\n0x01,0x01,0x01,0x01,0x05,0x09,/*\"淇\",4913*/},{\n\n0x11,0x22,0x88,0x68,0xFF,0x48,0x88,0xFE,0x12,0xF1,0x11,0x04,0x02,0x00,0x00,0x0F,\n0x08,0x04,0x03,0x00,0x0F,0x00,/*\"淅\",4914*/},{\n\n0x11,0x22,0x88,0x48,0xFF,0x28,0x58,0x87,0x60,0x07,0x18,0x04,0x02,0x00,0x00,0x0F,\n0x00,0x06,0x05,0x04,0x05,0x0E,/*\"淞\",4915*/},{\n\n0x22,0x44,0x3A,0xEA,0xAA,0xBA,0xAF,0xBA,0xAA,0xEA,0x3A,0x04,0x02,0x00,0x0B,0x06,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"瀆\",4916*/},{\n\n0x11,0x22,0x00,0x92,0x6A,0xA6,0x9A,0xF2,0xA2,0x12,0x0A,0x04,0x02,0x00,0x04,0x02,\n0x09,0x08,0x07,0x00,0x01,0x02,/*\"涿\",4917*/},{\n\n0x11,0x22,0x00,0x7F,0x49,0x49,0x7F,0x49,0x49,0x7F,0x00,0x04,0x02,0x01,0x09,0x07,\n0x01,0x01,0x01,0x0F,0x01,0x01,/*\"淠\",4918*/},{\n\n0x11,0x22,0xF7,0x55,0x55,0xFF,0x01,0xFF,0x55,0x55,0xF7,0x04,0x02,0x01,0x01,0x01,\n0x07,0x08,0x0F,0x09,0x09,0x0D,/*\"澠\",4919*/},{\n\n0x22,0x44,0x10,0x88,0x94,0x92,0xF1,0x92,0x94,0x88,0x10,0x04,0x02,0x08,0x0A,0x0C,\n0x08,0x0F,0x08,0x0C,0x0A,0x08,/*\"淦\",4920*/},{\n\n0x22,0x44,0xFE,0x92,0xFE,0x00,0xFE,0x42,0x7E,0x42,0x7E,0x04,0x0A,0x07,0x08,0x0F,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"淝\",4921*/},{\n\n0x10,0x22,0x04,0x00,0x86,0x92,0x92,0x93,0x92,0x92,0x86,0x04,0x02,0x01,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"淙\",4922*/},{\n\n0x22,0x44,0xA6,0xEA,0xBA,0xAA,0xFB,0xAA,0xB6,0xE2,0xA6,0x04,0x02,0x00,0x0F,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0F,0x00,/*\"瀋\",4923*/},{\n\n0x22,0x44,0x00,0x0C,0xF4,0x54,0x55,0x56,0x54,0x74,0x0C,0x04,0x02,0x01,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"涫\",4924*/},{\n\n0x22,0x44,0x20,0x6C,0xAB,0x2A,0xEA,0x2A,0xBA,0x66,0x20,0x04,0x02,0x01,0x04,0x02,\n0x09,0x0F,0x01,0x02,0x04,0x04,/*\"淥\",4925*/},{\n\n0x22,0x44,0xFF,0x29,0xF9,0x29,0xEF,0x00,0xFC,0x00,0xFF,0x04,0x0A,0x07,0x00,0x0F,\n0x02,0x03,0x00,0x09,0x08,0x0F,/*\"涮\",4926*/},{\n\n0x22,0x44,0x00,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x04,0x04,0x02,0x01,0x09,0x05,\n0x03,0x0F,0x03,0x05,0x09,0x09,/*\"渫\",4927*/},{\n\n0x11,0x22,0x00,0x7A,0x4A,0x7E,0xCA,0x7E,0x4A,0x7A,0x00,0x04,0x02,0x08,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x08,/*\"湮\",4928*/},{\n\n0x11,0x22,0x00,0xF9,0x09,0xF9,0xAD,0xAB,0xF9,0x09,0xF9,0x04,0x02,0x00,0x0F,0x04,\n0x07,0x04,0x04,0x07,0x04,0x0F,/*\"湎\",4929*/},{\n\n0x11,0x22,0x10,0xD2,0xFE,0x52,0x91,0x08,0xFF,0x10,0x0C,0x04,0x02,0x01,0x00,0x0F,\n0x00,0x08,0x06,0x01,0x06,0x08,/*\"湫\",4930*/},{\n\n0x10,0x21,0x02,0x00,0xBC,0xAA,0xA0,0xFF,0xA0,0xAA,0xBE,0x04,0x02,0x01,0x00,0x08,\n0x09,0x0A,0x04,0x04,0x0A,0x09,/*\"溲\",4931*/},{\n\n0x22,0x44,0x00,0xBE,0xAA,0xAB,0xAA,0xAA,0xAA,0xBE,0x00,0x04,0x02,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"湟\",4932*/},{\n\n0x11,0x22,0x48,0x54,0xF3,0x54,0x48,0xF7,0x04,0xFC,0x04,0x04,0x02,0x02,0x09,0x0F,\n0x01,0x0A,0x05,0x02,0x05,0x08,/*\"漵\",4933*/},{\n\n0x11,0x22,0x00,0x44,0x2A,0x19,0x08,0x48,0x49,0x3A,0x04,0x04,0x02,0x08,0x0F,0x09,\n0x0F,0x09,0x0F,0x09,0x0F,0x08,/*\"湓\",4934*/},{\n\n0x22,0x44,0x00,0xF4,0x55,0x56,0xF4,0x04,0xE6,0x05,0xF4,0x04,0x02,0x00,0x0F,0x01,\n0x09,0x0F,0x00,0x03,0x08,0x0F,/*\"湔\",4935*/},{\n\n0x22,0x44,0x00,0x06,0xEA,0xAA,0xAB,0xAA,0xAA,0xEA,0x06,0x04,0x02,0x00,0x08,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"渲\",4936*/},{\n\n0x11,0x22,0x00,0xFF,0x05,0x95,0xD5,0xB5,0x95,0xD5,0x97,0x04,0x02,0x08,0x07,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"渥\",4937*/},{\n\n0x11,0x22,0x00,0xFF,0x09,0xE9,0xA9,0xAF,0xA9,0xA9,0xEF,0x04,0x02,0x08,0x07,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x0F,/*\"湄\",4938*/},{\n\n0x11,0x22,0xBC,0xAA,0xBF,0xAA,0xBC,0x6A,0x5F,0x6A,0x08,0x04,0x02,0x0B,0x0E,0x0A,\n0x0E,0x0B,0x0F,0x09,0x0F,0x08,/*\"灩\",4939*/},{\n\n0x22,0x44,0x00,0xA2,0x6A,0xBA,0xAF,0xAA,0x6A,0xA2,0x20,0x04,0x02,0x00,0x0A,0x06,\n0x02,0x0F,0x02,0x06,0x0A,0x01,/*\"溱\",4940*/},{\n\n0x22,0x44,0x00,0x48,0x6A,0x5A,0x4F,0x4A,0x6A,0x48,0x08,0x04,0x02,0x08,0x0F,0x09,\n0x0F,0x09,0x0F,0x09,0x0F,0x08,/*\"溘\",4941*/},{\n\n0x11,0x22,0x40,0xD1,0x5F,0xD5,0x55,0xD5,0x7F,0xC9,0x40,0x04,0x02,0x04,0x07,0x05,\n0x0F,0x04,0x07,0x05,0x0F,0x02,/*\"灄\",4942*/},{\n\n0x22,0x44,0x00,0x52,0x52,0xB7,0x1A,0x12,0xB7,0x5A,0x52,0x04,0x02,0x00,0x01,0x09,\n0x07,0x01,0x01,0x0F,0x01,0x01,/*\"漭\",4943*/},{\n\n0x11,0x22,0x64,0xB2,0xAF,0xB4,0xA2,0xB4,0xAF,0xB4,0x62,0x04,0x02,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0E,0x0A,0x08,/*\"瀅\",4944*/},{\n\n0x22,0x44,0x00,0xFA,0x2A,0x2A,0xFF,0x2A,0x2B,0xFA,0x02,0x04,0x02,0x00,0x02,0x06,\n0x0A,0x02,0x0A,0x0F,0x02,0x02,/*\"溥\",4945*/},{\n\n0x11,0x22,0x81,0xBD,0xA5,0xBF,0xE5,0xBF,0xA5,0xBD,0x81,0x04,0x02,0x04,0x04,0x02,\n0x01,0x0F,0x01,0x02,0x04,0x04,/*\"溧\",4946*/},{\n\n0x11,0x22,0x00,0xFF,0x11,0xF5,0x95,0x35,0x55,0xB5,0x91,0x04,0x02,0x08,0x07,0x02,\n0x06,0x02,0x0A,0x0F,0x02,0x02,/*\"溽\",4947*/},{\n\n0x11,0x22,0x40,0xC0,0x5F,0xD5,0x15,0x55,0xD5,0x5F,0xC0,0x04,0x02,0x04,0x02,0x09,\n0x0F,0x00,0x04,0x02,0x09,0x0F,/*\"溻\",4948*/},{\n\n0x11,0x22,0x00,0xFF,0xA5,0x55,0xAD,0xF5,0xA5,0x15,0xFF,0x04,0x02,0x00,0x0F,0x0A,\n0x09,0x0A,0x0B,0x08,0x09,0x0F,/*\"溷\",4949*/},{\n\n0x22,0x44,0x02,0x11,0x57,0x55,0xFE,0x55,0x57,0x7D,0x11,0x04,0x02,0x00,0x04,0x05,\n0x05,0x0F,0x05,0x05,0x05,0x04,/*\"潷\",4950*/},{\n\n0x22,0x44,0x00,0xFE,0xAA,0xAB,0xAA,0xAA,0xAA,0xFE,0x00,0x04,0x02,0x0A,0x0A,0x0A,\n0x06,0x03,0x06,0x0B,0x0A,0x0A,/*\"溴\",4951*/},{\n\n0x22,0x44,0x20,0x22,0x51,0x54,0xC8,0x54,0x51,0x22,0x20,0x04,0x02,0x08,0x09,0x0D,\n0x09,0x0F,0x09,0x0D,0x09,0x08,/*\"滏\",4952*/},{\n\n0x22,0x44,0x00,0xFE,0x22,0xAA,0xAA,0xFF,0xAA,0xFA,0x22,0x04,0x02,0x08,0x07,0x00,\n0x0E,0x0A,0x0B,0x0A,0x0E,0x00,/*\"溏\",4953*/},{\n\n0x22,0x44,0x00,0xB2,0x96,0x9A,0xB3,0xD2,0x9A,0x96,0xB2,0x04,0x02,0x00,0x08,0x04,\n0x03,0x02,0x02,0x0A,0x0A,0x06,/*\"滂\",4954*/},{\n\n0x22,0x44,0x03,0x7D,0x55,0x55,0xD5,0x55,0x55,0x7D,0x03,0x04,0x02,0x01,0x09,0x05,\n0x01,0x01,0x01,0x05,0x09,0x01,/*\"溟\",4955*/},{\n\n0x11,0x22,0x08,0xEA,0xAF,0xAA,0xFA,0xAA,0xAF,0xEA,0x08,0x04,0x02,0x00,0x0B,0x06,\n0x02,0x03,0x02,0x06,0x0B,0x00,/*\"潢\",4956*/},{\n\n0x22,0x44,0x39,0x94,0xD3,0xB4,0x99,0x94,0x53,0x14,0x39,0x04,0x02,0x08,0x06,0x02,\n0x0B,0x0E,0x02,0x02,0x07,0x0A,/*\"瀠\",4957*/},{\n\n0x22,0x44,0x2A,0xEF,0x2A,0xFE,0x2A,0xEA,0xAF,0xFA,0x22,0x04,0x02,0x08,0x07,0x01,\n0x0F,0x01,0x0E,0x02,0x0F,0x00,/*\"瀟\",4958*/},{\n\n0x22,0x44,0x12,0x8A,0xBF,0x8A,0xD0,0x8A,0xBF,0x8A,0x92,0x04,0x02,0x00,0x08,0x0A,\n0x0B,0x04,0x04,0x0B,0x08,0x00,/*\"漤\",4959*/},{\n\n0x22,0x44,0x02,0xFA,0xAA,0xFF,0xAA,0xFF,0xAA,0xFA,0x02,0x04,0x02,0x00,0x00,0x0F,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"漕\",4960*/},{\n\n0x11,0x22,0x00,0xFC,0x94,0x94,0xBF,0xD5,0x55,0x45,0x6C,0x04,0x02,0x08,0x07,0x02,\n0x03,0x0A,0x0F,0x02,0x03,0x02,/*\"滹\",4961*/},{\n\n0x10,0x21,0x02,0x00,0x5F,0x75,0xD5,0x5F,0x35,0x95,0x1F,0x04,0x02,0x01,0x08,0x05,\n0x01,0x09,0x0F,0x01,0x05,0x09,/*\"漯\",4962*/},{\n\n0x22,0x44,0x00,0xEE,0xAA,0xAA,0xFF,0xAA,0xAA,0xEE,0x00,0x04,0x02,0x08,0x06,0x00,\n0x06,0x09,0x0A,0x0C,0x02,0x0C,/*\"漶\",4963*/},{\n\n0x11,0x22,0xD4,0x52,0xD1,0x52,0xD4,0xEC,0x0B,0xF8,0x08,0x04,0x02,0x09,0x07,0x09,\n0x07,0x09,0x04,0x03,0x04,0x08,/*\"瀲\",4964*/},{\n\n0x22,0x44,0x4A,0x26,0xFA,0x90,0xD4,0x7F,0x54,0xD8,0x16,0x04,0x02,0x0A,0x09,0x07,\n0x00,0x0F,0x05,0x05,0x0F,0x00,/*\"瀦\",4965*/},{\n\n0x22,0x44,0x8A,0x44,0xFB,0x10,0xDA,0x56,0xD3,0x16,0xFA,0x04,0x02,0x08,0x08,0x07,\n0x00,0x07,0x02,0x03,0x08,0x0F,/*\"漪\",4966*/},{\n\n0x22,0x44,0x00,0xFE,0x2A,0xAA,0x3E,0x2B,0xBE,0x2A,0xBA,0x04,0x02,0x08,0x07,0x00,\n0x0F,0x09,0x00,0x07,0x09,0x0C,/*\"漉\",4967*/},{\n\n0x22,0x44,0xFD,0x26,0xE4,0x08,0xD7,0x14,0xF4,0x14,0x34,0x04,0x0A,0x07,0x08,0x0F,\n0x08,0x07,0x08,0x0F,0x09,0x09,/*\"漩\",4968*/},{\n\n0x11,0x22,0x08,0xF9,0xAD,0xFB,0x10,0xEC,0x0B,0xF8,0x08,0x04,0x02,0x02,0x03,0x02,\n0x0F,0x09,0x04,0x03,0x04,0x08,/*\"澉\",4969*/},{\n\n0x22,0x44,0x02,0xEA,0xAF,0xEA,0x02,0x48,0x88,0xFF,0x08,0x04,0x02,0x08,0x0A,0x04,\n0x06,0x04,0x00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6A,0xAA,0x26,0x01,0x00,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x00,0x01,/*\"謇\",5008*/},{\n\n0x10,0x11,0xF2,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x04,0x03,0x04,0x08,\n0x08,0x08,0x08,0x08,0x08,0x08,/*\"辶\",5009*/},{\n\n0x10,0x11,0xF2,0x00,0x19,0x95,0x51,0x31,0xFF,0x11,0x11,0x08,0x04,0x03,0x04,0x09,\n0x08,0x08,0x0A,0x0B,0x08,0x08,/*\"迓\",5010*/},{\n\n0x10,0x11,0xF2,0x00,0x48,0x47,0x44,0xFC,0x44,0x44,0x40,0x08,0x04,0x03,0x04,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"迕\",5011*/},{\n\n0x10,0x11,0xF2,0x00,0xFE,0x02,0xFA,0x8A,0xFA,0x02,0xFE,0x08,0x04,0x03,0x04,0x0B,\n0x08,0x08,0x08,0x08,0x0A,0x0B,/*\"迥\",5012*/},{\n\n0x10,0x11,0xF2,0x00,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x08,0x04,0x03,0x04,0x08,\n0x08,0x0F,0x09,0x09,0x09,0x09,/*\"迮\",5013*/},{\n\n0x11,0xF2,0x00,0x24,0xFA,0x23,0xFE,0x12,0x8A,0xFA,0x02,0x08,0x07,0x08,0x08,0x09,\n0x0A,0x0A,0x0A,0x0A,0x0A,0x0B,/*\"迤\",5014*/},{\n\n0x11,0xF2,0x00,0xFD,0xAB,0x49,0xFF,0xA9,0x49,0xAB,0xFD,0x08,0x07,0x08,0x0F,0x0A,\n0x09,0x0F,0x0A,0x09,0x0A,0x0F,/*\"邇\",5015*/},{\n\n0x11,0xF2,0x00,0x84,0x7F,0x04,0xFC,0x00,0xFC,0x04,0xFC,0x08,0x07,0x0A,0x09,0x08,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"迦\",5016*/},{\n\n0x11,0xF2,0x00,0x92,0xAA,0x82,0x92,0xAA,0x82,0x92,0x2A,0x08,0x07,0x0A,0x0A,0x0A,\n0x0A,0x0B,0x0A,0x0A,0x0A,0x0A,/*\"逕\",5017*/},{\n\n0x10,0x11,0xF2,0x08,0xEC,0x2A,0x29,0x28,0x2A,0xEC,0x18,0x08,0x04,0x03,0x04,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"迨\",5018*/},{\n\n0x11,0xF2,0x00,0xFE,0x12,0xD2,0x52,0x51,0x51,0xD1,0x10,0x08,0x07,0x0A,0x09,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"逅\",5019*/},{\n\n0x10,0x11,0xF2,0x00,0x14,0x56,0x4B,0xEA,0x4A,0x56,0x10,0x08,0x04,0x03,0x04,0x0B,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"逄\",5020*/},{\n\n0x11,0xF2,0x02,0xFA,0xAA,0xAA,0xFF,0xAA,0xAA,0xFB,0x02,0x08,0x07,0x08,0x0B,0x08,\n0x08,0x09,0x08,0x0A,0x0B,0x08,/*\"逋\",5021*/},{\n\n0x11,0xF2,0x01,0xFB,0xA9,0xFB,0xAC,0xFB,0xA9,0xEB,0x09,0x08,0x07,0x0A,0x09,0x08,\n0x0B,0x0A,0x08,0x0B,0x0A,0x0B,/*\"邐\",5022*/},{\n\n0x10,0x11,0xF2,0x00,0x14,0xA4,0x44,0xFF,0x44,0xA5,0x14,0x08,0x04,0x03,0x04,0x09,\n0x08,0x0A,0x0B,0x08,0x08,0x09,/*\"逑\",5023*/},{\n\n0x10,0x11,0xF2,0x00,0xF9,0xAA,0xA8,0xAF,0xA8,0xAA,0xF9,0x08,0x04,0x03,0x04,0x0B,\n0x08,0x08,0x08,0x08,0x0A,0x0B,/*\"逍\",5024*/},{\n\n0x11,0xF2,0x00,0x4A,0x24,0xFB,0x00,0x90,0x7F,0x90,0x12,0x08,0x07,0x08,0x0A,0x0A,\n0x09,0x0A,0x09,0x08,0x08,0x0B,/*\"逖\",5025*/},{\n\n0x11,0xF2,0x20,0x94,0x4E,0xB5,0x24,0x24,0xEC,0x16,0x24,0x08,0x07,0x08,0x08,0x0C,\n0x0A,0x09,0x09,0x0A,0x0C,0x08,/*\"逡\",5026*/},{\n\n0x10,0x11,0xF2,0x00,0x48,0xAA,0x9A,0xCF,0x9A,0xAA,0x48,0x08,0x04,0x03,0x04,0x0A,\n0x0A,0x0A,0x0B,0x0A,0x0A,0x0A,/*\"逵\",5027*/},{\n\n0x11,0xF2,0x08,0xAA,0x9A,0xCA,0xBF,0x89,0x99,0xA8,0x88,0x08,0x07,0x08,0x08,0x0D,\n0x0A,0x0A,0x0A,0x0A,0x0D,0x08,/*\"逶\",5028*/},{\n\n0x11,0xF2,0x00,0x06,0xFA,0xAA,0xAA,0xAB,0xAA,0xBA,0x06,0x08,0x07,0x08,0x08,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"逭\",5029*/},{\n\n0x11,0xF2,0x00,0x51,0x95,0x15,0xF5,0x15,0x95,0x5F,0x10,0x08,0x07,0x0A,0x09,0x08,\n0x0A,0x0B,0x08,0x08,0x09,0x0A,/*\"逯\",5030*/},{\n\n0x10,0x11,0xF2,0x00,0xD6,0x54,0xD4,0x77,0xD4,0x54,0xD6,0x08,0x04,0x03,0x04,0x0B,\n0x08,0x09,0x08,0x09,0x0A,0x0B,/*\"遄\",5031*/},{\n\n0x11,0xF2,0x20,0xBE,0xAA,0xAB,0xEA,0xAA,0xAA,0xBE,0x20,0x08,0x07,0x0A,0x0A,0x0A,\n0x0A,0x0B,0x0A,0x0A,0x0A,0x0A,/*\"遑\",5032*/},{\n\n0x11,0xF2,0x00,0xFA,0xAB,0x9E,0x8A,0x9E,0xAB,0xFA,0x02,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"遒\",5033*/},{\n\n0x11,0xF2,0x00,0xFF,0xA9,0xAF,0x00,0x55,0x95,0x77,0x00,0x08,0x07,0x08,0x0B,0x08,\n0x08,0x0A,0x09,0x08,0x09,0x0A,/*\"遐\",5034*/},{\n\n0x11,0xF2,0x20,0xEA,0xBF,0xAA,0x28,0x34,0xC7,0x3C,0x04,0x08,0x07,0x0A,0x09,0x0A,\n0x0B,0x0A,0x09,0x08,0x0B,0x08,/*\"遨\",5035*/},{\n\n0x11,0xF2,0x08,0xEA,0xAF,0xAA,0xFA,0xAA,0xAF,0xEA,0x08,0x08,0x07,0x0A,0x0F,0x0A,\n0x0A,0x0B,0x0A,0x0A,0x0F,0x0A,/*\"遘\",5036*/},{\n\n0x11,0xF2,0x00,0xC0,0x5F,0xD5,0x15,0xD5,0x5F,0xC0,0x00,0x08,0x07,0x08,0x0A,0x0D,\n0x0F,0x08,0x0A,0x0D,0x0F,0x08,/*\"遢\",5037*/},{\n\n0x11,0xF2,0x00,0xEF,0xA9,0xB4,0xE9,0xA7,0xA9,0xEF,0x00,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0B,0x0A,0x0A,0x0B,0x08,/*\"遛\",5038*/},{\n\n0x11,0xF2,0x00,0x8F,0xE9,0xB9,0xAB,0xFD,0xA9,0xA9,0x2F,0x08,0x07,0x08,0x08,0x0F,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"暹\",5039*/},{\n\n0x11,0xF2,0x00,0x95,0x6E,0xC4,0x1F,0x44,0xEE,0x55,0x44,0x08,0x07,0x0A,0x09,0x0E,\n0x09,0x0B,0x0A,0x0F,0x0A,0x0A,/*\"遴\",5040*/},{\n\n0x10,0x11,0xF2,0x00,0xFC,0x54,0x54,0xFF,0x55,0x55,0x6D,0x08,0x04,0x03,0x04,0x0B,\n0x0D,0x0D,0x0A,0x0F,0x0A,0x0D,/*\"遽\",5041*/},{\n\n0x21,0xE2,0x04,0xFB,0xAA,0xFA,0xAE,0xF9,0x27,0xF9,0x2F,0x08,0x07,0x0A,0x09,0x08,\n0x09,0x0A,0x0B,0x09,0x0F,0x09,/*\"邂\",5042*/},{\n\n0x21,0xE2,0xA4,0x5A,0xAD,0xC4,0x3E,0xEB,0x2A,0xEA,0x3E,0x08,0x07,0x0A,0x09,0x0A,\n0x0B,0x0C,0x0B,0x08,0x0B,0x0A,/*\"邈\",5043*/},{\n\n0x11,0xF2,0x00,0xA6,0xAA,0x76,0xE3,0xA2,0x36,0xAA,0x26,0x08,0x07,0x08,0x0A,0x0A,\n0x0D,0x0A,0x0F,0x09,0x0A,0x0C,/*\"邃\",5044*/},{\n\n0x11,0xF2,0x00,0xFA,0x8D,0xD8,0xAA,0xAD,0xD8,0x8A,0xFD,0x08,0x07,0x08,0x0F,0x0A,\n0x08,0x0F,0x0A,0x08,0x0B,0x0C,/*\"邋\",5045*/},{\n\n0x02,0x22,0x22,0x22,0x22,0x22,0x22,0x22,0x22,0xFE,0x00,0x04,0x04,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"彐\",5046*/},{\n\n0x2A,0xAA,0xFF,0xAA,0xAA,0x80,0xAA,0xAA,0xFF,0xAA,0x2A,0x00,0x08,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"彗\",5047*/},{\n\n0x20,0xA0,0xAC,0x6B,0x6A,0xAA,0x2A,0x3A,0xA6,0x60,0x20,0x08,0x0A,0x0A,0x05,0x05,\n0x0A,0x0F,0x01,0x02,0x04,0x04,/*\"彖\",5048*/},{\n\n0x20,0xE0,0x2C,0x2B,0xEA,0xAA,0xAA,0x3A,0xE6,0x20,0xA0,0x00,0x0F,0x09,0x05,0x0A,\n0x07,0x0A,0x00,0x07,0x09,0x0C,/*\"彘\",5049*/},{\n\n0x00,0xFF,0x09,0x49,0x49,0xF9,0x49,0x49,0xC9,0x09,0x0F,0x08,0x07,0x00,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0C,/*\"尻\",5050*/},{\n\n0x00,0xFF,0x21,0xE1,0x3F,0x00,0x1F,0xD1,0x11,0x51,0x9F,0x08,0x07,0x00,0x00,0x01,\n0x02,0x05,0x08,0x08,0x08,0x09,/*\"咫\",5051*/},{\n\n0x00,0xFF,0x25,0x95,0x4D,0xA5,0xA5,0xFD,0xA5,0xA5,0x27,0x08,0x07,0x01,0x0F,0x00,\n0x08,0x0B,0x04,0x06,0x09,0x08,/*\"屐\",5052*/},{\n\n0x00,0xFF,0x05,0xF5,0x55,0xB5,0xC5,0x55,0xD5,0xF5,0x17,0x08,0x07,0x00,0x0F,0x02,\n0x01,0x03,0x02,0x0B,0x0F,0x00,/*\"屙\",5053*/},{\n\n0x00,0xFF,0x85,0x95,0x95,0x55,0x75,0x9D,0x95,0x95,0x07,0x08,0x07,0x0A,0x0E,0x03,\n0x02,0x00,0x0A,0x0E,0x03,0x02,/*\"孱\",5054*/},{\n\n0x00,0xFF,0xA5,0xD5,0x2D,0x45,0x75,0x45,0x7D,0x55,0x57,0x08,0x07,0x00,0x0F,0x00,\n0x08,0x06,0x08,0x0F,0x0A,0x0A,/*\"屣\",5055*/},{\n\n0x00,0xFF,0x55,0xED,0x15,0x7D,0x55,0xFD,0x55,0x7D,0x17,0x08,0x07,0x00,0x0F,0x00,\n0x09,0x0B,0x05,0x05,0x0B,0x01,/*\"屨\",5056*/},{\n\n0x00,0xFF,0x05,0x55,0x9D,0x55,0x35,0x55,0x9D,0x55,0x07,0x08,0x07,0x04,0x0D,0x07,\n0x05,0x00,0x05,0x0F,0x05,0x05,/*\"羼\",5057*/},{\n\n0xF2,0x92,0x9E,0x00,0x12,0xAA,0x92,0xAA,0x92,0xAA,0x02,0x08,0x08,0x07,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"弳\",5058*/},{\n\n0x12,0xB6,0xAB,0xAA,0xB6,0xA0,0xB6,0xAA,0xAA,0xF6,0x10,0x00,0x03,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0A,0x06,/*\"弩\",5059*/},{\n\n0xF2,0x92,0x9E,0x00,0x02,0xFE,0x52,0x52,0x52,0xFE,0x02,0x08,0x08,0x07,0x00,0x02,\n0x03,0x02,0x02,0x02,0x0F,0x01,/*\"弭\",5060*/},{\n\n0x74,0x54,0xFF,0x54,0xFF,0x54,0xFC,0x93,0xFA,0x96,0xF0,0x08,0x06,0x01,0x00,0x0F,\n0x02,0x07,0x08,0x08,0x08,0x0E,/*\"艴\",5061*/},{\n\n0xF2,0x92,0x9E,0x00,0xFA,0x4E,0xFA,0x00,0xF2,0x92,0x9E,0x08,0x08,0x07,0x00,0x0F,\n0x04,0x0F,0x00,0x08,0x08,0x07,/*\"弼\",5062*/},{\n\n0x5D,0x77,0xC0,0x55,0x4C,0x7F,0x4C,0x55,0xC0,0x5D,0x77,0x0F,0x01,0x05,0x07,0x05,\n0x0D,0x05,0x07,0x05,0x09,0x0F,/*\"鬻\",5063*/},{\n\n0x7C,0x40,0x40,0x40,0x40,0xFF,0x40,0x40,0x40,0x40,0xFC,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"屮\",5064*/},{\n\n0x88,0x78,0x0F,0xF8,0x10,0x08,0x27,0xC4,0x04,0x04,0xFC,0x08,0x05,0x02,0x05,0x08,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"妁\",5065*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xE2,0x22,0x22,0x22,0x3E,0x00,0x08,0x05,0x02,0x05,0x08,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"妃\",5066*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x22,0xFE,0x22,0x22,0xFE,0x22,0x08,0x05,0x02,0x05,0x08,\n0x06,0x01,0x00,0x00,0x0F,0x00,/*\"妍\",5067*/},{\n\n0xF8,0x0F,0xF8,0x08,0x24,0xFF,0x24,0xFC,0x24,0xFC,0x24,0x0D,0x02,0x05,0x00,0x0D,\n0x01,0x0D,0x01,0x0D,0x01,0x0D,/*\"嫵\",5068*/},{\n\n0xF8,0x0F,0xF8,0x00,0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x0D,0x02,0x05,0x00,0x0F,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"嫗\",5069*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFF,0x10,0x10,0xFF,0x10,0x0C,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x04,0x02,0x07,0x08,0x0E,/*\"妣\",5070*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0x90,0x8C,0xA3,0x8C,0x90,0x20,0x08,0x05,0x02,0x05,0x08,\n0x00,0x00,0x08,0x06,0x01,0x00,/*\"妗\",5071*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x78,0x48,0xFF,0x44,0x44,0xC0,0x08,0x05,0x02,0x0D,0x04,\n0x02,0x01,0x0F,0x00,0x02,0x03,/*\"姊\",5072*/},{\n\n0xF8,0x0F,0xF8,0x02,0xF6,0x5A,0x56,0x5A,0x79,0xC5,0x01,0x0D,0x02,0x05,0x0A,0x05,\n0x09,0x05,0x09,0x05,0x09,0x0F,/*\"嬀\",5073*/},{\n\n0x88,0x78,0x0F,0xF8,0x42,0xC2,0x7E,0x42,0x42,0xFE,0x00,0x08,0x05,0x02,0x05,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"妞\",5074*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0x22,0x2A,0xF2,0x2A,0x26,0x60,0x08,0x05,0x02,0x05,0x08,\n0x00,0x08,0x0F,0x00,0x00,0x00,/*\"妤\",5075*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xF8,0x82,0x44,0x00,0xFF,0x00,0x08,0x05,0x02,0x0D,0x00,\n0x01,0x08,0x04,0x02,0x01,0x0E,/*\"姒\",5076*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFE,0x12,0x12,0x12,0xFE,0x00,0x08,0x05,0x02,0x05,0x08,\n0x09,0x09,0x09,0x09,0x09,0x08,/*\"妲\",5077*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xF8,0x48,0xFF,0x48,0x48,0xF8,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x04,0x07,0x04,0x04,0x0F,/*\"妯\",5078*/},{\n\n0xF8,0x0F,0xF8,0x40,0xFE,0x42,0xFE,0x42,0xFE,0x42,0xFE,0x0D,0x02,0x05,0x00,0x0F,\n0x00,0x03,0x00,0x03,0x08,0x0F,/*\"姍\",5079*/},{\n\n0xA0,0xA4,0xAC,0xB4,0xE5,0xA6,0xA4,0xB4,0xAC,0xA4,0xA0,0x08,0x08,0x0A,0x0B,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x00,/*\"妾\",5080*/},{\n\n0xF8,0x0F,0xF8,0x00,0xF2,0x12,0x1E,0x02,0x1E,0x12,0xF2,0x0D,0x02,0x05,0x00,0x09,\n0x09,0x0F,0x08,0x0F,0x09,0x09,/*\"婭\",5081*/},{\n\n0xF8,0x0F,0xF8,0x00,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x0D,0x02,0x05,0x00,0x0A,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"嬈\",5082*/},{\n\n0x88,0x78,0x0F,0xF8,0x28,0x26,0xA4,0xFF,0xA4,0x24,0x20,0x08,0x05,0x02,0x05,0x0A,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"姝\",5083*/},{\n\n0x56,0x1D,0x54,0x00,0xBA,0x2B,0x3A,0x00,0x56,0x1D,0x54,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"孌\",5084*/},{\n\n0x88,0x78,0x0F,0xF8,0x40,0x24,0xD5,0x06,0xD4,0x24,0x44,0x08,0x05,0x02,0x0D,0x00,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"姣\",5085*/},{\n\n0x88,0x78,0x0F,0xF8,0x80,0x89,0xFA,0x88,0x88,0xFA,0x89,0x08,0x05,0x02,0x0D,0x00,\n0x08,0x07,0x00,0x00,0x0F,0x00,/*\"姘\",5086*/},{\n\n0x88,0x78,0x0F,0xF8,0x40,0x42,0x42,0xFE,0x21,0x21,0x20,0x08,0x05,0x02,0x05,0x08,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"奼\",5087*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x7F,0x49,0xFF,0x49,0x7F,0x00,0x08,0x05,0x02,0x05,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"娌\",5088*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xBE,0xAA,0xBF,0xAA,0xAA,0xBE,0x08,0x05,0x02,0x05,0x08,\n0x00,0x03,0x02,0x0A,0x0A,0x06,/*\"娉\",5089*/},{\n\n0xF8,0x0F,0xF8,0x00,0xE0,0x3F,0xA5,0xBD,0xA1,0x3F,0xE0,0x0D,0x02,0x05,0x00,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"媧\",5090*/},{\n\n0xF8,0x0F,0xF8,0x00,0xFF,0x15,0xFF,0xA0,0xFF,0x15,0xFF,0x0D,0x02,0x05,0x00,0x0F,\n0x08,0x07,0x0A,0x0F,0x00,0x0F,/*\"嫺\",5091*/},{\n\n0xA2,0x94,0x81,0xA2,0xE8,0xA6,0xA0,0x9F,0x90,0x92,0x84,0x08,0x08,0x0A,0x0B,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x00,/*\"娑\",5092*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x75,0x56,0xFC,0x56,0x5D,0xC0,0x08,0x05,0x02,0x05,0x0C,\n0x02,0x01,0x0F,0x00,0x02,0x03,/*\"娣\",5093*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xFF,0xA5,0xA5,0xE5,0x55,0x57,0x08,0x05,0x02,0x05,0x08,\n0x07,0x02,0x02,0x07,0x09,0x0D,/*\"娓\",5094*/},{\n\n0xF8,0x0F,0xF8,0x00,0xFE,0x32,0xCE,0xF8,0x8A,0xFE,0x02,0x0D,0x02,0x05,0x00,0x0F,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"婀\",5095*/},{\n\n0x88,0x78,0x0F,0xF8,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"婧\",5096*/},{\n\n0x88,0x78,0x0F,0xF8,0x44,0x54,0xD4,0x7F,0xD4,0x54,0x44,0x08,0x05,0x02,0x0D,0x02,\n0x01,0x0F,0x04,0x01,0x06,0x09,/*\"婊\",5097*/},{\n\n0x88,0x78,0x0F,0xF8,0x20,0xAA,0xAA,0xFF,0xAA,0xFA,0x22,0x08,0x05,0x02,0x05,0x08,\n0x06,0x08,0x0F,0x0A,0x0A,0x08,/*\"婕\",5098*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xC0,0x5F,0x55,0x55,0x5F,0xC0,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x05,0x05,0x05,0x05,0x0F,/*\"娼\",5099*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x08,0x05,0x02,0x05,0x0A,\n0x03,0x02,0x02,0x0F,0x02,0x02,/*\"婢\",5100*/},{\n\n0x88,0x78,0x0F,0xF8,0x07,0xF5,0x57,0xF0,0x57,0xF5,0x07,0x08,0x05,0x02,0x0D,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"嬋\",5101*/},{\n\n0x12,0xD6,0x4B,0x4A,0xD6,0x60,0xD6,0x4A,0x4A,0xD6,0x10,0x00,0x0F,0x00,0x01,0x04,\n0x02,0x04,0x01,0x08,0x0F,0x00,/*\"胬\",5102*/},{\n\n0xF8,0x0F,0xF8,0x00,0x80,0xBF,0xA9,0xA7,0xA9,0xBF,0x80,0x0D,0x02,0x05,0x08,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"媼\",5103*/},{\n\n0xF8,0x0F,0xF8,0x00,0x56,0x5A,0xD6,0x7A,0x52,0x59,0x55,0x0D,0x02,0x05,0x00,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"媛\",5104*/},{\n\n0x88,0x78,0x0F,0xF8,0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x08,0x05,0x02,0x0D,0x01,\n0x02,0x0A,0x0E,0x02,0x02,0x01,/*\"婷\",5105*/},{\n\n0x48,0x29,0x5B,0x7D,0x8B,0x18,0x44,0x2B,0x12,0x2E,0x42,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"婺\",5106*/},{\n\n0x88,0x78,0x0F,0xF8,0x08,0xEA,0xAF,0xFA,0xAF,0xEA,0x08,0x08,0x05,0x02,0x0D,0x02,\n0x0F,0x02,0x03,0x0A,0x0F,0x02,/*\"媾\",5107*/},{\n\n0x88,0x78,0x0F,0xF8,0x02,0xFA,0xAF,0xAA,0xAF,0xFA,0x02,0x08,0x05,0x02,0x0D,0x02,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"嫫\",5108*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0xBE,0x36,0x2B,0xB6,0x22,0xBE,0x08,0x05,0x02,0x0D,0x00,\n0x0F,0x09,0x00,0x07,0x09,0x0C,/*\"媲\",5109*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x5A,0xAE,0x5A,0x4E,0x29,0x5B,0x08,0x05,0x02,0x0D,0x00,\n0x0A,0x0B,0x05,0x05,0x0B,0x08,/*\"嬡\",5110*/},{\n\n0x88,0x78,0x0F,0xF8,0x56,0xEA,0xAA,0xBB,0xAA,0xEA,0x06,0x08,0x05,0x02,0x0D,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"嬪\",5111*/},{\n\n0x88,0x78,0x0F,0xF8,0x16,0x94,0x94,0xDF,0x94,0x94,0x16,0x08,0x05,0x02,0x0D,0x08,\n0x0B,0x0A,0x0F,0x0A,0x0B,0x0C,/*\"媸\",5112*/},{\n\n0x48,0xEA,0x5A,0x7F,0x5A,0xE8,0x44,0x6B,0x52,0x6E,0x42,0x08,0x07,0x09,0x09,0x0B,\n0x05,0x05,0x05,0x0B,0x09,0x09,/*\"嫠\",5113*/},{\n\n0xF8,0x0F,0xF8,0x10,0x91,0x7D,0x51,0x5F,0x55,0x55,0x11,0x0D,0x02,0x05,0x08,0x05,\n0x09,0x05,0x09,0x05,0x09,0x0F,/*\"嫣\",5114*/},{\n\n0xF8,0x0F,0xF8,0x10,0xDA,0x56,0x5A,0x5F,0x5A,0x56,0xDA,0x0D,0x02,0x05,0x00,0x0F,\n0x08,0x0F,0x0D,0x0F,0x08,0x0F,/*\"嬙\",5115*/},{\n\n0xF8,0x0F,0xF8,0x00,0x1D,0x55,0x5F,0x55,0x5F,0x55,0x1D,0x0D,0x02,0x05,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"嫖\",5116*/},{\n\n0xF8,0x0F,0xF8,0x00,0x0D,0x76,0x54,0xD7,0x54,0x76,0x0D,0x0D,0x02,0x05,0x00,0x07,\n0x01,0x01,0x0F,0x01,0x05,0x07,/*\"嫦\",5117*/},{\n\n0x88,0x78,0x0F,0xF8,0x00,0x5F,0x75,0xD5,0x5F,0x35,0x9F,0x08,0x05,0x02,0x05,0x08,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"嫘\",5118*/},{\n\n0x88,0x78,0x0F,0xF8,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0x08,0x05,0x02,0x05,0x0A,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"嫜\",5119*/},{\n\n0x88,0x78,0x0F,0xF8,0x02,0xEA,0xAA,0xAF,0xAA,0xEA,0x02,0x08,0x05,0x02,0x0D,0x02,\n0x0E,0x0B,0x0A,0x0B,0x0E,0x02,/*\"嬉\",5120*/},{\n\n0xF8,0x0F,0xF8,0x00,0xFA,0x8A,0xBA,0xAB,0xBA,0x8A,0xFA,0x0D,0x02,0x05,0x00,0x08,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x08,/*\"嬗\",5121*/},{\n\n0x20,0x1F,0x75,0x55,0xF7,0x00,0x0A,0x2E,0x7B,0x2E,0x0A,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"嬖\",5122*/},{\n\n0xBF,0xE5,0xBF,0xA5,0xFC,0x07,0xFC,0xA5,0xFF,0xA5,0xBF,0x08,0x07,0x08,0x0F,0x04,\n0x03,0x04,0x08,0x07,0x08,0x0F,/*\"嬲\",5123*/},{\n\n0xF8,0x0F,0xF8,0x00,0xFE,0x2A,0x7E,0xAB,0x1A,0x7E,0x2A,0x0D,0x02,0x05,0x08,0x07,\n0x08,0x0B,0x0E,0x0A,0x09,0x0C,/*\"嬤\",5124*/},{\n\n0x88,0x78,0x0F,0xF8,0x8C,0x95,0xE5,0x9F,0xC5,0x55,0xCC,0x08,0x05,0x02,0x0D,0x04,\n0x02,0x0F,0x02,0x0F,0x05,0x0F,/*\"孀\",5125*/},{\n\n0x41,0x21,0x19,0x07,0x01,0xC1,0x01,0x0D,0x4B,0x48,0x38,0x04,0x02,0x01,0x00,0x08,\n0x0F,0x00,0x00,0x01,0x02,0x04,/*\"尕\",5126*/},{\n\n0x28,0xA4,0x62,0x30,0x20,0xAF,0x20,0x20,0x62,0xA4,0x28,0x01,0x04,0x02,0x00,0x08,\n0x0F,0x00,0x00,0x02,0x04,0x01,/*\"尜\",5127*/},{\n\n0x00,0x02,0x26,0x2A,0x22,0x26,0xA9,0x61,0x29,0x05,0x00,0x01,0x01,0x01,0x09,0x09,\n0x0F,0x01,0x01,0x01,0x01,0x01,/*\"孚\",5128*/},{\n\n0x12,0x16,0x4B,0x4A,0x56,0x40,0xD6,0x4A,0x0A,0x16,0x10,0x02,0x02,0x02,0x0A,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"孥\",5129*/},{\n\n0x02,0x2A,0xB6,0xAB,0xB6,0x82,0xAA,0xB7,0x2A,0x36,0x02,0x02,0x02,0x02,0x0A,0x0A,\n0x0E,0x03,0x02,0x02,0x02,0x02,/*\"孳\",5130*/},{\n\n0x00,0x02,0x02,0x82,0x82,0xE2,0x52,0x4A,0x46,0x20,0x20,0x01,0x01,0x01,0x08,0x08,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"孑\",5131*/},{\n\n0x10,0x22,0x42,0x42,0x82,0xE2,0x12,0x0A,0x06,0x00,0x00,0x00,0x00,0x00,0x08,0x08,\n0x0F,0x01,0x01,0x02,0x02,0x02,/*\"孓\",5132*/},{\n\n0x82,0x82,0xF2,0x4E,0x08,0xF4,0x97,0x94,0xF4,0x04,0xFC,0x00,0x08,0x0F,0x00,0x00,\n0x07,0x08,0x08,0x08,0x09,0x0D,/*\"孢\",5133*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x00,0xFE,0x92,0x92,0xFE,0x00,0x06,0x00,0x0A,0x08,0x07,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"駔\",5134*/},{\n\n0x7F,0x55,0x7F,0x55,0xFF,0x02,0xFE,0x02,0xFE,0x82,0xFE,0x07,0x00,0x0B,0x08,0x0F,\n0x05,0x04,0x04,0x04,0x04,0x0F,/*\"駟\",5135*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x10,0xFC,0x03,0x48,0x88,0xFF,0x08,0x04,0x0A,0x08,0x07,0x00,\n0x0F,0x00,0x00,0x08,0x0F,0x00,/*\"駙\",5136*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x00,0x2C,0xDB,0x8E,0xAA,0xBE,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x0B,0x06,0x03,0x0A,0x0F,/*\"騶\",5137*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x47,0x55,0xD7,0x7D,0xD7,0x55,0x47,0x04,0x0A,0x08,0x07,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"驛\",5138*/},{\n\n0x12,0xF6,0xAB,0xAA,0xB6,0xE0,0xB6,0xAA,0xAA,0x36,0x10,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0A,0x0A,0x06,/*\"駑\",5139*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x10,0xDC,0x53,0x50,0xD8,0x30,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"駘\",5140*/},{\n\n0x7F,0x55,0x7F,0xD5,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x04,0x0B,0x08,0x07,0x08,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"驍\",5141*/},{\n\n0x7F,0x55,0x7F,0xD5,0xAA,0xFA,0xAF,0xFA,0xAF,0xFA,0xAA,0x04,0x0B,0x08,0x07,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"驊\",5142*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x00,0x45,0xFE,0x44,0xFE,0x45,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x08,0x07,0x00,0x0F,0x00,/*\"駢\",5143*/},{\n\n0xFE,0xAA,0xFE,0xAA,0xEF,0xA5,0xED,0xB0,0xED,0xA5,0xAD,0x06,0x00,0x0A,0x08,0x07,\n0x02,0x0F,0x0A,0x03,0x0E,0x0B,/*\"驪\",5144*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0x04,0xFF,0x54,0x54,0xFF,0x04,0x06,0x00,0x0A,0x08,0x07,\n0x09,0x05,0x01,0x01,0x05,0x09,/*\"騏\",5145*/},{\n\n0x7F,0x55,0x7F,0xD5,0x40,0x5F,0x55,0xFF,0x55,0x5F,0x40,0x04,0x0B,0x08,0x07,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"騍\",5146*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x04,0x0A,0x08,0x07,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"騅\",5147*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x82,0xAC,0x76,0xA5,0x74,0xAE,0xB4,0x06,0x00,0x0A,0x08,0x07,\n0x00,0x05,0x0A,0x05,0x02,0x00,/*\"驂\",5148*/},{\n\n0x7F,0xA1,0xA5,0x9B,0xA4,0xD7,0xC4,0xB7,0xA5,0x95,0x04,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0A,0x0A,0x06,/*\"騭\",5149*/},{\n\n0x14,0xED,0xB7,0xBD,0xA7,0xEC,0xB4,0xAB,0xAA,0x36,0x12,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0A,0x0A,0x06,/*\"騖\",5150*/},{\n\n0x48,0xAA,0xBA,0xAF,0xEA,0x8A,0xC4,0xAB,0x92,0xAE,0x42,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0A,0x0A,0x06,/*\"驁\",5151*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x00,0xDE,0x4A,0xD1,0x4E,0x52,0xDE,0x04,0x0A,0x08,0x07,0x00,\n0x0F,0x05,0x07,0x05,0x05,0x0F,/*\"騮\",5152*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x00,0xFE,0xAA,0xEA,0x8B,0x2A,0xEE,0x04,0x0A,0x08,0x07,0x04,\n0x03,0x0A,0x0F,0x02,0x09,0x0F,/*\"騸\",5153*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x1D,0x55,0x5F,0x55,0x5F,0x55,0x1D,0x04,0x0A,0x08,0x07,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"驃\",5154*/},{\n\n0xFE,0xAA,0xFE,0xAA,0x00,0xFE,0xD2,0xAF,0xDA,0x82,0xFE,0x04,0x0A,0x08,0x07,0x04,\n0x02,0x0D,0x0A,0x0C,0x02,0x04,/*\"驄\",5155*/},{\n\n0xFE,0xAA,0xFE,0xAA,0xFF,0x15,0x55,0xF5,0x1D,0x55,0xD7,0x06,0x00,0x0A,0x08,0x07,\n0x0A,0x0F,0x02,0x0A,0x0F,0x02,/*\"驏\",5156*/},{\n\n0x7F,0x55,0x7F,0xD5,0x0A,0x7A,0xD7,0x70,0xD7,0x7A,0x0D,0x04,0x0B,0x08,0x07,0x04,\n0x0D,0x07,0x05,0x07,0x0D,0x04,/*\"驥\",5157*/},{\n\n0x7F,0x55,0x7F,0xD5,0xBA,0xAA,0xFA,0x83,0xFA,0xAA,0xBA,0x04,0x0B,0x08,0x07,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"驤\",5158*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"糹\",5159*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x20,0x22,0x22,0xFE,0x22,0x22,0x0C,0x02,0x04,0x02,0x04,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"紆\",5160*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0x28,0xC8,0x08,0xFF,0x08,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x00,0x00,0x08,0x0F,0x00,/*\"紂\",5161*/},{\n\n0xD8,0xB4,0x93,0xC8,0x10,0x28,0x27,0xA4,0x64,0x24,0x04,0x0C,0x02,0x04,0x02,0x04,\n0x06,0x09,0x08,0x08,0x08,0x0E,/*\"紇\",5162*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x48,0xFF,0x08,0xF8,0x00,0x00,0x0C,0x02,0x04,0x02,0x0C,\n0x06,0x01,0x02,0x03,0x04,0x0F,/*\"紈\",5163*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFE,0x22,0xEA,0xBE,0xEB,0xBE,0xEA,0x0E,0x00,0x06,0x08,0x07,\n0x00,0x0B,0x06,0x03,0x06,0x0B,/*\"纊\",5164*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0x20,0xA2,0x62,0x22,0x20,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x06,0x05,0x04,0x06,0x0C,/*\"紜\",5165*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0xFF,0x10,0x10,0xFF,0x10,0x0C,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x04,0x02,0x07,0x08,0x0E,/*\"紕\",5166*/},{\n\n0xD8,0xB4,0x93,0xC8,0x20,0x22,0x2A,0xF2,0x2A,0x26,0x60,0x0C,0x02,0x04,0x02,0x04,\n0x00,0x08,0x0F,0x00,0x00,0x00,/*\"紓\",5167*/},{\n\n0xD8,0xB4,0x93,0xC8,0x04,0xFF,0x44,0x44,0x44,0xFF,0x04,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"紺\",5168*/},{\n\n0xD8,0xB4,0x93,0xC8,0x10,0xFE,0x10,0xFF,0x10,0xFF,0x10,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x08,0x09,0x09,0x09,0x08,/*\"紲\",5169*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0xC8,0x3F,0xE8,0x29,0xEA,0x08,0x0C,0x02,0x04,0x02,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"紱\",5170*/},{\n\n0xDC,0xB3,0xC8,0x84,0x5A,0x73,0xDE,0x52,0x5A,0x62,0xDE,0x0E,0x00,0x06,0x00,0x0B,\n0x06,0x03,0x02,0x0B,0x08,0x07,/*\"縐\",5171*/},{\n\n0xDC,0xB3,0xC8,0x00,0xF2,0x92,0xFF,0x92,0xFF,0x92,0x9E,0x0E,0x00,0x06,0x00,0x08,\n0x04,0x03,0x00,0x0F,0x04,0x07,/*\"紼\",5172*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0xBC,0x20,0xFF,0x20,0xBC,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x07,0x04,0x07,0x04,0x0F,/*\"絀\",5173*/},{\n\n0xD8,0xB4,0x93,0xC8,0x10,0xD8,0x54,0x53,0x50,0xD8,0x30,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"紿\",5174*/},{\n\n0xD8,0xB4,0x93,0xC8,0x52,0xCA,0x56,0x53,0x56,0x4A,0x52,0x0C,0x02,0x04,0x02,0x04,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"絝\",5175*/},{\n\n0xD8,0xB4,0x93,0xC8,0x24,0xF2,0x09,0x12,0x12,0xF2,0x12,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x00,0x08,0x08,0x0F,0x00,/*\"絎\",5176*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x54,0x57,0xEA,0x4A,0x56,0x10,0x0C,0x02,0x04,0x02,0x04,\n0x03,0x02,0x0F,0x02,0x02,0x02,/*\"絳\",5177*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0xFA,0xAA,0xFE,0xAA,0xFA,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x0A,0x04,0x0B,0x08,0x08,/*\"綆\",5178*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x00,0xF2,0x54,0x5F,0x54,0xF2,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x0F,0x01,0x01,0x09,0x0F,/*\"綃\",5179*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x75,0x56,0xFC,0x56,0x5D,0xC0,0x0C,0x02,0x04,0x02,0x04,\n0x02,0x01,0x0F,0x00,0x02,0x03,/*\"綈\",5180*/},{\n\n0xDC,0xB3,0xC8,0x00,0x28,0x9A,0x6A,0x4F,0x4A,0xDA,0x28,0x0E,0x00,0x06,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"綾\",5181*/},{\n\n0xD8,0xB4,0x93,0xC8,0x10,0xDA,0x56,0xD3,0x16,0xFA,0x10,0x0C,0x02,0x04,0x02,0x04,\n0x07,0x02,0x03,0x08,0x0F,0x00,/*\"綺\",5182*/},{\n\n0xD8,0xB4,0x93,0xC8,0x24,0x24,0xFF,0x00,0xFF,0x24,0x24,0x0C,0x02,0x04,0x02,0x05,\n0x01,0x0F,0x00,0x0F,0x01,0x01,/*\"緋\",5183*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xF2,0x14,0xD0,0x5F,0xD0,0x14,0xF2,0x02,0x02,0x0F,0x02,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"鞝\",5184*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0xDF,0x95,0x15,0xD5,0x15,0x9F,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x04,0x00,0x07,0x09,0x0C,/*\"緄\",5185*/},{\n\n0xDC,0xB3,0xC8,0x00,0x48,0xFA,0x4A,0xFE,0x49,0xF9,0x48,0x0E,0x00,0x06,0x00,0x02,\n0x0B,0x0A,0x0F,0x0A,0x0B,0x02,/*\"綞\",5186*/},{\n\n0xD8,0xB4,0x93,0xC8,0x32,0xD6,0x5A,0x56,0x5A,0xD9,0x35,0x0C,0x02,0x04,0x02,0x0C,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"綬\",5187*/},{\n\n0xDC,0xB3,0xC8,0x44,0xAB,0x92,0xAE,0xA0,0xBF,0xA4,0x28,0x0E,0x00,0x06,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"綹\",5188*/},{\n\n0xD8,0xB4,0x93,0xC8,0x50,0xB5,0x9C,0x97,0x94,0xB5,0x50,0x0C,0x02,0x04,0x02,0x04,\n0x07,0x08,0x08,0x0A,0x0B,0x0C,/*\"綣\",5189*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x0C,0xF4,0x55,0x56,0x74,0x0C,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x0F,0x05,0x05,0x05,0x0F,/*\"綰\",5190*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x04,0xDB,0x44,0xDB,0x44,0xDB,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x0F,0x05,0x07,0x05,0x0F,/*\"緇\",5191*/},{\n\n0xDC,0xB3,0xC8,0x00,0xE2,0xAF,0xAA,0xFA,0xAA,0xAF,0xE2,0x0E,0x00,0x06,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"緙\",5192*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x48,0xFF,0x48,0xFE,0x92,0xFE,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x0F,0x00,0x0F,0x04,0x0F,/*\"緗\",5193*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x5F,0x55,0xD5,0x55,0x5F,0x40,0x0C,0x02,0x04,0x02,0x0C,\n0x07,0x08,0x0F,0x09,0x09,0x08,/*\"緹\",5194*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFE,0x92,0xFE,0x08,0x7F,0x04,0xD8,0x0E,0x00,0x06,0x00,0x07,\n0x02,0x0B,0x04,0x02,0x01,0x00,/*\"緲\",5195*/},{\n\n0xD8,0xB4,0x93,0xC8,0x20,0xEE,0xAA,0xBF,0xAA,0xEE,0x20,0x0C,0x02,0x04,0x02,0x04,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"繢\",5196*/},{\n\n0xDC,0xB3,0xC8,0x00,0x7F,0x49,0xC9,0x7F,0x49,0x49,0x7F,0x0E,0x00,0x06,0x04,0x03,\n0x00,0x06,0x09,0x0C,0x01,0x06,/*\"緦\",5197*/},{\n\n0xDC,0xB3,0xC8,0x10,0xFC,0x03,0xFA,0xAA,0xFE,0xAA,0xFA,0x0E,0x00,0x06,0x00,0x0F,\n0x00,0x0A,0x04,0x0B,0x08,0x08,/*\"緶\",5198*/},{\n\n0xDC,0xB3,0xC8,0x10,0xFC,0x03,0x48,0x3A,0xEA,0x2E,0x08,0x0E,0x00,0x06,0x00,0x0F,\n0x00,0x09,0x05,0x03,0x05,0x09,/*\"緱\",5199*/},{\n\n0xD8,0xB4,0x93,0xC8,0x11,0xF2,0x00,0xFC,0x56,0x55,0xDC,0x0C,0x02,0x04,0x0A,0x04,\n0x03,0x04,0x0B,0x0A,0x0A,0x0B,/*\"縋\",5200*/},{\n\n0xD8,0xB4,0x93,0xC8,0x7F,0xD5,0x95,0x9D,0xB5,0xD7,0x60,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"緡\",5201*/},{\n\n0xD8,0xB4,0x93,0xC8,0x24,0xA9,0xBF,0xA1,0xBF,0xA9,0x24,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"縉\",5202*/},{\n\n0xD8,0xB4,0x93,0xC8,0x02,0xFA,0xAA,0xAF,0xAA,0xFA,0x02,0x0C,0x02,0x04,0x02,0x06,\n0x0B,0x06,0x02,0x06,0x0B,0x02,/*\"縝\",5203*/},{\n\n0xDC,0xB3,0xC8,0x00,0xFF,0x11,0xF5,0x95,0x35,0x55,0xB5,0x0E,0x00,0x06,0x08,0x07,\n0x02,0x06,0x02,0x0A,0x0F,0x02,/*\"縟\",5204*/},{\n\n0xDC,0xB3,0xC8,0x00,0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x0E,0x00,0x06,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"縞\",5205*/},{\n\n0xDC,0xB3,0xC8,0x00,0xBA,0xA2,0xB6,0xEB,0xB6,0xA2,0xBA,0x0E,0x00,0x06,0x00,0x0F,\n0x00,0x06,0x05,0x06,0x08,0x0F,/*\"縭\",5206*/},{\n\n0xDC,0xB3,0xC8,0x00,0xA9,0x9A,0x88,0x88,0x88,0x9A,0xA9,0x0E,0x00,0x06,0x08,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"縊\",5207*/},{\n\n0xD8,0xB4,0x93,0xC8,0x40,0x55,0xFE,0x54,0xFC,0x56,0xF5,0x0C,0x02,0x04,0x02,0x04,\n0x03,0x0F,0x01,0x0F,0x03,0x05,/*\"縑\",5208*/},{\n\n0xD8,0xB4,0x93,0xC8,0x56,0xEA,0xAA,0xBB,0xAA,0xEA,0x06,0x0C,0x02,0x04,0x02,0x04,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"繽\",5209*/},{\n\n0xDC,0xB3,0xC8,0x00,0x1D,0x55,0x5F,0x55,0x5F,0x55,0x1D,0x0E,0x00,0x06,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"縹\",5210*/},{\n\n0xDC,0xB3,0xC8,0x00,0x70,0x5F,0x75,0x55,0x75,0x5F,0x70,0x0E,0x00,0x06,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"縵\",5211*/},{\n\n0xD8,0xB4,0x93,0xC8,0x00,0x5F,0x75,0xD5,0x5F,0x35,0x9F,0x0C,0x02,0x04,0x02,0x0C,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"縲\",5212*/},{\n\n0xDC,0xB3,0xC8,0x40,0x4B,0xA5,0xAF,0x50,0x2B,0x45,0x4F,0x0E,0x00,0x06,0x00,0x0A,\n0x0A,0x0A,0x0A,0x05,0x04,0x02,/*\"繆\",5213*/},{\n\n0x98,0xD4,0xB3,0x90,0xC8,0x02,0xFD,0xAA,0xFD,0xAA,0xFD,0x0E,0x00,0x06,0x00,0x06,\n0x00,0x0A,0x06,0x0F,0x06,0x0A,/*\"繅\",5214*/},{\n\n0xDC,0xB3,0xC8,0x00,0xA4,0xBF,0xA4,0x00,0xFA,0xAE,0xFA,0x0E,0x00,0x06,0x00,0x0F,\n0x04,0x0F,0x00,0x0B,0x06,0x0B,/*\"纈\",5215*/},{\n\n0xDC,0xB3,0xC8,0x00,0x2A,0xF2,0xAA,0xA7,0xAA,0xF2,0x2A,0x0E,0x00,0x06,0x00,0x08,\n0x07,0x0A,0x0E,0x02,0x07,0x08,/*\"繚\",5216*/},{\n\n0xD8,0xB4,0x93,0xC8,0x3E,0xAB,0xA2,0xBE,0xA2,0xAB,0x3E,0x0C,0x02,0x04,0x02,0x04,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"繒\",5217*/},{\n\n0xDC,0xB3,0xC8,0x00,0x82,0xBE,0xAA,0xBE,0xAA,0xBE,0x82,0x0E,0x00,0x06,0x00,0x08,\n0x0F,0x0A,0x0F,0x0A,0x0F,0x08,/*\"繮\",5218*/},{\n\n0xDC,0xB3,0xC8,0x22,0xE4,0x2E,0xEA,0xBF,0xAA,0xEE,0x20,0x0E,0x00,0x06,0x08,0x07,\n0x08,0x0F,0x0A,0x0A,0x0E,0x08,/*\"繾\",5219*/},{\n\n0xDC,0xB3,0xC8,0x00,0x70,0x57,0x75,0x85,0x75,0x57,0x70,0x0E,0x00,0x06,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"繰\",5220*/},{\n\n0xD8,0xB4,0x93,0xC8,0x17,0xD5,0x57,0x55,0x57,0xD5,0x17,0x0C,0x02,0x04,0x02,0x0C,\n0x05,0x0F,0x09,0x03,0x05,0x0A,/*\"繯\",5221*/},{\n\n0xDC,0xB3,0xC8,0x44,0xEB,0x5A,0xFF,0x6A,0x5A,0x7F,0xEA,0x0E,0x00,0x06,0x00,0x0B,\n0x06,0x02,0x03,0x02,0x06,0x0B,/*\"纘\",5222*/},{\n\n0x00,0x20,0x30,0x28,0xA4,0x63,0x20,0x10,0x0C,0x00,0x00,0x00,0x04,0x06,0x05,0x04,\n0x04,0x04,0x04,0x05,0x06,0x0C,/*\"幺\",5223*/},{\n\n0x40,0xDA,0x55,0xDA,0x40,0xDF,0x60,0xDA,0x75,0x5A,0x40,0x00,0x0F,0x05,0x07,0x05,\n0x0F,0x08,0x05,0x02,0x05,0x0E,/*\"畿\",5224*/},{\n\n0x00,0x60,0x98,0x06,0x60,0x98,0x06,0x60,0x98,0x06,0x00,0x00,0x00,0x01,0x06,0x00,\n0x01,0x06,0x00,0x01,0x06,0x00,/*\"巛\",5225*/},{\n\n0x04,0xEA,0x31,0x20,0x24,0xEA,0x31,0x20,0x24,0xEA,0x11,0x00,0x0F,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x0F,0x00,/*\"甾\",5226*/},{\n\n0x00,0x82,0xBD,0xA8,0xAA,0xAD,0xA8,0xAA,0xBD,0x80,0x00,0x00,0x07,0x0A,0x0A,0x0A,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"邕\",5227*/},{\n\n0x22,0x22,0xFE,0x22,0x22,0x00,0x02,0x02,0xFE,0x02,0x02,0x04,0x04,0x07,0x02,0x02,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"玎\",5228*/},{\n\n0x22,0xFE,0x22,0xB4,0xEB,0xB4,0x80,0xFF,0xB4,0xEB,0xB4,0x04,0x07,0x02,0x08,0x07,\n0x02,0x08,0x05,0x02,0x05,0x0E,/*\"璣\",5229*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0x8A,0xBA,0xAF,0xEA,0xBE,0x88,0x04,0x04,0x03,0x02,0x00,\n0x06,0x04,0x04,0x0F,0x04,0x04,/*\"瑋\",5230*/},{\n\n0x22,0x22,0xFE,0x22,0x10,0x2C,0xE3,0x20,0x23,0xEC,0x10,0x04,0x04,0x03,0x02,0x08,\n0x06,0x01,0x08,0x08,0x07,0x00,/*\"玢\",5231*/},{\n\n0x22,0x22,0xFE,0x22,0x04,0x3C,0xC5,0x06,0xC4,0x3C,0x04,0x04,0x04,0x03,0x02,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"玟\",5232*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0x42,0x42,0xFE,0x42,0x42,0x00,0x04,0x04,0x03,0x02,0x08,\n0x08,0x08,0x0F,0x08,0x09,0x0A,/*\"珏\",5233*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0xF2,0x12,0xF2,0x02,0xFE,0x02,0x04,0x04,0x03,0x02,0x00,\n0x03,0x01,0x09,0x08,0x0F,0x00,/*\"珂\",5234*/},{\n\n0x22,0xFE,0x22,0x0A,0xEE,0xAB,0xEE,0x0A,0xF7,0x55,0x5D,0x04,0x07,0x02,0x00,0x0F,\n0x02,0x0F,0x00,0x07,0x09,0x0D,/*\"瓏\",5235*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0xC0,0x40,0x7F,0x48,0x48,0xC8,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"玷\",5236*/},{\n\n0x22,0x22,0xFE,0x22,0x10,0xFC,0x23,0x20,0xFF,0x12,0x14,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x00,0x00,0x03,0x04,0x0E,/*\"玳\",5237*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0xFC,0x44,0x46,0x45,0x44,0xFC,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"珀\",5238*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0xFF,0x49,0x49,0xF9,0x49,0x4F,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x00,0x03,0x04,0x0E,/*\"珉\",5239*/},{\n\n0x22,0xFE,0x22,0x08,0xFF,0x08,0xF8,0x00,0xFC,0x04,0xFC,0x04,0x07,0x0A,0x04,0x03,\n0x08,0x0F,0x00,0x0F,0x04,0x0F,/*\"珈\",5240*/},{\n\n0x22,0xFE,0x22,0x00,0x02,0xFE,0x52,0x52,0x52,0xFE,0x02,0x04,0x07,0x02,0x00,0x02,\n0x03,0x02,0x02,0x02,0x0F,0x01,/*\"珥\",5241*/},{\n\n0x22,0xFE,0x22,0x80,0x88,0xFF,0x88,0x88,0xFF,0x88,0x80,0x04,0x07,0x02,0x08,0x04,\n0x02,0x00,0x00,0x02,0x04,0x08,/*\"珙\",5242*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0xFA,0xAA,0xAE,0xAA,0xAA,0xFA,0x04,0x04,0x03,0x02,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"頊\",5243*/},{\n\n0x22,0xFE,0x22,0x00,0x3D,0xA1,0xFF,0x21,0xFE,0x32,0xCE,0x04,0x07,0x02,0x02,0x01,\n0x08,0x0F,0x00,0x0F,0x02,0x01,/*\"琊\",5244*/},{\n\n0x22,0xFE,0x22,0x00,0x24,0xF2,0x09,0x10,0x12,0xF2,0x12,0x04,0x07,0x02,0x00,0x00,\n0x0F,0x00,0x08,0x08,0x0F,0x00,/*\"珩\",5245*/},{\n\n0x22,0xFE,0x22,0x88,0x50,0xFF,0x00,0x00,0xFF,0x50,0x88,0x04,0x07,0x02,0x08,0x06,\n0x01,0x00,0x00,0x07,0x08,0x0E,/*\"珧\",5246*/},{\n\n0x22,0x22,0xFE,0x22,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"珞\",5247*/},{\n\n0x85,0xBF,0xAD,0x95,0xAD,0x9F,0xAD,0x95,0xAD,0xBF,0x85,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0E,0x0A,0x08,/*\"璽\",5248*/},{\n\n0x22,0xFE,0x22,0x00,0xF3,0x55,0x55,0xFF,0x55,0x55,0xF3,0x04,0x07,0x02,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"琿\",5249*/},{\n\n0x22,0xFE,0x22,0x11,0xF2,0x00,0xFA,0xAA,0xFF,0xAA,0xFA,0x04,0x07,0x02,0x08,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"璉\",5250*/},{\n\n0x22,0x22,0xFE,0x22,0x04,0xFF,0x54,0x54,0x54,0xFF,0x04,0x04,0x04,0x03,0x02,0x09,\n0x05,0x01,0x01,0x01,0x05,0x09,/*\"琪\",5251*/},{\n\n0x22,0xFE,0x22,0x00,0x02,0xF7,0x12,0xFA,0x12,0xF7,0x02,0x04,0x07,0x02,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"瑛\",5252*/},{\n\n0x22,0x22,0xFE,0x22,0x10,0xDA,0x56,0xD3,0x16,0xFA,0x10,0x04,0x04,0x03,0x02,0x00,\n0x07,0x02,0x03,0x08,0x0F,0x00,/*\"琦\",5253*/},{\n\n0x22,0xFE,0x22,0x00,0xF8,0x48,0x48,0x7F,0xAA,0xAA,0xD8,0x04,0x07,0x02,0x08,0x07,\n0x08,0x07,0x01,0x07,0x08,0x0C,/*\"琥\",5254*/},{\n\n0x22,0xFE,0x22,0x00,0xDF,0x15,0x15,0x15,0xD5,0x1F,0x80,0x04,0x07,0x02,0x00,0x0F,\n0x09,0x05,0x00,0x07,0x09,0x0C,/*\"琨\",5255*/},{\n\n0x22,0xFE,0x22,0x00,0x28,0xA6,0x10,0xCF,0x10,0x14,0xA2,0x04,0x07,0x02,0x08,0x09,\n0x04,0x02,0x01,0x02,0x05,0x08,/*\"琰\",5256*/},{\n\n0x22,0xFE,0x22,0x00,0x86,0x92,0x92,0x93,0x92,0x92,0x86,0x04,0x07,0x02,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"琮\",5257*/},{\n\n0x22,0xFE,0x22,0x80,0x66,0x9A,0xF2,0x03,0xF2,0x92,0xF6,0x04,0x07,0x02,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"琬\",5258*/},{\n\n0x22,0xFE,0x22,0x00,0x46,0x52,0x4A,0xE2,0x4A,0x52,0x46,0x04,0x07,0x02,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"琛\",5259*/},{\n\n0x22,0x22,0xFE,0x22,0x00,0xFE,0xAA,0xAA,0xFA,0xAA,0xAE,0x04,0x04,0x03,0x0A,0x06,\n0x01,0x0F,0x04,0x04,0x04,0x0F,/*\"琚\",5260*/},{\n\n0x22,0x22,0xFE,0x22,0x07,0xF1,0x55,0x55,0x55,0xF1,0x07,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"瑁\",5261*/},{\n\n0x22,0xFE,0x22,0xE8,0xA4,0xAA,0xE9,0x0A,0xC4,0x08,0xE8,0x04,0x07,0x02,0x0F,0x02,\n0x0A,0x0F,0x00,0x03,0x08,0x0F,/*\"瑜\",5262*/},{\n\n0x22,0xFE,0x22,0x00,0x56,0x5A,0xD6,0x7A,0x52,0x59,0x55,0x04,0x07,0x02,0x04,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"瑗\",5263*/},{\n\n0x22,0xFE,0x22,0xFF,0x49,0x4F,0x00,0xC9,0x49,0xCF,0x00,0x04,0x07,0x02,0x0F,0x02,\n0x02,0x08,0x05,0x02,0x05,0x08,/*\"瑕\",5264*/},{\n\n0x22,0xFE,0x22,0x00,0xC4,0x6A,0xD5,0x4A,0xD5,0x4A,0xD1,0x04,0x07,0x02,0x00,0x0F,\n0x04,0x06,0x05,0x06,0x04,0x0F,/*\"瑙\",5265*/},{\n\n0x22,0xFE,0x22,0x00,0x5A,0x8E,0x2A,0x5E,0x69,0x0D,0x59,0x04,0x07,0x02,0x00,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"璦\",5266*/},{\n\n0x22,0xFE,0x22,0x00,0xFE,0x22,0xAA,0xFF,0xAA,0xFA,0x22,0x04,0x07,0x02,0x08,0x07,\n0x00,0x0E,0x0B,0x0A,0x0E,0x00,/*\"瑭\",5267*/},{\n\n0x22,0xFE,0x22,0x00,0xE2,0xAF,0xAA,0xFA,0xAA,0xAF,0xE2,0x04,0x07,0x02,0x00,0x0A,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"瑾\",5268*/},{\n\n0x22,0xFE,0x22,0x08,0xEA,0xAF,0xAA,0xFA,0xAA,0xAF,0xEA,0x04,0x07,0x02,0x00,0x0B,\n0x06,0x02,0x03,0x02,0x06,0x0B,/*\"璜\",5269*/},{\n\n0x22,0xFE,0x22,0x00,0x5F,0x35,0xDF,0x00,0x5F,0x35,0x5F,0x04,0x07,0x02,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"瓔\",5270*/},{\n\n0x22,0xFE,0x22,0x40,0x26,0xF4,0xAC,0xA7,0xEC,0xB4,0xA6,0x04,0x07,0x02,0x00,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"璀\",5271*/},{\n\n0x22,0xFE,0x22,0x00,0xFE,0x92,0xDE,0xAB,0xDA,0x82,0xFE,0x04,0x07,0x02,0x08,0x06,\n0x00,0x06,0x09,0x0C,0x02,0x0C,/*\"璁\",5272*/},{\n\n0x22,0xFE,0x22,0x04,0xFD,0x26,0xE4,0x13,0xF2,0x92,0xB2,0x04,0x07,0x02,0x08,0x07,\n0x08,0x0F,0x04,0x0F,0x08,0x08,/*\"璇\",5273*/},{\n\n0x22,0x22,0xFE,0x22,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0x02,0x02,0x01,0x01,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"璋\",5274*/},{\n\n0x22,0xFE,0x22,0x00,0x25,0xAC,0xB7,0xE4,0xB7,0xAC,0x25,0x04,0x07,0x02,0x00,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"璞\",5275*/},{\n\n0x22,0xFE,0x22,0x10,0x58,0xAF,0x1A,0xC0,0x2A,0x92,0x2E,0x04,0x07,0x02,0x01,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"璨\",5276*/},{\n\n0x22,0xFE,0x22,0x00,0xFC,0x54,0x54,0xFF,0x55,0x55,0x6D,0x04,0x07,0x02,0x04,0x03,\n0x05,0x05,0x0A,0x0F,0x02,0x05,/*\"璩\",5277*/},{\n\n0x22,0xFE,0x22,0x9E,0x12,0xF2,0x9E,0x44,0xAB,0x92,0xAE,0x04,0x07,0x0A,0x0F,0x08,\n0x07,0x04,0x00,0x0F,0x04,0x0F,/*\"璐\",5278*/},{\n\n0xA0,0x9F,0xF5,0xD5,0xF7,0x80,0x8A,0xAE,0xFB,0xAE,0x8A,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0E,0x0A,0x08,/*\"璧\",5279*/},{\n\n0x22,0xFE,0x22,0x44,0xEB,0x5A,0xFF,0x6A,0x5A,0x7F,0xEA,0x04,0x07,0x02,0x00,0x0B,\n0x06,0x02,0x03,0x02,0x06,0x0B,/*\"瓚\",5280*/},{\n\n0x60,0xBE,0xA5,0xA0,0xBF,0xA5,0xBF,0xA0,0xA5,0xBF,0x60,0x08,0x08,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0E,0x0A,0x08,0x08,/*\"璺\",5281*/},{\n\n0x40,0x5F,0x55,0xD5,0x5F,0x48,0x3A,0xAE,0xEB,0xBE,0x88,0x08,0x07,0x08,0x0F,0x09,\n0x08,0x0B,0x0A,0x0F,0x0A,0x0A,/*\"韙\",5282*/},{\n\n0x8A,0xBE,0xEB,0xBE,0x08,0xDF,0x55,0xD5,0x55,0xDF,0x00,0x06,0x04,0x0F,0x04,0x08,\n0x0F,0x08,0x0F,0x08,0x0F,0x08,/*\"韞\",5283*/},{\n\n0x8A,0xBE,0xEB,0xBE,0x08,0xCA,0x52,0x26,0x09,0x51,0xCD,0x06,0x04,0x0F,0x04,0x00,\n0x0F,0x05,0x04,0x04,0x05,0x0F,/*\"韜\",5284*/},{\n\n0x88,0x68,0xFF,0x28,0x42,0x02,0xFE,0x02,0xFE,0x02,0x02,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"杌\",5285*/},{\n\n0x88,0x68,0xFF,0x28,0x50,0x08,0x27,0xC4,0x04,0x04,0xFC,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"杓\",5286*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0xE2,0x22,0x22,0x22,0x3E,0x00,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"杞\",5287*/},{\n\n0x88,0x68,0xFF,0x28,0x42,0x3E,0xC2,0x0A,0xD2,0x3E,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"杈\",5288*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0x7F,0x55,0x55,0x7F,0x55,0xD5,0x00,0x00,0x0F,0x00,0x02,\n0x01,0x02,0x01,0x0A,0x09,0x07,/*\"榪\",5289*/},{\n\n0x88,0x68,0xFF,0x48,0xFF,0x55,0xFD,0x53,0x35,0xFD,0x53,0x00,0x00,0x0F,0x08,0x07,\n0x08,0x0E,0x08,0x0F,0x0A,0x0A,/*\"櫪\",5290*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0xFF,0x10,0x10,0xFF,0x10,0x0C,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x02,0x07,0x08,0x0E,/*\"枇\",5291*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0x38,0x00,0xFF,0x00,0x04,0xB8,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,/*\"杪\",5292*/},{\n\n0x24,0xE4,0x54,0x4C,0x44,0x7F,0x44,0x4C,0x54,0xE4,0x24,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"杳\",5293*/},{\n\n0x88,0x68,0xFF,0x48,0xFC,0x84,0x44,0x3F,0x44,0x84,0xFC,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x00,0x00,0x00,0x08,0x0F,/*\"枘\",5294*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xFE,0xAA,0xAA,0xAA,0xFE,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"梘\",5295*/},{\n\n0x84,0x64,0xFF,0x24,0x88,0x87,0x84,0xFC,0x84,0x84,0x80,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"杵\",5296*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xC0,0x7F,0xD5,0x55,0x55,0x41,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"棖\",5297*/},{\n\n0xC8,0xFF,0x48,0x24,0xF2,0x09,0x90,0x0F,0xD0,0x0F,0x10,0x00,0x0F,0x00,0x00,0x0F,\n0x08,0x07,0x08,0x0F,0x09,0x09,/*\"樅\",5298*/},{\n\n0x00,0xFE,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xBE,0xA0,0xA0,0x02,0x0A,0x06,0x02,0x0F,\n0x02,0x06,0x0A,0x02,0x04,0x07,/*\"梟\",5299*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0x04,0xFD,0x26,0x24,0x24,0xE4,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x08,0x08,0x07,/*\"枋\",5300*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0xFE,0x42,0x7E,0x42,0x7E,0x00,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"杷\",5301*/},{\n\n0x88,0x68,0xFF,0x48,0x20,0x22,0x2A,0xF2,0x2A,0x26,0x60,0x00,0x00,0x0F,0x00,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"杼\",5302*/},{\n\n0x12,0x12,0x4A,0x46,0x42,0x5F,0x42,0x46,0x4A,0x12,0x12,0x01,0x09,0x05,0x01,0x09,\n0x0F,0x01,0x01,0x05,0x09,0x01,/*\"柰\",5303*/},{\n\n0xC8,0xFF,0x48,0x04,0xF3,0x56,0xF2,0x04,0xF3,0x16,0xF2,0x00,0x0F,0x00,0x00,0x0F,\n0x05,0x03,0x04,0x0F,0x02,0x03,/*\"櫛\",5304*/},{\n\n0x88,0x68,0xFF,0x48,0x80,0x42,0xF2,0x2E,0x22,0x22,0xE2,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"柘\",5305*/},{\n\n0x88,0x68,0xFF,0x4A,0xEE,0xAB,0xEE,0x0A,0xF7,0x55,0x5D,0x00,0x00,0x0F,0x00,0x0F,\n0x02,0x0F,0x00,0x07,0x09,0x0D,/*\"櫳\",5306*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xFE,0x42,0x32,0x9E,0x52,0x32,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x09,0x08,0x09,0x0A,/*\"柩\",5307*/},{\n\n0x84,0x64,0xFF,0x24,0x88,0xB2,0x82,0xFE,0x82,0xA2,0x98,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"枰\",5308*/},{\n\n0x84,0x64,0xFF,0x24,0xF8,0x28,0xA8,0xFF,0xAA,0xAA,0xDA,0x00,0x00,0x0F,0x04,0x0B,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"櫨\",5309*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x92,0x92,0xFE,0x92,0x92,0xFE,0x00,0x00,0x0F,0x00,0x01,\n0x00,0x00,0x0F,0x00,0x00,0x01,/*\"柙\",5310*/},{\n\n0x88,0x68,0xFF,0x48,0x20,0xAF,0x69,0x29,0x29,0x2F,0x20,0x00,0x00,0x0F,0x00,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"枵\",5311*/},{\n\n0x88,0x68,0xFF,0x28,0xFC,0x44,0x44,0xFF,0x44,0x44,0xFC,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"柚\",5312*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xFE,0x82,0x82,0x82,0xFE,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x02,0x00,0x02,0x04,0x08,/*\"枳\",5313*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xFE,0x12,0x92,0xF1,0x11,0x10,0x00,0x00,0x0F,0x00,0x08,\n0x07,0x00,0x00,0x0F,0x01,0x02,/*\"柝\",5314*/},{\n\n0x84,0x64,0xFF,0x24,0xFE,0x0A,0xEA,0x2A,0xEA,0x29,0xE9,0x00,0x00,0x0F,0x08,0x07,\n0x00,0x07,0x09,0x09,0x09,0x0D,/*\"梔\",5315*/},{\n\n0x88,0x68,0xFF,0x48,0x10,0x48,0x44,0x53,0x64,0xC8,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x02,0x04,0x0B,0x00,0x00,/*\"柃\",5316*/},{\n\n0x88,0x68,0xFF,0x48,0x10,0xE8,0x27,0x24,0xE4,0x04,0xFC,0x00,0x00,0x0F,0x00,0x00,\n0x03,0x01,0x01,0x09,0x08,0x07,/*\"枸\",5317*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0xFE,0x22,0x22,0xFE,0x21,0x21,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x08,0x03,0x04,0x0E,/*\"柢\",5318*/},{\n\n0x88,0x68,0xFF,0x48,0xB6,0xAD,0xBE,0xEB,0xBE,0x94,0xAB,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"櫟\",5319*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0x0C,0xE4,0x05,0x86,0x44,0x2C,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"柁\",5320*/},{\n\n0x88,0x68,0xFF,0x49,0xBF,0xA5,0xFF,0x91,0xBE,0xA2,0xBE,0x00,0x00,0x0F,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"檉\",5321*/},{\n\n0x88,0x68,0xFF,0x48,0x94,0xD4,0x7F,0x54,0x58,0x54,0x12,0x00,0x00,0x0F,0x01,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"栲\",5322*/},{\n\n0x88,0x68,0xFF,0x48,0x20,0xA4,0xE4,0x3F,0x34,0xA8,0xA6,0x00,0x00,0x0F,0x00,0x01,\n0x00,0x07,0x09,0x09,0x08,0x0C,/*\"栳\",5323*/},{\n\n0x88,0x68,0xFF,0x48,0xF2,0x12,0x1E,0x02,0x1E,0x12,0xF2,0x00,0x00,0x0F,0x00,0x09,\n0x09,0x0F,0x08,0x0F,0x09,0x09,/*\"椏\",5324*/},{\n\n0x88,0x68,0xFF,0x48,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"橈\",5325*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0x32,0x2A,0xE6,0x22,0x32,0x62,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"桎\",5326*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xF8,0xA8,0xAF,0xAA,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"楨\",5327*/},{\n\n0x88,0x68,0xFF,0x48,0x24,0x28,0xE0,0x3F,0xE0,0x28,0x24,0x00,0x00,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"桄\",5328*/},{\n\n0x88,0x68,0xFF,0x28,0xD6,0x54,0x54,0x57,0x54,0x54,0xD6,0x00,0x00,0x0F,0x00,0x09,\n0x0B,0x0D,0x09,0x0D,0x0B,0x09,/*\"榿\",5329*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0x72,0xCE,0x00,0x22,0xFE,0x21,0x00,0x00,0x0F,0x00,0x0A,\n0x04,0x0B,0x08,0x0A,0x0B,0x0A,/*\"梃\",5330*/},{\n\n0x88,0x68,0xFF,0x48,0x10,0x92,0x92,0xFE,0x91,0x91,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"栝\",5331*/},{\n\n0x88,0x68,0xFF,0x28,0xFC,0x44,0x42,0x01,0x44,0x44,0xFC,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x04,0x0F,/*\"桕\",5332*/},{\n\n0x88,0x68,0xFF,0x48,0xAA,0xFA,0xAF,0xFA,0xAF,0xFA,0xAA,0x00,0x00,0x0F,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"樺\",5333*/},{\n\n0x88,0x68,0xFF,0x48,0x24,0xF2,0x09,0x10,0x12,0xF2,0x12,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x00,0x08,0x08,0x0F,0x00,/*\"桁\",5334*/},{\n\n0x88,0x68,0xFF,0x48,0xF4,0xB2,0xD5,0xF5,0xD5,0xB2,0xF4,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"檜\",5335*/},{\n\n0x88,0xC4,0xAB,0x92,0x8E,0xC0,0x9A,0x92,0xFF,0x92,0x90,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"桀\",5336*/},{\n\n0x56,0x1D,0x54,0x00,0x3A,0xAB,0x3A,0x00,0x56,0x1D,0x54,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"欒\",5337*/},{\n\n0x90,0x54,0xB5,0x96,0x9C,0xD7,0x94,0x96,0xB5,0x54,0x90,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x00,/*\"桊\",5338*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0x4C,0xC4,0x75,0x46,0xC4,0x4C,0x00,0x00,0x0F,0x00,0x08,\n0x08,0x05,0x02,0x02,0x05,0x08,/*\"桉\",5339*/},{\n\n0x88,0x68,0xFF,0x48,0x12,0xA2,0xFE,0x00,0x12,0xA2,0xFE,0x00,0x00,0x0F,0x00,0x01,\n0x08,0x0F,0x00,0x01,0x08,0x0F,/*\"栩\",5340*/},{\n\n0x12,0x0A,0x3F,0xCA,0x52,0x40,0x52,0xCA,0x3F,0x0A,0x12,0x08,0x08,0x04,0x03,0x01,\n0x02,0x00,0x07,0x08,0x08,0x0E,/*\"梵\",5341*/},{\n\n0x88,0x68,0xFF,0x48,0x28,0xA6,0xA4,0xBF,0xA4,0xA4,0x20,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"梏\",5342*/},{\n\n0x88,0x68,0xFF,0x48,0x2A,0x32,0x26,0xAA,0x61,0x29,0x05,0x00,0x00,0x0F,0x00,0x01,\n0x01,0x09,0x0F,0x01,0x01,0x01,/*\"桴\",5343*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xF4,0x53,0xF2,0x5A,0x56,0xF0,0x00,0x00,0x0F,0x00,0x08,\n0x07,0x01,0x07,0x01,0x09,0x0F,/*\"桷\",5344*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0x54,0x65,0xC6,0x64,0x54,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x01,0x01,0x0F,0x01,0x01,0x00,/*\"梓\",5345*/},{\n\n0x88,0x68,0xFF,0x48,0x11,0x22,0x18,0x00,0xFF,0x08,0xB0,0x00,0x00,0x0F,0x00,0x02,\n0x09,0x08,0x04,0x02,0x01,0x00,/*\"桫\",5346*/},{\n\n0x88,0x68,0xFF,0x28,0xCD,0x55,0xC5,0x7F,0xC5,0x55,0xCD,0x00,0x00,0x0F,0x00,0x0D,\n0x0B,0x0D,0x0F,0x0D,0x0B,0x0D,/*\"欞\",5347*/},{\n\n0x88,0x68,0xFF,0x48,0x90,0xD4,0x7F,0x54,0x58,0xD4,0x12,0x00,0x00,0x0F,0x01,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"楮\",5348*/},{\n\n0x92,0x8A,0xBF,0x4A,0x12,0x00,0x12,0x4A,0xBF,0x8A,0x92,0x00,0x08,0x09,0x07,0x01,\n0x01,0x09,0x09,0x07,0x00,0x00,/*\"棼\",5349*/},{\n\n0x88,0x68,0xFF,0x48,0x3A,0xEA,0xBA,0xAF,0xBA,0xEA,0x3A,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"櫝\",5350*/},{\n\n0x22,0x3E,0x2A,0x7F,0x2A,0xBE,0x42,0x3E,0x0A,0x79,0x08,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"槧\",5351*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0xF8,0xA8,0xAF,0xAA,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"棹\",5352*/},{\n\n0xC8,0xFF,0x48,0xB7,0x4D,0xA7,0x25,0xFD,0x57,0xFD,0x57,0x00,0x0F,0x00,0x0D,0x01,\n0x05,0x08,0x0F,0x05,0x07,0x05,/*\"欏\",5353*/},{\n\n0x84,0x64,0xFF,0x24,0x48,0xFA,0x4A,0xFE,0x49,0xF9,0x48,0x00,0x00,0x0F,0x00,0x02,\n0x0B,0x0A,0x0F,0x0A,0x0B,0x02,/*\"棰\",5354*/},{\n\n0x88,0x68,0xFF,0x28,0x44,0xF4,0x95,0x96,0x94,0xF4,0x04,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"椋\",5355*/},{\n\n0x88,0x68,0xFF,0x48,0xBA,0xAB,0xBA,0x00,0xFE,0x32,0xCE,0x00,0x00,0x0F,0x02,0x0A,\n0x0E,0x03,0x02,0x0F,0x02,0x01,/*\"槨\",5356*/},{\n\n0xC8,0xFF,0x28,0x64,0xDC,0x88,0xAA,0xFF,0xAA,0xBE,0x08,0x00,0x0F,0x00,0x0A,0x07,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"楗\",5357*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xAA,0x2A,0xFF,0x2A,0xBE,0x08,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x09,0x0F,0x01,0x02,0x04,/*\"棣\",5358*/},{\n\n0x88,0x68,0xFF,0x48,0x00,0xFE,0xAA,0xAA,0xFA,0xAA,0xAE,0x00,0x00,0x0F,0x08,0x06,\n0x01,0x0F,0x04,0x04,0x04,0x0F,/*\"椐\",5359*/},{\n\n0x88,0x68,0xFF,0x48,0xA2,0x6A,0xBA,0xAF,0xAA,0x6A,0xA2,0x00,0x00,0x0F,0x00,0x02,\n0x0A,0x06,0x03,0x06,0x0A,0x02,/*\"楱\",5360*/},{\n\n0x88,0x68,0xFF,0x48,0x88,0x82,0xFF,0xAA,0xAA,0xFF,0x82,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x09,0x08,0x09,0x0A,/*\"椹\",5361*/},{\n\n0x84,0x64,0xFF,0x24,0xFA,0x0A,0x5A,0xEF,0x5A,0x0A,0xFA,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"楠\",5362*/},{\n\n0x88,0x68,0xFF,0x48,0x12,0xEA,0xA6,0xBF,0xA6,0xEA,0x12,0x00,0x00,0x0F,0x00,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"楂\",5363*/},{\n\n0x84,0x64,0xFF,0x44,0xFA,0xAA,0x8A,0xFF,0x8A,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"楝\",5364*/},{\n\n0xC8,0xFF,0x48,0x7F,0xD5,0x77,0xDD,0x4A,0x7B,0xCE,0x7A,0x00,0x0F,0x00,0x08,0x0B,\n0x06,0x02,0x07,0x0A,0x0B,0x0C,/*\"欖\",5365*/},{\n\n0x88,0x68,0xFF,0x48,0x10,0xF7,0x55,0x55,0x55,0xF7,0x10,0x00,0x00,0x0F,0x00,0x04,\n0x07,0x05,0x05,0x05,0x0F,0x02,/*\"楫\",5366*/},{\n\n0x88,0x68,0xFF,0x28,0xC0,0x5E,0xD2,0x12,0xD2,0x5E,0xC0,0x00,0x00,0x0F,0x00,0x0F,\n0x04,0x0F,0x00,0x0F,0x04,0x0F,/*\"榀\",5367*/},{\n\n0x4C,0x2B,0x1E,0x2A,0x4A,0x80,0x7F,0x55,0x55,0x5D,0x41,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"榘\",5368*/},{\n\n0x88,0x68,0xFF,0x48,0x92,0xFE,0x51,0x08,0xFF,0x10,0x0C,0x00,0x00,0x0F,0x01,0x00,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"楸\",5369*/},{\n\n0xC8,0xFF,0x48,0x00,0xFE,0x25,0x08,0xE7,0x21,0xEF,0x08,0x00,0x0F,0x00,0x02,0x0F,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"椴\",5370*/},{\n\n0x88,0x68,0xFF,0x48,0x11,0xF2,0x00,0xFC,0x56,0x55,0xDC,0x00,0x00,0x0F,0x08,0x04,\n0x03,0x04,0x0B,0x0A,0x0A,0x0B,/*\"槌\",5371*/},{\n\n0xC8,0xFF,0x48,0xAA,0xF3,0xAA,0x00,0xFE,0xAA,0xAA,0xFE,0x00,0x0F,0x04,0x0A,0x0F,\n0x02,0x04,0x08,0x07,0x08,0x0E,/*\"櫬\",5372*/},{\n\n0x88,0x68,0xFF,0x48,0xFF,0x15,0xFF,0xA0,0xFF,0x15,0xFF,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"櫚\",5373*/},{\n\n0x88,0x68,0xFF,0x28,0x44,0xD5,0x76,0x5C,0x56,0x55,0x44,0x00,0x00,0x0F,0x04,0x0A,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"槎\",5374*/},{\n\n0xC8,0xFF,0x48,0xBE,0x65,0x30,0xAF,0x3A,0x65,0xBF,0x20,0x00,0x0F,0x01,0x04,0x05,\n0x05,0x0F,0x05,0x05,0x04,0x01,/*\"櫸\",5375*/},{\n\n0x88,0x68,0xFF,0x48,0x06,0xEA,0xAA,0xAB,0xAA,0xEA,0x06,0x00,0x00,0x0F,0x00,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"楦\",5376*/},{\n\n0x84,0x64,0xFF,0x24,0xFF,0x09,0xE9,0xAF,0xA9,0xA9,0xEF,0x00,0x00,0x0F,0x08,0x07,\n0x00,0x0F,0x0A,0x0A,0x0A,0x0F,/*\"楣\",5377*/},{\n\n0xC8,0xFF,0x48,0xB9,0x87,0xAD,0x95,0xAD,0xC3,0xBE,0x00,0x00,0x0F,0x08,0x0F,0x08,\n0x0F,0x08,0x0F,0x08,0x0F,0x08,/*\"楹\",5378*/},{\n\n0x88,0x68,0xFF,0x48,0xA2,0x6A,0xBA,0xAF,0xAA,0x6A,0xA2,0x00,0x00,0x0F,0x00,0x0A,\n0x06,0x02,0x0F,0x02,0x06,0x0A,/*\"榛\",5379*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x52,0xFE,0x02,0xFE,0x52,0x52,0x00,0x00,0x0F,0x00,0x0F,\n0x09,0x0F,0x08,0x0F,0x09,0x09,/*\"榧\",5380*/},{\n\n0x88,0x68,0xFF,0x28,0x40,0x5F,0xD5,0x15,0x55,0x5F,0xC0,0x00,0x00,0x0F,0x00,0x05,\n0x0A,0x0F,0x00,0x05,0x0A,0x0F,/*\"榻\",5381*/},{\n\n0x88,0x68,0xFF,0x28,0x44,0xFE,0xAB,0xAA,0xFF,0xAA,0xAA,0x00,0x00,0x0F,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"榫\",5382*/},{\n\n0x84,0x64,0xFF,0xA4,0xFE,0xAB,0xFE,0x40,0x88,0xFF,0x08,0x00,0x00,0x0F,0x04,0x02,\n0x09,0x0F,0x00,0x08,0x0F,0x00,/*\"榭\",5383*/},{\n\n0x88,0x68,0xFF,0x48,0x80,0xBE,0xEA,0xAB,0xAA,0xBE,0x80,0x00,0x00,0x0F,0x00,0x02,\n0x05,0x04,0x0E,0x04,0x05,0x02,/*\"槔\",5384*/},{\n\n0x88,0x68,0xFF,0x48,0x22,0xFA,0xAA,0xAB,0xAA,0xFA,0x22,0x00,0x00,0x0F,0x00,0x04,\n0x02,0x0F,0x09,0x02,0x04,0x0A,/*\"榱\",5385*/},{\n\n0x88,0x68,0xFF,0x48,0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"槁\",5386*/},{\n\n0x84,0xB5,0x66,0x3C,0x26,0xB5,0x40,0x3F,0x15,0x95,0xFF,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"槊\",5387*/},{\n\n0x88,0x68,0xFF,0x28,0x56,0xEA,0xAA,0xBB,0xAA,0xEA,0x06,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"檳\",5388*/},{\n\n0x88,0x68,0xFF,0x48,0x96,0x4A,0x22,0x13,0x22,0x4A,0x96,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"榕\",5389*/},{\n\n0x88,0x68,0xFF,0x28,0x55,0x56,0x54,0x92,0xFF,0x5A,0xD4,0x00,0x00,0x0F,0x00,0x0F,\n0x05,0x0F,0x00,0x0F,0x05,0x0F,/*\"櫧\",5390*/},{\n\n0x88,0x68,0xFF,0x48,0xFF,0x05,0xED,0xB5,0xBD,0xB5,0xEF,0x00,0x00,0x0F,0x08,0x07,\n0x00,0x0F,0x02,0x02,0x0A,0x0F,/*\"榍\",5391*/},{\n\n0x88,0x68,0xFF,0x48,0xE2,0xAF,0xAA,0xFA,0xAA,0xAF,0xE2,0x00,0x00,0x0F,0x00,0x0A,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0A,/*\"槿\",5392*/},{\n\n0x84,0x64,0xFF,0x24,0xDA,0x56,0x5A,0x5F,0x5A,0x56,0xDA,0x00,0x00,0x0F,0x00,0x0F,\n0x08,0x0F,0x0D,0x0F,0x08,0x0F,/*\"檣\",5393*/},{\n\n0x88,0x68,0xFF,0x48,0xFC,0x44,0xFC,0x54,0xFF,0x04,0xE5,0x00,0x00,0x0F,0x08,0x07,\n0x0A,0x0F,0x05,0x03,0x05,0x0E,/*\"槭\",5394*/},{\n\n0x88,0x68,0xFF,0x28,0x4C,0xD5,0x45,0x5F,0x45,0x55,0x4C,0x00,0x00,0x0F,0x00,0x00,\n0x01,0x01,0x09,0x09,0x07,0x00,/*\"樗\",5395*/},{\n\n0x88,0x68,0xFF,0x48,0x0D,0xF6,0x94,0x97,0x94,0xF6,0x0D,0x00,0x00,0x0F,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"樘\",5396*/},{\n\n0xA9,0x55,0xAB,0xFD,0x29,0x45,0xFA,0xAF,0xAA,0xFC,0x0A,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"櫫\",5397*/},{\n\n0xC8,0xFF,0x48,0xF4,0x53,0xFA,0x56,0xF2,0x24,0xFF,0x80,0x00,0x0F,0x08,0x07,0x01,\n0x07,0x09,0x0F,0x01,0x0F,0x00,/*\"槲\",5398*/},{\n\n0xC8,0xFF,0x48,0xF9,0xAD,0xFB,0x10,0xEC,0x0B,0xF8,0x08,0x00,0x0F,0x02,0x03,0x02,\n0x0F,0x09,0x04,0x03,0x04,0x08,/*\"橄\",5399*/},{\n\n0xC8,0xFF,0x48,0xA4,0x24,0xFF,0xA4,0xF8,0x08,0xFF,0x4A,0x00,0x0F,0x00,0x0F,0x04,\n0x0F,0x08,0x0B,0x09,0x09,0x0B,/*\"樾\",5400*/},{\n\n0x12,0xEA,0xAF,0xEA,0x8F,0x7A,0x88,0x57,0x24,0x5C,0x84,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"檠\",5401*/},{\n\n0x9A,0x4A,0xEE,0xBA,0xAA,0xAF,0xAA,0xAA,0xAE,0xEA,0x1A,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"橐\",5402*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x2A,0xF2,0x2A,0xA2,0xDE,0x32,0x00,0x00,0x0F,0x08,0x07,\n0x09,0x07,0x09,0x05,0x03,0x0C,/*\"橛\",5403*/},{\n\n0x84,0x64,0xFF,0x24,0x08,0xFC,0x57,0x54,0xFD,0x56,0x54,0x00,0x00,0x0F,0x00,0x0C,\n0x03,0x0D,0x01,0x0D,0x01,0x0D,/*\"樵\",5404*/},{\n\n0x88,0x68,0xFF,0x48,0x72,0x46,0x6D,0xD7,0x6D,0x46,0x72,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x07,0x05,0x0F,0x01,0x0F,/*\"檎\",5405*/},{\n\n0x88,0x68,0xFF,0x28,0x44,0xBE,0xD5,0xBD,0xD7,0xBC,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"櫓\",5406*/},{\n\n0x84,0x64,0xFF,0x24,0xFA,0xAB,0xDE,0xCA,0xBE,0xAB,0xFA,0x00,0x00,0x0F,0x00,0x02,\n0x06,0x0A,0x02,0x0A,0x0F,0x02,/*\"樽\",5407*/},{\n\n0x88,0x68,0xFF,0x48,0xFF,0x05,0xAD,0x15,0xBD,0x15,0x2F,0x00,0x00,0x0F,0x08,0x07,\n0x02,0x05,0x05,0x0F,0x05,0x05,/*\"樨\",5408*/},{\n\n0x84,0x64,0xFF,0x24,0xE8,0x59,0xEB,0x7D,0xCD,0x4B,0xD8,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x0E,0x0A,0x0E,0x01,0x0F,/*\"橘\",5409*/},{\n\n0xC8,0xFF,0x48,0xDC,0xB3,0xC8,0xAC,0x6B,0xBA,0x26,0xA0,0x00,0x0F,0x00,0x0E,0x00,\n0x06,0x0A,0x05,0x0A,0x0F,0x02,/*\"櫞\",5410*/},{\n\n0x88,0x68,0xFF,0x28,0xCD,0x55,0x45,0xDF,0x45,0x55,0xCD,0x00,0x00,0x0F,0x00,0x0F,\n0x05,0x05,0x07,0x05,0x05,0x0F,/*\"檑\",5411*/},{\n\n0x88,0x68,0xFF,0x48,0xFE,0x15,0xAD,0xB5,0xA7,0xAC,0x14,0x00,0x00,0x0F,0x08,0x07,\n0x00,0x0E,0x0A,0x0A,0x0E,0x00,/*\"檐\",5412*/},{\n\n0xC8,0xFF,0x4A,0x3E,0xA2,0xBA,0xAB,0xBA,0x62,0x3E,0x02,0x00,0x0F,0x02,0x0A,0x06,\n0x02,0x0F,0x02,0x06,0x0A,0x02,/*\"檁\",5413*/},{\n\n0x20,0x1F,0x75,0x55,0x77,0x80,0x0A,0x2E,0x7B,0x2E,0x0A,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"檗\",5414*/},{\n\n0x88,0x68,0xFF,0x28,0x56,0x2A,0x5A,0x43,0x5A,0x2A,0x5E,0x00,0x00,0x0F,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"檫\",5415*/},{\n\n0x04,0xF5,0x96,0x7C,0x96,0xF5,0x04,0x10,0xFF,0x12,0x14,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x08,0x07,0x00,0x07,0x08,/*\"猷\",5416*/},{\n\n0x48,0x2A,0x3A,0xAF,0xEA,0x0A,0x44,0x2B,0x12,0x2E,0x42,0x0A,0x0A,0x0A,0x06,0x02,\n0x03,0x02,0x06,0x0B,0x0A,0x0A,/*\"獒\",5417*/},{\n\n0x82,0x7E,0x92,0xF2,0x10,0xC8,0x47,0x42,0x52,0xDE,0x00,0x08,0x04,0x02,0x01,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"歿\",5418*/},{\n\n0x82,0x7E,0x92,0xF2,0x00,0xFE,0x92,0x92,0x92,0xFE,0x00,0x08,0x04,0x02,0x01,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x08,/*\"殂\",5419*/},{\n\n0x82,0x7E,0x92,0xF2,0x84,0xFB,0xAA,0xAA,0xAA,0xFA,0x82,0x08,0x04,0x02,0x01,0x04,\n0x0B,0x06,0x0A,0x06,0x0A,0x0E,/*\"殤\",5420*/},{\n\n0x82,0x7E,0x92,0xF2,0x10,0x48,0x24,0x93,0x44,0x08,0x90,0x08,0x04,0x02,0x01,0x08,\n0x09,0x05,0x04,0x02,0x01,0x00,/*\"殄\",5421*/},{\n\n0x82,0x7E,0x92,0xF2,0x00,0xF0,0x57,0x55,0x55,0x57,0xF0,0x08,0x04,0x02,0x01,0x00,\n0x07,0x0D,0x05,0x05,0x0D,0x07,/*\"殞\",5422*/},{\n\n0x62,0x9E,0xF2,0x00,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x08,0x06,0x01,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"殮\",5423*/},{\n\n0x82,0x7E,0x92,0xF2,0x00,0x2A,0x32,0x26,0xAA,0x71,0x2D,0x08,0x04,0x02,0x01,0x00,\n0x01,0x01,0x09,0x0F,0x01,0x01,/*\"殍\",5424*/},{\n\n0x62,0x9E,0xF2,0x00,0xF7,0x55,0x57,0xF0,0x57,0x55,0xF7,0x08,0x06,0x01,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"殫\",5425*/},{\n\n0x82,0x7E,0x92,0xF2,0x00,0xF2,0x92,0xFA,0x46,0x92,0x70,0x08,0x04,0x02,0x01,0x08,\n0x08,0x0A,0x0B,0x09,0x08,0x0B,/*\"殛\",5426*/},{\n\n0x62,0x9E,0xF2,0x00,0x56,0xEA,0xAA,0xBB,0xAA,0xEA,0x06,0x08,0x06,0x01,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"殯\",5427*/},{\n\n0x62,0x9E,0xF2,0x00,0x62,0xAA,0xAA,0xAF,0xAA,0xAA,0x62,0x08,0x06,0x01,0x00,0x08,\n0x0B,0x0E,0x0A,0x0E,0x0B,0x08,/*\"殪\",5428*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x80,0x72,0x02,0xFE,0x02,0xFE,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x04,0x03,0x08,0x08,0x07,/*\"軔\",5429*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xFE,0x02,0xFA,0x8A,0xFA,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x07,0x00,0x07,0x08,0x0E,/*\"軛\",5430*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xC8,0x48,0x7F,0x48,0xC8,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"軲\",5431*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xF2,0x12,0xF2,0xFE,0x02,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x03,0x09,0x09,0x0F,0x00,/*\"軻\",5432*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xF8,0x28,0xA8,0xFF,0xAA,0xAA,0xDA,0x02,0x02,0x0F,0x06,0x0B,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"轤\",5433*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0x7E,0x42,0x42,0x42,0x7E,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x08,0x06,0x00,0x02,0x0C,/*\"軹\",5434*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x10,0x4E,0x48,0xFF,0x48,0x48,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x04,0x03,0x00,0x07,0x08,/*\"軼\",5435*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x10,0x4C,0xB3,0x44,0x88,0x10,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x09,0x04,0x02,0x01,0x00,/*\"軫\",5436*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0x4A,0x52,0xFE,0x51,0x49,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"軤\",5437*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xB6,0xAD,0xBE,0xEB,0xBE,0x94,0xAB,0x02,0x02,0x0F,0x02,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"轢\",5438*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x40,0xA2,0x9E,0x82,0xA2,0xBE,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"軺\",5439*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x24,0xE4,0x24,0xFF,0x04,0x05,0x02,0x02,0x0F,0x02,0x02,\n0x04,0x07,0x02,0x03,0x04,0x0E,/*\"軾\",5440*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0x32,0x2A,0xE6,0x32,0x62,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x09,0x09,0x0F,0x09,0x08,/*\"輊\",5441*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x28,0x24,0xE3,0x24,0x28,0x10,0x02,0x02,0x0F,0x02,0x0A,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"輇\",5442*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x44,0xAB,0x92,0x92,0xAE,0x40,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"輅\",5443*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFE,0x52,0xFE,0x02,0xFA,0x02,0x02,0x02,0x02,0x0F,0x02,0x03,\n0x02,0x0F,0x01,0x07,0x08,0x0E,/*\"輒\",5444*/},{\n\n0x48,0x6A,0xDA,0x4F,0x5A,0xE8,0x5A,0x4F,0xDA,0x6A,0x48,0x04,0x04,0x07,0x05,0x05,\n0x0F,0x05,0x05,0x07,0x04,0x04,/*\"輦\",5445*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFE,0x52,0xDA,0x72,0x5A,0x52,0xFE,0x02,0x02,0x0F,0x02,0x0F,\n0x00,0x03,0x02,0x02,0x08,0x0F,/*\"輞\",5446*/},{\n\n0xFA,0xAA,0xFF,0xAA,0x55,0x49,0xD7,0x00,0xD5,0x49,0xD7,0x02,0x02,0x0F,0x0A,0x05,\n0x02,0x05,0x08,0x05,0x02,0x0D,/*\"輟\",5447*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x04,0xDB,0x44,0xDB,0x44,0xDB,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x05,0x07,0x05,0x0F,/*\"輜\",5448*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0xA0,0x6A,0xBA,0xAF,0xEA,0xA2,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0A,0x06,0x03,0x06,0x0A,/*\"輳\",5449*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFE,0x2A,0xBE,0x2B,0xBE,0x2A,0xBA,0x02,0x02,0x0F,0x0A,0x07,\n0x00,0x0F,0x09,0x07,0x09,0x0C,/*\"轆\",5450*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x95,0x6E,0xC4,0x5F,0xEE,0x55,0x02,0x02,0x0F,0x02,0x02,\n0x09,0x06,0x01,0x02,0x0F,0x02,/*\"轔\",5451*/},{\n\n0x82,0xFA,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xFA,0x82,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0B,0x0A,0x0A,0x0A,0x0E,0x00,/*\"軎\",5452*/},{\n\n0x00,0x04,0x24,0x24,0xE7,0x9C,0x92,0xEB,0xAA,0xA6,0xB2,0x01,0x01,0x09,0x09,0x09,\n0x06,0x04,0x0A,0x0A,0x09,0x0C,/*\"戔\",5453*/},{\n\n0x08,0xFC,0xAA,0xAD,0xAA,0xFC,0x08,0x10,0xFF,0x88,0x6A,0x03,0x0E,0x0A,0x0A,0x0A,\n0x0E,0x08,0x04,0x03,0x05,0x0E,/*\"戧\",5454*/},{\n\n0x01,0x7D,0x55,0xD5,0x57,0x55,0x55,0xD5,0x55,0x7D,0x01,0x02,0x0A,0x0A,0x09,0x0B,\n0x05,0x05,0x05,0x0B,0x09,0x0C,/*\"戛\",5455*/},{\n\n0x00,0xFA,0xAA,0xAF,0xAA,0xFA,0x00,0x10,0xFF,0x88,0x6A,0x02,0x02,0x02,0x0F,0x02,\n0x02,0x0A,0x04,0x03,0x05,0x0E,/*\"戟\",5456*/},{\n\n0x10,0xF7,0x55,0x55,0x55,0xF7,0x10,0xFF,0x10,0x92,0x54,0x04,0x07,0x05,0x05,0x05,\n0x0F,0x04,0x03,0x05,0x08,0x0E,/*\"戢\",5457*/},{\n\n0x80,0x82,0xFF,0xAA,0xAA,0xFF,0x82,0x10,0xFF,0x88,0x6A,0x00,0x0F,0x0A,0x09,0x08,\n0x09,0x0A,0x04,0x03,0x05,0x0E,/*\"戡\",5458*/},{\n\n0x00,0xDF,0x95,0xF5,0x95,0x9F,0x00,0x10,0xFF,0x88,0x6A,0x09,0x0A,0x0A,0x0F,0x0A,\n0x0A,0x08,0x04,0x03,0x05,0x0E,/*\"戥\",5459*/},{\n\n0x91,0xAF,0x95,0xAD,0x81,0xA7,0xBC,0x10,0xFF,0x88,0x6A,0x0F,0x08,0x0F,0x08,0x07,\n0x04,0x0F,0x04,0x03,0x05,0x0E,/*\"戤\",5460*/},{\n\n0x2D,0xAB,0xAD,0xA1,0xAD,0xAB,0x2D,0x10,0xFF,0x88,0x6A,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x08,0x04,0x03,0x05,0x0E,/*\"戩\",5461*/},{\n\n0x9C,0x90,0xFC,0x04,0xF4,0x54,0x74,0xD4,0x0F,0xF4,0x46,0x03,0x08,0x07,0x00,0x07,\n0x05,0x07,0x0D,0x04,0x07,0x0C,/*\"臧\",5462*/},{\n\n0xFE,0x82,0xBA,0xAA,0xBA,0x82,0x00,0xE2,0x9E,0xF2,0x02,0x0F,0x0B,0x0A,0x0B,0x0A,\n0x0B,0x00,0x0F,0x08,0x07,0x08,/*\"甌\",5463*/},{\n\n0x48,0x44,0x53,0x64,0xC8,0x00,0xE2,0x9E,0xF2,0x02,0x00,0x00,0x02,0x04,0x0B,0x00,\n0x00,0x0F,0x08,0x07,0x08,0x0E,/*\"瓴\",5464*/},{\n\n0xAA,0xB2,0xB3,0xAA,0x20,0xC2,0xBE,0x12,0xF2,0x02,0x00,0x0F,0x04,0x04,0x0F,0x00,\n0x0F,0x04,0x01,0x07,0x08,0x0E,/*\"瓿\",5465*/},{\n\n0x8A,0xBA,0xEA,0xAF,0xEA,0xBA,0x8A,0xC0,0xD4,0xAA,0x95,0x00,0x0C,0x0B,0x0A,0x06,\n0x0A,0x02,0x06,0x08,0x08,0x0C,/*\"甏\",5466*/},{\n\n0x3E,0xAB,0xBE,0xAB,0x3E,0x00,0xE2,0x9E,0xF2,0x02,0x00,0x00,0x0F,0x0A,0x0F,0x00,\n0x00,0x0F,0x08,0x07,0x08,0x0E,/*\"甑\",5467*/},{\n\n0xA0,0x9F,0xF5,0xD5,0xF7,0x80,0x8A,0xAE,0xFB,0xAE,0x8A,0x00,0x0C,0x0B,0x0A,0x06,\n0x0A,0x02,0x06,0x08,0x08,0x0C,/*\"甓\",5468*/},{\n\n0x00,0x20,0x60,0xA0,0x20,0x3F,0x24,0x24,0xA4,0x64,0x00,0x08,0x08,0x08,0x04,0x05,\n0x02,0x02,0x05,0x04,0x08,0x08,/*\"攴\",5469*/},{\n\n0x40,0xA4,0x94,0x8C,0x87,0x84,0x84,0x9C,0xA0,0xA0,0x30,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"旮\",5470*/},{\n\n0x00,0x9F,0x95,0x95,0xF5,0x95,0x95,0x95,0x15,0x1F,0x00,0x08,0x08,0x04,0x02,0x01,\n0x00,0x00,0x07,0x08,0x08,0x0C,/*\"旯\",5471*/},{\n\n0xFE,0x22,0x22,0xFE,0x40,0x42,0x42,0xFE,0x42,0x42,0x40,0x07,0x02,0x02,0x07,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"旰\",5472*/},{\n\n0x00,0x5F,0x55,0x55,0x55,0xD5,0x55,0x55,0x55,0x5F,0x00,0x09,0x09,0x05,0x05,0x03,\n0x01,0x03,0x05,0x05,0x09,0x09,/*\"昊\",5473*/},{\n\n0x60,0xA8,0xAF,0xA9,0x29,0xFB,0x2D,0xA9,0xAF,0xA8,0x60,0x02,0x0A,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x0A,0x02,/*\"曇\",5474*/},{\n\n0x40,0x5F,0x55,0x55,0xD5,0xF5,0xD5,0x55,0x55,0x5F,0x40,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"杲\",5475*/},{\n\n0x00,0xDF,0x55,0x55,0x55,0x55,0xD5,0x55,0x55,0x5F,0x40,0x08,0x07,0x08,0x08,0x04,\n0x02,0x01,0x02,0x04,0x08,0x08,/*\"昃\",5476*/},{\n\n0xFE,0x22,0x22,0xFE,0x00,0xFE,0x12,0x12,0xF1,0x11,0x10,0x07,0x02,0x02,0x0B,0x04,\n0x03,0x00,0x00,0x0F,0x00,0x00,/*\"昕\",5477*/},{\n\n0xFE,0x22,0x22,0xFE,0x10,0x08,0x17,0x24,0x84,0x44,0xFC,0x07,0x02,0x02,0x07,0x00,\n0x02,0x02,0x01,0x08,0x08,0x07,/*\"昀\",5478*/},{\n\n0x00,0x1F,0xD5,0x15,0x15,0xF5,0x15,0x15,0x95,0x5F,0x00,0x08,0x09,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"炅\",5479*/},{\n\n0x00,0x9F,0x55,0x75,0x55,0xD5,0x55,0x55,0x55,0x5F,0xC0,0x01,0x06,0x04,0x06,0x05,\n0x04,0x05,0x0A,0x08,0x08,0x07,/*\"曷\",5480*/},{\n\n0x48,0x44,0xAB,0x92,0xAA,0xA6,0xA0,0xBF,0xA0,0xA2,0x2C,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"昝\",5481*/},{\n\n0xC0,0x5F,0x35,0x35,0xD5,0x15,0xD5,0x55,0x55,0x5F,0xC0,0x07,0x04,0x0A,0x05,0x03,\n0x00,0x0F,0x00,0x00,0x04,0x07,/*\"昴\",5482*/},{\n\n0x00,0x9F,0x95,0x95,0xB5,0xD5,0x95,0x95,0x95,0x9F,0x00,0x08,0x08,0x0A,0x0C,0x08,\n0x08,0x08,0x0C,0x0A,0x08,0x08,/*\"昱\",5483*/},{\n\n0x40,0xC8,0x08,0xF9,0x42,0xA0,0x10,0xFE,0x12,0x12,0xFE,0x04,0x03,0x08,0x0F,0x00,\n0x01,0x02,0x05,0x09,0x09,0x09,/*\"昶\",5484*/},{\n\n0xFE,0x22,0xFE,0x00,0xFF,0xA5,0xEF,0xB5,0xA5,0xAF,0x25,0x07,0x02,0x07,0x00,0x0F,\n0x08,0x0B,0x0A,0x0A,0x0B,0x08,/*\"暱\",5485*/},{\n\n0x48,0x48,0xAA,0xAA,0xBA,0xCF,0xEA,0xDC,0xCA,0x49,0x68,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"耆\",5486*/},{\n\n0x00,0xDF,0x55,0x55,0x55,0x55,0x55,0xF5,0x55,0x7F,0xC0,0x08,0x07,0x01,0x01,0x05,\n0x07,0x08,0x05,0x02,0x05,0x0E,/*\"晟\",5487*/},{\n\n0xFE,0x22,0xFE,0x00,0xAA,0xFA,0xAF,0xFA,0xAF,0xFA,0xAA,0x07,0x02,0x07,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"曄\",5488*/},{\n\n0x00,0x5F,0x95,0x15,0xF5,0x15,0xF5,0x15,0x95,0x5F,0x00,0x08,0x09,0x04,0x02,0x01,\n0x00,0x07,0x08,0x08,0x09,0x0C,/*\"晁\",5489*/},{\n\n0xC0,0x5F,0x55,0x55,0xD5,0x75,0x55,0x55,0x55,0x5F,0xC0,0x08,0x09,0x09,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x00,/*\"晏\",5490*/},{\n\n0xFE,0x22,0xFE,0x00,0xF3,0x55,0x55,0xFF,0x55,0x55,0xF3,0x07,0x02,0x07,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"暉\",5491*/},{\n\n0xFE,0x22,0xFE,0x00,0xF4,0x54,0x54,0xFF,0x54,0x55,0xF6,0x07,0x02,0x07,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"晡\",5492*/},{\n\n0xFE,0x22,0xFE,0x08,0x24,0x22,0x29,0xB2,0x64,0x08,0x08,0x07,0x02,0x07,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"晗\",5493*/},{\n\n0x80,0x5F,0x75,0x55,0xD5,0x15,0x15,0xF5,0x55,0x9F,0x00,0x04,0x05,0x0E,0x0B,0x0A,\n0x0A,0x0A,0x0B,0x0E,0x02,0x02,/*\"晷\",5494*/},{\n\n0xFE,0x22,0xFE,0x00,0x06,0xEA,0xAA,0xAB,0xAA,0xEA,0x06,0x07,0x02,0x07,0x00,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"暄\",5495*/},{\n\n0xFE,0x22,0xFE,0x00,0x4A,0x32,0x4E,0xC0,0x4F,0x32,0x49,0x07,0x02,0x07,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"暌\",5496*/},{\n\n0xFE,0x22,0xFE,0x00,0x5A,0x8E,0x2A,0x5E,0x69,0x0D,0x59,0x07,0x02,0x07,0x00,0x0A,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"曖\",5497*/},{\n\n0xFE,0x22,0xFE,0x00,0x03,0x7D,0x55,0xD5,0x55,0x7D,0x03,0x07,0x02,0x07,0x00,0x09,\n0x05,0x01,0x01,0x01,0x05,0x09,/*\"暝\",5498*/},{\n\n0xFE,0x22,0xFE,0x00,0xBA,0xAB,0xBA,0x10,0xEF,0x08,0xF8,0x07,0x02,0x07,0x00,0x0A,\n0x0E,0x03,0x0A,0x05,0x02,0x0D,/*\"暾\",5499*/},{\n\n0xFE,0x22,0xFE,0x00,0xF4,0x55,0x15,0xFF,0x15,0x55,0xF4,0x07,0x02,0x07,0x00,0x0D,\n0x05,0x0D,0x07,0x0D,0x05,0x0D,/*\"曛\",5500*/},{\n\n0xFE,0x22,0xFE,0x00,0x2B,0xF5,0xAF,0xA0,0xEB,0xB5,0xAF,0x07,0x02,0x07,0x00,0x00,\n0x0F,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"曜\",5501*/},{\n\n0xFE,0x22,0xFE,0x00,0xA2,0xEA,0xAB,0xBE,0xEB,0xAA,0xE2,0x07,0x02,0x07,0x01,0x02,\n0x0B,0x06,0x08,0x07,0x0A,0x0D,/*\"曦\",5502*/},{\n\n0x20,0xEF,0xA9,0xA9,0xE9,0x3B,0xED,0xA9,0xA9,0xEF,0x20,0x08,0x0A,0x06,0x0F,0x0A,\n0x02,0x02,0x07,0x0A,0x0A,0x08,/*\"曩\",5503*/},{\n\n0x08,0xEA,0xBE,0xAA,0xAA,0xAF,0xAA,0xAA,0xBE,0xEA,0x08,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"賁\",5504*/},{\n\n0x02,0xE2,0xBF,0xA2,0xA2,0xAF,0xAA,0xAA,0xAF,0xE2,0x22,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"貰\",5505*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x00,0x7E,0xC2,0x42,0xC2,0x7E,0x00,0x09,0x05,0x05,0x09,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"貺\",5506*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x00,0xD8,0x54,0x53,0x50,0xD8,0x30,0x09,0x05,0x05,0x09,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"貽\",5507*/},{\n\n0x28,0xBA,0xEF,0xBA,0xA8,0xC0,0xAA,0x9F,0xA2,0xBE,0x60,0x00,0x07,0x0C,0x05,0x06,\n0x04,0x05,0x06,0x0C,0x07,0x00,/*\"贄\",5508*/},{\n\n0x10,0xFE,0xB0,0xAF,0xAA,0xAA,0xA0,0xAF,0xB4,0xF2,0x19,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"貲\",5509*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x00,0x24,0x34,0xAD,0x66,0x24,0x94,0x09,0x05,0x05,0x09,0x00,\n0x09,0x09,0x04,0x02,0x05,0x08,/*\"賅\",5510*/},{\n\n0xFE,0x2A,0xFE,0x88,0xAA,0xAA,0xFF,0xAA,0xAA,0xBE,0x88,0x09,0x05,0x09,0x0E,0x0B,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x09,/*\"贐\",5511*/},{\n\n0xFE,0x2A,0xFE,0x00,0xFE,0x22,0xEA,0x2A,0xEA,0x2A,0xA2,0x09,0x05,0x09,0x08,0x07,\n0x00,0x0F,0x04,0x03,0x05,0x08,/*\"賑\",5512*/},{\n\n0x2A,0xE6,0x5A,0xD2,0x4A,0x7F,0xCA,0x52,0x5A,0xE6,0x2A,0x00,0x0B,0x06,0x02,0x03,\n0x02,0x02,0x03,0x06,0x0B,0x00,/*\"賚\",5513*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x00,0x28,0xC8,0xFF,0x68,0x89,0x4A,0x09,0x05,0x05,0x09,0x02,\n0x01,0x08,0x0F,0x00,0x01,0x02,/*\"賕\",5514*/},{\n\n0x2A,0xDA,0xAA,0xBA,0x86,0xBB,0x86,0xBA,0xAA,0xD6,0x22,0x08,0x07,0x00,0x0B,0x06,\n0x03,0x06,0x0B,0x00,0x0F,0x00,/*\"齎\",5515*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x00,0x08,0xA6,0x10,0xCF,0x14,0xA2,0x09,0x05,0x05,0x09,0x00,\n0x0A,0x09,0x04,0x03,0x05,0x08,/*\"賧\",5516*/},{\n\n0xFE,0x2A,0x2A,0xFE,0x00,0xFA,0x2A,0xFF,0x2A,0xFB,0x02,0x09,0x05,0x05,0x09,0x02,\n0x06,0x02,0x0A,0x0F,0x02,0x02,/*\"賻\",5517*/},{\n\n0xE0,0x20,0x3F,0xE4,0x04,0xFE,0xAA,0xAA,0xAA,0xFE,0x00,0x07,0x02,0x02,0x03,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"覘\",5518*/},{\n\n0xD6,0x54,0x57,0x54,0xD6,0x00,0xFE,0xAA,0xAA,0xFE,0x00,0x09,0x0B,0x05,0x07,0x05,\n0x08,0x06,0x01,0x07,0x08,0x0C,/*\"覬\",5519*/},{\n\n0x80,0x72,0x82,0xFE,0x82,0x72,0x80,0xFE,0xAA,0xAA,0xFE,0x08,0x08,0x08,0x07,0x04,\n0x04,0x00,0x08,0x07,0x08,0x0E,/*\"覡\",5520*/},{\n\n0x38,0xEA,0xBA,0xAF,0xBA,0xEA,0x38,0xFE,0xAA,0xAA,0xFE,0x00,0x0B,0x06,0x02,0x06,\n0x0B,0x00,0x08,0x07,0x08,0x0E,/*\"覿\",5521*/},{\n\n0xE8,0xA4,0xEA,0x09,0xCA,0x04,0xE8,0xFE,0xAA,0xAA,0xFE,0x0F,0x02,0x0F,0x00,0x03,\n0x08,0x0F,0x08,0x07,0x08,0x0E,/*\"覦\",5522*/},{\n\n0x08,0xEA,0xAF,0xFA,0xAF,0xEA,0x08,0xFE,0xAA,0xAA,0xFE,0x02,0x0F,0x02,0x03,0x0A,\n0x0F,0x02,0x08,0x07,0x08,0x0E,/*\"覯\",5523*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x00,0xFE,0xAA,0xAA,0xFE,0x00,0x0A,0x0A,0x0F,0x0A,0x0A,\n0x08,0x06,0x01,0x07,0x08,0x0C,/*\"覲\",5524*/},{\n\n0x00,0xFC,0x24,0xBF,0x55,0xD5,0x6D,0x00,0xFF,0x95,0xFF,0x08,0x07,0x0A,0x0F,0x08,\n0x0F,0x0A,0x01,0x08,0x07,0x0C,/*\"覷\",5525*/},{\n\n0x08,0x04,0xDE,0x81,0x88,0xC8,0x8F,0x88,0x95,0xA6,0x34,0x02,0x03,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"牮\",5526*/},{\n\n0x9D,0x95,0xF7,0x00,0x5C,0xD7,0x55,0x7D,0x55,0x77,0xDC,0x04,0x06,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x05,0x04,/*\"犟\",5527*/},{\n\n0x90,0x8E,0x88,0xFF,0x48,0x00,0xFF,0x20,0x10,0x08,0x04,0x00,0x00,0x00,0x0F,0x00,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"牝\",5528*/},{\n\n0x48,0xEA,0x5A,0xFF,0x5A,0x68,0xC4,0x6B,0x52,0x6E,0x42,0x08,0x07,0x02,0x05,0x05,\n0x05,0x0F,0x05,0x05,0x05,0x04,/*\"犛\",5529*/},{\n\n0x90,0x8E,0x88,0xFF,0x48,0x00,0xC8,0x48,0x7F,0x48,0xC8,0x00,0x00,0x00,0x0F,0x00,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"牯\",5530*/},{\n\n0x9C,0x88,0xFF,0x48,0x21,0xA5,0xBD,0xA7,0xA5,0xBD,0x21,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"牾\",5531*/},{\n\n0x9C,0x88,0xFF,0x48,0x28,0xA6,0xA4,0xBF,0xA4,0xA4,0x20,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"牿\",5532*/},{\n\n0x9C,0x88,0xFF,0x48,0x10,0xDA,0x56,0xD3,0x16,0xFA,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x02,0x03,0x08,0x0F,0x00,/*\"犄\",5533*/},{\n\n0x9C,0x88,0xFF,0x48,0x00,0xFF,0x55,0x55,0x55,0xFF,0x00,0x00,0x00,0x0F,0x00,0x01,\n0x09,0x05,0x01,0x05,0x09,0x01,/*\"犋\",5534*/},{\n\n0x9C,0x88,0xFF,0x48,0x64,0xDC,0x88,0xAA,0xFF,0xAA,0xBE,0x00,0x00,0x0F,0x00,0x0A,\n0x07,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"犍\",5535*/},{\n\n0x9C,0x88,0xFF,0x48,0xFE,0x2A,0xEA,0x2B,0xEA,0x2A,0xEE,0x00,0x00,0x0F,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"犏\",5536*/},{\n\n0x9C,0x88,0xFF,0x48,0x82,0xBA,0xAA,0xAB,0xAA,0xBA,0x82,0x00,0x00,0x0F,0x00,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"犒\",5537*/},{\n\n0x22,0xAA,0xFF,0xAA,0xA2,0xC0,0xA2,0x9E,0xC2,0x42,0x3E,0x02,0x02,0x02,0x0A,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"挈\",5538*/},{\n\n0x22,0x14,0x81,0xA2,0xA8,0xA6,0xA0,0x5F,0x10,0x12,0x04,0x02,0x02,0x02,0x0A,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"挲\",5539*/},{\n\n0x92,0xFE,0x91,0x28,0xE6,0x20,0xE7,0x08,0x92,0xFE,0x91,0x08,0x07,0x00,0x08,0x07,\n0x08,0x0F,0x00,0x08,0x0F,0x00,/*\"掰\",5540*/},{\n\n0x92,0xFE,0x91,0x08,0xD4,0x53,0xD4,0x08,0x92,0xFE,0x91,0x08,0x07,0x00,0x00,0x0F,\n0x04,0x0F,0x00,0x08,0x0F,0x00,/*\"搿\",5541*/},{\n\n0x20,0x9F,0xF5,0xD5,0xF7,0x80,0x8A,0xAE,0xFB,0x2E,0x0A,0x02,0x02,0x02,0x0A,0x0A,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"擘\",5542*/},{\n\n0x48,0x48,0x2A,0x2A,0x3A,0xCF,0xEA,0xDC,0x4A,0x49,0x68,0x04,0x05,0x05,0x05,0x07,\n0x0A,0x0A,0x0A,0x0A,0x08,0x0C,/*\"耄\",5543*/},{\n\n0x12,0x12,0xFE,0x89,0x40,0x36,0x25,0xFC,0x24,0x26,0x0C,0x01,0x01,0x07,0x08,0x09,\n0x09,0x09,0x0F,0x09,0x09,0x0D,/*\"毪\",5544*/},{\n\n0x20,0x2A,0x2A,0xAA,0x3E,0x55,0x55,0x55,0xD0,0xC0,0x60,0x05,0x05,0x0F,0x0A,0x02,\n0x04,0x05,0x07,0x0A,0x0A,0x0C,/*\"毳\",5545*/},{\n\n0x12,0xFE,0x89,0x32,0xEE,0x08,0xAA,0xFF,0xAA,0xBE,0x08,0x01,0x07,0x08,0x0D,0x0B,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0C,/*\"毽\",5546*/},{\n\n0x58,0x56,0x3B,0xA2,0x5A,0x57,0x9A,0x92,0xFE,0x49,0x49,0x00,0x05,0x05,0x0A,0x05,\n0x02,0x00,0x00,0x07,0x08,0x0E,/*\"毿\",5547*/},{\n\n0xE8,0xA4,0xEA,0x09,0xCA,0x04,0xE8,0x92,0xFE,0x49,0x49,0x0F,0x02,0x0F,0x00,0x03,\n0x08,0x0F,0x00,0x07,0x08,0x0E,/*\"毹\",5548*/},{\n\n0xFD,0x06,0x74,0x57,0x74,0x86,0xFD,0xD4,0x23,0x5E,0x82,0x04,0x05,0x05,0x05,0x07,\n0x0A,0x0A,0x0A,0x0A,0x08,0x0C,/*\"氅\",5549*/},{\n\n0x12,0x12,0xFE,0x89,0x44,0xBE,0xD5,0xBD,0xD7,0xBC,0x40,0x01,0x01,0x07,0x08,0x08,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x0C,/*\"氌\",5550*/},{\n\n0x12,0xFE,0x89,0x00,0x2A,0xE3,0xBE,0xA2,0xBE,0xE3,0x2A,0x01,0x07,0x08,0x08,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"氆\",5551*/},{\n\n0x9F,0xD5,0x7F,0x40,0xFF,0x55,0x5F,0x92,0xFE,0x49,0x49,0x00,0x0F,0x05,0x05,0x07,\n0x05,0x05,0x00,0x07,0x08,0x0E,/*\"氍\",5552*/},{\n\n0x08,0x24,0x2B,0xAA,0x2A,0x2A,0x2A,0x2A,0xEA,0x0A,0x02,0x00,0x08,0x04,0x03,0x00,\n0x00,0x00,0x00,0x03,0x04,0x0E,/*\"氕\",5553*/},{\n\n0x08,0x24,0xAB,0x2A,0x2A,0xAA,0x2A,0x2A,0xEA,0x0A,0x02,0x08,0x04,0x03,0x00,0x00,\n0x0F,0x00,0x00,0x03,0x04,0x0E,/*\"氘\",5554*/},{\n\n0x88,0x24,0x2B,0xEA,0x2A,0x2A,0xAA,0x2A,0xEA,0x0A,0x02,0x07,0x04,0x04,0x07,0x04,\n0x04,0x0F,0x00,0x03,0x04,0x0E,/*\"氙\",5555*/},{\n\n0x08,0x24,0xAB,0x2A,0xAA,0x2A,0xAA,0x2A,0xEA,0x0A,0x02,0x00,0x08,0x07,0x00,0x07,\n0x00,0x0F,0x00,0x03,0x04,0x0E,/*\"氚\",5556*/},{\n\n0x84,0x52,0xF5,0x55,0x55,0x55,0xD5,0x15,0xF5,0x01,0x00,0x02,0x02,0x06,0x09,0x03,\n0x05,0x02,0x02,0x03,0x04,0x0E,/*\"氡\",5557*/},{\n\n0xA8,0xA4,0xEB,0x2A,0xEA,0xAA,0xAA,0x0A,0xFA,0x02,0x02,0x0B,0x0A,0x0E,0x08,0x0E,\n0x0A,0x0B,0x00,0x03,0x04,0x0E,/*\"氬\",5558*/},{\n\n0xC4,0x52,0x55,0xD5,0x55,0x55,0xD5,0x15,0xF5,0x01,0x00,0x0F,0x08,0x0D,0x0B,0x0D,\n0x08,0x0F,0x00,0x03,0x04,0x0E,/*\"氤\",5559*/},{\n\n0x14,0xD2,0x55,0x7D,0x55,0xD5,0x15,0x05,0xFD,0x01,0x01,0x08,0x05,0x03,0x01,0x07,\n0x09,0x0C,0x00,0x03,0x04,0x0E,/*\"氪\",5560*/},{\n\n0x08,0x04,0xEB,0xAA,0x6A,0xAA,0xEA,0x0A,0xFA,0x02,0x02,0x08,0x0E,0x0B,0x0E,0x0A,\n0x0E,0x0B,0x0E,0x0B,0x04,0x0E,/*\"氳\",5561*/},{\n\n0x40,0x20,0x10,0x6C,0x8B,0x08,0x88,0x48,0x38,0x08,0x08,0x08,0x08,0x04,0x04,0x02,\n0x01,0x02,0x04,0x04,0x08,0x08,/*\"攵\",5562*/},{\n\n0x00,0xF4,0x94,0xFF,0x94,0xF4,0x10,0xEF,0x08,0xF8,0x08,0x04,0x02,0x01,0x0F,0x01,\n0x02,0x08,0x05,0x02,0x05,0x08,/*\"敕\",5563*/},{\n\n0x80,0xBE,0xEB,0xAA,0xBE,0x80,0x10,0xEF,0x08,0xF8,0x08,0x08,0x07,0x02,0x0A,0x0E,\n0x00,0x08,0x05,0x02,0x05,0x08,/*\"敫\",5564*/},{\n\n0x00,0xFE,0x90,0x9F,0x3A,0xEA,0xBA,0xAF,0xBA,0xEA,0x3A,0x08,0x07,0x00,0x0F,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"牘\",5565*/},{\n\n0xFE,0x90,0x9F,0x10,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x07,0x00,0x0F,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"牒\",5566*/},{\n\n0xFE,0x90,0x9F,0x10,0xFE,0xAA,0xAA,0xFB,0xAA,0xBA,0xAE,0x07,0x00,0x0F,0x02,0x01,\n0x0F,0x02,0x07,0x02,0x0A,0x0F,/*\"牖\",5567*/},{\n\n0x40,0x52,0x56,0xDA,0x72,0x56,0x59,0x51,0x59,0x55,0x40,0x04,0x02,0x09,0x09,0x0B,\n0x05,0x05,0x05,0x0B,0x08,0x08,/*\"爰\",5568*/},{\n\n0x4A,0x52,0x46,0xE9,0x45,0xF8,0x48,0x7F,0xAA,0xAA,0xD8,0x01,0x02,0x08,0x0F,0x02,\n0x09,0x06,0x02,0x06,0x08,0x0C,/*\"虢\",5569*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0x00,0xFC,0x00,0x00,0xFF,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x00,0x01,0x08,0x08,0x0F,/*\"刖\",5570*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x10,0xD2,0xB2,0x92,0x92,0x92,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"肟\",5571*/},{\n\n0x00,0xFE,0x92,0x92,0x92,0xFE,0x00,0x88,0x44,0x22,0x11,0x08,0x07,0x00,0x08,0x08,\n0x0F,0x00,0x08,0x04,0x02,0x01,/*\"肜\",5572*/},{\n\n0x02,0xEE,0xAA,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xEA,0x02,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"肓\",5573*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x88,0xFF,0x88,0x88,0xFF,0x88,0x08,0x07,0x08,0x0F,0x08,\n0x04,0x03,0x00,0x00,0x0F,0x00,/*\"肼\",5574*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x12,0xF2,0x12,0xF2,0x12,0x10,0x08,0x07,0x08,0x0F,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"朊\",5575*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x08,0xC8,0x3F,0xC8,0x08,0x08,0x08,0x07,0x08,0x0F,0x08,\n0x06,0x01,0x06,0x01,0x06,0x08,/*\"肽\",5576*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x08,0xE8,0x1F,0x88,0x68,0x08,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x00,0x06,0x05,0x04,0x0E,/*\"肱\",5577*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xF4,0x84,0xFF,0x84,0xF4,0x04,0x08,0x07,0x08,0x0F,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"肫\",5578*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xFC,0x44,0x3F,0x44,0x84,0xFC,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x00,0x00,0x00,0x08,0x0F,/*\"肭\",5579*/},{\n\n0x04,0xFA,0xAD,0xFA,0x84,0xED,0xBA,0xAE,0xAA,0xED,0x08,0x00,0x0F,0x04,0x02,0x04,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"餚\",5580*/},{\n\n0x00,0xFE,0x92,0xFE,0x20,0x18,0x07,0xE4,0x04,0x14,0x0C,0x08,0x07,0x08,0x0F,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"肷\",5581*/},{\n\n0xFF,0x49,0xFF,0x0A,0xEE,0xAB,0xEE,0x0A,0xF7,0x55,0x5D,0x07,0x08,0x0F,0x00,0x0F,\n0x02,0x0F,0x00,0x07,0x09,0x0D,/*\"朧\",5582*/},{\n\n0x00,0xFF,0x49,0xFF,0x00,0xFA,0xAA,0xFF,0xAA,0xAA,0xFA,0x08,0x07,0x08,0x0F,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"腖\",5583*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x20,0x20,0xFF,0xA4,0x24,0x24,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x00,0x0F,0x00,0x01,0x02,/*\"胩\",5584*/},{\n\n0xFE,0x92,0xFE,0x00,0xF8,0x28,0xA8,0xFF,0xAA,0xAA,0xDA,0x07,0x08,0x0F,0x04,0x0B,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"臚\",5585*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0xFE,0x92,0xFE,0x92,0xFE,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x01,0x00,0x0F,0x00,0x01,/*\"胛\",5586*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x00,0xFC,0x24,0xFF,0x24,0xFC,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x03,0x01,0x0F,0x01,0x03,/*\"胂\",5587*/},{\n\n0x3E,0xEA,0xAA,0xAA,0xAA,0xBF,0xAA,0xAA,0xAA,0xEA,0x3E,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"胄\",5588*/},{\n\n0x00,0xFE,0x92,0xFE,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x08,0x07,0x08,0x0F,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"胙\",5589*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xFE,0x02,0xFE,0x02,0xFD,0x01,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x00,0x0F,0x0A,0x0C,0x03,/*\"胍\",5590*/},{\n\n0x00,0xFE,0x92,0xFE,0x10,0x48,0x24,0x93,0x44,0x08,0x90,0x08,0x07,0x08,0x0F,0x08,\n0x09,0x05,0x04,0x02,0x01,0x00,/*\"胗\",5591*/},{\n\n0x00,0xFE,0x92,0x92,0xFE,0x10,0xE8,0x27,0xE4,0x04,0xFC,0x08,0x07,0x00,0x08,0x0F,\n0x00,0x03,0x01,0x09,0x08,0x07,/*\"朐\",5592*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xFE,0x22,0x22,0xFE,0x21,0x21,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x04,0x08,0x03,0x04,0x0E,/*\"胝\",5593*/},{\n\n0x00,0xFE,0x92,0xFE,0x10,0xAA,0x92,0xAA,0x92,0xAA,0x02,0x08,0x07,0x08,0x0F,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"脛\",5594*/},{\n\n0x00,0xFE,0x92,0xFE,0x24,0x28,0xE0,0x3F,0xE0,0x28,0x24,0x08,0x07,0x08,0x0F,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"胱\",5595*/},{\n\n0xFE,0x92,0xFE,0x00,0xFE,0x02,0xEA,0x2A,0xEA,0x02,0xFE,0x07,0x08,0x0F,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"胴\",5596*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xFE,0xA2,0x7A,0xA2,0x22,0xFE,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x04,0x04,0x04,0x05,0x0F,/*\"胭\",5597*/},{\n\n0xFE,0x92,0xFE,0x00,0xF4,0xB2,0xD5,0xF5,0xD5,0xB2,0xF4,0x07,0x08,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"膾\",5598*/},{\n\n0x00,0xFE,0x92,0xFE,0x40,0x51,0x4A,0xE4,0x4A,0x51,0x40,0x08,0x07,0x08,0x0F,0x02,\n0x01,0x08,0x0F,0x00,0x01,0x02,/*\"脎\",5599*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x24,0x34,0xAD,0x66,0x24,0x94,0x08,0x07,0x08,0x0F,0x00,\n0x09,0x09,0x04,0x02,0x05,0x08,/*\"胲\",5600*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x89,0xFA,0x88,0x88,0xFA,0x89,0x08,0x07,0x08,0x0F,0x00,\n0x08,0x07,0x00,0x00,0x0F,0x00,/*\"胼\",5601*/},{\n\n0x00,0xFE,0x92,0xFE,0x40,0x49,0x4A,0xF8,0x4A,0x49,0x40,0x08,0x07,0x08,0x0F,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"朕\",5602*/},{\n\n0x00,0xFE,0x92,0xFE,0x24,0x28,0xA0,0xFF,0xA0,0x28,0x24,0x08,0x07,0x08,0x0F,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"脒\",5603*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x92,0x4A,0x26,0xFA,0xA2,0x12,0x08,0x07,0x08,0x0F,0x00,\n0x04,0x0A,0x09,0x07,0x00,0x01,/*\"豚\",5604*/},{\n\n0xFF,0x49,0xFF,0x00,0xE0,0x3F,0xA5,0xBD,0xA1,0x3F,0xE0,0x07,0x08,0x0F,0x00,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"腡\",5605*/},{\n\n0x00,0xFE,0x92,0xFE,0x20,0x1C,0x20,0xFF,0x20,0x1C,0x20,0x08,0x07,0x08,0x0F,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"脞\",5606*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x2A,0x32,0x26,0xAA,0x71,0x2D,0x08,0x07,0x08,0x0F,0x00,\n0x01,0x01,0x09,0x0F,0x01,0x01,/*\"脬\",5607*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x4C,0xD4,0x55,0xD6,0x54,0x4C,0x08,0x07,0x08,0x0F,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"脘\",5608*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xFE,0x4A,0xCA,0xFA,0x8A,0x4E,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x02,0x09,0x0F,0x00,0x03,/*\"脲\",5609*/},{\n\n0x00,0xFF,0x49,0xFF,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"腈\",5610*/},{\n\n0xFA,0x4A,0x3E,0x4A,0xFA,0x10,0xEA,0xA6,0xF3,0xA6,0xEA,0x0F,0x05,0x05,0x05,0x0F,\n0x00,0x07,0x02,0x07,0x0A,0x0B,/*\"醃\",5611*/},{\n\n0x00,0xFE,0x92,0xFE,0x24,0x24,0xFF,0x00,0xFF,0x24,0x24,0x08,0x07,0x08,0x0F,0x01,\n0x01,0x0F,0x00,0x0F,0x01,0x01,/*\"腓\",5612*/},{\n\n0xFE,0x92,0xFE,0x00,0xFC,0x92,0x80,0xFF,0x80,0x92,0xFE,0x07,0x08,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"腴\",5613*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0x86,0x92,0x93,0x92,0x92,0x86,0x08,0x07,0x08,0x0F,0x04,\n0x02,0x08,0x0F,0x00,0x02,0x04,/*\"腙\",5614*/},{\n\n0x00,0xFE,0x92,0xFE,0x00,0xAC,0x24,0xE5,0x26,0x24,0x2C,0x08,0x07,0x08,0x0F,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"腚\",5615*/},{\n\n0xFE,0x92,0xFE,0x00,0x64,0xDC,0x88,0xAA,0xFF,0xAA,0xBE,0x07,0x08,0x0F,0x00,0x0A,\n0x07,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"腱\",5616*/},{\n\n0x00,0xFF,0x49,0xFF,0xA2,0x6A,0xBA,0xAF,0xAA,0x6A,0xA2,0x08,0x07,0x08,0x0F,0x02,\n0x0A,0x06,0x03,0x06,0x0A,0x02,/*\"腠\",5617*/},{\n\n0xFE,0x92,0xFE,0x00,0xFA,0x0A,0x5A,0xEF,0x5A,0x0A,0xFA,0x07,0x08,0x0F,0x00,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"腩\",5618*/},{\n\n0xFA,0x0A,0xFA,0xAE,0xFA,0x00,0xFE,0xAA,0xAA,0xFE,0x00,0x0F,0x04,0x07,0x04,0x07,\n0x08,0x06,0x01,0x07,0x08,0x0C,/*\"靦\",5619*/},{\n\n0xFF,0x49,0xFF,0x00,0x80,0xBF,0xA9,0xA7,0xA9,0xBF,0x80,0x07,0x08,0x0F,0x08,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"膃\",5620*/},{\n\n0xEE,0xA8,0x9F,0xAA,0xEF,0x45,0xD7,0x50,0x57,0x55,0x47,0x0F,0x0A,0x09,0x0A,0x0F,\n0x00,0x01,0x09,0x09,0x07,0x00,/*\"齶\",5621*/},{\n\n0xFE,0x92,0xFE,0x00,0xE8,0xA4,0xEA,0x09,0xCA,0x04,0xE8,0x07,0x08,0x0F,0x00,0x0F,\n0x02,0x0F,0x00,0x03,0x08,0x0F,/*\"腧\",5622*/},{\n\n0x00,0xFE,0x92,0xFE,0x20,0xAA,0x68,0x3F,0x68,0xAA,0x20,0x08,0x07,0x08,0x0F,0x09,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x09,/*\"塍\",5623*/},{\n\n0x00,0xFF,0x49,0xFF,0x50,0x35,0x1C,0xD7,0x14,0x35,0x50,0x08,0x07,0x08,0x0F,0x00,\n0x09,0x0B,0x05,0x05,0x0B,0x09,/*\"媵\",5624*/},{\n\n0xFF,0x49,0xFF,0x00,0xC1,0x5D,0xD5,0x55,0xD5,0x5D,0xC1,0x07,0x08,0x0F,0x00,0x0F,\n0x00,0x02,0x0F,0x02,0x08,0x0F,/*\"膈\",5625*/},{\n\n0x22,0x9E,0xAB,0xAA,0x9A,0x84,0xBB,0xAA,0x9A,0xA6,0x52,0x00,0x0F,0x02,0x02,0x02,\n0x02,0x02,0x02,0x0A,0x0F,0x00,/*\"膂\",5626*/},{\n\n0xFE,0x92,0xFE,0x00,0x56,0xEA,0xAA,0xBB,0xAA,0xEA,0x06,0x07,0x08,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"臏\",5627*/},{\n\n0x00,0xFE,0x92,0xFE,0xA0,0x6A,0x38,0xAF,0x28,0x6A,0xA0,0x08,0x07,0x08,0x0F,0x00,\n0x05,0x0A,0x0F,0x02,0x05,0x00,/*\"滕\",5628*/},{\n\n0xFE,0x92,0xFE,0x00,0x06,0xDA,0xB6,0x93,0x96,0xDA,0x06,0x07,0x08,0x0F,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"膣\",5629*/},{\n\n0x00,0xFE,0x92,0xFE,0x18,0x6A,0x2E,0xFB,0x2E,0x6A,0x18,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"膪\",5630*/},{\n\n0xFF,0x49,0xFF,0x02,0xEA,0xAF,0xEA,0x02,0xE4,0x3F,0xE4,0x07,0x08,0x0F,0x08,0x0A,\n0x04,0x06,0x0C,0x05,0x02,0x0D,/*\"臌\",5631*/},{\n\n0xFE,0x92,0xFE,0x00,0x9A,0xAF,0x6A,0xAA,0x2A,0xAF,0x5A,0x07,0x08,0x0F,0x00,0x0A,\n0x0A,0x05,0x0A,0x0F,0x02,0x04,/*\"朦\",5632*/},{\n\n0xFE,0x92,0xFE,0x00,0x70,0x57,0x75,0x85,0x75,0x57,0x70,0x07,0x08,0x0F,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"臊\",5633*/},{\n\n0x25,0xFE,0x25,0x00,0xFA,0x8A,0xBA,0xAB,0xBA,0x8A,0xFA,0x09,0x07,0x01,0x00,0x08,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x08,/*\"羶\",5634*/},{\n\n0xFE,0x92,0xFE,0x00,0xFE,0xAA,0xFE,0xAB,0xFA,0xAE,0xEA,0x07,0x08,0x0F,0x04,0x0B,\n0x06,0x0F,0x02,0x0F,0x06,0x0B,/*\"臁\",5635*/},{\n\n0xFE,0x92,0xFE,0x00,0x95,0x6E,0xC4,0x1F,0x44,0xEE,0x55,0x07,0x08,0x0F,0x02,0x09,\n0x06,0x01,0x03,0x02,0x0F,0x02,/*\"膦\",5636*/},{\n\n0xFE,0x49,0x80,0x1F,0xF2,0x49,0xFF,0x10,0x0F,0xC4,0x1C,0x09,0x05,0x01,0x01,0x01,\n0x05,0x09,0x09,0x06,0x01,0x0E,/*\"歟\",5637*/},{\n\n0x90,0xD5,0xBA,0xD2,0x95,0x90,0x10,0x0F,0xC4,0x14,0x0C,0x00,0x07,0x00,0x0F,0x04,\n0x07,0x08,0x06,0x01,0x06,0x08,/*\"欷\",5638*/},{\n\n0x10,0xDA,0x56,0xD3,0x16,0xFA,0x10,0x0F,0xC4,0x14,0x0C,0x00,0x07,0x02,0x03,0x08,\n0x0F,0x08,0x06,0x01,0x06,0x08,/*\"欹\",5639*/},{\n\n0xCA,0x2A,0xFE,0x09,0x49,0xC8,0x10,0x0F,0xC4,0x14,0x0C,0x0F,0x05,0x07,0x04,0x05,\n0x07,0x08,0x06,0x01,0x06,0x08,/*\"歃\",5640*/},{\n\n0x12,0xD6,0x5A,0x53,0x5A,0xD6,0x12,0x0F,0xC4,0x14,0x0C,0x00,0x0F,0x05,0x05,0x05,\n0x0F,0x08,0x06,0x01,0x06,0x08,/*\"歆\",5641*/},{\n\n0x04,0x72,0x55,0x55,0x72,0x04,0x10,0x0F,0xC4,0x14,0x0C,0x0B,0x05,0x0F,0x0A,0x05,\n0x0F,0x08,0x06,0x01,0x06,0x08,/*\"歙\",5642*/},{\n\n0xFE,0x52,0xF2,0x4A,0xFE,0x04,0xFB,0x2A,0x3A,0x42,0x7E,0x0F,0x05,0x07,0x0D,0x03,\n0x04,0x09,0x0A,0x0A,0x0A,0x0F,/*\"颮\",5643*/},{\n\n0x28,0xC9,0x0A,0xE8,0x00,0xFE,0x52,0xF2,0x4A,0xFE,0x00,0x04,0x04,0x02,0x02,0x08,\n0x07,0x05,0x07,0x0D,0x07,0x0C,/*\"颯\",5644*/},{\n\n0x00,0xFE,0x52,0xF2,0x4A,0xFE,0x00,0xFF,0x55,0xFF,0x00,0x08,0x07,0x05,0x07,0x0D,\n0x03,0x05,0x0B,0x09,0x0B,0x0D,/*\"颶\",5645*/},{\n\n0xFE,0x52,0xF2,0x4A,0xFE,0x00,0xBE,0xA9,0xFF,0xAA,0xBE,0x0F,0x05,0x07,0x0D,0x03,\n0x04,0x08,0x0D,0x0A,0x0A,0x0D,/*\"颼\",5646*/},{\n\n0x24,0x9C,0x47,0x8C,0x55,0x00,0xFE,0x52,0xF2,0x4A,0xFE,0x09,0x07,0x09,0x07,0x09,\n0x08,0x07,0x05,0x07,0x0D,0x03,/*\"飆\",5647*/},{\n\n0xFE,0x52,0xF2,0x4A,0xFE,0x00,0x51,0xE8,0x87,0xEA,0x51,0x0F,0x05,0x07,0x0D,0x03,\n0x04,0x0A,0x09,0x0A,0x09,0x0E,/*\"飈\",5648*/},{\n\n0x00,0x10,0x28,0xE7,0x21,0x21,0x21,0x21,0xA7,0x68,0x08,0x00,0x08,0x08,0x04,0x05,\n0x02,0x02,0x05,0x04,0x08,0x08,/*\"殳\",5649*/},{\n\n0x1A,0xAA,0xAA,0xAF,0xEA,0x1A,0x08,0xE7,0x21,0xEF,0x08,0x00,0x03,0x0A,0x0A,0x0E,\n0x00,0x08,0x05,0x02,0x05,0x08,/*\"彀\",5650*/},{\n\n0x5A,0xCA,0x4A,0xEF,0x4A,0xDA,0x48,0xE7,0x21,0xEF,0x08,0x04,0x07,0x05,0x0F,0x05,\n0x07,0x0C,0x05,0x02,0x05,0x08,/*\"轂\",5651*/},{\n\n0x5A,0xAA,0xBA,0xAF,0xEA,0x9A,0x08,0xE7,0x21,0xEF,0x08,0x08,0x07,0x02,0x07,0x0A,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"觳\",5652*/},{\n\n0x22,0x2A,0x2A,0x2A,0x7F,0x80,0x7F,0x2A,0x2A,0x2A,0x22,0x09,0x09,0x0B,0x05,0x05,\n0x05,0x05,0x05,0x0B,0x09,0x09,/*\"斐\",5653*/},{\n\n0x2A,0xDA,0x2A,0xBA,0xC6,0x3B,0xC6,0xBA,0x2A,0xD6,0x22,0x08,0x07,0x00,0x0A,0x0F,\n0x08,0x0F,0x0A,0x00,0x0F,0x00,/*\"齏\",5654*/},{\n\n0xC9,0x0A,0xF8,0x08,0xFF,0xD5,0x57,0xF8,0x57,0xD5,0xFF,0x0C,0x03,0x0C,0x00,0x0F,\n0x0A,0x06,0x0F,0x06,0x0A,0x0F,/*\"斕\",5655*/},{\n\n0x04,0xFC,0x25,0x26,0xE4,0x10,0x4C,0x43,0x8C,0x10,0x20,0x08,0x07,0x08,0x08,0x07,\n0x00,0x02,0x02,0x04,0x08,0x00,/*\"於\",5656*/},{\n\n0x04,0xFD,0x26,0xE4,0x14,0xD3,0x52,0xFE,0x52,0x52,0xD2,0x08,0x07,0x08,0x0F,0x00,\n0x07,0x00,0x0F,0x00,0x04,0x07,/*\"旆\",5657*/},{\n\n0x04,0xFD,0x26,0xE4,0x04,0x53,0x52,0xF2,0xAA,0xAA,0x82,0x08,0x07,0x08,0x0F,0x00,\n0x01,0x01,0x07,0x08,0x08,0x0E,/*\"旄\",5658*/},{\n\n0x04,0xFD,0x26,0xE4,0x04,0x83,0xFA,0xAA,0xCA,0xFA,0x82,0x08,0x07,0x08,0x0F,0x00,\n0x08,0x07,0x00,0x08,0x0F,0x00,/*\"旃\",5659*/},{\n\n0x04,0xFD,0x26,0xE4,0x04,0x43,0x32,0x22,0xFA,0x22,0x22,0x08,0x07,0x08,0x0F,0x00,\n0x08,0x09,0x09,0x0F,0x09,0x09,/*\"旌\",5660*/},{\n\n0x04,0xFD,0x26,0xE4,0x04,0xFB,0x2A,0xEA,0x2A,0xBA,0x02,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x00,0x07,0x09,0x08,0x0E,/*\"旎\",5661*/},{\n\n0x04,0xFD,0x26,0xE4,0x04,0x6B,0x5A,0x4E,0x4A,0x6A,0x02,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x00,0x0F,0x00,0x0F,0x08,/*\"旒\",5662*/},{\n\n0x04,0xFD,0x26,0xE4,0x44,0x6B,0x5A,0x4E,0x5A,0xEA,0x42,0x08,0x07,0x08,0x0F,0x00,\n0x07,0x05,0x07,0x08,0x0F,0x00,/*\"旖\",5663*/},{\n\n0x78,0x00,0xFF,0x08,0x44,0xDF,0x55,0x55,0x55,0x5F,0x40,0x08,0x06,0x01,0x06,0x0A,\n0x05,0x0B,0x05,0x0B,0x09,0x07,/*\"煬\",5664*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0x8A,0xBA,0xAF,0xEA,0xBE,0x88,0x08,0x06,0x01,0x06,0x00,\n0x06,0x04,0x04,0x0F,0x04,0x04,/*\"煒\",5665*/},{\n\n0x78,0x00,0xFF,0x04,0xBA,0xAB,0xBA,0x10,0xEF,0x08,0xF8,0x08,0x06,0x01,0x06,0x0A,\n0x0E,0x03,0x0A,0x05,0x02,0x0D,/*\"燉\",5666*/},{\n\n0x78,0x00,0xFF,0x04,0x08,0xFC,0xAA,0xAD,0xAA,0xFC,0x08,0x08,0x06,0x01,0x06,0x03,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"熗\",5667*/},{\n\n0x78,0x00,0xFF,0x08,0x84,0x42,0xF2,0x2E,0x22,0x22,0xE2,0x08,0x06,0x01,0x02,0x04,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"炻\",5668*/},{\n\n0x78,0x00,0xFF,0x10,0x4A,0x52,0x42,0xFE,0x41,0x51,0x49,0x08,0x06,0x01,0x02,0x04,\n0x00,0x08,0x0F,0x00,0x00,0x00,/*\"烀\",5669*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0x88,0x89,0xFA,0x88,0x88,0x08,0x08,0x06,0x01,0x06,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"炷\",5670*/},{\n\n0x78,0x00,0xFF,0x08,0x44,0x64,0x55,0xCE,0x44,0x24,0x04,0x08,0x06,0x01,0x02,0x04,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"炫\",5671*/},{\n\n0x04,0x76,0x55,0x54,0x54,0x54,0x54,0x54,0x54,0x76,0x0C,0x08,0x0A,0x09,0x04,0x04,\n0x03,0x04,0x04,0x0A,0x09,0x08,/*\"炱\",5672*/},{\n\n0x78,0x00,0xFF,0x04,0xAA,0xFA,0xAF,0xFA,0xAF,0xFA,0xAA,0x08,0x06,0x01,0x06,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"燁\",5673*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0x25,0x26,0xFC,0x26,0x25,0x00,0x08,0x06,0x01,0x02,0x05,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"烊\",5674*/},{\n\n0x78,0x00,0xFF,0x08,0x25,0xA5,0xBD,0xA7,0xA5,0xBD,0x21,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"焐\",5675*/},{\n\n0x78,0x00,0xFF,0x08,0x14,0x28,0x24,0xB3,0x64,0x08,0x10,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"焓\",5676*/},{\n\n0x78,0x00,0xFF,0x08,0xFF,0x15,0x9F,0x20,0x5F,0x15,0xFF,0x08,0x06,0x01,0x02,0x0F,\n0x01,0x03,0x04,0x06,0x09,0x0F,/*\"燜\",5677*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0xF8,0xA8,0xAF,0xAA,0xFA,0x02,0x08,0x06,0x01,0x02,0x04,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"焯\",5678*/},{\n\n0xA0,0x24,0xD2,0x10,0x88,0x07,0x88,0x10,0xD4,0x22,0xA0,0x09,0x04,0x03,0x05,0x08,\n0x00,0x09,0x04,0x03,0x05,0x08,/*\"焱\",5679*/},{\n\n0x78,0x00,0xFF,0x08,0xE4,0x3F,0xE4,0x00,0xFF,0x89,0xFF,0x08,0x06,0x01,0x02,0x07,\n0x02,0x0B,0x04,0x03,0x08,0x0F,/*\"煳\",5680*/},{\n\n0x78,0x00,0xFF,0x08,0x04,0x9F,0x95,0xB5,0xD5,0x95,0x9F,0x08,0x06,0x01,0x06,0x08,\n0x0A,0x0C,0x08,0x08,0x0C,0x0A,/*\"煜\",5681*/},{\n\n0x78,0x00,0xFF,0x08,0x44,0xDF,0x55,0xDF,0x55,0x5F,0x40,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"煨\",5682*/},{\n\n0x78,0x00,0xFF,0x08,0xFE,0x25,0x08,0xE7,0x21,0xEF,0x08,0x08,0x06,0x01,0x02,0x0F,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"煅\",5683*/},{\n\n0x08,0x04,0x7E,0x01,0x50,0x37,0x15,0x7D,0x15,0x37,0x50,0x08,0x0A,0x09,0x04,0x04,\n0x03,0x04,0x04,0x0A,0x09,0x08,/*\"煲\",5684*/},{\n\n0x78,0x00,0xFF,0x08,0x06,0xEA,0xAA,0xAB,0xAA,0xEA,0x06,0x08,0x06,0x01,0x06,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"煊\",5685*/},{\n\n0x78,0x00,0xFF,0x48,0xFE,0x2A,0xEA,0x2B,0xEA,0x2A,0xEE,0x08,0x06,0x01,0x02,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"煸\",5686*/},{\n\n0x78,0x00,0xFF,0x04,0x22,0xEC,0x00,0xFF,0x35,0xD5,0x5F,0x08,0x06,0x01,0x06,0x08,\n0x07,0x04,0x0B,0x09,0x08,0x0B,/*\"煺\",5687*/},{\n\n0x78,0x00,0xFF,0x08,0xDE,0x52,0x69,0xD2,0x4E,0x52,0xDE,0x08,0x06,0x01,0x02,0x0F,\n0x05,0x05,0x07,0x05,0x05,0x0F,/*\"熘\",5688*/},{\n\n0x78,0x00,0xFF,0x08,0x74,0x5F,0x75,0x55,0x75,0x5F,0x70,0x08,0x06,0x01,0x06,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"熳\",5689*/},{\n\n0x78,0x00,0xFF,0x10,0xFA,0x56,0xBA,0x93,0xBA,0x56,0xF2,0x08,0x06,0x01,0x02,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"熵\",5690*/},{\n\n0xA0,0x5F,0x95,0xF5,0x15,0x57,0x80,0x0A,0x92,0xFF,0x02,0x08,0x08,0x0A,0x04,0x04,\n0x02,0x04,0x04,0x0A,0x08,0x08,/*\"熨\",5691*/},{\n\n0x78,0x00,0xFF,0x08,0xD5,0x49,0x5F,0x60,0x55,0x49,0xDF,0x08,0x06,0x01,0x02,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"熠\",5692*/},{\n\n0x78,0x00,0xFF,0x08,0xFE,0x5A,0x13,0x7E,0x12,0x5A,0xFE,0x08,0x06,0x01,0x06,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"燠\",5693*/},{\n\n0x78,0x00,0xFF,0x04,0x52,0xB6,0x9A,0xBE,0x99,0xB5,0x50,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x0A,0x0F,0x0A,0x0F,0x00,/*\"燔\",5694*/},{\n\n0x78,0x00,0xFF,0x04,0x11,0xF2,0xA5,0x56,0xAC,0xF6,0xA5,0x08,0x06,0x01,0x06,0x08,\n0x07,0x0A,0x09,0x0A,0x0B,0x08,/*\"燧\",5695*/},{\n\n0x55,0x2B,0x55,0x79,0x14,0x25,0x2B,0x55,0x79,0x29,0x45,0x08,0x0A,0x09,0x04,0x04,\n0x03,0x04,0x04,0x0A,0x09,0x08,/*\"燹\",5696*/},{\n\n0x78,0x00,0xFF,0x10,0xBA,0xAE,0xBA,0x2E,0xB9,0xED,0xB9,0x08,0x06,0x01,0x02,0x0F,\n0x0A,0x07,0x08,0x0A,0x0F,0x00,/*\"爝\",5697*/},{\n\n0x30,0x5F,0xD5,0xF0,0x5F,0x95,0x5F,0xF0,0xD5,0x5F,0x30,0x0A,0x0B,0x0A,0x07,0x02,\n0x03,0x02,0x07,0x0A,0x0B,0x0A,/*\"爨\",5698*/},{\n\n0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x04,0x00,0x04,0x08,\n0x00,0x04,0x08,0x00,0x04,0x08,/*\"灬\",5699*/},{\n\n0x88,0xAA,0xAA,0xAA,0x2A,0xBF,0xAA,0xAA,0xEA,0xAA,0x98,0x03,0x0A,0x02,0x03,0x08,\n0x00,0x09,0x02,0x03,0x08,0x00,/*\"燾\",5700*/},{\n\n0x00,0xFE,0x12,0xFE,0x08,0xF4,0x97,0xF4,0x04,0xFC,0x00,0x08,0x05,0x01,0x05,0x08,\n0x00,0x04,0x0A,0x02,0x05,0x08,/*\"煦\",5701*/},{\n\n0x82,0x8A,0xBA,0xEA,0xAA,0xAF,0xAA,0xEA,0xBA,0x8A,0x82,0x08,0x07,0x02,0x06,0x0A,\n0x02,0x06,0x0A,0x02,0x07,0x08,/*\"熹\",5702*/},{\n\n0x00,0xFE,0x0A,0x8A,0x8A,0x8A,0xEB,0x8A,0xAA,0xCA,0x8E,0x08,0x07,0x08,0x08,0x04,\n0x02,0x01,0x02,0x04,0x08,0x08,/*\"戾\",5703*/},{\n\n0x00,0xFE,0x0A,0x8A,0x0A,0x2A,0x4B,0x0A,0xEA,0x0A,0x0E,0x08,0x07,0x02,0x02,0x03,\n0x02,0x02,0x02,0x0F,0x01,0x01,/*\"戽\",5704*/},{\n\n0x00,0xFE,0x0A,0xEA,0x2A,0xAA,0xAB,0xAA,0xAA,0x2A,0xEE,0x08,0x07,0x00,0x0F,0x00,\n0x03,0x02,0x02,0x03,0x08,0x0F,/*\"扃\",5705*/},{\n\n0x00,0xFE,0x0A,0x8A,0xEA,0xAA,0xAB,0xAA,0xEA,0x8A,0x0E,0x08,0x07,0x00,0x07,0x0A,\n0x0A,0x0B,0x0A,0x0A,0x0B,0x0C,/*\"扈\",5706*/},{\n\n0x00,0xFE,0x2A,0xAA,0xAA,0xFA,0x0B,0xFA,0xAA,0xAA,0x2E,0x08,0x07,0x02,0x02,0x02,\n0x0F,0x00,0x0F,0x02,0x02,0x02,/*\"扉\",5707*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"礻\",5708*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0xFE,0x42,0x42,0x42,0x7E,0x00,0x00,0x00,0x0F,0x00,0x00,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"祀\",5709*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0x22,0x22,0xFE,0x22,0x22,0x20,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"祆\",5710*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0xF8,0x00,0x00,0xFF,0x10,0x10,0x00,0x00,0x0F,0x00,0x08,\n0x0F,0x08,0x08,0x0F,0x08,0x08,/*\"祉\",5711*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0x48,0x48,0xFF,0x48,0x48,0x40,0x00,0x00,0x0F,0x00,0x04,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"祛\",5712*/},{\n\n0x84,0x45,0xF6,0x2C,0x48,0xC8,0x48,0x7F,0x48,0xC8,0x08,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"祜\",5713*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0xC8,0x3F,0xE8,0x29,0xEA,0x08,0x00,0x00,0x0F,0x00,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"祓\",5714*/},{\n\n0x84,0x45,0xF6,0x2C,0x48,0x07,0xFC,0x24,0x24,0x24,0x04,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"祚\",5715*/},{\n\n0x45,0xF6,0x2C,0x40,0xFD,0xAB,0x49,0xFF,0x49,0xAB,0xFD,0x00,0x0F,0x00,0x00,0x0F,\n0x02,0x01,0x0F,0x01,0x0A,0x0F,/*\"禰\",5716*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0xFE,0x22,0x22,0xFE,0x21,0x21,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x08,0x03,0x04,0x0E,/*\"祗\",5717*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0xEA,0x2A,0x2A,0xEA,0x02,0xFE,0x00,0x00,0x0F,0x00,0x00,\n0x03,0x01,0x01,0x09,0x08,0x07,/*\"祠\",5718*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0xF8,0xA8,0xAF,0xAA,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"禎\",5719*/},{\n\n0x84,0x45,0xF6,0x4C,0x84,0x48,0xFF,0x00,0xFF,0x48,0x84,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"祧\",5720*/},{\n\n0x84,0x45,0xF6,0x2C,0x40,0x04,0xFF,0x54,0x54,0xFF,0x04,0x00,0x00,0x0F,0x00,0x00,\n0x09,0x05,0x01,0x01,0x05,0x09,/*\"祺\",5721*/},{\n\n0x45,0xF6,0x2C,0x40,0xF7,0x55,0x57,0xF0,0x57,0x55,0xF7,0x00,0x0F,0x00,0x00,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"禪\",5722*/},{\n\n0x45,0xF6,0x2C,0x40,0x2A,0x7F,0x2A,0xC2,0x3E,0x42,0x7E,0x00,0x0F,0x00,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"禊\",5723*/},{\n\n0x45,0xF6,0x2C,0x40,0x04,0x25,0x26,0xFC,0x26,0x25,0x04,0x00,0x0F,0x00,0x00,0x0D,\n0x01,0x0D,0x01,0x0D,0x01,0x0D,/*\"禚\",5724*/},{\n\n0x84,0x45,0xF6,0x2C,0x42,0xEA,0xAA,0xAF,0xAA,0xEA,0x02,0x00,0x00,0x0F,0x00,0x02,\n0x0E,0x0B,0x0A,0x0B,0x0E,0x02,/*\"禧\",5725*/},{\n\n0x45,0xF6,0x2C,0x40,0xBA,0xAA,0xFA,0x83,0xFA,0xAA,0xBA,0x00,0x0F,0x00,0x00,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"禳\",5726*/},{\n\n0x02,0x02,0x02,0x02,0x7E,0x82,0x0A,0x12,0x22,0x02,0x02,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"忑\",5727*/},{\n\n0x20,0x20,0x20,0x20,0x3F,0xA4,0x24,0x24,0x24,0x24,0x20,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"忐\",5728*/},{\n\n0x05,0x56,0x5F,0xF4,0x5F,0x56,0x01,0x14,0x24,0xFF,0x04,0x09,0x05,0x01,0x05,0x0B,\n0x0D,0x09,0x0C,0x01,0x05,0x08,/*\"懟\",5729*/},{\n\n0x22,0x2A,0x7F,0x2A,0x22,0x40,0x22,0x1E,0x42,0x42,0x3E,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"恝\",5730*/},{\n\n0x88,0xAA,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xAA,0x88,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"恚\",5731*/},{\n\n0x01,0xFD,0x05,0x05,0x7D,0x07,0x7D,0x05,0x85,0xFD,0x01,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"恧\",5732*/},{\n\n0x08,0x04,0xFE,0x01,0x08,0x4A,0x4A,0x7E,0x49,0x49,0x08,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"恁\",5733*/},{\n\n0x40,0x54,0x55,0x56,0x54,0xFC,0x54,0x56,0x55,0x54,0x40,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"恙\",5734*/},{\n\n0x42,0x24,0x00,0x44,0x23,0x92,0x0E,0x12,0x22,0x4A,0x46,0x04,0x03,0x00,0x07,0x08,\n0x08,0x0B,0x08,0x0C,0x01,0x06,/*\"恣\",5735*/},{\n\n0x62,0xAA,0xAF,0xAA,0x62,0x98,0xB6,0x52,0x52,0xB6,0x84,0x08,0x06,0x00,0x06,0x08,\n0x0A,0x0C,0x08,0x0C,0x02,0x0C,/*\"愨\",5736*/},{\n\n0x24,0x12,0xF9,0x04,0x89,0x52,0x00,0x89,0x89,0xF9,0x09,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"愆\",5737*/},{\n\n0xFF,0x95,0x15,0x7D,0x97,0x50,0x84,0x5B,0x22,0x5E,0x82,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x01,0x06,/*\"愍\",5738*/},{\n\n0x00,0xFF,0x55,0x35,0x77,0x5D,0x55,0x55,0x77,0x15,0x01,0x08,0x05,0x01,0x05,0x0B,\n0x0D,0x09,0x0D,0x01,0x05,0x09,/*\"慝\",5739*/},{\n\n0x08,0xEA,0xAA,0xBE,0xA9,0xE9,0x00,0xFE,0xAB,0xAA,0xFE,0x08,0x06,0x00,0x06,0x08,\n0x0A,0x0C,0x08,0x0C,0x02,0x0C,/*\"憩\",5740*/},{\n\n0x22,0xAE,0xEA,0x3B,0x2E,0x22,0x84,0x5B,0x22,0x5E,0x82,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"憝\",5741*/},{\n\n0x24,0xFF,0x14,0x49,0xAB,0xFD,0x0B,0x18,0x24,0xFF,0x14,0x08,0x06,0x00,0x06,0x08,\n0x09,0x0A,0x08,0x0C,0x02,0x0C,/*\"懋\",5742*/},{\n\n0x88,0x52,0xE4,0xA2,0x6F,0xAA,0xFA,0xAA,0x6F,0xA2,0xE2,0x08,0x06,0x00,0x06,0x08,\n0x0A,0x0C,0x08,0x0C,0x02,0x0C,/*\"懣\",5743*/},{\n\n0x8A,0xBE,0xEB,0xBE,0x9A,0xF4,0xAB,0xEA,0xAA,0xF6,0x10,0x08,0x04,0x01,0x04,0x08,\n0x0E,0x09,0x0C,0x01,0x06,0x08,/*\"戇\",5744*/},{\n\n0x08,0x08,0x2A,0x2A,0x2A,0xFF,0x2A,0x2A,0x3E,0x08,0x08,0x00,0x00,0x00,0x00,0x00,\n0x0F,0x00,0x00,0x00,0x00,0x00,/*\"肀\",5745*/},{\n\n0x08,0x88,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xBE,0x88,0x08,0x02,0x02,0x02,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"聿\",5746*/},{\n\n0x12,0xD2,0x4A,0x46,0x50,0x5F,0x42,0x44,0x4A,0xD1,0x10,0x00,0x0F,0x05,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"沓\",5747*/},{\n\n0xC0,0x7E,0x55,0x40,0x55,0x4A,0x55,0x40,0x55,0x7F,0xC0,0x08,0x0A,0x06,0x02,0x08,\n0x0F,0x00,0x02,0x04,0x0A,0x08,/*\"澩\",5748*/},{\n\n0x92,0x92,0x0A,0xE6,0x10,0x9F,0x82,0xE4,0x8A,0x11,0x90,0x04,0x03,0x08,0x0F,0x01,\n0x02,0x09,0x0F,0x00,0x03,0x04,/*\"淼\",5749*/},{\n\n0xF2,0x2E,0xE2,0xB4,0xEB,0xB4,0x80,0xFF,0xB4,0xEB,0xB4,0x07,0x02,0x07,0x08,0x07,\n0x02,0x08,0x05,0x02,0x05,0x0E,/*\"磯\",5750*/},{\n\n0x42,0xF2,0x2E,0xE2,0x40,0x42,0x42,0xFE,0x42,0x42,0x40,0x00,0x07,0x02,0x07,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"矸\",5751*/},{\n\n0x42,0xF2,0x2E,0xE2,0x40,0xDF,0x55,0x55,0x55,0x5F,0x40,0x00,0x07,0x02,0x07,0x0A,\n0x05,0x0B,0x05,0x0B,0x09,0x07,/*\"碭\",5752*/},{\n\n0xA2,0xAA,0xAA,0xAA,0xAA,0xFF,0xAA,0xAA,0xAA,0xAA,0xA2,0x08,0x04,0x0E,0x0B,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"砉\",5753*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0x00,0x07,0x02,0x07,0x00,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"硨\",5754*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xF4,0x84,0xFF,0x84,0xF4,0x04,0x00,0x0F,0x04,0x0F,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"砘\",5755*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x32,0x2A,0xA2,0x62,0xFE,0x22,0x00,0x07,0x02,0x03,0x04,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"砑\",5756*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFE,0x12,0x12,0xF1,0x11,0x10,0x00,0x07,0x02,0x03,0x08,\n0x07,0x00,0x00,0x0F,0x00,0x00,/*\"斫\",5757*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x22,0x22,0x2A,0xB1,0x61,0x21,0x00,0x07,0x02,0x07,0x08,\n0x04,0x02,0x05,0x08,0x08,0x08,/*\"砭\",5758*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFE,0x52,0xF2,0x4A,0xFE,0x00,0x00,0x07,0x02,0x07,0x08,\n0x07,0x05,0x07,0x0D,0x07,0x0C,/*\"碸\",5759*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x48,0x48,0xFF,0x48,0x48,0x40,0x00,0x07,0x02,0x07,0x00,\n0x06,0x05,0x04,0x04,0x06,0x0C,/*\"砝\",5760*/},{\n\n0x42,0xF2,0x2E,0xE2,0x04,0x6F,0x84,0x04,0x84,0x6F,0x04,0x00,0x07,0x02,0x03,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"砹\",5761*/},{\n\n0xF2,0x2E,0xE2,0x00,0xFF,0x01,0xF5,0x5F,0xF5,0x5F,0xF5,0x07,0x02,0x03,0x04,0x03,\n0x0F,0x01,0x05,0x07,0x09,0x0F,/*\"礪\",5762*/},{\n\n0x88,0xFA,0xAE,0xAB,0xAE,0xFA,0x88,0xEF,0xAA,0xBA,0xC0,0x08,0x04,0x0E,0x0B,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"礱\",5763*/},{\n\n0x42,0xF2,0x2E,0xE2,0x08,0x07,0xFC,0x24,0x24,0x24,0x04,0x00,0x07,0x02,0x07,0x00,\n0x00,0x0F,0x01,0x01,0x01,0x01,/*\"砟\",5764*/},{\n\n0x42,0xF2,0x2E,0xE2,0x10,0x48,0x44,0xC3,0x44,0x48,0x10,0x00,0x07,0x02,0x07,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"砼\",5765*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFE,0x22,0x22,0xFE,0x21,0x21,0x00,0x07,0x02,0x07,0x00,\n0x0F,0x04,0x08,0x03,0x04,0x0E,/*\"砥\",5766*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x28,0xC8,0x09,0x0A,0xE8,0x08,0x00,0x07,0x02,0x07,0x08,\n0x08,0x09,0x0C,0x0B,0x08,0x08,/*\"砬\",5767*/},{\n\n0x42,0xF2,0x2E,0xE2,0x0C,0xE4,0x05,0x86,0x44,0x24,0x0C,0x00,0x07,0x02,0x07,0x00,\n0x07,0x09,0x08,0x08,0x08,0x0E,/*\"砣\",5768*/},{\n\n0x42,0xF2,0x2E,0xE2,0xF0,0x92,0xFF,0x92,0xFF,0x92,0x9E,0x00,0x07,0x02,0x03,0x08,\n0x04,0x03,0x00,0x0F,0x04,0x07,/*\"砩\",5769*/},{\n\n0xF2,0x2E,0xE2,0x22,0xFE,0x22,0xFE,0x22,0xFC,0x00,0xFF,0x07,0x02,0x07,0x08,0x07,\n0x00,0x0F,0x00,0x01,0x08,0x0F,/*\"硎\",5770*/},{\n\n0x42,0xF2,0x2E,0xE2,0x44,0xCF,0x44,0x54,0x64,0x4F,0x44,0x00,0x07,0x02,0x07,0x00,\n0x0F,0x08,0x08,0x08,0x08,0x00,/*\"硭\",5771*/},{\n\n0x42,0xF2,0x2E,0xE2,0x84,0x74,0x84,0xFF,0x84,0x74,0x84,0x00,0x07,0x02,0x07,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"硤\",5772*/},{\n\n0x42,0xF2,0x2E,0xE2,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x00,0x07,0x02,0x07,0x08,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"磽\",5773*/},{\n\n0x50,0x5E,0x50,0xCF,0x4A,0x4A,0x40,0x4F,0x54,0x52,0x59,0x04,0x02,0x0F,0x05,0x05,\n0x05,0x05,0x05,0x05,0x0F,0x00,/*\"砦\",5774*/},{\n\n0xF2,0x2E,0xE2,0x00,0xFE,0x02,0xEA,0x2A,0xEA,0x02,0xFE,0x07,0x02,0x07,0x00,0x0F,\n0x00,0x01,0x01,0x01,0x08,0x0F,/*\"硐\",5775*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0xFC,0x14,0xE6,0x15,0x04,0xFC,0x00,0x07,0x02,0x07,0x00,\n0x0F,0x05,0x04,0x05,0x04,0x0F,/*\"硇\",5776*/},{\n\n0x42,0xF2,0x2E,0xE2,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x00,0x07,0x02,0x07,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"硌\",5777*/},{\n\n0x42,0xF2,0x2E,0xE2,0x90,0x92,0xFE,0x51,0xFF,0x92,0x54,0x00,0x07,0x02,0x07,0x00,\n0x08,0x0F,0x02,0x03,0x04,0x0E,/*\"硪\",5778*/},{\n\n0xF2,0x2E,0xE2,0x00,0x22,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x07,0x02,0x07,0x00,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"磧\",5779*/},{\n\n0x42,0xF2,0x2E,0xE2,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x00,0x07,0x02,0x07,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"碓\",5780*/},{\n\n0x42,0xF2,0x2E,0xE2,0x20,0xAA,0xB2,0xA3,0xB2,0xAA,0x20,0x00,0x07,0x02,0x07,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"碚\",5781*/},{\n\n0x42,0xF2,0x2E,0xE2,0x2C,0xA4,0x24,0xE5,0x26,0x24,0x2C,0x00,0x07,0x02,0x0B,0x04,\n0x03,0x04,0x0F,0x09,0x09,0x08,/*\"碇\",5782*/},{\n\n0x42,0xF2,0x2E,0xE2,0x58,0x56,0xBB,0x22,0x5B,0x56,0x58,0x00,0x07,0x02,0x03,0x05,\n0x05,0x0A,0x0A,0x05,0x04,0x02,/*\"磣\",5783*/},{\n\n0x22,0xFA,0x16,0xF2,0xA0,0xEA,0xAA,0xFF,0xAA,0xEA,0xA2,0x00,0x07,0x02,0x07,0x00,\n0x03,0x02,0x0B,0x0A,0x07,0x02,/*\"碡\",5784*/},{\n\n0x42,0xF2,0x2E,0xE2,0x80,0x5F,0x75,0xD5,0x55,0x5F,0xC0,0x00,0x07,0x02,0x07,0x00,\n0x06,0x05,0x04,0x09,0x08,0x07,/*\"碣\",5785*/},{\n\n0xF2,0x2E,0xE2,0x00,0xB2,0x96,0x9A,0xD3,0x9A,0x96,0xB2,0x07,0x02,0x07,0x00,0x07,\n0x00,0x00,0x0F,0x00,0x04,0x07,/*\"碲\",5786*/},{\n\n0x42,0xF2,0x2E,0xE2,0x06,0xEA,0xAA,0xAB,0xAA,0xEA,0x06,0x00,0x07,0x02,0x03,0x08,\n0x0B,0x0A,0x0A,0x0A,0x0B,0x08,/*\"碹\",5787*/},{\n\n0x42,0xF2,0x2E,0xE2,0xC0,0x3E,0xEA,0x2B,0xEA,0x2A,0xEE,0x00,0x07,0x02,0x03,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"碥\",5788*/},{\n\n0x42,0xF2,0x2E,0xE2,0xA4,0x9B,0x86,0xD8,0x92,0xBF,0x92,0x00,0x07,0x02,0x03,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"磔\",5789*/},{\n\n0x42,0xF2,0x2E,0xE2,0x00,0x4A,0x66,0xD3,0x42,0x66,0x4A,0x00,0x07,0x02,0x07,0x04,\n0x02,0x0F,0x04,0x01,0x06,0x09,/*\"磙\",5790*/},{\n\n0x42,0xF2,0x2E,0xE2,0xB0,0x5B,0xB5,0x05,0xB5,0x5B,0xB0,0x00,0x07,0x02,0x03,0x0A,\n0x06,0x02,0x0F,0x02,0x06,0x0A,/*\"磉\",5791*/},{\n\n0x82,0xFA,0xAA,0xBF,0xAA,0xBA,0x84,0xDB,0xA9,0xDB,0x82,0x08,0x04,0x0E,0x0B,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"磬\",5792*/},{\n\n0xF2,0x2E,0xE2,0x04,0x49,0x22,0x00,0xFF,0x55,0x55,0x5D,0x07,0x02,0x07,0x00,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"磲\",5793*/},{\n\n0xF2,0x2E,0xE2,0x00,0xBA,0xAB,0xBA,0x10,0xEF,0x08,0xF8,0x07,0x02,0x07,0x00,0x0A,\n0x0E,0x03,0x0A,0x05,0x02,0x0D,/*\"礅\",5794*/},{\n\n0x42,0xF2,0x2E,0xE2,0x25,0xD9,0x57,0x50,0x57,0xDA,0x25,0x00,0x07,0x02,0x07,0x08,\n0x0B,0x0D,0x09,0x0D,0x0B,0x08,/*\"磴\",5795*/},{\n\n0x42,0xF2,0x2E,0xE2,0x82,0xBE,0xAA,0xBE,0xAA,0xBE,0x82,0x00,0x07,0x02,0x07,0x08,\n0x0F,0x0A,0x0F,0x0A,0x0F,0x08,/*\"礓\",5796*/},{\n\n0xF2,0x2E,0xE2,0xA0,0x52,0x2F,0x5A,0x42,0x5A,0x2F,0x5A,0x07,0x02,0x07,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"礤\",5797*/},{\n\n0xF2,0x2E,0xE2,0x00,0x9A,0xAF,0x6A,0xAA,0x2A,0xAF,0x5A,0x07,0x02,0x07,0x00,0x0A,\n0x0A,0x05,0x0A,0x0F,0x02,0x04,/*\"礞\",5798*/},{\n\n0x42,0xF2,0x2E,0xE2,0x48,0x92,0xF7,0x52,0xFA,0x57,0xFA,0x00,0x07,0x02,0x03,0x04,\n0x02,0x06,0x02,0x0A,0x0F,0x02,/*\"礴\",5799*/},{\n\n0x04,0x44,0xDE,0x76,0xD5,0x55,0x15,0xF6,0xBE,0xA4,0x04,0x01,0x0F,0x05,0x05,0x05,\n0x0F,0x01,0x06,0x0A,0x0B,0x0C,/*\"龕\",5800*/},{\n\n0x08,0xCA,0x5C,0x68,0x4F,0xF8,0x4F,0x68,0x5C,0xCA,0x08,0x00,0x0F,0x00,0x02,0x01,\n0x0F,0x01,0x02,0x08,0x0F,0x00,/*\"黹\",5801*/},{\n\n0xAA,0x8F,0xF8,0x8F,0xAA,0x00,0xC8,0x3F,0xE8,0x29,0xEA,0x0F,0x04,0x0F,0x02,0x0F,\n0x04,0x03,0x08,0x05,0x02,0x0D,/*\"黻\",5802*/},{\n\n0xAA,0x8F,0xF8,0x8F,0xAA,0x00,0xF4,0x54,0xFF,0x54,0xF5,0x0F,0x04,0x0F,0x02,0x0F,\n0x00,0x0F,0x01,0x07,0x09,0x0F,/*\"黼\",5803*/},{\n\n0xFE,0x92,0x92,0xFE,0x20,0x22,0x22,0xFE,0x22,0x22,0x20,0x0F,0x04,0x04,0x0F,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"盱\",5804*/},{\n\n0xFE,0x92,0x92,0xFE,0x00,0xF2,0x82,0xFE,0x92,0x92,0xF2,0x0F,0x04,0x04,0x0F,0x00,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"眄\",5805*/},{\n\n0xFE,0x92,0xFE,0x00,0xFE,0x82,0xBA,0x2A,0xAA,0xBA,0x82,0x0F,0x04,0x0F,0x00,0x0F,\n0x0A,0x0B,0x08,0x0B,0x0A,0x0B,/*\"瞘\",5806*/},{\n\n0xFE,0x92,0x92,0xFE,0x00,0xF4,0x84,0xFF,0x84,0x84,0xF4,0x0F,0x04,0x04,0x0F,0x00,\n0x00,0x00,0x07,0x08,0x08,0x0E,/*\"盹\",5807*/},{\n\n0xFE,0x92,0x92,0xFE,0x40,0x38,0x00,0xFF,0x00,0x04,0xB8,0x0F,0x04,0x04,0x07,0x08,\n0x08,0x04,0x04,0x02,0x01,0x00,/*\"眇\",5808*/},{\n\n0xFE,0x92,0xFE,0x00,0x1C,0x04,0xC4,0x3F,0xC4,0x04,0x1C,0x0F,0x04,0x0F,0x00,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0C,/*\"眈\",5809*/},{\n\n0x24,0x2B,0xEA,0xAA,0xAA,0xBF,0xAA,0xAA,0xEA,0x2A,0x20,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"眚\",5810*/},{\n\n0x44,0x2A,0xF3,0xAA,0xA6,0xA0,0xAF,0xB1,0xF5,0x17,0x18,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"眢\",5811*/},{\n\n0xFE,0x92,0x92,0xFE,0x00,0xD8,0x54,0x53,0x50,0xD8,0x30,0x0F,0x04,0x04,0x0F,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"眙\",5812*/},{\n\n0xFE,0x92,0x92,0xFE,0x20,0x24,0x24,0xBF,0x24,0x24,0x20,0x0F,0x04,0x04,0x07,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"眭\",5813*/},{\n\n0x10,0xFE,0xB0,0xAF,0xAA,0xAA,0xA0,0xAF,0xB4,0xF2,0x19,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"眥\",5814*/},{\n\n0xFE,0x92,0x92,0xFE,0x08,0x44,0xAB,0x52,0x6A,0x46,0xC0,0x0F,0x04,0x04,0x0F,0x08,\n0x09,0x04,0x05,0x02,0x01,0x00,/*\"眵\",5815*/},{\n\n0xFE,0x92,0x92,0xFE,0x80,0x6C,0x4A,0xF9,0x48,0x4C,0x18,0x0F,0x04,0x04,0x0F,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"眸\",5816*/},{\n\n0xFE,0x92,0xFE,0x00,0x44,0x34,0x44,0xFF,0x44,0x34,0x44,0x0F,0x04,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"睞\",5817*/},{\n\n0xFE,0x92,0xFE,0x00,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x0F,0x04,0x0F,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"瞼\",5818*/},{\n\n0xFE,0x92,0x92,0xFE,0x00,0x75,0x56,0xFC,0x56,0x5D,0xC0,0x0F,0x04,0x04,0x0F,0x04,\n0x02,0x01,0x0F,0x00,0x02,0x03,/*\"睇\",5819*/},{\n\n0xFE,0x92,0xFE,0x00,0x24,0x96,0x65,0x44,0x44,0xD6,0x2C,0x0F,0x04,0x0F,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"睃\",5820*/},{\n\n0xFE,0x92,0xFE,0x00,0xFE,0x42,0x52,0x52,0x7E,0x52,0x52,0x0F,0x04,0x07,0x08,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"睚\",5821*/},{\n\n0xFE,0x92,0xFE,0x00,0xFE,0x92,0x81,0x90,0x92,0xFE,0x00,0x0F,0x04,0x07,0x08,0x04,\n0x03,0x00,0x00,0x07,0x08,0x0C,/*\"睨\",5822*/},{\n\n0xFE,0x92,0x92,0xFE,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x0F,0x04,0x04,0x0F,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"睢\",5823*/},{\n\n0xFE,0x92,0xFE,0x00,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x00,0x0F,0x04,0x0F,0x02,0x03,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"睥\",5824*/},{\n\n0x4C,0x54,0xEC,0xA4,0xB4,0xAF,0xB5,0xA5,0xED,0x55,0x4C,0x00,0x00,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0F,0x00,0x00,/*\"睿\",5825*/},{\n\n0xFE,0x92,0xFE,0x00,0xBC,0xAA,0xA0,0xFF,0xA0,0xAA,0xBE,0x0F,0x04,0x0F,0x00,0x08,\n0x09,0x0A,0x04,0x04,0x0A,0x09,/*\"瞍\",5826*/},{\n\n0xFE,0x92,0xFE,0x00,0x4A,0x32,0x4E,0xC0,0x4F,0x32,0x49,0x0F,0x04,0x0F,0x00,0x09,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"睽\",5827*/},{\n\n0x14,0xED,0xB7,0xBD,0xA7,0xAC,0xB4,0xAB,0xAA,0xF6,0x12,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"瞀\",5828*/},{\n\n0xFE,0x92,0xFE,0x00,0x48,0x6A,0x5A,0x4F,0x4A,0x6A,0x48,0x0F,0x04,0x07,0x08,0x0F,\n0x09,0x0F,0x09,0x0F,0x09,0x0F,/*\"瞌\",5829*/},{\n\n0xFE,0x92,0xFE,0x00,0x03,0x7D,0x55,0xD5,0x55,0x7D,0x03,0x0F,0x04,0x0F,0x00,0x09,\n0x05,0x01,0x01,0x01,0x05,0x09,/*\"瞑\",5830*/},{\n\n0xFE,0x92,0xFE,0x00,0x1D,0x55,0x5F,0x55,0x5F,0x55,0x1D,0x0F,0x04,0x0F,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"瞟\",5831*/},{\n\n0xFE,0x92,0xFE,0x00,0x0D,0xF6,0x94,0x97,0x94,0xF6,0x0D,0x0F,0x04,0x0F,0x00,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"瞠\",5832*/},{\n\n0xFE,0x92,0xFE,0x08,0xF9,0xAD,0xFB,0x10,0xEC,0x0B,0xF8,0x0F,0x04,0x0F,0x02,0x03,\n0x02,0x0F,0x09,0x04,0x03,0x0C,/*\"瞰\",5833*/},{\n\n0xFE,0x92,0xFE,0x00,0x95,0x6E,0xC4,0x1F,0x44,0xEE,0x55,0x0F,0x04,0x0F,0x02,0x09,\n0x06,0x01,0x03,0x02,0x0F,0x02,/*\"瞵\",5834*/},{\n\n0xBA,0xEA,0xAF,0xEA,0xBA,0x80,0xDA,0xAA,0xAF,0xDA,0x42,0x00,0x0F,0x09,0x0A,0x0C,\n0x08,0x09,0x0A,0x0C,0x0F,0x00,/*\"瞽\",5835*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x00,0x02,0x02,0xFE,0x02,0x02,0x07,0x02,0x03,0x02,0x07,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"町\",5836*/},{\n\n0x80,0xBE,0xAA,0xAA,0xAA,0xBE,0xAA,0xAA,0xAA,0xBE,0x80,0x08,0x04,0x03,0x00,0x00,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"畀\",5837*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x08,0xC8,0x3F,0xC8,0x09,0x0A,0x07,0x02,0x03,0x02,0x0B,\n0x06,0x01,0x00,0x01,0x06,0x08,/*\"畎\",5838*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x10,0xEC,0x0B,0x88,0x78,0x08,0x07,0x02,0x03,0x02,0x0B,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"畋\",5839*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x00,0xFE,0x12,0xF2,0x11,0xF1,0x07,0x02,0x03,0x02,0x03,\n0x04,0x03,0x08,0x05,0x02,0x0D,/*\"畈\",5840*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x48,0x24,0x93,0x44,0x08,0x90,0x07,0x02,0x03,0x02,0x0B,\n0x09,0x05,0x04,0x02,0x01,0x00,/*\"畛\",5841*/},{\n\n0x54,0xB4,0x92,0x96,0xD5,0xF5,0x95,0x96,0x92,0xB4,0x54,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"畲\",5842*/},{\n\n0xFE,0x22,0xFE,0x22,0xCC,0x34,0xE5,0x06,0xE4,0x24,0xEC,0x07,0x02,0x03,0x0A,0x04,\n0x03,0x00,0x00,0x07,0x09,0x0D,/*\"畹\",5843*/},{\n\n0xFE,0x22,0xFE,0x22,0xFE,0x08,0xFA,0xAE,0xFB,0xAE,0xFA,0x07,0x02,0x03,0x02,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"疃\",5844*/},{\n\n0x20,0x2F,0x29,0x29,0x2F,0xA9,0x6F,0x29,0x29,0x2F,0x20,0x04,0x04,0x02,0x02,0x01,\n0x0F,0x00,0x00,0x01,0x02,0x04,/*\"罘\",5845*/},{\n\n0x20,0x2F,0xA9,0x29,0x2F,0xE9,0x2F,0x29,0x29,0x2F,0x20,0x08,0x08,0x0F,0x08,0x08,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"罡\",5846*/},{\n\n0x20,0xAF,0xA9,0xA9,0xAF,0xF9,0xAF,0xA9,0xA9,0xAF,0x20,0x00,0x0F,0x04,0x04,0x04,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"罟\",5847*/},{\n\n0x20,0xAF,0xA9,0xA9,0xAF,0xB9,0xAF,0xA9,0xA9,0xAF,0x20,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"詈\",5848*/},{\n\n0x20,0xAF,0xE9,0xA9,0xBF,0xE9,0xAF,0xA9,0xE9,0x6F,0xA0,0x01,0x00,0x07,0x02,0x02,\n0x07,0x0A,0x0A,0x0B,0x0C,0x00,/*\"罨\",5849*/},{\n\n0x20,0xF7,0xAD,0xA5,0xA7,0xF5,0x27,0xBD,0x55,0x57,0x68,0x08,0x07,0x02,0x0A,0x02,\n0x07,0x08,0x03,0x05,0x0D,0x06,/*\"羆\",5850*/},{\n\n0x10,0xD7,0x55,0x55,0xD7,0x7D,0xD7,0x55,0x55,0xD7,0x10,0x00,0x0F,0x04,0x05,0x05,\n0x0F,0x05,0x05,0x08,0x0F,0x00,/*\"罱\",5851*/},{\n\n0xE0,0x07,0xFD,0x55,0xE7,0xBD,0xA7,0xED,0xB5,0xA7,0x20,0x00,0x00,0x0F,0x00,0x0F,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"罹\",5852*/},{\n\n0xD0,0x7F,0xD5,0x7D,0xD7,0x05,0xF7,0x55,0xF5,0x57,0x50,0x05,0x05,0x0F,0x05,0x05,\n0x00,0x0D,0x01,0x05,0x09,0x0F,/*\"羈\",5853*/},{\n\n0xF0,0x97,0xB5,0xDD,0x97,0xF5,0x97,0xDD,0xB5,0x97,0xF0,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"罾\",5854*/},{\n\n0x08,0x4A,0x6A,0x5A,0x4A,0x4F,0x4A,0x4A,0x6A,0x4A,0x08,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盍\",5855*/},{\n\n0x7E,0x2A,0x01,0x24,0x5C,0x7F,0x18,0x24,0x00,0x2A,0x7E,0x08,0x0F,0x09,0x09,0x0F,\n0x09,0x0F,0x09,0x09,0x0F,0x08,/*\"盥\",5856*/},{\n\n0xA5,0x96,0x84,0x96,0xA5,0x20,0xD7,0x5D,0xF7,0x55,0xF7,0x0F,0x08,0x0F,0x04,0x07,\n0x04,0x05,0x05,0x07,0x0D,0x0F,/*\"蠲\",5857*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x09,0x07,0x05,0x04,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"釒\",5858*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xFF,0x00,0x00,0x00,0x00,0x08,0x09,0x07,0x05,0x04,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"釓\",5859*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0x82,0x62,0x1A,0x06,0x00,0x08,0x09,0x07,0x05,0x04,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"釔\",5860*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0x00,0xFF,0x10,0x20,0xC0,0x08,0x09,0x07,0x05,0x04,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"釙\",5861*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xFC,0x00,0x00,0xFF,0x00,0x08,0x09,0x07,0x05,0x04,\n0x00,0x01,0x08,0x08,0x0F,0x00,/*\"釗\",5862*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x02,0x02,0xF2,0x0A,0x06,0x00,0x08,0x09,0x07,0x05,0x04,\n0x00,0x08,0x0F,0x00,0x00,0x00,/*\"釕\",5863*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x10,0x10,0xFF,0x10,0x10,0x00,0x08,0x09,0x07,0x05,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"釷\",5864*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xFF,0x00,0xFE,0x00,0xFF,0x08,0x09,0x07,0x05,0x04,\n0x08,0x07,0x00,0x07,0x00,0x0F,/*\"釧\",5865*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0x88,0x44,0x22,0x11,0x88,0x08,0x09,0x07,0x05,0x04,\n0x08,0x08,0x04,0x02,0x01,0x00,/*\"釤\",5866*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFF,0x49,0x7F,0x00,0x7F,0x49,0xFF,0x0A,0x0F,0x05,0x00,0x0F,\n0x00,0x00,0x00,0x00,0x08,0x0F,/*\"鍆\",5867*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x02,0x3E,0xC2,0x0A,0xD2,0x3E,0x00,0x08,0x09,0x07,0x04,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"釵\",5868*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x48,0xB8,0x0F,0x88,0x78,0x08,0x08,0x09,0x07,0x05,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"釹\",5869*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x42,0x22,0xFA,0x06,0x22,0xC2,0x08,0x09,0x07,0x05,0x04,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"鈈\",5870*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x08,0xC8,0x3F,0xC8,0x08,0x08,0x08,0x09,0x07,0x05,0x08,\n0x06,0x01,0x06,0x01,0x06,0x08,/*\"鈦\",5871*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0xFE,0x12,0x12,0x12,0xF2,0x08,0x09,0x07,0x05,0x04,\n0x00,0x0F,0x09,0x09,0x09,0x09,/*\"鉅\",5872*/},{\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x08,\n0x0B,0x0D,0x09,0x0D,0x0B,0x08,/*\"鎧\",5910*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x28,0x26,0xA4,0xFF,0x24,0x20,0x08,0x09,0x07,0x04,0x00,\n0x02,0x01,0x00,0x0F,0x01,0x02,/*\"銖\",5911*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x72,0xCE,0x00,0x22,0xFE,0x21,0x08,0x09,0x07,0x04,0x0A,\n0x04,0x0B,0x08,0x0A,0x0B,0x0A,/*\"鋌\",5912*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x92,0x92,0xFE,0x91,0x91,0x80,0x08,0x09,0x07,0x05,0x00,\n0x0C,0x0A,0x09,0x08,0x0C,0x08,/*\"銩\",5913*/},{\n\n0x4A,0xF9,0x4A,0x00,0xAA,0xFA,0xAF,0xFA,0xAF,0xFA,0xAA,0x0A,0x0F,0x05,0x00,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"鏵\",5914*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x10,0x28,0x24,0xE3,0x24,0x28,0x10,0x08,0x09,0x07,0x04,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"銓\",5915*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x10,0xA8,0xA4,0xA3,0xA4,0xA8,0x10,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"鉿\",5916*/},{\n\n0x2A,0xF9,0xAA,0x4A,0xE4,0x4B,0x08,0xE7,0x21,0xEF,0x08,0x05,0x07,0x02,0x09,0x0F,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"鎩\",5917*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x84,0x48,0xFF,0x00,0xFF,0x48,0x84,0x08,0x09,0x07,0x04,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"銚\",5918*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x08,0x54,0x53,0xF2,0x5A,0xF6,0x40,0x08,0x09,0x07,0x04,0x00,\n0x09,0x09,0x0F,0x01,0x03,0x00,/*\"錚\",5919*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x08,0xF4,0x93,0xF2,0x9A,0xF6,0x08,0x09,0x07,0x05,0x04,\n0x00,0x07,0x08,0x08,0x08,0x0E,/*\"銫\",5920*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x64,0xD4,0x4D,0xC6,0x54,0xE4,0x08,0x09,0x07,0x04,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"銃\",5921*/},{\n\n0x4A,0xF9,0x4A,0x10,0x22,0x84,0x5F,0xD5,0x55,0x55,0x5F,0x0A,0x0F,0x05,0x02,0x01,\n0x0A,0x05,0x0B,0x05,0x0B,0x0F,/*\"鐋\",5922*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x4C,0xC5,0x76,0x44,0xC4,0x4C,0x08,0x09,0x07,0x04,0x00,\n0x09,0x05,0x02,0x02,0x05,0x08,/*\"銨\",5923*/},{\n\n0x4A,0xF9,0x4A,0x88,0x78,0x0F,0xF8,0x00,0xFC,0x04,0xFC,0x0A,0x0F,0x05,0x08,0x05,\n0x02,0x0D,0x00,0x07,0x02,0x07,/*\"銣\",5924*/},{\n\n0x4A,0xF9,0x4A,0x00,0x6A,0x27,0xAA,0x21,0x2A,0x27,0x6A,0x0A,0x0F,0x05,0x00,0x08,\n0x05,0x03,0x09,0x09,0x07,0x00,/*\"鐒\",5925*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x44,0x34,0x44,0xFF,0x44,0x34,0x44,0x08,0x09,0x07,0x04,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"錸\",5926*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xD4,0x24,0x84,0x3F,0xC4,0x05,0x08,0x09,0x07,0x04,0x01,\n0x03,0x04,0x06,0x01,0x07,0x0C,/*\"鋱\",5927*/},{\n\n0x4A,0xF9,0x4A,0xFE,0xAA,0xEE,0xBA,0x80,0x5E,0x22,0xDE,0x0A,0x0F,0x05,0x08,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"鏗\",5928*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x2F,0x29,0xE9,0x29,0x2F,0x00,0x08,0x09,0x07,0x04,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"鋥\",5929*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x7F,0x49,0xFF,0x49,0x7F,0x00,0x08,0x09,0x07,0x04,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"鋰\",5930*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x28,0xA6,0xA4,0xBF,0xA4,0xA4,0x08,0x09,0x07,0x04,0x00,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"鋯\",5931*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x92,0xFE,0x51,0x10,0xFF,0x92,0x54,0x08,0x09,0x07,0x04,0x08,\n0x0F,0x04,0x02,0x03,0x04,0x0E,/*\"鋨\",5932*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x20,0x1C,0x20,0xFF,0x20,0x1C,0x20,0x08,0x09,0x07,0x04,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"銼\",5933*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x00,0x4A,0x52,0x46,0xE9,0x45,0x08,0x09,0x07,0x05,0x04,\n0x00,0x01,0x02,0x08,0x0F,0x00,/*\"鋝\",5934*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xA4,0x34,0xAD,0x26,0xB4,0x64,0x08,0x09,0x07,0x04,0x08,\n0x07,0x00,0x07,0x00,0x0F,0x08,/*\"鋶\",5935*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFF,0x55,0xDF,0x40,0xDF,0x55,0xFF,0x0A,0x0F,0x05,0x00,0x0F,\n0x05,0x03,0x01,0x07,0x09,0x0F,/*\"鐦\",5936*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFF,0x15,0xDF,0x40,0xDF,0x15,0xFF,0x0A,0x0F,0x05,0x00,0x0F,\n0x00,0x07,0x05,0x07,0x08,0x0F,/*\"鐧\",5937*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xFC,0x55,0xD6,0x54,0x7C,0x80,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"鋃\",5938*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0xC0,0x55,0x55,0x55,0x5F,0xC0,0x08,0x09,0x07,0x05,0x04,\n0x08,0x0B,0x05,0x05,0x0B,0x08,/*\"鋟\",5939*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFF,0x15,0xD5,0x55,0xD5,0x17,0xF0,0x0A,0x0F,0x05,0x08,0x07,\n0x00,0x03,0x02,0x0B,0x08,0x07,/*\"鋦\",5940*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFE,0x32,0xCE,0xF8,0x8A,0xFE,0x02,0x0A,0x0F,0x05,0x00,0x0F,\n0x02,0x01,0x00,0x08,0x0F,0x00,/*\"錒\",5941*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x20,0xEA,0xAA,0xBF,0xAA,0xEA,0x22,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"錆\",5942*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xA4,0xEF,0xB4,0xA4,0xAF,0xA4,0x08,0x09,0x07,0x04,0x01,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"鍩\",5943*/},{\n\n0x2A,0xF9,0xAA,0x00,0x12,0xAA,0x26,0x73,0x26,0xAA,0x12,0x05,0x07,0x02,0x08,0x05,\n0x03,0x01,0x01,0x01,0x0F,0x01,/*\"錛\",5944*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0x5F,0x55,0x55,0x55,0xD5,0x5F,0x08,0x09,0x07,0x04,0x01,\n0x03,0x05,0x01,0x09,0x0F,0x01,/*\"鍀\",5945*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x40,0x5F,0x55,0xFF,0x55,0x5F,0x40,0x08,0x09,0x07,0x04,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"錁\",5946*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x00,0xDF,0x95,0x15,0xD5,0x15,0x9F,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x04,0x00,0x07,0x09,0x0C,/*\"錕\",5947*/},{\n\n0x4A,0xF9,0x4A,0x00,0x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,0x0F,0x00,/*\"鑥\",5985*/},{\n\n0x4A,0xF9,0x4A,0x00,0xBA,0xAB,0xBA,0x10,0xEF,0x08,0xF8,0x0A,0x0F,0x05,0x00,0x0A,\n0x0E,0x03,0x0A,0x05,0x02,0x0D,/*\"鐓\",5986*/},{\n\n0x4A,0xF9,0x4A,0x00,0xFF,0xD5,0x57,0xF8,0x57,0xD5,0xFF,0x0A,0x0F,0x05,0x00,0x0F,\n0x0A,0x06,0x0F,0x06,0x0A,0x0F,/*\"鑭\",5987*/},{\n\n0x4A,0xF9,0x4A,0x00,0x2A,0xA3,0xBE,0xA2,0xBE,0xA3,0x2A,0x0A,0x0F,0x05,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"鐠\",5988*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x06,0xEA,0x56,0x03,0x56,0xFA,0x06,0x08,0x09,0x07,0x04,0x00,\n0x0F,0x05,0x0F,0x05,0x07,0x08,/*\"鑹\",5989*/},{\n\n0x4A,0xF9,0x4A,0x00,0x79,0xCF,0xF0,0x97,0xFD,0x97,0xF0,0x0A,0x0F,0x05,0x00,0x08,\n0x0F,0x04,0x04,0x07,0x04,0x0E,/*\"鏹\",5990*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x25,0xD9,0x57,0x50,0x57,0xDA,0x25,0x08,0x09,0x07,0x04,0x08,\n0x0B,0x0D,0x09,0x0D,0x0B,0x08,/*\"鐙\",5991*/},{\n\n0xA4,0x2A,0xF9,0x2A,0xA4,0x10,0xFA,0x57,0xFA,0x57,0x52,0x08,0x09,0x07,0x05,0x04,\n0x09,0x0B,0x05,0x05,0x0B,0x09,/*\"鑊\",5992*/},{\n\n0x4A,0xF9,0x4A,0x20,0xD7,0x5D,0xF7,0x55,0xD7,0x15,0xF7,0x0A,0x0F,0x05,0x00,0x05,\n0x05,0x07,0x05,0x0D,0x08,0x07,/*\"鐲\",5993*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x08,0x08,0x09,0x07,0x04,0x0C,\n0x00,0x0C,0x0A,0x0C,0x02,0x0C,/*\"鐿\",5994*/},{\n\n0x4A,0xF9,0x4A,0x20,0x56,0x2A,0x5A,0x43,0x5A,0x2A,0x5E,0x0A,0x0F,0x05,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"鑔\",5995*/},{\n\n0x2A,0xF9,0xAA,0x00,0xFE,0x2A,0xFE,0xAB,0xFE,0xAA,0x7A,0x05,0x07,0x02,0x04,0x0B,\n0x00,0x0B,0x02,0x09,0x02,0x0B,/*\"鑣\",5996*/},{\n\n0xA4,0x2A,0xF9,0xAA,0x08,0xFA,0xAA,0xFE,0xA9,0xF9,0x08,0x08,0x09,0x07,0x04,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"鍾\",5997*/},{\n\n0x48,0x47,0xFC,0x44,0x00,0xF2,0x92,0x9E,0x00,0xFF,0x00,0x08,0x06,0x01,0x06,0x00,\n0x08,0x08,0x07,0x00,0x0F,0x00,/*\"矧\",5998*/},{\n\n0x48,0x47,0xFC,0x44,0x20,0x1C,0x20,0xFF,0x20,0x1C,0x20,0x08,0x06,0x01,0x06,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"矬\",5999*/},{\n\n0x48,0x47,0xFC,0x44,0x10,0xFC,0x27,0x24,0xFD,0x26,0x24,0x08,0x06,0x01,0x06,0x00,\n0x0F,0x09,0x09,0x0F,0x09,0x09,/*\"雉\",6000*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0xFF,0x10,0x10,0xFF,0x10,0x0C,0x01,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x02,0x07,0x08,0x0E,/*\"秕\",6001*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0x78,0x48,0xFF,0x44,0x44,0xC0,0x01,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x00,0x02,0x03,/*\"秭\",6002*/},{\n\n0x12,0xD2,0xFE,0x51,0x94,0x24,0xA4,0xFF,0xA4,0x24,0x04,0x01,0x00,0x0F,0x00,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"秣\",6003*/},{\n\n0x12,0xD2,0xFE,0x91,0x00,0x88,0x68,0xFF,0x68,0x89,0x0A,0x01,0x00,0x0F,0x00,0x02,\n0x01,0x00,0x0F,0x00,0x01,0x02,/*\"秫\",6004*/},{\n\n0x12,0xD2,0xFE,0x91,0x44,0xBE,0xD5,0xBD,0xD7,0xBC,0x40,0x01,0x00,0x0F,0x00,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"穭\",6005*/},{\n\n0x12,0xD2,0xFE,0x91,0x44,0x34,0x0F,0x7C,0x85,0x86,0xE4,0x01,0x00,0x0F,0x00,0x0E,\n0x08,0x08,0x0F,0x08,0x08,0x0E,/*\"嵇\",6006*/},{\n\n0x12,0xD2,0xFE,0x91,0x00,0x2A,0x32,0x26,0xAA,0x71,0x2D,0x01,0x00,0x0F,0x00,0x00,\n0x01,0x01,0x09,0x0F,0x01,0x01,/*\"稃\",6007*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0xFC,0x55,0xD6,0x54,0x7C,0x80,0x01,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"稂\",6008*/},{\n\n0x12,0xD2,0xFE,0x91,0x40,0x5F,0x55,0xFF,0x55,0x5F,0x40,0x01,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"稞\",6009*/},{\n\n0x12,0xD2,0xFE,0x91,0x08,0x14,0x92,0x19,0x52,0x34,0x08,0x01,0x00,0x0F,0x04,0x03,\n0x00,0x06,0x09,0x0C,0x01,0x06,/*\"稔\",6010*/},{\n\n0x12,0xD2,0xFE,0x91,0x02,0xFA,0xAA,0xAF,0xAA,0xFA,0x02,0x01,0x00,0x0F,0x00,0x02,\n0x0B,0x06,0x02,0x06,0x0B,0x02,/*\"稹\",6011*/},{\n\n0x12,0xD2,0xFE,0x51,0x80,0x5F,0xB5,0x1F,0x35,0x5F,0x80,0x01,0x00,0x0F,0x00,0x02,\n0x09,0x0B,0x05,0x05,0x0B,0x08,/*\"稷\",6012*/},{\n\n0x12,0xD2,0xFE,0x91,0xDA,0x56,0x5A,0x5F,0x5A,0x56,0xDA,0x01,0x00,0x0F,0x00,0x0F,\n0x08,0x0F,0x0D,0x0F,0x08,0x0F,/*\"穡\",6013*/},{\n\n0x54,0x4D,0xBF,0x2D,0x54,0x00,0xC0,0x40,0x7F,0x48,0xC8,0x05,0x0A,0x0F,0x02,0x05,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"黏\",6014*/},{\n\n0x4A,0xAA,0xFE,0xA9,0x48,0x02,0x7D,0xD5,0x55,0x7D,0x01,0x00,0x0F,0x0A,0x0F,0x00,\n0x0A,0x0B,0x05,0x05,0x0B,0x08,/*\"馥\",6015*/},{\n\n0x12,0xD2,0xFE,0x51,0xBA,0xAA,0xFA,0x83,0xFA,0xAA,0xBA,0x01,0x00,0x0F,0x00,0x0A,\n0x06,0x0F,0x0A,0x03,0x06,0x0A,/*\"穰\",6016*/},{\n\n0xFC,0x26,0x25,0xFC,0x00,0xFE,0x12,0xF2,0x12,0x91,0x71,0x07,0x02,0x02,0x0F,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"皈\",6017*/},{\n\n0xFC,0x26,0x25,0xFC,0x40,0x24,0xD5,0x06,0xD4,0x24,0x44,0x07,0x02,0x02,0x07,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"皎\",6018*/},{\n\n0xFC,0x46,0x45,0xFC,0x28,0xA6,0xA4,0xBF,0xA4,0xA4,0x20,0x0F,0x04,0x04,0x0F,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"皓\",6019*/},{\n\n0x12,0x8A,0xBF,0xCA,0x92,0xA0,0x9E,0x8A,0x8A,0xBA,0x09,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"皙\",6020*/},{\n\n0xFC,0x26,0x25,0xFC,0x52,0xB6,0x9A,0xBE,0x99,0xB5,0x50,0x07,0x02,0x02,0x07,0x00,\n0x0F,0x0A,0x0F,0x0A,0x0F,0x00,/*\"皤\",6021*/},{\n\n0xFE,0x02,0xFE,0x02,0xFD,0x28,0x26,0xA4,0x7F,0xA4,0x24,0x07,0x00,0x0F,0x0A,0x0D,\n0x02,0x05,0x04,0x08,0x08,0x09,/*\"瓞\",6022*/},{\n\n0x4A,0xD6,0x53,0x56,0x4A,0x00,0xFE,0x02,0xFE,0x02,0xFD,0x00,0x01,0x09,0x0F,0x00,\n0x08,0x07,0x00,0x0F,0x0A,0x0C,/*\"瓠\",6023*/},{\n\n0x00,0xF1,0x51,0x51,0x55,0xF9,0x55,0x53,0x51,0xF0,0x00,0x00,0x0F,0x01,0x01,0x01,\n0x07,0x01,0x01,0x09,0x0F,0x00,/*\"甬\",6024*/},{\n\n0x08,0xFF,0x08,0xF8,0x00,0xFE,0xAB,0xAA,0xAA,0xBE,0xA0,0x08,0x07,0x00,0x07,0x02,\n0x08,0x06,0x00,0x0A,0x08,0x07,/*\"鳩\",6025*/},{\n\n0x04,0xE4,0xA4,0xA4,0xB3,0xE6,0xAA,0xAA,0xF3,0x92,0x9A,0x08,0x03,0x0A,0x02,0x0A,\n0x02,0x0A,0x02,0x0A,0x0A,0x06,/*\"鳶\",6026*/},{\n\n0x8F,0xD2,0x99,0x00,0xFE,0xAA,0xAB,0xAA,0xAA,0xBE,0x80,0x00,0x0F,0x00,0x08,0x07,\n0x0A,0x06,0x0A,0x06,0x0A,0x0E,/*\"鴇\",6027*/},{\n\n0x1C,0xC4,0x3F,0xC4,0x1C,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x08,0x07,0x00,0x07,0x02,\n0x01,0x06,0x00,0x0A,0x08,0x07,/*\"鴆\",6028*/},{\n\n0xC8,0x48,0x7F,0x48,0xC8,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x0F,0x04,0x04,0x04,0x0F,\n0x08,0x06,0x00,0x0A,0x08,0x07,/*\"鴣\",6029*/},{\n\n0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x04,0x02,0x0F,0x02,0x04,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鶇\",6030*/},{\n\n0x00,0xF8,0x28,0xFF,0xAA,0xAA,0xDA,0x00,0xFE,0xAB,0xBE,0x06,0x09,0x0E,0x0B,0x0E,\n0x0B,0x0E,0x08,0x06,0x08,0x0F,/*\"鸕\",6031*/},{\n\n0xE8,0x27,0xE4,0x04,0xFC,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x03,0x01,0x09,0x08,0x07,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鴝\",6032*/},{\n\n0xFE,0x22,0xFE,0x21,0x21,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x0F,0x04,0x0B,0x04,0x0E,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鴟\",6033*/},{\n\n0x2A,0x8B,0xAE,0x8A,0xED,0x80,0xAA,0x8B,0xBE,0x0A,0x2D,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0B,0x0A,0x06,/*\"鷥\",6034*/},{\n\n0xF2,0x12,0xFA,0x16,0xF2,0x12,0xF2,0x00,0xFE,0xAB,0xBE,0x0F,0x00,0x07,0x00,0x07,\n0x08,0x0F,0x00,0x06,0x08,0x0F,/*\"鴯\",6035*/},{\n\n0x28,0xBA,0xEF,0xBA,0xE8,0x80,0xCA,0xBF,0x92,0x3E,0x60,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0B,0x0A,0x06,/*\"鷙\",6036*/},{\n\n0x92,0x92,0xFE,0x91,0x91,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x0F,0x04,0x04,0x04,0x0F,\n0x08,0x06,0x00,0x0A,0x08,0x07,/*\"鴰\",6037*/},{\n\n0x10,0xFC,0x83,0x48,0xFF,0x48,0x80,0xFE,0xAB,0xBE,0xA0,0x00,0x0F,0x00,0x00,0x0F,\n0x00,0x00,0x08,0x06,0x08,0x0F,/*\"鵂\",6038*/},{\n\n0x56,0x9D,0xD4,0x80,0xFA,0xAB,0xBA,0x80,0xD6,0x1D,0x54,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0B,0x0A,0x06,/*\"鸞\",6039*/},{\n\n0x1A,0x2A,0xAF,0x6A,0x1A,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x02,0x0A,0x0F,0x01,0x01,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鵓\",6040*/},{\n\n0xED,0xA5,0xED,0xB0,0xED,0xA5,0xAD,0x00,0xFE,0xAB,0xBE,0x07,0x02,0x0F,0x0A,0x03,\n0x0E,0x0B,0x00,0x06,0x08,0x0F,/*\"鸝\",6041*/},{\n\n0x28,0xA6,0xA4,0xBF,0xA4,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x00,0x0F,0x04,0x04,0x0F,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鵠\",6042*/},{\n\n0x22,0xD1,0x4C,0xD1,0x22,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x00,0x0F,0x04,0x07,0x00,\n0x08,0x06,0x00,0x0A,0x08,0x07,/*\"鵒\",6043*/},{\n\n0xFF,0x15,0xFF,0xA0,0xFF,0x15,0xFF,0x00,0xFE,0xAB,0xBE,0x0F,0x08,0x07,0x0A,0x0F,\n0x00,0x0F,0x00,0x06,0x08,0x0F,/*\"鷳\",6044*/},{\n\n0x75,0x56,0xFC,0x56,0xDD,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x02,0x01,0x0F,0x02,0x03,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鵜\",6045*/},{\n\n0x90,0x12,0xF2,0x90,0xFF,0x12,0x14,0x00,0xFE,0xAB,0xBE,0x0F,0x08,0x07,0x04,0x03,\n0x04,0x0E,0x00,0x06,0x08,0x0F,/*\"鵡\",6046*/},{\n\n0xF2,0x97,0xF2,0x97,0xF2,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x0F,0x04,0x07,0x04,0x0F,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鶓\",6047*/},{\n\n0x12,0xEA,0xA6,0xF3,0xA6,0xEA,0x10,0xFE,0xAB,0xBE,0xA0,0x00,0x07,0x02,0x0F,0x0A,\n0x0B,0x04,0x08,0x06,0x08,0x0F,/*\"鵪\",6048*/},{\n\n0x7C,0xD6,0x7D,0x54,0x7C,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x03,0x02,0x0F,0x02,0x02,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鵯\",6049*/},{\n\n0x02,0xBA,0xAA,0xAB,0xAA,0x3A,0x00,0xFE,0xAB,0xBE,0xA0,0x02,0x02,0x0A,0x0E,0x03,\n0x02,0x00,0x08,0x06,0x08,0x0F,/*\"鶉\",6050*/},{\n\n0xE4,0x3F,0xE4,0x00,0xFF,0x89,0xFF,0x00,0xFE,0xAB,0xBE,0x07,0x02,0x0B,0x04,0x03,\n0x08,0x0F,0x00,0x06,0x08,0x0F,/*\"鶘\",6051*/},{\n\n0x47,0xD5,0x57,0x50,0x57,0x55,0x47,0xFE,0xAB,0xBE,0xA0,0x00,0x01,0x01,0x09,0x09,\n0x07,0x00,0x08,0x06,0x08,0x0F,/*\"鶚\",6052*/},{\n\n0xE8,0x99,0x4A,0x08,0xEC,0x9B,0x48,0x00,0xFE,0xAB,0xBE,0x06,0x05,0x0E,0x00,0x06,\n0x05,0x0E,0x00,0x06,0x08,0x0F,/*\"鷀\",6053*/},{\n\n0x00,0xFF,0x09,0xEF,0xA9,0xEF,0x00,0xFE,0xAB,0xBE,0xA0,0x08,0x07,0x00,0x0F,0x0A,\n0x0F,0x00,0x08,0x06,0x08,0x0F,/*\"鶥\",6054*/},{\n\n0x28,0x99,0xAB,0xBD,0xCB,0x98,0xA4,0x97,0x8A,0x16,0x22,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0B,0x0A,0x06,/*\"鶩\",6055*/},{\n\n0xA6,0x9A,0xF6,0x9A,0x95,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x0E,0x08,0x07,0x04,0x0E,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鷂\",6056*/},{\n\n0x55,0xFE,0x54,0xFE,0x55,0xF4,0x40,0xFE,0xAB,0xBE,0xA0,0x05,0x0F,0x01,0x0F,0x05,\n0x09,0x00,0x08,0x06,0x08,0x0F,/*\"鶼\",6057*/},{\n\n0x5F,0x35,0xDF,0x00,0x5F,0x35,0x5F,0x00,0xFE,0xAB,0xBE,0x09,0x0B,0x05,0x05,0x05,\n0x0B,0x09,0x00,0x06,0x08,0x0F,/*\"鸚\",6058*/},{\n\n0xFE,0x22,0xFA,0x23,0xFA,0x22,0x00,0xFE,0xAB,0xBE,0xA0,0x0B,0x04,0x09,0x05,0x09,\n0x04,0x08,0x08,0x06,0x08,0x0F,/*\"鷓\",6059*/},{\n\n0x8B,0x45,0xAF,0x5A,0xA5,0x4F,0x00,0xFE,0xAB,0xBE,0xA0,0x00,0x0A,0x0A,0x09,0x04,\n0x02,0x00,0x08,0x06,0x08,0x0F,/*\"鷚\",6060*/},{\n\n0x2A,0x12,0xFA,0x57,0xFA,0x12,0x28,0xFE,0xAB,0xBE,0xA0,0x04,0x02,0x09,0x0F,0x01,\n0x02,0x04,0x08,0x06,0x08,0x0F,/*\"鷯\",6061*/},{\n\n0x08,0xFC,0x57,0x54,0xFD,0x56,0x54,0x00,0xFE,0xAB,0xBE,0x0C,0x03,0x0D,0x01,0x0D,\n0x01,0x0D,0x00,0x06,0x08,0x0F,/*\"鷦\",6062*/},{\n\n0x12,0xAE,0xBB,0x8E,0xD2,0xA4,0x9C,0x87,0x9C,0x25,0x34,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0B,0x0A,0x06,/*\"鷲\",6063*/},{\n\n0xE8,0x59,0xEB,0x7D,0xCD,0x4B,0xD8,0x00,0xFE,0xAB,0xBE,0x0F,0x01,0x0E,0x0A,0x0E,\n0x01,0x0F,0x00,0x06,0x08,0x0F,/*\"鷸\",6064*/},{\n\n0xFE,0xAB,0xAA,0xBE,0xA0,0x12,0xFA,0x57,0xFA,0x57,0x52,0x06,0x00,0x0A,0x08,0x07,\n0x09,0x0B,0x05,0x05,0x0B,0x09,/*\"鸌\",6065*/},{\n\n0xEE,0x8A,0xFA,0xAE,0xC0,0x94,0xF7,0xAA,0xAA,0xF6,0x10,0x08,0x03,0x0A,0x02,0x0A,\n0x03,0x0A,0x02,0x0B,0x0A,0x06,/*\"鷺\",6066*/},{\n\n0xBA,0xEF,0xBA,0xEF,0xBA,0x00,0xFE,0xAB,0xAA,0xBE,0xA0,0x00,0x0F,0x0A,0x0F,0x0A,\n0x00,0x06,0x00,0x0A,0x08,0x07,/*\"鸛\",6067*/},{\n\n0x08,0x90,0xFC,0x04,0x04,0x05,0x06,0x04,0x04,0x04,0x04,0x09,0x04,0x03,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"疒\",6068*/},{\n\n0x08,0x90,0xFC,0x24,0x24,0x25,0x26,0xE4,0x24,0x24,0x24,0x09,0x04,0x03,0x00,0x00,\n0x08,0x08,0x0F,0x00,0x00,0x00,/*\"疔\",6069*/},{\n\n0x88,0xFE,0x12,0xEE,0xBA,0xAA,0xEB,0x12,0xEE,0x3A,0xEA,0x08,0x07,0x00,0x0F,0x0A,\n0x06,0x0B,0x00,0x0F,0x02,0x03,/*\"癤\",6070*/},{\n\n0x10,0xFE,0x0A,0xEA,0xBE,0xAA,0xEB,0xAA,0xBE,0xEA,0x0A,0x09,0x07,0x0E,0x03,0x0A,\n0x0A,0x0F,0x0A,0x0E,0x03,0x0E,/*\"癘\",6071*/},{\n\n0x08,0x90,0xFC,0x04,0xC4,0x05,0x06,0xF4,0x04,0x04,0xC4,0x09,0x04,0x03,0x00,0x07,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"疝\",6072*/},{\n\n0x88,0xFE,0x02,0xFA,0xAA,0xEA,0x9B,0x0A,0xAA,0xEA,0x9A,0x08,0x07,0x08,0x07,0x08,\n0x0D,0x08,0x0F,0x0A,0x0B,0x08,/*\"癧\",6073*/},{\n\n0x08,0x90,0xFE,0x22,0x22,0xFA,0x23,0xE2,0x2A,0x32,0x22,0x09,0x04,0x03,0x08,0x06,\n0x01,0x00,0x07,0x08,0x08,0x0E,/*\"疣\",6074*/},{\n\n0x08,0x90,0xFE,0x12,0xFA,0x92,0x93,0x92,0x92,0xFA,0x12,0x09,0x04,0x03,0x00,0x0F,\n0x04,0x04,0x04,0x04,0x0F,0x00,/*\"疳\",6075*/},{\n\n0x88,0xFE,0x02,0xFA,0x6A,0x9A,0xE3,0x2A,0xEA,0xFA,0x0A,0x08,0x07,0x00,0x0F,0x02,\n0x01,0x01,0x01,0x09,0x0F,0x00,/*\"痾\",6076*/},{\n\n0x08,0x90,0xFE,0x02,0xFA,0x4A,0x4B,0x4A,0x4A,0xFA,0x02,0x09,0x04,0x03,0x08,0x0B,\n0x0A,0x0A,0x0A,0x0A,0x0B,0x08,/*\"疸\",6077*/},{\n\n0x08,0x90,0xFC,0x84,0x44,0x3D,0xE6,0xA4,0xA4,0xA4,0x24,0x09,0x04,0x03,0x00,0x00,\n0x00,0x0F,0x02,0x02,0x02,0x02,/*\"痄\",6078*/},{\n\n0x00,0xFC,0x24,0x3F,0xE4,0x0C,0xF4,0x97,0xF4,0x04,0xFC,0x04,0x0B,0x05,0x02,0x0D,\n0x00,0x07,0x08,0x08,0x09,0x0D,/*\"皰\",6079*/},{\n\n0x08,0x90,0xFC,0x04,0x24,0x25,0x2E,0xF4,0x24,0x24,0x24,0x09,0x04,0x03,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"疰\",6080*/},{\n\n0x08,0x90,0xFE,0x02,0x92,0xD2,0xB7,0x9A,0x92,0x52,0x12,0x09,0x04,0x03,0x00,0x04,\n0x04,0x06,0x05,0x04,0x06,0x0C,/*\"痃\",6081*/},{\n\n0x88,0xFE,0x02,0x12,0xFE,0x12,0xF3,0x02,0xF2,0x12,0xF2,0x08,0x07,0x08,0x06,0x09,\n0x08,0x07,0x00,0x0F,0x04,0x0F,/*\"痂\",6082*/},{\n\n0x08,0x90,0xFE,0x02,0xEA,0x2A,0x3B,0x0A,0x3A,0x2A,0xEA,0x09,0x04,0x03,0x00,0x09,\n0x09,0x0F,0x08,0x0F,0x09,0x09,/*\"瘂\",6083*/},{\n\n0x88,0xFE,0x02,0xEA,0xAA,0xAA,0xFF,0xAA,0xAA,0xBA,0x82,0x08,0x07,0x08,0x08,0x04,\n0x02,0x01,0x02,0x04,0x0A,0x0B,/*\"痍\",6084*/},{\n\n0x88,0xFE,0x12,0x92,0x92,0x92,0xFB,0x92,0x92,0x92,0x12,0x08,0x07,0x08,0x06,0x00,\n0x06,0x09,0x0A,0x0C,0x02,0x0C,/*\"痣\",6085*/},{\n\n0x88,0xFE,0x92,0xCA,0xBE,0xD2,0x8B,0xD2,0xBE,0xD2,0x8A,0x08,0x07,0x09,0x0A,0x06,\n0x03,0x02,0x0A,0x0A,0x06,0x01,/*\"癆\",6086*/},{\n\n0x08,0x90,0xFE,0x82,0xAA,0xEA,0xBB,0xAA,0xEA,0x8A,0x82,0x09,0x04,0x03,0x00,0x0E,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"痦\",6087*/},{\n\n0x08,0x90,0xFC,0x44,0x34,0x45,0xFE,0x44,0x34,0x44,0x84,0x09,0x04,0x0B,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x08,/*\"痤\",6088*/},{\n\n0x88,0xFE,0x02,0xFA,0x2A,0xFA,0xA3,0xE2,0x3A,0x2A,0xFA,0x08,0x07,0x00,0x0F,0x08,\n0x07,0x0A,0x0F,0x00,0x08,0x0F,/*\"癇\",6089*/},{\n\n0x88,0xFE,0x02,0x26,0x4A,0x82,0x73,0x02,0xFE,0x12,0x62,0x08,0x07,0x00,0x04,0x02,\n0x08,0x08,0x04,0x04,0x02,0x01,/*\"痧\",6090*/},{\n\n0x08,0x90,0xFE,0x02,0x4A,0xAA,0xDB,0x2A,0xCA,0x4A,0x2A,0x09,0x04,0x03,0x00,0x05,\n0x04,0x0A,0x09,0x07,0x01,0x02,/*\"瘃\",6091*/},{\n\n0x88,0xFE,0x02,0x92,0x92,0xFE,0x03,0x02,0xFE,0x92,0x92,0x08,0x07,0x00,0x04,0x04,\n0x0F,0x00,0x00,0x0F,0x04,0x04,/*\"痱\",6092*/},{\n\n0x08,0x90,0xFE,0x02,0xFA,0x0A,0xAB,0xFA,0xAA,0x0A,0xFA,0x09,0x04,0x03,0x00,0x0F,\n0x08,0x0B,0x0A,0x0B,0x08,0x0F,/*\"痼\",6093*/},{\n\n0x08,0x90,0xFE,0x02,0xA2,0x6A,0xAB,0x7A,0x2A,0x66,0xA2,0x09,0x04,0x03,0x09,0x09,\n0x0B,0x05,0x05,0x0B,0x09,0x01,/*\"痿\",6094*/},{\n\n0x88,0xFE,0x02,0xE2,0x52,0x02,0xFB,0x02,0x52,0xF2,0x02,0x08,0x07,0x08,0x09,0x05,\n0x03,0x01,0x03,0x05,0x09,0x08,/*\"瘐\",6095*/},{\n\n0x88,0xFE,0x12,0xF6,0x5A,0xD2,0x23,0x12,0x4E,0x92,0x22,0x08,0x07,0x08,0x07,0x08,\n0x0F,0x00,0x02,0x04,0x09,0x00,/*\"瘀\",6096*/},{\n\n0x08,0x90,0xFE,0x02,0x3A,0xEA,0xBB,0xE2,0xBA,0xEA,0x3A,0x09,0x04,0x03,0x00,0x02,\n0x03,0x02,0x0F,0x02,0x03,0x02,/*\"癉\",6097*/},{\n\n0x10,0xFE,0xEA,0xAA,0xFE,0xAA,0xEB,0x02,0xF2,0x02,0xFA,0x09,0x07,0x04,0x02,0x0F,\n0x02,0x04,0x00,0x03,0x08,0x0F,/*\"瘌\",6098*/},{\n\n0x08,0x90,0xFE,0x4A,0x3A,0xCA,0x7F,0xCA,0x3A,0x4A,0x0A,0x09,0x04,0x03,0x0A,0x09,\n0x0A,0x0F,0x0A,0x09,0x0A,0x02,/*\"瘞\",6099*/},{\n\n0x08,0x90,0xFE,0x12,0xFA,0x26,0xEB,0xAA,0xAA,0xBA,0xA2,0x09,0x04,0x03,0x00,0x0F,\n0x01,0x0A,0x06,0x03,0x06,0x0A,/*\"瘊\",6100*/},{\n\n0x88,0xFE,0x02,0x8A,0xAE,0xEA,0xBB,0xAA,0xAA,0xAE,0x8A,0x08,0x07,0x04,0x02,0x09,\n0x0A,0x0A,0x0E,0x0A,0x0A,0x08,/*\"瘥\",6101*/},{\n\n0x08,0x90,0xFE,0x22,0x22,0xFA,0x2B,0xFE,0x2A,0xFA,0x22,0x09,0x04,0x03,0x00,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"瘻\",6102*/},{\n\n0x88,0xFE,0x02,0xFA,0xAA,0xBA,0x03,0xAA,0xAA,0xBA,0x02,0x08,0x07,0x00,0x0F,0x02,\n0x02,0x08,0x05,0x02,0x05,0x08,/*\"瘕\",6103*/},{\n\n0x88,0xFE,0x42,0xCA,0xDA,0xAA,0xFB,0xAA,0xAA,0xDA,0x42,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0B,0x0C,/*\"瘙\",6104*/},{\n\n0x88,0xFE,0x02,0xAA,0xFE,0xAA,0x8B,0x7A,0x8A,0xFA,0x02,0x08,0x07,0x08,0x06,0x01,\n0x06,0x09,0x0A,0x0C,0x02,0x0C,/*\"瘛\",6105*/},{\n\n0x08,0x90,0xFE,0x0A,0xEA,0xBE,0xAB,0xAA,0xBE,0xEA,0x0A,0x09,0x04,0x03,0x0A,0x0B,\n0x06,0x02,0x02,0x06,0x0B,0x0A,/*\"瘼\",6106*/},{\n\n0x08,0xFE,0x82,0xFA,0xAE,0xFB,0x22,0x9A,0x8A,0xBA,0x22,0x09,0x07,0x08,0x07,0x0A,\n0x0F,0x00,0x0B,0x04,0x0B,0x08,/*\"瘢\",6107*/},{\n\n0x88,0xFE,0x42,0x56,0xEA,0xB2,0xAF,0xB2,0xEA,0x56,0x42,0x08,0x07,0x00,0x00,0x0F,\n0x02,0x02,0x0A,0x0F,0x00,0x00,/*\"瘠\",6108*/},{\n\n0x88,0xFE,0x22,0xEA,0xBE,0xAA,0xEB,0xAA,0xBE,0xEA,0x22,0x08,0x07,0x00,0x0B,0x06,\n0x02,0x03,0x02,0x06,0x0B,0x00,/*\"癀\",6109*/},{\n\n0x08,0x90,0xFE,0x02,0xEA,0xAA,0xFB,0xAA,0xFA,0xAA,0xEA,0x09,0x04,0x03,0x00,0x0A,\n0x06,0x0A,0x0E,0x02,0x06,0x0A,/*\"瘭\",6110*/},{\n\n0x88,0xFE,0x02,0x3E,0xAA,0xEA,0xBF,0xAA,0x6A,0x3E,0x02,0x08,0x07,0x00,0x0A,0x06,\n0x0A,0x0F,0x02,0x06,0x0B,0x00,/*\"瘰\",6111*/},{\n\n0x88,0xFE,0x02,0xBE,0x6A,0xBE,0x03,0xBE,0x6A,0xBE,0x02,0x08,0x07,0x09,0x09,0x0B,\n0x05,0x05,0x05,0x0B,0x09,0x09,/*\"癭\",6112*/},{\n\n0x08,0x90,0xFE,0xA2,0x5E,0x2A,0x5B,0x42,0x5A,0x2A,0x5A,0x09,0x04,0x03,0x00,0x09,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"瘵\",6113*/},{\n\n0x88,0xFE,0x02,0xFA,0x4A,0xBA,0x53,0xDE,0xAA,0xDA,0x42,0x08,0x07,0x00,0x0F,0x02,\n0x01,0x08,0x0A,0x0F,0x0A,0x08,/*\"癃\",6114*/},{\n\n0x88,0xFE,0x02,0xFA,0x4A,0xBA,0x13,0xAA,0xBA,0xEA,0x16,0x08,0x07,0x00,0x0F,0x02,\n0x09,0x04,0x0A,0x0C,0x02,0x0C,/*\"癮\",6115*/},{\n\n0x08,0xFE,0x82,0x96,0x4A,0x5F,0xA2,0x56,0x4A,0x9E,0x82,0x09,0x07,0x00,0x08,0x09,\n0x09,0x0A,0x05,0x04,0x02,0x00,/*\"瘳\",6116*/},{\n\n0x10,0xFE,0x8A,0xFA,0x8A,0xA2,0x2B,0xE2,0xAA,0xFA,0x8A,0x09,0x07,0x08,0x0F,0x04,\n0x02,0x01,0x06,0x08,0x0F,0x08,/*\"癍\",6117*/},{\n\n0x10,0xFE,0xEA,0xAA,0xFE,0xAA,0xEB,0x12,0xEE,0xBA,0xE2,0x09,0x07,0x04,0x02,0x0F,\n0x02,0x04,0x00,0x0B,0x06,0x0B,/*\"癩\",6118*/},{\n\n0x88,0xFE,0x22,0xEA,0x3A,0x2A,0x6F,0xAA,0x3A,0xEA,0x22,0x08,0x07,0x0C,0x01,0x0D,\n0x0B,0x0D,0x09,0x0D,0x01,0x0C,/*\"癔\",6119*/},{\n\n0x10,0xFE,0xAA,0xEA,0xAA,0xEA,0xBB,0x42,0xBA,0x8A,0xBA,0x09,0x07,0x0A,0x07,0x02,\n0x07,0x0A,0x00,0x0B,0x04,0x0B,/*\"癜\",6120*/},{\n\n0x08,0x90,0xFE,0x02,0xFA,0x4A,0x7B,0x02,0xAA,0xCE,0xAA,0x09,0x04,0x03,0x02,0x0F,\n0x09,0x0F,0x00,0x02,0x0F,0x02,/*\"癖\",6121*/},{\n\n0x08,0x90,0xFE,0x02,0xEA,0xBE,0xEB,0x02,0xEA,0xBA,0xEA,0x09,0x04,0x03,0x0A,0x07,\n0x02,0x07,0x0A,0x0B,0x06,0x0B,/*\"癲\",6122*/},{\n\n0x88,0xFE,0x02,0xBE,0xEA,0xBE,0xC3,0xBE,0xAA,0xBE,0x82,0x08,0x07,0x01,0x0F,0x0A,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"癯\",6123*/},{\n\n0x28,0xC9,0x0A,0xE8,0x00,0x12,0xA2,0xFE,0x10,0xA2,0xFE,0x04,0x04,0x02,0x02,0x00,\n0x01,0x08,0x0F,0x01,0x08,0x0F,/*\"翊\",6124*/},{\n\n0x28,0xC9,0x0A,0xE8,0x04,0x74,0x54,0xFF,0x54,0x74,0x04,0x04,0x04,0x02,0x02,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"竦\",6125*/},{\n\n0x06,0x82,0x4A,0xA6,0x3A,0x23,0x22,0x26,0xAA,0x62,0x06,0x08,0x08,0x08,0x04,0x05,\n0x02,0x02,0x01,0x00,0x00,0x00,/*\"穸\",6126*/},{\n\n0x06,0xD2,0x5A,0x56,0x52,0x53,0x52,0x56,0x5A,0x72,0x06,0x00,0x01,0x01,0x01,0x01,\n0x01,0x01,0x01,0x09,0x09,0x07,/*\"穹\",6127*/},{\n\n0x16,0xD2,0x1A,0x16,0x12,0xFB,0x12,0x16,0x1A,0xD2,0x16,0x00,0x01,0x01,0x01,0x01,\n0x07,0x09,0x09,0x09,0x09,0x0C,/*\"窀\",6128*/},{\n\n0x86,0x92,0x9A,0x96,0x92,0xB3,0xCA,0x8E,0x8A,0x8A,0x06,0x08,0x08,0x04,0x04,0x0A,\n0x0A,0x0A,0x0A,0x09,0x08,0x08,/*\"窆\",6129*/},{\n\n0x86,0xCA,0xA6,0x92,0x42,0x03,0x22,0xF2,0x26,0x2A,0xE6,0x04,0x06,0x05,0x04,0x06,\n0x08,0x06,0x01,0x08,0x08,0x07,/*\"窈\",6130*/},{\n\n0x06,0x12,0xAA,0x06,0xF2,0x03,0xF2,0x06,0xAA,0x12,0x06,0x08,0x09,0x04,0x02,0x01,\n0x00,0x07,0x08,0x08,0x09,0x0C,/*\"窕\",6131*/},{\n\n0xE6,0xAA,0xA6,0xEA,0xAA,0xBF,0xAA,0xEA,0xA6,0xAA,0xE6,0x00,0x0B,0x06,0x02,0x02,\n0x03,0x02,0x02,0x06,0x0B,0x00,/*\"竇\",6132*/},{\n\n0x06,0x0A,0xFE,0xAA,0xAA,0xFB,0xAA,0xAA,0xFE,0x0A,0x06,0x02,0x0A,0x0A,0x06,0x02,\n0x0F,0x02,0x06,0x0A,0x0A,0x02,/*\"窠\",6133*/},{\n\n0x26,0xEA,0x56,0x4A,0x56,0xD3,0x16,0x8A,0x16,0xEA,0x26,0x00,0x0F,0x05,0x05,0x0D,\n0x0F,0x00,0x03,0x08,0x0F,0x00,/*\"窬\",6134*/},{\n\n0x26,0xAA,0xAE,0xBA,0xAA,0xAF,0xAA,0xBA,0xAE,0xAA,0x26,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"窨\",6135*/},{\n\n0x46,0x4A,0xF6,0x52,0x52,0xFB,0x52,0x52,0xF6,0x4A,0x46,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"窶\",6136*/},{\n\n0xF6,0x1A,0xF6,0x52,0x8A,0xF3,0x12,0xF2,0x16,0xEA,0x06,0x07,0x00,0x0F,0x0A,0x0C,\n0x03,0x00,0x0F,0x0A,0x0C,0x01,/*\"窳\",6137*/},{\n\n0x84,0x45,0xF6,0x4C,0xA0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,/*\"衤\",6138*/},{\n\n0x84,0x45,0xF6,0x4C,0xA2,0x3E,0xC2,0x0A,0xD2,0x3E,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"衩\",6139*/},{\n\n0x45,0xF6,0xAC,0x00,0xFC,0x84,0x44,0x3F,0x44,0x84,0xFC,0x00,0x0F,0x00,0x00,0x0F,\n0x00,0x00,0x00,0x00,0x08,0x0F,/*\"衲\",6140*/},{\n\n0x84,0x45,0xF6,0xAC,0x40,0x44,0x44,0xFC,0x42,0x42,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x08,0x08,0x0F,0x08,0x08,0x00,/*\"衽\",6141*/},{\n\n0x84,0x45,0xF6,0xAC,0x00,0x90,0x8C,0xA3,0x8C,0x90,0x20,0x00,0x00,0x0F,0x00,0x00,\n0x00,0x00,0x08,0x06,0x01,0x00,/*\"衿\",6142*/},{\n\n0x84,0x45,0xF6,0xAC,0x40,0x44,0x44,0xFF,0x44,0x7C,0x40,0x00,0x00,0x0F,0x00,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"袂\",6143*/},{\n\n0x45,0xF6,0xAC,0x00,0x82,0x94,0x90,0xFF,0x90,0x94,0x82,0x00,0x0F,0x00,0x00,0x00,\n0x00,0x00,0x0F,0x00,0x00,0x00,/*\"袢\",6144*/},{\n\n0x45,0xF6,0xAC,0x00,0x86,0xBB,0xAA,0xAB,0xAA,0xBB,0x86,0x00,0x0F,0x00,0x00,0x0F,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0F,/*\"襠\",6145*/},{\n\n0x84,0x45,0xF6,0xAC,0x10,0xA8,0xA4,0xA3,0xA4,0xA8,0x10,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"袷\",6146*/},{\n\n0x84,0x45,0xF6,0xAC,0x48,0xC4,0xAB,0x92,0xAA,0xC6,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"袼\",6147*/},{\n\n0x84,0x45,0xF6,0xAC,0x00,0xFF,0x49,0xC9,0x49,0x7F,0x80,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"裉\",6148*/},{\n\n0x45,0xF6,0xAC,0x11,0xF2,0x00,0xFA,0xAA,0xFF,0xAA,0xFA,0x00,0x0F,0x00,0x08,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"褳\",6149*/},{\n\n0x84,0x45,0xF6,0xAC,0x00,0x2F,0x29,0xE9,0x29,0x2F,0x00,0x00,0x00,0x0F,0x00,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"裎\",6150*/},{\n\n0x45,0xF6,0xAC,0x00,0xD0,0x48,0xD4,0x13,0xD4,0x48,0xD0,0x00,0x0F,0x00,0x00,0x09,\n0x07,0x09,0x00,0x09,0x07,0x09,/*\"襝\",6151*/},{\n\n0x45,0xF6,0xAC,0x00,0xFF,0x15,0xFF,0xA0,0xFF,0x15,0xFF,0x00,0x0F,0x00,0x00,0x0F,\n0x08,0x07,0x0A,0x0F,0x00,0x0F,/*\"襉\",6152*/},{\n\n0x45,0xF6,0xAC,0x00,0x44,0x54,0xD4,0x7F,0xD4,0x54,0x44,0x00,0x0F,0x00,0x00,0x02,\n0x01,0x0F,0x04,0x01,0x06,0x09,/*\"裱\",6153*/},{\n\n0x45,0xF6,0xAC,0x10,0x90,0xD4,0x7F,0x54,0x58,0xD4,0x12,0x00,0x0F,0x00,0x01,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"褚\",6154*/},{\n\n0x84,0x45,0xF6,0xAC,0x80,0x5F,0xF5,0x55,0xD5,0x5F,0xC0,0x00,0x00,0x0F,0x00,0x02,\n0x09,0x04,0x02,0x09,0x08,0x07,/*\"裼\",6155*/},{\n\n0x84,0x45,0xF6,0xAC,0x00,0x7C,0xD6,0x75,0x5C,0x54,0x7C,0x00,0x00,0x0F,0x00,0x02,\n0x03,0x02,0x02,0x0F,0x02,0x02,/*\"裨\",6156*/},{\n\n0x84,0x45,0xF6,0xAC,0x00,0xFE,0xAA,0xAA,0xFA,0xAA,0xAE,0x00,0x00,0x0F,0x08,0x06,\n0x01,0x0F,0x04,0x04,0x04,0x0F,/*\"裾\",6157*/},{\n\n0x45,0xF6,0xAC,0x00,0xAA,0x92,0xAE,0x00,0xAA,0x92,0xAE,0x00,0x0F,0x00,0x08,0x0A,\n0x04,0x0B,0x00,0x0B,0x04,0x0B,/*\"裰\",6158*/},{\n\n0x84,0x45,0xF6,0xAC,0x42,0x27,0x52,0x4A,0x52,0x27,0x42,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"褡\",6159*/},{\n\n0x84,0x45,0xF6,0xAC,0x12,0xEA,0xBF,0xA0,0xAF,0xF2,0x19,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x02,0x02,0x0A,0x0F,0x00,/*\"褙\",6160*/},{\n\n0x84,0x45,0xF6,0xAC,0x10,0xFC,0x43,0x5E,0xF2,0x5E,0x40,0x00,0x00,0x0F,0x00,0x00,\n0x0F,0x02,0x01,0x0F,0x01,0x02,/*\"褓\",6161*/},{\n\n0x84,0x45,0xF6,0xAC,0x08,0xBE,0xAA,0xFF,0xAA,0xBE,0x88,0x00,0x00,0x0F,0x00,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"褸\",6162*/},{\n\n0x45,0xF6,0xAC,0x40,0xFE,0x2A,0xEA,0x2B,0xEA,0x2A,0xEE,0x00,0x0F,0x00,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"褊\",6163*/},{\n\n0x45,0xF6,0xAC,0x00,0x7F,0x55,0x77,0x5D,0x10,0x0F,0x34,0x00,0x0F,0x00,0x08,0x0F,\n0x09,0x0F,0x09,0x0F,0x09,0x0F,/*\"襤\",6164*/},{\n\n0x45,0xF6,0xAC,0xFE,0x02,0xF2,0x52,0xFF,0x55,0x15,0xB1,0x00,0x0F,0x08,0x07,0x02,\n0x09,0x06,0x02,0x07,0x09,0x0D,/*\"褫\",6165*/},{\n\n0x45,0xF6,0xAC,0x00,0xD5,0x49,0x5F,0x60,0x55,0x49,0xDF,0x00,0x0F,0x00,0x00,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"褶\",6166*/},{\n\n0x45,0xF6,0xAC,0x00,0x79,0xCF,0xF0,0x97,0xFD,0x97,0xF0,0x00,0x0F,0x00,0x00,0x08,\n0x0F,0x04,0x04,0x07,0x04,0x0E,/*\"襁\",6167*/},{\n\n0x45,0xF6,0xAC,0x00,0x4C,0x55,0x45,0xDF,0x45,0x55,0x4C,0x00,0x0F,0x00,0x00,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"襦\",6168*/},{\n\n0x45,0xF6,0xAC,0x00,0xAA,0x7F,0xAA,0xB4,0xAA,0x7F,0xAA,0x00,0x0F,0x00,0x00,0x02,\n0x02,0x0A,0x0F,0x02,0x02,0x02,/*\"襻\",6169*/},{\n\n0x02,0x02,0xE2,0x02,0x02,0xFE,0x42,0x42,0x42,0x4A,0x06,0x08,0x06,0x01,0x02,0x04,\n0x0F,0x08,0x08,0x08,0x08,0x08,/*\"疋\",6170*/},{\n\n0x21,0x11,0xED,0xB1,0xA1,0xBF,0xA9,0xA9,0xE9,0x29,0x23,0x00,0x00,0x0F,0x02,0x02,\n0x02,0x02,0x0A,0x0F,0x00,0x00,/*\"胥\",6171*/},{\n\n0xF3,0x55,0xFF,0x55,0xF3,0x00,0xFC,0xA4,0x3F,0xE4,0x0C,0x05,0x05,0x0F,0x05,0x05,\n0x04,0x0B,0x05,0x02,0x05,0x08,/*\"皸\",6172*/},{\n\n0x94,0x6E,0x45,0xCC,0x16,0xFC,0x24,0xE4,0x3F,0xE4,0x0C,0x08,0x05,0x02,0x05,0x08,\n0x07,0x08,0x05,0x02,0x05,0x08,/*\"皴\",6173*/},{\n\n0x20,0xAA,0xF2,0x2E,0x60,0x90,0x8C,0xA3,0x8C,0x90,0x20,0x01,0x08,0x0F,0x00,0x00,\n0x00,0x00,0x08,0x06,0x01,0x00,/*\"矜\",6174*/},{\n\n0x40,0x44,0x54,0x54,0xD4,0xFF,0xD4,0x54,0x54,0x44,0x40,0x04,0x04,0x02,0x01,0x00,\n0x0F,0x00,0x01,0x02,0x04,0x04,/*\"耒\",6175*/},{\n\n0x44,0x54,0xFF,0x54,0x44,0x00,0x42,0x42,0xF2,0x4A,0x46,0x02,0x01,0x0F,0x01,0x02,\n0x00,0x00,0x08,0x0F,0x00,0x00,/*\"耔\",6176*/},{\n\n0x44,0x54,0xFF,0x54,0x44,0x20,0x18,0x00,0xFF,0x08,0xB0,0x02,0x01,0x0F,0x01,0x02,\n0x08,0x08,0x04,0x02,0x01,0x00,/*\"耖\",6177*/},{\n\n0x44,0x54,0xFF,0x54,0x44,0x00,0xFE,0x92,0x92,0x92,0x9E,0x02,0x01,0x0F,0x01,0x02,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"耜\",6178*/},{\n\n0x44,0x54,0xFF,0x54,0x10,0xA8,0xA4,0xA3,0xA4,0xA8,0x10,0x02,0x01,0x0F,0x01,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"耠\",6179*/},{\n\n0x44,0x54,0xFF,0x54,0x6A,0x27,0xAA,0x21,0x2A,0x27,0x6A,0x02,0x01,0x0F,0x01,0x08,\n0x05,0x03,0x09,0x09,0x07,0x00,/*\"耮\",6180*/},{\n\n0x44,0x54,0xFF,0x54,0xF2,0x14,0xD0,0x5F,0xD0,0x14,0xF2,0x02,0x01,0x0F,0x01,0x0F,\n0x00,0x03,0x02,0x03,0x08,0x0F,/*\"耥\",6181*/},{\n\n0x44,0x54,0xFF,0x54,0x80,0xBF,0xA5,0xFF,0xA5,0xBF,0x80,0x02,0x01,0x0F,0x01,0x0F,\n0x00,0x02,0x03,0x06,0x08,0x0F,/*\"耦\",6182*/},{\n\n0x44,0x54,0xFF,0x54,0x08,0xBE,0xAA,0xFF,0xAA,0xBE,0x88,0x02,0x01,0x0F,0x01,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"耬\",6183*/},{\n\n0x44,0x54,0xFF,0x54,0x08,0xEA,0xAF,0xFA,0xAF,0xEA,0x08,0x02,0x01,0x0F,0x01,0x02,\n0x0F,0x02,0x03,0x0A,0x0F,0x02,/*\"耩\",6184*/},{\n\n0x44,0x54,0xFF,0x54,0xFF,0x11,0xF5,0x95,0x35,0x55,0xB5,0x02,0x01,0x0F,0x09,0x07,\n0x02,0x06,0x02,0x0A,0x0F,0x02,/*\"耨\",6185*/},{\n\n0x44,0x54,0xFF,0x54,0xFE,0xAA,0xFE,0x9A,0xAB,0xFE,0xAA,0x02,0x01,0x0F,0x09,0x07,\n0x04,0x0E,0x0B,0x0A,0x0A,0x0E,/*\"耱\",6186*/},{\n\n0x48,0x4A,0xAA,0xEA,0xBF,0xAA,0xAE,0xFA,0xA9,0x28,0x30,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"耋\",6187*/},{\n\n0x02,0xFE,0x52,0xFE,0x02,0x00,0x02,0x02,0xFE,0x02,0x02,0x02,0x03,0x02,0x0F,0x01,\n0x00,0x08,0x08,0x0F,0x00,0x00,/*\"耵\",6188*/},{\n\n0x02,0xFE,0x52,0xFE,0x02,0xFC,0x24,0xFF,0x24,0xFC,0x00,0x02,0x03,0x02,0x0F,0x01,\n0x0F,0x01,0x01,0x09,0x0F,0x01,/*\"聃\",6189*/},{\n\n0x02,0xFE,0x52,0xFE,0x12,0x48,0x44,0x53,0x64,0xC8,0x10,0x02,0x03,0x02,0x0F,0x01,\n0x00,0x02,0x04,0x0B,0x00,0x00,/*\"聆\",6190*/},{\n\n0x01,0xFF,0x49,0xFF,0x27,0x9A,0xA6,0xAB,0xB2,0x8A,0x36,0x02,0x03,0x02,0x0F,0x02,\n0x03,0x0A,0x0F,0x02,0x03,0x02,/*\"聹\",6191*/},{\n\n0x02,0xFE,0x52,0xFE,0x02,0x00,0x92,0x92,0xFE,0x91,0x91,0x02,0x03,0x02,0x0F,0x01,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"聒\",6192*/},{\n\n0x01,0xFF,0x49,0xFF,0x21,0xEE,0xAA,0xBF,0xAA,0xEE,0x20,0x02,0x03,0x02,0x0F,0x01,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"聵\",6193*/},{\n\n0xC8,0xAA,0xBA,0xAF,0xEA,0x8A,0xC4,0xAB,0x92,0xAE,0xC2,0x04,0x04,0x07,0x05,0x06,\n0x04,0x05,0x06,0x0F,0x02,0x02,/*\"聱\",6194*/},{\n\n0x01,0x1D,0xF5,0x55,0x5F,0x55,0x5F,0x55,0xF5,0x1D,0x01,0x04,0x04,0x05,0x05,0x05,\n0x0F,0x05,0x05,0x05,0x04,0x04,/*\"覃\",6195*/},{\n\n0x40,0x42,0xFE,0x42,0x40,0xFA,0xAA,0xAE,0xAA,0xAA,0xFA,0x00,0x00,0x0F,0x00,0x00,\n0x0B,0x06,0x02,0x02,0x06,0x0B,/*\"頇\",6196*/},{\n\n0x00,0xFE,0x12,0x12,0xF1,0x11,0xFA,0xAA,0xAE,0xAA,0xFA,0x08,0x07,0x00,0x00,0x0F,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頎\",6197*/},{\n\n0x08,0xE8,0x29,0xEA,0x08,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x08,0x07,0x00,0x07,0x02,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頏\",6198*/},{\n\n0xA4,0xA4,0xBF,0xA4,0xA4,0x00,0xFA,0xAA,0xAE,0xAA,0xFA,0x0F,0x04,0x04,0x04,0x0F,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頡\",6199*/},{\n\n0xA8,0xA4,0xA3,0xA4,0xA8,0x10,0xFA,0xAA,0xAE,0xAA,0xFA,0x0F,0x04,0x04,0x04,0x0F,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頜\",6200*/},{\n\n0x80,0x8F,0x14,0xF2,0x99,0x40,0xFA,0xAA,0xAE,0xAA,0xFA,0x04,0x03,0x08,0x0F,0x02,\n0x04,0x0B,0x06,0x02,0x06,0x0B,/*\"潁\",6201*/},{\n\n0x24,0x34,0xAD,0x66,0x24,0x94,0x00,0xFA,0xAE,0xAA,0xFA,0x09,0x09,0x04,0x02,0x05,\n0x08,0x00,0x0B,0x06,0x06,0x0B,/*\"頦\",6202*/},{\n\n0x08,0x24,0x2A,0xB1,0x62,0x04,0xFA,0xAA,0xAE,0xAA,0xFA,0x00,0x0F,0x05,0x05,0x0F,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"頷\",6203*/},{\n\n0x47,0xD5,0x57,0x50,0x57,0x55,0x47,0xFA,0xAE,0xAA,0xFA,0x00,0x01,0x01,0x09,0x09,\n0x07,0x00,0x0B,0x06,0x06,0x0B,/*\"顎\",6204*/},{\n\n0xAE,0xA8,0xA8,0xEF,0xA8,0xA8,0xAE,0x00,0xFA,0xAE,0xFA,0x0F,0x00,0x07,0x00,0x07,\n0x08,0x0F,0x00,0x0B,0x06,0x0B,/*\"顓\",6205*/},{\n\n0x51,0xDF,0x55,0xD5,0x7F,0xC9,0x40,0xFD,0x57,0x55,0xFD,0x04,0x07,0x05,0x0F,0x05,\n0x0F,0x02,0x09,0x05,0x05,0x09,/*\"顳\",6206*/},{\n\n0xE2,0xAF,0x2A,0xFA,0xAA,0x2F,0xE2,0x00,0xFA,0xAE,0xFA,0x0F,0x02,0x01,0x0F,0x02,\n0x09,0x0F,0x00,0x0B,0x06,0x0B,/*\"顢\",6207*/},{\n\n0xB0,0x5B,0xB5,0x05,0xB5,0x5B,0xB0,0x00,0xFD,0xAB,0xF9,0x0A,0x06,0x02,0x0F,0x02,\n0x06,0x0A,0x00,0x0B,0x06,0x0B,/*\"顙\",6208*/},{\n\n0x40,0xDF,0x55,0x75,0x55,0xDF,0x40,0xFD,0x57,0x55,0xFD,0x08,0x05,0x09,0x0F,0x01,\n0x05,0x08,0x09,0x05,0x05,0x09,/*\"顥\",6209*/},{\n\n0x4C,0x55,0x45,0xDF,0x45,0x55,0x4C,0x00,0xFD,0xAB,0xF9,0x0F,0x01,0x07,0x01,0x07,\n0x09,0x0F,0x00,0x0B,0x06,0x0B,/*\"顬\",6210*/},{\n\n0x54,0x4F,0xE4,0x5F,0x55,0xE4,0x5D,0x77,0xDD,0x35,0x5D,0x04,0x04,0x07,0x05,0x07,\n0x05,0x0D,0x05,0x07,0x04,0x04,/*\"顰\",6211*/},{\n\n0x00,0xF8,0x08,0x08,0x08,0xEF,0x8A,0x8A,0x8A,0x8A,0x18,0x08,0x07,0x01,0x01,0x01,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"虍\",6212*/},{\n\n0x00,0xFC,0x24,0x24,0x24,0x3F,0xD5,0x55,0x55,0x45,0x6C,0x08,0x07,0x09,0x09,0x0B,\n0x05,0x05,0x05,0x0B,0x09,0x09,/*\"虔\",6213*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFC,0x00,0x80,0x40,0xFF,0x04,0x04,0x03,0x02,0x07,\n0x00,0x01,0x01,0x00,0x00,0x0F,/*\"虯\",6214*/},{\n\n0x78,0x48,0xFF,0x48,0x9A,0xD5,0x98,0xFF,0x80,0xDA,0xB5,0x04,0x04,0x03,0x02,0x08,\n0x07,0x02,0x04,0x03,0x04,0x0E,/*\"蟣\",6215*/},{\n\n0xE2,0x3A,0xAA,0xAF,0xAA,0xFA,0xAA,0xAF,0xAA,0x3A,0xE2,0x08,0x08,0x0B,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0B,0x08,0x0C,/*\"蠆\",6216*/},{\n\n0x02,0xFE,0x02,0xFE,0x02,0x3C,0x24,0xFF,0x24,0xBC,0x00,0x08,0x07,0x00,0x07,0x08,\n0x0A,0x0A,0x09,0x09,0x0B,0x0C,/*\"虺\",6217*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x08,0x24,0x27,0xA4,0x64,0x04,0x04,0x04,0x03,0x02,0x07,\n0x00,0x06,0x09,0x08,0x08,0x0E,/*\"虼\",6218*/},{\n\n0xF8,0x88,0xFF,0x88,0xF8,0x00,0x08,0xF9,0x0A,0x08,0x08,0x08,0x08,0x07,0x04,0x0E,\n0x00,0x00,0x0F,0x08,0x08,0x08,/*\"虻\",6219*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x40,0x48,0xFF,0x48,0x48,0x40,0x04,0x04,0x03,0x02,0x0B,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"蚨\",6220*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFF,0x10,0xFF,0x20,0x10,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x04,0x07,0x08,0x0E,/*\"蚍\",6221*/},{\n\n0xF8,0x88,0xFF,0x88,0xF8,0x00,0xFC,0x84,0x7F,0x84,0xFC,0x08,0x08,0x07,0x04,0x0E,\n0x00,0x0F,0x00,0x00,0x08,0x0F,/*\"蚋\",6222*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFE,0xAA,0xAA,0xFE,0x00,0x04,0x04,0x03,0x02,0x07,\n0x08,0x06,0x01,0x07,0x08,0x0C,/*\"蜆\",6223*/},{\n\n0x78,0x48,0xFF,0x48,0x62,0xBA,0xAA,0xAB,0xAA,0x3A,0x62,0x04,0x04,0x03,0x02,0x0A,\n0x05,0x0B,0x0E,0x02,0x05,0x08,/*\"蠔\",6224*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x08,0xE4,0x03,0x04,0xE8,0x10,0x04,0x04,0x03,0x02,0x07,\n0x08,0x07,0x00,0x00,0x0F,0x00,/*\"蚧\",6225*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x20,0x18,0x87,0x60,0x07,0x18,0x04,0x04,0x03,0x02,0x07,\n0x00,0x06,0x05,0x04,0x05,0x0E,/*\"蚣\",6226*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x12,0x24,0x00,0xFF,0x80,0x04,0x04,0x03,0x02,0x07,\n0x00,0x01,0x01,0x01,0x0F,0x00,/*\"蚪\",6227*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xF2,0x92,0x9E,0x00,0xFF,0x04,0x04,0x03,0x02,0x07,\n0x00,0x08,0x08,0x07,0x00,0x0F,/*\"蚓\",6228*/},{\n\n0x10,0x96,0x94,0x94,0x94,0xDF,0x94,0x94,0x94,0x96,0x10,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蚩\",6229*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x04,0xFF,0x44,0x44,0xFF,0x04,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"蚶\",6230*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xC8,0x48,0x7F,0x48,0xC8,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"蛄\",6231*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xF2,0x12,0xF2,0xFE,0x02,0x04,0x04,0x03,0x02,0x07,\n0x00,0x03,0x09,0x09,0x0F,0x00,/*\"蚵\",6232*/},{\n\n0x78,0x48,0xFF,0x48,0xFF,0x01,0xF5,0x5F,0xF5,0x5F,0xF5,0x04,0x04,0x03,0x06,0x03,\n0x0F,0x01,0x05,0x07,0x09,0x0F,/*\"蠣\",6233*/},{\n\n0xF8,0x88,0xFF,0x88,0xF8,0x00,0xF8,0x48,0xFF,0x48,0xF8,0x08,0x08,0x07,0x04,0x0E,\n0x00,0x0F,0x04,0x07,0x04,0x0F,/*\"蚰\",6234*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFC,0x24,0xFF,0x24,0xFC,0x04,0x04,0x03,0x02,0x07,\n0x01,0x0F,0x01,0x01,0x09,0x0F,/*\"蚺\",6235*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x08,0x07,0xFC,0x24,0x24,0x04,0x04,0x04,0x03,0x02,0x07,\n0x00,0x00,0x0F,0x01,0x01,0x01,/*\"蚱\",6236*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFE,0x22,0x22,0xE1,0x21,0x04,0x04,0x03,0x02,0x07,\n0x08,0x0F,0x08,0x08,0x0F,0x08,/*\"蚯\",6237*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x10,0x4C,0x53,0x64,0xC8,0x10,0x04,0x04,0x03,0x02,0x07,\n0x00,0x02,0x04,0x0B,0x00,0x00,/*\"蛉\",6238*/},{\n\n0x78,0x48,0xFF,0x49,0xBF,0xA5,0xFF,0x91,0xBE,0xA2,0xBE,0x04,0x04,0x03,0x02,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"蟶\",6239*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0xE7,0x30,0x08,0xFF,0x08,0xF8,0x04,0x04,0x03,0x02,0x07,\n0x02,0x0B,0x06,0x01,0x08,0x0F,/*\"蚴\",6240*/},{\n\n0x10,0x91,0x8F,0x89,0xA0,0xDF,0x85,0x89,0x9F,0xA0,0x30,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蛩\",6241*/},{\n\n0x78,0x48,0xFF,0x48,0x80,0x74,0x84,0xFF,0x84,0x74,0x84,0x04,0x04,0x03,0x02,0x08,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"蛺\",6242*/},{\n\n0x78,0x48,0xFF,0x48,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x04,0x04,0x03,0x02,0x08,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"蟯\",6243*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x32,0x2A,0xE6,0x22,0x32,0x04,0x04,0x03,0x02,0x07,\n0x08,0x09,0x09,0x0F,0x09,0x09,/*\"蛭\",6244*/},{\n\n0x78,0x48,0xFF,0x48,0xFE,0xA5,0xBC,0x12,0xFE,0x12,0xF2,0x04,0x04,0x03,0x02,0x0F,\n0x04,0x07,0x00,0x0F,0x02,0x03,/*\"螄\",6245*/},{\n\n0x78,0x48,0xFF,0x48,0xFC,0x44,0xFF,0x44,0xFF,0x44,0xFC,0x04,0x04,0x03,0x02,0x0F,\n0x04,0x07,0x04,0x07,0x04,0x0F,/*\"蛐\",6246*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0xB2,0x2E,0xE0,0x12,0xFE,0x11,0x04,0x04,0x03,0x02,0x03,\n0x09,0x06,0x09,0x0A,0x0B,0x0A,/*\"蜓\",6247*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x92,0x92,0xFE,0x91,0x91,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"蛞\",6248*/},{\n\n0xF0,0x90,0xFF,0x90,0x48,0x7A,0x86,0x7B,0x06,0xFA,0x56,0x08,0x08,0x07,0x04,0x06,\n0x08,0x07,0x05,0x05,0x0F,0x00,/*\"蠐\",6249*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x40,0x24,0xD5,0x06,0xD4,0x24,0x04,0x04,0x03,0x02,0x07,\n0x00,0x08,0x05,0x02,0x05,0x08,/*\"蛟\",6250*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x25,0x26,0xFC,0x26,0x25,0x04,0x04,0x03,0x02,0x07,\n0x00,0x01,0x01,0x0F,0x01,0x01,/*\"蛘\",6251*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x80,0x6C,0x4A,0xF9,0x48,0x4C,0x04,0x04,0x03,0x02,0x07,\n0x02,0x02,0x02,0x0F,0x02,0x02,/*\"蛑\",6252*/},{\n\n0x00,0xFF,0x05,0xBD,0xA5,0x85,0xCD,0x95,0x95,0xAD,0x25,0x08,0x07,0x08,0x0B,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0B,0x0C,/*\"蜃\",6253*/},{\n\n0x0A,0xAA,0xBF,0x8A,0xA0,0xDE,0x8A,0x8A,0xB9,0x89,0x08,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蜇\",6254*/},{\n\n0xF8,0x88,0xFF,0x88,0xF8,0x00,0xF2,0x54,0x5F,0x54,0xF2,0x08,0x08,0x07,0x04,0x0E,\n0x00,0x0F,0x01,0x01,0x09,0x0F,/*\"蛸\",6255*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x2F,0x29,0xE9,0x29,0x2F,0x00,0x04,0x04,0x03,0x02,0x0B,\n0x05,0x03,0x01,0x03,0x05,0x09,/*\"蜈\",6256*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x92,0xFE,0x91,0xFC,0x00,0xFF,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x00,0x01,0x08,0x0F,/*\"蜊\",6257*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x48,0x54,0xF3,0x54,0x48,0x04,0x04,0x03,0x02,0x07,\n0x04,0x03,0x08,0x0F,0x01,0x06,/*\"蜍\",6258*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x2A,0x32,0x26,0xAA,0x71,0x2D,0x04,0x04,0x03,0x02,0x07,\n0x01,0x01,0x09,0x0F,0x01,0x01,/*\"蜉\",6259*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x45,0xD6,0x7C,0xD6,0x55,0x54,0x04,0x04,0x03,0x02,0x0B,\n0x06,0x01,0x00,0x07,0x08,0x0C,/*\"蜣\",6260*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x22,0xEA,0xAA,0xBF,0xEA,0x22,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x02,0x0A,0x0F,0x00,/*\"蜻\",6261*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x04,0xFF,0x54,0x54,0xFF,0x04,0x04,0x04,0x03,0x02,0x07,\n0x09,0x05,0x01,0x01,0x05,0x09,/*\"蜞\",6262*/},{\n\n0x78,0x48,0xFF,0x48,0x28,0xFF,0x48,0xFE,0x12,0xF2,0x11,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x03,0x00,0x0F,0x00,/*\"蜥\",6263*/},{\n\n0x78,0x48,0xFF,0x48,0xF4,0x94,0xF4,0x04,0xFF,0x84,0x65,0x04,0x04,0x03,0x02,0x04,\n0x04,0x0A,0x04,0x03,0x05,0x0E,/*\"蜮\",6264*/},{\n\n0x22,0xAA,0xAA,0xFF,0x80,0xC0,0x80,0xFF,0xAA,0xAA,0x22,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蜚\",6265*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x5F,0x55,0xFF,0x55,0x5F,0x04,0x04,0x03,0x02,0x07,\n0x04,0x02,0x01,0x0F,0x01,0x02,/*\"蜾\",6266*/},{\n\n0x78,0x48,0xFF,0x48,0xFF,0xA9,0xE9,0x1F,0xE9,0x0B,0xFF,0x04,0x04,0x03,0x02,0x0F,\n0x0A,0x0A,0x0C,0x0B,0x0D,0x0F,/*\"蟈\",6267*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x80,0x5F,0xF5,0x55,0xD5,0xDF,0x04,0x04,0x03,0x02,0x07,\n0x02,0x09,0x04,0x0B,0x08,0x07,/*\"蜴\",6268*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x7C,0xD6,0x7D,0x54,0x7C,0x04,0x04,0x03,0x02,0x07,\n0x02,0x03,0x02,0x0F,0x02,0x02,/*\"蜱\",6269*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFF,0xA9,0xBD,0xA9,0xFF,0x04,0x04,0x03,0x02,0x07,\n0x08,0x07,0x03,0x0A,0x0B,0x0F,/*\"蜩\",6270*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x55,0xB4,0x9F,0x94,0xB5,0x50,0x04,0x04,0x03,0x02,0x07,\n0x00,0x07,0x08,0x0A,0x0B,0x0C,/*\"蜷\",6271*/},{\n\n0x78,0x48,0xFF,0xC8,0x66,0x9A,0xF2,0x03,0xF2,0x92,0xF6,0x04,0x04,0x03,0x02,0x08,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"蜿\",6272*/},{\n\n0x78,0x48,0xFF,0x48,0xFD,0x56,0x7C,0x00,0xFE,0x32,0xCE,0x04,0x04,0x03,0x02,0x0F,\n0x05,0x02,0x04,0x0F,0x02,0x01,/*\"螂\",6273*/},{\n\n0x78,0x48,0xFF,0x48,0xF8,0x89,0xA9,0xBD,0x8B,0x89,0x88,0x04,0x04,0x03,0x0A,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"蜢\",6274*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0xA2,0xEA,0xBA,0xAF,0xEA,0xA2,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x0A,0x0A,0x0F,0x00,/*\"蝽\",6275*/},{\n\n0x78,0x48,0xFF,0x4C,0x72,0x2F,0x34,0xA2,0x34,0x2F,0x74,0x04,0x04,0x03,0x02,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"蠑\",6276*/},{\n\n0x78,0x48,0xFF,0x48,0xFA,0x0A,0x5A,0xEF,0x5A,0x0A,0xFA,0x04,0x04,0x03,0x02,0x0F,\n0x01,0x01,0x07,0x01,0x09,0x0F,/*\"蝻\",6277*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xDD,0x55,0xD5,0x55,0xDD,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x05,0x07,0x05,0x0F,/*\"蝠\",6278*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0xAA,0xA6,0xF3,0xA6,0xAA,0x92,0x04,0x04,0x03,0x02,0x07,\n0x08,0x0A,0x0F,0x0A,0x0A,0x08,/*\"蝰\",6279*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x92,0xFE,0x53,0x24,0xFF,0x80,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x01,0x01,0x0F,0x00,/*\"蝌\",6280*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x02,0x7D,0xD5,0x55,0x7D,0x01,0x04,0x04,0x03,0x02,0x07,\n0x0A,0x0B,0x05,0x05,0x0B,0x08,/*\"蝮\",6281*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0xBC,0xAA,0xFF,0xA0,0xAA,0xBE,0x04,0x04,0x03,0x02,0x03,\n0x08,0x09,0x06,0x04,0x0A,0x09,/*\"螋\",6282*/},{\n\n0x78,0x48,0xFF,0x48,0xE8,0xA4,0xEA,0x09,0xCA,0x04,0xE8,0x04,0x04,0x03,0x02,0x0F,\n0x02,0x0F,0x00,0x03,0x08,0x0F,/*\"蝓\",6283*/},{\n\n0x78,0x48,0xFF,0x48,0x08,0xF9,0x4A,0xC8,0x27,0xA4,0x64,0x04,0x04,0x03,0x0A,0x04,\n0x0B,0x08,0x07,0x09,0x0F,0x01,/*\"蝣\",6284*/},{\n\n0x78,0x48,0xFF,0x48,0x88,0xBE,0xAA,0xFF,0xAA,0xBE,0x88,0x04,0x04,0x03,0x02,0x08,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"螻\",6285*/},{\n\n0x78,0x48,0xFF,0x48,0xF4,0x55,0x3E,0x14,0x7E,0x55,0xF4,0x04,0x04,0x03,0x02,0x0F,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"蝤\",6286*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x80,0xFE,0x2A,0xEB,0x2A,0xEE,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x01,0x07,0x09,0x0F,/*\"蝙\",6287*/},{\n\n0x28,0x99,0xAB,0xBD,0x8B,0xD8,0xA4,0x97,0x8A,0x96,0x22,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"蝥\",6288*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0xA0,0x6A,0xBA,0xAF,0xEA,0xA2,0x04,0x04,0x03,0x02,0x03,\n0x00,0x0A,0x06,0x0F,0x06,0x0A,/*\"螓\",6289*/},{\n\n0x48,0xAA,0xBA,0xAF,0xEA,0xCA,0xC4,0xAB,0x92,0xAE,0x42,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"螯\",6290*/},{\n\n0x78,0x48,0xFF,0x48,0xE2,0xAF,0x2A,0xFA,0xAA,0x2F,0xE2,0x04,0x04,0x03,0x02,0x0F,\n0x02,0x01,0x0F,0x02,0x09,0x0F,/*\"蟎\",6291*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x52,0xB7,0x1A,0x12,0xB7,0x5A,0x04,0x04,0x03,0x02,0x07,\n0x09,0x07,0x01,0x01,0x0F,0x01,/*\"蟒\",6292*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFA,0xAF,0xAA,0xAF,0xFA,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0A,0x06,0x03,0x06,0x0A,/*\"蟆\",6293*/},{\n\n0x78,0x48,0xFF,0x48,0xFE,0x02,0xFA,0xAA,0xAE,0xAA,0xFA,0x04,0x04,0x03,0x0A,0x07,\n0x04,0x02,0x08,0x0F,0x02,0x04,/*\"螈\",6294*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFE,0xAA,0xAB,0xAA,0xFE,0x04,0x04,0x03,0x02,0x07,\n0x04,0x02,0x0C,0x09,0x0C,0x02,/*\"螅\",6295*/},{\n\n0x78,0x48,0xFF,0x48,0xBA,0xA2,0xB6,0xEB,0xB6,0xA2,0xBA,0x04,0x04,0x03,0x02,0x0F,\n0x00,0x06,0x05,0x06,0x08,0x0F,/*\"螭\",6296*/},{\n\n0x78,0x48,0xFF,0x48,0xFE,0x22,0xAA,0xFF,0xAA,0xFA,0x22,0x04,0x04,0x03,0x0A,0x07,\n0x00,0x0E,0x0B,0x0A,0x0E,0x00,/*\"螗\",6297*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xB2,0x96,0xDB,0x96,0xB2,0x04,0x04,0x03,0x02,0x07,\n0x00,0x08,0x07,0x02,0x0A,0x0E,/*\"螃\",6298*/},{\n\n0x28,0xCA,0xBA,0x8F,0xFA,0xCA,0xD4,0xAB,0x92,0xAE,0x42,0x08,0x0B,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0B,0x0C,/*\"螫\",6299*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xEA,0xAF,0xFA,0xAF,0xEA,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0B,0x06,0x03,0x06,0x0B,/*\"蟥\",6300*/},{\n\n0x78,0x48,0xFF,0x48,0xFA,0xAA,0xFF,0xAA,0xFF,0xAA,0xFA,0x04,0x04,0x03,0x02,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"螬\",6301*/},{\n\n0x78,0x48,0xFF,0x48,0x7D,0x15,0x5F,0x55,0x5F,0x55,0x1D,0x04,0x04,0x03,0x02,0x0B,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"螵\",6302*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0x0D,0xF4,0x97,0xF4,0x0D,0x04,0x04,0x03,0x02,0x07,\n0x00,0x08,0x0A,0x0F,0x0A,0x08,/*\"螳\",6303*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x52,0xB6,0x12,0x7E,0x31,0x55,0x04,0x04,0x03,0x0A,0x07,\n0x00,0x06,0x09,0x0C,0x01,0x06,/*\"蟋\",6304*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x04,0xBA,0x6B,0xBA,0x2E,0xB8,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0A,0x05,0x0A,0x0F,0x02,/*\"蟓\",6305*/},{\n\n0x90,0x94,0xD2,0x97,0xAA,0x4A,0x9A,0xAA,0xD6,0x90,0x90,0x0B,0x0A,0x0F,0x0A,0x0F,\n0x00,0x0B,0x0A,0x0F,0x0A,0x0F,/*\"螽\",6306*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x08,0xFA,0xAE,0xAB,0xAE,0xFA,0x04,0x04,0x03,0x02,0x07,\n0x02,0x02,0x02,0x0F,0x02,0x02,/*\"蟑\",6307*/},{\n\n0x78,0x48,0xFF,0x48,0x7A,0x22,0xDA,0xB7,0xDA,0x22,0x52,0x04,0x04,0x03,0x02,0x03,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"蟀\",6308*/},{\n\n0xA8,0xA8,0xE9,0x99,0x8B,0x2D,0xBD,0x8B,0xC9,0x88,0x98,0x0B,0x0A,0x0F,0x0A,0x0F,\n0x00,0x0B,0x0A,0x0F,0x0A,0x0F,/*\"蟊\",6309*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xEA,0xAF,0xEA,0x44,0x33,0x04,0x04,0x03,0x02,0x07,\n0x08,0x0A,0x04,0x0E,0x04,0x03,/*\"蟛\",6310*/},{\n\n0x78,0x48,0xFF,0x48,0x82,0xFA,0xAA,0xFF,0xAA,0xFA,0x82,0x04,0x04,0x03,0x02,0x08,\n0x04,0x0D,0x0A,0x0C,0x02,0x0C,/*\"蟪\",6311*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x52,0xB6,0x9A,0xBE,0x99,0xB5,0x04,0x04,0x03,0x02,0x07,\n0x00,0x0F,0x0A,0x0F,0x0A,0x0F,/*\"蟠\",6312*/},{\n\n0x78,0x48,0xFF,0x48,0xA2,0xEB,0xAA,0xFE,0xAA,0xEB,0xA2,0x04,0x04,0x03,0x02,0x00,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"蟮\",6313*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x12,0xFA,0x57,0xFA,0x57,0x52,0x04,0x04,0x03,0x02,0x07,\n0x09,0x0B,0x05,0x05,0x0B,0x09,/*\"蠖\",6314*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x9A,0x6F,0xAA,0x2A,0xAF,0x5A,0x04,0x04,0x03,0x02,0x07,\n0x0A,0x05,0x0A,0x0F,0x02,0x04,/*\"蠓\",6315*/},{\n\n0x78,0x48,0xFF,0x48,0x78,0x00,0xFE,0x15,0xAD,0xB7,0xAC,0x04,0x04,0x03,0x02,0x07,\n0x08,0x07,0x00,0x0E,0x0A,0x0E,/*\"蟾\",6316*/},{\n\n0x78,0x48,0xFF,0x48,0xFE,0xAA,0xFE,0xAB,0xFA,0xAE,0xEA,0x04,0x04,0x0B,0x06,0x0B,\n0x06,0x0F,0x02,0x0F,0x06,0x0B,/*\"蠊\",6317*/},{\n\n0x78,0x48,0xFF,0x48,0xBA,0xAF,0xBA,0xEA,0xBA,0xEF,0xBA,0x04,0x04,0x03,0x0A,0x07,\n0x02,0x04,0x0B,0x04,0x0A,0x0C,/*\"蠛\",6318*/},{\n\n0x84,0xD4,0xD6,0xCD,0xAD,0x55,0xE5,0x95,0xA7,0xD4,0xC0,0x0B,0x0A,0x0F,0x0A,0x0B,\n0x00,0x0B,0x0A,0x0F,0x0A,0x0B,/*\"蠡\",6319*/},{\n\n0x98,0xAA,0xEA,0xBA,0xAA,0xAF,0xAA,0xAA,0xEA,0x8A,0x98,0x0B,0x0A,0x0F,0x0A,0x0B,\n0x00,0x0B,0x0A,0x0F,0x0A,0x0B,/*\"蠹\",6320*/},{\n\n0x78,0x48,0xFF,0xC8,0x5F,0xF5,0x5F,0x40,0xFF,0x55,0x5F,0x04,0x04,0x03,0x02,0x08,\n0x0B,0x05,0x05,0x05,0x0B,0x09,/*\"蠼\",6321*/},{\n\n0x50,0x48,0x47,0x44,0x44,0xFC,0x44,0x44,0x44,0x44,0x40,0x00,0x0F,0x08,0x08,0x08,\n0x0F,0x08,0x08,0x08,0x0F,0x00,/*\"缶\",6322*/},{\n\n0x00,0x5F,0xB5,0xF5,0xDF,0x80,0xDF,0xB5,0xB5,0x5F,0x00,0x02,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0E,0x02,/*\"罌\",6323*/},{\n\n0x82,0x7A,0xAA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x02,0x06,0x0B,0x00,/*\"簀\",6361*/},{\n\n0x04,0xF3,0x12,0x56,0xD2,0x54,0xF3,0x52,0xD6,0x52,0x12,0x00,0x0F,0x08,0x09,0x0C,\n0x0B,0x09,0x0B,0x0C,0x09,0x08,/*\"篋\",6362*/},{\n\n0x24,0x23,0xAA,0xAE,0xEA,0xBC,0xAB,0xB2,0xAE,0xA2,0x22,0x01,0x01,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x00,/*\"箸\",6363*/},{\n\n0x94,0x93,0x96,0xBA,0xD2,0x94,0x93,0xBA,0x96,0x92,0x92,0x04,0x02,0x0F,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"箬\",6364*/},{\n\n0x24,0x23,0xF6,0xAA,0x22,0xF0,0x24,0x23,0x26,0xFA,0x22,0x01,0x09,0x0F,0x00,0x00,\n0x0F,0x09,0x09,0x09,0x0F,0x00,/*\"箝\",6365*/},{\n\n0x14,0x13,0xFA,0x96,0x3A,0x6C,0xBB,0x2A,0xBE,0x6A,0x3A,0x01,0x09,0x0F,0x00,0x04,\n0x05,0x05,0x0F,0x05,0x05,0x04,/*\"籜\",6366*/},{\n\n0x04,0xFB,0xAA,0xAE,0xAA,0xFC,0xAB,0xAA,0xAE,0xFA,0x02,0x02,0x0A,0x06,0x02,0x02,\n0x02,0x02,0x02,0x0E,0x02,0x02,/*\"箅\",6367*/},{\n\n0x04,0x3B,0xEA,0xAE,0xBA,0xE4,0xBB,0xAA,0xEE,0x3A,0x02,0x02,0x02,0x03,0x02,0x02,\n0x0F,0x02,0x02,0x03,0x02,0x02,/*\"簞\",6368*/},{\n\n0x34,0x13,0x52,0x36,0x12,0x1C,0x13,0x32,0x56,0x12,0x32,0x08,0x09,0x09,0x09,0x09,\n0x0F,0x09,0x09,0x09,0x09,0x08,/*\"箜\",6369*/},{\n\n0x34,0x93,0x72,0x56,0xD2,0x1C,0xD3,0x52,0x56,0xD2,0x32,0x09,0x08,0x05,0x02,0x01,\n0x00,0x07,0x08,0x0A,0x0B,0x0C,/*\"箢\",6370*/},{\n\n0x24,0x23,0xAA,0xAE,0xAA,0xFC,0xAB,0xAA,0xFE,0x22,0x22,0x08,0x07,0x02,0x0E,0x00,\n0x0F,0x00,0x0E,0x02,0x0F,0x00,/*\"簫\",6371*/},{\n\n0x04,0xF3,0x12,0x56,0x52,0x54,0x13,0xFA,0x16,0xDA,0x12,0x08,0x07,0x00,0x07,0x05,\n0x07,0x08,0x04,0x03,0x04,0x0E,/*\"箴\",6372*/},{\n\n0x24,0xE3,0xBA,0xAE,0xAA,0xBC,0xAB,0xAA,0xBE,0xE2,0x22,0x00,0x0B,0x06,0x02,0x02,\n0x02,0x02,0x02,0x06,0x0B,0x00,/*\"簣\",6373*/},{\n\n0x84,0xFB,0xAE,0xAA,0xAE,0xAC,0xAB,0xAA,0xAE,0xFA,0x82,0x08,0x0A,0x0A,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0A,0x0A,0x08,/*\"篁\",6374*/},{\n\n0x84,0xE3,0x1A,0x26,0x22,0xE8,0xAC,0xAB,0xBA,0xA6,0x22,0x00,0x0F,0x00,0x02,0x0B,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"篌\",6375*/},{\n\n0x22,0xE9,0xAB,0xBD,0xA9,0xEA,0xA9,0xBD,0xAB,0xE9,0x21,0x02,0x0F,0x02,0x02,0x02,\n0x03,0x02,0x02,0x0A,0x0F,0x02,/*\"篝\",6376*/},{\n\n0x04,0xFB,0x2A,0xAE,0xAA,0xFC,0x0B,0xFA,0xAE,0xAA,0x2A,0x00,0x0F,0x0A,0x0A,0x0A,\n0x0F,0x08,0x0F,0x0A,0x0A,0x0A,/*\"篚\",6377*/},{\n\n0x0C,0xEB,0xAA,0xAE,0xFA,0xAC,0xFB,0xAA,0xAE,0xEA,0x0A,0x0A,0x0A,0x0A,0x06,0x02,\n0x0F,0x02,0x06,0x0A,0x0A,0x0A,/*\"篥\",6378*/},{\n\n0x04,0xFB,0x8A,0xDE,0xAA,0xAC,0xAB,0xDA,0x8E,0xFA,0x02,0x00,0x0F,0x0A,0x0A,0x0A,\n0x00,0x07,0x0A,0x0A,0x09,0x0C,/*\"篦\",6379*/},{\n\n0x04,0xF3,0x0A,0xEE,0xAA,0xAC,0xFB,0xAA,0x6E,0xAA,0x62,0x08,0x07,0x08,0x07,0x08,\n0x06,0x02,0x03,0x07,0x09,0x0C,/*\"篪\",6380*/},{\n\n0x04,0xD3,0x56,0xFA,0x52,0xD4,0x43,0x3A,0x96,0x12,0x72,0x08,0x05,0x03,0x0F,0x03,\n0x05,0x08,0x06,0x01,0x06,0x08,/*\"簌\",6381*/},{\n\n0x04,0xBB,0xAA,0xAE,0xBA,0xEC,0xBB,0xEA,0xAE,0xBA,0x82,0x08,0x07,0x02,0x04,0x00,\n0x09,0x0A,0x04,0x0A,0x09,0x0C,/*\"篾\",6382*/},{\n\n0xF4,0x0B,0x02,0xF6,0x5A,0x54,0x53,0xF2,0x06,0x0A,0xFA,0x09,0x09,0x08,0x05,0x03,\n0x01,0x07,0x09,0x08,0x09,0x0D,/*\"篼\",6383*/},{\n\n0x04,0xFB,0xAA,0xAE,0xFA,0xAC,0xAB,0xFA,0xAE,0xEA,0x0A,0x08,0x07,0x00,0x0F,0x0A,\n0x0A,0x00,0x07,0x0A,0x0A,0x0D,/*\"簏\",6384*/},{\n\n0xFA,0x51,0xEB,0x41,0x51,0xEA,0x01,0xF9,0x4B,0xC9,0x45,0x0F,0x0D,0x0A,0x08,0x0D,\n0x0A,0x08,0x07,0x00,0x0F,0x00,/*\"籪\",6385*/},{\n\n0x02,0x01,0xFD,0x57,0x55,0x56,0xD5,0x55,0x7F,0x81,0x01,0x08,0x0E,0x0B,0x0B,0x0E,\n0x0A,0x0E,0x0B,0x0B,0x0E,0x0A,/*\"簋\",6386*/},{\n\n0x0C,0xEB,0xAA,0xAE,0xFA,0xAC,0xFB,0xAA,0xAE,0xEA,0x0A,0x04,0x04,0x07,0x04,0x04,\n0x0D,0x06,0x04,0x07,0x04,0x04,/*\"簟\",6387*/},{\n\n0xB4,0x6B,0x3A,0xEE,0xAA,0x04,0xB3,0x6A,0x3E,0xEA,0xAA,0x00,0x0F,0x09,0x09,0x09,\n0x0B,0x0D,0x09,0x09,0x0F,0x00,/*\"簪\",6388*/},{\n\n0xA4,0x4B,0xAE,0x9A,0xA2,0xA4,0xAB,0x92,0xB6,0x4A,0xA2,0x08,0x08,0x0B,0x0E,0x0A,\n0x0A,0x0A,0x0E,0x0B,0x08,0x08,/*\"簦\",6389*/},{\n\n0x0A,0xFD,0xAB,0xFD,0x09,0xFA,0x49,0xC9,0x7F,0xC9,0x19,0x0A,0x07,0x02,0x07,0x0A,\n0x07,0x08,0x05,0x02,0x05,0x08,/*\"簸\",6390*/},{\n\n0xEA,0xA9,0xFD,0xAB,0xE9,0x12,0xED,0xA9,0xAB,0xB9,0xE1,0x04,0x02,0x0F,0x02,0x04,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"籟\",6391*/},{\n\n0x12,0x11,0xFD,0x93,0xB9,0xAA,0x95,0xA9,0x9B,0xA9,0xB9,0x01,0x09,0x0F,0x00,0x0F,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x0F,/*\"籀\",6392*/},{\n\n0x00,0xFE,0x92,0x91,0x80,0xFF,0x80,0x92,0x92,0xFE,0x00,0x08,0x08,0x04,0x02,0x01,\n0x00,0x01,0x02,0x04,0x08,0x08,/*\"臾\",6393*/},{\n\n0x00,0x3E,0x2A,0xEA,0x29,0x20,0x2A,0xEA,0x2A,0x3E,0x00,0x01,0x09,0x05,0x03,0x01,\n0x01,0x01,0x0F,0x01,0x01,0x01,/*\"舁\",6394*/},{\n\n0x20,0xA2,0x6A,0xBA,0xAE,0x2B,0xAA,0xAA,0xEA,0xA2,0x20,0x01,0x00,0x0F,0x0A,0x0A,\n0x08,0x0A,0x0A,0x0F,0x00,0x01,/*\"舂\",6395*/},{\n\n0x00,0xBE,0xEA,0xAA,0xA9,0xA0,0xAA,0xAA,0xAA,0xBE,0x80,0x09,0x06,0x00,0x06,0x00,\n0x06,0x00,0x06,0x08,0x08,0x07,/*\"舄\",6396*/},{\n\n0x00,0xFE,0xAA,0xAA,0xAB,0xAA,0xAA,0xAA,0xAA,0xFE,0x00,0x0A,0x0A,0x06,0x02,0x02,\n0x0F,0x02,0x02,0x06,0x0A,0x0A,/*\"臬\",6397*/},{\n\n0xF8,0x0C,0xFB,0x08,0xF8,0x08,0xF8,0x22,0xFE,0x22,0xFE,0x07,0x04,0x07,0x04,0x03,\n0x02,0x03,0x0A,0x0F,0x08,0x0F,/*\"衄\",6398*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x00,0x02,0x02,0xFE,0x02,0x02,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x08,0x08,0x0F,0x08,0x08,/*\"舡\",6399*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x00,0xF8,0x00,0xFF,0x00,0xF8,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x07,0x04,0x07,0x04,0x0F,/*\"舢\",6400*/},{\n\n0x20,0xFE,0xAB,0xFE,0x22,0xAB,0x6A,0x3E,0xAA,0x6B,0xA2,0x08,0x07,0x08,0x0F,0x05,\n0x0F,0x05,0x09,0x07,0x0B,0x0D,/*\"艤\",6401*/},{\n\n0x20,0xFE,0xAB,0xFE,0x00,0xFF,0x10,0x10,0xFF,0x10,0x0C,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x04,0x02,0x07,0x08,0x0E,/*\"舭\",6402*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x00,0xF8,0x88,0xFF,0x88,0xF8,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x01,0x00,0x0F,0x00,0x01,/*\"舯\",6403*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x00,0xFE,0x12,0xF2,0x11,0xF1,0x08,0x07,0x01,0x0A,0x0F,\n0x04,0x03,0x08,0x05,0x02,0x0D,/*\"舨\",6404*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x00,0x04,0xFD,0x26,0x24,0xE4,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x08,0x07,0x00,0x08,0x0F,/*\"舫\",6405*/},{\n\n0x20,0xFE,0xAB,0xFE,0x00,0xF2,0x12,0xF2,0x02,0xFE,0x02,0x08,0x07,0x08,0x0F,0x00,\n0x03,0x01,0x09,0x08,0x0F,0x00,/*\"舸\",6406*/},{\n\n0x20,0xFE,0xAB,0xFE,0x00,0xF8,0x28,0xFF,0xAA,0xAA,0xDA,0x08,0x07,0x08,0x0F,0x06,\n0x09,0x0E,0x0B,0x0E,0x0B,0x0E,/*\"艫\",6407*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x00,0xF8,0x48,0xFF,0x48,0xF8,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x0F,0x04,0x07,0x04,0x0F,/*\"舳\",6408*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x08,0x07,0xFC,0x24,0x24,0x04,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x00,0x0F,0x01,0x01,0x01,/*\"舴\",6409*/},{\n\n0x40,0xFC,0x56,0x65,0xFE,0x12,0xFE,0x12,0xFE,0x92,0xF2,0x08,0x07,0x01,0x0A,0x0F,\n0x05,0x04,0x04,0x04,0x04,0x0F,/*\"舾\",6410*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x00,0xF2,0x54,0x5F,0x54,0xF2,0x08,0x07,0x01,0x0A,0x0F,\n0x00,0x0F,0x01,0x01,0x09,0x0F,/*\"艄\",6411*/},{\n\n0x20,0xFE,0xAB,0xFE,0x00,0xFF,0xA5,0xA5,0xE5,0x55,0x57,0x08,0x07,0x08,0x0F,0x08,\n0x07,0x02,0x02,0x07,0x09,0x0D,/*\"艉\",6412*/},{\n\n0x40,0xFE,0x4B,0x52,0xFE,0x89,0xA9,0xBD,0x8B,0x89,0x88,0x08,0x07,0x01,0x0A,0x0F,\n0x08,0x0F,0x08,0x0F,0x08,0x0F,/*\"艋\",6413*/},{\n\n0x20,0xFE,0xAB,0xFE,0x00,0xF5,0x56,0x5C,0x56,0xF5,0x04,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x05,0x05,0x05,0x0F,0x00,/*\"艏\",6414*/},{\n\n0x20,0xFE,0xAB,0xFE,0xF8,0xAA,0xFF,0xAA,0xFF,0xAA,0xFA,0x08,0x07,0x08,0x0F,0x00,\n0x0F,0x0A,0x0A,0x0A,0x0F,0x00,/*\"艚\",6415*/},{\n\n0x20,0xFE,0xAB,0xFE,0x08,0xFA,0xAE,0xFB,0xAE,0xFA,0x08,0x08,0x07,0x08,0x0F,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"艟\",6416*/},{\n\n0x20,0xFE,0xAB,0xFE,0x00,0x9A,0x6F,0xAA,0x2A,0xAF,0x5A,0x08,0x07,0x08,0x0F,0x00,\n0x0A,0x05,0x0A,0x0F,0x02,0x04,/*\"艨\",6417*/},{\n\n0x88,0x88,0x94,0x94,0x92,0xD9,0x92,0xB4,0x94,0x88,0x88,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"衾\",6418*/},{\n\n0xF8,0x0F,0xF8,0x00,0xB9,0x29,0xEF,0x00,0xB9,0x29,0xEF,0x0D,0x02,0x05,0x00,0x0A,\n0x09,0x07,0x00,0x0A,0x09,0x07,/*\"嫋\",6419*/},{\n\n0xA2,0x92,0x8F,0xA2,0xA2,0xDE,0x80,0xBE,0xA2,0xA2,0xBE,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"袈\",6420*/},{\n\n0x82,0x92,0x96,0x8A,0x82,0xDF,0x8A,0x8A,0x97,0x92,0x82,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"裘\",6421*/},{\n\n0xA2,0x94,0x81,0xA2,0xA8,0xE6,0xA0,0x9F,0x90,0x92,0x84,0x04,0x04,0x02,0x0E,0x09,\n0x04,0x01,0x02,0x04,0x0A,0x08,/*\"裟\",6422*/},{\n\n0x20,0x1F,0x75,0x55,0x77,0x80,0x0A,0x2E,0x7B,0x2E,0x0A,0x09,0x09,0x05,0x0D,0x0B,\n0x01,0x03,0x05,0x05,0x0B,0x09,/*\"襞\",6423*/},{\n\n0x89,0xAA,0xF8,0xAA,0x01,0xFE,0x22,0x22,0xFE,0x21,0x21,0x08,0x04,0x03,0x00,0x00,\n0x0F,0x04,0x08,0x03,0x04,0x0E,/*\"羝\",6424*/},{\n\n0x89,0xAA,0xF8,0xAA,0x11,0xAA,0x92,0xAA,0x92,0xAA,0x02,0x08,0x04,0x03,0x00,0x08,\n0x08,0x08,0x0F,0x08,0x08,0x08,/*\"羥\",6425*/},{\n\n0x25,0xFE,0x25,0x00,0x24,0x96,0x65,0x44,0x44,0xD6,0x2C,0x09,0x07,0x01,0x00,0x09,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"羧\",6426*/},{\n\n0x89,0xAA,0xF8,0xAA,0x01,0x9F,0x75,0xD5,0x55,0x5F,0xC0,0x08,0x04,0x03,0x00,0x01,\n0x06,0x05,0x04,0x0D,0x08,0x07,/*\"羯\",6427*/},{\n\n0x25,0xFE,0x25,0x00,0x16,0x94,0x7C,0x17,0xD4,0x14,0x96,0x09,0x07,0x01,0x08,0x06,\n0x01,0x0A,0x05,0x03,0x05,0x08,/*\"羰\",6428*/},{\n\n0xA2,0xAA,0xAA,0xEB,0xAA,0xBE,0xAA,0xEB,0xAA,0xEA,0xA2,0x02,0x01,0x0A,0x0B,0x06,\n0x01,0x0A,0x05,0x02,0x05,0x0E,/*\"羲\",6429*/},{\n\n0x12,0xD2,0xFE,0x91,0xF8,0x00,0x00,0xFF,0x00,0x00,0xF8,0x01,0x00,0x0F,0x00,0x07,\n0x04,0x04,0x07,0x04,0x04,0x0F,/*\"秈\",6430*/},{\n\n0x24,0xA8,0xFF,0xA8,0x24,0x10,0xEC,0x0B,0x88,0x78,0x08,0x01,0x00,0x0F,0x00,0x09,\n0x04,0x02,0x01,0x02,0x04,0x08,/*\"敉\",6431*/},{\n\n0x24,0xA8,0xFF,0xA8,0x04,0xFE,0x42,0x7E,0x42,0x42,0x7E,0x01,0x00,0x0F,0x00,0x01,\n0x07,0x08,0x08,0x08,0x08,0x0E,/*\"粑\",6432*/},{\n\n0x24,0xA8,0xFF,0x24,0xFF,0x01,0xF5,0x5F,0xF5,0x5F,0xF5,0x01,0x00,0x0F,0x05,0x03,\n0x0F,0x01,0x05,0x07,0x09,0x0F,/*\"糲\",6433*/},{\n\n0x5B,0x12,0xDF,0x12,0x5B,0x4A,0xF5,0xAF,0xEA,0xB5,0xAF,0x05,0x03,0x0F,0x03,0x05,\n0x00,0x0F,0x0A,0x0F,0x0A,0x0A,/*\"糶\",6434*/},{\n\n0x24,0xA8,0xFF,0x24,0xF2,0x12,0xFE,0x12,0xFE,0x92,0xF2,0x01,0x00,0x0F,0x01,0x0F,\n0x05,0x04,0x04,0x04,0x04,0x0F,/*\"粞\",6435*/},{\n\n0x10,0x11,0x4A,0x80,0x24,0xD3,0x0A,0x86,0x4A,0x12,0x26,0x09,0x09,0x05,0x03,0x01,\n0x0F,0x01,0x03,0x05,0x09,0x09,/*\"粢\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0x12,0xF2,0x9E,0x08,0x27,0xC4,0x04,0x04,0xFC,0x08,0x0F,0x08,0x07,0x04,\n0x00,0x00,0x00,0x08,0x08,0x07,/*\"趵\",6512*/},{\n\n0x9E,0x12,0xF2,0x5E,0x00,0x02,0xFE,0x02,0x32,0x2E,0xE0,0x07,0x04,0x03,0x02,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"趿\",6513*/},{\n\n0x9E,0x12,0xF2,0x5E,0x00,0x22,0xFE,0x22,0x22,0xFE,0x22,0x07,0x04,0x03,0x02,0x08,\n0x06,0x01,0x00,0x00,0x0F,0x00,/*\"趼\",6514*/},{\n\n0x9E,0x12,0xF2,0x9E,0x40,0x48,0x48,0xFF,0x48,0x48,0x40,0x0F,0x08,0x07,0x04,0x08,\n0x04,0x03,0x00,0x03,0x04,0x08,/*\"趺\",6515*/},{\n\n0x9E,0x12,0xF2,0x9E,0x08,0xFC,0xAA,0xAD,0xAA,0xFC,0x08,0x0F,0x08,0x07,0x04,0x03,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"蹌\",6516*/},{\n\n0x9E,0x12,0xFE,0x40,0xFE,0x22,0xFA,0x23,0x22,0xFA,0x22,0x07,0x04,0x0B,0x06,0x0B,\n0x04,0x09,0x05,0x09,0x05,0x08,/*\"蹠\",6517*/},{\n\n0x9E,0x12,0xF2,0x9E,0x10,0xFC,0x03,0x48,0x88,0xFF,0x08,0x0F,0x08,0x07,0x04,0x00,\n0x0F,0x00,0x00,0x08,0x0F,0x00,/*\"跗\",6518*/},{\n\n0x9E,0x12,0xF2,0x5E,0x20,0xFE,0x22,0xFE,0x22,0xFE,0x20,0x07,0x04,0x03,0x02,0x08,\n0x07,0x00,0x07,0x08,0x0F,0x00,/*\"跚\",6519*/},{\n\n0x9E,0x12,0xFE,0x40,0xB6,0xAD,0xBE,0xEB,0xBE,0x94,0xAB,0x07,0x04,0x03,0x02,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"躒\",6520*/},{\n\n0x9E,0x12,0xF2,0x9E,0x00,0x0C,0xE4,0x05,0x86,0x44,0x2C,0x0F,0x08,0x07,0x04,0x00,\n0x00,0x07,0x09,0x08,0x08,0x0E,/*\"跎\",6521*/},{\n\n0x9E,0x12,0xFE,0x48,0xFF,0x08,0xF8,0x00,0xFC,0x04,0xFC,0x07,0x04,0x0B,0x06,0x03,\n0x08,0x0F,0x00,0x0F,0x04,0x0F,/*\"跏\",6522*/},{\n\n0x9E,0x12,0xF2,0x5E,0x00,0xFC,0x24,0xE4,0x3F,0xE4,0x0C,0x07,0x04,0x03,0x0A,0x04,\n0x03,0x08,0x05,0x02,0x05,0x08,/*\"跛\",6523*/},{\n\n0x9E,0x12,0xF2,0x9E,0x00,0xD8,0x54,0x53,0x50,0xD8,0x30,0x0F,0x08,0x07,0x04,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"跆\",6524*/},{\n\n0x9E,0x12,0xF2,0x9E,0x20,0x24,0x24,0xBF,0x24,0x24,0x20,0x0F,0x08,0x07,0x04,0x08,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"跬\",6525*/},{\n\n0x9E,0x12,0xF2,0x5E,0xA8,0xFA,0xAA,0x0F,0xAA,0xFA,0xA8,0x07,0x04,0x03,0x02,0x08,\n0x0A,0x06,0x02,0x06,0x0A,0x0C,/*\"蹺\",6526*/},{\n\n0x9E,0x12,0xFE,0x40,0x5F,0xF5,0x55,0xFF,0x55,0xF5,0x5F,0x07,0x04,0x03,0x02,0x05,\n0x05,0x05,0x0F,0x05,0x05,0x05,/*\"蹕\",6527*/},{\n\n0x9E,0x12,0xF2,0x9E,0x50,0x4E,0xC8,0x7F,0xC8,0x48,0x40,0x0F,0x08,0x07,0x04,0x08,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"跣\",6528*/},{\n\n0x9E,0x12,0xF2,0x5E,0x21,0xE2,0x5D,0xF5,0x5F,0xF5,0x5D,0x07,0x04,0x03,0x02,0x08,\n0x07,0x08,0x0B,0x0D,0x0D,0x0E,/*\"躚\",6529*/},{\n\n0x9E,0x12,0xFE,0x68,0xDA,0x7A,0x06,0x7B,0x06,0x7A,0xD6,0x07,0x04,0x03,0x0A,0x07,\n0x05,0x05,0x05,0x05,0x05,0x0F,/*\"躋\",6530*/},{\n\n0x9E,0x12,0xF2,0x9E,0x40,0x24,0xD5,0x06,0xD4,0x24,0x44,0x0F,0x08,0x07,0x04,0x08,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"跤\",6531*/},{\n\n0x9E,0x12,0xF2,0x9E,0x00,0xFC,0x55,0xD6,0x54,0x7C,0x80,0x0F,0x08,0x07,0x04,0x00,\n0x0F,0x04,0x01,0x02,0x05,0x08,/*\"踉\",6532*/},{\n\n0xCF,0x09,0xF9,0x4F,0x00,0x39,0xC9,0x49,0x49,0x4F,0x60,0x07,0x04,0x03,0x02,0x04,\n0x02,0x0C,0x09,0x0C,0x01,0x06,/*\"跽\",6533*/},{\n\n0x9E,0x12,0xF2,0x9E,0x00,0xF8,0xA8,0xAF,0xAA,0xAA,0xFA,0x0F,0x08,0x07,0x04,0x02,\n0x02,0x02,0x0F,0x02,0x02,0x02,/*\"踔\",6534*/},{\n\n0xCF,0x09,0xF9,0x4F,0x00,0x5F,0x55,0xFF,0x55,0x5F,0x40,0x07,0x04,0x03,0x02,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"踝\",6535*/},{\n\n0x9E,0x12,0xFE,0x48,0x47,0xFC,0x44,0x40,0xFE,0x02,0xFE,0x07,0x04,0x03,0x0A,0x06,\n0x01,0x06,0x00,0x07,0x02,0x07,/*\"踟\",6536*/},{\n\n0x9E,0x12,0xFE,0x50,0x0E,0xE5,0xBD,0xB4,0xAE,0xE5,0x1D,0x07,0x04,0x03,0x02,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"躓\",6537*/},{\n\n0x9E,0x12,0xF2,0x5E,0x00,0xFC,0x04,0x85,0xFE,0xA4,0xA4,0x07,0x04,0x03,0x02,0x08,\n0x07,0x00,0x0F,0x04,0x04,0x0F,/*\"踮\",6538*/},{\n\n0x9E,0x12,0xF2,0x5E,0x20,0xAA,0xB2,0xA3,0xB2,0xAA,0x20,0x07,0x04,0x03,0x02,0x00,\n0x0F,0x04,0x04,0x04,0x0F,0x00,/*\"踣\",6539*/},{\n\n0x1F,0xF1,0x5F,0xFA,0xAB,0x9E,0xAB,0xFA,0xFF,0x31,0xCF,0x04,0x07,0x02,0x0A,0x06,\n0x03,0x06,0x0A,0x0F,0x02,0x01,/*\"躑\",6540*/},{\n\n0x9E,0x12,0xF2,0x9E,0x64,0xDC,0x88,0xAA,0xFF,0xAA,0xBE,0x0F,0x08,0x07,0x04,0x0A,\n0x07,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"踺\",6541*/},{\n\n0x9E,0x12,0xF2,0x5E,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x07,0x04,0x03,0x02,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"蹀\",6542*/},{\n\n0x9E,0x12,0xFE,0x40,0xAE,0xA8,0xA8,0xEF,0xA8,0xA8,0xAE,0x07,0x04,0x03,0x02,0x0F,\n0x00,0x07,0x00,0x07,0x08,0x0F,/*\"踹\",6543*/},{\n\n0x9E,0x12,0xF2,0x9E,0x08,0xFA,0xAA,0xFE,0xA9,0xF9,0x08,0x0F,0x08,0x07,0x04,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"踵\",6544*/},{\n\n0x9E,0x12,0xF2,0x5E,0x80,0xBA,0xAA,0xFE,0xA9,0xB9,0x80,0x07,0x04,0x03,0x02,0x0F,\n0x00,0x02,0x03,0x06,0x08,0x0F,/*\"踽\",6545*/},{\n\n0x9E,0x12,0xF2,0x5E,0x00,0xFE,0x8A,0xBE,0xAB,0xBE,0x8A,0x07,0x04,0x03,0x02,0x08,\n0x07,0x08,0x0B,0x04,0x0A,0x09,/*\"踱\",6546*/},{\n\n0x9E,0x12,0xF2,0x9E,0x44,0xD5,0x76,0x5C,0x56,0x55,0x44,0x0F,0x08,0x07,0x04,0x0A,\n0x09,0x09,0x0F,0x09,0x09,0x08,/*\"蹉\",6547*/},{\n\n0x9E,0x12,0xFE,0x40,0xFE,0x2A,0xEA,0x2B,0xEA,0x2A,0xEE,0x07,0x04,0x03,0x02,0x0F,\n0x01,0x07,0x01,0x07,0x09,0x0F,/*\"蹁\",6548*/},{\n\n0xCF,0x09,0xF9,0x4F,0x00,0x48,0x29,0xDB,0x7D,0x0B,0x18,0x07,0x04,0x03,0x02,0x08,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"蹂\",6549*/},{\n\n0x9E,0x12,0xFE,0x40,0xD1,0x5F,0xD5,0x55,0x7F,0xC9,0x40,0x07,0x04,0x03,0x06,0x07,\n0x05,0x0F,0x05,0x05,0x0F,0x02,/*\"躡\",6550*/},{\n\n0xCF,0x09,0xF9,0x4F,0xE2,0xAF,0x2A,0xFA,0xAA,0x2F,0xE2,0x07,0x04,0x03,0x02,0x0F,\n0x02,0x01,0x0F,0x02,0x09,0x0F,/*\"蹣\",6551*/},{\n\n0x9E,0x12,0xFE,0x40,0x86,0xAA,0xF6,0xAA,0xA1,0xD5,0x83,0x07,0x04,0x03,0x02,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"蹊\",6552*/},{\n\n0x9E,0x12,0xFE,0x40,0xFE,0xAA,0xBE,0xAB,0x52,0xFE,0x12,0x07,0x04,0x0B,0x06,0x0B,\n0x0E,0x0A,0x0F,0x08,0x0F,0x00,/*\"躕\",6553*/},{\n\n0x9E,0x12,0xFE,0x40,0xFE,0x2A,0xF2,0x2A,0xA2,0xDE,0x32,0x07,0x04,0x03,0x0A,0x07,\n0x09,0x07,0x09,0x05,0x03,0x0C,/*\"蹶\",6554*/},{\n\n0x9E,0x12,0xF2,0x9E,0x25,0xAC,0xB7,0xE4,0xB7,0xAC,0x25,0x0F,0x08,0x07,0x04,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"蹼\",6555*/},{\n\n0x9E,0x12,0xF2,0x9E,0x40,0xB6,0x9A,0xBE,0x99,0xB5,0x50,0x0F,0x08,0x07,0x04,0x00,\n0x0F,0x0A,0x0F,0x0A,0x0F,0x00,/*\"蹯\",6556*/},{\n\n0x9E,0x12,0xFE,0x40,0x7A,0xCB,0x7A,0x10,0xFF,0x12,0x14,0x07,0x04,0x03,0x02,0x09,\n0x0F,0x01,0x0A,0x07,0x08,0x0F,/*\"蹴\",6557*/},{\n\n0x9E,0x12,0xFE,0x60,0xD7,0x5D,0xF7,0x55,0xD7,0x15,0xF7,0x07,0x04,0x03,0x02,0x05,\n0x05,0x07,0x05,0x0D,0x08,0x07,/*\"躅\",6558*/},{\n\n0x9E,0x12,0xFE,0x40,0xFA,0x2F,0xBA,0x42,0xBA,0x2F,0xFA,0x07,0x04,0x03,0x02,0x0F,\n0x01,0x0F,0x05,0x07,0x05,0x0F,/*\"躪\",6559*/},{\n\n0x9E,0x12,0xF2,0x5E,0x00,0xFE,0xAA,0xFF,0xAA,0xBE,0x82,0x07,0x04,0x03,0x0A,0x04,\n0x0B,0x0A,0x0F,0x0A,0x09,0x02,/*\"躔\",6560*/},{\n\n0x9E,0x12,0xF2,0x9E,0x00,0xFA,0x8D,0xDA,0xAD,0xDA,0xFD,0x0F,0x08,0x07,0x04,0x00,\n0x0F,0x0A,0x07,0x0A,0x07,0x0C,/*\"躐\",6561*/},{\n\n0x9E,0x12,0xFE,0x44,0xEB,0x5A,0xFF,0x6A,0x5A,0x7F,0xEA,0x07,0x04,0x03,0x02,0x0B,\n0x06,0x02,0x03,0x02,0x06,0x0B,/*\"躦\",6562*/},{\n\n0x9E,0x12,0xF2,0x5E,0x00,0xEA,0xAB,0xEA,0x44,0x3F,0x48,0x07,0x04,0x03,0x02,0x09,\n0x0B,0x05,0x05,0x05,0x0B,0x08,/*\"躞\",6563*/},{\n\n0x00,0x24,0x24,0xAA,0x92,0x55,0x29,0xC8,0x04,0x00,0x00,0x00,0x01,0x05,0x04,0x02,\n0x0A,0x09,0x07,0x00,0x00,0x00,/*\"豸\",6564*/},{\n\n0xA4,0xAA,0x55,0xA8,0xC4,0x20,0x92,0x8E,0xA2,0xA2,0x9E,0x02,0x02,0x09,0x08,0x07,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"貂\",6565*/},{\n\n0xA4,0xAA,0x55,0xE8,0x00,0xF2,0x92,0x9A,0x96,0x92,0xF2,0x02,0x0A,0x09,0x07,0x00,\n0x0F,0x04,0x04,0x04,0x04,0x0F,/*\"貊\",6566*/},{\n\n0xA4,0xAA,0x55,0xE8,0x10,0xFC,0x8B,0x48,0xFF,0x48,0x88,0x02,0x0A,0x09,0x07,0x00,\n0x0F,0x00,0x00,0x0F,0x00,0x00,/*\"貅\",6567*/},{\n\n0xA4,0xAA,0x55,0xE8,0x02,0xFA,0xAF,0xAA,0xAF,0xFA,0x02,0x02,0x0A,0x09,0x07,0x0A,\n0x0A,0x06,0x03,0x06,0x0A,0x0A,/*\"貘\",6568*/},{\n\n0xA4,0xAA,0x55,0xE8,0x00,0xBE,0x36,0x2B,0xB6,0x22,0xBE,0x02,0x0A,0x09,0x07,0x00,\n0x0F,0x09,0x00,0x07,0x09,0x0C,/*\"貔\",6569*/},{\n\n0x08,0xF4,0x53,0xFA,0x56,0xF0,0x92,0xA4,0x80,0xFF,0x40,0x08,0x07,0x01,0x07,0x09,\n0x0F,0x00,0x00,0x00,0x0F,0x00,/*\"斛\",6570*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x44,0x44,0xFF,0x44,0x7C,0x40,0x07,0x01,0x07,0x09,0x0F,\n0x08,0x06,0x01,0x02,0x04,0x08,/*\"觖\",6571*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x84,0xFB,0xAA,0xAA,0xFA,0x82,0x07,0x01,0x07,0x09,0x0F,\n0x0A,0x07,0x0A,0x06,0x0A,0x0E,/*\"觴\",6572*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xFE,0x02,0xFE,0x02,0xFD,0x07,0x01,0x07,0x09,0x0F,\n0x04,0x03,0x00,0x0F,0x0A,0x0C,/*\"觚\",6573*/},{\n\n0x10,0x9E,0xD0,0xAF,0xAA,0xAA,0xE0,0xAF,0x94,0x92,0x19,0x01,0x08,0x07,0x02,0x02,\n0x07,0x02,0x02,0x0A,0x0F,0x00,/*\"觜\",6574*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x24,0xE8,0x3F,0xE0,0x28,0x24,0x07,0x01,0x07,0x09,0x0F,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"觥\",6575*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xF4,0x94,0xFF,0x94,0xF4,0x07,0x01,0x07,0x09,0x0F,\n0x00,0x04,0x02,0x0F,0x02,0x04,/*\"觫\",6576*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xF7,0x55,0xF7,0x55,0xF7,0x07,0x01,0x07,0x09,0x0F,\n0x00,0x05,0x05,0x0F,0x05,0x05,/*\"觶\",6577*/},{\n\n0x28,0xAE,0xA8,0xAF,0xAA,0xB0,0xA7,0xAA,0xAA,0xA9,0x2C,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"訾\",6578*/},{\n\n0xC2,0xBA,0xAA,0xBF,0xEA,0xBA,0x84,0xDB,0xA9,0xDB,0x82,0x00,0x02,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0E,0x02,0x00,/*\"謦\",6579*/},{\n\n0x22,0xEA,0xBF,0xEA,0x22,0x00,0xFE,0xAA,0xAA,0xFE,0x00,0x00,0x0F,0x02,0x0F,0x00,\n0x08,0x06,0x01,0x07,0x08,0x0C,/*\"靚\",6580*/},{\n\n0x8C,0x85,0xAD,0xA5,0xA5,0xAF,0xA5,0xA5,0xAD,0x85,0x8C,0x00,0x00,0x03,0x02,0x02,\n0x02,0x02,0x0A,0x0A,0x06,0x00,/*\"雩\",6581*/},{\n\n0x0C,0xE5,0x2D,0xA5,0xA5,0x6F,0x25,0xA5,0xAD,0x65,0x2C,0x08,0x07,0x0A,0x06,0x0F,\n0x02,0x04,0x02,0x0F,0x06,0x0A,/*\"靂\",6582*/},{\n\n0x8C,0xA5,0xAD,0xAD,0x85,0xDF,0x85,0xAD,0xAD,0xA5,0x8C,0x08,0x08,0x09,0x0A,0x04,\n0x04,0x04,0x0A,0x09,0x08,0x08,/*\"雯\",6583*/},{\n\n0x0C,0x25,0xA5,0x6D,0x05,0xAF,0xA5,0xED,0xA5,0x95,0x0C,0x09,0x0A,0x04,0x0B,0x08,\n0x0A,0x0A,0x0B,0x0A,0x0A,0x08,/*\"霆\",6584*/},{\n\n0x4C,0xD5,0x5D,0xD5,0x35,0xDF,0x35,0xD5,0x5D,0xB5,0x0C,0x09,0x06,0x05,0x05,0x04,\n0x04,0x04,0x05,0x05,0x0E,0x01,/*\"霽\",6585*/},{\n\n0x0C,0x65,0xAD,0x2D,0x85,0xBF,0x85,0xED,0xAD,0xA5,0x8C,0x01,0x0A,0x04,0x00,0x0E,\n0x02,0x02,0x0F,0x02,0x0A,0x0E,/*\"霈\",6586*/},{\n\n0x4C,0x55,0x55,0x55,0xE5,0x1F,0xE5,0x55,0x55,0x55,0x4C,0x04,0x05,0x05,0x05,0x0F,\n0x00,0x0F,0x05,0x05,0x05,0x04,/*\"霏\",6587*/},{\n\n0x4C,0x55,0x5D,0x75,0xD5,0x5F,0x55,0x75,0x5D,0x55,0x4C,0x09,0x09,0x0B,0x0B,0x05,\n0x05,0x05,0x0B,0x09,0x09,0x01,/*\"霎\",6588*/},{\n\n0x4C,0x95,0x2D,0x85,0xE5,0xAF,0xE5,0x95,0xDD,0xA5,0x0C,0x08,0x04,0x02,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x02,/*\"霪\",6589*/},{\n\n0xAC,0xA5,0xB5,0xAD,0x05,0xFF,0x95,0xBD,0xD5,0xF5,0x8C,0x0E,0x0A,0x0A,0x0E,0x01,\n0x06,0x04,0x06,0x05,0x0A,0x0F,/*\"靄\",6590*/},{\n\n0x8C,0xA5,0xFD,0xA5,0xF5,0xAF,0x85,0x75,0x4D,0xC5,0x4C,0x00,0x0F,0x02,0x02,0x0A,\n0x0F,0x08,0x05,0x02,0x05,0x08,/*\"霰\",6591*/},{\n\n0xAC,0xE5,0x9D,0x75,0x45,0x0F,0xE5,0xA5,0xED,0xA5,0xEC,0x0A,0x0A,0x05,0x0B,0x0E,\n0x00,0x0B,0x0A,0x0F,0x0A,0x0B,/*\"霾\",6592*/},{\n\n0xE8,0xCE,0xB8,0xCF,0xBA,0xCA,0xE8,0x40,0xFF,0x10,0x08,0x07,0x06,0x05,0x06,0x05,\n0x06,0x0F,0x00,0x07,0x08,0x0E,/*\"齔\",6593*/},{\n\n0xE8,0xCE,0xB8,0xCF,0xBA,0xCA,0xE8,0x00,0xFE,0x92,0xFE,0x07,0x06,0x05,0x06,0x05,\n0x06,0x0F,0x08,0x0F,0x08,0x0F,/*\"齟\",6594*/},{\n\n0xEE,0xA8,0x9F,0xAA,0xEA,0x08,0xF4,0x97,0xF4,0x04,0xFC,0x0F,0x0A,0x09,0x0A,0x0F,\n0x00,0x07,0x08,0x08,0x09,0x0D,/*\"齙\",6595*/},{\n\n0xE8,0xCE,0xB8,0xCF,0xBA,0xCA,0xE8,0x22,0x9E,0xA2,0xBE,0x07,0x06,0x05,0x06,0x05,\n0x06,0x0F,0x00,0x0F,0x04,0x0F,/*\"齠\",6596*/},{\n\n0xEE,0xA8,0x9F,0xAA,0xFA,0x00,0xFF,0x20,0xFF,0x10,0x08,0x0F,0x0A,0x09,0x0A,0x0F,\n0x08,0x07,0x04,0x07,0x08,0x0E,/*\"齜\",6597*/},{\n\n0xEE,0xA8,0x9F,0xAA,0xEA,0x00,0xFF,0x49,0xC9,0x7F,0x00,0x0F,0x0A,0x09,0x0A,0x0F,\n0x00,0x0F,0x04,0x01,0x06,0x09,/*\"齦\",6598*/},{\n\n0xEE,0xA8,0x9F,0xAA,0xEA,0x24,0xBD,0xA7,0xA5,0xBD,0x20,0x0F,0x0A,0x09,0x0A,0x0F,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"齬\",6599*/},{\n\n0xEE,0xA8,0x9F,0xAA,0xEA,0x00,0xDF,0x11,0xF1,0x91,0x9F,0x0F,0x0A,0x09,0x0A,0x0F,\n0x04,0x03,0x04,0x0F,0x08,0x08,/*\"齪\",6600*/},{\n\n0xEE,0xA8,0x9F,0xAA,0xEA,0x00,0xFF,0xD5,0xB5,0xD5,0x97,0x0F,0x0A,0x09,0x0A,0x0F,\n0x06,0x09,0x0A,0x0F,0x0A,0x0A,/*\"齷\",6601*/},{\n\n0x00,0xF7,0x55,0x55,0xFF,0x01,0xFF,0x55,0x55,0xF7,0x00,0x00,0x01,0x01,0x01,0x07,\n0x08,0x0F,0x09,0x09,0x09,0x0C,/*\"黽\",6602*/},{\n\n0x24,0xF4,0xAD,0xA5,0xE5,0x25,0xE5,0xAD,0xB5,0xF4,0x18,0x00,0x0E,0x0A,0x0A,0x07,\n0x08,0x0F,0x0A,0x0E,0x08,0x0C,/*\"黿\",6603*/},{\n\n0x27,0xE5,0xBD,0xAD,0xEF,0x38,0xEF,0xAD,0xBD,0xE5,0x27,0x00,0x0E,0x0A,0x0A,0x07,\n0x08,0x0F,0x0A,0x0E,0x08,0x0C,/*\"鼉\",6604*/},{\n\n0x20,0x10,0xFC,0x27,0x24,0x24,0xFD,0x26,0x24,0x24,0x04,0x00,0x00,0x0F,0x09,0x09,\n0x09,0x0F,0x09,0x09,0x09,0x08,/*\"隹\",6605*/},{\n\n0x08,0x04,0xFE,0xAB,0xAA,0xAA,0xFE,0xAB,0xAA,0xAA,0x82,0x02,0x02,0x03,0x02,0x02,\n0x0F,0x02,0x02,0x02,0x02,0x02,/*\"隼\",6606*/},{\n\n0x08,0x04,0xFE,0xAB,0xAA,0xAA,0xFE,0xAB,0xAA,0xAA,0x82,0x00,0x0E,0x03,0x02,0x06,\n0x04,0x06,0x02,0x0A,0x0E,0x00,/*\"雋\",6607*/},{\n\n0x00,0xFE,0x92,0xFE,0x10,0xFC,0xA7,0xA4,0xFD,0xA6,0xA4,0x04,0x07,0x04,0x03,0x02,\n0x0F,0x04,0x04,0x07,0x04,0x04,/*\"雎\",6608*/},{\n\n0x44,0xAB,0x92,0xAE,0x40,0x10,0xFC,0x27,0xFC,0x25,0x24,0x00,0x0F,0x04,0x0F,0x00,\n0x00,0x0F,0x09,0x0F,0x09,0x09,/*\"雒\",6609*/},{\n\n0x00,0x9F,0xD5,0x75,0x5F,0x40,0xDF,0x75,0x55,0x5F,0x40,0x01,0x00,0x0F,0x05,0x05,\n0x05,0x07,0x05,0x05,0x05,0x04,/*\"瞿\",6610*/},{\n\n0xFC,0x27,0xFC,0x25,0x54,0x55,0x54,0xFC,0x27,0xFC,0x25,0x0F,0x09,0x0F,0x09,0x07,\n0x05,0x07,0x0F,0x09,0x0F,0x09,/*\"讎\",6611*/},{\n\n0x90,0x91,0x4F,0xC9,0xA0,0x9F,0xA5,0xC9,0x5F,0xA0,0xB0,0x08,0x0A,0x0E,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0E,0x0A,0x08,/*\"銎\",6612*/},{\n\n0x56,0x1D,0x54,0x80,0xBA,0x6B,0xBA,0x80,0x56,0x1D,0x54,0x09,0x09,0x0B,0x0E,0x0A,\n0x0F,0x0A,0x0E,0x0B,0x09,0x09,/*\"鑾\",6613*/},{\n\n0x44,0x29,0x92,0xA4,0xD5,0xAD,0xC7,0x8D,0x95,0x25,0x04,0x09,0x09,0x0A,0x0E,0x0A,\n0x0F,0x0A,0x0E,0x0A,0x09,0x09,/*\"鋈\",6614*/},{\n\n0x22,0x3E,0x2A,0xFF,0xAA,0x7E,0xC2,0xBE,0x0A,0x79,0x08,0x09,0x09,0x0B,0x0E,0x0A,\n0x0F,0x0A,0x0E,0x0B,0x09,0x09,/*\"鏨\",6615*/},{\n\n0x94,0x8D,0x57,0xDD,0xA7,0x9C,0xB4,0xCB,0x4A,0x96,0x92,0x08,0x0A,0x0E,0x0A,0x0A,\n0x0F,0x0A,0x0A,0x0E,0x0A,0x08,/*\"鍪\",6616*/},{\n\n0x48,0x2A,0xBA,0xAF,0xEA,0xAA,0xC4,0xAB,0x92,0x2E,0x42,0x09,0x09,0x0A,0x0E,0x0A,\n0x0F,0x0A,0x0E,0x0A,0x09,0x09,/*\"鏊\",6617*/},{\n\n0x44,0x29,0x92,0x80,0xCA,0xBE,0xCA,0xBB,0x8A,0x3E,0x6A,0x09,0x09,0x0A,0x0E,0x0A,\n0x0F,0x0A,0x0E,0x0A,0x09,0x09,/*\"鎏\",6618*/},{\n\n0x20,0x1F,0x75,0xD5,0xF7,0xA0,0xCA,0xAE,0xFB,0x2E,0x0A,0x01,0x09,0x0B,0x0E,0x0A,\n0x0F,0x0A,0x0E,0x0A,0x09,0x01,/*\"鐾\",6619*/},{\n\n0x04,0xA4,0x6C,0xBA,0x2A,0x39,0x2A,0xBA,0x6C,0xA4,0x04,0x0D,0x0A,0x0E,0x0A,0x0D,\n0x00,0x0D,0x0A,0x0E,0x0A,0x0D,/*\"鑫\",6620*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x08,0xFF,0x08,0xF8,0x09,0x0A,0x0D,0x01,0x0D,0x01,0x0D,\n0x06,0x01,0x00,0x07,0x08,0x0E,/*\"魷\",6621*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x04,0x04,0xFD,0x26,0x24,0xE4,0x0D,0x01,0x0D,0x01,0x0D,\n0x08,0x06,0x01,0x08,0x08,0x07,/*\"魴\",6622*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xC8,0x3F,0xE8,0x29,0xEA,0x0D,0x01,0x0D,0x01,0x0D,\n0x04,0x03,0x08,0x05,0x02,0x0D,/*\"鮁\",6623*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x08,0xB2,0x82,0xFE,0xA2,0x9A,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x00,0x00,0x0F,0x00,0x00,/*\"鮃\",6624*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xC0,0x40,0x7F,0x48,0xC8,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"鮎\",6625*/},{\n\n0xF4,0x53,0xFA,0x56,0xF8,0x28,0xFF,0xAA,0xAA,0xDA,0x00,0x0D,0x01,0x0D,0x07,0x09,\n0x0E,0x0B,0x0E,0x0B,0x0E,0x08,/*\"鱸\",6626*/},{\n\n0x08,0xF4,0x53,0xFA,0x56,0xF0,0x92,0x52,0xFE,0x51,0x91,0x08,0x05,0x09,0x05,0x09,\n0x05,0x08,0x00,0x0F,0x00,0x00,/*\"穌\",6627*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x10,0xFC,0x4B,0x88,0xFF,0x08,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x00,0x08,0x0F,0x00,/*\"鮒\",6628*/},{\n\n0x60,0xBF,0xE5,0xA0,0xB5,0xAA,0xF5,0xA0,0xA5,0x3F,0x60,0x08,0x00,0x07,0x0A,0x02,\n0x07,0x02,0x0A,0x07,0x00,0x08,/*\"鱟\",6629*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x10,0xDC,0x53,0x50,0xD8,0x30,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"鮐\",6630*/},{\n\n0x08,0xF4,0x53,0xFA,0x56,0xF0,0x20,0x24,0xBF,0x24,0x24,0x08,0x05,0x09,0x05,0x09,\n0x05,0x08,0x09,0x0F,0x09,0x09,/*\"鮭\",6631*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x04,0xA4,0xA4,0xBF,0xA4,0xA4,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"鮚\",6632*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x24,0xF4,0x5C,0x57,0x54,0xF4,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x01,0x01,0x09,0x0F,/*\"鮪\",6633*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x02,0xF2,0x1A,0xF6,0x12,0xF2,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x00,0x03,0x08,0x0F,/*\"鮞\",6634*/},{\n\n0xF4,0x53,0xFA,0x56,0x48,0xFA,0x06,0x7B,0x06,0xFA,0x56,0x0D,0x01,0x0D,0x01,0x08,\n0x07,0x05,0x05,0x05,0x0F,0x00,/*\"鱭\",6635*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x24,0xD5,0x06,0xD4,0x24,0x44,0x0D,0x01,0x0D,0x01,0x0D,\n0x08,0x05,0x02,0x05,0x08,0x08,/*\"鮫\",6636*/},{\n\n0x48,0xAA,0xDA,0xAB,0xBE,0xAA,0xEA,0xAB,0x9A,0x2A,0x48,0x08,0x00,0x07,0x0A,0x02,\n0x07,0x02,0x0A,0x07,0x00,0x08,/*\"鯗\",6637*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x22,0xEA,0x2A,0xEA,0xBE,0xE0,0x0D,0x01,0x0D,0x01,0x0D,\n0x02,0x06,0x02,0x0A,0x0F,0x02,/*\"鱘\",6638*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xFA,0xAA,0xFE,0xAA,0xFA,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0A,0x04,0x0B,0x08,0x08,/*\"鯁\",6639*/},{\n\n0xF4,0x5B,0xF6,0x50,0xED,0xA5,0xED,0xB0,0xED,0xA5,0xAD,0x0D,0x01,0x0D,0x09,0x07,\n0x02,0x0F,0x0A,0x03,0x0E,0x0B,/*\"鱺\",6640*/},{\n\n0xF4,0x5B,0xF6,0x51,0xF2,0x00,0xFA,0xAA,0xFF,0xAA,0xFA,0x0D,0x01,0x0D,0x09,0x07,\n0x08,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"鰱\",6641*/},{\n\n0xF4,0x5B,0xF6,0x50,0xFE,0xAA,0xEE,0xBA,0x5E,0x22,0xDE,0x0D,0x01,0x0D,0x01,0x08,\n0x0A,0x0A,0x0F,0x0A,0x0A,0x08,/*\"鰹\",6642*/},{\n\n0xF4,0x5B,0xF6,0x50,0xFE,0x22,0xFE,0x54,0x5F,0xF4,0x50,0x0D,0x01,0x0D,0x01,0x07,\n0x02,0x07,0x01,0x0A,0x0F,0x00,/*\"鰣\",6643*/},{\n\n0xF4,0x5B,0xF6,0x50,0xFC,0x03,0xF4,0x97,0xEA,0x96,0xA0,0x0D,0x01,0x0D,0x01,0x0F,\n0x00,0x05,0x0A,0x0F,0x02,0x04,/*\"鰷\",6644*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0x92,0xDA,0xB6,0x91,0xC9,0x0D,0x01,0x0D,0x01,0x0D,\n0x04,0x02,0x08,0x0F,0x02,0x04,/*\"鯀\",6645*/},{\n\n0x22,0x94,0xC1,0xA2,0xB8,0xA6,0xE0,0xBF,0x90,0x12,0x04,0x08,0x00,0x07,0x0A,0x02,\n0x07,0x02,0x0A,0x07,0x00,0x08,/*\"鯊\",6646*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x4C,0xD4,0x55,0xD6,0x54,0x4C,0x0D,0x01,0x0D,0x01,0x0D,\n0x04,0x03,0x00,0x07,0x08,0x0C,/*\"鯇\",6647*/},{\n\n0xF4,0x5B,0xF6,0x50,0xFE,0x92,0xFE,0x00,0xFE,0x02,0xFE,0x0D,0x01,0x0D,0x01,0x0F,\n0x04,0x02,0x04,0x0F,0x01,0x01,/*\"鯽\",6648*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x20,0xEA,0xAA,0xBF,0xEA,0x22,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x02,0x0A,0x0F,0x00,/*\"鯖\",6649*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x28,0x9A,0x6F,0x4A,0xDA,0x28,0x0D,0x01,0x0D,0x01,0x0D,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"鯪\",6650*/},{\n\n0xF4,0x5B,0xF6,0x51,0xFF,0x49,0xFF,0x01,0xFE,0x02,0xFE,0x0D,0x01,0x0D,0x03,0x03,\n0x02,0x0F,0x09,0x04,0x03,0x0C,/*\"鯫\",6651*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0x24,0xFF,0x00,0xFF,0x24,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x01,0x0F,0x00,0x0F,0x01,/*\"鯡\",6652*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xDF,0x15,0xD5,0x9F,0x40,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x09,0x07,0x08,0x0E,/*\"鯤\",6653*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xC0,0x5F,0x55,0x5F,0xC0,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x05,0x05,0x05,0x0F,/*\"鯧\",6654*/},{\n\n0xF4,0x5B,0xF6,0x50,0xFE,0x02,0xD2,0x7E,0xD2,0x02,0xFE,0x0D,0x01,0x0D,0x01,0x0F,\n0x04,0x05,0x05,0x05,0x04,0x0F,/*\"鯝\",6655*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0xFE,0x92,0x81,0x92,0xFE,0x00,0x0D,0x01,0x0D,0x01,0x0D,\n0x08,0x07,0x00,0x07,0x08,0x0C,/*\"鯢\",6656*/},{\n\n0xF4,0x53,0xFA,0x56,0xF8,0x24,0xAA,0x31,0xA2,0x64,0x08,0x0D,0x01,0x0D,0x01,0x0D,\n0x02,0x0C,0x09,0x0C,0x02,0x04,/*\"鯰\",6657*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xFF,0xA9,0xBD,0xA9,0xFF,0x0D,0x01,0x0D,0x01,0x0D,\n0x08,0x07,0x03,0x0A,0x0B,0x0F,/*\"鯛\",6658*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0xAA,0xFA,0xA6,0xE2,0xFE,0x00,0x0D,0x01,0x0D,0x01,0x0D,\n0x04,0x07,0x04,0x0E,0x03,0x0C,/*\"鯴\",6659*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x04,0xDB,0x44,0xDB,0x44,0xDB,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x05,0x07,0x05,0x0F,/*\"鯔\",6660*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xEA,0xBE,0xAB,0xBE,0xEA,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0B,0x06,0x02,0x06,0x0B,/*\"鱝\",6661*/},{\n\n0xF4,0x5B,0xF6,0x50,0x04,0x7E,0x44,0xDF,0x54,0x5F,0x44,0x0D,0x01,0x0D,0x01,0x09,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"鰈\",6662*/},{\n\n0xF4,0x5B,0xF6,0x50,0xBA,0xAA,0xFE,0x82,0xBA,0xAA,0xBA,0x0D,0x01,0x0D,0x09,0x0E,\n0x0A,0x0F,0x08,0x0E,0x0A,0x0E,/*\"鱷\",6663*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x92,0xFE,0x51,0x08,0xFF,0x10,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x08,0x07,0x00,0x07,/*\"鰍\",6664*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x02,0x7D,0xD5,0x55,0x7D,0x01,0x0D,0x01,0x0D,0x01,0x0D,\n0x0A,0x0B,0x05,0x05,0x0B,0x08,/*\"鰒\",6665*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xBE,0xAB,0xAA,0xAA,0xBE,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"鰉\",6666*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x80,0xFE,0x2A,0xEB,0x2A,0xEE,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x01,0x07,0x09,0x0F,/*\"鯿\",6667*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xD3,0x55,0xEB,0x55,0xD3,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x05,0x05,0x07,0x05,0x0D,/*\"鰠\",6668*/},{\n\n0x48,0xAA,0xDA,0xAF,0xBA,0xAA,0xE4,0xAB,0x92,0x2E,0x42,0x08,0x00,0x07,0x0A,0x02,\n0x07,0x02,0x0A,0x07,0x00,0x08,/*\"鰲\",6669*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x4A,0xAA,0xBF,0xEA,0xDC,0x6A,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0F,0x0A,0x0A,0x0F,0x00,/*\"鰭\",6670*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0x5F,0xD5,0x15,0x55,0xDF,0x0D,0x01,0x0D,0x01,0x0D,\n0x05,0x0A,0x0F,0x05,0x0A,0x0F,/*\"鰨\",6671*/},{\n\n0xF4,0x53,0xFA,0x56,0xFF,0x49,0x2F,0xF9,0x0F,0x29,0x4F,0x0D,0x01,0x0D,0x01,0x0D,\n0x02,0x01,0x0F,0x00,0x01,0x02,/*\"鰥\",6672*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x42,0x36,0x2A,0xE6,0x29,0x25,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0D,0x09,0x0F,0x09,0x0D,/*\"鰩\",6673*/},{\n\n0xF4,0x5B,0xF6,0x52,0xAF,0xFA,0xAF,0xEA,0xFF,0x08,0xF8,0x0D,0x01,0x0D,0x01,0x02,\n0x0F,0x02,0x08,0x07,0x08,0x0F,/*\"鰳\",6674*/},{\n\n0xF4,0x53,0xFA,0x56,0xFD,0x15,0x5F,0x55,0x5F,0x55,0x1D,0x0D,0x01,0x0D,0x01,0x0D,\n0x05,0x09,0x0F,0x01,0x05,0x09,/*\"鰾\",6675*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0xAD,0xA5,0x9F,0xA5,0xAD,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x0A,0x0A,0x0A,0x0A,0x0F,/*\"鱈\",6676*/},{\n\n0xF4,0x53,0xFA,0x56,0xF0,0x00,0x70,0x5F,0x75,0x5F,0x70,0x0D,0x01,0x0D,0x01,0x0D,\n0x00,0x09,0x0B,0x05,0x05,0x0B,/*\"鰻\",6677*/},{\n\n0x04,0xBF,0xEA,0xBE,0xAA,0xBE,0xE4,0xAB,0x92,0x2E,0x42,0x08,0x00,0x07,0x0A,0x02,\n0x07,0x02,0x0A,0x07,0x00,0x08,/*\"鰵\",6678*/},{\n\n0xF4,0x5B,0xF6,0x50,0xFE,0x22,0xAA,0xAA,0xFF,0xAA,0xFA,0x0D,0x01,0x0D,0x09,0x07,\n0x00,0x0F,0x02,0x07,0x0A,0x0F,/*\"鱅\",6679*/},{\n\n0xF4,0x5B,0xF6,0x50,0xFE,0x2A,0xF2,0x2A,0xA2,0xDE,0x32,0x0D,0x01,0x0D,0x09,0x07,\n0x09,0x07,0x09,0x05,0x03,0x0C,/*\"鱖\",6680*/},{\n\n0xF4,0x5B,0xF6,0x50,0xA2,0xEB,0xAA,0xFE,0xAA,0xEB,0xA2,0x0D,0x01,0x0D,0x01,0x00,\n0x0E,0x0A,0x0A,0x0A,0x0E,0x00,/*\"鱔\",6681*/},{\n\n0xF4,0x5B,0xF6,0x50,0xFA,0xAB,0xDE,0xCA,0xBE,0xAB,0xFA,0x0D,0x01,0x0D,0x01,0x02,\n0x06,0x0A,0x02,0x0A,0x0F,0x02,/*\"鱒\",6682*/},{\n\n0xF4,0x5B,0xF6,0x50,0xBE,0xAA,0xBF,0xAA,0xBF,0xAA,0xBE,0x0D,0x01,0x0D,0x01,0x08,\n0x0B,0x0E,0x0A,0x0E,0x0B,0x08,/*\"鱧\",6683*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x00,0xFE,0x12,0x12,0xFE,0x00,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x09,0x09,0x09,0x09,0x08,/*\"靼\",6684*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0xFC,0x84,0xFF,0x84,0xFC,0x80,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x06,0x01,0x06,0x08,0x00,/*\"鞅\",6685*/},{\n\n0xE2,0xAF,0xFA,0xAF,0x11,0xF2,0x28,0xBA,0xEF,0xBA,0x28,0x02,0x02,0x0F,0x02,0x08,\n0x07,0x0A,0x0A,0x0F,0x0A,0x0A,/*\"韃\",6686*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xEA,0x9A,0xEE,0xAA,0xE9,0x99,0xA8,0x02,0x02,0x0F,0x02,0x0F,\n0x00,0x0E,0x0A,0x0E,0x00,0x0F,/*\"鞽\",6687*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xEA,0x04,0xF3,0x92,0xFA,0x96,0xF0,0x02,0x02,0x0F,0x02,0x02,\n0x08,0x06,0x01,0x07,0x08,0x0C,/*\"鞔\",6688*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xFA,0xAF,0xFA,0xAE,0xFA,0xAF,0xEA,0x02,0x02,0x0F,0x0A,0x07,\n0x08,0x03,0x0A,0x02,0x0A,0x0E,/*\"韉\",6689*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x04,0xAB,0xAE,0xAA,0x02,0xFE,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0E,0x0A,0x0E,0x08,0x0F,/*\"鞫\",6690*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x48,0x29,0xDB,0x7D,0x0B,0x18,0x02,0x02,0x0F,0x02,0x0A,\n0x05,0x03,0x0F,0x03,0x05,0x09,/*\"鞣\",6691*/},{\n\n0x8A,0xBE,0xEB,0xBE,0x08,0xEA,0xAF,0xFA,0xAF,0xEA,0x08,0x06,0x04,0x0F,0x04,0x02,\n0x0F,0x02,0x03,0x0A,0x0F,0x02,/*\"韝\",6692*/},{\n\n0xE2,0xAF,0xFA,0xAF,0xE2,0x40,0xEA,0xBF,0xEA,0xAF,0xEA,0x02,0x02,0x0F,0x02,0x02,\n0x00,0x0F,0x02,0x07,0x0A,0x0F,/*\"鞴\",6693*/},{\n\n0x18,0xEF,0xA9,0xA9,0xEF,0x18,0x10,0xEC,0x03,0xEC,0x10,0x00,0x0F,0x02,0x0A,0x0F,\n0x00,0x08,0x07,0x00,0x0F,0x00,/*\"骱\",6694*/},{\n\n0x18,0xEF,0xA9,0xA9,0xEF,0x18,0x50,0xCF,0x41,0xDF,0x10,0x00,0x0F,0x02,0x0A,0x0F,\n0x00,0x08,0x05,0x02,0x05,0x08,/*\"骰\",6695*/},{\n\n0x18,0xEF,0xA9,0xA9,0xEF,0x18,0xC8,0x48,0x7F,0x48,0xC8,0x00,0x0F,0x02,0x0A,0x0F,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"骷\",6696*/},{\n\n0x18,0xEF,0xA9,0xA9,0xEF,0x18,0xFE,0xAB,0xAA,0xBE,0xA0,0x00,0x0F,0x02,0x0A,0x0F,\n0x08,0x06,0x00,0x0A,0x08,0x07,/*\"鶻\",6697*/},{\n\n0x18,0xEF,0xA9,0xA9,0xEF,0x18,0xFE,0x22,0xFE,0x21,0x21,0x00,0x0F,0x02,0x0A,0x0F,\n0x00,0x0F,0x04,0x0B,0x04,0x0E,/*\"骶\",6698*/},{\n\n0x18,0xEF,0xA9,0xEF,0x18,0xFE,0x12,0x92,0x91,0x91,0x90,0x00,0x0F,0x02,0x0F,0x08,\n0x07,0x00,0x0F,0x04,0x04,0x0F,/*\"骺\",6699*/},{\n\n0x18,0xEF,0xA9,0xEF,0x18,0x44,0xAB,0x92,0x92,0xAE,0x40,0x00,0x0F,0x02,0x0F,0x00,\n0x00,0x0F,0x04,0x04,0x0F,0x00,/*\"骼\",6700*/},{\n\n0x18,0xEF,0xA9,0xEF,0x18,0x5F,0x55,0xFF,0x55,0x5F,0x40,0x00,0x0F,0x02,0x0F,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"髁\",6701*/},{\n\n0x18,0xEF,0xA9,0xA9,0xEF,0x18,0x7C,0xD6,0x7D,0x54,0x7C,0x00,0x0F,0x02,0x0A,0x0F,\n0x02,0x03,0x02,0x0F,0x02,0x02,/*\"髀\",6702*/},{\n\n0x18,0xEF,0xA9,0xEF,0x18,0xBE,0xAA,0xFF,0xAA,0xBE,0x88,0x00,0x0F,0x02,0x0F,0x00,\n0x0A,0x0B,0x04,0x04,0x0B,0x08,/*\"髏\",6703*/},{\n\n0x18,0xEF,0xA9,0xEF,0x18,0x46,0x52,0x2E,0x2B,0x5A,0x46,0x00,0x0F,0x02,0x0F,0x00,\n0x00,0x0F,0x05,0x05,0x0F,0x00,/*\"髂\",6704*/},{\n\n0x18,0xEF,0xA9,0xEF,0x1E,0xEA,0xBE,0xAB,0xBE,0xEA,0x06,0x00,0x0F,0x02,0x0F,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x0C,/*\"髖\",6705*/},{\n\n0x18,0xEF,0xA9,0xEF,0x5E,0xEA,0xAA,0xBB,0xAA,0xEA,0x06,0x00,0x0F,0x02,0x0F,0x00,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"髕\",6706*/},{\n\n0x18,0xEF,0xA9,0xA9,0xEF,0x38,0xD7,0x5D,0xF7,0x55,0xF7,0x00,0x0F,0x02,0x0A,0x0F,\n0x00,0x05,0x05,0x07,0x0D,0x0F,/*\"髑\",6707*/},{\n\n0x7C,0x56,0xFD,0x54,0xFC,0x00,0x90,0x54,0xFF,0x54,0x90,0x08,0x07,0x00,0x07,0x0A,\n0x0B,0x08,0x08,0x0B,0x08,0x0C,/*\"魅\",6708*/},{\n\n0x7C,0x56,0xFD,0x54,0xFC,0x00,0xC4,0x3F,0x54,0x95,0x74,0x08,0x07,0x00,0x07,0x0A,\n0x0B,0x08,0x0A,0x09,0x08,0x0D,/*\"魃\",6709*/},{\n\n0x00,0xFF,0x01,0xEF,0xA5,0xB5,0xFF,0xA1,0xB5,0xEF,0x15,0x08,0x07,0x08,0x0B,0x06,\n0x03,0x06,0x0A,0x0E,0x0B,0x0C,/*\"魘\",6710*/},{\n\n0x7C,0x56,0xFD,0x54,0xFD,0x55,0x25,0xFF,0x55,0x25,0xFD,0x08,0x07,0x00,0x07,0x0A,\n0x0B,0x08,0x08,0x08,0x09,0x0D,/*\"魎\",6711*/},{\n\n0x7C,0x56,0xFD,0x54,0xFC,0x00,0xFD,0x54,0x57,0x54,0xFD,0x08,0x07,0x00,0x07,0x0A,\n0x0B,0x09,0x08,0x08,0x09,0x0D,/*\"魈\",6712*/},{\n\n0x7C,0x56,0xFD,0x54,0xFE,0x2A,0xEE,0xBA,0xAE,0x2A,0xFE,0x08,0x07,0x00,0x07,0x0A,\n0x0B,0x08,0x08,0x08,0x09,0x0D,/*\"魍\",6713*/},{\n\n0x7C,0x56,0xFD,0x54,0xFC,0x00,0xBA,0xB6,0xEB,0xB6,0xBA,0x08,0x07,0x00,0x07,0x0A,\n0x0B,0x0F,0x08,0x0B,0x0A,0x0F,/*\"魑\",6714*/},{\n\n0x5A,0x35,0x9A,0x80,0x7E,0xAB,0x4E,0x80,0xFF,0x25,0x1B,0x01,0x01,0x0F,0x0D,0x05,\n0x07,0x05,0x0F,0x08,0x09,0x01,/*\"饗\",6715*/},{\n\n0x00,0xFF,0x01,0x9F,0xC5,0xB5,0xDF,0xA1,0xD5,0x8F,0x95,0x08,0x07,0x01,0x00,0x0F,\n0x0A,0x03,0x06,0x0B,0x0C,0x0A,/*\"饜\",6716*/},{\n\n0xA9,0xAF,0xD5,0xCD,0xA1,0xD4,0xAA,0xD5,0xEA,0x94,0x88,0x00,0x00,0x0F,0x0A,0x02,\n0x03,0x02,0x06,0x0B,0x0C,0x0A,/*\"餮\",6717*/},{\n\n0x84,0x97,0xDD,0xF7,0xA4,0xDC,0xA4,0xDF,0xD5,0xB5,0xAC,0x00,0x00,0x0F,0x0A,0x02,\n0x03,0x02,0x06,0x0B,0x0C,0x0A,/*\"饕\",6718*/},{\n\n0x52,0x5A,0xB6,0x92,0x4A,0xBF,0x6A,0xAA,0xBE,0x2A,0x2A,0x01,0x01,0x0F,0x0D,0x05,\n0x07,0x05,0x0F,0x08,0x09,0x01,/*\"饔\",6719*/},{\n\n0x40,0x7F,0xD5,0x55,0x55,0x41,0x00,0x88,0x44,0x22,0x11,0x06,0x05,0x04,0x04,0x05,\n0x06,0x08,0x08,0x04,0x02,0x01,/*\"髟\",6720*/},{\n\n0x50,0x7F,0x55,0x55,0x75,0x50,0x04,0x12,0x49,0x24,0x10,0x09,0x09,0x05,0x03,0x01,\n0x01,0x01,0x07,0x09,0x09,0x0D,/*\"髡\",6721*/},{\n\n0x14,0x5F,0x54,0x56,0xDD,0xB4,0xA0,0xA4,0x12,0x09,0x04,0x04,0x05,0x05,0x05,0x07,\n0x0A,0x0A,0x0A,0x0A,0x08,0x0C,/*\"髦\",6722*/},{\n\n0x0A,0xEF,0xAA,0xAB,0xAE,0xFA,0xA0,0xAA,0xAA,0xEA,0x05,0x02,0x0F,0x02,0x02,0x02,\n0x03,0x02,0x02,0x0A,0x0F,0x02,/*\"髯\",6723*/},{\n\n0x54,0x5F,0xD4,0x56,0x5D,0x54,0x40,0x44,0x52,0x49,0xC4,0x02,0x01,0x0E,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0F,0x01,/*\"髫\",6724*/},{\n\n0x2A,0xAF,0xAA,0xAB,0xAE,0xFA,0xA0,0xAA,0xAA,0xAA,0x25,0x00,0x0E,0x0A,0x0A,0x0A,\n0x0A,0x0A,0x0A,0x0A,0x0E,0x00,/*\"髻\",6725*/},{\n\n0x50,0x7F,0x55,0xD5,0x75,0x50,0x04,0x92,0x49,0x24,0x90,0x08,0x0F,0x08,0x07,0x05,\n0x05,0x00,0x07,0x0A,0x09,0x0C,/*\"髭\",6726*/},{\n\n0x14,0x9F,0xD4,0x36,0x9D,0x94,0x80,0xE4,0x92,0x89,0x84,0x01,0x00,0x0F,0x00,0x04,\n0x02,0x01,0x0F,0x01,0x02,0x04,/*\"髹\",6727*/},{\n\n0x4A,0x4F,0x6A,0xCB,0x4E,0x6A,0x40,0xCA,0x6A,0x4A,0x45,0x02,0x02,0x01,0x07,0x09,\n0x09,0x0D,0x0F,0x09,0x0E,0x02,/*\"鬈\",6728*/},{\n\n0x8A,0xAF,0xEA,0x9B,0x8E,0x0A,0xC0,0x0A,0xEA,0x8A,0x45,0x04,0x02,0x0F,0x02,0x04,\n0x00,0x09,0x04,0x03,0x04,0x08,/*\"鬏\",6729*/},{\n\n0x5A,0x2F,0xAA,0xAB,0xAE,0xEA,0xA8,0xAA,0xEA,0xAD,0x1D,0x01,0x07,0x0C,0x05,0x06,\n0x04,0x05,0x06,0x0C,0x07,0x00,/*\"鬢\",6730*/},{\n\n0x14,0xDF,0x54,0x56,0xDD,0x54,0xC0,0x44,0x52,0xC9,0x04,0x09,0x09,0x05,0x0F,0x09,\n0x03,0x05,0x05,0x0B,0x09,0x09,/*\"鬟\",6731*/},{\n\n0x14,0xDF,0xB4,0x96,0xDD,0xB4,0x80,0xC4,0xB2,0x89,0x04,0x00,0x0F,0x0A,0x02,0x00,\n0x0F,0x0A,0x00,0x03,0x04,0x0E,/*\"鬣\",6732*/},{\n\n0x00,0xFE,0x2A,0x1A,0x3E,0x8A,0x53,0x0A,0x3E,0x9A,0x2A,0x08,0x07,0x00,0x08,0x0D,\n0x0D,0x0B,0x0B,0x09,0x0C,0x08,/*\"麼\",6733*/},{\n\n0x00,0xFE,0x2A,0x1A,0x7E,0x4A,0xD3,0xAA,0xBE,0x1A,0x2A,0x08,0x07,0x00,0x04,0x05,\n0x05,0x07,0x0A,0x0A,0x0A,0x0C,/*\"麾\",6734*/},{\n\n0x00,0xFE,0x2A,0x9A,0xFE,0x8A,0x93,0x8A,0x7E,0x1A,0x2A,0x08,0x07,0x0A,0x06,0x02,\n0x0B,0x0E,0x02,0x02,0x07,0x0A,/*\"縻\",6735*/},{\n\n0x00,0xFE,0x2A,0xEA,0xBE,0xAA,0x2B,0xFE,0xAA,0xBA,0xC2,0x08,0x07,0x00,0x08,0x06,\n0x02,0x02,0x06,0x08,0x0C,0x00,/*\"麂\",6736*/},{\n\n0x00,0xFE,0x2A,0xAA,0xBE,0xAA,0xAB,0xBE,0xAA,0x7A,0x02,0x08,0x07,0x0A,0x0A,0x06,\n0x02,0x0F,0x02,0x06,0x0A,0x0A,/*\"麇\",6737*/},{\n\n0x00,0xFE,0x2A,0xAA,0xBE,0xAA,0xEB,0xBE,0xAA,0xBA,0x02,0x08,0x07,0x08,0x0A,0x0A,\n0x0A,0x0F,0x0A,0x0A,0x0A,0x08,/*\"麈\",6738*/},{\n\n0x00,0xFE,0x2A,0xAA,0x3E,0x2A,0xAB,0x3E,0x2A,0xBA,0x02,0x08,0x07,0x02,0x0A,0x07,\n0x02,0x0F,0x02,0x07,0x0A,0x02,/*\"麋\",6739*/},{\n\n0x00,0xFE,0x2A,0xFF,0xAA,0x3A,0x04,0xFF,0x54,0xFF,0x04,0x08,0x07,0x00,0x0F,0x04,\n0x02,0x09,0x05,0x01,0x05,0x09,/*\"麒\",6740*/},{\n\n0x00,0xFE,0xAA,0xAA,0x7E,0xEA,0xAB,0xFE,0x6A,0xBA,0x82,0x08,0x07,0x08,0x0A,0x0E,\n0x0A,0x0F,0x0A,0x0E,0x0A,0x08,/*\"鏖\",6741*/},{\n\n0x00,0xFE,0x2A,0xEA,0xBE,0xEA,0x2B,0xBE,0xAA,0xFA,0x82,0x08,0x07,0x0A,0x07,0x0A,\n0x0F,0x00,0x02,0x08,0x0F,0x00,/*\"麝\",6742*/},{\n\n0xFE,0x2A,0xFF,0xAA,0x3A,0x95,0x6E,0xC4,0x5F,0xEE,0x55,0x07,0x00,0x0F,0x04,0x02,\n0x09,0x06,0x01,0x02,0x0F,0x02,/*\"麟\",6743*/},{\n\n0x08,0xE4,0x3E,0xA1,0x28,0xE8,0x2F,0xA8,0x35,0xE6,0x34,0x04,0x0D,0x05,0x05,0x0D,\n0x07,0x0D,0x05,0x05,0x0D,0x04,/*\"黛\",6744*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x00,0xBC,0x20,0xFF,0x20,0xBC,0x0A,0x02,0x0D,0x01,0x0D,\n0x00,0x07,0x04,0x07,0x04,0x0F,/*\"黜\",6745*/},{\n\n0x5F,0x55,0xFF,0x55,0x9F,0x56,0xB9,0x04,0xFF,0x04,0xFC,0x0A,0x02,0x0D,0x01,0x0D,\n0x01,0x09,0x06,0x09,0x08,0x07,/*\"黝\",6746*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x00,0xA4,0xA4,0xBF,0xA4,0xA4,0x0A,0x02,0x0D,0x01,0x0D,\n0x00,0x0F,0x04,0x04,0x04,0x0F,/*\"黠\",6747*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x00,0x44,0xAB,0x52,0x6E,0xC0,0x0A,0x02,0x0D,0x01,0x0D,\n0x00,0x09,0x08,0x05,0x02,0x01,/*\"黟\",6748*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x20,0x96,0x65,0x44,0xD6,0x2C,0x0A,0x02,0x0D,0x01,0x0D,\n0x01,0x08,0x05,0x02,0x05,0x08,/*\"黢\",6749*/},{\n\n0x5F,0x55,0xFF,0x55,0x3F,0xEA,0xBA,0xAF,0xBA,0xEA,0x3A,0x0A,0x02,0x0D,0x01,0x0D,\n0x0B,0x06,0x02,0x06,0x0B,0x00,/*\"黷\",6750*/},{\n\n0x14,0xED,0x25,0xBF,0x25,0xEC,0x33,0xAA,0x26,0xF2,0x1E,0x04,0x0D,0x05,0x05,0x0D,\n0x07,0x0D,0x05,0x05,0x0D,0x04,/*\"黧\",6751*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x00,0xF4,0x95,0x96,0x94,0xF4,0x0A,0x02,0x0D,0x01,0x0D,\n0x04,0x02,0x08,0x0F,0x02,0x04,/*\"黥\",6752*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0xAC,0x76,0xA5,0x74,0xAE,0xB4,0x0A,0x02,0x0D,0x01,0x0D,\n0x00,0x05,0x0A,0x05,0x02,0x00,/*\"黲\",6753*/},{\n\n0x5F,0x55,0xFF,0x55,0x5F,0x00,0xD6,0x5A,0x53,0x5A,0xD6,0x0A,0x02,0x0D,0x01,0x0D,\n0x00,0x0F,0x05,0x05,0x05,0x0F,/*\"黯\",6754*/},{\n\n0xDE,0x95,0xD0,0x95,0xDF,0x10,0x2C,0xE3,0x20,0x23,0xEC,0x0F,0x0A,0x07,0x0A,0x07,\n0x08,0x06,0x01,0x08,0x08,0x07,/*\"鼢\",6755*/},{\n\n0xDE,0x95,0xD0,0x95,0xDF,0x00,0xF8,0x48,0xFF,0x48,0xF8,0x0F,0x0A,0x07,0x0A,0x07,\n0x08,0x0F,0x04,0x07,0x04,0x0F,/*\"鼬\",6756*/},{\n\n0xDE,0x95,0xD0,0x95,0xDF,0x00,0xA5,0xBD,0xA7,0xBD,0x21,0x0F,0x0A,0x07,0x0A,0x07,\n0x08,0x0F,0x04,0x04,0x0F,0x00,/*\"鼯\",6757*/},{\n\n0xDE,0x95,0xD0,0x95,0xDF,0x00,0xFF,0x81,0xBF,0xEB,0xBF,0x0F,0x0A,0x07,0x0A,0x07,\n0x08,0x0F,0x08,0x0D,0x0A,0x0D,/*\"鼴\",6758*/},{\n\n0xDE,0x95,0xD0,0x95,0xDF,0x02,0xB6,0xEA,0xA5,0x91,0xC5,0x0F,0x0A,0x07,0x0A,0x07,\n0x08,0x0A,0x06,0x03,0x06,0x0A,/*\"鼷\",6759*/},{\n\n0xF8,0xAE,0xFB,0xAE,0xF8,0x08,0xFF,0x08,0xF8,0x00,0x00,0x0A,0x06,0x02,0x0E,0x0A,\n0x04,0x03,0x00,0x07,0x08,0x0E,/*\"鼽\",6760*/},{\n\n0x00,0xF8,0xAE,0xFB,0xAE,0xF8,0x40,0x42,0xFE,0x42,0x40,0x02,0x0A,0x06,0x02,0x0E,\n0x02,0x02,0x00,0x0F,0x00,0x00,/*\"鼾\",6761*/},{\n\n0xF8,0xAE,0xFB,0xAE,0xF8,0x12,0xEA,0xA6,0xBF,0xA6,0xEA,0x0A,0x06,0x02,0x0E,0x02,\n0x08,0x0B,0x0A,0x0A,0x0A,0x0B,/*\"齄\",6762*/}};\n\n\n#endif"
  },
  {
    "path": "uv-k5font/uv-k5font_full/font.h",
    "content": "#define CHN_FONT_WIDTH 11\n#define CHN_FONT_HIGH   12\n#define CHN_FONT_NUM  6763\ntypedef unsigned char uint8_t;\nextern unsigned char new_font[CHN_FONT_NUM][22] ;\n"
  },
  {
    "path": "uv-k5font/uv-k5font_full/gb2312_f.txt",
    "content": "啊\n阿\n埃\n挨\n哎\n唉\n哀\n皚\n癌\n藹\n矮\n艾\n礙\n愛\n隘\n鞍\n氨\n安\n俺\n按\n暗\n岸\n胺\n案\n骯\n昂\n盎\n凹\n敖\n熬\n翱\n襖\n傲\n奧\n懊\n澳\n芭\n捌\n扒\n叭\n吧\n笆\n八\n疤\n巴\n拔\n跋\n靶\n把\n耙\n壩\n霸\n罷\n爸\n白\n柏\n百\n擺\n佰\n敗\n拜\n稗\n斑\n班\n搬\n扳\n般\n頒\n板\n版\n扮\n拌\n伴\n瓣\n半\n辦\n絆\n邦\n幫\n梆\n榜\n膀\n綁\n棒\n磅\n蚌\n鎊\n傍\n謗\n苞\n胞\n包\n褒\n剝\n薄\n雹\n保\n堡\n飽\n寶\n抱\n報\n暴\n豹\n鮑\n爆\n杯\n碑\n悲\n卑\n北\n輩\n背\n貝\n鋇\n倍\n狽\n備\n憊\n焙\n被\n奔\n苯\n本\n笨\n崩\n繃\n甭\n泵\n蹦\n迸\n逼\n鼻\n比\n鄙\n筆\n彼\n碧\n蓖\n蔽\n畢\n斃\n毖\n幣\n庇\n痹\n閉\n敝\n弊\n必\n闢\n壁\n臂\n避\n陛\n鞭\n邊\n編\n貶\n扁\n便\n變\n卞\n辨\n辯\n辮\n遍\n標\n彪\n膘\n表\n鱉\n憋\n別\n癟\n彬\n斌\n瀕\n濱\n賓\n擯\n兵\n冰\n柄\n丙\n秉\n餅\n炳\n病\n並\n玻\n菠\n播\n撥\n鉢\n波\n博\n勃\n搏\n鉑\n箔\n伯\n帛\n舶\n脖\n膊\n渤\n泊\n駁\n捕\n卜\n哺\n補\n埠\n不\n布\n步\n簿\n部\n怖\n擦\n猜\n裁\n材\n才\n財\n睬\n踩\n採\n彩\n菜\n蔡\n餐\n參\n蠶\n殘\n慚\n慘\n燦\n蒼\n艙\n倉\n滄\n藏\n操\n糙\n槽\n曹\n草\n廁\n策\n側\n冊\n測\n層\n蹭\n插\n叉\n茬\n茶\n查\n碴\n搽\n察\n岔\n差\n詫\n拆\n柴\n豺\n攙\n摻\n蟬\n饞\n讒\n纏\n鏟\n產\n闡\n顫\n昌\n猖\n場\n嘗\n常\n長\n償\n腸\n廠\n敞\n暢\n唱\n倡\n超\n抄\n鈔\n朝\n嘲\n潮\n巢\n吵\n炒\n車\n扯\n撤\n掣\n徹\n澈\n郴\n臣\n辰\n塵\n晨\n忱\n沉\n陳\n趁\n襯\n撐\n稱\n城\n橙\n成\n呈\n乘\n程\n懲\n澄\n誠\n承\n逞\n騁\n秤\n喫\n癡\n持\n匙\n池\n遲\n弛\n馳\n恥\n齒\n侈\n尺\n赤\n翅\n斥\n熾\n充\n衝\n蟲\n崇\n寵\n抽\n酬\n疇\n躊\n稠\n愁\n籌\n仇\n綢\n瞅\n醜\n臭\n初\n出\n櫥\n廚\n躇\n鋤\n雛\n滁\n除\n楚\n礎\n儲\n矗\n搐\n觸\n處\n揣\n川\n穿\n椽\n傳\n船\n喘\n串\n瘡\n窗\n幢\n牀\n闖\n創\n吹\n炊\n捶\n錘\n垂\n春\n椿\n醇\n脣\n淳\n純\n蠢\n戳\n綽\n疵\n茨\n磁\n雌\n辭\n慈\n瓷\n詞\n此\n刺\n賜\n次\n聰\n蔥\n囪\n匆\n從\n叢\n湊\n粗\n醋\n簇\n促\n躥\n篡\n竄\n摧\n崔\n催\n脆\n瘁\n粹\n淬\n翠\n村\n存\n寸\n磋\n撮\n搓\n措\n挫\n錯\n搭\n達\n答\n瘩\n打\n大\n呆\n歹\n傣\n戴\n帶\n殆\n代\n貸\n袋\n待\n逮\n怠\n耽\n擔\n丹\n單\n鄲\n撣\n膽\n旦\n氮\n但\n憚\n淡\n誕\n彈\n蛋\n當\n擋\n黨\n蕩\n檔\n刀\n搗\n蹈\n倒\n島\n禱\n導\n到\n稻\n悼\n道\n盜\n德\n得\n的\n蹬\n燈\n登\n等\n瞪\n凳\n鄧\n堤\n低\n滴\n迪\n敵\n笛\n狄\n滌\n翟\n嫡\n抵\n底\n地\n蒂\n第\n帝\n弟\n遞\n締\n顛\n掂\n滇\n碘\n點\n典\n靛\n墊\n電\n佃\n甸\n店\n惦\n奠\n澱\n殿\n碉\n叼\n雕\n凋\n刁\n掉\n吊\n釣\n調\n跌\n爹\n碟\n蝶\n迭\n諜\n疊\n丁\n盯\n叮\n釘\n頂\n鼎\n錠\n定\n訂\n丟\n東\n冬\n董\n懂\n動\n棟\n侗\n恫\n凍\n洞\n兜\n抖\n鬥\n陡\n豆\n逗\n痘\n都\n督\n毒\n犢\n獨\n讀\n堵\n睹\n賭\n杜\n鍍\n肚\n度\n渡\n妒\n端\n短\n鍛\n段\n斷\n緞\n堆\n兌\n隊\n對\n墩\n噸\n蹲\n敦\n頓\n囤\n鈍\n盾\n遁\n掇\n哆\n多\n奪\n垛\n躲\n朵\n跺\n舵\n剁\n惰\n墮\n蛾\n峨\n鵝\n俄\n額\n訛\n娥\n惡\n厄\n扼\n遏\n鄂\n餓\n恩\n而\n兒\n耳\n爾\n餌\n洱\n二\n貳\n發\n罰\n筏\n伐\n乏\n閥\n法\n琺\n藩\n帆\n番\n翻\n樊\n礬\n釩\n繁\n凡\n煩\n反\n返\n範\n販\n犯\n飯\n泛\n坊\n芳\n方\n肪\n房\n防\n妨\n仿\n訪\n紡\n放\n菲\n非\n啡\n飛\n肥\n匪\n誹\n吠\n肺\n廢\n沸\n費\n芬\n酚\n吩\n氛\n分\n紛\n墳\n焚\n汾\n粉\n奮\n份\n忿\n憤\n糞\n豐\n封\n楓\n蜂\n峯\n鋒\n風\n瘋\n烽\n逢\n馮\n縫\n諷\n奉\n鳳\n佛\n否\n夫\n敷\n膚\n孵\n扶\n拂\n輻\n幅\n氟\n符\n伏\n俘\n服\n浮\n涪\n福\n袱\n弗\n甫\n撫\n輔\n俯\n釜\n斧\n脯\n腑\n府\n腐\n赴\n副\n覆\n賦\n復\n傅\n付\n阜\n父\n腹\n負\n富\n訃\n附\n婦\n縛\n咐\n噶\n嘎\n該\n改\n概\n鈣\n蓋\n溉\n幹\n甘\n杆\n柑\n竿\n肝\n趕\n感\n稈\n敢\n贛\n岡\n剛\n鋼\n缸\n肛\n綱\n崗\n港\n槓\n篙\n皋\n高\n膏\n羔\n糕\n搞\n鎬\n稿\n告\n哥\n歌\n擱\n戈\n鴿\n胳\n疙\n割\n革\n葛\n格\n蛤\n閣\n隔\n鉻\n個\n各\n給\n根\n跟\n耕\n更\n庚\n羹\n埂\n耿\n梗\n工\n攻\n功\n恭\n龔\n供\n躬\n公\n宮\n弓\n鞏\n汞\n拱\n貢\n共\n鉤\n勾\n溝\n苟\n狗\n垢\n構\n購\n夠\n辜\n菇\n咕\n箍\n估\n沽\n孤\n姑\n鼓\n古\n蠱\n骨\n谷\n股\n故\n顧\n固\n僱\n刮\n瓜\n剮\n寡\n掛\n褂\n乖\n拐\n怪\n棺\n關\n官\n冠\n觀\n管\n館\n罐\n慣\n灌\n貫\n光\n廣\n逛\n瑰\n規\n圭\n硅\n歸\n龜\n閨\n軌\n鬼\n詭\n癸\n桂\n櫃\n跪\n貴\n劊\n輥\n滾\n棍\n鍋\n郭\n國\n果\n裹\n過\n哈\n骸\n孩\n海\n氦\n亥\n害\n駭\n酣\n憨\n邯\n韓\n含\n涵\n寒\n函\n喊\n罕\n翰\n撼\n捍\n旱\n憾\n悍\n焊\n汗\n漢\n夯\n杭\n航\n壕\n嚎\n豪\n毫\n郝\n好\n耗\n號\n浩\n呵\n喝\n荷\n菏\n核\n禾\n和\n何\n合\n盒\n貉\n閡\n河\n涸\n赫\n褐\n鶴\n賀\n嘿\n黑\n痕\n很\n狠\n恨\n哼\n亨\n橫\n衡\n恆\n轟\n哄\n烘\n虹\n鴻\n洪\n宏\n弘\n紅\n喉\n侯\n猴\n吼\n厚\n候\n後\n呼\n乎\n忽\n瑚\n壺\n葫\n胡\n蝴\n狐\n糊\n湖\n弧\n虎\n唬\n護\n互\n滬\n戶\n花\n譁\n華\n猾\n滑\n畫\n劃\n化\n話\n槐\n徊\n懷\n淮\n壞\n歡\n環\n桓\n還\n緩\n換\n患\n喚\n瘓\n豢\n煥\n渙\n宦\n幻\n荒\n慌\n黃\n磺\n蝗\n簧\n皇\n凰\n惶\n煌\n晃\n幌\n恍\n謊\n灰\n揮\n輝\n徽\n恢\n蛔\n回\n毀\n悔\n慧\n卉\n惠\n晦\n賄\n穢\n會\n燴\n匯\n諱\n誨\n繪\n葷\n昏\n婚\n魂\n渾\n混\n豁\n活\n夥\n火\n獲\n或\n惑\n霍\n貨\n禍\n擊\n圾\n基\n機\n畸\n稽\n積\n箕\n肌\n飢\n跡\n激\n譏\n雞\n姬\n績\n緝\n吉\n極\n棘\n輯\n籍\n集\n及\n急\n疾\n汲\n即\n嫉\n級\n擠\n幾\n脊\n己\n薊\n技\n冀\n季\n伎\n祭\n劑\n悸\n濟\n寄\n寂\n計\n記\n既\n忌\n際\n妓\n繼\n紀\n嘉\n枷\n夾\n佳\n家\n加\n莢\n頰\n賈\n甲\n鉀\n假\n稼\n價\n架\n駕\n嫁\n殲\n監\n堅\n尖\n箋\n間\n煎\n兼\n肩\n艱\n奸\n緘\n繭\n檢\n柬\n鹼\n礆\n揀\n撿\n簡\n儉\n剪\n減\n薦\n檻\n鑑\n踐\n賤\n見\n鍵\n箭\n件\n健\n艦\n劍\n餞\n漸\n濺\n澗\n建\n僵\n姜\n將\n漿\n江\n疆\n蔣\n槳\n獎\n講\n匠\n醬\n降\n蕉\n椒\n礁\n焦\n膠\n交\n郊\n澆\n驕\n嬌\n嚼\n攪\n鉸\n矯\n僥\n腳\n狡\n角\n餃\n繳\n絞\n剿\n教\n酵\n轎\n較\n叫\n窖\n揭\n接\n皆\n秸\n街\n階\n截\n劫\n節\n桔\n傑\n捷\n睫\n竭\n潔\n結\n解\n姐\n戒\n藉\n芥\n界\n借\n介\n疥\n誡\n屆\n巾\n筋\n斤\n金\n今\n津\n襟\n緊\n錦\n僅\n謹\n進\n靳\n晉\n禁\n近\n燼\n浸\n盡\n勁\n荊\n兢\n莖\n睛\n晶\n鯨\n京\n驚\n精\n粳\n經\n井\n警\n景\n頸\n靜\n境\n敬\n鏡\n徑\n痙\n靖\n竟\n競\n淨\n炯\n窘\n揪\n究\n糾\n玖\n韭\n久\n灸\n九\n酒\n廄\n救\n舊\n臼\n舅\n咎\n就\n疚\n鞠\n拘\n狙\n疽\n居\n駒\n菊\n局\n咀\n矩\n舉\n沮\n聚\n拒\n據\n巨\n具\n距\n踞\n鋸\n俱\n句\n懼\n炬\n劇\n捐\n鵑\n娟\n倦\n眷\n卷\n絹\n撅\n攫\n抉\n掘\n倔\n爵\n覺\n決\n訣\n絕\n均\n菌\n鈞\n軍\n君\n峻\n俊\n竣\n浚\n郡\n駿\n喀\n咖\n卡\n咯\n開\n揩\n楷\n凱\n慨\n刊\n堪\n勘\n坎\n砍\n看\n康\n慷\n糠\n扛\n抗\n亢\n炕\n考\n拷\n烤\n靠\n坷\n苛\n柯\n棵\n磕\n顆\n科\n殼\n咳\n可\n渴\n克\n刻\n客\n課\n肯\n啃\n墾\n懇\n坑\n吭\n空\n恐\n孔\n控\n摳\n口\n扣\n寇\n枯\n哭\n窟\n苦\n酷\n庫\n褲\n誇\n垮\n挎\n跨\n胯\n塊\n筷\n儈\n快\n寬\n款\n匡\n筐\n狂\n框\n礦\n眶\n曠\n況\n虧\n盔\n巋\n窺\n葵\n奎\n魁\n傀\n饋\n愧\n潰\n坤\n昆\n捆\n困\n括\n擴\n廓\n闊\n垃\n拉\n喇\n蠟\n臘\n辣\n啦\n萊\n來\n賴\n藍\n婪\n欄\n攔\n籃\n闌\n蘭\n瀾\n讕\n攬\n覽\n懶\n纜\n爛\n濫\n琅\n榔\n狼\n廊\n郎\n朗\n浪\n撈\n勞\n牢\n老\n佬\n姥\n酪\n烙\n澇\n勒\n樂\n雷\n鐳\n蕾\n磊\n累\n儡\n壘\n擂\n肋\n類\n淚\n棱\n楞\n冷\n釐\n梨\n犁\n黎\n籬\n狸\n離\n漓\n理\n李\n裏\n鯉\n禮\n莉\n荔\n吏\n慄\n麗\n厲\n勵\n礫\n歷\n利\n傈\n例\n俐\n痢\n立\n粒\n瀝\n隸\n力\n璃\n哩\n倆\n聯\n蓮\n連\n鐮\n廉\n憐\n漣\n簾\n斂\n臉\n鏈\n戀\n煉\n練\n糧\n涼\n梁\n粱\n良\n兩\n輛\n量\n晾\n亮\n諒\n撩\n聊\n僚\n療\n燎\n寥\n遼\n潦\n了\n撂\n鐐\n廖\n料\n列\n裂\n烈\n劣\n獵\n琳\n林\n磷\n霖\n臨\n鄰\n鱗\n淋\n凜\n賃\n吝\n拎\n玲\n菱\n零\n齡\n鈴\n伶\n羚\n凌\n靈\n陵\n嶺\n領\n另\n令\n溜\n琉\n榴\n硫\n餾\n留\n劉\n瘤\n流\n柳\n六\n龍\n聾\n嚨\n籠\n窿\n隆\n壟\n攏\n隴\n樓\n婁\n摟\n簍\n漏\n陋\n蘆\n盧\n顱\n廬\n爐\n擄\n滷\n虜\n魯\n麓\n碌\n露\n路\n賂\n鹿\n潞\n祿\n錄\n陸\n戮\n驢\n呂\n鋁\n侶\n旅\n履\n屢\n縷\n慮\n氯\n律\n率\n濾\n綠\n巒\n攣\n孿\n灤\n卵\n亂\n掠\n略\n掄\n輪\n倫\n侖\n淪\n綸\n論\n蘿\n螺\n羅\n邏\n鑼\n籮\n騾\n裸\n落\n洛\n駱\n絡\n媽\n麻\n瑪\n碼\n螞\n馬\n罵\n嘛\n嗎\n埋\n買\n麥\n賣\n邁\n脈\n瞞\n饅\n蠻\n滿\n蔓\n曼\n慢\n漫\n謾\n芒\n茫\n盲\n氓\n忙\n莽\n貓\n茅\n錨\n毛\n矛\n鉚\n卯\n茂\n冒\n帽\n貌\n貿\n麼\n玫\n枚\n梅\n酶\n黴\n煤\n沒\n眉\n媒\n鎂\n每\n美\n昧\n寐\n妹\n媚\n門\n悶\n們\n萌\n蒙\n檬\n盟\n錳\n猛\n夢\n孟\n眯\n醚\n靡\n糜\n迷\n謎\n彌\n米\n祕\n覓\n泌\n蜜\n密\n冪\n棉\n眠\n綿\n冕\n免\n勉\n娩\n緬\n面\n苗\n描\n瞄\n藐\n秒\n渺\n廟\n妙\n蔑\n滅\n民\n抿\n皿\n敏\n憫\n閩\n明\n螟\n鳴\n銘\n名\n命\n謬\n摸\n摹\n蘑\n模\n膜\n磨\n摩\n魔\n抹\n末\n莫\n墨\n默\n沫\n漠\n寞\n陌\n謀\n牟\n某\n拇\n牡\n畝\n姆\n母\n墓\n暮\n幕\n募\n慕\n木\n目\n睦\n牧\n穆\n拿\n哪\n吶\n鈉\n那\n娜\n納\n氖\n乃\n奶\n耐\n奈\n南\n男\n難\n囊\n撓\n腦\n惱\n鬧\n淖\n呢\n餒\n內\n嫩\n能\n妮\n霓\n倪\n泥\n尼\n擬\n你\n匿\n膩\n逆\n溺\n蔫\n拈\n年\n碾\n攆\n捻\n念\n娘\n釀\n鳥\n尿\n捏\n聶\n孽\n齧\n鑷\n鎳\n涅\n您\n檸\n獰\n凝\n寧\n擰\n濘\n牛\n扭\n鈕\n紐\n膿\n濃\n農\n弄\n奴\n努\n怒\n女\n暖\n虐\n瘧\n挪\n懦\n糯\n諾\n哦\n歐\n鷗\n毆\n藕\n嘔\n偶\n漚\n啪\n趴\n爬\n帕\n怕\n琶\n拍\n排\n牌\n徘\n湃\n派\n攀\n潘\n盤\n磐\n盼\n畔\n判\n叛\n乓\n龐\n旁\n耪\n胖\n拋\n咆\n刨\n炮\n袍\n跑\n泡\n呸\n胚\n培\n裴\n賠\n陪\n配\n佩\n沛\n噴\n盆\n砰\n抨\n烹\n澎\n彭\n蓬\n棚\n硼\n篷\n膨\n朋\n鵬\n捧\n碰\n坯\n砒\n霹\n批\n披\n劈\n琵\n毗\n啤\n脾\n疲\n皮\n匹\n痞\n僻\n屁\n譬\n篇\n偏\n片\n騙\n飄\n漂\n瓢\n票\n撇\n瞥\n拼\n頻\n貧\n品\n聘\n乒\n坪\n蘋\n萍\n平\n憑\n瓶\n評\n屏\n坡\n潑\n頗\n婆\n破\n魄\n迫\n粕\n剖\n撲\n鋪\n僕\n莆\n葡\n菩\n蒲\n埔\n樸\n圃\n普\n浦\n譜\n曝\n瀑\n期\n欺\n棲\n戚\n妻\n七\n悽\n漆\n柒\n沏\n其\n棋\n奇\n歧\n畦\n崎\n臍\n齊\n旗\n祈\n祁\n騎\n起\n豈\n乞\n企\n啓\n契\n砌\n器\n氣\n迄\n棄\n汽\n泣\n訖\n掐\n恰\n洽\n牽\n扦\n釺\n鉛\n千\n遷\n籤\n仟\n謙\n乾\n黔\n錢\n鉗\n前\n潛\n遣\n淺\n譴\n塹\n嵌\n欠\n歉\n槍\n嗆\n腔\n羌\n牆\n薔\n強\n搶\n橇\n鍬\n敲\n悄\n橋\n瞧\n喬\n僑\n巧\n鞘\n撬\n翹\n峭\n俏\n竅\n切\n茄\n且\n怯\n竊\n欽\n侵\n親\n秦\n琴\n勤\n芹\n擒\n禽\n寢\n沁\n青\n輕\n氫\n傾\n卿\n清\n擎\n晴\n氰\n情\n頃\n請\n慶\n瓊\n窮\n秋\n丘\n邱\n球\n求\n囚\n酋\n泅\n趨\n區\n蛆\n曲\n軀\n屈\n驅\n渠\n取\n娶\n齲\n趣\n去\n圈\n顴\n權\n醛\n泉\n全\n痊\n拳\n犬\n券\n勸\n缺\n炔\n瘸\n卻\n鵲\n榷\n確\n雀\n裙\n羣\n然\n燃\n冉\n染\n瓤\n壤\n攘\n嚷\n讓\n饒\n擾\n繞\n惹\n熱\n壬\n仁\n人\n忍\n韌\n任\n認\n刃\n妊\n紉\n扔\n仍\n日\n戎\n茸\n蓉\n榮\n融\n熔\n溶\n容\n絨\n冗\n揉\n柔\n肉\n茹\n蠕\n儒\n孺\n如\n辱\n乳\n汝\n入\n褥\n軟\n阮\n蕊\n瑞\n銳\n閏\n潤\n若\n弱\n撒\n灑\n薩\n腮\n鰓\n塞\n賽\n三\n叄\n傘\n散\n桑\n嗓\n喪\n搔\n騷\n掃\n嫂\n瑟\n色\n澀\n森\n僧\n莎\n砂\n殺\n剎\n沙\n紗\n傻\n啥\n煞\n篩\n曬\n珊\n苫\n杉\n山\n刪\n煽\n衫\n閃\n陝\n擅\n贍\n膳\n善\n汕\n扇\n繕\n墒\n傷\n商\n賞\n晌\n上\n尚\n裳\n梢\n捎\n稍\n燒\n芍\n勺\n韶\n少\n哨\n邵\n紹\n奢\n賒\n蛇\n舌\n舍\n赦\n攝\n射\n懾\n涉\n社\n設\n砷\n申\n呻\n伸\n身\n深\n娠\n紳\n神\n沈\n審\n嬸\n甚\n腎\n慎\n滲\n聲\n生\n甥\n牲\n升\n繩\n省\n盛\n剩\n勝\n聖\n師\n失\n獅\n施\n溼\n詩\n屍\n蝨\n十\n石\n拾\n時\n什\n食\n蝕\n實\n識\n史\n矢\n使\n屎\n駛\n始\n式\n示\n士\n世\n柿\n事\n拭\n誓\n逝\n勢\n是\n嗜\n噬\n適\n仕\n侍\n釋\n飾\n氏\n市\n恃\n室\n視\n試\n收\n手\n首\n守\n壽\n授\n售\n受\n瘦\n獸\n蔬\n樞\n梳\n殊\n抒\n輸\n叔\n舒\n淑\n疏\n書\n贖\n孰\n熟\n薯\n暑\n曙\n署\n蜀\n黍\n鼠\n屬\n術\n述\n樹\n束\n戍\n豎\n墅\n庶\n數\n漱\n恕\n刷\n耍\n摔\n衰\n甩\n帥\n栓\n拴\n霜\n雙\n爽\n誰\n水\n睡\n稅\n吮\n瞬\n順\n舜\n說\n碩\n朔\n爍\n斯\n撕\n嘶\n思\n私\n司\n絲\n死\n肆\n寺\n嗣\n四\n伺\n似\n飼\n巳\n松\n聳\n慫\n頌\n送\n宋\n訟\n誦\n搜\n艘\n擻\n嗽\n蘇\n酥\n俗\n素\n速\n粟\n僳\n塑\n溯\n宿\n訴\n肅\n酸\n蒜\n算\n雖\n隋\n隨\n綏\n髓\n碎\n歲\n穗\n遂\n隧\n祟\n孫\n損\n筍\n蓑\n梭\n唆\n縮\n瑣\n索\n鎖\n所\n塌\n他\n它\n她\n塔\n獺\n撻\n蹋\n踏\n胎\n苔\n抬\n臺\n泰\n酞\n太\n態\n汰\n坍\n攤\n貪\n癱\n灘\n壇\n檀\n痰\n潭\n譚\n談\n坦\n毯\n袒\n碳\n探\n嘆\n炭\n湯\n塘\n搪\n堂\n棠\n膛\n唐\n糖\n倘\n躺\n淌\n趟\n燙\n掏\n濤\n滔\n絛\n萄\n桃\n逃\n淘\n陶\n討\n套\n特\n藤\n騰\n疼\n謄\n梯\n剔\n踢\n銻\n提\n題\n蹄\n啼\n體\n替\n嚏\n惕\n涕\n剃\n屜\n天\n添\n填\n田\n甜\n恬\n舔\n腆\n挑\n條\n迢\n眺\n跳\n貼\n鐵\n帖\n廳\n聽\n烴\n汀\n廷\n停\n亭\n庭\n挺\n艇\n通\n桐\n酮\n瞳\n同\n銅\n彤\n童\n桶\n捅\n筒\n統\n痛\n偷\n投\n頭\n透\n凸\n禿\n突\n圖\n徒\n途\n塗\n屠\n土\n吐\n兔\n湍\n團\n推\n頹\n腿\n蛻\n褪\n退\n吞\n屯\n臀\n拖\n託\n脫\n鴕\n陀\n馱\n駝\n橢\n妥\n拓\n唾\n挖\n哇\n蛙\n窪\n娃\n瓦\n襪\n歪\n外\n豌\n彎\n灣\n玩\n頑\n丸\n烷\n完\n碗\n挽\n晚\n皖\n惋\n宛\n婉\n萬\n腕\n汪\n王\n亡\n枉\n網\n往\n旺\n望\n忘\n妄\n威\n巍\n微\n危\n韋\n違\n桅\n圍\n唯\n惟\n爲\n濰\n維\n葦\n萎\n委\n偉\n僞\n尾\n緯\n未\n蔚\n味\n畏\n胃\n喂\n魏\n位\n渭\n謂\n尉\n慰\n衛\n瘟\n溫\n蚊\n文\n聞\n紋\n吻\n穩\n紊\n問\n嗡\n翁\n甕\n撾\n蝸\n渦\n窩\n我\n斡\n臥\n握\n沃\n巫\n嗚\n鎢\n烏\n污\n誣\n屋\n無\n蕪\n梧\n吾\n吳\n毋\n武\n五\n捂\n午\n舞\n伍\n侮\n塢\n戊\n霧\n晤\n物\n勿\n務\n悟\n誤\n昔\n熙\n析\n西\n硒\n矽\n晰\n嘻\n吸\n錫\n犧\n稀\n息\n希\n悉\n膝\n夕\n惜\n熄\n烯\n溪\n汐\n犀\n檄\n襲\n席\n習\n媳\n喜\n銑\n洗\n系\n隙\n戲\n細\n瞎\n蝦\n匣\n霞\n轄\n暇\n峽\n俠\n狹\n下\n廈\n夏\n嚇\n掀\n鍁\n先\n仙\n鮮\n纖\n鹹\n賢\n銜\n舷\n閒\n涎\n弦\n嫌\n顯\n險\n現\n獻\n縣\n腺\n餡\n羨\n憲\n陷\n限\n線\n相\n廂\n鑲\n香\n箱\n襄\n湘\n鄉\n翔\n祥\n詳\n想\n響\n享\n項\n巷\n橡\n像\n向\n象\n蕭\n硝\n霄\n削\n哮\n囂\n銷\n消\n宵\n淆\n曉\n小\n孝\n校\n肖\n嘯\n笑\n效\n楔\n些\n歇\n蠍\n鞋\n協\n挾\n攜\n邪\n斜\n脅\n諧\n寫\n械\n卸\n蟹\n懈\n泄\n瀉\n謝\n屑\n薪\n芯\n鋅\n欣\n辛\n新\n忻\n心\n信\n釁\n星\n腥\n猩\n惺\n興\n刑\n型\n形\n邢\n行\n醒\n幸\n杏\n性\n姓\n兄\n兇\n胸\n匈\n洶\n雄\n熊\n休\n修\n羞\n朽\n嗅\n鏽\n秀\n袖\n繡\n墟\n戌\n需\n虛\n噓\n須\n徐\n許\n蓄\n酗\n敘\n旭\n序\n畜\n恤\n絮\n婿\n緒\n續\n軒\n喧\n宣\n懸\n旋\n玄\n選\n癬\n眩\n絢\n靴\n薛\n學\n穴\n雪\n血\n勳\n燻\n循\n旬\n詢\n尋\n馴\n巡\n殉\n汛\n訓\n訊\n遜\n迅\n壓\n押\n鴉\n鴨\n呀\n丫\n芽\n牙\n蚜\n崖\n衙\n涯\n雅\n啞\n亞\n訝\n焉\n咽\n閹\n煙\n淹\n鹽\n嚴\n研\n蜒\n巖\n延\n言\n顏\n閻\n炎\n沿\n奄\n掩\n眼\n衍\n演\n豔\n堰\n燕\n厭\n硯\n雁\n唁\n彥\n焰\n宴\n諺\n驗\n殃\n央\n鴦\n秧\n楊\n揚\n佯\n瘍\n羊\n洋\n陽\n氧\n仰\n癢\n養\n樣\n漾\n邀\n腰\n妖\n瑤\n搖\n堯\n遙\n窯\n謠\n姚\n咬\n舀\n藥\n要\n耀\n椰\n噎\n耶\n爺\n野\n冶\n也\n頁\n掖\n業\n葉\n曳\n腋\n夜\n液\n一\n壹\n醫\n揖\n銥\n依\n伊\n衣\n頤\n夷\n遺\n移\n儀\n胰\n疑\n沂\n宜\n姨\n彝\n椅\n蟻\n倚\n已\n乙\n矣\n以\n藝\n抑\n易\n邑\n屹\n億\n役\n臆\n逸\n肄\n疫\n亦\n裔\n意\n毅\n憶\n義\n益\n溢\n詣\n議\n誼\n譯\n異\n翼\n翌\n繹\n茵\n蔭\n因\n殷\n音\n陰\n姻\n吟\n銀\n淫\n寅\n飲\n尹\n引\n隱\n印\n英\n櫻\n嬰\n鷹\n應\n纓\n瑩\n螢\n營\n熒\n蠅\n迎\n贏\n盈\n影\n穎\n硬\n映\n喲\n擁\n傭\n臃\n癰\n庸\n雍\n踊\n蛹\n詠\n泳\n湧\n永\n恿\n勇\n用\n幽\n優\n悠\n憂\n尤\n由\n郵\n鈾\n猶\n油\n遊\n酉\n有\n友\n右\n佑\n釉\n誘\n又\n幼\n迂\n淤\n於\n盂\n榆\n虞\n愚\n輿\n餘\n俞\n逾\n魚\n愉\n渝\n漁\n隅\n予\n娛\n雨\n與\n嶼\n禹\n宇\n語\n羽\n玉\n域\n芋\n鬱\n籲\n遇\n喻\n峪\n御\n愈\n欲\n獄\n育\n譽\n浴\n寓\n裕\n預\n豫\n馭\n鴛\n淵\n冤\n元\n垣\n袁\n原\n援\n轅\n園\n員\n圓\n猿\n源\n緣\n遠\n苑\n願\n怨\n院\n曰\n約\n越\n躍\n鑰\n嶽\n粵\n月\n悅\n閱\n耘\n雲\n鄖\n勻\n隕\n允\n運\n蘊\n醞\n暈\n韻\n孕\n匝\n砸\n雜\n栽\n哉\n災\n宰\n載\n再\n在\n咱\n攢\n暫\n贊\n贓\n髒\n葬\n遭\n糟\n鑿\n藻\n棗\n早\n澡\n蚤\n躁\n噪\n造\n皁\n竈\n燥\n責\n擇\n則\n澤\n賊\n怎\n增\n憎\n曾\n贈\n扎\n喳\n渣\n札\n軋\n鍘\n閘\n眨\n柵\n榨\n咋\n乍\n炸\n詐\n摘\n齋\n宅\n窄\n債\n寨\n瞻\n氈\n詹\n粘\n沾\n盞\n斬\n輾\n嶄\n展\n蘸\n棧\n佔\n戰\n站\n湛\n綻\n樟\n章\n彰\n漳\n張\n掌\n漲\n杖\n丈\n帳\n賬\n仗\n脹\n瘴\n障\n招\n昭\n找\n沼\n趙\n照\n罩\n兆\n肇\n召\n遮\n折\n哲\n蟄\n轍\n者\n鍺\n蔗\n這\n浙\n珍\n斟\n真\n甄\n砧\n臻\n貞\n針\n偵\n枕\n疹\n診\n震\n振\n鎮\n陣\n蒸\n掙\n睜\n徵\n猙\n爭\n怔\n整\n拯\n正\n政\n幀\n症\n鄭\n證\n芝\n枝\n支\n吱\n蜘\n知\n肢\n脂\n汁\n之\n織\n職\n直\n植\n殖\n執\n值\n侄\n址\n指\n止\n趾\n只\n旨\n紙\n志\n摯\n擲\n至\n致\n置\n幟\n峙\n制\n智\n秩\n稚\n質\n炙\n痔\n滯\n治\n窒\n中\n盅\n忠\n鍾\n衷\n終\n種\n腫\n重\n仲\n衆\n舟\n周\n州\n洲\n謅\n粥\n軸\n肘\n帚\n咒\n皺\n宙\n晝\n驟\n珠\n株\n蛛\n朱\n豬\n諸\n誅\n逐\n竹\n燭\n煮\n拄\n矚\n囑\n主\n著\n柱\n助\n蛀\n貯\n鑄\n築\n住\n注\n祝\n駐\n抓\n爪\n拽\n專\n磚\n轉\n撰\n賺\n篆\n樁\n莊\n裝\n妝\n撞\n壯\n狀\n椎\n錐\n追\n贅\n墜\n綴\n諄\n準\n捉\n拙\n卓\n桌\n琢\n茁\n酌\n啄\n着\n灼\n濁\n茲\n諮\n資\n姿\n滋\n淄\n孜\n紫\n仔\n籽\n滓\n子\n自\n漬\n字\n鬃\n棕\n蹤\n宗\n綜\n總\n縱\n鄒\n走\n奏\n揍\n租\n足\n卒\n族\n祖\n詛\n阻\n組\n鑽\n纂\n嘴\n醉\n最\n罪\n尊\n遵\n昨\n左\n佐\n柞\n做\n作\n坐\n座\n亍\n丌\n兀\n丐\n廿\n卅\n丕\n亙\n丞\n鬲\n孬\n噩\n丨\n禺\n丿\n匕\n乇\n夭\n爻\n卮\n氐\n囟\n胤\n馗\n毓\n睾\n鼗\n丶\n亟\n鼐\n乜\n乩\n亓\n羋\n孛\n嗇\n嘏\n仄\n厙\n厝\n厴\n厥\n廝\n靨\n贗\n匚\n叵\n匭\n匱\n匾\n賾\n卦\n卣\n刂\n刈\n刎\n剄\n刳\n劌\n剴\n剌\n剞\n剡\n剜\n蒯\n剽\n劂\n劁\n劐\n劓\n冂\n罔\n亻\n仃\n仉\n仂\n仨\n仡\n仫\n仞\n傴\n仳\n伢\n佤\n仵\n倀\n傖\n伉\n佇\n佞\n佧\n攸\n佚\n佝\n佟\n佗\n伲\n伽\n佶\n佴\n侑\n侉\n侃\n侏\n佾\n佻\n儕\n佼\n儂\n侔\n儔\n儼\n儷\n俅\n俚\n俁\n俜\n俑\n俟\n俸\n倩\n偌\n俳\n倬\n倏\n倮\n倭\n俾\n倜\n倌\n倥\n倨\n僨\n偃\n偕\n偈\n偎\n傯\n僂\n儻\n儐\n儺\n傺\n僖\n儆\n僭\n僬\n僦\n僮\n儇\n儋\n仝\n氽\n佘\n僉\n俎\n龠\n汆\n糴\n兮\n巽\n黌\n馘\n囅\n夔\n勹\n匍\n訇\n匐\n鳧\n夙\n兕\n亠\n兗\n亳\n袞\n袤\n褻\n臠\n裒\n稟\n嬴\n蠃\n羸\n冫\n冱\n冽\n冼\n凇\n冖\n冢\n冥\n訁\n訐\n訌\n訕\n謳\n詎\n訥\n詁\n訶\n詆\n詔\n詘\n詒\n誆\n誄\n詿\n詰\n詼\n詵\n詬\n詮\n諍\n諢\n詡\n誚\n誥\n誑\n誒\n諏\n諑\n諉\n諛\n諗\n諂\n誶\n諶\n諫\n謔\n謁\n諤\n諭\n諼\n諳\n諦\n諮\n諞\n謨\n讜\n謖\n諡\n謐\n謫\n譾\n譖\n譙\n譎\n讞\n譫\n讖\n卩\n巹\n阝\n阢\n阡\n阱\n阪\n阽\n阼\n陂\n陘\n陔\n陟\n隉\n陬\n陲\n陴\n隈\n隍\n隗\n隰\n邗\n邛\n鄺\n邙\n鄔\n邡\n邴\n邳\n邶\n鄴\n邸\n邰\n郟\n郅\n邾\n鄶\n郄\n郇\n鄆\n酈\n郢\n郜\n郗\n郛\n郫\n郯\n郾\n鄄\n鄢\n鄞\n鄣\n鄱\n鄯\n鄹\n酃\n酆\n芻\n奐\n勱\n劬\n劭\n劾\n哿\n勐\n勖\n勰\n叟\n燮\n矍\n廴\n凵\n凼\n鬯\n厶\n弁\n畚\n巰\n坌\n堊\n垡\n塾\n墼\n壅\n壑\n圩\n圬\n圪\n圳\n壙\n圮\n圯\n壢\n圻\n坂\n坩\n壠\n坫\n壚\n坼\n坻\n坨\n坭\n坶\n坳\n埡\n垤\n垌\n塏\n埏\n垧\n堖\n垓\n垠\n埕\n塒\n堝\n壎\n埒\n垸\n埴\n埯\n埸\n埤\n埝\n堋\n堍\n埽\n埭\n堀\n堞\n堙\n塄\n堠\n塥\n塬\n墁\n墉\n墚\n墀\n馨\n鼙\n懿\n艹\n艽\n艿\n芏\n芊\n芨\n芄\n芎\n芑\n薌\n芙\n芫\n芸\n芾\n芰\n藶\n苊\n苣\n芘\n芷\n芮\n莧\n萇\n蓯\n芩\n芴\n芡\n芪\n芟\n苄\n苧\n芤\n苡\n茉\n苷\n苤\n蘢\n茇\n苜\n苴\n苒\n苘\n茌\n苻\n苓\n蔦\n茚\n茆\n塋\n煢\n苠\n苕\n茜\n荑\n蕘\n蓽\n茈\n莒\n茼\n茴\n茱\n莛\n蕎\n茯\n荏\n荇\n荃\n薈\n荀\n茗\n薺\n茭\n茺\n茳\n犖\n滎\n蕁\n茛\n藎\n蕒\n蓀\n葒\n葤\n莰\n荸\n蒔\n萵\n莠\n莪\n莓\n莜\n蒞\n荼\n薟\n莩\n荽\n蕕\n荻\n莘\n莞\n莨\n鶯\n蓴\n菁\n萁\n菥\n菘\n堇\n萘\n萋\n菝\n菽\n菖\n萜\n萸\n萑\n萆\n菔\n菟\n萏\n萃\n菸\n菹\n菪\n菅\n菀\n縈\n菰\n菡\n葜\n葑\n葚\n葙\n葳\n蕆\n蒈\n葺\n蕢\n葸\n萼\n葆\n葩\n葶\n蔞\n蒎\n萱\n葭\n蓁\n蓍\n蓐\n驀\n蒽\n蓓\n蓊\n蒿\n蒺\n蘺\n蒡\n蒹\n蒴\n蒗\n鎣\n蕷\n蔌\n甍\n蔸\n蓰\n蘞\n蔟\n藺\n蕖\n蔻\n蓿\n蓼\n蕙\n蕈\n蕨\n蕤\n蕞\n蕺\n瞢\n蕃\n蘄\n蕻\n薤\n薨\n薇\n薏\n蕹\n藪\n薜\n薅\n薹\n薷\n薰\n蘚\n藁\n藜\n藿\n蘧\n蘅\n蘩\n櫱\n蘼\n廾\n弈\n夼\n奩\n耷\n奕\n奚\n奘\n匏\n尢\n尥\n尬\n尷\n扌\n捫\n摶\n抻\n拊\n拚\n拗\n拮\n撟\n拶\n挹\n捋\n捃\n掭\n揶\n捱\n捺\n掎\n摑\n捭\n掬\n掊\n捩\n掮\n摜\n揲\n揸\n揠\n撳\n揄\n揞\n揎\n摒\n揆\n掾\n攄\n摁\n搋\n搛\n搠\n搌\n搦\n搡\n摞\n攖\n摭\n撖\n摺\n擷\n擼\n撙\n攛\n擀\n擐\n擗\n擤\n擢\n攉\n攥\n攮\n弋\n忒\n甙\n弒\n卟\n叱\n嘰\n叩\n叨\n叻\n吒\n吖\n吆\n呋\n嘸\n囈\n呔\n嚦\n呃\n吡\n唄\n咼\n吣\n吲\n咂\n咔\n呷\n呱\n呤\n咚\n嚀\n咄\n呶\n呦\n噝\n哐\n咭\n哂\n咴\n噠\n咧\n咦\n嘵\n嗶\n呲\n咣\n噦\n咻\n咿\n哌\n噲\n哚\n嚌\n咩\n咪\n吒\n噥\n哏\n哞\n嘜\n哧\n嘮\n哽\n唔\n哳\n嗩\n唣\n唏\n唑\n唧\n唪\n嘖\n喏\n喵\n啉\n囀\n啁\n啕\n唿\n啐\n唼\n唷\n啖\n啵\n啶\n啷\n唳\n唰\n啜\n喋\n嗒\n喃\n喱\n喹\n喈\n喁\n喟\n啾\n嗖\n喑\n啻\n嗟\n嘍\n嚳\n喔\n喙\n嗪\n嗷\n嗉\n嘟\n嗑\n囁\n嗬\n嗔\n嗦\n嗝\n嗄\n嗯\n嗥\n嗲\n噯\n嗌\n嗍\n嗨\n嗵\n嗤\n轡\n嘞\n嘈\n嘌\n嘁\n嚶\n嘣\n嗾\n嘀\n嘧\n嘭\n噘\n嘹\n噗\n嘬\n噍\n噢\n噙\n嚕\n噌\n噔\n嚆\n噤\n噱\n噫\n噻\n噼\n嚅\n嚓\n嚯\n囔\n囗\n囝\n囡\n圇\n囫\n囹\n囿\n圄\n圊\n圉\n圜\n幃\n帙\n帔\n帑\n幬\n幘\n幗\n帷\n幄\n幔\n幛\n幞\n幡\n岌\n屺\n岍\n岐\n嶇\n岈\n峴\n岙\n岑\n嵐\n岜\n岵\n岢\n崬\n岬\n岫\n岱\n岣\n峁\n岷\n嶧\n峒\n嶠\n峋\n崢\n嶗\n崍\n崧\n崦\n崮\n崤\n崞\n崆\n崛\n嶸\n崾\n崴\n崽\n嵬\n嵛\n嵯\n嶁\n嵫\n嵋\n嵊\n嵩\n嵴\n嶂\n嶙\n嶝\n豳\n嶷\n巔\n彳\n彷\n徂\n徇\n徉\n後\n徠\n徙\n徜\n徨\n徭\n徵\n徼\n衢\n彡\n犭\n犰\n犴\n獷\n獁\n狃\n狁\n狎\n狍\n狒\n狨\n獪\n狩\n猻\n狴\n狷\n猁\n狳\n獫\n狺\n狻\n猗\n猓\n玀\n猊\n猞\n猝\n獼\n猢\n猹\n猥\n蝟\n猸\n猱\n獐\n獍\n獗\n獠\n獬\n獯\n獾\n舛\n夥\n飧\n夤\n夂\n飠\n餳\n飩\n餼\n飪\n飫\n飭\n飴\n餉\n餑\n餘\n餛\n餷\n餿\n饃\n饈\n饉\n饊\n饌\n饢\n庀\n廡\n庋\n庖\n庥\n庠\n庹\n庵\n庾\n庳\n賡\n廒\n廑\n廛\n廨\n廩\n膺\n忄\n忉\n忖\n懺\n憮\n忮\n慪\n忡\n忤\n愾\n悵\n愴\n忪\n忭\n忸\n怙\n怵\n怦\n怛\n怏\n怍\n怩\n怫\n怊\n懌\n怡\n慟\n懨\n惻\n愷\n恂\n恪\n惲\n悖\n悚\n慳\n悝\n悃\n悒\n悌\n悛\n愜\n悻\n悱\n惝\n惘\n惆\n惚\n悴\n慍\n憒\n愕\n愣\n惴\n愀\n愎\n愫\n慊\n慵\n憬\n憔\n憧\n憷\n懍\n懵\n忝\n隳\n閂\n閆\n闈\n閎\n閔\n閌\n闥\n閭\n閫\n鬮\n閬\n閾\n閶\n鬩\n閿\n閽\n閼\n闃\n闋\n闔\n闐\n闕\n闞\n丬\n爿\n戕\n氵\n汔\n汜\n汊\n灃\n沅\n沐\n沔\n沌\n汨\n汩\n汴\n汶\n沆\n潙\n泐\n泔\n沭\n瀧\n瀘\n泱\n泗\n沲\n泠\n泖\n濼\n泫\n泮\n沱\n泓\n泯\n涇\n洹\n洧\n洌\n浹\n湞\n洇\n洄\n洙\n洎\n洫\n澮\n洮\n洵\n洚\n瀏\n滸\n潯\n洳\n涑\n浯\n淶\n潿\n浞\n涓\n涔\n浜\n浠\n浼\n浣\n渚\n淇\n淅\n淞\n瀆\n涿\n淠\n澠\n淦\n淝\n淙\n瀋\n涫\n淥\n涮\n渫\n湮\n湎\n湫\n溲\n湟\n漵\n湓\n湔\n渲\n渥\n湄\n灩\n溱\n溘\n灄\n漭\n瀅\n溥\n溧\n溽\n溻\n溷\n潷\n溴\n滏\n溏\n滂\n溟\n潢\n瀠\n瀟\n漤\n漕\n滹\n漯\n漶\n瀲\n瀦\n漪\n漉\n漩\n澉\n澍\n澌\n潸\n潲\n潼\n潺\n瀨\n濉\n澧\n澹\n澶\n濂\n濡\n濮\n濞\n濠\n濯\n瀚\n瀣\n瀛\n瀹\n瀵\n灝\n灞\n宀\n宄\n宕\n宓\n宥\n宸\n甯\n騫\n搴\n寤\n寮\n褰\n寰\n蹇\n謇\n辶\n迓\n迕\n迥\n迮\n迤\n邇\n迦\n逕\n迨\n逅\n逄\n逋\n邐\n逑\n逍\n逖\n逡\n逵\n逶\n逭\n逯\n遄\n遑\n遒\n遐\n遨\n遘\n遢\n遛\n暹\n遴\n遽\n邂\n邈\n邃\n邋\n彐\n彗\n彖\n彘\n尻\n咫\n屐\n屙\n孱\n屣\n屨\n羼\n弳\n弩\n弭\n艴\n弼\n鬻\n屮\n妁\n妃\n妍\n嫵\n嫗\n妣\n妗\n姊\n嬀\n妞\n妤\n姒\n妲\n妯\n姍\n妾\n婭\n嬈\n姝\n孌\n姣\n姘\n奼\n娌\n娉\n媧\n嫺\n娑\n娣\n娓\n婀\n婧\n婊\n婕\n娼\n婢\n嬋\n胬\n媼\n媛\n婷\n婺\n媾\n嫫\n媲\n嬡\n嬪\n媸\n嫠\n嫣\n嬙\n嫖\n嫦\n嫘\n嫜\n嬉\n嬗\n嬖\n嬲\n嬤\n孀\n尕\n尜\n孚\n孥\n孳\n孑\n孓\n孢\n駔\n駟\n駙\n騶\n驛\n駑\n駘\n驍\n驊\n駢\n驪\n騏\n騍\n騅\n驂\n騭\n騖\n驁\n騮\n騸\n驃\n驄\n驏\n驥\n驤\n糹\n紆\n紂\n紇\n紈\n纊\n紜\n紕\n紓\n紺\n紲\n紱\n縐\n紼\n絀\n紿\n絝\n絎\n絳\n綆\n綃\n綈\n綾\n綺\n緋\n鞝\n緄\n綞\n綬\n綹\n綣\n綰\n緇\n緙\n緗\n緹\n緲\n繢\n緦\n緶\n緱\n縋\n緡\n縉\n縝\n縟\n縞\n縭\n縊\n縑\n繽\n縹\n縵\n縲\n繆\n繅\n纈\n繚\n繒\n繮\n繾\n繰\n繯\n纘\n幺\n畿\n巛\n甾\n邕\n玎\n璣\n瑋\n玢\n玟\n珏\n珂\n瓏\n玷\n玳\n珀\n珉\n珈\n珥\n珙\n頊\n琊\n珩\n珧\n珞\n璽\n琿\n璉\n琪\n瑛\n琦\n琥\n琨\n琰\n琮\n琬\n琛\n琚\n瑁\n瑜\n瑗\n瑕\n瑙\n璦\n瑭\n瑾\n璜\n瓔\n璀\n璁\n璇\n璋\n璞\n璨\n璩\n璐\n璧\n瓚\n璺\n韙\n韞\n韜\n杌\n杓\n杞\n杈\n榪\n櫪\n枇\n杪\n杳\n枘\n梘\n杵\n棖\n樅\n梟\n枋\n杷\n杼\n柰\n櫛\n柘\n櫳\n柩\n枰\n櫨\n柙\n枵\n柚\n枳\n柝\n梔\n柃\n枸\n柢\n櫟\n柁\n檉\n栲\n栳\n椏\n橈\n桎\n楨\n桄\n榿\n梃\n栝\n桕\n樺\n桁\n檜\n桀\n欒\n桊\n桉\n栩\n梵\n梏\n桴\n桷\n梓\n桫\n欞\n楮\n棼\n櫝\n槧\n棹\n欏\n棰\n椋\n槨\n楗\n棣\n椐\n楱\n椹\n楠\n楂\n楝\n欖\n楫\n榀\n榘\n楸\n椴\n槌\n櫬\n櫚\n槎\n櫸\n楦\n楣\n楹\n榛\n榧\n榻\n榫\n榭\n槔\n榱\n槁\n槊\n檳\n榕\n櫧\n榍\n槿\n檣\n槭\n樗\n樘\n櫫\n槲\n橄\n樾\n檠\n橐\n橛\n樵\n檎\n櫓\n樽\n樨\n橘\n櫞\n檑\n檐\n檁\n檗\n檫\n猷\n獒\n歿\n殂\n殤\n殄\n殞\n殮\n殍\n殫\n殛\n殯\n殪\n軔\n軛\n軲\n軻\n轤\n軹\n軼\n軫\n軤\n轢\n軺\n軾\n輊\n輇\n輅\n輒\n輦\n輞\n輟\n輜\n輳\n轆\n轔\n軎\n戔\n戧\n戛\n戟\n戢\n戡\n戥\n戤\n戩\n臧\n甌\n瓴\n瓿\n甏\n甑\n甓\n攴\n旮\n旯\n旰\n昊\n曇\n杲\n昃\n昕\n昀\n炅\n曷\n昝\n昴\n昱\n昶\n暱\n耆\n晟\n曄\n晁\n晏\n暉\n晡\n晗\n晷\n暄\n暌\n曖\n暝\n暾\n曛\n曜\n曦\n曩\n賁\n貰\n貺\n貽\n贄\n貲\n賅\n贐\n賑\n賚\n賕\n齎\n賧\n賻\n覘\n覬\n覡\n覿\n覦\n覯\n覲\n覷\n牮\n犟\n牝\n犛\n牯\n牾\n牿\n犄\n犋\n犍\n犏\n犒\n挈\n挲\n掰\n搿\n擘\n耄\n毪\n毳\n毽\n毿\n毹\n氅\n氌\n氆\n氍\n氕\n氘\n氙\n氚\n氡\n氬\n氤\n氪\n氳\n攵\n敕\n敫\n牘\n牒\n牖\n爰\n虢\n刖\n肟\n肜\n肓\n肼\n朊\n肽\n肱\n肫\n肭\n餚\n肷\n朧\n腖\n胩\n臚\n胛\n胂\n胄\n胙\n胍\n胗\n朐\n胝\n脛\n胱\n胴\n胭\n膾\n脎\n胲\n胼\n朕\n脒\n豚\n腡\n脞\n脬\n脘\n脲\n腈\n醃\n腓\n腴\n腙\n腚\n腱\n腠\n腩\n靦\n膃\n齶\n腧\n塍\n媵\n膈\n膂\n臏\n滕\n膣\n膪\n臌\n朦\n臊\n羶\n臁\n膦\n歟\n欷\n欹\n歃\n歆\n歙\n颮\n颯\n颶\n颼\n飆\n飈\n殳\n彀\n轂\n觳\n斐\n齏\n斕\n於\n旆\n旄\n旃\n旌\n旎\n旒\n旖\n煬\n煒\n燉\n熗\n炻\n烀\n炷\n炫\n炱\n燁\n烊\n焐\n焓\n燜\n焯\n焱\n煳\n煜\n煨\n煅\n煲\n煊\n煸\n煺\n熘\n熳\n熵\n熨\n熠\n燠\n燔\n燧\n燹\n爝\n爨\n灬\n燾\n煦\n熹\n戾\n戽\n扃\n扈\n扉\n礻\n祀\n祆\n祉\n祛\n祜\n祓\n祚\n禰\n祗\n祠\n禎\n祧\n祺\n禪\n禊\n禚\n禧\n禳\n忑\n忐\n懟\n恝\n恚\n恧\n恁\n恙\n恣\n愨\n愆\n愍\n慝\n憩\n憝\n懋\n懣\n戇\n肀\n聿\n沓\n澩\n淼\n磯\n矸\n碭\n砉\n硨\n砘\n砑\n斫\n砭\n碸\n砝\n砹\n礪\n礱\n砟\n砼\n砥\n砬\n砣\n砩\n硎\n硭\n硤\n磽\n砦\n硐\n硇\n硌\n硪\n磧\n碓\n碚\n碇\n磣\n碡\n碣\n碲\n碹\n碥\n磔\n磙\n磉\n磬\n磲\n礅\n磴\n礓\n礤\n礞\n礴\n龕\n黹\n黻\n黼\n盱\n眄\n瞘\n盹\n眇\n眈\n眚\n眢\n眙\n眭\n眥\n眵\n眸\n睞\n瞼\n睇\n睃\n睚\n睨\n睢\n睥\n睿\n瞍\n睽\n瞀\n瞌\n瞑\n瞟\n瞠\n瞰\n瞵\n瞽\n町\n畀\n畎\n畋\n畈\n畛\n畲\n畹\n疃\n罘\n罡\n罟\n詈\n罨\n羆\n罱\n罹\n羈\n罾\n盍\n盥\n蠲\n釒\n釓\n釔\n釙\n釗\n釕\n釷\n釧\n釤\n鍆\n釵\n釹\n鈈\n鈦\n鉅\n鈑\n鈐\n鈁\n鈧\n鈄\n鈥\n鈀\n鈺\n鉦\n鈷\n鈳\n鉕\n鈽\n鈸\n鉞\n鉬\n鉭\n鈿\n鑠\n鈰\n鉉\n鉈\n鉍\n鈮\n鈹\n鐸\n銬\n銠\n鉺\n銪\n鋮\n鋏\n鐃\n鋣\n鐺\n銱\n銦\n鎧\n銖\n鋌\n銩\n鏵\n銓\n鉿\n鎩\n銚\n錚\n銫\n銃\n鐋\n銨\n銣\n鐒\n錸\n鋱\n鏗\n鋥\n鋰\n鋯\n鋨\n銼\n鋝\n鋶\n鐦\n鐧\n鋃\n鋟\n鋦\n錒\n錆\n鍩\n錛\n鍀\n錁\n錕\n錮\n鍃\n錇\n錈\n錟\n錙\n鍥\n鍇\n鍶\n鍔\n鍤\n鎪\n鍰\n鎄\n鏤\n鏘\n鐨\n鎇\n鏌\n鎘\n鐫\n鎿\n鎦\n鎰\n鎵\n鑌\n鏢\n鏜\n鏝\n鏍\n鏞\n鏃\n鏇\n鏑\n鐔\n钁\n鏷\n鑥\n鐓\n鑭\n鐠\n鑹\n鏹\n鐙\n鑊\n鐲\n鐿\n鑔\n鑣\n鍾\n矧\n矬\n雉\n秕\n秭\n秣\n秫\n穭\n嵇\n稃\n稂\n稞\n稔\n稹\n稷\n穡\n黏\n馥\n穰\n皈\n皎\n皓\n皙\n皤\n瓞\n瓠\n甬\n鳩\n鳶\n鴇\n鴆\n鴣\n鶇\n鸕\n鴝\n鴟\n鷥\n鴯\n鷙\n鴰\n鵂\n鸞\n鵓\n鸝\n鵠\n鵒\n鷳\n鵜\n鵡\n鶓\n鵪\n鵯\n鶉\n鶘\n鶚\n鷀\n鶥\n鶩\n鷂\n鶼\n鸚\n鷓\n鷚\n鷯\n鷦\n鷲\n鷸\n鸌\n鷺\n鸛\n疒\n疔\n癤\n癘\n疝\n癧\n疣\n疳\n痾\n疸\n痄\n皰\n疰\n痃\n痂\n瘂\n痍\n痣\n癆\n痦\n痤\n癇\n痧\n瘃\n痱\n痼\n痿\n瘐\n瘀\n癉\n瘌\n瘞\n瘊\n瘥\n瘻\n瘕\n瘙\n瘛\n瘼\n瘢\n瘠\n癀\n瘭\n瘰\n癭\n瘵\n癃\n癮\n瘳\n癍\n癩\n癔\n癜\n癖\n癲\n癯\n翊\n竦\n穸\n穹\n窀\n窆\n窈\n窕\n竇\n窠\n窬\n窨\n窶\n窳\n衤\n衩\n衲\n衽\n衿\n袂\n袢\n襠\n袷\n袼\n裉\n褳\n裎\n襝\n襉\n裱\n褚\n裼\n裨\n裾\n裰\n褡\n褙\n褓\n褸\n褊\n襤\n褫\n褶\n襁\n襦\n襻\n疋\n胥\n皸\n皴\n矜\n耒\n耔\n耖\n耜\n耠\n耮\n耥\n耦\n耬\n耩\n耨\n耱\n耋\n耵\n聃\n聆\n聹\n聒\n聵\n聱\n覃\n頇\n頎\n頏\n頡\n頜\n潁\n頦\n頷\n顎\n顓\n顳\n顢\n顙\n顥\n顬\n顰\n虍\n虔\n虯\n蟣\n蠆\n虺\n虼\n虻\n蚨\n蚍\n蚋\n蜆\n蠔\n蚧\n蚣\n蚪\n蚓\n蚩\n蚶\n蛄\n蚵\n蠣\n蚰\n蚺\n蚱\n蚯\n蛉\n蟶\n蚴\n蛩\n蛺\n蟯\n蛭\n螄\n蛐\n蜓\n蛞\n蠐\n蛟\n蛘\n蛑\n蜃\n蜇\n蛸\n蜈\n蜊\n蜍\n蜉\n蜣\n蜻\n蜞\n蜥\n蜮\n蜚\n蜾\n蟈\n蜴\n蜱\n蜩\n蜷\n蜿\n螂\n蜢\n蝽\n蠑\n蝻\n蝠\n蝰\n蝌\n蝮\n螋\n蝓\n蝣\n螻\n蝤\n蝙\n蝥\n螓\n螯\n蟎\n蟒\n蟆\n螈\n螅\n螭\n螗\n螃\n螫\n蟥\n螬\n螵\n螳\n蟋\n蟓\n螽\n蟑\n蟀\n蟊\n蟛\n蟪\n蟠\n蟮\n蠖\n蠓\n蟾\n蠊\n蠛\n蠡\n蠹\n蠼\n缶\n罌\n罄\n罅\n舐\n竺\n竽\n笈\n篤\n笄\n筧\n笊\n笫\n笏\n筇\n笸\n笪\n笙\n笮\n笱\n笠\n笥\n笤\n笳\n籩\n笞\n筘\n篳\n筅\n筵\n筌\n箏\n筠\n筮\n筻\n筢\n筲\n筱\n箐\n簀\n篋\n箸\n箬\n箝\n籜\n箅\n簞\n箜\n箢\n簫\n箴\n簣\n篁\n篌\n篝\n篚\n篥\n篦\n篪\n簌\n篾\n篼\n簏\n籪\n簋\n簟\n簪\n簦\n簸\n籟\n籀\n臾\n舁\n舂\n舄\n臬\n衄\n舡\n舢\n艤\n舭\n舯\n舨\n舫\n舸\n艫\n舳\n舴\n舾\n艄\n艉\n艋\n艏\n艚\n艟\n艨\n衾\n嫋\n袈\n裘\n裟\n襞\n羝\n羥\n羧\n羯\n羰\n羲\n秈\n敉\n粑\n糲\n糶\n粞\n粢\n粲\n粼\n糉\n糝\n餱\n糌\n餈\n糈\n糅\n糗\n糨\n艮\n暨\n羿\n翎\n翕\n翥\n翡\n翦\n翩\n翮\n翳\n糸\n縶\n綦\n綮\n繇\n纛\n麩\n麴\n赳\n趄\n趔\n趑\n趲\n赧\n赭\n豇\n豉\n酊\n酐\n酎\n酏\n酤\n酢\n酡\n酰\n酩\n酯\n釅\n釃\n酲\n酴\n酹\n醌\n醅\n醐\n醍\n醑\n醢\n醣\n醪\n醭\n醮\n醯\n醵\n醴\n醺\n豕\n鹺\n躉\n跫\n踅\n蹙\n蹩\n趵\n趿\n趼\n趺\n蹌\n蹠\n跗\n跚\n躒\n跎\n跏\n跛\n跆\n跬\n蹺\n蹕\n跣\n躚\n躋\n跤\n踉\n跽\n踔\n踝\n踟\n躓\n踮\n踣\n躑\n踺\n蹀\n踹\n踵\n踽\n踱\n蹉\n蹁\n蹂\n躡\n蹣\n蹊\n躕\n蹶\n蹼\n蹯\n蹴\n躅\n躪\n躔\n躐\n躦\n躞\n豸\n貂\n貊\n貅\n貘\n貔\n斛\n觖\n觴\n觚\n觜\n觥\n觫\n觶\n訾\n謦\n靚\n雩\n靂\n雯\n霆\n霽\n霈\n霏\n霎\n霪\n靄\n霰\n霾\n齔\n齟\n齙\n齠\n齜\n齦\n齬\n齪\n齷\n黽\n黿\n鼉\n隹\n隼\n雋\n雎\n雒\n瞿\n讎\n銎\n鑾\n鋈\n鏨\n鍪\n鏊\n鎏\n鐾\n鑫\n魷\n魴\n鮁\n鮃\n鮎\n鱸\n穌\n鮒\n鱟\n鮐\n鮭\n鮚\n鮪\n鮞\n鱭\n鮫\n鯗\n鱘\n鯁\n鱺\n鰱\n鰹\n鰣\n鰷\n鯀\n鯊\n鯇\n鯽\n鯖\n鯪\n鯫\n鯡\n鯤\n鯧\n鯝\n鯢\n鯰\n鯛\n鯴\n鯔\n鱝\n鰈\n鱷\n鰍\n鰒\n鰉\n鯿\n鰠\n鰲\n鰭\n鰨\n鰥\n鰩\n鰳\n鰾\n鱈\n鰻\n鰵\n鱅\n鱖\n鱔\n鱒\n鱧\n靼\n鞅\n韃\n鞽\n鞔\n韉\n鞫\n鞣\n韝\n鞴\n骱\n骰\n骷\n鶻\n骶\n骺\n骼\n髁\n髀\n髏\n髂\n髖\n髕\n髑\n魅\n魃\n魘\n魎\n魈\n魍\n魑\n饗\n饜\n餮\n饕\n饔\n髟\n髡\n髦\n髯\n髫\n髻\n髭\n髹\n鬈\n鬏\n鬢\n鬟\n鬣\n麼\n麾\n縻\n麂\n麇\n麈\n麋\n麒\n鏖\n麝\n麟\n黛\n黜\n黝\n黠\n黟\n黢\n黷\n黧\n黥\n黲\n黯\n鼢\n鼬\n鼯\n鼴\n鼷\n鼽\n鼾\n齄\n"
  },
  {
    "path": "uv-k5font/uv-k5font_full/main.cpp",
    "content": "\n#include<iostream>\n#include<fstream>\n#include<string>\n#include <vector>\n#include <array>\n#include <map>\n#include \"font.h\"\n#include \"bits/stdc++.h\"\nusing namespace std;\n#define IS_BIT_SET(byte, bit) ((byte>>bit) & (1))\n\nifstream file(\"../ALL_IN.txt\"); // ?I??????????????\n//ifstream file(\"../CHINESE7000_OUT.txt\"); // ?I??????????????\nofstream outFile(\"../name_tmp.txt\");\n//ofstream out_chinese_array(\"../chinese_array.txt\");\nofstream out_chinese_array(\"../chinese_array.txt\", std::ios::binary);\nofstream output_file(\"../chinses_map.txt\"); // ??????????????????????\nstring names[10000];\nunsigned char chinese[10000][2];\nunsigned char english[1000];\nbool en_flag[256] = {false};\n#define CAL\nint init_file() {\n    int lines = 0;\n    if (file.is_open()) {\n        string line;\n        while (getline(file, line)) {\n            // ??????????????????????????????\n            names[lines] = line;\n            lines++;\n\n        }\n\n        file.close();\n    } else {\n        cout << \"????????\" << endl;\n    }\n    return lines;\n\n}\n\nbool sortByValue(const pair<array<unsigned char, 2>, int> &a, const pair<array<unsigned char, 2>, int> &b) {\n    return a.second < b.second;\n}\n\nmap<array<unsigned char, 2>, unsigned int> map_str;\nmap<array<unsigned char, 2>, unsigned int> all_code;\n\nbool isGBKChineseCharacter(const string &str, size_t index) {\n    // ???GBK????????????????\n    if (index < str.size() - 1) {\n        unsigned char firstByte = static_cast<unsigned char>(str[index]);\n        unsigned char secondByte = static_cast<unsigned char>(str[index + 1]);\n        if (firstByte >= 0x81 && firstByte <= 0xFE &&\n            ((secondByte >= 0x40 && secondByte <= 0x7E) || (secondByte >= 0x80 && secondByte <= 0xFE))) {\n            return true;\n        }\n    }\n    return false;\n}\n\nvoid removeNullStrings(const std::string &inputFile, const std::string &outputFile) {\n    std::ifstream input(inputFile, std::ios::binary);\n    std::ofstream output(outputFile, std::ios::binary);\n\n    if (!input.is_open()) {\n        std::cerr << \"Unable to open input file\" << std::endl;\n        return;\n    }\n\n    if (!output.is_open()) {\n        std::cerr << \"Unable to open output file\" << std::endl;\n        return;\n    }\n\n    std::string buffer;\n    while (getline(input, buffer)) {\n        size_t found = buffer.find(\"\\\\x00\");\n        while (found != std::string::npos) {\n            buffer.erase(found, 4); // Erase 4 characters starting from found position\n            found = buffer.find(\"\\\\x00\", found);\n        }\n        output << buffer << std::endl;\n    }\n\n    input.close();\n    output.close();\n}\n\n\nvoid set_bit(uint8_t *value, uint8_t bit_position, uint8_t bit_value) {\n    if (bit_value == 0) {\n        *value = *value & ~(1 << bit_position); // ?????????? 0\n    } else {\n        *value = *value | (1 << bit_position);  // ?????????? 1\n    }\n}\n\n#define IS_BIT_SET(byte, bit) ((byte>>bit) & (1))\n\nvoid show_font(unsigned char show_font[22]) {\n    unsigned char bitmap[CHN_FONT_HIGH][CHN_FONT_WIDTH] = {0};\n    for (int i = 0; i < CHN_FONT_WIDTH * 2; i++) {\n        if (i < CHN_FONT_WIDTH) {\n            for (int j = 0; j < 8; j++) {\n                if (IS_BIT_SET(show_font[i], j))\n                    bitmap[j][i] = 1;\n            }\n        } else {\n            for (int j = 0; j < CHN_FONT_HIGH - 8; ++j) {\n                bitmap[j + 8][i - CHN_FONT_WIDTH] = IS_BIT_SET(show_font[i], j);\n            }\n        }\n\n    }\n    for (int i = 0; i < CHN_FONT_HIGH; ++i) {\n        for (int j = 0; j < CHN_FONT_WIDTH; ++j) {\n            if (bitmap[i][j])\n                printf(\"1\");\n            else\n                printf(\"0\");\n        }\n        printf(\"\\n\");\n\n    }\n}\nbool check_font(unsigned char *font1,unsigned char *font2)\n{\n    return (memcmp(font1,font2,CHN_FONT_WIDTH*2)==0);\n}\nvoid back_font(int num_show, unsigned char *font) { //??????????\n    unsigned int local = CHN_FONT_HIGH * CHN_FONT_WIDTH * num_show / 8;\n    unsigned int local_bit = (CHN_FONT_HIGH * CHN_FONT_WIDTH * num_show) % 8;\n    unsigned char now_font[CHN_FONT_WIDTH * 2] = {0};\n    for (int i = 0; i < CHN_FONT_WIDTH*2; ++i) {\n        unsigned char j_end=8;\n        if(i>=CHN_FONT_WIDTH)\n            j_end=CHN_FONT_HIGH-8 ;\n\n        for (int j = 0; j < j_end; ++j) {\n\n            if (IS_BIT_SET(font[local], local_bit))\n                set_bit(&now_font[i], j, 1);\n            local_bit++;\n            if (local_bit == 8) {\n                local_bit = 0;\n                local++;\n            }\n        }\n\n    }\n    if(!check_font(now_font,new_font[num_show]))\n    {\n        printf(\"SB\\n\");\n    }\n}\nint main() {\n    int num_names = init_file();\n    // cout << num_names << endl;\n\n    int num_chinese = 0;\n    int num_english = 0;\n    if (!outFile.is_open()) {\n        return -5;\n    }\n    // ??????????\n\n\n//        // ????????\n//    outFile << \"Hello, this is some text.\\n\";\n//    outFile << \"This is a new line.\";\n\n    for (int i = 0; i < num_names; i++) {\n\n\n        for (size_t j = 0; j < names[i].size(); ++j) {\n            if (isGBKChineseCharacter(names[i], j)) {\n\n                array<unsigned char, 2> tmp = {0};\n                tmp[0] = names[i][j];\n                tmp[1] = names[i][j + 1];\n\n                if (map_str.find(tmp) != map_str.end()) {\n                } else {\n                    // ???????????????????????????????1\n                    map_str[tmp] = num_chinese;\n                    //   cout<<num_chinese<<\":\"<<tmp[0]<< tmp[1]<<endl;\n\n                    chinese[num_chinese][0] = tmp[0];\n                    chinese[num_chinese][0] = tmp[1];\n                    //   outFile <<\"\\\\x\"<< hex << setw(2) << setfill('0') << uppercase <<  num_chinese << endl;\n\n                    num_chinese++;\n                }\n                j++; // ????????????????????????????\n\n            } else {\n\n                if (en_flag[names[i][j]]) {\n\n                } else {\n                    //         ???????????????????????????????1\n                    en_flag[names[i][j]] = true;\n                    english[num_english] = names[i][j];\n                    num_english++;\n                }\n            }\n        }\n    }\n\n\n\n\n    // outFile <<\"\\\\x\"<< hex << setw(2) << setfill('0') << uppercase <<   map_str[tmp] << endl;\n\n\n\n    vector<pair<array<unsigned char, 2>, int>> vec(map_str.begin(), map_str.end());\n\n    // ?????????????????????\n    sort(vec.begin(), vec.end(), sortByValue);\n    en_flag['\\n'] = true;\n    en_flag[' '] = true;\n\n    for (int i = '!'; i <= '~'; i++) {\n        en_flag[i] = true;\n    }\n    // ?????????????\n    int now_code = 0x8000;\n    for (const auto &pair: vec) {\n        // cout << \"{\" << static_cast<int>(pair.first[0]) << \", \" << static_cast<int>(pair.first[1]) << \"} : \" << pair.second << endl;\n        array<unsigned char, 2> tmp = {0};\n        tmp[0] = pair.first[0];\n        tmp[1] = pair.first[1];\n        if(now_code%256==0)\n            now_code+=1;\n        map_str[tmp] = now_code;\n\n        array<unsigned char, 2> tmp1;\n        tmp1[0] = tmp[0];\n        tmp1[1] = tmp[1];\n        all_code[tmp1] = map_str[tmp];\n\n        now_code++;\n//        cout << tmp[0] << tmp[1] << \":\" <<hex <<(int) map_str[tmp] << endl;\n        output_file << tmp[0] << tmp[1] << \":\" << std::hex << (int)map_str[tmp] << std::endl;\n\n    }\n\n\n    for (int i = 0; i < num_names; i++) {\n        for (size_t j = 0; j < names[i].size(); ++j) {\n            if (isGBKChineseCharacter(names[i], j)) {\n\n                array<unsigned char, 2> tmp = {0};\n                tmp[0] = names[i][j];\n                tmp[1] = names[i][j + 1];\n                unsigned int value = all_code[tmp];\n                unsigned char byte1 = (value >> 8) & 0xFF;\n                unsigned char byte2 = value & 0xFF;\n\n                outFile << \"\\\\x\" << std::hex << std::setw(2) << std::setfill('0') << std::uppercase << (int) byte1;\n                outFile.flush(); // ???????????????????\n\n// Outputting byte2 as a character other than '\\x00'\n                if (byte2 == 0x00) {\n                    outFile << \"\\\\x\\\\x\" << \"0000\";\n                } else {\n                    outFile << \"\\\\x\" << std::hex << std::setw(2) << std::setfill('0') << std::uppercase << (int) byte2;\n                }\n\n                j++;\n            } else {\n                array<unsigned char, 2> tmp = {0};\n                tmp[0] = 5;\n                tmp[1] = names[i][j];\n                outFile << \"\\\\x\" << hex << setw(2) << setfill('0') << uppercase << (int) tmp[1];\n                //  outFile << \"\\\\x\" << hex << setw(2) << setfill('0') << uppercase << static_cast<unsigned int>(all_code[tmp]);\n            }\n        }\n        outFile << endl;\n    }\n\n    outFile.close();\n\n    std::string inputFile = \"../name_tmp.txt\"; // Replace with your input file name\n    std::string outputFile = \"../name_out.txt\"; // Replace with your output file name\n    removeNullStrings(inputFile, outputFile);\n\n\n    cout << \"chinese num:\" << num_chinese << endl;\n    cout << \"english num\" << num_english << endl;\n    unsigned int NEW_FONT_BYTE = ceil((float) (CHN_FONT_NUM) * (float) (CHN_FONT_HIGH) * (float) (CHN_FONT_WIDTH) / 8);\n    cout << NEW_FONT_BYTE << endl;\n    unsigned char gFontChinese_out[NEW_FONT_BYTE] = {0};\n//    return 0;\n\n    int now_byte_index = 0;\n    int now_bit_index = 0;\n    for (int k = 0; k < CHN_FONT_NUM; k++) {//???\n        unsigned char bitmap[CHN_FONT_HIGH][CHN_FONT_WIDTH] = {0};\n        for (int i = 0; i < CHN_FONT_WIDTH * 2; i++) {\n            if (i < CHN_FONT_WIDTH) {\n                for (int j = 0; j < 8; j++) {\n                    if (IS_BIT_SET(new_font[k][i], j))\n                        bitmap[j][i] = 1;\n                }\n            } else {\n                for (int j = 0; j < CHN_FONT_HIGH - 8; ++j) {\n                    bitmap[j + 8][i - CHN_FONT_WIDTH] = IS_BIT_SET(new_font[k][i], j);\n                }\n            }\n        }\n\n\n#ifdef CAL\n        for (int i = 0; i < CHN_FONT_HIGH; ++i) {\n            for (int j = 0; j < CHN_FONT_WIDTH; ++j) {\n                if(bitmap[i][j])\n                    set_bit(&gFontChinese_out[now_byte_index], now_bit_index, 1);\n                now_bit_index++;\n                if (now_bit_index == 8) {\n                    now_bit_index = 0;\n                    now_byte_index++;\n                }\n            }\n        }\n#else\n        for (int i = 0; i < CHN_FONT_WIDTH; ++i) {\n            for (int j = 0; j < 8; ++j) {\n                if (bitmap[j][i])\n                    set_bit(&gFontChinese_out[now_byte_index], now_bit_index, 1);\n\n                now_bit_index++;\n                if (now_bit_index == 8) {\n                    now_bit_index = 0;\n                    now_byte_index++;\n                }\n\n            }\n        }\n\n        for (int i = 0; i < CHN_FONT_WIDTH; ++i) {\n            for (int j = 8; j < CHN_FONT_HIGH; ++j) {\n                if (bitmap[j][i])\n                    set_bit(&gFontChinese_out[now_byte_index], now_bit_index, 1);\n                now_bit_index++;\n                if (now_bit_index == 8) {\n                    now_bit_index = 0;\n                    now_byte_index++;\n                }\n\n            }\n        }\n\n        back_font(k, gFontChinese_out);\n#endif\n    }\n\n#ifndef CAL\n\n\n    out_chinese_array<<\"const uint8_t gFontChinese_out1[\"<<111590<<\"]={\"<<endl;\n    for (int i = 0; i < 111590; i++) {\n        out_chinese_array << \"0X\" << hex << setw(2) << setfill('0') << uppercase << (int) gFontChinese_out[i]<<\",\";\n        if(i%20==0&&i!=0)out_chinese_array<<endl;\n    }\n    out_chinese_array<<\"};\"<<endl;\n#else\n    cout<<now_byte_index<<endl;\n    out_chinese_array.write(reinterpret_cast<const char*>(gFontChinese_out), sizeof(gFontChinese_out));\n#endif\n    out_chinese_array.close();\n\ncout<<\"\"<<endl;\n}\n\n\n\n"
  },
  {
    "path": "uv-k5font/uv-k5font_full/name.txt",
    "content": "Ƶ\n\nģ\n\nģ\nƵ\nƵƵ\n\næ\nѹ\nŵ\nɾŵ\nŵ\nŵɨб\nɨб1\nɨб2\nָģʽ\nͳʱ\nʡģʽ\n˷\nŵʾģʽ\nԶ\n\nβ\nMDC ID\nβ\nмβ\n\nDTMF ID\nDTMF\nDTMF\nDTMF\nDTMF\nDTMFӦ\nDTMFλ\nDTMFԤز\nDTMFϵ\nDTMFʾ\nAMԶ\nշģʽ\nȼ\nƵν\n200M\n350M\n500M\n350M\nصѹ\nشС\nλ\n=\n=+ƫ\n=-ƫ\nر\n\n1 \n2 \n3 \n4 \n30 \n1 \n2 \n3 \n4 \n5 \n6 \n7 \n8 \n9 \n15 \nŵշ\n˫ŵ\nŵ丱ŵ\nŵ˫ŵ\nź5\nźֹͣ\nźźֹͣ\nƵ\nŵ\n\n+Ƶ\nӦ\n\nظӦ\nظӦ\n\n\n\n+\nQuindar\nر\nROGERβ\nMDCβ\nMDC\nMDCβ\nMDCROGER\nŵ\nȫ\nȫ\nȫ\n5 \n10 \n20 \nʱ\nʱ\n/ʱ\nȫ\nɨ\n͵ѹ\n # \næ\nֹ\nͳʱ\nߵѹ\n EXIT \nȫ\n\n?\n:\nɨ\nɾ?"
  },
  {
    "path": "uv-k5font/uv-k5font_full/name_out.txt",
    "content": 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  },
  {
    "path": "version.c",
    "content": "#include \"font.h\"\r\nconst char Version[]      = PACKED_FILE_SUFFIX;\r\n\r\n"
  },
  {
    "path": "version.h",
    "content": "/* Copyright 2023 Dual Tachyon\r\n * https://github.com/DualTachyon\r\n *\r\n * Licensed under the Apache License, Version 2.0 (the \"License\");\r\n * you may not use this file except in compliance with the License.\r\n * You may obtain a copy of the License at\r\n *\r\n *     http://www.apache.org/licenses/LICENSE-2.0\r\n *\r\n *     Unless required by applicable law or agreed to in writing, software\r\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\r\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n *     See the License for the specific language governing permissions and\r\n *     limitations under the License.\r\n */\r\n\r\n#ifndef VERSION_H\r\n#define VERSION_H\r\n\r\nextern const char Version[];\r\n\r\n#endif\r\n\r\n"
  },
  {
    "path": "win_make.bat",
    "content": "\r\n@echo off\r\n\r\n\r\n\r\n\r\n:: Compile directly in windows without the need of a linux virtual machine:\r\n:: \r\n:: 1. Download and install \"gcc-arm-none-eabi-10.3-2021.10-win32.exe\" from https://developer.arm.com/downloads/-/gnu-rm\r\n:: 2. Download and install \"gnu_make-3.81.exe\" from https://gnuwin32.sourceforge.net/packages/make.htm\r\n::\r\n:: 3. You may (or may not) need to manualy add a path to you OS environment PATH, ie ..\r\n::    C:\\Program Files (x86)\\GNU Arm Embedded Toolchain\\10 2021.10\\bin\r\n::\r\n:: 4. You may (or may not) need to reboot windows after installing the above\r\n:: \r\n:: You can then run this bat from the directory you saved the firmware source code too.\r\n\r\n\r\n\r\n:: You may need to edit/change these three paths to suit your setup\r\n::\r\n:: Temporarily add the compiler and make program directories to the system PATH ..\r\n::\r\n@set PATH=\"C:\\Program Files (x86)\\GNU Arm Embedded Toolchain\\10 2021.10\\bin\";%PATH%\r\n@set PATH=\"C:\\Program Files (x86)\\GNU Arm Embedded Toolchain\\10 2021.10\\arm-none-eabi\\bin\";%PATH%\r\n@set PATH=\"C:\\Program Files (x86)\\GnuWin32\\bin\\\";%PATH%\r\n\r\n:: Do the compile\r\n::\r\nmake clean\r\nmake full\r\n\r\n:: pyinstaller --onefile ./MDC_WRITE/main.py\r\n:: If you have python installed, you can create a 'packed' .bin from the compiled firmware.bin file.\r\n:: The Quansheng windows upload-to-radio program requires a 'packed' .bin file.\r\n::\r\n:: if you don't have python installed, then you can still upload the standard unpacked firmware.bin\r\n:: file another way ...\r\n::\r\n:: I wrote a GUI version of k5prog to do this easily in windows ..\r\n::    https://github.com/OneOfEleven/k5prog-win\r\n\r\n\r\n\r\n:: One of these two lines simply install the required python module if you want to create the packed\r\n:: firmware bin file, either only needs running once, ever.\r\n::\r\n::python  -m pip install --upgrade pip crcmod\r\n::python3 -m pip install --upgrade pip crcmod\r\n\r\n\r\n\r\n:: show the compiled .bin file size\r\n::\r\n::arm-none-eabi-size firmware\r\n\r\n\r\n\r\n\r\npause\r\n@echo on\r\n"
  },
  {
    "path": "写频脚本/picture.py",
    "content": "import serial\nfrom PyQt5.QtWidgets import QButtonGroup\n\nfrom PyQt5.QtCore import QTimer\nfrom PyQt5.QtWidgets import QMainWindow, QPushButton, QFileDialog, QLabel, QRadioButton, QMessageBox, QComboBox, \\\n    QProgressBar\nfrom PyQt5.QtWidgets import QApplication\nimport sys\nfrom PyQt5.QtGui import QImage, QPixmap, QColor, qGray, qRgb\nimport struct\nresized_image=None\ncal_bin=1\ncom_open=\"\"\nturn_color=0\nVERSION=0\ncompress_pixels = [0] * 1024\nCrc16Tab = [0, 4129, 8258, 12387, 16516, 20645, 24774, 28903, 33032, 37161, 41290, 45419, 49548, 53677, 57806, 61935, 4657, 528, 12915, 8786, 21173, 17044, 29431, 25302,\n            37689, 33560, 45947, 41818, 54205, 50076, 62463, 58334, 9314, 13379, 1056, 5121, 25830, 29895, 17572, 21637, 42346, 46411, 34088, 38153, 58862, 62927, 50604, 54669, 13907,\n            9842, 5649, 1584, 30423, 26358, 22165, 18100, 46939, 42874, 38681, 34616, 63455, 59390, 55197, 51132, 18628, 22757, 26758, 30887, 2112, 6241, 10242, 14371, 51660, 55789,\n            59790, 63919, 35144, 39273, 43274, 47403, 23285, 19156, 31415, 27286, 6769, 2640,14899, 10770, 56317, 52188, 64447, 60318, 39801, 35672, 47931, 43802, 27814, 31879,\n            19684, 23749, 11298, 15363, 3168, 7233, 60846, 64911, 52716, 56781, 44330, 48395,36200, 40265, 32407, 28342, 24277, 20212, 15891, 11826, 7761, 3696, 65439, 61374,\n            57309, 53244, 48923, 44858, 40793, 36728, 37256, 33193, 45514, 41451, 53516, 49453, 61774, 57711, 4224, 161, 12482, 8419, 20484, 16421, 28742, 24679, 33721, 37784, 41979,\n            46042, 49981, 54044, 58239, 62302, 689, 4752, 8947, 13010, 16949, 21012, 25207, 29270, 46570, 42443, 38312, 34185, 62830, 58703, 54572, 50445, 13538, 9411, 5280, 1153, 29798,\n            25671, 21540, 17413, 42971, 47098, 34713, 38840, 59231, 63358, 50973, 55100, 9939, 14066, 1681, 5808, 26199, 30326, 17941, 22068, 55628, 51565, 63758, 59695, 39368,\n            35305, 47498, 43435, 22596, 18533, 30726, 26663, 6336, 2273, 14466, 10403, 52093, 56156, 60223, 64286, 35833, 39896, 43963, 48026, 19061, 23124, 27191, 31254, 2801,\n            6864, 10931, 14994, 64814, 60687, 56684, 52557, 48554, 44427, 40424, 36297, 31782, 27655, 23652, 19525, 15522, 11395, 7392, 3265, 61215, 65342, 53085, 57212, 44955,\n            49082, 36825, 40952, 28183, 32310, 20053, 24180, 11923, 16050, 3793, 7920]\n\nclass MainWindow(QMainWindow):\n    def __init__(self):\n        super().__init__()\n\n        self.initUI()\n\n    def initUI(self):\n        global cal_bin\n        global turn_color\n\n        self.setWindowTitle(\"K5/K6开机图片V0.4\")\n        self.setGeometry(100, 100, 50+20+256, 250)\n\n        self.open_button = QPushButton(\"打开图片\", self)\n        self.open_button.setGeometry(10, 50, 100, 30)\n        self.open_button.clicked.connect(self.open_image)\n\n        self.process_button = QPushButton(\"写入图片\", self)\n        self.process_button.setGeometry(130, 50, 100, 30)\n        self.process_button.clicked.connect(self.process_image)\n        self.process_button.setEnabled(False)\n\n        self.label = QLabel(self)\n        self.label.setGeometry(35, 100, 256, 128)\n        self.button_group = QButtonGroup(self)\n        self.radioButton1 = QRadioButton(\"效果1\", self)\n        self.radioButton2 = QRadioButton(\"效果2\", self)\n        self.radioButton3 = QRadioButton(\"反色\", self)\n        cal_bin = 1\n        self.button_group.addButton(self.radioButton1)\n        self.button_group.addButton(self.radioButton2)\n        self.radioButton1.setGeometry(250, 40, 120, 20)\n        self.radioButton2.setGeometry(250, 55, 120, 30)\n        self.radioButton3.setGeometry(250, 75, 120, 30)\n\n        self.radioButton1.setChecked(True)  # 默认选中第一个单选按钮\n\n        self.radioButton1.toggled.connect(self.on_radio_button_toggled)\n        self.radioButton2.toggled.connect(self.on_radio_button_toggled)\n        self.radioButton3.toggled.connect(self.on_radio_button3_toggled)\n\n\n        turn_color = 0\n\n        self.combo_box = QComboBox(self)\n        self.combo_box.setGeometry(10, 10, 100, 20)\n        self.populate_serial_ports()  # Populate available serial ports\n        self.combo_box.currentIndexChanged.connect(self.on_combo_box_changed)\n\n        self.timer = QTimer()\n        self.timer.timeout.connect(self.populate_serial_ports)\n        self.timer.start(500)  # Refresh every 5 seconds (1000 milliseconds)\n\n        self.progress_bar = QProgressBar(self)\n        self.progress_bar.setGeometry(130, 10, 200, 20)\n        self.progress_bar.setValue(0)\n    # ... (previous code remains the same)\n\n    from PyQt5.QtWidgets import QComboBox\n\n    class MainWindow(QMainWindow):\n        def __init__(self):\n            super().__init__()\n\n            self.initUI()\n\n        def initUI(self):\n            # ... (existing code)\n\n            self.combo_box = QComboBox(self)\n            self.combo_box.setGeometry(20, 120, 200, 30)\n            self.populate_serial_ports()  # Populate available serial ports\n            self.combo_box.currentIndexChanged.connect(self.on_combo_box_changed)\n\n    def populate_serial_ports(self):\n        com_open = self.combo_box.currentText()\n        import serial.tools.list_ports\n        self.combo_box.clear()\n        ports = serial.tools.list_ports.comports()\n        for port in ports:\n            self.combo_box.addItem(port.device)\n        if com_open!=\"\":\n            index = self.combo_box.findText(com_open)\n            if index >= 0:\n                self.combo_box.setCurrentIndex(index)\n            else:\n                com_open = \"\"\n\n    def qimage_to_gray_list(self,img):\n        if img.isNull():\n            return None\n        global compress_pixels\n        width = img.width()\n        height = img.height()\n        compress_pixels = [0 for _ in range(len(compress_pixels))]\n        for y in range(height):\n            for x in range(width):\n                gray_value = QColor(img.pixelColor(x, y)).lightness()\n                if gray_value!=255 :\n                    compress_pixels[y // 8 * 128 + x]=compress_pixels[y//8*128+x]|(1<<(y%8))\n\n    def on_combo_box_changed(self, index):\n        global com_open\n        com_open = self.combo_box.currentText()\n\n    def on_radio_button_toggled(self):\n        global cal_bin\n        global resized_image\n        global turn_color\n\n        sender = self.sender()\n\n        if sender.isChecked():\n            if sender == self.radioButton1:\n                self.radioButton2.setChecked(False)\n                if self.process_button.isEnabled() and cal_bin == 2:\n                    binarized_image = self.binarize_image1(resized_image)\n                    compress_pixels=self.qimage_to_gray_list(binarized_image)\n                    self.show_img(binarized_image)\n                cal_bin=1\n            elif sender == self.radioButton2:\n                self.radioButton1.setChecked(False)\n                if self.process_button.isEnabled() and cal_bin == 1:\n                    binarized_image = self.binarize_image2(resized_image)\n                    compress_pixels=self.qimage_to_gray_list(binarized_image)\n                    self.show_img(binarized_image)\n                cal_bin=2\n\n    def on_radio_button3_toggled(self):\n        global turn_color\n        turn_color = 1 - turn_color\n        if self.process_button.isEnabled():\n            if self.radioButton1.isChecked():\n                binarized_image = self.binarize_image1(resized_image)\n            else:\n                binarized_image = self.binarize_image2(resized_image)\n            compress_pixels = self.qimage_to_gray_list(binarized_image)\n            self.show_img(binarized_image)\n\n    def open_image(self):\n        global resized_image\n        global cal_bin\n        options = QFileDialog.Options()\n        file_path, _ = QFileDialog.getOpenFileName(self, \"Open Image File\", \"\", \"Image Files (*.jpg *.png *.bmp *.jpeg)\",\n                                                   options=options)\n        if file_path:\n            self.image_path = file_path\n            self.process_button.setEnabled(True)\n            try:\n                original_image = QImage(self.image_path)\n                resized_image = self.resize_image_qimage(original_image, 128, 64)\n                if cal_bin==1:\n                    binarized_image = self.binarize_image1(resized_image)\n                else:\n                    binarized_image = self.binarize_image2(resized_image)\n\n                #binarized_image.save(\"C:/Users/RUPC/Desktop/3.jpg\")\n                compress_pixels=self.qimage_to_gray_list(binarized_image)\n                self.show_img(binarized_image)\n\n\n                # 设置 label 为主窗口的中央部件\n                # self.setCentralWidget(label)\n            except Exception as e:\n                print(\"Exception occurred:\", str(e))\n\n    def process_image(self):\n        global com_open\n        global compress_pixels\n        self.disable_all_widgets()\n        if self.time_set()==False:\n            self.enable_all_widgets()\n            self.progress_bar.setValue(0)\n            return False\n        add=0x02080\n        TYPE=0\n        with serial.Serial(com_open, 38400, timeout=1) as ser:\n            payload = b'\\x14\\x05' + b'\\x04\\x00' + b'\\x82\\x40\\x74\\x65'  # cmd_id + cmd_len (0+4) + unix timestamp LE\n            crc = self.crc16_ccitt(payload)\n            payload = payload + bytes([crc & 0xFF, ]) + bytes([crc >> 8, ])  # swap bytes of crc to get little endian\n            message = b'\\xAB\\xCD' + b'\\x08\\x00' + self.payload_xor(payload) + b'\\xDC\\xBA'\n            print('>>', message.hex())\n            ser.write(message)\n            full_response = ser.read(128)\n            if len(full_response) == 0:\n                self.message('写入失败')\n                self.progress_bar.setValue(0)\n                self.enable_all_widgets()\n                return False;\n            print('<<', full_response.hex())\n            payload_decoded = self.payload_xor(full_response[4:-4])  # skip header and checksum\n            s = struct.unpack_from('<HH20s', payload_decoded)\n            print('CMD: 0x{:04X}'.format(s[0]))\n            print('LEN: 0x{:04X}'.format(s[1]))\n            print('VER: {}'.format(s[2].split(b'\\0', 1)[0].decode()))  # null terminated string\n            s = format(s[2].split(b'\\0', 1)[0].decode())\n            # 检查是否以\"LOSEHU\"开头且以\"K\"结尾\n\n            if s.startswith(\"LOSEHU\") and s.endswith(\"K\"):\n                add = 0x02080\n            elif s.startswith(\"LOSEHU\") and s.endswith(\"H\"):\n                add = 0x02080\n\n\n            else:\n                self.message('该固件不支持开机图片')\n                self.progress_bar.setValue(0)\n                self.enable_all_widgets()\n                return False;\n\n        num=128\n        self.progress_bar.setValue(20)\n        # compress_pixels = [0] * 1024\n        #\n        # for i in range(8):\n        #     for j in range(128):\n        #         sum=0\n        #         for k in range(8):\n        #             sum=sum+(pixel_list[(k+i*8)*128+j]<<k)\n        #         if i==1:\n        #             compress_pixels[i*128+j]=255\n        #         else:\n        #             compress_pixels[i * 128 + j] = 0\n\n        try:\n            with serial.Serial(com_open, 38400, timeout=1) as ser:\n                pass\n                for i in range(8):\n                    add1=add%0x10000\n\n                    payload = b'\\x38\\x05' + b'\\x8A\\x00' + b'\\x00\\x00' + b'\\x82\\x00' + b'\\x82\\x40\\x74\\x65' +  add1.to_bytes(2, byteorder='little')\n\n\n                    for value in compress_pixels[i*128:i*128+128]:\n                        payload += value.to_bytes(1, byteorder='big')  # 转换为字节并添加到 payload\n\n                    # 将 payload 中的最后四个字节替换为当前时间戳\n                    crc = self.crc16_ccitt(payload)\n                    payload = payload + bytes([crc & 0xFF, ]) + bytes([crc >> 8, ])  # swap bytes of crc to get little endian\n\n                    message = b'\\xAB\\xCD' + b'\\x8e\\x00' + self.payload_xor(payload) + b'\\xDC\\xBA'\n                    hex_payload = ' '.join(hex(byte) for byte in message)\n                    print(hex_payload)\n                    ser.write(message)\n                    full_response = ser.read(128)\n                    if len(full_response) == 0:\n                        self.message('写入失败')\n                        self.progress_bar.setValue(0)\n                        self.enable_all_widgets()\n                        return False;\n                    add=add+128\n                    self.progress_bar.setValue(20+(i+1)*10)\n            self.message('写入成功')\n            self.progress_bar.setValue(0)\n            self.enable_all_widgets()\n\n\n        except serial.SerialException:\n            self.self.message('写入失败')\n            self.progress_bar.setValue(0)\n            self.enable_all_widgets()\n            return False;\n\n\n\n    def disable_all_widgets(self):\n        for widget in self.findChildren((QComboBox, QPushButton,QRadioButton)):\n            widget.setEnabled(False)\n\n    def enable_all_widgets(self):\n        for widget in self.findChildren((QComboBox, QPushButton,QRadioButton)):\n            widget.setEnabled(True)\n    def show_img(self,binarized_image):\n        pixmap = QPixmap.fromImage(self.resize_image_qimage(binarized_image, 256, 128))\n        self.label.setPixmap(pixmap)\n    def binarize_image1(self, original_image):\n        global turn_color\n        binarized_image = original_image.convertToFormat(QImage.Format_Mono)\n        binarized_image = binarized_image.convertToFormat(QImage.Format_Grayscale8)\n\n        if turn_color:\n            binarized_image=self.invert_grayscale_image(binarized_image)\n        return binarized_image\n\n    def otsu_threshold(self,qimage):\n        # Convert QImage to grayscale\n        gray_qimage = qimage.convertToFormat(QImage.Format_Grayscale8)\n\n        # Calculate histogram\n        histogram = [0] * 256\n        total_pixels = gray_qimage.width() * gray_qimage.height()\n\n        for y in range(gray_qimage.height()):\n            for x in range(gray_qimage.width()):\n                pixel = QColor(gray_qimage.pixel(x, y))\n                histogram[pixel.red()] += 1\n\n        # Compute Otsu's threshold\n        sum_total = 0\n        for i in range(256):\n            sum_total += i * histogram[i]\n\n        sumB = 0\n        wB = 0\n        maximum = 0.0\n        threshold = 0\n\n        for i in range(256):\n            wB += histogram[i]\n            if wB == 0:\n                continue\n            wF = total_pixels - wB\n            if wF == 0:\n                break\n            sumB += i * histogram[i]\n            mB = sumB / wB\n            mF = (sum_total - sumB) / wF\n            between = wB * wF * (mB - mF) * (mB - mF)\n            if between >= maximum:\n                threshold = i\n                maximum = between\n\n        return threshold\n    def binarize_image2(self, qimage):\n        global  turn_color\n        threshold = self.otsu_threshold(qimage)\n\n        # Convert QImage to grayscale\n        gray_qimage = qimage.convertToFormat(QImage.Format_Grayscale8)\n\n        # Apply Otsu's thresholding\n        for y in range(gray_qimage.height()):\n            for x in range(gray_qimage.width()):\n                pixel = QColor(gray_qimage.pixel(x, y))\n                if pixel.red() > threshold:\n                    gray_qimage.setPixel(x, y, QColor(255, 255, 255).rgb())  # White pixel\n                else:\n                    gray_qimage.setPixel(x, y, QColor(0, 0, 0).rgb())  # Black pixel\n        if turn_color:\n            gray_qimage=self.invert_grayscale_image(gray_qimage)\n        return gray_qimage\n\n    def resize_image_qimage(self, image,width,high):\n\n\n        # 缩放图像\n        resized_image = image.scaled(width, high)\n\n        return resized_image\n\n    def payload_xor(self,payload):\n        XOR_ARRAY = bytes.fromhex('166c14e62e910d402135d5401303e980')\n        XOR_LEN = len(XOR_ARRAY)\n\n        ba = bytearray(payload)\n        for i in range(0, len(ba)):\n            ba[i] ^= XOR_ARRAY[i % XOR_LEN]\n        return bytes(ba)\n\n    def crc16_ccitt(self,data):\n        i2 = 0\n        for i3 in range(0, len(data)):\n            out = Crc16Tab[((i2 >> 8) ^ data[i3]) & 255]\n            i2 = out ^ (i2 << 8)\n\n        return 65535 & i2\n\n    def convert_payload_to_hex(self,code):\n        payload_decoded = self.payload_xor(code[4:-4])  # 跳过头部和尾部的校验信息\n        hex_payload = ' '.join(['{:02X}'.format(byte) for byte in payload_decoded])\n        return hex_payload\n    def message(self,text):\n        msg_box = QMessageBox()\n        msg_box.setWindowTitle(\"提示\")\n        msg_box.setText(text)\n        msg_box.setIcon(QMessageBox.Information)\n        msg_box.setStandardButtons(QMessageBox.Ok)\n        msg_box.exec()\n    def time_set(self):\n        global com_open\n        try:\n            with serial.Serial(com_open, 38400, timeout=1) as ser:\n                settime = b'\\xAB\\xCD\\x08\\x00\\x02\\x69\\x10\\xE6\\xAC\\xD1\\x79\\x25\\x9D\\xAD\\xDC\\xBA'\n                ser.write(settime)\n                full_response = ser.read(128)\n                if len(full_response) == 0:\n                    self.populate_serial_ports()  # Populate available serial ports\n                    self.message(\"连接失败\")\n                    return False  # Connection failed due to exception\n\n\n\n        except serial.SerialException:\n            self.message(\"连接失败\")\n\n            return False  # Connection failed due to exception\n\n    def invert_grayscale_image(self,image):\n\n\n        width = image.width()\n        height = image.height()\n\n        for y in range(height):\n            for x in range(width):\n                pixel_value = image.pixel(x, y)\n                inverted_value = 255 - qGray(pixel_value)\n\n                inverted_pixel = qRgb(inverted_value, inverted_value, inverted_value)\n                image.setPixel(x, y, inverted_pixel)\n\n        return image\nif __name__ == \"__main__\":\n    app = QApplication(sys.argv)\n    window = MainWindow()\n    window.show()\n    sys.exit(app.exec_())\n"
  },
  {
    "path": "写频脚本/uvk5_cn.py",
    "content": "# Quansheng UV-K5 driver (c) 2023 Jacek Lipkowski <sq5bpf@lipkowski.org>\n# Modified for Full Chinese Firmware by hank9999\n#\n# based on template.py Copyright 2012 Dan Smith <dsmith@danplanet.com>\n#\n#\n# This is a preliminary version of a driver for the UV-K5\n# It is based on my reverse engineering effort described here:\n# https://github.com/sq5bpf/uvk5-reverse-engineering\n#\n# Warning: this driver is experimental, it may brick your radio,\n# eat your lunch and mess up your configuration.\n#\n#\n# This program is free software: you can redistribute it and/or modify\n# it under the terms of the GNU General Public License as published by\n# the Free Software Foundation, either version 2 of the License, or\n# (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n# GNU General Public License for more details.\n#\n# You should have received a copy of the GNU General Public License\n# along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\n\nimport struct\nimport logging\n\nfrom chirp import chirp_common, directory, bitwise, memmap, errors, util\nfrom chirp.errors import InvalidValueError\nfrom chirp.settings import RadioSetting, RadioSettingGroup, \\\n      RadioSettingValueBoolean, RadioSettingValueList, \\\n      RadioSettingValueInteger, RadioSettingValueString, \\\n      RadioSettings, RadioSettingValue\n\nLOG = logging.getLogger(__name__)\n\n# Show the obfuscated version of commands. Not needed normally, but\n# might be useful for someone who is debugging a similar radio\nDEBUG_SHOW_OBFUSCATED_COMMANDS = False\n\n# Show the memory being written/received. Not needed normally, because\n# this is the same information as in the packet hexdumps, but\n# might be useful for someone debugging some obscure memory issue\nDEBUG_SHOW_MEMORY_ACTIONS = False\n\nMEM_FORMAT = \"\"\"\n#seekto 0x0000;\nstruct {\n  ul32 freq;\n  ul32 offset;\n  u8 rxcode;\n  u8 txcode;\n\n  u8 unknown1:2,\n  txcodeflag:2,\n  unknown2:2,\n  rxcodeflag:2;\n\n  //u8 flags1;\n  u8 flags1_unknown7:1,\n  flags1_unknown6:1,\n  flags1_unknown5:1,\n  enable_am:1,\n  flags1_unknown3:1,\n  is_in_scanlist:1,\n  shift:2;\n\n  //u8 flags2;\n  u8 flags2_unknown7:1,\n  flags2_unknown6:1,\n  flags2_unknown5:1,\n  bclo:1,\n  txpower:2,\n  bandwidth:1,\n  freq_reverse:1;\n\n  //u8 dtmf_flags;\n  u8 dtmf_flags_unknown7:1,\n  dtmf_flags_unknown6:1,\n  dtmf_flags_unknown5:1,\n  dtmf_flags_unknown4:1,\n  dtmf_flags_unknown3:1,\n  dtmf_pttid:2,\n  dtmf_decode:1;\n\n\n  u8 step;\n  u8 scrambler;\n} channel[214];\n\n#seekto 0xd60;\nstruct {\nu8 is_scanlist1:1,\nis_scanlist2:1,\nunknown1:1,\nunknown2:1,\nis_free:1,\nband:3;\n} channel_attributes[200];\n\n#seekto 0xe40;\nul16 fmfreq[20];\n\n#seekto 0xe70;\nu8 call_channel;\nu8 squelch;\nu8 max_talk_time;\nu8 noaa_autoscan;\nu8 key_lock;\nu8 vox_switch;\nu8 vox_level;\nu8 mic_gain;\nu8 unknown3;\nu8 channel_display_mode;\nu8 crossband;\nu8 battery_save;\nu8 dual_watch;\nu8 backlight_auto_mode;\nu8 tail_note_elimination;\nu8 vfo_open;\n\n#seekto 0xe90;\nu8 beep_control;\nu8 key1_shortpress_action;\nu8 key1_longpress_action;\nu8 key2_shortpress_action;\nu8 key2_longpress_action;\nu8 scan_resume_mode;\nu8 auto_keypad_lock;\nu8 power_on_dispmode;\nu8 password[4];\n\n#seekto 0xea0;\nu8 keypad_tone;\nu8 language;\n\n#seekto 0xea8;\nu8 alarm_mode;\nu8 reminding_of_end_talk;\nu8 repeater_tail_elimination;\n\n#seekto 0xeb0;\nchar logo_line1[16];\nchar logo_line2[16];\n\n#seekto 0xed0;\nstruct {\nu8 side_tone;\nchar separate_code;\nchar group_call_code;\nu8 decode_response;\nu8 auto_reset_time;\nu8 preload_time;\nu8 first_code_persist_time;\nu8 hash_persist_time;\nu8 code_persist_time;\nu8 code_interval_time;\nu8 permit_remote_kill;\n} dtmf_settings;\n\n#seekto 0xee0;\nstruct {\nchar dtmf_local_code[3];\nchar unused1[5];\nchar kill_code[5];\nchar unused2[3];\nchar revive_code[5];\nchar unused3[3];\nchar dtmf_up_code[16];\nchar dtmf_down_code[16];\n} dtmf_settings_numbers;\n\n#seekto 0xf18;\nu8 scanlist_default;\nu8 scanlist1_priority_scan;\nu8 scanlist1_priority_ch1;\nu8 scanlist1_priority_ch2;\nu8 scanlist2_priority_scan;\nu8 scanlist2_priority_ch1;\nu8 scanlist2_priority_ch2;\nu8 scanlist_unknown_0xff;\n\n\n#seekto 0xf40;\nstruct {\nu8 flock;\nu8 tx350;\nu8 killed;\nu8 tx200;\nu8 tx500;\nu8 en350;\nu8 enscramble;\n} lock;\n\n#seekto 0xf50;\nstruct {\nchar name[16];\n} channelname[200];\n\n#seekto 0x1c00;\nstruct {\nchar name[8];\nchar number[3];\nchar unused_00[5];\n} dtmfcontact[16];\n\n#seekto 0x1fff;\nu8 mdc_num;\n\n#seekto 0x1d00;\nstruct {\n    u8 id[2];\n    char name[14];\n} mdccontact1[22];\n\n#seekto 0x1ed0;\nstruct {\nstruct {\n    u8 start;\n    u8 mid;\n    u8 end;\n} low;\nstruct {\n    u8 start;\n    u8 mid;\n    u8 end;\n} medium;\nstruct {\n    u8 start;\n    u8 mid;\n    u8 end;\n} high;\nu8 unused_00[7];\n} perbandpowersettings[7];\n\n#seekto 0x1f40;\nul16 battery_level[6];\n\"\"\"\n# bits that we will save from the channel structure (mostly unknown)\nSAVE_MASK_0A = 0b11001100\nSAVE_MASK_0B = 0b11101100\nSAVE_MASK_0C = 0b11100000\nSAVE_MASK_0D = 0b11111000\nSAVE_MASK_0E = 0b11110001\nSAVE_MASK_0F = 0b11110000\n\n# flags1\nFLAGS1_OFFSET_NONE = 0b00\nFLAGS1_OFFSET_MINUS = 0b10\nFLAGS1_OFFSET_PLUS = 0b01\n\nPOWER_HIGH = 0b10\nPOWER_MEDIUM = 0b01\nPOWER_LOW = 0b00\n\n# dtmf_flags\nPTTID_LIST = [\"off\", \"BOT\", \"EOT\", \"BOTH\"]\n\n# power\nUVK5_POWER_LEVELS = [chirp_common.PowerLevel(\"Low\",  watts=1.50),\n                     chirp_common.PowerLevel(\"Med\",  watts=3.00),\n                     chirp_common.PowerLevel(\"High\", watts=5.00),\n                     ]\n\n# scrambler\nSCRAMBLER_LIST = [\"off\", \"1\", \"2\", \"3\", \"4\", \"5\", \"6\", \"7\", \"8\", \"9\", \"10\"]\n\n# channel display mode\nCHANNELDISP_LIST = [\"Frequency\", \"Channel No\", \"Channel Name\"]\n# battery save\nBATSAVE_LIST = [\"OFF\", \"1:1\", \"1:2\", \"1:3\", \"1:4\"]\n\n# Backlight auto mode\nBACKLIGHT_LIST = [\"Off\", \"1s\", \"2s\", \"3s\", \"4s\", \"5s\"]\n\n# Crossband receiving/transmitting\nCROSSBAND_LIST = [\"Off\", \"Band A\", \"Band B\"]\nDUALWATCH_LIST = CROSSBAND_LIST\n\n# steps\nSTEPS = [2.5, 5.0, 6.25, 10.0, 12.5, 25.0, 8.33]\n\n# ctcss/dcs codes\nTMODES = [\"\", \"Tone\", \"DTCS\", \"DTCS\"]\nTONE_NONE = 0\nTONE_CTCSS = 1\nTONE_DCS = 2\nTONE_RDCS = 3\n\n\nCTCSS_TONES = [\n    67.0, 69.3, 71.9, 74.4, 77.0, 79.7, 82.5, 85.4,\n    88.5, 91.5, 94.8, 97.4, 100.0, 103.5, 107.2, 110.9,\n    114.8, 118.8, 123.0, 127.3, 131.8, 136.5, 141.3, 146.2,\n    151.4, 156.7, 159.8, 162.2, 165.5, 167.9, 171.3, 173.8,\n    177.3, 179.9, 183.5, 186.2, 189.9, 192.8, 196.6, 199.5,\n    203.5, 206.5, 210.7, 218.1, 225.7, 229.1, 233.6, 241.8,\n    250.3, 254.1\n]\n\n# lifted from ft4.py\nDTCS_CODES = [\n    23,  25,  26,  31,  32,  36,  43,  47,  51,  53,  54,\n    65,  71,  72,  73,  74,  114, 115, 116, 122, 125, 131,\n    132, 134, 143, 145, 152, 155, 156, 162, 165, 172, 174,\n    205, 212, 223, 225, 226, 243, 244, 245, 246, 251, 252,\n    255, 261, 263, 265, 266, 271, 274, 306, 311, 315, 325,\n    331, 332, 343, 346, 351, 356, 364, 365, 371, 411, 412,\n    413, 423, 431, 432, 445, 446, 452, 454, 455, 462, 464,\n    465, 466, 503, 506, 516, 523, 526, 532, 546, 565, 606,\n    612, 624, 627, 631, 632, 654, 662, 664, 703, 712, 723,\n    731, 732, 734, 743, 754\n]\n\nFLOCK_LIST = [\"Off\", \"FCC\", \"CE\", \"GB\", \"430\", \"438\"]\n\nSCANRESUME_LIST = [\"TO: Resume after 5 seconds\",\n                   \"CO: Resume after signal disappears\",\n                   \"SE: Stop scanning after receiving a signal\"]\n\nWELCOME_LIST = [\"Full Screen\", \"Welcome Info\", \"Voltage\"]\nKEYPADTONE_LIST = [\"Off\", \"Chinese\", \"English\"]\nLANGUAGE_LIST = [\"Chinese\", \"English\"]\nALARMMODE_LIST = [\"SITE\", \"TONE\"]\nREMENDOFTALK_LIST = [\"Off\", \"ROGER\", \"MDC\"]\nRTE_LIST = [\"Off\", \"100ms\", \"200ms\", \"300ms\", \"400ms\",\n            \"500ms\", \"600ms\", \"700ms\", \"800ms\", \"900ms\"]\n\nMEM_SIZE = 0x2000  # size of all memory\nPROG_SIZE = 0x1fff  # size of the memory that we will write\nMEM_BLOCK = 0x80  # largest block of memory that we can reliably write\n\n# fm radio supported frequencies\nFMMIN = 76.0\nFMMAX = 108.0\n\n# bands supported by the UV-K5\nBANDS = {\n        0: [50.0, 76.0],\n        1: [108.0, 135.9999],\n        2: [136.0, 199.9990],\n        3: [200.0, 299.9999],\n        4: [350.0, 399.9999],\n        5: [400.0, 469.9999],\n        6: [470.0, 600.0]\n        }\n\n# for radios with modified firmware:\nBANDS_NOLIMITS = {\n        0: [18.0, 76.0],\n        1: [108.0, 135.9999],\n        2: [136.0, 199.9990],\n        3: [200.0, 299.9999],\n        4: [350.0, 399.9999],\n        5: [400.0, 469.9999],\n        6: [470.0, 1300.0]\n        }\n\nSPECIALS = {\n        \"F1(50M-76M)A\": 200,\n        \"F1(50M-76M)B\": 201,\n        \"F2(108M-136M)A\": 202,\n        \"F2(108M-136M)B\": 203,\n        \"F3(136M-174M)A\": 204,\n        \"F3(136M-174M)B\": 205,\n        \"F4(174M-350M)A\": 206,\n        \"F4(174M-350M)B\": 207,\n        \"F5(350M-400M)A\": 208,\n        \"F5(350M-400M)B\": 209,\n        \"F6(400M-470M)A\": 210,\n        \"F6(400M-470M)B\": 211,\n        \"F7(470M-600M)A\": 212,\n        \"F7(470M-600M)B\": 213\n        }\n\nVFO_CHANNEL_NAMES = [\"F1(50M-76M)A\", \"F1(50M-76M)B\",\n                     \"F2(108M-136M)A\", \"F2(108M-136M)B\",\n                     \"F3(136M-174M)A\", \"F3(136M-174M)B\",\n                     \"F4(174M-350M)A\", \"F4(174M-350M)B\",\n                     \"F5(350M-400M)A\", \"F5(350M-400M)B\",\n                     \"F6(400M-470M)A\", \"F6(400M-470M)B\",\n                     \"F7(470M-600M)A\", \"F7(470M-600M)B\"]\n\nSCANLIST_LIST = [\"None\", \"1\", \"2\", \"1+2\"]\n\nDTMF_CHARS = \"0123456789ABCD*# \"\nDTMF_CHARS_ID = \"0123456789ABCDabcd\"\nDTMF_CHARS_KILL = \"0123456789ABCDabcd\"\nDTMF_CHARS_UPDOWN = \"0123456789ABCDabcd#* \"\nDTMF_CODE_CHARS = \"ABCD*# \"\nDTMF_DECODE_RESPONSE_LIST = [\"None\", \"Ring\", \"Reply\", \"Both\"]\n\nKEYACTIONS_LIST = [\"None\", \"Flashlight on/off\", \"Power select\",\n                   \"Monitor\", \"Scan on/off\", \"VOX on/off\",\n                   \"Alarm on/off\", \"FM radio on/off\", \"Transmit 1750 Hz\"]\n\n\nFONT_MAPPING = {\n    128: {1: '一', 2: '乙', 3: '二', 4: '十', 5: '丁', 6: '厂', 7: '七', 8: '卜', 9: '八', 10: '人', 11: '入', 12: '乂',\n          13: '儿', 14: '九', 15: '匕', 16: '几', 17: '刁', 18: '了', 19: '乃', 20: '刀', 21: '力', 22: '又', 23: '乜',\n          24: '三', 25: '干', 26: '亍', 27: '于', 28: '亏', 29: '士', 30: '土', 31: '工', 32: '才', 33: '下', 34: '寸',\n          35: '丈', 36: '大', 37: '兀', 38: '与', 39: '万', 40: '弋', 41: '上', 42: '小', 43: '口', 44: '山', 45: '巾',\n          46: '千', 47: '乞', 48: '川', 49: '亿', 50: '彳', 51: '个', 52: '么', 53: '久', 54: '勺', 55: '丸', 56: '夕',\n          57: '凡', 58: '及', 59: '广', 60: '亡', 61: '门', 62: '丫', 63: '义', 64: '之', 65: '尸', 66: '已', 67: '巳',\n          68: '弓', 69: '己', 70: '卫', 71: '孑', 72: '子', 73: '孓', 74: '也', 75: '女', 76: '飞', 77: '刃', 78: '习',\n          79: '叉', 80: '马', 81: '乡', 82: '幺', 83: '丰', 84: '王', 85: '井', 86: '开', 87: '亓', 88: '夫', 89: '天',\n          90: '元', 91: '无', 92: '韦', 93: '云', 94: '专', 95: '丐', 96: '扎', 97: '廿', 98: '艺', 99: '木', 100: '五',\n          101: '支', 102: '厅', 103: '卅', 104: '不', 105: '仄', 106: '太', 107: '犬', 108: '区', 109: '历', 110: '友',\n          111: '歹', 112: '尤', 113: '匹', 114: '厄', 115: '车', 116: '巨', 117: '牙', 118: '屯', 119: '戈', 120: '比',\n          121: '互', 122: '切', 123: '瓦', 124: '止', 125: '少', 126: '曰', 127: '日', 128: '中', 129: '贝', 130: '内',\n          131: '水', 132: '冈', 133: '见', 134: '手', 135: '午', 136: '牛', 137: '毛', 138: '气', 139: '壬', 140: '升',\n          141: '夭', 142: '长', 143: '仁', 144: '仃', 145: '什', 146: '片', 147: '仆', 148: '仉', 149: '化', 150: '仇',\n          151: '币', 152: '仂', 153: '仍', 154: '仅', 155: '斤', 156: '爪', 157: '反', 158: '兮', 159: '刈', 160: '介',\n          161: '父', 162: '爻', 163: '从', 164: '仑', 165: '今', 166: '凶', 167: '分', 168: '乏', 169: '公', 170: '仓',\n          171: '月', 172: '氏', 173: '勿', 174: '风', 175: '欠', 176: '丹', 177: '匀', 178: '乌', 179: '勾', 180: '殳',\n          181: '凤', 182: '卞', 183: '六', 184: '文', 185: '亢', 186: '方', 187: '闩', 188: '火', 189: '为', 190: '斗',\n          191: '忆', 192: '计', 193: '订', 194: '户', 195: '讣', 196: '认', 197: '讥', 198: '冗', 199: '心', 200: '尹',\n          201: '尺', 202: '夬', 203: '引', 204: '丑', 205: '爿', 206: '巴', 207: '孔', 208: '队', 209: '办', 210: '以',\n          211: '允', 212: '邓', 213: '予', 214: '劝', 215: '双', 216: '书', 217: '毋', 218: '幻', 219: '玉', 220: '刊',\n          221: '末', 222: '未', 223: '示', 224: '击', 225: '邗', 226: '戋', 227: '打', 228: '巧', 229: '正', 230: '扑',\n          231: '卉', 232: '扒', 233: '邛', 234: '功', 235: '扔', 236: '去', 237: '甘', 238: '世', 239: '艾', 240: '艽',\n          241: '古', 242: '节', 243: '艿', 244: '本', 245: '术', 246: '札', 247: '可', 248: '叵', 249: '匝', 250: '丙',\n          251: '左', 252: '厉', 253: '丕', 254: '石', 255: '右'},\n    129: {1: '布', 2: '夯', 3: '龙', 4: '戊', 5: '平', 6: '灭', 7: '轧', 8: '东', 9: '匜', 10: '劢', 11: '卡', 12: '北',\n          13: '占', 14: '凸', 15: '卢', 16: '业', 17: '旧', 18: '帅', 19: '归', 20: '目', 21: '旦', 22: '且', 23: '叮',\n          24: '叶', 25: '甲', 26: '申', 27: '号', 28: '电', 29: '田', 30: '由', 31: '卟', 32: '叭', 33: '只', 34: '央',\n          35: '史', 36: '叱', 37: '叽', 38: '兄', 39: '叼', 40: '叩', 41: '叫', 42: '叻', 43: '叨', 44: '另', 45: '叹',\n          46: '冉', 47: '皿', 48: '凹', 49: '囚', 50: '四', 51: '生', 52: '失', 53: '矢', 54: '氕', 55: '乍', 56: '禾',\n          57: '仨', 58: '仕', 59: '丘', 60: '付', 61: '仗', 62: '代', 63: '仙', 64: '仟', 65: '仡', 66: '仫', 67: '伋',\n          68: '们', 69: '仪', 70: '白', 71: '仔', 72: '他', 73: '仞', 74: '斥', 75: '卮', 76: '瓜', 77: '乎', 78: '丛',\n          79: '令', 80: '用', 81: '甩', 82: '印', 83: '氐', 84: '乐', 85: '尔', 86: '句', 87: '匆', 88: '犰', 89: '册',\n          90: '卯', 91: '犯', 92: '外', 93: '处', 94: '冬', 95: '鸟', 96: '务', 97: '刍', 98: '包', 99: '饥', 100: '主',\n          101: '市', 102: '庀', 103: '邝', 104: '立', 105: '冯', 106: '邙', 107: '玄', 108: '闪', 109: '兰', 110: '半',\n          111: '汀', 112: '汁', 113: '汇', 114: '头', 115: '汈', 116: '汉', 117: '忉', 118: '宁', 119: '穴', 120: '宄',\n          121: '它', 122: '讦', 123: '讧', 124: '讨', 125: '写', 126: '让', 127: '礼', 128: '讪', 129: '讫', 130: '训',\n          131: '必', 132: '议', 133: '讯', 134: '记', 135: '永', 136: '司', 137: '尻', 138: '尼', 139: '民', 140: '弗',\n          141: '弘', 142: '阢', 143: '出', 144: '阡', 145: '辽', 146: '奶', 147: '奴', 148: '尕', 149: '加', 150: '召',\n          151: '皮', 152: '边', 153: '孕', 154: '发', 155: '圣', 156: '对', 157: '弁', 158: '台', 159: '矛', 160: '纠',\n          161: '驭', 162: '母', 163: '幼', 164: '丝', 165: '匡', 166: '耒', 167: '邦', 168: '玎', 169: '玑', 170: '式',\n          171: '迂', 172: '刑', 173: '邢', 174: '戎', 175: '动', 176: '圩', 177: '圬', 178: '圭', 179: '扛', 180: '寺',\n          181: '吉', 182: '扣', 183: '扦', 184: '圪', 185: '考', 186: '托', 187: '圳', 188: '老', 189: '圾', 190: '巩',\n          191: '执', 192: '扩', 193: '圹', 194: '扪', 195: '扫', 196: '圯', 197: '圮', 198: '地', 199: '扬', 200: '场',\n          201: '耳', 202: '芋', 203: '芏', 204: '共', 205: '芊', 206: '芍', 207: '芨', 208: '芄', 209: '芒', 210: '亚',\n          211: '芝', 212: '芎', 213: '芑', 214: '芗', 215: '朽', 216: '朴', 217: '机', 218: '权', 219: '过', 220: '亘',\n          221: '臣', 222: '吏', 223: '再', 224: '协', 225: '西', 226: '压', 227: '厌', 228: '厍', 229: '戌', 230: '在',\n          231: '百', 232: '有', 233: '存', 234: '而', 235: '页', 236: '匠', 237: '夸', 238: '夺', 239: '夼', 240: '灰',\n          241: '达', 242: '戍', 243: '尥', 244: '列', 245: '死', 246: '成', 247: '夹', 248: '夷', 249: '轨', 250: '邪',\n          251: '尧', 252: '划', 253: '迈', 254: '毕', 255: '至'},\n    130: {1: '此', 2: '乩', 3: '贞', 4: '师', 5: '尘', 6: '尖', 7: '劣', 8: '光', 9: '当', 10: '吁', 11: '早', 12: '吐',\n          13: '吓', 14: '旯', 15: '曳', 16: '虫', 17: '曲', 18: '团', 19: '同', 20: '吕', 21: '吊', 22: '吃', 23: '因',\n          24: '吸', 25: '吗', 26: '吆', 27: '屿', 28: '屹', 29: '岌', 30: '帆', 31: '岁', 32: '回', 33: '岂', 34: '屺',\n          35: '则', 36: '刚', 37: '网', 38: '肉', 39: '凼', 40: '囝', 41: '囡', 42: '钆', 43: '钇', 44: '年', 45: '朱',\n          46: '缶', 47: '氘', 48: '氖', 49: '牝', 50: '先', 51: '丢', 52: '廷', 53: '舌', 54: '竹', 55: '迁', 56: '乔',\n          57: '迄', 58: '伟', 59: '传', 60: '乒', 61: '乓', 62: '休', 63: '伍', 64: '伎', 65: '伏', 66: '伛', 67: '优',\n          68: '臼', 69: '伢', 70: '伐', 71: '仳', 72: '延', 73: '佤', 74: '仲', 75: '仵', 76: '件', 77: '任', 78: '伤',\n          79: '伥', 80: '价', 81: '伦', 82: '份', 83: '伧', 84: '华', 85: '仰', 86: '伉', 87: '仿', 88: '伙', 89: '伪',\n          90: '伫', 91: '自', 92: '伊', 93: '血', 94: '向', 95: '囟', 96: '似', 97: '后', 98: '行', 99: '甪', 100: '舟',\n          101: '全', 102: '会', 103: '杀', 104: '合', 105: '兆', 106: '企', 107: '汆', 108: '氽', 109: '众', 110: '爷',\n          111: '伞', 112: '创', 113: '刖', 114: '肌', 115: '肋', 116: '朵', 117: '杂', 118: '夙', 119: '危', 120: '旬',\n          121: '旭', 122: '旮', 123: '旨', 124: '负', 125: '犴', 126: '刎', 127: '犷', 128: '匈', 129: '犸', 130: '舛',\n          131: '各', 132: '名', 133: '多', 134: '凫', 135: '争', 136: '邬', 137: '色', 138: '饧', 139: '冱', 140: '壮',\n          141: '冲', 142: '妆', 143: '冰', 144: '庄', 145: '庆', 146: '亦', 147: '刘', 148: '齐', 149: '交', 150: '次',\n          151: '衣', 152: '产', 153: '决', 154: '亥', 155: '邡', 156: '充', 157: '妄', 158: '闭', 159: '问', 160: '闯',\n          161: '羊', 162: '并', 163: '关', 164: '米', 165: '灯', 166: '州', 167: '汗', 168: '污', 169: '江', 170: '汕',\n          171: '汔', 172: '汲', 173: '汐', 174: '汛', 175: '汜', 176: '池', 177: '汝', 178: '汤', 179: '汊', 180: '忖',\n          181: '忏', 182: '忙', 183: '兴', 184: '宇', 185: '守', 186: '宅', 187: '字', 188: '安', 189: '讲', 190: '讳',\n          191: '讴', 192: '军', 193: '讵', 194: '讶', 195: '祁', 196: '讷', 197: '许', 198: '讹', 199: '论', 200: '讼',\n          201: '农', 202: '讽', 203: '设', 204: '访', 205: '诀', 206: '聿', 207: '寻', 208: '那', 209: '艮', 210: '厾',\n          211: '迅', 212: '尽', 213: '导', 214: '异', 215: '弛', 216: '阱', 217: '阮', 218: '孙', 219: '阵', 220: '阳',\n          221: '收', 222: '阪', 223: '阶', 224: '阴', 225: '防', 226: '丞', 227: '奸', 228: '如', 229: '妁', 230: '妇',\n          231: '妃', 232: '好', 233: '她', 234: '妈', 235: '戏', 236: '羽', 237: '观', 238: '牟', 239: '欢', 240: '买',\n          241: '纡', 242: '红', 243: '纣', 244: '驮', 245: '纤', 246: '纥', 247: '驯', 248: '纨', 249: '约', 250: '级',\n          251: '纩', 252: '纪', 253: '驰', 254: '纫', 255: '巡'},\n    131: {1: '寿', 2: '玕', 3: '弄', 4: '玙', 5: '麦', 6: '玖', 7: '玚', 8: '玛', 9: '形', 10: '进', 11: '戒', 12: '吞',\n          13: '远', 14: '违', 15: '韧', 16: '运', 17: '扶', 18: '抚', 19: '坛', 20: '抟', 21: '技', 22: '坏', 23: '抔',\n          24: '抠', 25: '坜', 26: '扰', 27: '扼', 28: '拒', 29: '找', 30: '批', 31: '扯', 32: '址', 33: '走', 34: '抄',\n          35: '汞', 36: '坝', 37: '贡', 38: '攻', 39: '赤', 40: '圻', 41: '折', 42: '抓', 43: '扳', 44: '坂', 45: '抡',\n          46: '扮', 47: '抢', 48: '扺', 49: '孝', 50: '坎', 51: '坍', 52: '均', 53: '坞', 54: '抑', 55: '抛', 56: '投',\n          57: '抃', 58: '坟', 59: '坑', 60: '抗', 61: '坊', 62: '抖', 63: '护', 64: '壳', 65: '志', 66: '扭', 67: '块',\n          68: '抉', 69: '声', 70: '把', 71: '报', 72: '拟', 73: '抒', 74: '却', 75: '劫', 76: '毐', 77: '芙', 78: '芫',\n          79: '芜', 80: '苇', 81: '邯', 82: '芸', 83: '芾', 84: '芰', 85: '苈', 86: '苊', 87: '苣', 88: '芽', 89: '芷',\n          90: '芮', 91: '苋', 92: '芼', 93: '苌', 94: '花', 95: '芹', 96: '芥', 97: '苁', 98: '芩', 99: '芬', 100: '苍',\n          101: '芪', 102: '芴', 103: '芡', 104: '芟', 105: '苄', 106: '芳', 107: '严', 108: '苎', 109: '芦', 110: '芯',\n          111: '劳', 112: '克', 113: '芭', 114: '苏', 115: '苡', 116: '杆', 117: '杜', 118: '杠', 119: '材', 120: '村',\n          121: '杖', 122: '杌', 123: '杏', 124: '杉', 125: '巫', 126: '杓', 127: '极', 128: '杧', 129: '杞', 130: '李',\n          131: '杨', 132: '杈', 133: '求', 134: '忑', 135: '孛', 136: '甫', 137: '匣', 138: '更', 139: '束', 140: '吾',\n          141: '豆', 142: '两', 143: '邴', 144: '酉', 145: '丽', 146: '医', 147: '辰', 148: '励', 149: '邳', 150: '否',\n          151: '还', 152: '矶', 153: '奁', 154: '豕', 155: '尬', 156: '歼', 157: '来', 158: '忒', 159: '连', 160: '欤',\n          161: '轩', 162: '轪', 163: '轫', 164: '迓', 165: '邶', 166: '忐', 167: '芈', 168: '步', 169: '卤', 170: '卣',\n          171: '邺', 172: '坚', 173: '肖', 174: '旰', 175: '旱', 176: '盯', 177: '呈', 178: '时', 179: '吴', 180: '呋',\n          181: '助', 182: '县', 183: '里', 184: '呓', 185: '呆', 186: '吱', 187: '吠', 188: '呔', 189: '呕', 190: '园',\n          191: '呖', 192: '呃', 193: '旷', 194: '围', 195: '呀', 196: '吨', 197: '旸', 198: '吡', 199: '町', 200: '足',\n          201: '虬', 202: '邮', 203: '男', 204: '困', 205: '吵', 206: '串', 207: '呙', 208: '呐', 209: '呗', 210: '员',\n          211: '听', 212: '吟', 213: '吩', 214: '呛', 215: '吻', 216: '吹', 217: '呜', 218: '吭', 219: '吣', 220: '吲',\n          221: '吼', 222: '邑', 223: '吧', 224: '囤', 225: '别', 226: '吮', 227: '岍', 228: '帏', 229: '岐', 230: '岖',\n          231: '岈', 232: '岗', 233: '岘', 234: '帐', 235: '岑', 236: '岚', 237: '兕', 238: '财', 239: '囵', 240: '囫',\n          241: '钉', 242: '针', 243: '钊', 244: '钋', 245: '钌', 246: '迕', 247: '氙', 248: '氚', 249: '牡', 250: '告',\n          251: '我', 252: '乱', 253: '利', 254: '秃', 255: '秀'},\n    132: {1: '私', 2: '岙', 3: '每', 4: '佞', 5: '兵', 6: '邱', 7: '估', 8: '体', 9: '何', 10: '佐', 11: '伾', 12: '佑',\n          13: '攸', 14: '但', 15: '伸', 16: '佃', 17: '佚', 18: '作', 19: '伯', 20: '伶', 21: '佣', 22: '低', 23: '你',\n          24: '佝', 25: '佟', 26: '住', 27: '位', 28: '伴', 29: '佗', 30: '身', 31: '皂', 32: '伺', 33: '佛', 34: '伽',\n          35: '囱', 36: '近', 37: '彻', 38: '役', 39: '彷', 40: '返', 41: '佘', 42: '余', 43: '希', 44: '佥', 45: '坐',\n          46: '谷', 47: '孚', 48: '妥', 49: '豸', 50: '含', 51: '邻', 52: '坌', 53: '岔', 54: '肝', 55: '肟', 56: '肛',\n          57: '肚', 58: '肘', 59: '肠', 60: '邸', 61: '龟', 62: '甸', 63: '奂', 64: '免', 65: '劬', 66: '狂', 67: '犹',\n          68: '狈', 69: '狄', 70: '角', 71: '删', 72: '狃', 73: '狁', 74: '鸠', 75: '条', 76: '彤', 77: '卵', 78: '灸',\n          79: '岛', 80: '邹', 81: '刨', 82: '饨', 83: '迎', 84: '饩', 85: '饪', 86: '饫', 87: '饬', 88: '饭', 89: '饮',\n          90: '系', 91: '言', 92: '冻', 93: '状', 94: '亩', 95: '况', 96: '亨', 97: '庑', 98: '床', 99: '庋', 100: '库',\n          101: '庇', 102: '疔', 103: '疖', 104: '疗', 105: '吝', 106: '应', 107: '冷', 108: '这', 109: '庐', 110: '序',\n          111: '辛', 112: '肓', 113: '弃', 114: '冶', 115: '忘', 116: '闰', 117: '闱', 118: '闲', 119: '闳', 120: '间',\n          121: '闵', 122: '闶', 123: '闷', 124: '羌', 125: '判', 126: '兑', 127: '灶', 128: '灿', 129: '灼', 130: '炀',\n          131: '弟', 132: '沣', 133: '汪', 134: '沅', 135: '沄', 136: '沐', 137: '沛', 138: '沔', 139: '汰', 140: '沤',\n          141: '沥', 142: '沌', 143: '沘', 144: '沏', 145: '沚', 146: '沙', 147: '汩', 148: '汨', 149: '汭', 150: '汽',\n          151: '沃', 152: '沂', 153: '沦', 154: '汹', 155: '汾', 156: '泛', 157: '沧', 158: '沨', 159: '沟', 160: '没',\n          161: '汴', 162: '汶', 163: '沆', 164: '沩', 165: '沪', 166: '沈', 167: '沉', 168: '沁', 169: '泐', 170: '怃',\n          171: '忮', 172: '怀', 173: '怄', 174: '忧', 175: '忡', 176: '忤', 177: '忾', 178: '怅', 179: '忻', 180: '忪',\n          181: '怆', 182: '忭', 183: '忱', 184: '快', 185: '忸', 186: '完', 187: '宋', 188: '宏', 189: '牢', 190: '究',\n          191: '穷', 192: '灾', 193: '良', 194: '证', 195: '诂', 196: '诃', 197: '启', 198: '评', 199: '补', 200: '初',\n          201: '社', 202: '祀', 203: '祃', 204: '诅', 205: '识', 206: '诈', 207: '诉', 208: '罕', 209: '诊', 210: '诋',\n          211: '诌', 212: '词', 213: '诎', 214: '诏', 215: '诐', 216: '译', 217: '诒', 218: '君', 219: '灵', 220: '即',\n          221: '层', 222: '屁', 223: '屃', 224: '尿', 225: '尾', 226: '迟', 227: '局', 228: '改', 229: '张', 230: '忌',\n          231: '际', 232: '陆', 233: '阿', 234: '孜', 235: '陇', 236: '陈', 237: '阽', 238: '阻', 239: '阼', 240: '附',\n          241: '坠', 242: '陀', 243: '陂', 244: '陉', 245: '妍', 246: '妩', 247: '妓', 248: '妪', 249: '妣', 250: '妙',\n          251: '妊', 252: '妖', 253: '妗', 254: '姊', 255: '妨'},\n    133: {1: '妫', 2: '妒', 3: '妞', 4: '姒', 5: '妤', 6: '努', 7: '邵', 8: '劭', 9: '忍', 10: '刭', 11: '劲', 12: '甬',\n          13: '邰', 14: '矣', 15: '鸡', 16: '纬', 17: '纭', 18: '驱', 19: '纯', 20: '纰', 21: '纱', 22: '纲', 23: '纳',\n          24: '纴', 25: '纵', 26: '驳', 27: '纶', 28: '纷', 29: '纸', 30: '纹', 31: '纺', 32: '纻', 33: '驴', 34: '纽',\n          35: '纾', 36: '奉', 37: '玩', 38: '玮', 39: '环', 40: '玡', 41: '武', 42: '青', 43: '责', 44: '现', 45: '玫',\n          46: '玠', 47: '玢', 48: '玥', 49: '表', 50: '玦', 51: '甙', 52: '盂', 53: '忝', 54: '规', 55: '匦', 56: '抹',\n          57: '卦', 58: '邽', 59: '坩', 60: '坷', 61: '坯', 62: '拓', 63: '垅', 64: '拢', 65: '拔', 66: '抨', 67: '坪',\n          68: '拣', 69: '拤', 70: '拈', 71: '坫', 72: '垆', 73: '坦', 74: '担', 75: '坤', 76: '押', 77: '抻', 78: '抽',\n          79: '拐', 80: '拃', 81: '拖', 82: '拊', 83: '者', 84: '拍', 85: '顶', 86: '坼', 87: '拆', 88: '拎', 89: '拥',\n          90: '抵', 91: '坻', 92: '拘', 93: '势', 94: '抱', 95: '拄', 96: '垃', 97: '拉', 98: '拦', 99: '幸', 100: '拌',\n          101: '拧', 102: '坨', 103: '坭', 104: '抿', 105: '拂', 106: '拙', 107: '招', 108: '坡', 109: '披', 110: '拨',\n          111: '择', 112: '拚', 113: '抬', 114: '拇', 115: '坳', 116: '拗', 117: '耵', 118: '其', 119: '耶', 120: '取',\n          121: '茉', 122: '苷', 123: '苦', 124: '苯', 125: '昔', 126: '苛', 127: '苤', 128: '若', 129: '茂', 130: '茏',\n          131: '苹', 132: '苫', 133: '苴', 134: '苜', 135: '苗', 136: '英', 137: '苒', 138: '苘', 139: '茌', 140: '苻',\n          141: '苓', 142: '茚', 143: '苟', 144: '茆', 145: '茑', 146: '苑', 147: '苞', 148: '范', 149: '茓', 150: '茔',\n          151: '茕', 152: '直', 153: '苠', 154: '茀', 155: '茁', 156: '茄', 157: '苕', 158: '茎', 159: '苔', 160: '茅',\n          161: '枉', 162: '林', 163: '枝', 164: '杯', 165: '枢', 166: '枥', 167: '柜', 168: '枇', 169: '杪', 170: '杳',\n          171: '枘', 172: '枧', 173: '杵', 174: '枚', 175: '枨', 176: '析', 177: '板', 178: '枞', 179: '松', 180: '枪',\n          181: '枫', 182: '构', 183: '杭', 184: '枋', 185: '杰', 186: '述', 187: '枕', 188: '杻', 189: '杷', 190: '杼',\n          191: '丧', 192: '或', 193: '画', 194: '卧', 195: '事', 196: '刺', 197: '枣', 198: '雨', 199: '卖', 200: '矸',\n          201: '郁', 202: '矻', 203: '矾', 204: '矽', 205: '矿', 206: '砀', 207: '码', 208: '厕', 209: '奈', 210: '刳',\n          211: '奔', 212: '奇', 213: '奄', 214: '奋', 215: '态', 216: '瓯', 217: '欧', 218: '殴', 219: '垄', 220: '殁',\n          221: '郏', 222: '妻', 223: '轰', 224: '顷', 225: '转', 226: '轭', 227: '斩', 228: '轮', 229: '软', 230: '到',\n          231: '郅', 232: '鸢', 233: '非', 234: '叔', 235: '歧', 236: '肯', 237: '齿', 238: '些', 239: '卓', 240: '虎',\n          241: '虏', 242: '肾', 243: '贤', 244: '尚', 245: '盱', 246: '旺', 247: '具', 248: '昊', 249: '昙', 250: '果',\n          251: '味', 252: '杲', 253: '昃', 254: '昆', 255: '国'},\n    134: {1: '哎', 2: '咕', 3: '昌', 4: '呵', 5: '咂', 6: '畅', 7: '呸', 8: '昕', 9: '明', 10: '易', 11: '咙', 12: '昀',\n          13: '昂', 14: '旻', 15: '昉', 16: '炅', 17: '咔', 18: '畀', 19: '虮', 20: '迪', 21: '典', 22: '固', 23: '忠',\n          24: '咀', 25: '呷', 26: '呻', 27: '黾', 28: '咒', 29: '咋', 30: '咐', 31: '呱', 32: '呼', 33: '呤', 34: '咚',\n          35: '鸣', 36: '咆', 37: '咛', 38: '咏', 39: '呢', 40: '咄', 41: '呶', 42: '咖', 43: '呦', 44: '咝', 45: '岵',\n          46: '岢', 47: '岸', 48: '岩', 49: '帖', 50: '罗', 51: '岿', 52: '岬', 53: '岫', 54: '帜', 55: '帙', 56: '帕',\n          57: '岭', 58: '岣', 59: '峁', 60: '刿', 61: '峂', 62: '迥', 63: '岷', 64: '剀', 65: '凯', 66: '帔', 67: '峄',\n          68: '沓', 69: '败', 70: '账', 71: '贩', 72: '贬', 73: '购', 74: '贮', 75: '囹', 76: '图', 77: '罔', 78: '钍',\n          79: '钎', 80: '钏', 81: '钐', 82: '钓', 83: '钒', 84: '钔', 85: '钕', 86: '钗', 87: '邾', 88: '制', 89: '知',\n          90: '迭', 91: '氛', 92: '迮', 93: '垂', 94: '牦', 95: '牧', 96: '物', 97: '乖', 98: '刮', 99: '秆', 100: '和',\n          101: '季', 102: '委', 103: '竺', 104: '秉', 105: '迤', 106: '佳', 107: '侍', 108: '佶', 109: '岳', 110: '佬',\n          111: '佴', 112: '供', 113: '使', 114: '侑', 115: '佰', 116: '侉', 117: '例', 118: '侠', 119: '臾', 120: '侥',\n          121: '版', 122: '侄', 123: '岱', 124: '侦', 125: '侣', 126: '侗', 127: '侃', 128: '侧', 129: '侏', 130: '凭',\n          131: '侨', 132: '侩', 133: '佻', 134: '佾', 135: '佩', 136: '货', 137: '侈', 138: '侪', 139: '佼', 140: '依',\n          141: '佯', 142: '侬', 143: '帛', 144: '卑', 145: '的', 146: '迫', 147: '阜', 148: '侔', 149: '质', 150: '欣',\n          151: '郈', 152: '征', 153: '徂', 154: '往', 155: '爬', 156: '彼', 157: '径', 158: '所', 159: '舍', 160: '金',\n          161: '刽', 162: '郐', 163: '刹', 164: '命', 165: '肴', 166: '郄', 167: '斧', 168: '怂', 169: '爸', 170: '采',\n          171: '籴', 172: '觅', 173: '受', 174: '乳', 175: '贪', 176: '念', 177: '贫', 178: '忿', 179: '瓮', 180: '戗',\n          181: '肼', 182: '肤', 183: '朊', 184: '肺', 185: '肢', 186: '肽', 187: '肱', 188: '肫', 189: '肿', 190: '肭',\n          191: '胀', 192: '朋', 193: '肷', 194: '股', 195: '肮', 196: '肪', 197: '肥', 198: '服', 199: '胁', 200: '周',\n          201: '剁', 202: '昏', 203: '迩', 204: '郇', 205: '鱼', 206: '兔', 207: '狉', 208: '狙', 209: '狎', 210: '狐',\n          211: '忽', 212: '狝', 213: '狗', 214: '狍', 215: '狞', 216: '狒', 217: '咎', 218: '备', 219: '炙', 220: '枭',\n          221: '饯', 222: '饰', 223: '饱', 224: '饲', 225: '饳', 226: '饴', 227: '冽', 228: '变', 229: '京', 230: '享',\n          231: '冼', 232: '庞', 233: '店', 234: '夜', 235: '庙', 236: '府', 237: '底', 238: '庖', 239: '疟', 240: '疠',\n          241: '疝', 242: '疙', 243: '疚', 244: '疡', 245: '剂', 246: '卒', 247: '郊', 248: '兖', 249: '庚', 250: '废',\n          251: '净', 252: '妾', 253: '盲', 254: '放', 255: '於'},\n    135: {1: '刻', 2: '劾', 3: '育', 4: '氓', 5: '闸', 6: '闹', 7: '郑', 8: '券', 9: '卷', 10: '单', 11: '炜', 12: '炬',\n          13: '炖', 14: '炒', 15: '炝', 16: '炊', 17: '炕', 18: '炎', 19: '炉', 20: '炔', 21: '沫', 22: '浅', 23: '法',\n          24: '泔', 25: '泄', 26: '沽', 27: '沭', 28: '河', 29: '泷', 30: '沾', 31: '泸', 32: '沮', 33: '泪', 34: '油',\n          35: '泱', 36: '泅', 37: '泗', 38: '泊', 39: '泠', 40: '泜', 41: '泺', 42: '泃', 43: '沿', 44: '泖', 45: '泡',\n          46: '注', 47: '泣', 48: '泫', 49: '泮', 50: '泞', 51: '沱', 52: '泻', 53: '泌', 54: '泳', 55: '泥', 56: '泯',\n          57: '沸', 58: '泓', 59: '沼', 60: '波', 61: '泼', 62: '泽', 63: '泾', 64: '治', 65: '怔', 66: '怯', 67: '怙',\n          68: '怵', 69: '怖', 70: '怦', 71: '怛', 72: '怏', 73: '性', 74: '怍', 75: '怕', 76: '怜', 77: '怩', 78: '怫',\n          79: '怊', 80: '怿', 81: '怪', 82: '怡', 83: '学', 84: '宝', 85: '宗', 86: '定', 87: '宕', 88: '宠', 89: '宜',\n          90: '审', 91: '宙', 92: '官', 93: '空', 94: '帘', 95: '穸', 96: '穹', 97: '宛', 98: '实', 99: '宓', 100: '诓',\n          101: '诔', 102: '试', 103: '郎', 104: '诖', 105: '诗', 106: '诘', 107: '戾', 108: '肩', 109: '房', 110: '诙',\n          111: '戽', 112: '诚', 113: '郓', 114: '衬', 115: '衫', 116: '衩', 117: '祆', 118: '祎', 119: '祉', 120: '视',\n          121: '祈', 122: '诛', 123: '诜', 124: '话', 125: '诞', 126: '诟', 127: '诠', 128: '诡', 129: '询', 130: '诣',\n          131: '诤', 132: '该', 133: '详', 134: '诧', 135: '诨', 136: '诩', 137: '建', 138: '肃', 139: '隶', 140: '录',\n          141: '帚', 142: '屉', 143: '居', 144: '届', 145: '刷', 146: '鸤', 147: '屈', 148: '弧', 149: '弥', 150: '弦',\n          151: '承', 152: '孟', 153: '陋', 154: '戕', 155: '陌', 156: '孤', 157: '孢', 158: '陕', 159: '亟', 160: '降',\n          161: '函', 162: '陔', 163: '限', 164: '卺', 165: '妹', 166: '姑', 167: '姐', 168: '妲', 169: '妯', 170: '姓',\n          171: '姗', 172: '妮', 173: '始', 174: '帑', 175: '弩', 176: '孥', 177: '驽', 178: '姆', 179: '虱', 180: '迦',\n          181: '迢', 182: '驾', 183: '叁', 184: '参', 185: '迨', 186: '艰', 187: '线', 188: '绀', 189: '绁', 190: '绂',\n          191: '练', 192: '驵', 193: '组', 194: '绅', 195: '细', 196: '驶', 197: '织', 198: '驷', 199: '驸', 200: '驹',\n          201: '终', 202: '绉', 203: '驺', 204: '驻', 205: '绊', 206: '驼', 207: '绋', 208: '绌', 209: '绍', 210: '驿',\n          211: '绎', 212: '经', 213: '骀', 214: '贯', 215: '甾', 216: '砉', 217: '耔', 218: '契', 219: '贰', 220: '奏',\n          221: '春', 222: '帮', 223: '珏', 224: '珐', 225: '珂', 226: '珑', 227: '玷', 228: '玳', 229: '珀', 230: '顸',\n          231: '珍', 232: '玲', 233: '珊', 234: '珉', 235: '珈', 236: '玻', 237: '毒', 238: '型', 239: '韨', 240: '拭',\n          241: '挂', 242: '封', 243: '持', 244: '拮', 245: '拷', 246: '拱', 247: '垭', 248: '挝', 249: '垣', 250: '项',\n          251: '垮', 252: '挎', 253: '垯', 254: '挞', 255: '城'},\n    136: {1: '挟', 2: '挠', 3: '垤', 4: '政', 5: '赴', 6: '赵', 7: '赳', 8: '贲', 9: '垱', 10: '挡', 11: '拽', 12: '垌',\n          13: '哉', 14: '垲', 15: '挺', 16: '括', 17: '挢', 18: '埏', 19: '郝', 20: '垍', 21: '垧', 22: '垢', 23: '拴',\n          24: '拾', 25: '挑', 26: '垛', 27: '指', 28: '垫', 29: '挣', 30: '挤', 31: '垓', 32: '垟', 33: '拼', 34: '垞',\n          35: '挖', 36: '按', 37: '挥', 38: '挦', 39: '挪', 40: '垠', 41: '拯', 42: '拶', 43: '某', 44: '甚', 45: '荆',\n          46: '茸', 47: '革', 48: '茜', 49: '茬', 50: '荐', 51: '荙', 52: '巷', 53: '荚', 54: '荑', 55: '贳', 56: '荛',\n          57: '荜', 58: '茈', 59: '带', 60: '草', 61: '茧', 62: '茼', 63: '莒', 64: '茵', 65: '茴', 66: '茱', 67: '莛',\n          68: '荞', 69: '茯', 70: '荏', 71: '荇', 72: '荃', 73: '荟', 74: '茶', 75: '荀', 76: '茗', 77: '荠', 78: '茭',\n          79: '茨', 80: '荒', 81: '垩', 82: '茳', 83: '茫', 84: '荡', 85: '荣', 86: '荤', 87: '荥', 88: '荦', 89: '荧',\n          90: '荨', 91: '茛', 92: '故', 93: '荩', 94: '胡', 95: '荪', 96: '荫', 97: '茹', 98: '荔', 99: '南', 100: '荬',\n          101: '荭', 102: '药', 103: '柰', 104: '标', 105: '栈', 106: '柑', 107: '枯', 108: '栉', 109: '柯', 110: '柄',\n          111: '柘', 112: '栊', 113: '柩', 114: '枰', 115: '栋', 116: '栌', 117: '相', 118: '查', 119: '柙', 120: '枵',\n          121: '柚', 122: '枳', 123: '柞', 124: '柏', 125: '柝', 126: '栀', 127: '柃', 128: '柢', 129: '栎', 130: '枸',\n          131: '栅', 132: '柳', 133: '柱', 134: '柿', 135: '栏', 136: '柈', 137: '柠', 138: '柁', 139: '枷', 140: '柽',\n          141: '树', 142: '勃', 143: '剌', 144: '郚', 145: '剅', 146: '要', 147: '酊', 148: '郦', 149: '柬', 150: '咸',\n          151: '威', 152: '歪', 153: '甭', 154: '研', 155: '砖', 156: '厘', 157: '砗', 158: '厚', 159: '砑', 160: '砘',\n          161: '砒', 162: '砌', 163: '砂', 164: '泵', 165: '砚', 166: '斫', 167: '砭', 168: '砜', 169: '砍', 170: '面',\n          171: '耐', 172: '耍', 173: '奎', 174: '耷', 175: '牵', 176: '鸥', 177: '虺', 178: '残', 179: '殂', 180: '殃',\n          181: '殇', 182: '殄', 183: '殆', 184: '轱', 185: '轲', 186: '轳', 187: '轴', 188: '轵', 189: '轶', 190: '轷',\n          191: '轸', 192: '轹', 193: '轺', 194: '轻', 195: '鸦', 196: '虿', 197: '皆', 198: '毖', 199: '韭', 200: '背',\n          201: '战', 202: '觇', 203: '点', 204: '虐', 205: '临', 206: '览', 207: '竖', 208: '尜', 209: '省', 210: '削',\n          211: '尝', 212: '哐', 213: '昧', 214: '眄', 215: '眍', 216: '盹', 217: '是', 218: '郢', 219: '眇', 220: '眊',\n          221: '盼', 222: '眨', 223: '昽', 224: '眈', 225: '哇', 226: '咭', 227: '哄', 228: '哑', 229: '显', 230: '冒',\n          231: '映', 232: '禺', 233: '哂', 234: '星', 235: '昨', 236: '咴', 237: '曷', 238: '昴', 239: '咧', 240: '昱',\n          241: '昵', 242: '咦', 243: '哓', 244: '昭', 245: '哔', 246: '畎', 247: '畏', 248: '毗', 249: '趴', 250: '呲',\n          251: '胄', 252: '胃', 253: '贵', 254: '畋', 255: '畈'},\n    137: {1: '界', 2: '虹', 3: '虾', 4: '虼', 5: '虻', 6: '蚁', 7: '思', 8: '蚂', 9: '盅', 10: '咣', 11: '虽', 12: '品',\n          13: '咽', 14: '骂', 15: '哕', 16: '剐', 17: '郧', 18: '勋', 19: '咻', 20: '哗', 21: '囿', 22: '咱', 23: '咿',\n          24: '响', 25: '哌', 26: '哙', 27: '哈', 28: '哚', 29: '咯', 30: '哆', 31: '咬', 32: '咳', 33: '咩', 34: '咪',\n          35: '咤', 36: '哝', 37: '哪', 38: '哏', 39: '哞', 40: '哟', 41: '峙', 42: '炭', 43: '峡', 44: '峣', 45: '罘',\n          46: '帧', 47: '罚', 48: '峒', 49: '峤', 50: '峋', 51: '峥', 52: '峧', 53: '帡', 54: '贱', 55: '贴', 56: '贶',\n          57: '贻', 58: '骨', 59: '幽', 60: '钘', 61: '钙', 62: '钚', 63: '钛', 64: '钝', 65: '钞', 66: '钟', 67: '钡',\n          68: '钠', 69: '钢', 70: '钣', 71: '钤', 72: '钥', 73: '钦', 74: '钧', 75: '钨', 76: '钩', 77: '钪', 78: '钫',\n          79: '钬', 80: '钭', 81: '钮', 82: '钯', 83: '卸', 84: '缸', 85: '拜', 86: '看', 87: '矩', 88: '矧', 89: '毡',\n          90: '氡', 91: '氟', 92: '氢', 93: '牯', 94: '怎', 95: '郜', 96: '牲', 97: '选', 98: '适', 99: '秕', 100: '秒',\n          101: '香', 102: '种', 103: '秭', 104: '秋', 105: '科', 106: '重', 107: '复', 108: '竽', 109: '竿', 110: '笈',\n          111: '笃', 112: '俦', 113: '段', 114: '俨', 115: '俅', 116: '便', 117: '俩', 118: '俪', 119: '叟', 120: '垡',\n          121: '贷', 122: '牮', 123: '顺', 124: '修', 125: '俏', 126: '俣', 127: '俚', 128: '保', 129: '俜', 130: '促',\n          131: '俄', 132: '俐', 133: '侮', 134: '俭', 135: '俗', 136: '俘', 137: '信', 138: '皇', 139: '泉', 140: '皈',\n          141: '鬼', 142: '侵', 143: '禹', 144: '侯', 145: '追', 146: '俑', 147: '俟', 148: '俊', 149: '盾', 150: '逅',\n          151: '待', 152: '徊', 153: '徇', 154: '徉', 155: '衍', 156: '律', 157: '很', 158: '须', 159: '舢', 160: '舣',\n          161: '叙', 162: '俞', 163: '弇', 164: '郗', 165: '剑', 166: '逃', 167: '俎', 168: '卻', 169: '爰', 170: '郛',\n          171: '食', 172: '瓴', 173: '盆', 174: '胚', 175: '胧', 176: '胨', 177: '胩', 178: '胪', 179: '胆', 180: '胛',\n          181: '胂', 182: '胜', 183: '胙', 184: '胍', 185: '胗', 186: '胝', 187: '朐', 188: '胞', 189: '胖', 190: '脉',\n          191: '胫', 192: '胎', 193: '鸨', 194: '匍', 195: '勉', 196: '狨', 197: '狭', 198: '狮', 199: '独', 200: '狯',\n          201: '狰', 202: '狡', 203: '飐', 204: '飑', 205: '狩', 206: '狱', 207: '狠', 208: '狲', 209: '訇', 210: '訄',\n          211: '逄', 212: '昝', 213: '贸', 214: '怨', 215: '急', 216: '饵', 217: '饶', 218: '蚀', 219: '饷', 220: '饸',\n          221: '饹', 222: '饺', 223: '饻', 224: '胤', 225: '饼', 226: '峦', 227: '弯', 228: '孪', 229: '娈', 230: '将',\n          231: '奖', 232: '哀', 233: '亭', 234: '亮', 235: '庤', 236: '度', 237: '弈', 238: '奕', 239: '迹', 240: '庭',\n          241: '庥', 242: '疬', 243: '疣', 244: '疥', 245: '疭', 246: '疮', 247: '疯', 248: '疫', 249: '疢', 250: '疤',\n          251: '庠', 252: '咨', 253: '姿', 254: '亲', 255: '竑'},\n    138: {1: '音', 2: '彦', 3: '飒', 4: '帝', 5: '施', 6: '闺', 7: '闻', 8: '闼', 9: '闽', 10: '闾', 11: '闿', 12: '阀',\n          13: '阁', 14: '阂', 15: '差', 16: '养', 17: '美', 18: '羑', 19: '姜', 20: '迸', 21: '叛', 22: '送', 23: '类',\n          24: '籼', 25: '迷', 26: '籽', 27: '娄', 28: '前', 29: '酋', 30: '首', 31: '逆', 32: '兹', 33: '总', 34: '炳',\n          35: '炻', 36: '炼', 37: '炟', 38: '炽', 39: '炯', 40: '炸', 41: '烀', 42: '烁', 43: '炮', 44: '炷', 45: '炫',\n          46: '烂', 47: '烃', 48: '剃', 49: '洼', 50: '洁', 51: '洱', 52: '洪', 53: '洹', 54: '洒', 55: '洧', 56: '洌',\n          57: '浃', 58: '柒', 59: '浇', 60: '泚', 61: '浈', 62: '浉', 63: '浊', 64: '洞', 65: '洇', 66: '洄', 67: '测',\n          68: '洙', 69: '洗', 70: '活', 71: '洑', 72: '涎', 73: '洎', 74: '洫', 75: '派', 76: '浍', 77: '洽', 78: '洮',\n          79: '染', 80: '洵', 81: '洚', 82: '洺', 83: '洛', 84: '浏', 85: '济', 86: '洨', 87: '浐', 88: '洋', 89: '洴',\n          90: '洣', 91: '洲', 92: '浑', 93: '浒', 94: '浓', 95: '津', 96: '浔', 97: '浕', 98: '洳', 99: '恸', 100: '恃',\n          101: '恒', 102: '恹', 103: '恢', 104: '恍', 105: '恫', 106: '恺', 107: '恻', 108: '恬', 109: '恤', 110: '恰',\n          111: '恂', 112: '恪', 113: '恼', 114: '恽', 115: '恨', 116: '举', 117: '觉', 118: '宣', 119: '宦', 120: '宥',\n          121: '宬', 122: '室', 123: '宫', 124: '宪', 125: '突', 126: '穿', 127: '窀', 128: '窃', 129: '客', 130: '诫',\n          131: '冠', 132: '诬', 133: '语', 134: '扁', 135: '扃', 136: '袆', 137: '衲', 138: '衽', 139: '袄', 140: '衿',\n          141: '袂', 142: '祛', 143: '祜', 144: '祓', 145: '祖', 146: '神', 147: '祝', 148: '祚', 149: '诮', 150: '祗',\n          151: '祢', 152: '祠', 153: '误', 154: '诰', 155: '诱', 156: '诲', 157: '诳', 158: '鸩', 159: '说', 160: '昶',\n          161: '诵', 162: '郡', 163: '垦', 164: '退', 165: '既', 166: '屋', 167: '昼', 168: '咫', 169: '屏', 170: '屎',\n          171: '弭', 172: '费', 173: '陡', 174: '逊', 175: '牁', 176: '眉', 177: '胥', 178: '孩', 179: '陛', 180: '陟',\n          181: '陧', 182: '陨', 183: '除', 184: '险', 185: '院', 186: '娃', 187: '姞', 188: '姥', 189: '娅', 190: '姨',\n          191: '娆', 192: '姻', 193: '姝', 194: '娇', 195: '姚', 196: '姽', 197: '姣', 198: '姘', 199: '姹', 200: '娜',\n          201: '怒', 202: '架', 203: '贺', 204: '盈', 205: '怼', 206: '羿', 207: '勇', 208: '炱', 209: '怠', 210: '癸',\n          211: '蚤', 212: '柔', 213: '矜', 214: '垒', 215: '绑', 216: '绒', 217: '结', 218: '绔', 219: '骁', 220: '绕',\n          221: '骄', 222: '骅', 223: '绗', 224: '绘', 225: '给', 226: '绚', 227: '彖', 228: '绛', 229: '络', 230: '骆',\n          231: '绝', 232: '绞', 233: '骇', 234: '统', 235: '骈', 236: '耕', 237: '耘', 238: '耖', 239: '耗', 240: '耙',\n          241: '艳', 242: '挈', 243: '恝', 244: '泰', 245: '秦', 246: '珥', 247: '珙', 248: '顼', 249: '珰', 250: '珠',\n          251: '珽', 252: '珩', 253: '珧', 254: '珣', 255: '珞'},\n    139: {1: '琤', 2: '班', 3: '珲', 4: '敖', 5: '素', 6: '匿', 7: '蚕', 8: '顽', 9: '盏', 10: '匪', 11: '恚', 12: '捞',\n          13: '栽', 14: '捕', 15: '埔', 16: '埂', 17: '捂', 18: '振', 19: '载', 20: '赶', 21: '起', 22: '盐', 23: '捎',\n          24: '捍', 25: '埕', 26: '捏', 27: '埘', 28: '埋', 29: '捉', 30: '捆', 31: '捐', 32: '埚', 33: '埙', 34: '损',\n          35: '袁', 36: '挹', 37: '捌', 38: '都', 39: '哲', 40: '逝', 41: '耆', 42: '耄', 43: '捡', 44: '挫', 45: '捋',\n          46: '埒', 47: '换', 48: '挽', 49: '贽', 50: '挚', 51: '热', 52: '恐', 53: '捣', 54: '垸', 55: '壶', 56: '捃',\n          57: '捅', 58: '盍', 59: '埃', 60: '挨', 61: '耻', 62: '耿', 63: '耽', 64: '聂', 65: '莰', 66: '茝', 67: '荸',\n          68: '莆', 69: '恭', 70: '莽', 71: '莱', 72: '莲', 73: '莳', 74: '莫', 75: '莴', 76: '莪', 77: '莉', 78: '莠',\n          79: '莓', 80: '荷', 81: '莜', 82: '莅', 83: '荼', 84: '莶', 85: '莩', 86: '荽', 87: '获', 88: '莸', 89: '荻',\n          90: '莘', 91: '晋', 92: '恶', 93: '莎', 94: '莞', 95: '莹', 96: '莨', 97: '莺', 98: '真', 99: '莙', 100: '鸪',\n          101: '莼', 102: '框', 103: '梆', 104: '桂', 105: '桔', 106: '栲', 107: '栳', 108: '郴', 109: '桓', 110: '栖',\n          111: '桡', 112: '桎', 113: '桢', 114: '桄', 115: '档', 116: '桐', 117: '桤', 118: '株', 119: '梃', 120: '栝',\n          121: '桥', 122: '桕', 123: '桦', 124: '桁', 125: '栓', 126: '桧', 127: '桃', 128: '桅', 129: '栒', 130: '格',\n          131: '桩', 132: '校', 133: '核', 134: '样', 135: '栟', 136: '桉', 137: '根', 138: '栩', 139: '逑', 140: '索',\n          141: '逋', 142: '彧', 143: '哥', 144: '速', 145: '鬲', 146: '豇', 147: '逗', 148: '栗', 149: '贾', 150: '酐',\n          151: '酎', 152: '酌', 153: '配', 154: '酏', 155: '逦', 156: '翅', 157: '辱', 158: '唇', 159: '厝', 160: '孬',\n          161: '夏', 162: '砝', 163: '砹', 164: '砸', 165: '砺', 166: '砰', 167: '砧', 168: '砷', 169: '砟', 170: '砼',\n          171: '砥', 172: '砾', 173: '砣', 174: '础', 175: '破', 176: '硁', 177: '恧', 178: '原', 179: '套', 180: '剞',\n          181: '逐', 182: '砻', 183: '烈', 184: '殊', 185: '殉', 186: '顾', 187: '轼', 188: '轾', 189: '轿', 190: '辀',\n          191: '辁', 192: '辂', 193: '较', 194: '鸫', 195: '顿', 196: '趸', 197: '毙', 198: '致', 199: '剕', 200: '龀',\n          201: '柴', 202: '桌', 203: '鸬', 204: '虔', 205: '虑', 206: '监', 207: '紧', 208: '逍', 209: '党', 210: '眬',\n          211: '唛', 212: '逞', 213: '晒', 214: '晟', 215: '眩', 216: '眠', 217: '晓', 218: '眙', 219: '唝', 220: '哧',\n          221: '哳', 222: '哮', 223: '唠', 224: '鸭', 225: '晃', 226: '哺', 227: '哽', 228: '唔', 229: '晔', 230: '晌',\n          231: '晁', 232: '剔', 233: '晏', 234: '晖', 235: '晕', 236: '鸮', 237: '趵', 238: '趿', 239: '畛', 240: '蚌',\n          241: '蚨', 242: '蚜', 243: '蚍', 244: '蚋', 245: '蚬', 246: '畔', 247: '蚝', 248: '蚧', 249: '蚣', 250: '蚊',\n          251: '蚪', 252: '蚓', 253: '哨', 254: '唢', 255: '哩'},\n    140: {1: '圃', 2: '哭', 3: '圄', 4: '哦', 5: '唣', 6: '唏', 7: '恩', 8: '盎', 9: '唑', 10: '鸯', 11: '唤', 12: '唁',\n          13: '哼', 14: '唧', 15: '啊', 16: '唉', 17: '唆', 18: '帱', 19: '崂', 20: '崃', 21: '罡', 22: '罢', 23: '罟',\n          24: '峭', 25: '峨', 26: '峪', 27: '峰', 28: '圆', 29: '觊', 30: '峻', 31: '贼', 32: '贿', 33: '赂', 34: '赃',\n          35: '赅', 36: '赆', 37: '钰', 38: '钱', 39: '钲', 40: '钳', 41: '钴', 42: '钵', 43: '钷', 44: '钹', 45: '钺',\n          46: '钻', 47: '钼', 48: '钽', 49: '钾', 50: '钿', 51: '铀', 52: '铁', 53: '铂', 54: '铃', 55: '铄', 56: '铅',\n          57: '铆', 58: '铈', 59: '铉', 60: '铊', 61: '铋', 62: '铌', 63: '铍', 64: '铎', 65: '眚', 66: '缺', 67: '氩',\n          68: '氤', 69: '氦', 70: '氧', 71: '氨', 72: '毪', 73: '特', 74: '牺', 75: '造', 76: '乘', 77: '敌', 78: '舐',\n          79: '秣', 80: '秫', 81: '秤', 82: '租', 83: '秧', 84: '积', 85: '盉', 86: '秩', 87: '称', 88: '秘', 89: '透',\n          90: '笄', 91: '笕', 92: '笔', 93: '笑', 94: '笊', 95: '笫', 96: '笏', 97: '笋', 98: '笆', 99: '俸', 100: '倩',\n          101: '债', 102: '俵', 103: '倻', 104: '借', 105: '偌', 106: '值', 107: '倚', 108: '俺', 109: '倾', 110: '倒',\n          111: '俳', 112: '俶', 113: '倬', 114: '倏', 115: '倘', 116: '俱', 117: '倡', 118: '候', 119: '赁', 120: '恁',\n          121: '倭', 122: '倪', 123: '俾', 124: '倜', 125: '隼', 126: '隽', 127: '倞', 128: '俯', 129: '倍', 130: '倦',\n          131: '倓', 132: '倌', 133: '倥', 134: '臬', 135: '健', 136: '臭', 137: '射', 138: '皋', 139: '躬', 140: '息',\n          141: '郫', 142: '倨', 143: '倔', 144: '衄', 145: '颀', 146: '徒', 147: '徕', 148: '徐', 149: '殷', 150: '舰',\n          151: '舨', 152: '舱', 153: '般', 154: '航', 155: '舫', 156: '瓞', 157: '途', 158: '拿', 159: '釜', 160: '耸',\n          161: '爹', 162: '舀', 163: '爱', 164: '豺', 165: '豹', 166: '奚', 167: '鬯', 168: '衾', 169: '鸰', 170: '颁',\n          171: '颂', 172: '翁', 173: '胯', 174: '胰', 175: '胱', 176: '胴', 177: '胭', 178: '脍', 179: '脎', 180: '脆',\n          181: '脂', 182: '胸', 183: '胳', 184: '脏', 185: '脐', 186: '胶', 187: '脑', 188: '胲', 189: '胼', 190: '朕',\n          191: '脒', 192: '胺', 193: '脓', 194: '鸱', 195: '玺', 196: '鱽', 197: '鸲', 198: '逛', 199: '狴', 200: '狸',\n          201: '狷', 202: '猁', 203: '狳', 204: '猃', 205: '狺', 206: '逖', 207: '狼', 208: '卿', 209: '狻', 210: '逢',\n          211: '桀', 212: '鸵', 213: '留', 214: '袅', 215: '眢', 216: '鸳', 217: '皱', 218: '饽', 219: '饿', 220: '馀',\n          221: '馁', 222: '凌', 223: '凇', 224: '凄', 225: '栾', 226: '挛', 227: '恋', 228: '桨', 229: '浆', 230: '衰',\n          231: '勍', 232: '衷', 233: '高', 234: '亳', 235: '郭', 236: '席', 237: '准', 238: '座', 239: '脊', 240: '症',\n          241: '疳', 242: '疴', 243: '病', 244: '疽', 245: '疸', 246: '疾', 247: '痄', 248: '斋', 249: '疹', 250: '痈',\n          251: '疼', 252: '疱', 253: '疰', 254: '痃', 255: '痂'},\n    141: {1: '疲', 2: '痉', 3: '效', 4: '离', 5: '衮', 6: '紊', 7: '唐', 8: '凋', 9: '颃', 10: '瓷', 11: '资', 12: '恣',\n          13: '凉', 14: '站', 15: '剖', 16: '竞', 17: '部', 18: '旁', 19: '旆', 20: '旄', 21: '旅', 22: '旃', 23: '畜',\n          24: '阃', 25: '阄', 26: '阅', 27: '阆', 28: '羞', 29: '羔', 30: '恙', 31: '瓶', 32: '桊', 33: '拳', 34: '敉',\n          35: '粉', 36: '料', 37: '粑', 38: '益', 39: '兼', 40: '朔', 41: '郸', 42: '烤', 43: '烘', 44: '烜', 45: '烦',\n          46: '烧', 47: '烛', 48: '烟', 49: '烨', 50: '烩', 51: '烙', 52: '烊', 53: '剡', 54: '郯', 55: '烬', 56: '递',\n          57: '涛', 58: '浙', 59: '涝', 60: '浡', 61: '浦', 62: '涑', 63: '浯', 64: '酒', 65: '涞', 66: '涟', 67: '涉',\n          68: '娑', 69: '消', 70: '涅', 71: '涠', 72: '浞', 73: '涓', 74: '涢', 75: '涡', 76: '浥', 77: '涔', 78: '浩',\n          79: '海', 80: '浜', 81: '涂', 82: '浠', 83: '浴', 84: '浮', 85: '涣', 86: '浼', 87: '涤', 88: '流', 89: '润',\n          90: '涧', 91: '涕', 92: '浣', 93: '浪', 94: '浸', 95: '涨', 96: '烫', 97: '涩', 98: '涌', 99: '涘', 100: '浚',\n          101: '悖', 102: '悚', 103: '悟', 104: '悭', 105: '悄', 106: '悍', 107: '悝', 108: '悃', 109: '悒', 110: '悔',\n          111: '悯', 112: '悦', 113: '悌', 114: '悢', 115: '悛', 116: '害', 117: '宽', 118: '宸', 119: '家', 120: '宵',\n          121: '宴', 122: '宾', 123: '窍', 124: '窅', 125: '窄', 126: '容', 127: '窈', 128: '剜', 129: '宰', 130: '案',\n          131: '请', 132: '朗', 133: '诸', 134: '诹', 135: '诺', 136: '读', 137: '扅', 138: '诼', 139: '冢', 140: '扇',\n          141: '诽', 142: '袜', 143: '袪', 144: '袒', 145: '袖', 146: '袗', 147: '袍', 148: '袢', 149: '被', 150: '袯',\n          151: '祯', 152: '祧', 153: '祥', 154: '课', 155: '冥', 156: '诿', 157: '谀', 158: '谁', 159: '谂', 160: '调',\n          161: '冤', 162: '谄', 163: '谅', 164: '谆', 165: '谇', 166: '谈', 167: '谊', 168: '剥', 169: '恳', 170: '展',\n          171: '剧', 172: '屑', 173: '屐', 174: '屙', 175: '弱', 176: '陵', 177: '陬', 178: '勐', 179: '奘', 180: '疍',\n          181: '牂', 182: '蚩', 183: '祟', 184: '陲', 185: '陴', 186: '陶', 187: '陷', 188: '陪', 189: '烝', 190: '姬',\n          191: '娠', 192: '娱', 193: '娌', 194: '娉', 195: '娟', 196: '娲', 197: '恕', 198: '娥', 199: '娩', 200: '娴',\n          201: '娣', 202: '娘', 203: '娓', 204: '婀', 205: '砮', 206: '哿', 207: '畚', 208: '通', 209: '能', 210: '难',\n          211: '逡', 212: '预', 213: '桑', 214: '剟', 215: '绠', 216: '骊', 217: '绡', 218: '骋', 219: '绢', 220: '绣',\n          221: '验', 222: '绤', 223: '绥', 224: '绦', 225: '骍', 226: '继', 227: '绨', 228: '骎', 229: '骏', 230: '邕',\n          231: '鸶', 232: '彗', 233: '耜', 234: '焘', 235: '舂', 236: '琎', 237: '球', 238: '琏', 239: '琐', 240: '理',\n          241: '琇', 242: '麸', 243: '琉', 244: '琅', 245: '捧', 246: '掭', 247: '堵', 248: '揶', 249: '措', 250: '描',\n          251: '埴', 252: '域', 253: '捺', 254: '掎', 255: '埼'},\n    142: {1: '掩', 2: '埯', 3: '捷', 4: '捯', 5: '排', 6: '焉', 7: '掉', 8: '掳', 9: '掴', 10: '埸', 11: '堌', 12: '捶',\n          13: '赦', 14: '赧', 15: '推', 16: '堆', 17: '捭', 18: '埠', 19: '晢', 20: '掀', 21: '逵', 22: '授', 23: '捻',\n          24: '埝', 25: '堋', 26: '教', 27: '堍', 28: '掏', 29: '掐', 30: '掬', 31: '鸷', 32: '掠', 33: '掂', 34: '掖',\n          35: '培', 36: '掊', 37: '接', 38: '堉', 39: '掷', 40: '掸', 41: '控', 42: '捩', 43: '掮', 44: '探', 45: '悫',\n          46: '埭', 47: '埽', 48: '据', 49: '掘', 50: '掺', 51: '掇', 52: '掼', 53: '职', 54: '聃', 55: '基', 56: '聆',\n          57: '勘', 58: '聊', 59: '聍', 60: '娶', 61: '菁', 62: '菝', 63: '著', 64: '菱', 65: '萁', 66: '菥', 67: '菘',\n          68: '堇', 69: '勒', 70: '黄', 71: '萘', 72: '萋', 73: '勩', 74: '菲', 75: '菽', 76: '菖', 77: '萌', 78: '萜',\n          79: '萝', 80: '菌', 81: '萎', 82: '萸', 83: '萑', 84: '菂', 85: '菜', 86: '棻', 87: '菔', 88: '菟', 89: '萄',\n          90: '萏', 91: '菊', 92: '萃', 93: '菩', 94: '菼', 95: '菏', 96: '萍', 97: '菹', 98: '菠', 99: '菪', 100: '菅',\n          101: '菀', 102: '萤', 103: '营', 104: '萦', 105: '乾', 106: '萧', 107: '菰', 108: '菡', 109: '萨', 110: '菇',\n          111: '械', 112: '梽', 113: '彬', 114: '梵', 115: '梦', 116: '婪', 117: '梗', 118: '梧', 119: '梾', 120: '梢',\n          121: '梏', 122: '梅', 123: '觋', 124: '检', 125: '桴', 126: '桷', 127: '梓', 128: '梳', 129: '棁', 130: '梯',\n          131: '桫', 132: '棂', 133: '桶', 134: '梭', 135: '救', 136: '啬', 137: '郾', 138: '匮', 139: '曹', 140: '敕',\n          141: '副', 142: '豉', 143: '票', 144: '鄄', 145: '酝', 146: '酞', 147: '酗', 148: '酚', 149: '厢', 150: '厣',\n          151: '戚', 152: '戛', 153: '硎', 154: '硅', 155: '硭', 156: '硒', 157: '硕', 158: '硖', 159: '硗', 160: '硐',\n          161: '硚', 162: '硇', 163: '硌', 164: '鸸', 165: '瓠', 166: '匏', 167: '奢', 168: '盔', 169: '爽', 170: '厩',\n          171: '聋', 172: '龚', 173: '袭', 174: '殒', 175: '殓', 176: '殍', 177: '盛', 178: '赉', 179: '匾', 180: '雩',\n          181: '雪', 182: '辄', 183: '辅', 184: '辆', 185: '堑', 186: '龁', 187: '颅', 188: '虚', 189: '彪', 190: '雀',\n          191: '堂', 192: '常', 193: '眶', 194: '眭', 195: '唪', 196: '眦', 197: '啧', 198: '匙', 199: '晡', 200: '晤',\n          201: '晨', 202: '眺', 203: '眵', 204: '睁', 205: '眯', 206: '眼', 207: '眸', 208: '悬', 209: '野', 210: '圊',\n          211: '啪', 212: '啦', 213: '喏', 214: '喵', 215: '啉', 216: '勖', 217: '曼', 218: '晦', 219: '晞', 220: '晗',\n          221: '晚', 222: '冕', 223: '啄', 224: '啭', 225: '啡', 226: '畦', 227: '趼', 228: '趺', 229: '距', 230: '趾',\n          231: '啃', 232: '跃', 233: '啮', 234: '跄', 235: '略', 236: '蚶', 237: '蛄', 238: '蛎', 239: '蛆', 240: '蚰',\n          241: '蚺', 242: '蛊', 243: '圉', 244: '蚱', 245: '蚯', 246: '蛉', 247: '蛀', 248: '蛇', 249: '蛏', 250: '蚴',\n          251: '唬', 252: '累', 253: '鄂', 254: '唱', 255: '患'},\n    143: {1: '啰', 2: '唾', 3: '唯', 4: '啤', 5: '啥', 6: '啁', 7: '啕', 8: '唿', 9: '啐', 10: '唼', 11: '唷', 12: '啴',\n          13: '啖', 14: '啵', 15: '啶', 16: '啷', 17: '唳', 18: '啸', 19: '啜', 20: '帻', 21: '崖', 22: '崎', 23: '崦',\n          24: '崭', 25: '逻', 26: '帼', 27: '崮', 28: '崔', 29: '帷', 30: '崟', 31: '崤', 32: '崩', 33: '崞', 34: '崇',\n          35: '崆', 36: '崛', 37: '赇', 38: '赈', 39: '婴', 40: '赊', 41: '圈', 42: '铐', 43: '铑', 44: '铒', 45: '铕',\n          46: '铗', 47: '铘', 48: '铙', 49: '铚', 50: '铛', 51: '铜', 52: '铝', 53: '铞', 54: '铟', 55: '铠', 56: '铡',\n          57: '铢', 58: '铣', 59: '铤', 60: '铥', 61: '铧', 62: '铨', 63: '铩', 64: '铪', 65: '铫', 66: '铭', 67: '铬',\n          68: '铮', 69: '铯', 70: '铰', 71: '铱', 72: '铲', 73: '铳', 74: '铴', 75: '铵', 76: '银', 77: '铷', 78: '矫',\n          79: '氪', 80: '牾', 81: '甜', 82: '鸹', 83: '秸', 84: '梨', 85: '犁', 86: '稆', 87: '秽', 88: '移', 89: '秾',\n          90: '逶', 91: '笺', 92: '筇', 93: '笨', 94: '笸', 95: '笼', 96: '笪', 97: '笛', 98: '笙', 99: '笮', 100: '符',\n          101: '笱', 102: '笠', 103: '笥', 104: '第', 105: '笳', 106: '笤', 107: '笾', 108: '笞', 109: '敏', 110: '偾',\n          111: '做', 112: '鸺', 113: '偃', 114: '偕', 115: '袋', 116: '悠', 117: '偿', 118: '偶', 119: '偈', 120: '偎',\n          121: '偲', 122: '傀', 123: '偷', 124: '您', 125: '偬', 126: '售', 127: '停', 128: '偻', 129: '偏', 130: '躯',\n          131: '皑', 132: '兜', 133: '皎', 134: '假', 135: '衅', 136: '鸻', 137: '徘', 138: '徙', 139: '徜', 140: '得',\n          141: '衔', 142: '舸', 143: '舻', 144: '舳', 145: '盘', 146: '舴', 147: '舶', 148: '船', 149: '鸼', 150: '舷',\n          151: '舵', 152: '斜', 153: '龛', 154: '盒', 155: '鸽', 156: '瓻', 157: '敛', 158: '悉', 159: '欲', 160: '彩',\n          161: '领', 162: '翎', 163: '脚', 164: '脖', 165: '脯', 166: '豚', 167: '脶', 168: '脸', 169: '脞', 170: '脬',\n          171: '脱', 172: '脘', 173: '脲', 174: '脧', 175: '匐', 176: '鱾', 177: '象', 178: '够', 179: '逸', 180: '猜',\n          181: '猪', 182: '猎', 183: '猫', 184: '猗', 185: '凰', 186: '猖', 187: '猡', 188: '猊', 189: '猞', 190: '猄',\n          191: '猝', 192: '斛', 193: '觖', 194: '猕', 195: '猛', 196: '馗', 197: '祭', 198: '馃', 199: '馄', 200: '馅',\n          201: '馆', 202: '凑', 203: '减', 204: '鸾', 205: '毫', 206: '孰', 207: '烹', 208: '庶', 209: '庹', 210: '麻',\n          211: '庵', 212: '庼', 213: '庾', 214: '庳', 215: '痔', 216: '痍', 217: '疵', 218: '痊', 219: '痒', 220: '痕',\n          221: '廊', 222: '康', 223: '庸', 224: '鹿', 225: '盗', 226: '章', 227: '竟', 228: '翊', 229: '商', 230: '旌',\n          231: '族', 232: '旎', 233: '旋', 234: '望', 235: '袤', 236: '率', 237: '阇', 238: '阈', 239: '阉', 240: '阊',\n          241: '阋', 242: '阌', 243: '阍', 244: '阎', 245: '阏', 246: '阐', 247: '着', 248: '羚', 249: '羝', 250: '羟',\n          251: '盖', 252: '眷', 253: '粝', 254: '粘', 255: '粗'},\n    144: {1: '粕', 2: '粒', 3: '断', 4: '剪', 5: '兽', 6: '焐', 7: '焊', 8: '烯', 9: '焓', 10: '焕', 11: '烽', 12: '焖',\n          13: '烷', 14: '烺', 15: '焌', 16: '清', 17: '渍', 18: '添', 19: '渚', 20: '鸿', 21: '淇', 22: '淋', 23: '淅',\n          24: '淞', 25: '渎', 26: '涯', 27: '淹', 28: '涿', 29: '渠', 30: '渐', 31: '淑', 32: '淖', 33: '挲', 34: '淌',\n          35: '淏', 36: '混', 37: '淠', 38: '涸', 39: '渑', 40: '淮', 41: '淦', 42: '淆', 43: '渊', 44: '淫', 45: '淝',\n          46: '渔', 47: '淘', 48: '淳', 49: '液', 50: '淬', 51: '涪', 52: '淤', 53: '淡', 54: '淙', 55: '淀', 56: '涫',\n          57: '深', 58: '渌', 59: '涮', 60: '涵', 61: '婆', 62: '梁', 63: '渗', 64: '淄', 65: '情', 66: '惬', 67: '悻',\n          68: '惜', 69: '惭', 70: '悱', 71: '悼', 72: '惝', 73: '惧', 74: '惕', 75: '惘', 76: '悸', 77: '惟', 78: '惆',\n          79: '惚', 80: '惊', 81: '惇', 82: '惦', 83: '悴', 84: '惮', 85: '惋', 86: '惨', 87: '惯', 88: '寇', 89: '寅',\n          90: '寄', 91: '寂', 92: '逭', 93: '宿', 94: '窒', 95: '窑', 96: '窕', 97: '密', 98: '谋', 99: '谌', 100: '谍',\n          101: '谎', 102: '谏', 103: '扈', 104: '皲', 105: '谐', 106: '谑', 107: '裆', 108: '袱', 109: '袼', 110: '裈',\n          111: '裉', 112: '祷', 113: '祸', 114: '祲', 115: '谒', 116: '谓', 117: '谔', 118: '谕', 119: '谖', 120: '谗',\n          121: '谙', 122: '谚', 123: '谛', 124: '谜', 125: '谝', 126: '敝', 127: '逮', 128: '逯', 129: '敢', 130: '尉',\n          131: '屠', 132: '艴', 133: '弹', 134: '隋', 135: '堕', 136: '郿', 137: '随', 138: '蛋', 139: '隅', 140: '隈',\n          141: '粜', 142: '隍', 143: '隗', 144: '隆', 145: '隐', 146: '婧', 147: '婊', 148: '婞', 149: '婳', 150: '婕',\n          151: '娼', 152: '婢', 153: '婚', 154: '婵', 155: '婶', 156: '婉', 157: '胬', 158: '袈', 159: '颇', 160: '颈',\n          161: '翌', 162: '恿', 163: '欸', 164: '绩', 165: '绪', 166: '绫', 167: '骐', 168: '续', 169: '骑', 170: '绮',\n          171: '绯', 172: '绰', 173: '骒', 174: '绲', 175: '绳', 176: '骓', 177: '维', 178: '绵', 179: '绶', 180: '绷',\n          181: '绸', 182: '绹', 183: '绺', 184: '绻', 185: '综', 186: '绽', 187: '绾', 188: '绿', 189: '骖', 190: '缀',\n          191: '缁', 192: '巢', 193: '耠', 194: '琫', 195: '琵', 196: '琴', 197: '琶', 198: '琪', 199: '瑛', 200: '琳',\n          201: '琦', 202: '琢', 203: '琥', 204: '琨', 205: '靓', 206: '琼', 207: '斑', 208: '琰', 209: '琮', 210: '琯',\n          211: '琬', 212: '琛', 213: '琚', 214: '辇', 215: '替', 216: '鼋', 217: '揳', 218: '揍', 219: '款', 220: '堪',\n          221: '堞', 222: '搽', 223: '塔', 224: '搭', 225: '塃', 226: '揸', 227: '堰', 228: '揠', 229: '堙', 230: '揩',\n          231: '越', 232: '趄', 233: '趁', 234: '趋', 235: '超', 236: '揽', 237: '提', 238: '堤', 239: '揖', 240: '博',\n          241: '揾', 242: '颉', 243: '揭', 244: '喜', 245: '彭', 246: '揣', 247: '塄', 248: '揿', 249: '插', 250: '揪',\n          251: '搜', 252: '煮', 253: '堠', 254: '耋', 255: '揄'},\n    145: {1: '援', 2: '搀', 3: '蛰', 4: '蛩', 5: '絷', 6: '塆', 7: '裁', 8: '揞', 9: '搁', 10: '搓', 11: '搂', 12: '搅',\n          13: '揎', 14: '壹', 15: '握', 16: '摒', 17: '揆', 18: '搔', 19: '揉', 20: '掾', 21: '葜', 22: '聒', 23: '斯',\n          24: '期', 25: '欺', 26: '联', 27: '葑', 28: '葚', 29: '葫', 30: '靰', 31: '靸', 32: '散', 33: '葳', 34: '惹',\n          35: '蒇', 36: '葬', 37: '蒈', 38: '募', 39: '葺', 40: '葛', 41: '蒉', 42: '葸', 43: '萼', 44: '蓇', 45: '萩',\n          46: '董', 47: '葆', 48: '葩', 49: '葡', 50: '敬', 51: '葱', 52: '蒋', 53: '葶', 54: '蒂', 55: '蒌', 56: '葓',\n          57: '蒎', 58: '落', 59: '萱', 60: '葖', 61: '韩', 62: '戟', 63: '朝', 64: '葭', 65: '辜', 66: '葵', 67: '棒',\n          68: '楮', 69: '棱', 70: '棋', 71: '椰', 72: '植', 73: '森', 74: '棼', 75: '焚', 76: '椟', 77: '椅', 78: '椒',\n          79: '棹', 80: '棵', 81: '棍', 82: '椤', 83: '棰', 84: '椎', 85: '棉', 86: '椑', 87: '鹀', 88: '赍', 89: '棚',\n          90: '椋', 91: '椁', 92: '棬', 93: '棕', 94: '棺', 95: '榔', 96: '楗', 97: '棣', 98: '椐', 99: '椭', 100: '鹁',\n          101: '惠', 102: '惑', 103: '逼', 104: '覃', 105: '粟', 106: '棘', 107: '酣', 108: '酤', 109: '酢', 110: '酥',\n          111: '酡', 112: '酦', 113: '鹂', 114: '觌', 115: '厨', 116: '厦', 117: '硬', 118: '硝', 119: '硪', 120: '硷',\n          121: '确', 122: '硫', 123: '雁', 124: '厥', 125: '殖', 126: '裂', 127: '雄', 128: '殚', 129: '殛', 130: '颊',\n          131: '雳', 132: '雯', 133: '辊', 134: '辋', 135: '椠', 136: '暂', 137: '辌', 138: '辍', 139: '辎', 140: '雅',\n          141: '翘', 142: '辈', 143: '斐', 144: '悲', 145: '紫', 146: '黹', 147: '辉', 148: '敞', 149: '棠', 150: '牚',\n          151: '赏', 152: '掌', 153: '晴', 154: '睐', 155: '暑', 156: '最', 157: '晰', 158: '量', 159: '睑', 160: '睇',\n          161: '鼎', 162: '睃', 163: '喷', 164: '戢', 165: '喋', 166: '嗒', 167: '喃', 168: '喳', 169: '晶', 170: '喇',\n          171: '遇', 172: '喊', 173: '喱', 174: '喹', 175: '遏', 176: '晷', 177: '晾', 178: '景', 179: '喈', 180: '畴',\n          181: '践', 182: '跖', 183: '跋', 184: '跌', 185: '跗', 186: '跞', 187: '跚', 188: '跑', 189: '跎', 190: '跏',\n          191: '跛', 192: '跆', 193: '遗', 194: '蛙', 195: '蛱', 196: '蛲', 197: '蛭', 198: '蛳', 199: '蛐', 200: '蛔',\n          201: '蛛', 202: '蜓', 203: '蛞', 204: '蜒', 205: '蛤', 206: '蛴', 207: '蛟', 208: '蛘', 209: '蛑', 210: '畯',\n          211: '喁', 212: '喝', 213: '鹃', 214: '喂', 215: '喟', 216: '斝', 217: '喘', 218: '啾', 219: '嗖', 220: '喤',\n          221: '喉', 222: '喻', 223: '喑', 224: '啼', 225: '嗟', 226: '喽', 227: '嗞', 228: '喧', 229: '喀', 230: '喔',\n          231: '喙', 232: '嵌', 233: '嵘', 234: '嵖', 235: '幅', 236: '崴', 237: '遄', 238: '詈', 239: '帽', 240: '嵎',\n          241: '崽', 242: '嵚', 243: '嵬', 244: '嵛', 245: '翙', 246: '嵯', 247: '嵝', 248: '嵫', 249: '幄', 250: '嵋',\n          251: '赋', 252: '赌', 253: '赎', 254: '赐', 255: '赑'},\n    146: {1: '赔', 2: '黑', 3: '铸', 4: '铹', 5: '铺', 6: '铻', 7: '铼', 8: '铽', 9: '链', 10: '铿', 11: '销', 12: '锁',\n          13: '锃', 14: '锄', 15: '锂', 16: '锅', 17: '锆', 18: '锇', 19: '锈', 20: '锉', 21: '锊', 22: '锋', 23: '锌',\n          24: '锎', 25: '锏', 26: '锐', 27: '锑', 28: '锒', 29: '锓', 30: '锔', 31: '锕', 32: '甥', 33: '掣', 34: '掰',\n          35: '短', 36: '智', 37: '矬', 38: '氰', 39: '毳', 40: '毯', 41: '氮', 42: '毽', 43: '氯', 44: '犊', 45: '犄',\n          46: '犋', 47: '鹄', 48: '犍', 49: '鹅', 50: '颋', 51: '剩', 52: '嵇', 53: '稍', 54: '程', 55: '稀', 56: '黍',\n          57: '稃', 58: '税', 59: '稂', 60: '筐', 61: '等', 62: '筘', 63: '筑', 64: '策', 65: '筚', 66: '筛', 67: '筜',\n          68: '筒', 69: '筅', 70: '筏', 71: '筵', 72: '筌', 73: '答', 74: '筋', 75: '筝', 76: '傣', 77: '傲', 78: '傅',\n          79: '傈', 80: '舄', 81: '牍', 82: '牌', 83: '傥', 84: '堡', 85: '集', 86: '焦', 87: '傍', 88: '傧', 89: '储',\n          90: '遑', 91: '皓', 92: '皖', 93: '粤', 94: '奥', 95: '傩', 96: '遁', 97: '街', 98: '惩', 99: '御', 100: '徨',\n          101: '循', 102: '舾', 103: '艇', 104: '舒', 105: '畲', 106: '弑', 107: '逾', 108: '颌', 109: '翕', 110: '釉',\n          111: '番', 112: '释', 113: '鹆', 114: '禽', 115: '舜', 116: '貂', 117: '腈', 118: '腊', 119: '腌', 120: '腓',\n          121: '腆', 122: '腴', 123: '脾', 124: '腋', 125: '腑', 126: '腙', 127: '腚', 128: '腔', 129: '腕', 130: '腱',\n          131: '腒', 132: '鱿', 133: '鲀', 134: '鲁', 135: '鲂', 136: '鲃', 137: '颍', 138: '猢', 139: '猹', 140: '猩',\n          141: '猥', 142: '猬', 143: '猾', 144: '猴', 145: '飓', 146: '觞', 147: '觚', 148: '猸', 149: '猱', 150: '惫',\n          151: '飧', 152: '然', 153: '馇', 154: '馈', 155: '馉', 156: '馊', 157: '馋', 158: '亵', 159: '装', 160: '蛮',\n          161: '脔', 162: '就', 163: '敦', 164: '裒', 165: '廋', 166: '斌', 167: '痣', 168: '痨', 169: '痦', 170: '痘',\n          171: '痞', 172: '痢', 173: '痤', 174: '痪', 175: '痫', 176: '痧', 177: '痛', 178: '鄌', 179: '赓', 180: '竦',\n          181: '童', 182: '瓿', 183: '竣', 184: '啻', 185: '颏', 186: '鹇', 187: '阑', 188: '阒', 189: '阔', 190: '阕',\n          191: '善', 192: '翔', 193: '羡', 194: '普', 195: '粪', 196: '粞', 197: '尊', 198: '奠', 199: '遒', 200: '道',\n          201: '遂', 202: '孳', 203: '曾', 204: '焯', 205: '焜', 206: '焰', 207: '焙', 208: '焱', 209: '鹈', 210: '湛',\n          211: '港', 212: '渫', 213: '滞', 214: '湖', 215: '湘', 216: '渣', 217: '渤', 218: '湮', 219: '湎', 220: '湝',\n          221: '湨', 222: '湜', 223: '渺', 224: '湿', 225: '温', 226: '渴', 227: '渭', 228: '溃', 229: '湍', 230: '溅',\n          231: '滑', 232: '湃', 233: '湫', 234: '溲', 235: '湟', 236: '溆', 237: '渝', 238: '湲', 239: '湾', 240: '渡',\n          241: '游', 242: '溠', 243: '溇', 244: '湔', 245: '滋', 246: '湉', 247: '渲', 248: '溉', 249: '渥', 250: '湄',\n          251: '滁', 252: '愤', 253: '慌', 254: '惰', 255: '愠'},\n    147: {1: '惺', 2: '愦', 3: '愕', 4: '惴', 5: '愣', 6: '愀', 7: '愎', 8: '惶', 9: '愧', 10: '愉', 11: '愔', 12: '慨',\n          13: '喾', 14: '割', 15: '寒', 16: '富', 17: '寓', 18: '窜', 19: '窝', 20: '窖', 21: '窗', 22: '窘', 23: '寐',\n          24: '谟', 25: '扉', 26: '遍', 27: '棨', 28: '雇', 29: '扊', 30: '裢', 31: '裎', 32: '裣', 33: '裕', 34: '裤',\n          35: '裥', 36: '裙', 37: '祾', 38: '祺', 39: '祼', 40: '谠', 41: '禅', 42: '禄', 43: '幂', 44: '谡', 45: '谢',\n          46: '谣', 47: '谤', 48: '谥', 49: '谦', 50: '谧', 51: '塈', 52: '遐', 53: '犀', 54: '属', 55: '屡', 56: '孱',\n          57: '弼', 58: '强', 59: '粥', 60: '巽', 61: '疏', 62: '隔', 63: '骘', 64: '隙', 65: '隘', 66: '媒', 67: '媪',\n          68: '絮', 69: '嫂', 70: '媛', 71: '婷', 72: '媚', 73: '婿', 74: '巯', 75: '毵', 76: '翚', 77: '登', 78: '皴',\n          79: '婺', 80: '骛', 81: '缂', 82: '缃', 83: '缄', 84: '缅', 85: '彘', 86: '缆', 87: '缇', 88: '缈', 89: '缉',\n          90: '缌', 91: '缎', 92: '缏', 93: '缑', 94: '缒', 95: '缓', 96: '缔', 97: '缕', 98: '骗', 99: '编', 100: '缗',\n          101: '骙', 102: '骚', 103: '缘', 104: '飨', 105: '耢', 106: '瑟', 107: '瑚', 108: '鹉', 109: '瑁', 110: '瑞',\n          111: '瑰', 112: '瑀', 113: '瑜', 114: '瑗', 115: '瑄', 116: '瑕', 117: '遨', 118: '骜', 119: '瑙', 120: '遘',\n          121: '韫', 122: '魂', 123: '髡', 124: '肆', 125: '摄', 126: '摸', 127: '填', 128: '搏', 129: '塥', 130: '塬',\n          131: '鄢', 132: '趔', 133: '趑', 134: '摅', 135: '塌', 136: '摁', 137: '鼓', 138: '摆', 139: '赪', 140: '携',\n          141: '塮', 142: '蜇', 143: '搋', 144: '搬', 145: '摇', 146: '搞', 147: '搪', 148: '塘', 149: '搒', 150: '搐',\n          151: '搛', 152: '搠', 153: '摈', 154: '彀', 155: '毂', 156: '搌', 157: '搦', 158: '摊', 159: '搡', 160: '聘',\n          161: '蓁', 162: '戡', 163: '斟', 164: '蒜', 165: '蓍', 166: '鄞', 167: '勤', 168: '靴', 169: '靳', 170: '靶',\n          171: '鹊', 172: '蓐', 173: '蓝', 174: '墓', 175: '幕', 176: '蓦', 177: '鹋', 178: '蒽', 179: '蓓', 180: '蓖',\n          181: '蓊', 182: '蒯', 183: '蓟', 184: '蓬', 185: '蓑', 186: '蒿', 187: '蒺', 188: '蓠', 189: '蒟', 190: '蒡',\n          191: '蓄', 192: '蒹', 193: '蒴', 194: '蒲', 195: '蒗', 196: '蓉', 197: '蒙', 198: '蓂', 199: '蓥', 200: '颐',\n          201: '蒸', 202: '献', 203: '蓣', 204: '楔', 205: '椿', 206: '楠', 207: '禁', 208: '楂', 209: '楚', 210: '楝',\n          211: '楷', 212: '榄', 213: '想', 214: '楫', 215: '榀', 216: '楞', 217: '楸', 218: '椴', 219: '槐', 220: '槌',\n          221: '楯', 222: '榆', 223: '榇', 224: '榈', 225: '槎', 226: '楼', 227: '榉', 228: '楦', 229: '概', 230: '楣',\n          231: '楹', 232: '椽', 233: '裘', 234: '赖', 235: '剽', 236: '甄', 237: '酮', 238: '酰', 239: '酯', 240: '酪',\n          241: '酩', 242: '酬', 243: '蜃', 244: '感', 245: '碛', 246: '碍', 247: '碘', 248: '碓', 249: '碑', 250: '硼',\n          251: '碉', 252: '碎', 253: '碚', 254: '碰', 255: '碇'},\n    148: {1: '碗', 2: '碌', 3: '碜', 4: '鹌', 5: '尴', 6: '雷', 7: '零', 8: '雾', 9: '雹', 10: '辏', 11: '辐', 12: '辑',\n          13: '辒', 14: '输', 15: '督', 16: '频', 17: '龃', 18: '龄', 19: '龅', 20: '龆', 21: '觜', 22: '訾', 23: '粲',\n          24: '虞', 25: '鉴', 26: '睛', 27: '睹', 28: '睦', 29: '瞄', 30: '睚', 31: '嗪', 32: '睫', 33: '韪', 34: '嗷',\n          35: '嗉', 36: '睡', 37: '睨', 38: '睢', 39: '雎', 40: '睥', 41: '睬', 42: '嘟', 43: '嗜', 44: '嗑', 45: '嗫',\n          46: '嗬', 47: '嗔', 48: '鄙', 49: '嗦', 50: '嗝', 51: '愚', 52: '戥', 53: '嗄', 54: '暖', 55: '盟', 56: '煦',\n          57: '歇', 58: '暗', 59: '暅', 60: '暄', 61: '暇', 62: '照', 63: '遢', 64: '暌', 65: '畸', 66: '跬', 67: '跨',\n          68: '跶', 69: '跷', 70: '跸', 71: '跐', 72: '跣', 73: '跹', 74: '跳', 75: '跺', 76: '跪', 77: '路', 78: '跻',\n          79: '跤', 80: '跟', 81: '遣', 82: '蛸', 83: '蜈', 84: '蜎', 85: '蜗', 86: '蛾', 87: '蜊', 88: '蜍', 89: '蜉',\n          90: '蜂', 91: '蜣', 92: '蜕', 93: '畹', 94: '蛹', 95: '嗣', 96: '嗯', 97: '嗅', 98: '嗥', 99: '嗲', 100: '嗳',\n          101: '嗡', 102: '嗌', 103: '嗍', 104: '嗨', 105: '嗤', 106: '嗵', 107: '嗓', 108: '署', 109: '置', 110: '罨',\n          111: '罪', 112: '罩', 113: '蜀', 114: '幌', 115: '嵊', 116: '嵩', 117: '嵴', 118: '骰', 119: '锖', 120: '锗',\n          121: '错', 122: '锘', 123: '锚', 124: '锛', 125: '锜', 126: '锝', 127: '锞', 128: '锟', 129: '锡', 130: '锢',\n          131: '锣', 132: '锤', 133: '锥', 134: '锦', 135: '锧', 136: '锨', 137: '锪', 138: '锫', 139: '锩', 140: '锬',\n          141: '锭', 142: '键', 143: '锯', 144: '锰', 145: '锱', 146: '矮', 147: '雉', 148: '氲', 149: '犏', 150: '辞',\n          151: '歃', 152: '稞', 153: '稚', 154: '稗', 155: '稔', 156: '稠', 157: '颓', 158: '愁', 159: '筹', 160: '筠',\n          161: '筢', 162: '筮', 163: '筻', 164: '筲', 165: '筼', 166: '筱', 167: '签', 168: '简', 169: '筷', 170: '毁',\n          171: '舅', 172: '鼠', 173: '牒', 174: '煲', 175: '催', 176: '傻', 177: '像', 178: '躲', 179: '鹎', 180: '魁',\n          181: '敫', 182: '僇', 183: '衙', 184: '微', 185: '徭', 186: '愆', 187: '艄', 188: '觎', 189: '毹', 190: '愈',\n          191: '遥', 192: '貊', 193: '貅', 194: '貉', 195: '颔', 196: '腻', 197: '腠', 198: '腩', 199: '腰', 200: '腼',\n          201: '腽', 202: '腥', 203: '腮', 204: '腭', 205: '腹', 206: '腺', 207: '腧', 208: '鹏', 209: '塍', 210: '媵',\n          211: '腾', 212: '腿', 213: '詹', 214: '鲅', 215: '鲆', 216: '鲇', 217: '鲈', 218: '鲉', 219: '鲊', 220: '稣',\n          221: '鲋', 222: '鲌', 223: '鲍', 224: '鲏', 225: '鲐', 226: '肄', 227: '猿', 228: '颖', 229: '鹐', 230: '飔',\n          231: '飕', 232: '觥', 233: '触', 234: '解', 235: '遛', 236: '煞', 237: '雏', 238: '馌', 239: '馍', 240: '馏',\n          241: '馐', 242: '酱', 243: '鹑', 244: '禀', 245: '亶', 246: '廒', 247: '瘃', 248: '痱', 249: '痹', 250: '痼',\n          251: '廓', 252: '痴', 253: '痿', 254: '瘐', 255: '瘁'},\n    149: {1: '瘅', 2: '痰', 3: '瘆', 4: '廉', 5: '鄘', 6: '麂', 7: '裔', 8: '靖', 9: '新', 10: '鄣', 11: '歆', 12: '韵',\n          13: '意', 14: '旒', 15: '雍', 16: '阖', 17: '阗', 18: '阘', 19: '阙', 20: '羧', 21: '豢', 22: '誊', 23: '粳',\n          24: '粮', 25: '数', 26: '煎', 27: '猷', 28: '塑', 29: '慈', 30: '煤', 31: '煳', 32: '煜', 33: '煨', 34: '煅',\n          35: '煌', 36: '煊', 37: '煸', 38: '煺', 39: '滟', 40: '溱', 41: '溘', 42: '滠', 43: '满', 44: '漭', 45: '漠',\n          46: '滢', 47: '滇', 48: '溥', 49: '溧', 50: '溽', 51: '源', 52: '滤', 53: '滥', 54: '裟', 55: '溻', 56: '溷',\n          57: '溦', 58: '滗', 59: '滫', 60: '溴', 61: '滏', 62: '滔', 63: '溪', 64: '滃', 65: '溜', 66: '滦', 67: '漓',\n          68: '滚', 69: '溏', 70: '滂', 71: '溢', 72: '溯', 73: '滨', 74: '溶', 75: '滓', 76: '溟', 77: '滘', 78: '溺',\n          79: '滍', 80: '粱', 81: '滩', 82: '滪', 83: '愫', 84: '慑', 85: '慎', 86: '慥', 87: '慊', 88: '誉', 89: '鲎',\n          90: '塞', 91: '骞', 92: '寞', 93: '窥', 94: '窦', 95: '窠', 96: '窣', 97: '窟', 98: '寝', 99: '谨', 100: '裱',\n          101: '褂', 102: '褚', 103: '裸', 104: '裼', 105: '裨', 106: '裾', 107: '裰', 108: '禊', 109: '福', 110: '谩',\n          111: '谪', 112: '谫', 113: '谬', 114: '群', 115: '殿', 116: '辟', 117: '障', 118: '媾', 119: '嫫', 120: '媳',\n          121: '媲', 122: '嫒', 123: '嫉', 124: '嫌', 125: '嫁', 126: '嫔', 127: '媸', 128: '叠', 129: '缙', 130: '缜',\n          131: '缚', 132: '缛', 133: '辔', 134: '缝', 135: '骝', 136: '缟', 137: '缠', 138: '缡', 139: '缢', 140: '缣',\n          141: '缤', 142: '骟', 143: '剿', 144: '耥', 145: '璈', 146: '静', 147: '碧', 148: '瑶', 149: '璃', 150: '瑭',\n          151: '瑢', 152: '獒', 153: '赘', 154: '熬', 155: '觏', 156: '慝', 157: '嫠', 158: '韬', 159: '髦', 160: '墈',\n          161: '墙', 162: '摽', 163: '墟', 164: '撇', 165: '墁', 166: '撂', 167: '摞', 168: '嘉', 169: '摧', 170: '撄',\n          171: '赫', 172: '截', 173: '翥', 174: '踅', 175: '誓', 176: '銎', 177: '摭', 178: '墉', 179: '境', 180: '摘',\n          181: '墒', 182: '摔', 183: '榖', 184: '撖', 185: '摺', 186: '綦', 187: '聚', 188: '蔫', 189: '蔷', 190: '靺',\n          191: '靼', 192: '鞅', 193: '靽', 194: '鞁', 195: '靿', 196: '蔌', 197: '蔽', 198: '慕', 199: '暮', 200: '摹',\n          201: '蔓', 202: '蔑', 203: '甍', 204: '蔸', 205: '蓰', 206: '蔹', 207: '蔡', 208: '蔗', 209: '蔟', 210: '蔺',\n          211: '戬', 212: '蕖', 213: '蔻', 214: '蓿', 215: '蔼', 216: '斡', 217: '熙', 218: '蔚', 219: '鹕', 220: '兢',\n          221: '嘏', 222: '蓼', 223: '榛', 224: '榧', 225: '模', 226: '槚', 227: '槛', 228: '榻', 229: '榫', 230: '槜',\n          231: '榭', 232: '槔', 233: '榴', 234: '槁', 235: '榜', 236: '槟', 237: '榨', 238: '榕', 239: '槠', 240: '榷',\n          241: '榍', 242: '歌', 243: '遭', 244: '僰', 245: '酵', 246: '酽', 247: '酾', 248: '酲', 249: '酷', 250: '酶',\n          251: '酴', 252: '酹', 253: '酿', 254: '酸', 255: '厮'},\n    150: {1: '碶', 2: '碡', 3: '碟', 4: '碴', 5: '碱', 6: '碣', 7: '碳', 8: '碲', 9: '磋', 10: '磁', 11: '碹', 12: '碥',\n          13: '愿', 14: '劂', 15: '臧', 16: '豨', 17: '殡', 18: '需', 19: '霆', 20: '霁', 21: '辕', 22: '辖', 23: '辗',\n          24: '蜚', 25: '裴', 26: '翡', 27: '雌', 28: '龇', 29: '龈', 30: '睿', 31: '弊', 32: '裳', 33: '颗', 34: '夥',\n          35: '瞅', 36: '瞍', 37: '睽', 38: '墅', 39: '嘞', 40: '嘈', 41: '嗽', 42: '嘌', 43: '嘁', 44: '嘎', 45: '暧',\n          46: '暝', 47: '踌', 48: '踉', 49: '跽', 50: '踊', 51: '蜻', 52: '蜞', 53: '蜡', 54: '蜥', 55: '蜮', 56: '蜾',\n          57: '蝈', 58: '蜴', 59: '蝇', 60: '蜘', 61: '蜱', 62: '蜩', 63: '蜷', 64: '蝉', 65: '蜿', 66: '螂', 67: '蜢',\n          68: '嘘', 69: '嘡', 70: '鹗', 71: '嘣', 72: '嘤', 73: '嘚', 74: '嘛', 75: '嘀', 76: '嗾', 77: '嘧', 78: '罴',\n          79: '罱', 80: '幔', 81: '嶂', 82: '幛', 83: '赙', 84: '罂', 85: '赚', 86: '骷', 87: '骶', 88: '鹘', 89: '锲',\n          90: '锴', 91: '锶', 92: '锷', 93: '锸', 94: '锹', 95: '锻', 96: '锽', 97: '锾', 98: '锵', 99: '锿', 100: '镀',\n          101: '镁', 102: '镂', 103: '镃', 104: '镄', 105: '镅', 106: '舞', 107: '犒', 108: '舔', 109: '稳', 110: '熏',\n          111: '箐', 112: '箦', 113: '箧', 114: '箍', 115: '箸', 116: '箨', 117: '箕', 118: '箬', 119: '算', 120: '箅',\n          121: '箩', 122: '箪', 123: '箔', 124: '管', 125: '箜', 126: '箢', 127: '箫', 128: '箓', 129: '毓', 130: '舆',\n          131: '僖', 132: '儆', 133: '僳', 134: '僚', 135: '僭', 136: '僬', 137: '劁', 138: '僦', 139: '僮', 140: '僧',\n          141: '鼻', 142: '魄', 143: '魅', 144: '魃', 145: '魆', 146: '睾', 147: '艋', 148: '鄱', 149: '貌', 150: '膜',\n          151: '膊', 152: '膈', 153: '膀', 154: '膑', 155: '鲑', 156: '鲔', 157: '鲙', 158: '鲚', 159: '鲛', 160: '鲜',\n          161: '鲟', 162: '疑', 163: '獐', 164: '獍', 165: '飗', 166: '觫', 167: '雒', 168: '孵', 169: '夤', 170: '馑',\n          171: '馒', 172: '銮', 173: '裹', 174: '敲', 175: '豪', 176: '膏', 177: '塾', 178: '遮', 179: '麽', 180: '廙',\n          181: '腐', 182: '瘩', 183: '瘌', 184: '瘗', 185: '瘟', 186: '瘦', 187: '瘊', 188: '瘥', 189: '瘘', 190: '瘙',\n          191: '廖', 192: '辣', 193: '彰', 194: '竭', 195: '韶', 196: '端', 197: '旗', 198: '旖', 199: '膂', 200: '阚',\n          201: '鄯', 202: '鲞', 203: '精', 204: '粼', 205: '粹', 206: '粽', 207: '糁', 208: '歉', 209: '槊', 210: '鹚',\n          211: '熄', 212: '熘', 213: '熔', 214: '煽', 215: '熥', 216: '潢', 217: '潆', 218: '潇', 219: '漤', 220: '漆',\n          221: '漕', 222: '漱', 223: '漂', 224: '滹', 225: '漫', 226: '漯', 227: '漶', 228: '潋', 229: '潴', 230: '漪',\n          231: '漉', 232: '漳', 233: '滴', 234: '漩', 235: '漾', 236: '演', 237: '澉', 238: '漏', 239: '潍', 240: '慢',\n          241: '慷', 242: '慵', 243: '寨', 244: '赛', 245: '搴', 246: '寡', 247: '窬', 248: '窨', 249: '窭', 250: '察',\n          251: '蜜', 252: '寤', 253: '寥', 254: '谭', 255: '肇'},\n    151: {1: '綮', 2: '谮', 3: '褡', 4: '褙', 5: '褐', 6: '褓', 7: '褛', 8: '褊', 9: '褪', 10: '禚', 11: '谯', 12: '谰',\n          13: '谱', 14: '谲', 15: '暨', 16: '屣', 17: '鹛', 18: '隧', 19: '嫣', 20: '嫱', 21: '嫩', 22: '嫖', 23: '嫦',\n          24: '嫚', 25: '嫘', 26: '嫜', 27: '嫡', 28: '嫪', 29: '鼐', 30: '翟', 31: '翠', 32: '熊', 33: '凳', 34: '瞀',\n          35: '鹜', 36: '骠', 37: '缥', 38: '缦', 39: '缧', 40: '骡', 41: '缨', 42: '骢', 43: '缩', 44: '缪', 45: '缫',\n          46: '慧', 47: '耦', 48: '耧', 49: '瑾', 50: '璜', 51: '璀', 52: '璎', 53: '璁', 54: '璋', 55: '璇', 56: '璆',\n          57: '奭', 58: '撵', 59: '髯', 60: '髫', 61: '撷', 62: '撕', 63: '撒', 64: '撅', 65: '撩', 66: '趣', 67: '趟',\n          68: '撑', 69: '撮', 70: '撬', 71: '赭', 72: '播', 73: '墦', 74: '擒', 75: '撸', 76: '鋆', 77: '墩', 78: '撞',\n          79: '撤', 80: '撙', 81: '增', 82: '撺', 83: '墀', 84: '撰', 85: '聩', 86: '聪', 87: '觐', 88: '鞋', 89: '鞑',\n          90: '蕙', 91: '鞒', 92: '鞍', 93: '蕈', 94: '蕨', 95: '蕤', 96: '蕞', 97: '蕺', 98: '瞢', 99: '蕉', 100: '劐',\n          101: '蕃', 102: '蕲', 103: '蕰', 104: '蕊', 105: '赜', 106: '蔬', 107: '蕴', 108: '鼒', 109: '槿', 110: '横',\n          111: '樯', 112: '槽', 113: '槭', 114: '樗', 115: '樘', 116: '樱', 117: '樊', 118: '橡', 119: '槲', 120: '樟',\n          121: '橄', 122: '敷', 123: '鹝', 124: '豌', 125: '飘', 126: '醋', 127: '醌', 128: '醇', 129: '醉', 130: '醅',\n          131: '靥', 132: '魇', 133: '餍', 134: '磕', 135: '磊', 136: '磔', 137: '磙', 138: '磅', 139: '碾', 140: '磉',\n          141: '殣', 142: '慭', 143: '震', 144: '霄', 145: '霉', 146: '霈', 147: '辘', 148: '龉', 149: '龊', 150: '觑',\n          151: '憋', 152: '瞌', 153: '瞒', 154: '题', 155: '暴', 156: '瞎', 157: '瞑', 158: '嘻', 159: '嘭', 160: '噎',\n          161: '嘶', 162: '噶', 163: '嘲', 164: '颙', 165: '暹', 166: '嘹', 167: '影', 168: '踔', 169: '踝', 170: '踢',\n          171: '踏', 172: '踟', 173: '踬', 174: '踩', 175: '踮', 176: '踣', 177: '踯', 178: '踪', 179: '踺', 180: '踞',\n          181: '蝽', 182: '蝶', 183: '蝾', 184: '蝴', 185: '蝻', 186: '蝠', 187: '蝰', 188: '蝎', 189: '蝌', 190: '蝮',\n          191: '螋', 192: '蝗', 193: '蝓', 194: '蝣', 195: '蝼', 196: '蝤', 197: '蝙', 198: '噗', 199: '嘬', 200: '颚',\n          201: '嘿', 202: '噍', 203: '噢', 204: '噙', 205: '噜', 206: '噌', 207: '嘱', 208: '噀', 209: '噔', 210: '颛',\n          211: '幞', 212: '幡', 213: '嶓', 214: '幢', 215: '嶙', 216: '嶝', 217: '墨', 218: '骺', 219: '骼', 220: '骸',\n          221: '镊', 222: '镆', 223: '镇', 224: '镈', 225: '镉', 226: '镋', 227: '镌', 228: '镍', 229: '镎', 230: '镏',\n          231: '镐', 232: '镑', 233: '镒', 234: '镓', 235: '镔', 236: '靠', 237: '稽', 238: '稷', 239: '稻', 240: '黎',\n          241: '稿', 242: '稼', 243: '箱', 244: '箴', 245: '篑', 246: '篁', 247: '篌', 248: '篓', 249: '箭', 250: '篇',\n          251: '篆', 252: '僵', 253: '牖', 254: '儇', 255: '儋'},\n    152: {1: '躺', 2: '僻', 3: '德', 4: '徵', 5: '艘', 6: '磐', 7: '虢', 8: '鹞', 9: '鹟', 10: '膝', 11: '膘', 12: '膛',\n          13: '滕', 14: '鲠', 15: '鲡', 16: '鲢', 17: '鲣', 18: '鲥', 19: '鲤', 20: '鲦', 21: '鲧', 22: '鲩', 23: '鲪',\n          24: '鲫', 25: '鲬', 26: '橥', 27: '獗', 28: '獠', 29: '觯', 30: '鹠', 31: '馓', 32: '馔', 33: '熟', 34: '摩',\n          35: '麾', 36: '褒', 37: '廛', 38: '鹡', 39: '瘛', 40: '瘼', 41: '瘪', 42: '瘢', 43: '瘤', 44: '瘠', 45: '瘫',\n          46: '齑', 47: '凛', 48: '颜', 49: '毅', 50: '羯', 51: '羰', 52: '糊', 53: '糇', 54: '遴', 55: '糌', 56: '糍',\n          57: '糈', 58: '糅', 59: '翦', 60: '遵', 61: '鹣', 62: '熜', 63: '熵', 64: '熠', 65: '潜', 66: '澍', 67: '澎',\n          68: '澌', 69: '潵', 70: '潮', 71: '潸', 72: '潭', 73: '潦', 74: '鲨', 75: '潲', 76: '鋈', 77: '潟', 78: '澳',\n          79: '潘', 80: '潼', 81: '澈', 82: '澜', 83: '潽', 84: '潺', 85: '澄', 86: '潏', 87: '懂', 88: '憬', 89: '憔',\n          90: '懊', 91: '憧', 92: '憎', 93: '寮', 94: '窳', 95: '额', 96: '谳', 97: '翩', 98: '褥', 99: '褴', 100: '褫',\n          101: '禤', 102: '谴', 103: '鹤', 104: '谵', 105: '憨', 106: '熨', 107: '慰', 108: '劈', 109: '履', 110: '屦',\n          111: '嬉', 112: '勰', 113: '戮', 114: '蝥', 115: '豫', 116: '缬', 117: '缭', 118: '缮', 119: '缯', 120: '骣',\n          121: '畿', 122: '耩', 123: '耨', 124: '耪', 125: '璞', 126: '璟', 127: '靛', 128: '璠', 129: '璘', 130: '聱',\n          131: '螯', 132: '髻', 133: '髭', 134: '髹', 135: '擀', 136: '撼', 137: '擂', 138: '操', 139: '熹', 140: '甏',\n          141: '擐', 142: '擅', 143: '擞', 144: '磬', 145: '鄹', 146: '颞', 147: '蕻', 148: '鞘', 149: '燕', 150: '黇',\n          151: '颟', 152: '薤', 153: '蕾', 154: '薯', 155: '薨', 156: '薛', 157: '薇', 158: '檠', 159: '擎', 160: '薪',\n          161: '薏', 162: '蕹', 163: '薮', 164: '薄', 165: '颠', 166: '翰', 167: '噩', 168: '薜', 169: '薅', 170: '樾',\n          171: '橱', 172: '橛', 173: '橇', 174: '樵', 175: '檎', 176: '橹', 177: '橦', 178: '樽', 179: '樨', 180: '橙',\n          181: '橘', 182: '橼', 183: '墼', 184: '整', 185: '橐', 186: '融', 187: '翮', 188: '瓢', 189: '醛', 190: '醐',\n          191: '醍', 192: '醒', 193: '醚', 194: '醑', 195: '觱', 196: '磺', 197: '磲', 198: '赝', 199: '飙', 200: '殪',\n          201: '霖', 202: '霏', 203: '霓', 204: '霍', 205: '霎', 206: '錾', 207: '辙', 208: '辚', 209: '臻', 210: '冀',\n          211: '餐', 212: '遽', 213: '氅', 214: '瞥', 215: '瞟', 216: '瞠', 217: '瞰', 218: '嚄', 219: '嚆', 220: '噤',\n          221: '暾', 222: '曈', 223: '蹀', 224: '蹅', 225: '踶', 226: '踹', 227: '踵', 228: '踽', 229: '嘴', 230: '踱',\n          231: '蹄', 232: '蹉', 233: '蹁', 234: '蹂', 235: '螨', 236: '蟒', 237: '蟆', 238: '螈', 239: '螅', 240: '螭',\n          241: '螗', 242: '螃', 243: '螠', 244: '螟', 245: '噱', 246: '器', 247: '噪', 248: '噬', 249: '噫', 250: '噻',\n          251: '噼', 252: '幪', 253: '罹', 254: '圜', 255: '鹦'},\n    153: {1: '赠', 2: '默', 3: '黔', 4: '镖', 5: '镗', 6: '镘', 7: '镚', 8: '镛', 9: '镜', 10: '镝', 11: '镞', 12: '镠',\n          13: '氇', 14: '氆', 15: '赞', 16: '憩', 17: '穑', 18: '穆', 19: '穄', 20: '篝', 21: '篚', 22: '篥', 23: '篮',\n          24: '篡', 25: '簉', 26: '篦', 27: '篪', 28: '篷', 29: '篙', 30: '篱', 31: '盥', 32: '儒', 33: '劓', 34: '翱',\n          35: '魉', 36: '魈', 37: '邀', 38: '徼', 39: '衡', 40: '歙', 41: '盦', 42: '膨', 43: '膪', 44: '膳', 45: '螣',\n          46: '膦', 47: '膙', 48: '雕', 49: '鲭', 50: '鲮', 51: '鲯', 52: '鲰', 53: '鲱', 54: '鲲', 55: '鲳', 56: '鲴',\n          57: '鲵', 58: '鲷', 59: '鲸', 60: '鲺', 61: '鲹', 62: '鲻', 63: '獴', 64: '獭', 65: '獬', 66: '邂', 67: '憝',\n          68: '亸', 69: '鹧', 70: '磨', 71: '廨', 72: '赟', 73: '癀', 74: '瘭', 75: '瘰', 76: '廪', 77: '瘿', 78: '瘵',\n          79: '瘴', 80: '癃', 81: '瘾', 82: '瘸', 83: '瘳', 84: '斓', 85: '麇', 86: '麈', 87: '凝', 88: '辨', 89: '辩',\n          90: '嬴', 91: '壅', 92: '羲', 93: '糙', 94: '糗', 95: '糖', 96: '糕', 97: '甑', 98: '燎', 99: '燠', 100: '燔',\n          101: '燃', 102: '燧', 103: '燊', 104: '燏', 105: '濑', 106: '濒', 107: '濉', 108: '潞', 109: '澧', 110: '澡',\n          111: '澴', 112: '激', 113: '澹', 114: '澥', 115: '澶', 116: '濂', 117: '澼', 118: '憷', 119: '懒', 120: '憾',\n          121: '懈', 122: '黉', 123: '褰', 124: '寰', 125: '窸', 126: '窿', 127: '褶', 128: '禧', 129: '壁', 130: '避',\n          131: '嬖', 132: '犟', 133: '隰', 134: '嬗', 135: '鹨', 136: '翯', 137: '颡', 138: '缰', 139: '缱', 140: '缲',\n          141: '缳', 142: '缴', 143: '璨', 144: '璩', 145: '璐', 146: '璪', 147: '戴', 148: '螫', 149: '擤', 150: '壕',\n          151: '擦', 152: '觳', 153: '罄', 154: '擢', 155: '藉', 156: '薹', 157: '鞡', 158: '鞠', 159: '藏', 160: '薷',\n          161: '薰', 162: '藐', 163: '藓', 164: '藁', 165: '檬', 166: '檑', 167: '檄', 168: '檐', 169: '檩', 170: '檀',\n          171: '懋', 172: '醢', 173: '翳', 174: '繄', 175: '礁', 176: '礅', 177: '磷', 178: '磴', 179: '鹩', 180: '霜',\n          181: '霞', 182: '龋', 183: '龌', 184: '豳', 185: '壑', 186: '黻', 187: '瞭', 188: '瞧', 189: '瞬', 190: '瞳',\n          191: '瞵', 192: '瞩', 193: '瞪', 194: '嚏', 195: '曙', 196: '嚅', 197: '蹑', 198: '蹒', 199: '蹋', 200: '蹈',\n          201: '蹊', 202: '蹓', 203: '蹐', 204: '蟥', 205: '螬', 206: '螵', 207: '疃', 208: '螳', 209: '螺', 210: '蟋',\n          211: '蟑', 212: '蟀', 213: '嚎', 214: '嚓', 215: '羁', 216: '罽', 217: '罾', 218: '嶷', 219: '赡', 220: '黜',\n          221: '黝', 222: '髁', 223: '髀', 224: '镡', 225: '镢', 226: '镣', 227: '镤', 228: '镥', 229: '镦', 230: '镧',\n          231: '镨', 232: '镩', 233: '镪', 234: '镫', 235: '罅', 236: '穗', 237: '黏', 238: '魏', 239: '簧', 240: '簌',\n          241: '篾', 242: '簃', 243: '篼', 244: '簏', 245: '簇', 246: '簖', 247: '簋', 248: '繁', 249: '鼢', 250: '黛',\n          251: '儡', 252: '鹪', 253: '鼾', 254: '皤', 255: '魍'},\n    154: {1: '徽', 2: '艚', 3: '龠', 4: '爵', 5: '繇', 6: '貘', 7: '邈', 8: '貔', 9: '臌', 10: '朦', 11: '臊', 12: '膻',\n          13: '臁', 14: '臆', 15: '臃', 16: '鲼', 17: '鲽', 18: '鲾', 19: '鳀', 20: '鳁', 21: '鳂', 22: '鳃', 23: '鳄',\n          24: '鳅', 25: '鳆', 26: '鳇', 27: '鳈', 28: '鳉', 29: '鳊', 30: '獯', 31: '螽', 32: '燮', 33: '鹫', 34: '襄',\n          35: '糜', 36: '縻', 37: '膺', 38: '癍', 39: '癌', 40: '麋', 41: '辫', 42: '赢', 43: '糟', 44: '糠', 45: '馘',\n          46: '燥', 47: '懑', 48: '濡', 49: '濮', 50: '濞', 51: '濠', 52: '濯', 53: '懦', 54: '豁', 55: '蹇', 56: '謇',\n          57: '邃', 58: '襕', 59: '襁', 60: '臀', 61: '檗', 62: '甓', 63: '臂', 64: '擘', 65: '孺', 66: '隳', 67: '嬷',\n          68: '翼', 69: '蟊', 70: '鹬', 71: '鍪', 72: '骤', 73: '鏊', 74: '鳌', 75: '鬹', 76: '鬈', 77: '鬃', 78: '瞽',\n          79: '藕', 80: '鞯', 81: '鞨', 82: '鞭', 83: '鞫', 84: '鞧', 85: '鞣', 86: '藜', 87: '藠', 88: '藤', 89: '藩',\n          90: '鹲', 91: '檫', 92: '檵', 93: '覆', 94: '醪', 95: '蹙', 96: '礞', 97: '礓', 98: '礌', 99: '燹', 100: '餮',\n          101: '蹩', 102: '瞿', 103: '瞻', 104: '曛', 105: '颢', 106: '曜', 107: '躇', 108: '蹦', 109: '鹭', 110: '蹢',\n          111: '蹜', 112: '蟛', 113: '蟪', 114: '蟠', 115: '蟮', 116: '嚚', 117: '嚣', 118: '鹮', 119: '黠', 120: '黟',\n          121: '髅', 122: '髂', 123: '镬', 124: '镭', 125: '镯', 126: '镰', 127: '镱', 128: '馥', 129: '簠', 130: '簟',\n          131: '簪', 132: '簦', 133: '鼫', 134: '鼬', 135: '鼩', 136: '雠', 137: '艟', 138: '翻', 139: '臑', 140: '鳍',\n          141: '鳎', 142: '鳏', 143: '鳐', 144: '鳑', 145: '鹱', 146: '鹰', 147: '癞', 148: '癔', 149: '癜', 150: '癖',\n          151: '糨', 152: '冁', 153: '瀑', 154: '瀍', 155: '瀌', 156: '鎏', 157: '懵', 158: '襟', 159: '璧', 160: '戳',\n          161: '彝', 162: '邋', 163: '鬏', 164: '攉', 165: '攒', 166: '鞲', 167: '鞴', 168: '藿', 169: '蘧', 170: '孽',\n          171: '蘅', 172: '警', 173: '蘑', 174: '藻', 175: '麓', 176: '攀', 177: '醭', 178: '醮', 179: '醯', 180: '礤',\n          181: '酃', 182: '霪', 183: '霭', 184: '黼', 185: '鳖', 186: '曝', 187: '嚯', 188: '蹰', 189: '蹶', 190: '蹽',\n          191: '蹼', 192: '蹯', 193: '蹴', 194: '蹾', 195: '蹲', 196: '蹭', 197: '蹿', 198: '蹬', 199: '蠖', 200: '蠓',\n          201: '蠋', 202: '蟾', 203: '蠊', 204: '巅', 205: '黢', 206: '髋', 207: '髌', 208: '镲', 209: '籀', 210: '簸',\n          211: '籁', 212: '簿', 213: '鳘', 214: '齁', 215: '魑', 216: '艨', 217: '鼗', 218: '鳓', 219: '鳔', 220: '鳕',\n          221: '鳗', 222: '鳙', 223: '鳚', 224: '蟹', 225: '颤', 226: '靡', 227: '癣', 228: '麒', 229: '鏖', 230: '瓣',\n          231: '蠃', 232: '羸', 233: '羹', 234: '爆', 235: '瀚', 236: '瀣', 237: '瀛', 238: '襦', 239: '谶', 240: '襞',\n          241: '疆', 242: '骥', 243: '缵', 244: '瓒', 245: '鬓', 246: '壤', 247: '攘', 248: '馨', 249: '蘩', 250: '蘖',\n          251: '蘘', 252: '醵', 253: '醴', 254: '霰', 255: '颥'},\n    155: {1: '酆', 2: '耀', 3: '矍', 4: '曦', 5: '躁', 6: '躅', 7: '蠕', 8: '鼍', 9: '嚼', 10: '嚷', 11: '巍', 12: '巉',\n          13: '黩', 14: '黥', 15: '镳', 16: '镴', 17: '黧', 18: '籍', 19: '纂', 20: '鼯', 21: '犨', 22: '臜', 23: '鳜',\n          24: '鳝', 25: '鳞', 26: '鳟', 27: '獾', 28: '魔', 29: '糯', 30: '灌', 31: '瀹', 32: '瀵', 33: '譬', 34: '孀',\n          35: '骧', 36: '耰', 37: '蠢', 38: '瓘', 39: '鼙', 40: '醺', 41: '礴', 42: '礳', 43: '霸', 44: '露', 45: '霹',\n          46: '颦', 47: '曩', 48: '躏', 49: '黯', 50: '髓', 51: '鼱', 52: '鳡', 53: '鳢', 54: '癫', 55: '麝', 56: '赣',\n          57: '夔', 58: '爝', 59: '灏', 60: '禳', 61: '鐾', 62: '羼', 63: '蠡', 64: '耲', 65: '耱', 66: '懿', 67: '韂',\n          68: '蘸', 69: '鹳', 70: '糵', 71: '蘼', 72: '囊', 73: '霾', 74: '氍', 75: '饕', 76: '躔', 77: '躐', 78: '髑',\n          79: '镵', 80: '镶', 81: '穰', 82: '鳤', 83: '瓤', 84: '饔', 85: '鬻', 86: '鬟', 87: '趱', 88: '攫', 89: '攥',\n          90: '颧', 91: '躜', 92: '罐', 93: '鼹', 94: '鼷', 95: '癯', 96: '麟', 97: '蠲', 98: '矗', 99: '蠹', 100: '醾',\n          101: '躞', 102: '衢', 103: '鑫', 104: '灞', 105: '襻', 106: '纛', 107: '鬣', 108: '攮', 109: '囔', 110: '馕',\n          111: '戆', 112: '蠼', 113: '爨', 114: '齉'}\n}\nREVERSE_FONT_MAPPING = {}\nfor first_byte, inner_dict in FONT_MAPPING.items():\n    for second_byte, character in inner_dict.items():\n        REVERSE_FONT_MAPPING[character] = (first_byte, second_byte)\nCHINESE_CHARSET = \"\".join(REVERSE_FONT_MAPPING.keys())\nVALID_CHARACTERS = chirp_common.CHARSET_ASCII + CHINESE_CHARSET\n\n\ndef convert_bytes_to_chinese(data: bytes) -> str:\n    \"\"\"Convert bytes to a string of chinese characters\"\"\"\n    last_byte = 0x00\n    text = ''\n    for byte in data:\n        if last_byte == 0x00 and byte == 0xFF or byte == 0x00:\n            break\n        if byte >= 0x80 and last_byte == 0x00:\n            last_byte = byte\n            continue\n        if last_byte != 0x00:\n            text += FONT_MAPPING[last_byte][byte]\n            last_byte = 0x00\n            continue\n        text += chr(byte)\n    return text\n\n\ndef convert_chinese_to_ascii_chars(data: str) -> str:\n    text = ''\n    for char in data:\n        if char in chirp_common.CHARSET_ASCII:\n            text += char\n        elif char in CHINESE_CHARSET:\n            reverse_str = REVERSE_FONT_MAPPING[char]\n            text += chr(reverse_str[0])\n            text += chr(reverse_str[1])\n    return text\n\n\nclass RadioSettingChineseValueString(RadioSettingValueString):\n\n    \"\"\"A string setting\"\"\"\n\n    def __init__(self, minlength, maxlength, current,\n                 autopad=True, charset=chirp_common.CHARSET_ASCII):\n        RadioSettingValueString.__init__(self, minlength, maxlength, current, autopad, charset)\n\n    def set_value(self, value):\n        if len(value) < self._minlength or len(convert_chinese_to_ascii_chars(value)) > self._maxlength:\n            raise InvalidValueError(\"Value must be between %i and %i chars\" %\n                                    (self._minlength, self._maxlength))\n        if self._autopad:\n            value = value.ljust(self._maxlength)\n        for char in value:\n            if char not in self._charset:\n                raise InvalidValueError(\"Value contains invalid \" +\n                                        \"character `%s'\" % char)\n        RadioSettingValue.set_value(self, value)\n\n\n# the communication is obfuscated using this fine mechanism\ndef xorarr(data: bytes):\n    tbl = [22, 108, 20, 230, 46, 145, 13, 64, 33, 53, 213, 64, 19, 3, 233, 128]\n    x = b\"\"\n    r = 0\n    for byte in data:\n        x += bytes([byte ^ tbl[r]])\n        r = (r+1) % len(tbl)\n    return x\n\n\n# if this crc was used for communication to AND from the radio, then it\n# would be a measure to increase reliability.\n# but it's only used towards the radio, so it's for further obfuscation\ndef calculate_crc16_xmodem(data: bytes):\n    poly = 0x1021\n    crc = 0x0\n    for byte in data:\n        crc = crc ^ (byte << 8)\n        for i in range(8):\n            crc = crc << 1\n            if (crc & 0x10000):\n                crc = (crc ^ poly) & 0xFFFF\n    return crc & 0xFFFF\n\n\ndef _send_command(serport, data: bytes):\n    \"\"\"Send a command to UV-K5 radio\"\"\"\n    LOG.debug(\"Sending command (unobfuscated) len=0x%4.4x:\\n%s\" %\n              (len(data), util.hexprint(data)))\n\n    crc = calculate_crc16_xmodem(data)\n    data2 = data + struct.pack(\"<H\", crc)\n\n    command = struct.pack(\">HBB\", 0xabcd, len(data), 0) + \\\n        xorarr(data2) + \\\n        struct.pack(\">H\", 0xdcba)\n    if DEBUG_SHOW_OBFUSCATED_COMMANDS:\n        LOG.debug(\"Sending command (obfuscated):\\n%s\" % util.hexprint(command))\n    try:\n        result = serport.write(command)\n    except Exception:\n        raise errors.RadioError(\"Error writing data to radio\")\n    return result\n\n\ndef _receive_reply(serport):\n    header = serport.read(4)\n    if len(header) != 4:\n        LOG.warning(\"Header short read: [%s] len=%i\" %\n                    (util.hexprint(header), len(header)))\n        raise errors.RadioError(\"Header short read\")\n    if header[0] != 0xAB or header[1] != 0xCD or header[3] != 0x00:\n        LOG.warning(\"Bad response header: %s len=%i\" %\n                    (util.hexprint(header), len(header)))\n        raise errors.RadioError(\"Bad response header\")\n\n    cmd = serport.read(int(header[2]))\n    if len(cmd) != int(header[2]):\n        LOG.warning(\"Body short read: [%s] len=%i\" %\n                    (util.hexprint(cmd), len(cmd)))\n        raise errors.RadioError(\"Command body short read\")\n\n    footer = serport.read(4)\n\n    if len(footer) != 4:\n        LOG.warning(\"Footer short read: [%s] len=%i\" %\n                    (util.hexprint(footer), len(footer)))\n        raise errors.RadioError(\"Footer short read\")\n\n    if footer[2] != 0xDC or footer[3] != 0xBA:\n        LOG.debug(\n                \"Reply before bad response footer (obfuscated)\"\n                \"len=0x%4.4x:\\n%s\" % (len(cmd), util.hexprint(cmd)))\n        LOG.warning(\"Bad response footer: %s len=%i\" %\n                    (util.hexprint(footer), len(footer)))\n        raise errors.RadioError(\"Bad response footer\")\n\n    if DEBUG_SHOW_OBFUSCATED_COMMANDS:\n        LOG.debug(\"Received reply (obfuscated) len=0x%4.4x:\\n%s\" %\n                  (len(cmd), util.hexprint(cmd)))\n\n    cmd2 = xorarr(cmd)\n\n    LOG.debug(\"Received reply (unobfuscated) len=0x%4.4x:\\n%s\" %\n              (len(cmd2), util.hexprint(cmd2)))\n\n    return cmd2\n\n\ndef _getstring(data: bytes, begin, maxlen):\n    tmplen = min(maxlen+1, len(data))\n    s = [data[i] for i in range(begin, tmplen)]\n    for key, val in enumerate(s):\n        if val < ord(' ') or val > ord('~'):\n            break\n    return ''.join(chr(x) for x in s[0:key])\n\n\ndef _sayhello(serport):\n    hellopacket = b\"\\x14\\x05\\x04\\x00\\x6a\\x39\\x57\\x64\"\n\n    tries = 5\n    while True:\n        LOG.debug(\"Sending hello packet\")\n        _send_command(serport, hellopacket)\n        o = _receive_reply(serport)\n        if (o):\n            break\n        tries -= 1\n        if tries == 0:\n            LOG.warning(\"Failed to initialise radio\")\n            raise errors.RadioError(\"Failed to initialize radio\")\n    firmware = _getstring(o, 4, 16)\n    LOG.info(\"Found firmware: %s\" % firmware)\n    return firmware\n\n\ndef _readmem(serport, offset, length):\n    LOG.debug(\"Sending readmem offset=0x%4.4x len=0x%4.4x\" % (offset, length))\n\n    readmem = b\"\\x1b\\x05\\x08\\x00\" + \\\n        struct.pack(\"<HBB\", offset, length, 0) + \\\n        b\"\\x6a\\x39\\x57\\x64\"\n    _send_command(serport, readmem)\n    o = _receive_reply(serport)\n    if DEBUG_SHOW_MEMORY_ACTIONS:\n        LOG.debug(\"readmem Received data len=0x%4.4x:\\n%s\" %\n                  (len(o), util.hexprint(o)))\n    return o[8:]\n\n\ndef _read_add_mem(serport, offset, length, add: list):\n    LOG.debug(\n        \"Sending read_add_mem offset=0x%4.4x len=0x%4.4x add=[0x%4.4x, 0x%4.4x]\" % (offset, length, add[0], add[1]))\n\n    readmem = b\"\\x2b\\x05\\x08\\x00\" + \\\n              struct.pack(\"<HBB\", offset, length, 0) + \\\n              b\"\\x6a\\x39\\x57\\x64\" + \\\n              struct.pack(\"<BB\", add[0], add[1])\n    _send_command(serport, readmem)\n    o = _receive_reply(serport)\n    if DEBUG_SHOW_MEMORY_ACTIONS:\n        LOG.debug(\"read_add_mem Received data len=0x%4.4x:\\n%s\" %\n                  (len(o), util.hexprint(o)))\n    return o[8:]\n\n\ndef _write_add_mem(serport, offset, add, data):\n    length = len(data) + len(add)\n    LOG.debug(\"Sending write_add_mem offset=0x%4.4x len=0x%4.4x add=[0x%4.4x, 0x%4.4x]\" %\n              (offset, length, add[0], add[1]))\n\n    if DEBUG_SHOW_MEMORY_ACTIONS:\n        LOG.debug(\"write_add_mem sent data offset=0x%4.4x len=0x%4.4x add=[0x%4.4x, 0x%4.4x]:\\n%s\" %\n                  (offset, length, add[0], add[1], util.hexprint(data)))\n\n    writemem = b\"\\x38\\x05\\x1c\\x00\" + \\\n        struct.pack(\"<HBB\", offset, length, 0) + \\\n        b\"\\x6a\\x39\\x57\\x64\" + \\\n        struct.pack(\"<BB\", add[0], add[1]) + data\n\n    _send_command(serport, writemem)\n    o = _receive_reply(serport)\n\n    LOG.debug(\"write_add_mem Received data: %s len=%i\" % (util.hexprint(o), len(o)))\n\n    if (o[0] == 0x1e\n            and\n            o[4] == (offset & 0xff)\n            and\n            o[5] == (offset >> 8) & 0xff):\n        return True\n    else:\n        LOG.warning(\"Bad data from write_add_mem\")\n        raise errors.RadioError(\"Bad response to write_add_mem\")\n\n\ndef _writemem(serport, data, offset):\n    LOG.debug(\"Sending writemem offset=0x%4.4x len=0x%4.4x\" %\n              (offset, len(data)))\n\n    if DEBUG_SHOW_MEMORY_ACTIONS:\n        LOG.debug(\"writemem sent data offset=0x%4.4x len=0x%4.4x:\\n%s\" %\n                  (offset, len(data), util.hexprint(data)))\n\n    dlen = len(data)\n    writemem = b\"\\x1d\\x05\" + \\\n        struct.pack(\"<BBHBB\", dlen+8, 0, offset, dlen, 1) + \\\n        b\"\\x6a\\x39\\x57\\x64\"+data\n\n    _send_command(serport, writemem)\n    o = _receive_reply(serport)\n\n    LOG.debug(\"writemem Received data: %s len=%i\" % (util.hexprint(o), len(o)))\n\n    if (o[0] == 0x1e\n            and\n            o[4] == (offset & 0xff)\n            and\n            o[5] == (offset >> 8) & 0xff):\n        return True\n    else:\n        LOG.warning(\"Bad data from writemem\")\n        raise errors.RadioError(\"Bad response to writemem\")\n\n\ndef _resetradio(serport):\n    resetpacket = b\"\\xdd\\x05\\x00\\x00\"\n    _send_command(serport, resetpacket)\n\n\ndef do_download(radio):\n    serport = radio.pipe\n    serport.timeout = 0.5\n    status = chirp_common.Status()\n    status.cur = 0\n    status.max = MEM_SIZE\n    status.msg = \"Downloading from radio\"\n    radio.status_fn(status)\n\n    eeprom = b\"\"\n    f = _sayhello(serport)\n    if f:\n        radio.FIRMWARE_VERSION = f\n    else:\n        raise errors.RadioError('Unable to determine firmware version')\n\n    addr = 0\n    while addr < MEM_SIZE:\n        o = _readmem(serport, addr, MEM_BLOCK)\n        status.cur = addr\n        radio.status_fn(status)\n\n        if o and len(o) == MEM_BLOCK:\n            eeprom += o\n            addr += MEM_BLOCK\n        else:\n            raise errors.RadioError(\"Memory download incomplete\")\n\n    return memmap.MemoryMapBytes(eeprom)\n\n\ndef do_add_download(radio):\n    serport = radio.pipe\n    serport.timeout = 0.5\n    status = chirp_common.Status()\n    status.cur = 0\n    status.max = 3\n    status.msg = \"Downloading added data from radio\"\n    radio.status_fn(status)\n\n    f = _sayhello(serport)\n    if f:\n        radio.FIRMWARE_VERSION = f\n    else:\n        raise errors.RadioError('Unable to determine firmware version')\n\n    welcome_len = _read_add_mem(serport, 0x01, 0x02, [0x1E, 0xE3])\n    status.cur = 1\n    radio.status_fn(status)\n    welcome_len1, welcome_len2 = welcome_len\n    if welcome_len1 > 18:\n        welcome_len1 = 18\n    if welcome_len2 > 18:\n        welcome_len2 = 18\n    welcome_text_1 = _read_add_mem(serport, 0x01, welcome_len1, [0x20, 0xE3])\n    status.cur = 2\n    radio.status_fn(status)\n    welcome_text_2 = _read_add_mem(serport, 0x01, welcome_len2, [0x33, 0xE3])\n    status.cur = 3\n    radio.status_fn(status)\n    return [welcome_text_1, welcome_text_2]\n\n\ndef do_upload(radio):\n    serport = radio.pipe\n    serport.timeout = 0.5\n    status = chirp_common.Status()\n    status.cur = 0\n    status.max = PROG_SIZE\n    status.msg = \"Uploading to radio\"\n    radio.status_fn(status)\n\n    f = _sayhello(serport)\n    if f:\n        radio.FIRMWARE_VERSION = f\n    else:\n        return False\n\n    addr = 0\n    while addr < PROG_SIZE:\n        o = radio.get_mmap()[addr:addr+MEM_BLOCK]\n        _writemem(serport, o, addr)\n        status.cur = addr\n        radio.status_fn(status)\n        if o:\n            addr += MEM_BLOCK\n        else:\n            raise errors.RadioError(\"Memory upload incomplete\")\n    status.msg = \"Uploaded OK\"\n\n    return True\n\n\ndef do_add_upload(radio):\n    serport = radio.pipe\n    serport.timeout = 0.5\n    status = chirp_common.Status()\n    status.cur = 0\n    status.max = 15\n    status.msg = \"Uploading add data to radio\"\n    radio.status_fn(status)\n\n    f = _sayhello(serport)\n    if f:\n        radio.FIRMWARE_VERSION = f\n    else:\n        return False\n\n    welcome_logo = radio.get_welcome_logo()\n    _write_add_mem(serport, 0x01, [0x1E, 0xE3], bytes([len(x) for x in welcome_logo]))\n    status.cur += 1\n    radio.status_fn(status)\n    _write_add_mem(serport, 0x01, [0x20, 0xE3], b'\\x00' * 18)\n    _write_add_mem(serport, 0x01, [0x20, 0xE3], welcome_logo[0])\n    status.cur += 1\n    radio.status_fn(status)\n    _write_add_mem(serport, 0x01, [0x33, 0xE3], b'\\x00' * 18)\n    _write_add_mem(serport, 0x01, [0x33, 0xE3], welcome_logo[1])\n    status.cur += 1\n    radio.status_fn(status)\n\n    addr = 0x1D00\n    _memobj = radio.get_memobj()\n    _write_add_mem(serport, 0x0, struct.pack(\"<H\", 0x1fff), _memobj.mdc_num.get_raw())\n    status.cur += 1\n    radio.status_fn(status)\n    for i in range(1, 23):\n        mdc_id = _memobj.mdccontact1[i - 1].id\n        mdc_name = _memobj.mdccontact1[i - 1].name\n        data = mdc_id.get_raw() + mdc_name.get_raw()\n        _write_add_mem(serport, 0x0, struct.pack(\"<H\", addr), data)\n        addr += 0x10\n        status.cur += 1\n        radio.status_fn(status)\n        if i==16:\n              addr=0x1f90\n    status.msg = \"Uploaded OK\"\n\n    return True\n\n\ndef _find_band(nolimits, hz):\n    mhz = hz/1000000.0\n    if nolimits:\n        B = BANDS_NOLIMITS\n    else:\n        B = BANDS\n\n    # currently the hacked firmware sets band=1 below 50 MHz\n    if nolimits and mhz < 50.0:\n        return 1\n\n    for a in B:\n        if mhz >= B[a][0] and mhz <= B[a][1]:\n            return a\n    return False\n\n\n@directory.register\nclass UVK5Radio(chirp_common.CloneModeRadio):\n    \"\"\"Quansheng UV-K5\"\"\"\n    VENDOR = \"Quansheng\"\n    MODEL = \"UV-K5 (cn)\"\n    BAUD_RATE = 38400\n    NEEDS_COMPAT_SERIAL = False\n    FIRMWARE_VERSION = \"\"\n    _expanded_limits = False\n\n    def __init__(self, pipe):\n          super().__init__(pipe)\n          self._welcome_logo = [b'', b'']\n\n    def get_prompts(x=None):\n        rp = chirp_common.RadioPrompts()\n        rp.experimental = _(\n            'This is an experimental driver for the Quansheng UV-K5. '\n            'It may harm your radio, or worse. Use at your own risk.\\n\\n'\n            'Before attempting to do any changes please download '\n            'the memory image from the radio with chirp '\n            'and keep it. This can be later used to recover the '\n            'original settings. \\n\\n'\n            'some details are not yet implemented')\n        rp.pre_download = _(\n            \"1. Turn radio on.\\n\"\n            \"2. Connect cable to mic/spkr connector.\\n\"\n            \"3. Make sure connector is firmly connected.\\n\"\n            \"4. Click OK to download image from device.\\n\\n\"\n            \"It will may not work if you turn on the radio \"\n            \"with the cable already attached\\n\")\n        rp.pre_upload = _(\n            \"1. Turn radio on.\\n\"\n            \"2. Connect cable to mic/spkr connector.\\n\"\n            \"3. Make sure connector is firmly connected.\\n\"\n            \"4. Click OK to upload the image to device.\\n\\n\"\n            \"It will may not work if you turn on the radio \"\n            \"with the cable already attached\")\n        return rp\n\n    # Return information about this radio's features, including\n    # how many memories it has, what bands it supports, etc\n    def get_features(self):\n        rf = chirp_common.RadioFeatures()\n        rf.has_bank = False\n        rf.valid_dtcs_codes = DTCS_CODES\n        rf.has_rx_dtcs = True\n        rf.has_ctone = True\n        rf.has_settings = True\n        rf.has_comment = False\n        rf.valid_name_length = 10\n        rf.valid_power_levels = UVK5_POWER_LEVELS\n        rf.valid_special_chans = list(SPECIALS.keys())\n        rf.valid_duplexes = [\"\", \"-\", \"+\", \"off\"]\n\n        # hack so we can input any frequency,\n        # the 0.1 and 0.01 steps don't work unfortunately\n        rf.valid_tuning_steps = [0.01, 0.1, 1.0] + STEPS\n\n        rf.valid_tmodes = [\"\", \"Tone\", \"TSQL\", \"DTCS\", \"Cross\"]\n        rf.valid_cross_modes = [\"Tone->Tone\", \"Tone->DTCS\", \"DTCS->Tone\",\n                                \"->Tone\", \"->DTCS\", \"DTCS->\", \"DTCS->DTCS\"]\n\n        rf.valid_characters = VALID_CHARACTERS\n        rf.valid_modes = [\"FM\", \"NFM\", \"AM\", \"NAM\"]\n        rf.valid_tmodes = [\"\", \"Tone\", \"TSQL\", \"DTCS\", \"Cross\"]\n\n        rf.valid_skips = [\"\"]\n\n        # This radio supports memories 1-200, 201-214 are the VFO memories\n        rf.memory_bounds = (1, 200)\n\n        rf.valid_bands = []\n        for a in BANDS_NOLIMITS:\n            rf.valid_bands.append(\n                    (int(BANDS_NOLIMITS[a][0]*1000000),\n                     int(BANDS_NOLIMITS[a][1]*1000000)))\n        return rf\n\n    # Do a download of the radio from the serial port\n    def sync_in(self):\n        self._mmap = do_download(self)\n        self._welcome_logo = do_add_download(self)\n        self.process_mmap()\n\n    # Do an upload of the radio to the serial port\n    def sync_out(self):\n        do_upload(self)\n        do_add_upload(self)\n        _resetradio(self.pipe)\n\n    # Convert the raw byte array into a memory object structure\n    def process_mmap(self):\n        self._memobj = bitwise.parse(MEM_FORMAT, self._mmap)\n\n    # Return a raw representation of the memory object, which\n    # is very helpful for development\n    def get_raw_memory(self, number):\n        return repr(self._memobj.channel[number-1])\n\n    def get_welcome_logo(self):\n        return self._welcome_logo\n\n    def validate_memory(self, mem):\n        msgs = super().validate_memory(mem)\n\n        if mem.duplex == 'off':\n            return msgs\n\n        # find tx frequency\n        if mem.duplex == '-':\n            txfreq = mem.freq - mem.offset\n        elif mem.duplex == '+':\n            txfreq = mem.freq + mem.offset\n        else:\n            txfreq = mem.freq\n\n        # find band\n        band = _find_band(self._expanded_limits, txfreq)\n        if band is False:\n            msg = \"Transmit frequency %.4f MHz is not supported by this radio\"\\\n                   % (txfreq/1000000.0)\n            msgs.append(chirp_common.ValidationError(msg))\n\n        band = _find_band(self._expanded_limits, mem.freq)\n        if band is False:\n            msg = \"The frequency %.4f MHz is not supported by this radio\" \\\n                   % (mem.freq/1000000.0)\n            msgs.append(chirp_common.ValidationError(msg))\n\n        return msgs\n\n    def _set_tone(self, mem, _mem):\n        ((txmode, txtone, txpol),\n         (rxmode, rxtone, rxpol)) = chirp_common.split_tone_encode(mem)\n\n        if txmode == \"Tone\":\n            txtoval = CTCSS_TONES.index(txtone)\n            txmoval = 0b01\n        elif txmode == \"DTCS\":\n            txmoval = txpol == \"R\" and 0b11 or 0b10\n            txtoval = DTCS_CODES.index(txtone)\n        else:\n            txmoval = 0\n            txtoval = 0\n\n        if rxmode == \"Tone\":\n            rxtoval = CTCSS_TONES.index(rxtone)\n            rxmoval = 0b01\n        elif rxmode == \"DTCS\":\n            rxmoval = rxpol == \"R\" and 0b11 or 0b10\n            rxtoval = DTCS_CODES.index(rxtone)\n        else:\n            rxmoval = 0\n            rxtoval = 0\n\n        _mem.rxcodeflag = rxmoval\n        _mem.txcodeflag = txmoval\n        _mem.unknown1 = 0\n        _mem.unknown2 = 0\n        _mem.rxcode = rxtoval\n        _mem.txcode = txtoval\n\n    def _get_tone(self, mem, _mem):\n        rxtype = _mem.rxcodeflag\n        txtype = _mem.txcodeflag\n        rx_tmode = TMODES[rxtype]\n        tx_tmode = TMODES[txtype]\n\n        rx_tone = tx_tone = None\n\n        if tx_tmode == \"Tone\":\n            if _mem.txcode < len(CTCSS_TONES):\n                tx_tone = CTCSS_TONES[_mem.txcode]\n            else:\n                tx_tone = 0\n                tx_tmode = \"\"\n        elif tx_tmode == \"DTCS\":\n            if _mem.txcode < len(DTCS_CODES):\n                tx_tone = DTCS_CODES[_mem.txcode]\n            else:\n                tx_tone = 0\n                tx_tmode = \"\"\n\n        if rx_tmode == \"Tone\":\n            if _mem.rxcode < len(CTCSS_TONES):\n                rx_tone = CTCSS_TONES[_mem.rxcode]\n            else:\n                rx_tone = 0\n                rx_tmode = \"\"\n        elif rx_tmode == \"DTCS\":\n            if _mem.rxcode < len(DTCS_CODES):\n                rx_tone = DTCS_CODES[_mem.rxcode]\n            else:\n                rx_tone = 0\n                rx_tmode = \"\"\n\n        tx_pol = txtype == 0x03 and \"R\" or \"N\"\n        rx_pol = rxtype == 0x03 and \"R\" or \"N\"\n\n        chirp_common.split_tone_decode(mem, (tx_tmode, tx_tone, tx_pol),\n                                       (rx_tmode, rx_tone, rx_pol))\n\n    # Extract a high-level memory object from the low-level memory map\n    # This is called to populate a memory in the UI\n    def get_memory(self, number2):\n\n        mem = chirp_common.Memory()\n\n        if isinstance(number2, str):\n            number = SPECIALS[number2]\n            mem.extd_number = number2\n        else:\n            number = number2 - 1\n\n        mem.number = number + 1\n\n        _mem = self._memobj.channel[number]\n\n        tmpcomment = \"\"\n\n        is_empty = False\n        # We'll consider any blank (i.e. 0 MHz frequency) to be empty\n        if (_mem.freq == 0xffffffff) or (_mem.freq == 0):\n            is_empty = True\n\n        tmpscn = SCANLIST_LIST[0]\n\n        # We'll also look at the channel attributes if a memory has them\n        if number < 200:\n            _mem3 = self._memobj.channel_attributes[number]\n            # free memory bit\n            if _mem3.is_free > 0:\n                is_empty = True\n            # scanlists\n            if _mem3.is_scanlist1 > 0 and _mem3.is_scanlist2 > 0:\n                tmpscn = SCANLIST_LIST[3]  # \"1+2\"\n            elif _mem3.is_scanlist1 > 0:\n                tmpscn = SCANLIST_LIST[1]  # \"1\"\n            elif _mem3.is_scanlist2 > 0:\n                tmpscn = SCANLIST_LIST[2]  # \"2\"\n\n        if is_empty:\n            mem.empty = True\n            # set some sane defaults:\n            mem.power = UVK5_POWER_LEVELS[2]\n            mem.extra = RadioSettingGroup(\"Extra\", \"extra\")\n            rs = RadioSetting(\n                \"bclo\", \"BCLO\",\n                RadioSettingValueBoolean(False))\n            mem.extra.append(rs)\n            rs = RadioSetting(\n                \"frev\", \"FreqRev\",\n                RadioSettingValueBoolean(False))\n            mem.extra.append(rs)\n            rs = RadioSetting(\n                \"pttid\", \"PTTID\",\n                RadioSettingValueList(PTTID_LIST, PTTID_LIST[0]))\n            mem.extra.append(rs)\n            rs = RadioSetting(\n                \"dtmfdecode\", _(\"DTMF decode\"),\n                RadioSettingValueBoolean(False))\n            mem.extra.append(rs)\n            rs = RadioSetting(\n                \"scrambler\", _(\"Scrambler\"),\n                RadioSettingValueList(SCRAMBLER_LIST, SCRAMBLER_LIST[0]))\n            mem.extra.append(rs)\n\n            rs = RadioSetting(\n                \"scanlists\", _(\"Scanlists\"),\n                RadioSettingValueList(SCANLIST_LIST, SCANLIST_LIST[0]))\n            mem.extra.append(rs)\n\n            # actually the step and duplex are overwritten by chirp based on\n            # bandplan. they are here to document sane defaults for IARU r1\n            # mem.tuning_step = 25.0\n            # mem.duplex = \"\"\n\n            return mem\n\n        if number > 199:\n            mem.immutable = [\"name\", \"scanlists\"]\n        else:\n            _mem2 = self._memobj.channelname[number]\n            raw_bytes = _mem2.get_raw()\n            mem.name = convert_bytes_to_chinese(raw_bytes).rstrip()\n\n        # Convert your low-level frequency to Hertz\n        mem.freq = int(_mem.freq)*10\n        mem.offset = int(_mem.offset)*10\n\n        if (mem.offset == 0):\n            mem.duplex = ''\n        else:\n            if _mem.shift == FLAGS1_OFFSET_MINUS:\n                if _mem.freq == _mem.offset:\n                    # fake tx disable by setting tx to 0 MHz\n                    mem.duplex = 'off'\n                    mem.offset = 0\n                else:\n                    mem.duplex = '-'\n            elif _mem.shift == FLAGS1_OFFSET_PLUS:\n                mem.duplex = '+'\n            else:\n                mem.duplex = ''\n\n        # tone data\n        self._get_tone(mem, _mem)\n\n        # mode\n        if _mem.enable_am > 0:\n            if _mem.bandwidth > 0:\n                mem.mode = \"NAM\"\n            else:\n                mem.mode = \"AM\"\n        else:\n            if _mem.bandwidth > 0:\n                mem.mode = \"NFM\"\n            else:\n                mem.mode = \"FM\"\n\n        # tuning step\n        tstep = _mem.step & 0x7\n        if tstep < len(STEPS):\n            mem.tuning_step = STEPS[tstep]\n        else:\n            mem.tuning_step = 2.5\n\n        # power\n        if _mem.txpower == POWER_HIGH:\n            mem.power = UVK5_POWER_LEVELS[2]\n        elif _mem.txpower == POWER_MEDIUM:\n            mem.power = UVK5_POWER_LEVELS[1]\n        else:\n            mem.power = UVK5_POWER_LEVELS[0]\n\n        # We'll consider any blank (i.e. 0 MHz frequency) to be empty\n        if (_mem.freq == 0xffffffff) or (_mem.freq == 0):\n            mem.empty = True\n        else:\n            mem.empty = False\n\n        mem.extra = RadioSettingGroup(\"Extra\", \"extra\")\n\n        # BCLO\n        is_bclo = bool(_mem.bclo > 0)\n        rs = RadioSetting(\"bclo\", \"BCLO\", RadioSettingValueBoolean(is_bclo))\n        mem.extra.append(rs)\n        tmpcomment += \"BCLO:\"+(is_bclo and \"ON\" or \"off\")+\" \"\n\n        # Frequency reverse - whatever that means, don't see it in the manual\n        is_frev = bool(_mem.freq_reverse > 0)\n        rs = RadioSetting(\"frev\", \"FreqRev\", RadioSettingValueBoolean(is_frev))\n        mem.extra.append(rs)\n        tmpcomment += \"FreqReverse:\"+(is_frev and \"ON\" or \"off\")+\" \"\n\n        # PTTID\n        pttid = _mem.dtmf_pttid\n        rs = RadioSetting(\"pttid\", \"PTTID\", RadioSettingValueList(\n            PTTID_LIST, PTTID_LIST[pttid]))\n        mem.extra.append(rs)\n        tmpcomment += \"PTTid:\"+PTTID_LIST[pttid]+\" \"\n\n        # DTMF DECODE\n        is_dtmf = bool(_mem.dtmf_decode > 0)\n        rs = RadioSetting(\"dtmfdecode\", _(\"DTMF decode\"),\n                          RadioSettingValueBoolean(is_dtmf))\n        mem.extra.append(rs)\n        tmpcomment += \"DTMFdecode:\"+(is_dtmf and \"ON\" or \"off\")+\" \"\n\n        # Scrambler\n        if _mem.scrambler & 0x0f < len(SCRAMBLER_LIST):\n            enc = _mem.scrambler & 0x0f\n        else:\n            enc = 0\n\n        rs = RadioSetting(\"scrambler\", _(\"Scrambler\"), RadioSettingValueList(\n            SCRAMBLER_LIST, SCRAMBLER_LIST[enc]))\n        mem.extra.append(rs)\n        tmpcomment += \"Scrambler:\"+SCRAMBLER_LIST[enc]+\" \"\n\n        rs = RadioSetting(\"scanlists\", _(\"Scanlists\"), RadioSettingValueList(\n            SCANLIST_LIST, tmpscn))\n        mem.extra.append(rs)\n\n        return mem\n\n    def set_settings(self, settings):\n        _mem = self._memobj\n        for element in settings:\n            if not isinstance(element, RadioSetting):\n                self.set_settings(element)\n                continue\n\n            # basic settings\n\n            # call channel\n            if element.get_name() == \"call_channel\":\n                _mem.call_channel = int(element.value)-1\n\n            # squelch\n            if element.get_name() == \"squelch\":\n                _mem.squelch = int(element.value)\n            # TOT\n            if element.get_name() == \"tot\":\n                _mem.max_talk_time = int(element.value)\n\n            # NOAA autoscan\n            if element.get_name() == \"noaa_autoscan\":\n                _mem.noaa_autoscan = element.value and 1 or 0\n\n            # VOX switch\n            if element.get_name() == \"vox_switch\":\n                _mem.vox_switch = element.value and 1 or 0\n\n            # vox level\n            if element.get_name() == \"vox_level\":\n                _mem.vox_level = int(element.value)-1\n\n            # mic gain\n            if element.get_name() == \"mic_gain\":\n                _mem.mic_gain = int(element.value)\n\n            # Channel display mode\n            if element.get_name() == \"channel_display_mode\":\n                _mem.channel_display_mode = CHANNELDISP_LIST.index(\n                    str(element.value))\n\n            # Crossband receiving/transmitting\n            if element.get_name() == \"crossband\":\n                _mem.crossband = CROSSBAND_LIST.index(str(element.value))\n\n            # Battery Save\n            if element.get_name() == \"battery_save\":\n                _mem.battery_save = BATSAVE_LIST.index(str(element.value))\n            # Dual Watch\n            if element.get_name() == \"dualwatch\":\n                _mem.dual_watch = DUALWATCH_LIST.index(str(element.value))\n\n            # Backlight auto mode\n            if element.get_name() == \"backlight_auto_mode\":\n                _mem.backlight_auto_mode = \\\n                        BACKLIGHT_LIST.index(str(element.value))\n\n            # Tail tone elimination\n            if element.get_name() == \"tail_note_elimination\":\n                _mem.tail_note_elimination = element.value and 1 or 0\n\n            # VFO Open\n            if element.get_name() == \"vfo_open\":\n                _mem.vfo_open = element.value and 1 or 0\n\n            # Beep control\n            if element.get_name() == \"beep_control\":\n                _mem.beep_control = element.value and 1 or 0\n\n            # Scan resume mode\n            if element.get_name() == \"scan_resume_mode\":\n                _mem.scan_resume_mode = SCANRESUME_LIST.index(\n                    str(element.value))\n\n            # Keypad lock\n            if element.get_name() == \"key_lock\":\n                _mem.key_lock = element.value and 1 or 0\n\n            # Auto keypad lock\n            if element.get_name() == \"auto_keypad_lock\":\n                _mem.auto_keypad_lock = element.value and 1 or 0\n\n            # Power on display mode\n            if element.get_name() == \"welcome_mode\":\n                _mem.power_on_dispmode = WELCOME_LIST.index(str(element.value))\n\n            # Keypad Tone\n            if element.get_name() == \"keypad_tone\":\n                _mem.keypad_tone = KEYPADTONE_LIST.index(str(element.value))\n\n            # Language\n            if element.get_name() == \"language\":\n                _mem.language = LANGUAGE_LIST.index(str(element.value))\n\n            # Alarm mode\n            if element.get_name() == \"alarm_mode\":\n                _mem.alarm_mode = ALARMMODE_LIST.index(str(element.value))\n\n            # Reminding of end of talk\n            if element.get_name() == \"reminding_of_end_talk\":\n                _mem.reminding_of_end_talk = REMENDOFTALK_LIST.index(\n                    str(element.value))\n\n            # Repeater tail tone elimination\n            if element.get_name() == \"repeater_tail_elimination\":\n                _mem.repeater_tail_elimination = RTE_LIST.index(\n                    str(element.value))\n\n            # Logo string 1\n            if element.get_name() == \"logo1\":\n                b = convert_chinese_to_ascii_chars(element.value).encode('latin-1')\n                self._welcome_logo[0] = b[0:18]\n\n            # Logo string 2\n            if element.get_name() == \"logo2\":\n                b = convert_chinese_to_ascii_chars(element.value).encode('latin-1')\n                self._welcome_logo[1] = b[0:18]\n\n            # unlock settings\n\n            # FLOCK\n            if element.get_name() == \"flock\":\n                _mem.lock.flock = FLOCK_LIST.index(str(element.value))\n\n            # 350TX\n            if element.get_name() == \"tx350\":\n                _mem.lock.tx350 = element.value and 1 or 0\n\n            # 200TX\n            if element.get_name() == \"tx200\":\n                _mem.lock.tx200 = element.value and 1 or 0\n\n            # 500TX\n            if element.get_name() == \"tx500\":\n                _mem.lock.tx500 = element.value and 1 or 0\n\n            # 350EN\n            if element.get_name() == \"en350\":\n                _mem.lock.en350 = element.value and 1 or 0\n\n            # SCREN\n            if element.get_name() == \"enscramble\":\n                _mem.lock.enscramble = element.value and 1 or 0\n\n            # KILLED\n            if element.get_name() == \"killed\":\n                _mem.lock.killed = element.value and 1 or 0\n\n            # fm radio\n            for i in range(1, 21):\n                freqname = \"FM_\" + str(i)\n                if element.get_name() == freqname:\n                    val = str(element.value).strip()\n                    try:\n                        val2 = int(float(val)*10)\n                    except Exception:\n                        val2 = 0xffff\n\n                    if val2 < FMMIN*10 or val2 > FMMAX*10:\n                        val2 = 0xffff\n#                        raise errors.InvalidValueError(\n#                                \"FM radio frequency should be a value \"\n#                                \"in the range %.1f - %.1f\" % (FMMIN , FMMAX))\n                    _mem.fmfreq[i-1] = val2\n\n            # dtmf settings\n            if element.get_name() == \"dtmf_side_tone\":\n                _mem.dtmf_settings.side_tone = \\\n                        element.value and 1 or 0\n\n            if element.get_name() == \"dtmf_separate_code\":\n                _mem.dtmf_settings.separate_code = str(element.value)\n\n            if element.get_name() == \"dtmf_group_call_code\":\n                _mem.dtmf_settings.group_call_code = element.value\n\n            if element.get_name() == \"dtmf_decode_response\":\n                _mem.dtmf_settings.decode_response = \\\n                        DTMF_DECODE_RESPONSE_LIST.index(str(element.value))\n\n            if element.get_name() == \"dtmf_auto_reset_time\":\n                _mem.dtmf_settings.auto_reset_time = \\\n                        int(int(element.value)/10)\n\n            if element.get_name() == \"dtmf_preload_time\":\n                _mem.dtmf_settings.preload_time = \\\n                        int(int(element.value)/10)\n\n            if element.get_name() == \"dtmf_first_code_persist_time\":\n                _mem.dtmf_settings.first_code_persist_time = \\\n                        int(int(element.value)/10)\n\n            if element.get_name() == \"dtmf_hash_persist_time\":\n                _mem.dtmf_settings.hash_persist_time = \\\n                        int(int(element.value)/10)\n\n            if element.get_name() == \"dtmf_code_persist_time\":\n                _mem.dtmf_settings.code_persist_time = \\\n                        int(int(element.value)/10)\n\n            if element.get_name() == \"dtmf_code_interval_time\":\n                _mem.dtmf_settings.code_interval_time = \\\n                        int(int(element.value)/10)\n\n            if element.get_name() == \"dtmf_permit_remote_kill\":\n                _mem.dtmf_settings.permit_remote_kill = \\\n                        element.value and 1 or 0\n\n            if element.get_name() == \"dtmf_dtmf_local_code\":\n                k = str(element.value).rstrip(\"\\x20\\xff\\x00\") + \"\\x00\"*3\n                _mem.dtmf_settings_numbers.dtmf_local_code = k[0:3]\n\n            if element.get_name() == \"dtmf_dtmf_up_code\":\n                k = str(element.value).strip(\"\\x20\\xff\\x00\") + \"\\x00\"*16\n                _mem.dtmf_settings_numbers.dtmf_up_code = k[0:16]\n\n            if element.get_name() == \"dtmf_dtmf_down_code\":\n                k = str(element.value).rstrip(\"\\x20\\xff\\x00\") + \"\\x00\"*16\n                _mem.dtmf_settings_numbers.dtmf_down_code = k[0:16]\n\n            if element.get_name() == \"dtmf_kill_code\":\n                k = str(element.value).strip(\"\\x20\\xff\\x00\") + \"\\x00\"*5\n                _mem.dtmf_settings_numbers.kill_code = k[0:5]\n\n            if element.get_name() == \"dtmf_revive_code\":\n                k = str(element.value).strip(\"\\x20\\xff\\x00\") + \"\\x00\"*5\n                _mem.dtmf_settings_numbers.revive_code = k[0:5]\n\n            # dtmf contacts\n            for i in range(1, 17):\n                varname = \"DTMF_\" + str(i)\n                if element.get_name() == varname:\n                    k = str(element.value).rstrip(\"\\x20\\xff\\x00\") + \"\\x00\"*8\n                    _mem.dtmfcontact[i-1].name = k[0:8]\n\n                varnumname = \"DTMFNUM_\" + str(i)\n                if element.get_name() == varnumname:\n                    k = str(element.value).rstrip(\"\\x20\\xff\\x00\") + \"\\xff\"*3\n                    _mem.dtmfcontact[i-1].number = k[0:3]\n\n            # MDC 联系人\n            element_name = element.get_name()\n            valid_mdc = 0\n            last_valid = 0\n            for i in range(1, 23):\n                mdc_id = \"MDC_ID_\" + str(i)\n                mdc_name = \"MDC_NAME_\" + str(i)\n                if element_name == mdc_id:\n                    k = str(element.value).replace(' ', '').rjust(4, '0')\n                    _mem.mdccontact1[i - 1].id = bytes.fromhex(k)[0:2]\n\n                if element_name == mdc_name:\n                    _mem.mdccontact1[i - 1].name = str(element.value)[0:14]\n\n                is_not_empty = _mem.mdccontact1[i - 1].id.get_raw() != b'\\x00' * 2 and _mem.mdccontact1[i - 1].name.get_raw() != b'\\x20' * 20\n                if is_not_empty and (last_valid == i - 1 or last_valid == 0):\n                    valid_mdc = i\n                    last_valid = i\n            _mem.mdc_num = valid_mdc\n\n            # scanlist stuff\n            if element.get_name() == \"scanlist_default\":\n                val = (int(element.value) == 2) and 1 or 0\n                _mem.scanlist_default = val\n\n            if element.get_name() == \"scanlist1_priority_scan\":\n                _mem.scanlist1_priority_scan = \\\n                        element.value and 1 or 0\n\n            if element.get_name() == \"scanlist2_priority_scan\":\n                _mem.scanlist2_priority_scan = \\\n                        element.value and 1 or 0\n\n            if element.get_name() == \"scanlist1_priority_ch1\" or \\\n                    element.get_name() == \"scanlist1_priority_ch2\" or \\\n                    element.get_name() == \"scanlist2_priority_ch1\" or \\\n                    element.get_name() == \"scanlist2_priority_ch2\":\n\n                val = int(element.value)\n\n                if val > 200 or val < 1:\n                    val = 0xff\n                else:\n                    val -= 1\n\n                if element.get_name() == \"scanlist1_priority_ch1\":\n                    _mem.scanlist1_priority_ch1 = val\n                if element.get_name() == \"scanlist1_priority_ch2\":\n                    _mem.scanlist1_priority_ch2 = val\n                if element.get_name() == \"scanlist2_priority_ch1\":\n                    _mem.scanlist2_priority_ch1 = val\n                if element.get_name() == \"scanlist2_priority_ch2\":\n                    _mem.scanlist2_priority_ch2 = val\n\n            if element.get_name() == \"key1_shortpress_action\":\n                _mem.key1_shortpress_action = KEYACTIONS_LIST.index(\n                        str(element.value))\n\n            if element.get_name() == \"key1_longpress_action\":\n                _mem.key1_longpress_action = KEYACTIONS_LIST.index(\n                        str(element.value))\n\n            if element.get_name() == \"key2_shortpress_action\":\n                _mem.key2_shortpress_action = KEYACTIONS_LIST.index(\n                        str(element.value))\n\n            if element.get_name() == \"key2_longpress_action\":\n                _mem.key2_longpress_action = KEYACTIONS_LIST.index(\n                        str(element.value))\n\n            if element.get_name() == \"nolimits\":\n                LOG.warning(\"User expanded band limits\")\n                self._expanded_limits = bool(element.value)\n\n    def get_settings(self):\n        _mem = self._memobj\n        basic = RadioSettingGroup(\"basic\", \"Basic Settings\")\n        keya = RadioSettingGroup(\"keya\", \"Programmable keys\")\n        dtmf = RadioSettingGroup(\"dtmf\", \"DTMF Settings\")\n        dtmfc = RadioSettingGroup(\"dtmfc\", \"DTMF Contacts\")\n        mdcc = RadioSettingGroup(\"mdcc\", \"MDC 联系人\")\n        scanl = RadioSettingGroup(\"scn\", \"Scan Lists\")\n        unlock = RadioSettingGroup(\"unlock\", \"Unlock Settings\")\n        fmradio = RadioSettingGroup(\"fmradio\", _(\"FM Radio\"))\n\n        roinfo = RadioSettingGroup(\"roinfo\", _(\"Driver information\"))\n\n        top = RadioSettings(\n                basic, keya, dtmf, dtmfc, mdcc, scanl, unlock, fmradio, roinfo)\n\n        # Programmable keys\n        tmpval = int(_mem.key1_shortpress_action)\n        if tmpval >= len(KEYACTIONS_LIST):\n            tmpval = 0\n        rs = RadioSetting(\"key1_shortpress_action\", \"Side key 1 short press\",\n                          RadioSettingValueList(\n                              KEYACTIONS_LIST, KEYACTIONS_LIST[tmpval]))\n        keya.append(rs)\n\n        tmpval = int(_mem.key1_longpress_action)\n        if tmpval >= len(KEYACTIONS_LIST):\n            tmpval = 0\n        rs = RadioSetting(\"key1_longpress_action\", \"Side key 1 long press\",\n                          RadioSettingValueList(\n                              KEYACTIONS_LIST, KEYACTIONS_LIST[tmpval]))\n        keya.append(rs)\n\n        tmpval = int(_mem.key2_shortpress_action)\n        if tmpval >= len(KEYACTIONS_LIST):\n            tmpval = 0\n        rs = RadioSetting(\"key2_shortpress_action\", \"Side key 2 short press\",\n                          RadioSettingValueList(\n                              KEYACTIONS_LIST, KEYACTIONS_LIST[tmpval]))\n        keya.append(rs)\n\n        tmpval = int(_mem.key2_longpress_action)\n        if tmpval >= len(KEYACTIONS_LIST):\n            tmpval = 0\n        rs = RadioSetting(\"key2_longpress_action\", \"Side key 2 long press\",\n                          RadioSettingValueList(\n                              KEYACTIONS_LIST, KEYACTIONS_LIST[tmpval]))\n        keya.append(rs)\n\n        # DTMF settings\n        tmppr = bool(_mem.dtmf_settings.side_tone > 0)\n        rs = RadioSetting(\n                \"dtmf_side_tone\",\n                \"DTMF Sidetone\",\n                RadioSettingValueBoolean(tmppr))\n        dtmf.append(rs)\n\n        tmpval = str(_mem.dtmf_settings.separate_code)\n        if tmpval not in DTMF_CODE_CHARS:\n            tmpval = '*'\n        val = RadioSettingValueString(1, 1, tmpval)\n        val.set_charset(DTMF_CODE_CHARS)\n        rs = RadioSetting(\"dtmf_separate_code\", \"Separate Code\", val)\n        dtmf.append(rs)\n\n        tmpval = str(_mem.dtmf_settings.group_call_code)\n        if tmpval not in DTMF_CODE_CHARS:\n            tmpval = '#'\n        val = RadioSettingValueString(1, 1, tmpval)\n        val.set_charset(DTMF_CODE_CHARS)\n        rs = RadioSetting(\"dtmf_group_call_code\", \"Group Call Code\", val)\n        dtmf.append(rs)\n\n        tmpval = _mem.dtmf_settings.decode_response\n        if tmpval >= len(DTMF_DECODE_RESPONSE_LIST):\n            tmpval = 0\n        rs = RadioSetting(\"dtmf_decode_response\", \"Decode Response\",\n                          RadioSettingValueList(\n                              DTMF_DECODE_RESPONSE_LIST,\n                              DTMF_DECODE_RESPONSE_LIST[tmpval]))\n        dtmf.append(rs)\n\n        tmpval = _mem.dtmf_settings.auto_reset_time\n        if tmpval > 60 or tmpval < 5:\n            tmpval = 5\n        rs = RadioSetting(\"dtmf_auto_reset_time\",\n                          \"Auto reset time (s)\",\n                          RadioSettingValueInteger(5, 60, tmpval))\n        dtmf.append(rs)\n\n        tmpval = int(_mem.dtmf_settings.preload_time)\n        if tmpval > 100 or tmpval < 3:\n            tmpval = 30\n        tmpval *= 10\n        rs = RadioSetting(\"dtmf_preload_time\",\n                          \"Pre-load time (ms)\",\n                          RadioSettingValueInteger(30, 1000, tmpval, 10))\n        dtmf.append(rs)\n\n        tmpval = int(_mem.dtmf_settings.first_code_persist_time)\n        if tmpval > 100 or tmpval < 3:\n            tmpval = 30\n        tmpval *= 10\n        rs = RadioSetting(\"dtmf_first_code_persist_time\",\n                          \"First code persist time (ms)\",\n                          RadioSettingValueInteger(30, 1000, tmpval, 10))\n        dtmf.append(rs)\n\n        tmpval = int(_mem.dtmf_settings.hash_persist_time)\n        if tmpval > 100 or tmpval < 3:\n            tmpval = 30\n        tmpval *= 10\n        rs = RadioSetting(\"dtmf_hash_persist_time\",\n                          \"#/* persist time (ms)\",\n                          RadioSettingValueInteger(30, 1000, tmpval, 10))\n        dtmf.append(rs)\n\n        tmpval = int(_mem.dtmf_settings.code_persist_time)\n        if tmpval > 100 or tmpval < 3:\n            tmpval = 30\n        tmpval *= 10\n        rs = RadioSetting(\"dtmf_code_persist_time\",\n                          \"Code persist time (ms)\",\n                          RadioSettingValueInteger(30, 1000, tmpval, 10))\n        dtmf.append(rs)\n\n        tmpval = int(_mem.dtmf_settings.code_interval_time)\n        if tmpval > 100 or tmpval < 3:\n            tmpval = 30\n        tmpval *= 10\n        rs = RadioSetting(\"dtmf_code_interval_time\",\n                          \"Code interval time (ms)\",\n                          RadioSettingValueInteger(30, 1000, tmpval, 10))\n        dtmf.append(rs)\n\n        tmpval = bool(_mem.dtmf_settings.permit_remote_kill > 0)\n        rs = RadioSetting(\n                \"dtmf_permit_remote_kill\",\n                \"Permit remote kill\",\n                RadioSettingValueBoolean(tmpval))\n        dtmf.append(rs)\n\n        tmpval = str(_mem.dtmf_settings_numbers.dtmf_local_code).upper().strip(\n                \"\\x00\\xff\\x20\")\n        for i in tmpval:\n            if i in DTMF_CHARS_ID:\n                continue\n            else:\n                tmpval = \"103\"\n                break\n        val = RadioSettingValueString(3, 3, tmpval)\n        val.set_charset(DTMF_CHARS_ID)\n        rs = RadioSetting(\"dtmf_dtmf_local_code\",\n                          \"Local code (3 chars 0-9 ABCD)\", val)\n        dtmf.append(rs)\n\n        tmpval = str(_mem.dtmf_settings_numbers.dtmf_up_code).upper().strip(\n                \"\\x00\\xff\\x20\")\n        for i in tmpval:\n            if i in DTMF_CHARS_UPDOWN or i == \"\":\n                continue\n            else:\n                tmpval = \"123\"\n                break\n        val = RadioSettingValueString(1, 16, tmpval)\n        val.set_charset(DTMF_CHARS_UPDOWN)\n        rs = RadioSetting(\"dtmf_dtmf_up_code\",\n                          \"Up code (1-16 chars 0-9 ABCD*#)\", val)\n        dtmf.append(rs)\n\n        tmpval = str(_mem.dtmf_settings_numbers.dtmf_down_code).upper().strip(\n                \"\\x00\\xff\\x20\")\n        for i in tmpval:\n            if i in DTMF_CHARS_UPDOWN:\n                continue\n            else:\n                tmpval = \"456\"\n                break\n        val = RadioSettingValueString(1, 16, tmpval)\n        val.set_charset(DTMF_CHARS_UPDOWN)\n        rs = RadioSetting(\"dtmf_dtmf_down_code\",\n                          \"Down code (1-16 chars 0-9 ABCD*#)\", val)\n        dtmf.append(rs)\n\n        tmpval = str(_mem.dtmf_settings_numbers.kill_code).upper().strip(\n                \"\\x00\\xff\\x20\")\n        for i in tmpval:\n            if i in DTMF_CHARS_KILL:\n                continue\n            else:\n                tmpval = \"77777\"\n                break\n        if not len(tmpval) == 5:\n            tmpval = \"77777\"\n        val = RadioSettingValueString(5, 5, tmpval)\n        val.set_charset(DTMF_CHARS_KILL)\n        rs = RadioSetting(\"dtmf_kill_code\",\n                          \"Kill code (5 chars 0-9 ABCD)\", val)\n        dtmf.append(rs)\n\n        tmpval = str(_mem.dtmf_settings_numbers.revive_code).upper().strip(\n                \"\\x00\\xff\\x20\")\n        for i in tmpval:\n            if i in DTMF_CHARS_KILL:\n                continue\n            else:\n                tmpval = \"88888\"\n                break\n        if not len(tmpval) == 5:\n            tmpval = \"88888\"\n        val = RadioSettingValueString(5, 5, tmpval)\n        val.set_charset(DTMF_CHARS_KILL)\n        rs = RadioSetting(\"dtmf_revive_code\",\n                          \"Revive code (5 chars 0-9 ABCD)\", val)\n        dtmf.append(rs)\n\n        val = RadioSettingValueString(0, 80,\n                                      \"All DTMF Contacts are 3 codes \"\n                                      \"(valid: 0-9 * # ABCD), \"\n                                      \"or an empty string\")\n        val.set_mutable(False)\n        rs = RadioSetting(\"dtmf_descr1\", \"DTMF Contacts\", val)\n        dtmfc.append(rs)\n\n        for i in range(1, 17):\n            varname = \"DTMF_\"+str(i)\n            varnumname = \"DTMFNUM_\"+str(i)\n            vardescr = \"DTMF Contact \"+str(i)+\" name\"\n            varinumdescr = \"DTMF Contact \"+str(i)+\" number\"\n\n            cntn = str(_mem.dtmfcontact[i-1].name).strip(\"\\x20\\x00\\xff\")\n            cntnum = str(_mem.dtmfcontact[i-1].number).strip(\"\\x20\\x00\\xff\")\n\n            val = RadioSettingValueString(0, 8, cntn)\n            rs = RadioSetting(varname, vardescr, val)\n            dtmfc.append(rs)\n\n            val = RadioSettingValueString(0, 3, cntnum)\n            val.set_charset(DTMF_CHARS)\n            rs = RadioSetting(varnumname, varinumdescr, val)\n            dtmfc.append(rs)\n\n        # MDC 联系人\n        val = RadioSettingValueString(0, 80,\n                                      \"MDC ID 应为 4位16进制数字 例如12AB, 联系人名称不能用中文, 请按顺序添加\", charset=VALID_CHARACTERS)\n        val.set_mutable(False)\n        rs = RadioSetting(\"mdc_descr1\", \"MDC 联系人\", val)\n        mdcc.append(rs)\n\n        for i in range(1, 23):\n            mdc_id = \"MDC_ID_\" + str(i)\n            mdc_name = \"MDC_NAME_\" + str(i)\n            mdc_id_descr = \"联系人\" + str(i) + \" | MDC ID\"\n            mdc_name_descr = \"联系人\" + str(i) + \" | 名称\"\n            if i <= int(_mem.mdc_num):\n                c_id = ''.join(['{:02X}'.format(int(byte)) for byte in _mem.mdccontact1[i - 1].id])\n                c_name = str(_mem.mdccontact1[i - 1].name)\n\n                val = RadioSettingValueString(0, 4, c_id, charset=' 0123456789ABCDEF')\n                rs = RadioSetting(mdc_id, mdc_id_descr, val)\n                mdcc.append(rs)\n\n                try:\n                    val = RadioSettingValueString(0, 14, c_name)\n                except Exception:\n                    val = RadioSettingValueString(0, 14, '')\n                rs = RadioSetting(mdc_name, mdc_name_descr, val)\n                mdcc.append(rs)\n            else:\n                val = RadioSettingValueString(0, 4, '', charset=' 0123456789ABCDEF')\n                rs = RadioSetting(mdc_id, mdc_id_descr, val)\n                mdcc.append(rs)\n\n                val = RadioSettingValueString(0, 14, '')\n                rs = RadioSetting(mdc_name, mdc_name_descr, val)\n                mdcc.append(rs)\n\n        # scanlists\n        if _mem.scanlist_default == 1:\n            tmpsc = 2\n        else:\n            tmpsc = 1\n        rs = RadioSetting(\"scanlist_default\",\n                          \"Default scanlist\",\n                          RadioSettingValueInteger(1, 2, tmpsc))\n        scanl.append(rs)\n\n        tmppr = bool((_mem.scanlist1_priority_scan & 1) > 0)\n        rs = RadioSetting(\n                \"scanlist1_priority_scan\",\n                \"Scanlist 1 priority channel scan\",\n                RadioSettingValueBoolean(tmppr))\n        scanl.append(rs)\n\n        tmpch = _mem.scanlist1_priority_ch1 + 1\n        if tmpch > 200:\n            tmpch = 0\n        rs = RadioSetting(\"scanlist1_priority_ch1\",\n                          \"Scanlist 1 priority channel 1 (0 - off)\",\n                          RadioSettingValueInteger(0, 200, tmpch))\n        scanl.append(rs)\n\n        tmpch = _mem.scanlist1_priority_ch2 + 1\n        if tmpch > 200:\n            tmpch = 0\n        rs = RadioSetting(\"scanlist1_priority_ch2\",\n                          \"Scanlist 1 priority channel 2 (0 - off)\",\n                          RadioSettingValueInteger(0, 200, tmpch))\n        scanl.append(rs)\n\n        tmppr = bool((_mem.scanlist2_priority_scan & 1) > 0)\n        rs = RadioSetting(\n                \"scanlist2_priority_scan\",\n                \"Scanlist 2 priority channel scan\",\n                RadioSettingValueBoolean(tmppr))\n        scanl.append(rs)\n\n        tmpch = _mem.scanlist2_priority_ch1 + 1\n        if tmpch > 200:\n            tmpch = 0\n        rs = RadioSetting(\"scanlist2_priority_ch1\",\n                          \"Scanlist 2 priority channel 1 (0 - off)\",\n                          RadioSettingValueInteger(0, 200, tmpch))\n        scanl.append(rs)\n\n        tmpch = _mem.scanlist2_priority_ch2 + 1\n        if tmpch > 200:\n            tmpch = 0\n        rs = RadioSetting(\"scanlist2_priority_ch2\",\n                          \"Scanlist 2 priority channel 2 (0 - off)\",\n                          RadioSettingValueInteger(0, 200, tmpch))\n        scanl.append(rs)\n\n        # basic settings\n\n        # call channel\n        tmpc = _mem.call_channel+1\n        if tmpc > 200:\n            tmpc = 1\n        rs = RadioSetting(\"call_channel\", \"One key call channel\",\n                          RadioSettingValueInteger(1, 200, tmpc))\n        basic.append(rs)\n\n        # squelch\n        tmpsq = _mem.squelch\n        if tmpsq > 9:\n            tmpsq = 1\n        rs = RadioSetting(\"squelch\", \"Squelch\",\n                          RadioSettingValueInteger(0, 9, tmpsq))\n        basic.append(rs)\n\n        # TOT\n        tmptot = _mem.max_talk_time\n        if tmptot > 10:\n            tmptot = 10\n        rs = RadioSetting(\n                \"tot\",\n                \"Max talk time [min]\",\n                RadioSettingValueInteger(0, 10, tmptot))\n        basic.append(rs)\n\n        # NOAA autoscan\n        rs = RadioSetting(\n                \"noaa_autoscan\",\n                \"NOAA Autoscan\", RadioSettingValueBoolean(\n                    bool(_mem.noaa_autoscan > 0)))\n        basic.append(rs)\n\n        # VOX switch\n        rs = RadioSetting(\n                \"vox_switch\",\n                \"VOX enabled\", RadioSettingValueBoolean(\n                    bool(_mem.vox_switch > 0)))\n        basic.append(rs)\n\n        # VOX Level\n        tmpvox = _mem.vox_level+1\n        if tmpvox > 10:\n            tmpvox = 10\n        rs = RadioSetting(\"vox_level\", \"VOX Level\",\n                          RadioSettingValueInteger(1, 10, tmpvox))\n        basic.append(rs)\n\n        # Mic gain\n        tmpmicgain = _mem.mic_gain\n        if tmpmicgain > 4:\n            tmpmicgain = 4\n        rs = RadioSetting(\"mic_gain\", \"Mic Gain\",\n                          RadioSettingValueInteger(0, 4, tmpmicgain))\n        basic.append(rs)\n\n        # Channel display mode\n        tmpchdispmode = _mem.channel_display_mode\n        if tmpchdispmode >= len(CHANNELDISP_LIST):\n            tmpchdispmode = 0\n        rs = RadioSetting(\n                \"channel_display_mode\",\n                \"Channel display mode\",\n                RadioSettingValueList(\n                    CHANNELDISP_LIST,\n                    CHANNELDISP_LIST[tmpchdispmode]))\n        basic.append(rs)\n\n        # Crossband receiving/transmitting\n        tmpcross = _mem.crossband\n        if tmpcross >= len(CROSSBAND_LIST):\n            tmpcross = 0\n        rs = RadioSetting(\n                \"crossband\",\n                \"Cross-band receiving/transmitting\",\n                RadioSettingValueList(\n                    CROSSBAND_LIST,\n                    CROSSBAND_LIST[tmpcross]))\n        basic.append(rs)\n\n        # Battery save\n        tmpbatsave = _mem.battery_save\n        if tmpbatsave >= len(BATSAVE_LIST):\n            tmpbatsave = BATSAVE_LIST.index(\"1:4\")\n        rs = RadioSetting(\n                \"battery_save\",\n                \"Battery Save\",\n                RadioSettingValueList(\n                    BATSAVE_LIST,\n                    BATSAVE_LIST[tmpbatsave]))\n        basic.append(rs)\n\n        # Dual watch\n        tmpdual = _mem.dual_watch\n        if tmpdual >= len(DUALWATCH_LIST):\n            tmpdual = 0\n        rs = RadioSetting(\"dualwatch\", \"Dual Watch\", RadioSettingValueList(\n            DUALWATCH_LIST, DUALWATCH_LIST[tmpdual]))\n        basic.append(rs)\n\n        # Backlight auto mode\n        tmpback = _mem.backlight_auto_mode\n        if tmpback >= len(BACKLIGHT_LIST):\n            tmpback = 0\n        rs = RadioSetting(\"backlight_auto_mode\",\n                          \"Backlight auto mode\",\n                          RadioSettingValueList(\n                              BACKLIGHT_LIST,\n                              BACKLIGHT_LIST[tmpback]))\n        basic.append(rs)\n\n        # Tail tone elimination\n        rs = RadioSetting(\n                \"tail_note_elimination\",\n                \"Tail tone elimination\",\n                RadioSettingValueBoolean(\n                    bool(_mem.tail_note_elimination > 0)))\n        basic.append(rs)\n\n        # VFO open\n        rs = RadioSetting(\"vfo_open\", \"VFO open\",\n                          RadioSettingValueBoolean(bool(_mem.vfo_open > 0)))\n        basic.append(rs)\n\n        # Beep control\n        rs = RadioSetting(\n                \"beep_control\",\n                \"Beep control\",\n                RadioSettingValueBoolean(bool(_mem.beep_control > 0)))\n        basic.append(rs)\n\n        # Scan resume mode\n        tmpscanres = _mem.scan_resume_mode\n        if tmpscanres >= len(SCANRESUME_LIST):\n            tmpscanres = 0\n        rs = RadioSetting(\n                \"scan_resume_mode\",\n                \"Scan resume mode\",\n                RadioSettingValueList(\n                    SCANRESUME_LIST,\n                    SCANRESUME_LIST[tmpscanres]))\n        basic.append(rs)\n\n        # Keypad locked\n        rs = RadioSetting(\n                \"key_lock\",\n                \"Keypad lock\",\n                RadioSettingValueBoolean(bool(_mem.key_lock > 0)))\n        basic.append(rs)\n\n        # Auto keypad lock\n        rs = RadioSetting(\n                \"auto_keypad_lock\",\n                \"Auto keypad lock\",\n                RadioSettingValueBoolean(bool(_mem.auto_keypad_lock > 0)))\n        basic.append(rs)\n\n        # Power on display mode\n        tmpdispmode = _mem.power_on_dispmode\n        if tmpdispmode >= len(WELCOME_LIST):\n            tmpdispmode = 0\n        rs = RadioSetting(\n                \"welcome_mode\",\n                \"Power on display mode\",\n                RadioSettingValueList(\n                    WELCOME_LIST,\n                    WELCOME_LIST[tmpdispmode]))\n        basic.append(rs)\n\n        # Keypad Tone\n        tmpkeypadtone = _mem.keypad_tone\n        if tmpkeypadtone >= len(KEYPADTONE_LIST):\n            tmpkeypadtone = 0\n        rs = RadioSetting(\"keypad_tone\", \"Keypad tone\", RadioSettingValueList(\n            KEYPADTONE_LIST, KEYPADTONE_LIST[tmpkeypadtone]))\n        basic.append(rs)\n\n        # Language\n        tmplanguage = _mem.language\n        if tmplanguage >= len(LANGUAGE_LIST):\n            tmplanguage = 0\n        rs = RadioSetting(\"language\", \"Language\", RadioSettingValueList(\n            LANGUAGE_LIST, LANGUAGE_LIST[tmplanguage]))\n        basic.append(rs)\n\n        # Alarm mode\n        tmpalarmmode = _mem.alarm_mode\n        if tmpalarmmode >= len(ALARMMODE_LIST):\n            tmpalarmmode = 0\n        rs = RadioSetting(\"alarm_mode\", \"Alarm mode\", RadioSettingValueList(\n            ALARMMODE_LIST, ALARMMODE_LIST[tmpalarmmode]))\n        basic.append(rs)\n\n        # Reminding of end of talk\n        tmpalarmmode = _mem.reminding_of_end_talk\n        if tmpalarmmode >= len(REMENDOFTALK_LIST):\n            tmpalarmmode = 0\n        rs = RadioSetting(\n                \"reminding_of_end_talk\",\n                \"Reminding of end of talk\",\n                RadioSettingValueList(\n                    REMENDOFTALK_LIST,\n                    REMENDOFTALK_LIST[tmpalarmmode]))\n        basic.append(rs)\n\n        # Repeater tail tone elimination\n        tmprte = _mem.repeater_tail_elimination\n        if tmprte >= len(RTE_LIST):\n            tmprte = 0\n        rs = RadioSetting(\n                \"repeater_tail_elimination\",\n                \"Repeater tail tone elimination\",\n                RadioSettingValueList(RTE_LIST, RTE_LIST[tmprte]))\n        basic.append(rs)\n\n        # Logo string 1\n        logo1 = convert_bytes_to_chinese(self._welcome_logo[0])\n        rs = RadioSetting(\"logo1\", _(\"欢迎字符1 (18字符)\"),\n                          RadioSettingChineseValueString(0, 18, logo1, False, VALID_CHARACTERS))\n        basic.append(rs)\n\n        # Logo string 2\n        logo2 = convert_bytes_to_chinese(self._welcome_logo[1])\n        rs = RadioSetting(\"logo2\", _(\"欢迎字符2 (18字符)\"),\n                          RadioSettingChineseValueString(0, 18, logo2, False, VALID_CHARACTERS))\n        basic.append(rs)\n\n        # FM radio\n        for i in range(1, 21):\n            freqname = \"FM_\"+str(i)\n            fmfreq = _mem.fmfreq[i-1]/10.0\n            if fmfreq < FMMIN or fmfreq > FMMAX:\n                rs = RadioSetting(freqname, freqname,\n                                  RadioSettingValueString(0, 5, \"\"))\n            else:\n                rs = RadioSetting(freqname, freqname,\n                                  RadioSettingValueString(0, 5, str(fmfreq)))\n\n            fmradio.append(rs)\n\n        # unlock settings\n\n        # F-LOCK\n        tmpflock = _mem.lock.flock\n        if tmpflock >= len(FLOCK_LIST):\n            tmpflock = 0\n        rs = RadioSetting(\n            \"flock\", \"F-LOCK\",\n            RadioSettingValueList(FLOCK_LIST, FLOCK_LIST[tmpflock]))\n        unlock.append(rs)\n\n        # 350TX\n        rs = RadioSetting(\"tx350\", \"350TX - unlock 350-400 MHz TX\",\n                          RadioSettingValueBoolean(\n                              bool(_mem.lock.tx350 > 0)))\n        unlock.append(rs)\n\n        # Killed\n        rs = RadioSetting(\"Killed\", \"KILLED Device was disabled (via DTMF)\",\n                          RadioSettingValueBoolean(\n                              bool(_mem.lock.killed > 0)))\n        unlock.append(rs)\n\n        # 200TX\n        rs = RadioSetting(\"tx200\", \"200TX - unlock 174-350 MHz TX\",\n                          RadioSettingValueBoolean(\n                              bool(_mem.lock.tx200 > 0)))\n        unlock.append(rs)\n\n        # 500TX\n        rs = RadioSetting(\"tx500\", \"500TX - unlock 500-600 MHz TX\",\n                          RadioSettingValueBoolean(\n                              bool(_mem.lock.tx500 > 0)))\n        unlock.append(rs)\n\n        # 350EN\n        rs = RadioSetting(\"en350\", \"350EN - unlock 350-400 MHz RX\",\n                          RadioSettingValueBoolean(\n                              bool(_mem.lock.en350 > 0)))\n        unlock.append(rs)\n\n        # SCREEN\n        rs = RadioSetting(\"scrambler\", \"SCREN - scrambler enable\",\n                          RadioSettingValueBoolean(\n                              bool(_mem.lock.enscramble > 0)))\n        unlock.append(rs)\n\n        # readonly info\n        # Firmware\n        if self.FIRMWARE_VERSION == \"\":\n            firmware = \"To get the firmware version please download\"\n            \"the image from the radio first\"\n        else:\n            firmware = self.FIRMWARE_VERSION\n\n        val = RadioSettingValueString(0, 128, firmware)\n        val.set_mutable(False)\n        rs = RadioSetting(\"fw_ver\", \"Firmware Version\", val)\n        roinfo.append(rs)\n\n        # No limits version for hacked firmware\n        val = RadioSettingValueBoolean(self._expanded_limits)\n        rs = RadioSetting(\"nolimits\", \"Limits disabled for modified firmware\",\n                          val)\n        rs.set_warning(_(\n            'This should only be enabled if you are using modified firmware '\n            'that supports wider frequency coverage. Enabling this will cause '\n            'CHIRP not to enforce OEM restrictions and may lead to undefined '\n            'or unregulated behavior. Use at your own risk!'),\n            safe_value=False)\n        roinfo.append(rs)\n\n        return top\n\n    # Store details about a high-level memory to the memory map\n    # This is called when a user edits a memory in the UI\n    def set_memory(self, mem):\n        number = mem.number-1\n\n        # Get a low-level memory object mapped to the image\n        _mem = self._memobj.channel[number]\n        _mem4 = self._memobj\n        # empty memory\n        if mem.empty:\n            _mem.set_raw(\"\\xFF\" * 16)\n            if number < 200:\n                _mem2 = self._memobj.channelname[number]\n                _mem2.set_raw(\"\\xFF\" * 16)\n                _mem4.channel_attributes[number].is_scanlist1 = 0\n                _mem4.channel_attributes[number].is_scanlist2 = 0\n                _mem4.channel_attributes[number].unknown1 = 0\n                _mem4.channel_attributes[number].unknown2 = 0\n                _mem4.channel_attributes[number].is_free = 1\n                _mem4.channel_attributes[number].band = 0x7\n            return mem\n\n        # clean the channel memory, restore some bits if it was used before\n        if _mem.get_raw(asbytes=False)[0] == \"\\xff\":\n            # this was an empty memory\n            _mem.set_raw(\"\\x00\" * 16)\n        else:\n            # this memory wasn't empty, save some bits that we don't know the\n            # meaning of, or that we don't support yet\n            prev_0a = _mem.get_raw()[0x0a] & SAVE_MASK_0A\n            prev_0b = _mem.get_raw()[0x0b] & SAVE_MASK_0B\n            prev_0c = _mem.get_raw()[0x0c] & SAVE_MASK_0C\n            prev_0d = _mem.get_raw()[0x0d] & SAVE_MASK_0D\n            prev_0e = _mem.get_raw()[0x0e] & SAVE_MASK_0E\n            prev_0f = _mem.get_raw()[0x0f] & SAVE_MASK_0F\n            _mem.set_raw(\"\\x00\" * 10 +\n                         chr(prev_0a) + chr(prev_0b) + chr(prev_0c) +\n                         chr(prev_0d) + chr(prev_0e) + chr(prev_0f))\n\n        if number < 200:\n            _mem4.channel_attributes[number].is_scanlist1 = 0\n            _mem4.channel_attributes[number].is_scanlist2 = 0\n            _mem4.channel_attributes[number].unknown1 = 0\n            _mem4.channel_attributes[number].unknown2 = 0\n            _mem4.channel_attributes[number].is_free = 1\n            _mem4.channel_attributes[number].band = 0x7\n\n        # find band\n        band = _find_band(self, mem.freq)\n\n        # mode\n        if mem.mode == \"NFM\":\n            _mem.bandwidth = 1\n            _mem.enable_am = 0\n        elif mem.mode == \"FM\":\n            _mem.bandwidth = 0\n            _mem.enable_am = 0\n        elif mem.mode == \"NAM\":\n            _mem.bandwidth = 1\n            _mem.enable_am = 1\n        elif mem.mode == \"AM\":\n            _mem.bandwidth = 0\n            _mem.enable_am = 1\n\n        # frequency/offset\n        _mem.freq = mem.freq/10\n        _mem.offset = mem.offset/10\n\n        if mem.duplex == \"\":\n            _mem.offset = 0\n            _mem.shift = 0\n        elif mem.duplex == '-':\n            _mem.shift = FLAGS1_OFFSET_MINUS\n        elif mem.duplex == '+':\n            _mem.shift = FLAGS1_OFFSET_PLUS\n        elif mem.duplex == 'off':\n            # we fake tx disable by setting the tx freq to 0 MHz\n            _mem.shift = FLAGS1_OFFSET_MINUS\n            _mem.offset = _mem.freq\n\n        # set band\n        if number < 200:\n            _mem4.channel_attributes[number].is_free = 0\n            _mem4.channel_attributes[number].band = band\n\n        # channels >200 are the 14 VFO chanells and don't have names\n        if number < 200:\n            _mem2 = self._memobj.channelname[number]\n            text = convert_chinese_to_ascii_chars(mem.name)\n            if len(text) < 16:\n                text += \"\\x00\" * (16-len(text))\n            elif len(text) >= 16:\n                text = text[:16]\n            _mem2.name = text  # Store the alpha tag\n\n        # tone data\n        self._set_tone(mem, _mem)\n\n        # step\n        _mem.step = STEPS.index(mem.tuning_step)\n\n        # tx power\n        if str(mem.power) == str(UVK5_POWER_LEVELS[2]):\n            _mem.txpower = POWER_HIGH\n        elif str(mem.power) == str(UVK5_POWER_LEVELS[1]):\n            _mem.txpower = POWER_MEDIUM\n        else:\n            _mem.txpower = POWER_LOW\n\n        for setting in mem.extra:\n            sname = setting.get_name()\n            svalue = setting.value.get_value()\n\n            if sname == \"bclo\":\n                _mem.bclo = svalue and 1 or 0\n\n            if sname == \"pttid\":\n                _mem.dtmf_pttid = PTTID_LIST.index(svalue)\n\n            if sname == \"frev\":\n                _mem.freq_reverse = svalue and 1 or 0\n\n            if sname == \"dtmfdecode\":\n                _mem.dtmf_decode = svalue and 1 or 0\n\n            if sname == \"scrambler\":\n                _mem.scrambler = (\n                    _mem.scrambler & 0xf0) | SCRAMBLER_LIST.index(svalue)\n\n            if number < 200 and sname == \"scanlists\":\n                if svalue == \"1\":\n                    _mem4.channel_attributes[number].is_scanlist1 = 1\n                    _mem4.channel_attributes[number].is_scanlist2 = 0\n                elif svalue == \"2\":\n                    _mem4.channel_attributes[number].is_scanlist1 = 0\n                    _mem4.channel_attributes[number].is_scanlist2 = 1\n                elif svalue == \"1+2\":\n                    _mem4.channel_attributes[number].is_scanlist1 = 1\n                    _mem4.channel_attributes[number].is_scanlist2 = 1\n                else:\n                    _mem4.channel_attributes[number].is_scanlist1 = 0\n                    _mem4.channel_attributes[number].is_scanlist2 = 0\n\n        return mem\n\n    def get_memobj(self):\n        return self._memobj"
  },
  {
    "path": "输入法/PINYIN.cpp",
    "content": "//\n// Created by RUPC on 2024/2/9.\n//\n#include \"PINYIN.h\"\n\n\nstruct PINYIN_T pin[399] {\n\n\n        {\"a     \",7,0x26B00},\n        {\"ai    \",23,0x26B0E},\n        {\"an    \",20,0x26B3C},\n        {\"ang   \",4,0x26B64},\n        {\"ao    \",23,0x26B6C},\n        {\"ba    \",24,0x26B9A},\n        {\"bai   \",12,0x26BCA},\n        {\"ban   \",20,0x26BE2},\n        {\"bang  \",14,0x26C0A},\n        {\"bao   \",27,0x26C26},\n        {\"bei   \",22,0x26C5C},\n        {\"ben   \",9,0x26C88},\n        {\"beng  \",9,0x26C9A},\n        {\"bi    \",57,0x26CAC},\n        {\"bian  \",25,0x26D1E},\n        {\"biao  \",15,0x26D50},\n        {\"bie   \",5,0x26D6E},\n        {\"bin   \",16,0x26D78},\n        {\"bing  \",14,0x26D98},\n        {\"bo    \",37,0x26DB4},\n        {\"bu    \",20,0x26DFE},\n        {\"ca    \",4,0x26E26},\n        {\"cai   \",11,0x26E2E},\n        {\"can   \",13,0x26E44},\n        {\"cang  \",6,0x26E5E},\n        {\"cao   \",9,0x26E6A},\n        {\"ce    \",6,0x26E7C},\n        {\"cen   \",3,0x26E88},\n        {\"ceng  \",4,0x26E8E},\n        {\"cha   \",23,0x26E96},\n        {\"chai  \",9,0x26EC4},\n        {\"chan  \",27,0x26ED6},\n        {\"chang \",27,0x26F0C},\n        {\"chao  \",15,0x26F42},\n        {\"che   \",9,0x26F60},\n        {\"chen  \",22,0x26F72},\n        {\"cheng \",28,0x26F9E},\n        {\"chi   \",38,0x26FD6},\n        {\"chong \",14,0x27022},\n        {\"chou  \",17,0x2703E},\n        {\"chu   \",28,0x27060},\n        {\"chuai \",6,0x27098},\n        {\"chuan \",13,0x270A4},\n        {\"chuang\",7,0x270BE},\n        {\"chui  \",9,0x270CC},\n        {\"chun  \",10,0x270DE},\n        {\"chuo  \",6,0x270F2},\n        {\"ci    \",19,0x270FE},\n        {\"cong  \",12,0x27124},\n        {\"cou   \",4,0x2713C},\n        {\"cu    \",12,0x27144},\n        {\"cuan  \",8,0x2715C},\n        {\"cui   \",15,0x2716C},\n        {\"cun   \",6,0x2718A},\n        {\"cuo   \",15,0x27196},\n        {\"da    \",18,0x271B4},\n        {\"dai   \",22,0x271D8},\n        {\"dan   \",27,0x27204},\n        {\"dang  \",12,0x2723A},\n        {\"dao   \",18,0x27252},\n        {\"de    \",6,0x27276},\n        {\"deng  \",14,0x27282},\n        {\"di    \",39,0x2729E},\n        {\"dia   \",1,0x272EC},\n        {\"dian  \",25,0x272EE},\n        {\"diao  \",14,0x27320},\n        {\"die   \",16,0x2733C},\n        {\"ding  \",19,0x2735C},\n        {\"diu   \",2,0x27382},\n        {\"dong  \",19,0x27386},\n        {\"dou   \",13,0x273AC},\n        {\"du    \",25,0x273C6},\n        {\"duan  \",9,0x273F8},\n        {\"dui   \",9,0x2740A},\n        {\"dun   \",17,0x2741C},\n        {\"duo   \",21,0x2743E},\n        {\"e     \",33,0x27468},\n        {\"en    \",3,0x274AA},\n        {\"er    \",14,0x274B0},\n        {\"fa    \",10,0x274CC},\n        {\"fan   \",24,0x274E0},\n        {\"fang  \",17,0x27510},\n        {\"fei   \",29,0x27532},\n        {\"fen   \",21,0x2756C},\n        {\"feng  \",21,0x27596},\n        {\"fo    \",1,0x275C0},\n        {\"fou   \",2,0x275C2},\n        {\"fu    \",83,0x275C6},\n        {\"ga    \",13,0x2766C},\n        {\"gai   \",12,0x27686},\n        {\"gan   \",24,0x2769E},\n        {\"gang  \",13,0x276CE},\n        {\"gao   \",19,0x276E8},\n        {\"ge    \",37,0x2770E},\n        {\"gei   \",1,0x27758},\n        {\"gen   \",6,0x2775A},\n        {\"geng  \",12,0x27766},\n        {\"gong  \",20,0x2777E},\n        {\"gou   \",22,0x277A6},\n        {\"gu    \",43,0x277D2},\n        {\"gua   \",12,0x27828},\n        {\"guai  \",4,0x27840},\n        {\"guan  \",20,0x27848},\n        {\"guang \",7,0x27870},\n        {\"gui   \",30,0x2787E},\n        {\"gun   \",7,0x278BA},\n        {\"guo   \",19,0x278C8},\n        {\"ha    \",4,0x278EE},\n        {\"hai   \",12,0x278F6},\n        {\"han   \",30,0x2790E},\n        {\"hang  \",10,0x2794A},\n        {\"hao   \",21,0x2795E},\n        {\"he    \",29,0x27988},\n        {\"hei   \",2,0x279C2},\n        {\"hen   \",4,0x279C6},\n        {\"heng  \",9,0x279CE},\n        {\"hong  \",17,0x279E0},\n        {\"hou   \",15,0x27A02},\n        {\"hu    \",47,0x27A20},\n        {\"hua   \",14,0x27A7E},\n        {\"huai  \",7,0x27A9A},\n        {\"huan  \",29,0x27AA8},\n        {\"huang \",20,0x27AE2},\n        {\"hui   \",40,0x27B0A},\n        {\"hun   \",11,0x27B5A},\n        {\"huo   \",21,0x27B70},\n        {\"ji    \",101,0x27B9A},\n        {\"jia   \",37,0x27C64},\n        {\"jian  \",69,0x27CAE},\n        {\"jiang \",24,0x27D38},\n        {\"jiao  \",47,0x27D68},\n        {\"jie   \",46,0x27DC6},\n        {\"jin   \",34,0x27E22},\n        {\"jing  \",41,0x27E66},\n        {\"jiong \",4,0x27EB8},\n        {\"jiu   \",27,0x27EC0},\n        {\"ju    \",55,0x27EF6},\n        {\"juan  \",16,0x27F64},\n        {\"jue   \",31,0x27F84},\n        {\"jun   \",16,0x27FC2},\n        {\"ka    \",7,0x27FE2},\n        {\"kai   \",13,0x27FF0},\n        {\"kan   \",14,0x2800A},\n        {\"kang  \",10,0x28026},\n        {\"kao   \",8,0x2803A},\n        {\"ke    \",35,0x2804A},\n        {\"ken   \",5,0x28090},\n        {\"keng  \",3,0x2809A},\n        {\"kong  \",7,0x280A0},\n        {\"kou   \",9,0x280AE},\n        {\"ku    \",12,0x280C0},\n        {\"kua   \",6,0x280D8},\n        {\"kuai  \",11,0x280E4},\n        {\"kuan  \",3,0x280FA},\n        {\"kuang \",16,0x28100},\n        {\"kui   \",28,0x28120},\n        {\"kun   \",11,0x28158},\n        {\"kuo   \",7,0x2816E},\n        {\"la    \",14,0x2817C},\n        {\"lai   \",12,0x28198},\n        {\"lan   \",22,0x281B0},\n        {\"lang  \",14,0x281DC},\n        {\"lao   \",20,0x281F8},\n        {\"le    \",8,0x28220},\n        {\"lei   \",20,0x28230},\n        {\"leng  \",5,0x28258},\n        {\"li    \",78,0x28262},\n        {\"lia   \",1,0x282FE},\n        {\"lian  \",26,0x28300},\n        {\"liang \",18,0x28334},\n        {\"liao  \",21,0x28358},\n        {\"lie   \",13,0x28382},\n        {\"lin   \",25,0x2839C},\n        {\"ling  \",28,0x283CE},\n        {\"liu   \",23,0x28406},\n        {\"long  \",18,0x28434},\n        {\"lou   \",16,0x28458},\n        {\"lu    \",36,0x28478},\n        {\"luan  \",11,0x284C0},\n        {\"lue   \",3,0x284D6},\n        {\"lun   \",8,0x284DC},\n        {\"luo   \",29,0x284EC},\n        {\"lv    \",21,0x28526},\n        {\"ma    \",16,0x28550},\n        {\"mai   \",9,0x28570},\n        {\"man   \",19,0x28582},\n        {\"mang  \",10,0x285A8},\n        {\"mao   \",26,0x285BC},\n        {\"me    \",2,0x285F0},\n        {\"mei   \",29,0x285F4},\n        {\"men   \",7,0x2862E},\n        {\"meng  \",20,0x2863C},\n        {\"mi    \",29,0x28664},\n        {\"mian  \",15,0x2869E},\n        {\"miao  \",16,0x286BC},\n        {\"mie   \",6,0x286DC},\n        {\"min   \",16,0x286E8},\n        {\"ming  \",13,0x28708},\n        {\"miu   \",2,0x28722},\n        {\"mo    \",37,0x28726},\n        {\"mou   \",9,0x28770},\n        {\"mu    \",24,0x28782},\n        {\"na    \",12,0x287B2},\n        {\"nai   \",11,0x287CA},\n        {\"nan   \",9,0x287E0},\n        {\"nang  \",5,0x287F2},\n        {\"nao   \",13,0x287FC},\n        {\"ne    \",5,0x28816},\n        {\"nei   \",4,0x28820},\n        {\"nen   \",2,0x28828},\n        {\"neng  \",1,0x2882C},\n        {\"ni    \",22,0x2882E},\n        {\"nian  \",14,0x2885A},\n        {\"niang \",2,0x28876},\n        {\"niao  \",6,0x2887A},\n        {\"nie   \",14,0x28886},\n        {\"nin   \",2,0x288A2},\n        {\"ning  \",10,0x288A6},\n        {\"niu   \",8,0x288BA},\n        {\"nong  \",6,0x288CA},\n        {\"nu    \",7,0x288D6},\n        {\"nuan  \",1,0x288E4},\n        {\"nue   \",3,0x288E6},\n        {\"nuo   \",9,0x288EC},\n        {\"nv    \",4,0x288FE},\n        {\"o     \",3,0x28906},\n        {\"ou    \",12,0x2890C},\n        {\"pa    \",12,0x28924},\n        {\"pai   \",10,0x2893C},\n        {\"pan   \",18,0x28950},\n        {\"pang  \",11,0x28974},\n        {\"pao   \",12,0x2898A},\n        {\"pei   \",15,0x289A2},\n        {\"pen   \",3,0x289C0},\n        {\"peng  \",18,0x289C6},\n        {\"pi    \",45,0x289EA},\n        {\"pian  \",13,0x28A44},\n        {\"piao  \",14,0x28A5E},\n        {\"pie   \",4,0x28A7A},\n        {\"pin   \",10,0x28A82},\n        {\"ping  \",14,0x28A96},\n        {\"po    \",20,0x28AB2},\n        {\"pou   \",3,0x28ADA},\n        {\"pu    \",28,0x28AE0},\n        {\"qi    \",74,0x28B18},\n        {\"qia   \",7,0x28BAC},\n        {\"qian  \",45,0x28BBA},\n        {\"qiang \",21,0x28C14},\n        {\"qiao  \",28,0x28C3E},\n        {\"qie   \",15,0x28C76},\n        {\"qin   \",24,0x28C94},\n        {\"qing  \",25,0x28CC4},\n        {\"qiong \",9,0x28CF6},\n        {\"qiu   \",25,0x28D08},\n        {\"qu    \",35,0x28D3A},\n        {\"quan  \",21,0x28D80},\n        {\"que   \",11,0x28DAA},\n        {\"qun   \",4,0x28DC0},\n        {\"ran   \",7,0x28DC8},\n        {\"rang  \",7,0x28DD6},\n        {\"rao   \",6,0x28DE4},\n        {\"re    \",4,0x28DF0},\n        {\"ren   \",17,0x28DF8},\n        {\"reng  \",2,0x28E1A},\n        {\"ri    \",1,0x28E1E},\n        {\"rong  \",15,0x28E20},\n        {\"rou   \",6,0x28E3E},\n        {\"ru    \",20,0x28E4A},\n        {\"ruan  \",3,0x28E72},\n        {\"rui   \",8,0x28E78},\n        {\"run   \",2,0x28E88},\n        {\"ruo   \",4,0x28E8C},\n        {\"sa    \",8,0x28E94},\n        {\"sai   \",6,0x28EA4},\n        {\"san   \",8,0x28EB0},\n        {\"sang  \",6,0x28EC0},\n        {\"sao   \",10,0x28ECC},\n        {\"se    \",7,0x28EE0},\n        {\"sen   \",1,0x28EEE},\n        {\"seng  \",1,0x28EF0},\n        {\"sha   \",20,0x28EF2},\n        {\"shai  \",4,0x28F1A},\n        {\"shan  \",37,0x28F22},\n        {\"shang \",14,0x28F6C},\n        {\"shao  \",19,0x28F88},\n        {\"she   \",20,0x28FAE},\n        {\"shen  \",29,0x28FD6},\n        {\"sheng \",17,0x29010},\n        {\"shi   \",68,0x29032},\n        {\"shou  \",14,0x290BA},\n        {\"shu   \",36,0x290D6},\n        {\"shua  \",3,0x2911E},\n        {\"shuai \",6,0x29124},\n        {\"shuan \",4,0x29130},\n        {\"shuang\",5,0x29138},\n        {\"shui  \",5,0x29142},\n        {\"shun  \",4,0x2914C},\n        {\"shuo  \",10,0x29154},\n        {\"si    \",35,0x29168},\n        {\"song  \",16,0x291AE},\n        {\"sou   \",15,0x291CE},\n        {\"su    \",22,0x291EC},\n        {\"suan  \",4,0x29218},\n        {\"sui   \",19,0x29220},\n        {\"sun   \",8,0x29246},\n        {\"suo   \",17,0x29256},\n        {\"ta    \",20,0x29278},\n        {\"tai   \",18,0x292A0},\n        {\"tan   \",27,0x292C4},\n        {\"tang  \",26,0x292FA},\n        {\"tao   \",18,0x2932E},\n        {\"te    \",5,0x29352},\n        {\"teng  \",5,0x2935C},\n        {\"ti    \",24,0x29366},\n        {\"tian  \",15,0x29396},\n        {\"tiao  \",16,0x293B4},\n        {\"tie   \",5,0x293D4},\n        {\"ting  \",18,0x293DE},\n        {\"tong  \",24,0x29402},\n        {\"tou   \",6,0x29432},\n        {\"tu    \",16,0x2943E},\n        {\"tuan  \",5,0x2945E},\n        {\"tui   \",8,0x29468},\n        {\"tun   \",9,0x29478},\n        {\"tuo   \",25,0x2948A},\n        {\"wa    \",11,0x294BC},\n        {\"wai   \",3,0x294D2},\n        {\"wan   \",29,0x294D8},\n        {\"wang  \",15,0x29512},\n        {\"wei   \",61,0x29530},\n        {\"wen   \",15,0x295AA},\n        {\"weng  \",5,0x295C8},\n        {\"wo    \",17,0x295D2},\n        {\"wu    \",56,0x295F4},\n        {\"xi    \",77,0x29664},\n        {\"xia   \",22,0x296FE},\n        {\"xian  \",48,0x2972A},\n        {\"xiang \",30,0x2978A},\n        {\"xiao  \",30,0x297C6},\n        {\"xie   \",42,0x29802},\n        {\"xin   \",18,0x29856},\n        {\"xing  \",22,0x2987A},\n        {\"xiong \",8,0x298A6},\n        {\"xiu   \",19,0x298B6},\n        {\"xu    \",35,0x298DC},\n        {\"xuan  \",27,0x29922},\n        {\"xue   \",11,0x29958},\n        {\"xun   \",32,0x2996E},\n        {\"ya    \",30,0x299AE},\n        {\"yan   \",67,0x299EA},\n        {\"yang  \",25,0x29A70},\n        {\"yao   \",35,0x29AA2},\n        {\"ye    \",24,0x29AE8},\n        {\"yi    \",109,0x29B18},\n        {\"yin   \",35,0x29BF2},\n        {\"ying  \",39,0x29C38},\n        {\"yo    \",3,0x29C86},\n        {\"yong  \",25,0x29C8C},\n        {\"you   \",42,0x29CBE},\n        {\"yu    \",95,0x29D12},\n        {\"yuan  \",35,0x29DD0},\n        {\"yue   \",18,0x29E16},\n        {\"yun   \",25,0x29E3A},\n        {\"za    \",8,0x29E6C},\n        {\"zai   \",10,0x29E7C},\n        {\"zan   \",11,0x29E90},\n        {\"zang  \",7,0x29EA6},\n        {\"zao   \",15,0x29EB4},\n        {\"ze    \",15,0x29ED2},\n        {\"zei   \",1,0x29EF0},\n        {\"zen   \",2,0x29EF2},\n        {\"zeng  \",9,0x29EF6},\n        {\"zha   \",28,0x29F08},\n        {\"zhai  \",12,0x29F40},\n        {\"zhan  \",21,0x29F58},\n        {\"zhang \",24,0x29F82},\n        {\"zhao  \",19,0x29FB2},\n        {\"zhe   \",20,0x29FD8},\n        {\"zhen  \",32,0x2A000},\n        {\"zheng \",23,0x2A040},\n        {\"zhi   \",81,0x2A06E},\n        {\"zhong \",17,0x2A110},\n        {\"zhou  \",24,0x2A132},\n        {\"zhu   \",50,0x2A162},\n        {\"zhua  \",3,0x2A1C6},\n        {\"zhuai \",2,0x2A1CC},\n        {\"zhuan \",11,0x2A1D0},\n        {\"zhuang\",11,0x2A1E6},\n        {\"zhui  \",10,0x2A1FC},\n        {\"zhun  \",5,0x2A210},\n        {\"zhuo  \",22,0x2A21A},\n        {\"zi    \",38,0x2A246},\n        {\"zong  \",11,0x2A292},\n        {\"zou   \",9,0x2A2A8},\n        {\"zu    \",11,0x2A2BA},\n        {\"zuan  \",6,0x2A2D0},\n        {\"zui   \",8,0x2A2DC},\n        {\"zun   \",5,0x2A2EC},\n        {\"zuo   \",19,0x2A2F6},\n\n\n\n\n};\n\n\nchar name[399][500]={\n        \"߹\",\n        \"\",\n        \"\",\n        \"\",\n        \"°ð\",\n        \"Ѱ˰ɰְΰհϰͰŰǰӰ԰Ȱаʰ̰Ұ\",\n        \"ٰװڰܰذݰ۲\",\n        \"߰\",\n        \"\",\n        \"ٱ\",\n        \"\",\n        \"\",\n        \"ı±Ű\",\n        \"ȱʱձDẔرܱƱϱ۱˱ɱڱͱұױٱαбӱֱݱѱ޵ݩذ\",\n        \"߱ޱ\",\n        \"\",\n        \"\",\n        \"\",\n        \"\",\n        \"زDzެ\",\n        \"߲\",\n        \"\",\n        \"²ŲIJƲòɲʲDzȲ˲\",\n        \"ϲвβҲѲͲ\",\n        \"زֲײղ\",\n        \"ݲٲܲ۲\",\n        \"߲\",\n        \"\",\n        \"\",\n        \"ɲ\",\n        \"˲٭\",\n        \"\",\n        \"\",\n        \"˴³\",\n        \"߳\",\n        \"óƳ³ijȳ\",\n        \"ɳʢųƳdz̳ʳϳͳѳҳγȳة\",\n        \"Գ߳ٳسճݳֳܳ޳ڳ۳ܯ߳\",\n        \"سӿ\",\n        \"ٱ\",\n        \"ۻء\",\n        \"\",\n        \"\",\n        \"\",\n        \"׵\",\n        \"ݻ\",\n        \"\",\n        \"δ˴ʴɴȴƴŴǴ̴ŴôͲ\",\n        \"ӴԴдҴϴ\",\n        \"\",\n        \"ִ״ش\",\n        \"ܴڴߥ\",\n        \"ߴݴ޴˥\",\n        \"\",\n        \"\",\n        \"\",\n        \"߾߰ܤ\",\n        \"ʯ\",\n        \"\",\n        \"߶\",\n        \"ĵصõµ\",\n        \"ȵƵ˵dzεɵʵ\",\n        \"صڵ׵͵еֵε۵ݵյܵ޵̵ĵѵϵҵԵۡڮصݶ\",\n        \"\",\n        \"ߵ\",\n        \"\",\n        \"ܦ\",\n        \"\",\n        \"\",\n        \"\",\n        \"\",\n        \"ȶɶ¶ǶƶĶöŶʶܶ\",\n        \"ζ̶϶˶Ͷ\",\n        \"ԶӶѶҶ\",\n        \"ֶٶ׶նض۶ܶڶݲ\",\n        \"޶Զȶ\",\n        \"Ŷﰢݭج\",\n        \"\",\n        \"٦\",\n        \"\",\n        \"ެ\",\n        \"ŷķ÷·\",\n        \"ǷɷʷѷηϷ˷ͷзƷ̷\",\n        \"ַݷҷ۷طܷ߷׷޷ӷٷԷշ\",\n        \"ٺۺ\",\n        \"\",\n        \"\",\n        \"򸸷󸳸иݳ߻ۮܽ\",\n        \"и¿٤\",\n        \"øĸǸŸƽؤ\",\n        \"ϸɸиҸ͸ʸθ̸˸Ӹߦ\",\n        \"ոָٸ۸׸ڸܸԸؿ\",\n        \"߸ݸ۬ھغ޻\",\n        \"￩ٺϸܪت\",\n        \"\",\n        \"ݢب\",\n        \"\",\n        \"\",\n        \"ڸ\",\n        \"ŹɹĹȹʹ¹ù˹̹͹ǹƼֹڬ\",\n        \"ҹιϹѹйڴ\",\n        \"ֹչ\",\n        \"عܹٹ۹ݹ߹޹ڹݸ\",\n        \"\",\n        \"Ȳ\",\n        \"\",\n        \"\",\n        \"Ϻ\",\n        \"Ⱥ\",\n        \"\",\n        \"ﺽ\",\n        \"úźƺºĺѸ޶\",\n        \"ͺȺϺӺ̺˺κǺɺغպֺк׺ʺѺҺڭ\",\n        \"ں\",\n        \"ܺݺ޺\",\n        \"ߺ޿\",\n        \"ڧޮްݦ\",\n        \"ܩ\",\n        \"Ϸ˺ͺ\",\n        \"\",\n        \"\",\n        \"û»ߧۨۼ\",\n        \"ƻŻλĻɻ˻ʻѻ̻Ȼǻлͻ\",\n        \"ػһӻԻٻڻݻ޻ջֻۻ߻׻仲ܻޥڶ\",\n        \"ڻ\",\n        \"ͻ޽߫\",\n        \"ȼǼƼļϵʻ¼ü˼̸ڵߴآܸ٥ު\",\n        \"ҼӼټۼܼ׼Ѽмμݼ޼ϼԼռؼѼ٤ۣ\",\n        \"潨߼齡dz𽢼뽤\",\n        \"ǿ\",\n        \"нŽǽ̽ϽɾУƽýνѽȽ½ͽĽܴٮ\",\n        \"ӽڽֽԽؽҽ׽ٽ߽ۿս۽ܽݽ޼ڦڵ\",\n        \"ﾡݣ\",\n        \"ݼ\",\n        \"\",\n        \";žƾɾþȾ˾¾Ǿʾľ̾\",\n        \"پ޾־߾Ӿ۾оվؾھܾϾѾҾݹ۾㳵׾Ҿڪ\",\n        \"Ȧ۲\",\n        \"Ǿާ\",\n        \"꿢\",\n        \"\",\n        \"\",\n        \"Ƕ٩ݨ\",\n        \"\",\n        \"\",\n        \"ȿɿ˿ÿƿſ̿οͿǿʿ¿Ŀ\",\n        \"Ͽпҿ\",\n        \"ӿ\",\n        \"տ׿ؿ\",\n        \"ڿۿٿޢߵ\",\n        \"޿ݿ߿ܥ\",\n        \"٨\",\n        \"ۦ\",\n        \"\",\n        \"ڿڲ\",\n        \"ظ\",\n        \"\",\n        \"\",\n        \"\",\n        \"\",\n        \"\",\n        \"ݹ\",\n        \"\",\n        \"߷\",\n        \"ڳ\",\n        \"ܨ\",\n        \"ٳٵ۪ݰت߿޼\",\n        \"\",\n        \"\",\n        \"ܮݹ\",\n        \"ޤ\",\n        \"\",\n        \"\",\n        \"۹\",\n        \"µ½\",\n        \"£¡¢Ū¤\",\n        \"¥§©ª¶¦¨\",\n        \"·¶¼¹½¯¬³±«­®µ°²¸¾º»´ޤ\",\n        \"\",\n        \"\",\n        \"\",\n        \"翩\",\n        \"¿\",\n        \"ĨĦ\",\n        \"۽ݤ\",\n        \"áܬ\",\n        \"æâäçãå\",\n        \"ëðñèìîòïóíêé\",\n        \"ô\",\n        \"ûÿúþøöùõü÷ýĭݮ\",\n        \"\",\n        \"åޫ\",\n        \"\",\n        \"\",\n        \"\",\n        \"ؿ\",\n        \"\",\n        \"ڤ\",\n        \"\",\n        \"ĥĨĩĤīûĪĬħģĦġĮİĭðįԺĢ\",\n        \"ijıIJٰ\",\n        \"ľĸĶĻĿĹIJģĺĵĴļĽķ\",\n        \"\",\n        \"ܵؾ٦\",\n        \"\",\n        \"߭\",\n        \"ث\",\n        \"ګ\",\n        \"\",\n        \"\",\n        \"\",\n        \"٣\",\n        \"ճإ\",\n        \"\",\n        \"\",\n        \"ؿ\",\n        \"\",\n        \"šŢ\",\n        \"ţŤŦť\",\n        \"ŪŨũŧٯ\",\n        \"ŭŬū\",\n        \"ů\",\n        \"Űű\",\n        \"ŲŵųŴ\",\n        \"Ů\",\n        \"Ŷ\",\n        \"żŻŷźŸŽŹک\",\n        \"ſžҰ\",\n        \"ٽ\",\n        \"ͷ\",\n        \"Ұ\",\n        \"\",\n        \"\",\n        \"\",\n        \"ܡ\",\n        \"ƤƥƨƢƧƣƦơƩاߨۯܱ\",\n        \"Ƭƪƭƫ\",\n        \"ƱƮƯưݳ\",\n        \"ƳƲ\",\n        \"ƷƶƸƴƵ\",\n        \"ƽƾƿƹƼƻƺٷ\",\n        \"Ȳӷ۶\",\n        \"\",\n        \"׸ֱձ?\",\n        \"ݽޭܻؽٹ\",\n        \"ǡǢ\",\n        \"ǰǮǧǣdzǩǷǦǶǥǨǯǬǴǫDZǸǤDzǭǵǪٻݡܷ\",\n        \"ǿǹǽǻǺǼǾ\",\n        \"¿ȸڽ\",\n        \"ۧ٤\",\n        \"\",\n        \"\",\n        \"\",\n        \"ٴ\",\n        \"ȥȡȢȤȣ޾ޡ۾ڰ\",\n        \"ȫȨȰȦȭȮȪȯȧȬȩڹ\",\n        \"ȴȱȷȸȳȵȲȶ\",\n        \"Ⱥȹ\",\n        \"ȾȼȻȽ\",\n        \"ȿ\",\n        \"\",\n        \"\",\n        \"\",\n        \"\",\n        \"\",\n        \"\",\n        \"\",\n        \"޸\",\n        \"\",\n        \"ި\",\n        \"\",\n        \"ټ\",\n        \"ئ\",\n        \"˼\",\n        \"ɢɡ\",\n        \"ɣɥɤ\",\n        \"ɨɩɦɧܣ\",\n        \"ɫɬɪ\",\n        \"ɭ\",\n        \"ɮ\",\n        \"ɱɳɶɴɵɰɲɯɷɼ\",\n        \"ɹɸɫ\",\n        \"ɽɼɾɿɺդɻ۷ڨ\",\n        \"\",\n        \"ۿ\",\n        \"\",\n        \"ʲݷڷ\",\n        \"ʡʣʤʢʥ\",\n        \"ʹʮʱʯʦʷʽʶʭʸʰʺʻʼʾʿʲֳʧʨʳʴʵʩʪʫʬݪ߱\",\n        \"\",\n        \"ˡ\",\n        \"ˢˣ\",\n        \"ˤ˦˧˥\",\n        \"˨˩\",\n        \"˫˪ˬ\",\n        \"ˮ˭˯˰˵\",\n        \"˳˱˲˴\",\n        \"˵˶˸˷\",\n        \"˿˺˽˻˼˾˹ʳŲٹ\",\n        \"ݿڡ\",\n        \"޴\",\n        \"\",\n        \"\",\n        \"ݴ\",\n        \"ݥ\",\n        \"ɯ\",\n        \"̡̢̤̣\",\n        \"̧̨̫̬̥̦̩̪̭߾޷ۢ\",\n        \"̸̶̵̷̴̲̼̯̰̳̺̹̱̮̻̾̽̿۰\",\n        \"\",\n        \"ػ߶\",\n        \"߯\",\n        \"\",\n        \"\",\n        \"\",\n        \"٬\",\n        \"\",\n        \"ͣͦͤͧͥ͢͡\",\n        \"ͬͨʹͭͰͲͱͳͯͮͩͫͪ١\",\n        \"ͷ͵͸Ͷ\",\n        \"ͼͿͺͻͽ͹;ܢݱ\",\n        \"\",\n        \"߯\",\n        \"ζ\",\n        \"ر٢\",\n        \"ݰ\",\n        \"\",\n        \"ݸܹ\",\n        \"â\",\n        \"ΪλδΧιθ΢ζβαΰΣΥίκΨάηΩΤΡενξΫγοΦήέμޱ\",\n        \"\",\n        \"޳\",\n        \"ݫ\",\n        \"أ\",\n        \"ϴϸϷϵϲϯϡϪϨϥϢϮϧϰϦϤϣϭϱϳϩ϶ϫϬۭݾ\",\n        \"ϿϺϹϼϻϽϾ\",\n        \"ϳ޺ݲ\",\n        \"ήܼ\",\n        \"СЦЧФТХУ\",\n        \"дЩЬЪбѪлжЮмзкийШаЭегЫЯвҶߢޯ\",\n        \"онпѰضݷܰ\",\n        \"ʡߩ\",\n        \"ܺ\",\n        \"\",\n        \"ޣڼ\",\n        \"ѡѤѣѢȯ\",\n        \"ѧѩѪѥѨѦ\",\n        \"ѰѶѬѵѭѳѮѲѸѱѴѷѫѯަ޹ۨ\",\n        \"ѽѹѺѿѼѾѻ\",\n        \"ٲ۱۳Ǧܾ\",\n        \"\",\n        \"ҪҡҩҧҤҨҥңҦҫҢԿزسߺűԼ\",\n        \"ҲҹҵҰҶүҳҺҴҸұҭҮҷҬа\",\n        \"һҽʳҼҾҿضβܲڱ٫߮޲߽\",\n        \"ӡܧ۴ط\",\n        \"ӦӲӰӪӭӳӬӮӥӢӱӨӯӤӣӧӫөݺ۫\",\n        \"Ӵ\",\n        \"ӿӵӼӺӽӾӶӻӸӹӷٸܭ\",\n        \"٧ݬݯݵ\",\n        \"ξԡԢԣԤԥԦεخٶع\",\n        \"ԶԱԪԺԲԭԸ԰ԮԳԹԩԴԵԬԨԷԫԧԯܾܫ\",\n        \"ԽԼԾԻ˵Կ\",\n        \"Ա۩ܿ\",\n        \"զ\",\n        \"\",\n        \"\",\n        \"߲\",\n        \"\",\n        \"զ\",\n        \"\",\n        \"\",\n        \"\",\n        \"ըբգեէթա߸դզ\",\n        \"ժխծիկլ\",\n        \"վռսյմճձչջղպտնշոհ\",\n        \"³۵\",\n        \"צ׳سگ\",\n        \"ߡ\",\n        \"\",\n        \"֤֢֣֡ں綡\",\n        \"ְֱֲֳִֵֶַָֹֺֻּֽ֪֧֥֦֭֮֨֩֫֬֯־ֿʶۤشμ\",\n        \"ڣ\",\n        \"ݧ\",\n        \"סעףפ٪ۥ\",\n        \"ץצ\",\n        \"קת\",\n        \"תרש׬׫׭\",\n        \"װײׯ׳׮״ױ\",\n        \"׷׹׺׶׸׵\",\n        \"׼׻\",\n        \"׽׾׿ߪپ\",\n        \"֨\",\n        \"\",\n        \"۸\",\n        \"\",\n        \"׬߬\",\n        \"Ѿީ\",\n        \"ߤ\",\n        \"\",\n\n};"
  },
  {
    "path": "输入法/PINYIN.h",
    "content": "//\n// Created by RUPC on 2024/2/9.\n//\n\n#ifndef UNTITLED24_PINYIN_H\n#define UNTITLED24_PINYIN_H\ntypedef unsigned int uint32_t;\ntypedef unsigned char uint8_t;\ntypedef int int32_t;\ntypedef unsigned short uint16_t;\n struct PINYIN_T\n{\n   const  char pinyin[7];\n    uint8_t num;\n    uint32_t add;\n};\nextern struct PINYIN_T pin[399] ;\nextern char name[399][500];\n#endif //UNTITLED24_PINYIN_H\n"
  },
  {
    "path": "输入法/font.c",
    "content": "/* Copyright 2023 Dual Tachyon\n * https://github.com/DualTachyon\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http://www.apache.org/licenses/LICENSE-2.0\n *\n *     Unless required by applicable law or agreed to in writing, software\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n *     See the License for the specific language governing permissions and\n *     limitations under the License.\n */\n\n#include \"font.h\"\n\nstruct hah pinyin_all[214] = {\n        {200000, 1, {{\"a     \"},}},\n        {220000, 2, {{\"ba    \"}, {\"ca    \"},}},\n        {224000, 2, {{\"bai   \"}, {\"cai   \"},}},\n        {226000, 4, {{\"ban   \"}, {\"bao   \"}, {\"can   \"}, {\"cao   \"},}},\n        {226400, 2, {{\"bang  \"}, {\"cang  \"},}},\n        {230000, 1, {{\"ce    \"},}},\n        {234000, 1, {{\"bei   \"},}},\n        {236000, 2, {{\"ben   \"}, {\"cen   \"},}},\n        {236400, 2, {{\"beng  \"}, {\"ceng  \"},}},\n        {240000, 3, {{\"ai    \"}, {\"bi    \"}, {\"ci    \"},}},\n        {242000, 1, {{\"cha   \"},}},\n        {242400, 1, {{\"chai  \"},}},\n        {242600, 4, {{\"bian  \"}, {\"biao  \"}, {\"chan  \"}, {\"chao  \"},}},\n        {242640, 1, {{\"chang \"},}},\n        {243000, 2, {{\"bie   \"}, {\"che   \"},}},\n        {243600, 1, {{\"chen  \"},}},\n        {243640, 1, {{\"cheng \"},}},\n        {244000, 1, {{\"chi   \"},}},\n        {246000, 1, {{\"bin   \"},}},\n        {246400, 1, {{\"bing  \"},}},\n        {246640, 1, {{\"chong \"},}},\n        {246800, 1, {{\"chou  \"},}},\n        {248000, 1, {{\"chu   \"},}},\n        {248240, 1, {{\"chuai \"},}},\n        {248260, 1, {{\"chuan \"},}},\n        {248264, 1, {{\"chuang\"},}},\n        {248400, 1, {{\"chui  \"},}},\n        {248600, 2, {{\"chun  \"}, {\"chuo  \"},}},\n        {260000, 3, {{\"an    \"}, {\"ao    \"}, {\"bo    \"},}},\n        {264000, 1, {{\"ang   \"},}},\n        {266400, 1, {{\"cong  \"},}},\n        {268000, 1, {{\"cou   \"},}},\n        {280000, 2, {{\"bu    \"}, {\"cu    \"},}},\n        {282600, 1, {{\"cuan  \"},}},\n        {284000, 1, {{\"cui   \"},}},\n        {286000, 2, {{\"cun   \"}, {\"cuo   \"},}},\n        {300000, 1, {{\"e     \"},}},\n        {320000, 2, {{\"da    \"}, {\"fa    \"},}},\n        {324000, 1, {{\"dai   \"},}},\n        {326000, 3, {{\"dan   \"}, {\"dao   \"}, {\"fan   \"},}},\n        {326400, 2, {{\"dang  \"}, {\"fang  \"},}},\n        {330000, 1, {{\"de    \"},}},\n        {334000, 1, {{\"fei   \"},}},\n        {336000, 1, {{\"fen   \"},}},\n        {336400, 2, {{\"deng  \"}, {\"feng  \"},}},\n        {340000, 1, {{\"di    \"},}},\n        {342000, 1, {{\"dia   \"},}},\n        {342600, 2, {{\"dian  \"}, {\"diao  \"},}},\n        {343000, 1, {{\"die   \"},}},\n        {346400, 1, {{\"ding  \"},}},\n        {348000, 1, {{\"diu   \"},}},\n        {360000, 2, {{\"en    \"}, {\"fo    \"},}},\n        {366400, 1, {{\"dong  \"},}},\n        {368000, 2, {{\"dou   \"}, {\"fou   \"},}},\n        {370000, 1, {{\"er    \"},}},\n        {380000, 2, {{\"du    \"}, {\"fu    \"},}},\n        {382600, 1, {{\"duan  \"},}},\n        {384000, 1, {{\"dui   \"},}},\n        {386000, 2, {{\"dun   \"}, {\"duo   \"},}},\n        {420000, 2, {{\"ga    \"}, {\"ha    \"},}},\n        {424000, 2, {{\"gai   \"}, {\"hai   \"},}},\n        {426000, 4, {{\"gan   \"}, {\"gao   \"}, {\"han   \"}, {\"hao   \"},}},\n        {426400, 2, {{\"gang  \"}, {\"hang  \"},}},\n        {430000, 2, {{\"ge    \"}, {\"he    \"},}},\n        {434000, 2, {{\"gei   \"}, {\"hei   \"},}},\n        {436000, 2, {{\"gen   \"}, {\"hen   \"},}},\n        {436400, 2, {{\"geng  \"}, {\"heng  \"},}},\n        {466400, 2, {{\"gong  \"}, {\"hong  \"},}},\n        {468000, 2, {{\"gou   \"}, {\"hou   \"},}},\n        {480000, 2, {{\"gu    \"}, {\"hu    \"},}},\n        {482000, 2, {{\"gua   \"}, {\"hua   \"},}},\n        {482400, 2, {{\"guai  \"}, {\"huai  \"},}},\n        {482600, 2, {{\"guan  \"}, {\"huan  \"},}},\n        {482640, 2, {{\"guang \"}, {\"huang \"},}},\n        {484000, 2, {{\"gui   \"}, {\"hui   \"},}},\n        {486000, 4, {{\"gun   \"}, {\"guo   \"}, {\"hun   \"}, {\"huo   \"},}},\n        {520000, 2, {{\"ka    \"}, {\"la    \"},}},\n        {524000, 2, {{\"kai   \"}, {\"lai   \"},}},\n        {526000, 4, {{\"kan   \"}, {\"kao   \"}, {\"lan   \"}, {\"lao   \"},}},\n        {526400, 2, {{\"kang  \"}, {\"lang  \"},}},\n        {530000, 2, {{\"ke    \"}, {\"le    \"},}},\n        {534000, 1, {{\"lei   \"},}},\n        {536000, 1, {{\"ken   \"},}},\n        {536400, 2, {{\"keng  \"}, {\"leng  \"},}},\n        {540000, 2, {{\"ji    \"}, {\"li    \"},}},\n        {542000, 2, {{\"jia   \"}, {\"lia   \"},}},\n        {542600, 4, {{\"jian  \"}, {\"jiao  \"}, {\"lian  \"}, {\"liao  \"},}},\n        {542640, 2, {{\"jiang \"}, {\"liang \"},}},\n        {543000, 2, {{\"jie   \"}, {\"lie   \"},}},\n        {546000, 2, {{\"jin   \"}, {\"lin   \"},}},\n        {546400, 2, {{\"jing  \"}, {\"ling  \"},}},\n        {546640, 1, {{\"jiong \"},}},\n        {548000, 2, {{\"jiu   \"}, {\"liu   \"},}},\n        {566400, 2, {{\"kong  \"}, {\"long  \"},}},\n        {568000, 2, {{\"kou   \"}, {\"lou   \"},}},\n        {580000, 4, {{\"ju    \"}, {\"ku    \"}, {\"lu    \"}, {\"lv    \"},}},\n        {582000, 1, {{\"kua   \"},}},\n        {582400, 1, {{\"kuai  \"},}},\n        {582600, 3, {{\"juan  \"}, {\"kuan  \"}, {\"luan  \"},}},\n        {582640, 1, {{\"kuang \"},}},\n        {583000, 2, {{\"jue   \"}, {\"lue   \"},}},\n        {584000, 1, {{\"kui   \"},}},\n        {586000, 5, {{\"jun   \"}, {\"kun   \"}, {\"kuo   \"}, {\"lun   \"}, {\"luo   \"},}},\n        {600000, 1, {{\"o     \"},}},\n        {620000, 2, {{\"ma    \"}, {\"na    \"},}},\n        {624000, 2, {{\"mai   \"}, {\"nai   \"},}},\n        {626000, 4, {{\"man   \"}, {\"mao   \"}, {\"nan   \"}, {\"nao   \"},}},\n        {626400, 2, {{\"mang  \"}, {\"nang  \"},}},\n        {630000, 2, {{\"me    \"}, {\"ne    \"},}},\n        {634000, 2, {{\"mei   \"}, {\"nei   \"},}},\n        {636000, 2, {{\"men   \"}, {\"nen   \"},}},\n        {636400, 2, {{\"meng  \"}, {\"neng  \"},}},\n        {640000, 2, {{\"mi    \"}, {\"ni    \"},}},\n        {642600, 4, {{\"mian  \"}, {\"miao  \"}, {\"nian  \"}, {\"niao  \"},}},\n        {642640, 1, {{\"niang \"},}},\n        {643000, 2, {{\"mie   \"}, {\"nie   \"},}},\n        {646000, 2, {{\"min   \"}, {\"nin   \"},}},\n        {646400, 2, {{\"ming  \"}, {\"ning  \"},}},\n        {648000, 2, {{\"miu   \"}, {\"niu   \"},}},\n        {660000, 1, {{\"mo    \"},}},\n        {666400, 1, {{\"nong  \"},}},\n        {668000, 1, {{\"mou   \"},}},\n        {680000, 4, {{\"mu    \"}, {\"nu    \"}, {\"nv    \"}, {\"ou    \"},}},\n        {682600, 1, {{\"nuan  \"},}},\n        {683000, 1, {{\"nue   \"},}},\n        {686000, 1, {{\"nuo   \"},}},\n        {720000, 2, {{\"pa    \"}, {\"sa    \"},}},\n        {724000, 2, {{\"pai   \"}, {\"sai   \"},}},\n        {726000, 6, {{\"pan   \"}, {\"pao   \"}, {\"ran   \"}, {\"rao   \"}, {\"san   \"}, {\"sao   \"},}},\n        {726400, 3, {{\"pang  \"}, {\"rang  \"}, {\"sang  \"},}},\n        {730000, 2, {{\"re    \"}, {\"se    \"},}},\n        {734000, 1, {{\"pei   \"},}},\n        {736000, 3, {{\"pen   \"}, {\"ren   \"}, {\"sen   \"},}},\n        {736400, 3, {{\"peng  \"}, {\"reng  \"}, {\"seng  \"},}},\n        {740000, 4, {{\"pi    \"}, {\"qi    \"}, {\"ri    \"}, {\"si    \"},}},\n        {742000, 2, {{\"qia   \"}, {\"sha   \"},}},\n        {742400, 1, {{\"shai  \"},}},\n        {742600, 6, {{\"pian  \"}, {\"piao  \"}, {\"qian  \"}, {\"qiao  \"}, {\"shan  \"}, {\"shao  \"},}},\n        {742640, 2, {{\"qiang \"}, {\"shang \"},}},\n        {743000, 3, {{\"pie   \"}, {\"qie   \"}, {\"she   \"},}},\n        {743600, 1, {{\"shen  \"},}},\n        {743640, 1, {{\"sheng \"},}},\n        {744000, 1, {{\"shi   \"},}},\n        {746000, 2, {{\"pin   \"}, {\"qin   \"},}},\n        {746400, 2, {{\"ping  \"}, {\"qing  \"},}},\n        {746640, 1, {{\"qiong \"},}},\n        {746800, 1, {{\"shou  \"},}},\n        {748000, 2, {{\"qiu   \"}, {\"shu   \"},}},\n        {748200, 1, {{\"shua  \"},}},\n        {748240, 1, {{\"shuai \"},}},\n        {748260, 1, {{\"shuan \"},}},\n        {748264, 1, {{\"shuang\"},}},\n        {748400, 1, {{\"shui  \"},}},\n        {748600, 2, {{\"shun  \"}, {\"shuo  \"},}},\n        {760000, 1, {{\"po    \"},}},\n        {766400, 2, {{\"rong  \"}, {\"song  \"},}},\n        {768000, 3, {{\"pou   \"}, {\"rou   \"}, {\"sou   \"},}},\n        {780000, 4, {{\"pu    \"}, {\"qu    \"}, {\"ru    \"}, {\"su    \"},}},\n        {782600, 3, {{\"quan  \"}, {\"ruan  \"}, {\"suan  \"},}},\n        {783000, 1, {{\"que   \"},}},\n        {784000, 2, {{\"rui   \"}, {\"sui   \"},}},\n        {786000, 5, {{\"qun   \"}, {\"run   \"}, {\"ruo   \"}, {\"sun   \"}, {\"suo   \"},}},\n        {820000, 1, {{\"ta    \"},}},\n        {824000, 1, {{\"tai   \"},}},\n        {826000, 2, {{\"tan   \"}, {\"tao   \"},}},\n        {826400, 1, {{\"tang  \"},}},\n        {830000, 1, {{\"te    \"},}},\n        {836400, 1, {{\"teng  \"},}},\n        {840000, 1, {{\"ti    \"},}},\n        {842600, 2, {{\"tian  \"}, {\"tiao  \"},}},\n        {843000, 1, {{\"tie   \"},}},\n        {846400, 1, {{\"ting  \"},}},\n        {866400, 1, {{\"tong  \"},}},\n        {868000, 1, {{\"tou   \"},}},\n        {880000, 1, {{\"tu    \"},}},\n        {882600, 1, {{\"tuan  \"},}},\n        {884000, 1, {{\"tui   \"},}},\n        {886000, 2, {{\"tun   \"}, {\"tuo   \"},}},\n        {920000, 3, {{\"wa    \"}, {\"ya    \"}, {\"za    \"},}},\n        {924000, 2, {{\"wai   \"}, {\"zai   \"},}},\n        {926000, 5, {{\"wan   \"}, {\"yan   \"}, {\"yao   \"}, {\"zan   \"}, {\"zao   \"},}},\n        {926400, 3, {{\"wang  \"}, {\"yang  \"}, {\"zang  \"},}},\n        {930000, 2, {{\"ye    \"}, {\"ze    \"},}},\n        {934000, 2, {{\"wei   \"}, {\"zei   \"},}},\n        {936000, 2, {{\"wen   \"}, {\"zen   \"},}},\n        {936400, 2, {{\"weng  \"}, {\"zeng  \"},}},\n        {940000, 3, {{\"xi    \"}, {\"yi    \"}, {\"zi    \"},}},\n        {942000, 2, {{\"xia   \"}, {\"zha   \"},}},\n        {942400, 1, {{\"zhai  \"},}},\n        {942600, 4, {{\"xian  \"}, {\"xiao  \"}, {\"zhan  \"}, {\"zhao  \"},}},\n        {942640, 2, {{\"xiang \"}, {\"zhang \"},}},\n        {943000, 2, {{\"xie   \"}, {\"zhe   \"},}},\n        {943600, 1, {{\"zhen  \"},}},\n        {943640, 1, {{\"zheng \"},}},\n        {944000, 1, {{\"zhi   \"},}},\n        {946000, 2, {{\"xin   \"}, {\"yin   \"},}},\n        {946400, 2, {{\"xing  \"}, {\"ying  \"},}},\n        {946640, 2, {{\"xiong \"}, {\"zhong \"},}},\n        {946800, 1, {{\"zhou  \"},}},\n        {948000, 2, {{\"xiu   \"}, {\"zhu   \"},}},\n        {948200, 1, {{\"zhua  \"},}},\n        {948240, 1, {{\"zhuai \"},}},\n        {948260, 1, {{\"zhuan \"},}},\n        {948264, 1, {{\"zhuang\"},}},\n        {948400, 1, {{\"zhui  \"},}},\n        {948600, 2, {{\"zhun  \"}, {\"zhuo  \"},}},\n        {960000, 2, {{\"wo    \"}, {\"yo    \"},}},\n        {966400, 2, {{\"yong  \"}, {\"zong  \"},}},\n        {968000, 2, {{\"you   \"}, {\"zou   \"},}},\n        {980000, 4, {{\"wu    \"}, {\"xu    \"}, {\"yu    \"}, {\"zu    \"},}},\n        {982600, 3, {{\"xuan  \"}, {\"yuan  \"}, {\"zuan  \"},}},\n        {983000, 2, {{\"xue   \"}, {\"yue   \"},}},\n        {984000, 1, {{\"zui   \"},}},\n        {986000, 4, {{\"xun   \"}, {\"yun   \"}, {\"zun   \"}, {\"zuo   \"},}},\n\n\n};"
  },
  {
    "path": "输入法/font.h",
    "content": "/* Copyright 2023 Dual Tachyon\n * https://github.com/DualTachyon\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     http://www.apache.org/licenses/LICENSE-2.0\n *\n *     Unless required by applicable law or agreed to in writing, software\n *     distributed under the License is distributed on an \"AS IS\" BASIS,\n *     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n *     See the License for the specific language governing permissions and\n *     limitations under the License.\n */\n\n#ifndef FONT_H\n#define FONT_H\n#include \"stdbool.h\"\n#include <stdint.h>\n\ntypedef struct hah{\n    int code;\n    int num;\n    char str[6][7];\n};\n\nextern const uint8_t gFontBigDigits[11][20/*20*/];\nextern const uint8_t gFont3x5[96][3];\nextern const uint8_t gFontSmall[95 - 1][6];\nextern struct hah pinyin_all[214];\n\n\n#endif\n\n"
  },
  {
    "path": "输入法/main.cpp",
    "content": "#include \"bits/stdc++.h\"\n#include \"PINYIN.h\"\n#include \"font.h\"\n\nusing namespace std;\ntypedef unsigned int uint32_t;\ntypedef unsigned char uint8_t;\ntypedef int int32_t;\ntypedef unsigned short uint16_t;\n\n\nFILE *file = NULL;\n\nvoid openFile(const char *filename) {\n    // Զƶдģʽļ\n    file = fopen(filename, \"wb\");\n    if (file == NULL) {\n        printf(\"OPEN FAILED %s\\n\", filename);\n        return;\n    }\n}\n\nvoid closeFile() {\n    // رļ\n    if (file != NULL) {\n        fclose(file);\n    }\n}\n\nvoid writeUint8ToFile(int position, uint8_t value) {\n    // ļǷѴ\n    if (file == NULL) {\n        printf(\"NOT OPEN\\n\");\n        return;\n    }\n\n    // ƶָλ\n    fseek(file, position, SEEK_SET);\n\n    // дuint8ֵ\n    fwrite(&value, sizeof(uint8_t), 1, file);\n\n//    printf(\"WRITE  %d TO %d\\n\", value, position);\n}\n\nint formatInt(int number) {\n    int formatted = number;\n    int length = 0;\n    int temp = number;\n\n    // λ\n    while (temp != 0) {\n        temp /= 10;\n        length++;\n    }\n    // λ6λں油0\n    if (length < 6) {\n        for (int i = 0; i < 6 - length; ++i) {\n            formatted *= 10;\n        }\n    }\n    return formatted;\n}\n\nchar num_excel[8][5] = {\n        \"abc\", \"def\", \"ghi\", \"jkl\", \"mno\", \"pqrs\", \"tuv\", \"wxyz\"\n};\n\nint get_num(const char *a) {\n    int num = 0;\n    int bin = 100000;\n    for (int j = 0; j < strlen(a); j++) {\n        int now_num = 0;\n        for (int i = 0; i < 8; ++i) {\n            for (int k = 0; k < strlen(num_excel[i]); ++k) {\n                if (num_excel[i][k] == a[j]) {\n                    now_num = i + 2;\n                    goto end_loop;\n                }\n            }\n        }\n        end_loop:\n        num += bin * now_num;\n        bin /= 10;\n    }\n    return num;\n}\nbool judge_belong(int a,int b)\n{\n    for (int i = 100000; i >=1 ; i/=10) {\n        if(a/i==0)break;\n        if(a/i!=b/i)return 0;\n        a=a-a/i*i;\n        b=b-b/i*i;\n\n    }\n    return 1;\n}\n\nint binarySearch(int target, int *not_found) {\n    int left = 0;\n    int right = 213;\n    *not_found = 1; // ʼ趨δҵ\n\n    while (left <= right) {\n        int mid = left + (right - left) / 2;\n        int mid_num = pinyin_all[mid].code;\n\n        if (mid_num == target) {\n            *not_found = 0; // ҵ\n            return mid;\n        } else if (target < mid_num) {\n            right = mid - 1;\n        } else {\n            left = mid + 1;\n        }\n    }\n\n    // ҲĿֵرĿֵһֵ\n    if (left <= 213) {\n        int mid_num = pinyin_all[left].code;\n        if (judge_belong(target, mid_num)) {\n\n            return left;\n        }\n\n    }\n\n    return -1;\n}\n\n\nint main() {\n    printf(\"%d\\n\", judge_belong(666000, 666400));\n\n    return 0;\n        FILE *file_printf;\n    file_printf = fopen(\"output.txt\", \"wb\"); // ļԹд\n\n    if (file_printf == NULL) {\n        printf(\"޷ļ\\n\");\n        return 1;\n    }\n\n\n    const char filename[] = \"../PINYIN.BIN\";\n    // ļ\n    openFile(filename);\n    char num_excel[1000000] = {0};\n    int max_num = 0;\n    for (int i = 0; i < 399; ++i) {\n        num_excel[get_num(pin[i].pinyin)]++;\n        if (num_excel[get_num(pin[i].pinyin)] > max_num)max_num = num_excel[get_num(pin[i].pinyin)];\n    }\n    fprintf(file_printf, \"%d 55555555555\\n\", max_num);\n    int youxiao_cnt = 0;\n    for (int i = 0; i < 1000000; ++i) {\n\n        if (num_excel[i]) {\n            //\n            writeUint8ToFile(youxiao_cnt * 128, (i & 0xff));\n            writeUint8ToFile(youxiao_cnt * 128 + 1, (i & 0xff00) >> 8);\n            writeUint8ToFile(youxiao_cnt * 128 + 2, (i & 0xff0000) >> 16);\n            writeUint8ToFile(youxiao_cnt * 128 + 3, (i & 0xff000000) >> 24);\n            //ƴ\n            writeUint8ToFile(youxiao_cnt * 128 + 4, num_excel[i]);\n            int pinyin_cnt = 1;\n            fprintf(file_printf, \"{%d,%d,{\", i, num_excel[i]);\n\n            for (int j = 0; j < 399; ++j) {\n                if (get_num(pin[j].pinyin) == i) //ƴ\n                {\n                    fprintf(file_printf, \"{\\\"%6s\\\"},\", pin[j].pinyin);\n\n                    //дƴ\n                    for (int k = 0; k < 6; k++)\n                        writeUint8ToFile(youxiao_cnt * 128 + pinyin_cnt * 16 + k, pin[j].pinyin[k]);\n                    //д\n                    writeUint8ToFile(youxiao_cnt * 128 + pinyin_cnt * 16 + 6, pin[j].num);\n                    //дַ\n                    writeUint8ToFile(youxiao_cnt * 128 + pinyin_cnt * 16 + 7, (pin[j].add & 0xff));\n                    writeUint8ToFile(youxiao_cnt * 128 + pinyin_cnt * 16 + 8, (pin[j].add & 0xff00) >> 8);\n                    writeUint8ToFile(youxiao_cnt * 128 + pinyin_cnt * 16 + 9, (pin[j].add & 0xff0000) >> 16);\n                    writeUint8ToFile(youxiao_cnt * 128 + pinyin_cnt * 16 + 10, (pin[j].add & 0xff000000) >> 24);\n                    pinyin_cnt++;\n                }\n            }\n            fprintf(file_printf, \"}},\\n\", i);\n\n            youxiao_cnt++;\n        }\n    }\n    for (int i = 0; i < 399; i++) {\n        for (int j = 0; j < strlen(name[i]); ++j) {\n            writeUint8ToFile(pin[i].add - 0x20000 + j, name[i][j]);\n\n        }\n    }\n    writeUint8ToFile(0xa31f, 0);\n\n    closeFile();\n    fclose(file_printf); // رļ\n\n\n\n\n    while (1) {\n        int input;\n        scanf(\"%d\", &input);\n        int flag;\n        int look = binarySearch(formatInt(input), &flag);\n        if (look != -1) {\n            if (flag) { //ûҵ\n                int cnt=0;\n                for (int j = look; j<214 ; j++) {\n\n                    if(judge_belong(formatInt(input),pinyin_all[j].code))\n                     {\n                         printf(\"%d %d\\n\",look,j);\n                        for (int i = 0; i < pinyin_all[j].num; ++i) {\n                            cnt++;\n                            printf(\"%d :%s \", cnt, pinyin_all[j].str[i]);\n                        }\n                        printf(\"\\n\");\n                    }else break;\n                }\n\n            } else {\n//                printf(\"%d:\\n\", pinyin_all[look].num);\n                for (int i = 0; i < pinyin_all[look].num; ++i) {\n                    printf(\"%d :%s \", i, pinyin_all[look].str[i]);\n                }\n                printf(\"\\n\");\n            }\n        }\n    }\n    return 0;\n\n}\n"
  }
]